From 08d5efe29da7e893582277bd9495a67acc7a5845 Mon Sep 17 00:00:00 2001 From: Evgeny Date: Fri, 14 Jul 2017 14:59:42 -0500 Subject: [PATCH] moving hsa-amd-aqlprofile to ssh://gerritgit/hsa/ec/aqlprofile Change-Id: Ic42752ca41f877db02aa5a5d8d617cd67cce8956 --- runtime/hsa-amd-aqlprofile/CMakeLists.txt | 30 - runtime/hsa-amd-aqlprofile/Readme.txt | 44 - .../cmake_modules/exportToolFlags.cmake | 66 - .../cmake_modules/validateBldEnv.cmake | 52 - .../doc/HSA_ven_amd_aqlprofile_api.pptx | Bin 1114397 -> 0 bytes .../HSA_ven_amd_aqlprofile_api_v1_2_0.docx | Bin 85703 -> 0 bytes .../gfxip/gfx8/features_bonaire.h | 1594 - .../gfxip/gfx8/features_hainan.h | 954 - .../gfxip/gfx8/features_oland.h | 979 - .../gfxip/gfx8/features_pitcairn.h | 1359 - .../gfxip/gfx8/features_tahiti.h | 1261 - .../gfxip/gfx8/features_tiran.h | 1640 - .../gfxip/gfx8/features_verde.h | 962 - .../gfxip/gfx8/gfx8_utils.h | 98 - .../gfxip/gfx8/si_ci_vi_merged_enum.h | 10081 --- .../gfxip/gfx8/si_ci_vi_merged_mask.h | 48849 ------------ .../gfxip/gfx8/si_ci_vi_merged_offset.h | 19182 ----- .../gfx8/si_ci_vi_merged_pm4_it_opcodes.h | 141 - .../gfxip/gfx8/si_ci_vi_merged_pm4cmds.h | 79 - .../gfxip/gfx8/si_ci_vi_merged_shift.h | 48643 ------------ .../gfxip/gfx8/si_ci_vi_merged_sq_reg.h | 15476 ---- .../gfxip/gfx8/si_ci_vi_merged_sq_uc_reg.h | 4485 -- .../gfxip/gfx8/si_ci_vi_merged_typedef.h | 12452 --- .../gfxip/gfx8/si_pm4defs.h | 2408 - .../gfxip/gfx9/f32_ce_pm4_packets_vg10.h | 676 - .../gfxip/gfx9/f32_me_pm4_packets_vg10.h | 2171 - .../gfxip/gfx9/f32_mec_aql_packets_vg10.h | 267 - .../gfxip/gfx9/f32_mec_cmn_structs_vg10.h | 682 - .../gfxip/gfx9/f32_mec_pm4_packets_vg10.h | 1724 - .../gfxip/gfx9/f32_mes_pm4_packets_vg10.h | 461 - .../gfxip/gfx9/f32_pfp_pm4_packets_vg10.h | 2220 - .../hsa-amd-aqlprofile/gfxip/gfx9/gfx9_enum.h | 11695 --- .../hsa-amd-aqlprofile/gfxip/gfx9/gfx9_mask.h | 63332 --------------- .../gfxip/gfx9/gfx9_offset.h | 17412 ----- .../gfxip/gfx9/gfx9_pm4_it_opcodes.h | 149 - .../gfxip/gfx9/gfx9_pm4defs.h | 30 - .../gfxip/gfx9/gfx9_shift.h | 63386 ---------------- .../gfxip/gfx9/gfx9_typedef.h | 10759 --- .../gfxip/gfx9/gfx9_utils.h | 141 - runtime/hsa-amd-aqlprofile/src/CMakeLists.txt | 70 - .../src/commandwriter/CMakeLists.txt | 10 - .../src/commandwriter/cmdwriter.h | 498 - .../src/commandwriter/gfx8_cmds.h | 161 - .../src/commandwriter/gfx8_cmdwriter.cpp | 765 - .../src/commandwriter/gfx8_cmdwriter.h | 201 - .../src/commandwriter/gfx9_cmds.h | 90 - .../src/commandwriter/gfx9_cmdwriter.cpp | 743 - .../src/commandwriter/gfx9_cmdwriter.h | 199 - .../src/core/CMakeLists.txt | 20 - .../src/core/amd_aql_pm4_ib_packet.h | 67 - .../src/core/aql_profile.cpp | 503 - .../hsa-amd-aqlprofile/src/core/aql_profile.h | 40 - .../src/core/aql_profile_exception.h | 34 - .../src/core/gfx8_factory.cpp | 50 - .../src/core/gfx9_factory.cpp | 65 - .../src/core/legacy_pm4.cpp | 97 - runtime/hsa-amd-aqlprofile/src/core/logger.h | 137 - .../hsa-amd-aqlprofile/src/core/pm4_factory.h | 157 - .../src/core/populate_aql.cpp | 49 - .../src/perfcounter/CMakeLists.txt | 17 - .../src/perfcounter/gfx8_block_info.cpp | 624 - .../src/perfcounter/gfx8_block_info.h | 227 - .../src/perfcounter/gfx8_perf_counter.cpp | 1307 - .../src/perfcounter/gfx8_perf_counter.h | 71 - .../src/perfcounter/gfx9_block_info.cpp | 553 - .../src/perfcounter/gfx9_block_info.h | 245 - .../src/perfcounter/gfx9_perf_counter.cpp | 1327 - .../src/perfcounter/gfx9_perf_counter.h | 69 - .../src/perfcounter/gpu_block_info.h | 98 - .../src/perfcounter/perf_counter.h | 35 - .../src/threadtrace/CMakeLists.txt | 16 - .../src/threadtrace/gfx8_thread_trace.cpp | 352 - .../src/threadtrace/gfx8_thread_trace.h | 99 - .../src/threadtrace/gfx9_thread_trace.cpp | 348 - .../src/threadtrace/gfx9_thread_trace.h | 104 - .../src/threadtrace/thread_trace.cpp | 59 - .../src/threadtrace/thread_trace.h | 97 - .../hsa-amd-aqlprofile/test/CMakeLists.txt | 48 - .../test/binary_search/binary_search.cc | 876 - .../binary_search/binary_search_kernels.cl | 127 - runtime/hsa-amd-aqlprofile/test/ctrl/test.cpp | 91 - .../hsa-amd-aqlprofile/test/ctrl/test_aql.h | 78 - .../test/ctrl/test_assert.h | 13 - .../hsa-amd-aqlprofile/test/ctrl/test_hsa.cpp | 237 - .../hsa-amd-aqlprofile/test/ctrl/test_hsa.h | 115 - .../test/ctrl/test_kernel.h | 105 - .../hsa-amd-aqlprofile/test/ctrl/test_pgen.h | 45 - .../test/ctrl/test_pgen_pmc.h | 163 - .../test/ctrl/test_pgen_sqtt.h | 162 - .../test/ctrl/test_pmgr.cpp | 130 - .../hsa-amd-aqlprofile/test/ctrl/test_pmgr.h | 71 - runtime/hsa-amd-aqlprofile/test/run.sh | 30 - .../gfx8_simpleConvolution.hsaco | Bin 9392 -> 0 bytes .../gfx9_simpleConvolution.hsaco | Bin 9392 -> 0 bytes .../simple_convolution/simple_convolution.cl | 81 - .../simple_convolution/simple_convolution.cpp | 160 - .../simple_convolution/simple_convolution.h | 90 - .../simple_convolution.hsail | 154 - .../test/util/CMakeLists.txt | 15 - .../test/util/helper_funcs.cpp | 230 - .../test/util/helper_funcs.h | 90 - .../test/util/hsa_rsrc_factory.cpp | 473 - .../test/util/hsa_rsrc_factory.h | 262 - .../test/util/perf_timer.cpp | 157 - .../hsa-amd-aqlprofile/test/util/perf_timer.h | 62 - 105 files changed, 359609 deletions(-) delete mode 100644 runtime/hsa-amd-aqlprofile/CMakeLists.txt delete mode 100644 runtime/hsa-amd-aqlprofile/Readme.txt delete mode 100644 runtime/hsa-amd-aqlprofile/cmake_modules/exportToolFlags.cmake delete mode 100644 runtime/hsa-amd-aqlprofile/cmake_modules/validateBldEnv.cmake delete mode 100644 runtime/hsa-amd-aqlprofile/doc/HSA_ven_amd_aqlprofile_api.pptx delete mode 100644 runtime/hsa-amd-aqlprofile/doc/HSA_ven_amd_aqlprofile_api_v1_2_0.docx delete mode 100644 runtime/hsa-amd-aqlprofile/gfxip/gfx8/features_bonaire.h delete mode 100644 runtime/hsa-amd-aqlprofile/gfxip/gfx8/features_hainan.h delete mode 100644 runtime/hsa-amd-aqlprofile/gfxip/gfx8/features_oland.h delete mode 100644 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CACHE BOOL "Verbose Output" FORCE ) - -set ( ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR} ) -set ( PROJ_DIR ${ROOT_DIR}/src ) -set ( TEST_DIR ${ROOT_DIR}/test ) - -# -# Build sources -# -include ( ${PROJ_DIR}/CMakeLists.txt ) - -# -# Build tests -# -add_subdirectory ( ${TEST_DIR} ${PROJECT_BINARY_DIR}/test ) - -# -# Style format -# -execute_process ( COMMAND sh -xc "/usr/bin/find ${PROJ_DIR} ${TEST_DIR} -name '*.cpp' -exec /usr/bin/clang-format -i -style=file \{\} \;" ) -execute_process ( COMMAND sh -xc "/usr/bin/find ${PROJ_DIR} ${TEST_DIR} -name '*.hpp' -exec /usr/bin/clang-format -i -style=file \{\} \;" ) -execute_process ( COMMAND sh -xc "/usr/bin/find ${PROJ_DIR} ${TEST_DIR} -name '*.h' -exec /usr/bin/clang-format -i -style=file \{\} \;" ) diff --git a/runtime/hsa-amd-aqlprofile/Readme.txt b/runtime/hsa-amd-aqlprofile/Readme.txt deleted file mode 100644 index c1165a7003..0000000000 --- a/runtime/hsa-amd-aqlprofile/Readme.txt +++ /dev/null @@ -1,44 +0,0 @@ -HSA extension AMD AQL profile library. -Provides AQL packets helper methods for -perfcounters (PMC) and SQ threadtraces (SQTT). - -Current library implementation supports only GFX9. -The library source tree: - - doc - Documantation, the API specification and the presentation - - inc - Public API - - hsa_ven_amd_aqlprofile.h - AMD AQL profile library public API - - src - AMD AQL profile library sources - - core - the library sources - - commandwriter - PM4 command writer originated from 'hsa-runtime/tools' - - perfcounter - PM4 perfcounter manager originated from 'hsa-runtime/tools' - - threadtrace - PM4 threadtrace manager originated from 'hsa-runtime/tools' - - test - the library test suite - - ctrl - Test controll - - util - Test utils - - SimpleConvolution - Simple convolution test - -To build the library: - -$ cd .../hsa-amd-aqlprofile -$ mkdir build -$ cd build -$ cmake .. -$ make - -To run the test: - -$ cd .../hsa-amd-aqlprofile/build -$ export LD_LIBRARY_PATH=$PWD -$ ./test/ctrl - -To enable PMC profiling: - -$ export ROCR_ENABLE_PMC=1 - -To enable SQTT profiling: - -$ export ROCR_ENABLE_SQTT=1 - -Or to use the script: - -$ ./run.sh diff --git a/runtime/hsa-amd-aqlprofile/cmake_modules/exportToolFlags.cmake b/runtime/hsa-amd-aqlprofile/cmake_modules/exportToolFlags.cmake deleted file mode 100644 index 59b470a991..0000000000 --- a/runtime/hsa-amd-aqlprofile/cmake_modules/exportToolFlags.cmake +++ /dev/null @@ -1,66 +0,0 @@ -# -# Compiler Preprocessor definitions. -# -add_definitions ( -D__linux__ ) -add_definitions ( -DUNIX_OS ) -add_definitions ( -DLINUX ) -add_definitions ( -D__AMD64__ ) -add_definitions ( -D__x86_64__ ) -add_definitions ( -DAMD_INTERNAL_BUILD ) -add_definitions ( -DLITTLEENDIAN_CPU=1 ) -add_definitions ( -DHSA_LARGE_MODEL= ) -add_definitions ( -DHSA_DEPRECATED= ) - -# -# Linux Compiler options -# -set ( CMAKE_CXX_FLAGS "-std=c++11") -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Werror" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Werror=return-type" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fexceptions" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fvisibility=hidden" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-error=sign-compare" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-error=enum-compare" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-error=comment " ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-error=pointer-arith" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-comment" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-sign-compare" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-pointer-arith" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-write-strings" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-conversion-null" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-deprecated-declarations" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-rtti" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-math-errno" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-threadsafe-statics" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fms-extensions" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fmerge-all-constants" ) -set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fPIC" ) - -# -# Extend Compiler flags based on build type -# -set ( CMAKE_BUILD_TYPE ${BUILD_TYPE} ) -if ( "${CMAKE_BUILD_TYPE}" STREQUAL Debug ) - set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -ggdb" ) -endif () - -# -# Extend Compiler flags based on Processor architecture -# -if ( CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64" ) - set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -m64 -msse -msse2" ) -elseif ( CMAKE_SYSTEM_PROCESSOR STREQUAL "x86" ) - set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -m32" ) -endif () - -# -# Basic Tool Chain Information -# -message ( "-------------IS64BIT: " ${IS64BIT} ) -message ( "-----------BuildType: " ${BUILD_TYPE} ) -message ( " -----------Compiler: " ${CMAKE_CXX_COMPILER} ) -message ( " ------------Version: " ${CMAKE_CXX_COMPILER_VERSION} ) -message ( " ------------ProjDir: " ${PROJ_DIR} ) -message ( " ------------TestDir: " ${PROJ_DIR} ) -message ( "------HSA-RuntimeDir: " ${HSA_RUNTIME_DIR} ) -message ( " -----------CoreUtil: " ${CORE_UTIL_DIR} ) diff --git a/runtime/hsa-amd-aqlprofile/cmake_modules/validateBldEnv.cmake b/runtime/hsa-amd-aqlprofile/cmake_modules/validateBldEnv.cmake deleted file mode 100644 index d38352bbbc..0000000000 --- a/runtime/hsa-amd-aqlprofile/cmake_modules/validateBldEnv.cmake +++ /dev/null @@ -1,52 +0,0 @@ -# -# Build is not supported on Windows plaform -# -if ( WIN32 ) - message ( FATAL_ERROR "Windows build is not supported." ) -endif () - -# -# External dependencies for Rocr Header files -# -if ( NOT DEFINED ENV{ROCR_INC_DIR} ) - message ( FATAL_ERROR "ERROR: Environment variable ROCR_INC_DIR is not set" ) - return () -endif () - -# -# External dependencies for Rocr Library files -# -if ( NOT DEFINED ENV{ROCR_LIB_DIR} ) - message ( FATAL_ERROR "ERROR: Environment variable ROCR_LIB_DIR is not set" ) - return () -endif () - -# -# Process Env to determine build type -# -string ( TOLOWER "$ENV{ROCR_BLD_TYPE}" type ) -if ( "${type}" STREQUAL debug ) - set ( ISDEBUG 1 ) - set ( BUILD_TYPE "Debug" ) -else () - set ( ISDEBUG 0 ) - set ( BUILD_TYPE "Release" ) -endif () - -# -# Determine build is 32-bit or 64-bit -# @note: By default it is not set -# -if ( "$ENV{ROCR_BLD_BITS}" STREQUAL 32 ) - set ( ONLY64STR "" ) - set ( IS64BIT 0 ) -else () - set ( ONLY64STR "64" ) - set ( IS64BIT 1 ) -endif () - -# -# Build information -# -message ( "---------ROCR-HdrDir: " $ENV{ROCR_INC_DIR} ) -message ( "---------ROCR-LibDir: " $ENV{ROCR_LIB_DIR} ) diff --git a/runtime/hsa-amd-aqlprofile/doc/HSA_ven_amd_aqlprofile_api.pptx b/runtime/hsa-amd-aqlprofile/doc/HSA_ven_amd_aqlprofile_api.pptx deleted file mode 100644 index ec356d64097a16868c2f2fdfe13786885a790802..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1114397 zcmeFZW0Wo3wk?>pZQHhO+qP}nwryjlZ98|GJ9pZdJN@!}=e~MXb-#1#wO0S`dGTXK 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0x00000003 - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_TS 0x00000004 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CONTEXT_DONE 0x00000005 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH 0x00000006 - EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // CS_PARTIAL_FLUSH 0x00000007 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_SYNC 0x00000008 - 0, // Reserved_0x09 0x00000009 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_RESET 0x0000000a - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_INCR_DE 0x0000000b - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_IB_END 0x0000000c - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RST_PIX_CNT 0x0000000d - 0, // Reserved_0x0E 0x0000000e - EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // VS_PARTIAL_FLUSH 0x0000000f - EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // PS_PARTIAL_FLUSH 0x00000010 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_HS_OUTPUT 0x00000011 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_LS_OUTPUT 0x00000012 - 0, // Reserved_0x13 0x00000013 - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_AND_INV_TS_EVENT - // 0x00000014 - EVENT_WRITE_INDEX_ZPASS_DONE, // ZPASS_DONE 0x00000015 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH_AND_INV_EVENT - // 0x00000016 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_START 0x00000017 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_STOP 0x00000018 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_START 0x00000019 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_STOP 0x0000001a - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_SAMPLE 0x0000001b - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_ES_OUTPUT 0x0000001c - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_GS_OUTPUT 0x0000001d - EVENT_WRITE_INDEX_SAMPLE_PIPELINESTAT, // SAMPLE_PIPELINESTAT 0x0000001e - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SO_VGTSTREAMOUT_FLUSH 0x0000001f - EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS - // 0x00000020 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RESET_VTX_CNT 0x00000021 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // BLOCK_CONTEXT_DONE 0x00000022 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CS_CONTEXT_DONE 0x00000023 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_FLUSH 0x00000024 - 0, // Reserved_0x25 0x00000025 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SQ_NON_EVENT 0x00000026 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SC_SEND_DB_VPZ 0x00000027 - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // BOTTOM_OF_PIPE_TS 0x00000028 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_SX_TS 0x00000029 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // DB_CACHE_FLUSH_AND_INV 0x0000002a - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_DB_DATA_TS 0x0000002b - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_DB_META 0x0000002c - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_CB_DATA_TS 0x0000002d - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_META 0x0000002e - EVENT_WRITE_EOS_INDEX_CSDONE_PSDONE, // CS_DONE 0x0000002f - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PS_DONE 0x00000030 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_PIXEL_DATA - // 0x00000031 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SX_CB_RAT_ACK_REQUEST 0x00000032 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_START 0x00000033 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_STOP 0x00000034 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_MARKER 0x00000035 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FLUSH 0x00000036 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FINISH 0x00000037 -}; - -/// @brief Enum specifying the size of elements of a buffer -enum BufElementSize { - kBufElementSize2 = 0, - kBufElementSize4 = 1, - kBufElementSize8 = 2, - kBufElementSize16 = 3 -}; - -/// @brief Enum specifying the striding of a buffer -enum BufIndexStride { - kBufIndexStride8 = 0, - kBufIndexStride16 = 1, - kBufIndexStride32 = 2, - kBufIndexStride64 = 3 -}; - -} // gfx8 - -} // pm4_profile - -#endif // _GFX8_UTILS_H_ diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_enum.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_enum.h deleted file mode 100644 index 8f75d3551b..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_enum.h +++ /dev/null @@ -1,10081 +0,0 @@ -#if !defined(SI_CI_VI_MERGED_ENUM_HEADER) -#define SI_CI_VI_MERGED_ENUM_HEADER - - -// -// Source merge files: -// E:\MergedHeaders\SI+CI+Amur\Original\SICI/si_ci_merged_enum.h -// E:\MergedHeaders\SI+CI+Amur\Original\Amur/vi_enum.h -// -// -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -typedef enum ArrayMode { - ARRAY_LINEAR_GENERAL = 0x00000000, - ARRAY_LINEAR_ALIGNED = 0x00000001, - ARRAY_1D_TILED_THIN1 = 0x00000002, - ARRAY_1D_TILED_THICK = 0x00000003, - ARRAY_2D_TILED_THIN1 = 0x00000004, - ARRAY_2D_TILED_THIN2__SI = 0x00000005, - ARRAY_PRT_TILED_THIN1__CI__VI = 0x00000005, - ARRAY_2D_TILED_THIN4__SI = 0x00000006, - ARRAY_PRT_2D_TILED_THIN1__CI__VI = 0x00000006, - ARRAY_2D_TILED_THICK = 0x00000007, - ARRAY_2D_TILED_XTHICK = 0x00000008, - ARRAY_2B_TILED_THIN2__SI = 0x00000009, - ARRAY_PRT_TILED_THICK__CI__VI = 0x00000009, - ARRAY_2B_TILED_THIN4__SI = 0x0000000a, - ARRAY_PRT_2D_TILED_THICK__CI__VI = 0x0000000a, - ARRAY_2B_TILED_THICK__SI = 0x0000000b, - ARRAY_PRT_3D_TILED_THIN1__CI__VI = 0x0000000b, - ARRAY_3D_TILED_THIN1 = 0x0000000c, - ARRAY_3D_TILED_THICK = 0x0000000d, - ARRAY_3D_TILED_XTHICK = 0x0000000e, - ARRAY_POWER_SAVE__SI = 0x0000000f, - ARRAY_PRT_3D_TILED_THICK__CI__VI = 0x0000000f, -} ArrayMode; - -typedef enum BUF_DATA_FORMAT { - BUF_DATA_FORMAT_INVALID = 0x00000000, - BUF_DATA_FORMAT_8 = 0x00000001, - BUF_DATA_FORMAT_16 = 0x00000002, - BUF_DATA_FORMAT_8_8 = 0x00000003, - BUF_DATA_FORMAT_32 = 0x00000004, - BUF_DATA_FORMAT_16_16 = 0x00000005, - BUF_DATA_FORMAT_10_11_11 = 0x00000006, - BUF_DATA_FORMAT_11_11_10 = 0x00000007, - BUF_DATA_FORMAT_10_10_10_2 = 0x00000008, - BUF_DATA_FORMAT_2_10_10_10 = 0x00000009, - BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a, - BUF_DATA_FORMAT_32_32 = 0x0000000b, - BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c, - BUF_DATA_FORMAT_32_32_32 = 0x0000000d, - BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e, - BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f, -} BUF_DATA_FORMAT; - -typedef enum BUF_NUM_FORMAT { - BUF_NUM_FORMAT_UNORM = 0x00000000, - BUF_NUM_FORMAT_SNORM = 0x00000001, - BUF_NUM_FORMAT_USCALED = 0x00000002, - BUF_NUM_FORMAT_SSCALED = 0x00000003, - BUF_NUM_FORMAT_UINT = 0x00000004, - BUF_NUM_FORMAT_SINT = 0x00000005, - BUF_NUM_FORMAT_SNORM_OGL__SI__CI = 0x00000006, - BUF_NUM_FORMAT_RESERVED_6__VI = 0x00000006, - BUF_NUM_FORMAT_FLOAT = 0x00000007, -} BUF_NUM_FORMAT; - -typedef enum BankHeight { - ADDR_SURF_BANK_HEIGHT_1 = 0x00000000, - ADDR_SURF_BANK_HEIGHT_2 = 0x00000001, - ADDR_SURF_BANK_HEIGHT_4 = 0x00000002, - ADDR_SURF_BANK_HEIGHT_8 = 0x00000003, -} BankHeight; - -typedef enum BankInterleaveSize { - ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, - ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, - ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, - ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, -} BankInterleaveSize; - -typedef enum BankSwapBytes { - CONFIG_128B_SWAPS = 0x00000000, - CONFIG_256B_SWAPS = 0x00000001, - CONFIG_512B_SWAPS = 0x00000002, - CONFIG_1KB_SWAPS = 0x00000003, -} BankSwapBytes; - -typedef enum BankTiling { - CONFIG_4_BANK = 0x00000000, - CONFIG_8_BANK = 0x00000001, -} BankTiling; - -typedef enum BankWidth { - ADDR_SURF_BANK_WIDTH_1 = 0x00000000, - ADDR_SURF_BANK_WIDTH_2 = 0x00000001, - ADDR_SURF_BANK_WIDTH_4 = 0x00000002, - ADDR_SURF_BANK_WIDTH_8 = 0x00000003, -} BankWidth; - -typedef enum BankWidthHeight { - ADDR_SURF_BANK_WH_1 = 0x00000000, - ADDR_SURF_BANK_WH_2 = 0x00000001, - ADDR_SURF_BANK_WH_4 = 0x00000002, - ADDR_SURF_BANK_WH_8 = 0x00000003, -} BankWidthHeight; - -typedef enum BlendOp { - BLEND_ZERO = 0x00000000, - BLEND_ONE = 0x00000001, - BLEND_SRC_COLOR = 0x00000002, - BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, - BLEND_SRC_ALPHA = 0x00000004, - BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, - BLEND_DST_ALPHA = 0x00000006, - BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, - BLEND_DST_COLOR = 0x00000008, - BLEND_ONE_MINUS_DST_COLOR = 0x00000009, - BLEND_SRC_ALPHA_SATURATE = 0x0000000a, - BLEND_BOTH_SRC_ALPHA = 0x0000000b, - BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c, - BLEND_CONSTANT_COLOR = 0x0000000d, - BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e, - BLEND_SRC1_COLOR = 0x0000000f, - BLEND_INV_SRC1_COLOR = 0x00000010, - BLEND_SRC1_ALPHA = 0x00000011, - BLEND_INV_SRC1_ALPHA = 0x00000012, - BLEND_CONSTANT_ALPHA = 0x00000013, - BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014, -} BlendOp; - -typedef enum BlendOpt { - FORCE_OPT_AUTO = 0x00000000, - FORCE_OPT_DISABLE = 0x00000001, - FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, - FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, - FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, - FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, - FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, - FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, -} BlendOpt; - -typedef enum CBMode { - CB_DISABLE = 0x00000000, - CB_NORMAL = 0x00000001, - CB_ELIMINATE_FAST_CLEAR = 0x00000002, - CB_RESOLVE = 0x00000003, - CB_DECOMPRESS = 0x00000004, - CB_FMASK_DECOMPRESS = 0x00000005, - CB_DCC_DECOMPRESS__VI = 0x00000006, -} CBMode; - -typedef enum CBPerfClearFilterSel { - CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, - CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, -} CBPerfClearFilterSel; - -typedef enum CBPerfOpFilterSel { - CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, - CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, - CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, - CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, - CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, - CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, -} CBPerfOpFilterSel; - -typedef enum CBPerfSel { - CB_PERF_SEL_NONE = 0x00000000, - CB_PERF_SEL_BUSY = 0x00000001, - CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002, - CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003, - CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004, - CB_PERF_SEL_DRAWN_QUAD = 0x00000005, - CB_PERF_SEL_DRAWN_PIXEL = 0x00000006, - CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007, - CB_PERF_SEL_DRAWN_TILE = 0x00000008, - CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009, - CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a, - CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b, - CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c, - CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d, - CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e, - CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f, - CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010, - CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011, - CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012, - CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013, - CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014, - CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015, - CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016, - CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e, - CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f, - CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020, - CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021, - CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022, - CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023, - CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024, - CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025, - CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026, - CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027, - CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028, - CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029, - CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a, - CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b, - CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c, - CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d, - CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e, - CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f, - CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030, - CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031, - CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032, - CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033, - CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034, - CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035, - CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036, - CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f, - CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040, - CB_PERF_SEL_CM_CACHE_HIT = 0x00000041, - CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042, - CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043, - CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044, - CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045, - CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046, - CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047, - CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048, - CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049, - CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a, - CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b, - CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c, - CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d, - CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e, - CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f, - CB_PERF_SEL_FC_CACHE_HIT = 0x00000050, - CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051, - CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052, - CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053, - CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054, - CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055, - CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056, - CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057, - CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058, - CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059, - CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a, - CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b, - CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c, - CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d, - CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e, - CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f, - CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060, - CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061, - CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062, - CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063, - CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064, - CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065, - CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066, - CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067, - CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068, - CB_PERF_SEL_CC_CACHE_STALL = 0x00000069, - CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a, - CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b, - CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c, - CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d, - CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e, - CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY__SI__CI = 0x0000006f, - CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC__VI = 0x0000006f, - CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB__SI__CI = 0x00000070, - CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY__VI = 0x00000070, - CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY__SI__CI = 0x00000071, - CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB__VI = 0x00000071, - CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB__SI__CI = 0x00000072, - CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY__VI = 0x00000072, - CB_PERF_SEL_CM_MC_WRITE_REQUEST__SI__CI = 0x00000073, - CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB__VI = 0x00000073, - CB_PERF_SEL_FC_MC_WRITE_REQUEST__SI__CI = 0x00000074, - CB_PERF_SEL_CM_MC_WRITE_REQUEST__VI = 0x00000074, - CB_PERF_SEL_CC_MC_WRITE_REQUEST__SI__CI = 0x00000075, - CB_PERF_SEL_FC_MC_WRITE_REQUEST__VI = 0x00000075, - CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000076, - CB_PERF_SEL_CC_MC_WRITE_REQUEST__VI = 0x00000076, - CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000077, - CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000077, - CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000078, - CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000078, - CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY__SI__CI = 0x00000079, - CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000079, - CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB__SI__CI = 0x0000007a, - CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY__VI = 0x0000007a, - CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY__SI__CI = 0x0000007b, - CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB__VI = 0x0000007b, - CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB__SI__CI = 0x0000007c, - CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY__VI = 0x0000007c, - CB_PERF_SEL_CM_MC_READ_REQUEST__SI__CI = 0x0000007d, - CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB__VI = 0x0000007d, - CB_PERF_SEL_FC_MC_READ_REQUEST__SI__CI = 0x0000007e, - CB_PERF_SEL_CM_MC_READ_REQUEST__VI = 0x0000007e, - CB_PERF_SEL_CC_MC_READ_REQUEST__SI__CI = 0x0000007f, - CB_PERF_SEL_FC_MC_READ_REQUEST__VI = 0x0000007f, - CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000080, - CB_PERF_SEL_CC_MC_READ_REQUEST__VI = 0x00000080, - CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000081, - CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000081, - CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000082, - CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000082, - CB_PERF_SEL_CM_TQ_FULL__SI__CI = 0x00000083, - CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000083, - CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL__SI__CI = 0x00000084, - CB_PERF_SEL_CM_TQ_FULL__VI = 0x00000084, - CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL__SI__CI = 0x00000085, - CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL__VI = 0x00000085, - CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL__SI__CI = 0x00000086, - CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL__VI = 0x00000086, - CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x00000087, - CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL__VI = 0x00000087, - CB_PERF_SEL_FOP_FMASK_RAW_STALL__SI__CI = 0x00000088, - CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL__VI = 0x00000088, - CB_PERF_SEL_FOP_FMASK_BYPASS_STALL__SI__CI = 0x00000089, - CB_PERF_SEL_FOP_FMASK_RAW_STALL__VI = 0x00000089, - CB_PERF_SEL_CC_SF_FULL__SI__CI = 0x0000008a, - CB_PERF_SEL_FOP_FMASK_BYPASS_STALL__VI = 0x0000008a, - CB_PERF_SEL_CC_RB_FULL__SI__CI = 0x0000008b, - CB_PERF_SEL_CC_SF_FULL__VI = 0x0000008b, - CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x0000008c, - CB_PERF_SEL_CC_RB_FULL__VI = 0x0000008c, - CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x0000008d, - CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL__VI = 0x0000008d, - CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL__SI__CI = 0x0000008e, - CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL__VI = 0x0000008e, - CB_PERF_SEL_EVENT__SI__CI = 0x0000008f, - CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL__VI = 0x0000008f, - CB_PERF_SEL_EVENT_CACHE_FLUSH_TS__SI__CI = 0x00000090, - CB_PERF_SEL_EVENT__VI = 0x00000090, - CB_PERF_SEL_EVENT_CONTEXT_DONE__SI__CI = 0x00000091, - CB_PERF_SEL_EVENT_CACHE_FLUSH_TS__VI = 0x00000091, - CB_PERF_SEL_EVENT_CACHE_FLUSH__SI__CI = 0x00000092, - CB_PERF_SEL_EVENT_CONTEXT_DONE__VI = 0x00000092, - CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SI__CI = 0x00000093, - CB_PERF_SEL_EVENT_CACHE_FLUSH__VI = 0x00000093, - CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT__SI__CI = 0x00000094, - CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__VI = 0x00000094, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS__SI__CI = 0x00000095, - CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT__VI = 0x00000095, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META__SI__CI = 0x00000096, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS__VI = 0x00000096, - CB_PERF_SEL_CC_SURFACE_SYNC__SI__CI = 0x00000097, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META__VI = 0x00000097, - CB_PERF_SEL_CMASK_READ_DATA_0xC__SI__CI = 0x00000098, - CB_PERF_SEL_CC_SURFACE_SYNC__VI = 0x00000098, - CB_PERF_SEL_CMASK_READ_DATA_0xD__SI__CI = 0x00000099, - CB_PERF_SEL_CMASK_READ_DATA_0xC__VI = 0x00000099, - CB_PERF_SEL_CMASK_READ_DATA_0xE__SI__CI = 0x0000009a, - CB_PERF_SEL_CMASK_READ_DATA_0xD__VI = 0x0000009a, - CB_PERF_SEL_CMASK_READ_DATA_0xF__SI__CI = 0x0000009b, - CB_PERF_SEL_CMASK_READ_DATA_0xE__VI = 0x0000009b, - CB_PERF_SEL_CMASK_WRITE_DATA_0xC__SI__CI = 0x0000009c, - CB_PERF_SEL_CMASK_READ_DATA_0xF__VI = 0x0000009c, - CB_PERF_SEL_CMASK_WRITE_DATA_0xD__SI__CI = 0x0000009d, - CB_PERF_SEL_CMASK_WRITE_DATA_0xC__VI = 0x0000009d, - CB_PERF_SEL_CMASK_WRITE_DATA_0xE__SI__CI = 0x0000009e, - CB_PERF_SEL_CMASK_WRITE_DATA_0xD__VI = 0x0000009e, - CB_PERF_SEL_CMASK_WRITE_DATA_0xF__SI__CI = 0x0000009f, - CB_PERF_SEL_CMASK_WRITE_DATA_0xE__VI = 0x0000009f, - CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT__SI__CI = 0x000000a0, - CB_PERF_SEL_CMASK_WRITE_DATA_0xF__VI = 0x000000a0, - CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT__SI__CI = 0x000000a1, - CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT__VI = 0x000000a1, - CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SI__CI = 0x000000a2, - CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT__VI = 0x000000a2, - CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SI__CI = 0x000000a3, - CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT__VI = 0x000000a3, - CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a4, - CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__VI = 0x000000a4, - CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a5, - CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a5, - CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a6, - CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a6, - CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a7, - CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a7, - CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a8, - CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a8, - CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a9, - CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a9, - CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000aa, - CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000aa, - CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SI__CI = 0x000000ab, - CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000ab, - CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ac, - CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__VI = 0x000000ac, - CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ad, - CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__VI = 0x000000ad, - CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ae, - CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__VI = 0x000000ae, - CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000af, - CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__VI = 0x000000af, - CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b0, - CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b0, - CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b1, - CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b1, - CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b2, - CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b2, - CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT__SI__CI = 0x000000b3, - CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b3, - CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS__SI__CI = 0x000000b4, - CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT__VI = 0x000000b4, - CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS__SI__CI = 0x000000b5, - CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS__VI = 0x000000b5, - CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS__SI__CI = 0x000000b6, - CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS__VI = 0x000000b6, - CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS__SI__CI = 0x000000b7, - CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS__VI = 0x000000b7, - CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS__SI__CI = 0x000000b8, - CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS__VI = 0x000000b8, - CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS__SI__CI = 0x000000b9, - CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS__VI = 0x000000b9, - CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT__SI__CI = 0x000000ba, - CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS__VI = 0x000000ba, - CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS__SI__CI = 0x000000bb, - CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT__VI = 0x000000bb, - CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS__SI__CI = 0x000000bc, - CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS__VI = 0x000000bc, - CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS__SI__CI = 0x000000bd, - CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS__VI = 0x000000bd, - CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS__SI__CI = 0x000000be, - CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS__VI = 0x000000be, - CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS__SI__CI = 0x000000bf, - CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS__VI = 0x000000bf, - CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS__SI__CI = 0x000000c0, - CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS__VI = 0x000000c0, - CB_PERF_SEL_QUAD_READS_FRAGMENT_0__SI__CI = 0x000000c1, - CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS__VI = 0x000000c1, - CB_PERF_SEL_QUAD_READS_FRAGMENT_1__SI__CI = 0x000000c2, - CB_PERF_SEL_QUAD_READS_FRAGMENT_0__VI = 0x000000c2, - CB_PERF_SEL_QUAD_READS_FRAGMENT_2__SI__CI = 0x000000c3, - CB_PERF_SEL_QUAD_READS_FRAGMENT_1__VI = 0x000000c3, - CB_PERF_SEL_QUAD_READS_FRAGMENT_3__SI__CI = 0x000000c4, - CB_PERF_SEL_QUAD_READS_FRAGMENT_2__VI = 0x000000c4, - CB_PERF_SEL_QUAD_READS_FRAGMENT_4__SI__CI = 0x000000c5, - CB_PERF_SEL_QUAD_READS_FRAGMENT_3__VI = 0x000000c5, - CB_PERF_SEL_QUAD_READS_FRAGMENT_5__SI__CI = 0x000000c6, - CB_PERF_SEL_QUAD_READS_FRAGMENT_4__VI = 0x000000c6, - CB_PERF_SEL_QUAD_READS_FRAGMENT_6__SI__CI = 0x000000c7, - CB_PERF_SEL_QUAD_READS_FRAGMENT_5__VI = 0x000000c7, - CB_PERF_SEL_QUAD_READS_FRAGMENT_7__SI__CI = 0x000000c8, - CB_PERF_SEL_QUAD_READS_FRAGMENT_6__VI = 0x000000c8, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0__SI__CI = 0x000000c9, - CB_PERF_SEL_QUAD_READS_FRAGMENT_7__VI = 0x000000c9, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1__SI__CI = 0x000000ca, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0__VI = 0x000000ca, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2__SI__CI = 0x000000cb, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1__VI = 0x000000cb, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3__SI__CI = 0x000000cc, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2__VI = 0x000000cc, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4__SI__CI = 0x000000cd, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3__VI = 0x000000cd, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5__SI__CI = 0x000000ce, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4__VI = 0x000000ce, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6__SI__CI = 0x000000cf, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5__VI = 0x000000cf, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7__SI__CI = 0x000000d0, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6__VI = 0x000000d0, - CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST__SI__CI = 0x000000d1, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7__VI = 0x000000d1, - CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS__SI__CI = 0x000000d2, - CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST__VI = 0x000000d2, - CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS__SI__CI = 0x000000d3, - CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS__VI = 0x000000d3, - CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED__SI__CI = 0x000000d4, - CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS__VI = 0x000000d4, - CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED__SI__CI = 0x000000d5, - CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED__VI = 0x000000d5, - CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED__SI__CI = 0x000000d6, - CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED__VI = 0x000000d6, - CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST__CI = 0x000000d7, - CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED__VI = 0x000000d7, - CB_PERF_SEL_DRAWN_BUSY__CI = 0x000000d8, - CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST__VI = 0x000000d8, - CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY__CI = 0x000000d9, - CB_PERF_SEL_DRAWN_BUSY__VI = 0x000000d9, - CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY__CI = 0x000000da, - CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY__VI = 0x000000da, - CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY__CI = 0x000000db, - CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY__VI = 0x000000db, - CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY__CI = 0x000000dc, - CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY__VI = 0x000000dc, - CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED__CI = 0x000000dd, - CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY__VI = 0x000000dd, - CB_PERF_SEL_FC_SEQUENCER_CLEAR__CI = 0x000000de, - CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED__VI = 0x000000de, - CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR__CI = 0x000000df, - CB_PERF_SEL_FC_SEQUENCER_CLEAR__VI = 0x000000df, - CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS__CI = 0x000000e0, - CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR__VI = 0x000000e0, - CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__CI = 0x000000e1, - CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS__VI = 0x000000e1, - CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__VI = 0x000000e2, - CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL__VI = 0x000000e3, - CB_PERF_SEL_FC_DOC_IS_STALLED__VI = 0x000000e4, - CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED__VI = 0x000000e5, - CB_PERF_SEL_FC_DOC_MRTS_COMBINED__VI = 0x000000e6, - CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS__VI = 0x000000e7, - CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT__VI = 0x000000e8, - CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS__VI = 0x000000e9, - CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT__VI = 0x000000ea, - CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL__VI = 0x000000eb, - CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR__VI = 0x000000ec, - CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS__VI = 0x000000ed, - CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS__VI = 0x000000ee, - CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS__VI = 0x000000ef, - CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS__VI = 0x000000f0, - CB_PERF_SEL_FC_DCC_CACHE_HIT__VI = 0x000000f1, - CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS__VI = 0x000000f2, - CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS__VI = 0x000000f3, - CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL__VI = 0x000000f4, - CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__VI = 0x000000f5, - CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__VI = 0x000000f6, - CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__VI = 0x000000f7, - CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL__VI = 0x000000f8, - CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL__VI = 0x000000f9, - CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL__VI = 0x000000fa, - CB_PERF_SEL_FC_DCC_CACHE_STALL__VI = 0x000000fb, - CB_PERF_SEL_FC_DCC_CACHE_FLUSH__VI = 0x000000fc, - CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED__VI = 0x000000fd, - CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED__VI = 0x000000fe, - CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED__VI = 0x000000ff, - CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT__VI = 0x00000100, - CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST__VI = 0x00000101, - CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000102, - CB_PERF_SEL_FC_MC_DCC_READ_REQUEST__VI = 0x00000103, - CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000104, - CB_PERF_SEL_CC_DCC_RDREQ_STALL__VI = 0x00000105, - CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN__VI = 0x00000106, - CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT__VI = 0x00000107, - CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN__VI = 0x00000108, - CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT__VI = 0x00000109, - CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR__VI = 0x0000010a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1__VI = 0x0000010b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2__VI = 0x0000010c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__VI = 0x0000010d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1__VI = 0x0000010e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1__VI = 0x0000010f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2__VI = 0x00000110, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1__VI = 0x00000111, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__VI = 0x00000112, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__VI = 0x00000113, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1__VI = 0x00000114, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2__VI = 0x00000115, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2__VI = 0x00000116, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2__VI = 0x00000117, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__VI = 0x00000118, - CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1__VI = 0x00000119, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1__VI = 0x0000011a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2__VI = 0x0000011b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3__VI = 0x0000011c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4__VI = 0x0000011d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1__VI = 0x0000011e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2__VI = 0x0000011f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3__VI = 0x00000120, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4__VI = 0x00000121, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1__VI = 0x00000122, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2__VI = 0x00000123, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3__VI = 0x00000124, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4__VI = 0x00000125, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1__VI = 0x00000126, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2__VI = 0x00000127, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3__VI = 0x00000128, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1__VI = 0x00000129, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2__VI = 0x0000012a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3__VI = 0x0000012b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4__VI = 0x0000012c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1__VI = 0x0000012d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2__VI = 0x0000012e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3__VI = 0x0000012f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4__VI = 0x00000130, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1__VI = 0x00000131, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2__VI = 0x00000132, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3__VI = 0x00000133, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4__VI = 0x00000134, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1__VI = 0x00000135, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2__VI = 0x00000136, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3__VI = 0x00000137, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1__VI = 0x00000138, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1__VI = 0x00000139, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1__VI = 0x0000013a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1__VI = 0x0000013b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1__VI = 0x0000013c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1__VI = 0x0000013d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1__VI = 0x0000013e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1__VI = 0x0000013f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2__VI = 0x00000140, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2__VI = 0x00000141, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2__VI = 0x00000142, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2__VI = 0x00000143, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2__VI = 0x00000144, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2__VI = 0x00000145, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2__VI = 0x00000146, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1__VI = 0x00000147, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1__VI = 0x00000148, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1__VI = 0x00000149, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1__VI = 0x0000014a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2__VI = 0x0000014b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2__VI = 0x0000014c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2__VI = 0x0000014d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2__VI = 0x0000014e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2__VI = 0x0000014f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2__VI = 0x00000150, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2__VI = 0x00000151, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1__VI = 0x00000152, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1__VI = 0x00000153, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1__VI = 0x00000154, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1__VI = 0x00000155, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1__VI = 0x00000156, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2__VI = 0x00000157, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3__VI = 0x00000158, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4__VI = 0x00000159, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5__VI = 0x0000015a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6__VI = 0x0000015b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0__VI = 0x0000015c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1__VI = 0x0000015d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1__VI = 0x0000015e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2__VI = 0x0000015f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3__VI = 0x00000160, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4__VI = 0x00000161, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5__VI = 0x00000162, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0__VI = 0x00000163, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1__VI = 0x00000164, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1__VI = 0x00000165, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1__VI = 0x00000166, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1__VI = 0x00000167, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1__VI = 0x00000168, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1__VI = 0x00000169, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1__VI = 0x0000016a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1__VI = 0x0000016b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1__VI = 0x0000016c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2__VI = 0x0000016d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2__VI = 0x0000016e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2__VI = 0x0000016f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2__VI = 0x00000170, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2__VI = 0x00000171, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2__VI = 0x00000172, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2__VI = 0x00000173, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1__VI = 0x00000174, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2__VI = 0x00000175, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3__VI = 0x00000176, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4__VI = 0x00000177, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5__VI = 0x00000178, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6__VI = 0x00000179, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7__VI = 0x0000017a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED__VI = 0x0000017b, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1__VI = 0x0000017c, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1__VI = 0x0000017d, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2__VI = 0x0000017e, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3__VI = 0x0000017f, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1__VI = 0x00000180, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2__VI = 0x00000181, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3__VI = 0x00000182, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4__VI = 0x00000183, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5__VI = 0x00000184, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1__VI = 0x00000185, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2__VI = 0x00000186, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3__VI = 0x00000187, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4__VI = 0x00000188, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5__VI = 0x00000189, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6__VI = 0x0000018a, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7__VI = 0x0000018b, - CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH__VI = 0x0000018c, - CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT__VI = 0x0000018d, - CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT__VI = 0x0000018e, - CB_PERF_SEL_RBP_SPLIT_MICROTILE__VI = 0x0000018f, - CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK__VI = 0x00000190, - CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK__VI = 0x00000191, - CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING__VI = 0x00000192, - CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS__VI = 0x00000193, - CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD__VI = 0x00000194, -} CBPerfSel; - -typedef enum CHUB_TC_RET_CREDITS_ENUM { - CHUB_TC_RET_CREDITS = 0x00000020, -} CHUB_TC_RET_CREDITS_ENUM; - -typedef enum CLKGATE_BASE_MODE { - MULT_8 = 0x00000000, - MULT_16 = 0x00000001, -} CLKGATE_BASE_MODE; - -typedef enum CLKGATE_SM_MODE { - ON_SEQ = 0x00000000, - OFF_SEQ = 0x00000001, - PROG_SEQ = 0x00000002, - READ_SEQ = 0x00000003, - SM_MODE_RESERVED = 0x00000004, -} CLKGATE_SM_MODE; - -typedef enum CPC_PERFCOUNT_SEL { - CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, - CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, - CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, - CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003, - CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004, - CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a, - CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, - CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, - CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012, - CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, - CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, - CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, - CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x00000016, - CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x00000017, - CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000018, -} CPC_PERFCOUNT_SEL; - -typedef enum CPF_PERFCOUNT_SEL { - CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, - CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001, - CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, - CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, - CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, - CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, - CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, - CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007, - CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008, - CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009, - CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, - CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, - CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, - CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, - CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, - CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f, - CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010, - CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x00000011, - CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x00000012, - CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000013, -} CPF_PERFCOUNT_SEL; - -typedef enum CPG_PERFCOUNT_SEL { - CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, - CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, - CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, - CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003, - CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, - CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, - CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, - CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, - CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008, - CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, - CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, - CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, - CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, - CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, - CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, - CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, - CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, - CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, - CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, - CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, - CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, - CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, - CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, - CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, - CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, - CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, - CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, - CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, - CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, - CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, - CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e, - CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, - CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, - CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, - CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022, - CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023, - CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, - CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, - CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, - CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, - CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028, - CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, - CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, - CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, - CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, - CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, - CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x0000002e, - CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x0000002f, - CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000030, -} CPG_PERFCOUNT_SEL; - -typedef enum CP_ALPHA_TAG_RAM_SEL { - CPG_TAG_RAM = 0x00000000, - CPC_TAG_RAM = 0x00000001, - CPF_TAG_RAM = 0x00000002, - RSV_TAG_RAM = 0x00000003, -} CP_ALPHA_TAG_RAM_SEL; - -typedef enum CP_ME_ID { - ME_ID0 = 0x00000000, - ME_ID1 = 0x00000001, - ME_ID2 = 0x00000002, - ME_ID3 = 0x00000003, -} CP_ME_ID; - -typedef enum CP_PERFCOUNT_SEL { - CP_PERF_SEL_ALWAYS_COUNT = 0x00000000, - CP_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, - CP_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, - CP_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003, - CP_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, - CP_PERF_SEL_ME_PARSER_BUSY = 0x00000005, - CP_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, - CP_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, - CP_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008, - CP_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, - CP_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, - CP_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, - CP_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, - CP_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, - CP_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, - CP_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, - CP_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, - CP_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, - CP_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, - CP_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, - CP_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, - CP_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, - CP_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, - CP_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, - CP_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, - CP_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, - CP_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, - CP_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, - CP_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, - CP_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, - CP_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e, - CP_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, - CP_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, - CP_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, - CP_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022, - CP_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023, - CP_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, - CP_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, - CP_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, - CP_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, - CP_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028, - CP_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, - CP_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, - CP_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, - CP_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, - CP_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, -} CP_PERFCOUNT_SEL; - -typedef enum CP_PERFMON_ENABLE_MODE { - CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, - CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, - CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, - CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, -} CP_PERFMON_ENABLE_MODE; - -typedef enum CP_PERFMON_STATE { - CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, - CP_PERFMON_STATE_START_COUNTING = 0x00000001, - CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, - CP_PERFMON_STATE_RESERVED_3 = 0x00000003, - CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, - CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} CP_PERFMON_STATE; - -typedef enum CP_PIPE_ID { - PIPE_ID0 = 0x00000000, - PIPE_ID1 = 0x00000001, - PIPE_ID2 = 0x00000002, - PIPE_ID3 = 0x00000003, -} CP_PIPE_ID; - -typedef enum CP_RING_ID { - RINGID0 = 0x00000000, - RINGID1 = 0x00000001, - RINGID2 = 0x00000002, - RINGID3__CI__VI = 0x00000003, -} CP_RING_ID; - -typedef enum CSDATA_TYPE { - CSDATA_TYPE_TG = 0x00000000, - CSDATA_TYPE_STATE = 0x00000001, - CSDATA_TYPE_EVENT = 0x00000002, - CSDATA_TYPE_PRIVATE = 0x00000003, -} CSDATA_TYPE; - -typedef enum CmaskCode { - CMASK_CLR00_F0 = 0x00000000, - CMASK_CLR00_F1 = 0x00000001, - CMASK_CLR00_F2 = 0x00000002, - CMASK_CLR00_FX = 0x00000003, - CMASK_CLR01_F0 = 0x00000004, - CMASK_CLR01_F1 = 0x00000005, - CMASK_CLR01_F2 = 0x00000006, - CMASK_CLR01_FX = 0x00000007, - CMASK_CLR10_F0 = 0x00000008, - CMASK_CLR10_F1 = 0x00000009, - CMASK_CLR10_F2 = 0x0000000a, - CMASK_CLR10_FX = 0x0000000b, - CMASK_CLR11_F0 = 0x0000000c, - CMASK_CLR11_F1 = 0x0000000d, - CMASK_CLR11_F2 = 0x0000000e, - CMASK_CLR11_FX = 0x0000000f, -} CmaskCode; - -typedef enum CmaskMode { - CMASK_CLEAR_NONE = 0x00000000, - CMASK_CLEAR_ONE = 0x00000001, - CMASK_CLEAR_ALL = 0x00000002, - CMASK_ANY_EXPANDED = 0x00000003, - CMASK_ALPHA0_FRAG1 = 0x00000004, - CMASK_ALPHA0_FRAG2 = 0x00000005, - CMASK_ALPHA0_FRAG4 = 0x00000006, - CMASK_ALPHA0_FRAGS = 0x00000007, - CMASK_ALPHA1_FRAG1 = 0x00000008, - CMASK_ALPHA1_FRAG2 = 0x00000009, - CMASK_ALPHA1_FRAG4 = 0x0000000a, - CMASK_ALPHA1_FRAGS = 0x0000000b, - CMASK_ALPHAX_FRAG1 = 0x0000000c, - CMASK_ALPHAX_FRAG2 = 0x0000000d, - CMASK_ALPHAX_FRAG4 = 0x0000000e, - CMASK_ALPHAX_FRAGS = 0x0000000f, -} CmaskMode; - -typedef enum ColorArray { - ARRAY_2D_ALT_COLOR = 0x00000000, - ARRAY_2D_COLOR = 0x00000001, - ARRAY_3D_SLICE_COLOR = 0x00000003, -} ColorArray; - -typedef enum ColorFormat { - COLOR_INVALID = 0x00000000, - COLOR_8 = 0x00000001, - COLOR_16 = 0x00000002, - COLOR_8_8 = 0x00000003, - COLOR_32 = 0x00000004, - COLOR_16_16 = 0x00000005, - COLOR_10_11_11 = 0x00000006, - COLOR_11_11_10 = 0x00000007, - COLOR_10_10_10_2 = 0x00000008, - COLOR_2_10_10_10 = 0x00000009, - COLOR_8_8_8_8 = 0x0000000a, - COLOR_32_32 = 0x0000000b, - COLOR_16_16_16_16 = 0x0000000c, - COLOR_RESERVED_13 = 0x0000000d, - COLOR_32_32_32_32 = 0x0000000e, - COLOR_RESERVED_15 = 0x0000000f, - COLOR_5_6_5 = 0x00000010, - COLOR_1_5_5_5 = 0x00000011, - COLOR_5_5_5_1 = 0x00000012, - COLOR_4_4_4_4 = 0x00000013, - COLOR_8_24 = 0x00000014, - COLOR_24_8 = 0x00000015, - COLOR_X24_8_32_FLOAT = 0x00000016, - COLOR_RESERVED_23 = 0x00000017, -} ColorFormat; - -typedef enum CombFunc { - COMB_DST_PLUS_SRC = 0x00000000, - COMB_SRC_MINUS_DST = 0x00000001, - COMB_MIN_DST_SRC = 0x00000002, - COMB_MAX_DST_SRC = 0x00000003, - COMB_DST_MINUS_SRC = 0x00000004, -} CombFunc; - -typedef enum CompareFrag { - FRAG_NEVER = 0x00000000, - FRAG_LESS = 0x00000001, - FRAG_EQUAL = 0x00000002, - FRAG_LEQUAL = 0x00000003, - FRAG_GREATER = 0x00000004, - FRAG_NOTEQUAL = 0x00000005, - FRAG_GEQUAL = 0x00000006, - FRAG_ALWAYS = 0x00000007, -} CompareFrag; - -typedef enum CompareRef { - REF_NEVER = 0x00000000, - REF_LESS = 0x00000001, - REF_EQUAL = 0x00000002, - REF_LEQUAL = 0x00000003, - REF_GREATER = 0x00000004, - REF_NOTEQUAL = 0x00000005, - REF_GEQUAL = 0x00000006, - REF_ALWAYS = 0x00000007, -} CompareRef; - -typedef enum ConservativeZExport { - EXPORT_ANY_Z = 0x00000000, - EXPORT_LESS_THAN_Z = 0x00000001, - EXPORT_GREATER_THAN_Z = 0x00000002, - EXPORT_RESERVED = 0x00000003, -} ConservativeZExport; - -typedef enum DRMDMA_PERF_SEL { - DRMDMA_PERF_CYCLE = 0x00000000, - DRMDMA_PERF_IDLE = 0x00000001, - DRMDMA_PERF_REG_IDLE = 0x00000002, - DRMDMA_PERF_RB_EMPTY = 0x00000003, - DRMDMA_PERF_RB_FULL = 0x00000004, - DRMDMA_PERF_RB_WPTR_WRAP = 0x00000005, - DRMDMA_PERF_RB_RPTR_WRAP = 0x00000006, - DRMDMA_PERF_RB_WPTR_POLL_READ = 0x00000007, - DRMDMA_PERF_RB_RPTR_WB = 0x00000008, - DRMDMA_PERF_RB_CMD_IDLE = 0x00000009, - DRMDMA_PERF_RB_CMD_FULL = 0x0000000a, - DRMDMA_PERF_IB_CMD_IDLE = 0x0000000b, - DRMDMA_PERF_IB_CMD_FULL = 0x0000000c, - DRMDMA_PERF_RD_DATA_IDLE = 0x0000000d, - DRMDMA_PERF_RD_DATA_FULL = 0x0000000e, - DRMDMA_PERF_EX_IDLE = 0x0000000f, - DRMDMA_PERF_EX_CMD_IDLE = 0x00000010, - DRMDMA_PERF_EX_WRITE_COMBINE = 0x00000011, - DRMDMA_PERF_EX_IDLE_POLL_TIMER_EXPIRE = 0x00000012, - DRMDMA_PERF_TILE_IDLE = 0x00000013, - DRMDMA_PERF_MC_WR_IDLE = 0x00000014, - DRMDMA_PERF_MC_WR_AFIFO_EMPTY = 0x00000015, - DRMDMA_PERF_MC_WR_AFIFO_FULL = 0x00000016, - DRMDMA_PERF_MC_WR_DFIFO_EMPTY = 0x00000017, - DRMDMA_PERF_MC_WR_DFIFO_FULL = 0x00000018, - DRMDMA_PERF_MC_WR_COUNT = 0x00000019, - DRMDMA_PERF_MC_WR_STALL = 0x0000001a, - DRMDMA_PERF_MC_WR_CLEAN_PENDING = 0x0000001b, - DRMDMA_PERF_MC_WR_CLEAN_STALL = 0x0000001c, - DRMDMA_PERF_MC_RD_IDLE = 0x0000001d, - DRMDMA_PERF_MC_RD_COUNT = 0x0000001e, - DRMDMA_PERF_MC_RD_STALL = 0x0000001f, - DRMDMA_PERF_MC_RD_RET_STALL = 0x00000020, - DRMDMA_PERF_MC_RD_NO_POLL_IDLE = 0x00000021, - DRMDMA_PERF_DRM_IDLE = 0x00000022, - DRMDMA_PERF_DRM_MASK_FULL = 0x00000023, - DRMDMA_PERF_DRM_REQ_STALL = 0x00000024, - DRMDMA_PERF_SEM_IDLE = 0x00000025, - DRMDMA_PERF_SEM_REQ_STALL = 0x00000026, - DRMDMA_PERF_SEM_REQ_COUNT = 0x00000027, - DRMDMA_PERF_SEM_RESP_INCOMPLETE = 0x00000028, - DRMDMA_PERF_SEM_RESP_FAIL = 0x00000029, - DRMDMA_PERF_SEM_RESP_PASS = 0x0000002a, - DRMDMA_PERF_INT_IDLE = 0x0000002b, - DRMDMA_PERF_INT_REQ_STALL = 0x0000002c, - DRMDMA_PERF_INT_REQ_COUNT = 0x0000002d, - DRMDMA_PERF_INT_RESP_ACCEPTED = 0x0000002e, - DRMDMA_PERF_INT_RESP_RETRY = 0x0000002f, - DRMDMA_PERF_NUM_PACKET = 0x00000030, - DRMDMA_PERF_VMC_REQ_COUNT = 0x00000031, - DRMDMA_PERF_VMC_RESP_FAIL = 0x00000032, - DRMDMA_PERF_VMC_RESP_PASS = 0x00000033, - DRMDMA_PERF_DRM1_IDLE = 0x00000034, - DRMDMA_PERF_DRM1_MASK_FULL = 0x00000035, - DRMDMA_PERF_DRM1_REQ_STALL = 0x00000036, -} DRMDMA_PERF_SEL; - -typedef enum DbPSLControl { - PSLC_AUTO = 0x00000000, - PSLC_ON_HANG_ONLY = 0x00000001, - PSLC_ASAP = 0x00000002, - PSLC_COUNTDOWN = 0x00000003, -} DbPSLControl; - -typedef enum DebugBlockId { - DBG_BLOCK_ID_RESERVED = 0x00000000, - DBG_BLOCK_ID_DBG = 0x00000001, - DBG_BLOCK_ID_VMC = 0x00000002, - DBG_BLOCK_ID_PDMA = 0x00000003, - DBG_BLOCK_ID_CG = 0x00000004, - DBG_BLOCK_ID_SRBM = 0x00000005, - DBG_BLOCK_ID_GRBM = 0x00000006, - DBG_BLOCK_ID_RLC = 0x00000007, - DBG_BLOCK_ID_CSC = 0x00000008, - DBG_BLOCK_ID_SEM = 0x00000009, - DBG_BLOCK_ID_IH = 0x0000000a, - DBG_BLOCK_ID_SC = 0x0000000b, - DBG_BLOCK_ID_SQ = 0x0000000c, - DBG_BLOCK_ID_AVP = 0x0000000d, - DBG_BLOCK_ID_GMCON = 0x0000000e, - DBG_BLOCK_ID_SMU = 0x0000000f, - DBG_BLOCK_ID_DRMDMA0 = 0x00000010, - DBG_BLOCK_ID_DRMDMA1 = 0x00000011, - DBG_BLOCK_ID_SPIM = 0x00000012, - DBG_BLOCK_ID_GDS = 0x00000013, - DBG_BLOCK_ID_SPIS = 0x00000014, - DBG_BLOCK_ID_UNUSED0 = 0x00000015, - DBG_BLOCK_ID_PA0 = 0x00000016, - DBG_BLOCK_ID_PA1 = 0x00000017, - DBG_BLOCK_ID_CP0 = 0x00000018, - DBG_BLOCK_ID_CP1 = 0x00000019, - DBG_BLOCK_ID_CP2 = 0x0000001a, - DBG_BLOCK_ID_UNUSED1 = 0x0000001b, - DBG_BLOCK_ID_UVDU = 0x0000001c, - DBG_BLOCK_ID_UVDM = 0x0000001d, - DBG_BLOCK_ID_VCE = 0x0000001e, - DBG_BLOCK_ID_UNUSED2 = 0x0000001f, - DBG_BLOCK_ID_VGT0 = 0x00000020, - DBG_BLOCK_ID_VGT1 = 0x00000021, - DBG_BLOCK_ID_IA = 0x00000022, - DBG_BLOCK_ID_UNUSED3 = 0x00000023, - DBG_BLOCK_ID_SCT0 = 0x00000024, - DBG_BLOCK_ID_SCT1 = 0x00000025, - DBG_BLOCK_ID_SPM0 = 0x00000026, - DBG_BLOCK_ID_SPM1 = 0x00000027, - DBG_BLOCK_ID_TCAA = 0x00000028, - DBG_BLOCK_ID_TCAB = 0x00000029, - DBG_BLOCK_ID_TCCA = 0x0000002a, - DBG_BLOCK_ID_TCCB = 0x0000002b, - DBG_BLOCK_ID_MCC0 = 0x0000002c, - DBG_BLOCK_ID_MCC1 = 0x0000002d, - DBG_BLOCK_ID_MCC2 = 0x0000002e, - DBG_BLOCK_ID_MCC3 = 0x0000002f, - DBG_BLOCK_ID_SX0 = 0x00000030, - DBG_BLOCK_ID_SX1 = 0x00000031, - DBG_BLOCK_ID_SX2 = 0x00000032, - DBG_BLOCK_ID_SX3 = 0x00000033, - DBG_BLOCK_ID_UNUSED4 = 0x00000034, - DBG_BLOCK_ID_UNUSED5 = 0x00000035, - DBG_BLOCK_ID_UNUSED6 = 0x00000036, - DBG_BLOCK_ID_UNUSED7 = 0x00000037, - DBG_BLOCK_ID_PC0 = 0x00000038, - DBG_BLOCK_ID_PC1 = 0x00000039, - DBG_BLOCK_ID_UNUSED8 = 0x0000003a, - DBG_BLOCK_ID_UNUSED9 = 0x0000003b, - DBG_BLOCK_ID_UNUSED10 = 0x0000003c, - DBG_BLOCK_ID_UNUSED11 = 0x0000003d, - DBG_BLOCK_ID_MCB = 0x0000003e, - DBG_BLOCK_ID_UNUSED12 = 0x0000003f, - DBG_BLOCK_ID_SCB0 = 0x00000040, - DBG_BLOCK_ID_SCB1 = 0x00000041, - DBG_BLOCK_ID_UNUSED13 = 0x00000042, - DBG_BLOCK_ID_UNUSED14 = 0x00000043, - DBG_BLOCK_ID_SCF0 = 0x00000044, - DBG_BLOCK_ID_SCF1 = 0x00000045, - DBG_BLOCK_ID_UNUSED15 = 0x00000046, - DBG_BLOCK_ID_UNUSED16 = 0x00000047, - DBG_BLOCK_ID_BCI0 = 0x00000048, - DBG_BLOCK_ID_BCI1 = 0x00000049, - DBG_BLOCK_ID_BCI2 = 0x0000004a, - DBG_BLOCK_ID_BCI3 = 0x0000004b, - DBG_BLOCK_ID_UNUSED17 = 0x0000004c, - DBG_BLOCK_ID_UNUSED18 = 0x0000004d, - DBG_BLOCK_ID_UNUSED19 = 0x0000004e, - DBG_BLOCK_ID_UNUSED20 = 0x0000004f, - DBG_BLOCK_ID_CB00 = 0x00000050, - DBG_BLOCK_ID_CB01 = 0x00000051, - DBG_BLOCK_ID_CB02 = 0x00000052, - DBG_BLOCK_ID_CB03 = 0x00000053, - DBG_BLOCK_ID_CB04 = 0x00000054, - DBG_BLOCK_ID_UNUSED21 = 0x00000055, - DBG_BLOCK_ID_UNUSED22 = 0x00000056, - DBG_BLOCK_ID_UNUSED23 = 0x00000057, - DBG_BLOCK_ID_CB10 = 0x00000058, - DBG_BLOCK_ID_CB11 = 0x00000059, - DBG_BLOCK_ID_CB12 = 0x0000005a, - DBG_BLOCK_ID_CB13 = 0x0000005b, - DBG_BLOCK_ID_CB14 = 0x0000005c, - DBG_BLOCK_ID_UNUSED24 = 0x0000005d, - DBG_BLOCK_ID_UNUSED25 = 0x0000005e, - DBG_BLOCK_ID_UNUSED26 = 0x0000005f, - DBG_BLOCK_ID_TCP0 = 0x00000060, - DBG_BLOCK_ID_TCP1 = 0x00000061, - DBG_BLOCK_ID_TCP2 = 0x00000062, - DBG_BLOCK_ID_TCP3 = 0x00000063, - DBG_BLOCK_ID_TCP4 = 0x00000064, - DBG_BLOCK_ID_TCP5 = 0x00000065, - DBG_BLOCK_ID_TCP6 = 0x00000066, - DBG_BLOCK_ID_TCP7 = 0x00000067, - DBG_BLOCK_ID_TCP8 = 0x00000068, - DBG_BLOCK_ID_TCP9 = 0x00000069, - DBG_BLOCK_ID_TCP10 = 0x0000006a, - DBG_BLOCK_ID_TCP11 = 0x0000006b, - DBG_BLOCK_ID_TCP12 = 0x0000006c, - DBG_BLOCK_ID_TCP13 = 0x0000006d, - DBG_BLOCK_ID_TCP14 = 0x0000006e, - DBG_BLOCK_ID_TCP15 = 0x0000006f, - DBG_BLOCK_ID_TCP16 = 0x00000070, - DBG_BLOCK_ID_TCP17 = 0x00000071, - DBG_BLOCK_ID_TCP18 = 0x00000072, - DBG_BLOCK_ID_TCP19 = 0x00000073, - DBG_BLOCK_ID_TCP20 = 0x00000074, - DBG_BLOCK_ID_TCP21 = 0x00000075, - DBG_BLOCK_ID_TCP22 = 0x00000076, - DBG_BLOCK_ID_TCP23 = 0x00000077, - DBG_BLOCK_ID_TCP_RESERVED0 = 0x00000078, - DBG_BLOCK_ID_TCP_RESERVED1 = 0x00000079, - DBG_BLOCK_ID_TCP_RESERVED2 = 0x0000007a, - DBG_BLOCK_ID_TCP_RESERVED3 = 0x0000007b, - DBG_BLOCK_ID_TCP_RESERVED4 = 0x0000007c, - DBG_BLOCK_ID_TCP_RESERVED5 = 0x0000007d, - DBG_BLOCK_ID_TCP_RESERVED6 = 0x0000007e, - DBG_BLOCK_ID_TCP_RESERVED7 = 0x0000007f, - DBG_BLOCK_ID_DB00 = 0x00000080, - DBG_BLOCK_ID_DB01 = 0x00000081, - DBG_BLOCK_ID_DB02 = 0x00000082, - DBG_BLOCK_ID_DB03 = 0x00000083, - DBG_BLOCK_ID_DB04 = 0x00000084, - DBG_BLOCK_ID_UNUSED27 = 0x00000085, - DBG_BLOCK_ID_UNUSED28 = 0x00000086, - DBG_BLOCK_ID_UNUSED29 = 0x00000087, - DBG_BLOCK_ID_DB10 = 0x00000088, - DBG_BLOCK_ID_DB11 = 0x00000089, - DBG_BLOCK_ID_DB12 = 0x0000008a, - DBG_BLOCK_ID_DB13 = 0x0000008b, - DBG_BLOCK_ID_DB14 = 0x0000008c, - DBG_BLOCK_ID_UNUSED30 = 0x0000008d, - DBG_BLOCK_ID_UNUSED31 = 0x0000008e, - DBG_BLOCK_ID_UNUSED32 = 0x0000008f, - DBG_BLOCK_ID_TCC0 = 0x00000090, - DBG_BLOCK_ID_TCC1 = 0x00000091, - DBG_BLOCK_ID_TCC2 = 0x00000092, - DBG_BLOCK_ID_TCC3 = 0x00000093, - DBG_BLOCK_ID_TCC4 = 0x00000094, - DBG_BLOCK_ID_TCC5 = 0x00000095, - DBG_BLOCK_ID_TCC6 = 0x00000096, - DBG_BLOCK_ID_TCC7 = 0x00000097, - DBG_BLOCK_ID_SPS00 = 0x00000098, - DBG_BLOCK_ID_SPS01 = 0x00000099, - DBG_BLOCK_ID_SPS02 = 0x0000009a, - DBG_BLOCK_ID_SPS10 = 0x0000009b, - DBG_BLOCK_ID_SPS11 = 0x0000009c, - DBG_BLOCK_ID_SPS12 = 0x0000009d, - DBG_BLOCK_ID_UNUSED33 = 0x0000009e, - DBG_BLOCK_ID_UNUSED34 = 0x0000009f, - DBG_BLOCK_ID_TA00 = 0x000000a0, - DBG_BLOCK_ID_TA01 = 0x000000a1, - DBG_BLOCK_ID_TA02 = 0x000000a2, - DBG_BLOCK_ID_TA03 = 0x000000a3, - DBG_BLOCK_ID_TA04 = 0x000000a4, - DBG_BLOCK_ID_TA05 = 0x000000a5, - DBG_BLOCK_ID_TA06 = 0x000000a6, - DBG_BLOCK_ID_TA07 = 0x000000a7, - DBG_BLOCK_ID_TA08 = 0x000000a8, - DBG_BLOCK_ID_TA09 = 0x000000a9, - DBG_BLOCK_ID_TA0A = 0x000000aa, - DBG_BLOCK_ID_TA0B = 0x000000ab, - DBG_BLOCK_ID_UNUSED35 = 0x000000ac, - DBG_BLOCK_ID_UNUSED36 = 0x000000ad, - DBG_BLOCK_ID_UNUSED37 = 0x000000ae, - DBG_BLOCK_ID_UNUSED38 = 0x000000af, - DBG_BLOCK_ID_TA10 = 0x000000b0, - DBG_BLOCK_ID_TA11 = 0x000000b1, - DBG_BLOCK_ID_TA12 = 0x000000b2, - DBG_BLOCK_ID_TA13 = 0x000000b3, - DBG_BLOCK_ID_TA14 = 0x000000b4, - DBG_BLOCK_ID_TA15 = 0x000000b5, - DBG_BLOCK_ID_TA16 = 0x000000b6, - DBG_BLOCK_ID_TA17 = 0x000000b7, - DBG_BLOCK_ID_TA18 = 0x000000b8, - DBG_BLOCK_ID_TA19 = 0x000000b9, - DBG_BLOCK_ID_TA1A = 0x000000ba, - DBG_BLOCK_ID_TA1B = 0x000000bb, - DBG_BLOCK_ID_UNUSED39 = 0x000000bc, - DBG_BLOCK_ID_UNUSED40 = 0x000000bd, - DBG_BLOCK_ID_UNUSED41 = 0x000000be, - DBG_BLOCK_ID_UNUSED42 = 0x000000bf, - DBG_BLOCK_ID_TD00 = 0x000000c0, - DBG_BLOCK_ID_TD01 = 0x000000c1, - DBG_BLOCK_ID_TD02 = 0x000000c2, - DBG_BLOCK_ID_TD03 = 0x000000c3, - DBG_BLOCK_ID_TD04 = 0x000000c4, - DBG_BLOCK_ID_TD05 = 0x000000c5, - DBG_BLOCK_ID_TD06 = 0x000000c6, - DBG_BLOCK_ID_TD07 = 0x000000c7, - DBG_BLOCK_ID_TD08 = 0x000000c8, - DBG_BLOCK_ID_TD09 = 0x000000c9, - DBG_BLOCK_ID_TD0A = 0x000000ca, - DBG_BLOCK_ID_TD0B = 0x000000cb, - DBG_BLOCK_ID_UNUSED43 = 0x000000cc, - DBG_BLOCK_ID_UNUSED44 = 0x000000cd, - DBG_BLOCK_ID_UNUSED45 = 0x000000ce, - DBG_BLOCK_ID_UNUSED46 = 0x000000cf, - DBG_BLOCK_ID_TD10 = 0x000000d0, - DBG_BLOCK_ID_TD11 = 0x000000d1, - DBG_BLOCK_ID_TD12 = 0x000000d2, - DBG_BLOCK_ID_TD13 = 0x000000d3, - DBG_BLOCK_ID_TD14 = 0x000000d4, - DBG_BLOCK_ID_TD15 = 0x000000d5, - DBG_BLOCK_ID_TD16 = 0x000000d6, - DBG_BLOCK_ID_TD17 = 0x000000d7, - DBG_BLOCK_ID_TD18 = 0x000000d8, - DBG_BLOCK_ID_TD19 = 0x000000d9, - DBG_BLOCK_ID_TD1A = 0x000000da, - DBG_BLOCK_ID_TD1B = 0x000000db, - DBG_BLOCK_ID_UNUSED47 = 0x000000dc, - DBG_BLOCK_ID_UNUSED48 = 0x000000dd, - DBG_BLOCK_ID_UNUSED49 = 0x000000de, - DBG_BLOCK_ID_UNUSED50 = 0x000000df, - DBG_BLOCK_ID_MCD0 = 0x000000e0, - DBG_BLOCK_ID_MCD1 = 0x000000e1, - DBG_BLOCK_ID_MCD2 = 0x000000e2, - DBG_BLOCK_ID_MCD3 = 0x000000e3, - DBG_BLOCK_ID_MCD4 = 0x000000e4, - DBG_BLOCK_ID_MCD5 = 0x000000e5, - DBG_BLOCK_ID_UNUSED51 = 0x000000e6, - DBG_BLOCK_ID_UNUSED52 = 0x000000e7, -} DebugBlockId; - -typedef enum DebugBlockId_BY16 { - DBG_BLOCK_ID_RESERVED_BY16 = 0x00000000, - DBG_BLOCK_ID_DRMDMA0_BY16 = 0x00000001, - DBG_BLOCK_ID_VGT0_BY16 = 0x00000002, - DBG_BLOCK_ID_SX0_BY16 = 0x00000003, - DBG_BLOCK_ID_SCB0_BY16 = 0x00000004, - DBG_BLOCK_ID_CB00_BY16 = 0x00000005, - DBG_BLOCK_ID_TCP0_BY16 = 0x00000006, - DBG_BLOCK_ID_TCP16_BY16 = 0x00000007, - DBG_BLOCK_ID_DB00_BY16 = 0x00000008, - DBG_BLOCK_ID_TCC0_BY16 = 0x00000009, - DBG_BLOCK_ID_TA00_BY16 = 0x0000000a, - DBG_BLOCK_ID_TA10_BY16 = 0x0000000b, - DBG_BLOCK_ID_TD00_BY16 = 0x0000000c, - DBG_BLOCK_ID_TD10_BY16 = 0x0000000d, - DBG_BLOCK_ID_MCD0_BY16 = 0x0000000e, -} DebugBlockId_BY16; - -typedef enum DebugBlockId_BY2 { - DBG_BLOCK_ID_RESERVED_BY2 = 0x00000000, - DBG_BLOCK_ID_VMC_BY2 = 0x00000001, - DBG_BLOCK_ID_CG_BY2 = 0x00000002, - DBG_BLOCK_ID_GRBM_BY2 = 0x00000003, - DBG_BLOCK_ID_CSC_BY2 = 0x00000004, - DBG_BLOCK_ID_IH_BY2 = 0x00000005, - DBG_BLOCK_ID_SQ_BY2 = 0x00000006, - DBG_BLOCK_ID_GMCON_BY2 = 0x00000007, - DBG_BLOCK_ID_DRMDMA0_BY2 = 0x00000008, - DBG_BLOCK_ID_SPIM_BY2 = 0x00000009, - DBG_BLOCK_ID_SPIS_BY2 = 0x0000000a, - DBG_BLOCK_ID_PA0_BY2 = 0x0000000b, - DBG_BLOCK_ID_CP0_BY2 = 0x0000000c, - DBG_BLOCK_ID_CP2_BY2 = 0x0000000d, - DBG_BLOCK_ID_UVDU_BY2 = 0x0000000e, - DBG_BLOCK_ID_VCE_BY2 = 0x0000000f, - DBG_BLOCK_ID_VGT0_BY2 = 0x00000010, - DBG_BLOCK_ID_IA_BY2 = 0x00000011, - DBG_BLOCK_ID_SCT0_BY2 = 0x00000012, - DBG_BLOCK_ID_SPM0_BY2 = 0x00000013, - DBG_BLOCK_ID_TCAA_BY2 = 0x00000014, - DBG_BLOCK_ID_TCCA_BY2 = 0x00000015, - DBG_BLOCK_ID_MCC0_BY2 = 0x00000016, - DBG_BLOCK_ID_MCC2_BY2 = 0x00000017, - DBG_BLOCK_ID_SX0_BY2 = 0x00000018, - DBG_BLOCK_ID_SX2_BY2 = 0x00000019, - DBG_BLOCK_ID_UNUSED4_BY2 = 0x0000001a, - DBG_BLOCK_ID_UNUSED6_BY2 = 0x0000001b, - DBG_BLOCK_ID_PC0_BY2 = 0x0000001c, - DBG_BLOCK_ID_UNUSED8_BY2 = 0x0000001d, - DBG_BLOCK_ID_UNUSED10_BY2 = 0x0000001e, - DBG_BLOCK_ID_MCB_BY2 = 0x0000001f, - DBG_BLOCK_ID_SCB0_BY2 = 0x00000020, - DBG_BLOCK_ID_UNUSED13_BY2 = 0x00000021, - DBG_BLOCK_ID_SCF0_BY2 = 0x00000022, - DBG_BLOCK_ID_UNUSED15_BY2 = 0x00000023, - DBG_BLOCK_ID_BCI0_BY2 = 0x00000024, - DBG_BLOCK_ID_BCI2_BY2 = 0x00000025, - DBG_BLOCK_ID_UNUSED17_BY2 = 0x00000026, - DBG_BLOCK_ID_UNUSED19_BY2 = 0x00000027, - DBG_BLOCK_ID_CB00_BY2 = 0x00000028, - DBG_BLOCK_ID_CB02_BY2 = 0x00000029, - DBG_BLOCK_ID_CB04_BY2 = 0x0000002a, - DBG_BLOCK_ID_UNUSED22_BY2 = 0x0000002b, - DBG_BLOCK_ID_CB10_BY2 = 0x0000002c, - DBG_BLOCK_ID_CB12_BY2 = 0x0000002d, - DBG_BLOCK_ID_CB14_BY2 = 0x0000002e, - DBG_BLOCK_ID_UNUSED25_BY2 = 0x0000002f, - DBG_BLOCK_ID_TCP0_BY2 = 0x00000030, - DBG_BLOCK_ID_TCP2_BY2 = 0x00000031, - DBG_BLOCK_ID_TCP4_BY2 = 0x00000032, - DBG_BLOCK_ID_TCP6_BY2 = 0x00000033, - DBG_BLOCK_ID_TCP8_BY2 = 0x00000034, - DBG_BLOCK_ID_TCP10_BY2 = 0x00000035, - DBG_BLOCK_ID_TCP12_BY2 = 0x00000036, - DBG_BLOCK_ID_TCP14_BY2 = 0x00000037, - DBG_BLOCK_ID_TCP16_BY2 = 0x00000038, - DBG_BLOCK_ID_TCP18_BY2 = 0x00000039, - DBG_BLOCK_ID_TCP20_BY2 = 0x0000003a, - DBG_BLOCK_ID_TCP22_BY2 = 0x0000003b, - DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x0000003c, - DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x0000003d, - DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x0000003e, - DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x0000003f, - DBG_BLOCK_ID_DB00_BY2 = 0x00000040, - DBG_BLOCK_ID_DB02_BY2 = 0x00000041, - DBG_BLOCK_ID_DB04_BY2 = 0x00000042, - DBG_BLOCK_ID_UNUSED28_BY2 = 0x00000043, - DBG_BLOCK_ID_DB10_BY2 = 0x00000044, - DBG_BLOCK_ID_DB12_BY2 = 0x00000045, - DBG_BLOCK_ID_DB14_BY2 = 0x00000046, - DBG_BLOCK_ID_UNUSED31_BY2 = 0x00000047, - DBG_BLOCK_ID_TCC0_BY2 = 0x00000048, - DBG_BLOCK_ID_TCC2_BY2 = 0x00000049, - DBG_BLOCK_ID_TCC4_BY2 = 0x0000004a, - DBG_BLOCK_ID_TCC6_BY2 = 0x0000004b, - DBG_BLOCK_ID_SPS00_BY2 = 0x0000004c, - DBG_BLOCK_ID_SPS02_BY2 = 0x0000004d, - DBG_BLOCK_ID_SPS11_BY2 = 0x0000004e, - DBG_BLOCK_ID_UNUSED33_BY2 = 0x0000004f, - DBG_BLOCK_ID_TA00_BY2 = 0x00000050, - DBG_BLOCK_ID_TA02_BY2 = 0x00000051, - DBG_BLOCK_ID_TA04_BY2 = 0x00000052, - DBG_BLOCK_ID_TA06_BY2 = 0x00000053, - DBG_BLOCK_ID_TA08_BY2 = 0x00000054, - DBG_BLOCK_ID_TA0A_BY2 = 0x00000055, - DBG_BLOCK_ID_UNUSED35_BY2 = 0x00000056, - DBG_BLOCK_ID_UNUSED37_BY2 = 0x00000057, - DBG_BLOCK_ID_TA10_BY2 = 0x00000058, - DBG_BLOCK_ID_TA12_BY2 = 0x00000059, - DBG_BLOCK_ID_TA14_BY2 = 0x0000005a, - DBG_BLOCK_ID_TA16_BY2 = 0x0000005b, - DBG_BLOCK_ID_TA18_BY2 = 0x0000005c, - DBG_BLOCK_ID_TA1A_BY2 = 0x0000005d, - DBG_BLOCK_ID_UNUSED39_BY2 = 0x0000005e, - DBG_BLOCK_ID_UNUSED41_BY2 = 0x0000005f, - DBG_BLOCK_ID_TD00_BY2 = 0x00000060, - DBG_BLOCK_ID_TD02_BY2 = 0x00000061, - DBG_BLOCK_ID_TD04_BY2 = 0x00000062, - DBG_BLOCK_ID_TD06_BY2 = 0x00000063, - DBG_BLOCK_ID_TD08_BY2 = 0x00000064, - DBG_BLOCK_ID_TD0A_BY2 = 0x00000065, - DBG_BLOCK_ID_UNUSED43_BY2 = 0x00000066, - DBG_BLOCK_ID_UNUSED45_BY2 = 0x00000067, - DBG_BLOCK_ID_TD10_BY2 = 0x00000068, - DBG_BLOCK_ID_TD12_BY2 = 0x00000069, - DBG_BLOCK_ID_TD14_BY2 = 0x0000006a, - DBG_BLOCK_ID_TD16_BY2 = 0x0000006b, - DBG_BLOCK_ID_TD18_BY2 = 0x0000006c, - DBG_BLOCK_ID_TD1A_BY2 = 0x0000006d, - DBG_BLOCK_ID_UNUSED47_BY2 = 0x0000006e, - DBG_BLOCK_ID_UNUSED49_BY2 = 0x0000006f, - DBG_BLOCK_ID_MCD0_BY2 = 0x00000070, - DBG_BLOCK_ID_MCD2_BY2 = 0x00000071, - DBG_BLOCK_ID_MCD4_BY2 = 0x00000072, - DBG_BLOCK_ID_UNUSED51_BY2 = 0x00000073, -} DebugBlockId_BY2; - -typedef enum DebugBlockId_BY4 { - DBG_BLOCK_ID_RESERVED_BY4 = 0x00000000, - DBG_BLOCK_ID_CG_BY4 = 0x00000001, - DBG_BLOCK_ID_CSC_BY4 = 0x00000002, - DBG_BLOCK_ID_SQ_BY4 = 0x00000003, - DBG_BLOCK_ID_DRMDMA0_BY4 = 0x00000004, - DBG_BLOCK_ID_SPIS_BY4 = 0x00000005, - DBG_BLOCK_ID_CP0_BY4 = 0x00000006, - DBG_BLOCK_ID_UVDU_BY4 = 0x00000007, - DBG_BLOCK_ID_VGT0_BY4 = 0x00000008, - DBG_BLOCK_ID_SCT0_BY4 = 0x00000009, - DBG_BLOCK_ID_TCAA_BY4 = 0x0000000a, - DBG_BLOCK_ID_MCC0_BY4 = 0x0000000b, - DBG_BLOCK_ID_SX0_BY4 = 0x0000000c, - DBG_BLOCK_ID_UNUSED4_BY4 = 0x0000000d, - DBG_BLOCK_ID_PC0_BY4 = 0x0000000e, - DBG_BLOCK_ID_UNUSED10_BY4 = 0x0000000f, - DBG_BLOCK_ID_SCB0_BY4 = 0x00000010, - DBG_BLOCK_ID_SCF0_BY4 = 0x00000011, - DBG_BLOCK_ID_BCI0_BY4 = 0x00000012, - DBG_BLOCK_ID_UNUSED17_BY4 = 0x00000013, - DBG_BLOCK_ID_CB00_BY4 = 0x00000014, - DBG_BLOCK_ID_CB04_BY4 = 0x00000015, - DBG_BLOCK_ID_CB10_BY4 = 0x00000016, - DBG_BLOCK_ID_CB14_BY4 = 0x00000017, - DBG_BLOCK_ID_TCP0_BY4 = 0x00000018, - DBG_BLOCK_ID_TCP4_BY4 = 0x00000019, - DBG_BLOCK_ID_TCP8_BY4 = 0x0000001a, - DBG_BLOCK_ID_TCP12_BY4 = 0x0000001b, - DBG_BLOCK_ID_TCP16_BY4 = 0x0000001c, - DBG_BLOCK_ID_TCP20_BY4 = 0x0000001d, - DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x0000001e, - DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x0000001f, - DBG_BLOCK_ID_DB_BY4 = 0x00000020, - DBG_BLOCK_ID_DB04_BY4 = 0x00000021, - DBG_BLOCK_ID_DB10_BY4 = 0x00000022, - DBG_BLOCK_ID_DB14_BY4 = 0x00000023, - DBG_BLOCK_ID_TCC0_BY4 = 0x00000024, - DBG_BLOCK_ID_TCC4_BY4 = 0x00000025, - DBG_BLOCK_ID_SPS00_BY4 = 0x00000026, - DBG_BLOCK_ID_SPS11_BY4 = 0x00000027, - DBG_BLOCK_ID_TA00_BY4 = 0x00000028, - DBG_BLOCK_ID_TA04_BY4 = 0x00000029, - DBG_BLOCK_ID_TA08_BY4 = 0x0000002a, - DBG_BLOCK_ID_UNUSED35_BY4 = 0x0000002b, - DBG_BLOCK_ID_TA10_BY4 = 0x0000002c, - DBG_BLOCK_ID_TA14_BY4 = 0x0000002d, - DBG_BLOCK_ID_TA18_BY4 = 0x0000002e, - DBG_BLOCK_ID_UNUSED39_BY4 = 0x0000002f, - DBG_BLOCK_ID_TD00_BY4 = 0x00000030, - DBG_BLOCK_ID_TD04_BY4 = 0x00000031, - DBG_BLOCK_ID_TD08_BY4 = 0x00000032, - DBG_BLOCK_ID_UNUSED43_BY4 = 0x00000033, - DBG_BLOCK_ID_TD10_BY4 = 0x00000034, - DBG_BLOCK_ID_TD14_BY4 = 0x00000035, - DBG_BLOCK_ID_TD18_BY4 = 0x00000036, - DBG_BLOCK_ID_UNUSED47_BY4 = 0x00000037, - DBG_BLOCK_ID_MCD0_BY4 = 0x00000038, - DBG_BLOCK_ID_MCD4_BY4 = 0x00000039, -} DebugBlockId_BY4; - -typedef enum DebugBlockId_BY8 { - DBG_BLOCK_ID_RESERVED_BY8 = 0x00000000, - DBG_BLOCK_ID_CSC_BY8 = 0x00000001, - DBG_BLOCK_ID_DRMDMA0_BY8 = 0x00000002, - DBG_BLOCK_ID_CP0_BY8 = 0x00000003, - DBG_BLOCK_ID_VGT0_BY8 = 0x00000004, - DBG_BLOCK_ID_TCAA_BY8 = 0x00000005, - DBG_BLOCK_ID_SX0_BY8 = 0x00000006, - DBG_BLOCK_ID_PC0_BY8 = 0x00000007, - DBG_BLOCK_ID_SCB0_BY8 = 0x00000008, - DBG_BLOCK_ID_BCI0_BY8 = 0x00000009, - DBG_BLOCK_ID_CB00_BY8 = 0x0000000a, - DBG_BLOCK_ID_CB10_BY8 = 0x0000000b, - DBG_BLOCK_ID_TCP0_BY8 = 0x0000000c, - DBG_BLOCK_ID_TCP8_BY8 = 0x0000000d, - DBG_BLOCK_ID_TCP16_BY8 = 0x0000000e, - DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0x0000000f, - DBG_BLOCK_ID_DB00_BY8 = 0x00000010, - DBG_BLOCK_ID_DB10_BY8 = 0x00000011, - DBG_BLOCK_ID_TCC0_BY8 = 0x00000012, - DBG_BLOCK_ID_SPS00_BY8 = 0x00000013, - DBG_BLOCK_ID_TA00_BY8 = 0x00000014, - DBG_BLOCK_ID_TA08_BY8 = 0x00000015, - DBG_BLOCK_ID_TA10_BY8 = 0x00000016, - DBG_BLOCK_ID_TA18_BY8 = 0x00000017, - DBG_BLOCK_ID_TD00_BY8 = 0x00000018, - DBG_BLOCK_ID_TD08_BY8 = 0x00000019, - DBG_BLOCK_ID_TD10_BY8 = 0x0000001a, - DBG_BLOCK_ID_TD18_BY8 = 0x0000001b, - DBG_BLOCK_ID_MCD0_BY8 = 0x0000001c, -} DebugBlockId_BY8; - -typedef enum DepthArray { - ARRAY_2D_ALT_DEPTH = 0x00000000, - ARRAY_2D_DEPTH = 0x00000001, -} DepthArray; - -typedef enum DepthFormat { - DEPTH_INVALID = 0x00000000, - DEPTH_16 = 0x00000001, - DEPTH_X8_24 = 0x00000002, - DEPTH_8_24 = 0x00000003, - DEPTH_X8_24_FLOAT = 0x00000004, - DEPTH_8_24_FLOAT = 0x00000005, - DEPTH_32_FLOAT = 0x00000006, - DEPTH_X24_8_32_FLOAT = 0x00000007, -} DepthFormat; - -typedef enum ENUM_SQ_EXPORT_RAT_INST { - SQ_EXPORT_RAT_INST_NOP = 0x00000000, - SQ_EXPORT_RAT_INST_STORE_TYPED = 0x00000001, - SQ_EXPORT_RAT_INST_STORE_RAW = 0x00000002, - SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x00000003, - SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x00000004, - SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x00000005, - SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x00000006, - SQ_EXPORT_RAT_INST_ADD = 0x00000007, - SQ_EXPORT_RAT_INST_SUB = 0x00000008, - SQ_EXPORT_RAT_INST_RSUB = 0x00000009, - SQ_EXPORT_RAT_INST_MIN_INT = 0x0000000a, - SQ_EXPORT_RAT_INST_MIN_UINT = 0x0000000b, - SQ_EXPORT_RAT_INST_MAX_INT = 0x0000000c, - SQ_EXPORT_RAT_INST_MAX_UINT = 0x0000000d, - SQ_EXPORT_RAT_INST_AND = 0x0000000e, - SQ_EXPORT_RAT_INST_OR = 0x0000000f, - SQ_EXPORT_RAT_INST_XOR = 0x00000010, - SQ_EXPORT_RAT_INST_MSKOR = 0x00000011, - SQ_EXPORT_RAT_INST_INC_UINT = 0x00000012, - SQ_EXPORT_RAT_INST_DEC_UINT = 0x00000013, - SQ_EXPORT_RAT_INST_STORE_DWORD = 0x00000014, - SQ_EXPORT_RAT_INST_STORE_SHORT = 0x00000015, - SQ_EXPORT_RAT_INST_STORE_BYTE = 0x00000016, - SQ_EXPORT_RAT_INST_NOP_RTN = 0x00000020, - SQ_EXPORT_RAT_INST_XCHG_RTN = 0x00000022, - SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x00000023, - SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x00000024, - SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x00000025, - SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x00000026, - SQ_EXPORT_RAT_INST_ADD_RTN = 0x00000027, - SQ_EXPORT_RAT_INST_SUB_RTN = 0x00000028, - SQ_EXPORT_RAT_INST_RSUB_RTN = 0x00000029, - SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x0000002a, - SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x0000002b, - SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x0000002c, - SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x0000002d, - SQ_EXPORT_RAT_INST_AND_RTN = 0x0000002e, - SQ_EXPORT_RAT_INST_OR_RTN = 0x0000002f, - SQ_EXPORT_RAT_INST_XOR_RTN = 0x00000030, - SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x00000031, - SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x00000032, - SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x00000033, -} ENUM_SQ_EXPORT_RAT_INST; - -typedef enum ForceControl { - FORCE_OFF = 0x00000000, - FORCE_ENABLE = 0x00000001, - FORCE_DISABLE = 0x00000002, - FORCE_RESERVED = 0x00000003, -} ForceControl; - -typedef enum GB_EDC_DED_MODE { - GB_EDC_DED_MODE_LOG = 0x00000000, - GB_EDC_DED_MODE_HALT = 0x00000001, - GB_EDC_DED_MODE_INT_HALT = 0x00000002, -} GB_EDC_DED_MODE; - -typedef enum GDS_PERFCOUNT_SELECT { - GDS_PERF_SEL_DS_ADDR_CONFL = 0, - GDS_PERF_SEL_DS_BANK_CONFL = 1, - GDS_PERF_SEL_WBUF_FLUSH = 2, - GDS_PERF_SEL_WR_COMP = 3, - GDS_PERF_SEL_WBUF_WR = 4, - GDS_PERF_SEL_RBUF_HIT = 5, - GDS_PERF_SEL_RBUF_MISS = 6, - GDS_PERF_SEL_SE0_SH0_NORET = 7, - GDS_PERF_SEL_SE0_SH0_RET = 8, - GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, - GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, - GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, - GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, - GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, - GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, - GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, - GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, - GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, - GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, - GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, - GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, - GDS_PERF_SEL_SE0_SH1_NORET = 21, - GDS_PERF_SEL_SE0_SH1_RET = 22, - GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, - GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, - GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, - GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, - GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, - GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, - GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, - GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, - GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, - GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, - GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, - GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, - GDS_PERF_SEL_SE1_SH0_NORET = 35, - GDS_PERF_SEL_SE1_SH0_RET = 36, - GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, - GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, - GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, - GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, - GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, - GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, - GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, - GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, - GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, - GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, - GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, - GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, - GDS_PERF_SEL_SE1_SH1_NORET = 49, - GDS_PERF_SEL_SE1_SH1_RET = 50, - GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, - GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, - GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, - GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, - GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, - GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, - GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, - GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, - GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, - GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, - GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, - GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, - GDS_PERF_SEL_GWS_RELEASED__SI = 63, - GDS_PERF_SEL_SE2_SH0_NORET__CI__VI = 63, - GDS_PERF_SEL_GWS_BYPASS__SI = 64, - GDS_PERF_SEL_SE2_SH0_RET__CI__VI = 64, - GDS_PERF_SEL_SE2_SH0_ORD_CNT__CI__VI = 65, - GDS_PERF_SEL_SE2_SH0_2COMP_REQ__CI__VI = 66, - GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID__CI__VI = 67, - GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID__CI__VI = 68, - GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD__CI__VI = 69, - GDS_PERF_SEL_SE2_SH0_GDS_WR_OP__CI__VI = 70, - GDS_PERF_SEL_SE2_SH0_GDS_RD_OP__CI__VI = 71, - GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP__CI__VI = 72, - GDS_PERF_SEL_SE2_SH0_GDS_REL_OP__CI__VI = 73, - GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP__CI__VI = 74, - GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP__CI__VI = 75, - GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP__CI__VI = 76, - GDS_PERF_SEL_SE2_SH1_NORET__CI__VI = 77, - GDS_PERF_SEL_SE2_SH1_RET__CI__VI = 78, - GDS_PERF_SEL_SE2_SH1_ORD_CNT__CI__VI = 79, - GDS_PERF_SEL_SE2_SH1_2COMP_REQ__CI__VI = 80, - GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID__CI__VI = 81, - GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID__CI__VI = 82, - GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD__CI__VI = 83, - GDS_PERF_SEL_SE2_SH1_GDS_WR_OP__CI__VI = 84, - GDS_PERF_SEL_SE2_SH1_GDS_RD_OP__CI__VI = 85, - GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP__CI__VI = 86, - GDS_PERF_SEL_SE2_SH1_GDS_REL_OP__CI__VI = 87, - GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP__CI__VI = 88, - GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP__CI__VI = 89, - GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP__CI__VI = 90, - GDS_PERF_SEL_SE3_SH0_NORET__CI__VI = 91, - GDS_PERF_SEL_SE3_SH0_RET__CI__VI = 92, - GDS_PERF_SEL_SE3_SH0_ORD_CNT__CI__VI = 93, - GDS_PERF_SEL_SE3_SH0_2COMP_REQ__CI__VI = 94, - GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID__CI__VI = 95, - GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID__CI__VI = 96, - GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD__CI__VI = 97, - GDS_PERF_SEL_SE3_SH0_GDS_WR_OP__CI__VI = 98, - GDS_PERF_SEL_SE3_SH0_GDS_RD_OP__CI__VI = 99, - GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP__CI__VI = 100, - GDS_PERF_SEL_SE3_SH0_GDS_REL_OP__CI__VI = 101, - GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP__CI__VI = 102, - GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP__CI__VI = 103, - GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP__CI__VI = 104, - GDS_PERF_SEL_SE3_SH1_NORET__CI__VI = 105, - GDS_PERF_SEL_SE3_SH1_RET__CI__VI = 106, - GDS_PERF_SEL_SE3_SH1_ORD_CNT__CI__VI = 107, - GDS_PERF_SEL_SE3_SH1_2COMP_REQ__CI__VI = 108, - GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID__CI__VI = 109, - GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID__CI__VI = 110, - GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD__CI__VI = 111, - GDS_PERF_SEL_SE3_SH1_GDS_WR_OP__CI__VI = 112, - GDS_PERF_SEL_SE3_SH1_GDS_RD_OP__CI__VI = 113, - GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP__CI__VI = 114, - GDS_PERF_SEL_SE3_SH1_GDS_REL_OP__CI__VI = 115, - GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP__CI__VI = 116, - GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP__CI__VI = 117, - GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP__CI__VI = 118, - GDS_PERF_SEL_GWS_RELEASED__CI__VI = 119, - GDS_PERF_SEL_GWS_BYPASS__CI__VI = 120, -} GDS_PERFCOUNT_SELECT; - -typedef enum GRBM_PERF_SEL { - GRBM_PERF_SEL_COUNT = 0x00000000, - GRBM_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, - GRBM_PERF_SEL_CP_BUSY = 0x00000003, - GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, - GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, - GRBM_PERF_SEL_CB_BUSY = 0x00000006, - GRBM_PERF_SEL_DB_BUSY = 0x00000007, - GRBM_PERF_SEL_PA_BUSY = 0x00000008, - GRBM_PERF_SEL_SC_BUSY = 0x00000009, - GRBM_PERF_SEL_RESERVED_2__SI = 0x0000000a, - GRBM_PERF_SEL_RESERVED_6__CI__VI = 0x0000000a, - GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, - GRBM_PERF_SEL_SX_BUSY = 0x0000000c, - GRBM_PERF_SEL_TA_BUSY = 0x0000000d, - GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, - GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, - GRBM_PERF_SEL_RESERVED_1__SI = 0x00000010, - GRBM_PERF_SEL_RESERVED_5__CI__VI = 0x00000010, - GRBM_PERF_SEL_VGT_BUSY = 0x00000011, - GRBM_PERF_SEL_RESERVED_0__SI = 0x00000012, - GRBM_PERF_SEL_RESERVED_4__CI__VI = 0x00000012, - GRBM_PERF_SEL_EXTERN_STALL__SI = 0x00000013, - GRBM_PERF_SEL_RESERVED_3__CI__VI = 0x00000013, - GRBM_PERF_SEL_CP_DMA_IDLE_STALL__SI = 0x00000014, - GRBM_PERF_SEL_RESERVED_2__CI__VI = 0x00000014, - GRBM_PERF_SEL_GFX_IDLE_STALL__SI = 0x00000015, - GRBM_PERF_SEL_RESERVED_1__CI__VI = 0x00000015, - GRBM_PERF_SEL_GFX_IDLE_CLEAN_STALL__SI = 0x00000016, - GRBM_PERF_SEL_RESERVED_0__CI__VI = 0x00000016, - GRBM_PERF_SEL_IA_BUSY = 0x00000017, - GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018, - GRBM_PERF_SEL_GDS_BUSY = 0x00000019, - GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, - GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, - GRBM_PERF_SEL_TC_BUSY = 0x0000001c, - GRBM_PERF_SEL_CPG_BUSY__CI__VI = 0x0000001d, - GRBM_PERF_SEL_CPC_BUSY__CI__VI = 0x0000001e, - GRBM_PERF_SEL_CPF_BUSY__CI__VI = 0x0000001f, - GRBM_PERF_SEL_WD_BUSY__CI__VI = 0x00000020, - GRBM_PERF_SEL_WD_NO_DMA_BUSY__CI__VI = 0x00000021, -} GRBM_PERF_SEL; - -typedef enum GRBM_SE0_PERF_SEL { - GRBM_SE0_PERF_SEL_COUNT = 0x00000000, - GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE0_PERF_SEL; - -typedef enum GRBM_SE1_PERF_SEL { - GRBM_SE1_PERF_SEL_COUNT = 0x00000000, - GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE1_PERF_SEL; - -typedef enum GRBM_SE2_PERF_SEL { - GRBM_SE2_PERF_SEL_COUNT = 0x00000000, - GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE2_PERF_SEL; - -typedef enum GRBM_SE3_PERF_SEL { - GRBM_SE3_PERF_SEL_COUNT = 0x00000000, - GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE3_PERF_SEL; - -typedef enum GroupInterleave { - CONFIG_256B_GROUP = 0x00000000, - CONFIG_512B_GROUP = 0x00000001, -} GroupInterleave; - -typedef enum IA_PERFCOUNT_SELECT { - ia_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE__SI = 0x00000000, - ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE__CI__VI = 0x00000000, - ia_perf_RBIU_IM_FIFO_STARVED__SI = 0x00000001, - ia_perf_MC_LAT_BIN_0__CI = 0x00000001, - ia_perf_dma_data_fifo_full__VI = 0x00000001, - ia_perf_RBIU_IM_FIFO_STALLED__SI = 0x00000002, - ia_perf_MC_LAT_BIN_1__CI = 0x00000002, - ia_perf_RESERVED1__VI = 0x00000002, - ia_perf_RBIU_DR_FIFO_STARVED__SI = 0x00000003, - ia_perf_MC_LAT_BIN_2__CI = 0x00000003, - ia_perf_RESERVED2__VI = 0x00000003, - ia_perf_RBIU_DR_FIFO_STALLED__SI = 0x00000004, - ia_perf_MC_LAT_BIN_3__CI = 0x00000004, - ia_perf_RESERVED3__VI = 0x00000004, - ia_perf_RBIU_DI_FIFO_STARVED__SI = 0x00000005, - ia_perf_MC_LAT_BIN_4__CI = 0x00000005, - ia_perf_RESERVED4__VI = 0x00000005, - ia_perf_RBIU_DI_FIFO_STALLED__SI = 0x00000006, - ia_perf_MC_LAT_BIN_5__CI = 0x00000006, - ia_perf_RESERVED5__VI = 0x00000006, - ia_perf_MC_LAT_BIN_0__SI__VI = 0x00000007, - ia_perf_MC_LAT_BIN_6__CI = 0x00000007, - ia_perf_MC_LAT_BIN_1__SI__VI = 0x00000008, - ia_perf_MC_LAT_BIN_7__CI = 0x00000008, - ia_perf_MC_LAT_BIN_2__SI__VI = 0x00000009, - ia_perf_ia_busy__CI = 0x00000009, - ia_perf_MC_LAT_BIN_3__SI__VI = 0x0000000a, - ia_perf_ia_sclk_reg_vld_event__CI = 0x0000000a, - ia_perf_MC_LAT_BIN_4__SI__VI = 0x0000000b, - ia_perf_RESERVED0__CI = 0x0000000b, - ia_perf_MC_LAT_BIN_5__SI__VI = 0x0000000c, - ia_perf_ia_sclk_core_vld_event__CI = 0x0000000c, - ia_perf_MC_LAT_BIN_6__SI__VI = 0x0000000d, - ia_perf_RESERVED1__CI = 0x0000000d, - ia_perf_MC_LAT_BIN_7__SI__VI = 0x0000000e, - ia_perf_ia_dma_return__CI = 0x0000000e, - ia_perf_ia_busy__SI__VI = 0x0000000f, - ia_perf_shift_starved_pipe1_event__CI = 0x0000000f, - ia_perf_ia_sclk_reg_vld_event__SI__VI = 0x00000010, - ia_perf_shift_starved_pipe0_event__CI = 0x00000010, - ia_perf_ia_sclk_input_vld_event__SI = 0x00000011, - ia_perf_ia_stalled__CI = 0x00000011, - ia_perf_RESERVED6__VI = 0x00000011, - ia_perf_ia_sclk_core_vld_event__SI__VI = 0x00000012, - ia_perf_ia_sclk_inval_vld_event__SI = 0x00000013, - ia_perf_RESERVED7__VI = 0x00000013, - ia_perf_ia_dma_return__SI__VI = 0x00000014, - ia_perf_ia_stalled__SI__VI = 0x00000015, - ia_perf_shift_starved_pipe0_event__VI = 0x00000016, - ia_perf_shift_starved_pipe1_event__VI = 0x00000017, -} IA_PERFCOUNT_SELECT; - -typedef enum IH_CLIENT_ID { - DC_IH_SRC_ID_START = 0x00000001, - DC_IH_SRC_ID_END = 0x0000001f, - VGA_IH_SRC_ID_START = 0x00000020, - VGA_IH_SRC_ID_END = 0x00000027, - CAP_IH_SRC_ID_START = 0x00000028, - CAP_IH_SRC_ID_END = 0x0000002f, - VIP_IH_SRC_ID_START = 0x00000030, - VIP_IH_SRC_ID_END = 0x0000003f, - ROM_IH_SRC_ID_START = 0x00000040, - ROM_IH_SRC_ID_END = 0x0000005d, - BIF_IH_SRC_ID_START = 0x0000005e, - BIF_IH_SRC_ID_END__SI = 0x0000005f, - SAM_IH_SRC_ID_START__CI__VI = 0x0000005f, - SRBM_IH_SRC_ID_START = 0x00000060, - SRBM_IH_SRC_ID_END = 0x00000067, - DRM_IH_SRC_ID_START = 0x00000068, - DRM_IH_SRC_ID_END = 0x00000071, - UVD_IH_SRC_ID_START = 0x00000072, - UVD_IH_SRC_ID_END = 0x00000085, - VMC_IH_SRC_ID_START = 0x00000086, - VMC_IH_SRC_ID_END = 0x0000008f, - RLC_IH_SRC_ID_START = 0x00000090, - RLC_IH_SRC_ID_END = 0x000000f3, - PDMA_IH_SRC_ID_START = 0x000000f4, - PDMA_IH_SRC_ID_END = 0x000000f7, - CG_IH_SRC_ID_START = 0x000000f8, - CG_IH_SRC_ID_END = 0x000000ff, -} IH_CLIENT_ID; - -typedef enum IH_PERF_SEL { - IH_PERF_CYCLE__SI = 0x00000000, - IH_PERF_SEL_CYCLE__CI__VI = 0x00000000, - IH_PERF_IDLE__SI = 0x00000001, - IH_PERF_SEL_IDLE__CI__VI = 0x00000001, - IH_PERF_INPUT_IDLE__SI = 0x00000002, - IH_PERF_SEL_INPUT_IDLE__CI__VI = 0x00000002, - IH_PERF_CLIENT0_IH_STALL__SI = 0x00000003, - IH_PERF_SEL_CLIENT0_IH_STALL__CI__VI = 0x00000003, - IH_PERF_CLIENT1_IH_STALL__SI = 0x00000004, - IH_PERF_SEL_CLIENT1_IH_STALL__CI__VI = 0x00000004, - IH_PERF_CLIENT2_IH_STALL__SI = 0x00000005, - IH_PERF_SEL_CLIENT2_IH_STALL__CI__VI = 0x00000005, - IH_PERF_CLIENT3_IH_STALL__SI = 0x00000006, - IH_PERF_SEL_CLIENT3_IH_STALL__CI__VI = 0x00000006, - IH_PERF_CLIENT4_IH_STALL__SI = 0x00000007, - IH_PERF_SEL_CLIENT4_IH_STALL__CI__VI = 0x00000007, - IH_PERF_CLIENT5_IH_STALL__SI = 0x00000008, - IH_PERF_SEL_CLIENT5_IH_STALL__CI__VI = 0x00000008, - IH_PERF_CLIENT6_IH_STALL__SI = 0x00000009, - IH_PERF_SEL_CLIENT6_IH_STALL__CI__VI = 0x00000009, - IH_PERF_CLIENT7_IH_STALL__SI = 0x0000000a, - IH_PERF_SEL_CLIENT7_IH_STALL__CI__VI = 0x0000000a, - IH_PERF_RB_IDLE__SI = 0x0000000b, - IH_PERF_SEL_RB_IDLE__CI__VI = 0x0000000b, - IH_PERF_RB_FULL__SI = 0x0000000c, - IH_PERF_SEL_RB_FULL__CI__VI = 0x0000000c, - IH_PERF_RB_OVERFLOW__SI = 0x0000000d, - IH_PERF_SEL_RB_OVERFLOW__CI__VI = 0x0000000d, - IH_PERF_RB_WPTR_WRITEBACK__SI = 0x0000000e, - IH_PERF_SEL_RB_WPTR_WRITEBACK__CI__VI = 0x0000000e, - IH_PERF_RB_WPTR_WRAP__SI = 0x0000000f, - IH_PERF_SEL_RB_WPTR_WRAP__CI__VI = 0x0000000f, - IH_PERF_RB_RPTR_WRAP__SI = 0x00000010, - IH_PERF_SEL_RB_RPTR_WRAP__CI__VI = 0x00000010, - IH_PERF_MC_WR_IDLE__SI = 0x00000011, - IH_PERF_SEL_MC_WR_IDLE__CI__VI = 0x00000011, - IH_PERF_MC_WR_COUNT__SI = 0x00000012, - IH_PERF_SEL_MC_WR_COUNT__CI__VI = 0x00000012, - IH_PERF_MC_WR_STALL__SI = 0x00000013, - IH_PERF_SEL_MC_WR_STALL__CI__VI = 0x00000013, - IH_PERF_MC_WR_CLEAN_PENDING__SI = 0x00000014, - IH_PERF_SEL_MC_WR_CLEAN_PENDING__CI__VI = 0x00000014, - IH_PERF_MC_WR_CLEAN_STALL__SI = 0x00000015, - IH_PERF_SEL_MC_WR_CLEAN_STALL__CI__VI = 0x00000015, - IH_PERF_BIF_RISING__SI = 0x00000016, - IH_PERF_SEL_BIF_RISING__CI__VI = 0x00000016, - IH_PERF_BIF_FALLING__SI = 0x00000017, - IH_PERF_SEL_BIF_FALLING__CI__VI = 0x00000017, - IH_PERF_CLIENT8_IH_STALL__SI = 0x00000018, - IH_PERF_SEL_CLIENT8_IH_STALL__CI__VI = 0x00000018, - IH_PERF_CLIENT9_IH_STALL__SI = 0x00000019, - IH_PERF_SEL_CLIENT9_IH_STALL__CI__VI = 0x00000019, - IH_PERF_SEL_CLIENT10_IH_STALL__CI__VI = 0x0000001a, - IH_PERF_SEL_CLIENT11_IH_STALL__CI__VI = 0x0000001b, - IH_PERF_SEL_CLIENT12_IH_STALL__CI__VI = 0x0000001c, - IH_PERF_SEL_CLIENT13_IH_STALL__CI__VI = 0x0000001d, - IH_PERF_SEL_CLIENT14_IH_STALL__CI__VI = 0x0000001e, - IH_PERF_SEL_CLIENT15_IH_STALL__CI__VI = 0x0000001f, - IH_PERF_SEL_CLIENT16_IH_STALL__CI__VI = 0x00000020, - IH_PERF_SEL_CLIENT17_IH_STALL__CI__VI = 0x00000021, - IH_PERF_SEL_CLIENT18_IH_STALL__CI__VI = 0x00000022, - IH_PERF_SEL_CLIENT19_IH_STALL__CI__VI = 0x00000023, - IH_PERF_SEL_CLIENT20_IH_STALL__VI = 0x00000024, - IH_PERF_SEL_CLIENT21_IH_STALL__VI = 0x00000025, - IH_PERF_SEL_CLIENT22_IH_STALL__VI = 0x00000026, -} IH_PERF_SEL; - -typedef enum IMG_DATA_FORMAT { - IMG_DATA_FORMAT_INVALID = 0x00000000, - IMG_DATA_FORMAT_8 = 0x00000001, - IMG_DATA_FORMAT_16 = 0x00000002, - IMG_DATA_FORMAT_8_8 = 0x00000003, - IMG_DATA_FORMAT_32 = 0x00000004, - IMG_DATA_FORMAT_16_16 = 0x00000005, - IMG_DATA_FORMAT_10_11_11 = 0x00000006, - IMG_DATA_FORMAT_11_11_10 = 0x00000007, - IMG_DATA_FORMAT_10_10_10_2 = 0x00000008, - IMG_DATA_FORMAT_2_10_10_10 = 0x00000009, - IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a, - IMG_DATA_FORMAT_32_32 = 0x0000000b, - IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c, - IMG_DATA_FORMAT_32_32_32 = 0x0000000d, - IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e, - IMG_DATA_FORMAT_RESERVED_15__SI__CI = 0x0000000f, - IMG_DATA_FORMAT_16_AS_32_32__VI = 0x0000000f, - IMG_DATA_FORMAT_5_6_5 = 0x00000010, - IMG_DATA_FORMAT_1_5_5_5 = 0x00000011, - IMG_DATA_FORMAT_5_5_5_1 = 0x00000012, - IMG_DATA_FORMAT_4_4_4_4 = 0x00000013, - IMG_DATA_FORMAT_8_24 = 0x00000014, - IMG_DATA_FORMAT_24_8 = 0x00000015, - IMG_DATA_FORMAT_X24_8_32 = 0x00000016, - IMG_DATA_FORMAT_RESERVED_23__SI__CI = 0x00000017, - IMG_DATA_FORMAT_8_AS_8_8_8_8__VI = 0x00000017, - IMG_DATA_FORMAT_RESERVED_24__SI__CI = 0x00000018, - IMG_DATA_FORMAT_ETC2_RGB__VI = 0x00000018, - IMG_DATA_FORMAT_RESERVED_25__SI__CI = 0x00000019, - IMG_DATA_FORMAT_ETC2_RGBA__VI = 0x00000019, - IMG_DATA_FORMAT_RESERVED_26__SI__CI = 0x0000001a, - IMG_DATA_FORMAT_ETC2_R__VI = 0x0000001a, - IMG_DATA_FORMAT_RESERVED_27__SI__CI = 0x0000001b, - IMG_DATA_FORMAT_ETC2_RG__VI = 0x0000001b, - IMG_DATA_FORMAT_RESERVED_28__SI__CI = 0x0000001c, - IMG_DATA_FORMAT_ETC2_RGBA1__VI = 0x0000001c, - IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d, - IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e, - IMG_DATA_FORMAT_RESERVED_31 = 0x0000001f, - IMG_DATA_FORMAT_GB_GR = 0x00000020, - IMG_DATA_FORMAT_BG_RG = 0x00000021, - IMG_DATA_FORMAT_5_9_9_9 = 0x00000022, - IMG_DATA_FORMAT_BC1 = 0x00000023, - IMG_DATA_FORMAT_BC2 = 0x00000024, - IMG_DATA_FORMAT_BC3 = 0x00000025, - IMG_DATA_FORMAT_BC4 = 0x00000026, - IMG_DATA_FORMAT_BC5 = 0x00000027, - IMG_DATA_FORMAT_BC6 = 0x00000028, - IMG_DATA_FORMAT_BC7 = 0x00000029, - IMG_DATA_FORMAT_RESERVED_42__SI__CI = 0x0000002a, - IMG_DATA_FORMAT_16_AS_16_16_16_16__VI = 0x0000002a, - IMG_DATA_FORMAT_RESERVED_43__SI__CI = 0x0000002b, - IMG_DATA_FORMAT_16_AS_32_32_32_32__VI = 0x0000002b, - IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x0000002c, - IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x0000002d, - IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x0000002e, - IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x0000002f, - IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x00000030, - IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x00000031, - IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x00000032, - IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x00000033, - IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x00000034, - IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x00000035, - IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x00000036, - IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x00000037, - IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x00000038, - IMG_DATA_FORMAT_4_4 = 0x00000039, - IMG_DATA_FORMAT_6_5_5 = 0x0000003a, - IMG_DATA_FORMAT_1 = 0x0000003b, - IMG_DATA_FORMAT_1_REVERSED = 0x0000003c, - IMG_DATA_FORMAT_32_AS_8__SI__CI = 0x0000003d, - IMG_DATA_FORMAT_8_AS_32__VI = 0x0000003d, - IMG_DATA_FORMAT_32_AS_8_8__SI__CI = 0x0000003e, - IMG_DATA_FORMAT_8_AS_32_32__VI = 0x0000003e, - IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f, -} IMG_DATA_FORMAT; - -typedef enum IMG_NUM_FORMAT { - IMG_NUM_FORMAT_UNORM = 0x00000000, - IMG_NUM_FORMAT_SNORM = 0x00000001, - IMG_NUM_FORMAT_USCALED = 0x00000002, - IMG_NUM_FORMAT_SSCALED = 0x00000003, - IMG_NUM_FORMAT_UINT = 0x00000004, - IMG_NUM_FORMAT_SINT = 0x00000005, - IMG_NUM_FORMAT_SNORM_OGL__SI__CI = 0x00000006, - IMG_NUM_FORMAT_RESERVED_6__VI = 0x00000006, - IMG_NUM_FORMAT_FLOAT = 0x00000007, - IMG_NUM_FORMAT_RESERVED_8 = 0x00000008, - IMG_NUM_FORMAT_SRGB = 0x00000009, - IMG_NUM_FORMAT_UBNORM__SI__CI = 0x0000000a, - IMG_NUM_FORMAT_RESERVED_10__VI = 0x0000000a, - IMG_NUM_FORMAT_UBNORM_OGL__SI__CI = 0x0000000b, - IMG_NUM_FORMAT_RESERVED_11__VI = 0x0000000b, - IMG_NUM_FORMAT_UBINT__SI__CI = 0x0000000c, - IMG_NUM_FORMAT_RESERVED_12__VI = 0x0000000c, - IMG_NUM_FORMAT_UBSCALED__SI__CI = 0x0000000d, - IMG_NUM_FORMAT_RESERVED_13__VI = 0x0000000d, - IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e, - IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f, -} IMG_NUM_FORMAT; - -typedef enum MacroTileAspect { - ADDR_SURF_MACRO_ASPECT_1 = 0x00000000, - ADDR_SURF_MACRO_ASPECT_2 = 0x00000001, - ADDR_SURF_MACRO_ASPECT_4 = 0x00000002, - ADDR_SURF_MACRO_ASPECT_8 = 0x00000003, -} MacroTileAspect; - -typedef enum MicroTileMode { - ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000, - ADDR_SURF_THIN_MICRO_TILING = 0x00000001, - ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002, - ADDR_SURF_THICK_MICRO_TILING__SI = 0x00000003, - ADDR_SURF_ROTATED_MICRO_TILING__CI__VI = 0x00000003, - ADDR_SURF_THICK_MICRO_TILING__CI__VI = 0x00000004, -} MicroTileMode; - -typedef enum MultiGPUTileSize { - ADDR_CONFIG_GPU_TILE_16 = 0x00000000, - ADDR_CONFIG_GPU_TILE_32 = 0x00000001, - ADDR_CONFIG_GPU_TILE_64 = 0x00000002, - ADDR_CONFIG_GPU_TILE_128 = 0x00000003, -} MultiGPUTileSize; - -typedef enum NonDispTilingOrder { - ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000, - ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001, -} NonDispTilingOrder; - -typedef enum NumBanks { - ADDR_SURF_2_BANK = 0x00000000, - ADDR_SURF_4_BANK = 0x00000001, - ADDR_SURF_8_BANK = 0x00000002, - ADDR_SURF_16_BANK = 0x00000003, -} NumBanks; - -typedef enum NumGPUs { - ADDR_CONFIG_1_GPU = 0x00000000, - ADDR_CONFIG_2_GPU = 0x00000001, - ADDR_CONFIG_4_GPU = 0x00000002, -} NumGPUs; - -typedef enum NumLowerPipes { - ADDR_CONFIG_1_LOWER_PIPES = 0x00000000, - ADDR_CONFIG_2_LOWER_PIPES = 0x00000001, -} NumLowerPipes; - -typedef enum NumPipes { - ADDR_CONFIG_1_PIPE = 0x00000000, - ADDR_CONFIG_2_PIPE = 0x00000001, - ADDR_CONFIG_4_PIPE = 0x00000002, - ADDR_CONFIG_8_PIPE = 0x00000003, -} NumPipes; - -typedef enum NumShaderEngines { - ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, - ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, -} NumShaderEngines; - -typedef enum PERFMON_COUNTER_MODE { - PERFMON_COUNTER_MODE_ACCUM = 0x00000000, - PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, - PERFMON_COUNTER_MODE_MAX = 0x00000002, - PERFMON_COUNTER_MODE_DIRTY = 0x00000003, - PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, - PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, - PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, - PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, - PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, - PERFMON_COUNTER_MODE_INACTIVE_CYCLES__CI__VI = 0x00000009, - PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, -} PERFMON_COUNTER_MODE; - -typedef enum PERFMON_SPM_MODE { - PERFMON_SPM_MODE_OFF = 0x00000000, - PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, - PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, - PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, - PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, - PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, - PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, - PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, - PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, - PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, - PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, -} PERFMON_SPM_MODE; - -typedef enum PerfCounter_Vals { - DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, - DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, - DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, - DB_PERF_SEL_SC_DB_tile_events = 0x00000003, - DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, - DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, - DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, - DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, - DB_PERF_SEL_hiz_qtiles_culled = 0x00000008, - DB_PERF_SEL_his_qtiles_culled = 0x00000009, - DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, - DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, - DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, - DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, - DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, - DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, - DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, - DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, - DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, - DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, - DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, - DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, - DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, - DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, - DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, - DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, - DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, - DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, - DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, - DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, - DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, - DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, - DB_PERF_SEL_UNUSED0__SI = 0x00000020, - DB_PERF_SEL_DB_SC_quad_tiles__CI__VI = 0x00000020, - DB_PERF_SEL_DB_SC_quad_tiles__SI = 0x00000021, - DB_PERF_SEL_DB_SC_quad_lit_quad__CI__VI = 0x00000021, - DB_PERF_SEL_DB_SC_quad_lit_quad__SI = 0x00000022, - DB_PERF_SEL_DB_CB_tile_sends__CI__VI = 0x00000022, - DB_PERF_SEL_DB_CB_tile_sends__SI = 0x00000023, - DB_PERF_SEL_DB_CB_tile_busy__CI__VI = 0x00000023, - DB_PERF_SEL_DB_CB_tile_busy__SI = 0x00000024, - DB_PERF_SEL_DB_CB_tile_stalls__CI__VI = 0x00000024, - DB_PERF_SEL_DB_CB_tile_stalls__SI = 0x00000025, - DB_PERF_SEL_SX_DB_quad_sends__CI__VI = 0x00000025, - DB_PERF_SEL_SX_DB_quad_sends__SI = 0x00000026, - DB_PERF_SEL_SX_DB_quad_busy__CI__VI = 0x00000026, - DB_PERF_SEL_SX_DB_quad_busy__SI = 0x00000027, - DB_PERF_SEL_SX_DB_quad_stalls__CI__VI = 0x00000027, - DB_PERF_SEL_SX_DB_quad_stalls__SI = 0x00000028, - DB_PERF_SEL_SX_DB_quad_quads__CI__VI = 0x00000028, - DB_PERF_SEL_SX_DB_quad_quads__SI = 0x00000029, - DB_PERF_SEL_SX_DB_quad_pixels__CI__VI = 0x00000029, - DB_PERF_SEL_SX_DB_quad_pixels__SI = 0x0000002a, - DB_PERF_SEL_SX_DB_quad_exports__CI__VI = 0x0000002a, - DB_PERF_SEL_SX_DB_quad_exports__SI = 0x0000002b, - DB_PERF_SEL_SH_quads_outstanding_sum__CI__VI = 0x0000002b, - DB_PERF_SEL_SH_quads_outstanding_sum__SI = 0x0000002c, - DB_PERF_SEL_DB_CB_lquad_sends__CI__VI = 0x0000002c, - DB_PERF_SEL_DB_CB_lquad_sends__SI = 0x0000002d, - DB_PERF_SEL_DB_CB_lquad_busy__CI__VI = 0x0000002d, - DB_PERF_SEL_DB_CB_lquad_busy__SI = 0x0000002e, - DB_PERF_SEL_DB_CB_lquad_stalls__CI__VI = 0x0000002e, - DB_PERF_SEL_DB_CB_lquad_stalls__SI = 0x0000002f, - DB_PERF_SEL_DB_CB_lquad_quads__CI__VI = 0x0000002f, - DB_PERF_SEL_DB_CB_lquad_quads__SI = 0x00000030, - DB_PERF_SEL_tile_rd_sends__CI__VI = 0x00000030, - DB_PERF_SEL_tile_rd_sends__SI = 0x00000031, - DB_PERF_SEL_mi_tile_rd_outstanding_sum__CI__VI = 0x00000031, - DB_PERF_SEL_mi_tile_rd_outstanding_sum__SI = 0x00000032, - DB_PERF_SEL_quad_rd_sends__CI__VI = 0x00000032, - DB_PERF_SEL_quad_rd_sends__SI = 0x00000033, - DB_PERF_SEL_quad_rd_busy__CI__VI = 0x00000033, - DB_PERF_SEL_quad_rd_busy__SI = 0x00000034, - DB_PERF_SEL_quad_rd_mi_stall__CI__VI = 0x00000034, - DB_PERF_SEL_quad_rd_mi_stall__SI = 0x00000035, - DB_PERF_SEL_quad_rd_rw_collision__CI__VI = 0x00000035, - DB_PERF_SEL_quad_rd_rw_collision__SI = 0x00000036, - DB_PERF_SEL_quad_rd_tag_stall__CI__VI = 0x00000036, - DB_PERF_SEL_quad_rd_tag_stall__SI = 0x00000037, - DB_PERF_SEL_quad_rd_32byte_reqs__CI__VI = 0x00000037, - DB_PERF_SEL_quad_rd_32byte_reqs__SI = 0x00000038, - DB_PERF_SEL_quad_rd_panic__CI__VI = 0x00000038, - DB_PERF_SEL_quad_rd_panic__SI = 0x00000039, - DB_PERF_SEL_mi_quad_rd_outstanding_sum__CI__VI = 0x00000039, - DB_PERF_SEL_mi_quad_rd_outstanding_sum__SI = 0x0000003a, - DB_PERF_SEL_quad_rdret_sends__CI__VI = 0x0000003a, - DB_PERF_SEL_quad_rdret_sends__SI = 0x0000003b, - DB_PERF_SEL_quad_rdret_busy__CI__VI = 0x0000003b, - DB_PERF_SEL_quad_rdret_busy__SI = 0x0000003c, - DB_PERF_SEL_tile_wr_sends__CI__VI = 0x0000003c, - DB_PERF_SEL_tile_wr_sends__SI = 0x0000003d, - DB_PERF_SEL_tile_wr_acks__CI__VI = 0x0000003d, - DB_PERF_SEL_tile_wr_acks__SI = 0x0000003e, - DB_PERF_SEL_mi_tile_wr_outstanding_sum__CI__VI = 0x0000003e, - DB_PERF_SEL_mi_tile_wr_outstanding_sum__SI = 0x0000003f, - DB_PERF_SEL_quad_wr_sends__CI__VI = 0x0000003f, - DB_PERF_SEL_quad_wr_sends__SI = 0x00000040, - DB_PERF_SEL_quad_wr_busy__CI__VI = 0x00000040, - DB_PERF_SEL_quad_wr_busy__SI = 0x00000041, - DB_PERF_SEL_quad_wr_mi_stall__CI__VI = 0x00000041, - DB_PERF_SEL_quad_wr_mi_stall__SI = 0x00000042, - DB_PERF_SEL_quad_wr_coherency_stall__CI__VI = 0x00000042, - DB_PERF_SEL_quad_wr_coherency_stall__SI = 0x00000043, - DB_PERF_SEL_quad_wr_acks__CI__VI = 0x00000043, - DB_PERF_SEL_quad_wr_acks__SI = 0x00000044, - DB_PERF_SEL_mi_quad_wr_outstanding_sum__CI__VI = 0x00000044, - DB_PERF_SEL_mi_quad_wr_outstanding_sum__SI = 0x00000045, - DB_PERF_SEL_Tile_Cache_misses__CI__VI = 0x00000045, - DB_PERF_SEL_Tile_Cache_misses__SI = 0x00000046, - DB_PERF_SEL_Tile_Cache_hits__CI__VI = 0x00000046, - DB_PERF_SEL_Tile_Cache_hits__SI = 0x00000047, - DB_PERF_SEL_Tile_Cache_flushes__CI__VI = 0x00000047, - DB_PERF_SEL_Tile_Cache_flushes__SI = 0x00000048, - DB_PERF_SEL_Tile_Cache_surface_stall__CI__VI = 0x00000048, - DB_PERF_SEL_Tile_Cache_surface_stall__SI = 0x00000049, - DB_PERF_SEL_Tile_Cache_starves__CI__VI = 0x00000049, - DB_PERF_SEL_Tile_Cache_starves__SI = 0x0000004a, - DB_PERF_SEL_Tile_Cache_mem_return_starve__CI__VI = 0x0000004a, - DB_PERF_SEL_Tile_Cache_mem_return_starve__SI = 0x0000004b, - DB_PERF_SEL_tcp_dispatcher_reads__CI__VI = 0x0000004b, - DB_PERF_SEL_tcp_dispatcher_reads__SI = 0x0000004c, - DB_PERF_SEL_tcp_prefetcher_reads__CI__VI = 0x0000004c, - DB_PERF_SEL_tcp_prefetcher_reads__SI = 0x0000004d, - DB_PERF_SEL_tcp_preloader_reads__CI__VI = 0x0000004d, - DB_PERF_SEL_tcp_preloader_reads__SI = 0x0000004e, - DB_PERF_SEL_tcp_dispatcher_flushes__CI__VI = 0x0000004e, - DB_PERF_SEL_tcp_dispatcher_flushes__SI = 0x0000004f, - DB_PERF_SEL_tcp_prefetcher_flushes__CI__VI = 0x0000004f, - DB_PERF_SEL_tcp_prefetcher_flushes__SI = 0x00000050, - DB_PERF_SEL_tcp_preloader_flushes__CI__VI = 0x00000050, - DB_PERF_SEL_tcp_preloader_flushes__SI = 0x00000051, - DB_PERF_SEL_Depth_Tile_Cache_sends__CI__VI = 0x00000051, - DB_PERF_SEL_Depth_Tile_Cache_sends__SI = 0x00000052, - DB_PERF_SEL_Depth_Tile_Cache_busy__CI__VI = 0x00000052, - DB_PERF_SEL_Depth_Tile_Cache_busy__SI = 0x00000053, - DB_PERF_SEL_Depth_Tile_Cache_starves__CI__VI = 0x00000053, - DB_PERF_SEL_Depth_Tile_Cache_starves__SI = 0x00000054, - DB_PERF_SEL_Depth_Tile_Cache_dtile_locked__CI__VI = 0x00000054, - DB_PERF_SEL_Depth_Tile_Cache_dtile_locked__SI = 0x00000055, - DB_PERF_SEL_Depth_Tile_Cache_alloc_stall__CI__VI = 0x00000055, - DB_PERF_SEL_Depth_Tile_Cache_alloc_stall__SI = 0x00000056, - DB_PERF_SEL_Depth_Tile_Cache_misses__CI__VI = 0x00000056, - DB_PERF_SEL_Depth_Tile_Cache_misses__SI = 0x00000057, - DB_PERF_SEL_Depth_Tile_Cache_hits__CI__VI = 0x00000057, - DB_PERF_SEL_Depth_Tile_Cache_hits__SI = 0x00000058, - DB_PERF_SEL_Depth_Tile_Cache_flushes__CI__VI = 0x00000058, - DB_PERF_SEL_Depth_Tile_Cache_flushes__SI = 0x00000059, - DB_PERF_SEL_Depth_Tile_Cache_noop_tile__CI__VI = 0x00000059, - DB_PERF_SEL_Depth_Tile_Cache_noop_tile__SI = 0x0000005a, - DB_PERF_SEL_Depth_Tile_Cache_detailed_noop__CI__VI = 0x0000005a, - DB_PERF_SEL_Depth_Tile_Cache_detailed_noop__SI = 0x0000005b, - DB_PERF_SEL_Depth_Tile_Cache_event__CI__VI = 0x0000005b, - DB_PERF_SEL_Depth_Tile_Cache_event__SI = 0x0000005c, - DB_PERF_SEL_Depth_Tile_Cache_tile_frees__CI__VI = 0x0000005c, - DB_PERF_SEL_Depth_Tile_Cache_tile_frees__SI = 0x0000005d, - DB_PERF_SEL_Depth_Tile_Cache_data_frees__CI__VI = 0x0000005d, - DB_PERF_SEL_Depth_Tile_Cache_data_frees__SI = 0x0000005e, - DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve__CI__VI = 0x0000005e, - DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve__SI = 0x0000005f, - DB_PERF_SEL_Stencil_Cache_misses__CI__VI = 0x0000005f, - DB_PERF_SEL_Stencil_Cache_misses__SI = 0x00000060, - DB_PERF_SEL_Stencil_Cache_hits__CI__VI = 0x00000060, - DB_PERF_SEL_Stencil_Cache_hits__SI = 0x00000061, - DB_PERF_SEL_Stencil_Cache_flushes__CI__VI = 0x00000061, - DB_PERF_SEL_Stencil_Cache_flushes__SI = 0x00000062, - DB_PERF_SEL_Stencil_Cache_starves__CI__VI = 0x00000062, - DB_PERF_SEL_Stencil_Cache_starves__SI = 0x00000063, - DB_PERF_SEL_Stencil_Cache_frees__CI__VI = 0x00000063, - DB_PERF_SEL_Stencil_Cache_frees__SI = 0x00000064, - DB_PERF_SEL_Z_Cache_separate_Z_misses__CI__VI = 0x00000064, - DB_PERF_SEL_Z_Cache_separate_Z_misses__SI = 0x00000065, - DB_PERF_SEL_Z_Cache_separate_Z_hits__CI__VI = 0x00000065, - DB_PERF_SEL_Z_Cache_separate_Z_hits__SI = 0x00000066, - DB_PERF_SEL_Z_Cache_separate_Z_flushes__CI__VI = 0x00000066, - DB_PERF_SEL_Z_Cache_separate_Z_flushes__SI = 0x00000067, - DB_PERF_SEL_Z_Cache_separate_Z_starves__CI__VI = 0x00000067, - DB_PERF_SEL_Z_Cache_separate_Z_starves__SI = 0x00000068, - DB_PERF_SEL_Z_Cache_pmask_misses__CI__VI = 0x00000068, - DB_PERF_SEL_Z_Cache_pmask_misses__SI = 0x00000069, - DB_PERF_SEL_Z_Cache_pmask_hits__CI__VI = 0x00000069, - DB_PERF_SEL_Z_Cache_pmask_hits__SI = 0x0000006a, - DB_PERF_SEL_Z_Cache_pmask_flushes__CI__VI = 0x0000006a, - DB_PERF_SEL_Z_Cache_pmask_flushes__SI = 0x0000006b, - DB_PERF_SEL_Z_Cache_pmask_starves__CI__VI = 0x0000006b, - DB_PERF_SEL_Z_Cache_pmask_starves__SI = 0x0000006c, - DB_PERF_SEL_Z_Cache_frees__CI__VI = 0x0000006c, - DB_PERF_SEL_Z_Cache_frees__SI = 0x0000006d, - DB_PERF_SEL_Plane_Cache_misses__CI__VI = 0x0000006d, - DB_PERF_SEL_Plane_Cache_misses__SI = 0x0000006e, - DB_PERF_SEL_Plane_Cache_hits__CI__VI = 0x0000006e, - DB_PERF_SEL_Plane_Cache_hits__SI = 0x0000006f, - DB_PERF_SEL_Plane_Cache_flushes__CI__VI = 0x0000006f, - DB_PERF_SEL_Plane_Cache_flushes__SI = 0x00000070, - DB_PERF_SEL_Plane_Cache_starves__CI__VI = 0x00000070, - DB_PERF_SEL_Plane_Cache_starves__SI = 0x00000071, - DB_PERF_SEL_Plane_Cache_frees__CI__VI = 0x00000071, - DB_PERF_SEL_Plane_Cache_frees__SI = 0x00000072, - DB_PERF_SEL_flush_expanded_stencil__CI__VI = 0x00000072, - DB_PERF_SEL_flush_expanded_stencil__SI = 0x00000073, - DB_PERF_SEL_flush_compressed_stencil__CI__VI = 0x00000073, - DB_PERF_SEL_flush_compressed_stencil__SI = 0x00000074, - DB_PERF_SEL_flush_single_stencil__CI__VI = 0x00000074, - DB_PERF_SEL_flush_single_stencil__SI = 0x00000075, - DB_PERF_SEL_planes_flushed__CI__VI = 0x00000075, - DB_PERF_SEL_planes_flushed__SI = 0x00000076, - DB_PERF_SEL_flush_1plane__CI__VI = 0x00000076, - DB_PERF_SEL_flush_1plane__SI = 0x00000077, - DB_PERF_SEL_flush_2plane__CI__VI = 0x00000077, - DB_PERF_SEL_flush_2plane__SI = 0x00000078, - DB_PERF_SEL_flush_3plane__CI__VI = 0x00000078, - DB_PERF_SEL_flush_3plane__SI = 0x00000079, - DB_PERF_SEL_flush_4plane__CI__VI = 0x00000079, - DB_PERF_SEL_flush_4plane__SI = 0x0000007a, - DB_PERF_SEL_flush_5plane__CI__VI = 0x0000007a, - DB_PERF_SEL_flush_5plane__SI = 0x0000007b, - DB_PERF_SEL_flush_6plane__CI__VI = 0x0000007b, - DB_PERF_SEL_flush_6plane__SI = 0x0000007c, - DB_PERF_SEL_flush_7plane__CI__VI = 0x0000007c, - DB_PERF_SEL_flush_7plane__SI = 0x0000007d, - DB_PERF_SEL_flush_8plane__CI__VI = 0x0000007d, - DB_PERF_SEL_flush_8plane__SI = 0x0000007e, - DB_PERF_SEL_flush_9plane__CI__VI = 0x0000007e, - DB_PERF_SEL_flush_9plane__SI = 0x0000007f, - DB_PERF_SEL_flush_10plane__CI__VI = 0x0000007f, - DB_PERF_SEL_flush_10plane__SI = 0x00000080, - DB_PERF_SEL_flush_11plane__CI__VI = 0x00000080, - DB_PERF_SEL_flush_11plane__SI = 0x00000081, - DB_PERF_SEL_flush_12plane__CI__VI = 0x00000081, - DB_PERF_SEL_flush_12plane__SI = 0x00000082, - DB_PERF_SEL_flush_13plane__CI__VI = 0x00000082, - DB_PERF_SEL_flush_13plane__SI = 0x00000083, - DB_PERF_SEL_flush_14plane__CI__VI = 0x00000083, - DB_PERF_SEL_flush_14plane__SI = 0x00000084, - DB_PERF_SEL_flush_15plane__CI__VI = 0x00000084, - DB_PERF_SEL_flush_15plane__SI = 0x00000085, - DB_PERF_SEL_flush_16plane__CI__VI = 0x00000085, - DB_PERF_SEL_flush_16plane__SI = 0x00000086, - DB_PERF_SEL_flush_expanded_z__CI__VI = 0x00000086, - DB_PERF_SEL_flush_expanded_z__SI = 0x00000087, - DB_PERF_SEL_earlyZ_waiting_for_postZ_done__CI__VI = 0x00000087, - DB_PERF_SEL_earlyZ_waiting_for_postZ_done__SI = 0x00000088, - DB_PERF_SEL_reZ_waiting_for_postZ_done__CI__VI = 0x00000088, - DB_PERF_SEL_reZ_waiting_for_postZ_done__SI = 0x00000089, - DB_PERF_SEL_dk_tile_sends__CI__VI = 0x00000089, - DB_PERF_SEL_dk_tile_sends__SI = 0x0000008a, - DB_PERF_SEL_dk_tile_busy__CI__VI = 0x0000008a, - DB_PERF_SEL_dk_tile_busy__SI = 0x0000008b, - DB_PERF_SEL_dk_tile_quad_starves__CI__VI = 0x0000008b, - DB_PERF_SEL_dk_tile_quad_starves__SI = 0x0000008c, - DB_PERF_SEL_dk_tile_stalls__CI__VI = 0x0000008c, - DB_PERF_SEL_dk_tile_stalls__SI = 0x0000008d, - DB_PERF_SEL_dk_squad_sends__CI__VI = 0x0000008d, - DB_PERF_SEL_dk_squad_sends__SI = 0x0000008e, - DB_PERF_SEL_dk_squad_busy__CI__VI = 0x0000008e, - DB_PERF_SEL_dk_squad_busy__SI = 0x0000008f, - DB_PERF_SEL_dk_squad_stalls__CI__VI = 0x0000008f, - DB_PERF_SEL_dk_squad_stalls__SI = 0x00000090, - DB_PERF_SEL_Op_Pipe_Busy__CI__VI = 0x00000090, - DB_PERF_SEL_Op_Pipe_Busy__SI = 0x00000091, - DB_PERF_SEL_Op_Pipe_MC_Read_stall__CI__VI = 0x00000091, - DB_PERF_SEL_Op_Pipe_MC_Read_stall__SI = 0x00000092, - DB_PERF_SEL_qc_busy__CI__VI = 0x00000092, - DB_PERF_SEL_qc_busy__SI = 0x00000093, - DB_PERF_SEL_qc_xfc__CI__VI = 0x00000093, - DB_PERF_SEL_qc_xfc__SI = 0x00000094, - DB_PERF_SEL_qc_conflicts__CI__VI = 0x00000094, - DB_PERF_SEL_qc_conflicts__SI = 0x00000095, - DB_PERF_SEL_qc_full_stall__CI__VI = 0x00000095, - DB_PERF_SEL_qc_full_stall__SI = 0x00000096, - DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ__CI__VI = 0x00000096, - DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ__SI = 0x00000097, - DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ__CI__VI = 0x00000097, - DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ__SI = 0x00000098, - DB_PERF_SEL_tsc_insert_summarize_stall__CI__VI = 0x00000098, - DB_PERF_SEL_tsc_insert_summarize_stall__SI = 0x00000099, - DB_PERF_SEL_tl_busy__CI__VI = 0x00000099, - DB_PERF_SEL_tl_busy__SI = 0x0000009a, - DB_PERF_SEL_tl_dtc_read_starved__CI__VI = 0x0000009a, - DB_PERF_SEL_tl_dtc_read_starved__SI = 0x0000009b, - DB_PERF_SEL_tl_z_fetch_stall__CI__VI = 0x0000009b, - DB_PERF_SEL_tl_z_fetch_stall__SI = 0x0000009c, - DB_PERF_SEL_tl_stencil_stall__CI__VI = 0x0000009c, - DB_PERF_SEL_tl_stencil_stall__SI = 0x0000009d, - DB_PERF_SEL_tl_z_decompress_stall__CI__VI = 0x0000009d, - DB_PERF_SEL_tl_z_decompress_stall__SI = 0x0000009e, - DB_PERF_SEL_tl_stencil_locked_stall__CI__VI = 0x0000009e, - DB_PERF_SEL_tl_stencil_locked_stall__SI = 0x0000009f, - DB_PERF_SEL_tl_events__CI__VI = 0x0000009f, - DB_PERF_SEL_tl_events__SI = 0x000000a0, - DB_PERF_SEL_tl_summarize_squads__CI__VI = 0x000000a0, - DB_PERF_SEL_tl_summarize_squads__SI = 0x000000a1, - DB_PERF_SEL_tl_flush_expand_squads__CI__VI = 0x000000a1, - DB_PERF_SEL_tl_flush_expand_squads__SI = 0x000000a2, - DB_PERF_SEL_tl_expand_squads__CI__VI = 0x000000a2, - DB_PERF_SEL_tl_expand_squads__SI = 0x000000a3, - DB_PERF_SEL_tl_preZ_squads__CI__VI = 0x000000a3, - DB_PERF_SEL_tl_preZ_squads__SI = 0x000000a4, - DB_PERF_SEL_tl_postZ_squads__CI__VI = 0x000000a4, - DB_PERF_SEL_tl_postZ_squads__SI = 0x000000a5, - DB_PERF_SEL_tl_preZ_noop_squads__CI__VI = 0x000000a5, - DB_PERF_SEL_tl_preZ_noop_squads__SI = 0x000000a6, - DB_PERF_SEL_tl_postZ_noop_squads__CI__VI = 0x000000a6, - DB_PERF_SEL_tl_postZ_noop_squads__SI = 0x000000a7, - DB_PERF_SEL_tl_tile_ops__CI__VI = 0x000000a7, - DB_PERF_SEL_UNUSED1__SI = 0x000000a8, - DB_PERF_SEL_tl_in_xfc__CI__VI = 0x000000a8, - DB_PERF_SEL_tl_tile_ops__SI = 0x000000a9, - DB_PERF_SEL_tl_in_single_stencil_expand_stall__CI__VI = 0x000000a9, - DB_PERF_SEL_tl_in_xfc__SI = 0x000000aa, - DB_PERF_SEL_tl_in_fast_z_stall__CI__VI = 0x000000aa, - DB_PERF_SEL_tl_in_single_stencil_expand_stall__SI = 0x000000ab, - DB_PERF_SEL_tl_out_xfc__CI__VI = 0x000000ab, - DB_PERF_SEL_UNUSED2__SI = 0x000000ac, - DB_PERF_SEL_tl_out_squads__CI__VI = 0x000000ac, - DB_PERF_SEL_tl_in_fast_z_stall__SI = 0x000000ad, - DB_PERF_SEL_zf_plane_multicycle__CI__VI = 0x000000ad, - DB_PERF_SEL_tl_out_xfc__SI = 0x000000ae, - DB_PERF_SEL_PostZ_Samples_passing_Z__CI__VI = 0x000000ae, - DB_PERF_SEL_tl_out_squads__SI = 0x000000af, - DB_PERF_SEL_PostZ_Samples_failing_Z__CI__VI = 0x000000af, - DB_PERF_SEL_zf_plane_multicycle__SI = 0x000000b0, - DB_PERF_SEL_PostZ_Samples_failing_S__CI__VI = 0x000000b0, - DB_PERF_SEL_PostZ_Samples_passing_Z__SI = 0x000000b1, - DB_PERF_SEL_PreZ_Samples_passing_Z__CI__VI = 0x000000b1, - DB_PERF_SEL_PostZ_Samples_failing_Z__SI = 0x000000b2, - DB_PERF_SEL_PreZ_Samples_failing_Z__CI__VI = 0x000000b2, - DB_PERF_SEL_PostZ_Samples_failing_S__SI = 0x000000b3, - DB_PERF_SEL_PreZ_Samples_failing_S__CI__VI = 0x000000b3, - DB_PERF_SEL_PreZ_Samples_passing_Z__SI = 0x000000b4, - DB_PERF_SEL_ts_tc_update_stall__CI__VI = 0x000000b4, - DB_PERF_SEL_PreZ_Samples_failing_Z__SI = 0x000000b5, - DB_PERF_SEL_sc_kick_start__CI__VI = 0x000000b5, - DB_PERF_SEL_PreZ_Samples_failing_S__SI = 0x000000b6, - DB_PERF_SEL_sc_kick_end__CI__VI = 0x000000b6, - DB_PERF_SEL_ts_tc_update_stall__SI = 0x000000b7, - DB_PERF_SEL_clock_reg_active__CI__VI = 0x000000b7, - DB_PERF_SEL_sc_kick_start__SI = 0x000000b8, - DB_PERF_SEL_clock_main_active__CI__VI = 0x000000b8, - DB_PERF_SEL_sc_kick_end__SI = 0x000000b9, - DB_PERF_SEL_clock_mem_export_active__CI__VI = 0x000000b9, - DB_PERF_SEL_clock_reg_active__SI = 0x000000ba, - DB_PERF_SEL_esr_ps_out_busy__CI__VI = 0x000000ba, - DB_PERF_SEL_clock_main_active__SI = 0x000000bb, - DB_PERF_SEL_esr_ps_lqf_busy__CI__VI = 0x000000bb, - DB_PERF_SEL_clock_mem_export_active__SI = 0x000000bc, - DB_PERF_SEL_esr_ps_lqf_stall__CI__VI = 0x000000bc, - DB_PERF_SEL_esr_ps_out_busy__SI = 0x000000bd, - DB_PERF_SEL_etr_out_send__CI__VI = 0x000000bd, - DB_PERF_SEL_esr_ps_lqf_busy__SI = 0x000000be, - DB_PERF_SEL_etr_out_busy__CI__VI = 0x000000be, - DB_PERF_SEL_esr_ps_lqf_stall__SI = 0x000000bf, - DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall__CI__VI = 0x000000bf, - DB_PERF_SEL_etr_out_send__SI = 0x000000c0, - DB_PERF_SEL_etr_out_cb_tile_stall__CI__VI = 0x000000c0, - DB_PERF_SEL_etr_out_busy__SI = 0x000000c1, - DB_PERF_SEL_etr_out_esr_stall__CI__VI = 0x000000c1, - DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall__SI = 0x000000c2, - DB_PERF_SEL_esr_ps_sqq_busy__CI__VI = 0x000000c2, - DB_PERF_SEL_etr_out_cb_tile_stall__SI = 0x000000c3, - DB_PERF_SEL_esr_ps_sqq_stall__CI__VI = 0x000000c3, - DB_PERF_SEL_etr_out_esr_stall__SI = 0x000000c4, - DB_PERF_SEL_esr_eot_fwd_busy__CI__VI = 0x000000c4, - DB_PERF_SEL_esr_ps_sqq_busy__SI = 0x000000c5, - DB_PERF_SEL_esr_eot_fwd_holding_squad__CI__VI = 0x000000c5, - DB_PERF_SEL_esr_ps_sqq_stall__SI = 0x000000c6, - DB_PERF_SEL_esr_eot_fwd_forward__CI__VI = 0x000000c6, - DB_PERF_SEL_esr_eot_fwd_busy__SI = 0x000000c7, - DB_PERF_SEL_esr_sqq_zi_busy__CI__VI = 0x000000c7, - DB_PERF_SEL_esr_eot_fwd_holding_squad__SI = 0x000000c8, - DB_PERF_SEL_esr_sqq_zi_stall__CI__VI = 0x000000c8, - DB_PERF_SEL_esr_eot_fwd_forward__SI = 0x000000c9, - DB_PERF_SEL_postzl_sq_pt_busy__CI__VI = 0x000000c9, - DB_PERF_SEL_esr_sqq_zi_busy__SI = 0x000000ca, - DB_PERF_SEL_postzl_sq_pt_stall__CI__VI = 0x000000ca, - DB_PERF_SEL_esr_sqq_zi_stall__SI = 0x000000cb, - DB_PERF_SEL_postzl_se_busy__CI__VI = 0x000000cb, - DB_PERF_SEL_postzl_sq_pt_busy__SI = 0x000000cc, - DB_PERF_SEL_postzl_se_stall__CI__VI = 0x000000cc, - DB_PERF_SEL_postzl_sq_pt_stall__SI = 0x000000cd, - DB_PERF_SEL_postzl_partial_launch__CI__VI = 0x000000cd, - DB_PERF_SEL_postzl_se_busy__SI = 0x000000ce, - DB_PERF_SEL_postzl_full_launch__CI__VI = 0x000000ce, - DB_PERF_SEL_postzl_se_stall__SI = 0x000000cf, - DB_PERF_SEL_postzl_partial_waiting__CI__VI = 0x000000cf, - DB_PERF_SEL_postzl_partial_launch__SI = 0x000000d0, - DB_PERF_SEL_postzl_tile_mem_stall__CI__VI = 0x000000d0, - DB_PERF_SEL_postzl_full_launch__SI = 0x000000d1, - DB_PERF_SEL_postzl_tile_init_stall__CI__VI = 0x000000d1, - DB_PERF_SEL_postzl_partial_waiting__SI = 0x000000d2, - DB_PEFF_SEL_prezl_tile_mem_stall__CI__VI = 0x000000d2, - DB_PERF_SEL_postzl_tile_mem_stall__SI = 0x000000d3, - DB_PERF_SEL_prezl_tile_init_stall__CI__VI = 0x000000d3, - DB_PERF_SEL_postzl_tile_init_stall__SI = 0x000000d4, - DB_PERF_SEL_dtt_sm_clash_stall__CI__VI = 0x000000d4, - DB_PEFF_SEL_prezl_tile_mem_stall__SI = 0x000000d5, - DB_PERF_SEL_dtt_sm_slot_stall__CI__VI = 0x000000d5, - DB_PERF_SEL_prezl_tile_init_stall__SI = 0x000000d6, - DB_PERF_SEL_dtt_sm_miss_stall__CI__VI = 0x000000d6, - DB_PERF_SEL_dtt_sm_clash_stall__SI = 0x000000d7, - DB_PERF_SEL_mi_rdreq_busy__CI__VI = 0x000000d7, - DB_PERF_SEL_dtt_sm_slot_stall__SI = 0x000000d8, - DB_PERF_SEL_mi_rdreq_stall__CI__VI = 0x000000d8, - DB_PERF_SEL_dtt_sm_miss_stall__SI = 0x000000d9, - DB_PERF_SEL_mi_wrreq_busy__CI__VI = 0x000000d9, - DB_PERF_SEL_mi_rdreq_busy__SI = 0x000000da, - DB_PERF_SEL_mi_wrreq_stall__CI__VI = 0x000000da, - DB_PERF_SEL_mi_rdreq_stall__SI = 0x000000db, - DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop__CI__VI = 0x000000db, - DB_PERF_SEL_mi_wrreq_busy__SI = 0x000000dc, - DB_PERF_SEL_dkg_tile_rate_tile__CI__VI = 0x000000dc, - DB_PERF_SEL_mi_wrreq_stall__SI = 0x000000dd, - DB_PERF_SEL_prezl_src_in_sends__CI__VI = 0x000000dd, - DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop__SI = 0x000000de, - DB_PERF_SEL_prezl_src_in_stall__CI__VI = 0x000000de, - DB_PERF_SEL_dkg_tile_rate_tile__SI = 0x000000df, - DB_PERF_SEL_prezl_src_in_squads__CI__VI = 0x000000df, - DB_PERF_SEL_prezl_src_in_sends__SI = 0x000000e0, - DB_PERF_SEL_prezl_src_in_squads_unrolled__CI__VI = 0x000000e0, - DB_PERF_SEL_prezl_src_in_stall__SI = 0x000000e1, - DB_PERF_SEL_prezl_src_in_tile_rate__CI__VI = 0x000000e1, - DB_PERF_SEL_prezl_src_in_squads__SI = 0x000000e2, - DB_PERF_SEL_prezl_src_in_tile_rate_unrolled__CI__VI = 0x000000e2, - DB_PERF_SEL_prezl_src_in_squads_unrolled__SI = 0x000000e3, - DB_PERF_SEL_prezl_src_out_stall__CI__VI = 0x000000e3, - DB_PERF_SEL_prezl_src_in_tile_rate__SI = 0x000000e4, - DB_PERF_SEL_postzl_src_in_sends__CI__VI = 0x000000e4, - DB_PERF_SEL_prezl_src_in_tile_rate_unrolled__SI = 0x000000e5, - DB_PERF_SEL_postzl_src_in_stall__CI__VI = 0x000000e5, - DB_PERF_SEL_prezl_src_out_stall__SI = 0x000000e6, - DB_PERF_SEL_postzl_src_in_squads__CI__VI = 0x000000e6, - DB_PERF_SEL_postzl_src_in_sends__SI = 0x000000e7, - DB_PERF_SEL_postzl_src_in_squads_unrolled__CI__VI = 0x000000e7, - DB_PERF_SEL_postzl_src_in_stall__SI = 0x000000e8, - DB_PERF_SEL_postzl_src_in_tile_rate__CI__VI = 0x000000e8, - DB_PERF_SEL_postzl_src_in_squads__SI = 0x000000e9, - DB_PERF_SEL_postzl_src_in_tile_rate_unrolled__CI__VI = 0x000000e9, - DB_PERF_SEL_postzl_src_in_squads_unrolled__SI = 0x000000ea, - DB_PERF_SEL_postzl_src_out_stall__CI__VI = 0x000000ea, - DB_PERF_SEL_postzl_src_in_tile_rate__SI = 0x000000eb, - DB_PERF_SEL_esr_ps_src_in_sends__CI__VI = 0x000000eb, - DB_PERF_SEL_postzl_src_in_tile_rate_unrolled__SI = 0x000000ec, - DB_PERF_SEL_esr_ps_src_in_stall__CI__VI = 0x000000ec, - DB_PERF_SEL_postzl_src_out_stall__SI = 0x000000ed, - DB_PERF_SEL_esr_ps_src_in_squads__CI__VI = 0x000000ed, - DB_PERF_SEL_esr_ps_src_in_sends__SI = 0x000000ee, - DB_PERF_SEL_esr_ps_src_in_squads_unrolled__CI__VI = 0x000000ee, - DB_PERF_SEL_esr_ps_src_in_stall__SI = 0x000000ef, - DB_PERF_SEL_esr_ps_src_in_tile_rate__CI__VI = 0x000000ef, - DB_PERF_SEL_esr_ps_src_in_squads__SI = 0x000000f0, - DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled__CI__VI = 0x000000f0, - DB_PERF_SEL_esr_ps_src_in_squads_unrolled__SI = 0x000000f1, - DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate__CI__VI = 0x000000f1, - DB_PERF_SEL_esr_ps_src_in_tile_rate__SI = 0x000000f2, - DB_PERF_SEL_esr_ps_src_out_stall__CI__VI = 0x000000f2, - DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled__SI = 0x000000f3, - DB_PERF_SEL_depth_bounds_qtiles_culled__CI__VI = 0x000000f3, - DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate__SI = 0x000000f4, - DB_PERF_SEL_PreZ_Samples_failing_DB__CI__VI = 0x000000f4, - DB_PERF_SEL_esr_ps_src_out_stall__SI = 0x000000f5, - DB_PERF_SEL_PostZ_Samples_failing_DB__CI__VI = 0x000000f5, - DB_PERF_SEL_depth_bounds_qtiles_culled__SI = 0x000000f6, - DB_PERF_SEL_flush_compressed__CI__VI = 0x000000f6, - DB_PERF_SEL_PreZ_Samples_failing_DB__SI = 0x000000f7, - DB_PERF_SEL_flush_plane_le4__CI__VI = 0x000000f7, - DB_PERF_SEL_PostZ_Samples_failing_DB__SI = 0x000000f8, - DB_PERF_SEL_tiles_z_fully_summarized__CI__VI = 0x000000f8, - DB_PERF_SEL_tiles_stencil_fully_summarized__CI__VI = 0x000000f9, - DB_PERF_SEL_tiles_z_clear_on_expclear__CI__VI = 0x000000fa, - DB_PERF_SEL_tiles_s_clear_on_expclear__CI__VI = 0x000000fb, - DB_PERF_SEL_tiles_decomp_on_expclear__CI__VI = 0x000000fc, - DB_PERF_SEL_tiles_compressed_to_decompressed__CI__VI = 0x000000fd, - DB_PERF_SEL_Op_Pipe_Prez_Busy__CI__VI = 0x000000fe, - DB_PERF_SEL_Op_Pipe_Postz_Busy__CI__VI = 0x000000ff, - DB_PERF_SEL_di_dt_stall__CI__VI = 0x00000100, - DB_PERF_SEL_DB_SC_quad_double_quad__VI = 0x00000101, - DB_PERF_SEL_SX_DB_quad_export_quads__VI = 0x00000102, - DB_PERF_SEL_SX_DB_quad_double_format__VI = 0x00000103, - DB_PERF_SEL_SX_DB_quad_fast_format__VI = 0x00000104, - DB_PERF_SEL_SX_DB_quad_slow_format__VI = 0x00000105, - DB_PERF_SEL_DB_CB_lquad_export_quads__VI = 0x00000106, - DB_PERF_SEL_DB_CB_lquad_double_format__VI = 0x00000107, - DB_PERF_SEL_DB_CB_lquad_fast_format__VI = 0x00000108, - DB_PERF_SEL_DB_CB_lquad_slow_format__VI = 0x00000109, -} PerfCounter_Vals; - -typedef enum PipeConfig { - ADDR_SURF_P2 = 0x00000000, - ADDR_SURF_P2_RESERVED0 = 0x00000001, - ADDR_SURF_P2_RESERVED1 = 0x00000002, - ADDR_SURF_P2_RESERVED2 = 0x00000003, - ADDR_SURF_P4_8x16 = 0x00000004, - ADDR_SURF_P4_16x16 = 0x00000005, - ADDR_SURF_P4_16x32 = 0x00000006, - ADDR_SURF_P4_32x32 = 0x00000007, - ADDR_SURF_P8_16x16_8x16 = 0x00000008, - ADDR_SURF_P8_16x32_8x16 = 0x00000009, - ADDR_SURF_P8_32x32_8x16 = 0x0000000a, - ADDR_SURF_P8_16x32_16x16 = 0x0000000b, - ADDR_SURF_P8_32x32_16x16 = 0x0000000c, - ADDR_SURF_P8_32x32_16x32 = 0x0000000d, - ADDR_SURF_P8_32x64_32x32 = 0x0000000e, - ADDR_SURF_P8_RESERVED0__CI__VI = 0x0000000f, - ADDR_SURF_P16_32x32_8x16__CI__VI = 0x00000010, - ADDR_SURF_P16_32x32_16x16__CI__VI = 0x00000011, -} PipeConfig; - -typedef enum PipeInterleaveSize { - ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, - ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, -} PipeInterleaveSize; - -typedef enum PipeTiling { - CONFIG_1_PIPE = 0x00000000, - CONFIG_2_PIPE = 0x00000001, - CONFIG_4_PIPE = 0x00000002, - CONFIG_8_PIPE = 0x00000003, -} PipeTiling; - -typedef enum PixelPipeCounterId { - PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, - PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, - PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, - PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, - PIXEL_PIPE_SCREEN_MIN_EXTENTS_0__VI = 0x00000004, - PIXEL_PIPE_SCREEN_MAX_EXTENTS_0__VI = 0x00000005, - PIXEL_PIPE_SCREEN_MIN_EXTENTS_1__VI = 0x00000006, - PIXEL_PIPE_SCREEN_MAX_EXTENTS_1__VI = 0x00000007, -} PixelPipeCounterId; - -typedef enum PixelPipeStride { - PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, - PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, - PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, - PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, -} PixelPipeStride; - -typedef enum PkrMap { - RASTER_CONFIG_PKR_MAP_0 = 0x00000000, - RASTER_CONFIG_PKR_MAP_1 = 0x00000001, - RASTER_CONFIG_PKR_MAP_2 = 0x00000002, - RASTER_CONFIG_PKR_MAP_3 = 0x00000003, -} PkrMap; - -typedef enum PkrXsel { - RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, - RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, - RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, - RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, -} PkrXsel; - -typedef enum PkrXsel2 { - RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, - RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, - RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, - RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, -} PkrXsel2; - -typedef enum PkrYsel { - RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, - RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, - RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, - RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, -} PkrYsel; - -typedef enum QuadExportFormat { - EXPORT_UNUSED = 0x00000000, - EXPORT_32_R = 0x00000001, - EXPORT_32_GR = 0x00000002, - EXPORT_32_AR = 0x00000003, - EXPORT_FP16_ABGR = 0x00000004, - EXPORT_UNSIGNED16_ABGR = 0x00000005, - EXPORT_SIGNED16_ABGR = 0x00000006, - EXPORT_32_ABGR = 0x00000007, - EXPORT_32BPP_8PIX__VI = 0x00000008, - EXPORT_16_16_UNSIGNED_8PIX__VI = 0x00000009, - EXPORT_16_16_SIGNED_8PIX__VI = 0x0000000a, - EXPORT_16_16_FLOAT_8PIX__VI = 0x0000000b, -} QuadExportFormat; - -typedef enum QuadExportFormatOld { - EXPORT_4P_32BPC_ABGR = 0x00000000, - EXPORT_4P_16BPC_ABGR = 0x00000001, - EXPORT_4P_32BPC_GR = 0x00000002, - EXPORT_4P_32BPC_AR = 0x00000003, - EXPORT_2P_32BPC_ABGR = 0x00000004, - EXPORT_8P_32BPC_R = 0x00000005, -} QuadExportFormatOld; - -typedef enum RCU_FCTRL_CID { - RCU__CCFID = 0x00000000, - RCU__DRMID = 0x00000001, - RCU__UVDID = 0x00000002, - RCU__HDCID = 0x00000003, - RCU__SPRID = 0x00000004, -} RCU_FCTRL_CID; - -typedef enum RCU_UC_INSTRS { - RCU__NOP = 0x00000000, - RCU__RDS2L = 0x00000001, - RCU__WRL2S = 0x00000002, - RCU__RDCMP = 0x00000003, - RCU__WRCLA = 0x00000004, - RCU__ECMP = 0x00000005, - RCU__WAITOE = 0x00000006, - RCU__CJUMP = 0x00000007, - RCU__JUMP = 0x00000008, - RCU__WAIT = 0x00000009, - RCU__ROMRD = 0x0000000a, - RCU__EFUSE = 0x0000000b, - RCU__EXIT = 0x0000000f, -} RCU_UC_INSTRS; - -typedef enum RCU_UC_REG_ADR { - RCU_DATAREG0 = 0x00000000, - RCU_DATAREG1 = 0x00000001, - RCU_DATAREG2 = 0x00000002, - RCU_DATAREG3 = 0x00000003, - RCU_DATAREG4 = 0x00000004, - RCU_DATAREG5 = 0x00000005, - RCU_DATAREG6 = 0x00000006, - RCU_DATAREG7 = 0x00000007, - RCU_DATAREG8 = 0x00000008, - RCU_DATAREG9 = 0x00000009, - RCU_DATAREG10 = 0x0000000a, - RCU_DATAREG11 = 0x0000000b, - RCU_DATAREG12 = 0x0000000c, - RCU_DATAREG13 = 0x0000000d, - RCU_DATAREG14 = 0x0000000e, - RCU_DATAREG15 = 0x0000000f, - RCU_DATAREG16 = 0x00000010, - RCU_DATAREG17 = 0x00000011, - RCU_DATAREG18 = 0x00000012, - RCU_DATAREG19 = 0x00000013, - RCU_DATAREG20 = 0x00000014, - RCU_DATAREG21 = 0x00000015, - RCU_DATAREG22 = 0x00000016, - RCU_DATAREG23 = 0x00000017, - RCU_DATAREG24 = 0x00000018, - RCU_DATAREG25 = 0x00000019, - RCU_DATAREG26 = 0x0000001a, - RCU_DATAREG27 = 0x0000001b, - RCU_DATAREG28 = 0x0000001c, - RCU_DATAREG29 = 0x0000001d, - RCU_CCREG0 = 0x00000020, - RCU_CCREG1 = 0x00000021, - RCU_CCREG2 = 0x00000022, - RCU_CCREG3 = 0x00000023, - RCU_CCREG4 = 0x00000024, - RCU_CCREG5 = 0x00000025, - RCU_CCREG6 = 0x00000026, - RCU_CCREG7 = 0x00000027, - RCU_CCREG_RCUID = 0x00000028, - RCU_CCREG_RCUDC = 0x00000029, - RCU_CCREG_RCUMISC = 0x0000002a, - RCU_CCREG_RCUCG = 0x0000002b, - RCU_CCREG12 = 0x0000002c, - RCU_CCREG13 = 0x0000002d, - RCU_CCREG14 = 0x0000002e, - RCU_CCREG15 = 0x0000002f, - RCU_CCREG16 = 0x00000030, - RCU_CCREG17 = 0x00000031, - RCU_CCREG18 = 0x00000032, - RCU_CCREG19 = 0x00000033, - RCU_CCREG20 = 0x00000034, - RCU_CCREG21 = 0x00000035, - RCU_CCREG22 = 0x00000036, - RCU_CCREG23 = 0x00000037, - RCU_CCREG24 = 0x00000038, - RCU_CCREG25 = 0x00000039, - RCU_CCREG26 = 0x0000003a, - RCU_CCREG27 = 0x0000003b, - RCU_CCREG28 = 0x0000003c, - RCU_CCREG29 = 0x0000003d, - RCU_CCREG30 = 0x0000003e, - RCU_CCREG31 = 0x0000003f, - RCU_CCREG32 = 0x00000040, - RCU_CCREG33 = 0x00000041, - RCU_CCREG34 = 0x00000042, - RCU_CCREG35 = 0x00000043, - RCU_CCREG36 = 0x00000044, - RCU_CCREG37 = 0x00000045, - RCU_CCREG38 = 0x00000046, - RCU_CCREG39 = 0x00000047, - RCU_CCREG40 = 0x00000048, - RCU_CCREG41 = 0x00000049, - RCU_CCREG42 = 0x0000004a, - RCU_INSTREG0 = 0x00000080, - RCU_INSTREG63 = 0x000000bf, -} RCU_UC_REG_ADR; - -typedef enum RbMap { - RASTER_CONFIG_RB_MAP_0 = 0x00000000, - RASTER_CONFIG_RB_MAP_1 = 0x00000001, - RASTER_CONFIG_RB_MAP_2 = 0x00000002, - RASTER_CONFIG_RB_MAP_3 = 0x00000003, -} RbMap; - -typedef enum RbXsel { - RASTER_CONFIG_RB_XSEL_0 = 0x00000000, - RASTER_CONFIG_RB_XSEL_1 = 0x00000001, -} RbXsel; - -typedef enum RbXsel2 { - RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, - RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, - RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, - RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, -} RbXsel2; - -typedef enum RbYsel { - RASTER_CONFIG_RB_YSEL_0 = 0x00000000, - RASTER_CONFIG_RB_YSEL_1 = 0x00000001, -} RbYsel; - -typedef enum ReadSize { - READ_256_BITS = 0x00000000, - READ_512_BITS = 0x00000001, -} ReadSize; - -typedef enum RingCounterControl { - COUNTER_RING_SPLIT = 0x00000000, - COUNTER_RING_0 = 0x00000001, - COUNTER_RING_1 = 0x00000002, -} RingCounterControl; - -typedef enum RoundMode { - ROUND_BY_HALF = 0x00000000, - ROUND_TRUNCATE = 0x00000001, -} RoundMode; - -typedef enum RowSize { - ADDR_CONFIG_1KB_ROW = 0x00000000, - ADDR_CONFIG_2KB_ROW = 0x00000001, - ADDR_CONFIG_4KB_ROW = 0x00000002, -} RowSize; - -typedef enum RowTiling { - CONFIG_1KB_ROW = 0x00000000, - CONFIG_2KB_ROW = 0x00000001, - CONFIG_4KB_ROW = 0x00000002, - CONFIG_8KB_ROW = 0x00000003, - CONFIG_1KB_ROW_OPT = 0x00000004, - CONFIG_2KB_ROW_OPT = 0x00000005, - CONFIG_4KB_ROW_OPT = 0x00000006, - CONFIG_8KB_ROW_OPT = 0x00000007, -} RowTiling; - -typedef enum SC_PERFCNT_SEL { - SC_SRPS_WINDOW_VALID = 0x00000000, - SC_PSSW_WINDOW_VALID = 0x00000001, - SC_TPQZ_WINDOW_VALID = 0x00000002, - SC_QZQP_WINDOW_VALID = 0x00000003, - SC_TRPK_WINDOW_VALID = 0x00000004, - SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, - SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, - SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, - SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, - SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, - SC_STARVED_BY_PA = 0x0000000a, - SC_STALLED_BY_PRIMFIFO = 0x0000000b, - SC_STALLED_BY_DB_TILE = 0x0000000c, - SC_STARVED_BY_DB_TILE = 0x0000000d, - SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, - SC_STALLED_BY_TILEFIFO = 0x0000000f, - SC_STALLED_BY_DB_QUAD = 0x00000010, - SC_STARVED_BY_DB_QUAD = 0x00000011, - SC_STALLED_BY_QUADFIFO = 0x00000012, - SC_STALLED_BY_BCI = 0x00000013, - SC_STALLED_BY_SPI = 0x00000014, - SC_SCISSOR_DISCARD = 0x00000015, - SC_BB_DISCARD = 0x00000016, - SC_SUPERTILE_COUNT = 0x00000017, - SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, - SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, - SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, - SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, - SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, - SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, - SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, - SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, - SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, - SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, - SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, - SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, - SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, - SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, - SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, - SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, - SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, - SC_TILE_PER_PRIM_H0 = 0x00000029, - SC_TILE_PER_PRIM_H1 = 0x0000002a, - SC_TILE_PER_PRIM_H2 = 0x0000002b, - SC_TILE_PER_PRIM_H3 = 0x0000002c, - SC_TILE_PER_PRIM_H4 = 0x0000002d, - SC_TILE_PER_PRIM_H5 = 0x0000002e, - SC_TILE_PER_PRIM_H6 = 0x0000002f, - SC_TILE_PER_PRIM_H7 = 0x00000030, - SC_TILE_PER_PRIM_H8 = 0x00000031, - SC_TILE_PER_PRIM_H9 = 0x00000032, - SC_TILE_PER_PRIM_H10 = 0x00000033, - SC_TILE_PER_PRIM_H11 = 0x00000034, - SC_TILE_PER_PRIM_H12 = 0x00000035, - SC_TILE_PER_PRIM_H13 = 0x00000036, - SC_TILE_PER_PRIM_H14 = 0x00000037, - SC_TILE_PER_PRIM_H15 = 0x00000038, - SC_TILE_PER_PRIM_H16 = 0x00000039, - SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, - SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, - SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, - SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, - SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, - SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, - SC_TILE_PER_SUPERTILE_H6 = 0x00000040, - SC_TILE_PER_SUPERTILE_H7 = 0x00000041, - SC_TILE_PER_SUPERTILE_H8 = 0x00000042, - SC_TILE_PER_SUPERTILE_H9 = 0x00000043, - SC_TILE_PER_SUPERTILE_H10 = 0x00000044, - SC_TILE_PER_SUPERTILE_H11 = 0x00000045, - SC_TILE_PER_SUPERTILE_H12 = 0x00000046, - SC_TILE_PER_SUPERTILE_H13 = 0x00000047, - SC_TILE_PER_SUPERTILE_H14 = 0x00000048, - SC_TILE_PER_SUPERTILE_H15 = 0x00000049, - SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, - SC_TILE_PICKED_H1 = 0x0000004b, - SC_TILE_PICKED_H2 = 0x0000004c, - SC_TILE_PICKED_H3 = 0x0000004d, - SC_TILE_PICKED_H4 = 0x0000004e, - SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x0000004f, - SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x00000050, - SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x00000051, - SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x00000052, - SC_QZ0_TILE_COUNT = 0x00000053, - SC_QZ1_TILE_COUNT = 0x00000054, - SC_QZ2_TILE_COUNT = 0x00000055, - SC_QZ3_TILE_COUNT = 0x00000056, - SC_QZ0_TILE_COVERED_COUNT = 0x00000057, - SC_QZ1_TILE_COVERED_COUNT = 0x00000058, - SC_QZ2_TILE_COVERED_COUNT = 0x00000059, - SC_QZ3_TILE_COVERED_COUNT = 0x0000005a, - SC_QZ0_TILE_NOT_COVERED_COUNT = 0x0000005b, - SC_QZ1_TILE_NOT_COVERED_COUNT = 0x0000005c, - SC_QZ2_TILE_NOT_COVERED_COUNT = 0x0000005d, - SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005e, - SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005f, - SC_QZ0_QUAD_PER_TILE_H1 = 0x00000060, - SC_QZ0_QUAD_PER_TILE_H2 = 0x00000061, - SC_QZ0_QUAD_PER_TILE_H3 = 0x00000062, - SC_QZ0_QUAD_PER_TILE_H4 = 0x00000063, - SC_QZ0_QUAD_PER_TILE_H5 = 0x00000064, - SC_QZ0_QUAD_PER_TILE_H6 = 0x00000065, - SC_QZ0_QUAD_PER_TILE_H7 = 0x00000066, - SC_QZ0_QUAD_PER_TILE_H8 = 0x00000067, - SC_QZ0_QUAD_PER_TILE_H9 = 0x00000068, - SC_QZ0_QUAD_PER_TILE_H10 = 0x00000069, - SC_QZ0_QUAD_PER_TILE_H11 = 0x0000006a, - SC_QZ0_QUAD_PER_TILE_H12 = 0x0000006b, - SC_QZ0_QUAD_PER_TILE_H13 = 0x0000006c, - SC_QZ0_QUAD_PER_TILE_H14 = 0x0000006d, - SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006e, - SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006f, - SC_QZ1_QUAD_PER_TILE_H0 = 0x00000070, - SC_QZ1_QUAD_PER_TILE_H1 = 0x00000071, - SC_QZ1_QUAD_PER_TILE_H2 = 0x00000072, - SC_QZ1_QUAD_PER_TILE_H3 = 0x00000073, - SC_QZ1_QUAD_PER_TILE_H4 = 0x00000074, - SC_QZ1_QUAD_PER_TILE_H5 = 0x00000075, - SC_QZ1_QUAD_PER_TILE_H6 = 0x00000076, - SC_QZ1_QUAD_PER_TILE_H7 = 0x00000077, - SC_QZ1_QUAD_PER_TILE_H8 = 0x00000078, - SC_QZ1_QUAD_PER_TILE_H9 = 0x00000079, - SC_QZ1_QUAD_PER_TILE_H10 = 0x0000007a, - SC_QZ1_QUAD_PER_TILE_H11 = 0x0000007b, - SC_QZ1_QUAD_PER_TILE_H12 = 0x0000007c, - SC_QZ1_QUAD_PER_TILE_H13 = 0x0000007d, - SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007e, - SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007f, - SC_QZ1_QUAD_PER_TILE_H16 = 0x00000080, - SC_QZ2_QUAD_PER_TILE_H0 = 0x00000081, - SC_QZ2_QUAD_PER_TILE_H1 = 0x00000082, - SC_QZ2_QUAD_PER_TILE_H2 = 0x00000083, - SC_QZ2_QUAD_PER_TILE_H3 = 0x00000084, - SC_QZ2_QUAD_PER_TILE_H4 = 0x00000085, - SC_QZ2_QUAD_PER_TILE_H5 = 0x00000086, - SC_QZ2_QUAD_PER_TILE_H6 = 0x00000087, - SC_QZ2_QUAD_PER_TILE_H7 = 0x00000088, - SC_QZ2_QUAD_PER_TILE_H8 = 0x00000089, - SC_QZ2_QUAD_PER_TILE_H9 = 0x0000008a, - SC_QZ2_QUAD_PER_TILE_H10 = 0x0000008b, - SC_QZ2_QUAD_PER_TILE_H11 = 0x0000008c, - SC_QZ2_QUAD_PER_TILE_H12 = 0x0000008d, - SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008e, - SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008f, - SC_QZ2_QUAD_PER_TILE_H15 = 0x00000090, - SC_QZ2_QUAD_PER_TILE_H16 = 0x00000091, - SC_QZ3_QUAD_PER_TILE_H0 = 0x00000092, - SC_QZ3_QUAD_PER_TILE_H1 = 0x00000093, - SC_QZ3_QUAD_PER_TILE_H2 = 0x00000094, - SC_QZ3_QUAD_PER_TILE_H3 = 0x00000095, - SC_QZ3_QUAD_PER_TILE_H4 = 0x00000096, - SC_QZ3_QUAD_PER_TILE_H5 = 0x00000097, - SC_QZ3_QUAD_PER_TILE_H6 = 0x00000098, - SC_QZ3_QUAD_PER_TILE_H7 = 0x00000099, - SC_QZ3_QUAD_PER_TILE_H8 = 0x0000009a, - SC_QZ3_QUAD_PER_TILE_H9 = 0x0000009b, - SC_QZ3_QUAD_PER_TILE_H10 = 0x0000009c, - SC_QZ3_QUAD_PER_TILE_H11 = 0x0000009d, - SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009e, - SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009f, - SC_QZ3_QUAD_PER_TILE_H14 = 0x000000a0, - SC_QZ3_QUAD_PER_TILE_H15 = 0x000000a1, - SC_QZ3_QUAD_PER_TILE_H16 = 0x000000a2, - SC_QZ0_QUAD_COUNT = 0x000000a3, - SC_QZ1_QUAD_COUNT = 0x000000a4, - SC_QZ2_QUAD_COUNT = 0x000000a5, - SC_QZ3_QUAD_COUNT = 0x000000a6, - SC_P0_HIZ_TILE_COUNT = 0x000000a7, - SC_P1_HIZ_TILE_COUNT = 0x000000a8, - SC_P2_HIZ_TILE_COUNT = 0x000000a9, - SC_P3_HIZ_TILE_COUNT = 0x000000aa, - SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000ab, - SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000ac, - SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000ad, - SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000ae, - SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000af, - SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000b0, - SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000b1, - SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000b2, - SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000b3, - SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b4, - SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b5, - SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b6, - SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b7, - SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b8, - SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b9, - SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000ba, - SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000bb, - SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000bc, - SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000bd, - SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000be, - SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bf, - SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000c0, - SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000c1, - SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000c2, - SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000c3, - SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c4, - SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c5, - SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c6, - SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c7, - SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c8, - SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c9, - SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000ca, - SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000cb, - SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000cc, - SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000cd, - SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ce, - SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cf, - SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000d0, - SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000d1, - SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000d2, - SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000d3, - SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d4, - SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d5, - SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d6, - SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d7, - SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d8, - SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d9, - SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000da, - SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000db, - SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000dc, - SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000dd, - SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000de, - SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000df, - SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000e0, - SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000e1, - SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000e2, - SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000e3, - SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e4, - SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e5, - SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e6, - SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e7, - SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e8, - SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e9, - SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000ea, - SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000eb, - SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000ec, - SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000ed, - SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ee, - SC_P0_HIZ_QUAD_COUNT = 0x000000ef, - SC_P1_HIZ_QUAD_COUNT = 0x000000f0, - SC_P2_HIZ_QUAD_COUNT = 0x000000f1, - SC_P3_HIZ_QUAD_COUNT = 0x000000f2, - SC_P0_DETAIL_QUAD_COUNT = 0x000000f3, - SC_P1_DETAIL_QUAD_COUNT = 0x000000f4, - SC_P2_DETAIL_QUAD_COUNT = 0x000000f5, - SC_P3_DETAIL_QUAD_COUNT = 0x000000f6, - SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, - SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, - SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, - SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, - SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, - SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, - SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, - SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, - SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, - SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x00000100, - SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x00000101, - SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x00000102, - SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x00000103, - SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000104, - SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000105, - SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000106, - SC_EARLYZ_QUAD_COUNT = 0x00000107, - SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000108, - SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000109, - SC_EARLYZ_QUAD_WITH_3_PIX = 0x0000010a, - SC_EARLYZ_QUAD_WITH_4_PIX = 0x0000010b, - SC_PKR_QUAD_PER_ROW_H1 = 0x0000010c, - SC_PKR_QUAD_PER_ROW_H2 = 0x0000010d, - SC_PKR_QUAD_PER_ROW_H3__SI__CI = 0x0000010e, - SC_PKR_4X2_QUAD_SPLIT__VI = 0x0000010e, - SC_PKR_QUAD_PER_ROW_H4__SI__CI = 0x0000010f, - SC_PKR_4X2_FILL_QUAD__VI = 0x0000010f, - SC_PKR_END_OF_VECTOR = 0x00000110, - SC_PKR_CONTROL_XFER = 0x00000111, - SC_PKR_DBHANG_FORCE_EOV = 0x00000112, - SC_REG_SCLK_BUSY = 0x00000113, - SC_GRP0_DYN_SCLK_BUSY = 0x00000114, - SC_GRP1_DYN_SCLK_BUSY = 0x00000115, - SC_GRP2_DYN_SCLK_BUSY = 0x00000116, - SC_GRP3_DYN_SCLK_BUSY = 0x00000117, - SC_GRP4_DYN_SCLK_BUSY = 0x00000118, - SC_PA0_SC_DATA_FIFO_RD = 0x00000119, - SC_PA0_SC_DATA_FIFO_WE = 0x0000011a, - SC_PA1_SC_DATA_FIFO_RD = 0x0000011b, - SC_PA1_SC_DATA_FIFO_WE = 0x0000011c, - SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x0000011d, - SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011e, - SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011f, - SC_PS_ARB_STALLED_FROM_BELOW = 0x00000120, - SC_PS_ARB_STARVED_FROM_ABOVE = 0x00000121, - SC_PS_ARB_SC_BUSY = 0x00000122, - SC_PS_ARB_PA_SC_BUSY = 0x00000123, - SC_PA2_SC_DATA_FIFO_RD__CI__VI = 0x00000124, - SC_PA2_SC_DATA_FIFO_WE__CI__VI = 0x00000125, - SC_PA3_SC_DATA_FIFO_RD__CI__VI = 0x00000126, - SC_PA3_SC_DATA_FIFO_WE__CI__VI = 0x00000127, - SC_PA_SC_DEALLOC_0_0_WE__CI__VI = 0x00000128, - SC_PA_SC_DEALLOC_0_1_WE__CI__VI = 0x00000129, - SC_PA_SC_DEALLOC_1_0_WE__CI__VI = 0x0000012a, - SC_PA_SC_DEALLOC_1_1_WE__CI__VI = 0x0000012b, - SC_PA_SC_DEALLOC_2_0_WE__CI__VI = 0x0000012c, - SC_PA_SC_DEALLOC_2_1_WE__CI__VI = 0x0000012d, - SC_PA_SC_DEALLOC_3_0_WE__CI__VI = 0x0000012e, - SC_PA_SC_DEALLOC_3_1_WE__CI__VI = 0x0000012f, - SC_PA0_SC_EOP_WE__CI__VI = 0x00000130, - SC_PA0_SC_EOPG_WE__CI__VI = 0x00000131, - SC_PA0_SC_EVENT_WE__CI__VI = 0x00000132, - SC_PA1_SC_EOP_WE__CI__VI = 0x00000133, - SC_PA1_SC_EOPG_WE__CI__VI = 0x00000134, - SC_PA1_SC_EVENT_WE__CI__VI = 0x00000135, - SC_PA2_SC_EOP_WE__CI__VI = 0x00000136, - SC_PA2_SC_EOPG_WE__CI__VI = 0x00000137, - SC_PA2_SC_EVENT_WE__CI__VI = 0x00000138, - SC_PA3_SC_EOP_WE__CI__VI = 0x00000139, - SC_PA3_SC_EOPG_WE__CI__VI = 0x0000013a, - SC_PA3_SC_EVENT_WE__CI__VI = 0x0000013b, - SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO__CI__VI = 0x0000013c, - SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH__CI__VI = 0x0000013d, - SC_PS_ARB_NULL_PRIM_BUBBLE_POP__CI__VI = 0x0000013e, - SC_PS_ARB_EOP_POP_SYNC_POP__CI__VI = 0x0000013f, - SC_PS_ARB_EVENT_SYNC_POP__CI__VI = 0x00000140, - SC_SC_PS_ENG_MULTICYCLE_BUBBLE__CI__VI = 0x00000141, - SC_PA0_SC_FPOV_WE__CI__VI = 0x00000142, - SC_PA1_SC_FPOV_WE__CI__VI = 0x00000143, - SC_PA2_SC_FPOV_WE__CI__VI = 0x00000144, - SC_PA3_SC_FPOV_WE__CI__VI = 0x00000145, - SC_PA0_SC_LPOV_WE__CI__VI = 0x00000146, - SC_PA1_SC_LPOV_WE__CI__VI = 0x00000147, - SC_PA2_SC_LPOV_WE__CI__VI = 0x00000148, - SC_PA3_SC_LPOV_WE__CI__VI = 0x00000149, - SC_SC_SPI_DEALLOC_0_0__CI__VI = 0x0000014a, - SC_SC_SPI_DEALLOC_0_1__CI__VI = 0x0000014b, - SC_SC_SPI_DEALLOC_0_2__CI__VI = 0x0000014c, - SC_SC_SPI_DEALLOC_1_0__CI__VI = 0x0000014d, - SC_SC_SPI_DEALLOC_1_1__CI__VI = 0x0000014e, - SC_SC_SPI_DEALLOC_1_2__CI__VI = 0x0000014f, - SC_SC_SPI_DEALLOC_2_0__CI__VI = 0x00000150, - SC_SC_SPI_DEALLOC_2_1__CI__VI = 0x00000151, - SC_SC_SPI_DEALLOC_2_2__CI__VI = 0x00000152, - SC_SC_SPI_DEALLOC_3_0__CI__VI = 0x00000153, - SC_SC_SPI_DEALLOC_3_1__CI__VI = 0x00000154, - SC_SC_SPI_DEALLOC_3_2__CI__VI = 0x00000155, - SC_SC_SPI_FPOV_0__CI__VI = 0x00000156, - SC_SC_SPI_FPOV_1__CI__VI = 0x00000157, - SC_SC_SPI_FPOV_2__CI__VI = 0x00000158, - SC_SC_SPI_FPOV_3__CI__VI = 0x00000159, - SC_SC_SPI_EVENT__CI__VI = 0x0000015a, - SC_PS_TS_EVENT_FIFO_PUSH__CI__VI = 0x0000015b, - SC_PS_TS_EVENT_FIFO_POP__CI__VI = 0x0000015c, - SC_PS_CTX_DONE_FIFO_PUSH__CI__VI = 0x0000015d, - SC_PS_CTX_DONE_FIFO_POP__CI__VI = 0x0000015e, - SC_MULTICYCLE_BUBBLE_FREEZE__CI__VI = 0x0000015f, - SC_EOP_SYNC_WINDOW__CI__VI = 0x00000160, - SC_PA0_SC_NULL_WE__CI__VI = 0x00000161, - SC_PA0_SC_NULL_DEALLOC_WE__CI__VI = 0x00000162, - SC_PA0_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x00000163, - SC_PA0_SC_DATA_FIFO_EOP_RD__CI__VI = 0x00000164, - SC_PA0_SC_DEALLOC_0_RD__CI__VI = 0x00000165, - SC_PA0_SC_DEALLOC_1_RD__CI__VI = 0x00000166, - SC_PA1_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x00000167, - SC_PA1_SC_DATA_FIFO_EOP_RD__CI__VI = 0x00000168, - SC_PA1_SC_DEALLOC_0_RD__CI__VI = 0x00000169, - SC_PA1_SC_DEALLOC_1_RD__CI__VI = 0x0000016a, - SC_PA1_SC_NULL_WE__CI__VI = 0x0000016b, - SC_PA1_SC_NULL_DEALLOC_WE__CI__VI = 0x0000016c, - SC_PA2_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x0000016d, - SC_PA2_SC_DATA_FIFO_EOP_RD__CI__VI = 0x0000016e, - SC_PA2_SC_DEALLOC_0_RD__CI__VI = 0x0000016f, - SC_PA2_SC_DEALLOC_1_RD__CI__VI = 0x00000170, - SC_PA2_SC_NULL_WE__CI__VI = 0x00000171, - SC_PA2_SC_NULL_DEALLOC_WE__CI__VI = 0x00000172, - SC_PA3_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x00000173, - SC_PA3_SC_DATA_FIFO_EOP_RD__CI__VI = 0x00000174, - SC_PA3_SC_DEALLOC_0_RD__CI__VI = 0x00000175, - SC_PA3_SC_DEALLOC_1_RD__CI__VI = 0x00000176, - SC_PA3_SC_NULL_WE__CI__VI = 0x00000177, - SC_PA3_SC_NULL_DEALLOC_WE__CI__VI = 0x00000178, - SC_PS_PA0_SC_FIFO_EMPTY__CI__VI = 0x00000179, - SC_PS_PA0_SC_FIFO_FULL__CI__VI = 0x0000017a, - SC_PA0_PS_DATA_SEND__CI__VI = 0x0000017b, - SC_PS_PA1_SC_FIFO_EMPTY__CI__VI = 0x0000017c, - SC_PS_PA1_SC_FIFO_FULL__CI__VI = 0x0000017d, - SC_PA1_PS_DATA_SEND__CI__VI = 0x0000017e, - SC_PS_PA2_SC_FIFO_EMPTY__CI__VI = 0x0000017f, - SC_PS_PA2_SC_FIFO_FULL__CI__VI = 0x00000180, - SC_PA2_PS_DATA_SEND__CI__VI = 0x00000181, - SC_PS_PA3_SC_FIFO_EMPTY__CI__VI = 0x00000182, - SC_PS_PA3_SC_FIFO_FULL__CI__VI = 0x00000183, - SC_PA3_PS_DATA_SEND__CI__VI = 0x00000184, - SC_BUSY_PROCESSING_MULTICYCLE_PRIM__CI__VI = 0x00000185, - SC_BUSY_CNT_NOT_ZERO__CI__VI = 0x00000186, - SC_BM_BUSY__CI__VI = 0x00000187, - SC_BACKEND_BUSY__CI__VI = 0x00000188, - SC_SCF_SCB_INTERFACE_BUSY__CI__VI = 0x00000189, - SC_SCB_BUSY__CI__VI = 0x0000018a, - SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY__VI = 0x0000018b, - SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL__VI = 0x0000018c, -} SC_PERFCNT_SEL; - -typedef enum SDMA_PERF_SEL { - SDMA_PERF_SEL_CYCLE = 0x00000000, - SDMA_PERF_SEL_IDLE = 0x00000001, - SDMA_PERF_SEL_REG_IDLE = 0x00000002, - SDMA_PERF_SEL_RB_EMPTY = 0x00000003, - SDMA_PERF_SEL_RB_FULL = 0x00000004, - SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, - SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, - SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, - SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, - SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, - SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, - SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, - SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, - SDMA_PERF_SEL_EX_IDLE = 0x0000000d, - SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, - SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, - SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, - SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, - SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, - SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, - SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, - SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, - SDMA_PERF_SEL_DRM_IDLE = 0x00000016, - SDMA_PERF_SEL_DRM_REQ_STALL = 0x00000017, - SDMA_PERF_SEL_SEM_IDLE = 0x00000018, - SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, - SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, - SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, - SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, - SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, - SDMA_PERF_SEL_INT_IDLE = 0x0000001e, - SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, - SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, - SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, - SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, - SDMA_PERF_SEL_NUM_PACKET = 0x00000023, - SDMA_PERF_SEL_DRM1_REQ_STALL = 0x00000024, - SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, - SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, - SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, - SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, - SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, - SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, - SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, - SDMA_PERF_SEL_CE_DRM_IDLE = 0x0000002c, - SDMA_PERF_SEL_CE_DRM1_IDLE = 0x0000002d, - SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, - SDMA_PERF_SEL_CE_DRM_FULL = 0x0000002f, - SDMA_PERF_SEL_CE_DRM1_FULL = 0x00000030, - SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, - SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, - SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, - SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, - SDMA_PERF_SEL_GFX_SELECT__VI = 0x00000035, - SDMA_PERF_SEL_RLC0_SELECT__VI = 0x00000036, - SDMA_PERF_SEL_RLC1_SELECT__VI = 0x00000037, - SDMA_PERF_SEL_CTX_CHANGE__VI = 0x00000038, - SDMA_PERF_SEL_CTX_CHANGE_EXPIRED__VI = 0x00000039, - SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION__VI = 0x0000003a, - SDMA_PERF_SEL_DOORBELL__VI = 0x0000003b, - SDMA_PERF_SEL_RD_BA_RTR__VI = 0x0000003c, - SDMA_PERF_SEL_WR_BA_RTR__VI = 0x0000003d, -} SDMA_PERF_SEL; - -typedef enum SH_MEM_ALIGNMENT_MODE { - SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, - SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, - SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, - SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, -} SH_MEM_ALIGNMENT_MODE; - -typedef enum SPI_FOG_MODE { - SPI_FOG_NONE = 0x00000000, - SPI_FOG_EXP = 0x00000001, - SPI_FOG_EXP2 = 0x00000002, - SPI_FOG_LINEAR = 0x00000003, -} SPI_FOG_MODE; - -typedef enum SPI_PERFCNT_SEL { - SPI_PERF_VS_WINDOW_VALID = 0x00000000, - SPI_PERF_VS_BUSY = 0x00000001, - SPI_PERF_VS_FIRST_WAVE = 0x00000002, - SPI_PERF_VS_LAST_WAVE = 0x00000003, - SPI_PERF_VS_LSHS_DEALLOC = 0x00000004, - SPI_PERF_VS_PC_STALL = 0x00000005, - SPI_PERF_VS_POS0_STALL = 0x00000006, - SPI_PERF_VS_POS1_STALL = 0x00000007, - SPI_PERF_VS_CRAWLER_STALL = 0x00000008, - SPI_PERF_VS_EVENT_WAVE = 0x00000009, - SPI_PERF_VS_WAVE = 0x0000000a, - SPI_PERF_VS_PERS_UPD_FULL__SI = 0x0000000b, - SPI_PERF_VS_PERS_UPD_FULL0__CI__VI = 0x0000000b, - SPI_PERF_GS_WINDOW_VALID__SI = 0x0000000c, - SPI_PERF_VS_PERS_UPD_FULL1__CI__VI = 0x0000000c, - SPI_PERF_GS_BUSY__SI = 0x0000000d, - SPI_PERF_VS_LATE_ALLOC_FULL__CI__VI = 0x0000000d, - SPI_PERF_GS_CRAWLER_STALL__SI = 0x0000000e, - SPI_PERF_VS_FIRST_SUBGRP__CI__VI = 0x0000000e, - SPI_PERF_GS_EVENT_WAVE__SI = 0x0000000f, - SPI_PERF_VS_LAST_SUBGRP__CI__VI = 0x0000000f, - SPI_PERF_GS_WAVE__SI = 0x00000010, - SPI_PERF_GS_WINDOW_VALID__CI__VI = 0x00000010, - SPI_PERF_GS_PERS_UPD_FULL__SI = 0x00000011, - SPI_PERF_GS_BUSY__CI__VI = 0x00000011, - SPI_PERF_ES_WINDOW_VALID__SI = 0x00000012, - SPI_PERF_GS_CRAWLER_STALL__CI__VI = 0x00000012, - SPI_PERF_ES_BUSY__SI = 0x00000013, - SPI_PERF_GS_EVENT_WAVE__CI__VI = 0x00000013, - SPI_PERF_ES_CRAWLER_STALL__SI = 0x00000014, - SPI_PERF_GS_WAVE__CI__VI = 0x00000014, - SPI_PERF_ES_FIRST_WAVE__SI = 0x00000015, - SPI_PERF_GS_PERS_UPD_FULL0__CI__VI = 0x00000015, - SPI_PERF_ES_LAST_WAVE__SI = 0x00000016, - SPI_PERF_GS_PERS_UPD_FULL1__CI__VI = 0x00000016, - SPI_PERF_ES_LSHS_DEALLOC__SI = 0x00000017, - SPI_PERF_GS_FIRST_SUBGRP__CI__VI = 0x00000017, - SPI_PERF_ES_EVENT_WAVE__SI = 0x00000018, - SPI_PERF_GS_LAST_SUBGRP__CI__VI = 0x00000018, - SPI_PERF_ES_WAVE__SI = 0x00000019, - SPI_PERF_ES_WINDOW_VALID__CI__VI = 0x00000019, - SPI_PERF_ES_PERS_UPD_FULL__SI = 0x0000001a, - SPI_PERF_ES_BUSY__CI__VI = 0x0000001a, - SPI_PERF_HS_WINDOW_VALID__SI = 0x0000001b, - SPI_PERF_ES_CRAWLER_STALL__CI__VI = 0x0000001b, - SPI_PERF_HS_BUSY__SI = 0x0000001c, - SPI_PERF_ES_FIRST_WAVE__CI__VI = 0x0000001c, - SPI_PERF_HS_CRAWLER_STALL__SI = 0x0000001d, - SPI_PERF_ES_LAST_WAVE__CI__VI = 0x0000001d, - SPI_PERF_HS_FIRST_WAVE__SI = 0x0000001e, - SPI_PERF_ES_LSHS_DEALLOC__CI__VI = 0x0000001e, - SPI_PERF_HS_LAST_WAVE__SI = 0x0000001f, - SPI_PERF_ES_EVENT_WAVE__CI__VI = 0x0000001f, - SPI_PERF_HS_LSHS_DEALLOC__SI = 0x00000020, - SPI_PERF_ES_WAVE__CI__VI = 0x00000020, - SPI_PERF_HS_EVENT_WAVE__SI = 0x00000021, - SPI_PERF_ES_PERS_UPD_FULL0__CI__VI = 0x00000021, - SPI_PERF_HS_WAVE__SI = 0x00000022, - SPI_PERF_ES_PERS_UPD_FULL1__CI__VI = 0x00000022, - SPI_PERF_HS_PERS_UPD_FULL__SI = 0x00000023, - SPI_PERF_ES_FIRST_SUBGRP__CI__VI = 0x00000023, - SPI_PERF_LS_WINDOW_VALID__SI = 0x00000024, - SPI_PERF_ES_LAST_SUBGRP__CI__VI = 0x00000024, - SPI_PERF_LS_BUSY__SI = 0x00000025, - SPI_PERF_HS_WINDOW_VALID__CI__VI = 0x00000025, - SPI_PERF_LS_CRAWLER_STALL__SI = 0x00000026, - SPI_PERF_HS_BUSY__CI__VI = 0x00000026, - SPI_PERF_LS_FIRST_WAVE__SI = 0x00000027, - SPI_PERF_HS_CRAWLER_STALL__CI__VI = 0x00000027, - SPI_PERF_LS_LAST_WAVE__SI = 0x00000028, - SPI_PERF_HS_FIRST_WAVE__CI__VI = 0x00000028, - SPI_PERF_OFFCHIP_LDS_STALL_LS__SI = 0x00000029, - SPI_PERF_HS_LAST_WAVE__CI__VI = 0x00000029, - SPI_PERF_LS_EVENT_WAVE__SI = 0x0000002a, - SPI_PERF_HS_LSHS_DEALLOC__CI__VI = 0x0000002a, - SPI_PERF_LS_WAVE__SI = 0x0000002b, - SPI_PERF_HS_EVENT_WAVE__CI__VI = 0x0000002b, - SPI_PERF_LS_PERS_UPD_FULL__SI = 0x0000002c, - SPI_PERF_HS_WAVE__CI__VI = 0x0000002c, - SPI_PERF_CS_R0_WINDOW_VALID__SI = 0x0000002d, - SPI_PERF_HS_PERS_UPD_FULL0__CI__VI = 0x0000002d, - SPI_PERF_CS_R0_BUSY__SI = 0x0000002e, - SPI_PERF_HS_PERS_UPD_FULL1__CI__VI = 0x0000002e, - SPI_PERF_CS_R0_INPUT_STARVED__SI = 0x0000002f, - SPI_PERF_LS_WINDOW_VALID__CI__VI = 0x0000002f, - SPI_PERF_CS_R0_NUM_THREADGROUPS__SI = 0x00000030, - SPI_PERF_LS_BUSY__CI__VI = 0x00000030, - SPI_PERF_CS_R0_CRAWLER_STALL__SI = 0x00000031, - SPI_PERF_LS_CRAWLER_STALL__CI__VI = 0x00000031, - SPI_PERF_CS_R0_EVENT_WAVE__SI = 0x00000032, - SPI_PERF_LS_FIRST_WAVE__CI__VI = 0x00000032, - SPI_PERF_CS_R0_WAVE__SI = 0x00000033, - SPI_PERF_LS_LAST_WAVE__CI__VI = 0x00000033, - SPI_PERF_CS_R1_WINDOW_VALID__SI = 0x00000034, - SPI_PERF_OFFCHIP_LDS_STALL_LS__CI__VI = 0x00000034, - SPI_PERF_CS_R1_BUSY__SI = 0x00000035, - SPI_PERF_LS_EVENT_WAVE__CI__VI = 0x00000035, - SPI_PERF_CS_R1_INPUT_STARVED__SI = 0x00000036, - SPI_PERF_LS_WAVE__CI__VI = 0x00000036, - SPI_PERF_CS_R1_NUM_THREADGROUPS__SI = 0x00000037, - SPI_PERF_LS_PERS_UPD_FULL0__CI__VI = 0x00000037, - SPI_PERF_CS_R1_CRAWLER_STALL__SI = 0x00000038, - SPI_PERF_LS_PERS_UPD_FULL1__CI__VI = 0x00000038, - SPI_PERF_CS_R1_EVENT_WAVE__SI = 0x00000039, - SPI_PERF_CSG_WINDOW_VALID__CI__VI = 0x00000039, - SPI_PERF_CS_R1_WAVE__SI = 0x0000003a, - SPI_PERF_CSG_BUSY__CI__VI = 0x0000003a, - SPI_PERF_CS_R2_WINDOW_VALID__SI = 0x0000003b, - SPI_PERF_CSG_NUM_THREADGROUPS__CI__VI = 0x0000003b, - SPI_PERF_CS_R2_BUSY__SI = 0x0000003c, - SPI_PERF_CSG_CRAWLER_STALL__CI__VI = 0x0000003c, - SPI_PERF_CS_R2_INPUT_STARVED__SI = 0x0000003d, - SPI_PERF_CSG_EVENT_WAVE__CI__VI = 0x0000003d, - SPI_PERF_CS_R2_NUM_THREADGROUPS__SI = 0x0000003e, - SPI_PERF_CSG_WAVE__CI__VI = 0x0000003e, - SPI_PERF_CS_R2_CRAWLER_STALL__SI = 0x0000003f, - SPI_PERF_CSN_WINDOW_VALID__CI__VI = 0x0000003f, - SPI_PERF_CS_R2_EVENT_WAVE__SI = 0x00000040, - SPI_PERF_CSN_BUSY__CI__VI = 0x00000040, - SPI_PERF_CS_R2_WAVE__SI = 0x00000041, - SPI_PERF_CSN_NUM_THREADGROUPS__CI__VI = 0x00000041, - SPI_PERF_PS_CTL_WINDOW_VALID__SI = 0x00000042, - SPI_PERF_CSN_CRAWLER_STALL__CI__VI = 0x00000042, - SPI_PERF_PS_CTL_BUSY__SI = 0x00000043, - SPI_PERF_CSN_EVENT_WAVE__CI__VI = 0x00000043, - SPI_PERF_PS_CTL_ACTIVE__SI = 0x00000044, - SPI_PERF_CSN_WAVE__CI__VI = 0x00000044, - SPI_PERF_PS_CTL_DEALLOC0__SI = 0x00000045, - SPI_PERF_PS_CTL_WINDOW_VALID__CI__VI = 0x00000045, - SPI_PERF_PS_CTL_DEALLOC1__SI = 0x00000046, - SPI_PERF_PS_CTL_BUSY__CI__VI = 0x00000046, - SPI_PERF_PS_CTL_FPOS0_STALL__SI = 0x00000047, - SPI_PERF_PS_CTL_ACTIVE__CI__VI = 0x00000047, - SPI_PERF_PS_CTL_FPOS1_STALL__SI = 0x00000048, - SPI_PERF_PS_CTL_DEALLOC_BIN0__CI__VI = 0x00000048, - SPI_PERF_PS_CTL_EVENT_WAVE__SI = 0x00000049, - SPI_PERF_PS_CTL_FPOS_BIN1_STALL__CI__VI = 0x00000049, - SPI_PERF_PS_CTL_WAVE__SI = 0x0000004a, - SPI_PERF_PS_CTL_EVENT_WAVE__CI__VI = 0x0000004a, - SPI_PERF_PS_CTL_OPT_WAVE__SI = 0x0000004b, - SPI_PERF_PS_CTL_WAVE__CI__VI = 0x0000004b, - SPI_PERF_PS_CTL_PASS_BIN0__SI = 0x0000004c, - SPI_PERF_PS_CTL_OPT_WAVE__CI__VI = 0x0000004c, - SPI_PERF_PS_CTL_PASS_BIN1__SI = 0x0000004d, - SPI_PERF_PS_CTL_PASS_BIN0__CI__VI = 0x0000004d, - SPI_PERF_PS_CTL_FPOS0__SI = 0x0000004e, - SPI_PERF_PS_CTL_PASS_BIN1__CI__VI = 0x0000004e, - SPI_PERF_PS_CTL_FPOS1__SI = 0x0000004f, - SPI_PERF_PS_CTL_FPOS_BIN2__CI__VI = 0x0000004f, - SPI_PERF_PS_CTL_PRIM_BIN0 = 0x00000050, - SPI_PERF_PS_CTL_PRIM_BIN1 = 0x00000051, - SPI_PERF_PS_CTL_CNF_BIN2 = 0x00000052, - SPI_PERF_PS_CTL_CNF_BIN3 = 0x00000053, - SPI_PERF_PS_CTL_CRAWLER_STALL = 0x00000054, - SPI_PERF_PS_CTL_LDS_RES_FULL = 0x00000055, - SPI_PERF_PS_PERS_UPD_FULL__SI = 0x00000056, - SPI_PERF_PS_PERS_UPD_FULL0__CI__VI = 0x00000056, - SPI_PERF_PIX_ALLOC_PEND_CNT__SI = 0x00000057, - SPI_PERF_PS_PERS_UPD_FULL1__CI__VI = 0x00000057, - SPI_PERF_PIX_ALLOC_SCB_STALL__SI = 0x00000058, - SPI_PERF_PIX_ALLOC_PEND_CNT__CI__VI = 0x00000058, - SPI_PERF_PIX_ALLOC_DB0_STALL__SI = 0x00000059, - SPI_PERF_PIX_ALLOC_SCB_STALL__CI__VI = 0x00000059, - SPI_PERF_PIX_ALLOC_DB1_STALL__SI = 0x0000005a, - SPI_PERF_PIX_ALLOC_DB0_STALL__CI__VI = 0x0000005a, - SPI_PERF_LDS_PC_VALID__SI = 0x0000005b, - SPI_PERF_PIX_ALLOC_DB1_STALL__CI__VI = 0x0000005b, - SPI_PERF_RESERVED__SI = 0x0000005c, - SPI_PERF_PIX_ALLOC_DB2_STALL__CI__VI = 0x0000005c, - SPI_PERF_RA_RING_REQ_BIN2__SI = 0x0000005d, - SPI_PERF_PIX_ALLOC_DB3_STALL__CI__VI = 0x0000005d, - SPI_PERF_RA_TASK_REQ_BIN3__SI = 0x0000005e, - SPI_PERF_LDS0_PC_VALID__CI__VI = 0x0000005e, - SPI_PERF_RA_WR_CTL_FULL__SI = 0x0000005f, - SPI_PERF_LDS1_PC_VALID__CI__VI = 0x0000005f, - SPI_PERF_RA_REQ_NO_ALLOC__SI = 0x00000060, - SPI_PERF_RA_PIPE_REQ_BIN2__CI__VI = 0x00000060, - SPI_PERF_RA_REQ_NO_ALLOC_PS__SI = 0x00000061, - SPI_PERF_RA_TASK_REQ_BIN3__CI__VI = 0x00000061, - SPI_PERF_RA_REQ_NO_ALLOC_VS__SI = 0x00000062, - SPI_PERF_RA_WR_CTL_FULL__CI__VI = 0x00000062, - SPI_PERF_RA_REQ_NO_ALLOC_GS__SI = 0x00000063, - SPI_PERF_RA_REQ_NO_ALLOC__CI__VI = 0x00000063, - SPI_PERF_RA_REQ_NO_ALLOC_ES__SI = 0x00000064, - SPI_PERF_RA_REQ_NO_ALLOC_PS__CI__VI = 0x00000064, - SPI_PERF_RA_REQ_NO_ALLOC_HS__SI = 0x00000065, - SPI_PERF_RA_REQ_NO_ALLOC_VS__CI__VI = 0x00000065, - SPI_PERF_RA_REQ_NO_ALLOC_LS__SI = 0x00000066, - SPI_PERF_RA_REQ_NO_ALLOC_GS__CI__VI = 0x00000066, - SPI_PERF_RA_REQ_NO_ALLOC_CS_R0__SI = 0x00000067, - SPI_PERF_RA_REQ_NO_ALLOC_ES__CI__VI = 0x00000067, - SPI_PERF_RA_REQ_NO_ALLOC_CS_R1__SI = 0x00000068, - SPI_PERF_RA_REQ_NO_ALLOC_HS__CI__VI = 0x00000068, - SPI_PERF_RA_REQ_NO_ALLOC_CS_R2__SI = 0x00000069, - SPI_PERF_RA_REQ_NO_ALLOC_LS__CI__VI = 0x00000069, - SPI_PERF_RA_RES_STALL_PS__SI = 0x0000006a, - SPI_PERF_RA_REQ_NO_ALLOC_CSG__CI__VI = 0x0000006a, - SPI_PERF_RA_RES_STALL_VS__SI = 0x0000006b, - SPI_PERF_RA_REQ_NO_ALLOC_CSN__CI__VI = 0x0000006b, - SPI_PERF_RA_RES_STALL_GS__SI = 0x0000006c, - SPI_PERF_RA_RES_STALL_PS__CI__VI = 0x0000006c, - SPI_PERF_RA_RES_STALL_ES__SI = 0x0000006d, - SPI_PERF_RA_RES_STALL_VS__CI__VI = 0x0000006d, - SPI_PERF_RA_RES_STALL_HS__SI = 0x0000006e, - SPI_PERF_RA_RES_STALL_GS__CI__VI = 0x0000006e, - SPI_PERF_RA_RES_STALL_LS__SI = 0x0000006f, - SPI_PERF_RA_RES_STALL_ES__CI__VI = 0x0000006f, - SPI_PERF_RA_RES_STALL_CS_R0__SI = 0x00000070, - SPI_PERF_RA_RES_STALL_HS__CI__VI = 0x00000070, - SPI_PERF_RA_RES_STALL_CS_R1__SI = 0x00000071, - SPI_PERF_RA_RES_STALL_LS__CI__VI = 0x00000071, - SPI_PERF_RA_RES_STALL_CS_R2__SI = 0x00000072, - SPI_PERF_RA_RES_STALL_CSG__CI__VI = 0x00000072, - SPI_PERF_RA_TMP_STALL_PS__SI = 0x00000073, - SPI_PERF_RA_RES_STALL_CSN__CI__VI = 0x00000073, - SPI_PERF_RA_TMP_STALL_VS__SI = 0x00000074, - SPI_PERF_RA_TMP_STALL_PS__CI__VI = 0x00000074, - SPI_PERF_RA_TMP_STALL_GS__SI = 0x00000075, - SPI_PERF_RA_TMP_STALL_VS__CI__VI = 0x00000075, - SPI_PERF_RA_TMP_STALL_ES__SI = 0x00000076, - SPI_PERF_RA_TMP_STALL_GS__CI__VI = 0x00000076, - SPI_PERF_RA_TMP_STALL_HS__SI = 0x00000077, - SPI_PERF_RA_TMP_STALL_ES__CI__VI = 0x00000077, - SPI_PERF_RA_TMP_STALL_LS__SI = 0x00000078, - SPI_PERF_RA_TMP_STALL_HS__CI__VI = 0x00000078, - SPI_PERF_RA_TMP_STALL_CS_R0__SI = 0x00000079, - SPI_PERF_RA_TMP_STALL_LS__CI__VI = 0x00000079, - SPI_PERF_RA_TMP_STALL_CS_R1__SI = 0x0000007a, - SPI_PERF_RA_TMP_STALL_CSG__CI__VI = 0x0000007a, - SPI_PERF_RA_TMP_STALL_CS_R2__SI = 0x0000007b, - SPI_PERF_RA_TMP_STALL_CSN__CI__VI = 0x0000007b, - SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000007c, - SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000007d, - SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000007e, - SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x0000007f, - SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000080, - SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x00000081, - SPI_PERF_RA_WAVE_SIMD_FULL_CS_R0__SI = 0x00000082, - SPI_PERF_RA_WAVE_SIMD_FULL_CSG__CI__VI = 0x00000082, - SPI_PERF_RA_WAVE_SIMD_FULL_CS_R1__SI = 0x00000083, - SPI_PERF_RA_WAVE_SIMD_FULL_CSN__CI__VI = 0x00000083, - SPI_PERF_RA_WAVE_SIMD_FULL_CS_R2__SI = 0x00000084, - SPI_PERF_RA_VGPR_SIMD_FULL_PS__CI__VI = 0x00000084, - SPI_PERF_RA_VGPR_SIMD_FULL_PS__SI = 0x00000085, - SPI_PERF_RA_VGPR_SIMD_FULL_VS__CI__VI = 0x00000085, - SPI_PERF_RA_VGPR_SIMD_FULL_VS__SI = 0x00000086, - SPI_PERF_RA_VGPR_SIMD_FULL_GS__CI__VI = 0x00000086, - SPI_PERF_RA_VGPR_SIMD_FULL_GS__SI = 0x00000087, - SPI_PERF_RA_VGPR_SIMD_FULL_ES__CI__VI = 0x00000087, - SPI_PERF_RA_VGPR_SIMD_FULL_ES__SI = 0x00000088, - SPI_PERF_RA_VGPR_SIMD_FULL_HS__CI__VI = 0x00000088, - SPI_PERF_RA_VGPR_SIMD_FULL_HS__SI = 0x00000089, - SPI_PERF_RA_VGPR_SIMD_FULL_LS__CI__VI = 0x00000089, - SPI_PERF_RA_VGPR_SIMD_FULL_LS__SI = 0x0000008a, - SPI_PERF_RA_VGPR_SIMD_FULL_CSG__CI__VI = 0x0000008a, - SPI_PERF_RA_VGPR_SIMD_FULL_CS_R0__SI = 0x0000008b, - SPI_PERF_RA_VGPR_SIMD_FULL_CSN__CI__VI = 0x0000008b, - SPI_PERF_RA_VGPR_SIMD_FULL_CS_R1__SI = 0x0000008c, - SPI_PERF_RA_SGPR_SIMD_FULL_PS__CI__VI = 0x0000008c, - SPI_PERF_RA_VGPR_SIMD_FULL_CS_R2__SI = 0x0000008d, - SPI_PERF_RA_SGPR_SIMD_FULL_VS__CI__VI = 0x0000008d, - SPI_PERF_RA_SGPR_SIMD_FULL_PS__SI = 0x0000008e, - SPI_PERF_RA_SGPR_SIMD_FULL_GS__CI__VI = 0x0000008e, - SPI_PERF_RA_SGPR_SIMD_FULL_VS__SI = 0x0000008f, - SPI_PERF_RA_SGPR_SIMD_FULL_ES__CI__VI = 0x0000008f, - SPI_PERF_RA_SGPR_SIMD_FULL_GS__SI = 0x00000090, - SPI_PERF_RA_SGPR_SIMD_FULL_HS__CI__VI = 0x00000090, - SPI_PERF_RA_SGPR_SIMD_FULL_ES__SI = 0x00000091, - SPI_PERF_RA_SGPR_SIMD_FULL_LS__CI__VI = 0x00000091, - SPI_PERF_RA_SGPR_SIMD_FULL_HS__SI = 0x00000092, - SPI_PERF_RA_SGPR_SIMD_FULL_CSG__CI__VI = 0x00000092, - SPI_PERF_RA_SGPR_SIMD_FULL_LS__SI = 0x00000093, - SPI_PERF_RA_SGPR_SIMD_FULL_CSN__CI__VI = 0x00000093, - SPI_PERF_RA_SGPR_SIMD_FULL_CS_R0__SI = 0x00000094, - SPI_PERF_RA_LDS_CU_FULL_PS__CI__VI = 0x00000094, - SPI_PERF_RA_SGPR_SIMD_FULL_CS_R1__SI = 0x00000095, - SPI_PERF_RA_LDS_CU_FULL_LS__CI__VI = 0x00000095, - SPI_PERF_RA_SGPR_SIMD_FULL_CS_R2__SI = 0x00000096, - SPI_PERF_RA_LDS_CU_FULL_ES__CI__VI = 0x00000096, - SPI_PERF_RA_LDS_CU_FULL_PS__SI = 0x00000097, - SPI_PERF_RA_LDS_CU_FULL_CSG__CI__VI = 0x00000097, - SPI_PERF_RA_LDS_CU_FULL_LS__SI = 0x00000098, - SPI_PERF_RA_LDS_CU_FULL_CSN__CI__VI = 0x00000098, - SPI_PERF_RA_LDS_CU_FULL_CS_R0__SI = 0x00000099, - SPI_PERF_RA_BAR_CU_FULL_HS__CI__VI = 0x00000099, - SPI_PERF_RA_LDS_CU_FULL_CS_R1__SI = 0x0000009a, - SPI_PERF_RA_BAR_CU_FULL_CSG__CI__VI = 0x0000009a, - SPI_PERF_RA_LDS_CU_FULL_CS_R2__SI = 0x0000009b, - SPI_PERF_RA_BAR_CU_FULL_CSN__CI__VI = 0x0000009b, - SPI_PERF_RA_BAR_CU_FULL_HS__SI = 0x0000009c, - SPI_PERF_RA_BULKY_CU_FULL_CSG__CI__VI = 0x0000009c, - SPI_PERF_RA_BAR_CU_FULL_CS_R0__SI = 0x0000009d, - SPI_PERF_RA_BULKY_CU_FULL_CSN__CI__VI = 0x0000009d, - SPI_PERF_RA_BAR_CU_FULL_CS_R1__SI = 0x0000009e, - SPI_PERF_RA_TGLIM_CU_FULL_CSG__CI__VI = 0x0000009e, - SPI_PERF_RA_BAR_CU_FULL_CS_R2__SI = 0x0000009f, - SPI_PERF_RA_TGLIM_CU_FULL_CSN__CI__VI = 0x0000009f, - SPI_PERF_RA_TGLIM_CU_FULL_CS_R0__SI = 0x000000a0, - SPI_PERF_RA_WVLIM_STALL_PS__CI__VI = 0x000000a0, - SPI_PERF_RA_TGLIM_CU_FULL_CS_R1__SI = 0x000000a1, - SPI_PERF_RA_WVLIM_STALL_VS__CI__VI = 0x000000a1, - SPI_PERF_RA_TGLIM_CU_FULL_CS_R2__SI = 0x000000a2, - SPI_PERF_RA_WVLIM_STALL_GS__CI__VI = 0x000000a2, - SPI_PERF_RA_WVLIM_STALL_PS__SI = 0x000000a3, - SPI_PERF_RA_WVLIM_STALL_ES__CI__VI = 0x000000a3, - SPI_PERF_RA_WVLIM_STALL_VS__SI = 0x000000a4, - SPI_PERF_RA_WVLIM_STALL_HS__CI__VI = 0x000000a4, - SPI_PERF_RA_WVLIM_STALL_GS__SI = 0x000000a5, - SPI_PERF_RA_WVLIM_STALL_LS__CI__VI = 0x000000a5, - SPI_PERF_RA_WVLIM_STALL_ES__SI = 0x000000a6, - SPI_PERF_RA_WVLIM_STALL_CSG__CI__VI = 0x000000a6, - SPI_PERF_RA_WVLIM_STALL_HS__SI = 0x000000a7, - SPI_PERF_RA_WVLIM_STALL_CSN__CI__VI = 0x000000a7, - SPI_PERF_RA_WVLIM_STALL_LS__SI = 0x000000a8, - SPI_PERF_RA_PS_LOCK__CI = 0x000000a8, - SPI_PERF_RA_PS_LOCK_NA__VI = 0x000000a8, - SPI_PERF_RA_WVLIM_STALL_CS_R0__SI = 0x000000a9, - SPI_PERF_RA_VS_LOCK__CI__VI = 0x000000a9, - SPI_PERF_RA_WVLIM_STALL_CS_R1__SI = 0x000000aa, - SPI_PERF_RA_GS_LOCK__CI__VI = 0x000000aa, - SPI_PERF_RA_WVLIM_STALL_CS_R2__SI = 0x000000ab, - SPI_PERF_RA_ES_LOCK__CI__VI = 0x000000ab, - SPI_PERF_RA_VS_LOCK__SI = 0x000000ac, - SPI_PERF_RA_HS_LOCK__CI__VI = 0x000000ac, - SPI_PERF_RA_GS_LOCK__SI = 0x000000ad, - SPI_PERF_RA_LS_LOCK__CI__VI = 0x000000ad, - SPI_PERF_RA_ES_LOCK__SI = 0x000000ae, - SPI_PERF_RA_CSG_LOCK__CI__VI = 0x000000ae, - SPI_PERF_RA_HS_LOCK__SI = 0x000000af, - SPI_PERF_RA_CSN_LOCK__CI__VI = 0x000000af, - SPI_PERF_RA_LS_LOCK__SI = 0x000000b0, - SPI_PERF_RA_RSV_UPD__CI__VI = 0x000000b0, - SPI_PERF_RA_CS_R0_LOCK__SI = 0x000000b1, - SPI_PERF_EXP_ARB_COL_CNT__CI__VI = 0x000000b1, - SPI_PERF_RA_CS_R1_LOCK__SI = 0x000000b2, - SPI_PERF_EXP_ARB_PAR_CNT__CI__VI = 0x000000b2, - SPI_PERF_RA_CS_R2_LOCK__SI = 0x000000b3, - SPI_PERF_EXP_ARB_POS_CNT__CI__VI = 0x000000b3, - SPI_PERF_EXP_ARB_COL_CNT__SI = 0x000000b4, - SPI_PERF_EXP_ARB_GDS_CNT__CI__VI = 0x000000b4, - SPI_PERF_EXP_ARB_PAR_CNT__SI = 0x000000b5, - SPI_PERF_CLKGATE_BUSY_STALL__CI__VI = 0x000000b5, - SPI_PERF_EXP_ARB_POS_CNT__SI = 0x000000b6, - SPI_PERF_CLKGATE_ACTIVE_STALL__CI__VI = 0x000000b6, - SPI_PERF_EXP_ARB_GDS_CNT__SI = 0x000000b7, - SPI_PERF_CLKGATE_ALL_CLOCKS_ON__CI__VI = 0x000000b7, - SPI_PERF_CLKGATE_BUSY_STALL__SI = 0x000000b8, - SPI_PERF_CLKGATE_CGTT_DYN_ON__CI__VI = 0x000000b8, - SPI_PERF_CLKGATE_ACTIVE_STALL__SI = 0x000000b9, - SPI_PERF_CLKGATE_CGTT_REG_ON__CI__VI = 0x000000b9, - SPI_PERF_CLKGATE_ALL_CLOCKS_ON__SI = 0x000000ba, - SPI_PERF_NUM_VS_POS_EXPORTS__VI = 0x000000ba, - SPI_PERF_CLKGATE_CGTT_DYN_ON__SI = 0x000000bb, - SPI_PERF_NUM_VS_PARAM_EXPORTS__VI = 0x000000bb, - SPI_PERF_CLKGATE_CGTT_REG_ON__SI = 0x000000bc, - SPI_PERF_NUM_PS_COL_EXPORTS__VI = 0x000000bc, - SPI_PERF_ES_GRP_FIFO_FULL__VI = 0x000000bd, - SPI_PERF_GS_GRP_FIFO_FULL__VI = 0x000000be, - SPI_PERF_HS_GRP_FIFO_FULL__VI = 0x000000bf, - SPI_PERF_LS_GRP_FIFO_FULL__VI = 0x000000c0, - SPI_PERF_VS_ALLOC_CNT__VI = 0x000000c1, - SPI_PERF_VS_LATE_ALLOC_ACCUM__VI = 0x000000c2, - SPI_PERF_PC_ALLOC_CNT__VI = 0x000000c3, - SPI_PERF_PC_ALLOC_ACCUM__VI = 0x000000c4, -} SPI_PERFCNT_SEL; - -typedef enum SPI_PNT_SPRITE_OVERRIDE { - SPI_PNT_SPRITE_SEL_0 = 0x00000000, - SPI_PNT_SPRITE_SEL_1 = 0x00000001, - SPI_PNT_SPRITE_SEL_S = 0x00000002, - SPI_PNT_SPRITE_SEL_T = 0x00000003, - SPI_PNT_SPRITE_SEL_NONE = 0x00000004, -} SPI_PNT_SPRITE_OVERRIDE; - -typedef enum SPI_SAMPLE_CNTL { - CENTROIDS_ONLY = 0x00000000, - CENTERS_ONLY = 0x00000001, - CENTROIDS_AND_CENTERS = 0x00000002, - UNDEF = 0x00000003, -} SPI_SAMPLE_CNTL; - -typedef enum SPI_SHADER_EX_FORMAT { - SPI_SHADER_ZERO = 0x00000000, - SPI_SHADER_32_R = 0x00000001, - SPI_SHADER_32_GR = 0x00000002, - SPI_SHADER_32_AR = 0x00000003, - SPI_SHADER_FP16_ABGR = 0x00000004, - SPI_SHADER_UNORM16_ABGR = 0x00000005, - SPI_SHADER_SNORM16_ABGR = 0x00000006, - SPI_SHADER_UINT16_ABGR = 0x00000007, - SPI_SHADER_SINT16_ABGR = 0x00000008, - SPI_SHADER_32_ABGR = 0x00000009, -} SPI_SHADER_EX_FORMAT; - -typedef enum SPI_SHADER_FORMAT { - SPI_SHADER_NONE = 0x00000000, - SPI_SHADER_1COMP = 0x00000001, - SPI_SHADER_2COMP = 0x00000002, - SPI_SHADER_4COMPRESS = 0x00000003, - SPI_SHADER_4COMP = 0x00000004, -} SPI_SHADER_FORMAT; - -typedef enum SPM_PERFMON_STATE { - STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, - STRM_PERFMON_STATE_START_COUNTING = 0x00000001, - STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, - STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, - STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, - STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} SPM_PERFMON_STATE; - -typedef enum SQC_DATA_CACHE_POLICIES { - SQC_DATA_CACHE_POLICY_HIT_LRU = 0x00000000, - SQC_DATA_CACHE_POLICY_MISS_EVICT = 0x00000001, -} SQC_DATA_CACHE_POLICIES; - -typedef enum SQ_CAC_POWER_SEL { - SQ_CAC_POWER_VALU = 0x00000000, - SQ_CAC_POWER_VALU0 = 0x00000001, - SQ_CAC_POWER_VALU1 = 0x00000002, - SQ_CAC_POWER_VALU2 = 0x00000003, - SQ_CAC_POWER_GPR_RD = 0x00000004, - SQ_CAC_POWER_GPR_WR = 0x00000005, - SQ_CAC_POWER_LDS_BUSY = 0x00000006, - SQ_CAC_POWER_ALU_BUSY = 0x00000007, - SQ_CAC_POWER_TEX_BUSY = 0x00000008, -} SQ_CAC_POWER_SEL; - -typedef enum SQ_DED_INFO_SOURCE { - SQ_DED_INFO_SOURCE_INVALID = 0x00000000, - SQ_DED_INFO_SOURCE_INST = 0x00000001, - SQ_DED_INFO_SOURCE_SGPR = 0x00000002, - SQ_DED_INFO_SOURCE_VGPR = 0x00000003, - SQ_DED_INFO_SOURCE_LDS = 0x00000004, - SQ_DED_INFO_SOURCE_GDS = 0x00000005, - SQ_DED_INFO_SOURCE_TA = 0x00000006, -} SQ_DED_INFO_SOURCE; - -typedef enum SQ_IBUF_ST { - SQ_IBUF_IB_IDLE = 0x00000000, - SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, - SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, - SQ_IBUF_IB_LE_4DW = 0x00000003, - SQ_IBUF_IB_WAIT_DRET = 0x00000004, - SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, - SQ_IBUF_IB_DRET = 0x00000006, - SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, -} SQ_IBUF_ST; - -typedef enum SQ_IMG_FILTER_TYPE { - SQ_IMG_FILTER_MODE_BLEND = 0x00000000, - SQ_IMG_FILTER_MODE_MIN = 0x00000001, - SQ_IMG_FILTER_MODE_MAX = 0x00000002, -} SQ_IMG_FILTER_TYPE; - -typedef enum SQ_IND_CMD_CMD { - SQ_IND_CMD_CMD_NULL = 0x00000000, - SQ_IND_CMD_CMD_HALT__SI__CI = 0x00000001, - SQ_IND_CMD_CMD_SETHALT__VI = 0x00000001, - SQ_IND_CMD_CMD_RESUME__SI__CI = 0x00000002, - SQ_IND_CMD_CMD_SAVECTX__VI = 0x00000002, - SQ_IND_CMD_CMD_KILL = 0x00000003, - SQ_IND_CMD_CMD_DEBUG = 0x00000004, - SQ_IND_CMD_CMD_TRAP = 0x00000005, - SQ_IND_CMD_CMD_SET_SPI_PRIO__VI = 0x00000006, -} SQ_IND_CMD_CMD; - -typedef enum SQ_IND_CMD_MODE { - SQ_IND_CMD_MODE_SINGLE = 0x00000000, - SQ_IND_CMD_MODE_BROADCAST = 0x00000001, - SQ_IND_CMD_MODE_BROADCAST_VM_ID__SI = 0x00000002, - SQ_IND_CMD_MODE_BROADCAST_QUEUE__CI__VI = 0x00000002, - SQ_IND_CMD_MODE_BROADCAST_PIPE__CI__VI = 0x00000003, - SQ_IND_CMD_MODE_BROADCAST_ME__CI__VI = 0x00000004, -} SQ_IND_CMD_MODE; - -typedef enum SQ_INST_STR_ST { - SQ_INST_STR_IB_WAVE_NORML = 0x00000000, - SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, - SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, - SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, - SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004, - SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005, - SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006, - SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007, -} SQ_INST_STR_ST; - -typedef enum SQ_INTERRUPT_WORD_ENCODING { - SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000, - SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001, - SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002, -} SQ_INTERRUPT_WORD_ENCODING; - -typedef enum SQ_PERF_SEL { - SQ_PERF_SEL_NONE = 0x00000000, - SQ_PERF_SEL_ACCUM_PREV = 0x00000001, - SQ_PERF_SEL_CYCLES = 0x00000002, - SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, - SQ_PERF_SEL_WAVES = 0x00000004, - SQ_PERF_SEL_LEVEL_WAVES = 0x00000005, - SQ_PERF_SEL_WAVES_CU__SI = 0x00000006, - SQ_PERF_SEL_WAVES_EQ_64__CI__VI = 0x00000006, - SQ_PERF_SEL_LEVEL_WAVES_CU__SI = 0x00000007, - SQ_PERF_SEL_WAVES_LT_64__CI__VI = 0x00000007, - SQ_PERF_SEL_BUSY_CU_CYCLES__SI = 0x00000008, - SQ_PERF_SEL_WAVES_LT_48__CI__VI = 0x00000008, - SQ_PERF_SEL_ITEMS__SI = 0x00000009, - SQ_PERF_SEL_WAVES_LT_32__CI__VI = 0x00000009, - SQ_PERF_SEL_QUADS__SI = 0x0000000a, - SQ_PERF_SEL_WAVES_LT_16__CI__VI = 0x0000000a, - SQ_PERF_SEL_EVENTS__SI = 0x0000000b, - SQ_PERF_SEL_WAVES_CU__CI__VI = 0x0000000b, - SQ_PERF_SEL_SURF_SYNCS__SI = 0x0000000c, - SQ_PERF_SEL_LEVEL_WAVES_CU__CI__VI = 0x0000000c, - SQ_PERF_SEL_INSTS__SI = 0x0000000d, - SQ_PERF_SEL_BUSY_CU_CYCLES__CI__VI = 0x0000000d, - SQ_PERF_SEL_INSTS_VALU__SI = 0x0000000e, - SQ_PERF_SEL_ITEMS__CI__VI = 0x0000000e, - SQ_PERF_SEL_INSTS_VMEM_WR__SI = 0x0000000f, - SQ_PERF_SEL_QUADS__CI__VI = 0x0000000f, - SQ_PERF_SEL_INSTS_VMEM_RD__SI = 0x00000010, - SQ_PERF_SEL_EVENTS__CI__VI = 0x00000010, - SQ_PERF_SEL_INSTS_VMEM__SI = 0x00000011, - SQ_PERF_SEL_SURF_SYNCS__CI__VI = 0x00000011, - SQ_PERF_SEL_INSTS_SALU__SI = 0x00000012, - SQ_PERF_SEL_TTRACE_REQS__CI__VI = 0x00000012, - SQ_PERF_SEL_INSTS_SMEM__SI = 0x00000013, - SQ_PERF_SEL_TTRACE_INFLIGHT_REQS__CI__VI = 0x00000013, - SQ_PERF_SEL_INSTS_LDS__SI = 0x00000014, - SQ_PERF_SEL_TTRACE_STALL__CI__VI = 0x00000014, - SQ_PERF_SEL_INSTS_GDS__SI = 0x00000015, - SQ_PERF_SEL_MSG_CNTR__CI__VI = 0x00000015, - SQ_PERF_SEL_INSTS_EXP__SI = 0x00000016, - SQ_PERF_SEL_MSG_PERF__CI__VI = 0x00000016, - SQ_PERF_SEL_INSTS_BRANCH__SI = 0x00000017, - SQ_PERF_SEL_MSG_GSCNT__CI__VI = 0x00000017, - SQ_PERF_SEL_INSTS_SENDMSG__SI = 0x00000018, - SQ_PERF_SEL_MSG_INTERRUPT__CI__VI = 0x00000018, - SQ_PERF_SEL_INST_LEVEL_VMEM__SI = 0x00000019, - SQ_PERF_SEL_INSTS__CI__VI = 0x00000019, - SQ_PERF_SEL_INST_LEVEL_SMEM__SI = 0x0000001a, - SQ_PERF_SEL_INSTS_VALU__CI__VI = 0x0000001a, - SQ_PERF_SEL_INST_LEVEL_LDS__SI = 0x0000001b, - SQ_PERF_SEL_INSTS_VMEM_WR__CI__VI = 0x0000001b, - SQ_PERF_SEL_INST_LEVEL_GDS__SI = 0x0000001c, - SQ_PERF_SEL_INSTS_VMEM_RD__CI__VI = 0x0000001c, - SQ_PERF_SEL_INST_LEVEL_EXP__SI = 0x0000001d, - SQ_PERF_SEL_INSTS_VMEM__CI__VI = 0x0000001d, - SQ_PERF_SEL_WAIT_CNT_VM__SI = 0x0000001e, - SQ_PERF_SEL_INSTS_SALU__CI__VI = 0x0000001e, - SQ_PERF_SEL_WAIT_CNT_LGKM__SI = 0x0000001f, - SQ_PERF_SEL_INSTS_SMEM__CI__VI = 0x0000001f, - SQ_PERF_SEL_WAIT_CNT_EXP__SI = 0x00000020, - SQ_PERF_SEL_INSTS_FLAT__CI__VI = 0x00000020, - SQ_PERF_SEL_WAIT_CNT_ANY__SI = 0x00000021, - SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY__CI__VI = 0x00000021, - SQ_PERF_SEL_WAIT_BARRIER__SI = 0x00000022, - SQ_PERF_SEL_INSTS_LDS__CI__VI = 0x00000022, - SQ_PERF_SEL_WAIT_EXP_ALLOC__SI = 0x00000023, - SQ_PERF_SEL_INSTS_GDS__CI__VI = 0x00000023, - SQ_PERF_SEL_WAIT_SLEEP__SI = 0x00000024, - SQ_PERF_SEL_INSTS_EXP__CI__VI = 0x00000024, - SQ_PERF_SEL_WAIT_INST_VMEM__SI = 0x00000025, - SQ_PERF_SEL_INSTS_EXP_GDS__CI__VI = 0x00000025, - SQ_PERF_SEL_WAIT_INST_SCA__SI = 0x00000026, - SQ_PERF_SEL_INSTS_BRANCH__CI__VI = 0x00000026, - SQ_PERF_SEL_WAIT_INST_LDS__SI = 0x00000027, - SQ_PERF_SEL_INSTS_SENDMSG__CI__VI = 0x00000027, - SQ_PERF_SEL_WAIT_INST_VALU__SI = 0x00000028, - SQ_PERF_SEL_INSTS_VSKIPPED__CI__VI = 0x00000028, - SQ_PERF_SEL_WAIT_INST_EXP_GDS__SI = 0x00000029, - SQ_PERF_SEL_INST_LEVEL_VMEM__CI__VI = 0x00000029, - SQ_PERF_SEL_WAIT_INST_MISC__SI = 0x0000002a, - SQ_PERF_SEL_INST_LEVEL_SMEM__CI__VI = 0x0000002a, - SQ_PERF_SEL_INST_CYCLES_VMEM_WR__SI = 0x0000002b, - SQ_PERF_SEL_INST_LEVEL_LDS__CI__VI = 0x0000002b, - SQ_PERF_SEL_INST_CYCLES_VMEM_RD__SI = 0x0000002c, - SQ_PERF_SEL_INST_LEVEL_GDS__CI__VI = 0x0000002c, - SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR__SI = 0x0000002d, - SQ_PERF_SEL_INST_LEVEL_EXP__CI__VI = 0x0000002d, - SQ_PERF_SEL_INST_CYCLES_VMEM_DATA__SI = 0x0000002e, - SQ_PERF_SEL_WAVE_CYCLES__CI__VI = 0x0000002e, - SQ_PERF_SEL_INST_CYCLES_VMEM_CMD__SI = 0x0000002f, - SQ_PERF_SEL_WAVE_READY__CI__VI = 0x0000002f, - SQ_PERF_SEL_INST_CYCLES_VMEM__SI = 0x00000030, - SQ_PERF_SEL_WAIT_CNT_VM__CI__VI = 0x00000030, - SQ_PERF_SEL_INST_CYCLES_LDS__SI = 0x00000031, - SQ_PERF_SEL_WAIT_CNT_LGKM__CI__VI = 0x00000031, - SQ_PERF_SEL_INST_CYCLES_VALU__SI = 0x00000032, - SQ_PERF_SEL_WAIT_CNT_EXP__CI__VI = 0x00000032, - SQ_PERF_SEL_INST_CYCLES_EXP__SI = 0x00000033, - SQ_PERF_SEL_WAIT_CNT_ANY__CI__VI = 0x00000033, - SQ_PERF_SEL_INST_CYCLES_GDS__SI = 0x00000034, - SQ_PERF_SEL_WAIT_BARRIER__CI__VI = 0x00000034, - SQ_PERF_SEL_INST_CYCLES_SCA__SI = 0x00000035, - SQ_PERF_SEL_WAIT_EXP_ALLOC__CI__VI = 0x00000035, - SQ_PERF_SEL_INST_CYCLES_SMEM__SI = 0x00000036, - SQ_PERF_SEL_WAIT_SLEEP__CI__VI = 0x00000036, - SQ_PERF_SEL_INST_CYCLES_SALU__SI = 0x00000037, - SQ_PERF_SEL_WAIT_OTHER__CI__VI = 0x00000037, - SQ_PERF_SEL_INST_CYCLES_EXP_GDS__SI = 0x00000038, - SQ_PERF_SEL_WAIT_ANY__CI__VI = 0x00000038, - SQ_PERF_SEL_INST_CYCLES_MISC__SI = 0x00000039, - SQ_PERF_SEL_WAIT_TTRACE__CI__VI = 0x00000039, - SQ_PERF_SEL_THREAD_CYCLES_VALU__SI = 0x0000003a, - SQ_PERF_SEL_WAIT_IFETCH__CI__VI = 0x0000003a, - SQ_PERF_SEL_INST_FETCH__SI = 0x0000003b, - SQ_PERF_SEL_WAIT_INST_VMEM__CI__VI = 0x0000003b, - SQ_PERF_SEL_VALU_LDS_DIRECT_RD__SI = 0x0000003c, - SQ_PERF_SEL_WAIT_INST_SCA__CI__VI = 0x0000003c, - SQ_PERF_SEL_VALU_LDS_INTERP_OP__SI = 0x0000003d, - SQ_PERF_SEL_WAIT_INST_LDS__CI__VI = 0x0000003d, - SQ_PERF_SEL_LDS_BANK_CONFLICT__SI = 0x0000003e, - SQ_PERF_SEL_WAIT_INST_VALU__CI__VI = 0x0000003e, - SQ_PERF_SEL_LDS_ADDR_CONFLICT__SI = 0x0000003f, - SQ_PERF_SEL_WAIT_INST_EXP_GDS__CI__VI = 0x0000003f, - SQ_PERF_SEL_VALU_DEP_STALL__SI = 0x00000040, - SQ_PERF_SEL_WAIT_INST_MISC__CI__VI = 0x00000040, - SQ_PERF_SEL_EXP_REQ_FIFO_FULL__SI = 0x00000041, - SQ_PERF_SEL_WAIT_INST_FLAT__CI__VI = 0x00000041, - SQ_PERF_SEL_LDS_BACK2BACK_STALL__SI = 0x00000042, - SQ_PERF_SEL_ACTIVE_INST_ANY__CI__VI = 0x00000042, - SQ_PERF_SEL_LDS_DATA_FIFO_FULL__SI = 0x00000043, - SQ_PERF_SEL_ACTIVE_INST_VMEM__CI__VI = 0x00000043, - SQ_PERF_SEL_LDS_CMD_FIFO_FULL__SI = 0x00000044, - SQ_PERF_SEL_ACTIVE_INST_LDS__CI__VI = 0x00000044, - SQ_PERF_SEL_VMEM_BACK2BACK_STALL__SI = 0x00000045, - SQ_PERF_SEL_ACTIVE_INST_VALU__CI__VI = 0x00000045, - SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL__SI = 0x00000046, - SQ_PERF_SEL_ACTIVE_INST_SCA__CI__VI = 0x00000046, - SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL__SI = 0x00000047, - SQ_PERF_SEL_ACTIVE_INST_EXP_GDS__CI__VI = 0x00000047, - SQ_PERF_SEL_VMEM_EX_DATA_FIFO_FULL__SI = 0x00000048, - SQ_PERF_SEL_ACTIVE_INST_MISC__CI__VI = 0x00000048, - SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL__SI = 0x00000049, - SQ_PERF_SEL_ACTIVE_INST_FLAT__CI__VI = 0x00000049, - SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL__SI = 0x0000004a, - SQ_PERF_SEL_INST_CYCLES_VMEM_WR__CI__VI = 0x0000004a, - SQ_PERF_SEL_VALU_SRC_C_CONFLICT__SI = 0x0000004b, - SQ_PERF_SEL_INST_CYCLES_VMEM_RD__CI__VI = 0x0000004b, - SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT__SI = 0x0000004c, - SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR__CI__VI = 0x0000004c, - SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT__SI = 0x0000004d, - SQ_PERF_SEL_INST_CYCLES_VMEM_DATA__CI__VI = 0x0000004d, - SQ_PERF_SEL_LDS_SRC_CD_CONFLICT__SI = 0x0000004e, - SQ_PERF_SEL_INST_CYCLES_VMEM_CMD__CI__VI = 0x0000004e, - SQ_PERF_SEL_PT_POWER_STALL__SI = 0x0000004f, - SQ_PERF_SEL_INST_CYCLES_VMEM__CI__VI = 0x0000004f, - SQ_PERF_SEL_PT_POWER_CREDIT_USED__SI = 0x00000050, - SQ_PERF_SEL_INST_CYCLES_LDS__CI__VI = 0x00000050, - SQ_PERF_SEL_TTRACE_STALL__SI = 0x00000051, - SQ_PERF_SEL_INST_CYCLES_VALU__CI__VI = 0x00000051, - SQ_PERF_SEL_USER0__SI = 0x00000052, - SQ_PERF_SEL_INST_CYCLES_EXP__CI__VI = 0x00000052, - SQ_PERF_SEL_USER1__SI = 0x00000053, - SQ_PERF_SEL_INST_CYCLES_GDS__CI__VI = 0x00000053, - SQ_PERF_SEL_USER2__SI = 0x00000054, - SQ_PERF_SEL_INST_CYCLES_SCA__CI__VI = 0x00000054, - SQ_PERF_SEL_USER3__SI = 0x00000055, - SQ_PERF_SEL_INST_CYCLES_SMEM__CI__VI = 0x00000055, - SQ_PERF_SEL_USER4__SI = 0x00000056, - SQ_PERF_SEL_INST_CYCLES_SALU__CI__VI = 0x00000056, - SQ_PERF_SEL_USER5__SI = 0x00000057, - SQ_PERF_SEL_INST_CYCLES_EXP_GDS__CI__VI = 0x00000057, - SQ_PERF_SEL_USER6__SI = 0x00000058, - SQ_PERF_SEL_INST_CYCLES_MISC__CI__VI = 0x00000058, - SQ_PERF_SEL_USER7__SI = 0x00000059, - SQ_PERF_SEL_THREAD_CYCLES_VALU__CI__VI = 0x00000059, - SQ_PERF_SEL_USER8__SI = 0x0000005a, - SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX__CI__VI = 0x0000005a, - SQ_PERF_SEL_USER9__SI = 0x0000005b, - SQ_PERF_SEL_IFETCH__CI__VI = 0x0000005b, - SQ_PERF_SEL_USER10__SI = 0x0000005c, - SQ_PERF_SEL_IFETCH_LEVEL__CI__VI = 0x0000005c, - SQ_PERF_SEL_USER11__SI = 0x0000005d, - SQ_PERF_SEL_CBRANCH_FORK__CI__VI = 0x0000005d, - SQ_PERF_SEL_USER12__SI = 0x0000005e, - SQ_PERF_SEL_CBRANCH_FORK_SPLIT__CI__VI = 0x0000005e, - SQ_PERF_SEL_USER13__SI = 0x0000005f, - SQ_PERF_SEL_VALU_LDS_DIRECT_RD__CI__VI = 0x0000005f, - SQ_PERF_SEL_USER14__SI = 0x00000060, - SQ_PERF_SEL_VALU_LDS_INTERP_OP__CI__VI = 0x00000060, - SQ_PERF_SEL_USER15__SI = 0x00000061, - SQ_PERF_SEL_LDS_BANK_CONFLICT__CI__VI = 0x00000061, - SQ_PERF_SEL_USER_LEVEL0__SI = 0x00000062, - SQ_PERF_SEL_LDS_ADDR_CONFLICT__CI__VI = 0x00000062, - SQ_PERF_SEL_USER_LEVEL1__SI = 0x00000063, - SQ_PERF_SEL_LDS_UNALIGNED_STALL__CI__VI = 0x00000063, - SQ_PERF_SEL_USER_LEVEL2__SI = 0x00000064, - SQ_PERF_SEL_LDS_MEM_VIOLATIONS__CI__VI = 0x00000064, - SQ_PERF_SEL_USER_LEVEL3__SI = 0x00000065, - SQ_PERF_SEL_LDS_ATOMIC_RETURN__CI__VI = 0x00000065, - SQ_PERF_SEL_USER_LEVEL4__SI = 0x00000066, - SQ_PERF_SEL_LDS_IDX_ACTIVE__CI__VI = 0x00000066, - SQ_PERF_SEL_USER_LEVEL5__SI = 0x00000067, - SQ_PERF_SEL_VALU_DEP_STALL__CI__VI = 0x00000067, - SQ_PERF_SEL_USER_LEVEL6__SI = 0x00000068, - SQ_PERF_SEL_VALU_STARVE__CI__VI = 0x00000068, - SQ_PERF_SEL_USER_LEVEL7__SI = 0x00000069, - SQ_PERF_SEL_EXP_REQ_FIFO_FULL__CI__VI = 0x00000069, - SQ_PERF_SEL_USER_LEVEL8__SI = 0x0000006a, - SQ_PERF_SEL_LDS_BACK2BACK_STALL__CI__VI = 0x0000006a, - SQ_PERF_SEL_USER_LEVEL9__SI = 0x0000006b, - SQ_PERF_SEL_LDS_DATA_FIFO_FULL__CI__VI = 0x0000006b, - SQ_PERF_SEL_USER_LEVEL10__SI = 0x0000006c, - SQ_PERF_SEL_LDS_CMD_FIFO_FULL__CI__VI = 0x0000006c, - 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0x000000d4, - SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC__CI__VI = 0x000000d4, - SQC_PERF_SEL_ICACHE_SQ0_STALL_BANK_ARB_NO_GNT__SI = 0x000000d5, - SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT__CI = 0x000000d5, - SQC_PERF_SEL_DCACHE_WB_INST__VI = 0x000000d5, - SQC_PERF_SEL_ICACHE_SQ1_STALL_BANK_ARB_NO_GNT__SI = 0x000000d6, - SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB__CI = 0x000000d6, - SQC_PERF_SEL_DCACHE_WB_ASYNC__VI = 0x000000d6, - SQC_PERF_SEL_ICACHE_SQ2_STALL_BANK_ARB_NO_GNT__SI = 0x000000d7, - SQC_PERF_SEL_DCACHE_CACHE_STALLED__CI = 0x000000d7, - SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST__VI = 0x000000d7, - SQC_PERF_SEL_ICACHE_SQ3_STALL_BANK_ARB_NO_GNT__SI = 0x000000d8, - SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO__CI = 0x000000d8, - SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC__VI = 0x000000d8, - SQC_PERF_SEL_ICACHE_SQ0_STALL_BANK_ARB_NOT_RDY__SI = 0x000000d9, - SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX__CI = 0x000000d9, - SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT__VI = 0x000000d9, - SQC_PERF_SEL_ICACHE_SQ1_STALL_BANK_ARB_NOT_RDY__SI = 0x000000da, - SQC_PERF_SEL_DCACHE_CACHE_STALL_VOLATILE_MISMATCH__CI = 0x000000da, - SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB__VI = 0x000000da, - SQC_PERF_SEL_ICACHE_SQ2_STALL_BANK_ARB_NOT_RDY__SI = 0x000000db, - SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT__CI = 0x000000db, - SQC_PERF_SEL_DCACHE_CACHE_STALLED__VI = 0x000000db, - SQC_PERF_SEL_ICACHE_SQ3_STALL_BANK_ARB_NOT_RDY__SI = 0x000000dc, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT__CI = 0x000000dc, - SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX__VI = 0x000000dc, - SQC_PERF_SEL_ICACHE_IDLE__SI = 0x000000dd, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO__CI = 0x000000dd, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT__VI = 0x000000dd, - SQC_PERF_SEL_ICACHE_BANKA_IDLE__SI = 0x000000de, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO__CI = 0x000000de, - SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT__VI = 0x000000de, - SQC_PERF_SEL_ICACHE_BANKB_IDLE__SI = 0x000000df, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF__CI = 0x000000df, - SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED__VI = 0x000000df, - SQC_PERF_SEL_ICACHE_BANKC_IDLE__SI = 0x000000e0, - SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT__CI = 0x000000e0, - SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE__VI = 0x000000e0, - SQC_PERF_SEL_ICACHE_BANKD_IDLE__SI = 0x000000e1, - SQC_PERF_SEL_DCACHE_REQ_1__CI = 0x000000e1, - SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT__VI = 0x000000e1, - SQC_PERF_SEL_ICACHE_NOT_STALL__SI = 0x000000e2, - SQC_PERF_SEL_DCACHE_REQ_2__CI = 0x000000e2, - SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH__VI = 0x000000e2, - SQC_PERF_SEL_ICACHE_BANKA_NOT_STALL__SI = 0x000000e3, - SQC_PERF_SEL_DCACHE_REQ_4__CI = 0x000000e3, - SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE__VI = 0x000000e3, - SQC_PERF_SEL_ICACHE_BANKB_NOT_STALL__SI = 0x000000e4, - SQC_PERF_SEL_DCACHE_REQ_8__CI = 0x000000e4, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO__VI = 0x000000e4, - SQC_PERF_SEL_ICACHE_BANKC_NOT_STALL__SI = 0x000000e5, - SQC_PERF_SEL_DCACHE_REQ_16__CI = 0x000000e5, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO__VI = 0x000000e5, - SQC_PERF_SEL_ICACHE_BANKD_NOT_STALL__SI = 0x000000e6, - SQC_PERF_SEL_DCACHE_REQ_TIME__CI = 0x000000e6, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF__VI = 0x000000e6, - SQC_PERF_SEL_ICACHE_STALL_INFLIGHT_NONZERO__SI = 0x000000e7, - SQC_PERF_SEL_SQ_DCACHE_REQS__CI = 0x000000e7, - SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT__VI = 0x000000e7, - SQC_PERF_SEL_ICACHE_BANKA_STALL_INFLIGHT_NONZERO__SI = 0x000000e8, - SQC_PERF_SEL_DCACHE_FLAT_REQ__CI = 0x000000e8, - SQC_PERF_SEL_DCACHE_REQ_READ_1__VI = 0x000000e8, - SQC_PERF_SEL_ICACHE_BANKB_STALL_INFLIGHT_NONZERO__SI = 0x000000e9, - SQC_PERF_SEL_DCACHE_NONFLAT_REQ__CI = 0x000000e9, - SQC_PERF_SEL_DCACHE_REQ_READ_2__VI = 0x000000e9, - SQC_PERF_SEL_ICACHE_BANKC_STALL_INFLIGHT_NONZERO__SI = 0x000000ea, - SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL__CI = 0x000000ea, - SQC_PERF_SEL_DCACHE_REQ_READ_4__VI = 0x000000ea, - SQC_PERF_SEL_ICACHE_BANKD_STALL_INFLIGHT_NONZERO__SI = 0x000000eb, - SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL__CI = 0x000000eb, - SQC_PERF_SEL_DCACHE_REQ_READ_8__VI = 0x000000eb, - SQC_PERF_SEL_ICACHE_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x000000ec, - SQC_PERF_SEL_ICACHE_POST_CC_LEVEL__CI = 0x000000ec, - SQC_PERF_SEL_DCACHE_REQ_READ_16__VI = 0x000000ec, - SQC_PERF_SEL_ICACHE_BANKA_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x000000ed, - SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL__CI = 0x000000ed, - SQC_PERF_SEL_DCACHE_REQ_TIME__VI = 0x000000ed, - SQC_PERF_SEL_ICACHE_BANKB_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x000000ee, - SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL__CI = 0x000000ee, - SQC_PERF_SEL_DCACHE_REQ_WRITE_1__VI = 0x000000ee, - SQC_PERF_SEL_ICACHE_BANKC_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x000000ef, - SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL__CI = 0x000000ef, - SQC_PERF_SEL_DCACHE_REQ_WRITE_2__VI = 0x000000ef, - SQC_PERF_SEL_ICACHE_BANKD_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x000000f0, - SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL__CI = 0x000000f0, - SQC_PERF_SEL_DCACHE_REQ_WRITE_4__VI = 0x000000f0, - SQC_PERF_SEL_ICACHE_STALL_INFLIGHT_MAX__SI = 0x000000f1, - SQC_PERF_SEL_DCACHE_POST_CC_LEVEL__CI = 0x000000f1, - SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE__VI = 0x000000f1, - SQC_PERF_SEL_ICACHE_BANKA_STALL_INFLIGHT_MAX__SI = 0x000000f2, - SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL__CI = 0x000000f2, - SQC_PERF_SEL_SQ_DCACHE_REQS__VI = 0x000000f2, - SQC_PERF_SEL_ICACHE_BANKB_STALL_INFLIGHT_MAX__SI = 0x000000f3, - SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL__CI = 0x000000f3, - SQC_PERF_SEL_DCACHE_FLAT_REQ__VI = 0x000000f3, - SQC_PERF_SEL_ICACHE_BANKC_STALL_INFLIGHT_MAX__SI = 0x000000f4, - SQC_PERF_SEL_TC_INFLIGHT_LEVEL__CI = 0x000000f4, - SQC_PERF_SEL_DCACHE_NONFLAT_REQ__VI = 0x000000f4, - SQC_PERF_SEL_ICACHE_BANKD_STALL_INFLIGHT_MAX__SI = 0x000000f5, - SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL__CI = 0x000000f5, - SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL__VI = 0x000000f5, - SQC_PERF_SEL_ICACHE_STALL_OUTPUT__SI = 0x000000f6, - SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL__CI = 0x000000f6, - SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL__VI = 0x000000f6, - SQC_PERF_SEL_ICACHE_BANKA_STALL_OUTPUT__SI = 0x000000f7, - SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED__CI = 0x000000f7, - SQC_PERF_SEL_TC_INFLIGHT_LEVEL__VI = 0x000000f7, - SQC_PERF_SEL_ICACHE_BANKB_STALL_OUTPUT__SI = 0x000000f8, - SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED__CI = 0x000000f8, - SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL__VI = 0x000000f8, - SQC_PERF_SEL_ICACHE_BANKC_STALL_OUTPUT__SI = 0x000000f9, - SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED__CI = 0x000000f9, - SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL__VI = 0x000000f9, - SQC_PERF_SEL_ICACHE_BANKD_STALL_OUTPUT__SI = 0x000000fa, - SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED__CI = 0x000000fa, - SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS__VI = 0x000000fa, - SQC_PERF_SEL_ICACHE_STALL_OUTPUT_MISS_FIFO__SI = 0x000000fb, - SQC_PERF_SEL_DUMMY_LAST__CI = 0x000000fb, - SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS__VI = 0x000000fb, - SQC_PERF_SEL_ICACHE_BANKA_STALL_OUTPUT_MISS_FIFO__SI = 0x000000fc, - SQC_PERF_SEL_ICACHE_GATCL1_REQUEST__VI = 0x000000fc, - SQC_PERF_SEL_ICACHE_BANKB_STALL_OUTPUT_MISS_FIFO__SI = 0x000000fd, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX__VI = 0x000000fd, - SQC_PERF_SEL_ICACHE_BANKC_STALL_OUTPUT_MISS_FIFO__SI = 0x000000fe, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT__VI = 0x000000fe, - SQC_PERF_SEL_ICACHE_BANKD_STALL_OUTPUT_MISS_FIFO__SI = 0x000000ff, - SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL__VI = 0x000000ff, - SQC_PERF_SEL_ICACHE_STALL_OUTPUT_HIT_FIFO__SI = 0x00000100, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x00000100, - SQC_PERF_SEL_ICACHE_BANKA_STALL_OUTPUT_HIT_FIFO__SI = 0x00000101, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS__VI = 0x00000101, - SQC_PERF_SEL_ICACHE_BANKB_STALL_OUTPUT_HIT_FIFO__SI = 0x00000102, - SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT__VI = 0x00000102, - SQC_PERF_SEL_ICACHE_BANKC_STALL_OUTPUT_HIT_FIFO__SI = 0x00000103, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL__VI = 0x00000103, - SQC_PERF_SEL_ICACHE_BANKD_STALL_OUTPUT_HIT_FIFO__SI = 0x00000104, - SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS__VI = 0x00000104, - SQC_PERF_SEL_ICACHE_STALL_OUTPUT_MISS_TC__SI = 0x00000105, - SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS__VI = 0x00000105, - SQC_PERF_SEL_ICACHE_BANKA_STALL_OUTPUT_MISS_TC__SI = 0x00000106, - SQC_PERF_SEL_DCACHE_GATCL1_REQUEST__VI = 0x00000106, - SQC_PERF_SEL_ICACHE_BANKB_STALL_OUTPUT_MISS_TC__SI = 0x00000107, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX__VI = 0x00000107, - SQC_PERF_SEL_ICACHE_BANKC_STALL_OUTPUT_MISS_TC__SI = 0x00000108, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT__VI = 0x00000108, - SQC_PERF_SEL_ICACHE_BANKD_STALL_OUTPUT_MISS_TC__SI = 0x00000109, - SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL__VI = 0x00000109, - SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB__SI = 0x0000010a, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x0000010a, - SQC_PERF_SEL_ICACHE_BANKA_STALL_OUTXBAR_ARB__SI = 0x0000010b, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS__VI = 0x0000010b, - SQC_PERF_SEL_ICACHE_BANKB_STALL_OUTXBAR_ARB__SI = 0x0000010c, - SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT__VI = 0x0000010c, - SQC_PERF_SEL_ICACHE_BANKC_STALL_OUTXBAR_ARB__SI = 0x0000010d, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL__VI = 0x0000010d, - SQC_PERF_SEL_ICACHE_BANKD_STALL_OUTXBAR_ARB__SI = 0x0000010e, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS__VI = 0x0000010e, - SQC_PERF_SEL_DCACHE_BUSY_CYCLES__SI = 0x0000010f, - SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL__VI = 0x0000010f, - SQC_PERF_SEL_DCACHE_INVAL__SI = 0x00000110, - SQC_PERF_SEL_DUMMY_LAST__VI = 0x00000110, - SQC_PERF_SEL_DCACHE_REQ__SI = 0x00000111, - SQ_PERF_SEL_INSTS_SMEM_NORM__VI = 0x00000111, - SQC_PERF_SEL_DCACHE_SQ0_REQ__SI = 0x00000112, - SQ_PERF_SEL_ATC_INSTS_VMEM__VI = 0x00000112, - SQC_PERF_SEL_DCACHE_SQ1_REQ__SI = 0x00000113, - SQ_PERF_SEL_ATC_INST_LEVEL_VMEM__VI = 0x00000113, - SQC_PERF_SEL_DCACHE_SQ2_REQ__SI = 0x00000114, - SQ_PERF_SEL_ATC_XNACK_FIRST__VI = 0x00000114, - SQC_PERF_SEL_DCACHE_SQ3_REQ__SI = 0x00000115, - SQ_PERF_SEL_ATC_XNACK_ALL__VI = 0x00000115, - SQC_PERF_SEL_DCACHE_BANKA_REQ__SI = 0x00000116, - SQ_PERF_SEL_ATC_XNACK_FIFO_FULL__VI = 0x00000116, - SQC_PERF_SEL_DCACHE_BANKB_REQ__SI = 0x00000117, - SQ_PERF_SEL_ATC_INSTS_SMEM__VI = 0x00000117, - SQC_PERF_SEL_DCACHE_BANKC_REQ__SI = 0x00000118, - SQ_PERF_SEL_ATC_INST_LEVEL_SMEM__VI = 0x00000118, - SQC_PERF_SEL_DCACHE_BANKD_REQ__SI = 0x00000119, - SQ_PERF_SEL_IFETCH_XNACK__VI = 0x00000119, - SQC_PERF_SEL_DCACHE_SQ0_BANKA_REQ__SI = 0x0000011a, - SQ_PERF_SEL_TLB_SHOOTDOWN__VI = 0x0000011a, - SQC_PERF_SEL_DCACHE_SQ0_BANKB_REQ__SI = 0x0000011b, - SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES__VI = 0x0000011b, - SQC_PERF_SEL_DCACHE_SQ0_BANKC_REQ__SI = 0x0000011c, - SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY__VI = 0x0000011c, - SQC_PERF_SEL_DCACHE_SQ0_BANKD_REQ__SI = 0x0000011d, - SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY__VI = 0x0000011d, - SQC_PERF_SEL_DCACHE_SQ1_BANKA_REQ__SI = 0x0000011e, - SQ_PERF_SEL_INSTS_VMEM_REPLAY__VI = 0x0000011e, - SQC_PERF_SEL_DCACHE_SQ1_BANKB_REQ__SI = 0x0000011f, - SQ_PERF_SEL_INSTS_SMEM_REPLAY__VI = 0x0000011f, - SQC_PERF_SEL_DCACHE_SQ1_BANKC_REQ__SI = 0x00000120, - SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY__VI = 0x00000120, - SQC_PERF_SEL_DCACHE_SQ1_BANKD_REQ__SI = 0x00000121, - SQ_PERF_SEL_INSTS_FLAT_REPLAY__VI = 0x00000121, - SQC_PERF_SEL_DCACHE_SQ2_BANKA_REQ__SI = 0x00000122, - SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY__VI = 0x00000122, - SQC_PERF_SEL_DCACHE_SQ2_BANKB_REQ__SI = 0x00000123, - SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY__VI = 0x00000123, - SQC_PERF_SEL_DCACHE_SQ2_BANKC_REQ__SI = 0x00000124, - SQC_PERF_SEL_DCACHE_SQ2_BANKD_REQ__SI = 0x00000125, - SQC_PERF_SEL_DCACHE_SQ3_BANKA_REQ__SI = 0x00000126, - SQC_PERF_SEL_DCACHE_SQ3_BANKB_REQ__SI = 0x00000127, - SQC_PERF_SEL_DCACHE_SQ3_BANKC_REQ__SI = 0x00000128, - SQC_PERF_SEL_DCACHE_SQ3_BANKD_REQ__SI = 0x00000129, - SQC_PERF_SEL_DCACHE_REQ_1__SI = 0x0000012a, - SQ_PERF_SEL_DUMMY_LAST1__VI = 0x0000012a, - SQC_PERF_SEL_DCACHE_REQ_2__SI = 0x0000012b, - SQC_PERF_SEL_DCACHE_REQ_4__SI = 0x0000012c, - SQC_PERF_SEL_DCACHE_REQ_8__SI = 0x0000012d, - SQC_PERF_SEL_DCACHE_REQ_16__SI = 0x0000012e, - SQC_PERF_SEL_DCACHE_REQ_TIME__SI = 0x0000012f, - SQC_PERF_SEL_DCACHE_HITS__SI = 0x00000130, - SQC_PERF_SEL_DCACHE_SQ0_HITS__SI = 0x00000131, - SQC_PERF_SEL_DCACHE_SQ1_HITS__SI = 0x00000132, - SQC_PERF_SEL_DCACHE_SQ2_HITS__SI = 0x00000133, - SQC_PERF_SEL_DCACHE_SQ3_HITS__SI = 0x00000134, - SQC_PERF_SEL_DCACHE_BANKA_HITS__SI = 0x00000135, - SQC_PERF_SEL_DCACHE_BANKB_HITS__SI = 0x00000136, - SQC_PERF_SEL_DCACHE_BANKC_HITS__SI = 0x00000137, - SQC_PERF_SEL_DCACHE_BANKD_HITS__SI = 0x00000138, - SQC_PERF_SEL_DCACHE_MISSES__SI = 0x00000139, - SQC_PERF_SEL_DCACHE_SQ0_MISSES__SI = 0x0000013a, - SQC_PERF_SEL_DCACHE_SQ1_MISSES__SI = 0x0000013b, - SQC_PERF_SEL_DCACHE_SQ2_MISSES__SI = 0x0000013c, - SQC_PERF_SEL_DCACHE_SQ3_MISSES__SI = 0x0000013d, - SQC_PERF_SEL_DCACHE_BANKA_MISSES__SI = 0x0000013e, - SQC_PERF_SEL_DCACHE_BANKB_MISSES__SI = 0x0000013f, - SQC_PERF_SEL_DCACHE_BANKC_MISSES__SI = 0x00000140, - SQC_PERF_SEL_DCACHE_BANKD_MISSES__SI = 0x00000141, - SQC_PERF_SEL_DCACHE_DUPL_MISSES__SI = 0x00000142, - SQC_PERF_SEL_DCACHE_SQ0_DUPL_MISSES__SI = 0x00000143, - SQC_PERF_SEL_DCACHE_SQ1_DUPL_MISSES__SI = 0x00000144, - SQC_PERF_SEL_DCACHE_SQ2_DUPL_MISSES__SI = 0x00000145, - SQC_PERF_SEL_DCACHE_SQ3_DUPL_MISSES__SI = 0x00000146, - SQC_PERF_SEL_DCACHE_BANKA_DUPL_MISSES__SI = 0x00000147, - SQC_PERF_SEL_DCACHE_BANKB_DUPL_MISSES__SI = 0x00000148, - SQC_PERF_SEL_DCACHE_BANKC_DUPL_MISSES__SI = 0x00000149, - SQC_PERF_SEL_DCACHE_BANKD_DUPL_MISSES__SI = 0x0000014a, - SQC_PERF_SEL_DCACHE_SQ0_STALL_BANK_ARB__SI = 0x0000014b, - SQC_PERF_SEL_DCACHE_SQ1_STALL_BANK_ARB__SI = 0x0000014c, - SQC_PERF_SEL_DCACHE_SQ2_STALL_BANK_ARB__SI = 0x0000014d, - SQC_PERF_SEL_DCACHE_SQ3_STALL_BANK_ARB__SI = 0x0000014e, - SQC_PERF_SEL_DCACHE_SQ0_STALL_BANK_ARB_NO_GNT__SI = 0x0000014f, - SQC_PERF_SEL_DCACHE_SQ1_STALL_BANK_ARB_NO_GNT__SI = 0x00000150, - SQC_PERF_SEL_DCACHE_SQ2_STALL_BANK_ARB_NO_GNT__SI = 0x00000151, - SQC_PERF_SEL_DCACHE_SQ3_STALL_BANK_ARB_NO_GNT__SI = 0x00000152, - SQC_PERF_SEL_DCACHE_SQ0_STALL_BANK_ARB_NOT_RDY__SI = 0x00000153, - SQC_PERF_SEL_DCACHE_SQ1_STALL_BANK_ARB_NOT_RDY__SI = 0x00000154, - SQC_PERF_SEL_DCACHE_SQ2_STALL_BANK_ARB_NOT_RDY__SI = 0x00000155, - SQC_PERF_SEL_DCACHE_SQ3_STALL_BANK_ARB_NOT_RDY__SI = 0x00000156, - SQC_PERF_SEL_DCACHE_IDLE__SI = 0x00000157, - SQC_PERF_SEL_DCACHE_BANKA_IDLE__SI = 0x00000158, - SQC_PERF_SEL_DCACHE_BANKB_IDLE__SI = 0x00000159, - SQC_PERF_SEL_DCACHE_BANKC_IDLE__SI = 0x0000015a, - SQC_PERF_SEL_DCACHE_BANKD_IDLE__SI = 0x0000015b, - SQC_PERF_SEL_DCACHE_NOT_STALL__SI = 0x0000015c, - SQC_PERF_SEL_DCACHE_BANKA_NOT_STALL__SI = 0x0000015d, - SQC_PERF_SEL_DCACHE_BANKB_NOT_STALL__SI = 0x0000015e, - SQC_PERF_SEL_DCACHE_BANKC_NOT_STALL__SI = 0x0000015f, - SQC_PERF_SEL_DCACHE_BANKD_NOT_STALL__SI = 0x00000160, - SQC_PERF_SEL_DCACHE_STALL_INFLIGHT_NONZERO__SI = 0x00000161, - SQC_PERF_SEL_DCACHE_BANKA_STALL_INFLIGHT_NONZERO__SI = 0x00000162, - SQC_PERF_SEL_DCACHE_BANKB_STALL_INFLIGHT_NONZERO__SI = 0x00000163, - SQC_PERF_SEL_DCACHE_BANKC_STALL_INFLIGHT_NONZERO__SI = 0x00000164, - SQC_PERF_SEL_DCACHE_BANKD_STALL_INFLIGHT_NONZERO__SI = 0x00000165, - SQC_PERF_SEL_DCACHE_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x00000166, - SQC_PERF_SEL_DCACHE_BANKA_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x00000167, - SQC_PERF_SEL_DCACHE_BANKB_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x00000168, - SQC_PERF_SEL_DCACHE_BANKC_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x00000169, - SQC_PERF_SEL_DCACHE_BANKD_STALL_INFLIGHT_NONZERO_TAG_AVAIL__SI = 0x0000016a, - SQC_PERF_SEL_DCACHE_STALL_INFLIGHT_MAX__SI = 0x0000016b, - SQC_PERF_SEL_DCACHE_BANKA_STALL_INFLIGHT_MAX__SI = 0x0000016c, - SQC_PERF_SEL_DCACHE_BANKB_STALL_INFLIGHT_MAX__SI = 0x0000016d, - SQC_PERF_SEL_DCACHE_BANKC_STALL_INFLIGHT_MAX__SI = 0x0000016e, - SQC_PERF_SEL_DCACHE_BANKD_STALL_INFLIGHT_MAX__SI = 0x0000016f, - SQC_PERF_SEL_DCACHE_STALL_OUTPUT__SI = 0x00000170, - SQC_PERF_SEL_DCACHE_BANKA_STALL_OUTPUT__SI = 0x00000171, - SQC_PERF_SEL_DCACHE_BANKB_STALL_OUTPUT__SI = 0x00000172, - SQC_PERF_SEL_DCACHE_BANKC_STALL_OUTPUT__SI = 0x00000173, - SQC_PERF_SEL_DCACHE_BANKD_STALL_OUTPUT__SI = 0x00000174, - SQC_PERF_SEL_DCACHE_STALL_OUTPUT_MISS_FIFO__SI = 0x00000175, - SQC_PERF_SEL_DCACHE_BANKA_STALL_OUTPUT_MISS_FIFO__SI = 0x00000176, - SQC_PERF_SEL_DCACHE_BANKB_STALL_OUTPUT_MISS_FIFO__SI = 0x00000177, - SQC_PERF_SEL_DCACHE_BANKC_STALL_OUTPUT_MISS_FIFO__SI = 0x00000178, - SQC_PERF_SEL_DCACHE_BANKD_STALL_OUTPUT_MISS_FIFO__SI = 0x00000179, - SQC_PERF_SEL_DCACHE_STALL_OUTPUT_HIT_FIFO__SI = 0x0000017a, - SQC_PERF_SEL_DCACHE_BANKA_STALL_OUTPUT_HIT_FIFO__SI = 0x0000017b, - SQC_PERF_SEL_DCACHE_BANKB_STALL_OUTPUT_HIT_FIFO__SI = 0x0000017c, - SQC_PERF_SEL_DCACHE_BANKC_STALL_OUTPUT_HIT_FIFO__SI = 0x0000017d, - SQC_PERF_SEL_DCACHE_BANKD_STALL_OUTPUT_HIT_FIFO__SI = 0x0000017e, - SQC_PERF_SEL_DCACHE_STALL_OUTPUT_MISS_TC__SI = 0x0000017f, - SQC_PERF_SEL_DCACHE_BANKA_STALL_OUTPUT_MISS_TC__SI = 0x00000180, - SQC_PERF_SEL_DCACHE_BANKB_STALL_OUTPUT_MISS_TC__SI = 0x00000181, - SQC_PERF_SEL_DCACHE_BANKC_STALL_OUTPUT_MISS_TC__SI = 0x00000182, - SQC_PERF_SEL_DCACHE_BANKD_STALL_OUTPUT_MISS_TC__SI = 0x00000183, - SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB__SI = 0x00000184, - SQC_PERF_SEL_DCACHE_BANKA_STALL_OUTXBAR_ARB__SI = 0x00000185, - SQC_PERF_SEL_DCACHE_BANKB_STALL_OUTXBAR_ARB__SI = 0x00000186, - SQC_PERF_SEL_DCACHE_BANKC_STALL_OUTXBAR_ARB__SI = 0x00000187, - SQC_PERF_SEL_DCACHE_BANKD_STALL_OUTXBAR_ARB__SI = 0x00000188, - SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED__SI = 0x00000189, - SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED__SI = 0x0000018a, - SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED__SI = 0x0000018b, - SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED__SI = 0x0000018c, - SQC_PERF_SEL_ERR_TC_RET_TAG_MISMATCH__SI = 0x0000018d, - SQC_PERF_SEL_PT_POWER_STALL__SI = 0x0000018e, -} SQ_PERF_SEL; - -typedef enum SQ_ROUND_MODE { - SQ_ROUND_NEAREST_EVEN = 0x00000000, - SQ_ROUND_PLUS_INFINITY = 0x00000001, - SQ_ROUND_MINUS_INFINITY = 0x00000002, - SQ_ROUND_TO_ZERO = 0x00000003, -} SQ_ROUND_MODE; - -typedef enum SQ_RSRC_BUF_TYPE { - SQ_RSRC_BUF = 0x00000000, - SQ_RSRC_BUF_RSVD_1 = 0x00000001, - SQ_RSRC_BUF_RSVD_2 = 0x00000002, - SQ_RSRC_BUF_RSVD_3 = 0x00000003, -} SQ_RSRC_BUF_TYPE; - -typedef enum SQ_RSRC_FLAT_TYPE { - SQ_RSRC_FLAT_RSVD_0 = 0x00000000, - SQ_RSRC_FLAT = 0x00000001, - SQ_RSRC_FLAT_RSVD_2 = 0x00000002, - SQ_RSRC_FLAT_RSVD_3 = 0x00000003, -} SQ_RSRC_FLAT_TYPE; - -typedef enum SQ_RSRC_IMG_TYPE { - SQ_RSRC_IMG_RSVD_0 = 0x00000000, - SQ_RSRC_IMG_RSVD_1 = 0x00000001, - SQ_RSRC_IMG_RSVD_2 = 0x00000002, - SQ_RSRC_IMG_RSVD_3 = 0x00000003, - SQ_RSRC_IMG_RSVD_4 = 0x00000004, - SQ_RSRC_IMG_RSVD_5 = 0x00000005, - SQ_RSRC_IMG_RSVD_6 = 0x00000006, - SQ_RSRC_IMG_RSVD_7 = 0x00000007, - SQ_RSRC_IMG_1D = 0x00000008, - SQ_RSRC_IMG_2D = 0x00000009, - SQ_RSRC_IMG_3D = 0x0000000a, - SQ_RSRC_IMG_CUBE = 0x0000000b, - SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, - SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, - SQ_RSRC_IMG_2D_MSAA = 0x0000000e, - SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, -} SQ_RSRC_IMG_TYPE; - -typedef enum SQ_SEL_XYZW01 { - SQ_SEL_0 = 0x00000000, - SQ_SEL_1 = 0x00000001, - SQ_SEL_RESERVED_0 = 0x00000002, - SQ_SEL_RESERVED_1 = 0x00000003, - SQ_SEL_X = 0x00000004, - SQ_SEL_Y = 0x00000005, - SQ_SEL_Z = 0x00000006, - SQ_SEL_W = 0x00000007, -} SQ_SEL_XYZW01; - -typedef enum SQ_TEX_ANISO_RATIO { - SQ_TEX_ANISO_RATIO_1 = 0x00000000, - SQ_TEX_ANISO_RATIO_2 = 0x00000001, - SQ_TEX_ANISO_RATIO_4 = 0x00000002, - SQ_TEX_ANISO_RATIO_8 = 0x00000003, - SQ_TEX_ANISO_RATIO_16 = 0x00000004, -} SQ_TEX_ANISO_RATIO; - -typedef enum SQ_TEX_BORDER_COLOR { - SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, - SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, - SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, - SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, -} SQ_TEX_BORDER_COLOR; - -typedef enum SQ_TEX_CLAMP { - SQ_TEX_WRAP = 0x00000000, - SQ_TEX_MIRROR = 0x00000001, - SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, - SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, - SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, - SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, - SQ_TEX_CLAMP_BORDER = 0x00000006, - SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, -} SQ_TEX_CLAMP; - -typedef enum SQ_TEX_DEPTH_COMPARE { - SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, - SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, - SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, - SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, - SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, - SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, - SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, - SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, -} SQ_TEX_DEPTH_COMPARE; - -typedef enum SQ_TEX_MIP_FILTER { - SQ_TEX_MIP_FILTER_NONE = 0x00000000, - SQ_TEX_MIP_FILTER_POINT = 0x00000001, - SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, - SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ__VI = 0x00000003, -} SQ_TEX_MIP_FILTER; - -typedef enum SQ_TEX_XY_FILTER { - SQ_TEX_XY_FILTER_POINT = 0x00000000, - SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, - SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, - SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, -} SQ_TEX_XY_FILTER; - -typedef enum SQ_TEX_Z_FILTER { - SQ_TEX_Z_FILTER_NONE = 0x00000000, - SQ_TEX_Z_FILTER_POINT = 0x00000001, - SQ_TEX_Z_FILTER_LINEAR = 0x00000002, -} SQ_TEX_Z_FILTER; - -typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { - SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000, - SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001, - SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002, -} SQ_THREAD_TRACE_CAPTURE_MODE; - -typedef enum SQ_THREAD_TRACE_INST_TYPE { - SQ_THREAD_TRACE_INST_TYPE_SMEM__SI__CI = 0x00000000, - SQ_THREAD_TRACE_INST_TYPE_SMEM_RD__VI = 0x00000000, - SQ_THREAD_TRACE_INST_TYPE_SALU__SI__CI = 0x00000001, - SQ_THREAD_TRACE_INST_TYPE_SALU_32__VI = 0x00000001, - SQ_THREAD_TRACE_INST_TYPE_VMEM_RA__SI = 0x00000002, - SQ_THREAD_TRACE_INST_TYPE_VMEM_RD__CI__VI = 0x00000002, - SQ_THREAD_TRACE_INST_TYPE_VMEM_WA__SI = 0x00000003, - SQ_THREAD_TRACE_INST_TYPE_VMEM_WR__CI__VI = 0x00000003, - SQ_THREAD_TRACE_INST_TYPE_VMEM_WD__SI = 0x00000004, - SQ_THREAD_TRACE_INST_TYPE_FLAT_WR__CI__VI = 0x00000004, - SQ_THREAD_TRACE_INST_TYPE_VALU__SI__CI = 0x00000005, - SQ_THREAD_TRACE_INST_TYPE_VALU_32__VI = 0x00000005, - SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006, - SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007, - SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008, - SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009, - SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a, - SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b, - SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c, - SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d, - SQ_THREAD_TRACE_INST_TYPE_GEOM__SI = 0x0000000e, - SQ_THREAD_TRACE_INST_TYPE_FLAT_RD__CI__VI = 0x0000000e, - SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f, - SQ_THREAD_TRACE_INST_TYPE_SMEM_WR__VI = 0x00000010, - SQ_THREAD_TRACE_INST_TYPE_SALU_64__VI = 0x00000011, - SQ_THREAD_TRACE_INST_TYPE_VALU_64__VI = 0x00000012, - SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY__VI = 0x00000013, - SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY__VI = 0x00000014, - SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY__VI = 0x00000015, - SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY__VI = 0x00000016, - SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY__VI = 0x00000017, - SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY__VI = 0x00000018, -} SQ_THREAD_TRACE_INST_TYPE; - -typedef enum SQ_THREAD_TRACE_ISSUE { - SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000, - SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001, - SQ_THREAD_TRACE_ISSUE_INST = 0x00000002, - SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003, -} SQ_THREAD_TRACE_ISSUE; - -typedef enum SQ_THREAD_TRACE_ISSUE_MASK { - SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000, - SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001, - SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002, - SQ_THREAD_TRACE_ISSUE_MASK_IMMED__CI__VI = 0x00000003, -} SQ_THREAD_TRACE_ISSUE_MASK; - -typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { - SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC__SI = 0x00000000, - SQ_THREAD_TRACE_MISC_TOKEN_TIME__CI__VI = 0x00000000, - SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN__SI = 0x00000001, - SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET__CI__VI = 0x00000001, - SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END__SI = 0x00000002, - SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST__CI__VI = 0x00000002, - SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC__CI__VI = 0x00000003, - SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN__CI__VI = 0x00000004, - SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END__CI__VI = 0x00000005, - SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX__VI = 0x00000006, - SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN__VI = 0x00000007, -} SQ_THREAD_TRACE_MISC_TOKEN_TYPE; - -typedef enum SQ_THREAD_TRACE_MODE_SEL { - SQ_THREAD_TRACE_MODE_OFF = 0x00000000, - SQ_THREAD_TRACE_MODE_ON = 0x00000001, - SQ_THREAD_TRACE_MODE_RANDOM__SI__CI = 0x00000002, -} SQ_THREAD_TRACE_MODE_SEL; - -typedef enum SQ_THREAD_TRACE_REG_OP { - SQ_THREAD_TRACE_REG_OP_READ = 0x00000000, - SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001, -} SQ_THREAD_TRACE_REG_OP; - -typedef enum SQ_THREAD_TRACE_REG_TYPE { - SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000, - SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001, - SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002, - SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003, - SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004, - SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005, - SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006, - SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007, -} SQ_THREAD_TRACE_REG_TYPE; - -typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { - SQ_THREAD_TRACE_TOKEN_TIME__SI = 0x00000000, - SQ_THREAD_TRACE_TOKEN_MISC__CI__VI = 0x00000000, - SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001, - SQ_THREAD_TRACE_TOKEN_REG = 0x00000002, - SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003, - SQ_THREAD_TRACE_TOKEN_WAVE_PS_ALLOC__SI = 0x00000004, - SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC__CI__VI = 0x00000004, - SQ_THREAD_TRACE_TOKEN_WAVE_VS_ALLOC__SI = 0x00000005, - SQ_THREAD_TRACE_TOKEN_REG_CSPRIV__CI__VI = 0x00000005, - SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006, - SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007, - SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008, - SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009, - SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a, - SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b, - SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c, - SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d, - SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e, - SQ_THREAD_TRACE_TOKEN_MISC__SI = 0x0000000f, - SQ_THREAD_TRACE_TOKEN_REG_CS__CI__VI = 0x0000000f, -} SQ_THREAD_TRACE_TOKEN_TYPE; - -typedef enum SQ_THREAD_TRACE_VM_ID_MASK { - SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000, - SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001, - SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002, -} SQ_THREAD_TRACE_VM_ID_MASK; - -typedef enum SQ_THREAD_TRACE_WAVE_MASK { - SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000, - SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001, - SQ_THREAD_TRACE_WAVE_MASK_1_2__SI__CI = 0x00000002, - SQ_THREAD_TRACE_WAVE_MASK_1_4__SI__CI = 0x00000003, - SQ_THREAD_TRACE_WAVE_MASK_1_8__SI__CI = 0x00000004, - SQ_THREAD_TRACE_WAVE_MASK_1_16__SI__CI = 0x00000005, - SQ_THREAD_TRACE_WAVE_MASK_1_32__SI__CI = 0x00000006, - SQ_THREAD_TRACE_WAVE_MASK_1_64__SI__CI = 0x00000007, -} SQ_THREAD_TRACE_WAVE_MASK; - -typedef enum SQ_WAVE_IB_ECC_ST { - SQ_WAVE_IB_ECC_CLEAN = 0x00000000, - SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, - SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, - SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, -} SQ_WAVE_IB_ECC_ST; - -typedef enum SQ_WAVE_TYPE { - SQ_WAVE_TYPE_PS = 0x00000000, - SQ_WAVE_TYPE_VS = 0x00000001, - SQ_WAVE_TYPE_GS = 0x00000002, - SQ_WAVE_TYPE_ES = 0x00000003, - SQ_WAVE_TYPE_HS = 0x00000004, - SQ_WAVE_TYPE_LS = 0x00000005, - SQ_WAVE_TYPE_CS = 0x00000006, - SQ_WAVE_TYPE_PS1 = 0x00000007, -} SQ_WAVE_TYPE; - -typedef enum SRBM_PERFCOUNT1_SEL { - SRBM_PERF_SEL_COUNT = 0x00000000, - SRBM_PERF_SEL_BIF_BUSY = 0x00000001, - SRBM_PERF_SEL_DRM_BUSY = 0x00000002, - SRBM_PERF_SEL_DRMDMA0_BUSY__SI = 0x00000003, - SRBM_PERF_SEL_SDMA0_BUSY__CI__VI = 0x00000003, - SRBM_PERF_SEL_IH_BUSY = 0x00000004, - SRBM_PERF_SEL_MCB_BUSY = 0x00000005, - SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x00000006, - SRBM_PERF_SEL_MCC_BUSY = 0x00000007, - SRBM_PERF_SEL_MCD_BUSY = 0x00000008, - SRBM_PERF_SEL_RESERVED0_BUSY__SI = 0x00000009, - SRBM_PERF_SEL_CHUB_BUSY__CI__VI = 0x00000009, - SRBM_PERF_SEL_SEM_BUSY = 0x0000000a, - SRBM_PERF_SEL_UVD_BUSY = 0x0000000b, - SRBM_PERF_SEL_VMC_BUSY = 0x0000000c, - SRBM_PERF_SEL_XSP_BUSY__SI__CI = 0x0000000d, - SRBM_PERF_SEL_ODE_BUSY__VI = 0x0000000d, - SRBM_PERF_SEL_DRMDMA1_BUSY__SI = 0x0000000e, - SRBM_PERF_SEL_SDMA1_BUSY__CI__VI = 0x0000000e, - SRBM_PERF_SEL_RESERVED1_BUSY__SI = 0x0000000f, - SRBM_PERF_SEL_SAM_BUSY__CI = 0x0000000f, - SRBM_PERF_SEL_SAMMSP_BUSY__VI = 0x0000000f, - SRBM_PERF_SEL_VCE_BUSY__SI__CI = 0x00000010, - SRBM_PERF_SEL_VCE0_BUSY__VI = 0x00000010, - SRBM_PERF_SEL_XDMA_BUSY = 0x00000011, - SRBM_PERF_SEL_ACP_BUSY__CI__VI = 0x00000012, - SRBM_PERF_SEL_SDMA2_BUSY__VI = 0x00000013, - SRBM_PERF_SEL_SDMA3_BUSY__VI = 0x00000014, - SRBM_PERF_SEL_SAMSCP_BUSY__VI = 0x00000015, - SRBM_PERF_SEL_VMC1_BUSY__VI = 0x00000016, - SRBM_PERF_SEL_ISP_BUSY__VI = 0x00000017, - SRBM_PERF_SEL_VCE1_BUSY__VI = 0x00000018, - SRBM_PERF_SEL_GCATCL2_BUSY__VI = 0x00000019, - SRBM_PERF_SEL_OSATCL2_BUSY__VI = 0x0000001a, - SRBM_PERF_SEL_VP8_BUSY__VI = 0x0000001b, -} SRBM_PERFCOUNT1_SEL; - -typedef enum SU_PERFCNT_SEL { - PERF_PAPC_PASX_REQ = 0x00000000, - PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, - PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, - PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, - PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, - PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, - PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, - PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, - PERF_PAPC_PA_INPUT_PRIM = 0x00000008, - PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, - PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, - PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, - PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, - PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, - PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, - PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, - PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, - PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, - PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, - PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, - PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, - PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, - PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, - PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, - PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, - PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, - PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, - PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, - PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, - PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, - PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, - PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, - PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, - PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, - PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, - PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, - PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, - PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, - PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, - PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, - PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, - PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, - PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, - PERF_PAPC_SU_INPUT_PRIM = 0x00000031, - PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, - PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, - PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, - PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, - PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, - PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, - PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, - PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, - PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, - PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, - PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, - PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, - PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, - PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, - PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, - PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, - PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, - PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, - PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, - PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, - PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, - PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, - PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, - PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, - PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, - PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, - PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, - PERF_PAPC_PASX_REC_IDLE = 0x00000050, - PERF_PAPC_PASX_REC_BUSY = 0x00000051, - PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, - PERF_PAPC_PASX_REC_STALLED = 0x00000053, - PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, - PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, - PERF_PAPC_CCGSM_IDLE = 0x00000056, - PERF_PAPC_CCGSM_BUSY = 0x00000057, - PERF_PAPC_CCGSM_STALLED = 0x00000058, - PERF_PAPC_CLPRIM_IDLE = 0x00000059, - PERF_PAPC_CLPRIM_BUSY = 0x0000005a, - PERF_PAPC_CLPRIM_STALLED = 0x0000005b, - PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, - PERF_PAPC_CLIPSM_IDLE = 0x0000005d, - PERF_PAPC_CLIPSM_BUSY = 0x0000005e, - PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, - PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, - PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, - PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, - PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, - PERF_PAPC_CLIPGA_IDLE = 0x00000064, - PERF_PAPC_CLIPGA_BUSY = 0x00000065, - PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, - PERF_PAPC_CLIPGA_STALLED = 0x00000067, - PERF_PAPC_CLIP_IDLE = 0x00000068, - PERF_PAPC_CLIP_BUSY = 0x00000069, - PERF_PAPC_SU_IDLE = 0x0000006a, - PERF_PAPC_SU_BUSY = 0x0000006b, - PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, - PERF_PAPC_SU_STALLED_SC = 0x0000006d, - PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, - PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, - PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, - PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, - PERF_PAPC_PASX_SE0_REQ = 0x00000072, - PERF_PAPC_PASX_SE1_REQ = 0x00000073, - PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, - PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, - PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, - PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, - PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, - PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, - PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, - PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, - PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, - PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, - PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, - PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, - PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, - PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, - PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, - PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, - PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, - PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, - PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, - PERF_PAPC_SU_CULLED_PRIM = 0x00000087, - PERF_PAPC_SU_OUTPUT_EOPG__CI__VI = 0x00000088, - PERF_PAPC_SU_SE2_PRIM_FILTER_CULL__CI__VI = 0x00000089, - PERF_PAPC_SU_SE3_PRIM_FILTER_CULL__CI__VI = 0x0000008a, - PERF_PAPC_SU_SE2_OUTPUT_PRIM__CI__VI = 0x0000008b, - PERF_PAPC_SU_SE3_OUTPUT_PRIM__CI__VI = 0x0000008c, - PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM__CI__VI = 0x0000008d, - PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM__CI__VI = 0x0000008e, - PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET__CI__VI = 0x0000008f, - PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET__CI__VI = 0x00000090, - PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET__CI__VI = 0x00000091, - PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET__CI__VI = 0x00000092, - PERF_PAPC_SU_SE0_OUTPUT_EOPG__CI__VI = 0x00000093, - PERF_PAPC_SU_SE1_OUTPUT_EOPG__CI__VI = 0x00000094, - PERF_PAPC_SU_SE2_OUTPUT_EOPG__CI__VI = 0x00000095, - PERF_PAPC_SU_SE3_OUTPUT_EOPG__CI__VI = 0x00000096, - PERF_PAPC_SU_SE2_STALLED_SC__CI__VI = 0x00000097, - PERF_PAPC_SU_SE3_STALLED_SC__CI__VI = 0x00000098, -} SU_PERFCNT_SEL; - -typedef enum SX_PERFCOUNT_SELECT { - SX_PERF_SEL_PA_IDLE_CYCLES = 0, - SX_PERF_SEL_PA_REQ = 1, - SX_PERF_SEL_PA_POS = 2, - SX_PERF_SEL_CLOCK = 3, - SX_PERF_SEL_GATE_EN1 = 4, - SX_PERF_SEL_GATE_EN2 = 5, - SX_PERF_SEL_GATE_EN3 = 6, - SX_PERF_SEL_GATE_EN4 = 7, - SX_PERF_SEL_SH_POS_STARVE = 8, - SX_PERF_SEL_SH_COLOR_STARVE = 9, - SX_PERF_SEL_SH_POS_STALL = 10, - SX_PERF_SEL_SH_COLOR_STALL = 11, - SX_PERF_SEL_DB0_PIXELS = 12, - SX_PERF_SEL_DB0_HALF_QUADS = 13, - SX_PERF_SEL_DB0_PIXEL_STALL = 14, - SX_PERF_SEL_DB0_PIXEL_IDLE = 15, - SX_PERF_SEL_DB0_PRED_PIXELS = 16, - SX_PERF_SEL_DB1_PIXELS = 17, - SX_PERF_SEL_DB1_HALF_QUADS = 18, - SX_PERF_SEL_DB1_PIXEL_STALL = 19, - SX_PERF_SEL_DB1_PIXEL_IDLE = 20, - SX_PERF_SEL_DB1_PRED_PIXELS = 21, - SX_PERF_SEL_DB2_PIXELS = 22, - SX_PERF_SEL_DB2_HALF_QUADS = 23, - SX_PERF_SEL_DB2_PIXEL_STALL = 24, - SX_PERF_SEL_DB2_PIXEL_IDLE = 25, - SX_PERF_SEL_DB2_PRED_PIXELS = 26, - SX_PERF_SEL_DB3_PIXELS = 27, - SX_PERF_SEL_DB3_HALF_QUADS = 28, - SX_PERF_SEL_DB3_PIXEL_STALL = 29, - SX_PERF_SEL_DB3_PIXEL_IDLE = 30, - SX_PERF_SEL_DB3_PRED_PIXELS = 31, - SX_PERF_SEL_COL_BUSY__CI__VI = 32, - SX_PERF_SEL_POS_BUSY__CI__VI = 33, -} SX_PERFCOUNT_SELECT; - -typedef enum SampleSplit { - ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000, - ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001, - ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002, - ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003, -} SampleSplit; - -typedef enum SampleSplitBytes { - CONFIG_1KB_SPLIT = 0x00000000, - CONFIG_2KB_SPLIT = 0x00000001, - CONFIG_4KB_SPLIT = 0x00000002, - CONFIG_8KB_SPLIT = 0x00000003, -} SampleSplitBytes; - -typedef enum ScMap { - RASTER_CONFIG_SC_MAP_0 = 0x00000000, - RASTER_CONFIG_SC_MAP_1 = 0x00000001, - RASTER_CONFIG_SC_MAP_2 = 0x00000002, - RASTER_CONFIG_SC_MAP_3 = 0x00000003, -} ScMap; - -typedef enum ScXsel { - RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, -} ScXsel; - -typedef enum ScYsel { - RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, -} ScYsel; - -typedef enum SeMap { - RASTER_CONFIG_SE_MAP_0 = 0x00000000, - RASTER_CONFIG_SE_MAP_1 = 0x00000001, - RASTER_CONFIG_SE_MAP_2 = 0x00000002, - RASTER_CONFIG_SE_MAP_3 = 0x00000003, -} SeMap; - -typedef enum SePairMap { - RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, - RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, - RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, - RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, -} SePairMap; - -typedef enum SePairXsel { - RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, -} SePairXsel; - -typedef enum SePairYsel { - RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, -} SePairYsel; - -typedef enum SeXsel { - RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, -} SeXsel; - -typedef enum SeYsel { - RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, -} SeYsel; - -typedef enum ShaderEngineTileSize { - ADDR_CONFIG_SE_TILE_16 = 0x00000000, - ADDR_CONFIG_SE_TILE_32 = 0x00000001, -} ShaderEngineTileSize; - -typedef enum SourceFormat { - EXPORT_4C_32BPC = 0x00000000, - EXPORT_4C_16BPC = 0x00000001, - EXPORT_2C_32BPC_GR = 0x00000002, - EXPORT_2C_32BPC_AR = 0x00000003, -} SourceFormat; - -typedef enum StencilFormat { - STENCIL_INVALID = 0x00000000, - STENCIL_8 = 0x00000001, -} StencilFormat; - -typedef enum StencilOp { - STENCIL_KEEP = 0x00000000, - STENCIL_ZERO = 0x00000001, - STENCIL_ONES = 0x00000002, - STENCIL_REPLACE_TEST = 0x00000003, - STENCIL_REPLACE_OP = 0x00000004, - STENCIL_ADD_CLAMP = 0x00000005, - STENCIL_SUB_CLAMP = 0x00000006, - STENCIL_INVERT = 0x00000007, - STENCIL_ADD_WRAP = 0x00000008, - STENCIL_SUB_WRAP = 0x00000009, - STENCIL_AND = 0x0000000a, - STENCIL_OR = 0x0000000b, - STENCIL_XOR = 0x0000000c, - STENCIL_NAND = 0x0000000d, - STENCIL_NOR = 0x0000000e, - STENCIL_XNOR = 0x0000000f, -} StencilOp; - -typedef enum SurfaceArray { - ARRAY_1D = 0x00000000, - ARRAY_2D = 0x00000001, - ARRAY_3D = 0x00000002, - ARRAY_3D_SLICE = 0x00000003, -} SurfaceArray; - -typedef enum SurfaceEndian { - ENDIAN_NONE = 0x00000000, - ENDIAN_8IN16 = 0x00000001, - ENDIAN_8IN32 = 0x00000002, - ENDIAN_8IN64 = 0x00000003, -} SurfaceEndian; - -typedef enum SurfaceFormat { - FMT_INVALID = 0x00000000, - FMT_8 = 0x00000001, - FMT_16 = 0x00000002, - FMT_8_8 = 0x00000003, - FMT_32 = 0x00000004, - FMT_16_16 = 0x00000005, - FMT_10_11_11 = 0x00000006, - FMT_11_11_10 = 0x00000007, - FMT_10_10_10_2 = 0x00000008, - FMT_2_10_10_10 = 0x00000009, - FMT_8_8_8_8 = 0x0000000a, - FMT_32_32 = 0x0000000b, - FMT_16_16_16_16 = 0x0000000c, - FMT_32_32_32 = 0x0000000d, - FMT_32_32_32_32 = 0x0000000e, - FMT_RESERVED_4 = 0x0000000f, - FMT_5_6_5 = 0x00000010, - FMT_1_5_5_5 = 0x00000011, - FMT_5_5_5_1 = 0x00000012, - FMT_4_4_4_4 = 0x00000013, - FMT_8_24 = 0x00000014, - FMT_24_8 = 0x00000015, - FMT_X24_8_32_FLOAT = 0x00000016, - FMT_RESERVED_33 = 0x00000017, - FMT_11_11_10_FLOAT = 0x00000018, - FMT_16_FLOAT = 0x00000019, - FMT_32_FLOAT = 0x0000001a, - FMT_16_16_FLOAT = 0x0000001b, - FMT_8_24_FLOAT = 0x0000001c, - FMT_24_8_FLOAT = 0x0000001d, - FMT_32_32_FLOAT = 0x0000001e, - FMT_10_11_11_FLOAT = 0x0000001f, - FMT_16_16_16_16_FLOAT = 0x00000020, - FMT_3_3_2 = 0x00000021, - FMT_6_5_5 = 0x00000022, - FMT_32_32_32_32_FLOAT = 0x00000023, - FMT_RESERVED_36 = 0x00000024, - FMT_1 = 0x00000025, - FMT_1_REVERSED = 0x00000026, - FMT_GB_GR = 0x00000027, - FMT_BG_RG = 0x00000028, - FMT_32_AS_8 = 0x00000029, - FMT_32_AS_8_8 = 0x0000002a, - FMT_5_9_9_9_SHAREDEXP = 0x0000002b, - FMT_8_8_8 = 0x0000002c, - FMT_16_16_16 = 0x0000002d, - FMT_16_16_16_FLOAT = 0x0000002e, - FMT_4_4 = 0x0000002f, - FMT_32_32_32_FLOAT = 0x00000030, - FMT_BC1 = 0x00000031, - FMT_BC2 = 0x00000032, - FMT_BC3 = 0x00000033, - FMT_BC4 = 0x00000034, - FMT_BC5 = 0x00000035, - FMT_BC6 = 0x00000036, - FMT_BC7 = 0x00000037, - FMT_32_AS_32_32_32_32 = 0x00000038, - FMT_APC3 = 0x00000039, - FMT_APC4 = 0x0000003a, - FMT_APC5 = 0x0000003b, - FMT_APC6 = 0x0000003c, - FMT_APC7 = 0x0000003d, - FMT_CTX1 = 0x0000003e, - FMT_RESERVED_63 = 0x0000003f, -} SurfaceFormat; - -typedef enum SurfaceNumber { - NUMBER_UNORM = 0x00000000, - NUMBER_SNORM = 0x00000001, - NUMBER_USCALED = 0x00000002, - NUMBER_SSCALED = 0x00000003, - NUMBER_UINT = 0x00000004, - NUMBER_SINT = 0x00000005, - NUMBER_SRGB = 0x00000006, - NUMBER_FLOAT = 0x00000007, -} SurfaceNumber; - -typedef enum SurfaceSwap { - SWAP_STD = 0x00000000, - SWAP_ALT = 0x00000001, - SWAP_STD_REV = 0x00000002, - SWAP_ALT_REV = 0x00000003, -} SurfaceSwap; - -typedef enum SurfaceTiling { - ARRAY_LINEAR = 0x00000000, - ARRAY_TILED = 0x00000001, -} SurfaceTiling; - -typedef enum TA_PERFCOUNT_SEL { - TA_PERF_SEL_ta_busy__SI__CI = 0x00000000, - TA_PERF_SEL_NULL__VI = 0x00000000, - TA_PERF_SEL_sh_fifo_busy = 0x00000001, - TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002, - TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003, - TA_PERF_SEL_sh_fifo_data_busy = 0x00000004, - TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005, - TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006, - TA_PERF_SEL_gradient_busy = 0x00000007, - TA_PERF_SEL_gradient_fifo_busy = 0x00000008, - TA_PERF_SEL_lod_busy = 0x00000009, - TA_PERF_SEL_lod_fifo_busy = 0x0000000a, - TA_PERF_SEL_addresser_busy = 0x0000000b, - TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, - TA_PERF_SEL_aligner_busy = 0x0000000d, - TA_PERF_SEL_write_path_busy = 0x0000000e, - TA_PERF_SEL_RESERVED_15__SI__CI = 0x0000000f, - TA_PERF_SEL_ta_busy__VI = 0x0000000f, - TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010, - TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011, - TA_PERF_SEL_sp_ta_data_cycles = 0x00000012, - TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013, - TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014, - TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015, - TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016, - TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017, - TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018, - TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019, - TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a, - TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b, - TA_PERF_SEL_RESERVED_28 = 0x0000001c, - TA_PERF_SEL_RESERVED_29 = 0x0000001d, - TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e, - TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f, - TA_PERF_SEL_total_wavefronts = 0x00000020, - TA_PERF_SEL_gradient_cycles = 0x00000021, - TA_PERF_SEL_walker_cycles = 0x00000022, - TA_PERF_SEL_aligner_cycles = 0x00000023, - TA_PERF_SEL_image_wavefronts = 0x00000024, - TA_PERF_SEL_image_read_wavefronts = 0x00000025, - TA_PERF_SEL_image_write_wavefronts = 0x00000026, - TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, - TA_PERF_SEL_image_total_cycles = 0x00000028, - TA_PERF_SEL_RESERVED_41 = 0x00000029, - TA_PERF_SEL_RESERVED_42 = 0x0000002a, - TA_PERF_SEL_RESERVED_43 = 0x0000002b, - TA_PERF_SEL_buffer_wavefronts = 0x0000002c, - TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d, - TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e, - TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, - TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030, - TA_PERF_SEL_buffer_total_cycles = 0x00000031, - TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032, - TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033, - TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034, - TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035, - TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, - TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, - TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038, - TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, - TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, - TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, - TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, - TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, - TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, - TA_PERF_SEL_RESERVED_63__SI = 0x0000003f, - TA_PERF_SEL_aniso_gt1_cycle_quads__CI__VI = 0x0000003f, - TA_PERF_SEL_color_1_cycle_pixels = 0x00000040, - TA_PERF_SEL_color_2_cycle_pixels = 0x00000041, - TA_PERF_SEL_color_3_cycle_pixels = 0x00000042, - TA_PERF_SEL_color_4_cycle_pixels = 0x00000043, - TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044, - TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045, - TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046, - TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047, - TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048, - TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, - TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, - TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, - TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, - TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, - TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, - TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, - TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, - TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, - TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, - TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, - TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, - TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, - TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, - TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, - TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, - TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, - TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, - TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, - TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, - TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, - TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, - TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, - TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, - TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, - TA_PERF_SEL_write_path_input_cycles = 0x00000062, - TA_PERF_SEL_write_path_output_cycles = 0x00000063, - TA_PERF_SEL_reg_sclk_vld__SI = 0x00000064, - TA_PERF_SEL_flat_wavefronts__CI__VI = 0x00000064, - TA_PERF_SEL_local_cg_dyn_sclk_grp0_en__SI = 0x00000065, - TA_PERF_SEL_flat_read_wavefronts__CI__VI = 0x00000065, - TA_PERF_SEL_local_cg_dyn_sclk_grp1_en__SI = 0x00000066, - TA_PERF_SEL_flat_write_wavefronts__CI__VI = 0x00000066, - TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en__SI = 0x00000067, - TA_PERF_SEL_flat_atomic_wavefronts__CI__VI = 0x00000067, - TA_PERF_SEL_local_cg_dyn_sclk_grp4_en__SI = 0x00000068, - TA_PERF_SEL_flat_coalesceable_wavefronts__CI__VI = 0x00000068, - TA_PERF_SEL_local_cg_dyn_sclk_grp5_en__SI = 0x00000069, - TA_PERF_SEL_reg_sclk_vld__CI__VI = 0x00000069, - TA_PERF_SEL_local_cg_dyn_sclk_grp0_en__CI__VI = 0x0000006a, - TA_PERF_SEL_local_cg_dyn_sclk_grp1_en__CI__VI = 0x0000006b, - TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en__CI__VI = 0x0000006c, - TA_PERF_SEL_local_cg_dyn_sclk_grp4_en__CI__VI = 0x0000006d, - TA_PERF_SEL_local_cg_dyn_sclk_grp5_en__CI__VI = 0x0000006e, - TA_PERF_SEL_xnack_on_phase0__VI = 0x0000006f, - TA_PERF_SEL_xnack_on_phase1__VI = 0x00000070, - TA_PERF_SEL_xnack_on_phase2__VI = 0x00000071, - TA_PERF_SEL_xnack_on_phase3__VI = 0x00000072, - TA_PERF_SEL_first_xnack_on_phase0__VI = 0x00000073, - TA_PERF_SEL_first_xnack_on_phase1__VI = 0x00000074, - TA_PERF_SEL_first_xnack_on_phase2__VI = 0x00000075, - TA_PERF_SEL_first_xnack_on_phase3__VI = 0x00000076, -} TA_PERFCOUNT_SEL; - -typedef enum TA_TC_ADDR_MODES { - TA_TC_ADDR_MODE_DEFAULT = 0x00000000, - TA_TC_ADDR_MODE_COMP0 = 0x00000001, - TA_TC_ADDR_MODE_COMP1 = 0x00000002, - TA_TC_ADDR_MODE_COMP2 = 0x00000003, - TA_TC_ADDR_MODE_COMP3 = 0x00000004, - TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, - TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, -} TA_TC_ADDR_MODES; - -typedef enum TCA_PERF_SEL { - TCA_PERF_SEL_NONE = 0x00000000, - TCA_PERF_SEL_CYCLE = 0x00000001, - TCA_PERF_SEL_BUSY = 0x00000002, - TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003, - TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004, - TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005, - TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006, - TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007, - TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008, - TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009, - TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a, - TCA_PERF_SEL_REQ_TCC0 = 0x0000000b, - TCA_PERF_SEL_REQ_TCC1 = 0x0000000c, - TCA_PERF_SEL_REQ_TCC2 = 0x0000000d, - TCA_PERF_SEL_REQ_TCC3 = 0x0000000e, - TCA_PERF_SEL_REQ_TCC4 = 0x0000000f, - TCA_PERF_SEL_REQ_TCC5 = 0x00000010, - TCA_PERF_SEL_REQ_TCC6 = 0x00000011, - TCA_PERF_SEL_REQ_TCC7 = 0x00000012, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a, - TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b, - TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c, - TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d, - TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e, - TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f, - TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020, - TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021, - TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022, - TCA_PERF_SEL_FORCED_HOLE_TCS__CI = 0x00000023, - TCA_PERF_SEL_REQ_TCS__CI = 0x00000024, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS__CI = 0x00000025, - TCA_PERF_SEL_CROSSBAR_STALL_TCS__CI = 0x00000026, -} TCA_PERF_SEL; - -typedef enum TCC_CACHE_POLICIES { - TCC_CACHE_POLICY_LRU = 0x00000000, - TCC_CACHE_POLICY_STREAM = 0x00000001, - TCC_CACHE_POLICY_BYPASS__SI__CI = 0x00000002, -} TCC_CACHE_POLICIES; - -typedef enum TCC_PERF_SEL { - TCC_PERF_SEL_NONE = 0x00000000, - TCC_PERF_SEL_CYCLE = 0x00000001, - TCC_PERF_SEL_BUSY = 0x00000002, - TCC_PERF_SEL_REQ = 0x00000003, - TCC_PERF_SEL_STREAMING_REQ = 0x00000004, - TCC_PERF_SEL_READ__SI__CI = 0x00000005, - TCC_PERF_SEL_EXE_REQ__VI = 0x00000005, - TCC_PERF_SEL_WRITE__SI__CI = 0x00000006, - TCC_PERF_SEL_COMPRESSED_REQ__VI = 0x00000006, - TCC_PERF_SEL_ATOMIC__SI__CI = 0x00000007, - TCC_PERF_SEL_COMPRESSED_0_REQ__VI = 0x00000007, - TCC_PERF_SEL_WBINVL2__SI__CI = 0x00000008, - TCC_PERF_SEL_METADATA_REQ__VI = 0x00000008, - TCC_PERF_SEL_WBINVL2_CYCLE__SI__CI = 0x00000009, - TCC_PERF_SEL_NC_VIRTUAL_REQ__VI = 0x00000009, - TCC_PERF_SEL_HIT__SI__CI = 0x0000000a, - TCC_PERF_SEL_NC_PHYSICAL_REQ__VI = 0x0000000a, - TCC_PERF_SEL_MISS__SI__CI = 0x0000000b, - TCC_PERF_SEL_UC_VIRTUAL_REQ__VI = 0x0000000b, - TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT__SI__CI = 0x0000000c, - TCC_PERF_SEL_UC_PHYSICAL_REQ__VI = 0x0000000c, - TCC_PERF_SEL_FULLY_WRITTEN_HIT__SI__CI = 0x0000000d, - TCC_PERF_SEL_CC_PHYSICAL_REQ__VI = 0x0000000d, - TCC_PERF_SEL_WRITEBACK__SI__CI = 0x0000000e, - TCC_PERF_SEL_PROBE__VI = 0x0000000e, - TCC_PERF_SEL_LATENCY_FIFO_FULL__SI__CI = 0x0000000f, - TCC_PERF_SEL_READ__VI = 0x0000000f, - TCC_PERF_SEL_SRC_FIFO_FULL__SI__CI = 0x00000010, - TCC_PERF_SEL_WRITE__VI = 0x00000010, - TCC_PERF_SEL_HOLE_FIFO_FULL__SI__CI = 0x00000011, - TCC_PERF_SEL_ATOMIC__VI = 0x00000011, - TCC_PERF_SEL_MC_WRREQ__SI__CI = 0x00000012, - TCC_PERF_SEL_HIT__VI = 0x00000012, - TCC_PERF_SEL_MC_WRREQ_STALL__SI__CI = 0x00000013, - TCC_PERF_SEL_MISS__VI = 0x00000013, - TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL__SI__CI = 0x00000014, - TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT__VI = 0x00000014, - TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL__SI__CI = 0x00000015, - TCC_PERF_SEL_FULLY_WRITTEN_HIT__VI = 0x00000015, - TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL__SI__CI = 0x00000016, - TCC_PERF_SEL_WRITEBACK__VI = 0x00000016, - TCC_PERF_SEL_MC_WRREQ_LEVEL__SI__CI = 0x00000017, - TCC_PERF_SEL_LATENCY_FIFO_FULL__VI = 0x00000017, - TCC_PERF_SEL_MC_RDREQ__SI__CI = 0x00000018, - TCC_PERF_SEL_SRC_FIFO_FULL__VI = 0x00000018, - TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL__SI__CI = 0x00000019, - TCC_PERF_SEL_HOLE_FIFO_FULL__VI = 0x00000019, - TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL__SI__CI = 0x0000001a, - TCC_PERF_SEL_MC_WRREQ__VI = 0x0000001a, - TCC_PERF_SEL_MC_RDREQ_LEVEL__SI__CI = 0x0000001b, - TCC_PERF_SEL_MC_WRREQ_UNCACHED__VI = 0x0000001b, - TCC_PERF_SEL_TAG_STALL__SI__CI = 0x0000001c, - TCC_PERF_SEL_MC_WRREQ_STALL__VI = 0x0000001c, - TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL__SI__CI = 0x0000001d, - TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL__VI = 0x0000001d, - TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL__SI__CI = 0x0000001e, - TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL__VI = 0x0000001e, - TCC_PERF_SEL_READ_RETURN_TIMEOUT__SI__CI = 0x0000001f, - TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL__VI = 0x0000001f, - TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT__SI__CI = 0x00000020, - TCC_PERF_SEL_MC_WRREQ_LEVEL__VI = 0x00000020, - TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE__SI__CI = 0x00000021, - TCC_PERF_SEL_MC_ATOMIC__VI = 0x00000021, - TCC_PERF_SEL_BUBBLE__SI__CI = 0x00000022, - TCC_PERF_SEL_MC_ATOMIC_LEVEL__VI = 0x00000022, - TCC_PERF_SEL_RETURN_ACK__SI__CI = 0x00000023, - TCC_PERF_SEL_MC_RDREQ__VI = 0x00000023, - TCC_PERF_SEL_RETURN_DATA__SI__CI = 0x00000024, - TCC_PERF_SEL_MC_RDREQ_UNCACHED__VI = 0x00000024, - TCC_PERF_SEL_RETURN_HOLE__SI__CI = 0x00000025, - TCC_PERF_SEL_MC_RDREQ_MDC__VI = 0x00000025, - TCC_PERF_SEL_RETURN_ACK_HOLE__SI__CI = 0x00000026, - TCC_PERF_SEL_MC_RDREQ_COMPRESSED__VI = 0x00000026, - TCC_PERF_SEL_IB_STALL__SI__CI = 0x00000027, - TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL__VI = 0x00000027, - TCC_PERF_SEL_TCA_LEVEL__SI__CI = 0x00000028, - TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL__VI = 0x00000028, - TCC_PERF_SEL_HOLE_LEVEL__SI__CI = 0x00000029, - TCC_PERF_SEL_MC_RDREQ_LEVEL__VI = 0x00000029, - TCC_PERF_SEL_MC_RDRET_NACK__CI = 0x0000002a, - TCC_PERF_SEL_TAG_STALL__VI = 0x0000002a, - TCC_PERF_SEL_MC_WRRET_NACK__CI = 0x0000002b, - TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL__VI = 0x0000002b, - TCC_PERF_SEL_EXE_REQ__CI = 0x0000002c, - TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL__VI = 0x0000002c, - TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL__VI = 0x0000002d, - TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL__VI = 0x0000002e, - TCC_PERF_SEL_TAG_PROBE_STALL__VI = 0x0000002f, - TCC_PERF_SEL_TAG_PROBE_FILTER_STALL__VI = 0x00000030, - TCC_PERF_SEL_READ_RETURN_TIMEOUT__VI = 0x00000031, - TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT__VI = 0x00000032, - TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE__VI = 0x00000033, - TCC_PERF_SEL_BUBBLE__VI = 0x00000034, - TCC_PERF_SEL_RETURN_ACK__VI = 0x00000035, - TCC_PERF_SEL_RETURN_DATA__VI = 0x00000036, - TCC_PERF_SEL_RETURN_HOLE__VI = 0x00000037, - TCC_PERF_SEL_RETURN_ACK_HOLE__VI = 0x00000038, - TCC_PERF_SEL_IB_REQ__VI = 0x00000039, - TCC_PERF_SEL_IB_STALL__VI = 0x0000003a, - TCC_PERF_SEL_IB_TAG_STALL__VI = 0x0000003b, - TCC_PERF_SEL_IB_MDC_STALL__VI = 0x0000003c, - TCC_PERF_SEL_TCA_LEVEL__VI = 0x0000003d, - TCC_PERF_SEL_HOLE_LEVEL__VI = 0x0000003e, - TCC_PERF_SEL_MC_RDRET_NACK__VI = 0x0000003f, - TCC_PERF_SEL_CLIENT0_REQ__SI__CI = 0x00000040, - TCC_PERF_SEL_MC_WRRET_NACK__VI = 0x00000040, - TCC_PERF_SEL_CLIENT1_REQ__SI__CI = 0x00000041, - TCC_PERF_SEL_NORMAL_WRITEBACK__VI = 0x00000041, - TCC_PERF_SEL_CLIENT2_REQ__SI__CI = 0x00000042, - TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK__VI = 0x00000042, - TCC_PERF_SEL_CLIENT3_REQ__SI__CI = 0x00000043, - TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK__VI = 0x00000043, - TCC_PERF_SEL_CLIENT4_REQ__SI__CI = 0x00000044, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK__VI = 0x00000044, - TCC_PERF_SEL_CLIENT5_REQ__SI__CI = 0x00000045, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK__VI = 0x00000045, - TCC_PERF_SEL_CLIENT6_REQ__SI__CI = 0x00000046, - TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK__VI = 0x00000046, - TCC_PERF_SEL_CLIENT7_REQ__SI__CI = 0x00000047, - TCC_PERF_SEL_NORMAL_EVICT__VI = 0x00000047, - TCC_PERF_SEL_CLIENT8_REQ__SI__CI = 0x00000048, - TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT__VI = 0x00000048, - TCC_PERF_SEL_CLIENT9_REQ__SI__CI = 0x00000049, - TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT__VI = 0x00000049, - TCC_PERF_SEL_CLIENT10_REQ__SI__CI = 0x0000004a, - TCC_PERF_SEL_TC_OP_WBINVL2_EVICT__VI = 0x0000004a, - TCC_PERF_SEL_CLIENT11_REQ__SI__CI = 0x0000004b, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT__VI = 0x0000004b, - TCC_PERF_SEL_CLIENT12_REQ__SI__CI = 0x0000004c, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT__VI = 0x0000004c, - TCC_PERF_SEL_CLIENT13_REQ__SI__CI = 0x0000004d, - TCC_PERF_SEL_ALL_TC_OP_INV_EVICT__VI = 0x0000004d, - TCC_PERF_SEL_CLIENT14_REQ__SI__CI = 0x0000004e, - TCC_PERF_SEL_PROBE_EVICT__VI = 0x0000004e, - TCC_PERF_SEL_CLIENT15_REQ__SI__CI = 0x0000004f, - TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE__VI = 0x0000004f, - TCC_PERF_SEL_CLIENT16_REQ__SI__CI = 0x00000050, - TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE__VI = 0x00000050, - TCC_PERF_SEL_CLIENT17_REQ__SI__CI = 0x00000051, - TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE__VI = 0x00000051, - TCC_PERF_SEL_CLIENT18_REQ__SI__CI = 0x00000052, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE__VI = 0x00000052, - TCC_PERF_SEL_CLIENT19_REQ__SI__CI = 0x00000053, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE__VI = 0x00000053, - TCC_PERF_SEL_CLIENT20_REQ__SI__CI = 0x00000054, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE__VI = 0x00000054, - TCC_PERF_SEL_CLIENT21_REQ__SI__CI = 0x00000055, - TCC_PERF_SEL_TC_OP_WBL2_NC_START__VI = 0x00000055, - TCC_PERF_SEL_CLIENT22_REQ__SI__CI = 0x00000056, - TCC_PERF_SEL_TC_OP_INVL2_NC_START__VI = 0x00000056, - TCC_PERF_SEL_CLIENT23_REQ__SI__CI = 0x00000057, - TCC_PERF_SEL_TC_OP_WBINVL2_START__VI = 0x00000057, - TCC_PERF_SEL_CLIENT24_REQ__SI__CI = 0x00000058, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_START__VI = 0x00000058, - TCC_PERF_SEL_CLIENT25_REQ__SI__CI = 0x00000059, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_START__VI = 0x00000059, - TCC_PERF_SEL_CLIENT26_REQ__SI__CI = 0x0000005a, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START__VI = 0x0000005a, - TCC_PERF_SEL_CLIENT27_REQ__SI__CI = 0x0000005b, - TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH__VI = 0x0000005b, - TCC_PERF_SEL_CLIENT28_REQ__SI__CI = 0x0000005c, - TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH__VI = 0x0000005c, - TCC_PERF_SEL_CLIENT29_REQ__SI__CI = 0x0000005d, - TCC_PERF_SEL_TC_OP_WBINVL2_FINISH__VI = 0x0000005d, - TCC_PERF_SEL_CLIENT30_REQ__SI__CI = 0x0000005e, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH__VI = 0x0000005e, - TCC_PERF_SEL_CLIENT31_REQ__SI__CI = 0x0000005f, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH__VI = 0x0000005f, - TCC_PERF_SEL_CLIENT32_REQ__SI__CI = 0x00000060, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH__VI = 0x00000060, - TCC_PERF_SEL_CLIENT33_REQ__SI__CI = 0x00000061, - TCC_PERF_SEL_MDC_REQ__VI = 0x00000061, - TCC_PERF_SEL_CLIENT34_REQ__SI__CI = 0x00000062, - TCC_PERF_SEL_MDC_LEVEL__VI = 0x00000062, - TCC_PERF_SEL_CLIENT35_REQ__SI__CI = 0x00000063, - TCC_PERF_SEL_MDC_TAG_HIT__VI = 0x00000063, - TCC_PERF_SEL_CLIENT36_REQ__SI__CI = 0x00000064, - TCC_PERF_SEL_MDC_SECTOR_HIT__VI = 0x00000064, - TCC_PERF_SEL_CLIENT37_REQ__SI__CI = 0x00000065, - TCC_PERF_SEL_MDC_SECTOR_MISS__VI = 0x00000065, - TCC_PERF_SEL_CLIENT38_REQ__SI__CI = 0x00000066, - TCC_PERF_SEL_MDC_TAG_STALL__VI = 0x00000066, - TCC_PERF_SEL_CLIENT39_REQ__SI__CI = 0x00000067, - TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL__VI = 0x00000067, - TCC_PERF_SEL_CLIENT40_REQ__SI__CI = 0x00000068, - TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL__VI = 0x00000068, - TCC_PERF_SEL_CLIENT41_REQ__SI__CI = 0x00000069, - TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL__VI = 0x00000069, - TCC_PERF_SEL_CLIENT42_REQ__SI__CI = 0x0000006a, - TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION__VI = 0x0000006a, - TCC_PERF_SEL_CLIENT43_REQ__SI__CI = 0x0000006b, - TCC_PERF_SEL_PROBE_FILTER_DISABLED__VI = 0x0000006b, - TCC_PERF_SEL_CLIENT44_REQ__SI__CI = 0x0000006c, - TCC_PERF_SEL_CLIENT45_REQ__SI__CI = 0x0000006d, - TCC_PERF_SEL_CLIENT46_REQ__SI__CI = 0x0000006e, - TCC_PERF_SEL_CLIENT47_REQ__SI__CI = 0x0000006f, - TCC_PERF_SEL_CLIENT48_REQ__SI__CI = 0x00000070, - TCC_PERF_SEL_CLIENT49_REQ__SI__CI = 0x00000071, - TCC_PERF_SEL_CLIENT50_REQ__SI__CI = 0x00000072, - TCC_PERF_SEL_CLIENT51_REQ__SI__CI = 0x00000073, - TCC_PERF_SEL_CLIENT52_REQ__SI__CI = 0x00000074, - TCC_PERF_SEL_CLIENT53_REQ__SI__CI = 0x00000075, - TCC_PERF_SEL_CLIENT54_REQ__SI__CI = 0x00000076, - TCC_PERF_SEL_CLIENT55_REQ__SI__CI = 0x00000077, - TCC_PERF_SEL_CLIENT56_REQ__SI__CI = 0x00000078, - TCC_PERF_SEL_CLIENT57_REQ__SI__CI = 0x00000079, - TCC_PERF_SEL_CLIENT58_REQ__SI__CI = 0x0000007a, - TCC_PERF_SEL_CLIENT59_REQ__SI__CI = 0x0000007b, - TCC_PERF_SEL_CLIENT60_REQ__SI__CI = 0x0000007c, - TCC_PERF_SEL_CLIENT61_REQ__SI__CI = 0x0000007d, - TCC_PERF_SEL_CLIENT62_REQ__SI__CI = 0x0000007e, - TCC_PERF_SEL_CLIENT63_REQ__SI__CI = 0x0000007f, - TCC_PERF_SEL_NORMAL_WRITEBACK__CI = 0x00000080, - TCC_PERF_SEL_CLIENT0_REQ__VI = 0x00000080, - TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK__CI = 0x00000081, - TCC_PERF_SEL_CLIENT1_REQ__VI = 0x00000081, - TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK__CI = 0x00000082, - TCC_PERF_SEL_CLIENT2_REQ__VI = 0x00000082, - TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK__CI = 0x00000083, - TCC_PERF_SEL_CLIENT3_REQ__VI = 0x00000083, - TCC_PERF_SEL_NORMAL_EVICT__CI = 0x00000084, - TCC_PERF_SEL_CLIENT4_REQ__VI = 0x00000084, - TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT__CI = 0x00000085, - TCC_PERF_SEL_CLIENT5_REQ__VI = 0x00000085, - TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT__CI = 0x00000086, - TCC_PERF_SEL_CLIENT6_REQ__VI = 0x00000086, - TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT__CI = 0x00000087, - TCC_PERF_SEL_CLIENT7_REQ__VI = 0x00000087, - TCC_PERF_SEL_TC_OP_WBINVL2_EVICT__CI = 0x00000088, - TCC_PERF_SEL_CLIENT8_REQ__VI = 0x00000088, - TCC_PERF_SEL_ALL_TC_OP_INV_EVICT__CI = 0x00000089, - TCC_PERF_SEL_CLIENT9_REQ__VI = 0x00000089, - TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT__CI = 0x0000008a, - TCC_PERF_SEL_CLIENT10_REQ__VI = 0x0000008a, - TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE__CI = 0x0000008b, - TCC_PERF_SEL_CLIENT11_REQ__VI = 0x0000008b, - TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE__CI = 0x0000008c, - TCC_PERF_SEL_CLIENT12_REQ__VI = 0x0000008c, - TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE__CI = 0x0000008d, - TCC_PERF_SEL_CLIENT13_REQ__VI = 0x0000008d, - TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE__CI = 0x0000008e, - TCC_PERF_SEL_CLIENT14_REQ__VI = 0x0000008e, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE__CI = 0x0000008f, - TCC_PERF_SEL_CLIENT15_REQ__VI = 0x0000008f, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE__CI = 0x00000090, - TCC_PERF_SEL_CLIENT16_REQ__VI = 0x00000090, - TCC_PERF_SEL_TC_OP_WBL2_VOL_START__CI = 0x00000091, - TCC_PERF_SEL_CLIENT17_REQ__VI = 0x00000091, - TCC_PERF_SEL_TC_OP_INVL2_VOL_START__CI = 0x00000092, - TCC_PERF_SEL_CLIENT18_REQ__VI = 0x00000092, - TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START__CI = 0x00000093, - TCC_PERF_SEL_CLIENT19_REQ__VI = 0x00000093, - TCC_PERF_SEL_TC_OP_WBINVL2_START__CI = 0x00000094, - TCC_PERF_SEL_CLIENT20_REQ__VI = 0x00000094, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START__CI = 0x00000095, - TCC_PERF_SEL_CLIENT21_REQ__VI = 0x00000095, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START__CI = 0x00000096, - TCC_PERF_SEL_CLIENT22_REQ__VI = 0x00000096, - TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH__CI = 0x00000097, - TCC_PERF_SEL_CLIENT23_REQ__VI = 0x00000097, - TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH__CI = 0x00000098, - TCC_PERF_SEL_CLIENT24_REQ__VI = 0x00000098, - TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH__CI = 0x00000099, - TCC_PERF_SEL_CLIENT25_REQ__VI = 0x00000099, - TCC_PERF_SEL_TC_OP_WBINVL2_FINISH__CI = 0x0000009a, - TCC_PERF_SEL_CLIENT26_REQ__VI = 0x0000009a, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH__CI = 0x0000009b, - TCC_PERF_SEL_CLIENT27_REQ__VI = 0x0000009b, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH__CI = 0x0000009c, - TCC_PERF_SEL_CLIENT28_REQ__VI = 0x0000009c, - TCC_PERF_SEL_VOL_MC_WRREQ__CI = 0x0000009d, - TCC_PERF_SEL_CLIENT29_REQ__VI = 0x0000009d, - TCC_PERF_SEL_VOL_MC_RDREQ__CI = 0x0000009e, - TCC_PERF_SEL_CLIENT30_REQ__VI = 0x0000009e, - TCC_PERF_SEL_VOL_REQ__CI = 0x0000009f, - TCC_PERF_SEL_CLIENT31_REQ__VI = 0x0000009f, - TCC_PERF_SEL_CLIENT32_REQ__VI = 0x000000a0, - TCC_PERF_SEL_CLIENT33_REQ__VI = 0x000000a1, - TCC_PERF_SEL_CLIENT34_REQ__VI = 0x000000a2, - TCC_PERF_SEL_CLIENT35_REQ__VI = 0x000000a3, - TCC_PERF_SEL_CLIENT36_REQ__VI = 0x000000a4, - TCC_PERF_SEL_CLIENT37_REQ__VI = 0x000000a5, - TCC_PERF_SEL_CLIENT38_REQ__VI = 0x000000a6, - TCC_PERF_SEL_CLIENT39_REQ__VI = 0x000000a7, - TCC_PERF_SEL_CLIENT40_REQ__VI = 0x000000a8, - TCC_PERF_SEL_CLIENT41_REQ__VI = 0x000000a9, - TCC_PERF_SEL_CLIENT42_REQ__VI = 0x000000aa, - TCC_PERF_SEL_CLIENT43_REQ__VI = 0x000000ab, - TCC_PERF_SEL_CLIENT44_REQ__VI = 0x000000ac, - TCC_PERF_SEL_CLIENT45_REQ__VI = 0x000000ad, - TCC_PERF_SEL_CLIENT46_REQ__VI = 0x000000ae, - TCC_PERF_SEL_CLIENT47_REQ__VI = 0x000000af, - TCC_PERF_SEL_CLIENT48_REQ__VI = 0x000000b0, - TCC_PERF_SEL_CLIENT49_REQ__VI = 0x000000b1, - TCC_PERF_SEL_CLIENT50_REQ__VI = 0x000000b2, - TCC_PERF_SEL_CLIENT51_REQ__VI = 0x000000b3, - TCC_PERF_SEL_CLIENT52_REQ__VI = 0x000000b4, - TCC_PERF_SEL_CLIENT53_REQ__VI = 0x000000b5, - TCC_PERF_SEL_CLIENT54_REQ__VI = 0x000000b6, - TCC_PERF_SEL_CLIENT55_REQ__VI = 0x000000b7, - TCC_PERF_SEL_CLIENT56_REQ__VI = 0x000000b8, - TCC_PERF_SEL_CLIENT57_REQ__VI = 0x000000b9, - TCC_PERF_SEL_CLIENT58_REQ__VI = 0x000000ba, - TCC_PERF_SEL_CLIENT59_REQ__VI = 0x000000bb, - TCC_PERF_SEL_CLIENT60_REQ__VI = 0x000000bc, - TCC_PERF_SEL_CLIENT61_REQ__VI = 0x000000bd, - TCC_PERF_SEL_CLIENT62_REQ__VI = 0x000000be, - TCC_PERF_SEL_CLIENT63_REQ__VI = 0x000000bf, - TCC_PERF_SEL_CLIENT64_REQ__VI = 0x000000c0, - TCC_PERF_SEL_CLIENT65_REQ__VI = 0x000000c1, - TCC_PERF_SEL_CLIENT66_REQ__VI = 0x000000c2, - TCC_PERF_SEL_CLIENT67_REQ__VI = 0x000000c3, - TCC_PERF_SEL_CLIENT68_REQ__VI = 0x000000c4, - TCC_PERF_SEL_CLIENT69_REQ__VI = 0x000000c5, - TCC_PERF_SEL_CLIENT70_REQ__VI = 0x000000c6, - TCC_PERF_SEL_CLIENT71_REQ__VI = 0x000000c7, - TCC_PERF_SEL_CLIENT72_REQ__VI = 0x000000c8, - TCC_PERF_SEL_CLIENT73_REQ__VI = 0x000000c9, - TCC_PERF_SEL_CLIENT74_REQ__VI = 0x000000ca, - TCC_PERF_SEL_CLIENT75_REQ__VI = 0x000000cb, - TCC_PERF_SEL_CLIENT76_REQ__VI = 0x000000cc, - TCC_PERF_SEL_CLIENT77_REQ__VI = 0x000000cd, - TCC_PERF_SEL_CLIENT78_REQ__VI = 0x000000ce, - TCC_PERF_SEL_CLIENT79_REQ__VI = 0x000000cf, - TCC_PERF_SEL_CLIENT80_REQ__VI = 0x000000d0, - TCC_PERF_SEL_CLIENT81_REQ__VI = 0x000000d1, - TCC_PERF_SEL_CLIENT82_REQ__VI = 0x000000d2, - TCC_PERF_SEL_CLIENT83_REQ__VI = 0x000000d3, - TCC_PERF_SEL_CLIENT84_REQ__VI = 0x000000d4, - TCC_PERF_SEL_CLIENT85_REQ__VI = 0x000000d5, - TCC_PERF_SEL_CLIENT86_REQ__VI = 0x000000d6, - TCC_PERF_SEL_CLIENT87_REQ__VI = 0x000000d7, - TCC_PERF_SEL_CLIENT88_REQ__VI = 0x000000d8, - TCC_PERF_SEL_CLIENT89_REQ__VI = 0x000000d9, - TCC_PERF_SEL_CLIENT90_REQ__VI = 0x000000da, - TCC_PERF_SEL_CLIENT91_REQ__VI = 0x000000db, - TCC_PERF_SEL_CLIENT92_REQ__VI = 0x000000dc, - TCC_PERF_SEL_CLIENT93_REQ__VI = 0x000000dd, - TCC_PERF_SEL_CLIENT94_REQ__VI = 0x000000de, - TCC_PERF_SEL_CLIENT95_REQ__VI = 0x000000df, - TCC_PERF_SEL_CLIENT96_REQ__VI = 0x000000e0, - TCC_PERF_SEL_CLIENT97_REQ__VI = 0x000000e1, - TCC_PERF_SEL_CLIENT98_REQ__VI = 0x000000e2, - TCC_PERF_SEL_CLIENT99_REQ__VI = 0x000000e3, - TCC_PERF_SEL_CLIENT100_REQ__VI = 0x000000e4, - TCC_PERF_SEL_CLIENT101_REQ__VI = 0x000000e5, - TCC_PERF_SEL_CLIENT102_REQ__VI = 0x000000e6, - TCC_PERF_SEL_CLIENT103_REQ__VI = 0x000000e7, - TCC_PERF_SEL_CLIENT104_REQ__VI = 0x000000e8, - TCC_PERF_SEL_CLIENT105_REQ__VI = 0x000000e9, - TCC_PERF_SEL_CLIENT106_REQ__VI = 0x000000ea, - TCC_PERF_SEL_CLIENT107_REQ__VI = 0x000000eb, - TCC_PERF_SEL_CLIENT108_REQ__VI = 0x000000ec, - TCC_PERF_SEL_CLIENT109_REQ__VI = 0x000000ed, - TCC_PERF_SEL_CLIENT110_REQ__VI = 0x000000ee, - TCC_PERF_SEL_CLIENT111_REQ__VI = 0x000000ef, - TCC_PERF_SEL_CLIENT112_REQ__VI = 0x000000f0, - TCC_PERF_SEL_CLIENT113_REQ__VI = 0x000000f1, - TCC_PERF_SEL_CLIENT114_REQ__VI = 0x000000f2, - TCC_PERF_SEL_CLIENT115_REQ__VI = 0x000000f3, - TCC_PERF_SEL_CLIENT116_REQ__VI = 0x000000f4, - TCC_PERF_SEL_CLIENT117_REQ__VI = 0x000000f5, - TCC_PERF_SEL_CLIENT118_REQ__VI = 0x000000f6, - TCC_PERF_SEL_CLIENT119_REQ__VI = 0x000000f7, - TCC_PERF_SEL_CLIENT120_REQ__VI = 0x000000f8, - TCC_PERF_SEL_CLIENT121_REQ__VI = 0x000000f9, - TCC_PERF_SEL_CLIENT122_REQ__VI = 0x000000fa, - TCC_PERF_SEL_CLIENT123_REQ__VI = 0x000000fb, - TCC_PERF_SEL_CLIENT124_REQ__VI = 0x000000fc, - TCC_PERF_SEL_CLIENT125_REQ__VI = 0x000000fd, - TCC_PERF_SEL_CLIENT126_REQ__VI = 0x000000fe, - TCC_PERF_SEL_CLIENT127_REQ__VI = 0x000000ff, -} TCC_PERF_SEL; - -typedef enum TCP_CACHE_POLICIES { - TCP_CACHE_POLICY_MISS_LRU = 0x00000000, - TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, - TCP_CACHE_POLICY_HIT_LRU = 0x00000002, - TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, -} TCP_CACHE_POLICIES; - -typedef enum TCP_CACHE_STORE_POLICIES { - TCP_CACHE_STORE_POLICY_MISS_LRU__SI__CI = 0x00000000, - TCP_CACHE_STORE_POLICY_WT_LRU__VI = 0x00000000, - TCP_CACHE_STORE_POLICY_MISS_EVICT__SI__CI = 0x00000001, - TCP_CACHE_STORE_POLICY_WT_EVICT__VI = 0x00000001, -} TCP_CACHE_STORE_POLICIES; - -typedef enum TCP_PERFCOUNT_SELECT { - TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES__SI = 0, - TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES__CI__VI = 0x00000000, - TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES__CI__VI = 0x00000001, - TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES__CI__VI = 0x00000002, - TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES__CI__VI = 0x00000003, - TCP_PERF_SEL_TD_TCP_STALL_CYCLES__CI__VI = 0x00000004, - TCP_PERF_SEL_TCR_TCP_STALL_CYCLES__CI__VI = 0x00000005, - TCP_PERF_SEL_LOD_STALL_CYCLES__CI__VI = 0x00000006, - TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000007, - TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000008, - TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000009, - TCP_PERF_SEL_ALLOC_STALL_CYCLES__CI__VI = 0x0000000a, - TCP_PERF_SEL_LFIFO_STALL_CYCLES__CI__VI = 0x0000000b, - TCP_PERF_SEL_RFIFO_STALL_CYCLES__CI__VI = 0x0000000c, - TCP_PERF_SEL_TCR_RDRET_STALL__CI__VI = 0x0000000d, - TCP_PERF_SEL_WRITE_CONFLICT_STALL__CI__VI = 0x0000000e, - TCP_PERF_SEL_HOLE_READ_STALL__CI__VI = 0x0000000f, - TCP_PERF_SEL_READCONFLICT_STALL_CYCLES__CI__VI = 0x00000010, - TCP_PERF_SEL_PENDING_STALL_CYCLES__CI__VI = 0x00000011, - TCP_PERF_SEL_READFIFO_STALL_CYCLES__CI__VI = 0x00000012, - TCP_PERF_SEL_TCP_LATENCY__CI__VI = 0x00000013, - TCP_PERF_SEL_TCC_READ_REQ_LATENCY__CI__VI = 0x00000014, - TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY__CI__VI = 0x00000015, - TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY__CI__VI = 0x00000016, - TCP_PERF_SEL_TCC_READ_REQ__CI__VI = 0x00000017, - TCP_PERF_SEL_TCC_WRITE_REQ__CI__VI = 0x00000018, - TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ__CI__VI = 0x00000019, - TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ__CI__VI = 0x0000001a, - TCP_PERF_SEL_TOTAL_LOCAL_READ__CI__VI = 0x0000001b, - TCP_PERF_SEL_TOTAL_GLOBAL_READ__CI__VI = 0x0000001c, - TCP_PERF_SEL_TOTAL_LOCAL_WRITE__CI__VI = 0x0000001d, - TCP_PERF_SEL_TOTAL_GLOBAL_WRITE__CI__VI = 0x0000001e, - TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET__CI__VI = 0x0000001f, - TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET__CI__VI = 0x00000020, - TCP_PERF_SEL_TOTAL_WBINVL1__CI__VI = 0x00000021, - TCP_PERF_SEL_IMG_READ_FMT_1__CI__VI = 0x00000022, - TCP_PERF_SEL_IMG_READ_FMT_8__CI__VI = 0x00000023, - TCP_PERF_SEL_IMG_READ_FMT_16__CI__VI = 0x00000024, - TCP_PERF_SEL_IMG_READ_FMT_32__CI__VI = 0x00000025, - TCP_PERF_SEL_IMG_READ_FMT_32_AS_8__CI__VI = 0x00000026, - TCP_PERF_SEL_IMG_READ_FMT_32_AS_16__CI__VI = 0x00000027, - TCP_PERF_SEL_IMG_READ_FMT_32_AS_128__CI__VI = 0x00000028, - TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE__CI__VI = 0x00000029, - TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE__CI__VI = 0x0000002a, - TCP_PERF_SEL_IMG_READ_FMT_96__CI__VI = 0x0000002b, - TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE__CI__VI = 0x0000002c, - TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE__CI__VI = 0x0000002d, - TCP_PERF_SEL_IMG_READ_FMT_BC1__CI__VI = 0x0000002e, - TCP_PERF_SEL_IMG_READ_FMT_BC2__CI__VI = 0x0000002f, - TCP_PERF_SEL_IMG_READ_FMT_BC3__CI__VI = 0x00000030, - TCP_PERF_SEL_IMG_READ_FMT_BC4__CI__VI = 0x00000031, - TCP_PERF_SEL_IMG_READ_FMT_BC5__CI__VI = 0x00000032, - TCP_PERF_SEL_IMG_READ_FMT_BC6__CI__VI = 0x00000033, - TCP_PERF_SEL_IMG_READ_FMT_BC7__CI__VI = 0x00000034, - TCP_PERF_SEL_IMG_READ_FMT_I8__CI__VI = 0x00000035, - TCP_PERF_SEL_IMG_READ_FMT_I16__CI__VI = 0x00000036, - TCP_PERF_SEL_IMG_READ_FMT_I32__CI__VI = 0x00000037, - TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8__CI__VI = 0x00000038, - TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16__CI__VI = 0x00000039, - TCP_PERF_SEL_IMG_READ_FMT_D8__CI__VI = 0x0000003a, - TCP_PERF_SEL_IMG_READ_FMT_D16__CI__VI = 0x0000003b, - TCP_PERF_SEL_IMG_READ_FMT_D32__CI__VI = 0x0000003c, - TCP_PERF_SEL_IMG_WRITE_FMT_8__CI__VI = 0x0000003d, - TCP_PERF_SEL_IMG_WRITE_FMT_16__CI__VI = 0x0000003e, - TCP_PERF_SEL_IMG_WRITE_FMT_32__CI__VI = 0x0000003f, - TCP_PERF_SEL_IMG_WRITE_FMT_64__CI__VI = 0x00000040, - TCP_PERF_SEL_IMG_WRITE_FMT_128__CI__VI = 0x00000041, - TCP_PERF_SEL_IMG_WRITE_FMT_D8__CI__VI = 0x00000042, - TCP_PERF_SEL_IMG_WRITE_FMT_D16__CI__VI = 0x00000043, - TCP_PERF_SEL_IMG_WRITE_FMT_D32__CI__VI = 0x00000044, - TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32__CI__VI = 0x00000045, - TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32__CI__VI = 0x00000046, - TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64__CI__VI = 0x00000047, - TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64__CI__VI = 0x00000048, - TCP_PERF_SEL_BUF_READ_FMT_8__CI__VI = 0x00000049, - TCP_PERF_SEL_BUF_READ_FMT_16__CI__VI = 0x0000004a, - TCP_PERF_SEL_BUF_READ_FMT_32__CI__VI = 0x0000004b, - TCP_PERF_SEL_BUF_WRITE_FMT_8__CI__VI = 0x0000004c, - TCP_PERF_SEL_BUF_WRITE_FMT_16__CI__VI = 0x0000004d, - TCP_PERF_SEL_BUF_WRITE_FMT_32__CI__VI = 0x0000004e, - TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32__CI__VI = 0x0000004f, - TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32__CI__VI = 0x00000050, - TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64__CI__VI = 0x00000051, - TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64__CI__VI = 0x00000052, - TCP_PERF_SEL_ARR_LINEAR_GENERAL__CI__VI = 0x00000053, - TCP_PERF_SEL_ARR_LINEAR_ALIGNED__CI__VI = 0x00000054, - TCP_PERF_SEL_ARR_1D_THIN1__CI__VI = 0x00000055, - TCP_PERF_SEL_ARR_1D_THICK__CI__VI = 0x00000056, - TCP_PERF_SEL_ARR_2D_THIN1__CI__VI = 0x00000057, - TCP_PERF_SEL_ARR_2D_THICK__CI__VI = 0x00000058, - TCP_PERF_SEL_ARR_2D_XTHICK__CI__VI = 0x00000059, - TCP_PERF_SEL_ARR_3D_THIN1__CI__VI = 0x0000005a, - TCP_PERF_SEL_ARR_3D_THICK__CI__VI = 0x0000005b, - TCP_PERF_SEL_ARR_3D_XTHICK__CI__VI = 0x0000005c, - TCP_PERF_SEL_DIM_1D__CI__VI = 0x0000005d, - TCP_PERF_SEL_DIM_2D__CI__VI = 0x0000005e, - TCP_PERF_SEL_DIM_3D__CI__VI = 0x0000005f, - TCP_PERF_SEL_DIM_1D_ARRAY__CI__VI = 0x00000060, - TCP_PERF_SEL_DIM_2D_ARRAY__CI__VI = 0x00000061, - TCP_PERF_SEL_DIM_2D_MSAA__CI__VI = 0x00000062, - TCP_PERF_SEL_DIM_2D_ARRAY_MSAA__CI__VI = 0x00000063, - TCP_PERF_SEL_DIM_CUBE_ARRAY__CI__VI = 0x00000064, - TCP_PERF_SEL_CP_TCP_INVALIDATE__CI__VI = 0x00000065, - TCP_PERF_SEL_TA_TCP_STATE_READ__CI__VI = 0x00000066, - TCP_PERF_SEL_TAGRAM0_REQ__CI__VI = 0x00000067, - TCP_PERF_SEL_TAGRAM1_REQ__CI__VI = 0x00000068, - TCP_PERF_SEL_TAGRAM2_REQ__CI__VI = 0x00000069, - TCP_PERF_SEL_TAGRAM3_REQ__CI__VI = 0x0000006a, - TCP_PERF_SEL_GATE_EN1__CI__VI = 0x0000006b, - TCP_PERF_SEL_GATE_EN2__CI__VI = 0x0000006c, - TCP_PERF_SEL_CORE_REG_SCLK_VLD__CI__VI = 0x0000006d, - TCP_PERF_SEL_TCC_REQ__CI__VI = 0x0000006e, - TCP_PERF_SEL_TCC_NON_READ_REQ__CI__VI = 0x0000006f, - TCP_PERF_SEL_TCC_BYPASS_READ_REQ__CI__VI = 0x00000070, - TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ__CI__VI = 0x00000071, - TCP_PERF_SEL_TCC_VOLATILE_READ_REQ__CI__VI = 0x00000072, - TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ__CI__VI = 0x00000073, - TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ__CI__VI = 0x00000074, - TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ__CI__VI = 0x00000075, - TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ__CI__VI = 0x00000076, - TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ__CI__VI = 0x00000077, - TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ__CI__VI = 0x00000078, - TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ__CI__VI = 0x00000079, - TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ__CI__VI = 0x0000007a, - TCP_PERF_SEL_TCC_ATOMIC_REQ__CI__VI = 0x0000007b, - TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ__CI__VI = 0x0000007c, - TCP_PERF_SEL_TCC_DATA_BUS_BUSY__CI__VI = 0x0000007d, - TCP_PERF_SEL_TOTAL_ACCESSES__CI__VI = 0x0000007e, - TCP_PERF_SEL_TOTAL_READ__CI__VI = 0x0000007f, - TCP_PERF_SEL_TOTAL_HIT_LRU_READ__CI__VI = 0x00000080, - TCP_PERF_SEL_TOTAL_HIT_EVICT_READ__CI__VI = 0x00000081, - TCP_PERF_SEL_TOTAL_MISS_LRU_READ__CI__VI = 0x00000082, - TCP_PERF_SEL_TOTAL_MISS_EVICT_READ__CI__VI = 0x00000083, - TCP_PERF_SEL_TOTAL_NON_READ__CI__VI = 0x00000084, - TCP_PERF_SEL_TOTAL_WRITE__CI__VI = 0x00000085, - TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE__CI__VI = 0x00000086, - TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE__CI__VI = 0x00000087, - TCP_PERF_SEL_TOTAL_WBINVL1_VOL__CI__VI = 0x00000088, - TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES__CI__VI = 0x00000089, - TCP_PERF_SEL_DISPLAY_MICROTILING__CI__VI = 0x0000008a, - TCP_PERF_SEL_THIN_MICROTILING__CI__VI = 0x0000008b, - TCP_PERF_SEL_DEPTH_MICROTILING__CI__VI = 0x0000008c, - TCP_PERF_SEL_ARR_PRT_THIN1__CI__VI = 0x0000008d, - TCP_PERF_SEL_ARR_PRT_2D_THIN1__CI__VI = 0x0000008e, - TCP_PERF_SEL_ARR_PRT_3D_THIN1__CI__VI = 0x0000008f, - TCP_PERF_SEL_ARR_PRT_THICK__CI__VI = 0x00000090, - TCP_PERF_SEL_ARR_PRT_2D_THICK__CI__VI = 0x00000091, - TCP_PERF_SEL_ARR_PRT_3D_THICK__CI__VI = 0x00000092, - TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL__CI__VI = 0x00000093, - TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL__CI__VI = 0x00000094, - TCP_PERF_SEL_UNALIGNED__CI__VI = 0x00000095, - TCP_PERF_SEL_ROTATED_MICROTILING__CI__VI = 0x00000096, - TCP_PERF_SEL_THICK_MICROTILING__CI__VI = 0x00000097, - TCP_PERF_SEL_ATC__CI__VI = 0x00000098, - TCP_PERF_SEL_POWER_STALL__CI__VI = 0x00000099, - TCP_PERF_SEL_RESERVED_154__VI = 0x0000009a, - TCP_PERF_SEL_TCC_LRU_REQ__VI = 0x0000009b, - TCP_PERF_SEL_TCC_STREAM_REQ__VI = 0x0000009c, - TCP_PERF_SEL_TCC_NC_READ_REQ__VI = 0x0000009d, - TCP_PERF_SEL_TCC_NC_WRITE_REQ__VI = 0x0000009e, - TCP_PERF_SEL_TCC_NC_ATOMIC_REQ__VI = 0x0000009f, - TCP_PERF_SEL_TCC_UC_READ_REQ__VI = 0x000000a0, - TCP_PERF_SEL_TCC_UC_WRITE_REQ__VI = 0x000000a1, - TCP_PERF_SEL_TCC_UC_ATOMIC_REQ__VI = 0x000000a2, - TCP_PERF_SEL_TCC_CC_READ_REQ__VI = 0x000000a3, - TCP_PERF_SEL_TCC_CC_WRITE_REQ__VI = 0x000000a4, - TCP_PERF_SEL_TCC_CC_ATOMIC_REQ__VI = 0x000000a5, - TCP_PERF_SEL_TCC_DCC_REQ__VI = 0x000000a6, - TCP_PERF_SEL_TCC_PHYSICAL_REQ__VI = 0x000000a7, - TCP_PERF_SEL_UNORDERED_MTYPE_STALL__VI = 0x000000a8, - TCP_PERF_SEL_VOLATILE__VI = 0x000000a9, - TCP_PERF_SEL_TC_TA_XNACK_STALL__VI = 0x000000aa, - TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL__VI = 0x000000ab, - TCP_PERF_SEL_SHOOTDOWN__VI = 0x000000ac, - TCP_PERF_SEL_GATCL1_TRANSLATION_MISS__VI = 0x000000ad, - TCP_PERF_SEL_GATCL1_PERMISSION_MISS__VI = 0x000000ae, - TCP_PERF_SEL_GATCL1_REQUEST__VI = 0x000000af, - TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX__VI = 0x000000b0, - TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT__VI = 0x000000b1, - TCP_PERF_SEL_GATCL1_LFIFO_FULL__VI = 0x000000b2, - TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x000000b3, - TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS__VI = 0x000000b4, - TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT__VI = 0x000000b5, - TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL__VI = 0x000000b6, - TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB__VI = 0x000000b7, - TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA__VI = 0x000000b8, - TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1__VI = 0x000000b9, - TCP_PERF_SEL_IMG_READ_FMT_ETC2_R__VI = 0x000000ba, - TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG__VI = 0x000000bb, - TCP_PERF_SEL_IMG_READ_FMT_8_AS_32__VI = 0x000000bc, - TCP_PERF_SEL_IMG_READ_FMT_8_AS_64__VI = 0x000000bd, - TCP_PERF_SEL_IMG_READ_FMT_16_AS_64__VI = 0x000000be, - TCP_PERF_SEL_IMG_READ_FMT_16_AS_128__VI = 0x000000bf, - TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32__VI = 0x000000c0, - TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64__VI = 0x000000c1, - TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64__VI = 0x000000c2, - TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128__VI = 0x000000c3, - TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES__SI = 1, - TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES__SI = 2, - TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES__SI = 3, - TCP_PERF_SEL_TD_TCP_STALL_CYCLES__SI = 4, - TCP_PERF_SEL_TCR_TCP_STALL_CYCLES__SI = 5, - TCP_PERF_SEL_LOD_STALL_CYCLES__SI = 6, - TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES__SI = 7, - TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES__SI = 8, - TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES__SI = 9, - TCP_PERF_SEL_ALLOC_STALL_CYCLES__SI = 10, - TCP_PERF_SEL_LFIFO_STALL_CYCLES__SI = 11, - TCP_PERF_SEL_RFIFO_STALL_CYCLES__SI = 12, - TCP_PERF_SEL_TCR_RDRET_STALL__SI = 13, - TCP_PERF_SEL_WRITE_CONFLICT_STALL__SI = 14, - TCP_PERF_SEL_HOLE_READ_STALL__SI = 15, - TCP_PERF_SEL_READCONFLICT_STALL_CYCLES__SI = 16, - TCP_PERF_SEL_PENDING_STALL_CYCLES__SI = 17, - TCP_PERF_SEL_READFIFO_STALL_CYCLES__SI = 18, - TCP_PERF_SEL_TCP_LATENCY__SI = 19, - TCP_PERF_SEL_TCC_READ_REQ_LATENCY__SI = 20, - TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY__SI = 21, - TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY__SI = 22, - TCP_PERF_SEL_TCC_READ_REQ__SI = 23, - TCP_PERF_SEL_TCC_WRITE_REQ__SI = 24, - TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ__SI = 25, - TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ__SI = 26, - TCP_PERF_SEL_TOTAL_LOCAL_READ__SI = 27, - TCP_PERF_SEL_TOTAL_GLOBAL_READ__SI = 28, - TCP_PERF_SEL_TOTAL_LOCAL_WRITE__SI = 29, - TCP_PERF_SEL_TOTAL_GLOBAL_WRITE__SI = 30, - TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET__SI = 31, - TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET__SI = 32, - TCP_PERF_SEL_TOTAL_WBINVL1__SI = 33, - TCP_PERF_SEL_IMG_READ_FMT_1__SI = 34, - TCP_PERF_SEL_IMG_READ_FMT_8__SI = 35, - TCP_PERF_SEL_IMG_READ_FMT_16__SI = 36, - TCP_PERF_SEL_IMG_READ_FMT_32__SI = 37, - TCP_PERF_SEL_IMG_READ_FMT_32_AS_8__SI = 38, - TCP_PERF_SEL_IMG_READ_FMT_32_AS_16__SI = 39, - TCP_PERF_SEL_IMG_READ_FMT_32_AS_128__SI = 40, - TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE__SI = 41, - TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE__SI = 42, - TCP_PERF_SEL_IMG_READ_FMT_96__SI = 43, - TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE__SI = 44, - TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE__SI = 45, - TCP_PERF_SEL_IMG_READ_FMT_BC1__SI = 46, - TCP_PERF_SEL_IMG_READ_FMT_BC2__SI = 47, - TCP_PERF_SEL_IMG_READ_FMT_BC3__SI = 48, - TCP_PERF_SEL_IMG_READ_FMT_BC4__SI = 49, - TCP_PERF_SEL_IMG_READ_FMT_BC5__SI = 50, - TCP_PERF_SEL_IMG_READ_FMT_BC6__SI = 51, - TCP_PERF_SEL_IMG_READ_FMT_BC7__SI = 52, - TCP_PERF_SEL_IMG_READ_FMT_I8__SI = 53, - TCP_PERF_SEL_IMG_READ_FMT_I16__SI = 54, - TCP_PERF_SEL_IMG_READ_FMT_I32__SI = 55, - TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8__SI = 56, - TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16__SI = 57, - TCP_PERF_SEL_IMG_READ_FMT_D8__SI = 58, - TCP_PERF_SEL_IMG_READ_FMT_D16__SI = 59, - TCP_PERF_SEL_IMG_READ_FMT_D32__SI = 60, - TCP_PERF_SEL_IMG_WRITE_FMT_8__SI = 61, - TCP_PERF_SEL_IMG_WRITE_FMT_16__SI = 62, - TCP_PERF_SEL_IMG_WRITE_FMT_32__SI = 63, - TCP_PERF_SEL_IMG_WRITE_FMT_64__SI = 64, - TCP_PERF_SEL_IMG_WRITE_FMT_128__SI = 65, - TCP_PERF_SEL_IMG_WRITE_FMT_D8__SI = 66, - TCP_PERF_SEL_IMG_WRITE_FMT_D16__SI = 67, - TCP_PERF_SEL_IMG_WRITE_FMT_D32__SI = 68, - TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32__SI = 69, - TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32__SI = 70, - TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64__SI = 71, - TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64__SI = 72, - TCP_PERF_SEL_BUF_READ_FMT_8__SI = 73, - TCP_PERF_SEL_BUF_READ_FMT_16__SI = 74, - TCP_PERF_SEL_BUF_READ_FMT_32__SI = 75, - TCP_PERF_SEL_BUF_WRITE_FMT_8__SI = 76, - TCP_PERF_SEL_BUF_WRITE_FMT_16__SI = 77, - TCP_PERF_SEL_BUF_WRITE_FMT_32__SI = 78, - TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32__SI = 79, - TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32__SI = 80, - TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64__SI = 81, - TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64__SI = 82, - TCP_PERF_SEL_ARR_LINEAR_GENERAL__SI = 83, - TCP_PERF_SEL_ARR_LINEAR_ALIGNED__SI = 84, - TCP_PERF_SEL_ARR_1D_THIN1__SI = 85, - TCP_PERF_SEL_ARR_1D_THICK__SI = 86, - TCP_PERF_SEL_ARR_2D_THIN1__SI = 87, - TCP_PERF_SEL_ARR_2D_THICK__SI = 88, - TCP_PERF_SEL_ARR_2D_XTHICK__SI = 89, - TCP_PERF_SEL_ARR_3D_THIN1__SI = 90, - TCP_PERF_SEL_ARR_3D_THICK__SI = 91, - TCP_PERF_SEL_ARR_3D_XTHICK__SI = 92, - TCP_PERF_SEL_DIM_1D__SI = 93, - TCP_PERF_SEL_DIM_2D__SI = 94, - TCP_PERF_SEL_DIM_3D__SI = 95, - TCP_PERF_SEL_DIM_1D_ARRAY__SI = 96, - TCP_PERF_SEL_DIM_2D_ARRAY__SI = 97, - TCP_PERF_SEL_DIM_2D_MSAA__SI = 98, - TCP_PERF_SEL_DIM_2D_ARRAY_MSAA__SI = 99, - TCP_PERF_SEL_DIM_CUBE_ARRAY__SI = 100, - TCP_PERF_SEL_CP_TCP_INVALIDATE__SI = 101, - TCP_PERF_SEL_TA_TCP_STATE_READ__SI = 102, - TCP_PERF_SEL_TAGRAM0_REQ__SI = 103, - TCP_PERF_SEL_TAGRAM1_REQ__SI = 104, - TCP_PERF_SEL_TAGRAM2_REQ__SI = 105, - TCP_PERF_SEL_TAGRAM3_REQ__SI = 106, - TCP_PERF_SEL_GATE_EN1__SI = 107, - TCP_PERF_SEL_GATE_EN2__SI = 108, - TCP_PERF_SEL_CORE_REG_SCLK_VLD__SI = 109, -} TCP_PERFCOUNT_SELECT; - -typedef enum TCP_WATCH_MODES { - TCP_WATCH_MODE_READ = 0x00000000, - TCP_WATCH_MODE_NONREAD = 0x00000001, - TCP_WATCH_MODE_ATOMIC = 0x00000002, - TCP_WATCH_MODE_ALL = 0x00000003, -} TCP_WATCH_MODES; - -typedef enum TCS_PERF_SEL { - TCS_PERF_SEL_NONE = 0x00000000, - TCS_PERF_SEL_CYCLE = 0x00000001, - TCS_PERF_SEL_BUSY = 0x00000002, - TCS_PERF_SEL_REQ = 0x00000003, - TCS_PERF_SEL_READ = 0x00000004, - TCS_PERF_SEL_WRITE = 0x00000005, - TCS_PERF_SEL_ATOMIC = 0x00000006, - TCS_PERF_SEL_HOLE_FIFO_FULL = 0x00000007, - TCS_PERF_SEL_REQ_FIFO_FULL = 0x00000008, - TCS_PERF_SEL_REQ_CREDIT_STALL = 0x00000009, - TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL = 0x0000000a, - TCS_PERF_SEL_REQ_STALL = 0x0000000b, - TCS_PERF_SEL_TCS_CHUB_REQ_SEND = 0x0000000c, - TCS_PERF_SEL_CHUB_TCS_RET_SEND = 0x0000000d, - TCS_PERF_SEL_RETURN_ACK = 0x0000000e, - TCS_PERF_SEL_RETURN_DATA = 0x0000000f, - TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL = 0x00000010, - TCS_PERF_SEL_IB_STALL = 0x00000011, - TCS_PERF_SEL_TCA_LEVEL = 0x00000012, - TCS_PERF_SEL_HOLE_LEVEL = 0x00000013, - TCS_PERF_SEL_CHUB_LEVEL = 0x00000014, - TCS_PERF_SEL_CLIENT0_REQ = 0x00000040, - TCS_PERF_SEL_CLIENT1_REQ = 0x00000041, - TCS_PERF_SEL_CLIENT2_REQ = 0x00000042, - TCS_PERF_SEL_CLIENT3_REQ = 0x00000043, - TCS_PERF_SEL_CLIENT4_REQ = 0x00000044, - TCS_PERF_SEL_CLIENT5_REQ = 0x00000045, - TCS_PERF_SEL_CLIENT6_REQ = 0x00000046, - TCS_PERF_SEL_CLIENT7_REQ = 0x00000047, - TCS_PERF_SEL_CLIENT8_REQ = 0x00000048, - TCS_PERF_SEL_CLIENT9_REQ = 0x00000049, - TCS_PERF_SEL_CLIENT10_REQ = 0x0000004a, - TCS_PERF_SEL_CLIENT11_REQ = 0x0000004b, - TCS_PERF_SEL_CLIENT12_REQ = 0x0000004c, - TCS_PERF_SEL_CLIENT13_REQ = 0x0000004d, - TCS_PERF_SEL_CLIENT14_REQ = 0x0000004e, - TCS_PERF_SEL_CLIENT15_REQ = 0x0000004f, - TCS_PERF_SEL_CLIENT16_REQ = 0x00000050, - TCS_PERF_SEL_CLIENT17_REQ = 0x00000051, - TCS_PERF_SEL_CLIENT18_REQ = 0x00000052, - TCS_PERF_SEL_CLIENT19_REQ = 0x00000053, - TCS_PERF_SEL_CLIENT20_REQ = 0x00000054, - TCS_PERF_SEL_CLIENT21_REQ = 0x00000055, - TCS_PERF_SEL_CLIENT22_REQ = 0x00000056, - TCS_PERF_SEL_CLIENT23_REQ = 0x00000057, - TCS_PERF_SEL_CLIENT24_REQ = 0x00000058, - TCS_PERF_SEL_CLIENT25_REQ = 0x00000059, - TCS_PERF_SEL_CLIENT26_REQ = 0x0000005a, - TCS_PERF_SEL_CLIENT27_REQ = 0x0000005b, - TCS_PERF_SEL_CLIENT28_REQ = 0x0000005c, - TCS_PERF_SEL_CLIENT29_REQ = 0x0000005d, - TCS_PERF_SEL_CLIENT30_REQ = 0x0000005e, - TCS_PERF_SEL_CLIENT31_REQ = 0x0000005f, - TCS_PERF_SEL_CLIENT32_REQ = 0x00000060, - TCS_PERF_SEL_CLIENT33_REQ = 0x00000061, - TCS_PERF_SEL_CLIENT34_REQ = 0x00000062, - TCS_PERF_SEL_CLIENT35_REQ = 0x00000063, - TCS_PERF_SEL_CLIENT36_REQ = 0x00000064, - TCS_PERF_SEL_CLIENT37_REQ = 0x00000065, - TCS_PERF_SEL_CLIENT38_REQ = 0x00000066, - TCS_PERF_SEL_CLIENT39_REQ = 0x00000067, - TCS_PERF_SEL_CLIENT40_REQ = 0x00000068, - TCS_PERF_SEL_CLIENT41_REQ = 0x00000069, - TCS_PERF_SEL_CLIENT42_REQ = 0x0000006a, - TCS_PERF_SEL_CLIENT43_REQ = 0x0000006b, - TCS_PERF_SEL_CLIENT44_REQ = 0x0000006c, - TCS_PERF_SEL_CLIENT45_REQ = 0x0000006d, - TCS_PERF_SEL_CLIENT46_REQ = 0x0000006e, - TCS_PERF_SEL_CLIENT47_REQ = 0x0000006f, - TCS_PERF_SEL_CLIENT48_REQ = 0x00000070, - TCS_PERF_SEL_CLIENT49_REQ = 0x00000071, - TCS_PERF_SEL_CLIENT50_REQ = 0x00000072, - TCS_PERF_SEL_CLIENT51_REQ = 0x00000073, - TCS_PERF_SEL_CLIENT52_REQ = 0x00000074, - TCS_PERF_SEL_CLIENT53_REQ = 0x00000075, - TCS_PERF_SEL_CLIENT54_REQ = 0x00000076, - TCS_PERF_SEL_CLIENT55_REQ = 0x00000077, - TCS_PERF_SEL_CLIENT56_REQ = 0x00000078, - TCS_PERF_SEL_CLIENT57_REQ = 0x00000079, - TCS_PERF_SEL_CLIENT58_REQ = 0x0000007a, - TCS_PERF_SEL_CLIENT59_REQ = 0x0000007b, - TCS_PERF_SEL_CLIENT60_REQ = 0x0000007c, - TCS_PERF_SEL_CLIENT61_REQ = 0x0000007d, - TCS_PERF_SEL_CLIENT62_REQ = 0x0000007e, - TCS_PERF_SEL_CLIENT63_REQ = 0x0000007f, -} TCS_PERF_SEL; - -typedef enum TC_CHUB_REQ_CREDITS_ENUM { - TC_CHUB_REQ_CREDITS = 0x00000010, -} TC_CHUB_REQ_CREDITS_ENUM; - -typedef enum TC_NACKS { - TC_NACK_NO_FAULT = 0x00000000, - TC_NACK_PAGE_FAULT = 0x00000001, - TC_NACK_PROTECTION_FAULT = 0x00000002, - TC_NACK_DATA_ERROR = 0x00000003, -} TC_NACKS; - -typedef enum TC_OP { - TC_OP_READ = 0x00000000, - TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, - TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, - TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, - TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, - TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005, - TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, - TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, - TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0x0000000c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, - TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, - TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, - TC_OP_ATOMIC_RSUB_RTN_32__SI = 0x00000011, - TC_OP_ATOMIC_SMIN_RTN_32__CI__VI = 0x00000011, - TC_OP_ATOMIC_SMIN_RTN_32__SI = 0x00000012, - TC_OP_ATOMIC_UMIN_RTN_32__CI__VI = 0x00000012, - TC_OP_ATOMIC_UMIN_RTN_32__SI = 0x00000013, - TC_OP_ATOMIC_SMAX_RTN_32__CI__VI = 0x00000013, - TC_OP_ATOMIC_SMAX_RTN_32__SI = 0x00000014, - TC_OP_ATOMIC_UMAX_RTN_32__CI__VI = 0x00000014, - TC_OP_ATOMIC_UMAX_RTN_32__SI = 0x00000015, - TC_OP_ATOMIC_AND_RTN_32__CI__VI = 0x00000015, - TC_OP_ATOMIC_AND_RTN_32__SI = 0x00000016, - TC_OP_ATOMIC_OR_RTN_32__CI__VI = 0x00000016, - TC_OP_ATOMIC_OR_RTN_32__SI = 0x00000017, - TC_OP_ATOMIC_XOR_RTN_32__CI__VI = 0x00000017, - TC_OP_ATOMIC_XOR_RTN_32__SI = 0x00000018, - TC_OP_ATOMIC_INC_RTN_32__CI__VI = 0x00000018, - TC_OP_ATOMIC_INC_RTN_32__SI = 0x00000019, - TC_OP_ATOMIC_DEC_RTN_32__CI__VI = 0x00000019, - TC_OP_ATOMIC_DEC_RTN_32__SI = 0x0000001a, - TC_OP_WBINVL1_VOL__CI__VI = 0x0000001a, - TC_OP_RESERVED_NON_FLOAT_RTN_32_0__SI__CI = 0x0000001b, - TC_OP_WBINVL1_SD__VI = 0x0000001b, - TC_OP_RESERVED_NON_FLOAT_RTN_32_1__SI__CI = 0x0000001c, - TC_OP_RESERVED_NON_FLOAT_RTN_32_0__VI = 0x0000001c, - TC_OP_RESERVED_NON_FLOAT_RTN_32_2__SI__CI = 0x0000001d, - TC_OP_RESERVED_NON_FLOAT_RTN_32_1__VI = 0x0000001d, - TC_OP_RESERVED_NON_FLOAT_RTN_32_3__SI__CI = 0x0000001e, - TC_OP_RESERVED_NON_FLOAT_RTN_32_2__VI = 0x0000001e, - TC_OP_RESERVED_NON_FLOAT_RTN_32_4__SI__CI = 0x0000001f, - TC_OP_RESERVED_NON_FLOAT_RTN_32_3__VI = 0x0000001f, - TC_OP_WRITE = 0x00000020, - TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, - TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, - TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, - TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, - TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, - TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, - TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, - TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0__SI__CI = 0x0000002c, - TC_OP_WBINVL2_SD__VI = 0x0000002c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1__SI__CI = 0x0000002d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0__VI = 0x0000002d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2__SI__CI = 0x0000002e, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1__VI = 0x0000002e, - TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, - TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, - TC_OP_ATOMIC_RSUB_RTN_64__SI = 0x00000031, - TC_OP_ATOMIC_SMIN_RTN_64__CI__VI = 0x00000031, - TC_OP_ATOMIC_SMIN_RTN_64__SI = 0x00000032, - TC_OP_ATOMIC_UMIN_RTN_64__CI__VI = 0x00000032, - TC_OP_ATOMIC_UMIN_RTN_64__SI = 0x00000033, - TC_OP_ATOMIC_SMAX_RTN_64__CI__VI = 0x00000033, - TC_OP_ATOMIC_SMAX_RTN_64__SI = 0x00000034, - TC_OP_ATOMIC_UMAX_RTN_64__CI__VI = 0x00000034, - TC_OP_ATOMIC_UMAX_RTN_64__SI = 0x00000035, - TC_OP_ATOMIC_AND_RTN_64__CI__VI = 0x00000035, - TC_OP_ATOMIC_AND_RTN_64__SI = 0x00000036, - TC_OP_ATOMIC_OR_RTN_64__CI__VI = 0x00000036, - TC_OP_ATOMIC_OR_RTN_64__SI = 0x00000037, - TC_OP_ATOMIC_XOR_RTN_64__CI__VI = 0x00000037, - TC_OP_ATOMIC_XOR_RTN_64__SI = 0x00000038, - TC_OP_ATOMIC_INC_RTN_64__CI__VI = 0x00000038, - TC_OP_ATOMIC_INC_RTN_64__SI = 0x00000039, - TC_OP_ATOMIC_DEC_RTN_64__CI__VI = 0x00000039, - TC_OP_ATOMIC_DEC_RTN_64__SI = 0x0000003a, - TC_OP_WBL2_VOL__CI = 0x0000003a, - TC_OP_WBL2_NC__VI = 0x0000003a, - TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x0000003b, - TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, - TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, - TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, - TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, - TC_OP_WBINVL1 = 0x00000040, - TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, - TC_OP_ATOMIC_FMIN_32 = 0x00000042, - TC_OP_ATOMIC_FMAX_32 = 0x00000043, - TC_OP_RESERVED_FOP_32_0 = 0x00000044, - TC_OP_RESERVED_FOP_32_1 = 0x00000045, - TC_OP_RESERVED_FOP_32_2 = 0x00000046, - TC_OP_ATOMIC_SWAP_32 = 0x00000047, - TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, - TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x0000004c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, - TC_OP_ATOMIC_ADD_32 = 0x0000004f, - TC_OP_ATOMIC_SUB_32 = 0x00000050, - TC_OP_ATOMIC_RSUB_32__SI = 0x00000051, - TC_OP_ATOMIC_SMIN_32__CI__VI = 0x00000051, - TC_OP_ATOMIC_SMIN_32__SI = 0x00000052, - TC_OP_ATOMIC_UMIN_32__CI__VI = 0x00000052, - TC_OP_ATOMIC_UMIN_32__SI = 0x00000053, - TC_OP_ATOMIC_SMAX_32__CI__VI = 0x00000053, - TC_OP_ATOMIC_SMAX_32__SI = 0x00000054, - TC_OP_ATOMIC_UMAX_32__CI__VI = 0x00000054, - TC_OP_ATOMIC_UMAX_32__SI = 0x00000055, - TC_OP_ATOMIC_AND_32__CI__VI = 0x00000055, - TC_OP_ATOMIC_AND_32__SI = 0x00000056, - TC_OP_ATOMIC_OR_32__CI__VI = 0x00000056, - TC_OP_ATOMIC_OR_32__SI = 0x00000057, - TC_OP_ATOMIC_XOR_32__CI__VI = 0x00000057, - TC_OP_ATOMIC_XOR_32__SI = 0x00000058, - TC_OP_ATOMIC_INC_32__CI__VI = 0x00000058, - TC_OP_ATOMIC_INC_32__SI = 0x00000059, - TC_OP_ATOMIC_DEC_32__CI__VI = 0x00000059, - TC_OP_ATOMIC_DEC_32__SI = 0x0000005a, - TC_OP_INVL2_VOL__CI = 0x0000005a, - TC_OP_INVL2_NC__VI = 0x0000005a, - TC_OP_RESERVED_NON_FLOAT_32_0 = 0x0000005b, - TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, - TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, - TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, - TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, - TC_OP_WBINVL2 = 0x00000060, - TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, - TC_OP_ATOMIC_FMIN_64 = 0x00000062, - TC_OP_ATOMIC_FMAX_64 = 0x00000063, - TC_OP_RESERVED_FOP_64_0 = 0x00000064, - TC_OP_RESERVED_FOP_64_1 = 0x00000065, - TC_OP_RESERVED_FOP_64_2 = 0x00000066, - TC_OP_ATOMIC_SWAP_64 = 0x00000067, - TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, - TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, - TC_OP_ATOMIC_ADD_64 = 0x0000006f, - TC_OP_ATOMIC_SUB_64 = 0x00000070, - TC_OP_ATOMIC_RSUB_64__SI = 0x00000071, - TC_OP_ATOMIC_SMIN_64__CI__VI = 0x00000071, - TC_OP_ATOMIC_SMIN_64__SI = 0x00000072, - TC_OP_ATOMIC_UMIN_64__CI__VI = 0x00000072, - TC_OP_ATOMIC_UMIN_64__SI = 0x00000073, - TC_OP_ATOMIC_SMAX_64__CI__VI = 0x00000073, - TC_OP_ATOMIC_SMAX_64__SI = 0x00000074, - TC_OP_ATOMIC_UMAX_64__CI__VI = 0x00000074, - TC_OP_ATOMIC_UMAX_64__SI = 0x00000075, - TC_OP_ATOMIC_AND_64__CI__VI = 0x00000075, - TC_OP_ATOMIC_AND_64__SI = 0x00000076, - TC_OP_ATOMIC_OR_64__CI__VI = 0x00000076, - TC_OP_ATOMIC_OR_64__SI = 0x00000077, - TC_OP_ATOMIC_XOR_64__CI__VI = 0x00000077, - TC_OP_ATOMIC_XOR_64__SI = 0x00000078, - TC_OP_ATOMIC_INC_64__CI__VI = 0x00000078, - TC_OP_ATOMIC_INC_64__SI = 0x00000079, - TC_OP_ATOMIC_DEC_64__CI__VI = 0x00000079, - TC_OP_ATOMIC_DEC_64__SI = 0x0000007a, - TC_OP_INVL1L2_VOL__CI = 0x0000007a, - TC_OP_WBINVL2_NC__VI = 0x0000007a, - TC_OP_RESERVED_NON_FLOAT_64_0 = 0x0000007b, - TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, - TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, - TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, - TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, -} TC_OP; - -typedef enum TC_OP_MASKS { - TC_OP_MASK_FLUSH_DENROM = 0x00000008, - TC_OP_MASK_64 = 0x00000020, - TC_OP_MASK_NO_RTN = 0x00000040, -} TC_OP_MASKS; - -typedef enum TD_PERFCOUNT_SEL { - TD_PERF_SEL_td_busy__SI__CI = 0x00000000, - TD_PERF_SEL_none__VI = 0x00000000, - TD_PERF_SEL_input_busy__SI__CI = 0x00000001, - TD_PERF_SEL_td_busy__VI = 0x00000001, - TD_PERF_SEL_output_busy__SI__CI = 0x00000002, - TD_PERF_SEL_input_busy__VI = 0x00000002, - TD_PERF_SEL_lerp_busy__SI__CI = 0x00000003, - TD_PERF_SEL_output_busy__VI = 0x00000003, - TD_PERF_SEL_RESERVED_4__SI__CI = 0x00000004, - TD_PERF_SEL_lerp_busy__VI = 0x00000004, - TD_PERF_SEL_reg_sclk_vld = 0x00000005, - TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006, - TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007, - TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008, - TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009, - TD_PERF_SEL_tc_td_fifo_full = 0x0000000a, - TD_PERF_SEL_constant_state_full = 0x0000000b, - TD_PERF_SEL_sample_state_full = 0x0000000c, - TD_PERF_SEL_output_fifo_full = 0x0000000d, - TD_PERF_SEL_RESERVED_14 = 0x0000000e, - TD_PERF_SEL_tc_stall = 0x0000000f, - TD_PERF_SEL_pc_stall = 0x00000010, - TD_PERF_SEL_gds_stall = 0x00000011, - TD_PERF_SEL_RESERVED_18 = 0x00000012, - TD_PERF_SEL_RESERVED_19 = 0x00000013, - TD_PERF_SEL_gather4_wavefront = 0x00000014, - TD_PERF_SEL_sample_c_wavefront = 0x00000015, - TD_PERF_SEL_load_wavefront = 0x00000016, - TD_PERF_SEL_atomic_wavefront = 0x00000017, - TD_PERF_SEL_store_wavefront = 0x00000018, - TD_PERF_SEL_ldfptr_wavefront = 0x00000019, - TD_PERF_SEL_RESERVED_26 = 0x0000001a, - TD_PERF_SEL_RESERVED_27 = 0x0000001b, - TD_PERF_SEL_RESERVED_28__SI__CI = 0x0000001c, - TD_PERF_SEL_d16_en_wavefront__VI = 0x0000001c, - TD_PERF_SEL_RESERVED_29__SI__CI = 0x0000001d, - TD_PERF_SEL_bicubic_filter_wavefront__VI = 0x0000001d, - TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e, - TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f, - TD_PERF_SEL_coalescable_wavefront = 0x00000020, - TD_PERF_SEL_coalesced_phase = 0x00000021, - TD_PERF_SEL_four_phase_wavefront = 0x00000022, - TD_PERF_SEL_eight_phase_wavefront = 0x00000023, - TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024, - TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025, - TD_PERF_SEL_write_ack_wavefront = 0x00000026, - TD_PERF_SEL_RESERVED_39 = 0x00000027, - TD_PERF_SEL_user_defined_border = 0x00000028, - TD_PERF_SEL_white_border = 0x00000029, - TD_PERF_SEL_opaque_black_border = 0x0000002a, - TD_PERF_SEL_RESERVED_43 = 0x0000002b, - TD_PERF_SEL_RESERVED_44 = 0x0000002c, - TD_PERF_SEL_nack = 0x0000002d, - TD_PERF_SEL_consume_gds_traffic__SI = 0x0000002e, - TD_PERF_SEL_td_sp_traffic__CI__VI = 0x0000002e, - TD_PERF_SEL_addresscmd_poison__SI = 0x0000002f, - TD_PERF_SEL_consume_gds_traffic__CI__VI = 0x0000002f, - TD_PERF_SEL_data_poison__SI = 0x00000030, - TD_PERF_SEL_addresscmd_poison__CI__VI = 0x00000030, - TD_PERF_SEL_data_poison__CI__VI = 0x00000031, - TD_PERF_SEL_start_cycle_0__CI__VI = 0x00000032, - TD_PERF_SEL_start_cycle_1__CI__VI = 0x00000033, - TD_PERF_SEL_start_cycle_2__CI__VI = 0x00000034, - TD_PERF_SEL_start_cycle_3__CI__VI = 0x00000035, - TD_PERF_SEL_null_cycle_output__CI__VI = 0x00000036, - TD_PERF_SEL_d16_data_packed__VI = 0x00000037, -} TD_PERFCOUNT_SEL; - -typedef enum TEX_BORDER_COLOR_TYPE { - TEX_BorderColor_TransparentBlack = 0x00000000, - TEX_BorderColor_OpaqueBlack = 0x00000001, - TEX_BorderColor_OpaqueWhite = 0x00000002, - TEX_BorderColor_Register = 0x00000003, -} TEX_BORDER_COLOR_TYPE; - -typedef enum TEX_CHROMA_KEY { - TEX_ChromaKey_Disabled = 0x00000000, - TEX_ChromaKey_Kill = 0x00000001, - TEX_ChromaKey_Blend = 0x00000002, - TEX_ChromaKey_RESERVED_3 = 0x00000003, -} TEX_CHROMA_KEY; - -typedef enum TEX_CLAMP { - TEX_Clamp_Repeat = 0x00000000, - TEX_Clamp_Mirror = 0x00000001, - TEX_Clamp_ClampToLast = 0x00000002, - TEX_Clamp_MirrorOnceToLast = 0x00000003, - TEX_Clamp_ClampHalfToBorder = 0x00000004, - TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, - TEX_Clamp_ClampToBorder = 0x00000006, - TEX_Clamp_MirrorOnceToBorder = 0x00000007, -} TEX_CLAMP; - -typedef enum TEX_COORD_TYPE { - TEX_CoordType_Unnormalized = 0x00000000, - TEX_CoordType_Normalized = 0x00000001, -} TEX_COORD_TYPE; - -typedef enum TEX_DEPTH_COMPARE_FUNCTION { - TEX_DepthCompareFunction_Never = 0x00000000, - TEX_DepthCompareFunction_Less = 0x00000001, - TEX_DepthCompareFunction_Equal = 0x00000002, - TEX_DepthCompareFunction_LessEqual = 0x00000003, - TEX_DepthCompareFunction_Greater = 0x00000004, - TEX_DepthCompareFunction_NotEqual = 0x00000005, - TEX_DepthCompareFunction_GreaterEqual = 0x00000006, - TEX_DepthCompareFunction_Always = 0x00000007, -} TEX_DEPTH_COMPARE_FUNCTION; - -typedef enum TEX_DIM { - TEX_Dim_1D = 0x00000000, - TEX_Dim_2D = 0x00000001, - TEX_Dim_3D = 0x00000002, - TEX_Dim_CubeMap = 0x00000003, - TEX_Dim_1DArray = 0x00000004, - TEX_Dim_2DArray = 0x00000005, - TEX_Dim_2D_MSAA = 0x00000006, - TEX_Dim_2DArray_MSAA = 0x00000007, -} TEX_DIM; - -typedef enum TEX_FORMAT_COMP { - TEX_FormatComp_Unsigned = 0x00000000, - TEX_FormatComp_Signed = 0x00000001, - TEX_FormatComp_UnsignedBiased = 0x00000002, - TEX_FormatComp_RESERVED_3 = 0x00000003, -} TEX_FORMAT_COMP; - -typedef enum TEX_MAX_ANISO_RATIO { - TEX_MaxAnisoRatio_1to1 = 0x00000000, - TEX_MaxAnisoRatio_2to1 = 0x00000001, - TEX_MaxAnisoRatio_4to1 = 0x00000002, - TEX_MaxAnisoRatio_8to1 = 0x00000003, - TEX_MaxAnisoRatio_16to1 = 0x00000004, - TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, - TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, - TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, -} TEX_MAX_ANISO_RATIO; - -typedef enum TEX_MIP_FILTER { - TEX_MipFilter_None = 0x00000000, - TEX_MipFilter_Point = 0x00000001, - TEX_MipFilter_Linear = 0x00000002, - TEX_MipFilter_RESERVED_3__SI__CI = 0x00000003, - TEX_MipFilter_Point_Aniso_Adj__VI = 0x00000003, -} TEX_MIP_FILTER; - -typedef enum TEX_REQUEST_SIZE { - TEX_RequestSize_32B = 0x00000000, - TEX_RequestSize_64B = 0x00000001, - TEX_RequestSize_128B = 0x00000002, - TEX_RequestSize_2X64B = 0x00000003, -} TEX_REQUEST_SIZE; - -typedef enum TEX_SAMPLER_TYPE { - TEX_SamplerType_Invalid = 0x00000000, - TEX_SamplerType_Valid = 0x00000001, -} TEX_SAMPLER_TYPE; - -typedef enum TEX_XY_FILTER { - TEX_XYFilter_Point = 0x00000000, - TEX_XYFilter_Linear = 0x00000001, - TEX_XYFilter_AnisoPoint = 0x00000002, - TEX_XYFilter_AnisoLinear = 0x00000003, -} TEX_XY_FILTER; - -typedef enum TEX_Z_FILTER { - TEX_ZFilter_None = 0x00000000, - TEX_ZFilter_Point = 0x00000001, - TEX_ZFilter_Linear = 0x00000002, - TEX_ZFilter_RESERVED_3 = 0x00000003, -} TEX_Z_FILTER; - -typedef enum TVX_DATA_FORMAT { - TVX_FMT_INVALID = 0x00000000, - TVX_FMT_8 = 0x00000001, - TVX_FMT_4_4 = 0x00000002, - TVX_FMT_3_3_2 = 0x00000003, - TVX_FMT_RESERVED_4 = 0x00000004, - TVX_FMT_16 = 0x00000005, - TVX_FMT_16_FLOAT = 0x00000006, - TVX_FMT_8_8 = 0x00000007, - TVX_FMT_5_6_5 = 0x00000008, - TVX_FMT_6_5_5 = 0x00000009, - TVX_FMT_1_5_5_5 = 0x0000000a, - TVX_FMT_4_4_4_4 = 0x0000000b, - TVX_FMT_5_5_5_1 = 0x0000000c, - TVX_FMT_32 = 0x0000000d, - TVX_FMT_32_FLOAT = 0x0000000e, - TVX_FMT_16_16 = 0x0000000f, - TVX_FMT_16_16_FLOAT = 0x00000010, - TVX_FMT_8_24 = 0x00000011, - TVX_FMT_8_24_FLOAT = 0x00000012, - TVX_FMT_24_8 = 0x00000013, - TVX_FMT_24_8_FLOAT = 0x00000014, - TVX_FMT_10_11_11 = 0x00000015, - TVX_FMT_10_11_11_FLOAT = 0x00000016, - TVX_FMT_11_11_10 = 0x00000017, - TVX_FMT_11_11_10_FLOAT = 0x00000018, - TVX_FMT_2_10_10_10 = 0x00000019, - TVX_FMT_8_8_8_8 = 0x0000001a, - TVX_FMT_10_10_10_2 = 0x0000001b, - TVX_FMT_X24_8_32_FLOAT = 0x0000001c, - TVX_FMT_32_32 = 0x0000001d, - TVX_FMT_32_32_FLOAT = 0x0000001e, - TVX_FMT_16_16_16_16 = 0x0000001f, - TVX_FMT_16_16_16_16_FLOAT = 0x00000020, - TVX_FMT_RESERVED_33 = 0x00000021, - TVX_FMT_32_32_32_32 = 0x00000022, - TVX_FMT_32_32_32_32_FLOAT = 0x00000023, - TVX_FMT_RESERVED_36 = 0x00000024, - TVX_FMT_1 = 0x00000025, - TVX_FMT_1_REVERSED = 0x00000026, - TVX_FMT_GB_GR = 0x00000027, - TVX_FMT_BG_RG = 0x00000028, - TVX_FMT_32_AS_8 = 0x00000029, - TVX_FMT_32_AS_8_8 = 0x0000002a, - TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b, - TVX_FMT_8_8_8 = 0x0000002c, - TVX_FMT_16_16_16 = 0x0000002d, - TVX_FMT_16_16_16_FLOAT = 0x0000002e, - TVX_FMT_32_32_32 = 0x0000002f, - TVX_FMT_32_32_32_FLOAT = 0x00000030, - TVX_FMT_BC1 = 0x00000031, - TVX_FMT_BC2 = 0x00000032, - TVX_FMT_BC3 = 0x00000033, - TVX_FMT_BC4 = 0x00000034, - TVX_FMT_BC5 = 0x00000035, - TVX_FMT_APC0 = 0x00000036, - TVX_FMT_APC1 = 0x00000037, - TVX_FMT_APC2 = 0x00000038, - TVX_FMT_APC3 = 0x00000039, - TVX_FMT_APC4 = 0x0000003a, - TVX_FMT_APC5 = 0x0000003b, - TVX_FMT_APC6 = 0x0000003c, - TVX_FMT_APC7 = 0x0000003d, - TVX_FMT_CTX1 = 0x0000003e, - TVX_FMT_RESERVED_63 = 0x0000003f, -} TVX_DATA_FORMAT; - -typedef enum TVX_DST_SEL { - TVX_DstSel_X = 0x00000000, - TVX_DstSel_Y = 0x00000001, - TVX_DstSel_Z = 0x00000002, - TVX_DstSel_W = 0x00000003, - TVX_DstSel_0f = 0x00000004, - TVX_DstSel_1f = 0x00000005, - TVX_DstSel_RESERVED_6 = 0x00000006, - TVX_DstSel_Mask = 0x00000007, -} TVX_DST_SEL; - -typedef enum TVX_ENDIAN_SWAP { - TVX_EndianSwap_None = 0x00000000, - TVX_EndianSwap_8in16 = 0x00000001, - TVX_EndianSwap_8in32 = 0x00000002, - TVX_EndianSwap_8in64 = 0x00000003, -} TVX_ENDIAN_SWAP; - -typedef enum TVX_INST { - TVX_Inst_NormalVertexFetch = 0x00000000, - TVX_Inst_SemanticVertexFetch = 0x00000001, - TVX_Inst_RESERVED_2 = 0x00000002, - TVX_Inst_LD = 0x00000003, - TVX_Inst_GetTextureResInfo = 0x00000004, - TVX_Inst_GetNumberOfSamples = 0x00000005, - TVX_Inst_GetLOD = 0x00000006, - TVX_Inst_GetGradientsH = 0x00000007, - TVX_Inst_GetGradientsV = 0x00000008, - TVX_Inst_SetTextureOffsets = 0x00000009, - TVX_Inst_KeepGradients = 0x0000000a, - TVX_Inst_SetGradientsH = 0x0000000b, - TVX_Inst_SetGradientsV = 0x0000000c, - TVX_Inst_Pass = 0x0000000d, - TVX_Inst_GetBufferResInfo = 0x0000000e, - TVX_Inst_RESERVED_15 = 0x0000000f, - TVX_Inst_Sample = 0x00000010, - TVX_Inst_Sample_L = 0x00000011, - TVX_Inst_Sample_LB = 0x00000012, - TVX_Inst_Sample_LZ = 0x00000013, - TVX_Inst_Sample_G = 0x00000014, - TVX_Inst_Gather4 = 0x00000015, - TVX_Inst_Sample_G_LB = 0x00000016, - TVX_Inst_Gather4_O = 0x00000017, - TVX_Inst_Sample_C = 0x00000018, - TVX_Inst_Sample_C_L = 0x00000019, - TVX_Inst_Sample_C_LB = 0x0000001a, - TVX_Inst_Sample_C_LZ = 0x0000001b, - TVX_Inst_Sample_C_G = 0x0000001c, - TVX_Inst_Gather4_C = 0x0000001d, - TVX_Inst_Sample_C_G_LB = 0x0000001e, - TVX_Inst_Gather4_C_O = 0x0000001f, -} TVX_INST; - -typedef enum TVX_NUM_FORMAT_ALL { - TVX_NumFormatAll_Norm = 0x00000000, - TVX_NumFormatAll_Int = 0x00000001, - TVX_NumFormatAll_Scaled = 0x00000002, - TVX_NumFormatAll_RESERVED_3 = 0x00000003, -} TVX_NUM_FORMAT_ALL; - -typedef enum TVX_SRC_SEL { - TVX_SrcSel_X = 0x00000000, - TVX_SrcSel_Y = 0x00000001, - TVX_SrcSel_Z = 0x00000002, - TVX_SrcSel_W = 0x00000003, - TVX_SrcSel_0f = 0x00000004, - TVX_SrcSel_1f = 0x00000005, -} TVX_SRC_SEL; - -typedef enum TVX_SRF_MODE_ALL { - TVX_SRFModeAll_ZCMO = 0x00000000, - TVX_SRFModeAll_NZ = 0x00000001, -} TVX_SRF_MODE_ALL; - -typedef enum TVX_TYPE { - TVX_Type_InvalidTextureResource = 0x00000000, - TVX_Type_InvalidVertexBuffer = 0x00000001, - TVX_Type_ValidTextureResource = 0x00000002, - TVX_Type_ValidVertexBuffer = 0x00000003, -} TVX_TYPE; - -typedef enum TileSplit { - ADDR_SURF_TILE_SPLIT_64B = 0x00000000, - ADDR_SURF_TILE_SPLIT_128B = 0x00000001, - ADDR_SURF_TILE_SPLIT_256B = 0x00000002, - ADDR_SURF_TILE_SPLIT_512B = 0x00000003, - ADDR_SURF_TILE_SPLIT_1KB = 0x00000004, - ADDR_SURF_TILE_SPLIT_2KB = 0x00000005, - ADDR_SURF_TILE_SPLIT_4KB = 0x00000006, -} TileSplit; - -typedef enum TileType { - ARRAY_COLOR_TILE = 0x00000000, - ARRAY_DEPTH_TILE = 0x00000001, -} TileType; - -typedef enum UVDFirmwareCommand { - UVDFC_FENCE = 0x00000000, - UVDFC_TRAP = 0x00000001, - UVDFC_DECODED_ADDR = 0x00000002, - UVDFC_MBLOCK_ADDR = 0x00000003, - UVDFC_ITBUF_ADDR = 0x00000004, - UVDFC_DISPLAY_ADDR = 0x00000005, - UVDFC_EOD = 0x00000006, - UVDFC_DISPLAY_PITCH = 0x00000007, - UVDFC_DISPLAY_TILING = 0x00000008, - UVDFC_BITSTREAM_ADDR = 0x00000009, - UVDFC_BITSTREAM_SIZE = 0x0000000a, -} UVDFirmwareCommand; - -typedef enum VGT_CACHE_INVALID_MODE { - VC_ONLY = 0x00000000, - TC_ONLY = 0x00000001, - VC_AND_TC = 0x00000002, -} VGT_CACHE_INVALID_MODE; - -typedef enum VGT_DI_INDEX_SIZE { - DI_INDEX_SIZE_16_BIT = 0x00000000, - DI_INDEX_SIZE_32_BIT = 0x00000001, - DI_INDEX_SIZE_8_BIT__VI = 0x00000002, -} VGT_DI_INDEX_SIZE; - -typedef enum VGT_DI_MAJOR_MODE_SELECT { - DI_MAJOR_MODE_0 = 0x00000000, - DI_MAJOR_MODE_1 = 0x00000001, -} VGT_DI_MAJOR_MODE_SELECT; - -typedef enum VGT_DI_PRIM_TYPE { - DI_PT_NONE = 0x00000000, - DI_PT_POINTLIST = 0x00000001, - DI_PT_LINELIST = 0x00000002, - DI_PT_LINESTRIP = 0x00000003, - DI_PT_TRILIST = 0x00000004, - DI_PT_TRIFAN = 0x00000005, - DI_PT_TRISTRIP = 0x00000006, - DI_PT_UNUSED_0 = 0x00000007, - DI_PT_UNUSED_1 = 0x00000008, - DI_PT_PATCH = 0x00000009, - DI_PT_LINELIST_ADJ = 0x0000000a, - DI_PT_LINESTRIP_ADJ = 0x0000000b, - DI_PT_TRILIST_ADJ = 0x0000000c, - DI_PT_TRISTRIP_ADJ = 0x0000000d, - DI_PT_UNUSED_3 = 0x0000000e, - DI_PT_UNUSED_4 = 0x0000000f, - DI_PT_TRI_WITH_WFLAGS = 0x00000010, - DI_PT_RECTLIST = 0x00000011, - DI_PT_LINELOOP = 0x00000012, - DI_PT_QUADLIST = 0x00000013, - DI_PT_QUADSTRIP = 0x00000014, - DI_PT_POLYGON = 0x00000015, - DI_PT_2D_COPY_RECT_LIST_V0 = 0x00000016, - DI_PT_2D_COPY_RECT_LIST_V1 = 0x00000017, - DI_PT_2D_COPY_RECT_LIST_V2 = 0x00000018, - DI_PT_2D_COPY_RECT_LIST_V3 = 0x00000019, - DI_PT_2D_FILL_RECT_LIST = 0x0000001a, - DI_PT_2D_LINE_STRIP = 0x0000001b, - DI_PT_2D_TRI_STRIP = 0x0000001c, -} VGT_DI_PRIM_TYPE; - -typedef enum VGT_DI_SOURCE_SELECT { - DI_SRC_SEL_DMA = 0x00000000, - DI_SRC_SEL_IMMEDIATE = 0x00000001, - DI_SRC_SEL_AUTO_INDEX = 0x00000002, - DI_SRC_SEL_RESERVED = 0x00000003, -} VGT_DI_SOURCE_SELECT; - -typedef enum VGT_DMA_BUF_TYPE { - VGT_DMA_BUF_MEM = 0x00000000, - VGT_DMA_BUF_RING = 0x00000001, - VGT_DMA_BUF_SETUP = 0x00000002, - VGT_DMA_PTR_UPDATE__VI = 0x00000003, -} VGT_DMA_BUF_TYPE; - -typedef enum VGT_DMA_SWAP_MODE { - VGT_DMA_SWAP_NONE = 0x00000000, - VGT_DMA_SWAP_16_BIT = 0x00000001, - VGT_DMA_SWAP_32_BIT = 0x00000002, - VGT_DMA_SWAP_WORD = 0x00000003, -} VGT_DMA_SWAP_MODE; - -typedef enum VGT_EVENT_TYPE { - Reserved_0x00 = 0x00000000, - SAMPLE_STREAMOUTSTATS1 = 0x00000001, - SAMPLE_STREAMOUTSTATS2 = 0x00000002, - SAMPLE_STREAMOUTSTATS3 = 0x00000003, - CACHE_FLUSH_TS = 0x00000004, - CONTEXT_DONE = 0x00000005, - CACHE_FLUSH = 0x00000006, - CS_PARTIAL_FLUSH = 0x00000007, - VGT_STREAMOUT_SYNC = 0x00000008, - Reserved_0x09 = 0x00000009, - VGT_STREAMOUT_RESET = 0x0000000a, - END_OF_PIPE_INCR_DE = 0x0000000b, - END_OF_PIPE_IB_END = 0x0000000c, - RST_PIX_CNT = 0x0000000d, - Reserved_0x0E = 0x0000000e, - VS_PARTIAL_FLUSH = 0x0000000f, - PS_PARTIAL_FLUSH = 0x00000010, - FLUSH_HS_OUTPUT = 0x00000011, - FLUSH_LS_OUTPUT = 0x00000012, - Reserved_0x13 = 0x00000013, - CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, - ZPASS_DONE = 0x00000015, - CACHE_FLUSH_AND_INV_EVENT = 0x00000016, - PERFCOUNTER_START = 0x00000017, - PERFCOUNTER_STOP = 0x00000018, - PIPELINESTAT_START = 0x00000019, - PIPELINESTAT_STOP = 0x0000001a, - PERFCOUNTER_SAMPLE = 0x0000001b, - FLUSH_ES_OUTPUT = 0x0000001c, - FLUSH_GS_OUTPUT = 0x0000001d, - SAMPLE_PIPELINESTAT = 0x0000001e, - SO_VGTSTREAMOUT_FLUSH = 0x0000001f, - SAMPLE_STREAMOUTSTATS = 0x00000020, - RESET_VTX_CNT = 0x00000021, - BLOCK_CONTEXT_DONE = 0x00000022, - CS_CONTEXT_DONE = 0x00000023, - VGT_FLUSH = 0x00000024, - Reserved_0x25__SI__CI = 0x00000025, - TGID_ROLLOVER__VI = 0x00000025, - SQ_NON_EVENT = 0x00000026, - SC_SEND_DB_VPZ = 0x00000027, - BOTTOM_OF_PIPE_TS = 0x00000028, - FLUSH_SX_TS = 0x00000029, - DB_CACHE_FLUSH_AND_INV = 0x0000002a, - FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, - FLUSH_AND_INV_DB_META = 0x0000002c, - FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, - FLUSH_AND_INV_CB_META = 0x0000002e, - CS_DONE = 0x0000002f, - PS_DONE = 0x00000030, - FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, - SX_CB_RAT_ACK_REQUEST = 0x00000032, - THREAD_TRACE_START = 0x00000033, - THREAD_TRACE_STOP = 0x00000034, - THREAD_TRACE_MARKER = 0x00000035, - THREAD_TRACE_FLUSH = 0x00000036, - THREAD_TRACE_FINISH = 0x00000037, - PIXEL_PIPE_STAT_CONTROL__CI__VI = 0x00000038, - PIXEL_PIPE_STAT_DUMP__CI__VI = 0x00000039, - PIXEL_PIPE_STAT_RESET__CI__VI = 0x0000003a, - CONTEXT_SUSPEND__CI__VI = 0x0000003b, - OFFCHIP_HS_DEALLOC__VI = 0x0000003c, -} VGT_EVENT_TYPE; - -typedef enum VGT_GROUP_CONV_SEL { - VGT_GRP_INDEX_16 = 0x00000000, - VGT_GRP_INDEX_32 = 0x00000001, - VGT_GRP_UINT_16 = 0x00000002, - VGT_GRP_UINT_32 = 0x00000003, - VGT_GRP_SINT_16 = 0x00000004, - VGT_GRP_SINT_32 = 0x00000005, - VGT_GRP_FLOAT_32 = 0x00000006, - VGT_GRP_AUTO_PRIM = 0x00000007, - VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, -} VGT_GROUP_CONV_SEL; - -typedef enum VGT_GRP_PRIM_ORDER { - VGT_GRP_LIST = 0x00000000, - VGT_GRP_STRIP = 0x00000001, - VGT_GRP_FAN = 0x00000002, - VGT_GRP_LOOP = 0x00000003, - VGT_GRP_POLYGON = 0x00000004, -} VGT_GRP_PRIM_ORDER; - -typedef enum VGT_GRP_PRIM_TYPE { - VGT_GRP_3D_POINT = 0x00000000, - VGT_GRP_3D_LINE = 0x00000001, - VGT_GRP_3D_TRI = 0x00000002, - VGT_GRP_3D_RECT = 0x00000003, - VGT_GRP_3D_QUAD = 0x00000004, - VGT_GRP_2D_COPY_RECT_V0 = 0x00000005, - VGT_GRP_2D_COPY_RECT_V1 = 0x00000006, - VGT_GRP_2D_COPY_RECT_V2 = 0x00000007, - VGT_GRP_2D_COPY_RECT_V3 = 0x00000008, - VGT_GRP_2D_FILL_RECT = 0x00000009, - VGT_GRP_2D_LINE = 0x0000000a, - VGT_GRP_2D_TRI = 0x0000000b, - VGT_GRP_PRIM_INDEX_LINE = 0x0000000c, - VGT_GRP_PRIM_INDEX_TRI = 0x0000000d, - VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e, - VGT_GRP_3D_LINE_ADJ = 0x0000000f, - VGT_GRP_3D_TRI_ADJ = 0x00000010, - VGT_GRP_3D_PATCH = 0x00000011, -} VGT_GRP_PRIM_TYPE; - -typedef enum VGT_GS_CUT_MODE { - GS_CUT_1024 = 0x00000000, - GS_CUT_512 = 0x00000001, - GS_CUT_256 = 0x00000002, - GS_CUT_128 = 0x00000003, -} VGT_GS_CUT_MODE; - -typedef enum VGT_GS_MODE_TYPE { - GS_OFF = 0x00000000, - GS_SCENARIO_A = 0x00000001, - GS_SCENARIO_B = 0x00000002, - GS_SCENARIO_G = 0x00000003, - GS_SCENARIO_C = 0x00000004, - SPRITE_EN = 0x00000005, -} VGT_GS_MODE_TYPE; - -typedef enum VGT_GS_OUTPRIM_TYPE { - POINTLIST = 0x00000000, - LINESTRIP = 0x00000001, - TRISTRIP = 0x00000002, -} VGT_GS_OUTPRIM_TYPE; - -typedef enum VGT_INDEX_TYPE_MODE { - VGT_INDEX_16 = 0x00000000, - VGT_INDEX_32 = 0x00000001, - VGT_INDEX_8__VI = 0x00000002, -} VGT_INDEX_TYPE_MODE; - -typedef enum VGT_OUTPATH_SELECT { - VGT_OUTPATH_VTX_REUSE = 0x00000000, - VGT_OUTPATH_TESS_EN = 0x00000001, - VGT_OUTPATH_PASSTHRU = 0x00000002, - VGT_OUTPATH_GS_BLOCK = 0x00000003, - VGT_OUTPATH_HS_BLOCK = 0x00000004, -} VGT_OUTPATH_SELECT; - -typedef enum VGT_OUT_PRIM_TYPE { - VGT_OUT_POINT = 0x00000000, - VGT_OUT_LINE = 0x00000001, - VGT_OUT_TRI = 0x00000002, - VGT_OUT_RECT_V0 = 0x00000003, - VGT_OUT_RECT_V1 = 0x00000004, - VGT_OUT_RECT_V2 = 0x00000005, - VGT_OUT_RECT_V3 = 0x00000006, - VGT_OUT_RESERVED = 0x00000007, - VGT_TE_QUAD = 0x00000008, - VGT_TE_PRIM_INDEX_LINE = 0x00000009, - VGT_TE_PRIM_INDEX_TRI = 0x0000000a, - VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, - VGT_OUT_LINE_ADJ = 0x0000000c, - VGT_OUT_TRI_ADJ = 0x0000000d, - VGT_OUT_PATCH = 0x0000000e, -} VGT_OUT_PRIM_TYPE; - -typedef enum VGT_PERFCOUNT_SELECT { - vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000, - vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001, - vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002, - vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003, - vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004, - vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005, - vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006, - vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x00000007, - vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x00000008, - vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009, - vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a, - vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b, - vgt_perf_VGT_SPI_GSPRIM_STALLED = 0x0000000c, - vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d, - vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e, - vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f, - vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010, - vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x00000011, - vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x00000012, - vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013, - vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014, - vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015, - vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016, - vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017, - vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018, - vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019, - vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000001a, - vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x0000001b, - vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c, - vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d, - vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e, - vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f, - vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020, - vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021, - vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022, - vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023, - vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024, - vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025, - vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026, - vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027, - vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028, - vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029, - vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a, - vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b, - vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c, - vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d, - vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e, - vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f, - vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030, - vgt_perf_vsvert_ds_send = 0x00000031, - vgt_perf_vsvert_api_send = 0x00000032, - vgt_perf_hs_tif_stall = 0x00000033, - vgt_perf_hs_input_stall = 0x00000034, - vgt_perf_hs_interface_stall = 0x00000035, - vgt_perf_hs_tfm_stall = 0x00000036, - vgt_perf_te11_starved = 0x00000037, - vgt_perf_gs_event_stall = 0x00000038, - vgt_perf_RESERVED0__SI = 0x00000039, - vgt_perf_vgt_pa_clipp_send_not_event__CI__VI = 0x00000039, - vgt_perf_RESERVED1__SI = 0x0000003a, - vgt_perf_vgt_pa_clipp_valid_prim__CI__VI = 0x0000003a, - vgt_perf_RESERVED2__SI = 0x0000003b, - vgt_perf_reused_es_indices__CI__VI = 0x0000003b, - vgt_perf_RESERVED3__SI = 0x0000003c, - vgt_perf_vs_cache_hits__CI__VI = 0x0000003c, - vgt_perf_RESERVED4__SI = 0x0000003d, - vgt_perf_gs_cache_hits__CI__VI = 0x0000003d, - vgt_perf_RESERVED5__SI = 0x0000003e, - vgt_perf_ds_cache_hits__CI__VI = 0x0000003e, - vgt_perf_RESERVED6__SI = 0x0000003f, - vgt_perf_total_cache_hits__CI__VI = 0x0000003f, - vgt_perf_vgt_busy = 0x00000040, - vgt_perf_vgt_gs_busy = 0x00000041, - vgt_perf_esvert_stalled_es_tbl = 0x00000042, - vgt_perf_esvert_stalled_gs_tbl = 0x00000043, - vgt_perf_esvert_stalled_gs_event = 0x00000044, - vgt_perf_esvert_stalled_gsprim = 0x00000045, - vgt_perf_gsprim_stalled_es_tbl = 0x00000046, - vgt_perf_gsprim_stalled_gs_tbl = 0x00000047, - vgt_perf_gsprim_stalled_gs_event = 0x00000048, - vgt_perf_gsprim_stalled_esvert = 0x00000049, - vgt_perf_esthread_stalled_es_rb_full = 0x0000004a, - vgt_perf_esthread_stalled_spi_bp = 0x0000004b, - vgt_perf_counters_avail_stalled = 0x0000004c, - vgt_perf_gs_rb_space_avail_stalled = 0x0000004d, - vgt_perf_gs_issue_rtr_stalled = 0x0000004e, - vgt_perf_gsthread_stalled = 0x0000004f, - vgt_perf_RESERVED7__SI = 0x00000050, - vgt_perf_strmout_stalled__CI__VI = 0x00000050, - vgt_perf_wait_for_es_done_stalled = 0x00000051, - vgt_perf_cm_stalled_by_gog = 0x00000052, - vgt_perf_cm_reading_stalled = 0x00000053, - vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054, - vgt_perf_gog_vs_tbl_stalled = 0x00000055, - vgt_perf_gog_out_indx_stalled = 0x00000056, - vgt_perf_gog_out_prim_stalled = 0x00000057, - vgt_perf_RESERVED8__SI = 0x00000058, - vgt_perf_waveid_stalled__CI__VI = 0x00000058, - vgt_perf_gog_busy = 0x00000059, - vgt_perf_reused_vs_indices = 0x0000005a, - vgt_perf_sclk_reg_vld_event = 0x0000005b, - vgt_perf_RESERVED9__SI = 0x0000005c, - vgt_perf_RESERVED0__CI = 0x0000005c, - vgt_perf_vs_conflicting_indices__VI = 0x0000005c, - vgt_perf_sclk_core_vld_event = 0x0000005d, - vgt_perf_RESERVED10__SI = 0x0000005e, - vgt_perf_RESERVED1__CI = 0x0000005e, - vgt_perf_hswave_stalled__VI = 0x0000005e, - vgt_perf_sclk_gs_vld_event = 0x0000005f, - vgt_perf_VGT_SPI_LSVERT_VALID = 0x00000060, - vgt_perf_VGT_SPI_LSVERT_EOV = 0x00000061, - vgt_perf_VGT_SPI_LSVERT_STALLED = 0x00000062, - vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x00000063, - vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x00000064, - vgt_perf_VGT_SPI_LSVERT_STATIC = 0x00000065, - vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066, - vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x00000067, - vgt_perf_VGT_SPI_LSWAVE_SEND = 0x00000068, - vgt_perf_VGT_SPI_HSVERT_VALID = 0x00000069, - vgt_perf_VGT_SPI_HSVERT_EOV = 0x0000006a, - vgt_perf_VGT_SPI_HSVERT_STALLED = 0x0000006b, - vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x0000006c, - vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x0000006d, - vgt_perf_VGT_SPI_HSVERT_STATIC = 0x0000006e, - vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f, - vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x00000070, - vgt_perf_VGT_SPI_HSWAVE_SEND = 0x00000071, - vgt_perf_RESERVED11__SI = 0x00000072, - vgt_perf_ds_prims__CI__VI = 0x00000072, - vgt_perf_null_tess_patches__SI__CI = 0x00000073, - vgt_perf_ls_thread_groups__VI = 0x00000073, - vgt_perf_ls_thread_groups__SI__CI = 0x00000074, - vgt_perf_hs_thread_groups__VI = 0x00000074, - vgt_perf_hs_thread_groups__SI__CI = 0x00000075, - vgt_perf_es_thread_groups__VI = 0x00000075, - vgt_perf_es_thread_groups__SI__CI = 0x00000076, - vgt_perf_vs_thread_groups__VI = 0x00000076, - vgt_perf_vs_thread_groups__SI__CI = 0x00000077, - vgt_perf_ls_done_latency__VI = 0x00000077, - vgt_perf_ls_done_latency__SI__CI = 0x00000078, - vgt_perf_hs_done_latency__VI = 0x00000078, - vgt_perf_hs_done_latency__SI__CI = 0x00000079, - vgt_perf_es_done_latency__VI = 0x00000079, - vgt_perf_es_done_latency__SI__CI = 0x0000007a, - vgt_perf_gs_done_latency__VI = 0x0000007a, - vgt_perf_gs_done_latency__SI__CI = 0x0000007b, - vgt_perf_vgt_hs_busy__VI = 0x0000007b, - vgt_perf_vgt_hs_busy__SI__CI = 0x0000007c, - vgt_perf_vgt_te11_busy__VI = 0x0000007c, - vgt_perf_vgt_te11_busy__SI__CI = 0x0000007d, - vgt_perf_ls_flush__VI = 0x0000007d, - vgt_perf_ls_flush__SI__CI = 0x0000007e, - vgt_perf_hs_flush__VI = 0x0000007e, - vgt_perf_hs_flush__SI__CI = 0x0000007f, - vgt_perf_es_flush__VI = 0x0000007f, - vgt_perf_es_flush__SI__CI = 0x00000080, - vgt_perf_vgt_pa_clipp_eopg__VI = 0x00000080, - vgt_perf_gs_flush__SI__CI = 0x00000081, - vgt_perf_ls_done__VI = 0x00000081, - vgt_perf_ls_done__SI__CI = 0x00000082, - vgt_perf_hs_done__VI = 0x00000082, - vgt_perf_hs_done__SI__CI = 0x00000083, - vgt_perf_es_done__VI = 0x00000083, - vgt_perf_es_done__SI__CI = 0x00000084, - vgt_perf_gs_done__VI = 0x00000084, - vgt_perf_gs_done__SI__CI = 0x00000085, - vgt_perf_vsfetch_done__VI = 0x00000085, - vgt_perf_vsfetch_done__SI__CI = 0x00000086, - vgt_perf_gs_done_received__VI = 0x00000086, - vgt_perf_RESERVED12__SI = 0x00000087, - vgt_perf_RESERVED2__CI = 0x00000087, - vgt_perf_es_ring_high_water_mark__VI = 0x00000087, - vgt_perf_es_ring_high_water_mark__SI__CI = 0x00000088, - vgt_perf_gs_ring_high_water_mark__VI = 0x00000088, - vgt_perf_gs_ring_high_water_mark__SI__CI = 0x00000089, - vgt_perf_vs_table_high_water_mark__VI = 0x00000089, - vgt_perf_vs_table_high_water_mark__SI__CI = 0x0000008a, - vgt_perf_hs_tgs_active_high_water_mark__VI = 0x0000008a, - vgt_perf_hs_tgs_active_high_water_mark__SI__CI = 0x0000008b, - vgt_perf_pa_clipp_dealloc__VI = 0x0000008b, - vgt_perf_cut_mem_flush_stalled__VI = 0x0000008c, - vgt_perf_vsvert_work_received__VI = 0x0000008d, - vgt_perf_vgt_pa_clipp_starved_after_work__VI = 0x0000008e, - vgt_perf_te11_con_starved_after_work__VI = 0x0000008f, - vgt_perf_hs_waiting_on_ls_done_stall__VI = 0x00000090, - vgt_spi_vsvert_valid__VI = 0x00000091, -} VGT_PERFCOUNT_SELECT; - -typedef enum VGT_RDREQ_POLICY { - VGT_POLICY_LRU = 0x00000000, - VGT_POLICY_STREAM = 0x00000001, - VGT_POLICY_BYPASS__SI__CI = 0x00000002, - VGT_POLICY_RESERVED__SI__CI = 0x00000003, -} VGT_RDREQ_POLICY; - -typedef enum VGT_STAGES_ES_EN { - ES_STAGE_OFF = 0x00000000, - ES_STAGE_DS = 0x00000001, - ES_STAGE_REAL = 0x00000002, - RESERVED_ES = 0x00000003, -} VGT_STAGES_ES_EN; - -typedef enum VGT_STAGES_GS_EN { - GS_STAGE_OFF = 0x00000000, - GS_STAGE_ON = 0x00000001, -} VGT_STAGES_GS_EN; - -typedef enum VGT_STAGES_HS_EN { - HS_STAGE_OFF = 0x00000000, - HS_STAGE_ON = 0x00000001, -} VGT_STAGES_HS_EN; - -typedef enum VGT_STAGES_LS_EN { - LS_STAGE_OFF = 0x00000000, - LS_STAGE_ON = 0x00000001, - CS_STAGE_ON = 0x00000002, - RESERVED_LS = 0x00000003, -} VGT_STAGES_LS_EN; - -typedef enum VGT_STAGES_VS_EN { - VS_STAGE_REAL = 0x00000000, - VS_STAGE_DS = 0x00000001, - VS_STAGE_COPY_SHADER = 0x00000002, - RESERVED_VS = 0x00000003, -} VGT_STAGES_VS_EN; - -typedef enum VGT_TESS_PARTITION { - PART_INTEGER = 0x00000000, - PART_POW2 = 0x00000001, - PART_FRAC_ODD = 0x00000002, - PART_FRAC_EVEN = 0x00000003, -} VGT_TESS_PARTITION; - -typedef enum VGT_TESS_TOPOLOGY { - OUTPUT_POINT = 0x00000000, - OUTPUT_LINE = 0x00000001, - OUTPUT_TRIANGLE_CW = 0x00000002, - OUTPUT_TRIANGLE_CCW = 0x00000003, -} VGT_TESS_TOPOLOGY; - -typedef enum VGT_TESS_TYPE { - TESS_ISOLINE = 0x00000000, - TESS_TRIANGLE = 0x00000001, - TESS_QUAD = 0x00000002, -} VGT_TESS_TYPE; - -typedef enum VTX_CLAMP { - VTX_Clamp_ClampToZero = 0x00000000, - VTX_Clamp_ClampToNAN = 0x00000001, -} VTX_CLAMP; - -typedef enum VTX_FETCH_TYPE { - VTX_FetchType_VertexData = 0x00000000, - VTX_FetchType_InstanceData = 0x00000001, - VTX_FetchType_NoIndexOffset = 0x00000002, - VTX_FetchType_RESERVED_3 = 0x00000003, -} VTX_FETCH_TYPE; - -typedef enum VTX_FORMAT_COMP_ALL { - VTX_FormatCompAll_Unsigned = 0x00000000, - VTX_FormatCompAll_Signed = 0x00000001, -} VTX_FORMAT_COMP_ALL; - -typedef enum VTX_MEM_REQUEST_SIZE { - VTX_MemRequestSize_32B = 0x00000000, - VTX_MemRequestSize_64B = 0x00000001, -} VTX_MEM_REQUEST_SIZE; - -typedef enum WD_IA_DRAW_TYPE { - WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, - WD_IA_DRAW_TYPE_DI_MM1 = 0x00000001, - WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, - WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, - WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, - WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, - WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, - WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, -} WD_IA_DRAW_TYPE; - -typedef enum WD_PERFCOUNT_SELECT { - wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00000000, - wd_perf_RBIU_DR_FIFO_STARVED = 0x00000001, - wd_perf_RBIU_DR_FIFO_STALLED = 0x00000002, - wd_perf_RBIU_DI_FIFO_STARVED = 0x00000003, - wd_perf_RBIU_DI_FIFO_STALLED = 0x00000004, - wd_perf_wd_busy = 0x00000005, - wd_perf_wd_sclk_reg_vld_event = 0x00000006, - wd_perf_wd_sclk_input_vld_event = 0x00000007, - wd_perf_wd_sclk_core_vld_event = 0x00000008, - wd_perf_wd_stalled = 0x00000009, - wd_perf_inside_tf_bin_0__VI = 0x0000000a, - wd_perf_inside_tf_bin_1__VI = 0x0000000b, - wd_perf_inside_tf_bin_2__VI = 0x0000000c, - wd_perf_inside_tf_bin_3__VI = 0x0000000d, - wd_perf_inside_tf_bin_4__VI = 0x0000000e, - wd_perf_inside_tf_bin_5__VI = 0x0000000f, - wd_perf_inside_tf_bin_6__VI = 0x00000010, - wd_perf_inside_tf_bin_7__VI = 0x00000011, - wd_perf_inside_tf_bin_8__VI = 0x00000012, - wd_perf_tfreq_lat_bin_0__VI = 0x00000013, - wd_perf_tfreq_lat_bin_1__VI = 0x00000014, - wd_perf_tfreq_lat_bin_2__VI = 0x00000015, - wd_perf_tfreq_lat_bin_3__VI = 0x00000016, - wd_perf_tfreq_lat_bin_4__VI = 0x00000017, - wd_perf_tfreq_lat_bin_5__VI = 0x00000018, - wd_perf_tfreq_lat_bin_6__VI = 0x00000019, - wd_perf_tfreq_lat_bin_7__VI = 0x0000001a, - wd_starved_on_hs_done__VI = 0x0000001b, - wd_perf_se0_hs_done_latency__VI = 0x0000001c, - wd_perf_se1_hs_done_latency__VI = 0x0000001d, - wd_perf_se2_hs_done_latency__VI = 0x0000001e, - wd_perf_se3_hs_done_latency__VI = 0x0000001f, - wd_perf_hs_done_se0__VI = 0x00000020, - wd_perf_hs_done_se1__VI = 0x00000021, - wd_perf_hs_done_se2__VI = 0x00000022, - wd_perf_hs_done_se3__VI = 0x00000023, - wd_perf_null_patches__VI = 0x00000024, -} WD_PERFCOUNT_SELECT; - -typedef enum ZFormat { - Z_INVALID = 0x00000000, - Z_16 = 0x00000001, - Z_24 = 0x00000002, - Z_32_FLOAT = 0x00000003, -} ZFormat; - -typedef enum ZLimitSumm { - FORCE_SUMM_OFF = 0x00000000, - FORCE_SUMM_MINZ = 0x00000001, - FORCE_SUMM_MAXZ = 0x00000002, - FORCE_SUMM_BOTH = 0x00000003, -} ZLimitSumm; - -typedef enum ZModeForce { - NO_FORCE = 0x00000000, - FORCE_EARLY_Z = 0x00000001, - FORCE_LATE_Z = 0x00000002, - FORCE_RE_Z = 0x00000003, -} ZModeForce; - -typedef enum ZOrder { - LATE_Z = 0x00000000, - EARLY_Z_THEN_LATE_Z = 0x00000001, - RE_Z = 0x00000002, - EARLY_Z_THEN_RE_Z = 0x00000003, -} ZOrder; - -typedef enum ZSamplePosition { - Z_SAMPLE_CENTER = 0x00000000, - Z_SAMPLE_CENTROID = 0x00000001, -} ZSamplePosition; - -typedef enum ZpassControl { - ZPASS_DISABLE = 0x00000000, - ZPASS_SAMPLES = 0x00000001, - ZPASS_PIXELS = 0x00000002, -} ZpassControl; - - -// Merged Enumerations -typedef enum CmaskAddr { - CMASK_ADDR_TILED = 0x00000000, - CMASK_ADDR_LINEAR = 0x00000001, - CMASK_ADDR_COMPATIBLE = 0x00000002, -} CmaskAddr; - -typedef enum ColorTransform { - DCC_CT_AUTO = 0x00000000, - DCC_CT_NONE = 0x00000001, - ABGR_TO_A_BG_G_RB = 0x00000002, - BGRA_TO_BG_G_RB_A = 0x00000003, -} ColorTransform; - -typedef enum ENUM_NUM_SIMD_PER_CU { - NUM_SIMD_PER_CU = 0x00000004, -} ENUM_NUM_SIMD_PER_CU; - -typedef enum GATCL1RequestType { - GATCL1_TYPE_NORMAL = 0x00000000, - GATCL1_TYPE_SHOOTDOWN = 0x00000001, - GATCL1_TYPE_BYPASS = 0x00000002, -} GATCL1RequestType; - -typedef enum MTYPE { - MTYPE_NC_NV = 0x00000000, - MTYPE_NC = 0x00000001, - MTYPE_CC = 0x00000002, - MTYPE_UC = 0x00000003, -} MTYPE; - -typedef enum SEM_PERF_SEL { - SEM_PERF_SEL_CYCLE = 0x00000000, - SEM_PERF_SEL_IDLE = 0x00000001, - SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, - SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, - SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004, - SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005, - SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006, - SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007, - SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008, - SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009, - SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a, - SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b, - SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c, - SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d, - SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e, - SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f, - SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010, - SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011, - SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012, - SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013, - SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014, - SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015, - SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016, - SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017, - SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018, - SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019, - SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a, - SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b, - SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c, - SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d, - SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e, - SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f, - SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020, - SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021, - SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022, - SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023, - SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024, - SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025, - SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026, - SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027, - SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028, - SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029, - SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a, - SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b, - SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c, - SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d, - SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e, - SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f, - SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030, - SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031, - SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032, - SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033, - SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034, - SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035, - SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036, - SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037, - SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038, - SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039, - SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a, - SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b, - SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c, - SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d, - SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e, - SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f, - SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040, - SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041, - SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042, - SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043, - SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044, - SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045, - SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046, - SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047, - SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048, - SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049, - SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a, - SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b, - SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c, - SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d, - SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e, - SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f, - SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050, - SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051, - SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052, - SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053, - SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054, - SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055, - SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056, - SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057, - SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058, - SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059, - SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a, - SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b, - SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c, - SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d, - SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e, - SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f, - SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060, - SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061, - SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062, - SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063, - SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064, - SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065, - SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066, - SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067, - SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068, - SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069, - SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a, - SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b, - SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c, - SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d, - SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e, - SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f, - SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070, - SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071, - SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072, - SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073, - SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074, - SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075, - SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076, - SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077, - SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078, - SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079, - SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a, - SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b, - SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c, - SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d, - SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e, - SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f, - SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080, - SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081, - SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082, - SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083, - SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084, - SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085, - SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086, - SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087, - SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088, - SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089, - SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a, - SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b, - SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c, - SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d, - SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e, - SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f, - SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090, - SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091, - SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092, - SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093, - SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094, - SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095, - SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096, - SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097, - SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098, - SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099, - SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a, - SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b, - SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c, - SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d, - SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e, - SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f, - SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0, - SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1, - SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2, - SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3, - SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4, - SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5, - SEM_PERF_SEL_MC_RD_REQ = 0x000000a6, - SEM_PERF_SEL_MC_RD_RET = 0x000000a7, - SEM_PERF_SEL_MC_WR_REQ = 0x000000a8, - SEM_PERF_SEL_MC_WR_RET = 0x000000a9, - SEM_PERF_SEL_ATC_REQ = 0x000000aa, - SEM_PERF_SEL_ATC_RET = 0x000000ab, - SEM_PERF_SEL_ATC_XNACK = 0x000000ac, - SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad, -} SEM_PERF_SEL; - -typedef enum SH_MEM_ADDRESS_MODE { - SH_MEM_ADDRESS_MODE_GPUVM64 = 0x00000000, - SH_MEM_ADDRESS_MODE_GPUVM32 = 0x00000001, - SH_MEM_ADDRESS_MODE_HSA64 = 0x00000002, - SH_MEM_ADDRESS_MODE_HSA32 = 0x00000003, -} SH_MEM_ADDRESS_MODE; - -typedef enum SQ_EDC_INFO_SOURCE { - SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, - SQ_EDC_INFO_SOURCE_INST = 0x00000001, - SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, - SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, - SQ_EDC_INFO_SOURCE_LDS = 0x00000004, - SQ_EDC_INFO_SOURCE_GDS = 0x00000005, - SQ_EDC_INFO_SOURCE_TA = 0x00000006, -} SQ_EDC_INFO_SOURCE; - -typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { - SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018, - SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019, -} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; - -typedef enum SRBM_GFX_CNTL_SEL { - SRBM_GFX_CNTL_BIF = 0x00000000, - SRBM_GFX_CNTL_SDMA0 = 0x00000001, - SRBM_GFX_CNTL_SDMA1 = 0x00000002, - SRBM_GFX_CNTL_GRBM = 0x00000003, - SRBM_GFX_CNTL_UVD = 0x00000004, - SRBM_GFX_CNTL_VCE0 = 0x00000005, - SRBM_GFX_CNTL_VCE1 = 0x00000006, - SRBM_GFX_CNTL_ACP = 0x00000007, - SRBM_GFX_CNTL_SMU = 0x00000008, - SRBM_GFX_CNTL_SAMMSP = 0x00000009, - SRBM_GFX_CNTL_SAMSCP = 0x0000000a, - SRBM_GFX_CNTL_ISP = 0x0000000b, - SRBM_GFX_CNTL_TST = 0x0000000c, - SRBM_GFX_CNTL_SDMA2 = 0x0000000d, - SRBM_GFX_CNTL_SDMA3 = 0x0000000e, - SRBM_GFX_CNTL_DRM = 0x0000000f, -} SRBM_GFX_CNTL_SEL; - -typedef enum SX_BLEND_OPT { - BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, - BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, - BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, - BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, - BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, - BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, - BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, - BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, -} SX_BLEND_OPT; - -typedef enum SX_DOWNCONVERT_FORMAT { - SX_RT_EXPORT_NO_CONVERSION = 0x00000000, - SX_RT_EXPORT_32_R = 0x00000001, - SX_RT_EXPORT_32_A = 0x00000002, - SX_RT_EXPORT_10_11_11 = 0x00000003, - SX_RT_EXPORT_2_10_10_10 = 0x00000004, - SX_RT_EXPORT_8_8_8_8 = 0x00000005, - SX_RT_EXPORT_5_6_5 = 0x00000006, - SX_RT_EXPORT_1_5_5_5 = 0x00000007, - SX_RT_EXPORT_4_4_4_4 = 0x00000008, - SX_RT_EXPORT_16_16_GR = 0x00000009, - SX_RT_EXPORT_16_16_AR = 0x0000000a, -} SX_DOWNCONVERT_FORMAT; - -typedef enum SX_OPT_COMB_FCN { - OPT_COMB_NONE = 0x00000000, - OPT_COMB_ADD = 0x00000001, - OPT_COMB_SUBTRACT = 0x00000002, - OPT_COMB_MIN = 0x00000003, - OPT_COMB_MAX = 0x00000004, - OPT_COMB_REVSUBTRACT = 0x00000005, - OPT_COMB_BLEND_DISABLED = 0x00000006, - OPT_COMB_SAFE_ADD = 0x00000007, -} SX_OPT_COMB_FCN; - -typedef enum SYS_GRBM_GFX_INDEX_SEL { - GRBM_GFX_INDEX_BIF = 0x00000000, - GRBM_GFX_INDEX_SDMA0 = 0x00000001, - GRBM_GFX_INDEX_SDMA1 = 0x00000002, - RESEVERED0 = 0x00000003, - GRBM_GFX_INDEX_UVD = 0x00000004, - GRBM_GFX_INDEX_VCE0 = 0x00000005, - GRBM_GFX_INDEX_VCE1 = 0x00000006, - GRBM_GFX_INDEX_ACP = 0x00000007, - GRBM_GFX_INDEX_SMU = 0x00000008, - GRBM_GFX_INDEX_SAMMSP = 0x00000009, - GRBM_GFX_INDEX_SAMSCP = 0x0000000a, - GRBM_GFX_INDEX_ISP = 0x0000000b, - GRBM_GFX_INDEX_TST = 0x0000000c, - GRBM_GFX_INDEX_SDMA2 = 0x0000000d, - GRBM_GFX_INDEX_SDMA3 = 0x0000000e, - GRBM_GFX_INDEX_DRM = 0x0000000f, -} SYS_GRBM_GFX_INDEX_SEL; - -typedef enum TCP_DSM_DATA_SEL { - TCP_DSM_DISABLE = 0x00000000, - TCP_DSM_SEL0 = 0x00000001, - TCP_DSM_SEL1 = 0x00000002, - TCP_DSM_SEL_BOTH = 0x00000003, -} TCP_DSM_DATA_SEL; - -typedef enum TCP_DSM_SINGLE_WRITE { - TCP_DSM_SINGLE_WRITE_DIS = 0x00000000, - TCP_DSM_SINGLE_WRITE_EN = 0x00000001, -} TCP_DSM_SINGLE_WRITE; - -typedef enum VGT_DIST_MODE { - NO_DIST = 0x00000000, - PATCHES = 0x00000001, - DONUTS = 0x00000002, -} VGT_DIST_MODE; - -typedef enum WD_IA_DRAW_SOURCE { - WD_IA_DRAW_SOURCE_DMA = 0x00000000, - WD_IA_DRAW_SOURCE_IMMD = 0x00000001, - WD_IA_DRAW_SOURCE_AUTO = 0x00000002, - WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, -} WD_IA_DRAW_SOURCE; - - -// Merged Defines -#define CCREG_SADR__SI 0x00000020 -#define CCREG_SIZE__SI 0x00000040 -#define CG_SRBM_END_ADDR__CI__VI 0x000008ff -#define CG_SRBM_END_ADDR__SI 0x00000900 -#define CG_SRBM_START_ADDR 0x00000600 -#define CMEM_SADR__SI 0x00000080 -#define CMEM_SIZE__SI 0x00000071 -#define CONFIG_SPACE1_END__CI__VI 0x00002bff -#define CONFIG_SPACE1_START__CI__VI 0x00002000 -#define CONFIG_SPACE2_END__CI__VI 0x00009fff -#define CONFIG_SPACE2_START__CI__VI 0x00003000 -#define CONFIG_SPACE_END__CI__VI 0x00009fff -#define CONFIG_SPACE_END__SI 0x000033ff -#define CONFIG_SPACE_START 0x00002000 -#define CONTEXT_SPACE_END__CI__VI 0x0000bfff -#define CONTEXT_SPACE_END__SI 0x0000afff -#define CONTEXT_SPACE_START 0x0000a000 -#define CSDATA_ADDR_WIDTH__CI__VI 0x00000007 -#define CSDATA_DATA_WIDTH__CI__VI 0x00000020 -#define CSDATA_TYPE_WIDTH__CI__VI 0x00000002 -#define DMREG_SADR__SI 0x00000000 -#define DMREG_SIZE__SI 0x0000001e -#define GB_TILING_CONFIG_MACROTABLE_SIZE__CI__VI 0x00000010 -#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020 -#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA -#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR -#define GL__DST_ALPHA BLEND_DST_ALPHA -#define GL__DST_COLOR BLEND_DST_COLOR -#define GL__ONE BLEND_ONE -#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA -#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR -#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA -#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR -#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA -#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR -#define GL__SRC_ALPHA BLEND_SRC_ALPHA -#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE -#define GL__SRC_COLOR BLEND_SRC_COLOR -#define GL__ZERO BLEND_ZERO -#define GPG_DISABLE_ROM__SI 0x00000001 -#define GPG_SMC_SRAM__SI 0x00000001 -#define GPG_WB_SRBM_TRANSLATE__SI 0x00000001 -#define GSTHREADID_SIZE 0x00000002 -#define HDCP_KEY_EADR__CI 0x000001ff -#define HDCP_KEY_SADR__CI 0x000000e1 -#define INDREG_SADR__SI 0x00000200 -#define INST_ID_ECC_INTERRUPT_MSG__CI__VI 0xfffffff0 -#define INST_ID_HOST_REG_TRAP_MSG__CI__VI 0xfffffffe -#define INST_ID_HW_TRAP__CI__VI 0xfffffff2 -#define INST_ID_KILL_SEQ__CI__VI 0xfffffff3 -#define INST_ID_TTRACE_NEW_PC_MSG__CI__VI 0xfffffff1 -#define IQ_DEQUEUE_RETRY__CI__VI 0x00000004 -#define IQ_INTR_TYPE_IB__CI__VI 0x00000001 -#define IQ_INTR_TYPE_MQD__CI__VI 0x00000002 -#define IQ_INTR_TYPE_PQ__CI__VI 0x00000000 -#define IQ_OFFLOAD_RETRY__CI__VI 0x00000001 -#define IQ_QUEUE_SLEEP__CI__VI 0x00000000 -#define IQ_SCH_WAVE_MSG__CI__VI 0x00000002 -#define IQ_SEM_REARM__CI__VI 0x00000003 -#define KEYS_CHAIN_ADR__CI 0x00000000 -#define PERSISTENT_SPACE_END 0x00002fff -#define PERSISTENT_SPACE_START 0x00002c00 -#define RCU_CCF_BITS0__CI 0x00000500 -#define RCU_CCF_BITS1__CI 0x00001000 -#define RCU_CCF_BITS__SI 0x00000508 -#define RCU_CCF_BYTES__SI 0x000000a1 -#define RCU_CCF_DWORDS0__CI 0x00000028 -#define RCU_CCF_DWORDS1__CI 0x0000007f -#define RCU_CCF_EADR__SI 0x000000a0 -#define RCU_CCF_SADR__SI 0x00000000 -#define RCU_DRM_BYTES__SI 0x00000011 -#define RCU_DRM_EADR__SI 0x000000b1 -#define RCU_DRM_SADR__SI 0x000000a1 -#define RCU_HDCP_BYTES__CI__VI 0x0000011f -#define RCU_HDCP_RTL_BYTES__CI__VI 0x0000011f -#define RCU_HDC_BYTES__SI 0x0000011f -#define RCU_HDC_EADR__SI 0x000001ff -#define RCU_HDC_SADR__SI 0x000000e1 -#define RCU_SAM_BYTES__CI 0x00000040 -#define RCU_SAM_RTL_BYTES__CI 0x00000040 -#define RCU_SECURE_DWORDS0__CI 0x00000058 -#define RCU_SECURE_DWORDS1__CI 0x00000001 -#define RCU_SMU_BYTES__CI__VI 0x00000011 -#define RCU_SMU_RTL_BYTES__CI__VI 0x00000011 -#define RCU_SRBM_END_ADDR__SI 0x00000060 -#define RCU_SRBM_START_ADDR__SI 0x00000040 -#define RCU_UVD_BYTES__SI 0x0000002f -#define RCU_UVD_EADR__SI 0x000000e0 -#define RCU_UVD_SADR__SI 0x000000b2 -#define ROM_SIGNATURE 0x0000aa55 -#define ROM_SRBM_END_ADDR__SI 0x000005ff -#define ROM_SRBM_START_ADDR__SI 0x00000580 -#define SAMU_KEY_EADR__CI 0x000000e0 -#define SAMU_KEY_SADR__CI 0x000000a1 -#define SEM_ECC_ERROR__CI__VI 0x00000000 -#define SEM_FAILED__CI__VI 0x00000002 -#define SEM_PASSED__CI__VI 0x00000003 -#define SEM_RESERVED__CI__VI 0x00000001 -#define SMC_BRIDGE_ADDR_BITS__SI 0x0000001e -#define SMC_BRIDGE_END_ADDR__SI 0xffffffff -#define SMC_BRIDGE_START_ADDR__SI 0xc0000000 -#define SMC_CG_ADDR_BITS__SI 0x00000010 -#define SMC_CG_END_ADDR__SI 0xc000ffff -#define SMC_CG_IND_ADDR_BITS__SI 0x00000010 -#define SMC_CG_IND_END_ADDR__SI 0xc003ffff -#define SMC_CG_IND_START_ADDR__SI 0xc0030000 -#define SMC_CG_START_ADDR__SI 0xc0000000 -#define SMC_CMN_ADDR_BITS__SI 0x0000001e -#define SMC_CMN_END_ADDR__SI 0xbfffffff -#define SMC_CMN_START_ADDR__SI 0x80000000 -#define SMC_DMA_ADDR_BITS__SI 0x0000000b -#define SMC_DMA_END_ADDR__SI 0x80011fff -#define SMC_DMA_START_ADDR__SI 0x80011800 -#define SMC_DRAM_CNTL_ADDR_BITS__SI 0x0000000a -#define SMC_DRAM_CNTL_END_ADDR__SI 0x000203ff -#define SMC_DRAM_CNTL_LOG2_RD_FIFO_SIZE__SI 0x00000001 -#define SMC_DRAM_CNTL_LOG2_WR_FIFO_SIZE__SI 0x00000002 -#define SMC_DRAM_CNTL_MC_ADDR_SIZE__SI 0x00000028 -#define SMC_DRAM_CNTL_MC_RD_ADDR_LSB__SI 0x00000008 -#define SMC_DRAM_CNTL_MC_WR_ADDR_LSB__SI 0x00000005 -#define SMC_DRAM_CNTL_RD_FIFO_SIZE_2__SI 0x00000002 -#define SMC_DRAM_CNTL_RD_FIFO_SIZE__SI 0x00000002 -#define SMC_DRAM_CNTL_START_ADDR__SI 0x00020000 -#define SMC_DRAM_CNTL_WR_FIFO_SIZE_4__SI 0x00000004 -#define SMC_DRAM_CNTL_WR_FIFO_SIZE__SI 0x00000004 -#define SMC_FUSION_ADDR_BITS__SI 0x0000001d -#define SMC_FUSION_END_ADDR__SI 0xffffffff -#define SMC_FUSION_START_ADDR__SI 0xe0000000 -#define SMC_GPG_ADDR_BITS__SI 0x0000001d -#define SMC_GPG_END_ADDR__SI 0xdfffffff -#define SMC_GPG_START_ADDR__SI 0xc0000000 -#define SMC_GPIO_START_ADDR__SI 0x80000200 -#define SMC_HEADER_SIZE__CI__VI 0x00000040 -#define SMC_INC_GPIO_IN__SI 0x00000001 -#define SMC_INC_GPIO_OUT__SI 0x00000001 -#define SMC_INTR_CNTL_ADDR_BITS__SI 0x0000000b -#define SMC_INTR_CNTL_END_ADDR__SI 0x800107ff -#define SMC_INTR_CNTL_SIZE__SI 0x00000006 -#define SMC_INTR_CNTL_START_ADDR__SI 0x80010000 -#define SMC_LM32CFG_START_ADDR__SI 0x80000000 -#define SMC_MBUS2CFG_START_ADDR__SI 0x80000100 -#define SMC_MBUS2_ARB_PRI_MAX__SI 0x00000004 -#define SMC_MBUS2_ARB_PRI_WIDTH__SI 0x00000003 -#define SMC_MBUS2_MASTERS__SI 0x00000005 -#define SMC_MBUS2_SLAVES__SI 0x0000000a -#define SMC_MEM_ADDR_BITS__SI 0x0000001f -#define SMC_MEM_END_ADDR__SI 0x7fffffff -#define SMC_MEM_START_ADDR__SI 0x00000000 -#define SMC_MSG_ADJUST_LOADLINE__CI__VI 0x00000018 -#define SMC_MSG_CASCADE_PLL_OFF__CI__VI 0x00000006 -#define SMC_MSG_CASCADE_PLL_ON__CI__VI 0x00000007 -#define SMC_MSG_CONFIG_BAPM__CI__VI 0x0000000d -#define SMC_MSG_CONFIG_HTC_LIMIT__CI__VI 0x00000010 -#define SMC_MSG_CONFIG_LCLK_DPM__CI__VI 0x00000009 -#define SMC_MSG_CONFIG_LOADLINE__CI__VI 0x00000017 -#define SMC_MSG_CONFIG_LPMx__CI__VI 0x0000000f -#define SMC_MSG_CONFIG_NBDPM__CI__VI 0x00000016 -#define SMC_MSG_CONFIG_TDC_LIMIT__CI__VI 0x0000000e -#define SMC_MSG_CONFIG_TDP_CNTL__CI__VI 0x00000013 -#define SMC_MSG_CONFIG_THERMAL_CNTL__CI__VI 0x00000011 -#define SMC_MSG_CONFIG_VOLTAGE_CNTL__CI__VI 0x00000012 -#define SMC_MSG_CONFIG_VPC_ACCUMULATOR__CI__VI 0x0000000c -#define SMC_MSG_DDI_PHY_OFF__CI__VI 0x00000004 -#define SMC_MSG_DDI_PHY_ON__CI__VI 0x00000005 -#define SMC_MSG_DIS_PM_CNTL__CI__VI 0x00000015 -#define SMC_MSG_EN_PM_CNTL__CI__VI 0x00000014 -#define SMC_MSG_FLUSH_DATA_CACHE__CI__VI 0x0000000a -#define SMC_MSG_FLUSH_INSTRUCTION_CACHE__CI__VI 0x0000000b -#define SMC_MSG_PHY_LN_OFF__CI__VI 0x00000002 -#define SMC_MSG_PHY_LN_ON__CI__VI 0x00000003 -#define SMC_MSG_PWR_OFF_x16__CI__VI 0x00000008 -#define SMC_MSG_RESET__CI__VI 0x00000020 -#define SMC_MSG_TEST__CI__VI 0x00000001 -#define SMC_MSG_VOLTAGE__CI__VI 0x00000025 -#define SMC_NUM_COUNTERS__SI 0x00000008 -#define SMC_NUM_GPIO_IN__SI 0x00000001 -#define SMC_NUM_GPIO_OUT__SI 0x00000001 -#define SMC_NUM_OCMP_REG__SI 0x00000004 -#define SMC_RAMS_LOG2__SI 0x00000005 -#define SMC_RAM_ADDR_BITS__SI 0x00000010 -#define SMC_RAM_END_ADDR__SI 0x0001ffff -#define SMC_RAM_START_ADDR__SI 0x00010000 -#define SMC_RCU_ADDR_BITS__SI 0x00000010 -#define SMC_RCU_END_ADDR__SI 0xc001ffff -#define SMC_RCU_START_ADDR__SI 0xc0010000 -#define SMC_ROM_ADDR_BITS__SI 0x00000010 -#define SMC_ROM_END_ADDR__SI 0x0000ffff -#define SMC_ROM_START_ADDR__SI 0x00000000 -#define SMC_SMU_ROM_ADDR_BITS__SI 0x00000010 -#define SMC_SMU_ROM_END_ADDR__SI 0xc002ffff -#define SMC_SMU_ROM_START_ADDR__SI 0xc0020000 -#define SMC_SRBM_ADDR_BITS__SI 0x00000013 -#define SMC_SRBM_CREDIT_FIFO_DEPTH__SI 0x00000010 -#define SMC_SRBM_END_ADDR__SI 0x800fffff -#define SMC_SRBM_START_ADDR__SI 0x80080000 -#define SMC_SYSCON_ADDR_BITS__SI 0x00000010 -#define SMC_SYSCON_END_ADDR__SI 0x8000ffff -#define SMC_SYSCON_START_ADDR__SI 0x80000000 -#define SMC_TIMER_ADDR_BITS__SI 0x0000000b -#define SMC_TIMER_END_ADDR__SI 0x80010fff -#define SMC_TIMER_START_ADDR__SI 0x80010800 -#define SMC_UART_ADDR_BITS__SI 0x0000000b -#define SMC_UART_END_ADDR__SI 0x800117ff -#define SMC_UART_START_ADDR__SI 0x80011000 -#define SMC_VERSION_MAJOR__CI__VI 0x00000007 -#define SMC_VERSION_MINOR__CI__VI 0x00000000 -#define SQDEC_BEGIN 0x00002300 -#define SQDEC_END 0x000023ff -#define SQGFXUDEC_BEGIN__CI 0x0000c340 -#define SQGFXUDEC_END__CI__VI 0x0000c380 -#define SQIND_GLOBAL_REGS_OFFSET 0x00000000 -#define SQIND_GLOBAL_REGS_SIZE 0x00000008 -#define SQIND_LOCAL_REGS_OFFSET 0x00000008 -#define SQIND_LOCAL_REGS_SIZE 0x00000008 -#define SQIND_WAVE_HWREGS_OFFSET 0x00000010 -#define SQIND_WAVE_HWREGS_SIZE 0x000001f0 -#define SQIND_WAVE_SGPRS_OFFSET 0x00000200 -#define SQIND_WAVE_SGPRS_SIZE 0x00000200 -#define SQPERFDDEC_BEGIN__CI__VI 0x0000d1c0 -#define SQPERFDDEC_END__CI__VI 0x0000d240 -#define SQPERFSDEC_BEGIN__CI__VI 0x0000d9c0 -#define SQPERFSDEC_END__CI__VI 0x0000da40 -#define SQPWRDEC_BEGIN__CI__VI 0x0000f08c -#define SQPWRDEC_END__CI__VI 0x0000f094 -#define SQ_ATTR0 0x00000000 -#define SQ_BUFFER_ATOMIC_FCMPSWAP__SI__CI 0x0000003e -#define SQ_BUFFER_ATOMIC_FCMPSWAP_X2__SI__CI 0x0000005e -#define SQ_BUFFER_ATOMIC_FMAX__SI__CI 0x00000040 -#define SQ_BUFFER_ATOMIC_FMAX_X2__SI__CI 0x00000060 -#define SQ_BUFFER_ATOMIC_FMIN__SI__CI 0x0000003f -#define SQ_BUFFER_ATOMIC_FMIN_X2__SI__CI 0x0000005f -#define SQ_BUFFER_ATOMIC_RSUB_X2__SI 0x00000054 -#define SQ_BUFFER_ATOMIC_RSUB__SI 0x00000034 -#define SQ_BUFFER_LOAD_DWORDX3__CI 0x0000000f -#define SQ_BUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_BUFFER_STORE_BYTE 0x00000018 -#define SQ_BUFFER_STORE_DWORD 0x0000001c -#define SQ_BUFFER_STORE_DWORDX2 0x0000001d -#define SQ_BUFFER_STORE_DWORDX3__CI 0x0000001f -#define SQ_BUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_BUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_BUFFER_STORE_SHORT 0x0000001a -#define SQ_BUFFER_WBINVL1_SC__SI 0x00000070 -#define SQ_BUFFER_WBINVL1_VOL__CI 0x00000070 -#define SQ_CHAN_W 0x00000003 -#define SQ_CHAN_X 0x00000000 -#define SQ_CHAN_Y 0x00000001 -#define SQ_CHAN_Z 0x00000002 -#define SQ_CNT1 0x00000000 -#define SQ_CNT2 0x00000001 -#define SQ_CNT3 0x00000002 -#define SQ_CNT4 0x00000003 -#define SQ_DFMT_10_10_10_2__SI__CI 0x00000008 -#define SQ_DFMT_10_11_11__SI__CI 0x00000006 -#define SQ_DFMT_11_11_10__SI__CI 0x00000007 -#define SQ_DFMT_16__SI__CI 0x00000002 -#define SQ_DFMT_16_16__SI__CI 0x00000005 -#define SQ_DFMT_16_16_16_16__SI__CI 0x0000000c -#define SQ_DFMT_2_10_10_10__SI__CI 0x00000009 -#define SQ_DFMT_32__SI__CI 0x00000004 -#define SQ_DFMT_32_32__SI__CI 0x0000000b -#define SQ_DFMT_32_32_32__SI__CI 0x0000000d -#define SQ_DFMT_32_32_32_32__SI__CI 0x0000000e -#define SQ_DFMT_8__SI__CI 0x00000001 -#define SQ_DFMT_8_8__SI__CI 0x00000003 -#define SQ_DFMT_8_8_8_8__SI__CI 0x0000000a -#define SQ_DFMT_INVALID__SI__CI 0x00000000 -#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 -#define SQ_DISPATCHER_GFX_MIN 0x00000010 -#define SQ_DS_ADD_RTN_U32 0x00000020 -#define SQ_DS_ADD_RTN_U64 0x00000060 -#define SQ_DS_ADD_SRC2_U32 0x00000080 -#define SQ_DS_ADD_SRC2_U64 0x000000c0 -#define SQ_DS_ADD_U32 0x00000000 -#define SQ_DS_ADD_U64 0x00000040 -#define SQ_DS_AND_B32 0x00000009 -#define SQ_DS_AND_B64 0x00000049 -#define SQ_DS_AND_RTN_B32 0x00000029 -#define SQ_DS_AND_RTN_B64 0x00000069 -#define SQ_DS_AND_SRC2_B32 0x00000089 -#define SQ_DS_AND_SRC2_B64 0x000000c9 -#define SQ_DS_CMPST_B32 0x00000010 -#define SQ_DS_CMPST_B64 0x00000050 -#define SQ_DS_CMPST_F32 0x00000011 -#define SQ_DS_CMPST_F64 0x00000051 -#define SQ_DS_CMPST_RTN_B32 0x00000030 -#define SQ_DS_CMPST_RTN_B64 0x00000070 -#define SQ_DS_CMPST_RTN_F32 0x00000031 -#define SQ_DS_CMPST_RTN_F64 0x00000071 -#define SQ_DS_CONDXCHG32_RTN_B128__CI__VI 0x000000fd -#define SQ_DS_CONDXCHG32_RTN_B64__CI__VI 0x0000007e -#define SQ_DS_DEC_RTN_U32 0x00000024 -#define SQ_DS_DEC_RTN_U64 0x00000064 -#define SQ_DS_DEC_SRC2_U32 0x00000084 -#define SQ_DS_DEC_SRC2_U64 0x000000c4 -#define SQ_DS_DEC_U32 0x00000004 -#define SQ_DS_DEC_U64 0x00000044 -#define SQ_DS_GWS_SEMA_RELEASE_ALL__CI 0x00000018 -#define SQ_DS_INC_RTN_U32 0x00000023 -#define SQ_DS_INC_RTN_U64 0x00000063 -#define SQ_DS_INC_SRC2_U32 0x00000083 -#define SQ_DS_INC_SRC2_U64 0x000000c3 -#define SQ_DS_INC_U32 0x00000003 -#define SQ_DS_INC_U64 0x00000043 -#define SQ_DS_MAX_F32 0x00000013 -#define SQ_DS_MAX_F64 0x00000053 -#define SQ_DS_MAX_I32 0x00000006 -#define SQ_DS_MAX_I64 0x00000046 -#define SQ_DS_MAX_RTN_F32 0x00000033 -#define SQ_DS_MAX_RTN_F64 0x00000073 -#define SQ_DS_MAX_RTN_I32 0x00000026 -#define SQ_DS_MAX_RTN_I64 0x00000066 -#define SQ_DS_MAX_RTN_U32 0x00000028 -#define SQ_DS_MAX_RTN_U64 0x00000068 -#define SQ_DS_MAX_SRC2_F32 0x00000093 -#define SQ_DS_MAX_SRC2_F64 0x000000d3 -#define SQ_DS_MAX_SRC2_I32 0x00000086 -#define SQ_DS_MAX_SRC2_I64 0x000000c6 -#define SQ_DS_MAX_SRC2_U32 0x00000088 -#define SQ_DS_MAX_SRC2_U64 0x000000c8 -#define SQ_DS_MAX_U32 0x00000008 -#define SQ_DS_MAX_U64 0x00000048 -#define SQ_DS_MIN_F32 0x00000012 -#define SQ_DS_MIN_F64 0x00000052 -#define SQ_DS_MIN_I32 0x00000005 -#define SQ_DS_MIN_I64 0x00000045 -#define SQ_DS_MIN_RTN_F32 0x00000032 -#define SQ_DS_MIN_RTN_F64 0x00000072 -#define SQ_DS_MIN_RTN_I32 0x00000025 -#define SQ_DS_MIN_RTN_I64 0x00000065 -#define SQ_DS_MIN_RTN_U32 0x00000027 -#define SQ_DS_MIN_RTN_U64 0x00000067 -#define SQ_DS_MIN_SRC2_F32 0x00000092 -#define SQ_DS_MIN_SRC2_F64 0x000000d2 -#define SQ_DS_MIN_SRC2_I32 0x00000085 -#define SQ_DS_MIN_SRC2_I64 0x000000c5 -#define SQ_DS_MIN_SRC2_U32 0x00000087 -#define SQ_DS_MIN_SRC2_U64 0x000000c7 -#define SQ_DS_MIN_U32 0x00000007 -#define SQ_DS_MIN_U64 0x00000047 -#define SQ_DS_MSKOR_B32 0x0000000c -#define SQ_DS_MSKOR_B64 0x0000004c -#define SQ_DS_MSKOR_RTN_B32 0x0000002c -#define SQ_DS_MSKOR_RTN_B64 0x0000006c -#define SQ_DS_NOP__CI__VI 0x00000014 -#define SQ_DS_OR_B32 0x0000000a -#define SQ_DS_OR_B64 0x0000004a -#define SQ_DS_OR_RTN_B32 0x0000002a -#define SQ_DS_OR_RTN_B64 0x0000006a -#define SQ_DS_OR_SRC2_B32 0x0000008a -#define SQ_DS_OR_SRC2_B64 0x000000ca -#define SQ_DS_READ2ST64_B32 0x00000038 -#define SQ_DS_READ2ST64_B64 0x00000078 -#define SQ_DS_READ2_B32 0x00000037 -#define SQ_DS_READ2_B64 0x00000077 -#define SQ_DS_READ_B128__CI__VI 0x000000ff -#define SQ_DS_READ_B32 0x00000036 -#define SQ_DS_READ_B64 0x00000076 -#define SQ_DS_READ_B96__CI__VI 0x000000fe -#define SQ_DS_READ_I16 0x0000003b -#define SQ_DS_READ_I8 0x00000039 -#define SQ_DS_READ_U16 0x0000003c -#define SQ_DS_READ_U8 0x0000003a -#define SQ_DS_RSUB_RTN_U32 0x00000022 -#define SQ_DS_RSUB_RTN_U64 0x00000062 -#define SQ_DS_RSUB_SRC2_U32 0x00000082 -#define SQ_DS_RSUB_SRC2_U64 0x000000c2 -#define SQ_DS_RSUB_U32 0x00000002 -#define SQ_DS_RSUB_U64 0x00000042 -#define SQ_DS_SUB_RTN_U32 0x00000021 -#define SQ_DS_SUB_RTN_U64 0x00000061 -#define SQ_DS_SUB_SRC2_U32 0x00000081 -#define SQ_DS_SUB_SRC2_U64 0x000000c1 -#define SQ_DS_SUB_U32 0x00000001 -#define SQ_DS_SUB_U64 0x00000041 -#define SQ_DS_WRAP_RTN_B32__CI__VI 0x00000034 -#define SQ_DS_WRITE2ST64_B32 0x0000000f -#define SQ_DS_WRITE2ST64_B64 0x0000004f -#define SQ_DS_WRITE2_B32 0x0000000e -#define SQ_DS_WRITE2_B64 0x0000004e -#define SQ_DS_WRITE_B128__CI__VI 0x000000df -#define SQ_DS_WRITE_B16 0x0000001f -#define SQ_DS_WRITE_B32 0x0000000d -#define SQ_DS_WRITE_B64 0x0000004d -#define SQ_DS_WRITE_B8 0x0000001e -#define SQ_DS_WRITE_B96__CI__VI 0x000000de -#define SQ_DS_WRITE_SRC2_B32 0x0000008d -#define SQ_DS_WRITE_SRC2_B64 0x000000cd -#define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f -#define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f -#define SQ_DS_WRXCHG2_RTN_B32 0x0000002e -#define SQ_DS_WRXCHG2_RTN_B64 0x0000006e -#define SQ_DS_WRXCHG_RTN_B32 0x0000002d -#define SQ_DS_WRXCHG_RTN_B64 0x0000006d -#define SQ_DS_XOR_B32 0x0000000b -#define SQ_DS_XOR_B64 0x0000004b -#define SQ_DS_XOR_RTN_B32 0x0000002b -#define SQ_DS_XOR_RTN_B64 0x0000006b -#define SQ_DS_XOR_SRC2_B32 0x0000008b -#define SQ_DS_XOR_SRC2_B64 0x000000cb -#define SQ_ENC_DS_BITS 0xd8000000 -#define SQ_ENC_DS_FIELD 0x00000036 -#define SQ_ENC_DS_MASK 0xfc000000 -#define SQ_ENC_EXP_MASK 0xfc000000 -#define SQ_ENC_FLAT_BITS__CI__VI 0xdc000000 -#define SQ_ENC_FLAT_FIELD__CI__VI 0x00000037 -#define SQ_ENC_FLAT_MASK__CI__VI 0xfc000000 -#define SQ_ENC_MIMG_BITS 0xf0000000 -#define SQ_ENC_MIMG_FIELD 0x0000003c -#define SQ_ENC_MIMG_MASK 0xfc000000 -#define SQ_ENC_MTBUF_BITS 0xe8000000 -#define SQ_ENC_MTBUF_FIELD 0x0000003a -#define SQ_ENC_MTBUF_MASK 0xfc000000 -#define SQ_ENC_MUBUF_BITS 0xe0000000 -#define SQ_ENC_MUBUF_FIELD 0x00000038 -#define SQ_ENC_MUBUF_MASK 0xfc000000 -#define SQ_ENC_SMRD_BITS__SI__CI 0xc0000000 -#define SQ_ENC_SMRD_FIELD__SI__CI 0x00000018 -#define SQ_ENC_SMRD_MASK__SI__CI 0xf8000000 -#define SQ_ENC_SOP1_BITS 0xbe800000 -#define SQ_ENC_SOP1_FIELD 0x0000017d -#define SQ_ENC_SOP1_MASK 0xff800000 -#define SQ_ENC_SOP2_BITS 0x80000000 -#define SQ_ENC_SOP2_FIELD 0x00000002 -#define SQ_ENC_SOP2_MASK 0xc0000000 -#define SQ_ENC_SOPC_BITS 0xbf000000 -#define SQ_ENC_SOPC_FIELD 0x0000017e -#define SQ_ENC_SOPC_MASK 0xff800000 -#define SQ_ENC_SOPK_BITS 0xb0000000 -#define SQ_ENC_SOPK_FIELD 0x0000000b -#define SQ_ENC_SOPK_MASK 0xf0000000 -#define SQ_ENC_SOPP_BITS 0xbf800000 -#define SQ_ENC_SOPP_FIELD 0x0000017f -#define SQ_ENC_SOPP_MASK 0xff800000 -#define SQ_ENC_VINTRP_MASK 0xfc000000 -#define SQ_ENC_VOP1_BITS 0x7e000000 -#define SQ_ENC_VOP1_FIELD 0x0000003f -#define SQ_ENC_VOP1_MASK 0xfe000000 -#define SQ_ENC_VOP2_BITS 0x00000000 -#define SQ_ENC_VOP2_FIELD 0x00000000 -#define SQ_ENC_VOP2_MASK 0x80000000 -#define SQ_ENC_VOP3_BITS 0xd0000000 -#define SQ_ENC_VOP3_FIELD 0x00000034 -#define SQ_ENC_VOP3_MASK 0xfc000000 -#define SQ_ENC_VOPC_BITS 0x7c000000 -#define SQ_ENC_VOPC_FIELD 0x0000003e -#define SQ_ENC_VOPC_MASK 0xfe000000 -#define SQ_EQ 0x00000002 -#define SQ_EXEC_HI 0x0000007f -#define SQ_EXEC_LO 0x0000007e -#define SQ_EXP 0x00000000 -#define SQ_EXP_GDS0 0x00000018 -#define SQ_EXP_MRT0 0x00000000 -#define SQ_EXP_MRTZ 0x00000008 -#define SQ_EXP_NULL 0x00000009 -#define SQ_EXP_NUM_GDS 0x00000005 -#define SQ_EXP_NUM_MRT 0x00000008 -#define SQ_EXP_NUM_PARAM 0x00000020 -#define SQ_EXP_NUM_POS 0x00000004 -#define SQ_EXP_PARAM0 0x00000020 -#define SQ_EXP_POS0 0x0000000c -#define SQ_EX_MODE_EXCP_ADDR_WATCH__CI__VI 0x00000007 -#define SQ_EX_MODE_EXCP_DIV0__CI__VI 0x00000002 -#define SQ_EX_MODE_EXCP_INEXACT__CI__VI 0x00000005 -#define SQ_EX_MODE_EXCP_INPUT_DENORM__CI__VI 0x00000001 -#define SQ_EX_MODE_EXCP_INT_DIV0__CI__VI 0x00000006 -#define SQ_EX_MODE_EXCP_INVALID__CI__VI 0x00000000 -#define SQ_EX_MODE_EXCP_MEM_VIOL__CI__VI 0x00000008 -#define SQ_EX_MODE_EXCP_OVERFLOW__CI__VI 0x00000003 -#define SQ_EX_MODE_EXCP_UNDERFLOW__CI__VI 0x00000004 -#define SQ_EX_MODE_EXCP_VALU_BASE__CI__VI 0x00000000 -#define SQ_EX_MODE_EXCP_VALU_SIZE__CI__VI 0x00000007 -#define SQ_F 0x00000000 -#define SQ_FLAT_ATOMIC_ADD_X2__CI 0x00000052 -#define SQ_FLAT_ATOMIC_ADD__CI 0x00000032 -#define SQ_FLAT_ATOMIC_AND_X2__CI 0x00000059 -#define SQ_FLAT_ATOMIC_AND__CI 0x00000039 -#define SQ_FLAT_ATOMIC_CMPSWAP_X2__CI 0x00000051 -#define SQ_FLAT_ATOMIC_CMPSWAP__CI 0x00000031 -#define SQ_FLAT_ATOMIC_DEC_X2__CI 0x0000005d -#define SQ_FLAT_ATOMIC_DEC__CI 0x0000003d -#define SQ_FLAT_ATOMIC_FCMPSWAP_X2__CI 0x0000005e -#define SQ_FLAT_ATOMIC_FCMPSWAP__CI 0x0000003e -#define SQ_FLAT_ATOMIC_FMAX_X2__CI 0x00000060 -#define SQ_FLAT_ATOMIC_FMAX__CI 0x00000040 -#define SQ_FLAT_ATOMIC_FMIN_X2__CI 0x0000005f -#define SQ_FLAT_ATOMIC_FMIN__CI 0x0000003f -#define SQ_FLAT_ATOMIC_INC_X2__CI 0x0000005c -#define SQ_FLAT_ATOMIC_INC__CI 0x0000003c -#define SQ_FLAT_ATOMIC_OR_X2__CI 0x0000005a -#define SQ_FLAT_ATOMIC_OR__CI 0x0000003a -#define SQ_FLAT_ATOMIC_SMAX_X2__CI 0x00000057 -#define SQ_FLAT_ATOMIC_SMAX__CI 0x00000037 -#define SQ_FLAT_ATOMIC_SMIN_X2__CI 0x00000055 -#define SQ_FLAT_ATOMIC_SMIN__CI 0x00000035 -#define SQ_FLAT_ATOMIC_SUB_X2__CI 0x00000053 -#define SQ_FLAT_ATOMIC_SUB__CI 0x00000033 -#define SQ_FLAT_ATOMIC_SWAP_X2__CI 0x00000050 -#define SQ_FLAT_ATOMIC_SWAP__CI 0x00000030 -#define SQ_FLAT_ATOMIC_UMAX_X2__CI 0x00000058 -#define SQ_FLAT_ATOMIC_UMAX__CI 0x00000038 -#define SQ_FLAT_ATOMIC_UMIN_X2__CI 0x00000056 -#define SQ_FLAT_ATOMIC_UMIN__CI 0x00000036 -#define SQ_FLAT_ATOMIC_XOR_X2__CI 0x0000005b -#define SQ_FLAT_ATOMIC_XOR__CI 0x0000003b -#define SQ_FLAT_LOAD_DWORDX2__CI 0x0000000d -#define SQ_FLAT_LOAD_DWORDX3__CI 0x0000000f -#define SQ_FLAT_LOAD_DWORDX4__CI 0x0000000e -#define SQ_FLAT_LOAD_DWORD__CI 0x0000000c -#define SQ_FLAT_LOAD_SBYTE__CI 0x00000009 -#define SQ_FLAT_LOAD_SSHORT__CI 0x0000000b -#define SQ_FLAT_LOAD_UBYTE__CI 0x00000008 -#define SQ_FLAT_LOAD_USHORT__CI 0x0000000a -#define SQ_FLAT_SCRATCH_HI__CI 0x00000069 -#define SQ_FLAT_SCRATCH_LO__CI 0x00000068 -#define SQ_FLAT_STORE_BYTE__CI__VI 0x00000018 -#define SQ_FLAT_STORE_DWORDX2__CI__VI 0x0000001d -#define SQ_FLAT_STORE_DWORDX3__CI 0x0000001f -#define SQ_FLAT_STORE_DWORDX4__CI 0x0000001e -#define SQ_FLAT_STORE_DWORD__CI__VI 0x0000001c -#define SQ_FLAT_STORE_SHORT__CI__VI 0x0000001a -#define SQ_GE 0x00000006 -#define SQ_GFXDEC_BEGIN 0x0000a000 -#define SQ_GFXDEC_END 0x0000c000 -#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a -#define SQ_GS_OP_CUT 0x00000001 -#define SQ_GS_OP_EMIT 0x00000002 -#define SQ_GS_OP_EMIT_CUT 0x00000003 -#define SQ_GS_OP_NOP 0x00000000 -#define SQ_GT 0x00000004 -#define SQ_HWREG_ID_SHIFT 0x00000000 -#define SQ_HWREG_ID_SIZE 0x00000006 -#define SQ_HWREG_OFFSET_SHIFT 0x00000006 -#define SQ_HWREG_OFFSET_SIZE 0x00000005 -#define SQ_HWREG_SIZE_SHIFT 0x0000000b -#define SQ_HWREG_SIZE_SIZE 0x00000005 -#define SQ_HW_REG_GPR_ALLOC 0x00000005 -#define SQ_HW_REG_HW_ID 0x00000004 -#define SQ_HW_REG_IB_DBG0 0x0000000c -#define SQ_HW_REG_IB_STS 0x00000007 -#define SQ_HW_REG_INST_DW0 0x0000000a -#define SQ_HW_REG_INST_DW1 0x0000000b -#define SQ_HW_REG_LDS_ALLOC 0x00000006 -#define SQ_HW_REG_MODE 0x00000001 -#define SQ_HW_REG_PC_HI 0x00000009 -#define SQ_HW_REG_PC_LO 0x00000008 -#define SQ_HW_REG_STATUS 0x00000002 -#define SQ_HW_REG_TRAPSTS 0x00000003 -#define SQ_IMAGE_ATOMIC_AND 0x00000018 -#define SQ_IMAGE_ATOMIC_DEC 0x0000001c -#define SQ_IMAGE_ATOMIC_FCMPSWAP__SI__CI 0x0000001d -#define SQ_IMAGE_ATOMIC_FMAX__SI__CI 0x0000001f -#define SQ_IMAGE_ATOMIC_FMIN__SI__CI 0x0000001e -#define SQ_IMAGE_ATOMIC_INC 0x0000001b -#define SQ_IMAGE_ATOMIC_OR 0x00000019 -#define SQ_IMAGE_ATOMIC_RSUB__SI 0x00000013 -#define SQ_IMAGE_ATOMIC_SMAX 0x00000016 -#define SQ_IMAGE_ATOMIC_SMIN 0x00000014 -#define SQ_IMAGE_ATOMIC_UMAX 0x00000017 -#define SQ_IMAGE_ATOMIC_UMIN 0x00000015 -#define SQ_IMAGE_ATOMIC_XOR 0x0000001a -#define SQ_IMAGE_GATHER4 0x00000040 -#define SQ_IMAGE_GATHER4_B 0x00000045 -#define SQ_IMAGE_GATHER4_B_CL 0x00000046 -#define SQ_IMAGE_GATHER4_B_CL_O 0x00000056 -#define SQ_IMAGE_GATHER4_B_O 0x00000055 -#define SQ_IMAGE_GATHER4_C 0x00000048 -#define SQ_IMAGE_GATHER4_CL 0x00000041 -#define SQ_IMAGE_GATHER4_CL_O 0x00000051 -#define SQ_IMAGE_GATHER4_C_B 0x0000004d -#define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e -#define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e -#define SQ_IMAGE_GATHER4_C_B_O 0x0000005d -#define SQ_IMAGE_GATHER4_C_CL 0x00000049 -#define SQ_IMAGE_GATHER4_C_CL_O 0x00000059 -#define SQ_IMAGE_GATHER4_C_L 0x0000004c -#define SQ_IMAGE_GATHER4_C_LZ 0x0000004f -#define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f -#define SQ_IMAGE_GATHER4_C_L_O 0x0000005c -#define SQ_IMAGE_GATHER4_C_O 0x00000058 -#define SQ_IMAGE_GATHER4_L 0x00000044 -#define SQ_IMAGE_GATHER4_LZ 0x00000047 -#define SQ_IMAGE_GATHER4_LZ_O 0x00000057 -#define SQ_IMAGE_GATHER4_L_O 0x00000054 -#define SQ_IMAGE_GATHER4_O 0x00000050 -#define SQ_IMAGE_GET_LOD 0x00000060 -#define SQ_IMAGE_GET_RESINFO 0x0000000e -#define SQ_IMAGE_LOAD 0x00000000 -#define SQ_IMAGE_LOAD_MIP 0x00000001 -#define SQ_IMAGE_LOAD_MIP_PCK 0x00000004 -#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005 -#define SQ_IMAGE_LOAD_PCK 0x00000002 -#define SQ_IMAGE_LOAD_PCK_SGN 0x00000003 -#define SQ_IMAGE_RSRC256 0x0000007e -#define SQ_IMAGE_SAMPLE 0x00000020 -#define SQ_IMAGE_SAMPLER 0x0000007f -#define SQ_IMAGE_SAMPLE_B 0x00000025 -#define SQ_IMAGE_SAMPLE_B_CL 0x00000026 -#define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036 -#define SQ_IMAGE_SAMPLE_B_O 0x00000035 -#define SQ_IMAGE_SAMPLE_C 0x00000028 -#define SQ_IMAGE_SAMPLE_CD 0x00000068 -#define SQ_IMAGE_SAMPLE_CD_CL 0x00000069 -#define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d -#define SQ_IMAGE_SAMPLE_CD_O 0x0000006c -#define SQ_IMAGE_SAMPLE_CL 0x00000021 -#define SQ_IMAGE_SAMPLE_CL_O 0x00000031 -#define SQ_IMAGE_SAMPLE_C_B 0x0000002d -#define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e -#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e -#define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d -#define SQ_IMAGE_SAMPLE_C_CD 0x0000006a -#define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b -#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f -#define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e -#define SQ_IMAGE_SAMPLE_C_CL 0x00000029 -#define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039 -#define SQ_IMAGE_SAMPLE_C_D 0x0000002a -#define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b -#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b -#define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a -#define SQ_IMAGE_SAMPLE_C_L 0x0000002c -#define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f -#define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f -#define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c -#define SQ_IMAGE_SAMPLE_C_O 0x00000038 -#define SQ_IMAGE_SAMPLE_D 0x00000022 -#define SQ_IMAGE_SAMPLE_D_CL 0x00000023 -#define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033 -#define SQ_IMAGE_SAMPLE_D_O 0x00000032 -#define SQ_IMAGE_SAMPLE_L 0x00000024 -#define SQ_IMAGE_SAMPLE_LZ 0x00000027 -#define SQ_IMAGE_SAMPLE_LZ_O 0x00000037 -#define SQ_IMAGE_SAMPLE_L_O 0x00000034 -#define SQ_IMAGE_SAMPLE_O 0x00000030 -#define SQ_IMAGE_STORE 0x00000008 -#define SQ_IMAGE_STORE_MIP 0x00000009 -#define SQ_IMAGE_STORE_MIP_PCK 0x0000000b -#define SQ_IMAGE_STORE_PCK 0x0000000a -#define SQ_INTERRUPT_ID__SI__CI 0x000000ef -#define SQ_LE 0x00000003 -#define SQ_LG 0x00000005 -#define SQ_LT 0x00000001 -#define SQ_M0 0x0000007c -#define SQ_MAX_PGM_SGPRS 0x00000068 -#define SQ_MAX_PGM_VGPRS 0x00000100 -#define SQ_MSG_GS 0x00000002 -#define SQ_MSG_GS_DONE 0x00000003 -#define SQ_MSG_INTERRUPT 0x00000001 -#define SQ_MSG_SYSMSG 0x0000000f -#define SQ_NE 0x00000005 -#define SQ_NEQ 0x0000000d -#define SQ_NFMT_FLOAT__SI__CI 0x00000007 -#define SQ_NFMT_SINT__SI__CI 0x00000005 -#define SQ_NFMT_SNORM__SI__CI 0x00000001 -#define SQ_NFMT_SNORM_OGL__SI__CI 0x00000006 -#define SQ_NFMT_SSCALED__SI__CI 0x00000003 -#define SQ_NFMT_UINT__SI__CI 0x00000004 -#define SQ_NFMT_UNORM__SI__CI 0x00000000 -#define SQ_NFMT_USCALED__SI__CI 0x00000002 -#define SQ_NGE 0x00000009 -#define SQ_NGT 0x0000000b -#define SQ_NLE 0x0000000c -#define SQ_NLG 0x0000000a -#define SQ_NLT 0x0000000e -#define SQ_NUM_ATTR 0x00000021 -#define SQ_NUM_TTMP 0x0000000c -#define SQ_NUM_VGPR 0x00000100 -#define SQ_O 0x00000007 -#define SQ_OMOD_D2 0x00000003 -#define SQ_OMOD_M2 0x00000001 -#define SQ_OMOD_M4 0x00000002 -#define SQ_OMOD_OFF 0x00000000 -#define SQ_PARAM_P0 0x00000002 -#define SQ_PARAM_P10 0x00000000 -#define SQ_PARAM_P20 0x00000001 -#define SQ_SENDMSG_GSOP_SHIFT 0x00000004 -#define SQ_SENDMSG_GSOP_SIZE 0x00000002 -#define SQ_SENDMSG_MSG_SHIFT 0x00000000 -#define SQ_SENDMSG_MSG_SIZE 0x00000004 -#define SQ_SENDMSG_STREAMID_SHIFT 0x00000008 -#define SQ_SENDMSG_STREAMID_SIZE 0x00000002 -#define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004 -#define SQ_SENDMSG_SYSTEM_SIZE 0x00000003 -#define SQ_SGPR0 0x00000000 -#define SQ_SRC_0 0x00000080 -#define SQ_SRC_0_5 0x000000f0 -#define SQ_SRC_1 0x000000f2 -#define SQ_SRC_10_INT 0x0000008a -#define SQ_SRC_11_INT 0x0000008b -#define SQ_SRC_12_INT 0x0000008c -#define SQ_SRC_13_INT 0x0000008d -#define SQ_SRC_14_INT 0x0000008e -#define SQ_SRC_15_INT 0x0000008f -#define SQ_SRC_16_INT 0x00000090 -#define SQ_SRC_17_INT 0x00000091 -#define SQ_SRC_18_INT 0x00000092 -#define SQ_SRC_19_INT 0x00000093 -#define SQ_SRC_1_INT 0x00000081 -#define SQ_SRC_2 0x000000f4 -#define SQ_SRC_20_INT 0x00000094 -#define SQ_SRC_21_INT 0x00000095 -#define SQ_SRC_22_INT 0x00000096 -#define SQ_SRC_23_INT 0x00000097 -#define SQ_SRC_24_INT 0x00000098 -#define SQ_SRC_25_INT 0x00000099 -#define SQ_SRC_26_INT 0x0000009a -#define SQ_SRC_27_INT 0x0000009b -#define SQ_SRC_28_INT 0x0000009c -#define SQ_SRC_29_INT 0x0000009d -#define SQ_SRC_2_INT 0x00000082 -#define SQ_SRC_30_INT 0x0000009e -#define SQ_SRC_31_INT 0x0000009f -#define SQ_SRC_32_INT 0x000000a0 -#define SQ_SRC_33_INT 0x000000a1 -#define SQ_SRC_34_INT 0x000000a2 -#define SQ_SRC_35_INT 0x000000a3 -#define SQ_SRC_36_INT 0x000000a4 -#define SQ_SRC_37_INT 0x000000a5 -#define SQ_SRC_38_INT 0x000000a6 -#define SQ_SRC_39_INT 0x000000a7 -#define SQ_SRC_3_INT 0x00000083 -#define SQ_SRC_4 0x000000f6 -#define SQ_SRC_40_INT 0x000000a8 -#define SQ_SRC_41_INT 0x000000a9 -#define SQ_SRC_42_INT 0x000000aa -#define SQ_SRC_43_INT 0x000000ab -#define SQ_SRC_44_INT 0x000000ac -#define SQ_SRC_45_INT 0x000000ad -#define SQ_SRC_46_INT 0x000000ae -#define SQ_SRC_47_INT 0x000000af -#define SQ_SRC_48_INT 0x000000b0 -#define SQ_SRC_49_INT 0x000000b1 -#define SQ_SRC_4_INT 0x00000084 -#define SQ_SRC_50_INT 0x000000b2 -#define SQ_SRC_51_INT 0x000000b3 -#define SQ_SRC_52_INT 0x000000b4 -#define SQ_SRC_53_INT 0x000000b5 -#define SQ_SRC_54_INT 0x000000b6 -#define SQ_SRC_55_INT 0x000000b7 -#define SQ_SRC_56_INT 0x000000b8 -#define SQ_SRC_57_INT 0x000000b9 -#define SQ_SRC_58_INT 0x000000ba -#define SQ_SRC_59_INT 0x000000bb -#define SQ_SRC_5_INT 0x00000085 -#define SQ_SRC_60_INT 0x000000bc -#define SQ_SRC_61_INT 0x000000bd -#define SQ_SRC_62_INT 0x000000be -#define SQ_SRC_63_INT 0x000000bf -#define SQ_SRC_64_INT 0x000000c0 -#define SQ_SRC_6_INT 0x00000086 -#define SQ_SRC_7_INT 0x00000087 -#define SQ_SRC_8_INT 0x00000088 -#define SQ_SRC_9_INT 0x00000089 -#define SQ_SRC_EXECZ 0x000000fc -#define SQ_SRC_LDS_DIRECT 0x000000fe -#define SQ_SRC_LITERAL 0x000000ff -#define SQ_SRC_M_0_5 0x000000f1 -#define SQ_SRC_M_1 0x000000f3 -#define SQ_SRC_M_10_INT 0x000000ca -#define SQ_SRC_M_11_INT 0x000000cb -#define SQ_SRC_M_12_INT 0x000000cc -#define SQ_SRC_M_13_INT 0x000000cd -#define SQ_SRC_M_14_INT 0x000000ce -#define SQ_SRC_M_15_INT 0x000000cf -#define SQ_SRC_M_16_INT 0x000000d0 -#define SQ_SRC_M_1_INT 0x000000c1 -#define SQ_SRC_M_2 0x000000f5 -#define SQ_SRC_M_2_INT 0x000000c2 -#define SQ_SRC_M_3_INT 0x000000c3 -#define SQ_SRC_M_4 0x000000f7 -#define SQ_SRC_M_4_INT 0x000000c4 -#define SQ_SRC_M_5_INT 0x000000c5 -#define SQ_SRC_M_6_INT 0x000000c6 -#define SQ_SRC_M_7_INT 0x000000c7 -#define SQ_SRC_M_8_INT 0x000000c8 -#define SQ_SRC_M_9_INT 0x000000c9 -#define SQ_SRC_SCC 0x000000fd -#define SQ_SRC_VCCZ 0x000000fb -#define SQ_SRC_VGPR0 0x00000100 -#define SQ_SRC_VGPR_BIT 0x00000100 -#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001 -#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003 -#define SQ_SYSMSG_OP_REG_RD 0x00000002 -#define SQ_SYSMSG_OP_TTRACE_PC 0x00000004 -#define SQ_S_ADDC_U32 0x00000004 -#define SQ_S_ADD_I32 0x00000002 -#define SQ_S_ADD_U32 0x00000000 -#define SQ_S_BARRIER 0x0000000a -#define SQ_S_BITCMP0_B32 0x0000000c -#define SQ_S_BITCMP0_B64 0x0000000e -#define SQ_S_BITCMP1_B32 0x0000000d -#define SQ_S_BITCMP1_B64 0x0000000f -#define SQ_S_BRANCH 0x00000002 -#define SQ_S_BUFFER_LOAD_DWORD 0x00000008 -#define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c -#define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009 -#define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a -#define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b -#define SQ_S_CBRANCH_CDBGSYS_AND_USER__CI__VI 0x0000001a -#define SQ_S_CBRANCH_CDBGSYS_OR_USER__CI__VI 0x00000019 -#define SQ_S_CBRANCH_CDBGSYS__CI__VI 0x00000017 -#define SQ_S_CBRANCH_CDBGUSER__CI__VI 0x00000018 -#define SQ_S_CBRANCH_EXECNZ 0x00000009 -#define SQ_S_CBRANCH_EXECZ 0x00000008 -#define SQ_S_CBRANCH_SCC0 0x00000004 -#define SQ_S_CBRANCH_SCC1 0x00000005 -#define SQ_S_CBRANCH_VCCNZ 0x00000007 -#define SQ_S_CBRANCH_VCCZ 0x00000006 -#define SQ_S_CMP_EQ_I32 0x00000000 -#define SQ_S_CMP_EQ_U32 0x00000006 -#define SQ_S_CMP_GE_I32 0x00000003 -#define SQ_S_CMP_GE_U32 0x00000009 -#define SQ_S_CMP_GT_I32 0x00000002 -#define SQ_S_CMP_GT_U32 0x00000008 -#define SQ_S_CMP_LE_I32 0x00000005 -#define SQ_S_CMP_LE_U32 0x0000000b -#define SQ_S_CMP_LG_I32 0x00000001 -#define SQ_S_CMP_LG_U32 0x00000007 -#define SQ_S_CMP_LT_I32 0x00000004 -#define SQ_S_CMP_LT_U32 0x0000000a -#define SQ_S_CSELECT_B32 0x0000000a -#define SQ_S_CSELECT_B64 0x0000000b -#define SQ_S_DCACHE_INV_VOL__CI 0x0000001d -#define SQ_S_DECPERFLEVEL 0x00000015 -#define SQ_S_ENDPGM 0x00000001 -#define SQ_S_ICACHE_INV 0x00000013 -#define SQ_S_INCPERFLEVEL 0x00000014 -#define SQ_S_LOAD_DWORD 0x00000000 -#define SQ_S_LOAD_DWORDX16 0x00000004 -#define SQ_S_LOAD_DWORDX2 0x00000001 -#define SQ_S_LOAD_DWORDX4 0x00000002 -#define SQ_S_LOAD_DWORDX8 0x00000003 -#define SQ_S_MAX_I32 0x00000008 -#define SQ_S_MAX_U32 0x00000009 -#define SQ_S_MIN_I32 0x00000006 -#define SQ_S_MIN_U32 0x00000007 -#define SQ_S_MOVK_I32 0x00000000 -#define SQ_S_NOP 0x00000000 -#define SQ_S_SENDMSG 0x00000010 -#define SQ_S_SENDMSGHALT 0x00000011 -#define SQ_S_SETHALT 0x0000000d -#define SQ_S_SETKILL__CI__VI 0x0000000b -#define SQ_S_SETPRIO 0x0000000f -#define SQ_S_SETVSKIP 0x00000010 -#define SQ_S_SLEEP 0x0000000e -#define SQ_S_SUBB_U32 0x00000005 -#define SQ_S_SUB_I32 0x00000003 -#define SQ_S_SUB_U32 0x00000001 -#define SQ_S_TRAP 0x00000012 -#define SQ_S_TTRACEDATA 0x00000016 -#define SQ_S_WAITCNT 0x0000000c -#define SQ_T 0x00000007 -#define SQ_TBA_HI 0x0000006d -#define SQ_TBA_LO 0x0000006c -#define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_TBUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_THREAD_TRACE_LFSR_CS__SI__CI 0x00008097 -#define SQ_THREAD_TRACE_LFSR_ES__SI__CI 0x00008029 -#define SQ_THREAD_TRACE_LFSR_GS__SI__CI 0x0000801f -#define SQ_THREAD_TRACE_LFSR_HS__SI__CI 0x0000805e -#define SQ_THREAD_TRACE_LFSR_LS__SI__CI 0x0000806b -#define SQ_THREAD_TRACE_LFSR_PS__SI__CI 0x00008016 -#define SQ_THREAD_TRACE_LFSR_VS__SI__CI 0x0000801c -#define SQ_THREAD_TRACE_TIME_UNIT 0x00000004 -#define SQ_TMA_HI 0x0000006f -#define SQ_TMA_LO 0x0000006e -#define SQ_TRU 0x0000000f -#define SQ_TTMP0 0x00000070 -#define SQ_TTMP1 0x00000071 -#define SQ_TTMP10 0x0000007a -#define SQ_TTMP11 0x0000007b -#define SQ_TTMP2 0x00000072 -#define SQ_TTMP3 0x00000073 -#define SQ_TTMP4 0x00000074 -#define SQ_TTMP5 0x00000075 -#define SQ_TTMP6 0x00000076 -#define SQ_TTMP7 0x00000077 -#define SQ_TTMP8 0x00000078 -#define SQ_TTMP9 0x00000079 -#define SQ_U 0x00000008 -#define SQ_VCC_ALL 0x00000000 -#define SQ_VCC_HI 0x0000006b -#define SQ_VCC_LO 0x0000006a -#define SQ_VGPR0 0x00000000 -#define SQ_V_ADD_I32__SI__CI 0x00000025 -#define SQ_V_ASHR_I32__SI__CI 0x00000017 -#define SQ_V_ASHR_I64__SI__CI 0x00000163 -#define SQ_V_CEIL_F64__CI__VI 0x00000018 -#define SQ_V_CMPSX_EQ_F32__SI__CI 0x00000052 -#define SQ_V_CMPSX_EQ_F64__SI__CI 0x00000072 -#define SQ_V_CMPSX_F_F32__SI__CI 0x00000050 -#define SQ_V_CMPSX_F_F64__SI__CI 0x00000070 -#define SQ_V_CMPSX_GE_F32__SI__CI 0x00000056 -#define SQ_V_CMPSX_GE_F64__SI__CI 0x00000076 -#define SQ_V_CMPSX_GT_F32__SI__CI 0x00000054 -#define SQ_V_CMPSX_GT_F64__SI__CI 0x00000074 -#define SQ_V_CMPSX_LE_F32__SI__CI 0x00000053 -#define SQ_V_CMPSX_LE_F64__SI__CI 0x00000073 -#define SQ_V_CMPSX_LG_F32__SI__CI 0x00000055 -#define SQ_V_CMPSX_LG_F64__SI__CI 0x00000075 -#define SQ_V_CMPSX_LT_F32__SI__CI 0x00000051 -#define SQ_V_CMPSX_LT_F64__SI__CI 0x00000071 -#define SQ_V_CMPSX_NEQ_F32__SI__CI 0x0000005d -#define SQ_V_CMPSX_NEQ_F64__SI__CI 0x0000007d -#define SQ_V_CMPSX_NGE_F32__SI__CI 0x00000059 -#define SQ_V_CMPSX_NGE_F64__SI__CI 0x00000079 -#define SQ_V_CMPSX_NGT_F32__SI__CI 0x0000005b -#define SQ_V_CMPSX_NGT_F64__SI__CI 0x0000007b -#define SQ_V_CMPSX_NLE_F32__SI__CI 0x0000005c -#define SQ_V_CMPSX_NLE_F64__SI__CI 0x0000007c -#define SQ_V_CMPSX_NLG_F32__SI__CI 0x0000005a -#define SQ_V_CMPSX_NLG_F64__SI__CI 0x0000007a -#define SQ_V_CMPSX_NLT_F32__SI__CI 0x0000005e -#define SQ_V_CMPSX_NLT_F64__SI__CI 0x0000007e -#define SQ_V_CMPSX_O_F32__SI__CI 0x00000057 -#define SQ_V_CMPSX_O_F64__SI__CI 0x00000077 -#define SQ_V_CMPSX_TRU_F32__SI__CI 0x0000005f -#define SQ_V_CMPSX_TRU_F64__SI__CI 0x0000007f -#define SQ_V_CMPSX_U_F32__SI__CI 0x00000058 -#define SQ_V_CMPSX_U_F64__SI__CI 0x00000078 -#define SQ_V_CMPS_EQ_F32__SI__CI 0x00000042 -#define SQ_V_CMPS_EQ_F64__SI__CI 0x00000062 -#define SQ_V_CMPS_F_F32__SI__CI 0x00000040 -#define SQ_V_CMPS_F_F64__SI__CI 0x00000060 -#define SQ_V_CMPS_GE_F32__SI__CI 0x00000046 -#define SQ_V_CMPS_GE_F64__SI__CI 0x00000066 -#define SQ_V_CMPS_GT_F32__SI__CI 0x00000044 -#define SQ_V_CMPS_GT_F64__SI__CI 0x00000064 -#define SQ_V_CMPS_LE_F32__SI__CI 0x00000043 -#define SQ_V_CMPS_LE_F64__SI__CI 0x00000063 -#define SQ_V_CMPS_LG_F32__SI__CI 0x00000045 -#define SQ_V_CMPS_LG_F64__SI__CI 0x00000065 -#define SQ_V_CMPS_LT_F32__SI__CI 0x00000041 -#define SQ_V_CMPS_LT_F64__SI__CI 0x00000061 -#define SQ_V_CMPS_NEQ_F32__SI__CI 0x0000004d -#define SQ_V_CMPS_NEQ_F64__SI__CI 0x0000006d -#define SQ_V_CMPS_NGE_F32__SI__CI 0x00000049 -#define SQ_V_CMPS_NGE_F64__SI__CI 0x00000069 -#define SQ_V_CMPS_NGT_F32__SI__CI 0x0000004b -#define SQ_V_CMPS_NGT_F64__SI__CI 0x0000006b -#define SQ_V_CMPS_NLE_F32__SI__CI 0x0000004c -#define SQ_V_CMPS_NLE_F64__SI__CI 0x0000006c -#define SQ_V_CMPS_NLG_F32__SI__CI 0x0000004a -#define SQ_V_CMPS_NLG_F64__SI__CI 0x0000006a -#define SQ_V_CMPS_NLT_F32__SI__CI 0x0000004e -#define SQ_V_CMPS_NLT_F64__SI__CI 0x0000006e -#define SQ_V_CMPS_O_F32__SI__CI 0x00000047 -#define SQ_V_CMPS_O_F64__SI__CI 0x00000067 -#define SQ_V_CMPS_TRU_F32__SI__CI 0x0000004f -#define SQ_V_CMPS_TRU_F64__SI__CI 0x0000006f -#define SQ_V_CMPS_U_F32__SI__CI 0x00000048 -#define SQ_V_CMPS_U_F64__SI__CI 0x00000068 -#define SQ_V_CNDMASK_B32 0x00000000 -#define SQ_V_CVT_F16_F32 0x0000000a -#define SQ_V_CVT_F32_F16 0x0000000b -#define SQ_V_CVT_F32_F64 0x0000000f -#define SQ_V_CVT_F32_I32 0x00000005 -#define SQ_V_CVT_F32_U32 0x00000006 -#define SQ_V_CVT_F32_UBYTE0 0x00000011 -#define SQ_V_CVT_F32_UBYTE1 0x00000012 -#define SQ_V_CVT_F32_UBYTE2 0x00000013 -#define SQ_V_CVT_F32_UBYTE3 0x00000014 -#define SQ_V_CVT_F64_F32 0x00000010 -#define SQ_V_CVT_F64_I32 0x00000004 -#define SQ_V_CVT_F64_U32 0x00000016 -#define SQ_V_CVT_FLR_I32_F32 0x0000000d -#define SQ_V_CVT_I32_F32 0x00000008 -#define SQ_V_CVT_I32_F64 0x00000003 -#define SQ_V_CVT_OFF_F32_I4 0x0000000e -#define SQ_V_CVT_RPI_I32_F32 0x0000000c -#define SQ_V_CVT_U32_F32 0x00000007 -#define SQ_V_CVT_U32_F64 0x00000015 -#define SQ_V_EXP_LEGACY_F32__CI 0x00000046 -#define SQ_V_FLOOR_F64__CI__VI 0x0000001a -#define SQ_V_INTERP_MOV_F32 0x00000002 -#define SQ_V_INTERP_P1_F32 0x00000000 -#define SQ_V_INTERP_P2_F32 0x00000001 -#define SQ_V_LOG_CLAMP_F32__SI__CI 0x00000026 -#define SQ_V_LOG_LEGACY_F32__CI 0x00000045 -#define SQ_V_LSHL_B32__SI__CI 0x00000019 -#define SQ_V_LSHL_B64__SI__CI 0x00000161 -#define SQ_V_LSHR_B32__SI__CI 0x00000015 -#define SQ_V_LSHR_B64__SI__CI 0x00000162 -#define SQ_V_MAD_I64_I32__CI 0x00000177 -#define SQ_V_MAD_U64_U32__CI 0x00000176 -#define SQ_V_MAX_LEGACY_F32__SI__CI 0x0000000e -#define SQ_V_MIN_LEGACY_F32__SI__CI 0x0000000d -#define SQ_V_MOV_B32 0x00000001 -#define SQ_V_MOV_FED_B32 0x00000009 -#define SQ_V_MQSAD_PK_U16_U8__CI 0x00000173 -#define SQ_V_MQSAD_U32_U8__CI 0x00000175 -#define SQ_V_MQSAD_U8__SI 0x00000173 -#define SQ_V_MULLIT_F32__SI__CI 0x00000150 -#define SQ_V_MUL_LO_I32__SI__CI 0x0000016b -#define SQ_V_NOP 0x00000000 -#define SQ_V_OP1_COUNT 0x00000080 -#define SQ_V_OP2_COUNT 0x00000040 -#define SQ_V_OP2_OFFSET 0x00000100 -#define SQ_V_OPC_COUNT 0x00000100 -#define SQ_V_OPC_OFFSET 0x00000000 -#define SQ_V_QSAD_PK_U16_U8__CI 0x00000172 -#define SQ_V_QSAD_U8__SI 0x00000172 -#define SQ_V_RCP_CLAMP_F32__SI__CI 0x00000028 -#define SQ_V_RCP_CLAMP_F64__SI__CI 0x00000030 -#define SQ_V_RCP_LEGACY_F32__SI__CI 0x00000029 -#define SQ_V_READFIRSTLANE_B32 0x00000002 -#define SQ_V_RNDNE_F64__CI__VI 0x00000019 -#define SQ_V_RSQ_CLAMP_F32__SI__CI 0x0000002c -#define SQ_V_RSQ_CLAMP_F64__SI__CI 0x00000032 -#define SQ_V_RSQ_LEGACY_F32__SI__CI 0x0000002d -#define SQ_V_SUBREV_I32__SI__CI 0x00000027 -#define SQ_V_SUB_I32__SI__CI 0x00000026 -#define SQ_V_TRUNC_F64__CI__VI 0x00000017 -#define SQ_WAITCNT_EXP_SHIFT 0x00000004 -#define SQ_WAITCNT_EXP_SIZE 0x00000003 -#define SQ_WAITCNT_LGKM_SHIFT 0x00000008 -#define SQ_WAITCNT_LGKM_SIZE 0x00000004 -#define SQ_WAITCNT_VM_SHIFT 0x00000000 -#define SQ_WAITCNT_VM_SIZE 0x00000004 -#define SQ_WAVE_TYPE_PS0 0x00000000 -#define SRCID_SECURE_9__CI 0x00000009 -#define SRCID_SECURE_B__CI 0x0000000b -#define UCONFIG_SPACE_END__CI__VI 0x0000ffff -#define UCONFIG_SPACE_START__CI__VI 0x0000c000 -#define VMID_SZ__CI__VI 0x00000004 - -// Merged Defines - -#define CCP_CHAIN_ADR__VI 0x00000009 -#define CCP_KEY_SADR__VI 0x00000010 -#define HDCP_KEY_EADR__VI 0x00000191 -#define HDCP_KEY_SADR__VI 0x00000073 -#define INST_ID_PRIV_START__VI 0x80000000 -#define INST_ID_SPI_WREXEC__VI 0xfffffff4 -#define KEYS_CHAIN_ADR__VI 0x00000002 -#define RCU_CCF_BITS__VI 0x000002a0 -#define RCU_CCF_DWORDS__VI 0x00000015 -#define RCU_SAM_BYTES__VI 0x00000062 -#define RCU_SAM_RTL_BYTES__VI 0x00000062 -#define SAMU_KEY_EADR__VI 0x00000061 -#define SAMU_KEY_SADR__VI 0x00000000 -#define SFP_BYTES__VI 0x00000080 -#define SFP_CHAIN_ADDR__VI 0x00000003 -#define SMU_KEY_EADR__VI 0x00000072 -#define SMU_KEY_SADR__VI 0x00000062 -#define SQGFXUDEC_BEGIN__VI 0x0000c330 -#define SQ_BUFFER_ATOMIC_ADD__SI__CI 0x00000032 -#define SQ_BUFFER_ATOMIC_ADD__VI 0x00000042 -#define SQ_BUFFER_ATOMIC_ADD_X2__SI__CI 0x00000052 -#define SQ_BUFFER_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_BUFFER_ATOMIC_AND__SI__CI 0x00000039 -#define SQ_BUFFER_ATOMIC_AND__VI 0x00000048 -#define SQ_BUFFER_ATOMIC_AND_X2__SI__CI 0x00000059 -#define SQ_BUFFER_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_BUFFER_ATOMIC_CMPSWAP__SI__CI 0x00000031 -#define SQ_BUFFER_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__SI__CI 0x00000051 -#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_BUFFER_ATOMIC_DEC__SI__CI 0x0000003d -#define SQ_BUFFER_ATOMIC_DEC__VI 0x0000004c -#define SQ_BUFFER_ATOMIC_DEC_X2__SI__CI 0x0000005d -#define SQ_BUFFER_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_BUFFER_ATOMIC_INC__SI__CI 0x0000003c -#define SQ_BUFFER_ATOMIC_INC__VI 0x0000004b -#define SQ_BUFFER_ATOMIC_INC_X2__SI__CI 0x0000005c -#define SQ_BUFFER_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_BUFFER_ATOMIC_OR__SI__CI 0x0000003a -#define SQ_BUFFER_ATOMIC_OR__VI 0x00000049 -#define SQ_BUFFER_ATOMIC_OR_X2__SI__CI 0x0000005a -#define SQ_BUFFER_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_BUFFER_ATOMIC_SMAX__SI__CI 0x00000037 -#define SQ_BUFFER_ATOMIC_SMAX__VI 0x00000046 -#define SQ_BUFFER_ATOMIC_SMAX_X2__SI__CI 0x00000057 -#define SQ_BUFFER_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_BUFFER_ATOMIC_SMIN__SI__CI 0x00000035 -#define SQ_BUFFER_ATOMIC_SMIN__VI 0x00000044 -#define SQ_BUFFER_ATOMIC_SMIN_X2__SI__CI 0x00000055 -#define SQ_BUFFER_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_BUFFER_ATOMIC_SUB__SI__CI 0x00000033 -#define SQ_BUFFER_ATOMIC_SUB__VI 0x00000043 -#define SQ_BUFFER_ATOMIC_SUB_X2__SI__CI 0x00000053 -#define SQ_BUFFER_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_BUFFER_ATOMIC_SWAP__SI__CI 0x00000030 -#define SQ_BUFFER_ATOMIC_SWAP__VI 0x00000040 -#define SQ_BUFFER_ATOMIC_SWAP_X2__SI__CI 0x00000050 -#define SQ_BUFFER_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_BUFFER_ATOMIC_UMAX__SI__CI 0x00000038 -#define SQ_BUFFER_ATOMIC_UMAX__VI 0x00000047 -#define SQ_BUFFER_ATOMIC_UMAX_X2__SI__CI 0x00000058 -#define SQ_BUFFER_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_BUFFER_ATOMIC_UMIN__SI__CI 0x00000036 -#define SQ_BUFFER_ATOMIC_UMIN__VI 0x00000045 -#define SQ_BUFFER_ATOMIC_UMIN_X2__SI__CI 0x00000056 -#define SQ_BUFFER_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_BUFFER_ATOMIC_XOR__SI__CI 0x0000003b -#define SQ_BUFFER_ATOMIC_XOR__VI 0x0000004a -#define SQ_BUFFER_ATOMIC_XOR_X2__SI__CI 0x0000005b -#define SQ_BUFFER_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_BUFFER_LOAD_DWORD__SI__CI 0x0000000c -#define SQ_BUFFER_LOAD_DWORD__VI 0x00000014 -#define SQ_BUFFER_LOAD_DWORDX2__SI__CI 0x0000000d -#define SQ_BUFFER_LOAD_DWORDX2__VI 0x00000015 -#define SQ_BUFFER_LOAD_DWORDX3__VI 0x00000016 -#define SQ_BUFFER_LOAD_DWORDX4__SI__CI 0x0000000e -#define SQ_BUFFER_LOAD_DWORDX4__VI 0x00000017 -#define SQ_BUFFER_LOAD_FORMAT_D16_X__VI 0x00000008 -#define SQ_BUFFER_LOAD_FORMAT_D16_XY__VI 0x00000009 -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ__VI 0x0000000a -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW__VI 0x0000000b -#define SQ_BUFFER_LOAD_SBYTE__SI__CI 0x00000009 -#define SQ_BUFFER_LOAD_SBYTE__VI 0x00000011 -#define SQ_BUFFER_LOAD_SSHORT__SI__CI 0x0000000b -#define SQ_BUFFER_LOAD_SSHORT__VI 0x00000013 -#define SQ_BUFFER_LOAD_UBYTE__SI__CI 0x00000008 -#define SQ_BUFFER_LOAD_UBYTE__VI 0x00000010 -#define SQ_BUFFER_LOAD_USHORT__SI__CI 0x0000000a -#define SQ_BUFFER_LOAD_USHORT__VI 0x00000012 -#define SQ_BUFFER_STORE_DWORDX3__VI 0x0000001e -#define SQ_BUFFER_STORE_DWORDX4__SI__CI 0x0000001e -#define SQ_BUFFER_STORE_DWORDX4__VI 0x0000001f -#define SQ_BUFFER_STORE_FORMAT_D16_X__VI 0x0000000c -#define SQ_BUFFER_STORE_FORMAT_D16_XY__VI 0x0000000d -#define SQ_BUFFER_STORE_FORMAT_D16_XYZ__VI 0x0000000e -#define SQ_BUFFER_STORE_FORMAT_D16_XYZW__VI 0x0000000f -#define SQ_BUFFER_STORE_LDS_DWORD__VI 0x0000003d -#define SQ_BUFFER_WBINVL1__SI__CI 0x00000071 -#define SQ_BUFFER_WBINVL1__VI 0x0000003e -#define SQ_BUFFER_WBINVL1_VOL__VI 0x0000003f -#define SQ_DPP_BOUND_OFF__VI 0x00000000 -#define SQ_DPP_BOUND_ZERO__VI 0x00000001 -#define SQ_DPP_QUAD_PERM__VI 0x00000000 -#define SQ_DPP_ROW_BCAST15__VI 0x00000142 -#define SQ_DPP_ROW_BCAST31__VI 0x00000143 -#define SQ_DPP_ROW_HALF_MIRROR__VI 0x00000141 -#define SQ_DPP_ROW_MIRROR__VI 0x00000140 -#define SQ_DPP_ROW_RR1__VI 0x00000121 -#define SQ_DPP_ROW_RR10__VI 0x0000012a -#define SQ_DPP_ROW_RR11__VI 0x0000012b -#define SQ_DPP_ROW_RR12__VI 0x0000012c -#define SQ_DPP_ROW_RR13__VI 0x0000012d -#define SQ_DPP_ROW_RR14__VI 0x0000012e -#define SQ_DPP_ROW_RR15__VI 0x0000012f -#define SQ_DPP_ROW_RR2__VI 0x00000122 -#define SQ_DPP_ROW_RR3__VI 0x00000123 -#define SQ_DPP_ROW_RR4__VI 0x00000124 -#define SQ_DPP_ROW_RR5__VI 0x00000125 -#define SQ_DPP_ROW_RR6__VI 0x00000126 -#define SQ_DPP_ROW_RR7__VI 0x00000127 -#define SQ_DPP_ROW_RR8__VI 0x00000128 -#define SQ_DPP_ROW_RR9__VI 0x00000129 -#define SQ_DPP_ROW_SL1__VI 0x00000101 -#define SQ_DPP_ROW_SL10__VI 0x0000010a -#define SQ_DPP_ROW_SL11__VI 0x0000010b -#define SQ_DPP_ROW_SL12__VI 0x0000010c -#define SQ_DPP_ROW_SL13__VI 0x0000010d -#define SQ_DPP_ROW_SL14__VI 0x0000010e -#define SQ_DPP_ROW_SL15__VI 0x0000010f -#define SQ_DPP_ROW_SL2__VI 0x00000102 -#define SQ_DPP_ROW_SL3__VI 0x00000103 -#define SQ_DPP_ROW_SL4__VI 0x00000104 -#define SQ_DPP_ROW_SL5__VI 0x00000105 -#define SQ_DPP_ROW_SL6__VI 0x00000106 -#define SQ_DPP_ROW_SL7__VI 0x00000107 -#define SQ_DPP_ROW_SL8__VI 0x00000108 -#define SQ_DPP_ROW_SL9__VI 0x00000109 -#define SQ_DPP_ROW_SR1__VI 0x00000111 -#define SQ_DPP_ROW_SR10__VI 0x0000011a -#define SQ_DPP_ROW_SR11__VI 0x0000011b -#define SQ_DPP_ROW_SR12__VI 0x0000011c -#define SQ_DPP_ROW_SR13__VI 0x0000011d -#define SQ_DPP_ROW_SR14__VI 0x0000011e -#define SQ_DPP_ROW_SR15__VI 0x0000011f -#define SQ_DPP_ROW_SR2__VI 0x00000112 -#define SQ_DPP_ROW_SR3__VI 0x00000113 -#define SQ_DPP_ROW_SR4__VI 0x00000114 -#define SQ_DPP_ROW_SR5__VI 0x00000115 -#define SQ_DPP_ROW_SR6__VI 0x00000116 -#define SQ_DPP_ROW_SR7__VI 0x00000117 -#define SQ_DPP_ROW_SR8__VI 0x00000118 -#define SQ_DPP_ROW_SR9__VI 0x00000119 -#define SQ_DPP_WF_RL1__VI 0x00000134 -#define SQ_DPP_WF_RR1__VI 0x0000013c -#define SQ_DPP_WF_SL1__VI 0x00000130 -#define SQ_DPP_WF_SR1__VI 0x00000138 -#define SQ_DS_ADD_F32__VI 0x00000015 -#define SQ_DS_ADD_RTN_F32__VI 0x00000035 -#define SQ_DS_ADD_SRC2_F32__VI 0x00000095 -#define SQ_DS_APPEND__SI__CI 0x0000003e -#define SQ_DS_APPEND__VI 0x000000be -#define SQ_DS_BPERMUTE_B32__VI 0x0000003f -#define SQ_DS_CONSUME__SI__CI 0x0000003d -#define SQ_DS_CONSUME__VI 0x000000bd -#define SQ_DS_GWS_BARRIER__SI__CI 0x0000001d -#define SQ_DS_GWS_BARRIER__VI 0x0000009d -#define SQ_DS_GWS_INIT__SI__CI 0x00000019 -#define SQ_DS_GWS_INIT__VI 0x00000099 -#define SQ_DS_GWS_SEMA_BR__SI__CI 0x0000001b -#define SQ_DS_GWS_SEMA_BR__VI 0x0000009b -#define SQ_DS_GWS_SEMA_P__SI__CI 0x0000001c -#define SQ_DS_GWS_SEMA_P__VI 0x0000009c -#define SQ_DS_GWS_SEMA_RELEASE_ALL__VI 0x00000098 -#define SQ_DS_GWS_SEMA_V__SI__CI 0x0000001a -#define SQ_DS_GWS_SEMA_V__VI 0x0000009a -#define SQ_DS_ORDERED_COUNT__SI__CI 0x0000003f -#define SQ_DS_ORDERED_COUNT__VI 0x000000bf -#define SQ_DS_PERMUTE_B32__VI 0x0000003e -#define SQ_DS_SWIZZLE_B32__SI__CI 0x00000035 -#define SQ_DS_SWIZZLE_B32__VI 0x0000003d -#define SQ_ENC_EXP_BITS__SI__CI 0xf8000000 -#define SQ_ENC_EXP_BITS__VI 0xc4000000 -#define SQ_ENC_EXP_FIELD__SI__CI 0x0000003e -#define SQ_ENC_EXP_FIELD__VI 0x00000031 -#define SQ_ENC_SMEM_BITS__VI 0xc0000000 -#define SQ_ENC_SMEM_FIELD__VI 0x00000030 -#define SQ_ENC_SMEM_MASK__VI 0xfc000000 -#define SQ_ENC_VINTRP_BITS__SI__CI 0xc8000000 -#define SQ_ENC_VINTRP_BITS__VI 0xd4000000 -#define SQ_ENC_VINTRP_FIELD__SI__CI 0x00000032 -#define SQ_ENC_VINTRP_FIELD__VI 0x00000035 -#define SQ_FLAT_ATOMIC_ADD__VI 0x00000042 -#define SQ_FLAT_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_FLAT_ATOMIC_AND__VI 0x00000048 -#define SQ_FLAT_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_FLAT_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_FLAT_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_FLAT_ATOMIC_DEC__VI 0x0000004c -#define SQ_FLAT_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_FLAT_ATOMIC_INC__VI 0x0000004b -#define SQ_FLAT_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_FLAT_ATOMIC_OR__VI 0x00000049 -#define SQ_FLAT_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_FLAT_ATOMIC_SMAX__VI 0x00000046 -#define SQ_FLAT_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_FLAT_ATOMIC_SMIN__VI 0x00000044 -#define SQ_FLAT_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_FLAT_ATOMIC_SUB__VI 0x00000043 -#define SQ_FLAT_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_FLAT_ATOMIC_SWAP__VI 0x00000040 -#define SQ_FLAT_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_FLAT_ATOMIC_UMAX__VI 0x00000047 -#define SQ_FLAT_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_FLAT_ATOMIC_UMIN__VI 0x00000045 -#define SQ_FLAT_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_FLAT_ATOMIC_XOR__VI 0x0000004a -#define SQ_FLAT_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_FLAT_LOAD_DWORD__VI 0x00000014 -#define SQ_FLAT_LOAD_DWORDX2__VI 0x00000015 -#define SQ_FLAT_LOAD_DWORDX3__VI 0x00000016 -#define SQ_FLAT_LOAD_DWORDX4__VI 0x00000017 -#define SQ_FLAT_LOAD_SBYTE__VI 0x00000011 -#define SQ_FLAT_LOAD_SSHORT__VI 0x00000013 -#define SQ_FLAT_LOAD_UBYTE__VI 0x00000010 -#define SQ_FLAT_LOAD_USHORT__VI 0x00000012 -#define SQ_FLAT_SCRATCH_HI__VI 0x00000067 -#define SQ_FLAT_SCRATCH_LO__VI 0x00000066 -#define SQ_FLAT_STORE_DWORDX3__VI 0x0000001e -#define SQ_FLAT_STORE_DWORDX4__VI 0x0000001f -#define SQ_HW_REG_IB_DBG1__VI 0x0000000d -#define SQ_IMAGE_ATOMIC_ADD__SI__CI 0x00000011 -#define SQ_IMAGE_ATOMIC_ADD__VI 0x00000012 -#define SQ_IMAGE_ATOMIC_CMPSWAP__SI__CI 0x00000010 -#define SQ_IMAGE_ATOMIC_CMPSWAP__VI 0x00000011 -#define SQ_IMAGE_ATOMIC_SUB__SI__CI 0x00000012 -#define SQ_IMAGE_ATOMIC_SUB__VI 0x00000013 -#define SQ_IMAGE_ATOMIC_SWAP__SI__CI 0x0000000f -#define SQ_IMAGE_ATOMIC_SWAP__VI 0x00000010 -#define SQ_L1__VI 0x00000001 -#define SQ_L10__VI 0x0000000a -#define SQ_L11__VI 0x0000000b -#define SQ_L12__VI 0x0000000c -#define SQ_L13__VI 0x0000000d -#define SQ_L14__VI 0x0000000e -#define SQ_L15__VI 0x0000000f -#define SQ_L2__VI 0x00000002 -#define SQ_L3__VI 0x00000003 -#define SQ_L4__VI 0x00000004 -#define SQ_L5__VI 0x00000005 -#define SQ_L6__VI 0x00000006 -#define SQ_L7__VI 0x00000007 -#define SQ_L8__VI 0x00000008 -#define SQ_L9__VI 0x00000009 -#define SQ_MSG_SAVEWAVE__VI 0x00000004 -#define SQ_NUM_SGPR__SI__CI 0x00000068 -#define SQ_NUM_SGPR__VI 0x00000066 -#define SQ_R1__VI 0x00000001 -#define SQ_R10__VI 0x0000000a -#define SQ_R11__VI 0x0000000b -#define SQ_R12__VI 0x0000000c -#define SQ_R13__VI 0x0000000d -#define SQ_R14__VI 0x0000000e -#define SQ_R15__VI 0x0000000f -#define SQ_R2__VI 0x00000002 -#define SQ_R3__VI 0x00000003 -#define SQ_R4__VI 0x00000004 -#define SQ_R5__VI 0x00000005 -#define SQ_R6__VI 0x00000006 -#define SQ_R7__VI 0x00000007 -#define SQ_R8__VI 0x00000008 -#define SQ_R9__VI 0x00000009 -#define SQ_SDWA_BYTE_0__VI 0x00000000 -#define SQ_SDWA_BYTE_1__VI 0x00000001 -#define SQ_SDWA_BYTE_2__VI 0x00000002 -#define SQ_SDWA_BYTE_3__VI 0x00000003 -#define SQ_SDWA_DWORD__VI 0x00000006 -#define SQ_SDWA_UNUSED_PAD__VI 0x00000000 -#define SQ_SDWA_UNUSED_PRESERVE__VI 0x00000002 -#define SQ_SDWA_UNUSED_SEXT__VI 0x00000001 -#define SQ_SDWA_WORD_0__VI 0x00000004 -#define SQ_SDWA_WORD_1__VI 0x00000005 -#define SQ_SRC_DPP__VI 0x000000fa -#define SQ_SRC_INV_2PI__VI 0x000000f8 -#define SQ_SRC_SDWA__VI 0x000000f9 -#define SQ_S_ABSDIFF_I32__SI__CI 0x0000002c -#define SQ_S_ABSDIFF_I32__VI 0x0000002a -#define SQ_S_ABS_I32__SI__CI 0x00000034 -#define SQ_S_ABS_I32__VI 0x00000030 -#define SQ_S_ADDK_I32__SI__CI 0x0000000f -#define SQ_S_ADDK_I32__VI 0x0000000e -#define SQ_S_ANDN2_B32__SI__CI 0x00000014 -#define SQ_S_ANDN2_B32__VI 0x00000012 -#define SQ_S_ANDN2_B64__SI__CI 0x00000015 -#define SQ_S_ANDN2_B64__VI 0x00000013 -#define SQ_S_ANDN2_SAVEEXEC_B64__SI__CI 0x00000027 -#define SQ_S_ANDN2_SAVEEXEC_B64__VI 0x00000023 -#define SQ_S_AND_B32__SI__CI 0x0000000e -#define SQ_S_AND_B32__VI 0x0000000c -#define SQ_S_AND_B64__SI__CI 0x0000000f -#define SQ_S_AND_B64__VI 0x0000000d -#define SQ_S_AND_SAVEEXEC_B64__SI__CI 0x00000024 -#define SQ_S_AND_SAVEEXEC_B64__VI 0x00000020 -#define SQ_S_ASHR_I32__SI__CI 0x00000022 -#define SQ_S_ASHR_I32__VI 0x00000020 -#define SQ_S_ASHR_I64__SI__CI 0x00000023 -#define SQ_S_ASHR_I64__VI 0x00000021 -#define SQ_S_ATC_PROBE__VI 0x00000026 -#define SQ_S_ATC_PROBE_BUFFER__VI 0x00000027 -#define SQ_S_BCNT0_I32_B32__SI__CI 0x0000000d -#define SQ_S_BCNT0_I32_B32__VI 0x0000000a -#define SQ_S_BCNT0_I32_B64__SI__CI 0x0000000e -#define SQ_S_BCNT0_I32_B64__VI 0x0000000b -#define SQ_S_BCNT1_I32_B32__SI__CI 0x0000000f -#define SQ_S_BCNT1_I32_B32__VI 0x0000000c -#define SQ_S_BCNT1_I32_B64__SI__CI 0x00000010 -#define SQ_S_BCNT1_I32_B64__VI 0x0000000d -#define SQ_S_BFE_I32__SI__CI 0x00000028 -#define SQ_S_BFE_I32__VI 0x00000026 -#define SQ_S_BFE_I64__SI__CI 0x0000002a -#define SQ_S_BFE_I64__VI 0x00000028 -#define SQ_S_BFE_U32__SI__CI 0x00000027 -#define SQ_S_BFE_U32__VI 0x00000025 -#define SQ_S_BFE_U64__SI__CI 0x00000029 -#define SQ_S_BFE_U64__VI 0x00000027 -#define SQ_S_BFM_B32__SI__CI 0x00000024 -#define SQ_S_BFM_B32__VI 0x00000022 -#define SQ_S_BFM_B64__SI__CI 0x00000025 -#define SQ_S_BFM_B64__VI 0x00000023 -#define SQ_S_BITSET0_B32__SI__CI 0x0000001b -#define SQ_S_BITSET0_B32__VI 0x00000018 -#define SQ_S_BITSET0_B64__SI__CI 0x0000001c -#define SQ_S_BITSET0_B64__VI 0x00000019 -#define SQ_S_BITSET1_B32__SI__CI 0x0000001d -#define SQ_S_BITSET1_B32__VI 0x0000001a -#define SQ_S_BITSET1_B64__SI__CI 0x0000001e -#define SQ_S_BITSET1_B64__VI 0x0000001b -#define SQ_S_BREV_B32__SI__CI 0x0000000b -#define SQ_S_BREV_B32__VI 0x00000008 -#define SQ_S_BREV_B64__SI__CI 0x0000000c -#define SQ_S_BREV_B64__VI 0x00000009 -#define SQ_S_BUFFER_ATOMIC_ADD__VI 0x00000042 -#define SQ_S_BUFFER_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_S_BUFFER_ATOMIC_AND__VI 0x00000048 -#define SQ_S_BUFFER_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_S_BUFFER_ATOMIC_DEC__VI 0x0000004c -#define SQ_S_BUFFER_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_S_BUFFER_ATOMIC_INC__VI 0x0000004b -#define SQ_S_BUFFER_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_S_BUFFER_ATOMIC_OR__VI 0x00000049 -#define SQ_S_BUFFER_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_S_BUFFER_ATOMIC_SMAX__VI 0x00000046 -#define SQ_S_BUFFER_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_S_BUFFER_ATOMIC_SMIN__VI 0x00000044 -#define SQ_S_BUFFER_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_S_BUFFER_ATOMIC_SUB__VI 0x00000043 -#define SQ_S_BUFFER_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_S_BUFFER_ATOMIC_SWAP__VI 0x00000040 -#define SQ_S_BUFFER_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_S_BUFFER_ATOMIC_UMAX__VI 0x00000047 -#define SQ_S_BUFFER_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_S_BUFFER_ATOMIC_UMIN__VI 0x00000045 -#define SQ_S_BUFFER_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_S_BUFFER_ATOMIC_XOR__VI 0x0000004a -#define SQ_S_BUFFER_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_S_BUFFER_STORE_DWORD__VI 0x00000018 -#define SQ_S_BUFFER_STORE_DWORDX2__VI 0x00000019 -#define SQ_S_BUFFER_STORE_DWORDX4__VI 0x0000001a -#define SQ_S_CBRANCH_G_FORK__SI__CI 0x0000002b -#define SQ_S_CBRANCH_G_FORK__VI 0x00000029 -#define SQ_S_CBRANCH_I_FORK__SI__CI 0x00000011 -#define SQ_S_CBRANCH_I_FORK__VI 0x00000010 -#define SQ_S_CBRANCH_JOIN__SI__CI 0x00000032 -#define SQ_S_CBRANCH_JOIN__VI 0x0000002e -#define SQ_S_CMOVK_I32__SI__CI 0x00000002 -#define SQ_S_CMOVK_I32__VI 0x00000001 -#define SQ_S_CMOV_B32__SI__CI 0x00000005 -#define SQ_S_CMOV_B32__VI 0x00000002 -#define SQ_S_CMOV_B64__SI__CI 0x00000006 -#define SQ_S_CMOV_B64__VI 0x00000003 -#define SQ_S_CMPK_EQ_I32__SI__CI 0x00000003 -#define SQ_S_CMPK_EQ_I32__VI 0x00000002 -#define SQ_S_CMPK_EQ_U32__SI__CI 0x00000009 -#define SQ_S_CMPK_EQ_U32__VI 0x00000008 -#define SQ_S_CMPK_GE_I32__SI__CI 0x00000006 -#define SQ_S_CMPK_GE_I32__VI 0x00000005 -#define SQ_S_CMPK_GE_U32__SI__CI 0x0000000c -#define SQ_S_CMPK_GE_U32__VI 0x0000000b -#define SQ_S_CMPK_GT_I32__SI__CI 0x00000005 -#define SQ_S_CMPK_GT_I32__VI 0x00000004 -#define SQ_S_CMPK_GT_U32__SI__CI 0x0000000b -#define SQ_S_CMPK_GT_U32__VI 0x0000000a -#define SQ_S_CMPK_LE_I32__SI__CI 0x00000008 -#define SQ_S_CMPK_LE_I32__VI 0x00000007 -#define SQ_S_CMPK_LE_U32__SI__CI 0x0000000e -#define SQ_S_CMPK_LE_U32__VI 0x0000000d -#define SQ_S_CMPK_LG_I32__SI__CI 0x00000004 -#define SQ_S_CMPK_LG_I32__VI 0x00000003 -#define SQ_S_CMPK_LG_U32__SI__CI 0x0000000a -#define SQ_S_CMPK_LG_U32__VI 0x00000009 -#define SQ_S_CMPK_LT_I32__SI__CI 0x00000007 -#define SQ_S_CMPK_LT_I32__VI 0x00000006 -#define SQ_S_CMPK_LT_U32__SI__CI 0x0000000d -#define SQ_S_CMPK_LT_U32__VI 0x0000000c -#define SQ_S_CMP_EQ_U64__VI 0x00000012 -#define SQ_S_CMP_LG_U64__VI 0x00000013 -#define SQ_S_DCACHE_INV__SI__CI 0x0000001f -#define SQ_S_DCACHE_INV__VI 0x00000020 -#define SQ_S_DCACHE_INV_VOL__VI 0x00000022 -#define SQ_S_DCACHE_WB__VI 0x00000021 -#define SQ_S_DCACHE_WB_VOL__VI 0x00000023 -#define SQ_S_ENDPGM_SAVED__VI 0x0000001b -#define SQ_S_FF0_I32_B32__SI__CI 0x00000011 -#define SQ_S_FF0_I32_B32__VI 0x0000000e -#define SQ_S_FF0_I32_B64__SI__CI 0x00000012 -#define SQ_S_FF0_I32_B64__VI 0x0000000f -#define SQ_S_FF1_I32_B32__SI__CI 0x00000013 -#define SQ_S_FF1_I32_B32__VI 0x00000010 -#define SQ_S_FF1_I32_B64__SI__CI 0x00000014 -#define SQ_S_FF1_I32_B64__VI 0x00000011 -#define SQ_S_FLBIT_I32__SI__CI 0x00000017 -#define SQ_S_FLBIT_I32__VI 0x00000014 -#define SQ_S_FLBIT_I32_B32__SI__CI 0x00000015 -#define SQ_S_FLBIT_I32_B32__VI 0x00000012 -#define SQ_S_FLBIT_I32_B64__SI__CI 0x00000016 -#define SQ_S_FLBIT_I32_B64__VI 0x00000013 -#define SQ_S_FLBIT_I32_I64__SI__CI 0x00000018 -#define SQ_S_FLBIT_I32_I64__VI 0x00000015 -#define SQ_S_GETPC_B64__SI__CI 0x0000001f -#define SQ_S_GETPC_B64__VI 0x0000001c -#define SQ_S_GETREG_B32__SI__CI 0x00000012 -#define SQ_S_GETREG_B32__VI 0x00000011 -#define SQ_S_GETREG_REGRD_B32__SI__CI 0x00000014 -#define SQ_S_GETREG_REGRD_B32__VI 0x00000013 -#define SQ_S_LSHL_B32__SI__CI 0x0000001e -#define SQ_S_LSHL_B32__VI 0x0000001c -#define SQ_S_LSHL_B64__SI__CI 0x0000001f -#define SQ_S_LSHL_B64__VI 0x0000001d -#define SQ_S_LSHR_B32__SI__CI 0x00000020 -#define SQ_S_LSHR_B32__VI 0x0000001e -#define SQ_S_LSHR_B64__SI__CI 0x00000021 -#define SQ_S_LSHR_B64__VI 0x0000001f -#define SQ_S_MEMREALTIME__VI 0x00000025 -#define SQ_S_MEMTIME__SI__CI 0x0000001e -#define SQ_S_MEMTIME__VI 0x00000024 -#define SQ_S_MOVRELD_B32__SI__CI 0x00000030 -#define SQ_S_MOVRELD_B32__VI 0x0000002c -#define SQ_S_MOVRELD_B64__SI__CI 0x00000031 -#define SQ_S_MOVRELD_B64__VI 0x0000002d -#define SQ_S_MOVRELS_B32__SI__CI 0x0000002e -#define SQ_S_MOVRELS_B32__VI 0x0000002a -#define SQ_S_MOVRELS_B64__SI__CI 0x0000002f -#define SQ_S_MOVRELS_B64__VI 0x0000002b -#define SQ_S_MOV_B32__SI__CI 0x00000003 -#define SQ_S_MOV_B32__VI 0x00000000 -#define SQ_S_MOV_B64__SI__CI 0x00000004 -#define SQ_S_MOV_B64__VI 0x00000001 -#define SQ_S_MOV_FED_B32__SI__CI 0x00000035 -#define SQ_S_MOV_FED_B32__VI 0x00000031 -#define SQ_S_MOV_REGRD_B32__SI__CI 0x00000033 -#define SQ_S_MOV_REGRD_B32__VI 0x0000002f -#define SQ_S_MULK_I32__SI__CI 0x00000010 -#define SQ_S_MULK_I32__VI 0x0000000f -#define SQ_S_MUL_I32__SI__CI 0x00000026 -#define SQ_S_MUL_I32__VI 0x00000024 -#define SQ_S_NAND_B32__SI__CI 0x00000018 -#define SQ_S_NAND_B32__VI 0x00000016 -#define SQ_S_NAND_B64__SI__CI 0x00000019 -#define SQ_S_NAND_B64__VI 0x00000017 -#define SQ_S_NAND_SAVEEXEC_B64__SI__CI 0x00000029 -#define SQ_S_NAND_SAVEEXEC_B64__VI 0x00000025 -#define SQ_S_NOR_B32__SI__CI 0x0000001a -#define SQ_S_NOR_B32__VI 0x00000018 -#define SQ_S_NOR_B64__SI__CI 0x0000001b -#define SQ_S_NOR_B64__VI 0x00000019 -#define SQ_S_NOR_SAVEEXEC_B64__SI__CI 0x0000002a -#define SQ_S_NOR_SAVEEXEC_B64__VI 0x00000026 -#define SQ_S_NOT_B32__SI__CI 0x00000007 -#define SQ_S_NOT_B32__VI 0x00000004 -#define SQ_S_NOT_B64__SI__CI 0x00000008 -#define SQ_S_NOT_B64__VI 0x00000005 -#define SQ_S_ORN2_B32__SI__CI 0x00000016 -#define SQ_S_ORN2_B32__VI 0x00000014 -#define SQ_S_ORN2_B64__SI__CI 0x00000017 -#define SQ_S_ORN2_B64__VI 0x00000015 -#define SQ_S_ORN2_SAVEEXEC_B64__SI__CI 0x00000028 -#define SQ_S_ORN2_SAVEEXEC_B64__VI 0x00000024 -#define SQ_S_OR_B32__SI__CI 0x00000010 -#define SQ_S_OR_B32__VI 0x0000000e -#define SQ_S_OR_B64__SI__CI 0x00000011 -#define SQ_S_OR_B64__VI 0x0000000f -#define SQ_S_OR_SAVEEXEC_B64__SI__CI 0x00000025 -#define SQ_S_OR_SAVEEXEC_B64__VI 0x00000021 -#define SQ_S_QUADMASK_B32__SI__CI 0x0000002c -#define SQ_S_QUADMASK_B32__VI 0x00000028 -#define SQ_S_QUADMASK_B64__SI__CI 0x0000002d -#define SQ_S_QUADMASK_B64__VI 0x00000029 -#define SQ_S_RFE_B64__SI__CI 0x00000022 -#define SQ_S_RFE_B64__VI 0x0000001f -#define SQ_S_RFE_RESTORE_B64__VI 0x0000002b -#define SQ_S_SETPC_B64__SI__CI 0x00000020 -#define SQ_S_SETPC_B64__VI 0x0000001d -#define SQ_S_SETREG_B32__SI__CI 0x00000013 -#define SQ_S_SETREG_B32__VI 0x00000012 -#define SQ_S_SETREG_IMM32_B32__SI__CI 0x00000015 -#define SQ_S_SETREG_IMM32_B32__VI 0x00000014 -#define SQ_S_SET_GPR_IDX_IDX__VI 0x00000032 -#define SQ_S_SET_GPR_IDX_MODE__VI 0x0000001d -#define SQ_S_SET_GPR_IDX_OFF__VI 0x0000001c -#define SQ_S_SET_GPR_IDX_ON__VI 0x00000011 -#define SQ_S_SEXT_I32_I16__SI__CI 0x0000001a -#define SQ_S_SEXT_I32_I16__VI 0x00000017 -#define SQ_S_SEXT_I32_I8__SI__CI 0x00000019 -#define SQ_S_SEXT_I32_I8__VI 0x00000016 -#define SQ_S_STORE_DWORD__VI 0x00000010 -#define SQ_S_STORE_DWORDX2__VI 0x00000011 -#define SQ_S_STORE_DWORDX4__VI 0x00000012 -#define SQ_S_SWAPPC_B64__SI__CI 0x00000021 -#define SQ_S_SWAPPC_B64__VI 0x0000001e -#define SQ_S_WAKEUP__VI 0x00000003 -#define SQ_S_WQM_B32__SI__CI 0x00000009 -#define SQ_S_WQM_B32__VI 0x00000006 -#define SQ_S_WQM_B64__SI__CI 0x0000000a -#define SQ_S_WQM_B64__VI 0x00000007 -#define SQ_S_XNOR_B32__SI__CI 0x0000001c -#define SQ_S_XNOR_B32__VI 0x0000001a -#define SQ_S_XNOR_B64__SI__CI 0x0000001d -#define SQ_S_XNOR_B64__VI 0x0000001b -#define SQ_S_XNOR_SAVEEXEC_B64__SI__CI 0x0000002b -#define SQ_S_XNOR_SAVEEXEC_B64__VI 0x00000027 -#define SQ_S_XOR_B32__SI__CI 0x00000012 -#define SQ_S_XOR_B32__VI 0x00000010 -#define SQ_S_XOR_B64__SI__CI 0x00000013 -#define SQ_S_XOR_B64__VI 0x00000011 -#define SQ_S_XOR_SAVEEXEC_B64__SI__CI 0x00000026 -#define SQ_S_XOR_SAVEEXEC_B64__VI 0x00000022 -#define SQ_TBUFFER_LOAD_FORMAT_D16_X__VI 0x00000008 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XY__VI 0x00000009 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ__VI 0x0000000a -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW__VI 0x0000000b -#define SQ_TBUFFER_STORE_FORMAT_D16_X__VI 0x0000000c -#define SQ_TBUFFER_STORE_FORMAT_D16_XY__VI 0x0000000d -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ__VI 0x0000000e -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW__VI 0x0000000f -#define SQ_V_ADDC_U32__SI__CI 0x00000028 -#define SQ_V_ADDC_U32__VI 0x0000001c -#define SQ_V_ADD_F16__VI 0x0000001f -#define SQ_V_ADD_F32__SI__CI 0x00000003 -#define SQ_V_ADD_F32__VI 0x00000001 -#define SQ_V_ADD_F64__SI__CI 0x00000164 -#define SQ_V_ADD_F64__VI 0x00000280 -#define SQ_V_ADD_U16__VI 0x00000026 -#define SQ_V_ADD_U32__VI 0x00000019 -#define SQ_V_ALIGNBIT_B32__SI__CI 0x0000014e -#define SQ_V_ALIGNBIT_B32__VI 0x000001ce -#define SQ_V_ALIGNBYTE_B32__SI__CI 0x0000014f -#define SQ_V_ALIGNBYTE_B32__VI 0x000001cf -#define SQ_V_AND_B32__SI__CI 0x0000001b -#define SQ_V_AND_B32__VI 0x00000013 -#define SQ_V_ASHRREV_I16__VI 0x0000002c -#define SQ_V_ASHRREV_I32__SI__CI 0x00000018 -#define SQ_V_ASHRREV_I32__VI 0x00000011 -#define SQ_V_ASHRREV_I64__VI 0x00000291 -#define SQ_V_BCNT_U32_B32__SI__CI 0x00000022 -#define SQ_V_BCNT_U32_B32__VI 0x0000028b -#define SQ_V_BFE_I32__SI__CI 0x00000149 -#define SQ_V_BFE_I32__VI 0x000001c9 -#define SQ_V_BFE_U32__SI__CI 0x00000148 -#define SQ_V_BFE_U32__VI 0x000001c8 -#define SQ_V_BFI_B32__SI__CI 0x0000014a -#define SQ_V_BFI_B32__VI 0x000001ca -#define SQ_V_BFM_B32__SI__CI 0x0000001e -#define SQ_V_BFM_B32__VI 0x00000293 -#define SQ_V_BFREV_B32__SI__CI 0x00000038 -#define SQ_V_BFREV_B32__VI 0x0000002c -#define SQ_V_CEIL_F16__VI 0x00000045 -#define SQ_V_CEIL_F32__SI__CI 0x00000022 -#define SQ_V_CEIL_F32__VI 0x0000001d -#define SQ_V_CLREXCP__SI__CI 0x00000041 -#define SQ_V_CLREXCP__VI 0x00000035 -#define SQ_V_CMPX_CLASS_F16__VI 0x00000015 -#define SQ_V_CMPX_CLASS_F32__SI__CI 0x00000098 -#define SQ_V_CMPX_CLASS_F32__VI 0x00000011 -#define SQ_V_CMPX_CLASS_F64__SI__CI 0x000000b8 -#define SQ_V_CMPX_CLASS_F64__VI 0x00000013 -#define SQ_V_CMPX_EQ_F16__VI 0x00000032 -#define SQ_V_CMPX_EQ_F32__SI__CI 0x00000012 -#define SQ_V_CMPX_EQ_F32__VI 0x00000052 -#define SQ_V_CMPX_EQ_F64__SI__CI 0x00000032 -#define SQ_V_CMPX_EQ_F64__VI 0x00000072 -#define SQ_V_CMPX_EQ_I16__VI 0x000000b2 -#define SQ_V_CMPX_EQ_I32__SI__CI 0x00000092 -#define SQ_V_CMPX_EQ_I32__VI 0x000000d2 -#define SQ_V_CMPX_EQ_I64__SI__CI 0x000000b2 -#define SQ_V_CMPX_EQ_I64__VI 0x000000f2 -#define SQ_V_CMPX_EQ_U16__VI 0x000000ba -#define SQ_V_CMPX_EQ_U32__SI__CI 0x000000d2 -#define SQ_V_CMPX_EQ_U32__VI 0x000000da -#define SQ_V_CMPX_EQ_U64__SI__CI 0x000000f2 -#define SQ_V_CMPX_EQ_U64__VI 0x000000fa -#define SQ_V_CMPX_F_F16__VI 0x00000030 -#define SQ_V_CMPX_F_F32__SI__CI 0x00000010 -#define SQ_V_CMPX_F_F32__VI 0x00000050 -#define SQ_V_CMPX_F_F64__SI__CI 0x00000030 -#define SQ_V_CMPX_F_F64__VI 0x00000070 -#define SQ_V_CMPX_F_I16__VI 0x000000b0 -#define SQ_V_CMPX_F_I32__SI__CI 0x00000090 -#define SQ_V_CMPX_F_I32__VI 0x000000d0 -#define SQ_V_CMPX_F_I64__SI__CI 0x000000b0 -#define SQ_V_CMPX_F_I64__VI 0x000000f0 -#define SQ_V_CMPX_F_U16__VI 0x000000b8 -#define SQ_V_CMPX_F_U32__SI__CI 0x000000d0 -#define SQ_V_CMPX_F_U32__VI 0x000000d8 -#define SQ_V_CMPX_F_U64__SI__CI 0x000000f0 -#define SQ_V_CMPX_F_U64__VI 0x000000f8 -#define SQ_V_CMPX_GE_F16__VI 0x00000036 -#define SQ_V_CMPX_GE_F32__SI__CI 0x00000016 -#define SQ_V_CMPX_GE_F32__VI 0x00000056 -#define SQ_V_CMPX_GE_F64__SI__CI 0x00000036 -#define SQ_V_CMPX_GE_F64__VI 0x00000076 -#define SQ_V_CMPX_GE_I16__VI 0x000000b6 -#define SQ_V_CMPX_GE_I32__SI__CI 0x00000096 -#define SQ_V_CMPX_GE_I32__VI 0x000000d6 -#define SQ_V_CMPX_GE_I64__SI__CI 0x000000b6 -#define SQ_V_CMPX_GE_I64__VI 0x000000f6 -#define SQ_V_CMPX_GE_U16__VI 0x000000be -#define SQ_V_CMPX_GE_U32__SI__CI 0x000000d6 -#define SQ_V_CMPX_GE_U32__VI 0x000000de -#define SQ_V_CMPX_GE_U64__SI__CI 0x000000f6 -#define SQ_V_CMPX_GE_U64__VI 0x000000fe -#define SQ_V_CMPX_GT_F16__VI 0x00000034 -#define SQ_V_CMPX_GT_F32__SI__CI 0x00000014 -#define SQ_V_CMPX_GT_F32__VI 0x00000054 -#define SQ_V_CMPX_GT_F64__SI__CI 0x00000034 -#define SQ_V_CMPX_GT_F64__VI 0x00000074 -#define SQ_V_CMPX_GT_I16__VI 0x000000b4 -#define SQ_V_CMPX_GT_I32__SI__CI 0x00000094 -#define SQ_V_CMPX_GT_I32__VI 0x000000d4 -#define SQ_V_CMPX_GT_I64__SI__CI 0x000000b4 -#define SQ_V_CMPX_GT_I64__VI 0x000000f4 -#define SQ_V_CMPX_GT_U16__VI 0x000000bc -#define SQ_V_CMPX_GT_U32__SI__CI 0x000000d4 -#define SQ_V_CMPX_GT_U32__VI 0x000000dc -#define SQ_V_CMPX_GT_U64__SI__CI 0x000000f4 -#define SQ_V_CMPX_GT_U64__VI 0x000000fc -#define SQ_V_CMPX_LE_F16__VI 0x00000033 -#define SQ_V_CMPX_LE_F32__SI__CI 0x00000013 -#define SQ_V_CMPX_LE_F32__VI 0x00000053 -#define SQ_V_CMPX_LE_F64__SI__CI 0x00000033 -#define SQ_V_CMPX_LE_F64__VI 0x00000073 -#define SQ_V_CMPX_LE_I16__VI 0x000000b3 -#define SQ_V_CMPX_LE_I32__SI__CI 0x00000093 -#define SQ_V_CMPX_LE_I32__VI 0x000000d3 -#define SQ_V_CMPX_LE_I64__SI__CI 0x000000b3 -#define SQ_V_CMPX_LE_I64__VI 0x000000f3 -#define SQ_V_CMPX_LE_U16__VI 0x000000bb -#define SQ_V_CMPX_LE_U32__SI__CI 0x000000d3 -#define SQ_V_CMPX_LE_U32__VI 0x000000db -#define SQ_V_CMPX_LE_U64__SI__CI 0x000000f3 -#define SQ_V_CMPX_LE_U64__VI 0x000000fb -#define SQ_V_CMPX_LG_F16__VI 0x00000035 -#define SQ_V_CMPX_LG_F32__SI__CI 0x00000015 -#define SQ_V_CMPX_LG_F32__VI 0x00000055 -#define SQ_V_CMPX_LG_F64__SI__CI 0x00000035 -#define SQ_V_CMPX_LG_F64__VI 0x00000075 -#define SQ_V_CMPX_LT_F16__VI 0x00000031 -#define SQ_V_CMPX_LT_F32__SI__CI 0x00000011 -#define SQ_V_CMPX_LT_F32__VI 0x00000051 -#define SQ_V_CMPX_LT_F64__SI__CI 0x00000031 -#define SQ_V_CMPX_LT_F64__VI 0x00000071 -#define SQ_V_CMPX_LT_I16__VI 0x000000b1 -#define SQ_V_CMPX_LT_I32__SI__CI 0x00000091 -#define SQ_V_CMPX_LT_I32__VI 0x000000d1 -#define SQ_V_CMPX_LT_I64__SI__CI 0x000000b1 -#define SQ_V_CMPX_LT_I64__VI 0x000000f1 -#define SQ_V_CMPX_LT_U16__VI 0x000000b9 -#define SQ_V_CMPX_LT_U32__SI__CI 0x000000d1 -#define SQ_V_CMPX_LT_U32__VI 0x000000d9 -#define SQ_V_CMPX_LT_U64__SI__CI 0x000000f1 -#define SQ_V_CMPX_LT_U64__VI 0x000000f9 -#define SQ_V_CMPX_NEQ_F16__VI 0x0000003d -#define SQ_V_CMPX_NEQ_F32__SI__CI 0x0000001d -#define SQ_V_CMPX_NEQ_F32__VI 0x0000005d -#define SQ_V_CMPX_NEQ_F64__SI__CI 0x0000003d -#define SQ_V_CMPX_NEQ_F64__VI 0x0000007d -#define SQ_V_CMPX_NE_I16__VI 0x000000b5 -#define SQ_V_CMPX_NE_I32__SI__CI 0x00000095 -#define SQ_V_CMPX_NE_I32__VI 0x000000d5 -#define SQ_V_CMPX_NE_I64__SI__CI 0x000000b5 -#define SQ_V_CMPX_NE_I64__VI 0x000000f5 -#define SQ_V_CMPX_NE_U16__VI 0x000000bd -#define SQ_V_CMPX_NE_U32__SI__CI 0x000000d5 -#define SQ_V_CMPX_NE_U32__VI 0x000000dd -#define SQ_V_CMPX_NE_U64__SI__CI 0x000000f5 -#define SQ_V_CMPX_NE_U64__VI 0x000000fd -#define SQ_V_CMPX_NGE_F16__VI 0x00000039 -#define SQ_V_CMPX_NGE_F32__SI__CI 0x00000019 -#define SQ_V_CMPX_NGE_F32__VI 0x00000059 -#define SQ_V_CMPX_NGE_F64__SI__CI 0x00000039 -#define SQ_V_CMPX_NGE_F64__VI 0x00000079 -#define SQ_V_CMPX_NGT_F16__VI 0x0000003b -#define SQ_V_CMPX_NGT_F32__SI__CI 0x0000001b -#define SQ_V_CMPX_NGT_F32__VI 0x0000005b -#define SQ_V_CMPX_NGT_F64__SI__CI 0x0000003b -#define SQ_V_CMPX_NGT_F64__VI 0x0000007b -#define SQ_V_CMPX_NLE_F16__VI 0x0000003c -#define SQ_V_CMPX_NLE_F32__SI__CI 0x0000001c -#define SQ_V_CMPX_NLE_F32__VI 0x0000005c -#define SQ_V_CMPX_NLE_F64__SI__CI 0x0000003c -#define SQ_V_CMPX_NLE_F64__VI 0x0000007c -#define SQ_V_CMPX_NLG_F16__VI 0x0000003a -#define SQ_V_CMPX_NLG_F32__SI__CI 0x0000001a -#define SQ_V_CMPX_NLG_F32__VI 0x0000005a -#define SQ_V_CMPX_NLG_F64__SI__CI 0x0000003a -#define SQ_V_CMPX_NLG_F64__VI 0x0000007a -#define SQ_V_CMPX_NLT_F16__VI 0x0000003e -#define SQ_V_CMPX_NLT_F32__SI__CI 0x0000001e -#define SQ_V_CMPX_NLT_F32__VI 0x0000005e -#define SQ_V_CMPX_NLT_F64__SI__CI 0x0000003e -#define SQ_V_CMPX_NLT_F64__VI 0x0000007e -#define SQ_V_CMPX_O_F16__VI 0x00000037 -#define SQ_V_CMPX_O_F32__SI__CI 0x00000017 -#define SQ_V_CMPX_O_F32__VI 0x00000057 -#define SQ_V_CMPX_O_F64__SI__CI 0x00000037 -#define SQ_V_CMPX_O_F64__VI 0x00000077 -#define SQ_V_CMPX_TRU_F16__VI 0x0000003f -#define SQ_V_CMPX_TRU_F32__SI__CI 0x0000001f -#define SQ_V_CMPX_TRU_F32__VI 0x0000005f -#define SQ_V_CMPX_TRU_F64__SI__CI 0x0000003f -#define SQ_V_CMPX_TRU_F64__VI 0x0000007f -#define SQ_V_CMPX_T_I16__VI 0x000000b7 -#define SQ_V_CMPX_T_I32__SI__CI 0x00000097 -#define SQ_V_CMPX_T_I32__VI 0x000000d7 -#define SQ_V_CMPX_T_I64__SI__CI 0x000000b7 -#define SQ_V_CMPX_T_I64__VI 0x000000f7 -#define SQ_V_CMPX_T_U16__VI 0x000000bf -#define SQ_V_CMPX_T_U32__SI__CI 0x000000d7 -#define SQ_V_CMPX_T_U32__VI 0x000000df -#define SQ_V_CMPX_T_U64__SI__CI 0x000000f7 -#define SQ_V_CMPX_T_U64__VI 0x000000ff -#define SQ_V_CMPX_U_F16__VI 0x00000038 -#define SQ_V_CMPX_U_F32__SI__CI 0x00000018 -#define SQ_V_CMPX_U_F32__VI 0x00000058 -#define SQ_V_CMPX_U_F64__SI__CI 0x00000038 -#define SQ_V_CMPX_U_F64__VI 0x00000078 -#define SQ_V_CMP_CLASS_F16__VI 0x00000014 -#define SQ_V_CMP_CLASS_F32__SI__CI 0x00000088 -#define SQ_V_CMP_CLASS_F32__VI 0x00000010 -#define SQ_V_CMP_CLASS_F64__SI__CI 0x000000a8 -#define SQ_V_CMP_CLASS_F64__VI 0x00000012 -#define SQ_V_CMP_EQ_F16__VI 0x00000022 -#define SQ_V_CMP_EQ_F32__SI__CI 0x00000002 -#define SQ_V_CMP_EQ_F32__VI 0x00000042 -#define SQ_V_CMP_EQ_F64__SI__CI 0x00000022 -#define SQ_V_CMP_EQ_F64__VI 0x00000062 -#define SQ_V_CMP_EQ_I16__VI 0x000000a2 -#define SQ_V_CMP_EQ_I32__SI__CI 0x00000082 -#define SQ_V_CMP_EQ_I32__VI 0x000000c2 -#define SQ_V_CMP_EQ_I64__SI__CI 0x000000a2 -#define SQ_V_CMP_EQ_I64__VI 0x000000e2 -#define SQ_V_CMP_EQ_U16__VI 0x000000aa -#define SQ_V_CMP_EQ_U32__SI__CI 0x000000c2 -#define SQ_V_CMP_EQ_U32__VI 0x000000ca -#define SQ_V_CMP_EQ_U64__SI__CI 0x000000e2 -#define SQ_V_CMP_EQ_U64__VI 0x000000ea -#define SQ_V_CMP_F_F16__VI 0x00000020 -#define SQ_V_CMP_F_F32__SI__CI 0x00000000 -#define SQ_V_CMP_F_F32__VI 0x00000040 -#define SQ_V_CMP_F_F64__SI__CI 0x00000020 -#define SQ_V_CMP_F_F64__VI 0x00000060 -#define SQ_V_CMP_F_I16__VI 0x000000a0 -#define SQ_V_CMP_F_I32__SI__CI 0x00000080 -#define SQ_V_CMP_F_I32__VI 0x000000c0 -#define SQ_V_CMP_F_I64__SI__CI 0x000000a0 -#define SQ_V_CMP_F_I64__VI 0x000000e0 -#define SQ_V_CMP_F_U16__VI 0x000000a8 -#define SQ_V_CMP_F_U32__SI__CI 0x000000c0 -#define SQ_V_CMP_F_U32__VI 0x000000c8 -#define SQ_V_CMP_F_U64__SI__CI 0x000000e0 -#define SQ_V_CMP_F_U64__VI 0x000000e8 -#define SQ_V_CMP_GE_F16__VI 0x00000026 -#define SQ_V_CMP_GE_F32__SI__CI 0x00000006 -#define SQ_V_CMP_GE_F32__VI 0x00000046 -#define SQ_V_CMP_GE_F64__SI__CI 0x00000026 -#define SQ_V_CMP_GE_F64__VI 0x00000066 -#define SQ_V_CMP_GE_I16__VI 0x000000a6 -#define SQ_V_CMP_GE_I32__SI__CI 0x00000086 -#define SQ_V_CMP_GE_I32__VI 0x000000c6 -#define SQ_V_CMP_GE_I64__SI__CI 0x000000a6 -#define SQ_V_CMP_GE_I64__VI 0x000000e6 -#define SQ_V_CMP_GE_U16__VI 0x000000ae -#define SQ_V_CMP_GE_U32__SI__CI 0x000000c6 -#define SQ_V_CMP_GE_U32__VI 0x000000ce -#define SQ_V_CMP_GE_U64__SI__CI 0x000000e6 -#define SQ_V_CMP_GE_U64__VI 0x000000ee -#define SQ_V_CMP_GT_F16__VI 0x00000024 -#define SQ_V_CMP_GT_F32__SI__CI 0x00000004 -#define SQ_V_CMP_GT_F32__VI 0x00000044 -#define SQ_V_CMP_GT_F64__SI__CI 0x00000024 -#define SQ_V_CMP_GT_F64__VI 0x00000064 -#define SQ_V_CMP_GT_I16__VI 0x000000a4 -#define SQ_V_CMP_GT_I32__SI__CI 0x00000084 -#define SQ_V_CMP_GT_I32__VI 0x000000c4 -#define SQ_V_CMP_GT_I64__SI__CI 0x000000a4 -#define SQ_V_CMP_GT_I64__VI 0x000000e4 -#define SQ_V_CMP_GT_U16__VI 0x000000ac -#define SQ_V_CMP_GT_U32__SI__CI 0x000000c4 -#define SQ_V_CMP_GT_U32__VI 0x000000cc -#define SQ_V_CMP_GT_U64__SI__CI 0x000000e4 -#define SQ_V_CMP_GT_U64__VI 0x000000ec -#define SQ_V_CMP_LE_F16__VI 0x00000023 -#define SQ_V_CMP_LE_F32__SI__CI 0x00000003 -#define SQ_V_CMP_LE_F32__VI 0x00000043 -#define SQ_V_CMP_LE_F64__SI__CI 0x00000023 -#define SQ_V_CMP_LE_F64__VI 0x00000063 -#define SQ_V_CMP_LE_I16__VI 0x000000a3 -#define SQ_V_CMP_LE_I32__SI__CI 0x00000083 -#define SQ_V_CMP_LE_I32__VI 0x000000c3 -#define SQ_V_CMP_LE_I64__SI__CI 0x000000a3 -#define SQ_V_CMP_LE_I64__VI 0x000000e3 -#define SQ_V_CMP_LE_U16__VI 0x000000ab -#define SQ_V_CMP_LE_U32__SI__CI 0x000000c3 -#define SQ_V_CMP_LE_U32__VI 0x000000cb -#define SQ_V_CMP_LE_U64__SI__CI 0x000000e3 -#define SQ_V_CMP_LE_U64__VI 0x000000eb -#define SQ_V_CMP_LG_F16__VI 0x00000025 -#define SQ_V_CMP_LG_F32__SI__CI 0x00000005 -#define SQ_V_CMP_LG_F32__VI 0x00000045 -#define SQ_V_CMP_LG_F64__SI__CI 0x00000025 -#define SQ_V_CMP_LG_F64__VI 0x00000065 -#define SQ_V_CMP_LT_F16__VI 0x00000021 -#define SQ_V_CMP_LT_F32__SI__CI 0x00000001 -#define SQ_V_CMP_LT_F32__VI 0x00000041 -#define SQ_V_CMP_LT_F64__SI__CI 0x00000021 -#define SQ_V_CMP_LT_F64__VI 0x00000061 -#define SQ_V_CMP_LT_I16__VI 0x000000a1 -#define SQ_V_CMP_LT_I32__SI__CI 0x00000081 -#define SQ_V_CMP_LT_I32__VI 0x000000c1 -#define SQ_V_CMP_LT_I64__SI__CI 0x000000a1 -#define SQ_V_CMP_LT_I64__VI 0x000000e1 -#define SQ_V_CMP_LT_U16__VI 0x000000a9 -#define SQ_V_CMP_LT_U32__SI__CI 0x000000c1 -#define SQ_V_CMP_LT_U32__VI 0x000000c9 -#define SQ_V_CMP_LT_U64__SI__CI 0x000000e1 -#define SQ_V_CMP_LT_U64__VI 0x000000e9 -#define SQ_V_CMP_NEQ_F16__VI 0x0000002d -#define SQ_V_CMP_NEQ_F32__SI__CI 0x0000000d -#define SQ_V_CMP_NEQ_F32__VI 0x0000004d -#define SQ_V_CMP_NEQ_F64__SI__CI 0x0000002d -#define SQ_V_CMP_NEQ_F64__VI 0x0000006d -#define SQ_V_CMP_NE_I16__VI 0x000000a5 -#define SQ_V_CMP_NE_I32__SI__CI 0x00000085 -#define SQ_V_CMP_NE_I32__VI 0x000000c5 -#define SQ_V_CMP_NE_I64__SI__CI 0x000000a5 -#define SQ_V_CMP_NE_I64__VI 0x000000e5 -#define SQ_V_CMP_NE_U16__VI 0x000000ad -#define SQ_V_CMP_NE_U32__SI__CI 0x000000c5 -#define SQ_V_CMP_NE_U32__VI 0x000000cd -#define SQ_V_CMP_NE_U64__SI__CI 0x000000e5 -#define SQ_V_CMP_NE_U64__VI 0x000000ed -#define SQ_V_CMP_NGE_F16__VI 0x00000029 -#define SQ_V_CMP_NGE_F32__SI__CI 0x00000009 -#define SQ_V_CMP_NGE_F32__VI 0x00000049 -#define SQ_V_CMP_NGE_F64__SI__CI 0x00000029 -#define SQ_V_CMP_NGE_F64__VI 0x00000069 -#define SQ_V_CMP_NGT_F16__VI 0x0000002b -#define SQ_V_CMP_NGT_F32__SI__CI 0x0000000b -#define SQ_V_CMP_NGT_F32__VI 0x0000004b -#define SQ_V_CMP_NGT_F64__SI__CI 0x0000002b -#define SQ_V_CMP_NGT_F64__VI 0x0000006b -#define SQ_V_CMP_NLE_F16__VI 0x0000002c -#define SQ_V_CMP_NLE_F32__SI__CI 0x0000000c -#define SQ_V_CMP_NLE_F32__VI 0x0000004c -#define SQ_V_CMP_NLE_F64__SI__CI 0x0000002c -#define SQ_V_CMP_NLE_F64__VI 0x0000006c -#define SQ_V_CMP_NLG_F16__VI 0x0000002a -#define SQ_V_CMP_NLG_F32__SI__CI 0x0000000a -#define SQ_V_CMP_NLG_F32__VI 0x0000004a -#define SQ_V_CMP_NLG_F64__SI__CI 0x0000002a -#define SQ_V_CMP_NLG_F64__VI 0x0000006a -#define SQ_V_CMP_NLT_F16__VI 0x0000002e -#define SQ_V_CMP_NLT_F32__SI__CI 0x0000000e -#define SQ_V_CMP_NLT_F32__VI 0x0000004e -#define SQ_V_CMP_NLT_F64__SI__CI 0x0000002e -#define SQ_V_CMP_NLT_F64__VI 0x0000006e -#define SQ_V_CMP_O_F16__VI 0x00000027 -#define SQ_V_CMP_O_F32__SI__CI 0x00000007 -#define SQ_V_CMP_O_F32__VI 0x00000047 -#define SQ_V_CMP_O_F64__SI__CI 0x00000027 -#define SQ_V_CMP_O_F64__VI 0x00000067 -#define SQ_V_CMP_TRU_F16__VI 0x0000002f -#define SQ_V_CMP_TRU_F32__SI__CI 0x0000000f -#define SQ_V_CMP_TRU_F32__VI 0x0000004f -#define SQ_V_CMP_TRU_F64__SI__CI 0x0000002f -#define SQ_V_CMP_TRU_F64__VI 0x0000006f -#define SQ_V_CMP_T_I16__VI 0x000000a7 -#define SQ_V_CMP_T_I32__SI__CI 0x00000087 -#define SQ_V_CMP_T_I32__VI 0x000000c7 -#define SQ_V_CMP_T_I64__SI__CI 0x000000a7 -#define SQ_V_CMP_T_I64__VI 0x000000e7 -#define SQ_V_CMP_T_U16__VI 0x000000af -#define SQ_V_CMP_T_U32__SI__CI 0x000000c7 -#define SQ_V_CMP_T_U32__VI 0x000000cf -#define SQ_V_CMP_T_U64__SI__CI 0x000000e7 -#define SQ_V_CMP_T_U64__VI 0x000000ef -#define SQ_V_CMP_U_F16__VI 0x00000028 -#define SQ_V_CMP_U_F32__SI__CI 0x00000008 -#define SQ_V_CMP_U_F32__VI 0x00000048 -#define SQ_V_CMP_U_F64__SI__CI 0x00000028 -#define SQ_V_CMP_U_F64__VI 0x00000068 -#define SQ_V_COS_F16__VI 0x0000004a -#define SQ_V_COS_F32__SI__CI 0x00000036 -#define SQ_V_COS_F32__VI 0x0000002a -#define SQ_V_CUBEID_F32__SI__CI 0x00000144 -#define SQ_V_CUBEID_F32__VI 0x000001c4 -#define SQ_V_CUBEMA_F32__SI__CI 0x00000147 -#define SQ_V_CUBEMA_F32__VI 0x000001c7 -#define SQ_V_CUBESC_F32__SI__CI 0x00000145 -#define SQ_V_CUBESC_F32__VI 0x000001c5 -#define SQ_V_CUBETC_F32__SI__CI 0x00000146 -#define SQ_V_CUBETC_F32__VI 0x000001c6 -#define SQ_V_CVT_F16_I16__VI 0x0000003a -#define SQ_V_CVT_F16_U16__VI 0x00000039 -#define SQ_V_CVT_I16_F16__VI 0x0000003c -#define SQ_V_CVT_NORM_I16_F16__VI 0x0000004d -#define SQ_V_CVT_NORM_U16_F16__VI 0x0000004e -#define SQ_V_CVT_PKACCUM_U8_F32__SI__CI 0x0000002c -#define SQ_V_CVT_PKACCUM_U8_F32__VI 0x000001f0 -#define SQ_V_CVT_PKNORM_I16_F16__VI 0x00000299 -#define SQ_V_CVT_PKNORM_I16_F32__SI__CI 0x0000002d -#define SQ_V_CVT_PKNORM_I16_F32__VI 0x00000294 -#define SQ_V_CVT_PKNORM_U16_F16__VI 0x0000029a -#define SQ_V_CVT_PKNORM_U16_F32__SI__CI 0x0000002e -#define SQ_V_CVT_PKNORM_U16_F32__VI 0x00000295 -#define SQ_V_CVT_PKRTZ_F16_F32__SI__CI 0x0000002f -#define SQ_V_CVT_PKRTZ_F16_F32__VI 0x00000296 -#define SQ_V_CVT_PK_I16_I32__SI__CI 0x00000031 -#define SQ_V_CVT_PK_I16_I32__VI 0x00000298 -#define SQ_V_CVT_PK_U16_U32__SI__CI 0x00000030 -#define SQ_V_CVT_PK_U16_U32__VI 0x00000297 -#define SQ_V_CVT_PK_U8_F32__SI__CI 0x0000015e -#define SQ_V_CVT_PK_U8_F32__VI 0x000001dd -#define SQ_V_CVT_U16_F16__VI 0x0000003b -#define SQ_V_DIV_FIXUP_F16__VI 0x000001ef -#define SQ_V_DIV_FIXUP_F32__SI__CI 0x0000015f -#define SQ_V_DIV_FIXUP_F32__VI 0x000001de -#define SQ_V_DIV_FIXUP_F64__SI__CI 0x00000160 -#define SQ_V_DIV_FIXUP_F64__VI 0x000001df -#define SQ_V_DIV_FMAS_F32__SI__CI 0x0000016f -#define SQ_V_DIV_FMAS_F32__VI 0x000001e2 -#define SQ_V_DIV_FMAS_F64__SI__CI 0x00000170 -#define SQ_V_DIV_FMAS_F64__VI 0x000001e3 -#define SQ_V_DIV_SCALE_F32__SI__CI 0x0000016d -#define SQ_V_DIV_SCALE_F32__VI 0x000001e0 -#define SQ_V_DIV_SCALE_F64__SI__CI 0x0000016e -#define SQ_V_DIV_SCALE_F64__VI 0x000001e1 -#define SQ_V_EXP_F16__VI 0x00000041 -#define SQ_V_EXP_F32__SI__CI 0x00000025 -#define SQ_V_EXP_F32__VI 0x00000020 -#define SQ_V_EXP_LEGACY_F32__VI 0x0000004b -#define SQ_V_FFBH_I32__SI__CI 0x0000003b -#define SQ_V_FFBH_I32__VI 0x0000002f -#define SQ_V_FFBH_U32__SI__CI 0x00000039 -#define SQ_V_FFBH_U32__VI 0x0000002d -#define SQ_V_FFBL_B32__SI__CI 0x0000003a -#define SQ_V_FFBL_B32__VI 0x0000002e -#define SQ_V_FLOOR_F16__VI 0x00000044 -#define SQ_V_FLOOR_F32__SI__CI 0x00000024 -#define SQ_V_FLOOR_F32__VI 0x0000001f -#define SQ_V_FMA_F16__VI 0x000001ee -#define SQ_V_FMA_F32__SI__CI 0x0000014b -#define SQ_V_FMA_F32__VI 0x000001cb -#define SQ_V_FMA_F64__SI__CI 0x0000014c -#define SQ_V_FMA_F64__VI 0x000001cc -#define SQ_V_FRACT_F16__VI 0x00000048 -#define SQ_V_FRACT_F32__SI__CI 0x00000020 -#define SQ_V_FRACT_F32__VI 0x0000001b -#define SQ_V_FRACT_F64__SI__CI 0x0000003e -#define SQ_V_FRACT_F64__VI 0x00000032 -#define SQ_V_FREXP_EXP_I16_F16__VI 0x00000043 -#define SQ_V_FREXP_EXP_I32_F32__SI__CI 0x0000003f -#define SQ_V_FREXP_EXP_I32_F32__VI 0x00000033 -#define SQ_V_FREXP_EXP_I32_F64__SI__CI 0x0000003c -#define SQ_V_FREXP_EXP_I32_F64__VI 0x00000030 -#define SQ_V_FREXP_MANT_F16__VI 0x00000042 -#define SQ_V_FREXP_MANT_F32__SI__CI 0x00000040 -#define SQ_V_FREXP_MANT_F32__VI 0x00000034 -#define SQ_V_FREXP_MANT_F64__SI__CI 0x0000003d -#define SQ_V_FREXP_MANT_F64__VI 0x00000031 -#define SQ_V_INTERP_P1LL_F16__VI 0x00000274 -#define SQ_V_INTERP_P1LV_F16__VI 0x00000275 -#define SQ_V_INTERP_P2_F16__VI 0x00000276 -#define SQ_V_INTRP_COUNT__VI 0x00000004 -#define SQ_V_INTRP_OFFSET__VI 0x00000270 -#define SQ_V_LDEXP_F16__VI 0x00000033 -#define SQ_V_LDEXP_F32__SI__CI 0x0000002b -#define SQ_V_LDEXP_F32__VI 0x00000288 -#define SQ_V_LDEXP_F64__SI__CI 0x00000168 -#define SQ_V_LDEXP_F64__VI 0x00000284 -#define SQ_V_LERP_U8__SI__CI 0x0000014d -#define SQ_V_LERP_U8__VI 0x000001cd -#define SQ_V_LOG_F16__VI 0x00000040 -#define SQ_V_LOG_F32__SI__CI 0x00000027 -#define SQ_V_LOG_F32__VI 0x00000021 -#define SQ_V_LOG_LEGACY_F32__VI 0x0000004c -#define SQ_V_LSHLREV_B16__VI 0x0000002a -#define SQ_V_LSHLREV_B32__SI__CI 0x0000001a -#define SQ_V_LSHLREV_B32__VI 0x00000012 -#define SQ_V_LSHLREV_B64__VI 0x0000028f -#define SQ_V_LSHRREV_B16__VI 0x0000002b -#define SQ_V_LSHRREV_B32__SI__CI 0x00000016 -#define SQ_V_LSHRREV_B32__VI 0x00000010 -#define SQ_V_LSHRREV_B64__VI 0x00000290 -#define SQ_V_MAC_F16__VI 0x00000023 -#define SQ_V_MAC_F32__SI__CI 0x0000001f -#define SQ_V_MAC_F32__VI 0x00000016 -#define SQ_V_MAC_LEGACY_F32__SI__CI 0x00000006 -#define SQ_V_MAC_LEGACY_F32__VI 0x0000028e -#define SQ_V_MADAK_F16__VI 0x00000025 -#define SQ_V_MADAK_F32__SI__CI 0x00000021 -#define SQ_V_MADAK_F32__VI 0x00000018 -#define SQ_V_MADMK_F16__VI 0x00000024 -#define SQ_V_MADMK_F32__SI__CI 0x00000020 -#define SQ_V_MADMK_F32__VI 0x00000017 -#define SQ_V_MAD_F16__VI 0x000001ea -#define SQ_V_MAD_F32__SI__CI 0x00000141 -#define SQ_V_MAD_F32__VI 0x000001c1 -#define SQ_V_MAD_I16__VI 0x000001ec -#define SQ_V_MAD_I32_I24__SI__CI 0x00000142 -#define SQ_V_MAD_I32_I24__VI 0x000001c2 -#define SQ_V_MAD_I64_I32__VI 0x000001e9 -#define SQ_V_MAD_LEGACY_F32__SI__CI 0x00000140 -#define SQ_V_MAD_LEGACY_F32__VI 0x000001c0 -#define SQ_V_MAD_U16__VI 0x000001eb -#define SQ_V_MAD_U32_U24__SI__CI 0x00000143 -#define SQ_V_MAD_U32_U24__VI 0x000001c3 -#define SQ_V_MAD_U64_U32__VI 0x000001e8 -#define SQ_V_MAX3_F32__SI__CI 0x00000154 -#define SQ_V_MAX3_F32__VI 0x000001d3 -#define SQ_V_MAX3_I32__SI__CI 0x00000155 -#define SQ_V_MAX3_I32__VI 0x000001d4 -#define SQ_V_MAX3_U32__SI__CI 0x00000156 -#define SQ_V_MAX3_U32__VI 0x000001d5 -#define SQ_V_MAX_F16__VI 0x0000002d -#define SQ_V_MAX_F32__SI__CI 0x00000010 -#define SQ_V_MAX_F32__VI 0x0000000b -#define SQ_V_MAX_F64__SI__CI 0x00000167 -#define SQ_V_MAX_F64__VI 0x00000283 -#define SQ_V_MAX_I16__VI 0x00000030 -#define SQ_V_MAX_I32__SI__CI 0x00000012 -#define SQ_V_MAX_I32__VI 0x0000000d -#define SQ_V_MAX_U16__VI 0x0000002f -#define SQ_V_MAX_U32__SI__CI 0x00000014 -#define SQ_V_MAX_U32__VI 0x0000000f -#define SQ_V_MBCNT_HI_U32_B32__SI__CI 0x00000024 -#define SQ_V_MBCNT_HI_U32_B32__VI 0x0000028d -#define SQ_V_MBCNT_LO_U32_B32__SI__CI 0x00000023 -#define SQ_V_MBCNT_LO_U32_B32__VI 0x0000028c -#define SQ_V_MED3_F32__SI__CI 0x00000157 -#define SQ_V_MED3_F32__VI 0x000001d6 -#define SQ_V_MED3_I32__SI__CI 0x00000158 -#define SQ_V_MED3_I32__VI 0x000001d7 -#define SQ_V_MED3_U32__SI__CI 0x00000159 -#define SQ_V_MED3_U32__VI 0x000001d8 -#define SQ_V_MIN3_F32__SI__CI 0x00000151 -#define SQ_V_MIN3_F32__VI 0x000001d0 -#define SQ_V_MIN3_I32__SI__CI 0x00000152 -#define SQ_V_MIN3_I32__VI 0x000001d1 -#define SQ_V_MIN3_U32__SI__CI 0x00000153 -#define SQ_V_MIN3_U32__VI 0x000001d2 -#define SQ_V_MIN_F16__VI 0x0000002e -#define SQ_V_MIN_F32__SI__CI 0x0000000f -#define SQ_V_MIN_F32__VI 0x0000000a -#define SQ_V_MIN_F64__SI__CI 0x00000166 -#define SQ_V_MIN_F64__VI 0x00000282 -#define SQ_V_MIN_I16__VI 0x00000032 -#define SQ_V_MIN_I32__SI__CI 0x00000011 -#define SQ_V_MIN_I32__VI 0x0000000c -#define SQ_V_MIN_U16__VI 0x00000031 -#define SQ_V_MIN_U32__SI__CI 0x00000013 -#define SQ_V_MIN_U32__VI 0x0000000e -#define SQ_V_MOVRELD_B32__SI__CI 0x00000042 -#define SQ_V_MOVRELD_B32__VI 0x00000036 -#define SQ_V_MOVRELSD_B32__SI__CI 0x00000044 -#define SQ_V_MOVRELSD_B32__VI 0x00000038 -#define SQ_V_MOVRELS_B32__SI__CI 0x00000043 -#define SQ_V_MOVRELS_B32__VI 0x00000037 -#define SQ_V_MQSAD_PK_U16_U8__VI 0x000001e6 -#define SQ_V_MQSAD_U32_U8__VI 0x000001e7 -#define SQ_V_MSAD_U8__SI__CI 0x00000171 -#define SQ_V_MSAD_U8__VI 0x000001e4 -#define SQ_V_MUL_F16__VI 0x00000022 -#define SQ_V_MUL_F32__SI__CI 0x00000008 -#define SQ_V_MUL_F32__VI 0x00000005 -#define SQ_V_MUL_F64__SI__CI 0x00000165 -#define SQ_V_MUL_F64__VI 0x00000281 -#define SQ_V_MUL_HI_I32__SI__CI 0x0000016c -#define SQ_V_MUL_HI_I32__VI 0x00000287 -#define SQ_V_MUL_HI_I32_I24__SI__CI 0x0000000a -#define SQ_V_MUL_HI_I32_I24__VI 0x00000007 -#define SQ_V_MUL_HI_U32__SI__CI 0x0000016a -#define SQ_V_MUL_HI_U32__VI 0x00000286 -#define SQ_V_MUL_HI_U32_U24__SI__CI 0x0000000c -#define SQ_V_MUL_HI_U32_U24__VI 0x00000009 -#define SQ_V_MUL_I32_I24__SI__CI 0x00000009 -#define SQ_V_MUL_I32_I24__VI 0x00000006 -#define SQ_V_MUL_LEGACY_F32__SI__CI 0x00000007 -#define SQ_V_MUL_LEGACY_F32__VI 0x00000004 -#define SQ_V_MUL_LO_U16__VI 0x00000029 -#define SQ_V_MUL_LO_U32__SI__CI 0x00000169 -#define SQ_V_MUL_LO_U32__VI 0x00000285 -#define SQ_V_MUL_U32_U24__SI__CI 0x0000000b -#define SQ_V_MUL_U32_U24__VI 0x00000008 -#define SQ_V_NOT_B32__SI__CI 0x00000037 -#define SQ_V_NOT_B32__VI 0x0000002b -#define SQ_V_OP1_OFFSET__SI__CI 0x00000180 -#define SQ_V_OP1_OFFSET__VI 0x00000140 -#define SQ_V_OP3_2IN_COUNT__VI 0x00000080 -#define SQ_V_OP3_2IN_OFFSET__VI 0x00000280 -#define SQ_V_OP3_3IN_COUNT__VI 0x000000b0 -#define SQ_V_OP3_3IN_OFFSET__VI 0x000001c0 -#define SQ_V_OP3_INTRP_COUNT__VI 0x0000000c -#define SQ_V_OP3_INTRP_OFFSET__VI 0x00000274 -#define SQ_V_OR_B32__SI__CI 0x0000001c -#define SQ_V_OR_B32__VI 0x00000014 -#define SQ_V_PERM_B32__VI 0x000001ed -#define SQ_V_QSAD_PK_U16_U8__VI 0x000001e5 -#define SQ_V_RCP_F16__VI 0x0000003d -#define SQ_V_RCP_F32__SI__CI 0x0000002a -#define SQ_V_RCP_F32__VI 0x00000022 -#define SQ_V_RCP_F64__SI__CI 0x0000002f -#define SQ_V_RCP_F64__VI 0x00000025 -#define SQ_V_RCP_IFLAG_F32__SI__CI 0x0000002b -#define SQ_V_RCP_IFLAG_F32__VI 0x00000023 -#define SQ_V_READLANE_B32__SI__CI 0x00000001 -#define SQ_V_READLANE_B32__VI 0x00000289 -#define SQ_V_RNDNE_F16__VI 0x00000047 -#define SQ_V_RNDNE_F32__SI__CI 0x00000023 -#define SQ_V_RNDNE_F32__VI 0x0000001e -#define SQ_V_RSQ_F16__VI 0x0000003f -#define SQ_V_RSQ_F32__SI__CI 0x0000002e -#define SQ_V_RSQ_F32__VI 0x00000024 -#define SQ_V_RSQ_F64__SI__CI 0x00000031 -#define SQ_V_RSQ_F64__VI 0x00000026 -#define SQ_V_SAD_HI_U8__SI__CI 0x0000015b -#define SQ_V_SAD_HI_U8__VI 0x000001da -#define SQ_V_SAD_U16__SI__CI 0x0000015c -#define SQ_V_SAD_U16__VI 0x000001db -#define SQ_V_SAD_U32__SI__CI 0x0000015d -#define SQ_V_SAD_U32__VI 0x000001dc -#define SQ_V_SAD_U8__SI__CI 0x0000015a -#define SQ_V_SAD_U8__VI 0x000001d9 -#define SQ_V_SIN_F16__VI 0x00000049 -#define SQ_V_SIN_F32__SI__CI 0x00000035 -#define SQ_V_SIN_F32__VI 0x00000029 -#define SQ_V_SQRT_F16__VI 0x0000003e -#define SQ_V_SQRT_F32__SI__CI 0x00000033 -#define SQ_V_SQRT_F32__VI 0x00000027 -#define SQ_V_SQRT_F64__SI__CI 0x00000034 -#define SQ_V_SQRT_F64__VI 0x00000028 -#define SQ_V_SUBBREV_U32__SI__CI 0x0000002a -#define SQ_V_SUBBREV_U32__VI 0x0000001e -#define SQ_V_SUBB_U32__SI__CI 0x00000029 -#define SQ_V_SUBB_U32__VI 0x0000001d -#define SQ_V_SUBREV_F16__VI 0x00000021 -#define SQ_V_SUBREV_F32__SI__CI 0x00000005 -#define SQ_V_SUBREV_F32__VI 0x00000003 -#define SQ_V_SUBREV_U16__VI 0x00000028 -#define SQ_V_SUBREV_U32__VI 0x0000001b -#define SQ_V_SUB_F16__VI 0x00000020 -#define SQ_V_SUB_F32__SI__CI 0x00000004 -#define SQ_V_SUB_F32__VI 0x00000002 -#define SQ_V_SUB_U16__VI 0x00000027 -#define SQ_V_SUB_U32__VI 0x0000001a -#define SQ_V_TRIG_PREOP_F64__SI__CI 0x00000174 -#define SQ_V_TRIG_PREOP_F64__VI 0x00000292 -#define SQ_V_TRUNC_F16__VI 0x00000046 -#define SQ_V_TRUNC_F32__SI__CI 0x00000021 -#define SQ_V_TRUNC_F32__VI 0x0000001c -#define SQ_V_WRITELANE_B32__SI__CI 0x00000002 -#define SQ_V_WRITELANE_B32__VI 0x0000028a -#define SQ_V_XOR_B32__SI__CI 0x0000001d -#define SQ_V_XOR_B32__VI 0x00000015 -#define SQ_XLATE_VOP3_TO_VINTRP_COUNT__VI 0x00000004 -#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET__VI 0x00000270 -#define SQ_XLATE_VOP3_TO_VOP1_COUNT__VI 0x00000080 -#define SQ_XLATE_VOP3_TO_VOP1_OFFSET__VI 0x00000140 -#define SQ_XLATE_VOP3_TO_VOP2_COUNT__VI 0x00000040 -#define SQ_XLATE_VOP3_TO_VOP2_OFFSET__VI 0x00000100 -#define SQ_XLATE_VOP3_TO_VOPC_COUNT__VI 0x00000100 -#define SQ_XLATE_VOP3_TO_VOPC_OFFSET__VI 0x00000000 -#define SQ_XNACK_MASK_HI__VI 0x00000069 -#define SQ_XNACK_MASK_LO__VI 0x00000068 -#define SRCID_SECURE_E__VI 0x0000000e - -#endif diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_mask.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_mask.h deleted file mode 100644 index fd9ae4ab68..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_mask.h +++ /dev/null @@ -1,48849 +0,0 @@ -#if !defined SI_CI_VI_merged_mask_HEADER -#define SI_CI_VI_merged_mask_HEADER - - -// -// Source merge files: -// E:\MergedHeaders\SI+CI+Amur\Original\SICI/si_ci_merged_mask.h -// E:\MergedHeaders\SI+CI+Amur\Original\Amur/vi_mask.h -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -#define ABM_DEBUG_01__DBG_ABM_ENABLE_REQ_MASK__SI 0x00004000L -#define ABM_DEBUG_01__DBG_ABM_ENABLE_RESYNC_MASK__SI 0x00008000L -#define ABM_DEBUG_01__DBG_ABM_ON_CLOCK_RUNNING_MASK__SI 0x00020000L -#define ABM_DEBUG_01__DBG_ABM_SOURCE_SELECT_MASK__SI 0x00010000L -#define ABM_DEBUG_01__DBG_CRTC1_ABM_DATA_ACTIVE_MASK__SI 0x00000400L -#define ABM_DEBUG_01__DBG_CRTC1_ABM_G_COLOR_MASK__SI 0x000000ffL -#define ABM_DEBUG_01__DBG_CRTC1_ABM_HBLANK_MASK__SI 0x00000200L -#define ABM_DEBUG_01__DBG_CRTC1_ABM_VBLANK_MASK__SI 0x00000100L -#define ABM_DEBUG_01__DBG_CRTC1_EN_MASK__SI 0x00000800L -#define ABM_DEBUG_01__DBG_CRTC1_VSYNC_MASK__SI 0x00002000L -#define ABM_DEBUG_01__DBG_CRTC1_VSYNC_POL_MASK__SI 0x00001000L -#define ABM_DEBUG_01__DBG_CRTC2_ABM_DATA_ACTIVE_MASK__SI 0x00200000L -#define ABM_DEBUG_01__DBG_CRTC2_ABM_G_COLOR_MASK__SI 0xff000000L -#define ABM_DEBUG_01__DBG_CRTC2_ABM_HBLANK_MASK__SI 0x00400000L -#define ABM_DEBUG_01__DBG_CRTC2_ABM_VBLANK_MASK__SI 0x00800000L -#define ABM_DEBUG_01__DBG_CRTC2_EN_MASK__SI 0x00100000L -#define ABM_DEBUG_01__DBG_CRTC2_VSYNC_MASK__SI 0x00040000L -#define ABM_DEBUG_01__DBG_CRTC2_VSYNC_POL_MASK__SI 0x00080000L -#define ABM_DEBUG_02__DBG_ABM_ENABLE_RESYNC_MASK__SI 0x00100000L -#define ABM_DEBUG_02__DBG_ABM_FMT_G_COLOR_MASK__SI 0x0000ff00L -#define ABM_DEBUG_02__DBG_ABM_SOURCE_SELECT_MASK__SI 0x00080000L -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_DATA_ACTIVE_MASK__SI 0x00040000L -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_G_COLOR_MASK__SI 0x000000ffL -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_HBLANK_MASK__SI 0x00020000L -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_VBLANK_MASK__SI 0x00010000L -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_DATA_ACTIVE_MASK__SI 0x00200000L -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_G_COLOR_MASK__SI 0xff000000L -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_HBLANK_MASK__SI 0x00400000L -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_VBLANK_MASK__SI 0x00800000L -#define ABM_DEBUG_03__DBG_HG_BIN_SEL_MASK__SI 0x001f0000L -#define ABM_DEBUG_03__DBG_HG_BIN_SEL_VALID_MASK__SI 0x00200000L -#define ABM_DEBUG_03__DBG_IPCSC_DATA_ACTIVE_MASK__SI 0x00002000L -#define ABM_DEBUG_03__DBG_IPCSC_HBLANK_MASK__SI 0x00001000L -#define ABM_DEBUG_03__DBG_IPCSC_IPCSC_SAFE_EN_MASK__SI 0x00000400L -#define ABM_DEBUG_03__DBG_IPCSC_LUMA_DATA_MASK__SI 0x000003ffL -#define ABM_DEBUG_03__DBG_IPCSC_RGB_SEL_MASK__SI 0x0000c000L -#define ABM_DEBUG_03__DBG_IPCSC_VBLANK_MASK__SI 0x00000800L -#define ABM_DEBUG_03__DBG_IPCSC_VMAX_MASK__SI 0xffc00000L -#define ABM_DEBUG_04__DBG_BL_FRAME_COUNT_MASK__SI 0x003fc000L -#define ABM_DEBUG_04__DBG_BL_INTERRUPT_MASK__SI 0x00002000L -#define ABM_DEBUG_04__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_04__DBG_HG_EN_MASK__SI 0x00000008L -#define ABM_DEBUG_04__DBG_HG_FRAME_COUNT_MASK__SI 0x00001fe0L -#define ABM_DEBUG_04__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_04__DBG_HG_INTERRUPT_MASK__SI 0x00000010L -#define ABM_DEBUG_04__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_04__DBG_LS_EN_MASK__SI 0x00400000L -#define ABM_DEBUG_04__DBG_LS_FRAME_COUNT_MASK__SI 0xff000000L -#define ABM_DEBUG_04__DBG_LS_INTERRUPT_MASK__SI 0x00800000L -#define ABM_DEBUG_05__DBG_HG_BIN_SHIFT_FLAG_1_4_MASK__SI 0x0000f000L -#define ABM_DEBUG_05__DBG_HG_BIN_SHIFT_INDEX_1_4_MASK__SI 0xffff0000L -#define ABM_DEBUG_05__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_05__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_05__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_05__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_05__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_06__DBG_HG_BIN_SHIFT_FLAG_5_8_MASK__SI 0x0000f000L -#define ABM_DEBUG_06__DBG_HG_BIN_SHIFT_INDEX_5_8_MASK__SI 0xffff0000L -#define ABM_DEBUG_06__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_06__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_06__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_06__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_06__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_07__DBG_HG_BIN_SHIFT_FLAG_9_12_MASK__SI 0x0000f000L -#define ABM_DEBUG_07__DBG_HG_BIN_SHIFT_INDEX_9_12_MASK__SI 0xffff0000L -#define ABM_DEBUG_07__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_07__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_07__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_07__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_07__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_08__DBG_HG_BIN_SHIFT_FLAG_13_16_MASK__SI 0x0000f000L -#define ABM_DEBUG_08__DBG_HG_BIN_SHIFT_INDEX_13_16_MASK__SI 0xffff0000L -#define ABM_DEBUG_08__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_08__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_08__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_08__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_08__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_09__DBG_HG_BIN_SHIFT_FLAG_17_20_MASK__SI 0x0000f000L -#define ABM_DEBUG_09__DBG_HG_BIN_SHIFT_INDEX_17_20_MASK__SI 0xffff0000L -#define ABM_DEBUG_09__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_09__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_09__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_09__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_09__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_10__DBG_HG_BIN_SHIFT_FLAG_21_24_MASK__SI 0x0000f000L -#define ABM_DEBUG_10__DBG_HG_BIN_SHIFT_INDEX_21_24_MASK__SI 0xffff0000L -#define ABM_DEBUG_10__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_10__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_10__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_10__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_10__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_11__DBG_HG_BIN_SHIFT_FLAG_25_28_MASK__SI 0x0000f000L -#define ABM_DEBUG_11__DBG_HG_BIN_SHIFT_INDEX_25_28_MASK__SI 0xffff0000L -#define ABM_DEBUG_11__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_11__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_11__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_11__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_11__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_12__DBG_HG_BIN_SHIFT_FLAG_29_32_MASK__SI 0x0000f000L -#define ABM_DEBUG_12__DBG_HG_BIN_SHIFT_INDEX_29_32_MASK__SI 0xffff0000L -#define ABM_DEBUG_12__DBG_HG_DATA_ACTIVE_MASK__SI 0x00000004L -#define ABM_DEBUG_12__DBG_HG_FRAME_COUNT_MASK__SI 0x00000ff0L -#define ABM_DEBUG_12__DBG_HG_HBALNK_MASK__SI 0x00000002L -#define ABM_DEBUG_12__DBG_HG_UPDATE_DATA_MASK__SI 0x00000008L -#define ABM_DEBUG_12__DBG_HG_VBLANK_MASK__SI 0x00000001L -#define ABM_DEBUG_ID__ABM_DEBUG_ID_MASK__SI 0xffffffffL -#define ABM_RBBMIF_RDWR_TIMEOUT__ABM_RBBMIF_RD_WR_TIMEOUT_DIS_MASK__SI 0x00000001L -#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define ACP_CONFIG__ACP_RDREQ_URG_MASK__CI 0x00000f00L -#define ACP_CONFIG__ACP_REQ_TRAN_MASK__CI 0x00010000L -#define ACTIVITY_MONITOR__ACTIVITY_READING_MASK__SI 0x0000ffffL -#define ACTIVITY_MONITOR__ACTIVITY_READING_VALID_MASK__SI 0x00010000L -#define ACTIVITY_THRESHOLDS__LOWERING_MASK__SI 0xffff0000L -#define ACTIVITY_THRESHOLDS__RAISING_MASK__SI 0x0000ffffL -#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000L -#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000ffffL -#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000L -#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000ffffL -#define ADC_INT_CTRL__HI_THRESHOLD_INT_EN_MASK__CI__VI 0x00008000L -#define ADC_INT_CTRL__HI_THRESHOLD_MASK__CI__VI 0x000003ffL -#define ADC_INT_CTRL__LO_THRESHOLD_INT_EN_MASK__CI__VI 0x80000000L -#define ADC_INT_CTRL__LO_THRESHOLD_MASK__CI__VI 0x03ff0000L -#define ADC_RANGE__ADC_MAX_MASK__CI__VI 0x000003ffL -#define ADC_RANGE__ADC_MIN_MASK__CI__VI 0x03ff0000L -#define AFMT_60958_0__AFMT_60958_CS_A_MASK__SI 0x00000001L -#define AFMT_60958_0__AFMT_60958_CS_B_MASK__SI 0x00000002L -#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK__SI 0x0000ff00L -#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK__SI 0x00f00000L -#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK__SI 0x30000000L -#define AFMT_60958_0__AFMT_60958_CS_C_MASK__SI 0x00000004L -#define AFMT_60958_0__AFMT_60958_CS_D_MASK__SI 0x00000038L -#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK__SI 0x000000c0L -#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK__SI 0x0f000000L -#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK__SI 0x000f0000L -#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK__SI 0x00f00000L -#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK__SI 0x000000f0L -#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK__SI 0x0000000fL -#define AFMT_60958_1__AFMT_60958_VALID_L_MASK__SI 0x00010000L -#define AFMT_60958_1__AFMT_60958_VALID_R_MASK__SI 0x00040000L -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK__SI 0x0000000fL -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK__SI 0x000000f0L -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK__SI 0x00000f00L -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK__SI 0x0000f000L -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK__SI 0x000f0000L -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK__SI 0x00f00000L -#define AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK__SI 0x0000ff00L -#define AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK__SI 0x00ff0000L -#define AFMT_ACP__AFMT_ACP_TYPE_MASK__SI 0x00000003L -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK__SI 0x0000f000L -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK__SI 0x00000010L -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK__SI 0xffff0000L -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK__SI 0x00000001L -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK__SI 0x00000100L -#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK__SI 0x00000001L -#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK__SI 0xffffff00L -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK__SI 0x00000700L -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK__SI 0x000000ffL -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK__SI 0x00ff0000L -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK__SI 0x00007800L -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK__SI 0x1f000000L -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK__SI 0x000000ffL -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK__SI 0x00008000L -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK__SI 0x00030000L -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK__SI 0x00007800L -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_CS_SOURCE_MASK__SI 0x00000010L -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK__SI 0x10000000L -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK__SI 0x0000ff00L -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK__SI 0x00000001L -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK__SI 0x00000002L -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK__SI 0x00ff0000L -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK__SI 0x01000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK__SI 0x04000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK__SI 0x01000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK__SI 0x00800000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_MASK_MASK__SI 0x00400000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK__SI 0x00000001L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK__SI 0x00001000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK__SI 0x00004000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK__SI 0x40000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_MASK_MASK__SI 0x08000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_FORMAT_WTRIG_ACK_MASK__SI 0x20000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_FORMAT_WTRIG_MASK_MASK__SI 0x10000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK__SI 0x80000000L -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK__SI 0x00000800L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK__SI 0x00001000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK__SI 0x00000c00L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK__SI 0x000000ffL -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK__SI 0x00c00000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK__SI 0x70000000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK__SI 0x80000000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK__SI 0x00300000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK__SI 0x00008000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK__SI 0x0c000000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK__SI 0x000f0000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK__SI 0x03000000L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK__SI 0x00000300L -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK__SI 0x00006000L -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK__SI 0x00003000L -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK__SI 0x00000080L -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK__SI 0x00000f00L -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK__SI 0xffff0000L -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK__SI 0x0000007fL -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK__SI 0x0000c000L -#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK__SI 0x0000ffffL -#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK__SI 0xffff0000L -#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK__SI 0x0000ffffL -#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK__SI 0xff000000L -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE0_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE1_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE2_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE3_MASK__SI 0xff000000L -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE4_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE5_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE6_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE7_MASK__SI 0xff000000L -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE10_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE11_MASK__SI 0xff000000L -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE8_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE9_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE12_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE13_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE14_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE15_MASK__SI 0xff000000L -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE16_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE17_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE18_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE19_MASK__SI 0xff000000L -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE20_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE21_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE22_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE23_MASK__SI 0xff000000L -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE24_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE25_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE26_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE27_MASK__SI 0xff000000L -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE28_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE29_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE30_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE31_MASK__SI 0xff000000L -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB0_MASK__SI 0x000000ffL -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB1_MASK__SI 0x0000ff00L -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB2_MASK__SI 0x00ff0000L -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB3_MASK__SI 0xff000000L -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE0_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE1_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE2_MASK__SI 0x00ff0000L -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE3_MASK__SI 0xff000000L -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE4_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE5_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE6_MASK__SI 0x00ff0000L -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE7_MASK__SI 0xff000000L -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE10_MASK__SI 0x00ff0000L -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE11_MASK__SI 0xff000000L -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE8_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE9_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE12_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE13_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE14_MASK__SI 0x00ff0000L -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE15_MASK__SI 0xff000000L -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE16_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE17_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE18_MASK__SI 0x00ff0000L -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE19_MASK__SI 0xff000000L -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE20_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE21_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE22_MASK__SI 0x00ff0000L -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE23_MASK__SI 0xff000000L -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE24_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE25_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE26_MASK__SI 0x00ff0000L -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE27_MASK__SI 0xff000000L -#define AFMT_GENERIC1_HDR__AFMT_GENERIC1_HB0_MASK__SI 0x000000ffL -#define AFMT_GENERIC1_HDR__AFMT_GENERIC1_HB1_MASK__SI 0x0000ff00L -#define AFMT_GENERIC1_HDR__AFMT_GENERIC1_HB2_MASK__SI 0x00ff0000L -#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK__SI 0x00000040L -#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK__SI 0x00000080L -#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK__SI 0x00000400L -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_ACK_MASK__SI 0x00000100L -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_INT_MASK__SI 0x00000004L -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_MASK_MASK__SI 0x00000010L -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_OCCURRED_MASK__SI 0x00000002L -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_MASK__SI 0x00000001L -#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK__SI 0x00000040L -#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK__SI 0x00000007L -#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK__SI 0x00000080L -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK__SI 0x000000ffL -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK__SI 0x0000ff00L -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK__SI 0x00ff0000L -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK__SI 0xff000000L -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK__SI 0x000000ffL -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK__SI 0x0000ff00L -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK__SI 0x00ff0000L -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK__SI 0xff000000L -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK__SI 0x00ff0000L -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK__SI 0xff000000L -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK__SI 0x000000ffL -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK__SI 0x0000ff00L -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK__SI 0x000000ffL -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK__SI 0x0000ff00L -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK__SI 0x00ff0000L -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK__SI 0xff000000L -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK__SI 0x000000ffL -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK__SI 0x0000ff00L -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK__SI 0x00ff0000L -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK__SI 0xff000000L -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK__SI 0x000000ffL -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK__SI 0x0000ff00L -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK__SI 0x00ff0000L -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK__SI 0xff000000L -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK__SI 0x000000ffL -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK__SI 0x0000ff00L -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK__SI 0x00ff0000L -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK__SI 0xff000000L -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK__SI 0x000000ffL -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK__SI 0x0000ff00L -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK__SI 0x00ff0000L -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK__SI 0xff000000L -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK__SI 0x000000ffL -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK__SI 0x0000ff00L -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK__SI 0x00ff0000L -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK__SI 0xff000000L -#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK__SI 0x00001000L -#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK__SI 0x000000ffL -#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK__SI 0x00000300L -#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK__SI 0x80000000L -#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK__SI 0x00ffffffL -#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK__SI 0xff000000L -#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK__SI 0x00ffffffL -#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK__SI 0x00ffffffL -#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK__SI 0x00ffffffL -#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK__SI 0x00000010L -#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK__SI 0x01000000L -#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK__SI 0x40000000L -#define AFMT_STATUS__AFMT_AZ_FORMAT_WTRIG_INT_MASK__SI 0x20000000L -#define AFMT_STATUS__AFMT_AZ_FORMAT_WTRIG_MASK__SI 0x10000000L -#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK__SI 0x00000100L -#define AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK__SI 0x00002000L -#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK__SI 0x00000004L -#define ALU_ADDER_INPUTS__ID1C_ALU_ADDER_INPUT1_MASK__SI 0x00003fffL -#define ALU_ADDER_INPUTS__ID1C_ALU_ADDER_INPUT2_MASK__SI 0x0fffc000L -#define ALU_ADDER_INPUTS__ID1C_ALU_CARRY_MASK__SI 0x10000000L -#define ALU_ADDER_INPUTS__ID1C_ALU_START_PULSE_MASK__SI 0x40000000L -#define ALU_ADDER_INPUTS__ID1C_ALU_STATE_MASK__SI 0x20000000L -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_CH_START_PHASE_H_INT_MASK__SI 0xe0000000L -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_H_REP_FAC_MASK__SI 0x1e000000L -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_HEIGHT_MASK__SI 0x003ff800L -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_H_HALF_RES_MASK__SI 0x00400000L -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_ROTATE_MASK__SI 0x01000000L -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_V_HALF_RES_MASK__SI 0x00800000L -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_WIDTH_MASK__SI 0x000007ffL -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_H_FRAC_MASK__SI 0x00007f00L -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_H_INT_MASK__SI 0x000000f0L -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_V_FRAC_BOT_MASK__SI 0xfe000000L -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_V_FRAC_MASK__SI 0x01fc0000L -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_V_INT_MASK__SI 0x00038000L -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_V_REP_FAC_MASK__SI 0x0000000fL -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_H_REP_FAC_MASK__SI 0x00000038L -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_H_SHARP_FAC_MASK__SI 0x000001c0L -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_START_PHASE_V_INT_BOT_MASK__SI 0x00000007L -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_TOP_OVERSCAN_MASK__SI 0x00fff000L -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_V_SHARP_FAC_MASK__SI 0x00000e00L -#define ALU_DISP_PARAM3__ID1F_ALU_DxNUM_H_TAP_MASK__SI 0xf0000000L -#define ALU_DISP_PARAM3__ID1F_ALU_DxNUM_TAP_CHROMA_MASK__SI 0x0f000000L -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_ACTIVE_MASK__SI 0x02000000L -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DISP_LEFT_OVERSCAN_MASK__SI 0x000007ffL -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DISP_RIGHT_OVESCAN_MASK__SI 0x003ff800L -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DONE_MASK__SI 0x01000000L -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DONE_PULSE_MASK__SI 0x80000000L -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_GRANTED_MASK__SI 0x00400000L -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_START_LINE_DEL_MASK__SI 0x20000000L -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_START_LINE_MASK__SI 0x08000000L -#define ALU_DISP_PARAM5__ID23_ALU_DISP_BOT_OVERSCAN_MASK__SI 0x01ffc000L -#define ALU_DISP_PARAM5__ID23_DISP_EOL_MASK__SI 0x40000000L -#define ALU_DISP_PARAM5__ID23_DISP_SOF_MASK__SI 0x80000000L -#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK__CI__VI 0x00003f00L -#define ATC_ATS_CNTL__DEBUG_ECO_MASK__CI__VI 0x000f0000L -#define ATC_ATS_CNTL__DISABLE_ATC_MASK__CI__VI 0x00000001L -#define ATC_ATS_CNTL__DISABLE_PASID_MASK__CI__VI 0x00000004L -#define ATC_ATS_CNTL__DISABLE_PRI_MASK__CI__VI 0x00000002L -#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK__CI__VI 0x00000004L -#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK__CI__VI 0x00020000L -#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK__CI__VI 0x00004000L -#define ATC_ATS_DEBUG__EXE_BIT_MASK__CI__VI 0x00000080L -#define ATC_ATS_DEBUG__IDENT_RETURN_MASK__CI__VI 0x00000002L -#define ATC_ATS_DEBUG__IGNORE_FED_MASK__CI__VI 0x00008000L -#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK__CI__VI 0x00000001L -#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK__CI__VI \ - 0x00010000L -#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK__CI__VI 0x00003c00L -#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK__CI__VI 0x00000020L -#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK__CI__VI 0x00000100L -#define ATC_ATS_DEBUG__PRIV_BIT_MASK__CI__VI 0x00000040L -#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK__CI__VI 0x00000200L -#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK__CI 0x0000003cL -#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK__CI__VI 0x00000001L -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK__CI 0xffffffffL -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK__CI 0x03f00000L -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK__CI 0x0000fc00L -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK__CI 0x0000003fL -#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK__CI__VI 0x00000100L -#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK__CI__VI 0x00010000L -#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK__CI__VI 0x0000001fL -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK__CI__VI 0xffffffffL -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK__CI__VI 0x00010000L -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK__CI__VI 0x00008000L -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK__CI 0x0000003fL -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK__CI__VI 0x00020000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK__CI__VI 0x0f000000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK__CI__VI 0x00040000L -#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK__CI__VI 0x00f80000L -#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK__CI__VI 0x00007c00L -#define ATC_ATS_STATUS__BUSY_MASK__CI__VI 0x00000001L -#define ATC_ATS_STATUS__CRASHED_MASK__CI__VI 0x00000002L -#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK__CI__VI 0x00000004L -#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK__CI__VI 0x0003f000L -#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK__CI__VI 0x0ff00000L -#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK__CI__VI 0x30000000L -#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK__CI__VI 0x80000000L -#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK__CI__VI 0x00000001L -#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK__CI__VI 0x00000002L -#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK__CI__VI 0x000000f0L -#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK__CI__VI 0x00000700L -#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK__CI__VI 0x40000000L -#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK__CI__VI 0x00000100L -#define ATC_L1RD_STATUS__BUSY_MASK__CI__VI 0x00000001L -#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK__CI__VI 0x00000002L -#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK__CI__VI 0x0003f000L -#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK__CI__VI 0x0ff00000L -#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK__CI__VI 0x30000000L -#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK__CI__VI 0x80000000L -#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK__CI__VI 0x00000001L -#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK__CI__VI 0x00000002L -#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK__CI__VI 0x000000f0L -#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK__CI__VI 0x00000700L -#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK__CI__VI 0x40000000L -#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK__CI__VI 0x00000100L -#define ATC_L1WR_STATUS__BUSY_MASK__CI__VI 0x00000001L -#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK__CI__VI 0x00000002L -#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK__CI__VI 0xffffffffL -#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK__CI__VI 0x00000003L -#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK__CI__VI 0x00000004L -#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK__CI__VI 0x00000010L -#define ATC_L2_CNTL2__BANK_SELECT_MASK__CI__VI 0x0000003fL -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK__CI__VI 0x00000100L -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK__CI__VI 0x00000e00L -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK__CI__VI 0x000000c0L -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK__CI__VI 0x001f8000L -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK__CI__VI 0x00007000L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK__CI__VI 0x00000100L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK__CI__VI 0x00000003L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK__CI__VI 0x00000200L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK__CI__VI 0x00000030L -#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK__CI__VI 0x00018000L -#define ATC_L2_DEBUG2__DEBUG_ECO_MASK__CI__VI 0x00060000L -#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK__CI__VI 0x00004000L -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK__CI 0x00000800L -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK__CI 0x00001000L -#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN_MASK__CI 0x00000400L -#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK__CI__VI 0x0000001fL -#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK__CI__VI 0x000000e0L -#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK__CI__VI 0x00000100L -#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK__CI__VI 0x00000200L -#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK__CI__VI 0x0000003fL -#define ATC_MISC_CG__ENABLE_MASK__CI__VI 0x00040000L -#define ATC_MISC_CG__MEM_LS_ENABLE_MASK__CI__VI 0x00080000L -#define ATC_MISC_CG__OFFDLY_MASK__CI__VI 0x00000fc0L -#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define ATC_VMID0_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID0_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID10_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID10_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID11_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID11_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID12_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID12_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID13_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID13_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID14_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID14_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID15_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID15_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID1_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID1_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID2_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID2_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID3_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID3_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID4_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID4_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID5_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID5_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID6_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID6_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID7_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID7_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID8_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID8_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID9_PASID_MAPPING__PASID_MASK__CI__VI 0x0000ffffL -#define ATC_VMID9_PASID_MAPPING__VALID_MASK__CI__VI 0x80000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK__CI__VI 0x00000001L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK__CI__VI 0x00000400L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK__CI__VI 0x00000800L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK__CI__VI 0x00001000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK__CI__VI 0x00002000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK__CI__VI 0x00004000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK__CI__VI 0x00008000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK__CI__VI 0x00000002L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK__CI__VI 0x00000004L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK__CI__VI 0x00000008L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK__CI__VI 0x00000010L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK__CI__VI 0x00000020L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK__CI__VI 0x00000040L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK__CI__VI 0x00000080L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK__CI__VI 0x00000100L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK__CI__VI 0x00000200L -#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK__CI__VI 0x0000ffffL -#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK__CI__VI 0x00000003L -#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK__CI__VI 0x0fffffffL -#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK__CI__VI 0x0fffffffL -#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK__CI__VI 0x0000ffffL -#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK__CI__VI 0x00000003L -#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK__CI__VI 0x0fffffffL -#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK__CI__VI 0x0fffffffL -#define ATTR00__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR01__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR02__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR03__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR04__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR05__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR06__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR07__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR08__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR09__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR0A__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR0B__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR0C__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR0D__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR0E__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR0F__ATTR_PAL_MASK__SI 0x0000003fL -#define ATTR10__ATTR_BLINK_EN_MASK__SI 0x00000008L -#define ATTR10__ATTR_CSEL_EN_MASK__SI 0x00000080L -#define ATTR10__ATTR_GRPH_MODE_MASK__SI 0x00000001L -#define ATTR10__ATTR_LGRPH_EN_MASK__SI 0x00000004L -#define ATTR10__ATTR_MONO_EN_MASK__SI 0x00000002L -#define ATTR10__ATTR_PANTOPONLY_MASK__SI 0x00000020L -#define ATTR10__ATTR_PCLKBY2_MASK__SI 0x00000040L -#define ATTR11__ATTR_OVSC_MASK__SI 0x000000ffL -#define ATTR12__ATTR_MAP_EN_MASK__SI 0x0000000fL -#define ATTR12__ATTR_VSMUX_MASK__SI 0x00000030L -#define ATTR13__ATTR_PPAN_MASK__SI 0x0000000fL -#define ATTR14__ATTR_CSEL1_MASK__SI 0x00000003L -#define ATTR14__ATTR_CSEL2_MASK__SI 0x0000000cL -#define ATTRDR__ATTR_DATA_MASK__SI 0x000000ffL -#define ATTRDW__ATTR_DATA_MASK__SI 0x000000ffL -#define ATTRX__ATTR_IDX_MASK__SI 0x0000001fL -#define ATTRX__ATTR_PAL_RW_ENB_MASK__SI 0x00000020L -#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK__SI 0x00000007L -#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK__SI 0xff000000L -#define AUTH_STATE__STATE_MASK 0x00000007L -#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK__SI 0x00000400L -#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK__SI 0x00000200L -#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK__SI 0x00000100L -#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_POLARITY_MASK__SI 0x00001000L -#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK__SI 0x00000001L -#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK__SI 0x10000000L -#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK__SI 0x0f000000L -#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK__SI 0x00f00000L -#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK__SI 0x000f0000L -#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK__SI 0x00000400L -#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK__SI 0x00000200L -#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK__SI 0x00000100L -#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_POLARITY_MASK__SI 0x00001000L -#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK__SI 0x00000001L -#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK__SI 0x10000000L -#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK__SI 0x0f000000L -#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK__SI 0x00f00000L -#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK__SI 0x000f0000L -#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK__SI 0x00000003L -#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK__SI 0x02000000L -#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK__SI 0x01000000L -#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK__SI 0x01000000L -#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK__SI 0x00000400L -#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK__SI 0x00000100L -#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK__SI 0x0000000cL -#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK__SI 0x00020000L -#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK__SI 0x00010000L -#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK__SI 0x00010000L -#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK__SI 0x20000000L -#define AUX_CONTROL__AUX_EN_MASK__SI 0x00000001L -#define AUX_CONTROL__AUX_HPD_SEL_MASK__SI 0x00700000L -#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK__SI 0x00010000L -#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK__SI 0x01000000L -#define AUX_CONTROL__AUX_LS_READ_EN_MASK__SI 0x00000100L -#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK__SI 0x00001000L -#define AUX_CONTROL__AUX_MODE_DET_EN_MASK__SI 0x00040000L -#define AUX_CONTROL__AUX_TEST_MODE_MASK__SI 0x10000000L -#define AUX_CONTROL__SPARE_0_MASK__SI 0x40000000L -#define AUX_CONTROL__SPARE_1_MASK__SI 0x80000000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK__SI 0x00020000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK__SI 0x00040000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK__SI 0x00080000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK__SI 0x70000000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK__SI 0x00003000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK__SI 0x00300000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK__SI 0x00000700L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK__SI 0x00000070L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK__SI 0x07000000L -#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK__SI 0x00010000L -#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK__SI 0x000000ffL -#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK__SI 0x001f0000L -#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK__SI 0x3fe00000L -#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK__SI 0x00000007L -#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK__SI 0x00001f00L -#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK__SI 0x00000007L -#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK__SI 0x00003f00L -#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK__SI 0x00000030L -#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK__SI 0x01ff0000L -#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK__SI 0x00000001L -#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK__SI 0x00000001L -#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK__SI 0x01ff0000L -#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK__SI 0x00000070L -#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK__SI 0x00000020L -#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK__SI 0x00000010L -#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK__SI 0x00000040L -#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK__SI 0x00000002L -#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK__SI 0x00000001L -#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK__SI 0x00000004L -#define AUX_LS_DATA__AUX_LS_DATA_MASK__SI 0x0000ff00L -#define AUX_LS_DATA__AUX_LS_INDEX_MASK__SI 0x001f0000L -#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK__SI 0x20000000L -#define AUX_LS_STATUS__AUX_LS_DONE_MASK__SI 0x00000001L -#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK__SI 0x00000200L -#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK__SI 0x00000800L -#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK__SI 0x1f000000L -#define AUX_LS_STATUS__AUX_LS_REQ_MASK__SI 0x00000002L -#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK__SI 0x00080000L -#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK__SI 0x00004000L -#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK__SI 0x00001000L -#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK__SI 0x00000100L -#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK__SI 0x00000400L -#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK__SI 0x00400000L -#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK__SI 0x00800000L -#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK__SI 0x00100000L -#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK__SI 0x00040000L -#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK__SI 0x00020000L -#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK__SI 0x00000080L -#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK__SI 0x00000070L -#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK__SI 0x80000000L -#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK__SI 0x40000000L -#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK__SI 0x00000004L -#define AUX_SW_CONTROL__AUX_SW_GO_MASK__SI 0x00000001L -#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK__SI 0x000000f0L -#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK__SI 0x001f0000L -#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK__SI 0x80000000L -#define AUX_SW_DATA__AUX_SW_DATA_MASK__SI 0x0000ff00L -#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK__SI 0x00000001L -#define AUX_SW_DATA__AUX_SW_INDEX_MASK__SI 0x001f0000L -#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK__SI 0xc0000000L -#define AUX_SW_STATUS__AUX_SW_DONE_MASK__SI 0x00000001L -#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK__SI 0x00000200L -#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK__SI 0x00000800L -#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK__SI 0x1f000000L -#define AUX_SW_STATUS__AUX_SW_REQ_MASK__SI 0x00000002L -#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK__SI 0x00080000L -#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK__SI 0x00004000L -#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK__SI 0x00001000L -#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK__SI 0x00000100L -#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK__SI 0x00000400L -#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK__SI 0x00400000L -#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK__SI 0x00800000L -#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK__SI 0x00100000L -#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK__SI 0x00040000L -#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK__SI 0x00020000L -#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK__SI 0x00000080L -#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK__SI 0x00000070L -#define AVP_BCKN_OVL__LINE_ADVANCED_CNT_MASK__SI 0xffff0000L -#define AVP_BCKN_OVL__OVL_UPDATE_TAKEN_MASK__SI 0x00000002L -#define AVP_BCKN_OVL__OVL_VBLANK_MASK__SI 0x00000001L -#define AVP_CONFIG__AVP_RDREQ_URG_MASK__SI 0x00000f00L -#define AVP_CONFIG__AVP_REQ_TRAN_MASK__SI 0x00010000L -#define AVP_RLC_CONTROL__RLC_REQ_ACK_MASK__SI 0x000000f0L -#define AVP_RLC_CONTROL__RLC_REQ_TYPE_MASK__SI 0x0000000fL -#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK__SI \ - 0xffffffffL -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_DTO_SOURCE_SEL_MASK__SI 0x00001000L -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK__SI 0x00000300L -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FS_DIV_SEL_MASK__SI 0x00000070L -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_XTAL_X2_MASK__SI 0x00000001L -#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK__SI 0xffff0000L -#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK__SI 0x0000ffffL -#define AZALIA_BDL_DMA_CONTROL__DBL_DMA_ISOCHRONOUS_MASK__SI 0x00000030L -#define AZALIA_BDL_DMA_CONTROL__DBL_DMA_NON_SNOOP_MASK__SI 0x00000003L -#define AZALIA_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK__SI 0x00000070L -#define AZALIA_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK__SI 0x00000007L -#define AZALIA_CODEC_CONTROL__AZALIA_FORCE_CONSUMER_MODE_MASK__SI 0x00000001L -#define AZALIA_CODEC_CONTROL__WALL_CLOCKS_PER_WRITE_TRIGGER_MASK__SI 0x00000070L -#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK__SI 0x00000010L -#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK__SI 0x00000001L -#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK__SI 0xffffffffL -#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK__SI 0xffffffffL -#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK__SI 0x00000001L -#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK__SI 0x00010000L -#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK__SI 0x00020000L -#define AZALIA_DATA_DMA_CONTROL__DATA_BUFFER_SIZE_MASK__SI 0x00003f00L -#define AZALIA_DATA_DMA_CONTROL__DATA_BUFFER_SIZE_SEL_MASK__SI 0x00008000L -#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK__SI 0x00000030L -#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK__SI 0x00000003L -#define AZALIA_DEBUG_A__AZALIA_DEBUG_A_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_B__AZALIA_DEBUG_B_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_C__AZALIA_DEBUG_C_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_D__AZALIA_DEBUG_D_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_E__AZALIA_DEBUG_E_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_F__AZALIA_DEBUG_F_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_G__AZALIA_DEBUG_G_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_H__AZALIA_DEBUG_H_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_ID__AZALIA_DEBUG_ID_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_I__AZALIA_DEBUG_I_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_J__AZALIA_DEBUG_J_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_K__AZALIA_DEBUG_K_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_L__AZALIA_DEBUG_L_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_M__AZALIA_DEBUG_M_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_N__AZALIA_DEBUG_N_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_O__AZALIA_DEBUG_O_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_P__AZALIA_DEBUG_P_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_Q__AZALIA_DEBUG_Q_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_R__AZALIA_DEBUG_R_MASK__SI 0xffffffffL -#define AZALIA_DEBUG_S__AZALIA_DEBUG_S_MASK__SI 0xffffffffL -#define AZALIA_DEBUG__AZALIA_DEBUG_MASK__SI 0xffffffffL -#define AZALIA_DRM_COMMAND__COMMIT_MASK__SI 0x80000000L -#define AZALIA_DRM_COMMAND__GEN_MASK_MASK__SI 0x00000200L -#define AZALIA_DRM_COMMAND__PACKET_TYPE_MASK__SI 0x00000003L -#define AZALIA_DRM_COMMAND__UNWRAP_KEY_MASK__SI 0x00000100L -#define AZALIA_DRM_MASK_FIFO_STATUS__MASK_FIFO_ACK_MASK__SI 0x00000010L -#define AZALIA_DRM_MASK_FIFO_STATUS__MASK_FIFO_STATUS_MASK__SI 0x00000001L -#define AZALIA_DRM_PAYLOAD0__PAYLOAD0_MASK__SI 0xffffffffL -#define AZALIA_DRM_PAYLOAD1__PAYLOAD1_MASK__SI 0xffffffffL -#define AZALIA_DRM_PAYLOAD2__PAYLOAD2_MASK__SI 0xffffffffL -#define AZALIA_DRM_PAYLOAD3__PAYLOAD3_MASK__SI 0xffffffffL -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK__SI \ - 0x00000010L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI \ - 0x00000400L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK__SI 0xffffffffL -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI \ - 0x00000200L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK__SI \ - 0x00000010L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI \ - 0x00000800L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI \ - 0x00000400L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI \ - 0x00000020L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK__SI 0xffffffffL -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F0_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F0_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F0_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID0_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID1_MASK__SI 0x00000f00L -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID2_MASK__SI 0x000f0000L -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID3_MASK__SI 0x0f000000L -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID0_MASK__SI 0x000000f0L -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID1_MASK__SI 0x0000f000L -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID2_MASK__SI 0x00f00000L -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID3_MASK__SI 0xf0000000L -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK__SI 0x000000f0L -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK__SI \ - 0x000000ffL -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK__SI \ - 0x0000ff00L -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK__SI \ - 0x00ff0000L -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK__SI \ - 0xff000000L -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK__SI \ - 0xffffffffL -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK__SI \ - 0xffffffffL -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK__SI \ - 0xffffffffL -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK__SI \ - 0xffffffffL -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_INDEX_MASK__SI 0x0000003fL -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK__SI 0xff000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_TYPE_MASK__SI 0x00000300L -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__SUPPORTS_AI_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK__SI \ - 0xff000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK__SI 0x80000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK__SI 0x00020000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK__SI 0x00fc0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK__SI 0x00010000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK__SI 0x78000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK__SI 0x0000007fL -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE_CHANGED_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_CAPABLE_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_DISABLE_UR_CAPABLE_MASK__SI 0x00000004L -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_ENABLE_UR_CAPABLE_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE_CHANGED_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_CAPABLE_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_DISABLE_UR_CAPABLE_MASK__SI 0x00000004L -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ENABLE_UR_CAPABLE_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_REQUIRED_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK__SI \ - 0x000000f0L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK__SI \ - 0x0000f000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK__SI 0x00000100L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK__SI \ - 0x00f00000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK__SI 0x00010000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK__SI \ - 0xf0000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK__SI 0x01000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY0_ID_MASK__SI 0x000000fcL -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY0_TYPE_MASK__SI 0x00000003L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY1_ID_MASK__SI 0x0000fc00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY1_TYPE_MASK__SI 0x00000300L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY2_ID_MASK__SI 0x00fc0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY2_TYPE_MASK__SI 0x00030000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY3_ID_MASK__SI 0xfc000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY3_TYPE_MASK__SI 0x03000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY4_ID_MASK__SI 0x000000fcL -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY4_TYPE_MASK__SI 0x00000003L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY5_ID_MASK__SI 0x0000fc00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY5_TYPE_MASK__SI 0x00000300L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER__NUMBER_OF_DISPLAY_ID_MASK__SI 0x00000007L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK__SI 0x000000ffL -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI 0x00000400L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK__SI 0x00010000L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__HDMI_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK__SI 0x00000008L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK__SI 0x00000004L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI \ - 0x00000400L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK__SI 0x00010000L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__HDMI_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK__SI 0x00000008L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK__SI 0x00000020L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK__SI \ - 0x00000004L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK__SI 0x00000010L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK__SI 0x00000002L -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK__SI 0x0000ff00L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_MASK__SI \ - 0x000000ffL -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_MASK__SI \ - 0x0000ff00L -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_MASK__SI \ - 0x00ff0000L -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_MASK__SI \ - 0xff000000L -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE0_MASK__SI 0x00000080L -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE1_MASK__SI 0x00008000L -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE2_MASK__SI 0x00800000L -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE3_MASK__SI 0x80000000L -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG0_MASK__SI 0x0000003fL -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG1_MASK__SI 0x00003f00L -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG2_MASK__SI 0x003f0000L -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG3_MASK__SI 0x3f000000L -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE0_MASK__SI 0x00000040L -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE1_MASK__SI 0x00004000L -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE2_MASK__SI 0x00400000L -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE3_MASK__SI 0x40000000L -#define AZALIA_F0_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__AZALIA_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_MASK__SI \ - 0xffffffffL -#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK__SI \ - 0xffffffffL -#define AZALIA_F0_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK__SI \ - 0xffffffffL -#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER_2__CC_MASK__SI 0x0000007fL -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK__SI \ - 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI \ - 0x00000400L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK__SI 0xffffffffL -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER_2__CC_MASK__SI 0x0000007fL -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK__SI \ - 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI \ - 0x00000400L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK__SI 0xffffffffL -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER_2__CC_MASK__SI 0x0000007fL -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK__SI \ - 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI \ - 0x00000400L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK__SI 0xffffffffL -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI \ - 0x00000700L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI \ - 0x00003800L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK__SI 0x00008000L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER_2__CC_MASK__SI 0x0000007fL -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__CC_MASK__SI 0x00007f00L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__COPY_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__L_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRO_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__VCFG_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__V_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK__SI \ - 0x00000010L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI \ - 0x00000400L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK__SI 0xffffffffL -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK__SI \ - 0x000000ffL -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK__SI \ - 0x000000ffL -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK__SI \ - 0x000000ffL -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK__SI \ - 0x000000ffL -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK__SI \ - 0x0000ff00L -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK__SI \ - 0x00ff0000L -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK__SI \ - 0xff000000L -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK__SI \ - 0x001f0000L -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK__SI \ - 0x00000fffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_DATA__ACP_DATA_MASK__SI 0x000000ffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__ACP_INDEX_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__SUPPORTS_AI_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK__SI 0xffffffffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK__SI 0x00ff0000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK__SI 0x00000078L -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK__SI 0x00000007L -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK__SI 0x0000ff00L -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK__SI \ - 0xff000000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK__SI 0x000000ffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN0_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK__SI 0x00000078L -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE_CHANGED_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_CAPABLE_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_DISABLE_UR_CAPABLE_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_ENABLE_UR_CAPABLE_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HBR__HBR_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HBR__HBR_ENABLE_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE_CHANGED_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_CAPABLE_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_DISABLE_UR_CAPABLE_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ENABLE_UR_CAPABLE_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_REQUIRED_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_PIN0_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK__SI 0x0000ff00L -#define AZALIA_F2_CODEC_PIN0_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK__SI 0x000000ffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK__SI \ - 0x0000000fL -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK__SI \ - 0x000000c0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK__SI \ - 0x0000fc00L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK__SI \ - 0x0000007fL -#define AZALIA_F2_CODEC_PIN0_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN0_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_DATA__VIDEO_ID_DATA_MASK__SI 0xffffffffL -#define AZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_INDEX__VIDEO_ID_INDEX_MASK__SI 0x00000003L -#define AZALIA_F2_CODEC_PIN0_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI 0x00000400L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK__SI 0x00010000L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__HDMI_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK__SI 0x0000ff00L -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK__SI \ - 0x0000000fL -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK__SI \ - 0x000000c0L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F2_CODEC_PIN1_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN1_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN1_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI 0x00000400L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK__SI 0x00010000L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__HDMI_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK__SI 0x0000ff00L -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK__SI \ - 0x0000000fL -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK__SI \ - 0x000000c0L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F2_CODEC_PIN2_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN2_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN2_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI 0x00000400L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK__SI 0x00010000L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__HDMI_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK__SI 0x0000ff00L -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK__SI 0x000000f0L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK__SI \ - 0x0000000fL -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK__SI \ - 0x000000c0L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK__SI 0x0000f000L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK__SI \ - 0x000000f0L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK__SI \ - 0x00f00000L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK__SI 0x3f000000L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK__SI 0x00000f00L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK__SI \ - 0xc0000000L -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK__SI 0x0000000fL -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK__SI 0x7fffffffL -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK__SI 0x80000000L -#define AZALIA_F2_CODEC_PIN3_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN3_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK__SI 0x0000003fL -#define AZALIA_F2_CODEC_PIN3_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK__SI \ - 0x00000008L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK__SI \ - 0x00000001L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK__SI \ - 0x000f0000L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK__SI \ - 0x00000100L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK__SI 0x00000200L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000002L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK__SI 0x00000800L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK__SI \ - 0x00000004L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK__SI 0x00000400L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK__SI \ - 0x00000040L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK__SI 0x00f00000L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK__SI \ - 0x00000080L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK__SI 0x00000040L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK__SI 0x00010000L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__HDMI_MASK__SI 0x00000080L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK__SI 0x00000008L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK__SI 0x00000001L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK__SI 0x00000020L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK__SI 0x00000004L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK__SI 0x00000010L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK__SI 0x00000002L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK__SI 0x0000ff00L -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK__SI \ - 0xffffffffL -#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK__SI \ - 0xffffffffL -#define AZALIA_HDCP_REQUIRED__HDCP_REQUIRED_BY_VIDEO_DRIVER_MASK__SI 0x00000001L -#define AZALIA_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK__SI 0x80000000L -#define AZALIA_HOT_PLUG_CONTROL__AZALIA_FORCE_CODEC_WAKE_MASK__SI 0x00000001L -#define AZALIA_HOT_PLUG_CONTROL__CODEC_HOT_PLUG_ENABLE_MASK__SI 0x00001000L -#define AZALIA_HOT_PLUG_CONTROL__FORCE_AUDIO_ENABLE_TO_HDMI_MASK__SI 0x00010000L -#define AZALIA_HOT_PLUG_CONTROL__FORCE_FIFO_ERROR_MASK__SI 0x00200000L -#define AZALIA_HOT_PLUG_CONTROL__IGNORE_CONTROLLER_CODEC_FORMAT_MISMATCH_MASK__SI 0x00100000L -#define AZALIA_HOT_PLUG_CONTROL__PIN0_AUDIO_ENABLED_MASK__SI 0x01000000L -#define AZALIA_HOT_PLUG_CONTROL__PIN0_JACK_DETECTION_ENABLE_MASK__SI 0x00000010L -#define AZALIA_HOT_PLUG_CONTROL__PIN0_UNSOLICITED_RESPONSE_ENABLE_MASK__SI 0x00000100L -#define AZALIA_HOT_PLUG_CONTROL__PIN1_AUDIO_ENABLED_MASK__SI 0x02000000L -#define AZALIA_HOT_PLUG_CONTROL__PIN1_JACK_DETECTION_ENABLE_MASK__SI 0x00000020L -#define AZALIA_HOT_PLUG_CONTROL__PIN1_UNSOLICITED_RESPONSE_ENABLE_MASK__SI 0x00000200L -#define AZALIA_HOT_PLUG_CONTROL__PIN2_AUDIO_ENABLED_MASK__SI 0x04000000L -#define AZALIA_HOT_PLUG_CONTROL__PIN2_JACK_DETECTION_ENABLE_MASK__SI 0x00000040L -#define AZALIA_HOT_PLUG_CONTROL__PIN2_UNSOLICITED_RESPONSE_ENABLE_MASK__SI 0x00000400L -#define AZALIA_HOT_PLUG_CONTROL__PIN3_AUDIO_ENABLED_MASK__SI 0x08000000L -#define AZALIA_HOT_PLUG_CONTROL__PIN3_JACK_DETECTION_ENABLE_MASK__SI 0x00000080L -#define AZALIA_HOT_PLUG_CONTROL__PIN3_UNSOLICITED_RESPONSE_ENABLE_MASK__SI 0x00000800L -#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK__SI 0x00000001L -#define AZALIA_POWER_MANAGEMENT_CONTROL__AZALIA_BUSY_CONTROL_MASK__SI 0x00000300L -#define AZALIA_POWER_MANAGEMENT_CONTROL__CODEC_WAKE_ON_POWER_TRANSITION_MASK__SI 0x00000010L -#define AZALIA_POWER_MANAGEMENT_CONTROL__D3_RESET_ENABLE_MASK__SI 0x00001000L -#define AZALIA_POWER_MANAGEMENT_CONTROL__RESET_ON_POWER_TRANSITION_MASK__SI 0x00000001L -#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK__SI 0x00000010L -#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK__SI 0x00000001L -#define AZALIA_RIRB_INTERRUPT_CONTROL__AZALIA_EMULATE_LINK_EN_MASK__SI 0x00000001L -#define AZALIA_RIRB_INTERRUPT_CONTROL__AZALIA_INTERRUPT_ON_INVALID_COMMAND_MASK__SI 0x00000100L -#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK__SI 0xffffffffL -#define AZALIA_UNSOLICITED_RESPONSE__PIN0_UNSOLICITED_RESPONSE_FORCE_MASK__SI 0x10000000L -#define AZALIA_UNSOLICITED_RESPONSE__PIN1_UNSOLICITED_RESPONSE_FORCE_MASK__SI 0x20000000L -#define AZALIA_UNSOLICITED_RESPONSE__PIN2_UNSOLICITED_RESPONSE_FORCE_MASK__SI 0x40000000L -#define AZALIA_UNSOLICITED_RESPONSE__PIN3_UNSOLICITED_RESPONSE_FORCE_MASK__SI 0x80000000L -#define AZALIA_UNSOLICITED_RESPONSE__UNSOLICITED_RESPONSE_PAYLOAD_MASK__SI 0x03ffffffL -#define AZALIA_WALL_CLOCK_LOAD__AZALIA_WALL_CLOCK_LOAD_MASK__SI 0xffffffffL -#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK__SI 0xffffffffL -#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK__CI__VI 0x0000000cL -#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK__CI__VI 0x00000002L -#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK__CI__VI 0x00000001L -#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK__CI__VI 0x00000080L -#define BACO_CNTL__BACO_BCLK_OFF_MASK__CI__VI 0x00000002L -#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK__CI__VI 0x00020000L -#define BACO_CNTL__BACO_EN_MASK__CI__VI 0x00000001L -#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK__CI__VI 0x00000020L -#define BACO_CNTL__BACO_ISO_DIS_MASK__CI__VI 0x00000004L -#define BACO_CNTL__BACO_MODE_MASK__CI__VI 0x00000040L -#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK__CI__VI 0x00010000L -#define BACO_CNTL__BACO_POWER_OFF_MASK__CI__VI 0x00000008L -#define BACO_CNTL__BACO_RESET_EN_MASK__CI__VI 0x00000010L -#define BACO_CNTL__PWRGOOD_BF_MASK__CI__VI 0x00000200L -#define BACO_CNTL__PWRGOOD_DVO_MASK__CI__VI 0x00001000L -#define BACO_CNTL__PWRGOOD_GPIO_MASK__CI__VI 0x00000400L -#define BACO_CNTL__PWRGOOD_MEM_MASK__CI__VI 0x00000800L -#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK__CI__VI 0x00000100L -#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffffL -#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffffL -#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffffL -#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffffL -#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffffL -#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffffL -#define BASE_CLASS__BASE_CLASS_MASK 0x000000ffL -#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL -#define BIF_AVP_FB_FLUSH__BIF_AVP_FB_FLUSH_DONE_MASK__SI 0x00000001L -#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK__CI__VI 0x00000001L -#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK__CI__VI 0x00000001L -#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK__CI 0x00000006L -#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK__CI 0x00000001L -#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0x000000ffL -#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L -#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000ffL -#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L -#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L -#define BIF_BUSNUM_LIST0__ID0_MASK 0x000000ffL -#define BIF_BUSNUM_LIST0__ID1_MASK 0x0000ff00L -#define BIF_BUSNUM_LIST0__ID2_MASK 0x00ff0000L -#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000L -#define BIF_BUSNUM_LIST1__ID4_MASK 0x000000ffL -#define BIF_BUSNUM_LIST1__ID5_MASK 0x0000ff00L -#define BIF_BUSNUM_LIST1__ID6_MASK 0x00ff0000L -#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000L -#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003fL -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK__CI__VI 0x00010000L -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK__CI__VI 0x00000020L -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK__CI__VI 0x0000001eL -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK__CI__VI 0x00000400L -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK__CI__VI 0x00008000L -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK__CI__VI 0x000003c0L -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK__CI__VI 0x00007800L -#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK__SI__CI 0x000003ffL -#define BIF_CLOCK_CNTL__TXCLK_PLL_SEL_MASK__SI 0x00000001L -#define BIF_CLOCK_CNTL__TXCLK_PLL_STATUS_MASK__SI 0x00000002L -#define BIF_CP_FB_FLUSH__BIF_CP_FB_FLUSH_DONE_MASK__SI 0x00000001L -#define BIF_DCT_FB_FLUSH__BIF_DCT_FB_FLUSH_DONE_MASK__SI 0x00000001L -#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x00000010L -#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x00000020L -#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x00000001L -#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x00001f00L -#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x001f0000L -#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x01000000L -#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x00000002L -#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x00000004L -#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x00000008L -#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x00000080L -#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000L -#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x00000040L -#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x0000003fL -#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x00003f00L -#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x0001ffffL -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK__CI__VI 0x000000ffL -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK__CI__VI 0x0000ff00L -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK__CI__VI 0x00ff0000L -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK__CI__VI 0xff000000L -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK__CI__VI 0x000000ffL -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK__CI__VI 0x0000ff00L -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK__CI__VI 0x00ff0000L -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK__CI__VI 0xff000000L -#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK__CI__VI 0x00000008L -#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK__CI__VI 0x00000001L -#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK__CI__VI 0x00000002L -#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK__CI__VI 0x00000004L -#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L -#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L -#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK__CI__VI 0x00000008L -#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK__CI__VI 0x00000004L -#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK__CI__VI 0x00000100L -#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK__CI__VI 0x00000001L -#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK__CI__VI 0x00000080L -#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK__CI__VI 0x00000020L -#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK__CI__VI 0x00000040L -#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK__CI__VI 0x00000002L -#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK__CI__VI 0x00000010L -#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK__CI__VI 0xffffffffL -#define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK__CI__VI 0x20000000L -#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK__CI__VI 0x00000010L -#define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK__CI__VI 0x00000080L -#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK__CI__VI 0x00001000L -#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK__CI__VI 0x00000f00L -#define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK__CI__VI 0x00000007L -#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK__CI__VI 0x00000008L -#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK__CI__VI 0x10000000L -#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK__CI__VI 0x00040000L -#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK__CI__VI 0x00f00000L -#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK__CI__VI 0x00080000L -#define BIF_IMPCTL_RXCNTL__SUSPEND_MASK__CI__VI 0x00000040L -#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK__CI__VI 0x00020000L -#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK__CI__VI 0x0001e000L -#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK__CI__VI 0x00002000L -#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK__CI__VI 0x00000001L -#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK__CI__VI 0x00004000L -#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK__CI__VI 0x03f00000L -#define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK__CI__VI 0x00000002L -#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK__CI__VI 0x00001f00L -#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK__CI__VI 0x000f8000L -#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK__CI__VI 0x00000004L -#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK__CI__VI 0x00000008L -#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK__CI__VI 0xfc000000L -#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK__CI__VI 0x00000f00L -#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK__CI__VI 0x00001000L -#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK__CI__VI 0x00000007L -#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK__CI__VI 0x00000008L -#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK__CI__VI 0x10000000L -#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK__CI__VI 0x00040000L -#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK__CI__VI 0x00080000L -#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK__CI__VI 0x00f00000L -#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK__CI__VI 0x0001e000L -#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK__CI__VI 0x00020000L -#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK__CI__VI 0x00000f00L -#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK__CI__VI 0x00001000L -#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK__CI__VI 0x00000007L -#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK__CI__VI 0x00000008L -#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK__CI__VI 0x10000000L -#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK__CI__VI 0x00040000L -#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK__CI__VI 0x00080000L -#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK__CI__VI 0x00f00000L -#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK__CI__VI 0x0001e000L -#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK__CI__VI 0x00020000L -#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK__CI 0x00000001L -#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK__CI__VI 0xffffffffL -#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK__CI__VI 0xffffffffL -#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK__CI__VI 0x00000001L -#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK__CI__VI 0x00000002L -#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK__CI__VI 0x00000004L -#define BIF_PERFMON_CNTL__PERF_SEL0_MASK__CI__VI 0x00001f00L -#define BIF_PERFMON_CNTL__PERF_SEL1_MASK__CI__VI 0x0003e000L -#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK__CI 0x00000007L -#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK__CI 0x00000038L -#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK__CI 0x000003c0L -#define BIF_PINSTRAP0__STRAP_BIF_AUDIO_EN_MASK__SI 0x00000002L -#define BIF_PINSTRAP0__STRAP_BIF_BIOS_ROM_EN_MASK__SI 0x00020000L -#define BIF_PINSTRAP0__STRAP_BIF_CLK_PM_EN_MASK__SI 0x00001000L -#define BIF_PINSTRAP0__STRAP_BIF_DBG_I2C_EN_MASK__SI 0x00000004L -#define BIF_PINSTRAP0__STRAP_BIF_ECN1P1_DIS_MASK__SI 0x00080000L -#define BIF_PINSTRAP0__STRAP_BIF_ERR_REPORTING_DIS_MASK__SI 0x00000800L -#define BIF_PINSTRAP0__STRAP_BIF_FORCE_COMPLIANCE_A_MASK__SI 0x00000100L -#define BIF_PINSTRAP0__STRAP_BIF_GEN2_EN_A_MASK__SI 0x00000008L -#define BIF_PINSTRAP0__STRAP_BIF_MEM_AP_SIZE_MASK__SI 0x0001c000L -#define BIF_PINSTRAP0__STRAP_BIF_MSI_DIS_MASK__SI 0x00000400L -#define BIF_PINSTRAP0__STRAP_BIF_REG_AP_SIZE1_MASK__SI 0x00000200L -#define BIF_PINSTRAP0__STRAP_BIF_RESERVED0_MASK__SI 0x00000040L -#define BIF_PINSTRAP0__STRAP_BIF_RESERVED1_MASK__SI 0x00000080L -#define BIF_PINSTRAP0__STRAP_BIF_RESERVED2_MASK__SI 0x00040000L -#define BIF_PINSTRAP0__STRAP_BIF_RX_PLL_CALIB_BYPASS_MASK__SI 0x00000001L -#define BIF_PINSTRAP0__STRAP_BIF_VGA_DIS_MASK__SI 0x00002000L -#define BIF_PINSTRAP0__STRAP_PHY_TX_DEEMPH_EN_MASK__SI 0x00000010L -#define BIF_PINSTRAP0__STRAP_PHY_TX_PWRS_ENB_MASK__SI 0x00000020L -#define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK__CI__VI 0x00000001L -#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK__CI 0x00000004L -#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK__CI__VI 0x00000002L -#define BIF_PWDN_STATUS__BU_REG_pw_status_MASK__CI__VI 0x00000001L -#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK__CI 0x00000004L -#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK__CI__VI 0x00000002L -#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK__CI 0x00000004L -#define BIF_RESET_CNTL__RST_DONE_MASK__CI 0x00000002L -#define BIF_RESET_CNTL__STRAP_EN_MASK__CI 0x00000001L -#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK__CI 0x00400000L -#define BIF_RESET_EN__CFG_RESET_EN_MASK__SI__CI 0x00000040L -#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK__SI__CI 0x0003f000L -#define BIF_RESET_EN__COR_RESET_EN_MASK__SI__CI 0x00000008L -#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK__SI__CI 0x000c0000L -#define BIF_RESET_EN__DRV_RESET_EN_MASK__SI__CI 0x00000080L -#define BIF_RESET_EN__FUNC0_FLR_EN_MASK__CI 0x00800000L -#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK__CI 0x0c000000L -#define BIF_RESET_EN__FUNC1_FLR_EN_MASK__CI 0x01000000L -#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK__CI 0x30000000L -#define BIF_RESET_EN__FUNC2_FLR_EN_MASK__CI 0x02000000L -#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK__CI 0xc0000000L -#define BIF_RESET_EN__HOT_RESET_EN_MASK__SI__CI 0x00000200L -#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK__SI__CI 0x00000400L -#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK__SI__CI 0x00000800L -#define BIF_RESET_EN__PHY_RESET_EN_MASK__SI__CI 0x00000004L -#define BIF_RESET_EN__PIF_RSTB_EN_MASK__CI 0x00100000L -#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK__CI 0x00200000L -#define BIF_RESET_EN__REG_RESET_EN_MASK__SI__CI 0x00000010L -#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK__SI__CI 0x00000100L -#define BIF_RESET_EN__SOFT_RST_MODE_MASK__CI 0x00000002L -#define BIF_RESET_EN__STY_RESET_EN_MASK__SI__CI 0x00000020L -#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK__CI__VI 0x00000001L -#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK__CI__VI 0x00000002L -#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK__CI__VI 0x00000001L -#define BIF_RFE_IMPRST_CNTL__REG_RST_warmRstImpEn_MASK__CI 0x00000002L -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK__CI__VI 0x00000001L -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK__CI 0x00000004L -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK__CI__VI 0x00000002L -#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK__CI__VI 0x0000000eL -#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK__CI__VI 0x00000001L -#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK__CI__VI 0x000000e0L -#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK__CI__VI 0x00000010L -#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK__CI__VI 0x01000000L -#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK__CI__VI 0x000000ffL -#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK__CI__VI 0x00000f00L -#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK__CI__VI 0x00ff0000L -#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK__CI__VI 0x01000000L -#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK__CI__VI 0x000000ffL -#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK__CI__VI 0x00000f00L -#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK__CI__VI 0x00ff0000L -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK__CI__VI \ - 0x000000ffL -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK__CI__VI \ - 0x00000f00L -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK__CI__VI \ - 0x00ff0000L -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK__CI__VI 0x01000000L -#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK__CI__VI 0x00000001L -#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK__CI__VI 0x00000002L -#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK__CI__VI 0x00000001L -#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK__CI__VI 0x0000ffffL -#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK__CI__VI 0x40000000L -#define BIF_RFE_SOFTRST_CNTL__REG_RST_warmRstRfeEn_MASK__CI 0x20000000L -#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK__CI__VI 0x80000000L -#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffffL -#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffffL -#define BIF_SLAVE_PERF_COUNTER0__BIF_SLAVE_PERF_COUNTER0_MASK__SI 0xffffffffL -#define BIF_SLAVE_PERF_COUNTER1__BIF_SLAVE_PERF_COUNTER1_MASK__SI 0xffffffffL -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT0_EVENT_SEL_MASK__SI 0x00001f00L -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT0_RESET_MASK__SI 0x00000002L -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT1_EVENT_SEL_MASK__SI 0x0003e000L -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT1_RESET_MASK__SI 0x00000004L -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT_EN_MASK__SI 0x00000001L -#define BIF_SLVARB_MODE__SLVARB_MODE_MASK__CI__VI 0x00000003L -#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK__CI 0x0003fffcL -#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK__CI 0x40000000L -#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK__CI 0x80000000L -#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK__CI 0x40000000L -#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK__CI 0x80000000L -#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK__CI 0x40000000L -#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK__CI 0x80000000L -#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK__CI 0x40000000L -#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK__CI 0x80000000L -#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK__CI 0x0003fffcL -#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK__CI 0x40000000L -#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK__CI 0x80000000L -#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK__CI 0x0003fffcL -#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK__CI 0x20000000L -#define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK__CI 0x0003fffcL -#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK__CI 0x40000000L -#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK__CI 0x80000000L -#define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK__CI 0x0003fffcL -#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK__CI 0x00000002L -#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK__CI 0x00000001L -#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK__CI 0x00000004L -#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK__CI__VI 0x1fffffffL -#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK__CI__VI 0x80000000L -#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK__CI__VI 0x1fffffffL -#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffffL -#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffffL -#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffffL -#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffffL -#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffffL -#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffffL -#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffffL -#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffffL -#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffffL -#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffffL -#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffffL -#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffffL -#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffffL -#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffffL -#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffffL -#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffffL -#define BIST__BIST_CAP_MASK 0x00000080L -#define BIST__BIST_COMP_MASK 0x0000000fL -#define BIST__BIST_STRT_MASK 0x00000040L -#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK__SI 0x00000008L -#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK__SI 0x00000004L -#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK__SI 0xffff0000L -#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK__SI 0x00000001L -#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK__SI 0x00000002L -#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK__SI 0x0001ffffL -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK__SI 0x80000000L -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK__SI \ - 0x00ff0000L -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK__SI \ - 0x00000002L -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK__SI 0x00000001L -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK__SI \ - 0x0000ff00L -#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK__SI 0x0001ffffL -#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK__SI 0x0001ffffL -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK__SI 0x00020000L -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK__SI 0x80000000L -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK__SI 0x01000000L -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK__SI 0x00000001L -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK__SI 0x00000100L -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK__SI 0x00010000L -#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK__SI 0x0001ffffL -#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK__SI 0x0001ffffL -#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK__SI 0x0001ffffL -#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK__SI 0x40000000L -#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK__SI 0x80000000L -#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK__SI 0x0000ffffL -#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK__SI 0x30000000L -#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK__SI 0x0000ffffL -#define BL_PWM_CNTL__BL_PWM_EN_MASK__SI 0x80000000L -#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK__SI 0x40000000L -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK__SI 0x00020000L -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK__SI 0x80000000L -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK__SI 0x01000000L -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK__SI 0x00000001L -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK__SI 0x00000100L -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK__SI 0x00010000L -#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK__SI 0x000f0000L -#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK__SI 0x0000ffffL -#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x00000100L -#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x00000002L -#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x00000001L -#define BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L -#define BUS_CNTL__PMI_INT_DIS_MASK 0x00000020L -#define BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L -#define BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L -#define BUS_CNTL__RD_STALL_IO_WR_MASK__CI__VI 0x00040000L -#define BUS_CNTL__SET_AZ_TC_MASK 0x00001c00L -#define BUS_CNTL__SET_MC_TC_MASK 0x0000e000L -#define BUS_CNTL__VGA_COHE_SPEC_TIMER_DIS_MASK__SI 0x00000200L -#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L -#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L -#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L -#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L -#define BWD_CHROMA_BOT_ADDR__BWD_UV_BOT_BASE_MASK__SI 0xffffffffL -#define BWD_CHROMA_TOP_ADDR__BWD_UV_TOP_BASE_MASK__SI 0xffffffffL -#define BWD_LUMA_BOT_ADDR__BWD_Y_BOT_BASE_MASK__SI 0xffffffffL -#define BWD_LUMA_TOP_ADDR__BWD_Y_TOP_BASE_MASK__SI 0xffffffffL -#define BX_RESET_EN__COR_RESET_EN_MASK__CI__VI 0x00000001L -#define BX_RESET_EN__REG_RESET_EN_MASK__CI__VI 0x00000002L -#define BX_RESET_EN__STY_RESET_EN_MASK__CI__VI 0x00000004L -#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0x000000ffL -#define CAC_ACC_ACP0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_BIF0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_CB0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_CB1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_CB2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_CB3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_CP0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_CP1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_CP2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DB0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DB1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DB2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DB3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DC0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DC1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DC2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_DC3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_IA0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_IDLE_PWR0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_LOWER_CMON__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_0__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_10__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_11__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_12__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_13__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_14__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_15__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_1__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_2__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_3__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_4__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_5__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_6__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_7__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_8__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_LOWER_REGION_9__ACCUMULATOR_31_0_MASK__SI 0xffffffffL -#define CAC_ACC_MCD0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_MCD1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_MCD2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_MCD3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_NW_ACP0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_ACP0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_BCI0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_BCI0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_BCI1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_BCI1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_BIF0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_BIF0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_CB0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_CB0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_CB1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_CB1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_CB2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_CB2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_CB3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_CB3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_CP0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_CP0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_CP1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_CP1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_CP2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_CP2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DB0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DB0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DB1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DB1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DB2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DB2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DB3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DB3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DC0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DC0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DC1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DC1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DC2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DC2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_DC3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_DC3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_GDS0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_GDS0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_GDS1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_GDS1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_GDS2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_GDS2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_GDS3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_GDS3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_IA0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_IA0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_IDLE_PWR0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_IDLE_PWR0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_LDS0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_LDS0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_LDS1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_LDS1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_LDS2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_LDS2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_LDS3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_LDS3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_MCD0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_MCD0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_MCD1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_MCD1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_MCD2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_MCD2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_MCD3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_MCD3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_PA0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_PA0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_PA1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_PA1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SC0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SC0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPI0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPI0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPI1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPI1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPI2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPI2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPI3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPI3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPI4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPI4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPI5__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPI5__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM5__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM5__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM6__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM6__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SPIM7__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SPIM7__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ5__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ5__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ6__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ6__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ7__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ7__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SQ8__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SQ8__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SX0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SX0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SX1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SX1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_SX2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_SX2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TA0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TA0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCC0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCC0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCC1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCC1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCC2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCC2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCC3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCC3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCC4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCC4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCP0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCP0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCP1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCP1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCP2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCP2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCP3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCP3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TCP4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TCP4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TD0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TD0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TD1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TD1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TD2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TD2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TD3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TD3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TD4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TD4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_TD5__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_TD5__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD5__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD5__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD6__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD6__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_UVD7__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_UVD7__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VCE0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VCE0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VCE1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VCE1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VCE2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VCE2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VCE3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VCE3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VCE4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VCE4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VGT0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VGT0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VGT1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VGT1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_VGT2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_VGT2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_WD0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_WD0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_XDMA0__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_XDMA0__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_XDMA1__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_XDMA1__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_XDMA2__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_XDMA2__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_XDMA3__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_XDMA3__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_XDMA4__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_XDMA4__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_NW_XDMA5__ACCUMULATOR_OUT_MASK__CI 0x000fffffL -#define CAC_ACC_NW_XDMA5__OVRFLOW_MASK__CI 0x80000000L -#define CAC_ACC_PA0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_PA1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SC0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM5__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM6__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SPIM7__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK__CI 0x000000ffL -#define CAC_ACC_SX0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SX1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_SX2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TA0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TD0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TD1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TD2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TD3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TD4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_TD5__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UPPER_CMON__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_0__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_10__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_11__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_12__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_13__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_14__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_15__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_1__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_2__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_3__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_4__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_5__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_6__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_7__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_8__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UPPER_REGION_9__ACCUMULATOR_40_32_MASK__SI 0x000001ffL -#define CAC_ACC_UVD0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UVD1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UVD2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UVD3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UVD4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UVD5__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UVD6__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_UVD7__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VCE0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VCE1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VCE2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VCE3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VCE4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_WD0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_XDMA0__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_XDMA1__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_XDMA2__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_XDMA3__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_XDMA4__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_ACC_XDMA5__ACCUMULATOR_31_0_MASK__CI 0xffffffffL -#define CAC_AGGR_LOWER__AGGREGATE_31_0_MASK__SI__CI 0xffffffffL -#define CAC_AGGR_UPPER__AGGREGATE_62_32_MASK__SI__CI 0x7fffffffL -#define CAC_AGGR_UPPER__AGGR_OVERFLOW_MASK__SI__CI 0x80000000L -#define CAC_OVRRD_ACP__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_ACP__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_BCI__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_BCI__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_BIF__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_BIF__OVRRD_SELECT_MASK__SI 0x00000001L -#define CAC_OVRRD_BIF__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_BIF__OVRRD_VALUE_MASK__SI 0x00000100L -#define CAC_OVRRD_CB__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_CB__OVRRD_SELECT_MASK__SI 0x0000000fL -#define CAC_OVRRD_CB__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_CB__OVRRD_VALUE_MASK__SI 0x00000f00L -#define CAC_OVRRD_CP__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_CP__OVRRD_SELECT_MASK__SI 0x00000001L -#define CAC_OVRRD_CP__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_CP__OVRRD_VALUE_MASK__SI 0x00000100L -#define CAC_OVRRD_DB__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_DB__OVRRD_SELECT_MASK__SI 0x0000000fL -#define CAC_OVRRD_DB__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_DB__OVRRD_VALUE_MASK__SI 0x00000f00L -#define CAC_OVRRD_DC__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_DC__OVRRD_SELECT_MASK__SI 0x0000000fL -#define CAC_OVRRD_DC__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_DC__OVRRD_VALUE_MASK__SI 0x00000f00L -#define CAC_OVRRD_GDS__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_GDS__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_IA__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_IA__OVRRD_SELECT_MASK__SI 0x00000001L -#define CAC_OVRRD_IA__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_IA__OVRRD_VALUE_MASK__SI 0x00000100L -#define CAC_OVRRD_IDLE_PWR__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_IDLE_PWR__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_LDS__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_LDS__OVRRD_SELECT_MASK__SI 0x00000003L -#define CAC_OVRRD_LDS__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_LDS__OVRRD_VALUE_MASK__SI 0x00000300L -#define CAC_OVRRD_MCD__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_MCD__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_MC__OVRRD_SELECT_MASK__SI 0x00000003L -#define CAC_OVRRD_MC__OVRRD_VALUE_MASK__SI 0x00000300L -#define CAC_OVRRD_PA__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_PA__OVRRD_SELECT_MASK__SI 0x00000003L -#define CAC_OVRRD_PA__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_PA__OVRRD_VALUE_MASK__SI 0x00000300L -#define CAC_OVRRD_SC__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_SC__OVRRD_SELECT_MASK__SI 0x00000003L -#define CAC_OVRRD_SC__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_SC__OVRRD_VALUE_MASK__SI 0x00000300L -#define CAC_OVRRD_SPIM__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_SPIM__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_SPI__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_SPI__OVRRD_SELECT_MASK__SI 0x0000003fL -#define CAC_OVRRD_SPI__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_SPI__OVRRD_VALUE_MASK__SI 0x00003f00L -#define CAC_OVRRD_SQ__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_SQ__OVRRD_SELECT_MASK__SI 0x00000007L -#define CAC_OVRRD_SQ__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_SQ__OVRRD_VALUE_MASK__SI 0x00000700L -#define CAC_OVRRD_SX__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_SX__OVRRD_SELECT_MASK__SI 0x00000007L -#define CAC_OVRRD_SX__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_SX__OVRRD_VALUE_MASK__SI 0x00000700L -#define CAC_OVRRD_TA__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_TA__OVRRD_SELECT_MASK__SI 0x00000001L -#define CAC_OVRRD_TA__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_TA__OVRRD_VALUE_MASK__SI 0x00000100L -#define CAC_OVRRD_TCC__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_TCC__OVRRD_SELECT_MASK__SI 0x0000001fL -#define CAC_OVRRD_TCC__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_TCC__OVRRD_VALUE_MASK__SI 0x00001f00L -#define CAC_OVRRD_TCP__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_TCP__OVRRD_SELECT_MASK__SI 0x00000003L -#define CAC_OVRRD_TCP__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_TCP__OVRRD_VALUE_MASK__SI 0x00000300L -#define CAC_OVRRD_TD__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_TD__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_UVD__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_UVD__OVRRD_SELECT_MASK__SI 0x000000ffL -#define CAC_OVRRD_UVD__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_UVD__OVRRD_VALUE_MASK__SI 0x0000ff00L -#define CAC_OVRRD_VCE__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_VCE__OVRRD_SELECT_MASK__SI 0x0000001fL -#define CAC_OVRRD_VCE__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_VCE__OVRRD_VALUE_MASK__SI 0x00001f00L -#define CAC_OVRRD_VGT__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_VGT__OVRRD_SELECT_MASK__SI 0x00000007L -#define CAC_OVRRD_VGT__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_VGT__OVRRD_VALUE_MASK__SI 0x00000700L -#define CAC_OVRRD_WD__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_WD__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_OVRRD_XDMA__OVRRD_SELECT_MASK__CI 0x0000ffffL -#define CAC_OVRRD_XDMA__OVRRD_VALUE_MASK__CI 0xffff0000L -#define CAC_PCIE_LNCNT_0_ACC_SUM__LNCNT_acc_sum_MASK__CI 0xffffffffL -#define CAC_PCIE_LNCNT_0_TIME_STAMP__LNCNT_RdVld_MASK__CI 0x80000000L -#define CAC_PCIE_LNCNT_0_TIME_STAMP__LNCNT_time_stamp_MASK__CI 0x0000ffffL -#define CAC_PCIE_LNCNT_1_ACC_SUM__LNCNT_acc_sum_MASK__CI 0xffffffffL -#define CAC_PCIE_LNCNT_1_TIME_STAMP__LNCNT_RdVld_MASK__CI 0x80000000L -#define CAC_PCIE_LNCNT_1_TIME_STAMP__LNCNT_time_stamp_MASK__CI 0x0000ffffL -#define CAC_PCIE_LNCNT_2_ACC_SUM__LNCNT_acc_sum_MASK__CI 0xffffffffL -#define CAC_PCIE_LNCNT_2_TIME_STAMP__LNCNT_RdVld_MASK__CI 0x80000000L -#define CAC_PCIE_LNCNT_2_TIME_STAMP__LNCNT_time_stamp_MASK__CI 0x0000ffffL -#define CAC_PCIE_LNCNT_3_ACC_SUM__LNCNT_acc_sum_MASK__CI 0xffffffffL -#define CAC_PCIE_LNCNT_3_TIME_STAMP__LNCNT_RdVld_MASK__CI 0x80000000L -#define CAC_PCIE_LNCNT_3_TIME_STAMP__LNCNT_time_stamp_MASK__CI 0x0000ffffL -#define CAC_PCIE_LNCNT_CNTL__LNCNT_read_req_MASK__CI 0x80000000L -#define CAC_SMC_IND_DATA__SMC_IND_DATA_MASK__CI 0xffffffffL -#define CAC_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI 0xffffffffL -#define CAC_THERMAL_STATUS__ASIC_MAX_TEMP_MASK__SI__CI 0x000001ffL -#define CAC_THRESHOLD_LOWER__OCP_THRESHOLD_MASK__SI__CI 0xffffffffL -#define CAC_THRESHOLD_UPPER__OCP_THRESHOLD_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_ACP_0__WEIGHT_ACP_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK__CI 0xffff0000L -#define CAC_WEIGHT_BIF_0__WEIGHT_BIF_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK__CI 0xffff0000L -#define CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_CP_1__WEIGHT_PA_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_DC_0__WEIGHT_DC_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_DC_0__WEIGHT_DC_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_DC_1__WEIGHT_DC_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_DC_1__WEIGHT_DC_SIG3_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK__CI 0xffff0000L -#define CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_IDLE_PWR_0__WEIGHT_IDLE_PWR_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_MCD_0__WEIGHT_MCD_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_MCD_0__WEIGHT_MCD_SIG1_MASK__CI 0xffff0000L -#define CAC_WEIGHT_MCD_1__WEIGHT_MCD_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_MCD_1__WEIGHT_MCD_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_MC_0__WEIGHT_MC_SIG0_MASK__SI 0x0000ffffL -#define CAC_WEIGHT_MC_0__WEIGHT_MC_SIG1_MASK__SI 0xffff0000L -#define CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1_MASK__SI 0xffff0000L -#define CAC_WEIGHT_SPIM_0__WEIGHT_SPIM_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_SPIM_0__WEIGHT_SPIM_SIG1_MASK__CI 0xffff0000L -#define CAC_WEIGHT_SPIM_1__WEIGHT_SPIM_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_SPIM_1__WEIGHT_SPIM_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_SPIM_2__WEIGHT_SPIM_SIG4_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_SPIM_2__WEIGHT_SPIM_SIG5_MASK__CI 0xffff0000L -#define CAC_WEIGHT_SPIM_3__WEIGHT_SPIM_SIG6_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_SPIM_3__WEIGHT_SPIM_SIG7_MASK__CI 0xffff0000L -#define CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK__CI 0xffff0000L -#define CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK__CI 0xffff0000L -#define CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_SX_0__WEIGHT_SX_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_SX_1__WEIGHT_SX_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK__CI 0xffff0000L -#define CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK__CI 0xffff0000L -#define CAC_WEIGHT_UVD_0__WEIGHT_UVD_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_UVD_0__WEIGHT_UVD_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_UVD_1__WEIGHT_UVD_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_UVD_1__WEIGHT_UVD_SIG3_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_UVD_2__WEIGHT_UVD_SIG4_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_UVD_2__WEIGHT_UVD_SIG5_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_UVD_3__WEIGHT_UVD_SIG6_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_UVD_3__WEIGHT_UVD_SIG7_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_VCE_0__WEIGHT_VCE_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_VCE_0__WEIGHT_VCE_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_VCE_1__WEIGHT_VCE_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_VCE_1__WEIGHT_VCE_SIG3_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_VCE_2__WEIGHT_VCE_SIG4_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK__SI__CI 0xffff0000L -#define CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK__SI__CI 0x0000ffffL -#define CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_XDMA_0__WEIGHT_XDMA_SIG0_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_XDMA_0__WEIGHT_XDMA_SIG1_MASK__CI 0xffff0000L -#define CAC_WEIGHT_XDMA_1__WEIGHT_XDMA_SIG2_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_XDMA_1__WEIGHT_XDMA_SIG3_MASK__CI 0xffff0000L -#define CAC_WEIGHT_XDMA_2__WEIGHT_XDMA_SIG4_MASK__CI 0x0000ffffL -#define CAC_WEIGHT_XDMA_2__WEIGHT_XDMA_SIG5_MASK__CI 0xffff0000L -#define CAP0_ANC0_OFFSET_HIGH__CAP_ANC0_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_ANC0_OFFSET__CAP_ANC0_OFFSET_MASK__SI 0xffffffffL -#define CAP0_ANC1_OFFSET_HIGH__CAP_ANC1_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_ANC1_OFFSET__CAP_ANC1_OFFSET_MASK__SI 0xffffffffL -#define CAP0_ANC2_OFFSET_HIGH__CAP_ANC2_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_ANC2_OFFSET__CAP_ANC2_OFFSET_MASK__SI 0xffffffffL -#define CAP0_ANC3_OFFSET_HIGH__CAP_ANC3_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_ANC3_OFFSET__CAP_ANC3_OFFSET_MASK__SI 0xffffffffL -#define CAP0_ANC_BUF01_BLOCK_CNT__CAP0_ANC_BUF0_BLOCK_CNT_MASK__SI 0x00000fffL -#define CAP0_ANC_BUF01_BLOCK_CNT__CAP0_ANC_BUF1_BLOCK_CNT_MASK__SI 0x0fff0000L -#define CAP0_ANC_BUF23_BLOCK_CNT__CAP0_ANC_BUF2_BLOCK_CNT_MASK__SI 0x00000fffL -#define CAP0_ANC_BUF23_BLOCK_CNT__CAP0_ANC_BUF3_BLOCK_CNT_MASK__SI 0x0fff0000L -#define CAP0_ANC_H_WINDOW__CAP_ANC_WIDTH_MASK__SI 0x00000fffL -#define CAP0_BUF0_EVEN_OFFSET_HIGH__CAP_BUF0_EVEN_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_BUF0_EVEN_OFFSET__CAP_BUF0_EVEN_OFFSET_MASK__SI 0xffffffffL -#define CAP0_BUF0_OFFSET_HIGH__CAP_BUF0_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_BUF0_OFFSET__CAP_BUF0_OFFSET_MASK__SI 0xffffffffL -#define CAP0_BUF1_EVEN_OFFSET_HIGH__CAP_BUF1_EVEN_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_BUF1_EVEN_OFFSET__CAP_BUF1_EVEN_OFFSET_MASK__SI 0xffffffffL -#define CAP0_BUF1_OFFSET_HIGH__CAP_BUF1_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_BUF1_OFFSET__CAP_BUF1_OFFSET_MASK__SI 0xffffffffL -#define CAP0_BUF_PITCH__CAP_BUF_PITCH_MASK__SI 0x00000fffL -#define CAP0_BUF_STATUS__CAP_ANC_BUF_STATUS_MASK__SI 0x00008000L -#define CAP0_BUF_STATUS__CAP_ANC_PRE_BUF_CNT_MASK__SI 0x0fff0000L -#define CAP0_BUF_STATUS__CAP_CAP_BUF_STATUS_MASK__SI 0x40000000L -#define CAP0_BUF_STATUS__CAP_CUR_ANC_BUF_MASK__SI 0x00006000L -#define CAP0_BUF_STATUS__CAP_CUR_FIELD_MASK__SI 0x00000020L -#define CAP0_BUF_STATUS__CAP_CUR_VBI_BUF_MASK__SI 0x00000300L -#define CAP0_BUF_STATUS__CAP_CUR_VID_BUF_MASK__SI 0x0000000cL -#define CAP0_BUF_STATUS__CAP_PRE_ANC_BUF_MASK__SI 0x00001800L -#define CAP0_BUF_STATUS__CAP_PRE_FIELD_MASK__SI 0x00000010L -#define CAP0_BUF_STATUS__CAP_PRE_VBI_BUF_MASK__SI 0x000000c0L -#define CAP0_BUF_STATUS__CAP_PRE_VID_BUF_MASK__SI 0x00000003L -#define CAP0_BUF_STATUS__CAP_VBI_BUF_STATUS_MASK__SI 0x00000400L -#define CAP0_BUF_STATUS__CAP_VIP_INC_MASK__SI 0x10000000L -#define CAP0_BUF_STATUS__CAP_VIP_PRE_REPEAT_FIELD_MASK__SI 0x20000000L -#define CAP0_BUF_STATUS__CAP_VIP_STATUS_STROBE_MASK__SI 0x80000000L -#define CAP0_CONFIG__CAP_ANC_DECODE_EN_MASK__SI 0x00001000L -#define CAP0_CONFIG__CAP_BUF_MODE_MASK__SI 0x00000180L -#define CAP0_CONFIG__CAP_BUF_TYPE_MASK__SI 0x00000030L -#define CAP0_CONFIG__CAP_FAKE_FIELD_EN_MASK__SI 0x00010000L -#define CAP0_CONFIG__CAP_FIELD_START_LINE_DIFF_MASK__SI 0x00060000L -#define CAP0_CONFIG__CAP_HDWNS_DEC_MASK__SI 0x04000000L -#define CAP0_CONFIG__CAP_HORZ_DOWN_MASK__SI 0x00180000L -#define CAP0_CONFIG__CAP_IMAGE_FLIP_EN_MASK__SI 0x08000000L -#define CAP0_CONFIG__CAP_INPUT_MODE_MASK__SI 0x00000001L -#define CAP0_CONFIG__CAP_MIRROR_EN_MASK__SI 0x00000200L -#define CAP0_CONFIG__CAP_ONESHOT_IMAGE_FLIP_EN_MASK__SI 0x10000000L -#define CAP0_CONFIG__CAP_ONESHOT_MIRROR_EN_MASK__SI 0x00000400L -#define CAP0_CONFIG__CAP_ONESHOT_MODE_MASK__SI 0x00000040L -#define CAP0_CONFIG__CAP_SOFT_PULL_DOWN_EN_MASK__SI 0x00004000L -#define CAP0_CONFIG__CAP_START_BUF_R_MASK__SI 0x00000004L -#define CAP0_CONFIG__CAP_START_BUF_W_MASK__SI 0x00000008L -#define CAP0_CONFIG__CAP_START_FIELD_MASK__SI 0x00000002L -#define CAP0_CONFIG__CAP_STREAM_FORMAT_MASK__SI 0x03800000L -#define CAP0_CONFIG__CAP_VBI_EN_MASK__SI 0x00002000L -#define CAP0_CONFIG__CAP_VERT_DOWN_MASK__SI 0x00600000L -#define CAP0_CONFIG__CAP_VIDEO_IN_FORMAT_MASK__SI 0x20000000L -#define CAP0_CONFIG__CAP_VIDEO_SIGNED_UV_MASK__SI 0x00000800L -#define CAP0_CONFIG__CAP_VIP_EXTEND_FLAG_EN_MASK__SI 0x00008000L -#define CAP0_CONFIG__VBI_HORZ_DOWN_MASK__SI 0xc0000000L -#define CAP0_DEBUG__CAP_H_STATUS_MASK__SI 0x00000fffL -#define CAP0_DEBUG__CAP_V_STATUS_MASK__SI 0x0fff0000L -#define CAP0_DEBUG__CAP_V_SYNC_MASK__SI 0x10000000L -#define CAP0_H_WINDOW__CAP_H_START_MASK__SI 0x00000fffL -#define CAP0_H_WINDOW__CAP_H_WIDTH_MASK__SI 0x0fff0000L -#define CAP0_ONESHOT_BUF_OFFSET_HIGH__CAP_ONESHOT_BUF_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_ONESHOT_BUF_OFFSET__CAP_ONESHOT_BUF_OFFSET_MASK__SI 0xffffffffL -#define CAP0_PORT_MODE_CNTL__CAP_DDR_MODE_MASK__SI 0x00000008L -#define CAP0_PORT_MODE_CNTL__CAP_DDR_SYNC_MASK__SI 0x00000010L -#define CAP0_PORT_MODE_CNTL__CAP_PORT_BYTE_USED_MASK__SI 0x00000004L -#define CAP0_PORT_MODE_CNTL__CAP_PORT_WIDTH_MASK__SI 0x00000002L -#define CAP0_PORT_MODE_CNTL__MOBILE_DIS_MASK__SI 0x00000020L -#define CAP0_TRIG_CNTL__CAP_EN_MASK__SI 0x00000010L -#define CAP0_TRIG_CNTL__CAP_TRIGGER_R_MASK__SI 0x00000003L -#define CAP0_TRIG_CNTL__CAP_TRIGGER_W_MASK__SI 0x00000001L -#define CAP0_TRIG_CNTL__CAP_VSYNC_CLR_MASK__SI 0x00010000L -#define CAP0_TRIG_CNTL__CAP_VSYNC_CNT_MASK__SI 0x0000ff00L -#define CAP0_VBI0_OFFSET_HIGH__CAP_VBI0_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_VBI0_OFFSET__CAP_VBI0_OFFSET_MASK__SI 0xffffffffL -#define CAP0_VBI1_OFFSET_HIGH__CAP_VBI1_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_VBI1_OFFSET__CAP_VBI1_OFFSET_MASK__SI 0xffffffffL -#define CAP0_VBI2_OFFSET_HIGH__CAP_VBI2_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_VBI2_OFFSET__CAP_VBI2_OFFSET_MASK__SI 0xffffffffL -#define CAP0_VBI3_OFFSET_HIGH__CAP_VBI3_OFFSET_HIGH_MASK__SI 0x000000ffL -#define CAP0_VBI3_OFFSET__CAP_VBI3_OFFSET_MASK__SI 0xffffffffL -#define CAP0_VBI_H_WINDOW__CAP_VBI_H_START_MASK__SI 0x00000fffL -#define CAP0_VBI_H_WINDOW__CAP_VBI_H_WIDTH_MASK__SI 0x0fff0000L -#define CAP0_VBI_V_WINDOW__CAP_VBI_V_END_MASK__SI 0x0fff0000L -#define CAP0_VBI_V_WINDOW__CAP_VBI_V_START_MASK__SI 0x00000fffL -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_SYNC_EN_MASK__SI 0x00000020L -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_EOF_MASK__SI 0x00000002L -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_EOL_MASK__SI 0x00000004L -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_FIELD_MASK__SI 0x00000008L -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_SOF_MASK__SI 0x00000001L -#define CAP0_V_WINDOW__CAP_V_END_MASK__SI 0x0fff0000L -#define CAP0_V_WINDOW__CAP_V_START_MASK__SI 0x00000fffL -#define CAP0_WR_BUFFER_STAT__WR_ACK_REQ_AK_MASK__SI 0x00000800L -#define CAP0_WR_BUFFER_STAT__WR_ACK_REQ_MASK__SI 0x00000800L -#define CAP0_WR_BUFFER_STAT__WR_BUFFER_FULLNESS_MASK__SI 0x000003ffL -#define CAP0_WR_BUFFER_STAT__WR_BUFFER_FULL_AK_MASK__SI 0x00000400L -#define CAP0_WR_BUFFER_STAT__WR_BUFFER_FULL_MASK__SI 0x00000400L -#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L -#define CAPTURE_START_STATUS__DACA_CAPTURE_START_AK_MASK__SI 0x00000040L -#define CAPTURE_START_STATUS__DACA_CAPTURE_START_INT_EN_MASK__SI 0x00001000L -#define CAPTURE_START_STATUS__DACA_CAPTURE_START_MASK__SI 0x00000001L -#define CAPTURE_START_STATUS__DACB_CAPTURE_START_AK_MASK__SI 0x00000080L -#define CAPTURE_START_STATUS__DACB_CAPTURE_START_INT_EN_MASK__SI 0x00002000L -#define CAPTURE_START_STATUS__DACB_CAPTURE_START_MASK__SI 0x00000002L -#define CAPTURE_START_STATUS__DIGA_CAPTURE_START_AK_MASK__SI 0x00000100L -#define CAPTURE_START_STATUS__DIGA_CAPTURE_START_INT_EN_MASK__SI 0x00004000L -#define CAPTURE_START_STATUS__DIGA_CAPTURE_START_MASK__SI 0x00000004L -#define CAPTURE_START_STATUS__DIGB_CAPTURE_START_AK_MASK__SI 0x00000200L -#define CAPTURE_START_STATUS__DIGB_CAPTURE_START_INT_EN_MASK__SI 0x00008000L -#define CAPTURE_START_STATUS__DIGB_CAPTURE_START_MASK__SI 0x00000008L -#define CAPTURE_START_STATUS__DVOA_CAPTURE_START_AK_MASK__SI 0x00000400L -#define CAPTURE_START_STATUS__DVOA_CAPTURE_START_INT_EN_MASK__SI 0x00010000L -#define CAPTURE_START_STATUS__DVOA_CAPTURE_START_MASK__SI 0x00000010L -#define CAP_DEBUG__CAP_EOF_AK_MASK__SI 0x00004000L -#define CAP_DEBUG__CAP_EOF_EN_MASK__SI 0x00000004L -#define CAP_DEBUG__CAP_EOF_MH_ACK_REQ_AK_MASK__SI 0x00008000L -#define CAP_DEBUG__CAP_EOF_MH_ACK_REQ_EN_MASK__SI 0x00000008L -#define CAP_DEBUG__CAP_EOF_MH_ACK_REQ_STATUS_MASK__SI 0x00000800L -#define CAP_DEBUG__CAP_EOF_STATUS_MASK__SI 0x00000400L -#define CAP_DEBUG__CAP_EOL_AK_MASK__SI 0x00001000L -#define CAP_DEBUG__CAP_EOL_EN_MASK__SI 0x00000001L -#define CAP_DEBUG__CAP_EOL_STATUS_MASK__SI 0x00000100L -#define CAP_DEBUG__CAP_SOF_AK_MASK__SI 0x00002000L -#define CAP_DEBUG__CAP_SOF_EN_MASK__SI 0x00000002L -#define CAP_DEBUG__CAP_SOF_STATUS_MASK__SI 0x00000200L -#define CAP_INT_CNTL__CAP0_ANC0_INT_EN_MASK__SI 0x00000080L -#define CAP_INT_CNTL__CAP0_ANC1_INT_EN_MASK__SI 0x00000100L -#define CAP_INT_CNTL__CAP0_ANC2_INT_EN_MASK__SI 0x00000800L -#define CAP_INT_CNTL__CAP0_ANC3_INT_EN_MASK__SI 0x00001000L -#define CAP_INT_CNTL__CAP0_BUF0_EVEN_INT_EN_MASK__SI 0x00000002L -#define CAP_INT_CNTL__CAP0_BUF0_INT_EN_MASK__SI 0x00000001L -#define CAP_INT_CNTL__CAP0_BUF1_EVEN_INT_EN_MASK__SI 0x00000008L -#define CAP_INT_CNTL__CAP0_BUF1_INT_EN_MASK__SI 0x00000004L -#define CAP_INT_CNTL__CAP0_BUF_INT_MUX_MASK__SI 0x00002000L -#define CAP_INT_CNTL__CAP0_ONESHOT_INT_EN_MASK__SI 0x00000040L -#define CAP_INT_CNTL__CAP0_VBI0_INT_EN_MASK__SI 0x00000010L -#define CAP_INT_CNTL__CAP0_VBI1_INT_EN_MASK__SI 0x00000020L -#define CAP_INT_CNTL__CAP0_VBI2_INT_EN_MASK__SI 0x00000200L -#define CAP_INT_CNTL__CAP0_VBI3_INT_EN_MASK__SI 0x00000400L -#define CAP_INT_STATUS__CAP0_ANC0_INT_AK_MASK__SI 0x00000080L -#define CAP_INT_STATUS__CAP0_ANC0_INT_MASK__SI 0x00000080L -#define CAP_INT_STATUS__CAP0_ANC1_INT_AK_MASK__SI 0x00000100L -#define CAP_INT_STATUS__CAP0_ANC1_INT_MASK__SI 0x00000100L -#define CAP_INT_STATUS__CAP0_ANC2_INT_AK_MASK__SI 0x00000800L -#define CAP_INT_STATUS__CAP0_ANC2_INT_MASK__SI 0x00000800L -#define CAP_INT_STATUS__CAP0_ANC3_INT_AK_MASK__SI 0x00001000L -#define CAP_INT_STATUS__CAP0_ANC3_INT_MASK__SI 0x00001000L -#define CAP_INT_STATUS__CAP0_BUF0_EVEN_INT_AK_MASK__SI 0x00000002L -#define CAP_INT_STATUS__CAP0_BUF0_EVEN_INT_MASK__SI 0x00000002L -#define CAP_INT_STATUS__CAP0_BUF0_INT_AK_MASK__SI 0x00000001L -#define CAP_INT_STATUS__CAP0_BUF0_INT_MASK__SI 0x00000001L -#define CAP_INT_STATUS__CAP0_BUF1_EVEN_INT_AK_MASK__SI 0x00000008L -#define CAP_INT_STATUS__CAP0_BUF1_EVEN_INT_MASK__SI 0x00000008L -#define CAP_INT_STATUS__CAP0_BUF1_INT_AK_MASK__SI 0x00000004L -#define CAP_INT_STATUS__CAP0_BUF1_INT_MASK__SI 0x00000004L -#define CAP_INT_STATUS__CAP0_ONESHOT_INT_AK_MASK__SI 0x00000040L -#define CAP_INT_STATUS__CAP0_ONESHOT_INT_MASK__SI 0x00000040L -#define CAP_INT_STATUS__CAP0_VBI0_INT_AK_MASK__SI 0x00000010L -#define CAP_INT_STATUS__CAP0_VBI0_INT_MASK__SI 0x00000010L -#define CAP_INT_STATUS__CAP0_VBI1_INT_AK_MASK__SI 0x00000020L -#define CAP_INT_STATUS__CAP0_VBI1_INT_MASK__SI 0x00000020L -#define CAP_INT_STATUS__CAP0_VBI2_INT_AK_MASK__SI 0x00000200L -#define CAP_INT_STATUS__CAP0_VBI2_INT_MASK__SI 0x00000200L -#define CAP_INT_STATUS__CAP0_VBI3_INT_AK_MASK__SI 0x00000400L -#define CAP_INT_STATUS__CAP0_VBI3_INT_MASK__SI 0x00000400L -#define CAP_PTR__CAP_PTR_MASK 0x000000ffL -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L -#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL -#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL -#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL -#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L -#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL -#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL -#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL -#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL -#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L -#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK__CI__VI 0x04000000L -#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L -#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK__CI__VI 0x7ff00000L -#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007ffL -#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003fffffL -#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L -#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L -#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L -#define CB_DEBUG_BUS_13__AC_BUSY_MASK__SI__CI 0x00000008L -#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK__SI__CI 0x00000020L -#define CB_DEBUG_BUS_13__CRW_BUSY_MASK__SI__CI 0x00000010L -#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK__SI__CI 0x00000200L -#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK__SI__CI 0x00000100L -#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK__SI__CI 0x00000080L -#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK__SI__CI 0x00000400L -#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK__SI__CI 0x00000040L -#define CB_DEBUG_BUS_13__MU_BUSY_MASK__SI__CI 0x00000002L -#define CB_DEBUG_BUS_13__MU_STATE_MASK__SI__CI 0x0007f800L -#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK__SI__CI 0x00000001L -#define CB_DEBUG_BUS_13__TQ_BUSY_MASK__SI__CI 0x00000004L -#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK__SI__CI 0x00000010L -#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK__SI__CI 0x00000008L -#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK__SI__CI 0x00000100L -#define CB_DEBUG_BUS_14__FOP_BUSY_MASK__SI__CI 0x00000002L -#define CB_DEBUG_BUS_14__LAT_BUSY_MASK__SI__CI 0x00000004L -#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK__SI__CI 0x00000020L -#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK__SI__CI 0x00000040L -#define CB_DEBUG_BUS_14__TILE_BUSY_MASK__SI__CI 0x00000080L -#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK__SI__CI 0x00000001L -#define CB_DEBUG_BUS_15__CS_BUSY_MASK__SI__CI 0x00000010L -#define CB_DEBUG_BUS_15__DS_BUSY_MASK__SI__CI 0x00000040L -#define CB_DEBUG_BUS_15__IB_BUSY_MASK__SI__CI 0x00000100L -#define CB_DEBUG_BUS_15__RB_BUSY_MASK__SI__CI 0x00000020L -#define CB_DEBUG_BUS_15__SF_BUSY_MASK__SI__CI 0x00000008L -#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK__SI__CI 0x00000004L -#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK__SI__CI 0x00000003L -#define CB_DEBUG_BUS_15__TB_BUSY_MASK__SI__CI 0x00000080L -#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK__SI__CI 0x00100000L -#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK__SI__CI 0x00400000L -#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK__SI__CI 0x00200000L -#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK__SI__CI 0x000003c0L -#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK__SI__CI 0x000f0000L -#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK__SI__CI 0x0000003fL -#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK__SI__CI 0x0000fc00L -#define CB_DEBUG_BUS_17__BB_BUSY_MASK__SI__CI 0x00000008L -#define CB_DEBUG_BUS_17__CC_BUSY_MASK__SI__CI 0x00000004L -#define CB_DEBUG_BUS_17__CM_BUSY_MASK__SI__CI 0x00000001L -#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK__SI__CI 0x00000020L -#define CB_DEBUG_BUS_17__FC_BUSY_MASK__SI__CI 0x00000002L -#define CB_DEBUG_BUS_17__MA_BUSY_MASK__SI__CI 0x00000010L -#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK__SI__CI 0x00000080L -#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK__SI__CI 0x00000040L -#define CB_DEBUG_BUS_18__NOT_USED_MASK__SI__CI 0x00ffffffL -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L -#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000L -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL -#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK__CI 0xff000000L -#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK__SI 0xff800000L -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK__CI__VI 0x00000001L -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK__CI__VI 0x00200000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK__CI__VI 0x00040000L -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L -#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define CB_PERFCOUNTER0_SELECT0__FORMAT_FILTER_ENABLE_MASK__SI 0x00001000L -#define CB_PERFCOUNTER0_SELECT0__FORMAT_FILTER_SEL_MASK__SI 0x0003e000L -#define CB_PERFCOUNTER0_SELECT0__OP_FILTER_ENABLE_MASK__SI 0x00000100L -#define CB_PERFCOUNTER0_SELECT0__OP_FILTER_SEL_MASK__SI 0x00000e00L -#define CB_PERFCOUNTER0_SELECT0__PERF_SEL_MASK__SI 0x000000ffL -#define CB_PERFCOUNTER0_SELECT1__CLEAR_FILTER_ENABLE_MASK__SI 0x00000001L -#define CB_PERFCOUNTER0_SELECT1__CLEAR_FILTER_SEL_MASK__SI 0x00000002L -#define CB_PERFCOUNTER0_SELECT1__MRT_FILTER_ENABLE_MASK__SI 0x00000004L -#define CB_PERFCOUNTER0_SELECT1__MRT_FILTER_SEL_MASK__SI 0x00000078L -#define CB_PERFCOUNTER0_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE_MASK__SI 0x00000800L -#define CB_PERFCOUNTER0_SELECT1__NUM_FRAGMENTS_FILTER_SEL_MASK__SI 0x00003000L -#define CB_PERFCOUNTER0_SELECT1__NUM_SAMPLES_FILTER_ENABLE_MASK__SI 0x00000080L -#define CB_PERFCOUNTER0_SELECT1__NUM_SAMPLES_FILTER_SEL_MASK__SI 0x00000700L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000001ffL -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x0007fc00L -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x0007fc00L -#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000001ffL -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define CB_PERFCOUNTER1_SELECT0__FORMAT_FILTER_ENABLE_MASK__SI 0x00001000L -#define CB_PERFCOUNTER1_SELECT0__FORMAT_FILTER_SEL_MASK__SI 0x0003e000L -#define CB_PERFCOUNTER1_SELECT0__OP_FILTER_ENABLE_MASK__SI 0x00000100L -#define CB_PERFCOUNTER1_SELECT0__OP_FILTER_SEL_MASK__SI 0x00000e00L -#define CB_PERFCOUNTER1_SELECT0__PERF_SEL_MASK__SI 0x000000ffL -#define CB_PERFCOUNTER1_SELECT1__CLEAR_FILTER_ENABLE_MASK__SI 0x00000001L -#define CB_PERFCOUNTER1_SELECT1__CLEAR_FILTER_SEL_MASK__SI 0x00000002L -#define CB_PERFCOUNTER1_SELECT1__MRT_FILTER_ENABLE_MASK__SI 0x00000004L -#define CB_PERFCOUNTER1_SELECT1__MRT_FILTER_SEL_MASK__SI 0x00000078L -#define CB_PERFCOUNTER1_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE_MASK__SI 0x00000800L -#define CB_PERFCOUNTER1_SELECT1__NUM_FRAGMENTS_FILTER_SEL_MASK__SI 0x00003000L -#define CB_PERFCOUNTER1_SELECT1__NUM_SAMPLES_FILTER_ENABLE_MASK__SI 0x00000080L -#define CB_PERFCOUNTER1_SELECT1__NUM_SAMPLES_FILTER_SEL_MASK__SI 0x00000700L -#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000001ffL -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define CB_PERFCOUNTER2_SELECT0__FORMAT_FILTER_ENABLE_MASK__SI 0x00001000L -#define CB_PERFCOUNTER2_SELECT0__FORMAT_FILTER_SEL_MASK__SI 0x0003e000L -#define CB_PERFCOUNTER2_SELECT0__OP_FILTER_ENABLE_MASK__SI 0x00000100L -#define CB_PERFCOUNTER2_SELECT0__OP_FILTER_SEL_MASK__SI 0x00000e00L -#define CB_PERFCOUNTER2_SELECT0__PERF_SEL_MASK__SI 0x000000ffL -#define CB_PERFCOUNTER2_SELECT1__CLEAR_FILTER_ENABLE_MASK__SI 0x00000001L -#define CB_PERFCOUNTER2_SELECT1__CLEAR_FILTER_SEL_MASK__SI 0x00000002L -#define CB_PERFCOUNTER2_SELECT1__MRT_FILTER_ENABLE_MASK__SI 0x00000004L -#define CB_PERFCOUNTER2_SELECT1__MRT_FILTER_SEL_MASK__SI 0x00000078L -#define CB_PERFCOUNTER2_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE_MASK__SI 0x00000800L -#define CB_PERFCOUNTER2_SELECT1__NUM_FRAGMENTS_FILTER_SEL_MASK__SI 0x00003000L -#define CB_PERFCOUNTER2_SELECT1__NUM_SAMPLES_FILTER_ENABLE_MASK__SI 0x00000080L -#define CB_PERFCOUNTER2_SELECT1__NUM_SAMPLES_FILTER_SEL_MASK__SI 0x00000700L -#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000001ffL -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define CB_PERFCOUNTER3_SELECT0__FORMAT_FILTER_ENABLE_MASK__SI 0x00001000L -#define CB_PERFCOUNTER3_SELECT0__FORMAT_FILTER_SEL_MASK__SI 0x0003e000L -#define CB_PERFCOUNTER3_SELECT0__OP_FILTER_ENABLE_MASK__SI 0x00000100L -#define CB_PERFCOUNTER3_SELECT0__OP_FILTER_SEL_MASK__SI 0x00000e00L -#define CB_PERFCOUNTER3_SELECT0__PERF_SEL_MASK__SI 0x000000ffL -#define CB_PERFCOUNTER3_SELECT1__CLEAR_FILTER_ENABLE_MASK__SI 0x00000001L -#define CB_PERFCOUNTER3_SELECT1__CLEAR_FILTER_SEL_MASK__SI 0x00000002L -#define CB_PERFCOUNTER3_SELECT1__MRT_FILTER_ENABLE_MASK__SI 0x00000004L -#define CB_PERFCOUNTER3_SELECT1__MRT_FILTER_SEL_MASK__SI 0x00000078L -#define CB_PERFCOUNTER3_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE_MASK__SI 0x00000800L -#define CB_PERFCOUNTER3_SELECT1__NUM_FRAGMENTS_FILTER_SEL_MASK__SI 0x00003000L -#define CB_PERFCOUNTER3_SELECT1__NUM_SAMPLES_FILTER_ENABLE_MASK__SI 0x00000080L -#define CB_PERFCOUNTER3_SELECT1__NUM_SAMPLES_FILTER_SEL_MASK__SI 0x00000700L -#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000001ffL -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK__CI__VI 0x00000400L -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK__CI__VI 0x00000800L -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK__CI__VI 0x00000010L -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK__CI__VI 0x000003e0L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK__CI__VI 0x00001000L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK__CI__VI 0x0000e000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK__CI__VI 0x00200000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK__CI__VI 0x00c00000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK__CI__VI 0x00020000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK__CI__VI 0x001c0000L -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK__CI__VI 0x00000001L -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK__CI__VI 0x0000000eL -#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL -#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L -#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L -#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L -#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L -#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L -#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L -#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L -#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL -#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L -#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L -#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L -#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L -#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L -#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L -#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L -#define CCIPHER_A_IK0__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_IK1__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_IK2__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_IK3__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S0__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S10__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S11__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S12__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S13__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S14__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S15__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S16__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S17__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S18__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S19__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S1__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S20__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S21__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S22__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S23__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S24__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S25__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S26__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S27__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S28__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S29__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S2__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S30__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S31__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S3__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S4__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S5__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S6__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S7__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S8__RESERVED_MASK 0xffffffffL -#define CCIPHER_A_S9__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_IK0__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_IK1__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_IK2__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_IK3__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S0__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S10__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S11__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S12__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S13__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S14__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S15__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S16__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S17__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S18__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S19__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S1__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S20__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S21__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S22__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S23__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S24__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S25__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S26__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S27__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S28__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S29__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S2__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S30__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S31__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S3__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S4__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S5__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S6__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S7__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S8__RESERVED_MASK 0xffffffffL -#define CCIPHER_B_S9__RESERVED_MASK 0xffffffffL -#define CC_BIF_AZALIA_ID__AZALIA_DID_MASK__SI 0x00000078L -#define CC_BIF_AZALIA_ID__STRAP_AZALIA_DID_MASK__CI 0x0001fffeL -#define CC_BIF_AZALIA_ID__STRAP_BIF_AZ_64BAR_EN_A_MASK__SI 0x00001000L -#define CC_BIF_AZALIA_ID__STRAP_BIF_AZ_NONLEGACY_DEVICE_TYPE_EN_MASK__SI 0x00002000L -#define CC_BIF_AZALIA_ID__STRAP_BIF_F0_64BAR_EN_A_MASK__SI 0x00000400L -#define CC_BIF_AZALIA_ID__STRAP_BIF_F0_NONLEGACY_DEVICE_TYPE_EN_MASK__SI 0x00000800L -#define CC_BIF_AZALIA_ID__STRAP_BIF_IO_BAR_DIS_MASK__SI 0x00000200L -#define CC_BIF_AZALIA_ID__STRAP_BIF_LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK__SI 0x00000080L -#define CC_BIF_AZALIA_ID__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A_MASK__SI 0x00010000L -#define CC_BIF_AZALIA_ID__STRAP_BIF_RXP_NAK_FIX_IN_MODE1_EN_MASK__SI 0x00004000L -#define CC_BIF_AZALIA_ID__STRAP_BIF_RXP_REALIGN_ON_EACH_TSX_OR_SKP_MASK__SI 0x00008000L -#define CC_BIF_AZALIA_ID__STRAP_BIF_SHUTOFF_PORTS_FOR_SYM_ERR_MASK__SI 0x00000100L -#define CC_BIF_AZALIA_ID__WRITE_DIS_MASK__SI 0x00000001L -#define CC_BIF_AZALIA_ID__WR_DIS_MASK__CI 0x00000001L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_AUDIO_EN_PIN_MASK__CI 0x00010000L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_BIOS_ROM_EN_MASK__CI 0x00000008L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_CEC_EN_PIN_MASK__CI 0x00020000L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_CLK_PM_EN_MASK__CI__VI 0x00000004L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_GEN3_EN_A_MASK__CI 0x00000002L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_MEM_AP_SIZE_PIN_MASK__CI 0x000000e0L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_SMBUS_DIS_MASK__CI 0x00000010L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN_MASK__CI 0x00000200L -#define CC_BIF_BU_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING_MASK__CI 0x00000800L -#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK__CI__VI 0x00000002L -#define CC_BIF_BX_FUSESTRAP0__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_AUDIO_EN_PIN_MASK__CI 0x00010000L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_BIOS_ROM_EN_MASK__CI 0x00000008L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_CEC_EN_PIN_MASK__CI 0x00020000L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_CLK_PM_EN_MASK__CI__VI 0x00000004L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_GEN3_EN_A_MASK__CI__VI 0x00000002L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_MEM_AP_SIZE_PIN_MASK__CI 0x000000e0L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_SMBUS_DIS_MASK__CI 0x00000010L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN_MASK__CI 0x00000200L -#define CC_BIF_BX_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING_MASK__CI 0x00000800L -#define CC_BIF_BX_STRAP0__STRAP_BIF_BAR_COMPLIANCE_EN_MASK__CI__VI 0x00002000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_DEBUG_ACCESS_MASK__CI__VI 0x00000800L -#define CC_BIF_BX_STRAP0__STRAP_BIF_DOORBELL_APER_SIZE_MASK__CI__VI 0x0000c000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_DOORBELL_BAR_DIS_MASK__CI__VI 0x00001000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_FB_ALWAYS_ON_MASK__CI__VI 0x00000100L -#define CC_BIF_BX_STRAP0__STRAP_BIF_FB_CPL_TYPE_SEL_MASK__CI__VI 0x00000600L -#define CC_BIF_BX_STRAP0__STRAP_BIF_MEM_AP_SIZE_MASK__CI__VI 0x00000038L -#define CC_BIF_BX_STRAP0__STRAP_BIF_REG_AP_SIZE_MASK__CI__VI 0x00000006L -#define CC_BIF_BX_STRAP0__STRAP_BIF_ROM_AP_SIZE_MASK__CI__VI 0x000000c0L -#define CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK__CI 0x07ff0000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_AUDIO_EN_MASK__CI 0x00002000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_AZ_64BAR_DIS_A_MASK__CI 0x00000020L -#define CC_BIF_BX_STRAP1__STRAP_BIF_AZ_LEGACY_DEVICE_TYPE_DIS_MASK__CI 0x00000400L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_64BAR_DIS_A_MASK__CI 0x00000008L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_BAR_EN_MASK__CI 0x00000040L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_DIS_MASK__CI 0x00000100L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_DIS_MASK__CI 0x00000200L -#define CC_BIF_BX_STRAP1__STRAP_BIF_IO_BAR_DIS_MASK__CI 0x00000002L -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_EP_ERR_MASK__CI 0x00000800L -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK__CI 0x00000080L -#define CC_BIF_BX_STRAP1__STRAP_BIF_VGA_DIS_MASK__CI 0x00000004L -#define CC_BIF_BX_STRAP1__STRAP_CEC_64BAR_DIS_MASK__CI 0x00000010L -#define CC_BIF_BX_STRAP1__STRAP_CEC_PME_SUPPORT_COMPLIANCE_DIS_MASK__CI 0x00001000L -#define CC_BIF_BX_STRAP1__STRAP_RESERVED_MASK__CI 0x003fc000L -#define CC_BIF_EFUSE0__STRAP_BIF_ASPM_L0SL1_INACTIVITY_EN_MASK__SI 0x00010000L -#define CC_BIF_EFUSE0__STRAP_BIF_IMP_MANUAL_OVERRIDE_MASK__SI 0x00000002L -#define CC_BIF_EFUSE0__STRAP_BIF_PAD_RX_MANUAL_IMPEDANCE_MASK__SI 0x0000003cL -#define CC_BIF_EFUSE0__STRAP_BIF_PAD_TX_MANUAL_IMPEDANCE_MASK__SI 0x000003c0L -#define CC_BIF_EFUSE0__STRAP_PHY_G2PLL_CREN_MODE_MASK__SI 0x00001000L -#define CC_BIF_EFUSE0__STRAP_PHY_G2PLL_IDLEDET_TH_MASK__SI 0x00006000L -#define CC_BIF_EFUSE0__STRAP_PHY_GEN1_RX_CRFRSIZE_MASK__SI 0xc0000000L -#define CC_BIF_EFUSE0__STRAP_PHY_GEN1_RX_CRFR_ON_MASK__SI 0x20000000L -#define CC_BIF_EFUSE0__STRAP_PHY_GEN2_RX_CRFRSIZE_MASK__SI 0x18000000L -#define CC_BIF_EFUSE0__STRAP_PHY_GEN2_RX_CRFR_ON_MASK__SI 0x00020000L -#define CC_BIF_EFUSE0__STRAP_PHY_GEN2_RX_CRPHSIZE_MASK__SI 0x000c0000L -#define CC_BIF_EFUSE0__STRAP_PHY_RX_CLKG_EN_MASK__SI 0x00000400L -#define CC_BIF_EFUSE0__STRAP_PHY_RX_INCAL_FORCE_MASK__SI 0x00000800L -#define CC_BIF_EFUSE0__STRAP_PHY_TX_CLKG_EN_MASK__SI 0x00100000L -#define CC_BIF_EFUSE0__STRAP_PHY_TX_DEEMPH_STR_MASK__SI 0x07800000L -#define CC_BIF_EFUSE0__STRAP_PHY_TX_DRV_STR_MASK__SI 0x00600000L -#define CC_BIF_EFUSE0__STRAP_PHY_TX_TAPINV_MASK__SI 0x00008000L -#define CC_BIF_EFUSE0__WRITE_DIS_MASK__SI 0x00000001L -#define CC_BIF_EFUSE1__STRAP_BIF_AER_EN_MASK__SI 0x00000080L -#define CC_BIF_EFUSE1__STRAP_BIF_ECN1P1_DIS_MASK__SI 0x02000000L -#define CC_BIF_EFUSE1__STRAP_BIF_ELAST_WATERMARK_MASK__SI 0x00060000L -#define CC_BIF_EFUSE1__STRAP_BIF_ERR_REPORTING_DIS_MASK__SI 0x00001000L -#define CC_BIF_EFUSE1__STRAP_BIF_EXIT_LATENCY_A_MASK__SI 0x00000f00L -#define CC_BIF_EFUSE1__STRAP_BIF_MSTCPL_TIMEOUT_EN_MASK__SI 0x00010000L -#define CC_BIF_EFUSE1__STRAP_BIF_PHY_RCVRDET_3NF_MASK__SI 0x00400000L -#define CC_BIF_EFUSE1__STRAP_BIF_PWRSAVE_PEIDL_GOOD_MASK__SI 0x00000010L -#define CC_BIF_EFUSE1__STRAP_BIF_RX_IGNORE_ALL_ERR_MASK__SI 0x00000002L -#define CC_BIF_EFUSE1__STRAP_BIF_SKIP_INTERVAL_A_MASK__SI 0x0000e000L -#define CC_BIF_EFUSE1__STRAP_BIF_STAGGER_CNTL_MASK__SI 0x00300000L -#define CC_BIF_EFUSE1__STRAP_BIF_SYMALIGN_DIS_ELIDLE_MASK__SI 0x00080000L -#define CC_BIF_EFUSE1__STRAP_BIF_SYMALIGN_MODE_MASK__SI 0x00000020L -#define CC_BIF_EFUSE1__STRAP_BIF_TX_PDNB_MODE_MASK__SI 0x00000040L -#define CC_BIF_EFUSE1__STRAP_INC_PLLCAL_PHASE_MASK__SI 0x3c000000L -#define CC_BIF_EFUSE1__STRAP_PHY_GEN1_PG2RX_EQ_MASK__SI 0x01800000L -#define CC_BIF_EFUSE1__STRAP_PHY_GEN1_RX_CRPHSIZE_MASK__SI 0x0000000cL -#define CC_BIF_EFUSE1__STRAP_PHY_GEN2_PG2RX_EQ_MASK__SI 0xc0000000L -#define CC_BIF_EFUSE1__WRITE_DIS_MASK__SI 0x00000001L -#define CC_BIF_EFUSE2__STRAP_BIF_2VC_EN_MASK__SI 0x01000000L -#define CC_BIF_EFUSE2__STRAP_BIF_BACKGROUND_IMP_CAL_MASK__SI 0x00100000L -#define CC_BIF_EFUSE2__STRAP_BIF_BYPASS_LDSK_TO_LC_MASK__SI 0x04000000L -#define CC_BIF_EFUSE2__STRAP_BIF_DEEMPH_BIF_SEL_A_MASK__SI 0x10000000L -#define CC_BIF_EFUSE2__STRAP_BIF_FB_ALWAYS_ON_MASK__SI 0x00200000L -#define CC_BIF_EFUSE2__STRAP_BIF_FB_CPL_TYPE_SEL_MASK__SI 0x00c00000L -#define CC_BIF_EFUSE2__STRAP_BIF_GEN2_COMPLIANCE_MASK__SI 0x00001000L -#define CC_BIF_EFUSE2__STRAP_BIF_LC_CHECK_DATA_RATE_MASK__SI 0x00004000L -#define CC_BIF_EFUSE2__STRAP_BIF_LC_ELEC_IDLE_MODE_A_MASK__SI 0x00018000L -#define CC_BIF_EFUSE2__STRAP_BIF_LC_SELECT_DEEMPHASIS_MASK__SI 0x08000000L -#define CC_BIF_EFUSE2__STRAP_BIF_LC_UPCONFIGURE_DIS_MASK__SI 0x00020000L -#define CC_BIF_EFUSE2__STRAP_BIF_LC_UPCONFIGURE_SUPPORT_MASK__SI 0x00040000L -#define CC_BIF_EFUSE2__STRAP_BIF_LDSK_X1_BYPASS_MASK__SI 0x00080000L -#define CC_BIF_EFUSE2__STRAP_BIF_RXP_LAT_REDUCTION_DIS_MASK__SI 0x00002000L -#define CC_BIF_EFUSE2__STRAP_BIF_TARGET_LINK_SPEED_A_MASK__SI 0x02000000L -#define CC_BIF_EFUSE2__STRAP_BIF_VENDOR_ID_MASK__SI 0x20000000L -#define CC_BIF_EFUSE2__STRAP_PHY_CLK_TX_DRV_STR_MASK__SI 0xc0000000L -#define CC_BIF_EFUSE2__STRAP_PHY_PLL_IBIAS_MASK__SI 0x00000fe0L -#define CC_BIF_EFUSE2__STRAP_PHY_TX_DEEMPH_STR74_MASK__SI 0x0000001eL -#define CC_BIF_EFUSE2__WRITE_DIS_MASK__SI 0x00000001L -#define CC_BIF_ID_STRAPS__DEVICE_ID_MASK__SI 0x000ffff0L -#define CC_BIF_ID_STRAPS__MAJOR_REV_ID_MASK__SI 0x00f00000L -#define CC_BIF_ID_STRAPS__MINOR_REV_ID_MASK__SI 0x0f000000L -#define CC_BIF_ID_STRAPS__STRAP_BIF_F0_DEVICE_ID_MASK__CI 0x000ffff0L -#define CC_BIF_ID_STRAPS__STRAP_BIF_F0_MAJOR_REV_ID_MASK__CI 0x00f00000L -#define CC_BIF_ID_STRAPS__STRAP_BIF_F0_MINOR_REV_ID_MASK__CI 0x0f000000L -#define CC_BIF_ID_STRAPS__STRAP_RESERVED_1_MASK__CI 0x0000000eL -#define CC_BIF_ID_STRAPS__STRAP_RESERVED_MASK__CI 0xf0000000L -#define CC_BIF_ID_STRAPS__WRITE_DIS_MASK__SI 0x00000001L -#define CC_BIF_ID_STRAPS__WR_DIS_MASK__CI 0x00000001L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_ASPM_L0SL1_INACTIVITY_EN_MASK__SI 0x00000002L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_BYPASS_SCRAMBLER_MASK__SI 0x00000001L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_ELAST_WATERMARK_MASK__SI 0x0000000cL -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_IMP_MANUAL_OVERRIDE_MASK__SI 0x00000040L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_PAD_RX_MANUAL_IMPEDANCE_MASK__SI 0x00000780L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_PAD_TX_MANUAL_IMPEDANCE_MASK__SI 0x00007800L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_STAGGER_CNTL_MASK__SI 0x00060000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_SYMALIGN_DIS_ELIDLE_MASK__SI 0x00008000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_TEST_TOGGLE_MODE_MASK__SI 0x00000010L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_TEST_TOGGLE_PATTERN_MASK__SI 0x00000020L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_TX_PDNB_MODE_MASK__SI 0x02000000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_INC_PLLCAL_PHASE_MASK__SI 0x00780000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_GEN1_RX_CRFRSIZE_MASK__SI 0x18000000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_GEN1_RX_CRFR_ON_MASK__SI 0x00010000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_GEN1_RX_CRPHSIZE_MASK__SI 0x60000000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_CLKG_EN_MASK__SI 0x04000000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_INCAL_FORCE_MASK__SI 0x80000000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_LBACK_EN_MASK__SI 0x00800000L -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_TOGGLE_EN_MASK__SI 0x01000000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_AER_EN_MASK__SI 0x80000000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_BACKGROUND_IMP_CAL_MASK__SI 0x00008000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_PHY_RCVRDET_3NF_MASK__SI 0x00004000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_PWRSAVE_PEIDL_GOOD_MASK__SI 0x00010000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_QUICKSIM_START_MASK__SI 0x00000800L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_SKIP_INTERVAL_A_MASK__SI 0x00e00000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_SYMALIGN_MODE_MASK__SI 0x00020000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_G2PLL_CREN_MODE_MASK__SI 0x00000001L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_G2PLL_IDLEDET_TH_MASK__SI 0x00000006L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_GEN1_PG2RX_EQ_MASK__SI 0x60000000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_PLL_IBIAS_MASK__SI 0x000003f8L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_RX_TEST_EN_INVERT_MASK__SI 0x00000400L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_TX_CLKG_EN_MASK__SI 0x01000000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_TX_DEEMPH_STR_MASK__SI 0x1e000000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_TX_DRV_STR_MASK__SI 0x00003000L -#define CC_BIF_ROMSTRAP1__ROMSTRAP_YTSX_COUNT_MASK__SI 0x001c0000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_AUDIO_EN_MASK__SI 0x04000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_BYPASS_RCVR_DET_A_MASK__SI 0x80000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_CFG_REG_RESET_ONLY_MASK__SI 0x20000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_COMPLIANCE_DIS_A_MASK__SI 0x01000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_DUALFUNC_DISPLAY_EN_MASK__SI 0x02000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_ECN1P1_EN_MASK__SI 0x00000040L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_EXIT_LATENCY_A_MASK__SI 0x0000000fL -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_F0_64BAR_EN_A_MASK__SI 0x00000020L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_F0_NONLEGACY_DEVICE_TYPE_EN_MASK__SI 0x00000010L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_F0_VC_EN_MASK__SI 0x10000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_LINK_DOWN_RESET_EN_MASK__SI 0x40000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_MEM_AP_SIZE_MASK__SI 0x00000380L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_MSI_DIS_MASK__SI 0x08000000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_REG_AP_SIZE1_MASK__SI 0x00000400L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_ROM_AP_SIZE_MASK__SI 0x00001800L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_BE_ERR_MASK__SI 0x00004000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_CFG_ERR_MASK__SI 0x00008000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_CFG_UR_MASK__SI 0x00010000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_CPL_ERR_MASK__SI 0x00020000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_EP_ERR_MASK__SI 0x00040000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_IO_ERR_MASK__SI 0x00080000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_IO_UR_MASK__SI 0x00100000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK__SI 0x00002000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK__SI 0x00200000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_MSG_ERR_MASK__SI 0x00400000L -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_TC_ERR_MASK__SI 0x00800000L -#define CC_BIF_ROMSTRAP3__ROMSTRAP_BIF_SUBSYS_ID_MASK__SI 0xffff0000L -#define CC_BIF_ROMSTRAP3__ROMSTRAP_BIF_SUBSYS_VEN_ID_MASK__SI 0x0000ffffL -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK__SI 0x80000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_AZ_64BAR_EN_A_MASK__SI 0x00800000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_AZ_NONLEGACY_DEVICE_TYPE_EN_MASK__SI 0x00400000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_FORCE_CDR_MODE_MASK__SI 0x00002000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_FORCE_GEN2_MODE_MASK__SI 0x00001000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_GEN2_COMPLIANCE_MASK__SI 0x10000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_CDR_SET_TYPE_MASK__SI 0x0000c000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_CDR_TEST_OFF_MASK__SI 0x00030000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_CHECK_DATA_RATE_MASK__SI 0x40000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK__SI 0x00100000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A_MASK__SI 0x04000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_RXP_LAT_REDUCTION_DIS_MASK__SI 0x20000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_RXP_NAK_FIX_IN_MODE1_EN_MASK__SI 0x01000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_RXP_REALIGN_ON_EACH_TSX_OR_SKP_MASK__SI 0x02000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_SHUTOFF_PORTS_FOR_SYM_ERR_MASK__SI 0x00200000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_VGA_DIS_MASK__SI 0x08000000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_CLK_TX_DRV_STR_MASK__SI 0x000c0000L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_PG2RX_EQ_MASK__SI 0x00000c00L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_RX_CRFRSIZE_MASK__SI 0x000000c0L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_RX_CRFR_ON_MASK__SI 0x00000020L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_RX_CRPHSIZE_MASK__SI 0x00000300L -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_TX_DEEMPH_STR74_MASK__SI 0x0000000fL -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_TX_TAPINV_MASK__SI 0x00000010L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_2VC_EN_MASK__SI 0x00200000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_BYPASS_LDSK_TO_LC_MASK__SI 0x00800000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_DEBUG_ACCESS_MASK__SI 0x00400000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_DEEMPH_BIF_SEL_A_MASK__SI 0x02000000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_FB_ALWAYS_ON_MASK__SI 0x00040000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_FB_CPL_TYPE_SEL_MASK__SI 0x00180000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_FORCE_COMPLIANCE_A_MASK__SI 0x40000000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_IO_BAR_DIS_MASK__SI 0x20000000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LANE_NEGOTIATION_MASK__SI 0x00000070L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_ELEC_IDLE_MODE_A_MASK__SI 0x00000003L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_INIT_SPEED_NEG_IN_L0s_EN_A_MASK__SI 0x00000004L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_INIT_SPEED_NEG_IN_L1_EN_A_MASK__SI 0x00000008L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_SELECT_DEEMPHASIS_MASK__SI 0x01000000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_TEST_TIMER_SEL_A_MASK__SI 0x00000180L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_UPCONFIGURE_DIS_MASK__SI 0x00000200L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_UPCONFIGURE_SUPPORT_MASK__SI 0x00000400L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LDSK_X1_BYPASS_MASK__SI 0x00000800L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_MSTCPL_TIMEOUT_EN_MASK__SI 0x00001000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_PARALLEL_LBACK_EN_MASK__SI 0x80000000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_P_SYMSYNC_BYPASS_MODE_MASK__SI 0x00004000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_P_SYMSYNC_ENABLE_IN_GEN1_MASK__SI 0x00008000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_RST_PDNB_REG_ON_CALRST_MASK__SI 0x10000000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_TARGET_LINK_SPEED_A_MASK__SI 0x00002000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_TX_TEST_ALL_MASK__SI 0x00030000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_VENDOR_ID_MASK__SI 0x04000000L -#define CC_BIF_ROMSTRAP5__ROMSTRAP_PHY_CALIB_RST_MASK__SI 0x08000000L -#define CC_BIF_SECURE_CNTL__SECURE_ID_MASK__CI__VI 0xffff0000L -#define CC_BIF_SECURE_CNTL__SECURE_LVL_MASK__CI__VI 0x00000300L -#define CC_BIF_SECURE_CNTL__WR_DIS_MASK__CI__VI 0x00000001L -#define CC_BIF_STRAP0__STRAP_BIF_2VC_EN_MASK__CI 0x00001000L -#define CC_BIF_STRAP0__STRAP_BIF_ASPM_L0SL1_INACTIVITY_EN_MASK__CI 0x00000002L -#define CC_BIF_STRAP0__STRAP_BIF_ECN1P1_DIS_MASK__CI 0x40000000L -#define CC_BIF_STRAP0__STRAP_BIF_F0_CPL_ABORT_ERR_EN_MASK__CI 0x80000000L -#define CC_BIF_STRAP0__STRAP_BIF_FORCE_COMPLIANCE_A_MASK__CI 0x20000000L -#define CC_BIF_STRAP0__STRAP_BIF_GEN2_COMPLIANCE_DIS_MASK__CI 0x00004000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_BYPASS_EQ_A_MASK__CI 0x00000040L -#define CC_BIF_STRAP0__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_A_MASK__CI 0x00000020L -#define CC_BIF_STRAP0__STRAP_BIF_LC_CHECK_DATA_RATE_DIS_MASK__CI 0x10000000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_ELEC_IDLE_MODE_A_MASK__CI 0x00000018L -#define CC_BIF_STRAP0__STRAP_BIF_LC_EQ_SEARCH_MODE_A_MASK__CI 0x00000180L -#define CC_BIF_STRAP0__STRAP_BIF_LC_SELECT_DEEMPHASIS_MASK__CI 0x02000000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A_MASK__CI 0x00000004L -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_NONDIS_MASK__CI 0x08000000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_SUPPORT_MASK__CI 0x04000000L -#define CC_BIF_STRAP0__STRAP_BIF_MSTCPL_TIMEOUT_EN_MASK__CI 0x00002000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_BE_ERR_MASK__CI 0x00020000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK__CI 0x00040000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CFG_UR_MASK__CI 0x00800000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK__CI 0x00080000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_IO_ERR_MASK__CI 0x00010000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_IO_UR_MASK__CI 0x01000000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK__CI 0x00100000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK__CI 0x00200000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_TC_ERR_MASK__CI 0x00400000L -#define CC_BIF_STRAP0__STRAP_BIF_RX_PLL_CALIB_BYPASS_MASK__CI 0x00008000L -#define CC_BIF_STRAP0__STRAP_BIF_SKIP_INTERVAL_A_MASK__CI 0x00000e00L -#define CC_BIF_STRAP1__STRAP_BIF_ECRC_CHECK_EN_MASK__CI 0x02000000L -#define CC_BIF_STRAP1__STRAP_BIF_ECRC_GEN_EN_MASK__CI__VI 0x00200000L -#define CC_BIF_STRAP1__STRAP_BIF_F0_MAX_PAYLOAD_SUPPORT_DIS_MASK__CI 0x08000000L -#define CC_BIF_STRAP1__STRAP_BIF_F0_PWR_EN_MASK__CI__VI 0x00040000L -#define CC_BIF_STRAP1__STRAP_BIF_F0_SUBSYS_ID_MASK__CI__VI 0x0001fffeL -#define CC_BIF_STRAP1__STRAP_BIF_F1_CPL_ABORT_ERR_EN_MASK__CI__VI 0x00020000L -#define CC_BIF_STRAP1__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK__CI__VI 0x00080000L -#define CC_BIF_STRAP1__STRAP_BIF_LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK__CI__VI 0x00400000L -#define CC_BIF_STRAP1__STRAP_BIF_MSI_DIS_MASK__CI 0x04000000L -#define CC_BIF_STRAP1__STRAP_BIF_SYMALIGN_HW_DEBUG_MASK__CI__VI 0x00100000L -#define CC_BIF_STRAP1__STRAP_BIF_SYMALIGN_MODE_MASK__CI 0x01000000L -#define CC_BIF_STRAP1__STRAP_BIF_VENDOR_ID_MASK__CI 0x00800000L -#define CC_BIF_STRAP1__STRAP_B_PCB_DIS0_MASK__CI 0x10000000L -#define CC_BIF_STRAP1__STRAP_B_PCB_DIS1_MASK__CI 0x20000000L -#define CC_BIF_STRAP1__STRAP_B_PCB_DRV_STR_MASK__CI 0xc0000000L -#define CC_BIF_STRAP2__STRAP_BIF_AER_EN_MASK__CI 0x00001000L -#define CC_BIF_STRAP2__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK__CI 0x04000000L -#define CC_BIF_STRAP2__STRAP_BIF_BYPASS_RCVR_DET_A_MASK__CI 0x00000800L -#define CC_BIF_STRAP2__STRAP_BIF_BYPASS_SCRAMBLER_MASK__CI 0x00010000L -#define CC_BIF_STRAP2__STRAP_BIF_CFG_REG_RESET_ONLY_MASK__CI 0x10000000L -#define CC_BIF_STRAP2__STRAP_BIF_COMPLIANCE_DIS_A_MASK__CI 0x00000400L -#define CC_BIF_STRAP2__STRAP_BIF_ERR_REPORTING_DIS_MASK__CI 0x08000000L -#define CC_BIF_STRAP2__STRAP_BIF_EXTENDED_TAG_ECN_EN_MASK__CI 0x80000000L -#define CC_BIF_STRAP2__STRAP_BIF_F0_POISONED_ADVISORY_NONFATAL_DIS_MASK__CI 0x00000002L -#define CC_BIF_STRAP2__STRAP_BIF_F0_VC_EN_MASK__CI 0x00002000L -#define CC_BIF_STRAP2__STRAP_BIF_F1_POISONED_ADVISORY_NONFATAL_DIS_MASK__CI 0x00000004L -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_CDR_MODE_MASK__CI 0x00100000L -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_GEN2_MODE_MASK__CI 0x00080000L -#define CC_BIF_STRAP2__STRAP_BIF_LANE_NEGOTIATION_A_MASK__CI 0x00000380L -#define CC_BIF_STRAP2__STRAP_BIF_LC_CDR_SET_TYPE_MASK__CI 0x00060000L -#define CC_BIF_STRAP2__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L0s_EN_A_MASK__CI 0x00000010L -#define CC_BIF_STRAP2__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L1_EN_A_MASK__CI 0x00000008L -#define CC_BIF_STRAP2__STRAP_BIF_LC_TEST_TIMER_SEL_A_MASK__CI 0x00000060L -#define CC_BIF_STRAP2__STRAP_BIF_LINK_DOWN_RESET_EN_MASK__CI 0x20000000L -#define CC_BIF_STRAP2__STRAP_BIF_PARALLEL_LBACK_EN_MASK__CI 0x01000000L -#define CC_BIF_STRAP2__STRAP_BIF_QUICKSIM_START_MASK__CI 0x40000000L -#define CC_BIF_STRAP2__STRAP_BIF_RST_PDNB_REG_ON_CALRST_MASK__CI 0x00800000L -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_MODE_MASK__CI 0x00004000L -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_PATTERN_MASK__CI 0x00008000L -#define CC_BIF_STRAP2__STRAP_BIF_TX_TEST_ALL_MASK__CI 0x00600000L -#define CC_BIF_STRAP2__STRAP_PHY_CALIB_RST_MASK__CI 0x02000000L -#define CC_BIF_STRAP3__STRAP_BIF_FLR_EN_MASK__CI 0x20000000L -#define CC_BIF_STRAP3__STRAP_BIF_FORCE_GEN3_MODE_MASK__CI 0x00800000L -#define CC_BIF_STRAP3__STRAP_BIF_GEN3_COMPLIANCE_DIS_MASK__CI 0x40000000L -#define CC_BIF_STRAP3__STRAP_BIF_INTERNAL_ERR_EN_MASK__CI 0x10000000L -#define CC_BIF_STRAP3__STRAP_BIF_LC_CDR_TEST_OFF_MASK__CI 0x00300000L -#define CC_BIF_STRAP3__STRAP_BIF_NO_SOFT_RESET_MASK__CI 0x00400000L -#define CC_BIF_STRAP3__STRAP_BIF_SUBSYS_VEN_ID_MASK__CI 0x0001fffeL -#define CC_BIF_STRAP3__STRAP_PIF_OPO_TRIGGER_MUX_SEL_MASK__CI 0x80000000L -#define CC_BIF_STRAP3__STRAP_PIF_RXDETECT_OVERRIDE_EN_MASK__CI 0x01000000L -#define CC_BIF_STRAP3__STRAP_PIF_SERIAL_CFG_ENABLE_MASK__CI 0x02000000L -#define CC_BIF_STRAP3__STRAP_PLL_CMP_FREQ_MODE_MASK__CI 0x0c000000L -#define CC_BIF_STRAP3__STRAP_YTSX_COUNT_MASK__CI 0x000e0000L -#define CC_BIF_STRAP4__STRAP_BIF_GEN2_EN_A_MASK__CI 0x10000000L -#define CC_BIF_STRAP4__STRAP_BIF_LC_AUTO_DISABLE_GEN2_EN_A_MASK__CI 0x02000000L -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_0_MASK__CI 0x000001feL -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_1_MASK__CI 0x0001fe00L -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_2_MASK__CI 0x01fe0000L -#define CC_BIF_STRAP4__STRAP_BIF_TARGET_LINK_SPEED_A_MASK__CI 0x0c000000L -#define CC_BIF_STRAP5__STRAP_BIF_F0_PAGE_REQ_EN_MASK__CI__VI 0x04000000L -#define CC_BIF_STRAP5__STRAP_BIF_F0_PASID_EN_MASK__CI__VI 0x08000000L -#define CC_BIF_STRAP5__STRAP_BIF_GASKET_SLV_COMB_DIS_MASK__CI 0x80000000L -#define CC_BIF_STRAP5__STRAP_BIF_PASID_EXE_PERMISSION_SUPPORTED_MASK__CI__VI 0x10000000L -#define CC_BIF_STRAP5__STRAP_BIF_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK__CI__VI 0x40000000L -#define CC_BIF_STRAP5__STRAP_BIF_PASID_PRIV_MODE_SUPPORTED_MASK__CI__VI 0x20000000L -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_3_MASK__CI 0x000001feL -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_4_MASK__CI 0x0001fe00L -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_5_MASK__CI 0x01fe0000L -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_SYSTEM_ALLOCATED_MASK__CI__VI 0x02000000L -#define CC_BIF_STRAP6__STRAP_BIF_F0_DPA_EN_MASK__CI 0x00000100L -#define CC_BIF_STRAP6__STRAP_BIF_F2_CPL_ABORT_ERR_EN_MASK__CI 0x00000002L -#define CC_BIF_STRAP6__STRAP_BIF_F2_POISONED_ADVISORY_NONFATAL_DIS_MASK__CI 0x00000004L -#define CC_BIF_STRAP6__STRAP_BIF_L0S_ACCEPTABLE_LATENCY_MASK__CI 0xe0000000L -#define CC_BIF_STRAP6__STRAP_BIF_L0S_EXIT_LATENCY_MASK__CI 0x03800000L -#define CC_BIF_STRAP6__STRAP_BIF_L1_EXIT_LATENCY_MASK__CI 0x1c000000L -#define CC_BIF_STRAP6__STRAP_BIF_LC_EQ_FS_A_MASK__CI 0x003f0000L -#define CC_BIF_STRAP6__STRAP_BIF_LC_EQ_LF_A_MASK__CI 0x0000fc00L -#define CC_BIF_STRAP6__STRAP_BIF_LC_X12_NEGOTIATION_DIS_A_MASK__CI 0x00400000L -#define CC_BIF_STRAP6__STRAP_CHIP_BIF_MODE_MASK__CI 0x00000200L -#define CC_BIF_STRAP6__STRAP_PIF_PLL_RAMP_UP_TIME_MASK__CI 0x000000e0L -#define CC_BIF_STRAP6__STRAP_PIF_RXDETECT_SAMPL_TIME_MASK__CI 0x00000018L -#define CC_BIF_STRAP7__STRAP_BIF_E2E_PREFIX_EN_A_MASK__CI 0x00004000L -#define CC_BIF_STRAP7__STRAP_BIF_EXTENDED_FMT_SUPPORTED_A_MASK__CI 0x00008000L -#define CC_BIF_STRAP7__STRAP_BIF_F0_ATS_EN_MASK__CI 0x00400000L -#define CC_BIF_STRAP7__STRAP_BIF_INITIAL_N_FTS_MASK__CI 0x00003fc0L -#define CC_BIF_STRAP7__STRAP_BIF_L1_ACCEPTABLE_LATENCY_MASK__CI 0x0000000eL -#define CC_BIF_STRAP7__STRAP_BIF_MAX_PASID_WIDTH_MASK__CI 0x003e0000L -#define CC_BIF_STRAP7__STRAP_BIF_PASID_PREFIX_SUPPORTED_MASK__CI 0x00010000L -#define CC_BIF_STRAP7__STRAP_BIF_PM_SUPPORT_MASK__CI 0x00000030L -#define CC_BIF_STRAP8__STRAP_RESERVE_MASK__CI 0xfffffffeL -#define CC_BIF_STRAP9__STRAP_BIF_AUDIO_EN_MASK__CI 0x00002000L -#define CC_BIF_STRAP9__STRAP_BIF_AZ_64BAR_DIS_A_MASK__CI 0x00000020L -#define CC_BIF_STRAP9__STRAP_BIF_AZ_LEGACY_DEVICE_TYPE_DIS_MASK__CI 0x00000400L -#define CC_BIF_STRAP9__STRAP_BIF_F0_64BAR_DIS_A_MASK__CI 0x00000008L -#define CC_BIF_STRAP9__STRAP_BIF_F0_BAR_EN_MASK__CI 0x00000040L -#define CC_BIF_STRAP9__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_DIS_MASK__CI 0x00000100L -#define CC_BIF_STRAP9__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_DIS_MASK__CI 0x00000200L -#define CC_BIF_STRAP9__STRAP_BIF_IO_BAR_DIS_MASK__CI 0x00000002L -#define CC_BIF_STRAP9__STRAP_BIF_RX_IGNORE_EP_ERR_MASK__CI 0x00000800L -#define CC_BIF_STRAP9__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK__CI 0x00000080L -#define CC_BIF_STRAP9__STRAP_BIF_VGA_DIS_MASK__CI 0x00000004L -#define CC_BIF_STRAP9__STRAP_CEC_64BAR_DIS_MASK__CI 0x00000010L -#define CC_BIF_STRAP9__STRAP_CEC_PME_SUPPORT_COMPLIANCE_DIS_MASK__CI 0x00001000L -#define CC_BIF_STRAP9__STRAP_RESERVED_MASK__CI 0x003fc000L -#define CC_BIF_STRAP_FUSE0__STRAP_BIF_EP_MODE_MASK__CI 0x00040000L -#define CC_BIF_STRAP_FUSE0__STRAP_BIF_KILL_GEN3_MASK__CI 0x00020000L -#define CC_BIF_STRAP_FUSE0__STRAP_CEC_ID_MASK__CI 0x0001fffeL -#define CC_BIF_STRAP_FUSE0__STRAP_RESERVED_MASK__CI 0x1ff80000L -#define CC_BIF_STRAP_FUSE0__WR_DIS_MASK__CI 0x00000001L -#define CC_CAC_CMON__CMON_ADC_GAIN_ADJ_MASK__CI 0x00000f80L -#define CC_CAC_CMON__CMON_BGADJ_MASK__CI 0x0000007eL -#define CC_CAC_CMON__IDSC_FADC_ADJ_MASK__CI 0x000f0000L -#define CC_CAC_CMON__IDSC_FX_ADJ_MASK__CI 0x0000f000L -#define CC_CAC_CMON__WRITE_DIS_MASK__CI 0x00000001L -#define CC_DC_MISC_STRAPS__DACA_BGADJ_MASK__SI 0x03f00000L -#define CC_DC_MISC_STRAPS__DACB_BGADJ_MASK__SI 0xfc000000L -#define CC_DC_MISC_STRAPS__HDCP_DEBUG_ENABLE_MASK__SI 0x00000080L -#define CC_DC_MISC_STRAPS__HDCP_DIS_MASK__SI 0x00000008L -#define CC_DC_MISC_STRAPS__HDCP_KEYS_INVALID_MASK__SI 0x00000020L -#define CC_DC_MISC_STRAPS__HDMI_DISABLE_MASK__SI 0x00000040L -#define CC_DC_MISC_STRAPS__MACROVISION_DIS_MASK__SI 0x00000010L -#define CC_DC_MISC_STRAPS__MOBILE_DIS_MASK__SI 0x00000002L -#define CC_DC_MISC_STRAPS__SPARE1_MASK__SI 0x00000700L -#define CC_DC_MISC_STRAPS__WRITE_DIS_MASK__SI 0x00000001L -#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L -#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L -#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L -#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L -#define CC_DRM_ID_STRAPS__WRITE_DIS_MASK 0x00000001L -#define CC_GC_EDC_CONFIG__DIS_EDC_MASK__CI__VI 0x00000002L -#define CC_GC_EDC_CONFIG__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK__CI__VI 0x00030000L -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK__CI__VI 0x0f000000L -#define CC_GC_PRIM_CONFIG__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_GC_SHADER_ARRAY_CONFIG__DIS_DPFP_MASK__SI 0x00000002L -#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK__CI 0x00000006L -#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK__CI 0x00000010L -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L -#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK__CI 0x00000008L -#define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS_MASK 0x00000001L -#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK__CI__VI 0x000007feL -#define CC_GIO_IOCCFG_FUSES__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK__CI__VI 0x0000003eL -#define CC_GIO_IOC_FUSES__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_GNB_SECURE_SPARE__DCE_SCAN_DISABLE_MASK__CI__VI 0x00000002L -#define CC_GNB_SECURE_SPARE__GNB_SECURE_SPARE_MASK__CI__VI 0x0000007cL -#define CC_GNB_SECURE_SPARE__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x0000001eL -#define CC_MC_MAX_CHANNEL__WRITE_DISABLE_MASK 0x00000001L -#define CC_PWR_DYN_GF_RM__GF_PDP_RME_MASK__CI__VI 0x08000000L -#define CC_PWR_DYN_GF_RM__GF_PDP_RM_MASK__CI__VI 0x07ffff00L -#define CC_PWR_DYN_GF_RM__GF_RF2P_RME_MASK__CI__VI 0x00000080L -#define CC_PWR_DYN_GF_RM__GF_RF2P_RM_MASK__CI__VI 0x0000007fL -#define CC_PWR_DYN_RM1__BF_HD1P_RMEN_MASK__CI__VI 0x00000004L -#define CC_PWR_DYN_RM1__BF_HD1P_RM_MASK__CI__VI 0x00000003L -#define CC_PWR_DYN_RM1__BF_PDP_RMEN_MASK__CI__VI 0x00000020L -#define CC_PWR_DYN_RM1__BF_PDP_RM_MASK__CI__VI 0x00000018L -#define CC_PWR_DYN_RM1__BF_RF2P_RMEN_MASK__CI__VI 0x00000100L -#define CC_PWR_DYN_RM1__BF_RF2P_RM_MASK__CI__VI 0x000000c0L -#define CC_PWR_DYN_RM1__GFX_HD1P_RMEN_MASK__CI__VI 0x00000800L -#define CC_PWR_DYN_RM1__GFX_HD1P_RM_MASK__CI__VI 0x00000600L -#define CC_PWR_DYN_RM1__GFX_PDP_RMEN_MASK__CI__VI 0x00004000L -#define CC_PWR_DYN_RM1__GFX_PDP_RM_MASK__CI__VI 0x00003000L -#define CC_PWR_DYN_RM1__GFX_RF2P_RMEN_MASK__CI__VI 0x00020000L -#define CC_PWR_DYN_RM1__GFX_RF2P_RM_MASK__CI__VI 0x00018000L -#define CC_PWR_DYN_RM1__UVD_HD1P_RMEN_MASK__CI__VI 0x00100000L -#define CC_PWR_DYN_RM1__UVD_HD1P_RM_MASK__CI__VI 0x000c0000L -#define CC_PWR_DYN_RM1__UVD_PDP_RMEN_MASK__CI__VI 0x00800000L -#define CC_PWR_DYN_RM1__UVD_PDP_RM_MASK__CI__VI 0x00600000L -#define CC_PWR_DYN_RM1__UVD_RF2P_RMEN_MASK__CI__VI 0x04000000L -#define CC_PWR_DYN_RM1__UVD_RF2P_RM_MASK__CI__VI 0x03000000L -#define CC_PWR_DYN_RM__DT_HD1P_RMEN_MASK__CI__VI 0x00100000L -#define CC_PWR_DYN_RM__DT_HD1P_RM_MASK__CI__VI 0x000c0000L -#define CC_PWR_DYN_RM__DT_PDP_RMEN_MASK__CI__VI 0x00800000L -#define CC_PWR_DYN_RM__DT_PDP_RM_MASK__CI__VI 0x00600000L -#define CC_PWR_DYN_RM__DT_RF2P_RMEN_MASK__CI__VI 0x04000000L -#define CC_PWR_DYN_RM__DT_RF2P_RM_MASK__CI__VI 0x03000000L -#define CC_PWR_DYN_RM__MC_HD1P_RMEN_MASK__CI__VI 0x00000800L -#define CC_PWR_DYN_RM__MC_HD1P_RM_MASK__CI__VI 0x00000600L -#define CC_PWR_DYN_RM__MC_PDP_RMEN_MASK__CI__VI 0x00004000L -#define CC_PWR_DYN_RM__MC_PDP_RM_MASK__CI__VI 0x00003000L -#define CC_PWR_DYN_RM__MC_RF2P_RMEN_MASK__CI__VI 0x00020000L -#define CC_PWR_DYN_RM__MC_RF2P_RM_MASK__CI__VI 0x00018000L -#define CC_PWR_DYN_RM__RM_REG_SEL_MASK__CI__VI 0x08000000L -#define CC_PWR_DYN_RM__SYS_HD1P_RMEN_MASK__CI__VI 0x00000004L -#define CC_PWR_DYN_RM__SYS_HD1P_RM_MASK__CI__VI 0x00000003L -#define CC_PWR_DYN_RM__SYS_PDP_RMEN_MASK__CI__VI 0x00000020L -#define CC_PWR_DYN_RM__SYS_PDP_RM_MASK__CI__VI 0x00000018L -#define CC_PWR_DYN_RM__SYS_RF2P_RMEN_MASK__CI__VI 0x00000100L -#define CC_PWR_DYN_RM__SYS_RF2P_RM_MASK__CI__VI 0x000000c0L -#define CC_PWR_GF_RM__GF_PDP_RME_MASK__CI__VI 0x10000000L -#define CC_PWR_GF_RM__GF_PDP_RM_MASK__CI__VI 0x0ffffe00L -#define CC_PWR_GF_RM__GF_RF2P_RME_MASK__CI__VI 0x00000100L -#define CC_PWR_GF_RM__GF_RF2P_RM_MASK__CI__VI 0x000000feL -#define CC_PWR_GF_RM__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_PWR_RM0__DT_HD1P_RMEN_MASK__CI__VI 0x00200000L -#define CC_PWR_RM0__DT_HD1P_RM_MASK__CI__VI 0x00180000L -#define CC_PWR_RM0__DT_PDP_RMEN_MASK__CI__VI 0x01000000L -#define CC_PWR_RM0__DT_PDP_RM_MASK__CI__VI 0x00c00000L -#define CC_PWR_RM0__DT_RF2P_RMEN_MASK__CI__VI 0x08000000L -#define CC_PWR_RM0__DT_RF2P_RM_MASK__CI__VI 0x06000000L -#define CC_PWR_RM0__MC_HD1P_RMEN_MASK__CI__VI 0x00001000L -#define CC_PWR_RM0__MC_HD1P_RM_MASK__CI__VI 0x00000c00L -#define CC_PWR_RM0__MC_PDP_RMEN_MASK__CI__VI 0x00008000L -#define CC_PWR_RM0__MC_PDP_RM_MASK__CI__VI 0x00006000L -#define CC_PWR_RM0__MC_RF2P_RMEN_MASK__CI__VI 0x00040000L -#define CC_PWR_RM0__MC_RF2P_RM_MASK__CI__VI 0x00030000L -#define CC_PWR_RM0__RM_FUSE_SEL_MASK__CI__VI 0x10000000L -#define CC_PWR_RM0__SYS_HD1P_RMEN_MASK__CI__VI 0x00000008L -#define CC_PWR_RM0__SYS_HD1P_RM_MASK__CI__VI 0x00000006L -#define CC_PWR_RM0__SYS_PDP_RMEN_MASK__CI__VI 0x00000040L -#define CC_PWR_RM0__SYS_PDP_RM_MASK__CI__VI 0x00000030L -#define CC_PWR_RM0__SYS_RF2P_RMEN_MASK__CI__VI 0x00000200L -#define CC_PWR_RM0__SYS_RF2P_RM_MASK__CI__VI 0x00000180L -#define CC_PWR_RM0__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_PWR_RM1__BF_HD1P_RMEN_MASK__CI__VI 0x00000008L -#define CC_PWR_RM1__BF_HD1P_RM_MASK__CI__VI 0x00000006L -#define CC_PWR_RM1__BF_PDP_RMEN_MASK__CI__VI 0x00000040L -#define CC_PWR_RM1__BF_PDP_RM_MASK__CI__VI 0x00000030L -#define CC_PWR_RM1__BF_RF2P_RMEN_MASK__CI__VI 0x00000200L -#define CC_PWR_RM1__BF_RF2P_RM_MASK__CI__VI 0x00000180L -#define CC_PWR_RM1__GFX_HD1P_RMEN_MASK__CI__VI 0x00001000L -#define CC_PWR_RM1__GFX_HD1P_RM_MASK__CI__VI 0x00000c00L -#define CC_PWR_RM1__GFX_PDP_RMEN_MASK__CI__VI 0x00008000L -#define CC_PWR_RM1__GFX_PDP_RM_MASK__CI__VI 0x00006000L -#define CC_PWR_RM1__GFX_RF2P_RMEN_MASK__CI__VI 0x00040000L -#define CC_PWR_RM1__GFX_RF2P_RM_MASK__CI__VI 0x00030000L -#define CC_PWR_RM1__UVD_HD1P_RMEN_MASK__CI__VI 0x00200000L -#define CC_PWR_RM1__UVD_HD1P_RM_MASK__CI__VI 0x00180000L -#define CC_PWR_RM1__UVD_PDP_RMEN_MASK__CI__VI 0x01000000L -#define CC_PWR_RM1__UVD_PDP_RM_MASK__CI__VI 0x00c00000L -#define CC_PWR_RM1__UVD_RF2P_RMEN_MASK__CI__VI 0x08000000L -#define CC_PWR_RM1__UVD_RF2P_RM_MASK__CI__VI 0x06000000L -#define CC_PWR_RM1__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L -#define CC_RB_BACKEND_DISABLE__WRITE_DIS_MASK 0x00000001L -#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL -#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L -#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L -#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L -#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L -#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L -#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L -#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK__CI__VI 0x00001000L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK__CI__VI 0x00100000L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY_MASK__SI 0x80000000L -#define CC_RB_REDUNDANCY__FAILED_RB0_MASK__CI__VI 0x00000f00L -#define CC_RB_REDUNDANCY__FAILED_RB1_MASK__CI__VI 0x000f0000L -#define CC_RB_REDUNDANCY__FAILED_RB_MASK__SI 0x00070000L -#define CC_RB_REDUNDANCY__WRITE_DIS_MASK 0x00000001L -#define CC_RCU_CG_STRAPS__CTF_DISABLE_MASK__SI 0x00040000L -#define CC_RCU_CG_STRAPS__FDO_INIT_SPINUP_DUTY_MASK__SI 0x0e000000L -#define CC_RCU_CG_STRAPS__FDO_INIT_SPINUP_TIME_MASK__SI 0x01c00000L -#define CC_RCU_CG_STRAPS__FDO_INIT_STATIC_DUTY_MASK__SI 0x70000000L -#define CC_RCU_CG_STRAPS__SPARE_MASK__SI 0x00200000L -#define CC_RCU_CG_STRAPS__UNUSED_MASK__SI 0x0001fffeL -#define CC_RCU_CG_STRAPS__WRITE_DIS_MASK__SI 0x00000001L -#define CC_RCU_CMON_STRAPS__CMON_ADC_GAIN_ADJ_MASK__SI 0x000003c0L -#define CC_RCU_CMON_STRAPS__CMON_BGADJ_MASK__SI 0x0000003fL -#define CC_RCU_DC_MISC_STRAPS__AZ_AUD_PIN_DIS_MASK__SI 0xfc000000L -#define CC_RCU_DC_MISC_STRAPS__DACA_BGADJ_MASK__SI 0x03f00000L -#define CC_RCU_DC_MISC_STRAPS__DC_CP_DEBUG_DIS_MASK__SI 0x00000008L -#define CC_RCU_DC_MISC_STRAPS__DC_WRITE_DIS_MASK__SI 0x00000001L -#define CC_RCU_DC_MISC_STRAPS__HDCP_DEBUG_ENABLE_MASK__SI 0x00000080L -#define CC_RCU_DC_MISC_STRAPS__HDCP_DIS_MASK__SI 0x00000004L -#define CC_RCU_DC_MISC_STRAPS__HDCP_KEYS_INVALID_MASK__SI 0x00000010L -#define CC_RCU_DC_MISC_STRAPS__HDMI_DISABLE_MASK__SI 0x00000020L -#define CC_RCU_DC_MISC_STRAPS__SPARE_MASK__SI 0x00000002L -#define CC_RCU_DC_MISC_STRAPS__UNUSED_MASK__SI 0x00000700L -#define CC_RCU_DC_PIPE_DIS__DC_PIPE_DIS_MASK__SI 0x0000001eL -#define CC_RCU_DC_PIPE_DIS__DC_WRITE_DIS_MASK__SI 0x00000001L -#define CC_RCU_DYN_RM2__BF_HD1P_RMEN_MASK__SI 0x00000004L -#define CC_RCU_DYN_RM2__BF_HD1P_RM_MASK__SI 0x00000003L -#define CC_RCU_DYN_RM2__BF_PDP_RMEN_MASK__SI 0x00000020L -#define CC_RCU_DYN_RM2__BF_PDP_RM_MASK__SI 0x00000018L -#define CC_RCU_DYN_RM2__BF_RF2P_RMEN_MASK__SI 0x00000100L -#define CC_RCU_DYN_RM2__BF_RF2P_RM_MASK__SI 0x000000c0L -#define CC_RCU_DYN_RM2__GFX_HD1P_RMEN_MASK__SI 0x00000800L -#define CC_RCU_DYN_RM2__GFX_HD1P_RM_MASK__SI 0x00000600L -#define CC_RCU_DYN_RM2__GFX_PDP_RMEN_MASK__SI 0x00004000L -#define CC_RCU_DYN_RM2__GFX_PDP_RM_MASK__SI 0x00003000L -#define CC_RCU_DYN_RM2__GFX_RF2P_RMEN_MASK__SI 0x00020000L -#define CC_RCU_DYN_RM2__GFX_RF2P_RM_MASK__SI 0x00018000L -#define CC_RCU_DYN_RM2__UVD_HD1P_RMEN_MASK__SI 0x00100000L -#define CC_RCU_DYN_RM2__UVD_HD1P_RM_MASK__SI 0x000c0000L -#define CC_RCU_DYN_RM2__UVD_PDP_RMEN_MASK__SI 0x00800000L -#define CC_RCU_DYN_RM2__UVD_PDP_RM_MASK__SI 0x00600000L -#define CC_RCU_DYN_RM2__UVD_RF2P_RMEN_MASK__SI 0x04000000L -#define CC_RCU_DYN_RM2__UVD_RF2P_RM_MASK__SI 0x03000000L -#define CC_RCU_DYN_RM__DC_HD1P_RMEN_MASK__SI 0x00100000L -#define CC_RCU_DYN_RM__DC_HD1P_RM_MASK__SI 0x000c0000L -#define CC_RCU_DYN_RM__DC_PDP_RMEN_MASK__SI 0x00800000L -#define CC_RCU_DYN_RM__DC_PDP_RM_MASK__SI 0x00600000L -#define CC_RCU_DYN_RM__DC_RF2P_RMEN_MASK__SI 0x04000000L -#define CC_RCU_DYN_RM__DC_RF2P_RM_MASK__SI 0x03000000L -#define CC_RCU_DYN_RM__MC_HD1P_RMEN_MASK__SI 0x00000800L -#define CC_RCU_DYN_RM__MC_HD1P_RM_MASK__SI 0x00000600L -#define CC_RCU_DYN_RM__MC_PDP_RMEN_MASK__SI 0x00004000L -#define CC_RCU_DYN_RM__MC_PDP_RM_MASK__SI 0x00003000L -#define CC_RCU_DYN_RM__MC_RF2P_RMEN_MASK__SI 0x00020000L -#define CC_RCU_DYN_RM__MC_RF2P_RM_MASK__SI 0x00018000L -#define CC_RCU_DYN_RM__SYS_HD1P_RMEN_MASK__SI 0x00000004L -#define CC_RCU_DYN_RM__SYS_HD1P_RM_MASK__SI 0x00000003L -#define CC_RCU_DYN_RM__SYS_PDP_RMEN_MASK__SI 0x00000020L -#define CC_RCU_DYN_RM__SYS_PDP_RM_MASK__SI 0x00000018L -#define CC_RCU_DYN_RM__SYS_RF2P_RMEN_MASK__SI 0x00000100L -#define CC_RCU_DYN_RM__SYS_RF2P_RM_MASK__SI 0x000000c0L -#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK__CI 0x00100000L -#define CC_RCU_FUSES__CC_WRITE_DISABLE_MASK__CI__VI 0x00000008L -#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK__CI__VI 0x00000020L -#define CC_RCU_FUSES__DC_WRITE_DIS_MASK__CI__VI 0x00001000L -#define CC_RCU_FUSES__DEBUG_DISABLE_MASK__CI__VI 0x00000004L -#define CC_RCU_FUSES__DRV_RST_MODE_MASK__CI__VI 0x00000040L -#define CC_RCU_FUSES__DSMU_DISABLE_MASK__CI 0x01000000L -#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK__CI__VI 0x00000010L -#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK__CI 0x00010000L -#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK__CI 0x00020000L -#define CC_RCU_FUSES__GPU_DIS_MASK__CI__VI 0x00000002L -#define CC_RCU_FUSES__GPU_ID_WRITE_DIS_MASK__CI__VI 0x00000800L -#define CC_RCU_FUSES__HDCP_FUSE_DISABLE_MASK__CI__VI 0x00002000L -#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK__CI__VI 0x00000100L -#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK__CI 0x00400000L -#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK__CI 0x00800000L -#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK__CI 0x00004000L -#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK__CI__VI 0x00000200L -#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK__CI__VI 0x00000400L -#define CC_RCU_FUSES__RCU_SPARE_MASK__CI 0xfe000000L -#define CC_RCU_FUSES__RED_WRITE_DIS_MASK__CI 0x00200000L -#define CC_RCU_FUSES__ROM_DIS_MASK__CI__VI 0x00000080L -#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK__CI 0x00080000L -#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK__CI 0x00008000L -#define CC_RCU_FUSES__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_RCU_FUSES__XFIRE_DISABLE_MASK__CI 0x00040000L -#define CC_RCU_ID_STRAPS__ATI_REV_ID_MASK__SI 0xf0000000L -#define CC_RCU_ID_STRAPS__DEVICE_ID_MASK__SI 0x000ffff0L -#define CC_RCU_ID_STRAPS__MAJOR_REV_ID_MASK__SI 0x00f00000L -#define CC_RCU_ID_STRAPS__MINOR_REV_ID_MASK__SI 0x0f000000L -#define CC_RCU_ID_STRAPS__Reserved_MASK__SI 0x0000000eL -#define CC_RCU_ID_STRAPS__WRITE_DIS_MASK__SI 0x00000001L -#define CC_RCU_MISC_STRAPS__LEAKAGE_ID_MASK__SI 0x00003ff0L -#define CC_RCU_MISC_STRAPS__PACKAGE_ID_MASK__SI 0x0000000fL -#define CC_RCU_MISC_STRAPS__SPARE_MASK__SI 0xffff0000L -#define CC_RCU_MISC_STRAPS__UNUSED_MASK__SI 0x0000c000L -#define CC_RCU_TMON_STRAPS__TMON0_BGADJ_MASK__SI 0x000000ffL -#define CC_RCU_TMON_STRAPS__TMON1_BGADJ_MASK__SI 0x0000ff00L -#define CC_RCU_TMON_STRAPS__TMON2_BGADJ_MASK__SI 0x00ff0000L -#define CC_RCU_TMON_STRAPS__TMON3_BGADJ_MASK__SI 0xff000000L -#define CC_SCLK_VID_FUSES__SClkVid0_MASK__CI__VI 0x000000ffL -#define CC_SCLK_VID_FUSES__SClkVid1_MASK__CI__VI 0x0000ff00L -#define CC_SCLK_VID_FUSES__SClkVid2_MASK__CI__VI 0x00ff0000L -#define CC_SCLK_VID_FUSES__SClkVid3_MASK__CI__VI 0xff000000L -#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK__CI__VI 0x60000000L -#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK__CI__VI 0x10000000L -#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK__CI__VI 0x00000002L -#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK__CI__VI 0x00040000L -#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK__CI__VI 0x00800000L -#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK__CI__VI 0x00100000L -#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK__CI__VI 0x00200000L -#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK__CI__VI 0x00400000L -#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK__CI__VI 0x00080000L -#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK__CI__VI 0x00000600L -#define CC_SMU_MISC_FUSES__MinSClkDid_MASK__CI__VI 0x000001fcL -#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK__CI__VI 0x0003f800L -#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK__CI__VI 0x08000000L -#define CC_SMU_MISC_FUSES__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK__CI__VI 0x00001000L -#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK__CI__VI 0x00002000L -#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK__CI__VI 0x04000000L -#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK__CI__VI 0x00400000L -#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK__CI__VI 0x00800000L -#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK__CI__VI 0x01000000L -#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK__CI__VI 0x00000400L -#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK__CI__VI 0x00000100L -#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK__CI__VI 0x00000080L -#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK__CI__VI 0x0000003eL -#define CC_SMU_TST_EFUSE1_MISC__RME_MASK__CI__VI 0x00000040L -#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK__CI__VI 0x00004000L -#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK__CI__VI 0x00000800L -#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK__CI__VI 0x00000200L -#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK__CI__VI 0x02000000L -#define CC_SMU_TST_EFUSE1_MISC__WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L -#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L -#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK__CI__VI 0x0f000000L -#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK__CI__VI 0xf0000000L -#define CC_SQC_BANK_DISABLE__WRITE_DIS_MASK 0x00000001L -#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L -#define CC_SYS_RB_BACKEND_DISABLE__WRITE_DIS_MASK 0x00000001L -#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY_MASK__SI__CI 0x80000000L -#define CC_SYS_RB_REDUNDANCY__FAILED_RB_MASK__SI__CI 0x00070000L -#define CC_SYS_RB_REDUNDANCY__WRITE_DIS_MASK 0x00000001L -#define CC_THM_FDO__FDO_INIT_SPINUP_DUTY_MASK__CI 0x00000070L -#define CC_THM_FDO__FDO_INIT_SPINUP_TIME_MASK__CI 0x0000000eL -#define CC_THM_FDO__FDO_INIT_STATIC_DUTY_MASK__CI 0x00000380L -#define CC_THM_FDO__FUSES_PROGRAMMED_MASK__CI 0x00000400L -#define CC_THM_FDO__UNUSED_MASK__CI 0x80000000L -#define CC_THM_FDO__WRITE_DIS_MASK__CI 0x00000001L -#define CC_THM_STRAPS0__CTF_DISABLE_MASK__CI 0x02000000L -#define CC_THM_STRAPS0__NUM_ACQ_MASK__CI 0x001c0000L -#define CC_THM_STRAPS0__TMON0_BGADJ_MASK__CI 0x000001feL -#define CC_THM_STRAPS0__TMON0_DISABLE_MASK__CI 0x04000000L -#define CC_THM_STRAPS0__TMON1_BGADJ_MASK__CI 0x0001fe00L -#define CC_THM_STRAPS0__TMON1_DISABLE_MASK__CI 0x08000000L -#define CC_THM_STRAPS0__TMON2_DISABLE_MASK__CI 0x10000000L -#define CC_THM_STRAPS0__TMON3_DISABLE_MASK__CI 0x20000000L -#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK__CI 0x00e00000L -#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK__CI 0x00020000L -#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK__CI 0x01000000L -#define CC_THM_STRAPS0__UNUSED_MASK__CI 0x80000000L -#define CC_THM_STRAPS0__WRITE_DIS_MASK__CI 0x00000001L -#define CC_THM_STRAPS1__TMON2_BGADJ_MASK__CI 0x000001feL -#define CC_THM_STRAPS1__TMON3_BGADJ_MASK__CI 0x0001fe00L -#define CC_THM_STRAPS1__UNUSED_MASK__CI 0x80000000L -#define CC_THM_STRAPS1__WRITE_DIS_MASK__CI 0x00000001L -#define CC_TST_EFUSE0_RM__HD_FUSE_MASK 0x00fe0000L -#define CC_TST_EFUSE0_RM__PDP_FUSE_MASK 0x0001fffeL -#define CC_TST_EFUSE0_RM__RF_FUSE_MASK 0x7f000000L -#define CC_TST_EFUSE0_RM__RME_FUSE_MASK 0x80000000L -#define CC_TST_EFUSE0_RM__WRITE_DIS_MASK 0x00000001L -#define CC_TST_EFUSE1_MISC__GPU_DISABLE_MASK 0x00000008L -#define CC_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x00000002L -#define CC_TST_EFUSE1_MISC__INTERNAL_GFX_DISABLE_MASK 0x00000010L -#define CC_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x00000004L -#define CC_TST_EFUSE1_MISC__WRITE_DIS_MASK 0x00000001L -#define CC_TST_ID_STRAPS__DEVICE_ID_MASK__CI__VI 0x000ffff0L -#define CC_TST_ID_STRAPS__GPU_ID_WRITE_DIS_MASK__CI__VI 0x00000001L -#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK__CI__VI 0x00f00000L -#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK__CI__VI 0x0f000000L -#define CEC_ADDR__LOGIC_ADDR0_MASK__CI__VI 0x0000000fL -#define CEC_ADDR__LOGIC_ADDR1_MASK__CI__VI 0x000000f0L -#define CEC_ADDR__LOGIC_ADDR2_MASK__CI__VI 0x00000f00L -#define CEC_ADDR__PHYSICAL_ADDR_MASK__CI__VI 0xffff0000L -#define CEC_CONTROL__BACO_D0_PME_INTX_SEL_MASK__CI__VI 0x00000010L -#define CEC_CONTROL__CEC_ENABLE_MASK__CI__VI 0x00000001L -#define CEC_CONTROL__INTX_FUNC_NUM_MASK__CI__VI 0x00000c00L -#define CEC_CONTROL__INT_MSG_TYPE_MASK__CI__VI 0x00000060L -#define CEC_CONTROL__PME_FUNC_NUM_MASK__CI__VI 0x0000000cL -#define CEC_CONTROL__SAMPLE_CLK_SRC_SEL_MASK__CI__VI 0x00000300L -#define CEC_CONTROL__TX_SEND_ENABLE_MASK__CI__VI 0x00000002L -#define CEC_DATA_LENGTH__RX_DATA_LENGTH_MASK__CI__VI 0x000000f0L -#define CEC_DATA_LENGTH__TX_DATA_LENGTH_MASK__CI__VI 0x0000000fL -#define CEC_HPD_CONTROL__HPD_CONNECTION_TIMER_MASK__CI__VI 0x00003ffeL -#define CEC_HPD_CONTROL__HPD_EN_MASK__CI__VI 0x00000001L -#define CEC_HPD_CONTROL__HPD_RX_INT_TIMER_MASK__CI__VI 0x03ff0000L -#define CEC_HPD_TOGGLE_FILT_CONTROL__HPD_CONNECT_INT_DELAY_MASK__CI__VI 0x000000ffL -#define CEC_HPD_TOGGLE_FILT_CONTROL__HPD_DISCONNECT_INT_DELAY_MASK__CI__VI 0x0000ff00L -#define CEC_INT_EN__BLOCK_ALL_BROADCAST_EN_MASK__CI__VI 0x00000004L -#define CEC_INT_EN__BLOCK_PART_BROADCAST_EN_MASK__CI__VI 0x00000002L -#define CEC_INT_EN__CEC_LINE_ERR_EN_MASK__CI__VI 0x00000001L -#define CEC_INT_EN__DEST_MISMATCH_EN_MASK__CI__VI 0x00000080L -#define CEC_INT_EN__HPD_INT_EN_MASK__CI__VI 0x00000100L -#define CEC_INT_EN__HPD_UNPLUG_INT_EN_MASK__CI__VI 0x00000200L -#define CEC_INT_EN__LOST_ARB_ERR_EN_MASK__CI__VI 0x00000040L -#define CEC_INT_EN__PHYSICAL_ADDRESS_INT_EN_MASK__CI__VI 0x00000400L -#define CEC_INT_EN__RETRY_FAILED_EN_MASK__CI__VI 0x00000008L -#define CEC_INT_EN__RX_IOC_EN_MASK__CI__VI 0x00000020L -#define CEC_INT_EN__TX_IOC_EN_MASK__CI__VI 0x00000010L -#define CEC_MISC__RETRY_COUNTER_MASK__CI__VI 0x00000007L -#define CEC_PAD_CNTL__CEC_PAD_A_MASK__CI__VI 0x00000001L -#define CEC_PAD_CNTL__CEC_PAD_CNTL_EN_MASK__CI__VI 0x00001000L -#define CEC_PAD_CNTL__CEC_PAD_MODE_MASK__CI__VI 0x00000004L -#define CEC_PAD_CNTL__CEC_PAD_SCHMEN_MASK__CI__VI 0x00000800L -#define CEC_PAD_CNTL__CEC_PAD_SEL_MASK__CI__VI 0x00000002L -#define CEC_PAD_CNTL__CEC_PAD_SLEWN_MASK__CI__VI 0x00000200L -#define CEC_PAD_CNTL__CEC_PAD_SN0_MASK__CI__VI 0x00000020L -#define CEC_PAD_CNTL__CEC_PAD_SN1_MASK__CI__VI 0x00000040L -#define CEC_PAD_CNTL__CEC_PAD_SN2_MASK__CI__VI 0x00000080L -#define CEC_PAD_CNTL__CEC_PAD_SN3_MASK__CI__VI 0x00000100L -#define CEC_PAD_CNTL__CEC_PAD_SPARE_MASK__CI__VI 0x00000018L -#define CEC_PAD_CNTL__CEC_PAD_WAKE_MASK__CI__VI 0x00000400L -#define CEC_RX_DATA_0__RX_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_RX_DATA_0__RX_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_RX_DATA_0__RX_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_RX_DATA_0__RX_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_RX_DATA_1__RX_BYTE_4_MASK__CI__VI 0x000000ffL -#define CEC_RX_DATA_1__RX_BYTE_5_MASK__CI__VI 0x0000ff00L -#define CEC_RX_DATA_1__RX_BYTE_6_MASK__CI__VI 0x00ff0000L -#define CEC_RX_DATA_1__RX_BYTE_7_MASK__CI__VI 0xff000000L -#define CEC_RX_DATA_2__RX_BYTE_8_MASK__CI__VI 0x000000ffL -#define CEC_RX_DATA_2__RX_BYTE_9_MASK__CI__VI 0x0000ff00L -#define CEC_RX_DATA_2__RX_BYTE_A_MASK__CI__VI 0x00ff0000L -#define CEC_RX_DATA_2__RX_BYTE_B_MASK__CI__VI 0xff000000L -#define CEC_RX_DATA_3__RX_BYTE_C_MASK__CI__VI 0x000000ffL -#define CEC_RX_DATA_3__RX_BYTE_D_MASK__CI__VI 0x0000ff00L -#define CEC_RX_DATA_3__RX_BYTE_E_MASK__CI__VI 0x00ff0000L -#define CEC_RX_DATA_3__RX_BYTE_F_MASK__CI__VI 0xff000000L -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_STATUS__CEC_RESET_DONE_MASK__CI__VI 0x00004000L -#define CEC_STATUS__DEST_MISMATCH_MASK__CI__VI 0x00000080L -#define CEC_STATUS__HPD_CONNECTION_STATUS_MASK__CI__VI 0x00000100L -#define CEC_STATUS__HPD_PLUG_EVENT_MASK__CI__VI 0x00000200L -#define CEC_STATUS__HPD_UNPLUG_EVENT_MASK__CI__VI 0x00000400L -#define CEC_STATUS__LINE_ERROR_MASK__CI__VI 0x00000002L -#define CEC_STATUS__LOST_ARB_ERR_MASK__CI__VI 0x00000040L -#define CEC_STATUS__PHYSICAL_ADDRESS_ALLO_EVENT_MASK__CI__VI 0x00001000L -#define CEC_STATUS__PHYSICAL_ADDRESS_LOSE_EVENT_MASK__CI__VI 0x00002000L -#define CEC_STATUS__PHYSICAL_ADDRESS_READY_MASK__CI__VI 0x00000800L -#define CEC_STATUS__RETRY_FAILED_MASK__CI__VI 0x00000008L -#define CEC_STATUS__RX_BUFFER_BUSY_MASK__CI__VI 0x00000001L -#define CEC_STATUS__RX_IOC_MASK__CI__VI 0x00000020L -#define CEC_STATUS__TX_IOC_MASK__CI__VI 0x00000010L -#define CEC_SW_OPCODE_0__WAKE_OPCODE_0_MASK__CI__VI 0x000000ffL -#define CEC_SW_OPCODE_0__WAKE_OPCODE_1_MASK__CI__VI 0x0000ff00L -#define CEC_SW_OPCODE_0__WAKE_OPCODE_2_MASK__CI__VI 0x00ff0000L -#define CEC_SW_OPCODE_0__WAKE_OPCODE_3_MASK__CI__VI 0xff000000L -#define CEC_SW_OPCODE_1__WAKE_OPCODE_4_MASK__CI__VI 0x000000ffL -#define CEC_SW_OPCODE_1__WAKE_OPCODE_5_MASK__CI__VI 0x0000ff00L -#define CEC_SW_OPCODE_1__WAKE_OPCODE_6_MASK__CI__VI 0x00ff0000L -#define CEC_SW_OPCODE_1__WAKE_OPCODE_7_MASK__CI__VI 0xff000000L -#define CEC_TX_DATA_0__TX_BYTE_0_MASK__CI__VI 0x000000ffL -#define CEC_TX_DATA_0__TX_BYTE_1_MASK__CI__VI 0x0000ff00L -#define CEC_TX_DATA_0__TX_BYTE_2_MASK__CI__VI 0x00ff0000L -#define CEC_TX_DATA_0__TX_BYTE_3_MASK__CI__VI 0xff000000L -#define CEC_TX_DATA_1__TX_BYTE_4_MASK__CI__VI 0x000000ffL -#define CEC_TX_DATA_1__TX_BYTE_5_MASK__CI__VI 0x0000ff00L -#define CEC_TX_DATA_1__TX_BYTE_6_MASK__CI__VI 0x00ff0000L -#define CEC_TX_DATA_1__TX_BYTE_7_MASK__CI__VI 0xff000000L -#define CEC_TX_DATA_2__TX_BYTE_8_MASK__CI__VI 0x000000ffL -#define CEC_TX_DATA_2__TX_BYTE_9_MASK__CI__VI 0x0000ff00L -#define CEC_TX_DATA_2__TX_BYTE_A_MASK__CI__VI 0x00ff0000L -#define CEC_TX_DATA_2__TX_BYTE_B_MASK__CI__VI 0xff000000L -#define CEC_TX_DATA_3__TX_BYTE_C_MASK__CI__VI 0x000000ffL -#define CEC_TX_DATA_3__TX_BYTE_D_MASK__CI__VI 0x0000ff00L -#define CEC_TX_DATA_3__TX_BYTE_E_MASK__CI__VI 0x00ff0000L -#define CEC_TX_DATA_3__TX_BYTE_F_MASK__CI__VI 0xff000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK__CI__VI 0x007f0000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU10_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU11_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK__CI__VI 0x007f0000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU13_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU14_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU15_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU1_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU2_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU3_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK__CI__VI 0x007f0000L -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU5_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU6_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU7_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK__CI__VI 0x007f0000L -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK__CI__VI 0x0000007fL -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK__CI__VI 0x007f0000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK__CI__VI 0x0000007fL -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK__CI__VI 0x007f0000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK__CI__VI 0x0000007fL -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK__CI__VI 0x007f0000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU9_TA_CTRL_REG__TA_MASK__CI__VI 0x0000007fL -#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__CI__VI 0x03000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__CI__VI 0x04000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK__CI__VI 0x007f0000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__CI__VI 0x00800000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x08000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__CI__VI 0x00000300L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__CI__VI 0x00000400L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK__CI__VI 0x0000007fL -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__CI__VI 0x00000080L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__CI__VI 0x00000800L -#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL -#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C0_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C0_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C0_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C0_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C0_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C0_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C0_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C0_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_MASK__SI 0x007f0000L -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C1_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C1_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C1_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C1_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C1_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C1_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C1_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C1_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C1_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C1_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C2_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C2_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C2_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C2_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C2_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C2_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C2_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C2_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C2_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C2_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C3_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C3_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C3_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C3_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C3_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C3_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C3_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C3_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C3_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C3_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C4_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C4_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C4_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C4_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C4_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C4_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C4_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C4_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_MASK__SI 0x007f0000L -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C5_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C5_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C5_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C5_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C5_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C5_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C5_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C5_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C5_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C5_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C6_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C6_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C6_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C6_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C6_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C6_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C6_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C6_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C6_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C6_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C7_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S0C7_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C7_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S0C7_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C7_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S0C7_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C7_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S0C7_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C7_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S0C7_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C0_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C0_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C0_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C0_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C0_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C0_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C0_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C0_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_MASK__SI 0x007f0000L -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C1_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C1_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C1_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C1_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C1_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C1_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C1_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C1_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C1_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C1_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C2_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C2_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C2_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C2_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C2_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C2_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C2_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C2_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C2_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C2_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C3_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C3_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C3_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C3_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C3_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C3_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C3_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C3_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C3_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C3_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C4_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C4_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C4_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C4_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C4_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C4_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C4_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C4_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_MASK__SI 0x007f0000L -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C5_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C5_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C5_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C5_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C5_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C5_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C5_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C5_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C5_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C5_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C6_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C6_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C6_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C6_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C6_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C6_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C6_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C6_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C6_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C6_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_MASK__SI 0x0000007fL -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_MASK__SI 0x007f0000L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C7_SP0_CTRL_REG__SP00_MASK__SI 0x0000007fL -#define CGTS_S1C7_SP0_CTRL_REG__SP00_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C7_SP0_CTRL_REG__SP01_MASK__SI 0x007f0000L -#define CGTS_S1C7_SP0_CTRL_REG__SP01_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C7_SP1_CTRL_REG__SP10_MASK__SI 0x0000007fL -#define CGTS_S1C7_SP1_CTRL_REG__SP10_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C7_SP1_CTRL_REG__SP11_MASK__SI 0x007f0000L -#define CGTS_S1C7_SP1_CTRL_REG__SP11_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C7_TA_CTRL_REG__TA_MASK__SI 0x0000007fL -#define CGTS_S1C7_TA_CTRL_REG__TA_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK__SI 0x03000000L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK__SI 0x04000000L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_MASK__SI 0x007f0000L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK__SI 0x00800000L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK__SI 0x08000000L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK__SI 0x00000300L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK__SI 0x00000400L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_MASK__SI 0x0000007fL -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK__SI 0x00000080L -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK__SI 0x00000800L -#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L -#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L -#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL -#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L -#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L -#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L -#define CGTS_TCC_DISABLE__WRITE_DIS_MASK 0x00000001L -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x00fff000L -#define CGTT_BIF_CLK_CTRL0__OFF_HYSTERESIS_MASK__SI 0x00000ff0L -#define CGTT_BIF_CLK_CTRL0__ON_DELAY_MASK__SI 0x0000000fL -#define CGTT_BIF_CLK_CTRL0__SOFT_OVERRIDE0_MASK__SI 0x80000000L -#define CGTT_BIF_CLK_CTRL0__SOFT_OVERRIDE1_MASK__SI 0x40000000L -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK__CI__VI 0x00000ff0L -#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK__CI__VI 0x0000000fL -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK__CI__VI 0x40000000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK__CI__VI 0x80000000L -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK__CI__VI 0x00000ff0L -#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK__CI__VI 0x0000000fL -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK__CI__VI 0x40000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK__CI__VI 0x80000000L -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_IA_CLK_CTRL__ADC_OVERRIDE_MASK__SI 0x10000000L -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK__CI__VI 0x40000000L -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK__SI 0x20000000L -#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L -#define CGTT_IA_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK__SI 0x40000000L -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK__CI__VI 0x20000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK__CI__VI 0x10000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L -#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x02000000L -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x04000000L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x00fff000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x00fff000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK__SI__CI 0x01000000L -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x00fff000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK__SI__CI 0x01000000L -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x00fff000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK__SI__CI 0x01000000L -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x00fff000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK__SI__CI 0x01000000L -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK__SI__CI 0x10000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK__CI 0x10000000L -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK__CI__VI 0x20000000L -#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK__CI__VI 0x04000000L -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK__CI__VI 0x00000ff0L -#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK__CI__VI 0x0000000fL -#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK__CI__VI 0x02000000L -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK__CI__VI 0x40000000L -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK__CI__VI 0x80000000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK__CI__VI 0x08000000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK__CI__VI 0x01000000L -#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_ACLK_STATUS__ACLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000002L -#define CG_ACLK_STATUS__ACLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK__CI__VI 0x0000007fL -#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK__CI__VI 0x00000080L -#define CG_AM_0_BUSY_CNT__AM_0_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_1_BUSY_CNT__AM_1_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_2_BUSY_CNT__AM_2_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_3_BUSY_CNT__AM_3_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_4_BUSY_CNT__AM_4_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_5_BUSY_CNT__AM_5_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_6_BUSY_CNT__AM_6_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_7_BUSY_CNT__AM_7_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define CG_AM_CNTL__START_BUSY_CNT_MASK__CI__VI 0x00000001L -#define CG_AM_CNTL__START_SCLK_CNT_MASK__CI__VI 0x00000002L -#define CG_AM_SATURATION_LIMIT__AM_SATURATION_LIMIT_MASK__CI__VI 0xffffffffL -#define CG_AM_SCLK_CNT__AM_SCLK_CNT_MASK__CI__VI 0xffffffffL -#define CG_AZ_REQ_AND_RSP__CG_CLIENT_REQ_MASK 0x000000ffL -#define CG_AZ_REQ_AND_RSP__CG_CLIENT_RESP_MASK 0x0000ff00L -#define CG_AZ_REQ_AND_RSP__CLIENT_CG_REQ_MASK 0x00ff0000L -#define CG_AZ_REQ_AND_RSP__CLIENT_CG_RESP_MASK 0xff000000L -#define CG_AZ_STATUS__BUSY_MASK__CI__VI 0x00000001L -#define CG_BIF_REQ_AND_RSP__CG_CLIENT_REQ_MASK__CI__VI 0x000000ffL -#define CG_BIF_REQ_AND_RSP__CG_CLIENT_RESP_MASK__CI__VI 0x0000ff00L -#define CG_BIF_REQ_AND_RSP__CLIENT_CG_REQ_MASK 0x00ff0000L -#define CG_BIF_REQ_AND_RSP__CLIENT_CG_RESP_MASK 0xff000000L -#define CG_BUSY_SAMPLING_PARAMETERS__BUSY_SAMPLING_PERIOD_MASK__SI 0x0000ffffL -#define CG_BUSY_SAMPLING_PARAMETERS__BUSY_SAMPLING_UNIT_MASK__SI 0x000f0000L -#define CG_CAC_CTRL_2__CAC_ENABLE_MASK__CI 0x00000001L -#define CG_CAC_CTRL__CAC_ENABLE_MASK__SI 0x00000100L -#define CG_CAC_CTRL__CAC_WINDOW_MASK__CI 0x00ffffffL -#define CG_CAC_CTRL__CAC_WINDOW_MASK__SI 0x000000ffL -#define CG_CAC_CTRL__OCP_CAC_WINDOW_MASK__SI 0x001ffe00L -#define CG_CAC_CTRL__OCP_OUT_SEL_MASK__CI 0x80000000L -#define CG_CAC_CTRL__OCP_OUT_SEL_MASK__SI 0x02000000L -#define CG_CAC_CTRL__OCP_SAMPLE_WINDOW_SIZE_MASK__CI 0x78000000L -#define CG_CAC_CTRL__OCP_SAMPLE_WINDOW_SIZE_MASK__SI 0x01e00000L -#define CG_CGLS_TILE_0__OVERRIDE_MASK__SI 0xffffffffL -#define CG_CGTT_LOCAL_0__OVERRIDE_MASK__SI 0xffffffffL -#define CG_CGTT_LOCAL_1__OVERRIDE_MASK__SI 0xffffffffL -#define CG_CGTT_OVERRIDE_0__CG_ROM_cgtt_sclk_override_MASK__CI__VI 0x00000020L -#define CG_CGTT_OVERRIDE_0__CG_SMU_cgtt_refclk_override_MASK__CI__VI 0x00000004L -#define CG_CGTT_OVERRIDE_0__CG_SMU_cgtt_sclk_override_MASK__CI__VI 0x00000001L -#define CG_CHRONO_31_0__CG_CHRONO_31_0_MASK 0xffffffffL -#define CG_CHRONO_63_32__CG_CHRONO_63_32_MASK 0xffffffffL -#define CG_CLIENT_HS_CNTL__RESERVED_MASK__CI__VI 0xfffffffcL -#define CG_CLIENT_HS_CNTL__SKIP_DC_HS_MASK__CI__VI 0x00000002L -#define CG_CLIENT_HS_CNTL__SKIP_VCE_HS_MASK__CI__VI 0x00000001L -#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK__CI__VI 0xff000000L -#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK__CI__VI 0x00c00000L -#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK__CI__VI 0x00000001L -#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK__CI__VI 0x00000008L -#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK__CI__VI 0x00000100L -#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK__CI__VI 0x00200000L -#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK__CI__VI 0x00100000L -#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK__CI__VI 0x00080000L -#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK__CI__VI 0x00040000L -#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK__CI__VI 0x00020000L -#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK__CI__VI 0x00010000L -#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK__CI__VI 0x00008000L -#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK__CI__VI 0x00004000L -#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK__CI__VI 0x00000004L -#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK__SI 0x00002000L -#define CG_CLKPIN_CNTL__CLK_SPARE_MASK__SI 0xff000000L -#define CG_CLKPIN_CNTL__CML_CTRL_MASK__SI 0x00c00000L -#define CG_CLKPIN_CNTL__ENABLE_XCLK_MASK__SI 0x00000001L -#define CG_CLKPIN_CNTL__MUX_TCLK_TO_XCLK_MASK__SI 0x00000100L -#define CG_CLKPIN_CNTL__WRITE_DISABLE_MASK__CI__VI 0x00000001L -#define CG_CLKPIN_CNTL__XO_IN2_BIDIR_CML_OE_MASK__SI 0x00200000L -#define CG_CLKPIN_CNTL__XO_IN2_CML_RXEN_MASK__SI 0x00100000L -#define CG_CLKPIN_CNTL__XO_IN2_ICORE_CLK_OE_MASK__SI 0x00080000L -#define CG_CLKPIN_CNTL__XO_IN2_OSCIN_EN_MASK__SI 0x00040000L -#define CG_CLKPIN_CNTL__XO_IN_BIDIR_CML_OE_MASK__SI 0x00020000L -#define CG_CLKPIN_CNTL__XO_IN_CML_RXEN_MASK__SI 0x00010000L -#define CG_CLKPIN_CNTL__XO_IN_ICORE_CLK_OE_MASK__SI 0x00008000L -#define CG_CLKPIN_CNTL__XO_IN_OSCIN_EN_MASK__SI 0x00004000L -#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK__CI__VI 0x00000002L -#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK__SI 0x00000200L -#define CG_CLK_DIVIDER_STATUS_0__DCLK_DIVIDER_STATUS_MASK__CI__VI 0x007f0000L -#define CG_CLK_DIVIDER_STATUS_0__LCLK_DIVIDER_STATUS_MASK__CI__VI 0x0000007fL -#define CG_CLK_DIVIDER_STATUS_0__SCLK_DIVIDER_STATUS_MASK__CI__VI 0x00007f00L -#define CG_CLK_DIVIDER_STATUS_0__VCLK_DIVIDER_STATUS_MASK__CI__VI 0x7f000000L -#define CG_CLK_DIVIDER_STATUS_1__ACLK_DIVIDER_STATUS_MASK__CI__VI 0x00007f00L -#define CG_CLK_DIVIDER_STATUS_1__ECLK_DIVIDER_STATUS_MASK__CI__VI 0x0000007fL -#define CG_CLK_DIVIDER_STATUS_1__EVCLK_DIVIDER_STATUS_MASK__CI__VI 0x1fc00000L -#define CG_CLK_DIVIDER_STATUS_1__SAMCLK_DIVIDER_STATUS_MASK__CI__VI 0x003f8000L -#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000002L -#define CG_DCLK_STATUS__DCLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_DC_REQ_AND_RSP__CG_CLIENT_REQ_MASK__SI 0x000000ffL -#define CG_DC_REQ_AND_RSP__CG_CLIENT_RESP_MASK__SI 0x0000ff00L -#define CG_DC_REQ_AND_RSP__CLIENT_CG_REQ_MASK__SI 0x00ff0000L -#define CG_DC_REQ_AND_RSP__CLIENT_CG_RESP_MASK__SI 0xff000000L -#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK__CI__VI 0xffffffffL -#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK__SI 0x00000003L -#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK__SI 0x03000000L -#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK__SI 0x0000000cL -#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK__SI 0x0c000000L -#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK__CI__VI 0x00000003L -#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK__CI__VI 0x03000000L -#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x0003fff0L -#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000L -#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x00700000L -#define CG_DISPLAY_GAP_COUNTER__VBI_PREDICTION_COUNT_MASK__CI 0xffffffffL -#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_ECLK_OVERCLOCKING_ATTEMPTS__ACLK_ATTEMPTS_MASK__CI__VI 0xffff0000L -#define CG_ECLK_OVERCLOCKING_ATTEMPTS__ECLK_ATTEMPTS_MASK__CI__VI 0x0000ffffL -#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000002L -#define CG_ECLK_STATUS__ECLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_EVCLK_CNTL__EVCLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_EVCLK_CNTL__EVCLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_EVCLK_CNTL__EVCLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_EVCLK_CNTL__EVCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_EVCLK_STATUS__EVCLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000002L -#define CG_EVCLK_STATUS__EVCLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK__SI__CI 0x0000ff00L -#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK__SI__CI 0x007e0000L -#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK__SI__CI 0x00010000L -#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK__SI__CI 0x00800000L -#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK__SI__CI 0xff000000L -#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK__SI__CI 0x000000ffL -#define CG_FDO_CTRL1__FDO_PWRDNB_MASK__SI__CI 0x40000000L -#define CG_FDO_CTRL1__FMAX_DUTY100_MASK__SI__CI 0x000000ffL -#define CG_FDO_CTRL1__FMIN_DUTY_MASK__SI__CI 0x0000ff00L -#define CG_FDO_CTRL1__M_MASK__SI__CI 0x00ff0000L -#define CG_FDO_CTRL1__RESERVED_MASK__SI__CI 0x3f000000L -#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK__SI__CI 0x00000700L -#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK__SI__CI 0x00003800L -#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK__SI__CI 0xfe000000L -#define CG_FDO_CTRL2__TMAX_MASK__SI__CI 0x01fe0000L -#define CG_FDO_CTRL2__TMIN_HYSTER_MASK__SI__CI 0x0001c000L -#define CG_FDO_CTRL2__TMIN_MASK__SI__CI 0x000000ffL -#define CG_FIR_FILTER_COEFF_TAP_0__DOWN_TREND_COEFFICIENT_0_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_0__UP_TREND_COEFFICIENT_0_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_10__DOWN_TREND_COEFFICIENT_10_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_10__UP_TREND_COEFFICIENT_10_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_11__DOWN_TREND_COEFFICIENT_11_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_11__UP_TREND_COEFFICIENT_11_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_12__DOWN_TREND_COEFFICIENT_12_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_12__UP_TREND_COEFFICIENT_12_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_13__DOWN_TREND_COEFFICIENT_13_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_13__UP_TREND_COEFFICIENT_13_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_14__DOWN_TREND_COEFFICIENT_14_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_14__UP_TREND_COEFFICIENT_14_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_1__DOWN_TREND_COEFFICIENT_1_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_1__UP_TREND_COEFFICIENT_1_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_2__DOWN_TREND_COEFFICIENT_2_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_2__UP_TREND_COEFFICIENT_2_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_3__DOWN_TREND_COEFFICIENT_3_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_3__UP_TREND_COEFFICIENT_3_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_4__DOWN_TREND_COEFFICIENT_4_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_4__UP_TREND_COEFFICIENT_4_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_5__DOWN_TREND_COEFFICIENT_5_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_5__UP_TREND_COEFFICIENT_5_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_6__DOWN_TREND_COEFFICIENT_6_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_6__UP_TREND_COEFFICIENT_6_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_7__DOWN_TREND_COEFFICIENT_7_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_7__UP_TREND_COEFFICIENT_7_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_8__DOWN_TREND_COEFFICIENT_8_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_8__UP_TREND_COEFFICIENT_8_MASK__SI 0x000003ffL -#define CG_FIR_FILTER_COEFF_TAP_9__DOWN_TREND_COEFFICIENT_9_MASK__SI 0x000ffc00L -#define CG_FIR_FILTER_COEFF_TAP_9__UP_TREND_COEFFICIENT_9_MASK__SI 0x000003ffL -#define CG_FPS_CNT__FPS_CNT_MASK__CI 0x000000ffL -#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_FREQ_TRAN_VOTING__BIF_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00000004L -#define CG_FREQ_TRAN_VOTING__BIF_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00000008L -#define CG_FREQ_TRAN_VOTING__DRMDMA_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00400000L -#define CG_FREQ_TRAN_VOTING__DRMDMA_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00800000L -#define CG_FREQ_TRAN_VOTING__DRM_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00001000L -#define CG_FREQ_TRAN_VOTING__DRM_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00002000L -#define CG_FREQ_TRAN_VOTING__GFX_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00000001L -#define CG_FREQ_TRAN_VOTING__GFX_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00000002L -#define CG_FREQ_TRAN_VOTING__HDP_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00000010L -#define CG_FREQ_TRAN_VOTING__HDP_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00000020L -#define CG_FREQ_TRAN_VOTING__IDCT_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00010000L -#define CG_FREQ_TRAN_VOTING__IDCT_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00020000L -#define CG_FREQ_TRAN_VOTING__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00000100L -#define CG_FREQ_TRAN_VOTING__IH_SEM_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00000200L -#define CG_FREQ_TRAN_VOTING__PDMA_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00000400L -#define CG_FREQ_TRAN_VOTING__PDMA_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00000800L -#define CG_FREQ_TRAN_VOTING__ROM_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x00000040L -#define CG_FREQ_TRAN_VOTING__ROM_STATIC_SCREEN_VOTE_EN_MASK__SI 0x00000080L -#define CG_FREQ_TRAN_VOTING__UVD_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x01000000L -#define CG_FREQ_TRAN_VOTING__UVD_STATIC_SCREEN_VOTE_EN_MASK__SI 0x02000000L -#define CG_FREQ_TRAN_VOTING__VCE_FREQ_THROTTLING_VOTE_EN_MASK__SI 0x04000000L -#define CG_FREQ_TRAN_VOTING__VCE_STATIC_SCREEN_VOTE_EN_MASK__SI 0x08000000L -#define CG_GFXCLK_ON_OFF_RAMP__PULSE_HIGH_CNT_MASK__SI 0x000001ffL -#define CG_GFXCLK_ON_OFF_RAMP__STEP_DELAY_CNT_MASK__SI 0x007ffe00L -#define CG_GFXCLK_ON_OFF_RAMP__STEP_UNIT_MASK__SI 0x07800000L -#define CG_GFX_IDLE_THRESHOLDS__CG_GFX_IDLE_CLK_STOP_THRESHOLD_MASK__SI 0x0000ffffL -#define CG_GFX_IDLE_THRESHOLDS__CG_GFX_IDLE_PWR_OFF_THRESHOLD_MASK__SI 0xffff0000L -#define CG_IND_ADDR__CG_IND_ADDR_MASK__SI 0x0000ffffL -#define CG_IND_DATA__CG_IND_DATA_MASK__SI 0xffffffffL -#define CG_INTERRUPT_STATUS__ACTIVITY_TRIGGER_MASK 0x00000004L -#define CG_INTERRUPT_STATUS__ACTIVITY_TRIGGER_MASK_MASK 0x00000100L -#define CG_INTERRUPT_STATUS__CTXSW_TRIGGER_MASK 0x00000002L -#define CG_INTERRUPT_STATUS__CTXSW_TRIGGER_MASK_MASK 0x00000080L -#define CG_INTERRUPT_STATUS__RESERVED_0_MASK__CI__VI 0x00000010L -#define CG_INTERRUPT_STATUS__RESERVED_1_MASK__CI__VI 0x00000400L -#define CG_INTERRUPT_STATUS__SMC_MSG_INT_MASK 0x00001000L -#define CG_INTERRUPT_STATUS__SMC_MSG_MASK_MASK 0x00002000L -#define CG_INTERRUPT_STATUS__SRBM_TRIGGER_MASK_MASK 0x00004000L -#define CG_INTERRUPT_STATUS__STATIC_SCREEN_DETECTION_MASK 0x00000008L -#define CG_INTERRUPT_STATUS__STATIC_SCREEN_DETECTION_MASK_MASK 0x00000200L -#define CG_INTERRUPT_STATUS__THERMAL_TRIGGER_MASK 0x00000001L -#define CG_INTERRUPT_STATUS__THERMAL_TRIGGER_MASK_MASK 0x00000040L -#define CG_LCLK_CNTL__LCLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_LCLK_CNTL__LCLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_LCLK_CNTL__LCLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_LCLK_CNTL__LCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_LCLK_STATUS__LCLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000002L -#define CG_LCLK_STATUS__LCLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_MISC_REG_2__IH_MAX_CREDITS_MASK 0x0000001fL -#define CG_MISC_REG__CLK_OBSRV_SEL1_MASK 0x000000ffL -#define CG_MISC_REG__CLK_OBSRV_SEL2_MASK 0x0000ff00L -#define CG_MISC_REG__CLK_OBSRV_SEL_MODE_MASK__CI__VI 0x08000000L -#define CG_MISC_REG__SYNCHRONIZER_COUNTER_MASK 0xf0000000L -#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK__SI__CI 0x0ff00000L -#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK__SI__CI 0x00000200L -#define CG_MULT_THERMAL_CTRL__TS_CLAMP_MASK__SI 0x00000100L -#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK__SI__CI 0x0000000fL -#define CG_MULT_THERMAL_CTRL__UNUSED_MASK__SI__CI 0x000000f0L -#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK__SI__CI 0x000001ffL -#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK__SI__CI 0x0003fe00L -#define CG_PROG_CNTR_STATUS_REG__CYCLES_CNT_MASK__SI 0x00003fffL -#define CG_PROG_CNTR_STATUS_REG__TIMES_CNT_MASK__SI 0x3fffc000L -#define CG_PROG_CNTR__CNTR_EN_MASK__SI 0x00040000L -#define CG_PROG_CNTR__DPM_STATE_MASK__SI 0x03c00000L -#define CG_PROG_CNTR__PERIOD_CNT_MASK__SI 0x00003fffL -#define CG_PROG_CNTR__STATE_SELECT_MASK__SI 0x00380000L -#define CG_PROG_CNTR__UNIT_CNT_MASK__SI 0x0003c000L -#define CG_SAMCLK_CNTL__SAMCLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_SAMCLK_CNTL__SAMCLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_SAMCLK_CNTL__SAMCLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_SAMCLK_CNTL__SAMCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_SAMCLK_OVERCLOCKING_ATTEMPTS__EVCLK_ATTEMPTS_MASK__CI__VI 0xffff0000L -#define CG_SAMCLK_OVERCLOCKING_ATTEMPTS__SAMCLK_ATTEMPTS_MASK__CI__VI 0x0000ffffL -#define CG_SAMCLK_STATUS__SAMCLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000002L -#define CG_SAMCLK_STATUS__SAMCLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_SCLK_CNTL__SCLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_SCLK_CNTL__SCLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_SCLK_CNTL__SCLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_SCLK_CNTL__SCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_SCLK_LCLK_OVERCLOCKING_ATTEMPTS__LCLK_ATTEMPTS_MASK__CI__VI 0xffff0000L -#define CG_SCLK_LCLK_OVERCLOCKING_ATTEMPTS__SCLK_ATTEMPTS_MASK__CI__VI 0x0000ffffL -#define CG_SCLK_STATUS__SCLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000008L -#define CG_SCLK_STATUS__SCLK_FORCE_STATUS_MASK__CI__VI 0x00000002L -#define CG_SCLK_STATUS__SCLK_OVERCLK_DETECT_MASK__CI__VI 0x00000004L -#define CG_SCLK_STATUS__SCLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_IDLE_AUTOCLEAR_MASK__SI 0x00020000L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_IDLE_CLEAR_MASK__SI 0x00040000L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_IDLE_MASK__SI 0x00010000L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_OCP_AUTOCLEAR_MASK__SI 0x00000002L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_OCP_CLEAR_MASK__SI 0x00000004L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_OCP_MASK__SI 0x00000001L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_AUTOCLEAR_MASK__SI 0x00000200L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK__SI 0x00000400L -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_MASK__SI 0x00000100L -#define CG_SPLL_AUTOSCALE_STATUS__AUTOSCALE_ON_IDLE_ACTIVE_MASK__SI 0x00000004L -#define CG_SPLL_AUTOSCALE_STATUS__AUTOSCALE_ON_OCP_ACTIVE_MASK__SI 0x00000001L -#define CG_SPLL_AUTOSCALE_STATUS__AUTOSCALE_ON_SS_ACTIVE_MASK__SI 0x00000002L -#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x000001ffL -#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x04000000L -#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x02000000L -#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000L -#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKR_UPDATE_MASK__SI__CI 0x20000000L -#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x00800000L -#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x00000800L -#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x01000000L -#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x08000000L -#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000L -#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL -#define CG_SPLL_FUNC_CNTL_4__BG_PDN_MASK__SI__CI 0x00400000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x01000000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x00800000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_REG_BIAS_MASK__SI__CI 0x001c0000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0x0c000000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x02000000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000L -#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x00200000L -#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0x000000c0L -#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x00000100L -#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x00000001L -#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0x0000000cL -#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x00000200L -#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x00000030L -#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x00000002L -#define CG_SPLL_FUNC_CNTL_5__SCLK_DFS_BYPASS_EN_MASK__CI 0x00000400L -#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK__CI__VI 0x000000ffL -#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK__CI__VI 0x0000ff00L -#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x00000008L -#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x00000004L -#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x00000001L -#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK__SI__CI 0x00000002L -#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x03ffffffL -#define CG_SPLL_SPREAD_SPECTRUM__BWADJ_MASK__SI__CI 0x0fff0000L -#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0x0000fff0L -#define CG_SPLL_SPREAD_SPECTRUM__SPARE_MASK__SI__CI 0x0000000cL -#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x00000003L -#define CG_SPLL_STATUS__GPLL_OPWRGOOD_ISO_ENB_MASK__CI__VI 0x00400000L -#define CG_SPLL_STATUS__GPLL_OPWRGOOD_S_MASK__CI__VI 0x00200000L -#define CG_SPLL_STATUS__GPLL_OPWRGOOD_V_MASK__CI__VI 0x00100000L -#define CG_SPLL_STATUS__SPLL_BABYSTEP_DONE_MASK 0x00000008L -#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x00000002L -#define CG_SPLL_STATUS__SPLL_CLKF_ACK_MASK 0x00000100L -#define CG_SPLL_STATUS__SPLL_CLKPB_ACK_MASK 0x00000400L -#define CG_SPLL_STATUS__SPLL_CLKR_ACK_MASK__SI__CI 0x00000200L -#define CG_SPLL_STATUS__SPLL_CTLACK_MASK 0x00000001L -#define CG_SPLL_STATUS__SPLL_INTRESET_MASK 0x00000800L -#define CG_SPLL_STATUS__SPLL_OSPARE_MASK 0x000f0000L -#define CG_SPLL_STATUS__SPLL_STATE_MASK 0x00000070L -#define CG_SPLL_STATUS__SPLL_UNLOCK_MASK 0x00000004L -#define CG_SPLL_STATUS__SPLL_UNLOCK_STICKY_MASK 0x00000080L -#define CG_SPLL_STATUS__SPLL_VCTRLADC_MASK 0x0000f000L -#define CG_SPMICLK_CNTL__SPMICLK_DIVIDER_EN_MASK__CI__VI 0x00000008L -#define CG_SPMICLK_CNTL__SPMICLK_DIVIDER_MASK__CI__VI 0x00000007L -#define CG_STATIC_SCREEN_CTRL__ACP_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000080L -#define CG_STATIC_SCREEN_CTRL__AVP_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00002000L -#define CG_STATIC_SCREEN_CTRL__BIF_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_STATIC_SCREEN_CTRL__DC_AZ_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000800L -#define CG_STATIC_SCREEN_CTRL__DRM_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_STATIC_SCREEN_CTRL__GRBM_0_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00004000L -#define CG_STATIC_SCREEN_CTRL__GRBM_10_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x01000000L -#define CG_STATIC_SCREEN_CTRL__GRBM_11_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x02000000L -#define CG_STATIC_SCREEN_CTRL__GRBM_12_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x04000000L -#define CG_STATIC_SCREEN_CTRL__GRBM_13_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x08000000L -#define CG_STATIC_SCREEN_CTRL__GRBM_14_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x10000000L -#define CG_STATIC_SCREEN_CTRL__GRBM_15_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x20000000L -#define CG_STATIC_SCREEN_CTRL__GRBM_1_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00008000L -#define CG_STATIC_SCREEN_CTRL__GRBM_2_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00010000L -#define CG_STATIC_SCREEN_CTRL__GRBM_3_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00020000L -#define CG_STATIC_SCREEN_CTRL__GRBM_4_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00040000L -#define CG_STATIC_SCREEN_CTRL__GRBM_5_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00080000L -#define CG_STATIC_SCREEN_CTRL__GRBM_6_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00100000L -#define CG_STATIC_SCREEN_CTRL__GRBM_7_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00200000L -#define CG_STATIC_SCREEN_CTRL__GRBM_8_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00400000L -#define CG_STATIC_SCREEN_CTRL__GRBM_9_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00800000L -#define CG_STATIC_SCREEN_CTRL__HDP_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_STATIC_SCREEN_CTRL__IDCT_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000040L -#define CG_STATIC_SCREEN_CTRL__IH_SEM_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_STATIC_SCREEN_CTRL__PDMA_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_STATIC_SCREEN_CTRL__RLC_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x40000000L -#define CG_STATIC_SCREEN_CTRL__ROM_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_STATIC_SCREEN_CTRL__SAM_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00001000L -#define CG_STATIC_SCREEN_CTRL__SDMA_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000100L -#define CG_STATIC_SCREEN_CTRL__UVD_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000200L -#define CG_STATIC_SCREEN_CTRL__VCE_STATIC_SCREEN_VOTE_EN_MASK__CI__VI 0x00000400L -#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0x0000ffffL -#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0x000f0000L -#define CG_SW_INT_CTXID__CTXID_MASK__SI 0x0fffffffL -#define CG_SW_INT__ID_MASK__SI 0x000000ffL -#define CG_SW_INT__VALID_MASK__SI 0x00000100L -#define CG_TACH_CTRL__EDGE_PER_REV_MASK__SI__CI 0x00000007L -#define CG_TACH_CTRL__TARGET_PERIOD_MASK__SI__CI 0xfffffff8L -#define CG_TACH_STATUS__TACH_PERIOD_MASK__SI__CI 0xffffffffL -#define CG_TARG_REF_CLK_CNTL__TARG_REF_CLK_DIVIDER_EN_MASK__CI__VI 0x00000008L -#define CG_TARG_REF_CLK_CNTL__TARG_REF_CLK_DIVIDER_MASK__CI__VI 0x00000007L -#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK__SI__CI 0x04000000L -#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK__SI__CI 0x02000000L -#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK__SI__CI 0x003fc000L -#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK__SI__CI 0x00000007L -#define CG_THERMAL_CTRL__RESERVED_MASK__SI__CI 0x01c00000L -#define CG_THERMAL_CTRL__SPARE_MASK__SI__CI 0x00003ff0L -#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK__SI__CI 0x00000008L -#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK__CI__VI 0x000000ffL -#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK__CI__VI 0x0000ff00L -#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK__CI__VI 0x00ff0000L -#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK__CI__VI 0x10000000L -#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK__CI__VI 0x01000000L -#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK__CI__VI 0x02000000L -#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK__CI__VI 0x08000000L -#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK__CI__VI 0x04000000L -#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK__CI__VI 0x00000008L -#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK__CI__VI 0x00000001L -#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK__CI__VI 0x00000010L -#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK__CI__VI 0x00000002L -#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK__CI__VI 0x00000020L -#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK__CI__VI 0x00000004L -#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK__CI__VI 0x00000001L -#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK__CI__VI 0x00000002L -#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK__CI__VI 0x00000008L -#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK__CI__VI 0x00000004L -#define CG_THERMAL_INT__CTF_DELAY_MASK__SI 0x30000000L -#define CG_THERMAL_INT__DIG_THERM_CTF_MASK__SI__CI 0x000000ffL -#define CG_THERMAL_INT__DIG_THERM_INTH_MASK__SI__CI 0x0000ff00L -#define CG_THERMAL_INT__DIG_THERM_INTL_MASK__SI__CI 0x00ff0000L -#define CG_THERMAL_INT__THERM_INT_MASK_MASK__SI__CI 0x0f000000L -#define CG_THERMAL_RANGE__ASIC_T_MAX_MASK__SI__CI 0x000001ffL -#define CG_THERMAL_RANGE__ASIC_T_MIN_MASK__SI__CI 0x01ff0000L -#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK__SI__CI 0x0001fe00L -#define CG_THERMAL_STATUS__GEN_STATUS_MASK__SI__CI 0x003c0000L -#define CG_THERMAL_STATUS__SPARE_MASK__SI__CI 0x000001ffL -#define CG_THERMAL_STATUS__THERM_ALERT_MASK__SI__CI 0x00020000L -#define CG_TIMESTAMP_HIGH__CG_HIGH_MASK__SI 0xffffffffL -#define CG_TIMESTAMP_LOW__CG_LOW_MASK__SI 0xffffffffL -#define CG_ULV_CONTROL__BIF_ULV_VOTE_EN_MASK__SI 0x00000020L -#define CG_ULV_CONTROL__DRMDMA_ULV_VOTE_EN_MASK__SI 0x00001000L -#define CG_ULV_CONTROL__DRM_ULV_VOTE_EN_MASK__SI 0x00000400L -#define CG_ULV_CONTROL__FORCE_ULV_INTERRUPT_MASK 0x40000000L -#define CG_ULV_CONTROL__GFXCLK_GATING_STATUS_MASK__CI__VI 0x00400000L -#define CG_ULV_CONTROL__GFXCLK_RECHK_WAIT_MASK__CI__VI 0x1f000000L -#define CG_ULV_CONTROL__GFX_ULV_VOTE_EN_MASK__SI 0x00000010L -#define CG_ULV_CONTROL__HDP_ULV_VOTE_EN_MASK__SI 0x00000040L -#define CG_ULV_CONTROL__HW_ULV_DETECT_MASK 0x00800000L -#define CG_ULV_CONTROL__IDCT_ULV_VOTE_EN_MASK__SI 0x00000800L -#define CG_ULV_CONTROL__IH_SEM_ULV_VOTE_EN_MASK__SI 0x00000100L -#define CG_ULV_CONTROL__INHIBIT_GFXCLK_STATUS_MASK__CI__VI 0x00200000L -#define CG_ULV_CONTROL__PDMA_ULV_VOTE_EN_MASK__SI 0x00000200L -#define CG_ULV_CONTROL__ROM_ULV_VOTE_EN_MASK__SI 0x00000080L -#define CG_ULV_CONTROL__SMC_ULV_STATE_MASK 0x80000000L -#define CG_ULV_CONTROL__ULV_EN_MASK 0x00000001L -#define CG_ULV_CONTROL__UVD_ULV_VOTE_EN_MASK__SI 0x00002000L -#define CG_ULV_CONTROL__VCE_ULV_VOTE_EN_MASK__SI 0x00004000L -#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0x0000ffffL -#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0x000f0000L -#define CG_ULV_VOTING__ACP_ULV_VOTE_EN_MASK__CI 0x00000080L -#define CG_ULV_VOTING__AVP_ULV_VOTE_EN_MASK__CI 0x00002000L -#define CG_ULV_VOTING__BIF_ULV_VOTE_EN_MASK__CI__VI 0x00000001L -#define CG_ULV_VOTING__DC_AZ_ULV_VOTE_EN_MASK__CI 0x00000800L -#define CG_ULV_VOTING__DRM_ULV_VOTE_EN_MASK__CI__VI 0x00000020L -#define CG_ULV_VOTING__GRBM_0_ULV_VOTE_EN_MASK__CI 0x00004000L -#define CG_ULV_VOTING__GRBM_10_ULV_VOTE_EN_MASK__CI 0x01000000L -#define CG_ULV_VOTING__GRBM_11_ULV_VOTE_EN_MASK__CI 0x02000000L -#define CG_ULV_VOTING__GRBM_12_ULV_VOTE_EN_MASK__CI 0x04000000L -#define CG_ULV_VOTING__GRBM_13_ULV_VOTE_EN_MASK__CI 0x08000000L -#define CG_ULV_VOTING__GRBM_14_ULV_VOTE_EN_MASK__CI 0x10000000L -#define CG_ULV_VOTING__GRBM_15_ULV_VOTE_EN_MASK__CI 0x20000000L -#define CG_ULV_VOTING__GRBM_1_ULV_VOTE_EN_MASK__CI 0x00008000L -#define CG_ULV_VOTING__GRBM_2_ULV_VOTE_EN_MASK__CI 0x00010000L -#define CG_ULV_VOTING__GRBM_3_ULV_VOTE_EN_MASK__CI 0x00020000L -#define CG_ULV_VOTING__GRBM_4_ULV_VOTE_EN_MASK__CI 0x00040000L -#define CG_ULV_VOTING__GRBM_5_ULV_VOTE_EN_MASK__CI 0x00080000L -#define CG_ULV_VOTING__GRBM_6_ULV_VOTE_EN_MASK__CI 0x00100000L -#define CG_ULV_VOTING__GRBM_7_ULV_VOTE_EN_MASK__CI 0x00200000L -#define CG_ULV_VOTING__GRBM_8_ULV_VOTE_EN_MASK__CI 0x00400000L -#define CG_ULV_VOTING__GRBM_9_ULV_VOTE_EN_MASK__CI 0x00800000L -#define CG_ULV_VOTING__HDP_ULV_VOTE_EN_MASK__CI__VI 0x00000002L -#define CG_ULV_VOTING__IDCT_ULV_VOTE_EN_MASK__CI 0x00000040L -#define CG_ULV_VOTING__IH_SEM_ULV_VOTE_EN_MASK__CI__VI 0x00000008L -#define CG_ULV_VOTING__PDMA_ULV_VOTE_EN_MASK__CI__VI 0x00000010L -#define CG_ULV_VOTING__RLC_ULV_VOTE_EN_MASK__CI 0x40000000L -#define CG_ULV_VOTING__ROM_ULV_VOTE_EN_MASK__CI__VI 0x00000004L -#define CG_ULV_VOTING__SAM_ULV_VOTE_EN_MASK__CI 0x00001000L -#define CG_ULV_VOTING__SDMA_ULV_VOTE_EN_MASK__CI 0x00000100L -#define CG_ULV_VOTING__UVD_ULV_VOTE_EN_MASK__CI 0x00000200L -#define CG_ULV_VOTING__VCE_ULV_VOTE_EN_MASK__CI 0x00000400L -#define CG_UPLL_FUNC_CNTL_2__DCLK_SRC_SEL_MASK__SI 0x3e000000L -#define CG_UPLL_FUNC_CNTL_2__UPLL_ENSAT_MASK__SI 0x00080000L -#define CG_UPLL_FUNC_CNTL_2__UPLL_FASTEN_MASK__SI 0x00040000L -#define CG_UPLL_FUNC_CNTL_2__UPLL_LEGACY_PDIV_MASK__SI 0x00020000L -#define CG_UPLL_FUNC_CNTL_2__UPLL_PDIV_A_MASK__SI 0x0000007fL -#define CG_UPLL_FUNC_CNTL_2__UPLL_PDIV_B_MASK__SI 0x00007f00L -#define CG_UPLL_FUNC_CNTL_2__UPLL_TEST_MASK__SI 0x40000000L -#define CG_UPLL_FUNC_CNTL_2__UPLL_UNLOCK_CLEAR_MASK__SI 0x80000000L -#define CG_UPLL_FUNC_CNTL_2__VCLK_SRC_SEL_MASK__SI 0x01f00000L -#define CG_UPLL_FUNC_CNTL_3__UPLL_DITHEN_MASK__SI 0x10000000L -#define CG_UPLL_FUNC_CNTL_3__UPLL_FB_DIV_MASK__SI 0x03ffffffL -#define CG_UPLL_FUNC_CNTL_4__BG_PDN_MASK__SI 0x00400000L -#define CG_UPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK__SI 0x00200000L -#define CG_UPLL_FUNC_CNTL_4__UPLL_FBCLK_SEL_MASK__SI 0x01000000L -#define CG_UPLL_FUNC_CNTL_4__UPLL_ILOCK_MASK__SI 0x00800000L -#define CG_UPLL_FUNC_CNTL_4__UPLL_REG_BIAS_MASK__SI 0x001c0000L -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_EN_MASK__SI 0x000000c0L -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_EXT_MASK__SI 0x0c000000L -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_EXT_SEL_MASK__SI 0x00000030L -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_TEST_SEL_MASK__SI 0x00000007L -#define CG_UPLL_FUNC_CNTL_4__UPLL_SPARE_EXT_MASK__SI 0x70000000L -#define CG_UPLL_FUNC_CNTL_4__UPLL_SPARE_MASK__SI 0x0003ff00L -#define CG_UPLL_FUNC_CNTL_4__UPLL_VCTRLADC_EN_MASK__SI 0x02000000L -#define CG_UPLL_FUNC_CNTL_4__UPLL_VTOI_BIAS_CNTL_MASK__SI 0x80000000L -#define CG_UPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK__SI 0x000000c0L -#define CG_UPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK__SI 0x00000100L -#define CG_UPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK__SI 0x00000001L -#define CG_UPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK__SI 0x0000000cL -#define CG_UPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK__SI 0x00000200L -#define CG_UPLL_FUNC_CNTL_5__RESET_TIMER_MASK__SI 0x00000030L -#define CG_UPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK__SI 0x00000002L -#define CG_UPLL_FUNC_CNTL__UPLL_BYPASS_EN_MASK__SI 0x00000004L -#define CG_UPLL_FUNC_CNTL__UPLL_CLKF_UPDATE_MASK__SI 0x00000040L -#define CG_UPLL_FUNC_CNTL__UPLL_CLKR_UPDATE_MASK__SI 0x00000080L -#define CG_UPLL_FUNC_CNTL__UPLL_CTLACK2_MASK__SI 0x80000000L -#define CG_UPLL_FUNC_CNTL__UPLL_CTLACK_MASK__SI 0x40000000L -#define CG_UPLL_FUNC_CNTL__UPLL_CTLREQ_MASK__SI 0x00000008L -#define CG_UPLL_FUNC_CNTL__UPLL_REFCLK_SEL_MASK__SI 0x00000030L -#define CG_UPLL_FUNC_CNTL__UPLL_REF_DIV_MASK__SI 0x003f0000L -#define CG_UPLL_FUNC_CNTL__UPLL_RESET_EN_MASK__SI 0x00000100L -#define CG_UPLL_FUNC_CNTL__UPLL_RESET_MASK__SI 0x00000001L -#define CG_UPLL_FUNC_CNTL__UPLL_SLEEP_MASK__SI 0x00000002L -#define CG_UPLL_FUNC_CNTL__UPLL_VCO_MODE_MASK__SI 0x00000600L -#define CG_UPLL_SPREAD_SPECTRUM_2__CLKV_MASK__SI 0x03ffffffL -#define CG_UPLL_SPREAD_SPECTRUM__BWADJ_MASK__SI 0x0fff0000L -#define CG_UPLL_SPREAD_SPECTRUM__CLKS_MASK__SI 0x0000fff0L -#define CG_UPLL_SPREAD_SPECTRUM__SPARE_MASK__SI 0x0000000cL -#define CG_UPLL_SPREAD_SPECTRUM__SSEN_MASK__SI 0x00000003L -#define CG_UPLL_STATUS__UPLL_CLKF_ACK_MASK__SI 0x00000004L -#define CG_UPLL_STATUS__UPLL_CLKR_ACK_MASK__SI 0x00000008L -#define CG_UPLL_STATUS__UPLL_CTLACK_A_MASK__SI 0x00000001L -#define CG_UPLL_STATUS__UPLL_CTLACK_B_MASK__SI 0x00000002L -#define CG_UPLL_STATUS__UPLL_INTRESET_MASK__SI 0x00001000L -#define CG_UPLL_STATUS__UPLL_OSPARE_MASK__SI 0x00000f00L -#define CG_UPLL_STATUS__UPLL_UNLOCK_MASK__SI 0x00010000L -#define CG_UPLL_STATUS__UPLL_UNLOCK_STICKY_MASK__SI 0x00020000L -#define CG_UPLL_STATUS__UPLL_VCTRLADC_MASK__SI 0x000000f0L -#define CG_VCEPLL_FUNC_CNTL_2__ECCLK_SRC_SEL_MASK__SI 0x3e000000L -#define CG_VCEPLL_FUNC_CNTL_2__EVCLK_SRC_SEL_MASK__SI 0x01f00000L -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_ENSAT_MASK__SI 0x00080000L -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_FASTEN_MASK__SI 0x00040000L -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_LEGACY_PDIV_MASK__SI 0x00020000L -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_A_MASK__SI 0x0000007fL -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_B_MASK__SI 0x00007f00L -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_TEST_MASK__SI 0x40000000L -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_UNLOCK_CLEAR_MASK__SI 0x80000000L -#define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_DITHEN_MASK__SI 0x10000000L -#define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_FB_DIV_MASK__SI 0x03ffffffL -#define CG_VCEPLL_FUNC_CNTL_4__BG_PDN_MASK__SI 0x00400000L -#define CG_VCEPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK__SI 0x00200000L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_FBCLK_SEL_MASK__SI 0x01000000L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_ILOCK_MASK__SI 0x00800000L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_REG_BIAS_MASK__SI 0x001c0000L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EN_MASK__SI 0x000000c0L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT_MASK__SI 0x0c000000L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT_SEL_MASK__SI 0x00000030L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_TEST_SEL_MASK__SI 0x00000007L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE_EXT_MASK__SI 0x70000000L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE_MASK__SI 0x0003ff00L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VCTRLADC_EN_MASK__SI 0x02000000L -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VTOI_BIAS_CNTL_MASK__SI 0x80000000L -#define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK__SI 0x000000c0L -#define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK__SI 0x00000100L -#define CG_VCEPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK__SI 0x00000001L -#define CG_VCEPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK__SI 0x0000000cL -#define CG_VCEPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK__SI 0x00000200L -#define CG_VCEPLL_FUNC_CNTL_5__RESET_TIMER_MASK__SI 0x00000030L -#define CG_VCEPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK__SI 0x00000002L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_BYPASS_EN_MASK__SI 0x00000004L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKF_UPDATE_MASK__SI 0x00000040L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKR_UPDATE_MASK__SI 0x00000080L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK2_MASK__SI 0x80000000L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK_MASK__SI 0x40000000L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLREQ_MASK__SI 0x00000008L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_REFCLK_SEL_MASK__SI 0x00000030L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_REF_DIV_MASK__SI 0x003f0000L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET_EN_MASK__SI 0x00000100L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET_MASK__SI 0x00000001L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_SLEEP_MASK__SI 0x00000002L -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_VCO_MODE_MASK__SI 0x00000600L -#define CG_VCEPLL_SPREAD_SPECTRUM_2__CLKV_MASK__SI 0x03ffffffL -#define CG_VCEPLL_SPREAD_SPECTRUM__BWADJ_MASK__SI 0x0fff0000L -#define CG_VCEPLL_SPREAD_SPECTRUM__CLKS_MASK__SI 0x0000fff0L -#define CG_VCEPLL_SPREAD_SPECTRUM__SPARE_MASK__SI 0x0000000cL -#define CG_VCEPLL_SPREAD_SPECTRUM__SSEN_MASK__SI 0x00000003L -#define CG_VCEPLL_STATUS__VCEPLL_CLKF_ACK_MASK__SI 0x00000004L -#define CG_VCEPLL_STATUS__VCEPLL_CLKR_ACK_MASK__SI 0x00000008L -#define CG_VCEPLL_STATUS__VCEPLL_CTLACK_A_MASK__SI 0x00000001L -#define CG_VCEPLL_STATUS__VCEPLL_CTLACK_B_MASK__SI 0x00000002L -#define CG_VCEPLL_STATUS__VCEPLL_INTRESET_MASK__SI 0x00001000L -#define CG_VCEPLL_STATUS__VCEPLL_OSPARE_MASK__SI 0x00000f00L -#define CG_VCEPLL_STATUS__VCEPLL_UNLOCK_MASK__SI 0x00010000L -#define CG_VCEPLL_STATUS__VCEPLL_UNLOCK_STICKY_MASK__SI 0x00020000L -#define CG_VCEPLL_STATUS__VCEPLL_VCTRLADC_MASK__SI 0x000000f0L -#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK__CI__VI 0x0001fc00L -#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK__CI__VI 0x00000100L -#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK__CI__VI 0x00000200L -#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define CG_VCLK_DCLK_OVERCLOCKING_ATTEMPTS__DCLK_ATTEMPTS_MASK__CI__VI 0xffff0000L -#define CG_VCLK_DCLK_OVERCLOCKING_ATTEMPTS__VCLK_ATTEMPTS_MASK__CI__VI 0x0000ffffL -#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK__CI__VI 0x00000002L -#define CG_VCLK_STATUS__VCLK_STATUS_MASK__CI__VI 0x00000001L -#define CG_WRM_RST_CNTL__CNT_MASK__CI__VI 0x00000fffL -#define CHROMA_BOT_ADDR__UV_BOT_BASE_MASK__SI 0xffffffffL -#define CHROMA_TOP_ADDR__UV_TOP_BASE_MASK__SI 0xffffffffL -#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define CLIENT0_BM__RESERVED_MASK 0xffffffffL -#define CLIENT0_CD0__RESERVED_MASK 0xffffffffL -#define CLIENT0_CD1__RESERVED_MASK 0xffffffffL -#define CLIENT0_CD2__RESERVED_MASK 0xffffffffL -#define CLIENT0_CD3__RESERVED_MASK 0xffffffffL -#define CLIENT0_CK0__RESERVED_MASK 0xffffffffL -#define CLIENT0_CK1__RESERVED_MASK 0xffffffffL -#define CLIENT0_CK2__RESERVED_MASK 0xffffffffL -#define CLIENT0_CK3__RESERVED_MASK 0xffffffffL -#define CLIENT0_K0__RESERVED_MASK 0xffffffffL -#define CLIENT0_K1__RESERVED_MASK 0xffffffffL -#define CLIENT0_K2__RESERVED_MASK 0xffffffffL -#define CLIENT0_K3__RESERVED_MASK 0xffffffffL -#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL -#define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL -#define CLIENT1_BM__RESERVED_MASK 0xffffffffL -#define CLIENT1_CD0__RESERVED_MASK 0xffffffffL -#define CLIENT1_CD1__RESERVED_MASK 0xffffffffL -#define CLIENT1_CD2__RESERVED_MASK 0xffffffffL -#define CLIENT1_CD3__RESERVED_MASK 0xffffffffL -#define CLIENT1_CK0__RESERVED_MASK 0xffffffffL -#define CLIENT1_CK1__RESERVED_MASK 0xffffffffL -#define CLIENT1_CK2__RESERVED_MASK 0xffffffffL -#define CLIENT1_CK3__RESERVED_MASK 0xffffffffL -#define CLIENT1_K0__RESERVED_MASK 0xffffffffL -#define CLIENT1_K1__RESERVED_MASK 0xffffffffL -#define CLIENT1_K2__RESERVED_MASK 0xffffffffL -#define CLIENT1_K3__RESERVED_MASK 0xffffffffL -#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL -#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL -#define CLIENT2_BM__RESERVED_MASK 0xffffffffL -#define CLIENT2_CD0__RESERVED_MASK 0xffffffffL -#define CLIENT2_CD1__RESERVED_MASK 0xffffffffL -#define CLIENT2_CD2__RESERVED_MASK 0xffffffffL -#define CLIENT2_CD3__RESERVED_MASK 0xffffffffL -#define CLIENT2_CK0__RESERVED_MASK 0xffffffffL -#define CLIENT2_CK1__RESERVED_MASK 0xffffffffL -#define CLIENT2_CK2__RESERVED_MASK 0xffffffffL -#define CLIENT2_CK3__RESERVED_MASK 0xffffffffL -#define CLIENT2_K0__RESERVED_MASK 0xffffffffL -#define CLIENT2_K1__RESERVED_MASK 0xffffffffL -#define CLIENT2_K2__RESERVED_MASK 0xffffffffL -#define CLIENT2_K3__RESERVED_MASK 0xffffffffL -#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffffL -#define CLIENT2_STATUS__RESERVED_MASK 0xffffffffL -#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L -#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L -#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L -#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L -#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL -#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L -#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L -#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L -#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L -#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L -#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L -#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L -#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L -#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L -#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L -#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L -#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L -#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L -#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L -#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L -#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL -#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L -#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L -#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L -#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L -#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L -#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L -#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L -#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L -#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L -#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L -#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L -#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L -#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL -#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L -#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L -#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL -#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L -#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK__CI__VI 0x00000001L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK__CI__VI 0x00001000L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK__CI__VI 0x00000004L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK__CI__VI 0x00000800L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK__CI__VI 0x00000002L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK__CI__VI 0x00000200L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK__CI__VI 0x00000020L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK__CI__VI 0x00000040L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK__CI__VI 0x00000080L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK__CI__VI 0x00000100L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK__CI__VI 0x00000018L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK__CI__VI 0x00000400L -#define CLOCK_POWER_CONTROL_5__Nb_Load_Line_Trim_MASK__CI__VI 0x0000001cL -#define CLOCK_POWER_CONTROL_5__Nb_Offset_Trim_MASK__CI__VI 0x00000003L -#define CLOCK_POWER_CONTROL_5__Nb_Psi1_MASK__CI__VI 0x00000020L -#define CLOCK_POWER_CONTROL_5__Nb_Tfn_MASK__CI__VI 0x00000040L -#define CLOCK_POWER_CONTROL_5__RESERVED_MASK__CI__VI 0xffffff80L -#define CMON_REGION_LOWER__CMON_REGION_31_0_MASK__SI__CI 0xffffffffL -#define CMON_REGION_UPPER__CMON_REGION_40_32_MASK__SI__CI 0x000001ffL -#define CMON_REG__ADC_DOUT_MASK__SI 0x3ff00000L -#define CMON_REG__ADC_MAX_MASK__SI 0x000003ffL -#define CMON_REG__ADC_MIN_MASK__SI 0x000ffc00L -#define CM_ARB_READ_CTL__ARB_TYPE_MASK__SI 0x00000001L -#define CM_ARB_READ_CTL__MAX_REQ_MASK__SI 0x00000600L -#define CM_ARB_READ_CTL__PRIORITY_ONE_MASK__SI 0x00000018L -#define CM_ARB_READ_CTL__PRIORITY_THREE_MASK__SI 0x00000180L -#define CM_ARB_READ_CTL__PRIORITY_TWO_MASK__SI 0x00000060L -#define CM_ARB_READ_CTL__PRIORITY_ZERO_MASK__SI 0x00000006L -#define CM_ARB_WRITE_CTL__ARB_TYPE_MASK__SI 0x00000001L -#define CM_ARB_WRITE_CTL__PRIORITY_ONE_MASK__SI 0x00000018L -#define CM_ARB_WRITE_CTL__PRIORITY_TWO_MASK__SI 0x00000060L -#define CM_ARB_WRITE_CTL__PRIORITY_ZERO_MASK__SI 0x00000006L -#define CM_BITPLANE_MODE__CM_BITPLANE_COLSKIP_MASK__SI 0x00000002L -#define CM_BITPLANE_MODE__CM_BITPLANE_MODE_MASK__SI 0x00000001L -#define CM_BLK_STAT__DB_READ_MASK__SI 0xff000000L -#define CM_BLK_STAT__IT_DONE_MASK__SI 0x0000ff00L -#define CM_BLK_STAT__MP_DONE_MASK__SI 0x00ff0000L -#define CM_BLK_STAT__RE_DONE_MASK__SI 0x000000ffL -#define CM_BUF_EMPTY__COLOC_BUF_EMPTY_MASK__SI 0x000f0000L -#define CM_BUF_EMPTY__CURRENT_BUF_EMPTY_MASK__SI 0x000000ffL -#define CM_BUF_EMPTY__TOP_BUF_EMPTY_MASK__SI 0x0000ff00L -#define CM_COLOC_ADR__COLOC_ADR_MASK__SI 0x3fffffc0L -#define CM_COLOC_LOC__COLOC_MB_NR_ONE_MASK__SI 0x0fffc000L -#define CM_COLOC_LOC__COLOC_MB_NR_ZERO_MASK__SI 0x00003fffL -#define CM_COLOC_SCAN_INFO__CURRENT_MB_NR_MASK__SI 0x3fff0000L -#define CM_COLOC_SCAN_INFO__MB_X_MASK__SI 0x000000ffL -#define CM_COLOC_SCAN_INFO__MB_Y_MASK__SI 0x0000ff00L -#define CM_COLOC_STAT__COLOC_STAT_MASK__SI 0x00003fffL -#define CM_CTL__CTXT_FMT_MASK__SI 0x000000c0L -#define CM_CTL__MEM_TIMEOUT_TIME_MASK__SI 0x0ff00000L -#define CM_CTL__NSG_MODE_MASK__SI 0x00000030L -#define CM_CTL__STANDARD_MASK__SI 0x0000000fL -#define CM_CTL__STD_VERSION_MASK__SI 0x00000f00L -#define CM_CTL__SW_MRST_MASK__SI 0x40000000L -#define CM_CTL__SW_RRST_MASK__SI 0x20000000L -#define CM_CTL__SW_SRST_MASK__SI 0x80000000L -#define CM_CTXT_ADR__CTXT_ADR_MASK__SI 0x3fffffc0L -#define CM_CTXT_FMO_MBNR__MB_NR_MASK__SI 0x00003fffL -#define CM_CTXT_TOP_FMO__D_OR_B_MASK__SI 0x00008000L -#define CM_CTXT_TOP_FMO__MB_NR_MASK__SI 0x00003fffL -#define CM_CTXT_TOP_PREFETCH__NUM_TOP_PREFETCH_MASK__SI 0x00000007L -#define CM_CURRENT_STAT__CURRENT_NOT_COMMIT_MASK__SI 0x000000ffL -#define CM_CURRENT_STAT__CURRENT_STAT_MASK__SI 0x003fff00L -#define CM_DEBUG_INT_STAT__BITPLANE_ERR_MASK__SI 0x00000200L -#define CM_DEBUG_INT_STAT__BOGUS_ADDRESS_MASK__SI 0x00000010L -#define CM_DEBUG_INT_STAT__BUFNUM_ERR_MASK__SI 0x00000008L -#define CM_DEBUG_INT_STAT__DONE_MASK__SI 0x00000001L -#define CM_DEBUG_INT_STAT__MEM_RD_FIFO_OVERFLOW_MASK__SI 0x00000040L -#define CM_DEBUG_INT_STAT__MEM_RD_FIFO_UNDERFLOW_MASK__SI 0x00000020L -#define CM_DEBUG_INT_STAT__MEM_RD_TIMEOUT_MASK__SI 0x00000002L -#define CM_DEBUG_INT_STAT__MEM_WR_FIFO_OVERFLOW_MASK__SI 0x00000100L -#define CM_DEBUG_INT_STAT__MEM_WR_FIFO_UNDERFLOW_MASK__SI 0x00000080L -#define CM_DEBUG_INT_STAT__MEM_WR_TIMEOUT_MASK__SI 0x00000004L -#define CM_FW_ADR__ADR_MASK__SI 0x00000fffL -#define CM_FW_CTL__ACCESS_MODE_MASK__SI 0x00000001L -#define CM_FW_CTL__AUTO_INC_MASK__SI 0x00000002L -#define CM_FW_LOWER_DAT__DAT_MASK__SI 0xffffffffL -#define CM_FW_UPPER_DAT__DAT_MASK__SI 0xffffffffL -#define CM_HW_DEBUG__DAT_MASK__SI 0xffffffffL -#define CM_INIT_TOP_BUF_NUM__TOP_BUF_NUM_MASK__SI 0x00000007L -#define CM_INT_EN__BITPLANE_ERR_MASK__SI 0x00000200L -#define CM_INT_EN__BOGUS_ADDRESS_MASK__SI 0x00000010L -#define CM_INT_EN__BUFNUM_ERR_MASK__SI 0x00000008L -#define CM_INT_EN__DONE_EN_MASK__SI 0x00000001L -#define CM_INT_EN__MEM_RD_FIFO_OVERFLOW_MASK__SI 0x00000040L -#define CM_INT_EN__MEM_RD_FIFO_UNDERFLOW_MASK__SI 0x00000020L -#define CM_INT_EN__MEM_RD_TIMEOUT_MASK__SI 0x00000002L -#define CM_INT_EN__MEM_WR_FIFO_OVERFLOW_MASK__SI 0x00000100L -#define CM_INT_EN__MEM_WR_FIFO_UNDERFLOW_MASK__SI 0x00000080L -#define CM_INT_EN__MEM_WR_TIMEOUT_MASK__SI 0x00000004L -#define CM_INT_STAT__BITPLANE_ERR_MASK__SI 0x00000200L -#define CM_INT_STAT__BOGUS_ADDRESS_MASK__SI 0x00000010L -#define CM_INT_STAT__BUFNUM_ERR_MASK__SI 0x00000008L -#define CM_INT_STAT__DONE_MASK__SI 0x00000001L -#define CM_INT_STAT__MEM_RD_FIFO_OVERFLOW_MASK__SI 0x00000040L -#define CM_INT_STAT__MEM_RD_FIFO_UNDERFLOW_MASK__SI 0x00000020L -#define CM_INT_STAT__MEM_RD_TIMEOUT_MASK__SI 0x00000002L -#define CM_INT_STAT__MEM_WR_FIFO_OVERFLOW_MASK__SI 0x00000100L -#define CM_INT_STAT__MEM_WR_FIFO_UNDERFLOW_MASK__SI 0x00000080L -#define CM_INT_STAT__MEM_WR_TIMEOUT_MASK__SI 0x00000004L -#define CM_LMA_ADR__ADR_MASK__SI 0x000003ffL -#define CM_LMA_CTL__ACCESS_MODE_MASK__SI 0x00000001L -#define CM_LMA_CTL__AUTO_INC_MASK__SI 0x00000040L -#define CM_LMA_CTL__LMA_DEBUG_MASK__SI 0x00000080L -#define CM_LMA_CTL__MEMORY_SELECT_MASK__SI 0x0000003eL -#define CM_LMA_DAT__DAT_MASK__SI 0xffffffffL -#define CM_QWORD8_BOTTOM__QWORD8_BOTTOM_MASK__SI 0xffffffffL -#define CM_QWORD8_TOP__QWORD8_TOP_MASK__SI 0xffffffffL -#define CM_RELEASE__CURR_BUF_NUM_MASK__SI 0x00000007L -#define CM_SLICE_INFO__COLOC_CFG_MASK__SI 0x0000001eL -#define CM_SLICE_INFO__MBAFF_FRAME_FLAG_MASK__SI 0x00000001L -#define CM_SPS_INFO__PIC_HEIGHT_MASK__SI 0x0000ff00L -#define CM_SPS_INFO__PIC_SIZE_MASK__SI 0x3fff0000L -#define CM_SPS_INFO__PIC_WIDTH_MASK__SI 0x000000ffL -#define CM_SRAM_RM_CTL__CM_M328X064H1M04S00_RME_MASK__SI 0x00000010L -#define CM_SRAM_RM_CTL__CM_M328X064H1M04S00_RM_MASK__SI 0x0000000fL -#define CM_STAT__READING_CTXT_BUSY_MASK__SI 0x00000002L -#define CM_STAT__WRITING_CTXT_BUSY_MASK__SI 0x00000001L -#define CM_TOP_STAT__TOP_STAT_MASK__SI 0x00003fffL -#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK__CI__VI 0x00000010L -#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK__CI__VI 0x00000008L -#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK__CI__VI 0x00000004L -#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK__CI__VI 0x00000003L -#define CNB_PWRMGT_CNTL__SPARE_MASK__CI__VI 0xffffffe0L -#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL -#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL -#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL -#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK__CI__VI 0xffffffffL -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK__CI__VI 0xffffffffL -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK__CI__VI 0xffffffffL -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK__CI__VI 0xffffffffL -#define COLOR_MATRIX_COEF_1_1__COLOR_MATRIX_COEF_1_1_MASK__SI 0x0001ffffL -#define COLOR_MATRIX_COEF_1_1__COLOR_MATRIX_SIGN_1_1_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_1_2__COLOR_MATRIX_COEF_1_2_MASK__SI 0x0000ffffL -#define COLOR_MATRIX_COEF_1_2__COLOR_MATRIX_SIGN_1_2_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_1_3__COLOR_MATRIX_COEF_1_3_MASK__SI 0x0000ffffL -#define COLOR_MATRIX_COEF_1_3__COLOR_MATRIX_SIGN_1_3_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_1_4__COLOR_MATRIX_COEF_1_4_MASK__SI 0x07ffff00L -#define COLOR_MATRIX_COEF_1_4__COLOR_MATRIX_SIGN_1_4_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_2_1__COLOR_MATRIX_COEF_2_1_MASK__SI 0x0000ffffL -#define COLOR_MATRIX_COEF_2_1__COLOR_MATRIX_SIGN_2_1_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_2_2__COLOR_MATRIX_COEF_2_2_MASK__SI 0x0001ffffL -#define COLOR_MATRIX_COEF_2_2__COLOR_MATRIX_SIGN_2_2_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_2_3__COLOR_MATRIX_COEF_2_3_MASK__SI 0x0000ffffL -#define COLOR_MATRIX_COEF_2_3__COLOR_MATRIX_SIGN_2_3_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_2_4__COLOR_MATRIX_COEF_2_4_MASK__SI 0x07ffff00L -#define COLOR_MATRIX_COEF_2_4__COLOR_MATRIX_SIGN_2_4_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_3_1__COLOR_MATRIX_COEF_3_1_MASK__SI 0x0000ffffL -#define COLOR_MATRIX_COEF_3_1__COLOR_MATRIX_SIGN_3_1_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_3_2__COLOR_MATRIX_COEF_3_2_MASK__SI 0x0000ffffL -#define COLOR_MATRIX_COEF_3_2__COLOR_MATRIX_SIGN_3_2_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_3_3__COLOR_MATRIX_COEF_3_3_MASK__SI 0x0001ffffL -#define COLOR_MATRIX_COEF_3_3__COLOR_MATRIX_SIGN_3_3_MASK__SI 0x80000000L -#define COLOR_MATRIX_COEF_3_4__COLOR_MATRIX_COEF_3_4_MASK__SI 0x07ffff00L -#define COLOR_MATRIX_COEF_3_4__COLOR_MATRIX_SIGN_3_4_MASK__SI 0x80000000L -#define COLOR_SPACE_CONVERT__COLOR_SUBSAMPLE_CRCB_MODE_MASK__SI 0x00000003L -#define COMMAND__AD_STEPPING_MASK 0x00000080L -#define COMMAND__BUS_MASTER_EN_MASK 0x00000004L -#define COMMAND__FAST_B2B_EN_MASK 0x00000200L -#define COMMAND__INT_DIS_MASK 0x00000400L -#define COMMAND__IO_ACCESS_EN_MASK 0x00000001L -#define COMMAND__MEM_ACCESS_EN_MASK 0x00000002L -#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x00000010L -#define COMMAND__PAL_SNOOP_EN_MASK 0x00000020L -#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x00000040L -#define COMMAND__SERR_EN_MASK 0x00000100L -#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x00000008L -#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL -#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL -#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L -#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK__CI__VI 0x00001000L -#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK__CI__VI 0x00000380L -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK__CI__VI 0x00000010L -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK__CI__VI 0x00000040L -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L -#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK__CI__VI 0x00004000L -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK__CI__VI 0x00000400L -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK__CI__VI 0x00000020L -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK__CI__VI 0x00000800L -#define COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK__SI 0x00000fffL -#define COMPUTE_MISC_RESERVED__RESERVED2_MASK__CI__VI 0x00000004L -#define COMPUTE_MISC_RESERVED__RESERVED3_MASK__CI__VI 0x00000008L -#define COMPUTE_MISC_RESERVED__RESERVED4_MASK__CI__VI 0x00000010L -#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK__CI__VI 0x00000003L -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK__CI__VI 0x00000001L -#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL -#define COMPUTE_PGM_HI__INST_ATC_MASK__CI__VI 0x00000100L -#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL -#define COMPUTE_PGM_RSRC1__BULKY_MASK__CI__VI 0x01000000L -#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK__CI__VI 0x02000000L -#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L -#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L -#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L -#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L -#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L -#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L -#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L -#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL -#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK__CI__VI 0x00006000L -#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L -#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L -#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L -#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L -#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L -#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK__CI__VI 0x00000001L -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK__CI__VI 0x07000000L -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK__CI__VI 0x00800000L -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK__CI__VI 0x000003ffL -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK__SI 0x0000003fL -#define COMPUTE_RESTART_X__RESTART_MASK__CI__VI 0xffffffffL -#define COMPUTE_RESTART_Y__RESTART_MASK__CI__VI 0xffffffffL -#define COMPUTE_RESTART_Z__RESTART_MASK__CI__VI 0xffffffffL -#define COMPUTE_START_X__START_MASK 0xffffffffL -#define COMPUTE_START_Y__START_MASK 0xffffffffL -#define COMPUTE_START_Z__START_MASK 0xffffffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK__CI__VI 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK__CI__VI 0xffff0000L -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK__CI__VI 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK__CI__VI 0xffff0000L -#define COMPUTE_TBA_HI__DATA_MASK 0x000000ffL -#define COMPUTE_TBA_LO__DATA_MASK 0xffffffffL -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK__CI__VI 0x00000001L -#define COMPUTE_TMA_HI__DATA_MASK 0x000000ffL -#define COMPUTE_TMA_LO__DATA_MASK 0xffffffffL -#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L -#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL -#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL -#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL -#define COMPUTE_VMID__DATA_MASK 0x0000000fL -#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffffL -#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L -#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L -#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L -#define CONFIG_CNTL__VGA_DIS_MASK 0x00000002L -#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffffL -#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffffL -#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000fffffL -#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK__SI 0x00000001L -#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK__SI 0x00000002L -#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK__SI 0xffffff80L -#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK__SI 0x0000007fL -#define CORB_READ_POINTER__CORB_READ_POINTER_MASK__SI 0x000000ffL -#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK__SI 0x00008000L -#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK__SI 0x000000f0L -#define CORB_SIZE__CORB_SIZE_MASK__SI 0x00000003L -#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK__SI 0x00000001L -#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK__SI 0xffffffffL -#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK__SI 0x000000ffL -#define CORE_PERF_BOOST_CONTROL__Apm_Master_En_MASK__CI__VI 0x00000080L -#define CORE_PERF_BOOST_CONTROL__Boost_Lock_MASK__CI__VI 0x80000000L -#define CORE_PERF_BOOST_CONTROL__Boost_Source_MASK__CI__VI 0x00000003L -#define CORE_PERF_BOOST_CONTROL__Num_Boost_States_MASK__CI__VI 0x0000001cL -#define CORE_PERF_BOOST_CONTROL__RESERVED_1_MASK__CI__VI 0x00000060L -#define CORE_PERF_BOOST_CONTROL__RESERVED_MASK__CI__VI 0x0fffff00L -#define CORE_PERF_BOOST_CONTROL__Tdp_Limit_Pstate_MASK__CI__VI 0x70000000L -#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK__CI 0x00000f00L -#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK__CI 0x00010000L -#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK__CI 0x00000f00L -#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK__CI 0x00010000L -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CPC_INT_CNTX_ID__CNTX_ID_MASK__CI 0x0000ffffL -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x0000003fL -#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x0000fc00L -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x0000fc00L -#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x0000003fL -#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x0000fc00L -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x0000fc00L -#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define CPG_CONFIG__CPG_RDREQ_URG_MASK__CI 0x00000f00L -#define CPG_CONFIG__CPG_REQ_TRAN_MASK__CI 0x00010000L -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x0000003fL -#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x0000fc00L -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x0000fc00L -#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define CPU_INT_ARGUMENT__DATA_MASK__CI__VI 0xffffffffL -#define CPU_INT_REQ__INT_TOGGLE_MASK__CI__VI 0x00000001L -#define CPU_INT_REQ__SERVICE_INDEX_MASK__CI__VI 0x0001fffeL -#define CPU_INT_RESPONSE__DATA_MASK__CI__VI 0xffffffffL -#define CPU_INT_STATUS__INT_ACK_MASK__CI__VI 0x00000001L -#define CPU_INT_STATUS__INT_DONE_MASK__CI__VI 0x00000002L -#define CPU_TDP_LIMIT_0__Cmp_Unit_Tdp_Limit_0_MASK__CI__VI 0x00ff0000L -#define CPU_TDP_LIMIT_0__Node_Tdp_Limit_MASK__CI__VI 0x00000fffL -#define CPU_TDP_LIMIT_0__RESERVED_1_MASK__CI__VI 0x0000f000L -#define CPU_TDP_LIMIT_0__RESERVED_MASK__CI__VI 0xff000000L -#define CPU_TDP_LIMIT_1__Cmp_Unit_Tdp_Limit_1_MASK__CI__VI 0x000000ffL -#define CPU_TDP_LIMIT_1__RESERVED_MASK__CI__VI 0xffffff00L -#define CPU_TDP_RUN_AVG__RESERVED_MASK__CI__VI 0xfc000000L -#define CPU_TDP_RUN_AVG__Run_Avg_Range_MASK__CI__VI 0x0000000fL -#define CPU_TDP_RUN_AVG__Tdp_Run_Avg_Acc_Cap_MASK__CI__VI 0x03fffff0L -#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L -#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK__CI__VI 0x00010000L -#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK__SI 0x00030000L -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK__SI 0x000000ffL -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL -#define CP_APPEND_DATA__DATA_MASK 0xffffffffL -#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffffL -#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffffL -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL -#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L -#define CP_BUSY_STAT__CS_CONTEXT_BUSY_MASK__SI 0x00010000L -#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L -#define CP_BUSY_STAT__INDR1_FETCHING_DATA_MASK__SI 0x00000004L -#define CP_BUSY_STAT__INDR2_FETCHING_DATA_MASK__SI 0x00000008L -#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L -#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L -#define CP_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK__SI 0x00000800L -#define CP_BUSY_STAT__PENDING_CMD_BUFFERS_MASK__SI 0x00000020L -#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L -#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L -#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L -#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L -#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L -#define CP_BUSY_STAT__RING_FETCHING_DATA_MASK__SI 0x00000002L -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L -#define CP_BUSY_STAT__STATE_FETCHING_DATA_MASK__SI 0x00000010L -#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L -#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK__CI__VI 0xffffffffL -#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK__CI__VI 0xffffffffL -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK__CI__VI 0xffffffffL -#define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK__CI__VI 0x00000004L -#define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK__CI__VI 0x00000008L -#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK__CI__VI 0x00000001L -#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK__CI__VI 0x00000002L -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK__CI__VI 0x0000ffffL -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK__SI 0x000000ffL -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL -#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK__CI__VI 0x000fffffL -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK__CI__VI 0x0000ffffL -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK__SI 0x000000ffL -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL -#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK__CI__VI 0x000fffffL -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK__CI__VI 0x0000ffffL -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK__SI 0x000000ffL -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL -#define CP_CE_INTR_ROUTINE_START__IR_START_MASK__CI__VI 0x000007ffL -#define CP_CE_PRGRM_CNTR_START__IP_START_MASK__CI__VI 0x000007ffL -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L -#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL -#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL -#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL -#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL -#define CP_CMD_INDEX__CMD_ME_SEL_MASK__CI__VI 0x00003000L -#define CP_CNTL__NOT_USED_MASK__SI 0x00000001L -#define CP_CNTX_STAT__ACTIVE_CS0_CONTEXTS_MASK__SI 0x000000ffL -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK__CI__VI 0x000000ffL -#define CP_CNTX_STAT__APPEND_CNTX_ACTIVE_MASK__SI 0x000ff000L -#define CP_CNTX_STAT__CURRENT_CS0_CONTEXT_MASK__SI 0x00000700L -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK__CI__VI 0x00000700L -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK__CI__VI 0x000000ffL -#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL -#define CP_COHER_CNTL2__VMID_MASK__SI 0x0000000fL -#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L -#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L -#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L -#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L -#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L -#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L -#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L -#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L -#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L -#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L -#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L -#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L -#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L -#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L -#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK__CI__VI 0x10000000L -#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK__CI__VI 0x00008000L -#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L -#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK__CI 0x00010000L -#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK__CI__VI 0x00040000L -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK__CI__VI 0x000000ffL -#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL -#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL -#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL -#define CP_COHER_STATUS__MEID_MASK__CI__VI 0x03000000L -#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000L -#define CP_COHER_STATUS__STATUS_MASK 0x80000000L -#define CP_CONFIG__CP_RDREQ_URG_MASK__SI 0x00000f00L -#define CP_CONFIG__CP_REQ_TRAN_MASK__SI 0x00010000L -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK__CI__VI 0x00000070L -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK__CI__VI 0x00000007L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK__CI__VI 0x00700000L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK__CI__VI 0x00070000L -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK__CI__VI 0x00000100L -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK__CI__VI 0x00000010L -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK__CI__VI 0x00000040L -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK__CI__VI 0x00000020L -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK__CI__VI 0x00000001L -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK__CI__VI 0x00000008L -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK__CI__VI 0x00000004L -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK__CI__VI 0x00000200L -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK__CI__VI 0x00000400L -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK__CI__VI 0x00000800L -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK__CI__VI 0x00001000L -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK__CI__VI 0x00002000L -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK__CI__VI 0x00000002L -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK__CI__VI 0x00000080L -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK__CI__VI 0x01000000L -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK__CI__VI 0x00100000L -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK__CI__VI 0x00400000L -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK__CI__VI 0x00200000L -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK__CI__VI 0x00010000L -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK__CI__VI 0x00080000L -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK__CI__VI 0x00040000L -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK__CI__VI 0x02000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK__CI__VI 0x04000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK__CI__VI 0x08000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK__CI__VI 0x10000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK__CI__VI 0x20000000L -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK__CI__VI 0x00020000L -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK__CI__VI 0x00800000L -#define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK__CI__VI 0x0000007fL -#define CP_CPC_DEBUG_DATA__DEBUG_DATA_MASK__CI__VI 0xffffffffL -#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK__CI__VI 0x20000000L -#define CP_CPC_DEBUG__DEBUG_BUS_SELECT_BITS_MASK__CI__VI 0x0000003fL -#define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK__CI__VI 0x04000000L -#define CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK__CI__VI 0x00400000L -#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK__CI__VI 0x80000000L -#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK__CI__VI 0x02000000L -#define CP_CPC_DEBUG__PRIV_VIOLATION_CNTL_MASK__CI__VI 0x18000000L -#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK__CI__VI 0x01000000L -#define CP_CPC_DEBUG__VMID_VIOLATION_CNTL_MASK__CI__VI 0x00008000L -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK__CI__VI 0x0000003fL -#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK__CI__VI 0x0000000fL -#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK__CI 0x0000001fL -#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK__CI__VI 0x0000ffffL -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK__CI__VI 0xffffffffL -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK__CI 0x000000ffL -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK__CI__VI 0x00000100L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK__CI 0x00000800L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK__CI 0x00001000L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK__CI__VI 0x00000200L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK__CI__VI 0x00000400L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK__CI__VI 0x00002000L -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK__CI__VI 0x00010000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK__CI 0x00080000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK__CI 0x00100000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK__CI__VI 0x00020000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK__CI__VI 0x00040000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK__CI__VI 0x00200000L -#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK__CI 0x00000001L -#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK__CI 0x00000002L -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK__CI__VI 0x00000010L -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK__CI__VI 0x00000008L -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK__CI__VI 0x00000040L -#define CP_CPC_STATUS__CPC_BUSY_MASK__CI__VI 0x80000000L -#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK__CI__VI 0x40000000L -#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK__CI__VI 0x20000000L -#define CP_CPC_STATUS__DC0_BUSY_MASK__CI__VI 0x00000004L -#define CP_CPC_STATUS__DC1_BUSY_MASK__CI__VI 0x00000008L -#define CP_CPC_STATUS__MEC1_BUSY_MASK__CI__VI 0x00000001L -#define CP_CPC_STATUS__MEC2_BUSY_MASK__CI__VI 0x00000002L -#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK__CI 0x00000100L -#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK__CI 0x00000200L -#define CP_CPC_STATUS__QU_BUSY_MASK__CI__VI 0x00001000L -#define CP_CPC_STATUS__RCIU1_BUSY_MASK__CI__VI 0x00000010L -#define CP_CPC_STATUS__RCIU2_BUSY_MASK__CI__VI 0x00000020L -#define CP_CPC_STATUS__ROQ1_BUSY_MASK__CI__VI 0x00000040L -#define CP_CPC_STATUS__ROQ2_BUSY_MASK__CI__VI 0x00000080L -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK__CI__VI 0x00000800L -#define CP_CPC_STATUS__TCIU_BUSY_MASK__CI__VI 0x00000400L -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK__CI__VI 0x00000080L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK__CI__VI 0x00000020L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK__CI__VI 0x00000040L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK__CI__VI 0x00000004L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK__CI__VI 0x00000008L -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK__CI__VI 0x00000100L -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK__CI__VI 0x00000002L -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK__CI__VI 0x00000010L -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK__CI__VI 0x00000800L -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK__CI__VI 0x00400000L -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK__CI__VI 0x00001000L -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK__CI__VI 0x00004000L -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK__CI__VI 0x00200000L -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK__CI__VI 0x00800000L -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK__CI__VI 0x80000000L -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK__CI__VI 0x00080000L -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK__CI__VI 0x00100000L -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK__CI__VI 0x00002000L -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK__CI__VI 0x00020000L -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK__CI__VI 0x40000000L -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK__CI__VI 0x00040000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK__CI__VI 0x01000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK__CI__VI 0x02000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK__CI__VI 0x10000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK__CI__VI 0x04000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK__CI__VI 0x08000000L -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK__CI__VI 0x00010000L -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK__CI__VI 0x00008000L -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK__CI__VI 0x20000000L -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK__CI__VI 0x00000200L -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK__CI__VI 0x00000001L -#define CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK__CI__VI 0x0000007fL -#define CP_CPF_DEBUG_DATA__DEBUG_DATA_MASK__CI__VI 0xffffffffL -#define CP_CPF_DEBUG__DEBUG_BUS_SELECT_BITS_MASK__CI__VI 0x0000003fL -#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK__CI__VI 0x02000000L -#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK__CI__VI 0x01000000L -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK__CI__VI 0x00000002L -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK__CI__VI 0x00000004L -#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK__CI 0x00000010L -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK__CI__VI 0x00000001L -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK__CI__VI 0x00000008L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK__CI__VI 0x00000020L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK__CI__VI 0x00000040L -#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK__CI__VI 0x40000000L -#define CP_CPF_STATUS__CPF_BUSY_MASK__CI__VI 0x80000000L -#define CP_CPF_STATUS__CSF_BUSY_MASK__CI__VI 0x00000002L -#define CP_CPF_STATUS__HQD_BUSY_MASK__CI__VI 0x00008000L -#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK__CI__VI 0x00002000L -#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK__CI 0x00000004L -#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK__CI 0x00000008L -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK__CI__VI 0x00000001L -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK__CI__VI 0x00000010L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK__CI__VI 0x00000400L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK__CI__VI 0x00000800L -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK__CI__VI 0x00000200L -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK__CI__VI 0x00000040L -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK__CI__VI 0x00000080L -#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK__CI__VI 0x00000020L -#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK__CI__VI 0x00000100L -#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK__CI__VI 0x00001000L -#define CP_CPF_STATUS__TCIU_BUSY_MASK__CI__VI 0x00004000L -#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0x0000000fL -#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0x0000000fL -#define CP_DEBUG_CNTL__CP_DEBUG_INDX_MASK__SI 0x0000007fL -#define CP_DEBUG_CNTL__DEBUG_INDX_MASK__CI__VI 0x0000007fL -#define CP_DEBUG_DATA__DATA_MASK__SI 0xffffffffL -#define CP_DEBUG_DATA__DEBUG_DATA_MASK__CI__VI 0xffffffffL -#define CP_DEBUG__BUSY_EXTENDER_MASK__CI__VI 0x00180000L -#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK__CI__VI 0x40000000L -#define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK__CI__VI 0x20000000L -#define CP_DEBUG__DEBUG_BUS_FLOP_EN_MASK__CI__VI 0x00000040L -#define CP_DEBUG__DEBUG_BUS_SELECT_BITS_MASK 0x0000003fL -#define CP_DEBUG__EVENT_FILT_DISABLE_MASK__CI__VI 0x04000000L -#define CP_DEBUG__INTERRUPT_DISABLE_MASK__CI__VI 0x00400000L -#define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L -#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L -#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK__SI 0x04000000L -#define CP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x18000000L -#define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK 0x00070000L -#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L -#define CP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00008000L -#define CP_DEVICE_ID__DEVICE_ID_MASK__CI__VI 0x000000ffL -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK__CI__VI 0xffffffffL -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK__CI__VI 0xffffffffL -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK__CI__VI 0xffffffffL -#define CP_DFY_ADDR_HI__ADDR_HI_MASK__CI__VI 0xffffffffL -#define CP_DFY_ADDR_LO__ADDR_LO_MASK__CI__VI 0xffffffe0L -#define CP_DFY_CNTL__ATC_MASK__CI 0x00000800L -#define CP_DFY_CNTL__POLICY_MASK__CI 0x00000300L -#define CP_DFY_CNTL__VOL_MASK__CI 0x00000400L -#define CP_DFY_DATA_0__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_10__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_11__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_12__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_13__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_14__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_15__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_1__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_2__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_3__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_4__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_5__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_6__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_7__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_8__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_DATA_9__DATA_MASK__CI__VI 0xffffffffL -#define CP_DFY_STAT__BURST_COUNT_MASK__CI__VI 0x0000ffffL -#define CP_DFY_STAT__BUSY_MASK__CI__VI 0x80000000L -#define CP_DFY_STAT__TAGS_PENDING_MASK__CI 0x00ff0000L -#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L -#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L -#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L -#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L -#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L -#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x001fffffL -#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x00200000L -#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x03000000L -#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0x00c00000L -#define CP_DMA_ME_CONTROL__DST_ATC_MASK__CI__VI 0x01000000L -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK__CI 0x06000000L -#define CP_DMA_ME_CONTROL__DST_SELECT_MASK__CI__VI 0x00300000L -#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK__CI 0x08000000L -#define CP_DMA_ME_CONTROL__SRC_ATC_MASK__CI__VI 0x00001000L -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK__CI 0x00006000L -#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK__CI__VI 0x60000000L -#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK__CI 0x00008000L -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK__SI 0x000000ffL -#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL -#define CP_DMA_ME_SRC_ADDR_HI__DST_SELECT_MASK__SI 0x00300000L -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK__SI 0x000000ffL -#define CP_DMA_ME_SRC_ADDR_HI__SRC_SELECT_MASK__SI 0x60000000L -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL -#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x001fffffL -#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x00200000L -#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x03000000L -#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0x00c00000L -#define CP_DMA_PFP_CONTROL__DST_ATC_MASK__CI__VI 0x01000000L -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK__CI 0x06000000L -#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK__CI__VI 0x00300000L -#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK__CI 0x08000000L -#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK__CI__VI 0x00001000L -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK__CI 0x00006000L -#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK__CI__VI 0x60000000L -#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK__CI 0x00008000L -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK__SI 0x000000ffL -#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL -#define CP_DMA_PFP_SRC_ADDR_HI__DST_SELECT_MASK__SI 0x00300000L -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK__SI 0x000000ffL -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_SELECT_MASK__SI 0x60000000L -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL -#define CP_DMA_PIO_COMMAND__BYTE_COUNT_MASK 0x001fffffL -#define CP_DMA_PIO_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_PIO_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_PIO_COMMAND__DIS_WC_MASK 0x00200000L -#define CP_DMA_PIO_COMMAND__DST_SWAP_MASK 0x03000000L -#define CP_DMA_PIO_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_PIO_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_PIO_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_PIO_COMMAND__SRC_SWAP_MASK 0x00c00000L -#define CP_DMA_PIO_CONTROL__DST_ATC_MASK__CI__VI 0x01000000L -#define CP_DMA_PIO_CONTROL__DST_CACHE_POLICY_MASK__CI 0x06000000L -#define CP_DMA_PIO_CONTROL__DST_SELECT_MASK__CI__VI 0x00300000L -#define CP_DMA_PIO_CONTROL__DST_VOLATILE_MASK__CI 0x08000000L -#define CP_DMA_PIO_CONTROL__SRC_ATC_MASK__CI__VI 0x00001000L -#define CP_DMA_PIO_CONTROL__SRC_CACHE_POLICY_MASK__CI 0x00006000L -#define CP_DMA_PIO_CONTROL__SRC_SELECT_MASK__CI__VI 0x60000000L -#define CP_DMA_PIO_CONTROL__SRC_VOLATILE_MASK__CI 0x00008000L -#define CP_DMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_DMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK__SI 0x000000ffL -#define CP_DMA_PIO_DST_ADDR__DST_ADDR_MASK 0xffffffffL -#define CP_DMA_PIO_SRC_ADDR_HI__DST_SELECT_MASK__SI 0x00300000L -#define CP_DMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_DMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK__SI 0x000000ffL -#define CP_DMA_PIO_SRC_ADDR_HI__SRC_SELECT_MASK__SI 0x60000000L -#define CP_DMA_PIO_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL -#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L -#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK__SI__CI 0x00000003L -#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK__SI__CI 0x000000f0L -#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK__SI__CI 0x00003c00L -#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK__SI__CI 0x000f0000L -#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK__SI__CI 0x00000003L -#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK__SI__CI 0x000000f0L -#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK__SI__CI 0x00003c00L -#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK__SI__CI 0x000f0000L -#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK__SI__CI 0x00000003L -#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK__SI__CI 0x000000f0L -#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK__SI__CI 0x00003c00L -#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK__SI__CI 0x000f0000L -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L -#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK__SI__CI 0x000000f0L -#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK__SI__CI 0x00003c00L -#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L -#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK__CI__VI 0x00000003L -#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_EOP_DONE_ADDR_HI__EOP_DONE_ADDR_HI_MASK__SI 0x000000ffL -#define CP_EOP_DONE_ADDR_HI__EOP_DONE_DATA_SEL_MASK__SI 0xe0000000L -#define CP_EOP_DONE_ADDR_HI__EOP_DONE_INT_SEL_MASK__SI 0x03000000L -#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK__CI__VI 0xfffffffcL -#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK__CI 0x00000003L -#define CP_EOP_DONE_ADDR_LO__EOP_DONE_ADDR_LO_MASK__SI 0xfffffffcL -#define CP_EOP_DONE_ADDR_LO__EOP_DONE_ADDR_SWAP_MASK__SI 0x00000003L -#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK__CI__VI 0x0000ffffL -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK__CI__VI 0xe0000000L -#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK__CI__VI 0x00030000L -#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK__CI__VI 0x07000000L -#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK__CI__VI 0xffffffffL -#define CP_EOP_DONE_DATA_HI__EOP_DONE_DATA_HI_MASK__SI 0xffffffffL -#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK__CI__VI 0xffffffffL -#define CP_EOP_DONE_DATA_LO__EOP_DONE_DATA_LO_MASK__SI 0xffffffffL -#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK__CI 0x06000000L -#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK__CI 0x08000000L -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK__CI__VI 0x0003f000L -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK__CI__VI 0x0000007fL -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL -#define CP_FETCHER_SOURCE__ME_SRC_MASK__CI 0x00000001L -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L -#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L -#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK__CI 0x000000ffL -#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK__CI 0xffffffffL -#define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_HPD_EOP_CONTROL__EOP_ATC_MASK__CI 0x00800000L -#define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK__CI 0x0000003fL -#define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK__CI 0x04000000L -#define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK__CI 0x70000000L -#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK__CI 0x80000000L -#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK__CI 0x00002000L -#define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK__CI 0x00000100L -#define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK__CI 0x00000e00L -#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK__CI 0x00004000L -#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK__CI 0x00001000L -#define CP_HPD_EOP_VMID__VMID_MASK__CI 0x0000000fL -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK__CI__VI 0x003f0000L -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK__CI__VI 0x00000007L -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK__CI__VI 0x00003f00L -#define CP_HQD_ACTIVE__ACTIVE_MASK__CI__VI 0x00000001L -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK__CI__VI 0x00000100L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK__CI 0x00000003L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK__CI__VI 0x00000010L -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK__CI__VI 0x00000001L -#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK__CI 0x0000000cL -#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK__CI 0x00000003L -#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK__CI 0x00000200L -#define CP_HQD_HQ_SCHEDULER0__RSVR_31_10_MASK__CI 0xfffffc00L -#define CP_HQD_HQ_SCHEDULER0__RSV_6_4_MASK__CI 0x00000070L -#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK__CI 0x00000080L -#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK__CI 0x00000100L -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK__CI__VI 0xffffffffL -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK__CI__VI 0xfffffffcL -#define CP_HQD_IB_CONTROL__IB_ATC_MASK__CI__VI 0x00800000L -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK__CI 0x03000000L -#define CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK__CI__VI 0x40000000L -#define CP_HQD_IB_CONTROL__IB_SIZE_MASK__CI__VI 0x000fffffL -#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK__CI 0x04000000L -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK__CI__VI 0x00300000L -#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK__CI__VI 0x80000000L -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK__CI__VI 0x000fffffL -#define CP_HQD_IQ_RPTR__OFFSET_MASK__CI__VI 0x0000003fL -#define CP_HQD_IQ_TIMER__ACTIVE_MASK__CI__VI 0x80000000L -#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK__CI__VI 0x003f0000L -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK__CI__VI 0x00003000L -#define CP_HQD_IQ_TIMER__IQ_ATC_MASK__CI__VI 0x00800000L -#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK__CI 0x04000000L -#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK__CI__VI 0x40000000L -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK__CI__VI 0x20000000L -#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK__CI__VI 0x00000700L -#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK__CI__VI 0x000000ffL -#define CP_HQD_MSG_TYPE__ACTION_MASK__CI 0x00000003L -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK__CI__VI 0x80000000L -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK__CI__VI 0x00000001L -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK__CI__VI 0x0003ff00L -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK__CI__VI 0x00000003L -#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK__CI__VI 0x000000ffL -#define CP_HQD_PQ_BASE__ADDR_MASK__CI__VI 0xffffffffL -#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK__CI 0x00030000L -#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK__CI__VI 0x80000000L -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK__CI__VI 0x00300000L -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK__CI__VI 0x08000000L -#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK__CI__VI 0x00800000L -#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK__CI 0x04000000L -#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK__CI__VI 0x40000000L -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK__CI__VI 0x0000003fL -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK__CI__VI 0x20000000L -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK__CI__VI 0x00003f00L -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK__CI__VI 0x10000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK__CI__VI 0x40000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK__CI__VI 0x80000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK__CI__VI 0x007ffffcL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK__CI__VI 0x20000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK__CI__VI 0x10000000L -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK__CI__VI 0xfffffffcL -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK__CI__VI 0xffffffffL -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK__CI__VI 0xfffffffcL -#define CP_HQD_PQ_WPTR__OFFSET_MASK__CI__VI 0xffffffffL -#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK__CI__VI 0x00003f00L -#define CP_HQD_QUANTUM__QUANTUM_EN_MASK__CI__VI 0x00000001L -#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK__CI__VI 0x00000010L -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK__CI__VI 0x0000000fL -#define CP_HQD_SEMA_CMD__RESULT_MASK__CI__VI 0x00000006L -#define CP_HQD_SEMA_CMD__RETRY_MASK__CI__VI 0x00000001L -#define CP_HQD_VMID__IB_VMID_MASK__CI__VI 0x00000f00L -#define CP_HQD_VMID__VMID_MASK__CI__VI 0x0000000fL -#define CP_HQD_VMID__VQID_MASK__CI__VI 0x03ff0000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL0_MASK__CI__VI 0x00000003L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL10_MASK__CI__VI 0x00300000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL11_MASK__CI__VI 0x00c00000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL12_MASK__CI__VI 0x03000000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL13_MASK__CI__VI 0x0c000000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL14_MASK__CI__VI 0x30000000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL15_MASK__CI__VI 0xc0000000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL1_MASK__CI__VI 0x0000000cL -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL2_MASK__CI__VI 0x00000030L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL3_MASK__CI__VI 0x000000c0L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL4_MASK__CI__VI 0x00000300L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL5_MASK__CI__VI 0x00000c00L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL6_MASK__CI__VI 0x00003000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL7_MASK__CI__VI 0x0000c000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL8_MASK__CI__VI 0x00030000L -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL9_MASK__CI__VI 0x000c0000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL16_MASK__CI__VI 0x00000003L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL17_MASK__CI__VI 0x0000000cL -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL18_MASK__CI__VI 0x00000030L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL19_MASK__CI__VI 0x000000c0L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL20_MASK__CI__VI 0x00000300L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL21_MASK__CI__VI 0x00000c00L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL22_MASK__CI__VI 0x00003000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL23_MASK__CI__VI 0x0000c000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL24_MASK__CI__VI 0x00030000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL25_MASK__CI__VI 0x000c0000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL26_MASK__CI__VI 0x00300000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL27_MASK__CI__VI 0x00c00000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL28_MASK__CI__VI 0x03000000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL29_MASK__CI__VI 0x0c000000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL30_MASK__CI__VI 0x30000000L -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL31_MASK__CI__VI 0xc0000000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL32_MASK__CI__VI 0x00000003L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL33_MASK__CI__VI 0x0000000cL -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL34_MASK__CI__VI 0x00000030L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL35_MASK__CI__VI 0x000000c0L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL36_MASK__CI__VI 0x00000300L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL37_MASK__CI__VI 0x00000c00L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL38_MASK__CI__VI 0x00003000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL39_MASK__CI__VI 0x0000c000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL40_MASK__CI__VI 0x00030000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL41_MASK__CI__VI 0x000c0000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL42_MASK__CI__VI 0x00300000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL43_MASK__CI__VI 0x00c00000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL44_MASK__CI__VI 0x03000000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL45_MASK__CI__VI 0x0c000000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL46_MASK__CI__VI 0x30000000L -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL47_MASK__CI__VI 0xc0000000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL48_MASK__CI__VI 0x00000003L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL49_MASK__CI__VI 0x0000000cL -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL50_MASK__CI__VI 0x00000030L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL51_MASK__CI__VI 0x000000c0L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL52_MASK__CI__VI 0x00000300L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL53_MASK__CI__VI 0x00000c00L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL54_MASK__CI__VI 0x00003000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL55_MASK__CI__VI 0x0000c000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL56_MASK__CI__VI 0x00030000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL57_MASK__CI__VI 0x000c0000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL58_MASK__CI__VI 0x00300000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL59_MASK__CI__VI 0x00c00000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL60_MASK__CI__VI 0x03000000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL61_MASK__CI__VI 0x0c000000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL62_MASK__CI__VI 0x30000000L -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL63_MASK__CI__VI 0xc0000000L -#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK__CI__VI 0x0000ffffL -#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK__SI 0x000000ffL -#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL -#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL -#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL -#define CP_IB1_PRIV_BASE_HI__IB1_PRIV_BASE_HI_MASK__CI__VI 0x0000ffffL -#define CP_IB1_PRIV_BASE_HI__IB1_PRIV_BASE_HI_MASK__SI 0x000000ffL -#define CP_IB1_PRIV_BASE_LO__IB1_PRIV_BASE_LO_MASK 0xfffffffcL -#define CP_IB1_PRIV_BUFSZ__IB1_PRIV_BUFSZ_MASK 0x000fffffL -#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK__CI__VI 0x0000ffffL -#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK__SI 0x000000ffL -#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL -#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL -#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING0__CP_RINGID0_INT_ENABLE_MASK__SI 0x80000000L -#define CP_INT_CNTL_RING0__CP_RINGID1_INT_ENABLE_MASK__SI 0x40000000L -#define CP_INT_CNTL_RING0__CP_RINGID2_INT_ENABLE_MASK__SI 0x20000000L -#define CP_INT_CNTL_RING0__GDS_ALLOC_ERROR_INT_ENABLE_MASK__SI 0x00008000L -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING0__SEM_SIG_INCOMPLETE_INT_ENABLE_MASK__SI 0x00010000L -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING0__WAITMEM_SEM_INT_ENABLE_MASK__SI 0x00200000L -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING1__CP_RINGID0_INT_ENABLE_MASK__SI 0x80000000L -#define CP_INT_CNTL_RING1__CP_RINGID1_INT_ENABLE_MASK__SI 0x40000000L -#define CP_INT_CNTL_RING1__CP_RINGID2_INT_ENABLE_MASK__SI 0x20000000L -#define CP_INT_CNTL_RING1__GDS_ALLOC_ERROR_INT_ENABLE_MASK__SI 0x00008000L -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING1__SEM_SIG_INCOMPLETE_INT_ENABLE_MASK__SI 0x00010000L -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING1__WAITMEM_SEM_INT_ENABLE_MASK__SI 0x00200000L -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING2__CP_RINGID0_INT_ENABLE_MASK__SI 0x80000000L -#define CP_INT_CNTL_RING2__CP_RINGID1_INT_ENABLE_MASK__SI 0x40000000L -#define CP_INT_CNTL_RING2__CP_RINGID2_INT_ENABLE_MASK__SI 0x20000000L -#define CP_INT_CNTL_RING2__GDS_ALLOC_ERROR_INT_ENABLE_MASK__SI 0x00008000L -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING2__SEM_SIG_INCOMPLETE_INT_ENABLE_MASK__SI 0x00010000L -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING2__WAITMEM_SEM_INT_ENABLE_MASK__SI 0x00200000L -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL__CP_RINGID0_INT_ENABLE_MASK__SI 0x80000000L -#define CP_INT_CNTL__CP_RINGID1_INT_ENABLE_MASK__SI 0x40000000L -#define CP_INT_CNTL__CP_RINGID2_INT_ENABLE_MASK__SI 0x20000000L -#define CP_INT_CNTL__GDS_ALLOC_ERROR_INT_ENABLE_MASK__SI 0x00008000L -#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL__SEM_SIG_INCOMPLETE_INT_ENABLE_MASK__SI 0x00010000L -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL__WAITMEM_SEM_INT_ENABLE_MASK__SI 0x00200000L -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK__SI__CI 0x00080000L -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING0__CP_RINGID0_INT_STAT_MASK__SI 0x80000000L -#define CP_INT_STATUS_RING0__CP_RINGID1_INT_STAT_MASK__SI 0x40000000L -#define CP_INT_STATUS_RING0__CP_RINGID2_INT_STAT_MASK__SI 0x20000000L -#define CP_INT_STATUS_RING0__GDS_ALLOC_ERROR_INT_STAT_MASK__SI 0x00008000L -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK__CI__VI 0x80000000L -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK__CI__VI 0x40000000L -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK__CI__VI 0x20000000L -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING0__SEM_SIG_INCOMPLETE_INT_STAT_MASK__SI 0x00010000L -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING0__WAITMEM_SEM_INT_STAT_MASK__SI 0x00200000L -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING1__CP_RINGID0_INT_STAT_MASK__SI 0x80000000L -#define CP_INT_STATUS_RING1__CP_RINGID1_INT_STAT_MASK__SI 0x40000000L -#define CP_INT_STATUS_RING1__CP_RINGID2_INT_STAT_MASK__SI 0x20000000L -#define CP_INT_STATUS_RING1__GDS_ALLOC_ERROR_INT_STAT_MASK__SI 0x00008000L -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK__CI__VI 0x80000000L -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK__CI__VI 0x40000000L -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK__CI__VI 0x20000000L -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING1__SEM_SIG_INCOMPLETE_INT_STAT_MASK__SI 0x00010000L -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING1__WAITMEM_SEM_INT_STAT_MASK__SI 0x00200000L -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING2__CP_RINGID0_INT_STAT_MASK__SI 0x80000000L -#define CP_INT_STATUS_RING2__CP_RINGID1_INT_STAT_MASK__SI 0x40000000L -#define CP_INT_STATUS_RING2__CP_RINGID2_INT_STAT_MASK__SI 0x20000000L -#define CP_INT_STATUS_RING2__GDS_ALLOC_ERROR_INT_STAT_MASK__SI 0x00008000L -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK__CI__VI 0x80000000L -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK__CI__VI 0x40000000L -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK__CI__VI 0x20000000L -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING2__SEM_SIG_INCOMPLETE_INT_STAT_MASK__SI 0x00010000L -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING2__WAITMEM_SEM_INT_STAT_MASK__SI 0x00200000L -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS__CP_RINGID0_INT_STAT_MASK__SI 0x80000000L -#define CP_INT_STATUS__CP_RINGID1_INT_STAT_MASK__SI 0x40000000L -#define CP_INT_STATUS__CP_RINGID2_INT_STAT_MASK__SI 0x20000000L -#define CP_INT_STATUS__GDS_ALLOC_ERROR_INT_STAT_MASK__SI 0x00008000L -#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK__CI__VI 0x80000000L -#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK__CI__VI 0x40000000L -#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK__CI__VI 0x20000000L -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS__SEM_SIG_INCOMPLETE_INT_STAT_MASK__SI 0x00010000L -#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS__WAITMEM_SEM_INT_STAT_MASK__SI 0x00200000L -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L -#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L -#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L -#define CP_INT_STAT_DEBUG__CP_RINGID0_INT_ASSERTED_MASK__SI 0x80000000L -#define CP_INT_STAT_DEBUG__CP_RINGID1_INT_ASSERTED_MASK__SI 0x40000000L -#define CP_INT_STAT_DEBUG__CP_RINGID2_INT_ASSERTED_MASK__SI 0x20000000L -#define CP_INT_STAT_DEBUG__GDS_ALLOC_ERROR_INT_ASSERTED_MASK__SI 0x00008000L -#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK__CI__VI 0x80000000L -#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK__CI__VI 0x40000000L -#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK__CI__VI 0x20000000L -#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L -#define CP_INT_STAT_DEBUG__SEM_SIG_INCOMPLETE_INT_ASSERTED_MASK__SI 0x00010000L -#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L -#define CP_INT_STAT_DEBUG__WAITMEM_SEM_INT_ASSERTED_MASK__SI 0x00200000L -#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK__CI__VI 0x0000ff00L -#define CP_IQ_WAIT_TIME1__GWS_MASK__CI__VI 0xff000000L -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK__CI__VI 0x000000ffL -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK__CI__VI 0x00ff0000L -#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK__CI__VI 0xff000000L -#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK__CI__VI 0x000000ffL -#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK__CI__VI 0x0000ff00L -#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK__CI__VI 0x00ff0000L -#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK__CI__VI 0x00000007L -#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK__SI__CI 0x0000001fL -#define CP_MC_RD_RETURN_TAGS__READ_RETURN_NACK_MASK__SI 0x00030000L -#define CP_MC_RD_RETURN_TAGS__READ_RETURN_TAG_MASK__SI 0x0000ffffL -#define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK__CI 0x0000003fL -#define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK__CI 0x00030000L -#define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK__CI 0xffffffffL -#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME0_PIPE0_VMID__VMID_MASK__CI__VI 0x0000000fL -#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME0_PIPE1_VMID__VMID_MASK__CI__VI 0x0000000fL -#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK__CI__VI 0x000000ffL -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK__CI__VI 0x0000ff00L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK__CI__VI 0x00ff0000L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK__CI__VI 0xff000000L -#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK__CI__VI 0x00004000L -#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK__CI__VI 0x00002000L -#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK__CI__VI 0x80000000L -#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK__CI__VI 0x40000000L -#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK__CI__VI 0x20000000L -#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK__CI__VI 0x01000000L -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK__CI__VI 0x00800000L -#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK__CI__VI 0x08000000L -#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK__CI__VI 0x04000000L -#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK__CI__VI 0x000000ffL -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK__CI__VI 0x0000ff00L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK__CI__VI 0x00ff0000L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK__CI__VI 0xff000000L -#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK__CI__VI 0x00004000L -#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK__CI__VI 0x00002000L -#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK__CI__VI 0x80000000L -#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK__CI__VI 0x40000000L -#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK__CI__VI 0x20000000L -#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK__CI__VI 0x01000000L -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK__CI__VI 0x00800000L -#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK__CI__VI 0x08000000L -#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK__CI__VI 0x04000000L -#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK__CI__VI 0x00004000L -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK__CI__VI 0x00002000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK__CI__VI 0x80000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK__CI__VI 0x40000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK__CI__VI 0x20000000L -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK__CI__VI 0x01000000L -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK__CI__VI 0x00800000L -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK__CI__VI 0x08000000L -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK__CI__VI 0x04000000L -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK__CI__VI 0x00020000L -#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK__CI__VI 0x00000003L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK__CI__VI 0x000000ffL -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK__CI__VI 0x0000ff00L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK__CI__VI 0x00ff0000L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK__CI__VI 0xff000000L -#define CP_MEC1_F32_INTERRUPT__ECC_ROQ_FED_INT_MASK__CI 0x00000001L -#define CP_MEC1_F32_INTERRUPT__MEC_F32_INT_3_MASK__CI 0x00000008L -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK__CI__VI 0x00000002L -#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK__CI__VI 0x00000004L -#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK__CI 0x00000fffL -#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK__CI 0x00000fffL -#define CP_MEC2_F32_INTERRUPT__ECC_ROQ_FED_INT_MASK__CI 0x00000001L -#define CP_MEC2_F32_INTERRUPT__MEC_F32_INT_3_MASK__CI 0x00000008L -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK__CI__VI 0x00000002L -#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK__CI__VI 0x00000004L -#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK__CI 0x00000fffL -#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK__CI 0x00000fffL -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK__CI__VI 0x00000010L -#define CP_MEC_CNTL__MEC_ME1_HALT_MASK__CI__VI 0x40000000L -#define CP_MEC_CNTL__MEC_ME1_STEP_MASK__CI__VI 0x80000000L -#define CP_MEC_CNTL__MEC_ME2_HALT_MASK__CI__VI 0x10000000L -#define CP_MEC_CNTL__MEC_ME2_STEP_MASK__CI__VI 0x20000000L -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK__CI__VI 0xffffffffL -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK__CI 0x00001fffL -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK__CI__VI 0xffffffffL -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK__CI__VI 0xffffffffL -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK__CI 0x00001fffL -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK__CI__VI 0xffffffffL -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L -#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L -#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL -#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL -#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L -#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK__CI__VI 0x000000ffL -#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL -#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK__CI__VI 0x00000010L -#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L -#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK__CI__VI 0x00000100L -#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L -#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK__CI__VI 0x00000040L -#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L -#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK__CI__VI 0x00000001L -#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK__CI__VI 0x00000004L -#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK__CI__VI 0x00000008L -#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK__CI__VI 0x00000002L -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL -#define CP_ME_INTR_ROUTINE_START__IR_START_MASK__CI 0x000007ffL -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK__SI 0x000000ffL -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x00000003L -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK__SI 0x000000ffL -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x00000003L -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL -#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK__SI__CI 0x00000001L -#define CP_ME_PRGRM_CNTR_START__IP_START_MASK__CI 0x000007ffL -#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK__CI__VI 0xfffffffcL -#define CP_MQD_CONTROL__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_MQD_CONTROL__MQD_ATC_MASK__CI__VI 0x00800000L -#define CP_MQD_CONTROL__MQD_VOLATILE_MASK__CI 0x04000000L -#define CP_MQD_CONTROL__PRIV_STATE_MASK__CI__VI 0x00000100L -#define CP_MQD_CONTROL__VMID_MASK__CI__VI 0x0000000fL -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL -#define CP_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK__SI 0x0000ffffL -#define CP_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK__SI 0xffffffffL -#define CP_PERFCOUNTER_SELECT__PERF_SEL_MASK__SI 0x0000003fL -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L -#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK__CI__VI 0x000000f0L -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK__CI__VI 0x00000001L -#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK__CI__VI 0x00000008L -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK__CI__VI 0x00000002L -#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK__CI__VI 0x00000004L -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK__CI__VI 0xffffffffL -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK__CI__VI 0xffffffffL -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL -#define CP_PFP_IB_CONTROL__IB_EN_MASK__CI__VI 0x000000ffL -#define CP_PFP_IB_CONTROL__IB_EN_MASK__SI 0x00000001L -#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK__CI 0x000007ffL -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L -#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK__CI 0x00008000L -#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK__CI 0x000007ffL -#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL -#define CP_PIPEID__PIPE_ID_MASK__CI__VI 0x00000003L -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK__SI 0xffffffffL -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK__SI__CI 0x00000003L -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK__CI__VI 0xffffffffL -#define CP_PQ_WPTR_POLL_CNTL__EN_MASK__CI__VI 0x80000000L -#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK__CI__VI 0x000000ffL -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK__CI__VI 0x40000000L -#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000ffffL -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK__CI__VI 0xffffffffL -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK__CI__VI 0xffffffffL -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK__CI__VI 0x00000003L -#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK__CI__VI 0x000003fcL -#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK__CI 0x00300000L -#define CP_PRT_LOD_STATS_CNTL2__MC_PRIV_MODE_MASK__CI 0x00400000L -#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK__CI__VI 0x07800000L -#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK__CI__VI 0x00080000L -#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK__CI__VI 0x0003fc00L -#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK__CI__VI 0x00040000L -#define CP_PWR_CNTL__GFX_CLK_HALT_MASK__CI 0x00000001L -#define CP_PWR_CNTL__TCIU_HALT_MASK__SI 0x00000001L -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L -#define CP_RB0_BASE_HI__RB_BASE_HI_MASK__CI__VI 0x000000ffL -#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL -#define CP_RB0_CNTL__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_RB0_CNTL__ENA_WPTR_POLL_MASK__SI 0x01000000L -#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -#define CP_RB0_CNTL__RB_VOLATILE_MASK__CI 0x04000000L -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__SI 0x000000ffL -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL -#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L -#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL -#define CP_RB0_WPTR__RB_WPTR_MASK 0x000fffffL -#define CP_RB1_BASE_HI__RB_BASE_HI_MASK__CI__VI 0x000000ffL -#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL -#define CP_RB1_CNTL__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -#define CP_RB1_CNTL__RB_VOLATILE_MASK__CI 0x04000000L -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__SI 0x000000ffL -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL -#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L -#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL -#define CP_RB1_WPTR__RB_WPTR_MASK 0x000fffffL -#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL -#define CP_RB2_CNTL__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -#define CP_RB2_CNTL__RB_VOLATILE_MASK__CI 0x04000000L -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__SI 0x000000ffL -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL -#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L -#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL -#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL -#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL -#define CP_RB_CNTL__CACHE_POLICY_MASK__CI 0x03000000L -#define CP_RB_CNTL__ENA_WPTR_POLL_MASK__SI 0x01000000L -#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -#define CP_RB_CNTL__RB_VOLATILE_MASK__CI 0x04000000L -#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK__SI 0x000000ffL -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL -#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L -#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL -#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL -#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL -#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L -#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL -#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK__CI 0x000000ffL -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK__SI__VI 0x000000ffL -#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK__CI 0xfffffffcL -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK__SI__VI 0xfffffffcL -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL -#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL -#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L -#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L -#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L -#define CP_RINGID__RINGID_MASK 0x00000003L -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L -#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L -#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L -#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL -#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL -#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L -#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L -#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL -#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L -#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L -#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03ff0000L -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003ffL -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03ff0000L -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003ffL -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03ff0000L -#define CP_ROQ_THRESHOLDS__IB1_START_MASK__CI__VI 0x000000ffL -#define CP_ROQ_THRESHOLDS__IB2_START_MASK__CI__VI 0x0000ff00L -#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL -#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000ffL -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffffL -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffffL -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK__CI__VI 0xffffffffL -#define CP_SC_PSINVOC_COUNT1_HI__PSINVOC_COUNT1_HI_MASK__SI 0xffffffffL -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK__CI__VI 0xffffffffL -#define CP_SC_PSINVOC_COUNT1_LO__PSINVOC_COUNT1_LO_MASK__SI 0xffffffffL -#define CP_SEM_INCOMPLETE_TIMER_CNTL__SIGNAL_TIMER_CNTL_MASK__SI 0x0000ffffL -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffffL -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK__SI 0x000000ffL -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L -#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK__SI__CI 0x00004000L -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L -#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK__SI__CI 0x00010000L -#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK__SI__CI 0x00020000L -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT1__RBIU_TO_EOPD_NOT_RDY_TO_RCV_MASK__SI 0x00000040L -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L -#define CP_STALLED_STAT1__RBIU_TO_PSTAT_NOT_RDY_TO_RCV_MASK__SI 0x00000200L -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT1__RBIU_TO_STRMO_NOT_RDY_TO_RCV_MASK__SI 0x00000100L -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK__CI__VI 0x20000000L -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK__SI 0x10000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK__CI__VI 0x10000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L -#define CP_STALLED_STAT2__PFP_HALTED_BY_INSTR_VIOLATION_MASK__SI 0x00000008L -#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK__SI__CI 0x00000040L -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK__CI__VI 0x00100000L -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK__CI__VI 0x00080000L -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK__SI__CI 0x00000080L -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L -#define CP_STALLED_STAT3__CE_HALTED_BY_INSTR_VIOLATION_MASK__SI 0x00000200L -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L -#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK__SI__CI 0x00000100L -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L -#define CP_STAT__CE_BUSY_MASK 0x04000000L -#define CP_STAT__CPC_CPG_BUSY_MASK__CI__VI 0x02000000L -#define CP_STAT__CP_BUSY_MASK 0x80000000L -#define CP_STAT__CSF_ARBITER_BUSY_MASK__SI 0x00000020L -#define CP_STAT__CSF_BUSY_MASK__SI 0x00000040L -#define CP_STAT__CSF_INDIRECT1_BUSY_MASK__SI 0x00000004L -#define CP_STAT__CSF_INDIRECT2_BUSY_MASK__SI 0x00000008L -#define CP_STAT__CSF_RING_BUSY_MASK__SI 0x00000001L -#define CP_STAT__CSF_STATE_BUSY_MASK__SI 0x00000010L -#define CP_STAT__CSF_WPTR_POLL_BUSY_MASK__SI 0x00000002L -#define CP_STAT__DC_BUSY_MASK__CI__VI 0x00002000L -#define CP_STAT__DMA_BUSY_MASK 0x00400000L -#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L -#define CP_STAT__MEQ_BUSY_MASK 0x00010000L -#define CP_STAT__ME_BUSY_MASK 0x00020000L -#define CP_STAT__MIU_RDREQ_BUSY_MASK__SI__CI 0x00000080L -#define CP_STAT__MIU_WRREQ_BUSY_MASK__SI__CI 0x00000100L -#define CP_STAT__PFP_BUSY_MASK 0x00008000L -#define CP_STAT__QUERY_BUSY_MASK 0x00040000L -#define CP_STAT__RCIU_BUSY_MASK 0x00800000L -#define CP_STAT__ROQ_ALIGN_BUSY_MASK__SI 0x00004000L -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L -#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L -#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L -#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L -#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L -#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L -#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L -#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L -#define CP_STAT__SURFACE_PROBE_BUSY_MASK__SI 0x02000000L -#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L -#define CP_STAT__TCIU_BUSY_MASK 0x08000000L -#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001ffL -#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003ffL -#define CP_STQ_STAT__STQ_WPTR_MASK__SI 0x03ff0000L -#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000ffL -#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000ff00L -#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00ff0000L -#define CP_STQ_WR_STAT__STQ_WPTR_MASK__CI__VI 0x000003ffL -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK__SI 0xffffffffL -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffcL -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK__SI__CI 0x00000003L -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L -#define CP_ST_BASE_HI__ST_BASE_HI_MASK__CI__VI 0x0000ffffL -#define CP_ST_BASE_HI__ST_BASE_HI_MASK__SI 0x000000ffL -#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffcL -#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffffL -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffffL -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffffL -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffffL -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffffL -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffffL -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffffL -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffffL -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffffL -#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK__CI__VI 0x0000ffffL -#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK__CI 0xffff0000L -#define CP_VMID_RESET__RESET_REQUEST_MASK__CI__VI 0x0000ffffL -#define CP_VMID_RESET__RESET_STATUS_MASK__CI__VI 0xffff0000L -#define CP_VMID__VMID_MASK 0x0000000fL -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffffL -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK__CI__VI 0x0000ffffL -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK__SI 0x000000ffL -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_WAIT_SEM_STATUS__WAIT_PENDING_MASK__CI 0x00000004L -#define CP_WAIT_SEM_STATUS__WAIT_STATUS_MASK__CI 0x00000003L -#define CRT00__H_TOTAL_MASK__SI 0x000000ffL -#define CRT01__H_DISP_END_MASK__SI 0x000000ffL -#define CRT02__H_BLANK_START_MASK__SI 0x000000ffL -#define CRT03__CR10CR11_R_DIS_B_MASK__SI 0x00000080L -#define CRT03__H_BLANK_END_MASK__SI 0x0000001fL -#define CRT03__H_DE_SKEW_MASK__SI 0x00000060L -#define CRT04__H_SYNC_START_MASK__SI 0x000000ffL -#define CRT05__H_BLANK_END_B5_MASK__SI 0x00000080L -#define CRT05__H_SYNC_END_MASK__SI 0x0000001fL -#define CRT05__H_SYNC_SKEW_MASK__SI 0x00000060L -#define CRT06__V_TOTAL_MASK__SI 0x000000ffL -#define CRT07__LINE_CMP_B8_MASK__SI 0x00000010L -#define CRT07__V_BLANK_START_B8_MASK__SI 0x00000008L -#define CRT07__V_DISP_END_B8_MASK__SI 0x00000002L -#define CRT07__V_DISP_END_B9_MASK__SI 0x00000040L -#define CRT07__V_SYNC_START_B8_MASK__SI 0x00000004L -#define CRT07__V_SYNC_START_B9_MASK__SI 0x00000080L -#define CRT07__V_TOTAL_B8_MASK__SI 0x00000001L -#define CRT07__V_TOTAL_B9_MASK__SI 0x00000020L -#define CRT08__BYTE_PAN_MASK__SI 0x00000060L -#define CRT08__ROW_SCAN_START_MASK__SI 0x0000001fL -#define CRT09__DOUBLE_CHAR_HEIGHT_MASK__SI 0x00000080L -#define CRT09__LINE_CMP_B9_MASK__SI 0x00000040L -#define CRT09__MAX_ROW_SCAN_MASK__SI 0x0000001fL -#define CRT09__V_BLANK_START_B9_MASK__SI 0x00000020L -#define CRT0A__CURSOR_DISABLE_MASK__SI 0x00000020L -#define CRT0A__CURSOR_START_MASK__SI 0x0000001fL -#define CRT0B__CURSOR_END_MASK__SI 0x0000001fL -#define CRT0B__CURSOR_SKEW_MASK__SI 0x00000060L -#define CRT0C__DISP_START_MASK__SI 0x000000ffL -#define CRT0D__DISP_START_MASK__SI 0x000000ffL -#define CRT0E__CURSOR_LOC_HI_MASK__SI 0x000000ffL -#define CRT0F__CURSOR_LOC_LO_MASK__SI 0x000000ffL -#define CRT10__V_SYNC_START_MASK__SI 0x000000ffL -#define CRT11__C0T7_WR_ONLY_MASK__SI 0x00000080L -#define CRT11__SEL5_REFRESH_CYC_MASK__SI 0x00000040L -#define CRT11__V_INTR_CLR_MASK__SI 0x00000010L -#define CRT11__V_INTR_EN_MASK__SI 0x00000020L -#define CRT11__V_SYNC_END_MASK__SI 0x0000000fL -#define CRT12__V_DISP_END_MASK__SI 0x000000ffL -#define CRT13__DISP_PITCH_MASK__SI 0x000000ffL -#define CRT14__ADDR_CNT_BY4_MASK__SI 0x00000020L -#define CRT14__DOUBLE_WORD_MASK__SI 0x00000040L -#define CRT14__UNDRLN_LOC_MASK__SI 0x0000001fL -#define CRT15__V_BLANK_START_MASK__SI 0x000000ffL -#define CRT16__V_BLANK_END_MASK__SI 0x000000ffL -#define CRT17__ADDR_CNT_BY2_MASK__SI 0x00000008L -#define CRT17__BYTE_MODE_MASK__SI 0x00000040L -#define CRT17__CRTC_SYNC_EN_MASK__SI 0x00000080L -#define CRT17__RA0_AS_A13B_MASK__SI 0x00000001L -#define CRT17__RA1_AS_A14B_MASK__SI 0x00000002L -#define CRT17__VCOUNT_BY2_MASK__SI 0x00000004L -#define CRT17__WRAP_A15TOA0_MASK__SI 0x00000020L -#define CRT18__LINE_CMP_MASK__SI 0x000000ffL -#define CRT1E__GRPH_DEC_RD1_MASK__SI 0x00000002L -#define CRT1F__GRPH_DEC_RD0_MASK__SI 0x000000ffL -#define CRT22__GRPH_LATCH_DATA_MASK__SI 0x000000ffL -#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK__SI 0x00000001L -#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK__SI 0x00000002L -#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK__SI 0x00000001L -#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK__SI 0x00000002L -#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK__SI 0x00000001L -#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK__SI 0x00000002L -#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK__SI 0x00000001L -#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK__SI 0x00000002L -#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK__SI 0x00000001L -#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK__SI 0x00000002L -#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK__SI 0x00000001L -#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK__SI 0x00000002L -#define CRTC8_DATA__VCRTC_DATA_MASK__SI 0x000000ffL -#define CRTC8_IDX__VCRTC_IDX_MASK__SI 0x0000003fL -#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK__SI 0x000000ffL -#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK__SI 0x00010000L -#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK__SI 0x000003ffL -#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK__SI 0x000ffc00L -#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK__SI 0x3ff00000L -#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK__SI 0x00000100L -#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK__SI 0x00010000L -#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK__SI 0x00000001L -#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK__SI 0x000003ffL -#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK__SI 0x000ffc00L -#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK__SI 0x3ff00000L -#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK__SI 0x00010000L -#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK__SI 0x00000300L -#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK__SI 0x01000000L -#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK__SI 0x00002000L -#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK__SI 0x00700000L -#define CRTC_CONTROL__CRTC_MASTER_EN_MASK__SI 0x00000001L -#define CRTC_CONTROL__CRTC_PREFETCH_EN_MASK__SI 0x10000000L -#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK__SI 0x20000000L -#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK__SI 0x00001000L -#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK__SI 0x00000010L -#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK__SI 0x00000001L -#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK__SI 0x0000001eL -#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK__SI 0x00000001L -#define CRTC_DEBUG_01__ID48_CRTC_BLANK_MASK__SI 0x08000000L -#define CRTC_DEBUG_01__ID48_CRTC_DATA_ACTIVE_MASK__SI 0x04000000L -#define CRTC_DEBUG_01__ID48_CRTC_FREEZE_MASK__SI 0x20000000L -#define CRTC_DEBUG_01__ID48_CRTC_HSYNC_A_MASK__SI 0x01000000L -#define CRTC_DEBUG_01__ID48_CRTC_HSYNC_B_MASK__SI 0x40000000L -#define CRTC_DEBUG_01__ID48_CRTC_H_COUNT_MASK__SI 0x00000fffL -#define CRTC_DEBUG_01__ID48_CRTC_STEREOSYNC_MASK__SI 0x10000000L -#define CRTC_DEBUG_01__ID48_CRTC_VSYNC_A_MASK__SI 0x02000000L -#define CRTC_DEBUG_01__ID48_CRTC_VSYNC_B_MASK__SI 0x80000000L -#define CRTC_DEBUG_01__ID48_CRTC_V_COUNT_MASK__SI 0x00fff000L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_EOL_MASK__SI 0x00004000L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_HALF_H_TOTAL_MASK__SI 0x00010000L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_HTOTAL_BY_8_MASK__SI 0x00020000L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_ACTIVE_END_MASK__SI 0x00000400L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_ACTIVE_START_MASK__SI 0x00000200L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_BLANK_END_MASK__SI 0x00000080L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_BLANK_START_MASK__SI 0x00000040L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_CAPTURESTART_A_MASK__SI 0x00001000L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_CAPTURESTART_B_MASK__SI 0x00002000L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_A_END_MASK__SI 0x00000002L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_A_START_MASK__SI 0x00000001L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_B_END_MASK__SI 0x00000010L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_B_START_MASK__SI 0x00000008L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_TV_FRAMESTART_MASK__SI 0x00040000L -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_SOL_MASK__SI 0x00008000L -#define CRTC_DEBUG_02__ID49_CRTC_H_ACTIVE_MASK__SI 0x00000800L -#define CRTC_DEBUG_02__ID49_CRTC_H_BLANK_MASK__SI 0x00000100L -#define CRTC_DEBUG_02__ID49_CRTC_H_COUNT_ADV_EN_MASK__SI 0x00080000L -#define CRTC_DEBUG_02__ID49_CRTC_H_COUNT_MASK__SI 0xfff00000L -#define CRTC_DEBUG_02__ID49_CRTC_H_SYNC_A_MASK__SI 0x00000004L -#define CRTC_DEBUG_02__ID49_CRTC_H_SYNC_B_MASK__SI 0x00000020L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_END_LINE_MASK__SI 0x00020000L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_HALF_H_TOTAL_MASK__SI 0x00000008L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_START_LINE_MASK__SI 0x00010000L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_ACTIVE_END_MASK__SI 0x00000200L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_ACTIVE_START_MASK__SI 0x00000100L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_BLANK_END_MASK__SI 0x00000040L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_BLANK_START_MASK__SI 0x00000020L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_CAPTURESTART_A_MASK__SI 0x00000800L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_CAPTURESTART_B_MASK__SI 0x00008000L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_A_END_MASK__SI 0x00000002L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_A_START_MASK__SI 0x00000001L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_B_END_MASK__SI 0x00002000L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_B_START_MASK__SI 0x00001000L -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_TV_FRAMESTART_MASK__SI 0x00040000L -#define CRTC_DEBUG_03__ID4A_CRTC_FIELD_NUMBER_EARLY_MASK__SI 0x00000004L -#define CRTC_DEBUG_03__ID4A_CRTC_V_ACTIVE_MASK__SI 0x00000400L -#define CRTC_DEBUG_03__ID4A_CRTC_V_BLANK_MASK__SI 0x00000080L -#define CRTC_DEBUG_03__ID4A_CRTC_V_COUNT_MASK__SI 0xfff00000L -#define CRTC_DEBUG_03__ID4A_CRTC_V_SYNC_A_MASK__SI 0x00000010L -#define CRTC_DEBUG_03__ID4A_CRTC_V_SYNC_B_MASK__SI 0x00004000L -#define CRTC_DEBUG_03__ID4A_CRTC_V_UPDATE_MASK__SI 0x00080000L -#define CRTC_DEBUG_04__ID4B_CRTC_BLANK_EN_MASK__SI 0x00800000L -#define CRTC_DEBUG_04__ID4B_CRTC_BLANK_MASK__SI 0x08000000L -#define CRTC_DEBUG_04__ID4B_CRTC_CRTC_EN_MASK__SI 0x00001000L -#define CRTC_DEBUG_04__ID4B_CRTC_DATA_ACTIVE_MASK__SI 0x40000000L -#define CRTC_DEBUG_04__ID4B_CRTC_EVENT_HALF_H_TOTAL_MASK__SI 0x00000004L -#define CRTC_DEBUG_04__ID4B_CRTC_EVENT_V_BLANK_START_MASK__SI 0x00000010L -#define CRTC_DEBUG_04__ID4B_CRTC_EVENT_V_TOTAL_MASK__SI 0x00000008L -#define CRTC_DEBUG_04__ID4B_CRTC_FIELD_NUMBER_EARLY_MASK__SI 0x00008000L -#define CRTC_DEBUG_04__ID4B_CRTC_FIELD_NUMBER_MASK__SI 0x00010000L -#define CRTC_DEBUG_04__ID4B_CRTC_FORCE_NEXT_FIELD_EVEN_MASK__SI 0x00004000L -#define CRTC_DEBUG_04__ID4B_CRTC_FORCE_NEXT_FIELD_ODD_MASK__SI 0x00002000L -#define CRTC_DEBUG_04__ID4B_CRTC_FREEZE_MASK__SI 0x01000000L -#define CRTC_DEBUG_04__ID4B_CRTC_H_BLANK_MASK__SI 0x02000000L -#define CRTC_DEBUG_04__ID4B_CRTC_H_DATA_ACTIVE_MASK__SI 0x10000000L -#define CRTC_DEBUG_04__ID4B_CRTC_H_TV_FRAMESTART_MASK__SI 0x00100000L -#define CRTC_DEBUG_04__ID4B_CRTC_H_UPDATE_EVENT_MASK__SI 0x00000001L -#define CRTC_DEBUG_04__ID4B_CRTC_INTERLACE_SELECT_MASK__SI 0x00020000L -#define CRTC_DEBUG_04__ID4B_CRTC_READ_REQUEST_MASK__SI 0x80000000L -#define CRTC_DEBUG_04__ID4B_CRTC_STEREOSYNC_OUTPUT_MASK__SI 0x00000200L -#define CRTC_DEBUG_04__ID4B_CRTC_STEREOSYNC_SELECT_MASK__SI 0x00000100L -#define CRTC_DEBUG_04__ID4B_CRTC_STEREO_CURRENT_EYE_MASK__SI 0x00000400L -#define CRTC_DEBUG_04__ID4B_CRTC_TV_FRAMESTART_FREQ_COUNT_MASK__SI 0x000c0000L -#define CRTC_DEBUG_04__ID4B_CRTC_TV_FRAMESTART_MASK__SI 0x00400000L -#define CRTC_DEBUG_04__ID4B_CRTC_V_BLANK_MASK__SI 0x04000000L -#define CRTC_DEBUG_04__ID4B_CRTC_V_DATA_ACTIVE_MASK__SI 0x20000000L -#define CRTC_DEBUG_04__ID4B_CRTC_V_TV_FRAMESTART_MASK__SI 0x00200000L -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_EVENT_MASK__SI 0x00000002L -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_MODE_1_MASK__SI 0x00000020L -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_MODE_2_MASK__SI 0x00000040L -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_MODE_3_MASK__SI 0x00000080L -#define CRTC_DEBUG_05__ID4C_CRTC_BLANK_DATA_EN_UPDATE_ENABLE_MASK__SI 0x08000000L -#define CRTC_DEBUG_05__ID4C_CRTC_BLANK_EN_MASK__SI 0x10000000L -#define CRTC_DEBUG_05__ID4C_CRTC_CRTCREGS_DISP_READ_REQUEST_DIS_MASK__SI 0x20000000L -#define CRTC_DEBUG_05__ID4C_CRTC_CRTC_EN_MASK__SI 0x00400000L -#define CRTC_DEBUG_05__ID4C_CRTC_CURRENT_CRTC_STATE_MASK__SI 0x00300000L -#define CRTC_DEBUG_05__ID4C_CRTC_CURRENT_STATE_SM_PCLK_MASK__SI 0x00000200L -#define CRTC_DEBUG_05__ID4C_CRTC_CURRENT_STATE_SM_SCLK_MASK__SI 0x00000c00L -#define CRTC_DEBUG_05__ID4C_CRTC_DISP_READ_REQUEST_DIS_MASK__SI 0x40000000L -#define CRTC_DEBUG_05__ID4C_CRTC_EVENT_H_SYNC_A_START_MASK__SI 0x01000000L -#define CRTC_DEBUG_05__ID4C_CRTC_EVENT_V_BLANK_START_MASK__SI 0x02000000L -#define CRTC_DEBUG_05__ID4C_CRTC_EXTEND_CRTC_EN_MASK__SI 0x00800000L -#define CRTC_DEBUG_05__ID4C_CRTC_H_SYNC_A_POL_MASK__SI 0x00008000L -#define CRTC_DEBUG_05__ID4C_CRTC_OVERSCAN_COLOR_EN_MASK__SI 0x00020000L -#define CRTC_DEBUG_05__ID4C_CRTC_RESET_SM_SCLK_MASK__SI 0x00000004L -#define CRTC_DEBUG_05__ID4C_CRTC_SYNC_POLARITY_SEL_MASK__SI 0x00004000L -#define CRTC_DEBUG_05__ID4C_CRTC_TIMING_SEL_MASK__SI 0x00040000L -#define CRTC_DEBUG_05__ID4C_CRTC_TOP_OVERSCAN_ODD_MASK__SI 0x00001000L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_DONE_MASK__SI 0x00000008L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_ENABLE_MASK__SI 0x00080000L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_ENABLE_PCLK_MASK__SI 0x00000100L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_ENABLE_SCLK_MASK__SI 0x00000020L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_EVENT_MASK__SI 0x00000080L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_INSTANTLY_MASK__SI 0x00000040L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_LOCK_ORED_MASK__SI 0x00000002L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_PENDING_MASK__SI 0x00000010L -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_VGA_CUR_BUF_MASK__SI 0x04000000L -#define CRTC_DEBUG_05__ID4C_CRTC_V_SYNC_A_POL_MASK__SI 0x00010000L -#define CRTC_DEBUG_05__ID4C_CRTC_V_SYNC_A_SEL_MASK__SI 0x00002000L -#define CRTC_DEBUG_05__ID4C_CRTC_V_UPDATE_MASK__SI 0x80000000L -#define CRTC_DEBUG_05__ID4C_CRTC_WTRIG_ORED_MASK__SI 0x00000001L -#define CRTC_DEBUG_06__ID4D_CRTC_AUTO_FORCE_VSYNC_NEXT_LINE_MASK__SI 0x00008000L -#define CRTC_DEBUG_06__ID4D_CRTC_FIELD_NUMBER_EARLY_MASK__SI 0x80000000L -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_PCLK_MASK__SI 0x00004000L -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_SCLK_MASK__SI 0x00000080L -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE_MASK__SI 0x00010000L -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK__SI 0x00020000L -#define CRTC_DEBUG_06__ID4D_CRTC_FRAME_COUNT_MASK__SI 0x00000e00L -#define CRTC_DEBUG_06__ID4D_CRTC_H_SYNC_A_MASK__SI 0x00040000L -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN_PCLK_MASK__SI 0x04000000L -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN_SCLK_MASK__SI 0x02000000L -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD_PCLK_MASK__SI 0x01000000L -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD_SCLK_MASK__SI 0x00000100L -#define CRTC_DEBUG_06__ID4D_CRTC_LATCH_IN_COUNT_MASK__SI 0x10000000L -#define CRTC_DEBUG_06__ID4D_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_PCLK_MASK__SI 0x00002000L -#define CRTC_DEBUG_06__ID4D_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_SCLK_MASK__SI 0x00001000L -#define CRTC_DEBUG_06__ID4D_CRTC_RBBMIF_READ_READY_MASK__SI 0x40000000L -#define CRTC_DEBUG_06__ID4D_CRTC_READ_READY_COUNT_MASK__SI 0x20000000L -#define CRTC_DEBUG_06__ID4D_CRTC_RESET_FRAME_COUNT_PCLK_MASK__SI 0x00000020L -#define CRTC_DEBUG_06__ID4D_CRTC_RESET_FRAME_COUNT_SCLK_MASK__SI 0x00000010L -#define CRTC_DEBUG_06__ID4D_CRTC_RTRIG_PRE_COUNT_MASK__SI 0x08000000L -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_CLEAR_PCLK_MASK__SI 0x00000008L -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_CLEAR_SCLK_MASK__SI 0x00000004L -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_MANUAL_TRIGGER_PCLK_MASK__SI 0x00000002L -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_MANUAL_TRIGGER_SCLK_MASK__SI 0x00000001L -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_OCCURRED_MASK__SI 0x00000040L -#define CRTC_DEBUG_06__ID4D_CRTC_V_COUNT_MASK__SI 0x00f00000L -#define CRTC_DEBUG_06__ID4D_CRTC_V_SYNC_A_MASK__SI 0x00080000L -#define CRTC_DEBUG_07__ID55_CRTC_VTOTAL_MAX_MASK__SI 0x03ffe000L -#define CRTC_DEBUG_07__ID55_CRTC_VTOTAL_MIN_MASK__SI 0x00001fffL -#define CRTC_DEBUG_08__ID56_CRTC_FBC_SURFACE_INV_EVENT_MASK__SI 0x00000100L -#define CRTC_DEBUG_08__ID56_CRTC_LOCK_VCOUNT_ON_EVENT_MASK__SI 0x00000020L -#define CRTC_DEBUG_08__ID56_CRTC_LOCK_VCOUNT_ON_VSYNC_MASK__SI 0x00000010L -#define CRTC_DEBUG_08__ID56_CRTC_MC_HIT_REGION_EVENT_MASK__SI 0x00000080L -#define CRTC_DEBUG_08__ID56_CRTC_MC_MEM_WRITE_EVENT_MASK__SI 0x00000040L -#define CRTC_DEBUG_08__ID56_CRTC_VSYNC_NOM_INT_MASK__SI 0x00000400L -#define CRTC_DEBUG_08__ID56_CRTC_VSYNC_NOM_MASK__SI 0x00000200L -#define CRTC_DEBUG_08__ID56_CRTC_VTOTAL_MIN_EVENT_INT_MASK__SI 0x00000008L -#define CRTC_DEBUG_08__ID56_CRTC_VTOTAL_MIN_EVENT_MASK__SI 0x00000004L -#define CRTC_DEBUG_08__ID56_CRTC_VTOTAL_TRIG_OCCURED_MASK__SI 0x00000002L -#define CRTC_DEBUG_08__ID56_CRTC_V_TOTAL_MIN_TRIG_MASK__SI 0x00000001L -#define CRTC_DEBUG_BITS__CRTC_DEBUG_BITS_MASK__SI 0xffffffffL -#define CRTC_DEBUG__ID4E_CRTC_FORCE_H_COUNT_MASK__SI 0x40000000L -#define CRTC_DEBUG__ID4E_CRTC_FORCE_V_COUNT_MASK__SI 0x00008000L -#define CRTC_DEBUG__ID4E_CRTC_H_COUNT_MASK__SI 0x3fc00000L -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_DELAY_COUNT_MASK__SI 0x000007c0L -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_FALLING_EDGE_MASK__SI 0x00000008L -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_FREQUENCY_COUNT_MASK__SI 0x00000030L -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_MASK__SI 0x00000001L -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_RISING_EDGE_MASK__SI 0x00000004L -#define CRTC_DEBUG__ID4E_CRTC_TRIG_B_MASK__SI 0x00000002L -#define CRTC_DEBUG__ID4E_CRTC_V_COUNT_MASK__SI 0x003f0000L -#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK__SI 0x00010000L -#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK__SI 0x00000100L -#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK__SI 0x00000001L -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_BLANK_MASK__SI 0x00000002L -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_ACTIVE_MASK__SI 0x00000001L -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_B_MASK__SI 0xffc00000L -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_G_MASK__SI 0x003ff000L -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_R_MASK__SI 0x00000ffcL -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_BLANK_MASK__SI 0x00000010L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_CAPTURESTART_A_MASK__SI 0x00000004L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_CAPTURESTART_B_MASK__SI 0x00000400L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_DATA_ACTIVE_MASK__SI 0x00000008L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_FIELD_NUMBER_MASK__SI 0x00000040L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_FREEZE_MASK__SI 0x00000080L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_HSYNC_A_MASK__SI 0x00000001L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_HSYNC_B_MASK__SI 0x00000100L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_STEREOSYNC_MASK__SI 0x00000020L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_VSYNC_A_MASK__SI 0x00000002L -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_VSYNC_B_MASK__SI 0x00000200L -#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK__SI 0x0000001eL -#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK__SI 0x00000001L -#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK__SI 0x1fff0000L -#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK__SI 0x00001fffL -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK__SI 0x00010000L -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK__SI 0x01000000L -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK__SI 0x00000100L -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK__SI 0x0000001fL -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK__SI 0x01000000L -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK__SI 0x00000003L -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK__SI 0x00010000L -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK__SI 0x00000100L -#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK__SI 0x1fff0000L -#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK__SI 0x00001fffL -#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK__SI 0x00010000L -#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK__SI 0x00020000L -#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK__SI 0x00000001L -#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK__SI 0x1fff0000L -#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK__SI 0x00001fffL -#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK__SI 0x00010000L -#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK__SI 0x00020000L -#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK__SI 0x00000001L -#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK__SI 0x1fff0000L -#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK__SI 0x00001fffL -#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK__SI 0x00001fffL -#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK__SI 0x00000001L -#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK__SI 0x00030000L -#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK__SI 0x00000001L -#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK__SI 0x00000002L -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK__SI 0x00000100L -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK__SI 0x00000200L -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK__SI 0x00010000L -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK__SI 0x00020000L -#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK__SI 0x00000001L -#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK__SI 0x00000002L -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK__SI 0x01000000L -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK__SI 0x04000000L -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK__SI 0x02000000L -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK__SI 0x08000000L -#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK__SI 0x10000000L -#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK__SI 0x20000000L -#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK__SI 0x00000010L -#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK__SI 0x00000020L -#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK__SI 0x00000001L -#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK__SI 0x00000001L -#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK__SI \ - 0x000000ffL -#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK__SI 0xffffff00L -#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK__SI 0x00000003L -#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK__SI 0x00100000L -#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK__SI 0x00000010L -#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK__SI 0x00010000L -#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK__SI 0x00000001L -#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK__SI 0x00001fffL -#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK__SI 0x000003ffL -#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK__SI 0x000ffc00L -#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK__SI 0x3ff00000L -#define CRTC_PIXCLK_DTO_MODULO__CRTC_PIXCLK_DTO_MODULO_MASK__SI 0xffffffffL -#define CRTC_PIXCLK_DTO_PHASE__CRTC_PIXCLK_DTO_PHASE_MASK__SI 0xffffffffL -#define CRTC_PIXEL_DATA_READBACK__CRTC_PIXEL_DATA_BLUE_CB_MASK__SI 0x000003ffL -#define CRTC_PIXEL_DATA_READBACK__CRTC_PIXEL_DATA_GREEN_Y_MASK__SI 0x000ffc00L -#define CRTC_PIXEL_DATA_READBACK__CRTC_PIXEL_DATA_RED_CR_MASK__SI 0x3ff00000L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_END_LINE_MASK__SI 0x00000010L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_EOL_MASK__SI 0x00000008L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_HTOTAL_BY_8_MASK__SI 0x00000080L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_INTERLACE_SELECT_MASK__SI 0x00000100L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_READ_REQUEST_DIS_MASK__SI 0x00000001L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_READ_REQUEST_MASK__SI 0x00000002L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_SOL_MASK__SI 0x00000020L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_START_LINE_MASK__SI 0x00000004L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_STEREO_SELECT_MASK__SI 0x00000200L -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_V_UPDATE_MASK__SI 0x00000040L -#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK__SI 0x00000003L -#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK__SI 0x00ffffffL -#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK__SI 0x1fff0000L -#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK__SI 0x00001fffL -#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK__SI 0x00000002L -#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK__SI 0x00000004L -#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK__SI 0x00000001L -#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK__SI 0x00000100L -#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK__SI 0x00000001L -#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK__SI 0x00ffffffL -#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK__SI 0x1fffffffL -#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK__SI 0x1fff0000L -#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK__SI 0x00001fffL -#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK__SI 0x1fffffffL -#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK__SI 0x00020000L -#define CRTC_STATUS__CRTC_H_BLANK_MASK__SI 0x00010000L -#define CRTC_STATUS__CRTC_H_SYNC_A_MASK__SI 0x00040000L -#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK__SI 0x00000002L -#define CRTC_STATUS__CRTC_V_BLANK_MASK__SI 0x00000001L -#define CRTC_STATUS__CRTC_V_START_LINE_MASK__SI 0x00000010L -#define CRTC_STATUS__CRTC_V_SYNC_A_MASK__SI 0x00000004L -#define CRTC_STATUS__CRTC_V_UPDATE_MASK__SI 0x00000008L -#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK__SI 0x01000000L -#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK__SI 0x00000100L -#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK__SI 0x00010000L -#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK__SI 0x00000003L -#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK__SI 0x00000001L -#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK__SI 0x03000000L -#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK__SI 0x00000100L -#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK__SI 0x00010000L -#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK__SI 0x0000ffffL -#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK__SI 0x003f0000L -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK__SI 0xff000000L -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK__SI 0x00010000L -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK__SI 0x00000001L -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK__SI 0x00000700L -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK__SI 0x0000f000L -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK__SI 0x0000000fL -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK__SI 0x000000f0L -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK__SI 0xffff0000L -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK__SI 0x00000f00L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK__SI 0x80000000L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK__SI 0x1f000000L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK__SI 0x00030000L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK__SI 0x00300000L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK__SI 0x00000200L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK__SI 0x00000800L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK__SI 0x00000070L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK__SI 0x00000400L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK__SI 0x00000100L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK__SI 0x00003000L -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK__SI 0x0000000fL -#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK__SI 0x00000001L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK__SI 0x80000000L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK__SI 0x1f000000L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK__SI 0x00030000L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK__SI 0x00300000L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK__SI 0x00000200L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK__SI 0x00000800L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK__SI 0x00000070L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK__SI 0x00000400L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK__SI 0x00000100L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK__SI 0x00003000L -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK__SI 0x0000000fL -#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK__SI 0x00000001L -#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK__SI 0x00000001L -#define CRTC_VBI_END__CRTC_VBI_H_END_MASK__SI 0x1fff0000L -#define CRTC_VBI_END__CRTC_VBI_V_END_MASK__SI 0x00001fffL -#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK__SI 0x00030000L -#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK__SI 0x00000100L -#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK__SI 0x00000001L -#define CRTC_VGA_INTERFACE__ID46_CRTC_VGA_CUR_BUF_MASK__SI 0x00000100L -#define CRTC_VGA_INTERFACE__ID46_CRTC_VGA_NODISPLAY_MASK__SI 0x00000400L -#define CRTC_VGA_INTERFACE__ID46_CRTC_VGA_RENDER_SYNC_MASK__SI 0x00000200L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_BUF_CNTL_MASK__SI 0x00000080L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_CRTC_EN_MASK__SI 0x00000001L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_DISP_EN_MASK__SI 0x00000002L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_MODE_EN_MASK__SI 0x00000004L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_OVERSCAN_COLOR_EN_MASK__SI 0x00000010L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_SYNC_POLARITY_SEL_MASK__SI 0x00000020L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_TIMING_SEL_MASK__SI 0x00000008L -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_V_SYNC_SEL_MASK__SI 0x00000040L -#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK__SI 0x00000001L -#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK__SI 0x00000010L -#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK__SI 0x00000001L -#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK__SI 0x1fff0000L -#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK__SI 0x00001fffL -#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK__SI 0x00000001L -#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK__SI 0x1fff0000L -#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK__SI 0x00001fffL -#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK__SI 0x00000001L -#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK__SI 0x1fff0000L -#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK__SI 0x00001fffL -#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK__SI 0x00000100L -#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK__SI 0x00001000L -#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK__SI 0xffff0000L -#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK__SI 0x00000010L -#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK__SI 0x00000001L -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK__SI 0x00000100L -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK__SI 0x00000010L -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK__SI 0x00000001L -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK__SI 0x00001000L -#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK__SI 0x00001fffL -#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK__SI 0x00001fffL -#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK__SI 0x00001fffL -#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK__SI 0x00000100L -#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK__SI 0x00000001L -#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK__CI__VI 0x001fffffL -#define CSPRIV_CONNECT__QUEUE_ID_MASK__CI__VI 0x00e00000L -#define CSPRIV_CONNECT__UNORD_DISP_MASK__CI__VI 0x80000000L -#define CSPRIV_CONNECT__VMID_MASK__CI__VI 0x3c000000L -#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK__CI__VI 0x0000001fL -#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK__CI__VI 0xffffffffL -#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK__CI__VI 0xffffffffL -#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK__CI__VI 0xffffffffL -#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK__CI__VI 0x10000000L -#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK__CI__VI 0x08000000L -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK__CI__VI 0x01000000L -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK__CI__VI 0x02000000L -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK__CI__VI 0x04000000L -#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK__CI__VI 0x00fff000L -#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK__CI__VI 0x00000fffL -#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -#define CURRENT_PG_STATUS__ACP_PG_status_MASK__CI__VI 0x00000001L -#define CURRENT_PG_STATUS__CHUB_PG_status_MASK__CI__VI 0x00001000L -#define CURRENT_PG_STATUS__DC_pipe0_PG_status_MASK__CI__VI 0x00000020L -#define CURRENT_PG_STATUS__DC_pipe1_PG_status_MASK__CI__VI 0x00000040L -#define CURRENT_PG_STATUS__DC_pipe2_PG_status_MASK__CI__VI 0x00000080L -#define CURRENT_PG_STATUS__DC_pipe3_PG_status_MASK__CI__VI 0x00000100L -#define CURRENT_PG_STATUS__DC_pipe4_PG_status_MASK__CI__VI 0x00000200L -#define CURRENT_PG_STATUS__DC_pipe5_PG_status_MASK__CI__VI 0x00000400L -#define CURRENT_PG_STATUS__IOMMU_PG_status_MASK__CI__VI 0x00000800L -#define CURRENT_PG_STATUS__MC_PG_status_MASK__CI__VI 0x00002000L -#define CURRENT_PG_STATUS__PCIE_PG_status_MASK__CI__VI 0x00000010L -#define CURRENT_PG_STATUS__SAM_PG_status_MASK__CI__VI 0x00000008L -#define CURRENT_PG_STATUS__SDMA_PG_status_MASK__CI__VI 0x00004000L -#define CURRENT_PG_STATUS__UVD_PG_status_MASK__CI__VI 0x00000004L -#define CURRENT_PG_STATUS__VCE_PG_status_MASK__CI__VI 0x00000002L -#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK__SI 0x000000ffL -#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK__SI 0x0000ff00L -#define CUR_COLOR1__CUR_COLOR1_RED_MASK__SI 0x00ff0000L -#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK__SI 0x000000ffL -#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK__SI 0x0000ff00L -#define CUR_COLOR2__CUR_COLOR2_RED_MASK__SI 0x00ff0000L -#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK__SI 0x00010000L -#define CUR_CONTROL__CURSOR_EN_MASK__SI 0x00000001L -#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK__SI 0x00100000L -#define CUR_CONTROL__CURSOR_MODE_MASK__SI 0x00000300L -#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK__SI 0x003f0000L -#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK__SI 0x0000003fL -#define CUR_POSITION__CURSOR_X_POSITION_MASK__SI 0x1fff0000L -#define CUR_POSITION__CURSOR_Y_POSITION_MASK__SI 0x00001fffL -#define CUR_SIZE__CURSOR_HEIGHT_MASK__SI 0x0000003fL -#define CUR_SIZE__CURSOR_WIDTH_MASK__SI 0x003f0000L -#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK__SI 0x000000ffL -#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK__SI 0xffffffffL -#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK__SI 0x01000000L -#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK__SI 0x00010000L -#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK__SI 0x00000001L -#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK__SI 0x00000002L -#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK__SI 0x00000001L -#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK__SI 0x00010000L -#define D1VGA_CONTROL__D1VGA_ROTATE_MASK__SI 0x03000000L -#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK__SI 0x00000200L -#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK__SI 0x00000100L -#define D1_PROTECTION__D1_DP_ENC_REQUIRED_MASK__SI 0x00000002L -#define D1_PROTECTION__D1_NO_DVO_OUT_MASK__SI 0x00000004L -#define D1_PROTECTION__D1_NO_LVDS_OUT_MASK__SI 0x00000010L -#define D1_PROTECTION__D1_NO_SDVO_OUT_MASK__SI 0x00000008L -#define D1_PROTECTION__D1_NO_VGA_OUT_MASK__SI 0x00000020L -#define D1_PROTECTION__D1_TMDS_ENC_REQUIRED_MASK__SI 0x00000001L -#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK__SI 0x00000001L -#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK__SI 0x00010000L -#define D2VGA_CONTROL__D2VGA_ROTATE_MASK__SI 0x03000000L -#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK__SI 0x00000200L -#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK__SI 0x00000100L -#define D2_PROTECTION__D2_DP_ENC_REQUIRED_MASK__SI 0x00000002L -#define D2_PROTECTION__D2_NO_DVO_OUT_MASK__SI 0x00000004L -#define D2_PROTECTION__D2_NO_LVDS_OUT_MASK__SI 0x00000010L -#define D2_PROTECTION__D2_NO_SDVO_OUT_MASK__SI 0x00000008L -#define D2_PROTECTION__D2_NO_VGA_OUT_MASK__SI 0x00000020L -#define D2_PROTECTION__D2_TMDS_ENC_REQUIRED_MASK__SI 0x00000001L -#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK__SI 0x00000001L -#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK__SI 0x00010000L -#define D3VGA_CONTROL__D3VGA_ROTATE_MASK__SI 0x03000000L -#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK__SI 0x00000200L -#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK__SI 0x00000100L -#define D3_PROTECTION__D3_DP_ENC_REQUIRED_MASK__SI 0x00000002L -#define D3_PROTECTION__D3_NO_DVO_OUT_MASK__SI 0x00000004L -#define D3_PROTECTION__D3_NO_LVDS_OUT_MASK__SI 0x00000010L -#define D3_PROTECTION__D3_NO_SDVO_OUT_MASK__SI 0x00000008L -#define D3_PROTECTION__D3_NO_VGA_OUT_MASK__SI 0x00000020L -#define D3_PROTECTION__D3_TMDS_ENC_REQUIRED_MASK__SI 0x00000001L -#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK__SI 0x00000001L -#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK__SI 0x00010000L -#define D4VGA_CONTROL__D4VGA_ROTATE_MASK__SI 0x03000000L -#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK__SI 0x00000200L -#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK__SI 0x00000100L -#define D4_PROTECTION__D4_DP_ENC_REQUIRED_MASK__SI 0x00000002L -#define D4_PROTECTION__D4_NO_DVO_OUT_MASK__SI 0x00000004L -#define D4_PROTECTION__D4_NO_LVDS_OUT_MASK__SI 0x00000010L -#define D4_PROTECTION__D4_NO_SDVO_OUT_MASK__SI 0x00000008L -#define D4_PROTECTION__D4_NO_VGA_OUT_MASK__SI 0x00000020L -#define D4_PROTECTION__D4_TMDS_ENC_REQUIRED_MASK__SI 0x00000001L -#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK__SI 0x00000001L -#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK__SI 0x00010000L -#define D5VGA_CONTROL__D5VGA_ROTATE_MASK__SI 0x03000000L -#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK__SI 0x00000200L -#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK__SI 0x00000100L -#define D5_PROTECTION__D5_DP_ENC_REQUIRED_MASK__SI 0x00000002L -#define D5_PROTECTION__D5_NO_DVO_OUT_MASK__SI 0x00000004L -#define D5_PROTECTION__D5_NO_LVDS_OUT_MASK__SI 0x00000010L -#define D5_PROTECTION__D5_NO_SDVO_OUT_MASK__SI 0x00000008L -#define D5_PROTECTION__D5_NO_VGA_OUT_MASK__SI 0x00000020L -#define D5_PROTECTION__D5_TMDS_ENC_REQUIRED_MASK__SI 0x00000001L -#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK__SI 0x00000001L -#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK__SI 0x00010000L -#define D6VGA_CONTROL__D6VGA_ROTATE_MASK__SI 0x03000000L -#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK__SI 0x00000200L -#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK__SI 0x00000100L -#define D6_PROTECTION__D6_DP_ENC_REQUIRED_MASK__SI 0x00000002L -#define D6_PROTECTION__D6_NO_DVO_OUT_MASK__SI 0x00000004L -#define D6_PROTECTION__D6_NO_LVDS_OUT_MASK__SI 0x00000010L -#define D6_PROTECTION__D6_NO_SDVO_OUT_MASK__SI 0x00000008L -#define D6_PROTECTION__D6_NO_VGA_OUT_MASK__SI 0x00000020L -#define D6_PROTECTION__D6_TMDS_ENC_REQUIRED_MASK__SI 0x00000001L -#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK__SI 0x000000ffL -#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK__SI 0x00000100L -#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK__SI 0x000000ffL -#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK__SI 0x0000ff00L -#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK__SI 0x00070000L -#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK__SI 0x0000ff00L -#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK__SI 0x00000003L -#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK__SI 0x00000001L -#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK__SI 0x00010000L -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK__SI 0x03000000L -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK__SI 0x00000010L -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK__SI 0x00030000L -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK__SI 0x00000300L -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK__SI 0x00000001L -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_COMPLETE_MASK__SI 0x10000000L -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_DACADJ_EN_MASK__SI 0x00000004L -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_EN_MASK__SI 0x00000002L -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_INITB_MASK__SI 0x00000001L -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_MASK_MASK__SI 0x00700000L -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_WAIT_ADJUST_MASK__SI 0x00003ff0L -#define DAC_BGADJ_CONTROL__DAC_BGADJ_SRC_MASK__SI 0x00000030L -#define DAC_BGADJ_CONTROL__DAC_BGADJ_TESTEN_MASK__SI 0x00000001L -#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK__SI 0x00040000L -#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK__SI 0x00000001L -#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK__SI 0x00000100L -#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK__SI 0x00020000L -#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK__SI 0x00010000L -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK__SI 0x00000002L -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK__SI 0x00000004L -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK__SI 0x00000001L -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK__SI 0x00000008L -#define DAC_CONTROL__DAC_DFORCE_EN_MASK__SI 0x00000001L -#define DAC_CONTROL__DAC_TV_ENABLE_MASK__SI 0x00000100L -#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK__SI 0x00010000L -#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK__SI 0x00000001L -#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK__SI 0x00000100L -#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK__SI 0x00010000L -#define DAC_CRC_EN__DAC_CRC_EN_MASK__SI 0x00000001L -#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK__SI 0x0000003fL -#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK__SI 0x0000003fL -#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK__SI 0x000003ffL -#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK__SI 0x000ffc00L -#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK__SI 0x3ff00000L -#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK__SI 0x000003ffL -#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK__SI 0x000ffc00L -#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK__SI 0x3ff00000L -#define DAC_DATA__DAC_DATA_MASK__SI 0x0000003fL -#define DAC_DEBUG1__DOUT_DAC_BLANKb_MASK__SI 0x00000002L -#define DAC_DEBUG1__DOUT_DAC_BLUE_MASK__SI 0x00000ffcL -#define DAC_DEBUG1__DOUT_DAC_GREEN_MASK__SI 0x003ff000L -#define DAC_DEBUG1__DOUT_DAC_PIXCLK_MASK__SI 0x00000001L -#define DAC_DEBUG1__DOUT_DAC_RED_MASK__SI 0xffc00000L -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_BGSLEEP_PU_OR_MASK__SI 0x00008000L -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_DAC_PIN_PD_OR_MASK__SI 0x00020000L -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_DAC_PIN_PU_OR_MASK__SI 0x00010000L -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_STATE_MASK__SI 0x00007000L -#define DAC_DEBUG2__DOUT_DAC_BDACPD_MASK__SI 0x04000000L -#define DAC_DEBUG2__DOUT_DAC_BGSLEEP_MASK__SI 0x02000000L -#define DAC_DEBUG2__DOUT_DAC_BLANKb_MASK__SI 0x00000002L -#define DAC_DEBUG2__DOUT_DAC_CAPTURE_START_MASK__SI 0x00000040L -#define DAC_DEBUG2__DOUT_DAC_DATA_SOURCE_ENABLED_MASK__SI 0x00200000L -#define DAC_DEBUG2__DOUT_DAC_DETECT_MASK__SI 0x20000000L -#define DAC_DEBUG2__DOUT_DAC_FIELD_NUMBER_MASK__SI 0x00000080L -#define DAC_DEBUG2__DOUT_DAC_GDACPD_MASK__SI 0x08000000L -#define DAC_DEBUG2__DOUT_DAC_HSYNC_EN_MASK__SI 0x00000008L -#define DAC_DEBUG2__DOUT_DAC_HSYNC_MASK__SI 0x00000004L -#define DAC_DEBUG2__DOUT_DAC_MON_2_MASK__SI 0x80000000L -#define DAC_DEBUG2__DOUT_DAC_MON_3_MASK__SI 0x40000000L -#define DAC_DEBUG2__DOUT_DAC_NBLANK_MASK__SI 0x00800000L -#define DAC_DEBUG2__DOUT_DAC_PEDESTAL_MASK__SI 0x01000000L -#define DAC_DEBUG2__DOUT_DAC_PIXCLK_MASK__SI 0x00000001L -#define DAC_DEBUG2__DOUT_DAC_PIXCLKa_MASK__SI 0x00400000L -#define DAC_DEBUG2__DOUT_DAC_RDACPD_MASK__SI 0x10000000L -#define DAC_DEBUG2__DOUT_DAC_SCLK_MASK__SI 0x00000800L -#define DAC_DEBUG2__DOUT_DAC_SOURCE_SEL_MASK__SI 0x00000600L -#define DAC_DEBUG2__DOUT_DAC_STEREOSYNC_MASK__SI 0x00000100L -#define DAC_DEBUG2__DOUT_DAC_VSYNC_EN_MASK__SI 0x00000020L -#define DAC_DEBUG2__DOUT_DAC_VSYNC_MASK__SI 0x00000010L -#define DAC_DEBUG2__DOUT_DAC_iBDACDET_from_macro_MASK__SI 0x00040000L -#define DAC_DEBUG2__DOUT_DAC_iGDACDET_from_macro_MASK__SI 0x00080000L -#define DAC_DEBUG2__DOUT_DAC_iRDACDET_from_macro_MASK__SI 0x00100000L -#define DAC_DEBUG3__DAC_DEBUG3_MASK__SI 0xffffffffL -#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK__SI 0xffffffffL -#define DAC_ENABLE__DAC_ENABLE_MASK__SI 0x00000001L -#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK__SI 0x000003ffL -#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK__SI 0x00000001L -#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK__SI 0x01000000L -#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK__SI 0x00000700L -#define DAC_MACRO_CNTL__DAC_ANALOG_MONITOR_MASK__SI 0x0f000000L -#define DAC_MACRO_CNTL__DAC_BANDGAP_ADJUSTMENT_MASK__SI 0x003f0000L -#define DAC_MACRO_CNTL__DAC_COREMON_MASK__SI 0x10000000L -#define DAC_MACRO_CNTL__DAC_WHITE_FINE_CONTROL_MASK__SI 0x00003f00L -#define DAC_MACRO_CNTL__DAC_WHITE_LEVEL_MASK__SI 0x00000003L -#define DAC_MASK__DAC_MASK_MASK__SI 0x000000ffL -#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK__SI 0x00000100L -#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK__SI 0x00010000L -#define DAC_POWERDOWN__DAC_POWERDOWN_MASK__SI 0x00000001L -#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK__SI 0x01000000L -#define DAC_PWR_CNTL__DAC_BG_MODE_MASK__SI 0x00000003L -#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK__SI 0x00030000L -#define DAC_R_INDEX__DAC_R_INDEX_MASK__SI 0x000000ffL -#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK__SI 0x00000007L -#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK__SI 0x00000008L -#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK__SI 0x00000007L -#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK__SI 0x00000001L -#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK__SI 0x00010000L -#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK__SI 0x00000100L -#define DAC_TEST_ENABLE__DAC_TEST_ENABLE_MASK__SI 0x00000001L -#define DAC_W_INDEX__DAC_W_INDEX_MASK__SI 0x000000ffL -#define DATA_FORMAT__ALLOW_REQ_MODE_1_2_MASK__SI 0x10000000L -#define DATA_FORMAT__ALWAYS_SCL_RTS_HI_MASK__SI 0x00000100L -#define DATA_FORMAT__INTERLEAVE_EN_MASK__SI 0x00000001L -#define DATA_FORMAT__PREFETCH_MASK__SI 0x00001000L -#define DATA_FORMAT__REQUEST_MODE_MASK__SI 0x03000000L -#define DATA_FORMAT__RESET_REQ_AT_EOL_MASK__SI 0x00000010L -#define DATA_FORMAT__SOF_READ_PT_MASK__SI 0x001f0000L -#define DBG_BUS_OUT1__DBG_BUS_OUT_MASK 0x00ffffffL -#define DBG_BUS_OUT1__DBG_CNTL_OUT_MASK 0x01000000L -#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK__CI 0x0000001eL -#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK__CI 0x00000001L -#define DBG_CHAIN_CONTROL__DBG_BLOCK_SEL_MASK 0x000000ffL -#define DBG_CHAIN_CONTROL__DBG_CHAN_SEL_MASK 0x00800000L -#define DBG_CHAIN_CONTROL__DBG_CONTROL_LOAD_MASK 0x01000000L -#define DBG_CHAIN_CONTROL__DBG_GROUP_SEL_MASK 0x0001f000L -#define DBG_CHAIN_CONTROL__DBG_MUX_SEL_MASK 0x00400000L -#define DBG_CHAIN_CONTROL__DBG_OUTPUT_SEL_MASK 0x00380000L -#define DBG_FBC_COMP_DEBUG__DBG_FBC_COMP_DEBUG_MASK__SI 0x00000fffL -#define DBG_FBC_CTL23__DBG_FBC_CTL2_MASK__SI 0x00000fffL -#define DBG_FBC_CTL23__DBG_FBC_CTL3_MASK__SI 0x00fff000L -#define DBG_FBC_DECOMP_CTL_DEBUG__DBG_FBC_DECOMP_CTL_DEBUG_MASK__SI 0x00000fffL -#define DBW_CHROMA_BOT_ADDR__DBW_UV_BOT_BASE_MASK__SI 0xffffffffL -#define DBW_CHROMA_TOP_ADDR__DBW_UV_TOP_BASE_MASK__SI 0xffffffffL -#define DBW_LUMA_BOT_ADDR__DBW_Y_BOT_BASE_MASK__SI 0xffffffffL -#define DBW_LUMA_TOP_ADDR__DBW_Y_TOP_BASE_MASK__SI 0xffffffffL -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000c00L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000c000L -#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L -#define DB_BUF_SIZE__HEIGHT_MASK__SI 0x0ff00000L -#define DB_BUF_SIZE__PITCH_MASK__SI 0x00000ff0L -#define DB_CF_DAT__DAT_MASK__SI 0x003fffffL -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000fL -#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x00fff000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L -#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK__CI__VI 0x00f00000L -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L -#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L -#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK__CI__VI 0x000f0000L -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK__CI__VI 0x0f000000L -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK__CI__VI 0xf0000000L -#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK__CI__VI 0x0000f000L -#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK__CI__VI 0x00000f00L -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001c00L -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000L -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003e0L -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001fL -#define DB_CTL__CTXT_FMT_MASK__SI 0x000000c0L -#define DB_CTL__DB_BIG_ENDIAN_MASK__SI 0x00000400L -#define DB_CTL__MEM_TIMEOUT_TIME_MASK__SI 0x0ff00000L -#define DB_CTL__NSG_MODE_MASK__SI 0x00000030L -#define DB_CTL__STANDARD_MASK__SI 0x0000000fL -#define DB_CTL__STD_VERSION_MASK__SI 0x0003c000L -#define DB_CTL__SW_MEM_RST_MASK__SI 0x10000000L -#define DB_CTL__SW_MRST_MASK__SI 0x40000000L -#define DB_CTL__SW_RRST_MASK__SI 0x20000000L -#define DB_CTL__SW_SRST_MASK__SI 0x80000000L -#define DB_CTL__TILE_FMT_MASK__SI 0x00001000L -#define DB_CTL__USE_DB_VC1_SP_CONTEXT_MASK__SI 0x00000800L -#define DB_CTL__UV_FMT_MASK__SI 0x00002000L -#define DB_CTL__VC1_PROFILE_MASK__SI 0x00000300L -#define DB_DBG_CTL__DBG_ALL_TOP_WRITES_MASK__SI 0x00000004L -#define DB_DBG_CTL__DBG_DIS_STAGEA_MASK__SI 0x00000001L -#define DB_DBG_CTL__DBG_DIS_STAGEB_MASK__SI 0x00000002L -#define DB_DBG_STAT__STATE_DBFSM_MASK__SI 0x0000001fL -#define DB_DBG_STAT__TEST_DEBUG_REG_MASK__SI 0x0007ffe0L -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L -#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003e00L -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L -#define DB_DEBUG2__DISABLE_HTILE_BASE_MATCH_STATE_LOAD_MASK__SI 0x40000000L -#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L -#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x00000100L -#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x00000020L -#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x00000080L -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK__CI__VI 0x40000000L -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK__SI 0x80000000L -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK__CI__VI 0x80000000L -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L -#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x00000040L -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK__CI__VI 0x00010000L -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK__SI 0x00020000L -#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK__CI 0xc0000000L -#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK__SI 0xfc000000L -#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK__CI__VI 0x02000000L -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK__CI__VI 0x01000000L -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK__CI__VI 0x00100000L -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK__SI 0x00200000L -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK__CI__VI 0x00002000L -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK__SI 0x00004000L -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK__CI__VI 0x00008000L -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK__SI 0x00010000L -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK__CI__VI 0x00004000L -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK__SI 0x00008000L -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK__CI__VI 0x00040000L -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK__SI 0x00080000L -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK__CI__VI 0x00001000L -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK__SI 0x00002000L -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK__CI__VI 0x08000000L -#define DB_DEBUG3__DISABLE_PC_WC_ZF_COLLISION_DETECTION_FIX_MASK__SI 0x01000000L -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK__CI__VI 0x00800000L -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK__CI__VI 0x00000400L -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK__SI 0x00000800L -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK__CI__VI 0x00000200L -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK__SI 0x00000400L -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK__CI__VI 0x00080000L -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK__SI 0x00100000L -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L -#define DB_DEBUG3__DISALLOW_REG_READS_IF_HARVESTED_MASK__SI 0x02000000L -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK__CI__VI 0x20000000L -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK__CI__VI 0x10000000L -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK__CI__VI 0x04000000L -#define DB_DEBUG3__ENABLE_HIZ_TILE_ZRANGE_FOR_SRC_QTILES_MASK__SI 0x00000200L -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK__CI__VI 0x00000800L -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK__SI 0x00001000L -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK__CI__VI 0x00200000L -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK__SI 0x00400000L -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK__CI__VI 0x00400000L -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK__SI 0x00800000L -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L -#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK__CI__VI 0x00020000L -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK__SI 0x00040000L -#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK__CI 0xfffffff0L -#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK__SI__VI 0xffffffc0L -#define DB_DEBUG4__DISABLE_PARTIAL_CONVERTED_FROM_SINGLE_FIX_MASK__SI 0x00000010L -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK__CI__VI 0x00000008L -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK__SI 0x00000020L -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L -#define DB_DEBUG4__DISABLE_REZ_SINGLE_STENCIL_FIX_MASK__SI 0x00000008L -#define DB_DEBUG_INT_STAT__CTXT_TIMEOUT_MASK__SI 0x00000008L -#define DB_DEBUG_INT_STAT__DBFSM_DONE_MASK__SI 0x00000001L -#define DB_DEBUG_INT_STAT__ERRDET_MASK__SI 0x00000010L -#define DB_DEBUG_INT_STAT__MEM_TIMEOUT_MASK__SI 0x00000004L -#define DB_DEBUG_INT_STAT__PKT_ERR_MASK__SI 0x00000002L -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000c00L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0f000000L -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L -#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L -#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L -#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L -#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L -#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L -#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffffL -#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffffL -#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L -#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L -#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L -#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L -#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L -#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L -#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0x0000000fL -#define DB_DEPTH_INFO__ARRAY_MODE_MASK__CI__VI 0x000000f0L -#define DB_DEPTH_INFO__BANK_HEIGHT_MASK__CI__VI 0x00018000L -#define DB_DEPTH_INFO__BANK_WIDTH_MASK__CI__VI 0x00006000L -#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK__CI__VI 0x00060000L -#define DB_DEPTH_INFO__NUM_BANKS_MASK__CI__VI 0x00180000L -#define DB_DEPTH_INFO__PIPE_CONFIG_MASK__CI__VI 0x00001f00L -#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x003ff800L -#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x000007ffL -#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x003fffffL -#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007ffL -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L -#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L -#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L -#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L -#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L -#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L -#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L -#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_CB_REPVAL_MASK__SI 0x00000ff0L -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_CR_REPVAL_MASK__SI 0x000ff000L -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_FADE_BLACK_MASK__SI 0x00000008L -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_MODE_MASK__SI 0x00000007L -#define DB_ERRDET_CONTROL__ERR_AIDB_ENABLE_MASK__SI 0x02000000L -#define DB_ERRDET_CONTROL__ERR_AIDB_THRESH_MASK__SI 0x0000ffffL -#define DB_ERRDET_CONTROL__ERR_CONCEAL_ENABLE_MASK__SI 0x04000000L -#define DB_ERRDET_CONTROL__ERR_GREY_THRESH_MASK__SI 0x01ff0000L -#define DB_ERRDET__ERR_FOUND_MASK__SI 0x00010000L -#define DB_ERRDET__ERR_TYPE_MASK__SI 0x00020000L -#define DB_ERRDET__ERR_X_COORD_MASK__SI 0x000000ffL -#define DB_ERRDET__ERR_Y_COORD_MASK__SI 0x0000ff00L -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000L -#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000fc00L -#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x0000001fL -#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x000003e0L -#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001f0000L -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000ffL -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007f00L -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01ff8000L -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000L -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007fL -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x01e00000L -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003f80L -#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x001fc000L -#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000L -#define DB_GREY_LEVELS__CBCR_HI_MASK__SI 0x0000ff00L -#define DB_GREY_LEVELS__CBCR_LO_MASK__SI 0x000000ffL -#define DB_GREY_LEVELS__LUMA_HI_MASK__SI 0xff000000L -#define DB_GREY_LEVELS__LUMA_LO_MASK__SI 0x00ff0000L -#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffffL -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L -#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L -#define DB_HTILE_SURFACE__LINEAR_MASK 0x00000001L -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000fc00L -#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003f0L -#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L -#define DB_HW_DEBUG__DB_HW_DEBUG_MASK__SI 0xffffffffL -#define DB_INTRA_HOR_ADR__INTRA_HOR_ADR_MASK__SI 0xffffffc0L -#define DB_INT_EN__CTXT_TIMEOUT_EN_MASK__SI 0x00000008L -#define DB_INT_EN__DBFSM_DONE_EN_MASK__SI 0x00000001L -#define DB_INT_EN__ERRDET_EN_MASK__SI 0x00000010L -#define DB_INT_EN__MEM_TIMEOUT_EN_MASK__SI 0x00000004L -#define DB_INT_EN__PKT_ERR_EN_MASK__SI 0x00000002L -#define DB_INT_STAT__CTXT_TIMEOUT_MASK__SI 0x00000008L -#define DB_INT_STAT__DBFSM_DONE_MASK__SI 0x00000001L -#define DB_INT_STAT__ERRDET_MASK__SI 0x00000010L -#define DB_INT_STAT__MEM_TIMEOUT_MASK__SI 0x00000004L -#define DB_INT_STAT__PKT_ERR_MASK__SI 0x00000002L -#define DB_LMA_ADR__ADR_MASK__SI 0x000000ffL -#define DB_LMA_CTL__ACCESS_MODE_MASK__SI 0x00000001L -#define DB_LMA_CTL__AUTO_INC_MASK__SI 0x00000040L -#define DB_LMA_CTL__MEMORY_SELECT_MASK__SI 0x0000003eL -#define DB_LMA_DAT__DAT_MASK__SI 0xffffffffL -#define DB_LUMA_ADR__LUMA_ADR_MASK__SI 0xffffffc0L -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK__CI__VI 0x7fffffffL -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK__CI__VI 0xffffffffL -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK__CI__VI 0x7fffffffL -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK__CI__VI 0xffffffffL -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK__CI__VI 0x7fffffffL -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK__CI__VI 0xffffffffL -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK__CI__VI 0x7fffffffL -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK__CI__VI 0xffffffffL -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00ff0000L -#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000L -#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000ffL -#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000ff00L -#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffffL -#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffffL -#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffffL -#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffffL -#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffffL -#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L -#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000f00L -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L -#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L -#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK__CI__VI 0x00800000L -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK__CI__VI 0x001c0000L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK__CI__VI 0x00038000L -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK__CI__VI 0x00007000L -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001cL -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK__CI__VI 0x00400000L -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK__CI__VI 0x00200000L -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK__CI__VI 0x00000800L -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000cL -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L -#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03e00000L -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L -#define DB_RING_CONTROL__COUNTER_CONTROL_MASK__CI__VI 0x00000003L -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L -#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L -#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L -#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L -#define DB_SLICE_INFO__LOOPFILTER_MASK__SI 0x00002000L -#define DB_SLICE_INFO__MBAFF_FRAME_FLAG_MASK__SI 0x00000040L -#define DB_SLICE_INFO__PICTURE_STRUCTURE_MASK__SI 0x00000038L -#define DB_SLICE_INFO__PQUANT_MASK__SI 0x00001f80L -#define DB_SLICE_INFO__SLICE_TYPE_MASK__SI 0x00000007L -#define DB_SPS_INFO__CHROMA_FORMAT_IDC_MASK__SI 0x00200000L -#define DB_SPS_INFO__MAX_X_MB_MASK__SI 0x00000ff0L -#define DB_SPS_INFO__MAX_Y_MB_MASK__SI 0x000ff000L -#define DB_SRAM_RM_CTL__DB_M032X064R2M01S00_RME_MASK__SI 0x00000010L -#define DB_SRAM_RM_CTL__DB_M032X064R2M01S00_RM_MASK__SI 0x0000000fL -#define DB_SRAM_RM_CTL__DB_M088X064R2M01S00_RME_MASK__SI 0x00004000L -#define DB_SRAM_RM_CTL__DB_M088X064R2M01S00_RM_MASK__SI 0x00003c00L -#define DB_SRAM_RM_CTL__DB_M096X032R2M02S00_RME_MASK__SI 0x00000200L -#define DB_SRAM_RM_CTL__DB_M096X032R2M02S00_RM_MASK__SI 0x000001e0L -#define DB_SRAM_RM_CTL__DB_WRM_MASK__SI 0x00078000L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000ff000L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000ff0L -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000ff000L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000ff0L -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L -#define DB_STAT__BUSY_MASK__SI 0x00000001L -#define DB_STAT__MEM_BUSY_MASK__SI 0x00000002L -#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000L -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000ffL -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L -#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L -#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000L -#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000ffL -#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L -#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000ffL -#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000f000L -#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000fL -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00f00000L -#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000f00L -#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000f0000L -#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000f0L -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L -#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x00700000L -#define DB_STENCIL_INFO__TILE_SPLIT_MASK__CI__VI 0x0000e000L -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L -#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffffL -#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffffL -#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L -#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000c0000L -#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L -#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000cL -#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L -#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000c0L -#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L -#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000c00L -#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L -#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000c000L -#define DB_TOP_Y_PIC__TOP_Y_PIC_MASK__SI 0x000000ffL -#define DB_UPROC_STAT__PKT_COUNT_MASK__SI 0x000000ffL -#define DB_UPROC_STAT__PKT_LEVEL_MASK__SI 0x00000f00L -#define DB_UPROC_STAT__PKT_OFLOW_MASK__SI 0x00001000L -#define DB_UPROC_STAT__PKT_UFLOW_MASK__SI 0x00002000L -#define DB_VC1_SP_CONTEXT__INTRA_CURR_MASK__SI 0x0000007eL -#define DB_VC1_SP_CONTEXT__INTRA_TOP_MASK__SI 0x00000780L -#define DB_VC1_SP_CONTEXT__INTRA_ULEFT_MASK__SI 0x00007800L -#define DB_VC1_SP_CONTEXT__OVERLAP_MASK__SI 0x00000001L -#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L -#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x07f00000L -#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007e0L -#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001fL -#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000f8000L -#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x08000000L -#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L -#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000L -#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000L -#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffffL -#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffffL -#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_Z_INFO__FORMAT_MASK 0x00000003L -#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000cL -#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L -#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x00700000L -#define DB_Z_INFO__TILE_SPLIT_MASK__CI__VI 0x0000e000L -#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L -#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L -#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffffL -#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffffL -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_BASE_MASK__SI 0x00100000L -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_DIV_MASK__SI 0x70000000L -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_EN_MASK__SI 0x00010000L -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_MULTI_MASK__SI 0x03000000L -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_FS_DIV_SEL_MASK__SI 0x00000070L -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK__SI 0x00000008L -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_WALLCLOCK_RATIO_MASK__SI 0x00000003L -#define DCCG_AUDIO_DTO0_LOAD__DCCG_AUDIO_DTO0_LOAD_MASK__SI 0x80000000L -#define DCCG_AUDIO_DTO0_LOAD__DCCG_AUDIO_DTO0_LOAD_VALUE_MASK__SI 0x00ffffffL -#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK__SI 0x00ffffffL -#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK__SI 0x00ffffffL -#define DCCG_AUDIO_DTO_SELECT__DCCG_AUDIO_DTO_SEL_MASK__SI 0x00000007L -#define DCCG_CG_PLL_PIXCLK_SEL__DCCG_CG_PLL_PIXCLK_SEL_MASK__SI 0x00000001L -#define DCCG_DEBUG_01__IDA0_P1PLL_FB_DIV_CHANGED_MASK__SI 0x00000008L -#define DCCG_DEBUG_01__IDA0_P1PLL_FB_DIV_CONV_MASK__SI 0x00fff000L -#define DCCG_DEBUG_01__IDA0_P1PLL_FB_DIV_FRACT_CONV_MASK__SI 0x0f000000L -#define DCCG_DEBUG_01__IDA0_P1PLL_HSYNC_MASK__SI 0x10000000L -#define DCCG_DEBUG_01__IDA0_P1PLL_REF_DIV_CHANGED_MASK__SI 0x00000004L -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_ACK_MASK__SI 0x00000200L -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_CURRENT_STATE_MASK__SI 0x00000060L -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_ENABLE_MASK__SI 0x00000080L -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_PENDING_MASK__SI 0x00000010L -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_REQ_MASK__SI 0x00000100L -#define DCCG_DEBUG_01__IDA0_P1PLL_VGA_TIMING_MODE_MASK__SI 0x00000002L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_12_MASK__SI 0x00001000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_13_MASK__SI 0x00002000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_ANTI_RUN_CLK_MASK__SI 0x20000000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_B_PCOUNT_MASK__SI 0x04000000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_B_PVCO_CAL1_MASK__SI 0x08000000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_B_PVCO_CAL2_MASK__SI 0x10000000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_PLL_CALIB_DONE_MASK__SI 0x02000000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_DIVUP_UPDATE_ACK_MASK__SI 0x00000200L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_DIVUP_UPDATE_REQ_MASK__SI 0x00000100L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_ALLOW_UPDATE_MASK__SI 0x00080000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_CURRENT_STATE_MASK__SI 0x00070000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_SLIP_ACK_FRACT_FB_MASK__SI 0x00008000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_START_SLIP_FRACT_FB_MASK__SI 0x00004000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_HSYNC_DIV_DONE_MASK__SI 0x00200000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_HSYNC_MASK__SI 0x00400000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_POST_DIV_VAL0_MASK__SI 0x00100000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_PPLL_HSYNC_MASK__SI 0x00800000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_STATE_MASK__SI 0x01000000L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_REFDIV_PLL_LOCKED_REG_MASK__SI 0x00000400L -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_REFDIV_SAFE_TO_UPDATE_MASK__SI 0x00000800L -#define DCCG_DEBUG_02__IDA1_P1PLL_PFD_DOWN_MASK__SI 0x80000000L -#define DCCG_DEBUG_02__IDA1_P1PLL_PFD_UP_MASK__SI 0x40000000L -#define DCCG_DEBUG_03__IDA2_P2PLL_FB_DIV_CHANGED_MASK__SI 0x00000008L -#define DCCG_DEBUG_03__IDA2_P2PLL_FB_DIV_CONV_MASK__SI 0x00fff000L -#define DCCG_DEBUG_03__IDA2_P2PLL_FB_DIV_FRACT_CONV_MASK__SI 0x0f000000L -#define DCCG_DEBUG_03__IDA2_P2PLL_HSYNC_MASK__SI 0x10000000L -#define DCCG_DEBUG_03__IDA2_P2PLL_REF_DIV_CHANGED_MASK__SI 0x00000004L -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_ACK_MASK__SI 0x00000200L -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_CURRENT_STATE_MASK__SI 0x00000060L -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_ENABLE_MASK__SI 0x00000080L -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_PENDING_MASK__SI 0x00000010L -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_REQ_MASK__SI 0x00000100L -#define DCCG_DEBUG_03__IDA2_P2PLL_VGA_TIMING_MODE_MASK__SI 0x00000002L -#define DCCG_DEBUG_04__IDA1_P2PLL_DEBUG_12_MASK__SI 0x00001000L -#define DCCG_DEBUG_04__IDA1_P2PLL_DEBUG_13_MASK__SI 0x00002000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_ANTI_RUN_CLK_MASK__SI 0x20000000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_B_PCOUNT_MASK__SI 0x04000000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_B_PVCO_CAL1_MASK__SI 0x08000000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_B_PVCO_CAL2_MASK__SI 0x10000000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_PLL_CALIB_DONE_MASK__SI 0x02000000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_DIVUP_UPDATE_ACK_MASK__SI 0x00000200L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_DIVUP_UPDATE_REQ_MASK__SI 0x00000100L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_ALLOW_UPDATE_MASK__SI 0x00080000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_CURRENT_STATE_MASK__SI 0x00070000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_SLIP_ACK_FRACT_FB_MASK__SI 0x00008000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_START_SLIP_FRACT_FB_MASK__SI 0x00004000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_HSYNC_DIV_DONE_MASK__SI 0x00200000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_HSYNC_MASK__SI 0x00400000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_POST_DIV_VAL0_MASK__SI 0x00100000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_PPLL_HSYNC_MASK__SI 0x00800000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_STATE_MASK__SI 0x01000000L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_REFDIV_PLL_LOCKED_REG_MASK__SI 0x00000400L -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_REFDIV_SAFE_TO_UPDATE_MASK__SI 0x00000800L -#define DCCG_DEBUG_04__IDA3_P2PLL_PFD_DOWN_MASK__SI 0x80000000L -#define DCCG_DEBUG_04__IDA3_P2PLL_PFD_UP_MASK__SI 0x40000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_PRE_RUN_MASK__SI 0x00000010L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_RUN_MASK__SI 0x00000040L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_RUN_REG_MASK__SI 0x00000020L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_SRC_MUX_SEL_MASK__SI 0x00000001L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_GLITCH_END_MASK__SI 0x00000008L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_SRC_SEL_CHANGE_MASK__SI 0x00000002L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_STOP_FOR_GLITCH_MASK__SI 0x00000004L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_PRE_RUN_MASK__SI 0x00000800L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_RUN_MASK__SI 0x00002000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_RUN_REG_MASK__SI 0x00001000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_SRC_MUX_SEL_MASK__SI 0x00000080L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_GLITCH_END_MASK__SI 0x00000400L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_SRC_SEL_CHANGE_MASK__SI 0x00000100L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_STOP_FOR_GLITCH_MASK__SI 0x00000200L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_DEFAULT_MVP_CLK_A_MASK__SI 0x00080000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_DEFAULT_MVP_CLK_B_MASK__SI 0x08000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_A_DUPLICATE_MASK__SI 0x01000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_A_MASK__SI 0x00010000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_B_DUPLICATE_MASK__SI 0x02000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_B_MASK__SI 0x00020000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MULTI_CHAIN_SCAN_MODE_MASK__SI 0x00008000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_A_MASK__SI 0x00800000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_A_MUX_SEL_MASK__SI 0x00600000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_B_MASK__SI 0x80000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_B_MUX_SEL_MASK__SI 0x60000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_PCLK_CRTC1_DUPLICATE_MASK__SI 0x10000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_PCLK_CRTC1_MASK__SI 0x00100000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_SINGLE_CHAIN_SCAN_MODE_MASK__SI 0x00004000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_TEST_TCK_DUPLICATE_MASK__SI 0x04000000L -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_TEST_TCK_MASK__SI 0x00040000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_DACA_CLK_SRC_MASK__SI 0x00000100L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_DACB_CLK_SRC_MASK__SI 0x00000800L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_DVOA_CLK_SRC_MASK__SI 0x00800000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_HDMI0_CLK_SRC_MASK__SI 0x00100000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_HDMI1_CLK_SRC_MASK__SI 0x04000000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_LVTMA_CLK_SRC_MASK__SI 0x00010000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC1_CLOCK_ON_MASK__SI 0x00000008L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC1_ENABLE_IN_TV_MODE_MASK__SI 0x00000004L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC1_ENABLE_MASK__SI 0x00000001L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC2_CLOCK_ON_MASK__SI 0x00000080L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC2_ENABLE_IN_TV_MODE_MASK__SI 0x00000040L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC2_ENABLE_MASK__SI 0x00000010L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACA_CLOCK_ON_MASK__SI 0x00000400L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACA_ENABLE_MASK__SI 0x00000200L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACB_CLOCK_ON_MASK__SI 0x00002000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACB_ENABLE_MASK__SI 0x00001000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DVOA_CLOCK_ON_MASK__SI 0x02000000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DVOA_ENABLE_MASK__SI 0x01000000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI0_CLOCK_ON_MASK__SI 0x00400000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI0_ENABLE_MASK__SI 0x00200000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI1_CLOCK_ON_MASK__SI 0x10000000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI1_ENABLE_MASK__SI 0x08000000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_LVTMA_CLOCK_ON_MASK__SI 0x00080000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_LVTMA_ENABLE_MASK__SI 0x00020000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_TMDSA_CLOCK_ON_MASK__SI 0x00040000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_TMDSA_ENABLE_MASK__SI 0x00008000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_TMDSA_CLK_SRC_MASK__SI 0x00004000L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_TVCLK_CRTC1_ENABLE_MASK__SI 0x00000002L -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_TVCLK_CRTC2_ENABLE_MASK__SI 0x00000020L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_G_SCL1_CLOCK_ON_MASK__SI 0x00000200L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_G_SCL2_CLOCK_ON_MASK__SI 0x00000800L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_R_CLOCK_ON_MASK__SI 0x00000020L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_R_RBBMIF_CLOCK_ON_MASK__SI 0x00000008L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_R_TVOUT_CLOCK_ON_MASK__SI 0x00000080L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_DISP_CLK_SCL1_BUSY_MASK__SI 0x00000100L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_DISP_CLK_SCL2_BUSY_MASK__SI 0x00000400L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_REGCLK_DISP_BUSY_MASK__SI 0x00000010L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_REGCLK_TVOUT_BUSY_MASK__SI 0x00000040L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_PM_DISABLE_MASK__SI 0x00000001L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_RBBM_REGCLK_ACTIVE_MASK__SI 0x00000002L -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_R_RBBMIF_BUSY_MASK__SI 0x00000004L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_DISPOUT_SOFT_RESET_MASK__SI 0x00000400L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_G_SCL1_RST_MASK__SI 0x00000040L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_G_SCL2_RST_MASK__SI 0x00000200L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_ALU_RST_MASK__SI 0x00000008L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_DCO_RST_MASK__SI 0x00000001L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_DISPOUT_RST_MASK__SI 0x00000800L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_SCL1_RST_MASK__SI 0x00000020L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_SCL2_RST_MASK__SI 0x00000100L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_R_RBBMIF_RST_MASK__SI 0x00001000L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_R_RST_MASK__SI 0x00002000L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_R_TVOUT_RST_MASK__SI 0x00000002L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_SCALER_ALU_SOFT_RESET_MASK__SI 0x00000004L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_SCL1_SOFT_RESET_MASK__SI 0x00000010L -#define DCCG_DEBUG_08__IDA7_DISP_CLK_SCL2_SOFT_RESET_MASK__SI 0x00000080L -#define DCCG_DEBUG_08__IDA7_PCLK_HDMI1_RST_MASK__SI 0x00010000L -#define DCCG_DEBUG_08__IDA7_PCLK_HDMI1_SOFT_RESET_MASK__SI 0x00008000L -#define DCCG_DEBUG_08__IDA7_RBBM_DISP_SOFT_RESET_MASK__SI 0x00004000L -#define DCCG_DEBUG_09__IDA8_DVO_EN_MASK__SI 0x08000000L -#define DCCG_DEBUG_09__IDA8_DVO_ON_COUNT_MASK__SI 0x70000000L -#define DCCG_DEBUG_09__IDA8_DVO_SETTINGS_CHANGED_MASK__SI 0x00800000L -#define DCCG_DEBUG_09__IDA8_DVO_SETTING_COUNT_MASK__SI 0x07000000L -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC1_RST_MASK__SI 0x00001000L -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC1_SOFT_RESET_MASK__SI 0x00000001L -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC2_RST_MASK__SI 0x00002000L -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC2_SOFT_RESET_MASK__SI 0x00000002L -#define DCCG_DEBUG_09__IDA8_PCLK_DACA_RST_MASK__SI 0x00004000L -#define DCCG_DEBUG_09__IDA8_PCLK_DACA_SOFT_RESET_MASK__SI 0x00000004L -#define DCCG_DEBUG_09__IDA8_PCLK_DACB_RST_MASK__SI 0x00008000L -#define DCCG_DEBUG_09__IDA8_PCLK_DACB_SOFT_RESET_MASK__SI 0x00000008L -#define DCCG_DEBUG_09__IDA8_PCLK_DVOA_RST_MASK__SI 0x00200000L -#define DCCG_DEBUG_09__IDA8_PCLK_DVOA_SOFT_RESET_MASK__SI 0x00000200L -#define DCCG_DEBUG_09__IDA8_PCLK_HDMI0_RST_MASK__SI 0x00100000L -#define DCCG_DEBUG_09__IDA8_PCLK_HDMI0_SOFT_RESET_MASK__SI 0x00000100L -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_DSYNC_RST_MASK__SI 0x00080000L -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_DSYNC_SOFT_RESET_MASK__SI 0x00000080L -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_RST_MASK__SI 0x00040000L -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_SOFT_RESET_MASK__SI 0x00000040L -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_DSYNC_RST_MASK__SI 0x00020000L -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_DSYNC_SOFT_RESET_MASK__SI 0x00000020L -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_RST_MASK__SI 0x00010000L -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_SOFT_RESET_MASK__SI 0x00000010L -#define DCCG_DEBUG_09__IDA8_PIX1CLK_RST_MASK__SI 0x00000400L -#define DCCG_DEBUG_09__IDA8_PIX2CLK_RST_MASK__SI 0x00000800L -#define DCCG_DEBUG_09__IDA8_RST_DVOCLK_D_MASK__SI 0x00400000L -#define DCCG_DEBUG_09__IDA8_SOFT_RST_DVOCLK_MASK__SI 0x80000000L -#define DCCG_DEBUG_10__IDA9_CLK_RESET_DVOCLK_RESET_MASK__SI 0x00001000L -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_A_MASK__SI 0x00008000L -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_A_RST_MASK__SI 0x00004000L -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_B_MASK__SI 0x00040000L -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_B_RST_MASK__SI 0x00020000L -#define DCCG_DEBUG_10__IDA9_CLK_RESET_PRE_MVP_CLK_A_RST_MASK__SI 0x00002000L -#define DCCG_DEBUG_10__IDA9_CLK_RESET_PRE_MVP_CLK_B_RST_MASK__SI 0x00010000L -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_CLK_SRC_SEL_MASK__SI 0x00000001L -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLKC_IN_PHASE_MASK__SI 0x00000004L -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLKD_IN_PHASE_MASK__SI 0x00000008L -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLK_C_CLOCK_ON_MASK__SI 0x00000010L -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLK_D_CLOCK_ON_MASK__SI 0x00000020L -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_SINGLE_CHANNEL_DDR_MASK__SI 0x00000002L -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_TEST_MODE_MASK__SI 0x00000040L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_DENOMINATOR_COUNT_MASK__SI 0xff000000L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_DTO_EN_MASK__SI 0x00000010L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_PCLK_TV_RST_MASK__SI 0x00000008L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_CLK_SRC_SEL_MASK__SI 0x00000004L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_DATA_SRC_SEL_MASK__SI 0x00000001L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_EN_MASK__SI 0x00000002L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_VCLK_EN_MASK__SI 0x00000020L -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_UPSAMPLER_PHASE_MASK__SI 0x00ff0000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_CLOCKING_MODE_MASK__SI 0x03000000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_ONE_SHOT_STOP_MASK__SI 0x00000004L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_RUN_CLK_MASK__SI 0x00000002L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_RUN_CLOCK_COUNT_MASK__SI 0x00000ff0L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_TRIGGER_EVENT_OCCURRED_MASK__SI 0x00000008L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_WTRIG_PRE_DCCG_ONE_SHOT_RUN_CLK_MASK__SI 0x08000000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_WTRIG_RUN_CLK_CURRENT_CLK_MASK__SI 0x00000001L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_ONE_SHOT_STOP_MASK__SI 0x00004000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_RUN_CLK_MASK__SI 0x00002000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_RUN_CLOCK_COUNT_MASK__SI 0x00ff0000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_TRIGGER_EVENT_OCCURRED_MASK__SI 0x00008000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_WTRIG_PRE_DCCG_ONE_SHOT_RUN_CLK_MASK__SI 0x20000000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_WTRIG_RUN_CLK_CURRENT_CLK_MASK__SI 0x00001000L -#define DCCG_DEBUG_12__IDAB_ONESHOT_TRIGGER_EN_MASK__SI 0x04000000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC_COARSE_SKEW_MASK__SI 0x03c00000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC_DLY_0_MASK__SI 0x20000000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC_FINE_SKEW_MASK__SI 0x1c000000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC_MASK__SI 0x40000000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD_COARSE_SKEW_MASK__SI 0x0000000fL -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD_DLY_0_MASK__SI 0x00000080L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD_FINE_SKEW_MASK__SI 0x00000070L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD_MASK__SI 0x00000100L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_COARSE_ADJUST_EN_MASK__SI 0x00000400L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_COARSE_SKEW_MASK__SI 0x0000f000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_DLY_0_MASK__SI 0x00100000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_FINE_ADJUST_EN_MASK__SI 0x00000800L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_FINE_SKEW_MASK__SI 0x00070000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_IN_PHASE_MASK__SI 0x00080000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_MASK__SI 0x00200000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_TST_DVOCLK_DUPLICATE_MASK__SI 0x80000000L -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_TST_DVOCLK_MASK__SI 0x00000200L -#define DCCG_DEBUG_BLOCK_ID__DCCG_DEBUG_BLOCK_ID_MASK__SI 0xffffffffL -#define DCCG_DEBUG__DCCG_DEBUG_MASK__SI 0xffffffffL -#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK__SI 0x00000010L -#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK__SI 0x00000020L -#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK__SI 0x00000001L -#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK__SI 0x00000002L -#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK__SI 0x00000040L -#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK__SI 0x00010000L -#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK__SI 0x00000100L -#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK__SI 0x00000200L -#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK__SI 0x00000400L -#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK__SI 0x00000800L -#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK__SI 0x00001000L -#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK__SI 0x00002000L -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK__SI 0x00010000L -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK__SI 0x000000ffL -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK__SI 0x01000000L -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK__SI 0x0000ff00L -#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK__SI 0x00000001L -#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK__SI 0xffffffffL -#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK__SI 0xffffffffL -#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK__SI 0xffffffffL -#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK__SI 0xffffffffL -#define DCDEBUG_DATA_TRIGGER_MASK__DCDEBUG_DATA_TRIGGER_MASK_MASK__SI 0xffffffffL -#define DCDEBUG_DATA_TRIGGER_PATTERN__DCDEBUG_DATA_TRIGGER_PATTERN_MASK__SI 0xffffffffL -#define DCDEBUG_EDGE_TRIGGER_MASK__DCDEBUG_EDGE_TRIGGER_MASK_MASK__SI 0xffffffffL -#define DCDEBUG_EDGE_TRIGGER_PATTERN__DCDEBUG_EDGE_TRIGGER_PATTERN_MASK__SI 0xffffffffL -#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK__SI 0x0000001fL -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK__SI 0x00000020L -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK__SI 0x00000040L -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK__SI 0x00300000L -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK__SI 0x00000080L -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK__SI 0x000fff00L -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK__SI 0x00001000L -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK__SI 0x0000000fL -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK__SI 0x000001f0L -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK__SI 0x10000000L -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK__SI 0x000f0000L -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK__SI 0x01f00000L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_EXTERNAL_TRIGGER_IN_EN_MASK__SI 0x00010000L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_EXTERNAL_TRIGGER_IN_PIN_MASK__SI 0x00f00000L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_EXTERNAL_TRIGGER_IN_POL_MASK__SI 0x00020000L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_EN_MASK__SI 0x00000001L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_INT_EN_MASK__SI 0x00000100L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_ONE_SHOT_CLOCK_MASK__SI 0x00000030L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_STATUS_OUT_EN_MASK__SI 0x01000000L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_STATUS_OUT_PIN_MASK__SI 0xf0000000L -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_STATUS_OUT_POL_MASK__SI 0x02000000L -#define DCDEBUG_TRIGGER_STAT__DCDEBUG_TRIGGER_ACK_MASK__SI 0x00000002L -#define DCDEBUG_TRIGGER_STAT__DCDEBUG_TRIGGER_STATUS_MASK__SI 0x00000001L -#define DCDEBUG_TRIGGER_STAT__DCDEBUG_TRIGGER_STATUS_STICKY_MASK__SI 0x00000010L -#define DCFE0_CLOCK_ENABLE__DCFE0_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DCFE1_CLOCK_ENABLE__DCFE1_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DCFE2_CLOCK_ENABLE__DCFE2_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DCFE3_CLOCK_ENABLE__DCFE3_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DCFE4_CLOCK_ENABLE__DCFE4_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DCFE5_CLOCK_ENABLE__DCFE5_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK__SI 0x00008000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK__SI 0x00004000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK__SI 0x00002000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK__SI 0x00100000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK__SI 0x00080000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK__SI 0x00010000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK__SI 0x00400000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK__SI 0x00200000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK__SI 0x08000000L -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK__SI 0x04000000L -#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK__SI 0x00040000L -#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK__SI 0x00800000L -#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK__SI 0x00020000L -#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK__SI 0x02000000L -#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK__SI 0x01000000L -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK__SI 0x00001000L -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK__SI 0x000000c0L -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK__SI 0x00000003L -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK__SI 0x00000c00L -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK__SI 0x00000030L -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK__SI 0x0000000cL -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK__SI 0x00000300L -#define DCIO_DEBUG2__DCIO_DEBUG2_MASK__SI 0xffffffffL -#define DCIO_DEBUG3__DCIO_DEBUG3_MASK__SI 0xffffffffL -#define DCIO_DEBUG4__DCIO_DEBUG4_MASK__SI 0xffffffffL -#define DCIO_DEBUG5__DCIO_DEBUG5_MASK__SI 0xffffffffL -#define DCIO_DEBUG6__DCIO_DEBUG6_MASK__SI 0xffffffffL -#define DCIO_DEBUG7__DCIO_DEBUG7_MASK__SI 0xffffffffL -#define DCIO_DEBUG__DCIO_DEBUG_MASK__SI 0xffffffffL -#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK__SI 0x0000000fL -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK__SI 0x00007000L -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_RESET_PM_MASK_MASK__SI 0x00000010L -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK__SI 0x00000020L -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK__SI 0x00000300L -#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK__SI 0x0000000fL -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK__SI 0x00007000L -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_RESET_PM_MASK_MASK__SI 0x00000010L -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK__SI 0x00000020L -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK__SI 0x00000300L -#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK__SI 0x0000000fL -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK__SI 0x00007000L -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_RESET_PM_MASK_MASK__SI 0x00000010L -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK__SI 0x00000020L -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK__SI 0x00000300L -#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DCPLL_CNTL__DCPLL_ANTI_GLITCH_RESET_MASK__SI 0x00002000L -#define DCPLL_CNTL__DCPLL_BYPASS_CAL_MASK__SI 0x00000004L -#define DCPLL_CNTL__DCPLL_CALIB_DONE_MASK__SI 0x00100000L -#define DCPLL_CNTL__DCPLL_CALREF_MASK__SI 0x00000300L -#define DCPLL_CNTL__DCPLL_CAL_BYPASS_REFDIV_MASK__SI 0x00000400L -#define DCPLL_CNTL__DCPLL_DEBUG_SIGNALS_ENABLE_MASK__SI 0x00004000L -#define DCPLL_CNTL__DCPLL_DIFF_REC_ENABLE_MASK__SI 0x00001000L -#define DCPLL_CNTL__DCPLL_DIRECT_CLOCK_2X_MASK__SI 0x80000000L -#define DCPLL_CNTL__DCPLL_DVOCLK_SRC_MASK__SI 0x40000000L -#define DCPLL_CNTL__DCPLL_LOCKED_MASK__SI 0x00200000L -#define DCPLL_CNTL__DCPLL_LOCK_FREQ_SEL_MASK__SI 0x00080000L -#define DCPLL_CNTL__DCPLL_LVTMCLK_SRC_MASK__SI 0x0c000000L -#define DCPLL_CNTL__DCPLL_PCIE_REFCLK_DISABLE_MASK__SI 0x00000800L -#define DCPLL_CNTL__DCPLL_PIXCLK_SRC_MASK__SI 0x30000000L -#define DCPLL_CNTL__DCPLL_PWRMGT_TURN_OFF_PLL_MASK__SI 0x00010000L -#define DCPLL_CNTL__DCPLL_RESET_MASK__SI 0x00000001L -#define DCPLL_CNTL__DCPLL_SLEEP_MASK__SI 0x00000002L -#define DCPLL_CNTL__DCPLL_TIMING_MODE_STATUS_MASK__SI 0x03000000L -#define DCPLL_CNTL__DCPLL_VCOREF_MASK__SI 0x00000030L -#define DCPLL_DEBUG_CLK_SEL__DCPLL_DEBUG_CLK_SEL_MASK__SI 0x00000700L -#define DCPLL_DISPCLK_DTO_CNTL__DCPLL_DISPCLK_DTO_DIS_MASK__SI 0x00001000L -#define DCPLL_DISPCLK_DTO_CNTL__DCPLL_DISPCLK_DTO_PHASE_MASK__SI 0x000001ffL -#define DCPLL_FB_DIV__DCPLL_FB_DIV_FRACTION_CNTL_MASK__SI 0x00000030L -#define DCPLL_FB_DIV__DCPLL_FB_DIV_FRACTION_MASK__SI 0x0000000fL -#define DCPLL_FB_DIV__DCPLL_FB_DIV_MASK__SI 0x0fff0000L -#define DCPLL_PLL_CNTL__DCPLL_CP_MASK__SI 0x00000f00L -#define DCPLL_PLL_CNTL__DCPLL_IBIAS_MASK__SI 0xff000000L -#define DCPLL_PLL_CNTL__DCPLL_LF_MODE_MASK__SI 0x001ff000L -#define DCPLL_PLL_CNTL__DCPLL_PLL_CTL_MASK__SI 0x0000001fL -#define DCPLL_POST_DIV_SRC__DCPLL_POST_DIV_SRC_MASK__SI 0x00000001L -#define DCPLL_POST_DIV__DCPLL_POST_DIV_MASK__SI 0x0000007fL -#define DCPLL_REF_DIV_SRC__DCPLL_REF_DIV_SRC_MASK__SI 0x00000007L -#define DCPLL_REF_DIV__DCPLL_CALIBRATION_REF_DIV_MASK__SI 0x0000f000L -#define DCPLL_REF_DIV__DCPLL_REF_DIV_MASK__SI 0x000003ffL -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_DETECT_ENABLE_MASK__SI 0x00000001L -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_DOWN_CNTL_MASK__SI 0x00000f00L -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_DUTY_CYCLE_SELECT_MASK__SI 0x00000002L -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_STICKY_CLEAR_MASK__SI 0x00000008L -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_STICKY_STATUS_MASK__SI 0x00000004L -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_UP_CNTL_MASK__SI 0x000000f0L -#define DCPLL_UPDATE_CNTL__DCPLL_UPDATE_PENDING_MASK__SI 0x00000001L -#define DCPLL_UPDATE_CNTL__DCPLL_UPDATE_POINT_MASK__SI 0x00000100L -#define DCPLL_UPDATE_LOCK__DCPLL_UPDATE_LOCK_MASK__SI 0x00000001L -#define DCPLL_VREG_CNTL__DCPLL_VREG_BIAS_MASK__SI 0x0f000000L -#define DCPLL_VREG_CNTL__DCPLL_VREG_CNTL_MASK__SI 0x00000003L -#define DCPLL_VREG_CNTL__DCPLL_VREG_POWER_DOWN_MASK__SI 0x20000000L -#define DCP_CONTROL__MAX_REQ_BUF_SIZE_MASK__SI 0x0000000fL -#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK__SI 0x00000001L -#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK__SI 0x00000300L -#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK__SI 0x0000001cL -#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK__SI 0xffffffffL -#define DCP_CRC_LAST__DCP_CRC_LAST_MASK__SI 0xffffffffL -#define DCP_CRC_MASK__DCP_CRC_MASK_MASK__SI 0xffffffffL -#define DCP_DEBUG_ID__DCP_DEBUG_ID_MASK__SI 0xffffffffL -#define DCP_DEBUG__DCP_DEBUG_MASK__SI 0xffffffffL -#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK__SI 0x0000000fL -#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK__SI 0x000000f0L -#define DCP_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK__SI 0x00000007L -#define DCP_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK__SI 0x00000018L -#define DCP_RBBMIF_RDWR_TIMEOUT__AZ_RBBMIF_RD_WR_TIMEOUT_DIS_MASK__SI 0x00000004L -#define DCP_RBBMIF_RDWR_TIMEOUT__DCP_RBBMIF_RD_WR_TIMEOUT_DIS_MASK__SI 0x00000001L -#define DCP_RBBMIF_RDWR_TIMEOUT__VGA_RBBMIF_RD_WR_TIMEOUT_DIS_MASK__SI 0x00000002L -#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DCP_TILING_CONFIG__BANK_SWAPS_MASK__SI 0x00003800L -#define DCP_TILING_CONFIG__BANK_TILING_MASK__SI 0x00000030L -#define DCP_TILING_CONFIG__GROUP_SIZE_MASK__SI 0x000000c0L -#define DCP_TILING_CONFIG__PIPE_TILING_MASK__SI 0x0000000eL -#define DCP_TILING_CONFIG__ROW_TILING_MASK__SI 0x00000700L -#define DCP_TILING_CONFIG__SAMPLE_SPLIT_MASK__SI 0x0000c000L -#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK__SI 0x00000100L -#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK__SI 0x00000001L -#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK__SI 0x07ff0000L -#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK__SI 0x00007fffL -#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK__SI 0x07ff0000L -#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK__SI 0x00007fffL -#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK__SI 0x07ff0000L -#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK__SI 0x00007fffL -#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK__SI 0x07ff0000L -#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK__SI 0x00007fffL -#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK__SI 0x07ff0000L -#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK__SI 0x00007fffL -#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK__SI 0x000003ffL -#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK__SI 0x03ff0000L -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK__SI 0x40000000L -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK__SI 0x10000000L -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK__SI 0x20000000L -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK__SI 0x000003ffL -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK__SI 0x03ff0000L -#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_CNTL__ABM1_EN_MASK__SI 0x00000001L -#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK__SI 0x00000100L -#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK__SI 0x00010000L -#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK__SI 0x00000001L -#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK__SI 0x00000100L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK__SI 0x00000004L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK__SI 0x80000000L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK__SI 0x00000400L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK__SI 0x00000001L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK__SI 0x00010000L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK__SI 0x00000100L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK__SI 0x00000002L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK__SI 0x01000000L -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK__SI 0x00000200L -#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK__SI 0xffffffffL -#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK__SI 0xffffffffL -#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK__SI 0xffffffffL -#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK__SI 0xffffffffL -#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK__SI 0xffffffffL -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK__SI 0x08000000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK__SI 0x20000000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK__SI 0x10000000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK__SI 0x40000000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK__SI 0x04000000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK__SI 0x00030000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK__SI 0x00001000L -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK__SI 0x00000003L -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK__SI 0x00000100L -#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK__SI 0x00100000L -#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK__SI 0xffffffffL -#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK__SI 0xffffffffL -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK__SI \ - 0x00ff0000L -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK__SI 0x00000002L -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK__SI 0x00000001L -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK__SI 0x0000ff00L -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK__SI 0x0000000fL -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK__SI 0x00000f00L -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK__SI 0x000f0000L -#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK__SI 0x03ff0000L -#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK__SI 0x000003ffL -#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK__SI 0x00ffffffL -#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK__SI 0x03ff0000L -#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK__SI 0x000003ffL -#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK__SI 0x03ff0000L -#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK__SI 0x000003ffL -#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK__SI 0x00ffffffL -#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK__SI 0x00ffffffL -#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK__SI 0x00ffffffL -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK__SI 0x80000000L -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK__SI \ - 0x00ff0000L -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK__SI 0x00000002L -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK__SI 0x00000001L -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK__SI 0x0000ff00L -#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK__SI 0xffffffffL -#define DC_DISPCLK_PERFCOUNTER0_HI__DC_DISPCLK_PERFCOUNTER0_HI_MASK__SI 0x0000ffffL -#define DC_DISPCLK_PERFCOUNTER0_LOW__DC_DISPCLK_PERFCOUNTER0_LOW_MASK__SI 0xffffffffL -#define DC_DISPCLK_PERFCOUNTER0_SELECT__DC_DISPCLK_PERFCOUNTER0_MODE_MASK__SI 0x00030000L -#define DC_DISPCLK_PERFCOUNTER0_SELECT__DC_DISPCLK_PERFCOUNTER0_SELECT_MASK__SI 0x000001ffL -#define DC_DISPCLK_PERFCOUNTER1_HI__DC_DISPCLK_PERFCOUNTER1_HI_MASK__SI 0x0000ffffL -#define DC_DISPCLK_PERFCOUNTER1_LOW__DC_DISPCLK_PERFCOUNTER1_LOW_MASK__SI 0xffffffffL -#define DC_DISPCLK_PERFCOUNTER1_SELECT__DC_DISPCLK_PERFCOUNTER1_MODE_MASK__SI 0x00030000L -#define DC_DISPCLK_PERFCOUNTER1_SELECT__DC_DISPCLK_PERFCOUNTER1_SELECT_MASK__SI 0x000001ffL -#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK__SI 0xffffffffL -#define DC_DOUT_DEBUG_MUX_CNTL__DAC_MUX_SELECT_MASK__SI 0x00000001L -#define DC_DOUT_DEBUG_MUX_CNTL__DC_I2C_MUX_SELECT_MASK__SI 0x001f0000L -#define DC_DOUT_DEBUG_MUX_CNTL__TMDS_DVO_MUX_SELECT_MASK__SI 0x00000300L -#define DC_FID_CNT__FID_ON_MARK_MASK__SI 0x00007fffL -#define DC_GENERICA__GENERICA_EN_MASK__SI 0x00000001L -#define DC_GENERICA__GENERICA_SEL_MASK__SI 0x00000f00L -#define DC_GENERICB__GENERICB_EN_MASK__SI 0x00000001L -#define DC_GENERICB__GENERICB_SEL_MASK__SI 0x00000f00L -#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK__SI 0x00000001L -#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK__SI 0x00000100L -#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK__SI 0x00000001L -#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK__SI 0x00000100L -#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK__SI 0x00100000L -#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK__SI 0x00010000L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK__SI 0x00000001L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK__SI 0x00000010L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK__SI 0x00000040L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK__SI 0x0f000000L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK__SI 0x00000100L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK__SI 0x00001000L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK__SI 0x00004000L -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK__SI 0xf0000000L -#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK__SI 0x00000001L -#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK__SI 0x00000100L -#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK__SI 0x00000001L -#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK__SI 0x00000100L -#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK__SI 0x00000001L -#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK__SI 0x00000100L -#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK__SI 0x00100000L -#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK__SI 0x00010000L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK__SI 0x00000001L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK__SI 0x00000010L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK__SI 0x00000040L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK__SI 0x0f000000L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK__SI 0x00000100L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK__SI 0x00001000L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK__SI 0x00004000L -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK__SI 0xf0000000L -#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK__SI 0x00000001L -#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK__SI 0x00000100L -#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK__SI 0x00000001L -#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK__SI 0x00000100L -#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK__SI 0x00000001L -#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK__SI 0x00000100L -#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK__SI 0x00100000L -#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK__SI 0x00010000L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK__SI 0x00000001L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK__SI 0x00000010L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK__SI 0x00000040L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK__SI 0x0f000000L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK__SI 0x00000100L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK__SI 0x00001000L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK__SI 0x00004000L -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK__SI 0xf0000000L -#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK__SI 0x00000001L -#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK__SI 0x00000100L -#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK__SI 0x00000001L -#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK__SI 0x00000100L -#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK__SI 0x00000001L -#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK__SI 0x00000100L -#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK__SI 0x00100000L -#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK__SI 0x00010000L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK__SI 0x00000001L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK__SI 0x00000010L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK__SI 0x00000040L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK__SI 0x0f000000L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK__SI 0x00000100L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK__SI 0x00001000L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK__SI 0x00004000L -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK__SI 0xf0000000L -#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK__SI 0x00000001L -#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK__SI 0x00000100L -#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK__SI 0x00000001L -#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK__SI 0x00000100L -#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK__SI 0x00000001L -#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK__SI 0x00000100L -#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK__SI 0x00100000L -#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK__SI 0x00010000L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK__SI 0x00000001L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK__SI 0x00000010L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK__SI 0x00000040L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK__SI 0x0f000000L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK__SI 0x00000100L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK__SI 0x00001000L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK__SI 0x00004000L -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK__SI 0xf0000000L -#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK__SI 0x00000001L -#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK__SI 0x00000100L -#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK__SI 0x00000001L -#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK__SI 0x00000100L -#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK__SI 0x00000001L -#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK__SI 0x00000100L -#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK__SI 0x00100000L -#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK__SI 0x00010000L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK__SI 0x00000001L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK__SI 0x00000010L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK__SI 0x00000040L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK__SI 0x0f000000L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK__SI 0x00000100L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK__SI 0x00001000L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK__SI 0x00004000L -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK__SI 0xf0000000L -#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK__SI 0x00000001L -#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK__SI 0x00000100L -#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK__SI 0x00000300L -#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK__SI 0x00000001L -#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK__SI 0x10000000L -#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK__SI 0x07000000L -#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK__SI 0x00ffffffL -#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK__SI 0xc0000000L -#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK__SI 0x10000000L -#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK__SI 0x07000000L -#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK__SI 0x00ffffffL -#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK__SI 0xc0000000L -#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK__SI 0x10000000L -#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK__SI 0x07000000L -#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK__SI 0x00ffffffL -#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK__SI 0xc0000000L -#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK__SI 0x10000000L -#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK__SI 0x07000000L -#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK__SI 0x00ffffffL -#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK__SI 0xc0000000L -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK__SI 0x00000001L -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK__SI 0x00000100L -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK__SI 0x00010000L -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK__SI 0x00100000L -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK__SI 0x00200000L -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK__SI 0x00400000L -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK__SI 0x00800000L -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK__SI 0x00000001L -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK__SI 0x00000100L -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK__SI 0x00010000L -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK__SI 0x00100000L -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK__SI 0x00200000L -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK__SI 0x00400000L -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK__SI 0x00800000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK__SI 0x00000001L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK__SI 0x00000002L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK__SI 0x00000004L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK__SI 0x00000010L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK__SI 0x00000020L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK__SI 0x00000040L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK__SI 0x00000100L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK__SI 0x00000200L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK__SI 0x00000400L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK__SI 0x00001000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK__SI 0x00002000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK__SI 0x00004000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK__SI 0x00010000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK__SI 0x00020000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK__SI 0x00040000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK__SI 0x00100000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK__SI 0x00200000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK__SI 0x00400000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK__SI 0x01000000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK__SI 0x02000000L -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK__SI 0x04000000L -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK__SI 0x00000001L -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK__SI 0x00000100L -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK__SI 0x00010000L -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK__SI 0x00100000L -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK__SI 0x00200000L -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK__SI 0x00400000L -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK__SI 0x00800000L -#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK__SI 0x00000001L -#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK__SI 0x00000100L -#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK__SI 0x00010000L -#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK__SI 0x01000000L -#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK__SI 0x04000000L -#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK__SI 0x10000000L -#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK__SI 0x00000001L -#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK__SI 0x00000100L -#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK__SI 0x00010000L -#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK__SI 0x01000000L -#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK__SI 0x04000000L -#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK__SI 0x10000000L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK__SI 0x00000001L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK__SI 0x00000010L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK__SI 0x00000040L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK__SI 0x00000100L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK__SI 0x00010000L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK__SI 0x01000000L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK__SI 0x04000000L -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK__SI 0x10000000L -#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK__SI 0x00000001L -#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK__SI 0x00000100L -#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK__SI 0x00010000L -#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK__SI 0x01000000L -#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK__SI 0x04000000L -#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK__SI 0x10000000L -#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK__SI 0x0f000000L -#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK__SI 0xf0000000L -#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK__SI 0x000f0000L -#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK__SI 0x00f00000L -#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK__SI 0x0000000fL -#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK__SI 0x000000f0L -#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK__SI 0x00000001L -#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK__SI 0x00000100L -#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK__SI 0x00010000L -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK__SI 0x00000001L -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK__SI 0x00000100L -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK__SI 0x00010000L -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK__SI 0x00000002L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK__SI 0x00000001L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK__SI 0x00000010L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK__SI 0x00000040L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK__SI 0x00000100L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK__SI 0x00001000L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK__SI 0x00004000L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK__SI 0x00010000L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK__SI 0x00100000L -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK__SI 0x00400000L -#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK__SI 0x00000001L -#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK__SI 0x00000100L -#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK__SI 0x00010000L -#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK__SI 0x00000001L -#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK__SI 0x00000100L -#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK__SI 0x00000001L -#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK__SI 0x00000100L -#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK__SI 0x00000001L -#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK__SI 0x00000010L -#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK__SI 0x00000040L -#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK__SI 0x00000100L -#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK__SI 0x00001000L -#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK__SI 0x00004000L -#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK__SI 0x00000001L -#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK__SI 0x00000100L -#define DC_GPIO_SYNCB_A__DC_GPIO_HSYNCB_A_MASK__SI 0x00000001L -#define DC_GPIO_SYNCB_A__DC_GPIO_VSYNCB_A_MASK__SI 0x00000100L -#define DC_GPIO_SYNCB_EN__DC_GPIO_HSYNCB_EN_MASK__SI 0x00000001L -#define DC_GPIO_SYNCB_EN__DC_GPIO_VSYNCB_EN_MASK__SI 0x00000100L -#define DC_GPIO_SYNCB_MASK__DC_GPIO_HSYNCB_MASK_MASK__SI 0x00000001L -#define DC_GPIO_SYNCB_MASK__DC_GPIO_HSYNCB_PD_DIS_MASK__SI 0x00000010L -#define DC_GPIO_SYNCB_MASK__DC_GPIO_HSYNCB_RECV_MASK__SI 0x00000040L -#define DC_GPIO_SYNCB_MASK__DC_GPIO_VSYNCB_MASK_MASK__SI 0x00000100L -#define DC_GPIO_SYNCB_MASK__DC_GPIO_VSYNCB_PD_DIS_MASK__SI 0x00001000L -#define DC_GPIO_SYNCB_MASK__DC_GPIO_VSYNCB_RECV_MASK__SI 0x00004000L -#define DC_GPIO_SYNCB_Y__DC_GPIO_HSYNCB_Y_MASK__SI 0x00000001L -#define DC_GPIO_SYNCB_Y__DC_GPIO_VSYNCB_Y_MASK__SI 0x00000100L -#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK__SI 0x00000007L -#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK__SI 0xffffffffL -#define DC_GPU_TIMER_START_POSITION__DC_GPU_TIMER_START_POSITION_P_FLIP_MASK__SI 0x00070000L -#define DC_GPU_TIMER_START_POSITION__DC_GPU_TIMER_START_POSITION_V_UPDATE_MASK__SI 0x00000007L -#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK__SI 0x00001fffL -#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK__SI 0x10000000L -#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK__SI 0x03ff0000L -#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK__SI 0x00000001L -#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK__SI 0x00010000L -#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK__SI 0x00000100L -#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK__SI 0x00100000L -#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK__SI 0x01000000L -#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK__SI 0x00000001L -#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK__SI 0x00000100L -#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK__SI 0x00000002L -#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK__SI 0x00001fffL -#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK__SI 0x10000000L -#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK__SI 0x03ff0000L -#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK__SI 0x00000001L -#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK__SI 0x00010000L -#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK__SI 0x00000100L -#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK__SI 0x00100000L -#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK__SI 0x01000000L -#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK__SI 0x00000001L -#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK__SI 0x00000100L -#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK__SI 0x00000002L -#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK__SI 0x00001fffL -#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK__SI 0x10000000L -#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK__SI 0x03ff0000L -#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK__SI 0x00000001L -#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK__SI 0x00010000L -#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK__SI 0x00000100L -#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK__SI 0x00100000L -#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK__SI 0x01000000L -#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK__SI 0x00000001L -#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK__SI 0x00000100L -#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK__SI 0x00000002L -#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK__SI 0x00001fffL -#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK__SI 0x10000000L -#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK__SI 0x03ff0000L -#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK__SI 0x00000001L -#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK__SI 0x00010000L -#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK__SI 0x00000100L -#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK__SI 0x00100000L -#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK__SI 0x01000000L -#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK__SI 0x00000001L -#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK__SI 0x00000100L -#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK__SI 0x00000002L -#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK__SI 0x00001fffL -#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK__SI 0x10000000L -#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK__SI 0x03ff0000L -#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK__SI 0x00000001L -#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK__SI 0x00010000L -#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK__SI 0x00000100L -#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK__SI 0x00100000L -#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK__SI 0x01000000L -#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK__SI 0x00000001L -#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK__SI 0x00000100L -#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK__SI 0x00000002L -#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK__SI 0x00001fffL -#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK__SI 0x10000000L -#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK__SI 0x03ff0000L -#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK__SI 0x00000001L -#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK__SI 0x00010000L -#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK__SI 0x00000100L -#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK__SI 0x00100000L -#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK__SI 0x01000000L -#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK__SI 0x00000001L -#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK__SI 0x00000100L -#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK__SI 0x00000002L -#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK__SI 0x00000100L -#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK__SI 0x00001000L -#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK__SI 0x02000000L -#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK__SI 0x01000000L -#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK__SI 0x00000010L -#define DC_I2C_ARBITRATION__DC_I2C_NO_RESTART_SW_GO_MASK__SI 0x00000020L -#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK__SI 0x0000000cL -#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK__SI 0x00200000L -#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK__SI 0x00000003L -#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK__SI 0x00100000L -#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK__SI 0x80000000L -#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK__SI 0x00000700L -#define DC_I2C_CONTROL__DC_I2C_GO_MASK__SI 0x00000001L -#define DC_I2C_CONTROL__DC_I2C_SDVO_ADDR_SEL_MASK__SI 0x00000040L -#define DC_I2C_CONTROL__DC_I2C_SDVO_EN_MASK__SI 0x00000010L -#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK__SI 0x00000004L -#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK__SI 0x00000002L -#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK__SI 0x00000008L -#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK__SI 0x00300000L -#define DC_I2C_DATA__DC_I2C_DATA_MASK__SI 0x0000ff00L -#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK__SI 0x00000001L -#define DC_I2C_DATA__DC_I2C_INDEX_MASK__SI 0x00ff0000L -#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK__SI 0x80000000L -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK__SI 0x00000008L -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK__SI 0x00010000L -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK__SI 0x00000003L -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK__SI 0x00020000L -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK__SI 0x00000080L -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK__SI 0x00000001L -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK__SI 0x00000002L -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK__SI 0x00ff0000L -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK__SI 0xff000000L -#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK__SI 0x00000010L -#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK__SI 0xffff0000L -#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK__SI 0x00000003L -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK__SI 0x00000008L -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK__SI 0x00010000L -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK__SI 0x00000003L -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK__SI 0x00020000L -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK__SI 0x00000080L -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK__SI 0x00000001L -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK__SI 0x00000002L -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK__SI 0x00ff0000L -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK__SI 0xff000000L -#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK__SI 0x00000010L -#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK__SI 0xffff0000L -#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK__SI 0x00000003L -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK__SI 0x00000008L -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK__SI 0x00010000L -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK__SI 0x00000003L -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK__SI 0x00020000L -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK__SI 0x00000080L -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK__SI 0x00000001L -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK__SI 0x00000002L -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK__SI 0x00ff0000L -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK__SI 0xff000000L -#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK__SI 0x00000010L -#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK__SI 0xffff0000L -#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK__SI 0x00000003L -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK__SI 0x00000008L -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK__SI 0x00010000L -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK__SI 0x00000003L -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK__SI 0x00020000L -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK__SI 0x00000080L -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK__SI 0x00000001L -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK__SI 0x00000002L -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK__SI 0x00ff0000L -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK__SI 0xff000000L -#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK__SI 0x00000010L -#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK__SI 0xffff0000L -#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK__SI 0x00000003L -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK__SI 0x00000008L -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK__SI 0x00010000L -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK__SI 0x00000003L -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK__SI 0x00020000L -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK__SI 0x00000080L -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK__SI 0x00000001L -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK__SI 0x00000002L -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK__SI 0x00ff0000L -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK__SI 0xff000000L -#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK__SI 0x00000010L -#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK__SI 0xffff0000L -#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK__SI 0x00000003L -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK__SI 0x00000008L -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK__SI 0x00010000L -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK__SI 0x00000003L -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK__SI 0x00020000L -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK__SI 0x00000080L -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK__SI 0x00000001L -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK__SI 0x00000002L -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK__SI 0x00ff0000L -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK__SI 0xff000000L -#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK__SI 0x00000010L -#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK__SI 0xffff0000L -#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK__SI 0x00000003L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK__SI 0x00000020L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK__SI 0x00000010L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK__SI 0x00000040L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK__SI 0x00000200L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK__SI 0x00000100L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK__SI 0x00000400L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK__SI 0x00002000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK__SI 0x00001000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK__SI 0x00004000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK__SI 0x00020000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK__SI 0x00010000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK__SI 0x00040000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK__SI 0x00200000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK__SI 0x00100000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK__SI 0x00400000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK__SI 0x02000000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK__SI 0x01000000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK__SI 0x04000000L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK__SI 0x00000002L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK__SI 0x00000001L -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK__SI 0x00000004L -#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK__SI 0x00000010L -#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK__SI 0x00000080L -#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK__SI 0x00000004L -#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK__SI 0x00000040L -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK__SI 0x00001000L -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK__SI 0x00002000L -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK__SI 0x00004000L -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK__SI 0x00008000L -#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK__SI 0x00040000L -#define DC_I2C_SW_STATUS__DC_I2C_SW_SDVO_NACK_MASK__SI 0x00000400L -#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK__SI 0x00000003L -#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK__SI 0x00000100L -#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK__SI 0x00000020L -#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK__SI 0x00ff0000L -#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK__SI 0x00000001L -#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK__SI 0x00001000L -#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK__SI 0x00002000L -#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK__SI 0x00000100L -#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK__SI 0x00ff0000L -#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK__SI 0x00000001L -#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK__SI 0x00001000L -#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK__SI 0x00002000L -#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK__SI 0x00000100L -#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK__SI 0x00ff0000L -#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK__SI 0x00000001L -#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK__SI 0x00001000L -#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK__SI 0x00002000L -#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK__SI 0x00000100L -#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK__SI 0x00ff0000L -#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK__SI 0x00000001L -#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK__SI 0x00001000L -#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK__SI 0x00002000L -#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK__SI 0x00000100L -#define DC_LB_BLACK_KEYER_B__DC_LB_BLACK_KEYER_B_MASK__SI 0x0000ffc0L -#define DC_LB_BLACK_KEYER_G__DC_LB_BLACK_KEYER_G_MASK__SI 0x0000ffc0L -#define DC_LB_BLACK_KEYER_R__DC_LB_BLACK_KEYER_R_MASK__SI 0x0000ffc0L -#define DC_LB_MEMORY_SPLIT__DC_LB_DISP1_END_ADR_MASK__SI 0x00007ff0L -#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_SPLIT_MASK__SI 0x00000003L -#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_SPLIT_MODE_MASK__SI 0x00000004L -#define DC_LB_MEMORY_SPLIT__DC_LB_SIZE_3840_MASK__SI 0x10000000L -#define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS_MASK__SI 0x000f0000L -#define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE_MASK__SI 0x000007ffL -#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK__SI 0x000003ffL -#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK__SI 0x000ffc00L -#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK__SI 0x3ff00000L -#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK__SI 0x00000002L -#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK__SI 0x00000001L -#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK__SI 0x0000ffffL -#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK__SI 0x0000ffffL -#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK__SI 0x0000ffffL -#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK__SI 0x00000020L -#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK__SI 0x00000010L -#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK__SI 0x00002000L -#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK__SI 0x00001000L -#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK__SI 0x00200000L -#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK__SI 0x00100000L -#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK__SI 0x0000000fL -#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK__SI 0x00000f00L -#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK__SI 0x000f0000L -#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK__SI 0x0000ffffL -#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK__SI 0xffff0000L -#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK__SI 0x000000ffL -#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK__SI 0x00000001L -#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK__SI 0x0000ffffL -#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK__SI 0x0000ffffL -#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK__SI 0x0000ffffL -#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK__SI 0x0000ffffL -#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK__SI 0x00000007L -#define DC_MVP_LB_CONTROL__DC_MVP_DFQ_EN_MASK__SI 0x00040000L -#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK__SI 0x80000000L -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK__SI 0x10000000L -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK__SI 0x00001000L -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK__SI 0x00010000L -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK__SI 0x00000100L -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK__SI 0x00100000L -#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK__SI 0x00000003L -#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK__SI 0x0000000fL -#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK__SI 0x00000030L -#define DC_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK__SI 0x0fffff00L -#define DC_PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK__SI 0x000000f0L -#define DC_PERFMON_CNTL__PERFMON_STATE_MASK__SI 0x00000003L -#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK__SI 0x0000c000L -#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK__SI 0x00010000L -#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK__SI 0x00002000L -#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_SOFT_MASK__SI 0x00001000L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_64BAR_EN_A_MASK__SI 0x00000004L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_AUDIO_EN_MASK__SI 0x00000010L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_CLK_PM_EN_MASK__SI 0x00000100L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_ECN1P1_DIS_MASK__SI 0x00000002L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_ERR_REPORTING_DIS_MASK__SI 0x00000080L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_IO_BAR_DIS_MASK__SI 0x00000001L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_MSI_DIS_MASK__SI 0x00000040L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_NONLEGACY_DEVICE_TYPE_EN_MASK__SI 0x00000008L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_REG_AP_SIZE_1_MASK__SI 0x00000020L -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_VGA_DIS_MASK__SI 0x00000200L -#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK__SI 0x00000800L -#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_STRAP_DIS_MASK__SI 0x00000400L -#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK__SI 0x00000003L -#define DC_REF_CLK_CNTL__HSYNCB_OUTPUT_SEL_MASK__SI 0x00000300L -#define DC_SCLK_PERFCOUNTER0_HI__DC_SCLK_PERFCOUNTER0_HI_MASK__SI 0x0000ffffL -#define DC_SCLK_PERFCOUNTER0_LOW__DC_SCLK_PERFCOUNTER0_LOW_MASK__SI 0xffffffffL -#define DC_SCLK_PERFCOUNTER0_SELECT__DC_SCLK_PERFCOUNTER0_MODE_MASK__SI 0x00030000L -#define DC_SCLK_PERFCOUNTER0_SELECT__DC_SCLK_PERFCOUNTER0_SELECT_MASK__SI 0x000001ffL -#define DC_SCLK_PERFCOUNTER1_HI__DC_SCLK_PERFCOUNTER1_HI_MASK__SI 0x0000ffffL -#define DC_SCLK_PERFCOUNTER1_LOW__DC_SCLK_PERFCOUNTER1_LOW_MASK__SI 0xffffffffL -#define DC_SCLK_PERFCOUNTER1_SELECT__DC_SCLK_PERFCOUNTER1_MODE_MASK__SI 0x00030000L -#define DC_SCLK_PERFCOUNTER1_SELECT__DC_SCLK_PERFCOUNTER1_SELECT_MASK__SI 0x000001ffL -#define DC_STUTTER_CNTL__ALLOW_DISABLE_LB_REQ_IN_STUTTER_MASK__SI 0x00004000L -#define DC_STUTTER_CNTL__DC_ALLOW_NB_PSTATES_FORCE_ONE_MASK__SI 0x02000000L -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ALWAYS_ON_A_MASK__SI 0x00000080L -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ALWAYS_ON_B_MASK__SI 0x00000100L -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ENABLE_A_MASK__SI 0x00000020L -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ENABLE_B_MASK__SI 0x00000040L -#define DC_STUTTER_CNTL__DC_STUTTER_ALWAYS_ON_A_MASK__SI 0x00000004L -#define DC_STUTTER_CNTL__DC_STUTTER_ALWAYS_ON_B_MASK__SI 0x00000008L -#define DC_STUTTER_CNTL__DC_STUTTER_ENABLE_A_MASK__SI 0x00000001L -#define DC_STUTTER_CNTL__DC_STUTTER_ENABLE_B_MASK__SI 0x00000002L -#define DC_STUTTER_CNTL__DC_STUTTER_HTIU_FORCE_ONE_MASK__SI 0x00000010L -#define DC_STUTTER_CNTL__DISABLE_WM_HIGH_IN_VNONACTIVE_MASK__SI 0x00001000L -#define DC_STUTTER_CNTL__DISP_URGENT_WHEN_NOT_ALLOW_STOP_MASK__SI 0x00200000L -#define DC_STUTTER_CNTL__ENABLE_2LINE_IN_COMPRESS_MODE_MASK__SI 0x01000000L -#define DC_STUTTER_CNTL__ENABLE_4LINE_UNCOMPRESS_MODE_MASK__SI 0x00800000L -#define DC_STUTTER_CNTL__IGNORE_CURSOR_MASK__SI 0x00040000L -#define DC_STUTTER_CNTL__IGNORE_ICON_MASK__SI 0x00008000L -#define DC_STUTTER_CNTL__INCLUDE_AZALIA_IN_STUTTER_MASK__SI 0x00000800L -#define DC_STUTTER_CNTL__NO_ALLOW_STOP_IN_START_LINE_MASK__SI 0x00100000L -#define DC_STUTTER_CNTL__STUTTER_FID_IN_COMPRESS_MODE_MASK__SI 0x00400000L -#define DC_STUTTER_CNTL__STUTTER_ON_MODE_MASK__SI 0x00000200L -#define DC_STUTTER_CNTL__USE_CPU_IDLE_IN_STUTTER_MASK__SI 0x00000400L -#define DC_STUTTER_STATUS__DC_CG_DISP1_VBI_MASK__SI 0x00001000L -#define DC_STUTTER_STATUS__DC_CG_DISP2_VBI_MASK__SI 0x00002000L -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_OCCURRED_ACK_MASK__SI 0x00000100L -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_OCCURRED_MASK__SI 0x00000010L -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_PERF_CNT_ACK_MASK__SI 0x00010000L -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_STATUS_MASK__SI 0x00000001L -#define DC_STUTTER_STATUS__DC_CG_WM_MCHANGE_OCCURRED_ACK_MASK__SI 0x00000200L -#define DC_STUTTER_STATUS__DC_CG_WM_MCHANGE_OCCURRED_MASK__SI 0x00000020L -#define DC_STUTTER_STATUS__DC_CG_WM_MCHANGE_STATUS_MASK__SI 0x00000002L -#define DC_STUTTER_STATUS__DC_STUTTER_MODE_EXTRA_PORTS_MASK__SI 0xff000000L -#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DC_TEST_DEBUG_VIP_CNTL__DC_TEST_DEBUG_VIP_BLOCK_SEL_MASK__SI 0x00003f00L -#define DC_TEST_DEBUG_VIP_CNTL__DC_TEST_DEBUG_VIP_GROUP_SEL_MASK__SI 0x003f0000L -#define DC_TEST_DEBUG_VIP_CNTL__DC_TEST_DEBUG_VIP_LEGACY_TEST_EN_MASK__SI 0x00000002L -#define DDIA_DEBUG1__DOUT_DDIA_PIXCLK_MASK__SI 0x00000001L -#define DDIA_DEBUG1__DOUT_DDIA_RAND_BLANKb_IN_MASK__SI 0x00080000L -#define DDIA_DEBUG1__DOUT_DDIA_RAND_CAP_START_IN_MASK__SI 0x00000002L -#define DDIA_DEBUG1__DOUT_DDIA_RAND_COLOR_IN_MASK__SI 0x00000ffcL -#define DDIA_DEBUG1__DOUT_DDIA_RAND_COLOR_OUT_MASK__SI 0xffc00000L -#define DDIA_DEBUG1__DOUT_DDIA_RAND_HSYNC_IN_MASK__SI 0x00100000L -#define DDIA_DEBUG1__DOUT_DDIA_RAND_RANDOM_NUMBER_MASK__SI 0x0000f000L -#define DDIA_DEBUG1__DOUT_DDIA_RAND_VSYNC_IN_MASK__SI 0x00200000L -#define DDIA_DEBUG1__DOUT_DDIA_TRUNC_SIZE_MASK__SI 0x00030000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_BLANKb_IN_MASK__SI 0x00080000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_CAP_START_IN_MASK__SI 0x00000002L -#define DDIA_DEBUG2__DOUT_DDIA_FM_COLOR_IN_MASK__SI 0x00000ffcL -#define DDIA_DEBUG2__DOUT_DDIA_FM_COLOR_OUT_MASK__SI 0xffc00000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_GL10_ON_MASK__SI 0x00004000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_GL4_ON_MASK__SI 0x00001000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_GL7_ON_MASK__SI 0x00002000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_HSYNC_IN_MASK__SI 0x00100000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_LINE_ACTIVE_MASK__SI 0x00008000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_LINE_END_MASK__SI 0x00010000L -#define DDIA_DEBUG2__DOUT_DDIA_FM_VSYNC_IN_MASK__SI 0x00200000L -#define DDIA_DEBUG2__DOUT_DDIA_PIXCLK_MASK__SI 0x00000001L -#define DDIA_DEBUG2__DOUT_DDIA_RAND_SIZE_MASK__SI 0x00060000L -#define DDIA_DEBUG3__DOUT_DDIA_422_BLANKb_IN_MASK__SI 0x00000002L -#define DDIA_DEBUG3__DOUT_DDIA_422_COLOR_IN_MASK__SI 0x00000ffcL -#define DDIA_DEBUG3__DOUT_DDIA_422_COLOR_OUT_MASK__SI 0x007fe000L -#define DDIA_DEBUG3__DOUT_DDIA_422_PHASE_MASK__SI 0x00001000L -#define DDIA_DEBUG3__DOUT_DDIA_CAP_START_TO_HDCP_MASK__SI 0x00800000L -#define DDIA_DEBUG3__DOUT_DDIA_DATA_TO_HDCP_MASK__SI 0xff000000L -#define DDIA_DEBUG3__DOUT_DDIA_PIXCLK_MASK__SI 0x00000001L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_COLOR_DE_MASK__SI 0x00400000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_COLOR_IN_MASK__SI 0x00000ff0L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_COLOR_OUT_MASK__SI 0x003fc000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL0_OUT_MASK__SI 0x02000000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL1_OUT_MASK__SI 0x04000000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL2_OUT_MASK__SI 0x08000000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL3_OUT_MASK__SI 0x10000000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_DE_IN_MASK__SI 0x00000008L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_HSYNC_IN_MASK__SI 0x00000002L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_HSYNC_OUT_MASK__SI 0x00800000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_PLCTL0_IN_MASK__SI 0x00002000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_PLDEVS_OUT_MASK__SI 0x20000000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_STEREOSYNC_IN_MASK__SI 0x00001000L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_VSYNC_IN_MASK__SI 0x00000004L -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_VSYNC_OUT_MASK__SI 0x01000000L -#define DDIA_DEBUG4__DOUT_DDIA_PIXCLK_MASK__SI 0x00000001L -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_CHAR_A_IN_MASK__SI 0x00000002L -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_CHAR_B_IN_MASK__SI 0x00000004L -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_DCB_MASK__SI 0x001ff000L -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_DE_IN_MASK__SI 0x00000008L -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_IN_MASK__SI 0x00000ff0L -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_TX_MASK__SI 0xffc00000L -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_DE_TX_MASK__SI 0x00200000L -#define DDIA_DEBUG5__DOUT_DDIA_PIXCLK_MASK__SI 0x00000001L -#define DDIA_DEBUG6__DOUT_DDIA_PIXCLK_MASK__SI 0x00000001L -#define DDIA_DEBUG6__DOUT_DDIA_TX_COLOR_DE_IN_MASK__SI 0x00000002L -#define DDIA_DEBUG6__DOUT_DDIA_TX_COLOR_IN_MASK__SI 0x00000ffcL -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL0_IN_MASK__SI 0x00001000L -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL1_IN_MASK__SI 0x00002000L -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL2_IN_MASK__SI 0x00004000L -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL3_IN_MASK__SI 0x00008000L -#define DDIA_DEBUG6__DOUT_DDIA_TX_HSYNC_IN_MASK__SI 0x00100000L -#define DDIA_DEBUG6__DOUT_DDIA_TX_PLPIXA_OUT_MASK__SI 0xffc00000L -#define DDIA_DEBUG6__DOUT_DDIA_TX_VSYNC_IN_MASK__SI 0x00200000L -#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL -#define DEBUG_DRM_MASK_0__DRM_RTN_MASK0_MASK__SI 0xffffffffL -#define DEBUG_DRM_MASK_1__DRM_RTN_MASK1_MASK__SI 0xffffffffL -#define DEBUG_DRM_MASK_2__DRM_RTN_MASK2_MASK__SI 0xffffffffL -#define DEBUG_DRM_MASK_3__DRM_RTN_MASK3_MASK__SI 0xffffffffL -#define DEBUG_ENCRYP_COEF_0__ENCRYP_COEF0_MASK__SI 0xffffffffL -#define DEBUG_ENCRYP_COEF_1__ENCRYP_COEF1_MASK__SI 0xffffffffL -#define DEBUG_ENCRYP_COEF_2__ENCRYP_COEF2_MASK__SI 0xffffffffL -#define DEBUG_ENCRYP_COEF_3__ENCRYP_COEF3_MASK__SI 0xffffffffL -#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x0003ffffL -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK__SI 0x00020000L -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK__SI 0x00010000L -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK__SI 0x00040000L -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK__SI 0x00007f00L -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK__SI 0x0000007fL -#define DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK__SI 0x00003fffL -#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK__CI__VI 0x00000020L -#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK__CI__VI 0x00000010L -#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUP_MASK__SI 0x00000010L -#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK__CI__VI 0x0000000fL -#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUP_MASK__SI 0x0000000fL -#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK__CI__VI 0x00200000L -#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK__CI__VI 0x00100000L -#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK__CI__VI 0x00c00000L -#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03fc0000L -#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0c000000L -#define DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L -#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L -#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0L -#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000e00L -#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L -#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L -#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L -#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK__CI__VI 0x00000020L -#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x00000010L -#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x0000000fL -#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK__CI__VI 0x00008000L -#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x00000400L -#define DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK__SI 0x00008000L -#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x00000001L -#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x00000100L -#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x00000004L -#define DEVICE_CNTL__INITIATE_FLR_MASK__CI__VI 0x00008000L -#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x000000e0L -#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK__CI__VI 0x00007000L -#define DEVICE_CNTL__MAX_REQUEST_SIZE_MASK__SI 0x00007000L -#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x00000002L -#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x00000800L -#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x00000200L -#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x00000010L -#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x00000008L -#define DEVICE_ID__DEVICE_ID_MASK 0x0000ffffL -#define DEVICE_STATUS2__RESERVED_MASK 0x0000ffffL -#define DEVICE_STATUS__AUX_PWR_MASK 0x00000010L -#define DEVICE_STATUS__CORR_ERR_MASK 0x00000001L -#define DEVICE_STATUS__FATAL_ERR_MASK 0x00000004L -#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x00000002L -#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x00000020L -#define DEVICE_STATUS__USR_DETECTED_MASK 0x00000008L -#define DFT_CLK_STOP_COUNTER_LSB__DELAY_MASK__CI__VI 0xffffffffL -#define DFT_CLK_STOP_COUNTER_MSB__DELAY_MASK__CI__VI 0x0fffffffL -#define DFT_CLK_STOP_COUNTER_MSB__ENABLE_MASK__CI__VI 0x10000000L -#define DFT_CLK_STOP_COUNTER_MSB__LOAD_MASK__CI__VI 0x20000000L -#define DFT_CLK_STOP_COUNTER_MSB__MISC_MASK__CI__VI 0xc0000000L -#define DFT_CLK_STOP__MAGIC_CODE_MASK__CI__VI 0xffffffffL -#define DH_TEST__DH_TEST_MASK 0x00000001L -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK__CI__VI 0x00000020L -#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK__CI__VI 0x00000001L -#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK__CI__VI 0x00000010L -#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK__CI__VI 0x0000000cL -#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK__CI__VI 0x00000002L -#define DIDT_DB_CTRL1__MAX_POWER_MASK__CI__VI 0xffff0000L -#define DIDT_DB_CTRL1__MIN_POWER_MASK__CI__VI 0x0000ffffL -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK__CI__VI 0x78000000L -#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK__CI__VI 0x00003fffL -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK__CI__VI 0x03ff0000L -#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK__CI__VI 0x000000ffL -#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK__CI__VI 0x0000ff00L -#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK__CI__VI 0x00ff0000L -#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK__CI__VI 0xff000000L -#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK__CI__VI 0x000000ffL -#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK__CI__VI 0x0000ff00L -#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK__CI__VI 0x00ff0000L -#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK__CI__VI 0xff000000L -#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK__CI__VI 0x00ff0000L -#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK__CI__VI 0xff000000L -#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK__CI__VI 0x000000ffL -#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK__CI__VI 0x0000ff00L -#define DIDT_IND_DATA__DIDT_IND_DATA_MASK__CI__VI 0xffffffffL -#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK__CI__VI 0xffffffffL -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK__CI__VI 0x00000020L -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK__CI__VI 0x00000001L -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK__CI__VI 0x00000010L -#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK__CI__VI 0x0000000cL -#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK__CI__VI 0x00000002L -#define DIDT_SQ_CTRL1__MAX_POWER_MASK__CI__VI 0xffff0000L -#define DIDT_SQ_CTRL1__MIN_POWER_MASK__CI__VI 0x0000ffffL -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK__CI__VI 0x78000000L -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK__CI__VI 0x00003fffL -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK__CI__VI 0x03ff0000L -#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK__CI__VI 0x000000ffL -#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK__CI__VI 0x0000ff00L -#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK__CI__VI 0x00ff0000L -#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK__CI__VI 0xff000000L -#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK__CI__VI 0x000000ffL -#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK__CI__VI 0x0000ff00L -#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK__CI__VI 0x00ff0000L -#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK__CI__VI 0xff000000L -#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK__CI__VI 0x00ff0000L -#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK__CI__VI 0xff000000L -#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK__CI__VI 0x000000ffL -#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK__CI__VI 0x0000ff00L -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK__CI__VI 0x00000020L -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK__CI__VI 0x00000001L -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK__CI__VI 0x00000010L -#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK__CI__VI 0x0000000cL -#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK__CI__VI 0x00000002L -#define DIDT_TCP_CTRL1__MAX_POWER_MASK__CI__VI 0xffff0000L -#define DIDT_TCP_CTRL1__MIN_POWER_MASK__CI__VI 0x0000ffffL -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK__CI__VI 0x78000000L -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK__CI__VI 0x00003fffL -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK__CI__VI 0x03ff0000L -#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK__CI__VI 0x000000ffL -#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK__CI__VI 0x0000ff00L -#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK__CI__VI 0x00ff0000L -#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK__CI__VI 0xff000000L -#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK__CI__VI 0x000000ffL -#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK__CI__VI 0x0000ff00L -#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK__CI__VI 0x00ff0000L -#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK__CI__VI 0xff000000L -#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK__CI__VI 0x00ff0000L -#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK__CI__VI 0xff000000L -#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK__CI__VI 0x000000ffL -#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK__CI__VI 0x0000ff00L -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK__CI__VI 0x00000020L -#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK__CI__VI 0x00000001L -#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK__CI__VI 0x00000010L -#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK__CI__VI 0x0000000cL -#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK__CI__VI 0x00000002L -#define DIDT_TD_CTRL1__MAX_POWER_MASK__CI__VI 0xffff0000L -#define DIDT_TD_CTRL1__MIN_POWER_MASK__CI__VI 0x0000ffffL -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK__CI__VI 0x78000000L -#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK__CI__VI 0x00003fffL -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK__CI__VI 0x03ff0000L -#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK__CI__VI 0x000000ffL -#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK__CI__VI 0x0000ff00L -#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK__CI__VI 0x00ff0000L -#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK__CI__VI 0xff000000L -#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK__CI__VI 0x000000ffL -#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK__CI__VI 0x0000ff00L -#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK__CI__VI 0x00ff0000L -#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK__CI__VI 0xff000000L -#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK__CI__VI 0x00ff0000L -#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK__CI__VI 0xff000000L -#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK__CI__VI 0x000000ffL -#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK__CI__VI 0x0000ff00L -#define DIGA_CLOCK_ENABLE__DIGA_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_CAPTURE_START_MASK__SI 0x00800000L -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_COLOR_IN_MASK__SI 0x00000ffcL -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_COLOR_OUT_MASK__SI 0xff000000L -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_HBLANKB_MASK__SI 0x00000002L -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_PHASE_MASK__SI 0x00000001L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_COLOR_DE_MASK__SI 0x00400000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_COLOR_IN_MASK__SI 0x00000ff0L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_COLOR_OUT_MASK__SI 0x003fc000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL0_OUT_MASK__SI 0x02000000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL1_OUT_MASK__SI 0x04000000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL2_OUT_MASK__SI 0x08000000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL3_OUT_MASK__SI 0x10000000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_DE_IN_MASK__SI 0x00000008L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_HSYNC_IN_MASK__SI 0x00000002L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_HSYNC_OUT_MASK__SI 0x00800000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_PLCTL0_IN_MASK__SI 0x00002000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_PLDEVS_OUT_MASK__SI 0x20000000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_STEREOSYNC_IN_MASK__SI 0x00001000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_VSYNC_IN_MASK__SI 0x00000004L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_VSYNC_OUT_MASK__SI 0x01000000L -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_PIXCLK_MASK__SI 0x00000001L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_CHAR_A_IN_MASK__SI 0x00000002L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_CHAR_B_IN_MASK__SI 0x00000004L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_DCB_MASK__SI 0x001ff000L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_DE_IN_MASK__SI 0x00000008L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_IN_MASK__SI 0x00000ff0L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_TX_MASK__SI 0xffc00000L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_DE_TX_MASK__SI 0x00200000L -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_PIXCLK_MASK__SI 0x00000001L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_PIXCLK_MASK__SI 0x00000001L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_COLOR_DE_IN_MASK__SI 0x00000002L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_COLOR_IN_MASK__SI 0x00000ffcL -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL0_IN_MASK__SI 0x00001000L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL1_IN_MASK__SI 0x00002000L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL2_IN_MASK__SI 0x00004000L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL3_IN_MASK__SI 0x00008000L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_HSYNC_IN_MASK__SI 0x00100000L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_PLPIXA_OUT_MASK__SI 0xffc00000L -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_VSYNC_IN_MASK__SI 0x00200000L -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_DE_MASK__SI 0x00002000L -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_HALF_CLK_PHASE_MASK__SI 0x00004000L -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_PANEL_COLOR_IN_MASK__SI 0x00000ff0L -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_PANEL_DE_IN_MASK__SI 0x00000002L -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_TEST_DATA_MASK__SI 0x007f0000L -#define DIGA_DEBUG7__DOUT_DIGA_PIXCLK1_MASK__SI 0x00001000L -#define DIGA_DEBUG7__DOUT_DIGA_PIXCLK_MASK__SI 0x00000001L -#define DIGA_DEBUG7__DOUT_DIGA_PM_PWRSEQ_TARGET_STATE_MASK__SI 0x01000000L -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_BLON_MASK__SI 0x40000000L -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_DIGON_MASK__SI 0x20000000L -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_DONE_MASK__SI 0x80000000L -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_REF_MASK__SI 0x04000000L -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_SYNCEN_MASK__SI 0x10000000L -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_TARGET_STATE_MASK__SI 0x02000000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DCLOCK1_MASK__SI 0x00008000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DCLOCK_MASK__SI 0x00000008L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DE1_MASK__SI 0x00002000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DE_MASK__SI 0x00000002L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DTMG_CTL2_MASK__SI 0x10000000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DTMG_MASK__SI 0x01000000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_ENABLE_DCLOCK1_MASK__SI 0x00004000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_ENABLE_DCLOCK_MASK__SI 0x00000004L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_HSYNC_CTL0_MASK__SI 0x40000000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_HSYNC_MASK__SI 0x04000000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_LINK0_COLOR_MASK__SI 0x00000ff0L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_LINK1_COLOR_MASK__SI 0x00ff0000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_VSYNC_CTL1_MASK__SI 0x20000000L -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_VSYNC_MASK__SI 0x02000000L -#define DIGA_DEBUG8__DOUT_DIGA_PIXCLK1_MASK__SI 0x00001000L -#define DIGA_DEBUG8__DOUT_DIGA_PIXCLK_MASK__SI 0x00000001L -#define DIGA_HDCP_DEBUG_INFO__DIGA_HDCP_DEBUG_INFO_MASK__SI 0xffffffffL -#define DIGA_LINK_CNTL__DIGA_CHANNEL0_INVERT_MASK__SI 0x00001000L -#define DIGA_LINK_CNTL__DIGA_CHANNEL1_INVERT_MASK__SI 0x00002000L -#define DIGA_LINK_CNTL__DIGA_CHANNEL2_INVERT_MASK__SI 0x00004000L -#define DIGA_LINK_CNTL__DIGA_CHANNEL3_INVERT_MASK__SI 0x00008000L -#define DIGA_LINK_CNTL__DIGA_MINIMUM_PIXVLD_LOW_DURATION_MASK__SI 0x00000700L -#define DIGA_LINK_CNTL__DIGA_PFREQCHG_MASK__SI 0x00000001L -#define DIGA_LINK_CNTL__DIGA_PIXVLD_RESET_MASK__SI 0x00000010L -#define DIGA_LINK_CNTL__DIGA_XBAR_SELECT_MASK__SI 0x00070000L -#define DIGA_TRANSMITTER_ENABLE__DIGA_CLK_EN_MASK__SI 0x00000100L -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE0EN_MASK__SI 0x00000001L -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE1EN_MASK__SI 0x00000002L -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE2EN_MASK__SI 0x00000004L -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE3EN_MASK__SI 0x00000008L -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANEEN_HPD_MASK_MASK__SI 0x00010000L -#define DIGB_CLOCK_ENABLE__DIGB_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_CAPTURE_START_MASK__SI 0x00800000L -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_COLOR_IN_MASK__SI 0x00000ffcL -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_COLOR_OUT_MASK__SI 0xff000000L -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_HBLANKB_MASK__SI 0x00000002L -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_PHASE_MASK__SI 0x00000001L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_COLOR_DE_MASK__SI 0x00400000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_COLOR_IN_MASK__SI 0x00000ff0L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_COLOR_OUT_MASK__SI 0x003fc000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL0_OUT_MASK__SI 0x02000000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL1_OUT_MASK__SI 0x04000000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL2_OUT_MASK__SI 0x08000000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL3_OUT_MASK__SI 0x10000000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_DE_IN_MASK__SI 0x00000008L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_HSYNC_IN_MASK__SI 0x00000002L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_HSYNC_OUT_MASK__SI 0x00800000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_PLCTL0_IN_MASK__SI 0x00002000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_PLDEVS_OUT_MASK__SI 0x20000000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_STEREOSYNC_IN_MASK__SI 0x00001000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_VSYNC_IN_MASK__SI 0x00000004L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_VSYNC_OUT_MASK__SI 0x01000000L -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_PIXCLK_MASK__SI 0x00000001L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_CHAR_A_IN_MASK__SI 0x00000002L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_CHAR_B_IN_MASK__SI 0x00000004L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_DCB_MASK__SI 0x001ff000L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_DE_IN_MASK__SI 0x00000008L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_IN_MASK__SI 0x00000ff0L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_TX_MASK__SI 0xffc00000L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_DE_TX_MASK__SI 0x00200000L -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_PIXCLK_MASK__SI 0x00000001L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_PIXCLK_MASK__SI 0x00000001L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_COLOR_DE_IN_MASK__SI 0x00000002L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_COLOR_IN_MASK__SI 0x00000ffcL -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL0_IN_MASK__SI 0x00001000L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL1_IN_MASK__SI 0x00002000L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL2_IN_MASK__SI 0x00004000L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL3_IN_MASK__SI 0x00008000L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_HSYNC_IN_MASK__SI 0x00100000L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_PLPIXA_OUT_MASK__SI 0xffc00000L -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_VSYNC_IN_MASK__SI 0x00200000L -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_DE_MASK__SI 0x00002000L -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_HALF_CLK_PHASE_MASK__SI 0x00004000L -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_PANEL_COLOR_IN_MASK__SI 0x00000ff0L -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_PANEL_DE_IN_MASK__SI 0x00000002L -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_TEST_DATA_MASK__SI 0x007f0000L -#define DIGB_DEBUG7__DOUT_DIGB_PIXCLK1_MASK__SI 0x00001000L -#define DIGB_DEBUG7__DOUT_DIGB_PIXCLK_MASK__SI 0x00000001L -#define DIGB_DEBUG7__DOUT_DIGB_PM_PWRSEQ_TARGET_STATE_MASK__SI 0x01000000L -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_BLON_MASK__SI 0x40000000L -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_DIGON_MASK__SI 0x20000000L -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_DONE_MASK__SI 0x80000000L -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_REF_MASK__SI 0x04000000L -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_SYNCEN_MASK__SI 0x10000000L -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_TARGET_STATE_MASK__SI 0x02000000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DCLOCK1_MASK__SI 0x00008000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DCLOCK_MASK__SI 0x00000008L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DE1_MASK__SI 0x00002000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DE_MASK__SI 0x00000002L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DTMG_CTL2_MASK__SI 0x10000000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DTMG_MASK__SI 0x01000000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_ENABLE_DCLOCK1_MASK__SI 0x00004000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_ENABLE_DCLOCK_MASK__SI 0x00000004L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_HSYNC_CTL0_MASK__SI 0x40000000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_HSYNC_MASK__SI 0x04000000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_LINK0_COLOR_MASK__SI 0x00000ff0L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_LINK1_COLOR_MASK__SI 0x00ff0000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_VSYNC_CTL1_MASK__SI 0x20000000L -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_VSYNC_MASK__SI 0x02000000L -#define DIGB_DEBUG8__DOUT_DIGB_PIXCLK1_MASK__SI 0x00001000L -#define DIGB_DEBUG8__DOUT_DIGB_PIXCLK_MASK__SI 0x00000001L -#define DIGB_HDCP_DEBUG_INFO__DIGB_HDCP_DEBUG_INFO_MASK__SI 0xffffffffL -#define DIGB_LINK_CNTL__DIGB_CHANNEL0_INVERT_MASK__SI 0x00001000L -#define DIGB_LINK_CNTL__DIGB_CHANNEL1_INVERT_MASK__SI 0x00002000L -#define DIGB_LINK_CNTL__DIGB_CHANNEL2_INVERT_MASK__SI 0x00004000L -#define DIGB_LINK_CNTL__DIGB_CHANNEL3_INVERT_MASK__SI 0x00008000L -#define DIGB_LINK_CNTL__DIGB_MINIMUM_PIXVLD_LOW_DURATION_MASK__SI 0x00000700L -#define DIGB_LINK_CNTL__DIGB_PFREQCHG_MASK__SI 0x00000001L -#define DIGB_LINK_CNTL__DIGB_PIXVLD_RESET_MASK__SI 0x00000010L -#define DIGB_LINK_CNTL__DIGB_XBAR_SELECT_MASK__SI 0x00070000L -#define DIGB_TRANSMITTER_ENABLE__DIGB_CLK_EN_MASK__SI 0x00000100L -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE0EN_MASK__SI 0x00000001L -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE1EN_MASK__SI 0x00000002L -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE2EN_MASK__SI 0x00000004L -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE3EN_MASK__SI 0x00000008L -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANEEN_HPD_MASK_MASK__SI 0x00010000L -#define DIGC_CLOCK_ENABLE__DIGC_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DIGD_CLOCK_ENABLE__DIGD_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DIGE_CLOCK_ENABLE__DIGE_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DIGF_CLOCK_ENABLE__DIGF_CLOCK_ENABLE_MASK__SI 0x00000001L -#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK__SI 0x000003ffL -#define DIG_CNTL__DIG_DUAL_LINK_ENABLE_MASK__SI 0x00010000L -#define DIG_CNTL__DIG_ENABLE_MASK__SI 0x00000100L -#define DIG_CNTL__DIG_HPD_SELECT_MASK__SI 0x70000000L -#define DIG_CNTL__DIG_MODE_MASK__SI 0x00007000L -#define DIG_CNTL__DIG_RB_SWITCH_EN_MASK__SI 0x00100000L -#define DIG_CNTL__DIG_SOURCE_SELECT_MASK__SI 0x00000007L -#define DIG_CNTL__DIG_START_MASK__SI 0x00000400L -#define DIG_CNTL__DIG_STEREOSYNC_SELECT_MASK__SI 0x00000070L -#define DIG_CNTL__DIG_SWAP_MASK__SI 0x00040000L -#define DIG_DEBUG__DIG_DEBUG_MASK__SI 0xffffffffL -#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK__SI 0x00000300L -#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK__SI 0x00000001L -#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK__SI 0x00000010L -#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK__SI 0x3fffffffL -#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK__SI 0x00ffffffL -#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK__SI 0x01000000L -#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK__SI 0x00000002L -#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK__SI 0x00000010L -#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK__SI 0x00000020L -#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK__SI 0x03ff0000L -#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK__SI 0x00000040L -#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK__SI 0x00000001L -#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK__SI 0x00000100L -#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK__SI 0x00000004L -#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK__SI 0x00000ff0L -#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK__SI 0x0000000fL -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_CRTC0_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_DCP0_PIXPIPE_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_DCP0_REQ_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_SCL0_ALU_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_SCL0_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_CRTC1_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_DCP1_PIXPIPE_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_DCP1_REQ_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_SCL1_ALU_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_SCL1_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_CRTC2_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_DCP2_PIXPIPE_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_DCP2_REQ_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_SCL2_ALU_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_SCL2_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_CRTC3_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_DCP3_PIXPIPE_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_DCP3_REQ_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_SCL3_ALU_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_SCL3_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_CRTC4_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_DCP4_PIXPIPE_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_DCP4_REQ_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_SCL4_ALU_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_SCL4_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_CRTC5_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_DCP5_PIXPIPE_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_DCP5_REQ_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_SCL5_ALU_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_SCL5_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF0_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF1_SOFT_RESET_MASK__SI 0x00000020L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF2_SOFT_RESET_MASK__SI 0x00000040L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF3_SOFT_RESET_MASK__SI 0x00000080L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF4_SOFT_RESET_MASK__SI 0x00000100L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF5_SOFT_RESET_MASK__SI 0x00000200L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_FBC_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_M_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_VGA_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_VIP_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_ABM_SOFT_RESET_MASK__SI 0x00200000L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DACA_SOFT_RESET_MASK__SI 0x00010000L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DACB_SOFT_RESET_MASK__SI 0x00020000L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGA_SOFT_RESET_MASK__SI 0x00000100L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGB_SOFT_RESET_MASK__SI 0x00000200L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGC_SOFT_RESET_MASK__SI 0x00000400L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGD_SOFT_RESET_MASK__SI 0x00000800L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGE_SOFT_RESET_MASK__SI 0x00001000L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGF_SOFT_RESET_MASK__SI 0x00002000L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DISPOUT_SOFT_RESET_MASK__SI 0x00100000L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DVO_SOFT_RESET_MASK__SI 0x00040000L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT0_SOFT_RESET_MASK__SI 0x00000001L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT1_SOFT_RESET_MASK__SI 0x00000002L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT2_SOFT_RESET_MASK__SI 0x00000004L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT3_SOFT_RESET_MASK__SI 0x00000008L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT4_SOFT_RESET_MASK__SI 0x00000010L -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT5_SOFT_RESET_MASK__SI 0x00000020L -#define DISPOUT_DEBUG_ID__DEBUG_ID_MASK__SI 0xffffffffL -#define DISPOUT_SOFT_RESET__DACACLK_SOFT_RESET_MASK__SI 0x00000001L -#define DISPOUT_SOFT_RESET__DACBCLK_SOFT_RESET_MASK__SI 0x00000002L -#define DISPOUT_SOFT_RESET__DVO_ENABLE_RST_MASK__SI 0x00000008L -#define DISPOUT_SOFT_RESET__MVP_CLKA_SOFT_RESET_MASK__SI 0x00010000L -#define DISPOUT_SOFT_RESET__MVP_CLKB_SOFT_RESET_MASK__SI 0x00020000L -#define DISPOUT_SOFT_RESET__PCLK_TVOUT_SOFT_RESET_MASK__SI 0x00100000L -#define DISPOUT_SOFT_RESET__SOFT_RESET_DVO_MASK__SI 0x00000004L -#define DISPOUT_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK__SI 0x10000000L -#define DISPOUT_SOFT_RESET__SYMCLKA_DSYNC_SOFT_RESET_MASK__SI 0x00000020L -#define DISPOUT_SOFT_RESET__SYMCLKA_SOFT_RESET_MASK__SI 0x00000010L -#define DISPOUT_SOFT_RESET__SYMCLKB_DSYNC_SOFT_RESET_MASK__SI 0x00000080L -#define DISPOUT_SOFT_RESET__SYMCLKB_SOFT_RESET_MASK__SI 0x00000040L -#define DISPOUT_SOFT_RESET__SYMCLKC_DSYNC_SOFT_RESET_MASK__SI 0x00000200L -#define DISPOUT_SOFT_RESET__SYMCLKC_SOFT_RESET_MASK__SI 0x00000100L -#define DISPOUT_SOFT_RESET__SYMCLKD_DSYNC_SOFT_RESET_MASK__SI 0x00000800L -#define DISPOUT_SOFT_RESET__SYMCLKD_SOFT_RESET_MASK__SI 0x00000400L -#define DISPOUT_SOFT_RESET__SYMCLKE_DSYNC_SOFT_RESET_MASK__SI 0x00002000L -#define DISPOUT_SOFT_RESET__SYMCLKE_SOFT_RESET_MASK__SI 0x00001000L -#define DISPOUT_SOFT_RESET__SYMCLKF_DSYNC_SOFT_RESET_MASK__SI 0x00008000L -#define DISPOUT_SOFT_RESET__SYMCLKF_SOFT_RESET_MASK__SI 0x00004000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX1_LS_DONE_INTERRUPT_MASK__SI 0x00000040L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX1_SW_DONE_INTERRUPT_MASK__SI 0x00000020L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX2_LS_DONE_INTERRUPT_MASK__SI 0x00000100L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX2_SW_DONE_INTERRUPT_MASK__SI 0x00000080L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK__SI 0x00000400L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK__SI 0x00000200L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX4_LS_DONE_INTERRUPT_MASK__SI 0x00001000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX4_SW_DONE_INTERRUPT_MASK__SI 0x00000800L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX5_LS_DONE_INTERRUPT_MASK__SI 0x00010000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX5_SW_DONE_INTERRUPT_MASK__SI 0x00008000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX6_LS_DONE_INTERRUPT_MASK__SI 0x00040000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX6_SW_DONE_INTERRUPT_MASK__SI 0x00020000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DACA_CAPTURE_START_INTERRUPT_MASK__SI 0x00800000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DACB_CAPTURE_START_INTERRUPT_MASK__SI 0x01000000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK__SI 0x00000001L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD5_INTERRUPT_MASK__SI 0x00080000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD5_RX_INTERRUPT_MASK__SI 0x00100000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD6_INTERRUPT_MASK__SI 0x00200000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD6_RX_INTERRUPT_MASK__SI 0x00400000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_CAPTURE_START_INTERRUPT_MASK__SI 0x02000000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK__SI \ - 0x00002000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT_MASK__SI 0x00000004L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK__SI 0x00000002L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_CAPTURE_START_INTERRUPT_MASK__SI 0x04000000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK__SI \ - 0x00004000L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT_MASK__SI 0x00000010L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK__SI 0x00000008L -#define DISP_INTERRUPT_STATUS_CONTINUE2__DVOA_CAPTURE_START_INTERRUPT_MASK__SI 0x08000000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D1MODE_DATA_UNDERFLOW_INTERRUPT_MASK__SI 0x00010000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D1MODE_REQUEST_UNDERFLOW_INTERRUPT_MASK__SI 0x00020000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D1SCL_DATA_UNDERFLOW_INTERRUPT_MASK__SI 0x00040000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D1SCL_HOST_CONFLICT_INTERRUPT_MASK__SI 0x00080000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D2MODE_DATA_UNDERFLOW_INTERRUPT_MASK__SI 0x00100000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D2MODE_REQUEST_UNDERFLOW_INTERRUPT_MASK__SI 0x00200000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D2SCL_DATA_UNDERFLOW_INTERRUPT_MASK__SI 0x00400000L -#define DISP_INTERRUPT_STATUS_CONTINUE__D2SCL_HOST_CONFLICT_INTERRUPT_MASK__SI 0x00800000L -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD1_RX_INTERRUPT_MASK__SI 0x20000000L -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK__SI 0x40000000L -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD3_INTERRUPT_MASK__SI 0x10000000L -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD4_INTERRUPT_MASK__SI 0x00004000L -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD4_RX_INTERRUPT_MASK__SI 0x00008000L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_AUTH_FAIL_INTERRUPT_MASK__SI 0x00000020L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_AUTH_SUCCESS_INTERRUPT_MASK__SI 0x00000010L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_I2C_XFER_DONE_INTERRUPT_MASK__SI 0x00000080L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_I2C_XFER_REQ_INTERRUPT_MASK__SI 0x00000040L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_FAIL_INTERRUPT_MASK__SI 0x00000200L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_SUCCESS_INTERRUPT_MASK__SI 0x00000100L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_DONE_INTERRUPT_MASK__SI 0x00000800L -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_REQ_INTERRUPT_MASK__SI 0x00000400L -#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK__SI 0x80000000L -#define DISP_INTERRUPT_STATUS_CONTINUE__DMCU_SCP_INT_MASK__SI 0x00000002L -#define DISP_INTERRUPT_STATUS_CONTINUE__HDMI0_ERROR_INTERRUPT_MASK__SI 0x04000000L -#define DISP_INTERRUPT_STATUS_CONTINUE__HDMI1_ERROR_INTERRUPT_MASK__SI 0x08000000L -#define DISP_INTERRUPT_STATUS_CONTINUE__MVP_FIFO_ERROR_INTERRUPT_MASK__SI 0x01000000L -#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK__SI 0x40000000L -#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK__SI 0x10000000L -#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK__SI 0x20000000L -#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK__SI 0x00000100L -#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK__SI 0x00000080L -#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK__SI 0x02000000L -#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK__SI 0x00000040L -#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK__SI 0x00000200L -#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK__SI 0x00000400L -#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK__SI 0x00800000L -#define DISP_INTERRUPT_STATUS__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK__SI 0x00002000L -#define DISP_INTERRUPT_STATUS__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK__SI 0x00001000L -#define DISP_INTERRUPT_STATUS__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK__SI 0x04000000L -#define DISP_INTERRUPT_STATUS__CRTC2_SNAPSHOT_INTERRUPT_MASK__SI 0x00000800L -#define DISP_INTERRUPT_STATUS__CRTC2_TRIGA_INTERRUPT_MASK__SI 0x00004000L -#define DISP_INTERRUPT_STATUS__CRTC2_TRIGB_INTERRUPT_MASK__SI 0x00008000L -#define DISP_INTERRUPT_STATUS__CRTC2_VSYNC_NOM_INTERRUPT_MASK__SI 0x01000000L -#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK__SI 0x00010000L -#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK__SI 0x00020000L -#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK__SI 0x00040000L -#define DISP_INTERRUPT_STATUS__DC_HPD2_INTERRUPT_MASK__SI 0x00080000L -#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK__SI 0x00200000L -#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK__SI 0x00100000L -#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK__SI 0x80000000L -#define DISP_INTERRUPT_STATUS__DISP_TIMER_INTERRUPT_MASK__SI 0x00400000L -#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK__SI 0x08000000L -#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK__SI 0x00000010L -#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK__SI 0x00000004L -#define DISP_INTERRUPT_STATUS__LB_D2_VBLANK_INTERRUPT_MASK__SI 0x00000020L -#define DISP_INTERRUPT_STATUS__LB_D2_VLINE_INTERRUPT_MASK__SI 0x00000008L -#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK__SI 0x00000001L -#define DISP_INTERRUPT_STATUS__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK__SI 0x00000002L -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK__SI 0x01ffffffL -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK__SI 0x02000000L -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SI 0x40000000L -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK__SI 0x08000000L -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK__SI 0x04000000L -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK__SI 0x20000000L -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK__SI 0x10000000L -#define DLL_CNTL__DLL_LOCK_TIME_MASK__SI__CI 0x003ff000L -#define DLL_CNTL__DLL_RESET_TIME_MASK__SI__CI 0x000003ffL -#define DLL_CNTL__MRDCK0_BYPASS_MASK__SI__CI 0x01000000L -#define DLL_CNTL__MRDCK1_BYPASS_MASK__SI__CI 0x02000000L -#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK__SI 0x00000001L -#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK__SI 0xffffff80L -#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK__SI \ - 0x0000007eL -#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK__SI 0xffffffffL -#define DMA_VIP0_TABLE_ADDR__DMA_VIPH_TABLE_ADDR_MASK__SI 0xffffffffL -#define DMA_VIP1_TABLE_ADDR__DMA_VIPH_TABLE_ADDR_MASK__SI 0xffffffffL -#define DMA_VIP2_TABLE_ADDR__DMA_VIPH_TABLE_ADDR_MASK__SI 0xffffffffL -#define DMA_VIP3_TABLE_ADDR__DMA_VIPH_TABLE_ADDR_MASK__SI 0xffffffffL -#define DMA_VIPH0_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT_MASK__SI 0xffffffffL -#define DMA_VIPH0_COMMAND__BYTE_COUNT_MASK__SI 0x001fffffL -#define DMA_VIPH0_COMMAND__DEST_OFFSET_HOLD_MASK__SI 0x20000000L -#define DMA_VIPH0_COMMAND__END_OF_LIST_STATUS_MASK__SI 0x80000000L -#define DMA_VIPH0_COMMAND__INTERRUPT_DIS_MASK__SI 0x40000000L -#define DMA_VIPH0_COMMAND__SOURCE_OFFSET_HOLD_MASK__SI 0x10000000L -#define DMA_VIPH0_COMMAND__SWAP_CONTROL_MASK__SI 0x03000000L -#define DMA_VIPH0_COMMAND__TRANSFER_DEST_MASK__SI 0x08000000L -#define DMA_VIPH0_COMMAND__TRANSFER_SOURCE_MASK__SI 0x04000000L -#define DMA_VIPH0_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH0_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH0_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH1_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT_MASK__SI 0xffffffffL -#define DMA_VIPH1_COMMAND__BYTE_COUNT_MASK__SI 0x001fffffL -#define DMA_VIPH1_COMMAND__DEST_OFFSET_HOLD_MASK__SI 0x20000000L -#define DMA_VIPH1_COMMAND__END_OF_LIST_STATUS_MASK__SI 0x80000000L -#define DMA_VIPH1_COMMAND__INTERRUPT_DIS_MASK__SI 0x40000000L -#define DMA_VIPH1_COMMAND__SOURCE_OFFSET_HOLD_MASK__SI 0x10000000L -#define DMA_VIPH1_COMMAND__SWAP_CONTROL_MASK__SI 0x03000000L -#define DMA_VIPH1_COMMAND__TRANSFER_DEST_MASK__SI 0x08000000L -#define DMA_VIPH1_COMMAND__TRANSFER_SOURCE_MASK__SI 0x04000000L -#define DMA_VIPH1_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH1_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH1_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH2_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT_MASK__SI 0xffffffffL -#define DMA_VIPH2_COMMAND__BYTE_COUNT_MASK__SI 0x001fffffL -#define DMA_VIPH2_COMMAND__DEST_OFFSET_HOLD_MASK__SI 0x20000000L -#define DMA_VIPH2_COMMAND__END_OF_LIST_STATUS_MASK__SI 0x80000000L -#define DMA_VIPH2_COMMAND__INTERRUPT_DIS_MASK__SI 0x40000000L -#define DMA_VIPH2_COMMAND__SOURCE_OFFSET_HOLD_MASK__SI 0x10000000L -#define DMA_VIPH2_COMMAND__SWAP_CONTROL_MASK__SI 0x03000000L -#define DMA_VIPH2_COMMAND__TRANSFER_DEST_MASK__SI 0x08000000L -#define DMA_VIPH2_COMMAND__TRANSFER_SOURCE_MASK__SI 0x04000000L -#define DMA_VIPH2_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH2_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH2_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH3_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT_MASK__SI 0xffffffffL -#define DMA_VIPH3_COMMAND__BYTE_COUNT_MASK__SI 0x001fffffL -#define DMA_VIPH3_COMMAND__DEST_OFFSET_HOLD_MASK__SI 0x20000000L -#define DMA_VIPH3_COMMAND__END_OF_LIST_STATUS_MASK__SI 0x80000000L -#define DMA_VIPH3_COMMAND__INTERRUPT_DIS_MASK__SI 0x40000000L -#define DMA_VIPH3_COMMAND__SOURCE_OFFSET_HOLD_MASK__SI 0x10000000L -#define DMA_VIPH3_COMMAND__SWAP_CONTROL_MASK__SI 0x03000000L -#define DMA_VIPH3_COMMAND__TRANSFER_DEST_MASK__SI 0x08000000L -#define DMA_VIPH3_COMMAND__TRANSFER_SOURCE_MASK__SI 0x04000000L -#define DMA_VIPH3_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH3_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH3_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH_MASK__SI 0x0000000fL -#define DMA_VIPH_ABORT__DMA_VIPH0_ABORT_EN_MASK__SI 0x00000008L -#define DMA_VIPH_ABORT__DMA_VIPH0_RESET_MASK__SI 0x00100000L -#define DMA_VIPH_ABORT__DMA_VIPH1_ABORT_EN_MASK__SI 0x00000080L -#define DMA_VIPH_ABORT__DMA_VIPH1_RESET_MASK__SI 0x00200000L -#define DMA_VIPH_ABORT__DMA_VIPH2_ABORT_EN_MASK__SI 0x00000800L -#define DMA_VIPH_ABORT__DMA_VIPH2_RESET_MASK__SI 0x00400000L -#define DMA_VIPH_ABORT__DMA_VIPH3_ABORT_EN_MASK__SI 0x00008000L -#define DMA_VIPH_ABORT__DMA_VIPH3_RESET_MASK__SI 0x00800000L -#define DMA_VIPH_CHUNK_0__DMA_VIPH0_NOCHUNK_MASK__SI 0x80000000L -#define DMA_VIPH_CHUNK_0__DMA_VIPH0_TABLE_SWAP_MASK__SI 0x000000c0L -#define DMA_VIPH_CHUNK_0__DMA_VIPH1_NOCHUNK_MASK__SI 0x40000000L -#define DMA_VIPH_CHUNK_0__DMA_VIPH1_TABLE_SWAP_MASK__SI 0x00000030L -#define DMA_VIPH_CHUNK_0__DMA_VIPH2_NOCHUNK_MASK__SI 0x20000000L -#define DMA_VIPH_CHUNK_0__DMA_VIPH2_TABLE_SWAP_MASK__SI 0x0000000cL -#define DMA_VIPH_CHUNK_0__DMA_VIPH3_NOCHUNK_MASK__SI 0x10000000L -#define DMA_VIPH_CHUNK_0__DMA_VIPH3_TABLE_SWAP_MASK__SI 0x00000003L -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP0_CHUNK_MASK__SI 0x000000ffL -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP1_CHUNK_MASK__SI 0x0000ff00L -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP2_CHUNK_MASK__SI 0x00ff0000L -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP3_CHUNK_MASK__SI 0xff000000L -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_READ_TIMEOUT_STATUS_MASK__SI 0x00000100L -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_READ_TIMEOUT_TO_PRIORITY_EN_MASK__SI 0x00000080L -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_READ_TIMER_MASK__SI 0x0000000fL -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_URGENT_EN_MASK__SI 0x00000200L -#define DMA_VIPH_STATUS__DMA_VIPH0_ACTIVE_MASK__SI 0x01000000L -#define DMA_VIPH_STATUS__DMA_VIPH0_AVAIL_MASK__SI 0x0000000fL -#define DMA_VIPH_STATUS__DMA_VIPH0_CURRENT_MASK__SI 0x00030000L -#define DMA_VIPH_STATUS__DMA_VIPH1_ACTIVE_MASK__SI 0x02000000L -#define DMA_VIPH_STATUS__DMA_VIPH1_AVAIL_MASK__SI 0x000000f0L -#define DMA_VIPH_STATUS__DMA_VIPH1_CURRENT_MASK__SI 0x000c0000L -#define DMA_VIPH_STATUS__DMA_VIPH2_ACTIVE_MASK__SI 0x04000000L -#define DMA_VIPH_STATUS__DMA_VIPH2_AVAIL_MASK__SI 0x00000f00L -#define DMA_VIPH_STATUS__DMA_VIPH2_CURRENT_MASK__SI 0x00300000L -#define DMA_VIPH_STATUS__DMA_VIPH3_ACTIVE_MASK__SI 0x08000000L -#define DMA_VIPH_STATUS__DMA_VIPH3_AVAIL_MASK__SI 0x0000f000L -#define DMA_VIPH_STATUS__DMA_VIPH3_CURRENT_MASK__SI 0x00c00000L -#define DMA_VIPH_STATUS__VIP_RBBM_H0DMA_IDLE_MASK__SI 0x10000000L -#define DMA_VIPH_STATUS__VIP_RBBM_H1DMA_IDLE_MASK__SI 0x20000000L -#define DMA_VIPH_STATUS__VIP_RBBM_H2DMA_IDLE_MASK__SI 0x40000000L -#define DMA_VIPH_STATUS__VIP_RBBM_H3DMA_IDLE_MASK__SI 0x80000000L -#define DMA_VIPH_WRCOMB__VIPDMA_WRCOMB_BYPASS_MASK__SI 0x00020000L -#define DMA_VIPH_WRCOMB__VIPDMA_WRCOMB_TIMEOUT_MASK__SI 0x0000ffffL -#define DMA_VIPH_WRCOMB__WRCOMB_STAT_EN_MASK__SI 0x00040000L -#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK__SI 0x00000004L -#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK__SI 0x00000008L -#define DMCU_CTRL__IGNORE_PWRMGT_MASK__SI 0x00000002L -#define DMCU_CTRL__RESET_UC_MASK__SI 0x00000001L -#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK__SI 0xffc00000L -#define DMCU_DEBUG_00__DBG_DMCU_abm1_dmcu_bl_update_interrupt_MASK__SI 0x00000400L -#define DMCU_DEBUG_00__DBG_DMCU_abm1_dmcu_hg_ready_interrupt_MASK__SI 0x00000100L -#define DMCU_DEBUG_00__DBG_DMCU_abm1_dmcu_ls_ready_interrupt_MASK__SI 0x00000200L -#define DMCU_DEBUG_00__DBG_DMCU_ack_MASK__SI 0x00004000L -#define DMCU_DEBUG_00__DBG_DMCU_ihc_abm1_bl_update_interrupt_MASK__SI 0x00000080L -#define DMCU_DEBUG_00__DBG_DMCU_ihc_abm1_hg_ready_interrupt_MASK__SI 0x00000020L -#define DMCU_DEBUG_00__DBG_DMCU_ihc_abm1_ls_ready_interrupt_MASK__SI 0x00000040L -#define DMCU_DEBUG_00__DBG_DMCU_ihc_dmcu_internal_interrupt_MASK__SI 0x00000008L -#define DMCU_DEBUG_00__DBG_DMCU_ihc_scp_interrput_MASK__SI 0x00000010L -#define DMCU_DEBUG_00__DBG_DMCU_mcp_intc_interrupt_MASK__SI 0x00000800L -#define DMCU_DEBUG_00__DBG_DMCU_pwr_MASK__SI 0x00002000L -#define DMCU_DEBUG_00__DBG_DMCU_scp_intc_interrupt_MASK__SI 0x00001000L -#define DMCU_DEBUG_00__DBG_DMCU_uc_irq_n_MASK__SI 0x00000004L -#define DMCU_DEBUG_00__DBG_DMCU_uc_rst_n_MASK__SI 0x00000001L -#define DMCU_DEBUG_00__DBG_DMCU_uc_xirq_n_MASK__SI 0x00000002L -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_addr_MASK__SI 0xffff0000L -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_as_MASK__SI 0x00000800L -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_cs_MASK__SI 0x00000400L -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_data_out_MASK__SI 0x000000ffL -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_rd_MASK__SI 0x00000100L -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_wr_MASK__SI 0x00000200L -#define DMCU_DEBUG_02__DBG_DMCU_eramarb_uc_mem_data_in_MASK__SI 0x000000ffL -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_addr_MASK__SI 0xffff0000L -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_as_MASK__SI 0x00000800L -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_cs_MASK__SI 0x00000400L -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_rd_MASK__SI 0x00000100L -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_wr_MASK__SI 0x00000200L -#define DMCU_DEBUG_03__DBG_DMCU_iramarb_uc_mem_data_in_MASK__SI 0xff000000L -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_addr_MASK__SI 0x00ff0000L -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_as_MASK__SI 0x00000800L -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_cs_MASK__SI 0x00000400L -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_data_out_MASK__SI 0x000000ffL -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_rd_MASK__SI 0x00000100L -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_wr_MASK__SI 0x00000200L -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_addr_MASK__SI 0x00001fffL -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_we_MASK__SI 0x00008000L -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_wem_MASK__SI 0x00f80000L -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_wr_data_MASK__SI 0xff000000L -#define DMCU_DEBUG_04__DBG_DMCU_eram_xa_ctrl_ReqHandlerState_MASK__SI 0x00070000L -#define DMCU_DEBUG_04__DBG_DMCU_eramarb_eramxac_rtr_MASK__SI 0x00002000L -#define DMCU_DEBUG_04__DBG_DMCU_eramxac_eramarb_rts_MASK__SI 0x00004000L -#define DMCU_DEBUG_05__DBG_DMCU_DCMEM_DMCU_eram_rd_data_MASK__SI 0xff000000L -#define DMCU_DEBUG_05__DBG_DMCU_DMCU_DCMEM_eram_addr_MASK__SI 0x00001fffL -#define DMCU_DEBUG_05__DBG_DMCU_DMCU_DCMEM_eram_we_MASK__SI 0x00008000L -#define DMCU_DEBUG_05__DBG_DMCU_eram_xa_ctrl_ReqHandlerState_MASK__SI 0x00070000L -#define DMCU_DEBUG_05__DBG_DMCU_eramarb_eramxac_rtr_MASK__SI 0x00002000L -#define DMCU_DEBUG_05__DBG_DMCU_eramxac_eramarb_rts_MASK__SI 0x00004000L -#define DMCU_DEBUG_06__DBG_DMCU_DMCU_DCMEM_eram_wr_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_07__DBG_DMCU_DMCU_DCMEM_eram_wem_MASK__SI 0xffffffffL -#define DMCU_DEBUG_08__DBG_DMCU_DCMEM_DMCU_eram_rd_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_addr_MASK__SI 0x000000ffL -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_we_MASK__SI 0x00008000L -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_wem_MASK__SI 0x00f80000L -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_wr_data_MASK__SI 0xff000000L -#define DMCU_DEBUG_09__DBG_DMCU_iram_xa_ctrl_ReqHandlerState_MASK__SI 0x00070000L -#define DMCU_DEBUG_0A__DBG_DMCU_DCMEM_DMCU_iram_rd_data_MASK__SI 0x0000ff00L -#define DMCU_DEBUG_0A__DBG_DMCU_DMCU_DCMEM_iram_addr_MASK__SI 0x000000ffL -#define DMCU_DEBUG_0B__DBG_DMCU_DMCU_DCMEM_eram_wr_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_ctrl_wr_accepted_MASK__SI 0x00080000L -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_ctrl_wr_addr_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_ctrl_wr_be_MASK__SI 0x00070000L -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_data_MASK__SI 0xff000000L -#define DMCU_DEBUG_0D__DBG_DMCU_dmcu_intreg_wr_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_ctrl_rd_addr_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_ctrl_rd_data_valid_MASK__SI 0x80000000L -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_ctrl_wait4rd_return_data_MASK__SI 0x40000000L -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_data_MASK__SI 0x3fff0000L -#define DMCU_DEBUG_0F__DBG_DMCU_dmcu_intreg_rd_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_a_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_be_MASK__SI 0x00780000L -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_rts_MASK__SI 0x00020000L -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_wd_MASK__SI 0xff000000L -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_we_MASK__SI 0x00040000L -#define DMCU_DEBUG_10__DBG_DMCU_RBBMARB_DMCU_rtr_MASK__SI 0x00010000L -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_a_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_be_MASK__SI 0x00c00000L -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_re_MASK__SI 0x00040000L -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_rts_MASK__SI 0x00020000L -#define DMCU_DEBUG_11__DBG_DMCU_RBBMARB_DMCU_rdo_MASK__SI 0xff000000L -#define DMCU_DEBUG_11__DBG_DMCU_RBBMARB_DMCU_rtr_MASK__SI 0x00010000L -#define DMCU_DEBUG_11__DBG_DMCU_rbbm_if_ReqFifoDeqState_MASK__SI 0x00380000L -#define DMCU_DEBUG_12__DBG_DMCU_DMCU_RBBMARB_wd_MASK__SI 0xffffffffL -#define DMCU_DEBUG_13__DBG_DMCU_RBBMARB_DMCU_rdo_MASK__SI 0xffffffffL -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_ReqEnq_DataDeq_State_MASK__SI 0x00000070L -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_din_MASK__SI 0x00ffff00L -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_empty_MASK__SI 0x00000008L -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_full_MASK__SI 0x00000004L -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_q_MASK__SI 0xff000000L -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_re_MASK__SI 0x00000002L -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_we_MASK__SI 0x00000001L -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_ReqEnq_DataDeq_State_MASK__SI 0x00000070L -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_din_MASK__SI 0x00ffff00L -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_empty_MASK__SI 0x00000008L -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_full_MASK__SI 0x00000004L -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_q_MASK__SI 0xff000000L -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_re_MASK__SI 0x00000002L -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_we_MASK__SI 0x00000001L -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Addr_MASK__SI 0xffff0000L -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Be_MASK__SI 0x000000f0L -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Complete_MASK__SI 0x00004000L -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Req_MASK__SI 0x00002000L -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_WriteData_MASK__SI 0x0000000fL -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Write_MASK__SI 0x00008000L -#define DMCU_DEBUG_16__DBG_DMCU_mbus_if_DcregAccessState_MASK__SI 0x00000f00L -#define DMCU_DEBUG_16__DBG_DMCU_pending_req_on_mbus_MASK__SI 0x00001000L -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Addr_MASK__SI 0xffff0000L -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Be_MASK__SI 0x000000f0L -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Complete_MASK__SI 0x00004000L -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_ReadData_MASK__SI 0x0000000fL -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Req_MASK__SI 0x00002000L -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Write_MASK__SI 0x00008000L -#define DMCU_DEBUG_17__DBG_DMCU_mbus_if_DcregAccessState_MASK__SI 0x00000f00L -#define DMCU_DEBUG_17__DBG_DMCU_pending_req_on_mbus_MASK__SI 0x00001000L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_eramarb_mem_dec_MASK__SI 0x00000040L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_iramarb_mem_dec_MASK__SI 0x00000080L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_dcreg_dec_MASK__SI 0x00000001L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_interrupt_status_reg_dec_MASK__SI 0x00000020L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_rd_ctrl_dec_MASK__SI 0x00000008L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_rd_data_dec_MASK__SI 0x00000010L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_wr_ctrl_dec_MASK__SI 0x00000002L -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_wr_data_dec_MASK__SI 0x00000004L -#define DMCU_DEBUG_19__DBG_DMCU_MBUS_WriteData_MASK__SI 0xffffffffL -#define DMCU_DEBUG_20__DBG_DMCU_MBUS_ReadData_MASK__SI 0xffffffffL -#define DMCU_DEBUG_21__DBG_DMCU_eram_xa_ctrl_ReqHandlerState_MASK__SI 0x00000007L -#define DMCU_DEBUG_21__DBG_DMCU_iram_xa_ctrl_ReqHandlerState_MASK__SI 0x00000038L -#define DMCU_DEBUG_21__DBG_DMCU_mbus_if_DcregAccessState_MASK__SI 0x00000f00L -#define DMCU_DEBUG_21__DBG_DMCU_rbbm_if_ReqEnq_DataDeq_State_MASK__SI 0x00070000L -#define DMCU_DEBUG_21__DBG_DMCU_rbbm_if_ReqFifoDeqState_MASK__SI 0x07000000L -#define DMCU_DEBUG_22__DBG_DMCU_sfr_addr_MASK__SI 0x0000ff00L -#define DMCU_DEBUG_22__DBG_DMCU_sfr_data_in_MASK__SI 0xff000000L -#define DMCU_DEBUG_22__DBG_DMCU_sfr_data_out_MASK__SI 0x000000ffL -#define DMCU_DEBUG_22__DBG_DMCU_sfr_rd_MASK__SI 0x00020000L -#define DMCU_DEBUG_22__DBG_DMCU_sfr_wp_MASK__SI 0x00040000L -#define DMCU_DEBUG_22__DBG_DMCU_sfr_wr_MASK__SI 0x00010000L -#define DMCU_DEBUG_23__DBG_DMCU_DMCU_DCMEM_eram_last_rd_addr_MASK__SI 0x1fff0000L -#define DMCU_DEBUG_23__DBG_DMCU_DMCU_DCMEM_eram_last_wr_addr_MASK__SI 0x00001fffL -#define DMCU_DEBUG_24__DBG_DMCU_DMCU_DCMEM_eram_last_wr_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_25__DBG_DMCU_DMCU_DCMEM_eram_last_wr_wem_MASK__SI 0xffffffffL -#define DMCU_DEBUG_26__DBG_DMCU_DCMEM_DMCU_eram_last_rd_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_27__DBG_DMCU_DMCU_DCMEM_iram_last_rd_addr_MASK__SI 0x0000ff00L -#define DMCU_DEBUG_27__DBG_DMCU_DMCU_DCMEM_iram_last_wr_addr_MASK__SI 0x000000ffL -#define DMCU_DEBUG_28__DBG_DMCU_DCMEM_DMCU_iram_last_rd_data_MASK__SI 0x00ff0000L -#define DMCU_DEBUG_28__DBG_DMCU_DMCU_DCMEM_iram_last_wem_MASK__SI 0x0000ff00L -#define DMCU_DEBUG_28__DBG_DMCU_DMCU_DCMEM_iram_last_wr_data_MASK__SI 0x000000ffL -#define DMCU_DEBUG_29__DBG_DMCU_DMCU_RBBMARB_last_rd_addr_MASK__SI 0xffff0000L -#define DMCU_DEBUG_29__DBG_DMCU_DMCU_RBBMARB_last_wr_addr_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_2A__DBG_DMCU_DMCU_RBBMARB_last_wr_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_2B__DBG_DMCU_DMCU_RBBMARB_last_wr_be_MASK__SI 0x0000000fL -#define DMCU_DEBUG_2C__DBG_DMCU_RBBMARB_DMCU_last_rd_data_MASK__SI 0xffffffffL -#define DMCU_DEBUG_32__DBG_DMCU_uc_pc_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_32__DBG_DMCU_uc_sp_MASK__SI 0xffff0000L -#define DMCU_DEBUG_33__DBG_DMCU_uc_index_x_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_33__DBG_DMCU_uc_index_y_MASK__SI 0xffff0000L -#define DMCU_DEBUG_34__DBG_DMCU_uc_accumulator_a_MASK__SI 0x000000ffL -#define DMCU_DEBUG_34__DBG_DMCU_uc_accumulator_b_MASK__SI 0x0000ff00L -#define DMCU_DEBUG_35__DBG_DMCU_uc_mathareg_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_35__DBG_DMCU_uc_mathbreg_MASK__SI 0xffff0000L -#define DMCU_DEBUG_36__DBG_DMCU_uc_mathcreg_MASK__SI 0xffffffffL -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_c_MASK__SI 0x00000001L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_h_MASK__SI 0x00000004L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_i_MASK__SI 0x00000002L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_n_MASK__SI 0x00000008L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_s_MASK__SI 0x00000010L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_v_MASK__SI 0x00000020L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_x_MASK__SI 0x00000040L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_x_override_MASK__SI 0x00000100L -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_z_MASK__SI 0x00000080L -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch1_MASK__SI 0x000000ffL -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch2_MASK__SI 0x0000ff00L -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch3_MASK__SI 0x00ff0000L -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch4_MASK__SI 0xff000000L -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch5_MASK__SI 0x000000ffL -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch6_MASK__SI 0x0000ff00L -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch7_MASK__SI 0x00ff0000L -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch8_MASK__SI 0xff000000L -#define DMCU_DEBUG_3A__DBG_DMCU_sfr_disable_irq_to_uc_MASK__SI 0x00000001L -#define DMCU_DEBUG_3A__DBG_DMCU_sfr_disable_xirq_to_uc_MASK__SI 0x00000002L -#define DMCU_DEBUG_CONSTANT__DBG_DMCU_5a5a_MASK__SI 0x0000ffffL -#define DMCU_DEBUG_CONSTANT__DBG_DMCU_beef_MASK__SI 0xffff0000L -#define DMCU_DEBUG_ID__DMCU_DEBUG_ID_MASK__SI 0xffffffffL -#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK__SI 0x0000ffffL -#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK__SI 0x000f0000L -#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK__SI 0x00100000L -#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK__SI 0xffffffffL -#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK__SI 0x0000ffffL -#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK__SI 0x000f0000L -#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK__SI 0x00100000L -#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK__SI 0xffffffffL -#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK__SI 0x00000001L -#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK__SI 0x00800000L -#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK__SI 0x007f0000L -#define DMCU_EVENT_TRIGGER__UC_PWR_UP_DOWN_COMPLETE_STATUS_MASK__SI 0x80000000L -#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK__SI 0x0000000cL -#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK__SI 0x00000003L -#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK__SI 0xffffffffL -#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK__SI 0xffffffffL -#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK__SI 0x000000ffL -#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK__SI 0x0000ff00L -#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK__SI 0x000000ffL -#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK__SI 0x0000ff00L -#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK__SI 0x000000ffL -#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK__SI 0x0000ff00L -#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK__SI 0x00000004L -#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK__SI 0x00000004L -#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK__SI 0x00000001L -#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK__SI 0x00000001L -#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK__SI 0x00000002L -#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK__SI 0x00000002L -#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK__SI 0x00000100L -#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK__SI 0x00000100L -#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK__SI 0x00000008L -#define DMCU_INTERRUPT_STATUS__PM_PWR_DOWN_INT_CLEAR_MASK__SI 0x00000020L -#define DMCU_INTERRUPT_STATUS__PM_PWR_DOWN_INT_OCCURRED_MASK__SI 0x00000020L -#define DMCU_INTERRUPT_STATUS__PM_PWR_UP_INT_CLEAR_MASK__SI 0x00000010L -#define DMCU_INTERRUPT_STATUS__PM_PWR_UP_INT_OCCURRED_MASK__SI 0x00000010L -#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK__SI 0x00000200L -#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK__SI 0x00000400L -#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK__SI 0x00000400L -#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK__SI 0x00000800L -#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK__SI 0x00000800L -#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK__SI 0x00000040L -#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK__SI 0x00000040L -#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK__SI 0x00000080L -#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK__SI 0x00000080L -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK__SI 0x00000004L -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK__SI 0x00000001L -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK__SI 0x00000002L -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK__SI 0x00000200L -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK__SI 0x00000400L -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK__SI 0x00000800L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK__SI 0x00000004L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK__SI 0x00000001L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK__SI 0x00000002L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK__SI 0x00000100L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK__SI 0x00000008L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__PM_PWR_DOWN_INT_TO_UC_EN_MASK__SI 0x00000020L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__PM_PWR_UP_INT_TO_UC_EN_MASK__SI 0x00000010L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK__SI 0x00000040L -#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK__SI 0x00000080L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000004L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000001L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000002L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000100L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000008L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__PM_PWR_DOWN_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000020L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__PM_PWR_UP_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000010L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000040L -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK__SI 0x00000080L -#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK__SI 0x00ff0000L -#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK__SI 0x000000ffL -#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK__SI 0x0000ff00L -#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK__SI 0x000003ffL -#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK__SI 0x000000ffL -#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK__SI 0x000003ffL -#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK__SI 0x000000ffL -#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK__SI 0x000000ffL -#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK__SI 0x0000ff00L -#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK__SI 0x00000002L -#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK__SI 0x00000001L -#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK__SI 0x00000008L -#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK__SI 0x00000004L -#define DMCU_STATUS__DMCU_RBBMIF_RD_WR_TIMEOUT_DIS_MASK__SI 0x80000000L -#define DMCU_STATUS__UC_IN_RESET_MASK__SI 0x00000001L -#define DMCU_STATUS__UC_IN_STOP_MODE_MASK__SI 0x00000004L -#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK__SI 0x00000002L -#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DMCU_UC_CCR__UC_CCR_C_MASK__SI 0x00000001L -#define DMCU_UC_CCR__UC_CCR_H_MASK__SI 0x00000020L -#define DMCU_UC_CCR__UC_CCR_I_MASK__SI 0x00000010L -#define DMCU_UC_CCR__UC_CCR_N_MASK__SI 0x00000008L -#define DMCU_UC_CCR__UC_CCR_S_MASK__SI 0x00000080L -#define DMCU_UC_CCR__UC_CCR_V_MASK__SI 0x00000002L -#define DMCU_UC_CCR__UC_CCR_X_MASK__SI 0x00000040L -#define DMCU_UC_CCR__UC_CCR_X_OVERRIDE_MASK__SI 0x00000100L -#define DMCU_UC_CCR__UC_CCR_Z_MASK__SI 0x00000004L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK__SI 0x00000008L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK__SI 0x00000001L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK__SI 0x00004000L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK__SI 0x00008000L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK__SI 0x00000200L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK__SI 0x00000004L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK__SI 0x00002000L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK__SI 0x00001000L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK__SI 0x00000800L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK__SI \ - 0x00000400L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK__SI 0x00000080L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK__SI 0x00000040L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK__SI 0x00000020L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK__SI 0x00000010L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK__SI 0x00000100L -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK__SI 0x00000002L -#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK__SI 0x0000ffffL -#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK__SI 0x00000003L -#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK__SI 0x00000700L -#define DMIF_DEBUG00__DMIF_DCP_debug00_cmd_grph_req_cnt_MASK__SI 0x0007f000L -#define DMIF_DEBUG00__DMIF_DCP_debug00_cmd_new_chunk_for_wr_MASK__SI 0x02000000L -#define DMIF_DEBUG00__DMIF_DCP_debug00_cmd_ovl_req_cnt_MASK__SI 0x01f80000L -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_cmd_state_MASK__SI 0x00000f00L -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_display1_update_MASK__SI 0x00000002L -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_display2_update_MASK__SI 0x00000004L -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_req_MASK__SI 0x00000008L -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_size_MASK__SI 0x00000030L -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_surface_MASK__SI 0x000000c0L -#define DMIF_DEBUG00__DMIF_DCP_debug00_dmif_dcp_req_fifo_empty_MASK__SI 0x00000001L -#define DMIF_DEBUG01__DMIF_DCP_debug01_cmd_q_mc_dmif_rdrtr_MASK__SI 0x00000001L -#define DMIF_DEBUG01__DMIF_DCP_debug01_dcp_dmif_urgent_MASK__SI 0x00008000L -#define DMIF_DEBUG01__DMIF_DCP_debug01_dcp_dmif_urglevel_MASK__SI 0x007f0000L -#define DMIF_DEBUG01__DMIF_DCP_debug01_dmif_mc_rdreq_MASK__SI 0x00000002L -#define DMIF_DEBUG01__DMIF_DCP_debug01_dmif_mc_rdtag_MASK__SI 0x00007ffcL -#define DMIF_DEBUG02__DMIF_DCP_debug02_chunk_readout_MASK__SI 0x00000040L -#define DMIF_DEBUG02__DMIF_DCP_debug02_grph_chunk_reading_MASK__SI 0x00000010L -#define DMIF_DEBUG02__DMIF_DCP_debug02_grph_new_chunk_for_wr_MASK__SI 0x00000001L -#define DMIF_DEBUG02__DMIF_DCP_debug02_grph_new_chunk_for_wr_taken_MASK__SI 0x00000004L -#define DMIF_DEBUG02__DMIF_DCP_debug02_ovl_chunk_reading_MASK__SI 0x00000020L -#define DMIF_DEBUG02__DMIF_DCP_debug02_ovl_new_chunk_for_wr_MASK__SI 0x00000002L -#define DMIF_DEBUG02__DMIF_DCP_debug02_ovl_new_chunk_for_wr_taken_MASK__SI 0x00000008L -#define DMIF_DEBUG03__DMIF_DCP_debug03_dcp_dmif_req_MASK__SI 0x00000001L -#define DMIF_DEBUG03__DMIF_DCP_debug03_dcp_dmif_size_MASK__SI 0x00000006L -#define DMIF_DEBUG03__DMIF_DCP_debug03_dcp_dmif_surface_MASK__SI 0x00000018L -#define DMIF_DEBUG03__DMIF_DCP_debug03_q_mc_dmif_rdtag_MASK__SI 0x0007ffc0L -#define DMIF_DEBUG03__DMIF_DCP_debug03_q_mc_dmif_rdtid_MASK__SI 0x00380000L -#define DMIF_DEBUG03__DMIF_DCP_debug03_q_mc_dmif_xfc_MASK__SI 0x00000020L -#define DMIF_DEBUG03__DMIF_DCP_debug03_wr_addr_MASK__SI 0x3fc00000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_dcp_dmif_grph_rtr_MASK__SI 0x01000000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_chunk_sending_MASK__SI 0x00400000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_dcp_data_buff_sel_MASK__SI 0x000c0000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_dcp_data_sel_MASK__SI 0x00100000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_last_pix_in_ow_MASK__SI 0x00020000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_pix_en_MASK__SI 0x00200000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_addr_MASK__SI 0x0000ff00L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_data_valid_MASK__SI 0x00010000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_en_MASK__SI 0x00000001L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_req_cnt_MASK__SI 0x000000feL -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rts_MASK__SI 0x00800000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_send_pix_cnt_MASK__SI 0x78000000L -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_send_pix_depth_MASK__SI 0x06000000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_dcp_dmif_ovl_rtr_MASK__SI 0x00800000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_chunk_sending_MASK__SI 0x00200000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_dcp_data_buff_sel_MASK__SI 0x00060000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_dcp_data_sel_MASK__SI 0x00080000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_last_pix_in_ow_MASK__SI 0x00010000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_pix_en_MASK__SI 0x00100000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_addr_MASK__SI 0x00007f80L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_data_valid_MASK__SI 0x00008000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_en_MASK__SI 0x00000001L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_req_cnt_MASK__SI 0x0000007eL -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rts_MASK__SI 0x00400000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_send_pix_cnt_MASK__SI 0x1c000000L -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_send_pix_depth_MASK__SI 0x03000000L -#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK__SI 0xffffffffL -#define DMIF_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK__SI 0x00000007L -#define DMIF_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK__SI 0x00000018L -#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK__SI 0x00003f00L -#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK__SI 0x00010000L -#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK__SI 0x00020000L -#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK__SI 0x0000003fL -#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DOUT_DEBUG__DOUT_DEBUG_MASK__SI 0xffffffffL -#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK__SI 0x00200000L -#define DOUT_POWER_MANAGEMENT_CNTL__PM_CURRENT_STATE_MASK__SI 0xf0000000L -#define DOUT_POWER_MANAGEMENT_CNTL__PM_DP_SW_FAST_TRAINING_ONLY_MASK__SI 0x00400000L -#define DOUT_POWER_MANAGEMENT_CNTL__PM_NO_DP_SUPPORT_DEBUG_MASK__SI 0x00100000L -#define DOUT_POWER_MANAGEMENT_CNTL__PM_PWRDN_PPLL_VREG_MASK__SI 0x01000000L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_BUSY_OFF_MASK__SI 0x00000001L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_DMCU_OFF_MASK__SI 0x00000020L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_PPLL_OFF_MASK__SI 0x00000100L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_PWRSEQ_OFF_MASK__SI 0x00000010L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_APLL_ON_MASK__SI 0x00001000L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_DMCU_ON_MASK__SI 0x00020000L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_MEM_INIT_DONE_MASK__SI 0x00010000L -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_PPLL_ON_MASK__SI 0x00000200L -#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK__SI 0xffffffffL -#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK__SI 0xffffffffL -#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK__SI 0xffffffffL -#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK__SI 0xffffffffL -#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK__SI 0xffffffffL -#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK__SI 0xffffffffL -#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK__SI 0xffffffffL -#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK__SI 0xffffffffL -#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK__SI 0xffffffffL -#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK__SI 0xffffffffL -#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK__SI 0xffffffffL -#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK__SI 0xffffffffL -#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK__SI 0xffffffffL -#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK__SI 0xffffffffL -#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK__SI 0xffffffffL -#define DP_CONFIG__DP_UDI_LANES_MASK__SI 0x00000003L -#define DP_CP_DEBUG1__DP_CP_DEBUG1_MASK__SI 0xffffffffL -#define DP_CP_DEBUG2__DP_CP_DEBUG2_MASK__SI 0xffffffffL -#define DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN_MASK__SI 0x0000ffffL -#define DP_DEBUG_A__DP_DEBUG_A_MASK__SI 0xffffffffL -#define DP_DEBUG_B__DP_DEBUG_B_MASK__SI 0xffffffffL -#define DP_DEBUG_C__DP_DEBUG_C_MASK__SI 0xffffffffL -#define DP_DEBUG_D__DP_DEBUG_D_MASK__SI 0xffffffffL -#define DP_DEBUG_E__DP_DEBUG_E_MASK__SI 0xffffffffL -#define DP_DEBUG_F__DP_DEBUG_F_MASK__SI 0xffffffffL -#define DP_DEBUG_G__DP_DEBUG_G_MASK__SI 0xffffffffL -#define DP_DEBUG_H__DP_DEBUG_H_MASK__SI 0xffffffffL -#define DP_DEBUG_ID__DP_DEBUG_ID_MASK__SI 0xffffffffL -#define DP_DEBUG_Q__DP_DEBUG_Q_MASK__SI 0xffffffffL -#define DP_DEBUG_R__DP_DEBUG_R_MASK__SI 0xffffffffL -#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK__SI 0x00010000L -#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK__SI 0x00000100L -#define DP_DPHY_8B10B_CNTL__DPHY_8b10b_CUR_DISP_MASK__SI 0x01000000L -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK__SI 0x00000001L -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK__SI 0x00000002L -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK__SI 0x00000004L -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK__SI 0x00000008L -#define DP_DPHY_CNTL__DPHY_BYPASS_MASK__SI 0x00010000L -#define DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK__SI 0x00000100L -#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK__SI 0x01000000L -#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK__SI 0x00000001L -#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK__SI 0x00ff0000L -#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK__SI 0x00000030L -#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK__SI 0x00000010L -#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK__SI 0x00000001L -#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK__SI 0x000000ffL -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK__SI 0x00000020L -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK__SI 0x00000040L -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK__SI 0x00000010L -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK__SI 0x000fff00L -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK__SI 0xfff00000L -#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK__SI 0x00000001L -#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK__SI 0x00000002L -#define DP_DPHY_INTERNAL_CTRL__DPHY_LANE_REVERSE_EN_MASK__SI 0x00000010L -#define DP_DPHY_INTERNAL_CTRL__DPHY_SCRAMBLER_RESET_CTRL_MASK__SI 0x00000001L -#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK__SI 0x00000001L -#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK__SI 0x7fffff00L -#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK__SI 0x00000010L -#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK__SI 0x00000010L -#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK__SI 0x0003ff00L -#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK__SI 0x00000001L -#define DP_DPHY_SYM__DPHY_SYM1_MASK__SI 0x000003ffL -#define DP_DPHY_SYM__DPHY_SYM2_MASK__SI 0x000ffc00L -#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK__SI 0x00000001L -#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK__SI 0xffffffffL -#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK__SI 0xffffffffL -#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK__SI 0xffffffffL -#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK__SI 0xffffffffL -#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK__SI 0xffffffffL -#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK__SI 0xffffffffL -#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK__SI 0xffffffffL -#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK__SI 0xffffffffL -#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK__SI 0xffffffffL -#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK__SI 0xffffffffL -#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK__SI 0xffffffffL -#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK__SI 0xffffffffL -#define DP_IDLE_PATTERN_CNTL__DP_IDLE_BS_INTERVAL_MASK__SI 0x0003ffffL -#define DP_IDLE_PATTERN_CNTL__DP_VBID_DISABLE_MASK__SI 0x01000000L -#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK__SI 0x00020000L -#define DP_LINK_CNTL__DP_LINK_STATUS_MASK__SI 0x00000100L -#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK__SI 0x00000010L -#define DP_LINK_CNTL__DP_POWER_MANAGEMENT_EN_MASK__SI 0x00010000L -#define DP_LINK_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK__SI 0x00001000L -#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK__SI 0x07000000L -#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK__SI 0x00000100L -#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK__SI 0x00000003L -#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK__SI 0x00010000L -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_HB1_MASK__SI 0x000000ffL -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_HB2_MASK__SI 0x0000ff00L -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_HB3_MASK__SI 0x00ff0000L -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_TYPE_LOCATION_MASK__SI 0x03000000L -#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK__SI 0x00ffffffL -#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK__SI 0x00ffffffL -#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK__SI 0x00ffffffL -#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK__SI 0x00ffffffL -#define DP_SEC_AUD_N__DP_SEC_N_BASE_MULTIPLE_MASK__SI 0x0f000000L -#define DP_SEC_AUD_N__DP_SEC_SS_EN_MASK__SI 0x10000000L -#define DP_SEC_CNTL__DP_SEC_ACP_ENABLE_MASK__SI 0x00010000L -#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK__SI 0x00001000L -#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK__SI 0x00000010L -#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK__SI 0x00000100L -#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK__SI 0x01000000L -#define DP_SEC_CNTL__DP_SEC_GSP_ENABLE_MASK__SI 0x00100000L -#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK__SI 0x10000000L -#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK__SI 0x00000001L -#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK__SI 0x00000fffL -#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK__SI 0xffff0000L -#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK__SI 0xffff0000L -#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK__SI 0x0000ffffL -#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK__SI 0x00003fffL -#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK__SI 0xffff0000L -#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK__SI 0x10000000L -#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK__SI 0x20000000L -#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK__SI 0x01000000L -#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK__SI 0x00100000L -#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK__SI 0x0000000fL -#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK__SI 0x00000010L -#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK__SI 0x00003f00L -#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK__SI 0x00000003L -#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK__SI 0x00000001L -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK__SI 0x00000040L -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK__SI 0x00000010L -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK__SI 0x00000020L -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK__SI 0x00000080L -#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK__SI 0x00000002L -#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK__SI 0x00000001L -#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK__SI 0x00000004L -#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK__SI 0x00000fffL -#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK__SI 0x00010000L -#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK__SI 0x01000000L -#define DP_VID_M__DP_VID_M_MASK__SI 0x00ffffffL -#define DP_VID_N__DP_VID_N_MASK__SI 0x00ffffffL -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK__SI 0x00100000L -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK__SI 0x00000300L -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK__SI 0x00000001L -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK__SI 0x00010000L -#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK__SI 0x00000100L -#define DP_VID_TIMING__DP_VID_N_DIV_MASK__SI 0xff000000L -#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK__SI 0x00000001L -#define DRMDMA0_CONFIG__DRMDMA_RDREQ_URG_MASK__SI 0x00000f00L -#define DRMDMA0_CONFIG__DRMDMA_REQ_TRAN_MASK__SI 0x00010000L -#define DRMDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK__SI 0x00000ff0L -#define DRMDMA1_CLK_CTRL__ON_DELAY_MASK__SI 0x0000000fL -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK__SI 0x80000000L -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK__SI 0x40000000L -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK__SI 0x20000000L -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK__SI 0x10000000L -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK__SI 0x08000000L -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK__SI 0x04000000L -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK__SI 0x02000000L -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK__SI 0x01000000L -#define DRMDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK__SI 0x10000000L -#define DRMDMA1_CNTL__DATA_SWAP_ENABLE_MASK__SI 0x00000008L -#define DRMDMA1_CNTL__DRM_CREDIT_MASK__SI 0x00001f00L -#define DRMDMA1_CNTL__FENCE_SWAP_ENABLE_MASK__SI 0x00000010L -#define DRMDMA1_CNTL__IB_PREEMPT_ENABLE_MASK__SI 0x20000000L -#define DRMDMA1_CNTL__MC_RDREQ_CREDIT_MASK__SI 0x0f800000L -#define DRMDMA1_CNTL__MC_WRREQ_CREDIT_MASK__SI 0x0003e000L -#define DRMDMA1_CNTL__MC_WR_CLEAN_CNT_MASK__SI 0x007c0000L -#define DRMDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK__SI 0x00000002L -#define DRMDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK__SI 0x00000004L -#define DRMDMA1_CNTL__SLOW_TILED_WRITE_MODE_MASK__SI 0x80000000L -#define DRMDMA1_CNTL__TRAP_ENABLE_MASK__SI 0x00000001L -#define DRMDMA1_CONFIG__DRMDMA_RDREQ_URG_MASK__SI 0x00000f00L -#define DRMDMA1_CONFIG__DRMDMA_REQ_TRAN_MASK__SI 0x00010000L -#define DRMDMA1_CONTEXT_CNTL__RESTORE_COUNT_MASK__SI 0x0000ffffL -#define DRMDMA1_CONTEXT_CNTL__RESUME_CTX_MASK__SI 0x00010000L -#define DRMDMA1_CONTEXT_CNTL__SESSION_SEL_MASK__SI 0x0f000000L -#define DRMDMA1_CRC_VALUE__CRC_VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM1_CTRL__DRM1_CREDIT_MASK__SI 0x0000001fL -#define DRMDMA1_DRM_COUNTERDATA0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_COUNTERDATA1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_COUNTERDATA2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_COUNTERDATA3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_COUNTERKEY0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_COUNTERKEY1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_COUNTERKEY2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_COUNTERKEY3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_IVLOAD0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_IVLOAD1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_IVLOAD2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_IVLOAD3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_IVLOAD4__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_OFFSET__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_UNROLLKEY__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_WRAPPEDKEY0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_WRAPPEDKEY1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_WRAPPEDKEY2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_DRM_WRAPPEDKEY3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA1_FAULT_ADDR_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA1_FAULT_ADDR_LO__ADDR_MASK__SI 0xfffff000L -#define DRMDMA1_FIFO_CNTL__CG_STATUS_OUTPUT_MASK__SI 0x00800000L -#define DRMDMA1_FIFO_CNTL__COPY_OVERLAP_ENABLE_MASK__SI 0x00010000L -#define DRMDMA1_FIFO_CNTL__DATA_FIFO_SIZE_MASK__SI 0x00000030L -#define DRMDMA1_FIFO_CNTL__DRM_FIFO_SIZE_MASK__SI 0x00000c00L -#define DRMDMA1_FIFO_CNTL__GPU_ID_MASK__SI 0x0000f000L -#define DRMDMA1_FIFO_CNTL__IB_FIFO_SIZE_MASK__SI 0x0000000cL -#define DRMDMA1_FIFO_CNTL__MC_VMID_FORCE_MASK__SI 0x00400000L -#define DRMDMA1_FIFO_CNTL__MC_VMID_MASK__SI 0x001c0000L -#define DRMDMA1_FIFO_CNTL__MC_WR_ADDR_FIFO_SIZE_MASK__SI 0x000000c0L -#define DRMDMA1_FIFO_CNTL__MC_WR_DATA_FIFO_SIZE_MASK__SI 0x00000300L -#define DRMDMA1_FIFO_CNTL__RB_FIFO_SIZE_MASK__SI 0x00000003L -#define DRMDMA1_FIFO_CNTL__WRITE_OVERLAP_ENABLE_MASK__SI 0x00020000L -#define DRMDMA1_IB_BASE_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA1_IB_BASE_LO__ADDR_MASK__SI 0xffffffe0L -#define DRMDMA1_IB_CNTL__IB_ENABLE_MASK__SI 0x00000001L -#define DRMDMA1_IB_CNTL__IB_SWAP_ENABLE_MASK__SI 0x00000010L -#define DRMDMA1_IB_OFFSET__OFFSET_MASK__SI 0x000fffffL -#define DRMDMA1_IB_RPTR__OFFSET_MASK__SI 0x003ffffcL -#define DRMDMA1_IB_SIZE__SIZE_MASK__SI 0x000fffffL -#define DRMDMA1_PERF_CNTL__CLEAR0_MASK__SI 0x00000002L -#define DRMDMA1_PERF_CNTL__CLEAR1_MASK__SI 0x00000200L -#define DRMDMA1_PERF_CNTL__ENABLE0_MASK__SI 0x00000001L -#define DRMDMA1_PERF_CNTL__ENABLE1_MASK__SI 0x00000100L -#define DRMDMA1_PERF_CNTL__SELECT0_MASK__SI 0x000000fcL -#define DRMDMA1_PERF_CNTL__SELECT1_MASK__SI 0x0000fc00L -#define DRMDMA1_PERF_COUNT0__PERF_COUNT_MASK__SI 0xffffffffL -#define DRMDMA1_PERF_COUNT1__PERF_COUNT_MASK__SI 0xffffffffL -#define DRMDMA1_PREEMPT__PREEMPT_MASK__SI 0x00000001L -#define DRMDMA1_PRIV_MODE__MC_PRIV_MODE_MASK__SI 0x00000001L -#define DRMDMA1_PRIV_MODE__MEM_POWER_OVERRIDE_MASK__SI 0x00000100L -#define DRMDMA1_RB_BASE__ADDR_MASK__SI 0xffffffffL -#define DRMDMA1_RB_CNTL__RB_ENABLE_MASK__SI 0x00000001L -#define DRMDMA1_RB_CNTL__RB_SIZE_MASK__SI 0x0000003eL -#define DRMDMA1_RB_CNTL__RB_SWAP_ENABLE_MASK__SI 0x00000200L -#define DRMDMA1_RB_CNTL__RB_TRAN_MASK__SI 0x00000100L -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__SI 0x00001000L -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__SI 0x00002000L -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__SI 0x001f0000L -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_TRAN_MASK__SI 0x00004000L -#define DRMDMA1_RB_RPTR_ADDR_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA1_RB_RPTR_ADDR_LO__ADDR_MASK__SI 0xfffffffcL -#define DRMDMA1_RB_RPTR__OFFSET_MASK__SI 0x0003fffcL -#define DRMDMA1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__SI 0xfffffffcL -#define DRMDMA1_RB_WPTR_POLL_CNTL__ENABLE_MASK__SI 0x00000001L -#define DRMDMA1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__SI 0x0000fff0L -#define DRMDMA1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__SI 0xffff0000L -#define DRMDMA1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__SI 0x00000002L -#define DRMDMA1_RB_WPTR_POLL_CNTL__TRAN_MASK__SI 0x00000004L -#define DRMDMA1_RB_WPTR__OFFSET_MASK__SI 0x0003fffcL -#define DRMDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK__SI 0x0000ffffL -#define DRMDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK__SI 0xffffffffL -#define DRMDMA1_STATUS_REG__DRM_IDLE_MASK__SI 0x00800000L -#define DRMDMA1_STATUS_REG__DRM_MASK_FULL_MASK__SI 0x01000000L -#define DRMDMA1_STATUS_REG__DRM_REQ_STALL_MASK__SI 0x02000000L -#define DRMDMA1_STATUS_REG__EX_IDLE_MASK__SI 0x00000400L -#define DRMDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK__SI 0x00000800L -#define DRMDMA1_STATUS_REG__IB_CMD_FULL_MASK__SI 0x00000080L -#define DRMDMA1_STATUS_REG__IB_CMD_IDLE_MASK__SI 0x00000040L -#define DRMDMA1_STATUS_REG__IDLE_MASK__SI 0x00000001L -#define DRMDMA1_STATUS_REG__INT_IDLE_MASK__SI 0x40000000L -#define DRMDMA1_STATUS_REG__INT_REQ_STALL_MASK__SI 0x80000000L -#define DRMDMA1_STATUS_REG__MC_RD_IDLE_MASK__SI 0x00080000L -#define DRMDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK__SI 0x00400000L -#define DRMDMA1_STATUS_REG__MC_RD_RET_STALL_MASK__SI 0x00200000L -#define DRMDMA1_STATUS_REG__MC_RD_STALL_MASK__SI 0x00100000L -#define DRMDMA1_STATUS_REG__MC_WR_AFIFO_FULL_MASK__SI 0x00004000L -#define DRMDMA1_STATUS_REG__MC_WR_CLEAN_PENDING_MASK__SI 0x00020000L -#define DRMDMA1_STATUS_REG__MC_WR_CLEAN_STALL_MASK__SI 0x00040000L -#define DRMDMA1_STATUS_REG__MC_WR_DFIFO_FULL_MASK__SI 0x00008000L -#define DRMDMA1_STATUS_REG__MC_WR_IDLE_MASK__SI 0x00002000L -#define DRMDMA1_STATUS_REG__MC_WR_STALL_MASK__SI 0x00010000L -#define DRMDMA1_STATUS_REG__RB_CMD_FULL_MASK__SI 0x00000020L -#define DRMDMA1_STATUS_REG__RB_CMD_IDLE_MASK__SI 0x00000010L -#define DRMDMA1_STATUS_REG__RB_EMPTY_MASK__SI 0x00000004L -#define DRMDMA1_STATUS_REG__RB_FULL_MASK__SI 0x00000008L -#define DRMDMA1_STATUS_REG__RD_DATA_FULL_MASK__SI 0x00000200L -#define DRMDMA1_STATUS_REG__RD_DATA_IDLE_MASK__SI 0x00000100L -#define DRMDMA1_STATUS_REG__REG_IDLE_MASK__SI 0x00000002L -#define DRMDMA1_STATUS_REG__SEM_IDLE_MASK__SI 0x04000000L -#define DRMDMA1_STATUS_REG__SEM_REQ_STALL_MASK__SI 0x08000000L -#define DRMDMA1_STATUS_REG__SEM_RESP_STATE_MASK__SI 0x30000000L -#define DRMDMA1_STATUS_REG__TILE_IDLE_MASK__SI 0x00001000L -#define DRMDMA1_TILING_CONFIG__BANK_INTERLEAVE_SIZE_MASK__SI 0x00000700L -#define DRMDMA1_TILING_CONFIG__MULTI_GPU_TILE_SIZE_MASK__SI 0x03000000L -#define DRMDMA1_TILING_CONFIG__NUM_GPUS_MASK__SI 0x00700000L -#define DRMDMA1_TILING_CONFIG__NUM_LOWER_PIPES_MASK__SI 0x40000000L -#define DRMDMA1_TILING_CONFIG__NUM_PIPES_MASK__SI 0x00000007L -#define DRMDMA1_TILING_CONFIG__NUM_SHADER_ENGINES_MASK__SI 0x00003000L -#define DRMDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK__SI 0x00000070L -#define DRMDMA1_TILING_CONFIG__ROW_SIZE_MASK__SI 0x30000000L -#define DRMDMA1_TILING_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK__SI 0x00070000L -#define DRMDMA_CLK_CTRL__OFF_HYSTERESIS_MASK__SI 0x00000ff0L -#define DRMDMA_CLK_CTRL__ON_DELAY_MASK__SI 0x0000000fL -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK__SI 0x80000000L -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK__SI 0x40000000L -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK__SI 0x20000000L -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK__SI 0x10000000L -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK__SI 0x08000000L -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK__SI 0x04000000L -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK__SI 0x02000000L -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK__SI 0x01000000L -#define DRMDMA_CNTL__CTXEMPTY_INT_ENABLE_MASK__SI 0x10000000L -#define DRMDMA_CNTL__DATA_SWAP_ENABLE_MASK__SI 0x00000008L -#define DRMDMA_CNTL__DRM_CREDIT_MASK__SI 0x00001f00L -#define DRMDMA_CNTL__FENCE_SWAP_ENABLE_MASK__SI 0x00000010L -#define DRMDMA_CNTL__IB_PREEMPT_ENABLE_MASK__SI 0x20000000L -#define DRMDMA_CNTL__MC_RDREQ_CREDIT_MASK__SI 0x0f800000L -#define DRMDMA_CNTL__MC_WRREQ_CREDIT_MASK__SI 0x0003e000L -#define DRMDMA_CNTL__MC_WR_CLEAN_CNT_MASK__SI 0x007c0000L -#define DRMDMA_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK__SI 0x00000002L -#define DRMDMA_CNTL__SEM_WAIT_INT_ENABLE_MASK__SI 0x00000004L -#define DRMDMA_CNTL__SLOW_TILED_WRITE_MODE_MASK__SI 0x80000000L -#define DRMDMA_CNTL__TRAP_ENABLE_MASK__SI 0x00000001L -#define DRMDMA_CONTEXT_CNTL__RESTORE_COUNT_MASK__SI 0x0000ffffL -#define DRMDMA_CONTEXT_CNTL__RESUME_CTX_MASK__SI 0x00010000L -#define DRMDMA_CONTEXT_CNTL__SESSION_SEL_MASK__SI 0x0f000000L -#define DRMDMA_CRC_VALUE__CRC_VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM1_CTRL__DRM1_CREDIT_MASK__SI 0x0000001fL -#define DRMDMA_DRM_COUNTERDATA0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_COUNTERDATA1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_COUNTERDATA2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_COUNTERDATA3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_COUNTERKEY0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_COUNTERKEY1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_COUNTERKEY2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_COUNTERKEY3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_IVLOAD0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_IVLOAD1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_IVLOAD2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_IVLOAD3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_IVLOAD4__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_OFFSET__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_UNROLLKEY__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_WRAPPEDKEY0__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_WRAPPEDKEY1__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_WRAPPEDKEY2__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_DRM_WRAPPEDKEY3__VALUE_MASK__SI 0xffffffffL -#define DRMDMA_FAULT_ADDR_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA_FAULT_ADDR_LO__ADDR_MASK__SI 0xfffff000L -#define DRMDMA_FIFO_CNTL__CG_STATUS_OUTPUT_MASK__SI 0x00800000L -#define DRMDMA_FIFO_CNTL__COPY_OVERLAP_ENABLE_MASK__SI 0x00010000L -#define DRMDMA_FIFO_CNTL__DATA_FIFO_SIZE_MASK__SI 0x00000030L -#define DRMDMA_FIFO_CNTL__DRM_FIFO_SIZE_MASK__SI 0x00000c00L -#define DRMDMA_FIFO_CNTL__GPU_ID_MASK__SI 0x0000f000L -#define DRMDMA_FIFO_CNTL__IB_FIFO_SIZE_MASK__SI 0x0000000cL -#define DRMDMA_FIFO_CNTL__MC_WR_ADDR_FIFO_SIZE_MASK__SI 0x000000c0L -#define DRMDMA_FIFO_CNTL__MC_WR_DATA_FIFO_SIZE_MASK__SI 0x00000300L -#define DRMDMA_FIFO_CNTL__RB_FIFO_SIZE_MASK__SI 0x00000003L -#define DRMDMA_FIFO_CNTL__WRITE_OVERLAP_ENABLE_MASK__SI 0x00020000L -#define DRMDMA_IB_BASE_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA_IB_BASE_LO__ADDR_MASK__SI 0xffffffe0L -#define DRMDMA_IB_CNTL__CMD_VMID_FORCE_MASK__SI 0x80000000L -#define DRMDMA_IB_CNTL__CMD_VMID_MASK__SI 0x07000000L -#define DRMDMA_IB_CNTL__IB_ENABLE_MASK__SI 0x00000001L -#define DRMDMA_IB_CNTL__IB_SWAP_ENABLE_MASK__SI 0x00000010L -#define DRMDMA_IB_OFFSET__OFFSET_MASK__SI 0x000fffffL -#define DRMDMA_IB_RPTR__OFFSET_MASK__SI 0x003ffffcL -#define DRMDMA_IB_SIZE__SIZE_MASK__SI 0x000fffffL -#define DRMDMA_PERF_CNTL__CLEAR0_MASK__SI 0x00000002L -#define DRMDMA_PERF_CNTL__CLEAR1_MASK__SI 0x00000200L -#define DRMDMA_PERF_CNTL__ENABLE0_MASK__SI 0x00000001L -#define DRMDMA_PERF_CNTL__ENABLE1_MASK__SI 0x00000100L -#define DRMDMA_PERF_CNTL__SELECT0_MASK__SI 0x000000fcL -#define DRMDMA_PERF_CNTL__SELECT1_MASK__SI 0x0000fc00L -#define DRMDMA_PERF_COUNT0__PERF_COUNT_MASK__SI 0xffffffffL -#define DRMDMA_PERF_COUNT1__PERF_COUNT_MASK__SI 0xffffffffL -#define DRMDMA_PREEMPT__PREEMPT_MASK__SI 0x00000001L -#define DRMDMA_PRIV_MODE__MC_PRIV_MODE_MASK__SI 0x00000001L -#define DRMDMA_PRIV_MODE__MEM_POWER_OVERRIDE_MASK__SI 0x00000100L -#define DRMDMA_RB_BASE__ADDR_MASK__SI 0xffffffffL -#define DRMDMA_RB_CNTL__RB_ENABLE_MASK__SI 0x00000001L -#define DRMDMA_RB_CNTL__RB_SIZE_MASK__SI 0x0000003eL -#define DRMDMA_RB_CNTL__RB_SWAP_ENABLE_MASK__SI 0x00000200L -#define DRMDMA_RB_CNTL__RB_TRAN_MASK__SI 0x00000100L -#define DRMDMA_RB_CNTL__RB_VMID_MASK__SI 0x07000000L -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__SI 0x00001000L -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__SI 0x00002000L -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__SI 0x001f0000L -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_TRAN_MASK__SI 0x00004000L -#define DRMDMA_RB_RPTR_ADDR_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA_RB_RPTR_ADDR_LO__ADDR_MASK__SI 0xfffffffcL -#define DRMDMA_RB_RPTR__OFFSET_MASK__SI 0x0003fffcL -#define DRMDMA_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__SI 0x000000ffL -#define DRMDMA_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__SI 0xfffffffcL -#define DRMDMA_RB_WPTR_POLL_CNTL__ENABLE_MASK__SI 0x00000001L -#define DRMDMA_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__SI 0x0000fff0L -#define DRMDMA_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__SI 0xffff0000L -#define DRMDMA_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__SI 0x00000002L -#define DRMDMA_RB_WPTR_POLL_CNTL__TRAN_MASK__SI 0x00000004L -#define DRMDMA_RB_WPTR__OFFSET_MASK__SI 0x0003fffcL -#define DRMDMA_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK__SI 0x0000ffffL -#define DRMDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK__SI 0xffffffffL -#define DRMDMA_STATUS_REG__DRM_IDLE_MASK__SI 0x00800000L -#define DRMDMA_STATUS_REG__DRM_MASK_FULL_MASK__SI 0x01000000L -#define DRMDMA_STATUS_REG__DRM_REQ_STALL_MASK__SI 0x02000000L -#define DRMDMA_STATUS_REG__EX_IDLE_MASK__SI 0x00000400L -#define DRMDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK__SI 0x00000800L -#define DRMDMA_STATUS_REG__IB_CMD_FULL_MASK__SI 0x00000080L -#define DRMDMA_STATUS_REG__IB_CMD_IDLE_MASK__SI 0x00000040L -#define DRMDMA_STATUS_REG__IDLE_MASK__SI 0x00000001L -#define DRMDMA_STATUS_REG__INT_IDLE_MASK__SI 0x40000000L -#define DRMDMA_STATUS_REG__INT_REQ_STALL_MASK__SI 0x80000000L -#define DRMDMA_STATUS_REG__MC_RD_IDLE_MASK__SI 0x00080000L -#define DRMDMA_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK__SI 0x00400000L -#define DRMDMA_STATUS_REG__MC_RD_RET_STALL_MASK__SI 0x00200000L -#define DRMDMA_STATUS_REG__MC_RD_STALL_MASK__SI 0x00100000L -#define DRMDMA_STATUS_REG__MC_WR_AFIFO_FULL_MASK__SI 0x00004000L -#define DRMDMA_STATUS_REG__MC_WR_CLEAN_PENDING_MASK__SI 0x00020000L -#define DRMDMA_STATUS_REG__MC_WR_CLEAN_STALL_MASK__SI 0x00040000L -#define DRMDMA_STATUS_REG__MC_WR_DFIFO_FULL_MASK__SI 0x00008000L -#define DRMDMA_STATUS_REG__MC_WR_IDLE_MASK__SI 0x00002000L -#define DRMDMA_STATUS_REG__MC_WR_STALL_MASK__SI 0x00010000L -#define DRMDMA_STATUS_REG__RB_CMD_FULL_MASK__SI 0x00000020L -#define DRMDMA_STATUS_REG__RB_CMD_IDLE_MASK__SI 0x00000010L -#define DRMDMA_STATUS_REG__RB_EMPTY_MASK__SI 0x00000004L -#define DRMDMA_STATUS_REG__RB_FULL_MASK__SI 0x00000008L -#define DRMDMA_STATUS_REG__RD_DATA_FULL_MASK__SI 0x00000200L -#define DRMDMA_STATUS_REG__RD_DATA_IDLE_MASK__SI 0x00000100L -#define DRMDMA_STATUS_REG__REG_IDLE_MASK__SI 0x00000002L -#define DRMDMA_STATUS_REG__SEM_IDLE_MASK__SI 0x04000000L -#define DRMDMA_STATUS_REG__SEM_REQ_STALL_MASK__SI 0x08000000L -#define DRMDMA_STATUS_REG__SEM_RESP_STATE_MASK__SI 0x30000000L -#define DRMDMA_STATUS_REG__TILE_IDLE_MASK__SI 0x00001000L -#define DRMDMA_TILING_CONFIG__BANK_INTERLEAVE_SIZE_MASK__SI 0x00000700L -#define DRMDMA_TILING_CONFIG__MULTI_GPU_TILE_SIZE_MASK__SI 0x03000000L -#define DRMDMA_TILING_CONFIG__NUM_GPUS_MASK__SI 0x00700000L -#define DRMDMA_TILING_CONFIG__NUM_LOWER_PIPES_MASK__SI 0x40000000L -#define DRMDMA_TILING_CONFIG__NUM_PIPES_MASK__SI 0x00000007L -#define DRMDMA_TILING_CONFIG__NUM_SHADER_ENGINES_MASK__SI 0x00003000L -#define DRMDMA_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK__SI 0x00000070L -#define DRMDMA_TILING_CONFIG__ROW_SIZE_MASK__SI 0x30000000L -#define DRMDMA_TILING_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK__SI 0x00070000L -#define DRM_ARB_PRIORITY__SLOT0_MASK 0x0000000fL -#define DRM_ARB_PRIORITY__SLOT1_MASK 0x000000f0L -#define DRM_ARB_PRIORITY__SLOT2_MASK 0x00000f00L -#define DRM_ARB_PRIORITY__SLOT3_MASK 0x0000f000L -#define DRM_ARB_PRIORITY__SLOT4_MASK 0x000f0000L -#define DRM_ARB_PRIORITY__SLOT5_MASK 0x00f00000L -#define DRM_ARB_PRIORITY__SLOT6_MASK 0x0f000000L -#define DRM_ARB_PRIORITY__SLOT7_MASK 0xf0000000L -#define DRM_BYTESWAP__CLIENT0_BYTESWAP_MASK 0x00000100L -#define DRM_BYTESWAP__CLIENT1_BYTESWAP_MASK 0x00010000L -#define DRM_BYTESWAP__CLIENT2_BYTESWAP_MASK 0x00000001L -#define DRM_DEBUG_ID__DRM_DEBUG_ID_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX0__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX1__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX2__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX3__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX4__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX5__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX6__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG_INDEX7__DRM_DEBUG_INDEX_MASK__SI 0xffffffffL -#define DRM_DEBUG__DEBUG_BUS_SELECT_MASK 0x1f000000L -#define DRM_DEBUG__DEBUG_UNUSED_0_MASK 0x00ffffffL -#define DRM_DEBUG__DEBUG_UNUSED_1_MASK 0xe0000000L -#define DRM_HFS_CONT__RESERVED_MASK 0xffffffffL -#define DRM_HFS_HW_NONCE0__HW_NONCE_MASK 0xffffffffL -#define DRM_HFS_HW_NONCE1__HW_NONCE_MASK 0xffffffffL -#define DRM_HFS_HW_NONCE2__HW_NONCE_MASK 0xffffffffL -#define DRM_HFS_HW_NONCE3__HW_NONCE_MASK 0xffffffffL -#define DRM_HFS_HW_RESULT0__HW_RESULT_MASK 0xffffffffL -#define DRM_HFS_HW_RESULT1__HW_RESULT_MASK 0xffffffffL -#define DRM_HFS_HW_RESULT2__HW_RESULT_MASK 0xffffffffL -#define DRM_HFS_HW_RESULT3__HW_RESULT_MASK 0xffffffffL -#define DRM_HFS_SECRET_SEL__SEL0_MASK 0x000000ffL -#define DRM_HFS_SECRET_SEL__SEL1_MASK 0x0000ff00L -#define DRM_HFS_SECRET_SEL__SEL2_MASK 0x00ff0000L -#define DRM_HFS_SECRET_SEL__SEL3_MASK 0xff000000L -#define DRM_HFS_START__HFS_TYPE_MASK 0x0000000fL -#define DRM_HFS_SW_NONCE0__SW_NONCE_MASK 0xffffffffL -#define DRM_HFS_SW_NONCE1__SW_NONCE_MASK 0xffffffffL -#define DRM_HFS_SW_NONCE2__SW_NONCE_MASK 0xffffffffL -#define DRM_HFS_SW_NONCE3__SW_NONCE_MASK 0xffffffffL -#define DRM_HFS_SW_RESULT0__SW_RESULT_MASK 0xffffffffL -#define DRM_HFS_SW_RESULT1__SW_RESULT_MASK 0xffffffffL -#define DRM_HFS_SW_RESULT2__SW_RESULT_MASK 0xffffffffL -#define DRM_HFS_SW_RESULT3__SW_RESULT_MASK 0xffffffffL -#define DRM_ID_EFUSE__DEBUG_MODE_MASK 0x00000001L -#define DRM_ID_EFUSE__HFS_FAIL_MASK 0x00000002L -#define DRM_ID_EFUSE__HFS_ID_MASK 0x000000f8L -#define DRM_ID_EFUSE__HFS_WAY_MASK 0x00000004L -#define DRM_IH_CREDITS__IH_CREDITS_MASK 0x0000001fL -#define DRM_INT_ACK__DH1_DONE_MASK 0x00000001L -#define DRM_INT_ACK__DH2_DONE_MASK 0x00000002L -#define DRM_INT_ACK__HFS_DONE_MASK 0x00000004L -#define DRM_INT_ACK__INVALID_CLIENT0_MASK 0x00000200L -#define DRM_INT_ACK__INVALID_CLIENT1_MASK 0x00000400L -#define DRM_INT_ACK__INVALID_CLIENT2_MASK 0x00000100L -#define DRM_INT_ACK__SIG_DONE_MASK 0x00000008L -#define DRM_INT_ACK__SIG_VALID_MASK 0x00000010L -#define DRM_INT_ACK__TIMEOUT_CLIENT0_MASK 0x00000040L -#define DRM_INT_ACK__TIMEOUT_CLIENT1_MASK 0x00000080L -#define DRM_INT_ACK__TIMEOUT_CLIENT2_MASK 0x00000020L -#define DRM_INT_MASK__DH1_DONE_MASK 0x00000001L -#define DRM_INT_MASK__DH2_DONE_MASK 0x00000002L -#define DRM_INT_MASK__HFS_DONE_MASK 0x00000004L -#define DRM_INT_MASK__INVALID_CLIENT0_MASK 0x00000200L -#define DRM_INT_MASK__INVALID_CLIENT1_MASK 0x00000400L -#define DRM_INT_MASK__INVALID_CLIENT2_MASK 0x00000100L -#define DRM_INT_MASK__SIG_DONE_MASK 0x00000008L -#define DRM_INT_MASK__SIG_VALID_MASK 0x00000010L -#define DRM_INT_MASK__TIMEOUT_CLIENT0_MASK 0x00000040L -#define DRM_INT_MASK__TIMEOUT_CLIENT1_MASK 0x00000080L -#define DRM_INT_MASK__TIMEOUT_CLIENT2_MASK 0x00000020L -#define DRM_INT_STATUS__DH1_DONE_MASK 0x00000001L -#define DRM_INT_STATUS__DH2_DONE_MASK 0x00000002L -#define DRM_INT_STATUS__HFS_DONE_MASK 0x00000004L -#define DRM_INT_STATUS__INVALID_CLIENT0_MASK 0x00000200L -#define DRM_INT_STATUS__INVALID_CLIENT1_MASK 0x00000400L -#define DRM_INT_STATUS__INVALID_CLIENT2_MASK 0x00000100L -#define DRM_INT_STATUS__SIG_DONE_MASK 0x00000008L -#define DRM_INT_STATUS__SIG_VALID_MASK 0x00000010L -#define DRM_INT_STATUS__TIMEOUT_CLIENT0_MASK 0x00000040L -#define DRM_INT_STATUS__TIMEOUT_CLIENT1_MASK 0x00000080L -#define DRM_INT_STATUS__TIMEOUT_CLIENT2_MASK 0x00000020L -#define DRM_KEYGEN_CONT__RESERVED_MASK 0xffffffffL -#define DRM_KEYGEN_RADDR__RADDR_MASK 0x0000003fL -#define DRM_KEYGEN_RDATA__RDATA_MASK 0xffffffffL -#define DRM_KEYGEN_START__RESERVED_MASK 0xffffffffL -#define DRM_KEYGEN_WADDR__WADDR_MASK 0x0000003fL -#define DRM_KEYGEN_WDATA__WDATA_MASK 0xffffffffL -#define DRM_PERFCOUNTER1_HI__HI_MASK 0x0000ffffL -#define DRM_PERFCOUNTER1_LO__LO_MASK 0xffffffffL -#define DRM_PERFCOUNTER1_SELECT__PERFCOUNTER1_SELECT_MASK 0x0000003fL -#define DRM_PERFCOUNTER2_HI__HI_MASK 0x0000ffffL -#define DRM_PERFCOUNTER2_LO__LO_MASK 0xffffffffL -#define DRM_PERFCOUNTER2_SELECT__PERFCOUNTER2_SELECT_MASK 0x0000003fL -#define DRM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL -#define DRM_PROTO_ADDR__ADDR_MASK 0x00000fffL -#define DRM_PROTO_DATA__DATA_MASK 0xffffffffL -#define DRM_RESET__CLIENT0_RESET_MASK 0x00000100L -#define DRM_RESET__CLIENT1_RESET_MASK 0x00010000L -#define DRM_RESET__CLIENT2_RESET_MASK 0x00000001L -#define DRM_SIG_FINISH__RESERVED_MASK 0xffffffffL -#define DRM_SIG_INVALID__INVALID_MASK 0xffffffffL -#define DRM_SIG_RADDR__ADDR_MASK 0x0003ffffL -#define DRM_SIG_RDATA__DATA_MASK 0xffffffffL -#define DRM_SIG_RESULT0__RESULT_MASK 0xffffffffL -#define DRM_SIG_RESULT1__RESULT_MASK 0xffffffffL -#define DRM_SIG_RESULT2__RESULT_MASK 0xffffffffL -#define DRM_SIG_RESULT3__RESULT_MASK 0xffffffffL -#define DRM_SIG_START__NONCE_MASK 0xffffffffL -#define DRM_STATUS__AUTH_STATE_MASK 0x0e000000L -#define DRM_STATUS__CLIENT0_BUSY_MASK 0x00000010L -#define DRM_STATUS__CLIENT0_PARSE_BUSY_MASK 0x00000800L -#define DRM_STATUS__CLIENT1_BUSY_MASK 0x00000004L -#define DRM_STATUS__CLIENT1_PARSE_BUSY_MASK 0x00000200L -#define DRM_STATUS__CLIENT2_BUSY_MASK 0x00000008L -#define DRM_STATUS__CLIENT2_PARSE_BUSY_MASK 0x00000400L -#define DRM_STATUS__DH_ACTIVE_MASK 0x00100000L -#define DRM_STATUS__DH_BUSY1_MASK 0x00000100L -#define DRM_STATUS__DH_BUSY2_MASK 0x00000080L -#define DRM_STATUS__DH_DONE_MASK 0x00020000L -#define DRM_STATUS__DRM_BUSY_MASK 0x00000001L -#define DRM_STATUS__DRM_INIT_MASK 0x00040000L -#define DRM_STATUS__HFS_ACTIVE_MASK 0x00200000L -#define DRM_STATUS__HFS_BUSY_MASK 0x00000040L -#define DRM_STATUS__HFS_DONE_MASK 0x00010000L -#define DRM_STATUS__HFS_PASS_MASK 0x01000000L -#define DRM_STATUS__SIG_ACTIVE_MASK 0x00400000L -#define DRM_STATUS__SIG_BUSY_MASK 0x00000020L -#define DRM_STATUS__SIG_RD_BUSY_MASK 0x00001000L -#define DRM_STATUS__TRNG_BUSY_MASK 0x00000002L -#define DRM_TIMEOUT__CLIENT0_TIMEOUT_MASK 0x0000ff00L -#define DRM_TIMEOUT__CLIENT1_TIMEOUT_MASK 0x00ff0000L -#define DRM_TIMEOUT__CLIENT2_TIMEOUT_MASK 0x000000ffL -#define DRM_TRNG_CNTL__EN_LFSR_MASK 0x00000002L -#define DRM_TRNG_CNTL__EN_OSC_MASK 0x00000001L -#define DRM_TRNG_CNTL__EN_OUT_MASK 0x00000100L -#define DRM_TRNG_DATA__RNG_VAL_MASK 0xffffffffL -#define DTO_VCLK_DENOMIN__DTO_EN_MASK__SI 0x80000000L -#define DTO_VCLK_DENOMIN__DTO_VCLK_DENOMIN_MASK__SI 0x00000fffL -#define DTO_VCLK_INC_CORR__DTO_VCLK_INC_CORR_MASK__SI 0xffffffffL -#define DTO_VCLK_INC__DTO_VCLK_INC_MASK__SI 0xffffffffL -#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK__SI 0x00020000L -#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK__SI 0x00001f00L -#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK__SI 0x00010000L -#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK__SI 0x00000007L -#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK__SI 0x00040000L -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK__SI 0x00020000L -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK__SI 0x00001f00L -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK__SI 0x00010000L -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK__SI 0x00000007L -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK__SI 0x00040000L -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK__SI 0x00100000L -#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK__SI 0x03000000L -#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK__SI 0x30000000L -#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK__SI 0x00020000L -#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK__SI 0x00001f00L -#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK__SI 0x00010000L -#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK__SI 0x00000007L -#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK__SI 0x00040000L -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_CAPTURE_START_MASK__SI 0x00800000L -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_COLOR_IN_MASK__SI 0x00000ffcL -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_COLOR_OUT_MASK__SI 0xff000000L -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_HBLANKB_MASK__SI 0x00000002L -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_PHASE_MASK__SI 0x00000001L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_DISP_IO_DVOCLK_MASK__SI 0x00000008L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_READ_ADD_INC_MASK__SI 0x00000001L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_READ_ADD_MASK__SI 0x00000060L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_START_DVOCLK_Q_MASK__SI 0x00000004L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_START_DVOCLK_RISE_MASK__SI 0x00000010L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_START_PIXCLK_MASK__SI 0x00000002L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_WRITE_ADD_MASK__SI 0x00000180L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_DE_IN_MASK__SI 0x00100000L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_FRAMEPULSE_IN_MASK__SI 0x00010000L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_HSYNC_IN_MASK__SI 0x00040000L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_PHASE_MASK__SI 0x00200000L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_START_MASK__SI 0x00080000L -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_VSYNC_IN_MASK__SI 0x00020000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_CAP_START_IN_MASK__SI 0x00400000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_COLOR_IN_MASK__SI 0x00000ff0L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DE_IN_MASK__SI 0x00000008L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DISP_IO_DVOCLK_MASK__SI 0x00020000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DVOCLK_C_MASK__SI 0x01000000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DVOCLK_D_MASK__SI 0x02000000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_HSYNC_IN_MASK__SI 0x00000002L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_PHASE_MASK__SI 0x00001000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_READ_ADD_INC_MASK__SI 0x00800000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_READ_ADD_MASK__SI 0x00018000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START_DVOCLK_MASK__SI 0x00100000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START_DVOCLK_RISE_MASK__SI 0x00200000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START_MASK__SI 0x00040000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START_PIXCLK_MASK__SI 0x00080000L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_VSYNC_IN_MASK__SI 0x00000004L -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_WRITE_ADD_MASK__SI 0x00006000L -#define DVOA_DEBUG5__DOUT_DVOA_PIXCLK_MASK__SI 0x00000001L -#define DVOA_DEBUG6__DOUT_DVOA_CAP_START_ON_DVOCLK_MASK__SI 0x10000000L -#define DVOA_DEBUG6__DOUT_DVOA_DVOCLK_MASK__SI 0x00000001L -#define DVOA_DEBUG6__DOUT_DVOA_DVOCNTL_MASK__SI 0x0000000eL -#define DVOA_DEBUG6__DOUT_DVOA_DVODATA_MASK__SI 0x0ffffff0L -#define DVOA_DEBUG6__DOUT_DVOA_STEREOSYNC_ON_DVOCLK_MASK__SI 0x20000000L -#define DVOA_DEBUG7__DOUT_DVOA_DDR_DVOCLK_DUPLICATE_MASK__SI 0x00001000L -#define DVOA_DEBUG7__DOUT_DVOA_DDR_DVOCLK_MASK__SI 0x00000001L -#define DVOA_DEBUG7__DOUT_DVOA_DDR_MVP_DVOCLK_DUPLICATE_MASK__SI 0x00010000L -#define DVOA_DEBUG7__DOUT_DVOA_DDR_MVP_DVOCLK_MASK__SI 0x00000010L -#define DVOA_DEBUG7__DOUT_DVOA_DVOCNTL_D_MASK__SI 0x0000000eL -#define DVOA_DEBUG7__DOUT_DVOA_DVO_DE_MASK__SI 0x00002000L -#define DVOA_DEBUG7__DOUT_DVOA_DVO_HSYNC_MASK__SI 0x00004000L -#define DVOA_DEBUG7__DOUT_DVOA_DVO_VSYNC_MASK__SI 0x00008000L -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVOCNTL_D_MASK__SI 0x00000060L -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVO_DE_MASK__SI 0x00020000L -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVO_HSYNC_MASK__SI 0x00040000L -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVO_VSYNC_MASK__SI 0x00080000L -#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK__SI 0x03000000L -#define DVO_CONTROL__DVO_CTL3_MASK__SI 0x80000000L -#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK__SI 0x00000100L -#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK__SI 0x00040000L -#define DVO_CONTROL__DVO_RATE_SELECT_MASK__SI 0x00000001L -#define DVO_CONTROL__DVO_REORDER_BITS_MASK__SI 0x10000000L -#define DVO_CONTROL__DVO_RESET_FIFO_MASK__SI 0x00010000L -#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK__SI 0x00000002L -#define DVO_CONTROL__DVO_SYNC_PHASE_MASK__SI 0x00020000L -#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK__SI 0x07ffffffL -#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK__SI 0x07ffffffL -#define DVO_CRC_EN__DVO_CRC2_EN_MASK__SI 0x00010000L -#define DVO_ENABLE__DVO_ENABLE_MASK__SI 0x00000001L -#define DVO_ENABLE__DVO_PIXEL_ENCODING_MASK__SI 0x00000100L -#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK__SI 0x00000100L -#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK__SI 0x00000003L -#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK__SI 0x00000007L -#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK__SI 0x00070000L -#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK__SI 0x0000f000L -#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK__SI 0x00000f00L -#define DVO_STRENGTH_CONTROL__DVOCLK_SRN_MASK__SI 0x02000000L -#define DVO_STRENGTH_CONTROL__DVOCLK_SRP_MASK__SI 0x01000000L -#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK__SI 0x10000000L -#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK__SI 0x20000000L -#define DVO_STRENGTH_CONTROL__DVO_SN_MASK__SI 0x000000f0L -#define DVO_STRENGTH_CONTROL__DVO_SP_MASK__SI 0x0000000fL -#define DVO_STRENGTH_CONTROL__DVO_SRN_MASK__SI 0x00020000L -#define DVO_STRENGTH_CONTROL__DVO_SRP_MASK__SI 0x00010000L -#define EFUSE_STATUS__CCF0_VALID_MASK__CI 0x00000001L -#define EFUSE_STATUS__RF0_MASK__CI 0x00ff0000L -#define EXP0__RESERVED_MASK 0xffffffffL -#define EXP1__RESERVED_MASK 0xffffffffL -#define EXP2__RESERVED_MASK 0xffffffffL -#define EXP3__RESERVED_MASK 0xffffffffL -#define EXP4__RESERVED_MASK 0xffffffffL -#define EXP5__RESERVED_MASK 0xffffffffL -#define EXP6__RESERVED_MASK 0xffffffffL -#define EXP7__RESERVED_MASK 0xffffffffL -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_DRIVER_ENABLE_MASK__SI 0x00000700L -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_POST_DIV_FORCE_MASK__SI 0x000f0000L -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_POST_DIV_RESET_MASK__SI 0x00000001L -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_POST_DIV_SELECT_MASK__SI 0x00000010L -#define EXT1_PPLL_CNTL__EXT1_PPLL_CP_MASK__SI 0x00000f00L -#define EXT1_PPLL_CNTL__EXT1_PPLL_CTL_MASK__SI 0x0000001fL -#define EXT1_PPLL_CNTL__EXT1_PPLL_IBIAS_MASK__SI 0xff000000L -#define EXT1_PPLL_CNTL__EXT1_PPLL_LF_MODE_MASK__SI 0x001ff000L -#define EXT1_PPLL_FB_DIV__EXT1_PPLL_FB_DIV_FRACTION_CNTL_MASK__SI 0x00000030L -#define EXT1_PPLL_FB_DIV__EXT1_PPLL_FB_DIV_FRACTION_MASK__SI 0x0000000fL -#define EXT1_PPLL_FB_DIV__EXT1_PPLL_FB_DIV_MASK__SI 0x07ff0000L -#define EXT1_PPLL_POST_DIV_SRC__EXT1_PPLL_POST_DIV_SRC_MASK__SI 0x00000001L -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV_HSYNC_EDGE_MASK__SI 0x00020000L -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV_HSYNC_EN_MASK__SI 0x00010000L -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV_HSYNC_MASK__SI 0x07f00000L -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV_MASK__SI 0x0000007fL -#define EXT1_PPLL_REF_DIV_SRC__EXT1_PPLL_REF_DIV_SRC_MASK__SI 0x00000007L -#define EXT1_PPLL_REF_DIV__EXT1_PPLL_CALIBRATION_REF_DIV_MASK__SI 0x0000f000L -#define EXT1_PPLL_REF_DIV__EXT1_PPLL_REF_DIV_MASK__SI 0x000003ffL -#define EXT1_PPLL_UPDATE_CNTL__EXT1_PPLL_AUTO_RESET_DISABLE_MASK__SI 0x00010000L -#define EXT1_PPLL_UPDATE_CNTL__EXT1_PPLL_UPDATE_PENDING_MASK__SI 0x00000001L -#define EXT1_PPLL_UPDATE_CNTL__EXT1_PPLL_UPDATE_POINT_MASK__SI 0x00000100L -#define EXT1_PPLL_UPDATE_LOCK__EXT1_PPLL_UPDATE_LOCK_MASK__SI 0x00000001L -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_DRIVER_ENABLE_MASK__SI 0x00000700L -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_POST_DIV_FORCE_MASK__SI 0x000f0000L -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_POST_DIV_RESET_MASK__SI 0x00000001L -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_POST_DIV_SELECT_MASK__SI 0x00000010L -#define EXT2_PPLL_CNTL__EXT2_PPLL_CP_MASK__SI 0x00000f00L -#define EXT2_PPLL_CNTL__EXT2_PPLL_CTL_MASK__SI 0x0000001fL -#define EXT2_PPLL_CNTL__EXT2_PPLL_IBIAS_MASK__SI 0xff000000L -#define EXT2_PPLL_CNTL__EXT2_PPLL_LF_MODE_MASK__SI 0x001ff000L -#define EXT2_PPLL_FB_DIV__EXT2_PPLL_FB_DIV_FRACTION_CNTL_MASK__SI 0x00000030L -#define EXT2_PPLL_FB_DIV__EXT2_PPLL_FB_DIV_FRACTION_MASK__SI 0x0000000fL -#define EXT2_PPLL_FB_DIV__EXT2_PPLL_FB_DIV_MASK__SI 0x07ff0000L -#define EXT2_PPLL_POST_DIV_SRC__EXT2_PPLL_POST_DIV_SRC_MASK__SI 0x00000001L -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV_HSYNC_EDGE_MASK__SI 0x00020000L -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV_HSYNC_EN_MASK__SI 0x00010000L -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV_HSYNC_MASK__SI 0x07f00000L -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV_MASK__SI 0x0000007fL -#define EXT2_PPLL_REF_DIV_SRC__EXT2_PPLL_REF_DIV_SRC_MASK__SI 0x00000007L -#define EXT2_PPLL_REF_DIV__EXT2_PPLL_CALIBRATION_REF_DIV_MASK__SI 0x0000f000L -#define EXT2_PPLL_REF_DIV__EXT2_PPLL_REF_DIV_MASK__SI 0x000003ffL -#define EXT2_PPLL_UPDATE_CNTL__EXT2_PPLL_AUTO_RESET_DISABLE_MASK__SI 0x00010000L -#define EXT2_PPLL_UPDATE_CNTL__EXT2_PPLL_UPDATE_PENDING_MASK__SI 0x00000001L -#define EXT2_PPLL_UPDATE_CNTL__EXT2_PPLL_UPDATE_POINT_MASK__SI 0x00000100L -#define EXT2_PPLL_UPDATE_LOCK__EXT2_PPLL_UPDATE_LOCK_MASK__SI 0x00000001L -#define EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK__SI 0x00000001L -#define EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK__SI 0x00000002L -#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK__SI 0x0fff0000L -#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK__SI 0x00000fffL -#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK__SI 0x00000fffL -#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK__SI 0x0fff0000L -#define FAST_AES0__RESERVED_MASK 0xffffffffL -#define FAST_AES1__RESERVED_MASK 0xffffffffL -#define FAST_AES2__RESERVED_MASK 0xffffffffL -#define FAST_AES3__RESERVED_MASK 0xffffffffL -#define FAST_AES4__RESERVED_MASK 0xffffffffL -#define FAST_AES5__RESERVED_MASK 0xffffffffL -#define FAST_AES6__RESERVED_MASK 0xffffffffL -#define FAST_AES7__RESERVED_MASK 0xffffffffL -#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK__SI 0x000f0000L -#define FBC_CNTL__FBC_COHERENCY_MODE_MASK__SI 0x00030000L -#define FBC_CNTL__FBC_EN_MASK__SI 0x80000000L -#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK__SI 0x00000001L -#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK__SI 0x02000000L -#define FBC_CNTL__FBC_SRC_SEL_MASK__SI 0x0000000eL -#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK__SI 0x00010000L -#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK__SI 0x00020000L -#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK__SI 0x00040000L -#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK__SI 0x00080000L -#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK__SI 0x00100000L -#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK__SI 0x0000000fL -#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK__SI 0x00000100L -#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK__SI 0x00000400L -#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK__SI 0x00000200L -#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK__SI 0x00000800L -#define FBC_COMP_MODE__FBC_IND_EN_MASK__SI 0x00010000L -#define FBC_COMP_MODE__FBC_RLE_EN_MASK__SI 0x00000001L -#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK__SI 0x000003ffL -#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK__SI 0x03ff0000L -#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK__SI 0x000003ffL -#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK__SI 0x03ff0000L -#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK__SI 0x00010000L -#define FBC_DEBUG0__FBC_DEBUG0_MASK__SI 0x00fe0000L -#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK__SI 0xff000000L -#define FBC_DEBUG0__FBC_PERF_MUX0_MASK__SI 0x000000ffL -#define FBC_DEBUG0__FBC_PERF_MUX1_MASK__SI 0x0000ff00L -#define FBC_DEBUG1__FBC_DEBUG1_MASK__SI 0xffffffffL -#define FBC_DEBUG2__FBC_DEBUG2_MASK__SI 0xffffffffL -#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK__SI 0x000000f0L -#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK__SI 0x00000300L -#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK__SI 0x00000008L -#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK__SI 0x00000003L -#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK__SI 0xffffffffL -#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK__SI 0xffffffffL -#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK__SI 0x000003ffL -#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK__SI 0x80000000L -#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK__SI 0xffffffffL -#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK__SI 0xffffffffL -#define FBC_IND_LUT0__FBC_IND_LUT0_MASK__SI 0x00ffffffL -#define FBC_IND_LUT10__FBC_IND_LUT10_MASK__SI 0x00ffffffL -#define FBC_IND_LUT11__FBC_IND_LUT11_MASK__SI 0x00ffffffL -#define FBC_IND_LUT12__FBC_IND_LUT12_MASK__SI 0x00ffffffL -#define FBC_IND_LUT13__FBC_IND_LUT13_MASK__SI 0x00ffffffL -#define FBC_IND_LUT14__FBC_IND_LUT14_MASK__SI 0x00ffffffL -#define FBC_IND_LUT15__FBC_IND_LUT15_MASK__SI 0x00ffffffL -#define FBC_IND_LUT1__FBC_IND_LUT1_MASK__SI 0x00ffffffL -#define FBC_IND_LUT2__FBC_IND_LUT2_MASK__SI 0x00ffffffL -#define FBC_IND_LUT3__FBC_IND_LUT3_MASK__SI 0x00ffffffL -#define FBC_IND_LUT4__FBC_IND_LUT4_MASK__SI 0x00ffffffL -#define FBC_IND_LUT5__FBC_IND_LUT5_MASK__SI 0x00ffffffL -#define FBC_IND_LUT6__FBC_IND_LUT6_MASK__SI 0x00ffffffL -#define FBC_IND_LUT7__FBC_IND_LUT7_MASK__SI 0x00ffffffL -#define FBC_IND_LUT8__FBC_IND_LUT8_MASK__SI 0x00ffffffL -#define FBC_IND_LUT9__FBC_IND_LUT9_MASK__SI 0x00ffffffL -#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK__SI 0x00010000L -#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK__SI 0x00000003L -#define FBC_MISC__FBC_DIVIDE_X_MASK__SI 0x00000300L -#define FBC_MISC__FBC_DIVIDE_Y_MASK__SI 0x00000400L -#define FBC_MISC__FBC_ERROR_PIXEL_MASK__SI 0x000000f0L -#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK__SI 0x00000008L -#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK__SI 0x00001000L -#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK__SI 0x00000800L -#define FBC_MISC__FBC_STOP_ON_ERROR_MASK__SI 0x00000004L -#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK__SI 0x00001f00L -#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK__SI 0x0000001fL -#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK__SI 0x00000080L -#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK__CI 0x00000001L -#define FIRMWARE_FLAGS__RESERVED_MASK__CI 0x00fffffeL -#define FIRMWARE_FLAGS__TEST_COUNT_MASK__CI 0xff000000L -#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK__SI 0x0c000000L -#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK__SI 0x30000000L -#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK__SI 0xc0000000L -#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK__SI 0x00002000L -#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK__SI 0x00008000L -#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK__SI 0x00004000L -#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK__SI 0x00001000L -#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK__SI 0x00000100L -#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK__SI 0x00000600L -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK__SI 0x00100000L -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK__SI 0x00010000L -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK__SI 0x00600000L -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK__SI 0x02000000L -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK__SI 0x01000000L -#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK__SI 0x00000010L -#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK__SI 0x00000001L -#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK__SI 0x00070000L -#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK__SI 0x00000001L -#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK__SI 0x00010000L -#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK__SI 0x00000010L -#define FMT_CRC_CNTL__FMT_CRC_EN_MASK__SI 0x00000001L -#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK__SI 0x00100000L -#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK__SI 0x01000000L -#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK__SI 0x00003000L -#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK__SI 0x00000100L -#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK__SI 0x00010000L -#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK__SI 0x0000ffffL -#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK__SI 0xffff0000L -#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK__SI 0x0000ffffL -#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK__SI 0xffff0000L -#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK__SI 0xffff0000L -#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK__SI 0x0000ffffL -#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK__SI 0xffff0000L -#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK__SI 0x0000ffffL -#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK__SI 0x00000003L -#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK__SI 0x000000ffL -#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK__SI 0x000000ffL -#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK__SI 0x000000ffL -#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK__SI 0x00000001L -#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK__SI 0x00000010L -#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK__SI 0x0000ffffL -#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK__SI 0xffff0000L -#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK__SI 0x0000ffffL -#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK__SI 0xffff0000L -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK__SI 0x00000001L -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK__SI 0x00010000L -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK__SI 0x00000700L -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK__SI 0x0000f000L -#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK__SI \ - 0x00000010L -#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK__SI \ - 0x00000001L -#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK__SI \ - 0xffffffffL -#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK__SI \ - 0xffffffffL -#define FREQ_CHANGE_TIMEOUT__FC_TIMEOUT_MASK__SI 0x0000ffffL -#define FREQ_CHANGE_TIMEOUT__FC_TIMEOUT_UNIT_MASK__SI 0x001f0000L -#define FWD_CHROMA_BOT_ADDR__FWD_UV_BOT_BASE_MASK__SI 0xffffffffL -#define FWD_CHROMA_TOP_ADDR__FWD_UV_TOP_BASE_MASK__SI 0xffffffffL -#define FWD_LUMA_BOT_ADDR__FWD_Y_BOT_BASE_MASK__SI 0xffffffffL -#define FWD_LUMA_TOP_ADDR__FWD_Y_TOP_BASE_MASK__SI 0xffffffffL -#define FW_CHRONO_31_0__FW_CHRONO_31_0_MASK__CI__VI 0xffffffffL -#define FW_CHRONO_63_32__FW_CHRONO_63_32_MASK__CI__VI 0xffffffffL -#define FW_DBG_COUNTER_1__COUNT1_MASK__CI__VI 0x0000ffffL -#define FW_DBG_COUNTER_1__COUNT2_MASK__CI__VI 0xffff0000L -#define FW_DBG_COUNTER_2__COUNT1_MASK__CI__VI 0x0000ffffL -#define FW_DBG_COUNTER_2__COUNT2_MASK__CI__VI 0xffff0000L -#define FW_DBG_SIGNAL_1__DATA_MASK__CI__VI 0x00ffffffL -#define FW_DBG_SIGNAL_2__DATA_MASK__CI__VI 0x00ffffffL -#define FW_PC_WATCH_1__ADDR_MASK__CI__VI 0xffffffffL -#define FW_PC_WATCH_2__ADDR_MASK__CI__VI 0xffff0000L -#define FW_PC_WATCH_3__ADDR_MASK__CI__VI 0xffffffffL -#define FW_PC_WATCH_4__ADDR_MASK__CI__VI 0xffff0000L -#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK__CI__VI 0xfffffffcL -#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK__CI__VI 0x00000040L -#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK__CI__VI 0x00000080L -#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK__CI__VI 0x00000001L -#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK__CI__VI 0x00000002L -#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK__CI__VI 0x00000004L -#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK__CI__VI 0x80000000L -#define GARLIC_FLUSH_CNTL__DISPLAY_MASK__CI__VI 0x00010000L -#define GARLIC_FLUSH_CNTL__DOORBELL_MASK__CI 0x00002000L -#define GARLIC_FLUSH_CNTL__SDMA1_RB_WPTR_MASK__CI 0x00000020L -#define GARLIC_FLUSH_CNTL__SDMA_RB_WPTR_MASK__CI 0x00000010L -#define GARLIC_FLUSH_CNTL__SPU_RBI_WPTR_MASK__CI 0x00000100L -#define GARLIC_FLUSH_CNTL__SPU_RBO_WPTR_MASK__CI 0x00000200L -#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK__CI__VI 0x00000008L -#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK__CI__VI 0x00000400L -#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK__CI__VI 0x00000800L -#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK__CI__VI 0x00001000L -#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK__CI__VI 0x00000001L -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L -#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L -#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L -#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L -#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffffL -#define GB_EDC_MODE__BYPASS_MASK 0x80000000L -#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L -#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00010000L -#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L -#define GB_GPU_ID__GPU_ID_MASK 0x0000000fL -#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE0__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE10__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE11__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE12__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE13__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE14__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE15__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE1__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE2__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE3__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE4__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE5__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE6__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE7__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE8__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK__CI__VI 0x0000000cL -#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK__CI__VI 0x00000003L -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK__CI__VI 0x00000030L -#define GB_MACROTILE_MODE9__NUM_BANKS_MASK__CI__VI 0x000000c0L -#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE0__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE0__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE0__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE0__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE0__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE10__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE10__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE10__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE10__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE10__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE11__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE11__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE11__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE11__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE11__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE12__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE12__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE12__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE12__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE12__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE13__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE13__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE13__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE13__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE13__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE14__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE14__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE14__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE14__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE14__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE15__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE15__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE15__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE15__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE15__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE16__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE16__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE16__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE16__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE16__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE17__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE17__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE17__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE17__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE17__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE18__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE18__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE18__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE18__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE18__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE19__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE19__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE19__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE19__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE19__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE1__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE1__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE1__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE1__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE1__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE20__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE20__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE20__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE20__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE20__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE21__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE21__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE21__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE21__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE21__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE22__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE22__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE22__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE22__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE22__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE23__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE23__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE23__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE23__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE23__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE24__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE24__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE24__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE24__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE24__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE25__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE25__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE25__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE25__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE25__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE26__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE26__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE26__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE26__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE26__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE27__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE27__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE27__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE27__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE27__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE28__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE28__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE28__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE28__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE28__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE29__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE29__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE29__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE29__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE29__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE2__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE2__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE2__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE2__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE2__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE30__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE30__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE30__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE30__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE30__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE31__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE31__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE31__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE31__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE31__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE3__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE3__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE3__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE3__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE3__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE4__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE4__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE4__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE4__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE4__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE5__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE5__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE5__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE5__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE5__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE6__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE6__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE6__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE6__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE6__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE7__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE7__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE7__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE7__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE7__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE8__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE8__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE8__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE8__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE8__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE9__BANK_HEIGHT_MASK__SI 0x00030000L -#define GB_TILE_MODE9__BANK_WIDTH_MASK__SI 0x0000c000L -#define GB_TILE_MODE9__MACRO_TILE_ASPECT_MASK__SI 0x000c0000L -#define GB_TILE_MODE9__MICRO_TILE_MODE_MASK__SI 0x00000003L -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK__CI__VI 0x01c00000L -#define GB_TILE_MODE9__NUM_BANKS_MASK__SI 0x00300000L -#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK__CI__VI 0x06000000L -#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L -#define GCK_ACLK_FUSES__AClkADCA_MASK__CI__VI 0x00000780L -#define GCK_ACLK_FUSES__AClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_ACLK_FUSES__AClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_ACLK_FUSES__AClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GCK_ACLK_FUSES__StartupAClkDid_MASK__CI__VI 0x0000007fL -#define GCK_DCLK_FUSES__DClkADCA_MASK__CI__VI 0x00000780L -#define GCK_DCLK_FUSES__DClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_DCLK_FUSES__DClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_DCLK_FUSES__DClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GCK_DCLK_FUSES__StartupDClkDid_MASK__CI__VI 0x0000007fL -#define GCK_DISPCLK_FUSES__DispClkADCA_MASK__CI__VI 0x00000780L -#define GCK_DISPCLK_FUSES__DispClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_DISPCLK_FUSES__DispClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_DISPCLK_FUSES__DispClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GCK_DISPCLK_FUSES__StartupDispClkDid_MASK__CI__VI 0x0000007fL -#define GCK_DPREFCLK_FUSES__DpRefClkADCA_MASK__CI__VI 0x00000780L -#define GCK_DPREFCLK_FUSES__DpRefClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_DPREFCLK_FUSES__DpRefClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_DPREFCLK_FUSES__DpRefClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GCK_DPREFCLK_FUSES__StartupDpRefClkDid_MASK__CI__VI 0x0000007fL -#define GCK_ECLK_FUSES__EClkADCA_MASK__CI__VI 0x00000780L -#define GCK_ECLK_FUSES__EClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_ECLK_FUSES__EClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_ECLK_FUSES__EClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GCK_ECLK_FUSES__StartupEClkDid_MASK__CI__VI 0x0000007fL -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_CLKF_UPDATE_MASK__CI 0x40000000L -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_CLKR_UPDATE_MASK__CI 0x80000000L -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_FB_DIV_MASK__CI__VI 0x03ffffffL -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_RESET_EN_MASK__CI 0x20000000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_BG_PDN_MASK__CI 0x00400000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_FBCLK_SEL_MASK__CI__VI 0x01000000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_ILOCK_MASK__CI__VI 0x00800000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_REG_BIAS_MASK__CI 0x001c0000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EN_MASK__CI 0x000000c0L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EXT_MASK__CI__VI 0x0c000000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EXT_SEL_MASK__CI 0x00000030L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_TEST_SEL_MASK__CI 0x00000007L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SPARE_EXT_MASK__CI__VI 0x70000000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SPARE_MASK__CI 0x0003ff00L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_TEST_FRAC_BYPASS_MASK__CI 0x00200000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_VCTRLADC_EN_MASK__CI__VI 0x02000000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_VTOI_BIAS_CNTL_MASK__CI__VI 0x80000000L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_FAST_LOCK_CNTRL_MASK__CI__VI 0x000000c0L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_FAST_LOCK_EN_MASK__CI__VI 0x00000100L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_FBDIV_SSC_BYPASS_MASK__CI 0x00000001L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_PFD_RESET_CNTRL_MASK__CI__VI 0x0000000cL -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_RESET_ANTI_MUX_MASK__CI__VI 0x00000200L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_RESET_TIMER_MASK__CI__VI 0x00000030L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_RISEFBVCO_EN_MASK__CI__VI 0x00000002L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_BYPASS_EN_MASK__CI 0x01000000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_DITHEN_MASK__CI__VI 0x00000200L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_INIT_RESET_TIMER_MASK__CI 0x007ff800L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_REFCLK_DIV_MASK__CI__VI 0x000001f8L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_RESET_MASK__CI 0x00800000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_SLEEP_MASK__CI 0x04000000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_SW_DIR_CONTROL_MASK__CI__VI 0x00000001L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_UNLOCK_CLEAR_MASK__CI 0x08000000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_VCOMODE_MASK__CI__VI 0x00000006L -#define GCK_GPUPLL_SPREAD_SPECTRUM_2__GPUPLL_CLKV_MASK__CI__VI 0x03ffffffL -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_BWADJ_MASK__CI 0x0fff0000L -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_CLKS_MASK__CI__VI 0x0000fff0L -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_SSEN_MASK__CI__VI 0x00000003L -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_SS_SPARE_MASK__CI 0x0000000cL -#define GCK_GPUPLL_STATUS__GPUPLL_CLKF_ACK_MASK__CI__VI 0x00000004L -#define GCK_GPUPLL_STATUS__GPUPLL_CLKR_ACK_MASK__CI 0x00000008L -#define GCK_GPUPLL_STATUS__GPUPLL_CTLACK_A_MASK__CI 0x00000001L -#define GCK_GPUPLL_STATUS__GPUPLL_CTLACK_B_MASK__CI 0x00000002L -#define GCK_GPUPLL_STATUS__GPUPLL_INTRESET_MASK__CI__VI 0x00001000L -#define GCK_GPUPLL_STATUS__GPUPLL_OSPARE_MASK__CI__VI 0x00000f00L -#define GCK_GPUPLL_STATUS__GPUPLL_UNLOCK_MASK__CI__VI 0x00010000L -#define GCK_GPUPLL_STATUS__GPUPLL_UNLOCK_STICKY_MASK__CI__VI 0x00020000L -#define GCK_GPUPLL_STATUS__GPUPLL_VCTRLADC_MASK__CI 0x000000f0L -#define GCK_MISC_2__miscRegisters_MASK__CI__VI 0xffffffe0L -#define GCK_MISC_FUSES__FastClkRampDis_MASK__CI__VI 0x00000001L -#define GCK_MISC_FUSES__WRCKDid_MASK__CI__VI 0x0000003eL -#define GCK_MISC_FUSES__WRITE_DIS_MASK__CI__VI 0x80000000L -#define GCK_MISC__EnableACLKInBypass_MASK__CI__VI 0x00000020L -#define GCK_MISC__EnableDCLKInBypass_MASK__CI__VI 0x00000001L -#define GCK_MISC__EnableDISPCLKInBypass_MASK__CI__VI 0x00000008L -#define GCK_MISC__EnableDPREFCLKInBypass_MASK__CI__VI 0x00000010L -#define GCK_MISC__EnableECLKInBypass_MASK__CI__VI 0x00000004L -#define GCK_MISC__EnableEVCLKInBypass_MASK__CI__VI 0x00000080L -#define GCK_MISC__EnableSAMCLKInBypass_MASK__CI__VI 0x00000040L -#define GCK_MISC__EnableVCLKInBypass_MASK__CI__VI 0x00000002L -#define GCK_MISC__miscRegisters_MASK__CI 0xffffff00L -#define GCK_PLL_CONTROL__BypassClocks_MASK__CI__VI 0x00000020L -#define GCK_PLL_CONTROL__PllBGPwrDn_MASK__CI__VI 0x00000002L -#define GCK_PLL_CONTROL__PllLockEn_MASK__CI__VI 0x00000010L -#define GCK_PLL_CONTROL__PllPwrDnReg_MASK__CI__VI 0x00000001L -#define GCK_PLL_CONTROL__PllReset_MASK__CI__VI 0x00000008L -#define GCK_PLL_CONTROL__TogglePllFbReq_MASK__CI__VI 0x00000040L -#define GCK_PLL_DGCK_CNTL__PLL_REFCLK_SEL_MASK__CI__VI 0x0c000000L -#define GCK_PLL_FUSES__GckFuseProg_MASK__CI__VI 0x00000001L -#define GCK_PLL_FUSES__MainPllBGCal_MASK__CI__VI 0x003c0000L -#define GCK_PLL_FUSES__MainPllBGRefAdj_MASK__CI__VI 0x0003e000L -#define GCK_PLL_FUSES__MainPllDutyCycleAdj_MASK__CI__VI 0x03c00000L -#define GCK_PLL_FUSES__MainPllFracDiv_MASK__CI__VI 0x3c000000L -#define GCK_PLL_FUSES__MainPllOTAHalfGain_MASK__CI__VI 0x40000000L -#define GCK_PLL_FUSES__MainPllOpFreqIdMax_MASK__CI__VI 0x00001f80L -#define GCK_PLL_FUSES__MainPllOpFreqIdStartup_MASK__CI__VI 0x0000007eL -#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK__CI 0x00007f00L -#define GCK_PLL_TEST_CNTL__TEST_COUNT_MASK__CI 0xfffe0000L -#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK__CI 0x00010000L -#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK__CI 0x000000f0L -#define GCK_PLL_TEST_CNTL__TST_RESET_MASK__CI 0x00008000L -#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK__CI 0x0000000fL -#define GCK_SAMCLK_FUSES__SAMClkADCA_MASK__CI__VI 0x00000780L -#define GCK_SAMCLK_FUSES__SAMClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_SAMCLK_FUSES__SAMClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_SAMCLK_FUSES__SAMClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GCK_SAMCLK_FUSES__StartupSAMClkDid_MASK__CI__VI 0x0000007fL -#define GCK_SCLK_FUSES__MinSClkDid_MASK__CI__VI 0x01fc0000L -#define GCK_SCLK_FUSES__SClkADCA_MASK__CI__VI 0x00000780L -#define GCK_SCLK_FUSES__SClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_SCLK_FUSES__SClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_SCLK_FUSES__SClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GCK_SCLK_FUSES__StartupSClkDid_MASK__CI__VI 0x0000007fL -#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define GCK_SPLL_FUSES__SPLLFreqIdMax_MASK__CI__VI 0x00001f80L -#define GCK_SPLL_FUSES__SPLLFreqIdStartup_MASK__CI__VI 0x0000007eL -#define GCK_SPLL_FUSES__SPllMiscFuseCtl_MASK__CI__VI 0x003c0000L -#define GCK_SPLL_FUSES__SPllRefAdj_MASK__CI__VI 0x0003e000L -#define GCK_SPLL_FUSES__UseSPll_MASK__CI__VI 0x00000001L -#define GCK_VCLK_FUSES__StartupVClkDid_MASK__CI__VI 0x0000007fL -#define GCK_VCLK_FUSES__VClkADCA_MASK__CI__VI 0x00000780L -#define GCK_VCLK_FUSES__VClkDDCA_MASK__CI__VI 0x00001800L -#define GCK_VCLK_FUSES__VClkDiDtFloor_MASK__CI__VI 0x00030000L -#define GCK_VCLK_FUSES__VClkDiDtWait_MASK__CI__VI 0x0000e000L -#define GC_PRIV_MODE__MC_PRIV_MODE_MASK 0x00000001L -#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK__CI__VI 0x00030000L -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK__CI__VI 0x0f000000L -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK__CI__VI 0x00001000L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK__CI__VI 0x00100000L -#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK__CI__VI 0x00000f00L -#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK__CI__VI 0x000f0000L -#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK__CI 0x00000006L -#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK__CI 0x00000010L -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L -#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK__CI 0x00000008L -#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L -#define GDS_ATOM_BASE__BASE_MASK 0x0000ffffL -#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000L -#define GDS_ATOM_CNTL__AINC_MASK 0x0000003fL -#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000c0L -#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L -#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffeL -#define GDS_ATOM_DST__DST_MASK 0xffffffffL -#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000ffL -#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00L -#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000ffL -#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00L -#define GDS_ATOM_OP__OP_MASK 0x000000ffL -#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00L -#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffffL -#define GDS_ATOM_READ0__DATA_MASK 0xffffffffL -#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffffL -#define GDS_ATOM_READ1__DATA_MASK 0xffffffffL -#define GDS_ATOM_SIZE__SIZE_MASK 0x0000ffffL -#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000L -#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffffL -#define GDS_ATOM_SRC0__DATA_MASK 0xffffffffL -#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffffL -#define GDS_ATOM_SRC1__DATA_MASK 0xffffffffL -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L -#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L -#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L -#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L -#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK__CI__VI 0x00000fffL -#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L -#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L -#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L -#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L -#define GDS_CONFIG__WRITE_DIS_MASK 0x00000001L -#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x0000001fL -#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0L -#define GDS_DEBUG_DATA__DATA_MASK 0xffffffffL -#define GDS_DEBUG_REG0__buff_write_MASK__CI__VI 0x00020000L -#define GDS_DEBUG_REG0__cstate_MASK__CI__VI 0x0001e000L -#define GDS_DEBUG_REG0__flush_request_MASK__CI__VI 0x00040000L -#define GDS_DEBUG_REG0__last_pixel_ptr_MASK__CI__VI 0x00001000L -#define GDS_DEBUG_REG0__se0_VGT_rdreq_addr_MASK__SI 0x0000007eL -#define GDS_DEBUG_REG0__se0_re0_MASK__SI 0x00000400L -#define GDS_DEBUG_REG0__se0_re1_MASK__SI 0x00000200L -#define GDS_DEBUG_REG0__se0_re2_MASK__SI 0x00000100L -#define GDS_DEBUG_REG0__se0_re3_MASK__SI 0x00000080L -#define GDS_DEBUG_REG0__se0_simd_id_MASK__SI 0x00380000L -#define GDS_DEBUG_REG0__se0_wave_fifo_empty_MASK__SI 0x00400000L -#define GDS_DEBUG_REG0__se0_wave_fifo_full_MASK__SI 0x00800000L -#define GDS_DEBUG_REG0__se0_wave_id_MASK__SI 0x0007f800L -#define GDS_DEBUG_REG0__spare1_MASK__CI__VI 0x0000003fL -#define GDS_DEBUG_REG0__spare1_MASK__SI 0x00000001L -#define GDS_DEBUG_REG0__spare_MASK__CI__VI 0xffc00000L -#define GDS_DEBUG_REG0__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK__CI__VI 0x00100000L -#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK__CI__VI 0x00200000L -#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK__CI__VI 0x00080000L -#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK__CI__VI 0x00000f80L -#define GDS_DEBUG_REG0__write_buff_valid_MASK__CI__VI 0x00000040L -#define GDS_DEBUG_REG10__se1_cmd_broadcast_MASK__SI 0x00080000L -#define GDS_DEBUG_REG10__se1_cmd_eog_MASK__SI 0x00800000L -#define GDS_DEBUG_REG10__se1_cmd_gpr_dst_MASK__SI 0x0007f800L -#define GDS_DEBUG_REG10__se1_cmd_last_quad_MASK__SI 0x00400000L -#define GDS_DEBUG_REG10__se1_cmd_read_op_MASK__SI 0x00100000L -#define GDS_DEBUG_REG10__se1_cmd_ret_data_op_MASK__SI 0x00200000L -#define GDS_DEBUG_REG10__se1_cmd_wave_id_MASK__SI 0x000007f8L -#define GDS_DEBUG_REG10__se1_launch_phase_MASK__SI 0x00000001L -#define GDS_DEBUG_REG10__se1_mem_data_rdy_MASK__SI 0x00000004L -#define GDS_DEBUG_REG10__se1_send_rddone_MASK__SI 0x00000002L -#define GDS_DEBUG_REG10__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG1__VGT_write_buff_valid_MASK__SI 0x00000040L -#define GDS_DEBUG_REG1__addr_fifo_empty_MASK__CI__VI 0x00200000L -#define GDS_DEBUG_REG1__addr_fifo_full_MASK__CI__VI 0x00100000L -#define GDS_DEBUG_REG1__awaiting_data_MASK__CI__VI 0x00080000L -#define GDS_DEBUG_REG1__buff_write_MASK__SI 0x00080000L -#define GDS_DEBUG_REG1__buffer_invalid_MASK__CI__VI 0x00800000L -#define GDS_DEBUG_REG1__buffer_loaded_MASK__CI__VI 0x00400000L -#define GDS_DEBUG_REG1__cstate_MASK__SI 0x0007e000L -#define GDS_DEBUG_REG1__data_ready_MASK__CI__VI 0x00040000L -#define GDS_DEBUG_REG1__flush_request_MASK__SI 0x00100000L -#define GDS_DEBUG_REG1__last_pixel_ptr_MASK__SI 0x00001000L -#define GDS_DEBUG_REG1__pixel_addr_MASK__CI__VI 0x0001fffcL -#define GDS_DEBUG_REG1__pixel_vld_MASK__CI__VI 0x00020000L -#define GDS_DEBUG_REG1__spare1_MASK__SI 0x0000003fL -#define GDS_DEBUG_REG1__spare_MASK 0xff000000L -#define GDS_DEBUG_REG1__tag_hit_MASK__CI__VI 0x00000001L -#define GDS_DEBUG_REG1__tag_miss_MASK__CI__VI 0x00000002L -#define GDS_DEBUG_REG1__wbuf_fifo_empty_MASK__SI 0x00400000L -#define GDS_DEBUG_REG1__wbuf_fifo_full_MASK__SI 0x00800000L -#define GDS_DEBUG_REG1__wr_buffer_wr_complete_MASK__SI 0x00200000L -#define GDS_DEBUG_REG1__wr_pixel_nxt_ptr_MASK__SI 0x00000f80L -#define GDS_DEBUG_REG2__addr_fifo_empty_MASK__SI 0x00200000L -#define GDS_DEBUG_REG2__addr_fifo_full_MASK__SI 0x00100000L -#define GDS_DEBUG_REG2__app_sel_MASK__CI__VI 0x000000f0L -#define GDS_DEBUG_REG2__awaiting_data_MASK__SI 0x00080000L -#define GDS_DEBUG_REG2__buffer_invalid_MASK__SI 0x00800000L -#define GDS_DEBUG_REG2__buffer_loaded_MASK__SI 0x00400000L -#define GDS_DEBUG_REG2__cmd_write_MASK__CI__VI 0x00000008L -#define GDS_DEBUG_REG2__data_ready_MASK__SI 0x00040000L -#define GDS_DEBUG_REG2__ds_credit_avail_MASK__CI__VI 0x00000002L -#define GDS_DEBUG_REG2__ds_full_MASK__CI__VI 0x00000001L -#define GDS_DEBUG_REG2__ord_idx_free_MASK__CI__VI 0x00000004L -#define GDS_DEBUG_REG2__pixel_addr_MASK__SI 0x0001fffcL -#define GDS_DEBUG_REG2__pixel_vld_MASK__SI 0x00020000L -#define GDS_DEBUG_REG2__req_MASK__CI__VI 0x007fff00L -#define GDS_DEBUG_REG2__spare_MASK__CI__VI 0xff800000L -#define GDS_DEBUG_REG2__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG2__tag_hit_MASK__SI 0x00000001L -#define GDS_DEBUG_REG2__tag_miss_MASK__SI 0x00000002L -#define GDS_DEBUG_REG3__pipe0_busy_num_MASK__CI__VI 0x00007800L -#define GDS_DEBUG_REG3__pipe_num_busy_MASK__CI__VI 0x000007ffL -#define GDS_DEBUG_REG3__pipe_stall_MASK__SI 0x00000008L -#define GDS_DEBUG_REG3__pipe_waddr_MASK__SI 0x00001ff0L -#define GDS_DEBUG_REG3__pipe_we_MASK__SI 0x00002000L -#define GDS_DEBUG_REG3__se0_ord_valid_MASK__SI 0x00004000L -#define GDS_DEBUG_REG3__spare1_MASK__SI 0x00000001L -#define GDS_DEBUG_REG3__spare_MASK__CI__VI 0xffff8000L -#define GDS_DEBUG_REG3__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG3__wave_id_ack_MASK__SI 0x00000002L -#define GDS_DEBUG_REG3__wave_id_valid_MASK__SI 0x00000004L -#define GDS_DEBUG_REG3__wc_se_sel_MASK__SI 0x00008000L -#define GDS_DEBUG_REG3__wc_wave_id_MASK__SI 0x00ff0000L -#define GDS_DEBUG_REG4__cmd_write_MASK__CI__VI 0x00020000L -#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK__CI__VI 0x00010000L -#define GDS_DEBUG_REG4__cur_reso_MASK__CI__VI 0x000001f8L -#define GDS_DEBUG_REG4__cur_reso_barrier_MASK__CI__VI 0x00002000L -#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK__CI__VI 0x00008000L -#define GDS_DEBUG_REG4__cur_reso_fed_MASK__CI__VI 0x00001000L -#define GDS_DEBUG_REG4__cur_reso_flag_MASK__CI__VI 0x00004000L -#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK__CI__VI 0x00000400L -#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK__CI__VI 0x00000800L -#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK__CI__VI 0x00000200L -#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK__CI__VI 0x00080000L -#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK__CI__VI 0x00040000L -#define GDS_DEBUG_REG4__gws_bulkfree_MASK__CI__VI 0x00200000L -#define GDS_DEBUG_REG4__gws_busy_MASK__CI__VI 0x00000001L -#define GDS_DEBUG_REG4__gws_out_stall_MASK__CI__VI 0x00000004L -#define GDS_DEBUG_REG4__gws_req_MASK__CI__VI 0x00000002L -#define GDS_DEBUG_REG4__ram_gws_re_MASK__CI__VI 0x00400000L -#define GDS_DEBUG_REG4__ram_gws_we_MASK__CI__VI 0x00800000L -#define GDS_DEBUG_REG4__ram_read_busy_MASK__CI__VI 0x00100000L -#define GDS_DEBUG_REG4__se0_bcast_fifo_empty_MASK__SI 0x00080000L -#define GDS_DEBUG_REG4__se0_bcast_fifo_full_MASK__SI 0x00100000L -#define GDS_DEBUG_REG4__se0_bcast_first_we_MASK__SI 0x00060000L -#define GDS_DEBUG_REG4__se0_bcast_phase_MASK__SI 0x00006000L -#define GDS_DEBUG_REG4__se0_bcast_sp_id_MASK__SI 0x00018000L -#define GDS_DEBUG_REG4__se0_gds_cmd_ret_MASK__SI 0x00400000L -#define GDS_DEBUG_REG4__se0_gds_op_MASK__SI 0x00800000L -#define GDS_DEBUG_REG4__se0_gds_ord_append_MASK__SI 0x00200000L -#define GDS_DEBUG_REG4__se0_last_qpipe_active_MASK__SI 0x00000004L -#define GDS_DEBUG_REG4__se0_sp0_active_MASK__SI 0x00000040L -#define GDS_DEBUG_REG4__se0_sp1_active_MASK__SI 0x00000020L -#define GDS_DEBUG_REG4__se0_sp2_active_MASK__SI 0x00000010L -#define GDS_DEBUG_REG4__se0_sp3_active_MASK__SI 0x00000008L -#define GDS_DEBUG_REG4__se0_two_addr_req_MASK__SI 0x00000001L -#define GDS_DEBUG_REG4__se0_uav_active_MASK__SI 0x00000002L -#define GDS_DEBUG_REG4__se0_uav_id_MASK__SI 0x00000380L -#define GDS_DEBUG_REG4__se0_uav_st_ptr_MASK__SI 0x00001c00L -#define GDS_DEBUG_REG4__spare_MASK 0xff000000L -#define GDS_DEBUG_REG5__alloc_opco_error_MASK__CI__VI 0x00000004L -#define GDS_DEBUG_REG5__dealloc_opco_error_MASK__CI__VI 0x00000008L -#define GDS_DEBUG_REG5__dec_error_MASK__CI__VI 0x00000002L -#define GDS_DEBUG_REG5__error_ds_address_MASK__CI__VI 0x003fff00L -#define GDS_DEBUG_REG5__se0_bcast_fifo_empty_MASK__SI 0x00080000L -#define GDS_DEBUG_REG5__se0_gpr_dst_q_MASK__SI 0x000007f8L -#define GDS_DEBUG_REG5__se0_instr_fifo_empty_MASK__SI 0x00400000L -#define GDS_DEBUG_REG5__se0_instr_fifo_full_MASK__SI 0x00800000L -#define GDS_DEBUG_REG5__se0_instr_fifo_re_MASK__SI 0x00100000L -#define GDS_DEBUG_REG5__se0_instr_fifo_we_MASK__SI 0x00200000L -#define GDS_DEBUG_REG5__se0_read_line_ns_MASK__SI 0x00000007L -#define GDS_DEBUG_REG5__se0_wave_id_q_MASK__SI 0x0007f800L -#define GDS_DEBUG_REG5__spare1_MASK__CI__VI 0xffc00000L -#define GDS_DEBUG_REG5__spare_MASK__CI__VI 0x000000e0L -#define GDS_DEBUG_REG5__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG5__wrap_opco_error_MASK__CI__VI 0x00000010L -#define GDS_DEBUG_REG5__write_dis_MASK__CI__VI 0x00000001L -#define GDS_DEBUG_REG6__counters_busy_MASK__CI__VI 0x001fffe0L -#define GDS_DEBUG_REG6__counters_enabled_MASK__CI__VI 0x0000001eL -#define GDS_DEBUG_REG6__oa_busy_MASK__CI__VI 0x00000001L -#define GDS_DEBUG_REG6__se0_cmd_broadcast_MASK__SI 0x00080000L -#define GDS_DEBUG_REG6__se0_cmd_eog_MASK__SI 0x00800000L -#define GDS_DEBUG_REG6__se0_cmd_gpr_dst_MASK__SI 0x0007f800L -#define GDS_DEBUG_REG6__se0_cmd_last_quad_MASK__SI 0x00400000L -#define GDS_DEBUG_REG6__se0_cmd_read_op_MASK__SI 0x00100000L -#define GDS_DEBUG_REG6__se0_cmd_ret_data_op_MASK__SI 0x00200000L -#define GDS_DEBUG_REG6__se0_cmd_wave_id_MASK__SI 0x000007f8L -#define GDS_DEBUG_REG6__se0_launch_phase_MASK__SI 0x00000001L -#define GDS_DEBUG_REG6__se0_mem_data_rdy_MASK__SI 0x00000004L -#define GDS_DEBUG_REG6__se0_send_rddone_MASK__SI 0x00000002L -#define GDS_DEBUG_REG6__spare_MASK__CI__VI 0xffe00000L -#define GDS_DEBUG_REG6__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG7__se1_VGT_rdreq_addr_MASK__SI 0x0000007eL -#define GDS_DEBUG_REG7__se1_re0_MASK__SI 0x00000400L -#define GDS_DEBUG_REG7__se1_re1_MASK__SI 0x00000200L -#define GDS_DEBUG_REG7__se1_re2_MASK__SI 0x00000100L -#define GDS_DEBUG_REG7__se1_re3_MASK__SI 0x00000080L -#define GDS_DEBUG_REG7__se1_simd_id_MASK__SI 0x00380000L -#define GDS_DEBUG_REG7__se1_wave_fifo_empty_MASK__SI 0x00400000L -#define GDS_DEBUG_REG7__se1_wave_fifo_full_MASK__SI 0x00800000L -#define GDS_DEBUG_REG7__se1_wave_id_MASK__SI 0x0007f800L -#define GDS_DEBUG_REG7__spare1_MASK__SI 0x00000001L -#define GDS_DEBUG_REG7__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG8__se1_bcast_fifo_empty_MASK__SI 0x00080000L -#define GDS_DEBUG_REG8__se1_bcast_fifo_full_MASK__SI 0x00100000L -#define GDS_DEBUG_REG8__se1_bcast_first_we_MASK__SI 0x00060000L -#define GDS_DEBUG_REG8__se1_bcast_phase_MASK__SI 0x00006000L -#define GDS_DEBUG_REG8__se1_bcast_sp_id_MASK__SI 0x00018000L -#define GDS_DEBUG_REG8__se1_gds_cmd_ret_MASK__SI 0x00400000L -#define GDS_DEBUG_REG8__se1_gds_op_MASK__SI 0x00800000L -#define GDS_DEBUG_REG8__se1_gds_ord_append_MASK__SI 0x00200000L -#define GDS_DEBUG_REG8__se1_last_qpipe_active_MASK__SI 0x00000004L -#define GDS_DEBUG_REG8__se1_sp0_active_MASK__SI 0x00000040L -#define GDS_DEBUG_REG8__se1_sp1_active_MASK__SI 0x00000020L -#define GDS_DEBUG_REG8__se1_sp2_active_MASK__SI 0x00000010L -#define GDS_DEBUG_REG8__se1_sp3_active_MASK__SI 0x00000008L -#define GDS_DEBUG_REG8__se1_two_addr_req_MASK__SI 0x00000001L -#define GDS_DEBUG_REG8__se1_uav_active_MASK__SI 0x00000002L -#define GDS_DEBUG_REG8__se1_uav_id_MASK__SI 0x00000380L -#define GDS_DEBUG_REG8__se1_uav_st_ptr_MASK__SI 0x00001c00L -#define GDS_DEBUG_REG8__spare_MASK__SI 0xff000000L -#define GDS_DEBUG_REG9__se1_bcast_fifo_empty_MASK__SI 0x00080000L -#define GDS_DEBUG_REG9__se1_gpr_dst_q_MASK__SI 0x000007f8L -#define GDS_DEBUG_REG9__se1_instr_fifo_empty_MASK__SI 0x00400000L -#define GDS_DEBUG_REG9__se1_instr_fifo_full_MASK__SI 0x00800000L -#define GDS_DEBUG_REG9__se1_instr_fifo_re_MASK__SI 0x00100000L -#define GDS_DEBUG_REG9__se1_instr_fifo_we_MASK__SI 0x00200000L -#define GDS_DEBUG_REG9__se1_read_line_ns_MASK__SI 0x00000007L -#define GDS_DEBUG_REG9__se1_wave_id_q_MASK__SI 0x0007f800L -#define GDS_DEBUG_REG9__spare_MASK__SI 0xff000000L -#define GDS_ENHANCE2__MISC_MASK__CI__VI 0x0000ffffL -#define GDS_ENHANCE2__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_ENHANCE__AUTO_INC_INDEX_MASK__CI__VI 0x00010000L -#define GDS_ENHANCE__CGPG_RESTORE_MASK__CI__VI 0x00020000L -#define GDS_ENHANCE__MISC_MASK 0x0000ffffL -#define GDS_ENHANCE__UNUSED_MASK__CI__VI 0xfffc0000L -#define GDS_ENHANCE__UNUSED_MASK__SI 0xffff0000L -#define GDS_GRBM_SECDED_CNT__DED_MASK__CI 0x0000ffffL -#define GDS_GRBM_SECDED_CNT__DED_MASK__SI 0xffff0000L -#define GDS_GRBM_SECDED_CNT__SEC_MASK__CI 0xffff0000L -#define GDS_GRBM_SECDED_CNT__SEC_MASK__SI 0x0000ffffL -#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK__CI__VI 0x00000001L -#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK__CI__VI 0x00000400L -#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK__CI__VI 0x00000800L -#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK__CI__VI 0x00001000L -#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK__CI__VI 0x00002000L -#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK__CI__VI 0x00004000L -#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK__CI__VI 0x00008000L -#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK__CI__VI 0x00010000L -#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK__CI__VI 0x00020000L -#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK__CI__VI 0x00040000L -#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK__CI__VI 0x00080000L -#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK__CI__VI 0x00000002L -#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK__CI__VI 0x00100000L -#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK__CI__VI 0x00200000L -#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK__CI__VI 0x00400000L -#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK__CI__VI 0x00800000L -#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK__CI__VI 0x01000000L -#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK__CI__VI 0x02000000L -#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK__CI__VI 0x04000000L -#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK__CI__VI 0x08000000L -#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK__CI__VI 0x10000000L -#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK__CI__VI 0x20000000L -#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK__CI__VI 0x00000004L -#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK__CI__VI 0x40000000L -#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK__CI__VI 0x80000000L -#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK__CI__VI 0x00000008L -#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK__CI__VI 0x00000010L -#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK__CI__VI 0x00000020L -#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK__CI__VI 0x00000040L -#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK__CI__VI 0x00000080L -#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK__CI__VI 0x00000100L -#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK__CI__VI 0x00000200L -#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK__CI__VI 0x00000001L -#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK__CI__VI 0x00000002L -#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK__CI__VI 0x00000004L -#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK__CI__VI 0x00000008L -#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK__CI__VI 0x00000010L -#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK__CI__VI 0x00000020L -#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK__CI__VI 0x00000040L -#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK__CI__VI 0x00000080L -#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK__CI__VI 0x00000100L -#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK__CI__VI 0x00000200L -#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK__CI__VI 0x00000400L -#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK__CI__VI 0x00000800L -#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK__CI__VI 0x00001000L -#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK__CI__VI 0x00002000L -#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK__CI__VI 0x00004000L -#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK__CI__VI 0x00008000L -#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK__CI__VI 0x00010000L -#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK__CI__VI 0x00020000L -#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK__CI__VI 0x00040000L -#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK__CI__VI 0x00080000L -#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK__CI__VI 0x00100000L -#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK__CI__VI 0x00200000L -#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK__CI__VI 0x00400000L -#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK__CI__VI 0x00800000L -#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK__CI__VI 0x01000000L -#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK__CI__VI 0x02000000L -#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK__CI__VI 0x04000000L -#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK__CI__VI 0x08000000L -#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK__CI__VI 0x10000000L -#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK__CI__VI 0x20000000L -#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK__CI__VI 0x40000000L -#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK__CI__VI 0x80000000L -#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003fL -#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0L -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK__CI__VI 0x0000ffffL -#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_GWS_RESOURCE_RESET__RESET_MASK__CI__VI 0x00000001L -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK__CI__VI 0x0000ff00L -#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001ffeL -#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L -#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L -#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK__CI__VI 0x00008000L -#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L -#define GDS_GWS_RESOURCE__UNUSED_MASK__SI 0x00008000L -#define GDS_GWS_VMID0__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID0__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID10__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID10__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID11__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID11__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID12__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID12__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID13__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID13__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID14__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID14__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID15__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID15__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID1__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID1__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID2__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID2__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID3__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID3__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID4__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID4__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID5__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID5__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID6__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID6__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID7__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID7__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID8__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID8__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_GWS_VMID9__BASE_MASK__CI__VI 0x0000003fL -#define GDS_GWS_VMID9__SIZE_MASK__CI__VI 0x007f0000L -#define GDS_OA_ADDRESS__CRAWLER_MASK__CI 0x00f00000L -#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK__CI 0x000f0000L -#define GDS_OA_ADDRESS__DS_ADDRESS_MASK__CI__VI 0x0000ffffL -#define GDS_OA_ADDRESS__ENABLE_MASK__CI__VI 0x80000000L -#define GDS_OA_ADDRESS__NO_ALLOC_MASK__CI__VI 0x40000000L -#define GDS_OA_ADDRESS__UNUSED_MASK__CI 0x3f000000L -#define GDS_OA_CGPG_RESTORE__MEID_MASK__CI__VI 0x00000f00L -#define GDS_OA_CGPG_RESTORE__PIPEID_MASK__CI__VI 0x0000f000L -#define GDS_OA_CGPG_RESTORE__UNUSED_MASK__CI 0xffff0000L -#define GDS_OA_CGPG_RESTORE__VMID_MASK__CI__VI 0x000000ffL -#define GDS_OA_CNTL__INDEX_MASK__CI__VI 0x0000000fL -#define GDS_OA_CNTL__UNUSED_MASK__CI__VI 0xfffffff0L -#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK__CI__VI 0xffffffffL -#define GDS_OA_DED__ME0_CS_DED_MASK__CI 0x00000004L -#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK__CI 0x00000001L -#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK__CI 0x00000002L -#define GDS_OA_DED__ME1_PIPE0_DED_MASK__CI 0x00000010L -#define GDS_OA_DED__ME1_PIPE1_DED_MASK__CI 0x00000020L -#define GDS_OA_DED__ME1_PIPE2_DED_MASK__CI 0x00000040L -#define GDS_OA_DED__ME1_PIPE3_DED_MASK__CI 0x00000080L -#define GDS_OA_DED__ME2_PIPE0_DED_MASK__CI 0x00000100L -#define GDS_OA_DED__ME2_PIPE1_DED_MASK__CI 0x00000200L -#define GDS_OA_DED__ME2_PIPE2_DED_MASK__CI 0x00000400L -#define GDS_OA_DED__ME2_PIPE3_DED_MASK__CI 0x00000800L -#define GDS_OA_DED__PIPE0_DED_MASK__SI 0x00000001L -#define GDS_OA_DED__PIPE1_DED_MASK__SI 0x00000002L -#define GDS_OA_DED__PIPE2_DED_MASK__SI 0x00000004L -#define GDS_OA_DED__PIPE3_DED_MASK__SI 0x00000008L -#define GDS_OA_DED__UNUSED0_MASK__CI 0x00000008L -#define GDS_OA_DED__UNUSED1_MASK__CI 0xfffff000L -#define GDS_OA_DED__UNUSED_MASK__SI 0xfffffff0L -#define GDS_OA_INCDEC__INCDEC_MASK__CI__VI 0x80000000L -#define GDS_OA_INCDEC__VALUE_MASK__CI__VI 0x7fffffffL -#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK__CI__VI 0x00000004L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK__CI__VI 0x00000001L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK__CI__VI 0x00000002L -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK__CI__VI 0x00000010L -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK__CI__VI 0x00000020L -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK__CI__VI 0x00000040L -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK__CI__VI 0x00000080L -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK__CI__VI 0x00000100L -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK__CI__VI 0x00000200L -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK__CI__VI 0x00000400L -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK__CI__VI 0x00000800L -#define GDS_OA_RESET_MASK__UNUSED0_MASK__CI__VI 0x00000008L -#define GDS_OA_RESET_MASK__UNUSED1_MASK__CI__VI 0xfffff000L -#define GDS_OA_RESET__PIPE_ID_MASK__CI__VI 0x0000ff00L -#define GDS_OA_RESET__RESET_MASK__CI__VI 0x00000001L -#define GDS_OA_RING_SIZE__RING_SIZE_MASK__CI__VI 0xffffffffL -#define GDS_OA_VMID0__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID0__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID10__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID10__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID11__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID11__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID12__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID12__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID13__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID13__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID14__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID14__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID15__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID15__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID1__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID1__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID2__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID2__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID3__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID3__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID4__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID4__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID5__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID5__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID6__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID6__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID7__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID7__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID8__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID8__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_OA_VMID9__MASK_MASK__CI__VI 0x0000ffffL -#define GDS_OA_VMID9__UNUSED_MASK__CI__VI 0xffff0000L -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK__CI__VI 0x000003ffL -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK__CI__VI 0x000ffc00L -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define GDS_PROTECTION_FAULT__ADDRESS_MASK__CI__VI 0xffff0000L -#define GDS_PROTECTION_FAULT__CU_ID_MASK__CI__VI 0x000003c0L -#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK__CI__VI 0x00000002L -#define GDS_PROTECTION_FAULT__GRBM_MASK__CI__VI 0x00000004L -#define GDS_PROTECTION_FAULT__SH_ID_MASK__CI__VI 0x00000038L -#define GDS_PROTECTION_FAULT__SIMD_ID_MASK__CI__VI 0x00000c00L -#define GDS_PROTECTION_FAULT__WAVE_ID_MASK__CI__VI 0x0000f000L -#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK__CI__VI 0x00000001L -#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffffL -#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffffL -#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffffL -#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffffL -#define GDS_RD_DATA__READ_DATA_MASK 0xffffffffL -#define GDS_SECDED_CNT__DED_MASK__CI 0x0000ffffL -#define GDS_SECDED_CNT__DED_MASK__SI 0xffff0000L -#define GDS_SECDED_CNT__SEC_MASK__CI 0xffff0000L -#define GDS_SECDED_CNT__SEC_MASK__SI 0x0000ffffL -#define GDS_VMID0_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID0_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID10_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID10_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID11_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID11_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID12_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID12_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID13_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID13_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID14_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID14_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID15_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID15_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID1_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID1_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID2_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID2_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID3_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID3_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID4_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID4_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID5_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID5_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID6_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID6_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID7_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID7_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID8_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID8_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VMID9_BASE__BASE_MASK__CI__VI 0x0000ffffL -#define GDS_VMID9_SIZE__SIZE_MASK__CI__VI 0x0001ffffL -#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK__CI__VI 0xffff0000L -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK__CI__VI 0x00000002L -#define GDS_VM_PROTECTION_FAULT__GRBM_MASK__CI__VI 0x00000010L -#define GDS_VM_PROTECTION_FAULT__GWS_MASK__CI__VI 0x00000004L -#define GDS_VM_PROTECTION_FAULT__OA_MASK__CI__VI 0x00000008L -#define GDS_VM_PROTECTION_FAULT__VMID_MASK__CI__VI 0x00000f00L -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK__CI__VI 0x00000001L -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffffL -#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffffL -#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffffL -#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffffL -#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffffL -#define GENENB__BLK_IO_BASE_MASK__SI 0x000000ffL -#define GENERAL_PWRMGT__ACPI_D3_VID_MASK__CI__VI 0x00180000L -#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x00800000L -#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x00000001L -#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK__CI__VI 0x00004000L -#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK__CI__VI 0x00008000L -#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK__CI__VI 0x00020000L -#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK__CI__VI 0x00010000L -#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK__CI__VI 0x00000100L -#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK__CI__VI 0x00000200L -#define GENERAL_PWRMGT__MC_ALLOW_STOP_MASK__SI 0xc0000000L -#define GENERAL_PWRMGT__SPARE11_MASK 0x00000800L -#define GENERAL_PWRMGT__SPARE18_MASK 0x00040000L -#define GENERAL_PWRMGT__SPARE19_MASK__SI 0x00080000L -#define GENERAL_PWRMGT__SPARE20_MASK__SI 0x00100000L -#define GENERAL_PWRMGT__SPARE27_MASK__CI__VI 0x08000000L -#define GENERAL_PWRMGT__SPARE_MASK__CI__VI 0xf0000000L -#define GENERAL_PWRMGT__SPARE_MASK__SI 0x08000000L -#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x00000002L -#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x00000040L -#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x00000004L -#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x00000008L -#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x00000400L -#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK__SI 0x80000000L -#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK__SI 0x00000001L -#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK__SI 0x00000004L -#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK__SI 0x00000002L -#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK__SI 0x0000ff00L -#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK__SI 0x00000001L -#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK__SI 0x000f0000L -#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK__SI 0x80000000L -#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK__SI 0x00000002L -#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK__SI 0x00000001L -#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK__SI 0x00000004L -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK__SI 0x00000004L -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK__SI 0x00000002L -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK__SI 0x00000001L -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK__SI 0x00000040L -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK__SI 0x00000020L -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK__SI 0x00000010L -#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK__SI 0x0000007fL -#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK__SI 0x00007f00L -#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK__SI 0x00000080L -#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK__SI 0x00000001L -#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK__SI 0x00000002L -#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK__SI 0xff000000L -#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK__SI 0x00000010L -#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK__SI 0xffff0000L -#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK__SI 0x00000003L -#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK__SI 0x00000020L -#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK__SI 0x00000010L -#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK__SI 0x00000400L -#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK__SI 0x0000000fL -#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK__SI 0x00000200L -#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK__SI 0x00000040L -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK__SI 0x00000200L -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK__SI 0x000f0000L -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK__SI 0x00000001L -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK__SI 0x00001000L -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK__SI 0x00002000L -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK__SI 0x00000100L -#define GENFC_RD__VSYNC_SEL_R_MASK__SI 0x00000008L -#define GENFC_WT__VSYNC_SEL_W_MASK__SI 0x00000008L -#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK__SI 0x00000001L -#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK__SI 0x00000020L -#define GENMO_RD__VGA_CKSEL_MASK__SI 0x0000000cL -#define GENMO_RD__VGA_HSYNC_POL_MASK__SI 0x00000040L -#define GENMO_RD__VGA_RAM_EN_MASK__SI 0x00000002L -#define GENMO_RD__VGA_VSYNC_POL_MASK__SI 0x00000080L -#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK__SI 0x00000001L -#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK__SI 0x00000020L -#define GENMO_WT__VGA_CKSEL_MASK__SI 0x0000000cL -#define GENMO_WT__VGA_HSYNC_POL_MASK__SI 0x00000040L -#define GENMO_WT__VGA_RAM_EN_MASK__SI 0x00000002L -#define GENMO_WT__VGA_VSYNC_POL_MASK__SI 0x00000080L -#define GENS0__CRT_INTR_MASK__SI 0x00000080L -#define GENS0__SENSE_SWITCH_MASK__SI 0x00000010L -#define GENS1__NO_DISPLAY_MASK__SI 0x00000001L -#define GENS1__PIXEL_READ_BACK_MASK__SI 0x00000030L -#define GENS1__VGA_VSTATUS_MASK__SI 0x00000008L -#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK__CI__VI 0x00010000L -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK__CI__VI 0x00001fffL -#define GFX_PIPE_CONTROL__RESERVED_MASK__CI__VI 0x0000e000L -#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK__CI 0x00000001L -#define GFX_RLC_CONTROL__RLC_REQ_ACK_MASK__SI 0x000000f0L -#define GFX_RLC_CONTROL__RLC_REQ_TYPE_MASK__SI 0x0000000fL -#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK__SI 0x000000f8L -#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK__SI 0x00000f00L -#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK__SI 0x0000f000L -#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK__SI 0x00000002L -#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK__SI 0x00000001L -#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK__SI 0x00000100L -#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK__SI 0x00000001L -#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK__SI 0x00000002L -#define GLOBAL_STATUS__FLUSH_STATUS_MASK__SI 0x00000002L -#define GMCON_DEBUG__GFX_CLEAR_MASK__CI__VI 0x00000002L -#define GMCON_DEBUG__GFX_STALL_MASK__CI__VI 0x00000001L -#define GMCON_DEBUG__MISC_FLAGS_MASK__CI 0x3ffffffcL -#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK__CI__VI 0x00000001L -#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK__CI__VI 0x00000002L -#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK__CI__VI 0x00000004L -#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK__CI__VI 0x00000008L -#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK__CI 0x000003f0L -#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK__CI 0x00000007L -#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK__CI 0x00000038L -#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK__CI__VI 0x0001f800L -#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK__CI__VI 0x40000000L -#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK__CI__VI 0x20000000L -#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK__CI 0x1ffe0000L -#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK__CI__VI 0x000007c0L -#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK__CI__VI 0x80000000L -#define GMCON_MISC3__RENG_DISABLE_MCC_MASK__CI 0x0000003fL -#define GMCON_MISC3__RENG_DISABLE_MCD_MASK__CI 0x00000fc0L -#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK__CI 0x02000000L -#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK__CI 0x04000000L -#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK__CI 0x00fff000L -#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK__CI 0x01000000L -#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK__CI__VI 0x70000000L -#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK__CI__VI 0x08000000L -#define GMCON_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK__CI__VI 0x000003ffL -#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK__CI__VI 0x00000400L -#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK__CI__VI 0x00000800L -#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK__CI__VI 0x0000f000L -#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK__CI__VI 0x02000000L -#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK__CI__VI 0x04000000L -#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK__CI__VI 0x80000000L -#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK__CI__VI 0x00060000L -#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK__CI__VI 0x00400000L -#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK__CI__VI 0x00200000L -#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK__CI__VI 0x01000000L -#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK__CI__VI 0x00800000L -#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK__CI__VI 0x00180000L -#define GMCON_MISC__STCTRL_STUTTER_EN_MASK__CI__VI 0x00010000L -#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK__CI__VI 0x10000000L -#define GMCON_PERF_MON_CNTL0__START_MODE_MASK__CI__VI 0x03000000L -#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK__CI__VI 0x00000fffL -#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK__CI__VI 0x0c000000L -#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK__CI__VI 0x00fff000L -#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK__CI 0x00fc0000L -#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK__CI 0x3f000000L -#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK__CI__VI 0x00000fc0L -#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK__CI__VI 0x0003f000L -#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK__CI__VI 0x0000003fL -#define GMCON_PERF_MON_RSLT0__COUNT_MASK__CI__VI 0xffffffffL -#define GMCON_PERF_MON_RSLT1__COUNT_MASK__CI__VI 0xffffffffL -#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK__CI__VI 0x000000ffL -#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK__CI__VI 0x00000400L -#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK__CI__VI 0x00000800L -#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK__CI__VI 0x00000100L -#define GMCON_PGFSM_CONFIG__POWER_UP_MASK__CI__VI 0x00000200L -#define GMCON_PGFSM_CONFIG__READ_MASK__CI__VI 0x00002000L -#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK__CI__VI 0xf0000000L -#define GMCON_PGFSM_CONFIG__RSRVD_MASK__CI__VI 0x07ffc000L -#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK__CI__VI 0x08000000L -#define GMCON_PGFSM_CONFIG__WRITE_MASK__CI__VI 0x00001000L -#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK__CI__VI 0x0f000000L -#define GMCON_PGFSM_READ__READ_VALUE_MASK__CI__VI 0x00ffffffL -#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK__CI__VI 0x10000000L -#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK__CI__VI 0xffffffffL -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK__CI__VI 0x003ff000L -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK__CI__VI 0xffc00000L -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK__CI__VI 0x00000002L -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK__CI__VI 0x00000ffcL -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK__CI__VI 0x00000001L -#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK__CI__VI 0xffffffffL -#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK__CI__VI 0x000003ffL -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK__CI__VI 0x0000ffffL -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK__CI__VI 0xffff0000L -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK__CI__VI 0x0000ffffL -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK__CI__VI 0xffff0000L -#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK__CI__VI 0x0000ffffL -#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK__CI__VI 0xffff0000L -#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK__CI__VI 0x0000ffffL -#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK__CI__VI 0xffff0000L -#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK__CI__VI 0x0000ffffL -#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK__CI__VI 0xffff0000L -#define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL -#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL -#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L -#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x00000040L -#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x0000001fL -#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL -#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L -#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL -#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L -#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L -#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL -#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L -#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL -#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L -#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL -#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L -#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL -#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L -#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL -#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffffL -#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0x0000000fL -#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0x000000f0L -#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L -#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_0_MASK__CI__VI 0x00000001L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_1_MASK__CI__VI 0x00000002L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_2_MASK__CI__VI 0x00000004L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_3_MASK__CI__VI 0x00000008L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_4_MASK__CI__VI 0x00000010L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_5_MASK__CI__VI 0x00000020L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_6_MASK__CI__VI 0x00000040L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_7_MASK__CI__VI 0x00000080L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_8_MASK__CI__VI 0x00000100L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_9_MASK__CI__VI 0x00000200L -#define GPU_GARLIC_FLUSH_DONE__CP0_MASK__CI__VI 0x00000001L -#define GPU_GARLIC_FLUSH_DONE__CP1_MASK__CI__VI 0x00000002L -#define GPU_GARLIC_FLUSH_DONE__CP2_MASK__CI__VI 0x00000004L -#define GPU_GARLIC_FLUSH_DONE__CP3_MASK__CI__VI 0x00000008L -#define GPU_GARLIC_FLUSH_DONE__CP4_MASK__CI__VI 0x00000010L -#define GPU_GARLIC_FLUSH_DONE__CP5_MASK__CI__VI 0x00000020L -#define GPU_GARLIC_FLUSH_DONE__CP6_MASK__CI__VI 0x00000040L -#define GPU_GARLIC_FLUSH_DONE__CP7_MASK__CI__VI 0x00000080L -#define GPU_GARLIC_FLUSH_DONE__CP8_MASK__CI__VI 0x00000100L -#define GPU_GARLIC_FLUSH_DONE__CP9_MASK__CI__VI 0x00000200L -#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK__CI__VI 0x00000400L -#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK__CI__VI 0x00000800L -#define GPU_GARLIC_FLUSH_REQ__CP0_MASK__CI__VI 0x00000001L -#define GPU_GARLIC_FLUSH_REQ__CP1_MASK__CI__VI 0x00000002L -#define GPU_GARLIC_FLUSH_REQ__CP2_MASK__CI__VI 0x00000004L -#define GPU_GARLIC_FLUSH_REQ__CP3_MASK__CI__VI 0x00000008L -#define GPU_GARLIC_FLUSH_REQ__CP4_MASK__CI__VI 0x00000010L -#define GPU_GARLIC_FLUSH_REQ__CP5_MASK__CI__VI 0x00000020L -#define GPU_GARLIC_FLUSH_REQ__CP6_MASK__CI__VI 0x00000040L -#define GPU_GARLIC_FLUSH_REQ__CP7_MASK__CI__VI 0x00000080L -#define GPU_GARLIC_FLUSH_REQ__CP8_MASK__CI__VI 0x00000100L -#define GPU_GARLIC_FLUSH_REQ__CP9_MASK__CI__VI 0x00000200L -#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK__CI__VI 0x00000400L -#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK__CI__VI 0x00000800L -#define GPU_HDP_FLUSH_DONE__CP0_MASK__CI__VI 0x00000001L -#define GPU_HDP_FLUSH_DONE__CP1_MASK__CI__VI 0x00000002L -#define GPU_HDP_FLUSH_DONE__CP2_MASK__CI__VI 0x00000004L -#define GPU_HDP_FLUSH_DONE__CP3_MASK__CI__VI 0x00000008L -#define GPU_HDP_FLUSH_DONE__CP4_MASK__CI__VI 0x00000010L -#define GPU_HDP_FLUSH_DONE__CP5_MASK__CI__VI 0x00000020L -#define GPU_HDP_FLUSH_DONE__CP6_MASK__CI__VI 0x00000040L -#define GPU_HDP_FLUSH_DONE__CP7_MASK__CI__VI 0x00000080L -#define GPU_HDP_FLUSH_DONE__CP8_MASK__CI__VI 0x00000100L -#define GPU_HDP_FLUSH_DONE__CP9_MASK__CI__VI 0x00000200L -#define GPU_HDP_FLUSH_DONE__SDMA0_MASK__CI__VI 0x00000400L -#define GPU_HDP_FLUSH_DONE__SDMA1_MASK__CI__VI 0x00000800L -#define GPU_HDP_FLUSH_REQ__CP0_MASK__CI__VI 0x00000001L -#define GPU_HDP_FLUSH_REQ__CP1_MASK__CI__VI 0x00000002L -#define GPU_HDP_FLUSH_REQ__CP2_MASK__CI__VI 0x00000004L -#define GPU_HDP_FLUSH_REQ__CP3_MASK__CI__VI 0x00000008L -#define GPU_HDP_FLUSH_REQ__CP4_MASK__CI__VI 0x00000010L -#define GPU_HDP_FLUSH_REQ__CP5_MASK__CI__VI 0x00000020L -#define GPU_HDP_FLUSH_REQ__CP6_MASK__CI__VI 0x00000040L -#define GPU_HDP_FLUSH_REQ__CP7_MASK__CI__VI 0x00000080L -#define GPU_HDP_FLUSH_REQ__CP8_MASK__CI__VI 0x00000100L -#define GPU_HDP_FLUSH_REQ__CP9_MASK__CI__VI 0x00000200L -#define GPU_HDP_FLUSH_REQ__SDMA0_MASK__CI__VI 0x00000400L -#define GPU_HDP_FLUSH_REQ__SDMA1_MASK__CI__VI 0x00000800L -#define GRA00__GRPH_SET_RESET0_MASK__SI 0x00000001L -#define GRA00__GRPH_SET_RESET1_MASK__SI 0x00000002L -#define GRA00__GRPH_SET_RESET2_MASK__SI 0x00000004L -#define GRA00__GRPH_SET_RESET3_MASK__SI 0x00000008L -#define GRA01__GRPH_SET_RESET_ENA0_MASK__SI 0x00000001L -#define GRA01__GRPH_SET_RESET_ENA1_MASK__SI 0x00000002L -#define GRA01__GRPH_SET_RESET_ENA2_MASK__SI 0x00000004L -#define GRA01__GRPH_SET_RESET_ENA3_MASK__SI 0x00000008L -#define GRA02__GRPH_CCOMP_MASK__SI 0x0000000fL -#define GRA03__GRPH_FN_SEL_MASK__SI 0x00000018L -#define GRA03__GRPH_ROTATE_MASK__SI 0x00000007L -#define GRA04__GRPH_RMAP_MASK__SI 0x00000003L -#define GRA05__CGA_ODDEVEN_MASK__SI 0x00000010L -#define GRA05__GRPH_OES_MASK__SI 0x00000020L -#define GRA05__GRPH_PACK_MASK__SI 0x00000040L -#define GRA05__GRPH_READ1_MASK__SI 0x00000008L -#define GRA05__GRPH_WRITE_MODE_MASK__SI 0x00000003L -#define GRA06__GRPH_ADRSEL_MASK__SI 0x0000000cL -#define GRA06__GRPH_GRAPHICS_MASK__SI 0x00000001L -#define GRA06__GRPH_ODDEVEN_MASK__SI 0x00000002L -#define GRA07__GRPH_XCARE0_MASK__SI 0x00000001L -#define GRA07__GRPH_XCARE1_MASK__SI 0x00000002L -#define GRA07__GRPH_XCARE2_MASK__SI 0x00000004L -#define GRA07__GRPH_XCARE3_MASK__SI 0x00000008L -#define GRA08__GRPH_BMSK_MASK__SI 0x000000ffL -#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL -#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L -#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L -#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL -#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x0000003fL -#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffffL -#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK__CI__VI 0x00000001L -#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK__CI__VI 0x00000002L -#define GRBM_DEBUG_SNAPSHOT__CP_RDY_MASK__SI 0x00000008L -#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK__CI__VI 0x00000020L -#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK__SI 0x00000200L -#define GRBM_DEBUG_SNAPSHOT__IA_RING0_RDY_MASK__SI 0x00000040L -#define GRBM_DEBUG_SNAPSHOT__IA_RING1_RDY_MASK__SI 0x00000080L -#define GRBM_DEBUG_SNAPSHOT__IA_RING2_RDY_MASK__SI 0x00000100L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK__CI__VI 0x00000040L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK__CI__VI 0x00004000L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK__CI__VI 0x00000080L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK__CI__VI 0x00008000L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING0_RDY0_MASK__SI 0x00000400L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING0_RDY1_MASK__SI 0x00001000L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING1_RDY1_MASK__SI 0x00002000L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING2_RDY1_MASK__SI 0x00004000L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK__CI__VI 0x00000100L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK__CI__VI 0x00010000L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK__CI__VI 0x00000200L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK__CI__VI 0x00020000L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING0_RDY0_MASK__SI 0x00000800L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING0_RDY1_MASK__SI 0x00008000L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING1_RDY1_MASK__SI 0x00010000L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING2_RDY1_MASK__SI 0x00020000L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK__CI__VI 0x00000400L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK__CI__VI 0x00040000L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK__CI__VI 0x00000800L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK__CI__VI 0x00080000L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK__CI__VI 0x00001000L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK__CI__VI 0x00100000L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK__CI__VI 0x00002000L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK__CI__VI 0x00200000L -#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK__CI__VI 0x00000004L -#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK__SI 0x00000002L -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK__CI__VI 0x00000008L -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK__CI__VI 0x00000010L -#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000040L -#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x00001000L -#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0x00000f00L -#define GRBM_DEBUG__IGNORE_FAO_MASK 0x00000020L -#define GRBM_DEBUG__IGNORE_RDY_MASK 0x00000002L -#define GRBM_DEBUG__OVERRIDE_WU_MASK__SI 0x00000001L -#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000080L -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L -#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000ffL -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L -#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00ff0000L -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L -#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000ff00L -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L -#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L -#define GRBM_NOWHERE__DATA_MASK 0xffffffffL -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x10000000L -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x10000000L -#define GRBM_PWR_CNTL__REQ_TYPE_MASK__SI__CI 0x0000000fL -#define GRBM_PWR_CNTL__RSP_TYPE_MASK__SI__CI 0x000000f0L -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK__CI__VI 0x00080000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK__CI__VI 0x00100000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK__CI__VI 0x00200000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK__CI__VI 0x00400000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK__CI__VI 0x00800000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK__CI__VI 0x01000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK__CI__VI 0x02000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK__CI__VI 0x04000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK__CI__VI 0x08000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK__CI__VI 0x10000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK__CI__VI 0x20000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK__CI__VI 0x40000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK__CI__VI 0x80000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK__CI__VI 0x00040000L -#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK__CI__VI 0x00020000L -#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL -#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L -#define GRBM_READ_ERROR__READ_MEID_MASK__CI__VI 0x00c00000L -#define GRBM_READ_ERROR__READ_PIPEID_MASK__CI__VI 0x00300000L -#define GRBM_READ_ERROR__READ_REQUESTER_GDS_DMA_MASK__SI 0x00800000L -#define GRBM_READ_ERROR__READ_REQUESTER_RING0_CF_MASK__SI 0x04000000L -#define GRBM_READ_ERROR__READ_REQUESTER_RING0_PF_MASK__SI 0x08000000L -#define GRBM_READ_ERROR__READ_REQUESTER_RING1_MASK__SI 0x02000000L -#define GRBM_READ_ERROR__READ_REQUESTER_RING2_MASK__SI 0x01000000L -#define GRBM_READ_ERROR__READ_REQUESTER_RLC_MASK__SI 0x00400000L -#define GRBM_READ_ERROR__READ_REQUESTER_SRBM_MASK__SI 0x10000000L -#define GRBM_READ_ERROR__READ_REQUESTER_WU_POLL_MASK__SI 0x40000000L -#define GRBM_READ_ERROR__READ_RINGID_MASK__SI 0x00300000L -#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL -#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL -#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL -#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL -#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL -#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL -#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL -#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00200000L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00040000L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK__CI__VI 0x00000800L -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00020000L -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK__CI__VI 0x00000400L -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00100000L -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00010000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00008000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00002000L -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00001000L -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00080000L -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00200000L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00040000L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK__CI__VI 0x00000800L -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00020000L -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK__CI__VI 0x00000400L -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00100000L -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK__CI__VI 0x0000003fL -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00010000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00008000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00002000L -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00001000L -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK__CI__VI 0x00080000L -#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000fc0L -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003fL -#define GRBM_SOFT_RESET__SOFT_RESET_BCI_MASK__SI 0x00000080L -#define GRBM_SOFT_RESET__SOFT_RESET_CB_MASK__SI 0x00000002L -#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK__CI__VI 0x00040000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK__CI__VI 0x00020000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK__CI__VI 0x00080000L -#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L -#define GRBM_SOFT_RESET__SOFT_RESET_DB_MASK__SI 0x00000008L -#define GRBM_SOFT_RESET__SOFT_RESET_GDS_MASK__SI 0x00000010L -#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK__CI__VI 0x00010000L -#define GRBM_SOFT_RESET__SOFT_RESET_IA_MASK__SI 0x00008000L -#define GRBM_SOFT_RESET__SOFT_RESET_PA_MASK__SI 0x00000020L -#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L -#define GRBM_SOFT_RESET__SOFT_RESET_SC_MASK__SI 0x00000040L -#define GRBM_SOFT_RESET__SOFT_RESET_SPI_MASK__SI 0x00000100L -#define GRBM_SOFT_RESET__SOFT_RESET_SX_MASK__SI 0x00000400L -#define GRBM_SOFT_RESET__SOFT_RESET_TA_MASK__SI 0x00001000L -#define GRBM_SOFT_RESET__SOFT_RESET_TC_MASK__SI 0x00000800L -#define GRBM_SOFT_RESET__SOFT_RESET_VGT_MASK__SI 0x00004000L -#define GRBM_STATUS2__CPC_BUSY_MASK__CI__VI 0x20000000L -#define GRBM_STATUS2__CPF_BUSY_MASK__CI__VI 0x10000000L -#define GRBM_STATUS2__CPG_BUSY_MASK__CI__VI 0x40000000L -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK__CI__VI 0x00000010L -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK__CI__VI 0x0000000fL -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK__CI__VI 0x00000020L -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK__CI__VI 0x00000040L -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK__CI__VI 0x00000080L -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK__CI__VI 0x00000100L -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK__CI__VI 0x00000200L -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK__CI__VI 0x00000400L -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK__CI__VI 0x00000800L -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK__CI__VI 0x00001000L -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK__CI__VI 0x00002000L -#define GRBM_STATUS2__RLC_BUSY_MASK__CI__VI 0x01000000L -#define GRBM_STATUS2__RLC_BUSY_MASK__SI 0x00000100L -#define GRBM_STATUS2__RLC_RQ_PENDING_MASK__CI__VI 0x00004000L -#define GRBM_STATUS2__RLC_RQ_PENDING_MASK__SI 0x00000001L -#define GRBM_STATUS2__TC_BUSY_MASK__CI__VI 0x02000000L -#define GRBM_STATUS2__TC_BUSY_MASK__SI 0x00000200L -#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L -#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L -#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE2__BCI_BUSY_MASK__CI__VI 0x00400000L -#define GRBM_STATUS_SE2__CB_BUSY_MASK__CI__VI 0x80000000L -#define GRBM_STATUS_SE2__CB_CLEAN_MASK__CI__VI 0x00000004L -#define GRBM_STATUS_SE2__DB_BUSY_MASK__CI__VI 0x40000000L -#define GRBM_STATUS_SE2__DB_CLEAN_MASK__CI__VI 0x00000002L -#define GRBM_STATUS_SE2__PA_BUSY_MASK__CI__VI 0x01000000L -#define GRBM_STATUS_SE2__SC_BUSY_MASK__CI__VI 0x20000000L -#define GRBM_STATUS_SE2__SPI_BUSY_MASK__CI__VI 0x08000000L -#define GRBM_STATUS_SE2__SX_BUSY_MASK__CI__VI 0x04000000L -#define GRBM_STATUS_SE2__TA_BUSY_MASK__CI__VI 0x02000000L -#define GRBM_STATUS_SE2__VGT_BUSY_MASK__CI__VI 0x00800000L -#define GRBM_STATUS_SE3__BCI_BUSY_MASK__CI__VI 0x00400000L -#define GRBM_STATUS_SE3__CB_BUSY_MASK__CI__VI 0x80000000L -#define GRBM_STATUS_SE3__CB_CLEAN_MASK__CI__VI 0x00000004L -#define GRBM_STATUS_SE3__DB_BUSY_MASK__CI__VI 0x40000000L -#define GRBM_STATUS_SE3__DB_CLEAN_MASK__CI__VI 0x00000002L -#define GRBM_STATUS_SE3__PA_BUSY_MASK__CI__VI 0x01000000L -#define GRBM_STATUS_SE3__SC_BUSY_MASK__CI__VI 0x20000000L -#define GRBM_STATUS_SE3__SPI_BUSY_MASK__CI__VI 0x08000000L -#define GRBM_STATUS_SE3__SX_BUSY_MASK__CI__VI 0x04000000L -#define GRBM_STATUS_SE3__TA_BUSY_MASK__CI__VI 0x02000000L -#define GRBM_STATUS_SE3__VGT_BUSY_MASK__CI__VI 0x00800000L -#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L -#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L -#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L -#define GRBM_STATUS__CF_RQ_PENDING_MASK__SI 0x00000080L -#define GRBM_STATUS__CMDFIFO_AVAIL_MASK__SI 0x0000000fL -#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L -#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L -#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L -#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L -#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L -#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L -#define GRBM_STATUS__GRBM_EE_BUSY_MASK__SI 0x00000400L -#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L -#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L -#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK__CI__VI 0x00000080L -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK__CI__VI 0x0000000fL -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK__CI__VI 0x00000100L -#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L -#define GRBM_STATUS__PF_RQ_PENDING_MASK__SI 0x00000100L -#define GRBM_STATUS__RING1_RQ_PENDING_MASK__SI 0x00000040L -#define GRBM_STATUS__RING2_RQ_PENDING_MASK__SI 0x00000010L -#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L -#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L -#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x00000020L -#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L -#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L -#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L -#define GRBM_STATUS__WD_BUSY_MASK__CI__VI 0x00200000L -#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK__CI__VI 0x00010000L -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000ffL -#define GRPH8_DATA__GRPH_DATA_MASK__SI 0x000000ffL -#define GRPH8_IDX__GRPH_IDX_MASK__SI 0x0000000fL -#define GRPH_ALPHA__GRPH_ALPHA_MASK__SI 0x000000ffL -#define GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__GRPH_COLOR_MATRIX_TRANSFORMATION_EN_MASK__SI \ - 0x00000001L -#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK__SI 0x0001ffc0L -#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK__SI 0x000000ffL -#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK__SI 0xffffff00L -#define GRPH_CONTROL__GRPH_16BIT_ALPHA_MODE_MASK__SI 0x03000000L -#define GRPH_CONTROL__GRPH_16BIT_FIXED_ALPHA_RANGE_MASK__SI 0x70000000L -#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK__SI 0x00010000L -#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK__SI 0x00f00000L -#define GRPH_CONTROL__GRPH_DEPTH_MASK__SI 0x00000003L -#define GRPH_CONTROL__GRPH_FORMAT_MASK__SI 0x00000700L -#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK__SI 0x00020000L -#define GRPH_CONTROL__GRPH_TILE_COMPACT_EN_MASK__SI 0x00001000L -#define GRPH_CONTROL__GRPH_Z_MASK__SI 0x00000030L -#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK__SI 0x00000700L -#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK__SI 0x00000001L -#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK__SI 0x00000070L -#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK__SI 0x00000200L -#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK__SI 0x00000100L -#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK__SI 0x0000000fL -#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK__SI 0x000000f0L -#define GRPH_ENABLE__GRPH_ENABLE_MASK__SI 0x00000001L -#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK__SI 0x00000001L -#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK__SI 0x00000001L -#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK__SI 0x00000100L -#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK__SI 0x00000100L -#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK__SI 0x00000001L -#define GRPH_KEY_RANGE_ALPHA__GRPH_KEY_ALPHA_HIGH_MASK__SI 0xffff0000L -#define GRPH_KEY_RANGE_ALPHA__GRPH_KEY_ALPHA_LOW_MASK__SI 0x0000ffffL -#define GRPH_KEY_RANGE_BLUE__GRPH_KEY_BLUE_HIGH_MASK__SI 0xffff0000L -#define GRPH_KEY_RANGE_BLUE__GRPH_KEY_BLUE_LOW_MASK__SI 0x0000ffffL -#define GRPH_KEY_RANGE_GREEN__GRPH_KEY_GREEN_HIGH_MASK__SI 0xffff0000L -#define GRPH_KEY_RANGE_GREEN__GRPH_KEY_GREEN_LOW_MASK__SI 0x0000ffffL -#define GRPH_KEY_RANGE_RED__GRPH_KEY_RED_HIGH_MASK__SI 0xffff0000L -#define GRPH_KEY_RANGE_RED__GRPH_KEY_RED_LOW_MASK__SI 0x0000ffffL -#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK__SI 0x00010000L -#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK__SI 0x00000100L -#define GRPH_PITCH__GRPH_PITCH_MASK__SI 0x00003fffL -#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK__SI 0x000000ffL -#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK__SI 0x00000001L -#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK__SI 0xffffff00L -#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK__SI \ - 0x000000ffL -#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK__SI 0x00000001L -#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK__SI 0xffffff00L -#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK__SI 0x000000ffL -#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK__SI 0xffffff00L -#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK__SI 0x00001fffL -#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK__SI 0x00001fffL -#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK__SI 0x00000c00L -#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK__SI 0x00000300L -#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK__SI 0x00000003L -#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK__SI 0x000000c0L -#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK__SI 0x00000030L -#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK__SI 0x01000000L -#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK__SI 0x00000001L -#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK__SI 0x00000002L -#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK__SI 0x10000000L -#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK__SI 0x00000004L -#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK__SI 0x00000008L -#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK__SI 0x00010000L -#define GRPH_X_END__GRPH_X_END_MASK__SI 0x00003fffL -#define GRPH_X_START__GRPH_X_START_MASK__SI 0x00001fffL -#define GRPH_Y_END__GRPH_Y_END_MASK__SI 0x00003fffL -#define GRPH_Y_START__GRPH_Y_START_MASK__SI 0x00001fffL -#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL -#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL -#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL -#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL -#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL -#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL -#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL -#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL -#define HDCP_CONTROL__HDCP_ENABLE_MASK__SI 0x00000001L -#define HDCP_CONTROL__HDCP_ENCRYPTION_ENABLE_MASK__SI 0x00000100L -#define HDCP_CONTROL__HDCP_SHORT_OESS_ON_MASK__SI 0x00010000L -#define HDCP_DEBUG_CONTROL__HDCP_ADVANCE_CIPHER_ON_AVMUTE_MASK__SI 0x00040000L -#define HDCP_DEBUG_CONTROL__HDCP_BLANK_ALL_PACKETS_ON_ENC_ENB_MASK__SI 0x00000080L -#define HDCP_DEBUG_CONTROL__HDCP_DEBUG_RNG_CIPHER_MASK__SI 0x00000004L -#define HDCP_DEBUG_CONTROL__HDCP_DISABLE_RI_CHECK_IN_ADVANCE_CIPHER_ENC_DIS_MASK__SI 0x00000020L -#define HDCP_DEBUG_CONTROL__HDCP_EESS_WHEN_AVMUTE_MASK__SI 0x00080000L -#define HDCP_DEBUG_CONTROL__HDCP_EESS_WHEN_UNAUTHENTICATED_MASK__SI 0x00200000L -#define HDCP_DEBUG_CONTROL__HDCP_FRAMECOUNT_START_VAL_MASK__SI 0xff000000L -#define HDCP_DEBUG_CONTROL__HDCP_FRAMES_TO_PJ_CHECK_MASK__SI 0x00030000L -#define HDCP_DEBUG_CONTROL__HDCP_FRAMES_TO_RI_CHECK_MASK__SI 0x00003000L -#define HDCP_DEBUG_CONTROL__HDCP_FRAME_COUNT_SELECT_MASK__SI 0x00000002L -#define HDCP_DEBUG_CONTROL__HDCP_IGNORED_PJ_CHECK_TIMEOUT_MASK__SI 0x00800000L -#define HDCP_DEBUG_CONTROL__HDCP_IGNORED_RI_CHECK_TIMEOUT_MASK__SI 0x00400000L -#define HDCP_DEBUG_CONTROL__HDCP_IGNORE_HPD_DISCONNECT_MASK__SI 0x00000010L -#define HDCP_DEBUG_CONTROL__HDCP_MAX_PJ_MISMATCH_COUNT_MASK__SI 0x00000300L -#define HDCP_DEBUG_CONTROL__HDCP_MAX_PJ_MISMATCH_COUNT_RESET_MASK__SI 0x00000800L -#define HDCP_DEBUG_CONTROL__HDCP_NO_DEFERRED_ENC_DIS_MASK__SI 0x00004000L -#define HDCP_DEBUG_CONTROL__HDCP_RAISE_URG_2_FRAMES_EARLY_MASK__SI 0x00000040L -#define HDCP_DEBUG_CONTROL__HDCP_SW_I2C_XFER_REQ_TIMEOUT_DISABLE_MASK__SI 0x00100000L -#define HDCP_DEBUG_CONTROL__HDCP_SYNC_KEY_READ_MASK__SI 0x00000008L -#define HDCP_DEBUG_CONTROL__HDCP_USER_DEFINED_AN_MASK__SI 0x00000001L -#define HDCP_DEBUG__HDCP_DEBUG_MASK__SI 0x0000ffffL -#define HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK_MASK__SI 0x00000002L -#define HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_MASK__SI 0x00000001L -#define HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT_MASK__SI 0x00000700L -#define HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE_MASK__SI 0x00000001L -#define HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET_MASK__SI 0x00000004L -#define HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK_MASK__SI 0x00000001L -#define HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT_MASK__SI 0x00f00000L -#define HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY_MASK__SI 0xff000000L -#define HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE_MASK__SI 0x00000002L -#define HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE_MASK__SI 0x00000100L -#define HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ_MASK__SI 0xff000000L -#define HDCP_I2C_STATUS__HDCP_I2C_ABORTED_MASK__SI 0x00001000L -#define HDCP_I2C_STATUS__HDCP_I2C_FAILED_MASK__SI 0x00010000L -#define HDCP_I2C_STATUS__HDCP_I2C_NACK0_MASK__SI 0x00004000L -#define HDCP_I2C_STATUS__HDCP_I2C_NACK1_MASK__SI 0x00008000L -#define HDCP_I2C_STATUS__HDCP_I2C_RETRIES_MASK__SI 0x00f00000L -#define HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT_MASK__SI 0x00002000L -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE_MASK__SI 0x00000400L -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED_MASK__SI 0x00000004L -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_MASK__SI 0x00000010L -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_MASK__SI 0x000003c0L -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG_MASK__SI 0x00000020L -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK_MASK__SI 0x00000020L -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK_MASK__SI 0x00000080L -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT_MASK__SI 0x00000010L -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK_MASK__SI 0x00000040L -#define HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK_MASK__SI 0x00000002L -#define HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT_MASK__SI 0x00000001L -#define HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK_MASK__SI 0x00000004L -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK_MASK__SI 0x00002000L -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT_MASK__SI 0x00001000L -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK_MASK__SI 0x00004000L -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK_MASK__SI 0x00000200L -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT_MASK__SI 0x00000100L -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK_MASK__SI 0x00000400L -#define HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY_MASK__SI 0x00000100L -#define HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY_MASK__SI 0x00000200L -#define HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO_MASK__SI 0x000000f0L -#define HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_MASK__SI 0x00000004L -#define HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS_MASK__SI 0x00000001L -#define HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE_MASK__SI 0x70000000L -#define HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT_MASK__SI 0x00030000L -#define HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE_MASK__SI 0x01000000L -#define HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES_MASK__SI 0x00001000L -#define HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES_MASK__SI 0x00100000L -#define HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY_MASK__SI 0x00000100L -#define HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY_MASK__SI 0x00000200L -#define HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO_MASK__SI 0x000000f0L -#define HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_MASK__SI 0x00000004L -#define HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS_MASK__SI 0x00000001L -#define HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE_MASK__SI 0x70000000L -#define HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT_MASK__SI 0x00030000L -#define HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE_MASK__SI 0x01000000L -#define HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES_MASK__SI 0x00001000L -#define HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS_MASK__SI 0x000000ffL -#define HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS_MASK__SI 0x00ffff00L -#define HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1_MASK__SI 0x000000ffL -#define HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI_MASK__SI 0x0000ffffL -#define HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ_MASK__SI 0x000000ffL -#define HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO_MASK__SI 0x0000ff00L -#define HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1_MASK__SI 0x000000ffL -#define HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1_MASK__SI 0x000000ffL -#define HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO_MASK__SI 0x0000ffffL -#define HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI_MASK__SI 0x0000ffffL -#define HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ_MASK__SI 0x000000ffL -#define HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO_MASK__SI 0x0000ff00L -#define HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1_MASK__SI 0x000000ffL -#define HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1_MASK__SI 0xffffffffL -#define HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2_MASK__SI 0xffffffffL -#define HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE_MASK__SI 0x00000001L -#define HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE_MASK__SI 0x00000002L -#define HDCP_SHA_CONTROL__HDCP_DEBUG_EN_MASK__SI 0x80000000L -#define HDCP_SHA_CONTROL__HDCP_SHA_DBG_EN_MASK__SI 0x00000100L -#define HDCP_SHA_CONTROL__HDCP_SHA_DBG_NO_APPEND_BYTES_MASK__SI 0x00001000L -#define HDCP_SHA_CONTROL__HDCP_SHA_RESET_MASK__SI 0x00000001L -#define HDCP_SHA_CONTROL__HDCP_SHA_SELECT_MASK__SI 0x00000070L -#define HDCP_SHA_DATA__HDCP_SHA_DATA_DONE_MASK__SI 0x00000001L -#define HDCP_SHA_DATA__HDCP_SHA_DATA_MASK__SI 0x00ff0000L -#define HDCP_SHA_DBG_M0_0__HDCP_SHA_DBG_M0_0_MASK__SI 0xffffffffL -#define HDCP_SHA_DBG_M0_1__HDCP_SHA_DBG_M0_1_MASK__SI 0xffffffffL -#define HDCP_SHA_STATUS__HDCP_SHA_BLOCK_DONE_MASK__SI 0x00000001L -#define HDCP_SHA_STATUS__HDCP_SHA_BUSY_MASK__SI 0x00100000L -#define HDCP_SHA_STATUS__HDCP_SHA_COMP_DONE_MASK__SI 0x00000010L -#define HDCP_SHA_STATUS__HDCP_SHA_DBG_V_MATCHES_MASK__SI 0x01000000L -#define HDCP_SHA_STATUS__HDCP_SHA_M0_INVALID_MASK__SI 0x00010000L -#define HDCP_SHA_STATUS__HDCP_SHA_OVERFLOW_MASK__SI 0x00000100L -#define HDCP_SHA_STATUS__HDCP_SHA_WRITE_ERROR_MASK__SI 0x00001000L -#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK__SI 0xfffff000L -#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK__SI 0x000fffffL -#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK__SI 0xfffff000L -#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK__SI 0x000fffffL -#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK__SI 0xfffff000L -#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK__SI 0x000fffffL -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK__SI 0x80000000L -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK__SI 0x00001000L -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK__SI 0x00000002L -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK__SI 0x00070000L -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK__SI 0x00000030L -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK__SI 0x00000001L -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK__SI 0x00000100L -#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK__SI 0xfffff000L -#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK__SI 0x000fffffL -#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK__SI 0x00000030L -#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK__SI 0x001f0000L -#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK__SI 0x00000100L -#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK__SI 0x30000000L -#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK__SI 0x01000000L -#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK__SI 0x00000100L -#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK__SI 0x00000200L -#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK__SI 0x00000001L -#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK__SI 0x00000010L -#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK__SI 0x00000010L -#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK__SI 0x00000004L -#define HDMI_GC__HDMI_GC_AVMUTE_MASK__SI 0x00000001L -#define HDMI_GC__HDMI_PACKING_PHASE_MASK__SI 0x00000f00L -#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK__SI 0x00001000L -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC0_CONT_MASK__SI 0x00000002L -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC0_LINE_MASK__SI 0x003f0000L -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC0_SEND_MASK__SI 0x00000001L -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC1_CONT_MASK__SI 0x00000020L -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC1_LINE_MASK__SI 0x3f000000L -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC1_SEND_MASK__SI 0x00000010L -#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK__SI 0x00000020L -#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK__SI 0x00000010L -#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK__SI 0x00000002L -#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK__SI 0x00000001L -#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK__SI 0x00000200L -#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK__SI 0x00000100L -#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK__SI 0x00003f00L -#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK__SI 0x0000003fL -#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK__SI 0x003f0000L -#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK__SI 0x00000001L -#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK__SI 0x00010000L -#define HDMI_STATUS__HDMI_ERROR_INT_MASK__SI 0x08000000L -#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK__SI 0x00100000L -#define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK__SI 0x3f000000L -#define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK__SI 0x00001000L -#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK__SI 0x00000020L -#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK__SI 0x00000010L -#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK__SI 0x00000200L -#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK__SI 0x003f0000L -#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK__SI 0x00000100L -#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK__SI 0x00000001L -#define HDP_DEBUG0__HDP_DEBUG_MASK 0xffffffffL -#define HDP_DEBUG1__HDP_DEBUG_MASK 0xffffffffL -#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L -#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x00000007L -#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x00400000L -#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x00800000L -#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L -#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x000001f8L -#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L -#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0f000000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L -#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L -#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L -#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x0000003fL -#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L -#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0x0fffffffL -#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x00000060L -#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x00008000L -#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L -#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L -#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L -#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L -#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000ff00L -#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000ffL -#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L -#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x00000007L -#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x00000018L -#define HDP_SURFACE0_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE0_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE0_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE0_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE0_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE0_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE0_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE0_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE0_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE0_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE0_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE0_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE0_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE10_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE10_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE10_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE10_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE10_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE10_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE10_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE10_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE10_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE10_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE10_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE10_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE10_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE11_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE11_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE11_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE11_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE11_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE11_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE11_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE11_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE11_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE11_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE11_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE11_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE11_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE12_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE12_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE12_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE12_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE12_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE12_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE12_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE12_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE12_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE12_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE12_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE12_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE12_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE13_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE13_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE13_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE13_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE13_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE13_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE13_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE13_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE13_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE13_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE13_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE13_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE13_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE14_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE14_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE14_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE14_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE14_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE14_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE14_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE14_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE14_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE14_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE14_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE14_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE14_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE15_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE15_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE15_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE15_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE15_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE15_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE15_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE15_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE15_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE15_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE15_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE15_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE15_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE16_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE16_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE16_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE16_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE16_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE16_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE16_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE16_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE16_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE16_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE16_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE16_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE16_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE17_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE17_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE17_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE17_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE17_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE17_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE17_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE17_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE17_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE17_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE17_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE17_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE17_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE18_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE18_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE18_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE18_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE18_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE18_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE18_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE18_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE18_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE18_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE18_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE18_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE18_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE19_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE19_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE19_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE19_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE19_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE19_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE19_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE19_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE19_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE19_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE19_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE19_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE19_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE1_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE1_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE1_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE1_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE1_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE1_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE1_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE1_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE1_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE1_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE1_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE1_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE1_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE20_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE20_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE20_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE20_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE20_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE20_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE20_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE20_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE20_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE20_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE20_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE20_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE20_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE21_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE21_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE21_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE21_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE21_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE21_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE21_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE21_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE21_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE21_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE21_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE21_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE21_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE22_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE22_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE22_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE22_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE22_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE22_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE22_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE22_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE22_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE22_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE22_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE22_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE22_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE23_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE23_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE23_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE23_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE23_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE23_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE23_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE23_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE23_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE23_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE23_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE23_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE23_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE24_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE24_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE24_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE24_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE24_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE24_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE24_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE24_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE24_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE24_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE24_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE24_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE24_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE25_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE25_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE25_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE25_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE25_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE25_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE25_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE25_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE25_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE25_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE25_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE25_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE25_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE26_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE26_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE26_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE26_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE26_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE26_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE26_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE26_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE26_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE26_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE26_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE26_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE26_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE27_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE27_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE27_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE27_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE27_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE27_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE27_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE27_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE27_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE27_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE27_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE27_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE27_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE28_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE28_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE28_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE28_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE28_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE28_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE28_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE28_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE28_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE28_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE28_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE28_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE28_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE29_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE29_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE29_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE29_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE29_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE29_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE29_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE29_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE29_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE29_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE29_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE29_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE29_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE2_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE2_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE2_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE2_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE2_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE2_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE2_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE2_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE2_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE2_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE2_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE2_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE2_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE30_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE30_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE30_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE30_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE30_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE30_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE30_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE30_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE30_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE30_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE30_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE30_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE30_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE31_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE31_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE31_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE31_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE31_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE31_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE31_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE31_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE31_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE31_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE31_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE31_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE31_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE3_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE3_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE3_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE3_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE3_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE3_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE3_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE3_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE3_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE3_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE3_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE3_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE3_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE4_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE4_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE4_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE4_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE4_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE4_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE4_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE4_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE4_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE4_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE4_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE4_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE4_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE5_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE5_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE5_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE5_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE5_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE5_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE5_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE5_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE5_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE5_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE5_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE5_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE5_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE6_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE6_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE6_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE6_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE6_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE6_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE6_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE6_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE6_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE6_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE6_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE6_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE6_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE7_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE7_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE7_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE7_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE7_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE7_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE7_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE7_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE7_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE7_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE7_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE7_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE7_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE8_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE8_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE8_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE8_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE8_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE8_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE8_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE8_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE8_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE8_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE8_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE8_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE8_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE9_BASE__SURF_BASE_MASK 0x0fffffffL -#define HDP_SURFACE9_INFO__SURF_ADDR_TYPE_MASK 0x00000001L -#define HDP_SURFACE9_INFO__SURF_ARRAY_MODE_MASK 0x0000001eL -#define HDP_SURFACE9_INFO__SURF_ENDIAN_MASK 0x00000060L -#define HDP_SURFACE9_INFO__SURF_PIXEL_SIZE_MASK 0x00000380L -#define HDP_SURFACE9_INFO__SURF_PRIV_MASK 0x00008000L -#define HDP_SURFACE9_INFO__SURF_SAMPLE_NUM_MASK 0x00001c00L -#define HDP_SURFACE9_INFO__SURF_SAMPLE_SIZE_MASK 0x00006000L -#define HDP_SURFACE9_INFO__SURF_TILE_COMPACT_MASK 0x00010000L -#define HDP_SURFACE9_LOWER_BOUND__SURF_LOWER_MASK 0x00ffffffL -#define HDP_SURFACE9_SIZE__SURF_PITCH_TILE_MAX_MASK 0x000003ffL -#define HDP_SURFACE9_SIZE__SURF_SLICE_TILE_MAX_MASK 0x3ffffc00L -#define HDP_SURFACE9_UPPER_BOUND__SURF_UPPER_MASK 0x00ffffffL -#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF10_READ_FLAG_CLR_MASK 0x00000400L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF11_READ_FLAG_CLR_MASK 0x00000800L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF12_READ_FLAG_CLR_MASK 0x00001000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF13_READ_FLAG_CLR_MASK 0x00002000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF14_READ_FLAG_CLR_MASK 0x00004000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF15_READ_FLAG_CLR_MASK 0x00008000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF16_READ_FLAG_CLR_MASK 0x00010000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF17_READ_FLAG_CLR_MASK 0x00020000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF18_READ_FLAG_CLR_MASK 0x00040000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF19_READ_FLAG_CLR_MASK 0x00080000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF20_READ_FLAG_CLR_MASK 0x00100000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF21_READ_FLAG_CLR_MASK 0x00200000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF22_READ_FLAG_CLR_MASK 0x00400000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF23_READ_FLAG_CLR_MASK 0x00800000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF24_READ_FLAG_CLR_MASK 0x01000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF25_READ_FLAG_CLR_MASK 0x02000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF26_READ_FLAG_CLR_MASK 0x04000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF27_READ_FLAG_CLR_MASK 0x08000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF28_READ_FLAG_CLR_MASK 0x10000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF29_READ_FLAG_CLR_MASK 0x20000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF2_READ_FLAG_CLR_MASK 0x00000004L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF30_READ_FLAG_CLR_MASK 0x40000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF31_READ_FLAG_CLR_MASK 0x80000000L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF3_READ_FLAG_CLR_MASK 0x00000008L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF4_READ_FLAG_CLR_MASK 0x00000010L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF5_READ_FLAG_CLR_MASK 0x00000020L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF6_READ_FLAG_CLR_MASK 0x00000040L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF7_READ_FLAG_CLR_MASK 0x00000080L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF8_READ_FLAG_CLR_MASK 0x00000100L -#define HDP_SURFACE_READ_FLAGS_CLR__SURF9_READ_FLAG_CLR_MASK 0x00000200L -#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L -#define HDP_SURFACE_READ_FLAGS__SURF10_READ_FLAG_MASK 0x00000400L -#define HDP_SURFACE_READ_FLAGS__SURF11_READ_FLAG_MASK 0x00000800L -#define HDP_SURFACE_READ_FLAGS__SURF12_READ_FLAG_MASK 0x00001000L -#define HDP_SURFACE_READ_FLAGS__SURF13_READ_FLAG_MASK 0x00002000L -#define HDP_SURFACE_READ_FLAGS__SURF14_READ_FLAG_MASK 0x00004000L -#define HDP_SURFACE_READ_FLAGS__SURF15_READ_FLAG_MASK 0x00008000L -#define HDP_SURFACE_READ_FLAGS__SURF16_READ_FLAG_MASK 0x00010000L -#define HDP_SURFACE_READ_FLAGS__SURF17_READ_FLAG_MASK 0x00020000L -#define HDP_SURFACE_READ_FLAGS__SURF18_READ_FLAG_MASK 0x00040000L -#define HDP_SURFACE_READ_FLAGS__SURF19_READ_FLAG_MASK 0x00080000L -#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L -#define HDP_SURFACE_READ_FLAGS__SURF20_READ_FLAG_MASK 0x00100000L -#define HDP_SURFACE_READ_FLAGS__SURF21_READ_FLAG_MASK 0x00200000L -#define HDP_SURFACE_READ_FLAGS__SURF22_READ_FLAG_MASK 0x00400000L -#define HDP_SURFACE_READ_FLAGS__SURF23_READ_FLAG_MASK 0x00800000L -#define HDP_SURFACE_READ_FLAGS__SURF24_READ_FLAG_MASK 0x01000000L -#define HDP_SURFACE_READ_FLAGS__SURF25_READ_FLAG_MASK 0x02000000L -#define HDP_SURFACE_READ_FLAGS__SURF26_READ_FLAG_MASK 0x04000000L -#define HDP_SURFACE_READ_FLAGS__SURF27_READ_FLAG_MASK 0x08000000L -#define HDP_SURFACE_READ_FLAGS__SURF28_READ_FLAG_MASK 0x10000000L -#define HDP_SURFACE_READ_FLAGS__SURF29_READ_FLAG_MASK 0x20000000L -#define HDP_SURFACE_READ_FLAGS__SURF2_READ_FLAG_MASK 0x00000004L -#define HDP_SURFACE_READ_FLAGS__SURF30_READ_FLAG_MASK 0x40000000L -#define HDP_SURFACE_READ_FLAGS__SURF31_READ_FLAG_MASK 0x80000000L -#define HDP_SURFACE_READ_FLAGS__SURF3_READ_FLAG_MASK 0x00000008L -#define HDP_SURFACE_READ_FLAGS__SURF4_READ_FLAG_MASK 0x00000010L -#define HDP_SURFACE_READ_FLAGS__SURF5_READ_FLAG_MASK 0x00000020L -#define HDP_SURFACE_READ_FLAGS__SURF6_READ_FLAG_MASK 0x00000040L -#define HDP_SURFACE_READ_FLAGS__SURF7_READ_FLAG_MASK 0x00000080L -#define HDP_SURFACE_READ_FLAGS__SURF8_READ_FLAG_MASK 0x00000100L -#define HDP_SURFACE_READ_FLAGS__SURF9_READ_FLAG_MASK 0x00000200L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF10_WRITE_FLAG_CLR_MASK 0x00000400L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF11_WRITE_FLAG_CLR_MASK 0x00000800L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF12_WRITE_FLAG_CLR_MASK 0x00001000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF13_WRITE_FLAG_CLR_MASK 0x00002000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF14_WRITE_FLAG_CLR_MASK 0x00004000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF15_WRITE_FLAG_CLR_MASK 0x00008000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF16_WRITE_FLAG_CLR_MASK 0x00010000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF17_WRITE_FLAG_CLR_MASK 0x00020000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF18_WRITE_FLAG_CLR_MASK 0x00040000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF19_WRITE_FLAG_CLR_MASK 0x00080000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF20_WRITE_FLAG_CLR_MASK 0x00100000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF21_WRITE_FLAG_CLR_MASK 0x00200000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF22_WRITE_FLAG_CLR_MASK 0x00400000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF23_WRITE_FLAG_CLR_MASK 0x00800000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF24_WRITE_FLAG_CLR_MASK 0x01000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF25_WRITE_FLAG_CLR_MASK 0x02000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF26_WRITE_FLAG_CLR_MASK 0x04000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF27_WRITE_FLAG_CLR_MASK 0x08000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF28_WRITE_FLAG_CLR_MASK 0x10000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF29_WRITE_FLAG_CLR_MASK 0x20000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF2_WRITE_FLAG_CLR_MASK 0x00000004L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF30_WRITE_FLAG_CLR_MASK 0x40000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF31_WRITE_FLAG_CLR_MASK 0x80000000L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF3_WRITE_FLAG_CLR_MASK 0x00000008L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF4_WRITE_FLAG_CLR_MASK 0x00000010L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF5_WRITE_FLAG_CLR_MASK 0x00000020L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF6_WRITE_FLAG_CLR_MASK 0x00000040L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF7_WRITE_FLAG_CLR_MASK 0x00000080L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF8_WRITE_FLAG_CLR_MASK 0x00000100L -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF9_WRITE_FLAG_CLR_MASK 0x00000200L -#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L -#define HDP_SURFACE_WRITE_FLAGS__SURF10_WRITE_FLAG_MASK 0x00000400L -#define HDP_SURFACE_WRITE_FLAGS__SURF11_WRITE_FLAG_MASK 0x00000800L -#define HDP_SURFACE_WRITE_FLAGS__SURF12_WRITE_FLAG_MASK 0x00001000L -#define HDP_SURFACE_WRITE_FLAGS__SURF13_WRITE_FLAG_MASK 0x00002000L -#define HDP_SURFACE_WRITE_FLAGS__SURF14_WRITE_FLAG_MASK 0x00004000L -#define HDP_SURFACE_WRITE_FLAGS__SURF15_WRITE_FLAG_MASK 0x00008000L -#define HDP_SURFACE_WRITE_FLAGS__SURF16_WRITE_FLAG_MASK 0x00010000L -#define HDP_SURFACE_WRITE_FLAGS__SURF17_WRITE_FLAG_MASK 0x00020000L -#define HDP_SURFACE_WRITE_FLAGS__SURF18_WRITE_FLAG_MASK 0x00040000L -#define HDP_SURFACE_WRITE_FLAGS__SURF19_WRITE_FLAG_MASK 0x00080000L -#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L -#define HDP_SURFACE_WRITE_FLAGS__SURF20_WRITE_FLAG_MASK 0x00100000L -#define HDP_SURFACE_WRITE_FLAGS__SURF21_WRITE_FLAG_MASK 0x00200000L -#define HDP_SURFACE_WRITE_FLAGS__SURF22_WRITE_FLAG_MASK 0x00400000L -#define HDP_SURFACE_WRITE_FLAGS__SURF23_WRITE_FLAG_MASK 0x00800000L -#define HDP_SURFACE_WRITE_FLAGS__SURF24_WRITE_FLAG_MASK 0x01000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF25_WRITE_FLAG_MASK 0x02000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF26_WRITE_FLAG_MASK 0x04000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF27_WRITE_FLAG_MASK 0x08000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF28_WRITE_FLAG_MASK 0x10000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF29_WRITE_FLAG_MASK 0x20000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF2_WRITE_FLAG_MASK 0x00000004L -#define HDP_SURFACE_WRITE_FLAGS__SURF30_WRITE_FLAG_MASK 0x40000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF31_WRITE_FLAG_MASK 0x80000000L -#define HDP_SURFACE_WRITE_FLAGS__SURF3_WRITE_FLAG_MASK 0x00000008L -#define HDP_SURFACE_WRITE_FLAGS__SURF4_WRITE_FLAG_MASK 0x00000010L -#define HDP_SURFACE_WRITE_FLAGS__SURF5_WRITE_FLAG_MASK 0x00000020L -#define HDP_SURFACE_WRITE_FLAGS__SURF6_WRITE_FLAG_MASK 0x00000040L -#define HDP_SURFACE_WRITE_FLAGS__SURF7_WRITE_FLAG_MASK 0x00000080L -#define HDP_SURFACE_WRITE_FLAGS__SURF8_WRITE_FLAG_MASK 0x00000100L -#define HDP_SURFACE_WRITE_FLAGS__SURF9_WRITE_FLAG_MASK 0x00000200L -#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffffL -#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x00003800L -#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x00000030L -#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0x000000c0L -#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0x0000000eL -#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x00000700L -#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0x0000c000L -#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0000ffffL -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0x0000000fL -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0x00000ff0L -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000L -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000L -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000L -#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000ffL -#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000ff00L -#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00ff0000L -#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000L -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000ffffL -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000f0000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000fL -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000f0L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x00020000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000f800L -#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffffL -#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffffL -#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000L -#define HDP_XDP_DBG_ADDR__STS_MASK 0x0000ffffL -#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000L -#define HDP_XDP_DBG_DATA__STS_MASK 0x0000ffffL -#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000L -#define HDP_XDP_DBG_MASK__STS_MASK 0x0000ffffL -#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffffL -#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffffL -#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffffL -#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03ffffffL -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003fL -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000fc0L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x00000001L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000006L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x00000008L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x00000001L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x00000006L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x00000008L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x00700000L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x00000010L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x00000060L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x00000080L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000fc000L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x00003f00L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L -#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000ffffL -#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000f0000L -#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000fL -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x001ffffeL -#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x001ffffeL -#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x001ffffeL -#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x001ffffeL -#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x001ffffeL -#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x001ffffeL -#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x001ffffeL -#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x00003fffL -#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x00000018L -#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x00000001L -#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x00000006L -#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x0000003fL -#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x00000040L -#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x00000080L -#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000ffffL -#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000L -#define HD_BACKPORCH_DUR__HD_BP_DUR_PBPR_MASK__SI 0x07ff0000L -#define HD_BACKPORCH_DUR__HD_BP_DUR_Y_MASK__SI 0x000007ffL -#define HD_CGMS_TIMING__HD_CGMS_EN_MASK__SI 0x80000000L -#define HD_CGMS_TIMING__HD_CGMS_RB_EN_MASK__SI 0x20000000L -#define HD_CGMS_TIMING__HD_CGMS_VEND_MASK__SI 0x07ff0000L -#define HD_CGMS_TIMING__HD_CGMS_WIDTH_MASK__SI 0x000000ffL -#define HD_CGMS_TIMING__HD_CGMS_YG_EN_MASK__SI 0x40000000L -#define HD_EMBEDDED_SYNC_CNTL__HD_DEBUG0_MASK__SI 0xffff0000L -#define HD_EMBEDDED_SYNC_CNTL__HD_EMBED_SYNC_EN_PB_B_MASK__SI 0x00000002L -#define HD_EMBEDDED_SYNC_CNTL__HD_EMBED_SYNC_EN_PR_R_MASK__SI 0x00000004L -#define HD_EMBEDDED_SYNC_CNTL__HD_EMBED_SYNC_EN_Y_G_MASK__SI 0x00000001L -#define HD_EMBEDDED_SYNC_CNTL__HD_TRILEVEL_SYNC_EN_MASK__SI 0x00000008L -#define HD_INCR__HD_INCR_PB_B_PR_R_MASK__SI 0x03ff0000L -#define HD_INCR__HD_INCR_Y_G_MASK__SI 0x000003ffL -#define HD_POS_SYNC_LEVEL__HD_POS_SYNC_LEVEL_PB_B_PR_R_MASK__SI 0x03ff0000L -#define HD_POS_SYNC_LEVEL__HD_POS_SYNC_LEVEL_Y_G_MASK__SI 0x000003ffL -#define HD_SERATION_DUR__HD_SER_DUR_PBPR_MASK__SI 0x07ff0000L -#define HD_SERATION_DUR__HD_SER_DUR_Y_MASK__SI 0x000007ffL -#define HD_TRILEVEL_DUR__HD_TRILEVEL_DUR_PBPR_MASK__SI 0x07ff0000L -#define HD_TRILEVEL_DUR__HD_TRILEVEL_DUR_Y_MASK__SI 0x000007ffL -#define HEADER__DEVICE_TYPE_MASK 0x00000080L -#define HEADER__HEADER_TYPE_MASK 0x0000007fL -#define HFS_SEED0__RESERVED_MASK 0xffffffffL -#define HFS_SEED1__RESERVED_MASK 0xffffffffL -#define HFS_SEED2__RESERVED_MASK 0xffffffffL -#define HFS_SEED3__RESERVED_MASK 0xffffffffL -#define HOST_BUSNUM__HOST_ID_MASK__CI__VI 0x0000ffffL -#define HOST_BUSNUM__HOST_ID_MASK__SI 0x000000ffL -#define HPD_DEBUG__DOUT_HPD_DEBUG_MASK__SI 0x3fffffffL -#define HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L -#define HW_DEBUG__HW_16_DEBUG_MASK 0x00010000L -#define HW_DEBUG__HW_17_DEBUG_MASK 0x00020000L -#define HW_DEBUG__HW_18_DEBUG_MASK 0x00040000L -#define HW_DEBUG__HW_19_DEBUG_MASK 0x00080000L -#define HW_DEBUG__HW_20_DEBUG_MASK 0x00100000L -#define HW_DEBUG__HW_21_DEBUG_MASK 0x00200000L -#define HW_DEBUG__HW_22_DEBUG_MASK 0x00400000L -#define HW_DEBUG__HW_23_DEBUG_MASK 0x00800000L -#define HW_DEBUG__HW_24_DEBUG_MASK 0x01000000L -#define HW_DEBUG__HW_25_DEBUG_MASK 0x02000000L -#define HW_DEBUG__HW_26_DEBUG_MASK 0x04000000L -#define HW_DEBUG__HW_27_DEBUG_MASK 0x08000000L -#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000L -#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000L -#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000L -#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000L -#define I2C_CNTL_0__I2C_ABORT_MASK__SI 0x00000800L -#define I2C_CNTL_0__I2C_DONE_MASK__SI 0x00000001L -#define I2C_CNTL_0__I2C_DRIVE_EN_MASK__SI 0x00000040L -#define I2C_CNTL_0__I2C_DRIVE_SEL_MASK__SI 0x00000080L -#define I2C_CNTL_0__I2C_GO_MASK__SI 0x00001000L -#define I2C_CNTL_0__I2C_HALT_MASK__SI 0x00000004L -#define I2C_CNTL_0__I2C_NACK_MASK__SI 0x00000002L -#define I2C_CNTL_0__I2C_PRESCALE_MASK__SI 0xffff0000L -#define I2C_CNTL_0__I2C_RECEIVE_MASK__SI 0x00000400L -#define I2C_CNTL_0__I2C_SOFT_RST_MASK__SI 0x00000020L -#define I2C_CNTL_0__I2C_START_MASK__SI 0x00000100L -#define I2C_CNTL_0__I2C_STOP_MASK__SI 0x00000200L -#define I2C_CNTL_1__I2C_ADDR_COUNT_MASK__SI 0x00000070L -#define I2C_CNTL_1__I2C_DATA_COUNT_MASK__SI 0x0000000fL -#define I2C_CNTL_1__I2C_EN_MASK__SI 0x00020000L -#define I2C_CNTL_1__I2C_INTRA_BYTE_DELAY_MASK__SI 0x0000ff00L -#define I2C_CNTL_1__I2C_SEL_MASK__SI 0x00010000L -#define I2C_CNTL_1__I2C_TIME_LIMIT_MASK__SI 0xff000000L -#define I2C_DATA__I2C_DATA_MASK__SI 0x000000ffL -#define I2C_DEBUG_BUS__DOUT_HPD_DEBUG_EXTN_MASK__SI 0x0000003fL -#define I2C_DEBUG_BUS__DOUT_I2C_DEBUG_BUS_MASK__SI 0xff000000L -#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L -#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L -#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L -#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L -#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x0000003fL -#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x00000040L -#define IA_DEBUG_DATA__DATA_MASK 0xffffffffL -#define IA_DEBUG_REG0__SPARE0_MASK__CI__VI 0x00000010L -#define IA_DEBUG_REG0__SPARE1_MASK__CI__VI 0x00000200L -#define IA_DEBUG_REG0__SPARE2_MASK__CI__VI 0x00ffc000L -#define IA_DEBUG_REG0__SPARE3_MASK__CI__VI 0x04000000L -#define IA_DEBUG_REG0__SPARE3_MASK__SI 0x00100000L -#define IA_DEBUG_REG0__SPARE4_MASK__CI__VI 0x08000000L -#define IA_DEBUG_REG0__SPARE5_MASK__CI__VI 0x40000000L -#define IA_DEBUG_REG0__SPARE6_MASK__CI__VI 0x80000000L -#define IA_DEBUG_REG0__adc_busy_r0_MASK__SI 0x00800000L -#define IA_DEBUG_REG0__adc_busy_r1_MASK__SI 0x00400000L -#define IA_DEBUG_REG0__adc_busy_r2_MASK__SI 0x00200000L -#define IA_DEBUG_REG0__core_clk_busy_MASK__CI__VI 0x02000000L -#define IA_DEBUG_REG0__core_clk_busy_MASK__SI 0x04000000L -#define IA_DEBUG_REG0__dma_busy_MASK 0x00000040L -#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK__CI__VI 0x00001000L -#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x00000400L -#define IA_DEBUG_REG0__dma_req_busy_MASK__CI__VI 0x00000020L -#define IA_DEBUG_REG0__dma_request_busy_MASK__SI 0x00000020L -#define IA_DEBUG_REG0__grp_busy_MASK 0x00000100L -#define IA_DEBUG_REG0__grp_dma_hp_read_MASK__CI__VI 0x00002000L -#define IA_DEBUG_REG0__grp_dma_read_MASK 0x00000800L -#define IA_DEBUG_REG0__grp_rbiu_di_read_MASK__SI 0x00080000L -#define IA_DEBUG_REG0__ia_busy_MASK 0x00000004L -#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x00000001L -#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x00000008L -#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x00000002L -#define IA_DEBUG_REG0__input_clk_busy_MASK__SI 0x02000000L -#define IA_DEBUG_REG0__inval_clk_busy_MASK__SI 0x08000000L -#define IA_DEBUG_REG0__invld_busy_MASK__SI 0x00000200L -#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x00000080L -#define IA_DEBUG_REG0__rbiu_busy_MASK__SI 0x00000010L -#define IA_DEBUG_REG0__rbiu_di_fifo_empty_MASK__SI 0x00004000L -#define IA_DEBUG_REG0__rbiu_di_fifo_full_MASK__SI 0x00008000L -#define IA_DEBUG_REG0__rbiu_dr_fifo_empty_MASK__SI 0x00010000L -#define IA_DEBUG_REG0__rbiu_dr_fifo_full_MASK__SI 0x00020000L -#define IA_DEBUG_REG0__rbiu_grp_di_valid_MASK__SI 0x00040000L -#define IA_DEBUG_REG0__rbiu_im_fifo_empty_MASK__SI 0x00001000L -#define IA_DEBUG_REG0__rbiu_im_fifo_full_MASK__SI 0x00002000L -#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L -#define IA_DEBUG_REG0__sclk_adc_vld_MASK__SI 0x40000000L -#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L -#define IA_DEBUG_REG0__sclk_input_vld_MASK__SI 0x80000000L -#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000L -#define IA_DEBUG_REG1__SPARE0_MASK__SI 0x0c000000L -#define IA_DEBUG_REG1__current_data_valid_MASK__CI__VI 0x10000000L -#define IA_DEBUG_REG1__discard_1st_chunk_MASK__CI__VI 0x00000100L -#define IA_DEBUG_REG1__discard_2nd_chunk_MASK__CI__VI 0x00000200L -#define IA_DEBUG_REG1__disp_initiator_valid_q_MASK__SI 0x80000000L -#define IA_DEBUG_REG1__dma_buf_type_q_MASK__CI__VI 0x00000060L -#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK__CI__VI 0x00004000L -#define IA_DEBUG_REG1__dma_data_fifo_full_MASK__CI__VI 0x00008000L -#define IA_DEBUG_REG1__dma_grp_valid_MASK__CI__VI 0x04000000L -#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK__CI__VI 0x00000001L -#define IA_DEBUG_REG1__dma_input_fifo_full_MASK__CI__VI 0x00000002L -#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK__CI__VI 0x00002000L -#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK__CI__VI 0x40000000L -#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK__CI__VI 0x00000008L -#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK__CI__VI 0x00010000L -#define IA_DEBUG_REG1__dma_req_fifo_full_MASK__CI__VI 0x00020000L -#define IA_DEBUG_REG1__dma_req_path_q_MASK__CI__VI 0x00000080L -#define IA_DEBUG_REG1__dma_request_valid_q_MASK__SI 0x00000080L -#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK__CI__VI 0x80000000L -#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK__CI__VI 0x01000000L -#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK__CI__VI 0x02000000L -#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK__CI__VI 0x00000800L -#define IA_DEBUG_REG1__dma_zero_indices_q_MASK__CI__VI 0x00000010L -#define IA_DEBUG_REG1__draw_initiator_valid_q_MASK__SI 0x00000010L -#define IA_DEBUG_REG1__event_addr_valid_q_MASK__SI 0x00000040L -#define IA_DEBUG_REG1__event_initiator_valid_q_MASK__SI 0x00000020L -#define IA_DEBUG_REG1__free_cnt_q_MASK__SI 0x03f00000L -#define IA_DEBUG_REG1__grbm_fifo_empty_MASK__SI 0x00000001L -#define IA_DEBUG_REG1__grbm_fifo_full_MASK__SI 0x00000002L -#define IA_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK__SI 0x0001f000L -#define IA_DEBUG_REG1__grbm_fifo_rdata_state_MASK__SI 0x000e0000L -#define IA_DEBUG_REG1__grbm_fifo_re_MASK__SI 0x00000008L -#define IA_DEBUG_REG1__grbm_fifo_we_MASK__SI 0x00000004L -#define IA_DEBUG_REG1__grp_dma_read_MASK__CI__VI 0x08000000L -#define IA_DEBUG_REG1__immed_data_valid_q_MASK__SI 0x00000100L -#define IA_DEBUG_REG1__indx_offset_valid_q_MASK__SI 0x00000800L -#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK__CI__VI 0x00001000L -#define IA_DEBUG_REG1__max_indx_valid_q_MASK__SI 0x00000400L -#define IA_DEBUG_REG1__min_indx_valid_q_MASK__SI 0x00000200L -#define IA_DEBUG_REG1__out_of_range_r2_q_MASK__CI__VI 0x20000000L -#define IA_DEBUG_REG1__rbiu_di_fifo_we_MASK__SI 0x10000000L -#define IA_DEBUG_REG1__rbiu_dr_fifo_we_MASK__SI 0x20000000L -#define IA_DEBUG_REG1__rbiu_im_fifo_we_MASK__SI 0x40000000L -#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK__CI__VI 0x00000400L -#define IA_DEBUG_REG1__stage2_dr_MASK__CI__VI 0x00040000L -#define IA_DEBUG_REG1__stage2_rtr_MASK__CI__VI 0x00080000L -#define IA_DEBUG_REG1__stage3_dr_MASK__CI__VI 0x00100000L -#define IA_DEBUG_REG1__stage3_rtr_MASK__CI__VI 0x00200000L -#define IA_DEBUG_REG1__stage4_dr_MASK__CI__VI 0x00400000L -#define IA_DEBUG_REG1__stage4_rtr_MASK__CI__VI 0x00800000L -#define IA_DEBUG_REG1__start_new_packet_MASK__CI__VI 0x00000004L -#define IA_DEBUG_REG2__bfa_dma_rdreq_freeze_MASK__SI 0x00000800L -#define IA_DEBUG_REG2__current_data_valid_MASK__SI 0x10000000L -#define IA_DEBUG_REG2__dma_bfa_rdreq_frozen_MASK__SI 0x00000400L -#define IA_DEBUG_REG2__dma_busy_MASK__SI 0x00000001L -#define IA_DEBUG_REG2__dma_data_fifo_empty_q_MASK__SI 0x00004000L -#define IA_DEBUG_REG2__dma_data_fifo_full_MASK__SI 0x00008000L -#define IA_DEBUG_REG2__dma_grp_valid_MASK__SI 0x04000000L -#define IA_DEBUG_REG2__dma_mask_fifo_empty_MASK__SI 0x00002000L -#define IA_DEBUG_REG2__dma_rdreq_dr_q_MASK__SI 0x00000008L -#define IA_DEBUG_REG2__dma_skid_fifo_empty_MASK__SI 0x01000000L -#define IA_DEBUG_REG2__dma_skid_fifo_full_MASK__SI 0x02000000L -#define IA_DEBUG_REG2__grp_dma_read_MASK__SI 0x08000000L -#define IA_DEBUG_REG2__hp_current_data_valid_MASK__CI__VI 0x10000000L -#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK__CI__VI 0x00000100L -#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK__CI__VI 0x00000200L -#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK__CI__VI 0x00000060L -#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK__CI__VI 0x00004000L -#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK__CI__VI 0x00008000L -#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK__CI__VI 0x04000000L -#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK__CI__VI 0x00000001L -#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK__CI__VI 0x00000002L -#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK__CI__VI 0x00002000L -#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK__CI__VI 0x40000000L -#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK__CI__VI 0x00000008L -#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK__CI__VI 0x00010000L -#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK__CI__VI 0x00020000L -#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK__CI__VI 0x00000080L -#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK__CI__VI 0x80000000L -#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK__CI__VI 0x01000000L -#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK__CI__VI 0x02000000L -#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK__CI__VI 0x00000800L -#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK__CI__VI 0x00000010L -#define IA_DEBUG_REG2__hp_grp_dma_read_MASK__CI__VI 0x08000000L -#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK__CI__VI 0x00001000L -#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK__CI__VI 0x20000000L -#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK__CI__VI 0x00000400L -#define IA_DEBUG_REG2__hp_stage2_dr_MASK__CI__VI 0x00040000L -#define IA_DEBUG_REG2__hp_stage2_rtr_MASK__CI__VI 0x00080000L -#define IA_DEBUG_REG2__hp_stage3_dr_MASK__CI__VI 0x00100000L -#define IA_DEBUG_REG2__hp_stage3_rtr_MASK__CI__VI 0x00200000L -#define IA_DEBUG_REG2__hp_stage4_dr_MASK__CI__VI 0x00400000L -#define IA_DEBUG_REG2__hp_stage4_rtr_MASK__CI__VI 0x00800000L -#define IA_DEBUG_REG2__hp_start_new_packet_MASK__CI__VI 0x00000004L -#define IA_DEBUG_REG2__instances_remaining_MASK__SI 0x80000000L -#define IA_DEBUG_REG2__last_rdreq_in_dma_op_MASK__SI 0x00001000L -#define IA_DEBUG_REG2__mask_kill_MASK__SI 0x40000000L -#define IA_DEBUG_REG2__mc_rdreq_sent_cnt_q_MASK__SI 0x000003f0L -#define IA_DEBUG_REG2__rbiu_dma_valid_MASK__SI 0x00000002L -#define IA_DEBUG_REG2__rbiu_read_MASK__SI 0x00000004L -#define IA_DEBUG_REG2__reserved_MASK__SI 0x00030000L -#define IA_DEBUG_REG2__second_128bit_read_MASK__SI 0x20000000L -#define IA_DEBUG_REG2__stage2_dr_MASK__SI 0x00040000L -#define IA_DEBUG_REG2__stage2_rtr_MASK__SI 0x00080000L -#define IA_DEBUG_REG2__stage3_dr_MASK__SI 0x00100000L -#define IA_DEBUG_REG2__stage3_rtr_MASK__SI 0x00200000L -#define IA_DEBUG_REG2__stage4_dr_MASK__SI 0x00400000L -#define IA_DEBUG_REG2__stage4_rtr_MASK__SI 0x00800000L -#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK__CI__VI 0x20000000L -#define IA_DEBUG_REG3__SPARE_MASK__SI 0xc0000000L -#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK__CI__VI 0x80000000L -#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK__CI__VI 0x40000000L -#define IA_DEBUG_REG3__adc_spi_freeze_r0_MASK__SI 0x00000200L -#define IA_DEBUG_REG3__adc_spi_freeze_r1_MASK__SI 0x00080000L -#define IA_DEBUG_REG3__adc_spi_freeze_r2_MASK__SI 0x20000000L -#define IA_DEBUG_REG3__csinvoc_en_r0_MASK__SI 0x00000008L -#define IA_DEBUG_REG3__csinvoc_en_r1_MASK__SI 0x00002000L -#define IA_DEBUG_REG3__csinvoc_en_r2_MASK__SI 0x00800000L -#define IA_DEBUG_REG3__current_state_r0_MASK__SI 0x00000007L -#define IA_DEBUG_REG3__current_state_r1_MASK__SI 0x00001c00L -#define IA_DEBUG_REG3__current_state_r2_MASK__SI 0x00700000L -#define IA_DEBUG_REG3__discard_1st_chunk_MASK__CI__VI 0x04000000L -#define IA_DEBUG_REG3__discard_2nd_chunk_MASK__CI__VI 0x08000000L -#define IA_DEBUG_REG3__dispatch_init_force_start_at_000_r0_MASK__SI 0x00000020L -#define IA_DEBUG_REG3__dispatch_init_force_start_at_000_r1_MASK__SI 0x00008000L -#define IA_DEBUG_REG3__dispatch_init_force_start_at_000_r2_MASK__SI 0x02000000L -#define IA_DEBUG_REG3__dispatch_init_ordered_append_enbl_r0_MASK__SI 0x00000040L -#define IA_DEBUG_REG3__dispatch_init_ordered_append_enbl_r1_MASK__SI 0x00010000L -#define IA_DEBUG_REG3__dispatch_init_ordered_append_enbl_r2_MASK__SI 0x04000000L -#define IA_DEBUG_REG3__dispatch_init_partial_tg_en_r0_MASK__SI 0x00000010L -#define IA_DEBUG_REG3__dispatch_init_partial_tg_en_r1_MASK__SI 0x00004000L -#define IA_DEBUG_REG3__dispatch_init_partial_tg_en_r2_MASK__SI 0x01000000L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK__CI__VI 0x00000008L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK__CI__VI 0x00000004L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK__CI__VI 0x00000002L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK__CI__VI 0x00000010L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK__CI__VI 0x00000001L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK__CI__VI 0x00000800L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK__CI__VI 0x00000400L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK__CI__VI 0x00000200L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK__CI__VI 0x00001000L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK__CI__VI 0x00000100L -#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK__CI__VI 0x00008000L -#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK__CI__VI 0x00000020L -#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK__CI__VI 0x00002000L -#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK__CI__VI 0x00040000L -#define IA_DEBUG_REG3__kill_threadgroup_r0_MASK__SI 0x00000100L -#define IA_DEBUG_REG3__kill_threadgroup_r1_MASK__SI 0x00040000L -#define IA_DEBUG_REG3__kill_threadgroup_r2_MASK__SI 0x10000000L -#define IA_DEBUG_REG3__last_tc_req_p1_MASK__CI__VI 0x10000000L -#define IA_DEBUG_REG3__mc_out_rtr_MASK__CI__VI 0x00004000L -#define IA_DEBUG_REG3__must_service_pipe0_req_MASK__CI__VI 0x00000040L -#define IA_DEBUG_REG3__pair0_valid_p1_MASK__CI__VI 0x00100000L -#define IA_DEBUG_REG3__pair1_valid_p1_MASK__CI__VI 0x00200000L -#define IA_DEBUG_REG3__pair2_valid_p1_MASK__CI__VI 0x00400000L -#define IA_DEBUG_REG3__pair3_valid_p1_MASK__CI__VI 0x00800000L -#define IA_DEBUG_REG3__pipe0_dr_MASK__CI__VI 0x00010000L -#define IA_DEBUG_REG3__pipe0_rtr_MASK__CI__VI 0x00020000L -#define IA_DEBUG_REG3__reset_wave_id_r0_MASK__SI 0x00000080L -#define IA_DEBUG_REG3__reset_wave_id_r1_MASK__SI 0x00020000L -#define IA_DEBUG_REG3__reset_wave_id_r2_MASK__SI 0x08000000L -#define IA_DEBUG_REG3__send_pipe1_req_MASK__CI__VI 0x00000080L -#define IA_DEBUG_REG3__tc_out_rtr_MASK__CI__VI 0x00080000L -#define IA_DEBUG_REG3__tc_req_count_q_MASK__CI__VI 0x03000000L -#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000L -#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x00100000L -#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK__CI__VI 0x20000000L -#define IA_DEBUG_REG4__di_first_group_of_inst_q_MASK__SI 0x20000000L -#define IA_DEBUG_REG4__di_major_mode_p1_q_0_MASK__SI 0x00010000L -#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK__CI__VI 0x00010000L -#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0x0c000000L -#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0x00e00000L -#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x02000000L -#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x01000000L -#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x00000040L -#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x00000080L -#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0x000e0000L -#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x00008000L -#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x00004000L -#define IA_DEBUG_REG4__last_shift_of_draw_MASK__CI__VI 0x40000000L -#define IA_DEBUG_REG4__last_shift_of_instance_MASK__SI 0x40000000L -#define IA_DEBUG_REG4__pipe0_dr_MASK 0x00000001L -#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x00000100L -#define IA_DEBUG_REG4__pipe1_dr_MASK 0x00000002L -#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x00000200L -#define IA_DEBUG_REG4__pipe2_dr_MASK 0x00000004L -#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x00000400L -#define IA_DEBUG_REG4__pipe3_dr_MASK 0x00000008L -#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x00000800L -#define IA_DEBUG_REG4__pipe4_dr_MASK 0x00000010L -#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x00001000L -#define IA_DEBUG_REG4__pipe5_dr_MASK 0x00000020L -#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x00002000L -#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000L -#define IA_DEBUG_REG5__current_instance_q_15_0_MASK__SI 0xffff0000L -#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0x0000ffffL -#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK__CI__VI 0x80000000L -#define IA_DEBUG_REG5__draw_input_fifo_full_MASK__CI__VI 0x40000000L -#define IA_DEBUG_REG5__instanceid_13_0_MASK__CI__VI 0x3fff0000L -#define IA_DEBUG_REG6__after_group_partial_MASK__CI__VI 0x00400000L -#define IA_DEBUG_REG6__after_prim_partial_MASK__SI 0x00400000L -#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x00008000L -#define IA_DEBUG_REG6__current_shift_q_MASK 0x0000000fL -#define IA_DEBUG_REG6__current_stride_pre_MASK 0x000000f0L -#define IA_DEBUG_REG6__current_stride_q_MASK 0x00001f00L -#define IA_DEBUG_REG6__extract_group_MASK 0x00800000L -#define IA_DEBUG_REG6__first_group_partial_MASK__CI__VI 0x00002000L -#define IA_DEBUG_REG6__first_prim_partial_MASK__SI 0x00002000L -#define IA_DEBUG_REG6__grp_shift_debug_data_MASK__CI__VI 0xff000000L -#define IA_DEBUG_REG6__next_group_partial_MASK__CI__VI 0x00200000L -#define IA_DEBUG_REG6__next_prim_partial_MASK__SI 0x00200000L -#define IA_DEBUG_REG6__next_stride_q_MASK 0x001f0000L -#define IA_DEBUG_REG6__second_group_partial_MASK__CI__VI 0x00004000L -#define IA_DEBUG_REG6__second_prim_partial_MASK__SI 0x00004000L -#define IA_DEBUG_REG6__shifter_load_needed_MASK__SI 0x40000000L -#define IA_DEBUG_REG6__shifter_space_avail_MASK__SI 0x20000000L -#define IA_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK__SI 0x80000000L -#define IA_DEBUG_REG6__shifter_word_count_q_MASK__SI 0x1f000000L -#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x02000000L -#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x04000000L -#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x08000000L -#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK__CI__VI 0x00800000L -#define IA_DEBUG_REG7__last_group_of_inst_p2_q_MASK__SI 0x00800000L -#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x00700000L -#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0x0000000fL -#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x01000000L -#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000L -#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000L -#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000L -#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000L -#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0x0000f000L -#define IA_DEBUG_REG7__shift_vect1_comp_en_p2_q_MASK__SI 0x00000f00L -#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0x000f0000L -#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK__CI__VI 0x00000f00L -#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0x000000f0L -#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x0000001fL -#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000L -#define IA_DEBUG_REG8__grp_continued_MASK 0x00000800L -#define IA_DEBUG_REG8__grp_eop_MASK 0x02000000L -#define IA_DEBUG_REG8__grp_eopg_MASK 0x04000000L -#define IA_DEBUG_REG8__grp_event_flag_MASK 0x08000000L -#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x01000000L -#define IA_DEBUG_REG8__grp_output_path_MASK 0x00e00000L -#define IA_DEBUG_REG8__grp_state_sel_MASK 0x00007000L -#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x001f8000L -#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x00000100L -#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x00000400L -#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x00000200L -#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x00000080L -#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x00000020L -#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x00000040L -#define IA_DEBUG_REG9__SPARE0_MASK__CI__VI 0x00004000L -#define IA_DEBUG_REG9__SPARE1_MASK__CI__VI 0x00008000L -#define IA_DEBUG_REG9__disp_se_switch_p6_MASK__SI 0x00004000L -#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x00000400L -#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x00000200L -#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x00000002L -#define IA_DEBUG_REG9__gfx_send_to_se1_p5_q_MASK__SI 0x00002000L -#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK__CI__VI 0x00040000L -#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK__CI__VI 0x00080000L -#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x00000008L -#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x00000004L -#define IA_DEBUG_REG9__other_se_empty_packet_p6_MASK__SI 0x00008000L -#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x00000020L -#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x00000080L -#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x00000010L -#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x00000100L -#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x00000040L -#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x00020000L -#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x00000800L -#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x00001000L -#define IA_DEBUG_REG9__prim_counter_q_MASK__CI__VI 0xfff00000L -#define IA_DEBUG_REG9__prim_counter_q_MASK__SI 0xfffc0000L -#define IA_DEBUG_REG9__send_to_se1_p5_q_MASK__SI 0x00000001L -#define IA_DEBUG_REG9__send_to_se1_p6_MASK__CI__VI 0x00000001L -#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK__CI__VI 0x00010000L -#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK__CI__VI 0x00002000L -#define IA_DEBUG_REG9__valid_eop_switch_p6_MASK__SI 0x00010000L -#define IA_ENHANCE__MISC_MASK 0xffffffffL -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000ffffL -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK__CI__VI 0x00100000L -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L -#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L -#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L -#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL -#define IA_VMID_OVERRIDE__ENABLE_MASK__SI__CI 0x00000001L -#define IA_VMID_OVERRIDE__VMID_MASK__SI__CI 0x0000001eL -#define ICON_COLOR1__ICON_COLOR1_BLUE_MASK__SI 0x000000ffL -#define ICON_COLOR1__ICON_COLOR1_GREEN_MASK__SI 0x0000ff00L -#define ICON_COLOR1__ICON_COLOR1_RED_MASK__SI 0x00ff0000L -#define ICON_COLOR2__ICON_COLOR2_BLUE_MASK__SI 0x000000ffL -#define ICON_COLOR2__ICON_COLOR2_GREEN_MASK__SI 0x0000ff00L -#define ICON_COLOR2__ICON_COLOR2_RED_MASK__SI 0x00ff0000L -#define ICON_CONTROL__ICON_2X_MAGNIFY_MASK__SI 0x00010000L -#define ICON_CONTROL__ICON_ENABLE_MASK__SI 0x00000001L -#define ICON_CONTROL__ICON_FORCE_MC_ON_MASK__SI 0x00100000L -#define ICON_SIZE__ICON_HEIGHT_MASK__SI 0x0000007fL -#define ICON_SIZE__ICON_WIDTH_MASK__SI 0x007f0000L -#define ICON_START_POSITION__ICON_X_POSITION_MASK__SI 0x1fff0000L -#define ICON_START_POSITION__ICON_Y_POSITION_MASK__SI 0x00001fffL -#define ICON_SURFACE_ADDRESS_HIGH__ICON_SURFACE_ADDRESS_HIGH_MASK__SI 0x000000ffL -#define ICON_SURFACE_ADDRESS__ICON_SURFACE_ADDRESS_MASK__SI 0xffffffffL -#define ICON_UPDATE__ICON_DISABLE_MULTIPLE_UPDATE_MASK__SI 0x01000000L -#define ICON_UPDATE__ICON_UPDATE_LOCK_MASK__SI 0x00010000L -#define ICON_UPDATE__ICON_UPDATE_PENDING_MASK__SI 0x00000001L -#define ICON_UPDATE__ICON_UPDATE_TAKEN_MASK__SI 0x00000002L -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_DATA_SEND_MASK__SI 0x80000000L -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_EOC_MASK__SI 0x40000000L -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_P0_B_CB_MASK__SI 0x3ff00000L -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_P0_G_Y_MASK__SI 0x000ffc00L -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_P0_R_CR_MASK__SI 0x000003ffL -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_DISPNUM_MASK__SI 0x40000000L -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_P1_B_CB_MASK__SI 0x3ff00000L -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_P1_G_Y_MASK__SI 0x000ffc00L -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_P1_R_CR_MASK__SI 0x000003ffL -#define ID01_DCP_LB_DATA_P1__ID01_LB_DCP_SOF2_MASK__SI 0x80000000L -#define ID02_DCP_DMIF_GRPH_DATA_LOW_p0__ID02_DMIF_DCP_grph_data_LOW_p0_MASK__SI 0xffffffffL -#define ID03_DCP_DMIF_GRPH_DATA_HIGH_p0__ID03_DMIF_DCP_grph_data_HIGH_p0_MASK__SI 0xffffffffL -#define ID04_DCP_DMIF_GRPH_DATA_LOW_p1__ID04_DMIF_DCP_grph_data_LOW_p1_MASK__SI 0xffffffffL -#define ID05_DCP_DMIF_GRPH_DATA_HIGH_p1__ID05_DMIF_DCP_grph_data_HIGH_p1_MASK__SI 0xffffffffL -#define ID06_DCP_DMIF_OVLDATA_p0__ID06_DMIF_DCP_ovl_data_p0_MASK__SI 0xffffffffL -#define ID07_DCP_DMIF_OVLDATA_p1__ID07_DMIF_DCP_ovl_data_p1_MASK__SI 0xffffffffL -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_DCP_LB_RTR_MASK__SI 0x40000000L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_CHUNKSIZE_MASK__SI 0x08000000L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_DISPNUM_MASK__SI 0x00000080L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_L0_TAG_MASK__SI 0x00000007L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_L1_TAG_MASK__SI 0x00000038L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_LAST_CHUNK_OF_LINE_MASK__SI 0x10000000L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_NOT_LAST_LINE_PAIR_MASK__SI 0x20000000L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_RTS_MASK__SI 0x00000040L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_SOF1_MASK__SI 0x80000000L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_X_MASK__SI 0x00003f00L -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_Y_MASK__SI 0x07ffc000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_req_MASK__SI 0x00100000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_size_MASK__SI 0x00600000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_surface_MASK__SI 0x03000000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_x_MASK__SI 0x0000007fL -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_y_MASK__SI 0x000fff80L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DMIF_DCP_req_fifo_empty_MASK__SI 0x00800000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D1_START_LINE_MASK__SI 0x04000000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D1_STEREO_SELECT_MASK__SI 0x10000000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D1_V_UPDATE_MASK__SI 0x40000000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D2_START_LINE_MASK__SI 0x08000000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D2_STEREO_SELECT_MASK__SI 0x20000000L -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D2_V_UPDATE_MASK__SI 0x80000000L -#define ID10_DCP_DCCIF_DATA__ID10_CRTC1_DCP_htotal_by_8_MASK__SI 0x00010000L -#define ID10_DCP_DCCIF_DATA__ID10_CRTC2_DCP_htotal_by_8_MASK__SI 0x00020000L -#define ID10_DCP_DCCIF_DATA__ID10_DCCG_SCLK_G_DCP_clock_on_MASK__SI 0x00002000L -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_CLIENT_RTAG_MASK__SI 0x000007f8L -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_CLIENT_R_ID_MASK__SI 0x00001800L -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_CLIENT_VALID_MASK__SI 0x00000004L -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_DCP_CURSOR_RRTR_MASK__SI 0x00000002L -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_DCP_ICON_RRTR_MASK__SI 0x00000001L -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_grph_rtr_MASK__SI 0x00080000L -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_ovl_rtr_MASK__SI 0x00100000L -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_req_MASK__SI 0x00200000L -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_size_MASK__SI 0x00c00000L -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_urgent_MASK__SI 0x80000000L -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_x_MASK__SI 0x7f000000L -#define ID10_DCP_DCCIF_DATA__ID10_DMIF_DCP_busy_MASK__SI 0x00008000L -#define ID10_DCP_DCCIF_DATA__ID10_LB_DCP_URGENT_MASK__SI 0x00040000L -#define ID10_DCP_DCCIF_DATA__ID10_LB_DCP_WR_busy_MASK__SI 0x00004000L -#define ID11_DCP_DCCIF_REQUEST__ID11_DCP_ICON_DCCIF_ID_MASK__SI 0xe0000000L -#define ID11_DCP_DCCIF_REQUEST__ID11_DCP_ICON_DCCIF_RADDR_MASK__SI 0x1ffffffeL -#define ID11_DCP_DCCIF_REQUEST__ID11_DCP_ICON_DCCIF_RREQ_MASK__SI 0x00000001L -#define ID12_DCP_DCCIF_REQUEST__ID12_DCP_CURSOR_DCCIF_ID_MASK__SI 0xe0000000L -#define ID12_DCP_DCCIF_REQUEST__ID12_DCP_CURSOR_DCCIF_RADDR_MASK__SI 0x1ffffffeL -#define ID12_DCP_DCCIF_REQUEST__ID12_DCP_CURSOR_DCCIF_RREQ_MASK__SI 0x00000001L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_CURSOR_DCCIF_RTAG_MASK__SI 0x0000ff00L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_CURSOR_DCCIF_URGENT_MASK__SI 0x00020000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_CURSOR_EN_p0_MASK__SI 0x02000000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_CURSOR_EN_p1_MASK__SI 0x04000000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_GRPH_EN_p0_MASK__SI 0x00200000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_GRPH_EN_p1_MASK__SI 0x00400000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_G_O_REQUEST_STATE_MASK__SI 0xe0000000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_ICON_EN_p0_MASK__SI 0x08000000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_ICON_EN_p1_MASK__SI 0x10000000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_OVL_EN_p0_MASK__SI 0x00800000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_OVL_EN_p1_MASK__SI 0x01000000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_ICON_DCCIF_RTAG_MASK__SI 0x000000ffL -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_ICON_DCCIF_URGENT_MASK__SI 0x00040000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_PER_lut_host_rw_MASK__SI 0x00080000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_PER_lut_rw_by_host_MASK__SI 0x00100000L -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_RBBMIF_ready_MASK__SI 0x00010000L -#define ID14_DCP_DMIF_STATUS__ID14_DCP_d1req_pipe_idle_MASK__SI 0x00000001L -#define ID14_DCP_DMIF_STATUS__ID14_DCP_d2req_pipe_idle_MASK__SI 0x00000002L -#define ID14_DCP_DMIF_STATUS__ID15_DMIF_dmif_req_pipe_idle_MASK__SI 0x00010000L -#define ID14_DMIF_STATUS__ID14_DCP_d1req_pipe_idle_MASK__SI 0x00000001L -#define ID14_DMIF_STATUS__ID14_DCP_d2req_pipe_idle_MASK__SI 0x00000002L -#define ID14_DMIF_STATUS__ID15_DMIF_DCP_debug_mc_max_latency_overflow_MASK__SI 0x02000000L -#define ID14_DMIF_STATUS__ID15_DMIF_DCP_debug_mc_min_latency_overflow_MASK__SI 0x01000000L -#define ID14_DMIF_STATUS__ID15_DMIF_dmif_req_pipe_idle_MASK__SI 0x00010000L -#define ID15_DMIF_MC_LATENCY__ID15_DMIF_DCP_debug_mc_max_latency_MASK__SI 0xffff0000L -#define ID15_DMIF_MC_LATENCY__ID15_DMIF_DCP_debug_mc_min_latency_MASK__SI 0x0000ffffL -#define ID16_MCIF_MC_LATENCY__ID16_MCIF_DCP_debug_mc_max_latency_overflow_MASK__SI 0x02000000L -#define ID16_MCIF_MC_LATENCY__ID16_MCIF_DCP_debug_mc_min_latency_overflow_MASK__SI 0x01000000L -#define ID17_MCIF_MC_LATENCY__ID17_MCIF_DCP_debug_mc_max_latency_MASK__SI 0xffff0000L -#define ID17_MCIF_MC_LATENCY__ID17_MCIF_DCP_debug_mc_min_latency_MASK__SI 0x0000ffffL -#define ID18_D1GRPH_PRIMARY_SURFACE_ADDRESS__ID18_D1GRPH_PRIMARY_SURFACE_ADDRESS_MASK__SI \ - 0xffffffffL -#define ID19_D1GRPH_SECONDARY_SURFACE_ADDRESS__ID19_D1GRPH_SECONDARY_SURFACE_ADDRESS_MASK__SI \ - 0xffffffffL -#define ID20_D1OVL_SURFACE_ADDRESS__ID20_D1OVL_SURFACE_ADDRESS_MASK__SI 0xffffffffL -#define ID21_D1GRPH_COMPRESS_SURFACE_ADDRESS__ID21_D1GRPH_COMPRESS_SURFACE_ADDRESS_MASK__SI \ - 0xffffffffL -#define ID22_D1CURSOR_SURFACE_ADDRESS__ID22_D1CURSOR_SURFACE_ADDRESS_MASK__SI 0x0fffffffL -#define ID23_D1ICON_SURFACE_ADDRESS__ID23_D1ICON_SURFACE_ADDRESS_MASK__SI 0x0fffffffL -#define ID30_DCCARB_VIP_R_ADDR__ID30_DCCARB_VIP_R_ADDR_MASK__SI 0xffffffffL -#define ID31_DCCARB_DCT_R_ADDR__ID31_DCCARB_DCT_R_ADDR_MASK__SI 0xffffffffL -#define ID34_DCCARB_FBC_R_ADDR__ID34_DCCARB_FBC_R_ADDR_MASK__SI 0xffffffffL -#define ID35_DCCARB_VGA_W_ADDR__ID35_DCCARB_VGA_W_ADDR_MASK__SI 0xffffffffL -#define ID36_DCCARB_FBC_W_ADDR__ID36_DCCARB_FBC_W_ADDR_MASK__SI 0xffffffffL -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_MC_RDREQ_FREE_MASK__SI 0x00000002L -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_MC_RDREQ_SEND_MASK__SI 0x00000001L -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_TAP_RDNFO_ASK_MASK__SI 0x00000010L -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_TAP_RDNFO_GO_MASK__SI 0x00000020L -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_TAP_RDREQ_SEND_MASK__SI 0x00000008L -#define ID37_MC_IF_DEBUG_01__ID37_MC_DMIF_RDRET_VLD_MASK__SI 0x00000004L -#define ID37_MC_IF_DEBUG_01__ID37_MC_VIP_WRCLEAN_PHASE_MASK__SI 0x00018000L -#define ID37_MC_IF_DEBUG_01__ID37_TAP_DMIF_RDRET_NACK_MASK__SI 0x00000180L -#define ID37_MC_IF_DEBUG_01__ID37_TAP_DMIF_RDRET_VLD_MASK__SI 0x00000040L -#define ID37_MC_IF_DEBUG_01__ID37_TAP_VIP_WRRET_NACK_MASK__SI 0x00600000L -#define ID37_MC_IF_DEBUG_01__ID37_TAP_VIP_WRRET_VLD_MASK__SI 0x00100000L -#define ID37_MC_IF_DEBUG_01__ID37_VIP_MC_WRREQ_FREE_MASK__SI 0x00002000L -#define ID37_MC_IF_DEBUG_01__ID37_VIP_MC_WRREQ_PHASE_MASK__SI 0x00004000L -#define ID37_MC_IF_DEBUG_01__ID37_VIP_MC_WRREQ_SEND_MASK__SI 0x00001000L -#define ID37_MC_IF_DEBUG_01__ID37_VIP_TAP_WRNFO_ASK_MASK__SI 0x00040000L -#define ID37_MC_IF_DEBUG_01__ID37_VIP_TAP_WRNFO_GO_MASK__SI 0x00080000L -#define ID37_MC_IF_DEBUG_01__ID37_VIP_TAP_WRREQ_SEND_MASK__SI 0x00020000L -#define ID38_MC_IF_DEBUG_02__ID38_DMIF_MC_RDREQ_ADDR_MASK__SI 0xffffffffL -#define ID39_MC_IF_DEBUG_03__ID39_DMIF_TAP_RDREQ_ADDR_MASK__SI 0x0fffffffL -#define ID40_MC_IF_DEBUG_04__ID40_VIP_MC_WRREQ_ADDR_MASK__SI 0xffffffffL -#define ID41_MC_IF_DEBUG_05__ID41_VIP_TAP_WRREQ_ADDR_MASK__SI 0x7fffffffL -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_RDREQ_FREE_MASK__SI 0x00000002L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_RDREQ_SEND_MASK__SI 0x00000001L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_WRREQ_FREE_MASK__SI 0x00002000L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_WRREQ_PHASE_MASK__SI 0x00004000L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_WRREQ_SEND_MASK__SI 0x00001000L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_RDNFO_ASK_MASK__SI 0x00000010L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_RDNFO_GO_MASK__SI 0x00000020L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_RDREQ_SEND_MASK__SI 0x00000008L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_WRNFO_ASK_MASK__SI 0x00040000L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_WRNFO_GO_MASK__SI 0x00080000L -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_WRREQ_SEND_MASK__SI 0x00020000L -#define ID42_MC_IF_DEBUG_06__ID42_MC_MCIF_RDRET_VLD_MASK__SI 0x00000004L -#define ID42_MC_IF_DEBUG_06__ID42_MC_MCIF_WRCLEAN_PHASE_MASK__SI 0x00018000L -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_RDRET_NACK_MASK__SI 0x00000180L -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_RDRET_VLD_MASK__SI 0x00000040L -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_WRRET_NACK_MASK__SI 0x00600000L -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_WRRET_VLD_MASK__SI 0x00100000L -#define ID43_MC_IF_DEBUG_07__ID43_MCIF_MC_RDREQ_ADDR_MASK__SI 0xffffffffL -#define ID44_MC_IF_DEBUG_08__ID44_MCIF_TAP_RDREQ_ADDR_MASK__SI 0x0fffffffL -#define ID45_MC_IF_DEBUG_09__ID45_MCIF_MC_WRREQ_ADDR_MASK__SI 0xffffffffL -#define ID46_MC_IF_DEBUG_10__ID46_MCIF_TAP_WRREQ_ADDR_MASK__SI 0x7fffffffL -#define IDCT_AUTH0__AUTH0_MASK__SI 0xffffffffL -#define IDCT_AUTH1__AUTH1_MASK__SI 0xffffffffL -#define IDCT_AUTH2__AUTH2_MASK__SI 0xffffffffL -#define IDCT_AUTH3__AUTH3_MASK__SI 0xffffffffL -#define IDCT_AUTH_CONTROL0__CONTROL0_BITS_MASK__SI 0xffffffffL -#define IDCT_AUTH_CONTROL1__CONTROL1_BITS_MASK__SI 0xffffffffL -#define IDCT_AUTH_CONTROL2__CONTROL2_BITS_MASK__SI 0xffffffffL -#define IDCT_AUTH_CONTROL3__CONTROL3_BITS_MASK__SI 0xffffffffL -#define IDCT_COEF_BASE__IDCT_COEF_MEM_LOCATION_MASK__SI 0xffffffffL -#define IDCT_COEF_DATA__IDCT_COEF_DATA_MASK__SI 0xffffffffL -#define IDCT_CONFIG__IDCT_RDREQ_URG_MASK__SI 0x00000f00L -#define IDCT_CONFIG__IDCT_REQ_TRAN_MASK__SI 0x00010000L -#define IDCT_CONTROL__COEF_FETCH_WATERMARK_MASK__SI 0x3c000000L -#define IDCT_CONTROL__COEF_SWAP_MASK__SI 0x03000000L -#define IDCT_CONTROL__DCT_CORE_BYPASS_MASK__SI 0x00020000L -#define IDCT_CONTROL__DRM_MASK_DEBUG_EN_MASK__SI 0x40000000L -#define IDCT_CONTROL__IDCT_248_MODE_MASK__SI 0x00002000L -#define IDCT_CONTROL__IDCT_CTL_INTRA_MASK__SI 0x00000020L -#define IDCT_CONTROL__IDCT_CTL_SCAN_PATTERN_MASK__SI 0x00000018L -#define IDCT_CONTROL__IDCT_DECRYP_SEL_MASK__SI 0x00000200L -#define IDCT_CONTROL__IDCT_FIELD_ENCODING_MASK__SI 0x00000800L -#define IDCT_CONTROL__IDCT_MISMATCH_CONTROL_MASK__SI 0x00010000L -#define IDCT_CONTROL__IDCT_SCRAMBLE_MASK__SI 0x00000400L -#define IDCT_CONTROL__IDCT_ZERO_ON_ERROR_MASK__SI 0x00001000L -#define IDCT_CURRENT_MB_STATUS_DEBUG__CURRENT_MACROBLOCK_NUMBER_MASK__SI 0x0000ffffL -#define IDCT_DEBUG_00__DEBUG00_SCRAM_IDCT3A_MASK__SI 0x000007ffL -#define IDCT_DEBUG_01__DEBUG01_SCRAM_IDCT3B_MASK__SI 0x000007ffL -#define IDCT_DEBUG_02__DEBUG02_SCRAM_IDCT3C_MASK__SI 0x000007ffL -#define IDCT_DEBUG_03__DEBUG03_SCRAM_IDCT3D_MASK__SI 0x000007ffL -#define IDCT_DEBUG_04__DEBUG04_DEZIGZAG_MASK__SI 0x00000fffL -#define IDCT_DEBUG_05__DEBUG05_INTER_BUF_MASK__SI 0x00000fffL -#define IDCT_DEBUG_06__DEBUG06_OUT_BUF_MASK__SI 0x00000fffL -#define IDCT_DEBUG_0A__DEBUG0A_IDCT_RD_CTRL_DEBUG_1_MASK__SI 0x00000fffL -#define IDCT_DEBUG_0A__DEBUG0A_IDCT_RD_CTRL_DEBUG_2_MASK__SI 0x00fff000L -#define IDCT_DEBUG_0B__DEBUG0B_IDCT_RD_CTRL_DEBUG_3_MASK__SI 0x00000fffL -#define IDCT_DEBUG_0B__DEBUG0B_IDCT_RD_CTRL_DEBUG_4_MASK__SI 0x00fff000L -#define IDCT_DEBUG_0C__DEBUG0C_IDCT_RD_CTRL_DEBUG_5_MASK__SI 0x00000fffL -#define IDCT_DEBUG_0C__DEBUG0C_IDCT_RD_CTRL_DEBUG_6_MASK__SI 0x00fff000L -#define IDCT_DEBUG_18__DEBUG18_IDCT_RD_CTRL_DEBUG_7_MASK__SI 0x00000fffL -#define IDCT_DEBUG_18__DEBUG18_IDCT_RD_CTRL_DEBUG_8_MASK__SI 0x00fff000L -#define IDCT_DEBUG_19__DEBUG19_IDCT_RD_CTRL_DEBUG_10_MASK__SI 0x00fff000L -#define IDCT_DEBUG_19__DEBUG19_IDCT_RD_CTRL_DEBUG_9_MASK__SI 0x00000fffL -#define IDCT_DEBUG_20__DEBUG20_IDCT_RD_CTRL_DEBUG_11_MASK__SI 0x00000fffL -#define IDCT_DEBUG_20__DEBUG20_IDCT_RD_CTRL_DEBUG_12_MASK__SI 0x00fff000L -#define IDCT_DEBUG_21__DEBUG21_IDCT_RD_CTRL_DEBUG_13_MASK__SI 0x00000fffL -#define IDCT_DEBUG_21__DEBUG21_IDCT_RD_CTRL_DEBUG_14_MASK__SI 0x00fff000L -#define IDCT_DEBUG_22__DEBUG22_IDCT_RD_CTRL_DEBUG_15_MASK__SI 0x00000fffL -#define IDCT_DEBUG_23__DEBUG23_IDCT_DRM_IF_DEBUG_1_MASK__SI 0x00000fffL -#define IDCT_DEBUG_23__DEBUG23_IDCT_DRM_IF_DEBUG_2_MASK__SI 0x00fff000L -#define IDCT_DEBUG_24__DEBUG24_IDCT_DRM_IF_DEBUG_3_MASK__SI 0x00000fffL -#define IDCT_DRM_CONTROL_STATUS__DRM_VCPU_FLUSHED_MASK__SI 0x00000001L -#define IDCT_DRM_CONTROL_STATUS__DRM_VCPU_STOP_FLUSH_MASK__SI 0x00000002L -#define IDCT_DRM_WR_CREDIT__DRM_WR_CREDIT_MASK__SI 0x0000003fL -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_00_MASK__SI 0x00000001L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_01_MASK__SI 0x00000002L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_02_MASK__SI 0x00000004L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_03_MASK__SI 0x00000008L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_04_MASK__SI 0x00000010L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_05_MASK__SI 0x00000020L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_06_MASK__SI 0x00000040L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_07_MASK__SI 0x00000080L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_08_MASK__SI 0x00000100L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_09_MASK__SI 0x00000200L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_10_MASK__SI 0x00000400L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_11_MASK__SI 0x00000800L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_12_MASK__SI 0x00001000L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_13_MASK__SI 0x00002000L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_14_MASK__SI 0x00004000L -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_15_MASK__SI 0x00008000L -#define IDCT_IDLE_DEBUG__CMDIF_CTRL_IDLE_STAT_MASK__SI 0x00000400L -#define IDCT_IDLE_DEBUG__DEZIGZAG_IDLE_STAT_MASK__SI 0x10000000L -#define IDCT_IDLE_DEBUG__DRM_IF_IDLE_STAT_MASK__SI 0x40000000L -#define IDCT_IDLE_DEBUG__IDCT_END_OF_STREAM_STAT_MASK__SI 0x00000010L -#define IDCT_IDLE_DEBUG__IDCT_IDLE_STAT_MASK__SI 0x00000001L -#define IDCT_IDLE_DEBUG__INTER_BUF_IDLE_STAT_MASK__SI 0x08000000L -#define IDCT_IDLE_DEBUG__OUT_BUF_IDLE_STAT_MASK__SI 0x04000000L -#define IDCT_IDLE_DEBUG__XDCT_COEF_RDER_IDLE_STAT_MASK__SI 0x02000000L -#define IDCT_PIO_MODE_XY__IDCT_PIO_SCREEN_X_MASK__SI 0x00000fffL -#define IDCT_PIO_MODE_XY__IDCT_PIO_SCREEN_Y_MASK__SI 0x0fff0000L -#define IDCT_SCRAMBLE_SELECT__IDCT_SCRAMBLE_SELECT_MASK__SI 0x00000003L -#define IDCT_SCRATCH__IDCT_SCRATCH_MASK__SI 0xffffffffL -#define IDCT_SPAN__IDCT_SPAN_MASK__SI 0x000007ffL -#define IDCT_STATUS__IDCT_ERROR_00_MASK__SI 0x00000001L -#define IDCT_STATUS__IDCT_ERROR_01_MASK__SI 0x00000002L -#define IDCT_STATUS__IDCT_ERROR_02_MASK__SI 0x00000004L -#define IDCT_STATUS__IDCT_ERROR_03_MASK__SI 0x00000008L -#define IDCT_STATUS__IDCT_ERROR_04_MASK__SI 0x00000010L -#define IDCT_STATUS__IDCT_ERROR_05_MASK__SI 0x00000020L -#define IDCT_STATUS__IDCT_ERROR_06_MASK__SI 0x00000040L -#define IDCT_STATUS__IDCT_ERROR_07_MASK__SI 0x00000080L -#define IDCT_STATUS__IDCT_ERROR_08_MASK__SI 0x00000100L -#define IDCT_STATUS__IDCT_ERROR_09_MASK__SI 0x00000200L -#define IDCT_STATUS__IDCT_ERROR_10_MASK__SI 0x00000400L -#define IDCT_STATUS__IDCT_ERROR_11_MASK__SI 0x00000800L -#define IDCT_STATUS__IDCT_ERROR_12_MASK__SI 0x00001000L -#define IDCT_STATUS__IDCT_ERROR_13_MASK__SI 0x00002000L -#define IDCT_STATUS__IDCT_ERROR_14_MASK__SI 0x00004000L -#define IDCT_STATUS__IDCT_ERROR_15_MASK__SI 0x00008000L -#define IDCT_STATUS__IDCT_IDLE_MASK__SI 0x80000000L -#define IDCT_STATUS__IDCT_PIO_READY_MASK__SI 0x40000000L -#define IDCT_STREAM_ID__STREAM_ID_MASK__SI 0x0000000fL -#define IDCT_TEST_DEBUG_DATA__IDCT_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define IDCT_TEST_DEBUG_INDEX__IDCT_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define IDDCCIF00_DBG_DCCIF_A__DBG_DCCIF_A_MASK__SI 0xffffffffL -#define IDDCCIF01_DBG_DCCIF_B__DBG_DCCIF_B_MASK__SI 0xffffffffL -#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK__SI 0xffffffffL -#define IDDCCIF03_DBG_DCCIF_D__DBG_DCCIF_D_MASK__SI 0xffffffffL -#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK__SI 0xffffffffL -#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK__SI 0xffffffffL -#define IDDCCIF06_DBG_DCCIF_G__DBG_DCCIF_G_MASK__SI 0xffffffffL -#define IDDCCIF07_DBG_DCCIF_H__DBG_DCCIF_H_MASK__SI 0xffffffffL -#define IDDCCIF08_DBG_DCCIF_I__DBG_DCCIF_I_MASK__SI 0xffffffffL -#define IDDCCIF09_DBG_DCCIF_J__DBG_DCCIF_J_MASK__SI 0xffffffffL -#define IDDCCIF10_DBG_DCCIF_K__DBG_DCCIF_K_MASK__SI 0xffffffffL -#define IDDCCIF11_DBG_DCCIF_L__DBG_DCCIF_L_MASK__SI 0xffffffffL -#define IDSC_REG__CLK_SELECT_MASK__CI 0x40000000L -#define IDSC_REG__CMON_ADC_DOUT_MASK__CI 0x3ff00000L -#define IDSC_REG__CMON_ADC_MAX_MASK__CI 0x000003ffL -#define IDSC_REG__CMON_ADC_MIN_MASK__CI 0x000ffc00L -#define IDSC_REG__FULL_TEST_MODE_MASK__CI 0x80000000L -#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK__SI__CI 0x0000ff00L -#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK__SI__CI 0x3fff0000L -#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK__SI__CI 0x00000008L -#define IH_ADVFAULT_CNTL__WATERMARK_MASK__SI__CI 0x00000007L -#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK__SI__CI 0x00000010L -#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x00000300L -#define IH_CNTL__ENABLE_INTR_MASK 0x00000001L -#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x00007c00L -#define IH_CNTL__MC_SWAP_MASK 0x00000006L -#define IH_CNTL__MC_TRAN_MASK__SI__CI 0x00000008L -#define IH_CNTL__MC_VMID_MASK__CI__VI 0x1e000000L -#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0x000f8000L -#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L -#define IH_CNTL__RPTR_REARM_MASK 0x00000010L -#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x00000010L -#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x00000001L -#define IH_LEVEL_STATUS__DRM_STATUS_MASK 0x00000002L -#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x00000004L -#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x00000008L -#define IH_LEVEL_STATUS__XDMA_STATUS_MASK__CI__VI 0x00000020L -#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK__CI__VI 0xffffffffL -#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK__CI__VI 0xffffffffL -#define IH_PERFMON_CNTL__CLEAR0_MASK__CI__VI 0x00000002L -#define IH_PERFMON_CNTL__CLEAR1_MASK__CI__VI 0x00000200L -#define IH_PERFMON_CNTL__ENABLE0_MASK__CI__VI 0x00000001L -#define IH_PERFMON_CNTL__ENABLE1_MASK__CI__VI 0x00000100L -#define IH_PERFMON_CNTL__PERF_SEL0_MASK__CI__VI 0x000000fcL -#define IH_PERFMON_CNTL__PERF_SEL1_MASK__CI__VI 0x0000fc00L -#define IH_PERF_CNTL__CLEAR0_MASK__SI 0x00000002L -#define IH_PERF_CNTL__CLEAR1_MASK__SI 0x00000200L -#define IH_PERF_CNTL__ENABLE0_MASK__SI 0x00000001L -#define IH_PERF_CNTL__ENABLE1_MASK__SI 0x00000100L -#define IH_PERF_CNTL__SELECT0_MASK__SI 0x0000007cL -#define IH_PERF_CNTL__SELECT1_MASK__SI 0x00007c00L -#define IH_PERF_COUNT0__PERF_COUNT_MASK__SI 0xffffffffL -#define IH_PERF_COUNT1__PERF_COUNT_MASK__SI 0xffffffffL -#define IH_RB_BASE__ADDR_MASK 0xffffffffL -#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000040L -#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L -#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L -#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L -#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L -#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L -#define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL -#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL -#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL -#define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL -#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L -#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L -#define IH_STATUS__IDLE_MASK 0x00000001L -#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L -#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L -#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L -#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L -#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L -#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L -#define IH_STATUS__RB_FULL_MASK 0x00000008L -#define IH_STATUS__RB_IDLE_MASK 0x00000004L -#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L -#define IH_VMID_0_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_10_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_11_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_12_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_13_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_14_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_15_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_1_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_2_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_3_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_4_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_5_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_6_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_7_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_8_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IH_VMID_9_LUT__PASID_MASK__CI__VI 0x0000ffffL -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK__SI 0xffffffffL -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK__SI 0x0000ffffL -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK__SI \ - 0xf0000000L -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK__SI \ - 0x0fffffffL -#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK__SI 0x00000001L -#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK__SI 0x00000002L -#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK__SI 0xffffffffL -#define IMPCTL_RESET__IMP_SW_RESET_MASK__CI__VI 0x00000001L -#define IM_INT_EN__CM_INT_EN_MASK__SI 0x00000004L -#define IM_INT_EN__DB_INT_EN_MASK__SI 0x00000040L -#define IM_INT_EN__IT_INT_EN_MASK__SI 0x00000010L -#define IM_INT_EN__MI_INT_EN_MASK__SI 0x00000002L -#define IM_INT_EN__MP_INT_EN_MASK__SI 0x00000020L -#define IM_INT_EN__PES_INT_EN_MASK__SI 0x00000080L -#define IM_INT_EN__RE_INT_EN_MASK__SI 0x00000008L -#define IM_INT_EN__RI_INT_EN_MASK__SI 0x00000001L -#define IM_INT_STAT__CM_INT_MASK__SI 0x00000004L -#define IM_INT_STAT__DB_INT_MASK__SI 0x00000040L -#define IM_INT_STAT__IT_INT_MASK__SI 0x00000010L -#define IM_INT_STAT__MI_INT_MASK__SI 0x00000002L -#define IM_INT_STAT__MP_INT_MASK__SI 0x00000020L -#define IM_INT_STAT__PES_INT_MASK__SI 0x00000080L -#define IM_INT_STAT__RE_INT_MASK__SI 0x00000008L -#define IM_INT_STAT__RI_INT_MASK__SI 0x00000001L -#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK__SI 0x0000ffffL -#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffffL -#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x00001e00L -#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L -#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L -#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L -#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000f0L -#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L -#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x00006000L -#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK__SI 0x40000000L -#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK__SI 0x80000000L -#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE_MASK__SI 0x00000001L -#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0x000000ffL -#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0x000000ffL -#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK__SI 0x40000000L -#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK__SI 0x80000000L -#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS_MASK__SI 0x00000001L -#define INT_MASK__VBLANK_CP_SEL_MASK__SI 0x40000000L -#define INT_MASK__VBLANK_INT_MASK_MASK__SI 0x00000001L -#define INT_MASK__VLINE_INT_MASK_MASK__SI 0x00000010L -#define IOU_MISC_STATUS__IOC_GPU_DIS_MASK__CI__VI 0x00000001L -#define IOU_SMC_IND_DATA__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define IOU_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define IT_BUF_SIZE__PITCH_MASK__SI 0x00000ff0L -#define IT_CF_DAT__COMMAND_DAT_MASK__SI 0xffffffffL -#define IT_CTL__FLUSH_MB_MASK__SI 0x10000000L -#define IT_CTL__MEM_TIMEOUT_MASK__SI 0x0ff00000L -#define IT_CTL__NSG_MODE_MASK__SI 0x00000030L -#define IT_CTL__STANDARD_MASK__SI 0x0000000fL -#define IT_CTL__STD_VERSION_MASK__SI 0x000f0000L -#define IT_CTL__SW_MRST_MASK__SI 0x40000000L -#define IT_CTL__SW_RRST_MASK__SI 0x20000000L -#define IT_CTL__SW_SRST_MASK__SI 0x80000000L -#define IT_CTL__TBYPS_MASK__SI 0x00000040L -#define IT_DEBUG_BUS__DAT_MASK__SI 0xffffffffL -#define IT_DEBUG_INT_STAT__CTXT_READ_RDY_MASK__SI 0x00000004L -#define IT_DEBUG_INT_STAT__CTXT_READ_TIMEOUT_MASK__SI 0x00000020L -#define IT_DEBUG_INT_STAT__CTXT_WRITE_DONE_MASK__SI 0x00000008L -#define IT_DEBUG_INT_STAT__CTXT_WRITE_TIMEOUT_MASK__SI 0x00000040L -#define IT_DEBUG_INT_STAT__DONE_MASK__SI 0x00000001L -#define IT_DEBUG_INT_STAT__HOR_CHROMAPRED_ERR_MASK__SI 0x00002000L -#define IT_DEBUG_INT_STAT__HOR_PRED16_ERR_MASK__SI 0x00000400L -#define IT_DEBUG_INT_STAT__ILLEGAL_4X4_PREDMODE_ERR_MASK__SI 0x00000100L -#define IT_DEBUG_INT_STAT__ILLEGAL_CHROMAPRED_ERR_MASK__SI 0x00008000L -#define IT_DEBUG_INT_STAT__MB_PROC_DONE_MASK__SI 0x00000002L -#define IT_DEBUG_INT_STAT__MEM_READ_TIMEOUT_MASK__SI 0x00000010L -#define IT_DEBUG_INT_STAT__MEM_WRITE_TIMEOUT_MASK__SI 0x00010000L -#define IT_DEBUG_INT_STAT__PLANE_CHROMAPRED_ERR_MASK__SI 0x00001000L -#define IT_DEBUG_INT_STAT__PLANE_PRED16_ERR_MASK__SI 0x00000800L -#define IT_DEBUG_INT_STAT__RD_NEIGHBOUR_ERR_MASK__SI 0x00000080L -#define IT_DEBUG_INT_STAT__RE_IT_OVERFLOW_ERR_MASK__SI 0x00040000L -#define IT_DEBUG_INT_STAT__RE_IT_UNDERFLOW_ERR_MASK__SI 0x00020000L -#define IT_DEBUG_INT_STAT__VERT_CHROMAPRED_ERR_MASK__SI 0x00004000L -#define IT_DEBUG_INT_STAT__VERT_PRED16_ERR_MASK__SI 0x00000200L -#define IT_HW_DEBUG__DAT_MASK__SI 0xffffffffL -#define IT_INTRA_HOR_ADR__HOR_ADR_RESERVE_HI_MASK__SI 0xc0000000L -#define IT_INTRA_HOR_ADR__HOR_ADR_RESERVE_LO_MASK__SI 0x0000003fL -#define IT_INTRA_HOR_ADR__INTRA_HOR_ADR_MASK__SI 0x3fffffc0L -#define IT_INT_EN__CTXT_READ_RDY_EN_MASK__SI 0x00000004L -#define IT_INT_EN__CTXT_READ_TIMEOUT_EN_MASK__SI 0x00000020L -#define IT_INT_EN__CTXT_WRITE_DONE_EN_MASK__SI 0x00000008L -#define IT_INT_EN__CTXT_WRITE_TIMEOUT_EN_MASK__SI 0x00000040L -#define IT_INT_EN__DONE_EN_MASK__SI 0x00000001L -#define IT_INT_EN__HOR_CHROMAPRED_ERR_EN_MASK__SI 0x00002000L -#define IT_INT_EN__HOR_PRED16_ERR_EN_MASK__SI 0x00000400L -#define IT_INT_EN__ILLEGAL_4X4_PREDMODE_ERR_EN_MASK__SI 0x00000100L -#define IT_INT_EN__ILLEGAL_CHROMAPRED_ERR_EN_MASK__SI 0x00008000L -#define IT_INT_EN__MB_PROC_DONE_EN_MASK__SI 0x00000002L -#define IT_INT_EN__MEM_READ_TIMEOUT_EN_MASK__SI 0x00000010L -#define IT_INT_EN__MEM_WRITE_TIMEOUT_EN_MASK__SI 0x00010000L -#define IT_INT_EN__PLANE_CHROMAPRED_ERR_EN_MASK__SI 0x00001000L -#define IT_INT_EN__PLANE_PRED16_ERR_EN_MASK__SI 0x00000800L -#define IT_INT_EN__RD_NEIGHBOUR_ERR_EN_MASK__SI 0x00000080L -#define IT_INT_EN__RE_IT_OVERFLOW_ERR_EN_MASK__SI 0x00040000L -#define IT_INT_EN__RE_IT_UNDERFLOW_ERR_EN_MASK__SI 0x00020000L -#define IT_INT_EN__VERT_CHROMAPRED_ERR_EN_MASK__SI 0x00004000L -#define IT_INT_EN__VERT_PRED16_ERR_EN_MASK__SI 0x00000200L -#define IT_INT_STAT__CTXT_READ_RDY_MASK__SI 0x00000004L -#define IT_INT_STAT__CTXT_READ_TIMEOUT_MASK__SI 0x00000020L -#define IT_INT_STAT__CTXT_WRITE_DONE_MASK__SI 0x00000008L -#define IT_INT_STAT__CTXT_WRITE_TIMEOUT_MASK__SI 0x00000040L -#define IT_INT_STAT__DONE_MASK__SI 0x00000001L -#define IT_INT_STAT__HOR_CHROMAPRED_ERR_MASK__SI 0x00002000L -#define IT_INT_STAT__HOR_PRED16_ERR_MASK__SI 0x00000400L -#define IT_INT_STAT__ILLEGAL_4X4_PREDMODE_ERR_MASK__SI 0x00000100L -#define IT_INT_STAT__ILLEGAL_CHROMAPRED_ERR_MASK__SI 0x00008000L -#define IT_INT_STAT__MB_PROC_DONE_MASK__SI 0x00000002L -#define IT_INT_STAT__MEM_READ_TIMEOUT_MASK__SI 0x00000010L -#define IT_INT_STAT__MEM_WRITE_TIMEOUT_MASK__SI 0x00010000L -#define IT_INT_STAT__PLANE_CHROMAPRED_ERR_MASK__SI 0x00001000L -#define IT_INT_STAT__PLANE_PRED16_ERR_MASK__SI 0x00000800L -#define IT_INT_STAT__RD_NEIGHBOUR_ERR_MASK__SI 0x00000080L -#define IT_INT_STAT__RE_IT_OVERFLOW_ERR_MASK__SI 0x00040000L -#define IT_INT_STAT__RE_IT_UNDERFLOW_ERR_MASK__SI 0x00020000L -#define IT_INT_STAT__VERT_CHROMAPRED_ERR_MASK__SI 0x00004000L -#define IT_INT_STAT__VERT_PRED16_ERR_MASK__SI 0x00000200L -#define IT_LMA_ADR__LMA_ADR_MASK__SI 0x000000ffL -#define IT_LMA_CTL__ACCESS_MODE_MASK__SI 0x00000001L -#define IT_LMA_CTL__AUTO_INCREMENT_MASK__SI 0x00000040L -#define IT_LMA_CTL__MEMORY_SELECT_MASK__SI 0x0000003eL -#define IT_LMA_DAT__LMA_DAT_MASK__SI 0x000000ffL -#define IT_PPS_INFO__CONSTRAINED_INTRA_PRED_FLAG_MASK__SI 0x00000001L -#define IT_PPS_INFO__FCM_MASK__SI 0x00006000L -#define IT_PPS_INFO__FMO_MASK__SI 0x00001000L -#define IT_PPS_INFO__INTERLACED_MASK__SI 0x00000800L -#define IT_PPS_INFO__NON_UNIFORM_MASK__SI 0x00000080L -#define IT_PPS_INFO__PQUANT_MASK__SI 0x0000007eL -#define IT_PPS_INFO__PTYPE_MASK__SI 0x00000700L -#define IT_SLICE_INFO__MBAFF_FRAME_FLAG_MASK__SI 0x00000001L -#define IT_SPS_INFO__CHROMA_FORMAT_IDC_MASK__SI 0x10000000L -#define IT_SPS_INFO__PIC_HEIGHT_MASK__SI 0x0fff0000L -#define IT_SPS_INFO__PIC_WIDTH_MASK__SI 0x00000fffL -#define IT_SPS_INFO__PROFILE_MASK__SI 0x60000000L -#define IT_SRAM_RM_CTL__IT_M032X064R2M01S00_RME_MASK__SI 0x00000200L -#define IT_SRAM_RM_CTL__IT_M032X064R2M01S00_RM_MASK__SI 0x000001e0L -#define IT_SRAM_RM_CTL__IT_M128X016R2M01S00_RME_MASK__SI 0x00080000L -#define IT_SRAM_RM_CTL__IT_M128X016R2M01S00_RM_MASK__SI 0x00078000L -#define IT_SRAM_RM_CTL__IT_M224X008H1M08S00_RME_MASK__SI 0x00000010L -#define IT_SRAM_RM_CTL__IT_M224X008H1M08S00_RM_MASK__SI 0x0000000fL -#define IT_SRAM_RM_CTL__IT_M384X010R2M04S00_RME_MASK__SI 0x00004000L -#define IT_SRAM_RM_CTL__IT_M384X010R2M04S00_RM_MASK__SI 0x00003c00L -#define IT_SRAM_RM_CTL__IT_WRM_MASK__SI 0x00f00000L -#define IT_STAT__CTXT_RD_BUSY_MASK__SI 0x00000008L -#define IT_STAT__DECODE_MBP_BUSY_MASK__SI 0x00000002L -#define IT_STAT__DECODE_TPACKET_BUSY_MASK__SI 0x00000001L -#define IT_STAT__IPRED_CHROMA_PEL_BUSY_MASK__SI 0x00000080L -#define IT_STAT__IPRED_CHROMA_PRED_BUSY_MASK__SI 0x00000100L -#define IT_STAT__IPRED_LUMA_PEL_BUSY_MASK__SI 0x00000020L -#define IT_STAT__IPRED_LUMA_PRED_BUSY_MASK__SI 0x00000040L -#define IT_STAT__OUTPUT_BUSY_MASK__SI 0x00000200L -#define IT_STAT__PREFETCH_BUSY_MASK__SI 0x00000400L -#define IT_STAT__RUN_BUSY_MASK__SI 0x00000004L -#define IT_STAT__TRANS_CHROMA_BUSY_MASK__SI 0x00000010L -#define IT_STAT__VC1_COMPUTE_BUSY_MASK__SI 0x00000800L -#define IT_STAT__VC1_MEMWRITE_BUSY_MASK__SI 0x00001000L -#define KEFUSE0__RESERVED_MASK 0xffffffffL -#define KEFUSE1__RESERVED_MASK 0xffffffffL -#define KEFUSE2__RESERVED_MASK 0xffffffffL -#define KEFUSE3__RESERVED_MASK 0xffffffffL -#define KHFS0__RESERVED_MASK 0xffffffffL -#define KHFS1__RESERVED_MASK 0xffffffffL -#define KHFS2__RESERVED_MASK 0xffffffffL -#define KHFS3__RESERVED_MASK 0xffffffffL -#define KSESSION0__RESERVED_MASK 0xffffffffL -#define KSESSION1__RESERVED_MASK 0xffffffffL -#define KSESSION2__RESERVED_MASK 0xffffffffL -#define KSESSION3__RESERVED_MASK 0xffffffffL -#define KSIG0__RESERVED_MASK 0xffffffffL -#define KSIG1__RESERVED_MASK 0xffffffffL -#define KSIG2__RESERVED_MASK 0xffffffffL -#define KSIG3__RESERVED_MASK 0xffffffffL -#define LATENCY__LATENCY_TIMER_MASK 0x000000ffL -#define LB_DCP_WRITE__ID92_DATA_AVAIL_MASK__SI 0x00000080L -#define LB_DCP_WRITE__ID92_DCP_DISP_NUM_MASK__SI 0x00040000L -#define LB_DCP_WRITE__ID92_DCP_TAG_MASK__SI 0x00007000L -#define LB_DCP_WRITE__ID92_EOC_MASK__SI 0x00080000L -#define LB_DCP_WRITE__ID92_EOC_W_MASK__SI 0x00008000L -#define LB_DCP_WRITE__ID92_FIFO_READ_SEL_MASK__SI 0x00000400L -#define LB_DCP_WRITE__ID92_IGNORE_MASK__SI 0x00000004L -#define LB_DCP_WRITE__ID92_LB_DISP_NUM_MASK__SI 0x00020000L -#define LB_DCP_WRITE__ID92_REQ_MASK__SI 0x00010000L -#define LB_DCP_WRITE__ID92_ROW_ADR_MASK__SI 0x00000002L -#define LB_DCP_WRITE__ID92_ROW_READ_SEL_MASK__SI 0x00000200L -#define LB_DCP_WRITE__ID92_SEND_MASK__SI 0x00000008L -#define LB_DCP_WRITE__ID92_SOF1_MASK__SI 0x00000001L -#define LB_DCP_WRITE__ID92_SOF2_MASK__SI 0x00000800L -#define LB_DCP_WRITE__ID92_WEN_MASK__SI 0x00000100L -#define LB_DCP_WRITE__ID92_WORD_ADR_MASK__SI 0x00000070L -#define LB_DCP_WRITE__ID92_WRITE_ADR_MASK__SI 0xfff00000L -#define LB_DEBUG_ID__LB_DEBUG_ID_MASK__SI 0xffffffffL -#define LB_DEBUG_PRE_ECO__DISABLE_LB_MEM_ADR_CLAMPING_MASK__SI 0x00001000L -#define LB_DEBUG_PRE_ECO__DISABLE_LB_RTR_USE_MEM_LEVEL_OLD_MASK__SI 0x00000020L -#define LB_DEBUG_PRE_ECO__DISABLE_NEW_LEVEL_MASK__SI 0x00000010L -#define LB_DEBUG_PRE_ECO__DISABLE_NEW_WCONTROL_INTERLEAVE_MASK__SI 0x00000001L -#define LB_DEBUG_PRE_ECO__DISABLE_NEW_WPOINTER_MASK__SI 0x00000100L -#define LB_DEBUG_PRE_ECO__DISABLE_RND_SCR_SCALE_EN_MASK__SI 0x00010000L -#define LB_DEBUG_PRE_ECO__LB_DEBUG_PRE_ECO_MASK__SI 0xfffe0000L -#define LB_DEBUG__LB_DEBUG_MASK__SI 0xffffffffL -#define LB_DISP1_ALU__ID95_DISP1_EOL_Q_MASK__SI 0x00000001L -#define LB_DISP1_ALU__ID95_DISP1_LC_FRAME_BUSY_MASK__SI 0x00000010L -#define LB_DISP1_ALU__ID95_DISP1_LC_FRAME_DONE_MASK__SI 0x00000100L -#define LB_DISP1_ALU__ID95_DISP1_LC_LINE_BUSY_MASK__SI 0x00000008L -#define LB_DISP1_ALU__ID95_DISP1_LC_LINE_DONE_MASK__SI 0x00000080L -#define LB_DISP1_ALU__ID95_DISP1_RT_FRAME_CAL_BUSY_MASK__SI 0x00000004L -#define LB_DISP1_ALU__ID95_DISP1_RT_FRAME_CAL_DONE_MASK__SI 0x00000040L -#define LB_DISP1_ALU__ID95_DISP1_RT_LINE_CAL_BUSY_MASK__SI 0x00000002L -#define LB_DISP1_ALU__ID95_DISP1_RT_LINE_CAL_DONE_MASK__SI 0x00000020L -#define LB_DISP1_ALU__ID95_DISP1_SOF_MASK__SI 0x00001000L -#define LB_DISP1_ALU__ID95_DISP1_STATE_MASK__SI 0x00000e00L -#define LB_DISP1_ALU__ID95_DISP1_SUM_MASK__SI 0xfffe0000L -#define LB_DISP1_ALU__ID95_DISP1_S_MASK__SI 0x0001e000L -#define LB_DISP1_PARAM__ID97_DISP1_END_SIZE_MASK__SI 0x00070000L -#define LB_DISP1_PARAM__ID97_DISP1_END_TAP_CYCLE_MASK__SI 0x20000000L -#define LB_DISP1_PARAM__ID97_DISP1_LAST_LINE_MASK__SI 0x40000000L -#define LB_DISP1_PARAM__ID97_DISP1_NUMS_LINE_AVAIL_MASK__SI 0x00003800L -#define LB_DISP1_PARAM__ID97_DISP1_PITCH_MASK__SI 0x000007ffL -#define LB_DISP1_PARAM__ID97_DISP1_READ_CYCLE_MASK__SI 0x00008000L -#define LB_DISP1_PARAM__ID97_DISP1_READ_PIXEL_COUNTER_MASK__SI 0x0f000000L -#define LB_DISP1_PARAM__ID97_DISP1_SEND_FOR_THE_NXT_LINE_MASK__SI 0x80000000L -#define LB_DISP1_PARAM__ID97_DISP1_SEND_MASK__SI 0x10000000L -#define LB_DISP1_PARAM__ID97_DISP1_SOF_MASK__SI 0x00080000L -#define LB_DISP1_PARAM__ID97_DISP1_WRITE_CYCLE_MASK__SI 0x00004000L -#define LB_DISP1_PARAM__ID97_DISP1_WRITE_PIXEL_COUNTER_MASK__SI 0x00f00000L -#define LB_DISP1_REQ__ID90_DISP1_CHUNCK_LOC_STATE_MASK__SI 0x00000600L -#define LB_DISP1_REQ__ID90_DISP1_DCP_ACK_MASK__SI 0x10000000L -#define LB_DISP1_REQ__ID90_DISP1_EOL_MASK__SI 0x00000008L -#define LB_DISP1_REQ__ID90_DISP1_INIT_MASK__SI 0x40000000L -#define LB_DISP1_REQ__ID90_DISP1_NUM_LINE_TOBE_SERVICED_MASK__SI 0x000000e0L -#define LB_DISP1_REQ__ID90_DISP1_PULSE_ALL_LINE_SERV_MASK__SI 0x80000000L -#define LB_DISP1_REQ__ID90_DISP1_READ_POINTER_MASK__SI 0x000fc000L -#define LB_DISP1_REQ__ID90_DISP1_REQ_MASK__SI 0x00000100L -#define LB_DISP1_REQ__ID90_DISP1_REQ_POINTER_MASK__SI 0x07f00000L -#define LB_DISP1_REQ__ID90_DISP1_RESET_REQ_MASK__SI 0x08000000L -#define LB_DISP1_REQ__ID90_DISP1_SOF_MASK__SI 0x00000010L -#define LB_DISP1_REQ__ID90_DISP1_TAG_MASK__SI 0x00003800L -#define LB_DISP1_REQ__ID90_DISP1_TAP_SHIFT_MASK__SI 0x00000007L -#define LB_DISP2_ALU__ID96_DISP2_EOL_Q_MASK__SI 0x00000001L -#define LB_DISP2_ALU__ID96_DISP2_LC_FRAME_BUSY_MASK__SI 0x00000010L -#define LB_DISP2_ALU__ID96_DISP2_LC_FRAME_DONE_MASK__SI 0x00000100L -#define LB_DISP2_ALU__ID96_DISP2_LC_LINE_BUSY_MASK__SI 0x00000008L -#define LB_DISP2_ALU__ID96_DISP2_LC_LINE_DONE_MASK__SI 0x00000080L -#define LB_DISP2_ALU__ID96_DISP2_RT_FRAME_CAL_BUSY_MASK__SI 0x00000004L -#define LB_DISP2_ALU__ID96_DISP2_RT_FRAME_CAL_DONE_MASK__SI 0x00000040L -#define LB_DISP2_ALU__ID96_DISP2_RT_LINE_CAL_BUSY_MASK__SI 0x00000002L -#define LB_DISP2_ALU__ID96_DISP2_RT_LINE_CAL_DONE_MASK__SI 0x00000020L -#define LB_DISP2_ALU__ID96_DISP2_SOF_MASK__SI 0x00001000L -#define LB_DISP2_ALU__ID96_DISP2_STATE_MASK__SI 0x00000e00L -#define LB_DISP2_ALU__ID96_DISP2_SUM_MASK__SI 0xfffe0000L -#define LB_DISP2_ALU__ID96_DISP2_S_MASK__SI 0x0001e000L -#define LB_DISP2_PARAM__ID98_DISP2_END_SIZE_MASK__SI 0x00070000L -#define LB_DISP2_PARAM__ID98_DISP2_END_TAP_CYCLE_MASK__SI 0x20000000L -#define LB_DISP2_PARAM__ID98_DISP2_LAST_LINE_MASK__SI 0x40000000L -#define LB_DISP2_PARAM__ID98_DISP2_NUMS_LINE_AVAIL_MASK__SI 0x00003800L -#define LB_DISP2_PARAM__ID98_DISP2_PITCH_MASK__SI 0x000007ffL -#define LB_DISP2_PARAM__ID98_DISP2_READ_CYCLE_MASK__SI 0x00008000L -#define LB_DISP2_PARAM__ID98_DISP2_READ_PIXEL_COUNTER_MASK__SI 0x0f000000L -#define LB_DISP2_PARAM__ID98_DISP2_SEND_FOR_THE_NXT_LINE_MASK__SI 0x80000000L -#define LB_DISP2_PARAM__ID98_DISP2_SEND_MASK__SI 0x10000000L -#define LB_DISP2_PARAM__ID98_DISP2_SOF_MASK__SI 0x00080000L -#define LB_DISP2_PARAM__ID98_DISP2_WRITE_CYCLE_MASK__SI 0x00004000L -#define LB_DISP2_PARAM__ID98_DISP2_WRITE_PIXEL_COUNTER_MASK__SI 0x00f00000L -#define LB_DISP2_REQ__ID91_DISP2_CHUNCK_LOC_STATE_MASK__SI 0x00000600L -#define LB_DISP2_REQ__ID91_DISP2_DCP_ACK_MASK__SI 0x10000000L -#define LB_DISP2_REQ__ID91_DISP2_EOL_MASK__SI 0x00000008L -#define LB_DISP2_REQ__ID91_DISP2_INIT_MASK__SI 0x40000000L -#define LB_DISP2_REQ__ID91_DISP2_NUM_LINE_TOBE_SERVICED_MASK__SI 0x000000e0L -#define LB_DISP2_REQ__ID91_DISP2_PULSE_ALL_LINE_SERV_MASK__SI 0x80000000L -#define LB_DISP2_REQ__ID91_DISP2_READ_POINTER_MASK__SI 0x000fc000L -#define LB_DISP2_REQ__ID91_DISP2_REQ_MASK__SI 0x00000100L -#define LB_DISP2_REQ__ID91_DISP2_REQ_POINTER_MASK__SI 0x07f00000L -#define LB_DISP2_REQ__ID91_DISP2_RESET_REQ_MASK__SI 0x08000000L -#define LB_DISP2_REQ__ID91_DISP2_SOF_MASK__SI 0x00000010L -#define LB_DISP2_REQ__ID91_DISP2_TAG_MASK__SI 0x00003800L -#define LB_DISP2_REQ__ID91_DISP2_TAP_SHIFT_MASK__SI 0x00000007L -#define LB_MAX_REQ_OUTSTANDING__LB_MAX_REQ_OUTSTANDING_MASK__SI 0x0000000fL -#define LB_MCLK_CHG_DBG1__IDA3_DC_CG_DISP1_WM_MCLK_CHG_CNT_OVERFLOW_MASK__SI 0x80000000L -#define LB_MCLK_CHG_DBG1__IDA3_DC_CG_DISP1_WM_MCLK_CHG_MAX_CNT_MASK__SI 0x0000ffffL -#define LB_MCLK_CHG_DBG1__IDA3_DC_CG_DISP1_WM_MCLK_CHG_MIN_CNT_MASK__SI 0x7fff0000L -#define LB_MCLK_CHG_DBG2__IDA4_DC_CG_DISP2_WM_MCLK_CHG_CNT_OVERFLOW_MASK__SI 0x80000000L -#define LB_MCLK_CHG_DBG2__IDA4_DC_CG_DISP2_WM_MCLK_CHG_MAX_CNT_MASK__SI 0x0000ffffL -#define LB_MCLK_CHG_DBG2__IDA4_DC_CG_DISP2_WM_MCLK_CHG_MIN_CNT_MASK__SI 0x7fff0000L -#define LB_MVP_DEBUG1__IDE7_CRTC1_LB_MVP_AFR_HSYNC_SWITCH_DONE_MASK__SI 0x00002000L -#define LB_MVP_DEBUG1__IDE7_D1_AFR_FIFO_EMPTY_COND_MASK__SI 0x40000000L -#define LB_MVP_DEBUG1__IDE7_D1_AFR_FIFO_EMPTY_MASK__SI 0x10000000L -#define LB_MVP_DEBUG1__IDE7_D1_FLIP_NOW_MASK__SI 0x00400000L -#define LB_MVP_DEBUG1__IDE7_D1_FLIP_NOW_OCCURRED1_MASK__SI 0x00000400L -#define LB_MVP_DEBUG1__IDE7_D1_FLIP_REQUEST_MASK__SI 0x00010000L -#define LB_MVP_DEBUG1__IDE7_D1_HSYNC_FLIP_NOW_MASK__SI 0x00000040L -#define LB_MVP_DEBUG1__IDE7_D1_SWAP_LOCK_IN_MASK__SI 0x00100000L -#define LB_MVP_DEBUG1__IDE7_D1_SWAP_LOCK_MASK__SI 0x00000001L -#define LB_MVP_DEBUG1__IDE7_D1_SWAP_LOCK_OUT_MASK__SI 0x00000004L -#define LB_MVP_DEBUG1__IDE7_D1_UPDATE_PENDING_MASK__SI 0x00040000L -#define LB_MVP_DEBUG1__IDE7_D1_VSYNC_FLIP_NOW_MASK__SI 0x00000100L -#define LB_MVP_DEBUG1__IDE7_D1_V_UPDATE_MASK__SI 0x01000000L -#define LB_MVP_DEBUG1__IDE7_D2_AFR_FIFO_EMPTY_COND_MASK__SI 0x80000000L -#define LB_MVP_DEBUG1__IDE7_D2_AFR_FIFO_EMPTY_MASK__SI 0x20000000L -#define LB_MVP_DEBUG1__IDE7_D2_FLIP_NOW_MASK__SI 0x00800000L -#define LB_MVP_DEBUG1__IDE7_D2_FLIP_NOW_OCCURRED1_MASK__SI 0x00000800L -#define LB_MVP_DEBUG1__IDE7_D2_FLIP_REQUEST_MASK__SI 0x00020000L -#define LB_MVP_DEBUG1__IDE7_D2_HSYNC_FLIP_NOW_MASK__SI 0x00000080L -#define LB_MVP_DEBUG1__IDE7_D2_SWAP_LOCK_IN_MASK__SI 0x00200000L -#define LB_MVP_DEBUG1__IDE7_D2_SWAP_LOCK_MASK__SI 0x00000002L -#define LB_MVP_DEBUG1__IDE7_D2_SWAP_LOCK_OUT_MASK__SI 0x00000008L -#define LB_MVP_DEBUG1__IDE7_D2_UPDATE_PENDING_MASK__SI 0x00080000L -#define LB_MVP_DEBUG1__IDE7_D2_VSYNC_FLIP_NOW_MASK__SI 0x00000200L -#define LB_MVP_DEBUG1__IDE7_D2_V_UPDATE_MASK__SI 0x02000000L -#define LB_MVP_DEBUG1__IDE7_LATCH_D1_Y_AFTER_VBLANK_MASK__SI 0x00004000L -#define LB_MVP_DEBUG1__IDE7_LATCH_D2_Y_AFTER_VBLANK_MASK__SI 0x00008000L -#define LB_MVP_DEBUG1__IDE7_LB_CRTC1_MVP_AFR_HSYNC_SWITCH_MASK__SI 0x00001000L -#define LB_MVP_DEBUG1__IDE7_LB_DCP_D1_ALLOW_FLIP_MASK__SI 0x00000010L -#define LB_MVP_DEBUG1__IDE7_LB_DCP_D2_ALLOW_FLIP_MASK__SI 0x00000020L -#define LB_MVP_DEBUG1__IDE7_WTRIG_POST_FLD_D1_MVP_AFR_FLIP_MODE_MASK__SI 0x04000000L -#define LB_MVP_DEBUG1__IDE7_WTRIG_POST_FLD_D2_MVP_AFR_FLIP_MODE_MASK__SI 0x08000000L -#define LB_MVP_DEBUG2__IDE8_CRTC1_LB_MVP_FLIP_LINE_NUMBER_MASK__SI 0x00001fffL -#define LB_MVP_DEBUG2__IDE8_CRTC2_LB_MVP_FLIP_LINE_NUMBER_MASK__SI 0x03ffe000L -#define LB_MVP_DEBUG3__IDE9_D1_FLIP_REQUEST_MASK__SI 0x40000000L -#define LB_MVP_DEBUG3__IDE9_D2_FLIP_REQUEST_MASK__SI 0x80000000L -#define LB_MVP_DEBUG3__IDE9_LB_CRTC1_MVP_FLIP_LINE_NUMBER_MASK__SI 0x00001fffL -#define LB_MVP_DEBUG3__IDE9_LB_CRTC1_MVP_FLIP_QUEUE_STATUS_MASK__SI 0x0c000000L -#define LB_MVP_DEBUG3__IDE9_LB_CRTC2_MVP_FLIP_LINE_NUMBER_MASK__SI 0x03ffe000L -#define LB_MVP_DEBUG3__IDE9_LB_CRTC2_MVP_FLIP_QUEUE_STATUS_MASK__SI 0x30000000L -#define LB_MVP_DEBUG4__IDEA_LAST_D1_Y_MASK__SI 0x00001fffL -#define LB_MVP_DEBUG4__IDEA_LAST_D2_Y_MASK__SI 0x03ffe000L -#define LB_MVP_DEBUG5__IDEB_D1_MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK__SI 0x0000000fL -#define LB_MVP_DEBUG5__IDEB_D2_MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK__SI 0x000000f0L -#define LB_MVP_DEBUG5__IDEB_LB_DCP_MVP_REQ_MASK__SI 0x00800000L -#define LB_MVP_DEBUG5__IDEB_LB_MVP_LAST_CHUNK_MASK__SI 0x00200000L -#define LB_MVP_DEBUG5__IDEB_LB_MVP_REQ_DISPNUM_MASK__SI 0x00400000L -#define LB_MVP_DEBUG5__IDEB_LB_MVP_Y_MASK__SI 0x001fff00L -#define LB_NEW_LEVEL1__ID81_DISP1_3RD_LINE_WRITE_LEVEL_MASK__SI 0x07fc0000L -#define LB_NEW_LEVEL1__ID81_DISP1_NEXT_LINE_SEND_DONE_MASK__SI 0x10000000L -#define LB_NEW_LEVEL1__ID81_DISP1_READ_WRITE_LEVEL_MASK__SI 0x000001ffL -#define LB_NEW_LEVEL1__ID81_DISP1_SEND_FOR_NEXT_LINE_MASK__SI 0x40000000L -#define LB_NEW_LEVEL1__ID81_DISP1_SEND_FOR_THIRD_LINE_MASK__SI 0x80000000L -#define LB_NEW_LEVEL1__ID81_DISP1_THIRD_LINE_SEND_DONE_MASK__SI 0x20000000L -#define LB_NEW_LEVEL1__ID81_DISP1_THIS_LINE_SEND_DONE_MASK__SI 0x08000000L -#define LB_NEW_LEVEL1__ID81_DISP1_WRITE_ONLY_LEVEL_MASK__SI 0x0003fe00L -#define LB_NEW_LEVEL2__ID82_DISP2_3RD_LINE_WRITE_LEVEL_MASK__SI 0x07fc0000L -#define LB_NEW_LEVEL2__ID82_DISP2_NEXT_LINE_SEND_DONE_MASK__SI 0x10000000L -#define LB_NEW_LEVEL2__ID82_DISP2_READ_WRITE_LEVEL_MASK__SI 0x000001ffL -#define LB_NEW_LEVEL2__ID82_DISP2_SEND_FOR_NEXT_LINE_MASK__SI 0x40000000L -#define LB_NEW_LEVEL2__ID82_DISP2_SEND_FOR_THIRD_LINE_MASK__SI 0x80000000L -#define LB_NEW_LEVEL2__ID82_DISP2_THIRD_LINE_SEND_DONE_MASK__SI 0x20000000L -#define LB_NEW_LEVEL2__ID82_DISP2_THIS_LINE_SEND_DONE_MASK__SI 0x08000000L -#define LB_NEW_LEVEL2__ID82_DISP2_WRITE_ONLY_LEVEL_MASK__SI 0x0003fe00L -#define LB_NEW_STATUS1__ID80_CURSOR_ICON_ALLOW_STUTTER_MASK__SI 0x04000000L -#define LB_NEW_STATUS1__ID80_DC_CG_DISP1_VBI_MASK__SI 0x40000000L -#define LB_NEW_STATUS1__ID80_DC_CG_DISP2_VBI_MASK__SI 0x80000000L -#define LB_NEW_STATUS1__ID80_DC_CG_WM_HIGH_OCCURRED_MASK__SI 0x00800000L -#define LB_NEW_STATUS1__ID80_DC_CG_WM_HIGH_STATUS_MASK__SI 0x00400000L -#define LB_NEW_STATUS1__ID80_DC_CG_WM_MCHANGE_OCCURRED_MASK__SI 0x20000000L -#define LB_NEW_STATUS1__ID80_DC_CG_WM_MCHANGE_STATUS_MASK__SI 0x10000000L -#define LB_NEW_STATUS1__ID80_DISP1_MODE_PREFETCH_MASK__SI 0x00000001L -#define LB_NEW_STATUS1__ID80_DISP1_NEW_LINE_RECEIVED_MASK__SI 0x01000000L -#define LB_NEW_STATUS1__ID80_DISP1_NUM_PARTITIONS_MASK__SI 0x0000003cL -#define LB_NEW_STATUS1__ID80_DISP1_REQ_FIFO_LEVEL_MASK__SI 0x0000fc00L -#define LB_NEW_STATUS1__ID80_DISP2_MODE_PREFETCH_MASK__SI 0x00000002L -#define LB_NEW_STATUS1__ID80_DISP2_NEW_LINE_RECEIVED_MASK__SI 0x02000000L -#define LB_NEW_STATUS1__ID80_DISP2_NUM_PARTITIONS_MASK__SI 0x000003c0L -#define LB_NEW_STATUS1__ID80_DISP2_REQ_FIFO_LEVEL_MASK__SI 0x003f0000L -#define LB_SCL1_READ__ID93_DISP1_BLACK_STATE_MASK__SI 0x00020000L -#define LB_SCL1_READ__ID93_DISP1_EOL_MASK__SI 0x00000002L -#define LB_SCL1_READ__ID93_DISP1_FIRST_LINE_MASK__SI 0x0000e000L -#define LB_SCL1_READ__ID93_DISP1_LAST_LINE_MASK__SI 0x00010000L -#define LB_SCL1_READ__ID93_DISP1_LINE_SEL_MASK__SI 0x00001c00L -#define LB_SCL1_READ__ID93_DISP1_NUM_TAP_IGNORE_MASK__SI 0x000000e0L -#define LB_SCL1_READ__ID93_DISP1_READ_ADR_MASK__SI 0xffe00000L -#define LB_SCL1_READ__ID93_DISP1_RTR_MASK__SI 0x00000100L -#define LB_SCL1_READ__ID93_DISP1_RTS_MASK__SI 0x00000200L -#define LB_SCL1_READ__ID93_DISP1_SOF_MASK__SI 0x00000001L -#define LB_SCL1_READ__ID93_DISP1_TAP_MASK__SI 0x001c0000L -#define LB_SCL1_READ__ID93_DISP1_TAP_SHIFT_MASK__SI 0x0000001cL -#define LB_SCL2_READ__ID94_DISP2_BLACK_STATE_MASK__SI 0x00020000L -#define LB_SCL2_READ__ID94_DISP2_EOL_MASK__SI 0x00000002L -#define LB_SCL2_READ__ID94_DISP2_FIRST_LINE_MASK__SI 0x0000e000L -#define LB_SCL2_READ__ID94_DISP2_LAST_LINE_MASK__SI 0x00010000L -#define LB_SCL2_READ__ID94_DISP2_LINE_SEL_MASK__SI 0x00001c00L -#define LB_SCL2_READ__ID94_DISP2_NUM_TAP_IGNORE_MASK__SI 0x000000e0L -#define LB_SCL2_READ__ID94_DISP2_READ_ADR_MASK__SI 0xffe00000L -#define LB_SCL2_READ__ID94_DISP2_RTR_MASK__SI 0x00000100L -#define LB_SCL2_READ__ID94_DISP2_RTS_MASK__SI 0x00000200L -#define LB_SCL2_READ__ID94_DISP2_SOF_MASK__SI 0x00000001L -#define LB_SCL2_READ__ID94_DISP2_TAP_MASK__SI 0x001c0000L -#define LB_SCL2_READ__ID94_DISP2_TAP_SHIFT_MASK__SI 0x0000001cL -#define LB_SLOW_REQ_VAL__LB_SLOW_REQ_VAL_MASK__SI 0x0000001fL -#define LB_STUTTER_DBG1__IDA0_DC_CG_DISP1_WM_HIGH_CNT_OVERFLOW_MASK__SI 0x80000000L -#define LB_STUTTER_DBG1__IDA0_DC_CG_DISP1_WM_HIGH_MAX_CNT_MASK__SI 0x0000ffffL -#define LB_STUTTER_DBG1__IDA0_DC_CG_DISP1_WM_HIGH_MIN_CNT_MASK__SI 0x7fff0000L -#define LB_STUTTER_DBG2__IDA1_DC_CG_DISP2_WM_HIGH_CNT_OVERFLOW_MASK__SI 0x80000000L -#define LB_STUTTER_DBG2__IDA1_DC_CG_DISP2_WM_HIGH_MAX_CNT_MASK__SI 0x0000ffffL -#define LB_STUTTER_DBG2__IDA1_DC_CG_DISP2_WM_HIGH_MIN_CNT_MASK__SI 0x7fff0000L -#define LB_STUTTER_DBG3__IDA2_D1_WM_ABOVE_STUTTER_ON_MASK__SI 0x04000000L -#define LB_STUTTER_DBG3__IDA2_D1_WM_BELOW_STUTTER_OFF_MASK__SI 0x01000000L -#define LB_STUTTER_DBG3__IDA2_D2_WM_ABOVE_STUTTER_ON_MASK__SI 0x08000000L -#define LB_STUTTER_DBG3__IDA2_D2_WM_BELOW_STUTTER_OFF_MASK__SI 0x02000000L -#define LB_STUTTER_DBG3__IDA2_DC_CG_DISP1_WM_HIGH_MASK__SI 0x00000001L -#define LB_STUTTER_DBG3__IDA2_DC_CG_DISP2_WM_HIGH_MASK__SI 0x00001000L -#define LB_STUTTER_DBG3__IDA2_DISP1_COMP_LEVEL_ALLOW_STOP_MASK__SI 0x00000100L -#define LB_STUTTER_DBG3__IDA2_DISP1_CURSOR_ICON_ALLOW_STOP_MASK__SI 0x00000040L -#define LB_STUTTER_DBG3__IDA2_DISP1_FID_ALLOW_STOP_MASK__SI 0x00000080L -#define LB_STUTTER_DBG3__IDA2_DISP1_LEVEL_ALLOW_STOP_MASK__SI 0x00000004L -#define LB_STUTTER_DBG3__IDA2_DISP1_NEW_LINE_RECVD_MASK__SI 0x00000020L -#define LB_STUTTER_DBG3__IDA2_DISP1_OUTPUT_LINE_RECVD_MASK__SI 0x00000002L -#define LB_STUTTER_DBG3__IDA2_DISP1_UNCOMP_LINE_RECVD_MASK__SI 0x00000018L -#define LB_STUTTER_DBG3__IDA2_DISP1_WM_MCLK_CHG_MASK__SI 0x10000000L -#define LB_STUTTER_DBG3__IDA2_DISP2_COMP_LEVEL_ALLOW_STOP_MASK__SI 0x00100000L -#define LB_STUTTER_DBG3__IDA2_DISP2_CURSOR_ICON_ALLOW_STOP_MASK__SI 0x00040000L -#define LB_STUTTER_DBG3__IDA2_DISP2_FID_ALLOW_STOP_MASK__SI 0x00080000L -#define LB_STUTTER_DBG3__IDA2_DISP2_LEVEL_ALLOW_STOP_MASK__SI 0x00004000L -#define LB_STUTTER_DBG3__IDA2_DISP2_NEW_LINE_RECVD_MASK__SI 0x00020000L -#define LB_STUTTER_DBG3__IDA2_DISP2_OUTPUT_LINE_RECVD_MASK__SI 0x00002000L -#define LB_STUTTER_DBG3__IDA2_DISP2_UNCOMP_LINE_RECVD_MASK__SI 0x00018000L -#define LB_STUTTER_DBG3__IDA2_DISP2_WM_MCLK_CHG_MASK__SI 0x20000000L -#define LB_STUTTER_DBG3__IDA2_LINE_RECEIVED1_MASK__SI 0x00000c00L -#define LB_STUTTER_DBG3__IDA2_LINE_RECEIVED2_MASK__SI 0x00c00000L -#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK__SI 0x00000003L -#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define LB_URGENCY__ID99_DISP1_URGENCY_FLAG_MASK__SI 0x00000001L -#define LB_URGENCY__ID99_DISP1_URGLEVEL_MASK__SI 0x000000feL -#define LB_URGENCY__ID99_DISP2_URGENCY_FLAG_MASK__SI 0x00000100L -#define LB_URGENCY__ID99_DISP2_URGLEVEL_MASK__SI 0x0000fe00L -#define LB_URGENCY__ID99_LB_DCP_URGENCY_FLAG_MASK__SI 0x00010000L -#define LB_URGENCY__ID99_LB_DCP_URGLEVEL_DEBUG_MASK__SI 0xfe000000L -#define LB_URGENCY__ID99_LB_DCP_URGLEVEL_MASK__SI 0x00fe0000L -#define LB_URGENT_LEVEL_CNTL__CURR_PRIORITY_MARK_MASK__SI 0x00007fffL -#define LB_URGENT_LEVEL_CNTL__LB_MAX_URGENT_WHEN_UNDERFLOW_MASK__SI 0x80000000L -#define LB_URGENT_LEVEL_CNTL__LB_URGENT_LEVEL_SEL_MASK__SI 0x00008000L -#define LCAC_CPL_CB_CNTL__CPL_CB_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_CB_CNTL__CPL_CB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_CB_OVR_SEL__CPL_CB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_CB_OVR_VAL__CPL_CB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_CPL_CNTL__CPL_ENABLE_MASK__CI 0x00000001L -#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK__CI 0x0001fffeL -#define LCAC_CPL_DB_CNTL__CPL_DB_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_DB_CNTL__CPL_DB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_DB_OVR_SEL__CPL_DB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_DB_OVR_VAL__CPL_DB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_LDS_CNTL__CPL_LDS_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_LDS_CNTL__CPL_LDS_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_LDS_OVR_SEL__CPL_LDS_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_LDS_OVR_VAL__CPL_LDS_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_MC_CNTL__CPL_MC_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_MC_CNTL__CPL_MC_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_MC_OVR_SEL__CPL_MC_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_MC_OVR_VAL__CPL_MC_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK__CI 0xffffffffL -#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK__CI 0xffffffffL -#define LCAC_CPL_PA_CNTL__CPL_PA_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_PA_CNTL__CPL_PA_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_PA_OVR_SEL__CPL_PA_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_PA_OVR_VAL__CPL_PA_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_SC_CNTL__CPL_SC_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_SC_CNTL__CPL_SC_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_SC_OVR_SEL__CPL_SC_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_SC_OVR_VAL__CPL_SC_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_SPI_CNTL__CPL_SPI_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_SPI_CNTL__CPL_SPI_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_SPI_OVR_SEL__CPL_SPI_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_SPI_OVR_VAL__CPL_SPI_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_SQ_CNTL__CPL_SQ_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_SQ_CNTL__CPL_SQ_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_SQ_OVR_SEL__CPL_SQ_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_SQ_OVR_VAL__CPL_SQ_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_SX_CNTL__CPL_SX_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_SX_CNTL__CPL_SX_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_SX_OVR_SEL__CPL_SX_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_SX_OVR_VAL__CPL_SX_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_TA_CNTL__CPL_TA_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_TA_CNTL__CPL_TA_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_TA_OVR_SEL__CPL_TA_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_TA_OVR_VAL__CPL_TA_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_TCC_CNTL__CPL_TCC_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_TCC_CNTL__CPL_TCC_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_TCC_OVR_SEL__CPL_TCC_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_TCC_OVR_VAL__CPL_TCC_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_TCP_CNTL__CPL_TCP_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_TCP_CNTL__CPL_TCP_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_TCP_OVR_SEL__CPL_TCP_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_TCP_OVR_VAL__CPL_TCP_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_CPL_VGT_CNTL__CPL_VGT_ENABLE_MASK__SI 0x00000001L -#define LCAC_CPL_VGT_CNTL__CPL_VGT_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_CPL_VGT_OVR_SEL__CPL_VGT_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_CPL_VGT_OVR_VAL__CPL_VGT_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_MC0_CNTL__MC0_ENABLE_MASK__SI__CI 0x00000001L -#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK__SI__CI 0x0001fffeL -#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK__SI__CI 0xffffffffL -#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK__SI__CI 0xffffffffL -#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_MC1_CNTL__MC1_ENABLE_MASK__SI__CI 0x00000001L -#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK__SI__CI 0x0001fffeL -#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK__SI__CI 0xffffffffL -#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK__SI__CI 0xffffffffL -#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_MC2_CNTL__MC2_ENABLE_MASK__SI__CI 0x00000001L -#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK__SI__CI 0x0001fffeL -#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK__SI__CI 0xffffffffL -#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK__SI__CI 0xffffffffL -#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_MC3_CNTL__MC3_ENABLE_MASK__SI__CI 0x00000001L -#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK__SI__CI 0x0001fffeL -#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK__SI__CI 0xffffffffL -#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK__SI__CI 0xffffffffL -#define LCAC_MC4_CNTL__MC4_ENABLE_MASK__SI 0x00000001L -#define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_MC5_CNTL__MC5_ENABLE_MASK__SI 0x00000001L -#define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX0_CB_CNTL__SX0_CB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX0_CB_CNTL__SX0_CB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX0_CB_OVR_SEL__SX0_CB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX0_CB_OVR_VAL__SX0_CB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_SX0_CNTL__SX0_ENABLE_MASK__CI 0x00000001L -#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK__CI 0x0001fffeL -#define LCAC_SX0_DB_CNTL__SX0_DB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX0_DB_CNTL__SX0_DB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX0_DB_OVR_SEL__SX0_DB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX0_DB_OVR_VAL__SX0_DB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX0_LDS_CNTL__SX0_LDS_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX0_LDS_CNTL__SX0_LDS_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX0_LDS_OVR_SEL__SX0_LDS_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX0_LDS_OVR_VAL__SX0_LDS_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK__CI 0xffffffffL -#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK__CI 0xffffffffL -#define LCAC_SX0_TA_CNTL__SX0_TA_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX0_TA_CNTL__SX0_TA_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX0_TA_OVR_SEL__SX0_TA_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX0_TA_OVR_VAL__SX0_TA_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX0_TCC_CNTL__SX0_TCC_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX0_TCC_CNTL__SX0_TCC_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX0_TCC_OVR_SEL__SX0_TCC_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX0_TCC_OVR_VAL__SX0_TCC_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX0_TCP_CNTL__SX0_TCP_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX0_TCP_CNTL__SX0_TCP_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX0_TCP_OVR_SEL__SX0_TCP_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX0_TCP_OVR_VAL__SX0_TCP_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX1_CB_CNTL__SX1_CB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX1_CB_CNTL__SX1_CB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX1_CB_OVR_SEL__SX1_CB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX1_CB_OVR_VAL__SX1_CB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX1_CNTL__SX1_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_SX1_CNTL__SX1_ENABLE_MASK__CI 0x00000001L -#define LCAC_SX1_CNTL__SX1_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_SX1_CNTL__SX1_THRESHOLD_MASK__CI 0x0001fffeL -#define LCAC_SX1_DB_CNTL__SX1_DB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX1_DB_CNTL__SX1_DB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX1_DB_OVR_SEL__SX1_DB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX1_DB_OVR_VAL__SX1_DB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX1_LDS_CNTL__SX1_LDS_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX1_LDS_CNTL__SX1_LDS_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX1_LDS_OVR_SEL__SX1_LDS_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX1_LDS_OVR_VAL__SX1_LDS_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX1_OVR_SEL__SX1_OVR_SEL_MASK__CI 0xffffffffL -#define LCAC_SX1_OVR_VAL__SX1_OVR_VAL_MASK__CI 0xffffffffL -#define LCAC_SX1_TA_CNTL__SX1_TA_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX1_TA_CNTL__SX1_TA_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX1_TA_OVR_SEL__SX1_TA_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX1_TA_OVR_VAL__SX1_TA_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX1_TCC_CNTL__SX1_TCC_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX1_TCC_CNTL__SX1_TCC_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX1_TCC_OVR_SEL__SX1_TCC_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX1_TCC_OVR_VAL__SX1_TCC_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX1_TCP_CNTL__SX1_TCP_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX1_TCP_CNTL__SX1_TCP_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX1_TCP_OVR_SEL__SX1_TCP_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX1_TCP_OVR_VAL__SX1_TCP_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX2_CB_CNTL__SX2_CB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX2_CB_CNTL__SX2_CB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX2_CB_OVR_SEL__SX2_CB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX2_CB_OVR_VAL__SX2_CB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX2_CNTL__SX2_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_SX2_CNTL__SX2_ENABLE_MASK__CI 0x00000001L -#define LCAC_SX2_CNTL__SX2_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_SX2_CNTL__SX2_THRESHOLD_MASK__CI 0x0001fffeL -#define LCAC_SX2_DB_CNTL__SX2_DB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX2_DB_CNTL__SX2_DB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX2_DB_OVR_SEL__SX2_DB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX2_DB_OVR_VAL__SX2_DB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX2_LDS_CNTL__SX2_LDS_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX2_LDS_CNTL__SX2_LDS_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX2_LDS_OVR_SEL__SX2_LDS_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX2_LDS_OVR_VAL__SX2_LDS_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX2_OVR_SEL__SX2_OVR_SEL_MASK__CI 0xffffffffL -#define LCAC_SX2_OVR_VAL__SX2_OVR_VAL_MASK__CI 0xffffffffL -#define LCAC_SX2_TA_CNTL__SX2_TA_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX2_TA_CNTL__SX2_TA_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX2_TA_OVR_SEL__SX2_TA_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX2_TA_OVR_VAL__SX2_TA_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX2_TCC_CNTL__SX2_TCC_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX2_TCC_CNTL__SX2_TCC_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX2_TCC_OVR_SEL__SX2_TCC_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX2_TCC_OVR_VAL__SX2_TCC_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX2_TCP_CNTL__SX2_TCP_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX2_TCP_CNTL__SX2_TCP_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX2_TCP_OVR_SEL__SX2_TCP_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX2_TCP_OVR_VAL__SX2_TCP_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX3_CB_CNTL__SX3_CB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX3_CB_CNTL__SX3_CB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX3_CB_OVR_SEL__SX3_CB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX3_CB_OVR_VAL__SX3_CB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX3_CNTL__SX3_BLOCK_ID_MASK__CI 0x003e0000L -#define LCAC_SX3_CNTL__SX3_ENABLE_MASK__CI 0x00000001L -#define LCAC_SX3_CNTL__SX3_SIGNAL_ID_MASK__CI 0x3fc00000L -#define LCAC_SX3_CNTL__SX3_THRESHOLD_MASK__CI 0x0001fffeL -#define LCAC_SX3_DB_CNTL__SX3_DB_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX3_DB_CNTL__SX3_DB_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX3_DB_OVR_SEL__SX3_DB_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX3_DB_OVR_VAL__SX3_DB_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX3_LDS_CNTL__SX3_LDS_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX3_LDS_CNTL__SX3_LDS_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX3_LDS_OVR_SEL__SX3_LDS_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX3_LDS_OVR_VAL__SX3_LDS_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX3_OVR_SEL__SX3_OVR_SEL_MASK__CI 0xffffffffL -#define LCAC_SX3_OVR_VAL__SX3_OVR_VAL_MASK__CI 0xffffffffL -#define LCAC_SX3_TA_CNTL__SX3_TA_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX3_TA_CNTL__SX3_TA_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX3_TA_OVR_SEL__SX3_TA_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX3_TA_OVR_VAL__SX3_TA_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX3_TCC_CNTL__SX3_TCC_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX3_TCC_CNTL__SX3_TCC_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX3_TCC_OVR_SEL__SX3_TCC_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX3_TCC_OVR_VAL__SX3_TCC_OVR_VAL_MASK__SI 0xffffffffL -#define LCAC_SX3_TCP_CNTL__SX3_TCP_ENABLE_MASK__SI 0x00000001L -#define LCAC_SX3_TCP_CNTL__SX3_TCP_THRESHOLD_MASK__SI 0x0001fffeL -#define LCAC_SX3_TCP_OVR_SEL__SX3_TCP_OVR_SEL_MASK__SI 0xffffffffL -#define LCAC_SX3_TCP_OVR_VAL__SX3_TCP_OVR_VAL_MASK__SI 0xffffffffL -#define LCLK_ACTIVITY_CNT_CNTL__START_ACTIVITY_CNT_MASK__CI__VI 0x00000001L -#define LCLK_ACTIVITY_CNT_STATUS__ACTIVITY_CNT_MASK__CI__VI 0x00ffffffL -#define LCLK_ACTIVITY_CNT_STATUS__ACTIVITY_CNT_VALID_MASK__CI__VI 0x80000000L -#define LCLK_AM_CNTL__ACTIVITY_CNT_RST_MASK__CI__VI 0x00000001L -#define LCLK_AM_CNTL__BUSY_CNT_RESOLUTION_MASK__CI__VI 0x000000c0L -#define LCLK_AM_CNTL__BUSY_CNT_SEL_MASK__CI__VI 0x00000018L -#define LCLK_AM_CNTL__EN_BIF_CNT_MASK__CI__VI 0x00000100L -#define LCLK_AM_CNTL__EN_ORB_DS_CNT_MASK__CI__VI 0x00000400L -#define LCLK_AM_CNTL__EN_ORB_US_CNT_MASK__CI__VI 0x00000200L -#define LCLK_AM_CNTL__PERIOD_CNT_RST_MASK__CI__VI 0x00000002L -#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK__CI__VI 0x00000002L -#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK__CI__VI 0x00100000L -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK__CI__VI 0x00001000L -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK__CI__VI 0x00000800L -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK__CI__VI 0x00000400L -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK__CI__VI 0x00002000L -#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK__CI__VI 0x00000004L -#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK__CI__VI 0x00004000L -#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK__CI__VI 0x00020000L -#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK__CI__VI 0x00010000L -#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK__CI__VI 0x00080000L -#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK__CI__VI 0x00040000L -#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK__CI__VI 0x00008000L -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK__CI__VI 0x00000040L -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK__CI__VI 0x00000080L -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK__CI__VI 0x00000100L -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK__CI__VI 0x00000200L -#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK__CI 0xffe00000L -#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK__CI__VI 0x00000001L -#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK__CI__VI 0x00000010L -#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK__CI__VI 0x00000020L -#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK__CI__VI 0x00000007L -#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK__CI__VI 0x80000000L -#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK__CI__VI 0x0000fff0L -#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK__CI__VI 0x00000008L -#define LCLK_PERIOD_CNT_STATUS__PERIOD_CNT_MASK__CI__VI 0x00ffffffL -#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK__CI__VI 0x00000100L -#define LINK_CAP2__RESERVED_MASK__CI__VI 0xfffffe00L -#define LINK_CAP2__RESERVED_MASK__SI 0xffffffffL -#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK__CI__VI 0x000000feL -#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK__CI__VI 0x00400000L -#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L -#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L -#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L -#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L -#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L -#define LINK_CAP__LINK_SPEED_MASK 0x0000000fL -#define LINK_CAP__LINK_WIDTH_MASK 0x000003f0L -#define LINK_CAP__PM_SUPPORT_MASK 0x00000c00L -#define LINK_CAP__PORT_NUMBER_MASK 0xff000000L -#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L -#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK__CI__VI 0x0000f000L -#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK__SI 0x00001000L -#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x00000800L -#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x00000010L -#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x00000400L -#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x00000020L -#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x00000040L -#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x0000000fL -#define LINK_CNTL2__XMIT_MARGIN_MASK 0x00000380L -#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x00000100L -#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x00000040L -#define LINK_CNTL__EXTENDED_SYNC_MASK 0x00000080L -#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x00000200L -#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x00000800L -#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x00000400L -#define LINK_CNTL__LINK_DIS_MASK 0x00000010L -#define LINK_CNTL__PM_CONTROL_MASK 0x00000003L -#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x00000008L -#define LINK_CNTL__RETRAIN_LINK_MASK 0x00000020L -#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x00000001L -#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK__CI__VI 0x00000002L -#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK__CI__VI 0x00000004L -#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK__CI__VI 0x00000008L -#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK__CI__VI 0x00000010L -#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK__CI__VI 0x00000020L -#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x0000000fL -#define LINK_STATUS__DL_ACTIVE_MASK 0x00002000L -#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x00008000L -#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x00004000L -#define LINK_STATUS__LINK_TRAINING_MASK 0x00000800L -#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x000003f0L -#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x00001000L -#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK__CI 0x00000001L -#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK__CI 0x00000006L -#define LPML_SCALAR_1__Lmpl1_MASK__CI 0x0000003fL -#define LPML_SCALAR_1__Lmpl2_MASK__CI 0x00000fc0L -#define LPML_SCALAR_1__Lmpl3_MASK__CI 0x0003f000L -#define LPML_SCALAR_1__Lmpl4_MASK__CI 0x00fc0000L -#define LPML_SCALAR_1__Lmpl5_MASK__CI 0x3f000000L -#define LPML_SCALAR_1__RESERVED_MASK__CI__VI 0xc0000000L -#define LPML_SCALAR_2__Lmpl0_MASK__CI 0x0003f000L -#define LPML_SCALAR_2__Lmpl6_MASK__CI 0x0000003fL -#define LPML_SCALAR_2__Lmpl7_MASK__CI 0x00000fc0L -#define LPML_SCALAR_2__RESERVED_MASK__CI__VI 0xfffc0000L -#define LPMV_SCALAR_1__Lmpv1_MASK__CI 0x0000003fL -#define LPMV_SCALAR_1__Lmpv2_MASK__CI 0x00000fc0L -#define LPMV_SCALAR_1__Lmpv3_MASK__CI 0x0003f000L -#define LPMV_SCALAR_1__Lmpv4_MASK__CI 0x00fc0000L -#define LPMV_SCALAR_1__Lmpv5_MASK__CI 0x3f000000L -#define LPMV_SCALAR_1__RESERVED_MASK__CI__VI 0xc0000000L -#define LPMV_SCALAR_2__Lmpv0_MASK__CI 0x0003f000L -#define LPMV_SCALAR_2__Lmpv6_MASK__CI 0x0000003fL -#define LPMV_SCALAR_2__Lmpv7_MASK__CI 0x00000fc0L -#define LPMV_SCALAR_2__Lpm_Trigger_MASK__CI__VI 0x80000000L -#define LPMV_SCALAR_2__RESERVED_MASK__CI__VI 0x7ffc0000L -#define LUMA_BOT_ADDR__Y_BOT_BASE_MASK__SI 0xffffffffL -#define LUMA_TOP_ADDR__Y_TOP_BASE_MASK__SI 0xffffffffL -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_CLK_PREMPHEN_MASK__SI 0x00000001L -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_CLK_PREMPH_DT_MASK__SI 0x00000f00L -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_CLK_PREMPH_STR_MASK__SI 0x00000070L -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_DAT_PREMPHEN_MASK__SI 0x00010000L -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_DAT_PREMPH_DT_MASK__SI 0x0f000000L -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_DAT_PREMPH_STR_MASK__SI 0x00700000L -#define LVDSA_TRANSMITTER_ADJUST__LVDSA_NTXVS_MASK__SI 0x00001f00L -#define LVDSA_TRANSMITTER_ADJUST__LVDSA_PTXVS_MASK__SI 0x001f0000L -#define LVDSA_TRANSMITTER_ADJUST__LVDSA_TXOP_MASK__SI 0x00000007L -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_CLK_PREMPHEN_MASK__SI 0x00000001L -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_CLK_PREMPH_DT_MASK__SI 0x00000f00L -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_CLK_PREMPH_STR_MASK__SI 0x00000070L -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_DAT_PREMPHEN_MASK__SI 0x00010000L -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_DAT_PREMPH_DT_MASK__SI 0x0f000000L -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_DAT_PREMPH_STR_MASK__SI 0x00700000L -#define LVDSB_TRANSMITTER_ADJUST__LVDSB_NTXVS_MASK__SI 0x00001f00L -#define LVDSB_TRANSMITTER_ADJUST__LVDSB_PTXVS_MASK__SI 0x001f0000L -#define LVDSB_TRANSMITTER_ADJUST__LVDSB_TXOP_MASK__SI 0x00000007L -#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK__SI 0x00000001L -#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK__SI 0x00000010L -#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK__SI 0x00000100L -#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK__SI 0x00000400L -#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK__SI 0x00000200L -#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK__SI 0x00007000L -#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK__SI 0x00040000L -#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK__SI 0x00010000L -#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK__SI 0x00020000L -#define LVTMA_PWRSEQ_CNTL__LVTMA_BGSLEEP_MASK__SI 0x00000020L -#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK__SI 0x01000000L -#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK__SI 0x02000000L -#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK__SI 0x04000000L -#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK__SI 0x00010000L -#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK__SI 0x00020000L -#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK__SI 0x00040000L -#define LVTMA_PWRSEQ_CNTL__LVTMA_PLL_ENABLE_PWRSEQ_MASK_MASK__SI 0x00000004L -#define LVTMA_PWRSEQ_CNTL__LVTMA_PLL_RESET_PWRSEQ_MASK_MASK__SI 0x00000008L -#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK__SI 0x00000002L -#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK__SI 0x00000001L -#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK__SI 0x00000010L -#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK__SI 0x00000100L -#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK__SI 0x00000200L -#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK__SI 0x00000400L -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK__SI 0x00ff0000L -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK__SI 0xff000000L -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK__SI 0x000000ffL -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK__SI 0x0000ff00L -#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK__SI 0x000000ffL -#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK__SI 0xffff0000L -#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK__SI 0x00000fffL -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK__SI 0x00000008L -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK__SI 0x00000002L -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK__SI 0x00000010L -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK__SI 0x00000f00L -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK__SI 0x00000004L -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK__SI 0x00000001L -#define LX0__RESERVED_MASK 0xffffffffL -#define LX1__RESERVED_MASK 0xffffffffL -#define LX2__RESERVED_MASK 0xffffffffL -#define LX3__RESERVED_MASK 0xffffffffL -#define MAJOR_VERSION__MAJOR_VERSION_MASK__SI 0x000000ffL -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK__SI 0x000000ffL -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK__SI 0x0000ff00L -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK__SI 0x00ff0000L -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK__SI 0xff000000L -#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK__SI 0x00000001L -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK__SI 0x000000ffL -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK__SI 0x0000ff00L -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK__SI 0x00ff0000L -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK__SI 0xff000000L -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK__SI 0x000000ffL -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK__SI 0x0000ff00L -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK__SI 0x00ff0000L -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK__SI 0xff000000L -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK__SI 0x000000ffL -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK__SI 0x0000ff00L -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK__SI 0x00ff0000L -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK__SI 0xff000000L -#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x003f0000L -#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK__CI__VI 0x0000007fL -#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK__SI 0x0000003fL -#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK__SI 0x00000001L -#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK__SI 0x00030000L -#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK__SI 0x00000007L -#define MAX_LATENCY__MAX_LAT_MASK 0x000000ffL -#define MB_DONE__MB_X_MASK__SI 0x00000fffL -#define MB_DONE__MB_Y_MASK__SI 0x0fff0000L -#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK__SI 0x00000010L -#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK__SI 0x00ff0000L -#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK__SI 0x00000003L -#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK__SI 0x40000000L -#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK__SI 0x80000000L -#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK__SI 0x3f000000L -#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK__SI 0x00000100L -#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK__SI 0x000000ffL -#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK__SI 0x0000ff00L -#define MCLK_AM_CNTL__CLEAR_MCLK_AM_BUSY_CNT_MASK__CI__VI 0x00000001L -#define MCLK_AM_CNTL__CLEAR_MCLK_AM_SCLK_CNT_MASK__CI__VI 0x00000002L -#define MCLK_AM_CNTL__START_MCLK_AM_BUSY_CNT_MASK__CI__VI 0x00000004L -#define MCLK_AM_CNTL__START_MCLK_AM_SCLK_CNT_MASK__CI__VI 0x00000008L -#define MCLK_AM_PERIOD_CNT__AM_MCLK_PERIOD_CNT_MASK__CI__VI 0xffffffffL -#define MCLK_AM_READ_CNT__AM_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define MCLK_AM_WRITE_CNT__AM_BUSY_CNT_MASK__CI__VI 0xffffffffL -#define MCLK_CHG_CNT__MCLK_CHG_MARK_A_MASK__SI 0x00007fffL -#define MCLK_CHG_CNT__MCLK_CHG_MARK_B_MASK__SI 0x7fff0000L -#define MCLK_PWRMGT_CNTL__DLL_READY_MASK__SI__CI 0x00000040L -#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK__SI__CI 0x01000000L -#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK__SI__CI 0x0000001fL -#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK__SI__CI 0x00000080L -#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK__SI__CI 0x00000100L -#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK__SI__CI 0x00010000L -#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK__SI__CI 0x00000200L -#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK__SI__CI 0x00020000L -#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0x0000000fL -#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0x00000ff0L -#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0x0ffff000L -#define MC_ARB_ADDR_SWIZ0__A10_MASK__CI__VI 0x00000f00L -#define MC_ARB_ADDR_SWIZ0__A11_MASK__CI__VI 0x0000f000L -#define MC_ARB_ADDR_SWIZ0__A12_MASK__CI__VI 0x000f0000L -#define MC_ARB_ADDR_SWIZ0__A13_MASK__CI__VI 0x00f00000L -#define MC_ARB_ADDR_SWIZ0__A14_MASK__CI__VI 0x0f000000L -#define MC_ARB_ADDR_SWIZ0__A15_MASK__CI__VI 0xf0000000L -#define MC_ARB_ADDR_SWIZ0__A8_MASK__CI__VI 0x0000000fL -#define MC_ARB_ADDR_SWIZ0__A9_MASK__CI__VI 0x000000f0L -#define MC_ARB_ADDR_SWIZ1__A16_MASK__CI__VI 0x0000000fL -#define MC_ARB_ADDR_SWIZ1__A17_MASK__CI__VI 0x000000f0L -#define MC_ARB_ADDR_SWIZ1__A18_MASK__CI__VI 0x00000f00L -#define MC_ARB_ADDR_SWIZ1__A19_MASK__CI__VI 0x0000f000L -#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK__CI__VI 0x00070000L -#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK__CI__VI 0x00380000L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK__CI__VI 0x00000001L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK__CI__VI 0x00000002L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK__CI__VI 0x00000004L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK__CI__VI 0x00000008L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK__CI__VI 0x00000010L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK__CI__VI 0x00000020L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK__CI__VI 0x00000040L -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK__CI__VI 0x00000080L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK__CI__VI 0x00000100L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK__CI__VI 0x00000200L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK__CI__VI 0x00000400L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK__CI__VI 0x00000800L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK__CI__VI 0x00001000L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK__CI__VI 0x00002000L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK__CI__VI 0x00004000L -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK__CI__VI 0x00008000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x01000000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x02000000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x04000000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x08000000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000L -#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000L -#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x00010000L -#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x00020000L -#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x00040000L -#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x00080000L -#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x00100000L -#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x00200000L -#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x00400000L -#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x00800000L -#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x00000003L -#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0x0000000cL -#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x00000030L -#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0x000000c0L -#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x00000300L -#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0x00000c00L -#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x00003000L -#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0x0000c000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x01000000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x02000000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x04000000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x08000000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000L -#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000L -#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x00010000L -#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x00020000L -#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x00040000L -#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x00080000L -#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x00100000L -#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x00200000L -#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x00400000L -#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x00800000L -#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x00000003L -#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0x0000000cL -#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x00000030L -#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0x000000c0L -#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x00000300L -#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0x00000c00L -#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x00003000L -#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0x0000c000L -#define MC_ARB_BANKMAP__BANK0_MASK 0x0000000fL -#define MC_ARB_BANKMAP__BANK1_MASK 0x000000f0L -#define MC_ARB_BANKMAP__BANK2_MASK 0x00000f00L -#define MC_ARB_BANKMAP__BANK3_MASK 0x0000f000L -#define MC_ARB_BANKMAP__RANK_MASK 0x000f0000L -#define MC_ARB_BURST_TIME__STATE0_MASK 0x0000001fL -#define MC_ARB_BURST_TIME__STATE1_MASK 0x000003e0L -#define MC_ARB_BURST_TIME__STATE2_MASK 0x00007c00L -#define MC_ARB_BURST_TIME__STATE3_MASK 0x000f8000L -#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK__CI__VI 0x00100000L -#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK__CI__VI 0x00200000L -#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK__CI__VI 0x00400000L -#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK__CI__VI 0x00800000L -#define MC_ARB_BUSY_STATUS__HM_RD0_MASK__CI__VI 0x00000010L -#define MC_ARB_BUSY_STATUS__HM_RD1_MASK__CI__VI 0x00000020L -#define MC_ARB_BUSY_STATUS__HM_WR0_MASK__CI__VI 0x00000040L -#define MC_ARB_BUSY_STATUS__HM_WR1_MASK__CI__VI 0x00000080L -#define MC_ARB_BUSY_STATUS__LM_RD0_MASK__CI__VI 0x00000001L -#define MC_ARB_BUSY_STATUS__LM_RD1_MASK__CI__VI 0x00000002L -#define MC_ARB_BUSY_STATUS__LM_WR0_MASK__CI__VI 0x00000004L -#define MC_ARB_BUSY_STATUS__LM_WR1_MASK__CI__VI 0x00000008L -#define MC_ARB_BUSY_STATUS__POP0_MASK__CI__VI 0x00001000L -#define MC_ARB_BUSY_STATUS__POP1_MASK__CI__VI 0x00002000L -#define MC_ARB_BUSY_STATUS__RDRET0_MASK__CI__VI 0x00040000L -#define MC_ARB_BUSY_STATUS__RDRET1_MASK__CI__VI 0x00080000L -#define MC_ARB_BUSY_STATUS__REM_RD0_MASK__CI__VI 0x10000000L -#define MC_ARB_BUSY_STATUS__REM_RD1_MASK__CI__VI 0x20000000L -#define MC_ARB_BUSY_STATUS__REM_WR0_MASK__CI__VI 0x40000000L -#define MC_ARB_BUSY_STATUS__REM_WR1_MASK__CI__VI 0x80000000L -#define MC_ARB_BUSY_STATUS__REPLAY0_MASK__CI__VI 0x00010000L -#define MC_ARB_BUSY_STATUS__REPLAY1_MASK__CI__VI 0x00020000L -#define MC_ARB_BUSY_STATUS__RTT0_MASK__CI__VI 0x04000000L -#define MC_ARB_BUSY_STATUS__RTT1_MASK__CI__VI 0x08000000L -#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK__CI__VI 0x00004000L -#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK__CI__VI 0x00008000L -#define MC_ARB_BUSY_STATUS__WCDR0_MASK__CI 0x01000000L -#define MC_ARB_BUSY_STATUS__WCDR1_MASK__CI 0x02000000L -#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK__CI__VI 0x00000100L -#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK__CI__VI 0x00000200L -#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK__CI__VI 0x00000400L -#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK__CI__VI 0x00000800L -#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x00002000L -#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x00000001L -#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x0000007eL -#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x00001f80L -#define MC_ARB_CG__ARB_CG_REQ_MASK__SI 0x00ff0000L -#define MC_ARB_CG__ARB_CG_RESP_MASK__SI 0xff000000L -#define MC_ARB_CG__CG_ARB_REQ_MASK 0x000000ffL -#define MC_ARB_CG__CG_ARB_RESP_MASK 0x0000ff00L -#define MC_ARB_CG__RSV_0_MASK__CI__VI 0x00ff0000L -#define MC_ARB_CG__RSV_1_MASK__CI__VI 0xff000000L -#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000L -#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0x000000ffL -#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0x0000ff00L -#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0x00ff0000L -#define MC_ARB_DRAM_TIMING2_2__BUS_TURN_MASK__SI 0x1f000000L -#define MC_ARB_DRAM_TIMING2_2__RAS2RAS_MASK__SI 0x000000ffL -#define MC_ARB_DRAM_TIMING2_2__RP_MASK__SI 0x0000ff00L -#define MC_ARB_DRAM_TIMING2_2__WRPLUSRP_MASK__SI 0x00ff0000L -#define MC_ARB_DRAM_TIMING2_3__BUS_TURN_MASK__SI 0x1f000000L -#define MC_ARB_DRAM_TIMING2_3__RAS2RAS_MASK__SI 0x000000ffL -#define MC_ARB_DRAM_TIMING2_3__RP_MASK__SI 0x0000ff00L -#define MC_ARB_DRAM_TIMING2_3__WRPLUSRP_MASK__SI 0x00ff0000L -#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000L -#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0x000000ffL -#define MC_ARB_DRAM_TIMING2__RP_MASK 0x0000ff00L -#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0x00ff0000L -#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0x000000ffL -#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0x0000ff00L -#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0x00ff0000L -#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000L -#define MC_ARB_DRAM_TIMING_2__ACTRD_MASK__SI 0x000000ffL -#define MC_ARB_DRAM_TIMING_2__ACTWR_MASK__SI 0x0000ff00L -#define MC_ARB_DRAM_TIMING_2__RASMACTRD_MASK__SI 0x00ff0000L -#define MC_ARB_DRAM_TIMING_2__RASMACTWR_MASK__SI 0xff000000L -#define MC_ARB_DRAM_TIMING_3__ACTRD_MASK__SI 0x000000ffL -#define MC_ARB_DRAM_TIMING_3__ACTWR_MASK__SI 0x0000ff00L -#define MC_ARB_DRAM_TIMING_3__RASMACTRD_MASK__SI 0x00ff0000L -#define MC_ARB_DRAM_TIMING_3__RASMACTWR_MASK__SI 0xff000000L -#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0x000000ffL -#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0x0000ff00L -#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0x00ff0000L -#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000L -#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK__CI__VI 0xffffff80L -#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x00000010L -#define MC_ARB_FED_CNTL__MODE_MASK 0x00000003L -#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK__CI__VI 0x00000020L -#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK__CI__VI 0x00000040L -#define MC_ARB_FED_CNTL__WR_ERR_MASK 0x0000000cL -#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0x0000000fL -#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0x000000f0L -#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L -#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x00000100L -#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x00000200L -#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0x0000000fL -#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0x000000f0L -#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L -#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x00000100L -#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x00000200L -#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0x000000ffL -#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0x0000ff00L -#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0x00ff0000L -#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000L -#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0x0000ff00L -#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0x00ff0000L -#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000L -#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0x000000ffL -#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x00000018L -#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x00000004L -#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x00000003L -#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x00000020L -#define MC_ARB_GECC2_MISC__COL10_HACK_MASK__CI__VI 0x00000010L -#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK__CI__VI 0x00000020L -#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK__CI 0xffffff80L -#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK__CI__VI 0x00000040L -#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0x0000000fL -#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x00000100L -#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x00001000L -#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x00000001L -#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x00000010L -#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x00000400L -#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x00004000L -#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x00000004L -#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x00000040L -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK__CI__VI 0x01000000L -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK__CI__VI 0x10000000L -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK__CI__VI 0x00010000L -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK__CI__VI 0x00100000L -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK__CI__VI 0x02000000L -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK__CI__VI 0x20000000L -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK__CI__VI 0x00020000L -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK__CI__VI 0x00200000L -#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x00000008L -#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x00000080L -#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x00000800L -#define MC_ARB_GECC2_STATUS__RSVD3_MASK__CI__VI 0x00008000L -#define MC_ARB_GECC2_STATUS__RSVD4_MASK__CI__VI 0x000c0000L -#define MC_ARB_GECC2_STATUS__RSVD5_MASK__CI__VI 0x00c00000L -#define MC_ARB_GECC2_STATUS__RSVD6_MASK__CI__VI 0x0c000000L -#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x00000200L -#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x00002000L -#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x00000002L -#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x00000020L -#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x00004000L -#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x001f8000L -#define MC_ARB_GECC2__ECC_MODE_MASK 0x00000006L -#define MC_ARB_GECC2__ENABLE_MASK 0x00000001L -#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x00000060L -#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x00000780L -#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x00000018L -#define MC_ARB_GECC2__READ_ERR_MASK 0x00003800L -#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK__CI__VI 0x00400000L -#define MC_ARB_GECC2__WRADDR_CONV_MASK__CI__VI 0x00200000L -#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK__CI__VI 0x00000200L -#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK__CI__VI 0x00000800L -#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK__CI__VI 0x003fc000L -#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK__CI__VI 0x00000100L -#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK__CI__VI 0x01c00000L -#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK__CI__VI 0x00003000L -#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK__CI__VI 0x00000400L -#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK__CI__VI 0x00000200L -#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK__CI__VI 0x00000800L -#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK__CI__VI 0x003fc000L -#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK__CI__VI 0x00000100L -#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK__CI__VI 0x01c00000L -#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK__CI__VI 0x00003000L -#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK__CI__VI 0x00000400L -#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK__CI__VI 0x000000ffL -#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK__CI__VI 0x0000ff00L -#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK__CI__VI 0x00ff0000L -#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK__CI__VI 0xff000000L -#define MC_ARB_LAZY0_RD__GROUP0_MASK 0x000000ffL -#define MC_ARB_LAZY0_RD__GROUP1_MASK 0x0000ff00L -#define MC_ARB_LAZY0_RD__GROUP2_MASK 0x00ff0000L -#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000L -#define MC_ARB_LAZY0_WR__GROUP0_MASK 0x000000ffL -#define MC_ARB_LAZY0_WR__GROUP1_MASK 0x0000ff00L -#define MC_ARB_LAZY0_WR__GROUP2_MASK 0x00ff0000L -#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000L -#define MC_ARB_LAZY1_RD__GROUP4_MASK 0x000000ffL -#define MC_ARB_LAZY1_RD__GROUP5_MASK 0x0000ff00L -#define MC_ARB_LAZY1_RD__GROUP6_MASK 0x00ff0000L -#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000L -#define MC_ARB_LAZY1_WR__GROUP4_MASK 0x000000ffL -#define MC_ARB_LAZY1_WR__GROUP5_MASK 0x0000ff00L -#define MC_ARB_LAZY1_WR__GROUP6_MASK 0x00ff0000L -#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000L -#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0x00e00000L -#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x00040000L -#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x00080000L -#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x00100000L -#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x00010000L -#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0x000000ffL -#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0x0000ff00L -#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x00020000L -#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0x00e00000L -#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x00040000L -#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x00080000L -#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x00100000L -#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x00010000L -#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0x000000ffL -#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0x0000ff00L -#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x00020000L -#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK__CI__VI 0x000000ffL -#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK__CI__VI 0x0000ff00L -#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK__CI__VI 0x00040000L -#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK__CI__VI 0x00080000L -#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK__CI__VI 0x00010000L -#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK__CI__VI 0x00020000L -#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK__CI__VI 0xffffffffL -#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK__CI__VI 0xffffffffL -#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x00010000L -#define MC_ARB_MINCLKS__READ_CLKS_MASK 0x000000ffL -#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK__CI__VI 0x00060000L -#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0x0000ff00L -#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000L -#define MC_ARB_MISC2__GECC_MASK 0x00040000L -#define MC_ARB_MISC2__GECC_RST_MASK 0x00080000L -#define MC_ARB_MISC2__GECC_STATUS_MASK 0x00100000L -#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x00000800L -#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x00002000L -#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x00001000L -#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x0003c000L -#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000L -#define MC_ARB_MISC2__SCRAMBLE_2D_MASK 0x00000018L -#define MC_ARB_MISC2__SCRAMBLE_ENABLE_MASK 0x00000001L -#define MC_ARB_MISC2__SCRAMBLE_MIX_MASK 0x00000002L -#define MC_ARB_MISC2__SCRAMBLE_WITH_ADDR_MASK 0x00000004L -#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000L -#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x01e00000L -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x00000040L -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x00000080L -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x00000100L -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x00000200L -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x00000400L -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x00000020L -#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000L -#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0x0e000000L -#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK__CI__VI 0x00000001L -#define MC_ARB_MISC3__TBD_FIELD_MASK__CI 0xfffffffeL -#define MC_ARB_MISC__ACPURG_STALL_MASK__CI__VI 0x80000000L -#define MC_ARB_MISC__CALI_ENABLE_MASK 0x00100000L -#define MC_ARB_MISC__CALI_RATES_MASK 0x00600000L -#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x000007f8L -#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x00800000L -#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x01000000L -#define MC_ARB_MISC__DISPURG_STALL_MASK 0x02000000L -#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000L -#define MC_ARB_MISC__EXTEND_WEIGHT_MASK__CI__VI 0x40000000L -#define MC_ARB_MISC__HARSHNESS_MASK 0x0007f800L -#define MC_ARB_MISC__IDLE_RFSH_MASK 0x00000002L -#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x00080000L -#define MC_ARB_MISC__STICKY_RFSH_MASK 0x00000001L -#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x00000004L -#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK__CI 0x00000001L -#define MC_ARB_PERF_MON_CNTL0__ALLOW_WRAP_MASK__SI 0x10000000L -#define MC_ARB_PERF_MON_CNTL0__START_MODE_MASK__SI 0x03000000L -#define MC_ARB_PERF_MON_CNTL0__START_THRESH_MASK__SI 0x00000fffL -#define MC_ARB_PERF_MON_CNTL0__STOP_MODE_MASK__SI 0x0c000000L -#define MC_ARB_PERF_MON_CNTL0__STOP_THRESH_MASK__SI 0x00fff000L -#define MC_ARB_PERF_MON_CNTL1__MON0_ID_MASK__SI 0x00fc0000L -#define MC_ARB_PERF_MON_CNTL1__MON1_ID_MASK__SI 0x3f000000L -#define MC_ARB_PERF_MON_CNTL1__START_TRIG_ID_MASK__SI 0x00000fc0L -#define MC_ARB_PERF_MON_CNTL1__STOP_TRIG_ID_MASK__SI 0x0003f000L -#define MC_ARB_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK__SI 0x0000003fL -#define MC_ARB_PERF_MON_CNTL2__MON0_ID_HI_MASK__SI 0x00030000L -#define MC_ARB_PERF_MON_CNTL2__MON1_ID_HI_MASK__SI 0x000c0000L -#define MC_ARB_PERF_MON_CNTL2__MON2_ID_MASK__SI 0x000000ffL -#define MC_ARB_PERF_MON_CNTL2__MON3_ID_MASK__SI 0x0000ff00L -#define MC_ARB_PERF_MON_CNTL2__START_TRIG_ID_HI_MASK__SI 0x00c00000L -#define MC_ARB_PERF_MON_CNTL2__STOP_TRIG_ID_HI_MASK__SI 0x03000000L -#define MC_ARB_PERF_MON_CNTL2__THRESH_CNTR_ID_HI_MASK__SI 0x00300000L -#define MC_ARB_PERF_MON_RSLT0__COUNT_MASK__SI 0xffffffffL -#define MC_ARB_PERF_MON_RSLT1__COUNT_MASK__SI 0xffffffffL -#define MC_ARB_PERF_MON_RSLT2__COUNT_MASK__SI 0xffffffffL -#define MC_ARB_PERF_MON_RSLT3__COUNT_MASK__SI 0xffffffffL -#define MC_ARB_PM_CNTL__ALLOW_STOP_SEL0_MASK__SI 0x01000000L -#define MC_ARB_PM_CNTL__ALLOW_STOP_SEL1_MASK__SI 0x02000000L -#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x00000020L -#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0x00f00000L -#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x00000040L -#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x00040000L -#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x00080000L -#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x00000003L -#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x00000004L -#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x00000008L -#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x00000080L -#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x00000300L -#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x00000400L -#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x00000800L -#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x00004000L -#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L -#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x00001000L -#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x00002000L -#define MC_ARB_PM_CNTL__RSV_0_MASK__CI 0x00030000L -#define MC_ARB_PM_CNTL__RSV_1_MASK__CI 0x01000000L -#define MC_ARB_PM_CNTL__RSV_2_MASK__CI 0x02000000L -#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x00000010L -#define MC_ARB_PM_CNTL__STUTTER_MODE_MASK__SI 0x00030000L -#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x00080000L -#define MC_ARB_POP__ENABLE_ARB_MASK 0x00000001L -#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x00040000L -#define MC_ARB_POP__POP_DEPTH_MASK 0x0000003cL -#define MC_ARB_POP__QUICK_STOP_MASK 0x00020000L -#define MC_ARB_POP__SKID_DEPTH_MASK 0x00007000L -#define MC_ARB_POP__SPEC_OPEN_MASK 0x00000002L -#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x00018000L -#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0x00000fc0L -#define MC_ARB_RAMCFG__BURSTLENGTH_MASK__SI 0x00000200L -#define MC_ARB_RAMCFG__BURST_TIME_MASK__SI 0x0003e000L -#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x00000100L -#define MC_ARB_RAMCFG__CHANSIZE_OVERRIDE_MASK__SI 0x00000800L -#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x00000003L -#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0x000000c0L -#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x00001000L -#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x00000004L -#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x00000038L -#define MC_ARB_RAMCFG__REQUEST_512B_MASK__SI 0x00000400L -#define MC_ARB_RAMCFG__RSV_1_MASK__CI__VI 0x00000200L -#define MC_ARB_RAMCFG__RSV_2_MASK__CI__VI 0x00000400L -#define MC_ARB_RAMCFG__RSV_3_MASK__CI__VI 0x00000800L -#define MC_ARB_RAMCFG__RSV_4_MASK__CI__VI 0x0003e000L -#define MC_ARB_REFRESH_SCALE_CNTL__MC_ARB_REFRESH_SCALE_MASK__SI 0x0000ff00L -#define MC_ARB_REFRESH_SCALE_CNTL__MC_WAIT_PERIOD_MASK__SI 0x000000ffL -#define MC_ARB_REMREQ__RD_WATER_MASK 0x000000ffL -#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0x00f00000L -#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0x000f0000L -#define MC_ARB_REMREQ__WR_WATER_MASK 0x0000ff00L -#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x00000080L -#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x00007f00L -#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x00000040L -#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x00000001L -#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x00000002L -#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x00000020L -#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK__CI__VI 0x00008000L -#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x00000010L -#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x00000008L -#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x00000004L -#define MC_ARB_RET_CREDITS2__ACP_WR_MASK__CI__VI 0x000000ffL -#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0x00ff0000L -#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0x0000ff00L -#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0x000000ffL -#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000L -#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0x0000ff00L -#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0x000000ffL -#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0x00ff0000L -#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0x0f000000L -#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x00000800L -#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x00000001L -#define MC_ARB_RFSH_CNTL__URG0_MASK 0x0000003eL -#define MC_ARB_RFSH_CNTL__URG1_MASK 0x000007c0L -#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0x000000ffL -#define MC_ARB_RFSH_RATE__POWERMODE1_MASK__SI 0x0000ff00L -#define MC_ARB_RFSH_RATE__POWERMODE2_MASK__SI 0x00ff0000L -#define MC_ARB_RFSH_RATE__POWERMODE3_MASK__SI 0xff000000L -#define MC_ARB_RSV0__TBD_FIELD_MASK__SI 0xffffffffL -#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x00000100L -#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x00000200L -#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x00000400L -#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x01000000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x00008000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x00010000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x00020000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x00040000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x00080000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x00100000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x00200000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x00400000L -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x00800000L -#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x00000001L -#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x00000010L -#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x00000020L -#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x02000000L -#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x00000002L -#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0x0000000cL -#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x00004000L -#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x00000040L -#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x00003800L -#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x00000080L -#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0x000fe000L -#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x00001fc0L -#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x0000001fL -#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x01f00000L -#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000L -#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000L -#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x00000020L -#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x00002000L -#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x00001000L -#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0x00000fc0L -#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x0000003fL -#define MC_ARB_RTT_DATA__PATTERN_MASK 0x000000ffL -#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x00000003L -#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0x0000000cL -#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0x00000ff0L -#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x01fe0000L -#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x0001f000L -#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000L -#define MC_ARB_SCRAMBLE_KEY0__KEY_MASK 0xffffffffL -#define MC_ARB_SCRAMBLE_KEY1__KEY_MASK 0xffffffffL -#define MC_ARB_SPARE0__BIT_MASK__SI 0xffffffffL -#define MC_ARB_SPARE1__BIT_MASK__SI 0xffffffffL -#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x00000100L -#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0x000000ffL -#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000L -#define MC_ARB_SQM_CNTL__RATIO_MASK 0x00ff0000L -#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK__CI__VI 0x00000200L -#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK__CI__VI 0x0000fc00L -#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK__SI 0x0000fe00L -#define MC_ARB_SSM__FORMAT_MASK__CI 0x0000001fL -#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x00000006L -#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x00000001L -#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x00000010L -#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x00000008L -#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x00000006L -#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x00000001L -#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x00000010L -#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x00000008L -#define MC_ARB_WCDR_2__DEBUG_0_MASK__SI__CI 0x00000200L -#define MC_ARB_WCDR_2__DEBUG_1_MASK__SI__CI 0x00000400L -#define MC_ARB_WCDR_2__DEBUG_2_MASK__SI__CI 0x00000800L -#define MC_ARB_WCDR_2__DEBUG_3_MASK__SI__CI 0x00001000L -#define MC_ARB_WCDR_2__DEBUG_4_MASK__SI__CI 0x00002000L -#define MC_ARB_WCDR_2__DEBUG_5_MASK__SI__CI 0x00004000L -#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK__SI__CI 0x0000000fL -#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK__SI__CI 0x000001f0L -#define MC_ARB_WCDR__IDLE_BURST_MASK__SI__CI 0x00001f80L -#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK__SI__CI 0x00002000L -#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK__SI__CI 0x00010000L -#define MC_ARB_WCDR__IDLE_ENABLE_MASK__SI__CI 0x00000001L -#define MC_ARB_WCDR__IDLE_PERIOD_MASK__SI__CI 0x0000007cL -#define MC_ARB_WCDR__IDLE_WAKEUP_MASK__SI__CI 0x0000c000L -#define MC_ARB_WCDR__SEQ_IDLE_MASK__SI__CI 0x00000002L -#define MC_ARB_WCDR__WPRE_ENABLE_MASK__SI__CI 0x00020000L -#define MC_ARB_WCDR__WPRE_INC_READ_MASK__SI__CI 0x02000000L -#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK__SI__CI 0x08000000L -#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK__SI__CI 0x04000000L -#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK__SI__CI 0x01c00000L -#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK__SI__CI 0x003c0000L -#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK__SI__CI 0x10000000L -#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK__CI__VI 0x00000800L -#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK__CI__VI 0x00001000L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x00000008L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x00000010L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x00000020L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x00000040L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x00000080L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x00000100L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x00000200L -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x00000400L -#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK__CI__VI 0x00002000L -#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x00000004L -#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x00000003L -#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK__CI__VI 0x00000800L -#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK__CI__VI 0x00001000L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x00000008L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x00000010L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x00000020L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x00000040L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x00000080L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x00000100L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x00000200L -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x00000400L -#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK__CI__VI 0x00002000L -#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x00000004L -#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x00000003L -#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x00000003L -#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0x0000000cL -#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x00000030L -#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0x000000c0L -#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x00000300L -#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0x00000c00L -#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x00003000L -#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0x0000c000L -#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0x00ff0000L -#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x00000003L -#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0x0000000cL -#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x00000030L -#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0x000000c0L -#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x00000300L -#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0x00000c00L -#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x00003000L -#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0x0000c000L -#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0x00ff0000L -#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK__SI__CI 0x000000f0L -#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK__SI__CI 0x02000000L -#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK__SI__CI 0x00ffff00L -#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK__SI__CI 0x01000000L -#define MC_BIST_AUTO_CNTL__MOP_MASK__SI__CI 0x00000003L -#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK__SI__CI 0x00000004L -#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK__SI__CI 0x00000002L -#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK__SI__CI 0x00010000L -#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK__SI__CI 0x00020000L -#define MC_BIST_CMD_CNTL__DONE_MASK__SI__CI 0x80000000L -#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK__SI__CI 0x10000000L -#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK__SI__CI 0x20000000L -#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK__SI__CI 0x0000fff0L -#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK__SI__CI 0x0ffc0000L -#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK__SI__CI 0x00000008L -#define MC_BIST_CMD_CNTL__RESET_MASK__SI__CI 0x00000001L -#define MC_BIST_CMD_CNTL__STATUS_CH_MASK__SI__CI 0x40000000L -#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK__SI__CI 0x0000001fL -#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK__SI__CI 0x00000100L -#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK__SI__CI 0x0001f000L -#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK__SI__CI 0x00100000L -#define MC_BIST_CMP_CNTL__CMP_MASK__SI__CI 0x00030000L -#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK__SI__CI 0x00000ff0L -#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK__SI__CI 0x0000000fL -#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK__SI__CI 0x00300000L -#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK__SI__CI 0x00002000L -#define MC_BIST_CMP_CNTL__DAT_MODE_MASK__SI__CI 0x00040000L -#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK__SI__CI 0x00080000L -#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK__SI__CI 0x00004000L -#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK__SI__CI 0x00008000L -#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK__SI__CI 0x00001000L -#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK__SI__CI 0xffc00000L -#define MC_BIST_CNTL__ADR_MODE_MASK__SI__CI 0x00000020L -#define MC_BIST_CNTL__DAT_MODE_MASK__SI__CI 0x00000040L -#define MC_BIST_CNTL__DONE_MASK__SI__CI 0x40000000L -#define MC_BIST_CNTL__ENABLE_D0_MASK__SI__CI 0x00001000L -#define MC_BIST_CNTL__ENABLE_D1_MASK__SI__CI 0x00002000L -#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK__SI__CI 0x00004000L -#define MC_BIST_CNTL__LOAD_RTDATA_MASK__SI__CI 0x80000000L -#define MC_BIST_CNTL__LOOP_CNT_MASK__SI__CI 0x0fff0000L -#define MC_BIST_CNTL__LOOP_MASK__SI__CI 0x00000c00L -#define MC_BIST_CNTL__MOP_MODE_MASK__SI__CI 0x00000010L -#define MC_BIST_CNTL__PTR_RST_D0_MASK__SI__CI 0x00000004L -#define MC_BIST_CNTL__PTR_RST_D1_MASK__SI__CI 0x00000008L -#define MC_BIST_CNTL__RESET_MASK__SI__CI 0x00000001L -#define MC_BIST_CNTL__RUN_MASK__SI__CI 0x00000002L -#define MC_BIST_DATA_MASK__MASK_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD0__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD1__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD2__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD3__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD4__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD5__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD6__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DATA_WORD7__DATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK__SI__CI 0x00000040L -#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK__SI__CI 0x00000100L -#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK__SI__CI 0x00000020L -#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK__SI__CI 0x00000080L -#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK__SI__CI 0x00000200L -#define MC_BIST_DIR_CNTL__EOB_MASK__SI__CI 0x00000008L -#define MC_BIST_DIR_CNTL__MOP3_MASK__SI__CI 0x00000400L -#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK__SI__CI 0x00000010L -#define MC_BIST_DIR_CNTL__MOP_MASK__SI__CI 0x00000007L -#define MC_BIST_EADDR__BANK_MASK__SI__CI 0x0f000000L -#define MC_BIST_EADDR__COLH_MASK__SI__CI 0x20000000L -#define MC_BIST_EADDR__COL_MASK__SI__CI 0x000003ffL -#define MC_BIST_EADDR__RANK_MASK__SI__CI 0x10000000L -#define MC_BIST_EADDR__ROWH_MASK__SI__CI 0xc0000000L -#define MC_BIST_EADDR__ROW_MASK__SI__CI 0x00fffc00L -#define MC_BIST_MISMATCH_ADDR__BANK_MASK__SI__CI 0x0f000000L -#define MC_BIST_MISMATCH_ADDR__COLH_MASK__SI__CI 0x20000000L -#define MC_BIST_MISMATCH_ADDR__COL_MASK__SI__CI 0x000003ffL -#define MC_BIST_MISMATCH_ADDR__RANK_MASK__SI__CI 0x10000000L -#define MC_BIST_MISMATCH_ADDR__ROWH_MASK__SI__CI 0xc0000000L -#define MC_BIST_MISMATCH_ADDR__ROW_MASK__SI__CI 0x00fffc00L -#define MC_BIST_RDATA_EDC__EDC_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_MASK__MASK_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD0__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD1__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD2__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD3__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD4__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD5__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD6__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_RDATA_WORD7__RDATA_MASK__SI__CI 0xffffffffL -#define MC_BIST_SADDR__BANK_MASK__SI__CI 0x0f000000L -#define MC_BIST_SADDR__COLH_MASK__SI__CI 0x20000000L -#define MC_BIST_SADDR__COL_MASK__SI__CI 0x000003ffL -#define MC_BIST_SADDR__RANK_MASK__SI__CI 0x10000000L -#define MC_BIST_SADDR__ROWH_MASK__SI__CI 0xc0000000L -#define MC_BIST_SADDR__ROW_MASK__SI__CI 0x00fffc00L -#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000L -#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L -#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L -#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L -#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L -#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L -#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L -#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L -#define MC_CG_CONFIG__INDEX_MASK 0x003fffc0L -#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L -#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L -#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L -#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L -#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x00000030L -#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffffL -#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK__CI 0x00000080L -#define MC_CITF_CNTL__DUMMY_MASK__SI 0x00003f80L -#define MC_CITF_CNTL__EXEMPTPM_MASK 0x00000008L -#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x00000030L -#define MC_CITF_CNTL__IGNOREPM_MASK 0x00000004L -#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x00000040L -#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK__CI 0x00000100L -#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x02000000L -#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x01000000L -#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0x0000ff00L -#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0x000000ffL -#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0x00ff0000L -#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK__CI 0x00020000L -#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0x0000ff00L -#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0x000000ffL -#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x0000003fL -#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0x00000fc0L -#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0x000000ffL -#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0x0000ff00L -#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x0000001eL -#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK__CI__VI 0x000003c0L -#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x00000020L -#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x00000001L -#define MC_CITF_DAGB_DLY__DLY_MASK 0x0000001fL -#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK__CI__VI 0x0000003fL -#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK__CI__VI 0x00000fc0L -#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0x00fc0000L -#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x0003f000L -#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000L -#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x0000003fL -#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x00040000L -#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0x00000fc0L -#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x0000003fL -#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x0003f000L -#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x00040000L -#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L -#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x0000003fL -#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x0003f000L -#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x00040000L -#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0x00000fc0L -#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x0000003fL -#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x0003f000L -#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define MC_CITF_PERF_MON_CNTL0__ALLOW_WRAP_MASK__SI 0x10000000L -#define MC_CITF_PERF_MON_CNTL0__START_MODE_MASK__SI 0x03000000L -#define MC_CITF_PERF_MON_CNTL0__START_THRESH_MASK__SI 0x00000fffL -#define MC_CITF_PERF_MON_CNTL0__STOP_MODE_MASK__SI 0x0c000000L -#define MC_CITF_PERF_MON_CNTL0__STOP_THRESH_MASK__SI 0x00fff000L -#define MC_CITF_PERF_MON_CNTL1__MON0_ID_MASK__SI 0x00fc0000L -#define MC_CITF_PERF_MON_CNTL1__MON1_ID_MASK__SI 0x3f000000L -#define MC_CITF_PERF_MON_CNTL1__START_TRIG_ID_MASK__SI 0x00000fc0L -#define MC_CITF_PERF_MON_CNTL1__STOP_TRIG_ID_MASK__SI 0x0003f000L -#define MC_CITF_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK__SI 0x0000003fL -#define MC_CITF_PERF_MON_CNTL2__CID_MASK__CI__VI 0x000000ffL -#define MC_CITF_PERF_MON_CNTL2__CID_MASK__SI 0x000001ffL -#define MC_CITF_PERF_MON_CNTL2__MON0_ID6_MASK__SI 0x00001000L -#define MC_CITF_PERF_MON_CNTL2__MON1_ID6_MASK__SI 0x00002000L -#define MC_CITF_PERF_MON_CNTL2__START_TRIG_ID6_MASK__SI 0x00000400L -#define MC_CITF_PERF_MON_CNTL2__STOP_TRIG_ID6_MASK__SI 0x00000800L -#define MC_CITF_PERF_MON_CNTL2__THRESH_CNTR_ID6_MASK__SI 0x00000200L -#define MC_CITF_PERF_MON_RSLT0__COUNT_MASK__SI 0xffffffffL -#define MC_CITF_PERF_MON_RSLT1__COUNT_MASK__SI 0xffffffffL -#define MC_CITF_PERF_MON_RSLT2__RSLT1_HIGH_MASK__SI 0x0000003fL -#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x00004000L -#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x0000007fL -#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x00003f80L -#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x00000001L -#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x00000002L -#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x00000010L -#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x00000020L -#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x00000004L -#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x00000008L -#define MC_CITF_WTM_RD_CNTL__DIABLE_LOCAL_MASK__SI 0x02000000L -#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK__CI__VI 0x02000000L -#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x01000000L -#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x00000007L -#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x00000038L -#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L -#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L -#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x00007000L -#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x00038000L -#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L -#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L -#define MC_CITF_WTM_WR_CNTL__DIABLE_LOCAL_MASK__SI 0x02000000L -#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK__CI__VI 0x02000000L -#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x01000000L -#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x00000007L -#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x00000038L -#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L -#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L -#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x00007000L -#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x00038000L -#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L -#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L -#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0x00000f00L -#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK__CI__VI 0x02000000L -#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK__CI__VI 0x00006000L -#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK__CI__VI 0x08000000L -#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK__CI__VI 0x00060000L -#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x00000001L -#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x00000002L -#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK__CI__VI 0x04000000L -#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK__CI__VI 0x00018000L -#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK__CI__VI 0x10000000L -#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK__CI__VI 0x00180000L -#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x00000004L -#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x00000008L -#define MC_CITF_XTRA_ENABLE__DUMMY0_MASK__SI 0x00000040L -#define MC_CITF_XTRA_ENABLE__DUMMY1_MASK__SI 0x00000080L -#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK__CI__VI 0x00600000L -#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK__CI__VI 0x01800000L -#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x00000010L -#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK__CI__VI 0x60000000L -#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x00001000L -#define MC_CITF_XTRA_ENABLE__TC3_RD_MASK__SI 0x00000020L -#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L -#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L -#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L -#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L -#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L -#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L -#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000L -#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L -#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000L -#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L -#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L -#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L -#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L -#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK__SI 0x00000010L -#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK__SI 0x00000001L -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK__SI 0x00100000L -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK__SI 0x00010000L -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK__SI 0x10000000L -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK__SI 0x01000000L -#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK__SI 0x00001000L -#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK__SI 0x00000100L -#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK__CI 0x00000004L -#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK__CI 0x00000001L -#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK__CI 0x00000002L -#define MC_DLB_CONFIG0__MASK_MASK__CI 0x000000f0L -#define MC_DLB_CONFIG0__PTR_MASK__CI 0x0003ff00L -#define MC_DLB_CONFIG1__DATA_MASK__CI 0xffffffffL -#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK__CI 0x00000008L -#define MC_DLB_MISCCTRL0__DATA_SEL_MASK__CI 0x000000f0L -#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK__CI 0x00000002L -#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK__CI 0x00000004L -#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK__CI 0x00007f00L -#define MC_DLB_MISCCTRL0__UDD_MASK__CI 0xffff0000L -#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK__CI 0x00000001L -#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK__CI 0xffffffffL -#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK__CI 0x04000000L -#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK__CI 0x00040000L -#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK__CI 0x00080000L -#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK__CI 0x00020000L -#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK__CI 0x0001ffffL -#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK__CI 0x20000000L -#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK__CI 0x10000000L -#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK__CI 0x40000000L -#define MC_DLB_MISCCTRL2__STOP_CLK_MASK__CI 0x00200000L -#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK__CI 0x00100000L -#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK__CI 0x03000000L -#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK__CI 0x00000004L -#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK__CI 0x00001c00L -#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK__CI 0x00000040L -#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK__CI 0x00000002L -#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK__CI 0x00000300L -#define MC_DLB_SETUPFIFO__STROBE_MASK__CI 0x000f0000L -#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK__CI 0x00000030L -#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__CI 0x00000008L -#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK__CI 0x00000001L -#define MC_DLB_SETUPSWEEP__CONFIG_MASK__CI 0x00000002L -#define MC_DLB_SETUPSWEEP__DLLDLY_MASK__CI 0x000000f0L -#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK__CI 0x00001f00L -#define MC_DLB_SETUPSWEEP__DLL_RST_MASK__CI 0x00000001L -#define MC_DLB_SETUPSWEEP__MASTER_MASK__CI 0x00000004L -#define MC_DLB_SETUP__CHK_DATA_BITS_MASK__CI 0x00ff0000L -#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK__CI 0x00000008L -#define MC_DLB_SETUP__DLB_EN_MASK__CI 0x00000001L -#define MC_DLB_SETUP__DLB_FIFO_EN_MASK__CI 0x00000002L -#define MC_DLB_SETUP__DLB_PRBS_EN_MASK__CI 0x00000010L -#define MC_DLB_SETUP__DLB_STATUS_EN_MASK__CI 0x00000004L -#define MC_DLB_SETUP__MEM_BIT_SEL_MASK__CI 0x1f000000L -#define MC_DLB_SETUP__PRBS_CHK_RST_MASK__CI 0x00000040L -#define MC_DLB_SETUP__PRBS_GEN_RST_MASK__CI 0x00000020L -#define MC_DLB_SETUP__PRBS_PHY_RST_MASK__CI 0x00000080L -#define MC_DLB_SETUP__QDR_MODE_MASK__CI 0x00000100L -#define MC_DLB_SETUP__RXTXLP_EN_MASK__CI 0x80000000L -#define MC_DLB_STATUS_MISC0__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS_MISC1__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS_MISC2__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS_MISC3__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS_MISC4__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS_MISC5__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS_MISC6__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS_MISC7__DATA_MASK__CI 0xffffffffL -#define MC_DLB_STATUS__LOCK_MASK__CI 0x000000f0L -#define MC_DLB_STATUS__STICK_ERROR_MASK__CI 0x0000000fL -#define MC_DLB_STATUS__SWEEP_DONE_MASK__CI 0x00000f00L -#define MC_DLB_WRITE_MASK__BIT_MASK_MASK__CI 0x003fffffL -#define MC_DLB_WRITE_MASK__CH_MASK_MASK__CI 0x0f000000L -#define MC_HUB_MISC_DBG__CTRL0_MASK__CI 0x00001f00L -#define MC_HUB_MISC_DBG__CTRL1_MASK__CI 0x0003e000L -#define MC_HUB_MISC_DBG__SELECT0_MASK__SI__CI 0x0000000fL -#define MC_HUB_MISC_DBG__SELECT1_MASK__SI__CI 0x000000f0L -#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffffL -#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x00040000L -#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0x00000fc0L -#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x0000003fL -#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x0003f000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK__CI 0x01000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK__CI 0x02000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK__CI 0x04000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK__SI 0x00000001L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK__CI 0x08000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK__SI 0x00000002L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK__CI__VI 0x00000100L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK__SI 0x00000400L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK__CI__VI 0x00000200L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK__SI 0x00000800L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA0_READ_MASK__SI 0x00000100L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA0_WRITE_MASK__SI 0x00000200L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA1_READ_MASK__SI 0x00000010L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA1_WRITE_MASK__SI 0x00000020L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK__CI__VI 0x00000001L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK__SI 0x00000004L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK__CI__VI 0x00000002L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK__SI 0x00000008L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK__CI__VI 0x00004000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK__SI 0x00010000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK__CI__VI 0x00008000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK__SI 0x00020000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK__CI 0x00100000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK__CI 0x00200000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK__CI__VI 0x00010000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK__SI 0x00040000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK__CI__VI 0x00020000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK__SI 0x00080000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK__CI__VI 0x00000004L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK__SI 0x00000040L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK__CI__VI 0x00000008L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK__SI 0x00000080L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK__CI__VI 0x00000010L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK__CI__VI 0x00000020L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK__CI__VI 0x00000040L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK__CI__VI 0x00000080L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK__CI__VI 0x00001000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK__SI 0x00004000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK__CI__VI 0x00002000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK__SI 0x00008000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK__CI__VI 0x00000400L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK__SI 0x00001000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK__CI__VI 0x00000800L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK__SI 0x00002000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK__CI 0x00400000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK__SI 0x01000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK__CI 0x00800000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK__SI 0x02000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VGT_READ_MASK__SI 0x00400000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VGT_WRITE_MASK__SI 0x00800000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK__CI__VI 0x00040000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK__SI 0x00100000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK__CI__VI 0x00080000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK__SI 0x00200000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK__CI 0x10000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK__SI__VI 0x04000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK__CI 0x20000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK__SI__VI 0x08000000L -#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x00000003L -#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x00000018L -#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x00000004L -#define MC_HUB_MISC_POWER__SS_STUTTER_MODE_MASK__SI 0x00000020L -#define MC_HUB_MISC_POWER__STUTTER_LPT_MODE_MASK__SI 0x00000040L -#define MC_HUB_MISC_POWER__STUTTER_MODE_MASK__SI 0x00000003L -#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x00040000L -#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0x00000fc0L -#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x0000003fL -#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x0003f000L -#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x00000001L -#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x00000002L -#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x00040000L -#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L -#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x0000003fL -#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x0003f000L -#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK__CI__VI 0x00000003L -#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK__CI__VI 0x0000007cL -#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK__CI__VI 0x00010000L -#define MC_HUB_RDREQ_ACPG__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK__CI__VI 0x00020000L -#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK__CI__VI 0x00040000L -#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK__CI__VI 0x01f80000L -#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK__CI__VI 0x00010000L -#define MC_HUB_RDREQ_ACPO__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK__CI__VI 0x00020000L -#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK__CI__VI 0x00040000L -#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK__CI__VI 0x01f80000L -#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK__CI 0x00100000L -#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x00000004L -#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x00000008L -#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x00000020L -#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x00000040L -#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x00000080L -#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x00000100L -#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L -#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x00000001L -#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_RDREQ_CPC__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_RDREQ_CPC__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_RDREQ_CPC__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_RDREQ_CPF__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_RDREQ_CPF__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_RDREQ_CPF__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_RDREQ_CPG__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_RDREQ_CPG__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_RDREQ_CPG__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_RDREQ_CP__BLACKOUT_EXEMPT_MASK__SI 0x00000008L -#define MC_HUB_RDREQ_CP__ENABLE_MASK__SI 0x00000001L -#define MC_HUB_RDREQ_CP__LAZY_TIMER_MASK__SI 0x00007800L -#define MC_HUB_RDREQ_CP__MAXBURST_MASK__SI 0x00000780L -#define MC_HUB_RDREQ_CP__PRESCALE_MASK__SI 0x00000006L -#define MC_HUB_RDREQ_CP__STALL_MODE_MASK__SI 0x00000030L -#define MC_HUB_RDREQ_CP__STALL_OVERRIDE_MASK__SI 0x00000040L -#define MC_HUB_RDREQ_CP__STALL_OVERRIDE_WTM_MASK__SI 0x00008000L -#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0x00ff0000L -#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000L -#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0x000000ffL -#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0x0000ff00L -#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x00000003L -#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x0000007cL -#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_DRMDMA0__BLACKOUT_EXEMPT_MASK__SI 0x00000008L -#define MC_HUB_RDREQ_DRMDMA0__ENABLE_MASK__SI 0x00000001L -#define MC_HUB_RDREQ_DRMDMA0__LAZY_TIMER_MASK__SI 0x00007800L -#define MC_HUB_RDREQ_DRMDMA0__MAXBURST_MASK__SI 0x00000780L -#define MC_HUB_RDREQ_DRMDMA0__PRESCALE_MASK__SI 0x00000006L -#define MC_HUB_RDREQ_DRMDMA0__STALL_MODE_MASK__SI 0x00000030L -#define MC_HUB_RDREQ_DRMDMA0__STALL_OVERRIDE_MASK__SI 0x00000040L -#define MC_HUB_RDREQ_DRMDMA0__STALL_OVERRIDE_WTM_MASK__SI 0x00008000L -#define MC_HUB_RDREQ_DRMDMA1__BLACKOUT_EXEMPT_MASK__SI 0x00000008L -#define MC_HUB_RDREQ_DRMDMA1__ENABLE_MASK__SI 0x00000001L -#define MC_HUB_RDREQ_DRMDMA1__LAZY_TIMER_MASK__SI 0x00007800L -#define MC_HUB_RDREQ_DRMDMA1__MAXBURST_MASK__SI 0x00000780L -#define MC_HUB_RDREQ_DRMDMA1__PRESCALE_MASK__SI 0x00000006L -#define MC_HUB_RDREQ_DRMDMA1__STALL_MODE_MASK__SI 0x00000030L -#define MC_HUB_RDREQ_DRMDMA1__STALL_OVERRIDE_MASK__SI 0x00000040L -#define MC_HUB_RDREQ_DRMDMA1__STALL_OVERRIDE_WTM_MASK__SI 0x00008000L -#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0x000000ffL -#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0x000000ffL -#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_RDREQ_IA0__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_RDREQ_IA0__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_RDREQ_IA0__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_RDREQ_IA1__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_RDREQ_IA1__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_RDREQ_IA1__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_RDREQ_IA__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_RDREQ_IA__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_RDREQ_IA__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_RDREQ_IA__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x0003f800L -#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x00000004L -#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x01fc0000L -#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x00000780L -#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x00000078L -#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK__SI__CI 0xfe000000L -#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x0003f800L -#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x00000004L -#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x01fc0000L -#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x00000780L -#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x00000078L -#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK__SI__CI 0xfe000000L -#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x0003f800L -#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x00000004L -#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x01fc0000L -#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x00000780L -#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x00000078L -#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK__SI__CI 0xfe000000L -#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x0003f800L -#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x00000004L -#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x01fc0000L -#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x00000780L -#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x00000078L -#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK__SI__CI 0xfe000000L -#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_RDREQ_SAM__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_RDREQ_SAM__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_RDREQ_SAM__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x0000007fL -#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x00007f00L -#define MC_HUB_RDREQ_SIP__DUMMY_MASK__SI__CI 0x00000080L -#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L -#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L -#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L -#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L -#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x00000001L -#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x00010000L -#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK__SI__CI 0x00000008L -#define MC_HUB_RDREQ_VCEU__ENABLE_MASK__SI__CI 0x00000001L -#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK__SI__CI 0x00007800L -#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK__SI__CI 0x00000780L -#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK__SI__CI 0x00000006L -#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK__SI__CI 0x00000030L -#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK__SI__CI 0x00000040L -#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK__SI__CI 0x00008000L -#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK__SI__CI 0x00000008L -#define MC_HUB_RDREQ_VCE__ENABLE_MASK__SI__CI 0x00000001L -#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK__SI__CI 0x00007800L -#define MC_HUB_RDREQ_VCE__MAXBURST_MASK__SI__CI 0x00000780L -#define MC_HUB_RDREQ_VCE__PRESCALE_MASK__SI__CI 0x00000006L -#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK__SI__CI 0x00000030L -#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK__SI__CI 0x00000040L -#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK__SI__CI 0x00008000L -#define MC_HUB_RDREQ_VGT__BLACKOUT_EXEMPT_MASK__SI 0x00000008L -#define MC_HUB_RDREQ_VGT__ENABLE_MASK__SI 0x00000001L -#define MC_HUB_RDREQ_VGT__LAZY_TIMER_MASK__SI 0x00007800L -#define MC_HUB_RDREQ_VGT__MAXBURST_MASK__SI 0x00000780L -#define MC_HUB_RDREQ_VGT__PRESCALE_MASK__SI 0x00000006L -#define MC_HUB_RDREQ_VGT__STALL_MODE_MASK__SI 0x00000030L -#define MC_HUB_RDREQ_VGT__STALL_OVERRIDE_MASK__SI 0x00000040L -#define MC_HUB_RDREQ_VGT__STALL_OVERRIDE_WTM_MASK__SI 0x00008000L -#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L -#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L -#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x00000001L -#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x00000780L -#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x00000006L -#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x00000030L -#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x0000003fL -#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000L -#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK__CI__VI 0x00010000L -#define MC_HUB_WDP_ACPG__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_WDP_ACPG__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_WDP_ACPG__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK__CI__VI 0x00020000L -#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK__CI__VI 0x00040000L -#define MC_HUB_WDP_ACPG__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK__CI__VI 0x01f80000L -#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK__CI__VI 0x00010000L -#define MC_HUB_WDP_ACPO__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_WDP_ACPO__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_WDP_ACPO__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK__CI__VI 0x00020000L -#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK__CI__VI 0x00040000L -#define MC_HUB_WDP_ACPO__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK__CI__VI 0x01f80000L -#define MC_HUB_WDP_BP__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_BP__RDRET_MASK 0x0003fffeL -#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000L -#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x00001fe0L -#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00002000L -#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00004000L -#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x00008000L -#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x00040000L -#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x00010000L -#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x00000002L -#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x00000004L -#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x00000008L -#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x00020000L -#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x00080000L -#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L -#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x00100000L -#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_WDP_CPC__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_WDP_CPC__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_WDP_CPC__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_WDP_CPC__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_WDP_CPF__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_WDP_CPF__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_WDP_CPF__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_WDP_CPF__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_WDP_CPG__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_WDP_CPG__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_WDP_CPG__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_WDP_CPG__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_WDP_CP__BLACKOUT_EXEMPT_MASK__SI 0x00000008L -#define MC_HUB_WDP_CP__ENABLE_MASK__SI 0x00000001L -#define MC_HUB_WDP_CP__LAZY_TIMER_MASK__SI 0x00007800L -#define MC_HUB_WDP_CP__MAXBURST_MASK__SI 0x00000780L -#define MC_HUB_WDP_CP__PRESCALE_MASK__SI 0x00000006L -#define MC_HUB_WDP_CP__STALL_MODE_MASK__SI 0x00000030L -#define MC_HUB_WDP_CP__STALL_OVERRIDE_MASK__SI 0x00000040L -#define MC_HUB_WDP_CP__STALL_OVERRIDE_WTM_MASK__SI 0x00008000L -#define MC_HUB_WDP_CREDITS__STOR0_MASK 0x00ff0000L -#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000L -#define MC_HUB_WDP_CREDITS__VM0_MASK 0x000000ffL -#define MC_HUB_WDP_CREDITS__VM1_MASK 0x0000ff00L -#define MC_HUB_WDP_DRMDMA0__BLACKOUT_EXEMPT_MASK__SI 0x00000008L -#define MC_HUB_WDP_DRMDMA0__ENABLE_MASK__SI 0x00000001L -#define MC_HUB_WDP_DRMDMA0__LAZY_TIMER_MASK__SI 0x00007800L -#define MC_HUB_WDP_DRMDMA0__MAXBURST_MASK__SI 0x00000780L -#define MC_HUB_WDP_DRMDMA0__PRESCALE_MASK__SI 0x00000006L -#define MC_HUB_WDP_DRMDMA0__STALL_MODE_MASK__SI 0x00000030L -#define MC_HUB_WDP_DRMDMA0__STALL_OVERRIDE_MASK__SI 0x00000040L -#define MC_HUB_WDP_DRMDMA0__STALL_OVERRIDE_WTM_MASK__SI 0x00008000L -#define MC_HUB_WDP_DRMDMA1__BLACKOUT_EXEMPT_MASK__SI 0x00000008L -#define MC_HUB_WDP_DRMDMA1__ENABLE_MASK__SI 0x00000001L -#define MC_HUB_WDP_DRMDMA1__LAZY_TIMER_MASK__SI 0x00007800L -#define MC_HUB_WDP_DRMDMA1__MAXBURST_MASK__SI 0x00000780L -#define MC_HUB_WDP_DRMDMA1__PRESCALE_MASK__SI 0x00000006L -#define MC_HUB_WDP_DRMDMA1__STALL_MODE_MASK__SI 0x00000030L -#define MC_HUB_WDP_DRMDMA1__STALL_OVERRIDE_MASK__SI 0x00000040L -#define MC_HUB_WDP_DRMDMA1__STALL_OVERRIDE_WTM_MASK__SI 0x00008000L -#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x00000001L -#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x00000002L -#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0x000000f0L -#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0x0000000fL -#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x00010000L -#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0x0000ff00L -#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0x000000f0L -#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0x0000000fL -#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x00010000L -#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0x0000ff00L -#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_HDP__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_IH__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_IH__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_IH__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x00001f80L -#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000L -#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x0001e000L -#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x00000078L -#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x00000004L -#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0x00fe0000L -#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x00001f80L -#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000L -#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x0001e000L -#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x00000078L -#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x00000004L -#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0x00fe0000L -#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x00001f80L -#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000L -#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x0001e000L -#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x00000078L -#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x00000004L -#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0x00fe0000L -#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x00001f80L -#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000L -#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L -#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x0001e000L -#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x00000078L -#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x00000004L -#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0x00fe0000L -#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_MGPU2__CID2_MASK__SI__CI 0x000000ffL -#define MC_HUB_WDP_MGPU__CID_MASK__SI__CI 0x0000ff00L -#define MC_HUB_WDP_MGPU__ENABLE_MASK__SI__CI 0x00800000L -#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK__SI__CI 0x007f0000L -#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK__SI__CI 0x7f000000L -#define MC_HUB_WDP_MGPU__STOR_MASK__SI__CI 0x000000ffL -#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_RLC__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK__CI 0x00000008L -#define MC_HUB_WDP_SAM__ENABLE_MASK__CI 0x00000001L -#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK__CI 0x00007800L -#define MC_HUB_WDP_SAM__MAXBURST_MASK__CI 0x00000780L -#define MC_HUB_WDP_SAM__PRESCALE_MASK__CI 0x00000006L -#define MC_HUB_WDP_SAM__STALL_MODE_MASK__CI 0x00000030L -#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK__CI 0x00000040L -#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK__CI 0x00008000L -#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_WDP_SDMA0__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_WDP_SDMA0__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_WDP_SDMA0__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_WDP_SDMA1__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_WDP_SDMA1__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_WDP_SDMA1__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_SEM__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_SH0__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_SH1__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_WDP_SH2__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_WDP_SH2__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_WDP_SH2__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_WDP_SH2__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK__CI__VI 0x00000008L -#define MC_HUB_WDP_SH3__ENABLE_MASK__CI__VI 0x00000001L -#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK__CI__VI 0x00007800L -#define MC_HUB_WDP_SH3__MAXBURST_MASK__CI__VI 0x00000780L -#define MC_HUB_WDP_SH3__PRESCALE_MASK__CI__VI 0x00000006L -#define MC_HUB_WDP_SH3__STALL_MODE_MASK__CI__VI 0x00000030L -#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK__CI__VI 0x00000040L -#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK__CI__VI 0x00008000L -#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x000001fcL -#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x00000003L -#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_SMU__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L -#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK__SI 0x00000800L -#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L -#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK__SI 0x00001000L -#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L -#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK__SI 0x00002000L -#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L -#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK__SI 0x00004000L -#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x00000001L -#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_UMC__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_UVD__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x00010000L -#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK__SI__CI 0x00000008L -#define MC_HUB_WDP_VCEU__ENABLE_MASK__SI__CI 0x00000001L -#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK__SI__CI 0x00007800L -#define MC_HUB_WDP_VCEU__MAXBURST_MASK__SI__CI 0x00000780L -#define MC_HUB_WDP_VCEU__PRESCALE_MASK__SI__CI 0x00000006L -#define MC_HUB_WDP_VCEU__STALL_MODE_MASK__SI__CI 0x00000030L -#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK__SI__CI 0x00000040L -#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK__SI__CI 0x00008000L -#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK__SI__CI 0x00000008L -#define MC_HUB_WDP_VCE__ENABLE_MASK__SI__CI 0x00000001L -#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK__SI__CI 0x00007800L -#define MC_HUB_WDP_VCE__MAXBURST_MASK__SI__CI 0x00000780L -#define MC_HUB_WDP_VCE__PRESCALE_MASK__SI__CI 0x00000006L -#define MC_HUB_WDP_VCE__STALL_MODE_MASK__SI__CI 0x00000030L -#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK__SI__CI 0x00000040L -#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK__SI__CI 0x00008000L -#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L -#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L -#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L -#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L -#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L -#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L -#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L -#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L -#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L -#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L -#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_HUB_WDP_XDP__ENABLE_MASK 0x00000001L -#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x00007800L -#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x00000780L -#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x00000006L -#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x00000030L -#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x00000040L -#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x00200000L -#define MC_HUB_WRRET_CNTL__BP_MASK 0x001ffffeL -#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000L -#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000L -#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000L -#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x00000001L -#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0x000000feL -#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x00000001L -#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0x000000feL -#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x00000001L -#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0x000000feL -#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x00000001L -#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0x000000feL -#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x00000001L -#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x00000001L -#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x00000002L -#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x00000004L -#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x00000008L -#define MC_IMP_CNTL__CAL_PWRON_MASK__SI__CI 0x80000000L -#define MC_IMP_CNTL__CAL_VREFMODE_MASK__SI__CI 0x00000040L -#define MC_IMP_CNTL__CAL_VREF_MASK__SI__CI 0x007f0000L -#define MC_IMP_CNTL__CAL_VREF_SEL_MASK__SI__CI 0x00000020L -#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK__SI__CI 0x20000000L -#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK__SI__CI 0x40000000L -#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK__SI__CI 0x00000200L -#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK__SI__CI 0x0000e000L -#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK__SI__CI 0x0000001fL -#define MC_IMP_CNTL__TIMEOUT_ERR_MASK__SI__CI 0x00000100L -#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK__SI__CI 0x80000000L -#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK__SI__CI 0x10000000L -#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK__SI__CI 0x40000000L -#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK__SI__CI 0x20000000L -#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK__CI 0x00ff0000L -#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK__SI 0x0fff0000L -#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK__SI__CI 0x0000ff00L -#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK__SI__CI 0x000000ffL -#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK__SI__CI 0x0000ff00L -#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK__SI__CI 0x000000ffL -#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK__SI__CI 0xff000000L -#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK__SI__CI 0x00ff0000L -#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK__SI__CI 0xff000000L -#define MC_IMP_STATUS__NSTR_CAL_MASK__SI__CI 0x00ff0000L -#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK__SI__CI 0x0000ff00L -#define MC_IMP_STATUS__PSTR_CAL_MASK__SI__CI 0x000000ffL -#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK__SI__CI 0x0c000000L -#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK__SI__CI 0x10000000L -#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK__SI__CI 0x20000000L -#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK__SI__CI 0x00000fc0L -#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK__SI__CI 0x0000003fL -#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK__SI__CI 0x0003f000L -#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK__SI__CI 0x01000000L -#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK__SI__CI 0x02000000L -#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK__SI__CI 0x0c000000L -#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK__SI__CI 0x10000000L -#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK__SI__CI 0x20000000L -#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK__SI__CI 0x00000fc0L -#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK__SI__CI 0x0000003fL -#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK__SI__CI 0x0003f000L -#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK__SI__CI 0x01000000L -#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK__SI__CI 0x02000000L -#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK__SI__CI 0x000000ffL -#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK__SI__CI 0x0000ff00L -#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK__SI__CI 0x00ff0000L -#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK__SI__CI 0xff000000L -#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK__SI__CI 0x000000ffL -#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK__SI__CI 0x0000ff00L -#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK__SI__CI 0x00ff0000L -#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK__SI__CI 0xff000000L -#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK__SI__CI 0x00000001L -#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK__SI__CI 0x00000002L -#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK__SI__CI 0x00000004L -#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK__SI__CI 0x00000008L -#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK__SI__CI 0x00000010L -#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK__SI__CI 0x00000020L -#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK__CI 0x000f0000L -#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK__CI 0x00000f00L -#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK__CI 0x0000f000L -#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK__SI__CI 0x00000040L -#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK__SI__CI 0x00000080L -#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK__SI__CI 0x00000001L -#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK__SI__CI 0x00000002L -#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK__SI__CI 0x00000004L -#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK__SI__CI 0x00000008L -#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK__SI__CI 0x00000010L -#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK__SI__CI 0x00000020L -#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK__CI 0x000f0000L -#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK__CI 0x00000f00L -#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK__CI 0x0000f000L -#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK__SI__CI 0x00000040L -#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK__SI__CI 0x00000080L -#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK__SI__CI 0x00400000L -#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK__SI__CI 0x00800000L -#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK__SI__CI 0x10000000L -#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK__SI__CI 0x20000000L -#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK__SI__CI 0x00100000L -#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK__SI__CI 0x00200000L -#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK__SI__CI 0x40000000L -#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK__SI__CI 0x80000000L -#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK__SI__CI 0x00000400L -#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK__SI__CI 0x00000800L -#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK__SI__CI 0x00000100L -#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK__SI__CI 0x00000200L -#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK__SI__CI 0x0000f000L -#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK__SI__CI 0x000f0000L -#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK__SI__CI 0x0000000fL -#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK__SI__CI 0x000000f0L -#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK__SI__CI 0x04000000L -#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK__SI__CI 0x08000000L -#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK__SI__CI 0x01000000L -#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK__SI__CI 0x02000000L -#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK__SI__CI 0x00400000L -#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK__SI__CI 0x00800000L -#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK__SI__CI 0x10000000L -#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK__SI__CI 0x20000000L -#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK__SI__CI 0x00100000L -#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK__SI__CI 0x00200000L -#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK__SI__CI 0x40000000L -#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK__SI__CI 0x80000000L -#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK__SI__CI 0x00000400L -#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK__SI__CI 0x00000800L -#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK__SI__CI 0x00000100L -#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK__SI__CI 0x00000200L -#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK__SI__CI 0x0000f000L -#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK__SI__CI 0x000f0000L -#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK__SI__CI 0x0000000fL -#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK__SI__CI 0x000000f0L -#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK__SI__CI 0x04000000L -#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK__SI__CI 0x08000000L -#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK__SI__CI 0x01000000L -#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK__SI__CI 0x02000000L -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_100__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_100__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_100__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_100__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_101__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_101__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_101__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_101__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_102__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_102__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_102__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_102__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_103__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_103__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_103__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_103__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_104__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_104__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_104__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_104__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_105__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_105__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_105__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_105__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_106__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_106__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_106__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_106__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_107__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_107__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_107__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_107__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_108__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_108__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_108__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_108__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_109__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_109__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_109__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_109__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_10__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_10__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_10__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_10__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_110__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_110__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_110__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_110__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_111__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_111__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_111__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_111__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_112__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_112__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_112__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_112__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_113__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_113__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_113__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_113__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_114__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_114__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_114__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_114__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_115__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_115__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_115__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_115__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_116__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_116__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_116__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_116__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_117__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_117__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_117__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_117__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_118__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_118__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_118__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_118__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_119__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_119__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_119__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_119__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_11__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_11__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_11__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_11__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_120__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_120__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_120__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_120__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_121__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_121__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_121__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_121__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_122__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_122__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_122__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_122__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_123__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_123__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_123__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_123__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_124__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_124__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_124__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_124__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_125__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_125__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_125__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_125__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_126__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_126__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_126__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_126__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_127__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_127__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_127__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_127__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_128__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_128__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_128__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_128__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_129__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_129__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_129__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_129__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_12__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_12__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_12__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_12__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_130__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_130__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_130__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_130__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_131__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_131__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_131__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_131__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_132__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_132__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_132__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_132__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_133__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_133__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_133__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_133__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_134__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_134__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_134__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_134__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_135__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_135__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_135__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_135__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_136__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_136__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_136__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_136__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_137__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_137__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_137__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_137__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_138__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_138__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_138__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_138__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_139__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_139__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_139__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_139__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_13__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_13__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_13__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_13__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_140__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_140__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_140__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_140__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_141__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_141__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_141__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_141__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_142__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_142__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_142__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_142__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_143__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_143__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_143__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_143__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_144__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_144__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_144__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_144__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_145__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_145__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_145__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_145__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_146__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_146__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_146__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_146__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_147__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_147__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_147__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_147__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_148__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_148__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_148__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_148__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_149__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_149__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_149__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_149__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_14__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_14__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_14__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_14__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_150__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_150__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_150__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_150__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_151__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_151__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_151__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_151__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_152__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_152__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_152__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_152__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_153__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_153__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_153__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_153__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_154__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_154__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_154__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_154__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_155__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_155__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_155__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_155__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_156__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_156__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_156__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_156__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_157__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_157__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_157__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_157__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_158__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_158__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_158__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_158__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_159__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_159__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_159__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_159__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_15__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_15__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_15__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_15__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_16__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_16__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_16__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_16__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_17__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_17__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_17__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_17__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_18__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_18__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_18__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_18__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_19__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_19__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_19__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_19__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_20__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_20__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_20__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_20__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_21__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_21__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_21__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_21__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_22__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_22__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_22__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_22__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_23__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_23__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_23__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_23__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_24__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_24__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_24__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_24__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_25__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_25__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_25__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_25__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_26__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_26__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_26__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_26__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_27__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_27__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_27__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_27__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_28__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_28__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_28__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_28__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_29__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_29__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_29__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_29__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_2__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_2__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_2__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_2__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_30__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_30__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_30__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_30__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_31__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_31__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_31__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_31__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_32__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_32__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_32__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_32__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_33__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_33__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_33__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_33__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_34__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_34__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_34__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_34__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_35__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_35__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_35__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_35__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_36__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_36__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_36__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_36__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_37__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_37__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_37__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_37__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_38__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_38__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_38__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_38__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_39__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_39__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_39__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_39__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_3__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_3__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_3__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_3__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_40__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_40__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_40__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_40__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_41__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_41__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_41__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_41__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_42__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_42__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_42__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_42__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_43__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_43__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_43__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_43__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_44__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_44__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_44__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_44__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_45__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_45__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_45__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_45__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_46__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_46__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_46__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_46__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_47__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_47__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_47__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_47__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_48__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_48__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_48__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_48__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_49__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_49__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_49__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_49__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_4__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_4__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_4__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_4__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_50__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_50__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_50__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_50__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_51__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_51__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_51__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_51__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_52__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_52__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_52__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_52__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_53__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_53__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_53__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_53__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_54__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_54__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_54__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_54__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_55__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_55__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_55__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_55__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_56__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_56__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_56__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_56__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_57__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_57__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_57__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_57__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_58__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_58__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_58__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_58__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_59__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_59__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_59__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_59__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_5__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_5__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_5__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_5__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_60__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_60__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_60__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_60__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_61__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_61__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_61__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_61__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_62__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_62__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_62__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_62__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_63__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_63__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_63__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_63__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_64__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_64__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_64__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_64__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_65__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_65__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_65__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_65__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_66__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_66__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_66__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_66__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_67__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_67__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_67__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_67__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_68__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_68__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_68__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_68__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_69__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_69__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_69__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_69__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_6__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_6__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_6__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_6__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_70__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_70__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_70__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_70__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_71__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_71__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_71__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_71__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_72__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_72__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_72__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_72__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_73__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_73__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_73__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_73__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_74__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_74__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_74__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_74__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_75__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_75__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_75__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_75__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_76__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_76__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_76__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_76__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_77__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_77__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_77__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_77__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_78__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_78__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_78__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_78__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_79__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_79__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_79__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_79__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_7__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_7__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_7__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_7__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_80__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_80__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_80__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_80__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_81__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_81__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_81__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_81__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_82__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_82__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_82__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_82__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_83__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_83__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_83__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_83__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_84__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_84__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_84__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_84__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_85__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_85__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_85__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_85__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_86__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_86__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_86__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_86__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_87__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_87__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_87__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_87__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_88__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_88__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_88__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_88__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_89__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_89__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_89__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_89__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_8__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_8__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_8__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_8__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_90__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_90__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_90__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_90__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_91__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_91__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_91__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_91__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_92__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_92__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_92__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_92__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_93__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_93__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_93__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_93__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_94__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_94__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_94__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_94__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_95__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_95__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_95__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_95__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_96__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_96__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_96__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_96__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_97__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_97__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_97__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_97__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_98__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_98__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_98__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_98__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_99__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_99__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_99__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_99__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_UP_9__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_UP_9__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_UP_9__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_UP_9__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK__SI__CI 0x000000ffL -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK__SI__CI 0x0000ff00L -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK__SI__CI 0x00ff0000L -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK__SI__CI 0xff000000L -#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK__CI 0x40000000L -#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK__SI__CI 0x0c000000L -#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK__SI__CI 0x10000000L -#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK__SI__CI 0x20000000L -#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK__SI__CI 0x00000fc0L -#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK__SI__CI 0x00fc0000L -#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK__SI__CI 0x0000003fL -#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK__SI__CI 0x0003f000L -#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK__SI__CI 0x01000000L -#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK__SI__CI 0x02000000L -#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK__CI 0x40000000L -#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK__SI__CI 0x0c000000L -#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK__SI__CI 0x10000000L -#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK__SI__CI 0x20000000L -#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK__SI__CI 0x00000fc0L -#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK__SI__CI 0x00fc0000L -#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK__SI__CI 0x0000003fL -#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK__SI__CI 0x0003f000L -#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK__SI__CI 0x01000000L -#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK__SI__CI 0x02000000L -#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK__SI__CI 0x00100000L -#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK__SI__CI 0x00c00000L -#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK__SI__CI 0x03000000L -#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK__SI__CI 0x00200000L -#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK__SI__CI 0x00000010L -#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK__SI__CI 0x00000004L -#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK__SI__CI 0x00000008L -#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK__SI__CI 0x20000000L -#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK__SI__CI 0x00002000L -#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK__SI__CI 0x00001000L -#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK__SI__CI 0x00000800L -#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK__SI__CI 0x00000400L -#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK__SI__CI 0x40000000L -#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK__SI__CI 0x00000200L -#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK__SI__CI 0x00000080L -#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK__SI__CI 0x00000100L -#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK__SI__CI 0x08000000L -#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK__SI__CI 0x80000000L -#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK__SI__CI 0x10000000L -#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK__SI__CI 0x00004000L -#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK__SI__CI 0x000f8000L -#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK__SI__CI 0x00100000L -#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK__SI__CI 0x00c00000L -#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK__SI__CI 0x03000000L -#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK__SI__CI 0x00200000L -#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK__SI__CI 0x00000010L -#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK__SI__CI 0x00000004L -#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK__SI__CI 0x00000008L -#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK__SI__CI 0x00000001L -#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK__SI__CI 0x00000002L -#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK__SI__CI 0x20000000L -#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK__SI__CI 0x00002000L -#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK__SI__CI 0x00001000L -#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK__SI__CI 0x00000800L -#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK__SI__CI 0x00000400L -#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK__SI__CI 0x40000000L -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK__SI__CI 0x00000200L -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK__SI__CI 0x00000080L -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK__SI__CI 0x00000100L -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK__SI__CI 0x00000020L -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK__SI__CI 0x00000040L -#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK__SI__CI 0x08000000L -#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK__SI__CI 0x80000000L -#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK__SI__CI 0x10000000L -#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK__SI__CI 0x00004000L -#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK__SI__CI 0x000f8000L -#define MC_IO_PAD_CNTL__ATBEN_MASK__SI__CI 0x3f000000L -#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK__SI__CI 0x80000000L -#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK__SI__CI 0x40000000L -#define MC_IO_PAD_CNTL__ATBSEL_MASK__SI__CI 0x00f00000L -#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK__SI__CI 0x0000ff00L -#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK__SI__CI 0x000000ffL -#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK__SI__CI 0x00040000L -#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK__SI__CI 0x00080000L -#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK__SI__CI 0x00020000L -#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK__CI 0x00200000L -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK__CI 0x00080000L -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK__SI__CI 0xf0000000L -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK__CI 0x00100000L -#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK__SI__CI 0x0e000000L -#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK__CI 0x00400000L -#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK__CI 0x00800000L -#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK__SI__CI 0x0000000fL -#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK__SI__CI 0x000000f0L -#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK__SI__CI 0x0000ff00L -#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK__SI__CI 0x00040000L -#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK__SI__CI 0x00020000L -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTRACK01_0_MASK__SI 0x00800000L -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTRACK01_1_MASK__SI 0x01000000L -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXPWRON_B0_MASK__SI 0x00080000L -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXPWRON_B1_MASK__SI 0x00100000L -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXSEL_B0_MASK__SI 0x00200000L -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXSEL_B1_MASK__SI 0x00400000L -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK__CI 0x00200000L -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK__CI 0x00080000L -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK__SI__CI 0xf0000000L -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK__CI 0x00100000L -#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK__SI__CI 0x0e000000L -#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK__CI 0x00400000L -#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK__CI 0x00800000L -#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK__SI__CI 0x0000000fL -#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK__SI__CI 0x000000f0L -#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK__SI__CI 0x0000ff00L -#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK__SI__CI 0x00040000L -#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK__SI__CI 0x00020000L -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTRACK01_0_MASK__SI 0x00800000L -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTRACK01_1_MASK__SI 0x01000000L -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXPWRON_B0_MASK__SI 0x00080000L -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXPWRON_B1_MASK__SI 0x00100000L -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXSEL_B0_MASK__SI 0x00200000L -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXSEL_B1_MASK__SI 0x00400000L -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK__CI 0x00200000L -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK__CI 0x00080000L -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK__SI__CI 0xf0000000L -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK__CI 0x00100000L -#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK__SI__CI 0x0e000000L -#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK__CI 0x00400000L -#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK__CI 0x00800000L -#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK__SI__CI 0x0000000fL -#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK__SI__CI 0x000000f0L -#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK__SI__CI 0x0000ff00L -#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK__SI__CI 0x00040000L -#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK__SI__CI 0x00020000L -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTRACK01_0_MASK__SI 0x00800000L -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTRACK01_1_MASK__SI 0x01000000L -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXPWRON_B0_MASK__SI 0x00080000L -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXPWRON_B1_MASK__SI 0x00100000L -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXSEL_B0_MASK__SI 0x00200000L -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXSEL_B1_MASK__SI 0x00400000L -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK__CI 0x00200000L -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK__CI 0x00080000L -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK__SI__CI 0xf0000000L -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK__CI 0x00100000L -#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK__SI__CI 0x0e000000L -#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK__CI 0x00400000L -#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK__CI 0x00800000L -#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK__SI__CI 0x0000000fL -#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK__SI__CI 0x000000f0L -#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK__SI__CI 0x0000ff00L -#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK__SI__CI 0x00040000L -#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK__SI__CI 0x00020000L -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTRACK01_0_MASK__SI 0x00800000L -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTRACK01_1_MASK__SI 0x01000000L -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXPWRON_B0_MASK__SI 0x00080000L -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXPWRON_B1_MASK__SI 0x00100000L -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXSEL_B0_MASK__SI 0x00200000L -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXSEL_B1_MASK__SI 0x00400000L -#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK__SI__CI 0x00700000L -#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK__SI__CI 0x07000000L -#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK__SI__CI 0x10000000L -#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK__SI__CI 0xc0000000L -#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK__SI__CI 0x00000004L -#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK__SI__CI 0x20000000L -#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK__SI__CI 0x00000030L -#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK__SI__CI 0x00000080L -#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK__SI__CI 0x00000040L -#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK__SI__CI 0x000c0000L -#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK__SI__CI 0x00000f00L -#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK__SI__CI 0x0000f000L -#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK__SI__CI 0x00000008L -#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK__SI__CI 0x00700000L -#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK__SI__CI 0x07000000L -#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK__SI__CI 0x10000000L -#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK__SI__CI 0xc0000000L -#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK__SI__CI 0x00000004L -#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK__SI__CI 0x20000000L -#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK__SI__CI 0x00000030L -#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK__SI__CI 0x00000080L -#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK__SI__CI 0x00000040L -#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK__SI__CI 0x000c0000L -#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK__SI__CI 0x00000f00L -#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK__SI__CI 0x0000f000L -#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK__SI__CI 0x00000008L -#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK__SI__CI 0x00700000L -#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK__SI__CI 0x07000000L -#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK__SI__CI 0x10000000L -#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK__SI__CI 0xc0000000L -#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK__SI__CI 0x00000004L -#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK__SI__CI 0x20000000L -#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK__SI__CI 0x00000030L -#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK__SI__CI 0x00000080L -#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK__SI__CI 0x00000040L -#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK__SI__CI 0x000c0000L -#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK__SI__CI 0x00000f00L -#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK__SI__CI 0x0000f000L -#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK__SI__CI 0x00000008L -#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK__SI__CI 0x00010000L -#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK__SI__CI 0x00700000L -#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK__SI__CI 0x07000000L -#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK__SI__CI 0x10000000L -#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK__SI__CI 0xc0000000L -#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK__SI__CI 0x00000004L -#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK__SI__CI 0x20000000L -#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK__SI__CI 0x00000030L -#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK__SI__CI 0x00000080L -#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK__SI__CI 0x00000040L -#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK__SI__CI 0x000c0000L -#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK__SI__CI 0x00000f00L -#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK__SI__CI 0x0000f000L -#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK__SI__CI 0x00000008L -#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK__SI__CI 0x00010000L -#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK__SI__CI 0x40000000L -#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK__SI__CI 0x80000000L -#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK__SI__CI 0x0000000cL -#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK__SI__CI 0x00000040L -#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK__SI__CI 0x00000010L -#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK__SI__CI 0x00700000L -#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK__SI__CI 0x000f0000L -#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK__SI__CI 0x0000e000L -#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK__SI__CI 0x00000f00L -#define MC_IO_TXCNTL_APHY_D0__QDR_MASK__SI__CI 0x00000020L -#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK__SI__CI 0x01000000L -#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK__SI__CI 0x00001000L -#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK__SI__CI 0x38000000L -#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK__SI__CI 0x04000000L -#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK__SI__CI 0x00000080L -#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK__SI__CI 0x02000000L -#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK__SI__CI 0x00800000L -#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK__SI__CI 0x40000000L -#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK__SI__CI 0x80000000L -#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK__SI__CI 0x0000000cL -#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK__SI__CI 0x00000040L -#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK__SI__CI 0x00000010L -#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK__SI__CI 0x00700000L -#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK__SI__CI 0x000f0000L -#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK__SI__CI 0x0000e000L -#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK__SI__CI 0x00000f00L -#define MC_IO_TXCNTL_APHY_D1__QDR_MASK__SI__CI 0x00000020L -#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK__SI__CI 0x01000000L -#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK__SI__CI 0x00001000L -#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK__SI__CI 0x38000000L -#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK__SI__CI 0x04000000L -#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK__SI__CI 0x00000080L -#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK__SI__CI 0x02000000L -#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK__SI__CI 0x00800000L -#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK__SI__CI 0x0000000cL -#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK__SI__CI 0x02000000L -#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK__SI__CI 0x00000040L -#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK__SI__CI 0x00000010L -#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK__SI__CI 0x00f00000L -#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK__SI__CI 0x0000f000L -#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK__SI__CI 0x000f0000L -#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK__SI__CI 0x08000000L -#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK__SI__CI 0x00000f00L -#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK__SI__CI 0x00000020L -#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK__SI__CI 0x01000000L -#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK__SI__CI 0xf0000000L -#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK__SI__CI 0x04000000L -#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK__SI__CI 0x00000080L -#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK__SI__CI 0x0000000cL -#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK__SI__CI 0x02000000L -#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK__SI__CI 0x00000040L -#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK__SI__CI 0x00000010L -#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK__SI__CI 0x00f00000L -#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK__SI__CI 0x0000f000L -#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK__SI__CI 0x000f0000L -#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK__SI__CI 0x08000000L -#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK__SI__CI 0x00000f00L -#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK__SI__CI 0x00000020L -#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK__SI__CI 0x01000000L -#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK__SI__CI 0xf0000000L -#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK__SI__CI 0x04000000L -#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK__SI__CI 0x00000080L -#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK__SI__CI 0x0000000cL -#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK__SI__CI 0x02000000L -#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK__SI__CI 0x00000040L -#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK__SI__CI 0x00000010L -#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK__SI__CI 0x00f00000L -#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK__SI__CI 0x0000f000L -#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK__SI__CI 0x000f0000L -#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK__SI__CI 0x08000000L -#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK__SI__CI 0x00000f00L -#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK__SI__CI 0x00000020L -#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK__SI__CI 0x01000000L -#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK__SI__CI 0xf0000000L -#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK__SI__CI 0x04000000L -#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK__SI__CI 0x00000080L -#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK__SI__CI 0x00000003L -#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK__SI__CI 0x0000000cL -#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK__SI__CI 0x02000000L -#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK__SI__CI 0x00000040L -#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK__SI__CI 0x00000010L -#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK__SI__CI 0x00f00000L -#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK__SI__CI 0x0000f000L -#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK__SI__CI 0x000f0000L -#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK__SI__CI 0x08000000L -#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK__SI__CI 0x00000f00L -#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK__SI__CI 0x00000020L -#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK__SI__CI 0x01000000L -#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK__SI__CI 0xf0000000L -#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK__SI__CI 0x04000000L -#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK__SI__CI 0x00000080L -#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L -#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL -#define MC_NPL_STATUS__D0_NDELAY_MASK__SI__CI 0x0000000cL -#define MC_NPL_STATUS__D0_NEARLY_MASK__SI__CI 0x00000020L -#define MC_NPL_STATUS__D0_PDELAY_MASK__SI__CI 0x00000003L -#define MC_NPL_STATUS__D0_PEARLY_MASK__SI__CI 0x00000010L -#define MC_NPL_STATUS__D1_NDELAY_MASK__SI__CI 0x00000300L -#define MC_NPL_STATUS__D1_NEARLY_MASK__SI__CI 0x00000800L -#define MC_NPL_STATUS__D1_PDELAY_MASK__SI__CI 0x000000c0L -#define MC_NPL_STATUS__D1_PEARLY_MASK__SI__CI 0x00000400L -#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK__SI__CI 0x00040000L -#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK__SI__CI 0x00080000L -#define MC_PHY_TIMING_2__IND_LD_CNT_MASK__SI__CI 0x0000007fL -#define MC_PHY_TIMING_2__RXC0_FRC_MASK__SI__CI 0x00001000L -#define MC_PHY_TIMING_2__RXC0_INV_MASK__SI__CI 0x00000100L -#define MC_PHY_TIMING_2__RXC1_FRC_MASK__SI__CI 0x00002000L -#define MC_PHY_TIMING_2__RXC1_INV_MASK__SI__CI 0x00000200L -#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK__CI 0x01000000L -#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK__CI 0x02000000L -#define MC_PHY_TIMING_2__TXC0_FRC_MASK__SI__CI 0x00004000L -#define MC_PHY_TIMING_2__TXC0_INV_MASK__SI__CI 0x00000400L -#define MC_PHY_TIMING_2__TXC1_FRC_MASK__SI__CI 0x00008000L -#define MC_PHY_TIMING_2__TXC1_INV_MASK__SI__CI 0x00000800L -#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK__SI__CI 0x00010000L -#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK__SI__CI 0x00020000L -#define MC_PHY_TIMING_2__WR_DLY_MASK__SI__CI 0x00f00000L -#define MC_PHY_TIMING_D0__RXC0_DLY_MASK__SI__CI 0x0000000fL -#define MC_PHY_TIMING_D0__RXC0_EXT_MASK__SI__CI 0x000000f0L -#define MC_PHY_TIMING_D0__RXC1_DLY_MASK__SI__CI 0x00000f00L -#define MC_PHY_TIMING_D0__RXC1_EXT_MASK__SI__CI 0x0000f000L -#define MC_PHY_TIMING_D0__TXC0_DLY_MASK__SI__CI 0x00070000L -#define MC_PHY_TIMING_D0__TXC0_EXT_MASK__SI__CI 0x00f00000L -#define MC_PHY_TIMING_D0__TXC1_DLY_MASK__SI__CI 0x07000000L -#define MC_PHY_TIMING_D0__TXC1_EXT_MASK__SI__CI 0xf0000000L -#define MC_PHY_TIMING_D1__RXC0_DLY_MASK__SI__CI 0x0000000fL -#define MC_PHY_TIMING_D1__RXC0_EXT_MASK__SI__CI 0x000000f0L -#define MC_PHY_TIMING_D1__RXC1_DLY_MASK__SI__CI 0x00000f00L -#define MC_PHY_TIMING_D1__RXC1_EXT_MASK__SI__CI 0x0000f000L -#define MC_PHY_TIMING_D1__TXC0_DLY_MASK__SI__CI 0x00070000L -#define MC_PHY_TIMING_D1__TXC0_EXT_MASK__SI__CI 0x00f00000L -#define MC_PHY_TIMING_D1__TXC1_DLY_MASK__SI__CI 0x07000000L -#define MC_PHY_TIMING_D1__TXC1_EXT_MASK__SI__CI 0xf0000000L -#define MC_PMG_AUTO_CFG__DLL_CNT_MASK__SI__CI 0xff000000L -#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK__SI__CI 0x00000800L -#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK__SI__CI 0x000f0000L -#define MC_PMG_AUTO_CFG__PREA_SRX_MASK__SI__CI 0x00002000L -#define MC_PMG_AUTO_CFG__RFS_SRX_MASK__SI__CI 0x00001000L -#define MC_PMG_AUTO_CFG__RST_MRS_MASK__SI__CI 0x00000002L -#define MC_PMG_AUTO_CFG__RXPDNB_MASK__SI__CI 0x00400000L -#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK__SI__CI 0x00000400L -#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK__SI__CI 0x00008000L -#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK__SI__CI 0x00800000L -#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK__SI__CI 0x00000100L -#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK__SI__CI 0x00000200L -#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK__SI__CI 0x00004000L -#define MC_PMG_AUTO_CFG__SYC_CLK_MASK__SI__CI 0x00000001L -#define MC_PMG_AUTO_CFG__TRI_MIO_MASK__SI__CI 0x00000004L -#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK__SI__CI 0x00100000L -#define MC_PMG_AUTO_CFG__XSR_TMR_MASK__SI__CI 0x000000f0L -#define MC_PMG_AUTO_CFG__YCLK_ON_MASK__CI 0x00200000L -#define MC_PMG_AUTO_CMD__ADR_MASK__SI__CI 0x0001ffffL -#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_PMG_CFG__DPM_WAKE_MASK__SI__CI 0x00000400L -#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK__SI__CI 0x00400000L -#define MC_PMG_CFG__MRS_WAIT_CNT_MASK__SI__CI 0x000f0000L -#define MC_PMG_CFG__PREA_SRX_MASK__SI__CI 0x00002000L -#define MC_PMG_CFG__RFS_SRX_MASK__SI__CI 0x00001000L -#define MC_PMG_CFG__RST_EMRS_MASK__SI__CI 0x00000004L -#define MC_PMG_CFG__RST_MRS1_MASK__SI__CI 0x00000100L -#define MC_PMG_CFG__RST_MRS2_MASK__SI__CI 0x00000200L -#define MC_PMG_CFG__RST_MRS_MASK__SI__CI 0x00000002L -#define MC_PMG_CFG__RXPDNB_MASK__SI__CI 0x02000000L -#define MC_PMG_CFG__SYC_CLK_MASK__SI__CI 0x00000001L -#define MC_PMG_CFG__TRI_MIO_MASK__SI__CI 0x00000008L -#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK__SI__CI 0x00100000L -#define MC_PMG_CFG__XSR_TMR_MASK__SI__CI 0x000000f0L -#define MC_PMG_CFG__YCLK_ON_MASK__CI 0x00200000L -#define MC_PMG_CFG__ZQCL_SEND_MASK__SI__CI 0x0c000000L -#define MC_PMG_CMD_EMRS__ADR_MASK__SI__CI 0x0000ffffL -#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_PMG_CMD_EMRS__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_PMG_CMD_EMRS__CSB_MASK__SI__CI 0x00600000L -#define MC_PMG_CMD_EMRS__END_MASK__SI__CI 0x00100000L -#define MC_PMG_CMD_EMRS__MOP_MASK__SI__CI 0x00070000L -#define MC_PMG_CMD_MRS1__ADR_MASK__SI__CI 0x0000ffffL -#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_PMG_CMD_MRS1__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_PMG_CMD_MRS1__CSB_MASK__SI__CI 0x00600000L -#define MC_PMG_CMD_MRS1__END_MASK__SI__CI 0x00100000L -#define MC_PMG_CMD_MRS1__MOP_MASK__SI__CI 0x00070000L -#define MC_PMG_CMD_MRS2__ADR_MASK__SI__CI 0x0000ffffL -#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_PMG_CMD_MRS2__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_PMG_CMD_MRS2__CSB_MASK__SI__CI 0x00600000L -#define MC_PMG_CMD_MRS2__END_MASK__SI__CI 0x00100000L -#define MC_PMG_CMD_MRS2__MOP_MASK__SI__CI 0x00070000L -#define MC_PMG_CMD_MRS__ADR_MASK__SI__CI 0x0000ffffL -#define MC_PMG_CMD_MRS__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_PMG_CMD_MRS__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_PMG_CMD_MRS__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_PMG_CMD_MRS__CSB_MASK__SI__CI 0x00600000L -#define MC_PMG_CMD_MRS__END_MASK__SI__CI 0x00100000L -#define MC_PMG_CMD_MRS__MOP_MASK__SI__CI 0x00070000L -#define MC_PWRMGT__MC_PULSE_EN_MASK__CI__VI 0x00000400L -#define MC_PWRMGT__MC_PULSE_PERIOD_MASK__CI__VI 0x000003ffL -#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_RD_CB__DUMMY_MASK__SI 0x00010000L -#define MC_RD_CB__ENABLE_MASK 0x00000001L -#define MC_RD_CB__LAZY_TIMER_MASK 0x00007800L -#define MC_RD_CB__MAX_BURST_MASK 0x00000780L -#define MC_RD_CB__PRESCALE_MASK 0x00000006L -#define MC_RD_CB__STALL_MODE_MASK 0x00000030L -#define MC_RD_CB__STALL_OVERRIDE_MASK 0x00000040L -#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_RD_DB__DUMMY_MASK__SI 0x00010000L -#define MC_RD_DB__ENABLE_MASK 0x00000001L -#define MC_RD_DB__LAZY_TIMER_MASK 0x00007800L -#define MC_RD_DB__MAX_BURST_MASK 0x00000780L -#define MC_RD_DB__PRESCALE_MASK 0x00000006L -#define MC_RD_DB__STALL_MODE_MASK 0x00000030L -#define MC_RD_DB__STALL_OVERRIDE_MASK 0x00000040L -#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_RD_GRP_EXT__DBSTEN0_MASK 0x0000000fL -#define MC_RD_GRP_EXT__TC0_MASK 0x000000f0L -#define MC_RD_GRP_GFX__ACPG_MASK__CI__VI 0x0000f000L -#define MC_RD_GRP_GFX__ACPO_MASK__CI__VI 0x000f0000L -#define MC_RD_GRP_GFX__CP_MASK 0x0000000fL -#define MC_RD_GRP_GFX__IA_MASK__CI__VI 0x00000f00L -#define MC_RD_GRP_GFX__SH0_MASK__SI 0x000000f0L -#define MC_RD_GRP_GFX__SH1_MASK__SI 0x0000f000L -#define MC_RD_GRP_GFX__SH_MASK__CI__VI 0x000000f0L -#define MC_RD_GRP_GFX__VGT_MASK__SI 0x00000f00L -#define MC_RD_GRP_GFX__XDMAM_MASK__CI 0x00f00000L -#define MC_RD_GRP_GFX__XDMAM_MASK__SI 0x000f0000L -#define MC_RD_GRP_LCL__CB0_MASK 0x0000f000L -#define MC_RD_GRP_LCL__CBCMASK0_MASK 0x000f0000L -#define MC_RD_GRP_LCL__CBFMASK0_MASK 0x00f00000L -#define MC_RD_GRP_LCL__DB0_MASK 0x0f000000L -#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000L -#define MC_RD_GRP_OTH__DRMDMA0_MASK__SI 0x000000f0L -#define MC_RD_GRP_OTH__HDP_MASK 0x00000f00L -#define MC_RD_GRP_OTH__SAM_MASK__CI 0xf0000000L -#define MC_RD_GRP_OTH__SDMA0_MASK__CI__VI 0x000000f0L -#define MC_RD_GRP_OTH__SEM_MASK 0x0000f000L -#define MC_RD_GRP_OTH__SPU_MASK__SI 0xf0000000L -#define MC_RD_GRP_OTH__UMC_MASK 0x000f0000L -#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0x0000000fL -#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0x0f000000L -#define MC_RD_GRP_OTH__UVD_MASK 0x00f00000L -#define MC_RD_GRP_SYS__DMIF_MASK 0x0000f000L -#define MC_RD_GRP_SYS__DRMDMA1_MASK__SI 0x00000f00L -#define MC_RD_GRP_SYS__MCIF_MASK 0x000f0000L -#define MC_RD_GRP_SYS__RLC_MASK 0x0000000fL -#define MC_RD_GRP_SYS__SDMA1_MASK__CI__VI 0x00000f00L -#define MC_RD_GRP_SYS__SMU_MASK 0x00f00000L -#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000L -#define MC_RD_GRP_SYS__VCE_MASK 0x0f000000L -#define MC_RD_GRP_SYS__VMC_MASK 0x000000f0L -#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_RD_HUB__DUMMY_MASK__SI 0x00010000L -#define MC_RD_HUB__ENABLE_MASK 0x00000001L -#define MC_RD_HUB__LAZY_TIMER_MASK 0x00007800L -#define MC_RD_HUB__MAX_BURST_MASK 0x00000780L -#define MC_RD_HUB__PRESCALE_MASK 0x00000006L -#define MC_RD_HUB__STALL_MODE_MASK 0x00000030L -#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x00000040L -#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_RD_TC0__DUMMY_MASK__SI 0x00010000L -#define MC_RD_TC0__ENABLE_MASK 0x00000001L -#define MC_RD_TC0__LAZY_TIMER_MASK 0x00007800L -#define MC_RD_TC0__MAX_BURST_MASK 0x00000780L -#define MC_RD_TC0__PRESCALE_MASK 0x00000006L -#define MC_RD_TC0__STALL_MODE_MASK 0x00000030L -#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x00000040L -#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_RD_TC1__DUMMY_MASK__SI 0x00010000L -#define MC_RD_TC1__ENABLE_MASK 0x00000001L -#define MC_RD_TC1__LAZY_TIMER_MASK 0x00007800L -#define MC_RD_TC1__MAX_BURST_MASK 0x00000780L -#define MC_RD_TC1__PRESCALE_MASK 0x00000006L -#define MC_RD_TC1__STALL_MODE_MASK 0x00000030L -#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x00000040L -#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0x00ff0000L -#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x0000ff00L -#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x000000ffL -#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0x000000ffL -#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0x0000ff00L -#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000L -#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000ffffL -#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x0000003eL -#define MC_RPB_CID_QUEUE_EX__START_MASK 0x00000001L -#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0x000000ffL -#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x00000c00L -#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00000300L -#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0x000000ffL -#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00001800L -#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x00002000L -#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000100L -#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00000600L -#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x00010000L -#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x00020000L -#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x00008000L -#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000L -#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0x000fff00L -#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0x000000ffL -#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000ff00L -#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000ffL -#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0x0000ff00L -#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0x000000ffL -#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L -#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L -#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001e0L -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003e00L -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007c000L -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00f80000L -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000L -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L -#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L -#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffffL -#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL -#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L -#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L -#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L -#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000080L -#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x00000001L -#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x00000078L -#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000006L -#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL -#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L -#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L -#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK__SI__CI 0x00000007L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK__SI__CI 0x00000038L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK__SI__CI 0x000001c0L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK__SI__CI 0x00000e00L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK__SI__CI 0x00007000L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK__SI__CI 0x00038000L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK__SI__CI 0x001c0000L -#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK__SI__CI 0x00e00000L -#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK__SI__CI 0x00000003L -#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK__SI__CI 0x0000000cL -#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK__SI__CI 0x00000030L -#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK__SI__CI 0x000000c0L -#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK__SI__CI 0x00000003L -#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK__SI__CI 0x0000000cL -#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK__SI__CI 0x00000030L -#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK__SI__CI 0x000000c0L -#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK__SI__CI 0x00000e00L -#define MC_SEQ_CAS_TIMING_LP__TCL_MASK__SI__CI 0x1f000000L -#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK__SI__CI 0x0000000cL -#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK__SI__CI 0x00000003L -#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK__SI__CI 0x0000f000L -#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK__SI__CI 0x000001f0L -#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK__SI__CI 0x001f0000L -#define MC_SEQ_CAS_TIMING__TCCDL_MASK__SI__CI 0x00000e00L -#define MC_SEQ_CAS_TIMING__TCL_MASK__SI__CI 0x1f000000L -#define MC_SEQ_CAS_TIMING__TNOPR_MASK__SI__CI 0x0000000cL -#define MC_SEQ_CAS_TIMING__TNOPW_MASK__SI__CI 0x00000003L -#define MC_SEQ_CAS_TIMING__TR2R_MASK__SI__CI 0x0000f000L -#define MC_SEQ_CAS_TIMING__TR2W_MASK__SI__CI 0x000001f0L -#define MC_SEQ_CAS_TIMING__TW2R_MASK__SI__CI 0x001f0000L -#define MC_SEQ_CG__CG_SEQ_REQ_MASK__SI__CI 0x000000ffL -#define MC_SEQ_CG__CG_SEQ_RESP_MASK__SI__CI 0x0000ff00L -#define MC_SEQ_CG__SEQ_CG_REQ_MASK__SI__CI 0x00ff0000L -#define MC_SEQ_CG__SEQ_CG_RESP_MASK__SI__CI 0xff000000L -#define MC_SEQ_CMD__ADR_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_CMD__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_SEQ_CMD__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_SEQ_CMD__CHAN0_MASK__SI__CI 0x01000000L -#define MC_SEQ_CMD__CHAN1_MASK__SI__CI 0x02000000L -#define MC_SEQ_CMD__CSB_MASK__SI__CI 0x00600000L -#define MC_SEQ_CMD__END_MASK__SI__CI 0x00100000L -#define MC_SEQ_CMD__MOP_MASK__SI__CI 0x000f0000L -#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK__SI__CI 0x00000300L -#define MC_SEQ_CNTL_2__DRST_NSTR_MASK__SI__CI 0x0000fc00L -#define MC_SEQ_CNTL_2__DRST_PDRV_MASK__CI 0x0000000fL -#define MC_SEQ_CNTL_2__DRST_PD_MASK__CI 0x00000020L -#define MC_SEQ_CNTL_2__DRST_PSTR_MASK__SI__CI 0x003f0000L -#define MC_SEQ_CNTL_2__DRST_PU_MASK__CI 0x00000010L -#define MC_SEQ_CNTL_2__PIPE_DELAY_IN_1_D0_MASK__SI 0x00000002L -#define MC_SEQ_CNTL_2__PIPE_DELAY_IN_1_D1_MASK__SI 0x00000008L -#define MC_SEQ_CNTL_2__PIPE_DELAY_OUT_1_D0_MASK__SI 0x00000001L -#define MC_SEQ_CNTL_2__PIPE_DELAY_OUT_1_D1_MASK__SI 0x00000004L -#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK__SI__CI 0x0f000000L -#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK__SI__CI 0xf0000000L -#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK__SI__CI 0x00400000L -#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK__SI__CI 0x00800000L -#define MC_SEQ_CNTL_3__CAC_EN_MASK__CI 0x80000000L -#define MC_SEQ_CNTL_3__DBI_FRC_MASK__CI 0x00200000L -#define MC_SEQ_CNTL_3__DQS_FRC_MASK__CI 0x00800000L -#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK__CI 0x0f000000L -#define MC_SEQ_CNTL_3__FCK_FRC_MASK__CI 0x00100000L -#define MC_SEQ_CNTL_3__IDSC_EN_MASK__CI 0x40000000L -#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK__CI 0x00000038L -#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK__CI 0x00000e00L -#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK__CI 0x00000007L -#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK__CI 0x000001c0L -#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK__CI 0x00400000L -#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK__CI 0x00001000L -#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK__CI 0x00002000L -#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK__CI 0x000f0000L -#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK__SI__CI 0x00f00000L -#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK__SI__CI 0x0f000000L -#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK__SI__CI 0xf0000000L -#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK__SI__CI 0x00040000L -#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK__SI__CI 0x00020000L -#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK__SI__CI 0x00000300L -#define MC_SEQ_CNTL__DAT_INV_MASK__SI__CI 0x00000040L -#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK__SI__CI 0x0000000cL -#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK__SI__CI 0x00000003L -#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK__SI__CI 0x00008000L -#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK__SI__CI 0x00004000L -#define MC_SEQ_CNTL__MSK_DF1_MASK__SI__CI 0x00000080L -#define MC_SEQ_CNTL__PIPE_DELAY_IN_D0_MASK__SI 0x00000800L -#define MC_SEQ_CNTL__PIPE_DELAY_IN_D1_MASK__SI 0x00002000L -#define MC_SEQ_CNTL__PIPE_DELAY_OUT_D0_MASK__SI 0x00000400L -#define MC_SEQ_CNTL__PIPE_DELAY_OUT_D1_MASK__SI 0x00001000L -#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK__SI__CI 0x00010000L -#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK__SI__CI 0x00080000L -#define MC_SEQ_CNTL__SAFE_MODE_MASK__SI__CI 0x00000030L -#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK__CI 0x000000e0L -#define MC_SEQ_DLL_STBY_LP__EN_MASK__CI 0x00000001L -#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK__CI 0x3f000000L -#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK__CI 0x00000008L -#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK__CI 0x00000010L -#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK__CI 0x00000f00L -#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK__CI 0x00ff0000L -#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK__CI 0x0000f000L -#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK__CI 0x00000002L -#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK__CI 0x00000004L -#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK__CI 0x000000e0L -#define MC_SEQ_DLL_STBY__EN_MASK__CI 0x00000001L -#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK__CI 0x3f000000L -#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK__CI 0x00000008L -#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK__CI 0x00000010L -#define MC_SEQ_DLL_STBY__STBY_DLY_MASK__CI 0x00000f00L -#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK__CI 0x00ff0000L -#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK__CI 0x0000f000L -#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK__CI 0x00000002L -#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK__CI 0x00000004L -#define MC_SEQ_DRAM_2__ADBI_ACT_MASK__SI__CI 0x04000000L -#define MC_SEQ_DRAM_2__ADBI_DF1_MASK__SI__CI 0x02000000L -#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK__SI__CI 0x00000004L -#define MC_SEQ_DRAM_2__ADR_DBI_MASK__SI__CI 0x00000002L -#define MC_SEQ_DRAM_2__ADR_DDR_MASK__SI__CI 0x00000001L -#define MC_SEQ_DRAM_2__BNK_MRS_MASK__SI__CI 0x00002000L -#define MC_SEQ_DRAM_2__CMD_QDR_MASK__SI__CI 0x00000008L -#define MC_SEQ_DRAM_2__CS_BY16_MASK__SI__CI 0x80000000L -#define MC_SEQ_DRAM_2__DAT_QDR_MASK__SI__CI 0x00000010L -#define MC_SEQ_DRAM_2__DBI_ACT_MASK__SI__CI 0x10000000L -#define MC_SEQ_DRAM_2__DBI_DF1_MASK__SI__CI 0x08000000L -#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK__SI__CI 0x20000000L -#define MC_SEQ_DRAM_2__DBI_OVR_MASK__SI__CI 0x00004000L -#define MC_SEQ_DRAM_2__DLL_EST_MASK__SI__CI 0x00001000L -#define MC_SEQ_DRAM_2__DQM_EST_MASK__SI__CI 0x00000080L -#define MC_SEQ_DRAM_2__PCH_BNK_MASK__SI__CI 0x01000000L -#define MC_SEQ_DRAM_2__PLL_CLR_MASK__SI__CI 0x00000800L -#define MC_SEQ_DRAM_2__PLL_CNT_MASK__SI__CI 0x00ff0000L -#define MC_SEQ_DRAM_2__PLL_EST_MASK__SI__CI 0x00000400L -#define MC_SEQ_DRAM_2__RDAT_EDC_MASK__SI__CI 0x00000040L -#define MC_SEQ_DRAM_2__RD_DQS_MASK__SI__CI 0x00000100L -#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK__SI__CI 0x40000000L -#define MC_SEQ_DRAM_2__TRI_CLK_MASK__SI__CI 0x00008000L -#define MC_SEQ_DRAM_2__WDAT_EDC_MASK__SI__CI 0x00000020L -#define MC_SEQ_DRAM_2__WR_DQS_MASK__SI__CI 0x00000200L -#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK__SI__CI 0xffff0000L -#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_DRAM__ADR_2CK_MASK__SI__CI 0x00000001L -#define MC_SEQ_DRAM__ADR_DF1_MASK__SI__CI 0x00000004L -#define MC_SEQ_DRAM__ADR_MUX_MASK__SI__CI 0x00000002L -#define MC_SEQ_DRAM__AP8_MASK__SI__CI 0x00000008L -#define MC_SEQ_DRAM__BO4_MASK__SI__CI 0x00004000L -#define MC_SEQ_DRAM__CKE_ACT_MASK__SI__CI 0x00002000L -#define MC_SEQ_DRAM__CKE_DYN_MASK__SI__CI 0x00001000L -#define MC_SEQ_DRAM__DAT_DF1_MASK__SI__CI 0x00000010L -#define MC_SEQ_DRAM__DAT_INV_MASK__SI__CI 0x01000000L -#define MC_SEQ_DRAM__DLL_CLR_MASK__SI__CI 0x00008000L -#define MC_SEQ_DRAM__DLL_CNT_MASK__SI__CI 0x00ff0000L -#define MC_SEQ_DRAM__DQM_ACT_MASK__SI__CI 0x00000080L -#define MC_SEQ_DRAM__DQM_DF1_MASK__SI__CI 0x00000040L -#define MC_SEQ_DRAM__DQS_DF1_MASK__SI__CI 0x00000020L -#define MC_SEQ_DRAM__INV_ACM_MASK__SI__CI 0x02000000L -#define MC_SEQ_DRAM__ODT_ACT_MASK__SI__CI 0x08000000L -#define MC_SEQ_DRAM__ODT_ENB_MASK__SI__CI 0x04000000L -#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK__CI 0x80000000L -#define MC_SEQ_DRAM__RST_CTL_MASK__SI__CI 0x10000000L -#define MC_SEQ_DRAM__STB_CNT_MASK__SI__CI 0x00000f00L -#define MC_SEQ_DRAM__TRI_CKE_MASK__SI__CI 0x40000000L -#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK__SI__CI 0x20000000L -#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK__SI__CI 0x00000100L -#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK__SI__CI 0x00000200L -#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK__CI 0x10000000L -#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK__CI 0x00f00000L -#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK__CI 0x0f000000L -#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK__SI__CI 0x00000030L -#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK__SI__CI 0x000000c0L -#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK__SI__CI 0x00007000L -#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK__SI__CI 0x00030000L -#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK__SI__CI 0x000c0000L -#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK__SI__CI 0x00000003L -#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK__SI__CI 0x00000c00L -#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK__SI__CI 0x0000000cL -#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK__CI 0xffffffffL -#define MC_SEQ_G5PDX_CMD0__CMD_MASK__CI 0xffffffffL -#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK__CI 0xffffffffL -#define MC_SEQ_G5PDX_CMD1__CMD_MASK__CI 0xffffffffL -#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK__CI 0x00000001L -#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK__CI 0x00000002L -#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK__CI 0x00f00000L -#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK__CI 0x0000f000L -#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK__CI 0x000003f0L -#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK__CI 0x000f0000L -#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK__CI 0x00000004L -#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK__CI 0x00000008L -#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK__CI 0x00000001L -#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK__CI 0x00000002L -#define MC_SEQ_G5PDX_CTRL__TMRD_MASK__CI 0x00f00000L -#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK__CI 0x0000f000L -#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK__CI 0x000003f0L -#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK__CI 0x000f0000L -#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK__CI 0x00000004L -#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK__CI 0x00000008L -#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK__SI__CI 0x000001ffL -#define MC_SEQ_IO_RDBI__MASK_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_REDC__EDC_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK__SI__CI 0xff000000L -#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK__SI__CI 0x00000fffL -#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK__SI__CI 0x00fff000L -#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK__SI__CI 0xff000000L -#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK__SI__CI 0x00000fffL -#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK__SI__CI 0x00fff000L -#define MC_SEQ_IO_RWORD0__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RWORD1__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RWORD2__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RWORD3__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RWORD4__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RWORD5__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RWORD6__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_IO_RWORD7__RDATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC0__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC1__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC3__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC4__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC5__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC6__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC7__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC8__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC9__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK__SI__CI 0x00001f00L -#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK__SI__CI 0x00000007L -#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK__SI__CI 0x00000070L -#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK__SI__CI 0x00e00000L -#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK__SI__CI 0x0f000000L -#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK__SI__CI 0x0000e000L -#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK__SI__CI 0xf0000000L -#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK__SI__CI 0x001f0000L -#define MC_SEQ_MISC_TIMING2__FAW_MASK__SI__CI 0x00001f00L -#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK__SI__CI 0x00000007L -#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK__SI__CI 0x00000070L -#define MC_SEQ_MISC_TIMING2__T32AW_MASK__SI__CI 0x01e00000L -#define MC_SEQ_MISC_TIMING2__TREDC_MASK__SI__CI 0x0000e000L -#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK__SI__CI 0xf0000000L -#define MC_SEQ_MISC_TIMING2__TWEDC_MASK__SI__CI 0x001f0000L -#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK__SI__CI 0x1ff00000L -#define MC_SEQ_MISC_TIMING_LP__TRP_MASK__SI__CI 0x000f8000L -#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK__SI__CI 0x00003f00L -#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK__SI__CI 0x0000003fL -#define MC_SEQ_MISC_TIMING__TRFC_MASK__SI__CI 0x1ff00000L -#define MC_SEQ_MISC_TIMING__TRP_MASK__SI__CI 0x000f8000L -#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK__SI__CI 0x00003f00L -#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK__SI__CI 0x0000003fL -#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK__SI__CI 0x00000001L -#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK__SI__CI 0x00000020L -#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK__SI__CI 0x00000002L -#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK__SI__CI 0x00000004L -#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK__SI__CI 0x00000008L -#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK__SI__CI 0x00000010L -#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK__SI__CI 0x00000040L -#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK__SI__CI 0x00000080L -#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK__SI__CI 0x00000001L -#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK__SI__CI 0x00000100L -#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK__SI__CI 0x00000200L -#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK__SI__CI 0x00000400L -#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK__SI__CI 0x00000800L -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK__SI__CI 0x00001000L -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK__SI__CI 0x00002000L -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK__SI__CI 0x00004000L -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK__SI__CI 0x00008000L -#define MC_SEQ_PERF_CNTL__CNTL_MASK__SI__CI 0xc0000000L -#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK__SI__CI 0x3fffffffL -#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK__SI__CI 0x0000000fL -#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK__SI__CI 0x000000f0L -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK__SI__CI 0x00000f00L -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK__SI__CI 0x0000f000L -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK__SI__CI 0x000f0000L -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK__SI__CI 0x00f00000L -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK__SI__CI 0x0f000000L -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK__SI__CI 0xf0000000L -#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK__CI 0x00008000L -#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK__CI 0x00000001L -#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK__CI 0x00000002L -#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK__CI 0x00000080L -#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK__CI 0x00002000L -#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK__CI 0x00004000L -#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK__CI 0x00000200L -#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK__CI 0x00000100L -#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK__CI 0x00000400L -#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK__CI 0x00001000L -#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK__CI 0x00000800L -#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK__SI__CI 0x00600000L -#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK__SI__CI 0x00100000L -#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK__SI__CI 0x00070000L -#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK__SI__CI 0x00600000L -#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK__SI__CI 0x00100000L -#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK__SI__CI 0x00070000L -#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK__SI__CI 0x00600000L -#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK__SI__CI 0x00100000L -#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK__SI__CI 0x00070000L -#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK__SI__CI 0x20000000L -#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK__SI__CI 0x10000000L -#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK__SI__CI 0x00080000L -#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK__SI__CI 0x00600000L -#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK__SI__CI 0x00100000L -#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK__SI__CI 0x00070000L -#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK__CI 0x0000ffffL -#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK__CI 0x01000000L -#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK__CI 0x00800000L -#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK__CI 0x00080000L -#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK__CI 0x00600000L -#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK__CI 0x00100000L -#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK__CI 0x00070000L -#define MC_SEQ_PMG_DVS_CMD__ADR_MASK__CI 0x0000ffffL -#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK__CI 0x01000000L -#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK__CI 0x00800000L -#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK__CI 0x00080000L -#define MC_SEQ_PMG_DVS_CMD__CSB_MASK__CI 0x00600000L -#define MC_SEQ_PMG_DVS_CMD__END_MASK__CI 0x00100000L -#define MC_SEQ_PMG_DVS_CMD__MOP_MASK__CI 0x00070000L -#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK__CI 0x00000001L -#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK__CI 0x0000003eL -#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK__CI 0x00000001L -#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK__CI 0x0000003eL -#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK__SI__CI 0x00040000L -#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK__SI__CI 0x00000300L -#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK__SI__CI 0x000000c0L -#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK__SI__CI 0x00003c00L -#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK__SI__CI 0x00000001L -#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK__SI__CI 0x00020000L -#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK__SI__CI 0x00000002L -#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK__SI__CI 0x0000003cL -#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK__SI__CI 0x00010000L -#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK__SI__CI 0x80000000L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK__SI__CI 0x00010000L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK__SI__CI 0x00000020L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK__SI__CI 0x00000002L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK__SI__CI 0x00000010L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK__SI__CI 0x00000001L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK__SI__CI 0x00000040L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK__SI__CI 0x00000004L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK__SI__CI 0x00000080L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK__SI__CI 0x00000008L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK__SI__CI 0x00002000L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK__SI__CI 0x00000200L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK__SI__CI 0x00001000L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK__SI__CI 0x00000100L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK__SI__CI 0x00004000L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK__SI__CI 0x00000400L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK__SI__CI 0x00008000L -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK__SI__CI 0x00000800L -#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK__SI__CI 0x80000000L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK__SI__CI 0x00010000L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK__SI__CI 0x00000020L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK__SI__CI 0x00000002L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK__SI__CI 0x00000010L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK__SI__CI 0x00000001L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK__SI__CI 0x00000040L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK__SI__CI 0x00000004L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK__SI__CI 0x00000080L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK__SI__CI 0x00000008L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK__SI__CI 0x00002000L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK__SI__CI 0x00000200L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK__SI__CI 0x00001000L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK__SI__CI 0x00000100L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK__SI__CI 0x00004000L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK__SI__CI 0x00000400L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK__SI__CI 0x00008000L -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK__SI__CI 0x00000800L -#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK__SI__CI 0x001c0000L -#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK__CI 0xff000000L -#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK__SI__CI 0x0003f000L -#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK__SI__CI 0x00000f00L -#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK__SI__CI 0x00800000L -#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK__SI__CI 0x00000007L -#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK__SI__CI 0x00000070L -#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK__SI__CI 0x001c0000L -#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK__CI 0xff000000L -#define MC_SEQ_PMG_TIMING__TCKE_MASK__SI__CI 0x0003f000L -#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK__SI__CI 0x00000f00L -#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK__SI__CI 0x00800000L -#define MC_SEQ_PMG_TIMING__TCKSRE_MASK__SI__CI 0x00000007L -#define MC_SEQ_PMG_TIMING__TCKSRX_MASK__SI__CI 0x00000070L -#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK__SI__CI 0x000f8000L -#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK__SI__CI 0x00007c00L -#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK__SI__CI 0x000003e0L -#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK__SI__CI 0x0000001fL -#define MC_SEQ_RAS_TIMING_LP__TRC_MASK__SI__CI 0x7f000000L -#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RAS_TIMING__TRCDRA_MASK__SI__CI 0x000f8000L -#define MC_SEQ_RAS_TIMING__TRCDR_MASK__SI__CI 0x00007c00L -#define MC_SEQ_RAS_TIMING__TRCDWA_MASK__SI__CI 0x000003e0L -#define MC_SEQ_RAS_TIMING__TRCDW_MASK__SI__CI 0x0000001fL -#define MC_SEQ_RAS_TIMING__TRC_MASK__SI__CI 0x7f000000L -#define MC_SEQ_RAS_TIMING__TRRD_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK__SI__CI 0x01f00000L -#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK__SI__CI 0x3e000000L -#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK__SI__CI 0x00000007L -#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK__SI__CI 0x000000f8L -#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK__SI__CI 0x00000300L -#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK__SI__CI 0x00000c00L -#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK__SI__CI 0x00010000L -#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK__SI__CI 0x00020000L -#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK__SI__CI 0x01f00000L -#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK__SI__CI 0x3e000000L -#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK__SI__CI 0x00000007L -#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK__SI__CI 0x000000f8L -#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK__SI__CI 0x00000300L -#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK__SI__CI 0x00000c00L -#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK__SI__CI 0x00010000L -#define MC_SEQ_RD_CTL_D0__STR_PST_MASK__SI__CI 0x00020000L -#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK__SI__CI 0x01f00000L -#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK__SI__CI 0x3e000000L -#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK__SI__CI 0x00000007L -#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK__SI__CI 0x000000f8L -#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK__SI__CI 0x00000300L -#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK__SI__CI 0x00000c00L -#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK__SI__CI 0x00010000L -#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK__SI__CI 0x00020000L -#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK__SI__CI 0x01f00000L -#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK__SI__CI 0x3e000000L -#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK__SI__CI 0x00000007L -#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK__SI__CI 0x000000f8L -#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK__SI__CI 0x00000300L -#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK__SI__CI 0x00000c00L -#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK__SI__CI 0x00010000L -#define MC_SEQ_RD_CTL_D1__STR_PST_MASK__SI__CI 0x00020000L -#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK__SI__CI 0xffffffffL -#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK__SI__CI 0xffffffffL -#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK__SI__CI 0xffffffffL -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK__SI__CI 0xf0000000L -#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK__SI__CI 0x000f0000L -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK__SI__CI 0x00f00000L -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK__SI__CI 0x0f000000L -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK__SI__CI 0xf0000000L -#define MC_SEQ_SREG_READ__DATA_MASK__CI 0xffffffffL -#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK__CI 0x0000000fL -#define MC_SEQ_SREG_STATUS__PND_RD_MASK__CI 0x00000f00L -#define MC_SEQ_SREG_STATUS__PND_WR_MASK__CI 0x0000f000L -#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK__SI__CI 0x00000004L -#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK__SI__CI 0x00000008L -#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK__SI__CI 0x01f00000L -#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK__SI__CI 0x00010000L -#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK__SI__CI 0x00000001L -#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK__SI__CI 0x00000002L -#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK__CI 0x08000000L -#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK__SI__CI 0x00000100L -#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK__SI__CI 0x02000000L -#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK__SI__CI 0x00004000L -#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK__SI__CI 0x00001000L -#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK__CI 0x10000000L -#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK__SI__CI 0x00000200L -#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK__SI__CI 0x04000000L -#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK__SI__CI 0x00008000L -#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK__SI__CI 0x00002000L -#define MC_SEQ_STATUS_M__SLF_D0_MASK__SI__CI 0x00000010L -#define MC_SEQ_STATUS_M__SLF_D1_MASK__SI__CI 0x00000020L -#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK__SI__CI 0x00000040L -#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK__SI__CI 0x00000080L -#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK__SI__CI 0x00000010L -#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK__SI__CI 0x00000001L -#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK__SI__CI 0x00000100L -#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK__SI__CI 0x00000020L -#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK__SI__CI 0x00000002L -#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK__SI__CI 0x00000200L -#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK__SI__CI 0x00000080L -#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK__SI__CI 0x00000040L -#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK__SI__CI 0xff800000L -#define MC_SEQ_SUP_CNTL__PGM_READ_MASK__SI__CI 0x00000020L -#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK__SI__CI 0x00000010L -#define MC_SEQ_SUP_CNTL__RESET_PC_MASK__SI__CI 0x00000008L -#define MC_SEQ_SUP_CNTL__RUN_MASK__SI__CI 0x00000001L -#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK__SI__CI 0x00000002L -#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK__SI__CI 0x00000004L -#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_IR_STAT__STATUS_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_PGM__CNTL_MASK__SI__CI 0xffffffffL -#define MC_SEQ_SUP_R_PGM__PGM_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK__SI__CI 0x04000000L -#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK__SI__CI 0x02000000L -#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK__SI__CI 0x00380000L -#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TCG_CNTL__DONE_MASK__SI__CI 0x80000000L -#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK__SI__CI 0x00000002L -#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK__SI__CI 0x00000004L -#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK__SI__CI 0x00040000L -#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK__SI__CI 0x00000080L -#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK__SI__CI 0x00400000L -#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK__CI 0x20000000L -#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK__CI 0x10000000L -#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK__SI__CI 0x00010000L -#define MC_SEQ_TCG_CNTL__MOP_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TCG_CNTL__NFIFO_MASK__SI__CI 0x00000070L -#define MC_SEQ_TCG_CNTL__RESET_MASK__SI__CI 0x00000001L -#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK__SI__CI 0x00020000L -#define MC_SEQ_TCG_CNTL__START_MASK__SI__CI 0x00000008L -#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK__SI__CI 0x00800000L -#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK__SI__CI 0x01000000L -#define MC_SEQ_TIMER_RD__COUNTER_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TIMER_WR__COUNTER_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK__SI__CI 0x00040000L -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK__SI__CI 0x00080000L -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK__SI__CI 0x00200000L -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK__SI__CI 0x00400000L -#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK__SI__CI 0x00000001L -#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000100L -#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000400L -#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK__SI__CI 0x01000000L -#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK__SI__CI 0x00000004L -#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK__SI__CI 0x00000010L -#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK__SI__CI 0x00000002L -#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000200L -#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000800L -#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK__SI__CI 0x02000000L -#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK__SI__CI 0x00000008L -#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK__SI__CI 0x00000020L -#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK__SI__CI 0x00800000L -#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK__SI__CI 0x00100000L -#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK__SI__CI 0x00000040L -#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK__CI 0x04000000L -#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK__SI__CI 0x00002000L -#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK__SI__CI 0x00000080L -#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK__SI__CI 0x00001000L -#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK__CI 0x08000000L -#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK__SI__CI 0x00020000L -#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK__SI__CI 0x00008000L -#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK__SI__CI 0x00004000L -#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK__SI__CI 0x00000100L -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK__SI__CI 0x00000001L -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK__SI__CI 0x00000200L -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK__SI__CI 0x00000002L -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK__SI__CI 0x00000004L -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK__SI__CI 0x00000030L -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK__SI__CI 0x00000008L -#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK__SI__CI 0xffff0000L -#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK__SI__CI 0x000003e0L -#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK__SI__CI 0x000f8000L -#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK__SI__CI 0x00007c00L -#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK__SI__CI 0x0000001fL -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK__SI__CI 0x00040000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK__SI__CI 0x00080000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK__SI__CI 0x00200000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK__SI__CI 0x00400000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK__SI__CI 0x00010000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK__SI__CI 0x00000001L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000100L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000400L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK__SI__CI 0x01000000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK__SI__CI 0x00000004L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK__SI__CI 0x00000010L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK__SI__CI 0x00000002L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000200L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000800L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK__SI__CI 0x02000000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK__SI__CI 0x00000008L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK__SI__CI 0x00000020L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK__SI__CI 0x00800000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK__SI__CI 0x00100000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK__SI__CI 0x00000040L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK__CI 0x04000000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK__SI__CI 0x00002000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK__SI__CI 0x00000080L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK__SI__CI 0x00001000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK__CI 0x08000000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK__SI__CI 0x00020000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK__SI__CI 0x00008000L -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK__SI__CI 0x00004000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK__SI__CI 0x00000100L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK__SI__CI 0x00000400L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK__SI__CI 0x00100000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK__SI__CI 0x00000200L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK__SI__CI 0x00000800L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK__SI__CI 0x01000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK__SI__CI 0x04000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK__SI__CI 0x02000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK__SI__CI 0x08000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK__SI__CI 0x00000001L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK__SI__CI 0x00000004L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK__SI__CI 0x00000002L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK__SI__CI 0x00000008L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK__SI__CI 0x20000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK__SI__CI 0x00010000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK__SI__CI 0x00040000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK__SI__CI 0x00020000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK__SI__CI 0x00080000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK__SI__CI 0x00000010L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK__SI__CI 0x00000040L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK__SI__CI 0x00000020L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK__SI__CI 0x00000080L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK__SI__CI 0x00200000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK__SI__CI 0x00400000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK__SI__CI 0x10000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK__SI__CI 0x40000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK__SI__CI 0x80000000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK__SI__CI 0x00001000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK__SI__CI 0x00004000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK__SI__CI 0x00002000L -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK__SI__CI 0x00008000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK__SI__CI 0x00040000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK__SI__CI 0x00080000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK__SI__CI 0x00200000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK__SI__CI 0x00400000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK__SI__CI 0x00000001L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000100L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000400L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK__SI__CI 0x01000000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK__SI__CI 0x00000004L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK__SI__CI 0x00000010L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK__SI__CI 0x00000002L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000200L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000800L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK__SI__CI 0x02000000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK__SI__CI 0x00000008L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK__SI__CI 0x00000020L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK__SI__CI 0x00800000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK__SI__CI 0x00100000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK__SI__CI 0x00000040L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK__CI 0x04000000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK__SI__CI 0x00002000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK__SI__CI 0x00000080L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK__SI__CI 0x00001000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK__CI 0x08000000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK__SI__CI 0x00020000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK__SI__CI 0x00008000L -#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK__SI__CI 0x00004000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK__SI__CI 0x00040000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK__SI__CI 0x00080000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK__SI__CI 0x00200000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK__SI__CI 0x00400000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK__SI__CI 0x00000001L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000100L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000400L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK__SI__CI 0x01000000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK__SI__CI 0x00000004L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK__SI__CI 0x00000010L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK__SI__CI 0x00000002L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000200L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK__SI__CI 0x00000800L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK__SI__CI 0x02000000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK__SI__CI 0x00000008L -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK__SI__CI 0x00000020L -#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK__SI__CI 0x00800000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK__SI__CI 0x00100000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK__SI__CI 0x00000040L -#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK__CI 0x04000000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK__SI__CI 0x00002000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK__SI__CI 0x00000080L -#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK__SI__CI 0x00001000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK__CI 0x08000000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK__SI__CI 0x00020000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK__SI__CI 0x00008000L -#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK__SI__CI 0x00004000L -#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK__SI__CI 0x0000ff00L -#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK__SI__CI 0x00ff0000L -#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK__SI__CI 0xff000000L -#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK__SI__CI 0x00000002L -#define MC_SEQ_TSM_CTRL__DIRECTION_MASK__SI__CI 0x00000020L -#define MC_SEQ_TSM_CTRL__DONE0_MASK__CI 0x00001000L -#define MC_SEQ_TSM_CTRL__DONE1_MASK__CI 0x00002000L -#define MC_SEQ_TSM_CTRL__DONE_MASK__SI__CI 0x00000004L -#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK__CI 0x00000800L -#define MC_SEQ_TSM_CTRL__ERR_MASK__SI__CI 0x00000008L -#define MC_SEQ_TSM_CTRL__INVERT_MASK__SI__CI 0x00000040L -#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK__SI__CI 0x00000080L -#define MC_SEQ_TSM_CTRL__POINTER_MASK__SI__CI 0xffff0000L -#define MC_SEQ_TSM_CTRL__ROT_INV_MASK__SI__CI 0x00000400L -#define MC_SEQ_TSM_CTRL__START_MASK__SI__CI 0x00000001L -#define MC_SEQ_TSM_CTRL__STEP_MASK__SI__CI 0x00000010L -#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK__SI__CI 0x00000300L -#define MC_SEQ_TSM_DBI__DBI_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK__SI__CI 0x0000001fL -#define MC_SEQ_TSM_EDC__EDC_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK__SI__CI 0xff000000L -#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK__SI__CI 0x0000ff00L -#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK__SI__CI 0xffff0000L -#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TSM_GCNT__TESTS_MASK__SI__CI 0x0000ff00L -#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK__CI 0x03f00000L -#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK__CI 0xfc000000L -#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK__SI__CI 0x0000ffffL -#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TSM_NCNT__TESTS_MASK__SI__CI 0x0000ff00L -#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK__SI__CI 0xffff0000L -#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TSM_OCNT__TESTS_MASK__SI__CI 0x0000ff00L -#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK__SI__CI 0x00ff0000L -#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK__SI__CI 0xff000000L -#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK__SI__CI 0x0000ff00L -#define MC_SEQ_TSM_WCDR__WCDR_MASK__SI__CI 0xffffffffL -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK__SI__CI 0x000f0000L -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK__SI__CI 0x00f00000L -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK__SI__CI 0x0f000000L -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK__SI__CI 0xf0000000L -#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK__SI__CI 0x0000000fL -#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK__SI__CI 0x000000f0L -#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK__SI__CI 0x00000f00L -#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK__SI__CI 0x0000f000L -#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK__SI__CI 0xffffffffL -#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK__SI__CI 0x00004000L -#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK__SI__CI 0x00100000L -#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK__SI__CI 0x00200000L -#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK__SI__CI 0x0f000000L -#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK__SI__CI 0xf0000000L -#define MC_SEQ_WCDR_CTRL__RD_EN_MASK__SI__CI 0x00002000L -#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK__SI__CI 0x00008000L -#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK__SI__CI 0x000f0000L -#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK__SI__CI 0x000000ffL -#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK__SI__CI 0x00000f00L -#define MC_SEQ_WCDR_CTRL__WR_EN_MASK__SI__CI 0x00001000L -#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK__SI__CI 0x00000001L -#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK__SI__CI 0x00000008L -#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK__SI__CI 0x00000002L -#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK__SI__CI 0x00000010L -#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK__SI__CI 0x00000004L -#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK__SI__CI 0x00000020L -#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK__SI__CI 0x00000040L -#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK__SI__CI 0x00000001L -#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK__SI__CI 0x00000008L -#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK__SI__CI 0x00000002L -#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK__SI__CI 0x00000010L -#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK__SI__CI 0x00000004L -#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK__SI__CI 0x00000020L -#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK__SI__CI 0x00000040L -#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK__SI__CI 0x00000400L -#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK__SI__CI 0x20000000L -#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK__SI__CI 0x00000800L -#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK__SI__CI 0x40000000L -#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK__SI__CI 0x00000200L -#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK__SI__CI 0x0000000fL -#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK__SI__CI 0x000000f0L -#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK__SI__CI 0x00000100L -#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK__SI__CI 0x0f000000L -#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK__SI__CI 0x10000000L -#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK__SI__CI 0x0000f000L -#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK__SI__CI 0x000f0000L -#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK__SI__CI 0x00300000L -#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK__SI__CI 0x00000400L -#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK__SI__CI 0x20000000L -#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK__SI__CI 0x00000800L -#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK__SI__CI 0x40000000L -#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK__SI__CI 0x00000200L -#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK__SI__CI 0x0000000fL -#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK__SI__CI 0x000000f0L -#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK__SI__CI 0x00000100L -#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK__SI__CI 0x0f000000L -#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK__SI__CI 0x10000000L -#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK__SI__CI 0x0000f000L -#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK__SI__CI 0x000f0000L -#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK__SI__CI 0x00300000L -#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK__SI__CI 0x00000400L -#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK__SI__CI 0x20000000L -#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK__SI__CI 0x00000800L -#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK__SI__CI 0x40000000L -#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK__SI__CI 0x00000200L -#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK__SI__CI 0x0000000fL -#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK__SI__CI 0x000000f0L -#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK__SI__CI 0x00000100L -#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK__SI__CI 0x0f000000L -#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK__SI__CI 0x10000000L -#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK__SI__CI 0x0000f000L -#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK__SI__CI 0x000f0000L -#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK__SI__CI 0x00300000L -#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK__SI__CI 0x00000400L -#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK__SI__CI 0x20000000L -#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK__SI__CI 0x00000800L -#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK__SI__CI 0x40000000L -#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK__SI__CI 0x00000200L -#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK__SI__CI 0x0000000fL -#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK__SI__CI 0x000000f0L -#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK__SI__CI 0x00000100L -#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK__SI__CI 0x0f000000L -#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK__SI__CI 0x10000000L -#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK__SI__CI 0x0000f000L -#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK__SI__CI 0x000f0000L -#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK__SI__CI 0x00300000L -#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x00000007L -#define MC_SHARED_BLACKOUT_CNTL__GFX_CLEAR_MASK__SI 0x00000020L -#define MC_SHARED_BLACKOUT_CNTL__GFX_STALL_MASK__SI 0x00000010L -#define MC_SHARED_CHMAP__CHAN0_MASK 0x0000000fL -#define MC_SHARED_CHMAP__CHAN1_MASK 0x000000f0L -#define MC_SHARED_CHMAP__CHAN2_MASK 0x00000f00L -#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0x0000f000L -#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK__SI__CI 0x000000ffL -#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK__SI__CI 0x0000ff00L -#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK__SI__CI 0x00ff0000L -#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK__SI__CI 0xff000000L -#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK__SI__CI 0x000000ffL -#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK__SI__CI 0x0000ff00L -#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK__SI__CI 0x00ff0000L -#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK__SI__CI 0xff000000L -#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK__SI__CI 0xffff0000L -#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK__SI__CI 0x0000ffffL -#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK__SI__CI 0xffff0000L -#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK__SI__CI 0x0000ffffL -#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK__SI__CI 0xffffffffL -#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK__SI__CI 0xffffffffL -#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK__SI__CI 0x0000000fL -#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK__SI__CI 0x000000f0L -#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK__SI__CI 0x10000000L -#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK__SI__CI 0x20000000L -#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK__SI__CI 0x40000000L -#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK__SI__CI 0x0000f000L -#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK__SI__CI 0x00000f00L -#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK__SI__CI 0x0000000fL -#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK__SI__CI 0x000000f0L -#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK__SI__CI 0x10000000L -#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK__SI__CI 0x20000000L -#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK__SI__CI 0x40000000L -#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK__SI__CI 0x0000f000L -#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK__SI__CI 0x00000f00L -#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK__SI__CI 0x10000000L -#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK__SI__CI 0x03ff0000L -#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK__SI__CI 0x00000400L -#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK__SI__CI 0x00000002L -#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK__SI__CI 0x00000100L -#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK__SI__CI 0x00000001L -#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK__SI__CI 0x00000030L -#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK__SI__CI 0x00000200L -#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK__SI__CI 0x00000800L -#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK__SI__CI 0x10000000L -#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK__SI__CI 0x03ff0000L -#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK__SI__CI 0x00000400L -#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK__SI__CI 0x00000002L -#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK__SI__CI 0x00000100L -#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK__SI__CI 0x00000001L -#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK__SI__CI 0x00000030L -#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK__SI__CI 0x00000200L -#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK__SI__CI 0x00000800L -#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK__SI__CI 0x0000ff00L -#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK__SI__CI 0x00ff0000L -#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK__SI__CI 0xff000000L -#define MC_TSM_DEBUG_BKPT__DATA_MASK__SI__CI 0xffffffffL -#define MC_TSM_DEBUG_FLAG__DATA_MASK__SI__CI 0xffffffffL -#define MC_TSM_DEBUG_GCNT__DATA_MASK__SI__CI 0xffffffffL -#define MC_TSM_DEBUG_MISC__FLAG_MASK__SI__CI 0x000000ffL -#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK__SI__CI 0x00000f00L -#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK__SI__CI 0x0000f000L -#define MC_TSM_DEBUG_ST01__DATA_MASK__SI__CI 0xffffffffL -#define MC_TSM_DEBUG_ST23__DATA_MASK__SI__CI 0xffffffffL -#define MC_TSM_DEBUG_ST45__DATA_MASK__SI__CI 0xffffffffL -#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x0003ffffL -#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x0003ffffL -#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x0003ffffL -#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x00000100L -#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x00000200L -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x00000003L -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0x0000000cL -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x00000030L -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0x000000c0L -#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL -#define MC_VM_FB_LOCATION__FB_BASE_MASK 0x0000ffffL -#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000L -#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0003ffffL -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK__CI__VI 0x20000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK__CI__VI 0x10000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK__CI__VI 0x0f000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__CI__VI 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK__CI__VI 0x000000ffL -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK__CI__VI 0xffff0000L -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK__CI__VI 0x0000ffffL -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK__CI__VI 0xffffffffL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__CI__VI 0x02000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__CI__VI 0x01000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__CI__VI 0x0000000fL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__CI__VI 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__CI__VI 0x04000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__CI__VI 0x00ff0000L -#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L -#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L -#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L -#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L -#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK__CI__VI 0x00080000L -#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L -#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L -#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L -#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L -#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK__CI__VI 0x00080000L -#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L -#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L -#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L -#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L -#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK__CI__VI 0x00080000L -#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL -#define MC_VM_MB_SECURE__ENABLE_INSECURE_READS_WHEN_SECURE_MASK__SI 0x00000001L -#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L -#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L -#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L -#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L -#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK__CI__VI 0x00080000L -#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L -#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L -#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L -#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L -#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK__CI__VI 0x00080000L -#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L -#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L -#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L -#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L -#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK__CI__VI 0x00080000L -#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L -#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L -#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L -#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L -#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK__CI__VI 0x00080000L -#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x00000001L -#define MC_VM_MD_L1_TLB4_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK__SI 0x00007000L -#define MC_VM_MD_L1_TLB4_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK__SI 0x00000e00L -#define MC_VM_MD_L1_TLB4_DEBUG__INVALIDATE_L1_TLB_MASK__SI 0x00000001L -#define MC_VM_MD_L1_TLB4_DEBUG__L1_TLB_DEBUG_MASK__SI 0x00078000L -#define MC_VM_MD_L1_TLB4_DEBUG__SEND_FREE_AT_RTN_MASK__SI 0x00000100L -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MD_L1_TLB4_STATUS__BUSY_MASK__SI 0x00000001L -#define MC_VM_MD_L1_TLB5_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK__SI 0x00007000L -#define MC_VM_MD_L1_TLB5_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK__SI 0x00000e00L -#define MC_VM_MD_L1_TLB5_DEBUG__INVALIDATE_L1_TLB_MASK__SI 0x00000001L -#define MC_VM_MD_L1_TLB5_DEBUG__L1_TLB_DEBUG_MASK__SI 0x00078000L -#define MC_VM_MD_L1_TLB5_DEBUG__SEND_FREE_AT_RTN_MASK__SI 0x00000100L -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000010L -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER_MASK__SI \ - 0x00000008L -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS_MASK__SI 0x00000fc0L -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x00000007L -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000020L -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define MC_VM_MD_L1_TLB5_STATUS__BUSY_MASK__SI 0x00000001L -#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL -#define MC_VM_MD_SECURE__ENABLE_INSECURE_READS_WHEN_SECURE_MASK__SI 0x00000001L -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x00000002L -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L -#define MC_VM_STEERING__DEFAULT_STEERING_MASK__CI__VI 0x00000003L -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_WR_CB__DUMMY_MASK__SI 0x00010000L -#define MC_WR_CB__ENABLE_MASK 0x00000001L -#define MC_WR_CB__LAZY_TIMER_MASK 0x00007800L -#define MC_WR_CB__MAX_BURST_MASK 0x00000780L -#define MC_WR_CB__PRESCALE_MASK 0x00000006L -#define MC_WR_CB__STALL_MODE_MASK 0x00000030L -#define MC_WR_CB__STALL_OVERRIDE_MASK 0x00000040L -#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_WR_DB__DUMMY_MASK__SI 0x00010000L -#define MC_WR_DB__ENABLE_MASK 0x00000001L -#define MC_WR_DB__LAZY_TIMER_MASK 0x00007800L -#define MC_WR_DB__MAX_BURST_MASK 0x00000780L -#define MC_WR_DB__PRESCALE_MASK 0x00000006L -#define MC_WR_DB__STALL_MODE_MASK 0x00000030L -#define MC_WR_DB__STALL_OVERRIDE_MASK 0x00000040L -#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_WR_GRP_EXT__DBSTEN0_MASK 0x0000000fL -#define MC_WR_GRP_EXT__TC0_MASK 0x000000f0L -#define MC_WR_GRP_GFX__ACPG_MASK__CI__VI 0x00000f00L -#define MC_WR_GRP_GFX__ACPO_MASK__CI__VI 0x0000f000L -#define MC_WR_GRP_GFX__CP_MASK 0x0000000fL -#define MC_WR_GRP_GFX__SH0_MASK__SI 0x000000f0L -#define MC_WR_GRP_GFX__SH1_MASK__SI 0x00000f00L -#define MC_WR_GRP_GFX__SH_MASK__CI__VI 0x000000f0L -#define MC_WR_GRP_GFX__XDMAM_MASK__CI 0x00f00000L -#define MC_WR_GRP_GFX__XDMAM_MASK__SI 0x000f0000L -#define MC_WR_GRP_GFX__XDMA_MASK__CI 0x000f0000L -#define MC_WR_GRP_GFX__XDMA_MASK__SI 0x0000f000L -#define MC_WR_GRP_LCL__BCAST0_MASK__SI 0x0f000000L -#define MC_WR_GRP_LCL__CB0_MASK 0x0000000fL -#define MC_WR_GRP_LCL__CBCMASK0_MASK 0x000000f0L -#define MC_WR_GRP_LCL__CBFMASK0_MASK 0x00000f00L -#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000L -#define MC_WR_GRP_LCL__DB0_MASK 0x0000f000L -#define MC_WR_GRP_LCL__DBHTILE0_MASK 0x000f0000L -#define MC_WR_GRP_LCL__SX0_MASK 0x00f00000L -#define MC_WR_GRP_OTH__DRMDMA0_MASK__SI 0x000000f0L -#define MC_WR_GRP_OTH__HDP_MASK 0x00000f00L -#define MC_WR_GRP_OTH__SDMA0_MASK__CI__VI 0x000000f0L -#define MC_WR_GRP_OTH__SEM_MASK 0x0000f000L -#define MC_WR_GRP_OTH__UMC_MASK 0x000f0000L -#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0x0000000fL -#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000L -#define MC_WR_GRP_OTH__UVD_MASK 0x00f00000L -#define MC_WR_GRP_OTH__XDP_MASK 0x0f000000L -#define MC_WR_GRP_SYS__DRMDMA1_MASK__SI 0x000f0000L -#define MC_WR_GRP_SYS__IH_MASK 0x0000000fL -#define MC_WR_GRP_SYS__MCIF_MASK 0x000000f0L -#define MC_WR_GRP_SYS__RLC_MASK 0x00000f00L -#define MC_WR_GRP_SYS__SAM_MASK__CI 0x0000f000L -#define MC_WR_GRP_SYS__SDMA1_MASK__CI__VI 0x00f00000L -#define MC_WR_GRP_SYS__SMU_MASK__CI__VI 0x000f0000L -#define MC_WR_GRP_SYS__SMU_MASK__SI 0x00f00000L -#define MC_WR_GRP_SYS__SPU_MASK__SI 0x0000f000L -#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000L -#define MC_WR_GRP_SYS__VCE_MASK 0x0f000000L -#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_WR_HUB__DUMMY_MASK__SI 0x00010000L -#define MC_WR_HUB__ENABLE_MASK 0x00000001L -#define MC_WR_HUB__LAZY_TIMER_MASK 0x00007800L -#define MC_WR_HUB__MAX_BURST_MASK 0x00000780L -#define MC_WR_HUB__PRESCALE_MASK 0x00000006L -#define MC_WR_HUB__STALL_MODE_MASK 0x00000030L -#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x00000040L -#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_WR_TC0__DUMMY_MASK__SI 0x00010000L -#define MC_WR_TC0__ENABLE_MASK 0x00000001L -#define MC_WR_TC0__LAZY_TIMER_MASK 0x00007800L -#define MC_WR_TC0__MAX_BURST_MASK 0x00000780L -#define MC_WR_TC0__PRESCALE_MASK 0x00000006L -#define MC_WR_TC0__STALL_MODE_MASK 0x00000030L -#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x00000040L -#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L -#define MC_WR_TC1__DUMMY_MASK__SI 0x00010000L -#define MC_WR_TC1__ENABLE_MASK 0x00000001L -#define MC_WR_TC1__LAZY_TIMER_MASK 0x00007800L -#define MC_WR_TC1__MAX_BURST_MASK 0x00000780L -#define MC_WR_TC1__PRESCALE_MASK 0x00000006L -#define MC_WR_TC1__STALL_MODE_MASK 0x00000030L -#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x00000040L -#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L -#define MC_XBAR_ADDR_DEC__GECC_MASK 0x00000002L -#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x00000001L -#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x00000008L -#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x00000004L -#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0x0000000fL -#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0x000000f0L -#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0x00000f00L -#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0x0000f000L -#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0x000f0000L -#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0x00f00000L -#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0x0f000000L -#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000L -#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x00000004L -#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x00000002L -#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x00000001L -#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x00000003L -#define MC_XBAR_CHTRIREMAP__CH1_MASK 0x0000000cL -#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x00000030L -#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK__SI__CI 0x10000000L -#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK__SI__CI 0x03000000L -#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK__SI__CI 0x00000fffL -#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK__SI__CI 0x0c000000L -#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK__SI__CI 0x00fff000L -#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK__SI__CI 0x0000ff00L -#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK__SI__CI 0x00ff0000L -#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK__SI__CI 0x000000ffL -#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK__SI__CI 0x000000ffL -#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK__SI__CI 0x0000ff00L -#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK__SI__CI 0x00ff0000L -#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK__SI__CI 0xff000000L -#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK__SI__CI 0x000000ffL -#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK__SI__CI 0x0000ff00L -#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK__SI__CI 0x00ff0000L -#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK__SI__CI 0xff000000L -#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK__SI__CI 0xffffffffL -#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK__SI__CI 0xffffffffL -#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK__SI__CI 0xffffffffL -#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK__SI__CI 0xffffffffL -#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0x000000ffL -#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0x0000ff00L -#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0x00ff0000L -#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000L -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0x000000ffL -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0x0000ff00L -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0x00ff0000L -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000L -#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0x000000ffL -#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0x0000ff00L -#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0x00ff0000L -#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000L -#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0x00ff0000L -#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0x000000ffL -#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0x0000ff00L -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0x000000ffL -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0x0000ff00L -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0x00ff0000L -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000L -#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0x000000ffL -#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0x0000ff00L -#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x00000002L -#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x00000001L -#define MC_XBAR_SPARE0__BIT_MASK 0xffffffffL -#define MC_XBAR_SPARE1__BIT_MASK 0xffffffffL -#define MC_XBAR_TWOCHAN__CH0_MASK 0x00000006L -#define MC_XBAR_TWOCHAN__CH1_MASK 0x00000018L -#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x00000001L -#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0x000000ffL -#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0x0000ff00L -#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0x00ff0000L -#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000L -#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0x000000ffL -#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0x0000ff00L -#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0x00ff0000L -#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000L -#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0x000000ffL -#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0x0000ff00L -#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x00003c00L -#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x00000070L -#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x00000380L -#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x0003c000L -#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0x0000000fL -#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0x000000ffL -#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x01fe0000L -#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0x0000ff00L -#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x00010000L -#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x02000000L -#define MC_XPB_CLG_EXTRA__CMP0_MASK 0x000000ffL -#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x01fe0000L -#define MC_XPB_CLG_EXTRA__MSK0_MASK 0x0000ff00L -#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x00010000L -#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x02000000L -#define MC_XPB_CLK_GAT__ENABLE_MASK 0x00040000L -#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L -#define MC_XPB_CLK_GAT__OFFDLY_MASK 0x00000fc0L -#define MC_XPB_CLK_GAT__ONDLY_MASK 0x0000003fL -#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x0003f000L -#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000ffL -#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L -#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L -#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L -#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L -#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000ff00L -#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000ffL -#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L -#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L -#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007f0000L -#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L -#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L -#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L -#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L -#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L -#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L -#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07f80000L -#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000ffL -#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007f00L -#define MC_XPB_LB_ADDR__CMP0_MASK 0x000003ffL -#define MC_XPB_LB_ADDR__CMP1_MASK 0x03f00000L -#define MC_XPB_LB_ADDR__MASK0_MASK 0x000ffc00L -#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000L -#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000ffffL -#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0x000000ffL -#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0x0000ff00L -#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0x00ff0000L -#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000L -#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L -#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR0__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR1__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR2__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR3__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR4__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR5__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR6__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000fL -#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000f0L -#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR7__VALID_MASK 0x00001000L -#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000fL -#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L -#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L -#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L -#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L -#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L -#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L -#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L -#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L -#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0x00000f00L -#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0x0000f000L -#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0x000000ffL -#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0fffff00L -#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000ffL -#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0fffff00L -#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000ffL -#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000L -#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L -#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000f00L -#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L -#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0x000000ffL -#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L -#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L -#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L -#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x07fffffcL -#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x00000002L -#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L -#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003fL -#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000fc0L -#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003f000L -#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L -#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L -#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000feL -#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L -#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L -#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L -#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L -#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007f00L -#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L -#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L -#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L -#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L -#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000L -#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L -#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L -#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffffL -#define MC_XPB_STICKY__BITS_MASK 0xffffffffL -#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L -#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L -#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L -#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L -#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L -#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L -#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L -#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L -#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L -#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L -#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L -#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L -#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L -#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L -#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L -#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L -#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L -#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L -#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L -#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L -#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x0000003fL -#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0x00000fc0L -#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x0003f000L -#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x0000003fL -#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0x00000fc0L -#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x0003f000L -#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x00030000L -#define MC_XPB_WCB_CFG__SID_MAX_MASK 0x000c0000L -#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0x0000ffffL -#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0x0000ffffL -#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007f0000L -#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000L -#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL -#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L -#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL -#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L -#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL -#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L -#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL -#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L -#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L -#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L -#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L -#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L -#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL -#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L -#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L -#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL -#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL -#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK__CI__VI 0x00000001L -#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK__SI 0x00100000L -#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK__SI 0x0000007fL -#define MICROSECOND_TIME_BASE_DIV__PPLL_REFCLK_SEL_MASK__SI 0x01000000L -#define MICROSECOND_TIME_BASE_DIV__PPLL_REFCLK_SOFT_RESET_MASK__SI 0x10000000L -#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK__SI 0x00020000L -#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK__SI 0x00007f00L -#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK__SI 0x00010000L -#define MINOR_VERSION__MINOR_VERSION_MASK__SI 0x000000ffL -#define MIN_GRANT__MIN_GNT_MASK 0x000000ffL -#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK__CI__VI 0x000000ffL -#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK__CI__VI 0x00ff0000L -#define MISC_CLK_CTRL__ZCLK_SEL_MASK__CI__VI 0x0000ff00L -#define MLPS0_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT_MASK__CI__VI 0x00008000L -#define MLPS0_DEBUG_BUS_SIGNALS__INT_OSC_CLK_MASK__CI__VI 0x00000040L -#define MLPS0_DEBUG_BUS_SIGNALS__RES_OUT_MASK__CI__VI 0x0000001fL -#define MLPS0_DEBUG_BUS_SIGNALS__SPARE_MASK__CI__VI 0x00007f80L -#define MLPS0_DEBUG_BUS_SIGNALS__STRAP_OUTA_MASK__CI__VI 0x001f0000L -#define MLPS0_DEBUG_BUS_SIGNALS__STRAP_OUTB_MASK__CI__VI 0x03e00000L -#define MLPS0_DEBUG_BUS_SIGNALS__STRAP_OUTC_MASK__CI__VI 0x7c000000L -#define MLPS0_DEBUG_BUS_SIGNALS__Y_MASK__CI__VI 0x00000020L -#define MLPS1_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT_MASK__CI__VI 0x00008000L -#define MLPS1_DEBUG_BUS_SIGNALS__INT_OSC_CLK_MASK__CI__VI 0x00000040L -#define MLPS1_DEBUG_BUS_SIGNALS__RES_OUT_MASK__CI__VI 0x0000001fL -#define MLPS1_DEBUG_BUS_SIGNALS__SPARE_MASK__CI__VI 0x00007f80L -#define MLPS1_DEBUG_BUS_SIGNALS__STRAP_OUTA_MASK__CI__VI 0x001f0000L -#define MLPS1_DEBUG_BUS_SIGNALS__STRAP_OUTB_MASK__CI__VI 0x03e00000L -#define MLPS1_DEBUG_BUS_SIGNALS__STRAP_OUTC_MASK__CI__VI 0x7c000000L -#define MLPS1_DEBUG_BUS_SIGNALS__Y_MASK__CI__VI 0x00000020L -#define MLPS2_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT_MASK__CI__VI 0x00008000L -#define MLPS2_DEBUG_BUS_SIGNALS__INT_OSC_CLK_MASK__CI__VI 0x00000040L -#define MLPS2_DEBUG_BUS_SIGNALS__RES_OUT_MASK__CI__VI 0x0000001fL -#define MLPS2_DEBUG_BUS_SIGNALS__SPARE_MASK__CI__VI 0x00007f80L -#define MLPS2_DEBUG_BUS_SIGNALS__STRAP_OUTA_MASK__CI__VI 0x001f0000L -#define MLPS2_DEBUG_BUS_SIGNALS__STRAP_OUTB_MASK__CI__VI 0x03e00000L -#define MLPS2_DEBUG_BUS_SIGNALS__STRAP_OUTC_MASK__CI__VI 0x7c000000L -#define MLPS2_DEBUG_BUS_SIGNALS__Y_MASK__CI__VI 0x00000020L -#define MLPS3_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT_MASK__CI__VI 0x00008000L -#define MLPS3_DEBUG_BUS_SIGNALS__INT_OSC_CLK_MASK__CI__VI 0x00000040L -#define MLPS3_DEBUG_BUS_SIGNALS__RES_OUT_MASK__CI__VI 0x0000001fL -#define MLPS3_DEBUG_BUS_SIGNALS__SPARE_MASK__CI__VI 0x00007f80L -#define MLPS3_DEBUG_BUS_SIGNALS__STRAP_OUTA_MASK__CI__VI 0x001f0000L -#define MLPS3_DEBUG_BUS_SIGNALS__STRAP_OUTB_MASK__CI__VI 0x03e00000L -#define MLPS3_DEBUG_BUS_SIGNALS__STRAP_OUTC_MASK__CI__VI 0x7c000000L -#define MLPS3_DEBUG_BUS_SIGNALS__Y_MASK__CI__VI 0x00000020L -#define MLPSPAD_PINSTRAPS__MLPS_EFUSE_RD_DISABLE_MASK__CI 0x00002000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_0_MASK__CI__VI 0x00000001L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_10_MASK__CI__VI 0x00000400L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_11_MASK__CI__VI 0x00000800L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_12_MASK__CI__VI 0x00001000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_14_MASK__CI__VI 0x00004000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_16_MASK__CI__VI 0x00010000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_17_MASK__CI__VI 0x00020000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_18_MASK__CI__VI 0x00040000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_19_MASK__CI__VI 0x00080000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_1_MASK__CI__VI 0x00000002L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_20_MASK__CI__VI 0x00100000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_21_MASK__CI__VI 0x00200000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_22_MASK__CI__VI 0x00400000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_23_MASK__CI__VI 0x00800000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_24_MASK__CI__VI 0x01000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_25_MASK__CI__VI 0x02000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_26_MASK__CI__VI 0x04000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_27_MASK__CI__VI 0x08000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_28_MASK__CI__VI 0x10000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_29_MASK__CI__VI 0x20000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_2_MASK__CI__VI 0x00000004L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_30_MASK__CI__VI 0x40000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_31_MASK__CI__VI 0x80000000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_3_MASK__CI__VI 0x00000008L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_4_MASK__CI__VI 0x00000010L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_5_MASK__CI__VI 0x00000020L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_6_MASK__CI__VI 0x00000040L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_7_MASK__CI__VI 0x00000080L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_8_MASK__CI__VI 0x00000100L -#define MLPSPAD_PINSTRAPS__MLPS_ROM_EXIST_MASK__CI 0x00008000L -#define MLPSPAD_PINSTRAPS__MLPS_ROM_REPAIR_MASK__CI 0x00000200L -#define MLPS_CNTL__ADC_ENB_MASK__CI__VI 0x00000001L -#define MLPS_CNTL__DIFF_REC_EN_MASK__CI__VI 0x00000002L -#define MLPS_CNTL__SPARE_MASK__CI__VI 0x000007f8L -#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L -#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x00000008L -#define MM_DATA__MM_DATA_MASK 0xffffffffL -#define MM_INDEX_HI__MM_OFFSET_HI_MASK__CI__VI 0xffffffffL -#define MM_INDEX__MM_APER_MASK 0x80000000L -#define MM_INDEX__MM_OFFSET_MASK 0x7fffffffL -#define MPLL_AD_FUNC_CNTL__SPARE_MASK__SI__CI 0xfffffff8L -#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK__SI__CI 0x00000007L -#define MPLL_AD_STATUS__FREQ_LOCK_MASK__SI__CI 0x00040000L -#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK__SI__CI 0x00080000L -#define MPLL_AD_STATUS__OINT_RESET_MASK__SI__CI 0x00020000L -#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK__SI__CI 0x00000070L -#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK__SI__CI 0x0001ff80L -#define MPLL_AD_STATUS__VCTRLADC_MASK__SI__CI 0x00000007L -#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0x0000ff00L -#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK__SI__CI 0x00600000L -#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK__SI__CI 0x00100000L -#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK__SI__CI 0x00020000L -#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK__SI__CI 0x80000000L -#define MPLL_CNTL_MODE__INSTR_DELAY_MASK__SI__CI 0x000000ffL -#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK__SI__CI 0x00010000L -#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK__SI__CI 0x00004000L -#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK__SI__CI 0x00000800L -#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK__SI__CI 0x00000100L -#define MPLL_CNTL_MODE__QDR_MASK__SI__CI 0x00002000L -#define MPLL_CNTL_MODE__SPARE_1_MASK__SI__CI 0x00001000L -#define MPLL_CNTL_MODE__SPARE_2_MASK__SI__CI 0x00800000L -#define MPLL_CNTL_MODE__SPARE_3_MASK__SI__CI 0x70000000L -#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK__SI__CI 0x04000000L -#define MPLL_CNTL_MODE__SS_SSEN_MASK__SI__CI 0x03000000L -#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK__SI__CI 0x08000000L -#define MPLL_CONTROL__AD_BG_PWRON_MASK__SI__CI 0x00001000L -#define MPLL_CONTROL__AD_PLL_PWRON_MASK__SI__CI 0x00002000L -#define MPLL_CONTROL__AD_PLL_RESET_MASK__SI__CI 0x00004000L -#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK__SI__CI 0x00010000L -#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK__SI__CI 0x00020000L -#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK__SI__CI 0x00040000L -#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK__SI__CI 0x00100000L -#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK__SI__CI 0x00200000L -#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK__SI__CI 0x00400000L -#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK__SI__CI 0x01000000L -#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK__SI__CI 0x02000000L -#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK__SI__CI 0x04000000L -#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK__SI__CI 0x10000000L -#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK__SI__CI 0x20000000L -#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK__SI__CI 0x40000000L -#define MPLL_CONTROL__GDDR_PWRON_MASK__SI__CI 0x00000001L -#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK__SI__CI 0x00000004L -#define MPLL_CONTROL__REFCLK_PWRON_MASK__SI__CI 0x00000002L -#define MPLL_CONTROL__SPARE_AD_0_MASK__SI__CI 0x00008000L -#define MPLL_CONTROL__SPARE_DQ_0_0_MASK__SI__CI 0x00080000L -#define MPLL_CONTROL__SPARE_DQ_0_1_MASK__SI__CI 0x00800000L -#define MPLL_CONTROL__SPARE_DQ_1_0_MASK__SI__CI 0x08000000L -#define MPLL_CONTROL__SPARE_DQ_1_1_MASK__SI__CI 0x80000000L -#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK__SI__CI 0x00040000L -#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK__SI__CI 0x00080000L -#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK__SI__CI 0x00020000L -#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK__SI__CI 0x00000070L -#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK__SI__CI 0x0001ff80L -#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK__SI__CI 0x00000007L -#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK__SI__CI 0x00040000L -#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK__SI__CI 0x00080000L -#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK__SI__CI 0x00020000L -#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK__SI__CI 0x00000070L -#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK__SI__CI 0x0001ff80L -#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK__SI__CI 0x00000007L -#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK__SI__CI 0x00040000L -#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK__SI__CI 0x00080000L -#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK__SI__CI 0x00020000L -#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK__SI__CI 0x00000070L -#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK__SI__CI 0x0001ff80L -#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK__SI__CI 0x00000007L -#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK__SI__CI 0x00040000L -#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK__SI__CI 0x00080000L -#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK__SI__CI 0x00020000L -#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK__SI__CI 0x00000070L -#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK__SI__CI 0x0001ff80L -#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK__SI__CI 0x00000007L -#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK__SI__CI 0x00000008L -#define MPLL_DQ_FUNC_CNTL__SPARE_MASK__SI__CI 0xffffffe0L -#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK__SI__CI 0x00000007L -#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK__SI__CI 0x00000010L -#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK__SI__CI 0x0000fff0L -#define MPLL_FUNC_CNTL_1__CLKF_MASK__SI__CI 0x0fff0000L -#define MPLL_FUNC_CNTL_1__SPARE_0_MASK__SI__CI 0x0000000cL -#define MPLL_FUNC_CNTL_1__SPARE_1_MASK__SI__CI 0xf0000000L -#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK__SI__CI 0x00000003L -#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK__SI__CI 0x000e0000L -#define MPLL_FUNC_CNTL_2__BACKUP_MASK__SI__CI 0xf8000000L -#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK__CI 0x00010000L -#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK__SI__CI 0x07f00000L -#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK__SI__CI 0x00000080L -#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK__SI__CI 0x00003000L -#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK__CI 0x00008000L -#define MPLL_FUNC_CNTL_2__RESET_EN_MASK__SI__CI 0x00000004L -#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK__SI__CI 0x00000c00L -#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK__CI 0x00004000L -#define MPLL_FUNC_CNTL_2__SPARE_0_MASK__SI 0x0001c000L -#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK__SI__CI 0x00000008L -#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK__SI__CI 0x00000010L -#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK__SI__CI 0x00000040L -#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK__SI__CI 0x00000020L -#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK__SI__CI 0x00000200L -#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK__SI__CI 0x00000100L -#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK__SI__CI 0x00000002L -#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK__SI__CI 0x00000001L -#define MPLL_FUNC_CNTL__BG_100ADJ_MASK__SI__CI 0x00000f00L -#define MPLL_FUNC_CNTL__BG_135ADJ_MASK__SI__CI 0x000f0000L -#define MPLL_FUNC_CNTL__BWCTRL_MASK__SI__CI 0x0ff00000L -#define MPLL_FUNC_CNTL__REG_BIAS_MASK__SI__CI 0xc0000000L -#define MPLL_FUNC_CNTL__SPARE_0_MASK__SI__CI 0x00000020L -#define MPLL_SEQ_UCODE_1__INSTR0_MASK__SI__CI 0x0000000fL -#define MPLL_SEQ_UCODE_1__INSTR1_MASK__SI__CI 0x000000f0L -#define MPLL_SEQ_UCODE_1__INSTR2_MASK__SI__CI 0x00000f00L -#define MPLL_SEQ_UCODE_1__INSTR3_MASK__SI__CI 0x0000f000L -#define MPLL_SEQ_UCODE_1__INSTR4_MASK__SI__CI 0x000f0000L -#define MPLL_SEQ_UCODE_1__INSTR5_MASK__SI__CI 0x00f00000L -#define MPLL_SEQ_UCODE_1__INSTR6_MASK__SI__CI 0x0f000000L -#define MPLL_SEQ_UCODE_1__INSTR7_MASK__SI__CI 0xf0000000L -#define MPLL_SEQ_UCODE_2__INSTR10_MASK__SI__CI 0x00000f00L -#define MPLL_SEQ_UCODE_2__INSTR11_MASK__SI__CI 0x0000f000L -#define MPLL_SEQ_UCODE_2__INSTR12_MASK__SI__CI 0x000f0000L -#define MPLL_SEQ_UCODE_2__INSTR13_MASK__SI__CI 0x00f00000L -#define MPLL_SEQ_UCODE_2__INSTR14_MASK__SI__CI 0x0f000000L -#define MPLL_SEQ_UCODE_2__INSTR15_MASK__SI__CI 0xf0000000L -#define MPLL_SEQ_UCODE_2__INSTR8_MASK__SI__CI 0x0000000fL -#define MPLL_SEQ_UCODE_2__INSTR9_MASK__SI__CI 0x000000f0L -#define MPLL_SS1__CLKV_MASK__SI__CI 0x03ffffffL -#define MPLL_SS1__SPARE_MASK__SI__CI 0xfc000000L -#define MPLL_SS2__CLKS_MASK__SI__CI 0x00000fffL -#define MPLL_SS2__SPARE_MASK__SI__CI 0xfffff000L -#define MPLL_TIME__MPLL_LOCK_TIME_MASK__SI__CI 0x0000ffffL -#define MPLL_TIME__MPLL_RESET_TIME_MASK__SI__CI 0xffff0000L -#define MPRD_BUF_SIZE__HEIGHT_MASK__SI 0x0fff0000L -#define MPRD_BUF_SIZE__PITCH_MASK__SI 0x00000fffL -#define MPRD_BUF_WIDTH__WIDTH_MASK__SI 0x00000fffL -#define MPRD_BYPASS_PITCH__INTRA_SURFACE_PITCH_MASK__SI 0x00001fffL -#define MPRD_BYPASS_PITCH__NON_INTRA_SURFACE_PITCH_MASK__SI 0x1fff0000L -#define MPRD_CNTRL__ADDR_MODE_MASK__SI 0x00000004L -#define MPRD_CNTRL__BYPASS_SWAP_UV_MASK__SI 0x00000008L -#define MPRD_CNTRL__DROP_REF_BUF_WRITES_DIS_MASK__SI 0x00000800L -#define MPRD_CNTRL__DROP_REF_BUF_WRITES_MASK__SI 0x00000400L -#define MPRD_CNTRL__IDCT_OVERFLOW_DISCARD_DIS_MASK__SI 0x00000010L -#define MPRD_CNTRL__MPRD_DBW_ADDR_MODE_MASK__SI 0x00000380L -#define MPRD_CNTRL__MPRD_DBW_EN_MASK__SI 0x00000020L -#define MPRD_CNTRL__MPRD_DBW_FIELD_FORMAT_MASK__SI 0x00000040L -#define MPRD_CNTRL__OP_MODE_MASK__SI 0x00000003L -#define MPRD_CNTRL__WRITE_CLEAN_TIMER_MASK__SI 0x0003e000L -#define MPRD_CNTRL__WRPATH_MEM_PTR_RESET_MASK__SI 0x00001000L -#define MPRD_DBW_BUF_SIZE__DBW_HEIGHT_MASK__SI 0x0fff0000L -#define MPRD_DBW_BUF_SIZE__DBW_PITCH_MASK__SI 0x00000fffL -#define MPRD_HW_DEBUG__MPRD_HW_DEBUG_MASK__SI 0xffffffffL -#define MPRD_OUTOFRANGE_PIXELS__CHROMA_PIXELS_MASK__SI 0x0000ff00L -#define MPRD_OUTOFRANGE_PIXELS__LUMA_PIXELS_MASK__SI 0x000000ffL -#define MPRD_STATUS__IDCT_MB_OUT_OF_SYNC_MASK__SI 0x00000004L -#define MPRD_STATUS__IDCT_OVERFLOW_ERROR_MASK__SI 0x00000010L -#define MPRD_STATUS__IDCT_PEL_OUT_OF_SYNC_MASK__SI 0x00000008L -#define MPRD_STATUS__IDCT_PIO_MODE_DONE_MASK__SI 0x00000020L -#define MPRD_STATUS__MPRD_BUSY_MASK__SI 0x00000001L -#define MPRD_STATUS__VCPU_COMMAND_ERROR_MASK__SI 0x00000002L -#define MP_BUF_MAP__BUF_MAP_MASK__SI 0xffffffffL -#define MP_BUF_NUM__BUF_NUM_MASK__SI 0x0000001fL -#define MP_BUF_SIZE__HEIGHT_MASK__SI 0x0ff00000L -#define MP_BUF_SIZE__PITCH_MASK__SI 0x00000ff0L -#define MP_CACHE_CTRL__BYPASS_MASK__SI 0x00000001L -#define MP_CACHE_CTRL__COUNTER_SELECT_MASK__SI 0x00000038L -#define MP_CACHE_CTRL__ENABLE_COUNT_MASK__SI 0x00000002L -#define MP_CACHE_CTRL__READ_COUNTER_MASK__SI 0x00000004L -#define MP_CACHE_PERF_COUNTER__PERF_COUNTER_MASK__SI 0xffffffffL -#define MP_CACHE_SRAM_RM_CTL__MP_M024X216R2M01S00_RME_MASK__SI 0x00000200L -#define MP_CACHE_SRAM_RM_CTL__MP_M024X216R2M01S00_RM_MASK__SI 0x000001e0L -#define MP_CACHE_SRAM_RM_CTL__MP_M128X075R2M01S00_RME_MASK__SI 0x20000000L -#define MP_CACHE_SRAM_RM_CTL__MP_M128X075R2M01S00_RM_MASK__SI 0x1e000000L -#define MP_CACHE_SRAM_RM_CTL__MP_M144X020R2M04S00_RME_MASK__SI 0x00080000L -#define MP_CACHE_SRAM_RM_CTL__MP_M144X020R2M04S00_RM_MASK__SI 0x00078000L -#define MP_CACHE_SRAM_RM_CTL__MP_M192X033R2M02S00_RME_MASK__SI 0x00004000L -#define MP_CACHE_SRAM_RM_CTL__MP_M192X033R2M02S00_RM_MASK__SI 0x00003c00L -#define MP_CACHE_SRAM_RM_CTL__MP_M192X068R2M02S00_RME_MASK__SI 0x01000000L -#define MP_CACHE_SRAM_RM_CTL__MP_M192X068R2M02S00_RM_MASK__SI 0x00f00000L -#define MP_CACHE_SRAM_RM_CTL__MP_M768X128H1M04S00_RME_MASK__SI 0x00000010L -#define MP_CACHE_SRAM_RM_CTL__MP_M768X128H1M04S00_RM_MASK__SI 0x0000000fL -#define MP_CF_DAT__DAT_MASK__SI 0xffffffffL -#define MP_COL_INFO__CODED_FRAME_MASK__SI 0x00000004L -#define MP_COL_INFO__LONG_TERM_MASK__SI 0x00000008L -#define MP_COL_INFO__MBAFF_FRAME_FLAG_MASK__SI 0x00000010L -#define MP_COL_INFO__STRUCTURE_MASK__SI 0x00000003L -#define MP_COL_PIC_BOTTOM__POC_MASK__SI 0x0000ffffL -#define MP_COL_PIC_TOP__POC_MASK__SI 0x0000ffffL -#define MP_CTL__CTXT_FMT_MASK__SI 0x000000c0L -#define MP_CTL__FULL_PEL_FILT_MASK__SI 0x00000100L -#define MP_CTL__NSG_MODE_MASK__SI 0x00000030L -#define MP_CTL__STANDARD_MASK__SI 0x0000000fL -#define MP_CTL__SW_MRST_MASK__SI 0x40000000L -#define MP_CTL__SW_RRST_MASK__SI 0x20000000L -#define MP_CTL__SW_SRST_MASK__SI 0x80000000L -#define MP_CTL__TILE_FMT_MASK__SI 0x00001000L -#define MP_CTL__TIMEOUT_TIME_MASK__SI 0x0ff00000L -#define MP_CTL__TRCK_MODE_MASK__SI 0x00000200L -#define MP_CTL__UV_FMT_MASK__SI 0x00002000L -#define MP_CURR_PIC_BOTTOM__POC_MASK__SI 0x0000ffffL -#define MP_CURR_PIC_TOP__POC_MASK__SI 0x0000ffffL -#define MP_DEBUG_INT_STAT__CFIFO_LESS_ERROR_MASK__SI 0x00000010L -#define MP_DEBUG_INT_STAT__CFIFO_MORE_ERROR_MASK__SI 0x00000008L -#define MP_DEBUG_INT_STAT__CTXT_READ_TIMEOUT_MASK__SI 0x00080000L -#define MP_DEBUG_INT_STAT__CTXT_WRITE_TIMEOUT_MASK__SI 0x00100000L -#define MP_DEBUG_INT_STAT__DONE_MASK__SI 0x00000001L -#define MP_DEBUG_INT_STAT__DPB_ILLEGAL_ENTRY_MASK__SI 0x00000040L -#define MP_DEBUG_INT_STAT__MC_FIFO_OVF_MASK__SI 0x00200000L -#define MP_DEBUG_INT_STAT__NON_CONFORMANT_ERROR_MASK__SI 0x00000100L -#define MP_DEBUG_INT_STAT__PEL_COORD_FIFO_OVF_MASK__SI 0x00800000L -#define MP_DEBUG_INT_STAT__PEL_COORD_FIFO_UDF_MASK__SI 0x00400000L -#define MP_DEBUG_INT_STAT__POC_ILLEGAL_ENTRY_MASK__SI 0x00000020L -#define MP_DEBUG_INT_STAT__REF_PEL_FIFO_OVF_MASK__SI 0x00000004L -#define MP_DEBUG_INT_STAT__TEMPORAL_ERR_MASK__SI 0x00000002L -#define MP_DEBUG_INT_STAT__VC1_ERR_DMV_TIMEOUT_MASK__SI 0x00010000L -#define MP_DEBUG_INT_STAT__VC1_ERR_MB4MV_BFRAME_MASK__SI 0x00000800L -#define MP_DEBUG_INT_STAT__VC1_ERR_MB4MV_MASK__SI 0x00001000L -#define MP_DEBUG_INT_STAT__VC1_ERR_MBFLAG_MASK__SI 0x00004000L -#define MP_DEBUG_INT_STAT__VC1_ERR_MBX_MASK__SI 0x00000200L -#define MP_DEBUG_INT_STAT__VC1_ERR_MBY_MASK__SI 0x00000400L -#define MP_DEBUG_INT_STAT__VC1_ERR_MVSW_MASK__SI 0x00008000L -#define MP_DEBUG_INT_STAT__VC1_ERR_NO_HYBRID_MASK__SI 0x00020000L -#define MP_DEBUG_INT_STAT__VC1_ERR_PFRAME_MBDIR_MASK__SI 0x00002000L -#define MP_DEBUG_INT_STAT__VC1_ERR_PRED_RANGE_MASK__SI 0x00040000L -#define MP_DEBUG_INT_STAT__WGT_ILLEGAL_ENTRY_MASK__SI 0x00000080L -#define MP_HW_DEBUG__DAT_MASK__SI 0xffffffffL -#define MP_INT_EN__CFIFO_LESS_ERROR_EN_MASK__SI 0x00000010L -#define MP_INT_EN__CFIFO_MORE_ERROR_EN_MASK__SI 0x00000008L -#define MP_INT_EN__CTXT_READ_TIMEOUT_EN_MASK__SI 0x00080000L -#define MP_INT_EN__CTXT_WRITE_TIMEOUT_EN_MASK__SI 0x00100000L -#define MP_INT_EN__DONE_EN_MASK__SI 0x00000001L -#define MP_INT_EN__DPB_ILLEGAL_ENTRY_EN_MASK__SI 0x00000040L -#define MP_INT_EN__MC_FIFO_OVF_EN_MASK__SI 0x00200000L -#define MP_INT_EN__NON_CONFORMANT_ERROR_EN_MASK__SI 0x00000100L -#define MP_INT_EN__PEL_COORD_FIFO_OVF_EN_MASK__SI 0x00800000L -#define MP_INT_EN__PEL_COORD_FIFO_UDF_EN_MASK__SI 0x00400000L -#define MP_INT_EN__POC_ILLEGAL_ENTRY_EN_MASK__SI 0x00000020L -#define MP_INT_EN__REF_PEL_FIFO_OVF_EN_MASK__SI 0x00000004L -#define MP_INT_EN__TEMPORAL_ERR_EN_MASK__SI 0x00000002L -#define MP_INT_EN__VC1_ERR_DMV_TIMEOUT_EN_MASK__SI 0x00010000L -#define MP_INT_EN__VC1_ERR_MB4MV_BFRAME_EN_MASK__SI 0x00000800L -#define MP_INT_EN__VC1_ERR_MB4MV_EN_MASK__SI 0x00001000L -#define MP_INT_EN__VC1_ERR_MBFLAG_EN_MASK__SI 0x00004000L -#define MP_INT_EN__VC1_ERR_MBX_EN_MASK__SI 0x00000200L -#define MP_INT_EN__VC1_ERR_MBY_EN_MASK__SI 0x00000400L -#define MP_INT_EN__VC1_ERR_MVSW_EN_MASK__SI 0x00008000L -#define MP_INT_EN__VC1_ERR_NO_HYBRID_EN_MASK__SI 0x00020000L -#define MP_INT_EN__VC1_ERR_PFRAME_MBDIR_EN_MASK__SI 0x00002000L -#define MP_INT_EN__VC1_ERR_PRED_RANGE_EN_MASK__SI 0x00040000L -#define MP_INT_EN__WGT_ILLEGAL_ENTRY_EN_MASK__SI 0x00000080L -#define MP_INT_STAT__CFIFO_LESS_ERROR_MASK__SI 0x00000010L -#define MP_INT_STAT__CFIFO_MORE_ERROR_MASK__SI 0x00000008L -#define MP_INT_STAT__CTXT_READ_TIMEOUT_MASK__SI 0x00080000L -#define MP_INT_STAT__CTXT_WRITE_TIMEOUT_MASK__SI 0x00100000L -#define MP_INT_STAT__DONE_MASK__SI 0x00000001L -#define MP_INT_STAT__DPB_ILLEGAL_ENTRY_MASK__SI 0x00000040L -#define MP_INT_STAT__MC_FIFO_OVF_MASK__SI 0x00200000L -#define MP_INT_STAT__NON_CONFORMANT_ERROR_MASK__SI 0x00000100L -#define MP_INT_STAT__PEL_COORD_FIFO_OVF_MASK__SI 0x00800000L -#define MP_INT_STAT__PEL_COORD_FIFO_UDF_MASK__SI 0x00400000L -#define MP_INT_STAT__POC_ILLEGAL_ENTRY_MASK__SI 0x00000020L -#define MP_INT_STAT__REF_PEL_FIFO_OVF_MASK__SI 0x00000004L -#define MP_INT_STAT__TEMPORAL_ERR_MASK__SI 0x00000002L -#define MP_INT_STAT__VC1_ERR_DMV_TIMEOUT_MASK__SI 0x00010000L -#define MP_INT_STAT__VC1_ERR_MB4MV_BFRAME_MASK__SI 0x00000800L -#define MP_INT_STAT__VC1_ERR_MB4MV_MASK__SI 0x00001000L -#define MP_INT_STAT__VC1_ERR_MBFLAG_MASK__SI 0x00004000L -#define MP_INT_STAT__VC1_ERR_MBX_MASK__SI 0x00000200L -#define MP_INT_STAT__VC1_ERR_MBY_MASK__SI 0x00000400L -#define MP_INT_STAT__VC1_ERR_MVSW_MASK__SI 0x00008000L -#define MP_INT_STAT__VC1_ERR_NO_HYBRID_MASK__SI 0x00020000L -#define MP_INT_STAT__VC1_ERR_PFRAME_MBDIR_MASK__SI 0x00002000L -#define MP_INT_STAT__VC1_ERR_PRED_RANGE_MASK__SI 0x00040000L -#define MP_INT_STAT__WGT_ILLEGAL_ENTRY_MASK__SI 0x00000080L -#define MP_LISTX0_0__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_0__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_0__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_0__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_0__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_0__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_10__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_10__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_10__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_10__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_10__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_10__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_11__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_11__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_11__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_11__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_11__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_11__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_12__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_12__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_12__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_12__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_12__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_12__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_13__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_13__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_13__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_13__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_13__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_13__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_14__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_14__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_14__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_14__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_14__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_14__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_15__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_15__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_15__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_15__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_15__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_15__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_1__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_1__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_1__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_1__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_1__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_1__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_2__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_2__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_2__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_2__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_2__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_2__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_3__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_3__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_3__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_3__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_3__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_3__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_4__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_4__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_4__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_4__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_4__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_4__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_5__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_5__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_5__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_5__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_5__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_5__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_6__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_6__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_6__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_6__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_6__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_6__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_7__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_7__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_7__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_7__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_7__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_7__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_8__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_8__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_8__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_8__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_8__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_8__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX0_9__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX0_9__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX0_9__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX0_9__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX0_9__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX0_9__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_0__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_0__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_0__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_0__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_0__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_0__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_10__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_10__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_10__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_10__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_10__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_10__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_11__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_11__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_11__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_11__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_11__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_11__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_12__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_12__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_12__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_12__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_12__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_12__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_13__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_13__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_13__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_13__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_13__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_13__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_14__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_14__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_14__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_14__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_14__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_14__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_15__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_15__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_15__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_15__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_15__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_15__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_1__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_1__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_1__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_1__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_1__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_1__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_2__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_2__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_2__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_2__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_2__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_2__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_3__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_3__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_3__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_3__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_3__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_3__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_4__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_4__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_4__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_4__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_4__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_4__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_5__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_5__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_5__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_5__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_5__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_5__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_6__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_6__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_6__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_6__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_6__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_6__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_7__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_7__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_7__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_7__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_7__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_7__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_8__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_8__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_8__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_8__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_8__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_8__STRUCTURE_MASK__SI 0x00000060L -#define MP_LISTX1_9__BUF_NUM2_MASK__SI 0x00001f00L -#define MP_LISTX1_9__BUF_NUM_MASK__SI 0x0000001fL -#define MP_LISTX1_9__LONG_TERM2_MASK__SI 0x00008000L -#define MP_LISTX1_9__LONG_TERM_MASK__SI 0x00000080L -#define MP_LISTX1_9__STRUCTURE2_MASK__SI 0x00006000L -#define MP_LISTX1_9__STRUCTURE_MASK__SI 0x00000060L -#define MP_LMA_ADR__ADR_MASK__SI 0x000000ffL -#define MP_LMA_CTL__ACCESS_MODE_MASK__SI 0x00000001L -#define MP_LMA_CTL__AUTO_INC_MASK__SI 0x00000040L -#define MP_LMA_CTL__MEMORY_SELECT_MASK__SI 0x0000003eL -#define MP_LMA_DAT__DAT_MASK__SI 0xffffffffL -#define MP_PPS_INFO__APPLY_WEIGHTS_MASK__SI 0x00000001L -#define MP_PPS_INFO__DIV_REF_IDX_MASK__SI 0x00000002L -#define MP_PPS_INFO__FIELD_PIC_FLAG_MASK__SI 0x00010000L -#define MP_PPS_INFO__NUM_REF_IDX_L0_ACTIVE_MASK__SI 0x000000fcL -#define MP_PPS_INFO__NUM_REF_IDX_L1_ACTIVE_MASK__SI 0x00003f00L -#define MP_PPS_INFO__RANGERED_UP_DOWN_MASK__SI 0x00060000L -#define MP_PPS_INFO__STRUCTURE_MASK__SI 0x0000c000L -#define MP_PPS_INFO__TRCK_MODE_VAL_MASK__SI 0x07f80000L -#define MP_SLICE_INFO__CHROMA_LOG2_WEIGHT_DENOM_MASK__SI 0x00000070L -#define MP_SLICE_INFO__DIRECT_SPATIAL_MV_PRED_FLAG_MASK__SI 0x00000200L -#define MP_SLICE_INFO__LUMA_LOG2_WEIGHT_DENOM_MASK__SI 0x0000000eL -#define MP_SLICE_INFO__MBAFF_FRAME_FLAG_MASK__SI 0x00000001L -#define MP_SLICE_INFO__WEIGHTED_BIPRED_IDC_MASK__SI 0x00000180L -#define MP_SPS_INFO__CHROMA_FORMAT_IDC_MASK__SI 0x10000000L -#define MP_SPS_INFO__DIRECT_8X8_INFERENCE_FLAG_MASK__SI 0x40000000L -#define MP_SPS_INFO__FRAME_MBS_ONLY_FLAG_MASK__SI 0x20000000L -#define MP_SPS_INFO__PIC_HEIGHT_MASK__SI 0x0fff0000L -#define MP_SPS_INFO__PIC_WIDTH_MASK__SI 0x00000fffL -#define MP_SRAM_RM_CTL__MP_M064X016H1M04S00_RME_MASK__SI 0x00000010L -#define MP_SRAM_RM_CTL__MP_M064X016H1M04S00_RM_MASK__SI 0x0000000fL -#define MP_SRAM_RM_CTL__MP_M064X027H1M04S00_RME_MASK__SI 0x00000200L -#define MP_SRAM_RM_CTL__MP_M064X027H1M04S00_RM_MASK__SI 0x000001e0L -#define MP_SRAM_RM_CTL__MP_M064X040R2M01S00_RME_MASK__SI 0x00080000L -#define MP_SRAM_RM_CTL__MP_M064X040R2M01S00_RM_MASK__SI 0x00078000L -#define MP_SRAM_RM_CTL__MP_M096X032R2M02S00_RME_MASK__SI 0x00004000L -#define MP_SRAM_RM_CTL__MP_M096X032R2M02S00_RM_MASK__SI 0x00003c00L -#define MP_SRAM_RM_CTL__MP_WRM_MASK__SI 0x00f00000L -#define MP_STAT__BUSY_MASK__SI 0x00000001L -#define MP_STAT__MEM_TRANS_PEND_MASK__SI 0x00000002L -#define MP_STAT__MP_DB_TRANS_MASK__SI 0x00000004L -#define MP_VC1_DONE_CTXT__DONE_CTXT_MASK__SI 0x00000001L -#define MP_VC1_PPS_INFO__B_FRAME_MASK__SI 0x20000000L -#define MP_VC1_PPS_INFO__FASTUVMC_MASK__SI 0x00100000L -#define MP_VC1_PPS_INFO__FIELD_PIC_FLAG_MASK__SI 0x00000002L -#define MP_VC1_PPS_INFO__LUMSCALE_MASK__SI 0x00000fc0L -#define MP_VC1_PPS_INFO__MVMODE_MASK__SI 0x00000018L -#define MP_VC1_PPS_INFO__MVRANGE_MASK__SI 0x000c0000L -#define MP_VC1_PPS_INFO__PROFILE_MASK__SI 0xc0000000L -#define MP_VC1_PPS_INFO__RNDFLAG_MASK__SI 0x00000020L -#define MP_VC1_PPS_INFO__SCALE_FACTOR_MASK__SI 0x1fe00000L -#define MP_VC1_PPS_INFO__TOP_FIELD_FIRST_MASK__SI 0x00000001L -#define MP_VC1_REF_INFO__NUMREF_MASK__SI 0x00000020L -#define MP_VC1_REF_INFO__REFDIST_MASK__SI 0x0000000fL -#define MP_VC1_REF_INFO__REF_PIC_FLAG_MASK__SI 0x00000010L -#define MP_VC1_USE_HYBRIDPRED__DONE_HYBRIDPRED_MASK__SI 0x00000001L -#define MP_VC1_USE_HYBRIDPRED__INTRA_MASK__SI 0x00000004L -#define MP_VC1_USE_HYBRIDPRED__USE_HYBRIDPRED_MASK__SI 0x00000002L -#define MSI_CAP_LIST__CAP_ID_MASK 0x000000ffL -#define MSI_CAP_LIST__NEXT_PTR_MASK 0x0000ff00L -#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffffL -#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffcL -#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x00000080L -#define MSI_MSG_CNTL__MSI_EN_MASK 0x00000001L -#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x0000000eL -#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x00000070L -#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000ffffL -#define MSI_MSG_DATA__MSI_DATA_MASK 0x0000ffffL -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK__SI 0x0000000fL -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK__SI 0x00001000L -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK__SI 0x00000100L -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK__SI 0x00000010L -#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK__SI 0x00000003L -#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK__SI 0x3ff00000L -#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK__SI 0x000ffc00L -#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK__SI 0x000003ffL -#define MVP_CONTROL1__MVP_30BPP_EN_MASK__SI 0x10000000L -#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK__SI 0x00000400L -#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK__SI 0x00010000L -#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK__SI 0x01000000L -#define MVP_CONTROL1__MVP_EN_MASK__SI 0x00000001L -#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK__SI 0x00300000L -#define MVP_CONTROL1__MVP_MIXER_MODE_MASK__SI 0x00000070L -#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK__SI 0x00000200L -#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK__SI 0x00000100L -#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK__SI 0x00001000L -#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK__SI 0x40000000L -#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK__SI 0x80000000L -#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK__SI 0x00010000L -#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK__SI 0x00100000L -#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK__SI 0x00000100L -#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK__SI 0x00001000L -#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK__SI 0x00000001L -#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK__SI 0x00000010L -#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK__SI 0x10000000L -#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK__SI 0x01000000L -#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK__SI 0x00000010L -#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK__SI 0x00000100L -#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK__SI 0x00100000L -#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK__SI 0x10000000L -#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK__SI 0x00001000L -#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK__SI 0x00010000L -#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK__SI 0x00000001L -#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK__SI 0x01000000L -#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK__SI 0x000000ffL -#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK__SI 0x20000000L -#define MVP_CRC_CNTL__MVP_CRC_EN_MASK__SI 0x10000000L -#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK__SI 0x0000ff00L -#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK__SI 0x00ff0000L -#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK__SI 0x40000000L -#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK__SI 0x0000ffffL -#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK__SI 0xffff0000L -#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK__SI 0x0000ffffL -#define MVP_DEBUG_01__IDDC_MVP_DATA_ACTIVE_D1_MASK__SI 0x00400000L -#define MVP_DEBUG_01__IDDC_MVP_DATA_ACTIVE_MASK__SI 0x00000400L -#define MVP_DEBUG_01__IDDC_MVP_DEGAMMA_RED_PIXEL_FROM_MASTER_MASK__SI 0x003ff000L -#define MVP_DEBUG_01__IDDC_MVP_MASTER_RED_PIXEL_BEFORE_ADDER_MASK__SI 0xff800000L -#define MVP_DEBUG_01__IDDC_MVP_RED_PIXEL_FROM_MASTER_MASK__SI 0x000003ffL -#define MVP_DEBUG_02__IDDD_MVP_DATA_ACTIVE_D1_MASK__SI 0x00400000L -#define MVP_DEBUG_02__IDDD_MVP_DATA_ACTIVE_MASK__SI 0x00000400L -#define MVP_DEBUG_02__IDDD_MVP_DEGAMMA_RED_PIXEL_FROM_SLAVE_MASK__SI 0x003ff000L -#define MVP_DEBUG_02__IDDD_MVP_RED_PIXEL_FROM_SLAVE_MASK__SI 0x000003ffL -#define MVP_DEBUG_02__IDDD_MVP_SLAVE_RED_PIXEL_BEFORE_ADDER_MASK__SI 0xff800000L -#define MVP_DEBUG_03__IDDE_MVP_DATA_ACTIVE_D1_DUPLICATE_MASK__SI 0x00400000L -#define MVP_DEBUG_03__IDDE_MVP_DATA_ACTIVE_D1_MASK__SI 0x00000400L -#define MVP_DEBUG_03__IDDE_MVP_DATA_ACTIVE_D3_MASK__SI 0x80000000L -#define MVP_DEBUG_03__IDDE_MVP_MASTER_RED_PIXEL_BEFORE_ADDER_MASK__SI 0x000003ffL -#define MVP_DEBUG_03__IDDE_MVP_RED_PIXEL_AFTER_ADDER_MASK__SI 0x7f800000L -#define MVP_DEBUG_03__IDDE_MVP_SLAVE_RED_PIXEL_BEFORE_ADDER_MASK__SI 0x003ff000L -#define MVP_DEBUG_04__IDDF_MVP_DATA_ACTIVE_D3_DUPLICATE_MASK__SI 0x00800000L -#define MVP_DEBUG_04__IDDF_MVP_DATA_ACTIVE_D3_MASK__SI 0x00000400L -#define MVP_DEBUG_04__IDDF_MVP_RED_PIXEL_AFTER_ADDER_MASK__SI 0x000003ffL -#define MVP_DEBUG_04__IDDF_MVP_RED_PIXEL_AFTER_KEYER_ADJUST_MASK__SI 0x007ff000L -#define MVP_DEBUG_05__IDE0_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_CAPTURE_MASK__SI 0x00000100L -#define MVP_DEBUG_05__IDE0_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT_MASK__SI 0x40000000L -#define MVP_DEBUG_05__IDE0_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_REQUEST_MASK__SI 0x00004000L -#define MVP_DEBUG_05__IDE0_MVP_ENABLE_MASK__SI 0x00000001L -#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK__SI 0x00000006L -#define MVP_DEBUG_05__IDE0_MVP_HEAD_SLAVE_GPU_INBAND_OUT_MODE_MASK__SI 0x03000000L -#define MVP_DEBUG_05__IDE0_MVP_HSYNC_FLIP_ENABLE_MASK__SI 0x00000040L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE_CONDITION_DUPLICATE_MASK__SI 0x00020000L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE_CONDITION_MASK__SI 0x00000020L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE_MASK__SI 0x00000400L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE_POSITION_MASK__SI 0x00000080L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT_CONDITION_MASK__SI 0x04000000L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT_HORIZONTAL_POSITION_MASK__SI 0x08000000L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT_MASK__SI 0x20000000L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT_POSITION_MASK__SI 0x10000000L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_REQUEST_HORIZONTAL_POSITION_MASK__SI 0x00001000L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_REQUEST_MASK__SI 0x00010000L -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_REQUEST_POSITION_MASK__SI 0x00002000L -#define MVP_DEBUG_05__IDE0_MVP_MASTER_GPU_IGNORE_INBAND_CHAR_MASK__SI 0x00000008L -#define MVP_DEBUG_05__IDE0_MVP_MIDDLE_SLAVE_GPU_PASS_INBAND_CHAR_MASK__SI 0x00000010L -#define MVP_DEBUG_05__IDE0_MVP_MIXER_FIFO_READ_EN_MASK__SI 0x00040000L -#define MVP_DEBUG_05__IDE0_MVP_MIXER_MODE_MASK__SI 0x00e00000L -#define MVP_DEBUG_05__IDE0_MVP_PIXEL_SELECT_IN_AFR_DRIVER_MODE_MASK__SI 0x00080000L -#define MVP_DEBUG_05__IDE0_MVP_PIXEL_SELECT_IN_AFR_SWITCH_MODE_MASK__SI 0x00100000L -#define MVP_DEBUG_05__IDE0_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_CAPTURE_MASK__SI 0x00000200L -#define MVP_DEBUG_05__IDE0_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT_MASK__SI 0x80000000L -#define MVP_DEBUG_05__IDE0_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_REQUEST_MASK__SI 0x00008000L -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS_IN_HSYNC_FLIP_MODE_DUPLICATE_MASK__SI \ - 0x00180000L -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS_IN_HSYNC_FLIP_MODE_MASK__SI 0x00000060L -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS_IN_VSYNC_FLIP_MODE_MASK__SI 0x00000018L -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS_MASK__SI 0x00000180L -#define MVP_DEBUG_06__IDE1_MVP_AFR_HSYNC_SWITCH_DONE_MASK__SI 0x00200000L -#define MVP_DEBUG_06__IDE1_MVP_AFR_HSYNC_SWITCH_MASK__SI 0x00040000L -#define MVP_DEBUG_06__IDE1_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT_MASK__SI 0x04000000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_CONTROL_CHAR_CAPTURED_DUPLICATE_MASK__SI 0x00006000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_CONTROL_CHAR_CAPTURED_MASK__SI 0x00000006L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW_ASSERT_POSITION_MASK__SI 0x02000000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW_DEASSERT_POSITION_MASK__SI 0x08000000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW_MASK__SI 0x80000000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW_STATUS_MASK__SI 0x40000000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_REQUEST_CAPTURE_POSITION_MASK__SI 0x10000000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_REQUEST_MASK__SI 0x20000000L -#define MVP_DEBUG_06__IDE1_MVP_FLIP_REQUEST_OCCURRED_MASK__SI 0x00800000L -#define MVP_DEBUG_06__IDE1_MVP_HSYNC_FLIP_ENABLE_DUPLICATE_MASK__SI 0x01000000L -#define MVP_DEBUG_06__IDE1_MVP_HSYNC_FLIP_ENABLE_MASK__SI 0x00000200L -#define MVP_DEBUG_06__IDE1_MVP_INBAND_CHAR_CAPTURE_DUPLICATE_MASK__SI 0x00001000L -#define MVP_DEBUG_06__IDE1_MVP_INBAND_CHAR_CAPTURE_MASK__SI 0x00000001L -#define MVP_DEBUG_06__IDE1_MVP_INPUT_FLIP_REQUEST_MASK__SI 0x00400000L -#define MVP_DEBUG_06__IDE1_MVP_PIXEL_SELECT_IN_AFR_SWITCH_MODE_MASK__SI 0x00000400L -#define MVP_DEBUG_06__IDE1_MVP_TEMPORARY_AFR_FLIP_QUEUE_STATUS_MASK__SI 0x00018000L -#define MVP_DEBUG_06__IDE1_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_CAPTURE_MASK__SI 0x00020000L -#define MVP_DEBUG_07__IDE2_MVP_FLIP_NOW_ASSERT_POSITION_MASK__SI 0x40000000L -#define MVP_DEBUG_07__IDE2_MVP_FLIP_REQUEST_MASK__SI 0x20000000L -#define MVP_DEBUG_07__IDE2_MVP_INBAND_CHAR_INSERT_MASK__SI 0x01000000L -#define MVP_DEBUG_07__IDE2_MVP_INBAND_CHAR_MASK__SI 0x00ffffffL -#define MVP_DEBUG_07__IDE2_MVP_SLAVE_AFR_FLIP_QUEUE_STATUS_MASK__SI 0x06000000L -#define MVP_DEBUG_07__IDE2_MVP_SLAVE_FLIP_CONTROL_CHAR_MASK__SI 0x18000000L -#define MVP_DEBUG_08__IDE3_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT_MASK__SI 0x00000002L -#define MVP_DEBUG_08__IDE3_MVP_FLIP_LINE_NUMBER_MASK__SI 0x03ffe000L -#define MVP_DEBUG_08__IDE3_MVP_FLIP_NOW_ASSERT_POSITION_DUPLICATE_MASK__SI 0x00001000L -#define MVP_DEBUG_08__IDE3_MVP_FLIP_NOW_ASSERT_POSITION_MASK__SI 0x00000004L -#define MVP_DEBUG_08__IDE3_MVP_HSYNC_FLIP_ENABLE_MASK__SI 0x00000001L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT_MASK__SI 0x00000200L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_ENABLE_MASK__SI 0x00000001L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_LINE_NUMBER_MASK__SI 0xffe00000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW_ASSERT_DUPLICATE_MASK__SI 0x00100000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW_ASSERT_MASK__SI 0x00040000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW_ASSERT_POSITION_MASK__SI 0x00020000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW_MASK__SI 0x00080000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_REQUEST_CAPTURE_POSITION_MASK__SI 0x00002000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_REQUEST_MASK__SI 0x00004000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_REQUEST_OCCURRED_MASK__SI 0x00008000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK__SI 0x00000006L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_HSYNC_FLIP_ENABLE_MASK__SI 0x00001000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT_CONDITION_MASK__SI 0x00000020L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT_HORIZONTAL_POSITION_MASK__SI 0x00000040L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT_MASK__SI 0x00000100L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT_POSITION_MASK__SI 0x00000080L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_OUT_MODE_MASK__SI 0x00000018L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INPUT_FLIP_REQUEST_MASK__SI 0x00010000L -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT_MASK__SI 0x00000400L -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_FLIP_REQUEST_MASK__SI 0x00000004L -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_INBAND_CHAR_MASK__SI 0xffffff00L -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_INBAND_OUT_MODE_MASK__SI 0x00000003L -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_SLAVE_AFR_FLIP_QUEUE_STATUS_MASK__SI 0x00000060L -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_SLAVE_FLIP_CONTROL_CHAR_MASK__SI 0x00000018L -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_MASTER_MASK__SI 0x00002000L -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_MASTER_TRANSITION_MASK__SI 0x00008000L -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_MASTER_TRANSITION_OCCURRED_MASK__SI \ - 0x00020000L -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_SLAVE_MASK__SI 0x00001000L -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_SLAVE_TRANSITION_MASK__SI 0x00004000L -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_SLAVE_TRANSITION_OCCURRED_MASK__SI \ - 0x00010000L -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_TRANSITION_FROM_BOTH_MASTER_AND_SLAVE_MASK__SI \ - 0x00040000L -#define MVP_DEBUG_11__IDE6_MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK__SI 0x00200000L -#define MVP_DEBUG_11__IDE6_MVP_BLANK_FALLING_EDGE_MASK__SI 0x00000002L -#define MVP_DEBUG_11__IDE6_MVP_HSYNC_FLIP_ENABLE_MASK__SI 0x00000004L -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_EN_MASK__SI 0x00000040L -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_DOUBLE_BUFFERED_MASK__SI 0x00000020L -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_INPUT_MASK__SI 0x00000010L -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_IN_AFR_MANUAL_SWITCH_MODE_MASK__SI 0x00080000L -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SOURCE_SELECT_UPDATE_POSITION_MASK__SI 0x00000008L -#define MVP_DEBUG_11__IDE6_MVP_PIXEL_SELECT_IN_AFR_DRIVER_MODE_MASK__SI 0x00000080L -#define MVP_DEBUG_11__IDE6_MVP_PIXEL_SELECT_IN_AFR_MANUAL_SWITCH_MODE_MASK__SI 0x00100000L -#define MVP_DEBUG_11__IDE6_MVP_V_BLANK_FALLING_EDGE_MASK__SI 0x00000001L -#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK__SI 0x00000001L -#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK__SI 0x01fffffeL -#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK__SI 0x00000001L -#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK__SI 0x01fffffeL -#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK__SI 0x04000000L -#define MVP_DEBUG_13__IDED_START_READ_B_MASK__SI 0x02000000L -#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK__SI 0x38000000L -#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK__SI 0x00100000L -#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK__SI 0x00080000L -#define MVP_DEBUG_14__IDEE_READ_ADD_MASK__SI 0x00000007L -#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK__SI 0x00020000L -#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK__SI 0x00010000L -#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK__SI 0x00040000L -#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK__SI 0x00008000L -#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK__SI 0x00004000L -#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK__SI 0x00000800L -#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK__SI 0x00001000L -#define MVP_DEBUG_14__IDEE_START_READ_B_MASK__SI 0x00000400L -#define MVP_DEBUG_14__IDEE_START_READ_MASK__SI 0x00000200L -#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK__SI 0x00002000L -#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK__SI 0x00000038L -#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK__SI 0x000001c0L -#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK__SI 0xfffffff0L -#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK__SI 0x00000001L -#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK__SI 0x00000008L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK__SI 0x00000004L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK__SI 0x00000002L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK__SI 0x00000ff0L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK__SI 0x00001000L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK__SI 0x00000001L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK__SI 0x00002000L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK__SI 0x00ff0000L -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK__SI 0xff000000L -#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK__SI 0x00000002L -#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK__SI 0xfffffffcL -#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK__SI 0x00000001L -#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK__SI 0x00ff0000L -#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK__SI 0x0000ff00L -#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK__SI 0x000000ffL -#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK__SI 0x80000000L -#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK__SI 0x40000000L -#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK__SI 0x000000ffL -#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK__SI 0x00010000L -#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK__SI 0x00000100L -#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK__SI 0x00001000L -#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK__SI 0x10000000L -#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK__SI 0x00100000L -#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK__SI 0x01000000L -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK__SI 0x40000000L -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK__SI 0x003fff00L -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK__SI 0x00000003L -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK__SI 0x3f000000L -#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK__SI 0x00000001L -#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK__SI 0xffffff00L -#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK__SI 0x00000010L -#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK__SI 0x80000000L -#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK__SI 0x1fff0000L -#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK__SI 0x00001fffL -#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK__SI 0x00001fffL -#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK__SI 0x80000000L -#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK__SI 0x1fff0000L -#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK__SI 0x00001fffL -#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define NB_PSTATE_CONTROL__Mem_Pstate_Dis_MASK__CI__VI 0x80000000L -#define NB_PSTATE_CONTROL__Nb_Pstate_Gnb_Slow_Dis_MASK__CI__VI 0x00800000L -#define NB_PSTATE_CONTROL__Nb_Pstate_Hi_MASK__CI__VI 0x000000c0L -#define NB_PSTATE_CONTROL__Nb_Pstate_Hi_Res_MASK__CI__VI 0x38000000L -#define NB_PSTATE_CONTROL__Nb_Pstate_Lo_MASK__CI__VI 0x00000018L -#define NB_PSTATE_CONTROL__Nb_Pstate_Lo_Res_MASK__CI__VI 0x07000000L -#define NB_PSTATE_CONTROL__Nb_Pstate_Max_Val_MASK__CI__VI 0x00000003L -#define NB_PSTATE_CONTROL__Nb_Pstate_Threshold_MASK__CI__VI 0x00000e00L -#define NB_PSTATE_CONTROL__RESERVED_1_MASK__CI__VI 0x007f8000L -#define NB_PSTATE_CONTROL__RESERVED_2_MASK__CI__VI 0x00001000L -#define NB_PSTATE_CONTROL__RESERVED_3_MASK__CI__VI 0x00000100L -#define NB_PSTATE_CONTROL__RESERVED_4_MASK__CI__VI 0x00000020L -#define NB_PSTATE_CONTROL__RESERVED_5_MASK__CI__VI 0x00000004L -#define NB_PSTATE_CONTROL__RESERVED_MASK__CI__VI 0x40000000L -#define NB_PSTATE_CONTROL__Sw_Nb_Pstate_Dis_On_p0_MASK__CI__VI 0x00002000L -#define NB_PSTATE_CONTROL__Sw_Nb_Pstate_Lo_Dis_MASK__CI__VI 0x00004000L -#define NB_PSTATE_STATUS__Cur_Nb_Did_MASK__CI__VI 0x00000200L -#define NB_PSTATE_STATUS__Cur_Nb_Fid_MASK__CI__VI 0x000001f8L -#define NB_PSTATE_STATUS__Curr_Mem_Pstate_MASK__CI__VI 0x01000000L -#define NB_PSTATE_STATUS__Curr_Nb_Pstate_MASK__CI__VI 0x00180000L -#define NB_PSTATE_STATUS__Curr_Nb_Vid_6_0_MASK__CI__VI 0x0007f000L -#define NB_PSTATE_STATUS__Curr_Nb_Vid_7_MASK__CI__VI 0x00800000L -#define NB_PSTATE_STATUS__Nb_Pstate_Dis_MASK__CI__VI 0x00000001L -#define NB_PSTATE_STATUS__RESERVED_1_MASK__CI__VI 0x00600000L -#define NB_PSTATE_STATUS__RESERVED_2_MASK__CI__VI 0x00000c00L -#define NB_PSTATE_STATUS__RESERVED_MASK__CI__VI 0xfe000000L -#define NB_PSTATE_STATUS__Startup_Nb_Pstate_MASK__CI__VI 0x00000006L -#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK__CI 0x000003ffL -#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK__CI 0x00000400L -#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK__CI 0x00200000L -#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK__CI 0x00000001L -#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK__CI 0x001ffffeL -#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7fffffffL -#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L -#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK__SI 0x0000ffffL -#define OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK__SI \ - 0xffffff80L -#define OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK__SI \ - 0x0000007fL -#define OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK__SI \ - 0xffffffffL -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK__SI \ - 0x04000000L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK__SI \ - 0x00000010L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK__SI 0x10000000L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK__SI \ - 0x00000008L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__FIFO_ERROR_MASK__SI 0x08000000L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__FIFO_READY_MASK__SI 0x20000000L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK__SI \ - 0x00000004L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STREAM_NUMBER_MASK__SI 0x00f00000L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STREAM_RESET_MASK__SI 0x00000001L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STREAM_RUN_MASK__SI 0x00000002L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK__SI 0x00030000L -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK__SI 0x00040000L -#define OUTPUT_STREAM_DESCRIPTOR_0_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK__SI 0xffffffffL -#define OUTPUT_STREAM_DESCRIPTOR_0_FIFO_SIZE__FIFO_SIZE_MASK__SI 0x0000ffffL -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__BITS_PER_SAMPLE_MASK__SI 0x00000070L -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__NUMBER_OF_CHANNELS_MASK__SI 0x0000000fL -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SAMPLE_BASE_DIVISOR_MASK__SI 0x00000700L -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SAMPLE_BASE_MULTIPLE_MASK__SI 0x00003800L -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SAMPLE_BASE_RATE_MASK__SI 0x00004000L -#define OUTPUT_STREAM_DESCRIPTOR_0_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK__SI 0x000000ffL -#define OUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK__SI \ - 0xffffffffL -#define OUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK__SI \ - 0xffffffffL -#define OVLSCL_DEBUG0__OVLSCL_DEBUG0_MASK__SI 0xffffffffL -#define OVLSCL_DEBUG1__OVLSCL_DEBUG1_MASK__SI 0xffffffffL -#define OVLSCL_DEBUG2__OVLSCL_DEBUG2_MASK__SI 0xffffffffL -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK__SI 0x000003ffL -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK__SI 0x000ffc00L -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK__SI 0x3ff00000L -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK__SI 0x80000000L -#define OVL_ALPHA_CONTROL__OVL_ALPHA_INV_MASK__SI 0x00010000L -#define OVL_ALPHA_CONTROL__OVL_ALPHA_MODE_MASK__SI 0x00000003L -#define OVL_ALPHA_CONTROL__OVL_ALPHA_PREMULT_MASK__SI 0x00000100L -#define OVL_ALPHA__OVL_ALPHA_MASK__SI 0x000000ffL -#define OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__OVL_COLOR_MATRIX_TRANSFORMATION_CNTL_MASK__SI \ - 0x00000007L -#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK__SI 0x00010000L -#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK__SI 0x00f00000L -#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK__SI 0x01000000L -#define OVL_CONTROL1__OVL_DEPTH_MASK__SI 0x00000003L -#define OVL_CONTROL1__OVL_FORMAT_MASK__SI 0x00000700L -#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK__SI 0x00020000L -#define OVL_CONTROL1__OVL_TILE_COMPACT_EN_MASK__SI 0x00001000L -#define OVL_CONTROL1__OVL_Z_MASK__SI 0x00000030L -#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK__SI 0x00000001L -#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK__SI 0x00000700L -#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK__SI 0x00000001L -#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK__SI 0x00000070L -#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK__SI 0x0000000fL -#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK__SI 0x00000200L -#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK__SI 0x00000100L -#define OVL_ENABLE__OVLSCL_EN_MASK__SI 0x00000100L -#define OVL_ENABLE__OVL_ENABLE_MASK__SI 0x00000001L -#define OVL_END__OVL_X_END_MASK__SI 0x3fff0000L -#define OVL_END__OVL_Y_END_MASK__SI 0x00003fffL -#define OVL_KEY_ALPHA__OVL_KEY_ALPHA_HIGH_MASK__SI 0x00ff0000L -#define OVL_KEY_ALPHA__OVL_KEY_ALPHA_LOW_MASK__SI 0x000000ffL -#define OVL_KEY_CONTROL__GRPH_KEY_FUNCTION_MASK__SI 0x00000003L -#define OVL_KEY_CONTROL__OVL_KEY_COMPARE_MIX_MASK__SI 0x00010000L -#define OVL_KEY_CONTROL__OVL_KEY_FUNCTION_MASK__SI 0x00000300L -#define OVL_KEY_RANGE_BLUE_CB__OVL_KEY_BLUE_CB_HIGH_MASK__SI 0x03ff0000L -#define OVL_KEY_RANGE_BLUE_CB__OVL_KEY_BLUE_CB_LOW_MASK__SI 0x000003ffL -#define OVL_KEY_RANGE_GREEN_Y__OVL_KEY_GREEN_Y_HIGH_MASK__SI 0x03ff0000L -#define OVL_KEY_RANGE_GREEN_Y__OVL_KEY_GREEN_Y_LOW_MASK__SI 0x000003ffL -#define OVL_KEY_RANGE_RED_CR__OVL_KEY_RED_CR_HIGH_MASK__SI 0x03ff0000L -#define OVL_KEY_RANGE_RED_CR__OVL_KEY_RED_CR_LOW_MASK__SI 0x000003ffL -#define OVL_MATRIX_COEF_1_1__OVL_MATRIX_COEF_1_1_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_1_1__OVL_MATRIX_SIGN_1_1_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_1_2__OVL_MATRIX_COEF_1_2_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_1_2__OVL_MATRIX_SIGN_1_2_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_1_3__OVL_MATRIX_COEF_1_3_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_1_3__OVL_MATRIX_SIGN_1_3_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_1_4__OVL_MATRIX_COEF_1_4_MASK__SI 0x07ffff00L -#define OVL_MATRIX_COEF_1_4__OVL_MATRIX_SIGN_1_4_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_2_1__OVL_MATRIX_COEF_2_1_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_2_1__OVL_MATRIX_SIGN_2_1_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_2_2__OVL_MATRIX_COEF_2_2_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_2_2__OVL_MATRIX_SIGN_2_2_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_2_3__OVL_MATRIX_COEF_2_3_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_2_3__OVL_MATRIX_SIGN_2_3_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_2_4__OVL_MATRIX_COEF_2_4_MASK__SI 0x07ffff00L -#define OVL_MATRIX_COEF_2_4__OVL_MATRIX_SIGN_2_4_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_3_1__OVL_MATRIX_COEF_3_1_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_3_1__OVL_MATRIX_SIGN_3_1_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_3_2__OVL_MATRIX_COEF_3_2_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_3_2__OVL_MATRIX_SIGN_3_2_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_3_3__OVL_MATRIX_COEF_3_3_MASK__SI 0x0007ffffL -#define OVL_MATRIX_COEF_3_3__OVL_MATRIX_SIGN_3_3_MASK__SI 0x80000000L -#define OVL_MATRIX_COEF_3_4__OVL_MATRIX_COEF_3_4_MASK__SI 0x07ffff00L -#define OVL_MATRIX_COEF_3_4__OVL_MATRIX_SIGN_3_4_MASK__SI 0x80000000L -#define OVL_MATRIX_TRANSFORM_EN__OVL_MATRIX_TRANSFORM_EN_MASK__SI 0x00000001L -#define OVL_PITCH__OVL_PITCH_MASK__SI 0x00003fffL -#define OVL_PWL_0TOF__OVL_PWL_0TOF_OFFSET_MASK__SI 0x000001ffL -#define OVL_PWL_0TOF__OVL_PWL_0TOF_SLOPE_MASK__SI 0x07ff0000L -#define OVL_PWL_100TO13F__OVL_PWL_100TO13F_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_100TO13F__OVL_PWL_100TO13F_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_10TO1F__OVL_PWL_10TO1F_OFFSET_MASK__SI 0x000001ffL -#define OVL_PWL_10TO1F__OVL_PWL_10TO1F_SLOPE_MASK__SI 0x07ff0000L -#define OVL_PWL_140TO17F__OVL_PWL_140TO17F_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_140TO17F__OVL_PWL_140TO17F_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_180TO1BF__OVL_PWL_180TO1BF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_180TO1BF__OVL_PWL_180TO1BF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_1C0TO1FF__OVL_PWL_1C0TO1FF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_1C0TO1FF__OVL_PWL_1C0TO1FF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_200TO23F__OVL_PWL_200TO23F_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_200TO23F__OVL_PWL_200TO23F_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_20TO3F__OVL_PWL_20TO3F_OFFSET_MASK__SI 0x000003ffL -#define OVL_PWL_20TO3F__OVL_PWL_20TO3F_SLOPE_MASK__SI 0x03ff0000L -#define OVL_PWL_240TO27F__OVL_PWL_240TO27F_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_240TO27F__OVL_PWL_240TO27F_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_280TO2BF__OVL_PWL_280TO2BF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_280TO2BF__OVL_PWL_280TO2BF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_2C0TO2FF__OVL_PWL_2C0TO2FF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_2C0TO2FF__OVL_PWL_2C0TO2FF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_300TO33F__OVL_PWL_300TO33F_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_300TO33F__OVL_PWL_300TO33F_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_340TO37F__OVL_PWL_340TO37F_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_340TO37F__OVL_PWL_340TO37F_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_380TO3BF__OVL_PWL_380TO3BF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_380TO3BF__OVL_PWL_380TO3BF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_3C0TO3FF__OVL_PWL_3C0TO3FF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_3C0TO3FF__OVL_PWL_3C0TO3FF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_40TO7F__OVL_PWL_40TO7F_OFFSET_MASK__SI 0x000003ffL -#define OVL_PWL_40TO7F__OVL_PWL_40TO7F_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_80TOBF__OVL_PWL_80TOBF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_80TOBF__OVL_PWL_80TOBF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_C0TOFF__OVL_PWL_C0TOFF_OFFSET_MASK__SI 0x000007ffL -#define OVL_PWL_C0TOFF__OVL_PWL_C0TOFF_SLOPE_MASK__SI 0x01ff0000L -#define OVL_PWL_TRANSFORM_EN__OVL_PWL_TRANSFORM_EN_MASK__SI 0x00000001L -#define OVL_RT_BAND_POSITION__OVL_RT_BTM_SCAN_MASK__SI 0x3fff0000L -#define OVL_RT_BAND_POSITION__OVL_RT_TOP_SCAN_MASK__SI 0x00003fffL -#define OVL_RT_PROCEED_COND__OVL_RT_CLEAR_GOBBLE_GO_MASK__SI 0x00004000L -#define OVL_RT_PROCEED_COND__OVL_RT_PROCEED_ON_EOF_DISABLE_MASK__SI 0x00000100L -#define OVL_RT_PROCEED_COND__OVL_RT_REDUCE_DELAY_MASK__SI 0x00000001L -#define OVL_RT_PROCEED_COND__OVL_RT_RT_FLIP_MASK__SI 0x00000010L -#define OVL_RT_PROCEED_COND__OVL_RT_TEAR_PROOF_HEIGHT_MASK__SI 0x3fff0000L -#define OVL_RT_PROCEED_COND__OVL_RT_WITH_HELD_ON_SOF_MASK__SI 0x00001000L -#define OVL_RT_SKEWCOMMAND__OVL_RT_CLEAR_GOBBLE_COUNT_MASK__SI 0x00000001L -#define OVL_RT_SKEWCOMMAND__OVL_RT_CLEAR_SUBMIT_COUNT_MASK__SI 0x00000100L -#define OVL_RT_SKEWCOMMAND__OVL_RT_GOBBLE_COUNT_MASK__SI 0x00070000L -#define OVL_RT_SKEWCOMMAND__OVL_RT_INC_GOBBLE_COUNT_MASK__SI 0x00000010L -#define OVL_RT_SKEWCOMMAND__OVL_RT_INC_SUBMIT_COUNT_MASK__SI 0x00001000L -#define OVL_RT_SKEWCOMMAND__OVL_RT_SUBMIT_COUNT_MASK__SI 0x07000000L -#define OVL_RT_SKEWCONTROL__OVL_RT_CAPS_MASK__SI 0x00000007L -#define OVL_RT_SKEWCONTROL__OVL_RT_SKEW_MAX_MASK__SI 0x00000070L -#define OVL_RT_STAT__OVL_LINE_COUNTER_MASK__SI 0xfff00000L -#define OVL_RT_STAT__OVL_RT_BAND_INVISIBLE_MASK__SI 0x00000100L -#define OVL_RT_STAT__OVL_RT_BAND_SYNC_MASK__SI 0x00000200L -#define OVL_RT_STAT__OVL_RT_EOF_PRPCEED_MASK__SI 0x00000400L -#define OVL_RT_STAT__OVL_RT_FIP_PROCEED_ACK_MASK__SI 0x00000001L -#define OVL_RT_STAT__OVL_RT_FIP_PROCEED_MASK__SI 0x00000800L -#define OVL_RT_STAT__OVL_RT_FRAME_SYNC_ACK_MASK__SI 0x00000002L -#define OVL_RT_STAT__OVL_RT_FRAME_SYNC_MASK__SI 0x00001000L -#define OVL_RT_STAT__OVL_RT_GOBBLE_GO_MASK__SI 0x00002000L -#define OVL_RT_STAT__OVL_RT_NEW_SUBMIT_MASK__SI 0x00004000L -#define OVL_RT_STAT__OVL_RT_OVL_ENDED_MASK__SI 0x00010000L -#define OVL_RT_STAT__OVL_RT_OVL_START_ACK_MASK__SI 0x00000004L -#define OVL_RT_STAT__OVL_RT_OVL_START_MASK__SI 0x00008000L -#define OVL_RT_STAT__OVL_RT_SAFE_ZONE_MASK__SI 0x00020000L -#define OVL_RT_STAT__OVL_RT_SWITCH_REGIONS_MASK__SI 0x00040000L -#define OVL_RT_STAT__OVL_SKEW_MAX_REACHED_MASK__SI 0x00080000L -#define OVL_START__OVL_X_START_MASK__SI 0x1fff0000L -#define OVL_START__OVL_Y_START_MASK__SI 0x00001fffL -#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK__SI 0x000000ffL -#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK__SI 0x000000ffL -#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK__SI 0xffffff00L -#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK__SI 0x00000001L -#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK__SI 0xffffff00L -#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK__SI 0x00001fffL -#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK__SI 0x00001fffL -#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK__SI 0x00000c00L -#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK__SI 0x00000300L -#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK__SI 0x00000003L -#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK__SI 0x000000c0L -#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK__SI 0x00000030L -#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK__SI 0x01000000L -#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK__SI 0x00010000L -#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK__SI 0x00000001L -#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK__SI 0x00000002L -#define P1PLL_CNTL__P1PLL_ANTI_GLITCH_RESET_MASK__SI 0x00002000L -#define P1PLL_CNTL__P1PLL_BYPASS_CAL_MASK__SI 0x00000004L -#define P1PLL_CNTL__P1PLL_CALIB_DONE_MASK__SI 0x00100000L -#define P1PLL_CNTL__P1PLL_CALREF_MASK__SI 0x00000300L -#define P1PLL_CNTL__P1PLL_CAL_BYPASS_REFDIV_MASK__SI 0x00000400L -#define P1PLL_CNTL__P1PLL_DEBUG_SIGNALS_ENABLE_MASK__SI 0x00004000L -#define P1PLL_CNTL__P1PLL_DIFF_REC_ENABLE_MASK__SI 0x00001000L -#define P1PLL_CNTL__P1PLL_DIRECT_CLOCK_2X_MASK__SI 0x80000000L -#define P1PLL_CNTL__P1PLL_DVOCLK_SRC_MASK__SI 0x40000000L -#define P1PLL_CNTL__P1PLL_LOCKED_MASK__SI 0x00200000L -#define P1PLL_CNTL__P1PLL_LOCK_FREQ_SEL_MASK__SI 0x00080000L -#define P1PLL_CNTL__P1PLL_LVTMCLK_SRC_MASK__SI 0x0c000000L -#define P1PLL_CNTL__P1PLL_PCIE_REFCLK_DISABLE_MASK__SI 0x00000800L -#define P1PLL_CNTL__P1PLL_PIXCLK_SRC_MASK__SI 0x30000000L -#define P1PLL_CNTL__P1PLL_PWRMGT_TURN_OFF_PLL_MASK__SI 0x00010000L -#define P1PLL_CNTL__P1PLL_RESET_MASK__SI 0x00000001L -#define P1PLL_CNTL__P1PLL_SLEEP_MASK__SI 0x00000002L -#define P1PLL_CNTL__P1PLL_TIMING_MODE_STATUS_MASK__SI 0x03000000L -#define P1PLL_CNTL__P1PLL_VCOREF_MASK__SI 0x00000030L -#define P1PLL_DEBUG_CLK_SEL__P1PLL_DEBUG_CLK_SEL_MASK__SI 0x00000007L -#define P1PLL_DS_CNTL__P1PLL_DS_FRAC_MASK__SI 0x0000ffffL -#define P1PLL_DS_CNTL__P1PLL_DS_MODE_MASK__SI 0x00040000L -#define P1PLL_DS_CNTL__P1PLL_DS_ORDER_MASK__SI 0x00030000L -#define P1PLL_DS_CNTL__P1PLL_DS_PRBS_EN_MASK__SI 0x00080000L -#define P1PLL_IDCLKA_CNTL__P1PLL_IDCLKA_SRCSEL_FORCE_ENABLE_MASK__SI 0x00000100L -#define P1PLL_IDCLKA_CNTL__P1PLL_IDCLKA_SRCSEL_FORCE_VALUE_MASK__SI 0x00001000L -#define P1PLL_IDCLKA_CNTL__P1PLL_IDCLKA_SRCSEL_MASK__SI 0x00000001L -#define P1PLL_IDCLKA_CNTL__P1PLL_LVTMCLK_SRC_FORCE_ENABLE_MASK__SI 0x00010000L -#define P1PLL_IDCLKA_CNTL__P1PLL_LVTMCLK_SRC_FORCE_VALUE_MASK__SI 0x00300000L -#define P1PLL_INT_SS_CNTL__P1PLL_SS_AMOUNT_FBDIV_MASK__SI 0x000000ffL -#define P1PLL_INT_SS_CNTL__P1PLL_SS_AMOUNT_NFRAC_SLIP_MASK__SI 0x00000f00L -#define P1PLL_INT_SS_CNTL__P1PLL_SS_MODE_MASK__SI 0x00002000L -#define P1PLL_INT_SS_CNTL__P1PLL_SS_STEP_SIZE_DSFRAC_MASK__SI 0xffff0000L -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_DETECT_ENABLE_MASK__SI 0x00000001L -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_DOWN_CNTL_MASK__SI 0x00000f00L -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_DUTY_CYCLE_SELECT_MASK__SI 0x00000002L -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_STICKY_CLEAR_MASK__SI 0x00000008L -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_STICKY_STATUS_MASK__SI 0x00000004L -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_UP_CNTL_MASK__SI 0x000000f0L -#define P1PLL_VREG_CNTL__P1PLL_VREG_BIAS_MASK__SI 0x0f000000L -#define P1PLL_VREG_CNTL__P1PLL_VREG_CNTL_MASK__SI 0x00000003L -#define P1PLL_VREG_CNTL__P1PLL_VREG_POWER_DOWN_MASK__SI 0x20000000L -#define P2PLL_CNTL__P2PLL_ANTI_GLITCH_RESET_MASK__SI 0x00002000L -#define P2PLL_CNTL__P2PLL_BYPASS_CAL_MASK__SI 0x00000004L -#define P2PLL_CNTL__P2PLL_CALIB_DONE_MASK__SI 0x00100000L -#define P2PLL_CNTL__P2PLL_CALREF_MASK__SI 0x00000300L -#define P2PLL_CNTL__P2PLL_CAL_BYPASS_REFDIV_MASK__SI 0x00000400L -#define P2PLL_CNTL__P2PLL_DEBUG_SIGNALS_ENABLE_MASK__SI 0x00004000L -#define P2PLL_CNTL__P2PLL_DIFF_REC_ENABLE_MASK__SI 0x00001000L -#define P2PLL_CNTL__P2PLL_DIRECT_CLOCK_2X_MASK__SI 0x80000000L -#define P2PLL_CNTL__P2PLL_DVOCLK_SRC_MASK__SI 0x40000000L -#define P2PLL_CNTL__P2PLL_LOCKED_MASK__SI 0x00200000L -#define P2PLL_CNTL__P2PLL_LOCK_FREQ_SEL_MASK__SI 0x00080000L -#define P2PLL_CNTL__P2PLL_LVTMCLK_SRC_MASK__SI 0x0c000000L -#define P2PLL_CNTL__P2PLL_PCIE_REFCLK_DISABLE_MASK__SI 0x00000800L -#define P2PLL_CNTL__P2PLL_PIXCLK_SRC_MASK__SI 0x30000000L -#define P2PLL_CNTL__P2PLL_PWRMGT_TURN_OFF_PLL_MASK__SI 0x00010000L -#define P2PLL_CNTL__P2PLL_RESET_MASK__SI 0x00000001L -#define P2PLL_CNTL__P2PLL_SLEEP_MASK__SI 0x00000002L -#define P2PLL_CNTL__P2PLL_TIMING_MODE_STATUS_MASK__SI 0x03000000L -#define P2PLL_CNTL__P2PLL_VCOREF_MASK__SI 0x00000030L -#define P2PLL_DEBUG_CLK_SEL__P2PLL_DEBUG_CLK_SEL_MASK__SI 0x00000700L -#define P2PLL_DS_CNTL__P2PLL_DS_FRAC_MASK__SI 0x0000ffffL -#define P2PLL_DS_CNTL__P2PLL_DS_MODE_MASK__SI 0x00040000L -#define P2PLL_DS_CNTL__P2PLL_DS_ORDER_MASK__SI 0x00030000L -#define P2PLL_DS_CNTL__P2PLL_DS_PRBS_EN_MASK__SI 0x00080000L -#define P2PLL_IDCLKB_CNTL__P2PLL_IDCLKB_SRCSEL_FORCE_ENABLE_MASK__SI 0x00000100L -#define P2PLL_IDCLKB_CNTL__P2PLL_IDCLKB_SRCSEL_FORCE_VALUE_MASK__SI 0x00001000L -#define P2PLL_IDCLKB_CNTL__P2PLL_IDCLKB_SRCSEL_MASK__SI 0x00000001L -#define P2PLL_IDCLKB_CNTL__P2PLL_LVTMCLK_SRC_FORCE_ENABLE_MASK__SI 0x00010000L -#define P2PLL_IDCLKB_CNTL__P2PLL_LVTMCLK_SRC_FORCE_VALUE_MASK__SI 0x00300000L -#define P2PLL_INT_SS_CNTL__P2PLL_SS_AMOUNT_FBDIV_MASK__SI 0x000000ffL -#define P2PLL_INT_SS_CNTL__P2PLL_SS_AMOUNT_NFRAC_SLIP_MASK__SI 0x00000f00L -#define P2PLL_INT_SS_CNTL__P2PLL_SS_MODE_MASK__SI 0x00002000L -#define P2PLL_INT_SS_CNTL__P2PLL_SS_STEP_SIZE_DSFRAC_MASK__SI 0xffff0000L -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_DETECT_ENABLE_MASK__SI 0x00000001L -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_DOWN_CNTL_MASK__SI 0x00000f00L -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_DUTY_CYCLE_SELECT_MASK__SI 0x00000002L -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_STICKY_CLEAR_MASK__SI 0x00000008L -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_STICKY_STATUS_MASK__SI 0x00000004L -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_UP_CNTL_MASK__SI 0x000000f0L -#define P2PLL_VREG_CNTL__P2PLL_VREG_BIAS_MASK__SI 0x0f000000L -#define P2PLL_VREG_CNTL__P2PLL_VREG_CNTL_MASK__SI 0x00000003L -#define P2PLL_VREG_CNTL__P2PLL_VREG_POWER_DOWN_MASK__SI 0x20000000L -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00ffffffL -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0c000000L -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L -#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L -#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000c000L -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L -#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L -#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L -#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L -#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L -#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L -#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L -#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L -#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L -#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L -#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L -#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L -#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L -#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L -#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK__CI__VI 0x00000001L -#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L -#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L -#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L -#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000ffffL -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000L -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000ffffL -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000fL -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000f0L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000f00L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000f000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000f0000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00f00000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0f000000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000f00L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000f000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000f0000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00f00000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0f000000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000fL -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000f0L -#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000ffffL -#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000003fL -#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL -#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x00000003L -#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0x0000000cL -#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x00000003L -#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0x0000000cL -#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000L -#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003f000L -#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00fc0000L -#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0f000000L -#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000f0L -#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000f00L -#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000fL -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000200L -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK__CI__VI 0x10000000L -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK__CI__VI 0x00004000L -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK__CI__VI \ - 0x02000000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK__CI__VI 0x00200000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK__CI__VI 0x00800000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK__CI__VI 0x00040000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK__CI__VI 0x00010000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK__CI__VI 0x00400000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK__CI__VI 0x00080000L -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK__CI__VI 0x00002000L -#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0x000000c0L -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK__CI__VI 0x00000400L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK__CI__VI 0x00000800L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK__CI__VI 0x00001000L -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK__CI__VI 0x20000000L -#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L -#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L -#define PA_SC_ENHANCE__ECO_SPARE2_MASK__SI 0x20000000L -#define PA_SC_ENHANCE__ECO_SPARE3_MASK__SI 0x10000000L -#define PA_SC_ENHANCE__ECO_SPARE4_MASK__SI 0x08000000L -#define PA_SC_ENHANCE__ECO_SPARE5_MASK__SI 0x04000000L -#define PA_SC_ENHANCE__ECO_SPARE6_MASK__SI 0x02000000L -#define PA_SC_ENHANCE__ECO_SPARE7_MASK__SI 0x01000000L -#define PA_SC_ENHANCE__ECO_SPARE8_MASK__SI 0x00fff000L -#define PA_SC_ENHANCE__ECO_SPARE9_MASK__SI 0x00000800L -#define PA_SC_ENHANCE__ECO_SPAREA_MASK__SI 0x00000400L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK__CI__VI 0x00008000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK__CI__VI 0x01000000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK__CI__VI 0x00020000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK__CI__VI 0x00100000L -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK__CI__VI 0x08000000L -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK__CI__VI 0x04000000L -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000100L -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK__CI__VI 0x000003ffL -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK__SI 0x000000ffL -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007fc0L -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000L -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003fL -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001f8000L -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000ffffL -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000L -#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007fffL -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007fffL -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK__CI__VI 0x0000ffffL -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK__CI__VI 0x00000001L -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK__CI__VI 0x00000002L -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK__CI__VI 0x00000001L -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK__CI__VI 0x00003fffL -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK__CI__VI 0x0000ffffL -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK__CI__VI 0x00003fffL -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00fc0000L -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000fc0L -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003fL -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003f000L -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L -#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L -#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00f00000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L -#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK__CI__VI 0x0000ffffL -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK__CI__VI 0x00000001L -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK__CI__VI 0x00000002L -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK__CI__VI 0x00000001L -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK__CI__VI 0x00003fffL -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK__CI__VI 0x0000ffffL -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK__CI__VI 0x00003fffL -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK__SI 0x000001ffL -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK__CI__VI 0x00000003L -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK__CI__VI 0x0000000cL -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK__CI__VI 0x00000030L -#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L -#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK__CI__VI 0x0000c000L -#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000c00L -#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000cL -#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L -#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L -#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L -#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L -#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000c0000L -#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L -#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L -#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0c000000L -#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK__CI__VI 0x00000003L -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK__CI__VI 0x0000000cL -#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK__CI__VI 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK__CI__VI 0xffff0000L -#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK__CI__VI 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK__CI__VI 0xffff0000L -#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK__CI__VI 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK__CI__VI 0xffff0000L -#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK__CI__VI 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK__CI__VI 0xffff0000L -#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000ffffL -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000L -#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000ffffL -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000L -#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK__CI__VI 0x0000ffffL -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK__CI__VI 0x00000001L -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK__CI__VI 0x00000002L -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK__CI__VI 0x00000001L -#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK__CI__VI 0x00003fffL -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK__CI__VI 0x0000ffffL -#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK__CI__VI 0x00003fffL -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffffL -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000ffffL -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000L -#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007fffL -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000L -#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007fffL -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L -#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL -#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001ffL -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01ff0000L -#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffffL -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00ffffffL -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L -#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL -#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL -#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffffL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000ffL -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000ff00L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK__CI__VI 0x40000000L -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK__CI__VI 0x80000000L -#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L -#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L -#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L -#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L -#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L -#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L -#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L -#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK__CI__VI 0x00000001L -#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK__CI__VI 0x0000003eL -#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK__CI__VI 0x00000f00L -#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK__CI__VI 0x00800000L -#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK__CI__VI 0x00000080L -#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK__CI__VI 0x00200000L -#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK__CI__VI 0x00400000L -#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK__CI__VI 0x00100000L -#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK__CI__VI 0x0000003fL -#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK__CI__VI 0xff000000L -#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK__CI__VI 0x00010000L -#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK__CI__VI 0x00000100L -#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK__CI__VI 0x000000ffL -#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK__CI__VI 0x00f00000L -#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK__CI__VI 0x000e0000L -#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK__CI__VI 0x0000ffffL -#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK__CI__VI 0x000000ffL -#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK__CI__VI 0x00010000L -#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK__CI__VI 0x0000ff00L -#define PB0_GLB_CTRL_REG0__BACKUP_MASK__CI__VI 0x0000ffffL -#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK__CI__VI 0x00030000L -#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK__CI__VI 0x00700000L -#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK__CI__VI 0x00800000L -#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK__CI__VI 0x01000000L -#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK__CI__VI 0x02000000L -#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK__CI__VI 0x04000000L -#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK__CI__VI 0xc0000000L -#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK__CI__VI 0x80000000L -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK__CI__VI 0x00000001L -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK__CI__VI 0x0000007eL -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK__CI__VI 0x00000080L -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK__CI__VI 0x00003f00L -#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK__CI__VI 0x00004000L -#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK__CI__VI 0x003f8000L -#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK__CI__VI 0x00400000L -#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK__CI__VI 0x3f800000L -#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK__CI__VI 0x40000000L -#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK__CI__VI 0x00000001L -#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK__CI__VI 0x000000feL -#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK__CI__VI 0x00000100L -#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK__CI__VI 0x0000fe00L -#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK__CI__VI 0x00010000L -#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK__CI__VI 0x00fe0000L -#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK__CI__VI 0x01000000L -#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK__CI__VI 0xfe000000L -#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK__CI__VI 0x00000060L -#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK__CI__VI 0x00000180L -#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK__CI__VI 0x00000600L -#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK__CI__VI 0x0001c000L -#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK__CI__VI 0x00001000L -#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK__CI__VI 0x00000800L -#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK__CI__VI 0x001c0000L -#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK__CI__VI 0x80000000L -#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK__CI__VI 0x00400000L -#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK__CI__VI 0x07800000L -#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK__CI__VI 0x08000000L -#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK__CI__VI 0x70000000L -#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK__CI__VI 0x00200000L -#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK__CI__VI 0x0000001fL -#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK__CI__VI 0x03c00000L -#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK__CI__VI 0x0000ffffL -#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK__CI__VI 0x00040000L -#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK__CI__VI 0x00030000L -#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK__CI__VI 0x04000000L -#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK__CI__VI 0x10000000L -#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK__CI__VI 0x08000000L -#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK__CI__VI 0x000000ffL -#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK__CI__VI 0x0000ffffL -#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK__CI__VI 0xffff0000L -#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK__CI__VI 0x00008000L -#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK__CI__VI 0xffff0000L -#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK__CI__VI 0x00000004L -#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK__CI__VI 0x00000008L -#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK__CI__VI 0x00000001L -#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK__CI__VI 0x00000001L -#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK__CI__VI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK__CI 0x00000008L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK__CI 0x00000010L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK__CI__VI 0x00100000L -#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK__CI__VI 0x000f0000L -#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK__CI__VI 0x00000f00L -#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK__CI__VI 0x0000f000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK__CI__VI 0x00001000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK__CI__VI 0x00002000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK__CI__VI 0x00004000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK__CI__VI 0x00008000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK__CI__VI 0x000c0000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK__CI__VI 0x00c00000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK__CI__VI 0x0c000000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK__CI__VI 0xc0000000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK__CI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK__CI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK__CI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK__CI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK__CI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK__CI 0x30000000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK__CI__VI 0x00001000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK__CI__VI 0x00002000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK__CI__VI 0x00004000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK__CI__VI 0x00008000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK__CI__VI 0x000c0000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK__CI__VI 0x00c00000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK__CI__VI 0x0c000000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK__CI__VI 0xc0000000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK__CI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK__CI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK__CI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK__CI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK__CI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK__CI 0x30000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK__CI__VI 0x00004000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK__CI__VI 0x00008000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK__CI__VI 0x00001000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK__CI__VI 0x00002000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK__CI__VI 0x0c000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK__CI__VI 0xc0000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK__CI__VI 0x000c0000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK__CI__VI 0x00c00000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK__CI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK__CI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK__CI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK__CI 0x30000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK__CI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK__CI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK__CI__VI 0x00001000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK__CI__VI 0x00002000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK__CI__VI 0x00004000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK__CI__VI 0x00008000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK__CI__VI 0x000c0000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK__CI__VI 0x00c00000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK__CI__VI 0x0c000000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK__CI__VI 0xc0000000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK__CI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK__CI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK__CI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK__CI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK__CI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK__CI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK__CI 0x30000000L -#define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK__CI 0x00000001L -#define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK__CI 0x00000002L -#define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK__CI 0x00000004L -#define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK__CI 0x00000008L -#define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK__CI 0x00000010L -#define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK__CI 0x00000020L -#define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK__CI 0x00000040L -#define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK__CI 0x00000080L -#define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK__CI 0x00000100L -#define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK__CI 0x00000200L -#define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK__CI 0x00000400L -#define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK__CI 0x00000800L -#define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK__CI 0x00001000L -#define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK__CI 0x00002000L -#define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK__CI 0x00004000L -#define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK__CI 0x00008000L -#define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK__CI 0x00010000L -#define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK__CI 0x00020000L -#define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK__CI 0x00040000L -#define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK__CI 0x00080000L -#define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK__CI 0x00100000L -#define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK__CI 0x00200000L -#define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK__CI 0x00400000L -#define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK__CI 0x00800000L -#define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK__CI 0x01000000L -#define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK__CI 0x02000000L -#define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK__CI 0x04000000L -#define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK__CI 0x08000000L -#define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK__CI 0x10000000L -#define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK__CI 0x20000000L -#define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK__CI 0x40000000L -#define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK__CI 0x80000000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK__CI 0x00000080L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK__CI 0x00000100L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK__CI 0x00040000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK__CI 0x00080000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK__CI 0x00100000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK__CI 0x00200000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK__CI 0x00400000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK__CI 0x00800000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK__CI 0x00000200L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK__CI 0x00000400L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK__CI 0x00000800L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK__CI 0x00001000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK__CI 0x00002000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK__CI 0x00004000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK__CI 0x00008000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK__CI 0x00010000L -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK__CI 0x00020000L -#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK__CI 0x00000006L -#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK__CI 0x07000000L -#define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK__CI 0x00000002L -#define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK__CI 0x00000020L -#define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK__CI 0x00000200L -#define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK__CI 0x00002000L -#define PB0_PIF_CNTL__DIVINIT_MODE_MASK__CI 0x00000100L -#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK__CI 0x00700000L -#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK__CI 0x00000010L -#define PB0_PIF_CNTL__ENABLE_CT_TRIGGER_CLKEN_FIX_MASK__CI 0x40000000L -#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK__CI 0x00800000L -#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK__CI 0x10000000L -#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK__CI 0x20000000L -#define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK__CI 0x000e0000L -#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK__CI 0x00000008L -#define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK__CI 0x00000004L -#define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK__CI 0x00000400L -#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK__CI 0x00000040L -#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK__CI 0x00000080L -#define PB0_PIF_CNTL__RXEN_GATER_MASK__CI 0x0f000000L -#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK__CI 0x00000800L -#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK__CI 0x00000001L -#define PB0_PIF_CNTL__TXGND_TIME_MASK__CI 0x00010000L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK__CI 0x00000001L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK__CI 0x00000002L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK__CI 0x00000004L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK__CI 0x00000008L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK__CI 0x00000010L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK__CI 0x00000020L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK__CI 0x00000040L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK__CI 0x00000080L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK__CI 0x00000100L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK__CI 0x00000200L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK__CI 0x00000400L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK__CI 0x00000800L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK__CI 0x00001000L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK__CI 0x00002000L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK__CI 0x00004000L -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK__CI 0x00008000L -#define PB0_PIF_PAIRING__MULTI_PIF_MASK__CI 0x02000000L -#define PB0_PIF_PAIRING__X16_LANE_15_0_MASK__CI 0x00100000L -#define PB0_PIF_PAIRING__X2_LANE_11_10_MASK__CI 0x00000020L -#define PB0_PIF_PAIRING__X2_LANE_13_12_MASK__CI 0x00000040L -#define PB0_PIF_PAIRING__X2_LANE_15_14_MASK__CI 0x00000080L -#define PB0_PIF_PAIRING__X2_LANE_1_0_MASK__CI 0x00000001L -#define PB0_PIF_PAIRING__X2_LANE_3_2_MASK__CI 0x00000002L -#define PB0_PIF_PAIRING__X2_LANE_5_4_MASK__CI 0x00000004L -#define PB0_PIF_PAIRING__X2_LANE_7_6_MASK__CI 0x00000008L -#define PB0_PIF_PAIRING__X2_LANE_9_8_MASK__CI 0x00000010L -#define PB0_PIF_PAIRING__X4_LANE_11_8_MASK__CI 0x00000400L -#define PB0_PIF_PAIRING__X4_LANE_15_12_MASK__CI 0x00000800L -#define PB0_PIF_PAIRING__X4_LANE_3_0_MASK__CI 0x00000100L -#define PB0_PIF_PAIRING__X4_LANE_7_4_MASK__CI 0x00000200L -#define PB0_PIF_PAIRING__X8_LANE_15_8_MASK__CI 0x00020000L -#define PB0_PIF_PAIRING__X8_LANE_7_0_MASK__CI 0x00010000L -#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK__CI 0x0000000eL -#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK__CI 0x00000100L -#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK__CI 0x00000200L -#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK__CI 0x00004000L -#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK__CI 0x00038000L -#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK__CI 0x00000010L -#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK__CI 0x000000e0L -#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK__CI 0x00000400L -#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK__CI 0x00003800L -#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK__CI 0x00000001L -#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK__CI 0x0000000eL -#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK__CI 0x00000008L -#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK__CI 0x10000000L -#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK__CI 0xe0000000L -#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK__CI 0x00001c00L -#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK__CI 0x00000380L -#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK__CI 0x07000000L -#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK__CI 0x00000070L -#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK__CI 0x00010000L -#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK__CI 0x00000007L -#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK__CI 0x00000008L -#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK__CI 0x10000000L -#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK__CI 0xe0000000L -#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK__CI 0x00001c00L -#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK__CI 0x00000380L -#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK__CI 0x07000000L -#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK__CI 0x00000070L -#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK__CI 0x00010000L -#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK__CI 0x00000007L -#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK__CI 0x00000008L -#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK__CI 0x10000000L -#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK__CI 0xe0000000L -#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK__CI 0x00001c00L -#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK__CI 0x00000380L -#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK__CI 0x07000000L -#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK__CI 0x00000070L -#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK__CI 0x00010000L -#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK__CI 0x00000007L -#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK__CI 0x00000008L -#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK__CI 0x10000000L -#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK__CI 0xe0000000L -#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK__CI 0x00001c00L -#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK__CI 0x00000380L -#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK__CI 0x07000000L -#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK__CI 0x00000070L -#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK__CI 0x00010000L -#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK__CI 0x00000007L -#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK__CI__VI 0xffffffffL -#define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK__CI 0x00000001L -#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK__CI 0x00000010L -#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK__CI 0x00000020L -#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK__CI 0x00000004L -#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK__CI 0x00000008L -#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK__CI 0x00010000L -#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK__CI 0x04000000L -#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK__CI 0x08000000L -#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK__CI 0x10000000L -#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK__CI 0x20000000L -#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK__CI 0x40000000L -#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK__CI 0x80000000L -#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK__CI 0x00020000L -#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK__CI 0x00040000L -#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK__CI 0x00080000L -#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK__CI 0x00100000L -#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK__CI 0x00200000L -#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK__CI 0x00400000L -#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK__CI 0x00800000L -#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK__CI 0x01000000L -#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK__CI 0x02000000L -#define PB0_PIF_SC_CTL__SC_PHASE_1_MASK__CI 0x00000100L -#define PB0_PIF_SC_CTL__SC_PHASE_2_MASK__CI 0x00000200L -#define PB0_PIF_SC_CTL__SC_PHASE_3_MASK__CI 0x00000400L -#define PB0_PIF_SC_CTL__SC_PHASE_4_MASK__CI 0x00000800L -#define PB0_PIF_SC_CTL__SC_PHASE_5_MASK__CI 0x00001000L -#define PB0_PIF_SC_CTL__SC_PHASE_6_MASK__CI 0x00002000L -#define PB0_PIF_SC_CTL__SC_PHASE_7_MASK__CI 0x00004000L -#define PB0_PIF_SC_CTL__SC_PHASE_8_MASK__CI 0x00008000L -#define PB0_PIF_SC_CTL__SC_RXDETECT_MASK__CI 0x00000002L -#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK__CI 0x00000040L -#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK__CI 0x00000001L -#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK__CI 0x00000010L -#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK__CI 0x00000020L -#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK__CI 0x00000004L -#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK__CI 0x00000008L -#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK__CI 0x00000700L -#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK__CI 0x00000002L -#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK__CI 0x00000040L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK__CI 0x00000001L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK__CI 0x00000400L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK__CI 0x00000800L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK__CI 0x00001000L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK__CI 0x00002000L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK__CI 0x00004000L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK__CI 0x00008000L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK__CI 0x00000002L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK__CI 0x00000004L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK__CI 0x00000008L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK__CI 0x00000010L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK__CI 0x00000020L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK__CI 0x00000040L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK__CI 0x00000080L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK__CI 0x00000100L -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK__CI 0x00000200L -#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK__CI__VI 0x00000003L -#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK__CI__VI 0x00000004L -#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK__CI__VI 0x00000008L -#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK__CI__VI 0x00000010L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK__CI__VI 0x00000008L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x00000007L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK__CI__VI 0x00000080L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK__CI__VI 0x00000070L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK__CI__VI 0x00000200L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK__CI__VI 0x00000100L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK__CI__VI 0x00040000L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK__CI__VI 0x0003fc00L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK__CI__VI 0x10000000L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x0ff80000L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK__CI__VI 0x80000000L -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK__CI__VI 0x60000000L -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK__CI__VI 0x00000008L -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK__CI__VI 0x00000007L -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK__CI__VI 0x00040000L -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK__CI__VI 0x0003c000L -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK__CI__VI 0x00000020L -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000010L -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK__CI__VI 0x00000080L -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000040L -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK__CI__VI 0x00000200L -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00000100L -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK__CI__VI 0x00000003L -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK__CI__VI 0x00000004L -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK__CI__VI 0x000007f0L -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK__CI__VI 0x00000008L -#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK__CI__VI 0x00000800L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK__CI__VI 0x00000100L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x000000ffL -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK__CI__VI 0x00001000L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK__CI__VI 0x00000e00L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK__CI__VI 0x00004000L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK__CI__VI 0x00002000L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK__CI__VI 0x10000000L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK__CI__VI 0x0fff8000L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK__CI__VI 0x80000000L -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x40000000L -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK__CI__VI 0x00400000L -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK__CI__VI 0x00380000L -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK__CI__VI 0x00000020L -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK__CI__VI 0x0000001fL -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK__CI__VI 0x00000100L -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK__CI__VI 0x000000c0L -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK__CI__VI 0x00000400L -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000200L -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK__CI__VI 0x00001000L -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000800L -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK__CI__VI 0x00004000L -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00002000L -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK__CI 0x00000300L -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK__CI__VI 0x00000070L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00000200L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00000400L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00000800L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK__CI 0x00100000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK__CI 0x00200000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00001000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00002000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00004000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK__CI 0x00400000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK__CI 0x00800000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x00000100L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00000002L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00000004L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00000008L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK__CI 0x00010000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK__CI 0x00020000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00000010L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00000020L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00000040L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK__CI 0x00040000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK__CI 0x00080000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x00000080L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK__CI__VI 0x00000001L -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK__CI__VI 0x000003ffL -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK__CI__VI 0x000ffc00L -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK__CI__VI 0x3ff00000L -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK__CI 0xc0000000L -#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK__CI__VI 0xc0000000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK__CI__VI 0x0000000fL -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK__CI__VI 0x000000f0L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK__CI__VI 0x00000f00L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK__CI__VI 0x0000f000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK__CI__VI 0x000f0000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK__CI__VI 0x00f00000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK__CI__VI 0x01000000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK__CI__VI 0x02000000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK__CI__VI 0x04000000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK__CI__VI 0x08000000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK__CI__VI 0x10000000L -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK__CI__VI 0x20000000L -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK__CI__VI 0x0000f000L -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK__CI__VI 0x000f0000L -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK__CI__VI 0x00f00000L -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK__CI__VI 0x03000000L -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK__CI__VI 0x0c000000L -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK__CI__VI 0x30000000L -#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK__CI__VI 0xc0000000L -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK__CI__VI 0x00000001L -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK__CI__VI 0x00000002L -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK__CI__VI 0x00000004L -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK__CI__VI 0x00f00000L -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK__CI__VI 0x0f000000L -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK__CI__VI 0xf0000000L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK__CI__VI 0x00000007L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK__CI__VI 0x00000038L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK__CI__VI 0x000001c0L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK__CI__VI 0x00f00000L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK__CI__VI 0x0f000000L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK__CI__VI 0xf0000000L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK__CI__VI 0x00000e00L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK__CI__VI 0x00007000L -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK__CI__VI 0x00038000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK__CI__VI 0x0000001fL -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK__CI__VI 0x000003e0L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK__CI__VI 0x00007c00L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK__CI__VI 0x00008000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK__CI__VI 0x00010000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK__CI__VI 0x00020000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK__CI__VI 0x00040000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK__CI__VI 0x00080000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK__CI__VI 0x00100000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK__CI__VI 0x08000000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK__CI__VI 0x10000000L -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK__CI__VI 0x20000000L -#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK__CI__VI 0x40000000L -#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x08000000L -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK__CI__VI 0x0000000fL -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK__CI__VI 0x000000f0L -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK__CI__VI 0x00000f00L -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK__CI__VI 0x0000f000L -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK__CI__VI 0x000f0000L -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK__CI__VI 0x00f00000L -#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK__CI__VI 0x01000000L -#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x04000000L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK__CI__VI 0x001c0000L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK__CI__VI 0x00e00000L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK__CI__VI 0x07000000L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK__CI__VI 0x08000000L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK__CI__VI 0x10000000L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK__CI__VI 0x20000000L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK__CI__VI 0x0000000fL -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK__CI__VI 0x000000f0L -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK__CI__VI 0x00000f00L -#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK__CI__VI 0x00001000L -#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00002000L -#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK__CI 0x00020000L -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK__CI__VI 0x80000000L -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK__CI__VI 0x40000000L -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK__CI__VI 0x00000001L -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK__CI__VI 0x00000008L -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK__CI__VI 0x00000004L -#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK__CI__VI 0x20000000L -#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK__CI__VI 0x10000000L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK__CI__VI 0x00000100L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK__CI__VI 0x000000c0L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK__CI__VI 0x00000400L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK__CI__VI 0x00000200L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK__CI__VI 0x00001000L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK__CI__VI 0x00000800L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK__CI__VI 0x00004000L -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK__CI__VI 0x00002000L -#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK__CI__VI 0x00010000L -#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK__CI__VI 0x00008000L -#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK__CI__VI 0x00040000L -#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK__CI__VI 0x00020000L -#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK__CI__VI 0x00100000L -#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK__CI__VI 0x00080000L -#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK__CI__VI 0x00400000L -#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK__CI__VI 0x00200000L -#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK__CI__VI 0x01000000L -#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK__CI__VI 0x00800000L -#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK__CI__VI 0x00000001L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK__CI 0x00000010L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK__CI 0x00000080L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK__CI 0x00000020L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK__CI 0x00000040L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK__CI 0x00001000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK__CI 0x00008000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK__CI 0x00002000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK__CI 0x00004000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK__CI 0x00010000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK__CI 0x00080000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK__CI 0x00020000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK__CI 0x00040000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK__CI 0x00100000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK__CI 0x00800000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK__CI 0x00200000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK__CI 0x00400000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK__CI 0x00000100L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK__CI 0x00000800L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK__CI 0x00000200L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK__CI 0x00000400L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK__CI 0x00000008L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK__CI 0x00000070L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK__CI 0x00000070L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK__CI 0x00000070L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK__CI 0x00000070L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK__CI 0x00000070L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK__CI 0x00000070L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK__CI 0x00000070L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK__CI 0x00000070L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK__CI 0x00000070L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK__CI 0x00000070L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK__CI 0x00000070L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK__CI 0x00000070L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK__CI 0x00000070L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK__CI 0x00000070L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK__CI 0x00000070L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK__CI__VI 0x00000007L -#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK__CI__VI 0x000000ffL -#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK__CI__VI 0x00002000L -#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK__CI__VI 0x00000c00L -#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK__CI__VI 0x00001000L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK__CI__VI 0x00000008L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK__CI__VI 0x00000080L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK__CI__VI 0x00000100L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK__CI__VI 0x00000200L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK__CI 0x00000070L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK__CI__VI 0x00000007L -#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK__CI__VI 0x00000060L -#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK__CI__VI 0x00008000L -#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK__CI__VI 0x01e00000L -#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK__CI__VI 0x00100000L -#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK__CI__VI 0x00000008L -#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK__CI__VI 0x00000004L -#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK__CI__VI 0x000f0000L -#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK__CI__VI 0x00004000L -#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK__CI__VI 0x00000002L -#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK__CI__VI 0x00000f80L -#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK__CI__VI 0x00001000L -#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK__CI__VI 0x00002000L -#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK__CI__VI 0x00000002L -#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK__CI__VI 0x00000004L -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK__CI__VI 0x0000000eL -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK__CI__VI 0x00001ff0L -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK__CI__VI 0x00ff0000L -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK__CI__VI 0x00008000L -#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK__CI__VI 0x01000000L -#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK__CI__VI 0x00002000L -#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK__CI__VI 0x00000300L -#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK__CI__VI 0x00000c00L -#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK__CI__VI 0x00000040L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK__CI__VI 0x0000f000L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK__CI__VI 0x00000020L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK__CI__VI 0x000f0000L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK__CI__VI 0x00000080L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK__CI__VI 0x00f00000L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK__CI__VI 0x0f000000L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK__CI__VI 0x80000000L -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK__CI__VI 0x0000001eL -#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK__CI__VI 0x70000000L -#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK__CI__VI 0x00000060L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK__CI__VI 0x01ff8000L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK__CI__VI 0x00007800L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK__CI__VI 0x00000002L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK__CI__VI 0x1e000000L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK__CI__VI 0x60000000L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK__CI__VI 0x00000080L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK__CI__VI 0x00000700L -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK__CI__VI 0x80000000L -#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK__CI__VI 0x0000001cL -#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK__CI__VI 0x20000000L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK__CI__VI 0x0000001eL -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK__CI__VI 0x000001e0L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK__CI__VI 0x00003e00L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK__CI__VI 0x0007c000L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK__CI__VI 0x00780000L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK__CI__VI 0x07800000L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK__CI__VI 0x08000000L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK__CI__VI 0x10000000L -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK__CI__VI 0x40000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK__CI__VI 0x00000001L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK__CI__VI 0x00000400L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK__CI__VI 0x00000800L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK__CI__VI 0x00001000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK__CI__VI 0x00002000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK__CI__VI 0x00004000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK__CI__VI 0x00008000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK__CI__VI 0x00010000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK__CI__VI 0x00020000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK__CI__VI 0x00040000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK__CI__VI 0x00080000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK__CI__VI 0x00000002L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK__CI__VI 0x00100000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK__CI__VI 0x00200000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK__CI__VI 0x00400000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK__CI__VI 0x00800000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK__CI__VI 0x01000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK__CI__VI 0x02000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK__CI__VI 0x04000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK__CI__VI 0x08000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK__CI__VI 0x10000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK__CI__VI 0x20000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK__CI__VI 0x00000004L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK__CI__VI 0x40000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK__CI__VI 0x80000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK__CI__VI 0x00000008L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK__CI__VI 0x00000040L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK__CI__VI 0x00000080L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK__CI__VI 0x00000001L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK__CI__VI 0x00000002L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK__CI__VI 0x00000004L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK__CI__VI 0x00000008L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK__CI__VI 0x00000040L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK__CI__VI 0x00000080L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK__CI__VI 0x00000400L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK__CI__VI 0x00000800L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK__CI__VI 0x00001000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK__CI__VI 0x00002000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK__CI__VI 0x00004000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK__CI__VI 0x00008000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK__CI__VI 0x00010000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK__CI__VI 0x00020000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK__CI__VI 0x00040000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK__CI__VI 0x00080000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK__CI__VI 0x00100000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK__CI__VI 0x00200000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK__CI__VI 0x00400000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK__CI__VI 0x00800000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK__CI__VI 0x01000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK__CI__VI 0x02000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK__CI__VI 0x04000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK__CI__VI 0x08000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK__CI__VI 0x10000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK__CI__VI 0x20000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK__CI__VI 0x40000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK__CI__VI 0x80000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK__CI__VI 0x00000001L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK__CI__VI 0x00000002L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK__CI__VI 0x00000004L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK__CI__VI 0x00000008L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK__CI__VI 0x00000040L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK__CI__VI 0x00000080L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK__CI__VI 0x00000400L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK__CI__VI 0x00000800L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK__CI__VI 0x00001000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK__CI__VI 0x00002000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK__CI__VI 0x00004000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK__CI__VI 0x00008000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK__CI__VI 0x00010000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK__CI__VI 0x00020000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK__CI__VI 0x00040000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK__CI__VI 0x00080000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK__CI__VI 0x00100000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK__CI__VI 0x00200000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK__CI__VI 0x00400000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK__CI__VI 0x00800000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK__CI__VI 0x01000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK__CI__VI 0x02000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK__CI__VI 0x04000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK__CI__VI 0x08000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK__CI__VI 0x10000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK__CI__VI 0x20000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK__CI__VI 0x40000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK__CI__VI 0x80000000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK__CI__VI 0x00000040L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK__CI__VI 0x00000080L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK__CI__VI 0x00000400L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK__CI__VI 0x00000800L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK__CI__VI 0x00001000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK__CI__VI 0x00002000L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK__CI__VI 0x00000001L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK__CI__VI 0x00000002L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK__CI__VI 0x00000004L -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK__CI__VI 0x00000008L -#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK__CI__VI 0x00000700L -#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK__CI__VI 0x00003800L -#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK__CI__VI 0x0001c000L -#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK__CI__VI 0x00400000L -#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK__CI__VI 0x00200000L -#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK__CI__VI 0x00080000L -#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK__CI__VI 0x00800000L -#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK__CI__VI 0x00000007L -#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK__CI__VI 0x00000038L -#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK__CI 0x01000000L -#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK__CI__VI 0x00100000L -#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK__CI__VI 0x00060000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK__CI__VI 0x40000000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK__CI__VI 0x00000001L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK__CI__VI 0x00000400L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK__CI__VI 0x00000800L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK__CI__VI 0x00001000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK__CI__VI 0x00002000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK__CI__VI 0x00004000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK__CI__VI 0x00008000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK__CI__VI 0x00000002L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK__CI__VI 0x00000004L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK__CI__VI 0x00000008L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK__CI__VI 0x00000040L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK__CI__VI 0x00000080L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK__CI__VI 0x00010000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK__CI__VI 0x00200000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK__CI__VI 0x00400000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK__CI__VI 0x00800000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK__CI__VI 0x00020000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK__CI__VI 0x00040000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK__CI__VI 0x00080000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK__CI__VI 0x00100000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK__CI__VI 0x01000000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK__CI__VI 0x08000000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK__CI__VI 0x02000000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK__CI__VI 0x04000000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK__CI__VI 0x10000000L -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK__CI__VI 0x20000000L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK__CI__VI 0x00000008L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK__CI__VI 0x00000007L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x000000f0L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x00001e00L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK__CI__VI 0x00002000L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x0007c000L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK__CI__VI 0x00080000L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x01f00000L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK__CI__VI 0x02000000L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x3c000000L -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK__CI__VI 0x40000000L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x0000000fL -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK__CI__VI 0x00000040L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x00000080L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK__CI__VI 0x00000400L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK__CI__VI 0x00001000L -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK__CI__VI 0x00000800L -#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK__CI__VI 0x00004000L -#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK__CI__VI 0x00002000L -#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK__CI__VI 0x02000000L -#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK__CI__VI 0x01ff8000L -#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK__CI__VI 0x08000000L -#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK__CI__VI 0x04000000L -#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK__CI__VI 0x20000000L -#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK__CI__VI 0x10000000L -#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK__CI__VI 0x80000000L -#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK__CI__VI 0x40000000L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x0000f000L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x000f0000L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x01f00000L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x3e000000L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK__CI__VI 0x00000800L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK__CI__VI 0x00000400L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK__CI__VI 0x00000008L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK__CI__VI 0x00000004L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK__CI__VI 0x00000080L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK__CI__VI 0x00000040L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK__CI__VI 0x00000001L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK__CI__VI 0x00003c00L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x0003c000L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK__CI__VI 0x007c0000L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x0f800000L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x0000000fL -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK__CI__VI 0xf0000000L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x000000f0L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x00000100L -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x00000200L -#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x0000000fL -#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK__CI__VI 0x00000010L -#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x00000020L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK__CI 0x00000100L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK__CI 0x00000800L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK__CI 0x00000200L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK__CI 0x00000400L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK__CI 0x00001000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK__CI 0x00008000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK__CI 0x00002000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK__CI 0x00004000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK__CI 0x00000010L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK__CI 0x00000080L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK__CI 0x00000020L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK__CI 0x00000040L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK__CI 0x00000008L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK__CI 0x00000008L -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK__CI 0x00000008L -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK__CI 0x00000008L -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK__CI 0x00000008L -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK__CI 0x00000008L -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK__CI 0x00000008L -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK__CI 0x00000008L -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK__CI 0x00000008L -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK__CI 0x00000008L -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK__CI 0x00000008L -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK__CI 0x00000008L -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK__CI 0x00000008L -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK__CI 0x00000008L -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK__CI 0x00000008L -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK__CI 0x00000008L -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK__CI__VI 0x00000007L -#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK__CI__VI 0x00000002L -#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK__CI__VI 0x00000001L -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK__CI__VI 0x00000008L -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK__CI__VI 0x00000004L -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK__CI__VI 0x00000020L -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK__CI__VI 0x00000010L -#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK__CI__VI 0x00000040L -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK__CI__VI 0x00000300L -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK__CI__VI 0x0000fc00L -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK__CI__VI 0x00000080L -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK__CI 0x00000008L -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK__CI__VI 0x00000070L -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK__CI__VI 0x00000007L -#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK__CI__VI 0x00000001L -#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK__CI__VI 0x0000003eL -#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK__CI__VI 0x00000f00L -#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK__CI__VI 0x00800000L -#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK__CI__VI 0x00000080L -#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK__CI__VI 0x00200000L -#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK__CI__VI 0x00400000L -#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK__CI__VI 0x00100000L -#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK__CI__VI 0x0000003fL -#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK__CI__VI 0xff000000L -#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK__CI__VI 0x00010000L -#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK__CI__VI 0x00000100L -#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK__CI__VI 0x000000ffL -#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK__CI__VI 0x00f00000L -#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK__CI__VI 0x000e0000L -#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK__CI__VI 0x0000ffffL -#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK__CI__VI 0x000000ffL -#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK__CI__VI 0x00010000L -#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK__CI__VI 0x0000ff00L -#define PB1_GLB_CTRL_REG0__BACKUP_MASK__CI__VI 0x0000ffffL -#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK__CI__VI 0x00030000L -#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK__CI__VI 0x00700000L -#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK__CI__VI 0x00800000L -#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK__CI__VI 0x01000000L -#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK__CI__VI 0x02000000L -#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK__CI__VI 0x04000000L -#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK__CI__VI 0xc0000000L -#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK__CI__VI 0x80000000L -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK__CI__VI 0x00000001L -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK__CI__VI 0x0000007eL -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK__CI__VI 0x00000080L -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK__CI__VI 0x00003f00L -#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK__CI__VI 0x00004000L -#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK__CI__VI 0x003f8000L -#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK__CI__VI 0x00400000L -#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK__CI__VI 0x3f800000L -#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK__CI__VI 0x40000000L -#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK__CI__VI 0x00000001L -#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK__CI__VI 0x000000feL -#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK__CI__VI 0x00000100L -#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK__CI__VI 0x0000fe00L -#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK__CI__VI 0x00010000L -#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK__CI__VI 0x00fe0000L -#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK__CI__VI 0x01000000L -#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK__CI__VI 0xfe000000L -#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK__CI__VI 0x00000060L -#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK__CI__VI 0x00000180L -#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK__CI__VI 0x00000600L -#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK__CI__VI 0x0001c000L -#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK__CI__VI 0x00001000L -#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK__CI__VI 0x00000800L -#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK__CI__VI 0x001c0000L -#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK__CI__VI 0x80000000L -#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK__CI__VI 0x00400000L -#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK__CI__VI 0x07800000L -#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK__CI__VI 0x08000000L -#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK__CI__VI 0x70000000L -#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK__CI__VI 0x00200000L -#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK__CI__VI 0x0000001fL -#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK__CI__VI 0x03c00000L -#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK__CI__VI 0x0000ffffL -#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK__CI__VI 0x00040000L -#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK__CI__VI 0x00030000L -#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK__CI__VI 0x04000000L -#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK__CI__VI 0x10000000L -#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK__CI__VI 0x08000000L -#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK__CI__VI 0x000000ffL -#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK__CI__VI 0x0000ffffL -#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK__CI__VI 0xffff0000L -#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK__CI__VI 0x00008000L -#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK__CI__VI 0xffff0000L -#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK__CI__VI 0x00000004L -#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK__CI__VI 0x00000008L -#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK__CI__VI 0x00000001L -#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK__CI__VI 0x00000001L -#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK__CI__VI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK__CI 0x00000008L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK__CI 0x00000010L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK__CI__VI 0x00100000L -#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK__CI__VI 0x000f0000L -#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK__CI__VI 0x00000f00L -#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK__CI__VI 0x0000f000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK__CI__VI 0x00001000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK__CI__VI 0x00002000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK__CI__VI 0x00004000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK__CI__VI 0x00008000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK__CI__VI 0x000c0000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK__CI__VI 0x00c00000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK__CI__VI 0x0c000000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK__CI__VI 0xc0000000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK__CI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK__CI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK__CI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK__CI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK__CI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK__CI 0x30000000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK__CI__VI 0x00001000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK__CI__VI 0x00002000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK__CI__VI 0x00004000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK__CI__VI 0x00008000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK__CI__VI 0x000c0000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK__CI__VI 0x00c00000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK__CI__VI 0x0c000000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK__CI__VI 0xc0000000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK__CI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK__CI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK__CI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK__CI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK__CI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK__CI 0x30000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK__CI__VI 0x00004000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK__CI__VI 0x00008000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK__CI__VI 0x00001000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK__CI__VI 0x00002000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK__CI__VI 0x0c000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK__CI__VI 0xc0000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK__CI__VI 0x000c0000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK__CI__VI 0x00c00000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK__CI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK__CI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK__CI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK__CI 0x30000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK__CI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK__CI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK__CI__VI 0x00001000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK__CI__VI 0x00002000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK__CI__VI 0x00004000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK__CI__VI 0x00008000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK__CI__VI 0x000c0000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK__CI__VI 0x00c00000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK__CI__VI 0x0c000000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK__CI__VI 0xc0000000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK__CI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK__CI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK__CI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK__CI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK__CI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK__CI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK__CI 0x30000000L -#define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK__CI 0x00000001L -#define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK__CI 0x00000002L -#define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK__CI 0x00000004L -#define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK__CI 0x00000008L -#define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK__CI 0x00000010L -#define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK__CI 0x00000020L -#define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK__CI 0x00000040L -#define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK__CI 0x00000080L -#define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK__CI 0x00000100L -#define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK__CI 0x00000200L -#define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK__CI 0x00000400L -#define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK__CI 0x00000800L -#define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK__CI 0x00001000L -#define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK__CI 0x00002000L -#define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK__CI 0x00004000L -#define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK__CI 0x00008000L -#define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK__CI 0x00010000L -#define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK__CI 0x00020000L -#define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK__CI 0x00040000L -#define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK__CI 0x00080000L -#define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK__CI 0x00100000L -#define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK__CI 0x00200000L -#define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK__CI 0x00400000L -#define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK__CI 0x00800000L -#define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK__CI 0x01000000L -#define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK__CI 0x02000000L -#define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK__CI 0x04000000L -#define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK__CI 0x08000000L -#define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK__CI 0x10000000L -#define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK__CI 0x20000000L -#define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK__CI 0x40000000L -#define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK__CI 0x80000000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK__CI 0x00000080L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK__CI 0x00000100L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK__CI 0x00040000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK__CI 0x00080000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK__CI 0x00100000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK__CI 0x00200000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK__CI 0x00400000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK__CI 0x00800000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK__CI 0x00000200L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK__CI 0x00000400L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK__CI 0x00000800L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK__CI 0x00001000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK__CI 0x00002000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK__CI 0x00004000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK__CI 0x00008000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK__CI 0x00010000L -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK__CI 0x00020000L -#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK__CI 0x00000006L -#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK__CI 0x07000000L -#define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK__CI 0x00000002L -#define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK__CI 0x00000020L -#define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK__CI 0x00000200L -#define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK__CI 0x00002000L -#define PB1_PIF_CNTL__DIVINIT_MODE_MASK__CI 0x00000100L -#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK__CI 0x00700000L -#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK__CI 0x00000010L -#define PB1_PIF_CNTL__ENABLE_CT_TRIGGER_CLKEN_FIX_MASK__CI 0x40000000L -#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK__CI 0x00800000L -#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK__CI 0x10000000L -#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK__CI 0x20000000L -#define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK__CI 0x000e0000L -#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK__CI 0x00000008L -#define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK__CI 0x00000004L -#define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK__CI 0x00000400L -#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK__CI 0x00000040L -#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK__CI 0x00000080L -#define PB1_PIF_CNTL__RXEN_GATER_MASK__CI 0x0f000000L -#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK__CI 0x00000800L -#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK__CI 0x00000001L -#define PB1_PIF_CNTL__TXGND_TIME_MASK__CI 0x00010000L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK__CI 0x00000001L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK__CI 0x00000002L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK__CI 0x00000004L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK__CI 0x00000008L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK__CI 0x00000010L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK__CI 0x00000020L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK__CI 0x00000040L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK__CI 0x00000080L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK__CI 0x00000100L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK__CI 0x00000200L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK__CI 0x00000400L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK__CI 0x00000800L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK__CI 0x00001000L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK__CI 0x00002000L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK__CI 0x00004000L -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK__CI 0x00008000L -#define PB1_PIF_PAIRING__MULTI_PIF_MASK__CI 0x02000000L -#define PB1_PIF_PAIRING__X16_LANE_15_0_MASK__CI 0x00100000L -#define PB1_PIF_PAIRING__X2_LANE_11_10_MASK__CI 0x00000020L -#define PB1_PIF_PAIRING__X2_LANE_13_12_MASK__CI 0x00000040L -#define PB1_PIF_PAIRING__X2_LANE_15_14_MASK__CI 0x00000080L -#define PB1_PIF_PAIRING__X2_LANE_1_0_MASK__CI 0x00000001L -#define PB1_PIF_PAIRING__X2_LANE_3_2_MASK__CI 0x00000002L -#define PB1_PIF_PAIRING__X2_LANE_5_4_MASK__CI 0x00000004L -#define PB1_PIF_PAIRING__X2_LANE_7_6_MASK__CI 0x00000008L -#define PB1_PIF_PAIRING__X2_LANE_9_8_MASK__CI 0x00000010L -#define PB1_PIF_PAIRING__X4_LANE_11_8_MASK__CI 0x00000400L -#define PB1_PIF_PAIRING__X4_LANE_15_12_MASK__CI 0x00000800L -#define PB1_PIF_PAIRING__X4_LANE_3_0_MASK__CI 0x00000100L -#define PB1_PIF_PAIRING__X4_LANE_7_4_MASK__CI 0x00000200L -#define PB1_PIF_PAIRING__X8_LANE_15_8_MASK__CI 0x00020000L -#define PB1_PIF_PAIRING__X8_LANE_7_0_MASK__CI 0x00010000L -#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK__CI 0x0000000eL -#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK__CI 0x00000100L -#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK__CI 0x00000200L -#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK__CI 0x00004000L -#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK__CI 0x00038000L -#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK__CI 0x00000010L -#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK__CI 0x000000e0L -#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK__CI 0x00000400L -#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK__CI 0x00003800L -#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK__CI 0x00000001L -#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK__CI 0x0000000eL -#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK__CI 0x00000008L -#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK__CI 0x10000000L -#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK__CI 0xe0000000L -#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK__CI 0x00001c00L -#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK__CI 0x00000380L -#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK__CI 0x07000000L -#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK__CI 0x00000070L -#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK__CI 0x00010000L -#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK__CI 0x00000007L -#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK__CI 0x00000008L -#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK__CI 0x10000000L -#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK__CI 0xe0000000L -#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK__CI 0x00001c00L -#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK__CI 0x00000380L -#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK__CI 0x07000000L -#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK__CI 0x00000070L -#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK__CI 0x00010000L -#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK__CI 0x00000007L -#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK__CI 0x00000008L -#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK__CI 0x10000000L -#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK__CI 0xe0000000L -#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK__CI 0x00001c00L -#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK__CI 0x00000380L -#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK__CI 0x07000000L -#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK__CI 0x00000070L -#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK__CI 0x00010000L -#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK__CI 0x00000007L -#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK__CI 0x00000008L -#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK__CI 0x10000000L -#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK__CI 0xe0000000L -#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK__CI 0x00001c00L -#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK__CI 0x00000380L -#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK__CI 0x07000000L -#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK__CI 0x00000070L -#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK__CI 0x00010000L -#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK__CI 0x00000007L -#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK__CI__VI 0xffffffffL -#define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK__CI 0x00000001L -#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK__CI 0x00000010L -#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK__CI 0x00000020L -#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK__CI 0x00000004L -#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK__CI 0x00000008L -#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK__CI 0x00010000L -#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK__CI 0x04000000L -#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK__CI 0x08000000L -#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK__CI 0x10000000L -#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK__CI 0x20000000L -#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK__CI 0x40000000L -#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK__CI 0x80000000L -#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK__CI 0x00020000L -#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK__CI 0x00040000L -#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK__CI 0x00080000L -#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK__CI 0x00100000L -#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK__CI 0x00200000L -#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK__CI 0x00400000L -#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK__CI 0x00800000L -#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK__CI 0x01000000L -#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK__CI 0x02000000L -#define PB1_PIF_SC_CTL__SC_PHASE_1_MASK__CI 0x00000100L -#define PB1_PIF_SC_CTL__SC_PHASE_2_MASK__CI 0x00000200L -#define PB1_PIF_SC_CTL__SC_PHASE_3_MASK__CI 0x00000400L -#define PB1_PIF_SC_CTL__SC_PHASE_4_MASK__CI 0x00000800L -#define PB1_PIF_SC_CTL__SC_PHASE_5_MASK__CI 0x00001000L -#define PB1_PIF_SC_CTL__SC_PHASE_6_MASK__CI 0x00002000L -#define PB1_PIF_SC_CTL__SC_PHASE_7_MASK__CI 0x00004000L -#define PB1_PIF_SC_CTL__SC_PHASE_8_MASK__CI 0x00008000L -#define PB1_PIF_SC_CTL__SC_RXDETECT_MASK__CI 0x00000002L -#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK__CI 0x00000040L -#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK__CI 0x00000001L -#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK__CI 0x00000010L -#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK__CI 0x00000020L -#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK__CI 0x00000004L -#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK__CI 0x00000008L -#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK__CI 0x00000700L -#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK__CI 0x00000002L -#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK__CI 0x00000040L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK__CI 0x00000001L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK__CI 0x00000400L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK__CI 0x00000800L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK__CI 0x00001000L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK__CI 0x00002000L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK__CI 0x00004000L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK__CI 0x00008000L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK__CI 0x00000002L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK__CI 0x00000004L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK__CI 0x00000008L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK__CI 0x00000010L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK__CI 0x00000020L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK__CI 0x00000040L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK__CI 0x00000080L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK__CI 0x00000100L -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK__CI 0x00000200L -#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK__CI__VI 0x00000003L -#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK__CI__VI 0x00000004L -#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK__CI__VI 0x00000008L -#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK__CI__VI 0x00000010L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK__CI__VI 0x00000008L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x00000007L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK__CI__VI 0x00000080L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK__CI__VI 0x00000070L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK__CI__VI 0x00000200L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK__CI__VI 0x00000100L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK__CI__VI 0x00040000L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK__CI__VI 0x0003fc00L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK__CI__VI 0x10000000L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x0ff80000L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK__CI__VI 0x80000000L -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK__CI__VI 0x60000000L -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK__CI__VI 0x00000008L -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK__CI__VI 0x00000007L -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK__CI__VI 0x00040000L -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK__CI__VI 0x0003c000L -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK__CI__VI 0x00000020L -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000010L -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK__CI__VI 0x00000080L -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000040L -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK__CI__VI 0x00000200L -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00000100L -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK__CI__VI 0x00000003L -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK__CI__VI 0x00000004L -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK__CI__VI 0x000007f0L -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK__CI__VI 0x00000008L -#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK__CI__VI 0x00000800L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK__CI__VI 0x00000100L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x000000ffL -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK__CI__VI 0x00001000L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK__CI__VI 0x00000e00L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK__CI__VI 0x00004000L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK__CI__VI 0x00002000L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK__CI__VI 0x10000000L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK__CI__VI 0x0fff8000L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK__CI__VI 0x80000000L -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK__CI__VI 0x40000000L -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK__CI__VI 0x00400000L -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK__CI__VI 0x00380000L -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK__CI__VI 0x00000020L -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK__CI__VI 0x0000001fL -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK__CI__VI 0x00000100L -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK__CI__VI 0x000000c0L -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK__CI__VI 0x00000400L -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000200L -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK__CI__VI 0x00001000L -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK__CI__VI 0x00000800L -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK__CI__VI 0x00004000L -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00002000L -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK__CI 0x00000300L -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK__CI 0x00000002L -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK__CI 0x00000001L -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK__CI__VI 0x00000070L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00000200L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00000400L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00000800L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK__CI 0x00100000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK__CI 0x00200000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00001000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00002000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00004000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK__CI 0x00400000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK__CI 0x00800000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x00000100L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00000002L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00000004L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00000008L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK__CI 0x00010000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK__CI 0x00020000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK__CI__VI 0x00000010L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK__CI__VI 0x00000020L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00000040L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK__CI 0x00040000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK__CI 0x00080000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x00000080L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK__CI__VI 0x00000001L -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK__CI__VI 0x000003ffL -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK__CI__VI 0x000ffc00L -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK__CI__VI 0x3ff00000L -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK__CI 0xc0000000L -#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK__CI__VI 0xc0000000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK__CI__VI 0x0000000fL -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK__CI__VI 0x000000f0L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK__CI__VI 0x00000f00L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK__CI__VI 0x0000f000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK__CI__VI 0x000f0000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK__CI__VI 0x00f00000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK__CI__VI 0x01000000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK__CI__VI 0x02000000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK__CI__VI 0x04000000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK__CI__VI 0x08000000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK__CI__VI 0x10000000L -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK__CI__VI 0x20000000L -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK__CI__VI 0x0000f000L -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK__CI__VI 0x000f0000L -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK__CI__VI 0x00f00000L -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK__CI__VI 0x03000000L -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK__CI__VI 0x0c000000L -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK__CI__VI 0x30000000L -#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK__CI__VI 0xc0000000L -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK__CI__VI 0x00000001L -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK__CI__VI 0x00000002L -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK__CI__VI 0x00000004L -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK__CI__VI 0x00f00000L -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK__CI__VI 0x0f000000L -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK__CI__VI 0xf0000000L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK__CI__VI 0x00000007L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK__CI__VI 0x00000038L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK__CI__VI 0x000001c0L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK__CI__VI 0x00f00000L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK__CI__VI 0x0f000000L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK__CI__VI 0xf0000000L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK__CI__VI 0x00000e00L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK__CI__VI 0x00007000L -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK__CI__VI 0x00038000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK__CI__VI 0x0000001fL -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK__CI__VI 0x000003e0L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK__CI__VI 0x00007c00L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK__CI__VI 0x00008000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK__CI__VI 0x00010000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK__CI__VI 0x00020000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK__CI__VI 0x00040000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK__CI__VI 0x00080000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK__CI__VI 0x00100000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK__CI__VI 0x08000000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK__CI__VI 0x10000000L -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK__CI__VI 0x20000000L -#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK__CI__VI 0x40000000L -#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x08000000L -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK__CI__VI 0x0000000fL -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK__CI__VI 0x000000f0L -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK__CI__VI 0x00000f00L -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK__CI__VI 0x0000f000L -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK__CI__VI 0x000f0000L -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK__CI__VI 0x00f00000L -#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK__CI__VI 0x01000000L -#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK__CI__VI 0x04000000L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK__CI__VI 0x001c0000L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK__CI__VI 0x00e00000L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK__CI__VI 0x07000000L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK__CI__VI 0x08000000L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK__CI__VI 0x10000000L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK__CI__VI 0x20000000L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK__CI__VI 0x0000000fL -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK__CI__VI 0x000000f0L -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK__CI__VI 0x00000f00L -#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK__CI__VI 0x00001000L -#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK__CI__VI 0x00002000L -#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK__CI 0x00020000L -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK__CI__VI 0x80000000L -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK__CI__VI 0x40000000L -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK__CI__VI 0x00000001L -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK__CI__VI 0x00000008L -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK__CI__VI 0x00000004L -#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK__CI__VI 0x20000000L -#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK__CI__VI 0x10000000L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK__CI__VI 0x00000100L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK__CI__VI 0x000000c0L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK__CI__VI 0x00000400L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK__CI__VI 0x00000200L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK__CI__VI 0x00001000L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK__CI__VI 0x00000800L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK__CI__VI 0x00004000L -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK__CI__VI 0x00002000L -#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK__CI__VI 0x00010000L -#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK__CI__VI 0x00008000L -#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK__CI__VI 0x00040000L -#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK__CI__VI 0x00020000L -#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK__CI__VI 0x00100000L -#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK__CI__VI 0x00080000L -#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK__CI__VI 0x00400000L -#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK__CI__VI 0x00200000L -#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK__CI__VI 0x01000000L -#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK__CI__VI 0x00800000L -#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK__CI__VI 0x00000001L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK__CI 0x00000010L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK__CI 0x00000080L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK__CI 0x00000020L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK__CI 0x00000040L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK__CI 0x00001000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK__CI 0x00008000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK__CI 0x00002000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK__CI 0x00004000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK__CI 0x00010000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK__CI 0x00080000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK__CI 0x00020000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK__CI 0x00040000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK__CI 0x00100000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK__CI 0x00800000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK__CI 0x00200000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK__CI 0x00400000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK__CI 0x00000100L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK__CI 0x00000800L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK__CI 0x00000200L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK__CI 0x00000400L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK__CI 0x00000008L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK__CI 0x00000070L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK__CI 0x00000070L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK__CI 0x00000070L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK__CI 0x00000070L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK__CI 0x00000070L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK__CI 0x00000070L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK__CI 0x00000070L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK__CI 0x00000070L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK__CI 0x00000070L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK__CI 0x00000070L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK__CI 0x00000070L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK__CI 0x00000070L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK__CI 0x00000070L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK__CI 0x00000070L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK__CI 0x00000070L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK__CI__VI 0x00000007L -#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK__CI__VI 0x000000ffL -#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK__CI__VI 0x00002000L -#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK__CI__VI 0x00000c00L -#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK__CI__VI 0x00001000L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK__CI__VI 0x00000008L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK__CI__VI 0x00000080L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK__CI__VI 0x00000100L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK__CI__VI 0x00000200L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK__CI 0x00000070L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK__CI__VI 0x00000007L -#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK__CI__VI 0x00000060L -#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK__CI__VI 0x00008000L -#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK__CI__VI 0x01e00000L -#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK__CI__VI 0x00100000L -#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK__CI__VI 0x00000008L -#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK__CI__VI 0x00000004L -#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK__CI__VI 0x000f0000L -#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK__CI__VI 0x00004000L -#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK__CI__VI 0x00000002L -#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK__CI__VI 0x00000f80L -#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK__CI__VI 0x00001000L -#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK__CI__VI 0x00002000L -#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK__CI__VI 0x00000002L -#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK__CI__VI 0x00000004L -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK__CI__VI 0x0000000eL -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK__CI__VI 0x00001ff0L -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK__CI__VI 0x00ff0000L -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK__CI__VI 0x00008000L -#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK__CI__VI 0x01000000L -#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK__CI__VI 0x00002000L -#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK__CI__VI 0x00000300L -#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK__CI__VI 0x00000c00L -#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK__CI__VI 0x00000040L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK__CI__VI 0x0000f000L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK__CI__VI 0x00000020L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK__CI__VI 0x000f0000L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK__CI__VI 0x00000080L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK__CI__VI 0x00f00000L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK__CI__VI 0x0f000000L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK__CI__VI 0x80000000L -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK__CI__VI 0x0000001eL -#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK__CI__VI 0x70000000L -#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK__CI__VI 0x00000060L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK__CI__VI 0x01ff8000L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK__CI__VI 0x00007800L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK__CI__VI 0x00000002L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK__CI__VI 0x1e000000L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK__CI__VI 0x60000000L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK__CI__VI 0x00000080L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK__CI__VI 0x00000700L -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK__CI__VI 0x80000000L -#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK__CI__VI 0x0000001cL -#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK__CI__VI 0x20000000L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK__CI__VI 0x0000001eL -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK__CI__VI 0x000001e0L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK__CI__VI 0x00003e00L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK__CI__VI 0x0007c000L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK__CI__VI 0x00780000L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK__CI__VI 0x07800000L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK__CI__VI 0x08000000L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK__CI__VI 0x10000000L -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK__CI__VI 0x40000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK__CI__VI 0x00000001L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK__CI__VI 0x00000400L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK__CI__VI 0x00000800L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK__CI__VI 0x00001000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK__CI__VI 0x00002000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK__CI__VI 0x00004000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK__CI__VI 0x00008000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK__CI__VI 0x00010000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK__CI__VI 0x00020000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK__CI__VI 0x00040000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK__CI__VI 0x00080000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK__CI__VI 0x00000002L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK__CI__VI 0x00100000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK__CI__VI 0x00200000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK__CI__VI 0x00400000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK__CI__VI 0x00800000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK__CI__VI 0x01000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK__CI__VI 0x02000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK__CI__VI 0x04000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK__CI__VI 0x08000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK__CI__VI 0x10000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK__CI__VI 0x20000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK__CI__VI 0x00000004L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK__CI__VI 0x40000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK__CI__VI 0x80000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK__CI__VI 0x00000008L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK__CI__VI 0x00000040L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK__CI__VI 0x00000080L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK__CI__VI 0x00000001L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK__CI__VI 0x00000002L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK__CI__VI 0x00000004L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK__CI__VI 0x00000008L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK__CI__VI 0x00000040L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK__CI__VI 0x00000080L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK__CI__VI 0x00000400L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK__CI__VI 0x00000800L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK__CI__VI 0x00001000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK__CI__VI 0x00002000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK__CI__VI 0x00004000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK__CI__VI 0x00008000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK__CI__VI 0x00010000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK__CI__VI 0x00020000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK__CI__VI 0x00040000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK__CI__VI 0x00080000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK__CI__VI 0x00100000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK__CI__VI 0x00200000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK__CI__VI 0x00400000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK__CI__VI 0x00800000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK__CI__VI 0x01000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK__CI__VI 0x02000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK__CI__VI 0x04000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK__CI__VI 0x08000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK__CI__VI 0x10000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK__CI__VI 0x20000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK__CI__VI 0x40000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK__CI__VI 0x80000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK__CI__VI 0x00000001L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK__CI__VI 0x00000002L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK__CI__VI 0x00000004L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK__CI__VI 0x00000008L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK__CI__VI 0x00000040L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK__CI__VI 0x00000080L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK__CI__VI 0x00000400L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK__CI__VI 0x00000800L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK__CI__VI 0x00001000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK__CI__VI 0x00002000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK__CI__VI 0x00004000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK__CI__VI 0x00008000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK__CI__VI 0x00010000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK__CI__VI 0x00020000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK__CI__VI 0x00040000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK__CI__VI 0x00080000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK__CI__VI 0x00100000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK__CI__VI 0x00200000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK__CI__VI 0x00400000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK__CI__VI 0x00800000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK__CI__VI 0x01000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK__CI__VI 0x02000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK__CI__VI 0x04000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK__CI__VI 0x08000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK__CI__VI 0x10000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK__CI__VI 0x20000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK__CI__VI 0x40000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK__CI__VI 0x80000000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK__CI__VI 0x00000040L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK__CI__VI 0x00000080L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK__CI__VI 0x00000400L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK__CI__VI 0x00000800L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK__CI__VI 0x00001000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK__CI__VI 0x00002000L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK__CI__VI 0x00000001L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK__CI__VI 0x00000002L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK__CI__VI 0x00000004L -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK__CI__VI 0x00000008L -#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK__CI__VI 0x00000700L -#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK__CI__VI 0x00003800L -#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK__CI__VI 0x0001c000L -#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK__CI__VI 0x00400000L -#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK__CI__VI 0x00200000L -#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK__CI__VI 0x00080000L -#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK__CI__VI 0x00800000L -#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK__CI__VI 0x00000007L -#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK__CI__VI 0x00000038L -#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK__CI 0x01000000L -#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK__CI__VI 0x00100000L -#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK__CI__VI 0x00060000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK__CI__VI 0x40000000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK__CI__VI 0x00000001L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK__CI__VI 0x00000400L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK__CI__VI 0x00000800L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK__CI__VI 0x00001000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK__CI__VI 0x00002000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK__CI__VI 0x00004000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK__CI__VI 0x00008000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK__CI__VI 0x00000002L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK__CI__VI 0x00000004L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK__CI__VI 0x00000008L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK__CI__VI 0x00000040L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK__CI__VI 0x00000080L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK__CI__VI 0x00010000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK__CI__VI 0x00200000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK__CI__VI 0x00400000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK__CI__VI 0x00800000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK__CI__VI 0x00020000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK__CI__VI 0x00040000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK__CI__VI 0x00080000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK__CI__VI 0x00100000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK__CI__VI 0x01000000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK__CI__VI 0x08000000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK__CI__VI 0x02000000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK__CI__VI 0x04000000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK__CI__VI 0x10000000L -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK__CI__VI 0x20000000L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK__CI__VI 0x00000008L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK__CI__VI 0x00000007L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x000000f0L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x00001e00L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK__CI__VI 0x00002000L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x0007c000L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK__CI__VI 0x00080000L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x01f00000L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK__CI__VI 0x02000000L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x3c000000L -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK__CI__VI 0x40000000L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x0000000fL -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK__CI__VI 0x00000040L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK__CI__VI 0x00000080L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK__CI__VI 0x00000400L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK__CI__VI 0x00001000L -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK__CI__VI 0x00000800L -#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK__CI__VI 0x00004000L -#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK__CI__VI 0x00002000L -#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK__CI__VI 0x02000000L -#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK__CI__VI 0x01ff8000L -#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK__CI__VI 0x08000000L -#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK__CI__VI 0x04000000L -#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK__CI__VI 0x20000000L -#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK__CI__VI 0x10000000L -#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK__CI__VI 0x80000000L -#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK__CI__VI 0x40000000L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x0000f000L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x000f0000L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x01f00000L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x3e000000L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK__CI__VI 0x00000800L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK__CI__VI 0x00000400L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK__CI__VI 0x00000008L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK__CI__VI 0x00000004L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK__CI__VI 0x00000080L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK__CI__VI 0x00000040L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK__CI__VI 0x00000002L -#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK__CI__VI 0x00000001L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK__CI__VI 0x00003c00L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x0003c000L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK__CI__VI 0x007c0000L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x0f800000L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x0000000fL -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK__CI__VI 0xf0000000L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x000000f0L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK__CI__VI 0x00000100L -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK__CI__VI 0x00000200L -#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x0000000fL -#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK__CI__VI 0x00000010L -#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK__CI__VI 0x00000020L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK__CI 0x00000100L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK__CI 0x00000800L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK__CI 0x00000200L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK__CI 0x00000400L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK__CI 0x00001000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK__CI 0x00008000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK__CI 0x00002000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK__CI 0x00004000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK__CI 0x00000010L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK__CI 0x00000080L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK__CI 0x00000020L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK__CI 0x00000040L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK__CI 0x00000001L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK__CI 0x00000008L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK__CI 0x00000002L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK__CI 0x00000004L -#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK__CI 0x00000008L -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK__CI 0x00000008L -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK__CI 0x00000008L -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK__CI 0x00000008L -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK__CI 0x00000008L -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK__CI 0x00000008L -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK__CI 0x00000008L -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK__CI 0x00000008L -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK__CI 0x00000008L -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK__CI 0x00000008L -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK__CI 0x00000008L -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK__CI 0x00000008L -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK__CI 0x00000008L -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK__CI 0x00000008L -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK__CI 0x00000008L -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK__CI__VI 0x00000007L -#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK__CI__VI 0x00000002L -#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK__CI__VI 0x00000001L -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK__CI__VI 0x00000008L -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK__CI__VI 0x00000004L -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK__CI__VI 0x00000020L -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK__CI__VI 0x00000010L -#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK__CI__VI 0x00000040L -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK__CI__VI 0x00000300L -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK__CI__VI 0x0000fc00L -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK__CI__VI 0x00000080L -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK__CI 0x00000008L -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK__CI__VI 0x00000070L -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK__CI__VI 0x00000007L -#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK__CI__VI 0xffff0000L -#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK__CI__VI 0x0000ff00L -#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK__CI__VI 0x00000001L -#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L -#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK__CI__VI 0x00030000L -#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK__CI__VI 0x001c0000L -#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_NS_MASK__SI 0x007f0000L -#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007f00L -#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L -#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L -#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L -#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L -#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK__CI__VI 0x00000010L -#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK__CI__VI 0x00000040L -#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK__SI 0x00000010L -#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L -#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffffL -#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffffL -#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L -#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L -#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L -#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L -#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L -#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L -#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000cL -#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L -#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L -#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000c0L -#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L -#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK__CI__VI 0x00000002L -#define PCIEP_STRAP_MISC__STRAP_EXIT_LATENCY_MASK__SI 0x0000000fL -#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK__CI__VI 0x00000004L -#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK__CI__VI 0x00000020L -#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK__CI__VI 0x00000018L -#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK__CI__VI 0x00000001L -#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK__SI 0x00000010L -#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK__CI__VI 0x00000040L -#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK__CI__VI 0x0000ff00L -#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK__CI__VI 0x00000008L -#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK__CI__VI 0x00000020L -#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK__CI__VI 0x00000004L -#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK__CI__VI 0x00000001L -#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK__CI__VI 0x00000002L -#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK__CI__VI 0x00000010L -#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK__CI__VI 0x00000040L -#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK__CI__VI 0x00000008L -#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK__CI__VI 0x00000020L -#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK__CI__VI 0x00000004L -#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK__CI__VI 0x00000001L -#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK__CI__VI 0x00000002L -#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK__CI__VI 0x00000010L -#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L -#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001fL -#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK__CI__VI 0x00000200L -#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK__CI__VI 0x00000400L -#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK__CI 0x00008000L -#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000ffffL -#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000f0000L -#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000L -#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK__CI__VI 0x0000001fL -#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK__CI__VI 0x00000020L -#define PCIE_ATS_CAP__RR_PROTECTION_FAULT_MASK__CI 0x00000040L -#define PCIE_ATS_CNTL__ATC_ENABLE_MASK__CI__VI 0x00008000L -#define PCIE_ATS_CNTL__STU_MASK__CI__VI 0x0000001fL -#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK__CI__VI 0x00fffff0L -#define PCIE_BAR1_CNTL__BAR_INDEX_MASK__CI__VI 0x00000007L -#define PCIE_BAR1_CNTL__BAR_SIZE_MASK__CI__VI 0x00001f00L -#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK__CI__VI 0x000000e0L -#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK__CI__VI 0x00fffff0L -#define PCIE_BAR2_CNTL__BAR_INDEX_MASK__CI__VI 0x00000007L -#define PCIE_BAR2_CNTL__BAR_SIZE_MASK__CI__VI 0x00001f00L -#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK__CI__VI 0x000000e0L -#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK__CI__VI 0x00fffff0L -#define PCIE_BAR3_CNTL__BAR_INDEX_MASK__CI__VI 0x00000007L -#define PCIE_BAR3_CNTL__BAR_SIZE_MASK__CI__VI 0x00001f00L -#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK__CI__VI 0x000000e0L -#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK__CI__VI 0x00fffff0L -#define PCIE_BAR4_CNTL__BAR_INDEX_MASK__CI__VI 0x00000007L -#define PCIE_BAR4_CNTL__BAR_SIZE_MASK__CI__VI 0x00001f00L -#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK__CI__VI 0x000000e0L -#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK__CI__VI 0x00fffff0L -#define PCIE_BAR5_CNTL__BAR_INDEX_MASK__CI__VI 0x00000007L -#define PCIE_BAR5_CNTL__BAR_SIZE_MASK__CI__VI 0x00001f00L -#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK__CI__VI 0x000000e0L -#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK__CI__VI 0x00fffff0L -#define PCIE_BAR6_CNTL__BAR_INDEX_MASK__CI__VI 0x00000007L -#define PCIE_BAR6_CNTL__BAR_SIZE_MASK__CI__VI 0x00001f00L -#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK__CI__VI 0x000000e0L -#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_BUS_CNTL__BUS_DBL_RESYNC_MASK__SI 0x00000001L -#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L -#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L -#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK__CI__VI 0x00001000L -#define PCIE_B_P90_CNTL__B_P90IMP_BACKUP_MASK__SI 0x0000000fL -#define PCIE_B_P90_CNTL__B_P90PLL_BACKUP_MASK__SI 0xfffff000L -#define PCIE_CAC_DEVICE_CORRELATION__DEVICE_CORRELATION_MASK__SI 0xffffffffL -#define PCIE_CAC_ENH_CAP_LIST__CAP_ID_MASK__SI 0x0000ffffL -#define PCIE_CAC_ENH_CAP_LIST__CAP_VER_MASK__SI 0x000f0000L -#define PCIE_CAC_ENH_CAP_LIST__NEXT_PTR_MASK__SI 0xfff00000L -#define PCIE_CAP_LIST__CAP_ID_MASK 0x000000ffL -#define PCIE_CAP_LIST__NEXT_PTR_MASK 0x0000ff00L -#define PCIE_CAP__DEVICE_TYPE_MASK 0x000000f0L -#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x00003e00L -#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x00000100L -#define PCIE_CAP__TCS_ROUTING_SUPPORTED_MASK__SI 0x00004000L -#define PCIE_CAP__VERSION_MASK 0x0000000fL -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK__CI__VI 0x00000002L -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK__SI 0x00000001L -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK__CI__VI 0x00000004L -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK__CI__VI 0x00000001L -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK__SI 0x00000002L -#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L -#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK__CI__VI 0x00002000L -#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L -#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L -#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L -#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L -#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L -#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK__CI__VI 0x00001000L -#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L -#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000c0L -#define PCIE_CI_CNTL__CI_SLV_REQ_DELAY_EN_MASK__SI 0x01000000L -#define PCIE_CI_CNTL__CI_SLV_REQ_DELAY_TIMER_MASK__SI 0x7e000000L -#define PCIE_CI_CNTL__TX_SLV_CPL_DELAY_EN_MASK__SI 0x00002000L -#define PCIE_CI_CNTL__TX_SLV_CPL_DELAY_TIMER_MASK__SI 0x00ffc000L -#define PCIE_CI_MST_C_RTR_TIMEOUT_CNTL__CI_MST_C_RTR_TIMEOUT_RST_MASK__SI 0x00000001L -#define PCIE_CI_MST_C_RTR_TIMEOUT_CNTL__CI_MST_C_RTR_TIMEOUT_VALUE_MASK__SI 0xfffffff0L -#define PCIE_CI_MST_R_RTR_TIMEOUT_CNTL__CI_MST_R_RTR_TIMEOUT_RST_MASK__SI 0x00000001L -#define PCIE_CI_MST_R_RTR_TIMEOUT_CNTL__CI_MST_R_RTR_TIMEOUT_VALUE_MASK__SI 0xfffffff0L -#define PCIE_CI_SLV_R_RTR_TIMEOUT_CNTL__CI_SLV_R_RTR_TIMEOUT_RST_MASK__SI 0x00000001L -#define PCIE_CI_SLV_R_RTR_TIMEOUT_CNTL__CI_SLV_R_RTR_TIMEOUT_VALUE_MASK__SI 0xfffffff0L -#define PCIE_CNTL2__MST_MEM_LS_EN_MASK__CI__VI 0x00040000L -#define PCIE_CNTL2__MST_MEM_SD_EN_MASK__CI__VI 0x00400000L -#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK__CI__VI 0x00080000L -#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK__CI__VI 0x00800000L -#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK__CI__VI 0x1f000000L -#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK__CI__VI 0x00020000L -#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK__CI__VI 0x00200000L -#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK__CI__VI 0x00010000L -#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK__CI__VI 0x00100000L -#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007c0L -#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L -#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003eL -#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L -#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK__CI__VI 0x0000000eL -#define PCIE_CNTL__LC_PREVENT_SPD_CHG_OVERLAP_MASK__SI 0x00800000L -#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L -#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK__CI__VI 0x00000100L -#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK__CI__VI 0x00800000L -#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L -#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK__CI__VI 0x40000000L -#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK__CI__VI 0x00008000L -#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK__SI__CI 0x00100000L -#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L -#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L -#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L -#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L -#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L -#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L -#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001c00L -#define PCIE_CNTL__RX_SB_COMPLETE_FULL_FIX_MASK__SI 0x00002000L -#define PCIE_CNTL__RX_SB_REJECT_IF_FULL_MASK__SI 0x00004000L -#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000L -#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L -#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK__CI__VI 0x06000000L -#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK__CI__VI 0x00010000L -#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK__CI__VI 0x00100000L -#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK__CI__VI 0x01000000L -#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK__CI__VI 0x000e0000L -#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK__CI__VI 0x00e00000L -#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000fL -#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L -#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L -#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L -#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK__CI__VI 0x00004000L -#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK__CI__VI 0x00008000L -#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L -#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L -#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L -#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L -#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L -#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L -#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK__CI__VI 0x00004000L -#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK__CI__VI 0x00008000L -#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L -#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L -#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L -#define PCIE_DATA_2__PCIE_DATA_MASK__CI__VI 0xffffffffL -#define PCIE_DATA__PCIE_DATA_MASK 0xffffffffL -#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000L -#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0x000000ffL -#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x00000100L -#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffffL -#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffffL -#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000ffffL -#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000f0000L -#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000L -#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK__CI__VI 0x00003000L -#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK__CI__VI 0x0000001fL -#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK__CI__VI 0x00000300L -#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK__CI__VI 0x00ff0000L -#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK__CI__VI 0xff000000L -#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK__CI__VI 0x0000001fL -#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK__CI__VI 0x00000100L -#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK__CI__VI 0x0000001fL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK__CI__VI 0x00000800L -#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK__CI__VI 0x00001000L -#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK__CI__VI 0x00002000L -#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK__CI__VI 0x00000700L -#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK__CI__VI 0x00008000L -#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK__CI__VI 0x00004000L -#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK__CI__VI 0x00010000L -#define PCIE_ERR_CNTL__ERR_GEN_INTERRUPT_MASK__SI 0x00000002L -#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L -#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK__CI__VI 0x00000004L -#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK__CI__VI 0x00000080L -#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK__CI__VI 0x00000020L -#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK__CI__VI 0x00000002L -#define PCIE_ERR_CNTL__SYM_UNLOCKED_EN_MASK__SI 0x00000004L -#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK__CI__VI 0x00000040L -#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK__CI__VI 0x00000010L -#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK__CI__VI 0x00003000L -#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK__CI__VI 0x00000300L -#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK__CI__VI 0x00ff0000L -#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK__CI__VI 0xff000000L -#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK__CI__VI 0x0000001fL -#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK__CI__VI 0x000000ffL -#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000ffL -#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000ff00L -#define PCIE_FC_NP__NPD_CREDITS_MASK 0x000000ffL -#define PCIE_FC_NP__NPH_CREDITS_MASK 0x0000ff00L -#define PCIE_FC_P__PD_CREDITS_MASK 0x000000ffL -#define PCIE_FC_P__PH_CREDITS_MASK 0x0000ff00L -#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffffL -#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffffL -#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffffL -#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffffL -#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_BUS_BLK1_MASK 0x01000000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_BUS_BLK2_MASK 0x02000000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_EN_MASK 0x04000000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_MULTIBLOCK_EN_MASK 0x08000000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_MUX_BLK1_MASK 0x0003f000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_MUX_BLK2_MASK 0x00fc0000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_RESERVE_MASK 0xf0000000L -#define PCIE_I2C_DEBUG_BUS__DEBUG_SEL_BLK1_MASK 0x0000003fL -#define PCIE_I2C_DEBUG_BUS__DEBUG_SEL_BLK2_MASK 0x00000fc0L -#define PCIE_I2C_REG_ADDR_EXPAND__BDI2C_CPLDATA_RTN_EXPAND_MASK__SI 0x001e0000L -#define PCIE_I2C_REG_ADDR_EXPAND__BDREG_CPLDATA_RTN_EXPAND_MASK__SI 0x01e00000L -#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001ffffL -#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffffL -#define PCIE_INDEX_2__PCIE_INDEX_MASK__CI__VI 0xffffffffL -#define PCIE_INDEX__PCIE_INDEX_MASK__CI__VI 0xffffffffL -#define PCIE_INDEX__PCIE_INDEX_MASK__SI 0x000000ffL -#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L -#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L -#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x00000080L -#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L -#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L -#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L -#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK__CI__VI 0x00000100L -#define PCIE_INT_CNTL__SLOT_POWER_CHG_INT_EN_MASK__SI 0x00000020L -#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L -#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L -#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L -#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x00000080L -#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L -#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L -#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L -#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK__CI__VI 0x00000100L -#define PCIE_INT_STATUS__SLOT_POWER_CHG_INT_STATUS_MASK__SI 0x00000020L -#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L -#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00000070L -#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x0000000fL -#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK__CI__VI 0x00008000L -#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK__CI__VI 0x00007000L -#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK__CI__VI 0x00000f00L -#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK__CI__VI 0x0000ffffL -#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK__CI__VI 0xffff0000L -#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L -#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L -#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L -#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L -#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L -#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L -#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L -#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L -#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L -#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L -#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L -#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L -#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000fffL -#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00fff000L -#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L -#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L -#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L -#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L -#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L -#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L -#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L -#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000c000L -#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L -#define PCIE_LC_CNTL2__LC_ENABLE_RX_CR_EN_DEASSERTION_MASK__SI 0x10000000L -#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L -#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L -#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L -#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L -#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L -#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L -#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK__CI__VI 0x10000000L -#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L -#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L -#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L -#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L -#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003fL -#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L -#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L -#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L -#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK__CI__VI 0x00040000L -#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK__CI__VI 0x00180000L -#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK__CI__VI 0x000000c0L -#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK__CI__VI 0x00000100L -#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK__CI__VI 0x00010000L -#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK__CI__VI 0x00000200L -#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L -#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK__CI__VI 0x00800000L -#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK__CI__VI 0x00003000L -#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK__CI__VI 0x0000c000L -#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK__CI__VI 0x00000400L -#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK__CI__VI 0x00200000L -#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK__CI__VI 0x40000000L -#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK__CI__VI 0x03000000L -#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK__CI__VI 0x00020000L -#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK__CI__VI 0x80000000L -#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L -#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK__CI__VI 0x00000800L -#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L -#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK__CI__VI 0x00400000L -#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L -#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L -#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK__CI__VI 0x3c000000L -#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK__CI__VI 0x00000010L -#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK__CI__VI 0x00010000L -#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK__CI__VI 0x00000300L -#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK__CI__VI 0x01000000L -#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK__CI__VI 0x00000040L -#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK__CI__VI 0x00020000L -#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK__CI__VI 0x003c0000L -#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK__CI__VI 0x00000080L -#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK__CI__VI 0x00800000L -#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK__CI__VI 0x00004000L -#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK__CI__VI 0x00000020L -#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK__CI__VI 0x00002000L -#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK__CI__VI 0x00000003L -#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK__CI__VI 0x00008000L -#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK__CI__VI 0x00400000L -#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK__CI__VI 0x00000800L -#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK__CI__VI 0x00001000L -#define PCIE_LC_CNTL4__LC_USC_SET_EQ_VARIABLE_MASK__CI 0x00000400L -#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK__CI__VI 0x0000003fL -#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK__CI__VI 0x00000fc0L -#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK__CI__VI 0x0003f000L -#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK__CI__VI 0x00fc0000L -#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000f0L -#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L -#define PCIE_LC_CNTL__LC_CM_HI_ENABLE_COUNT_MASK__SI 0x00000001L -#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L -#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L -#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L -#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L -#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L -#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L -#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L -#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L -#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L -#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000f00L -#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L -#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000f000L -#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000c0000L -#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L -#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L -#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L -#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L -#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L -#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK__CI__VI 0x00000001L -#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK__CI__VI 0x00001f80L -#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK__CI__VI 0x0007e000L -#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK__CI__VI 0x0000007eL -#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000ffffL -#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK__CI__VI 0x00080000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK__CI__VI 0x00040000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK__CI__VI 0x00600000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK__CI__VI 0x00800000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK__CI__VI 0x00100000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L -#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000L -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00ff0000L -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000ffL -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L -#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK__CI__VI 0x00020000L -#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK__SI 0x00400000L -#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK__CI__VI 0x00400000L -#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK__SI 0x02000000L -#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK__CI__VI 0x04000000L -#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK__SI 0x10000000L -#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK__CI__VI 0x00010000L -#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK__SI 0x00200000L -#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK__CI__VI 0x00006000L -#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK__SI 0x00000800L -#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK__CI__VI 0x03000000L -#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK__SI 0x08000000L -#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK__CI__VI 0x80000000L -#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK__CI__VI 0x40000000L -#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK__CI__VI 0x00008000L -#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK__SI 0x00100000L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK__CI__VI 0x00000100L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK__SI 0x00000040L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK__CI__VI 0x00000040L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK__SI 0x00000010L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK__CI__VI 0x00000080L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK__SI 0x00000020L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK__CI__VI 0x00000020L -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK__SI 0x00000008L -#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L -#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK__CI__VI 0x00000002L -#define PCIE_LC_SPEED_CNTL__LC_GO_TO_RECOVERY_MASK__SI 0x00040000L -#define PCIE_LC_SPEED_CNTL__LC_HW_VOLTAGE_IF_CONTROL_MASK__SI 0x00003000L -#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK__CI__VI 0x00000200L -#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK__SI 0x00000080L -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK__CI__VI 0x10000000L -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK__SI 0x40000000L -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK__CI__VI 0x20000000L -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK__SI 0x80000000L -#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK__CI__VI 0x08000000L -#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK__SI 0x20000000L -#define PCIE_LC_SPEED_CNTL__LC_N_EIE_SEL_MASK__SI 0x00080000L -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK__CI__VI 0x00040000L -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK__SI 0x00800000L -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK__CI__VI 0x00100000L -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK__CI__VI 0x00080000L -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK__SI 0x01000000L -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK__CI__VI 0x00200000L -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK__CI__VI 0x00000c00L -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK__SI 0x00000300L -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK__CI__VI 0x00001000L -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SI 0x00000400L -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK__CI__VI 0x00800000L -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK__SI 0x04000000L -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK__CI__VI 0x00000004L -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK__SI 0x00000002L -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK__CI__VI 0x00000018L -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK__SI 0x00000004L -#define PCIE_LC_SPEED_CNTL__LC_VOLTAGE_TIMER_SEL_MASK__SI 0x0003c000L -#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003fL -#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003f00L -#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003f0000L -#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000L -#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003fL -#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003f00L -#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003f0000L -#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000L -#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003fL -#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003f00L -#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003f0000L -#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000L -#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003fL -#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003f00L -#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003f0000L -#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000L -#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003f0000L -#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000L -#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003fL -#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003f00L -#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003fL -#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003f00L -#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003f0000L -#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000L -#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003fL -#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003f00L -#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003f0000L -#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000L -#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003fL -#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003f00L -#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003f0000L -#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000L -#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003fL -#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003f00L -#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003f0000L -#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000L -#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003fL -#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003f00L -#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003f0000L -#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000L -#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003fL -#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003f00L -#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003f0000L -#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000L -#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003fL -#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003f00L -#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003f0000L -#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000L -#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000e0L -#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001cL -#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L -#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L -#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000ffffL -#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000L -#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK__CI__VI 0x10000000L -#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00c00000L -#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L -#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_1_MASK__SI 0x08000000L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_2_MASK__CI 0x20000000L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_2_MASK__SI 0x10000000L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_3_MASK__CI 0x40000000L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_3_MASK__SI 0x20000000L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_4_MASK__CI 0x80000000L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_4_MASK__SI 0x40000000L -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_5_MASK__SI 0x80000000L -#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK__CI__VI 0x00002000L -#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L -#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L -#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L -#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L -#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK__CI__VI 0x00080000L -#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L -#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L -#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L -#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK__CI__VI 0x00100000L -#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L -#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L -#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L -#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK__CI__VI 0x08000000L -#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L -#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000fL -#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L -#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK__CI__VI 0x00000002L -#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK__CI__VI 0x00000001L -#define PCIE_LINK_CNTL3__RESERVED_MASK__CI__VI 0xfffffffcL -#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK__CI__VI 0xffffffffL -#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK__CI__VI 0xffffffffL -#define PCIE_P90RX_PRBS10_CNTL__P90RX_PRBS10_CLR_MASK__SI 0x0000ffffL -#define PCIE_P90RX_PRBS10_CNTL__P90TX_PRBS10_EN_MASK__SI 0xffff0000L -#define PCIE_P90_BRX_PRBS10_ER__P90_BRX_PRBS10_ER_MASK__SI 0x0000ffffL -#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK__CI__VI 0x00000001L -#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK__CI__VI 0x00000002L -#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK__CI__VI 0x00000001L -#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK__CI__VI 0x00000100L -#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK__CI__VI 0x00000002L -#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK__CI__VI 0x00001f00L -#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK__CI__VI 0x00000002L -#define PCIE_PASID_CAP__PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK__CI 0x00000008L -#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK__CI__VI 0x00000004L -#define PCIE_PASID_CAP__PASID_TLP_PREFIX_SUPPORTED_MASK__CI 0x00000001L -#define PCIE_PASID_CNTL__PASID_ENABLE_MASK__CI__VI 0x00000001L -#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK__CI__VI 0x00000002L -#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK__CI__VI 0x00000004L -#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000f00L -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000f0L -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0f000000L -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000fL -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000f00L -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000f0L -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0f000000L -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000fL -#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L -#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000L -#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000ffL -#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000ff00L -#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L -#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000L -#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000ffL -#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000ff00L -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000L -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000ffL -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000ff00L -#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L -#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000L -#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000ffL -#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000ff00L -#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L -#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000L -#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000ffL -#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000ff00L -#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00ff0000L -#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000L -#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000ffL -#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000ff00L -#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00ff0000L -#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000L -#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000ffL -#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000ff00L -#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffffL -#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffffL -#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffffL -#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffffL -#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffffL -#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffffL -#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffffL -#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffffL -#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffffL -#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffffL -#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffffL -#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffffL -#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffffL -#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffffL -#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L -#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L -#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L -#define PCIE_PERF_LATENCY_CNTL__CFG_IO_REQ_MASK__SI 0x00000800L -#define PCIE_PERF_LATENCY_CNTL__CPL_MODE_MASK__SI 0x00004000L -#define PCIE_PERF_LATENCY_CNTL__MEM_REQ_MASK__SI 0x00000400L -#define PCIE_PERF_LATENCY_CNTL__NO_SNOOP_MASK__SI 0x00000200L -#define PCIE_PERF_LATENCY_CNTL__PORT_MODE_MASK__SI 0x00000080L -#define PCIE_PERF_LATENCY_CNTL__PORT_NUM_MASK__SI 0x00000070L -#define PCIE_PERF_LATENCY_CNTL__REQ_ID_MODE_MASK__SI 0x00001000L -#define PCIE_PERF_LATENCY_CNTL__SNOOP_MASK__SI 0x00000100L -#define PCIE_PERF_LATENCY_CNTL__TAG_MODE_MASK__SI 0x00002000L -#define PCIE_PERF_LATENCY_CNTL__TIMER_EN_MASK__SI 0x00000001L -#define PCIE_PERF_LATENCY_CNTL__TIMER_RESET_MASK__SI 0x00000004L -#define PCIE_PERF_LATENCY_CNTL__TIMER_SHADOW_WR_MASK__SI 0x00000002L -#define PCIE_PERF_LATENCY_CNTL__TRAFFIC_CLASS_MASK__SI 0x00ff0000L -#define PCIE_PERF_LATENCY_COUNTER0__NUM_REQ_MASK__SI 0xffffffffL -#define PCIE_PERF_LATENCY_COUNTER1__NUM_EXCEED_MASK__SI 0xffffffffL -#define PCIE_PERF_LATENCY_MAX__PEAK_MASK__SI 0x0000ffffL -#define PCIE_PERF_LATENCY_MAX__REQUESTER_ID_MASK__SI 0xffff0000L -#define PCIE_PERF_LATENCY_REQ_ID__REQUESTER_ID_MASK__SI 0x0000ffffL -#define PCIE_PERF_LATENCY_REQ_ID__REQUESTER_MASK_MASK__SI 0xffff0000L -#define PCIE_PERF_LATENCY_TAG__TAG_MASK_MASK__SI 0x0000ff00L -#define PCIE_PERF_LATENCY_TAG__TAG_MASK__SI 0x000000ffL -#define PCIE_PERF_LATENCY_THRESHOLD__THRESHOLD_MASK__SI 0x0000ffffL -#define PCIE_PERF_LATENCY_TIMER_HI__TIMER_HI_MASK__SI 0xffffffffL -#define PCIE_PERF_LATENCY_TIMER_LO__TIMER_LO_MASK__SI 0xffffffffL -#define PCIE_PERF_MAS_ACC_END_LO__PERF_MAS_ACC_END_LO_MASK__SI 0xfffffffcL -#define PCIE_PERF_MAS_ACC_START_END_HI__PERF_MAS_ACC_END_HI_MASK__SI 0x0000ff00L -#define PCIE_PERF_MAS_ACC_START_END_HI__PERF_MAS_ACC_START_HI_MASK__SI 0x000000ffL -#define PCIE_PERF_MAS_ACC_START_LO__PERF_MAS_ACC_START_LO_MASK__SI 0xfffffffcL -#define PCIE_PERF_SLV_ACC_HI__PERF_SLV_ACC_HI_MASK__SI 0xffffffffL -#define PCIE_PERF_SLV_ACC_LO__PERF_SLV_ACC_LO_MASK__SI 0xfffffffcL -#define PCIE_PI_RCVL0S_FTS_DET__PI_RCVL0S_FTS_DET_MAX_MASK__SI 0x1fff0000L -#define PCIE_PI_RCVL0S_FTS_DET__PI_RCVL0S_FTS_DET_MIN_MASK__SI 0x00003ffeL -#define PCIE_PI_RCVL0S_FTS_DET__PI_RCVL0S_FTS_DET_RST_MASK__SI 0x00000001L -#define PCIE_PORT_DATA__PCIE_DATA_MASK__SI 0xffffffffL -#define PCIE_PORT_INDEX__PCIE_INDEX_MASK__SI 0x000000ffL -#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L -#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L -#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000c00L -#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L -#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000ffL -#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000L -#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x00000001L -#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x0000000eL -#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x00000001L -#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0x000f0000L -#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000ffffL -#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffffL -#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffffL -#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000ffffL -#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000ffL -#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffffL -#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000L -#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK__CI__VI 0x0000c000L -#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L -#define PCIE_PRBS_MISC__PRBS_GEN2_SPEED_MASK__SI 0x00008000L -#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000ffffL -#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000L -#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000ffffL -#define PCIE_PRBS_USER_PATTERN__PRBS_USER_DEFINE_PATTERN_MASK__SI 0x3fffffffL -#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK__CI__VI 0x3fffffffL -#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK__CI__VI 0x00000001L -#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK__CI__VI 0x000000ffL -#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK__CI__VI 0x000000ffL -#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK__CI__VI 0x00000300L -#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK__CI__VI 0x00006000L -#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK__CI__VI 0x00001c00L -#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK__CI__VI 0x001c0000L -#define PCIE_PWR_BUDGET_DATA__TYPE_MASK__CI__VI 0x00038000L -#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_0_MASK__SI 0x00010000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_10_MASK__SI 0x04000000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_11_MASK__SI 0x08000000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_12_MASK__SI 0x10000000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_13_MASK__SI 0x20000000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_14_MASK__SI 0x40000000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_15_MASK__SI 0x80000000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_1_MASK__SI 0x00020000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_2_MASK__SI 0x00040000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_3_MASK__SI 0x00080000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_4_MASK__SI 0x00100000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_5_MASK__SI 0x00200000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_6_MASK__SI 0x00400000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_7_MASK__SI 0x00800000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_8_MASK__SI 0x01000000L -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_9_MASK__SI 0x02000000L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_0_MASK__SI 0x00000001L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_10_MASK__SI 0x00000400L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_11_MASK__SI 0x00000800L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_12_MASK__SI 0x00001000L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_13_MASK__SI 0x00002000L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_14_MASK__SI 0x00004000L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_15_MASK__SI 0x00008000L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_1_MASK__SI 0x00000002L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_2_MASK__SI 0x00000004L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_3_MASK__SI 0x00000008L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_4_MASK__SI 0x00000010L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_5_MASK__SI 0x00000020L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_6_MASK__SI 0x00000040L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_7_MASK__SI 0x00000080L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_8_MASK__SI 0x00000100L -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_9_MASK__SI 0x00000200L -#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK__CI__VI 0x0000ffffL -#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK__CI__VI 0xffff0000L -#define PCIE_P_CNTL__B_PG2RX_CR_EN_MODE_MASK__SI 0x40000000L -#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK__CI__VI 0x00010000L -#define PCIE_P_CNTL__LC_RXP_DONT_ALIGN_ON_TSx_MASK__SI 0x20000000L -#define PCIE_P_CNTL__PI_RXEN_GATER_MASK__SI 0x0f000000L -#define PCIE_P_CNTL__PI_SYMALIGN_DIS_ELIDLE_MASK__SI 0x00000080L -#define PCIE_P_CNTL__P_ALLOW_PRX_FRONTEND_SHUTOFF_MASK__SI 0x00001000L -#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L -#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK__CI__VI 0x00001000L -#define PCIE_P_CNTL__P_EBUF_SYNC_MODE_MASK__SI 0x00000400L -#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK__CI__VI 0x00000008L -#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000c000L -#define PCIE_P_CNTL__P_ENABLE_PLL_LOCKING_IN_QUICKSIM_MASK__SI 0x00000004L -#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK__CI__VI 0x00000010L -#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK__CI__VI 0x00000040L -#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK__CI__VI 0x00000080L -#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK__CI__VI 0x00000020L -#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK__CI__VI 0x00000100L -#define PCIE_P_CNTL__P_LDSK_MASK_RCVR_ELEC_IDLE_MASK__SI 0x00000800L -#define PCIE_P_CNTL__P_MASK_RCVR_EIDLE_EN_MASK__SI 0x00000100L -#define PCIE_P_CNTL__P_PLL_BUF_PDNB_MASK__SI 0x00000010L -#define PCIE_P_CNTL__P_PLL_PDNB_MASK__SI 0x00000200L -#define PCIE_P_CNTL__P_PLL_PWRDN_IN_L1L23_MASK__SI 0x00000008L -#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L -#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK__CI__VI 0x00000004L -#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L -#define PCIE_P_CNTL__P_TXCLK_RCV_PWRDN_MASK__SI 0x00000040L -#define PCIE_P_CNTL__P_TXCLK_SND_PWRDN_MASK__SI 0x00000020L -#define PCIE_P_CNTL__RXP_NAK_FIX_IN_MODE1_EN_MASK__SI 0x80000000L -#define PCIE_P_CNTL__RXP_REALIGN_ON_EACH_TSX_OR_SKP_MASK__SI 0x10000000L -#define PCIE_P_CNTL__RXP_XBAR_MUX0_MASK__SI 0x00030000L -#define PCIE_P_CNTL__RXP_XBAR_MUX1_MASK__SI 0x000c0000L -#define PCIE_P_CNTL__RXP_XBAR_MUX2_MASK__SI 0x00300000L -#define PCIE_P_CNTL__RXP_XBAR_MUX3_MASK__SI 0x00c00000L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_0_MASK__SI 0x00000001L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_10_MASK__SI 0x00000400L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_11_MASK__SI 0x00000800L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_12_MASK__SI 0x00001000L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_13_MASK__SI 0x00002000L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_14_MASK__SI 0x00004000L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_15_MASK__SI 0x00008000L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_1_MASK__SI 0x00000002L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_2_MASK__SI 0x00000004L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_3_MASK__SI 0x00000008L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_4_MASK__SI 0x00000010L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_5_MASK__SI 0x00000020L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_6_MASK__SI 0x00000040L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_7_MASK__SI 0x00000080L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_8_MASK__SI 0x00000100L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_9_MASK__SI 0x00000200L -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK__CI__VI 0x0000ffffL -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_0_MASK__SI 0x00010000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_10_MASK__SI 0x04000000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_11_MASK__SI 0x08000000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_12_MASK__SI 0x10000000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_13_MASK__SI 0x20000000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_14_MASK__SI 0x40000000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_15_MASK__SI 0x80000000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_1_MASK__SI 0x00020000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_2_MASK__SI 0x00040000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_3_MASK__SI 0x00080000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_4_MASK__SI 0x00100000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_5_MASK__SI 0x00200000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_6_MASK__SI 0x00400000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_7_MASK__SI 0x00800000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_8_MASK__SI 0x01000000L -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_9_MASK__SI 0x02000000L -#define PCIE_P_DECODE_ERR_CNTL__CODE_ERR_CNT_RESET_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNTL__DISPARITY_ERR_CNT_RESET_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_0__CODE_ERR_CNT_0_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_0__DISPARITY_ERR_CNT_0_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_10__CODE_ERR_CNT_10_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_10__DISPARITY_ERR_CNT_10_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_11__CODE_ERR_CNT_11_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_11__DISPARITY_ERR_CNT_11_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_12__CODE_ERR_CNT_12_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_12__DISPARITY_ERR_CNT_12_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_13__CODE_ERR_CNT_13_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_13__DISPARITY_ERR_CNT_13_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_14__CODE_ERR_CNT_14_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_14__DISPARITY_ERR_CNT_14_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_15__CODE_ERR_CNT_15_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_15__DISPARITY_ERR_CNT_15_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_1__CODE_ERR_CNT_1_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_1__DISPARITY_ERR_CNT_1_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_2__CODE_ERR_CNT_2_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_2__DISPARITY_ERR_CNT_2_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_3__CODE_ERR_CNT_3_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_3__DISPARITY_ERR_CNT_3_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_4__CODE_ERR_CNT_4_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_4__DISPARITY_ERR_CNT_4_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_5__CODE_ERR_CNT_5_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_5__DISPARITY_ERR_CNT_5_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_6__CODE_ERR_CNT_6_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_6__DISPARITY_ERR_CNT_6_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_7__CODE_ERR_CNT_7_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_7__DISPARITY_ERR_CNT_7_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_8__CODE_ERR_CNT_8_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_8__DISPARITY_ERR_CNT_8_MASK__SI 0xffff0000L -#define PCIE_P_DECODE_ERR_CNT_9__CODE_ERR_CNT_9_MASK__SI 0x0000ffffL -#define PCIE_P_DECODE_ERR_CNT_9__DISPARITY_ERR_CNT_9_MASK__SI 0xffff0000L -#define PCIE_P_IMP_CNTL_STRENGTH__PI_HALT_IMP_CAL_MASK__SI 0x10000000L -#define PCIE_P_IMP_CNTL_STRENGTH__P_PAD_MANUAL_OVERRIDE_MASK__SI 0x80000000L -#define PCIE_P_IMP_CNTL_STRENGTH__P_RX_IMP_CNTL_MASK__SI 0x0f000000L -#define PCIE_P_IMP_CNTL_STRENGTH__P_RX_IMP_CNTL_READ_BACK_MASK__SI 0x00000f00L -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_IMP_CNTL_MASK__SI 0x00f00000L -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_IMP_CNTL_READ_BACK_MASK__SI 0x000000f0L -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_STR_CNTL_MASK__SI 0x000f0000L -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_STR_CNTL_READ_BACK_MASK__SI 0x0000000fL -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_DEC_THRESHOLD_MASK__SI 0x1f000000L -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_INC_THRESHOLD_MASK__SI 0x001f0000L -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_SAMPLE_DELAY_MASK__SI 0x00001f00L -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_UPDATE_RATE_MASK__SI 0x0000001fL -#define PCIE_P_MISC_DEBUG_STATUS__P_HW_DEBUG_MASK__SI 0x0000fff0L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_0_MASK__SI 0x00010000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_10_MASK__SI 0x04000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_11_MASK__SI 0x08000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_12_MASK__SI 0x10000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_13_MASK__SI 0x20000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_14_MASK__SI 0x40000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_15_MASK__SI 0x80000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_1_MASK__SI 0x00020000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_2_MASK__SI 0x00040000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_3_MASK__SI 0x00080000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_4_MASK__SI 0x00100000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_5_MASK__SI 0x00200000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_6_MASK__SI 0x00400000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_7_MASK__SI 0x00800000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_8_MASK__SI 0x01000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_9_MASK__SI 0x02000000L -#define PCIE_P_MISC_DEBUG_STATUS__P_LANE_REVERSAL_MASK__SI 0x00000004L -#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK__CI__VI 0x000000ffL -#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK__CI__VI 0xffff0000L -#define PCIE_P_PAD_FORCE_DIS__B_PBG_PDNB_FDIS_MASK__SI 0x02000000L -#define PCIE_P_PAD_FORCE_DIS__B_PIMP_RX_PDNB_FDIS_MASK__SI 0x08000000L -#define PCIE_P_PAD_FORCE_DIS__B_PIMP_TX_PDNB_FDIS_MASK__SI 0x04000000L -#define PCIE_P_PAD_FORCE_DIS__B_PI_DREN_FDIS_MASK__SI 0x01000000L -#define PCIE_P_PAD_FORCE_DIS__B_PPLL_BUF_PDNB_FDIS_MASK__SI 0x00f00000L -#define PCIE_P_PAD_FORCE_DIS__B_PPLL_PDNB_FDIS_MASK__SI 0x000f0000L -#define PCIE_P_PAD_FORCE_DIS__B_PRX_PDNB_FDIS_MASK__SI 0x0000ff00L -#define PCIE_P_PAD_FORCE_DIS__B_PTX_PDNB_FDIS_MASK__SI 0x000000ffL -#define PCIE_P_PAD_FORCE_EN__B_PBG_PDNB_FEN_MASK__SI 0x02000000L -#define PCIE_P_PAD_FORCE_EN__B_PIMP_RX_PDNB_FEN_MASK__SI 0x08000000L -#define PCIE_P_PAD_FORCE_EN__B_PIMP_TX_PDNB_FEN_MASK__SI 0x04000000L -#define PCIE_P_PAD_FORCE_EN__B_PI_DREN_FEN_MASK__SI 0x01000000L -#define PCIE_P_PAD_FORCE_EN__B_PPLL_BUF_PDNB_FEN_MASK__SI 0x00f00000L -#define PCIE_P_PAD_FORCE_EN__B_PPLL_PDNB_FEN_MASK__SI 0x000f0000L -#define PCIE_P_PAD_FORCE_EN__B_PRX_PDNB_FEN_MASK__SI 0x0000ff00L -#define PCIE_P_PAD_FORCE_EN__B_PTX_PDNB_FEN_MASK__SI 0x000000ffL -#define PCIE_P_PAD_MISC_CNTL__P_LINK_RETRAIN_ON_ERR_EN_MASK__SI 0x00000008L -#define PCIE_P_PAD_MISC_CNTL__P_PAD_IMP_DUMMYOUT_MASK__SI 0x00000002L -#define PCIE_P_PAD_MISC_CNTL__P_PAD_IMP_TESTOUT_MASK__SI 0x00000004L -#define PCIE_P_PAD_MISC_CNTL__P_PAD_I_DUMMYOUT_MASK__SI 0x00000001L -#define PCIE_P_PAD_MISC_CNTL__P_PLLCAL_INC_LOWER_PHASE_MASK__SI 0x00000070L -#define PCIE_P_PLL_CNTL__P_CALREF_MASK__SI 0x0000000cL -#define PCIE_P_PLL_CNTL__P_VCOREF_MASK__SI 0x00000003L -#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007eL -#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_0_MASK__SI 0x00010000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_10_MASK__SI 0x04000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_11_MASK__SI 0x08000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_12_MASK__SI 0x10000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_13_MASK__SI 0x20000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_14_MASK__SI 0x40000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_15_MASK__SI 0x80000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_1_MASK__SI 0x00020000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_2_MASK__SI 0x00040000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_3_MASK__SI 0x00080000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_4_MASK__SI 0x00100000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_5_MASK__SI 0x00200000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_6_MASK__SI 0x00400000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_7_MASK__SI 0x00800000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_8_MASK__SI 0x01000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_9_MASK__SI 0x02000000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_0_MASK__SI 0x00000001L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_10_MASK__SI 0x00000400L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_11_MASK__SI 0x00000800L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_12_MASK__SI 0x00001000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_13_MASK__SI 0x00002000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_14_MASK__SI 0x00004000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_15_MASK__SI 0x00008000L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_1_MASK__SI 0x00000002L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_2_MASK__SI 0x00000004L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_3_MASK__SI 0x00000008L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_4_MASK__SI 0x00000010L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_5_MASK__SI 0x00000020L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_6_MASK__SI 0x00000040L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_7_MASK__SI 0x00000080L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_8_MASK__SI 0x00000100L -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_9_MASK__SI 0x00000200L -#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK__CI__VI 0x0000ff00L -#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK__CI__VI 0x000000ffL -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_DCB_ERR_RETRAIN_MASK__SI 0x02000000L -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_THRESH_CLEARSKP_MASK__SI 0x01000000L -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_THRESH_CODE_ERR_MASK__SI 0x0000ff00L -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_THRESH_DISP_ERR_MASK__SI 0x000000ffL -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_DEC_THRESHOLD_MASK__SI 0x1f000000L -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_INC_THRESHOLD_MASK__SI 0x001f0000L -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_SAMPLE_DELAY_MASK__SI 0x00001f00L -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_UPDATE_RATE_MASK__SI 0x0000001fL -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_BYPASS_MODE_MASK__SI 0x00100000L -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_ELECT_IDLE_DET_EN_MASK__SI 0x00000001L -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_ENABLE_IN_GEN1_MASK__SI 0x00200000L -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_M_GOOD_MASK__SI 0x000003fcL -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_N_BAD_MASK__SI 0x0003fc00L -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_PAD_MODE_MASK__SI 0x000c0000L -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_SYNC_MODE_MASK__SI 0x00000002L -#define PCIE_REG_R_RTR_TIMEOUT_CNTL__REG_R_RTR_TIMEOUT_RST_MASK__SI 0x00000001L -#define PCIE_REG_R_RTR_TIMEOUT_CNTL__REG_R_RTR_TIMEOUT_VALUE_MASK__SI 0xfffffff0L -#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffffL -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_C_RTR_ERROR_MASK__SI 0x00000004L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_C_RTR_STATUS_MASK__SI 0x00040000L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_R_RTR_ERROR_MASK__SI 0x00000002L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_R_RTR_STATUS_MASK__SI 0x00020000L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_SLV_R_RTR_ERROR_MASK__SI 0x00000001L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_SLV_R_RTR_STATUS_MASK__SI 0x00010000L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__REG_R_RTR_ERROR_MASK__SI 0x00000008L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__REG_R_RTR_STATUS_MASK__SI 0x00080000L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__TX_SLVCPL_TIMEOUT_ERROR_MASK__SI 0x00000010L -#define PCIE_RTR_CPL_TIMEOUT_STATUS__TX_SLVCPL_TIMEOUT_STATUS_MASK__SI 0x00100000L -#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK__CI__VI 0x00000008L -#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK__CI__VI 0x00000001L -#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK__CI__VI 0x00000020L -#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK__CI__VI 0x00000010L -#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK__CI__VI 0x00000002L -#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK__CI__VI 0x00000004L -#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK__CI__VI 0x00000010L -#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK__CI__VI 0x00000008L -#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK__CI__VI 0x00000004L -#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK__CI__VI 0x00000001L -#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK__CI__VI 0x00000002L -#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L -#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L -#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK__CI__VI 0x00001000L -#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L -#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L -#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L -#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK__CI__VI 0x00800000L -#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L -#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L -#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L -#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK__CI__VI 0x01000000L -#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L -#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L -#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L -#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK__CI__VI 0x00400000L -#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L -#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L -#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK__CI__VI 0x02000000L -#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK__CI__VI 0x00200000L -#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L -#define PCIE_RX_CNTL__RX_IGNORE_VEND0_UR_MASK__SI 0x00001000L -#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L -#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L -#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L -#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L -#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000fffL -#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00ff0000L -#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000fffL -#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00ff0000L -#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000fffL -#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00ff0000L -#define PCIE_RX_CREDITS_RECEIVED_CPL__RX_CREDITS_RECEIVED_CPLD_MASK__SI 0x00000fffL -#define PCIE_RX_CREDITS_RECEIVED_CPL__RX_CREDITS_RECEIVED_CPLH_MASK__SI 0x00ff0000L -#define PCIE_RX_CREDITS_RECEIVED_NP__RX_CREDITS_RECEIVED_NPD_MASK__SI 0x00000fffL -#define PCIE_RX_CREDITS_RECEIVED_NP__RX_CREDITS_RECEIVED_NPH_MASK__SI 0x00ff0000L -#define PCIE_RX_CREDITS_RECEIVED_P__RX_CREDITS_RECEIVED_PD_MASK__SI 0x00000fffL -#define PCIE_RX_CREDITS_RECEIVED_P__RX_CREDITS_RECEIVED_PH_MASK__SI 0x00ff0000L -#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK__CI__VI 0x00000fffL -#define PCIE_RX_LASTACK_SEQNUM__RX_LASTACK_SEQNUM_MASK__SI 0x00000fffL -#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffffL -#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffffL -#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffffL -#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffffL -#define PCIE_RX_NUM_NACK_GENERATED__RX_NUM_NACK_GENERATED_MASK__SI 0xffffffffL -#define PCIE_RX_NUM_NACK__RX_NUM_NACK_MASK__SI 0xffffffffL -#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK__CI__VI 0xffffffffL -#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK__CI__VI 0xffffffffL -#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00ffffffL -#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L -#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffffL -#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK__CI__VI 0x0000ffffL -#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK__CI__VI 0x000f0000L -#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK__CI__VI 0xfff00000L -#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK__CI__VI 0x00000040L -#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK__CI__VI 0x00000020L -#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK__CI__VI 0x00000400L -#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK__CI__VI 0x00000080L -#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK__CI__VI 0x00000200L -#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK__CI__VI 0x00000010L -#define PCIE_STRAP_F0__STRAP_F0_EN_MASK__CI__VI 0x00000001L -#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK__CI__VI 0x00000002L -#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK__CI 0x00002000L -#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK__CI__VI 0x00000004L -#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK__CI__VI 0x00000800L -#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK__CI__VI 0x00001000L -#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK__CI__VI 0x00000100L -#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK__CI__VI 0x00000008L -#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK__CI__VI 0x00000040L -#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK__CI__VI 0x00000020L -#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK__CI__VI 0x00000400L -#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK__CI__VI 0x00000080L -#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK__CI__VI 0x00000200L -#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK__CI__VI 0x00000010L -#define PCIE_STRAP_F1__STRAP_F1_EN_MASK__CI 0x00000001L -#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK__CI__VI 0x00000002L -#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK__CI__VI 0x00000004L -#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK__CI__VI 0x00000800L -#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK__CI__VI 0x00001000L -#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK__CI__VI 0x00000100L -#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK__CI__VI 0x00000008L -#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK__CI__VI 0x00000040L -#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK__CI__VI 0x00000020L -#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK__CI__VI 0x00000400L -#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK__CI__VI 0x00000080L -#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK__CI__VI 0x00000200L -#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK__CI__VI 0x00000010L -#define PCIE_STRAP_F2__STRAP_F2_EN_MASK__CI 0x00000001L -#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK__CI__VI 0x00000002L -#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK__CI__VI 0x00000004L -#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK__CI__VI 0x00000800L -#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK__CI__VI 0x00001000L -#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK__CI__VI 0x00000100L -#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK__CI__VI 0x00000008L -#define PCIE_STRAP_F3__RESERVED_MASK__CI__VI 0xffffffffL -#define PCIE_STRAP_F4__RESERVED_MASK__CI__VI 0xffffffffL -#define PCIE_STRAP_F5__RESERVED_MASK__CI__VI 0xffffffffL -#define PCIE_STRAP_F6__RESERVED_MASK__CI__VI 0xffffffffL -#define PCIE_STRAP_F7__RESERVED_MASK__CI__VI 0xffffffffL -#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x00000080L -#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007fL -#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L -#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK__CI__VI 0x00000008L -#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L -#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK__CI__VI 0x00000010L -#define PCIE_STRAP_MISC__RESERVED1_MASK__SI 0x00000010L -#define PCIE_STRAP_MISC__RESERVED2_MASK__SI 0x08000000L -#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK 0x00000040L -#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L -#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x02000000L -#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L -#define PCIE_STRAP_MISC__STRAP_F0_AER_EN_MASK__SI 0x00000100L -#define PCIE_STRAP_MISC__STRAP_F0_EN_MASK__SI 0x00000200L -#define PCIE_STRAP_MISC__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK__SI 0x00001000L -#define PCIE_STRAP_MISC__STRAP_F0_MSI_EN_MASK__SI 0x00000400L -#define PCIE_STRAP_MISC__STRAP_F0_VC_EN_MASK__SI 0x00000800L -#define PCIE_STRAP_MISC__STRAP_F1_AER_EN_MASK__SI 0x00002000L -#define PCIE_STRAP_MISC__STRAP_F1_EN_MASK__SI 0x00004000L -#define PCIE_STRAP_MISC__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK__SI 0x00020000L -#define PCIE_STRAP_MISC__STRAP_F1_MSI_EN_MASK__SI 0x00008000L -#define PCIE_STRAP_MISC__STRAP_F1_VC_EN_MASK__SI 0x00010000L -#define PCIE_STRAP_MISC__STRAP_F2_AER_EN_MASK__SI 0x00040000L -#define PCIE_STRAP_MISC__STRAP_F2_EN_MASK__SI 0x00080000L -#define PCIE_STRAP_MISC__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK__SI 0x00400000L -#define PCIE_STRAP_MISC__STRAP_F2_MSI_EN_MASK__SI 0x00100000L -#define PCIE_STRAP_MISC__STRAP_F2_VC_EN_MASK__SI 0x00200000L -#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK__CI__VI 0x40000000L -#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK__SI__CI 0x0000000fL -#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK__CI__VI 0x00001f00L -#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L -#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK__CI__VI 0x00002000L -#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK__CI__VI 0x00008000L -#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK__CI__VI 0x00004000L -#define PCIE_STRAP_MISC__STRAP_PASID_TLP_PREFIX_SUPPORTED_MASK__CI 0x00000080L -#define PCIE_STRAP_MISC__STRAP_PHY_RCVRDET_3NF_MASK__SI 0x00000080L -#define PCIE_STRAP_MISC__STRAP_PWRSAVE_PEIDL_GOOD_MASK__SI 0x00000020L -#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L -#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK__CI__VI 0x00000010L -#define PCIE_STRAP_PI__STRAP_BACKGROUND_IMP_CAL_MASK__SI 0x00000002L -#define PCIE_STRAP_PI__STRAP_BYPASS_LDSK_TO_LC_MASK__SI 0x80000000L -#define PCIE_STRAP_PI__STRAP_ELAST_WATERMARK_MASK__SI 0x00001800L -#define PCIE_STRAP_PI__STRAP_EXTDEV_EN_MASK__SI 0x0c000000L -#define PCIE_STRAP_PI__STRAP_IMP_MANUAL_OVERRIDE_MASK__SI 0x00000004L -#define PCIE_STRAP_PI__STRAP_INC_PLLCAL_PHASE_MASK__SI 0x01e00000L -#define PCIE_STRAP_PI__STRAP_INIT_REAL_PES_MODE_MASK__SI 0x00100000L -#define PCIE_STRAP_PI__STRAP_LDSK_X1_BYPASS_MASK__SI 0x00004000L -#define PCIE_STRAP_PI__STRAP_PAD_RX_MANUAL_IMPEDANCE_MASK__SI 0x00000078L -#define PCIE_STRAP_PI__STRAP_PAD_TX_MANUAL_IMPEDANCE_MASK__SI 0x00000780L -#define PCIE_STRAP_PI__STRAP_PHY_RX_INCAL_FORCE_MASK__SI 0x02000000L -#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L -#define PCIE_STRAP_PI__STRAP_RXP_LAT_REDUCTION_DIS_MASK__SI 0x00002000L -#define PCIE_STRAP_PI__STRAP_SHUTOFF_PORTS_FOR_SYM_ERR_MASK__SI 0x40000000L -#define PCIE_STRAP_PI__STRAP_STAGGER_CNTL_MASK__SI 0x00018000L -#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L -#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L -#define PCIE_STRAP_PI__STRAP_TX_PDNB_MODE_MASK__SI 0x00020000L -#define PCIE_STRAP_PI__STRAP_VCO_MODE_MASK__SI 0x000c0000L -#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK__CI__VI 0xffffffffL -#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK__CI__VI 0xffffffffL -#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK__CI__VI 0xffffffffL -#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK__CI__VI 0xffffffffL -#define PCIE_TRUSTED_BASE_CLASS__BASE_CLASS_MASK__SI 0x000000ffL -#define PCIE_TRUSTED_CAC_CAP_LIST__CAP_ID_MASK__SI 0x0000ffffL -#define PCIE_TRUSTED_CAC_CAP_LIST__CAP_VER_MASK__SI 0x000f0000L -#define PCIE_TRUSTED_CAC_CAP_LIST__NEXT_PTR_MASK__SI 0xfff00000L -#define PCIE_TRUSTED_CAC_DEVICE_CORRELATION__DEVICE_CORRELATION_MASK__SI 0xffffffffL -#define PCIE_TRUSTED_FIRST_CAP_OFFSET__FIRST_CAP_OFFSET_MASK__SI 0x00000fffL -#define PCIE_TRUSTED_PROG_INTERFACE__PROG_INTERFACE_MASK__SI 0x000000ffL -#define PCIE_TRUSTED_SUB_CLASS__SUB_CLASS_MASK__SI 0x000000ffL -#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK__CI__VI 0x00000fffL -#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK__SI 0x000000ffL -#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK__CI__VI 0x00001000L -#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK__SI 0x00000100L -#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L -#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L -#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK__CI__VI 0x01000000L -#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK__CI__VI 0x02000000L -#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK__CI__VI 0x04000000L -#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK__CI__VI 0x00800000L -#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_MASK__SI 0xfc000000L -#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_SEL_MASK__SI 0x03000000L -#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK__CI__VI 0x00008000L -#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK__SI 0x00080000L -#define PCIE_TX_CNTL__TX_GAP_BTW_PKTS_MASK__SI 0x00070000L -#define PCIE_TX_CNTL__TX_GENERATE_CRC_ERR_MASK__SI 0x00008000L -#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L -#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L -#define PCIE_TX_CNTL__TX_REPLAY_NUM_COUNT_MASK__SI 0x000003ffL -#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L -#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000c00L -#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000fffL -#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00ff0000L -#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000fffL -#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00ff0000L -#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000fffL -#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00ff0000L -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK__CI__VI 0x00000700L -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK__CI__VI 0x07000000L -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK__CI__VI 0x00000070L -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK__CI__VI 0x00700000L -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK__CI__VI 0x00000007L -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK__CI__VI 0x00070000L -#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000fffL -#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00ff0000L -#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000fffL -#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00ff0000L -#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000fffL -#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00ff0000L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK__CI__VI 0x00000030L -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK__CI__VI 0x0000000cL -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK__CI__VI 0x00000003L -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK__CI__VI 0x00000300L -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK__CI__VI 0x000000c0L -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK__CI__VI 0x00003000L -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK__CI__VI 0x00000c00L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK__CI__VI 0x00000030L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK__CI__VI 0x0000000cL -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK__CI__VI 0x00000003L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK__CI__VI 0x00000300L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK__CI__VI 0x000000c0L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK__CI__VI 0x00003000L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK__CI__VI 0x00000c00L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK__CI__VI 0x00300000L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK__CI__VI 0x000c0000L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK__CI__VI 0x00030000L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK__CI__VI 0x03000000L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK__CI__VI 0x00c00000L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK__CI__VI 0x30000000L -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK__CI__VI 0x0c000000L -#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffffL -#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffffL -#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffffL -#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffffL -#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK__CI__VI 0x00000007L -#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK__SI 0x000003ffL -#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000L -#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L -#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000ff00L -#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000f8L -#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_CPL_ACK_EN_MASK__SI 0x00800000L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_CPL_ACK_MASK__SI 0x003f0000L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_NP_ACK_EN_MASK__SI 0x00008000L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_NP_ACK_MASK__SI 0x00003f00L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_NP_VC1_ACK_EN_MASK__SI 0x00004000L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_P_ACK_EN_MASK__SI 0x00000080L -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_P_ACK_MASK__SI 0x0000003fL -#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0fff0000L -#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000fffL -#define PCIE_TX_SLVCPL_TIMEOUT_CNTL__TX_SLVCPL_TIMEOUT_RST_MASK__SI 0x00000001L -#define PCIE_TX_SLVCPL_TIMEOUT_CNTL__TX_SLVCPL_TIMEOUT_VALUE_MASK__SI 0xfffffff0L -#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00ffffffL -#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L -#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK__CI__VI 0x01000000L -#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L -#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L -#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L -#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L -#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L -#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L -#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK__CI__VI 0x00800000L -#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L -#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L -#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L -#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK__CI__VI 0x02000000L -#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK__CI__VI 0x00400000L -#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L -#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L -#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L -#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK__CI__VI 0x01000000L -#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L -#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L -#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L -#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L -#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L -#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L -#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK__CI__VI 0x00800000L -#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L -#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L -#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L -#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK__CI__VI 0x02000000L -#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK__CI__VI 0x00400000L -#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L -#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L -#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L -#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK__CI__VI 0x01000000L -#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L -#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L -#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L -#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L -#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L -#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L -#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK__CI__VI 0x00800000L -#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L -#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L -#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L -#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK__CI__VI 0x02000000L -#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK__CI__VI 0x00400000L -#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L -#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L -#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003f0000L -#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000ffL -#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000L -#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L -#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L -#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000e0000L -#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L -#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000feL -#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L -#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L -#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x00000001L -#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x00000002L -#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003f0000L -#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000ffL -#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000L -#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L -#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L -#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000e0000L -#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L -#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000feL -#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L -#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L -#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x00000001L -#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x00000002L -#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000ffffL -#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000f0000L -#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000L -#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffffL -#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffffL -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000ffffL -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000f0000L -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000L -#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000ffffL -#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000L -#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000f0000L -#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L -#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L -#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L -#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L -#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L -#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L -#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L -#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK__CI__VI 0x000fffffL -#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK__CI__VI 0x80000000L -#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK__CI__VI 0x000fffffL -#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK__CI__VI 0x000fffffL -#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK__CI__VI 0x80000000L -#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK__CI__VI 0x000fffffL -#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK__CI__VI 0x000fffffL -#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK__CI__VI 0x80000000L -#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK__CI__VI 0x000fffffL -#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK__CI__VI 0x000fffffL -#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK__CI__VI 0x80000000L -#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK__CI__VI 0x000fffffL -#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000L -#define PEER_REG_RANGE0__START_ADDR_MASK 0x0000ffffL -#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000L -#define PEER_REG_RANGE1__START_ADDR_MASK 0x0000ffffL -#define PERF_MON_CTRL_1__CHAN_1_MODE_MASK__CI__VI 0x07000000L -#define PERF_MON_CTRL_1__CHAN_1_PERIODIC_MASK__CI__VI 0x00100000L -#define PERF_MON_CTRL_1__CHAN_1_SEL_MASK__CI__VI 0x0000001fL -#define PERF_MON_CTRL_1__CHAN_2_MODE_MASK__CI__VI 0x38000000L -#define PERF_MON_CTRL_1__CHAN_2_PERIODIC_MASK__CI__VI 0x00200000L -#define PERF_MON_CTRL_1__CHAN_2_SEL_MASK__CI__VI 0x000003e0L -#define PERF_MON_CTRL_1__CHAN_3_PERIODIC_MASK__CI__VI 0x00400000L -#define PERF_MON_CTRL_1__CHAN_3_SEL_MASK__CI__VI 0x00007c00L -#define PERF_MON_CTRL_1__CHAN_4_PERIODIC_MASK__CI__VI 0x00800000L -#define PERF_MON_CTRL_1__CHAN_4_SEL_MASK__CI__VI 0x000f8000L -#define PERF_MON_CTRL_1__RESERVED_MASK__CI__VI 0xc0000000L -#define PERF_MON_CTRL_2__CHAN_3_MODE_MASK__CI__VI 0x01c00000L -#define PERF_MON_CTRL_2__CHAN_4_MODE_MASK__CI__VI 0x0e000000L -#define PERF_MON_CTRL_2__ENABLE_MASK__CI__VI 0x00100000L -#define PERF_MON_CTRL_2__PERIOD_MASK__CI__VI 0x0000ffffL -#define PERF_MON_CTRL_2__RESERVED_MASK__CI__VI 0xf0000000L -#define PERF_MON_CTRL_2__RESET_MASK__CI__VI 0x00200000L -#define PERF_MON_CTRL_2__UNIT_MASK__CI__VI 0x000f0000L -#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK__SI 0x00010000L -#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK__SI 0x00001000L -#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK__SI 0x00004000L -#define PHY_PAD_FORCE_DIS1__B_PIMP_RX_PDNB_DIS_MASK__SI 0x00000020L -#define PHY_PAD_FORCE_DIS1__B_PIMP_TX_PDNB_DIS_MASK__SI 0x00000010L -#define PHY_PAD_FORCE_DIS1__B_PPLL_BUF_PDNB_DIS_MASK__SI 0x0000000cL -#define PHY_PAD_FORCE_DIS1__B_PPLL_PDNB_DIS_MASK__SI 0x00000003L -#define PHY_PAD_FORCE_DIS1__B_PRX_FRONTEND_DIS_MASK__SI 0x003fffc0L -#define PHY_PAD_FORCE_DIS2__B_PRX_PDNB_DIS_MASK__SI 0xffff0000L -#define PHY_PAD_FORCE_DIS2__B_PTX_PDNB_DIS_MASK__SI 0x0000ffffL -#define PHY_PAD_FORCE_EN1__B_PIMP_RX_PDNB_EN_MASK__SI 0x00000020L -#define PHY_PAD_FORCE_EN1__B_PIMP_TX_PDNB_EN_MASK__SI 0x00000010L -#define PHY_PAD_FORCE_EN1__B_PPLL_BUF_PDNB_EN_MASK__SI 0x0000000cL -#define PHY_PAD_FORCE_EN1__B_PPLL_PDNB_EN_MASK__SI 0x00000003L -#define PHY_PAD_FORCE_EN1__B_PRX_FRONTEND_EN_MASK__SI 0x003fffc0L -#define PHY_PAD_FORCE_EN2__B_PRX_PDNB_EN_MASK__SI 0x0000ffffL -#define PHY_PAD_FORCE_EN2__B_PTX_PDNB_EN_MASK__SI 0xffff0000L -#define PHY_TESTMODES__HISPEED_BYPASS_EN_MASK__SI 0x00000001L -#define PHY_TESTMODES__LOCK_DETECT_EN_0_MASK__SI 0x00000040L -#define PHY_TESTMODES__LOCK_DETECT_EN_1_MASK__SI 0x00000080L -#define PHY_TESTMODES__SELECT_OUTPUT_MASK__SI 0x0000001cL -#define PHY_TESTMODES__SWAP_OUTPUT_MASK__SI 0x00000002L -#define PIPE0_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK__SI 0xffff0000L -#define PIPE0_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK__SI 0x0000ffffL -#define PIPE0_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE0_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK__SI 0xffff0000L -#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE0_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK__SI 0xffff0000L -#define PIPE0_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK__SI 0x0000ffffL -#define PIPE1_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK__SI 0xffff0000L -#define PIPE1_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK__SI 0x0000ffffL -#define PIPE1_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE1_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK__SI 0xffff0000L -#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE1_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK__SI 0xffff0000L -#define PIPE1_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK__SI 0x0000ffffL -#define PIPE2_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK__SI 0xffff0000L -#define PIPE2_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK__SI 0x0000ffffL -#define PIPE2_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE2_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK__SI 0xffff0000L -#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE2_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK__SI 0xffff0000L -#define PIPE2_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK__SI 0x0000ffffL -#define PIPE3_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK__SI 0xffff0000L -#define PIPE3_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK__SI 0x0000ffffL -#define PIPE3_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE3_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK__SI 0xffff0000L -#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE3_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK__SI 0xffff0000L -#define PIPE3_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK__SI 0x0000ffffL -#define PIPE4_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK__SI 0xffff0000L -#define PIPE4_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK__SI 0x0000ffffL -#define PIPE4_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE4_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK__SI 0xffff0000L -#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE4_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK__SI 0xffff0000L -#define PIPE4_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK__SI 0x0000ffffL -#define PIPE5_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK__SI 0xffff0000L -#define PIPE5_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK__SI 0x0000ffffL -#define PIPE5_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE5_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK__SI 0xffff0000L -#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK__SI 0x0000ffffL -#define PIPE5_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK__SI 0xffff0000L -#define PIPE5_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK__SI 0x0000ffffL -#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK__SI 0x00000030L -#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK__SI 0x00000001L -#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK__SI 0x00000030L -#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK__SI 0x00000001L -#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x00007f00L -#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000L -#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0x000000f0L -#define PLL_TEST_CNTL__TST_RESET_MASK 0x00008000L -#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x0000000fL -#define PMI_CAP_LIST__CAP_ID_MASK 0x000000ffL -#define PMI_CAP_LIST__NEXT_PTR_MASK 0x0000ff00L -#define PMI_CAP__AUX_CURRENT_MASK 0x000001c0L -#define PMI_CAP__D1_SUPPORT_MASK 0x00000200L -#define PMI_CAP__D2_SUPPORT_MASK 0x00000400L -#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x00000020L -#define PMI_CAP__PME_CLOCK_MASK 0x00000008L -#define PMI_CAP__PME_SUPPORT_MASK 0x0000f800L -#define PMI_CAP__VERSION_MASK 0x00000007L -#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L -#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L -#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L -#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001e00L -#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L -#define PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L -#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L -#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000L -#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L -#define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON_MASK__SI 0x00100000L -#define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK_MASK__SI 0x01000000L -#define PRIORITY_A_CNT__PRIORITY_A_OFF_MASK__SI 0x00010000L -#define PRIORITY_A_CNT__PRIORITY_MARK_A_MASK__SI 0x00007fffL -#define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON_MASK__SI 0x00100000L -#define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK_MASK__SI 0x01000000L -#define PRIORITY_B_CNT__PRIORITY_B_OFF_MASK__SI 0x00010000L -#define PRIORITY_B_CNT__PRIORITY_MARK_B_MASK__SI 0x00007fffL -#define PROCESSOR_TDP__Base_Tdp_MASK__CI__VI 0xffff0000L -#define PROCESSOR_TDP__Processor_Tdp_MASK__CI__VI 0x0000ffffL -#define PROG_INTERFACE__PROG_INTERFACE_MASK 0x000000ffL -#define PSTATE_STATUS__Cmp_Unit0_Pstate_MASK__CI__VI 0x00000007L -#define PSTATE_STATUS__Cmp_Unit1_Pstate_MASK__CI__VI 0x00000070L -#define PSTATE_STATUS__Curr_Core_Vid_Pstate_MASK__CI__VI 0x03800000L -#define PSTATE_STATUS__Curr_Nb_Vid_Pstate_MASK__CI__VI 0x0c000000L -#define PSTATE_STATUS__Pwr_Mgmt_Req_Act1_MASK__CI__VI 0x40000000L -#define PSTATE_STATUS__Pwr_Mgmt_Req_Act2_MASK__CI__VI 0x80000000L -#define PSTATE_STATUS__Pwr_Mgmt_Req_Wait_MASK__CI__VI 0x10000000L -#define PSTATE_STATUS__RESERVED_1_MASK__CI__VI 0x00000008L -#define PSTATE_STATUS__RESERVED_MASK__CI__VI 0x007fff80L -#define PSTATE_STATUS__Vid_Transition_Act_MASK__CI__VI 0x20000000L -#define PWR_BIF_SSA__WAKE_UP_MASK__CI__VI 0x00000001L -#define PWR_EVENT_CLEAR__AZALIA_MASK__CI__VI 0x00000400L -#define PWR_EVENT_CLEAR__BIF_MASK__CI__VI 0x00000800L -#define PWR_EVENT_CLEAR__DC_MASK__CI__VI 0x00001000L -#define PWR_EVENT_CLEAR__DISPLAY_GAP_MASK__CI__VI 0x00000200L -#define PWR_EVENT_CLEAR__MCB_MASK__CI__VI 0x00000100L -#define PWR_EVENT_CLEAR__MCD0_MASK__CI__VI 0x00000001L -#define PWR_EVENT_CLEAR__MCD1_MASK__CI__VI 0x00000002L -#define PWR_EVENT_CLEAR__MCD2_MASK__CI__VI 0x00000004L -#define PWR_EVENT_CLEAR__MCD3_MASK__CI__VI 0x00000008L -#define PWR_EVENT_CLEAR__MCD4_MASK__CI__VI 0x00000010L -#define PWR_EVENT_CLEAR__MCD5_MASK__CI__VI 0x00000020L -#define PWR_EVENT_CLEAR__MCD6_MASK__CI__VI 0x00000040L -#define PWR_EVENT_CLEAR__MCD7_MASK__CI__VI 0x00000080L -#define PWR_EVENT_CLEAR__UVD_MASK__CI__VI 0x00004000L -#define PWR_EVENT_CLEAR__VCE_MASK__CI__VI 0x00002000L -#define PWR_EVENT_PENDING__AZALIA_MASK__CI__VI 0x00000400L -#define PWR_EVENT_PENDING__BIF_MASK__CI__VI 0x00000800L -#define PWR_EVENT_PENDING__DC_MASK__CI__VI 0x00001000L -#define PWR_EVENT_PENDING__DISPLAY_GAP_MASK__CI__VI 0x00000200L -#define PWR_EVENT_PENDING__MCB_MASK__CI__VI 0x00000100L -#define PWR_EVENT_PENDING__MCD0_MASK__CI__VI 0x00000001L -#define PWR_EVENT_PENDING__MCD1_MASK__CI__VI 0x00000002L -#define PWR_EVENT_PENDING__MCD2_MASK__CI__VI 0x00000004L -#define PWR_EVENT_PENDING__MCD3_MASK__CI__VI 0x00000008L -#define PWR_EVENT_PENDING__MCD4_MASK__CI__VI 0x00000010L -#define PWR_EVENT_PENDING__MCD5_MASK__CI__VI 0x00000020L -#define PWR_EVENT_PENDING__MCD6_MASK__CI__VI 0x00000040L -#define PWR_EVENT_PENDING__MCD7_MASK__CI__VI 0x00000080L -#define PWR_EVENT_PENDING__UVD_MASK__CI__VI 0x00004000L -#define PWR_EVENT_PENDING__VCE_MASK__CI__VI 0x00002000L -#define PWR_EVENT_POLARITY__AZALIA_MASK__CI__VI 0x00000400L -#define PWR_EVENT_POLARITY__BIF_MASK__CI__VI 0x00000800L -#define PWR_EVENT_POLARITY__DC_MASK__CI__VI 0x00001000L -#define PWR_EVENT_POLARITY__DISPLAY_GAP_MASK__CI__VI 0x00000200L -#define PWR_EVENT_POLARITY__MCB_MASK__CI__VI 0x00000100L -#define PWR_EVENT_POLARITY__MCD0_MASK__CI__VI 0x00000001L -#define PWR_EVENT_POLARITY__MCD1_MASK__CI__VI 0x00000002L -#define PWR_EVENT_POLARITY__MCD2_MASK__CI__VI 0x00000004L -#define PWR_EVENT_POLARITY__MCD3_MASK__CI__VI 0x00000008L -#define PWR_EVENT_POLARITY__MCD4_MASK__CI__VI 0x00000010L -#define PWR_EVENT_POLARITY__MCD5_MASK__CI__VI 0x00000020L -#define PWR_EVENT_POLARITY__MCD6_MASK__CI__VI 0x00000040L -#define PWR_EVENT_POLARITY__MCD7_MASK__CI__VI 0x00000080L -#define PWR_EVENT_POLARITY__UVD_MASK__CI__VI 0x00004000L -#define PWR_EVENT_POLARITY__VCE_MASK__CI__VI 0x00002000L -#define PWR_EVENT_SENSE__AZALIA_MASK__CI__VI 0x00000400L -#define PWR_EVENT_SENSE__BIF_MASK__CI__VI 0x00000800L -#define PWR_EVENT_SENSE__DC_MASK__CI__VI 0x00001000L -#define PWR_EVENT_SENSE__DISPLAY_GAP_MASK__CI__VI 0x00000200L -#define PWR_EVENT_SENSE__MCB_MASK__CI__VI 0x00000100L -#define PWR_EVENT_SENSE__MCD0_MASK__CI__VI 0x00000001L -#define PWR_EVENT_SENSE__MCD1_MASK__CI__VI 0x00000002L -#define PWR_EVENT_SENSE__MCD2_MASK__CI__VI 0x00000004L -#define PWR_EVENT_SENSE__MCD3_MASK__CI__VI 0x00000008L -#define PWR_EVENT_SENSE__MCD4_MASK__CI__VI 0x00000010L -#define PWR_EVENT_SENSE__MCD5_MASK__CI__VI 0x00000020L -#define PWR_EVENT_SENSE__MCD6_MASK__CI__VI 0x00000040L -#define PWR_EVENT_SENSE__MCD7_MASK__CI__VI 0x00000080L -#define PWR_EVENT_SENSE__UVD_MASK__CI__VI 0x00004000L -#define PWR_EVENT_SENSE__VCE_MASK__CI__VI 0x00002000L -#define PWR_IDSC_CTRL2__CMON_ADC_RANGE_RST_MASK__CI 0x00000002L -#define PWR_IDSC_CTRL2__CMON_INPUT_SEL_MASK__CI 0x00000004L -#define PWR_IDSC_CTRL2__CMON_RESET_MASK__CI 0x00000001L -#define PWR_IDSC_CTRL2__IDSC_DCM_OVERRIDE_MASK__CI 0x00000100L -#define PWR_IDSC_CTRL2__IDSC_DVID_MASK__CI 0x00800000L -#define PWR_IDSC_CTRL2__IDSC_EFUSE_READY_MASK__CI 0x00000010L -#define PWR_IDSC_CTRL2__IDSC_FADC_ADJ_MASK__CI 0x0001e000L -#define PWR_IDSC_CTRL2__IDSC_FADC_CALIBRATE_MASK__CI 0x00020000L -#define PWR_IDSC_CTRL2__IDSC_FX_ADJ_MASK__CI 0x003c0000L -#define PWR_IDSC_CTRL2__IDSC_FX_CALIBRATE_MASK__CI 0x00400000L -#define PWR_IDSC_CTRL2__IDSC_LEGACY_MODE_MASK__CI 0x00000008L -#define PWR_IDSC_CTRL2__IDSC_MCLK_FREQ_MASK__CI 0x00001e00L -#define PWR_IDSC_CTRL2__IDSC_SWITCHING_FREQ_MASK__CI 0x000000c0L -#define PWR_IDSC_CTRL2__IDSC_TWO_PHASE_MASK__CI 0x00000020L -#define PWR_IDSC_CTRL__CMON_ADC_CFG_MASK__CI 0x00003000L -#define PWR_IDSC_CTRL__CMON_ADC_GAIN_ADJ_MASK__CI 0x00000f80L -#define PWR_IDSC_CTRL__CMON_ADC_GAIN_ADJ_MODE_MASK__CI 0x80000000L -#define PWR_IDSC_CTRL__CMON_BGADJ_MASK__CI 0x0000007eL -#define PWR_IDSC_CTRL__CMON_BGADJ_MODE_MASK__CI 0x40000000L -#define PWR_IDSC_CTRL__CMON_DAC_BYPASS_MASK__CI 0x0ffc0000L -#define PWR_IDSC_CTRL__CMON_OFFSET_CAN_EN_MASK__CI 0x10000000L -#define PWR_IDSC_CTRL__CMON_PDB_MASK__CI 0x00000001L -#define PWR_IDSC_CTRL__CMON_SELF_CAL_EN_MASK__CI 0x20000000L -#define PWR_IDSC_CTRL__CMON_TESTCNTL_MASK__CI 0x0003c000L -#define PWR_INT_GPIO_CLEAR__INT_GPIO_CLEAR_MASK__CI 0xffffffffL -#define PWR_INT_GPIO_PENDING__INT_GPIO_PENDING_MASK__CI 0xffffffffL -#define PWR_INT_GPIO_POLARITY__INT_GPIO_POLARITY_MASK__CI 0xffffffffL -#define PWR_INT_GPIO_SENSE__INT_GPIO_SENSE_MASK__CI 0xffffffffL -#define PWR_MM_CNTL__CG_DCO_CLK_SLOW_MASK__CI__VI 0x00000002L -#define PWR_MM_CNTL__CG_VCE_CLK_SLOW_MASK__CI__VI 0x00000001L -#define PWR_MM_CNTL__DCO_CG_CLK_SLOW_ACK_MASK__CI__VI 0x00008000L -#define PWR_MM_CNTL__DC_SMU_EVENT_INTERRUPT_MASK__CI__VI 0x00000004L -#define PWR_MM_CNTL__UVD_CG_CLK_SWITCH_ACK_MASK__CI__VI 0x00010000L -#define PWR_MM_CNTL__VCE_CG_CLK_SLOW_ACK_MASK__CI__VI 0x00004000L -#define PWR_MM_CNTL__VCE_CG_CLK_SWITCH_ACK_MASK__CI__VI 0x00020000L -#define PWR_RLC_CNTL__RLC_CGCG_OVERRIDE_OFF_MASK__CI__VI 0x00000001L -#define PWR_RLC_CNTL__RLC_CGCG_OVERRIDE_ON_MASK__CI__VI 0x00000002L -#define PWR_SMC_IND_DATA__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define PWR_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define PWR_STAT_CNTR_CNTL__CNTR_EN_MASK__CI__VI 0x00040000L -#define PWR_STAT_CNTR_CNTL__DIVIDE_MASK__CI__VI 0x03000000L -#define PWR_STAT_CNTR_CNTL__DPM_STATE_MASK__CI__VI 0x00780000L -#define PWR_STAT_CNTR_CNTL__PERIOD_CNT_MASK__CI__VI 0x00003fffL -#define PWR_STAT_CNTR_CNTL__SEL_MASK__CI__VI 0xf0000000L -#define PWR_STAT_CNTR_CNTL__UNIT_CNT_MASK__CI__VI 0x0003c000L -#define PWR_STAT_CNTR_EVENT_0__EVENT_0_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_1__EVENT_1_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_2__EVENT_2_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_3__EVENT_3_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_4__EVENT_4_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_5__EVENT_5_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_6__EVENT_6_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_7__EVENT_7_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_EVENT_8__EVENT_8_TIMES_CNT_MASK__CI__VI 0x0000ffffL -#define PWR_STAT_CNTR_TIME__BUF_EMPTY_MASK__CI__VI 0x80000000L -#define PWR_STAT_CNTR_TIME__BUF_POP_MASK__CI__VI 0x40000000L -#define PWR_STAT_CNTR_TIME__EVENT_CYCLES_CNT_MASK__CI__VI 0x0003ffffL -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_0_SELECT_MASK__CI__VI 0x000000e0L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_1_SELECT_MASK__CI__VI 0x00000700L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_2_SELECT_MASK__CI__VI 0x00003800L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_3_SELECT_MASK__CI__VI 0x0001c000L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_4_SELECT_MASK__CI__VI 0x000e0000L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_5_SELECT_MASK__CI__VI 0x00700000L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_6_SELECT_MASK__CI__VI 0x03800000L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_7_SELECT_MASK__CI__VI 0x1c000000L -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_8_SELECT_MASK__CI__VI 0xe0000000L -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_0_MASK__CI__VI 0x0000000fL -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_1_MASK__CI__VI 0x000000f0L -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_2_MASK__CI__VI 0x00000f00L -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_3_MASK__CI__VI 0x0000f000L -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_0_MASK__CI__VI 0x0000001fL -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_1_MASK__CI__VI 0x000003e0L -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_2_MASK__CI__VI 0x00007c00L -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_3_MASK__CI__VI 0x000f8000L -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_4_MASK__CI__VI 0x01f00000L -#define PWR_SVI2_PLANE1_LOAD__LOADLINE_MASK__CI 0x0000001fL -#define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK__CI 0x00000040L -#define PWR_SVI2_PLANE1_LOAD__PSI0_VID_MASK__CI 0x00007f80L -#define PWR_SVI2_PLANE1_LOAD__PSI1_MASK__CI 0x00000020L -#define PWR_SVI2_PLANE1_LOAD__WAIT_VID_COMP_DIS_MASK__CI 0x00008000L -#define PWR_SVI2_PLANE2_LOAD__LOADLINE_MASK__CI 0x0000001fL -#define PWR_SVI2_PLANE2_LOAD__PSI0_EN_MASK__CI 0x00000040L -#define PWR_SVI2_PLANE2_LOAD__PSI0_VID_MASK__CI 0x00007f80L -#define PWR_SVI2_PLANE2_LOAD__PSI1_MASK__CI 0x00000020L -#define PWR_SVI2_STATUS__DELAY_CNT_BUSY_MASK__CI 0x00040000L -#define PWR_SVI2_STATUS__PLANE1_VID_MASK__CI 0x000000ffL -#define PWR_SVI2_STATUS__PLANE2_VID_MASK__CI 0x0000ff00L -#define PWR_SVI2_STATUS__SVI2_BUSY_MASK__CI 0x00020000L -#define PWR_SVI2_STATUS__VID_CHANGE_BUSY_MASK__CI 0x00010000L -#define PWR_SVI2_TELEMETRY_1__IDD_INFO_MASK__CI 0x000001ffL -#define PWR_SVI2_TELEMETRY_1__VDD_INFO_MASK__CI 0x01ff0000L -#define PWR_SVI2_TELEMETRY_2__IDD_INFO_MASK__CI 0x000001ffL -#define PWR_SVI2_TELEMETRY_2__VDD_INFO_MASK__CI 0x01ff0000L -#define PWR_SVI2_TFN__SVI2_HIGH_FREQ_SEL_MASK__CI 0x00000004L -#define PWR_SVI2_TFN__TFN_CTRL_MASK__CI 0x00000003L -#define PWR_SVI2_THERM_CNTL__THERM_TRIP_MASK__CI 0x00000100L -#define PWR_SVI2_THERM_CNTL__THERM_VID_MASK__CI 0x000000ffL -#define PWR_SVI2_VID__NB_VSTIME_MASK__CI 0x00003800L -#define PWR_SVI2_VID__SEND_VID_EN_MASK__CI 0x00000400L -#define PWR_SVI2_VID__SVID_CODE_MASK__CI 0x000000ffL -#define PWR_SVI2_VID__VID_PLANE_MASK__CI 0x00000300L -#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL -#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffffL -#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffffL -#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffffL -#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffffL -#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL -#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK__SI__CI 0xffffffffL -#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffffL -#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffffL -#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffffL -#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffffL -#define RCU_ASIC_SERIAL_NUM0__BITS31_0_MASK__SI 0xffffffffL -#define RCU_ASIC_SERIAL_NUM1__BITS49_32_MASK__SI 0x0003ffffL -#define RCU_BACKUP_STRAP0__BITS_MASK__SI 0xffffffffL -#define RCU_BACKUP_STRAP1__BITS_MASK__SI 0xffffffffL -#define RCU_BACKUP_STRAP2__BITS_MASK__SI 0xffffffffL -#define RCU_BACKUP_STRAP3__BITS_MASK__SI 0xffffffffL -#define RCU_CC_ATC_FUSE__TRANSLATE_SECURE_MASK__SI 0x00000002L -#define RCU_CC_ATC_FUSE__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_AZALIA_ID__BITS_MASK__SI 0x00000078L -#define RCU_CC_BIF_AZALIA_ID__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_ID_STRAPS__SPARE_MASK__SI 0x0000000eL -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_ATI_REV_ID_MASK__SI 0xf0000000L -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_F0_DEVICE_ID_MASK__SI 0x000ffff0L -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_F0_MAJOR_REV_ID_MASK__SI 0x00f00000L -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_F0_MINOR_REV_ID_MASK__SI 0x0f000000L -#define RCU_CC_BIF_ID_STRAPS__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_SECURE_CNTL__SECURE_ID_MASK__SI 0xffff0000L -#define RCU_CC_BIF_SECURE_CNTL__SECURE_LVL_MASK__SI 0x00000300L -#define RCU_CC_BIF_SECURE_CNTL__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP0__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP0__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP10__BITS24_5_MASK__SI 0x01ffffe0L -#define RCU_CC_BIF_STRAP10__BITS3_2_MASK__SI 0x0000000cL -#define RCU_CC_BIF_STRAP10__UNUSED31_25_MASK__SI 0xfe000000L -#define RCU_CC_BIF_STRAP10__UNUSED4_MASK__SI 0x00000010L -#define RCU_CC_BIF_STRAP10__UNUSED_MASK__SI 0x00000002L -#define RCU_CC_BIF_STRAP10__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP11__BITS_MASK__SI 0x7ffffffeL -#define RCU_CC_BIF_STRAP11__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP12__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP12__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP13__BITS_MASK__SI 0x01fffffeL -#define RCU_CC_BIF_STRAP13__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP14__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP14__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP1__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP1__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP2__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP2__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP3__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP3__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP4__BITS_MASK__SI 0x0ffffffeL -#define RCU_CC_BIF_STRAP4__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP5__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP5__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP6__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP6__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP7__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP7__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP8__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP8__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP9__BITS_MASK__SI 0xfffffffeL -#define RCU_CC_BIF_STRAP9__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_BIF_STRAP_FUSE0__BITS_MASK__SI 0x00007ffeL -#define RCU_CC_BIF_STRAP_FUSE0__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_DC_AUDIO__AUD_PORT_CONN_MASK__SI 0x00000007L -#define RCU_CC_DC_AUDIO__AUD_PORT_CONN_OVR_MASK__SI 0x00000008L -#define RCU_CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK__SI 0x0000007eL -#define RCU_CC_DC_PIPE_DIS__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_GC_RB_REDUNDANCY0__EN_RB_REDUNDANCY_SE0_MASK__SI 0x80000000L -#define RCU_CC_GC_RB_REDUNDANCY0__FAILED_RB_SE0_MASK__SI 0x00070000L -#define RCU_CC_GC_RB_REDUNDANCY0__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_GC_RB_REDUNDANCY1__EN_RB_REDUNDANCY_SE1_MASK__SI 0x80000000L -#define RCU_CC_GC_RB_REDUNDANCY1__FAILED_RB_SE1_MASK__SI 0x00070000L -#define RCU_CC_GC_RB_REDUNDANCY1__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG0__DIS_DPFP_MASK__SI 0x00000002L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG0__INACTIVE_COMPUTE_UNITS_SE0_SH0_MASK__SI 0xffff0000L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG0__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG1__DIS_DPFP_MASK__SI 0x00000002L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG1__INACTIVE_COMPUTE_UNITS_SE0_SH1_MASK__SI 0xffff0000L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG1__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG2__DIS_DPFP_MASK__SI 0x00000002L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG2__INACTIVE_COMPUTE_UNITS_SE1_SH0_MASK__SI 0xffff0000L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG2__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG3__DIS_DPFP_MASK__SI 0x00000002L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG3__INACTIVE_COMPUTE_UNITS_SE1_SH1_MASK__SI 0xffff0000L -#define RCU_CC_GC_SHADER_ARRAY_CONFIG3__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_MC_MAX_CHANNEL__MAX_CHANNELS_MASK__SI 0x0000003eL -#define RCU_CC_MC_MAX_CHANNEL__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_RB_BACKEND_DISABLE0__RB_BACKEND_DISABLE_SE0_SH0_MASK__SI 0x000f0000L -#define RCU_CC_RB_BACKEND_DISABLE0__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_RB_BACKEND_DISABLE1__RB_BACKEND_DISABLE_SE0_SH1_MASK__SI 0x000f0000L -#define RCU_CC_RB_BACKEND_DISABLE1__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_RB_BACKEND_DISABLE2__RB_BACKEND_DISABLE_SE1_SH0_MASK__SI 0x000f0000L -#define RCU_CC_RB_BACKEND_DISABLE2__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_RB_BACKEND_DISABLE3__RB_BACKEND_DISABLE_SE1_SH1_MASK__SI 0x000f0000L -#define RCU_CC_RB_BACKEND_DISABLE3__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_TCC_DISABLE__TCC_DISABLE_MASK__SI 0xffff0000L -#define RCU_CC_TCC_DISABLE__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_CC_UVD_DISABLE__UVD_DISABLE_MASK__SI 0x00000002L -#define RCU_CC_UVD_DISABLE__WRITE_DIS_MASK__SI 0x00000001L -#define RCU_DYN_RM2__BF_HD1P_RMEN_MASK__SI 0x00000004L -#define RCU_DYN_RM2__BF_HD1P_RM_MASK__SI 0x00000003L -#define RCU_DYN_RM2__BF_PDP_RMEN_MASK__SI 0x00000020L -#define RCU_DYN_RM2__BF_PDP_RM_MASK__SI 0x00000018L -#define RCU_DYN_RM2__BF_RF2P_RMEN_MASK__SI 0x00000100L -#define RCU_DYN_RM2__BF_RF2P_RM_MASK__SI 0x000000c0L -#define RCU_DYN_RM2__GFX_HD1P_RMEN_MASK__SI 0x00000800L -#define RCU_DYN_RM2__GFX_HD1P_RM_MASK__SI 0x00000600L -#define RCU_DYN_RM2__GFX_PDP_RMEN_MASK__SI 0x00004000L -#define RCU_DYN_RM2__GFX_PDP_RM_MASK__SI 0x00003000L -#define RCU_DYN_RM2__GFX_RF2P_RMEN_MASK__SI 0x00020000L -#define RCU_DYN_RM2__GFX_RF2P_RM_MASK__SI 0x00018000L -#define RCU_DYN_RM2__UVD_HD1P_RMEN_MASK__SI 0x00100000L -#define RCU_DYN_RM2__UVD_HD1P_RM_MASK__SI 0x000c0000L -#define RCU_DYN_RM2__UVD_PDP_RMEN_MASK__SI 0x00800000L -#define RCU_DYN_RM2__UVD_PDP_RM_MASK__SI 0x00600000L -#define RCU_DYN_RM2__UVD_RF2P_RMEN_MASK__SI 0x04000000L -#define RCU_DYN_RM2__UVD_RF2P_RM_MASK__SI 0x03000000L -#define RCU_DYN_RM__DT_HD1P_RMEN_MASK__SI 0x00100000L -#define RCU_DYN_RM__DT_HD1P_RM_MASK__SI 0x000c0000L -#define RCU_DYN_RM__DT_PDP_RMEN_MASK__SI 0x00800000L -#define RCU_DYN_RM__DT_PDP_RM_MASK__SI 0x00600000L -#define RCU_DYN_RM__DT_RF2P_RMEN_MASK__SI 0x04000000L -#define RCU_DYN_RM__DT_RF2P_RM_MASK__SI 0x03000000L -#define RCU_DYN_RM__MC_HD1P_RMEN_MASK__SI 0x00000800L -#define RCU_DYN_RM__MC_HD1P_RM_MASK__SI 0x00000600L -#define RCU_DYN_RM__MC_PDP_RMEN_MASK__SI 0x00004000L -#define RCU_DYN_RM__MC_PDP_RM_MASK__SI 0x00003000L -#define RCU_DYN_RM__MC_RF2P_RMEN_MASK__SI 0x00020000L -#define RCU_DYN_RM__MC_RF2P_RM_MASK__SI 0x00018000L -#define RCU_DYN_RM__RM_REG_SEL_MASK__SI 0x08000000L -#define RCU_DYN_RM__SYS_HD1P_RMEN_MASK__SI 0x00000004L -#define RCU_DYN_RM__SYS_HD1P_RM_MASK__SI 0x00000003L -#define RCU_DYN_RM__SYS_PDP_RMEN_MASK__SI 0x00000020L -#define RCU_DYN_RM__SYS_PDP_RM_MASK__SI 0x00000018L -#define RCU_DYN_RM__SYS_RF2P_RMEN_MASK__SI 0x00000100L -#define RCU_DYN_RM__SYS_RF2P_RM_MASK__SI 0x000000c0L -#define RCU_EFUSE_SCRATCH__GENERIC_BIOS_SCRATCH_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS0__EFUSE_BITS31_0_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS10__EFUSE_BITS351_320_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS11__EFUSE_BITS383_352_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS12__EFUSE_BITS415_384_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS13__EFUSE_BITS447_416_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS14__EFUSE_BITS479_448_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS15__EFUSE_BITS511_480_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS16__EFUSE_BITS543_512_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS17__EFUSE_BITS575_544_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS18__EFUSE_BITS607_576_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS19__EFUSE_BITS639_608_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS1__EFUSE_BITS63_32_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS20__EFUSE_BITS671_640_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS21__EFUSE_BITS703_672_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS22__EFUSE_BITS735_704_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS23__EFUSE_BITS767_736_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS24__EFUSE_BITS799_768_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS25__EFUSE_BITS831_800_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS26__EFUSE_BITS863_832_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS27__EFUSE_BITS895_864_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS28__EFUSE_BITS927_896_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS29__EFUSE_BITS959_928_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS2__EFUSE_BITS95_64_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS30__EFUSE_BITS991_960_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS31__EFUSE_BITS1023_992_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS32__EFUSE_BITS1055_1024_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS33__EFUSE_BITS1087_1056_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS34__EFUSE_BITS1119_1088_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS35__EFUSE_BITS1151_1120_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS36__EFUSE_BITS1183_1152_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS37__EFUSE_BITS1215_1184_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS38__EFUSE_BITS1247_1216_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS39__EFUSE_BITS1279_1248_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS3__EFUSE_BITS127_96_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS40__EFUSE_BITS1311_1280_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS4__EFUSE_BITS159_128_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS5__EFUSE_BITS191_160_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS6__EFUSE_BITS223_192_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS7__EFUSE_BITS255_224_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS8__EFUSE_BITS287_256_MASK__SI 0xffffffffL -#define RCU_EFUSE_STRAPS9__EFUSE_BITS319_288_MASK__SI 0xffffffffL -#define RCU_FCTRL__DRM_START_MASK__SI 0x00000001L -#define RCU_FCTRL__EFUSE_PD_MASK__SI 0x00000004L -#define RCU_FCTRL__FSM_RST_MASK__SI 0x00000008L -#define RCU_FCTRL__HDCP_START_MASK__SI 0x00000002L -#define RCU_FCTRL__SPARE2_MASK__SI 0x00003fc0L -#define RCU_FCTRL__TCLK_DIS_MASK__SI 0x00000020L -#define RCU_FCTRL__UVD_START_MASK__SI 0x00000010L -#define RCU_IND_DATA__RCU_IND_DATA_MASK__SI 0xffffffffL -#define RCU_IND_INDEX__RCU_IND_ADDR_MASK__SI 0x00001fffL -#define RCU_MISC_CTRL__BIF_RST_DIS_MASK__SI 0x00000004L -#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK__CI__VI 0x00010000L -#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK__CI__VI 0x00020000L -#define RCU_MISC_CTRL__CG_RST_GLB_REQ_DIS_MASK__SI 0x00000020L -#define RCU_MISC_CTRL__DRV_RST_MODE_MASK__SI 0x00000001L -#define RCU_MISC_CTRL__FCTRL_IDLE_DIS_MASK__SI 0x00000080L -#define RCU_MISC_CTRL__HDCP_START_MASK__CI__VI 0x00200000L -#define RCU_MISC_CTRL__IGNORE_CG_ACK_MASK__SI 0x00000002L -#define RCU_MISC_CTRL__IGNORE_DRM_RD_DONE_MASK__SI 0x00000200L -#define RCU_MISC_CTRL__JTAG_SRBM_DIS_MASK__SI 0x00000008L -#define RCU_MISC_CTRL__MEM_REP_4BIFRST_DIS_MASK__SI 0x00000100L -#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK__CI__VI 0x00000010L -#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK__CI__VI 0x00000100L -#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK__CI__VI 0x00000002L -#define RCU_MISC_CTRL__REG_HDCP_FUSE_DISABLE_MASK__CI__VI 0x00000080L -#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK__CI__VI 0x00000008L -#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK__CI__VI 0x00000020L -#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK__CI__VI 0xff800000L -#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK__SI 0x000ffc00L -#define RCU_MISC_CTRL__SAMU_START_MASK__CI__VI 0x00400000L -#define RCU_MISC_CTRL__SPARE_MASK__SI 0x00000040L -#define RCU_MISC_CTRL__TST_TCLK_SLOW_EN_MASK__SI 0x00000010L -#define RCU_PCIECONFIG__PCIE_gfx_early_reset_MASK__CI__VI 0x00000001L -#define RCU_PCIECONFIG__PCIE_gfx_hard_reset_MASK__CI__VI 0x00000002L -#define RCU_PCIECONFIG__PCIE_reset_override_MASK__CI__VI 0x00000004L -#define RCU_ROM_BIF_STRAP0__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP0__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP10__BITS24_5_MASK__SI 0x01ffffe0L -#define RCU_ROM_BIF_STRAP10__BITS3_2_MASK__SI 0x0000000cL -#define RCU_ROM_BIF_STRAP10__UNUSED31_25_MASK__SI 0xfe000000L -#define RCU_ROM_BIF_STRAP10__UNUSED4_MASK__SI 0x00000010L -#define RCU_ROM_BIF_STRAP10__UNUSED_MASK__SI 0x00000003L -#define RCU_ROM_BIF_STRAP11__BITS_MASK__SI 0x7ffffffeL -#define RCU_ROM_BIF_STRAP11__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP12__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP12__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP13__BITS_MASK__SI 0x01fffffeL -#define RCU_ROM_BIF_STRAP13__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP14__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP14__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP1__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP1__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP2__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP2__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP3__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP3__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP4__BITS_MASK__SI 0x0ffffffeL -#define RCU_ROM_BIF_STRAP4__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP5__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP5__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP6__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP6__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP7__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP7__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP8__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP8__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_BIF_STRAP9__BITS_MASK__SI 0xfffffffeL -#define RCU_ROM_BIF_STRAP9__UNUSED_MASK__SI 0x00000001L -#define RCU_ROM_MSC_STRAPS0__ATI_REV_ID_MASK__SI 0x1e000000L -#define RCU_ROM_MSC_STRAPS0__DEVICE_ID_MASK__SI 0x01fffe00L -#define RCU_ROM_MSC_STRAPS0__HDCP_DIS_MASK__SI 0x00000004L -#define RCU_ROM_MSC_STRAPS0__MC_ATC_MASK__SI 0x00000100L -#define RCU_ROM_MSC_STRAPS0__ROM_VALID_MASK__SI 0x20000000L -#define RCU_ROM_MSC_STRAPS0__SPARE_MASK__SI 0x00000002L -#define RCU_ROM_MSC_STRAPS0__UVD_DISABLE_MASK__SI 0x00000008L -#define RCU_ROM_MSC_STRAPS1__INACTIVE_COMPUTE_UNITS_SE0_SH0_MASK__SI 0x0000ffffL -#define RCU_ROM_MSC_STRAPS1__INACTIVE_COMPUTE_UNITS_SE0_SH1_MASK__SI 0xffff0000L -#define RCU_ROM_MSC_STRAPS2__INACTIVE_COMPUTE_UNITS_SE1_SH0_MASK__SI 0x0000ffffL -#define RCU_ROM_MSC_STRAPS2__INACTIVE_COMPUTE_UNITS_SE1_SH1_MASK__SI 0xffff0000L -#define RCU_ROM_MSC_STRAPS3__AUD_PORT_CONN_MASK__SI 0x00070000L -#define RCU_ROM_MSC_STRAPS3__AUD_PORT_CONN_OVR_MASK__SI 0x00080000L -#define RCU_ROM_MSC_STRAPS3__BITS_MASK__SI 0xfff00000L -#define RCU_ROM_MSC_STRAPS3__VM_SECURE_ID_MASK__SI 0x0000ffffL -#define RCU_ROM_MSC_STRAPS4__EN_RB_REDUNDANCY_SE0_MASK__SI 0x00400000L -#define RCU_ROM_MSC_STRAPS4__EN_RB_REDUNDANCY_SE1_MASK__SI 0x00800000L -#define RCU_ROM_MSC_STRAPS4__FAILED_RB_SE0_MASK__SI 0x00070000L -#define RCU_ROM_MSC_STRAPS4__FAILED_RB_SE1_MASK__SI 0x00380000L -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE0_SH0_MASK__SI 0x0000000fL -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE0_SH1_MASK__SI 0x000000f0L -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE1_SH0_MASK__SI 0x00000f00L -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE1_SH1_MASK__SI 0x0000f000L -#define RCU_ROM_MSC_STRAPS5__TCC_DISABLE_MASK__SI 0x0000ffffL -#define RCU_ROM_MSC_STRAPS5__UNUSED_MASK__SI 0xffff0000L -#define RCU_ROM_SPARE_STRAP0__BITS_MASK__SI 0xffffffffL -#define RCU_ROM_SPARE_STRAP1__BITS_MASK__SI 0xffffffffL -#define RCU_ROM_SPARE_STRAP2__BITS_MASK__SI 0xffffffffL -#define RCU_ROM_SPARE_STRAP3__BITS_MASK__SI 0xffffffffL -#define RCU_SCRATCH_0__SCRATCH_0_MASK__SI 0xffffffffL -#define RCU_SCRATCH_1__SCRATCH_1_MASK__SI 0xffffffffL -#define RCU_SCRATCH_2__SCRATCH_2_MASK__SI 0xffffffffL -#define RCU_SPARE_EFUSE__WORD_READ_MASK__SI 0xffffffffL -#define RCU_STATUS__BIF_RST_COUNT_MASK__SI 0x0000ff00L -#define RCU_STATUS__EFUSE_RF_MASK__SI 0x00000030L -#define RCU_STATUS__FCTRL_SPARE_RD_VLD_MASK__SI 0x00000080L -#define RCU_STATUS__FUSES_PROGRAMMED_MASK__SI 0x10000000L -#define RCU_STATUS__RCU_UC_PC_MASK__SI 0x0fff0000L -#define RCU_STATUS__UVD_SMU_EFUSE_RDY_MASK__SI 0x00000040L -#define RCU_SYSRESET__ACP_hard_resetb_MASK__CI 0x00200000L -#define RCU_SYSRESET__BIF_cec_hard_resetb_MASK__CI__VI 0x00008000L -#define RCU_SYSRESET__DC_az_hard_resetb_MASK__CI 0x00020000L -#define RCU_SYSRESET__GCK_hard_resetb_MASK__CI__VI 0x00000001L -#define RCU_SYSRESET__GIO_rst_early_resetb_MASK__CI__VI 0x00000010L -#define RCU_SYSRESET__GIO_rst_hard_resetb_MASK__CI__VI 0x00000100L -#define RCU_SYSRESET__IOMMU_hard_resetb_MASK__CI 0x01000000L -#define RCU_SYSRESET__PCIE_powergood_MASK__CI__VI 0x00000400L -#define RCU_SYSRESET__RB0_hard_resetb_MASK__CI 0x00400000L -#define RCU_SYSRESET__RB1_hard_resetb_MASK__CI 0x00800000L -#define RCU_SYSRESET__TARG_early_resetb_MASK__CI__VI 0x00000020L -#define RCU_SYSRESET__UVD_hard_resetb_MASK__CI 0x00080000L -#define RCU_SYSRESET__VCE_hard_resetb_MASK__CI 0x00100000L -#define RCU_SYSRESET__VDDC_hard_resetb_MASK__CI__VI 0x00010000L -#define RCU_UC_EVENTS_DATA__BIF_STRAPS_WRITTEN_MASK__SI 0x00010000L -#define RCU_UC_EVENTS_DATA__CC_EFUSE_BYTE1_RDVLD_MASK__SI 0x00000004L -#define RCU_UC_EVENTS_DATA__CC_EFUSE_RDVLD_MASK__SI 0x00000008L -#define RCU_UC_EVENTS_DATA__CONFIG_DONE_MASK__SI 0x00000020L -#define RCU_UC_EVENTS_DATA__DRM_EFUSE_RD_DONE_MASK__SI 0x00000200L -#define RCU_UC_EVENTS_DATA__HARD_RST_DONE_MASK__SI 0x00000010L -#define RCU_UC_EVENTS_DATA__MEM_HARDREP_DONE_MASK__SI 0x00000100L -#define RCU_UC_EVENTS_DATA__PINSTRAP_CC_BYPASS_MASK__SI 0x00000002L -#define RCU_UC_EVENTS_DATA__PINSTRAP_MEM_HARDREP_MASK__SI 0x00000040L -#define RCU_UC_EVENTS_DATA__PINSTRAP_ROMEXIST_MASK__SI 0x00000001L -#define RCU_UC_EVENTS_DATA__UC_FLAG_MASK__SI 0x00000400L -#define RCU_UC_EVENTS_DATA__UC_SET_EVENT_MASK__SI 0x00fe0000L -#define RCU_UC_EVENTS_DATA__UVD_RD_DONE_MASK__SI 0x00001000L -#define RCU_UC_EVENTS__BIF_STRAPS_WRITTEN_MASK__SI 0x00010000L -#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK__CI__VI 0x00000200L -#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK__CI__VI 0x00000400L -#define RCU_UC_EVENTS__CC_EFUSE_BYTE1_RDVLD_MASK__SI 0x00000004L -#define RCU_UC_EVENTS__CC_EFUSE_FDO_RDVLD_MASK__SI 0x00004000L -#define RCU_UC_EVENTS__CC_EFUSE_RDVLD_MASK__SI 0x00000008L -#define RCU_UC_EVENTS__CC_EFUSE_RM_RDVLD_MASK__SI 0x00002000L -#define RCU_UC_EVENTS__CONFIG_DONE_MASK__SI 0x00000020L -#define RCU_UC_EVENTS__DRM_EFUSE_RD_DONE_MASK__SI 0x00000200L -#define RCU_UC_EVENTS__FCH_HALT_MASK__CI__VI 0x00000800L -#define RCU_UC_EVENTS__FCH_LOCKDOWN_WRITE_DIS_MASK__CI__VI 0x00001000L -#define RCU_UC_EVENTS__HARD_RST_DONE_MASK__SI 0x00000010L -#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK__CI__VI 0x00010000L -#define RCU_UC_EVENTS__MEM_HARDREP_DONE_MASK__SI 0x00000100L -#define RCU_UC_EVENTS__PINSTRAP_CC_BYPASS_MASK__SI 0x00000002L -#define RCU_UC_EVENTS__PINSTRAP_MEM_HARDREP_MASK__SI 0x00000040L -#define RCU_UC_EVENTS__PINSTRAP_ROMEXIST_MASK__SI 0x00000001L -#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK__CI__VI 0x00020000L -#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK__CI__VI 0x00040000L -#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK__CI__VI 0x00080000L -#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK__CI__VI 0x00002000L -#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK__CI__VI 0x00000001L -#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK__CI__VI 0x00000008L -#define RCU_UC_EVENTS__TP_Tester_MASK__CI__VI 0x00000040L -#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK__CI__VI 0x00000002L -#define RCU_UC_EVENTS__UC_FLAG_MASK__SI 0x00000400L -#define RCU_UC_EVENTS__UC_SET_EVENT_MASK__SI 0x00fe0000L -#define RCU_UC_EVENTS__UVD_RD_DONE_MASK__SI 0x00001000L -#define RCU_UC_EVENTS__boot_seq_done_MASK__CI__VI 0x00000080L -#define RCU_UC_EVENTS__drv_rst_mode_MASK__CI__VI 0x00000004L -#define RCU_UC_EVENTS__lm32_irq31_sel_MASK__CI__VI 0x03000000L -#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK__CI__VI 0x00000100L -#define RCU_UC_INT__DRV_ADDR_MASK__SI 0x007fc000L -#define RCU_UC_INT__INT_ADDR_MASK__SI 0x00003fe0L -#define RCU_UC_INT__INT_EN_MASK__SI 0x00000001L -#define RCU_UC_INT__INT_TRIG_MASK__SI 0x00000002L -#define RCU_UC_INT__VC3D_ADDR_MASK__SI 0xff800000L -#define RCU_UC_ROMRD_INSTR__ROM_DATA_MASK__SI 0xffff0000L -#define RCU_UC_ROMRD_INSTR__ROM_INDEX_MASK__SI 0x0000ffffL -#define REQ_FIFO_STAT__REQ_FIFO_LEVEL_MASK__SI 0x0000003fL -#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK__SI 0x000000ffL -#define REVISION_ID__MAJOR_REV_ID_MASK 0x000000f0L -#define REVISION_ID__MINOR_REV_ID_MASK 0x0000000fL -#define RE_CTL2_B__DISABLE_SHIFTER_BIT_CNT_B_MASK__SI 0x80000000L -#define RE_CTL2_B__MAX_BYTES_B_MASK__SI 0x00ffffffL -#define RE_CTL2_B__SHIFTER_BIT_CNT_RST_B_MASK__SI 0x40000000L -#define RE_CTL2_B__SW_FEED_EMPTY_B_MASK__SI 0x20000000L -#define RE_CTL2__DISABLE_SHIFTER_BIT_CNT_MASK__SI 0x80000000L -#define RE_CTL2__MAX_BYTES_MASK__SI 0x00ffffffL -#define RE_CTL2__SHIFTER_BIT_CNT_RST_MASK__SI 0x40000000L -#define RE_CTL2__SW_FEED_EMPTY_MASK__SI 0x20000000L -#define RE_CTL__EMU_REMOVE_DIS_B_MASK__SI 0x00008000L -#define RE_CTL__EMU_REMOVE_DIS_MASK__SI 0x00000020L -#define RE_CTL__PURGE_DIS_MASK__SI 0x00004000L -#define RE_CTL__QUEUE_BYPASS_MASK__SI 0x01000000L -#define RE_CTL__QUEUE_TIMEOUT_COUNT_MASK__SI 0x00003f00L -#define RE_CTL__QUEUE_TIMEOUT_EN_MASK__SI 0x00000040L -#define RE_CTL__REG_CMD_RESULT_MASK__SI 0x00000010L -#define RE_CTL__RE_PURGE_COUNT_MASK__SI 0x00ff0000L -#define RE_CTL__STANDARD_MASK__SI 0x0000000fL -#define RE_CTL__STREAM_B_SEL_MASK__SI 0x00000080L -#define RE_CTL__SW_BRST_B_MASK__SI 0x08000000L -#define RE_CTL__SW_BRST_MASK__SI 0x40000000L -#define RE_CTL__SW_RRST2_B_MASK__SI 0x04000000L -#define RE_CTL__SW_RRST2_MASK__SI 0x10000000L -#define RE_CTL__SW_RRST_MASK__SI 0x20000000L -#define RE_CTL__SW_SRST_MASK__SI 0x80000000L -#define RE_DEBUG_INT_STAT__BIN_IDX_ERR_MASK__SI 0x00001000L -#define RE_DEBUG_INT_STAT__CABAC_INIT_DONE_MASK__SI 0x00000001L -#define RE_DEBUG_INT_STAT__FEED_EMPTY_ERR_MASK__SI 0x00000800L -#define RE_DEBUG_INT_STAT__LP_DEC_ERR_MASK__SI 0x00000010L -#define RE_DEBUG_INT_STAT__MB_RES_DONE_MASK__SI 0x00000004L -#define RE_DEBUG_INT_STAT__OVERRUN_ERR_MASK__SI 0x00000100L -#define RE_DEBUG_INT_STAT__PES_SC_FOUND_MASK__SI 0x00002000L -#define RE_DEBUG_INT_STAT__QUEUE_TIMEOUT_ERR_MASK__SI 0x00004000L -#define RE_DEBUG_INT_STAT__RB_DEC_ERR_MASK__SI 0x00000040L -#define RE_DEBUG_INT_STAT__SHIFTER_OVERRUN_ERR_MASK__SI 0x00000400L -#define RE_DEBUG_INT_STAT__SI_B_MASK__SI 0x00008000L -#define RE_DEBUG_INT_STAT__SI_MASK__SI 0x00000002L -#define RE_DEBUG_INT_STAT__T1TC_DEC_ERR_MASK__SI 0x00000008L -#define RE_DEBUG_INT_STAT__TIMEOUT_ERR_MASK__SI 0x00000200L -#define RE_DEBUG_INT_STAT__TZ_DEC_ERR_MASK__SI 0x00000020L -#define RE_DEBUG_INT_STAT__UE_DEC_ERR_MASK__SI 0x00000080L -#define RE_DEBUG_SI_B__DAT_MASK__SI 0xffffffffL -#define RE_DEBUG_SI__DAT_MASK__SI 0xffffffffL -#define RE_DECODE_CMD__MBPART_IDX_MASK__SI 0x30000000L -#define RE_DECODE_CMD__NUM_OF_FIXED_BIT_MASK__SI 0x0fffff00L -#define RE_DECODE_CMD__SE_ID_MASK__SI 0x000000ffL -#define RE_DECODE_CMD__SUBMBPART_IDX_MASK__SI 0xc0000000L -#define RE_HW_DEBUG__DAT_MASK__SI 0xffffffffL -#define RE_INT_EN__BIN_IDX_ERR_EN_MASK__SI 0x00001000L -#define RE_INT_EN__CABAC_INIT_DONE_EN_MASK__SI 0x00000001L -#define RE_INT_EN__FEED_EMPTY_ERR_EN_MASK__SI 0x00000800L -#define RE_INT_EN__LP_DEC_ERR_EN_MASK__SI 0x00000010L -#define RE_INT_EN__MB_RES_DONE_EN_MASK__SI 0x00000004L -#define RE_INT_EN__OVERRUN_ERR_EN_MASK__SI 0x00000100L -#define RE_INT_EN__PES_SC_FOUND_EN_MASK__SI 0x00002000L -#define RE_INT_EN__QUEUE_TIMEOUT_ERR_EN_MASK__SI 0x00004000L -#define RE_INT_EN__RB_DEC_ERR_EN_MASK__SI 0x00000040L -#define RE_INT_EN__SHIFTER_OVERRUN_ERR_EN_MASK__SI 0x00000400L -#define RE_INT_EN__SI_B_EN_MASK__SI 0x00008000L -#define RE_INT_EN__SI_EN_MASK__SI 0x00000002L -#define RE_INT_EN__T1TC_DEC_ERR_EN_MASK__SI 0x00000008L -#define RE_INT_EN__TIMEOUT_ERR_EN_MASK__SI 0x00000200L -#define RE_INT_EN__TZ_DEC_ERR_EN_MASK__SI 0x00000020L -#define RE_INT_EN__UE_DEC_ERR_EN_MASK__SI 0x00000080L -#define RE_INT_STAT__BIN_IDX_ERR_MASK__SI 0x00001000L -#define RE_INT_STAT__CABAC_INIT_DONE_MASK__SI 0x00000001L -#define RE_INT_STAT__FEED_EMPTY_ERR_MASK__SI 0x00000800L -#define RE_INT_STAT__LP_DEC_ERR_MASK__SI 0x00000010L -#define RE_INT_STAT__MB_RES_DONE_MASK__SI 0x00000004L -#define RE_INT_STAT__OVERRUN_ERR_MASK__SI 0x00000100L -#define RE_INT_STAT__PES_SC_FOUND_MASK__SI 0x00002000L -#define RE_INT_STAT__QUEUE_TIMEOUT_ERR_MASK__SI 0x00004000L -#define RE_INT_STAT__RB_DEC_ERR_MASK__SI 0x00000040L -#define RE_INT_STAT__SHIFTER_OVERRUN_ERR_MASK__SI 0x00000400L -#define RE_INT_STAT__SI_B_MASK__SI 0x00008000L -#define RE_INT_STAT__SI_MASK__SI 0x00000002L -#define RE_INT_STAT__T1TC_DEC_ERR_MASK__SI 0x00000008L -#define RE_INT_STAT__TIMEOUT_ERR_MASK__SI 0x00000200L -#define RE_INT_STAT__TZ_DEC_ERR_MASK__SI 0x00000020L -#define RE_INT_STAT__UE_DEC_ERR_MASK__SI 0x00000080L -#define RE_LMA_ADR__ADR_MASK__SI 0x000001ffL -#define RE_LMA_CTL__ACCESS_MODE_MASK__SI 0x00000001L -#define RE_LMA_CTL__AUTO_INC_MASK__SI 0x00000040L -#define RE_LMA_CTL__MEMORY_SELECT_MASK__SI 0x00000006L -#define RE_LMA_DAT__DAT_MASK__SI 0xffffffffL -#define RE_PES_CTL__EMU_MASK_RST_B_MASK__SI 0x00040000L -#define RE_PES_CTL__EMU_MASK_RST_MASK__SI 0x00000004L -#define RE_PES_CTL__PES_SC_NBL_ONLY_B_MASK__SI 0x00020000L -#define RE_PES_CTL__PES_SC_NBL_ONLY_MASK__SI 0x00000002L -#define RE_PES_CTL__PES_SC_SUFFIX_B_MASK__SI 0xff000000L -#define RE_PES_CTL__PES_SC_SUFFIX_MASK__SI 0x0000ff00L -#define RE_PES_CTL__PES_STREAM_B_MASK__SI 0x00010000L -#define RE_PES_CTL__PES_STREAM_MASK__SI 0x00000001L -#define RE_PES_DECODE_CMD__PES_NUM_OF_FIXED_BIT_MASK__SI 0x0fffff00L -#define RE_PES_DECODE_CMD__PES_SE_ID_MASK__SI 0x000000ffL -#define RE_PES_RESULT__PES_SYMBOL_MASK__SI 0xffffffffL -#define RE_PES_SHIFTER_STAT__PES_BIT_POS_B_MASK__SI 0x07000000L -#define RE_PES_SHIFTER_STAT__PES_BIT_POS_MASK__SI 0x00000700L -#define RE_PES_SHIFTER_STAT__PES_SHIFTER_REFILL_B_MASK__SI 0x00800000L -#define RE_PES_SHIFTER_STAT__PES_SHIFTER_REFILL_MASK__SI 0x00000080L -#define RE_PES_SHIFTER_STAT__PES_VALID_BITS_B_MASK__SI 0x007f0000L -#define RE_PES_SHIFTER_STAT__PES_VALID_BITS_MASK__SI 0x0000007fL -#define RE_PPS_INFO__CABAC_ENTROPY_FLAG_MASK__SI 0x00000001L -#define RE_PPS_INFO__NUM_REF_IDX_L0_ACTIVE_GT1_MASK__SI 0x00000002L -#define RE_PPS_INFO__NUM_REF_IDX_L1_ACTIVE_GT1_MASK__SI 0x00000004L -#define RE_PPS_INFO__PIC_HEIGHT7_3_MASK__SI 0x000000f8L -#define RE_PPS_INFO__PIC_HEIGHT_DIV3_MASK__SI 0x003f0000L -#define RE_PPS_INFO__PIC_HEIGHT_MOD3_MASK__SI 0x00c00000L -#define RE_PPS_INFO__PIC_WIDTH_DIV3_MASK__SI 0x3f000000L -#define RE_PPS_INFO__PIC_WIDTH_MASK__SI 0x0000ff00L -#define RE_PPS_INFO__PIC_WIDTH_MOD3_MASK__SI 0xc0000000L -#define RE_RESULT__SYMBOL_MASK__SI 0xffffffffL -#define RE_SHIFTER_B_STAT2__BIT_POS_B_MASK__SI 0xe0000000L -#define RE_SHIFTER_B_STAT2__SHIFTER_BIT_CNT_B_MASK__SI 0x07ffffffL -#define RE_SHIFTER_CTXT__DAT_MASK__SI 0xffffffffL -#define RE_SHIFTER_STAT2__BIT_POS_MASK__SI 0xe0000000L -#define RE_SHIFTER_STAT2__SHIFTER_BIT_CNT_MASK__SI 0x07ffffffL -#define RE_SHIFTER_STAT__SHIFTER_REFILL_B_MASK__SI 0x00800000L -#define RE_SHIFTER_STAT__SHIFTER_REFILL_MASK__SI 0x00000080L -#define RE_SHIFTER_STAT__VALID_BITS_B_MASK__SI 0x007f0000L -#define RE_SHIFTER_STAT__VALID_BITS_MASK__SI 0x0000007fL -#define RE_SHIFTER_STAT__VLD_BITS_BEFORE_SC_B_MASK__SI 0x7f000000L -#define RE_SHIFTER_STAT__VLD_BITS_BEFORE_SC_MASK__SI 0x00007f00L -#define RE_SI_B_CTL__BURST_SIZE_B_MASK__SI 0xfff00000L -#define RE_SI_B_CTL__CLEAN_SHUTDOWN_EN_B_MASK__SI 0x00001000L -#define RE_SI_B_CTL__DEBUG_BUS_SELECT_B_MASK__SI 0x00070000L -#define RE_SI_B_CTL__DISABLE_PARTIAL_DWORD_OUT_B_MASK__SI 0x00000008L -#define RE_SI_B_CTL__DISCARD_DATA_IN_B_MASK__SI 0x00000200L -#define RE_SI_B_CTL__DISCONNECT_CLIENT_READ_B_MASK__SI 0x00000400L -#define RE_SI_B_CTL__DISCONNECT_SI_WRITE_B_MASK__SI 0x00000800L -#define RE_SI_B_CTL__ENDIAN_B_MASK__SI 0x00000010L -#define RE_SI_B_CTL__FIRST_BYTE_START_LOC_B_MASK__SI 0x00000006L -#define RE_SI_B_CTL__REQUEST_EN_B_MASK__SI 0x00000001L -#define RE_SI_B_CTL__RESET_DATA_PATH_B_MASK__SI 0x00004000L -#define RE_SI_B_CTL__RESET_GLOBAL_B_MASK__SI 0x00008000L -#define RE_SI_B_CTL__RESET_REQ_CNTRL_B_MASK__SI 0x00002000L -#define RE_SI_B_CTL__STREAM_ID_B_MASK__SI 0x000000e0L -#define RE_SI_B_CTL__STREAM_ID_EN_B_MASK__SI 0x00000100L -#define RE_SI_B_STAT__ALL_TRANSFER_DONE_STATUS_B_MASK__SI 0x00000010L -#define RE_SI_B_STAT__BYTE_CNT_ERR_B_MASK__SI 0x00000002L -#define RE_SI_B_STAT__CLIENT_RESPONSE_STATUS_B_MASK__SI 0x00000040L -#define RE_SI_B_STAT__CLIENT_STATUS_B_MASK__SI 0x00000300L -#define RE_SI_B_STAT__DEPTH_DATA_FIFO_B_MASK__SI 0x3fc00000L -#define RE_SI_B_STAT__DROP_DATA_FIFO_FULL_ERR_B_MASK__SI 0x00000080L -#define RE_SI_B_STAT__DWORD_MISALIGN_ERR_B_MASK__SI 0x00000001L -#define RE_SI_B_STAT__DWORD_PACKER_VALID_B_MASK__SI 0x00000400L -#define RE_SI_B_STAT__NUM_OUTSTAND_BYTES_B_MASK__SI 0x0007f800L -#define RE_SI_B_STAT__NUM_OUTSTAND_REQ_B_MASK__SI 0x00380000L -#define RE_SI_B_STAT__RECEIVED_FIRST_BYTE_STATUS_B_MASK__SI 0x00000020L -#define RE_SI_B_STAT__REQ_CNT_ERR_B_MASK__SI 0x00000004L -#define RE_SI_B_STAT__SPACE_CNT_ERR_B_MASK__SI 0x00000008L -#define RE_SI_CTL__BURST_SIZE_MASK__SI 0xfff00000L -#define RE_SI_CTL__CLEAN_SHUTDOWN_EN_MASK__SI 0x00001000L -#define RE_SI_CTL__DEBUG_BUS_SELECT_MASK__SI 0x00070000L -#define RE_SI_CTL__DISABLE_PARTIAL_DWORD_OUT_MASK__SI 0x00000008L -#define RE_SI_CTL__DISCARD_DATA_IN_MASK__SI 0x00000200L -#define RE_SI_CTL__DISCONNECT_CLIENT_READ_MASK__SI 0x00000400L -#define RE_SI_CTL__DISCONNECT_SI_WRITE_MASK__SI 0x00000800L -#define RE_SI_CTL__ENDIAN_MASK__SI 0x00000010L -#define RE_SI_CTL__FIRST_BYTE_START_LOC_MASK__SI 0x00000006L -#define RE_SI_CTL__REQUEST_EN_MASK__SI 0x00000001L -#define RE_SI_CTL__RESET_DATA_PATH_MASK__SI 0x00004000L -#define RE_SI_CTL__RESET_GLOBAL_MASK__SI 0x00008000L -#define RE_SI_CTL__RESET_REQ_CNTRL_MASK__SI 0x00002000L -#define RE_SI_CTL__STREAM_ID_EN_MASK__SI 0x00000100L -#define RE_SI_CTL__STREAM_ID_MASK__SI 0x000000e0L -#define RE_SI_INT_CTL__SI_INT_MASK_B_MASK__SI 0x00ff0000L -#define RE_SI_INT_CTL__SI_INT_MASK_MASK__SI 0x000000ffL -#define RE_SI_STAT__ALL_TRANSFER_DONE_STATUS_MASK__SI 0x00000010L -#define RE_SI_STAT__BYTE_CNT_ERR_MASK__SI 0x00000002L -#define RE_SI_STAT__CLIENT_RESPONSE_STATUS_MASK__SI 0x00000040L -#define RE_SI_STAT__CLIENT_STATUS_MASK__SI 0x00000300L -#define RE_SI_STAT__DEPTH_DATA_FIFO_MASK__SI 0x3fc00000L -#define RE_SI_STAT__DROP_DATA_FIFO_FULL_ERR_MASK__SI 0x00000080L -#define RE_SI_STAT__DWORD_MISALIGN_ERR_MASK__SI 0x00000001L -#define RE_SI_STAT__DWORD_PACKER_VALID_MASK__SI 0x00000400L -#define RE_SI_STAT__NUM_OUTSTAND_BYTES_MASK__SI 0x0007f800L -#define RE_SI_STAT__NUM_OUTSTAND_REQ_MASK__SI 0x00380000L -#define RE_SI_STAT__RECEIVED_FIRST_BYTE_STATUS_MASK__SI 0x00000020L -#define RE_SI_STAT__REQ_CNT_ERR_MASK__SI 0x00000004L -#define RE_SI_STAT__SPACE_CNT_ERR_MASK__SI 0x00000008L -#define RE_SLICE_INFO__CABAC_INIT_IDC_MASK__SI 0x00000030L -#define RE_SLICE_INFO__MBAFF_FRAME_FLAG_MASK__SI 0x00000008L -#define RE_SLICE_INFO__NON_FMO_MASK__SI 0x00000040L -#define RE_SLICE_INFO__SLICE_NUM_MASK__SI 0x00ff0000L -#define RE_SLICE_INFO__SLICE_QPY_MASK__SI 0x00003f00L -#define RE_SLICE_INFO__SLICE_TYPE_MASK__SI 0x00000007L -#define RE_SLICE_INFO__VC1_PQINDEXGT8_MASK__SI 0x01000000L -#define RE_SLICE_INFO__VC1_TTFRM_MASK__SI 0xc0000000L -#define RE_SLICE_INFO__VC1_TTMBF_MASK__SI 0x20000000L -#define RE_SLICE_INFO__VC1_TXACFRM2_MASK__SI 0x18000000L -#define RE_SLICE_INFO__VC1_TXACFRM_MASK__SI 0x06000000L -#define RE_SPS_INFO__CHROMA_FORMAT_IDC_MASK__SI 0x00000001L -#define RE_SPS_INFO__MULTI_SC_DIS_MASK__SI 0x00000200L -#define RE_SPS_INFO__QI_ERR_EN_MASK__SI 0x00000100L -#define RE_SPS_INFO__SC_NOSTOP_DIS_MASK__SI 0x00000400L -#define RE_SPS_INFO__STD_VERSION_MASK__SI 0x000000f0L -#define RE_SPS_INFO__VC1_DQUANT_MASK__SI 0x00000006L -#define RE_SPS_INFO__VC1_VSTRANSFORM_MASK__SI 0x00000008L -#define RE_SRAM_RM_CTL__RE_M064X039R2M01S00_RME_MASK__SI 0x00004000L -#define RE_SRAM_RM_CTL__RE_M064X039R2M01S00_RM_MASK__SI 0x00003c00L -#define RE_SRAM_RM_CTL__RE_M144X015R2M04S00_RME_MASK__SI 0x00000200L -#define RE_SRAM_RM_CTL__RE_M144X015R2M04S00_RM_MASK__SI 0x000001e0L -#define RE_SRAM_RM_CTL__RE_M464X008R2M04S00_RME_MASK__SI 0x00000010L -#define RE_SRAM_RM_CTL__RE_M464X008R2M04S00_RM_MASK__SI 0x0000000fL -#define RE_SRAM_RM_CTL__RE_WRM_MASK__SI 0x00078000L -#define RE_STAT__CABAC_CTL_BUSY_MASK__SI 0x00000002L -#define RE_STAT__CABAC_INIT_BUSY_MASK__SI 0x00000001L -#define RE_STAT__CABAC_MVD_BUSY_MASK__SI 0x00000004L -#define RE_STAT__CABAC_RES_BUSY_MASK__SI 0x00000008L -#define RE_STAT__CAVLC_RES_BUSY_MASK__SI 0x00000010L -#define RE_STAT__CTXT_INTF_BUSY_MASK__SI 0x00000040L -#define RE_STAT__REFILL_SI_FIFO_NOT_EMPTY_MASK__SI 0x00000200L -#define RE_STAT__RE_COMMANDS_BUSY_MASK__SI 0x00000100L -#define RE_STAT__RE_PES_COMMANDS_BUSY_MASK__SI 0x00000400L -#define RE_STAT__RLVL_ENC_BUSY_MASK__SI 0x00000020L -#define RE_STAT__SEARCH_START_BUSY_MASK__SI 0x00000080L -#define RINGOSC_MASK__MASK_MASK 0x0000ffffL -#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK__SI 0x00000001L -#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK__SI 0x00000004L -#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK__SI 0x00000002L -#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK__SI 0xffffff80L -#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK__SI 0x0000007fL -#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK__SI 0x000000f0L -#define RIRB_SIZE__RIRB_SIZE_MASK__SI 0x00000003L -#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK__SI 0x00000001L -#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK__SI 0x00000004L -#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK__SI 0xffffffffL -#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK__SI 0x000000ffL -#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK__SI 0x00008000L -#define RI_CRC__CRC_MASK__SI 0x00001fffL -#define RI_CTL__BUS_TIMEOUT_DIS_MASK__SI 0x00000800L -#define RI_CTL__BUS_TIMEOUT_LIMIT_MASK__SI 0x000000f8L -#define RI_CTL__CRC_SEL_MASK__SI 0x00007000L -#define RI_CTL__DEBUG_BUS_SEL_MASK__SI 0x00000700L -#define RI_CTL__RD_DELAY_MASK__SI 0x00000007L -#define RI_DEBUG_INT_STAT__BUS_TIMEOUT_ERR_MASK__SI 0x00000001L -#define RI_INT_EN__BUS_TIMEOUT_ERR_EN_MASK__SI 0x00000001L -#define RI_INT_STAT__BUS_TIMEOUT_ERR_MASK__SI 0x00000001L -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007fff8L -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000L -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffeL -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L -#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK__CI__VI 0x07ffff00L -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK__SI 0x0000ff00L -#define RLC_CGCG_CGLS_CTRL__CGCG_GRBM_CRDT_DELAY_MASK__SI 0x07ff0000L -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L -#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000fcL -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L -#define RLC_CGCG_CGLS_CTRL__SPARE_MASK__SI__CI 0x80000000L -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000fL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000f0L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0fff0000L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000f00L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000f000L -#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffffL -#define RLC_CLEARSTATE_RESTORE_BASE__BASE_MASK__SI 0xffffffffL -#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L -#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L -#define RLC_CNTL__RESERVED_MASK 0xffffff00L -#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L -#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L -#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x00000010L -#define RLC_CURRENT_CONTEXT__CURRENT_CONTEXT_MASK__SI 0x0fffffffL -#define RLC_CURRENT_CONTEXT__RESERVED_MASK__SI 0xf0000000L -#define RLC_CU_STATUS__WORK_PENDING_MASK__CI__VI 0xffffffffL -#define RLC_CU_STATUS__WORK_PENDING_SE0_SH0_MASK__SI 0x000000ffL -#define RLC_CU_STATUS__WORK_PENDING_SE0_SH1_MASK__SI 0x0000ff00L -#define RLC_CU_STATUS__WORK_PENDING_SE1_SH0_MASK__SI 0x00ff0000L -#define RLC_CU_STATUS__WORK_PENDING_SE1_SH1_MASK__SI 0xff000000L -#define RLC_DEBUG_SELECT__F32_SELECT_MASK__SI 0x00003f00L -#define RLC_DEBUG_SELECT__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_DEBUG_SELECT__RESERVED_MASK__SI 0xffff8000L -#define RLC_DEBUG_SELECT__SCRATCH_RAM_ONLY_MASK__SI 0x00004000L -#define RLC_DEBUG_SELECT__SELECT_MASK 0x000000ffL -#define RLC_DEBUG__DATA_MASK 0xffffffffL -#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK__SI__CI 0x00000010L -#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK__SI__CI 0x00000001L -#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK__SI__CI 0x0000000eL -#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK__SI__CI 0xffffffe0L -#define RLC_DRMDMA_CURRENT_CONTEXT__CURRENT_CONTEXT_MASK__SI 0x0fffffffL -#define RLC_DRMDMA_CURRENT_CONTEXT__RESERVED_MASK__SI 0xf0000000L -#define RLC_DRMDMA_HB_RPTR__HB_RPTR_MASK__SI 0xffffffffL -#define RLC_DRMDMA_HB_WPTR_MSB_ADDR__HB_WPTR_MSB_ADDR_MASK__SI 0x000000ffL -#define RLC_DRMDMA_HB_WPTR_MSB_ADDR__RESERVED_MASK__SI 0xffffff00L -#define RLC_DRMDMA_HB_WPTR__HB_WPTR_MASK__SI 0xffffffffL -#define RLC_DRMDMA_RL_BASE__RL_BASE_MASK__SI 0xffffffffL -#define RLC_DRMDMA_RL_SIZE__RESERVED_MASK__SI 0xfffffff0L -#define RLC_DRMDMA_RL_SIZE__RL_SIZE_MASK__SI 0x0000000fL -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE0_SH0_MASK__SI 0x000000ffL -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE0_SH1_MASK__SI 0x0000ff00L -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE1_SH0_MASK__SI 0x00ff0000L -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE1_SH1_MASK__SI 0xff000000L -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK__CI__VI 0xffffffffL -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE0_SH0_MASK__SI 0x000000ffL -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE0_SH1_MASK__SI 0x0000ff00L -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE1_SH0_MASK__SI 0x00ff0000L -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE1_SH1_MASK__SI 0xff000000L -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK__CI__VI 0xffffffffL -#define RLC_GCPM_GENERAL_0__DATA_MASK__SI 0xffffffffL -#define RLC_GCPM_GENERAL_1__DATA_MASK__SI 0xffffffffL -#define RLC_GCPM_GENERAL_2__DATA_MASK__SI 0xffffffffL -#define RLC_GCPM_GENERAL_3__DATA_MASK__SI 0xffffffffL -#define RLC_GCPM_GENERAL_4__DATA_MASK__SI 0xffffffffL -#define RLC_GCPM_GENERAL_5__DATA_MASK__SI 0xffffffffL -#define RLC_GCPM_GENERAL_6__DATA_MASK__SI 0xffffffffL -#define RLC_GCPM_GENERAL_7__DATA_MASK__SI 0xffffffffL -#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK__CI 0xffffffffL -#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK__CI 0xffffff00L -#define RLC_GPM_DEBUG_SELECT__SELECT_MASK__CI__VI 0x000000ffL -#define RLC_GPM_DEBUG__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_0__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_1__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_2__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_3__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_4__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_5__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_6__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_GENERAL_7__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_LOG_ADDR__ADDR_MASK__CI 0xffffffffL -#define RLC_GPM_LOG_CONT__CONT_MASK__CI__VI 0xffffffffL -#define RLC_GPM_LOG_SIZE__SIZE_MASK__CI__VI 0xffffffffL -#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK__CI__VI 0x0000f000L -#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK__CI__VI 0x00100000L -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK__CI__VI 0x00030000L -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK__CI__VI 0x0000000fL -#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK__CI__VI 0xffe00000L -#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK__CI__VI 0x000000f0L -#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK__CI__VI 0x00000f00L -#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK__CI__VI 0x000c0000L -#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK__CI__VI 0x0000f000L -#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK__CI__VI 0x00100000L -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK__CI__VI 0x00030000L -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK__CI__VI 0x0000000fL -#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK__CI__VI 0xffe00000L -#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK__CI__VI 0x000000f0L -#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK__CI__VI 0x00000f00L -#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK__CI__VI 0x000c0000L -#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK__CI__VI 0x000001ffL -#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK__CI__VI 0xfffffe00L -#define RLC_GPM_SCRATCH_DATA__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK__CI__VI 0x00000004L -#define RLC_GPM_STAT__GFX_LS_STATUS_MASK__CI__VI 0x00000008L -#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK__CI__VI 0x00000002L -#define RLC_GPM_STAT__RESERVED_MASK__CI 0xfffffff0L -#define RLC_GPM_STAT__RLC_BUSY_MASK__CI__VI 0x00000001L -#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK__CI__VI 0xfffffff0L -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK__CI__VI 0x00000001L -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK__CI__VI 0x00000002L -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK__CI__VI 0x00000004L -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK__CI__VI 0x00000008L -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK__CI__VI 0x000000ffL -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK__CI__VI 0x0000ff00L -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK__CI__VI 0x00ff0000L -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK__CI__VI 0xff000000L -#define RLC_GPM_UCODE_ADDR__RESERVED_MASK__CI__VI 0xfffff000L -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK__CI__VI 0x00000fffL -#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPM_VMID_THREAD0__RESERVED_MASK__CI 0xfffffff0L -#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK__CI__VI 0x0000000fL -#define RLC_GPM_VMID_THREAD1__RESERVED_MASK__CI 0xfffffff0L -#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK__CI__VI 0x0000000fL -#define RLC_GPR_REG1__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPR_REG2__DATA_MASK__CI__VI 0xffffffffL -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0L -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003fL -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffffL -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffffL -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffffL -#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK__CI__VI 0xffffffffL -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK__CI__VI 0xffffffffL -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE0_SH0_CU_MASK_MASK__SI 0x000000ffL -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE0_SH1_CU_MASK_MASK__SI 0x0000ff00L -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE1_SH0_CU_MASK_MASK__SI 0x00ff0000L -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE1_SH1_CU_MASK_MASK__SI 0xff000000L -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK__CI__VI 0x00000ff0L -#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L -#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L -#define RLC_LB_CNTL__RESERVED_MASK__CI__VI 0xfffff000L -#define RLC_LB_CNTL__RESERVED_MASK__SI 0xfffffff0L -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffffL -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffffL -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK__CI__VI 0xffffffffL -#define RLC_LB_INIT_CU_MASK__SE0_SH0_CU_MASK_MASK__SI 0x000000ffL -#define RLC_LB_INIT_CU_MASK__SE0_SH1_CU_MASK_MASK__SI 0x0000ff00L -#define RLC_LB_INIT_CU_MASK__SE1_SH0_CU_MASK_MASK__SI 0x00ff0000L -#define RLC_LB_INIT_CU_MASK__SE1_SH1_CU_MASK_MASK__SI 0xff000000L -#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000feL -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000ff00L -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000L -#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffffL -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000ffL -#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00L -#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000L -#define RLC_MC_CNTL__RDNFO_URG_MASK 0x00f00000L -#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x08000000L -#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x03000000L -#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x04000000L -#define RLC_MC_CNTL__RESERVED_B_MASK 0x000fe000L -#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000L -#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x00000010L -#define RLC_MC_CNTL__WRNFO_URG_MASK 0x000001e0L -#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x00001e00L -#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x00000008L -#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x00000003L -#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x00000004L -#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00ff0000L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000ff00L -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L -#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK__CI__VI 0xffffffffL -#define RLC_PG_ALWAYS_ON_CU_MASK__SE0_SH1_AON_CU_MASK_MASK__SI 0x0000ff00L -#define RLC_PG_ALWAYS_ON_CU_MASK__SE0_SHO_AON_CU_MASK_MASK__SI 0x000000ffL -#define RLC_PG_ALWAYS_ON_CU_MASK__SE1_SH1_AON_CU_MASK_MASK__SI 0xff000000L -#define RLC_PG_ALWAYS_ON_CU_MASK__SE1_SHO_AON_CU_MASK_MASK__SI 0x00ff0000L -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK__CI__VI 0x00010000L -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L -#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK__CI 0xff000000L -#define RLC_PG_CNTL__RESERVED1_MASK__CI 0x00f80000L -#define RLC_PG_CNTL__RESERVED_MASK__CI 0x0000fff0L -#define RLC_PG_CNTL__RESERVED_MASK__SI 0xfffffff0L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK__CI__VI 0x00040000L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK__CI__VI 0x00020000L -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK__CI__VI 0xffff0000L -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK__CI__VI 0x0000ff00L -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK__CI__VI 0x000000ffL -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK__CI__VI 0x00ff0000L -#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK__CI__VI 0xff000000L -#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK__CI__VI 0x0000ff00L -#define RLC_PG_DELAY__POWER_UP_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_RL_BASE__RL_BASE_MASK__SI 0xffffffffL -#define RLC_RL_SIZE__RESERVED_MASK__SI 0xfffffff0L -#define RLC_RL_SIZE__RL_SIZE_MASK__SI 0x0000000fL -#define RLC_SAFE_MODE__MESSAGE_MASK__CI__VI 0x0000001eL -#define RLC_SAFE_MODE__REQ_MASK__CI 0x00000001L -#define RLC_SAFE_MODE__RESERVED_MASK__CI 0xffffffe0L -#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK__SI__CI 0xffffffffL -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK__CI__VI 0xffffffffL -#define RLC_SERDES_MASTER_BUSY_0__BUSY_MASK_MASK__SI 0xffffffffL -#define RLC_SERDES_MASTER_BUSY_1__BUSY_MASK_MASK__SI 0xffffffffL -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK__CI__VI 0x00010000L -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK__CI 0xff800000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK__CI__VI 0x0000ffffL -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK__CI 0x00080000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK__CI 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK__CI 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK__CI 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK__CI 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK__CI 0x00040000L -#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffffL -#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffffL -#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffffL -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK__CI__VI 0x0000000fL -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK__CI 0x0000c000L -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_INDEX_MASK__SI 0x00003000L -#define RLC_SERDES_RD_MASTER_INDEX__MASTER_INDEX_MASK__SI 0x0000003fL -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK__CI 0x00003800L -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK__CI__VI 0x000001c0L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK__CI__VI 0x00000200L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK__CI__VI 0x00000400L -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK__CI__VI 0x00000030L -#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK__CI 0xffff0000L -#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK__SI 0xffffc000L -#define RLC_SERDES_RD_MASTER_INDEX__TTOP_INDEX_MASK__SI 0x00000fc0L -#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK__CI__VI 0x000000ffL -#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK__CI 0x00100000L -#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK__CI 0x00200000L -#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK__CI 0x00020000L -#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK__CI 0x00010000L -#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK__CI 0x00080000L -#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK__CI 0x00040000L -#define RLC_SERDES_WR_CTRL__CTRL_MASK__SI 0xffffffffL -#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK__CI 0x00400000L -#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK__CI 0x00800000L -#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK__CI__VI 0x00000400L -#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK__CI__VI 0x00000800L -#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK__CI__VI 0x00000100L -#define RLC_SERDES_WR_CTRL__POWER_UP_MASK__CI__VI 0x00000200L -#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK__CI__VI 0x00002000L -#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK__CI__VI 0xf0000000L -#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK__CI 0x0000c000L -#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK__CI 0x0f000000L -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK__CI__VI 0x00001000L -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK__CI__VI 0xffffffffL -#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffffL -#define RLC_SERDES_WR_MASTER_MASK_0__MASTER_MASK_MASK__SI 0xffffffffL -#define RLC_SERDES_WR_MASTER_MASK_1__MASTER_MASK_MASK__SI 0xffffffffL -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK__CI__VI 0x00010000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK__CI 0xff800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK__CI__VI 0x0000ffffL -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK__CI 0x00080000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK__CI 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK__CI 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK__CI 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK__CI 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK__CI 0x00040000L -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffeL -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L -#define RLC_SMU_PG_CTRL__SPARE_MASK__SI__CI 0xfffffffeL -#define RLC_SMU_PG_CTRL__START_PG_MASK__SI__CI 0x00000001L -#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK__SI__CI 0xfffffffeL -#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK__SI__CI 0x00000001L -#define RLC_SOFT_RESET_GPU__RESERVED_MASK__SI__CI 0xfffffffeL -#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK__SI__CI 0x00000001L -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK__CI__VI 0x00007f00L -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK__CI__VI 0x00008000L -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK__CI__VI 0xffff0000L -#define RLC_SPM_DEBUG_SELECT__SELECT_MASK__CI__VI 0x000000ffL -#define RLC_SPM_DEBUG__DATA_MASK__CI__VI 0xffffffffL -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK__CI__VI 0xffffffffL -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK__CI__VI 0xffffffffL -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_INT_CNTL__RESERVED_MASK__CI__VI 0xfffffffeL -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK__CI__VI 0x00000001L -#define RLC_SPM_INT_STATUS__RESERVED_MASK__CI__VI 0xfffffffeL -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK__CI__VI 0x00000001L -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK__CI__VI 0x00003000L -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK__CI__VI 0xffff0000L -#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK__CI__VI 0x00000fffL -#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK__CI__VI 0x0000c000L -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK__CI__VI 0xffff0000L -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK__CI__VI 0x0000ffffL -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK__CI__VI 0xffffffffL -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK__CI__VI 0xffffffffL -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK__CI__VI 0x0000f800L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK__CI__VI 0x000000ffL -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK__CI__VI 0x00000700L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK__CI__VI 0x80000000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK__CI__VI 0x001f0000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK__CI__VI 0x03e00000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK__CI__VI 0x7c000000L -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK__CI__VI 0xffffffffL -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK__CI__VI 0xffffffffL -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK__CI__VI 0xffffffffL -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK__CI__VI 0xffffffffL -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI 0x000000ffL -#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI 0xffffff00L -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK__CI__VI 0x000000ffL -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK__CI__VI 0xffffff00L -#define RLC_SPM_VMID__RESERVED_MASK__CI__VI 0xfffffff0L -#define RLC_SPM_VMID__RLC_SPM_VMID_MASK__CI__VI 0x0000000fL -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK__CI__VI 0xffffffffL -#define RLC_STAT__GFX_CLOCK_STATUS_MASK__SI 0x00000004L -#define RLC_STAT__GFX_LS_STATUS_MASK__SI 0x00000008L -#define RLC_STAT__GFX_POWER_STATUS_MASK__SI 0x00000002L -#define RLC_STAT__RESERVED_MASK__CI 0xfffffff8L -#define RLC_STAT__RESERVED_MASK__SI__VI 0xfffffff0L -#define RLC_STAT__RLC_BUSY_MASK 0x00000001L -#define RLC_STAT__RLC_GPM_BUSY_MASK__CI__VI 0x00000002L -#define RLC_STAT__RLC_SPM_BUSY_MASK__CI__VI 0x00000004L -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000ffL -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000ff00L -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00ff0000L -#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000L -#define RLC_THREAD_ENABLE__RESERVED_MASK__SI 0xfffffff0L -#define RLC_THREAD_ENABLE__THREAD0_ENABLE_MASK__SI 0x00000001L -#define RLC_THREAD_ENABLE__THREAD1_ENABLE_MASK__SI 0x00000002L -#define RLC_THREAD_ENABLE__THREAD2_ENABLE_MASK__SI 0x00000004L -#define RLC_THREAD_ENABLE__THREAD3_ENABLE_MASK__SI 0x00000008L -#define RLC_THREAD_PRIORITY__THREAD0_PRIORITY_MASK__SI 0x000000ffL -#define RLC_THREAD_PRIORITY__THREAD1_PRIORITY_MASK__SI 0x0000ff00L -#define RLC_THREAD_PRIORITY__THREAD2_PRIORITY_MASK__SI 0x00ff0000L -#define RLC_THREAD_PRIORITY__THREAD3_PRIORITY_MASK__SI 0xff000000L -#define RLC_TTOP_DELAY__MEM_SLEEP_DELAY_MASK__SI 0xff000000L -#define RLC_TTOP_DELAY__POWER_DOWN_DELAY_MASK__SI 0x0000ff00L -#define RLC_TTOP_DELAY__POWER_UP_DELAY_MASK__SI 0x000000ffL -#define RLC_TTOP_DELAY__TILE_TOP_PRO_DELAY_MASK__SI 0x00ff0000L -#define RLC_UCODE_ADDR__RESERVED_MASK__SI 0xfffff000L -#define RLC_UCODE_ADDR__UCODE_ADDR_MASK__SI 0x00000fffL -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffffL -#define RLC_UCODE_DATA__UCODE_DATA_MASK__SI 0xffffffffL -#define RLC_VMID_THREAD1__RESERVED_MASK__SI 0xfffffff0L -#define RLC_VMID_THREAD1__RLC_VMID_MASK__SI 0x0000000fL -#define RLC_VMID_THREAD2__RESERVED_MASK__SI 0xfffffff0L -#define RLC_VMID_THREAD2__RLC_VMID_MASK__SI 0x0000000fL -#define RLC_VMID_THREAD3__RESERVED_MASK__SI 0xfffffff0L -#define RLC_VMID_THREAD3__RLC_VMID_MASK__SI 0x0000000fL -#define RLC_VMID__RESERVED_MASK__SI 0xfffffff0L -#define RLC_VMID__RLC_VMID_MASK__SI 0x0000000fL -#define ROLLING_WINDOW_CAC_AGGR_LOWER__AGGREGATE_31_0_MASK__SI__CI 0xffffffffL -#define ROLLING_WINDOW_CAC_AGGR_UPPER__AGGREGATE_43_32_MASK__SI 0x00000fffL -#define ROLLING_WINDOW_CAC_AGGR_UPPER__AGGREGATE_47_32_MASK__CI 0x0000ffffL -#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffffL -#define ROM_CC_BIF_PINSTRAP__BIF_BIOS_ROM_EN_MASK__CI__VI 0x00000008L -#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK__CI__VI 0x00000004L -#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_EN_A_MASK__CI__VI 0x00000002L -#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_PIN_MASK__CI__VI 0x000000e0L -#define ROM_CC_BIF_PINSTRAP__BIF_SMBUS_DIS_MASK__CI__VI 0x00000010L -#define ROM_CC_BIF_PINSTRAP__BIF_TX_CFG_DRV_FULL_SWING_MASK__CI__VI 0x00000800L -#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_PIN_MASK__CI__VI 0x00000200L -#define ROM_CC_STRAP_PIN_REG0__BPHYC_STRAP_TX_DEEMPH_EN_MASK__CI__VI 0x00000002L -#define ROM_CC_STRAP_PIN_REG0__BPHYC_STRAP_TX_FULL_SWING_MASK__CI__VI 0x00000004L -#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000004L -#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0x00ff0000L -#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0x0000ff00L -#define ROM_CNTL__SCK_OVERWRITE_MASK 0x00000002L -#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000L -#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0f000000L -#define ROM_DATA__ROM_DATA_MASK 0xffffffffL -#define ROM_INDEX__ROM_INDEX_MASK 0x00ffffffL -#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define ROM_START__ROM_START_MASK 0x00ffffffL -#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L -#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L -#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000ffffL -#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L -#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00L -#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000ffL -#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffffL -#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L -#define S0_S1_VID_DC_SMIO_CNTL__S0_SCL_DATA_MASK 0x00010000L -#define S0_S1_VID_DC_SMIO_CNTL__S0_SDA_DATA_MASK 0x00000001L -#define S0_S1_VID_DC_SMIO_CNTL__S1_SCL_DATA_MASK 0x00020000L -#define S0_S1_VID_DC_SMIO_CNTL__S1_SDA_DATA_MASK 0x00000002L -#define S0_S1_VID_DC_SMIO_CNTL__SCL_EN_MASK 0x01000000L -#define S0_S1_VID_DC_SMIO_CNTL__SDA_EN_MASK 0x00000100L -#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xffffffffL -#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xffffffffL -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DCCIF_DC_BUSY_MASK__SI 0x00000040L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DCP_CURSOR_BUSY_MASK__SI 0x00000010L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DCP_ICON_BUSY_MASK__SI 0x00000020L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_G_DCP_CLOCK_ON_MASK__SI 0x00080000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_G_SCL12_CLOCK_ON_MASK__SI 0x00200000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_G_VGA_CLOCK_ON_MASK__SI 0x00008000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_M_CLOCK_ON_MASK__SI 0x00000100L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_CLOCK_ON_MASK__SI 0x00000400L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_RBBMIF_BUSY_MASK__SI 0x00000004L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_RBBMIF_CLOCK_ON_MASK__SI 0x00000008L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_VGA_CLOCK_ON_MASK__SI 0x00010000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_DISP_CLK_G_DCP_BUSY_MASK__SI 0x00020000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_DISP_CLK_G_VGA_BUSY_MASK__SI 0x00002000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_DISP_CLK_R_VGA_BUSY_MASK__SI 0x00001000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_MEMCLK_BUSY_MASK__SI 0x00000080L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_REGCLK_DISP_BUSY_MASK__SI 0x00000200L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_PM_DISABLE_MASK__SI 0x00000001L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RBBMIF_VGAREG_BUSY_MASK__SI 0x00000800L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RBBM_REGCLK_ACTIVE_MASK__SI 0x00000002L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RUN_CLK_DEBUG_DCP_DISP_CLK_MASK__SI 0x00040000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RUN_CLK_DEBUG_SCL_DISP_CLK_MASK__SI 0x00100000L -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RUN_CLK_DEBUG_VGA_DISP_CLK_MASK__SI 0x00004000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_DCCIF_SOFT_RESET_MASK__SI 0x00002000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_DCP_PIXPIPE_SOFT_RESET_MASK__SI 0x00020000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_DCP_REQ_SOFT_RESET_MASK__SI 0x00008000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_G_DCP_RST_MASK__SI 0x00040000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_G_VGA_RST_MASK__SI 0x00000010L -#define SCG_DEBUG_02__IDA1_DISP_CLK_M_DCCIF_RST_MASK__SI 0x00004000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_P_DCP_RST_MASK__SI 0x00010000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_P_DC_RST_MASK__SI 0x00000800L -#define SCG_DEBUG_02__IDA1_DISP_CLK_P_VGA_RST_MASK__SI 0x00000004L -#define SCG_DEBUG_02__IDA1_DISP_CLK_R_RBBMIF_RST_MASK__SI 0x00000400L -#define SCG_DEBUG_02__IDA1_DISP_CLK_R_RST_MASK__SI 0x00001000L -#define SCG_DEBUG_02__IDA1_DISP_CLK_R_VGA_RST_MASK__SI 0x00000008L -#define SCG_DEBUG_02__IDA1_DISP_CLK_VGA_SOFT_RESET_MASK__SI 0x00000002L -#define SCG_DEBUG_02__IDA1_RBBM_DISP_SOFT_RESET_MASK__SI 0x00000200L -#define SCG_DEBUG_02__IDA1_RBBM_VGA_SOFT_RESET_MASK__SI 0x00000001L -#define SCG_DEBUG_03__IDA2_ONESHOT_CLOCKING_MODE_MASK__SI 0x03000000L -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_ONE_SHOT_STOP_MASK__SI 0x00000004L -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_RUN_CLK_MASK__SI 0x00000002L -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_RUN_CLOCK_COUNT_MASK__SI 0x00000ff0L -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_TRIGGER_EVENT_OCCURRED_MASK__SI 0x00000008L -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_WTRIG_PRE_SCG_ONE_SHOT_RUN_CLK_MASK__SI 0x08000000L -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_WTRIG_RUN_CLK_CURRENT_CLK_MASK__SI 0x00000001L -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_ONE_SHOT_STOP_MASK__SI 0x00004000L -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_RUN_CLK_MASK__SI 0x00002000L -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_RUN_CLOCK_COUNT_MASK__SI 0x00ff0000L -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_TRIGGER_EVENT_OCCURRED_MASK__SI 0x00008000L -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_WTRIG_PRE_DCCG_ONE_SHOT_RUN_CLK_MASK__SI 0x10000000L -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_WTRIG_RUN_CLK_CURRENT_CLK_MASK__SI 0x00001000L -#define SCG_DEBUG_03__IDA2_ONESHOT_TRIGGER_EN_MASK__SI 0x04000000L -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_ONE_SHOT_STOP_MASK__SI 0x00000004L -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_RUN_CLK_MASK__SI 0x00000002L -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_RUN_CLOCK_COUNT_MASK__SI 0x00000ff0L -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_TRIGGER_EVENT_OCCURRED_MASK__SI 0x00000008L -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_WTRIG_PRE_SCG_ONE_SHOT_RUN_CLK_MASK__SI 0x00001000L -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_WTRIG_RUN_CLK_CURRENT_CLK_MASK__SI 0x00000001L -#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK__SI 0x00000ff0L -#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK__SI 0x0000000fL -#define SCLK_DCI_SOFT_RESET__SCLK_AZ_SOFT_RESET_MASK__SI 0x00000002L -#define SCLK_DCI_SOFT_RESET__SCLK_DCI_SOFT_RESET_MASK__SI 0x00000001L -#define SCLK_DCO_SOFT_RESET__SCLK_DIGA_SOFT_RESET_MASK__SI 0x00000001L -#define SCLK_DCO_SOFT_RESET__SCLK_DIGB_SOFT_RESET_MASK__SI 0x00000002L -#define SCLK_DCO_SOFT_RESET__SCLK_DIGC_SOFT_RESET_MASK__SI 0x00000004L -#define SCLK_DCO_SOFT_RESET__SCLK_DIGD_SOFT_RESET_MASK__SI 0x00000008L -#define SCLK_DCO_SOFT_RESET__SCLK_DIGE_SOFT_RESET_MASK__SI 0x00000010L -#define SCLK_DCO_SOFT_RESET__SCLK_DIGF_SOFT_RESET_MASK__SI 0x00000020L -#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK__CI__VI 0x00000200L -#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK__CI__VI 0x00000100L -#define SCLK_DEEP_SLEEP_CNTL2__DRM_BUSY_MASK_MASK__CI__VI 0x00000020L -#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK__CI__VI 0x00000002L -#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK__CI__VI 0x00000040L -#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK__CI__VI 0x00000008L -#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK__CI__VI 0xff000000L -#define SCLK_DEEP_SLEEP_CNTL2__LB_UNDERFLOW_PROTECT_EN_MASK__CI__VI 0x00100000L -#define SCLK_DEEP_SLEEP_CNTL2__MC2SRBM_BUSY_MASK_MASK__CI 0x00004000L -#define SCLK_DEEP_SLEEP_CNTL2__MC3SRBM_BUSY_MASK_MASK__CI 0x00008000L -#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK__CI__VI 0x00000010L -#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK__CI__VI 0x00000001L -#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK__CI__VI 0x00000004L -#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK__CI__VI 0x00001000L -#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK__CI__VI 0x00002000L -#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK__CI__VI 0x00000080L -#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK__CI__VI 0x00e00000L -#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK__CI__VI 0x00000400L -#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK__CI__VI 0x00000800L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK__CI__VI 0x00000001L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK__CI__VI 0x00000400L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK__CI__VI 0x00000800L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK__CI__VI 0x00001000L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK__CI__VI 0x00002000L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK__CI__VI 0x00004000L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK__CI__VI 0x00008000L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK__CI__VI 0x00000002L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK__CI__VI 0x00000004L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK__CI__VI 0x00000008L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK__CI__VI 0x00000010L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK__CI__VI 0x00000020L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK__CI__VI 0x00000040L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK__CI__VI 0x00000080L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK__CI__VI 0x00000100L -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK__CI__VI 0x00000200L -#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK__CI__VI 0x00040000L -#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK__CI__VI 0x40000000L -#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK__CI__VI 0x00080000L -#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK__CI__VI 0x08000000L -#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK__CI__VI 0x00000007L -#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK__CI__VI 0x80000000L -#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK__CI__VI 0x04000000L -#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK__CI__VI 0x0000fff0L -#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK__CI__VI 0x10000000L -#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK__CI__VI 0x00200000L -#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK__CI__VI 0x00400000L -#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK__CI__VI 0x00800000L -#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK__CI__VI 0x00000008L -#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK__CI__VI 0x00010000L -#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK__CI__VI 0x00020000L -#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK__CI__VI 0x02000000L -#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK__CI__VI 0x01000000L -#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK__CI__VI 0x00100000L -#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK__CI__VI 0x20000000L -#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK__CI__VI 0x00000007L -#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK__CI__VI 0x00000038L -#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK__CI__VI 0x000e0000L -#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK__CI__VI 0x00010000L -#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK__CI__VI 0x00700000L -#define SCLK_MIN_DIV__FRACV_MASK__CI__VI 0x00000fffL -#define SCLK_MIN_DIV__INTV_MASK__CI__VI 0x0007f000L -#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK__CI__VI 0x00008000L -#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK__CI__VI 0x00400000L -#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK__CI__VI 0x00800000L -#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK__CI__VI 0x00200000L -#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x00000080L -#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x00004000L -#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK__CI__VI 0x00000004L -#define SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK__SI 0x00000020L -#define SCLK_PWRMGT_CNTL__FIR_RESET_MASK__SI 0x00000010L -#define SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK__SI 0x00000040L -#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000L -#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000L -#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x00000400L -#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x00000100L -#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x00000800L -#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x00001000L -#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x00002000L -#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x00000200L -#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK__CI__VI 0x40000000L -#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK__CI__VI 0x80000000L -#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x001f0000L -#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK__CI__VI 0x00000040L -#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK__CI__VI 0x01000000L -#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK__CI__VI 0x00000010L -#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK__CI__VI 0x00000020L -#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x00000002L -#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x00000001L -#define SCLK_PWRMGT_CNTL__SPARE_MASK__SI 0x0000000cL -#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK__CI__VI 0x02000000L -#define SCLK_STARTUP_DID__SCLK_STARTUP_DID_MASK__CI__VI 0x0000007fL -#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK__SI 0x00000001L -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_HORZ_CALC_AUTO_COEF_EN_MASK__SI 0x01000000L -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_HORZ_CALC_AUTO_RATIO_EN_MASK__SI 0x00010000L -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_VERT_CALC_AUTO_COEF_EN_MASK__SI 0x00000100L -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_VERT_CALC_AUTO_RATIO_EN_MASK__SI 0x00000001L -#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK__SI 0x00000003L -#define SCL_COEFRAM__ID09_SCL_HOST_CR_FILTER_OFFSET_MASK__SI 0x000007e0L -#define SCL_COEFRAM__ID09_SCL_HOST_CR_FILTER_TYPE_MASK__SI 0x00000018L -#define SCL_COEFRAM__ID09_SCL_HOST_CR_REQUEST_MASK__SI 0x00000001L -#define SCL_COEFRAM__ID09_SCL_HOST_CR_REQUEST_TYPE_MASK__SI 0x00000006L -#define SCL_COEFRAM__ID09_SCL_SCL_CR_FILTER_OFFSET_0_MASK__SI 0x007e0000L -#define SCL_COEFRAM__ID09_SCL_SCL_CR_FILTER_OFFSET_1_MASK__SI 0xfc000000L -#define SCL_COEFRAM__ID09_SCL_SCL_CR_FILTER_TYPE_0_MASK__SI 0x00018000L -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_0_MASK__SI 0x00001000L -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_1_MASK__SI 0x00800000L -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_TYPE_0_MASK__SI 0x00006000L -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_TYPE_1_MASK__SI 0x03000000L -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK__SI 0x00000100L -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK__SI 0x00000001L -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK__SI 0x00010000L -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK__SI 0x00001000L -#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK__SI 0x00030000L -#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK__SI 0x00000f00L -#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK__SI 0x0000000fL -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK__SI 0x00008000L -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK__SI 0x00003fffL -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK__SI 0x80000000L -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK__SI 0x3fff0000L -#define SCL_CONTROL1__ID00_SCL_ADVANCE_FILTER_POS_MASK__SI 0x00800000L -#define SCL_CONTROL1__ID00_SCL_BFILT_BFKP_STATE_MASK__SI 0x00003000L -#define SCL_CONTROL1__ID00_SCL_BFILT_POS_STATE_MASK__SI 0x0001c000L -#define SCL_CONTROL1__ID00_SCL_CLOCK_V_ACTIVE_MASK__SI 0x10000000L -#define SCL_CONTROL1__ID00_SCL_COEFRAM_BUSY_MASK__SI 0x40000000L -#define SCL_CONTROL1__ID00_SCL_H_FILT_POS_STATE_MASK__SI 0x00000c00L -#define SCL_CONTROL1__ID00_SCL_H_READ_PTR_INIT_STATE_MASK__SI 0x00060000L -#define SCL_CONTROL1__ID00_SCL_H_SCALE_ACTIVE_MASK__SI 0x00100000L -#define SCL_CONTROL1__ID00_SCL_H_SOURCE_ACTIVE_MASK__SI 0x00080000L -#define SCL_CONTROL1__ID00_SCL_LB_EOL_MASK__SI 0x00400000L -#define SCL_CONTROL1__ID00_SCL_LB_SOF_MASK__SI 0x00200000L -#define SCL_CONTROL1__ID00_SCL_LC_STATE_MASK__SI 0x000000ffL -#define SCL_CONTROL1__ID00_SCL_SCALE_ACTIVE_MASK__SI 0x20000000L -#define SCL_CONTROL1__ID00_SCL_SCLK_G_SCL_ON_MASK__SI 0x80000000L -#define SCL_CONTROL1__ID00_SCL_VCG_REQUEST_DONE_MASK__SI 0x08000000L -#define SCL_CONTROL1__ID00_SCL_VCOEFGEN_STATE_MASK__SI 0x07000000L -#define SCL_CONTROL1__ID00_SCL_V_FILT_POS_STATE_MASK__SI 0x00000300L -#define SCL_CONTROL2__ID01_SCL_END_LINE_MASK__SI 0x00200000L -#define SCL_CONTROL2__ID01_SCL_LB_EOL_MASK__SI 0x00020000L -#define SCL_CONTROL2__ID01_SCL_LB_SOF_MASK__SI 0x00010000L -#define SCL_CONTROL2__ID01_SCL_RBBMIF_READY_MASK__SI 0x00008000L -#define SCL_CONTROL2__ID01_SCL_READY_STATE_MASK__SI 0x00007000L -#define SCL_CONTROL2__ID01_SCL_START_LINE_MASK__SI 0x00100000L -#define SCL_CONTROL2__ID01_SCL_V_UPDATE_MASK__SI 0x00000001L -#define SCL_CONTROL__SCL_SWAP_RED_BLUE_MASK__SI 0x00010000L -#define SCL_CRC_CURRENT__SCL_CRC_CURRENT_MASK__SI 0xffffffffL -#define SCL_CRC_ENABLE__SCL_CRC_ENABLE_MASK__SI 0x00000001L -#define SCL_CRC_LAST__SCL_CRC_LAST_MASK__SI 0xffffffffL -#define SCL_CRC_MASK__SCL_CRC_MASK_MASK__SI 0xffffffffL -#define SCL_CRC_SOURCE_SEL__SCL_CRC_SOURCE_SEL_MASK__SI 0x00000003L -#define SCL_CRTC_INTERFACE__ID03_CRTC_SCL_READ_REQUEST_MASK__SI 0x00000001L -#define SCL_CRTC_INTERFACE__ID03_SCL_CRTC_PIX_B_CB_MASK__SI 0x7fe00000L -#define SCL_CRTC_INTERFACE__ID03_SCL_CRTC_PIX_G_Y_MASK__SI 0x000007feL -#define SCL_CRTC_INTERFACE__ID03_SCL_CRTC_PIX_R_CR_MASK__SI 0x001ff800L -#define SCL_CRTC_INTERFACE__ID03_SCL_LB_EOL_MASK__SI 0x80000000L -#define SCL_DEBUG_ID__SCL_DEBUG_ID_MASK__SI 0xffffffffL -#define SCL_DEBUG__SCL_DEBUG_MASK__SI 0xffffffffL -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_CONT_EN_MASK__SI 0x00000100L -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_DE_ONLY_MASK__SI 0x00010000L -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_EN_MASK__SI 0x00000010L -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_LINE_EN_MASK__SI 0x00001000L -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_EN_MASK__SI 0x00000001L -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_LINE_WIDTH_EXCEEDED_ACK_MASK__SI 0x01000000L -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_LINE_WIDTH_EXCEEDED_MASK__SI 0x00100000L -#define SCL_DTMTEST_CRC_BLUE__SCL_DTMTEST_CRC_BLUE_MASK_MASK__SI 0x0000ffffL -#define SCL_DTMTEST_CRC_BLUE__SCL_DTMTEST_CRC_SIG_BLUE_MASK__SI 0xffff0000L -#define SCL_DTMTEST_CRC_GREEN__SCL_DTMTEST_CRC_GREEN_MASK_MASK__SI 0x0000ffffL -#define SCL_DTMTEST_CRC_GREEN__SCL_DTMTEST_CRC_SIG_GREEN_MASK__SI 0xffff0000L -#define SCL_DTMTEST_CRC_RED__SCL_DTMTEST_CRC_RED_MASK_MASK__SI 0x0000ffffL -#define SCL_DTMTEST_CRC_RED__SCL_DTMTEST_CRC_SIG_RED_MASK__SI 0xffff0000L -#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK__SI 0x00000010L -#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK__SI 0x00000007L -#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK__SI 0x00001000L -#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK__SI 0x00000700L -#define SCL_HFILT_COEF__ID08_SCL_ADVANCE_FILTER_POS_MASK__SI 0x00200000L -#define SCL_HFILT_COEF__ID08_SCL_HCG_HF_COEF_RGB_Y_0_MASK__SI 0x000001ffL -#define SCL_HFILT_COEF__ID08_SCL_HCG_HF_COEF_RGB_Y_1_MASK__SI 0x001ff000L -#define SCL_HFILT_COEF__ID08_SCL_H_SCALE_ACTIVE_MASK__SI 0x00400000L -#define SCL_HFILT_COEF__ID08_SCL_LB_EOL_MASK__SI 0x00800000L -#define SCL_HFILT_COEF__ID08_SCL_SOURCE_X_COUNT_Y_LSB7_MASK__SI 0x7f000000L -#define SCL_HFILT_IO__ID07_SCL_ADVANCE_FILTER_POS_MASK__SI 0x10000000L -#define SCL_HFILT_IO__ID07_SCL_HF_RF_G_Y_MASK__SI 0x00000ffcL -#define SCL_HFILT_IO__ID07_SCL_HF_RF_READY_MASK__SI 0x00000001L -#define SCL_HFILT_IO__ID07_SCL_H_PIX_VALID_MASK__SI 0x01000000L -#define SCL_HFILT_IO__ID07_SCL_H_SCALE_ACTIVE_MASK__SI 0x20000000L -#define SCL_HFILT_IO__ID07_SCL_H_SOURCE_ACTIVE_MASK__SI 0x02000000L -#define SCL_HFILT_IO__ID07_SCL_LB_EOL_MASK__SI 0x00800000L -#define SCL_HFILT_IO__ID07_SCL_NUM_BLACK_PIX_C_MASK__SI 0x001e0000L -#define SCL_HFILT_IO__ID07_SCL_NUM_BLACK_PIX_Y_MASK__SI 0x0001f000L -#define SCL_HFILT_IO__ID07_SCL_RF_HF_SEND_MASK__SI 0x00000002L -#define SCL_HFILT_IO__ID07_SCL_SCLK_G_SCL_ON_MASK__SI 0x80000000L -#define SCL_HFILT_IO__ID07_SCL_SOURCE_LINE_ENDED_MASK__SI 0x04000000L -#define SCL_HIGH_PASS_FILTER_CONTROL__SCL_HP_SCALE_FACTOR_FRAC_MASK__SI 0x0000f800L -#define SCL_HIGH_PASS_FILTER_CONTROL__SCL_HP_SCALE_FACTOR_INT_MASK__SI 0x00030000L -#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_ALPHA_COEF_EN_MASK__SI 0x00000100L -#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_ALPHA_COEF_MODE_MASK__SI 0x00030000L -#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK__SI 0x00000001L -#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR_MASK__SI 0x0000ffffL -#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR_MASK__SI 0x00070000L -#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y_MASK__SI 0x0000ffffL -#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y_MASK__SI 0x000f0000L -#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK__SI 0x03ffffffL -#define SCL_H_COUNTERS__ID0B_SCL_HACCUM_C_MASK__SI 0x00fff000L -#define SCL_H_COUNTERS__ID0B_SCL_HACCUM_Y_MASK__SI 0x00000fffL -#define SCL_H_COUNTERS__ID0B_SCL_LB_EOL_MASK__SI 0x80000000L -#define SCL_H_COUNTERS__ID0B_SCL_LB_SOF_MASK__SI 0x40000000L -#define SCL_H_COUNTERS__ID0B_SCL_SOURCE_X_COUNT_MSB6_MASK__SI 0x3f000000L -#define SCL_LB_INTERFACE__ID02_LB_SCL_RTR_MASK__SI 0x00000008L -#define SCL_LB_INTERFACE__ID02_LB_SCL_TAPNUM_MASK__SI 0x00007000L -#define SCL_LB_INTERFACE__ID02_SCL_ALU_AUTOCAL_DONE_MASK__SI 0x00040000L -#define SCL_LB_INTERFACE__ID02_SCL_LB_EOL_MASK__SI 0x00000002L -#define SCL_LB_INTERFACE__ID02_SCL_LB_NUMTAP_IGNORE_MASK__SI 0x00000700L -#define SCL_LB_INTERFACE__ID02_SCL_LB_RND_SCR_MASK__SI 0x00038000L -#define SCL_LB_INTERFACE__ID02_SCL_LB_RTS_MASK__SI 0x00000004L -#define SCL_LB_INTERFACE__ID02_SCL_LB_SHIFT_IN_BLACK_MASK__SI 0x00000080L -#define SCL_LB_INTERFACE__ID02_SCL_LB_SOF_MASK__SI 0x00000001L -#define SCL_LB_INTERFACE__ID02_SCL_LB_TAP_SHIFT_MASK__SI 0x00000070L -#define SCL_LOW_PASS_FILTER_CONTROL__SCL_LP_SCALE_FACTOR_FRAC_MASK__SI 0x0000f800L -#define SCL_LOW_PASS_FILTER_CONTROL__SCL_LP_SCALE_FACTOR_INT_MASK__SI 0x00030000L -#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK__SI 0x00000f00L -#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK__SI 0x0000000fL -#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK__SI 0x0fffff80L -#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK__SI 0x00000010L -#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK__SI 0x00000001L -#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK__SI 0x001fffffL -#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK__SI 0x00003fffL -#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK__SI 0x3fff0000L -#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK__SI 0x00000001L -#define SCL_ONE_SHOT_WATERMARK__SCL_ONE_SHOT_WATERMARK_MASK__SI 0x0000000fL -#define SCL_RBBMIF_RDWR_TIMEOUT__DISP_RBBMIF_RD_WR_TIMEOUT_DIS_MASK__SI 0x00000001L -#define SCL_READBBUF_IO__ID04_SCL_H_REPLICATION_FACTOR_MASK__SI 0x000f0000L -#define SCL_READBBUF_IO__ID04_SCL_H_SOURCE_ACTIVE_MASK__SI 0x00100000L -#define SCL_READBBUF_IO__ID04_SCL_LB_EOL_MASK__SI 0x00800000L -#define SCL_READBBUF_IO__ID04_SCL_PIX_ADVANCE_MASK__SI 0x10000000L -#define SCL_READBBUF_IO__ID04_SCL_RB_RF_PIX_G_MASK__SI 0x00000ffcL -#define SCL_READBBUF_IO__ID04_SCL_RB_RF_READY_MASK__SI 0x00000001L -#define SCL_READBBUF_IO__ID04_SCL_RB_VF_READY_MASK__SI 0x00001000L -#define SCL_READBBUF_IO__ID04_SCL_RF_RB_SEND_MASK__SI 0x00000002L -#define SCL_READBBUF_IO__ID04_SCL_VF_RB_SEND_MASK__SI 0x00002000L -#define SCL_READBBUF_IO__ID04_SCL_V_SCALE_ACTIVE_MASK__SI 0x01000000L -#define SCL_SCALER_ENABLE__SCL_SCALE_EN_MASK__SI 0x00000001L -#define SCL_TAP_CONTROL__SCL_HORZ_NUM_OF_TAPS_MASK__SI 0x00000f00L -#define SCL_TAP_CONTROL__SCL_VERT_NUM_OF_TAPS_MASK__SI 0x00000007L -#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_ACK_MASK__SI 0x00000100L -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_FLAG_MASK__SI 0x00000001L -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_INT_STATUS_MASK__SI 0x00010000L -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_MASK_MASK__SI 0x00001000L -#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK__SI 0x00010000L -#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK__SI 0x00000001L -#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK__SI 0x00000100L -#define SCL_VERT_FILTER_CONTROL__SCL_BAND_FILTER_BYPASS_MASK__SI 0x01000000L -#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_ALPHA_COEF_EN_MASK__SI 0x00000100L -#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_ALPHA_COEF_MODE_MASK__SI 0x00030000L -#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK__SI 0x00000001L -#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK__SI 0x0000ffffL -#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK__SI 0x00070000L -#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK__SI 0x0000ffffL -#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK__SI 0x00070000L -#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK__SI 0x03ffffffL -#define SCL_VFILT_COEF__ID06_SCL_LB_EOL_MASK__SI 0x00800000L -#define SCL_VFILT_COEF__ID06_SCL_VCG_REQUEST_DONE_MASK__SI 0x01000000L -#define SCL_VFILT_COEF__ID06_SCL_VCG_VF_COEF_HP_MASK__SI 0x001ff000L -#define SCL_VFILT_COEF__ID06_SCL_VCG_VF_COEF_LP_MASK__SI 0x000001ffL -#define SCL_VFILT_IO__ID05_SCL_HF_VF_SEND_MASK__SI 0x00000002L -#define SCL_VFILT_IO__ID05_SCL_LB_EOL_MASK__SI 0x00800000L -#define SCL_VFILT_IO__ID05_SCL_PIPE_START_TAPNUM_MASK__SI 0x00700000L -#define SCL_VFILT_IO__ID05_SCL_SCLK_G_SCL_ON_MASK__SI 0x80000000L -#define SCL_VFILT_IO__ID05_SCL_VF_HF_PIX_G_Y_MASK__SI 0x00001ffcL -#define SCL_VFILT_IO__ID05_SCL_VF_HF_READY_MASK__SI 0x00000001L -#define SCL_VFILT_IO__ID05_SCL_V_PIX_VALID_MASK__SI 0x00010000L -#define SCL_V_COUNTERS__ID0A_SCL_LB_EOL_MASK__SI 0x00020000L -#define SCL_V_COUNTERS__ID0A_SCL_LB_SOF_MASK__SI 0x00010000L -#define SCL_V_COUNTERS__ID0A_SCL_SOURCE_Y_COUNT_MASK__SI 0xfff80000L -#define SCL_V_COUNTERS__ID0A_SCL_VACCUM_MASK__SI 0x00000fffL -#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK__CI__VI 0xffffffffL -#define SCRATCH_ADDR__SCRATCH_ADDR_MASK__SI 0xffffffffL -#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL -#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL -#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL -#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL -#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL -#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL -#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL -#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL -#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK__CI__VI 0x00030000L -#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK__CI__VI 0x000000ffL -#define SCRATCH_UMSK__SCRATCH_SWAP_MASK__SI 0x00030000L -#define SCRATCH_UMSK__SCRATCH_UMSK_MASK__SI 0x000000ffL -#define SD1_CC_EDS_LEVEL_CNTL__SD1_VBI_CC_EDS_LEVEL_MASK__SI 0x0000007fL -#define SD1_CHROMA_MOD_CNTL__SD1_CHROMA_PRE_MOD_DELAY_EN_MASK__SI 0x08000000L -#define SD1_CHROMA_MOD_CNTL__SD1_COL_SC_SECOND_CORR_EN_MASK__SI 0x04000000L -#define SD1_CHROMA_MOD_CNTL__SD1_FORCE_BLACK_WHITE_MASK__SI 0x20000000L -#define SD1_CHROMA_MOD_CNTL__SD1_FORCE_BURST_ALWAYS_MASK__SI 0x40000000L -#define SD1_CHROMA_MOD_CNTL__SD1_UVFLT_EN_MASK__SI 0x80000000L -#define SD1_CHROMA_MOD_CNTL__SD1_U_BURST_LEVEL_MASK__SI 0x000001ffL -#define SD1_CHROMA_MOD_CNTL__SD1_V_BURST_LEVEL_MASK__SI 0x01ff0000L -#define SD1_CHROMA_OFFSET__SD1_CHROMA_OFFSET_MASK__SI 0x000003ffL -#define SD1_COL_SC_DENOMIN__SD1_COL_SC_DENOMIN_MASK__SI 0x01ffffffL -#define SD1_COL_SC_INC_CORR__SD1_COL_SC_INC_CORR_MASK__SI 0x1fffffffL -#define SD1_COL_SC_INC__SD1_COL_SC_INC_MASK__SI 0x1fffffffL -#define SD1_COL_SC_PHASE_CNTL__SD1_COL_SC_PHASE_INIT_MASK__SI 0x0000ffffL -#define SD1_CRC_CNTL__SD1_CRC_DATAIN_SEL_MASK__SI 0x00000030L -#define SD1_CRC_CNTL__SD1_CRC_EN_MASK__SI 0x00000001L -#define SD1_CRC_CNTL__SD1_PROGRESSIVE_MODE_CRC_MASK__SI 0x00000100L -#define SD1_CRC_CNTL__SD1_RST_SC_ON_FSYNC_4CRC_MASK__SI 0x00000080L -#define SD1_CRTC_HV_START__SD1_CRTC_H_START_MASK__SI 0x00001fffL -#define SD1_CRTC_HV_START__SD1_CRTC_V_START_MASK__SI 0x1fff0000L -#define SD1_CRTC_TV_FRAMESTART_CNTL__SD1_CRTC_TV_FRAMESTART_FREQ_MASK__SI 0x00000003L -#define SD1_FORCE_DAC_DATA__SD1_FORCE_DAC_DATA_MASK__SI 0x000003ffL -#define SD1_LUMA_BLANK_SETUP_LEVELS__SD1_BLANK_LEVEL_MASK__SI 0x000001ffL -#define SD1_LUMA_BLANK_SETUP_LEVELS__SD1_SETUP_LEVEL_MASK__SI 0x01ff0000L -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_COMB_EN_MASK__SI 0x00000001L -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_COMB_LINE_SEL_MASK__SI 0x00000300L -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_DISABLE_FIRST_LAST_MASK__SI 0x00000002L -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_P2_MASK__SI 0x003f0000L -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_P3_MASK__SI 0x7f000000L -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P4_MASK__SI 0x000000ffL -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P5_MASK__SI 0x00000100L -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P6_MASK__SI 0x003f0000L -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P7_MASK__SI 0x0f000000L -#define SD1_LUMA_COMB_FILT_CNTL3__SD1_P10_MASK__SI 0x0000003fL -#define SD1_LUMA_COMB_FILT_CNTL3__SD1_P8_MASK__SI 0x0001ff00L -#define SD1_LUMA_COMB_FILT_CNTL3__SD1_P9_MASK__SI 0x07f00000L -#define SD1_LUMA_COMB_FILT_CNTL4__SD1_FORCE_P9_MASK__SI 0x00000100L -#define SD1_LUMA_COMB_FILT_CNTL4__SD1_P11_MASK__SI 0x0000003fL -#define SD1_LUMA_FILT_CNTL__SD1_COMPY_OUT_BLEND_MASK__SI 0x00000f00L -#define SD1_LUMA_FILT_CNTL__SD1_COMP_PASSTHRU_BLEND_MASK__SI 0x000f0000L -#define SD1_LUMA_FILT_CNTL__SD1_INSIDE_ACTIVE_SLEW_EN_MASK__SI 0x02000000L -#define SD1_LUMA_FILT_CNTL__SD1_LUMA_DITHER_SEL_MASK__SI 0x30000000L -#define SD1_LUMA_FILT_CNTL__SD1_OUTSIDE_ACTIVE_SLEW_EN_MASK__SI 0x01000000L -#define SD1_LUMA_FILT_CNTL__SD1_SVIDY_OUT_BLEND_MASK__SI 0x0000f000L -#define SD1_LUMA_FILT_CNTL__SD1_SVID_PASSTHRU_BLEND_MASK__SI 0x00f00000L -#define SD1_LUMA_FILT_CNTL__SD1_YFLT_EN_MASK__SI 0x00000001L -#define SD1_LUMA_OFFSET_LIMIT__SD1_LUMA_LIMIT_MASK__SI 0x003ff000L -#define SD1_LUMA_OFFSET_LIMIT__SD1_LUMA_OFFSET_MASK__SI 0x000003ffL -#define SD1_LUMA_OFFSET_LIMIT__SD1_YC_OFFSET_LIMIT_BYPASS_MASK__SI 0x01000000L -#define SD1_LUMA_SYNC_TIP_LEVELS__SD1_PBPR_SYNC_TIP_LEVEL_MASK__SI 0x01ff0000L -#define SD1_LUMA_SYNC_TIP_LEVELS__SD1_Y_SYNC_TIP_LEVEL_MASK__SI 0x000001ffL -#define SD1_MAIN_CNTL2__SD1_HDTV_SEL_MASK__SI 0x00000002L -#define SD1_MAIN_CNTL2__SD1_IKOS_CAP_FRAME_PULSE_MASK__SI 0x00000004L -#define SD1_MAIN_CNTL2__SD1_TVOUT_EN_MASK__SI 0x00000001L -#define SD1_MAIN_CNTL2__TVOUT_RBBMIF_RDWR_TIMEOUT_DIS_MASK__SI 0x80000000L -#define SD1_MAIN_CNTL__SD1_ALT_PHASE_EN_MASK__SI 0x00000040L -#define SD1_MAIN_CNTL__SD1_ALT_PHASE_RST_ON_SYNC_MASK__SI 0x04000000L -#define SD1_MAIN_CNTL__SD1_BLANK_ON_RB_SEL_MASK__SI 0x00008000L -#define SD1_MAIN_CNTL__SD1_FIELD_SYNC_CNTL_MASK__SI 0x00000030L -#define SD1_MAIN_CNTL__SD1_FIELD_SYNC_TRIGGER_MASK__SI 0x00000008L -#define SD1_MAIN_CNTL__SD1_INVERT_ALT_LINE_MASK__SI 0x00000080L -#define SD1_MAIN_CNTL__SD1_MISC_DOUBLEB_REGS_CNTL_MASK__SI 0x00000600L -#define SD1_MAIN_CNTL__SD1_MISC_REGS_LOCK_MASK__SI 0x00000100L -#define SD1_MAIN_CNTL__SD1_PATTERN_GEN_EN_MASK__SI 0x00010000L -#define SD1_MAIN_CNTL__SD1_PATTERN_GEN_SEL_MASK__SI 0x000e0000L -#define SD1_MAIN_CNTL__SD1_PIX_DELAY_MASK__SI 0x03f00000L -#define SD1_MAIN_CNTL__SD1_PIX_DELAY_SEL_MASK__SI 0x08000000L -#define SD1_MAIN_CNTL__SD1_RESET_SCPHASE_TRIGGER_MASK__SI 0x00000004L -#define SD1_MAIN_CNTL__SD1_RESYNC_ALWAYS_MASK__SI 0x00000002L -#define SD1_MAIN_CNTL__SD1_RGB_OUTPUT_EN_MASK__SI 0x00004000L -#define SD1_MAIN_CNTL__SD1_TV_ASYNC_RST_MASK__SI 0x00000001L -#define SD1_MAIN_CNTL__SD1_U_1024_DATAIN_EN_MASK__SI 0x40000000L -#define SD1_MAIN_CNTL__SD1_VBI_PASSTHRU_EN_MASK__SI 0x00000800L -#define SD1_MAIN_CNTL__SD1_V_1024_DATAIN_EN_MASK__SI 0x80000000L -#define SD1_MAIN_CNTL__SD1_YPBPR_480I_EN_MASK__SI 0x00001000L -#define SD1_MAIN_CNTL__SD1_YPBPR_480P_EN_MASK__SI 0x00002000L -#define SD1_MAIN_CNTL__SD1_Y_1024_DATAIN_EN_MASK__SI 0x30000000L -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_AMPL_STEP_MASK__SI 0x0000001fL -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_CYC_50HZ_EN_MASK__SI 0x00000200L -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_CYC_TMODE_EN_MASK__SI 0x00000100L -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_PULSATE_EN_MASK__SI 0x00000400L -#define SD1_MV_AGC_CNTL__SD1_MV_OVRB_EN_MASK__SI 0x01000000L -#define SD1_MV_AGC_CNTL__SD1_MV_OVRB_LEVEL_MASK__SI 0x00ff0000L -#define SD1_MV_AGC_MAX_LEVELS__SD1_MV_AGC_AMPL_MAX_MASK__SI 0x000003ffL -#define SD1_MV_AGC_MAX_LEVELS__SD1_MV_PBPR_EN_MASK__SI 0x80000000L -#define SD1_MV_AGC_PAL_A_B_LEVELS__SD1_MV_AGC_AMPL_A_MASK__SI 0x000001ffL -#define SD1_MV_AGC_PAL_A_B_LEVELS__SD1_MV_AGC_AMPL_B_MASK__SI 0x00ff0000L -#define SD1_MV_BLANK_SETUP_LEVELS__SD1_MV_BLANK_LEVEL_MASK__SI 0x000001ffL -#define SD1_MV_BLANK_SETUP_LEVELS__SD1_MV_SETUP_LEVEL_MASK__SI 0x01ff0000L -#define SD1_MV_BP_LEVEL__SD1_MV_BP_LEVEL_MASK__SI 0x000003ffL -#define SD1_MV_N0_CONTROL__SD1_MV_DOUBLEB_REGS_CNTL_MASK__SI 0x00000600L -#define SD1_MV_N0_CONTROL__SD1_MV_N0_CONTROL_MASK__SI 0x0000003fL -#define SD1_MV_N0_CONTROL__SD1_MV_REGS_LOCK_MASK__SI 0x00000100L -#define SD1_MV_N10_PS_AGC__SD1_MV_N10_A_PS_SPACE_MASK__SI 0x000000ffL -#define SD1_MV_N10_PS_AGC__SD1_MV_N10_B_PS_SPACE_MASK__SI 0x0000ff00L -#define SD1_MV_N11_N12_PS_AGC__SD1_MV_N11_PS_AGC_LINE_SEL_MASK__SI 0x00007fffL -#define SD1_MV_N11_N12_PS_AGC__SD1_MV_N12_PS_AGC_LINE_FORMAT_MASK__SI 0x7fff0000L -#define SD1_MV_N13_N14_PS_AGC_H_EN__SD1_MV_N13_A_PS_AGC_H_EN_MASK__SI 0x000000ffL -#define SD1_MV_N13_N14_PS_AGC_H_EN__SD1_MV_N14_B_PS_AGC_H_EN_MASK__SI 0x0000ff00L -#define SD1_MV_N15_BP_TIMING__SD1_MV_H_BP_DUR_MASK__SI 0x0000ff00L -#define SD1_MV_N15_BP_TIMING__SD1_MV_N15_NUM_OF_BP_LINES_MASK__SI 0x000000ffL -#define SD1_MV_N15_BP_TIMING__SD1_MV_V_BP_START_PRE_VSYNC1_MASK__SI 0x00010000L -#define SD1_MV_N15_BP_TIMING__SD1_MV_V_BP_START_PRE_VSYNC2_MASK__SI 0x00020000L -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_CS_BURST_ADVANCE_DUR_MASK__SI 0x0000003fL -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_CS_MODIFY_4FALL_DEL_MASK__SI 0x001f0000L -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_CS_UVFILT_RISE_DEL_MASK__SI 0x00001f00L -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_N16_CS_BURST_ADV_EN_MASK__SI 0x00800000L -#define SD1_MV_N17_TO_N19_CS__SD1_MV_N17_CS_ZONE1_DUR_MASK__SI 0x0000007fL -#define SD1_MV_N17_TO_N19_CS__SD1_MV_N18_CS_ZONE2_DUR_MASK__SI 0x00007f00L -#define SD1_MV_N17_TO_N19_CS__SD1_MV_N19_CS_ZONE3_DUR_MASK__SI 0x00ff0000L -#define SD1_MV_N1_TO_N3_CS__SD1_MV_N1_FIRST_CS_LINE_F1_MASK__SI 0x0000003fL -#define SD1_MV_N1_TO_N3_CS__SD1_MV_N2_FIRST_CS_SPACE_F1_MASK__SI 0x00003f00L -#define SD1_MV_N1_TO_N3_CS__SD1_MV_N3_FIRST_CS_LINE_F2_MASK__SI 0x01ff0000L -#define SD1_MV_N20_TO_N22_CS_RGB__SD1_MV_N20_CS_ZONE_PHASES_MASK__SI 0x00000007L -#define SD1_MV_N20_TO_N22_CS_RGB__SD1_MV_N21_CS_LINE_PHASES_MASK__SI 0x0003ff00L -#define SD1_MV_N20_TO_N22_CS_RGB__SD1_MV_N22_RGB_COPY_PROTECT_MASK__SI 0x00100000L -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N4_FIRST_CS_SPACE_F2_MASK__SI 0x0000003fL -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N5_OTHER_CS_SPACE_MASK__SI 0x00003f00L -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N6_NUM_OF_CS_MASK__SI 0x000f0000L -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N7_NUM_LINES_PER_CS_MASK__SI 0x07000000L -#define SD1_MV_N8_PS_AGC__SD1_MV_H_AGC_DUR_MASK__SI 0x00ff0000L -#define SD1_MV_N8_PS_AGC__SD1_MV_N8_A_PS_DUR_MASK__SI 0x0000007fL -#define SD1_MV_N8_PS_AGC__SD1_MV_N8_B_PS_DUR_MASK__SI 0x00007f00L -#define SD1_MV_N9_PS_AGC__SD1_MV_N9_A_FIRST_PS_START_MASK__SI 0x000001ffL -#define SD1_MV_N9_PS_AGC__SD1_MV_N9_B_FIRST_PS_START_MASK__SI 0x01ff0000L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_H_MV_VBI_INIT_MASK__SI 0x00000004L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_BP_INIT_MASK__SI 0x00000001L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_BURST_INIT_MASK__SI 0x00000008L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_COUNT_INIT_MASK__SI 0x000000f0L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_LINE_COUNT_INIT_MASK__SI 0x00000700L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_START_INIT_MASK__SI 0x007ff000L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_PS_AGC_INIT_MASK__SI 0x01000000L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_PS_AGC_LINE_COUNT_INIT_MASK__SI 0xf0000000L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_PS_AGC_PALX_LO_INIT_MASK__SI 0x02000000L -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_VBI_INIT_MASK__SI 0x00000002L -#define SD1_MV_V_PS_AGC_TIMING__SD1_MV_V_PS_AGC_START1_MASK__SI 0x000007ffL -#define SD1_MV_V_PS_AGC_TIMING__SD1_MV_V_PS_AGC_START2_MASK__SI 0x007ff000L -#define SD1_MV_V_PS_AGC_TIMING__SD1_MV_V_PS_STATE_X_HI_DUR_MASK__SI 0x0f000000L -#define SD1_MV_V_REDUCE_SYNC_ENDS__SD1_MV_VBI_END1_MASK__SI 0x000007ffL -#define SD1_MV_V_REDUCE_SYNC_ENDS__SD1_MV_VBI_END2_MASK__SI 0x03ff8000L -#define SD1_RGB_OR_PBPR_BLANK_LEVEL__SD1_RGB_OR_PBPR_BLANK_LEVEL_MASK__SI 0x000001ffL -#define SD1_SCM_COL_SC_DENOMIN__SD1_SCM_COL_SC_DENOMIN_MASK__SI 0x01ffffffL -#define SD1_SCM_COL_SC_INC_CORR__SD1_SCM_COL_SC_INC_CORR_MASK__SI 0x1fffffffL -#define SD1_SCM_COL_SC_INC__SD1_SCM_COL_SC_INC_MASK__SI 0x1fffffffL -#define SD1_SCM_DB_DR_SCALE_FACTORS__SD1_SCM_DB_SCALE_FACTOR_MASK__SI 0x0000ffffL -#define SD1_SCM_DB_DR_SCALE_FACTORS__SD1_SCM_DR_SCALE_FACTOR_MASK__SI 0xffff0000L -#define SD1_SCM_MAX_DTO_SWING__SD1_SCM_MAX_DTO_SWING_MASK__SI 0x0fffffffL -#define SD1_SCM_MIN_DTO_SWING__SD1_SCM_MIN_DTO_SWING_MASK__SI 0x0fffffffL -#define SD1_SCM_MOD_CNTL__SD1_INVERT_SCM_3LINE_MASK__SI 0x08000000L -#define SD1_SCM_MOD_CNTL__SD1_SCM_2LINE_EN_MASK__SI 0x40000000L -#define SD1_SCM_MOD_CNTL__SD1_SCM_3LINE_INIT_MASK__SI 0x30000000L -#define SD1_SCM_MOD_CNTL__SD1_SCM_BURST_GAIN_MASK__SI 0x00000fffL -#define SD1_SCM_MOD_CNTL__SD1_SCM_DTO_LIMIT_EN_MASK__SI 0x80000000L -#define SD1_SCM_MOD_CNTL__SD1_SCM_ENABLE_MASK__SI 0x01000000L -#define SD1_SCM_MOD_CNTL__SD1_SCM_INVERT_PHASE_EN_MASK__SI 0x04000000L -#define SD1_SCM_MOD_CNTL__SD1_SCM_NOTCH_TUNER_MASK__SI 0x003f0000L -#define SD1_SCM_MOD_CNTL__SD1_SCM_RST_DTO_ON_BLANK_MASK__SI 0x02000000L -#define SD1_SDTV0_DEBUG__SD1_SDTV0_DEBUG_MASK__SI 0xffffffffL -#define SD1_TIMING_H_134BIT__SD1_H_134BIT_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_20BIT__SD1_H_20BIT_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW1__SD1_H_ACTIVE_FILT_END1_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW1__SD1_H_ACTIVE_FILT_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW2__SD1_H_ACTIVE_FILT_END2_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW2__SD1_H_ACTIVE_FILT_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_H_ADV_ACTIVE__SD1_H_ADV_ACTIVE_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_H_ADV_ACTIVE__SD1_H_ADV_ACTIVE_START2_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_ADV_VBI_PASSTHRU__SD1_H_ADV_VBI_PASSTHRU_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_BURST__SD1_H_BURST_DUR_MASK__SI 0x00ff0000L -#define SD1_TIMING_H_BURST__SD1_H_BURST_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_CC_EDS__SD1_H_CC_OR_EDS_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_COUNT_INIT__SD1_H_COUNT_INIT_MASK__SI 0x00000fffL -#define SD1_TIMING_H_COUNT__SD1_H_COUNT_MASK__SI 0x00000fffL -#define SD1_TIMING_H_EQUALIZATION1__SD1_H_EQ_PULSE_END1_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_EQUALIZATION1__SD1_H_EQ_PULSE_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_H_EQUALIZATION2__SD1_H_EQ_PULSE_END2_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_EQUALIZATION2__SD1_H_EQ_PULSE_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_H_HSYNC__SD1_H_HSYNC_END_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_HSYNC__SD1_H_HSYNC_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_RUNIN_FILT_WINDOW__SD1_H_RUNIN_FILT_END_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_RUNIN_FILT_WINDOW__SD1_H_RUNIN_FILT_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_SERATION1__SD1_H_SER_PULSE_END1_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_SERATION1__SD1_H_SER_PULSE_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_H_SERATION2__SD1_H_SER_PULSE_END2_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_SERATION2__SD1_H_SER_PULSE_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_H_SETUP1__SD1_H_SETUP_END1_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_SETUP1__SD1_H_SETUP_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_H_SETUP2__SD1_H_SETUP_END2_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_SETUP2__SD1_H_SETUP_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_H_TOTAL__SD1_H_TOTAL_MASK__SI 0x00000fffL -#define SD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW__SD1_H_VBI_PASSTHRU_FILT_END_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW__SD1_H_VBI_PASSTHRU_FILT_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_VBI_PASSTHRU__SD1_H_VBI_PASSTHRU_END_MASK__SI 0x0fff0000L -#define SD1_TIMING_H_VBI_PASSTHRU__SD1_H_VBI_PASSTHRU_START_MASK__SI 0x00000fffL -#define SD1_TIMING_H_WSS__SD1_H_WSS_START_MASK__SI 0x00000fffL -#define SD1_TIMING_INTERNAL_INIT__SD1_H_BURST_INIT_MASK__SI 0x00000040L -#define SD1_TIMING_INTERNAL_INIT__SD1_H_EQ_PULSE_INIT_MASK__SI 0x00000004L -#define SD1_TIMING_INTERNAL_INIT__SD1_H_HSYNC_INIT_MASK__SI 0x00000001L -#define SD1_TIMING_INTERNAL_INIT__SD1_H_SER_PULSE_INIT_MASK__SI 0x00000008L -#define SD1_TIMING_INTERNAL_INIT__SD1_H_SETUP_INIT_MASK__SI 0x00000100L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_ACTIVE_INIT_MASK__SI 0x00000400L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_BURST_INIT_MASK__SI 0x00000080L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_CC_LINE_INIT_MASK__SI 0x00001000L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_EDS_LINE_INIT_MASK__SI 0x00004000L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_EQ_SER_INIT_MASK__SI 0x00000010L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F1_134BIT_LINE_INIT_MASK__SI 0x00100000L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F1_20BIT_LINE_INIT_MASK__SI 0x00010000L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F2_134BIT_LINE_INIT_MASK__SI 0x00200000L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F2_20BIT_LINE_INIT_MASK__SI 0x00020000L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_HSYNC_INIT_MASK__SI 0x00000002L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_SER_INIT_MASK__SI 0x00000020L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_SETUP_INIT_MASK__SI 0x00000200L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_VBI_PASSTHRU_INIT_MASK__SI 0x00080000L -#define SD1_TIMING_INTERNAL_INIT__SD1_V_WSS_LINE_INIT_MASK__SI 0x00040000L -#define SD1_TIMING_V_134BIT__SD1_V_134BIT1_LINE_MASK__SI 0x000007ffL -#define SD1_TIMING_V_134BIT__SD1_V_134BIT2_LINE_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_20BIT__SD1_V_20BIT1_LINE_MASK__SI 0x000007ffL -#define SD1_TIMING_V_20BIT__SD1_V_20BIT2_LINE_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_ACTIVE1__SD1_V_ACTIVE_END1_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_ACTIVE1__SD1_V_ACTIVE_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_V_ACTIVE2__SD1_V_ACTIVE_END2_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_ACTIVE2__SD1_V_ACTIVE_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_V_BURST1__SD1_ALT_BURST_BLANK_EN_MASK__SI 0x10000000L -#define SD1_TIMING_V_BURST1__SD1_ALT_V_BURST_END1_MASK__SI 0x40000000L -#define SD1_TIMING_V_BURST1__SD1_ALT_V_BURST_START1_MASK__SI 0x20000000L -#define SD1_TIMING_V_BURST1__SD1_V_BURST_END1_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_BURST1__SD1_V_BURST_START1_MASK__SI 0x000007ffL -#define SD1_TIMING_V_BURST2__SD1_ALT_V_BURST_END2_MASK__SI 0x20000000L -#define SD1_TIMING_V_BURST2__SD1_ALT_V_BURST_START2_MASK__SI 0x10000000L -#define SD1_TIMING_V_BURST2__SD1_V_BURST_END2_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_BURST2__SD1_V_BURST_START2_MASK__SI 0x000007ffL -#define SD1_TIMING_V_CC_EDS__SD1_V_CC_LINE_MASK__SI 0x000007ffL -#define SD1_TIMING_V_CC_EDS__SD1_V_EDS_LINE_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_EQUALIZATION1__SD1_V_EQ_PULSE_DUR1_MASK__SI 0x07ff8000L -#define SD1_TIMING_V_EQUALIZATION1__SD1_V_EQ_PULSE_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_V_EQUALIZATION2__SD1_V_EQ_PULSE_DUR2_MASK__SI 0x07ff8000L -#define SD1_TIMING_V_EQUALIZATION2__SD1_V_EQ_PULSE_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_V_F_COUNT_INIT__SD1_F_COUNT_INIT_MASK__SI 0x000f0000L -#define SD1_TIMING_V_F_COUNT_INIT__SD1_V_COUNT_INIT_MASK__SI 0x000007ffL -#define SD1_TIMING_V_F_COUNT__SD1_F_COUNT_MASK__SI 0x000f0000L -#define SD1_TIMING_V_F_COUNT__SD1_V_COUNT_MASK__SI 0x000007ffL -#define SD1_TIMING_V_F_TOTAL__SD1_F_TOTAL_MASK__SI 0x000f0000L -#define SD1_TIMING_V_F_TOTAL__SD1_V_TOTAL_MASK__SI 0x000007ffL -#define SD1_TIMING_V_SERATION1__SD1_V_SER_PULSE_DUR1_MASK__SI 0x07ff8000L -#define SD1_TIMING_V_SERATION1__SD1_V_SER_PULSE_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_V_SERATION2__SD1_V_SER_PULSE_DUR2_MASK__SI 0x07ff8000L -#define SD1_TIMING_V_SERATION2__SD1_V_SER_PULSE_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_V_SETUP1__SD1_V_SETUP_END1_MASK__SI 0x07ff8000L -#define SD1_TIMING_V_SETUP1__SD1_V_SETUP_START1_MASK__SI 0x00000fffL -#define SD1_TIMING_V_SETUP2__SD1_V_SETUP_END2_MASK__SI 0x07ff8000L -#define SD1_TIMING_V_SETUP2__SD1_V_SETUP_START2_MASK__SI 0x00000fffL -#define SD1_TIMING_V_VBI_PASSTHRU1__SD1_V_VBI_PASSTHRU_END1_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_VBI_PASSTHRU1__SD1_V_VBI_PASSTHRU_START1_MASK__SI 0x000007ffL -#define SD1_TIMING_V_VBI_PASSTHRU2__SD1_V_VBI_PASSTHRU_END2_MASK__SI 0x07ff0000L -#define SD1_TIMING_V_VBI_PASSTHRU2__SD1_V_VBI_PASSTHRU_START2_MASK__SI 0x000007ffL -#define SD1_TIMING_V_WSS__SD1_V_WSS_LINE_MASK__SI 0x000007ffL -#define SD1_TV_SOURCE_CONTROL__SD1_TV_DATA_SOURCE_MASK__SI 0x00000001L -#define SD1_UPSAMPLE_MODE__SD1_FOUR_TAP_MODE_MASK__SI 0x00000001L -#define SD1_UPSAMPLE_MODE__SD1_UPSAMP_PICK_NEAR_MASK__SI 0x00000010L -#define SD1_U_AND_V_GAIN_SETTINGS__SD1_U_GAIN_MASK__SI 0x000001ffL -#define SD1_U_AND_V_GAIN_SETTINGS__SD1_V_GAIN_MASK__SI 0x01ff0000L -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_U_BREAK_EN_MASK__SI 0x00001000L -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_U_GAIN_LIMIT_MASK__SI 0x000003ffL -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_V_BREAK_EN_MASK__SI 0x10000000L -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_V_GAIN_LIMIT_MASK__SI 0x03ff0000L -#define SD1_VBI_134BIT_CNTL__SD1_134BIT_FIELD1_EN_MASK__SI 0x40000000L -#define SD1_VBI_134BIT_CNTL__SD1_134BIT_FIELD2_EN_MASK__SI 0x80000000L -#define SD1_VBI_134BIT_CNTL__SD1_134BIT_SAME_DATA_EN_MASK__SI 0x00100000L -#define SD1_VBI_134BIT_CNTL__SD1_VBI_134BIT_END_STATUS_MASK__SI 0x0c000000L -#define SD1_VBI_134BIT_CNTL__SD1_VBI_134BIT_WT_ACK_MASK__SI 0x02000000L -#define SD1_VBI_134BIT_CNTL__SD1_VBI_134BIT_WT_MASK__SI 0x01000000L -#define SD1_VBI_134BIT_DTO_CNTL__SD1_VBI_134BIT_DTO_P_MASK__SI 0x7fffffffL -#define SD1_VBI_134BIT_H_DATA__SD1_VBI_134BIT_H_DATA_MASK__SI 0x0000003fL -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_CGMSA_MASK__SI 0x00003000L -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_CRC_MASK__SI 0x003f0000L -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_DIS_MASK__SI 0x00000001L -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_HEADER_MASK__SI 0x000003f0L -#define SD1_VBI_134BIT_P_DATA0__SD1_VBI_134BIT_P_DATA0_MASK__SI 0xffffffffL -#define SD1_VBI_134BIT_P_DATA1__SD1_VBI_134BIT_P_DATA1_MASK__SI 0xffffffffL -#define SD1_VBI_134BIT_P_DATA2__SD1_VBI_134BIT_P_DATA2_MASK__SI 0xffffffffL -#define SD1_VBI_134BIT_P_DATA3__SD1_VBI_134BIT_P_DATA3_MASK__SI 0xffffffffL -#define SD1_VBI_20BIT_CNTL__SD1_20BIT_FIELD1_EN_MASK__SI 0x40000000L -#define SD1_VBI_20BIT_CNTL__SD1_20BIT_FIELD2_EN_MASK__SI 0x80000000L -#define SD1_VBI_20BIT_CNTL__SD1_20BIT_SAME_DATA_EN_MASK__SI 0x00100000L -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_DATA_MASK__SI 0x000fffffL -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_END_STATUS_MASK__SI 0x0c000000L -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_WT_ACK_MASK__SI 0x02000000L -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_WT_MASK__SI 0x01000000L -#define SD1_VBI_20BIT_DTO_CNTL__SD1_VBI_20BIT_DTO_P_MASK__SI 0x7fffffffL -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_CGMSA_MASK__SI 0x00003000L -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_CRC_MASK__SI 0x003f0000L -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_DIS_MASK__SI 0x00000001L -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_HEADER_MASK__SI 0x000003f0L -#define SD1_VBI_CC_CNTL__SD1_CC_EN_MASK__SI 0x80000000L -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_DATA_MASK__SI 0x0000ffffL -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_END_STATUS_MASK__SI 0x0c000000L -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_WT_ACK_MASK__SI 0x02000000L -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_WT_MASK__SI 0x01000000L -#define SD1_VBI_CC_EDS_DTO_CNTL__SD1_VBI_CC_EDS_DTO_P_MASK__SI 0x7fffffffL -#define SD1_VBI_EDS_CNTL__SD1_EDS_EN_MASK__SI 0x80000000L -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_DATA_MASK__SI 0x0000ffffL -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_END_STATUS_MASK__SI 0x0c000000L -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_WT_ACK_MASK__SI 0x02000000L -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_WT_MASK__SI 0x01000000L -#define SD1_VBI_LEVEL_CNTL__SD1_VBI_134BIT_LEVEL_MASK__SI 0x7f000000L -#define SD1_VBI_LEVEL_CNTL__SD1_VBI_20BIT_LEVEL_MASK__SI 0x00007f00L -#define SD1_VBI_LEVEL_CNTL__SD1_VBI_WSS_LEVEL_MASK__SI 0x007f0000L -#define SD1_VBI_RUNIN_GAIN_CNTL__SD1_VBI_CC_EDS_RUNIN_GAIN_MASK__SI 0x000001ffL -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_DATA_MASK__SI 0x00003fffL -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_END_STATUS_MASK__SI 0x0c000000L -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_WT_ACK_MASK__SI 0x02000000L -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_WT_MASK__SI 0x01000000L -#define SD1_VBI_WSS_CNTL__SD1_WSS_EN_MASK__SI 0x80000000L -#define SD1_VBI_WSS_DTO_CNTL__SD1_VBI_WSS_DTO_P_MASK__SI 0x7fffffffL -#define SD1_VIDEO_PORT_SIG__SD1_CRC_SIG_MASK__SI 0x3fffffffL -#define SD1_VIDOUT_MUX_CNTL__SD1_ENCODER_BYPASS_EN_MASK__SI 0x10000000L -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_OUTPUT_DITHER_SEL_MASK__SI 0xc0000000L -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX0_EN_MASK__SI 0x00000001L -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX0_MASK__SI 0x000000f0L -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX1_EN_MASK__SI 0x00000002L -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX1_MASK__SI 0x00000f00L -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX2_EN_MASK__SI 0x00000004L -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX2_MASK__SI 0x0000f000L -#define SD1_Y_AND_PASSTHRU_GAIN_SETTINGS__SD1_VBI_PASSTHRU_GAIN_MASK__SI 0x01ff0000L -#define SD1_Y_AND_PASSTHRU_GAIN_SETTINGS__SD1_Y_GAIN_MASK__SI 0x000001ffL -#define SD1_Y_BREAK_POINT_SETTING__SD1_Y_BREAK_EN_MASK__SI 0x00010000L -#define SD1_Y_BREAK_POINT_SETTING__SD1_Y_GAIN_LIMIT_MASK__SI 0x000007ffL -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK__CI__VI 0x00800000L -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK__CI__VI 0x00010000L -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK__CI__VI 0x00100000L -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK__CI__VI 0x00000ff0L -#define SDMA0_CLK_CTRL__ON_DELAY_MASK__CI__VI 0x0000000fL -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK__CI__VI 0x80000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK__CI__VI 0x40000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK__CI__VI 0x20000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK__CI__VI 0x10000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK__CI__VI 0x08000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK__CI__VI 0x04000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK__CI__VI 0x02000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK__CI__VI 0x01000000L -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK__CI__VI 0x00040000L -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK__CI__VI 0x10000000L -#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK__CI__VI 0x00000008L -#define SDMA0_CNTL__DRM_CREDIT_MASK__CI__VI 0x000007c0L -#define SDMA0_CNTL__ECC_ENABLE_MASK__CI 0x40000000L -#define SDMA0_CNTL__ECC_INT_ENABLE_MASK__CI 0x80000000L -#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK__CI__VI 0x20000000L -#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK__CI__VI 0x0fc00000L -#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK__CI__VI 0x0001f800L -#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK__CI 0x00000002L -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK__CI__VI 0x00000004L -#define SDMA0_CNTL__TRAP_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_CONFIG__SDMA_RDREQ_URG_MASK__CI 0x00000f00L -#define SDMA0_CONFIG__SDMA_REQ_TRAN_MASK__CI 0x00010000L -#define SDMA0_F32_CNTL__HALT_MASK__CI__VI 0x00000001L -#define SDMA0_F32_CNTL__STEP_MASK__CI__VI 0x00000002L -#define SDMA0_FREEZE__FREEZE_MASK__CI__VI 0x00000010L -#define SDMA0_FREEZE__FROZEN_MASK__CI__VI 0x00000020L -#define SDMA0_FREEZE__PREEMPT_MASK__CI 0x00000001L -#define SDMA0_GFX_APE1_CNTL__BASE_MASK__CI__VI 0x0000ffffL -#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK__CI__VI 0xffff0000L -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK__CI__VI 0x00010000L -#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK__CI__VI 0x0f000000L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK__CI__VI 0x00000080L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK__CI__VI 0x00000100L -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK__CI__VI 0x00000070L -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK__CI__VI 0x00000008L -#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK__CI__VI 0x00000004L -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK__CI__VI 0x00000001L -#define SDMA0_GFX_DRM_COUNTERDATA0__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_COUNTERDATA1__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_COUNTERDATA2__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_COUNTERDATA3__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_COUNTERKEY0__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_COUNTERKEY1__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_COUNTERKEY2__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_COUNTERKEY3__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_IVLOAD0__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_IVLOAD1__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_IVLOAD2__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_IVLOAD3__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_IVLOAD4__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_OFFSET__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_UNROLLKEY__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_WRAPPEDKEY0__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_WRAPPEDKEY1__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_WRAPPEDKEY2__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_DRM_WRAPPEDKEY3__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK__CI__VI 0xffffffe0L -#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK__CI__VI 0x000f0000L -#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_GFX_IB_CNTL__IB_PRIV_MASK__CI__VI 0x80000000L -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK__CI__VI 0x00000100L -#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA0_GFX_IB_RPTR__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA0_GFX_IB_SIZE__SIZE_MASK__CI__VI 0x000fffffL -#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK__CI__VI 0x00ffffffL -#define SDMA0_GFX_RB_BASE__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK__CI__VI 0x00800000L -#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK__CI__VI 0x0000003eL -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK__CI__VI 0x00000200L -#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK__CI__VI 0x0f000000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__CI__VI 0x00001000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__CI__VI 0x00002000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__CI__VI 0x001f0000L -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA0_GFX_RB_RPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__CI__VI 0x0000fff0L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__CI__VI 0xffff0000L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__CI__VI 0x00000002L -#define SDMA0_GFX_RB_WPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK__CI__VI 0x00003fffL -#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK__CI__VI 0x00000001L -#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK__CI__VI 0x00000010L -#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK__CI__VI 0x00000700L -#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK__CI__VI 0x40000000L -#define SDMA0_HASH__BANK_BITS_MASK__CI__VI 0x00000070L -#define SDMA0_HASH__BANK_XOR_COUNT_MASK__CI__VI 0x00007000L -#define SDMA0_HASH__CHANNEL_BITS_MASK__CI__VI 0x00000007L -#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK__CI__VI 0x00000700L -#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK__CI__VI 0xffffffffL -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK__CI__VI 0xffffffffL -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK__CI__VI 0x00000002L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK__CI__VI 0x00000200L -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK__CI__VI 0x00000001L -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK__CI__VI 0x00000100L -#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK__CI__VI 0x000000fcL -#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK__CI__VI 0x0000fc00L -#define SDMA0_PHASE0_QUANTUM__PREFER_MASK__CI__VI 0x40000000L -#define SDMA0_PHASE0_QUANTUM__UNIT_MASK__CI__VI 0x0000000fL -#define SDMA0_PHASE0_QUANTUM__VALUE_MASK__CI__VI 0x00ffff00L -#define SDMA0_PHASE1_QUANTUM__PREFER_MASK__CI__VI 0x40000000L -#define SDMA0_PHASE1_QUANTUM__UNIT_MASK__CI__VI 0x0000000fL -#define SDMA0_PHASE1_QUANTUM__VALUE_MASK__CI__VI 0x00ffff00L -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK__CI__VI 0x00000100L -#define SDMA0_PROGRAM__STREAM_MASK__CI__VI 0xffffffffL -#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC0_APE1_CNTL__BASE_MASK__CI__VI 0x0000ffffL -#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK__CI__VI 0xffff0000L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK__CI__VI 0x00000080L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK__CI__VI 0x00000100L -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK__CI__VI 0x00000070L -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK__CI__VI 0x00000008L -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK__CI__VI 0x00000004L -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK__CI__VI 0x00000001L -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK__CI__VI 0x00000001L -#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK__CI__VI 0x40000000L -#define SDMA0_RLC0_DOORBELL__ENABLE_MASK__CI__VI 0x10000000L -#define SDMA0_RLC0_DOORBELL__OFFSET_MASK__CI__VI 0x001fffffL -#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK__CI__VI 0xffffffe0L -#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK__CI__VI 0x000f0000L -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_RLC0_IB_CNTL__IB_PRIV_MASK__CI__VI 0x80000000L -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK__CI__VI 0x00000100L -#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA0_RLC0_IB_SIZE__SIZE_MASK__CI__VI 0x000fffffL -#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK__CI__VI 0x00ffffffL -#define SDMA0_RLC0_RB_BASE__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK__CI__VI 0x00800000L -#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK__CI__VI 0x0000003eL -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK__CI__VI 0x00000200L -#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK__CI__VI 0x0f000000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__CI__VI 0x00001000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__CI__VI 0x00002000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__CI__VI 0x001f0000L -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__CI__VI 0x0000fff0L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__CI__VI 0xffff0000L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__CI__VI 0x00000002L -#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK__CI__VI 0x00003fffL -#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK__CI__VI 0x00000001L -#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK__CI__VI 0x00000010L -#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK__CI__VI 0x00000700L -#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK__CI__VI 0x40000000L -#define SDMA0_RLC1_APE1_CNTL__BASE_MASK__CI__VI 0x0000ffffL -#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK__CI__VI 0xffff0000L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK__CI__VI 0x00000080L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK__CI__VI 0x00000100L -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK__CI__VI 0x00000070L -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK__CI__VI 0x00000008L -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK__CI__VI 0x00000004L -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK__CI__VI 0x00000001L -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK__CI__VI 0x00000001L -#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK__CI__VI 0x40000000L -#define SDMA0_RLC1_DOORBELL__ENABLE_MASK__CI__VI 0x10000000L -#define SDMA0_RLC1_DOORBELL__OFFSET_MASK__CI__VI 0x001fffffL -#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK__CI__VI 0xffffffe0L -#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK__CI__VI 0x000f0000L -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_RLC1_IB_CNTL__IB_PRIV_MASK__CI__VI 0x80000000L -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK__CI__VI 0x00000100L -#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA0_RLC1_IB_SIZE__SIZE_MASK__CI__VI 0x000fffffL -#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK__CI__VI 0x00ffffffL -#define SDMA0_RLC1_RB_BASE__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK__CI__VI 0x00800000L -#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK__CI__VI 0x0000003eL -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK__CI__VI 0x00000200L -#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK__CI__VI 0x0f000000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__CI__VI 0x00001000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__CI__VI 0x00002000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__CI__VI 0x001f0000L -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK__CI__VI 0x00000001L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__CI__VI 0x0000fff0L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__CI__VI 0xffff0000L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__CI__VI 0x00000002L -#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK__CI__VI 0x00003fffL -#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK__CI__VI 0x00000001L -#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK__CI__VI 0x00000010L -#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK__CI__VI 0x00000700L -#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK__CI__VI 0x40000000L -#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK__CI 0x0000ffffL -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK__CI__VI 0xffffffffL -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK__CI__VI 0x00000400L -#define SDMA0_STATUS1_REG__CE_DRM1_FULL_MASK__CI__VI 0x00001000L -#define SDMA0_STATUS1_REG__CE_DRM1_IDLE_MASK__CI__VI 0x00000100L -#define SDMA0_STATUS1_REG__CE_DRM_FULL_MASK__CI__VI 0x00000800L -#define SDMA0_STATUS1_REG__CE_DRM_IDLE_MASK__CI__VI 0x00000080L -#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK__CI__VI 0x00000040L -#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK__CI__VI 0x00004000L -#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK__CI__VI 0x00002000L -#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK__CI__VI 0x00000020L -#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK__CI__VI 0x00000010L -#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK__CI__VI 0x00020000L -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK__CI__VI 0x00000008L -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK__CI__VI 0x00000004L -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK__CI__VI 0x00000001L -#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK__CI__VI 0x00000002L -#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK__CI__VI 0x00040000L -#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK__CI__VI 0x00000100L -#define SDMA0_STATUS_REG__DRM_IDLE_MASK__CI__VI 0x00800000L -#define SDMA0_STATUS_REG__DRM_MASK_FULL_MASK__CI__VI 0x01000000L -#define SDMA0_STATUS_REG__EX_IDLE_MASK__CI__VI 0x00000400L -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK__CI__VI 0x00000800L -#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK__CI__VI 0x00000080L -#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK__CI__VI 0x00000040L -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK__CI__VI 0x00040000L -#define SDMA0_STATUS_REG__IDLE_MASK__CI__VI 0x00000001L -#define SDMA0_STATUS_REG__INSIDE_IB_MASK__CI__VI 0x00000200L -#define SDMA0_STATUS_REG__INT_IDLE_MASK__CI__VI 0x40000000L -#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK__CI__VI 0x80000000L -#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK__CI__VI 0x00080000L -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK__CI__VI 0x00400000L -#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK__CI__VI 0x00200000L -#define SDMA0_STATUS_REG__MC_WR_AFIFO_FULL_MASK__CI 0x00004000L -#define SDMA0_STATUS_REG__MC_WR_DFIFO_FULL_MASK__CI 0x00008000L -#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK__CI__VI 0x00002000L -#define SDMA0_STATUS_REG__PACKET_READY_MASK__CI__VI 0x00001000L -#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK__CI__VI 0x02000000L -#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK__CI__VI 0x00000020L -#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK__CI__VI 0x00000010L -#define SDMA0_STATUS_REG__RB_EMPTY_MASK__CI__VI 0x00000004L -#define SDMA0_STATUS_REG__RB_FULL_MASK__CI__VI 0x00000008L -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK__CI__VI 0x00020000L -#define SDMA0_STATUS_REG__REG_IDLE_MASK__CI__VI 0x00000002L -#define SDMA0_STATUS_REG__SEM_IDLE_MASK__CI__VI 0x04000000L -#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK__CI__VI 0x08000000L -#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK__CI__VI 0x30000000L -#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK__CI__VI 0x00000070L -#define SDMA0_UCODE_ADDR__VALUE_MASK__CI 0x000007ffL -#define SDMA0_UCODE_DATA__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK__CI__VI 0x00800000L -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK__CI__VI 0x00010000L -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK__CI__VI 0x00100000L -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK__CI__VI 0x00000ff0L -#define SDMA1_CLK_CTRL__ON_DELAY_MASK__CI__VI 0x0000000fL -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK__CI__VI 0x80000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK__CI__VI 0x40000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK__CI__VI 0x20000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK__CI__VI 0x10000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK__CI__VI 0x08000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK__CI__VI 0x04000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK__CI__VI 0x02000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK__CI__VI 0x01000000L -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK__CI__VI 0x00040000L -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK__CI__VI 0x10000000L -#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK__CI__VI 0x00000008L -#define SDMA1_CNTL__DRM_CREDIT_MASK__CI__VI 0x000007c0L -#define SDMA1_CNTL__ECC_ENABLE_MASK__CI 0x40000000L -#define SDMA1_CNTL__ECC_INT_ENABLE_MASK__CI 0x80000000L -#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK__CI__VI 0x20000000L -#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK__CI__VI 0x0fc00000L -#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK__CI__VI 0x0001f800L -#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK__CI 0x00000002L -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK__CI__VI 0x00000004L -#define SDMA1_CNTL__TRAP_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK__CI 0x00000f00L -#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK__CI 0x00010000L -#define SDMA1_F32_CNTL__HALT_MASK__CI__VI 0x00000001L -#define SDMA1_F32_CNTL__STEP_MASK__CI__VI 0x00000002L -#define SDMA1_FREEZE__FREEZE_MASK__CI__VI 0x00000010L -#define SDMA1_FREEZE__FROZEN_MASK__CI__VI 0x00000020L -#define SDMA1_FREEZE__PREEMPT_MASK__CI 0x00000001L -#define SDMA1_GFX_APE1_CNTL__BASE_MASK__CI__VI 0x0000ffffL -#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK__CI__VI 0xffff0000L -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK__CI__VI 0x00010000L -#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK__CI__VI 0x0f000000L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK__CI__VI 0x00000080L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK__CI__VI 0x00000100L -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK__CI__VI 0x00000070L -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK__CI__VI 0x00000008L -#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK__CI__VI 0x00000004L -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK__CI__VI 0x00000001L -#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK__CI__VI 0xffffffe0L -#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK__CI__VI 0x000f0000L -#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_GFX_IB_CNTL__IB_PRIV_MASK__CI__VI 0x80000000L -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK__CI__VI 0x00000100L -#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA1_GFX_IB_RPTR__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA1_GFX_IB_SIZE__SIZE_MASK__CI__VI 0x000fffffL -#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK__CI__VI 0x00ffffffL -#define SDMA1_GFX_RB_BASE__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK__CI__VI 0x00800000L -#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK__CI__VI 0x0000003eL -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK__CI__VI 0x00000200L -#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK__CI__VI 0x0f000000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__CI__VI 0x00001000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__CI__VI 0x00002000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__CI__VI 0x001f0000L -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA1_GFX_RB_RPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__CI__VI 0x0000fff0L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__CI__VI 0xffff0000L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__CI__VI 0x00000002L -#define SDMA1_GFX_RB_WPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK__CI__VI 0x00003fffL -#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK__CI__VI 0x00000001L -#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK__CI__VI 0x00000010L -#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK__CI__VI 0x00000700L -#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK__CI__VI 0x40000000L -#define SDMA1_HASH__BANK_BITS_MASK__CI__VI 0x00000070L -#define SDMA1_HASH__BANK_XOR_COUNT_MASK__CI__VI 0x00007000L -#define SDMA1_HASH__CHANNEL_BITS_MASK__CI__VI 0x00000007L -#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK__CI__VI 0x00000700L -#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK__CI__VI 0xffffffffL -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK__CI__VI 0xffffffffL -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK__CI__VI 0x00000002L -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK__CI__VI 0x00000200L -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK__CI__VI 0x00000001L -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK__CI__VI 0x00000100L -#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK__CI__VI 0x000000fcL -#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK__CI__VI 0x0000fc00L -#define SDMA1_PHASE0_QUANTUM__PREFER_MASK__CI__VI 0x40000000L -#define SDMA1_PHASE0_QUANTUM__UNIT_MASK__CI__VI 0x0000000fL -#define SDMA1_PHASE0_QUANTUM__VALUE_MASK__CI__VI 0x00ffff00L -#define SDMA1_PHASE1_QUANTUM__PREFER_MASK__CI__VI 0x40000000L -#define SDMA1_PHASE1_QUANTUM__UNIT_MASK__CI__VI 0x0000000fL -#define SDMA1_PHASE1_QUANTUM__VALUE_MASK__CI__VI 0x00ffff00L -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK__CI__VI 0x00000100L -#define SDMA1_PROGRAM__STREAM_MASK__CI__VI 0xffffffffL -#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC0_APE1_CNTL__BASE_MASK__CI__VI 0x0000ffffL -#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK__CI__VI 0xffff0000L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK__CI__VI 0x00000080L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK__CI__VI 0x00000100L -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK__CI__VI 0x00000070L -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK__CI__VI 0x00000008L -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK__CI__VI 0x00000004L -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK__CI__VI 0x00000001L -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK__CI__VI 0x00000001L -#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK__CI__VI 0x40000000L -#define SDMA1_RLC0_DOORBELL__ENABLE_MASK__CI__VI 0x10000000L -#define SDMA1_RLC0_DOORBELL__OFFSET_MASK__CI__VI 0x001fffffL -#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK__CI__VI 0xffffffe0L -#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK__CI__VI 0x000f0000L -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_RLC0_IB_CNTL__IB_PRIV_MASK__CI__VI 0x80000000L -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK__CI__VI 0x00000100L -#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA1_RLC0_IB_SIZE__SIZE_MASK__CI__VI 0x000fffffL -#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK__CI__VI 0x00ffffffL -#define SDMA1_RLC0_RB_BASE__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK__CI__VI 0x00800000L -#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK__CI__VI 0x0000003eL -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK__CI__VI 0x00000200L -#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK__CI__VI 0x0f000000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__CI__VI 0x00001000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__CI__VI 0x00002000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__CI__VI 0x001f0000L -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__CI__VI 0x0000fff0L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__CI__VI 0xffff0000L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__CI__VI 0x00000002L -#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK__CI__VI 0x00003fffL -#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK__CI__VI 0x00000001L -#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK__CI__VI 0x00000010L -#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK__CI__VI 0x00000700L -#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK__CI__VI 0x40000000L -#define SDMA1_RLC1_APE1_CNTL__BASE_MASK__CI__VI 0x0000ffffL -#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK__CI__VI 0xffff0000L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK__CI__VI 0x00000080L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK__CI__VI 0x00000100L -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK__CI__VI 0x00000070L -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK__CI__VI 0x00000008L -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK__CI__VI 0x00000004L -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK__CI__VI 0x00000001L -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK__CI__VI 0x00000001L -#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK__CI__VI 0x40000000L -#define SDMA1_RLC1_DOORBELL__ENABLE_MASK__CI__VI 0x10000000L -#define SDMA1_RLC1_DOORBELL__OFFSET_MASK__CI__VI 0x001fffffL -#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK__CI__VI 0xffffffe0L -#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK__CI__VI 0x000f0000L -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_RLC1_IB_CNTL__IB_PRIV_MASK__CI__VI 0x80000000L -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK__CI__VI 0x00000010L -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK__CI__VI 0x00000100L -#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK__CI__VI 0x003ffffcL -#define SDMA1_RLC1_IB_SIZE__SIZE_MASK__CI__VI 0x000fffffL -#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK__CI__VI 0x00ffffffL -#define SDMA1_RLC1_RB_BASE__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK__CI__VI 0x00800000L -#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK__CI__VI 0x0000003eL -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK__CI__VI 0x00000200L -#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK__CI__VI 0x0f000000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK__CI__VI 0x00001000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK__CI__VI 0x00002000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK__CI__VI 0x001f0000L -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK__CI__VI 0xffffffffL -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK__CI__VI 0x00000001L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK__CI__VI 0x0000fff0L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__CI__VI 0xffff0000L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK__CI__VI 0x00000002L -#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK__CI__VI 0xfffffffcL -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK__CI__VI 0x00003fffL -#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK__CI__VI 0x00000001L -#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK__CI__VI 0x00000010L -#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK__CI__VI 0x00000700L -#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK__CI__VI 0x40000000L -#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK__CI 0x0000ffffL -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK__CI__VI 0xffffffffL -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK__CI__VI 0x00000400L -#define SDMA1_STATUS1_REG__CE_DRM1_FULL_MASK__CI__VI 0x00001000L -#define SDMA1_STATUS1_REG__CE_DRM1_IDLE_MASK__CI__VI 0x00000100L -#define SDMA1_STATUS1_REG__CE_DRM_FULL_MASK__CI__VI 0x00000800L -#define SDMA1_STATUS1_REG__CE_DRM_IDLE_MASK__CI__VI 0x00000080L -#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK__CI__VI 0x00000040L -#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK__CI__VI 0x00004000L -#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK__CI__VI 0x00002000L -#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK__CI__VI 0x00000020L -#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK__CI__VI 0x00000010L -#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK__CI__VI 0x00020000L -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK__CI__VI 0x00000008L -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK__CI__VI 0x00000004L -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK__CI__VI 0x00000001L -#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK__CI__VI 0x00000002L -#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK__CI__VI 0x00040000L -#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK__CI__VI 0x00000100L -#define SDMA1_STATUS_REG__DRM_IDLE_MASK__CI__VI 0x00800000L -#define SDMA1_STATUS_REG__DRM_MASK_FULL_MASK__CI__VI 0x01000000L -#define SDMA1_STATUS_REG__EX_IDLE_MASK__CI__VI 0x00000400L -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK__CI__VI 0x00000800L -#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK__CI__VI 0x00000080L -#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK__CI__VI 0x00000040L -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK__CI__VI 0x00040000L -#define SDMA1_STATUS_REG__IDLE_MASK__CI__VI 0x00000001L -#define SDMA1_STATUS_REG__INSIDE_IB_MASK__CI__VI 0x00000200L -#define SDMA1_STATUS_REG__INT_IDLE_MASK__CI__VI 0x40000000L -#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK__CI__VI 0x80000000L -#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK__CI__VI 0x00080000L -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK__CI__VI 0x00400000L -#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK__CI__VI 0x00200000L -#define SDMA1_STATUS_REG__MC_WR_AFIFO_FULL_MASK__CI 0x00004000L -#define SDMA1_STATUS_REG__MC_WR_DFIFO_FULL_MASK__CI 0x00008000L -#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK__CI__VI 0x00002000L -#define SDMA1_STATUS_REG__PACKET_READY_MASK__CI__VI 0x00001000L -#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK__CI__VI 0x02000000L -#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK__CI__VI 0x00000020L -#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK__CI__VI 0x00000010L -#define SDMA1_STATUS_REG__RB_EMPTY_MASK__CI__VI 0x00000004L -#define SDMA1_STATUS_REG__RB_FULL_MASK__CI__VI 0x00000008L -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK__CI__VI 0x00020000L -#define SDMA1_STATUS_REG__REG_IDLE_MASK__CI__VI 0x00000002L -#define SDMA1_STATUS_REG__SEM_IDLE_MASK__CI__VI 0x04000000L -#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK__CI__VI 0x08000000L -#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK__CI__VI 0x30000000L -#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK__CI__VI 0x00000070L -#define SDMA1_UCODE_ADDR__VALUE_MASK__CI 0x000007ffL -#define SDMA1_UCODE_DATA__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK__CI 0x00000f00L -#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK__CI 0x00010000L -#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK__CI__VI 0x000000ffL -#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK__CI__VI 0x00000400L -#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK__CI__VI 0x00000800L -#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK__CI__VI 0x00000100L -#define SDMA_PGFSM_CONFIG__POWER_UP_MASK__CI__VI 0x00000200L -#define SDMA_PGFSM_CONFIG__READ_MASK__CI__VI 0x00002000L -#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK__CI__VI 0xf0000000L -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK__CI__VI 0x08000000L -#define SDMA_PGFSM_CONFIG__WRITE_MASK__CI__VI 0x00001000L -#define SDMA_PGFSM_READ__VALUE_MASK__CI__VI 0x00ffffffL -#define SDMA_PGFSM_WRITE__VALUE_MASK__CI__VI 0xffffffffL -#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK__CI__VI 0x00000002L -#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK__CI__VI 0x00000001L -#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK__CI__VI 0x00000030L -#define SDMA_POWER_GATING__PG_STATE_VALID_MASK__CI__VI 0x00000004L -#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK__CI__VI 0x000fff00L -#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK__CI__VI 0xfff00000L -#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK__CI__VI 0x00000040L -#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK__CI__VI 0x00000080L -#define SDVO_CNTL__SDVO_REARRANGER_EN_MASK__SI 0x00000100L -#define SDVO_CNTL__SDVO_REPL_MODE_SELECT_MASK__SI 0x00000001L -#define SDVO_CNTL__SDVO_SYNC_PHASE_MASK__SI 0x00001000L -#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK__CI__VI 0x00000002L -#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK__CI__VI 0x00000001L -#define SEM_EDC_CONFIG__DIS_EDC_MASK__CI__VI 0x00000002L -#define SEM_EDC_CONFIG__WRITE_DIS_MASK__CI__VI 0x00000001L -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA0_CLIENT0_MASK__SI 0x00007000L -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA0_CLIENT1_MASK__SI 0x00038000L -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA1_CLIENT0_MASK__SI 0x001c0000L -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA1_CLIENT1_MASK__SI 0x00e00000L -#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK__CI__VI 0x001c0000L -#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK__CI__VI 0x00007000L -#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK__CI__VI 0x00038000L -#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK__CI__VI 0x00e00000L -#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ff00L -#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0x000000ffL -#define SEM_MAILBOX__HOSTPORT_MASK 0x0000ff00L -#define SEM_MAILBOX__SIDEPORT_MASK 0x000000ffL -#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK__CI__VI 0x00003f00L -#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L -#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK__CI__VI 0x000000fcL -#define SEM_STATUS__CHECK0_FIFO_FULL_MASK__CI__VI 0x00000020L -#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK__CI__VI 0x00001000L -#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK__CI__VI 0x00002000L -#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK__CI__VI 0x00000004L -#define SEM_STATUS__MC_RDREQ_PENDING_MASK__CI__VI 0x00000040L -#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK__CI__VI 0x00000008L -#define SEM_STATUS__MC_WRREQ_PENDING_MASK__CI__VI 0x00000080L -#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK__CI__VI 0x00000100L -#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK__CI__VI 0x00000200L -#define SEM_STATUS__SEM_IDLE_MASK__CI__VI 0x00000001L -#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK__CI__VI 0x00000002L -#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK__CI__VI 0x00000400L -#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK__CI__VI 0x00000800L -#define SEM_STATUS__WRITE1_FIFO_FULL_MASK__CI__VI 0x00000010L -#define SEQ00__SEQ_RST0B_MASK__SI 0x00000001L -#define SEQ00__SEQ_RST1B_MASK__SI 0x00000002L -#define SEQ01__SEQ_DOT8_MASK__SI 0x00000001L -#define SEQ01__SEQ_MAXBW_MASK__SI 0x00000020L -#define SEQ01__SEQ_PCLKBY2_MASK__SI 0x00000008L -#define SEQ01__SEQ_SHIFT2_MASK__SI 0x00000004L -#define SEQ01__SEQ_SHIFT4_MASK__SI 0x00000010L -#define SEQ02__SEQ_MAP0_EN_MASK__SI 0x00000001L -#define SEQ02__SEQ_MAP1_EN_MASK__SI 0x00000002L -#define SEQ02__SEQ_MAP2_EN_MASK__SI 0x00000004L -#define SEQ02__SEQ_MAP3_EN_MASK__SI 0x00000008L -#define SEQ03__SEQ_FONT_A0_MASK__SI 0x00000020L -#define SEQ03__SEQ_FONT_A1_MASK__SI 0x00000004L -#define SEQ03__SEQ_FONT_A2_MASK__SI 0x00000008L -#define SEQ03__SEQ_FONT_B0_MASK__SI 0x00000010L -#define SEQ03__SEQ_FONT_B1_MASK__SI 0x00000001L -#define SEQ03__SEQ_FONT_B2_MASK__SI 0x00000002L -#define SEQ04__SEQ_256K_MASK__SI 0x00000002L -#define SEQ04__SEQ_CHAIN_MASK__SI 0x00000008L -#define SEQ04__SEQ_ODDEVEN_MASK__SI 0x00000004L -#define SEQ8_DATA__SEQ_DATA_MASK__SI 0x000000ffL -#define SEQ8_IDX__SEQ_IDX_MASK__SI 0x00000007L -#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000L -#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000L -#define SETUP_DEBUG_REG0__event_id_gated_MASK 0x0fc00000L -#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00004000L -#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00200000L -#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00008000L -#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00080000L -#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000L -#define SETUP_DEBUG_REG0__pmode_state_MASK 0x00003f00L -#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x00000003L -#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x00030000L -#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00040000L -#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00100000L -#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000003cL -#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000L -#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000L -#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0x0000ffffL -#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000L -#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0x0000ffffL -#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000L -#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0x0000ffffL -#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x00003fffL -#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00008000L -#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00080000L -#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x00700000L -#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x03000000L -#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000L -#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000L -#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00004000L -#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x00070000L -#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000L -#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00800000L -#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x0fffc000L -#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x00003fffL -#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000L -#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000L -#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000L -#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK__CI__VI 0xffffffffL -#define SH_MEM_APE1_BASE__BASE_MASK__CI__VI 0xffffffffL -#define SH_MEM_APE1_LIMIT__LIMIT_MASK__CI__VI 0xffffffffL -#define SH_MEM_BASES__PRIVATE_BASE_MASK__CI__VI 0x0000ffffL -#define SH_MEM_BASES__SHARED_BASE_MASK__CI__VI 0xffff0000L -#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK__CI 0x0000000cL -#define SH_MEM_CONFIG__APE1_MTYPE_MASK__CI 0x00000380L -#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK__CI 0x00000070L -#define SH_MEM_CONFIG__PRIVATE_ATC_MASK__CI 0x00000002L -#define SH_MEM_CONFIG__PTR32_MASK__CI 0x00000001L -#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK__CI__VI 0x00000006L -#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK__CI__VI 0x00000018L -#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK__CI__VI 0x000000e0L -#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK__CI__VI 0x0000ff00L -#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK__CI__VI 0x00000001L -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK__SI 0x000000ffL -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK__SI 0x0000ff00L -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK__SI 0x00ff0000L -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK__SI 0xff000000L -#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK__SI 0x00000100L -#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK__SI 0x00000001L -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK__SI 0x000000ffL -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK__SI 0x0000ff00L -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK__SI 0x00ff0000L -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK__SI 0xff000000L -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK__SI 0x000000ffL -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK__SI 0x0000ff00L -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK__SI 0x00ff0000L -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK__SI 0xff000000L -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK__SI 0x000000ffL -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK__SI 0x0000ff00L -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK__SI 0x00ff0000L -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK__SI 0xff000000L -#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x00000010L -#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK__CI__VI 0x00000020L -#define SLAVE_HANG_ERROR__CFG_HANG_ERROR_MASK__CI 0x00000040L -#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK__CI__VI 0x00000100L -#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK__CI__VI 0x00000200L -#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x00000002L -#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x00000008L -#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x00000001L -#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x00000004L -#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK__CI__VI 0x00000080L -#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_EN_MASK__SI 0x00000001L -#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0x0000000eL -#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x00100000L -#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x00007c00L -#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x00008000L -#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x0000001fL -#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x000001e0L -#define SLOW_AES0__RESERVED_MASK 0xffffffffL -#define SLOW_AES1__RESERVED_MASK 0xffffffffL -#define SLOW_AES2__RESERVED_MASK 0xffffffffL -#define SLOW_AES3__RESERVED_MASK 0xffffffffL -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK__CI__VI 0x00000001L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK__CI__VI 0x00001000L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK__CI__VI 0x00000004L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK__CI__VI 0x00000800L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK__CI__VI 0x00000002L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK__CI 0x00000200L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK__CI__VI 0x00000020L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK__CI__VI 0x00000040L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK__CI__VI 0x00000080L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK__CI__VI 0x00000100L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK__CI__VI 0x00000018L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK__CI__VI 0x00000400L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK__CI__VI 0x00000001L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK__CI__VI 0x00001000L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK__CI__VI 0x00000004L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK__CI__VI 0x00000800L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK__CI__VI 0x00000002L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK__CI 0x00000200L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK__CI__VI 0x00000020L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK__CI__VI 0x00000040L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK__CI__VI 0x00000080L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK__CI__VI 0x00000100L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK__CI__VI 0x00000018L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK__CI__VI 0x00000400L -#define SMBUS_SLV_CNTL__SMB_SLV_ADR_MASK__CI 0x000000feL -#define SMBUS_SLV_CNTL__SMB_SOFT_RESET_MASK__CI 0x00000001L -#define SMC_ACP_RESP__ACK_MASK__CI__VI 0x00000003L -#define SMC_ACP_RESP__SCRATCH_MASK__CI__VI 0x0000ff00L -#define SMC_DBG_CNTL__DBG_CODE_MASK__CI__VI 0x000000ffL -#define SMC_DBG_CNTL__SINGLE_STEP_MASK__CI__VI 0x00000100L -#define SMC_DEBUG_BUS__DEBUG_EN_MASK__SI 0x00000001L -#define SMC_DMA_CAPTURE_EN__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_0__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_1__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_2__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_3__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_CAPT_7__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_STATUS_0__DMA_BUSY_MASK 0x00000001L -#define SMC_DMA_CORE_STATUS_0__RSVD_MASK 0xfffffffeL -#define SMC_DMA_CORE_STATUS_1__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_STATUS_2__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_STATUS_3__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_STATUS_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_STATUS_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_STATUS_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_CORE_STATUS_7__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_0__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_1__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_2__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_3__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_CAPT_7__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_0__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_1__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_2__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_3__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_DEVQ_STATUS_7__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_0__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_1__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_2__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_3__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_CAPT_7__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_0__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_1__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_2__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_3__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_DMEM_STATUS_7__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_CAPT_1__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_CAPT_2__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_CAPT_3__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_CAPT_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_CAPT_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_CAPT_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_CAPT_7__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_0__START_ADDR_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_1__END_ADDR_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_2__WR_ADDR_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_3__RD_ADDR_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_4__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_5__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_6__RSVD_MASK 0xffffffffL -#define SMC_DMA_IMEMQ_STATUS_7__RSVD_MASK 0xffffffffL -#define SMC_DRAM_ACCESS_CNTL__allow_dram_access_MASK__CI__VI 0x00000001L -#define SMC_DRAM_CNTL_RDREQ_ADDR__addr_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__addr_47_40_MASK__CI__VI 0xff000000L -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__mask_MASK 0x00ff0000L -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__reserved_MASK__SI 0xff000000L -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__tag_MASK 0x0000ffffL -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__atc_MASK__CI__VI 0x00080000L -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__cid_MASK 0x0000ff00L -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__priv_MASK 0x00000020L -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__reserved_MASK__CI__VI 0xfff00000L -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__reserved_MASK__SI 0xfff80000L -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__stall_MASK 0x00000010L -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__swap_MASK 0x000000c0L -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__urg_MASK 0x0000000fL -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__vmid_MASK 0x00070000L -#define SMC_DRAM_CNTL_RDRET_DATA_0_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_0_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_0_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_0_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_0_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_0_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_0_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_0_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_1_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_2_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_3_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_4_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_5_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_6_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_0__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_1__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_2__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_3__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_4__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_5__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_6__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_DATA_7_7__DATA_MASK 0xffffffffL -#define SMC_DRAM_CNTL_RDRET_NACK__nack_0_MASK 0x00000003L -#define SMC_DRAM_CNTL_RDRET_NACK__nack_1_MASK 0x0000000cL -#define SMC_DRAM_CNTL_RDRET_NACK__nack_2_MASK 0x00000030L -#define SMC_DRAM_CNTL_RDRET_NACK__nack_3_MASK 0x000000c0L -#define SMC_DRAM_CNTL_RDRET_NACK__nack_4_MASK 0x00000300L -#define SMC_DRAM_CNTL_RDRET_NACK__nack_5_MASK 0x00000c00L -#define SMC_DRAM_CNTL_RDRET_NACK__nack_6_MASK 0x00003000L -#define SMC_DRAM_CNTL_RDRET_NACK__nack_7_MASK 0x0000c000L -#define SMC_DRAM_CNTL_RDRET_NACK__reserved_MASK 0xffff0000L -#define SMC_DRAM_CNTL_RDRET_VALID__reserved_MASK 0xffffff00L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_0_MASK 0x00000001L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_1_MASK 0x00000002L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_2_MASK 0x00000004L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_3_MASK 0x00000008L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_4_MASK 0x00000010L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_5_MASK 0x00000020L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_6_MASK 0x00000040L -#define SMC_DRAM_CNTL_RDRET_VALID__vld_7_MASK 0x00000080L -#define SMC_DRAM_CNTL_WRREQ_CNTL__atc_MASK__CI__VI 0x20000000L -#define SMC_DRAM_CNTL_WRREQ_CNTL__cid_MASK 0x00ff0000L -#define SMC_DRAM_CNTL_WRREQ_CNTL__priv_MASK 0x00008000L -#define SMC_DRAM_CNTL_WRREQ_CNTL__stall_MASK 0x00004000L -#define SMC_DRAM_CNTL_WRREQ_CNTL__swap_MASK 0x03000000L -#define SMC_DRAM_CNTL_WRREQ_CNTL__tag_MASK 0x000003ffL -#define SMC_DRAM_CNTL_WRREQ_CNTL__urg_MASK 0x00003c00L -#define SMC_DRAM_CNTL_WRREQ_CNTL__vmid_MASK 0x1c000000L -#define SMC_DRAM_CNTL_WRREQ_DATA_0__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_DATA_1__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_DATA_2__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_DATA_3__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_DATA_4__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_DATA_5__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_DATA_6__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_DATA_7__data_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_39_37_MASK 0x00000007L -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_40_MASK__CI__VI 0x000007f8L -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK__CI__VI 0xfffff800L -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK__SI 0xfffffff8L -#define SMC_DRAM_CNTL_WRREQ_LOW_ADDR__addr_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_MASK__mask_MASK 0xffffffffL -#define SMC_DRAM_CNTL_WRREQ_STATUS__credit_counter_MASK 0x0000001fL -#define SMC_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty_MASK 0x00000100L -#define SMC_DRAM_CNTL_WRREQ_STATUS__reserved0_MASK 0x000000e0L -#define SMC_DRAM_CNTL_WRREQ_STATUS__reserved1_MASK 0x0000fe00L -#define SMC_DRAM_CNTL_WRREQ_STATUS__reserved2_MASK 0xfff00000L -#define SMC_DRAM_CNTL_WRREQ_STATUS__tag_pointer_MASK 0x000f0000L -#define SMC_DRAM_CNTL_WRRET_STATUS_0__nack_MASK 0x00000006L -#define SMC_DRAM_CNTL_WRRET_STATUS_0__reserved_MASK 0x0000fff8L -#define SMC_DRAM_CNTL_WRRET_STATUS_0__tag_MASK 0x03ff0000L -#define SMC_DRAM_CNTL_WRRET_STATUS_0__valid_MASK 0x00000001L -#define SMC_DRAM_CNTL_WRRET_STATUS_1__nack_MASK__SI 0x00000006L -#define SMC_DRAM_CNTL_WRRET_STATUS_1__reserved_MASK__SI 0x0000fff8L -#define SMC_DRAM_CNTL_WRRET_STATUS_1__tag_MASK__SI 0x03ff0000L -#define SMC_DRAM_CNTL_WRRET_STATUS_1__valid_MASK__SI 0x00000001L -#define SMC_DRAM_CNTL_WRRET_STATUS_2__nack_MASK__SI 0x00000006L -#define SMC_DRAM_CNTL_WRRET_STATUS_2__reserved_MASK__SI 0x0000fff8L -#define SMC_DRAM_CNTL_WRRET_STATUS_2__tag_MASK__SI 0x03ff0000L -#define SMC_DRAM_CNTL_WRRET_STATUS_2__valid_MASK__SI 0x00000001L -#define SMC_DRAM_CNTL_WRRET_STATUS_3__nack_MASK__SI 0x00000006L -#define SMC_DRAM_CNTL_WRRET_STATUS_3__reserved_MASK__SI 0x0000fff8L -#define SMC_DRAM_CNTL_WRRET_STATUS_3__tag_MASK__SI 0x03ff0000L -#define SMC_DRAM_CNTL_WRRET_STATUS_3__valid_MASK__SI 0x00000001L -#define SMC_EVENT_CLEAR__AZALIA_MASK__SI 0x00000002L -#define SMC_EVENT_CLEAR__BIF_MASK__SI 0x00000004L -#define SMC_EVENT_CLEAR__DC_MASK__SI 0x00000008L -#define SMC_EVENT_CLEAR__DISPLAY_GAP_MASK__SI 0x00000001L -#define SMC_EVENT_CLEAR__MCB_MASK__SI 0x00000010L -#define SMC_EVENT_CLEAR__MCD0_MASK__SI 0x00000020L -#define SMC_EVENT_CLEAR__MCD1_MASK__SI 0x00000040L -#define SMC_EVENT_CLEAR__MCD2_MASK__SI 0x00000080L -#define SMC_EVENT_CLEAR__MCD3_MASK__SI 0x00000100L -#define SMC_EVENT_PENDING__AZALIA_MASK__SI 0x00000002L -#define SMC_EVENT_PENDING__BIF_MASK__SI 0x00000004L -#define SMC_EVENT_PENDING__DC_MASK__SI 0x00000008L -#define SMC_EVENT_PENDING__DISPLAY_GAP_MASK__SI 0x00000001L -#define SMC_EVENT_PENDING__MCB_MASK__SI 0x00000010L -#define SMC_EVENT_PENDING__MCD0_MASK__SI 0x00000020L -#define SMC_EVENT_PENDING__MCD1_MASK__SI 0x00000040L -#define SMC_EVENT_PENDING__MCD2_MASK__SI 0x00000080L -#define SMC_EVENT_PENDING__MCD3_MASK__SI 0x00000100L -#define SMC_EVENT_POLARITY__AZALIA_MASK__SI 0x00000002L -#define SMC_EVENT_POLARITY__BIF_MASK__SI 0x00000004L -#define SMC_EVENT_POLARITY__DC_MASK__SI 0x00000008L -#define SMC_EVENT_POLARITY__DISPLAY_GAP_MASK__SI 0x00000001L -#define SMC_EVENT_POLARITY__MCB_MASK__SI 0x00000010L -#define SMC_EVENT_POLARITY__MCD0_MASK__SI 0x00000020L -#define SMC_EVENT_POLARITY__MCD1_MASK__SI 0x00000040L -#define SMC_EVENT_POLARITY__MCD2_MASK__SI 0x00000080L -#define SMC_EVENT_POLARITY__MCD3_MASK__SI 0x00000100L -#define SMC_EVENT_SENSE__AZALIA_MASK__SI 0x00000002L -#define SMC_EVENT_SENSE__BIF_MASK__SI 0x00000004L -#define SMC_EVENT_SENSE__DC_MASK__SI 0x00000008L -#define SMC_EVENT_SENSE__DISPLAY_GAP_MASK__SI 0x00000001L -#define SMC_EVENT_SENSE__MCB_MASK__SI 0x00000010L -#define SMC_EVENT_SENSE__MCD0_MASK__SI 0x00000020L -#define SMC_EVENT_SENSE__MCD1_MASK__SI 0x00000040L -#define SMC_EVENT_SENSE__MCD2_MASK__SI 0x00000080L -#define SMC_EVENT_SENSE__MCD3_MASK__SI 0x00000100L -#define SMC_HOST_MSG__SMC_HOST_msg_MASK 0xffffffffL -#define SMC_HOST_RESP__SMC_HOST_resp_MASK 0xffffffffL -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x00000001L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK__CI__VI 0x00000002L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK__SI 0x00000100L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK__CI__VI 0x00000004L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK__SI 0x00010000L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK__CI__VI 0x00000008L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK__SI 0x01000000L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK__CI__VI 0x00000010L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK__CI__VI 0x00000020L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK__CI__VI 0x00000040L -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK__CI__VI 0x00000080L -#define SMC_IND_DATA_0__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA_1__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA_2__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA_3__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA_4__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA_5__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA_6__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA_7__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffffL -#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffffL -#define SMC_INTR_CNTL_INTR_ID__INTR_ID_MASK 0x000000ffL -#define SMC_INTR_CNTL_INTR_ID__RESERVED_MASK 0xffffff00L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_0_MASK 0x00000001L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_10_MASK 0x00000400L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_11_MASK 0x00000800L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_12_MASK 0x00001000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_13_MASK 0x00002000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_14_MASK 0x00004000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_15_MASK 0x00008000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_16_MASK 0x00010000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_17_MASK 0x00020000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_18_MASK 0x00040000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_19_MASK 0x00080000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_1_MASK 0x00000002L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_20_MASK 0x00100000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_21_MASK 0x00200000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_22_MASK 0x00400000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_23_MASK 0x00800000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_24_MASK 0x01000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_25_MASK 0x02000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_26_MASK 0x04000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_27_MASK 0x08000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_28_MASK 0x10000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_29_MASK 0x20000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_2_MASK 0x00000004L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_30_MASK 0x40000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_31_MASK 0x80000000L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_3_MASK 0x00000008L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_4_MASK 0x00000010L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_5_MASK 0x00000020L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_6_MASK 0x00000040L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_7_MASK 0x00000080L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_8_MASK 0x00000100L -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_9_MASK 0x00000200L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_0_MASK 0x00000001L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_10_MASK 0x00000400L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_11_MASK 0x00000800L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_12_MASK 0x00001000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_13_MASK 0x00002000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_14_MASK 0x00004000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_15_MASK 0x00008000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_16_MASK 0x00010000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_17_MASK 0x00020000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_18_MASK 0x00040000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_19_MASK 0x00080000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_1_MASK 0x00000002L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_20_MASK 0x00100000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_21_MASK 0x00200000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_22_MASK 0x00400000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_23_MASK 0x00800000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_24_MASK 0x01000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_25_MASK 0x02000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_26_MASK 0x04000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_27_MASK 0x08000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_28_MASK 0x10000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_29_MASK 0x20000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_2_MASK 0x00000004L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_30_MASK 0x40000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_31_MASK 0x80000000L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_3_MASK 0x00000008L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_4_MASK 0x00000010L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_5_MASK 0x00000020L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_6_MASK 0x00000040L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_7_MASK 0x00000080L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_8_MASK 0x00000100L -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_9_MASK 0x00000200L -#define SMC_INTR_CNTL_LINE__INTR_LINE_MASK 0x00000001L -#define SMC_INTR_CNTL_LINE__RESERVED_MASK 0xfffffffeL -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_0_MASK 0x00000001L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_10_MASK 0x00000400L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_11_MASK 0x00000800L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_12_MASK 0x00001000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_13_MASK 0x00002000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_14_MASK 0x00004000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_15_MASK 0x00008000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_16_MASK 0x00010000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_17_MASK 0x00020000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_18_MASK 0x00040000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_19_MASK 0x00080000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_1_MASK 0x00000002L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_20_MASK 0x00100000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_21_MASK 0x00200000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_22_MASK 0x00400000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_23_MASK 0x00800000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_24_MASK 0x01000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_25_MASK 0x02000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_26_MASK 0x04000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_27_MASK 0x08000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_28_MASK 0x10000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_29_MASK 0x20000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_2_MASK 0x00000004L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_30_MASK 0x40000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_31_MASK 0x80000000L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_3_MASK 0x00000008L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_4_MASK 0x00000010L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_5_MASK 0x00000020L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_6_MASK 0x00000040L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_7_MASK 0x00000080L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_8_MASK 0x00000100L -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_9_MASK 0x00000200L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_0_MASK 0x00000001L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_10_MASK 0x00000400L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_11_MASK 0x00000800L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_12_MASK 0x00001000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_13_MASK 0x00002000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_14_MASK 0x00004000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_15_MASK 0x00008000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_16_MASK 0x00010000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_17_MASK 0x00020000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_18_MASK 0x00040000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_19_MASK 0x00080000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_1_MASK 0x00000002L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_20_MASK 0x00100000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_21_MASK 0x00200000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_22_MASK 0x00400000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_23_MASK 0x00800000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_24_MASK 0x01000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_25_MASK 0x02000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_26_MASK 0x04000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_27_MASK 0x08000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_28_MASK 0x10000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_29_MASK 0x20000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_2_MASK 0x00000004L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_30_MASK 0x40000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_31_MASK 0x80000000L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_3_MASK 0x00000008L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_4_MASK 0x00000010L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_5_MASK 0x00000020L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_6_MASK 0x00000040L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_7_MASK 0x00000080L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_8_MASK 0x00000100L -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_9_MASK 0x00000200L -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_0_MASK 0x000000ffL -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_1_MASK 0x0000ff00L -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_2_MASK 0x00ff0000L -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_3_MASK 0xff000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_0_MASK 0x00000001L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_10_MASK 0x00000400L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_11_MASK 0x00000800L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_12_MASK 0x00001000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_13_MASK 0x00002000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_14_MASK 0x00004000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_15_MASK 0x00008000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_16_MASK 0x00010000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_17_MASK 0x00020000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_18_MASK 0x00040000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_19_MASK 0x00080000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_1_MASK 0x00000002L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_20_MASK 0x00100000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_21_MASK 0x00200000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_22_MASK 0x00400000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_23_MASK 0x00800000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_24_MASK 0x01000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_25_MASK 0x02000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_26_MASK 0x04000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_27_MASK 0x08000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_28_MASK 0x10000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_29_MASK 0x20000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_2_MASK 0x00000004L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_30_MASK 0x40000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_31_MASK 0x80000000L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_3_MASK 0x00000008L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_4_MASK 0x00000010L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_5_MASK 0x00000020L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_6_MASK 0x00000040L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_7_MASK 0x00000080L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_8_MASK 0x00000100L -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_9_MASK 0x00000200L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_0_MASK 0x00000001L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_10_MASK 0x00000400L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_11_MASK 0x00000800L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_12_MASK 0x00001000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_13_MASK 0x00002000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_14_MASK 0x00004000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_15_MASK 0x00008000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_16_MASK 0x00010000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_17_MASK 0x00020000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_18_MASK 0x00040000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_19_MASK 0x00080000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_1_MASK 0x00000002L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_20_MASK 0x00100000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_21_MASK 0x00200000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_22_MASK 0x00400000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_23_MASK 0x00800000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_24_MASK 0x01000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_25_MASK 0x02000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_26_MASK 0x04000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_27_MASK 0x08000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_28_MASK 0x10000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_29_MASK 0x20000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_2_MASK 0x00000004L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_30_MASK 0x40000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_31_MASK 0x80000000L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_3_MASK 0x00000008L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_4_MASK 0x00000010L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_5_MASK 0x00000020L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_6_MASK 0x00000040L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_7_MASK 0x00000080L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_8_MASK 0x00000100L -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_9_MASK 0x00000200L -#define SMC_INT_GPIO_CLEAR__INT_GPIO_CLEAR_MASK__SI 0xffffffffL -#define SMC_INT_GPIO_PENDING__INT_GPIO_PENDING_MASK__SI 0xffffffffL -#define SMC_INT_GPIO_POLARITY__INT_GPIO_POLARITY_MASK__SI 0xffffffffL -#define SMC_INT_GPIO_SENSE__INT_GPIO_SENSE_MASK__SI 0xffffffffL -#define SMC_INT_REQ__INT_REQ_MASK__SI 0x00000001L -#define SMC_INT_REQ__RESERVED_MASK__SI 0x0000fffeL -#define SMC_INT_REQ__SERV_INDEX_MASK__SI 0xffff0000L -#define SMC_INT_STATUS__INT_ACK_MASK__SI 0x00000001L -#define SMC_INT_STATUS__INT_DONE_MASK__SI 0x00000002L -#define SMC_LM32_ADDER0__operand_0_MASK 0xffffffffL -#define SMC_LM32_ADDER1__operand_1_MASK 0xffffffffL -#define SMC_LM32_ADDER2__result_MASK 0xffffffffL -#define SMC_LM32_ARITH_MISC__adder_carry_n_MASK 0x00000002L -#define SMC_LM32_ARITH_MISC__adder_op_MASK 0x00000001L -#define SMC_LM32_ARITH_MISC__adder_overflow_MASK 0x00000004L -#define SMC_LM32_ARITH_MISC__mc_arith_divide_MASK 0x00000008L -#define SMC_LM32_ARITH_MISC__mc_arith_divide_by_0_MASK 0x00000020L -#define SMC_LM32_ARITH_MISC__mc_arith_modulus_MASK 0x00000010L -#define SMC_LM32_BP0__BP_ADDR_MASK 0xfffffffcL -#define SMC_LM32_BP0__BP_EN_MASK 0x00000001L -#define SMC_LM32_BP1__BP_ADDR_MASK 0xfffffffcL -#define SMC_LM32_BP1__BP_EN_MASK 0x00000001L -#define SMC_LM32_BP2__BP_ADDR_MASK 0xfffffffcL -#define SMC_LM32_BP2__BP_EN_MASK 0x00000001L -#define SMC_LM32_BP3__BP_ADDR_MASK 0xfffffffcL -#define SMC_LM32_BP3__BP_EN_MASK 0x00000001L -#define SMC_LM32_DC__C0_MASK 0x0000000cL -#define SMC_LM32_DC__C1_MASK 0x00000030L -#define SMC_LM32_DC__C2_MASK 0x000000c0L -#define SMC_LM32_DC__C3_MASK 0x00000300L -#define SMC_LM32_DC__REMAP_EXCEPTIONS_MASK 0x00000002L -#define SMC_LM32_DC__SINGLE_STEP_MASK 0x00000001L -#define SMC_LM32_DEBA__DEBA_MASK 0xffffff00L -#define SMC_LM32_GPR_0__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_10__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_11__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_12__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_13__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_14__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_15__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_16__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_17__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_18__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_19__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_1__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_20__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_21__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_22__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_23__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_24__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_25__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_26__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_27__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_28__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_29__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_2__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_30__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_31__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_3__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_4__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_5__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_6__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_7__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_8__gpr_MASK 0xffffffffL -#define SMC_LM32_GPR_9__gpr_MASK 0xffffffffL -#define SMC_LM32_MC_ARITH__result_MASK 0xffffffffL -#define SMC_LM32_MULTIPLIER__result_MASK 0xffffffffL -#define SMC_LM32_MULT_MC0__operand_0_MASK 0xffffffffL -#define SMC_LM32_MULT_MC1__operand_1_MASK 0xffffffffL -#define SMC_LM32_WP0__WP_ADDR_MASK 0xffffffffL -#define SMC_LM32_WP1__WP_ADDR_MASK 0xffffffffL -#define SMC_LM32_WP2__WP_ADDR_MASK 0xffffffffL -#define SMC_LM32_WP3__WP_ADDR_MASK 0xffffffffL -#define SMC_MESSAGE_0__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_0__SMC_MSG_MASK__SI 0xffffffffL -#define SMC_MESSAGE_10__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_11__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_1__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_1__SMC_MSG_MASK__SI 0xffffffffL -#define SMC_MESSAGE_2__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_3__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_4__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_5__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_6__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_7__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_8__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MESSAGE_9__SMC_MSG_MASK__CI__VI 0x0000ffffL -#define SMC_MISC_HANDSHAKE__CGPG_DONE_MASK__CI__VI 0x00000001L -#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK__CI__VI 0xffffffffL -#define SMC_MUTEX_0__MUTEX_0_MASK__CI__VI 0x000000ffL -#define SMC_MUTEX_1__MUTEX_MASK__CI__VI 0x000000ffL -#define SMC_MUTEX_2__MUTEX_MASK__CI__VI 0x000000ffL -#define SMC_MUTEX_3__MUTEX_MASK__CI__VI 0x000000ffL -#define SMC_PC_A__smc_pc_a_MASK__CI__VI 0xffffffffL -#define SMC_PC_C__smc_pc_c_MASK__CI__VI 0xffffffffL -#define SMC_PC_D__smc_pc_d_MASK__CI__VI 0xffffffffL -#define SMC_PC_F__smc_pc_f_MASK__CI__VI 0xffffffffL -#define SMC_PC_M__smc_pc_m_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_0_BR_INST__branch_instruction_0_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_0_BR_INST__branch_instruction_0_MASK__SI 0x3fffffffL -#define SMC_PC_TRACE_0_BR_TAR__branch_target_0_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_0_BR_TAR__branch_target_0_MASK__SI 0x3fffffffL -#define SMC_PC_TRACE_1_BR_INST__branch_instruction_1_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_1_BR_INST__branch_instruction_1_MASK__SI 0x3fffffffL -#define SMC_PC_TRACE_1_BR_TAR__branch_target_1_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_1_BR_TAR__branch_target_1_MASK__SI 0x3fffffffL -#define SMC_PC_TRACE_2_BR_INST__branch_instruction_2_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_2_BR_INST__branch_instruction_2_MASK__SI 0x3fffffffL -#define SMC_PC_TRACE_2_BR_TAR__branch_target_2_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_2_BR_TAR__branch_target_2_MASK__SI 0x3fffffffL -#define SMC_PC_TRACE_3_BR_INST__branch_instruction_3_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_3_BR_INST__branch_instruction_3_MASK__SI 0x3fffffffL -#define SMC_PC_TRACE_3_BR_TAR__branch_target_3_MASK__CI__VI 0xffffffffL -#define SMC_PC_TRACE_3_BR_TAR__branch_target_3_MASK__SI 0x3fffffffL -#define SMC_PC_W__smc_pc_w_MASK__CI__VI 0xffffffffL -#define SMC_PC_X__smc_pc_x_MASK__CI__VI 0xffffffffL -#define SMC_PC__smc_pc_MASK__SI 0x3fffffffL -#define SMC_RAMFLOP_0__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_10__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_11__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_12__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_13__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_14__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_15__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_16__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_17__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_18__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_19__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_1__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_20__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_21__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_22__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_23__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_24__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_25__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_26__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_27__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_28__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_29__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_2__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_30__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_31__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_3__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_4__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_5__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_6__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_7__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_8__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RAMFLOP_9__DATA_MASK__CI__VI 0xffffffffL -#define SMC_RESP_0__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_0__SMC_RESP_MASK__SI 0xffffffffL -#define SMC_RESP_10__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_11__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_1__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_1__SMC_RESP_MASK__SI 0xffffffffL -#define SMC_RESP_2__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_3__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_4__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_5__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_6__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_7__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_8__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_RESP_9__SMC_RESP_MASK__CI__VI 0x0000ffffL -#define SMC_SCRATCH0__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH10__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH11__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH12__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH1__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH2__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH3__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH4__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH5__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH6__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH7__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH8__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffffL -#define SMC_SP__SP_MASK__CI__VI 0xffffffffL -#define SMC_SRBM_CREDITS__CREDIT_NUM_MASK 0x0000001fL -#define SMC_SW_INT_CTXID__CTXID_MASK__CI__VI 0x0fffffffL -#define SMC_SW_INT__ID_MASK__CI__VI 0x000000ffL -#define SMC_SW_INT__VALID_MASK__CI__VI 0x00000100L -#define SMC_SYSCON_ACP_RESP__ACK_MASK__CI__VI 0x00000003L -#define SMC_SYSCON_ACP_RESP__SCRATCH_MASK__CI__VI 0x0000ff00L -#define SMC_SYSCON_DBG_CNTL__DBG_CODE_MASK__CI__VI 0x000000ffL -#define SMC_SYSCON_DBG_CNTL__SINGLE_STEP_MASK__CI__VI 0x00000100L -#define SMC_SYSCON_GPIO_IN_0__gpio_in_MASK 0xffffffffL -#define SMC_SYSCON_GPIO_IN_1__gpio_in_MASK 0xffffffffL -#define SMC_SYSCON_GPIO_IN_2__gpio_in_MASK 0xffffffffL -#define SMC_SYSCON_GPIO_IN_3__gpio_in_MASK 0xffffffffL -#define SMC_SYSCON_GPIO_OUT_0__gpio_out_MASK 0xffffffffL -#define SMC_SYSCON_GPIO_OUT_1__gpio_out_MASK 0xffffffffL -#define SMC_SYSCON_GPIO_OUT_2__gpio_out_MASK 0xffffffffL -#define SMC_SYSCON_GPIO_OUT_3__gpio_out_MASK 0xffffffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_0_1__host_ram_pwrdn_0_reg_MASK__SI 0x0000ffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_0_1__host_ram_pwrdn_1_reg_MASK__SI 0xffff0000L -#define SMC_SYSCON_HOST_RAM_PWRDN_0__host_ram_pwrdn_0_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_1__host_ram_pwrdn_1_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_2_3__host_ram_pwrdn_2_reg_MASK__SI 0x0000ffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_2_3__host_ram_pwrdn_3_reg_MASK__SI 0xffff0000L -#define SMC_SYSCON_HOST_RAM_PWRDN_2__host_ram_pwrdn_2_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_3__host_ram_pwrdn_3_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_4__host_ram_pwrdn_4_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_HOST_RAM_PWRDN_4__host_ram_pwrdn_4_reg_MASK__SI 0x0000ffffL -#define SMC_SYSCON_INTR_SERVICE_INDEX__drv_service_index_MASK__SI 0x0000ffffL -#define SMC_SYSCON_INTR_STATUS__drv_intr_req_ack_MASK__SI 0x00000001L -#define SMC_SYSCON_INTR_STATUS__drv_intr_req_done_MASK__SI 0x00000100L -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_auto_cg_en_MASK 0x00000002L -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_auto_cg_timeout_MASK 0x00ffff00L -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_ck_disable_MASK 0x00000001L -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_cken_MASK 0x01000000L -#define SMC_SYSCON_LM32_CLOCK_CNTL_1__lm32_auto_ck_disable_MASK 0x00000001L -#define SMC_SYSCON_LM32_CLOCK_CNTL_2__lm32_wake_on_irq_MASK 0xffffffffL -#define SMC_SYSCON_LM32_RESET_CNTL__ColdReset_MASK__SI 0x80000000L -#define SMC_SYSCON_LM32_RESET_CNTL__RegReset_MASK 0x40000000L -#define SMC_SYSCON_LM32_RESET_CNTL__lm32_rst_reg_MASK 0x00000001L -#define SMC_SYSCON_LM32_RESET_CNTL__srbm_soft_rst_override_MASK__CI__VI 0x00000002L -#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en_MASK__CI__VI 0x00000001L -#define SMC_SYSCON_MSG_0__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_0__smc_msg_MASK__SI 0xffffffffL -#define SMC_SYSCON_MSG_10__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_11__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_1__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_1__smc_msg_MASK__SI 0xffffffffL -#define SMC_SYSCON_MSG_2__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_3__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_4__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_5__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_6__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_7__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_8__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_9__smc_msg_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_10__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_11__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_1__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_2__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_3__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_4__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_5__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_6__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_7__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_8__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_ARG_9__smc_msg_arg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_MSG_RESP_0__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_0__smc_resp_MASK__SI 0xffffffffL -#define SMC_SYSCON_MSG_RESP_10__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_11__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_1__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_1__smc_resp_MASK__SI 0xffffffffL -#define SMC_SYSCON_MSG_RESP_2__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_3__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_4__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_5__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_6__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_7__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_8__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSG_RESP_9__smc_resp_MASK__CI__VI 0x0000ffffL -#define SMC_SYSCON_MSTRCFG_0__mbus2_mstr_cg_override_MASK 0x40000000L -#define SMC_SYSCON_MSTRCFG_0__mbus2_mstr_disable_MASK 0x80000000L -#define SMC_SYSCON_MSTRCFG_0__mbus2_mstr_pri_MASK 0x00000007L -#define SMC_SYSCON_MSTRCFG_1__mbus2_mstr_cg_override_MASK 0x40000000L -#define SMC_SYSCON_MSTRCFG_1__mbus2_mstr_disable_MASK 0x80000000L -#define SMC_SYSCON_MSTRCFG_1__mbus2_mstr_pri_MASK 0x00000007L -#define SMC_SYSCON_MSTRCFG_2__mbus2_mstr_cg_override_MASK 0x40000000L -#define SMC_SYSCON_MSTRCFG_2__mbus2_mstr_disable_MASK 0x80000000L -#define SMC_SYSCON_MSTRCFG_2__mbus2_mstr_pri_MASK 0x00000007L -#define SMC_SYSCON_MSTRCFG_3__mbus2_mstr_cg_override_MASK 0x40000000L -#define SMC_SYSCON_MSTRCFG_3__mbus2_mstr_disable_MASK 0x80000000L -#define SMC_SYSCON_MSTRCFG_3__mbus2_mstr_pri_MASK 0x00000007L -#define SMC_SYSCON_MSTRCFG_4__mbus2_mstr_cg_override_MASK 0x40000000L -#define SMC_SYSCON_MSTRCFG_4__mbus2_mstr_disable_MASK 0x80000000L -#define SMC_SYSCON_MSTRCFG_4__mbus2_mstr_pri_MASK 0x00000007L -#define SMC_SYSCON_MSTRCFG_5__mbus2_mstr_cg_override_MASK__CI__VI 0x40000000L -#define SMC_SYSCON_MSTRCFG_5__mbus2_mstr_disable_MASK__CI__VI 0x80000000L -#define SMC_SYSCON_MSTRCFG_5__mbus2_mstr_pri_MASK__CI__VI 0x00000007L -#define SMC_SYSCON_MUTEX_0__MUTEX_0_MASK__CI__VI 0x000000ffL -#define SMC_SYSCON_MUTEX_1__MUTEX_1_MASK__CI__VI 0x000000ffL -#define SMC_SYSCON_MUTEX_2__MUTEX_2_MASK__CI__VI 0x000000ffL -#define SMC_SYSCON_MUTEX_3__MUTEX_3_MASK__CI__VI 0x000000ffL -#define SMC_SYSCON_RAM_CFG__MEB_timeout_MASK 0x0000ff00L -#define SMC_SYSCON_RAM_CFG__ram_arb_scheme_MASK 0x00000001L -#define SMC_SYSCON_RAM_CFG__ram_read_pipeline_MASK 0x00000002L -#define SMC_SYSCON_SLVCFG__mbus2_slv_cg_en_MASK 0x80000000L -#define SMC_SYSCON_SLVCFG__mbus2_slv_cg_timeout_MASK 0x000fffffL -#define SMC_SYSCON_SP__SP_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_UC_RAM_PWRDN_0_1__uc_ram_pwrdn_0_reg_MASK__SI 0x0000ffffL -#define SMC_SYSCON_UC_RAM_PWRDN_0_1__uc_ram_pwrdn_1_reg_MASK__SI 0xffff0000L -#define SMC_SYSCON_UC_RAM_PWRDN_0__uc_ram_pwrdn_0_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_UC_RAM_PWRDN_1__uc_ram_pwrdn_1_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_UC_RAM_PWRDN_2_3__uc_ram_pwrdn_2_reg_MASK__SI 0x0000ffffL -#define SMC_SYSCON_UC_RAM_PWRDN_2_3__uc_ram_pwrdn_3_reg_MASK__SI 0xffff0000L -#define SMC_SYSCON_UC_RAM_PWRDN_2__uc_ram_pwrdn_2_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_UC_RAM_PWRDN_3__uc_ram_pwrdn_3_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_UC_RAM_PWRDN_4__uc_ram_pwrdn_4_reg_MASK__CI__VI 0xffffffffL -#define SMC_SYSCON_UC_RAM_PWRDN_4__uc_ram_pwrdn_4_reg_MASK__SI 0x0000ffffL -#define SMC_TIMER_0_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_0_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_0_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_0_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_0_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_0_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_0_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_0_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_0_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_0_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_0_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_0_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_0_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_0_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_0_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_0_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_0_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_0_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_0_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_0_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_0_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_0_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_0_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_0_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_0_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_0_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_0_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_1_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_1_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_1_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_1_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_1_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_1_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_1_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_1_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_1_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_1_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_1_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_1_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_1_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_1_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_1_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_1_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_1_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_1_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_1_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_1_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_1_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_1_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_1_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_1_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_1_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_1_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_1_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_2_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_2_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_2_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_2_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_2_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_2_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_2_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_2_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_2_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_2_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_2_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_2_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_2_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_2_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_2_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_2_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_2_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_2_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_2_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_2_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_2_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_2_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_2_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_2_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_2_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_2_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_2_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_3_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_3_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_3_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_3_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_3_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_3_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_3_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_3_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_3_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_3_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_3_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_3_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_3_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_3_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_3_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_3_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_3_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_3_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_3_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_3_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_3_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_3_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_3_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_3_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_3_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_3_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_3_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_4_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_4_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_4_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_4_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_4_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_4_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_4_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_4_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_4_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_4_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_4_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_4_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_4_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_4_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_4_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_4_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_4_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_4_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_4_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_4_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_4_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_4_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_4_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_4_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_4_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_4_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_4_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_5_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_5_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_5_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_5_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_5_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_5_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_5_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_5_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_5_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_5_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_5_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_5_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_5_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_5_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_5_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_5_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_5_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_5_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_5_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_5_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_5_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_5_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_5_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_5_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_5_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_5_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_5_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_6_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_6_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_6_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_6_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_6_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_6_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_6_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_6_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_6_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_6_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_6_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_6_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_6_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_6_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_6_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_6_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_6_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_6_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_6_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_6_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_6_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_6_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_6_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_6_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_6_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_6_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_6_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_7_0_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_7_1_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_7_2_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_7_3_OCMP__DATA_MASK 0xffffffffL -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_7_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L -#define SMC_TIMER_7_CNT__VALUE_MASK 0xffffffffL -#define SMC_TIMER_7_CTRL_0__CLEAR_MASK__CI__VI 0x00010000L -#define SMC_TIMER_7_CTRL_0__CLEAR_MASK__SI 0x00000100L -#define SMC_TIMER_7_CTRL_0__DEC_MASK__CI__VI 0x00000100L -#define SMC_TIMER_7_CTRL_0__DEC_MASK__SI 0x00010000L -#define SMC_TIMER_7_CTRL_0__PULSE_COUNT_MODE_MASK__CI__VI 0x00000001L -#define SMC_TIMER_7_CTRL_0__PULSE_COUNT_MODE_MASK__SI 0x01000000L -#define SMC_TIMER_7_CTRL_0__START_MASK__CI__VI 0x01000000L -#define SMC_TIMER_7_CTRL_0__START_MASK__SI 0x00000001L -#define SMC_TIMER_7_CTRL_1__PWM_OUTPUT_EN_MASK__CI__VI 0x01000000L -#define SMC_TIMER_7_CTRL_1__PWM_OUTPUT_EN_MASK__SI 0x00000001L -#define SMC_TIMER_7_CTRL_1__RESERVED_MASK__CI__VI 0x000000ffL -#define SMC_TIMER_7_CTRL_1__RESERVED_MASK__SI 0xfffe0000L -#define SMC_TIMER_7_CTRL_1__TIMER_SATURATION_EN_MASK__CI__VI 0x00000100L -#define SMC_TIMER_7_CTRL_1__TIMER_SATURATION_EN_MASK__SI 0x00010000L -#define SMC_TIMER_7_CTRL_1__TIME_SLICE_MODE_EN_MASK__CI__VI 0x00010000L -#define SMC_TIMER_7_CTRL_1__TIME_SLICE_MODE_EN_MASK__SI 0x00000100L -#define SMC_TIMER_7_INTERRUPT__ENABLE_0_MASK 0x00000001L -#define SMC_TIMER_7_INTERRUPT__ENABLE_1_MASK 0x00000002L -#define SMC_TIMER_7_INTERRUPT__ENABLE_2_MASK 0x00000004L -#define SMC_TIMER_7_INTERRUPT__ENABLE_3_MASK 0x00000008L -#define SMC_TIMER_7_INTERRUPT__RESERVED_MASK 0xfffffff0L -#define SMC_UART_CFG__clk_div_MASK__SI__CI 0x0000ffffL -#define SMC_UART_CG_CNTL__rx_clk_en_override_MASK__CI 0x00000002L -#define SMC_UART_CG_CNTL__tx_clk_en_override_MASK__CI 0x00000001L -#define SMC_UART_RXQ_STATUS__rx_byte_MASK__SI__CI 0x000000ffL -#define SMC_UART_RXQ_STATUS__rx_frame_error_MASK__SI__CI 0x00000100L -#define SMC_UART_RXQ_STATUS__rxq_count_MASK__SI__CI 0x0000f000L -#define SMC_UART_RXQ_STATUS__rxq_empty_MASK__SI__CI 0x00000200L -#define SMC_UART_RXQ_STATUS__rxq_full_MASK__SI__CI 0x00000400L -#define SMC_UART_RXQ_STATUS__rxq_overflow_MASK__SI__CI 0x00000800L -#define SMC_UART_RX_CFG__internal_loopback_MASK__SI__CI 0x00000002L -#define SMC_UART_RX_CFG__rx_ena_MASK__SI__CI 0x00000001L -#define SMC_UART_TX_Q__tx_byte_MASK__SI__CI 0x000000ffL -#define SMC_UART_TX_STATUS__txq_count_MASK__SI__CI 0x000000ffL -#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xffffffffL -#define SMU_AUTH_STATUS__SMU_AUTH_DONE_MASK__CI__VI 0x00000001L -#define SMU_AUTH_STATUS__SMU_AUTH_PASS_MASK__CI__VI 0x00000002L -#define SMU_BLOCKED_DATA__blocked_data_MASK__CI__VI 0xffffffffL -#define SMU_BRIDGE_MSTRCFG__mbus2_mstr_cg_override_MASK__CI__VI 0x40000000L -#define SMU_BRIDGE_MSTRCFG__mbus2_mstr_disable_MASK__CI__VI 0x80000000L -#define SMU_BRIDGE_MSTRCFG__mbus2_mstr_pri_MASK__CI__VI 0x00000001L -#define SMU_CABLESAFE__CABLESAFE_MASK__CI__VI 0x0000003fL -#define SMU_DFT_MISC__PCIE_DTM_XFER_PHY_MASK__CI__VI 0x00000002L -#define SMU_DFT_MISC__PCIE_DTM_XFER_WRP_MASK__CI__VI 0x00000001L -#define SMU_DMA_ACTIVE_SAMPLE__ENABLE_MASK__CI__VI 0x00000001L -#define SMU_DMA_ACTIVE_SAMPLE__PERIOD_MASK__CI__VI 0xffff0000L -#define SMU_DMA_ACTIVE_SAMPLE__TRAN_CNT_MASK__CI__VI 0x00000300L -#define SMU_EFUSE_0__EFUSE_DATA_MASK__CI__VI 0xffffffffL -#define SMU_FIRMWARE_AUTH__SMU_AUTH_IN_PROG_MASK__CI__VI 0x00000001L -#define SMU_FIRMWARE_AUTH__SMU_AUTH_counter_MASK__CI__VI 0x00000f00L -#define SMU_FIRMWARE_AUTH__SMU_KEY_RD_DONE_MASK__CI__VI 0x00000006L -#define SMU_FIRMWARE_AUTH__SMU_KEY_SEL_MASK__CI__VI 0x00020000L -#define SMU_FIRMWARE_AUTH__SMU_PROTECTED_MODE_MASK__CI__VI 0x00010000L -#define SMU_FIRMWARE_AUTH__SMU_SRAM_RD_BLOCK_EN_MASK__CI__VI 0x00000008L -#define SMU_FIRMWARE_AUTH__SMU_SRAM_WR_BLOCK_EN_MASK__CI__VI 0x00000010L -#define SMU_GPIOPAD_A__GPIO_A_MASK__CI__VI 0x7fffffffL -#define SMU_GPIOPAD_EN__GPIO_EN_MASK__CI__VI 0x7fffffffL -#define SMU_GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK__CI__VI 0x00000020L -#define SMU_GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK__CI__VI 0x0000001fL -#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK__CI__VI 0x1fffffffL -#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK__CI__VI 0x80000000L -#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK__CI__VI 0x1fffffffL -#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK__CI__VI 0x80000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK__CI__VI 0x00000001L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK__CI__VI 0x00000400L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK__CI__VI 0x00000800L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK__CI__VI 0x00001000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK__CI__VI 0x00002000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK__CI__VI 0x00004000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK__CI__VI 0x00008000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK__CI__VI 0x00010000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK__CI__VI 0x00020000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK__CI__VI 0x00040000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK__CI__VI 0x00080000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK__CI__VI 0x00000002L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK__CI__VI 0x00100000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK__CI__VI 0x00200000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK__CI__VI 0x00400000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK__CI__VI 0x00800000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK__CI__VI 0x01000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK__CI__VI 0x02000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK__CI__VI 0x04000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK__CI__VI 0x08000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK__CI__VI 0x10000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK__CI__VI 0x00000004L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK__CI__VI 0x00000008L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK__CI__VI 0x00000010L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK__CI__VI 0x00000020L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK__CI__VI 0x00000040L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK__CI__VI 0x00000080L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK__CI__VI 0x00000100L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK__CI__VI 0x00000200L -#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK__CI__VI 0x80000000L -#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK__CI__VI 0x1fffffffL -#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK__CI__VI 0x80000000L -#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK__CI__VI 0x1fffffffL -#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK__CI__VI 0x80000000L -#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK__CI__VI 0x1fffffffL -#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK__CI__VI 0x80000000L -#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK__CI__VI 0x7fffffffL -#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK__CI__VI 0x7fffffffL -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK__CI__VI 0x00000001L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK__CI__VI 0x00000400L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK__CI__VI 0x00000800L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK__CI__VI 0x00001000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK__CI__VI 0x00002000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK__CI__VI 0x00004000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK__CI__VI 0x00008000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK__CI__VI 0x00010000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK__CI__VI 0x00020000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK__CI__VI 0x00040000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK__CI__VI 0x00080000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK__CI__VI 0x00000002L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK__CI__VI 0x00100000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK__CI__VI 0x00200000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK__CI__VI 0x00400000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK__CI__VI 0x00800000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK__CI__VI 0x01000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK__CI__VI 0x02000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK__CI__VI 0x04000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK__CI__VI 0x08000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK__CI__VI 0x10000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK__CI__VI 0x20000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK__CI__VI 0x00000004L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK__CI__VI 0x40000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK__CI__VI 0x00000008L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK__CI__VI 0x00000010L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK__CI__VI 0x00000020L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK__CI__VI 0x00000040L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK__CI__VI 0x00000080L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK__CI__VI 0x00000100L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK__CI__VI 0x00000200L -#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK__CI__VI 0x7fffffffL -#define SMU_GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK__CI__VI 0x7fffffffL -#define SMU_GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK__CI__VI 0x0000000fL -#define SMU_GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK__CI__VI 0x000000f0L -#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK__CI__VI 0x00000001L -#define SMU_GPIOPAD_Y__GPIO_Y_MASK__CI__VI 0x7fffffffL -#define SMU_IOC_CTRL__IOC_mst_busy_MASK__CI__VI 0x00000010L -#define SMU_IOC_CTRL__IOC_mst_debug_rst_MASK__CI__VI 0x00000040L -#define SMU_IOC_CTRL__IOC_mst_disabled_MASK__CI__VI 0x00000020L -#define SMU_IOC_CTRL__IOC_mst_force_active_MASK__CI__VI 0x00000004L -#define SMU_IOC_CTRL__IOC_mst_rdValid_MASK__CI__VI 0x00000008L -#define SMU_IOC_CTRL__IOC_mst_send_MASK__CI__VI 0x00000001L -#define SMU_IOC_CTRL__IOC_mst_stop_MASK__CI__VI 0x00000002L -#define SMU_IOC_CTRL__IOC_mst_stop_ack_MASK__CI__VI 0x00000080L -#define SMU_IOC_MSTRCFG__mbus2_mstr_cg_override_MASK__CI__VI 0x40000000L -#define SMU_IOC_MSTRCFG__mbus2_mstr_disable_MASK__CI__VI 0x80000000L -#define SMU_IOC_MSTRCFG__mbus2_mstr_pri_MASK__CI__VI 0x00000001L -#define SMU_IOC_PHASE1__BiuCqfC_AltReqAddrLo_MASK__CI__VI 0xfffffff8L -#define SMU_IOC_PHASE1__BiuCqfC_AltReqRdCmd_MASK__CI__VI 0x00000004L -#define SMU_IOC_PHASE1__BiuCqfC_AwqReqCommit_MASK__CI__VI 0x00000002L -#define SMU_IOC_PHASE2__BiuCqfC_AltReqAddrHi_MASK__CI__VI 0x000000ffL -#define SMU_IOC_PHASE2__BiuCqfC_AltReqMask_MASK__CI__VI 0x0000ff00L -#define SMU_IOC_PHASE3__BiuDbfC_C2aDataOut_MASK__CI__VI 0xffffffffL -#define SMU_IOC_RDDATA__IOC_mst_rdData_MASK__CI__VI 0xffffffffL -#define SMU_KEY_READ_STATUS__HDCP_KEY_RD_STATUS_MASK__CI__VI 0x00000003L -#define SMU_KEY_READ_STATUS__SAMU_KEY_RD_STATUS_MASK__CI__VI 0x00000300L -#define SMU_LCLK_CNTL__LCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define SMU_LCLK_STATUS__LCLK_STATUS_MASK__CI__VI 0x00000001L -#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK__CI__VI 0xffffffffL -#define SMU_MISC_STATUS__SOC_DEBUG_ENABLE_MASK__CI__VI 0x00000002L -#define SMU_PM_MISC__AllCpusInCC6IntCtrl_MASK__CI__VI 0x00030000L -#define SMU_PM_MISC__MemPsIntCtrl_MASK__CI__VI 0x0000c000L -#define SMU_PM_MISC__PM_AllCpusInCC6_MASK__CI__VI 0x00000001L -#define SMU_PM_MISC__PM_CommitSelfRefr_MASK__CI__VI 0x000003fcL -#define SMU_PM_MISC__PM_HtcActive_MASK__CI__VI 0x00001000L -#define SMU_PM_MISC__PM_MemPs_MASK__CI__VI 0x00002000L -#define SMU_PM_MISC__PM_NbPs_MASK__CI__VI 0x00000002L -#define SMU_PM_MISC__PM_PreSelfRefresh_MASK__CI__VI 0x00000400L -#define SMU_PM_MISC__PM_ReqNbPstate_MASK__CI__VI 0x00000800L -#define SMU_PM_MISC__SPARE_MASK__CI__VI 0xfffc0000L -#define SMU_PM_SIGNALS_OVERRIDE__PM_AllCpusInCC6_ovrd_MASK__CI__VI 0x00000001L -#define SMU_PM_SIGNALS_OVERRIDE__RESERVED_MASK__CI__VI 0xfffffffeL -#define SMU_PSTATE_CONTROL__RESERVED_MASK__CI__VI 0xfffffff0L -#define SMU_PSTATE_CONTROL__Smu_Pstate_Limit_En_MASK__CI__VI 0x00000001L -#define SMU_PSTATE_CONTROL__Smu_Pstate_Limit_MASK__CI__VI 0x0000000eL -#define SMU_RST_CTRL__DIST_BIF_STRAP_ON_DRV_RST_MASK__CI__VI 0x40000000L -#define SMU_RST_CTRL__DIST_BIF_STRAP_ON_LINK_RST_MASK__CI__VI 0x80000000L -#define SMU_RST_CTRL__FusesValPwrOk_STATUS_MASK__CI__VI 0x00010000L -#define SMU_RST_CTRL__GCK_early_resetb_MASK__CI__VI 0x00000100L -#define SMU_RST_CTRL__IRESET_STATUS_MASK__CI__VI 0x00020000L -#define SMU_RST_CTRL__SMU_RESET_STATUS_MASK__CI__VI 0x00040000L -#define SMU_RST_CTRL__SMU_RST_SEL_MASK__CI__VI 0x00000001L -#define SMU_RST_OVERRIDE__FusesValPwrOk_OVERRIDE_MASK__CI__VI 0x0000000cL -#define SMU_RST_OVERRIDE__IRESET_OVERRIDE_MASK__CI__VI 0x00000030L -#define SMU_RST_OVERRIDE__SMU_RST_OVERRIDE_MASK__CI__VI 0x00000003L -#define SMU_SCLK_CNTL__SCLK_DIVIDER_MASK__CI__VI 0x0000007fL -#define SMU_SCLK_STATUS__SCLK_STATUS_MASK__CI__VI 0x00000001L -#define SMU_SCRATCH0__SCRATCH_VALUE_MASK__CI__VI 0xffffffffL -#define SMU_SCRATCH_A__SMU_SCRATCH_A_MASK__CI__VI 0xffffffffL -#define SMU_SCRATCH_B__SMU_SCRATCH_B_MASK__CI__VI 0xffffffffL -#define SMU_SCRATCH_C__SMU_SCRATCH_C_MASK__CI__VI 0xffffffffL -#define SMU_SECURE_KEY_0__SMU_SECURE_KEY_0_MASK__CI__VI 0xffffffffL -#define SMU_SECURE_KEY_1__SMU_SECURE_KEY_1_MASK__CI__VI 0xffffffffL -#define SMU_SECURE_KEY_2__SMU_SECURE_KEY_2_MASK__CI__VI 0xffffffffL -#define SMU_SECURE_KEY_3__SMU_SECURE_KEY_3_MASK__CI__VI 0xffffffffL -#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SMU_SRAM_BLOCK_READ_HIGH_ADDR__sram_high_read_addr_MASK__CI__VI 0xffffffffL -#define SMU_SRAM_BLOCK_READ_LOW_ADDR__sram_low_read_addr_MASK__CI__VI 0xffffffffL -#define SMU_SRAM_BLOCK_WRITE_HIGH_ADDR__sram_high_write_addr_MASK__CI__VI 0xffffffffL -#define SMU_SRAM_BLOCK_WRITE_LOW_ADDR__sram_low_write_addr_MASK__CI__VI 0xffffffffL -#define SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK__SI 0x00003fffL -#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000ffffL -#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000L -#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000ffffL -#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK__CI__VI 0xffff0000L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK__CI__VI 0x00000007L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK__CI__VI 0x00000038L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK__CI__VI 0x000001c0L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK__CI__VI 0x00000e00L -#define SPI_ARB_PRIORITY__RING_ORDER_TS0_MASK__SI 0x00000007L -#define SPI_ARB_PRIORITY__RING_ORDER_TS1_MASK__SI 0x00000038L -#define SPI_ARB_PRIORITY__RING_ORDER_TS2_MASK__SI 0x000001c0L -#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK__CI__VI 0x00003000L -#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK__CI__VI 0x0000c000L -#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK__CI__VI 0x00030000L -#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK__CI__VI 0x000c0000L -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L -#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L -#define SPI_CDBG_SYS_CS0__PIPE0_MASK__CI__VI 0x000000ffL -#define SPI_CDBG_SYS_CS0__PIPE1_MASK__CI__VI 0x0000ff00L -#define SPI_CDBG_SYS_CS0__PIPE2_MASK__CI__VI 0x00ff0000L -#define SPI_CDBG_SYS_CS0__PIPE3_MASK__CI__VI 0xff000000L -#define SPI_CDBG_SYS_CS1__PIPE0_MASK__CI__VI 0x000000ffL -#define SPI_CDBG_SYS_CS1__PIPE1_MASK__CI__VI 0x0000ff00L -#define SPI_CDBG_SYS_CS1__PIPE2_MASK__CI__VI 0x00ff0000L -#define SPI_CDBG_SYS_CS1__PIPE3_MASK__CI__VI 0xff000000L -#define SPI_CDBG_SYS_GFX__CS_EN_MASK__CI__VI 0x00000040L -#define SPI_CDBG_SYS_GFX__ES_EN_MASK__CI__VI 0x00000008L -#define SPI_CDBG_SYS_GFX__GS_EN_MASK__CI__VI 0x00000004L -#define SPI_CDBG_SYS_GFX__HS_EN_MASK__CI__VI 0x00000010L -#define SPI_CDBG_SYS_GFX__LS_EN_MASK__CI__VI 0x00000020L -#define SPI_CDBG_SYS_GFX__PS_EN_MASK__CI__VI 0x00000001L -#define SPI_CDBG_SYS_GFX__VS_EN_MASK__CI__VI 0x00000002L -#define SPI_CDBG_SYS_HP3D__ES_EN_MASK__CI__VI 0x00000008L -#define SPI_CDBG_SYS_HP3D__GS_EN_MASK__CI__VI 0x00000004L -#define SPI_CDBG_SYS_HP3D__HS_EN_MASK__CI__VI 0x00000010L -#define SPI_CDBG_SYS_HP3D__LS_EN_MASK__CI__VI 0x00000020L -#define SPI_CDBG_SYS_HP3D__PS_EN_MASK__CI__VI 0x00000001L -#define SPI_CDBG_SYS_HP3D__VS_EN_MASK__CI__VI 0x00000002L -#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK__CI__VI 0x00000001L -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK__CI__VI 0x00003c00L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK__CI__VI 0x00000200L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000fL -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00e00000L -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001fffffL -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK__CI__VI 0x08000000L -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK__CI__VI 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK__CI__VI 0xffffffffL -#define SPI_DEBUG_BUSY__CS0_BUSY_MASK__CI__VI 0x00000100L -#define SPI_DEBUG_BUSY__CS0_BUSY_MASK__SI 0x00000080L -#define SPI_DEBUG_BUSY__CS1_BUSY_MASK__CI__VI 0x00000200L -#define SPI_DEBUG_BUSY__CS1_BUSY_MASK__SI 0x00000100L -#define SPI_DEBUG_BUSY__CS2_BUSY_MASK__CI__VI 0x00000400L -#define SPI_DEBUG_BUSY__CS2_BUSY_MASK__SI 0x00000200L -#define SPI_DEBUG_BUSY__CS3_BUSY_MASK__CI__VI 0x00000800L -#define SPI_DEBUG_BUSY__CS4_BUSY_MASK__CI__VI 0x00001000L -#define SPI_DEBUG_BUSY__CS5_BUSY_MASK__CI__VI 0x00002000L -#define SPI_DEBUG_BUSY__CS6_BUSY_MASK__CI__VI 0x00004000L -#define SPI_DEBUG_BUSY__CS7_BUSY_MASK__CI__VI 0x00008000L -#define SPI_DEBUG_BUSY__CSG_BUSY_MASK__CI__VI 0x00000080L -#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L -#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK__CI__VI 0x00200000L -#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK__SI 0x00008000L -#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK__CI__VI 0x00400000L -#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK__SI 0x00010000L -#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L -#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L -#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK__CI__VI 0x00010000L -#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK__SI 0x00000400L -#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK__CI__VI 0x00020000L -#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK__SI 0x00000800L -#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L -#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK__CI__VI 0x00100000L -#define SPI_DEBUG_BUSY__PC_POSB_BUSY_MASK__SI 0x00004000L -#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L -#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L -#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK__CI__VI 0x00040000L -#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK__SI 0x00001000L -#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK__CI__VI 0x00080000L -#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK__SI 0x00002000L -#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK__CI__VI 0x00800000L -#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK__SI 0x00020000L -#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L -#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x00000001L -#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK__CI__VI 0x000003f0L -#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK__SI 0x000003e0L -#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK__CI__VI 0x0e000000L -#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L -#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L -#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000fc00L -#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK__CI__VI 0x0000000eL -#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK__SI 0x0000001eL -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x00080000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x00200000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x00400000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x00800000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x01000000L -#define SPI_DEBUG_READ__DATA_MASK 0x00ffffffL -#define SPI_DYN_GPR_LOCK_EN__ES_LOW_THRESHOLD_MASK__SI 0x00000f00L -#define SPI_DYN_GPR_LOCK_EN__GS_LOW_THRESHOLD_MASK__SI 0x000000f0L -#define SPI_DYN_GPR_LOCK_EN__HS_LOW_THRESHOLD_MASK__SI 0x0000f000L -#define SPI_DYN_GPR_LOCK_EN__LS_LOW_THRESHOLD_MASK__SI 0x000f0000L -#define SPI_DYN_GPR_LOCK_EN__VS_LOW_THRESHOLD_MASK__SI 0x0000000fL -#define SPI_GDBG_TBA_HI__MEM_BASE_MASK__CI__VI 0x000000ffL -#define SPI_GDBG_TBA_LO__MEM_BASE_MASK__CI__VI 0xffffffffL -#define SPI_GDBG_TMA_HI__MEM_BASE_MASK__CI__VI 0x000000ffL -#define SPI_GDBG_TMA_LO__MEM_BASE_MASK__CI__VI 0xffffffffL -#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK__CI__VI 0x00000080L -#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK__CI__VI 0x00000003L -#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK__CI__VI 0x00000100L -#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK__CI__VI 0x0000000cL -#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK__CI__VI 0x00000200L -#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK__CI__VI 0x00000070L -#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK__CI__VI 0x00008000L -#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK__CI__VI 0xffff0000L -#define SPI_GDBG_TRAP_DATA0__DATA_MASK__CI__VI 0xffffffffL -#define SPI_GDBG_TRAP_DATA1__DATA_MASK__CI__VI 0xffffffffL -#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK__CI__VI 0x000001ffL -#define SPI_GDBG_TRAP_MASK__REPLACE_MASK__CI__VI 0x00000200L -#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK__CI__VI 0x00000001L -#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000ff00L -#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000ffL -#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000L -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001cL -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000e0L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L -#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L -#define SPI_LB_CU_MASK__CU_MASK_MASK 0x0000ffffL -#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffffL -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK__CI__VI 0x000003c0L -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK__CI__VI 0x0000003fL -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK__CI__VI 0x000000ffL -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK__CI__VI 0xffffffffL -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK__CI__VI 0x000000ffL -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK__CI__VI 0xffffffffL -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK__CI__VI 0x000003c0L -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK__CI__VI 0x0000003fL -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK__CI__VI 0x000000ffL -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK__CI__VI 0xffffffffL -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK__CI__VI 0x000000ffL -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK__CI__VI 0xffffffffL -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK__CI__VI 0x000000ffL -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK__CI__VI 0x000000ffL -#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000f0L -#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000fL -#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000f000L -#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000f00L -#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00f00000L -#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000f0000L -#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000L -#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0f000000L -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0x0000ffffL -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_0__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_10__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_11__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_12__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_13__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_14__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_15__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_16__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_17__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_18__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_19__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_1__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_20__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_21__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_22__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_23__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_24__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_25__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_26__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_27__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_28__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_29__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_2__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_30__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_31__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_3__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_4__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_5__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_6__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_7__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_8__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_9__DUP_MASK__CI__VI 0x00040000L -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L -#define SPI_PS_IN_CONTROL__FOG_ADDR_MASK__SI 0x00003f80L -#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL -#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L -#define SPI_PS_IN_CONTROL__PASS_FOG_THROUGH_PS_MASK__SI 0x00008000L -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK__CI__VI 0x00000004L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK__CI__VI 0x00000001L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK__CI__VI 0x00000002L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK__CI__VI 0x00000010L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK__CI__VI 0x00000008L -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK__CI__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK__CI__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK__CI__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK__CI__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK__CI__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_0__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_0__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_0__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_0__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_0__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_1__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_1__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_1__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_1__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_1__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_2__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_2__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_2__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_2__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_2__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_3__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_3__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_3__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_3__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_3__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_4__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_4__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_4__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_4__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_4__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_5__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_5__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_5__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_5__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_5__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_6__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_6__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_6__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_6__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_6__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__EN_A_MASK__SI 0x00008000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__EN_B_MASK__SI 0x80000000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__LDS_A_MASK__SI 0x00001c00L -#define SPI_RESOURCE_RESERVE_CU_AB_7__LDS_B_MASK__SI 0x1c000000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__SGPR_A_MASK__SI 0x00000380L -#define SPI_RESOURCE_RESERVE_CU_AB_7__SGPR_B_MASK__SI 0x03800000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__TYPE_A_MASK__SI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_AB_7__TYPE_B_MASK__SI 0x000f0000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__VGPR_A_MASK__SI 0x00000070L -#define SPI_RESOURCE_RESERVE_CU_AB_7__VGPR_B_MASK__SI 0x00700000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__WAVES_A_MASK__SI 0x00006000L -#define SPI_RESOURCE_RESERVE_CU_AB_7__WAVES_B_MASK__SI 0x60000000L -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK__CI__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK__CI__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK__CI__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK__CI__VI 0x0000fffeL -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000fL -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000f0L -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000f00L -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000f000L -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000f0000L -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00f00000L -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0f000000L -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000L -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK__CI__VI 0x0000003fL -#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK__CI__VI 0x38000000L -#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK__CI__VI 0x40000000L -#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x03000000L -#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK__CI__VI 0x0e000000L -#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK__CI__VI 0x10000000L -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK__CI__VI 0x07000000L -#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK__CI__VI 0x08000000L -#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK__CI__VI 0x1c000000L -#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK__CI__VI 0x20000000L -#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x03000000L -#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK__CI__VI 0x0e000000L -#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK__CI__VI 0x10000000L -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK__CI__VI 0x38000000L -#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK__CI__VI 0x40000000L -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L -#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK__CI__VI 0x0001ff00L -#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK__CI__VI 0x1ff00000L -#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK__CI__VI 0x00000080L -#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK__CI__VI 0x00000001L -#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK__CI__VI 0x00000040L -#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK__CI__VI 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK__CI__VI 0x0001ff00L -#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK__CI__VI 0x1ff00000L -#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK__CI__VI 0x00000080L -#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK__CI__VI 0x00000001L -#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK__CI__VI 0x00000040L -#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK__CI__VI 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK__CI__VI 0x0001ff00L -#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK__SI 0x00007f00L -#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK__CI__VI 0x1ff00000L -#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK__CI__VI 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK__SI 0x00003f80L -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK__CI__VI 0x0003fe00L -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK__SI 0x0000fe00L -#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK__CI__VI 0x01ff0000L -#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK__CI__VI 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK__CI__VI 0x00000001L -#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK__CI__VI 0x00000040L -#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK__CI__VI 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK__CI__VI 0x01ff0000L -#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK__CI__VI 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK__CI__VI 0x00000001L -#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK__CI__VI 0x00000040L -#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK__CI__VI 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK__CI__VI 0x01ff0000L -#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK__CI__VI 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK__CI__VI 0x00000001L -#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK__CI__VI 0x00000040L -#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK__CI__VI 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK__CI__VI 0x01ff0000L -#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK__SI 0x007f0000L -#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK__CI__VI 0x01ff0000L -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK__SI 0x007f0000L -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000ff00L -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK__CI__VI 0x003fe000L -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK__SI 0x000fe000L -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK__CI__VI 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK__CI__VI 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK__CI__VI 0x003f0000L -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK__CI__VI 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK__CI__VI 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK__CI__VI 0x003f0000L -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK__CI__VI 0x000003c0L -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK__CI__VI 0x0000003fL -#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK__CI__VI 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK__CI__VI 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK__CI__VI 0x003f0000L -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK__CI__VI 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK__CI__VI 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK__CI__VI 0x003f0000L -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK__CI__VI 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK__CI__VI 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK__CI__VI 0x003f0000L -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000fL -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000f0L -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000f00L -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000f000L -#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0x000000ffL -#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffffL -#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffffL -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000fL -#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L -#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00200000L -#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L -#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L -#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000200L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000400L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x00000800L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x00001000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x00002000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x00004000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x00008000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x00010000L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000020L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000040L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x00000080L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x00000100L -#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x00000010L -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x00020000L -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x00040000L -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x00080000L -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x00100000L -#define SPI_STATIC_THREAD_MGMT_1__PS_CU_EN_MASK__SI 0x0000ffffL -#define SPI_STATIC_THREAD_MGMT_1__VS_CU_EN_MASK__SI 0xffff0000L -#define SPI_STATIC_THREAD_MGMT_2__ES_CU_EN_MASK__SI 0xffff0000L -#define SPI_STATIC_THREAD_MGMT_2__GS_CU_EN_MASK__SI 0x0000ffffL -#define SPI_STATIC_THREAD_MGMT_3__LSHS_CU_EN_MASK__SI 0x0000ffffL -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000ffffL -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000L -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000ffffL -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000L -#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L -#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000fffL -#define SPI_VS_OUT_CONFIG__VS_EXPORTS_FOG_MASK__SI 0x00000080L -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003eL -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L -#define SPI_VS_OUT_CONFIG__VS_OUT_FOG_VEC_ADDR_MASK__SI 0x00001f00L -#define SPI_WAVE_MGMT_1__NUM_ES_WAVES_MASK__SI 0x00fc0000L -#define SPI_WAVE_MGMT_1__NUM_GS_WAVES_MASK__SI 0x0003f000L -#define SPI_WAVE_MGMT_1__NUM_HS_WAVES_MASK__SI 0x3f000000L -#define SPI_WAVE_MGMT_1__NUM_PS_WAVES_MASK__SI 0x0000003fL -#define SPI_WAVE_MGMT_1__NUM_VS_WAVES_MASK__SI 0x00000fc0L -#define SPI_WAVE_MGMT_2__NUM_LS_WAVES_MASK__SI 0x0000003fL -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK__CI 0x0000001fL -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK__CI 0x0000001fL -#define SPI_WF_LIFETIME_CNTL__EN_MASK__CI__VI 0x00000010L -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK__CI__VI 0x0000000fL -#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK__CI__VI 0x80000000L -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK__CI__VI 0x7fffffffL -#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0x000ff000L -#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L -#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x00000008L -#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x00000002L -#define SPLL_CNTL_MODE__SPLL_REFCLK_SEL_MASK__SI 0x0c000000L -#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000L -#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L -#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0x00000c00L -#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x00000004L -#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000L -#define SPLL_TIME__SPLL_LOCK_TIME_MASK 0x0000ffffL -#define SPLL_TIME__SPLL_RESET_TIME_MASK 0xffff0000L -#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_MASK__CI__VI 0x00000001L -#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK__CI__VI 0x00000002L -#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6_MASK__CI 0x0001fffcL -#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_MASK__CI 0x00000001L -#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK__CI 0x00000002L -#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6_MASK__CI 0x0001fffcL -#define SPMI_CONFIG_0_0__SPMI_ENABLE_MASK__CI 0x00000001L -#define SPMI_CONFIG_0_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK__CI 0x07c00000L -#define SPMI_CONFIG_0_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK__CI 0x003e0000L -#define SPMI_CONFIG_0_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK__CI 0x0000007cL -#define SPMI_CONFIG_0_0__SPMI_SIGNALING_DELAY_CYCLES_MASK__CI 0x00000f80L -#define SPMI_CONFIG_0_0__SPMI_SIGNALING_HOLD_CYCLES_MASK__CI 0x0001f000L -#define SPMI_CONFIG_0_1__SPMI_CHAIN_SIZE_MASK__CI 0x0000ffe0L -#define SPMI_CONFIG_0_1__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK__CI 0x0000001fL -#define SPMI_CONFIG_1_0__SPMI_ENABLE_MASK__CI 0x00000001L -#define SPMI_CONFIG_1_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK__CI 0x07c00000L -#define SPMI_CONFIG_1_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK__CI 0x003e0000L -#define SPMI_CONFIG_1_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK__CI 0x0000007cL -#define SPMI_CONFIG_1_0__SPMI_SIGNALING_DELAY_CYCLES_MASK__CI 0x00000f80L -#define SPMI_CONFIG_1_0__SPMI_SIGNALING_HOLD_CYCLES_MASK__CI 0x0001f000L -#define SPMI_CONFIG_1_1__SPMI_CHAIN_SIZE_MASK__CI 0x0000ffe0L -#define SPMI_CONFIG_1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK__CI 0x0000001fL -#define SPMI_FSM_BUSY_0__FSM_BUSY_MASK__CI__VI 0x00000001L -#define SPMI_FSM_BUSY_1__FSM_BUSY_MASK__CI 0x00000001L -#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER_MASK__CI__VI 0x00000001L -#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER_MASK__CI 0x00000001L -#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER_MASK__CI__VI 0x00000001L -#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER_MASK__CI 0x00000001L -#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER_MASK__CI__VI 0x00000001L -#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER_MASK__CI 0x00000001L -#define SPMI_IND_ADDR__SPMI_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SPMI_IND_DATA__SPMI_IND_DATA_MASK__CI__VI 0xffffffffL -#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED_MASK__CI__VI 0x00000001L -#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED_MASK__CI 0x00000001L -#define SPMI_PATH_0__PATH_ENABLE_ACK_MASK__CI__VI 0x00000002L -#define SPMI_PATH_0__PATH_ENABLE_REQ_MASK__CI__VI 0x00000001L -#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear_MASK__CI__VI 0x00000010L -#define SPMI_PATH_1__PATH_ENABLE_ACK_MASK__CI 0x00000002L -#define SPMI_PATH_1__PATH_ENABLE_REQ_MASK__CI 0x00000001L -#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear_MASK__CI 0x00000010L -#define SPMI_RESET__ASYNC_RESET_0_MASK__CI__VI 0x00000001L -#define SPMI_RESET__ASYNC_RESET_1_MASK__CI 0x00000002L -#define SPMI_RESET__SYNC_RESET_MASK__CI 0x00000004L -#define SPMI_SMC_IND_DATA__SMC_IND_DATA_MASK__CI__VI 0xffffffffL -#define SPMI_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI__VI 0xffffffffL -#define SPMI_SRAM_ADDRESS__SRAM_ADDRESS_MASK__CI__VI 0xffffffffL -#define SPMI_SRAM_DATA__SRAM_DATA_MASK__CI__VI 0xffffffffL -#define SPMI_TIMER__PERIOD_MASK__CI 0xffffffffL -#define SQC_CACHES__DATA_INVALIDATE_MASK__SI__CI 0x00000002L -#define SQC_CACHES__INST_INVALIDATE_MASK__SI__CI 0x00000001L -#define SQC_CACHES__INVALIDATE_VOLATILE_MASK__CI 0x00000004L -#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000cL -#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L -#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L -#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L -#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L -#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L -#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L -#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L -#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK__CI__VI 0x00000800L -#define SQC_POLICY__DATA_L1_POLICY_0_MASK__CI 0x00000001L -#define SQC_POLICY__DATA_L1_POLICY_1_MASK__CI 0x00000002L -#define SQC_POLICY__DATA_L1_POLICY_2_MASK__CI 0x00000004L -#define SQC_POLICY__DATA_L1_POLICY_3_MASK__CI 0x00000008L -#define SQC_POLICY__DATA_L1_POLICY_4_MASK__CI 0x00000010L -#define SQC_POLICY__DATA_L1_POLICY_5_MASK__CI 0x00000020L -#define SQC_POLICY__DATA_L1_POLICY_6_MASK__CI 0x00000040L -#define SQC_POLICY__DATA_L1_POLICY_7_MASK__CI 0x00000080L -#define SQC_POLICY__DATA_L2_POLICY_0_MASK__CI 0x00000300L -#define SQC_POLICY__DATA_L2_POLICY_1_MASK__CI 0x00000c00L -#define SQC_POLICY__DATA_L2_POLICY_2_MASK__CI 0x00003000L -#define SQC_POLICY__DATA_L2_POLICY_3_MASK__CI 0x0000c000L -#define SQC_POLICY__DATA_L2_POLICY_4_MASK__CI 0x00030000L -#define SQC_POLICY__DATA_L2_POLICY_5_MASK__CI 0x000c0000L -#define SQC_POLICY__DATA_L2_POLICY_6_MASK__CI 0x00300000L -#define SQC_POLICY__DATA_L2_POLICY_7_MASK__CI 0x00c00000L -#define SQC_POLICY__INST_L2_POLICY_MASK__CI 0x03000000L -#define SQC_SECDED_CNT__DATA_DED_MASK__SI__CI 0xff000000L -#define SQC_SECDED_CNT__DATA_SEC_MASK__SI__CI 0x00ff0000L -#define SQC_SECDED_CNT__INST_DED_MASK__SI__CI 0x0000ff00L -#define SQC_SECDED_CNT__INST_SEC_MASK__SI__CI 0x000000ffL -#define SQC_VOLATILE__DATA_L1_MASK__CI 0x0000000fL -#define SQC_VOLATILE__DATA_L2_MASK__CI 0x000000f0L -#define SQC_VOLATILE__INST_L2_MASK__CI 0x00000100L -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000ffffL -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L -#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000L -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffffL -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L -#define SQ_BUF_RSRC_WORD3__ATC_MASK__CI__VI 0x01000000L -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L -#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L -#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L -#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x00180000L -#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x02000000L -#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x04000000L -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L -#define SQ_BUF_RSRC_WORD3__MTYPE_MASK__CI__VI 0x38000000L -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L -#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000L -#define SQ_CAC_MASK__GPR_MASK__SI 0x00000004L -#define SQ_CAC_MASK__VALU_MASK__SI 0x00000001L -#define SQ_CAC_MASK__VALU_MUL_MASK__SI 0x00000002L -#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK__CI__VI 0x000000ffL -#define SQ_CMD__CHECK_VMID_MASK__CI__VI 0x00000080L -#define SQ_CMD__CMD_MASK__CI__VI 0x00000007L -#define SQ_CMD__MODE_MASK__CI__VI 0x00000070L -#define SQ_CMD__QUEUE_ID_MASK__CI__VI 0x07000000L -#define SQ_CMD__SIMD_ID_MASK__CI__VI 0x00300000L -#define SQ_CMD__TRAP_ID_MASK__CI 0x00000700L -#define SQ_CMD__VM_ID_MASK__CI__VI 0xf0000000L -#define SQ_CMD__WAVE_ID_MASK__CI__VI 0x000f0000L -#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L -#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK__SI__CI 0x00000400L -#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK__SI__CI 0x00000200L -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK__CI__VI 0x00008000L -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK__CI__VI 0x00002000L -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK__CI__VI 0x00004000L -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK__CI__VI 0x00001000L -#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK__CI 0x00000800L -#define SQ_CONFIG__UNUSED_MASK 0x000000ffL -#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000ffL -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK__CI__VI 0x000000ffL -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK__CI__VI 0x0000ff00L -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK__CI__VI 0xff000000L -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK__CI__VI 0x00ff0000L -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK__CI__VI 0x0000000fL -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK__CI 0x000000f0L -#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L -#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK__CI__VI 0x00000002L -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L -#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L -#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L -#define SQ_DED_CNT__LDS_DED_MASK__SI__CI 0x0000003fL -#define SQ_DED_CNT__SGPR_DED_MASK__SI__CI 0x00001f00L -#define SQ_DED_CNT__VGPR_DED_MASK__SI__CI 0x01ff0000L -#define SQ_DED_INFO__RING_ID_MASK__SI 0x0000e000L -#define SQ_DED_INFO__SIMD_ID_MASK__SI__CI 0x00000030L -#define SQ_DED_INFO__SOURCE_MASK__SI__CI 0x000001c0L -#define SQ_DED_INFO__VM_ID_MASK__SI__CI 0x00001e00L -#define SQ_DED_INFO__WAVE_ID_MASK__SI__CI 0x0000000fL -#define SQ_DS_0__ENCODING_MASK 0xfc000000L -#define SQ_DS_0__OFFSET0_MASK 0x000000ffL -#define SQ_DS_0__OFFSET1_MASK 0x0000ff00L -#define SQ_DS_1__ADDR_MASK 0x000000ffL -#define SQ_DS_1__DATA0_MASK 0x0000ff00L -#define SQ_DS_1__DATA1_MASK 0x00ff0000L -#define SQ_DS_1__VDST_MASK 0xff000000L -#define SQ_EXP_0__COMPR_MASK 0x00000400L -#define SQ_EXP_0__DONE_MASK 0x00000800L -#define SQ_EXP_0__ENCODING_MASK 0xfc000000L -#define SQ_EXP_0__EN_MASK 0x0000000fL -#define SQ_EXP_0__TGT_MASK 0x000003f0L -#define SQ_EXP_0__VM_MASK 0x00001000L -#define SQ_EXP_1__VSRC0_MASK 0x000000ffL -#define SQ_EXP_1__VSRC1_MASK 0x0000ff00L -#define SQ_EXP_1__VSRC2_MASK 0x00ff0000L -#define SQ_EXP_1__VSRC3_MASK 0xff000000L -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000fL -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000f00L -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000c0000L -#define SQ_FLAT_0__ENCODING_MASK__CI__VI 0xfc000000L -#define SQ_FLAT_0__GLC_MASK__CI__VI 0x00010000L -#define SQ_FLAT_0__OP_MASK__CI__VI 0x01fc0000L -#define SQ_FLAT_0__SLC_MASK__CI__VI 0x00020000L -#define SQ_FLAT_1__ADDR_MASK__CI__VI 0x000000ffL -#define SQ_FLAT_1__DATA_MASK__CI__VI 0x0000ff00L -#define SQ_FLAT_1__TFE_MASK__CI__VI 0x00800000L -#define SQ_FLAT_1__VDST_MASK__CI__VI 0xff000000L -#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK__CI__VI 0x0007ffffL -#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK__CI__VI 0x00ffffffL -#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK__CI__VI 0x000ffff0L -#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK__CI__VI 0x0000000fL -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000ffL -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03f00000L -#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000fff00L -#define SQ_IMG_RSRC_WORD1__MTYPE_MASK__CI__VI 0xc0000000L -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000L -#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0fffc000L -#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000L -#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L -#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003fffL -#define SQ_IMG_RSRC_WORD3__ATC_MASK__CI__VI 0x08000000L -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000f000L -#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L -#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000f0000L -#define SQ_IMG_RSRC_WORD3__MTYPE_MASK__CI__VI 0x04000000L -#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x02000000L -#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x01f00000L -#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000L -#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001fffL -#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x07ffe000L -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001fffL -#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x03ffe000L -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK__CI__VI 0x000ff000L -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK__CI__VI 0x00100000L -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000fffL -#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK__CI 0xffe00000L -#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK__SI__CI 0xffffffffL -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07e00000L -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L -#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L -#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L -#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001c0L -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000e00L -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L -#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00fff000L -#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000fffL -#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0f000000L -#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000L -#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000L -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003fffL -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000fc000L -#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0c000000L -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00c00000L -#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000fffL -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000L -#define SQ_IND_CMD__CMD_MASK__SI 0x00000007L -#define SQ_IND_CMD__MODE_MASK__SI 0x00000030L -#define SQ_IND_CMD__TRAP_ID_MASK__SI 0x00000700L -#define SQ_IND_CMD__VM_ID_MASK__SI 0xf0000000L -#define SQ_IND_DATA__DATA_MASK 0xffffffffL -#define SQ_IND_INDEX__AUTO_INCR_MASK__CI__VI 0x00001000L -#define SQ_IND_INDEX__FORCE_READ_MASK__CI__VI 0x00002000L -#define SQ_IND_INDEX__INDEX_MASK 0xffff0000L -#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L -#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L -#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000fc0L -#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L -#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000fL -#define SQ_INST__ENCODING_MASK 0xffffffffL -#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK__CI__VI 0x00ffffffL -#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK__CI__VI 0x00000001L -#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK__CI__VI 0x00000010L -#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0x0c000000L -#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK__CI__VI 0x00000020L -#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK__CI__VI 0x00000040L -#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK__CI__VI 0x00000080L -#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK__CI__VI 0x00000008L -#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK__CI__VI 0x03000000L -#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK__SI 0x02000000L -#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK__CI__VI 0x00000004L -#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x00000001L -#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK__CI__VI 0x00000002L -#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0x0c000000L -#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK__CI__VI 0x03000000L -#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK__SI 0x02000000L -#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0x00f00000L -#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x000000ffL -#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0x0c000000L -#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK__CI__VI 0x00000200L -#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK__CI__VI 0x03000000L -#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK__SI 0x02000000L -#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK__CI__VI 0x00000100L -#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK__SI 0x01000000L -#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x000c0000L -#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x00003c00L -#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x0003c000L -#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L -#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L -#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L -#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffffL -#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffffL -#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffffL -#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffffL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK__CI__VI 0x0000ffffL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK__CI__VI 0xffff0000L -#define SQ_MIMG_0__DA_MASK 0x00004000L -#define SQ_MIMG_0__DMASK_MASK 0x00000f00L -#define SQ_MIMG_0__ENCODING_MASK 0xfc000000L -#define SQ_MIMG_0__GLC_MASK 0x00002000L -#define SQ_MIMG_0__LWE_MASK 0x00020000L -#define SQ_MIMG_0__OP_MASK 0x01fc0000L -#define SQ_MIMG_0__R128_MASK 0x00008000L -#define SQ_MIMG_0__SLC_MASK 0x02000000L -#define SQ_MIMG_0__TFE_MASK 0x00010000L -#define SQ_MIMG_0__UNORM_MASK 0x00001000L -#define SQ_MIMG_1__SRSRC_MASK 0x001f0000L -#define SQ_MIMG_1__SSAMP_MASK 0x03e00000L -#define SQ_MIMG_1__VADDR_MASK 0x000000ffL -#define SQ_MIMG_1__VDATA_MASK 0x0000ff00L -#define SQ_MTBUF_0__ADDR64_MASK__SI__CI 0x00008000L -#define SQ_MTBUF_0__DFMT_MASK 0x00780000L -#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000L -#define SQ_MTBUF_0__GLC_MASK 0x00004000L -#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MTBUF_0__NFMT_MASK 0x03800000L -#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MTBUF_0__OFFSET_MASK 0x00000fffL -#define SQ_MTBUF_1__SLC_MASK 0x00400000L -#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000L -#define SQ_MTBUF_1__SRSRC_MASK 0x001f0000L -#define SQ_MTBUF_1__TFE_MASK 0x00800000L -#define SQ_MTBUF_1__VADDR_MASK 0x000000ffL -#define SQ_MTBUF_1__VDATA_MASK 0x0000ff00L -#define SQ_MUBUF_0__ADDR64_MASK__SI__CI 0x00008000L -#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000L -#define SQ_MUBUF_0__GLC_MASK 0x00004000L -#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MUBUF_0__LDS_MASK 0x00010000L -#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MUBUF_0__OFFSET_MASK 0x00000fffL -#define SQ_MUBUF_0__OP_MASK 0x01fc0000L -#define SQ_MUBUF_1__SLC_MASK__SI__CI 0x00400000L -#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000L -#define SQ_MUBUF_1__SRSRC_MASK 0x001f0000L -#define SQ_MUBUF_1__TFE_MASK 0x00800000L -#define SQ_MUBUF_1__VADDR_MASK 0x000000ffL -#define SQ_MUBUF_1__VDATA_MASK 0x0000ff00L -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000L -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK__CI 0x000000ffL -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK__SI__VI 0x000001ffL -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK__CI__VI 0x00f00000L -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK__CI__VI 0x0000f000L -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000L -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK__CI__VI 0x00000001L -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001f00L -#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L -#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L -#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L -#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L -#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L -#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L -#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L -#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK__CI__VI 0x0000ffffL -#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK__CI__VI 0xffff0000L -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003fffL -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L -#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000L -#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003fffL -#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000L -#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007fL -#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x001ffc00L -#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L -#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000f00L -#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK__CI__VI 0x80000000L -#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK__CI__VI 0x40000000L -#define SQ_REG_CREDITS__REG_BUSY_MASK__CI__VI 0x10000000L -#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003fL -#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK__CI__VI 0x20000000L -#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK__CI__VI 0x000000ffL -#define SQ_SEC_CNT__LDS_SEC_MASK__SI__CI 0x0000003fL -#define SQ_SEC_CNT__SGPR_SEC_MASK__SI__CI 0x00001f00L -#define SQ_SEC_CNT__VGPR_SEC_MASK__SI__CI 0x01ff0000L -#define SQ_SMRD__ENCODING_MASK__SI__CI 0xf8000000L -#define SQ_SMRD__IMM_MASK__SI__CI 0x00000100L -#define SQ_SMRD__OFFSET_MASK__SI__CI 0x000000ffL -#define SQ_SMRD__OP_MASK__SI__CI 0x07c00000L -#define SQ_SMRD__SBASE_MASK__SI__CI 0x00007e00L -#define SQ_SMRD__SDST_MASK__SI__CI 0x003f8000L -#define SQ_SOP1__ENCODING_MASK 0xff800000L -#define SQ_SOP1__OP_MASK 0x0000ff00L -#define SQ_SOP1__SDST_MASK 0x007f0000L -#define SQ_SOP1__SSRC0_MASK 0x000000ffL -#define SQ_SOP2__ENCODING_MASK 0xc0000000L -#define SQ_SOP2__OP_MASK 0x3f800000L -#define SQ_SOP2__SDST_MASK 0x007f0000L -#define SQ_SOP2__SSRC0_MASK 0x000000ffL -#define SQ_SOP2__SSRC1_MASK 0x0000ff00L -#define SQ_SOPC__ENCODING_MASK 0xff800000L -#define SQ_SOPC__OP_MASK 0x007f0000L -#define SQ_SOPC__SSRC0_MASK 0x000000ffL -#define SQ_SOPC__SSRC1_MASK 0x0000ff00L -#define SQ_SOPK__ENCODING_MASK 0xf0000000L -#define SQ_SOPK__OP_MASK 0x0f800000L -#define SQ_SOPK__SDST_MASK 0x007f0000L -#define SQ_SOPK__SIMM16_MASK 0x0000ffffL -#define SQ_SOPP__ENCODING_MASK 0xff800000L -#define SQ_SOPP__OP_MASK 0x007f0000L -#define SQ_SOPP__SIMM16_MASK 0x0000ffffL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L -#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK__CI__VI 0x0000000fL -#define SQ_THREAD_TRACE_BASE2__ATC_MASK__CI 0x00000010L -#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffffL -#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffffL -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L -#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L -#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001fL -#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK__SI__CI 0xffff0000L -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK__CI__VI 0x00000080L -#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L -#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000f00L -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK__CI__VI 0x00004000L -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK__CI__VI 0x00008000L -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L -#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001c0000L -#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000e00L -#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001c0L -#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L -#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L -#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L -#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L -#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L -#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x04000000L -#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L -#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000ffffL -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000L -#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003fffffL -#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK__CI__VI 0x03ff0000L -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK__SI 0x00070000L -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK__CI__VI 0x000003ffL -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK__SI 0x00000007L -#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L -#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK__CI 0x0000ffffL -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK__CI__VI 0x01000000L -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00ff0000L -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000ffffL -#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffffL -#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffffL -#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffffL -#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffffL -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0x0000fc00L -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x000001c0L -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001e0L -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00ffffffL -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000c000L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003c00L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0x0000ffffL -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x00000600L -#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK__SI__CI 0x00000800L -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x000001e0L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000c00L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000c000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000c0000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00c00000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0c000000L -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK__CI__VI 0x0000e000L -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK__SI 0x000000c0L -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK__CI__VI 0x00001000L -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK__SI 0x00000020L -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK__CI__VI 0x00000ff0L -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK__SI 0x00000010L -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01fff000L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000c00L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003fL -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007ffc0L -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__DISPATCHER_MASK__SI 0x000003e0L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK__CI__VI 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK__CI__VI 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK__CI__VI 0x00000200L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001c00L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffffL -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK__CI__VI 0xffff0000L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK__CI__VI 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK__CI__VI 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK__CI__VI 0x0000fe00L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK__CI__VI 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK__CI__VI 0x0000000fL -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK__CI__VI 0x0000ffffL -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000L -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffffL -#define SQ_THREAD_TRACE_WORD_TIME__PACKET_LOST_MASK__SI 0x00008000L -#define SQ_THREAD_TRACE_WORD_TIME__TIME_DELTA_MASK__SI 0x00003ff0L -#define SQ_THREAD_TRACE_WORD_TIME__TIME_RESET_MASK__SI 0x00004000L -#define SQ_THREAD_TRACE_WORD_TIME__TOKEN_TYPE_MASK__SI 0x0000000fL -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001f0000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000c000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003c00L -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0x0000c000L -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x00003c00L -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000L -#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffffL -#define SQ_TIME_HI__TIME_MASK 0xffffffffL -#define SQ_TIME_LO__TIME_MASK 0xffffffffL -#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L -#define SQ_VINTRP__ATTR_MASK 0x0000fc00L -#define SQ_VINTRP__ENCODING_MASK 0xfc000000L -#define SQ_VINTRP__OP_MASK 0x00030000L -#define SQ_VINTRP__VDST_MASK 0x03fc0000L -#define SQ_VINTRP__VSRC_MASK 0x000000ffL -#define SQ_VOP1__ENCODING_MASK 0xfe000000L -#define SQ_VOP1__OP_MASK 0x0001fe00L -#define SQ_VOP1__SRC0_MASK 0x000001ffL -#define SQ_VOP1__VDST_MASK 0x01fe0000L -#define SQ_VOP2__ENCODING_MASK 0x80000000L -#define SQ_VOP2__OP_MASK 0x7e000000L -#define SQ_VOP2__SRC0_MASK 0x000001ffL -#define SQ_VOP2__VDST_MASK 0x01fe0000L -#define SQ_VOP2__VSRC1_MASK 0x0001fe00L -#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000L -#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007f00L -#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000ffL -#define SQ_VOP3_0__ABS_MASK 0x00000700L -#define SQ_VOP3_0__ENCODING_MASK 0xfc000000L -#define SQ_VOP3_0__VDST_MASK 0x000000ffL -#define SQ_VOP3_1__NEG_MASK 0xe0000000L -#define SQ_VOP3_1__OMOD_MASK 0x18000000L -#define SQ_VOP3_1__SRC0_MASK 0x000001ffL -#define SQ_VOP3_1__SRC1_MASK 0x0003fe00L -#define SQ_VOP3_1__SRC2_MASK 0x07fc0000L -#define SQ_VOPC__ENCODING_MASK 0xfe000000L -#define SQ_VOPC__OP_MASK 0x01fe0000L -#define SQ_VOPC__SRC0_MASK 0x000001ffL -#define SQ_VOPC__VSRC1_MASK 0x0001fe00L -#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffffL -#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffffL -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003f0000L -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0f000000L -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003fL -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003f00L -#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000f00L -#define SQ_WAVE_HW_ID__ME_ID_MASK__CI__VI 0xc0000000L -#define SQ_WAVE_HW_ID__PIPE_ID_MASK__CI__VI 0x000000c0L -#define SQ_WAVE_HW_ID__QUEUE_ID_MASK__CI__VI 0x07000000L -#define SQ_WAVE_HW_ID__RING_ID_MASK__SI 0x07000000L -#define SQ_WAVE_HW_ID__SE_ID_MASK__CI__VI 0x00006000L -#define SQ_WAVE_HW_ID__SE_ID_MASK__SI 0x00002000L -#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L -#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L -#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L -#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000f0000L -#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00f00000L -#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000fL -#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L -#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L -#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000c00L -#define SQ_WAVE_IB_DBG0__KILL_MASK__CI 0x08000000L -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK__CI 0x10000000L -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000e0L -#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L -#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L -#define SQ_WAVE_IB_STS__LGKM_CNT_MASK__CI__VI 0x00000f00L -#define SQ_WAVE_IB_STS__LGKM_CNT_MASK__SI 0x00001f00L -#define SQ_WAVE_IB_STS__VALU_CNT_MASK__CI__VI 0x00007000L -#define SQ_WAVE_IB_STS__VALU_CNT_MASK__SI 0x0000e000L -#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000fL -#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffffL -#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffffL -#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000ffL -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001ff000L -#define SQ_WAVE_M0__M0_MASK 0xffffffffL -#define SQ_WAVE_MODE__CSP_MASK 0xe0000000L -#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L -#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L -#define SQ_WAVE_MODE__EXCP_EN_MASK__CI__VI 0x001ff000L -#define SQ_WAVE_MODE__EXCP_EN_MASK__SI 0x0007f000L -#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000f0L -#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000fL -#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L -#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L -#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L -#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffffL -#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK__CI__VI 0x00200000L -#define SQ_WAVE_STATUS__COND_DBG_USER_MASK__CI__VI 0x00100000L -#define SQ_WAVE_STATUS__DATA_ATC_MASK__CI 0x00400000L -#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK__CI 0x07000000L -#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L -#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L -#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L -#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L -#define SQ_WAVE_STATUS__INST_ATC_MASK__CI__VI 0x00800000L -#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L -#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L -#define SQ_WAVE_STATUS__MUST_EXPORT_MASK__CI__VI 0x08000000L -#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L -#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L -#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L -#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L -#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L -#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L -#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L -#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L -#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L -#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L -#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L -#define SQ_WAVE_STATUS__WAVE_PRIO_MASK__SI__CI 0x00000018L -#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0x000000ffL -#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffffL -#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0x000000ffL -#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffffL -#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000L -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003f0000L -#define SQ_WAVE_TRAPSTS__EXCP_MASK__CI__VI 0x000001ffL -#define SQ_WAVE_TRAPSTS__EXCP_MASK__SI 0x0000007fL -#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffffL -#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffffL -#define SRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL -#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L -#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL -#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK__CI__VI 0x00020000L -#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x00010000L -#define SRBM_CNTL__READ_TIMEOUT_MASK__SI__CI 0x000003ffL -#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x0000003fL -#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffffL -#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK__CI__VI 0x00000010L -#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x00000080L -#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x00000040L -#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x00000020L -#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x00000001L -#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000L -#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x08000000L -#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x04000000L -#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x02000000L -#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x01000000L -#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x00800000L -#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x00400000L -#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x00200000L -#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x00100000L -#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x00080000L -#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x00040000L -#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x00020000L -#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x00010000L -#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x00008000L -#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x00004000L -#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x00002000L -#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK__SI__CI 0x00001000L -#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x00000800L -#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK__CI 0x00000002L -#define SRBM_DEBUG_SNAPSHOT__SAM_RDY_MASK__CI 0x00000008L -#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK__CI__VI 0x00000004L -#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x00000200L -#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK__SI__CI 0x20000000L -#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x00000100L -#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK__SI__CI 0x00000400L -#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000002L -#define SRBM_DEBUG__DRMDMA_CLOCK_DOMAIN_OVERRIDE_MASK__SI 0x00000080L -#define SRBM_DEBUG__IGNORE_RDY_MASK 0x00000001L -#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK__CI__VI 0x00000100L -#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK__CI__VI 0x00000200L -#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK__CI__VI 0x00000080L -#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000004L -#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000010L -#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000040L -#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000020L -#define SRBM_DRMDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK__SI 0x00001f00L -#define SRBM_DRMDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK__SI 0x0000000fL -#define SRBM_GFX_CNTL__MEID_MASK__CI__VI 0x0000000cL -#define SRBM_GFX_CNTL__PIPEID_MASK__CI__VI 0x00000003L -#define SRBM_GFX_CNTL__QUEUEID_MASK__CI__VI 0x00000700L -#define SRBM_GFX_CNTL__RINGID_MASK__SI 0x00000003L -#define SRBM_GFX_CNTL__VMID_MASK 0x000000f0L -#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L -#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L -#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L -#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK__CI__VI 0x00001f00L -#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK__CI__VI 0x0000000fL -#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffffL -#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffffL -#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL -#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffffL -#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL -#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL -#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L -#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L -#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL -#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL -#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L -#define SRBM_READ_ERROR__READ_REQUESTER_ACP_MASK__CI 0x08000000L -#define SRBM_READ_ERROR__READ_REQUESTER_DRMDMA1_MASK__SI 0x00200000L -#define SRBM_READ_ERROR__READ_REQUESTER_DRMDMA_MASK__SI 0x10000000L -#define SRBM_READ_ERROR__READ_REQUESTER_DRM_MASK 0x40000000L -#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x02000000L -#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x01000000L -#define SRBM_READ_ERROR__READ_REQUESTER_SAM_MASK__CI 0x00800000L -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK__CI__VI 0x00200000L -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK__CI__VI 0x10000000L -#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x04000000L -#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x00400000L -#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000L -#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK__SI__CI 0x00100000L -#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK__CI__VI 0x00001f00L -#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK__CI__VI 0x0000000fL -#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK__CI__VI 0x00001f00L -#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK__CI__VI 0x0000000fL -#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK__CI__VI 0x04000000L -#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x00000002L -#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK__CI__VI 0x00001000L -#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x00000020L -#define SRBM_SOFT_RESET__SOFT_RESET_DRMDMA1_MASK__SI 0x00000040L -#define SRBM_SOFT_RESET__SOFT_RESET_DRMDMA_MASK__SI 0x00100000L -#define SRBM_SOFT_RESET__SOFT_RESET_DRM_MASK 0x00000080L -#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x00000100L -#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x00000200L -#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L -#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x00000800L -#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK__SI__CI 0x00800000L -#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x00400000L -#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x00004000L -#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK__CI 0x00000010L -#define SRBM_SOFT_RESET__SOFT_RESET_SAM_MASK__CI 0x08000000L -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK__CI__VI 0x00000040L -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK__CI__VI 0x00100000L -#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x00008000L -#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK__CI__VI 0x00010000L -#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x00200000L -#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x00040000L -#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK__SI__CI 0x01000000L -#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x00020000L -#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x02000000L -#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK__SI__CI 0x00080000L -#define SRBM_STATUS2__CHUB_BUSY_MASK__CI__VI 0x00000200L -#define SRBM_STATUS2__DRMDMA1_BUSY_MASK__SI 0x00000040L -#define SRBM_STATUS2__DRMDMA1_RQ_PENDING_MASK__SI 0x00000004L -#define SRBM_STATUS2__DRMDMA_BUSY_MASK__SI 0x00000020L -#define SRBM_STATUS2__DRMDMA_RQ_PENDING_MASK__SI 0x00000001L -#define SRBM_STATUS2__SDMA1_BUSY_MASK__CI__VI 0x00000040L -#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK__CI__VI 0x00000004L -#define SRBM_STATUS2__SDMA_BUSY_MASK__CI__VI 0x00000020L -#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK__CI__VI 0x00000001L -#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x00000002L -#define SRBM_STATUS2__VCE_BUSY_MASK__SI__CI 0x00000080L -#define SRBM_STATUS2__VCE_RQ_PENDING_MASK__SI__CI 0x00000008L -#define SRBM_STATUS2__XDMA_BUSY_MASK 0x00000100L -#define SRBM_STATUS2__XSP_BUSY_MASK__SI__CI 0x00000010L -#define SRBM_STATUS__ACP_BUSY_MASK__CI__VI 0x00010000L -#define SRBM_STATUS__ACP_RQ_PENDING_MASK__CI__VI 0x00000008L -#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000L -#define SRBM_STATUS__DRM_BUSY_MASK 0x00040000L -#define SRBM_STATUS__DRM_RQ_PENDING_MASK 0x00000001L -#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x00000020L -#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x00000040L -#define SRBM_STATUS__IH_BUSY_MASK 0x00020000L -#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK__SI__CI 0x00000080L -#define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L -#define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L -#define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L -#define SRBM_STATUS__SAM_BUSY_MASK__CI 0x00100000L -#define SRBM_STATUS__SAM_RQ_PENDING_MASK__CI 0x00000004L -#define SRBM_STATUS__SEM_BUSY_MASK 0x00004000L -#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x00000010L -#define SRBM_STATUS__UVD_BUSY_MASK 0x00080000L -#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x00000002L -#define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L -#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L -#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL -#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L -#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL -#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L -#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL -#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK__SI 0x00000001L -#define STATUS__CAP_LIST_MASK 0x00000010L -#define STATUS__DEVSEL_TIMING_MASK 0x00000600L -#define STATUS__FAST_BACK_CAPABLE_MASK 0x00000080L -#define STATUS__INT_STATUS_MASK 0x00000008L -#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x00000100L -#define STATUS__PARITY_ERROR_DETECTED_MASK 0x00008000L -#define STATUS__PCI_66_EN_MASK 0x00000020L -#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x00002000L -#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x00001000L -#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x00004000L -#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x00000800L -#define STATUS__UDF_EN_MASK__SI__CI 0x00000040L -#define STREAM_SYNCHRONIZATION__STREAM_SYNCHRONIZATION_MASK__SI 0x00000001L -#define STUTTER_A_CNT__STUTTER_OFF_MARK_A_MASK__SI 0x7fff0000L -#define STUTTER_A_CNT__STUTTER_ON_MARK_A_MASK__SI 0x00007fffL -#define STUTTER_B_CNT__STUTTER_OFF_MARK_B_MASK__SI 0x7fff0000L -#define STUTTER_B_CNT__STUTTER_ON_MARK_B_MASK__SI 0x00007fffL -#define SUB_CLASS__SUB_CLASS_MASK 0x000000ffL -#define SVI2_NB_STATUS__Nb_Curr_Tel_MASK__CI__VI 0x000000ffL -#define SVI2_NB_STATUS__Nb_Volt_Tel_MASK__CI__VI 0x01ff0000L -#define SVI2_NB_STATUS__RESERVED_1_MASK__CI__VI 0x0000ff00L -#define SVI2_NB_STATUS__RESERVED_MASK__CI__VI 0xfe000000L -#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x000001c0L -#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x0000003fL -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x0c000000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x03ff0000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x0000f000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00000e00L -#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00300000L -#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x0000007fL -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000L -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0x0f000000L -#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0x000f0000L -#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L -#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x00007c00L -#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00000380L -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x00800000L -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x00400000L -#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x0000007fL -#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x007f0000L -#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x00008000L -#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000180L -#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x00007e00L -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000L -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x03800000L -#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0x000000ffL -#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x001fc000L -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000L -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000L -#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00600000L -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x00002000L -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x00001000L -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x02000000L -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x04000000L -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000L -#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00800000L -#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x00000f00L -#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x01000000L -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x08000000L -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000L -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007fL -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L -#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L -#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x01000000L -#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L -#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L -#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x00200000L -#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L -#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK__CI__VI 0x00020000L -#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK__CI__VI 0x00040000L -#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK__CI__VI 0x00010000L -#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK__CI__VI 0x00004000L -#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK__CI__VI 0x00008000L -#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK__CI__VI 0x00002000L -#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L -#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L -#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L -#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L -#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L -#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK__CI__VI 0x00000040L -#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK__CI__VI 0x00000010L -#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK__CI__VI 0x00000020L -#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK__CI__VI 0x00000008L -#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK__CI__VI 0x00000002L -#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK__CI__VI 0x00000004L -#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x00000001L -#define SX_DEBUG_BUSY_2__RESERVED1_MASK__SI 0x0000007eL -#define SX_DEBUG_BUSY_2__RESERVED2_MASK__SI 0x0007e000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L -#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000L -#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L -#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L -#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L -#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L -#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L -#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L -#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L -#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L -#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L -#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L -#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L -#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L -#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L -#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L -#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L -#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L -#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L -#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L -#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L -#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L -#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L -#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L -#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L -#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L -#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK__CI__VI 0x000003ffL -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK__CI__VI 0x000ffc00L -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK__CI__VI 0x000003ffL -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK__CI__VI 0x000ffc00L -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK__CI__VI 0x000ffc00L -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK__CI__VI 0x000003ffL -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK__SI 0x000000ffL -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0x00000f00L -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0x0f000000L -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0x0000000fL -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0x000f0000L -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0x0000f000L -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000L -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0x000000f0L -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0x00f00000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0x000000f0L -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK__CI__VI 0x1c000000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0x00000f00L -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x001f0000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_VID_INDEX_MASK__SI 0x30000000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__SPARE_MASK__SI 0x0c000000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0x0000000fL -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK__CI__VI 0xe0000000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0x0000f000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x03e00000L -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_VID_INDEX_MASK__SI 0xc0000000L -#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK__CI__VI 0x000000ffL -#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL -#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL -#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L -#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001f0000L -#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000e000L -#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000L -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK__CI__VI 0x000000ffL -#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL -#define TA_DEBUG_DATA__DATA_MASK 0xffffffffL -#define TA_DEBUG_INDEX__INDEX_MASK 0x0000001fL -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000000ffL -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x0003fc00L -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x0003fc00L -#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x0003fc00L -#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL -#define TA_RESERVED_010C__Unused_MASK__CI__VI 0xffffffffL -#define TA_SCRATCH__SCRATCH_MASK 0xffffffffL -#define TA_STATUS__AL_BUSY_MASK 0x40000000L -#define TA_STATUS__BUSY_MASK 0x80000000L -#define TA_STATUS__FA_BUSY_MASK 0x20000000L -#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L -#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L -#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L -#define TA_STATUS__FG_BUSY_MASK 0x02000000L -#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L -#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L -#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L -#define TA_STATUS__FL_BUSY_MASK 0x08000000L -#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L -#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L -#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L -#define TA_STATUS__IN_BUSY_MASK 0x01000000L -#define TA_STATUS__LA_BUSY_MASK 0x04000000L -#define TA_STATUS__TA_BUSY_MASK 0x10000000L -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000fL -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0x0f000000L -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0xf0000000L -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK__CI__VI 0x0f000000L -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK__CI__VI 0xf0000000L -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L -#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000f0000L -#define TCC_CTRL__RATE_MASK 0x0000000cL -#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000f000L -#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK__CI__VI 0x00100000L -#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000f0L -#define TCC_EDC_COUNTER__DED_COUNT_MASK__SI__CI 0x000f0000L -#define TCC_EDC_COUNTER__SEC_COUNT_MASK__SI__CI 0x0000000fL -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0x0f000000L -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0xf0000000L -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK__CI__VI 0x0f000000L -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK__CI__VI 0xf0000000L -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCC_REDUNDANCY__MC_SEL0_MASK__CI__VI 0x00000001L -#define TCC_REDUNDANCY__MC_SEL1_MASK__CI__VI 0x00000002L -#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00ff0000L -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000ffffL -#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000L -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L -#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001feL -#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L -#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001c0L -#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000fL -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L -#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000fL -#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000f0L -#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000f00L -#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000f000L -#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000f0000L -#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00f00000L -#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0f000000L -#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000L -#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000fL -#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000f0L -#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000f00L -#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000f000L -#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000f0000L -#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00f00000L -#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0f000000L -#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000L -#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK__CI__VI 0x00000020L -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK__CI__VI 0x00000010L -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0fc00000L -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001f8000L -#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L -#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L -#define TCP_CNTL__INV_ALL_VMIDS_MASK__CI__VI 0x20000000L -#define TCP_CNTL__L1_SIZE_MASK 0x0000000cL -#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003ffL -#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007f0000L -#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000L -#define TCP_DEBUG_DATA__DATA_MASK 0x00ffffffL -#define TCP_DEBUG_INDEX__INDEX_MASK 0x0000001fL -#define TCP_EDC_COUNTER__DED_COUNT_MASK__SI__CI 0x000f0000L -#define TCP_EDC_COUNTER__SEC_COUNT_MASK__SI__CI 0x0000000fL -#define TCP_INVALIDATE__START_MASK 0x00000001L -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L -#define TCP_WATCH0_ADDR_H__ADDR_MASK__CI__VI 0x0000ffffL -#define TCP_WATCH0_ADDR_L__ADDR_MASK__CI__VI 0xffffffc0L -#define TCP_WATCH0_CNTL__MASK_MASK__CI__VI 0x00ffffffL -#define TCP_WATCH0_CNTL__MODE_MASK__CI__VI 0x60000000L -#define TCP_WATCH0_CNTL__VALID_MASK__CI__VI 0x80000000L -#define TCP_WATCH0_CNTL__VMID_MASK__CI__VI 0x0f000000L -#define TCP_WATCH1_ADDR_H__ADDR_MASK__CI__VI 0x0000ffffL -#define TCP_WATCH1_ADDR_L__ADDR_MASK__CI__VI 0xffffffc0L -#define TCP_WATCH1_CNTL__MASK_MASK__CI__VI 0x00ffffffL -#define TCP_WATCH1_CNTL__MODE_MASK__CI__VI 0x60000000L -#define TCP_WATCH1_CNTL__VALID_MASK__CI__VI 0x80000000L -#define TCP_WATCH1_CNTL__VMID_MASK__CI__VI 0x0f000000L -#define TCP_WATCH2_ADDR_H__ADDR_MASK__CI__VI 0x0000ffffL -#define TCP_WATCH2_ADDR_L__ADDR_MASK__CI__VI 0xffffffc0L -#define TCP_WATCH2_CNTL__MASK_MASK__CI__VI 0x00ffffffL -#define TCP_WATCH2_CNTL__MODE_MASK__CI__VI 0x60000000L -#define TCP_WATCH2_CNTL__VALID_MASK__CI__VI 0x80000000L -#define TCP_WATCH2_CNTL__VMID_MASK__CI__VI 0x0f000000L -#define TCP_WATCH3_ADDR_H__ADDR_MASK__CI__VI 0x0000ffffL -#define TCP_WATCH3_ADDR_L__ADDR_MASK__CI__VI 0xffffffc0L -#define TCP_WATCH3_CNTL__MASK_MASK__CI__VI 0x00ffffffL -#define TCP_WATCH3_CNTL__MODE_MASK__CI__VI 0x60000000L -#define TCP_WATCH3_CNTL__VALID_MASK__CI__VI 0x80000000L -#define TCP_WATCH3_CNTL__VMID_MASK__CI__VI 0x0f000000L -#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK__CI 0x00000ff0L -#define TCS_CGTT_SCLK_CTRL__ON_DELAY_MASK__CI 0x0000000fL -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK__CI 0x80000000L -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK__CI 0x40000000L -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK__CI 0x20000000L -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK__CI 0x10000000L -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK__CI 0x08000000L -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK__CI 0x04000000L -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK__CI 0x02000000L -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK__CI 0x01000000L -#define TCS_CTRL__RATE_MASK__CI 0x00000003L -#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI 0x0f000000L -#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI 0xf0000000L -#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI 0x000003ffL -#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI 0x000ffc00L -#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI 0x00f00000L -#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI 0x0f000000L -#define TCS_PERFCOUNTER0_SELECT__PERF_MODE_MASK__CI 0xf0000000L -#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI 0x000ffc00L -#define TCS_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI 0x000003ffL -#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI 0x00f00000L -#define TCS_PERFCOUNTER1_SELECT__PERF_MODE_MASK__CI 0xf0000000L -#define TCS_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI 0x000003ffL -#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK__CI 0x00f00000L -#define TCS_PERFCOUNTER2_SELECT__PERF_MODE_MASK__CI 0xf0000000L -#define TCS_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI 0x000003ffL -#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK__CI 0xffffffffL -#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK__CI 0x00f00000L -#define TCS_PERFCOUNTER3_SELECT__PERF_MODE_MASK__CI 0xf0000000L -#define TCS_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI 0x000003ffL -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK__CI__VI 0x00000003L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK__CI__VI 0x00300000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK__CI__VI 0x00c00000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK__CI__VI 0x03000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK__CI__VI 0x0c000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK__CI__VI 0x30000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK__CI__VI 0xc0000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK__CI__VI 0x0000000cL -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK__CI__VI 0x00000030L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK__CI__VI 0x000000c0L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK__CI__VI 0x00000300L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK__CI__VI 0x00000c00L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK__CI__VI 0x00003000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK__CI__VI 0x0000c000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK__CI__VI 0x00030000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK__CI__VI 0x000c0000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK__CI__VI 0x00000003L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK__CI__VI 0x0000000cL -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK__CI__VI 0x00000030L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK__CI__VI 0x000000c0L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK__CI__VI 0x00000300L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK__CI__VI 0x00000c00L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK__CI__VI 0x00003000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK__CI__VI 0x0000c000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK__CI__VI 0x00030000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK__CI__VI 0x000c0000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK__CI__VI 0x00300000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK__CI__VI 0x00c00000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK__CI__VI 0x03000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK__CI__VI 0x0c000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK__CI__VI 0x30000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK__CI__VI 0xc0000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK__CI__VI 0x00000001L -#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK__CI__VI 0x00000400L -#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK__CI__VI 0x00000800L -#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK__CI__VI 0x00001000L -#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK__CI__VI 0x00002000L -#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK__CI__VI 0x00004000L -#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK__CI__VI 0x00008000L -#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK__CI__VI 0x00010000L -#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK__CI__VI 0x00020000L -#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK__CI__VI 0x00040000L -#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK__CI__VI 0x00080000L -#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK__CI__VI 0x00000002L -#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK__CI__VI 0x00100000L -#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK__CI__VI 0x00200000L -#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK__CI__VI 0x00400000L -#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK__CI__VI 0x00800000L -#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK__CI__VI 0x01000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK__CI__VI 0x02000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK__CI__VI 0x04000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK__CI__VI 0x08000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK__CI__VI 0x10000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK__CI__VI 0x20000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK__CI__VI 0x00000004L -#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK__CI__VI 0x40000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK__CI__VI 0x80000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK__CI__VI 0x00000008L -#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK__CI__VI 0x00000010L -#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK__CI__VI 0x00000020L -#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK__CI__VI 0x00000040L -#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK__CI__VI 0x00000080L -#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK__CI__VI 0x00000100L -#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK__CI__VI 0x00000200L -#define TC_CFG_L1_VOLATILE__VOL_MASK__CI__VI 0x0000000fL -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK__CI__VI 0x00000003L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK__CI__VI 0x00300000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK__CI__VI 0x00c00000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK__CI__VI 0x03000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK__CI__VI 0x0c000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK__CI__VI 0x30000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK__CI__VI 0xc0000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK__CI__VI 0x0000000cL -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK__CI__VI 0x00000030L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK__CI__VI 0x000000c0L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK__CI__VI 0x00000300L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK__CI__VI 0x00000c00L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK__CI__VI 0x00003000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK__CI__VI 0x0000c000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK__CI__VI 0x00030000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK__CI__VI 0x000c0000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK__CI__VI 0x00000003L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK__CI__VI 0x00300000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK__CI__VI 0x00c00000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK__CI__VI 0x03000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK__CI__VI 0x0c000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK__CI__VI 0x30000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK__CI__VI 0xc0000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK__CI__VI 0x0000000cL -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK__CI__VI 0x00000030L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK__CI__VI 0x000000c0L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK__CI__VI 0x00000300L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK__CI__VI 0x00000c00L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK__CI__VI 0x00003000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK__CI__VI 0x0000c000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK__CI__VI 0x00030000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK__CI__VI 0x000c0000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK__CI__VI 0x00000003L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK__CI__VI 0x0000000cL -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK__CI__VI 0x00000030L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK__CI__VI 0x000000c0L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK__CI__VI 0x00000300L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK__CI__VI 0x00000c00L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK__CI__VI 0x00003000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK__CI__VI 0x0000c000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK__CI__VI 0x00030000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK__CI__VI 0x000c0000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK__CI__VI 0x00300000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK__CI__VI 0x00c00000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK__CI__VI 0x03000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK__CI__VI 0x0c000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK__CI__VI 0x30000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK__CI__VI 0xc0000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK__CI__VI 0x00000003L -#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK__CI__VI 0x00300000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK__CI__VI 0x00c00000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK__CI__VI 0x03000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK__CI__VI 0x0c000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK__CI__VI 0x30000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK__CI__VI 0xc0000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK__CI__VI 0x0000000cL -#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK__CI__VI 0x00000030L -#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK__CI__VI 0x000000c0L -#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK__CI__VI 0x00000300L -#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK__CI__VI 0x00000c00L -#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK__CI__VI 0x00003000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK__CI__VI 0x0000c000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK__CI__VI 0x00030000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK__CI__VI 0x000c0000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK__CI__VI 0x00000003L -#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK__CI__VI 0x0000000cL -#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK__CI__VI 0x00000030L -#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK__CI__VI 0x000000c0L -#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK__CI__VI 0x00000300L -#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK__CI__VI 0x00000c00L -#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK__CI__VI 0x00003000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK__CI__VI 0x0000c000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK__CI__VI 0x00030000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK__CI__VI 0x000c0000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK__CI__VI 0x00300000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK__CI__VI 0x00c00000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK__CI__VI 0x03000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK__CI__VI 0x0c000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK__CI__VI 0x30000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK__CI__VI 0xc0000000L -#define TC_CFG_L2_VOLATILE__VOL_MASK__CI__VI 0x0000000fL -#define TDP_ACC_CORE_0__Cmp_Unit_Tdp_Margin_Acc_MASK__CI__VI 0x001fffffL -#define TDP_ACC_CORE_0__Cmp_Unit_Tdp_Sample_Cnt_MASK__CI__VI 0xff000000L -#define TDP_ACC_CORE_0__RESERVED_MASK__CI__VI 0x00e00000L -#define TDP_ACC_CORE_1__Cmp_Unit_Tdp_Margin_Acc_MASK__CI__VI 0x001fffffL -#define TDP_ACC_CORE_1__Cmp_Unit_Tdp_Sample_Cnt_MASK__CI__VI 0xff000000L -#define TDP_ACC_CORE_1__RESERVED_MASK__CI__VI 0x00e00000L -#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL -#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK__CI__VI 0x00100000L -#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L -#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L -#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L -#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L -#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L -#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L -#define TD_CNTL__PRECISION_COMPATIBILITY_MASK__CI__VI 0x00008000L -#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L -#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L -#define TD_DEBUG_DATA__DATA_MASK__CI__VI 0xffffffffL -#define TD_DEBUG_DATA__DATA_MASK__SI 0x00ffffffL -#define TD_DEBUG_INDEX__INDEX_MASK 0x0000001fL -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000000ffL -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x0003fc00L -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x0003fc00L -#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x0003fc00L -#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000000ffL -#define TD_SCRATCH__SCRATCH_MASK 0xffffffffL -#define TD_STATUS__BUSY_MASK 0x80000000L -#define THERMAL_PROTECT_COUNTER__THERMAL_PROTECT_COUNTER_MASK__SI 0xffffffffL -#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0x000000ffL -#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0x0000ff00L -#define THM_CMON_CTRL2__ADC_RANGE_RST_MASK__SI 0x00000001L -#define THM_CMON_CTRL__ADC_CFG_MASK__SI 0x00001800L -#define THM_CMON_CTRL__ADC_GAIN_ADJ_MASK__SI 0x00000780L -#define THM_CMON_CTRL__ADC_GAIN_ADJ_MODE_MASK__SI 0x40000000L -#define THM_CMON_CTRL__BGADJ_MASK__SI 0x0000007eL -#define THM_CMON_CTRL__BGADJ_MODE_MASK__SI 0x20000000L -#define THM_CMON_CTRL__CMON_RESET_MASK__SI 0x80000000L -#define THM_CMON_CTRL__DAC_BYPASS_MASK__SI 0x07fe0000L -#define THM_CMON_CTRL__OFFSET_CAN_EN_MASK__SI 0x08000000L -#define THM_CMON_CTRL__PDB_MASK__SI 0x00000001L -#define THM_CMON_CTRL__SELF_CAL_EN_MASK__SI 0x10000000L -#define THM_CMON_CTRL__TESTCNTL_MASK__SI 0x0001e000L -#define THM_CTF_DELAY__CTF_DELAY_CNT_MASK__CI 0x000fffffL -#define THM_CTF_STATUS__CTF_THRESHOLD_EXCEEDED_MASK__CI 0x00000001L -#define THM_CTF_STATUS__CTF_TRIGGERED_MASK__CI 0x00000002L -#define THM_SMC_IND_DATA__SMC_IND_DATA_MASK__CI 0xffffffffL -#define THM_SMC_IND_INDEX__SMC_IND_ADDR_MASK__CI 0xffffffffL -#define THM_SW_TEMP__SW_TEMP_MASK__CI 0x000001ffL -#define THM_TMON0_CSR_RD__READ_DATA_MASK__SI__CI 0x00000fffL -#define THM_TMON0_CSR_WR__CSR_ADDR_MASK__SI__CI 0x00000ffcL -#define THM_TMON0_CSR_WR__CSR_READ_MASK__SI__CI 0x00000002L -#define THM_TMON0_CSR_WR__CSR_WRITE_MASK__SI__CI 0x00000001L -#define THM_TMON0_CSR_WR__SPARE_MASK__SI__CI 0x01000000L -#define THM_TMON0_CSR_WR__WRITE_DATA_MASK__SI__CI 0x00fff000L -#define THM_TMON0_CTRL2__RDIL_PRESENT_MASK__SI__CI 0x0000ffffL -#define THM_TMON0_CTRL2__RDIR_PRESENT_MASK__SI__CI 0xffff0000L -#define THM_TMON0_CTRL__BGADJ_MASK__SI__CI 0x000001feL -#define THM_TMON0_CTRL__BGADJ_MODE_MASK__SI__CI 0x00000200L -#define THM_TMON0_CTRL__DEBUG_MODE_MASK__SI__CI 0x00001000L -#define THM_TMON0_CTRL__INT_MEAS_EN_MASK__SI__CI 0x00000800L -#define THM_TMON0_CTRL__POWER_DOWN_MASK__SI__CI 0x00000001L -#define THM_TMON0_CTRL__TMON_PAUSE_MASK__SI__CI 0x00000400L -#define THM_TMON0_DEBUG__DEBUG_RDI_MASK__SI__CI 0x0000001fL -#define THM_TMON0_DEBUG__DEBUG_Z_MASK__SI__CI 0x0000ffe0L -#define THM_TMON0_INT_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_INT_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_INT_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL0_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL0_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL0_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL10_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL10_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL10_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL11_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL11_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL11_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL12_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL12_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL12_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL13_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL13_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL13_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL14_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL14_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL14_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL15_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL15_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL15_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL1_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL1_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL1_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL2_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL2_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL2_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL3_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL3_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL3_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL4_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL4_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL4_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL5_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL5_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL5_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL6_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL6_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL6_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL7_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL7_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL7_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL8_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL8_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL8_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIL9_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIL9_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIL9_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR0_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR0_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR0_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR10_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR10_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR10_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR11_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR11_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR11_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR12_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR12_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR12_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR13_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR13_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR13_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR14_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR14_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR14_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR15_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR15_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR15_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR1_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR1_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR1_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR2_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR2_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR2_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR3_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR3_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR3_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR4_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR4_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR4_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR5_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR5_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR5_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR6_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR6_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR6_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR7_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR7_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR7_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR8_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR8_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR8_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON0_RDIR9_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON0_RDIR9_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON0_RDIR9_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_CSR_RD__READ_DATA_MASK__SI__CI 0x00000fffL -#define THM_TMON1_CSR_WR__CSR_ADDR_MASK__SI__CI 0x00000ffcL -#define THM_TMON1_CSR_WR__CSR_READ_MASK__SI__CI 0x00000002L -#define THM_TMON1_CSR_WR__CSR_WRITE_MASK__SI__CI 0x00000001L -#define THM_TMON1_CSR_WR__SPARE_MASK__SI__CI 0x01000000L -#define THM_TMON1_CSR_WR__WRITE_DATA_MASK__SI__CI 0x00fff000L -#define THM_TMON1_CTRL2__RDIL_PRESENT_MASK__SI__CI 0x0000ffffL -#define THM_TMON1_CTRL2__RDIR_PRESENT_MASK__SI__CI 0xffff0000L -#define THM_TMON1_CTRL__BGADJ_MASK__SI__CI 0x000001feL -#define THM_TMON1_CTRL__BGADJ_MODE_MASK__SI__CI 0x00000200L -#define THM_TMON1_CTRL__DEBUG_MODE_MASK__SI__CI 0x00001000L -#define THM_TMON1_CTRL__INT_MEAS_EN_MASK__SI__CI 0x00000800L -#define THM_TMON1_CTRL__POWER_DOWN_MASK__SI__CI 0x00000001L -#define THM_TMON1_CTRL__TMON_PAUSE_MASK__SI__CI 0x00000400L -#define THM_TMON1_DEBUG__DEBUG_RDI_MASK__SI__CI 0x0000001fL -#define THM_TMON1_DEBUG__DEBUG_Z_MASK__SI__CI 0x0000ffe0L -#define THM_TMON1_INT_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_INT_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_INT_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL0_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL0_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL0_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL10_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL10_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL10_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL11_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL11_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL11_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL12_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL12_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL12_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL13_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL13_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL13_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL14_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL14_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL14_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL15_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL15_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL15_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL1_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL1_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL1_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL2_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL2_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL2_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL3_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL3_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL3_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL4_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL4_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL4_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL5_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL5_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL5_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL6_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL6_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL6_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL7_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL7_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL7_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL8_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL8_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL8_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIL9_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIL9_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIL9_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR0_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR0_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR0_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR10_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR10_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR10_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR11_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR11_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR11_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR12_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR12_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR12_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR13_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR13_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR13_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR14_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR14_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR14_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR15_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR15_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR15_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR1_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR1_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR1_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR2_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR2_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR2_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR3_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR3_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR3_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR4_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR4_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR4_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR5_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR5_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR5_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR6_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR6_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR6_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR7_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR7_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR7_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR8_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR8_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR8_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON1_RDIR9_DATA__TEMP_MASK__SI__CI 0x00fff000L -#define THM_TMON1_RDIR9_DATA__VALID_MASK__SI__CI 0x00000800L -#define THM_TMON1_RDIR9_DATA__Z_MASK__SI__CI 0x000007ffL -#define THM_TMON_CONFIG2__A_MASK__SI__CI 0x00000fffL -#define THM_TMON_CONFIG2__B_MASK__SI__CI 0x0003f000L -#define THM_TMON_CONFIG2__C_MASK__SI__CI 0x1ffc0000L -#define THM_TMON_CONFIG2__K_MASK__SI__CI 0x20000000L -#define THM_TMON_CONFIG__CONFIG_SOURCE_MASK__CI 0x00000020L -#define THM_TMON_CONFIG__DEBUG_BUS_EN_MASK__SI 0x00000020L -#define THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK__SI__CI 0x00000008L -#define THM_TMON_CONFIG__NUM_ACQ_MASK__SI__CI 0x00000007L -#define THM_TMON_CONFIG__RDI_INTERLEAVE_MASK__SI__CI 0x00000010L -#define THM_TMON_CONFIG__Z_MASK__SI__CI 0xffe00000L -#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK__SI 0x00000300L -#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK__SI 0x00000010L -#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK__SI 0x00000001L -#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK__SI 0x00000300L -#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK__SI 0x00000003L -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK__SI 0x00000001L -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK__SI 0x00000002L -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK__SI 0x00000004L -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK__SI 0x00000008L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK__SI 0x80000000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK__SI 0x00000070L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK__SI 0x00000080L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK__SI 0x00000300L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK__SI 0x0000000fL -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK__SI 0x00000800L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK__SI 0x00001000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK__SI 0x00000400L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK__SI 0x00700000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK__SI 0x00800000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK__SI 0x03000000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK__SI 0x000f0000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK__SI 0x08000000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK__SI 0x10000000L -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK__SI 0x04000000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK__SI 0x00000070L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK__SI 0x00000080L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK__SI 0x00000300L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK__SI 0x0000000fL -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK__SI 0x00000800L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK__SI 0x00001000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK__SI 0x00000400L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK__SI 0x00700000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK__SI 0x00800000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK__SI 0x03000000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK__SI 0x000f0000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK__SI 0x08000000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK__SI 0x10000000L -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK__SI 0x04000000L -#define TMDS_CTL_BITS__TMDS_CTL0_MASK__SI 0x00000001L -#define TMDS_CTL_BITS__TMDS_CTL1_MASK__SI 0x00000100L -#define TMDS_CTL_BITS__TMDS_CTL2_MASK__SI 0x00010000L -#define TMDS_CTL_BITS__TMDS_CTL3_MASK__SI 0x01000000L -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK__SI 0x00000001L -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK__SI 0x01000000L -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK__SI 0x00000100L -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK__SI 0x000f0000L -#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK__SI 0x00000070L -#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK__SI 0x02000000L -#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK__SI 0x01000000L -#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK__SI 0x00000001L -#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK__SI 0x00000200L -#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK__SI 0x00000100L -#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK__SI 0x00020000L -#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK__SI 0x00010000L -#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK__SI 0x00000003L -#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK__SI 0x000003ffL -#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK__SI 0x03ff0000L -#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK__SI 0x000003ffL -#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK__SI 0x03ff0000L -#define TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK__SI 0x000003ffL -#define TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK__SI 0x03ff0000L -#define TST_MISC_CTRL__BITS31_4_MASK 0xfffffff0L -#define TST_MISC_CTRL__JTAG_SRBM_DIS_MASK 0x00000002L -#define TST_MISC_CTRL__TST_CNB_DONE_MASK 0x00000008L -#define TST_MISC_CTRL__TST_SMSCLK_DIS_MASK 0x00000004L -#define TST_MISC_CTRL__TST_TCLK_SLOW_EN_MASK 0x00000001L -#define TST_TC_JTAG_0__TST_TC_MODE_MASK 0x00010000L -#define TST_TC_JTAG_0__TST_TC_TDI_MASK 0x0000ff00L -#define TST_TC_JTAG_0__TST_TC_TDO_MASK_MASK 0xff000000L -#define TST_TC_JTAG_0__TST_TC_TMS_MASK 0x000000ffL -#define TST_TC_JTAG_1__TC_TST_DONE_MASK 0x80000000L -#define TST_TC_JTAG_1__TC_TST_TDO_MASK 0x000000ffL -#define UART_CLK_GPIO_SEL__CLK_OBSERVE_GPIO_MASK 0x00007c00L -#define UART_CLK_GPIO_SEL__UART_RX_GPIO_MASK 0x000003e0L -#define UART_CLK_GPIO_SEL__UART_TX_GPIO_MASK 0x0000001fL -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_ACK_MASK__SI 0x00000100L -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_FLAG_MASK__SI 0x00000001L -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_INT_STATUS_MASK__SI 0x01000000L -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_MASK_MASK__SI 0x00010000L -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_ACK_MASK__SI 0x00000200L -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_FLAG_MASK__SI 0x00000002L -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_INT_STATUS_MASK__SI 0x02000000L -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_MASK_MASK__SI 0x00020000L -#define UNDERFLOW_STATUS__UNDERFLOW_MASK_NO_RTS_ACTIVE_MASK__SI 0x00040000L -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK__SI 0x00000001L -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK__SI 0x00000040L -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK__SI 0x00000030L -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK__SI 0x00010000L -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK__SI 0x00001000L -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK__SI 0x00000100L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK__SI 0x00000400L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK__SI 0x00000200L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK__SI 0x00000100L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKA_MASK__SI 0x00001000L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK__SI 0x00000001L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK__SI 0x10000000L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK__SI 0x0f000000L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK__SI 0x00f00000L -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK__SI 0x000f0000L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK__SI 0x00000400L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK__SI 0x00000200L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK__SI 0x00000100L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKB_MASK__SI 0x00001000L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK__SI 0x00000001L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK__SI 0x10000000L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK__SI 0x0f000000L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK__SI 0x00f00000L -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK__SI 0x000f0000L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK__SI 0x00000400L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK__SI 0x00000200L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK__SI 0x00000100L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKC_MASK__SI 0x00001000L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK__SI 0x00000001L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK__SI 0x10000000L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK__SI 0x0f000000L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK__SI 0x00f00000L -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK__SI 0x000f0000L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK__SI 0x00000400L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK__SI 0x00000200L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK__SI 0x00000100L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKD_MASK__SI 0x00001000L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK__SI 0x00000001L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK__SI 0x10000000L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK__SI 0x0f000000L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK__SI 0x00f00000L -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK__SI 0x000f0000L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK__SI 0x00000400L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK__SI 0x00000200L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK__SI 0x00000100L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKE_MASK__SI 0x00001000L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK__SI 0x00000001L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK__SI 0x10000000L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK__SI 0x0f000000L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK__SI 0x00f00000L -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK__SI 0x000f0000L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK__SI 0x00000400L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK__SI 0x00000200L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK__SI 0x00000100L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKF_MASK__SI 0x00001000L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK__SI 0x00000001L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK__SI 0x10000000L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK__SI 0x0f000000L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK__SI 0x00f00000L -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK__SI 0x000f0000L -#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK__SI 0xffffffffL -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR0_MASK__SI 0x0000000cL -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR1_MASK__SI 0x000000c0L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR2_MASK__SI 0x00000c00L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR3_MASK__SI 0x0000c000L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR4_MASK__SI 0x000c0000L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS0_MASK__SI 0x00000003L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS1_MASK__SI 0x00000030L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS2_MASK__SI 0x00000300L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS3_MASK__SI 0x00003000L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS4_MASK__SI 0x00030000L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS_STR_EN_MASK__SI 0x00100000L -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS_STR_MASK__SI 0x0f000000L -#define UNIPHY_MACRO_CONTROL2__UNIPHY_BGADJ_MASK__SI 0x0003f000L -#define UNIPHY_MACRO_CONTROL2__UNIPHY_BGPDN_MASK__SI 0x10000000L -#define UNIPHY_MACRO_CONTROL2__UNIPHY_RESERVED_MASK__SI 0x0000003fL -#define UNIPHY_MACRO_CONTROL2__UNIPHY_TX_VS_ADJ_MASK__SI 0x01f00000L -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_BUF_PDNB_MASK__SI 0x00000001L -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_CLKF_MASK__SI 0x00007f00L -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_CLKR_MASK__SI 0x00030000L -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_INT_CP_CNTL_MASK__SI 0x0f000000L -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_PROP_CP_CNTL_MASK__SI 0xf0000000L -#define UNIPHY_MACRO_CONTROL3__UNIPHY_PHYPLL_PDIV_SEL_MASK__SI 0x00700000L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK__SI 0x00000003L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK__SI 0x0000000cL -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK__SI 0x00000030L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK__SI 0x000000c0L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_P90PLL_RESET_EN_MASK__SI 0x00001000L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_P90PLL_TCLK_10X_SRC_MASK__SI 0x00002000L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_PBYPASS_MASK__SI 0x00008000L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_PG2PLL_VCTRLADC_EN_MASK__SI 0x00100000L -#define UNIPHY_MACRO_CONTROL4__UNIPHY_PTCLK_10X_EN_MASK__SI 0x00020000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_BG2PLL_VCTRLADC_MASK__SI 0x0f000000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_EN_MASK__SI 0x00001000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_4_MASK__SI 0x20000000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK__SI 0x000f0000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK__SI 0x00002000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_GEN_STATUS_4_MASK__SI 0x40000000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_GEN_STATUS_MASK__SI 0x00f00000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_P90_BPLL_INTRESET_MASK__SI 0x10000000L -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK__SI 0x0000000fL -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TX_MASK__SI 0x000003f0L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_CLKINV_MASK__SI 0x00001000L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_IDCLK_SEL_MASK__SI 0x00000100L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_IDSCKSEL_MASK__SI 0x00000030L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_INCOHERENT_BY2_MASK__SI 0x00010000L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_ITCLKSEL_MASK__SI 0x40000000L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_ITMDS_INCO_EN_MASK__SI 0x10000000L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_PLL_ENABLE_MASK__SI 0x00000001L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_PLL_PWRUP_SEQ_EN_MASK__SI 0x00000040L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_PLL_RESET_MASK__SI 0x00000002L -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_VCO_MODE_MASK__SI 0x00100000L -#define URGENCY_STAT__MEMORY_LEVEL_MASK__SI 0x000fff00L -#define URGENCY_STAT__URGENCY_STAT_MASK__SI 0x00000001L -#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L -#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L -#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK__CI__VI 0x0f000000L -#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK__CI__VI 0xf0000000L -#define UVD_ADDR_MODE__ADDR_MODE_DBW_EN_MASK__SI 0x00000010L -#define UVD_ADDR_MODE__ADDR_MODE_DBW_MASK__SI 0x0000000cL -#define UVD_ADDR_MODE__ADDR_MODE_DB_MASK__SI 0x00000060L -#define UVD_ADDR_MODE__ADDR_MODE_MASK__SI 0x00000003L -#define UVD_ADDR_MODE__ARRAY_MODE_MASK__SI 0x00001e00L -#define UVD_ADDR_MODE__DBW_ARRAY_MODE_MASK__SI 0x0001e000L -#define UVD_ADDR_MODE__DBW_FIELD_FORMAT_MASK__SI 0x00000100L -#define UVD_ADDR_MODE__DB_ARRAY_MODE_MASK__SI 0x001e0000L -#define UVD_ADDR_MODE__DB_MP_ADDR_MODE_DECOUPLE_MASK__SI 0x00000080L -#define UVD_ADDR_MODE__USE_ADDR_MACRO_MASK__SI 0x00200000L -#define UVD_AVP_COOKIE_ID__ID_MASK__SI 0x0fffffffL -#define UVD_AVP_CSA_ADDR__ADDR_MASK__SI 0x0fffffffL -#define UVD_AVP_CSA_SIZE__SIZE_MASK__SI 0xffffffffL -#define UVD_AVP_EXT_INT_CTX_ID__CTX_ID_MASK__SI 0x0fffffffL -#define UVD_AVP_EXT_INT_ID__ID_MASK__SI 0x000000ffL -#define UVD_AVP_FCS_STATUS__STATUS_MASK__SI 0xffffffffL -#define UVD_AVP_IDLE_COOKIE_ID__ID_MASK__SI 0x0fffffffL -#define UVD_AVP_RLC_HB_BASE__HB_BASE_MASK__SI 0xffffffffL -#define UVD_AVP_RLC_HB_CNTL__HB_BUFSZ_MASK__SI 0xffffffffL -#define UVD_AVP_RLC_HB_RPTR__HB_RPTR_MASK__SI 0xffffffffL -#define UVD_AVP_RLC_HB_WPTR_LSB_ADDR__HB_WPTR_LSB_ADDR_MASK__SI 0xfffffffcL -#define UVD_AVP_RLC_HB_WPTR_MSB_ADDR__HB_WPTR_MSB_ADDR_MASK__SI 0x000000ffL -#define UVD_AVP_RLC_HB_WPTR__HB_WPTR_MASK__SI 0xffffffffL -#define UVD_AVP_RLC_RL_BASE__RL_BASE_MASK__SI 0xffffffffL -#define UVD_AVP_RLC_RL_SIZE__RL_SIZE_MASK__SI 0x0000000fL -#define UVD_AVP_RLC_SCRATCH__SCRATCH_MASK__SI 0xffffffffL -#define UVD_CBUF_ID__CBUF_ID_MASK__SI 0xffffffffL -#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK__SI 0x0000f000L -#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK__SI 0x00000f00L -#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK__SI 0x00000001L -#define UVD_CGC_CTRL__IDCT_MODE_MASK__SI 0x00800000L -#define UVD_CGC_CTRL__LBSI_MODE_MASK__SI 0x04000000L -#define UVD_CGC_CTRL__LMI_MC_MODE_MASK__SI 0x00200000L -#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK__SI 0x00400000L -#define UVD_CGC_CTRL__MPC_MODE_MASK__SI 0x02000000L -#define UVD_CGC_CTRL__MPEG2_MODE_MASK__SI 0x00040000L -#define UVD_CGC_CTRL__MPRD_MODE_MASK__SI 0x01000000L -#define UVD_CGC_CTRL__RBC_MODE_MASK__SI 0x00100000L -#define UVD_CGC_CTRL__REGS_MODE_MASK__SI 0x00080000L -#define UVD_CGC_CTRL__SYS_MODE_MASK__SI 0x00010000L -#define UVD_CGC_CTRL__UDEC_MODE_MASK__SI 0x00020000L -#define UVD_CGC_GATE__IDCT_MASK__SI 0x00000080L -#define UVD_CGC_GATE__LBSI_MASK__SI 0x00000400L -#define UVD_CGC_GATE__LMI_MC_MASK__SI 0x00000020L -#define UVD_CGC_GATE__LMI_UMC_MASK__SI 0x00000040L -#define UVD_CGC_GATE__MPC_MASK__SI 0x00000200L -#define UVD_CGC_GATE__MPEG2_MASK__SI 0x00000004L -#define UVD_CGC_GATE__MPRD_MASK__SI 0x00000100L -#define UVD_CGC_GATE__RBC_MASK__SI 0x00000010L -#define UVD_CGC_GATE__REGS_MASK__SI 0x00000008L -#define UVD_CGC_GATE__SYS_MASK__SI 0x00000001L -#define UVD_CGC_GATE__UDEC_MASK__SI 0x00000002L -#define UVD_CGC_STATUS__IDCT_SCLK_MASK__SI 0x00004000L -#define UVD_CGC_STATUS__IDCT_VCLK_MASK__SI 0x00008000L -#define UVD_CGC_STATUS__LBSI_SCLK_MASK__SI 0x00200000L -#define UVD_CGC_STATUS__LBSI_VCLK_MASK__SI 0x00400000L -#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK__SI 0x00001000L -#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK__SI 0x00002000L -#define UVD_CGC_STATUS__MPC_DCLK_MASK__SI 0x00100000L -#define UVD_CGC_STATUS__MPC_SCLK_MASK__SI 0x00080000L -#define UVD_CGC_STATUS__MPEG2_DCLK_MASK__SI 0x00000080L -#define UVD_CGC_STATUS__MPEG2_SCLK_MASK__SI 0x00000040L -#define UVD_CGC_STATUS__MPEG2_VCLK_MASK__SI 0x00000100L -#define UVD_CGC_STATUS__MPRD_DCLK_MASK__SI 0x00020000L -#define UVD_CGC_STATUS__MPRD_SCLK_MASK__SI 0x00010000L -#define UVD_CGC_STATUS__MPRD_VCLK_MASK__SI 0x00040000L -#define UVD_CGC_STATUS__RBC_SCLK_MASK__SI 0x00000800L -#define UVD_CGC_STATUS__REGS_SCLK_MASK__SI 0x00000200L -#define UVD_CGC_STATUS__REGS_VCLK_MASK__SI 0x00000400L -#define UVD_CGC_STATUS__SYS_DCLK_MASK__SI 0x00000002L -#define UVD_CGC_STATUS__SYS_SCLK_MASK__SI 0x00000001L -#define UVD_CGC_STATUS__SYS_VCLK_MASK__SI 0x00000004L -#define UVD_CGC_STATUS__UDEC_DCLK_MASK__SI 0x00000010L -#define UVD_CGC_STATUS__UDEC_SCLK_MASK__SI 0x00000008L -#define UVD_CGC_STATUS__UDEC_VCLK_MASK__SI 0x00000020L -#define UVD_CONFIG__UVD_RDREQ_URG_MASK__SI__CI 0x00000f00L -#define UVD_CONFIG__UVD_REQ_TRAN_MASK__SI__CI 0x00010000L -#define UVD_CONTEXT_ID__CONTEXT_ID_MASK__SI 0xffffffffL -#define UVD_COOKIE_ID__ID_MASK__SI 0x0fffffffL -#define UVD_CSA_ADDR__ADDR_MASK__SI 0x0fffffffL -#define UVD_CSA_SIZE__SIZE_MASK__SI 0xffffffffL -#define UVD_CTX_DATA__DATA_MASK__SI 0xffffffffL -#define UVD_CTX_INDEX__INDEX_MASK__SI 0x000000ffL -#define UVD_CXW_BLOCK_STATUS__LBSI_IDLE_MASK__SI 0x00000002L -#define UVD_CXW_BLOCK_STATUS__LMI_IDLE_MASK__SI 0x00000004L -#define UVD_CXW_BLOCK_STATUS__VCPU_IDLE_MASK__SI 0x00000001L -#define UVD_CXW_CNTL__EXTERNAL_CXW_EN_MASK__SI 0x00000002L -#define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN_MASK__SI 0x00000020L -#define UVD_CXW_CNTL__HOST_CXW_EN_MASK__SI 0x00000001L -#define UVD_CXW_CNTL__HOST_CXW_INT_EN_MASK__SI 0x00000010L -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_EN_MASK__SI 0x00000004L -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_IDCT_EN_MASK__SI 0x00000100L -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_IDCT_INT_EN_MASK__SI 0x00000400L -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_INT_EN_MASK__SI 0x00000040L -#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN_MASK__SI 0x00000008L -#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN_MASK__SI 0x00000080L -#define UVD_CXW_EN__CXW_ENABLE_MASK__SI 0x00000001L -#define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED_MASK__SI 0x00000002L -#define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED_MASK__SI 0x00000001L -#define UVD_CXW_EVENT__REG_PRIVILEGE_FAULT_EVENT_IDCT_OCCURRED_MASK__SI 0x00000040L -#define UVD_CXW_EVENT__REG_PRIVILEGE_FAULT_EVENT_OCCURRED_MASK__SI 0x00000004L -#define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK__SI 0x00000020L -#define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED_MASK__SI 0x00000010L -#define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK__SI 0x00000008L -#define UVD_CXW_FINISHED__CXW_FINISHED_MASK__SI 0x00000001L -#define UVD_CXW_INT_ID__ID_MASK__SI 0x000000ffL -#define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR_MASK__SI 0xffffffc0L -#define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE_MASK__SI 0xffffffffL -#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE_MASK__SI 0x04000000L -#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE_MASK__SI 0x08000000L -#define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET_MASK__SI 0x03ffffffL -#define UVD_CXW_SE__CXW_SCAN_ENABLE_MASK__SI 0x00000001L -#define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL_MASK__SI 0x00000001L -#define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT_MASK__SI 0x00000ffeL -#define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED_MASK__SI 0x00000001L -#define UVD_CXW_START__START_CXW_MASK__SI 0x00000001L -#define UVD_CXW_WR_INT_CTX_ID__ID_MASK__SI 0x0fffffffL -#define UVD_CXW_WR_INT_ID__ID_MASK__SI 0x000000ffL -#define UVD_CXW_WR__DAT_MASK__SI 0x0fffffffL -#define UVD_CXW_WR__STAT_MASK__SI 0x80000000L -#define UVD_DBW_BUF_SIZE__PITCH_MASK__SI 0x00000ff0L -#define UVD_DBW_CHROMA_ADR__CHROMA_ADR_MASK__SI 0xffffffc0L -#define UVD_DBW_CHROMA_BOT_ADR__CHROMA_BOT_ADR_MASK__SI 0xffffffc0L -#define UVD_DBW_LUMA_ADR__LUMA_ADR_MASK__SI 0xffffffc0L -#define UVD_DBW_LUMA_BOT_ADR__LUMA_BOT_ADR_MASK__SI 0xffffffc0L -#define UVD_DBW_MACRO_TILE_CONFIG__CHROMA_INVERT_BANK_MASK__SI 0x00000030L -#define UVD_DBW_MACRO_TILE_CONFIG__CHROMA_INVERT_CHAN_MASK__SI 0x00000040L -#define UVD_DBW_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_6_MASK__SI 0x00000001L -#define UVD_DBW_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_7_MASK__SI 0x00000002L -#define UVD_DBW_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_8_MASK__SI 0x00000004L -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_10_SEL_MASK__SI 0x000f0000L -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_11_SEL_MASK__SI 0x00f00000L -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_12_SEL_MASK__SI 0x0f000000L -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_13_SEL_MASK__SI 0xf0000000L -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_6_SEL_MASK__SI 0x0000000fL -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_7_SEL_MASK__SI 0x000000f0L -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_8_SEL_MASK__SI 0x00000f00L -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_9_SEL_MASK__SI 0x0000f000L -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_14_SEL_MASK__SI 0x0000000fL -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_15_SEL_MASK__SI 0x000000f0L -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_16_SEL_MASK__SI 0x00000f00L -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_17_SEL_MASK__SI 0x0000f000L -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_18_SEL_MASK__SI 0x000f0000L -#define UVD_DB_MACRO_TILE_CONFIG__CHROMA_INVERT_BANK_MASK__SI 0x00000030L -#define UVD_DB_MACRO_TILE_CONFIG__CHROMA_INVERT_CHAN_MASK__SI 0x00000040L -#define UVD_DB_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_6_MASK__SI 0x00000001L -#define UVD_DB_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_7_MASK__SI 0x00000002L -#define UVD_DB_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_8_MASK__SI 0x00000004L -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_10_SEL_MASK__SI 0x000f0000L -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_11_SEL_MASK__SI 0x00f00000L -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_12_SEL_MASK__SI 0x0f000000L -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_13_SEL_MASK__SI 0xf0000000L -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_6_SEL_MASK__SI 0x0000000fL -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_7_SEL_MASK__SI 0x000000f0L -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_8_SEL_MASK__SI 0x00000f00L -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_9_SEL_MASK__SI 0x0000f000L -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_14_SEL_MASK__SI 0x0000000fL -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_15_SEL_MASK__SI 0x000000f0L -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_16_SEL_MASK__SI 0x00000f00L -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_17_SEL_MASK__SI 0x0000f000L -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_18_SEL_MASK__SI 0x000f0000L -#define UVD_DEBUG_CTRL__SEL0_MASK__SI 0x0000000fL -#define UVD_DEBUG_CTRL__SEL1_MASK__SI 0x00000f00L -#define UVD_DEBUG_CTRL__SWAP_MODE_MASK__SI 0xc0000000L -#define UVD_DEBUG_SCRATCH__DATA_00_MASK__SI 0x00000001L -#define UVD_DEBUG_SCRATCH__DATA_01_MASK__SI 0x00000002L -#define UVD_DEBUG_SCRATCH__DATA_02_MASK__SI 0x00000004L -#define UVD_DEBUG_SCRATCH__DATA_03_MASK__SI 0x00000008L -#define UVD_DEBUG_SCRATCH__DATA_04_MASK__SI 0x00000010L -#define UVD_DEBUG_SCRATCH__DATA_05_MASK__SI 0x00000020L -#define UVD_DEBUG_SCRATCH__DATA_06_MASK__SI 0x00000040L -#define UVD_DEBUG_SCRATCH__DATA_07_MASK__SI 0x00000080L -#define UVD_DEBUG_SCRATCH__DATA_08_MASK__SI 0x00000100L -#define UVD_DEBUG_SCRATCH__DATA_09_MASK__SI 0x00000200L -#define UVD_DEBUG_SCRATCH__DATA_10_MASK__SI 0x00000400L -#define UVD_DEBUG_SCRATCH__DATA_11_MASK__SI 0x00000800L -#define UVD_DEBUG_SCRATCH__DATA_12_MASK__SI 0x00001000L -#define UVD_DEBUG_SCRATCH__DATA_13_MASK__SI 0x00002000L -#define UVD_DEBUG_SCRATCH__DATA_14_MASK__SI 0x00004000L -#define UVD_DEBUG_SCRATCH__DATA_15_MASK__SI 0x00008000L -#define UVD_DEBUG_SCRATCH__DATA_16_MASK__SI 0x00010000L -#define UVD_DEBUG_SCRATCH__DATA_17_MASK__SI 0x00020000L -#define UVD_DEBUG_SCRATCH__DATA_18_MASK__SI 0x00040000L -#define UVD_DEBUG_SCRATCH__DATA_19_MASK__SI 0x00080000L -#define UVD_DEBUG_SCRATCH__DATA_20_MASK__SI 0x00100000L -#define UVD_DEBUG_SCRATCH__DATA_21_MASK__SI 0x00200000L -#define UVD_DEBUG_SCRATCH__DATA_22_MASK__SI 0x00400000L -#define UVD_DEBUG_SCRATCH__DATA_23_MASK__SI 0x00800000L -#define UVD_DEBUG_SCRATCH__DATA_24_MASK__SI 0x01000000L -#define UVD_DEBUG_SCRATCH__DATA_25_MASK__SI 0x02000000L -#define UVD_DEBUG_SCRATCH__DATA_26_MASK__SI 0x04000000L -#define UVD_DEBUG_SCRATCH__DATA_27_MASK__SI 0x08000000L -#define UVD_DEBUG_SCRATCH__DATA_28_MASK__SI 0x10000000L -#define UVD_DEBUG_SCRATCH__DATA_29_MASK__SI 0x20000000L -#define UVD_DEBUG_SCRATCH__DATA_30_MASK__SI 0x40000000L -#define UVD_DEBUG_SCRATCH__DATA_31_MASK__SI 0x80000000L -#define UVD_DRM_CMD__CMD_MASK__SI 0xffffffffL -#define UVD_DRM_CNTDAT0__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_CNTDAT1__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_CNTDAT2__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_CNTDAT3__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_CNTKEY0__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_CNTKEY1__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_CNTKEY2__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_CNTKEY3__CNT_MASK__SI 0xffffffffL -#define UVD_DRM_KEY0__KEY_MASK__SI 0xffffffffL -#define UVD_DRM_KEY1__KEY_MASK__SI 0xffffffffL -#define UVD_DRM_KEY2__KEY_MASK__SI 0xffffffffL -#define UVD_DRM_KEY3__KEY_MASK__SI 0xffffffffL -#define UVD_DRM_OFFSET__OFFSET_MASK__SI 0xffffffffL -#define UVD_DRV_FW_MSG__MSG_MASK__SI 0xffffffffL -#define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK__SI 0xffff0000L -#define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK__SI 0x0000ffffL -#define UVD_ENGINE_CNTL__ENGINE_START_MASK__SI 0x00000001L -#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK__SI 0x00000002L -#define UVD_FCS_AVP_SYS_INT_ACK__BLOCK_ACK_MASK__SI 0x00000002L -#define UVD_FCS_AVP_SYS_INT_ACK__CONTEXT_IDLE_MASK__SI 0x00000004L -#define UVD_FCS_AVP_SYS_INT_ACK__CTL_ACK_MASK__SI 0x00000001L -#define UVD_FCS_AVP_SYS_INT_ACK__EXT_INT_MASK__SI 0x00000008L -#define UVD_FCS_AVP_SYS_INT_ACK__NEW_RL_MASK__SI 0x00000010L -#define UVD_FCS_AVP_SYS_INT_EN__BLOCK_ACK_MASK__SI 0x00000002L -#define UVD_FCS_AVP_SYS_INT_EN__CONTEXT_IDLE_MASK__SI 0x00000004L -#define UVD_FCS_AVP_SYS_INT_EN__CTL_ACK_MASK__SI 0x00000001L -#define UVD_FCS_AVP_SYS_INT_EN__EXT_INT_MASK__SI 0x00000008L -#define UVD_FCS_AVP_SYS_INT_EN__NEW_RL_MASK__SI 0x00000010L -#define UVD_FCS_AVP_SYS_INT_STAT__BLOCK_ACK_MASK__SI 0x00000002L -#define UVD_FCS_AVP_SYS_INT_STAT__CONTEXT_IDLE_MASK__SI 0x00000004L -#define UVD_FCS_AVP_SYS_INT_STAT__CTL_ACK_MASK__SI 0x00000001L -#define UVD_FCS_AVP_SYS_INT_STAT__EXT_INT_MASK__SI 0x00000008L -#define UVD_FCS_AVP_SYS_INT_STAT__NEW_RL_MASK__SI 0x00000010L -#define UVD_FCS_AVP_VCPU_INT_ACK__BLOCK_ACK_MASK__SI 0x00000002L -#define UVD_FCS_AVP_VCPU_INT_ACK__CONTEXT_IDLE_MASK__SI 0x00000004L -#define UVD_FCS_AVP_VCPU_INT_ACK__CTL_ACK_MASK__SI 0x00000001L -#define UVD_FCS_AVP_VCPU_INT_ACK__EXT_INT_MASK__SI 0x00000008L -#define UVD_FCS_AVP_VCPU_INT_ACK__NEW_RL_MASK__SI 0x00000010L -#define UVD_FCS_AVP_VCPU_INT_EN__BLOCK_ACK_MASK__SI 0x00000002L -#define UVD_FCS_AVP_VCPU_INT_EN__CONTEXT_IDLE_MASK__SI 0x00000004L -#define UVD_FCS_AVP_VCPU_INT_EN__CTL_ACK_MASK__SI 0x00000001L -#define UVD_FCS_AVP_VCPU_INT_EN__EXT_INT_MASK__SI 0x00000008L -#define UVD_FCS_AVP_VCPU_INT_EN__NEW_RL_MASK__SI 0x00000010L -#define UVD_FCS_AVP_VCPU_INT_STAT__BLOCK_ACK_MASK__SI 0x00000002L -#define UVD_FCS_AVP_VCPU_INT_STAT__CONTEXT_IDLE_MASK__SI 0x00000004L -#define UVD_FCS_AVP_VCPU_INT_STAT__CTL_ACK_MASK__SI 0x00000001L -#define UVD_FCS_AVP_VCPU_INT_STAT__EXT_INT_MASK__SI 0x00000008L -#define UVD_FCS_AVP_VCPU_INT_STAT__NEW_RL_MASK__SI 0x00000010L -#define UVD_FCS_CTRL__ADM_MODE_MASK__SI 0x00000001L -#define UVD_FCS_STATUS__STATUS_MASK__SI 0xffffffffL -#define UVD_FCS_SYS_INT_ACK__GPF_MASK__SI 0x00000080L -#define UVD_FCS_SYS_INT_ACK__HOST_CXW_MASK__SI 0x00000020L -#define UVD_FCS_SYS_INT_ACK__IDLE_CXW_MASK__SI 0x00000040L -#define UVD_FCS_SYS_INT_ACK__NEW_RL_MASK__SI 0x00000100L -#define UVD_FCS_SYS_INT_ACK__RBC_PRIV_FAULT_IDCT_MASK__SI 0x00000010L -#define UVD_FCS_SYS_INT_ACK__RBC_PRIV_FAULT_MASK__SI 0x00000008L -#define UVD_FCS_SYS_INT_ACK__SEMA_SIG_INC_TIMEOUT_MASK__SI 0x00000004L -#define UVD_FCS_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_MASK__SI 0x00000002L -#define UVD_FCS_SYS_INT_ACK__SEMA_WAIT_INC_TIMEOUT_MASK__SI 0x00000001L -#define UVD_FCS_SYS_INT_EN__GPF_MASK__SI 0x00000080L -#define UVD_FCS_SYS_INT_EN__HOST_CXW_MASK__SI 0x00000020L -#define UVD_FCS_SYS_INT_EN__IDLE_CXW_MASK__SI 0x00000040L -#define UVD_FCS_SYS_INT_EN__NEW_RL_MASK__SI 0x00000100L -#define UVD_FCS_SYS_INT_EN__RBC_PRIV_FAULT_IDCT_MASK__SI 0x00000010L -#define UVD_FCS_SYS_INT_EN__RBC_PRIV_FAULT_MASK__SI 0x00000008L -#define UVD_FCS_SYS_INT_EN__SEMA_SIG_INC_TIMEOUT_MASK__SI 0x00000004L -#define UVD_FCS_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_MASK__SI 0x00000002L -#define UVD_FCS_SYS_INT_EN__SEMA_WAIT_INC_TIMEOUT_MASK__SI 0x00000001L -#define UVD_FCS_SYS_INT_STAT__GPF_MASK__SI 0x00000080L -#define UVD_FCS_SYS_INT_STAT__HOST_CXW_MASK__SI 0x00000020L -#define UVD_FCS_SYS_INT_STAT__IDLE_CXW_MASK__SI 0x00000040L -#define UVD_FCS_SYS_INT_STAT__NEW_RL_MASK__SI 0x00000100L -#define UVD_FCS_SYS_INT_STAT__RBC_PRIV_FAULT_IDCT_MASK__SI 0x00000010L -#define UVD_FCS_SYS_INT_STAT__RBC_PRIV_FAULT_MASK__SI 0x00000008L -#define UVD_FCS_SYS_INT_STAT__SEMA_SIG_INC_TIMEOUT_MASK__SI 0x00000004L -#define UVD_FCS_SYS_INT_STAT__SEMA_WAIT_FAULT_TIMEOUT_MASK__SI 0x00000002L -#define UVD_FCS_SYS_INT_STAT__SEMA_WAIT_INC_TIMEOUT_MASK__SI 0x00000001L -#define UVD_FCS_VCPU_INT_ACK__GPF_MASK__SI 0x00000080L -#define UVD_FCS_VCPU_INT_ACK__HOST_CXW_MASK__SI 0x00000020L -#define UVD_FCS_VCPU_INT_ACK__IDLE_CXW_MASK__SI 0x00000040L -#define UVD_FCS_VCPU_INT_ACK__NEW_RL_MASK__SI 0x00000100L -#define UVD_FCS_VCPU_INT_ACK__RBC_PRIV_FAULT_IDCT_MASK__SI 0x00000010L -#define UVD_FCS_VCPU_INT_ACK__RBC_PRIV_FAULT_MASK__SI 0x00000008L -#define UVD_FCS_VCPU_INT_ACK__SEMA_SIG_INC_TIMEOUT_MASK__SI 0x00000004L -#define UVD_FCS_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_MASK__SI 0x00000002L -#define UVD_FCS_VCPU_INT_ACK__SEMA_WAIT_INC_TIMEOUT_MASK__SI 0x00000001L -#define UVD_FCS_VCPU_INT_EN__GPF_MASK__SI 0x00000080L -#define UVD_FCS_VCPU_INT_EN__HOST_CXW_MASK__SI 0x00000020L -#define UVD_FCS_VCPU_INT_EN__IDLE_CXW_MASK__SI 0x00000040L -#define UVD_FCS_VCPU_INT_EN__NEW_RL_MASK__SI 0x00000100L -#define UVD_FCS_VCPU_INT_EN__RBC_PRIV_FAULT_IDCT_MASK__SI 0x00000010L -#define UVD_FCS_VCPU_INT_EN__RBC_PRIV_FAULT_MASK__SI 0x00000008L -#define UVD_FCS_VCPU_INT_EN__SEMA_SIG_INC_TIMEOUT_MASK__SI 0x00000004L -#define UVD_FCS_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_MASK__SI 0x00000002L -#define UVD_FCS_VCPU_INT_EN__SEMA_WAIT_INC_TIMEOUT_MASK__SI 0x00000001L -#define UVD_FCS_VCPU_INT_STAT__GPF_MASK__SI 0x00000080L -#define UVD_FCS_VCPU_INT_STAT__HOST_CXW_MASK__SI 0x00000020L -#define UVD_FCS_VCPU_INT_STAT__IDLE_CXW_MASK__SI 0x00000040L -#define UVD_FCS_VCPU_INT_STAT__NEW_RL_MASK__SI 0x00000100L -#define UVD_FCS_VCPU_INT_STAT__RBC_PRIV_FAULT_IDCT_MASK__SI 0x00000010L -#define UVD_FCS_VCPU_INT_STAT__RBC_PRIV_FAULT_MASK__SI 0x00000008L -#define UVD_FCS_VCPU_INT_STAT__SEMA_SIG_INC_TIMEOUT_MASK__SI 0x00000004L -#define UVD_FCS_VCPU_INT_STAT__SEMA_WAIT_FAULT_TIMEOUT_MASK__SI 0x00000002L -#define UVD_FCS_VCPU_INT_STAT__SEMA_WAIT_INC_TIMEOUT_MASK__SI 0x00000001L -#define UVD_FW_BYTECNT__BYTECNT_MASK__SI 0xffffffffL -#define UVD_FW_DEBUG_ADDR__DEBUG_ADDR_MASK__SI 0x0000001fL -#define UVD_FW_DEBUG_DATA__DEBUG_DATA_MASK__SI 0xffffffffL -#define UVD_FW_DRV_MSG_ACK__ACK_MASK__SI 0x00000001L -#define UVD_FW_EXP_RESULT0__RESULT0_MASK__SI 0xffffffffL -#define UVD_FW_EXP_RESULT1__RESULT1_MASK__SI 0xffffffffL -#define UVD_FW_EXP_RESULT2__RESULT2_MASK__SI 0xffffffffL -#define UVD_FW_EXP_RESULT3__RESULT3_MASK__SI 0xffffffffL -#define UVD_FW_LENGTH__LENGTH_MASK__SI 0xffffffffL -#define UVD_FW_NONCE0__NONCE0_MASK__SI 0xffffffffL -#define UVD_FW_NONCE1__NONCE1_MASK__SI 0xffffffffL -#define UVD_FW_NONCE2__NONCE2_MASK__SI 0xffffffffL -#define UVD_FW_NONCE3__NONCE3_MASK__SI 0xffffffffL -#define UVD_FW_PERIODIC_CNTL__BUSY_EN_MASK__SI 0x00000004L -#define UVD_FW_PERIODIC_CNTL__RATE_MASK__SI 0x00000700L -#define UVD_FW_PERIODIC_CNTL__TIMER_DEC_PERIOD_MASK__SI 0x00000018L -#define UVD_FW_PERIODIC_CNTL__TIMER_DEFAULT_MASK__SI 0xffff8000L -#define UVD_FW_PERIODIC_CNTL__TIMER_EN_MASK__SI 0x00000002L -#define UVD_FW_SELF_RECOVERY_CNTL__FW_SLF_RCV_RETRY_MASK__SI 0x00000e00L -#define UVD_FW_SELF_RECOVERY_CNTL__FW_WATCHDOG_TIMER_MASK__SI 0x0000001fL -#define UVD_FW_START__KEYSEL_MASK__SI 0xffffffffL -#define UVD_FW_STATS__NUM_RUNS_MASK__SI 0xffffffffL -#define UVD_FW_STATUS__ACTIVE_MASK__SI 0x00000002L -#define UVD_FW_STATUS__BUSY_MASK__SI 0x00000001L -#define UVD_FW_STATUS__DONE_MASK__SI 0x00000100L -#define UVD_FW_STATUS__EFUSE_CFG_MASK__SI 0xff000000L -#define UVD_FW_STATUS__EFUSE_DROP_MASK__SI 0x00800000L -#define UVD_FW_STATUS__EFUSE_ERR_MASK__SI 0x00400000L -#define UVD_FW_STATUS__EFUSE_RDY_MASK__SI 0x00200000L -#define UVD_FW_STATUS__FAIL_MASK__SI 0x00020000L -#define UVD_FW_STATUS__INVALID_0_PADDING_MASK__SI 0x00080000L -#define UVD_FW_STATUS__INVALID_LEN_MASK__SI 0x00040000L -#define UVD_FW_STATUS__INVALID_NONCE_MASK__SI 0x00100000L -#define UVD_FW_STATUS__PASS_MASK__SI 0x00010000L -#define UVD_FW_STATUS__SEND_EFUSE_REQ_MASK__SI 0x00000004L -#define UVD_GPCOM_SYS_CMD__CMD_MASK__SI 0x7ffffffeL -#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK__SI 0x00000001L -#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK__SI 0x80000000L -#define UVD_GPCOM_SYS_DATA0__DATA0_MASK__SI 0xffffffffL -#define UVD_GPCOM_SYS_DATA1__DATA1_MASK__SI 0xffffffffL -#define UVD_GPCOM_VCPU_CMD__CMD_MASK__SI 0x7ffffffeL -#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK__SI 0x00000001L -#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK__SI 0x80000000L -#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK__SI 0xffffffffL -#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK__SI 0xffffffffL -#define UVD_GPF_STATUS__UMC_RD_MASK__SI 0x000000c0L -#define UVD_GPF_STATUS__UMC_WR_MASK__SI 0x00000030L -#define UVD_GPF_STATUS__UVD_RD_MASK__SI 0x0000000cL -#define UVD_GPF_STATUS__UVD_WR_MASK__SI 0x00000003L -#define UVD_GP_SCRATCH0__DATA_MASK__SI 0xffffffffL -#define UVD_GP_SCRATCH1__DATA_MASK__SI 0xffffffffL -#define UVD_GP_SCRATCH2__DATA_MASK__SI 0xffffffffL -#define UVD_GP_SCRATCH3__DATA_MASK__SI 0xffffffffL -#define UVD_GP_SCRATCH4__DATA_MASK__SI 0xffffffffL -#define UVD_GP_SCRATCH5__DATA_MASK__SI 0xffffffffL -#define UVD_GP_SCRATCH6__DATA_MASK__SI 0xffffffffL -#define UVD_GP_SCRATCH7__DATA_MASK__SI 0xffffffffL -#define UVD_HEIGHT__DUM_MASK__SI 0xffffffffL -#define UVD_IDLE_COOKIE_ID__ID_MASK__SI 0x0fffffffL -#define UVD_JOB_DONE__JOB_DONE_MASK__SI 0x00000003L -#define UVD_JOB_START__JOB_START_MASK__SI 0x00000001L -#define UVD_LBSI_ADDR_0__ADDR_MASK__SI 0xffffffc0L -#define UVD_LBSI_ADDR_0__BYTE_SWAP_MASK__SI 0x00000003L -#define UVD_LBSI_ADDR_0__FILL_MASK__SI 0x00000038L -#define UVD_LBSI_ADDR_0__VADDR_MASK__SI 0x00000004L -#define UVD_LBSI_ADDR_1__ADDR_MASK__SI 0xffffffc0L -#define UVD_LBSI_ADDR_1__BYTE_SWAP_MASK__SI 0x00000003L -#define UVD_LBSI_ADDR_1__FILL_MASK__SI 0x00000038L -#define UVD_LBSI_ADDR_1__VADDR_MASK__SI 0x00000004L -#define UVD_LBSI_BURST_LEN__BURST_LEN_MASK__SI 0xfff00000L -#define UVD_LBSI_CONFIG__CONFIG_MASK__SI 0xffffffffL -#define UVD_LBSI_CURR_ADDR__CURR_ADDR_MASK__SI 0xffffffc0L -#define UVD_LBSI_DRM_FLUSH_CTL_STATUS__LBSI_DRM_VCPU_RDY_TO_RST_MASK__SI 0x00000001L -#define UVD_LBSI_DRM_FLUSH_CTL_STATUS__LBSI_DRM_VCPU_STOP_REQ_MASK__SI 0x00000002L -#define UVD_LBSI_LEN_0__LEN_MASK__SI 0x00ffffffL -#define UVD_LBSI_LEN_0__STAT_0_MASK__SI 0x0f000000L -#define UVD_LBSI_LEN_0__STAT_1_MASK__SI 0xf0000000L -#define UVD_LBSI_LEN_1__LEN_MASK__SI 0x00ffffffL -#define UVD_LBSI_LEN_1__STAT_0_MASK__SI 0x0f000000L -#define UVD_LBSI_LEN_1__STAT_1_MASK__SI 0xf0000000L -#define UVD_LBSI_PF_BUFF_COUNT__ACTIVE_STREAM_MASK__SI 0x04000000L -#define UVD_LBSI_PF_BUFF_COUNT__NUM_BUFFERS_MASK__SI 0x08000000L -#define UVD_LBSI_PF_BUFF_COUNT__PEND_COUNT_MASK__SI 0xf0000000L -#define UVD_LBSI_PF_BUFF_COUNT__PF_BYTE_COUNT_MASK__SI 0x01ffffffL -#define UVD_LBSI_RE_WAIT_COUNT__COUNT_MASK__SI 0xffffffffL -#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK__SI 0x000000f0L -#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK__SI 0x00000f00L -#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK__SI 0x0000000fL -#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK__SI 0x0000f000L -#define UVD_LMI_ARB_CTRL__CM_RD_WAIT_EN_MASK__SI 0x00000200L -#define UVD_LMI_ARB_CTRL__CM_WR_WAIT_EN_MASK__SI 0x02000000L -#define UVD_LMI_ARB_CTRL__DBW_WR_WAIT_EN_MASK__SI 0x08000000L -#define UVD_LMI_ARB_CTRL__DB_RD_WAIT_EN_MASK__SI 0x00000400L -#define UVD_LMI_ARB_CTRL__DB_WR_WAIT_EN_MASK__SI 0x04000000L -#define UVD_LMI_ARB_CTRL__IDCT_RD_WAIT_EN_MASK__SI 0x00000800L -#define UVD_LMI_ARB_CTRL__IT_RD_WAIT_EN_MASK__SI 0x00000100L -#define UVD_LMI_ARB_CTRL__IT_WR_WAIT_EN_MASK__SI 0x01000000L -#define UVD_LMI_ARB_CTRL__LBSI_RD_WAIT_EN_MASK__SI 0x00002000L -#define UVD_LMI_ARB_CTRL__MPC_RD_WAIT_EN_MASK__SI 0x00001000L -#define UVD_LMI_ARB_CTRL__RBC_RD_WAIT_EN_MASK__SI 0x00004000L -#define UVD_LMI_ARB_CTRL__RD_WAIT_TIMER_MASK__SI 0x000000ffL -#define UVD_LMI_ARB_CTRL__WR_WAIT_TIMER_MASK__SI 0x00ff0000L -#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK__SI 0x0000ff00L -#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK__SI 0xffff0000L -#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK__SI 0x000000ffL -#define UVD_LMI_AXI_ERR_STATUS__AXI_ERR_ADDR_LSBS_MASK__SI 0x00000070L -#define UVD_LMI_AXI_ERR_STATUS__AXI_ERR_AWRITE_MASK__SI 0x00000080L -#define UVD_LMI_AXI_ERR_STATUS__AXI_ERR_LEN_MASK__SI 0x0000000fL -#define UVD_LMI_CACHE_CTRL__CM_EN_MASK__SI 0x00000004L -#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK__SI 0x00000008L -#define UVD_LMI_CACHE_CTRL__IT_EN_MASK__SI 0x00000001L -#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK__SI 0x00000002L -#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK__SI 0x00000010L -#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK__SI 0x00000020L -#define UVD_LMI_CLEAN_STATUS__CM_RD_MASK__SI 0x00000002L -#define UVD_LMI_CLEAN_STATUS__CM_WR_MASK__SI 0x00020000L -#define UVD_LMI_CLEAN_STATUS__DBW_WR_MASK__SI 0x00080000L -#define UVD_LMI_CLEAN_STATUS__DB_RD_MASK__SI 0x00000004L -#define UVD_LMI_CLEAN_STATUS__DB_WR_MASK__SI 0x00040000L -#define UVD_LMI_CLEAN_STATUS__FWV_RD_MASK__SI 0x00000100L -#define UVD_LMI_CLEAN_STATUS__IDCT_RD_MASK__SI 0x00000008L -#define UVD_LMI_CLEAN_STATUS__IT_RD_MASK__SI 0x00000001L -#define UVD_LMI_CLEAN_STATUS__IT_WR_MASK__SI 0x00010000L -#define UVD_LMI_CLEAN_STATUS__LBSI_RD_MASK__SI 0x00000020L -#define UVD_LMI_CLEAN_STATUS__MPC_RD_MASK__SI 0x00000010L -#define UVD_LMI_CLEAN_STATUS__RBC_RD_MASK__SI 0x00000040L -#define UVD_LMI_CLEAN_STATUS__SPH_WR_MASK__SI 0x00200000L -#define UVD_LMI_CLEAN_STATUS__VCPU_RD_MASK__SI 0x00000080L -#define UVD_LMI_CLEAN_STATUS__VCPU_WR_MASK__SI 0x00100000L -#define UVD_LMI_CRC0__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CRC1__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CRC2__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CRC3__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CRC4__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CRC5__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CRC6__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CRC7__CRC32_MASK__SI 0xffffffffL -#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK__SI 0x00000004L -#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK__SI 0x00000080L -#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK__SI 0x00000008L -#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK__SI 0x00000070L -#define UVD_LMI_CTRL2__SPH_DIS_MASK__SI 0x00000001L -#define UVD_LMI_CTRL2__STALL_ARB_MASK__SI 0x00000002L -#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK__SI 0x00000100L -#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK__SI 0x00000800L -#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK__SI 0x00400000L -#define UVD_LMI_CTRL__CRC_RESET_MASK__SI 0x00004000L -#define UVD_LMI_CTRL__CRC_SEL_MASK__SI 0x000f8000L -#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK__SI 0x00002000L -#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK__SI 0x00800000L -#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK__SI 0x01000000L -#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK__SI 0x00100000L -#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK__SI 0x02000000L -#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK__SI 0x00001000L -#define UVD_LMI_CTRL__REQ_MODE_MASK__SI 0x00000200L -#define UVD_LMI_CTRL__RFU_MASK__SI 0xfc000000L -#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK__SI 0x00200000L -#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK__SI 0x00000100L -#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK__SI 0x000000ffL -#define UVD_LMI_EXT40_ADDR__ADDR_MASK__SI 0x000000ffL -#define UVD_LMI_EXT40_ADDR__INDEX_MASK__SI 0x000f0000L -#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK__SI 0x80000000L -#define UVD_LMI_ISOC_CTRL__CM_EN_MASK__SI 0x00000020L -#define UVD_LMI_ISOC_CTRL__DB_EN_MASK__SI 0x00000040L -#define UVD_LMI_ISOC_CTRL__FWV_EN_MASK__SI 0x00001000L -#define UVD_LMI_ISOC_CTRL__IDCT_EN_MASK__SI 0x00000080L -#define UVD_LMI_ISOC_CTRL__IT_EN_MASK__SI 0x00000010L -#define UVD_LMI_ISOC_CTRL__LBSI_EN_MASK__SI 0x00000200L -#define UVD_LMI_ISOC_CTRL__MPC_EN_MASK__SI 0x00000100L -#define UVD_LMI_ISOC_CTRL__RANGE1_EN_MASK__SI 0x00000001L -#define UVD_LMI_ISOC_CTRL__RANGE2_EN_MASK__SI 0x00000002L -#define UVD_LMI_ISOC_CTRL__RBC_EN_MASK__SI 0x00000400L -#define UVD_LMI_ISOC_CTRL__VCPU_EN_MASK__SI 0x00000800L -#define UVD_LMI_ISOC_PREF_BASE1__ADDR_MASK__SI 0xffffffffL -#define UVD_LMI_ISOC_PREF_BASE2__ADDR_MASK__SI 0xffffffffL -#define UVD_LMI_ISOC_PREF_LIMIT1__ADDR_MASK__SI 0xffffffffL -#define UVD_LMI_ISOC_PREF_LIMIT2__ADDR_MASK__SI 0xffffffffL -#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK__SI 0x000000ffL -#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK__SI 0x0000ff00L -#define UVD_LMI_LAT_CTRL__AVG_START_MASK__SI 0x00000400L -#define UVD_LMI_LAT_CTRL__MAX_START_MASK__SI 0x00000100L -#define UVD_LMI_LAT_CTRL__MIN_START_MASK__SI 0x00000200L -#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK__SI 0x00000800L -#define UVD_LMI_LAT_CTRL__SCALE_MASK__SI 0x000000ffL -#define UVD_LMI_LAT_CTRL__SKIP_MASK__SI 0x000f0000L -#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK__SI 0x003f0000L -#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK__SI 0x3f000000L -#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK__SI 0x0000003fL -#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK__SI 0x00003f00L -#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK__SI 0x0000ffffL -#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK__SI 0xffffffffL -#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK__SI 0x00001f00L -#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK__SI 0x00000003L -#define UVD_LMI_RD_BURST_CTRL__CM_MASK__SI 0x000000f0L -#define UVD_LMI_RD_BURST_CTRL__DB_MASK__SI 0x00000f00L -#define UVD_LMI_RD_BURST_CTRL__IDCT_MASK__SI 0x0000f000L -#define UVD_LMI_RD_BURST_CTRL__IT_MASK__SI 0x0000000fL -#define UVD_LMI_RD_BURST_CTRL__LBSI_MASK__SI 0x00f00000L -#define UVD_LMI_RD_BURST_CTRL__MPC_MASK__SI 0x000f0000L -#define UVD_LMI_RD_BURST_CTRL__RBC_MASK__SI 0x0f000000L -#define UVD_LMI_SPH__ADDR_MASK__SI 0x0fffffffL -#define UVD_LMI_SPH__STS_MASK__SI 0x30000000L -#define UVD_LMI_SPH__STS_OVERFLOW_MASK__SI 0x80000000L -#define UVD_LMI_SPH__STS_VALID_MASK__SI 0x40000000L -#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK__SI 0x00001000L -#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK__SI 0x00002000L -#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK__SI 0x00000080L -#define UVD_LMI_STATUS__READ_CLEAN_MASK__SI 0x00000001L -#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK__SI 0x00000100L -#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK__SI 0x00000800L -#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK__SI 0x00000010L -#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK__SI 0x00000200L -#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK__SI 0x00000400L -#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK__SI 0x00000020L -#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK__SI 0x00000040L -#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK__SI 0x00000008L -#define UVD_LMI_STATUS__WRITE_CLEAN_MASK__SI 0x00000002L -#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK__SI 0x00000004L -#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK__SI 0x00000c00L -#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK__SI 0x000c0000L -#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK__SI 0x03000000L -#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK__SI 0x0000c000L -#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK__SI 0x00030000L -#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK__SI 0x0000000cL -#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK__SI 0x00003000L -#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK__SI 0x00c00000L -#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK__SI 0x00000003L -#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK__SI 0x00000030L -#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK__SI 0x0c000000L -#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK__SI 0x000000c0L -#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK__SI 0x00000300L -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK__SI 0x00000002L -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK__SI 0x0000003cL -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK__SI 0x00000200L -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK__SI 0x00003c00L -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK__SI 0x00020000L -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK__SI 0x003c0000L -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK__SI 0x02000000L -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK__SI 0x3c000000L -#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK__SI 0x00000001L -#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK__SI 0x00000100L -#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK__SI 0x00010000L -#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK__SI 0x01000000L -#define UVD_LMI_UVD_SWAP__CM_RD_MASK__SI 0x0000000cL -#define UVD_LMI_UVD_SWAP__CM_WR_MASK__SI 0x00300000L -#define UVD_LMI_UVD_SWAP__DBW_WR_MASK__SI 0x03000000L -#define UVD_LMI_UVD_SWAP__DB_RD_MASK__SI 0x00000030L -#define UVD_LMI_UVD_SWAP__DB_WR_MASK__SI 0x00c00000L -#define UVD_LMI_UVD_SWAP__FWV_RD_MASK__SI 0x00030000L -#define UVD_LMI_UVD_SWAP__IDCT_RD_MASK__SI 0x000000c0L -#define UVD_LMI_UVD_SWAP__IT_RD_MASK__SI 0x00000003L -#define UVD_LMI_UVD_SWAP__IT_WR_MASK__SI 0x000c0000L -#define UVD_LMI_UVD_SWAP__LBSI_RD_MASK__SI 0x00000c00L -#define UVD_LMI_UVD_SWAP__MPC_RD_MASK__SI 0x00000300L -#define UVD_LMI_UVD_SWAP__RBC_RD_MASK__SI 0x00003000L -#define UVD_LMI_UVD_SWAP__VCPU_RD_MASK__SI 0x0000c000L -#define UVD_LMI_UVD_SWAP__VCPU_WR_MASK__SI 0x0c000000L -#define UVD_LMI_VCPU_VM1__ENABLE_MASK__SI 0x80000000L -#define UVD_LMI_VCPU_VM1__LOWER_RANGE_MASK__SI 0x00000fffL -#define UVD_LMI_VCPU_VM1__UPPER_RANGE_MASK__SI 0x00fff000L -#define UVD_LMI_VCPU_VM__ENABLE_MASK__SI 0x80000000L -#define UVD_LMI_VCPU_VM__LOWER_RANGE_MASK__SI 0x00000fffL -#define UVD_LMI_VCPU_VM__UPPER_RANGE_MASK__SI 0x00fff000L -#define UVD_LMI_VM_CTRL__CM_VM_MASK__SI 0x00000002L -#define UVD_LMI_VM_CTRL__CSM_VM_MASK__SI 0x00000080L -#define UVD_LMI_VM_CTRL__DBW_VM_MASK__SI 0x00000400L -#define UVD_LMI_VM_CTRL__DB_VM_MASK__SI 0x00000010L -#define UVD_LMI_VM_CTRL__IB_VM_MASK__SI 0x00000040L -#define UVD_LMI_VM_CTRL__IT_VM_MASK__SI 0x00000004L -#define UVD_LMI_VM_CTRL__MP_VM_MASK__SI 0x00000008L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_CSM_MASK__SI 0x00020000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_DBW_MASK__SI 0x00080000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_IB_MASK__SI 0x02000000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_LBSI_MASK__SI 0x00100000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_RB_MASK__SI 0x00400000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_RB_RPTR_MASK__SI 0x01000000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_RB_WR_MASK__SI 0x00800000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_UDEC_MASK__SI 0x00040000L -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_VCPU_MASK__SI 0x00010000L -#define UVD_LMI_VM_CTRL__RB_RPTR_VM_MASK__SI 0x00000800L -#define UVD_LMI_VM_CTRL__RB_VM_MASK__SI 0x00000020L -#define UVD_LMI_VM_CTRL__RB_WR_VM_MASK__SI 0x00000100L -#define UVD_LMI_VM_CTRL__VCPU_VM_MASK__SI 0x00000001L -#define UVD_LMI_WR_BURST_CTRL__CM_MASK__SI 0x000000f0L -#define UVD_LMI_WR_BURST_CTRL__DBW_MASK__SI 0x0000f000L -#define UVD_LMI_WR_BURST_CTRL__DB_MASK__SI 0x00000f00L -#define UVD_LMI_WR_BURST_CTRL__IT_MASK__SI 0x0000000fL -#define UVD_LMI_WR_COMB_CTRL__CM_MAX_MASK__SI 0x00007000L -#define UVD_LMI_WR_COMB_CTRL__CM_TIMER_MASK__SI 0x00000f00L -#define UVD_LMI_WR_COMB_CTRL__DBW_MAX_MASK__SI 0x70000000L -#define UVD_LMI_WR_COMB_CTRL__DBW_TIMER_MASK__SI 0x0f000000L -#define UVD_LMI_WR_COMB_CTRL__DB_MAX_MASK__SI 0x00700000L -#define UVD_LMI_WR_COMB_CTRL__DB_TIMER_MASK__SI 0x000f0000L -#define UVD_LMI_WR_COMB_CTRL__IT_MAX_MASK__SI 0x00000070L -#define UVD_LMI_WR_COMB_CTRL__IT_TIMER_MASK__SI 0x0000000fL -#define UVD_MACRO_TILE_CONFIG__CHROMA_INVERT_BANK_MASK__SI 0x00000030L -#define UVD_MACRO_TILE_CONFIG__CHROMA_INVERT_CHAN_MASK__SI 0x00000040L -#define UVD_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_6_MASK__SI 0x00000001L -#define UVD_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_7_MASK__SI 0x00000002L -#define UVD_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_8_MASK__SI 0x00000004L -#define UVD_MASTINT_EN__INT_OVERRUN_MASK__SI 0x007ffff0L -#define UVD_MASTINT_EN__OVERRUN_RST_MASK__SI 0x00000001L -#define UVD_MASTINT_EN__SYS_EN_MASK__SI 0x00000004L -#define UVD_MASTINT_EN__VCPU_EN_MASK__SI 0x00000002L -#define UVD_MB_CTL_BUF_BASE__BASE_MASK__SI 0xffffffffL -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_10_SEL_MASK__SI 0x000f0000L -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_11_SEL_MASK__SI 0x00f00000L -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_12_SEL_MASK__SI 0x0f000000L -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_13_SEL_MASK__SI 0xf0000000L -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_6_SEL_MASK__SI 0x0000000fL -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_7_SEL_MASK__SI 0x000000f0L -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_8_SEL_MASK__SI 0x00000f00L -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_9_SEL_MASK__SI 0x0000f000L -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_14_SEL_MASK__SI 0x0000000fL -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_15_SEL_MASK__SI 0x000000f0L -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_16_SEL_MASK__SI 0x00000f00L -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_17_SEL_MASK__SI 0x0000f000L -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_18_SEL_MASK__SI 0x000f0000L -#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK__SI 0xffffffffL -#define UVD_MPC_CHROMA_HIT__CNTR_MASK__SI 0xffffffffL -#define UVD_MPC_CHROMA_SRCH__CNTR_MASK__SI 0xffffffffL -#define UVD_MPC_CNTL__AVE_WEIGHT_MASK__SI 0x00030000L -#define UVD_MPC_CNTL__DBG_MUX_MASK__SI 0x00000700L -#define UVD_MPC_CNTL__PERF_RST_MASK__SI 0x00000040L -#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK__SI 0x00000038L -#define UVD_MPC_CNTL__URGENT_EN_MASK__SI 0x00040000L -#define UVD_MPC_LUMA_HITPEND__CNTR_MASK__SI 0xffffffffL -#define UVD_MPC_LUMA_HIT__CNTR_MASK__SI 0xffffffffL -#define UVD_MPC_LUMA_SRCH__CNTR_MASK__SI 0xffffffffL -#define UVD_MPC_PERF0__MAX_LAT_MASK__SI 0x000003ffL -#define UVD_MPC_PERF1__AVE_LAT_MASK__SI 0x000003ffL -#define UVD_MPC_PITCH__LUMA_PITCH_MASK__SI 0x000007ffL -#define UVD_MPC_REF_BAR0__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR10__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR11__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR12__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR13__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR14__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR15__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR16__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR1__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR2__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR3__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR4__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR5__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR6__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR7__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR8__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_BAR9__ADDR_MASK__SI 0xffffffffL -#define UVD_MPC_REF_PIC_ADDR_CONF__ADDR_40BIT_TRANSLATE_EN_MASK__SI 0x80000000L -#define UVD_MPC_REF_PIC_ADDR_CONF__INDEX_BITS_MASK__SI 0x00000007L -#define UVD_MPC_REF_PIC_ADDR_CONF__OFFSET_BITS_MASK__SI 0x000000f0L -#define UVD_MPC_SET_ALU__FUNCT_MASK__SI 0x00000007L -#define UVD_MPC_SET_ALU__OPERAND_MASK__SI 0x00000ff0L -#define UVD_MPC_SET_MUXA0__VARA_0_MASK__SI 0x0000003fL -#define UVD_MPC_SET_MUXA0__VARA_1_MASK__SI 0x00000fc0L -#define UVD_MPC_SET_MUXA0__VARA_2_MASK__SI 0x0003f000L -#define UVD_MPC_SET_MUXA0__VARA_3_MASK__SI 0x00fc0000L -#define UVD_MPC_SET_MUXA0__VARA_4_MASK__SI 0x3f000000L -#define UVD_MPC_SET_MUXA1__VARA_5_MASK__SI 0x0000003fL -#define UVD_MPC_SET_MUXA1__VARA_6_MASK__SI 0x00000fc0L -#define UVD_MPC_SET_MUXA1__VARA_7_MASK__SI 0x0003f000L -#define UVD_MPC_SET_MUXB0__VARB_0_MASK__SI 0x0000003fL -#define UVD_MPC_SET_MUXB0__VARB_1_MASK__SI 0x00000fc0L -#define UVD_MPC_SET_MUXB0__VARB_2_MASK__SI 0x0003f000L -#define UVD_MPC_SET_MUXB0__VARB_3_MASK__SI 0x00fc0000L -#define UVD_MPC_SET_MUXB0__VARB_4_MASK__SI 0x3f000000L -#define UVD_MPC_SET_MUXB1__VARB_5_MASK__SI 0x0000003fL -#define UVD_MPC_SET_MUXB1__VARB_6_MASK__SI 0x00000fc0L -#define UVD_MPC_SET_MUXB1__VARB_7_MASK__SI 0x0003f000L -#define UVD_MPC_SET_MUX__SET_0_MASK__SI 0x00000007L -#define UVD_MPC_SET_MUX__SET_1_MASK__SI 0x00000038L -#define UVD_MPC_SET_MUX__SET_2_MASK__SI 0x000001c0L -#define UVD_MPEG2_CTRL__EN_MASK__SI 0x00000001L -#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK__SI 0xffff0000L -#define UVD_MPEG2_CTRL__TRICK_MODE_MASK__SI 0x00000002L -#define UVD_MPEG2_ERROR__STATUS_MASK__SI 0xffffffffL -#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK__SI 0x00000fffL -#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK__SI 0x0fff0000L -#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK__SI 0x00000003L -#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK__SI 0x00300000L -#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK__SI 0x00c00000L -#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK__SI 0x03000000L -#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK__SI 0x0c000000L -#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK__SI 0x30000000L -#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK__SI 0xc0000000L -#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK__SI 0x0000000cL -#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK__SI 0x00000030L -#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK__SI 0x000000c0L -#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK__SI 0x00000300L -#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK__SI 0x00000c00L -#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK__SI 0x00003000L -#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK__SI 0x0000c000L -#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK__SI 0x00030000L -#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK__SI 0x000c0000L -#define UVD_NO_OP__NO_OP_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_CONF__CONCATENATE_MASK__SI 0x000f0000L -#define UVD_PERF_BANK_CONF__PEEK_MASK__SI 0x0000ff00L -#define UVD_PERF_BANK_CONF__RESET_MASK__SI 0x000000ffL -#define UVD_PERF_BANK_COUNT0__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_COUNT1__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_COUNT2__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_COUNT3__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_COUNT4__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_COUNT5__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_COUNT6__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_COUNT7__COUNT_MASK__SI 0xffffffffL -#define UVD_PERF_BANK_EVENT_SEL0__SEL0_MASK__SI 0x000000ffL -#define UVD_PERF_BANK_EVENT_SEL0__SEL1_MASK__SI 0x0000ff00L -#define UVD_PERF_BANK_EVENT_SEL0__SEL2_MASK__SI 0x00ff0000L -#define UVD_PERF_BANK_EVENT_SEL0__SEL3_MASK__SI 0xff000000L -#define UVD_PERF_BANK_EVENT_SEL1__SEL4_MASK__SI 0x000000ffL -#define UVD_PERF_BANK_EVENT_SEL1__SEL5_MASK__SI 0x0000ff00L -#define UVD_PERF_BANK_EVENT_SEL1__SEL6_MASK__SI 0x00ff0000L -#define UVD_PERF_BANK_EVENT_SEL1__SEL7_MASK__SI 0xff000000L -#define UVD_PICCOUNT__DUM_MASK__SI 0xffffffffL -#define UVD_PIC_CTL_BUF_BASE__BASE_MASK__SI 0xffffffffL -#define UVD_PITCH__DUM_MASK__SI 0xffffffffL -#define UVD_PRIVILEGE_REG_MASK_1__RBC_PRIVILEGE_REG_MASK_MASK__SI 0xffffffffL -#define UVD_PRIVILEGE_REG_MASK_IDCT__MASK_MASK__SI 0x000000ffL -#define UVD_PWR_STATUS__STATUS_MASK__SI 0xffffffffL -#define UVD_RBC_BDM_PRE__BDM_ENABLE_MASK__SI 0x00000001L -#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK__SI 0x00380000L -#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK__SI 0x0000ff00L -#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK__SI 0x0e000000L -#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK__SI 0x00070000L -#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK__SI 0x000000ffL -#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK__SI 0x01c00000L -#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP_MASK__SI 0xffff0000L -#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG_MASK__SI 0x0000ffffL -#define UVD_RBC_CAM_EN__RBC_CAM_EN_MASK__SI 0x00000001L -#define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX_MASK__SI 0xffffffffL -#define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC_MASK__SI 0x00000001L -#define UVD_RBC_IB_BASE__IB_BASE_MASK__SI 0xffffffc0L -#define UVD_RBC_IB_PRIVILEGE_REG_CHECK__IB_PRIVILEGE_REG_CHECK_EN_MASK__SI 0x00000001L -#define UVD_RBC_IB_PRIVILEGE_REG_CHECK__IB_PRIVILEGE_REG_CHECK_IDCT_EN_MASK__SI 0x00000002L -#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK__SI 0x007ffff0L -#define UVD_RBC_IB_SIZE__IB_SIZE_MASK__SI 0x007ffff0L -#define UVD_RBC_PRIV_FAULT_REG__IDCTPDEC_REG_MASK__SI 0x01fc0000L -#define UVD_RBC_PRIV_FAULT_REG__UVDDEC_REG_MASK__SI 0x00000ffcL -#define UVD_RBC_RB_BASE__RB_BASE_MASK__SI 0xffffffc0L -#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK__SI 0x00001f00L -#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK__SI 0x0000001fL -#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK__SI 0x00010000L -#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK__SI 0x01000000L -#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK__SI 0x10000000L -#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK__SI 0x00100000L -#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK__SI 0xffffffffL -#define UVD_RBC_RB_RPTR__RB_RPTR_MASK__SI 0x007ffff0L -#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK__SI 0x00007fffL -#define UVD_RBC_RB_WPTR__RB_WPTR_MASK__SI 0x007ffff0L -#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK__SI 0x00000003L -#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK__SI 0x00000001L -#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK__SI 0xfffffffcL -#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK__SI 0xffff0000L -#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK__SI 0x0000ffffL -#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK__SI 0x007ffff0L -#define UVD_RB_ARB_CTRL__RBC_DIS_MASK__SI 0x00000020L -#define UVD_RB_ARB_CTRL__RBC_DROP_MASK__SI 0x00000010L -#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK__SI 0x00000002L -#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK__SI 0x00000001L -#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK__SI 0x00000008L -#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK__SI 0x00000004L -#define UVD_REPLAY_OFFSET__REPLAY_OFFSET_MASK__SI 0xffffffffL -#define UVD_RESERVED_0__RESERVED_MASK__SI 0xffffffffL -#define UVD_RESERVED_1__RESERVED_MASK__SI 0xffffffffL -#define UVD_RESERVED_2__RESERVED_MASK__SI 0xffffffffL -#define UVD_RLC_CONTROL__RLC_REQ_ACK_MASK__SI 0x000000f0L -#define UVD_RLC_CONTROL__RLC_REQ_TYPE_MASK__SI 0x0000000fL -#define UVD_RLC_HB_BASE__HB_BASE_MASK__SI 0xffffffffL -#define UVD_RLC_HB_CNTL__HB_BUFSZ_MASK__SI 0xffffffffL -#define UVD_RLC_HB_RPTR__HB_RPTR_MASK__SI 0xffffffffL -#define UVD_RLC_HB_WPTR_LSB_ADDR__HB_WPTR_LSB_ADDR_MASK__SI 0xfffffffcL -#define UVD_RLC_HB_WPTR_MSB_ADDR__HB_WPTR_MSB_ADDR_MASK__SI 0x000000ffL -#define UVD_RLC_HB_WPTR__HB_WPTR_MASK__SI 0xffffffffL -#define UVD_RLC_RL_BASE__RL_BASE_MASK__SI 0xffffffffL -#define UVD_RLC_RL_SIZE__RL_SIZE_MASK__SI 0x0000000fL -#define UVD_RLC_SCRATCH__SCRATCH_MASK__SI 0xffffffffL -#define UVD_RMAP_CONF__CLOSED_ENTRY_MASK__SI 0x00000001L -#define UVD_RMAP_CONF__MAPUV_FLAG_MASK__SI 0x00000100L -#define UVD_RMAP_CONF__MAPUV_MASK__SI 0x00000e00L -#define UVD_RMAP_CONF__MAPY_FLAG_MASK__SI 0x00000010L -#define UVD_RMAP_CONF__MAPY_MASK__SI 0x000000e0L -#define UVD_SCRATCH_NP__DATA_MASK__SI 0xffffffffL -#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK__SI 0x000fffffL -#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK__SI 0x000fffffL -#define UVD_SEMA_CMD__MODE_MASK__SI 0x00000040L -#define UVD_SEMA_CMD__REQ_CMD_MASK__SI 0x0000000fL -#define UVD_SEMA_CMD__WR_PHASE_MASK__SI 0x00000030L -#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK__SI 0x00000002L -#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK__SI 0x00000001L -#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK__SI 0x07000000L -#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK__SI 0x001ffffeL -#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK__SI 0x00000001L -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK__SI 0x00000004L -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK__SI 0x00000008L -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK__SI 0x00000002L -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK__SI 0x00000001L -#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK__SI 0x07000000L -#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK__SI 0x001ffffeL -#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK__SI 0x00000001L -#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK__SI 0x07000000L -#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK__SI 0x001ffffeL -#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK__SI 0x00000001L -#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK__SI 0x00000020L -#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK__SI 0x00000040L -#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK__SI 0x00000200L -#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK__SI 0x00001000L -#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK__SI 0x00000400L -#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK__SI 0x00000002L -#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK__SI 0x00000004L -#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK__SI 0x00002000L -#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK__SI 0x00000100L -#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK__SI 0x00000800L -#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK__SI 0x00000001L -#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK__SI 0x00004000L -#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK__SI 0x00000080L -#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK__SI 0x00000010L -#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK__SI 0x00000008L -#define UVD_STATUS__AVP_BLOCK_ACK_MASK__SI 0x00002000L -#define UVD_STATUS__AVP_BUSY_MASK__SI 0x00000100L -#define UVD_STATUS__AVP_CTL_ACK_MASK__SI 0x00000400L -#define UVD_STATUS__DRM_BUSY_MASK__SI 0x00020000L -#define UVD_STATUS__IDCT_BLOCK_ACK_MASK__SI 0x00004000L -#define UVD_STATUS__IDCT_BUSY_MASK__SI 0x00000200L -#define UVD_STATUS__IDCT_CTL_ACK_MASK__SI 0x00000800L -#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK__SI 0x00010000L -#define UVD_STATUS__RBC_BUSY_MASK__SI 0x00000001L -#define UVD_STATUS__SYS_GPCOM_REQ_MASK__SI 0x80000000L -#define UVD_STATUS__UVD_BLOCK_ACK_MASK__SI 0x00008000L -#define UVD_STATUS__UVD_CTL_ACK_MASK__SI 0x00001000L -#define UVD_STATUS__VCPU_REPORT_MASK__SI 0x000000feL -#define UVD_STOP_CONTEXT__CONTEXT_MODE_MASK__SI 0x00000002L -#define UVD_STOP_CONTEXT__STOP_CONTEXT_MASK__SI 0x00000001L -#define UVD_SW_SCRATCH_00__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_01__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_02__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_03__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_04__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_05__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_06__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_07__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_08__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_09__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_10__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_11__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_12__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_13__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_14__DATA_MASK__SI 0xffffffffL -#define UVD_SW_SCRATCH_15__DATA_MASK__SI 0xffffffffL -#define UVD_SYS_INT_ACK__CXW_FINISHED_ACK_MASK__SI 0x00020000L -#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK__SI 0x00000008L -#define UVD_SYS_INT_ACK__FCS_ACK_MASK__SI 0x04000000L -#define UVD_SYS_INT_ACK__FWV_STATUS_ACK_MASK__SI 0x00008000L -#define UVD_SYS_INT_ACK__IDCT_ACK_MASK__SI 0x01000000L -#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK__SI 0x00010000L -#define UVD_SYS_INT_ACK__LBSI_ACK_MASK__SI 0x00000800L -#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK__SI 0x00004000L -#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK__SI 0x00002000L -#define UVD_SYS_INT_ACK__MPRD_ACK_MASK__SI 0x02000000L -#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK__SI 0x20000000L -#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK__SI 0x00000040L -#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK__SI 0x00400000L -#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK__SI 0x00000004L -#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK__SI 0x00800000L -#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK__SI 0x00000002L -#define UVD_SYS_INT_ACK__SEMA_WAIT_INCOMPLETE_TIMEOUT_ACK_MASK__SI 0x00000001L -#define UVD_SYS_INT_ACK__UDEC_ACK_MASK__SI 0x00001000L -#define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK_MASK__SI 0x00000100L -#define UVD_SYS_INT_ACK__WPTR_IDLE_ACK_MASK__SI 0x00200000L -#define UVD_SYS_INT_EN__CXW_FINISHED_EN_MASK__SI 0x00020000L -#define UVD_SYS_INT_EN__CXW_WR_EN_MASK__SI 0x00000008L -#define UVD_SYS_INT_EN__FCS_EN_MASK__SI 0x04000000L -#define UVD_SYS_INT_EN__FWV_STATUS_EN_MASK__SI 0x00008000L -#define UVD_SYS_INT_EN__IDCT_EN_MASK__SI 0x01000000L -#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK__SI 0x00010000L -#define UVD_SYS_INT_EN__LBSI_EN_MASK__SI 0x00000800L -#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK__SI 0x00004000L -#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK__SI 0x00002000L -#define UVD_SYS_INT_EN__MPRD_EN_MASK__SI 0x02000000L -#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK__SI 0x20000000L -#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK__SI 0x00000040L -#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK__SI 0x00400000L -#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK__SI 0x00000004L -#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK__SI 0x00800000L -#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK__SI 0x00000002L -#define UVD_SYS_INT_EN__SEMA_WAIT_INCOMPLETE_TIMEOUT_EN_MASK__SI 0x00000001L -#define UVD_SYS_INT_EN__UDEC_EN_MASK__SI 0x00001000L -#define UVD_SYS_INT_EN__UVD_HOST_CXW_EN_MASK__SI 0x00000100L -#define UVD_SYS_INT_EN__WPTR_IDLE_EN_MASK__SI 0x00200000L -#define UVD_SYS_INT_STATUS__CXW_FINISHED_INT_MASK__SI 0x00020000L -#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK__SI 0x00000008L -#define UVD_SYS_INT_STATUS__FCS_INT_MASK__SI 0x04000000L -#define UVD_SYS_INT_STATUS__FWV_STATUS_INT_MASK__SI 0x00008000L -#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK__SI 0x00040000L -#define UVD_SYS_INT_STATUS__IDCT_INT_MASK__SI 0x01000000L -#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK__SI 0x00010000L -#define UVD_SYS_INT_STATUS__LBSI_INT_MASK__SI 0x00000800L -#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK__SI 0x00004000L -#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK__SI 0x00002000L -#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK__SI 0x20000000L -#define UVD_SYS_INT_STATUS__MPRD_INT_MASK__SI 0x02000000L -#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT_MASK__SI 0x00400000L -#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK__SI 0x00000040L -#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK__SI 0x00000004L -#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK__SI 0x00800000L -#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK__SI 0x00000002L -#define UVD_SYS_INT_STATUS__SEMA_WAIT_INCOMPLETE_TIMEOUT_INT_MASK__SI 0x00000001L -#define UVD_SYS_INT_STATUS__UDEC_INT_MASK__SI 0x00001000L -#define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT_MASK__SI 0x00000100L -#define UVD_SYS_INT_STATUS__WPTR_IDLE_INT_MASK__SI 0x00200000L -#define UVD_UDEC_ADR__SYNC_RE_MASK__SI 0x00000080L -#define UVD_UDEC_DBW_TILING_CONFIG__BANK_SWAPS_MASK__SI 0x00003800L -#define UVD_UDEC_DBW_TILING_CONFIG__BANK_TILING_MASK__SI 0x00000030L -#define UVD_UDEC_DBW_TILING_CONFIG__GROUP_SIZE_MASK__SI 0x000000c0L -#define UVD_UDEC_DBW_TILING_CONFIG__PIPE_TILING_MASK__SI 0x0000000eL -#define UVD_UDEC_DBW_TILING_CONFIG__ROW_TILING_MASK__SI 0x00000700L -#define UVD_UDEC_DBW_TILING_CONFIG__SAMPLE_SPLIT_MASK__SI 0x0000c000L -#define UVD_UDEC_DB_TILING_CONFIG__BANK_SWAPS_MASK__SI 0x00003800L -#define UVD_UDEC_DB_TILING_CONFIG__BANK_TILING_MASK__SI 0x00000030L -#define UVD_UDEC_DB_TILING_CONFIG__GROUP_SIZE_MASK__SI 0x000000c0L -#define UVD_UDEC_DB_TILING_CONFIG__PIPE_TILING_MASK__SI 0x0000000eL -#define UVD_UDEC_DB_TILING_CONFIG__ROW_TILING_MASK__SI 0x00000700L -#define UVD_UDEC_DB_TILING_CONFIG__SAMPLE_SPLIT_MASK__SI 0x0000c000L -#define UVD_UDEC_DEBUG_MUX__MUX_MASK__SI 0x0000003fL -#define UVD_UDEC_TILING_CONFIG__BANK_SWAPS_MASK__SI 0x00003800L -#define UVD_UDEC_TILING_CONFIG__BANK_TILING_MASK__SI 0x00000030L -#define UVD_UDEC_TILING_CONFIG__GROUP_SIZE_MASK__SI 0x000000c0L -#define UVD_UDEC_TILING_CONFIG__PIPE_TILING_MASK__SI 0x0000000eL -#define UVD_UDEC_TILING_CONFIG__ROW_TILING_MASK__SI 0x00000700L -#define UVD_UDEC_TILING_CONFIG__SAMPLE_SPLIT_MASK__SI 0x0000c000L -#define UVD_UMC_AVP_BLOCK_REQ__CMC_BLOCK_REQ_MASK__SI 0x00000001L -#define UVD_UMC_AVP_CTL_CMD__CMC_REQ_MASK__SI 0x00000001L -#define UVD_UMC_IDCT_BLOCK_REQ__CMC_BLOCK_REQ_MASK__SI 0x00000001L -#define UVD_UMC_IDCT_CTL_CMD__CMC_REQ_MASK__SI 0x00000001L -#define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ_MASK__SI 0x00000001L -#define UVD_UMC_UVD_CTL_CMD__CMC_REQ_MASK__SI 0x00000001L -#define UVD_UVBASE__DUM_MASK__SI 0xffffffffL -#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK__SI 0x01ffffffL -#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK__SI 0x001fffffL -#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK__SI 0x001fffffL -#define UVD_VCPU_CNTL__ABORT_REQ_MASK__SI 0x00000100L -#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK__SI 0x00000010L -#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK__SI 0x00020000L -#define UVD_VCPU_CNTL__CLK_EN_MASK__SI 0x00000200L -#define UVD_VCPU_CNTL__DBG_MUX_MASK__SI 0x0000e000L -#define UVD_VCPU_CNTL__IRQ_ERR_MASK__SI 0x0000000fL -#define UVD_VCPU_CNTL__JTAG_EN_MASK__SI 0x00010000L -#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK__SI 0x00000020L -#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK__SI 0x00000040L -#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK__SI 0x00000080L -#define UVD_VCPU_CNTL__TIE_Q_NO_FLOP_MASK__SI 0x00080000L -#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK__SI 0x00040000L -#define UVD_VCPU_CNTL__TRCE_EN_MASK__SI 0x00000400L -#define UVD_VCPU_CNTL__TRCE_MUX_MASK__SI 0x00001800L -#define UVD_VCPU_DBG__DBG_RD_MASK__SI 0xffffffffL -#define UVD_VCPU_INT_ACK__AVP_BLOCK_ACK_ACK_MASK__SI 0x00000080L -#define UVD_VCPU_INT_ACK__AVP_CTL_ACK_ACK_MASK__SI 0x00000008L -#define UVD_VCPU_INT_ACK__CXW_FINISHED_ACK_MASK__SI 0x00080000L -#define UVD_VCPU_INT_ACK__CXW_START_ACK_MASK__SI 0x00040000L -#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK__SI 0x80000000L -#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK__SI 0x40000000L -#define UVD_VCPU_INT_ACK__FWV_STATUS_ACK_MASK__SI 0x00008000L -#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK__SI 0x01000000L -#define UVD_VCPU_INT_ACK__IDCT_BLOCK_ACK_ACK_MASK__SI 0x00000200L -#define UVD_VCPU_INT_ACK__IDCT_CTL_ACK_ACK_MASK__SI 0x00000010L -#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK__SI 0x00020000L -#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK__SI 0x00000800L -#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK__SI 0x00004000L -#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK__SI 0x00002000L -#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK__SI 0x02000000L -#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK__SI 0x20000000L -#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK__SI 0x00000040L -#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK__SI 0x00400000L -#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK__SI 0x00010000L -#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK__SI 0x00000004L -#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK__SI 0x00800000L -#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK__SI 0x00000002L -#define UVD_VCPU_INT_ACK__SEMA_WAIT_INCOMPLETE_TIMEOUT_ACK_MASK__SI 0x00000001L -#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK__SI 0x00001000L -#define UVD_VCPU_INT_ACK__UVD_BLOCK_ACK_ACK_MASK__SI 0x00000400L -#define UVD_VCPU_INT_ACK__UVD_CTL_ACK_ACK_MASK__SI 0x00000020L -#define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK_MASK__SI 0x00000100L -#define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK_MASK__SI 0x00200000L -#define UVD_VCPU_INT_EN__AVP_BLOCK_ACK_EN_MASK__SI 0x00000080L -#define UVD_VCPU_INT_EN__AVP_CTL_ACK_EN_MASK__SI 0x00000008L -#define UVD_VCPU_INT_EN__CXW_FINISHED_EN_MASK__SI 0x00080000L -#define UVD_VCPU_INT_EN__CXW_START_EN_MASK__SI 0x00040000L -#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK__SI 0x80000000L -#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK__SI 0x40000000L -#define UVD_VCPU_INT_EN__FWV_STATUS_EN_MASK__SI 0x00008000L -#define UVD_VCPU_INT_EN__IDCT_BLOCK_ACK_EN_MASK__SI 0x00000200L -#define UVD_VCPU_INT_EN__IDCT_CTL_ACK_EN_MASK__SI 0x00000010L -#define UVD_VCPU_INT_EN__IDCT_EN_MASK__SI 0x01000000L -#define UVD_VCPU_INT_EN__JOB_START_EN_MASK__SI 0x00020000L -#define UVD_VCPU_INT_EN__LBSI_EN_MASK__SI 0x00000800L -#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK__SI 0x00004000L -#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK__SI 0x00002000L -#define UVD_VCPU_INT_EN__MPRD_EN_MASK__SI 0x02000000L -#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK__SI 0x20000000L -#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK__SI 0x00000040L -#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK__SI 0x00400000L -#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK__SI 0x00010000L -#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK__SI 0x00000004L -#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK__SI 0x00800000L -#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK__SI 0x00000002L -#define UVD_VCPU_INT_EN__SEMA_WAIT_INCOMPLETE_TIMEOUT_EN_MASK__SI 0x00000001L -#define UVD_VCPU_INT_EN__UDEC_EN_MASK__SI 0x00001000L -#define UVD_VCPU_INT_EN__UVD_BLOCK_ACK_EN_MASK__SI 0x00000400L -#define UVD_VCPU_INT_EN__UVD_CTL_ACK_EN_MASK__SI 0x00000020L -#define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN_MASK__SI 0x00000100L -#define UVD_VCPU_INT_EN__WPTR_IDLE_EN_MASK__SI 0x00200000L -#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK__SI 0x00000001L -#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK__SI 0x00000002L -#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK__SI 0x00000004L -#define UVD_VCPU_INT_STATUS__AVP_BLOCK_ACK_INT_MASK__SI 0x00000080L -#define UVD_VCPU_INT_STATUS__AVP_CTL_ACK_INT_MASK__SI 0x00000008L -#define UVD_VCPU_INT_STATUS__CXW_FINISHED_INT_MASK__SI 0x00080000L -#define UVD_VCPU_INT_STATUS__CXW_START_INT_MASK__SI 0x00040000L -#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK__SI 0x80000000L -#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK__SI 0x40000000L -#define UVD_VCPU_INT_STATUS__FWV_STATUS_INT_MASK__SI 0x00008000L -#define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK__SI 0x00100000L -#define UVD_VCPU_INT_STATUS__IDCT_BLOCK_ACK_INT_MASK__SI 0x00000200L -#define UVD_VCPU_INT_STATUS__IDCT_CTL_ACK_INT_MASK__SI 0x00000010L -#define UVD_VCPU_INT_STATUS__IDCT_INT_MASK__SI 0x01000000L -#define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK__SI 0x00020000L -#define UVD_VCPU_INT_STATUS__LBSI_INT_MASK__SI 0x00000800L -#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK__SI 0x00004000L -#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK__SI 0x00002000L -#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK__SI 0x20000000L -#define UVD_VCPU_INT_STATUS__MPRD_INT_MASK__SI 0x02000000L -#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT_MASK__SI 0x00400000L -#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK__SI 0x00000040L -#define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK__SI 0x00010000L -#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK__SI 0x00000004L -#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK__SI 0x00800000L -#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK__SI 0x00000002L -#define UVD_VCPU_INT_STATUS__SEMA_WAIT_INCOMPLETE_TIMEOUT_INT_MASK__SI 0x00000001L -#define UVD_VCPU_INT_STATUS__UDEC_INT_MASK__SI 0x00001000L -#define UVD_VCPU_INT_STATUS__UVD_BLOCK_ACK_INT_MASK__SI 0x00000400L -#define UVD_VCPU_INT_STATUS__UVD_CTL_ACK_INT_MASK__SI 0x00000020L -#define UVD_VCPU_INT_STATUS__UVD_HOST_CXW_INT_MASK__SI 0x00000100L -#define UVD_VCPU_INT_STATUS__WPTR_IDLE_INT_MASK__SI 0x00200000L -#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK__SI 0x01ffffffL -#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK__SI 0x01ffffffL -#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK__SI 0x001fffffL -#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK__SI 0x001fffffL -#define UVD_VCPU_PDEBUG_CCOUNT__CCOUNT_MASK__SI 0xffffffffL -#define UVD_VCPU_PDEBUG_DATA_H__DATA_H_MASK__SI 0xffffffffL -#define UVD_VCPU_PDEBUG_DATA_L__DATA_L_MASK__SI 0xffffffffL -#define UVD_VCPU_PDEBUG_EPC__EPC_MASK__SI 0xffffffffL -#define UVD_VCPU_PDEBUG_EXCCAUSE__EXCCAUSE_MASK__SI 0xffffffffL -#define UVD_VCPU_PDEBUG_ICOUNT__ICOUNT_MASK__SI 0xffffffffL -#define UVD_VCPU_PDEBUG_PSTATUS__PSTATUS_MASK__SI 0x0000ffffL -#define UVD_VCPU_PDEBUG_PS__PS_MASK__SI 0xffffffffL -#define UVD_VCPU_PRID__PRID_MASK__SI 0x0000ffffL -#define UVD_VCPU_TRCE_RD__DATA_MASK__SI 0xffffffffL -#define UVD_VCPU_TRCE__PC_MASK__SI 0x0fffffffL -#define UVD_WIDTH__DUM_MASK__SI 0xffffffffL -#define UVD_YBASE__DUM_MASK__SI 0xffffffffL -#define VBLANK_STATUS__VBLANK_ACK_MASK__SI 0x00000010L -#define VBLANK_STATUS__VBLANK_INTERRUPT_MASK__SI 0x00010000L -#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK__SI 0x00020000L -#define VBLANK_STATUS__VBLANK_OCCURRED_MASK__SI 0x00000001L -#define VBLANK_STATUS__VBLANK_STAT_MASK__SI 0x00001000L -#define VCE_CONFIG__VCE_RDREQ_URG_MASK__CI 0x00000f00L -#define VCE_CONFIG__VCE_REQ_TRAN_MASK__CI 0x00010000L -#define VENDOR_CAP_LIST__CAP_ID_MASK__CI__VI 0x000000ffL -#define VENDOR_CAP_LIST__LENGTH_MASK__CI__VI 0x00ff0000L -#define VENDOR_CAP_LIST__NEXT_PTR_MASK__CI__VI 0x0000ff00L -#define VENDOR_ID__VENDOR_ID_MASK 0x0000ffffL -#define VGA25_PPLL_CNTL__VGA25_PPLL_CP_MASK__SI 0x00000f00L -#define VGA25_PPLL_CNTL__VGA25_PPLL_CTL_MASK__SI 0x0000001fL -#define VGA25_PPLL_CNTL__VGA25_PPLL_IBIAS_MASK__SI 0xff000000L -#define VGA25_PPLL_CNTL__VGA25_PPLL_LF_MODE_MASK__SI 0x001ff000L -#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK__SI 0x00000030L -#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK__SI 0x0000000fL -#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK__SI 0x07ff0000L -#define VGA25_PPLL_POST_DIV_SRC__VGA25_PPLL_POST_DIV_SRC_MASK__SI 0x00000001L -#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_MASK__SI 0x0000007fL -#define VGA25_PPLL_REF_DIV_SRC__VGA25_PPLL_REF_DIV_SRC_MASK__SI 0x00000007L -#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK__SI 0x000003ffL -#define VGA28_PPLL_CNTL__VGA28_PPLL_CP_MASK__SI 0x00000f00L -#define VGA28_PPLL_CNTL__VGA28_PPLL_CTL_MASK__SI 0x0000001fL -#define VGA28_PPLL_CNTL__VGA28_PPLL_IBIAS_MASK__SI 0xff000000L -#define VGA28_PPLL_CNTL__VGA28_PPLL_LF_MODE_MASK__SI 0x001ff000L -#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK__SI 0x00000030L -#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK__SI 0x0000000fL -#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK__SI 0x07ff0000L -#define VGA28_PPLL_POST_DIV_SRC__VGA28_PPLL_POST_DIV_SRC_MASK__SI 0x00000001L -#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_MASK__SI 0x0000007fL -#define VGA28_PPLL_REF_DIV_SRC__VGA28_PPLL_REF_DIV_SRC_MASK__SI 0x00000007L -#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK__SI 0x000003ffL -#define VGA41_PPLL_CNTL__VGA41_PPLL_CP_MASK__SI 0x00000f00L -#define VGA41_PPLL_CNTL__VGA41_PPLL_CTL_MASK__SI 0x0000001fL -#define VGA41_PPLL_CNTL__VGA41_PPLL_IBIAS_MASK__SI 0xff000000L -#define VGA41_PPLL_CNTL__VGA41_PPLL_LF_MODE_MASK__SI 0x001ff000L -#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK__SI 0x00000030L -#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK__SI 0x0000000fL -#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK__SI 0x07ff0000L -#define VGA41_PPLL_POST_DIV_SRC__VGA41_PPLL_POST_DIV_SRC_MASK__SI 0x00000001L -#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_MASK__SI 0x0000007fL -#define VGA41_PPLL_REF_DIV_SRC__VGA41_PPLL_REF_DIV_SRC_MASK__SI 0x00000007L -#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK__SI 0x000003ffL -#define VGADCCIF_HOSTIF_R_ADDR__VGADCCIF_HOSTIF_R_ADDR_MASK__SI 0xffffffffL -#define VGADCCIF_HOSTIF_W_ADDR__VGADCCIF_HOSTIF_W_ADDR_MASK__SI 0xffffffffL -#define VGADCCIF_RENDERIF_R_ADDR__VGADCCIF_RENDERIF_R_ADDR_MASK__SI 0xffffffffL -#define VGADCCIF_RENDERIF_W_ADDR__VGADCCIF_RENDERIF_W_ADDR_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_A__DBG_DCCIF_A_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_B__DBG_DCCIF_B_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_D__DBG_DCCIF_D_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_E__DBG_DCCIF_E_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_F__DBG_DCCIF_F_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_G__DBG_DCCIF_G_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_H__DBG_DCCIF_H_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_I__DBG_DCCIF_I_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_J__DBG_DCCIF_J_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_K__DBG_DCCIF_K_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_L__DBG_DCCIF_L_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_M__DBG_DCCIF_M_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_N__DBG_DCCIF_N_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_O__DBG_DCCIF_O_MASK__SI 0xffffffffL -#define VGADCC_DBG_DCCIF_P__DBG_DCCIF_P_MASK__SI 0xffffffffL -#define VGA_ADDR__ADDRESGEN_STATE_MASK__SI 0x0000001fL -#define VGA_ADDR__ADDRESSGEN_A_MASK__SI 0xfffffc00L -#define VGA_ADDR__VGARENDER_ADDRSOPSTART_MASK__SI 0x00000020L -#define VGA_ADDR__VGARENDER_ADDRSOP_MASK__SI 0x000003c0L -#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK__SI 0x00100000L -#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK__SI 0x3f000000L -#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK__SI 0x00010000L -#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK__SI 0x00000100L -#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK__SI 0x00000001L -#define VGA_COHERENCY_TIMER_CNTL__VGA_COHE_SPEC_TIMER_SEL_MASK__SI 0x00000003L -#define VGA_CRTC__VGA_CRTC_CUR_STATE_MASK__SI 0x0000007cL -#define VGA_CRTC__VGA_REG_CUROP_MASK__SI 0x3fc00000L -#define VGA_CRTC__VGA_REG_GEN_STATE_MASK__SI 0x00000780L -#define VGA_CRTC__VGA_REG_RDY_MASK__SI 0x00000002L -#define VGA_CRTC__VGA_REG_SUM_MASK__SI 0x003ff800L -#define VGA_CRTC__VGA_START_REG_TRAN_MASK__SI 0x00000001L -#define VGA_DEBUG_ID__VGA_DEBUG_ID_MASK__SI 0xffffffffL -#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK__SI 0xffffffffL -#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK__SI 0x000000ffL -#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK__SI 0x01ffffffL -#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK__SI 0x01ffffffL -#define VGA_GRAPH__ADDRESSGEN_ADDRSOPDONE_MASK__SI 0x00400000L -#define VGA_GRAPH__DCCIF_VGA_WACK_MASK__SI 0x00200000L -#define VGA_GRAPH__GFXPIXGEN_ENDOFCHAR_MASK__SI 0x00080000L -#define VGA_GRAPH__GFXPIXGEN_PIXGENDONE_MASK__SI 0x00100000L -#define VGA_GRAPH__GFXRENDERSUP_ADDPITCH_MASK__SI 0x01000000L -#define VGA_GRAPH__GFXRENDERSUP_ADDRSEL_MASK__SI 0x00060000L -#define VGA_GRAPH__GFXRENDERSUP_BUFOFFSET_MASK__SI 0x0001c000L -#define VGA_GRAPH__GFXRENDERSUP_DWB_RST_WR_A_MASK__SI 0x20000000L -#define VGA_GRAPH__GFXRENDERSUP_DWORD_BUFFER_RDY_MASK__SI 0x10000000L -#define VGA_GRAPH__GFXRENDERSUP_DWORD_BUFFER_WEN_MASK__SI 0x80000000L -#define VGA_GRAPH__GFXRENDERSUP_FIRSTANDLASTPIX_MASK__SI 0x00003800L -#define VGA_GRAPH__GFXRENDERSUP_FIRSTCHARINLINE_MASK__SI 0x00000200L -#define VGA_GRAPH__GFXRENDERSUP_LASTCHARINLINE_MASK__SI 0x00000400L -#define VGA_GRAPH__GFXRENDERSUP_LAST_LINE_RENDERED_MASK__SI 0x08000000L -#define VGA_GRAPH__GFXRENDERSUP_LC_MASK__SI 0x00800000L -#define VGA_GRAPH__GFXRENDERSUP_PIXELWRITER_NXTWRADDRS_MASK__SI 0x40000000L -#define VGA_GRAPH__GFXRENDERSUP_RENDER_END_MASK__SI 0x04000000L -#define VGA_GRAPH__GFXRENDERSUP_STARTGFXPIXGEN_MASK__SI 0x00000100L -#define VGA_GRAPH__GFX_GEN_STATE_MASK__SI 0x0000000fL -#define VGA_GRAPH__GFX_LINE_GEN_STATE_MASK__SI 0x000000f0L -#define VGA_GRAPH__VGADCC_RD_RTR_MASK__SI 0x02000000L -#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK__SI 0x00000010L -#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK__SI 0x00000001L -#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK__SI 0x00000100L -#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK__SI 0x00010000L -#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK__SI 0x01000000L -#define VGA_HDP__BIF_VGA_A_MASK__SI 0x1fffc000L -#define VGA_HDP__BIF_VGA_BE_MASK__SI 0x0000003eL -#define VGA_HDP__BIF_VGA_OP_MASK__SI 0x40000000L -#define VGA_HDP__BIF_VGA_SEND_MASK__SI 0x00000001L -#define VGA_HDP__BIF_VGA_WD_MASK__SI 0x00001f80L -#define VGA_HDP__VGA_BIF_CLEAN_MASK__SI 0x00002000L -#define VGA_HDP__VGA_BIF_RD_VALID_MASK__SI 0x80000000L -#define VGA_HDP__VGA_BIF_RTR_MASK__SI 0x20000000L -#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK__SI 0xffffffffL -#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK__SI 0x00010000L -#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK__SI 0x00000001L -#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK__SI 0x01000000L -#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK__SI 0x00000100L -#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK__SI 0x00000004L -#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK__SI 0x00000001L -#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK__SI 0x00000008L -#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK__SI 0x00000002L -#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK__SI 0x00000003L -#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK__SI 0x20000000L -#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK__SI 0x80000000L -#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK__SI 0x03000000L -#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK__SI 0x00030000L -#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK__SI 0x04000000L -#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK__SI 0x00000300L -#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK__SI 0x08000000L -#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK__SI 0x00000018L -#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK__SI 0x000000e0L -#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK__SI 0x10000000L -#define VGA_MAIN__DISP_CUR_BUFF_FOLLOWS_VGA_MASK__SI 0x00008000L -#define VGA_MAIN__VGA_BLINK_PHASE_MASK__SI 0x00180000L -#define VGA_MAIN__VGA_BUF_CNTL_MASK__SI 0x08000000L -#define VGA_MAIN__VGA_CG_BUSY_MASK__SI 0x00000200L -#define VGA_MAIN__VGA_CUR_BUF1_MASK__SI 0x00000400L -#define VGA_MAIN__VGA_CUR_BUF2_MASK__SI 0x00000800L -#define VGA_MAIN__VGA_DATA_CHANGED_MASK__SI 0x00000010L -#define VGA_MAIN__VGA_DISP_BUF_CNTL_MASK__SI 0x00004000L -#define VGA_MAIN__VGA_ENER_END_OR_TIMEOUT_MASK__SI 0x00800000L -#define VGA_MAIN__VGA_FORCE_BLANK_MASK__SI 0x00000040L -#define VGA_MAIN__VGA_MAIN_CUR_STATE_MASK__SI 0x0000000fL -#define VGA_MAIN__VGA_ONLY_UPDATE_REG_MASK__SI 0x00000020L -#define VGA_MAIN__VGA_OVERSCAN_UPDATE_MASK__SI 0x02000000L -#define VGA_MAIN__VGA_RENDERATTR_BUSY_MASK__SI 0x00040000L -#define VGA_MAIN__VGA_RENDER_BUFF_SEL_MASK__SI 0x80000000L -#define VGA_MAIN__VGA_RENDER_SYNC1_MASK__SI 0x10000000L -#define VGA_MAIN__VGA_RENDER_SYNC2_MASK__SI 0x20000000L -#define VGA_MAIN__VGA_RENDER_SYNC_MASK__SI 0x00000100L -#define VGA_MAIN__VGA_STARTCLK_MASK__SI 0x00010000L -#define VGA_MAIN__VGA_START_REG_TRAN_MASK__SI 0x00000080L -#define VGA_MAIN__VGA_START_RENDER_MASK__SI 0x40000000L -#define VGA_MAIN__VGA_UDPATE_REG_MASK__SI 0x00020000L -#define VGA_MAIN__VGA_VSYNC_TIMEOUT_MASK__SI 0x01000000L -#define VGA_MAIN__VGA_XTAL_REF_CLK_MASK__SI 0x00200000L -#define VGA_MAIN__VSYNC_BOTH_GEN_STATE_MASK__SI 0x00003000L -#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK__SI 0x000000ffL -#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK__SI 0xffffffffL -#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK__SI 0x000003ffL -#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK__SI 0x03ff0000L -#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK__SI 0x000003ffL -#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK__SI 0x03ff0000L -#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK__SI 0x00000100L -#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK__SI 0x00000001L -#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK__SI 0x00000030L -#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK__SI 0x00010000L -#define VGA_REG__VGA_GATED_CLOCK_RUNNING_MASK__SI 0x08000000L -#define VGA_REG__VGA_I_RBBM_WD_MASK__SI 0xf0000000L -#define VGA_REG__VGA_RBBMIF_ADDR_MASK__SI 0x003fc000L -#define VGA_REG__VGA_RBBMIF_BE_MASK__SI 0x03c00000L -#define VGA_REG__VGA_RBBMIF_RDY0_MASK__SI 0x04000000L -#define VGA_REG__VGA_RBBMIF_RSTR_MASK__SI 0x00002000L -#define VGA_REG__VGA_RBBMIF_WSTR_MASK__SI 0x00001000L -#define VGA_REG__VGA_REG_RDY_I_MASK__SI 0x000000f0L -#define VGA_REG__VGA_REG_REQ_O_MASK__SI 0x00000f00L -#define VGA_REG__VGA_REG_WAIT_STATE_MASK__SI 0x0000000fL -#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK__SI 0x02000000L -#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK__SI 0x00000060L -#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK__SI 0x0000001fL -#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK__SI 0x00000080L -#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK__SI 0x00000100L -#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK__SI 0x01000000L -#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK__SI 0x00030000L -#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK__SI 0x00000001L -#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK__SI \ - 0x00000100L -#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK__SI 0x00000002L -#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK__SI \ - 0x00000200L -#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK__SI 0x00000004L -#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK__SI \ - 0x00000400L -#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK__SI 0x00000008L -#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK__SI \ - 0x00000800L -#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK__SI 0x00000010L -#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK__SI \ - 0x00001000L -#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK__SI 0x00000020L -#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK__SI \ - 0x00002000L -#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK__SI 0x00010000L -#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK__SI 0x00fc0000L -#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK__SI 0x00020000L -#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK__SI 0x00000007L -#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK__SI 0x00000700L -#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK__SI 0x00010000L -#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK__SI 0x00000001L -#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK__SI 0x01000000L -#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK__SI 0x00000100L -#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK__SI 0x00000004L -#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK__SI 0x00000001L -#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK__SI 0x00000008L -#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK__SI 0x00000002L -#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK__SI 0x00000300L -#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK__SI 0x00000003L -#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK__SI 0x00000001L -#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK__SI 0x01000000L -#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK__SI 0x00010000L -#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK__SI 0x00000100L -#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK__SI 0xffffffffL -#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK__SI 0x000000ffL -#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK__SI 0x00000100L -#define VGA_TEXT__TXTBLKGEN_FIRSTCHARINBUF_MASK__SI 0x00038000L -#define VGA_TEXT__TXTBLKGEN_FONTRDINDEX_MASK__SI 0x00006000L -#define VGA_TEXT__TXTBLKGEN_FONTREQUEST_MASK__SI 0x00001000L -#define VGA_TEXT__TXTBLKGEN_GENDONE_MASK__SI 0x00000800L -#define VGA_TEXT__TXTBLKGEN_LASTCHARDONE_MASK__SI 0x00400000L -#define VGA_TEXT__TXTBLKGEN_LASTCHARINBUF_MASK__SI 0x001c0000L -#define VGA_TEXT__TXTBLKGEN_NXTCHARINROWREQ_MASK__SI 0x00200000L -#define VGA_TEXT__TXTRENDERSUP_DWB_RST_WR_A_MASK__SI 0x20000000L -#define VGA_TEXT__TXTRENDERSUP_DWORD_BUFFER_RDY_MASK__SI 0x10000000L -#define VGA_TEXT__TXTRENDERSUP_DWORD_BUFFER_WEN_MASK__SI 0x80000000L -#define VGA_TEXT__TXTRENDERSUP_FIRSTCHARINROW_MASK__SI 0x00000100L -#define VGA_TEXT__TXTRENDERSUP_LASTCHARINROW_MASK__SI 0x00000200L -#define VGA_TEXT__TXTRENDERSUP_LASTLINERENDERED_MASK__SI 0x01000000L -#define VGA_TEXT__TXTRENDERSUP_LASTLINE_MASK__SI 0x04000000L -#define VGA_TEXT__TXTRENDERSUP_PIXELWRITER_NXTWRADDRS_MASK__SI 0x40000000L -#define VGA_TEXT__TXTRENDERSUP_RDSEND_MASK__SI 0x00800000L -#define VGA_TEXT__TXTRENDERSUP_STARTGEN_MASK__SI 0x00000400L -#define VGA_TEXT__TXTRENDERSUP_TOPTXTLINE_MASK__SI 0x02000000L -#define VGA_TEXT__TXT_GEN_STATE_MASK__SI 0x0000000fL -#define VGA_TEXT__TXT_LINE_GEN_STATE_MASK__SI 0x000000f0L -#define VGA_VGADCCIF__VGADCCIF_VGAHDP_D_RDY_MASK__SI 0x00000100L -#define VGA_VGADCCIF__VGADCCIF_VGAHDP_R_RTR_MASK__SI 0x00000080L -#define VGA_VGADCCIF__VGADCCIF_VGAHDP_W_RTR_MASK__SI 0x00000020L -#define VGA_VGADCCIF__VGADCCIF_VGARENDER_VALID_MASK__SI 0x00040000L -#define VGA_VGADCCIF__VGADCC_VGA_R_RTR_MASK__SI 0x40000000L -#define VGA_VGADCCIF__VGADCC_VGA_TAG_MASK__SI 0x00200000L -#define VGA_VGADCCIF__VGADCC_VGA_VALID_MASK__SI 0x00400000L -#define VGA_VGADCCIF__VGADCC_VGA_WACK_MASK__SI 0x00080000L -#define VGA_VGADCCIF__VGADCC_VGA_W_RTR_MASK__SI 0x01000000L -#define VGA_VGADCCIF__VGAHDP_MULTIPLEX_READBUFFER_RD_SEND_MASK__SI 0x00001000L -#define VGA_VGADCCIF__VGAHDP_NULL_BYTE_ENABLE_READ_MASK__SI 0x00000200L -#define VGA_VGADCCIF__VGAHDP_READ_OUTSTANDING_MASK__SI 0x00000800L -#define VGA_VGADCCIF__VGAHDP_VGADCCIF_R_SEND_MASK__SI 0x00000040L -#define VGA_VGADCCIF__VGAHDP_VGADCCIF_WM_MASK__SI 0x0000000fL -#define VGA_VGADCCIF__VGAHDP_VGADCCIF_W_SEND_MASK__SI 0x00000010L -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_R_RTR_MASK__SI 0x00020000L -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_R_SEND_MASK__SI 0x00010000L -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_WACK_REQ_MASK__SI 0x00008000L -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_W_RTR_MASK__SI 0x00004000L -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_W_SEND_MASK__SI 0x00002000L -#define VGA_VGADCCIF__VGA_BIF_RD_VALID_MASK__SI 0x80000000L -#define VGA_VGADCCIF__VGA_DCCIF_WPHASE1_CLEAN_MASK__SI 0x00000400L -#define VGA_VGADCCIF__VGA_VGADCC_R_REQ_MASK__SI 0x20000000L -#define VGA_VGADCCIF__VGA_VGADCC_TAG_MASK__SI 0x00100000L -#define VGA_VGADCCIF__VGA_VGADCC_W_BE_MASK__SI 0x1e000000L -#define VGA_VGADCCIF__VGA_VGADCC_W_REQ_MASK__SI 0x00800000L -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000c0L -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L -#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001f0000L -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L -#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L -#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L -#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L -#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L -#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L -#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L -#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L -#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L -#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L -#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L -#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000003fL -#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x00000040L -#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL -#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000L -#define VGT_DEBUG_REG0__SPARE10_MASK 0x00040000L -#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000L -#define VGT_DEBUG_REG0__SPARE2_MASK 0x02000000L -#define VGT_DEBUG_REG0__SPARE3_MASK 0x00100000L -#define VGT_DEBUG_REG0__SPARE4_MASK 0x00000080L -#define VGT_DEBUG_REG0__SPARE5_MASK 0x00000040L -#define VGT_DEBUG_REG0__SPARE6_MASK 0x00000020L -#define VGT_DEBUG_REG0__SPARE7_MASK 0x00000010L -#define VGT_DEBUG_REG0__SPARE8_MASK 0x00000008L -#define VGT_DEBUG_REG0__SPARE9_MASK 0x00000002L -#define VGT_DEBUG_REG0__cm_busy_MASK 0x00008000L -#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x00200000L -#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x04000000L -#define VGT_DEBUG_REG0__frmt_busy_MASK 0x00020000L -#define VGT_DEBUG_REG0__gog_busy_MASK 0x00010000L -#define VGT_DEBUG_REG0__gs_busy_MASK 0x00001000L -#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x08000000L -#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x00800000L -#define VGT_DEBUG_REG0__pi_busy_MASK 0x00000100L -#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x00000400L -#define VGT_DEBUG_REG0__rcm_busy_MASK 0x00002000L -#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L -#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L -#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000L -#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x00400000L -#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x00080000L -#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x00000800L -#define VGT_DEBUG_REG0__tm_busy_MASK 0x00004000L -#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00000004L -#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00000001L -#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x00000200L -#define VGT_DEBUG_REG10__SPARE2_MASK__CI__VI 0x00000600L -#define VGT_DEBUG_REG10__SPARE4_MASK__SI 0x00000780L -#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x00000020L -#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x00000040L -#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000L -#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x007fe000L -#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x0000001fL -#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK__CI__VI 0x00000180L -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x00001000L -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x00000800L -#define VGT_DEBUG_REG11__SPARE0_MASK 0x00040000L -#define VGT_DEBUG_REG11__SPARE1_MASK 0x00000020L -#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x00008000L -#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x00004000L -#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x00000800L -#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x00001000L -#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x00000400L -#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x00100000L -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x00000008L -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x08000000L -#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x00000200L -#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000L -#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x00200000L -#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x00010000L -#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x00080000L -#define VGT_DEBUG_REG11__hold_eswave_MASK 0x00000100L -#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000L -#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000L -#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x00000080L -#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x00000040L -#define VGT_DEBUG_REG11__tm_busy_MASK__SI 0x00000001L -#define VGT_DEBUG_REG11__tm_busy_q_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG11__tm_noif_busy_MASK__SI 0x00000002L -#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG11__tm_out_busy_MASK__SI 0x00000004L -#define VGT_DEBUG_REG11__tm_out_busy_q_MASK__CI__VI 0x00000004L -#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x00020000L -#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x01000000L -#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x00400000L -#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x00800000L -#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x00000010L -#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000L -#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x02000000L -#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x04000000L -#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000L -#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x00000007L -#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x00000038L -#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x000001c0L -#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0x00000e00L -#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x00007000L -#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x00038000L -#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x001c0000L -#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0x00e00000L -#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x07000000L -#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000L -#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000L -#define VGT_DEBUG_REG13__SPARE0_MASK 0x04000000L -#define VGT_DEBUG_REG13__SPARE1_MASK 0x02000000L -#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000L -#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x01000000L -#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x00000007L -#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x00000038L -#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x000001c0L -#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0x00000e00L -#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x00007000L -#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x00038000L -#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x003c0000L -#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x00800000L -#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x00400000L -#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000L -#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000L -#define VGT_DEBUG_REG14__SPARE2_MASK 0x001ff000L -#define VGT_DEBUG_REG14__SPARE3_MASK 0x0000000fL -#define VGT_DEBUG_REG14__SPARE8_MASK 0x00000180L -#define VGT_DEBUG_REG14__SPARE_MASK 0x01c00000L -#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000L -#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x02000000L -#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x00000400L -#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x00000020L -#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x00000800L -#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x00000010L -#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000L -#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x08000000L -#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x00200000L -#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x04000000L -#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x00000040L -#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x00000200L -#define VGT_DEBUG_REG15__SPARE25_MASK 0x03f00000L -#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000L -#define VGT_DEBUG_REG15__active_sm_q_MASK 0x000003e0L -#define VGT_DEBUG_REG15__cm_busy_MASK__SI 0x00000001L -#define VGT_DEBUG_REG15__cm_busy_q_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0x000f8000L -#define VGT_DEBUG_REG15__counters_busy_MASK__SI 0x00000002L -#define VGT_DEBUG_REG15__counters_busy_q_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG15__counters_full_MASK 0x00000010L -#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x00007c00L -#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000L -#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x00000004L -#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x00000008L -#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0x0c000000L -#define VGT_DEBUG_REG16__SPARE24_MASK__CI__VI 0x00800000L -#define VGT_DEBUG_REG16__SPARE24_MASK__SI 0x01800000L -#define VGT_DEBUG_REG16__SPARE29_MASK__SI 0x20000000L -#define VGT_DEBUG_REG16__gog_busy_MASK 0x00000001L -#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0x0e000000L -#define VGT_DEBUG_REG16__gog_state_q_MASK 0x0000000eL -#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x00080000L -#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x00020000L -#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x00002000L -#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000L -#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000L -#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000L -#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x00100000L -#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x00010000L -#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x00004000L -#define VGT_DEBUG_REG16__r0_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG16__r1_rtr_MASK 0x00000020L -#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x00000040L -#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x00000200L -#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x00000100L -#define VGT_DEBUG_REG16__r2_rtr_MASK 0x00000400L -#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x00000080L -#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG16__send_event_q_MASK 0x00400000L -#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x00200000L -#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x00040000L -#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x00008000L -#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK__CI__VI 0x01000000L -#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK__CI__VI 0x20000000L -#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000L -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x0003f000L -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0x00000fc0L -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x0000003fL -#define VGT_DEBUG_REG18__SPARE_MASK__SI 0xffffffffL -#define VGT_DEBUG_REG18__components_valid_r0_q_MASK__CI__VI 0xe0000000L -#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK__CI__VI 0x00800000L -#define VGT_DEBUG_REG18__eop_r0_q_MASK__CI__VI 0x00400000L -#define VGT_DEBUG_REG18__grp_vr_valid_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK__CI__VI 0x08000000L -#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK__CI__VI 0x10000000L -#define VGT_DEBUG_REG18__indices_to_send_q_MASK__CI__VI 0x00000700L -#define VGT_DEBUG_REG18__indx0_hit_d_MASK__CI__VI 0x00040000L -#define VGT_DEBUG_REG18__indx0_new_d_MASK__CI__VI 0x00002000L -#define VGT_DEBUG_REG18__indx1_hit_d_MASK__CI__VI 0x00020000L -#define VGT_DEBUG_REG18__indx1_new_d_MASK__CI__VI 0x00004000L -#define VGT_DEBUG_REG18__indx2_hit_d_MASK__CI__VI 0x00010000L -#define VGT_DEBUG_REG18__indx2_new_d_MASK__CI__VI 0x00008000L -#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK__CI__VI 0x00100000L -#define VGT_DEBUG_REG18__last_indx_of_prim_MASK__CI__VI 0x00001000L -#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK__CI__VI 0x00200000L -#define VGT_DEBUG_REG18__out_vr_indx_read_MASK__CI__VI 0x00000040L -#define VGT_DEBUG_REG18__out_vr_prim_read_MASK__CI__VI 0x00000080L -#define VGT_DEBUG_REG18__pipe0_dr_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG18__pipe0_rtr_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG18__pipe1_dr_MASK__CI__VI 0x00000004L -#define VGT_DEBUG_REG18__pipe1_rtr_MASK__CI__VI 0x00000020L -#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK__CI__VI 0x00080000L -#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK__CI__VI 0x07000000L -#define VGT_DEBUG_REG18__valid_indices_MASK__CI__VI 0x00000800L -#define VGT_DEBUG_REG18__vr_grp_read_MASK__CI__VI 0x00000008L -#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x00000080L -#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x00000040L -#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x00004000L -#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x08000000L -#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x04000000L -#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x00001000L -#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x00002000L -#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x00080000L -#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x00040000L -#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x00010000L -#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x00020000L -#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x03f00000L -#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000L -#define VGT_DEBUG_REG19__hold_prim_MASK 0x00000800L -#define VGT_DEBUG_REG19__new_packet_q_MASK 0x00008000L -#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000L -#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000L -#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_MASK__SI 0x00000020L -#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK__CI__VI 0x00000020L -#define VGT_DEBUG_REG19__pa_clips_fifo_busy_MASK__SI 0x00000010L -#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_MASK__SI 0x00000400L -#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK__CI__VI 0x00000400L -#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x00000004L -#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x00000008L -#define VGT_DEBUG_REG19__separate_out_busy_MASK__SI 0x00000001L -#define VGT_DEBUG_REG19__separate_out_busy_q_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG19__separate_out_indx_busy_MASK__SI 0x00000002L -#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_MASK__SI 0x00000100L -#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK__CI__VI 0x00000100L -#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_MASK__SI 0x00000200L -#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK__CI__VI 0x00000200L -#define VGT_DEBUG_REG1__SPARE0_MASK 0x00000200L -#define VGT_DEBUG_REG1__SPARE10_MASK 0x00200000L -#define VGT_DEBUG_REG1__SPARE11_MASK 0x00080000L -#define VGT_DEBUG_REG1__SPARE12_MASK 0x00020000L -#define VGT_DEBUG_REG1__SPARE1_MASK 0x00000100L -#define VGT_DEBUG_REG1__SPARE23_MASK 0x00800000L -#define VGT_DEBUG_REG1__SPARE25_MASK 0x02000000L -#define VGT_DEBUG_REG1__SPARE2_MASK 0x00000080L -#define VGT_DEBUG_REG1__SPARE3_MASK 0x00000040L -#define VGT_DEBUG_REG1__SPARE4_MASK 0x00000020L -#define VGT_DEBUG_REG1__SPARE5_MASK 0x00000010L -#define VGT_DEBUG_REG1__SPARE6_MASK 0x00000008L -#define VGT_DEBUG_REG1__SPARE7_MASK 0x00000004L -#define VGT_DEBUG_REG1__SPARE8_MASK 0x00000002L -#define VGT_DEBUG_REG1__SPARE9_MASK 0x00000001L -#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000L -#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000L -#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x08000000L -#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000L -#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000L -#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x04000000L -#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x00001000L -#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x00004000L -#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x00000400L -#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00100000L -#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00400000L -#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x00002000L -#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00008000L -#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x01000000L -#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00010000L -#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00040000L -#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x00000800L -#define VGT_DEBUG_REG20__SPARE17_MASK 0x00020000L -#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x003c0000L -#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000L -#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000L -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x00010000L -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0x0000ffffL -#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000L -#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000L -#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x01000000L -#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000L -#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x04000000L -#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x00008000L -#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x00002000L -#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x00000002L -#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x00000080L -#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x00010000L -#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x00100000L -#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x00200000L -#define VGT_DEBUG_REG21__null_r2_q_MASK 0x08000000L -#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x00000001L -#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x00000040L -#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000L -#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000L -#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000L -#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x00000004L -#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x00000100L -#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x00000008L -#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x00000200L -#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x00000010L -#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x00000400L -#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0x000e0000L -#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x00400000L -#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x02000000L -#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x00000020L -#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x00000800L -#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x00800000L -#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x00004000L -#define VGT_DEBUG_REG22__cm_state16_MASK 0x00000003L -#define VGT_DEBUG_REG22__cm_state17_MASK 0x0000000cL -#define VGT_DEBUG_REG22__cm_state18_MASK 0x00000030L -#define VGT_DEBUG_REG22__cm_state19_MASK 0x000000c0L -#define VGT_DEBUG_REG22__cm_state20_MASK 0x00000300L -#define VGT_DEBUG_REG22__cm_state21_MASK 0x00000c00L -#define VGT_DEBUG_REG22__cm_state22_MASK 0x00003000L -#define VGT_DEBUG_REG22__cm_state23_MASK 0x0000c000L -#define VGT_DEBUG_REG22__cm_state24_MASK 0x00030000L -#define VGT_DEBUG_REG22__cm_state25_MASK 0x000c0000L -#define VGT_DEBUG_REG22__cm_state26_MASK 0x00300000L -#define VGT_DEBUG_REG22__cm_state27_MASK 0x00c00000L -#define VGT_DEBUG_REG22__cm_state28_MASK 0x03000000L -#define VGT_DEBUG_REG22__cm_state29_MASK 0x0c000000L -#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000L -#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000L -#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000L -#define VGT_DEBUG_REG23__frmt_busy_MASK 0x00000001L -#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x00018000L -#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x00001000L -#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x00000200L -#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x00000400L -#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x00000008L -#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0x00e00000L -#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x00000004L -#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x00000002L -#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x00004000L -#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x00002000L -#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x00000800L -#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x00000100L -#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x00000080L -#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x00000040L -#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x00000020L -#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x001e0000L -#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000L -#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0x00ffffffL -#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x03000000L -#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000L -#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000L -#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000L -#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x03ffffffL -#define VGT_DEBUG_REG26__SPARE_MASK__SI 0xffffffffL -#define VGT_DEBUG_REG26__cm_state0_MASK__CI__VI 0x00000003L -#define VGT_DEBUG_REG26__cm_state10_MASK__CI__VI 0x00300000L -#define VGT_DEBUG_REG26__cm_state11_MASK__CI__VI 0x00c00000L -#define VGT_DEBUG_REG26__cm_state12_MASK__CI__VI 0x03000000L -#define VGT_DEBUG_REG26__cm_state13_MASK__CI__VI 0x0c000000L -#define VGT_DEBUG_REG26__cm_state14_MASK__CI__VI 0x30000000L -#define VGT_DEBUG_REG26__cm_state15_MASK__CI__VI 0xc0000000L -#define VGT_DEBUG_REG26__cm_state1_MASK__CI__VI 0x0000000cL -#define VGT_DEBUG_REG26__cm_state2_MASK__CI__VI 0x00000030L -#define VGT_DEBUG_REG26__cm_state3_MASK__CI__VI 0x000000c0L -#define VGT_DEBUG_REG26__cm_state4_MASK__CI__VI 0x00000300L -#define VGT_DEBUG_REG26__cm_state5_MASK__CI__VI 0x00000c00L -#define VGT_DEBUG_REG26__cm_state6_MASK__CI__VI 0x00003000L -#define VGT_DEBUG_REG26__cm_state7_MASK__CI__VI 0x0000c000L -#define VGT_DEBUG_REG26__cm_state8_MASK__CI__VI 0x00030000L -#define VGT_DEBUG_REG26__cm_state9_MASK__CI__VI 0x000c0000L -#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x00000800L -#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x00000400L -#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x00080000L -#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x00003000L -#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x00000002L -#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x00000020L -#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x00010000L -#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x00020000L -#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x00008000L -#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000L -#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x00004000L -#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x00000300L -#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x00000080L -#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x00040000L -#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000L -#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x00000001L -#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x00000004L -#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x00000040L -#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x00000008L -#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x00800000L -#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x00400000L -#define VGT_DEBUG_REG28__con_state_q_MASK 0x0000000fL -#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x00010000L -#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x00040000L -#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x00100000L -#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x00080000L -#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x00020000L -#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x01000000L -#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L -#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x00004000L -#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x00008000L -#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x00000200L -#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x00000100L -#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x00000400L -#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000L -#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000L -#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x02000000L -#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x04000000L -#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000L -#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L -#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x00000080L -#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x00000020L -#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x00000010L -#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000L -#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x00800000L -#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x00400000L -#define VGT_DEBUG_REG29__con_state_q_MASK 0x0000000fL -#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x00010000L -#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x00040000L -#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x00100000L -#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x00080000L -#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x00020000L -#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x01000000L -#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L -#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x00004000L -#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x00008000L -#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x00000200L -#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x00000100L -#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x00000400L -#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000L -#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000L -#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x02000000L -#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x04000000L -#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000L -#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L -#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x00000080L -#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x00000020L -#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x00000010L -#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000L -#define VGT_DEBUG_REG2__SPARE_MASK__CI__VI 0xe0000000L -#define VGT_DEBUG_REG2__SPARE_MASK__SI 0xffffffffL -#define VGT_DEBUG_REG2__grpModBusy_MASK__CI__VI 0x00000080L -#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK__CI__VI 0x00001000L -#define VGT_DEBUG_REG2__hsInputFifoFull_MASK__CI__VI 0x00040000L -#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK__CI__VI 0x00002000L -#define VGT_DEBUG_REG2__hsTifFifoFull_MASK__CI__VI 0x00080000L -#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK__CI__VI 0x00000400L -#define VGT_DEBUG_REG2__hsVertFifoFull_MASK__CI__VI 0x00010000L -#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK__CI__VI 0x00000800L -#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK__CI__VI 0x00020000L -#define VGT_DEBUG_REG2__hs_grp_busy_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG2__hs_noif_busy_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK__CI__VI 0x00000040L -#define VGT_DEBUG_REG2__lsFwaveFlag_MASK__CI__VI 0x08000000L -#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK__CI__VI 0x00000100L -#define VGT_DEBUG_REG2__lsVertFifoFull_MASK__CI__VI 0x00004000L -#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK__CI__VI 0x00000008L -#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK__CI__VI 0x00000200L -#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK__CI__VI 0x00008000L -#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK__CI__VI 0x00000020L -#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK__CI__VI 0x10000000L -#define VGT_DEBUG_REG2__ls_sh_id_MASK__CI__VI 0x04000000L -#define VGT_DEBUG_REG2__p0_dr_MASK__CI__VI 0x00400000L -#define VGT_DEBUG_REG2__p0_rtr_MASK__CI__VI 0x00100000L -#define VGT_DEBUG_REG2__p0_rts_MASK__CI__VI 0x01000000L -#define VGT_DEBUG_REG2__p1_dr_MASK__CI__VI 0x00800000L -#define VGT_DEBUG_REG2__p1_rtr_MASK__CI__VI 0x00200000L -#define VGT_DEBUG_REG2__p1_rts_MASK__CI__VI 0x02000000L -#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG2__tfmmIsBusy_MASK__CI__VI 0x00000004L -#define VGT_DEBUG_REG30__SPARE_MASK__SI 0xe0000000L -#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK__CI 0x01000000L -#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK__CI 0x00000008L -#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK__CI 0x08000000L -#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK__CI 0x04000000L -#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK__CI 0x02000000L -#define VGT_DEBUG_REG30__grpModBusy_MASK__SI 0x00000080L -#define VGT_DEBUG_REG30__hsInputFifoEmpty_MASK__SI 0x00001000L -#define VGT_DEBUG_REG30__hsInputFifoFull_MASK__SI 0x00040000L -#define VGT_DEBUG_REG30__hsTifFifoEmpty_MASK__SI 0x00002000L -#define VGT_DEBUG_REG30__hsTifFifoFull_MASK__SI 0x00080000L -#define VGT_DEBUG_REG30__hsVertFifoEmpty_MASK__SI 0x00000400L -#define VGT_DEBUG_REG30__hsVertFifoFull_MASK__SI 0x00010000L -#define VGT_DEBUG_REG30__hsWaveFifoEmpty_MASK__SI 0x00000800L -#define VGT_DEBUG_REG30__hsWaveFifoFull_MASK__SI 0x00020000L -#define VGT_DEBUG_REG30__hs_grp_busy_MASK__SI 0x00000001L -#define VGT_DEBUG_REG30__hs_noif_busy_MASK__SI 0x00000002L -#define VGT_DEBUG_REG30__hs_te11_tess_input_rts_MASK__SI 0x00000040L -#define VGT_DEBUG_REG30__last_tf_of_tg_MASK__CI 0x00080000L -#define VGT_DEBUG_REG30__lsFwaveFlag_MASK__SI 0x08000000L -#define VGT_DEBUG_REG30__lsVertFifoEmpty_MASK__SI 0x00000100L -#define VGT_DEBUG_REG30__lsVertFifoFull_MASK__SI 0x00004000L -#define VGT_DEBUG_REG30__lsVertIfBusy_0_MASK__SI 0x00000008L -#define VGT_DEBUG_REG30__lsWaveFifoEmpty_MASK__SI 0x00000200L -#define VGT_DEBUG_REG30__lsWaveFifoFull_MASK__SI 0x00008000L -#define VGT_DEBUG_REG30__lsWaveIfBusy_0_MASK__SI 0x00000020L -#define VGT_DEBUG_REG30__lsWaveSendFlush_MASK__SI 0x10000000L -#define VGT_DEBUG_REG30__ls_sh_id_MASK__SI 0x04000000L -#define VGT_DEBUG_REG30__p0_dr_MASK__SI 0x00400000L -#define VGT_DEBUG_REG30__p0_rtr_MASK__SI 0x00100000L -#define VGT_DEBUG_REG30__p0_rts_MASK__SI 0x01000000L -#define VGT_DEBUG_REG30__p1_dr_MASK__SI 0x00800000L -#define VGT_DEBUG_REG30__p1_rtr_MASK__SI 0x00200000L -#define VGT_DEBUG_REG30__p1_rts_MASK__SI 0x02000000L -#define VGT_DEBUG_REG30__pipe0_dr_MASK__CI 0x00000001L -#define VGT_DEBUG_REG30__pipe0_rtr_MASK__CI 0x00000010L -#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK__CI 0x00000002L -#define VGT_DEBUG_REG30__pipe1_rtr_MASK__CI 0x00000020L -#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK__CI 0x00000040L -#define VGT_DEBUG_REG30__pipe2_dr_MASK__CI 0x00000004L -#define VGT_DEBUG_REG30__pipe2_rtr_MASK__CI 0x00000080L -#define VGT_DEBUG_REG30__pipe4_dr_MASK__CI 0x40000000L -#define VGT_DEBUG_REG30__pipe4_rtr_MASK__CI 0x80000000L -#define VGT_DEBUG_REG30__te11_hs_tess_input_rtr_MASK__SI 0x00000010L -#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK__CI 0x00070000L -#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK__CI 0x00f00000L -#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK__CI 0x30000000L -#define VGT_DEBUG_REG30__tfmmIsBusy_MASK__SI 0x00000004L -#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK__CI 0x00000200L -#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK__CI 0x00000100L -#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK__CI 0x00000400L -#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK__CI 0x00000800L -#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK__CI 0x00001000L -#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK__CI 0x00002000L -#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK__CI 0x00004000L -#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK__CI 0x00008000L -#define VGT_DEBUG_REG31__hsWaveRelInd_MASK__SI 0xfc000000L -#define VGT_DEBUG_REG31__inner_ring_done_q_MASK__CI__VI 0x80000000L -#define VGT_DEBUG_REG31__lsPatchCnt_MASK__SI 0x03fc0000L -#define VGT_DEBUG_REG31__lsTgRelInd_MASK__SI 0x00000fffL -#define VGT_DEBUG_REG31__lsWaveRelInd_MASK__SI 0x0003f000L -#define VGT_DEBUG_REG31__outer_ring_done_q_MASK__CI__VI 0x40000000L -#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK__CI__VI 0x00400000L -#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK__CI__VI 0x00800000L -#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK__CI__VI 0x00100000L -#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK__CI__VI 0x00200000L -#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK__CI__VI 0x02000000L -#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK__CI__VI 0x10000000L -#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK__CI__VI 0x04000000L -#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK__CI__VI 0x20000000L -#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK__CI__VI 0x01000000L -#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK__CI__VI 0x08000000L -#define VGT_DEBUG_REG31__pipe0_dr_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG31__pipe0_rtr_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK__CI__VI 0x00000008L -#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK__CI__VI 0x00000004L -#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK__CI__VI 0x00000020L -#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK__CI__VI 0x00002000L -#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK__CI__VI 0x00001000L -#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK__CI__VI 0x00000080L -#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK__CI__VI 0x00008000L -#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK__CI__VI 0x00000040L -#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK__CI__VI 0x00004000L -#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK__CI__VI 0x00000200L -#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK__CI__VI 0x00020000L -#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK__CI__VI 0x00000100L -#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK__CI__VI 0x00010000L -#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK__CI__VI 0x00000800L -#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK__CI__VI 0x00080000L -#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK__CI__VI 0x00000400L -#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK__CI__VI 0x00040000L -#define VGT_DEBUG_REG32__SPARE_MASK__CI__VI 0xf0000000L -#define VGT_DEBUG_REG32__SPARE_MASK__SI 0x80000000L -#define VGT_DEBUG_REG32__event_flag_p5_q_MASK__CI__VI 0x00000100L -#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK__CI__VI 0x00000080L -#define VGT_DEBUG_REG32__fifos_rtr_MASK__CI__VI 0x08000000L -#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK__CI__VI 0x00000400L -#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK__CI__VI 0x00000200L -#define VGT_DEBUG_REG32__first_ring_of_patch_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG32__hsCpCnt_MASK__SI 0x1f000000L -#define VGT_DEBUG_REG32__hsFwaveFlag_MASK__SI 0x40000000L -#define VGT_DEBUG_REG32__hsPatchCnt_MASK__SI 0x000000ffL -#define VGT_DEBUG_REG32__hsPrimId_15_0_MASK__SI 0x00ffff00L -#define VGT_DEBUG_REG32__hsWaveSendFlush_MASK__SI 0x20000000L -#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK__CI__VI 0x01000000L -#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK__CI__VI 0x02000000L -#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK__CI__VI 0x00000004L -#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK__CI__VI 0x00000040L -#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK__CI__VI 0x00000800L -#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK__CI__VI 0x00000020L -#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK__CI__VI 0x00000008L -#define VGT_DEBUG_REG32__last_ring_of_patch_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK__CI__VI 0x04000000L -#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK__CI__VI 0x00020000L -#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK__CI__VI 0x00010000L -#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK__CI__VI 0x00100000L -#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK__CI__VI 0x00040000L -#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK__CI__VI 0x00400000L -#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK__CI__VI 0x00200000L -#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK__CI__VI 0x00080000L -#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK__CI__VI 0x00800000L -#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK__CI__VI 0x00008000L -#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK__CI__VI 0x00004000L -#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK__CI__VI 0x00003000L -#define VGT_DEBUG_REG33__SPARE1_MASK__SI 0x07000000L -#define VGT_DEBUG_REG33__SPARE2_MASK__SI 0x00070000L -#define VGT_DEBUG_REG33__SPARE3_MASK__SI 0x00000700L -#define VGT_DEBUG_REG33__SPARE4_MASK__SI 0x00000007L -#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK__CI__VI 0x00040000L -#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK__CI__VI 0x00010000L -#define VGT_DEBUG_REG33__con_ring1_busy_MASK__CI__VI 0x80000000L -#define VGT_DEBUG_REG33__con_ring2_busy_MASK__CI__VI 0x40000000L -#define VGT_DEBUG_REG33__con_ring3_busy_MASK__CI__VI 0x20000000L -#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK__CI__VI 0x00080000L -#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK__CI__VI 0x00020000L -#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK__CI__VI 0x00008000L -#define VGT_DEBUG_REG33__hsVertCreditCnt_0_MASK__SI 0x0000f800L -#define VGT_DEBUG_REG33__hsWaveCreditCnt_0_MASK__SI 0x000000f8L -#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK__CI__VI 0x00100000L -#define VGT_DEBUG_REG33__lsVertCreditCnt_0_MASK__SI 0xf8000000L -#define VGT_DEBUG_REG33__lsWaveCreditCnt_0_MASK__SI 0x00f80000L -#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG33__pipe1_dr_MASK__CI__VI 0x00000004L -#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK__CI__VI 0x00001000L -#define VGT_DEBUG_REG33__pipe2_dr_MASK__CI__VI 0x00000008L -#define VGT_DEBUG_REG33__pipe2_rtr_MASK__CI__VI 0x00000080L -#define VGT_DEBUG_REG33__pipe3_dr_MASK__CI__VI 0x00000100L -#define VGT_DEBUG_REG33__pipe3_rtr_MASK__CI__VI 0x00000200L -#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK__CI__VI 0x00000800L -#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK__CI__VI 0x00000040L -#define VGT_DEBUG_REG33__ring1_valid_p2_MASK__CI__VI 0x00800000L -#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK__CI__VI 0x00000400L -#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK__CI__VI 0x00000020L -#define VGT_DEBUG_REG33__ring2_valid_p2_MASK__CI__VI 0x00400000L -#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK__CI__VI 0x00002000L -#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG33__ring3_valid_p2_MASK__CI__VI 0x00200000L -#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK__CI__VI 0x10000000L -#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK__CI__VI 0x0c000000L -#define VGT_DEBUG_REG33__tess_type_p0_q_MASK__CI__VI 0x03000000L -#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK__CI__VI 0x00004000L -#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK__CI__VI 0x00800000L -#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK__CI__VI 0x00400000L -#define VGT_DEBUG_REG34__con_state_q_MASK__CI__VI 0x0000000fL -#define VGT_DEBUG_REG34__debug_BASE_MASK__SI 0x0000ffffL -#define VGT_DEBUG_REG34__debug_SIZE_MASK__SI 0xffff0000L -#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK__CI__VI 0x00010000L -#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK__CI__VI 0x00040000L -#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK__CI__VI 0x00100000L -#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK__CI__VI 0x00080000L -#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK__CI__VI 0x00020000L -#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK__CI__VI 0x01000000L -#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK__CI__VI 0x00200000L -#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK__CI__VI 0x00004000L -#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK__CI__VI 0x00008000L -#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK__CI__VI 0x00000200L -#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK__CI__VI 0x00001000L -#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK__CI__VI 0x00000100L -#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK__CI__VI 0x00000800L -#define VGT_DEBUG_REG34__pipe1_dr_MASK__CI__VI 0x00000400L -#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK__CI__VI 0x40000000L -#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK__CI__VI 0x08000000L -#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK__CI__VI 0x10000000L -#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK__CI__VI 0x02000000L -#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK__CI__VI 0x04000000L -#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK__CI__VI 0x20000000L -#define VGT_DEBUG_REG34__pipe1_rtr_MASK__CI__VI 0x00002000L -#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK__CI__VI 0x00000040L -#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK__CI__VI 0x00000080L -#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK__CI__VI 0x00000020L -#define VGT_DEBUG_REG34__second_cycle_q_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK__CI__VI 0x80000000L -#define VGT_DEBUG_REG35__SPARE_MASK__SI 0x0000ffe0L -#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK__CI 0x80000000L -#define VGT_DEBUG_REG35__TF_addr_MASK__SI 0xffff0000L -#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK__CI 0x40000000L -#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK__CI 0x20000000L -#define VGT_DEBUG_REG35__debug_tfmmFifoEmpty_MASK__SI 0x00000001L -#define VGT_DEBUG_REG35__debug_tfmmFifoFull_MASK__SI 0x00000002L -#define VGT_DEBUG_REG35__event_flag_p1_q_MASK__CI 0x00040000L -#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK__CI 0x10000000L -#define VGT_DEBUG_REG35__hs_pipe0_dr_MASK__SI 0x00000004L -#define VGT_DEBUG_REG35__hs_pipe0_rtr_MASK__SI 0x00000008L -#define VGT_DEBUG_REG35__hs_pipe1_rtr_MASK__SI 0x00000010L -#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK__CI 0x00000800L -#define VGT_DEBUG_REG35__null_flag_p1_q_MASK__CI 0x00080000L -#define VGT_DEBUG_REG35__pipe0_dr_MASK__CI 0x00000001L -#define VGT_DEBUG_REG35__pipe0_rtr_MASK__CI 0x00000004L -#define VGT_DEBUG_REG35__pipe1_dr_MASK__CI 0x00000002L -#define VGT_DEBUG_REG35__pipe1_rtr_MASK__CI 0x00000008L -#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK__CI 0x08000000L -#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK__CI 0x0003f000L -#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK__CI 0x00000040L -#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK__CI 0x07f00000L -#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK__CI 0x00000080L -#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK__CI 0x00000100L -#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK__CI 0x00000200L -#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK__CI 0x00000010L -#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK__CI 0x00000020L -#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK__CI 0x00000400L -#define VGT_DEBUG_REG36__cm_state0_MASK__SI 0x00000003L -#define VGT_DEBUG_REG36__cm_state10_MASK__SI 0x00300000L -#define VGT_DEBUG_REG36__cm_state11_MASK__SI 0x00c00000L -#define VGT_DEBUG_REG36__cm_state12_MASK__SI 0x03000000L -#define VGT_DEBUG_REG36__cm_state13_MASK__SI 0x0c000000L -#define VGT_DEBUG_REG36__cm_state14_MASK__SI 0x30000000L -#define VGT_DEBUG_REG36__cm_state15_MASK__SI 0xc0000000L -#define VGT_DEBUG_REG36__cm_state1_MASK__SI 0x0000000cL -#define VGT_DEBUG_REG36__cm_state2_MASK__SI 0x00000030L -#define VGT_DEBUG_REG36__cm_state3_MASK__SI 0x000000c0L -#define VGT_DEBUG_REG36__cm_state4_MASK__SI 0x00000300L -#define VGT_DEBUG_REG36__cm_state5_MASK__SI 0x00000c00L -#define VGT_DEBUG_REG36__cm_state6_MASK__SI 0x00003000L -#define VGT_DEBUG_REG36__cm_state7_MASK__SI 0x0000c000L -#define VGT_DEBUG_REG36__cm_state8_MASK__SI 0x00030000L -#define VGT_DEBUG_REG36__cm_state9_MASK__SI 0x000c0000L -#define VGT_DEBUG_REG37__dynamic_hs_p0_q_MASK__SI 0x01000000L -#define VGT_DEBUG_REG37__event_or_null_p1_MASK__SI 0x00000008L -#define VGT_DEBUG_REG37__first_data_chunk_invalid_p0_q_MASK__SI 0x08000000L -#define VGT_DEBUG_REG37__first_data_ret_of_req_p0_q_MASK__SI 0x04000000L -#define VGT_DEBUG_REG37__first_fetch_of_tg_p0_q_MASK__SI 0x02000000L -#define VGT_DEBUG_REG37__last_tf_of_tg_MASK__SI 0x00080000L -#define VGT_DEBUG_REG37__pipe0_dr_MASK__SI 0x00000001L -#define VGT_DEBUG_REG37__pipe0_rtr_MASK__SI 0x00000010L -#define VGT_DEBUG_REG37__pipe0_tf_dr_MASK__SI 0x00000002L -#define VGT_DEBUG_REG37__pipe1_rtr_MASK__SI 0x00000020L -#define VGT_DEBUG_REG37__pipe1_tf_rtr_MASK__SI 0x00000040L -#define VGT_DEBUG_REG37__pipe2_dr_MASK__SI 0x00000004L -#define VGT_DEBUG_REG37__pipe2_rtr_MASK__SI 0x00000080L -#define VGT_DEBUG_REG37__pipe4_dr_MASK__SI 0x40000000L -#define VGT_DEBUG_REG37__pipe4_rtr_MASK__SI 0x80000000L -#define VGT_DEBUG_REG37__tf_fetch_state_q_MASK__SI 0x00070000L -#define VGT_DEBUG_REG37__tf_pointer_p0_q_MASK__SI 0x00f00000L -#define VGT_DEBUG_REG37__tf_xfer_count_p2_q_MASK__SI 0x30000000L -#define VGT_DEBUG_REG37__ttp_patch_fifo_empty_MASK__SI 0x00000200L -#define VGT_DEBUG_REG37__ttp_patch_fifo_full_MASK__SI 0x00000100L -#define VGT_DEBUG_REG37__ttp_tf0_fifo_empty_MASK__SI 0x00000400L -#define VGT_DEBUG_REG37__ttp_tf1_fifo_empty_MASK__SI 0x00000800L -#define VGT_DEBUG_REG37__ttp_tf2_fifo_empty_MASK__SI 0x00001000L -#define VGT_DEBUG_REG37__ttp_tf3_fifo_empty_MASK__SI 0x00002000L -#define VGT_DEBUG_REG37__ttp_tf4_fifo_empty_MASK__SI 0x00004000L -#define VGT_DEBUG_REG37__ttp_tf5_fifo_empty_MASK__SI 0x00008000L -#define VGT_DEBUG_REG38__inner_ring_done_q_MASK__SI 0x80000000L -#define VGT_DEBUG_REG38__outer_ring_done_q_MASK__SI 0x40000000L -#define VGT_DEBUG_REG38__pg_con_inner_point1_rts_MASK__SI 0x00400000L -#define VGT_DEBUG_REG38__pg_con_inner_point2_rts_MASK__SI 0x00800000L -#define VGT_DEBUG_REG38__pg_con_outer_point1_rts_MASK__SI 0x00100000L -#define VGT_DEBUG_REG38__pg_con_outer_point2_rts_MASK__SI 0x00200000L -#define VGT_DEBUG_REG38__pg_edge_fifo_empty_MASK__SI 0x02000000L -#define VGT_DEBUG_REG38__pg_edge_fifo_full_MASK__SI 0x10000000L -#define VGT_DEBUG_REG38__pg_inner3_perp_fifo_empty_MASK__SI 0x04000000L -#define VGT_DEBUG_REG38__pg_inner_perp_fifo_full_MASK__SI 0x20000000L -#define VGT_DEBUG_REG38__pg_patch_fifo_empty_MASK__SI 0x01000000L -#define VGT_DEBUG_REG38__pg_patch_fifo_full_MASK__SI 0x08000000L -#define VGT_DEBUG_REG38__pipe0_dr_MASK__SI 0x00000001L -#define VGT_DEBUG_REG38__pipe0_rtr_MASK__SI 0x00000002L -#define VGT_DEBUG_REG38__pipe1_inner_dr_MASK__SI 0x00000008L -#define VGT_DEBUG_REG38__pipe1_outer_dr_MASK__SI 0x00000004L -#define VGT_DEBUG_REG38__pipe2_inner_dr_MASK__SI 0x00000020L -#define VGT_DEBUG_REG38__pipe2_inner_rtr_MASK__SI 0x00002000L -#define VGT_DEBUG_REG38__pipe2_outer_dr_MASK__SI 0x00000010L -#define VGT_DEBUG_REG38__pipe2_outer_rtr_MASK__SI 0x00001000L -#define VGT_DEBUG_REG38__pipe3_inner_dr_MASK__SI 0x00000080L -#define VGT_DEBUG_REG38__pipe3_inner_rtr_MASK__SI 0x00008000L -#define VGT_DEBUG_REG38__pipe3_outer_dr_MASK__SI 0x00000040L -#define VGT_DEBUG_REG38__pipe3_outer_rtr_MASK__SI 0x00004000L -#define VGT_DEBUG_REG38__pipe4_inner_dr_MASK__SI 0x00000200L -#define VGT_DEBUG_REG38__pipe4_inner_rtr_MASK__SI 0x00020000L -#define VGT_DEBUG_REG38__pipe4_outer_dr_MASK__SI 0x00000100L -#define VGT_DEBUG_REG38__pipe4_outer_rtr_MASK__SI 0x00010000L -#define VGT_DEBUG_REG38__pipe5_inner_dr_MASK__SI 0x00000800L -#define VGT_DEBUG_REG38__pipe5_inner_rtr_MASK__SI 0x00080000L -#define VGT_DEBUG_REG38__pipe5_outer_dr_MASK__SI 0x00000400L -#define VGT_DEBUG_REG38__pipe5_outer_rtr_MASK__SI 0x00040000L -#define VGT_DEBUG_REG39__SPARE_MASK__SI 0xf0000000L -#define VGT_DEBUG_REG39__event_flag_p5_q_MASK__SI 0x00000100L -#define VGT_DEBUG_REG39__event_null_special_p0_q_MASK__SI 0x00000080L -#define VGT_DEBUG_REG39__fifos_rtr_MASK__SI 0x08000000L -#define VGT_DEBUG_REG39__first_point_of_edge_p5_q_MASK__SI 0x00000400L -#define VGT_DEBUG_REG39__first_point_of_patch_p5_q_MASK__SI 0x00000200L -#define VGT_DEBUG_REG39__first_ring_of_patch_MASK__SI 0x00000001L -#define VGT_DEBUG_REG39__inner2_fifos_rtr_MASK__SI 0x01000000L -#define VGT_DEBUG_REG39__inner_fifos_rtr_MASK__SI 0x02000000L -#define VGT_DEBUG_REG39__last_edge_of_inner_ring_MASK__SI 0x00000010L -#define VGT_DEBUG_REG39__last_edge_of_outer_ring_MASK__SI 0x00000004L -#define VGT_DEBUG_REG39__last_patch_of_tg_p0_q_MASK__SI 0x00000040L -#define VGT_DEBUG_REG39__last_patch_of_tg_p5_q_MASK__SI 0x00000800L -#define VGT_DEBUG_REG39__last_point_of_inner_edge_MASK__SI 0x00000020L -#define VGT_DEBUG_REG39__last_point_of_outer_edge_MASK__SI 0x00000008L -#define VGT_DEBUG_REG39__last_ring_of_patch_MASK__SI 0x00000002L -#define VGT_DEBUG_REG39__outer_fifos_rtr_MASK__SI 0x04000000L -#define VGT_DEBUG_REG39__pg_edge_fifo2_full_MASK__SI 0x00020000L -#define VGT_DEBUG_REG39__pg_edge_fifo3_full_MASK__SI 0x00010000L -#define VGT_DEBUG_REG39__pg_inner2_point_fifo_full_MASK__SI 0x00100000L -#define VGT_DEBUG_REG39__pg_inner3_point_fifo_full_MASK__SI 0x00040000L -#define VGT_DEBUG_REG39__pg_inner_point_fifo_full_MASK__SI 0x00400000L -#define VGT_DEBUG_REG39__pg_outer2_point_fifo_full_MASK__SI 0x00200000L -#define VGT_DEBUG_REG39__pg_outer3_point_fifo_full_MASK__SI 0x00080000L -#define VGT_DEBUG_REG39__pg_outer_point_fifo_full_MASK__SI 0x00800000L -#define VGT_DEBUG_REG39__pipe5_inner2_rtr_MASK__SI 0x00008000L -#define VGT_DEBUG_REG39__pipe5_inner3_rtr_MASK__SI 0x00004000L -#define VGT_DEBUG_REG39__tess_topology_p5_q_MASK__SI 0x00003000L -#define VGT_DEBUG_REG3__SPARE_MASK__SI 0xffffffffL -#define VGT_DEBUG_REG3__hsWaveRelInd_MASK__CI__VI 0xfc000000L -#define VGT_DEBUG_REG3__lsPatchCnt_MASK__CI__VI 0x03fc0000L -#define VGT_DEBUG_REG3__lsTgRelInd_MASK__CI__VI 0x00000fffL -#define VGT_DEBUG_REG3__lsWaveRelInd_MASK__CI__VI 0x0003f000L -#define VGT_DEBUG_REG40__con_prim_fifo_empty_MASK__SI 0x00040000L -#define VGT_DEBUG_REG40__con_prim_fifo_full_MASK__SI 0x00010000L -#define VGT_DEBUG_REG40__con_ring1_busy_MASK__SI 0x80000000L -#define VGT_DEBUG_REG40__con_ring2_busy_MASK__SI 0x40000000L -#define VGT_DEBUG_REG40__con_ring3_busy_MASK__SI 0x20000000L -#define VGT_DEBUG_REG40__con_vert_fifo_empty_MASK__SI 0x00080000L -#define VGT_DEBUG_REG40__con_vert_fifo_full_MASK__SI 0x00020000L -#define VGT_DEBUG_REG40__first_prim_of_patch_q_MASK__SI 0x00008000L -#define VGT_DEBUG_REG40__last_patch_of_tg_p0_q_MASK__SI 0x00100000L -#define VGT_DEBUG_REG40__pipe0_patch_dr_MASK__SI 0x00000001L -#define VGT_DEBUG_REG40__pipe0_patch_rtr_MASK__SI 0x00000010L -#define VGT_DEBUG_REG40__pipe1_dr_MASK__SI 0x00000004L -#define VGT_DEBUG_REG40__pipe1_patch_rtr_MASK__SI 0x00001000L -#define VGT_DEBUG_REG40__pipe2_dr_MASK__SI 0x00000008L -#define VGT_DEBUG_REG40__pipe2_rtr_MASK__SI 0x00000080L -#define VGT_DEBUG_REG40__pipe3_dr_MASK__SI 0x00000100L -#define VGT_DEBUG_REG40__pipe3_rtr_MASK__SI 0x00000200L -#define VGT_DEBUG_REG40__ring1_in_sync_q_MASK__SI 0x00000800L -#define VGT_DEBUG_REG40__ring1_pipe1_dr_MASK__SI 0x00000040L -#define VGT_DEBUG_REG40__ring1_valid_p2_MASK__SI 0x00800000L -#define VGT_DEBUG_REG40__ring2_in_sync_q_MASK__SI 0x00000400L -#define VGT_DEBUG_REG40__ring2_pipe1_dr_MASK__SI 0x00000020L -#define VGT_DEBUG_REG40__ring2_valid_p2_MASK__SI 0x00400000L -#define VGT_DEBUG_REG40__ring3_in_sync_q_MASK__SI 0x00002000L -#define VGT_DEBUG_REG40__ring3_pipe1_dr_MASK__SI 0x00000002L -#define VGT_DEBUG_REG40__ring3_valid_p2_MASK__SI 0x00200000L -#define VGT_DEBUG_REG40__te11_out_vert_gs_en_MASK__SI 0x10000000L -#define VGT_DEBUG_REG40__tess_topology_p0_q_MASK__SI 0x0c000000L -#define VGT_DEBUG_REG40__tess_type_p0_q_MASK__SI 0x03000000L -#define VGT_DEBUG_REG40__tm_te11_event_rtr_MASK__SI 0x00004000L -#define VGT_DEBUG_REG41__advance_inner_point_p1_MASK__SI 0x00800000L -#define VGT_DEBUG_REG41__advance_outer_point_p1_MASK__SI 0x00400000L -#define VGT_DEBUG_REG41__con_state_q_MASK__SI 0x0000000fL -#define VGT_DEBUG_REG41__first_ring_of_patch_p0_q_MASK__SI 0x00010000L -#define VGT_DEBUG_REG41__last_edge_of_outer_ring_p0_q_MASK__SI 0x00040000L -#define VGT_DEBUG_REG41__last_point_of_inner_ring_p1_MASK__SI 0x00100000L -#define VGT_DEBUG_REG41__last_point_of_outer_ring_p1_MASK__SI 0x00080000L -#define VGT_DEBUG_REG41__last_ring_of_patch_p0_q_MASK__SI 0x00020000L -#define VGT_DEBUG_REG41__next_ring_is_rect_p0_q_MASK__SI 0x01000000L -#define VGT_DEBUG_REG41__outer_edge_tf_eq_one_p0_q_MASK__SI 0x00200000L -#define VGT_DEBUG_REG41__outer_parity_p0_q_MASK__SI 0x00004000L -#define VGT_DEBUG_REG41__parallel_parity_p0_q_MASK__SI 0x00008000L -#define VGT_DEBUG_REG41__pipe0_edge_dr_MASK__SI 0x00000200L -#define VGT_DEBUG_REG41__pipe0_edge_rtr_MASK__SI 0x00001000L -#define VGT_DEBUG_REG41__pipe0_patch_dr_MASK__SI 0x00000100L -#define VGT_DEBUG_REG41__pipe0_patch_rtr_MASK__SI 0x00000800L -#define VGT_DEBUG_REG41__pipe1_dr_MASK__SI 0x00000400L -#define VGT_DEBUG_REG41__pipe1_edge_rtr_MASK__SI 0x40000000L -#define VGT_DEBUG_REG41__pipe1_inner1_rtr_MASK__SI 0x08000000L -#define VGT_DEBUG_REG41__pipe1_inner2_rtr_MASK__SI 0x10000000L -#define VGT_DEBUG_REG41__pipe1_outer1_rtr_MASK__SI 0x02000000L -#define VGT_DEBUG_REG41__pipe1_outer2_rtr_MASK__SI 0x04000000L -#define VGT_DEBUG_REG41__pipe1_patch_rtr_MASK__SI 0x20000000L -#define VGT_DEBUG_REG41__pipe1_rtr_MASK__SI 0x00002000L -#define VGT_DEBUG_REG41__process_tri_1st_2nd_half_p0_q_MASK__SI 0x00000040L -#define VGT_DEBUG_REG41__process_tri_center_poly_p0_q_MASK__SI 0x00000080L -#define VGT_DEBUG_REG41__process_tri_middle_p0_q_MASK__SI 0x00000020L -#define VGT_DEBUG_REG41__second_cycle_q_MASK__SI 0x00000010L -#define VGT_DEBUG_REG41__use_stored_inner_q_ring1_MASK__SI 0x80000000L -#define VGT_DEBUG_REG42__TC_VGT_rdret_data_in_MASK__SI 0x80000000L -#define VGT_DEBUG_REG42__VGT_TC_rdnfo_stall_out_MASK__SI 0x40000000L -#define VGT_DEBUG_REG42__VGT_TC_rdreq_send_out_MASK__SI 0x20000000L -#define VGT_DEBUG_REG42__event_flag_p1_q_MASK__SI 0x00040000L -#define VGT_DEBUG_REG42__first_req_of_tg_p1_q_MASK__SI 0x10000000L -#define VGT_DEBUG_REG42__last_req_of_tg_p2_MASK__SI 0x00000800L -#define VGT_DEBUG_REG42__null_flag_p1_q_MASK__SI 0x00080000L -#define VGT_DEBUG_REG42__pipe0_dr_MASK__SI 0x00000001L -#define VGT_DEBUG_REG42__pipe0_rtr_MASK__SI 0x00000004L -#define VGT_DEBUG_REG42__pipe1_dr_MASK__SI 0x00000002L -#define VGT_DEBUG_REG42__pipe1_rtr_MASK__SI 0x00000008L -#define VGT_DEBUG_REG42__second_tf_ret_data_q_MASK__SI 0x08000000L -#define VGT_DEBUG_REG42__spi_vgt_hs_done_cnt_q_MASK__SI 0x0003f000L -#define VGT_DEBUG_REG42__tf_data_fifo_busy_q_MASK__SI 0x00000040L -#define VGT_DEBUG_REG42__tf_data_fifo_cnt_q_MASK__SI 0x07f00000L -#define VGT_DEBUG_REG42__tf_data_fifo_rtr_q_MASK__SI 0x00000080L -#define VGT_DEBUG_REG42__tf_skid_fifo_empty_MASK__SI 0x00000100L -#define VGT_DEBUG_REG42__tf_skid_fifo_full_MASK__SI 0x00000200L -#define VGT_DEBUG_REG42__tfreq_tg_fifo_empty_MASK__SI 0x00000010L -#define VGT_DEBUG_REG42__tfreq_tg_fifo_full_MASK__SI 0x00000020L -#define VGT_DEBUG_REG42__vgt_tc_rdreq_rtr_q_MASK__SI 0x00000400L -#define VGT_DEBUG_REG4__SPARE_MASK__CI__VI 0x80000000L -#define VGT_DEBUG_REG4__SPARE_MASK__SI 0xffffffffL -#define VGT_DEBUG_REG4__hsCpCnt_MASK__CI__VI 0x1f000000L -#define VGT_DEBUG_REG4__hsFwaveFlag_MASK__CI__VI 0x40000000L -#define VGT_DEBUG_REG4__hsPatchCnt_MASK__CI__VI 0x000000ffL -#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK__CI__VI 0x00ffff00L -#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK__CI__VI 0x20000000L -#define VGT_DEBUG_REG5__SPARE1_MASK__CI__VI 0x07000000L -#define VGT_DEBUG_REG5__SPARE2_MASK__CI__VI 0x00070000L -#define VGT_DEBUG_REG5__SPARE3_MASK__CI__VI 0x00000700L -#define VGT_DEBUG_REG5__SPARE4_MASK__CI__VI 0x00000007L -#define VGT_DEBUG_REG5__SPARE_MASK__SI 0xffffffffL -#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK__CI__VI 0x0000f800L -#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK__CI__VI 0x000000f8L -#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK__CI__VI 0xf8000000L -#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK__CI__VI 0x00f80000L -#define VGT_DEBUG_REG6__SPARE_MASK__SI 0xffffffffL -#define VGT_DEBUG_REG6__debug_BASE_MASK__CI__VI 0x0000ffffL -#define VGT_DEBUG_REG6__debug_SIZE_MASK__CI__VI 0xffff0000L -#define VGT_DEBUG_REG7__SPARE_MASK__CI__VI 0x0000ffe0L -#define VGT_DEBUG_REG7__TF_addr_MASK__CI__VI 0xffff0000L -#define VGT_DEBUG_REG7__components_valid_r0_q_MASK__SI 0xe0000000L -#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG7__eject_vtx_vect_r1_d_MASK__SI 0x00800000L -#define VGT_DEBUG_REG7__eop_r0_q_MASK__SI 0x00400000L -#define VGT_DEBUG_REG7__grp_vr_valid_MASK__SI 0x00000001L -#define VGT_DEBUG_REG7__gs_scenario_a_r0_q_MASK__SI 0x08000000L -#define VGT_DEBUG_REG7__gs_scenario_b_r0_q_MASK__SI 0x10000000L -#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK__CI__VI 0x00000004L -#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK__CI__VI 0x00000008L -#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK__CI__VI 0x00000010L -#define VGT_DEBUG_REG7__indices_to_send_q_MASK__SI 0x00000700L -#define VGT_DEBUG_REG7__indx0_hit_d_MASK__SI 0x00040000L -#define VGT_DEBUG_REG7__indx0_new_d_MASK__SI 0x00002000L -#define VGT_DEBUG_REG7__indx1_hit_d_MASK__SI 0x00020000L -#define VGT_DEBUG_REG7__indx1_new_d_MASK__SI 0x00004000L -#define VGT_DEBUG_REG7__indx2_hit_d_MASK__SI 0x00010000L -#define VGT_DEBUG_REG7__indx2_new_d_MASK__SI 0x00008000L -#define VGT_DEBUG_REG7__last_group_of_instance_r0_q_MASK__SI 0x00100000L -#define VGT_DEBUG_REG7__last_indx_of_prim_MASK__SI 0x00001000L -#define VGT_DEBUG_REG7__null_primitive_r0_q_MASK__SI 0x00200000L -#define VGT_DEBUG_REG7__out_vr_indx_read_MASK__SI 0x00000040L -#define VGT_DEBUG_REG7__out_vr_prim_read_MASK__SI 0x00000080L -#define VGT_DEBUG_REG7__pipe0_dr_MASK__SI 0x00000002L -#define VGT_DEBUG_REG7__pipe0_rtr_MASK__SI 0x00000010L -#define VGT_DEBUG_REG7__pipe1_dr_MASK__SI 0x00000004L -#define VGT_DEBUG_REG7__pipe1_rtr_MASK__SI 0x00000020L -#define VGT_DEBUG_REG7__st_vertex_reuse_off_r0_q_MASK__SI 0x00080000L -#define VGT_DEBUG_REG7__sub_prim_type_r0_q_MASK__SI 0x07000000L -#define VGT_DEBUG_REG7__valid_indices_MASK__SI 0x00000800L -#define VGT_DEBUG_REG7__vr_grp_read_MASK__SI 0x00000008L -#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x00400000L -#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x00080000L -#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x00004000L -#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x02000000L -#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x00008000L -#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x00020000L -#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x00000020L -#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x04000000L -#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x08000000L -#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x01000000L -#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x00040000L -#define VGT_DEBUG_REG8__r0_rtr_MASK 0x00000400L -#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x00000004L -#define VGT_DEBUG_REG8__r1_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x00800000L -#define VGT_DEBUG_REG8__r2_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG8__rcm_busy_MASK__SI 0x00000001L -#define VGT_DEBUG_REG8__rcm_busy_q_MASK__CI__VI 0x00000001L -#define VGT_DEBUG_REG8__rcm_noif_busy_MASK__SI 0x00000002L -#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK__CI__VI 0x00000002L -#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x00000010L -#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x00000008L -#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000L -#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000L -#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000L -#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000L -#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x00200000L -#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x00010000L -#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x00100000L -#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x00000040L -#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x00000080L -#define VGT_DEBUG_REG8__valid_r2_MASK 0x00000100L -#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x00000200L -#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000L -#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x00000010L -#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x00000020L -#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x00000040L -#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x02000000L -#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x00000080L -#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x00000008L -#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x01000000L -#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x00400000L -#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x04000000L -#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x00040000L -#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x00000400L -#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x0003f800L -#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x00380000L -#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x00000003L -#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x00800000L -#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000L -#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x00000200L -#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x00000100L -#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x00000004L -#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000L -#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000L -#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x000000ffL -#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK__CI__VI 0x00020000L -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK__CI__VI 0x0000ffffL -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK__CI__VI 0x00100000L -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001ffL -#define VGT_DMA_INDEX_TYPE__ATC_MASK__CI 0x00000100L -#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK__CI__VI 0x00000030L -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK__CI__VI 0x00000200L -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK__CI 0x000000c0L -#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK__CI__VI 0x00000400L -#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000cL -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK__CI__VI 0x00003f00L -#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffffL -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK__CI__VI 0x0000003fL -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003fL -#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffffL -#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000cL -#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L -#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L -#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003fL -#define VGT_ENHANCE__MISC_MASK 0xffffffffL -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL -#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL -#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007ffL -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0fffffffL -#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07fc0000L -#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003fff00L -#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L -#define VGT_FIFO_DEPTHS__RESERVED_1_MASK__CI 0x00400000L -#define VGT_FIFO_DEPTHS__RESERVED_1_MASK__SI 0xffc00000L -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007fL -#define VGT_GROUP_DECR__DECR_MASK 0x0000000fL -#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000fL -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001fL -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00ff0000L -#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000ff00L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0f000000L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000L -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000fL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000f0L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000f00L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000f0000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00ff0000L -#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000ff00L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0f000000L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000L -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000fL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000f0L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000f00L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000f0000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL -#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007fffL -#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007fffL -#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007fffL -#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL -#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001fcL -#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007ffL -#define VGT_GS_MODE__COMPUTE_MODE_MASK__SI__CI 0x00004000L -#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L -#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK__SI__CI 0x00010000L -#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L -#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK__SI__CI 0x00008000L -#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L -#define VGT_GS_MODE__MODE_MASK 0x00000007L -#define VGT_GS_MODE__ONCHIP_MASK__CI__VI 0x00600000L -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L -#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L -#define VGT_GS_MODE__RESERVED_1_MASK 0x000007c0L -#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L -#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK__CI__VI 0x000007ffL -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK__CI__VI 0x003ff800L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003f00L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003f0000L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0fc00000L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003fL -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L -#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007ffL -#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000fL -#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001fL -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007fffL -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007fffL -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007fffL -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL -#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffffL -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffffL -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000ffL -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK__CI__VI 0x000001ffL -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK__SI 0x0000007fL -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK__CI__VI 0x00000600L -#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL -#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffffL -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffffL -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffffL -#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L -#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003f00L -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000fc000L -#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000ffL -#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffffL -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x00000003L -#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffffL -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffffL -#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffffL -#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007fL -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK__CI__VI 0xf0000000L -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK__CI__VI 0x0f000000L -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK__CI__VI 0x000003ffL -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK__CI__VI 0x000ffc00L -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK__CI__VI 0x00f00000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK__CI__VI 0x0f000000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK__CI__VI 0x000ffc00L -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000003ffL -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK__SI 0x000000ffL -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000ffL -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L -#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffffL -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003fL -#define VGT_RESET_DEBUG__GS_DISABLE_MASK__CI__VI 0x00000001L -#define VGT_RESET_DEBUG__TESS_DISABLE_MASK__CI__VI 0x00000002L -#define VGT_RESET_DEBUG__WD_DISABLE_MASK__CI__VI 0x00000004L -#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L -#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L -#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L -#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L -#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L -#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L -#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000c0L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000fL -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000f0L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000f00L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000f000L -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000f00L -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK__CI__VI 0x00000700L -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK__CI__VI 0x00003800L -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK__CI__VI 0x0001c000L -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK__CI__VI 0x000e0000L -#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK__CI__VI 0x000000ffL -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffffL -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffffL -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001ffL -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003ffL -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003ffL -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003ffL -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003ffL -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L -#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007eL -#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffffL -#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L -#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L -#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003c00L -#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001cL -#define VGT_TF_PARAM__RDREQ_POLICY_MASK__CI 0x00018000L -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L -#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000e0L -#define VGT_TF_PARAM__TYPE_MASK 0x00000003L -#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000ffffL -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000ffL -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK__CI__VI 0x00000fffL -#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003ffL -#define VID_BUFFER_CONTROL__CAP0_ANC_VBI_QUAD_BUF_MASK__SI 0x00020000L -#define VID_BUFFER_CONTROL__CAP0_BUFFER_EMPTY_MASK__SI 0x01000000L -#define VID_BUFFER_CONTROL__CAP0_BUFFER_WATER_MARK_MASK__SI 0x000003ffL -#define VID_BUFFER_CONTROL__CAP_SWAP_MASK__SI 0x00600000L -#define VID_BUFFER_CONTROL__CAP_URGENT_EN_MASK__SI 0x80000000L -#define VID_BUFFER_CONTROL__FULL_BUFFER_EN_MASK__SI 0x00010000L -#define VID_BUFFER_CONTROL__VID_BUFFER_RESET_MASK__SI 0x00100000L -#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK__SI 0x00003fffL -#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK__SI 0x3fff0000L -#define VIEWPORT_START__VIEWPORT_X_START_MASK__SI 0x1fff0000L -#define VIEWPORT_START__VIEWPORT_Y_START_MASK__SI 0x00001fffL -#define VIPH_CH0_ABCNT__VIPH_CH0_ACNT_MASK__SI 0x000fffffL -#define VIPH_CH0_ADDR__VIPH_CH0_AD_MASK__SI 0x000000ffL -#define VIPH_CH0_DATA__VIPH_CH0_DT_MASK__SI 0xffffffffL -#define VIPH_CH0_SBCNT__VIPH_CH0_SCNT_MASK__SI 0x000fffffL -#define VIPH_CH1_ABCNT__VIPH_CH1_ACNT_MASK__SI 0x000fffffL -#define VIPH_CH1_ADDR__VIPH_CH1_AD_MASK__SI 0x000000ffL -#define VIPH_CH1_DATA__VIPH_CH1_DT_MASK__SI 0xffffffffL -#define VIPH_CH1_SBCNT__VIPH_CH1_SCNT_MASK__SI 0x000fffffL -#define VIPH_CH2_ABCNT__VIPH_CH2_ACNT_MASK__SI 0x000fffffL -#define VIPH_CH2_ADDR__VIPH_CH2_AD_MASK__SI 0x000000ffL -#define VIPH_CH2_DATA__VIPH_CH2_DT_MASK__SI 0xffffffffL -#define VIPH_CH2_SBCNT__VIPH_CH2_SCNT_MASK__SI 0x000fffffL -#define VIPH_CH3_ABCNT__VIPH_CH3_ACNT_MASK__SI 0x000fffffL -#define VIPH_CH3_ADDR__VIPH_CH3_AD_MASK__SI 0x000000ffL -#define VIPH_CH3_DATA__VIPH_CH3_DT_MASK__SI 0xffffffffL -#define VIPH_CH3_SBCNT__VIPH_CH3_SCNT_MASK__SI 0x000fffffL -#define VIPH_CONTROL__VIPH_CLK_SEL_MASK__SI 0x000000ffL -#define VIPH_CONTROL__VIPH_DMA_MODE_MASK__SI 0x00100000L -#define VIPH_CONTROL__VIPH_DV0_WID_MASK__SI 0x01000000L -#define VIPH_CONTROL__VIPH_DV1_WID_MASK__SI 0x02000000L -#define VIPH_CONTROL__VIPH_DV2_WID_MASK__SI 0x04000000L -#define VIPH_CONTROL__VIPH_DV3_WID_MASK__SI 0x08000000L -#define VIPH_CONTROL__VIPH_EN_MASK__SI 0x00200000L -#define VIPH_CONTROL__VIPH_INT_SEL_MASK__SI 0x40000000L -#define VIPH_CONTROL__VIPH_MAX_WAIT_MASK__SI 0x000f0000L -#define VIPH_CONTROL__VIPH_PWR_DOWN_AK_MASK__SI 0x10000000L -#define VIPH_CONTROL__VIPH_PWR_DOWN_MASK__SI 0x10000000L -#define VIPH_CONTROL__VIPH_REG_RDY_MASK__SI 0x00002000L -#define VIPH_CONTROL__VIPH_VIPCLK_DIS_MASK__SI 0x20000000L -#define VIPH_CONTROL__VIP_DEVICE_MASK__SI 0x00800000L -#define VIPH_CONTROL__VIP_DEVICE_STRAP_DIS_MASK__SI 0x80000000L -#define VIPH_DMA_CHUNK__VIPH_CH0_ABORT_MASK__SI 0x00010000L -#define VIPH_DMA_CHUNK__VIPH_CH0_CHUNK_MASK__SI 0x0000000fL -#define VIPH_DMA_CHUNK__VIPH_CH1_ABORT_MASK__SI 0x00020000L -#define VIPH_DMA_CHUNK__VIPH_CH1_CHUNK_MASK__SI 0x00000030L -#define VIPH_DMA_CHUNK__VIPH_CH2_ABORT_MASK__SI 0x00040000L -#define VIPH_DMA_CHUNK__VIPH_CH2_CHUNK_MASK__SI 0x000000c0L -#define VIPH_DMA_CHUNK__VIPH_CH3_ABORT_MASK__SI 0x00080000L -#define VIPH_DMA_CHUNK__VIPH_CH3_CHUNK_MASK__SI 0x00000300L -#define VIPH_DV_INT__VIPH_DV0_AK_MASK__SI 0x00000010L -#define VIPH_DV_INT__VIPH_DV0_INT_EN_MASK__SI 0x00000001L -#define VIPH_DV_INT__VIPH_DV0_INT_MASK__SI 0x00000010L -#define VIPH_DV_INT__VIPH_DV1_AK_MASK__SI 0x00000020L -#define VIPH_DV_INT__VIPH_DV1_INT_EN_MASK__SI 0x00000002L -#define VIPH_DV_INT__VIPH_DV1_INT_MASK__SI 0x00000020L -#define VIPH_DV_INT__VIPH_DV2_AK_MASK__SI 0x00000040L -#define VIPH_DV_INT__VIPH_DV2_INT_EN_MASK__SI 0x00000004L -#define VIPH_DV_INT__VIPH_DV2_INT_MASK__SI 0x00000040L -#define VIPH_DV_INT__VIPH_DV3_AK_MASK__SI 0x00000080L -#define VIPH_DV_INT__VIPH_DV3_INT_EN_MASK__SI 0x00000008L -#define VIPH_DV_INT__VIPH_DV3_INT_MASK__SI 0x00000080L -#define VIPH_DV_LAT__VIPH_DV0_LAT_MASK__SI 0x000f0000L -#define VIPH_DV_LAT__VIPH_DV1_LAT_MASK__SI 0x00f00000L -#define VIPH_DV_LAT__VIPH_DV2_LAT_MASK__SI 0x0f000000L -#define VIPH_DV_LAT__VIPH_DV3_LAT_MASK__SI 0xf0000000L -#define VIPH_DV_LAT__VIPH_TIME_UNIT_MASK__SI 0x00000fffL -#define VIPH_READ_URG__VIPH_CH0_RURG_MASK__SI 0x000000ffL -#define VIPH_READ_URG__VIPH_CH1_RURG_MASK__SI 0x0000ff00L -#define VIPH_READ_URG__VIPH_CH2_RURG_MASK__SI 0x00ff0000L -#define VIPH_READ_URG__VIPH_CH3_RURG_MASK__SI 0xff000000L -#define VIPH_REG_ADDR__VIPH_REG_AD_MASK__SI 0x0000ffffL -#define VIPH_REG_DATA__VIPH_REG_DT_R_MASK__SI 0xffffffffL -#define VIPH_REG_DATA__VIPH_REG_DT_W_MASK__SI 0xffffffffL -#define VIPH_TIMEOUT_STAT__VIPH_AUTO_INT_AK_MASK__SI 0x00000020L -#define VIPH_TIMEOUT_STAT__VIPH_AUTO_INT_MASK_MASK__SI 0x00002000L -#define VIPH_TIMEOUT_STAT__VIPH_AUTO_INT_STAT_MASK__SI 0x00000020L -#define VIPH_TIMEOUT_STAT__VIPH_DV0_INT_MASK_MASK__SI 0x00010000L -#define VIPH_TIMEOUT_STAT__VIPH_DV1_INT_MASK_MASK__SI 0x00020000L -#define VIPH_TIMEOUT_STAT__VIPH_DV2_INT_MASK_MASK__SI 0x00040000L -#define VIPH_TIMEOUT_STAT__VIPH_DV3_INT_MASK_MASK__SI 0x00080000L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_AK_MASK__SI 0x00000001L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_MASK_MASK__SI 0x00000100L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_STAT_MASK__SI 0x00000001L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_AK_MASK__SI 0x00000002L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_MASK_MASK__SI 0x00000200L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_STAT_MASK__SI 0x00000002L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_AK_MASK__SI 0x00000004L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_MASK_MASK__SI 0x00000400L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_STAT_MASK__SI 0x00000004L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_AK_MASK__SI 0x00000008L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_MASK_MASK__SI 0x00000800L -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_STAT_MASK__SI 0x00000008L -#define VIPH_TIMEOUT_STAT__VIPH_INTPIN_EN_MASK__SI 0x00100000L -#define VIPH_TIMEOUT_STAT__VIPH_INTPIN_INT_MASK__SI 0x00200000L -#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS_MASK__SI 0x01000000L -#define VIPH_TIMEOUT_STAT__VIPH_REG_AK_MASK__SI 0x00000010L -#define VIPH_TIMEOUT_STAT__VIPH_REG_MASK_MASK__SI 0x00001000L -#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT_MASK__SI 0x00000010L -#define VIPH_TIMEOUT_STAT__VIP_RBBMIF_RDWR_TIMEOUT_DIS_MASK__SI 0x80000000L -#define VIPH_WRCOMB_STALL__VIPH_WRCOMB_STALL_AK_MASK__SI 0x00000001L -#define VIPH_WRCOMB_STALL__VIPH_WRCOMB_STALL_MASK__SI 0x00000001L -#define VIPH_WRCOMB_STAT0__THR_CNT_MASK__SI 0x0000ffffL -#define VIPH_WRCOMB_STAT0__TOUT_CNT_MASK__SI 0xffff0000L -#define VIPH_WRCOMB_STAT1__CHS_CNT_MASK__SI 0xffff0000L -#define VIPH_WRCOMB_STAT1__DONE_CNT_MASK__SI 0x0000ffffL -#define VIPPAD_A__VIPPAD_A_DVALID_MASK__SI 0x00020000L -#define VIPPAD_A__VIPPAD_A_PSYNC_MASK__SI 0x00040000L -#define VIPPAD_A__VIPPAD_A_SCL_MASK__SI 0x00000001L -#define VIPPAD_A__VIPPAD_A_SDA_MASK__SI 0x00000002L -#define VIPPAD_A__VIPPAD_A_VHAD_MASK__SI 0x0000000cL -#define VIPPAD_A__VIPPAD_A_VID_MASK__SI 0x0000ff00L -#define VIPPAD_A__VIPPAD_A_VIPCLK_MASK__SI 0x00000020L -#define VIPPAD_A__VIPPAD_A_VPCLK0_MASK__SI 0x00010000L -#define VIPPAD_A__VIPPAD_A_VPHCTL_MASK__SI 0x00000010L -#define VIPPAD_EN__VIPPAD_EN_DVALID_MASK__SI 0x00020000L -#define VIPPAD_EN__VIPPAD_EN_PSYNC_MASK__SI 0x00040000L -#define VIPPAD_EN__VIPPAD_EN_SCL_MASK__SI 0x00000001L -#define VIPPAD_EN__VIPPAD_EN_SDA_MASK__SI 0x00000002L -#define VIPPAD_EN__VIPPAD_EN_VHAD_MASK__SI 0x0000000cL -#define VIPPAD_EN__VIPPAD_EN_VID_MASK__SI 0x0000ff00L -#define VIPPAD_EN__VIPPAD_EN_VIPCLK_MASK__SI 0x00000020L -#define VIPPAD_EN__VIPPAD_EN_VPCLK0_MASK__SI 0x00010000L -#define VIPPAD_EN__VIPPAD_EN_VPHCTL_MASK__SI 0x00000010L -#define VIPPAD_MASK__VIPPAD_MASK_DVALID_MASK__SI 0x00020000L -#define VIPPAD_MASK__VIPPAD_MASK_PSYNC_MASK__SI 0x00040000L -#define VIPPAD_MASK__VIPPAD_MASK_SCL_MASK__SI 0x00000001L -#define VIPPAD_MASK__VIPPAD_MASK_SDA_MASK__SI 0x00000002L -#define VIPPAD_MASK__VIPPAD_MASK_VHAD_MASK__SI 0x0000000cL -#define VIPPAD_MASK__VIPPAD_MASK_VID_MASK__SI 0x0000ff00L -#define VIPPAD_MASK__VIPPAD_MASK_VIPCLK_MASK__SI 0x00000020L -#define VIPPAD_MASK__VIPPAD_MASK_VPCLK0_MASK__SI 0x00010000L -#define VIPPAD_MASK__VIPPAD_MASK_VPHCTL_MASK__SI 0x00000010L -#define VIPPAD_PD_DIS__VIPPAD_DVALID_PD_DIS_MASK__SI 0x00020000L -#define VIPPAD_PD_DIS__VIPPAD_PSYNC_PD_DIS_MASK__SI 0x00040000L -#define VIPPAD_PD_DIS__VIPPAD_SCL_PD_DIS_MASK__SI 0x00000001L -#define VIPPAD_PD_DIS__VIPPAD_SDA_PD_DIS_MASK__SI 0x00000002L -#define VIPPAD_PD_DIS__VIPPAD_VHAD_PD_DIS_MASK__SI 0x0000000cL -#define VIPPAD_PD_DIS__VIPPAD_VID_PD_DIS_MASK__SI 0x0000ff00L -#define VIPPAD_PD_DIS__VIPPAD_VIPCLK_PD_DIS_MASK__SI 0x00000020L -#define VIPPAD_PD_DIS__VIPPAD_VPCLK0_PD_DIS_MASK__SI 0x00010000L -#define VIPPAD_PD_DIS__VIPPAD_VPHCTL_PD_DIS_MASK__SI 0x00000010L -#define VIPPAD_RECV__VIPPAD_DVALID_RECV_MASK__SI 0x00020000L -#define VIPPAD_RECV__VIPPAD_PSYNC_RECV_MASK__SI 0x00040000L -#define VIPPAD_RECV__VIPPAD_SCL_RECV_MASK__SI 0x00000001L -#define VIPPAD_RECV__VIPPAD_SDA_RECV_MASK__SI 0x00000002L -#define VIPPAD_RECV__VIPPAD_VHAD_RECV_MASK__SI 0x0000000cL -#define VIPPAD_RECV__VIPPAD_VID_RECV_MASK__SI 0x0000ff00L -#define VIPPAD_RECV__VIPPAD_VIPCLK_RECV_MASK__SI 0x00000020L -#define VIPPAD_RECV__VIPPAD_VPCLK0_RECV_MASK__SI 0x00010000L -#define VIPPAD_RECV__VIPPAD_VPHCTL_RECV_MASK__SI 0x00000010L -#define VIPPAD_STRENGTH__I2C_STRENGTH_SN_MASK__SI 0x0000000fL -#define VIPPAD_STRENGTH__I2C_STRENGTH_SP_MASK__SI 0x000000f0L -#define VIPPAD_STRENGTH__VIDCAP_STRENGTH_SN_MASK__SI 0x0f000000L -#define VIPPAD_STRENGTH__VIDCAP_STRENGTH_SP_MASK__SI 0xf0000000L -#define VIPPAD_STRENGTH__VIPHCLK_STRENGTH_SN_MASK__SI 0x000f0000L -#define VIPPAD_STRENGTH__VIPHCLK_STRENGTH_SP_MASK__SI 0x00f00000L -#define VIPPAD_STRENGTH__VIPHDAT_STRENGTH_SN_MASK__SI 0x00000f00L -#define VIPPAD_STRENGTH__VIPHDAT_STRENGTH_SP_MASK__SI 0x0000f000L -#define VIPPAD_Y__VIPPAD_Y_DVALID_MASK__SI 0x00020000L -#define VIPPAD_Y__VIPPAD_Y_PSYNC_MASK__SI 0x00040000L -#define VIPPAD_Y__VIPPAD_Y_SCL_MASK__SI 0x00000001L -#define VIPPAD_Y__VIPPAD_Y_SDA_MASK__SI 0x00000002L -#define VIPPAD_Y__VIPPAD_Y_VHAD_MASK__SI 0x0000000cL -#define VIPPAD_Y__VIPPAD_Y_VID_MASK__SI 0x0000ff00L -#define VIPPAD_Y__VIPPAD_Y_VIPCLK_MASK__SI 0x00000020L -#define VIPPAD_Y__VIPPAD_Y_VPCLK0_MASK__SI 0x00010000L -#define VIPPAD_Y__VIPPAD_Y_VPHCTL_MASK__SI 0x00000010L -#define VIP_DCCIF_CNTL__VIP_DCCIF_ALIGN64BYTE_MASK__SI 0x00000300L -#define VIP_DCCIF_CNTL__VIP_DCCIF_TIMEOUT_MASK__SI 0x0000003fL -#define VIP_DCCIF_CNTL__VIP_DCCIF_W256ONLY_MASK__SI 0x00001000L -#define VIP_HW_DEBUG__VIPDMA_MH_ACK_REQ_AK_MASK__SI 0x00000020L -#define VIP_HW_DEBUG__VIPDMA_MH_ACK_REQ_EN_MASK__SI 0x00000008L -#define VIP_HW_DEBUG__VIPDMA_MH_ACK_REQ_STATUS_MASK__SI 0x00000010L -#define VIP_HW_DEBUG__VIP_HW_0_DEBUG_MASK__SI 0x00000001L -#define VIP_HW_DEBUG__VIP_HW_1_DEBUG_MASK__SI 0x00000002L -#define VIP_HW_DEBUG__VIP_HW_2_DEBUG_MASK__SI 0x00000004L -#define VIP_HW_DEBUG__VIP_HW_6_DEBUG_MASK__SI 0x00000040L -#define VIP_HW_DEBUG__VIP_HW_7_DEBUG_MASK__SI 0x00000080L -#define VIP_HW_DEBUG__VIP_HW_8_DEBUG_MASK__SI 0x00000100L -#define VIP_HW_DEBUG__VIP_HW_9_DEBUG_MASK__SI 0x00000200L -#define VIP_HW_DEBUG__VIP_HW_A_DEBUG_MASK__SI 0x00000400L -#define VIP_HW_DEBUG__VIP_HW_B_DEBUG_MASK__SI 0x00000800L -#define VIP_HW_DEBUG__VIP_HW_C_DEBUG_MASK__SI 0x00001000L -#define VIP_HW_DEBUG__VIP_HW_D_DEBUG_MASK__SI 0x00002000L -#define VIP_HW_DEBUG__VIP_HW_E_DEBUG_MASK__SI 0x00004000L -#define VIP_HW_DEBUG__VIP_HW_F_DEBUG_MASK__SI 0x00008000L -#define VIP_INT__CAP0_INT_ACTIVE_MASK__SI 0x00004000L -#define VIP_INT__DMA_VIPH0_INT_AK_MASK__SI 0x00010000L -#define VIP_INT__DMA_VIPH0_INT_EN_MASK__SI 0x00000001L -#define VIP_INT__DMA_VIPH0_INT_MASK__SI 0x00000100L -#define VIP_INT__DMA_VIPH1_INT_AK_MASK__SI 0x00020000L -#define VIP_INT__DMA_VIPH1_INT_EN_MASK__SI 0x00000002L -#define VIP_INT__DMA_VIPH1_INT_MASK__SI 0x00000200L -#define VIP_INT__DMA_VIPH2_INT_AK_MASK__SI 0x00040000L -#define VIP_INT__DMA_VIPH2_INT_EN_MASK__SI 0x00000004L -#define VIP_INT__DMA_VIPH2_INT_MASK__SI 0x00000400L -#define VIP_INT__DMA_VIPH3_INT_AK_MASK__SI 0x00080000L -#define VIP_INT__DMA_VIPH3_INT_EN_MASK__SI 0x00000008L -#define VIP_INT__DMA_VIPH3_INT_MASK__SI 0x00000800L -#define VIP_INT__I2C_INT_AK_MASK__SI 0x00100000L -#define VIP_INT__I2C_INT_EN_MASK__SI 0x00000010L -#define VIP_INT__I2C_INT_MASK__SI 0x00001000L -#define VIP_INT__VIPDMA_BUF_INT_MUX_MASK__SI 0x00200000L -#define VIP_INT__VIPH_INT_EN_MASK__SI 0x00000020L -#define VIP_INT__VIPH_INT_MASK__SI 0x00002000L -#define VIP_MCIF_CNTL__CAPTURE_WPRIV_MASK__SI 0x00020000L -#define VIP_MCIF_CNTL__CAPTURE_WTRAN_MASK__SI 0x00010000L -#define VIP_MCIF_CNTL__VIPH_CH0_RPRIV_MASK__SI 0x00000008L -#define VIP_MCIF_CNTL__VIPH_CH0_RTRAN_MASK__SI 0x00000002L -#define VIP_MCIF_CNTL__VIPH_CH0_WPRIV_MASK__SI 0x00000004L -#define VIP_MCIF_CNTL__VIPH_CH0_WTRAN_MASK__SI 0x00000001L -#define VIP_MCIF_CNTL__VIPH_CH1_RPRIV_MASK__SI 0x00000080L -#define VIP_MCIF_CNTL__VIPH_CH1_RTRAN_MASK__SI 0x00000020L -#define VIP_MCIF_CNTL__VIPH_CH1_WPRIV_MASK__SI 0x00000040L -#define VIP_MCIF_CNTL__VIPH_CH1_WTRAN_MASK__SI 0x00000010L -#define VIP_MCIF_CNTL__VIPH_CH2_RPRIV_MASK__SI 0x00000800L -#define VIP_MCIF_CNTL__VIPH_CH2_RTRAN_MASK__SI 0x00000200L -#define VIP_MCIF_CNTL__VIPH_CH2_WPRIV_MASK__SI 0x00000400L -#define VIP_MCIF_CNTL__VIPH_CH2_WTRAN_MASK__SI 0x00000100L -#define VIP_MCIF_CNTL__VIPH_CH3_RPRIV_MASK__SI 0x00008000L -#define VIP_MCIF_CNTL__VIPH_CH3_RTRAN_MASK__SI 0x00002000L -#define VIP_MCIF_CNTL__VIPH_CH3_WPRIV_MASK__SI 0x00004000L -#define VIP_MCIF_CNTL__VIPH_CH3_WTRAN_MASK__SI 0x00001000L -#define VLINE_START_END__VLINE_END_MASK__SI 0x3fff0000L -#define VLINE_START_END__VLINE_INV_MASK__SI 0x80000000L -#define VLINE_START_END__VLINE_START_MASK__SI 0x00003fffL -#define VLINE_STATUS__VLINE_ACK_MASK__SI 0x00000010L -#define VLINE_STATUS__VLINE_INTERRUPT_MASK__SI 0x00010000L -#define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK__SI 0x00020000L -#define VLINE_STATUS__VLINE_OCCURRED_MASK__SI 0x00000001L -#define VLINE_STATUS__VLINE_STAT_MASK__SI 0x00001000L -#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L -#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L -#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK \ - 0x00000002L -#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK \ - 0x00000004L -#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L -#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK__SI__CI 0x00400000L -#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK__SI__CI 0x00200000L -#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK__SI__CI 0x00800000L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20000000L -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10000000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL -#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL -#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK__CI__VI 0xffffffffL -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L -#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L -#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK \ - 0x00000002L -#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK \ - 0x00000004L -#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L -#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK__SI__CI 0x00400000L -#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK__SI__CI 0x00200000L -#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK__SI__CI 0x00800000L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20000000L -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10000000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL -#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL -#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK__CI__VI 0xffffffffL -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L -#define VM_DEBUG__FLAGS_MASK 0xffffffffL -#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0x0fffffffL -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0x0000000cL -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L -#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x000001ffL -#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x0003fe00L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x00000001L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x00000400L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x00000800L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x00001000L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x00002000L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x00004000L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x00008000L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x00000002L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x00000004L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x00000008L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x00000010L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x00000020L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x00000040L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x00000080L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x00000100L -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x00000200L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x00000001L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x00000400L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x00000800L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x00001000L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x00002000L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x00004000L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x00008000L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x00000002L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x00000004L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x00000008L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x00000010L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x00000020L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x00000040L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x00000080L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x00000100L -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x00000200L -#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0x0fffffffL -#define VM_L2_CG__ENABLE_MASK 0x00040000L -#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define VM_L2_CG__OFFDLY_MASK 0x00000fc0L -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0c000000L -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L -#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK__CI__VI 0x70000000L -#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003fL -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00e00000L -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0f000000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000f8000L -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000c0L -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001f00L -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK__CI__VI 0x40000000L -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK__CI__VI 0x00000800L -#define VM_L2_CNTL__ENABLE_INSECURE_READS_WHEN_SECURE_MASK__SI 0x00000800L -#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03e00000L -#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0c000000L -#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000cL -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0x0fffffffL -#define VM_L2_PERF_COUNTER_CNTL__CLEAR_ALL_L2_PERFORMANCE_COUNTERS_MASK__SI 0x00000040L -#define VM_L2_PERF_COUNTER_CNTL__CLEAR_SELECTED_L2_PERFORMANCE_COUNTER_MASK__SI 0x00000020L -#define VM_L2_PERF_COUNTER_CNTL__ENABLE_L2_PERFORMANCE_COUNTERS_MASK__SI 0x0fffff00L -#define VM_L2_PERF_COUNTER_CNTL__L2_PERFORMANCE_COUNTER_SELECT_MASK__SI 0x0000001fL -#define VM_L2_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK__SI 0x00000080L -#define VM_L2_PERF_COUNTER_STATUS__L2_PERFORMANCE_COUNTER_MASK__SI 0xffffffffL -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001fffeL -#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L -#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL -#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK__SI 0x00000001L -#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK__CI__VI 0x00000001L -#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK__CI__VI 0x00000010L -#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x00000008L -#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L -#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK__CI__VI 0x00000040L -#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK__SI 0x00000002L -#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK__CI__VI 0x00000002L -#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK__CI__VI 0x00000020L -#define VM_SECURE_FAULT_CNTL__ALLOW_CLIENTS_TO_ACCESS_MAPPED_SYSTEM_MEMORY_MASK 0x00000004L -#define VM_SECURE_FAULT_CNTL__ALLOW_RLC_TO_ACCESS_FB_MASK 0x00000002L -#define VM_SECURE_FAULT_CNTL__ENABLE_VM_SECURE_FAULT_MASK 0x00000001L -#define V_COUNTER__V_COUNTER_MASK__SI 0x00003fffL -#define WAIT_UNTIL_POLL_CNTL__POLL_ADDR_MASK__SI 0x0000ffffL -#define WAIT_UNTIL_POLL_CNTL__POLL_COMPARE_FUNCTION_MASK__SI 0x00070000L -#define WAIT_UNTIL_POLL_CNTL__POLL_INTERVAL_MASK__SI 0xfff00000L -#define WAIT_UNTIL_POLL_MASK__POLL_MASK_MASK__SI 0xffffffffL -#define WAIT_UNTIL_POLL_REFDATA__POLL_REFDATA_MASK__SI 0xffffffffL -#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK__SI 0x00f00000L -#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK__SI 0x00020000L -#define WAIT_UNTIL__WAIT_3D_IDLE_MASK__SI 0x00008000L -#define WAIT_UNTIL__WAIT_CMDFIFO_MASK__SI 0x00000400L -#define WAIT_UNTIL__WAIT_CP_DMA_IDLE_MASK__SI 0x00000100L -#define WAIT_UNTIL__WAIT_EXTERN_SIG_MASK__SI 0x00080000L -#define WAIT_UNTIL__WAIT_RING1_MASK__SI 0x80000000L -#define WAIT_UNTIL__WAIT_RING2_MASK__SI 0x40000000L -#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK__SI 0x00000001L -#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK__SI 0xffffffffL -#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK__SI 0xffffffffL -#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK__CI__VI 0x00000008L -#define WD_CNTL_STATUS__WD_BUSY_MASK__CI__VI 0x00000001L -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK__CI__VI 0x00000004L -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK__CI__VI 0x00000002L -#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK__CI__VI 0x0000003fL -#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK__CI__VI 0x00000040L -#define WD_DEBUG_DATA__DATA_MASK__CI__VI 0xffffffffL -#define WD_DEBUG_REG0__SPARE2_MASK__CI__VI 0x00001000L -#define WD_DEBUG_REG0__SPARE3_MASK__CI__VI 0x00010000L -#define WD_DEBUG_REG0__core_clk_busy_MASK__CI__VI 0x04000000L -#define WD_DEBUG_REG0__input_clk_busy_MASK__CI__VI 0x02000000L -#define WD_DEBUG_REG0__rbiu_busy_MASK__CI__VI 0x00000010L -#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK__CI__VI 0x00020000L -#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK__CI__VI 0x00000800L -#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK__CI__VI 0x00002000L -#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK__CI__VI 0x00000400L -#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK__CI__VI 0x00040000L -#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK__CI__VI 0x00004000L -#define WD_DEBUG_REG0__reg_clk_busy_MASK__CI__VI 0x01000000L -#define WD_DEBUG_REG0__sclk_core_vld_MASK__CI__VI 0x40000000L -#define WD_DEBUG_REG0__sclk_input_vld_MASK__CI__VI 0x20000000L -#define WD_DEBUG_REG0__sclk_reg_vld_MASK__CI__VI 0x10000000L -#define WD_DEBUG_REG0__se0_synced_q_MASK__CI__VI 0x00100000L -#define WD_DEBUG_REG0__se1_synced_q_MASK__CI__VI 0x00200000L -#define WD_DEBUG_REG0__se2_synced_q_MASK__CI__VI 0x00400000L -#define WD_DEBUG_REG0__se3_synced_q_MASK__CI__VI 0x00800000L -#define WD_DEBUG_REG0__spl_di_busy_MASK__CI__VI 0x00000040L -#define WD_DEBUG_REG0__spl_dma_busy_MASK__CI__VI 0x00000020L -#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK__CI__VI 0x00000200L -#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK__CI__VI 0x00080000L -#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK__CI__VI 0x00008000L -#define WD_DEBUG_REG0__vgt0_active_q_MASK__CI__VI 0x00000080L -#define WD_DEBUG_REG0__vgt1_active_q_MASK__CI__VI 0x00000100L -#define WD_DEBUG_REG0__vgt2_active_q_MASK__CI__VI 0x08000000L -#define WD_DEBUG_REG0__vgt3_active_q_MASK__CI__VI 0x80000000L -#define WD_DEBUG_REG0__wd_busy_MASK__CI__VI 0x00000004L -#define WD_DEBUG_REG0__wd_busy_extended_MASK__CI__VI 0x00000001L -#define WD_DEBUG_REG0__wd_nodma_busy_MASK__CI__VI 0x00000008L -#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK__CI__VI 0x00000002L -#define WD_DEBUG_REG1__SPARE0_MASK__CI__VI 0x00000100L -#define WD_DEBUG_REG1__dma_request_valid_q_MASK__CI__VI 0x00000080L -#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK__CI__VI 0x00000010L -#define WD_DEBUG_REG1__event_addr_valid_q_MASK__CI__VI 0x00000040L -#define WD_DEBUG_REG1__event_initiator_valid_q_MASK__CI__VI 0x00000020L -#define WD_DEBUG_REG1__free_cnt_q_MASK__CI__VI 0x03f00000L -#define WD_DEBUG_REG1__grbm_fifo_empty_MASK__CI__VI 0x00000001L -#define WD_DEBUG_REG1__grbm_fifo_full_MASK__CI__VI 0x00000002L -#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK__CI__VI 0x0001f000L -#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK__CI__VI 0x000e0000L -#define WD_DEBUG_REG1__grbm_fifo_re_MASK__CI__VI 0x00000008L -#define WD_DEBUG_REG1__grbm_fifo_we_MASK__CI__VI 0x00000004L -#define WD_DEBUG_REG1__indx_offset_valid_q_MASK__CI__VI 0x00000800L -#define WD_DEBUG_REG1__max_indx_valid_q_MASK__CI__VI 0x00000400L -#define WD_DEBUG_REG1__min_indx_valid_q_MASK__CI__VI 0x00000200L -#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK__CI__VI 0x10000000L -#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK__CI__VI 0x20000000L -#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK__CI__VI 0x04000000L -#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK__CI__VI 0x40000000L -#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK__CI__VI 0x80000000L -#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK__CI__VI 0x08000000L -#define WD_DEBUG_REG2__SPARE0_MASK__CI__VI 0x00000100L -#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK__CI__VI 0x00000080L -#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK__CI__VI 0x00000010L -#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK__CI__VI 0x00000040L -#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK__CI__VI 0x00000020L -#define WD_DEBUG_REG2__p1_free_cnt_q_MASK__CI__VI 0x03f00000L -#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK__CI__VI 0x00000001L -#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK__CI__VI 0x00000002L -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK__CI__VI 0x0001f000L -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK__CI__VI 0x000e0000L -#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK__CI__VI 0x00000008L -#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK__CI__VI 0x00000004L -#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK__CI__VI 0x00000800L -#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK__CI__VI 0x00000400L -#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK__CI__VI 0x00000200L -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK__CI__VI 0x10000000L -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK__CI__VI 0x20000000L -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK__CI__VI 0x04000000L -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK__CI__VI 0x40000000L -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK__CI__VI 0x80000000L -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK__CI__VI 0x08000000L -#define WD_DEBUG_REG3__SPARE0_MASK__CI__VI 0x00000002L -#define WD_DEBUG_REG3__SPARE1_MASK__CI__VI 0x00800000L -#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK__CI__VI 0x02000000L -#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK__CI__VI 0x00080000L -#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK__CI__VI 0x00040000L -#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK__CI__VI 0x01000000L -#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK__CI__VI 0x00020000L -#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK__CI__VI 0x00010000L -#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK__CI__VI 0x00000300L -#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK__CI__VI 0x00001000L -#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK__CI__VI 0x00000800L -#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK__CI__VI 0x08000000L -#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK__CI__VI 0x00000400L -#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK__CI__VI 0x00100000L -#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK__CI__VI 0x00008000L -#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK__CI__VI 0x00400000L -#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK__CI__VI 0x00200000L -#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK__CI__VI 0x00004000L -#define WD_DEBUG_REG3__out_of_range_p4_MASK__CI__VI 0x00002000L -#define WD_DEBUG_REG3__pipe0_dr_MASK__CI__VI 0x00000004L -#define WD_DEBUG_REG3__pipe0_rtr_MASK__CI__VI 0x00000008L -#define WD_DEBUG_REG3__pipe1_dr_MASK__CI__VI 0x00000010L -#define WD_DEBUG_REG3__pipe1_rtr_MASK__CI__VI 0x00000020L -#define WD_DEBUG_REG3__pipe3_dr_MASK__CI__VI 0x10000000L -#define WD_DEBUG_REG3__pipe3_rtr_MASK__CI__VI 0x20000000L -#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK__CI__VI 0x00000001L -#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK__CI__VI 0x04000000L -#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK__CI__VI 0x40000000L -#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK__CI__VI 0x80000000L -#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK__CI__VI 0x00000040L -#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK__CI__VI 0x00000080L -#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK__CI__VI 0x20000000L -#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK__CI__VI 0x10000000L -#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK__CI__VI 0x00002000L -#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK__CI__VI 0x00001000L -#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK__CI__VI 0x00070000L -#define WD_DEBUG_REG4__di_type_p0_MASK__CI__VI 0x0000c000L -#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK__CI__VI 0x00080000L -#define WD_DEBUG_REG4__dual_ia_mode_MASK__CI__VI 0x80000000L -#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK__CI__VI 0x04000000L -#define WD_DEBUG_REG4__ext_event_wait_q_MASK__CI__VI 0x08000000L -#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK__CI__VI 0x00200000L -#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK__CI__VI 0x00800000L -#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK__CI__VI 0x00400000L -#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK__CI__VI 0x01000000L -#define WD_DEBUG_REG4__not_eop_wait_q_MASK__CI__VI 0x02000000L -#define WD_DEBUG_REG4__pipe0_dr_MASK__CI__VI 0x00000010L -#define WD_DEBUG_REG4__pipe0_rtr_MASK__CI__VI 0x00000020L -#define WD_DEBUG_REG4__pipe1_dr_MASK__CI__VI 0x00000040L -#define WD_DEBUG_REG4__pipe1_rtr_MASK__CI__VI 0x00000080L -#define WD_DEBUG_REG4__pipe2_dr_MASK__CI__VI 0x00000100L -#define WD_DEBUG_REG4__pipe2_rtr_MASK__CI__VI 0x00000200L -#define WD_DEBUG_REG4__pipe3_ld_MASK__CI__VI 0x00000400L -#define WD_DEBUG_REG4__pipe3_rtr_MASK__CI__VI 0x00000800L -#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK__CI__VI 0x00000001L -#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK__CI__VI 0x00000004L -#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK__CI__VI 0x00100000L -#define WD_DEBUG_REG4__send_to_ia1_q_MASK__CI__VI 0x40000000L -#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK__CI__VI 0x00000002L -#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK__CI__VI 0x00000008L -#define WD_DEBUG_REG5__SPARE0_MASK__CI__VI 0x00000002L -#define WD_DEBUG_REG5__SPARE1_MASK__CI__VI 0x00800000L -#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK__CI__VI 0x02000000L -#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK__CI__VI 0x00080000L -#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK__CI__VI 0x00040000L -#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK__CI__VI 0x01000000L -#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK__CI__VI 0x00020000L -#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK__CI__VI 0x00010000L -#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK__CI__VI 0x00000300L -#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK__CI__VI 0x00001000L -#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK__CI__VI 0x00000800L -#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK__CI__VI 0x08000000L -#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK__CI__VI 0x00000400L -#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK__CI__VI 0x00100000L -#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK__CI__VI 0x00008000L -#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK__CI__VI 0x00400000L -#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK__CI__VI 0x00200000L -#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK__CI__VI 0x00004000L -#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK__CI__VI 0x00002000L -#define WD_DEBUG_REG5__p1_pipe0_dr_MASK__CI__VI 0x00000004L -#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK__CI__VI 0x00000008L -#define WD_DEBUG_REG5__p1_pipe1_dr_MASK__CI__VI 0x00000010L -#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK__CI__VI 0x00000020L -#define WD_DEBUG_REG5__p1_pipe3_dr_MASK__CI__VI 0x10000000L -#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK__CI__VI 0x20000000L -#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK__CI__VI 0x00000001L -#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK__CI__VI 0x04000000L -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK__CI__VI 0x40000000L -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK__CI__VI 0x80000000L -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK__CI__VI 0x00000040L -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK__CI__VI 0x00000080L -#define WD_ENHANCE__MISC_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK__CI__VI 0x000000ffL -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK__CI__VI 0x000000ffL -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK__CI__VI 0x000000ffL -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK__CI__VI 0xffffffffL -#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK__CI__VI 0xf0000000L -#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK__CI__VI 0x000000ffL - -// Merged Defines - -#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK__VI 0x00040000L -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK__VI 0x0fffffffL -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK__VI 0x0ff00000L -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK__VI 0x0003fc00L -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK__VI 0x000000ffL -#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK__VI 0x0000003eL -#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK__VI 0x00000001L -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK__VI 0x000000ffL -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK__VI 0x00000001L -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK__VI 0x00000400L -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK__VI 0x00000800L -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK__VI 0x00001000L -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK__VI 0x00002000L -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK__VI 0x00004000L -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK__VI 0x00008000L -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK__VI 0x00000002L -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK__VI 0x00000004L -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK__VI 0x00000008L -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK__VI 0x00000010L -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK__VI 0x00000020L -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK__VI 0x00000040L -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK__VI 0x00000080L -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK__VI 0x00000100L -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK__VI 0x00000200L -#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK__VI 0x000f8000L -#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK__VI 0x00004000L -#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK__VI 0x00002000L -#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK__VI 0x00001000L -#define ATC_L1RD_DEBUG2_TLB__L2_XNACK_RETRY_PERIOD_MASK__VI 0x000003ffL -#define ATC_L1RD_STATUS__CAM_INDEX_MASK__VI 0x003e0000L -#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK__VI 0x0001f000L -#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK__VI 0x000f8000L -#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK__VI 0x00004000L -#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK__VI 0x00002000L -#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK__VI 0x00001000L -#define ATC_L1WR_DEBUG2_TLB__L2_XNACK_RETRY_PERIOD_MASK__VI 0x000003ffL -#define ATC_L1WR_STATUS__CAM_INDEX_MASK__VI 0x003e0000L -#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK__VI 0x0001f000L -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK__VI 0x000ffffcL -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK__VI 0x00000002L -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK__VI 0x00000001L -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK__VI 0x00f00000L -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK__VI 0xffffffffL -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK__VI 0x0fffffffL -#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK__VI 0x00002000L -#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK__VI 0x00000080L -#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK__VI 0x0000007fL -#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK__VI 0x00001f00L -#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK__VI 0x0001c000L -#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK__VI 0x7f800000L -#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK__VI 0x80000000L -#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK__VI 0x00000400L -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK__VI 0x00000800L -#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK__VI 0x00780000L -#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK__VI 0x02000000L -#define ATC_L2_DEBUG__CACHE_INDEX_MASK__VI 0x000fff00L -#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK__VI 0x80000000L -#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK__VI 0x40000000L -#define ATC_L2_DEBUG__CACHE_READ_MASK__VI 0x20000000L -#define ATC_L2_DEBUG__CACHE_SELECT_MASK__VI 0x01000000L -#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK__VI 0x08000000L -#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK__VI 0x00000080L -#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK__VI 0x00000007L -#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK__VI 0x000007f8L -#define ATC_L2_STATUS__BUSY_MASK__VI 0x00000001L -#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK__VI 0x3ffffffeL -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK__VI 0x40000000L -#define BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK__VI 0x00000010L -#define BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK__VI 0x00040000L -#define BACO_CNTL__PWRGOOD_IDSC_MASK__VI 0x00002000L -#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK__VI 0x00000001L -#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK__VI 0x00000002L -#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK__VI 0x00010000L -#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK__VI 0x00020000L -#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK__VI 0x00000001L -#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK__VI 0x00000002L -#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK__VI 0x00010000L -#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK__VI 0x00000001L -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM_MASK__VI 0x00020000L -#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK__VI 0x00000002L -#define BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK__VI 0x00000001L -#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK__VI 0x00000001L -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK__VI 0x01000000L -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK__VI 0x02000000L -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK__VI 0x04000000L -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK__VI 0x08000000L -#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK__VI 0x00010000L -#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK__VI 0x00000020L -#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK__VI 0x00000010L -#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK__VI 0x80000000L -#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK__VI 0x00000ffcL -#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK__VI 0x00000ffcL -#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK__VI 0x80000000L -#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK__VI 0x00000ffcL -#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK__VI 0x00000ffcL -#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK__VI 0x00000800L -#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK__VI 0x00002000L -#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK__VI 0x00004000L -#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK__VI 0x00000400L -#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK__VI 0x00001000L -#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK__VI 0x00008000L -#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK__VI 0x00000200L -#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK__VI 0x0001ffffL -#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK__VI 0xffffffffL -#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK__VI 0x00000002L -#define BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK__VI 0x00000001L -#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK__VI 0x00000008L -#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd_MASK__VI 0x00000004L -#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK__VI 0x00000008L -#define BIF_PWDN_STATUS__SMBUS_REG_pw_status_MASK__VI 0x00000004L -#define BIF_RB_BASE__ADDR_MASK__VI 0xffffffffL -#define BIF_RB_CNTL__BIF_RB_TRAN_MASK__VI 0x00020000L -#define BIF_RB_CNTL__RB_ENABLE_MASK__VI 0x00000001L -#define BIF_RB_CNTL__RB_SIZE_MASK__VI 0x0000003eL -#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK__VI 0x80000000L -#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK__VI 0x00000100L -#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK__VI 0x00003e00L -#define BIF_RB_RPTR__OFFSET_MASK__VI 0x0003fffcL -#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK__VI 0x000000ffL -#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK__VI 0xfffffffcL -#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK__VI 0x00000001L -#define BIF_RB_WPTR__OFFSET_MASK__VI 0x0003fffcL -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK__VI 0x00000008L -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst_MASK__VI 0x00000004L -#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer_MASK__VI 0x000000ffL -#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer_MASK__VI 0x00000f00L -#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer_MASK__VI 0x00ff0000L -#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout_MASK__VI 0x01000000L -#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK__VI 0x00000002L -#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK__VI 0x00000001L -#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK__VI 0x00000001L -#define BIF_SMU_DATA__BIF_SMU_DATA_MASK__VI 0x0007fffcL -#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK__VI 0x0007fffcL -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK__VI 0x00000001L -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK__VI 0x00000002L -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK__VI 0x00000010L -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK__VI 0x00000020L -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK__VI 0x00000004L -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK__VI 0x00000008L -#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK__VI 0x40000000L -#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK__VI 0x0003fffcL -#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK__VI 0x80000000L -#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK__VI 0x0003fffcL -#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK__VI 0x80000000L -#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK__VI 0x0000ffffL -#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK__VI 0x00000001L -#define BX_RESET_EN__FLR_TIMER_SEL_MASK__VI 0x00000600L -#define BX_RESET_EN__FLR_TWICE_EN_MASK__VI 0x00000100L -#define CB_COLOR0_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR0_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR1_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR1_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR2_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR2_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR3_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR3_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR4_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR4_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR5_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR5_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR6_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR6_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR7_DCC_BASE__BASE_256B_MASK__VI 0xffffffffL -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK__VI 0x00000180L -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK__VI 0x00000200L -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK__VI 0x00000002L -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK__VI 0x0003c000L -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK__VI 0x00003c00L -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000060L -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK__VI 0x0000000cL -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK__VI 0x00000010L -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK__VI 0x60000000L -#define CB_COLOR7_INFO__DCC_ENABLE_MASK__VI 0x10000000L -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK__VI 0x08000000L -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK__VI 0x00000001L -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK__VI 0x0f000000L -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK__VI 0xf0000000L -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK__VI 0x0000ff00L -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK__VI 0x00000040L -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK__VI 0x0000001fL -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000020L -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK__VI 0x007f0000L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK__VI 0x00000001L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK__VI 0x00000002L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK__VI 0x0000007cL -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_10__CORE_SCLK_VLD_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_10__REG_SCLK0_VLD_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_10__REG_SCLK1_VLD_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT_MASK__VI 0x003ff800L -#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT_MASK__VI 0x000007ffL -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1_MASK__VI 0x00000007L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1_MASK__VI 0x00000018L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2_MASK__VI 0x00000060L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3_MASK__VI 0x00000180L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1_MASK__VI 0x00000600L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2_MASK__VI 0x00001800L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3_MASK__VI 0x00006000L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4_MASK__VI 0x00018000L -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5_MASK__VI 0x00060000L -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_17__AC_BUSY_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_17__CRW_BUSY_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_17__MU_BUSY_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_17__MU_STATE_MASK__VI 0x0007f800L -#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_17__TQ_BUSY_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_18__DAG_BUSY_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_18__DCC_BUSY_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_18__DOC_BUSY_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_18__DOC_STALL_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_18__FOP_BUSY_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_18__LAT_BUSY_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_18__TILE_BUSY_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_19__CS_BUSY_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_19__DC_BUSY_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_19__DC_READY_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_19__DD_BUSY_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_19__DD_READY_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_19__DF_BUSY_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_19__DK_BUSY_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_19__DRR_BUSY_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_19__DS_BUSY_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_19__IB_BUSY_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_19__RB_BUSY_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_19__SF_BUSY_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK__VI 0x00000003L -#define CB_DEBUG_BUS_19__TB_BUSY_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_1__CB_BUSY_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK__VI 0x0000003fL -#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK__VI 0x00000fc0L -#define CB_DEBUG_BUS_21__BB_BUSY_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_21__CC_BUSY_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_21__CM_BUSY_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_21__FC_BUSY_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_21__MA_BUSY_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK__VI 0x00000fffL -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK__VI 0x00fff000L -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_3__CC_RB_FULL_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_3__CC_SF_FULL_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_3__CM_CACHE_HIT_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_3__CM_TQ_FULL_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_3__LQUAD_NO_TILE_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_4__CC_CACHE_HIT_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_4__CM_CACHE_STALL_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL_MASK__VI 0x00008000L -#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_4__FC_CACHE_HIT_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK__VI 0x00000800L -#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_4__FC_CACHE_STALL_MASK__VI 0x00010000L -#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL_MASK__VI 0x00000004L -#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH_MASK__VI 0x00020000L -#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL_MASK__VI 0x00000001L -#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED_MASK__VI 0x00380000L -#define CB_DEBUG_BUS_5__CC_CACHE_STALL_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED_MASK__VI 0x00040000L -#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL_MASK__VI 0x00000002L -#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED_MASK__VI 0x0001c000L -#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH_MASK__VI 0x00000200L -#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED_MASK__VI 0x00003800L -#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED_MASK__VI 0x00000007L -#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST_MASK__VI 0x00000020L -#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST_MASK__VI 0x00000100L -#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT_MASK__VI 0x0001fe00L -#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST_MASK__VI 0x00000008L -#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST_MASK__VI 0x00000040L -#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST_MASK__VI 0x00000010L -#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST_MASK__VI 0x00000080L -#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT_MASK__VI 0x001ff800L -#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT_MASK__VI 0x000007ffL -#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT_MASK__VI 0x000000ffL -#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK__VI 0x0007ff00L -#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK__VI 0x000003ffL -#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC_MASK__VI 0x00000400L -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL_MASK__VI 0x00078000L -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT_MASK__VI 0x00080000L -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_MASK__VI 0x00004000L -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE_MASK__VI 0x00100000L -#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT_MASK__VI 0x00002000L -#define CB_DEBUG_BUS_9__EVENT_ALL_MASK__VI 0x00200000L -#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS_MASK__VI 0x00400000L -#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE_MASK__VI 0x00800000L -#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT_MASK__VI 0x00001000L -#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK__VI 0x00000800L -#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK__VI 0xf0000000L -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK__VI 0x0f000000L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK__VI 0x00000020L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK__VI 0x00000080L -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK__VI 0x00000800L -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK__VI 0x00000004L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK__VI 0x00000010L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK__VI 0x00000100L -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK__VI 0x00000008L -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK__VI 0x00001000L -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK__VI 0x00000400L -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK__VI 0x00000002L -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK__VI 0x00000200L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_GEN3_EN_PIN_A_MASK__VI 0x00000002L -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN_MASK__VI 0x00000010L -#define CC_BIF_BU_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING_MASK__VI 0x00000020L -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN_MASK__VI 0x00000010L -#define CC_BIF_BX_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING_MASK__VI 0x00000020L -#define CC_BIF_BX_PINSTRAP1__STRAP_BIF_AUDIO_EN_PIN_MASK__VI 0x00000002L -#define CC_BIF_BX_PINSTRAP1__STRAP_BIF_CEC_EN_PIN_MASK__VI 0x00000004L -#define CC_BIF_BX_PINSTRAP2__STRAP_BIF_BIOS_ROM_EN_MASK__VI 0x00000010L -#define CC_BIF_BX_PINSTRAP2__STRAP_BIF_MEM_AP_SIZE_PIN_MASK__VI 0x0000000eL -#define CC_BIF_BX_STRAP0__STRAP_BIF_AUDIO_EN_MASK__VI 0x02000000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_AZ_64BAR_DIS_A_MASK__VI 0x10000000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_F0_64BAR_DIS_A_MASK__VI 0x04000000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_IO_BAR_DIS_MASK__VI 0x00020000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_LFB_ERRMSG_EN_MASK__VI 0x40000000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK__VI 0x00010000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_VF_DOORBELL_APER_SIZE_MASK__VI 0x01800000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_VF_MEM_AP_SIZE_MASK__VI 0x001c0000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_VF_REG_AP_SIZE_MASK__VI 0x00600000L -#define CC_BIF_BX_STRAP0__STRAP_BIF_XSTCLK_SWITCH_OVERRIDE_MASK__VI 0x20000000L -#define CC_BIF_BX_STRAP0__STRAP_CEC_64BAR_DIS_MASK__VI 0x08000000L -#define CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK__VI 0x80000000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_BAR_EN_MASK__VI 0x00000100L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_EN_MASK__VI 0x00000004L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_MSI_PERVECTOR_MASK_CAP_MASK__VI 0x00200000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F1_LEGACY_DEVICE_TYPE_EN_MASK__VI 0x00000008L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F1_MSI_PERVECTOR_MASK_CAP_MASK__VI 0x00400000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_EN_MASK__VI 0x00000010L -#define CC_BIF_BX_STRAP1__STRAP_BIF_F2_MSI_PERVECTOR_MASK_CAP_MASK__VI 0x00800000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_MAX_PASID_WIDTH_MASK__VI 0x0003e000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_EP_ERR_MASK__VI 0x00000080L -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK__VI 0x00000040L -#define CC_BIF_BX_STRAP1__STRAP_BIF_SRIOV_EN_MASK__VI 0x01000000L -#define CC_BIF_BX_STRAP1__STRAP_BIF_VGA_DIS_MASK__VI 0x00000002L -#define CC_BIF_BX_STRAP1__STRAP_CEC_PME_SUPPORT_EN_MASK__VI 0x00100000L -#define CC_BIF_BX_STRAP1__STRAP_GPU_PME_SUPPORT_EN_MASK__VI 0x00080000L -#define CC_BIF_BX_STRAP1__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK__VI 0x00000020L -#define CC_BIF_BX_STRAP1__STRAP_RESERVED_MASK__VI 0xfe000000L -#define CC_BIF_BX_STRAP2__STRAP_BIF_IOV_LKRST_DIS_MASK__VI 0x00000002L -#define CC_BIF_BX_STRAP2__STRAP_BIF_MSI_CLR_PENDING_EN_MASK__VI 0x00000004L -#define CC_BIF_BX_STRAP2__STRAP_RESERVED_MASK__VI 0xfffffff8L -#define CC_BIF_HARDCODE_STRAPS0__STRAP_BIF_F2_BASE_CLASS_MASK__VI 0x1fe00000L -#define CC_BIF_HARDCODE_STRAPS1__STRAP_BIF_F1_BASE_CLASS_MASK__VI 0x00001fe0L -#define CC_BIF_HARDCODE_STRAPS1__STRAP_BIF_MST_ADR64_EN_MASK__VI 0x80000000L -#define CC_BIF_HARDCODE_STRAPS3__STRAP_BIF_F0_BASE_CLASS_MASK__VI 0x000000ffL -#define CC_BIF_SMB_PINSTRAP0__STRAP_BIF_SMBUS_DIS_MASK__VI 0x00000002L -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_ARP_DIS_MASK__VI 0x00000002L -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_BACKUP_EN_MASK__VI 0x00000040L -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_FILTER_DIS_MASK__VI 0x00000080L -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_HOLD_SMBCLK_LOW_DIS_MASK__VI 0x00000008L -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_NOTIFY_ARP_MST_DIS_MASK__VI 0x00000010L -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_THM_OVERRIDE_DIS_MASK__VI 0x00000004L -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_UDID_RAN_NUM_DIS_MASK__VI 0x00000100L -#define CC_BIF_SMB_STRAP1__STRAP_BIF_F0_DEVICE_ID_MASK__VI 0x000ffff0L -#define CC_BIF_SMB_STRAP1__STRAP_BIF_F0_MINOR_REV_ID_MASK__VI 0x07000000L -#define CC_BIF_SMB_STRAP2__STRAP_BIF_F0_SUBSYS_ID_MASK__VI 0x0001fffeL -#define CC_BIF_SMB_STRAP3__STRAP_BIF_F0_SUBSYS_VEN_ID_MASK__VI 0x003fffc0L -#define CC_BIF_SMB_STRAP4__STRAP_BIF_VENDOR_ID_MASK__VI 0x00000008L -#define CC_BIF_STRAP0__STRAP_BIF_2VC_EN_MASK__VI 0x00000004L -#define CC_BIF_STRAP0__STRAP_BIF_ECN1P1_EN_MASK__VI 0x00010000L -#define CC_BIF_STRAP0__STRAP_BIF_F0_CPL_ABORT_ERR_EN_MASK__VI 0x00000010L -#define CC_BIF_STRAP0__STRAP_BIF_GEN2_COMPLIANCE_MASK__VI 0x00020000L -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_SpareRegs_MASK__VI 0x03e00000L -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_TxFifoBypass_MASK__VI 0x00040000L -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_TxFifoDelay2_MASK__VI 0x00100000L -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_TxFifoDelay_MASK__VI 0x00080000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_CHECK_DATA_RATE_MASK__VI 0x00008000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_SELECT_DEEMPHASIS_MASK__VI 0x00001000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_DIS_MASK__VI 0x00004000L -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_SUPPORT_MASK__VI 0x00002000L -#define CC_BIF_STRAP0__STRAP_BIF_MSTCPL_TIMEOUT_EN_MASK__VI 0x00000008L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_BE_ERR_MASK__VI 0x00000040L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK__VI 0x00000080L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK__VI 0x00000100L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_IO_ERR_MASK__VI 0x00000020L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK__VI 0x00000200L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK__VI 0x00000400L -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_TC_ERR_MASK__VI 0x00000800L -#define CC_BIF_STRAP0__STRAP_RESERVED_0_MASK__VI 0xfc000000L -#define CC_BIF_STRAP10_A__STRAP_BIF_BCH_ECC_EN_A_MASK__VI 0x00000002L -#define CC_BIF_STRAP10_A__STRAP_BIF_BYPASS_RCVR_DET_A_MASK__VI 0x00000200L -#define CC_BIF_STRAP10_A__STRAP_BIF_COMPLIANCE_DIS_A_MASK__VI 0x00000100L -#define CC_BIF_STRAP10_A__STRAP_BIF_FORCE_COMPLIANCE_A_MASK__VI 0x00000020L -#define CC_BIF_STRAP10_A__STRAP_BIF_GEN2_EN_A_MASK__VI 0x00000800L -#define CC_BIF_STRAP10_A__STRAP_BIF_LANE_NEGOTIATION_A_MASK__VI 0x0001c000L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_A_MASK__VI 0x00000400L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_A_MASK__VI \ - 0x0c000000L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_BYPASS_EQ_A_MASK__VI 0x00000010L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_A_MASK__VI 0x00000008L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_ELEC_IDLE_MODE_A_MASK__VI 0x00060000L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_EQ_SEARCH_MODE_A_MASK__VI 0x00600000L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L0s_EN_A_MASK__VI 0x00000080L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L1_EN_A_MASK__VI 0x00000040L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_SPC_MODE_2P5GT_A_MASK__VI 0x10000000L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_SPC_MODE_5GT_A_MASK__VI 0x20000000L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_SPC_MODE_8GT_A_MASK__VI 0x40000000L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A_MASK__VI 0x00000004L -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_TEST_TIMER_SEL_A_MASK__VI 0x00003000L -#define CC_BIF_STRAP10_A__STRAP_BIF_SKIP_INTERVAL_A_MASK__VI 0x03800000L -#define CC_BIF_STRAP10_A__STRAP_BIF_TARGET_LINK_SPEED_A_MASK__VI 0x00180000L -#define CC_BIF_STRAP11_A__STRAP_BIF_FTS_yTSx_COUNT_A_MASK__VI 0x00018000L -#define CC_BIF_STRAP11_A__STRAP_BIF_L1_ACCEPTABLE_LATENCY_A_MASK__VI 0x0000000eL -#define CC_BIF_STRAP11_A__STRAP_BIF_L1_EXIT_LATENCY_A_MASK__VI 0x00000070L -#define CC_BIF_STRAP11_A__STRAP_BIF_LC_L0S_INACTIVITY_A_MASK__VI 0x01e00000L -#define CC_BIF_STRAP11_A__STRAP_BIF_LC_L1_INACTIVITY_A_MASK__VI 0x001e0000L -#define CC_BIF_STRAP11_A__STRAP_BIF_LONG_yTSx_COUNT_A_MASK__VI 0x00000600L -#define CC_BIF_STRAP11_A__STRAP_BIF_MED_yTSx_COUNT_A_MASK__VI 0x00001800L -#define CC_BIF_STRAP11_A__STRAP_BIF_PM_SUPPORT_A_MASK__VI 0x00000180L -#define CC_BIF_STRAP11_A__STRAP_BIF_SHORT_yTSx_COUNT_A_MASK__VI 0x00006000L -#define CC_BIF_STRAP11_A__STRAP_RESERVED_11_A_MASK__VI 0xfe000000L -#define CC_BIF_STRAP1__STRAP_BIF_ECRC_CHECK_EN_MASK__VI 0x01000000L -#define CC_BIF_STRAP1__STRAP_BIF_F0_ATS_EN_MASK__VI 0x20000000L -#define CC_BIF_STRAP1__STRAP_BIF_F2_POISONED_ADVISORY_NONFATAL_MASK__VI 0x80000000L -#define CC_BIF_STRAP1__STRAP_BIF_MSI_EN_MASK__VI 0x40000000L -#define CC_BIF_STRAP1__STRAP_BIF_SYMALIGN_MODE_MASK__VI 0x00800000L -#define CC_BIF_STRAP2__STRAP_BIF_AER_EN_MASK__VI 0x00000002L -#define CC_BIF_STRAP2__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK__VI 0x00000100L -#define CC_BIF_STRAP2__STRAP_BIF_BYPASS_SCRAMBLER_MASK__VI 0x00000020L -#define CC_BIF_STRAP2__STRAP_BIF_ERR_REPORTING_DIS_MASK__VI 0x00000200L -#define CC_BIF_STRAP2__STRAP_BIF_EXTENDED_TAG_ECN_EN_MASK__VI 0x00000400L -#define CC_BIF_STRAP2__STRAP_BIF_F0_MSI_MULTI_CAP_MASK__VI 0x03800000L -#define CC_BIF_STRAP2__STRAP_BIF_F0_POISONED_ADVISORY_NONFATAL_MASK__VI 0x00000800L -#define CC_BIF_STRAP2__STRAP_BIF_F0_VC_EN_MASK__VI 0x00000004L -#define CC_BIF_STRAP2__STRAP_BIF_F1_MSI_MULTI_CAP_MASK__VI 0x1c000000L -#define CC_BIF_STRAP2__STRAP_BIF_F1_POISONED_ADVISORY_NONFATAL_MASK__VI 0x00001000L -#define CC_BIF_STRAP2__STRAP_BIF_F2_MSI_MULTI_CAP_MASK__VI 0xe0000000L -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_CDR_MODE_MASK__VI 0x00000080L -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_GEN2_MODE_MASK__VI 0x00000040L -#define CC_BIF_STRAP2__STRAP_BIF_LC_CDR_SET_TYPE_MASK__VI 0x00018000L -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F0_ATOMIC_64BIT_EN_MASK__VI 0x00100000L -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK__VI 0x00020000L -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F1_ATOMIC_64BIT_EN_MASK__VI 0x00200000L -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F1_ATOMIC_EN_MASK__VI 0x00040000L -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F2_ATOMIC_64BIT_EN_MASK__VI 0x00400000L -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F2_ATOMIC_EN_MASK__VI 0x00080000L -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_MODE_MASK__VI 0x00000008L -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_PATTERN_MASK__VI 0x00000010L -#define CC_BIF_STRAP2__STRAP_BIF_TX_TEST_ALL_MASK__VI 0x00006000L -#define CC_BIF_STRAP3__STRAP_BIF_FLR_EN_MASK__VI 0x00000010L -#define CC_BIF_STRAP3__STRAP_BIF_FORCE_GEN3_MODE_MASK__VI 0x00000004L -#define CC_BIF_STRAP3__STRAP_BIF_GEN3_COMPLIANCE_MASK__VI 0x00000020L -#define CC_BIF_STRAP3__STRAP_BIF_INTERNAL_ERR_EN_MASK__VI 0x00000008L -#define CC_BIF_STRAP3__STRAP_BIF_LC_CDR_TEST_OFF_ENCODE_MASK__VI 0x00c00000L -#define CC_BIF_STRAP3__STRAP_BIF_NO_SOFT_RESET_MASK__VI 0x00000002L -#define CC_BIF_STRAP3__STRAP_BIF_SRIOV_EN_MASK__VI 0x04000000L -#define CC_BIF_STRAP3__STRAP_BIF_SUBSYS_VEN_ID_MASK__VI 0x003fffc0L -#define CC_BIF_STRAP3__STRAP_BIF_TOTAL_VFS_MASK__VI 0xf8000000L -#define CC_BIF_STRAP3__STRAP_PLL_CMP_FREQ_MODE_MASK__VI 0x03000000L -#define CC_BIF_STRAP4__STRAP_BIF_F0_MAX_PAYLOAD_SUPPORT_MASK__VI 0x00000070L -#define CC_BIF_STRAP4__STRAP_BIF_LTR_SUPPORTED_MASK__VI 0x00000002L -#define CC_BIF_STRAP4__STRAP_BIF_OBFF_SUPPORTED_MASK__VI 0x0000000cL -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_8T0_0_MASK__VI 0x00007f80L -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_8T0_1_MASK__VI 0x007f8000L -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_8T0_2_MASK__VI 0x7f800000L -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_8T0_3_MASK__VI 0x000001feL -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_8T0_4_MASK__VI 0x0001fe00L -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_8T0_5_MASK__VI 0x01fe0000L -#define CC_BIF_STRAP6__STRAP_BIF_F0_DPA_EN_MASK__VI 0x00000002L -#define CC_BIF_STRAP6__STRAP_BIF_F2_CPL_ABORT_ERR_EN_MASK__VI 0x00000004L -#define CC_BIF_STRAP6__STRAP_BIF_VENDOR_ID_MASK__VI 0x00000008L -#define CC_BIF_STRAP6__STRAP_RESERVED_6_MASK__VI 0xfffffff0L -#define CC_BIF_STRAP7__STRAP_BIF_F0_BAR_EN_MASK__VI 0x00000100L -#define CC_BIF_STRAP7__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_EN_MASK__VI 0x00000004L -#define CC_BIF_STRAP7__STRAP_BIF_F1_LEGACY_DEVICE_TYPE_EN_MASK__VI 0x00000008L -#define CC_BIF_STRAP7__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_EN_MASK__VI 0x00000010L -#define CC_BIF_STRAP7__STRAP_BIF_MAX_PASID_WIDTH_MASK__VI 0x0003e000L -#define CC_BIF_STRAP7__STRAP_BIF_RX_IGNORE_EP_ERR_MASK__VI 0x00000080L -#define CC_BIF_STRAP7__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK__VI 0x00000040L -#define CC_BIF_STRAP7__STRAP_BIF_VGA_DIS_MASK__VI 0x00000002L -#define CC_BIF_STRAP7__STRAP_CEC_PME_SUPPORT_EN_MASK__VI 0x00100000L -#define CC_BIF_STRAP7__STRAP_GPU_PME_SUPPORT_EN_MASK__VI 0x00080000L -#define CC_BIF_STRAP7__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK__VI 0x00000020L -#define CC_BIF_STRAP7__STRAP_RESERVED_MASK__VI 0xffe00000L -#define CC_BIF_STRAP8__STRAP_BIF_ARI_EN_MASK__VI 0x00000004L -#define CC_BIF_STRAP8__STRAP_BIF_CFG_REG_RESET_ONLY_MASK__VI 0x00040000L -#define CC_BIF_STRAP8__STRAP_BIF_F0_ACS_EN_MASK__VI 0x00004000L -#define CC_BIF_STRAP8__STRAP_BIF_F0_DSN_EN_MASK__VI 0x00000800L -#define CC_BIF_STRAP8__STRAP_BIF_F1_ACS_EN_MASK__VI 0x00008000L -#define CC_BIF_STRAP8__STRAP_BIF_F1_BAR_EN_MASK__VI 0x00000200L -#define CC_BIF_STRAP8__STRAP_BIF_F1_DPA_EN_MASK__VI 0x00000020L -#define CC_BIF_STRAP8__STRAP_BIF_F1_DSN_EN_MASK__VI 0x00001000L -#define CC_BIF_STRAP8__STRAP_BIF_F1_PWR_EN_MASK__VI 0x00000080L -#define CC_BIF_STRAP8__STRAP_BIF_F1_VC_EN_MASK__VI 0x00000008L -#define CC_BIF_STRAP8__STRAP_BIF_F2_ACS_EN_MASK__VI 0x00010000L -#define CC_BIF_STRAP8__STRAP_BIF_F2_BAR_EN_MASK__VI 0x00000400L -#define CC_BIF_STRAP8__STRAP_BIF_F2_DPA_EN_MASK__VI 0x00000040L -#define CC_BIF_STRAP8__STRAP_BIF_F2_DSN_EN_MASK__VI 0x00002000L -#define CC_BIF_STRAP8__STRAP_BIF_F2_PWR_EN_MASK__VI 0x00000100L -#define CC_BIF_STRAP8__STRAP_BIF_F2_VC_EN_MASK__VI 0x00000010L -#define CC_BIF_STRAP8__STRAP_BIF_LINK_DOWN_RESET_EN_MASK__VI 0x00080000L -#define CC_BIF_STRAP8__STRAP_BIF_MC_EN_MASK__VI 0x00000002L -#define CC_BIF_STRAP8__STRAP_PHY_CALIB_RST_MASK__VI 0x00020000L -#define CC_BIF_STRAP8__STRAP_RESERVED_8_MASK__VI 0xfff00000L -#define CC_BIF_STRAP9_A__STRAP_BIF_E2E_PREFIX_EN_A_MASK__VI 0x00000002L -#define CC_BIF_STRAP9_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_A_MASK__VI 0x00000004L -#define CC_BIF_STRAP9_A__STRAP_BIF_INITIAL_N_FTS_A_MASK__VI 0x00ff0000L -#define CC_BIF_STRAP9_A__STRAP_BIF_L0S_ACCEPTABLE_LATENCY_A_MASK__VI 0x07000000L -#define CC_BIF_STRAP9_A__STRAP_BIF_L0S_EXIT_LATENCY_A_MASK__VI 0x38000000L -#define CC_BIF_STRAP9_A__STRAP_BIF_LC_EQ_FS_A_MASK__VI 0x0000fc00L -#define CC_BIF_STRAP9_A__STRAP_BIF_LC_EQ_LF_A_MASK__VI 0x000003f0L -#define CC_BIF_STRAP9_A__STRAP_BIF_LC_X12_NEGOTIATION_DIS_A_MASK__VI 0x00000008L -#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK__VI 0x00000002L -#define CC_FCTRL_FUSES__WRITE_DIS_MASK__VI 0x00000001L -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK__VI 0x00000006L -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK__VI 0x00000010L -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK__VI 0x00000008L -#define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS_MASK__VI 0x00000001L -#define CC_HARVEST_FUSES__ACP_EXISTS_MASK__VI 0x00000040L -#define CC_HARVEST_FUSES__DC_DISABLE_MASK__VI 0x00003f00L -#define CC_HARVEST_FUSES__UVD_DISABLE_MASK__VI 0x00000010L -#define CC_HARVEST_FUSES__VCE_DISABLE_MASK__VI 0x00000006L -#define CC_HARVEST_FUSES__WRITE_DIS_MASK__VI 0x00000001L -#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK__VI 0x00080000L -#define CC_RCU_FUSES__DSMU_DISABLE_MASK__VI 0x00800000L -#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK__VI 0x00008000L -#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK__VI 0x00010000L -#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK__VI 0x00200000L -#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK__VI 0x00400000L -#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK__VI 0x02000000L -#define CC_RCU_FUSES__RCU_SPARE_MASK__VI 0xfc000000L -#define CC_RCU_FUSES__RED_WRITE_DIS_MASK__VI 0x00100000L -#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK__VI 0x00040000L -#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK__VI 0x00004000L -#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK__VI 0x01000000L -#define CC_RCU_FUSES__XFIRE_DISABLE_MASK__VI 0x00020000L -#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK__VI 0x00001000L -#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK__VI 0x00100000L -#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK__VI 0x00000f00L -#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK__VI 0x000f0000L -#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK__VI 0xf0000000L -#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK__VI 0x00ffffffL -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK__VI 0x20000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK__VI 0x20000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK__VI 0x20000000L -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK__VI 0x20000000L -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK__VI 0x10000000L -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK__VI 0x20000000L -#define CGTT_SX_CLK_CTRL1__DBG_EN_MASK__VI 0x01000000L -#define CGTT_SX_CLK_CTRL2__DBG_EN_MASK__VI 0x01000000L -#define CGTT_SX_CLK_CTRL3__DBG_EN_MASK__VI 0x01000000L -#define CGTT_SX_CLK_CTRL4__DBG_EN_MASK__VI 0x01000000L -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK__VI 0x10000000L -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK__VI 0x10000000L -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIR_CNTL_DIVIDER_MASK__VI 0x0001fc00L -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIR_CNTL_EN_MASK__VI 0x00000100L -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIR_CNTL_TOG_MASK__VI 0x00000200L -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIVIDER_MASK__VI 0x0000007fL -#define CG_ACLK_DIV_PSPCLK_OVERCLOCKING_ATTEMPTS__ACLK_DIV_ATTEMPTS_MASK__VI 0x0000ffffL -#define CG_ACLK_DIV_PSPCLK_OVERCLOCKING_ATTEMPTS__PSPCLK_ATTEMPTS_MASK__VI 0xffff0000L -#define CG_ACLK_DIV_STATUS__ACLK_DIV_DIR_CNTL_DONETOG_MASK__VI 0x00000002L -#define CG_ACLK_DIV_STATUS__ACLK_DIV_STATUS_MASK__VI 0x00000001L -#define CG_CGTT_OVERRIDE_0__CG_SMU_cgtt_lclk_override_MASK__VI 0x00000002L -#define CG_CLK_DIVIDER_STATUS_2__ACLK_DIV_DIVIDER_STATUS_MASK__VI 0x0000007fL -#define CG_CLK_DIVIDER_STATUS_2__PSPCLK_DIVIDER_STATUS_MASK__VI 0x00007f00L -#define CG_FPS_CNT__FPS_CNT_MASK__VI 0xffffffffL -#define CG_PSPCLK_CNTL__PSPCLK_DIR_CNTL_DIVIDER_MASK__VI 0x0001fc00L -#define CG_PSPCLK_CNTL__PSPCLK_DIR_CNTL_EN_MASK__VI 0x00000100L -#define CG_PSPCLK_CNTL__PSPCLK_DIR_CNTL_TOG_MASK__VI 0x00000200L -#define CG_PSPCLK_CNTL__PSPCLK_DIVIDER_MASK__VI 0x0000007fL -#define CG_PSPCLK_STATUS__PSPCLK_DIR_CNTL_DONETOG_MASK__VI 0x00000002L -#define CG_PSPCLK_STATUS__PSPCLK_STATUS_MASK__VI 0x00000001L -#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK__VI 0x00400000L -#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK__VI 0x40000000L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK__SI__CI 0x000000c0L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK__VI 0x00000180L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK__SI__CI 0x00000030L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK__VI 0x00000060L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK__SI__CI 0x00000007L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK__VI 0x0000000fL -#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK__SI__CI 0x0003ff00L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK__VI 0x0007fc00L -#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN_MASK__VI 0x00000200L -#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK__VI 0x00000800L -#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN_MASK__VI 0x00000400L -#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK__VI 0xfe000000L -#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK__VI 0x001e0000L -#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK__VI 0x01e00000L -#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK__VI 0x00010000L -#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK__VI 0x00000fffL -#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ_MASK__SI__CI 0xf0000000L -#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ_MASK__VI 0x0003c000L -#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON_MASK__VI 0x00002000L -#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK__VI 0x00000010L -#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK__VI 0x10000000L -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK__VI 0x00001000L -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK__SI__CI 0x07f00000L -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK__VI 0x01fc0000L -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK__VI 0x00000800L -#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK__VI 0x00000002L -#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK__SI__CI 0x000003f0L -#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK__VI 0x000007e0L -#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS_MASK__VI 0x0e000000L -#define CG_SPLL_STATUS__SPLL_DIVA_ACK_MASK__VI 0x02000000L -#define CG_SPLL_STATUS__SPLL_LOCK_TIMER_DONE_MASK__VI 0x01000000L -#define CG_SPLL_STATUS__SPLL_OTEST_LOCK_MASK__VI 0x00800000L -#define CG_ULV_VOTING__ACP_ULV_VOTE_EN_MASK__VI 0x00000040L -#define CG_ULV_VOTING__DC_AZ_ULV_VOTE_EN_MASK__VI 0x00000400L -#define CG_ULV_VOTING__GRBM_0_ULV_VOTE_EN_MASK__VI 0x00001000L -#define CG_ULV_VOTING__GRBM_10_ULV_VOTE_EN_MASK__VI 0x00400000L -#define CG_ULV_VOTING__GRBM_11_ULV_VOTE_EN_MASK__VI 0x00800000L -#define CG_ULV_VOTING__GRBM_12_ULV_VOTE_EN_MASK__VI 0x01000000L -#define CG_ULV_VOTING__GRBM_13_ULV_VOTE_EN_MASK__VI 0x02000000L -#define CG_ULV_VOTING__GRBM_14_ULV_VOTE_EN_MASK__VI 0x04000000L -#define CG_ULV_VOTING__GRBM_15_ULV_VOTE_EN_MASK__VI 0x08000000L -#define CG_ULV_VOTING__GRBM_1_ULV_VOTE_EN_MASK__VI 0x00002000L -#define CG_ULV_VOTING__GRBM_2_ULV_VOTE_EN_MASK__VI 0x00004000L -#define CG_ULV_VOTING__GRBM_3_ULV_VOTE_EN_MASK__VI 0x00008000L -#define CG_ULV_VOTING__GRBM_4_ULV_VOTE_EN_MASK__VI 0x00010000L -#define CG_ULV_VOTING__GRBM_5_ULV_VOTE_EN_MASK__VI 0x00020000L -#define CG_ULV_VOTING__GRBM_6_ULV_VOTE_EN_MASK__VI 0x00040000L -#define CG_ULV_VOTING__GRBM_7_ULV_VOTE_EN_MASK__VI 0x00080000L -#define CG_ULV_VOTING__GRBM_8_ULV_VOTE_EN_MASK__VI 0x00100000L -#define CG_ULV_VOTING__GRBM_9_ULV_VOTE_EN_MASK__VI 0x00200000L -#define CG_ULV_VOTING__RLC_ULV_VOTE_EN_MASK__VI 0x10000000L -#define CG_ULV_VOTING__SAM_ULV_VOTE_EN_MASK__VI 0x00000800L -#define CG_ULV_VOTING__SDMA_ULV_VOTE_EN_MASK__VI 0x00000080L -#define CG_ULV_VOTING__UVD_ULV_VOTE_EN_MASK__VI 0x00000100L -#define CG_ULV_VOTING__VCE_ULV_VOTE_EN_MASK__VI 0x00000200L -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK__VI 0x00002000L -#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK__VI 0xff000000L -#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK__VI 0xffffffffL -#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK__VI 0xffffffffL -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK__VI 0x0001ffe0L -#define COMPUTE_NOWHERE__DATA_MASK__VI 0xffffffffL -#define COMPUTE_RELAUNCH__IS_EVENT_MASK__VI 0x40000000L -#define COMPUTE_RELAUNCH__IS_STATE_MASK__VI 0x80000000L -#define COMPUTE_RELAUNCH__PAYLOAD_MASK__VI 0x3fffffffL -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK__VI 0xffffffffL -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK__VI 0x0000ffffL -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK__VI 0xffffffffL -#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK__VI 0x00000001L -#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK__VI 0x00000006L -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CPC_INT_CNTX_ID__CNTX_ID_MASK__VI 0x0fffffffL -#define CPC_INT_CNTX_ID__QUEUE_ID_MASK__VI 0x70000000L -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK__VI 0x000e0000L -#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK__VI 0x00000001L -#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK__VI 0x00000200L -#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK__VI 0x00004000L -#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK__VI 0x00200000L -#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK__VI 0x00100000L -#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK__VI 0x00008000L -#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK__VI 0x00000100L -#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK__VI 0x00002000L -#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK__VI 0x00400000L -#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK__VI 0x00800000L -#define CPM_CONTROL__SPARE_REGS_MASK__VI 0xff000000L -#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK__VI 0x00000002L -#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK__VI 0x00000400L -#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK__VI 0x00000010L -#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK__VI 0x00000020L -#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK__VI 0x00000004L -#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK__VI 0x00000800L -#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK__VI 0x00010000L -#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK__VI 0x00000008L -#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK__VI 0x00000080L -#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK__VI 0x00000040L -#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK__VI 0x00001000L -#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK__VI 0x02000000L -#define CP_APPEND_ADDR_HI__MTYPE_MASK__VI 0x18000000L -#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK__VI 0x000003ffL -#define CP_CE_COMPLETION_STATUS__STATUS_MASK__VI 0x00000003L -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK__VI 0xffffffffL -#define CP_CE_RB_OFFSET__RB_OFFSET_MASK__VI 0x000fffffL -#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK__SI__CI 0x00030000L -#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK__VI 0x00070000L -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK__VI 0x40000000L -#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK__VI 0x80000000L -#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK__VI 0x00000008L -#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK__VI 0x00000004L -#define CP_CPC_DEBUG__BUSY_EXTENDER_MASK__VI 0x00180000L -#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK__VI 0x00200000L -#define CP_CPC_IC_BASE_CNTL__ATC_MASK__VI 0x00800000L -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK__VI 0x18000000L -#define CP_CPC_IC_BASE_CNTL__VMID_MASK__VI 0x0000000fL -#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK__VI 0x0000ffffL -#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK__VI 0xfffff000L -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK__VI 0x00000020L -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK__VI 0x00000001L -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK__VI 0x00000010L -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK__VI 0x000000ffL -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK__VI 0x0000ff00L -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK__VI 0x000001ffL -#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK__VI 0x01000000L -#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK__VI 0x00400000L -#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK__VI 0x00800000L -#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK__VI 0x00002000L -#define CP_CPF_DEBUG__BUSY_EXTENDER_MASK__VI 0x00180000L -#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK__VI 0x00000200L -#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK__VI 0x00000080L -#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK__VI 0x00000100L -#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK__VI 0x00020000L -#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK__VI 0x08000000L -#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK__VI 0x04000000L -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK__VI 0x30000000L -#define CP_CPF_STATUS__PRT_BUSY_MASK__VI 0x00010000L -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK__SI__CI 0x00003f00L -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK__VI 0x0001ff00L -#define CP_DFY_CMD__OFFSET_MASK__VI 0x000001ffL -#define CP_DFY_CMD__SIZE_MASK__VI 0xffff0000L -#define CP_DFY_CNTL__ENABLE_MASK__VI 0x80000000L -#define CP_DFY_CNTL__LFSR_RESET_MASK__VI 0x10000000L -#define CP_DFY_CNTL__MODE_MASK__VI 0x60000000L -#define CP_DFY_CNTL__MTYPE_MASK__VI 0x0000000cL -#define CP_DFY_CNTL__POLICY_MASK__VI 0x00000001L -#define CP_DFY_CNTL__WRITE_DIS_MASK__VI 0x08000000L -#define CP_DFY_STAT__TAGS_PENDING_MASK__VI 0x01ff0000L -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK__VI 0xffffffffL -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK__VI 0x02000000L -#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK__VI 0x00c00000L -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK__VI 0x00002000L -#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK__VI 0x00000c00L -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK__VI 0x02000000L -#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK__VI 0x00c00000L -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK__VI 0x00002000L -#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK__VI 0x00000c00L -#define CP_DMA_PIO_CONTROL__DST_CACHE_POLICY_MASK__VI 0x02000000L -#define CP_DMA_PIO_CONTROL__DST_MTYPE_MASK__VI 0x00c00000L -#define CP_DMA_PIO_CONTROL__SRC_CACHE_POLICY_MASK__VI 0x00002000L -#define CP_DMA_PIO_CONTROL__SRC_MTYPE_MASK__VI 0x00000c00L -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK__VI 0xffffffffL -#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK__VI 0x0000ffffL -#define CP_DRAW_OBJECT__OBJECT_MASK__VI 0xffffffffL -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK__VI 0x00000004L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK__VI 0x00000001L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK__VI 0x00000002L -#define CP_DRAW_WINDOW_CNTL__MODE_MASK__VI 0x00000100L -#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK__VI 0xffffffffL -#define CP_DRAW_WINDOW_LO__MAX_MASK__VI 0xffff0000L -#define CP_DRAW_WINDOW_LO__MIN_MASK__VI 0x0000ffffL -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK__VI 0xffffffffL -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK__VI 0xffffffffL -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK__VI 0xffffffffL -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK__VI 0xffffffffL -#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK__VI 0x000000f0L -#define CP_ECC_FIRSTOCCURRENCE__ME_MASK__VI 0x00000300L -#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK__VI 0x00000c00L -#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK__VI 0x00007000L -#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK__VI 0x0fffffffL -#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK__VI 0x02000000L -#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK__VI 0x18000000L -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK__VI 0xffffffffL -#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK__VI 0x000000e0L -#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK__VI 0x0000ff00L -#define CP_HPD_STATUS0__QUEUE_STATE_MASK__VI 0x0000001fL -#define CP_HQD_ACTIVE__BUSY_GATE_MASK__VI 0x00000002L -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK__VI 0x00007ffcL -#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK__VI 0x00007000L -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK__VI 0xfffff000L -#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK__VI 0x00000001L -#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK__VI 0x00000006L -#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK__VI 0x00000008L -#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK__VI 0x01fff000L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK__VI 0x00000400L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK__VI 0x00000007L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK__VI 0x00000200L -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK__VI 0x000000ffL -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK__VI 0xffffffffL -#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK__VI 0x00800000L -#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK__VI 0x0000003fL -#define CP_HQD_EOP_CONTROL__MTYPE_MASK__VI 0x00018000L -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK__VI 0x80000000L -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK__VI 0x00002000L -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK__VI 0x00000100L -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK__VI 0x00004000L -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK__VI 0x00001000L -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK__VI 0x60000000L -#define CP_HQD_EOP_DONES__DONE_COUNT_MASK__VI 0xffffffffL -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK__VI 0x00010000L -#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK__VI 0x00000fffL -#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK__VI 0x80000000L -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK__VI 0x40000000L -#define CP_HQD_EOP_RPTR__RPTR_MASK__VI 0x00001fffL -#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK__VI 0x00001fffL -#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK__VI 0x1fff0000L -#define CP_HQD_EOP_WPTR__WPTR_MASK__VI 0x00001fffL -#define CP_HQD_ERROR__EDC_ERROR_ID_MASK__VI 0x0000000fL -#define CP_HQD_ERROR__SUA_ERROR_MASK__VI 0x00000010L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK__VI 0x0003f000L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK__VI 0x000003f0L -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK__VI 0x00000002L -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK__VI 0x00000001L -#define CP_HQD_HQ_CONTROL0__CONTROL_MASK__VI 0xffffffffL -#define CP_HQD_HQ_CONTROL1__CONTROL_MASK__VI 0xffffffffL -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK__VI 0xffffffffL -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK__VI 0x0000000cL -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK__VI 0x00000003L -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK__VI 0x00000200L -#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK__VI 0xfffffc00L -#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK__VI 0x00000070L -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK__VI 0x00000080L -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK__VI 0x00000100L -#define CP_HQD_HQ_STATUS1__STATUS_MASK__VI 0xffffffffL -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK__VI 0x01000000L -#define CP_HQD_IB_CONTROL__MTYPE_MASK__VI 0x18000000L -#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK__VI 0x0000c000L -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK__VI 0x00000800L -#define CP_HQD_IQ_TIMER__MTYPE_MASK__VI 0x18000000L -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK__VI 0x00400000L -#define CP_HQD_MSG_TYPE__ACTION_MASK__VI 0x00000007L -#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK__VI 0x00000070L -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK__VI 0x00000002L -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK__VI 0x00000001L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK__VI 0x00000020L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK__VI 0x00000010L -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK__VI 0x40000000L -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK__VI 0x20000000L -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK__VI 0x10000000L -#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK__VI 0x00060000L -#define CP_HQD_PQ_CONTROL__MTYPE_MASK__VI 0x00018000L -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK__VI 0x06000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK__VI 0x00000002L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK__VI 0x03800000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK__VI 0x00000001L -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK__VI 0x80000000L -#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK__VI 0x01fffffcL -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x00000fffL -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK__VI 0xffffffffL -#define CP_HYP_CONFIG_RANGE_BASE_1__BASE_MASK__VI 0x0000ffffL -#define CP_HYP_CONFIG_RANGE_BASE_2__BASE_MASK__VI 0x0000ffffL -#define CP_HYP_CONFIG_RANGE_END_1__END_MASK__VI 0x0000ffffL -#define CP_HYP_CONFIG_RANGE_END_2__END_MASK__VI 0x0000ffffL -#define CP_HYP_CONTEXT_RANGE_BASE__BASE_MASK__VI 0x0000ffffL -#define CP_HYP_CONTEXT_RANGE_END__END_MASK__VI 0x0000ffffL -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x0001ffffL -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK__VI 0xffffffffL -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x0001ffffL -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK__VI 0xffffffffL -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x00001fffL -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK__VI 0xffffffffL -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x00001fffL -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK__VI 0xffffffffL -#define CP_HYP_SHADER_RANGE_BASE__BASE_MASK__VI 0x0000ffffL -#define CP_HYP_SHADER_RANGE_END__END_MASK__VI 0x0000ffffL -#define CP_HYP_UCONFIG_RANGE_BASE__BASE_MASK__VI 0x0000ffffL -#define CP_HYP_UCONFIG_RANGE_END__END_MASK__VI 0x0000ffffL -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK__VI 0xffffffffL -#define CP_INDEX_TYPE__INDEX_TYPE_MASK__VI 0x00000003L -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK__VI 0x00040000L -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK__VI 0x00000800L -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK__VI 0x00200000L -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK__VI 0x00040000L -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK__VI 0x00000800L -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK__VI 0x00200000L -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK__VI 0x00040000L -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK__VI 0x00000800L -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK__VI 0x00200000L -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK__VI 0x00040000L -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK__VI 0x00000800L -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK__VI 0x00200000L -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK__VI 0x00040000L -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK__VI 0x00000800L -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK__VI 0x00080000L -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK__VI 0x00200000L -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK__VI 0x00040000L -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK__VI 0x00000800L -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK__VI 0x00200000L -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK__VI 0x00040000L -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK__VI 0x00000800L -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK__VI 0x00200000L -#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK__VI 0x00040000L -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK__VI 0x00000800L -#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK__VI 0x00200000L -#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK__VI 0x00040000L -#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK__VI 0x00000800L -#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK__VI 0x00200000L -#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK__VI 0x00001000L -#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK__VI 0x00001000L -#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK__VI 0x00001000L -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK__VI 0x00008000L -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK__VI 0x00001000L -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK__VI 0x00008000L -#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK__VI 0x00000100L -#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK__VI 0x00000010L -#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK__VI 0x00000001L -#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK__VI 0x00000020L -#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK__VI 0x00000008L -#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK__VI 0x00000200L -#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK__VI 0x00000080L -#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK__VI 0x00000040L -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK__VI 0x00000100L -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK__VI 0x00000010L -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK__VI 0x00000001L -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK__VI 0x00000020L -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK__VI 0x00000008L -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK__VI 0x00000200L -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK__VI 0x00000002L -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK__VI 0x00000004L -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK__VI 0x00000080L -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK__VI 0x00000040L -#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK__VI 0x0000ffffL -#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK__VI 0x0000ffffL -#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK__VI 0x00000100L -#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK__VI 0x00000010L -#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK__VI 0x00000001L -#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK__VI 0x00000020L -#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK__VI 0x00000008L -#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK__VI 0x00000200L -#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK__VI 0x00000080L -#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK__VI 0x00000040L -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK__VI 0x00000100L -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK__VI 0x00000010L -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK__VI 0x00000001L -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK__VI 0x00000020L -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK__VI 0x00000008L -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK__VI 0x00000200L -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK__VI 0x00000002L -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK__VI 0x00000004L -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK__VI 0x00000080L -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK__VI 0x00000040L -#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK__VI 0x0000ffffL -#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK__VI 0x0000ffffL -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK__VI 0x00010000L -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK__VI 0x00020000L -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK__VI 0x00040000L -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK__VI 0x00080000L -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK__VI 0x00100000L -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK__VI 0x00200000L -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK__VI 0x007ffffcL -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK__VI 0x007ffffcL -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x0001ffffL -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x0001ffffL -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK__VI 0x00000080L -#define CP_MEM_SLP_CNTL__RESERVED_MASK__SI__CI 0x000000fcL -#define CP_MEM_SLP_CNTL__RESERVED_MASK__VI 0x0000007cL -#define CP_ME_CNTL__CE_PIPE0_RESET_MASK__VI 0x00010000L -#define CP_ME_CNTL__ME_PIPE0_RESET_MASK__VI 0x00100000L -#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK__VI 0x00040000L -#define CP_ME_INTR_ROUTINE_START__IR_START_MASK__VI 0x00000fffL -#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK__VI 0x00400000L -#define CP_ME_MC_RADDR_HI__MTYPE_MASK__VI 0x00300000L -#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK__VI 0x00400000L -#define CP_ME_MC_WADDR_HI__MTYPE_MASK__VI 0x00300000L -#define CP_ME_PREEMPTION__OBSOLETE_MASK__VI 0x00000001L -#define CP_ME_PRGRM_CNTR_START__IP_START_MASK__VI 0x00000fffL -#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK__SI__CI 0x00000fffL -#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK__VI 0x00001fffL -#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK__SI__CI 0x00000fffL -#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK__VI 0x00001fffL -#define CP_MQD_CONTROL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_MQD_CONTROL__MTYPE_MASK__VI 0x18000000L -#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK__VI 0x00002000L -#define CP_MQD_CONTROL__PROCESSING_MQD_MASK__VI 0x00001000L -#define CP_PFP_COMPLETION_STATUS__STATUS_MASK__VI 0x00000003L -#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK__VI 0x00000fffL -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK__VI 0xffffffffL -#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK__VI 0x00000fffL -#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK__SI__CI 0x00000fffL -#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK__VI 0x00001fffL -#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK__VI 0x02000000L -#define CP_PIPE_STATS_CONTROL__MTYPE_MASK__VI 0x18000000L -#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK__VI 0x00000002L -#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK__VI 0x00000001L -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK__VI 0x00000001L -#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK__VI 0x10000000L -#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK__VI 0xc0000000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK__VI 0x00000100L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK__VI 0x00000200L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK__VI 0x00000400L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK__VI 0x00000800L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK__VI 0x00010000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK__VI 0x00020000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK__VI 0x00040000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK__VI 0x00080000L -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK__VI 0x00000001L -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK__VI 0x00000002L -#define CP_RB0_CNTL__BUF_SWAP_MASK__SI__CI 0x00030000L -#define CP_RB0_CNTL__BUF_SWAP_MASK__VI 0x00060000L -#define CP_RB0_CNTL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_RB0_CNTL__MTYPE_MASK__VI 0x00018000L -#define CP_RB1_CNTL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_RB1_CNTL__MTYPE_MASK__VI 0x00018000L -#define CP_RB2_CNTL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_RB2_CNTL__MTYPE_MASK__VI 0x00018000L -#define CP_RB_CNTL__BUF_SWAP_MASK__SI__CI 0x00030000L -#define CP_RB_CNTL__BUF_SWAP_MASK__VI 0x00060000L -#define CP_RB_CNTL__CACHE_POLICY_MASK__VI 0x01000000L -#define CP_RB_CNTL__MTYPE_MASK__VI 0x00018000L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK__VI 0x40000000L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK__VI 0x80000000L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK__VI 0x007ffffcL -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK__VI 0x007ffffcL -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK__VI 0x007ffffcL -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK__VI 0x00000080L -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK__VI 0x00000040L -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK__VI 0x00000004L -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK__VI 0x00000020L -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK__VI 0x00000008L -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK__VI 0x00000002L -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK__VI 0x00000010L -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK__VI 0x00000001L -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK__VI 0x00004000L -#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK__VI 0x00100000L -#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK__VI 0x00040000L -#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK__VI 0x00080000L -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK__VI 0x00020000L -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK__VI 0x00010000L -#define CP_STAT__ATCL2IU_BUSY_MASK__VI 0x00004000L -#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK__VI 0x02000000L -#define CP_STREAM_OUT_CONTROL__MTYPE_MASK__VI 0x18000000L -#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK__VI 0x000f0000L -#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK__VI 0xffff0000L -#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK__VI 0x0000ffffL -#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_APER_AD_MASK__VI 0x0000001eL -#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK__VI 0x00000001L -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK__VI 0x40000000L -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK__VI 0x80000000L -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK__VI 0x00000010L -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK__VI 0x00000020L -#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK__VI 0x00020000L -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK__VI 0x00001000L -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK__VI 0x00008000L -#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK__VI 0x40000000L -#define DB_Z_INFO__CLEAR_DISALLOWED_MASK__VI 0x40000000L -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK__VI 0x07800000L -#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK__VI 0x00000080L -#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK__VI 0x00000100L -#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK__VI 0x00000040L -#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK__VI 0x00000200L -#define DEVICE_CAP2__LTR_SUPPORTED_MASK__VI 0x00000800L -#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK__VI 0x00000400L -#define DEVICE_CAP2__OBFF_SUPPORTED_MASK__VI 0x000c0000L -#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK__VI 0x00003000L -#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK__VI 0x00000080L -#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK__VI 0x00000040L -#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK__VI 0x00000200L -#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK__VI 0x00000100L -#define DEVICE_CNTL2__LTR_EN_MASK__VI 0x00000400L -#define DEVICE_CNTL2__OBFF_EN_MASK__VI 0x00006000L -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK__VI 0x00000020L -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK__VI 0x00000001L -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK__VI 0x00000010L -#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK__VI 0x0000000cL -#define DIDT_DBR_CTRL0__UNUSED_0_MASK__VI 0xffffffc0L -#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK__VI 0x00000002L -#define DIDT_DBR_CTRL1__MAX_POWER_MASK__VI 0xffff0000L -#define DIDT_DBR_CTRL1__MIN_POWER_MASK__VI 0x0000ffffL -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK__VI 0x78000000L -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK__VI 0x00003fffL -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK__VI 0x03ff0000L -#define DIDT_DBR_CTRL2__UNUSED_0_MASK__VI 0x0000c000L -#define DIDT_DBR_CTRL2__UNUSED_1_MASK__VI 0x04000000L -#define DIDT_DBR_CTRL2__UNUSED_2_MASK__VI 0x80000000L -#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK__VI 0xffff0000L -#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK__VI 0x0000ffffL -#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK__VI 0x000000ffL -#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK__VI 0x0000ff00L -#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK__VI 0x00ff0000L -#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK__VI 0xff000000L -#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK__VI 0x000000ffL -#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK__VI 0x0000ff00L -#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK__VI 0x00ff0000L -#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK__VI 0xff000000L -#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK__VI 0x00ff0000L -#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK__VI 0xff000000L -#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK__VI 0x000000ffL -#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK__VI 0x0000ff00L -#define DIDT_DB_CTRL0__UNUSED_0_MASK__VI 0xffffffc0L -#define DIDT_DB_CTRL2__UNUSED_0_MASK__VI 0x0000c000L -#define DIDT_DB_CTRL2__UNUSED_1_MASK__VI 0x04000000L -#define DIDT_DB_CTRL2__UNUSED_2_MASK__VI 0x80000000L -#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK__VI 0xffff0000L -#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK__VI 0x0000ffffL -#define DIDT_SQ_CTRL0__UNUSED_0_MASK__VI 0xffffffc0L -#define DIDT_SQ_CTRL2__UNUSED_0_MASK__VI 0x0000c000L -#define DIDT_SQ_CTRL2__UNUSED_1_MASK__VI 0x04000000L -#define DIDT_SQ_CTRL2__UNUSED_2_MASK__VI 0x80000000L -#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK__VI 0xffff0000L -#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK__VI 0x0000ffffL -#define DIDT_TCP_CTRL0__UNUSED_0_MASK__VI 0xffffffc0L -#define DIDT_TCP_CTRL2__UNUSED_0_MASK__VI 0x0000c000L -#define DIDT_TCP_CTRL2__UNUSED_1_MASK__VI 0x04000000L -#define DIDT_TCP_CTRL2__UNUSED_2_MASK__VI 0x80000000L -#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK__VI 0xffff0000L -#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK__VI 0x0000ffffL -#define DIDT_TD_CTRL0__UNUSED_0_MASK__VI 0xffffffc0L -#define DIDT_TD_CTRL2__UNUSED_0_MASK__VI 0x0000c000L -#define DIDT_TD_CTRL2__UNUSED_1_MASK__VI 0x04000000L -#define DIDT_TD_CTRL2__UNUSED_2_MASK__VI 0x80000000L -#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK__VI 0xffff0000L -#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK__VI 0x0000ffffL -#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK__VI 0x0007fffcL -#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK__VI 0x00008000L -#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK__VI 0x00002000L -#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK__VI 0x40000000L -#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK__VI 0x00000100L -#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK__VI 0x00000200L -#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK__VI 0x00000010L -#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK__VI 0x00000020L -#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK__VI 0x00020000L -#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK__VI 0x00040000L -#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK__VI 0x00004000L -#define GCK_ACLK_DIV_FUSES__AClkDivADCA_MASK__VI 0x00000780L -#define GCK_ACLK_DIV_FUSES__AClkDivDDCA_MASK__VI 0x00001800L -#define GCK_ACLK_DIV_FUSES__AClkDivDiDtFloor_MASK__VI 0x00030000L -#define GCK_ACLK_DIV_FUSES__AClkDivDiDtWait_MASK__VI 0x0000e000L -#define GCK_ACLK_DIV_FUSES__StartupAClkDivDid_MASK__VI 0x0000007fL -#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK__VI 0x00e00000L -#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK__VI 0x38000000L -#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK__VI 0x00000e00L -#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK__VI 0x00038000L -#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK__VI 0x001c0000L -#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK__VI 0x00000007L -#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK__VI 0x000001c0L -#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK__VI 0x07000000L -#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK__VI 0x00000038L -#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK__VI 0x00007000L -#define GCK_ADFS_CLK_BYPASS_CNTL2__PSPCLK_BYPASS_CNTL_MASK__VI 0x00000007L -#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK__VI 0x00000080L -#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK__VI 0x00000100L -#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK__VI 0x00000008L -#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK__VI 0x00000020L -#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK__VI 0x00000040L -#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK__VI 0x00000001L -#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK__VI 0x00000004L -#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK__VI 0x00000002L -#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK__VI 0x00000200L -#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK__VI 0x00000400L -#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK__VI 0x00000800L -#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK__VI 0x00000010L -#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK__VI 0x00001000L -#define GCK_GPUPLL_DGCK_CNTL_1__GPUPLL_LOCK_TIMER_MASK__VI 0xffff0000L -#define GCK_GPUPLL_DGCK_CNTL_1__GPUPLL_PWRON_TIMER_MASK__VI 0x0000ffffL -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_CLKF_UPDATE_MASK__VI 0x00000002L -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_MIN_PWRDN_TIMER_MASK__VI 0x000001f8L -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_RESET_EN_MASK__VI 0x00000001L -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_TEST_UNLOCK_CLR_MASK__VI 0x00000004L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_BG_PWRON_MASK__VI 0x00400000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EN_MASK__VI 0x00001800L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EXT_SEL_MASK__VI 0x000007e0L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_TEST_SEL_MASK__VI 0x0000000fL -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SPARE_MASK__VI 0x0007c000L -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SSAMP_EN_MASK__VI 0x00002000L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_LF_CNTR_MASK__VI 0xfe000000L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_VCTL_CNTRL_IN_MASK__VI 0x001e0000L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_VCTL_CNTRL_OUT_MASK__VI 0x01e00000L -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_VCTL_EN_MASK__VI 0x00010000L -#define GCK_GPUPLL_DGCK_CNTL_6__GPUPLL_FBDIV_SSC_BYPASS_MASK__VI 0x00000001L -#define GCK_GPUPLL_DGCK_CNTL_6__GPUPLL_TEST_FRAC_BYPASS_MASK__VI 0x00000002L -#define GCK_GPUPLL_DGCK_CNTL_7__GPUPLL_BW_CNTRL_MASK__VI 0x00000fffL -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_BYPASS_EN_MASK__VI 0x04000000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_INIT_RESET_TIMER_MASK__VI 0x01ffe000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_OTEST_LOCK_EN_MASK__VI 0x20000000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_PWRON_MASK__VI 0x08000000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_REG_BIAS_MASK__VI 0x00001c00L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_RESET_MASK__VI 0x02000000L -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_UNLOCK_CLEAR_MASK__VI 0x10000000L -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_BGADJ_MASK__VI 0x000f0000L -#define GCK_GPUPLL_STATUS__GPUPLL_LOCK_TIMER_DONE_MASK__VI 0x01000000L -#define GCK_GPUPLL_STATUS__GPUPLL_OPWRGOOD_ISO_ENB_MASK__VI 0x00400000L -#define GCK_GPUPLL_STATUS__GPUPLL_OPWRGOOD_S_MASK__VI 0x00200000L -#define GCK_GPUPLL_STATUS__GPUPLL_OPWRGOOD_V_MASK__VI 0x00100000L -#define GCK_GPUPLL_STATUS__GPUPLL_OTEST_LOCK_MASK__VI 0x00800000L -#define GCK_GPUPLL_STATUS__GPUPLL_VCTRLADC_MASK__VI 0x00000070L -#define GCK_LCLK_FUSES__LClkADCA_MASK__VI 0x00000780L -#define GCK_LCLK_FUSES__LClkDDCA_MASK__VI 0x00001800L -#define GCK_LCLK_FUSES__LClkDiDtFloor_MASK__VI 0x00030000L -#define GCK_LCLK_FUSES__LClkDiDtWait_MASK__VI 0x0000e000L -#define GCK_LCLK_FUSES__StartupLClkDid_MASK__VI 0x0000007fL -#define GCK_MISC_FUSES__PSP_ENABLE_MASK__VI 0x40000000L -#define GCK_MISC_FUSES__WRITE_DIS_MASK_MASK__VI 0x0003ffc0L -#define GCK_MISC__EnableACLK_DIVInBypass_MASK__VI 0x00000200L -#define GCK_MISC__EnablePSPCLKInBypass_MASK__VI 0x00000400L -#define GCK_MISC__PostDivCntlDis_MASK__VI 0x00000800L -#define GCK_MISC__Reserved_MASK__VI 0x00000100L -#define GCK_MISC__miscRegisters_MASK__VI 0xfffff000L -#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK__VI 0xfffe0000L -#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK__VI 0x0001fc00L -#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK__VI 0x00040000L -#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK__VI 0x000003e0L -#define GCK_PLL_TEST_CNTL__TST_RESET_MASK__VI 0x00020000L -#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK__VI 0x0000001fL -#define GCK_PSPCLK_FUSES__PspClkADCA_MASK__VI 0x00000780L -#define GCK_PSPCLK_FUSES__PspClkDDCA_MASK__VI 0x00001800L -#define GCK_PSPCLK_FUSES__PspClkDiDtFloor_MASK__VI 0x00030000L -#define GCK_PSPCLK_FUSES__PspClkDiDtWait_MASK__VI 0x0000e000L -#define GCK_PSPCLK_FUSES__StartupPspClkDid_MASK__VI 0x0000007fL -#define GCK_RESET_TMR_FUSES__Start_GPUPLL_INIT_RESET_TIMER_MASK__VI 0x0fff0000L -#define GCK_RESET_TMR_FUSES__Start_GPUPLL_PWRON_TIMER_MASK__VI 0x0000ffffL -#define GCK_SPARE_1__GCK_SPARE_1_MASK__VI 0xffffffffL -#define GCK_TPLL_FUSES__Start_GPUPLL_BGADJ_MASK__VI 0x0000f000L -#define GCK_TPLL_FUSES__Start_GPUPLL_BW_CNTRL_MASK__VI 0x00000fffL -#define GCK_TPLL_FUSES__Start_GPUPLL_REG_BIAS_MASK__VI 0x00e00000L -#define GCK_TPLL_FUSES__Start_GPUPLL_VCOMODE_MASK__VI 0x00180000L -#define GCK_TPLL_FUSES__Start_PFD_RESET_CNTRL_MASK__VI 0x00060000L -#define GCK_TPLL_FUSES__Start_VTOI_BIAS_CNTL_MASK__VI 0x00010000L -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG4__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG5__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG6__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_CU_LKG7__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_GCATCL20__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_NONCU_LKG0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_NONCU_LKG1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_NONCU_LKG2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_NONCU_LKG3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_NONCU_LKG4__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_NONCU_LKG5__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_NONCU_LKG6__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK__VI 0x000000ffL -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK__VI 0xffffff00L -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK__VI 0xffffffffL -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK__VI 0x00000ff0L -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK__VI 0x0000000fL -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK__VI 0x40000000L -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK__VI 0x80000000L -#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK__VI 0x007e0000L -#define GC_CAC_CNTL__CAC_ENABLE_MASK__VI 0x00000001L -#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK__VI 0x7f800000L -#define GC_CAC_CNTL__CAC_THRESHOLD_MASK__VI 0x0001fffeL -#define GC_CAC_CNTL__UNUSED_0_MASK__VI 0x80000000L -#define GC_CAC_CTRL_1__CAC_WINDOW_MASK__VI 0x00ffffffL -#define GC_CAC_CTRL_1__TDP_WINDOW_MASK__VI 0xff000000L -#define GC_CAC_CTRL_2__CAC_ENABLE_MASK__VI 0x00000001L -#define GC_CAC_CTRL_2__UNUSED_0_MASK__VI 0xfffffffeL -#define GC_CAC_IND_DATA__CAC_IND_DATA_MASK__VI 0xffffffffL -#define GC_CAC_IND_INDEX__CAC_IND_ADDR_MASK__VI 0xffffffffL -#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK__VI 0xffffffffL -#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK__VI 0xffffffffL -#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_CU_LKG__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_CU_LKG__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_GCATCL2__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_GCATCL2__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_NONCU_LKG__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_NONCU_LKG__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK__VI 0x0000ffffL -#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK__VI 0xffff0000L -#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK__VI 0xffffffffL -#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK__VI 0xffffffffL -#define GC_CAC_WEIGHT_BCI_0__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CU_LKG_0__WEIGHT_CU_LKG_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CU_LKG_0__WEIGHT_CU_LKG_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CU_LKG_1__WEIGHT_CU_LKG_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CU_LKG_1__WEIGHT_CU_LKG_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CU_LKG_2__WEIGHT_CU_LKG_SIG4_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CU_LKG_2__WEIGHT_CU_LKG_SIG5_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_CU_LKG_3__WEIGHT_CU_LKG_SIG6_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_CU_LKG_3__WEIGHT_CU_LKG_SIG7_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_GCATCL2_0__WEIGHT_GCATCL2_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_GCATCL2_0__unused_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_NONCU_LKG_0__WEIGHT_NONCU_LKG_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_NONCU_LKG_0__WEIGHT_NONCU_LKG_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_NONCU_LKG_1__WEIGHT_NONCU_LKG_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_NONCU_LKG_1__WEIGHT_NONCU_LKG_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_NONCU_LKG_2__WEIGHT_NONCU_LKG_SIG4_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_NONCU_LKG_2__WEIGHT_NONCU_LKG_SIG5_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_NONCU_LKG_3__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_NONCU_LKG_3__WEIGHT_NONCU_LKG_SIG6_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK__VI 0x0000ffffL -#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK__VI 0xffff0000L -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK__VI 0x0000ffffL -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK__VI 0x00000006L -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK__VI 0x00000010L -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK__VI 0x00000008L -#define GDS_ATOM_CNTL__DMODE_MASK__SI__CI 0x00000100L -#define GDS_ATOM_CNTL__DMODE_MASK__VI 0x00000300L -#define GDS_ATOM_CNTL__UNUSED2_MASK__SI__CI 0xfffffe00L -#define GDS_ATOM_CNTL__UNUSED2_MASK__VI 0xfffffc00L -#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK__VI 0x00000800L -#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK__VI 0x00001000L -#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK__VI 0x00002000L -#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK__VI 0x00004000L -#define GDS_CNTL_STATUS__DS_BUSY_MASK__VI 0x00000100L -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK__VI 0x00000080L -#define GDS_CNTL_STATUS__GWS_BUSY_MASK__VI 0x00000200L -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK__VI 0x00000400L -#define GDS_CS_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_CS_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_CS_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_CS_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_CS_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_CS_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_CS_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_CS_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_CS_CTXSW_STATUS__R_MASK__VI 0x00000001L -#define GDS_CS_CTXSW_STATUS__UNUSED_MASK__VI 0xfffffffcL -#define GDS_CS_CTXSW_STATUS__W_MASK__VI 0x00000002L -#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK__VI 0x00000004L -#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK__VI 0x00000020L -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK__VI 0x00000001L -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK__VI 0x00000002L -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK__VI 0x00000008L -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK__VI 0x00000010L -#define GDS_DSM_CNTL__UNUSED_MASK__VI 0xffffffc0L -#define GDS_EDC_CNT__DED_MASK__VI 0x000000ffL -#define GDS_EDC_CNT__SEC_MASK__VI 0x00ff0000L -#define GDS_EDC_CNT__SED_MASK__VI 0x0000ff00L -#define GDS_EDC_GRBM_CNT__DED_MASK__VI 0x000000ffL -#define GDS_EDC_GRBM_CNT__SEC_MASK__VI 0x00ff0000L -#define GDS_EDC_OA_DED__ME0_CS_DED_MASK__VI 0x00000004L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK__VI 0x00000001L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK__VI 0x00000002L -#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK__VI 0x00000010L -#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK__VI 0x00000020L -#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK__VI 0x00000040L -#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK__VI 0x00000080L -#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK__VI 0x00000100L -#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK__VI 0x00000200L -#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK__VI 0x00000400L -#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK__VI 0x00000800L -#define GDS_EDC_OA_DED__UNUSED0_MASK__VI 0x00000008L -#define GDS_EDC_OA_DED__UNUSED1_MASK__VI 0xfffff000L -#define GDS_GFX_CTXSW_STATUS__R_MASK__VI 0x00000001L -#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK__VI 0xfffffffcL -#define GDS_GFX_CTXSW_STATUS__W_MASK__VI 0x00000002L -#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK__SI__CI 0x10000000L -#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK__VI 0x20000000L -#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK__SI__CI 0x07ff0000L -#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK__VI 0x0fff0000L -#define GDS_GWS_RESOURCE__HEAD_VALID_MASK__SI__CI 0x08000000L -#define GDS_GWS_RESOURCE__HEAD_VALID_MASK__VI 0x10000000L -#define GDS_GWS_RESOURCE__UNUSED1_MASK__SI__CI 0xe0000000L -#define GDS_GWS_RESOURCE__UNUSED1_MASK__VI 0xc0000000L -#define GDS_OA_ADDRESS__CRAWLER_MASK__VI 0x000f0000L -#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK__VI 0x00300000L -#define GDS_OA_ADDRESS__UNUSED_MASK__VI 0x3fc00000L -#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK__VI 0x000f0000L -#define GDS_OA_CGPG_RESTORE__UNUSED_MASK__VI 0xfff00000L -#define GDS_PS0_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS0_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS0_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS0_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS0_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS0_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS0_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS0_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS1_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS1_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS1_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS1_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS1_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS1_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS1_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS1_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS2_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS2_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS2_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS2_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS2_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS2_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS2_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS2_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS3_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS3_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS3_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS3_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS3_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS3_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS3_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS3_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS4_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS4_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS4_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS4_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS4_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS4_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS4_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS4_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS5_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS5_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS5_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS5_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS5_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS5_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS5_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS5_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS6_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS6_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS6_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS6_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS6_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS6_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS6_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS6_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS7_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_PS7_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS7_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_PS7_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS7_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_PS7_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_PS7_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_PS7_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GDS_VS_CTXSW_CNT0__PTR_MASK__VI 0xffff0000L -#define GDS_VS_CTXSW_CNT0__UPDN_MASK__VI 0x0000ffffL -#define GDS_VS_CTXSW_CNT1__PTR_MASK__VI 0xffff0000L -#define GDS_VS_CTXSW_CNT1__UPDN_MASK__VI 0x0000ffffL -#define GDS_VS_CTXSW_CNT2__PTR_MASK__VI 0xffff0000L -#define GDS_VS_CTXSW_CNT2__UPDN_MASK__VI 0x0000ffffL -#define GDS_VS_CTXSW_CNT3__PTR_MASK__VI 0xffff0000L -#define GDS_VS_CTXSW_CNT3__UPDN_MASK__VI 0x0000ffffL -#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK__VI 0x00000004L -#define GMCON_DEBUG__MISC_FLAGS_MASK__VI 0xffffff00L -#define GMCON_DEBUG__SR_COMMIT_STATE_MASK__VI 0x00000008L -#define GMCON_DEBUG__STCTRL_ST_MASK__VI 0x000000f0L -#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK__VI 0xffffffffL -#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK__VI 0x00000ff0L -#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK__VI 0x0000003fL -#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK__VI 0x1ffe0000L -#define GMCON_MISC3__RENG_DISABLE_MCC_MASK__VI 0x000000ffL -#define GMCON_MISC3__RENG_DISABLE_MCD_MASK__VI 0x0000ff00L -#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK__VI 0x20000000L -#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK__VI 0x40000000L -#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK__VI 0x0fff0000L -#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK__VI 0x10000000L -#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK__VI 0x40000000L -#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK__VI 0x80000000L -#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK__VI 0x20000000L -#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK__VI 0x01fc0000L -#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK__VI 0xfe000000L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_10_MASK__VI 0x00000400L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_11_MASK__VI 0x00000800L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_12_MASK__VI 0x00001000L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_13_MASK__VI 0x00002000L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_14_MASK__VI 0x00004000L -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_15_MASK__VI 0x00008000L -#define GPU_BIST_CONTROL__CP_DFY_CNTL_WRITE_DIS_MASK__VI 0x00000040L -#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK__VI 0x0000003cL -#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK__VI 0xff000000L -#define GPU_BIST_CONTROL__RESERVED_MASK__VI 0x00ffff80L -#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK__VI 0x00000002L -#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK__VI 0x00000001L -#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK__VI 0x00001000L -#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK__VI 0x00002000L -#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK__VI 0x00001000L -#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK__VI 0x00002000L -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK__VI 0x00000ff0L -#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK__VI 0x0000000fL -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK__VI 0x40000000L -#define GRBM_CNTL__REPORT_LAST_RDERR_MASK__VI 0x80000000L -#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK__VI 0x80000000L -#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK__VI 0x00002000L -#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK__VI 0x00000003L -#define GRBM_DSM_BYPASS__BYPASS_EN_MASK__VI 0x00000004L -#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK__VI 0x0000ffffL -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK__VI 0xffff0000L -#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK__VI 0x00000007L -#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK__VI 0x00008000L -#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK__VI 0x00000003L -#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK__VI 0x00000030L -#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK__VI 0x00004000L -#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK__VI 0x0000000cL -#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK__VI 0x000000c0L -#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK__VI 0x00100000L -#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK__VI 0x04000000L -#define GRBM_TRAP_ADDR_MSK__DATA_MASK__VI 0x0000ffffL -#define GRBM_TRAP_ADDR__DATA_MASK__VI 0x0000ffffL -#define GRBM_TRAP_OP__RW_MASK__VI 0x00000001L -#define GRBM_TRAP_WD_MSK__DATA_MASK__VI 0xffffffffL -#define GRBM_TRAP_WD__DATA_MASK__VI 0xffffffffL -#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK__VI 0x80000000L -#define GRBM_WRITE_ERROR__WRITE_MEID_MASK__VI 0x00c00000L -#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK__VI 0x00300000L -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK__VI 0x00000001L -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK__VI 0x00000002L -#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK__VI 0x0000001cL -#define GRBM_WRITE_ERROR__WRITE_VFID_MASK__VI 0x000001e0L -#define GRBM_WRITE_ERROR__WRITE_VF_MASK__VI 0x00001000L -#define GRBM_WRITE_ERROR__WRITE_VMID_MASK__VI 0x0001e000L -#define GSKT_CONTROL__GSKT_SpareRegs_MASK__VI 0x000000f8L -#define GSKT_CONTROL__GSKT_TxFifoBypass_MASK__VI 0x00000001L -#define GSKT_CONTROL__GSKT_TxFifoDelay2_MASK__VI 0x00000004L -#define GSKT_CONTROL__GSKT_TxFifoDelay_MASK__VI 0x00000002L -#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK__VI 0xf0000000L -#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK__VI 0x0fffffffL -#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK__VI 0x00000020L -#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK__VI 0x00000008L -#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK__VI 0x00000001L -#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK__VI 0x00000004L -#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK__VI 0x00000010L -#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK__VI 0xffffffffL -#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK__VI 0xffffffffL -#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK__VI 0xffffffffL -#define IH_RB_WPTR__RB_LEFT_NONE_MASK__VI 0x00040000L -#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK__VI 0x00080000L -#define IH_VERSION__VALUE_MASK__VI 0x00000fffL -#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK__VI 0x00008000L -#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK__VI 0x00000008L -#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK__VI 0xffc00000L -#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK__VI 0x00200000L -#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK__VI 0x7fff0000L -#define LM_CONTROL__LoopbackFifoPtr_MASK__VI 0x00000700L -#define LM_CONTROL__LoopbackHalfRate_MASK__VI 0x000000c0L -#define LM_CONTROL__LoopbackSelect_MASK__VI 0x0000001eL -#define LM_CONTROL__PRBSPCIeLbSelect_MASK__VI 0x00000020L -#define LM_LANEENABLE__LANE_enable_MASK__VI 0x0000ffffL -#define LM_PCIERXMUX0__RXLANE0_MASK__VI 0x000000ffL -#define LM_PCIERXMUX0__RXLANE1_MASK__VI 0x0000ff00L -#define LM_PCIERXMUX0__RXLANE2_MASK__VI 0x00ff0000L -#define LM_PCIERXMUX0__RXLANE3_MASK__VI 0xff000000L -#define LM_PCIERXMUX1__RXLANE4_MASK__VI 0x000000ffL -#define LM_PCIERXMUX1__RXLANE5_MASK__VI 0x0000ff00L -#define LM_PCIERXMUX1__RXLANE6_MASK__VI 0x00ff0000L -#define LM_PCIERXMUX1__RXLANE7_MASK__VI 0xff000000L -#define LM_PCIERXMUX2__RXLANE10_MASK__VI 0x00ff0000L -#define LM_PCIERXMUX2__RXLANE11_MASK__VI 0xff000000L -#define LM_PCIERXMUX2__RXLANE8_MASK__VI 0x000000ffL -#define LM_PCIERXMUX2__RXLANE9_MASK__VI 0x0000ff00L -#define LM_PCIERXMUX3__RXLANE12_MASK__VI 0x000000ffL -#define LM_PCIERXMUX3__RXLANE13_MASK__VI 0x0000ff00L -#define LM_PCIERXMUX3__RXLANE14_MASK__VI 0x00ff0000L -#define LM_PCIERXMUX3__RXLANE15_MASK__VI 0xff000000L -#define LM_PCIETXMUX0__TXLANE0_MASK__VI 0x000000ffL -#define LM_PCIETXMUX0__TXLANE1_MASK__VI 0x0000ff00L -#define LM_PCIETXMUX0__TXLANE2_MASK__VI 0x00ff0000L -#define LM_PCIETXMUX0__TXLANE3_MASK__VI 0xff000000L -#define LM_PCIETXMUX1__TXLANE4_MASK__VI 0x000000ffL -#define LM_PCIETXMUX1__TXLANE5_MASK__VI 0x0000ff00L -#define LM_PCIETXMUX1__TXLANE6_MASK__VI 0x00ff0000L -#define LM_PCIETXMUX1__TXLANE7_MASK__VI 0xff000000L -#define LM_PCIETXMUX2__TXLANE10_MASK__VI 0x00ff0000L -#define LM_PCIETXMUX2__TXLANE11_MASK__VI 0xff000000L -#define LM_PCIETXMUX2__TXLANE8_MASK__VI 0x000000ffL -#define LM_PCIETXMUX2__TXLANE9_MASK__VI 0x0000ff00L -#define LM_PCIETXMUX3__TXLANE12_MASK__VI 0x000000ffL -#define LM_PCIETXMUX3__TXLANE13_MASK__VI 0x0000ff00L -#define LM_PCIETXMUX3__TXLANE14_MASK__VI 0x00ff0000L -#define LM_PCIETXMUX3__TXLANE15_MASK__VI 0xff000000L -#define LM_POWERCONTROL1__LMDeemph0_MASK__VI 0x00000100L -#define LM_POWERCONTROL1__LMDeemph1_MASK__VI 0x00020000L -#define LM_POWERCONTROL1__LMDeemph2_MASK__VI 0x04000000L -#define LM_POWERCONTROL1__LMLaneUnused0_MASK__VI 0x00000040L -#define LM_POWERCONTROL1__LMLaneUnused1_MASK__VI 0x00008000L -#define LM_POWERCONTROL1__LMLaneUnused2_MASK__VI 0x01000000L -#define LM_POWERCONTROL1__LMSkipBit0_MASK__VI 0x00000020L -#define LM_POWERCONTROL1__LMSkipBit1_MASK__VI 0x00004000L -#define LM_POWERCONTROL1__LMSkipBit2_MASK__VI 0x00800000L -#define LM_POWERCONTROL1__LMTxClkEn0_MASK__VI 0x00000002L -#define LM_POWERCONTROL1__LMTxClkEn1_MASK__VI 0x00000400L -#define LM_POWERCONTROL1__LMTxClkEn2_MASK__VI 0x00080000L -#define LM_POWERCONTROL1__LMTxEn0_MASK__VI 0x00000001L -#define LM_POWERCONTROL1__LMTxEn1_MASK__VI 0x00000200L -#define LM_POWERCONTROL1__LMTxEn2_MASK__VI 0x00040000L -#define LM_POWERCONTROL1__LMTxMargin0_MASK__VI 0x0000001cL -#define LM_POWERCONTROL1__LMTxMargin1_MASK__VI 0x00003800L -#define LM_POWERCONTROL1__LMTxMargin2_MASK__VI 0x00700000L -#define LM_POWERCONTROL1__LMTxMarginEn0_MASK__VI 0x00000080L -#define LM_POWERCONTROL1__LMTxMarginEn1_MASK__VI 0x00010000L -#define LM_POWERCONTROL1__LMTxMarginEn2_MASK__VI 0x02000000L -#define LM_POWERCONTROL1__TxCoeffID0_MASK__VI 0x18000000L -#define LM_POWERCONTROL1__TxCoeffID1_MASK__VI 0x60000000L -#define LM_POWERCONTROL2__LMDeemph3_MASK__VI 0x00000100L -#define LM_POWERCONTROL2__LMLaneUnused3_MASK__VI 0x00000040L -#define LM_POWERCONTROL2__LMSkipBit3_MASK__VI 0x00000020L -#define LM_POWERCONTROL2__LMTxClkEn3_MASK__VI 0x00000002L -#define LM_POWERCONTROL2__LMTxEn3_MASK__VI 0x00000001L -#define LM_POWERCONTROL2__LMTxMargin3_MASK__VI 0x0000001cL -#define LM_POWERCONTROL2__LMTxMarginEn3_MASK__VI 0x00000080L -#define LM_POWERCONTROL2__TxCoeff0_MASK__VI 0x0007e000L -#define LM_POWERCONTROL2__TxCoeff1_MASK__VI 0x01f80000L -#define LM_POWERCONTROL2__TxCoeff2_MASK__VI 0x7e000000L -#define LM_POWERCONTROL2__TxCoeffID2_MASK__VI 0x00000600L -#define LM_POWERCONTROL2__TxCoeffID3_MASK__VI 0x00001800L -#define LM_POWERCONTROL3__RxEqCtl0_MASK__VI 0x00000fc0L -#define LM_POWERCONTROL3__RxEqCtl1_MASK__VI 0x0003f000L -#define LM_POWERCONTROL3__RxEqCtl2_MASK__VI 0x00fc0000L -#define LM_POWERCONTROL3__RxEqCtl3_MASK__VI 0x3f000000L -#define LM_POWERCONTROL3__TxCoeff3_MASK__VI 0x0000003fL -#define LM_POWERCONTROL4__LaneNum0_MASK__VI 0x0000f000L -#define LM_POWERCONTROL4__LaneNum1_MASK__VI 0x000f0000L -#define LM_POWERCONTROL4__LaneNum2_MASK__VI 0x00f00000L -#define LM_POWERCONTROL4__LaneNum3_MASK__VI 0x0f000000L -#define LM_POWERCONTROL4__LinkNum0_MASK__VI 0x00000007L -#define LM_POWERCONTROL4__LinkNum1_MASK__VI 0x00000038L -#define LM_POWERCONTROL4__LinkNum2_MASK__VI 0x000001c0L -#define LM_POWERCONTROL4__LinkNum3_MASK__VI 0x00000e00L -#define LM_POWERCONTROL4__SpcMode0_MASK__VI 0x10000000L -#define LM_POWERCONTROL4__SpcMode1_MASK__VI 0x20000000L -#define LM_POWERCONTROL4__SpcMode2_MASK__VI 0x40000000L -#define LM_POWERCONTROL4__SpcMode3_MASK__VI 0x80000000L -#define LM_POWERCONTROL__LMLinkSpeed0_MASK__VI 0x000000c0L -#define LM_POWERCONTROL__LMLinkSpeed1_MASK__VI 0x0000c000L -#define LM_POWERCONTROL__LMLinkSpeed2_MASK__VI 0x00c00000L -#define LM_POWERCONTROL__LMLinkSpeed3_MASK__VI 0xc0000000L -#define LM_POWERCONTROL__LMRxPhyCmd0_MASK__VI 0x00000038L -#define LM_POWERCONTROL__LMRxPhyCmd1_MASK__VI 0x00003800L -#define LM_POWERCONTROL__LMRxPhyCmd2_MASK__VI 0x00380000L -#define LM_POWERCONTROL__LMRxPhyCmd3_MASK__VI 0x38000000L -#define LM_POWERCONTROL__LMTxPhyCmd0_MASK__VI 0x00000007L -#define LM_POWERCONTROL__LMTxPhyCmd1_MASK__VI 0x00000700L -#define LM_POWERCONTROL__LMTxPhyCmd2_MASK__VI 0x00070000L -#define LM_POWERCONTROL__LMTxPhyCmd3_MASK__VI 0x07000000L -#define LM_PRBSCONTROL__LMLaneDegrade0_MASK__VI 0x10000000L -#define LM_PRBSCONTROL__LMLaneDegrade1_MASK__VI 0x20000000L -#define LM_PRBSCONTROL__LMLaneDegrade2_MASK__VI 0x40000000L -#define LM_PRBSCONTROL__LMLaneDegrade3_MASK__VI 0x80000000L -#define LM_PRBSCONTROL__PRBSPCIeSelect_MASK__VI 0x0000ffffL -#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK__VI 0x00000002L -#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK__VI 0x00000004L -#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK__VI 0x00000008L -#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK__VI 0x00000010L -#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK__VI 0x00000001L -#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK__VI 0x00000007L -#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK__VI 0x00000070L -#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK__VI 0x0000ffffL -#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK__VI 0xffff0000L -#define LNC_BW_WACC__LNC_BW_WACC_MASK__VI 0xffffffffL -#define LNC_CMN_WACC__LNC_CMN_WACC_MASK__VI 0xffffffffL -#define LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK__VI 0xffffffffL -#define LPML_SCALAR_1__Lpml1_MASK__VI 0x0000003fL -#define LPML_SCALAR_1__Lpml2_MASK__VI 0x00000fc0L -#define LPML_SCALAR_1__Lpml3_MASK__VI 0x0003f000L -#define LPML_SCALAR_1__Lpml4_MASK__VI 0x00fc0000L -#define LPML_SCALAR_1__Lpml5_MASK__VI 0x3f000000L -#define LPML_SCALAR_2__Lpml0_MASK__VI 0x0003f000L -#define LPML_SCALAR_2__Lpml6_MASK__VI 0x0000003fL -#define LPML_SCALAR_2__Lpml7_MASK__VI 0x00000fc0L -#define LPMV_SCALAR_1__Lpmv1_MASK__VI 0x0000003fL -#define LPMV_SCALAR_1__Lpmv2_MASK__VI 0x00000fc0L -#define LPMV_SCALAR_1__Lpmv3_MASK__VI 0x0003f000L -#define LPMV_SCALAR_1__Lpmv4_MASK__VI 0x00fc0000L -#define LPMV_SCALAR_1__Lpmv5_MASK__VI 0x3f000000L -#define LPMV_SCALAR_2__Lpmv0_MASK__VI 0x0003f000L -#define LPMV_SCALAR_2__Lpmv6_MASK__VI 0x0000003fL -#define LPMV_SCALAR_2__Lpmv7_MASK__VI 0x00000fc0L -#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK__VI 0x00000008L -#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK__VI 0x00000004L -#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK__VI 0x00000002L -#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK__VI 0x00000001L -#define MAILBOX_INDEX__MAILBOX_INDEX_MASK__VI 0x0000000fL -#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK__VI 0x00000002L -#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK__VI 0x00000001L -#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK__VI 0xffffffffL -#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK__VI 0x01000000L -#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK__VI 0x02000000L -#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK__VI 0x00400000L -#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK__VI 0x00800000L -#define MC_ARB_ATOMIC__OUTSTANDING_MASK__VI 0x0000ff00L -#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK__VI 0x00000080L -#define MC_ARB_ATOMIC__SDMA_GRP_MASK__VI 0x00000070L -#define MC_ARB_ATOMIC__TC_GRP_EN_MASK__VI 0x00000008L -#define MC_ARB_ATOMIC__TC_GRP_MASK__VI 0x00000007L -#define MC_ARB_BUSY_STATUS__WRRET0_MASK__VI 0x01000000L -#define MC_ARB_BUSY_STATUS__WRRET1_MASK__VI 0x02000000L -#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK__VI 0x00001000L -#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK__VI 0x00000400L -#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK__VI 0xffffe000L -#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK__VI 0x00000080L -#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK__VI 0x00000100L -#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK__VI 0x00000800L -#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK__VI 0x00000200L -#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK__VI 0x00020000L -#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK__VI 0x00010000L -#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK__VI 0x01000000L -#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK__VI 0x000000ffL -#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK__VI 0x0000ff00L -#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK__VI 0x00200000L -#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK__VI 0x00400000L -#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK__VI 0x00800000L -#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK__VI 0x00040000L -#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK__VI 0x00080000L -#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK__VI 0x00100000L -#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK__VI 0x0000c000L -#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK__VI 0x00030000L -#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK__VI 0x00000003L -#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK__VI 0x0000000cL -#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK__VI 0x00000030L -#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK__VI 0x000000c0L -#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK__VI 0x00000300L -#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK__VI 0x00000c00L -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK__VI 0x00300000L -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK__VI 0x00c00000L -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK__VI 0x000c0000L -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK__VI 0x03000000L -#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK__VI 0x0c000000L -#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK__VI 0x30000000L -#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK__VI 0x00003000L -#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK__VI 0xc0000000L -#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK__VI 0x000c0000L -#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK__VI 0x00300000L -#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK__VI 0x00000003L -#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK__VI 0x0000000cL -#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK__VI 0x00000030L -#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK__VI 0x000000c0L -#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK__VI 0x00000300L -#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK__VI 0x00000c00L -#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK__VI 0x00003000L -#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK__VI 0x00c00000L -#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK__VI 0x03000000L -#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK__VI 0x0c000000L -#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK__VI 0x00030000L -#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK__VI 0x30000000L -#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK__VI 0x0000c000L -#define MC_ARB_GRUB_PRIORITY1_WR__VCE_MASK__VI 0xc0000000L -#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK__VI 0x00003000L -#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK__VI 0x30000000L -#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK__VI 0xc0000000L -#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK__VI 0x03000000L -#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK__VI 0x00000c00L -#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK__VI 0x00000003L -#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK__VI 0x00c00000L -#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK__VI 0x0000000cL -#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK__VI 0x0000c000L -#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK__VI 0x000c0000L -#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK__VI 0x00300000L -#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK__VI 0x00030000L -#define MC_ARB_GRUB_PRIORITY2_RD__VCEU_MASK__VI 0x000000c0L -#define MC_ARB_GRUB_PRIORITY2_RD__VCE_MASK__VI 0x00000030L -#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK__VI 0x0c000000L -#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK__VI 0x00000300L -#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK__VI 0x00000c00L -#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK__VI 0x03000000L -#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK__VI 0x30000000L -#define MC_ARB_GRUB_PRIORITY2_WR__RSV3_MASK__VI 0xc0000000L -#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK__VI 0x0000000cL -#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK__VI 0x00000300L -#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK__VI 0x00c00000L -#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK__VI 0x00003000L -#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK__VI 0x00030000L -#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK__VI 0x000c0000L -#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK__VI 0x0000c000L -#define MC_ARB_GRUB_PRIORITY2_WR__VCEU_MASK__VI 0x00000003L -#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK__VI 0x0c000000L -#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK__VI 0x000000c0L -#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK__VI 0x00000030L -#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK__VI 0x00300000L -#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK__VI 0x00ff0000L -#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK__VI 0xff000000L -#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK__VI 0x000000ffL -#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK__VI 0x0000ff00L -#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK__VI 0x00000100L -#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK__VI 0x00000200L -#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK__VI 0x00000001L -#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK__VI 0x00000002L -#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK__VI 0x00000004L -#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK__VI 0x00000008L -#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK__VI 0x00000010L -#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK__VI 0x00000020L -#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK__VI 0x00000800L -#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK__VI 0x00001000L -#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK__VI 0x00000400L -#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK__VI 0x00002000L -#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK__VI 0x00800000L -#define MC_ARB_GRUB_REALTIME_RD__IA_MASK__VI 0x00000080L -#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK__VI 0x80000000L -#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK__VI 0x00004000L -#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK__VI 0x00008000L -#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK__VI 0x20000000L -#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK__VI 0x00400000L -#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK__VI 0x00020000L -#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK__VI 0x10000000L -#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK__VI 0x00040000L -#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK__VI 0x00000040L -#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK__VI 0x01000000L -#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK__VI 0x04000000L -#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK__VI 0x08000000L -#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK__VI 0x02000000L -#define MC_ARB_GRUB_REALTIME_RD__VCEU_MASK__VI 0x00100000L -#define MC_ARB_GRUB_REALTIME_RD__VCE_MASK__VI 0x00080000L -#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK__VI 0x00010000L -#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK__VI 0x40000000L -#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK__VI 0x00200000L -#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK__VI 0x00000200L -#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK__VI 0x00000400L -#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK__VI 0x00000001L -#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK__VI 0x00000002L -#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK__VI 0x00000004L -#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK__VI 0x00000008L -#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK__VI 0x00000010L -#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK__VI 0x00000020L -#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK__VI 0x00000040L -#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK__VI 0x00200000L -#define MC_ARB_GRUB_REALTIME_WR__IH_MASK__VI 0x10000000L -#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK__VI 0x40000000L -#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK__VI 0x00000800L -#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK__VI 0x00001000L -#define MC_ARB_GRUB_REALTIME_WR__RSV2_MASK__VI 0x80000000L -#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK__VI 0x00020000L -#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK__VI 0x00100000L -#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK__VI 0x00002000L -#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK__VI 0x08000000L -#define MC_ARB_GRUB_REALTIME_WR__SH_MASK__VI 0x00000100L -#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK__VI 0x00004000L -#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK__VI 0x00000080L -#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK__VI 0x00400000L -#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK__VI 0x01000000L -#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK__VI 0x02000000L -#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK__VI 0x00800000L -#define MC_ARB_GRUB_REALTIME_WR__VCEU_MASK__VI 0x00010000L -#define MC_ARB_GRUB_REALTIME_WR__VCE_MASK__VI 0x00008000L -#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK__VI 0x20000000L -#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK__VI 0x00080000L -#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK__VI 0x00040000L -#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK__VI 0x04000000L -#define MC_ARB_GRUB__GRUB_WATERMARK_MASK__VI 0x000000ffL -#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK__VI 0x00ff0000L -#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK__VI 0x0000ff00L -#define MC_ARB_GRUB__REG_RD_SEL_MASK__VI 0x04000000L -#define MC_ARB_GRUB__REG_WR_EN_MASK__VI 0x03000000L -#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK__VI 0x01000000L -#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK__VI 0x00000004L -#define MC_ARB_MISC3__CHAN4_EN_MASK__VI 0x00000002L -#define MC_ARB_MISC3__TBD_FIELD_MASK__VI 0xffffffe0L -#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK__VI 0x00000010L -#define MC_ARB_MISC3__UVD_URG_MODE_MASK__VI 0x00000008L -#define MC_ARB_PERF_CID__CH0_EN_MASK__VI 0x00010000L -#define MC_ARB_PERF_CID__CH0_MASK__VI 0x000000ffL -#define MC_ARB_PERF_CID__CH1_EN_MASK__VI 0x00020000L -#define MC_ARB_PERF_CID__CH1_MASK__VI 0x0000ff00L -#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK__VI 0x00010000L -#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK__VI 0x00020000L -#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK__VI 0x01000000L -#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK__VI 0x02000000L -#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK__VI 0x01000000L -#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK__VI 0x00000400L -#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK__VI 0x00008000L -#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK__VI 0x00004000L -#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK__VI 0x00000800L -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK__VI 0x00000100L -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK__VI 0x00000200L -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK__VI 0x00001000L -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK__VI 0x00002000L -#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK__VI 0x00ff0000L -#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK__VI 0x10000000L -#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK__VI 0x0001c000L -#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK__VI 0x00002000L -#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK__VI 0x00001000L -#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK__VI 0x00ff0000L -#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK__VI 0xff000000L -#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK__VI 0x00000800L -#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK__VI 0x00000700L -#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK__VI 0x00008000L -#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK__VI 0x00007000L -#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK__VI 0x00000008L -#define MC_ARB_SNOOP__TC_GRP_RD_MASK__VI 0x00000007L -#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK__VI 0x00000080L -#define MC_ARB_SNOOP__TC_GRP_WR_MASK__VI 0x00000070L -#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK__VI 0x00000040L -#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK__VI 0x00000080L -#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK__VI 0x00000800L -#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK__VI 0x00000180L -#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK__VI 0x00000200L -#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK__VI 0x000000ffL -#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK__SI__CI 0x00010000L -#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK__VI 0x01000000L -#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK__VI 0x02000000L -#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK__VI 0x00ff0000L -#define MC_CITF_DAGB_DLY__CLI_MASK__SI__CI 0x001f0000L -#define MC_CITF_DAGB_DLY__CLI_MASK__VI 0x003f0000L -#define MC_CITF_DAGB_DLY__POS_MASK__SI__CI 0x1f000000L -#define MC_CITF_DAGB_DLY__POS_MASK__VI 0x3f000000L -#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK__VI 0x00020000L -#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK__SI__CI 0x00000040L -#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK__VI 0x00000002L -#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK__SI__CI 0x00001000L -#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK__VI 0x00000080L -#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK__VI 0x00040000L -#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK__SI__CI 0x00000080L -#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK__VI 0x00000004L -#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK__SI__CI 0x00002000L -#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK__VI 0x00000100L -#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK__SI__CI 0x00004000L -#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK__VI 0x00000200L -#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK__VI 0x00004000L -#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK__SI__CI 0x00000100L -#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK__VI 0x00000008L -#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK__SI__CI 0x00010000L -#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK__VI 0x00000800L -#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK__VI 0x00008000L -#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK__SI__CI 0x00000400L -#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK__VI 0x00000020L -#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK__SI__CI 0x00020000L -#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK__VI 0x00001000L -#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK__VI 0x00010000L -#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK__SI__CI 0x00008000L -#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK__VI 0x00000400L -#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK__SI__CI 0x00040000L -#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK__VI 0x00002000L -#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK__SI__CI 0x00000200L -#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK__VI 0x00000010L -#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK__SI__CI 0x00000800L -#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK__VI 0x00000040L -#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK__VI 0x00000040L -#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK__VI 0x00007f80L -#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK__VI 0x00001000L -#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK__VI 0x00002000L -#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK__VI 0x00000040L -#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK__VI 0x00000080L -#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK__VI 0x00000800L -#define MC_CONFIG__MCDS_WR_ENABLE_MASK__VI 0x00000010L -#define MC_CONFIG__MCDT_WR_ENABLE_MASK__VI 0x00000020L -#define MC_CONFIG__MCDU_WR_ENABLE_MASK__VI 0x00000040L -#define MC_CONFIG__MCDV_WR_ENABLE_MASK__VI 0x00000080L -#define MC_CONFIG__MC_RD_ENABLE_MASK__SI__CI 0x00000030L -#define MC_CONFIG__MC_RD_ENABLE_MASK__VI 0x00000700L -#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK__VI 0x00010000L -#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK__VI 0x00008000L -#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK__VI 0x03fe0000L -#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK__VI 0xfc000000L -#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK__VI 0x000000ffL -#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK__VI 0x00007f00L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK__VI 0x00004000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK__VI 0x00000080L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK__VI 0x00000008L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK__VI 0x00000100L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK__VI 0x00000010L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK__VI 0x00000001L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK__VI 0x1f000000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK__VI 0x00000800L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK__VI 0x20000000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK__VI 0x00040000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK__VI 0x00200000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK__VI 0x00100000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK__VI 0x00800000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK__VI 0x00008000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK__VI 0x00030000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK__VI 0x00080000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK__VI 0x00400000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK__VI 0x00001000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK__VI 0x00000200L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK__VI 0x00000020L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK__VI 0x00000002L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK__VI 0x00002000L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK__VI 0x00000400L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK__VI 0x00000040L -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK__VI 0x00000004L -#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK__VI 0x00000030L -#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK__VI 0x0000000cL -#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK__VI 0x00000003L -#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK__VI 0x00000003L -#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK__VI 0x000000c0L -#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK__VI 0x0000000cL -#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK__VI 0x00000300L -#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK__VI 0x000c0000L -#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK__VI 0x0c000000L -#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK__VI 0x00030000L -#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK__VI 0x00300000L -#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK__VI 0x00c00000L -#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK__VI 0x03000000L -#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK__VI 0x00000030L -#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK__VI 0x00003000L -#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK__VI 0x0000c000L -#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK__VI 0xc0000000L -#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK__VI 0x30000000L -#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK__VI 0x00000c00L -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK__VI 0x00000200L -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK__VI 0x00000100L -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK__VI 0x0000000fL -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK__VI 0x000000f0L -#define MC_FUS_DRAM0_CS01_MASK__ADDRMASK21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM0_CS01_MASK__ADDRMASK38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM0_CS23_MASK__ADDRMASK21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM0_CS23_MASK__ADDRMASK38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM0_CTL_BASE__DCTADRMAPVAL_MASK__VI 0x20000000L -#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK__VI 0x0fffff80L -#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK__VI 0x00000078L -#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK__VI 0x10000000L -#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK__VI 0x00000007L -#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK__VI 0x001fffffL -#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK__VI 0x00200000L -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK__VI 0x00000200L -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK__VI 0x00000100L -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK__VI 0x0000000fL -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK__VI 0x000000f0L -#define MC_FUS_DRAM1_CS01_MASK__ADDRMASK21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM1_CS01_MASK__ADDRMASK38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM1_CS23_MASK__ADDRMASK21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM1_CS23_MASK__ADDRMASK38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK__VI 0x0000ffe0L -#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK__VI 0x7ff80000L -#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK__VI 0x00000001L -#define MC_FUS_DRAM1_CTL_BASE__DCTADRMAPVAL_MASK__VI 0x20000000L -#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK__VI 0x0fffff80L -#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK__VI 0x00000078L -#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK__VI 0x10000000L -#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK__VI 0x00000007L -#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK__VI 0x001fffffL -#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK__VI 0x00200000L -#define MC_FUS_DRAM_APER_BASE__BASE_MASK__VI 0x000fffffL -#define MC_FUS_DRAM_APER_DEF__DEF_MASK__VI 0x0fffffffL -#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK__VI 0x10000000L -#define MC_FUS_DRAM_APER_TOP__TOP_MASK__VI 0x000fffffL -#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK__VI 0x00000fffL -#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK__VI 0x00fff000L -#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK__VI 0x00000fffL -#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK__VI 0x00fff000L -#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK__VI 0x00000007L -#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK__VI 0x00007fc0L -#define MC_FUS_DRAM_MODE__DRAMTYPE_MASK__VI 0x00000038L -#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY_MASK__VI 0x00000010L -#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE_MASK__VI 0x00000008L -#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL_MASK__VI 0x0000c000L -#define MC_GRUB_FEATURES__ARB_STALL_EN_MASK__VI 0x00000400L -#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL_MASK__VI 0x00003000L -#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL_MASK__VI 0x000c0000L -#define MC_GRUB_FEATURES__CREDIT_STALL_EN_MASK__VI 0x00000800L -#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL_MASK__VI 0x00030000L -#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE_MASK__VI 0x00000004L -#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE_MASK__VI 0x00000020L -#define MC_GRUB_FEATURES__RT_BYPASS_OFF_MASK__VI 0x00000040L -#define MC_GRUB_FEATURES__SCLK_CG_DISABLE_MASK__VI 0x00000002L -#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE_MASK__VI 0x00000080L -#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE_MASK__VI 0x00000100L -#define MC_GRUB_FEATURES__WR_COMBINE_OFF_MASK__VI 0x00000001L -#define MC_GRUB_FEATURES__WR_REORDER_OFF_MASK__VI 0x00100000L -#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR_MASK__VI 0x20000000L -#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE_MASK__VI 0x10000000L -#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE_MASK__VI 0x0f000000L -#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK__VI 0x0000ff00L -#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_MASK__VI 0x000000ffL -#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR_MASK__VI 0x20000000L -#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE_MASK__VI 0x10000000L -#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE_MASK__VI 0x0f000000L -#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK__VI 0x0000ff00L -#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_MASK__VI 0x000000ffL -#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK__VI 0xffff0000L -#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI_MASK__VI 0x0000ffffL -#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO_MASK__VI 0xffffffffL -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK__VI 0x02000000L -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK__VI 0x01000000L -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK__VI 0x0000000fL -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK__VI 0x0000ff00L -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK__VI 0x04000000L -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK__VI 0x00ff0000L -#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY_MASK__VI 0x00001f00L -#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY_MASK__VI 0x001f0000L -#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY_MASK__VI 0x0000001fL -#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI_MASK__VI 0x00003f00L -#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO_MASK__VI 0x0000003fL -#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL_MASK__VI 0x00008000L -#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH_MASK__VI 0x00070000L -#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH_MASK__VI 0x00700000L -#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP_MASK__VI 0x00000100L -#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP_MASK__VI 0x00000003L -#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP_MASK__VI 0x00000200L -#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP_MASK__VI 0x0000000cL -#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP_MASK__VI 0x00000400L -#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP_MASK__VI 0x00000030L -#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP_MASK__VI 0x00000800L -#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP_MASK__VI 0x000000c0L -#define MC_GRUB_TCB_DATA_HI__DATA_MASK__VI 0xffffffffL -#define MC_GRUB_TCB_DATA_LO__DATA_MASK__VI 0xffffffffL -#define MC_GRUB_TCB_INDEX__INDEX_MASK__VI 0x0000007fL -#define MC_GRUB_TCB_INDEX__RD_EN_MASK__VI 0x00000400L -#define MC_GRUB_TCB_INDEX__TCB0_WR_EN_MASK__VI 0x00000100L -#define MC_GRUB_TCB_INDEX__TCB1_WR_EN_MASK__VI 0x00000200L -#define MC_GRUB_TCB_INDEX__TCB_SEL_MASK__VI 0x00000800L -#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE_MASK__VI 0x0000f000L -#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE_MASK__VI 0x000f0000L -#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT_MASK__VI 0x0000003fL -#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE_MASK__VI 0x00000f00L -#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH_MASK__VI 0x01f00000L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK__VI 0x00000800L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK__VI 0x00000010L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK__VI 0x00000001L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK__VI 0x00000080L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK__VI 0x00004000L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK__VI 0x00000100L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK__VI 0x00000002L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK__VI 0x00001000L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK__VI 0x00000004L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK__VI 0x00000008L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK__VI 0x00000040L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK__VI 0x00000020L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK__VI 0x00000400L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK__VI 0x00000200L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK__VI 0x00008000L -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK__VI 0x00002000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK__VI 0x00400000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK__VI 0x00800000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK__VI 0x10000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK__VI 0x20000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK__VI 0x01000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK__VI 0x02000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK__VI 0x00100000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK__VI 0x00200000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK__VI 0x40000000L -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK__VI 0x80000000L -#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK__VI 0x00040000L -#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK__SI__CI 0x00002000L -#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK__VI 0x00080000L -#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK__VI 0x00000004L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK__VI 0x00000080L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK__VI 0x00000100L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK__SI__CI 0x00000004L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK__VI 0x00000008L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK__SI__CI 0x00000008L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK__VI 0x00000010L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK__SI__CI 0x00000010L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK__VI 0x00000020L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK__SI__CI 0x00000020L -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK__VI 0x00000040L -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK__VI 0x00004000L -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK__SI__CI 0x00000100L -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK__VI 0x00001000L -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK__SI__CI 0x00000200L -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK__VI 0x00002000L -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK__VI 0x00000800L -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK__SI__CI 0x00000040L -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK__VI 0x00000200L -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK__SI__CI 0x00000080L -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK__VI 0x00000400L -#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK__SI__CI 0x00001000L -#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK__VI 0x00020000L -#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK__SI__CI 0x00000400L -#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK__VI 0x00008000L -#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK__SI__CI 0x00000800L -#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK__VI 0x000001feL -#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK__VI 0x0001fe00L -#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK__VI 0x01000000L -#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK__SI__CI 0x00000200L -#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK__VI 0x00002000L -#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK__SI__CI 0x0001fc00L -#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK__VI 0x001fc000L -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK__SI__CI 0x00020000L -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK__VI 0x00200000L -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK__SI__CI 0x00040000L -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK__VI 0x00400000L -#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK__VI 0x78000000L -#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK__VI 0x02000000L -#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK__VI 0x00000200L -#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK__VI 0x00000400L -#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK__VI 0x00000800L -#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK__VI 0x00001000L -#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK__SI__CI 0x00080000L -#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK__VI 0x00800000L -#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK__VI 0x04000000L -#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK__VI 0x000000ffL -#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK__SI__CI 0x000000ffL -#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK__VI 0x0000ff00L -#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK__VI 0x0000ff00L -#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK__VI 0x0000ff00L -#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK__VI 0x00020000L -#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK__VI 0x00040000L -#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK__VI 0x01f80000L -#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK__VI 0x00020000L -#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK__VI 0x00040000L -#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK__VI 0x01f80000L -#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK__VI 0x00020000L -#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK__VI 0x00040000L -#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK__VI 0x01f80000L -#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK__VI 0x0003f800L -#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_RDREQ_MCDS__BUS_MASK__VI 0x00000004L -#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK__VI 0x01fc0000L -#define MC_HUB_RDREQ_MCDS__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK__VI 0x0003f800L -#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_RDREQ_MCDT__BUS_MASK__VI 0x00000004L -#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK__VI 0x01fc0000L -#define MC_HUB_RDREQ_MCDT__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK__VI 0x0003f800L -#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_RDREQ_MCDU__BUS_MASK__VI 0x00000004L -#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK__VI 0x01fc0000L -#define MC_HUB_RDREQ_MCDU__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK__VI 0x0003f800L -#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_RDREQ_MCDV__BUS_MASK__VI 0x00000004L -#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK__VI 0x01fc0000L -#define MC_HUB_RDREQ_MCDV__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK__VI 0xfe000000L -#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK__VI 0x00000080L -#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK__SI__CI 0x00000080L -#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK__VI 0x00000800L -#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK__SI__CI 0x00000040L -#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK__VI 0x00000400L -#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK__SI__CI 0x00000020L -#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK__VI 0x00000200L -#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK__SI__CI 0x00000400L -#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK__VI 0x00004000L -#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK__SI__CI 0x00000200L -#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK__VI 0x00002000L -#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK__SI__CI 0x00000100L -#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK__VI 0x00001000L -#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK__VI 0x00000020L -#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK__VI 0x00000080L -#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK__VI 0x00000100L -#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK__SI__CI 0x00000800L -#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00020000L -#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00020000L -#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00020000L -#define MC_HUB_RDREQ_VCE0__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00020000L -#define MC_HUB_RDREQ_VCE1__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_RDREQ_VP8__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_RDREQ_VP8__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_RDREQ_VP8__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK__SI__CI 0x001f0000L -#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK__VI 0x003f0000L -#define MC_HUB_WDP_BP2__RDRET_MASK__VI 0x0000ffffL -#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK__VI 0x000001feL -#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK__VI 0x0001fe00L -#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK__VI 0x00fe0000L -#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK__VI 0x7f000000L -#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK__VI 0x000001feL -#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK__VI 0x0001fe00L -#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK__VI 0x00fe0000L -#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK__VI 0x7f000000L -#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK__VI 0x00800000L -#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK__VI 0x00200000L -#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK__VI 0x00400000L -#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK__VI 0x000000ffL -#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK__VI 0x0000ff00L -#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK__VI 0x0000007fL -#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK__VI 0x00003f80L -#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK__VI 0x01fe0000L -#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK__VI 0x01fe0000L -#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK__VI 0x00020000L -#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK__VI 0x00040000L -#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK__VI 0x01f80000L -#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK__VI 0x00020000L -#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK__VI 0x00040000L -#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK__VI 0x01f80000L -#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK__VI 0x00020000L -#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK__VI 0x00040000L -#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK__VI 0x01f80000L -#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK__VI 0x00020000L -#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK__VI 0x00040000L -#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK__VI 0x01f80000L -#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK__VI 0x00001f80L -#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK__VI 0x7f000000L -#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_WDP_MCDS__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK__VI 0x0001e000L -#define MC_HUB_WDP_MCDS__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_WDP_MCDS__STALL_MODE_MASK__VI 0x00000004L -#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK__VI 0x00fe0000L -#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK__VI 0x00001f80L -#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK__VI 0x7f000000L -#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_WDP_MCDT__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK__VI 0x0001e000L -#define MC_HUB_WDP_MCDT__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_WDP_MCDT__STALL_MODE_MASK__VI 0x00000004L -#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK__VI 0x00fe0000L -#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK__VI 0x00001f80L -#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK__VI 0x7f000000L -#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_WDP_MCDU__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK__VI 0x0001e000L -#define MC_HUB_WDP_MCDU__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_WDP_MCDU__STALL_MODE_MASK__VI 0x00000004L -#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK__VI 0x00fe0000L -#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK__VI 0x00001f80L -#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK__VI 0x7f000000L -#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK__VI 0x00000002L -#define MC_HUB_WDP_MCDV__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK__VI 0x0001e000L -#define MC_HUB_WDP_MCDV__MAXBURST_MASK__VI 0x00000078L -#define MC_HUB_WDP_MCDV__STALL_MODE_MASK__VI 0x00000004L -#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK__VI 0x00fe0000L -#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SAMMSP__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK__SI__CI 0x00000080L -#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK__VI 0x00080000L -#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK__SI__CI 0x00000040L -#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK__VI 0x00040000L -#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK__SI__CI 0x00000020L -#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK__VI 0x00020000L -#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK__SI__CI 0x00000400L -#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK__VI 0x00400000L -#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK__SI__CI 0x00000200L -#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK__VI 0x00200000L -#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK__SI__CI 0x00000100L -#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK__VI 0x00100000L -#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK__VI 0x00000020L -#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK__VI 0x00002000L -#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK__VI 0x00000040L -#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK__VI 0x00004000L -#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK__VI 0x00000080L -#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK__VI 0x00008000L -#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK__VI 0x00000100L -#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK__VI 0x00010000L -#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK__VI 0x00000200L -#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK__VI 0x00000400L -#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK__VI 0x00000800L -#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK__VI 0x00001000L -#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00020000L -#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00020000L -#define MC_HUB_WDP_VCE0__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_VCE0__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_VCE0__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_VCE0__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK__VI 0x00010000L -#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00020000L -#define MC_HUB_WDP_VCE1__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_VCE1__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_VCE1__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_VCE1__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK__VI 0x00010000L -#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_VCEU0__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_VCEU0__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_VCEU0__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_VCEU1__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_VCEU1__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_VCEU1__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK__VI 0x00000008L -#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WDP_VP8__ENABLE_MASK__VI 0x00000001L -#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK__VI 0x00007800L -#define MC_HUB_WDP_VP8__MAXBURST_MASK__VI 0x00000780L -#define MC_HUB_WDP_VP8__PRESCALE_MASK__VI 0x00000006L -#define MC_HUB_WDP_VP8__STALL_MODE_MASK__VI 0x00000030L -#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK__VI 0x00000040L -#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK__VI 0x00008000L -#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK__VI 0x00010000L -#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK__VI 0x000000feL -#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK__VI 0x00000001L -#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK__VI 0x000000feL -#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK__VI 0x00000001L -#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK__VI 0x000000feL -#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK__VI 0x00000001L -#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK__VI 0x000000feL -#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK__VI 0x00000001L -#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK__VI 0x00000010L -#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK__VI 0x00000020L -#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK__VI 0x00000040L -#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK__VI 0x00000080L -#define MC_RD_GRP_GFX__ISP_MASK__VI 0x00f00000L -#define MC_RD_GRP_GFX__VP8_MASK__VI 0x0f000000L -#define MC_RD_GRP_GFX__XDMAM_MASK__VI 0xf0000000L -#define MC_RD_GRP_OTH__SAMMSP_MASK__VI 0xf0000000L -#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK__VI 0x00000040L -#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK__VI 0x00000006L -#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK__VI 0x00000020L -#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK__VI 0x00000010L -#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK__VI 0x00000001L -#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK__VI 0x00000008L -#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK__VI 0x00000001L -#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK__VI 0xff000000L -#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK__VI 0x00ff0000L -#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK__VI 0x00000006L -#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK__VI 0x0000ff00L -#define MC_RPB_TCI_CNTL__TCI_VMID_MASK__VI 0x000000f0L -#define MC_RPB_TCI_CNTL__TCI_VOL_MASK__VI 0x00000008L -#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK__VI 0x0000000fL -#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK__VI 0x80000000L -#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK__VI 0x00000ff0L -#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK__VI 0x00000008L -#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK__VI 0x00001000L -#define MC_SHARED_CHMAP__CHAN3_MASK__VI 0x000f0000L -#define MC_SHARED_CHMAP__CHAN4_MASK__VI 0x00f00000L -#define MC_SHARED_CHREMAP2__CHAN10_MASK__VI 0x00000f00L -#define MC_SHARED_CHREMAP2__CHAN11_MASK__VI 0x0000f000L -#define MC_SHARED_CHREMAP2__CHAN12_MASK__VI 0x000f0000L -#define MC_SHARED_CHREMAP2__CHAN13_MASK__VI 0x00f00000L -#define MC_SHARED_CHREMAP2__CHAN14_MASK__VI 0x0f000000L -#define MC_SHARED_CHREMAP2__CHAN15_MASK__VI 0xf0000000L -#define MC_SHARED_CHREMAP2__CHAN8_MASK__VI 0x0000000fL -#define MC_SHARED_CHREMAP2__CHAN9_MASK__VI 0x000000f0L -#define MC_SHARED_CHREMAP__CHAN0_MASK__SI__CI 0x00000007L -#define MC_SHARED_CHREMAP__CHAN0_MASK__VI 0x0000000fL -#define MC_SHARED_CHREMAP__CHAN1_MASK__SI__CI 0x00000038L -#define MC_SHARED_CHREMAP__CHAN1_MASK__VI 0x000000f0L -#define MC_SHARED_CHREMAP__CHAN2_MASK__SI__CI 0x000001c0L -#define MC_SHARED_CHREMAP__CHAN2_MASK__VI 0x00000f00L -#define MC_SHARED_CHREMAP__CHAN3_MASK__SI__CI 0x00000e00L -#define MC_SHARED_CHREMAP__CHAN3_MASK__VI 0x0000f000L -#define MC_SHARED_CHREMAP__CHAN4_MASK__SI__CI 0x00007000L -#define MC_SHARED_CHREMAP__CHAN4_MASK__VI 0x000f0000L -#define MC_SHARED_CHREMAP__CHAN5_MASK__SI__CI 0x00038000L -#define MC_SHARED_CHREMAP__CHAN5_MASK__VI 0x00f00000L -#define MC_SHARED_CHREMAP__CHAN6_MASK__SI__CI 0x001c0000L -#define MC_SHARED_CHREMAP__CHAN6_MASK__VI 0x0f000000L -#define MC_SHARED_CHREMAP__CHAN7_MASK__SI__CI 0x00e00000L -#define MC_SHARED_CHREMAP__CHAN7_MASK__VI 0xf0000000L -#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK__VI 0x00000001L -#define MC_SHARED_VIRT_RESET_REQ__PF_MASK__VI 0x80000000L -#define MC_SHARED_VIRT_RESET_REQ__VF_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK__VI 0xffff0000L -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK__VI 0x0000ffffL -#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK__VI 0x00007000L -#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK__VI 0x00000e00L -#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK__VI 0x00000001L -#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK__VI 0x00078000L -#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK__VI 0x00080000L -#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK__VI 0x00000100L -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK__VI 0x00000001L -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK__VI 0xff800000L -#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK__VI 0xffffffffL -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK__VI 0xffffffffL -#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK__VI 0x00000008L -#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK__VI 0x00800000L -#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK__VI 0x80000000L -#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK__VI 0x3fffffffL -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK__VI 0xff800000L -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK__VI 0x000000ffL -#define MC_WR_GRP_GFX__ISP_MASK__VI 0x000f0000L -#define MC_WR_GRP_GFX__VP8_MASK__VI 0x00f00000L -#define MC_WR_GRP_GFX__XDMAM_MASK__VI 0xf0000000L -#define MC_WR_GRP_GFX__XDMA_MASK__VI 0x0f000000L -#define MC_WR_GRP_SYS__SAMMSP_MASK__VI 0x0000f000L -#define MC_XBAR_ARB__ACP_RDRET_URG_MASK__VI 0x00000008L -#define MC_XBAR_ARB__HDP_RDRET_URG_MASK__VI 0x00000010L -#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK__VI 0x10000000L -#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK__VI 0x03000000L -#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK__VI 0x00000fffL -#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK__VI 0x0c000000L -#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK__VI 0x00fff000L -#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK__VI 0x0000ff00L -#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK__VI 0x00ff0000L -#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK__VI 0x000000ffL -#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK__VI 0x000000ffL -#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK__VI 0x0000ff00L -#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK__VI 0x00ff0000L -#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK__VI 0xff000000L -#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK__VI 0x000000ffL -#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK__VI 0x0000ff00L -#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK__VI 0x00ff0000L -#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK__VI 0xff000000L -#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK__VI 0xffffffffL -#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK__VI 0xffffffffL -#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK__VI 0xffffffffL -#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK__VI 0xffffffffL -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_13_MASK__VI 0x00002000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_15_MASK__VI 0x00008000L -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_9_MASK__VI 0x00000200L -#define MP_FPS_CNT__FPS_CNT_MASK__VI 0x000000ffL -#define MSI_MASK_64__MSI_MASK_64_MASK__VI 0xffffffffL -#define MSI_MASK__MSI_MASK_MASK__VI 0xffffffffL -#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK__VI 0x00000100L -#define MSI_PENDING_64__MSI_PENDING_64_MASK__VI 0xffffffffL -#define MSI_PENDING__MSI_PENDING_MASK__VI 0xffffffffL -#define ORB_IF_config__wait_for_xfer_done_MASK__VI 0x00000001L -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK__VI 0x04000000L -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK__VI 0x00000001L -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK__VI 0x00000002L -#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK__VI 0x00000010L -#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK__VI 0x00000020L -#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK__VI 0x00000040L -#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK__VI 0x00000080L -#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING_MASK__VI 0x00000008L -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK__VI 0x00000001L -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK__VI 0x00000006L -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK__VI 0x00000003L -#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK__VI 0x00000004L -#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK__VI 0x00000008L -#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK__VI 0x00000010L -#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK__VI 0x00000020L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK__VI 0x00000008L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK__VI 0x00000010L -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK__VI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK__VI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK__VI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK__VI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK__VI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK__VI 0x30000000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK__VI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK__VI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK__VI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK__VI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK__VI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK__VI 0x30000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK__VI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK__VI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK__VI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK__VI 0x30000000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK__VI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK__VI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK__VI 0x00000004L -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK__VI 0x00000002L -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK__VI 0x00000001L -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK__VI 0x00030000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK__VI 0x00300000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK__VI 0x03000000L -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK__VI 0x30000000L -#define PB0_HW_DEBUG__HW_00_DEBUG_MASK__VI 0x00000001L -#define PB0_HW_DEBUG__HW_01_DEBUG_MASK__VI 0x00000002L -#define PB0_HW_DEBUG__HW_02_DEBUG_MASK__VI 0x00000004L -#define PB0_HW_DEBUG__HW_03_DEBUG_MASK__VI 0x00000008L -#define PB0_HW_DEBUG__HW_04_DEBUG_MASK__VI 0x00000010L -#define PB0_HW_DEBUG__HW_05_DEBUG_MASK__VI 0x00000020L -#define PB0_HW_DEBUG__HW_06_DEBUG_MASK__VI 0x00000040L -#define PB0_HW_DEBUG__HW_07_DEBUG_MASK__VI 0x00000080L -#define PB0_HW_DEBUG__HW_08_DEBUG_MASK__VI 0x00000100L -#define PB0_HW_DEBUG__HW_09_DEBUG_MASK__VI 0x00000200L -#define PB0_HW_DEBUG__HW_10_DEBUG_MASK__VI 0x00000400L -#define PB0_HW_DEBUG__HW_11_DEBUG_MASK__VI 0x00000800L -#define PB0_HW_DEBUG__HW_12_DEBUG_MASK__VI 0x00001000L -#define PB0_HW_DEBUG__HW_13_DEBUG_MASK__VI 0x00002000L -#define PB0_HW_DEBUG__HW_14_DEBUG_MASK__VI 0x00004000L -#define PB0_HW_DEBUG__HW_15_DEBUG_MASK__VI 0x00008000L -#define PB0_HW_DEBUG__HW_16_DEBUG_MASK__VI 0x00010000L -#define PB0_HW_DEBUG__HW_17_DEBUG_MASK__VI 0x00020000L -#define PB0_HW_DEBUG__HW_18_DEBUG_MASK__VI 0x00040000L -#define PB0_HW_DEBUG__HW_19_DEBUG_MASK__VI 0x00080000L -#define PB0_HW_DEBUG__HW_20_DEBUG_MASK__VI 0x00100000L -#define PB0_HW_DEBUG__HW_21_DEBUG_MASK__VI 0x00200000L -#define PB0_HW_DEBUG__HW_22_DEBUG_MASK__VI 0x00400000L -#define PB0_HW_DEBUG__HW_23_DEBUG_MASK__VI 0x00800000L -#define PB0_HW_DEBUG__HW_24_DEBUG_MASK__VI 0x01000000L -#define PB0_HW_DEBUG__HW_25_DEBUG_MASK__VI 0x02000000L -#define PB0_HW_DEBUG__HW_26_DEBUG_MASK__VI 0x04000000L -#define PB0_HW_DEBUG__HW_27_DEBUG_MASK__VI 0x08000000L -#define PB0_HW_DEBUG__HW_28_DEBUG_MASK__VI 0x10000000L -#define PB0_HW_DEBUG__HW_29_DEBUG_MASK__VI 0x20000000L -#define PB0_HW_DEBUG__HW_30_DEBUG_MASK__VI 0x40000000L -#define PB0_HW_DEBUG__HW_31_DEBUG_MASK__VI 0x80000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK__VI 0x00010000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_10_MASK__VI 0x04000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_11_MASK__VI 0x08000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_12_MASK__VI 0x10000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_13_MASK__VI 0x20000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_14_MASK__VI 0x40000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_15_MASK__VI 0x80000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK__VI 0x00020000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK__VI 0x00040000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK__VI 0x00080000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK__VI 0x00100000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK__VI 0x00200000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK__VI 0x00400000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK__VI 0x00800000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_8_MASK__VI 0x01000000L -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_9_MASK__VI 0x02000000L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK__VI 0x00000001L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_10_MASK__VI 0x00000400L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_11_MASK__VI 0x00000800L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_12_MASK__VI 0x00001000L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_13_MASK__VI 0x00002000L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_14_MASK__VI 0x00004000L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_15_MASK__VI 0x00008000L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK__VI 0x00000002L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK__VI 0x00000004L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK__VI 0x00000008L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK__VI 0x00000010L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK__VI 0x00000020L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK__VI 0x00000040L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK__VI 0x00000080L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_8_MASK__VI 0x00000100L -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_9_MASK__VI 0x00000200L -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK__VI 0x00000003L -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK__VI 0x00000060L -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK__VI 0x00000010L -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK__VI 0x0000000cL -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK__VI 0x00010000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_10_MASK__VI 0x04000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_11_MASK__VI 0x08000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_12_MASK__VI 0x10000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_13_MASK__VI 0x20000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_14_MASK__VI 0x40000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_15_MASK__VI 0x80000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK__VI 0x00020000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK__VI 0x00040000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK__VI 0x00080000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK__VI 0x00100000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK__VI 0x00200000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK__VI 0x00400000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK__VI 0x00800000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_8_MASK__VI 0x01000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_9_MASK__VI 0x02000000L -#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK__VI 0x00000040L -#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK__VI 0x00000002L -#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK__VI 0x00000180L -#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK__VI 0x00000004L -#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK__VI 0x00000200L -#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK__VI 0x00000038L -#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK__VI 0x00000001L -#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK__VI 0x00000002L -#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD_MASK__VI 0x00000010L -#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK__VI 0x00000004L -#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK__VI 0x00000008L -#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK__VI 0x00000001L -#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK__VI 0x00100000L -#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK__VI 0x00000020L -#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK__VI 0x00000040L -#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK__VI 0x00000080L -#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK__VI 0x00000001L -#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK__VI 0x00000002L -#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK__VI 0x00000004L -#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK__VI 0x00000008L -#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK__VI 0x00000010L -#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK__VI 0x00000400L -#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK__VI 0x00000800L -#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK__VI 0x00000100L -#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK__VI 0x00000200L -#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK__VI 0x00020000L -#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK__VI 0x00010000L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK__VI 0x00010000L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK__VI 0x00000001L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_10_MASK__VI 0x00000400L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_11_MASK__VI 0x00000800L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_12_MASK__VI 0x00001000L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_13_MASK__VI 0x00002000L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_14_MASK__VI 0x00004000L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_15_MASK__VI 0x00008000L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK__VI 0x00000002L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK__VI 0x00000004L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK__VI 0x00000008L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK__VI 0x00000010L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK__VI 0x00000020L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK__VI 0x00000040L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK__VI 0x00000080L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_8_MASK__VI 0x00000100L -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_9_MASK__VI 0x00000200L -#define PB0_PIF_HW_DEBUG__HW_00_DEBUG_MASK__VI 0x00000001L -#define PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK__VI 0x00000002L -#define PB0_PIF_HW_DEBUG__HW_02_DEBUG_MASK__VI 0x00000004L -#define PB0_PIF_HW_DEBUG__HW_03_DEBUG_MASK__VI 0x00000008L -#define PB0_PIF_HW_DEBUG__HW_04_DEBUG_MASK__VI 0x00000010L -#define PB0_PIF_HW_DEBUG__HW_05_DEBUG_MASK__VI 0x00000020L -#define PB0_PIF_HW_DEBUG__HW_06_DEBUG_MASK__VI 0x00000040L -#define PB0_PIF_HW_DEBUG__HW_07_DEBUG_MASK__VI 0x00000080L -#define PB0_PIF_HW_DEBUG__HW_08_DEBUG_MASK__VI 0x00000100L -#define PB0_PIF_HW_DEBUG__HW_09_DEBUG_MASK__VI 0x00000200L -#define PB0_PIF_HW_DEBUG__HW_10_DEBUG_MASK__VI 0x00000400L -#define PB0_PIF_HW_DEBUG__HW_11_DEBUG_MASK__VI 0x00000800L -#define PB0_PIF_HW_DEBUG__HW_12_DEBUG_MASK__VI 0x00001000L -#define PB0_PIF_HW_DEBUG__HW_13_DEBUG_MASK__VI 0x00002000L -#define PB0_PIF_HW_DEBUG__HW_14_DEBUG_MASK__VI 0x00004000L -#define PB0_PIF_HW_DEBUG__HW_15_DEBUG_MASK__VI 0x00008000L -#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK__VI 0x03000000L -#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK__VI 0xfc000000L -#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK__VI 0x00040000L -#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK__VI 0x00080000L -#define PB0_PIF_LANE0_OVRD2__FREQDIV_0_MASK__VI 0x00000018L -#define PB0_PIF_LANE0_OVRD2__GANGMODE_0_MASK__VI 0x00000007L -#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0_MASK__VI 0x00000060L -#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK__VI 0x00100000L -#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK__VI 0x00400000L -#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK__VI 0x00800000L -#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK__VI 0x00200000L -#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK__VI 0x00030000L -#define PB0_PIF_LANE0_OVRD2__RXPWR_0_MASK__VI 0x0000e000L -#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK__VI 0x00000080L -#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK__VI 0x00001800L -#define PB0_PIF_LANE0_OVRD2__TXPWR_0_MASK__VI 0x00000700L -#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK__VI 0x00010000L -#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK__VI 0x00020000L -#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK__VI 0x00004000L -#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK__VI 0x00008000L -#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK__VI 0x00000100L -#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK__VI 0x00000200L -#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK__VI 0x00000002L -#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK__VI 0x00000001L -#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK__VI 0x00000004L -#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK__VI 0x00000400L -#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK__VI 0x00001000L -#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK__VI 0x00002000L -#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK__VI 0x00000800L -#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK__VI 0x00000080L -#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK__VI 0x00000040L -#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK__VI 0x00000008L -#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK__VI 0x00000020L -#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK__VI 0x00000010L -#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK__VI 0x03000000L -#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK__VI 0xfc000000L -#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK__VI 0x00040000L -#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK__VI 0x00080000L -#define PB0_PIF_LANE1_OVRD2__FREQDIV_1_MASK__VI 0x00000018L -#define PB0_PIF_LANE1_OVRD2__GANGMODE_1_MASK__VI 0x00000007L -#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1_MASK__VI 0x00000060L -#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK__VI 0x00100000L -#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK__VI 0x00400000L -#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK__VI 0x00800000L -#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK__VI 0x00200000L -#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK__VI 0x00030000L -#define PB0_PIF_LANE1_OVRD2__RXPWR_1_MASK__VI 0x0000e000L -#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK__VI 0x00000080L -#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK__VI 0x00001800L -#define PB0_PIF_LANE1_OVRD2__TXPWR_1_MASK__VI 0x00000700L -#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK__VI 0x00010000L -#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK__VI 0x00020000L -#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK__VI 0x00004000L -#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK__VI 0x00008000L -#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK__VI 0x00000100L -#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK__VI 0x00000200L -#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK__VI 0x00000002L -#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK__VI 0x00000001L -#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK__VI 0x00000004L -#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK__VI 0x00000400L -#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK__VI 0x00001000L -#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK__VI 0x00002000L -#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK__VI 0x00000800L -#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK__VI 0x00000080L -#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK__VI 0x00000040L -#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK__VI 0x00000008L -#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK__VI 0x00000020L -#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK__VI 0x00000010L -#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK__VI 0x03000000L -#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK__VI 0xfc000000L -#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK__VI 0x00040000L -#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK__VI 0x00080000L -#define PB0_PIF_LANE2_OVRD2__FREQDIV_2_MASK__VI 0x00000018L -#define PB0_PIF_LANE2_OVRD2__GANGMODE_2_MASK__VI 0x00000007L -#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2_MASK__VI 0x00000060L -#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK__VI 0x00100000L -#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK__VI 0x00400000L -#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK__VI 0x00800000L -#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK__VI 0x00200000L -#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK__VI 0x00030000L -#define PB0_PIF_LANE2_OVRD2__RXPWR_2_MASK__VI 0x0000e000L -#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK__VI 0x00000080L -#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK__VI 0x00001800L -#define PB0_PIF_LANE2_OVRD2__TXPWR_2_MASK__VI 0x00000700L -#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK__VI 0x00010000L -#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK__VI 0x00020000L -#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK__VI 0x00004000L -#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK__VI 0x00008000L -#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK__VI 0x00000100L -#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK__VI 0x00000200L -#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK__VI 0x00000002L -#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK__VI 0x00000001L -#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK__VI 0x00000004L -#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK__VI 0x00000400L -#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK__VI 0x00001000L -#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK__VI 0x00002000L -#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK__VI 0x00000800L -#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK__VI 0x00000080L -#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK__VI 0x00000040L -#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK__VI 0x00000008L -#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK__VI 0x00000020L -#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK__VI 0x00000010L -#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK__VI 0x03000000L -#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK__VI 0xfc000000L -#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK__VI 0x00040000L -#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK__VI 0x00080000L -#define PB0_PIF_LANE3_OVRD2__FREQDIV_3_MASK__VI 0x00000018L -#define PB0_PIF_LANE3_OVRD2__GANGMODE_3_MASK__VI 0x00000007L -#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3_MASK__VI 0x00000060L -#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK__VI 0x00100000L -#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK__VI 0x00400000L -#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK__VI 0x00800000L -#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK__VI 0x00200000L -#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK__VI 0x00030000L -#define PB0_PIF_LANE3_OVRD2__RXPWR_3_MASK__VI 0x0000e000L -#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK__VI 0x00000080L -#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK__VI 0x00001800L -#define PB0_PIF_LANE3_OVRD2__TXPWR_3_MASK__VI 0x00000700L -#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK__VI 0x00010000L -#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK__VI 0x00020000L -#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK__VI 0x00004000L -#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK__VI 0x00008000L -#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK__VI 0x00000100L -#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK__VI 0x00000200L -#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK__VI 0x00000002L -#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK__VI 0x00000001L -#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK__VI 0x00000004L -#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK__VI 0x00000400L -#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK__VI 0x00001000L -#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK__VI 0x00002000L -#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK__VI 0x00000800L -#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK__VI 0x00000080L -#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK__VI 0x00000040L -#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK__VI 0x00000008L -#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK__VI 0x00000020L -#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK__VI 0x00000010L -#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK__VI 0x03000000L -#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK__VI 0xfc000000L -#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK__VI 0x00040000L -#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK__VI 0x00080000L -#define PB0_PIF_LANE4_OVRD2__FREQDIV_4_MASK__VI 0x00000018L -#define PB0_PIF_LANE4_OVRD2__GANGMODE_4_MASK__VI 0x00000007L -#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4_MASK__VI 0x00000060L -#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK__VI 0x00100000L -#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK__VI 0x00400000L -#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK__VI 0x00800000L -#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK__VI 0x00200000L -#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK__VI 0x00030000L -#define PB0_PIF_LANE4_OVRD2__RXPWR_4_MASK__VI 0x0000e000L -#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK__VI 0x00000080L -#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK__VI 0x00001800L -#define PB0_PIF_LANE4_OVRD2__TXPWR_4_MASK__VI 0x00000700L -#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK__VI 0x00010000L -#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK__VI 0x00020000L -#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK__VI 0x00004000L -#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK__VI 0x00008000L -#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK__VI 0x00000100L -#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK__VI 0x00000200L -#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK__VI 0x00000002L -#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK__VI 0x00000001L -#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK__VI 0x00000004L -#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK__VI 0x00000400L -#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK__VI 0x00001000L -#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK__VI 0x00002000L -#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK__VI 0x00000800L -#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK__VI 0x00000080L -#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK__VI 0x00000040L -#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK__VI 0x00000008L -#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK__VI 0x00000020L -#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK__VI 0x00000010L -#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK__VI 0x03000000L -#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK__VI 0xfc000000L -#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK__VI 0x00040000L -#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK__VI 0x00080000L -#define PB0_PIF_LANE5_OVRD2__FREQDIV_5_MASK__VI 0x00000018L -#define PB0_PIF_LANE5_OVRD2__GANGMODE_5_MASK__VI 0x00000007L -#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5_MASK__VI 0x00000060L -#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK__VI 0x00100000L -#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK__VI 0x00400000L -#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK__VI 0x00800000L -#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK__VI 0x00200000L -#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK__VI 0x00030000L -#define PB0_PIF_LANE5_OVRD2__RXPWR_5_MASK__VI 0x0000e000L -#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK__VI 0x00000080L -#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK__VI 0x00001800L -#define PB0_PIF_LANE5_OVRD2__TXPWR_5_MASK__VI 0x00000700L -#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK__VI 0x00010000L -#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK__VI 0x00020000L -#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK__VI 0x00004000L -#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK__VI 0x00008000L -#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK__VI 0x00000100L -#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK__VI 0x00000200L -#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK__VI 0x00000002L -#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK__VI 0x00000001L -#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK__VI 0x00000004L -#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK__VI 0x00000400L -#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK__VI 0x00001000L -#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK__VI 0x00002000L -#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK__VI 0x00000800L -#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK__VI 0x00000080L -#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK__VI 0x00000040L -#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK__VI 0x00000008L -#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK__VI 0x00000020L -#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK__VI 0x00000010L -#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK__VI 0x03000000L -#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK__VI 0xfc000000L -#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK__VI 0x00040000L -#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK__VI 0x00080000L -#define PB0_PIF_LANE6_OVRD2__FREQDIV_6_MASK__VI 0x00000018L -#define PB0_PIF_LANE6_OVRD2__GANGMODE_6_MASK__VI 0x00000007L -#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6_MASK__VI 0x00000060L -#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK__VI 0x00100000L -#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK__VI 0x00400000L -#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK__VI 0x00800000L -#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK__VI 0x00200000L -#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK__VI 0x00030000L -#define PB0_PIF_LANE6_OVRD2__RXPWR_6_MASK__VI 0x0000e000L -#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK__VI 0x00000080L -#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK__VI 0x00001800L -#define PB0_PIF_LANE6_OVRD2__TXPWR_6_MASK__VI 0x00000700L -#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK__VI 0x00010000L -#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK__VI 0x00020000L -#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK__VI 0x00004000L -#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK__VI 0x00008000L -#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK__VI 0x00000100L -#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK__VI 0x00000200L -#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK__VI 0x00000002L -#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK__VI 0x00000001L -#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK__VI 0x00000004L -#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK__VI 0x00000400L -#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK__VI 0x00001000L -#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK__VI 0x00002000L -#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK__VI 0x00000800L -#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK__VI 0x00000080L -#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK__VI 0x00000040L -#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK__VI 0x00000008L -#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK__VI 0x00000020L -#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK__VI 0x00000010L -#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK__VI 0x03000000L -#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK__VI 0xfc000000L -#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK__VI 0x00040000L -#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK__VI 0x00080000L -#define PB0_PIF_LANE7_OVRD2__FREQDIV_7_MASK__VI 0x00000018L -#define PB0_PIF_LANE7_OVRD2__GANGMODE_7_MASK__VI 0x00000007L -#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7_MASK__VI 0x00000060L -#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK__VI 0x00100000L -#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK__VI 0x00400000L -#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK__VI 0x00800000L -#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK__VI 0x00200000L -#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK__VI 0x00030000L -#define PB0_PIF_LANE7_OVRD2__RXPWR_7_MASK__VI 0x0000e000L -#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK__VI 0x00000080L -#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK__VI 0x00001800L -#define PB0_PIF_LANE7_OVRD2__TXPWR_7_MASK__VI 0x00000700L -#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK__VI 0x00010000L -#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK__VI 0x00020000L -#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK__VI 0x00004000L -#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK__VI 0x00008000L -#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK__VI 0x00000100L -#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK__VI 0x00000200L -#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK__VI 0x00000002L -#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK__VI 0x00000001L -#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK__VI 0x00000004L -#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK__VI 0x00000400L -#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK__VI 0x00001000L -#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK__VI 0x00002000L -#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK__VI 0x00000800L -#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK__VI 0x00000080L -#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK__VI 0x00000040L -#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK__VI 0x00000008L -#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK__VI 0x00000020L -#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK__VI 0x00000010L -#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK__VI 0x01000000L -#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK__VI 0x00060000L -#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK__VI 0x00e00000L -#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK__VI 0x00180000L -#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK__VI 0x00010000L -#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK__VI 0x000001c0L -#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK__VI 0x06000000L -#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK__VI 0x08000000L -#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK__VI 0x00000007L -#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK__VI 0x00000038L -#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK__VI 0x00800000L -#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK__VI 0x01000000L -#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK__VI 0x00000e00L -#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK__VI 0x00200000L -#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT_MASK__VI 0x00038000L -#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF_MASK__VI 0x000001c0L -#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK__VI 0x001c0000L -#define PB0_PIF_RX_CTRL__RXPWR_IN_S2_MASK__VI 0x00000007L -#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK__VI 0x00000038L -#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK__VI 0x00007000L -#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK__VI 0x00400000L -#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK__VI 0x02000000L -#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK__VI 0x00000020L -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK__VI 0x00001000L -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK__VI 0x00002000L -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK__VI 0x00004000L -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK__VI 0x00008000L -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK__VI 0x00010000L -#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK__VI 0x000000c0L -#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK__VI 0x00000400L -#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK__VI 0x00000800L -#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK__VI 0x00000300L -#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK__VI 0x00000004L -#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK__VI 0x00000010L -#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK__VI 0x00000002L -#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK__VI 0x00000008L -#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK__VI 0x000001c0L -#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK__VI 0x02000000L -#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK__VI 0x00200000L -#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK__VI 0x00060000L -#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK__VI 0x00010000L -#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK__VI 0x1c000000L -#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK__VI 0x01c00000L -#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK__VI 0x00000007L -#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK__VI 0x00000038L -#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK__VI 0x00000e00L -#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK__VI 0x00200000L -#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT_MASK__VI 0x00038000L -#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF_MASK__VI 0x000001c0L -#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK__VI 0x001c0000L -#define PB0_PIF_TX_CTRL__TXPWR_IN_S2_MASK__VI 0x00000007L -#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK__VI 0x00000038L -#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK__VI 0x00007000L -#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK__VI 0x00400000L -#define PB0_PIF_TX_CTRL__TX_PWR_GATING_IN_L1_MASK__VI 0x00800000L -#define PB0_PIF_TX_CTRL__TX_PWR_GATING_IN_UNUSED_MASK__VI 0x01000000L -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK__VI 0x00000300L -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK__VI 0x00000300L -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK__VI 0x00000300L -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK__VI 0x00000300L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK__VI 0x00020000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK__VI 0x00040000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK__VI 0x00008000L -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK__VI 0x00010000L -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK__VI 0x00000018L -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK__VI 0x00000060L -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK__VI 0x00000180L -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK__VI 0x00000e00L -#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK__VI 0x00003000L -#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK__VI 0x0000c000L -#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK__VI 0x00030000L -#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK__VI 0x80000000L -#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK__VI 0x10000000L -#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK__VI 0x20000000L -#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK__VI 0x00004000L -#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK__VI 0x00020000L -#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK__VI 0x00010000L -#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK__VI 0x00000003L -#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK__VI 0x0000000cL -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK__VI 0x00000010L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK__VI 0x00000080L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK__VI 0x00000020L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK__VI 0x00000040L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK__VI 0x00001000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK__VI 0x00008000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK__VI 0x00002000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK__VI 0x00004000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK__VI 0x00010000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK__VI 0x00080000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK__VI 0x00020000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK__VI 0x00040000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK__VI 0x00000100L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK__VI 0x00000800L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK__VI 0x00000200L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK__VI 0x00000400L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK__VI 0x00100000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK__VI 0x00800000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK__VI 0x00200000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK__VI 0x00400000L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK__VI 0x00000008L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK__VI 0x00000040L -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK__VI 0x0003fc00L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK__VI 0x00000040L -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK__VI 0x0003fc00L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK__VI 0x00000040L -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK__VI 0x0003fc00L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK__VI 0x00000040L -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK__VI 0x0003fc00L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK__VI 0x00000040L -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK__VI 0x0003fc00L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK__VI 0x00000040L -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK__VI 0x0003fc00L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK__VI 0x00000040L -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK__VI 0x0003fc00L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK__VI 0x00000040L -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK__VI 0x0003fc00L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK__VI 0x00000040L -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK__VI 0x0003fc00L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK__VI 0x00000040L -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK__VI 0x0003fc00L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK__VI 0x00000040L -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK__VI 0x0003fc00L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK__VI 0x00000040L -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK__VI 0x0003fc00L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK__VI 0x00000040L -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK__VI 0x0003fc00L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK__VI 0x00000040L -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK__VI 0x0003fc00L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK__VI 0x00000040L -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK__VI 0x0003fc00L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK__VI 0x00000040L -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK__VI 0x0003fc00L -#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK__VI 0x00000010L -#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK__VI 0x00000006L -#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK__VI 0x00000080L -#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK__VI 0x00001800L -#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_PWRON_IN_RAMPDOWN_MASK__VI 0x00002000L -#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK__VI 0x00000400L -#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK__VI 0x00000060L -#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK__VI 0x00000018L -#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK__VI 0x00000300L -#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK__VI 0x00000180L -#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK__VI 0x0000001cL -#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK__VI 0x10000000L -#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK__VI 0x20000000L -#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK__VI 0xc0000000L -#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK__VI 0x00000060L -#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK__VI 0x00000600L -#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK__VI 0x00001800L -#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK__VI 0x01000000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK__VI 0x00000100L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK__VI 0x00000800L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK__VI 0x00000200L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK__VI 0x00000400L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK__VI 0x00001000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK__VI 0x00008000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK__VI 0x00002000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK__VI 0x00004000L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK__VI 0x00000008L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK__VI 0x00000004L -#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK__VI 0x00000008L -#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK__VI 0x00000010L -#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK__VI 0x00000020L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK__VI 0x00000008L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK__VI 0x00000010L -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK__VI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK__VI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK__VI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK__VI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK__VI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK__VI 0x30000000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK__VI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK__VI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK__VI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK__VI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK__VI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK__VI 0x30000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK__VI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK__VI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK__VI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK__VI 0x30000000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK__VI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK__VI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK__VI 0x00000004L -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK__VI 0x00000002L -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK__VI 0x00000001L -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK__VI 0x00030000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK__VI 0x00300000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK__VI 0x03000000L -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK__VI 0x30000000L -#define PB1_HW_DEBUG__HW_00_DEBUG_MASK__VI 0x00000001L -#define PB1_HW_DEBUG__HW_01_DEBUG_MASK__VI 0x00000002L -#define PB1_HW_DEBUG__HW_02_DEBUG_MASK__VI 0x00000004L -#define PB1_HW_DEBUG__HW_03_DEBUG_MASK__VI 0x00000008L -#define PB1_HW_DEBUG__HW_04_DEBUG_MASK__VI 0x00000010L -#define PB1_HW_DEBUG__HW_05_DEBUG_MASK__VI 0x00000020L -#define PB1_HW_DEBUG__HW_06_DEBUG_MASK__VI 0x00000040L -#define PB1_HW_DEBUG__HW_07_DEBUG_MASK__VI 0x00000080L -#define PB1_HW_DEBUG__HW_08_DEBUG_MASK__VI 0x00000100L -#define PB1_HW_DEBUG__HW_09_DEBUG_MASK__VI 0x00000200L -#define PB1_HW_DEBUG__HW_10_DEBUG_MASK__VI 0x00000400L -#define PB1_HW_DEBUG__HW_11_DEBUG_MASK__VI 0x00000800L -#define PB1_HW_DEBUG__HW_12_DEBUG_MASK__VI 0x00001000L -#define PB1_HW_DEBUG__HW_13_DEBUG_MASK__VI 0x00002000L -#define PB1_HW_DEBUG__HW_14_DEBUG_MASK__VI 0x00004000L -#define PB1_HW_DEBUG__HW_15_DEBUG_MASK__VI 0x00008000L -#define PB1_HW_DEBUG__HW_16_DEBUG_MASK__VI 0x00010000L -#define PB1_HW_DEBUG__HW_17_DEBUG_MASK__VI 0x00020000L -#define PB1_HW_DEBUG__HW_18_DEBUG_MASK__VI 0x00040000L -#define PB1_HW_DEBUG__HW_19_DEBUG_MASK__VI 0x00080000L -#define PB1_HW_DEBUG__HW_20_DEBUG_MASK__VI 0x00100000L -#define PB1_HW_DEBUG__HW_21_DEBUG_MASK__VI 0x00200000L -#define PB1_HW_DEBUG__HW_22_DEBUG_MASK__VI 0x00400000L -#define PB1_HW_DEBUG__HW_23_DEBUG_MASK__VI 0x00800000L -#define PB1_HW_DEBUG__HW_24_DEBUG_MASK__VI 0x01000000L -#define PB1_HW_DEBUG__HW_25_DEBUG_MASK__VI 0x02000000L -#define PB1_HW_DEBUG__HW_26_DEBUG_MASK__VI 0x04000000L -#define PB1_HW_DEBUG__HW_27_DEBUG_MASK__VI 0x08000000L -#define PB1_HW_DEBUG__HW_28_DEBUG_MASK__VI 0x10000000L -#define PB1_HW_DEBUG__HW_29_DEBUG_MASK__VI 0x20000000L -#define PB1_HW_DEBUG__HW_30_DEBUG_MASK__VI 0x40000000L -#define PB1_HW_DEBUG__HW_31_DEBUG_MASK__VI 0x80000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK__VI 0x00010000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_10_MASK__VI 0x04000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_11_MASK__VI 0x08000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_12_MASK__VI 0x10000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_13_MASK__VI 0x20000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_14_MASK__VI 0x40000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_15_MASK__VI 0x80000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK__VI 0x00020000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK__VI 0x00040000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK__VI 0x00080000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK__VI 0x00100000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK__VI 0x00200000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK__VI 0x00400000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK__VI 0x00800000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_8_MASK__VI 0x01000000L -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_9_MASK__VI 0x02000000L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK__VI 0x00000001L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_10_MASK__VI 0x00000400L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_11_MASK__VI 0x00000800L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_12_MASK__VI 0x00001000L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_13_MASK__VI 0x00002000L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_14_MASK__VI 0x00004000L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_15_MASK__VI 0x00008000L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK__VI 0x00000002L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK__VI 0x00000004L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK__VI 0x00000008L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK__VI 0x00000010L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK__VI 0x00000020L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK__VI 0x00000040L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK__VI 0x00000080L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_8_MASK__VI 0x00000100L -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_9_MASK__VI 0x00000200L -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK__VI 0x00000003L -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK__VI 0x00000060L -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK__VI 0x00000010L -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK__VI 0x0000000cL -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK__VI 0x00010000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_10_MASK__VI 0x04000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_11_MASK__VI 0x08000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_12_MASK__VI 0x10000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_13_MASK__VI 0x20000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_14_MASK__VI 0x40000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_15_MASK__VI 0x80000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK__VI 0x00020000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK__VI 0x00040000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK__VI 0x00080000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK__VI 0x00100000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK__VI 0x00200000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK__VI 0x00400000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK__VI 0x00800000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_8_MASK__VI 0x01000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_9_MASK__VI 0x02000000L -#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK__VI 0x00000040L -#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK__VI 0x00000002L -#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK__VI 0x00000180L -#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK__VI 0x00000004L -#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK__VI 0x00000200L -#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK__VI 0x00000038L -#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK__VI 0x00000001L -#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK__VI 0x00000002L -#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD_MASK__VI 0x00000010L -#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK__VI 0x00000004L -#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK__VI 0x00000008L -#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK__VI 0x00000001L -#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK__VI 0x00100000L -#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK__VI 0x00000020L -#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK__VI 0x00000040L -#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK__VI 0x00000080L -#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK__VI 0x00000001L -#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK__VI 0x00000002L -#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK__VI 0x00000004L -#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK__VI 0x00000008L -#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK__VI 0x00000010L -#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK__VI 0x00000400L -#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK__VI 0x00000800L -#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK__VI 0x00000100L -#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK__VI 0x00000200L -#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK__VI 0x00020000L -#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK__VI 0x00010000L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK__VI 0x00010000L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK__VI 0x00000001L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_10_MASK__VI 0x00000400L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_11_MASK__VI 0x00000800L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_12_MASK__VI 0x00001000L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_13_MASK__VI 0x00002000L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_14_MASK__VI 0x00004000L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_15_MASK__VI 0x00008000L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK__VI 0x00000002L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK__VI 0x00000004L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK__VI 0x00000008L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK__VI 0x00000010L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK__VI 0x00000020L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK__VI 0x00000040L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK__VI 0x00000080L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_8_MASK__VI 0x00000100L -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_9_MASK__VI 0x00000200L -#define PB1_PIF_HW_DEBUG__HW_00_DEBUG_MASK__VI 0x00000001L -#define PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK__VI 0x00000002L -#define PB1_PIF_HW_DEBUG__HW_02_DEBUG_MASK__VI 0x00000004L -#define PB1_PIF_HW_DEBUG__HW_03_DEBUG_MASK__VI 0x00000008L -#define PB1_PIF_HW_DEBUG__HW_04_DEBUG_MASK__VI 0x00000010L -#define PB1_PIF_HW_DEBUG__HW_05_DEBUG_MASK__VI 0x00000020L -#define PB1_PIF_HW_DEBUG__HW_06_DEBUG_MASK__VI 0x00000040L -#define PB1_PIF_HW_DEBUG__HW_07_DEBUG_MASK__VI 0x00000080L -#define PB1_PIF_HW_DEBUG__HW_08_DEBUG_MASK__VI 0x00000100L -#define PB1_PIF_HW_DEBUG__HW_09_DEBUG_MASK__VI 0x00000200L -#define PB1_PIF_HW_DEBUG__HW_10_DEBUG_MASK__VI 0x00000400L -#define PB1_PIF_HW_DEBUG__HW_11_DEBUG_MASK__VI 0x00000800L -#define PB1_PIF_HW_DEBUG__HW_12_DEBUG_MASK__VI 0x00001000L -#define PB1_PIF_HW_DEBUG__HW_13_DEBUG_MASK__VI 0x00002000L -#define PB1_PIF_HW_DEBUG__HW_14_DEBUG_MASK__VI 0x00004000L -#define PB1_PIF_HW_DEBUG__HW_15_DEBUG_MASK__VI 0x00008000L -#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK__VI 0x03000000L -#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK__VI 0xfc000000L -#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK__VI 0x00040000L -#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK__VI 0x00080000L -#define PB1_PIF_LANE0_OVRD2__FREQDIV_0_MASK__VI 0x00000018L -#define PB1_PIF_LANE0_OVRD2__GANGMODE_0_MASK__VI 0x00000007L -#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0_MASK__VI 0x00000060L -#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK__VI 0x00100000L -#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK__VI 0x00400000L -#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK__VI 0x00800000L -#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK__VI 0x00200000L -#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK__VI 0x00030000L -#define PB1_PIF_LANE0_OVRD2__RXPWR_0_MASK__VI 0x0000e000L -#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK__VI 0x00000080L -#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK__VI 0x00001800L -#define PB1_PIF_LANE0_OVRD2__TXPWR_0_MASK__VI 0x00000700L -#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK__VI 0x00010000L -#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK__VI 0x00020000L -#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK__VI 0x00004000L -#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK__VI 0x00008000L -#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK__VI 0x00000100L -#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK__VI 0x00000200L -#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK__VI 0x00000002L -#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK__VI 0x00000001L -#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK__VI 0x00000004L -#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK__VI 0x00000400L -#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK__VI 0x00001000L -#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK__VI 0x00002000L -#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK__VI 0x00000800L -#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK__VI 0x00000080L -#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK__VI 0x00000040L -#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK__VI 0x00000008L -#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK__VI 0x00000020L -#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK__VI 0x00000010L -#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK__VI 0x03000000L -#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK__VI 0xfc000000L -#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK__VI 0x00040000L -#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK__VI 0x00080000L -#define PB1_PIF_LANE1_OVRD2__FREQDIV_1_MASK__VI 0x00000018L -#define PB1_PIF_LANE1_OVRD2__GANGMODE_1_MASK__VI 0x00000007L -#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1_MASK__VI 0x00000060L -#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK__VI 0x00100000L -#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK__VI 0x00400000L -#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK__VI 0x00800000L -#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK__VI 0x00200000L -#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK__VI 0x00030000L -#define PB1_PIF_LANE1_OVRD2__RXPWR_1_MASK__VI 0x0000e000L -#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK__VI 0x00000080L -#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK__VI 0x00001800L -#define PB1_PIF_LANE1_OVRD2__TXPWR_1_MASK__VI 0x00000700L -#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK__VI 0x00010000L -#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK__VI 0x00020000L -#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK__VI 0x00004000L -#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK__VI 0x00008000L -#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK__VI 0x00000100L -#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK__VI 0x00000200L -#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK__VI 0x00000002L -#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK__VI 0x00000001L -#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK__VI 0x00000004L -#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK__VI 0x00000400L -#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK__VI 0x00001000L -#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK__VI 0x00002000L -#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK__VI 0x00000800L -#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK__VI 0x00000080L -#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK__VI 0x00000040L -#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK__VI 0x00000008L -#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK__VI 0x00000020L -#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK__VI 0x00000010L -#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK__VI 0x03000000L -#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK__VI 0xfc000000L -#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK__VI 0x00040000L -#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK__VI 0x00080000L -#define PB1_PIF_LANE2_OVRD2__FREQDIV_2_MASK__VI 0x00000018L -#define PB1_PIF_LANE2_OVRD2__GANGMODE_2_MASK__VI 0x00000007L -#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2_MASK__VI 0x00000060L -#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK__VI 0x00100000L -#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK__VI 0x00400000L -#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK__VI 0x00800000L -#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK__VI 0x00200000L -#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK__VI 0x00030000L -#define PB1_PIF_LANE2_OVRD2__RXPWR_2_MASK__VI 0x0000e000L -#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK__VI 0x00000080L -#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK__VI 0x00001800L -#define PB1_PIF_LANE2_OVRD2__TXPWR_2_MASK__VI 0x00000700L -#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK__VI 0x00010000L -#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK__VI 0x00020000L -#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK__VI 0x00004000L -#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK__VI 0x00008000L -#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK__VI 0x00000100L -#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK__VI 0x00000200L -#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK__VI 0x00000002L -#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK__VI 0x00000001L -#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK__VI 0x00000004L -#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK__VI 0x00000400L -#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK__VI 0x00001000L -#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK__VI 0x00002000L -#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK__VI 0x00000800L -#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK__VI 0x00000080L -#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK__VI 0x00000040L -#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK__VI 0x00000008L -#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK__VI 0x00000020L -#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK__VI 0x00000010L -#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK__VI 0x03000000L -#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK__VI 0xfc000000L -#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK__VI 0x00040000L -#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK__VI 0x00080000L -#define PB1_PIF_LANE3_OVRD2__FREQDIV_3_MASK__VI 0x00000018L -#define PB1_PIF_LANE3_OVRD2__GANGMODE_3_MASK__VI 0x00000007L -#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3_MASK__VI 0x00000060L -#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK__VI 0x00100000L -#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK__VI 0x00400000L -#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK__VI 0x00800000L -#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK__VI 0x00200000L -#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK__VI 0x00030000L -#define PB1_PIF_LANE3_OVRD2__RXPWR_3_MASK__VI 0x0000e000L -#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK__VI 0x00000080L -#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK__VI 0x00001800L -#define PB1_PIF_LANE3_OVRD2__TXPWR_3_MASK__VI 0x00000700L -#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK__VI 0x00010000L -#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK__VI 0x00020000L -#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK__VI 0x00004000L -#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK__VI 0x00008000L -#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK__VI 0x00000100L -#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK__VI 0x00000200L -#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK__VI 0x00000002L -#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK__VI 0x00000001L -#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK__VI 0x00000004L -#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK__VI 0x00000400L -#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK__VI 0x00001000L -#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK__VI 0x00002000L -#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK__VI 0x00000800L -#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK__VI 0x00000080L -#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK__VI 0x00000040L -#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK__VI 0x00000008L -#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK__VI 0x00000020L -#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK__VI 0x00000010L -#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK__VI 0x03000000L -#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK__VI 0xfc000000L -#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK__VI 0x00040000L -#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK__VI 0x00080000L -#define PB1_PIF_LANE4_OVRD2__FREQDIV_4_MASK__VI 0x00000018L -#define PB1_PIF_LANE4_OVRD2__GANGMODE_4_MASK__VI 0x00000007L -#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4_MASK__VI 0x00000060L -#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK__VI 0x00100000L -#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK__VI 0x00400000L -#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK__VI 0x00800000L -#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK__VI 0x00200000L -#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK__VI 0x00030000L -#define PB1_PIF_LANE4_OVRD2__RXPWR_4_MASK__VI 0x0000e000L -#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK__VI 0x00000080L -#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK__VI 0x00001800L -#define PB1_PIF_LANE4_OVRD2__TXPWR_4_MASK__VI 0x00000700L -#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK__VI 0x00010000L -#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK__VI 0x00020000L -#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK__VI 0x00004000L -#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK__VI 0x00008000L -#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK__VI 0x00000100L -#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK__VI 0x00000200L -#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK__VI 0x00000002L -#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK__VI 0x00000001L -#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK__VI 0x00000004L -#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK__VI 0x00000400L -#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK__VI 0x00001000L -#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK__VI 0x00002000L -#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK__VI 0x00000800L -#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK__VI 0x00000080L -#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK__VI 0x00000040L -#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK__VI 0x00000008L -#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK__VI 0x00000020L -#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK__VI 0x00000010L -#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK__VI 0x03000000L -#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK__VI 0xfc000000L -#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK__VI 0x00040000L -#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK__VI 0x00080000L -#define PB1_PIF_LANE5_OVRD2__FREQDIV_5_MASK__VI 0x00000018L -#define PB1_PIF_LANE5_OVRD2__GANGMODE_5_MASK__VI 0x00000007L -#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5_MASK__VI 0x00000060L -#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK__VI 0x00100000L -#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK__VI 0x00400000L -#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK__VI 0x00800000L -#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK__VI 0x00200000L -#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK__VI 0x00030000L -#define PB1_PIF_LANE5_OVRD2__RXPWR_5_MASK__VI 0x0000e000L -#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK__VI 0x00000080L -#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK__VI 0x00001800L -#define PB1_PIF_LANE5_OVRD2__TXPWR_5_MASK__VI 0x00000700L -#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK__VI 0x00010000L -#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK__VI 0x00020000L -#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK__VI 0x00004000L -#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK__VI 0x00008000L -#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK__VI 0x00000100L -#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK__VI 0x00000200L -#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK__VI 0x00000002L -#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK__VI 0x00000001L -#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK__VI 0x00000004L -#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK__VI 0x00000400L -#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK__VI 0x00001000L -#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK__VI 0x00002000L -#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK__VI 0x00000800L -#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK__VI 0x00000080L -#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK__VI 0x00000040L -#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK__VI 0x00000008L -#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK__VI 0x00000020L -#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK__VI 0x00000010L -#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK__VI 0x03000000L -#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK__VI 0xfc000000L -#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK__VI 0x00040000L -#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK__VI 0x00080000L -#define PB1_PIF_LANE6_OVRD2__FREQDIV_6_MASK__VI 0x00000018L -#define PB1_PIF_LANE6_OVRD2__GANGMODE_6_MASK__VI 0x00000007L -#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6_MASK__VI 0x00000060L -#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK__VI 0x00100000L -#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK__VI 0x00400000L -#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK__VI 0x00800000L -#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK__VI 0x00200000L -#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK__VI 0x00030000L -#define PB1_PIF_LANE6_OVRD2__RXPWR_6_MASK__VI 0x0000e000L -#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK__VI 0x00000080L -#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK__VI 0x00001800L -#define PB1_PIF_LANE6_OVRD2__TXPWR_6_MASK__VI 0x00000700L -#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK__VI 0x00010000L -#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK__VI 0x00020000L -#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK__VI 0x00004000L -#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK__VI 0x00008000L -#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK__VI 0x00000100L -#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK__VI 0x00000200L -#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK__VI 0x00000002L -#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK__VI 0x00000001L -#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK__VI 0x00000004L -#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK__VI 0x00000400L -#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK__VI 0x00001000L -#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK__VI 0x00002000L -#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK__VI 0x00000800L -#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK__VI 0x00000080L -#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK__VI 0x00000040L -#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK__VI 0x00000008L -#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK__VI 0x00000020L -#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK__VI 0x00000010L -#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK__VI 0x03000000L -#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK__VI 0xfc000000L -#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK__VI 0x00040000L -#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK__VI 0x00080000L -#define PB1_PIF_LANE7_OVRD2__FREQDIV_7_MASK__VI 0x00000018L -#define PB1_PIF_LANE7_OVRD2__GANGMODE_7_MASK__VI 0x00000007L -#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7_MASK__VI 0x00000060L -#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK__VI 0x00100000L -#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK__VI 0x00400000L -#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK__VI 0x00800000L -#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK__VI 0x00200000L -#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK__VI 0x00030000L -#define PB1_PIF_LANE7_OVRD2__RXPWR_7_MASK__VI 0x0000e000L -#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK__VI 0x00000080L -#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK__VI 0x00001800L -#define PB1_PIF_LANE7_OVRD2__TXPWR_7_MASK__VI 0x00000700L -#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK__VI 0x00010000L -#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK__VI 0x00020000L -#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK__VI 0x00004000L -#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK__VI 0x00008000L -#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK__VI 0x00000100L -#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK__VI 0x00000200L -#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK__VI 0x00000002L -#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK__VI 0x00000001L -#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK__VI 0x00000004L -#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK__VI 0x00000400L -#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK__VI 0x00001000L -#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK__VI 0x00002000L -#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK__VI 0x00000800L -#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK__VI 0x00000080L -#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK__VI 0x00000040L -#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK__VI 0x00000008L -#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK__VI 0x00000020L -#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK__VI 0x00000010L -#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK__VI 0x01000000L -#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK__VI 0x00060000L -#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK__VI 0x00e00000L -#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK__VI 0x00180000L -#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK__VI 0x00010000L -#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK__VI 0x000001c0L -#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK__VI 0x06000000L -#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK__VI 0x08000000L -#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK__VI 0x00000007L -#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK__VI 0x00000038L -#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK__VI 0x00800000L -#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK__VI 0x01000000L -#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK__VI 0x00000e00L -#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK__VI 0x00200000L -#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT_MASK__VI 0x00038000L -#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF_MASK__VI 0x000001c0L -#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK__VI 0x001c0000L -#define PB1_PIF_RX_CTRL__RXPWR_IN_S2_MASK__VI 0x00000007L -#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK__VI 0x00000038L -#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK__VI 0x00007000L -#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK__VI 0x00400000L -#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK__VI 0x02000000L -#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK__VI 0x00000020L -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK__VI 0x00001000L -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK__VI 0x00002000L -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK__VI 0x00004000L -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK__VI 0x00008000L -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK__VI 0x00010000L -#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK__VI 0x000000c0L -#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK__VI 0x00000400L -#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK__VI 0x00000800L -#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK__VI 0x00000300L -#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK__VI 0x00000004L -#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK__VI 0x00000010L -#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK__VI 0x00000002L -#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK__VI 0x00000008L -#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK__VI 0x000001c0L -#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK__VI 0x02000000L -#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK__VI 0x00200000L -#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK__VI 0x00060000L -#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK__VI 0x00010000L -#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK__VI 0x1c000000L -#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK__VI 0x01c00000L -#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK__VI 0x00000007L -#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK__VI 0x00000038L -#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK__VI 0x00000e00L -#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK__VI 0x00200000L -#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT_MASK__VI 0x00038000L -#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF_MASK__VI 0x000001c0L -#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK__VI 0x001c0000L -#define PB1_PIF_TX_CTRL__TXPWR_IN_S2_MASK__VI 0x00000007L -#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK__VI 0x00000038L -#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK__VI 0x00007000L -#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK__VI 0x00400000L -#define PB1_PIF_TX_CTRL__TX_PWR_GATING_IN_L1_MASK__VI 0x00800000L -#define PB1_PIF_TX_CTRL__TX_PWR_GATING_IN_UNUSED_MASK__VI 0x01000000L -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK__VI 0x00000300L -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK__VI 0x00000300L -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK__VI 0x00000300L -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK__VI 0x00000002L -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK__VI 0x00000001L -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK__VI 0x00000300L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK__VI 0x00020000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK__VI 0x00040000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK__VI 0x00008000L -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK__VI 0x00010000L -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK__VI 0x00000018L -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK__VI 0x00000060L -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK__VI 0x00000180L -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK__VI 0x00000e00L -#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK__VI 0x00003000L -#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK__VI 0x0000c000L -#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK__VI 0x00030000L -#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK__VI 0x80000000L -#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK__VI 0x10000000L -#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK__VI 0x20000000L -#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK__VI 0x00004000L -#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK__VI 0x00020000L -#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK__VI 0x00010000L -#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK__VI 0x00000003L -#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK__VI 0x0000000cL -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK__VI 0x00000010L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK__VI 0x00000080L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK__VI 0x00000020L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK__VI 0x00000040L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK__VI 0x00001000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK__VI 0x00008000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK__VI 0x00002000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK__VI 0x00004000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK__VI 0x00010000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK__VI 0x00080000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK__VI 0x00020000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK__VI 0x00040000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK__VI 0x00000100L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK__VI 0x00000800L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK__VI 0x00000200L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK__VI 0x00000400L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK__VI 0x00100000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK__VI 0x00800000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK__VI 0x00200000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK__VI 0x00400000L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK__VI 0x00000008L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK__VI 0x00000040L -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK__VI 0x0003fc00L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK__VI 0x00000040L -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK__VI 0x0003fc00L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK__VI 0x00000040L -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK__VI 0x0003fc00L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK__VI 0x00000040L -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK__VI 0x0003fc00L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK__VI 0x00000040L -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK__VI 0x0003fc00L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK__VI 0x00000040L -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK__VI 0x0003fc00L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK__VI 0x00000040L -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK__VI 0x0003fc00L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK__VI 0x00000040L -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK__VI 0x0003fc00L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK__VI 0x00000040L -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK__VI 0x0003fc00L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK__VI 0x00000040L -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK__VI 0x0003fc00L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK__VI 0x00000040L -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK__VI 0x0003fc00L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK__VI 0x00000040L -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK__VI 0x0003fc00L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK__VI 0x00000040L -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK__VI 0x0003fc00L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK__VI 0x00000040L -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK__VI 0x0003fc00L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK__VI 0x00000040L -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK__VI 0x0003fc00L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK__VI 0x00000040L -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK__VI 0x0003fc00L -#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK__VI 0x00000010L -#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK__VI 0x00000006L -#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK__VI 0x00000080L -#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK__VI 0x00001800L -#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_PWRON_IN_RAMPDOWN_MASK__VI 0x00002000L -#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK__VI 0x00000400L -#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK__VI 0x00000060L -#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK__VI 0x00000018L -#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK__VI 0x00000300L -#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK__VI 0x00000180L -#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK__VI 0x0000001cL -#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK__VI 0x10000000L -#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK__VI 0x20000000L -#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK__VI 0xc0000000L -#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK__VI 0x00000060L -#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK__VI 0x00000600L -#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK__VI 0x00001800L -#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK__VI 0x01000000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK__VI 0x00000100L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK__VI 0x00000800L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK__VI 0x00000200L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK__VI 0x00000400L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK__VI 0x00001000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK__VI 0x00008000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK__VI 0x00002000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK__VI 0x00004000L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK__VI 0x00000001L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK__VI 0x00000008L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK__VI 0x00000002L -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK__VI 0x00000004L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK__VI 0x00030000L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK__VI 0x0000c000L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK__VI 0x000000c0L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK__VI 0x00000030L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK__VI 0x00c00000L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK__VI 0x00003000L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK__VI 0x0000000cL -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK__VI 0x00300000L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK__VI 0x00000003L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK__VI 0x00000c00L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK__VI 0x00000300L -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK__VI 0x000c0000L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK__VI 0x00000030L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK__VI 0x000000c0L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK__VI 0x00030000L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK__VI 0x000c0000L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK__VI 0x00000c00L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK__VI 0x00000003L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK__VI 0x00003000L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK__VI 0x0000000cL -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK__VI 0x0000c000L -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK__VI 0x00000300L -#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK__VI 0x00000003L -#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK__VI 0x00000800L -#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK__VI 0x00000002L -#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK__VI 0x00000001L -#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK__VI 0x0000ff00L -#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK__VI 0x00000002L -#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK__VI 0x00000070L -#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK__VI 0x00000001L -#define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK__VI 0x0000ffffL -#define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK__VI 0x000f0000L -#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK__VI 0xfff00000L -#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK__VI 0x00000040L -#define PCIE_CNTL2__MST_MEM_DS_EN_MASK__VI 0x40000000L -#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK__VI 0x80000000L -#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK__VI 0x20000000L -#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK__VI 0x00002000L -#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK__VI 0x00004000L -#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK__VI 0x00000800L -#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK__VI 0x00001000L -#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK__VI 0x00100000L -#define PCIE_EFUSE2__PCIE_EFUSE2_MASK__VI 0xffffffffL -#define PCIE_EFUSE3__PCIE_EFUSE3_MASK__VI 0xffffffffL -#define PCIE_EFUSE4__PCIE_EFUSE4_MASK__VI 0xffffffffL -#define PCIE_EFUSE5__PCIE_EFUSE5_MASK__VI 0xffffffffL -#define PCIE_EFUSE__PCIE_EFUSE_MASK__VI 0xffffffffL -#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK__VI 0x00020000L -#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK__VI 0x00040000L -#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK__VI 0x00000100L -#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK__VI 0x00000001L -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK__VI 0x0000fc00L -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK__VI 0x3fc00000L -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK__VI 0x003f0000L -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK__VI 0x000003f0L -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK__VI 0x0000000fL -#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK__VI 0x02000000L -#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK__VI 0x00000008L -#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK__VI 0x00000004L -#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK__VI 0x00000400L -#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK__VI 0xfc000000L -#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK__VI 0x01000000L -#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK__VI 0x00000001L -#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK__VI 0x00000004L -#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK__VI 0x00000010L -#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK__VI 0x00080000L -#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK__VI 0x00100000L -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK__VI 0x00000001L -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK__VI 0x00001f80L -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK__VI 0x0007e000L -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK__VI 0x0000007eL -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK__VI 0x01f80000L -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK__VI 0x7e000000L -#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK__VI 0x01000000L -#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK__VI 0xc0000000L -#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK__VI 0x00008000L -#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK__VI 0x20000000L -#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK__VI 0x00004000L -#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK__VI 0x1c000000L -#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK__VI 0x03ff0000L -#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK__VI 0x00001c00L -#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK__VI 0x000003ffL -#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK__VI 0x0000ffffL -#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK__VI 0x000f0000L -#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK__VI 0xfff00000L -#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK__VI 0xfffff000L -#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK__VI 0x0000003fL -#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK__VI 0xffffffffL -#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK__VI 0xffffffffL -#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK__VI 0xffffffffL -#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK__VI 0xffffffffL -#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK__VI 0xffffffffL -#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK__VI 0x00008000L -#define PCIE_MC_CAP__MC_MAX_GROUP_MASK__VI 0x0000003fL -#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK__VI 0x00003f00L -#define PCIE_MC_CNTL__MC_ENABLE_MASK__VI 0x00008000L -#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK__VI 0x0000003fL -#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK__VI 0x0000ffffL -#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK__VI 0x000f0000L -#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK__VI 0xfff00000L -#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK__VI 0xffffffffL -#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK__VI 0xffffffffL -#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK__VI 0x00080000L -#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK__VI 0x00040000L -#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK__VI 0x00020000L -#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK__VI 0x00000004L -#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK__VI 0x00010000L -#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK__VI 0x00f00000L -#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK__VI 0x00000001L -#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK__VI 0x00000008L -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK__VI 0x000000f0L -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK__VI 0x00000f00L -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK__VI 0x0000f000L -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK__VI 0x00000002L -#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK__VI 0x00008000L -#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK__SI__CI 0x00000010L -#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK__VI 0x00000020L -#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK__SI__CI 0x00000060L -#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK__VI 0x000000c0L -#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK__SI__CI 0x00000f80L -#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK__VI 0x00001f00L -#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK__SI__CI 0x00000006L -#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK__VI 0x0000000eL -#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK__SI__CI 0x00000008L -#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK__VI 0x00000010L -#define PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK__VI 0x00010000L -#define PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK__VI 0x0000ffffL -#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK__VI 0x00000100L -#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK__VI 0x03ff0000L -#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK__VI 0x00000e00L -#define PCIE_RX_CNTL__RX_TPH_DIS_MASK__VI 0x04000000L -#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK__VI 0x00000002L -#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK__VI 0x00000001L -#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK__VI 0xffe00000L -#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK__VI 0x00000010L -#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK__VI 0x00000001L -#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK__VI 0x00000002L -#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK__VI 0x00000004L -#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK__VI 0x00000008L -#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK__VI 0x0000ffffL -#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK__VI 0x000f0000L -#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK__VI 0xfff00000L -#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK__VI 0x0000ffffL -#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK__VI 0x000000ffL -#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK__VI 0x0000ffffL -#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK__VI 0x0000ffffL -#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK__VI 0x00000001L -#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK__VI 0xffffffffL -#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK__VI 0xffffffffL -#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK__VI 0x0000ffffL -#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK__VI 0xffffffffL -#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK__VI 0xffffffffL -#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK__VI 0xffffffffL -#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK__VI 0xffffffffL -#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK__VI 0xffffffffL -#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK__VI 0xffffffffL -#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK__VI 0x0000ffffL -#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK__VI \ - 0xffffffffL -#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK__VI 0x0000ffffL -#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK__VI 0x00080000L -#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK__VI 0x00040000L -#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK__VI 0x00100000L -#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK__VI 0x00008000L -#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK__VI 0x00002000L -#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK__VI 0x00004000L -#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK__VI 0x00020000L -#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK__VI 0x00e00000L -#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK__VI 0x08000000L -#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK__VI 0x00010000L -#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK__VI 0x07000000L -#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK__VI 0x00080000L -#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK__VI 0x00040000L -#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK__VI 0x00100000L -#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK__VI 0x00008000L -#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK__VI 0x00002000L -#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK__VI 0x00004000L -#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK__VI 0x00e00000L -#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK__VI 0x08000000L -#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK__VI 0x00010000L -#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK__VI 0x00080000L -#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK__VI 0x00040000L -#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK__VI 0x00100000L -#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK__VI 0x00008000L -#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK__VI 0x00002000L -#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK__VI 0x00004000L -#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK__VI 0x00e00000L -#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK__VI 0x08000000L -#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK__VI 0x00010000L -#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK__VI 0x80000000L -#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK__VI 0x00000004L -#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK__VI 0x00000100L -#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK__VI 0x00000002L -#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK__VI 0x00000001L -#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK__VI 0x00000600L -#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK__VI 0x07ff0000L -#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK__VI 0x00000300L -#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK__VI 0x00000007L -#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK__VI 0x0000ffffL -#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK__VI 0x000f0000L -#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK__VI 0xfff00000L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK__VI 0x00004000L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK__VI 0x00001c00L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK__VI 0x00002000L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK__VI 0x00000380L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK__VI 0x00008000L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK__VI 0x00000038L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK__VI 0x00000040L -#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK__VI 0x00000007L -#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK__VI 0x00010000L -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK__VI 0x0000ffffL -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK__VI 0x000f0000L -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK__VI 0xfff00000L -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK__VI 0x00000001L -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK__VI 0x0000ffffL -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK__VI 0xfff00000L -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK__VI 0x000f0000L -#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK__VI 0x00000001L -#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK__VI 0x00000002L -#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK__VI 0x00000004L -#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK__VI 0x00000100L -#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK__VI 0x00000080L -#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK__VI 0x00000070L -#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK__VI 0x00000007L -#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK__VI 0x00000001L -#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK__VI 0xffffffffL -#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK__VI 0xffffffffL -#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK__VI 0x00000001L -#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK__VI 0x00000002L -#define PWR_INT_GPIO_CLEAR__INT_GPIO_CLEAR_MASK__VI 0x7fffffffL -#define PWR_INT_GPIO_PENDING__INT_GPIO_PENDING_MASK__VI 0x7fffffffL -#define PWR_INT_GPIO_POLARITY__INT_GPIO_POLARITY_MASK__VI 0x7fffffffL -#define PWR_INT_GPIO_SENSE__INT_GPIO_SENSE_MASK__VI 0x7fffffffL -#define PWR_OBSRV_CNTL__NONCLK_OBSRV_SEL1_MASK__VI 0x000000ffL -#define PWR_OBSRV_CNTL__NONCLK_OBSRV_SEL2_MASK__VI 0x0000ff00L -#define RAS_TA_SIGNATURE1__SIGNATURE_MASK__VI 0xffffffffL -#define RCU_SYSRESET__ACP_hard_resetb_MASK__VI 0x08000000L -#define RCU_SYSRESET__DC_az_hard_resetb_MASK__VI 0x00040000L -#define RCU_SYSRESET__IOMMU_hard_resetb_MASK__VI 0x10000000L -#define RCU_SYSRESET__UVD_hard_resetb_MASK__VI 0x01000000L -#define RCU_SYSRESET__VCE_hard_resetb_MASK__VI 0x06000000L -#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK__VI 0x00000001L -#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK__VI 0x00000001L -#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK__VI 0x00000001L -#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK__VI 0x00000001L -#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK__VI 0x0007fffcL -#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK__VI 0x0007fffcL -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK__VI 0x80000000L -#define RLC_CLK_CNTL__RESERVED_MASK__VI 0xfffffffcL -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK__VI 0x00000002L -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK__VI 0x00000001L -#define RLC_CP_RESPONSE0__RESPONSE_MASK__VI 0xffffffffL -#define RLC_CP_RESPONSE1__RESPONSE_MASK__VI 0xffffffffL -#define RLC_CP_RESPONSE2__RESPONSE_MASK__VI 0xffffffffL -#define RLC_CP_RESPONSE3__RESPONSE_MASK__VI 0xffffffffL -#define RLC_CP_SCHEDULERS__scheduler0_MASK__VI 0x000000ffL -#define RLC_CP_SCHEDULERS__scheduler1_MASK__VI 0x0000ff00L -#define RLC_CP_SCHEDULERS__scheduler2_MASK__VI 0x00ff0000L -#define RLC_CP_SCHEDULERS__scheduler3_MASK__VI 0xff000000L -#define RLC_CSIB_ADDR_HI__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_CSIB_ADDR_LO__ADDRESS_MASK__VI 0xffffffffL -#define RLC_CSIB_LENGTH__LENGTH_MASK__VI 0xffffffffL -#define RLC_DEBE_0__SE0_SH0_CU_CONFIG_MASK__VI 0x00000fffL -#define RLC_DEBE_0__SE1_SH0_CU_CONFIG_MASK__VI 0x00fff000L -#define RLC_DEBE_0__SE2_SH0_CU_CONFIG_PART_1_MASK__VI 0xff000000L -#define RLC_DEBE_1__SE2_SH0_CU_CONFIG_PART_2_MASK__VI 0x0000000fL -#define RLC_DEBE_1__SE3_SH0_CU_CONFIG_MASK__VI 0x0000fff0L -#define RLC_DEBE_1__TCC_CONFIG_MASK__VI 0xffff0000L -#define RLC_DEBE_2__DCE_CONFIG_MASK__VI 0xfc000000L -#define RLC_DEBE_2__PRIM_CONFIG_MASK__VI 0x03f00000L -#define RLC_DEBE_2__SE0_RB_CONFIG_MASK__VI 0x0000000fL -#define RLC_DEBE_2__SE1_RB_CONFIG_MASK__VI 0x000000f0L -#define RLC_DEBE_2__SE2_RB_CONFIG_MASK__VI 0x00000f00L -#define RLC_DEBE_2__SE3_RB_CONFIG_MASK__VI 0x0000f000L -#define RLC_DEBE_2__SPARE_RB_CONFIG_MASK__VI 0x000f0000L -#define RLC_DEBE_3__ACP_CONFIG_MASK__VI 0x00000078L -#define RLC_DEBE_3__RESERVED_MASK__VI 0xffffff80L -#define RLC_DEBE_3__UVD_CONFIG_MASK__VI 0x00000001L -#define RLC_DEBE_3__VCE_CONFIG_MASK__VI 0x00000006L -#define RLC_DEBE_WRITE_DIS__ACP_WRITE_DIS_MASK__VI 0x00000080L -#define RLC_DEBE_WRITE_DIS__CU_WRITE_DIS_MASK__VI 0x00000001L -#define RLC_DEBE_WRITE_DIS__DCE_WRITE_DIS_MASK__VI 0x00000010L -#define RLC_DEBE_WRITE_DIS__PRIM_WRITE_DIS_MASK__VI 0x00000008L -#define RLC_DEBE_WRITE_DIS__RB_WRITE_DIS_MASK__VI 0x00000004L -#define RLC_DEBE_WRITE_DIS__RESERVED_MASK__VI 0xffffff00L -#define RLC_DEBE_WRITE_DIS__TCC_WRITE_DIS_MASK__VI 0x00000002L -#define RLC_DEBE_WRITE_DIS__UVD_WRITE_DIS_MASK__VI 0x00000020L -#define RLC_DEBE_WRITE_DIS__VCE_WRITE_DIS_MASK__VI 0x00000040L -#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK__VI 0x00000300L -#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK__VI 0xfffffc00L -#define RLC_GPM_GENERAL_10__DATA_MASK__VI 0xffffffffL -#define RLC_GPM_GENERAL_11__DATA_MASK__VI 0xffffffffL -#define RLC_GPM_GENERAL_12__DATA_MASK__VI 0xffffffffL -#define RLC_GPM_GENERAL_8__DATA_MASK__VI 0xffffffffL -#define RLC_GPM_GENERAL_9__DATA_MASK__VI 0xffffffffL -#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK__VI 0xffffffffL -#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK__VI 0xffffffffL -#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK__VI 0xffffffffL -#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK__VI 0xffffffffL -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK__VI 0x00020000L -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK__VI 0x00001000L -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK__VI 0x00000100L -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK__VI 0x00000040L -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK__VI 0x00000020L -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK__VI 0x00010000L -#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK__VI 0x00008000L -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK__VI 0x00000800L -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK__VI 0x00000080L -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK__VI 0x00000010L -#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK__VI 0xff000000L -#define RLC_GPM_STAT__RESERVED_MASK__VI 0x00fc0000L -#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK__VI 0x00000400L -#define RLC_GPM_STAT__SAVING_REGISTERS_MASK__VI 0x00000200L -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK__VI 0x00004000L -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK__VI 0x00002000L -#define RLC_GPM_THREAD_RESET__RESERVED_MASK__VI 0xfffffff0L -#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK__VI 0x00000001L -#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK__VI 0x00000002L -#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK__VI 0x00000004L -#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK__VI 0x00000008L -#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK__VI 0x000000f0L -#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK__VI 0xfffff800L -#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK__VI 0x00000700L -#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK__VI 0x000000f0L -#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK__VI 0xfffff800L -#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK__VI 0x00000700L -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK__VI 0x80000000L -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK__VI 0x7ffffff0L -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK__VI 0x0000000fL -#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK__VI 0xffffffffL -#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK__VI 0x0000fffeL -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK__VI 0x00000001L -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK__VI 0xffff0000L -#define RLC_MEM_SLP_CNTL__RESERVED_MASK__SI__CI 0x000000fcL -#define RLC_MEM_SLP_CNTL__RESERVED_MASK__VI 0x0000007cL -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK__VI 0x00000080L -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK__VI 0x00008000L -#define RLC_MGCG_CTRL__MGCG_EN_MASK__VI 0x00000001L -#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK__VI 0x00007f80L -#define RLC_MGCG_CTRL__ON_DELAY_MASK__VI 0x00000078L -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK__VI 0x00010000L -#define RLC_MGCG_CTRL__SILICON_EN_MASK__VI 0x00000002L -#define RLC_MGCG_CTRL__SIMULATION_EN_MASK__VI 0x00000004L -#define RLC_MGCG_CTRL__SPARE_MASK__VI 0xfffe0000L -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK__VI 0x00000001L -#define RLC_PG_CNTL__CP_PG_DISABLE_MASK__VI 0x00008000L -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK__VI 0x00000010L -#define RLC_PG_CNTL__PG_OVERRIDE_MASK__VI 0x00004000L -#define RLC_PG_CNTL__RESERVED1_MASK__VI 0x00f00000L -#define RLC_PG_CNTL__RESERVED_MASK__VI 0x00003fe0L -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK__VI 0x00080000L -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK__VI 0x000000ffL -#define RLC_PG_DELAY_3__RESERVED_MASK__VI 0xffffff00L -#define RLC_RLCV_COMMAND__CMD_MASK__VI 0x0000000fL -#define RLC_RLCV_COMMAND__RESERVED_MASK__VI 0xfffffff0L -#define RLC_RLCV_SAFE_MODE__CMD_MASK__VI 0x00000001L -#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK__VI 0x0000001eL -#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK__VI 0x000000e0L -#define RLC_RLCV_SAFE_MODE__RESERVED_MASK__VI 0xfffff000L -#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK__VI 0x00000f00L -#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK__VI 0x00000010L -#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK__VI 0x00000004L -#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK__VI 0x00000008L -#define RLC_ROM_CNTL__RESERVED_MASK__VI 0xffffffe0L -#define RLC_ROM_CNTL__SLP_MODE_EN_MASK__VI 0x00000002L -#define RLC_ROM_CNTL__USE_ROM_MASK__VI 0x00000001L -#define RLC_SAFE_MODE__CMD_MASK__VI 0x00000001L -#define RLC_SAFE_MODE__RESERVED1_MASK__VI 0x000000e0L -#define RLC_SAFE_MODE__RESERVED_MASK__VI 0xfffff000L -#define RLC_SAFE_MODE__RESPONSE_MASK__VI 0x00000f00L -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK__VI 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK__VI 0xff000000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK__VI 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK__VI 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK__VI 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK__VI 0x00800000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK__VI 0x00040000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK__VI 0x00080000L -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK__VI 0x00018000L -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK__VI 0x00007800L -#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK__VI 0xfffe0000L -#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK__VI 0x03ff0000L -#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK__VI 0x00004000L -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK__VI 0x08000000L -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK__VI 0x00008000L -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK__VI 0x04000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK__VI 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK__VI 0xff000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK__VI 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK__VI 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK__VI 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK__VI 0x00800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK__VI 0x00040000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK__VI 0x00080000L -#define RLC_SMU_ARGUMENT_1__ARG_MASK__VI 0xffffffffL -#define RLC_SMU_ARGUMENT_2__ARG_MASK__VI 0xffffffffL -#define RLC_SMU_COMMAND__CMD_MASK__VI 0xffffffffL -#define RLC_SMU_MESSAGE__CMD_MASK__VI 0xffffffffL -#define RLC_SMU_RESP__CONTENT_MASK__VI 0xffffffffL -#define RLC_SMU_SAFE_MODE__CMD_MASK__VI 0x00000001L -#define RLC_SMU_SAFE_MODE__MESSAGE_MASK__VI 0x0000001eL -#define RLC_SMU_SAFE_MODE__RESERVED1_MASK__VI 0x000000e0L -#define RLC_SMU_SAFE_MODE__RESERVED_MASK__VI 0xfffff000L -#define RLC_SMU_SAFE_MODE__RESPONSE_MASK__VI 0x00000f00L -#define RLC_SRM_ARAM_ADDR__ADDR_MASK__VI 0x000003ffL -#define RLC_SRM_ARAM_ADDR__RESERVED_MASK__VI 0xfffffc00L -#define RLC_SRM_ARAM_DATA__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK__VI 0x00000002L -#define RLC_SRM_CNTL__RESERVED_MASK__VI 0xfffffffcL -#define RLC_SRM_CNTL__SRM_ENABLE_MASK__VI 0x00000001L -#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK__VI 0xffffff00L -#define RLC_SRM_DEBUG_SELECT__SELECT_MASK__VI 0x000000ffL -#define RLC_SRM_DEBUG__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_DRAM_ADDR__ADDR_MASK__VI 0x000003ffL -#define RLC_SRM_DRAM_ADDR__RESERVED_MASK__VI 0xfffffc00L -#define RLC_SRM_DRAM_DATA__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_GPM_ABORT__ABORT_MASK__VI 0x00000001L -#define RLC_SRM_GPM_ABORT__RESERVED_MASK__VI 0xfffffffeL -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK__VI 0x00000001L -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK__VI 0x00000002L -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK__VI 0xfffffffcL -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK__VI 0x80000000L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK__VI 0x00000002L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK__VI 0x0000001cL -#define RLC_SRM_GPM_COMMAND__OP_MASK__VI 0x00000001L -#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK__VI 0x60000000L -#define RLC_SRM_GPM_COMMAND__SIZE_MASK__VI 0x0001ffe0L -#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK__VI 0x1ffe0000L -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK__VI 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK__VI 0xffff0000L -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK__VI 0xffffffffL -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK__VI 0x00000001L -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK__VI 0x00000002L -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK__VI 0xfffffffcL -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK__VI 0x80000000L -#define RLC_SRM_RLCV_COMMAND__OP_MASK__VI 0x00000001L -#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK__VI 0x70000000L -#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK__VI 0x0000000eL -#define RLC_SRM_RLCV_COMMAND__SIZE_MASK__VI 0x0000fff0L -#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK__VI 0x0fff0000L -#define RLC_SRM_STAT__RESERVED_MASK__VI 0xfffffffeL -#define RLC_SRM_STAT__SRM_STATUS_MASK__VI 0x00000001L -#define RLC_STAT__RLC_SRM_BUSY_MASK__VI 0x00000008L -#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK__VI 0x00004000L -#define SDMA0_ACTIVE_FCN_ID__VFID_MASK__VI 0x0000000fL -#define SDMA0_ACTIVE_FCN_ID__VF_MASK__VI 0x80000000L -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK__VI 0x80000000L -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK__VI 0x7fffffffL -#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK__VI 0xffffffffL -#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK__VI 0xffffffffL -#define SDMA0_BA_THRESHOLD__READ_THRES_MASK__VI 0x000003ffL -#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK__VI 0x03ff0000L -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK__VI 0x0c000000L -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK__VI 0x30000000L -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK__VI 0xc0000000L -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK__VI 0x00000004L -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK__VI 0x00000002L -#define SDMA0_CNTL__ATC_L1_ENABLE_MASK__VI 0x00000002L -#define SDMA0_CNTL__DRM_RESTORE_ENABLE_MASK__VI 0x00080000L -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK__VI 0x40000000L -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK__VI 0x00000020L -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK__VI 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK__VI 0x00080000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK__VI 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK__VI 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA0_MASK__VI 0x10000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA1_MASK__VI 0x20000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA2_MASK__VI 0x40000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA3_MASK__VI 0x80000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY0_MASK__VI 0x01000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY1_MASK__VI 0x02000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY2_MASK__VI 0x04000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY3_MASK__VI 0x08000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY0_MASK__VI 0x00100000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY1_MASK__VI 0x00200000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY2_MASK__VI 0x00400000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY3_MASK__VI 0x00800000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK__VI 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK__VI 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK__VI 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK__VI 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK__VI 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK__VI 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK__VI 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK__VI 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK__VI 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK__VI 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK__VI 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK__VI 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK__VI 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK__VI 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK__VI 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK__VI 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK__VI 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK__VI 0xfffc0000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK__VI 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK__VI 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK__VI 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK__VI 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD0_MASK__VI 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD1_MASK__VI 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD2_MASK__VI 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD3_MASK__VI 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD4_MASK__VI 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_OFFSET_MASK__VI 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_UNROLLKEY_MASK__VI 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK__VI 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK__VI 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK__VI 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK__VI 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK__VI 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK__VI 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK__VI 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK__VI 0xffffff80L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK__VI 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK__VI 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK__VI 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK__VI 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK__VI 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK__VI 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK__VI 0x00000020L -#define SDMA0_EDC_CONFIG__DIS_EDC_MASK__VI 0x00000002L -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK__VI 0x00000004L -#define SDMA0_EDC_CONFIG__WRITE_DIS_MASK__VI 0x00000001L -#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK__VI 0x000000fcL -#define SDMA0_FREEZE__F32_FREEZE_MASK__VI 0x00000040L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK__VI 0x00000200L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK__VI 0x00000400L -#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK__VI 0xfffffffcL -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK__VI 0x00000001L -#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK__VI 0xfffffffcL -#define SDMA0_GFX_DOORBELL__CAPTURED_MASK__VI 0x40000000L -#define SDMA0_GFX_DOORBELL__ENABLE_MASK__VI 0x10000000L -#define SDMA0_GFX_DOORBELL__OFFSET_MASK__VI 0x001fffffL -#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK__VI 0xffffffffL -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK__VI 0x00003fffL -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK__VI 0x00000100L -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK__VI 0x00000002L -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK__VI 0x00000001L -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK__VI 0x000000f0L -#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK__VI 0xffffffffL -#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK__VI 0xffffffffL -#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK__VI 0xffffffffL -#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK__VI 0xffffffffL -#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK__VI 0xffffffffL -#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK__VI 0xffffffffL -#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK__VI 0x00000001L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK__VI 0x00000004L -#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK__VI 0x00000002L -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK__VI 0x00000fffL -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK__VI 0x01ff0000L -#define SDMA0_ID__DEVICE_ID_MASK__VI 0x000000ffL -#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK__VI 0xfffffff8L -#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK__VI 0x00000002L -#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK__VI 0x00000004L -#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK__VI 0x00000001L -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_S1_MASK__VI 0x0003f000L -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_S2_MASK__VI 0x003c0000L -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK__VI 0x00000400L -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK__VI 0x00000200L -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK__VI 0x00000800L -#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK__VI 0x00010000L -#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK__VI 0x00020000L -#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK__VI 0xc0000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_ATOMIC_CNTL_MASK__VI 0x20000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK__VI 0x08000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK__VI 0x00000020L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK__VI 0x00000008L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK__VI 0x00000010L -#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK__VI 0x10000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK__VI 0x04000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK__VI 0x00040000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK__VI 0x00080000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK__VI 0x00000080L -#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK__VI 0x00000800L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK__VI 0x00100000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK__VI 0x00200000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK__VI 0x00000004L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK__VI 0x00001000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK__VI 0x00000400L -#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK__VI 0x00008000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK__VI 0x00000200L -#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK__VI 0x00004000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK__VI 0x00002000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK__VI 0x00000040L -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK__VI 0x00000001L -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK__VI 0x00000002L -#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK__VI 0x00800000L -#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK__VI 0x02000000L -#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK__VI 0x01000000L -#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK__VI 0x00400000L -#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK__VI 0xffffffe0L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK__VI 0x00000008L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK__VI 0x00000001L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK__VI 0x00000010L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK__VI 0x00000004L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK__VI 0x00000002L -#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK__VI 0x00000003L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK__VI 0x00000200L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK__VI 0x00000400L -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK__VI 0xfffffffcL -#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK__VI 0xffffffffL -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK__VI 0x00003fffL -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK__VI 0x00000100L -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK__VI 0x00000002L -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK__VI 0x00000001L -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK__VI 0x000000f0L -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK__VI 0xffffffffL -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK__VI 0xffffffffL -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK__VI 0xffffffffL -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK__VI 0xffffffffL -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK__VI 0xffffffffL -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK__VI 0xffffffffL -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK__VI 0x00000001L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK__VI 0x00000004L -#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK__VI 0x00000002L -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK__VI 0x00000fffL -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK__VI 0x01ff0000L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK__VI 0x00000200L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK__VI 0x00000400L -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK__VI 0xfffffffcL -#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK__VI 0xffffffffL -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK__VI 0x00003fffL -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK__VI 0x00000100L -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK__VI 0x00000002L -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK__VI 0x00000001L -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK__VI 0x000000f0L -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK__VI 0xffffffffL -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK__VI 0xffffffffL -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK__VI 0xffffffffL -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK__VI 0xffffffffL -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK__VI 0xffffffffL -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK__VI 0xffffffffL -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK__VI 0x00000001L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK__VI 0x00000004L -#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK__VI 0x00000002L -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK__VI 0x00000fffL -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK__VI 0x01ff0000L -#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK__VI 0x00000200L -#define SDMA0_STATUS2_REG__CMD_OP_MASK__VI 0xffff0000L -#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK__VI 0x0000fffcL -#define SDMA0_STATUS2_REG__ID_MASK__VI 0x00000003L -#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK__VI 0x00008000L -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK__VI 0x00100000L -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK__VI 0x00010000L -#define SDMA0_STATUS_REG__SRBM_IDLE_MASK__VI 0x00004000L -#define SDMA0_UCODE_ADDR__VALUE_MASK__VI 0x00001fffL -#define SDMA0_VERSION__VALUE_MASK__VI 0x0000ffffL -#define SDMA0_VF_ENABLE__VF_ENABLE_MASK__VI 0x00000001L -#define SDMA0_VIRT_RESET_REQ__PF_MASK__VI 0x80000000L -#define SDMA0_VIRT_RESET_REQ__VF_MASK__VI 0x0000ffffL -#define SDMA0_VM_CNTL__CMD_MASK__VI 0x0000000fL -#define SDMA0_VM_CTX_CNTL__PRIV_MASK__VI 0x00000001L -#define SDMA0_VM_CTX_CNTL__VMID_MASK__VI 0x000000f0L -#define SDMA0_VM_CTX_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA0_VM_CTX_LO__ADDR_MASK__VI 0xfffffffcL -#define SDMA1_ACTIVE_FCN_ID__VFID_MASK__VI 0x0000000fL -#define SDMA1_ACTIVE_FCN_ID__VF_MASK__VI 0x80000000L -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK__VI 0x80000000L -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK__VI 0x7fffffffL -#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK__VI 0xffffffffL -#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK__VI 0xffffffffL -#define SDMA1_BA_THRESHOLD__READ_THRES_MASK__VI 0x000003ffL -#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK__VI 0x03ff0000L -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK__VI 0x0c000000L -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK__VI 0x30000000L -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK__VI 0xc0000000L -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK__VI 0x00000004L -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK__VI 0x00000002L -#define SDMA1_CNTL__ATC_L1_ENABLE_MASK__VI 0x00000002L -#define SDMA1_CNTL__DRM_RESTORE_ENABLE_MASK__VI 0x00080000L -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK__VI 0x40000000L -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK__VI 0x00000020L -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK__VI 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK__VI 0xfff00000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK__VI 0x00080000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK__VI 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK__VI 0x00040000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK__VI 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK__VI 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK__VI 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK__VI 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK__VI 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK__VI 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK__VI 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK__VI 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK__VI 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK__VI 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK__VI 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK__VI 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK__VI 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK__VI 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK__VI 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK__VI 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK__VI 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK__VI 0xfffc0000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK__VI 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK__VI 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK__VI 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK__VI 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK__VI 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK__VI 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK__VI 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK__VI 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK__VI 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK__VI 0x0000007fL -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK__VI 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK__VI 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK__VI 0xffffff80L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK__VI 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK__VI 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK__VI 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK__VI 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK__VI 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK__VI 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK__VI 0x00000020L -#define SDMA1_EDC_CONFIG__DIS_EDC_MASK__VI 0x00000002L -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK__VI 0x00000004L -#define SDMA1_EDC_CONFIG__WRITE_DIS_MASK__VI 0x00000001L -#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK__VI 0x000000fcL -#define SDMA1_FREEZE__F32_FREEZE_MASK__VI 0x00000040L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK__VI 0x00000200L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK__VI 0x00000400L -#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK__VI 0xfffffffcL -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK__VI 0x00000001L -#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK__VI 0xfffffffcL -#define SDMA1_GFX_DOORBELL__CAPTURED_MASK__VI 0x40000000L -#define SDMA1_GFX_DOORBELL__ENABLE_MASK__VI 0x10000000L -#define SDMA1_GFX_DOORBELL__OFFSET_MASK__VI 0x001fffffL -#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK__VI 0xffffffffL -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK__VI 0x00003fffL -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK__VI 0x00000100L -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK__VI 0x00000002L -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK__VI 0x00000001L -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK__VI 0x000000f0L -#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK__VI 0xffffffffL -#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK__VI 0xffffffffL -#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK__VI 0xffffffffL -#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK__VI 0xffffffffL -#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK__VI 0xffffffffL -#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK__VI 0xffffffffL -#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK__VI 0x00000001L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK__VI 0x00000004L -#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK__VI 0x00000002L -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK__VI 0x00000fffL -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK__VI 0x01ff0000L -#define SDMA1_ID__DEVICE_ID_MASK__VI 0x000000ffL -#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK__VI 0xfffffff8L -#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK__VI 0x00000002L -#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK__VI 0x00000004L -#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK__VI 0x00000001L -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_S1_MASK__VI 0x0003f000L -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_S2_MASK__VI 0x003c0000L -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK__VI 0x00000400L -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK__VI 0x00000200L -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK__VI 0x00000800L -#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK__VI 0x00010000L -#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK__VI 0x00020000L -#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK__VI 0xc0000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_ATOMIC_CNTL_MASK__VI 0x20000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK__VI 0x08000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK__VI 0x00000020L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK__VI 0x00000008L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK__VI 0x00000010L -#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK__VI 0x10000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK__VI 0x04000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK__VI 0x00040000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK__VI 0x00080000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK__VI 0x00000080L -#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK__VI 0x00000800L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK__VI 0x00100000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK__VI 0x00200000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK__VI 0x00000004L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK__VI 0x00001000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK__VI 0x00000400L -#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK__VI 0x00008000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK__VI 0x00000200L -#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK__VI 0x00004000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK__VI 0x00002000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK__VI 0x00000040L -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK__VI 0x00000001L -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK__VI 0x00000002L -#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK__VI 0x03c00000L -#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK__VI 0xffffffe0L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK__VI 0x00000008L -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK__VI 0x00000001L -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK__VI 0x00000010L -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK__VI 0x00000004L -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK__VI 0x00000002L -#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK__VI 0x00000003L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK__VI 0x00000200L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK__VI 0x00000400L -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK__VI 0xfffffffcL -#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK__VI 0xffffffffL -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK__VI 0x00003fffL -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK__VI 0x00000100L -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK__VI 0x00000002L -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK__VI 0x00000001L -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK__VI 0x000000f0L -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK__VI 0xffffffffL -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK__VI 0xffffffffL -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK__VI 0xffffffffL -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK__VI 0xffffffffL -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK__VI 0xffffffffL -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK__VI 0xffffffffL -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK__VI 0x00000001L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK__VI 0x00000004L -#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK__VI 0x00000002L -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK__VI 0x00000fffL -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK__VI 0x01ff0000L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK__VI 0x00000200L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK__VI 0x00000400L -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK__VI 0xfffffffcL -#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK__VI 0xffffffffL -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK__VI 0x00003fffL -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK__VI 0x00000100L -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK__VI 0x00000002L -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK__VI 0x00000001L -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK__VI 0x000000f0L -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK__VI 0xffffffffL -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK__VI 0xffffffffL -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK__VI 0xffffffffL -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK__VI 0xffffffffL -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK__VI 0xffffffffL -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK__VI 0xffffffffL -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK__VI 0x00000001L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK__VI 0x00000004L -#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK__VI 0x00000002L -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK__VI 0x00000fffL -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK__VI 0x01ff0000L -#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK__VI 0x00000200L -#define SDMA1_STATUS2_REG__CMD_OP_MASK__VI 0xffff0000L -#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK__VI 0x0000fffcL -#define SDMA1_STATUS2_REG__ID_MASK__VI 0x00000003L -#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK__VI 0x00008000L -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK__VI 0x00100000L -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK__VI 0x00010000L -#define SDMA1_STATUS_REG__SRBM_IDLE_MASK__VI 0x00004000L -#define SDMA1_UCODE_ADDR__VALUE_MASK__VI 0x00001fffL -#define SDMA1_VERSION__VALUE_MASK__VI 0x0000ffffL -#define SDMA1_VF_ENABLE__VF_ENABLE_MASK__VI 0x00000001L -#define SDMA1_VIRT_RESET_REQ__PF_MASK__VI 0x80000000L -#define SDMA1_VIRT_RESET_REQ__VF_MASK__VI 0x0000ffffL -#define SDMA1_VM_CNTL__CMD_MASK__VI 0x0000000fL -#define SDMA1_VM_CTX_CNTL__PRIV_MASK__VI 0x00000001L -#define SDMA1_VM_CTX_CNTL__VMID_MASK__VI 0x000000f0L -#define SDMA1_VM_CTX_HI__ADDR_MASK__VI 0xffffffffL -#define SDMA1_VM_CTX_LO__ADDR_MASK__VI 0xfffffffcL -#define SEM_ACTIVE_FCN_ID__VFID_MASK__VI 0x0000000fL -#define SEM_ACTIVE_FCN_ID__VF_MASK__VI 0x80000000L -#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK__VI 0x00000080L -#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK__VI 0x00003000L -#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK__VI 0x00000004L -#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK__VI 0x00000018L -#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK__VI 0x00000f00L -#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK__VI 0x00000040L -#define SEM_CHICKEN_BITS__SIGNAL_FAIL_MASK__VI 0x00000020L -#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK__VI 0x0000001fL -#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK__VI 0xff000000L -#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK__VI 0x00ff0000L -#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK__VI 0xff000000L -#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK__VI 0x00ff0000L -#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK__VI 0xffffffffL -#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK__VI 0xffffffffL -#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK__VI 0x00000002L -#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK__VI 0x00000800L -#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK__VI 0x00000001L -#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK__VI 0x00000400L -#define SEM_PERFMON_CNTL__PERF_SEL0_MASK__VI 0x000003fcL -#define SEM_PERFMON_CNTL__PERF_SEL1_MASK__VI 0x000ff000L -#define SEM_STATUS__ATC_REQ_PENDING_MASK__VI 0x00008000L -#define SEM_STATUS__SWITCH_READY_MASK__VI 0x80000000L -#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK__VI 0x00004000L -#define SEM_VF_ENABLE__VALUE_MASK__VI 0x00000001L -#define SEM_VIRT_RESET_REQ__PF_MASK__VI 0x80000000L -#define SEM_VIRT_RESET_REQ__VF_MASK__VI 0x0000ffffL -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK__VI 0x00000ff0L -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK__VI 0x0000000fL -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK__VI 0x40000000L -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK__VI 0x80000000L -#define SH_MEM_CONFIG__ADDRESS_MODE_MASK__VI 0x00000003L -#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK__VI 0x00000018L -#define SH_MEM_CONFIG__APE1_ATC_MASK__VI 0x00000800L -#define SH_MEM_CONFIG__APE1_MTYPE_MASK__VI 0x00000700L -#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK__VI 0x000000e0L -#define SH_MEM_CONFIG__PRIVATE_ATC_MASK__VI 0x00000004L -#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK__VI 0x7e000000L -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEW_MASK__VI 0x00000200L -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEW_MASK__VI 0x00000200L -#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK__VI 0xffffffffL -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK__VI 0x000000ffL -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK__VI 0x0000ff00L -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK__VI 0x00ff0000L -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK__VI 0xff000000L -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK__VI 0x000000ffL -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK__VI 0x0000ff00L -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK__VI 0x00ff0000L -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK__VI 0xff000000L -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK__VI 0x000000ffL -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK__VI 0x0000ff00L -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK__VI 0x00ff0000L -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK__VI 0xff000000L -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK__VI 0x000000ffL -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK__VI 0x0000ff00L -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK__VI 0x00ff0000L -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK__VI 0xff000000L -#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK__VI 0x0000ff00L -#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK__VI 0x000000feL -#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK__VI 0x00070000L -#define SMBUS_CNTL0__THM_READY_MASK__VI 0x00100000L -#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK__VI 0x0001fe00L -#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK__VI 0x000001feL -#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK__VI 0x00000001L -#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK__VI 0x3fc00000L -#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK__VI 0x003fffffL -#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK__VI 0x3ff00000L -#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK__VI 0x000007e0L -#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK__VI 0x0000001fL -#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK__VI 0x000ff800L -#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK__VI 0x07ffe000L -#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK__VI 0x00001fffL -#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK__VI 0x00000100L -#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK__VI 0x00000001L -#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK__VI 0x7fffffffL -#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK__VI 0x80000000L -#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK__VI 0xffffffffL -#define SMBUS_UDID_CNTL2__ASF_MASK__VI 0x00000200L -#define SMBUS_UDID_CNTL2__IPMI_MASK__VI 0x00000400L -#define SMBUS_UDID_CNTL2__OEM_MASK__VI 0x00000100L -#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK__VI 0x00000001L -#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK__VI 0x000000f0L -#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK__VI 0x0000000eL -#define SMU_ACTIVE_FCN_ID__VFID_MASK__VI 0x0000000fL -#define SMU_ACTIVE_FCN_ID__VF_MASK__VI 0x80000000L -#define SMU_AUTH_INPUT_DATA__AUTH_START_ADDR_MASK__VI 0x7fffffffL -#define SMU_AUTH_INPUT_DATA__AUTO_START_MASK__VI 0x80000000L -#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK__VI 0x00000001L -#define SMU_CG_FPS_CNT__FPS_CNT_MASK__VI 0x000000ffL -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cmp_Unit0_Pstate_MASK__VI 0x00000007L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cmp_Unit1_Pstate_MASK__VI 0x00000070L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cur_Core_Vid_Pstate_MASK__VI 0x03800000L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cur_Nb_Vid_Pstate_MASK__VI 0x0c000000L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Pwr_Mgmt_Req_Act1_MASK__VI 0x40000000L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Pwr_Mgmt_Req_Act2_MASK__VI 0x80000000L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Pwr_Mgmt_Req_Wait_MASK__VI 0x10000000L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__RESERVED0_MASK__VI 0x007fff80L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__RESERVED1_MASK__VI 0x00000008L -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Vid_Transition_Act_MASK__VI 0x20000000L -#define SMU_DC_CNTL__CG_DCO_CLK_SLOW_MASK__VI 0x00000001L -#define SMU_DC_CNTL__DCO_CG_CLK_SLOW_ACK_MASK__VI 0x00000004L -#define SMU_DC_CNTL__DC_SMU_EVENT_INTERRUPT_MASK__VI 0x00000002L -#define SMU_DMA_ACTIVE_SAMPLE__SB_CORE_SEL_MASK__VI 0x0000f000L -#define SMU_IND_DATA_0__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_DATA_1__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_DATA_2__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_DATA_3__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_DATA_4__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_DATA_5__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_DATA_6__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_DATA_7__SMC_IND_DATA_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK__VI 0xffffffffL -#define SMU_MP1_RLC2MP_RESP__CONTENT_MASK__VI 0xffffffffL -#define SMU_MP1_SRBM2P_MSG_5__CONTENT_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_0__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_100__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_101__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_102__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_103__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_104__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_105__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_106__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_107__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_108__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_109__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_10__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_110__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_111__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_112__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_113__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_114__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_115__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_116__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_117__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_118__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_119__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_11__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_120__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_121__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_122__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_123__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_124__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_125__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_126__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_127__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_12__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_13__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_14__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_15__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_16__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_17__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_18__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_19__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_1__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_20__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_21__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_22__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_23__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_24__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_25__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_26__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_27__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_28__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_29__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_2__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_30__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_31__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_32__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_33__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_34__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_35__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_36__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_37__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_38__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_39__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_3__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_40__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_41__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_42__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_43__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_44__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_45__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_46__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_47__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_48__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_49__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_4__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_50__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_51__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_52__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_53__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_54__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_55__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_56__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_57__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_58__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_59__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_5__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_60__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_61__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_62__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_63__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_64__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_65__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_66__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_67__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_68__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_69__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_6__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_70__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_71__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_72__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_73__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_74__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_75__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_76__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_77__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_78__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_79__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_7__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_80__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_81__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_82__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_83__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_84__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_85__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_86__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_87__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_88__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_89__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_8__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_90__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_91__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_92__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_93__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_94__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_95__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_96__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_97__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_98__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_99__DATA_MASK__VI 0xffffffffL -#define SMU_PM_STATUS_9__DATA_MASK__VI 0xffffffffL -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_COMPUTE_UNIT_0__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_COMPUTE_UNIT_0__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_COMPUTE_UNIT_0__RESERVED0_MASK__VI 0xe0000000L -#define SMU_PSTATE_COMPUTE_UNIT_0__RESERVED1_MASK__VI 0x07fe0000L -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_COMPUTE_UNIT_1__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_COMPUTE_UNIT_1__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_COMPUTE_UNIT_1__RESERVED0_MASK__VI 0xe0000000L -#define SMU_PSTATE_COMPUTE_UNIT_1__RESERVED1_MASK__VI 0x07fe0000L -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_0__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_0__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_0__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_0__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_0__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_1__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_1__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_1__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_1__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_1__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_2__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_2__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_2__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_2__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_2__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_3__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_3__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_3__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_3__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_3__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_4__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_4__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_4__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_4__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_4__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_5__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_5__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_5__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_5__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_5__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_6__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_6__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_6__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_6__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_6__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Did_MASK__VI 0x000001c0L -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Fid_MASK__VI 0x0000003fL -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Vid7_MASK__VI 0x10000000L -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Vid_6_0_MASK__VI 0x0000fe00L -#define SMU_PSTATE_CONFIGURATION_7__IddDiv_MASK__VI 0x06000000L -#define SMU_PSTATE_CONFIGURATION_7__IddValue_MASK__VI 0x01fe0000L -#define SMU_PSTATE_CONFIGURATION_7__Nb_Pstate_MASK__VI 0x00010000L -#define SMU_PSTATE_CONFIGURATION_7__Pstate_En_MASK__VI 0x08000000L -#define SMU_PSTATE_CONFIGURATION_7__RESERVED_MASK__VI 0xe0000000L -#define SMU_PSTATE_CONFIGURATION__Priority_Selector_MASK__VI 0x00000001L -#define SMU_PSTATE_CONFIGURATION__Pstate_CC6_Exit_MASK__VI 0x00000004L -#define SMU_PSTATE_CONFIGURATION__Pstate_Req_Exit_MASK__VI 0x00000002L -#define SMU_PSTATE_CONFIGURATION__RESERVED_MASK__VI 0xfffffff8L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit0_Smu_Pstate_Active_MASK__VI 0x00000002L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit0_Smu_Pstate_Request_MASK__VI 0x00000001L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit1_Smu_Pstate_Active_MASK__VI 0x00000008L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit1_Smu_Pstate_Request_MASK__VI 0x00000004L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit2_Smu_Pstate_Active_MASK__VI 0x00000020L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit2_Smu_Pstate_Request_MASK__VI 0x00000010L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit3_Smu_Pstate_Active_MASK__VI 0x00000080L -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit3_Smu_Pstate_Request_MASK__VI 0x00000040L -#define SMU_PSTATE_CONTROL_AND_STATUS__RESERVED_MASK__VI 0xffffff00L -#define SMU_RLC_RESPONSE__RESP_MASK__VI 0xffffffffL -#define SMU_TCON_0__TCON_DATA_MASK__VI 0x00000fffL -#define SMU_TP_SHORT_INIT__RESERVED_MASK__VI 0xffffff00L -#define SMU_TP_SHORT_INIT__TP_SHORT_INIT_MASK__VI 0x000000ffL -#define SMU_UVD_CNTL__UVD_CG_CLK_SWITCH_ACK_MASK__VI 0x00000001L -#define SMU_VCE_CNTL__VCE_CG_CLK_SLOW_ACK_MASK__VI 0x00000001L -#define SMU_VCE_CNTL__VCE_CG_CLK_SWITCH_ACK_MASK__VI 0x00000002L -#define SMU_VF_ENABLE__VF_ENABLE_MASK__VI 0x00000001L -#define SMU_VIRT_RESET_REQ__PF_MASK__VI 0x80000000L -#define SMU_VIRT_RESET_REQ__VF_MASK__VI 0x0000ffffL -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK__VI 0x00000004L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK__VI 0x00000002L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK__VI 0x40000000L -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK__VI 0x00000001L -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK__VI 0x80000000L -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK__VI 0x000000f0L -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK__VI 0x0000000fL -#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK__VI 0x00000004L -#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK__VI 0x00000001L -#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK__VI 0x00000002L -#define SPI_DSM_CNTL__UNUSED_MASK__VI 0xfffffff8L -#define SPI_EDC_CNT__SED_MASK__VI 0x000000ffL -#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK__VI 0x0001fffeL -#define SPI_GFX_CNTL__RESET_COUNTS_MASK__VI 0x00000001L -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK__VI 0x01000000L -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK__VI 0x02000000L -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK__VI 0x00600000L -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK__VI 0x00080000L -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK__VI 0x00800000L -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK__VI 0x00100000L -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK__VI 0x00078000L -#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK__VI 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK__VI 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK__VI 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK__VI 0x00007000L -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK__VI 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK__VI 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK__VI 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK__VI 0x01000000L -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK__VI 0x0000fffeL -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK__VI 0x01000000L -#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK__VI 0xfc000000L -#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK__VI 0xfc000000L -#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK__VI 0x0000fc00L -#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK__VI 0xfc000000L -#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK__VI 0x00400000L -#define SPI_START_PHASE__SGPR_START_PHASE_MASK__VI 0x0000000cL -#define SPI_START_PHASE__VGPR_START_PHASE_MASK__VI 0x00000003L -#define SPI_START_PHASE__WAVE_START_PHASE_MASK__VI 0x00000030L -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK__VI 0x003e0000L -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK__VI 0x07c00000L -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK__VI 0x0001f000L -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK__VI 0x00000f80L -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK__VI 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK__VI 0x003e0000L -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK__VI 0x07c00000L -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK__VI 0x0001f000L -#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK__VI 0x00000f80L -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK__VI 0x0000007fL -#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6_MASK__VI 0x0000fffcL -#define SPMI_CONFIG0_0__SPMI_ENABLE_MASK__VI 0x00000001L -#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK__VI 0x07c00000L -#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK__VI 0x003e0000L -#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK__VI 0x0000007cL -#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES_MASK__VI 0x00000f80L -#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES_MASK__VI 0x0001f000L -#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE_MASK__VI 0x0000ffe0L -#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK__VI 0x0000001fL -#define SPMI_FORCE_CLOCK_GATERS__CLOCK_GATER_0_FORCE_MASK__VI 0x00000001L -#define SPMI_FORCE_CLOCK_GATERS__SRAM_CLOCK_GATER_FORCE_MASK__VI 0x00000100L -#define SPMI_RESET__SYNC_RESET_MASK__VI 0x80000000L -#define SPMI_SPARE_EX__SPARE_DATA_EX_MASK__VI 0xffffffffL -#define SPMI_SPARE__SPARE_DATA_MASK__VI 0xffffffffL -#define SPMI_SRAM_CLK_GATER__SRAM_CLK_GATER_EN_MASK__VI 0x00000001L -#define SPMI_SRAM_CLK_GATER__SRAM_CLK_GATER_TIMER_MASK__VI 0x000007feL -#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK__VI 0x00ff0000L -#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK__VI 0x000000ffL -#define SQC_CACHES__COMPLETE_MASK__VI 0x00010000L -#define SQC_CACHES__INVALIDATE_MASK__VI 0x00000004L -#define SQC_CACHES__TARGET_DATA_MASK__VI 0x00000002L -#define SQC_CACHES__TARGET_INST_MASK__VI 0x00000001L -#define SQC_CACHES__VOL_MASK__VI 0x00000010L -#define SQC_CACHES__WRITEBACK_MASK__VI 0x00000008L -#define SQC_CONFIG__EVICT_LRU_MASK__VI 0x00003000L -#define SQC_CONFIG__FORCE_1_BANK_MASK__VI 0x00008000L -#define SQC_CONFIG__FORCE_2_BANK_MASK__VI 0x00004000L -#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK__VI 0x00ff0000L -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK__VI 0x00020000L -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK__VI 0x00100000L -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK__VI 0x00800000L -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK__VI 0x04000000L -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK__VI 0x20000000L -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK__VI 0x00000004L -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK__VI 0x00000020L -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK__VI 0x00000100L -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK__VI 0x00000800L -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK__VI 0x00004000L -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK__VI 0x00018000L -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK__VI 0x000c0000L -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK__VI 0x00600000L -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK__VI 0x03000000L -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK__VI 0x18000000L -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK__VI 0x00000003L -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK__VI 0x00000018L -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK__VI 0x000000c0L -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK__VI 0x00000600L -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK__VI 0x00003000L -#define SQC_EDC_CNT__DATA_DED_MASK__VI 0xff000000L -#define SQC_EDC_CNT__DATA_SEC_MASK__VI 0x00ff0000L -#define SQC_EDC_CNT__INST_DED_MASK__VI 0x0000ff00L -#define SQC_EDC_CNT__INST_SEC_MASK__VI 0x000000ffL -#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK__VI 0x00100000L -#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK__VI 0x00080000L -#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK__VI 0x00040000L -#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK__VI 0x01800000L -#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK__VI 0x00600000L -#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK__VI 0x08000000L -#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK__VI 0x04000000L -#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK__VI 0x02000000L -#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK__VI 0xc0000000L -#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK__VI 0x30000000L -#define SQC_GATCL1_CNTL__RESERVED_MASK__VI 0x0003ffffL -#define SQC_WRITEBACK__DIRTY_MASK__VI 0x00000002L -#define SQC_WRITEBACK__DWB_MASK__VI 0x00000001L -#define SQ_CMD__DATA_MASK__VI 0x00000700L -#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK__VI 0x00000400L -#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK__VI 0x00000200L -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK__VI 0x00020000L -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK__VI 0x00010000L -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK__VI 0x00040000L -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK__VI 0x00180000L -#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK__VI 0x01e00000L -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK__VI 0x000003f0L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK__VI 0x00040000L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK__VI 0x00200000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK__VI 0x00010000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK__VI 0x00020000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK__VI 0x00080000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK__VI 0x00100000L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK__VI 0x00000100L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK__VI 0x00000200L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK__VI 0x01000000L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK__VI 0x02000000L -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK__VI 0x00000400L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK__VI 0x00000004L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK__VI 0x00000008L -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK__VI 0x04000000L -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK__VI 0x00000001L -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK__VI 0x00000002L -#define SQ_DS_0__GDS_MASK__SI__CI 0x00020000L -#define SQ_DS_0__GDS_MASK__VI 0x00010000L -#define SQ_DS_0__OP_MASK__SI__CI 0x03fc0000L -#define SQ_DS_0__OP_MASK__VI 0x01fe0000L -#define SQ_EDC_DED_CNT__LDS_DED_MASK__VI 0x000000ffL -#define SQ_EDC_DED_CNT__SGPR_DED_MASK__VI 0x0000ff00L -#define SQ_EDC_DED_CNT__VGPR_DED_MASK__VI 0x00ff0000L -#define SQ_EDC_INFO__SIMD_ID_MASK__VI 0x00000030L -#define SQ_EDC_INFO__SOURCE_MASK__VI 0x000001c0L -#define SQ_EDC_INFO__VM_ID_MASK__VI 0x00001e00L -#define SQ_EDC_INFO__WAVE_ID_MASK__VI 0x0000000fL -#define SQ_EDC_SEC_CNT__LDS_SEC_MASK__VI 0x000000ffL -#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK__VI 0x0000ff00L -#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK__VI 0x00ff0000L -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK__VI 0x00400000L -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK__VI 0x00800000L -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK__VI 0x00200000L -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK__VI 0x0f000000L -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK__VI 0xf0000000L -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK__VI 0xffffffffL -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK__VI 0x80000000L -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK__VI 0x80000000L -#define SQ_M0_GPR_IDX_WORD__INDEX_MASK__VI 0x000000ffL -#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK__VI 0x00008000L -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK__VI 0x00001000L -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK__VI 0x00002000L -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK__VI 0x00004000L -#define SQ_MIMG_1__D16_MASK__VI 0x80000000L -#define SQ_MTBUF_0__OP_MASK__SI__CI 0x00070000L -#define SQ_MTBUF_0__OP_MASK__VI 0x00078000L -#define SQ_MUBUF_0__SLC_MASK__VI 0x00020000L -#define SQ_SMEM_0__ENCODING_MASK__VI 0xfc000000L -#define SQ_SMEM_0__GLC_MASK__VI 0x00010000L -#define SQ_SMEM_0__IMM_MASK__VI 0x00020000L -#define SQ_SMEM_0__OP_MASK__VI 0x03fc0000L -#define SQ_SMEM_0__SBASE_MASK__VI 0x0000003fL -#define SQ_SMEM_0__SDATA_MASK__VI 0x00001fc0L -#define SQ_SMEM_1__OFFSET_MASK__VI 0x000fffffL -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK__VI 0xffffffffL -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK__SI__CI 0x0000f000L -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK__VI 0x0000f800L -#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK__VI 0x00008000L -#define SQ_VOP3_0_SDST_ENC__OP_MASK__SI__CI 0x03fe0000L -#define SQ_VOP3_0_SDST_ENC__OP_MASK__VI 0x03ff0000L -#define SQ_VOP3_0__CLAMP_MASK__SI__CI 0x00000800L -#define SQ_VOP3_0__CLAMP_MASK__VI 0x00008000L -#define SQ_VOP3_0__OP_MASK__SI__CI 0x03fe0000L -#define SQ_VOP3_0__OP_MASK__VI 0x03ff0000L -#define SQ_VOP_DPP__BANK_MASK_MASK__VI 0x0f000000L -#define SQ_VOP_DPP__BOUND_CTRL_MASK__VI 0x00080000L -#define SQ_VOP_DPP__DPP_CTRL_MASK__VI 0x0001ff00L -#define SQ_VOP_DPP__ROW_MASK_MASK__VI 0xf0000000L -#define SQ_VOP_DPP__SRC0_ABS_MASK__VI 0x00200000L -#define SQ_VOP_DPP__SRC0_MASK__VI 0x000000ffL -#define SQ_VOP_DPP__SRC0_NEG_MASK__VI 0x00100000L -#define SQ_VOP_DPP__SRC1_ABS_MASK__VI 0x00800000L -#define SQ_VOP_DPP__SRC1_NEG_MASK__VI 0x00400000L -#define SQ_VOP_SDWA__CLAMP_MASK__VI 0x00002000L -#define SQ_VOP_SDWA__DST_SEL_MASK__VI 0x00000700L -#define SQ_VOP_SDWA__DST_UNUSED_MASK__VI 0x00001800L -#define SQ_VOP_SDWA__SRC0_ABS_MASK__VI 0x00200000L -#define SQ_VOP_SDWA__SRC0_MASK__VI 0x000000ffL -#define SQ_VOP_SDWA__SRC0_NEG_MASK__VI 0x00100000L -#define SQ_VOP_SDWA__SRC0_SEL_MASK__VI 0x00070000L -#define SQ_VOP_SDWA__SRC0_SEXT_MASK__VI 0x00080000L -#define SQ_VOP_SDWA__SRC1_ABS_MASK__VI 0x20000000L -#define SQ_VOP_SDWA__SRC1_NEG_MASK__VI 0x10000000L -#define SQ_VOP_SDWA__SRC1_SEL_MASK__VI 0x07000000L -#define SQ_VOP_SDWA__SRC1_SEXT_MASK__VI 0x08000000L -#define SQ_WAVE_IB_DBG0__ECC_ST_MASK__SI__CI 0x00c00000L -#define SQ_WAVE_IB_DBG0__ECC_ST_MASK__VI 0x03000000L -#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK__SI__CI 0x06000000L -#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK__VI 0x18000000L -#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK__SI__CI 0x00070000L -#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK__VI 0x000f0000L -#define SQ_WAVE_IB_DBG0__IS_HYB_MASK__SI__CI 0x01000000L -#define SQ_WAVE_IB_DBG0__IS_HYB_MASK__VI 0x04000000L -#define SQ_WAVE_IB_DBG0__KILL_MASK__VI 0x20000000L -#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK__SI__CI 0x00380000L -#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK__VI 0x00f00000L -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK__VI 0x40000000L -#define SQ_WAVE_IB_DBG1__IXNACK_MASK__VI 0x00000001L -#define SQ_WAVE_IB_DBG1__QCNT_MASK__VI 0x00000f00L -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK__VI 0x00000004L -#define SQ_WAVE_IB_DBG1__XCNT_MASK__VI 0x000000f0L -#define SQ_WAVE_IB_DBG1__XNACK_MASK__VI 0x00000002L -#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK__VI 0x00008000L -#define SQ_WAVE_IB_STS__RCNT_MASK__VI 0x000f0000L -#define SQ_WAVE_MODE__GPR_IDX_EN_MASK__VI 0x08000000L -#define SQ_WAVE_PC_HI__PC_HI_MASK__SI__CI 0x000000ffL -#define SQ_WAVE_PC_HI__PC_HI_MASK__VI 0x0000ffffL -#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK__VI 0x00400000L -#define SQ_WAVE_STATUS__USER_PRIO_MASK__VI 0x00000018L -#define SQ_WAVE_TRAPSTS__SAVECTX_MASK__VI 0x00000400L -#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK__VI 0x0000ffffL -#define SQ_WREXEC_EXEC_HI__ATC_MASK__VI 0x08000000L -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK__VI 0x04000000L -#define SQ_WREXEC_EXEC_HI__MSB_MASK__VI 0x80000000L -#define SQ_WREXEC_EXEC_HI__MTYPE_MASK__VI 0x70000000L -#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK__VI 0xffffffffL -#define SRBM_BIF_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_BIF_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_BIF_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_BIF_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_BIF_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_BIF_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_BIF_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_BIF_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_BIF_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_BIF_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_BIF_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_BIF_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_BIF_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_BIF_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_BIF_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_BIF_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_BIF_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_BIF_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_BIF_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_BIF_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_BIF_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_BIF_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_BIF_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_BIF_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_BIF_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_BIF_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_BIF_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_CAM_INDEX__CAM_INDEX_MASK__SI__CI 0x00000007L -#define SRBM_CAM_INDEX__CAM_INDEX_MASK__VI 0x00000003L -#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT_MASK__VI 0x00080000L -#define SRBM_CNTL__REPORT_LAST_RDERR_MASK__VI 0x00040000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_CPU_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_CPU_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_CPU_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_CPU_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_CPU_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_CPU_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_CPU_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_CPU_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_CPU_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_CPU_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_CPU_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_CPU_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_CPU_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_CPU_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_CPU_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_CPU_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_CPU_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_CPU_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_CPU_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_CPU_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_CPU_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_CPU_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_CPU_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_CPU_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_CPU_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_CPU_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK__VI 0x00000001L -#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK__VI 0x00000002L -#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK__VI 0x80000000L -#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK__VI 0x00001000L -#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK__VI 0x00000008L -#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK__VI 0x40000000L -#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK__VI 0x20000000L -#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK__VI 0x00000400L -#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK__VI 0x00000400L -#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK__VI 0x00000800L -#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK__VI 0x0000ffffL -#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK__VI 0x00010000L -#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK__VI 0xffffffffL -#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK__VI 0x0000ffffL -#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK__VI 0x00010000L -#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK__VI 0xffffffffL -#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK__VI 0x0003fffcL -#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK__VI 0x00f00000L -#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK__VI 0x00080000L -#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK__VI 0x80000000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK__VI 0x00000002L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK__VI 0x00100000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK__VI 0x00000001L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK__VI 0x00008000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_DRM_MASK__VI 0x00000010L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK__VI 0x00001000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK__VI 0x00010000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK__VI 0x00004000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK__VI 0x00040000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK__VI 0x00000008L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK__VI 0x00000004L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK__VI 0x00000200L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK__VI 0x00000100L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK__VI 0x00000080L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK__VI 0x00000040L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK__VI 0x00080000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK__VI 0x00002000L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK__VI 0x00000020L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK__VI 0x00000400L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK__VI 0x00000800L -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK__VI 0x00020000L -#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK__VI 0x04000000L -#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK__VI 0x01000000L -#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK__VI 0x02000000L -#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK__VI 0x10000000L -#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK__VI 0x08000000L -#define SRBM_GFX_CNTL_DATA__MEID_MASK__VI 0x0000000cL -#define SRBM_GFX_CNTL_DATA__PIPEID_MASK__VI 0x00000003L -#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK__VI 0x00000700L -#define SRBM_GFX_CNTL_DATA__VMID_MASK__VI 0x000000f0L -#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK__VI 0x0000000fL -#define SRBM_GRBM_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_GRBM_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_GRBM_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_INT_ACK__RAERR_INT_ACK_MASK__VI 0x00000002L -#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK__VI 0x00000002L -#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK__VI 0x00000002L -#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK__VI 0x00001f00L -#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK__VI 0x0000000fL -#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_PEER_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_PEER_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_PEER_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_PEER_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_PEER_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_PEER_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_PEER_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_PEER_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_PEER_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_PEER_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_PEER_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_PEER_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_PEER_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_PEER_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_PEER_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_PEER_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_PEER_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_PEER_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_PEER_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_PEER_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_PEER_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_PEER_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_PEER_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_PEER_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_PEER_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_PEER_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_PEER_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_PF_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_PF_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_PF_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_PF_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_PF_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_PF_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_PF_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_PF_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_PF_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_PF_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_PF_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_PF_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_PF_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_PF_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_PF_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_PF_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_PF_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_PF_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_PF_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_PF_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_PF_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_PF_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_PF_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_PF_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_PF_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_PF_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_PF_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_PF_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_PF_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_PF_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_PF_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_PF_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_PF_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_PF_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_PF_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_PF_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_PF_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_PF_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_PF_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_PF_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_PF_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_PF_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_PF_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_PF_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_PF_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_PF_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_PF_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_PF_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_PF_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_PF_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_PF_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_PF_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_PF_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_PF_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_PF_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_PF_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_READ_CNTL__READ_TIMEOUT_MASK__VI 0x00ffffffL -#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK__VI 0x00000001L -#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK__VI 0x00000002L -#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK__VI 0x00000004L -#define SRBM_READ_ERROR2__READ_VFID_MASK__VI 0x0f000000L -#define SRBM_READ_ERROR2__READ_VF_MASK__VI 0x00800000L -#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK__VI 0x00800000L -#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK__VI 0x08000000L -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK__VI 0x00080000L -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK__VI 0x00040000L -#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK__VI 0x00100000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SMU_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_SMU_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_SMU_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_SMU_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_SMU_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_SMU_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_SMU_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_SMU_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_SMU_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_SMU_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_SMU_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_SMU_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_SMU_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_SMU_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_SMU_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_SMU_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_SMU_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_SMU_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_SMU_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_SMU_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_SMU_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_SMU_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_SMU_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_SMU_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_SMU_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_SMU_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_SMU_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK__VI 0x00000001L -#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK__VI 0x00002000L -#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK__VI 0x00000010L -#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK__VI 0x20000000L -#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK__VI 0x40000000L -#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK__VI 0x00800000L -#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK__VI 0x08000000L -#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK__VI 0x10000000L -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK__VI 0x00000008L -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK__VI 0x00000004L -#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK__VI 0x01000000L -#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK__VI 0x80000000L -#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK__VI 0x00080000L -#define SRBM_STATUS2__ISP_BUSY_MASK__VI 0x00002000L -#define SRBM_STATUS2__ISP_RQ_PENDING_MASK__VI 0x00080000L -#define SRBM_STATUS2__ODE_BUSY_MASK__VI 0x00008000L -#define SRBM_STATUS2__SAMSCP_BUSY_MASK__VI 0x00001000L -#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK__VI 0x00040000L -#define SRBM_STATUS2__SDMA2_BUSY_MASK__VI 0x00000400L -#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK__VI 0x00010000L -#define SRBM_STATUS2__SDMA3_BUSY_MASK__VI 0x00000800L -#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK__VI 0x00020000L -#define SRBM_STATUS2__VCE0_BUSY_MASK__VI 0x00000080L -#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK__VI 0x00000008L -#define SRBM_STATUS2__VCE1_BUSY_MASK__VI 0x00004000L -#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK__VI 0x00100000L -#define SRBM_STATUS2__VP8_BUSY_MASK__VI 0x00000010L -#define SRBM_STATUS3__MCC0_BUSY_MASK__VI 0x00000001L -#define SRBM_STATUS3__MCC1_BUSY_MASK__VI 0x00000002L -#define SRBM_STATUS3__MCC2_BUSY_MASK__VI 0x00000004L -#define SRBM_STATUS3__MCC3_BUSY_MASK__VI 0x00000008L -#define SRBM_STATUS3__MCC4_BUSY_MASK__VI 0x00000010L -#define SRBM_STATUS3__MCC5_BUSY_MASK__VI 0x00000020L -#define SRBM_STATUS3__MCC6_BUSY_MASK__VI 0x00000040L -#define SRBM_STATUS3__MCC7_BUSY_MASK__VI 0x00000080L -#define SRBM_STATUS3__MCD0_BUSY_MASK__VI 0x00000100L -#define SRBM_STATUS3__MCD1_BUSY_MASK__VI 0x00000200L -#define SRBM_STATUS3__MCD2_BUSY_MASK__VI 0x00000400L -#define SRBM_STATUS3__MCD3_BUSY_MASK__VI 0x00000800L -#define SRBM_STATUS3__MCD4_BUSY_MASK__VI 0x00001000L -#define SRBM_STATUS3__MCD5_BUSY_MASK__VI 0x00002000L -#define SRBM_STATUS3__MCD6_BUSY_MASK__VI 0x00004000L -#define SRBM_STATUS3__MCD7_BUSY_MASK__VI 0x00008000L -#define SRBM_STATUS3__SECURE_MODE_MASK__VI 0x00010000L -#define SRBM_STATUS__GCATCL2_BUSY_MASK__VI 0x00200000L -#define SRBM_STATUS__OSATCL2_BUSY_MASK__VI 0x00400000L -#define SRBM_STATUS__SAMMSP_BUSY_MASK__VI 0x00100000L -#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK__VI 0x00000004L -#define SRBM_STATUS__VMC1_BUSY_MASK__VI 0x00002000L -#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_TST_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_TST_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_TST_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_TST_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_TST_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_TST_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_TST_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_TST_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_TST_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_TST_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_TST_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_TST_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_TST_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_TST_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_TST_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_TST_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_TST_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_TST_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_TST_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_TST_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_TST_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_TST_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_TST_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_TST_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_TST_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_TST_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_TST_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_TST_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_TST_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_TST_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_TST_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_TST_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_TST_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_TST_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_TST_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_TST_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_TST_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_TST_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_TST_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_TST_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_TST_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_TST_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_TST_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_TST_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_TST_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_TST_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_TST_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_TST_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_TST_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_TST_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_TST_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_TST_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_TST_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_TST_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_TST_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_TST_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_TST_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK__VI 0x0000ffffL -#define SRBM_VF_ENABLE__VF_ENABLE_MASK__VI 0x00000001L -#define SRBM_VF_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_VF_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_VF_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_VF_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_VF_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_VF_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_VF_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_VF_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_VF_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_VF_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_VF_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_VF_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_VF_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_VF_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_VF_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_VF_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_VF_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_VF_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_VF_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_VF_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_VF_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_VF_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_VF_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_VF_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_VF_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_VF_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_VF_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_VF_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_VF_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_VF_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_VF_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_VF_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_VF_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_VF_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_VF_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_VF_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_VF_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_VF_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_VF_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_VF_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_VF_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_VF_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_VF_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_VF_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_VF_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_VF_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_VF_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_VF_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_VF_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_VF_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_VF_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_VF_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_VF_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_VF_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_VF_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_VF_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_VF_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE0_MASK__VI 0x00000001L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE10_MASK__VI 0x00000400L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE11_MASK__VI 0x00000800L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE12_MASK__VI 0x00001000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE13_MASK__VI 0x00002000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE14_MASK__VI 0x00004000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE15_MASK__VI 0x00008000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE16_MASK__VI 0x00010000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE17_MASK__VI 0x00020000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE18_MASK__VI 0x00040000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE19_MASK__VI 0x00080000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE1_MASK__VI 0x00000002L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE20_MASK__VI 0x00100000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE21_MASK__VI 0x00200000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE22_MASK__VI 0x00400000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE23_MASK__VI 0x00800000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE24_MASK__VI 0x01000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE25_MASK__VI 0x02000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE26_MASK__VI 0x04000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE27_MASK__VI 0x08000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE28_MASK__VI 0x10000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE29_MASK__VI 0x20000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE2_MASK__VI 0x00000004L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE30_MASK__VI 0x40000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE31_MASK__VI 0x80000000L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE3_MASK__VI 0x00000008L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE4_MASK__VI 0x00000010L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE5_MASK__VI 0x00000020L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE6_MASK__VI 0x00000040L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE7_MASK__VI 0x00000080L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE8_MASK__VI 0x00000100L -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE9_MASK__VI 0x00000200L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE32_MASK__VI 0x00000001L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE33_MASK__VI 0x00000002L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE34_MASK__VI 0x00000004L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE35_MASK__VI 0x00000008L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE36_MASK__VI 0x00000010L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE37_MASK__VI 0x00000020L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE38_MASK__VI 0x00000040L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE39_MASK__VI 0x00000080L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE40_MASK__VI 0x00000100L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE41_MASK__VI 0x00000200L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE42_MASK__VI 0x00000400L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE43_MASK__VI 0x00000800L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE44_MASK__VI 0x00001000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE45_MASK__VI 0x00002000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE46_MASK__VI 0x00004000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE47_MASK__VI 0x00008000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE48_MASK__VI 0x00010000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE49_MASK__VI 0x00020000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE50_MASK__VI 0x00040000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE51_MASK__VI 0x00080000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE52_MASK__VI 0x00100000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE53_MASK__VI 0x00200000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE54_MASK__VI 0x00400000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE55_MASK__VI 0x00800000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE56_MASK__VI 0x01000000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE57_MASK__VI 0x02000000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE58_MASK__VI 0x04000000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE59_MASK__VI 0x08000000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE60_MASK__VI 0x10000000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE61_MASK__VI 0x20000000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE62_MASK__VI 0x40000000L -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE63_MASK__VI 0x80000000L -#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK__VI 0x00000001L -#define SRBM_VIRT_RESET_REQ__PF_MASK__VI 0x80000000L -#define SRBM_VIRT_RESET_REQ__VF_MASK__VI 0x0000ffffL -#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK__VI 0x00001f00L -#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK__VI 0x0000000fL -#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK__VI 0xffff0000L -#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK__VI 0x0000ffffL -#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK__VI 0x00020000L -#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK__VI 0x00400000L -#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK__VI 0x00040000L -#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK__VI 0x00010000L -#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK__VI 0x00100000L -#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK__VI 0x00080000L -#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK__VI 0x00200000L -#define SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK__VI 0x00008000L -#define SWRST_COMMAND_1__CMDCFGEN_MASK__VI 0x20000000L -#define SWRST_COMMAND_1__RESETCPM_MASK__VI 0x00008000L -#define SWRST_COMMAND_1__RESETHLTR_MASK__VI 0x00004000L -#define SWRST_COMMAND_1__RESETIMPARB0_MASK__VI 0x00100000L -#define SWRST_COMMAND_1__RESETIMPARB1_MASK__VI 0x00200000L -#define SWRST_COMMAND_1__RESETLANEMUX_MASK__VI 0x00000004L -#define SWRST_COMMAND_1__RESETLC_MASK__VI 0x00000040L -#define SWRST_COMMAND_1__RESETMNTR_MASK__VI 0x00002000L -#define SWRST_COMMAND_1__RESETPHY0_MASK__VI 0x01000000L -#define SWRST_COMMAND_1__RESETPHY1_MASK__VI 0x02000000L -#define SWRST_COMMAND_1__RESETPIF0_MASK__VI 0x00010000L -#define SWRST_COMMAND_1__RESETPIF1_MASK__VI 0x00020000L -#define SWRST_COMMAND_1__RESETPRBS_MASK__VI 0x00000002L -#define SWRST_COMMAND_1__RESETSRBM0_MASK__VI 0x00000010L -#define SWRST_COMMAND_1__RESETSRBM1_MASK__VI 0x00000020L -#define SWRST_COMMAND_1__RESETWRAPREGS_MASK__VI 0x00000008L -#define SWRST_COMMAND_1__SWITCHCLK_MASK__VI 0x00000001L -#define SWRST_COMMAND_1__SYNCIDLEPIF0_MASK__VI 0x00000100L -#define SWRST_COMMAND_1__SYNCIDLEPIF1_MASK__VI 0x00000200L -#define SWRST_COMMAND_1__TOGGLESTRAP_MASK__VI 0x10000000L -#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK__VI 0x00000002L -#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK__VI 0x00000001L -#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK__VI 0x00010000L -#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK__VI 0x00020000L -#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK__VI 0x00020000L -#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK__VI 0x00400000L -#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK__VI 0x00040000L -#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK__VI 0x00010000L -#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK__VI 0x00100000L -#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK__VI 0x00080000L -#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK__VI 0x00200000L -#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK__VI 0x00008000L -#define SWRST_CONTROL_1__CMDCFG_RCEN_MASK__VI 0x20000000L -#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK__VI 0x00008000L -#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK__VI 0x00004000L -#define SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK__VI 0x00100000L -#define SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK__VI 0x00200000L -#define SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK__VI 0x00000004L -#define SWRST_CONTROL_1__RESETLC_RCEN_MASK__VI 0x00000040L -#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK__VI 0x00002000L -#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK__VI 0x01000000L -#define SWRST_CONTROL_1__RESETPHY1_RCEN_MASK__VI 0x02000000L -#define SWRST_CONTROL_1__RESETPIF0_RCEN_MASK__VI 0x00010000L -#define SWRST_CONTROL_1__RESETPIF1_RCEN_MASK__VI 0x00020000L -#define SWRST_CONTROL_1__RESETPRBS_RCEN_MASK__VI 0x00000002L -#define SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK__VI 0x00000010L -#define SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK__VI 0x00000020L -#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK__VI 0x00000008L -#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK__VI 0x10000000L -#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK__VI 0x00000001L -#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK__VI 0x00000100L -#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK__VI 0x00000200L -#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK__VI 0x00020000L -#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK__VI 0x00400000L -#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK__VI 0x00040000L -#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK__VI 0x00010000L -#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK__VI 0x00100000L -#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK__VI 0x00080000L -#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK__VI 0x00200000L -#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK__VI 0x00008000L -#define SWRST_CONTROL_3__CMDCFG_ATEN_MASK__VI 0x20000000L -#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK__VI 0x00008000L -#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK__VI 0x00004000L -#define SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK__VI 0x00100000L -#define SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK__VI 0x00200000L -#define SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK__VI 0x00000004L -#define SWRST_CONTROL_3__RESETLC_ATEN_MASK__VI 0x00000040L -#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK__VI 0x00002000L -#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK__VI 0x01000000L -#define SWRST_CONTROL_3__RESETPHY1_ATEN_MASK__VI 0x02000000L -#define SWRST_CONTROL_3__RESETPIF0_ATEN_MASK__VI 0x00010000L -#define SWRST_CONTROL_3__RESETPIF1_ATEN_MASK__VI 0x00020000L -#define SWRST_CONTROL_3__RESETPRBS_ATEN_MASK__VI 0x00000002L -#define SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK__VI 0x00000010L -#define SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK__VI 0x00000020L -#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK__VI 0x00000008L -#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK__VI 0x10000000L -#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK__VI 0x00000001L -#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK__VI 0x00000100L -#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK__VI 0x00000200L -#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK__VI 0x00020000L -#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK__VI 0x00400000L -#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK__VI 0x00040000L -#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK__VI 0x00010000L -#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK__VI 0x00100000L -#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK__VI 0x00080000L -#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK__VI 0x00200000L -#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK__VI 0x00004000L -#define SWRST_CONTROL_5__WRCMDCFG_EN_MASK__VI 0x20000000L -#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK__VI 0x00008000L -#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK__VI 0x00004000L -#define SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK__VI 0x00100000L -#define SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK__VI 0x00200000L -#define SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK__VI 0x00000004L -#define SWRST_CONTROL_5__WRRESETLC_EN_MASK__VI 0x00000040L -#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK__VI 0x00002000L -#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK__VI 0x01000000L -#define SWRST_CONTROL_5__WRRESETPHY1_EN_MASK__VI 0x02000000L -#define SWRST_CONTROL_5__WRRESETPIF0_EN_MASK__VI 0x00010000L -#define SWRST_CONTROL_5__WRRESETPIF1_EN_MASK__VI 0x00020000L -#define SWRST_CONTROL_5__WRRESETPRBS_EN_MASK__VI 0x00000002L -#define SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK__VI 0x00000010L -#define SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK__VI 0x00000020L -#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK__VI 0x00000008L -#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK__VI 0x10000000L -#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK__VI 0x00000001L -#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK__VI 0x00000100L -#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK__VI 0x00000200L -#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK__VI 0x00000100L -#define SWRST_CONTROL_6__WARMRESET_EN_MASK__VI 0x00000001L -#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK__VI 0x00000001L -#define SWRST_EP_COMMAND_0__EP_DRV_RESET_MASK__VI 0x00000004L -#define SWRST_EP_COMMAND_0__EP_FLR0_RESET_MASK__VI 0x00010000L -#define SWRST_EP_COMMAND_0__EP_FLR1_RESET_MASK__VI 0x00020000L -#define SWRST_EP_COMMAND_0__EP_FLR2_RESET_MASK__VI 0x00040000L -#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK__VI 0x00000100L -#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK__VI 0x00000400L -#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK__VI 0x00000200L -#define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK__VI 0x00000002L -#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK__VI 0x00000001L -#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN_MASK__VI 0x00080000L -#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN_MASK__VI 0x00000004L -#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN_MASK__VI 0x00010000L -#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN_MASK__VI 0x00020000L -#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN_MASK__VI 0x00040000L -#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST_MASK__VI 0x00f00000L -#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK__VI 0x00000100L -#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK__VI 0x00000400L -#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK__VI 0x00000200L -#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK__VI 0x00000002L -#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK__VI 0x00000002L -#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK__VI 0x00000400L -#define SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK__VI 0x00010000L -#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK__VI 0x00020000L -#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK__VI 0x00001000L -#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN_MASK__VI 0x10000000L -#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR_MASK__VI 0x60000000L -#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK__VI 0x00000200L -#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK__VI 0x00004000L -#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK__VI 0x00002000L -#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK__VI 0x00000001L -#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK__VI 0x0000001cL -#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK__VI 0x00000100L -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK__VI 0x00000002L -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK__VI 0x00000001L -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK__VI 0x00000020L -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK__VI 0x00000010L -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK__VI 0x00000200L -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK__VI 0x00000100L -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK__VI 0x00002000L -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK__VI 0x00001000L -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK__VI 0x00020000L -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK__VI 0x00010000L -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK__VI 0x00200000L -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK__VI 0x00100000L -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK__VI 0x02000000L -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK__VI 0x01000000L -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK__VI 0x20000000L -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK__VI 0x10000000L -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK__VI 0x80000000L -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK__VI 0x0000000fL -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK__VI 0x000000f0L -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK__VI 0x00000f00L -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK__VI 0x0000f000L -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK__VI 0x000f0000L -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK__VI 0x00f00000L -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK__VI 0x0f000000L -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK__VI 0xf0000000L -#define SX_DEBUG_1__DEBUG_DATA_MASK__SI__CI 0xffffff80L -#define SX_DEBUG_1__DEBUG_DATA_MASK__VI 0xffffe000L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK__VI 0x00000200L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK__VI 0x00000400L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK__VI 0x00000100L -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK__VI 0x00001000L -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK__VI 0x00000800L -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK__VI 0x07000000L -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK__VI 0x00700000L -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK__VI 0x00070000L -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK__VI 0x00000700L -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK__VI 0x00000070L -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK__VI 0x00000007L -#define SX_PS_DOWNCONVERT__MRT0_MASK__VI 0x0000000fL -#define SX_PS_DOWNCONVERT__MRT1_MASK__VI 0x000000f0L -#define SX_PS_DOWNCONVERT__MRT2_MASK__VI 0x00000f00L -#define SX_PS_DOWNCONVERT__MRT3_MASK__VI 0x0000f000L -#define SX_PS_DOWNCONVERT__MRT4_MASK__VI 0x000f0000L -#define SX_PS_DOWNCONVERT__MRT5_MASK__VI 0x00f00000L -#define SX_PS_DOWNCONVERT__MRT6_MASK__VI 0x0f000000L -#define SX_PS_DOWNCONVERT__MRT7_MASK__VI 0xf0000000L -#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK__VI 0x40000000L -#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK__VI 0x000000ffL -#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK__VI 0x80000000L -#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK__VI 0x00ff0000L -#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK__VI 0x20000000L -#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK__VI 0x0000ff00L -#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK__VI 0x0000000fL -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK__VI 0x00080000L -#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK__VI 0x00020000L -#define TA_CNTL_AUX__ANISO_TAP_MASK__VI 0x00040000L -#define TA_CNTL_AUX__D16_PACK_DISABLE_MASK__VI 0x00000010L -#define TA_CNTL_AUX__RESERVED_MASK__VI 0x0000000eL -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK__VI 0x00000001L -#define TA_CNTL__FX_XNACK_CREDIT_MASK__VI 0x0000007fL -#define TA_CNTL__SQ_XNACK_CREDIT_MASK__VI 0x00001e00L -#define TCC_CTRL__MDC_SECTOR_SIZE_MASK__VI 0x0c000000L -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK__VI 0xf0000000L -#define TCC_CTRL__MDC_SIZE_MASK__VI 0x03000000L -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK__VI 0x00000f00L -#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK__VI 0x00000003L -#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK__VI 0x00000004L -#define TCC_EDC_CNT__DED_COUNT_MASK__VI 0x00ff0000L -#define TCC_EDC_CNT__SEC_COUNT_MASK__VI 0x000000ffL -#define TCC_EXE_DISABLE__EXE_DISABLE_MASK__VI 0x00000002L -#define TCC_EXE_DISABLE__WRITE_DIS_MASK__VI 0x00000001L -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK__VI 0x000000ffL -#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK__VI 0x000000ffL -#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK__VI 0x00000003L -#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK__VI 0x00000004L -#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK__VI 0x00000018L -#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK__VI 0x00000020L -#define TCP_EDC_CNT__DED_COUNT_MASK__VI 0x00ff0000L -#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK__VI 0x0000ff00L -#define TCP_EDC_CNT__SEC_COUNT_MASK__VI 0x000000ffL -#define TCP_EDC_CNT__UNUSED_MASK__VI 0xff000000L -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK__VI 0x08000000L -#define TCP_GATCL1_CNTL__FORCE_MISS_MASK__VI 0x04000000L -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK__VI 0x02000000L -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK__VI 0xc0000000L -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK__VI 0x30000000L -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK__VI 0x00000001L -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK__VI 0x00000002L -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK__VI 0x00000004L -#define TCP_STATUS__ADRS_BUSY_MASK__VI 0x00000004L -#define TCP_STATUS__CNTRL_BUSY_MASK__VI 0x00000010L -#define TCP_STATUS__FORMAT_BUSY_MASK__VI 0x00000080L -#define TCP_STATUS__INPUT_BUSY_MASK__VI 0x00000002L -#define TCP_STATUS__LFIFO_BUSY_MASK__VI 0x00000020L -#define TCP_STATUS__READ_BUSY_MASK__VI 0x00000040L -#define TCP_STATUS__TAGRAMS_BUSY_MASK__VI 0x00000008L -#define TCP_WATCH0_CNTL__ATC_MASK__VI 0x10000000L -#define TCP_WATCH1_CNTL__ATC_MASK__VI 0x10000000L -#define TCP_WATCH2_CNTL__ATC_MASK__VI 0x10000000L -#define TCP_WATCH3_CNTL__ATC_MASK__VI 0x10000000L -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK__VI 0x00800000L -#define TD_CNTL__DISABLE_D16_PACKING_MASK__VI 0x00400000L -#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK__VI 0x00200000L -#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK__VI 0x00000004L -#define TD_DSM_CNTL__FORCE_SEDB_0_MASK__VI 0x00000001L -#define TD_DSM_CNTL__FORCE_SEDB_1_MASK__VI 0x00000002L -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK__VI 0x00000010L -#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK__VI 0xffffffffL -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK__VI 0xffffffffL -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK__VI 0x0007fe00L -#define VGT_DMA_INDEX_TYPE__MTYPE_MASK__VI 0x00001800L -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK__VI 0x00000040L -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK__VI 0x0fc00000L -#define VGT_GS_MODE__RESERVED_3_MASK__VI 0x00004000L -#define VGT_GS_MODE__RESERVED_4_MASK__VI 0x00008000L -#define VGT_GS_MODE__RESERVED_5_MASK__VI 0x00010000L -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK__VI 0x00000200L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK__VI 0x00000400L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK__VI 0x00000800L -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK__VI 0x00001000L -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK__VI 0x000000ffL -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK__VI 0x00ff0000L -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK__VI 0x0000ff00L -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK__VI 0xff000000L -#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK__VI 0x00060000L -#define VGT_TF_PARAM__MTYPE_MASK__VI 0x00180000L -#define VGT_TF_PARAM__RDREQ_POLICY_MASK__VI 0x00008000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK__VI 0x00400000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK__VI 0x00200000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK__VI 0x00800000L -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK__SI__CI 0x000ff000L -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK__VI 0x001ff000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK__VI 0x00400000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK__VI 0x00200000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK__VI 0x00800000L -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK__SI__CI 0x000ff000L -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK__VI 0x001ff000L -#define VM_INIT_STATUS__VM_INIT_STATUS_MASK__VI 0x00000001L -#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK__SI__CI 0x000000ffL -#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK__VI 0x0000007fL -#define VM_L2_CG__OVERRIDE_MASK__VI 0x00100000L -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK__VI 0x0000003fL -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK__VI 0x00000040L -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_SHARED_MASK__VI 0x00000080L -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_SNOOP_MASK__VI 0x00000100L -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK__VI 0x00000200L -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_SHARED_MASK__VI 0x00000400L -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_SNOOP_MASK__VI 0x00000800L -#define WD_DEBUG_REG10__donut_en_p1_q_MASK__VI 0x00000100L -#define WD_DEBUG_REG10__donut_se_switch_p2_MASK__VI 0x00000200L -#define WD_DEBUG_REG10__eop_p1_q_MASK__VI 0x00008000L -#define WD_DEBUG_REG10__eopg_p1_q_MASK__VI 0x00004000L -#define WD_DEBUG_REG10__is_event_p1_q_MASK__VI 0x00002000L -#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK__VI 0x00001000L -#define WD_DEBUG_REG10__last_donut_switch_p2_MASK__VI 0x00000800L -#define WD_DEBUG_REG10__patch_accum_q_MASK__VI 0x00ff0000L -#define WD_DEBUG_REG10__patch_se_switch_p2_MASK__VI 0x00000400L -#define WD_DEBUG_REG10__pipe0_dr_MASK__VI 0x00000010L -#define WD_DEBUG_REG10__pipe0_rtr_MASK__VI 0x00000040L -#define WD_DEBUG_REG10__pipe1_dr_MASK__VI 0x00000020L -#define WD_DEBUG_REG10__pipe1_rtr_MASK__VI 0x00000080L -#define WD_DEBUG_REG10__ttp_pd_eop_MASK__VI 0x00000008L -#define WD_DEBUG_REG10__ttp_pd_eopg_MASK__VI 0x00000004L -#define WD_DEBUG_REG10__ttp_pd_is_event_MASK__VI 0x00000002L -#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK__VI 0x00000001L -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK__VI 0x02000000L -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK__VI 0x01000000L -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK__VI 0x08000000L -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK__VI 0x04000000L -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK__VI 0x20000000L -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK__VI 0x10000000L -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK__VI 0x80000000L -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK__VI 0x40000000L -#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK__VI 0xffffffffL -#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK__VI 0x00000001L -#define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in_MASK__VI 0x00000010L -#define WD_DEBUG_REG7__SPARE1_MASK__VI 0x00000f00L -#define WD_DEBUG_REG7__SPARE2_MASK__VI 0x0000f000L -#define WD_DEBUG_REG7__SPARE5_MASK__VI 0x00080000L -#define WD_DEBUG_REG7__SPARE6_MASK__VI 0x0f000000L -#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK__VI 0x40000000L -#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK__VI 0x20000000L -#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK__VI 0x00200000L -#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK__VI 0x00100000L -#define WD_DEBUG_REG7__se1_thdgrp_eop_MASK__VI 0x00800000L -#define WD_DEBUG_REG7__se1_thdgrp_is_event_MASK__VI 0x00400000L -#define WD_DEBUG_REG7__te11_arb_busy_MASK__VI 0x80000000L -#define WD_DEBUG_REG7__te11_arb_state_q_MASK__VI 0x00070000L -#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK__VI 0x10000000L -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK__VI 0x00000004L -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK__VI 0x00000008L -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK__VI 0x00000002L -#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty_MASK__VI 0x00000040L -#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full_MASK__VI 0x00000080L -#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re_MASK__VI 0x00000020L -#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK__VI 0x80000000L -#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK__VI 0x40000000L -#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK__VI 0x20000000L -#define WD_DEBUG_REG8__event_flag_p1_q_MASK__VI 0x00040000L -#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK__VI 0x10000000L -#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK__VI 0x00000800L -#define WD_DEBUG_REG8__null_flag_p1_q_MASK__VI 0x00080000L -#define WD_DEBUG_REG8__pipe0_dr_MASK__VI 0x00000001L -#define WD_DEBUG_REG8__pipe0_rtr_MASK__VI 0x00000004L -#define WD_DEBUG_REG8__pipe1_dr_MASK__VI 0x00000002L -#define WD_DEBUG_REG8__pipe1_rtr_MASK__VI 0x00000008L -#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK__VI 0x0003f000L -#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK__VI 0x08000000L -#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK__VI 0x00000040L -#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK__VI 0x07f00000L -#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK__VI 0x00000080L -#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK__VI 0x00000100L -#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK__VI 0x00000200L -#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK__VI 0x00000010L -#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK__VI 0x00000020L -#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK__VI 0x00000400L -#define WD_DEBUG_REG9__SPARE0_MASK__VI 0x0000f800L -#define WD_DEBUG_REG9__SPARE1_MASK__VI 0x08000000L -#define WD_DEBUG_REG9__SPARE2_MASK__VI 0x30000000L -#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK__VI 0x01000000L -#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK__VI 0x00000008L -#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK__VI 0x02000000L -#define WD_DEBUG_REG9__last_patch_of_tg_MASK__VI 0x00080000L -#define WD_DEBUG_REG9__mem_is_even_MASK__VI 0x04000000L -#define WD_DEBUG_REG9__pipe0_dr_MASK__VI 0x00000001L -#define WD_DEBUG_REG9__pipe0_rtr_MASK__VI 0x00000010L -#define WD_DEBUG_REG9__pipe1_rtr_MASK__VI 0x00000020L -#define WD_DEBUG_REG9__pipe2_dr_MASK__VI 0x00000004L -#define WD_DEBUG_REG9__pipe2_rtr_MASK__VI 0x00000080L -#define WD_DEBUG_REG9__pipe4_dr_MASK__VI 0x40000000L -#define WD_DEBUG_REG9__pipe4_rtr_MASK__VI 0x80000000L -#define WD_DEBUG_REG9__pipec_tf_dr_MASK__VI 0x00000002L -#define WD_DEBUG_REG9__pipec_tf_rtr_MASK__VI 0x00000040L -#define WD_DEBUG_REG9__tf_fetch_state_q_MASK__VI 0x00070000L -#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK__VI 0x00f00000L -#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK__VI 0x00000200L -#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK__VI 0x00000100L -#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK__VI 0x00000400L -#define WD_QOS__DRAW_STALL_MASK__VI 0x00000001L - -#endif // SI_CI_VI_merged_mask_HEADER diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_offset.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_offset.h deleted file mode 100644 index efa8a4ee7f..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_offset.h +++ /dev/null @@ -1,19182 +0,0 @@ -#if !defined SI_CI_VI_merged_offset_HEADER -#define SI_CI_VI_merged_offset_HEADER - - -// -// Source merge files: -// E:\MergedHeaders\SI+CI+Amur\Original\SICI/si_ci_merged_offset.h -// E:\MergedHeaders\SI+CI+Amur\Original\Amur/vi_offset.h -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -#define cfgADAPTER_ID 0x000B -#define cfgADAPTER_ID_W 0x0013 -#define cfgADAPTER_ID_W_alt_1 0x0013 -#define cfgADAPTER_ID_W_alt_2 0x0013 -#define cfgADAPTER_ID_W_alt_3__CI__VI 0x0013 -#define cfgADAPTER_ID_alt_1 0x000B -#define cfgADAPTER_ID_alt_2 0x000B -#define cfgADAPTER_ID_alt_3__CI__VI 0x000B -#define cfgBASE_ADDR_1 0x0004 -#define cfgBASE_ADDR_1_alt_1 0x0004 -#define cfgBASE_ADDR_1_alt_2 0x0004 -#define cfgBASE_ADDR_1_alt_3__CI__VI 0x0004 -#define cfgBASE_ADDR_2 0x0005 -#define cfgBASE_ADDR_2_alt_1 0x0005 -#define cfgBASE_ADDR_2_alt_2 0x0005 -#define cfgBASE_ADDR_2_alt_3__CI__VI 0x0005 -#define cfgBASE_ADDR_3 0x0006 -#define cfgBASE_ADDR_3_alt_1 0x0006 -#define cfgBASE_ADDR_3_alt_2 0x0006 -#define cfgBASE_ADDR_3_alt_3__CI__VI 0x0006 -#define cfgBASE_ADDR_4 0x0007 -#define cfgBASE_ADDR_4_alt_1 0x0007 -#define cfgBASE_ADDR_4_alt_2 0x0007 -#define cfgBASE_ADDR_4_alt_3__CI__VI 0x0007 -#define cfgBASE_ADDR_5 0x0008 -#define cfgBASE_ADDR_5_alt_1 0x0008 -#define cfgBASE_ADDR_5_alt_2 0x0008 -#define cfgBASE_ADDR_5_alt_3__CI__VI 0x0008 -#define cfgBASE_ADDR_6 0x0009 -#define cfgBASE_ADDR_6_alt_1 0x0009 -#define cfgBASE_ADDR_6_alt_2 0x0009 -#define cfgBASE_ADDR_6_alt_3__CI__VI 0x0009 -#define cfgBASE_CLASS 0x0002 -#define cfgBASE_CLASS_alt_1 0x0002 -#define cfgBASE_CLASS_alt_2 0x0002 -#define cfgBASE_CLASS_alt_3__CI__VI 0x0002 -#define cfgBIST 0x0003 -#define cfgBIST_alt_1 0x0003 -#define cfgBIST_alt_2 0x0003 -#define cfgBIST_alt_3__CI__VI 0x0003 -#define cfgCACHE_LINE 0x0003 -#define cfgCACHE_LINE_alt_1 0x0003 -#define cfgCACHE_LINE_alt_2 0x0003 -#define cfgCACHE_LINE_alt_3__CI__VI 0x0003 -#define cfgCAP_PTR 0x000D -#define cfgCAP_PTR_alt_1 0x000D -#define cfgCAP_PTR_alt_2 0x000D -#define cfgCAP_PTR_alt_3__CI__VI 0x000D -#define cfgCOMMAND 0x0001 -#define cfgCOMMAND_alt_1 0x0001 -#define cfgCOMMAND_alt_2 0x0001 -#define cfgCOMMAND_alt_3__CI__VI 0x0001 -#define cfgDEVICE_CAP 0x0017 -#define cfgDEVICE_CAP2 0x001F -#define cfgDEVICE_CAP2_alt_1 0x001F -#define cfgDEVICE_CAP2_alt_2 0x001F -#define cfgDEVICE_CAP2_alt_3__CI__VI 0x001F -#define cfgDEVICE_CAP_alt_1 0x0017 -#define cfgDEVICE_CAP_alt_2 0x0017 -#define cfgDEVICE_CAP_alt_3__CI__VI 0x0017 -#define cfgDEVICE_CNTL 0x0018 -#define cfgDEVICE_CNTL2 0x0020 -#define cfgDEVICE_CNTL2_alt_1 0x0020 -#define cfgDEVICE_CNTL2_alt_2 0x0020 -#define cfgDEVICE_CNTL2_alt_3__CI__VI 0x0020 -#define cfgDEVICE_CNTL_alt_1 0x0018 -#define cfgDEVICE_CNTL_alt_2 0x0018 -#define cfgDEVICE_CNTL_alt_3__CI__VI 0x0018 -#define cfgDEVICE_ID 0x0000 -#define cfgDEVICE_ID_alt_1 0x0000 -#define cfgDEVICE_ID_alt_2 0x0000 -#define cfgDEVICE_ID_alt_3__CI__VI 0x0000 -#define cfgDEVICE_STATUS 0x0018 -#define cfgDEVICE_STATUS2 0x0020 -#define cfgDEVICE_STATUS2_alt_1 0x0020 -#define cfgDEVICE_STATUS2_alt_2 0x0020 -#define cfgDEVICE_STATUS2_alt_3__CI__VI 0x0020 -#define cfgDEVICE_STATUS_alt_1 0x0018 -#define cfgDEVICE_STATUS_alt_2 0x0018 -#define cfgDEVICE_STATUS_alt_3__CI__VI 0x0018 -#define cfgHEADER 0x0003 -#define cfgHEADER_alt_1 0x0003 -#define cfgHEADER_alt_2 0x0003 -#define cfgHEADER_alt_3__CI__VI 0x0003 -#define cfgINTERRUPT_LINE 0x000F -#define cfgINTERRUPT_LINE_alt_1 0x000F -#define cfgINTERRUPT_LINE_alt_2 0x000F -#define cfgINTERRUPT_LINE_alt_3__CI__VI 0x000F -#define cfgINTERRUPT_PIN 0x000F -#define cfgINTERRUPT_PIN_alt_1 0x000F -#define cfgINTERRUPT_PIN_alt_2 0x000F -#define cfgINTERRUPT_PIN_alt_3__CI__VI 0x000F -#define cfgLATENCY 0x0003 -#define cfgLATENCY_alt_1 0x0003 -#define cfgLATENCY_alt_2 0x0003 -#define cfgLATENCY_alt_3__CI__VI 0x0003 -#define cfgLINK_CAP 0x0019 -#define cfgLINK_CAP2 0x0021 -#define cfgLINK_CAP2_alt_1 0x0021 -#define cfgLINK_CAP2_alt_2 0x0021 -#define cfgLINK_CAP2_alt_3__CI__VI 0x0021 -#define cfgLINK_CAP_alt_1 0x0019 -#define cfgLINK_CAP_alt_2 0x0019 -#define cfgLINK_CAP_alt_3__CI__VI 0x0019 -#define cfgLINK_CNTL 0x001A -#define cfgLINK_CNTL2 0x0022 -#define cfgLINK_CNTL2_alt_1 0x0022 -#define cfgLINK_CNTL2_alt_2 0x0022 -#define cfgLINK_CNTL2_alt_3__CI__VI 0x0022 -#define cfgLINK_CNTL_alt_1 0x001A -#define cfgLINK_CNTL_alt_2 0x001A -#define cfgLINK_CNTL_alt_3__CI__VI 0x001A -#define cfgLINK_STATUS 0x001A -#define cfgLINK_STATUS2 0x0022 -#define cfgLINK_STATUS2_alt_1 0x0022 -#define cfgLINK_STATUS2_alt_2 0x0022 -#define cfgLINK_STATUS2_alt_3__CI__VI 0x0022 -#define cfgLINK_STATUS_alt_1 0x001A -#define cfgLINK_STATUS_alt_2 0x001A -#define cfgLINK_STATUS_alt_3__CI__VI 0x001A -#define cfgMAX_LATENCY 0x000F -#define cfgMAX_LATENCY_alt_1 0x000F -#define cfgMAX_LATENCY_alt_2 0x000F -#define cfgMAX_LATENCY_alt_3__CI__VI 0x000F -#define cfgMIN_GRANT 0x000F -#define cfgMIN_GRANT_alt_1 0x000F -#define cfgMIN_GRANT_alt_2 0x000F -#define cfgMIN_GRANT_alt_3__CI__VI 0x000F -#define cfgMSI_CAP_LIST 0x0028 -#define cfgMSI_CAP_LIST_alt_1 0x0028 -#define cfgMSI_CAP_LIST_alt_2 0x0028 -#define cfgMSI_CAP_LIST_alt_3__CI__VI 0x0028 -#define cfgMSI_MSG_ADDR_HI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_1 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_2 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_3__CI__VI 0x002A -#define cfgMSI_MSG_ADDR_LO 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_1 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_2 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_3__CI__VI 0x0029 -#define cfgMSI_MSG_CNTL 0x0028 -#define cfgMSI_MSG_CNTL_alt_1 0x0028 -#define cfgMSI_MSG_CNTL_alt_2 0x0028 -#define cfgMSI_MSG_CNTL_alt_3__CI__VI 0x0028 -#define cfgMSI_MSG_DATA 0x002A -#define cfgMSI_MSG_DATA_64 0x002B -#define cfgMSI_MSG_DATA_64_alt_1 0x002B -#define cfgMSI_MSG_DATA_64_alt_2 0x002B -#define cfgMSI_MSG_DATA_64_alt_3__CI__VI 0x002B -#define cfgMSI_MSG_DATA_alt_1 0x002A -#define cfgMSI_MSG_DATA_alt_2 0x002A -#define cfgMSI_MSG_DATA_alt_3__CI__VI 0x002A -#define cfgPCIE_ACS_CAP__CI__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_1__CI__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_2__CI__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_3__CI__VI 0x00A9 -#define cfgPCIE_ACS_CNTL__CI__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_1__CI__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_2__CI__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_3__CI__VI 0x00A9 -#define cfgPCIE_ACS_ENH_CAP_LIST__CI__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_1__CI__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_2__CI__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_3__CI__VI 0x00A8 -#define cfgPCIE_ADV_ERR_CAP_CNTL 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_1 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_2 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_3__CI__VI 0x005A -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_1 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_2 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_3__CI__VI 0x0054 -#define cfgPCIE_ATS_CAP__CI__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_1__CI__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_2__CI__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_3__CI__VI 0x00AD -#define cfgPCIE_ATS_CNTL__CI__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_1__CI__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_2__CI__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_3__CI__VI 0x00AD -#define cfgPCIE_ATS_ENH_CAP_LIST__CI__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_1__CI__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_2__CI__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_3__CI__VI 0x00AC -#define cfgPCIE_BAR1_CAP__CI__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_1__CI__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_2__CI__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_3__CI__VI 0x0081 -#define cfgPCIE_BAR1_CNTL__CI__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_1__CI__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_2__CI__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_3__CI__VI 0x0082 -#define cfgPCIE_BAR2_CAP__CI__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_1__CI__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_2__CI__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_3__CI__VI 0x0083 -#define cfgPCIE_BAR2_CNTL__CI__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_1__CI__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_2__CI__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_3__CI__VI 0x0084 -#define cfgPCIE_BAR3_CAP__CI__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_1__CI__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_2__CI__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_3__CI__VI 0x0085 -#define cfgPCIE_BAR3_CNTL__CI__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_1__CI__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_2__CI__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_3__CI__VI 0x0086 -#define cfgPCIE_BAR4_CAP__CI__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_1__CI__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_2__CI__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_3__CI__VI 0x0087 -#define cfgPCIE_BAR4_CNTL__CI__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_1__CI__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_2__CI__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_3__CI__VI 0x0088 -#define cfgPCIE_BAR5_CAP__CI__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_1__CI__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_2__CI__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_3__CI__VI 0x0089 -#define cfgPCIE_BAR5_CNTL__CI__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_1__CI__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_2__CI__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_3__CI__VI 0x008A -#define cfgPCIE_BAR6_CAP__CI__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_1__CI__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_2__CI__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_3__CI__VI 0x008B -#define cfgPCIE_BAR6_CNTL__CI__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_1__CI__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_2__CI__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_3__CI__VI 0x008C -#define cfgPCIE_BAR_ENH_CAP_LIST__CI__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_1__CI__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_2__CI__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_3__CI__VI 0x0080 -#define cfgPCIE_CAC_DEVICE_CORRELATION__SI 0x0065 -#define cfgPCIE_CAC_DEVICE_CORRELATION_alt_1__SI 0x0065 -#define cfgPCIE_CAC_DEVICE_CORRELATION_alt_2__SI 0x0065 -#define cfgPCIE_CAC_ENH_CAP_LIST__SI 0x0064 -#define cfgPCIE_CAC_ENH_CAP_LIST_alt_1__SI 0x0064 -#define cfgPCIE_CAC_ENH_CAP_LIST_alt_2__SI 0x0064 -#define cfgPCIE_CAP 0x0016 -#define cfgPCIE_CAP_LIST 0x0016 -#define cfgPCIE_CAP_LIST_alt_1 0x0016 -#define cfgPCIE_CAP_LIST_alt_2 0x0016 -#define cfgPCIE_CAP_LIST_alt_3__CI__VI 0x0016 -#define cfgPCIE_CAP_alt_1 0x0016 -#define cfgPCIE_CAP_alt_2 0x0016 -#define cfgPCIE_CAP_alt_3__CI__VI 0x0016 -#define cfgPCIE_CORR_ERR_MASK 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_1 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_2 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_3__CI__VI 0x0059 -#define cfgPCIE_CORR_ERR_STATUS 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_1 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_2 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_3__CI__VI 0x0058 -#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_1 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_2 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_3__CI__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_1 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_2 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_3__CI__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_1 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_2 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_3__CI__VI 0x0050 -#define cfgPCIE_DPA_CAP__CI__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_1__CI__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_2__CI__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_3__CI__VI 0x0095 -#define cfgPCIE_DPA_CNTL__CI__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_1__CI__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_2__CI__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_3__CI__VI 0x0097 -#define cfgPCIE_DPA_ENH_CAP_LIST__CI__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_1__CI__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_2__CI__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_3__CI__VI 0x0094 -#define cfgPCIE_DPA_LATENCY_INDICATOR__CI__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_1__CI__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_2__CI__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_3__CI__VI 0x0096 -#define cfgPCIE_DPA_STATUS__CI__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_1__CI__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_2__CI__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_3__CI__VI 0x0097 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_1__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_2__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_3__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_1__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_2__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_3__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_1__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_2__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_3__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_1__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_2__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_3__CI__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_1__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_2__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_3__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_1__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_2__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_3__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_1__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_2__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_3__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_1__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_2__CI__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_3__CI__VI 0x0099 -#define cfgPCIE_HDR_LOG0 0x005B -#define cfgPCIE_HDR_LOG0_alt_1 0x005B -#define cfgPCIE_HDR_LOG0_alt_2 0x005B -#define cfgPCIE_HDR_LOG0_alt_3__CI__VI 0x005B -#define cfgPCIE_HDR_LOG1 0x005C -#define cfgPCIE_HDR_LOG1_alt_1 0x005C -#define cfgPCIE_HDR_LOG1_alt_2 0x005C -#define cfgPCIE_HDR_LOG1_alt_3__CI__VI 0x005C -#define cfgPCIE_HDR_LOG2 0x005D -#define cfgPCIE_HDR_LOG2_alt_1 0x005D -#define cfgPCIE_HDR_LOG2_alt_2 0x005D -#define cfgPCIE_HDR_LOG2_alt_3__CI__VI 0x005D -#define cfgPCIE_HDR_LOG3 0x005E -#define cfgPCIE_HDR_LOG3_alt_1 0x005E -#define cfgPCIE_HDR_LOG3_alt_2 0x005E -#define cfgPCIE_HDR_LOG3_alt_3__CI__VI 0x005E -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_1__CI__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_2__CI__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_3__CI__VI 0x009F -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A4 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A5 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A6 -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_1__CI__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_2__CI__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_3__CI__VI 0x009F -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A0 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A1 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A2 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A3 -#define cfgPCIE_LANE_ERROR_STATUS__CI__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_1__CI__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_2__CI__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_3__CI__VI 0x009E -#define cfgPCIE_LINK_CNTL3__CI__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_1__CI__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_2__CI__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_3__CI__VI 0x009D -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_1__CI__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_2__CI__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_3__CI__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_1__CI__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_2__CI__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_3__CI__VI 0x00B2 -#define cfgPCIE_PAGE_REQ_CNTL__CI__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_1__CI__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_2__CI__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_3__CI__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_1__CI__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_2__CI__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_3__CI__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_STATUS__CI__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_1__CI__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_2__CI__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_3__CI__VI 0x00B1 -#define cfgPCIE_PASID_CAP__CI__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_1__CI__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_2__CI__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_3__CI__VI 0x00B5 -#define cfgPCIE_PASID_CNTL__CI__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_1__CI__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_2__CI__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_3__CI__VI 0x00B5 -#define cfgPCIE_PASID_ENH_CAP_LIST__CI__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_1__CI__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_2__CI__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_3__CI__VI 0x00B4 -#define cfgPCIE_PORT_VC_CAP_REG1 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_1 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_2 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_3__CI__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG2 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_1 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_2 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_3__CI__VI 0x0046 -#define cfgPCIE_PORT_VC_CNTL 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_1 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_2 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_3__CI__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_1 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_2 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_3__CI__VI 0x0047 -#define cfgPCIE_PWR_BUDGET_CAP__CI__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_1__CI__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_2__CI__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_3__CI__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT__CI__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_1__CI__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_2__CI__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_3__CI__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA__CI__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_1__CI__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_2__CI__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_3__CI__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_1__CI__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_2__CI__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_3__CI__VI 0x0090 -#define cfgPCIE_SECONDARY_ENH_CAP_LIST__CI__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_1__CI__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_2__CI__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_3__CI__VI 0x009C -#define cfgPCIE_TLP_PREFIX_LOG0__CI__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_1__CI__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_2__CI__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_3__CI__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG1__CI__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_1__CI__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_2__CI__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_3__CI__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG2__CI__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_1__CI__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_2__CI__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_3__CI__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG3__CI__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_1__CI__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_2__CI__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_3__CI__VI 0x0065 -#define cfgPCIE_TRUSTED_BASE_CLASS__SI 0x0000 -#define cfgPCIE_TRUSTED_BASE_CLASS_alt_1__SI 0x0000 -#define cfgPCIE_TRUSTED_BASE_CLASS_alt_2__SI 0x0000 -#define cfgPCIE_TRUSTED_CAC_CAP_LIST__SI 0x0004 -#define cfgPCIE_TRUSTED_CAC_CAP_LIST_alt_1__SI 0x0004 -#define cfgPCIE_TRUSTED_CAC_CAP_LIST_alt_2__SI 0x0004 -#define cfgPCIE_TRUSTED_CAC_DEVICE_CORRELATION__SI 0x0005 -#define cfgPCIE_TRUSTED_CAC_DEVICE_CORRELATION_alt_1__SI 0x0005 -#define cfgPCIE_TRUSTED_CAC_DEVICE_CORRELATION_alt_2__SI 0x0005 -#define cfgPCIE_TRUSTED_FIRST_CAP_OFFSET__SI 0x0001 -#define cfgPCIE_TRUSTED_FIRST_CAP_OFFSET_alt_1__SI 0x0001 -#define cfgPCIE_TRUSTED_FIRST_CAP_OFFSET_alt_2__SI 0x0001 -#define cfgPCIE_TRUSTED_PROG_INTERFACE__SI 0x0000 -#define cfgPCIE_TRUSTED_PROG_INTERFACE_alt_1__SI 0x0000 -#define cfgPCIE_TRUSTED_PROG_INTERFACE_alt_2__SI 0x0000 -#define cfgPCIE_TRUSTED_SUB_CLASS__SI 0x0000 -#define cfgPCIE_TRUSTED_SUB_CLASS_alt_1__SI 0x0000 -#define cfgPCIE_TRUSTED_SUB_CLASS_alt_2__SI 0x0000 -#define cfgPCIE_UNCORR_ERR_MASK 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_1 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_2 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_3__CI__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_SEVERITY 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_1 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_2 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_3__CI__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_STATUS 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_1 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_2 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_3__CI__VI 0x0055 -#define cfgPCIE_VC0_RESOURCE_CAP 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_1 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_2 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_3__CI__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CNTL 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_1 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_2 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_3__CI__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_STATUS 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_1 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_2 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_3__CI__VI 0x004A -#define cfgPCIE_VC1_RESOURCE_CAP 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_1 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_2 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_3__CI__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CNTL 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_1 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_2 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_3__CI__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_STATUS 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_1 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_2 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_3__CI__VI 0x004D -#define cfgPCIE_VC_ENH_CAP_LIST 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_1 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_2 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_3__CI__VI 0x0044 -#define cfgPCIE_VENDOR_SPECIFIC1 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_1 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_2 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_3__CI__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC2 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_1 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_2 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_3__CI__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_1 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_2 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_3__CI__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_1 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_2 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_3__CI__VI 0x0041 -#define cfgPMI_CAP 0x0014 -#define cfgPMI_CAP_LIST 0x0014 -#define cfgPMI_CAP_LIST_alt_1 0x0014 -#define cfgPMI_CAP_LIST_alt_2 0x0014 -#define cfgPMI_CAP_LIST_alt_3__CI__VI 0x0014 -#define cfgPMI_CAP_alt_1 0x0014 -#define cfgPMI_CAP_alt_2 0x0014 -#define cfgPMI_CAP_alt_3__CI__VI 0x0014 -#define cfgPMI_STATUS_CNTL 0x0015 -#define cfgPMI_STATUS_CNTL_alt_1 0x0015 -#define cfgPMI_STATUS_CNTL_alt_2 0x0015 -#define cfgPMI_STATUS_CNTL_alt_3__CI__VI 0x0015 -#define cfgPROG_INTERFACE 0x0002 -#define cfgPROG_INTERFACE_alt_1 0x0002 -#define cfgPROG_INTERFACE_alt_2 0x0002 -#define cfgPROG_INTERFACE_alt_3__CI__VI 0x0002 -#define cfgREVISION_ID 0x0002 -#define cfgREVISION_ID_alt_1 0x0002 -#define cfgREVISION_ID_alt_2 0x0002 -#define cfgREVISION_ID_alt_3__CI__VI 0x0002 -#define cfgROM_BASE_ADDR 0x000C -#define cfgROM_BASE_ADDR_alt_1 0x000C -#define cfgROM_BASE_ADDR_alt_2 0x000C -#define cfgROM_BASE_ADDR_alt_3__CI__VI 0x000C -#define cfgSTATUS 0x0001 -#define cfgSTATUS_alt_1 0x0001 -#define cfgSTATUS_alt_2 0x0001 -#define cfgSTATUS_alt_3__CI__VI 0x0001 -#define cfgSUB_CLASS 0x0002 -#define cfgSUB_CLASS_alt_1 0x0002 -#define cfgSUB_CLASS_alt_2 0x0002 -#define cfgSUB_CLASS_alt_3__CI__VI 0x0002 -#define cfgVENDOR_CAP_LIST__CI__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_1__CI__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_2__CI__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_3__CI__VI 0x0012 -#define cfgVENDOR_ID 0x0000 -#define cfgVENDOR_ID_alt_1 0x0000 -#define cfgVENDOR_ID_alt_2 0x0000 -#define cfgVENDOR_ID_alt_3__CI__VI 0x0000 -#define ioATTRDR__SI 0x00F0 -#define ioATTRDW__SI 0x00F0 -#define ioATTRX__SI 0x00F0 -#define ioBIF_RFE_SNOOP_REG__CI__VI 0x0027 -#define ioCRTC8_DATA__SI 0x00ED -#define ioCRTC8_DATA_alt_1__SI 0x00F5 -#define ioCRTC8_IDX__SI 0x00ED -#define ioCRTC8_IDX_alt_1__SI 0x00F5 -#define ioDAC_DATA__SI 0x00F2 -#define ioDAC_MASK__SI 0x00F1 -#define ioDAC_R_INDEX__SI 0x00F1 -#define ioDAC_W_INDEX__SI 0x00F2 -#define ioGENENB__SI 0x00F0 -#define ioGENFC_RD__SI 0x00F2 -#define ioGENFC_WT__SI 0x00EE -#define ioGENFC_WT_alt_1__SI 0x00F6 -#define ioGENMO_RD__SI 0x00F3 -#define ioGENMO_WT__SI 0x00F0 -#define ioGENS0__SI 0x00F0 -#define ioGENS1__SI 0x00EE -#define ioGENS1_alt_1__SI 0x00F6 -#define ioGRPH8_DATA__SI 0x00F3 -#define ioGRPH8_IDX__SI 0x00F3 -#define ioMM_DATA 0x0001 -#define ioMM_INDEX 0x0000 -#define ioMM_INDEX_HI__CI__VI 0x0006 -#define ioPCIE_DATA_2__CI__VI 0x000D -#define ioPCIE_DATA__CI__VI 0x000F -#define ioPCIE_DATA__SI 0x000D -#define ioPCIE_INDEX_2__CI__VI 0x000C -#define ioPCIE_INDEX__CI__VI 0x000E -#define ioPCIE_INDEX__SI 0x000C -#define ioPCIE_PORT_DATA__SI 0x000F -#define ioPCIE_PORT_INDEX__SI 0x000E -#define ioROM_DATA__SI 0x002B -#define ioROM_INDEX__SI 0x002A -#define ioSEQ8_DATA__SI 0x00F1 -#define ioSEQ8_IDX__SI 0x00F1 -#define ioVGA_MEM_READ_PAGE_ADDR__SI 0x0013 -#define ioVGA_MEM_WRITE_PAGE_ADDR__SI 0x0012 -#define mmABM_RBBMIF_RDWR_TIMEOUT__SI 0x031F -#define mmABM_TEST_DEBUG_DATA__SI 0x169F -#define mmABM_TEST_DEBUG_INDEX__SI 0x169E -#define mmACP_CONFIG__CI 0x0F95 -#define mmACTIVITY_MONITOR__SI 0x01E5 -#define mmACTIVITY_THRESHOLDS__SI 0x0200 -#define mmAFMT_60958_0__SI 0x1C41 -#define mmAFMT_60958_1__SI 0x1C42 -#define mmAFMT_60958_2__SI 0x1C48 -#define mmAFMT_ACP__SI 0x1C15 -#define mmAFMT_AUDIO_CRC_CONTROL__SI 0x1C43 -#define mmAFMT_AUDIO_CRC_RESULT__SI 0x1C49 -#define mmAFMT_AUDIO_INFO0__SI 0x1C3F -#define mmAFMT_AUDIO_INFO1__SI 0x1C40 -#define mmAFMT_AUDIO_PACKET_CONTROL2__SI 0x1C17 -#define mmAFMT_AUDIO_PACKET_CONTROL__SI 0x1C4B -#define mmAFMT_AVI_INFO0__SI 0x1C21 -#define mmAFMT_AVI_INFO1__SI 0x1C22 -#define mmAFMT_AVI_INFO2__SI 0x1C23 -#define mmAFMT_AVI_INFO3__SI 0x1C24 -#define mmAFMT_GENERIC0_0__SI 0x1C28 -#define mmAFMT_GENERIC0_1__SI 0x1C29 -#define mmAFMT_GENERIC0_2__SI 0x1C2A -#define mmAFMT_GENERIC0_3__SI 0x1C2B -#define mmAFMT_GENERIC0_4__SI 0x1C2C -#define mmAFMT_GENERIC0_5__SI 0x1C2D -#define mmAFMT_GENERIC0_6__SI 0x1C2E -#define mmAFMT_GENERIC0_7__SI 0x1C4E -#define mmAFMT_GENERIC0_HDR__SI 0x1C27 -#define mmAFMT_GENERIC1_0__SI 0x1C30 -#define mmAFMT_GENERIC1_1__SI 0x1C31 -#define mmAFMT_GENERIC1_2__SI 0x1C32 -#define mmAFMT_GENERIC1_3__SI 0x1C33 -#define mmAFMT_GENERIC1_4__SI 0x1C34 -#define mmAFMT_GENERIC1_5__SI 0x1C35 -#define mmAFMT_GENERIC1_6__SI 0x1C36 -#define mmAFMT_GENERIC1_HDR__SI 0x1C2F -#define mmAFMT_INFOFRAME_CONTROL0__SI 0x1C4D -#define mmAFMT_INTERRUPT_STATUS__SI 0x1C14 -#define mmAFMT_ISRC1_0__SI 0x1C18 -#define mmAFMT_ISRC1_1__SI 0x1C19 -#define mmAFMT_ISRC1_2__SI 0x1C1A -#define mmAFMT_ISRC1_3__SI 0x1C1B -#define mmAFMT_ISRC1_4__SI 0x1C1C -#define mmAFMT_ISRC2_0__SI 0x1C1D -#define mmAFMT_ISRC2_1__SI 0x1C1E -#define mmAFMT_ISRC2_2__SI 0x1C1F -#define mmAFMT_ISRC2_3__SI 0x1C20 -#define mmAFMT_MPEG_INFO0__SI 0x1C25 -#define mmAFMT_MPEG_INFO1__SI 0x1C26 -#define mmAFMT_RAMP_CONTROL0__SI 0x1C44 -#define mmAFMT_RAMP_CONTROL1__SI 0x1C45 -#define mmAFMT_RAMP_CONTROL2__SI 0x1C46 -#define mmAFMT_RAMP_CONTROL3__SI 0x1C47 -#define mmAFMT_STATUS__SI 0x1C4A -#define mmAFMT_VBI_PACKET_CONTROL__SI 0x1C4C -#define mmATC_ATS_CNTL__CI__VI 0x0CC9 -#define mmATC_ATS_DEBUG__CI__VI 0x0CCA -#define mmATC_ATS_DEFAULT_PAGE_CNTL__CI__VI 0x0CD1 -#define mmATC_ATS_DEFAULT_PAGE_LOW__CI__VI 0x0CD0 -#define mmATC_ATS_FAULT_CNTL__CI__VI 0x0CCD -#define mmATC_ATS_FAULT_DEBUG__CI__VI 0x0CCB -#define mmATC_ATS_FAULT_STATUS_ADDR__CI__VI 0x0CCF -#define mmATC_ATS_FAULT_STATUS_INFO__CI__VI 0x0CCE -#define mmATC_ATS_STATUS__CI__VI 0x0CCC -#define mmATC_L1RD_DEBUG_TLB__CI__VI 0x0CDE -#define mmATC_L1RD_STATUS__CI__VI 0x0CE0 -#define mmATC_L1WR_DEBUG_TLB__CI__VI 0x0CDF -#define mmATC_L1WR_STATUS__CI__VI 0x0CE1 -#define mmATC_L1_ADDRESS_OFFSET__CI__VI 0x0CDD -#define mmATC_L1_CNTL__CI__VI 0x0CDC -#define mmATC_L2_CNTL2__CI__VI 0x0CD6 -#define mmATC_L2_CNTL__CI__VI 0x0CD5 -#define mmATC_L2_DEBUG2__CI__VI 0x0CD8 -#define mmATC_L2_DEBUG__CI__VI 0x0CD7 -#define mmATC_MISC_CG__CI__VI 0x0CD4 -#define mmATC_PERFCOUNTER0_CFG__CI__VI 0x07C8 -#define mmATC_PERFCOUNTER1_CFG__CI__VI 0x07C9 -#define mmATC_PERFCOUNTER2_CFG__CI__VI 0x07CA -#define mmATC_PERFCOUNTER3_CFG__CI__VI 0x07CB -#define mmATC_PERFCOUNTER_HI__CI__VI 0x07AF -#define mmATC_PERFCOUNTER_LO__CI__VI 0x07A7 -#define mmATC_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07D5 -#define mmATC_VMID0_PASID_MAPPING__CI__VI 0x0CE7 -#define mmATC_VMID10_PASID_MAPPING__CI__VI 0x0CF1 -#define mmATC_VMID11_PASID_MAPPING__CI__VI 0x0CF2 -#define mmATC_VMID12_PASID_MAPPING__CI__VI 0x0CF3 -#define mmATC_VMID13_PASID_MAPPING__CI__VI 0x0CF4 -#define mmATC_VMID14_PASID_MAPPING__CI__VI 0x0CF5 -#define mmATC_VMID15_PASID_MAPPING__CI__VI 0x0CF6 -#define mmATC_VMID1_PASID_MAPPING__CI__VI 0x0CE8 -#define mmATC_VMID2_PASID_MAPPING__CI__VI 0x0CE9 -#define mmATC_VMID3_PASID_MAPPING__CI__VI 0x0CEA -#define mmATC_VMID4_PASID_MAPPING__CI__VI 0x0CEB -#define mmATC_VMID5_PASID_MAPPING__CI__VI 0x0CEC -#define mmATC_VMID6_PASID_MAPPING__CI__VI 0x0CED -#define mmATC_VMID7_PASID_MAPPING__CI__VI 0x0CEE -#define mmATC_VMID8_PASID_MAPPING__CI__VI 0x0CEF -#define mmATC_VMID9_PASID_MAPPING__CI__VI 0x0CF0 -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI 0x0CE6 -#define mmATC_VM_APERTURE0_CNTL2__CI__VI 0x0CC6 -#define mmATC_VM_APERTURE0_CNTL__CI__VI 0x0CC4 -#define mmATC_VM_APERTURE0_HIGH_ADDR__CI__VI 0x0CC2 -#define mmATC_VM_APERTURE0_LOW_ADDR__CI__VI 0x0CC0 -#define mmATC_VM_APERTURE1_CNTL2__CI__VI 0x0CC7 -#define mmATC_VM_APERTURE1_CNTL__CI__VI 0x0CC5 -#define mmATC_VM_APERTURE1_HIGH_ADDR__CI__VI 0x0CC3 -#define mmATC_VM_APERTURE1_LOW_ADDR__CI__VI 0x0CC1 -#define mmATTRDR__SI 0x00F0 -#define mmATTRDW__SI 0x00F0 -#define mmATTRX__SI 0x00F0 -#define mmAUXN_IMPCAL__SI 0x194B -#define mmAUXP_IMPCAL__SI 0x194A -#define mmAUX_ARB_CONTROL__SI 0x1882 -#define mmAUX_CONTROL__SI 0x1880 -#define mmAUX_DPHY_RX_CONTROL0__SI 0x188A -#define mmAUX_DPHY_RX_CONTROL1__SI 0x188B -#define mmAUX_DPHY_RX_STATUS__SI 0x188D -#define mmAUX_DPHY_TX_CONTROL__SI 0x1889 -#define mmAUX_DPHY_TX_REF_CONTROL__SI 0x1888 -#define mmAUX_DPHY_TX_STATUS__SI 0x188C -#define mmAUX_INTERRUPT_CONTROL__SI 0x1883 -#define mmAUX_LS_DATA__SI 0x1887 -#define mmAUX_LS_STATUS__SI 0x1885 -#define mmAUX_SW_CONTROL__SI 0x1881 -#define mmAUX_SW_DATA__SI 0x1886 -#define mmAUX_SW_STATUS__SI 0x1884 -#define mmAVP_BCKN_OVL__SI 0x1AF5 -#define mmAVP_CONFIG__SI 0x0F97 -#define mmAVP_RLC_CONTROL__SI 0x0F95 -#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI 0x17F6 -#define mmAZALIA_AUDIO_DTO_CONTROL__SI 0x173D -#define mmAZALIA_AUDIO_DTO__SI 0x173C -#define mmAZALIA_BDL_DMA_CONTROL__SI 0x1730 -#define mmAZALIA_CHANNEL_COUNT_CONTROL__SI 0x17F9 -#define mmAZALIA_CODEC_CONTROL__SI 0x1739 -#define mmAZALIA_CORB_DMA_CONTROL__SI 0x172F -#define mmAZALIA_CUMULATIVE_LATENCY_COUNT__SI 0x1737 -#define mmAZALIA_CUMULATIVE_REQUEST_COUNT__SI 0x1738 -#define mmAZALIA_CYCLIC_BUFFER_SYNC__SI 0x17F7 -#define mmAZALIA_DATA_DMA_CONTROL__SI 0x1731 -#define mmAZALIA_DEBUG__SI 0x173B -#define mmAZALIA_DRM_COMMAND__SI 0x17F1 -#define mmAZALIA_DRM_MASK_FIFO_STATUS__SI 0x17F8 -#define mmAZALIA_DRM_PAYLOAD0__SI 0x17F2 -#define mmAZALIA_DRM_PAYLOAD1__SI 0x17F3 -#define mmAZALIA_DRM_PAYLOAD2__SI 0x17F4 -#define mmAZALIA_DRM_PAYLOAD3__SI 0x177E -#define mmAZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SI 0x174E -#define mmAZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__SI 0x1754 -#define mmAZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI 0x1746 -#define mmAZALIA_F0_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__SI 0x175E -#define mmAZALIA_F0_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__SI 0x1760 -#define mmAZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI 0x175A -#define mmAZALIA_F0_CODEC_CONVERTER123_PARAMETER_STREAM_FORMATS__SI 0x175F -#define mmAZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SI 0x1757 -#define mmAZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__SI 0x175B -#define mmAZALIA_F0_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__SI 0x1761 -#define mmAZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SI 0x1758 -#define mmAZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__SI 0x175C -#define mmAZALIA_F0_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__SI 0x1762 -#define mmAZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SI 0x1759 -#define mmAZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__SI 0x175D -#define mmAZALIA_F0_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__SI 0x1763 -#define mmAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI 0x174F -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI 0x174C -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI 0x174D -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI 0x1750 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI 0x1742 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI 0x1745 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI 0x1744 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI 0x1741 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI 0x1743 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__SI 0x176E -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__SI 0x176F -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__SI 0x1779 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__SI 0x177A -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__SI 0x177B -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__SI 0x177C -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__SI 0x1770 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__SI 0x1771 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__SI 0x1772 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__SI 0x1773 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__SI 0x1774 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__SI 0x1775 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__SI 0x1776 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__SI 0x1777 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__SI 0x1778 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__SI 0x176C -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_DRM__SI 0x17FC -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__SI 0x176D -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__SI 0x177D -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__SI 0x17FD -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__SI 0x17FE -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER__SI 0x17FF -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI 0x1751 -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR__SI 0x17FB -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC__SI 0x17FA -#define mmAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__SI 0x1752 -#define mmAZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI 0x1747 -#define mmAZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__SI 0x1748 -#define mmAZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI 0x1764 -#define mmAZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__SI 0x1765 -#define mmAZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI 0x1766 -#define mmAZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__SI 0x1769 -#define mmAZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI 0x1767 -#define mmAZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__SI 0x176A -#define mmAZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI 0x1768 -#define mmAZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__SI 0x176B -#define mmAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI 0x174A -#define mmAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI 0x174B -#define mmAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI 0x1753 -#define mmAZALIA_F0_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__SI 0x1749 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI 0x173F -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI 0x1740 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI 0x173E -#define mmAZALIA_HDCP_REQUIRED__SI 0x17F0 -#define mmAZALIA_HOT_PLUG_CONTROL__SI 0x172C -#define mmAZALIA_LATENCY_COUNTER_CONTROL__SI 0x1735 -#define mmAZALIA_POWER_MANAGEMENT_CONTROL__SI 0x1733 -#define mmAZALIA_RIRB_AND_DP_CONTROL__SI 0x172D -#define mmAZALIA_RIRB_INTERRUPT_CONTROL__SI 0x173A -#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE__SI 0x1732 -#define mmAZALIA_UNSOLICITED_RESPONSE__SI 0x172E -#define mmAZALIA_WALL_CLOCK_LOAD__SI 0x1734 -#define mmAZALIA_WORSTCASE_LATENCY_COUNT__SI 0x1736 -#define mmAZ_TEST_DEBUG_DATA__SI 0x1756 -#define mmAZ_TEST_DEBUG_INDEX__SI 0x1755 -#define mmBACO_CNTL_MISC__CI__VI 0x14DB -#define mmBACO_CNTL__CI__VI 0x14E5 -#define mmBCI_DEBUG_READ__CI__VI 0x24EB -#define mmBCI_DEBUG_READ__SI 0x24E3 -#define mmBIF_AVP_FB_FLUSH__SI 0x1538 -#define mmBIF_BACO_DEBUG_LATCH__CI__VI 0x14DC -#define mmBIF_BACO_DEBUG__CI__VI 0x14DF -#define mmBIF_BACO_MSIC__CI 0x1480 -#define mmBIF_BUSNUM_CNTL1 0x1525 -#define mmBIF_BUSNUM_CNTL2 0x152B -#define mmBIF_BUSNUM_LIST0 0x1526 -#define mmBIF_BUSNUM_LIST1 0x1527 -#define mmBIF_BUSY_DELAY_CNTR 0x1529 -#define mmBIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI 0x1455 -#define mmBIF_CLK_PDWN_DELAY_TIMER__CI 0x1483 -#define mmBIF_CLK_PDWN_DELAY_TIMER__SI 0x151F -#define mmBIF_CLOCK_CNTL__SI 0x1510 -#define mmBIF_CP_FB_FLUSH__SI 0x1537 -#define mmBIF_DCT_FB_FLUSH__SI 0x1539 -#define mmBIF_DEBUG_CNTL 0x151C -#define mmBIF_DEBUG_MUX 0x151D -#define mmBIF_DEBUG_OUT 0x151E -#define mmBIF_DEVFUNCNUM_LIST0__CI__VI 0x14E8 -#define mmBIF_DEVFUNCNUM_LIST1__CI__VI 0x14E7 -#define mmBIF_DOORBELL_CNTL__CI__VI 0x14C3 -#define mmBIF_FB_EN 0x1524 -#define mmBIF_FEATURES_CONTROL_MISC__CI__VI 0x14C2 -#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI 0x1454 -#define mmBIF_IMPCTL_RXCNTL__CI__VI 0x1451 -#define mmBIF_IMPCTL_SMPLCNTL__CI__VI 0x1450 -#define mmBIF_IMPCTL_TXCNTL_pd__CI__VI 0x1452 -#define mmBIF_IMPCTL_TXCNTL_pu__CI__VI 0x1453 -#define mmBIF_LNCNT_RESET__CI 0x1488 -#define mmBIF_PERFCOUNTER0_RESULT__CI__VI 0x152D -#define mmBIF_PERFCOUNTER1_RESULT__CI__VI 0x152E -#define mmBIF_PERFMON_CNTL__CI__VI 0x152C -#define mmBIF_PIF_TXCLK_SWITCH_TIMER__CI 0x1481 -#define mmBIF_PINSTRAP0__SI 0x1507 -#define mmBIF_PWDN_COMMAND__CI__VI 0x1444 -#define mmBIF_PWDN_STATUS__CI__VI 0x1445 -#define mmBIF_RESET_CNTL__CI 0x1486 -#define mmBIF_RESET_EN__CI 0x1482 -#define mmBIF_RESET_EN__SI 0x1511 -#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI 0x1442 -#define mmBIF_RFE_IMPRST_CNTL__CI__VI 0x1458 -#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER__CI__VI 0x1443 -#define mmBIF_RFE_MMCFG_CNTL__CI__VI 0x144C -#define mmBIF_RFE_MST_BU_CMDSTATUS__CI__VI 0x1446 -#define mmBIF_RFE_MST_BX_CMDSTATUS__CI 0x1448 -#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI 0x1447 -#define mmBIF_RFE_MST_TMOUT_STATUS__CI__VI 0x144B -#define mmBIF_RFE_SNOOP_REG__CI__VI 0x0027 -#define mmBIF_RFE_SOFTRST_CNTL__CI__VI 0x1441 -#define mmBIF_SCRATCH0 0x150E -#define mmBIF_SCRATCH1 0x150F -#define mmBIF_SLAVE_PERF_COUNTER0__SI 0x152D -#define mmBIF_SLAVE_PERF_COUNTER1__SI 0x152E -#define mmBIF_SLAVE_PERF_COUNTER_CNTL__SI 0x152C -#define mmBIF_SLVARB_MODE__CI__VI 0x14C4 -#define mmBIF_SSA_DISP_LOWER__CI 0x14D2 -#define mmBIF_SSA_DISP_UPPER__CI 0x14D3 -#define mmBIF_SSA_GFX0_LOWER__CI 0x14CA -#define mmBIF_SSA_GFX0_UPPER__CI 0x14CB -#define mmBIF_SSA_GFX1_LOWER__CI 0x14CC -#define mmBIF_SSA_GFX1_UPPER__CI 0x14CD -#define mmBIF_SSA_GFX2_LOWER__CI 0x14CE -#define mmBIF_SSA_GFX2_UPPER__CI 0x14CF -#define mmBIF_SSA_GFX3_LOWER__CI 0x14D0 -#define mmBIF_SSA_GFX3_UPPER__CI 0x14D1 -#define mmBIF_SSA_MC_LOWER__CI 0x14D4 -#define mmBIF_SSA_MC_UPPER__CI 0x14D5 -#define mmBIF_SSA_PWR_STATUS__CI 0x14C8 -#define mmBIF_XDMA_HI__CI__VI 0x14C1 -#define mmBIF_XDMA_LO__CI__VI 0x14C0 -#define mmBIOS_SCRATCH_0 0x05C9 -#define mmBIOS_SCRATCH_1 0x05CA -#define mmBIOS_SCRATCH_10 0x05D3 -#define mmBIOS_SCRATCH_11 0x05D4 -#define mmBIOS_SCRATCH_12 0x05D5 -#define mmBIOS_SCRATCH_13 0x05D6 -#define mmBIOS_SCRATCH_14 0x05D7 -#define mmBIOS_SCRATCH_15 0x05D8 -#define mmBIOS_SCRATCH_2 0x05CB -#define mmBIOS_SCRATCH_3 0x05CC -#define mmBIOS_SCRATCH_4 0x05CD -#define mmBIOS_SCRATCH_5 0x05CE -#define mmBIOS_SCRATCH_6 0x05CF -#define mmBIOS_SCRATCH_7 0x05D0 -#define mmBIOS_SCRATCH_8 0x05D1 -#define mmBIOS_SCRATCH_9 0x05D2 -#define mmBL1_PWM_ABM_CNTL__SI 0x162E -#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL__SI 0x1628 -#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE__SI 0x162F -#define mmBL1_PWM_CURRENT_ABM_LEVEL__SI 0x162B -#define mmBL1_PWM_FINAL_DUTY_CYCLE__SI 0x162C -#define mmBL1_PWM_GRP2_REG_LOCK__SI 0x1630 -#define mmBL1_PWM_MINIMUM_DUTY_CYCLE__SI 0x162D -#define mmBL1_PWM_TARGET_ABM_LEVEL__SI 0x162A -#define mmBL1_PWM_USER_LEVEL__SI 0x1629 -#define mmBL_PWM_CNTL2__SI 0x1968 -#define mmBL_PWM_CNTL__SI 0x1967 -#define mmBL_PWM_GRP1_REG_LOCK__SI 0x196A -#define mmBL_PWM_PERIOD_CNTL__SI 0x1969 -#define mmBUS_CNTL 0x1508 -#define mmBWD_CHROMA_BOT_ADDR__SI 0x3894 -#define mmBWD_CHROMA_TOP_ADDR__SI 0x3893 -#define mmBWD_LUMA_BOT_ADDR__SI 0x3892 -#define mmBWD_LUMA_TOP_ADDR__SI 0x3891 -#define mmBX_RESET_EN__CI__VI 0x1514 -#define mmCAC_AGGR_LOWER__SI 0x0237 -#define mmCAC_AGGR_UPPER__SI 0x023E -#define mmCAC_SMC_IND_DATA__CI 0x0081 -#define mmCAC_SMC_IND_DATA_alt_1__CI 0x0083 -#define mmCAC_SMC_IND_DATA_alt_2__CI 0x0085 -#define mmCAC_SMC_IND_DATA_alt_3__CI 0x0087 -#define mmCAC_SMC_IND_INDEX__CI 0x0080 -#define mmCAC_SMC_IND_INDEX_alt_1__CI 0x0082 -#define mmCAC_SMC_IND_INDEX_alt_2__CI 0x0084 -#define mmCAC_SMC_IND_INDEX_alt_3__CI 0x0086 -#define mmCAC_THERMAL_STATUS__SI 0x0236 -#define mmCAC_THRESHOLD_LOWER__SI 0x0230 -#define mmCAC_THRESHOLD_UPPER__SI 0x0231 -#define mmCAP0_ANC0_OFFSET_HIGH__SI 0x02B4 -#define mmCAP0_ANC0_OFFSET__SI 0x02D2 -#define mmCAP0_ANC1_OFFSET_HIGH__SI 0x02B5 -#define mmCAP0_ANC1_OFFSET__SI 0x02D3 -#define mmCAP0_ANC2_OFFSET_HIGH__SI 0x02B6 -#define mmCAP0_ANC2_OFFSET__SI 0x02DC -#define mmCAP0_ANC3_OFFSET_HIGH__SI 0x02B7 -#define mmCAP0_ANC3_OFFSET__SI 0x02DD -#define mmCAP0_ANC_BUF01_BLOCK_CNT__SI 0x02D8 -#define mmCAP0_ANC_BUF23_BLOCK_CNT__SI 0x02D9 -#define mmCAP0_ANC_H_WINDOW__SI 0x02D4 -#define mmCAP0_BUF0_EVEN_OFFSET_HIGH__SI 0x02AD -#define mmCAP0_BUF0_EVEN_OFFSET__SI 0x02C5 -#define mmCAP0_BUF0_OFFSET_HIGH__SI 0x02AB -#define mmCAP0_BUF0_OFFSET__SI 0x02C3 -#define mmCAP0_BUF1_EVEN_OFFSET_HIGH__SI 0x02AE -#define mmCAP0_BUF1_EVEN_OFFSET__SI 0x02C6 -#define mmCAP0_BUF1_OFFSET_HIGH__SI 0x02AC -#define mmCAP0_BUF1_OFFSET__SI 0x02C4 -#define mmCAP0_BUF_PITCH__SI 0x02C7 -#define mmCAP0_BUF_STATUS__SI 0x02D7 -#define mmCAP0_CONFIG__SI 0x02D1 -#define mmCAP0_DEBUG__SI 0x02D0 -#define mmCAP0_H_WINDOW__SI 0x02C9 -#define mmCAP0_ONESHOT_BUF_OFFSET_HIGH__SI 0x02AF -#define mmCAP0_ONESHOT_BUF_OFFSET__SI 0x02D6 -#define mmCAP0_PORT_MODE_CNTL__SI 0x02CE -#define mmCAP0_TRIG_CNTL__SI 0x02CF -#define mmCAP0_VBI0_OFFSET_HIGH__SI 0x02B0 -#define mmCAP0_VBI0_OFFSET__SI 0x02CA -#define mmCAP0_VBI1_OFFSET_HIGH__SI 0x02B1 -#define mmCAP0_VBI1_OFFSET__SI 0x02CB -#define mmCAP0_VBI2_OFFSET_HIGH__SI 0x02B2 -#define mmCAP0_VBI2_OFFSET__SI 0x02DA -#define mmCAP0_VBI3_OFFSET_HIGH__SI 0x02B3 -#define mmCAP0_VBI3_OFFSET__SI 0x02DB -#define mmCAP0_VBI_H_WINDOW__SI 0x02CD -#define mmCAP0_VBI_V_WINDOW__SI 0x02CC -#define mmCAP0_VIDEO_SYNC_TEST__SI 0x02D5 -#define mmCAP0_V_WINDOW__SI 0x02C8 -#define mmCAP0_WR_BUFFER_STAT__SI 0x02AA -#define mmCAPTURE_HOST_BUSNUM 0x153C -#define mmCAPTURE_START_STATUS__SI 0x1840 -#define mmCAP_DEBUG__SI 0x02BC -#define mmCAP_INT_CNTL__SI 0x02C1 -#define mmCAP_INT_STATUS__SI 0x02C2 -#define mmCB_BLEND0_CONTROL 0xA1E0 -#define mmCB_BLEND1_CONTROL 0xA1E1 -#define mmCB_BLEND2_CONTROL 0xA1E2 -#define mmCB_BLEND3_CONTROL 0xA1E3 -#define mmCB_BLEND4_CONTROL 0xA1E4 -#define mmCB_BLEND5_CONTROL 0xA1E5 -#define mmCB_BLEND6_CONTROL 0xA1E6 -#define mmCB_BLEND7_CONTROL 0xA1E7 -#define mmCB_BLEND_ALPHA 0xA108 -#define mmCB_BLEND_BLUE 0xA107 -#define mmCB_BLEND_GREEN 0xA106 -#define mmCB_BLEND_RED 0xA105 -#define mmCB_CGTT_SCLK_CTRL__CI__VI 0xF0A8 -#define mmCB_CGTT_SCLK_CTRL__SI 0x2698 -#define mmCB_COLOR0_ATTRIB 0xA31D -#define mmCB_COLOR0_BASE 0xA318 -#define mmCB_COLOR0_CLEAR_WORD0 0xA323 -#define mmCB_COLOR0_CLEAR_WORD1 0xA324 -#define mmCB_COLOR0_CMASK 0xA31F -#define mmCB_COLOR0_CMASK_SLICE 0xA320 -#define mmCB_COLOR0_FMASK 0xA321 -#define mmCB_COLOR0_FMASK_SLICE 0xA322 -#define mmCB_COLOR0_INFO 0xA31C -#define mmCB_COLOR0_PITCH 0xA319 -#define mmCB_COLOR0_SLICE 0xA31A -#define mmCB_COLOR0_VIEW 0xA31B -#define mmCB_COLOR1_ATTRIB 0xA32C -#define mmCB_COLOR1_BASE 0xA327 -#define mmCB_COLOR1_CLEAR_WORD0 0xA332 -#define mmCB_COLOR1_CLEAR_WORD1 0xA333 -#define mmCB_COLOR1_CMASK 0xA32E -#define mmCB_COLOR1_CMASK_SLICE 0xA32F -#define mmCB_COLOR1_FMASK 0xA330 -#define mmCB_COLOR1_FMASK_SLICE 0xA331 -#define mmCB_COLOR1_INFO 0xA32B -#define mmCB_COLOR1_PITCH 0xA328 -#define mmCB_COLOR1_SLICE 0xA329 -#define mmCB_COLOR1_VIEW 0xA32A -#define mmCB_COLOR2_ATTRIB 0xA33B -#define mmCB_COLOR2_BASE 0xA336 -#define mmCB_COLOR2_CLEAR_WORD0 0xA341 -#define mmCB_COLOR2_CLEAR_WORD1 0xA342 -#define mmCB_COLOR2_CMASK 0xA33D -#define mmCB_COLOR2_CMASK_SLICE 0xA33E -#define mmCB_COLOR2_FMASK 0xA33F -#define mmCB_COLOR2_FMASK_SLICE 0xA340 -#define mmCB_COLOR2_INFO 0xA33A -#define mmCB_COLOR2_PITCH 0xA337 -#define mmCB_COLOR2_SLICE 0xA338 -#define mmCB_COLOR2_VIEW 0xA339 -#define mmCB_COLOR3_ATTRIB 0xA34A -#define mmCB_COLOR3_BASE 0xA345 -#define mmCB_COLOR3_CLEAR_WORD0 0xA350 -#define mmCB_COLOR3_CLEAR_WORD1 0xA351 -#define mmCB_COLOR3_CMASK 0xA34C -#define mmCB_COLOR3_CMASK_SLICE 0xA34D -#define mmCB_COLOR3_FMASK 0xA34E -#define mmCB_COLOR3_FMASK_SLICE 0xA34F -#define mmCB_COLOR3_INFO 0xA349 -#define mmCB_COLOR3_PITCH 0xA346 -#define mmCB_COLOR3_SLICE 0xA347 -#define mmCB_COLOR3_VIEW 0xA348 -#define mmCB_COLOR4_ATTRIB 0xA359 -#define mmCB_COLOR4_BASE 0xA354 -#define mmCB_COLOR4_CLEAR_WORD0 0xA35F -#define mmCB_COLOR4_CLEAR_WORD1 0xA360 -#define mmCB_COLOR4_CMASK 0xA35B -#define mmCB_COLOR4_CMASK_SLICE 0xA35C -#define mmCB_COLOR4_FMASK 0xA35D -#define mmCB_COLOR4_FMASK_SLICE 0xA35E -#define mmCB_COLOR4_INFO 0xA358 -#define mmCB_COLOR4_PITCH 0xA355 -#define mmCB_COLOR4_SLICE 0xA356 -#define mmCB_COLOR4_VIEW 0xA357 -#define mmCB_COLOR5_ATTRIB 0xA368 -#define mmCB_COLOR5_BASE 0xA363 -#define mmCB_COLOR5_CLEAR_WORD0 0xA36E -#define mmCB_COLOR5_CLEAR_WORD1 0xA36F -#define mmCB_COLOR5_CMASK 0xA36A -#define mmCB_COLOR5_CMASK_SLICE 0xA36B -#define mmCB_COLOR5_FMASK 0xA36C -#define mmCB_COLOR5_FMASK_SLICE 0xA36D -#define mmCB_COLOR5_INFO 0xA367 -#define mmCB_COLOR5_PITCH 0xA364 -#define mmCB_COLOR5_SLICE 0xA365 -#define mmCB_COLOR5_VIEW 0xA366 -#define mmCB_COLOR6_ATTRIB 0xA377 -#define mmCB_COLOR6_BASE 0xA372 -#define mmCB_COLOR6_CLEAR_WORD0 0xA37D -#define mmCB_COLOR6_CLEAR_WORD1 0xA37E -#define mmCB_COLOR6_CMASK 0xA379 -#define mmCB_COLOR6_CMASK_SLICE 0xA37A -#define mmCB_COLOR6_FMASK 0xA37B -#define mmCB_COLOR6_FMASK_SLICE 0xA37C -#define mmCB_COLOR6_INFO 0xA376 -#define mmCB_COLOR6_PITCH 0xA373 -#define mmCB_COLOR6_SLICE 0xA374 -#define mmCB_COLOR6_VIEW 0xA375 -#define mmCB_COLOR7_ATTRIB 0xA386 -#define mmCB_COLOR7_BASE 0xA381 -#define mmCB_COLOR7_CLEAR_WORD0 0xA38C -#define mmCB_COLOR7_CLEAR_WORD1 0xA38D -#define mmCB_COLOR7_CMASK 0xA388 -#define mmCB_COLOR7_CMASK_SLICE 0xA389 -#define mmCB_COLOR7_FMASK 0xA38A -#define mmCB_COLOR7_FMASK_SLICE 0xA38B -#define mmCB_COLOR7_INFO 0xA385 -#define mmCB_COLOR7_PITCH 0xA382 -#define mmCB_COLOR7_SLICE 0xA383 -#define mmCB_COLOR7_VIEW 0xA384 -#define mmCB_COLOR_CONTROL 0xA202 -#define mmCB_DEBUG_BUS_1 0x2699 -#define mmCB_DEBUG_BUS_10 0x26A2 -#define mmCB_DEBUG_BUS_11 0x26A3 -#define mmCB_DEBUG_BUS_12 0x26A4 -#define mmCB_DEBUG_BUS_13 0x26A5 -#define mmCB_DEBUG_BUS_14 0x26A6 -#define mmCB_DEBUG_BUS_15 0x26A7 -#define mmCB_DEBUG_BUS_16 0x26A8 -#define mmCB_DEBUG_BUS_17 0x26A9 -#define mmCB_DEBUG_BUS_18 0x26AA -#define mmCB_DEBUG_BUS_2 0x269A -#define mmCB_DEBUG_BUS_3 0x269B -#define mmCB_DEBUG_BUS_4 0x269C -#define mmCB_DEBUG_BUS_5 0x269D -#define mmCB_DEBUG_BUS_6 0x269E -#define mmCB_DEBUG_BUS_7 0x269F -#define mmCB_DEBUG_BUS_8 0x26A0 -#define mmCB_DEBUG_BUS_9 0x26A1 -#define mmCB_HW_CONTROL 0x2684 -#define mmCB_HW_CONTROL_1 0x2685 -#define mmCB_HW_CONTROL_2 0x2686 -#define mmCB_HW_CONTROL_3__CI__VI 0x2683 -#define mmCB_PERFCOUNTER0_HI__CI__VI 0xD407 -#define mmCB_PERFCOUNTER0_HI__SI 0x2691 -#define mmCB_PERFCOUNTER0_LO__CI__VI 0xD406 -#define mmCB_PERFCOUNTER0_LO__SI 0x2690 -#define mmCB_PERFCOUNTER0_SELECT0__SI 0x2688 -#define mmCB_PERFCOUNTER0_SELECT1__CI__VI 0xDC02 -#define mmCB_PERFCOUNTER0_SELECT1__SI 0x2689 -#define mmCB_PERFCOUNTER0_SELECT__CI__VI 0xDC01 -#define mmCB_PERFCOUNTER1_HI__CI__VI 0xD409 -#define mmCB_PERFCOUNTER1_HI__SI 0x2693 -#define mmCB_PERFCOUNTER1_LO__CI__VI 0xD408 -#define mmCB_PERFCOUNTER1_LO__SI 0x2692 -#define mmCB_PERFCOUNTER1_SELECT0__SI 0x268A -#define mmCB_PERFCOUNTER1_SELECT1__SI 0x268B -#define mmCB_PERFCOUNTER1_SELECT__CI__VI 0xDC03 -#define mmCB_PERFCOUNTER2_HI__CI__VI 0xD40B -#define mmCB_PERFCOUNTER2_HI__SI 0x2695 -#define mmCB_PERFCOUNTER2_LO__CI__VI 0xD40A -#define mmCB_PERFCOUNTER2_LO__SI 0x2694 -#define mmCB_PERFCOUNTER2_SELECT0__SI 0x268C -#define mmCB_PERFCOUNTER2_SELECT1__SI 0x268D -#define mmCB_PERFCOUNTER2_SELECT__CI__VI 0xDC04 -#define mmCB_PERFCOUNTER3_HI__CI__VI 0xD40D -#define mmCB_PERFCOUNTER3_HI__SI 0x2697 -#define mmCB_PERFCOUNTER3_LO__CI__VI 0xD40C -#define mmCB_PERFCOUNTER3_LO__SI 0x2696 -#define mmCB_PERFCOUNTER3_SELECT0__SI 0x268E -#define mmCB_PERFCOUNTER3_SELECT1__SI 0x268F -#define mmCB_PERFCOUNTER3_SELECT__CI__VI 0xDC05 -#define mmCB_PERFCOUNTER_FILTER__CI__VI 0xDC00 -#define mmCB_SHADER_MASK 0xA08F -#define mmCB_TARGET_MASK 0xA08E -#define mmCC_BIF_AZALIA_ID__CI 0x14A9 -#define mmCC_BIF_AZALIA_ID__SI 0x152A -#define mmCC_BIF_BU_PINSTRAP0__CI 0x14AC -#define mmCC_BIF_BX_FUSESTRAP0__CI__VI 0x14D7 -#define mmCC_BIF_BX_PINSTRAP0__CI__VI 0x1507 -#define mmCC_BIF_BX_STRAP0__CI__VI 0x14E1 -#define mmCC_BIF_BX_STRAP1__CI__VI 0x14E2 -#define mmCC_BIF_EFUSE0__SI 0x1504 -#define mmCC_BIF_EFUSE1__SI 0x1505 -#define mmCC_BIF_EFUSE2__SI 0x1523 -#define mmCC_BIF_ID_STRAPS__CI 0x14AA -#define mmCC_BIF_ID_STRAPS__SI 0x1506 -#define mmCC_BIF_ROMSTRAP0__SI 0x1500 -#define mmCC_BIF_ROMSTRAP1__SI 0x1501 -#define mmCC_BIF_ROMSTRAP2__SI 0x1502 -#define mmCC_BIF_ROMSTRAP3__SI 0x1503 -#define mmCC_BIF_ROMSTRAP4__SI 0x1521 -#define mmCC_BIF_ROMSTRAP5__SI 0x1522 -#define mmCC_BIF_SECURE_CNTL__CI__VI 0x14E3 -#define mmCC_BIF_STRAP0__CI 0x14BF -#define mmCC_BIF_STRAP1__CI 0x14BE -#define mmCC_BIF_STRAP2__CI 0x14BD -#define mmCC_BIF_STRAP3__CI 0x14BC -#define mmCC_BIF_STRAP4__CI 0x14BB -#define mmCC_BIF_STRAP5__CI 0x14BA -#define mmCC_BIF_STRAP6__CI 0x14B9 -#define mmCC_BIF_STRAP7__CI 0x14B8 -#define mmCC_BIF_STRAP8__CI 0x14B7 -#define mmCC_BIF_STRAP9__CI 0x14B6 -#define mmCC_BIF_STRAP_FUSE0__CI 0x14AB -#define mmCC_DC_MISC_STRAPS__SI 0x1955 -#define mmCC_DRM_ID_STRAPS 0x1559 -#define mmCC_GC_EDC_CONFIG__CI__VI 0x3098 -#define mmCC_GC_PRIM_CONFIG__CI__VI 0x2240 -#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226F -#define mmCC_MC_MAX_CHANNEL 0x096E -#define mmCC_RB_BACKEND_DISABLE 0x263D -#define mmCC_RB_DAISY_CHAIN 0x2641 -#define mmCC_RB_REDUNDANCY 0x263C -#define mmCC_RCU_CG_STRAPS__SI 0x0050 -#define mmCC_RCU_CMON_STRAPS__SI 0x0055 -#define mmCC_RCU_DC_MISC_STRAPS__SI 0x005E -#define mmCC_RCU_DC_PIPE_DIS__SI 0x005F -#define mmCC_RCU_DYN_RM2__SI 0x0052 -#define mmCC_RCU_DYN_RM__SI 0x0051 -#define mmCC_RCU_ID_STRAPS__SI 0x004C -#define mmCC_RCU_MISC_STRAPS__SI 0x005D -#define mmCC_RCU_TMON_STRAPS__SI 0x0053 -#define mmCC_SQC_BANK_DISABLE 0x2307 -#define mmCC_SYS_RB_BACKEND_DISABLE 0x03A0 -#define mmCC_SYS_RB_REDUNDANCY 0x039F -#define mmCC_TST_EFUSE0_RM 0x0060 -#define mmCC_TST_EFUSE1_MISC 0x0061 -#define mmCEC_ADDR__CI__VI 0x0003 -#define mmCEC_CONTROL__CI__VI 0x0001 -#define mmCEC_DATA_LENGTH__CI__VI 0x0004 -#define mmCEC_HPD_CONTROL__CI__VI 0x0006 -#define mmCEC_HPD_TOGGLE_FILT_CONTROL__CI__VI 0x0007 -#define mmCEC_INT_EN__CI__VI 0x0002 -#define mmCEC_MISC__CI__VI 0x0005 -#define mmCEC_PAD_CNTL__CI__VI 0x000E -#define mmCEC_RX_DATA_0__CI__VI 0x0010 -#define mmCEC_RX_DATA_1__CI__VI 0x0011 -#define mmCEC_RX_DATA_2__CI__VI 0x0012 -#define mmCEC_RX_DATA_3__CI__VI 0x0013 -#define mmCEC_SCRATCH_REG_0__CI__VI 0x0014 -#define mmCEC_SCRATCH_REG_1__CI__VI 0x0015 -#define mmCEC_SCRATCH_REG_2__CI__VI 0x0016 -#define mmCEC_SCRATCH_REG_3__CI__VI 0x0017 -#define mmCEC_SCRATCH_REG_4__CI__VI 0x0018 -#define mmCEC_SCRATCH_REG_5__CI__VI 0x0019 -#define mmCEC_STATUS__CI__VI 0x0000 -#define mmCEC_SW_OPCODE_0__CI__VI 0x000C -#define mmCEC_SW_OPCODE_1__CI__VI 0x000D -#define mmCEC_TX_DATA_0__CI__VI 0x0008 -#define mmCEC_TX_DATA_1__CI__VI 0x0009 -#define mmCEC_TX_DATA_2__CI__VI 0x000A -#define mmCEC_TX_DATA_3__CI__VI 0x000B -#define mmCGTS_CU0_LDS_SQ_CTRL_REG__CI__VI 0xF009 -#define mmCGTS_CU0_SP0_CTRL_REG__CI__VI 0xF008 -#define mmCGTS_CU0_SP1_CTRL_REG__CI__VI 0xF00B -#define mmCGTS_CU0_TA_SQC_CTRL_REG__CI__VI 0xF00A -#define mmCGTS_CU0_TD_TCP_CTRL_REG__CI__VI 0xF00C -#define mmCGTS_CU10_LDS_SQ_CTRL_REG__CI__VI 0xF03B -#define mmCGTS_CU10_SP0_CTRL_REG__CI__VI 0xF03A -#define mmCGTS_CU10_SP1_CTRL_REG__CI__VI 0xF03D -#define mmCGTS_CU10_TA_CTRL_REG__CI__VI 0xF03C -#define mmCGTS_CU10_TD_TCP_CTRL_REG__CI__VI 0xF03E -#define mmCGTS_CU11_LDS_SQ_CTRL_REG__CI__VI 0xF040 -#define mmCGTS_CU11_SP0_CTRL_REG__CI__VI 0xF03F -#define mmCGTS_CU11_SP1_CTRL_REG__CI__VI 0xF042 -#define mmCGTS_CU11_TA_CTRL_REG__CI__VI 0xF041 -#define mmCGTS_CU11_TD_TCP_CTRL_REG__CI__VI 0xF043 -#define mmCGTS_CU12_LDS_SQ_CTRL_REG__CI__VI 0xF045 -#define mmCGTS_CU12_SP0_CTRL_REG__CI__VI 0xF044 -#define mmCGTS_CU12_SP1_CTRL_REG__CI__VI 0xF047 -#define mmCGTS_CU12_TA_SQC_CTRL_REG__CI__VI 0xF046 -#define mmCGTS_CU12_TD_TCP_CTRL_REG__CI__VI 0xF048 -#define mmCGTS_CU13_LDS_SQ_CTRL_REG__CI__VI 0xF04A -#define mmCGTS_CU13_SP0_CTRL_REG__CI__VI 0xF049 -#define mmCGTS_CU13_SP1_CTRL_REG__CI__VI 0xF04C -#define mmCGTS_CU13_TA_CTRL_REG__CI__VI 0xF04B -#define mmCGTS_CU13_TD_TCP_CTRL_REG__CI__VI 0xF04D -#define mmCGTS_CU14_LDS_SQ_CTRL_REG__CI__VI 0xF04F -#define mmCGTS_CU14_SP0_CTRL_REG__CI__VI 0xF04E -#define mmCGTS_CU14_SP1_CTRL_REG__CI__VI 0xF051 -#define mmCGTS_CU14_TA_CTRL_REG__CI__VI 0xF050 -#define mmCGTS_CU14_TD_TCP_CTRL_REG__CI__VI 0xF052 -#define mmCGTS_CU15_LDS_SQ_CTRL_REG__CI__VI 0xF054 -#define mmCGTS_CU15_SP0_CTRL_REG__CI__VI 0xF053 -#define mmCGTS_CU15_SP1_CTRL_REG__CI__VI 0xF056 -#define mmCGTS_CU15_TA_CTRL_REG__CI__VI 0xF055 -#define mmCGTS_CU15_TD_TCP_CTRL_REG__CI__VI 0xF057 -#define mmCGTS_CU1_LDS_SQ_CTRL_REG__CI__VI 0xF00E -#define mmCGTS_CU1_SP0_CTRL_REG__CI__VI 0xF00D -#define mmCGTS_CU1_SP1_CTRL_REG__CI__VI 0xF010 -#define mmCGTS_CU1_TA_CTRL_REG__CI__VI 0xF00F -#define mmCGTS_CU1_TD_TCP_CTRL_REG__CI__VI 0xF011 -#define mmCGTS_CU2_LDS_SQ_CTRL_REG__CI__VI 0xF013 -#define mmCGTS_CU2_SP0_CTRL_REG__CI__VI 0xF012 -#define mmCGTS_CU2_SP1_CTRL_REG__CI__VI 0xF015 -#define mmCGTS_CU2_TA_CTRL_REG__CI__VI 0xF014 -#define mmCGTS_CU2_TD_TCP_CTRL_REG__CI__VI 0xF016 -#define mmCGTS_CU3_LDS_SQ_CTRL_REG__CI__VI 0xF018 -#define mmCGTS_CU3_SP0_CTRL_REG__CI__VI 0xF017 -#define mmCGTS_CU3_SP1_CTRL_REG__CI__VI 0xF01A -#define mmCGTS_CU3_TA_CTRL_REG__CI__VI 0xF019 -#define mmCGTS_CU3_TD_TCP_CTRL_REG__CI__VI 0xF01B -#define mmCGTS_CU4_LDS_SQ_CTRL_REG__CI__VI 0xF01D -#define mmCGTS_CU4_SP0_CTRL_REG__CI__VI 0xF01C -#define mmCGTS_CU4_SP1_CTRL_REG__CI__VI 0xF01F -#define mmCGTS_CU4_TA_SQC_CTRL_REG__CI__VI 0xF01E -#define mmCGTS_CU4_TD_TCP_CTRL_REG__CI__VI 0xF020 -#define mmCGTS_CU5_LDS_SQ_CTRL_REG__CI__VI 0xF022 -#define mmCGTS_CU5_SP0_CTRL_REG__CI__VI 0xF021 -#define mmCGTS_CU5_SP1_CTRL_REG__CI__VI 0xF024 -#define mmCGTS_CU5_TA_CTRL_REG__CI__VI 0xF023 -#define mmCGTS_CU5_TD_TCP_CTRL_REG__CI__VI 0xF025 -#define mmCGTS_CU6_LDS_SQ_CTRL_REG__CI__VI 0xF027 -#define mmCGTS_CU6_SP0_CTRL_REG__CI__VI 0xF026 -#define mmCGTS_CU6_SP1_CTRL_REG__CI__VI 0xF029 -#define mmCGTS_CU6_TA_CTRL_REG__CI__VI 0xF028 -#define mmCGTS_CU6_TD_TCP_CTRL_REG__CI__VI 0xF02A -#define mmCGTS_CU7_LDS_SQ_CTRL_REG__CI__VI 0xF02C -#define mmCGTS_CU7_SP0_CTRL_REG__CI__VI 0xF02B -#define mmCGTS_CU7_SP1_CTRL_REG__CI__VI 0xF02E -#define mmCGTS_CU7_TA_CTRL_REG__CI__VI 0xF02D -#define mmCGTS_CU7_TD_TCP_CTRL_REG__CI__VI 0xF02F -#define mmCGTS_CU8_LDS_SQ_CTRL_REG__CI__VI 0xF031 -#define mmCGTS_CU8_SP0_CTRL_REG__CI__VI 0xF030 -#define mmCGTS_CU8_SP1_CTRL_REG__CI__VI 0xF033 -#define mmCGTS_CU8_TA_SQC_CTRL_REG__CI__VI 0xF032 -#define mmCGTS_CU8_TD_TCP_CTRL_REG__CI__VI 0xF034 -#define mmCGTS_CU9_LDS_SQ_CTRL_REG__CI__VI 0xF036 -#define mmCGTS_CU9_SP0_CTRL_REG__CI__VI 0xF035 -#define mmCGTS_CU9_SP1_CTRL_REG__CI__VI 0xF038 -#define mmCGTS_CU9_TA_CTRL_REG__CI__VI 0xF037 -#define mmCGTS_CU9_TD_TCP_CTRL_REG__CI__VI 0xF039 -#define mmCGTS_RD_CTRL_REG__CI__VI 0xF001 -#define mmCGTS_RD_CTRL_REG__SI 0x2455 -#define mmCGTS_RD_REG__CI__VI 0xF002 -#define mmCGTS_RD_REG__SI 0x2456 -#define mmCGTS_S0C0_LDS_SQ_CTRL_REG__SI 0x2459 -#define mmCGTS_S0C0_SP0_CTRL_REG__SI 0x2458 -#define mmCGTS_S0C0_SP1_CTRL_REG__SI 0x245B -#define mmCGTS_S0C0_TA_SQC_CTRL_REG__SI 0x245A -#define mmCGTS_S0C0_TD_TCP_CTRL_REG__SI 0x245C -#define mmCGTS_S0C1_LDS_SQ_CTRL_REG__SI 0x245E -#define mmCGTS_S0C1_SP0_CTRL_REG__SI 0x245D -#define mmCGTS_S0C1_SP1_CTRL_REG__SI 0x2460 -#define mmCGTS_S0C1_TA_CTRL_REG__SI 0x245F -#define mmCGTS_S0C1_TD_TCP_CTRL_REG__SI 0x2461 -#define mmCGTS_S0C2_LDS_SQ_CTRL_REG__SI 0x2463 -#define mmCGTS_S0C2_SP0_CTRL_REG__SI 0x2462 -#define mmCGTS_S0C2_SP1_CTRL_REG__SI 0x2465 -#define mmCGTS_S0C2_TA_CTRL_REG__SI 0x2464 -#define mmCGTS_S0C2_TD_TCP_CTRL_REG__SI 0x2466 -#define mmCGTS_S0C3_LDS_SQ_CTRL_REG__SI 0x2468 -#define mmCGTS_S0C3_SP0_CTRL_REG__SI 0x2467 -#define mmCGTS_S0C3_SP1_CTRL_REG__SI 0x246A -#define mmCGTS_S0C3_TA_CTRL_REG__SI 0x2469 -#define mmCGTS_S0C3_TD_TCP_CTRL_REG__SI 0x246B -#define mmCGTS_S0C4_LDS_SQ_CTRL_REG__SI 0x246D -#define mmCGTS_S0C4_SP0_CTRL_REG__SI 0x246C -#define mmCGTS_S0C4_SP1_CTRL_REG__SI 0x246F -#define mmCGTS_S0C4_TA_SQC_CTRL_REG__SI 0x246E -#define mmCGTS_S0C4_TD_TCP_CTRL_REG__SI 0x2470 -#define mmCGTS_S0C5_LDS_SQ_CTRL_REG__SI 0x2472 -#define mmCGTS_S0C5_SP0_CTRL_REG__SI 0x2471 -#define mmCGTS_S0C5_SP1_CTRL_REG__SI 0x2474 -#define mmCGTS_S0C5_TA_CTRL_REG__SI 0x2473 -#define mmCGTS_S0C5_TD_TCP_CTRL_REG__SI 0x2475 -#define mmCGTS_S0C6_LDS_SQ_CTRL_REG__SI 0x2477 -#define mmCGTS_S0C6_SP0_CTRL_REG__SI 0x2476 -#define mmCGTS_S0C6_SP1_CTRL_REG__SI 0x2479 -#define mmCGTS_S0C6_TA_CTRL_REG__SI 0x2478 -#define mmCGTS_S0C6_TD_TCP_CTRL_REG__SI 0x247A -#define mmCGTS_S0C7_LDS_SQ_CTRL_REG__SI 0x247C -#define mmCGTS_S0C7_SP0_CTRL_REG__SI 0x247B -#define mmCGTS_S0C7_SP1_CTRL_REG__SI 0x247E -#define mmCGTS_S0C7_TA_CTRL_REG__SI 0x247D -#define mmCGTS_S0C7_TD_TCP_CTRL_REG__SI 0x247F -#define mmCGTS_S1C0_LDS_SQ_CTRL_REG__SI 0x2481 -#define mmCGTS_S1C0_SP0_CTRL_REG__SI 0x2480 -#define mmCGTS_S1C0_SP1_CTRL_REG__SI 0x2483 -#define mmCGTS_S1C0_TA_SQC_CTRL_REG__SI 0x2482 -#define mmCGTS_S1C0_TD_TCP_CTRL_REG__SI 0x2484 -#define mmCGTS_S1C1_LDS_SQ_CTRL_REG__SI 0x2486 -#define mmCGTS_S1C1_SP0_CTRL_REG__SI 0x2485 -#define mmCGTS_S1C1_SP1_CTRL_REG__SI 0x2488 -#define mmCGTS_S1C1_TA_CTRL_REG__SI 0x2487 -#define mmCGTS_S1C1_TD_TCP_CTRL_REG__SI 0x2489 -#define mmCGTS_S1C2_LDS_SQ_CTRL_REG__SI 0x248B -#define mmCGTS_S1C2_SP0_CTRL_REG__SI 0x248A -#define mmCGTS_S1C2_SP1_CTRL_REG__SI 0x248D -#define mmCGTS_S1C2_TA_CTRL_REG__SI 0x248C -#define mmCGTS_S1C2_TD_TCP_CTRL_REG__SI 0x248E -#define mmCGTS_S1C3_LDS_SQ_CTRL_REG__SI 0x2490 -#define mmCGTS_S1C3_SP0_CTRL_REG__SI 0x248F -#define mmCGTS_S1C3_SP1_CTRL_REG__SI 0x2492 -#define mmCGTS_S1C3_TA_CTRL_REG__SI 0x2491 -#define mmCGTS_S1C3_TD_TCP_CTRL_REG__SI 0x2493 -#define mmCGTS_S1C4_LDS_SQ_CTRL_REG__SI 0x2495 -#define mmCGTS_S1C4_SP0_CTRL_REG__SI 0x2494 -#define mmCGTS_S1C4_SP1_CTRL_REG__SI 0x2497 -#define mmCGTS_S1C4_TA_SQC_CTRL_REG__SI 0x2496 -#define mmCGTS_S1C4_TD_TCP_CTRL_REG__SI 0x2498 -#define mmCGTS_S1C5_LDS_SQ_CTRL_REG__SI 0x249A -#define mmCGTS_S1C5_SP0_CTRL_REG__SI 0x2499 -#define mmCGTS_S1C5_SP1_CTRL_REG__SI 0x249C -#define mmCGTS_S1C5_TA_CTRL_REG__SI 0x249B -#define mmCGTS_S1C5_TD_TCP_CTRL_REG__SI 0x249D -#define mmCGTS_S1C6_LDS_SQ_CTRL_REG__SI 0x249F -#define mmCGTS_S1C6_SP0_CTRL_REG__SI 0x249E -#define mmCGTS_S1C6_SP1_CTRL_REG__SI 0x24A1 -#define mmCGTS_S1C6_TA_CTRL_REG__SI 0x24A0 -#define mmCGTS_S1C6_TD_TCP_CTRL_REG__SI 0x24A2 -#define mmCGTS_S1C7_LDS_SQ_CTRL_REG__SI 0x24A4 -#define mmCGTS_S1C7_SP0_CTRL_REG__SI 0x24A3 -#define mmCGTS_S1C7_SP1_CTRL_REG__SI 0x24A6 -#define mmCGTS_S1C7_TA_CTRL_REG__SI 0x24A5 -#define mmCGTS_S1C7_TD_TCP_CTRL_REG__SI 0x24A7 -#define mmCGTS_SM_CTRL_REG__CI__VI 0xF000 -#define mmCGTS_SM_CTRL_REG__SI 0x2454 -#define mmCGTS_TCC_DISABLE__CI__VI 0xF003 -#define mmCGTS_TCC_DISABLE__SI 0x2452 -#define mmCGTS_USER_TCC_DISABLE__CI__VI 0xF004 -#define mmCGTS_USER_TCC_DISABLE__SI 0x2453 -#define mmCGTT_BCI_CLK_CTRL__CI__VI 0xF082 -#define mmCGTT_BCI_CLK_CTRL__SI 0x24A9 -#define mmCGTT_BIF_CLK_CTRL0__SI 0x1512 -#define mmCGTT_CPC_CLK_CTRL__CI__VI 0xF0B2 -#define mmCGTT_CPF_CLK_CTRL__CI__VI 0xF0B1 -#define mmCGTT_CP_CLK_CTRL__CI__VI 0xF0B0 -#define mmCGTT_CP_CLK_CTRL__SI 0x3059 -#define mmCGTT_DRM_CLK_CTRL0 0x1579 -#define mmCGTT_GDS_CLK_CTRL__CI__VI 0xF0A0 -#define mmCGTT_GDS_CLK_CTRL__SI 0x25DD -#define mmCGTT_IA_CLK_CTRL__CI__VI 0xF085 -#define mmCGTT_IA_CLK_CTRL__SI 0x2261 -#define mmCGTT_PA_CLK_CTRL__CI__VI 0xF088 -#define mmCGTT_PA_CLK_CTRL__SI 0x2286 -#define mmCGTT_PC_CLK_CTRL__CI__VI 0xF081 -#define mmCGTT_PC_CLK_CTRL__SI 0x24A8 -#define mmCGTT_RLC_CLK_CTRL__CI__VI 0xF0B8 -#define mmCGTT_RLC_CLK_CTRL__SI 0x30E0 -#define mmCGTT_ROM_CLK_CTRL0__SI 0x0583 -#define mmCGTT_SC_CLK_CTRL__CI__VI 0xF089 -#define mmCGTT_SC_CLK_CTRL__SI 0x22CA -#define mmCGTT_SPI_CLK_CTRL__CI__VI 0xF080 -#define mmCGTT_SPI_CLK_CTRL__SI 0x2451 -#define mmCGTT_SQG_CLK_CTRL__CI__VI 0xF08D -#define mmCGTT_SQG_CLK_CTRL__SI 0x2363 -#define mmCGTT_SQ_CLK_CTRL__CI__VI 0xF08C -#define mmCGTT_SQ_CLK_CTRL__SI 0x2362 -#define mmCGTT_SX_CLK_CTRL0__CI__VI 0xF094 -#define mmCGTT_SX_CLK_CTRL0__SI 0x240C -#define mmCGTT_SX_CLK_CTRL1__CI__VI 0xF095 -#define mmCGTT_SX_CLK_CTRL1__SI 0x240D -#define mmCGTT_SX_CLK_CTRL2__CI__VI 0xF096 -#define mmCGTT_SX_CLK_CTRL2__SI 0x240E -#define mmCGTT_SX_CLK_CTRL3__CI__VI 0xF097 -#define mmCGTT_SX_CLK_CTRL3__SI 0x240F -#define mmCGTT_SX_CLK_CTRL4__CI__VI 0xF098 -#define mmCGTT_SX_CLK_CTRL4__SI 0x2410 -#define mmCGTT_TCI_CLK_CTRL__CI__VI 0xF09F -#define mmCGTT_TCI_CLK_CTRL__SI 0x2B60 -#define mmCGTT_TCP_CLK_CTRL__CI__VI 0xF09E -#define mmCGTT_TCP_CLK_CTRL__SI 0x2B15 -#define mmCGTT_VGT_CLK_CTRL__CI__VI 0xF084 -#define mmCGTT_VGT_CLK_CTRL__SI 0x225F -#define mmCGTT_WD_CLK_CTRL__CI__VI 0xF086 -#define mmCG_AZ_REQ_AND_RSP__SI 0x021A -#define mmCG_BIF_REQ_AND_RSP__SI 0x0218 -#define mmCG_BUSY_SAMPLING_PARAMETERS__SI 0x01FF -#define mmCG_CAC_CTRL__SI 0x022E -#define mmCG_CHRONO_31_0__SI 0x0238 -#define mmCG_CHRONO_63_32__SI 0x0239 -#define mmCG_CLKPIN_CNTL__SI 0x0198 -#define mmCG_DC_REQ_AND_RSP__SI 0x0219 -#define mmCG_DISPLAY_GAP_CNTL__SI 0x020A -#define mmCG_FDO_CTRL0__SI 0x01D5 -#define mmCG_FDO_CTRL1__SI 0x01D6 -#define mmCG_FDO_CTRL2__SI 0x01D7 -#define mmCG_FIR_FILTER_COEFF_TAP_0__SI 0x01F0 -#define mmCG_FIR_FILTER_COEFF_TAP_10__SI 0x01FA -#define mmCG_FIR_FILTER_COEFF_TAP_11__SI 0x01FB -#define mmCG_FIR_FILTER_COEFF_TAP_12__SI 0x01FC -#define mmCG_FIR_FILTER_COEFF_TAP_13__SI 0x01FD -#define mmCG_FIR_FILTER_COEFF_TAP_14__SI 0x01FE -#define mmCG_FIR_FILTER_COEFF_TAP_1__SI 0x01F1 -#define mmCG_FIR_FILTER_COEFF_TAP_2__SI 0x01F2 -#define mmCG_FIR_FILTER_COEFF_TAP_3__SI 0x01F3 -#define mmCG_FIR_FILTER_COEFF_TAP_4__SI 0x01F4 -#define mmCG_FIR_FILTER_COEFF_TAP_5__SI 0x01F5 -#define mmCG_FIR_FILTER_COEFF_TAP_6__SI 0x01F6 -#define mmCG_FIR_FILTER_COEFF_TAP_7__SI 0x01F7 -#define mmCG_FIR_FILTER_COEFF_TAP_8__SI 0x01F8 -#define mmCG_FIR_FILTER_COEFF_TAP_9__SI 0x01F9 -#define mmCG_FPS_CNT__CI 0x0194 -#define mmCG_FREQ_TRAN_VOTING__SI 0x01EF -#define mmCG_GFXCLK_ON_OFF_RAMP__SI 0x01EE -#define mmCG_GFX_IDLE_THRESHOLDS__SI 0x0201 -#define mmCG_IND_ADDR__SI 0x023C -#define mmCG_IND_DATA__SI 0x023D -#define mmCG_INTERRUPT_STATUS__SI 0x0204 -#define mmCG_MISC_REG_2__SI 0x0209 -#define mmCG_MISC_REG__SI 0x0207 -#define mmCG_MULT_THERMAL_CTRL__SI 0x01C4 -#define mmCG_MULT_THERMAL_STATUS__SI 0x01C5 -#define mmCG_PROG_CNTR_STATUS_REG__SI 0x021C -#define mmCG_PROG_CNTR__SI 0x021B -#define mmCG_SPLL_AUTOSCALE_CNTL__SI 0x018B -#define mmCG_SPLL_AUTOSCALE_STATUS__SI 0x018C -#define mmCG_SPLL_FUNC_CNTL_2__SI 0x0181 -#define mmCG_SPLL_FUNC_CNTL_3__SI 0x0182 -#define mmCG_SPLL_FUNC_CNTL_4__SI 0x0183 -#define mmCG_SPLL_FUNC_CNTL_5__SI 0x0184 -#define mmCG_SPLL_FUNC_CNTL__SI 0x0180 -#define mmCG_SPLL_SPREAD_SPECTRUM_2__SI 0x0189 -#define mmCG_SPLL_SPREAD_SPECTRUM__SI 0x0188 -#define mmCG_SPLL_STATUS__SI 0x0185 -#define mmCG_STATIC_SCREEN_PARAMETER__SI 0x0203 -#define mmCG_SW_INT_CTXID__SI 0x0217 -#define mmCG_SW_INT__SI 0x0216 -#define mmCG_TACH_CTRL__SI 0x01DC -#define mmCG_TACH_STATUS__SI 0x01DD -#define mmCG_THERMAL_CTRL__SI 0x01C0 -#define mmCG_THERMAL_INT__SI 0x01C2 -#define mmCG_THERMAL_RANGE__SI 0x01C6 -#define mmCG_THERMAL_STATUS__SI 0x01C1 -#define mmCG_TIMESTAMP_HIGH__SI 0x3DF6 -#define mmCG_TIMESTAMP_LOW__SI 0x3DF5 -#define mmCG_ULV_CONTROL__SI 0x021E -#define mmCG_ULV_PARAMETER__SI 0x021F -#define mmCG_UPLL_FUNC_CNTL_2__SI 0x018E -#define mmCG_UPLL_FUNC_CNTL_3__SI 0x018F -#define mmCG_UPLL_FUNC_CNTL_4__SI 0x0191 -#define mmCG_UPLL_FUNC_CNTL_5__SI 0x0192 -#define mmCG_UPLL_FUNC_CNTL__SI 0x018D -#define mmCG_UPLL_SPREAD_SPECTRUM_2__SI 0x0195 -#define mmCG_UPLL_SPREAD_SPECTRUM__SI 0x0194 -#define mmCG_UPLL_STATUS__SI 0x0193 -#define mmCHROMA_BOT_ADDR__SI 0x388C -#define mmCHROMA_TOP_ADDR__SI 0x388B -#define mmCHUB_ATC_PERFCOUNTER0_CFG__CI__VI 0x07D8 -#define mmCHUB_ATC_PERFCOUNTER1_CFG__CI__VI 0x07D9 -#define mmCHUB_ATC_PERFCOUNTER_HI__CI__VI 0x07D7 -#define mmCHUB_ATC_PERFCOUNTER_LO__CI__VI 0x07D6 -#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07DA -#define mmCLKREQB_PAD_CNTL__CI__VI 0x1521 -#define mmCMON_REGION_LOWER__SI 0x022F -#define mmCMON_REGION_UPPER__SI 0x0234 -#define mmCMON_REG__SI 0x023B -#define mmCM_ARB_READ_CTL__SI 0x3EC4 -#define mmCM_ARB_WRITE_CTL__SI 0x3EC5 -#define mmCM_BITPLANE_MODE__SI 0x3ED7 -#define mmCM_BLK_STAT__SI 0x3EDE -#define mmCM_BUF_EMPTY__SI 0x3EC9 -#define mmCM_COLOC_ADR__SI 0x3ED2 -#define mmCM_COLOC_LOC__SI 0x3EC7 -#define mmCM_COLOC_SCAN_INFO__SI 0x3EC8 -#define mmCM_COLOC_STAT__SI 0x3ECB -#define mmCM_CTL__SI 0x3EC2 -#define mmCM_CTXT_ADR__SI 0x3ECE -#define mmCM_CTXT_FMO_MBNR__SI 0x3ED0 -#define mmCM_CTXT_TOP_FMO__SI 0x3ED1 -#define mmCM_CTXT_TOP_PREFETCH__SI 0x3ECF -#define mmCM_CURRENT_STAT__SI 0x3ECD -#define mmCM_DEBUG_INT_STAT__SI 0x3EDD -#define mmCM_FW_ADR__SI 0x3EE0 -#define mmCM_FW_CTL__SI 0x3EDF -#define mmCM_FW_LOWER_DAT__SI 0x3EE1 -#define mmCM_FW_UPPER_DAT__SI 0x3EE2 -#define mmCM_HW_DEBUG__SI 0x3EDC -#define mmCM_INIT_TOP_BUF_NUM__SI 0x3EC6 -#define mmCM_INT_EN__SI 0x3EC0 -#define mmCM_INT_STAT__SI 0x3EC1 -#define mmCM_LMA_ADR__SI 0x3ED9 -#define mmCM_LMA_CTL__SI 0x3ED8 -#define mmCM_LMA_DAT__SI 0x3EDA -#define mmCM_QWORD8_BOTTOM__SI 0x3ED6 -#define mmCM_QWORD8_TOP__SI 0x3ED5 -#define mmCM_RELEASE__SI 0x3ECA -#define mmCM_SLICE_INFO__SI 0x3ED4 -#define mmCM_SPS_INFO__SI 0x3ED3 -#define mmCM_SRAM_RM_CTL__SI 0x3EDB -#define mmCM_STAT__SI 0x3EC3 -#define mmCM_TOP_STAT__SI 0x3ECC -#define mmCOHER_DEST_BASE_0 0xA092 -#define mmCOHER_DEST_BASE_1 0xA093 -#define mmCOHER_DEST_BASE_2 0xA07E -#define mmCOHER_DEST_BASE_3 0xA07F -#define mmCOHER_DEST_BASE_HI_0__CI__VI 0xA07A -#define mmCOHER_DEST_BASE_HI_1__CI__VI 0xA07B -#define mmCOHER_DEST_BASE_HI_2__CI__VI 0xA07C -#define mmCOHER_DEST_BASE_HI_3__CI__VI 0xA07D -#define mmCOLOR_MATRIX_COEF_1_1__SI 0x1A5A -#define mmCOLOR_MATRIX_COEF_1_2__SI 0x1A5B -#define mmCOLOR_MATRIX_COEF_1_3__SI 0x1A5C -#define mmCOLOR_MATRIX_COEF_1_4__SI 0x1A5D -#define mmCOLOR_MATRIX_COEF_2_1__SI 0x1A5E -#define mmCOLOR_MATRIX_COEF_2_2__SI 0x1A5F -#define mmCOLOR_MATRIX_COEF_2_3__SI 0x1A60 -#define mmCOLOR_MATRIX_COEF_2_4__SI 0x1A61 -#define mmCOLOR_MATRIX_COEF_3_1__SI 0x1A62 -#define mmCOLOR_MATRIX_COEF_3_2__SI 0x1A63 -#define mmCOLOR_MATRIX_COEF_3_3__SI 0x1A64 -#define mmCOLOR_MATRIX_COEF_3_4__SI 0x1A65 -#define mmCOLOR_SPACE_CONVERT__SI 0x1A0F -#define mmCOMPUTE_DIM_X 0x2E01 -#define mmCOMPUTE_DIM_Y 0x2E02 -#define mmCOMPUTE_DIM_Z 0x2E03 -#define mmCOMPUTE_DISPATCH_INITIATOR 0x2E00 -#define mmCOMPUTE_MAX_WAVE_ID__SI 0x2E0B -#define mmCOMPUTE_MISC_RESERVED__CI__VI 0x2E1F -#define mmCOMPUTE_NUM_THREAD_X 0x2E07 -#define mmCOMPUTE_NUM_THREAD_Y 0x2E08 -#define mmCOMPUTE_NUM_THREAD_Z 0x2E09 -#define mmCOMPUTE_PERFCOUNT_ENABLE__CI__VI 0x2E0B -#define mmCOMPUTE_PGM_HI 0x2E0D -#define mmCOMPUTE_PGM_LO 0x2E0C -#define mmCOMPUTE_PGM_RSRC1 0x2E12 -#define mmCOMPUTE_PGM_RSRC2 0x2E13 -#define mmCOMPUTE_PIPELINESTAT_ENABLE__CI__VI 0x2E0A -#define mmCOMPUTE_RESOURCE_LIMITS 0x2E15 -#define mmCOMPUTE_RESTART_X__CI__VI 0x2E1B -#define mmCOMPUTE_RESTART_Y__CI__VI 0x2E1C -#define mmCOMPUTE_RESTART_Z__CI__VI 0x2E1D -#define mmCOMPUTE_START_X 0x2E04 -#define mmCOMPUTE_START_Y 0x2E05 -#define mmCOMPUTE_START_Z 0x2E06 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2E16 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2E17 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI 0x2E19 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI 0x2E1A -#define mmCOMPUTE_TBA_HI 0x2E0F -#define mmCOMPUTE_TBA_LO 0x2E0E -#define mmCOMPUTE_THREAD_TRACE_ENABLE__CI__VI 0x2E1E -#define mmCOMPUTE_TMA_HI 0x2E11 -#define mmCOMPUTE_TMA_LO 0x2E10 -#define mmCOMPUTE_TMPRING_SIZE 0x2E18 -#define mmCOMPUTE_USER_DATA_0 0x2E40 -#define mmCOMPUTE_USER_DATA_1 0x2E41 -#define mmCOMPUTE_USER_DATA_10 0x2E4A -#define mmCOMPUTE_USER_DATA_11 0x2E4B -#define mmCOMPUTE_USER_DATA_12 0x2E4C -#define mmCOMPUTE_USER_DATA_13 0x2E4D -#define mmCOMPUTE_USER_DATA_14 0x2E4E -#define mmCOMPUTE_USER_DATA_15 0x2E4F -#define mmCOMPUTE_USER_DATA_2 0x2E42 -#define mmCOMPUTE_USER_DATA_3 0x2E43 -#define mmCOMPUTE_USER_DATA_4 0x2E44 -#define mmCOMPUTE_USER_DATA_5 0x2E45 -#define mmCOMPUTE_USER_DATA_6 0x2E46 -#define mmCOMPUTE_USER_DATA_7 0x2E47 -#define mmCOMPUTE_USER_DATA_8 0x2E48 -#define mmCOMPUTE_USER_DATA_9 0x2E49 -#define mmCOMPUTE_VMID 0x2E14 -#define mmCONFIG_APER_SIZE 0x150C -#define mmCONFIG_CNTL 0x1509 -#define mmCONFIG_F0_BASE 0x150B -#define mmCONFIG_MEMSIZE 0x150A -#define mmCONFIG_REG_APER_SIZE 0x150D -#define mmCPC1_CONFIG__CI 0x0F97 -#define mmCPC2_CONFIG__CI 0x0F98 -#define mmCPC_INT_CNTL__CI__VI 0x30B4 -#define mmCPC_INT_CNTX_ID__CI__VI 0x30B7 -#define mmCPC_INT_STATUS__CI__VI 0x30B5 -#define mmCPC_PERFCOUNTER0_HI__CI__VI 0xD007 -#define mmCPC_PERFCOUNTER0_LO__CI__VI 0xD006 -#define mmCPC_PERFCOUNTER0_SELECT1__CI__VI 0xD804 -#define mmCPC_PERFCOUNTER0_SELECT__CI__VI 0xD809 -#define mmCPC_PERFCOUNTER1_HI__CI__VI 0xD005 -#define mmCPC_PERFCOUNTER1_LO__CI__VI 0xD004 -#define mmCPC_PERFCOUNTER1_SELECT__CI__VI 0xD803 -#define mmCPF_PERFCOUNTER0_HI__CI__VI 0xD00B -#define mmCPF_PERFCOUNTER0_LO__CI__VI 0xD00A -#define mmCPF_PERFCOUNTER0_SELECT1__CI__VI 0xD806 -#define mmCPF_PERFCOUNTER0_SELECT__CI__VI 0xD807 -#define mmCPF_PERFCOUNTER1_HI__CI__VI 0xD009 -#define mmCPF_PERFCOUNTER1_LO__CI__VI 0xD008 -#define mmCPF_PERFCOUNTER1_SELECT__CI__VI 0xD805 -#define mmCPG_CONFIG__CI 0x0F96 -#define mmCPG_PERFCOUNTER0_HI__CI__VI 0xD003 -#define mmCPG_PERFCOUNTER0_LO__CI__VI 0xD002 -#define mmCPG_PERFCOUNTER0_SELECT1__CI__VI 0xD801 -#define mmCPG_PERFCOUNTER0_SELECT__CI__VI 0xD802 -#define mmCPG_PERFCOUNTER1_HI__CI__VI 0xD001 -#define mmCPG_PERFCOUNTER1_LO__CI__VI 0xD000 -#define mmCPG_PERFCOUNTER1_SELECT__CI__VI 0xD800 -#define mmCP_APPEND_ADDR_HI__CI__VI 0xC059 -#define mmCP_APPEND_ADDR_HI__SI 0x2159 -#define mmCP_APPEND_ADDR_LO__CI__VI 0xC058 -#define mmCP_APPEND_ADDR_LO__SI 0x2158 -#define mmCP_APPEND_DATA__CI__VI 0xC05A -#define mmCP_APPEND_DATA__SI 0x215A -#define mmCP_APPEND_LAST_CS_FENCE__CI__VI 0xC05B -#define mmCP_APPEND_LAST_CS_FENCE__SI 0x215B -#define mmCP_APPEND_LAST_PS_FENCE__CI__VI 0xC05C -#define mmCP_APPEND_LAST_PS_FENCE__SI 0x215C -#define mmCP_ATOMIC_PREOP_HI__CI__VI 0xC05E -#define mmCP_ATOMIC_PREOP_HI__SI 0x215E -#define mmCP_ATOMIC_PREOP_LO__CI__VI 0xC05D -#define mmCP_ATOMIC_PREOP_LO__SI 0x215D -#define mmCP_BUSY_STAT 0x219F -#define mmCP_CEQ1_AVAIL 0x21E6 -#define mmCP_CEQ2_AVAIL 0x21E7 -#define mmCP_CE_COMPARE_COUNT__CI__VI 0x20C0 -#define mmCP_CE_COUNTER__CI__VI 0xC09A -#define mmCP_CE_DE_COUNT__CI__VI 0x20C1 -#define mmCP_CE_F32_INTERRUPT__CI__VI 0x3075 -#define mmCP_CE_HEADER_DUMP 0x21A4 -#define mmCP_CE_IB1_BASE_HI__CI__VI 0xC0C7 -#define mmCP_CE_IB1_BASE_HI__SI 0x21C7 -#define mmCP_CE_IB1_BASE_LO__CI__VI 0xC0C6 -#define mmCP_CE_IB1_BASE_LO__SI 0x21C6 -#define mmCP_CE_IB1_BUFSZ__CI__VI 0xC0C8 -#define mmCP_CE_IB1_BUFSZ__SI 0x21C8 -#define mmCP_CE_IB1_OFFSET__CI__VI 0xC098 -#define mmCP_CE_IB2_BASE_HI__CI__VI 0xC0CA -#define mmCP_CE_IB2_BASE_HI__SI 0x21CA -#define mmCP_CE_IB2_BASE_LO__CI__VI 0xC0C9 -#define mmCP_CE_IB2_BASE_LO__SI 0x21C9 -#define mmCP_CE_IB2_BUFSZ__CI__VI 0xC0CB -#define mmCP_CE_IB2_BUFSZ__SI 0x21CB -#define mmCP_CE_IB2_OFFSET__CI__VI 0xC099 -#define mmCP_CE_INIT_BASE_HI__CI__VI 0xC0C4 -#define mmCP_CE_INIT_BASE_HI__SI 0x21C4 -#define mmCP_CE_INIT_BASE_LO__CI__VI 0xC0C3 -#define mmCP_CE_INIT_BASE_LO__SI 0x21C3 -#define mmCP_CE_INIT_BUFSZ__CI__VI 0xC0C5 -#define mmCP_CE_INIT_BUFSZ__SI 0x21C5 -#define mmCP_CE_INTR_ROUTINE_START__CI__VI 0x30A8 -#define mmCP_CE_PRGRM_CNTR_START__CI__VI 0x30A3 -#define mmCP_CE_ROQ_IB1_STAT 0x21E9 -#define mmCP_CE_ROQ_IB2_STAT 0x21EA -#define mmCP_CE_ROQ_RB_STAT 0x21E8 -#define mmCP_CMD_DATA 0x21DF -#define mmCP_CMD_INDEX 0x21DE -#define mmCP_CNTL__SI 0x304B -#define mmCP_CNTX_STAT 0x21B8 -#define mmCP_COHER_BASE_HI__CI__VI 0xC079 -#define mmCP_COHER_BASE__CI__VI 0xC07E -#define mmCP_COHER_BASE__SI 0x217E -#define mmCP_COHER_CNTL2__SI 0x217A -#define mmCP_COHER_CNTL__CI__VI 0xC07C -#define mmCP_COHER_CNTL__SI 0x217C -#define mmCP_COHER_SIZE_HI__CI__VI 0xC08C -#define mmCP_COHER_SIZE__CI__VI 0xC07D -#define mmCP_COHER_SIZE__SI 0x217D -#define mmCP_COHER_START_DELAY__CI__VI 0xC07B -#define mmCP_COHER_START_DELAY__SI 0x217B -#define mmCP_COHER_STATUS__CI__VI 0xC07F -#define mmCP_COHER_STATUS__SI 0x217F -#define mmCP_CONFIG__SI 0x0F92 -#define mmCP_CONTEXT_CNTL__CI__VI 0x30AD -#define mmCP_CPC_BUSY_STAT__CI__VI 0x2085 -#define mmCP_CPC_DEBUG_CNTL__CI__VI 0x2080 -#define mmCP_CPC_DEBUG_DATA__CI__VI 0x2081 -#define mmCP_CPC_DEBUG__CI__VI 0x3081 -#define mmCP_CPC_GRBM_FREE_COUNT__CI__VI 0x208B -#define mmCP_CPC_HALT_HYST_COUNT__CI__VI 0x20A7 -#define mmCP_CPC_MC_CNTL__CI 0x208A -#define mmCP_CPC_PRIV_VIOLATION_ADDR__CI__VI 0x208C -#define mmCP_CPC_SCRATCH_DATA__CI__VI 0x2091 -#define mmCP_CPC_SCRATCH_INDEX__CI__VI 0x2090 -#define mmCP_CPC_STALLED_STAT1__CI__VI 0x2086 -#define mmCP_CPC_STATUS__CI__VI 0x2084 -#define mmCP_CPF_BUSY_STAT__CI__VI 0x2088 -#define mmCP_CPF_DEBUG_CNTL__CI__VI 0x2082 -#define mmCP_CPF_DEBUG_DATA__CI__VI 0x2083 -#define mmCP_CPF_DEBUG__CI__VI 0x3080 -#define mmCP_CPF_STALLED_STAT1__CI__VI 0x2089 -#define mmCP_CPF_STATUS__CI__VI 0x2087 -#define mmCP_CSF_CNTL 0x21B5 -#define mmCP_CSF_STAT 0x21B4 -#define mmCP_DEBUG 0x307F -#define mmCP_DEBUG_CNTL 0x21F8 -#define mmCP_DEBUG_DATA 0x21F9 -#define mmCP_DEVICE_ID__CI__VI 0x304B -#define mmCP_DE_CE_COUNT__CI__VI 0x20C2 -#define mmCP_DE_DE_COUNT__CI__VI 0x20C4 -#define mmCP_DE_LAST_INVAL_COUNT__CI__VI 0x20C3 -#define mmCP_DFY_ADDR_HI__CI__VI 0x3022 -#define mmCP_DFY_ADDR_LO__CI__VI 0x3023 -#define mmCP_DFY_CNTL__CI__VI 0x3020 -#define mmCP_DFY_DATA_0__CI__VI 0x3024 -#define mmCP_DFY_DATA_10__CI__VI 0x302E -#define mmCP_DFY_DATA_11__CI__VI 0x302F -#define mmCP_DFY_DATA_12__CI__VI 0x3030 -#define mmCP_DFY_DATA_13__CI__VI 0x3031 -#define mmCP_DFY_DATA_14__CI__VI 0x3032 -#define mmCP_DFY_DATA_15__CI__VI 0x3033 -#define mmCP_DFY_DATA_1__CI__VI 0x3025 -#define mmCP_DFY_DATA_2__CI__VI 0x3026 -#define mmCP_DFY_DATA_3__CI__VI 0x3027 -#define mmCP_DFY_DATA_4__CI__VI 0x3028 -#define mmCP_DFY_DATA_5__CI__VI 0x3029 -#define mmCP_DFY_DATA_6__CI__VI 0x302A -#define mmCP_DFY_DATA_7__CI__VI 0x302B -#define mmCP_DFY_DATA_8__CI__VI 0x302C -#define mmCP_DFY_DATA_9__CI__VI 0x302D -#define mmCP_DFY_STAT__CI__VI 0x3021 -#define mmCP_DMA_CNTL__CI__VI 0xC08A -#define mmCP_DMA_CNTL__SI 0x218A -#define mmCP_DMA_ME_COMMAND__CI__VI 0xC084 -#define mmCP_DMA_ME_COMMAND__SI 0x2184 -#define mmCP_DMA_ME_CONTROL__CI__VI 0xC078 -#define mmCP_DMA_ME_DST_ADDR_HI__CI__VI 0xC083 -#define mmCP_DMA_ME_DST_ADDR_HI__SI 0x2183 -#define mmCP_DMA_ME_DST_ADDR__CI__VI 0xC082 -#define mmCP_DMA_ME_DST_ADDR__SI 0x2182 -#define mmCP_DMA_ME_SRC_ADDR_HI__CI__VI 0xC081 -#define mmCP_DMA_ME_SRC_ADDR_HI__SI 0x2181 -#define mmCP_DMA_ME_SRC_ADDR__CI__VI 0xC080 -#define mmCP_DMA_ME_SRC_ADDR__SI 0x2180 -#define mmCP_DMA_PFP_COMMAND__CI__VI 0xC089 -#define mmCP_DMA_PFP_COMMAND__SI 0x2189 -#define mmCP_DMA_PFP_CONTROL__CI__VI 0xC077 -#define mmCP_DMA_PFP_DST_ADDR_HI__CI__VI 0xC088 -#define mmCP_DMA_PFP_DST_ADDR_HI__SI 0x2188 -#define mmCP_DMA_PFP_DST_ADDR__CI__VI 0xC087 -#define mmCP_DMA_PFP_DST_ADDR__SI 0x2187 -#define mmCP_DMA_PFP_SRC_ADDR_HI__CI__VI 0xC086 -#define mmCP_DMA_PFP_SRC_ADDR_HI__SI 0x2186 -#define mmCP_DMA_PFP_SRC_ADDR__CI__VI 0xC085 -#define mmCP_DMA_PFP_SRC_ADDR__SI 0x2185 -#define mmCP_DMA_PIO_COMMAND__CI__VI 0xC0E8 -#define mmCP_DMA_PIO_COMMAND__SI 0x2168 -#define mmCP_DMA_PIO_CONTROL__CI__VI 0xC063 -#define mmCP_DMA_PIO_DST_ADDR_HI__CI__VI 0xC067 -#define mmCP_DMA_PIO_DST_ADDR_HI__SI 0x2167 -#define mmCP_DMA_PIO_DST_ADDR__CI__VI 0xC066 -#define mmCP_DMA_PIO_DST_ADDR__SI 0x2166 -#define mmCP_DMA_PIO_SRC_ADDR_HI__CI__VI 0xC065 -#define mmCP_DMA_PIO_SRC_ADDR_HI__SI 0x2165 -#define mmCP_DMA_PIO_SRC_ADDR__CI__VI 0xC064 -#define mmCP_DMA_PIO_SRC_ADDR__SI 0x2164 -#define mmCP_DMA_READ_TAGS__CI__VI 0xC08B -#define mmCP_DMA_READ_TAGS__SI 0x218B -#define mmCP_ECC_FIRSTOCCURRENCE 0x307A -#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307B -#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307C -#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307D -#define mmCP_ENDIAN_SWAP__CI__VI 0x3050 -#define mmCP_EOP_DONE_ADDR_HI__CI__VI 0xC001 -#define mmCP_EOP_DONE_ADDR_HI__SI 0x2101 -#define mmCP_EOP_DONE_ADDR_LO__CI__VI 0xC000 -#define mmCP_EOP_DONE_ADDR_LO__SI 0x2100 -#define mmCP_EOP_DONE_DATA_CNTL__CI__VI 0xC0D6 -#define mmCP_EOP_DONE_DATA_HI__CI__VI 0xC003 -#define mmCP_EOP_DONE_DATA_HI__SI 0x2103 -#define mmCP_EOP_DONE_DATA_LO__CI__VI 0xC002 -#define mmCP_EOP_DONE_DATA_LO__SI 0x2102 -#define mmCP_EOP_DONE_EVENT_CNTL__CI__VI 0xC0D5 -#define mmCP_EOP_LAST_FENCE_HI__CI__VI 0xC005 -#define mmCP_EOP_LAST_FENCE_HI__SI 0x2105 -#define mmCP_EOP_LAST_FENCE_LO__CI__VI 0xC004 -#define mmCP_EOP_LAST_FENCE_LO__SI 0x2104 -#define mmCP_FETCHER_SOURCE__CI 0x3082 -#define mmCP_GDS_ATOMIC0_PREOP_HI__CI__VI 0xC060 -#define mmCP_GDS_ATOMIC0_PREOP_HI__SI 0x2160 -#define mmCP_GDS_ATOMIC0_PREOP_LO__CI__VI 0xC05F -#define mmCP_GDS_ATOMIC0_PREOP_LO__SI 0x215F -#define mmCP_GDS_ATOMIC1_PREOP_HI__CI__VI 0xC062 -#define mmCP_GDS_ATOMIC1_PREOP_HI__SI 0x2162 -#define mmCP_GDS_ATOMIC1_PREOP_LO__CI__VI 0xC061 -#define mmCP_GDS_ATOMIC1_PREOP_LO__SI 0x2161 -#define mmCP_GRBM_FREE_COUNT 0x21A3 -#define mmCP_HPD_EOP_BASE_ADDR_HI__CI 0x3242 -#define mmCP_HPD_EOP_BASE_ADDR__CI 0x3241 -#define mmCP_HPD_EOP_CONTROL__CI 0x3244 -#define mmCP_HPD_EOP_VMID__CI 0x3243 -#define mmCP_HPD_ROQ_OFFSETS__CI__VI 0x3240 -#define mmCP_HQD_ACTIVE__CI__VI 0x3247 -#define mmCP_HQD_ATOMIC0_PREOP_HI__CI__VI 0x3262 -#define mmCP_HQD_ATOMIC0_PREOP_LO__CI__VI 0x3261 -#define mmCP_HQD_ATOMIC1_PREOP_HI__CI__VI 0x3264 -#define mmCP_HQD_ATOMIC1_PREOP_LO__CI__VI 0x3263 -#define mmCP_HQD_DEQUEUE_REQUEST__CI__VI 0x325D -#define mmCP_HQD_DMA_OFFLOAD__CI__VI 0x325E -#define mmCP_HQD_HQ_SCHEDULER0__CI__VI 0x3265 -#define mmCP_HQD_HQ_SCHEDULER1__CI__VI 0x3266 -#define mmCP_HQD_IB_BASE_ADDR_HI__CI__VI 0x3258 -#define mmCP_HQD_IB_BASE_ADDR__CI__VI 0x3257 -#define mmCP_HQD_IB_CONTROL__CI__VI 0x325A -#define mmCP_HQD_IB_RPTR__CI__VI 0x3259 -#define mmCP_HQD_IQ_RPTR__CI__VI 0x325C -#define mmCP_HQD_IQ_TIMER__CI__VI 0x325B -#define mmCP_HQD_MSG_TYPE__CI__VI 0x3260 -#define mmCP_HQD_PERSISTENT_STATE__CI__VI 0x3249 -#define mmCP_HQD_PIPE_PRIORITY__CI__VI 0x324A -#define mmCP_HQD_PQ_BASE_HI__CI__VI 0x324E -#define mmCP_HQD_PQ_BASE__CI__VI 0x324D -#define mmCP_HQD_PQ_CONTROL__CI__VI 0x3256 -#define mmCP_HQD_PQ_DOORBELL_CONTROL__CI__VI 0x3254 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI 0x3251 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI 0x3250 -#define mmCP_HQD_PQ_RPTR__CI__VI 0x324F -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI 0x3253 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR__CI__VI 0x3252 -#define mmCP_HQD_PQ_WPTR__CI__VI 0x3255 -#define mmCP_HQD_QUANTUM__CI__VI 0x324C -#define mmCP_HQD_QUEUE_PRIORITY__CI__VI 0x324B -#define mmCP_HQD_SEMA_CMD__CI__VI 0x325F -#define mmCP_HQD_VMID__CI__VI 0x3248 -#define mmCP_HYP_REG_PRIV_LEVEL_A__CI__VI 0xF800 -#define mmCP_HYP_REG_PRIV_LEVEL_B__CI__VI 0xF801 -#define mmCP_HYP_REG_PRIV_LEVEL_C__CI__VI 0xF802 -#define mmCP_HYP_REG_PRIV_LEVEL_D__CI__VI 0xF803 -#define mmCP_IB1_BASE_HI__CI__VI 0xC0CD -#define mmCP_IB1_BASE_HI__SI 0x21CD -#define mmCP_IB1_BASE_LO__CI__VI 0xC0CC -#define mmCP_IB1_BASE_LO__SI 0x21CC -#define mmCP_IB1_BUFSZ__CI__VI 0xC0CE -#define mmCP_IB1_BUFSZ__SI 0x21CE -#define mmCP_IB1_OFFSET__CI__VI 0xC092 -#define mmCP_IB1_OFFSET__SI 0x2192 -#define mmCP_IB1_PREAMBLE_BEGIN__CI__VI 0xC094 -#define mmCP_IB1_PREAMBLE_BEGIN__SI 0x2194 -#define mmCP_IB1_PREAMBLE_END__CI__VI 0xC095 -#define mmCP_IB1_PREAMBLE_END__SI 0x2195 -#define mmCP_IB1_PRIV_BASE_HI 0x3071 -#define mmCP_IB1_PRIV_BASE_LO 0x3070 -#define mmCP_IB1_PRIV_BUFSZ 0x3072 -#define mmCP_IB2_BASE_HI__CI__VI 0xC0D0 -#define mmCP_IB2_BASE_HI__SI 0x21D0 -#define mmCP_IB2_BASE_LO__CI__VI 0xC0CF -#define mmCP_IB2_BASE_LO__SI 0x21CF -#define mmCP_IB2_BUFSZ__CI__VI 0xC0D1 -#define mmCP_IB2_BUFSZ__SI 0x21D1 -#define mmCP_IB2_OFFSET__CI__VI 0xC093 -#define mmCP_IB2_OFFSET__SI 0x2193 -#define mmCP_IB2_PREAMBLE_BEGIN__CI__VI 0xC096 -#define mmCP_IB2_PREAMBLE_BEGIN__SI 0x2196 -#define mmCP_IB2_PREAMBLE_END__CI__VI 0xC097 -#define mmCP_IB2_PREAMBLE_END__SI 0x2197 -#define mmCP_INT_CNTL 0x3049 -#define mmCP_INT_CNTL_RING0 0x306A -#define mmCP_INT_CNTL_RING1 0x306B -#define mmCP_INT_CNTL_RING2 0x306C -#define mmCP_INT_STATUS 0x304A -#define mmCP_INT_STATUS_RING0 0x306D -#define mmCP_INT_STATUS_RING1 0x306E -#define mmCP_INT_STATUS_RING2 0x306F -#define mmCP_INT_STAT_DEBUG 0x21F7 -#define mmCP_IQ_WAIT_TIME1__CI__VI 0x30AF -#define mmCP_IQ_WAIT_TIME2__CI__VI 0x30B0 -#define mmCP_MAX_CONTEXT__CI__VI 0x30AE -#define mmCP_MC_PACK_DELAY_CNT__SI__CI 0x21A7 -#define mmCP_MC_RD_RETURN_TAGS__SI 0x21A6 -#define mmCP_MC_TAG_CNTL__CI 0x21A8 -#define mmCP_MC_TAG_DATA__CI 0x21A9 -#define mmCP_ME0_PIPE0_PRIORITY__CI__VI 0x304D -#define mmCP_ME0_PIPE0_VMID__CI__VI 0x3052 -#define mmCP_ME0_PIPE1_PRIORITY__CI__VI 0x304E -#define mmCP_ME0_PIPE1_VMID__CI__VI 0x3053 -#define mmCP_ME0_PIPE2_PRIORITY__CI__VI 0x304F -#define mmCP_ME0_PIPE_PRIORITY_CNTS__CI__VI 0x304C -#define mmCP_ME1_INT_STAT_DEBUG__CI__VI 0x3095 -#define mmCP_ME1_PIPE0_INT_CNTL__CI__VI 0x3085 -#define mmCP_ME1_PIPE0_INT_STATUS__CI__VI 0x308D -#define mmCP_ME1_PIPE0_PRIORITY__CI__VI 0x309A -#define mmCP_ME1_PIPE1_INT_CNTL__CI__VI 0x3086 -#define mmCP_ME1_PIPE1_INT_STATUS__CI__VI 0x308E -#define mmCP_ME1_PIPE1_PRIORITY__CI__VI 0x309B -#define mmCP_ME1_PIPE2_INT_CNTL__CI__VI 0x3087 -#define mmCP_ME1_PIPE2_INT_STATUS__CI__VI 0x308F -#define mmCP_ME1_PIPE2_PRIORITY__CI__VI 0x309C -#define mmCP_ME1_PIPE3_INT_CNTL__CI__VI 0x3088 -#define mmCP_ME1_PIPE3_INT_STATUS__CI__VI 0x3090 -#define mmCP_ME1_PIPE3_PRIORITY__CI__VI 0x309D -#define mmCP_ME1_PIPE_PRIORITY_CNTS__CI__VI 0x3099 -#define mmCP_ME2_INT_STAT_DEBUG__CI__VI 0x3096 -#define mmCP_ME2_PIPE0_INT_CNTL__CI__VI 0x3089 -#define mmCP_ME2_PIPE0_INT_STATUS__CI__VI 0x3091 -#define mmCP_ME2_PIPE0_PRIORITY__CI__VI 0x309F -#define mmCP_ME2_PIPE1_INT_CNTL__CI__VI 0x308A -#define mmCP_ME2_PIPE1_INT_STATUS__CI__VI 0x3092 -#define mmCP_ME2_PIPE1_PRIORITY__CI__VI 0x30A0 -#define mmCP_ME2_PIPE2_INT_CNTL__CI__VI 0x308B -#define mmCP_ME2_PIPE2_INT_STATUS__CI__VI 0x3093 -#define mmCP_ME2_PIPE2_PRIORITY__CI__VI 0x30A1 -#define mmCP_ME2_PIPE3_INT_CNTL__CI__VI 0x308C -#define mmCP_ME2_PIPE3_INT_STATUS__CI__VI 0x3094 -#define mmCP_ME2_PIPE3_PRIORITY__CI__VI 0x30A2 -#define mmCP_ME2_PIPE_PRIORITY_CNTS__CI__VI 0x309E -#define mmCP_MEC1_F32_INTERRUPT__CI__VI 0x3076 -#define mmCP_MEC1_INTR_ROUTINE_START__CI__VI 0x30AB -#define mmCP_MEC1_PRGRM_CNTR_START__CI__VI 0x30A6 -#define mmCP_MEC2_F32_INTERRUPT__CI__VI 0x3077 -#define mmCP_MEC2_INTR_ROUTINE_START__CI__VI 0x30AC -#define mmCP_MEC2_PRGRM_CNTR_START__CI__VI 0x30A7 -#define mmCP_MEC_CNTL__CI__VI 0x208D -#define mmCP_MEC_ME1_HEADER_DUMP__CI__VI 0x208E -#define mmCP_MEC_ME1_UCODE_ADDR__CI 0x305C -#define mmCP_MEC_ME1_UCODE_DATA__CI 0x305D -#define mmCP_MEC_ME2_HEADER_DUMP__CI__VI 0x208F -#define mmCP_MEC_ME2_UCODE_ADDR__CI 0x305E -#define mmCP_MEC_ME2_UCODE_DATA__CI 0x305F -#define mmCP_MEM_SLP_CNTL 0x3079 -#define mmCP_MEQ_AVAIL 0x21DD -#define mmCP_MEQ_STAT 0x21E5 -#define mmCP_MEQ_STQ_THRESHOLD__CI__VI 0x21BD -#define mmCP_MEQ_THRESHOLDS 0x21D9 -#define mmCP_ME_ATOMIC_PREOP_HI__CI__VI 0xC05E -#define mmCP_ME_ATOMIC_PREOP_LO__CI__VI 0xC05D -#define mmCP_ME_CNTL 0x21B6 -#define mmCP_ME_F32_INTERRUPT__CI__VI 0x3073 -#define mmCP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI 0xC060 -#define mmCP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI 0xC05F -#define mmCP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI 0xC062 -#define mmCP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI 0xC061 -#define mmCP_ME_HEADER_DUMP 0x21A1 -#define mmCP_ME_INTR_ROUTINE_START__CI__VI 0x30AA -#define mmCP_ME_MC_RADDR_HI__CI__VI 0xC06E -#define mmCP_ME_MC_RADDR_HI__SI 0x216E -#define mmCP_ME_MC_RADDR_LO__CI__VI 0xC06D -#define mmCP_ME_MC_RADDR_LO__SI 0x216D -#define mmCP_ME_MC_WADDR_HI__CI__VI 0xC06A -#define mmCP_ME_MC_WADDR_HI__SI 0x216A -#define mmCP_ME_MC_WADDR_LO__CI__VI 0xC069 -#define mmCP_ME_MC_WADDR_LO__SI 0x2169 -#define mmCP_ME_MC_WDATA_HI__CI__VI 0xC06C -#define mmCP_ME_MC_WDATA_HI__SI 0x216C -#define mmCP_ME_MC_WDATA_LO__CI__VI 0xC06B -#define mmCP_ME_MC_WDATA_LO__SI 0x216B -#define mmCP_ME_PREEMPTION 0x21B9 -#define mmCP_ME_PRGRM_CNTR_START__CI__VI 0x30A5 -#define mmCP_MQD_BASE_ADDR_HI__CI__VI 0x3246 -#define mmCP_MQD_BASE_ADDR__CI__VI 0x3245 -#define mmCP_MQD_CONTROL__CI__VI 0x3267 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI__CI__VI 0xC00B -#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI__SI 0x210B -#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO__CI__VI 0xC00A -#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO__SI 0x210A -#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI__CI__VI 0xC00F -#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI__SI 0x210F -#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO__CI__VI 0xC00E -#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO__SI 0x210E -#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI__CI__VI 0xC013 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI__SI 0x2113 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO__CI__VI 0xC012 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO__SI 0x2112 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI__CI__VI 0xC017 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI__SI 0x2117 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO__CI__VI 0xC016 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO__SI 0x2116 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI__CI__VI 0xC009 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI__SI 0x2109 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO__CI__VI 0xC008 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO__SI 0x2108 -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI__CI__VI 0xC00D -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI__SI 0x210D -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO__CI__VI 0xC00C -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO__SI 0x210C -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI__CI__VI 0xC011 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI__SI 0x2111 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO__CI__VI 0xC010 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO__SI 0x2110 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI__CI__VI 0xC015 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI__SI 0x2115 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO__CI__VI 0xC014 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO__SI 0x2114 -#define mmCP_PA_CINVOC_COUNT_HI__CI__VI 0xC029 -#define mmCP_PA_CINVOC_COUNT_HI__SI 0x2129 -#define mmCP_PA_CINVOC_COUNT_LO__CI__VI 0xC028 -#define mmCP_PA_CINVOC_COUNT_LO__SI 0x2128 -#define mmCP_PA_CPRIM_COUNT_HI__CI__VI 0xC02B -#define mmCP_PA_CPRIM_COUNT_HI__SI 0x212B -#define mmCP_PA_CPRIM_COUNT_LO__CI__VI 0xC02A -#define mmCP_PA_CPRIM_COUNT_LO__SI 0x212A -#define mmCP_PERFCOUNTER_HI__SI 0x21FE -#define mmCP_PERFCOUNTER_LO__SI 0x21FD -#define mmCP_PERFCOUNTER_SELECT__SI 0x21FC -#define mmCP_PERFMON_CNTL__CI__VI 0xD808 -#define mmCP_PERFMON_CNTL__SI 0x21FF -#define mmCP_PERFMON_CNTX_CNTL 0xA0D8 -#define mmCP_PFP_ATOMIC_PREOP_HI__CI__VI 0xC053 -#define mmCP_PFP_ATOMIC_PREOP_LO__CI__VI 0xC052 -#define mmCP_PFP_F32_INTERRUPT__CI__VI 0x3074 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI 0xC055 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI 0xC054 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI 0xC057 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI 0xC056 -#define mmCP_PFP_HEADER_DUMP 0x21A2 -#define mmCP_PFP_IB_CONTROL__CI__VI 0xC08D -#define mmCP_PFP_IB_CONTROL__SI 0x218D -#define mmCP_PFP_INTR_ROUTINE_START__CI__VI 0x30A9 -#define mmCP_PFP_LOAD_CONTROL__CI__VI 0xC08E -#define mmCP_PFP_LOAD_CONTROL__SI 0x218E -#define mmCP_PFP_PRGRM_CNTR_START__CI__VI 0x30A4 -#define mmCP_PIPEID__CI__VI 0xA0D9 -#define mmCP_PIPE_STATS_ADDR_HI__CI__VI 0xC019 -#define mmCP_PIPE_STATS_ADDR_HI__SI 0x2119 -#define mmCP_PIPE_STATS_ADDR_LO__CI__VI 0xC018 -#define mmCP_PIPE_STATS_ADDR_LO__SI 0x2118 -#define mmCP_PQ_WPTR_POLL_CNTL1__CI__VI 0x3084 -#define mmCP_PQ_WPTR_POLL_CNTL__CI__VI 0x3083 -#define mmCP_PRIV_VIOLATION_ADDR 0x21FA -#define mmCP_PRT_LOD_STATS_CNTL0__CI__VI 0x20AD -#define mmCP_PRT_LOD_STATS_CNTL1__CI__VI 0x20AE -#define mmCP_PRT_LOD_STATS_CNTL2__CI__VI 0x20AF -#define mmCP_PWR_CNTL 0x3078 -#define mmCP_QUEUE_THRESHOLDS 0x21D8 -#define mmCP_RB0_BASE 0x3040 -#define mmCP_RB0_BASE_HI__CI__VI 0x30B1 -#define mmCP_RB0_CNTL 0x3041 -#define mmCP_RB0_RPTR 0x21C0 -#define mmCP_RB0_RPTR_ADDR 0x3043 -#define mmCP_RB0_RPTR_ADDR_HI 0x3044 -#define mmCP_RB0_WPTR 0x3045 -#define mmCP_RB1_BASE 0x3060 -#define mmCP_RB1_BASE_HI__CI__VI 0x30B2 -#define mmCP_RB1_CNTL 0x3061 -#define mmCP_RB1_RPTR 0x21BF -#define mmCP_RB1_RPTR_ADDR 0x3062 -#define mmCP_RB1_RPTR_ADDR_HI 0x3063 -#define mmCP_RB1_WPTR 0x3064 -#define mmCP_RB2_BASE 0x3065 -#define mmCP_RB2_CNTL 0x3066 -#define mmCP_RB2_RPTR 0x21BE -#define mmCP_RB2_RPTR_ADDR 0x3067 -#define mmCP_RB2_RPTR_ADDR_HI 0x3068 -#define mmCP_RB2_WPTR 0x3069 -#define mmCP_RB_BASE 0x3040 -#define mmCP_RB_CNTL 0x3041 -#define mmCP_RB_OFFSET__CI__VI 0xC091 -#define mmCP_RB_OFFSET__SI 0x2191 -#define mmCP_RB_RPTR 0x21C0 -#define mmCP_RB_RPTR_ADDR 0x3043 -#define mmCP_RB_RPTR_ADDR_HI 0x3044 -#define mmCP_RB_RPTR_WR 0x3042 -#define mmCP_RB_VMID 0x3051 -#define mmCP_RB_WPTR 0x3045 -#define mmCP_RB_WPTR_DELAY 0x21C1 -#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 -#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 -#define mmCP_RB_WPTR_POLL_CNTL 0x21C2 -#define mmCP_RING0_PRIORITY 0x304D -#define mmCP_RING1_PRIORITY 0x304E -#define mmCP_RING2_PRIORITY 0x304F -#define mmCP_RINGID 0xA0D9 -#define mmCP_RING_PRIORITY_CNTS 0x304C -#define mmCP_ROQ1_THRESHOLDS 0x21D5 -#define mmCP_ROQ2_AVAIL 0x21DC -#define mmCP_ROQ2_THRESHOLDS 0x21D6 -#define mmCP_ROQ_AVAIL 0x21DA -#define mmCP_ROQ_IB1_STAT 0x21E1 -#define mmCP_ROQ_IB2_STAT 0x21E2 -#define mmCP_ROQ_RB_STAT 0x21E0 -#define mmCP_ROQ_THRESHOLDS__CI__VI 0x21BC -#define mmCP_SCRATCH_DATA__CI__VI 0xC090 -#define mmCP_SCRATCH_DATA__SI 0x2190 -#define mmCP_SCRATCH_INDEX__CI__VI 0xC08F -#define mmCP_SCRATCH_INDEX__SI 0x218F -#define mmCP_SC_PSINVOC_COUNT0_HI__CI__VI 0xC02D -#define mmCP_SC_PSINVOC_COUNT0_HI__SI 0x212D -#define mmCP_SC_PSINVOC_COUNT0_LO__CI__VI 0xC02C -#define mmCP_SC_PSINVOC_COUNT0_LO__SI 0x212C -#define mmCP_SC_PSINVOC_COUNT1_HI__CI__VI 0xC02F -#define mmCP_SC_PSINVOC_COUNT1_HI__SI 0x212F -#define mmCP_SC_PSINVOC_COUNT1_LO__CI__VI 0xC02E -#define mmCP_SC_PSINVOC_COUNT1_LO__SI 0x212E -#define mmCP_SEM_INCOMPLETE_TIMER_CNTL__SI 0x2172 -#define mmCP_SEM_WAIT_TIMER__CI__VI 0xC06F -#define mmCP_SEM_WAIT_TIMER__SI 0x216F -#define mmCP_SIG_SEM_ADDR_HI__CI__VI 0xC071 -#define mmCP_SIG_SEM_ADDR_HI__SI 0x2171 -#define mmCP_SIG_SEM_ADDR_LO__CI__VI 0xC070 -#define mmCP_SIG_SEM_ADDR_LO__SI 0x2170 -#define mmCP_STALLED_STAT1 0x219D -#define mmCP_STALLED_STAT2 0x219E -#define mmCP_STALLED_STAT3 0x219C -#define mmCP_STAT 0x21A0 -#define mmCP_STQ_AVAIL 0x21DB -#define mmCP_STQ_STAT 0x21E3 -#define mmCP_STQ_THRESHOLDS 0x21D7 -#define mmCP_STQ_WR_STAT__CI__VI 0x21E4 -#define mmCP_STREAM_OUT_ADDR_HI__CI__VI 0xC007 -#define mmCP_STREAM_OUT_ADDR_HI__SI 0x2107 -#define mmCP_STREAM_OUT_ADDR_LO__CI__VI 0xC006 -#define mmCP_STREAM_OUT_ADDR_LO__SI 0x2106 -#define mmCP_STRMOUT_CNTL__CI__VI 0xC03F -#define mmCP_STRMOUT_CNTL__SI 0x213F -#define mmCP_ST_BASE_HI__CI__VI 0xC0D3 -#define mmCP_ST_BASE_HI__SI 0x21D3 -#define mmCP_ST_BASE_LO__CI__VI 0xC0D2 -#define mmCP_ST_BASE_LO__SI 0x21D2 -#define mmCP_ST_BUFSZ__CI__VI 0xC0D4 -#define mmCP_ST_BUFSZ__SI 0x21D4 -#define mmCP_VGT_CSINVOC_COUNT_HI__CI__VI 0xC031 -#define mmCP_VGT_CSINVOC_COUNT_HI__SI 0x2131 -#define mmCP_VGT_CSINVOC_COUNT_LO__CI__VI 0xC030 -#define mmCP_VGT_CSINVOC_COUNT_LO__SI 0x2130 -#define mmCP_VGT_DSINVOC_COUNT_HI__CI__VI 0xC027 -#define mmCP_VGT_DSINVOC_COUNT_HI__SI 0x2127 -#define mmCP_VGT_DSINVOC_COUNT_LO__CI__VI 0xC026 -#define mmCP_VGT_DSINVOC_COUNT_LO__SI 0x2126 -#define mmCP_VGT_GSINVOC_COUNT_HI__CI__VI 0xC023 -#define mmCP_VGT_GSINVOC_COUNT_HI__SI 0x2123 -#define mmCP_VGT_GSINVOC_COUNT_LO__CI__VI 0xC022 -#define mmCP_VGT_GSINVOC_COUNT_LO__SI 0x2122 -#define mmCP_VGT_GSPRIM_COUNT_HI__CI__VI 0xC01F -#define mmCP_VGT_GSPRIM_COUNT_HI__SI 0x211F -#define mmCP_VGT_GSPRIM_COUNT_LO__CI__VI 0xC01E -#define mmCP_VGT_GSPRIM_COUNT_LO__SI 0x211E -#define mmCP_VGT_HSINVOC_COUNT_HI__CI__VI 0xC025 -#define mmCP_VGT_HSINVOC_COUNT_HI__SI 0x2125 -#define mmCP_VGT_HSINVOC_COUNT_LO__CI__VI 0xC024 -#define mmCP_VGT_HSINVOC_COUNT_LO__SI 0x2124 -#define mmCP_VGT_IAPRIM_COUNT_HI__CI__VI 0xC01D -#define mmCP_VGT_IAPRIM_COUNT_HI__SI 0x211D -#define mmCP_VGT_IAPRIM_COUNT_LO__CI__VI 0xC01C -#define mmCP_VGT_IAPRIM_COUNT_LO__SI 0x211C -#define mmCP_VGT_IAVERT_COUNT_HI__CI__VI 0xC01B -#define mmCP_VGT_IAVERT_COUNT_HI__SI 0x211B -#define mmCP_VGT_IAVERT_COUNT_LO__CI__VI 0xC01A -#define mmCP_VGT_IAVERT_COUNT_LO__SI 0x211A -#define mmCP_VGT_VSINVOC_COUNT_HI__CI__VI 0xC021 -#define mmCP_VGT_VSINVOC_COUNT_HI__SI 0x2121 -#define mmCP_VGT_VSINVOC_COUNT_LO__CI__VI 0xC020 -#define mmCP_VGT_VSINVOC_COUNT_LO__SI 0x2120 -#define mmCP_VMID 0xA0DA -#define mmCP_VMID_PREEMPT__CI__VI 0x30B6 -#define mmCP_VMID_RESET__CI__VI 0x30B3 -#define mmCP_WAIT_REG_MEM_TIMEOUT__CI__VI 0xC074 -#define mmCP_WAIT_REG_MEM_TIMEOUT__SI 0x2174 -#define mmCP_WAIT_SEM_ADDR_HI__CI__VI 0xC076 -#define mmCP_WAIT_SEM_ADDR_HI__SI 0x2176 -#define mmCP_WAIT_SEM_ADDR_LO__CI__VI 0xC075 -#define mmCP_WAIT_SEM_ADDR_LO__SI 0x2175 -#define mmCP_WAIT_SEM_STATUS__CI 0xC073 -#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__SI 0x1BC3 -#define mmCRTC0_CRTC_BLACK_COLOR__SI 0x1BA2 -#define mmCRTC0_CRTC_BLANK_CONTROL__SI 0x1B9D -#define mmCRTC0_CRTC_BLANK_DATA_COLOR__SI 0x1BA1 -#define mmCRTC0_CRTC_CONTROL__SI 0x1B9C -#define mmCRTC0_CRTC_COUNT_CONTROL__SI 0x1BA9 -#define mmCRTC0_CRTC_COUNT_RESET__SI 0x1BAA -#define mmCRTC0_CRTC_DEBUG_BITS__SI 0x1BC5 -#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL__SI 0x1BB6 -#define mmCRTC0_CRTC_DTMTEST_CNTL__SI 0x1B92 -#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION__SI 0x1B93 -#define mmCRTC0_CRTC_FLOW_CONTROL__SI 0x1B99 -#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL__SI 0x1B98 -#define mmCRTC0_CRTC_H_BLANK_START_END__SI 0x1B81 -#define mmCRTC0_CRTC_H_SYNC_A_CNTL__SI 0x1B83 -#define mmCRTC0_CRTC_H_SYNC_A__SI 0x1B82 -#define mmCRTC0_CRTC_H_SYNC_B_CNTL__SI 0x1B85 -#define mmCRTC0_CRTC_H_SYNC_B__SI 0x1B84 -#define mmCRTC0_CRTC_H_TOTAL__SI 0x1B80 -#define mmCRTC0_CRTC_INTERLACE_CONTROL__SI 0x1B9E -#define mmCRTC0_CRTC_INTERLACE_STATUS__SI 0x1B9F -#define mmCRTC0_CRTC_INTERRUPT_CONTROL__SI 0x1BB4 -#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI 0x1BAB -#define mmCRTC0_CRTC_MASTER_EN__SI 0x1BC2 -#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI 0x1BC0 -#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT__SI 0x1BBF -#define mmCRTC0_CRTC_MVP_STATUS__SI 0x1BC1 -#define mmCRTC0_CRTC_NOM_VERT_POSITION__SI 0x1BA5 -#define mmCRTC0_CRTC_OVERSCAN_COLOR__SI 0x1BA0 -#define mmCRTC0_CRTC_PIXCLK_DTO_MODULO__SI 0x1BB9 -#define mmCRTC0_CRTC_PIXCLK_DTO_PHASE__SI 0x1BB8 -#define mmCRTC0_CRTC_PIXEL_DATA_READBACK__SI 0x1B9A -#define mmCRTC0_CRTC_SNAPSHOT_CONTROL__SI 0x1BB0 -#define mmCRTC0_CRTC_SNAPSHOT_FRAME__SI 0x1BB2 -#define mmCRTC0_CRTC_SNAPSHOT_POSITION__SI 0x1BB1 -#define mmCRTC0_CRTC_SNAPSHOT_STATUS__SI 0x1BAF -#define mmCRTC0_CRTC_START_LINE_CONTROL__SI 0x1BB3 -#define mmCRTC0_CRTC_STATUS_FRAME_COUNT__SI 0x1BA6 -#define mmCRTC0_CRTC_STATUS_HV_COUNT__SI 0x1BA8 -#define mmCRTC0_CRTC_STATUS_POSITION__SI 0x1BA4 -#define mmCRTC0_CRTC_STATUS_POSITION__VI 0x1BA4 -#define mmCRTC0_CRTC_STATUS_VF_COUNT__SI 0x1BA7 -#define mmCRTC0_CRTC_STATUS__SI 0x1BA3 -#define mmCRTC0_CRTC_STEREO_CONTROL__SI 0x1BAE -#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE__SI 0x1B9B -#define mmCRTC0_CRTC_STEREO_STATUS__SI 0x1BAD -#define mmCRTC0_CRTC_TEST_DEBUG_DATA__SI 0x1BC7 -#define mmCRTC0_CRTC_TEST_DEBUG_INDEX__SI 0x1BC6 -#define mmCRTC0_CRTC_TEST_PATTERN_COLOR__SI 0x1BBC -#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL__SI 0x1BBA -#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS__SI 0x1BBB -#define mmCRTC0_CRTC_TRIGA_CNTL__SI 0x1B94 -#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG__SI 0x1B95 -#define mmCRTC0_CRTC_TRIGB_CNTL__SI 0x1B96 -#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG__SI 0x1B97 -#define mmCRTC0_CRTC_UPDATE_LOCK__SI 0x1BB5 -#define mmCRTC0_CRTC_VBI_END__SI 0x1B86 -#define mmCRTC0_CRTC_VERT_SYNC_CONTROL__SI 0x1BAC -#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI 0x1BB7 -#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS__SI 0x1B8C -#define mmCRTC0_CRTC_V_BLANK_START_END__SI 0x1B8D -#define mmCRTC0_CRTC_V_SYNC_A_CNTL__SI 0x1B8F -#define mmCRTC0_CRTC_V_SYNC_A__SI 0x1B8E -#define mmCRTC0_CRTC_V_SYNC_B_CNTL__SI 0x1B91 -#define mmCRTC0_CRTC_V_SYNC_B__SI 0x1B90 -#define mmCRTC0_CRTC_V_TOTAL_CONTROL__SI 0x1B8A -#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS__SI 0x1B8B -#define mmCRTC0_CRTC_V_TOTAL_MAX__SI 0x1B89 -#define mmCRTC0_CRTC_V_TOTAL_MIN__SI 0x1B88 -#define mmCRTC0_CRTC_V_TOTAL__SI 0x1B87 -#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS__SI 0x1BC4 -#define mmCRTC0_MASTER_UPDATE_LOCK__SI 0x1BBD -#define mmCRTC0_MASTER_UPDATE_MODE__SI 0x1BBE -#define mmCRTC0_MASTER_UPDATE_MODE__VI 0x1BBE -#define mmCRTC0_PIXEL_RATE_CNTL__SI 0x0120 -#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__SI 0x1EC3 -#define mmCRTC1_CRTC_BLACK_COLOR__SI 0x1EA2 -#define mmCRTC1_CRTC_BLANK_CONTROL__SI 0x1E9D -#define mmCRTC1_CRTC_BLANK_DATA_COLOR__SI 0x1EA1 -#define mmCRTC1_CRTC_CONTROL__SI 0x1E9C -#define mmCRTC1_CRTC_COUNT_CONTROL__SI 0x1EA9 -#define mmCRTC1_CRTC_COUNT_RESET__SI 0x1EAA -#define mmCRTC1_CRTC_DEBUG_BITS__SI 0x1EC5 -#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL__SI 0x1EB6 -#define mmCRTC1_CRTC_DTMTEST_CNTL__SI 0x1E92 -#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION__SI 0x1E93 -#define mmCRTC1_CRTC_FLOW_CONTROL__SI 0x1E99 -#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL__SI 0x1E98 -#define mmCRTC1_CRTC_H_BLANK_START_END__SI 0x1E81 -#define mmCRTC1_CRTC_H_SYNC_A_CNTL__SI 0x1E83 -#define mmCRTC1_CRTC_H_SYNC_A__SI 0x1E82 -#define mmCRTC1_CRTC_H_SYNC_B_CNTL__SI 0x1E85 -#define mmCRTC1_CRTC_H_SYNC_B__SI 0x1E84 -#define mmCRTC1_CRTC_H_TOTAL__SI 0x1E80 -#define mmCRTC1_CRTC_INTERLACE_CONTROL__SI 0x1E9E -#define mmCRTC1_CRTC_INTERLACE_STATUS__SI 0x1E9F -#define mmCRTC1_CRTC_INTERRUPT_CONTROL__SI 0x1EB4 -#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI 0x1EAB -#define mmCRTC1_CRTC_MASTER_EN__SI 0x1EC2 -#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI 0x1EC0 -#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT__SI 0x1EBF -#define mmCRTC1_CRTC_MVP_STATUS__SI 0x1EC1 -#define mmCRTC1_CRTC_NOM_VERT_POSITION__SI 0x1EA5 -#define mmCRTC1_CRTC_OVERSCAN_COLOR__SI 0x1EA0 -#define mmCRTC1_CRTC_PIXCLK_DTO_MODULO__SI 0x1EB9 -#define mmCRTC1_CRTC_PIXCLK_DTO_PHASE__SI 0x1EB8 -#define mmCRTC1_CRTC_PIXEL_DATA_READBACK__SI 0x1E9A -#define mmCRTC1_CRTC_SNAPSHOT_CONTROL__SI 0x1EB0 -#define mmCRTC1_CRTC_SNAPSHOT_FRAME__SI 0x1EB2 -#define mmCRTC1_CRTC_SNAPSHOT_POSITION__SI 0x1EB1 -#define mmCRTC1_CRTC_SNAPSHOT_STATUS__SI 0x1EAF -#define mmCRTC1_CRTC_START_LINE_CONTROL__SI 0x1EB3 -#define mmCRTC1_CRTC_STATUS_FRAME_COUNT__SI 0x1EA6 -#define mmCRTC1_CRTC_STATUS_HV_COUNT__SI 0x1EA8 -#define mmCRTC1_CRTC_STATUS_POSITION__SI 0x1EA4 -#define mmCRTC1_CRTC_STATUS_POSITION__VI 0x1DA4 -#define mmCRTC1_CRTC_STATUS_VF_COUNT__SI 0x1EA7 -#define mmCRTC1_CRTC_STATUS__SI 0x1EA3 -#define mmCRTC1_CRTC_STEREO_CONTROL__SI 0x1EAE -#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE__SI 0x1E9B -#define mmCRTC1_CRTC_STEREO_STATUS__SI 0x1EAD -#define mmCRTC1_CRTC_TEST_DEBUG_DATA__SI 0x1EC7 -#define mmCRTC1_CRTC_TEST_DEBUG_INDEX__SI 0x1EC6 -#define mmCRTC1_CRTC_TEST_PATTERN_COLOR__SI 0x1EBC -#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL__SI 0x1EBA -#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS__SI 0x1EBB -#define mmCRTC1_CRTC_TRIGA_CNTL__SI 0x1E94 -#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG__SI 0x1E95 -#define mmCRTC1_CRTC_TRIGB_CNTL__SI 0x1E96 -#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG__SI 0x1E97 -#define mmCRTC1_CRTC_UPDATE_LOCK__SI 0x1EB5 -#define mmCRTC1_CRTC_VBI_END__SI 0x1E86 -#define mmCRTC1_CRTC_VERT_SYNC_CONTROL__SI 0x1EAC -#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI 0x1EB7 -#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS__SI 0x1E8C -#define mmCRTC1_CRTC_V_BLANK_START_END__SI 0x1E8D -#define mmCRTC1_CRTC_V_SYNC_A_CNTL__SI 0x1E8F -#define mmCRTC1_CRTC_V_SYNC_A__SI 0x1E8E -#define mmCRTC1_CRTC_V_SYNC_B_CNTL__SI 0x1E91 -#define mmCRTC1_CRTC_V_SYNC_B__SI 0x1E90 -#define mmCRTC1_CRTC_V_TOTAL_CONTROL__SI 0x1E8A -#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS__SI 0x1E8B -#define mmCRTC1_CRTC_V_TOTAL_MAX__SI 0x1E89 -#define mmCRTC1_CRTC_V_TOTAL_MIN__SI 0x1E88 -#define mmCRTC1_CRTC_V_TOTAL__SI 0x1E87 -#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS__SI 0x1EC4 -#define mmCRTC1_MASTER_UPDATE_LOCK__SI 0x1EBD -#define mmCRTC1_MASTER_UPDATE_MODE__SI 0x1EBE -#define mmCRTC1_MASTER_UPDATE_MODE__VI 0x1DBE -#define mmCRTC1_PIXEL_RATE_CNTL__SI 0x0121 -#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__SI 0x41C3 -#define mmCRTC2_CRTC_BLACK_COLOR__SI 0x41A2 -#define mmCRTC2_CRTC_BLANK_CONTROL__SI 0x419D -#define mmCRTC2_CRTC_BLANK_DATA_COLOR__SI 0x41A1 -#define mmCRTC2_CRTC_CONTROL__SI 0x419C -#define mmCRTC2_CRTC_COUNT_CONTROL__SI 0x41A9 -#define mmCRTC2_CRTC_COUNT_RESET__SI 0x41AA -#define mmCRTC2_CRTC_DEBUG_BITS__SI 0x41C5 -#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL__SI 0x41B6 -#define mmCRTC2_CRTC_DTMTEST_CNTL__SI 0x4192 -#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION__SI 0x4193 -#define mmCRTC2_CRTC_FLOW_CONTROL__SI 0x4199 -#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL__SI 0x4198 -#define mmCRTC2_CRTC_H_BLANK_START_END__SI 0x4181 -#define mmCRTC2_CRTC_H_SYNC_A_CNTL__SI 0x4183 -#define mmCRTC2_CRTC_H_SYNC_A__SI 0x4182 -#define mmCRTC2_CRTC_H_SYNC_B_CNTL__SI 0x4185 -#define mmCRTC2_CRTC_H_SYNC_B__SI 0x4184 -#define mmCRTC2_CRTC_H_TOTAL__SI 0x4180 -#define mmCRTC2_CRTC_INTERLACE_CONTROL__SI 0x419E -#define mmCRTC2_CRTC_INTERLACE_STATUS__SI 0x419F -#define mmCRTC2_CRTC_INTERRUPT_CONTROL__SI 0x41B4 -#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI 0x41AB -#define mmCRTC2_CRTC_MASTER_EN__SI 0x41C2 -#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI 0x41C0 -#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT__SI 0x41BF -#define mmCRTC2_CRTC_MVP_STATUS__SI 0x41C1 -#define mmCRTC2_CRTC_NOM_VERT_POSITION__SI 0x41A5 -#define mmCRTC2_CRTC_OVERSCAN_COLOR__SI 0x41A0 -#define mmCRTC2_CRTC_PIXCLK_DTO_MODULO__SI 0x41B9 -#define mmCRTC2_CRTC_PIXCLK_DTO_PHASE__SI 0x41B8 -#define mmCRTC2_CRTC_PIXEL_DATA_READBACK__SI 0x419A -#define mmCRTC2_CRTC_SNAPSHOT_CONTROL__SI 0x41B0 -#define mmCRTC2_CRTC_SNAPSHOT_FRAME__SI 0x41B2 -#define mmCRTC2_CRTC_SNAPSHOT_POSITION__SI 0x41B1 -#define mmCRTC2_CRTC_SNAPSHOT_STATUS__SI 0x41AF -#define mmCRTC2_CRTC_START_LINE_CONTROL__SI 0x41B3 -#define mmCRTC2_CRTC_STATUS_FRAME_COUNT__SI 0x41A6 -#define mmCRTC2_CRTC_STATUS_HV_COUNT__SI 0x41A8 -#define mmCRTC2_CRTC_STATUS_POSITION__SI 0x41A4 -#define mmCRTC2_CRTC_STATUS_POSITION__VI 0x1FA4 -#define mmCRTC2_CRTC_STATUS_VF_COUNT__SI 0x41A7 -#define mmCRTC2_CRTC_STATUS__SI 0x41A3 -#define mmCRTC2_CRTC_STEREO_CONTROL__SI 0x41AE -#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE__SI 0x419B -#define mmCRTC2_CRTC_STEREO_STATUS__SI 0x41AD -#define mmCRTC2_CRTC_TEST_DEBUG_DATA__SI 0x41C7 -#define mmCRTC2_CRTC_TEST_DEBUG_INDEX__SI 0x41C6 -#define mmCRTC2_CRTC_TEST_PATTERN_COLOR__SI 0x41BC -#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL__SI 0x41BA -#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS__SI 0x41BB -#define mmCRTC2_CRTC_TRIGA_CNTL__SI 0x4194 -#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG__SI 0x4195 -#define mmCRTC2_CRTC_TRIGB_CNTL__SI 0x4196 -#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG__SI 0x4197 -#define mmCRTC2_CRTC_UPDATE_LOCK__SI 0x41B5 -#define mmCRTC2_CRTC_VBI_END__SI 0x4186 -#define mmCRTC2_CRTC_VERT_SYNC_CONTROL__SI 0x41AC -#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI 0x41B7 -#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS__SI 0x418C -#define mmCRTC2_CRTC_V_BLANK_START_END__SI 0x418D -#define mmCRTC2_CRTC_V_SYNC_A_CNTL__SI 0x418F -#define mmCRTC2_CRTC_V_SYNC_A__SI 0x418E -#define mmCRTC2_CRTC_V_SYNC_B_CNTL__SI 0x4191 -#define mmCRTC2_CRTC_V_SYNC_B__SI 0x4190 -#define mmCRTC2_CRTC_V_TOTAL_CONTROL__SI 0x418A -#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS__SI 0x418B -#define mmCRTC2_CRTC_V_TOTAL_MAX__SI 0x4189 -#define mmCRTC2_CRTC_V_TOTAL_MIN__SI 0x4188 -#define mmCRTC2_CRTC_V_TOTAL__SI 0x4187 -#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS__SI 0x41C4 -#define mmCRTC2_MASTER_UPDATE_LOCK__SI 0x41BD -#define mmCRTC2_MASTER_UPDATE_MODE__SI 0x41BE -#define mmCRTC2_MASTER_UPDATE_MODE__VI 0x1FBE -#define mmCRTC2_PIXEL_RATE_CNTL__SI 0x0122 -#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__SI 0x44C3 -#define mmCRTC3_CRTC_BLACK_COLOR__SI 0x44A2 -#define mmCRTC3_CRTC_BLANK_CONTROL__SI 0x449D -#define mmCRTC3_CRTC_BLANK_DATA_COLOR__SI 0x44A1 -#define mmCRTC3_CRTC_CONTROL__SI 0x449C -#define mmCRTC3_CRTC_COUNT_CONTROL__SI 0x44A9 -#define mmCRTC3_CRTC_COUNT_RESET__SI 0x44AA -#define mmCRTC3_CRTC_DEBUG_BITS__SI 0x44C5 -#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL__SI 0x44B6 -#define mmCRTC3_CRTC_DTMTEST_CNTL__SI 0x4492 -#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION__SI 0x4493 -#define mmCRTC3_CRTC_FLOW_CONTROL__SI 0x4499 -#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL__SI 0x4498 -#define mmCRTC3_CRTC_H_BLANK_START_END__SI 0x4481 -#define mmCRTC3_CRTC_H_SYNC_A_CNTL__SI 0x4483 -#define mmCRTC3_CRTC_H_SYNC_A__SI 0x4482 -#define mmCRTC3_CRTC_H_SYNC_B_CNTL__SI 0x4485 -#define mmCRTC3_CRTC_H_SYNC_B__SI 0x4484 -#define mmCRTC3_CRTC_H_TOTAL__SI 0x4480 -#define mmCRTC3_CRTC_INTERLACE_CONTROL__SI 0x449E -#define mmCRTC3_CRTC_INTERLACE_STATUS__SI 0x449F -#define mmCRTC3_CRTC_INTERRUPT_CONTROL__SI 0x44B4 -#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI 0x44AB -#define mmCRTC3_CRTC_MASTER_EN__SI 0x44C2 -#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI 0x44C0 -#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT__SI 0x44BF -#define mmCRTC3_CRTC_MVP_STATUS__SI 0x44C1 -#define mmCRTC3_CRTC_NOM_VERT_POSITION__SI 0x44A5 -#define mmCRTC3_CRTC_OVERSCAN_COLOR__SI 0x44A0 -#define mmCRTC3_CRTC_PIXCLK_DTO_MODULO__SI 0x44B9 -#define mmCRTC3_CRTC_PIXCLK_DTO_PHASE__SI 0x44B8 -#define mmCRTC3_CRTC_PIXEL_DATA_READBACK__SI 0x449A -#define mmCRTC3_CRTC_SNAPSHOT_CONTROL__SI 0x44B0 -#define mmCRTC3_CRTC_SNAPSHOT_FRAME__SI 0x44B2 -#define mmCRTC3_CRTC_SNAPSHOT_POSITION__SI 0x44B1 -#define mmCRTC3_CRTC_SNAPSHOT_STATUS__SI 0x44AF -#define mmCRTC3_CRTC_START_LINE_CONTROL__SI 0x44B3 -#define mmCRTC3_CRTC_STATUS_FRAME_COUNT__SI 0x44A6 -#define mmCRTC3_CRTC_STATUS_HV_COUNT__SI 0x44A8 -#define mmCRTC3_CRTC_STATUS_POSITION__SI 0x44A4 -#define mmCRTC3_CRTC_STATUS_POSITION__VI 0x41A4 -#define mmCRTC3_CRTC_STATUS_VF_COUNT__SI 0x44A7 -#define mmCRTC3_CRTC_STATUS__SI 0x44A3 -#define mmCRTC3_CRTC_STEREO_CONTROL__SI 0x44AE -#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE__SI 0x449B -#define mmCRTC3_CRTC_STEREO_STATUS__SI 0x44AD -#define mmCRTC3_CRTC_TEST_DEBUG_DATA__SI 0x44C7 -#define mmCRTC3_CRTC_TEST_DEBUG_INDEX__SI 0x44C6 -#define mmCRTC3_CRTC_TEST_PATTERN_COLOR__SI 0x44BC -#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL__SI 0x44BA -#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS__SI 0x44BB -#define mmCRTC3_CRTC_TRIGA_CNTL__SI 0x4494 -#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG__SI 0x4495 -#define mmCRTC3_CRTC_TRIGB_CNTL__SI 0x4496 -#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG__SI 0x4497 -#define mmCRTC3_CRTC_UPDATE_LOCK__SI 0x44B5 -#define mmCRTC3_CRTC_VBI_END__SI 0x4486 -#define mmCRTC3_CRTC_VERT_SYNC_CONTROL__SI 0x44AC -#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI 0x44B7 -#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS__SI 0x448C -#define mmCRTC3_CRTC_V_BLANK_START_END__SI 0x448D -#define mmCRTC3_CRTC_V_SYNC_A_CNTL__SI 0x448F -#define mmCRTC3_CRTC_V_SYNC_A__SI 0x448E -#define mmCRTC3_CRTC_V_SYNC_B_CNTL__SI 0x4491 -#define mmCRTC3_CRTC_V_SYNC_B__SI 0x4490 -#define mmCRTC3_CRTC_V_TOTAL_CONTROL__SI 0x448A -#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS__SI 0x448B -#define mmCRTC3_CRTC_V_TOTAL_MAX__SI 0x4489 -#define mmCRTC3_CRTC_V_TOTAL_MIN__SI 0x4488 -#define mmCRTC3_CRTC_V_TOTAL__SI 0x4487 -#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS__SI 0x44C4 -#define mmCRTC3_MASTER_UPDATE_LOCK__SI 0x44BD -#define mmCRTC3_MASTER_UPDATE_MODE__SI 0x44BE -#define mmCRTC3_MASTER_UPDATE_MODE__VI 0x41BE -#define mmCRTC3_PIXEL_RATE_CNTL__SI 0x0123 -#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__SI 0x47C3 -#define mmCRTC4_CRTC_BLACK_COLOR__SI 0x47A2 -#define mmCRTC4_CRTC_BLANK_CONTROL__SI 0x479D -#define mmCRTC4_CRTC_BLANK_DATA_COLOR__SI 0x47A1 -#define mmCRTC4_CRTC_CONTROL__SI 0x479C -#define mmCRTC4_CRTC_COUNT_CONTROL__SI 0x47A9 -#define mmCRTC4_CRTC_COUNT_RESET__SI 0x47AA -#define mmCRTC4_CRTC_DEBUG_BITS__SI 0x47C5 -#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL__SI 0x47B6 -#define mmCRTC4_CRTC_DTMTEST_CNTL__SI 0x4792 -#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION__SI 0x4793 -#define mmCRTC4_CRTC_FLOW_CONTROL__SI 0x4799 -#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL__SI 0x4798 -#define mmCRTC4_CRTC_H_BLANK_START_END__SI 0x4781 -#define mmCRTC4_CRTC_H_SYNC_A_CNTL__SI 0x4783 -#define mmCRTC4_CRTC_H_SYNC_A__SI 0x4782 -#define mmCRTC4_CRTC_H_SYNC_B_CNTL__SI 0x4785 -#define mmCRTC4_CRTC_H_SYNC_B__SI 0x4784 -#define mmCRTC4_CRTC_H_TOTAL__SI 0x4780 -#define mmCRTC4_CRTC_INTERLACE_CONTROL__SI 0x479E -#define mmCRTC4_CRTC_INTERLACE_STATUS__SI 0x479F -#define mmCRTC4_CRTC_INTERRUPT_CONTROL__SI 0x47B4 -#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI 0x47AB -#define mmCRTC4_CRTC_MASTER_EN__SI 0x47C2 -#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI 0x47C0 -#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT__SI 0x47BF -#define mmCRTC4_CRTC_MVP_STATUS__SI 0x47C1 -#define mmCRTC4_CRTC_NOM_VERT_POSITION__SI 0x47A5 -#define mmCRTC4_CRTC_OVERSCAN_COLOR__SI 0x47A0 -#define mmCRTC4_CRTC_PIXCLK_DTO_MODULO__SI 0x47B9 -#define mmCRTC4_CRTC_PIXCLK_DTO_PHASE__SI 0x47B8 -#define mmCRTC4_CRTC_PIXEL_DATA_READBACK__SI 0x479A -#define mmCRTC4_CRTC_SNAPSHOT_CONTROL__SI 0x47B0 -#define mmCRTC4_CRTC_SNAPSHOT_FRAME__SI 0x47B2 -#define mmCRTC4_CRTC_SNAPSHOT_POSITION__SI 0x47B1 -#define mmCRTC4_CRTC_SNAPSHOT_STATUS__SI 0x47AF -#define mmCRTC4_CRTC_START_LINE_CONTROL__SI 0x47B3 -#define mmCRTC4_CRTC_STATUS_FRAME_COUNT__SI 0x47A6 -#define mmCRTC4_CRTC_STATUS_HV_COUNT__SI 0x47A8 -#define mmCRTC4_CRTC_STATUS_POSITION__SI 0x47A4 -#define mmCRTC4_CRTC_STATUS_POSITION__VI 0x43A4 -#define mmCRTC4_CRTC_STATUS_VF_COUNT__SI 0x47A7 -#define mmCRTC4_CRTC_STATUS__SI 0x47A3 -#define mmCRTC4_CRTC_STEREO_CONTROL__SI 0x47AE -#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE__SI 0x479B -#define mmCRTC4_CRTC_STEREO_STATUS__SI 0x47AD -#define mmCRTC4_CRTC_TEST_DEBUG_DATA__SI 0x47C7 -#define mmCRTC4_CRTC_TEST_DEBUG_INDEX__SI 0x47C6 -#define mmCRTC4_CRTC_TEST_PATTERN_COLOR__SI 0x47BC -#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL__SI 0x47BA -#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS__SI 0x47BB -#define mmCRTC4_CRTC_TRIGA_CNTL__SI 0x4794 -#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG__SI 0x4795 -#define mmCRTC4_CRTC_TRIGB_CNTL__SI 0x4796 -#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG__SI 0x4797 -#define mmCRTC4_CRTC_UPDATE_LOCK__SI 0x47B5 -#define mmCRTC4_CRTC_VBI_END__SI 0x4786 -#define mmCRTC4_CRTC_VERT_SYNC_CONTROL__SI 0x47AC -#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI 0x47B7 -#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS__SI 0x478C -#define mmCRTC4_CRTC_V_BLANK_START_END__SI 0x478D -#define mmCRTC4_CRTC_V_SYNC_A_CNTL__SI 0x478F -#define mmCRTC4_CRTC_V_SYNC_A__SI 0x478E -#define mmCRTC4_CRTC_V_SYNC_B_CNTL__SI 0x4791 -#define mmCRTC4_CRTC_V_SYNC_B__SI 0x4790 -#define mmCRTC4_CRTC_V_TOTAL_CONTROL__SI 0x478A -#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS__SI 0x478B -#define mmCRTC4_CRTC_V_TOTAL_MAX__SI 0x4789 -#define mmCRTC4_CRTC_V_TOTAL_MIN__SI 0x4788 -#define mmCRTC4_CRTC_V_TOTAL__SI 0x4787 -#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS__SI 0x47C4 -#define mmCRTC4_MASTER_UPDATE_LOCK__SI 0x47BD -#define mmCRTC4_MASTER_UPDATE_MODE__SI 0x47BE -#define mmCRTC4_MASTER_UPDATE_MODE__VI 0x43BE -#define mmCRTC4_PIXEL_RATE_CNTL__SI 0x0124 -#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__SI 0x4AC3 -#define mmCRTC5_CRTC_BLACK_COLOR__SI 0x4AA2 -#define mmCRTC5_CRTC_BLANK_CONTROL__SI 0x4A9D -#define mmCRTC5_CRTC_BLANK_DATA_COLOR__SI 0x4AA1 -#define mmCRTC5_CRTC_CONTROL__SI 0x4A9C -#define mmCRTC5_CRTC_COUNT_CONTROL__SI 0x4AA9 -#define mmCRTC5_CRTC_COUNT_RESET__SI 0x4AAA -#define mmCRTC5_CRTC_DEBUG_BITS__SI 0x4AC5 -#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL__SI 0x4AB6 -#define mmCRTC5_CRTC_DTMTEST_CNTL__SI 0x4A92 -#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION__SI 0x4A93 -#define mmCRTC5_CRTC_FLOW_CONTROL__SI 0x4A99 -#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL__SI 0x4A98 -#define mmCRTC5_CRTC_H_BLANK_START_END__SI 0x4A81 -#define mmCRTC5_CRTC_H_SYNC_A_CNTL__SI 0x4A83 -#define mmCRTC5_CRTC_H_SYNC_A__SI 0x4A82 -#define mmCRTC5_CRTC_H_SYNC_B_CNTL__SI 0x4A85 -#define mmCRTC5_CRTC_H_SYNC_B__SI 0x4A84 -#define mmCRTC5_CRTC_H_TOTAL__SI 0x4A80 -#define mmCRTC5_CRTC_INTERLACE_CONTROL__SI 0x4A9E -#define mmCRTC5_CRTC_INTERLACE_STATUS__SI 0x4A9F -#define mmCRTC5_CRTC_INTERRUPT_CONTROL__SI 0x4AB4 -#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI 0x4AAB -#define mmCRTC5_CRTC_MASTER_EN__SI 0x4AC2 -#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI 0x4AC0 -#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT__SI 0x4ABF -#define mmCRTC5_CRTC_MVP_STATUS__SI 0x4AC1 -#define mmCRTC5_CRTC_NOM_VERT_POSITION__SI 0x4AA5 -#define mmCRTC5_CRTC_OVERSCAN_COLOR__SI 0x4AA0 -#define mmCRTC5_CRTC_PIXCLK_DTO_MODULO__SI 0x4AB9 -#define mmCRTC5_CRTC_PIXCLK_DTO_PHASE__SI 0x4AB8 -#define mmCRTC5_CRTC_PIXEL_DATA_READBACK__SI 0x4A9A -#define mmCRTC5_CRTC_SNAPSHOT_CONTROL__SI 0x4AB0 -#define mmCRTC5_CRTC_SNAPSHOT_FRAME__SI 0x4AB2 -#define mmCRTC5_CRTC_SNAPSHOT_POSITION__SI 0x4AB1 -#define mmCRTC5_CRTC_SNAPSHOT_STATUS__SI 0x4AAF -#define mmCRTC5_CRTC_START_LINE_CONTROL__SI 0x4AB3 -#define mmCRTC5_CRTC_STATUS_FRAME_COUNT__SI 0x4AA6 -#define mmCRTC5_CRTC_STATUS_HV_COUNT__SI 0x4AA8 -#define mmCRTC5_CRTC_STATUS_POSITION__SI 0x4AA4 -#define mmCRTC5_CRTC_STATUS_POSITION__VI 0x45A4 -#define mmCRTC5_CRTC_STATUS_VF_COUNT__SI 0x4AA7 -#define mmCRTC5_CRTC_STATUS__SI 0x4AA3 -#define mmCRTC5_CRTC_STEREO_CONTROL__SI 0x4AAE -#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE__SI 0x4A9B -#define mmCRTC5_CRTC_STEREO_STATUS__SI 0x4AAD -#define mmCRTC5_CRTC_TEST_DEBUG_DATA__SI 0x4AC7 -#define mmCRTC5_CRTC_TEST_DEBUG_INDEX__SI 0x4AC6 -#define mmCRTC5_CRTC_TEST_PATTERN_COLOR__SI 0x4ABC -#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL__SI 0x4ABA -#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS__SI 0x4ABB -#define mmCRTC5_CRTC_TRIGA_CNTL__SI 0x4A94 -#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG__SI 0x4A95 -#define mmCRTC5_CRTC_TRIGB_CNTL__SI 0x4A96 -#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG__SI 0x4A97 -#define mmCRTC5_CRTC_UPDATE_LOCK__SI 0x4AB5 -#define mmCRTC5_CRTC_VBI_END__SI 0x4A86 -#define mmCRTC5_CRTC_VERT_SYNC_CONTROL__SI 0x4AAC -#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI 0x4AB7 -#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS__SI 0x4A8C -#define mmCRTC5_CRTC_V_BLANK_START_END__SI 0x4A8D -#define mmCRTC5_CRTC_V_SYNC_A_CNTL__SI 0x4A8F -#define mmCRTC5_CRTC_V_SYNC_A__SI 0x4A8E -#define mmCRTC5_CRTC_V_SYNC_B_CNTL__SI 0x4A91 -#define mmCRTC5_CRTC_V_SYNC_B__SI 0x4A90 -#define mmCRTC5_CRTC_V_TOTAL_CONTROL__SI 0x4A8A -#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS__SI 0x4A8B -#define mmCRTC5_CRTC_V_TOTAL_MAX__SI 0x4A89 -#define mmCRTC5_CRTC_V_TOTAL_MIN__SI 0x4A88 -#define mmCRTC5_CRTC_V_TOTAL__SI 0x4A87 -#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS__SI 0x4AC4 -#define mmCRTC5_MASTER_UPDATE_LOCK__SI 0x4ABD -#define mmCRTC5_MASTER_UPDATE_MODE__SI 0x4ABE -#define mmCRTC5_MASTER_UPDATE_MODE__VI 0x45BE -#define mmCRTC5_PIXEL_RATE_CNTL__SI 0x0125 -#define mmCRTC8_DATA__SI 0x00ED -#define mmCRTC8_DATA_alt_1__SI 0x00F5 -#define mmCRTC8_IDX__SI 0x00ED -#define mmCRTC8_IDX_alt_1__SI 0x00F5 -#define mmCRTC_ALLOW_STOP_OFF_V_CNT__SI 0x1BC3 -#define mmCRTC_BLACK_COLOR__SI 0x1BA2 -#define mmCRTC_BLANK_CONTROL__SI 0x1B9D -#define mmCRTC_BLANK_DATA_COLOR__SI 0x1BA1 -#define mmCRTC_CONTROL__SI 0x1B9C -#define mmCRTC_COUNT_CONTROL__SI 0x1BA9 -#define mmCRTC_COUNT_RESET__SI 0x1BAA -#define mmCRTC_DEBUG_BITS__SI 0x1BC5 -#define mmCRTC_DOUBLE_BUFFER_CONTROL__SI 0x1BB6 -#define mmCRTC_DTMTEST_CNTL__SI 0x1B92 -#define mmCRTC_DTMTEST_STATUS_POSITION__SI 0x1B93 -#define mmCRTC_FLOW_CONTROL__SI 0x1B99 -#define mmCRTC_FORCE_COUNT_NOW_CNTL__SI 0x1B98 -#define mmCRTC_H_BLANK_START_END__SI 0x1B81 -#define mmCRTC_H_SYNC_A_CNTL__SI 0x1B83 -#define mmCRTC_H_SYNC_A__SI 0x1B82 -#define mmCRTC_H_SYNC_B_CNTL__SI 0x1B85 -#define mmCRTC_H_SYNC_B__SI 0x1B84 -#define mmCRTC_H_TOTAL__SI 0x1B80 -#define mmCRTC_INTERLACE_CONTROL__SI 0x1B9E -#define mmCRTC_INTERLACE_STATUS__SI 0x1B9F -#define mmCRTC_INTERRUPT_CONTROL__SI 0x1BB4 -#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI 0x1BAB -#define mmCRTC_MASTER_EN__SI 0x1BC2 -#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI 0x1BC0 -#define mmCRTC_MVP_INBAND_CNTL_INSERT__SI 0x1BBF -#define mmCRTC_MVP_STATUS__SI 0x1BC1 -#define mmCRTC_NOM_VERT_POSITION__SI 0x1BA5 -#define mmCRTC_OVERSCAN_COLOR__SI 0x1BA0 -#define mmCRTC_PIXCLK_DTO_MODULO__SI 0x1BB9 -#define mmCRTC_PIXCLK_DTO_PHASE__SI 0x1BB8 -#define mmCRTC_PIXEL_DATA_READBACK__SI 0x1B9A -#define mmCRTC_SNAPSHOT_CONTROL__SI 0x1BB0 -#define mmCRTC_SNAPSHOT_FRAME__SI 0x1BB2 -#define mmCRTC_SNAPSHOT_POSITION__SI 0x1BB1 -#define mmCRTC_SNAPSHOT_STATUS__SI 0x1BAF -#define mmCRTC_START_LINE_CONTROL__SI 0x1BB3 -#define mmCRTC_STATUS_FRAME_COUNT__SI 0x1BA6 -#define mmCRTC_STATUS_HV_COUNT__SI 0x1BA8 -#define mmCRTC_STATUS_POSITION__SI 0x1BA4 -#define mmCRTC_STATUS_VF_COUNT__SI 0x1BA7 -#define mmCRTC_STATUS__SI 0x1BA3 -#define mmCRTC_STEREO_CONTROL__SI 0x1BAE -#define mmCRTC_STEREO_FORCE_NEXT_EYE__SI 0x1B9B -#define mmCRTC_STEREO_STATUS__SI 0x1BAD -#define mmCRTC_TEST_DEBUG_DATA__SI 0x1BC7 -#define mmCRTC_TEST_DEBUG_INDEX__SI 0x1BC6 -#define mmCRTC_TEST_PATTERN_COLOR__SI 0x1BBC -#define mmCRTC_TEST_PATTERN_CONTROL__SI 0x1BBA -#define mmCRTC_TEST_PATTERN_PARAMETERS__SI 0x1BBB -#define mmCRTC_TRIGA_CNTL__SI 0x1B94 -#define mmCRTC_TRIGA_MANUAL_TRIG__SI 0x1B95 -#define mmCRTC_TRIGB_CNTL__SI 0x1B96 -#define mmCRTC_TRIGB_MANUAL_TRIG__SI 0x1B97 -#define mmCRTC_UPDATE_LOCK__SI 0x1BB5 -#define mmCRTC_VBI_END__SI 0x1B86 -#define mmCRTC_VERT_SYNC_CONTROL__SI 0x1BAC -#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE__SI 0x1BB7 -#define mmCRTC_VSYNC_NOM_INT_STATUS__SI 0x1B8C -#define mmCRTC_V_BLANK_START_END__SI 0x1B8D -#define mmCRTC_V_SYNC_A_CNTL__SI 0x1B8F -#define mmCRTC_V_SYNC_A__SI 0x1B8E -#define mmCRTC_V_SYNC_B_CNTL__SI 0x1B91 -#define mmCRTC_V_SYNC_B__SI 0x1B90 -#define mmCRTC_V_TOTAL_CONTROL__SI 0x1B8A -#define mmCRTC_V_TOTAL_INT_STATUS__SI 0x1B8B -#define mmCRTC_V_TOTAL_MAX__SI 0x1B89 -#define mmCRTC_V_TOTAL_MIN__SI 0x1B88 -#define mmCRTC_V_TOTAL__SI 0x1B87 -#define mmCRTC_V_UPDATE_INT_STATUS__SI 0x1BC4 -#define mmCS_COPY_STATE 0xA1F3 -#define mmCUR_COLOR1__SI 0x1A6C -#define mmCUR_COLOR2__SI 0x1A6D -#define mmCUR_CONTROL__SI 0x1A66 -#define mmCUR_HOT_SPOT__SI 0x1A6B -#define mmCUR_POSITION__SI 0x1A6A -#define mmCUR_SIZE__SI 0x1A68 -#define mmCUR_SURFACE_ADDRESS_HIGH__SI 0x1A69 -#define mmCUR_SURFACE_ADDRESS__SI 0x1A67 -#define mmCUR_UPDATE__SI 0x1A6E -#define mmD1VGA_CONTROL__SI 0x00CC -#define mmD1_PROTECTION__SI 0x1805 -#define mmD2VGA_CONTROL__SI 0x00CE -#define mmD2_PROTECTION__SI 0x1806 -#define mmD3VGA_CONTROL__SI 0x00F8 -#define mmD3_PROTECTION__SI 0x184F -#define mmD4VGA_CONTROL__SI 0x00F9 -#define mmD4_PROTECTION__SI 0x1850 -#define mmD5VGA_CONTROL__SI 0x00FA -#define mmD5_PROTECTION__SI 0x1851 -#define mmD6VGA_CONTROL__SI 0x00FB -#define mmD6_PROTECTION__SI 0x1852 -#define mmDAC0_DAC_AUTODETECT_CONTROL2__SI 0x19AF -#define mmDAC0_DAC_AUTODETECT_CONTROL3__SI 0x19B0 -#define mmDAC0_DAC_AUTODETECT_CONTROL__SI 0x19AE -#define mmDAC0_DAC_AUTODETECT_INT_CONTROL__SI 0x19B2 -#define mmDAC0_DAC_AUTODETECT_STATUS__SI 0x19B1 -#define mmDAC0_DAC_COMPARATOR_ENABLE__SI 0x19B7 -#define mmDAC0_DAC_COMPARATOR_OUTPUT__SI 0x19B8 -#define mmDAC0_DAC_CONTROL__SI 0x19B6 -#define mmDAC0_DAC_CRC_CONTROL__SI 0x19A7 -#define mmDAC0_DAC_CRC_EN__SI 0x19A6 -#define mmDAC0_DAC_CRC_SIG_CONTROL_MASK__SI 0x19A9 -#define mmDAC0_DAC_CRC_SIG_CONTROL__SI 0x19AB -#define mmDAC0_DAC_CRC_SIG_RGB_MASK__SI 0x19A8 -#define mmDAC0_DAC_CRC_SIG_RGB__SI 0x19AA -#define mmDAC0_DAC_DFT_CONFIG__SI 0x19BA -#define mmDAC0_DAC_ENABLE__SI 0x19A4 -#define mmDAC0_DAC_FORCE_DATA__SI 0x19B4 -#define mmDAC0_DAC_FORCE_OUTPUT_CNTL__SI 0x19B3 -#define mmDAC0_DAC_POWERDOWN__SI 0x19B5 -#define mmDAC0_DAC_PWR_CNTL__SI 0x19B9 -#define mmDAC0_DAC_SOURCE_SELECT__SI 0x19A5 -#define mmDAC0_DAC_STEREOSYNC_SELECT__SI 0x19AD -#define mmDAC0_DAC_SYNC_TRISTATE_CONTROL__SI 0x19AC -#define mmDAC1_DAC_AUTODETECT_CONTROL2__SI 0x19EF -#define mmDAC1_DAC_AUTODETECT_CONTROL3__SI 0x19F0 -#define mmDAC1_DAC_AUTODETECT_CONTROL__SI 0x19EE -#define mmDAC1_DAC_AUTODETECT_INT_CONTROL__SI 0x19F2 -#define mmDAC1_DAC_AUTODETECT_STATUS__SI 0x19F1 -#define mmDAC1_DAC_COMPARATOR_ENABLE__SI 0x19F7 -#define mmDAC1_DAC_COMPARATOR_OUTPUT__SI 0x19F8 -#define mmDAC1_DAC_CONTROL__SI 0x19F6 -#define mmDAC1_DAC_CRC_CONTROL__SI 0x19E7 -#define mmDAC1_DAC_CRC_EN__SI 0x19E6 -#define mmDAC1_DAC_CRC_SIG_CONTROL_MASK__SI 0x19E9 -#define mmDAC1_DAC_CRC_SIG_CONTROL__SI 0x19EB -#define mmDAC1_DAC_CRC_SIG_RGB_MASK__SI 0x19E8 -#define mmDAC1_DAC_CRC_SIG_RGB__SI 0x19EA -#define mmDAC1_DAC_DFT_CONFIG__SI 0x19FA -#define mmDAC1_DAC_ENABLE__SI 0x19E4 -#define mmDAC1_DAC_FORCE_DATA__SI 0x19F4 -#define mmDAC1_DAC_FORCE_OUTPUT_CNTL__SI 0x19F3 -#define mmDAC1_DAC_POWERDOWN__SI 0x19F5 -#define mmDAC1_DAC_PWR_CNTL__SI 0x19F9 -#define mmDAC1_DAC_SOURCE_SELECT__SI 0x19E5 -#define mmDAC1_DAC_STEREOSYNC_SELECT__SI 0x19ED -#define mmDAC1_DAC_SYNC_TRISTATE_CONTROL__SI 0x19EC -#define mmDAC_AUTODETECT_CONTROL2__SI 0x19AF -#define mmDAC_AUTODETECT_CONTROL3__SI 0x19B0 -#define mmDAC_AUTODETECT_CONTROL__SI 0x19AE -#define mmDAC_AUTODETECT_INT_CONTROL__SI 0x19B2 -#define mmDAC_AUTODETECT_STATUS__SI 0x19B1 -#define mmDAC_AUTO_CALIB_CONTROL__SI 0x193A -#define mmDAC_BGADJ_CONTROL__SI 0x1938 -#define mmDAC_COMPARATOR_ENABLE__SI 0x19B7 -#define mmDAC_COMPARATOR_OUTPUT__SI 0x19B8 -#define mmDAC_CONTROL__SI 0x19B6 -#define mmDAC_CRC_CONTROL__SI 0x19A7 -#define mmDAC_CRC_EN__SI 0x19A6 -#define mmDAC_CRC_SIG_CONTROL_MASK__SI 0x19A9 -#define mmDAC_CRC_SIG_CONTROL__SI 0x19AB -#define mmDAC_CRC_SIG_RGB_MASK__SI 0x19A8 -#define mmDAC_CRC_SIG_RGB__SI 0x19AA -#define mmDAC_DATA__SI 0x00F2 -#define mmDAC_DFT_CONFIG__SI 0x19BA -#define mmDAC_ENABLE__SI 0x19A4 -#define mmDAC_FORCE_DATA__SI 0x19B4 -#define mmDAC_FORCE_OUTPUT_CNTL__SI 0x19B3 -#define mmDAC_MACRO_CNTL__SI 0x1939 -#define mmDAC_MASK__SI 0x00F1 -#define mmDAC_POWERDOWN__SI 0x19B5 -#define mmDAC_PWR_CNTL__SI 0x19B9 -#define mmDAC_R_INDEX__SI 0x00F1 -#define mmDAC_SOURCE_SELECT__SI 0x19A5 -#define mmDAC_STEREOSYNC_SELECT__SI 0x19AD -#define mmDAC_SYNC_TRISTATE_CONTROL__SI 0x19AC -#define mmDAC_TEST_ENABLE__SI 0x193B -#define mmDAC_W_INDEX__SI 0x00F2 -#define mmDATA_FORMAT__SI 0x1AC0 -#define mmDBG_BUS_OUT1 0x03C1 -#define mmDBG_BYPASS_SRBM_ACCESS__CI 0x14EB -#define mmDBG_CHAIN_CONTROL 0x03C0 -#define mmDBW_CHROMA_BOT_ADDR__SI 0x389B -#define mmDBW_CHROMA_TOP_ADDR__SI 0x389A -#define mmDBW_LUMA_BOT_ADDR__SI 0x3899 -#define mmDBW_LUMA_TOP_ADDR__SI 0x3898 -#define mmDB_ALPHA_TO_MASK 0xA2DC -#define mmDB_BUF_SIZE__SI 0x3FC6 -#define mmDB_CF_DAT__SI 0x3FCC -#define mmDB_CGTT_CLK_CTRL_0__CI__VI 0xF0A4 -#define mmDB_CGTT_CLK_CTRL_0__SI 0x261A -#define mmDB_COUNT_CONTROL 0xA001 -#define mmDB_CREDIT_LIMIT 0x2614 -#define mmDB_CTL__SI 0x3FC2 -#define mmDB_DBG_CTL__SI 0x3FD4 -#define mmDB_DBG_STAT__SI 0x3FD6 -#define mmDB_DEBUG 0x260C -#define mmDB_DEBUG2 0x260D -#define mmDB_DEBUG3 0x260E -#define mmDB_DEBUG4 0x260F -#define mmDB_DEBUG_INT_STAT__SI 0x3FD7 -#define mmDB_DEPTH_BOUNDS_MAX 0xA009 -#define mmDB_DEPTH_BOUNDS_MIN 0xA008 -#define mmDB_DEPTH_CLEAR 0xA00B -#define mmDB_DEPTH_CONTROL 0xA200 -#define mmDB_DEPTH_INFO 0xA00F -#define mmDB_DEPTH_SIZE 0xA016 -#define mmDB_DEPTH_SLICE 0xA017 -#define mmDB_DEPTH_VIEW 0xA002 -#define mmDB_EQAA 0xA201 -#define mmDB_ERRCONCEAL_CONTROL__SI 0x3FD9 -#define mmDB_ERRDET_CONTROL__SI 0x3FD3 -#define mmDB_ERRDET__SI 0x3FD2 -#define mmDB_FIFO_DEPTH1 0x2618 -#define mmDB_FIFO_DEPTH2 0x2619 -#define mmDB_FREE_CACHELINES 0x2617 -#define mmDB_GREY_LEVELS__SI 0x3FC8 -#define mmDB_HTILE_DATA_BASE 0xA005 -#define mmDB_HTILE_SURFACE 0xA2AF -#define mmDB_HW_DEBUG__SI 0x3FD8 -#define mmDB_INTRA_HOR_ADR__SI 0x3FC7 -#define mmDB_INT_EN__SI 0x3FC0 -#define mmDB_INT_STAT__SI 0x3FC1 -#define mmDB_LMA_ADR__SI 0x3FCE -#define mmDB_LMA_CTL__SI 0x3FCD -#define mmDB_LMA_DAT__SI 0x3FCF -#define mmDB_LUMA_ADR__SI 0x3FC4 -#define mmDB_OCCLUSION_COUNT0_HI__CI__VI 0xC3C1 -#define mmDB_OCCLUSION_COUNT0_LOW__CI__VI 0xC3C0 -#define mmDB_OCCLUSION_COUNT1_HI__CI__VI 0xC3C3 -#define mmDB_OCCLUSION_COUNT1_LOW__CI__VI 0xC3C2 -#define mmDB_OCCLUSION_COUNT2_HI__CI__VI 0xC3C5 -#define mmDB_OCCLUSION_COUNT2_LOW__CI__VI 0xC3C4 -#define mmDB_OCCLUSION_COUNT3_HI__CI__VI 0xC3C7 -#define mmDB_OCCLUSION_COUNT3_LOW__CI__VI 0xC3C6 -#define mmDB_PERFCOUNTER0_HI__CI__VI 0xD441 -#define mmDB_PERFCOUNTER0_HI__SI 0x2602 -#define mmDB_PERFCOUNTER0_LO__CI__VI 0xD440 -#define mmDB_PERFCOUNTER0_LO__SI 0x2601 -#define mmDB_PERFCOUNTER0_SELECT1__CI__VI 0xDC41 -#define mmDB_PERFCOUNTER0_SELECT__CI__VI 0xDC40 -#define mmDB_PERFCOUNTER0_SELECT__SI 0x2600 -#define mmDB_PERFCOUNTER1_HI__CI__VI 0xD443 -#define mmDB_PERFCOUNTER1_HI__SI 0x2605 -#define mmDB_PERFCOUNTER1_LO__CI__VI 0xD442 -#define mmDB_PERFCOUNTER1_LO__SI 0x2604 -#define mmDB_PERFCOUNTER1_SELECT1__CI__VI 0xDC43 -#define mmDB_PERFCOUNTER1_SELECT__CI__VI 0xDC42 -#define mmDB_PERFCOUNTER1_SELECT__SI 0x2603 -#define mmDB_PERFCOUNTER2_HI__CI__VI 0xD445 -#define mmDB_PERFCOUNTER2_HI__SI 0x2608 -#define mmDB_PERFCOUNTER2_LO__CI__VI 0xD444 -#define mmDB_PERFCOUNTER2_LO__SI 0x2607 -#define mmDB_PERFCOUNTER2_SELECT__CI__VI 0xDC44 -#define mmDB_PERFCOUNTER2_SELECT__SI 0x2606 -#define mmDB_PERFCOUNTER3_HI__CI__VI 0xD447 -#define mmDB_PERFCOUNTER3_HI__SI 0x260B -#define mmDB_PERFCOUNTER3_LO__CI__VI 0xD446 -#define mmDB_PERFCOUNTER3_LO__SI 0x260A -#define mmDB_PERFCOUNTER3_SELECT__CI__VI 0xDC46 -#define mmDB_PERFCOUNTER3_SELECT__SI 0x2609 -#define mmDB_PRELOAD_CONTROL 0xA2B2 -#define mmDB_READ_DEBUG_0 0x2620 -#define mmDB_READ_DEBUG_1 0x2621 -#define mmDB_READ_DEBUG_2 0x2622 -#define mmDB_READ_DEBUG_3 0x2623 -#define mmDB_READ_DEBUG_4 0x2624 -#define mmDB_READ_DEBUG_5 0x2625 -#define mmDB_READ_DEBUG_6 0x2626 -#define mmDB_READ_DEBUG_7 0x2627 -#define mmDB_READ_DEBUG_8 0x2628 -#define mmDB_READ_DEBUG_9 0x2629 -#define mmDB_READ_DEBUG_A 0x262A -#define mmDB_READ_DEBUG_B 0x262B -#define mmDB_READ_DEBUG_C 0x262C -#define mmDB_READ_DEBUG_D 0x262D -#define mmDB_READ_DEBUG_E 0x262E -#define mmDB_READ_DEBUG_F 0x262F -#define mmDB_RENDER_CONTROL 0xA000 -#define mmDB_RENDER_OVERRIDE 0xA003 -#define mmDB_RENDER_OVERRIDE2 0xA004 -#define mmDB_RING_CONTROL__CI__VI 0x261B -#define mmDB_SHADER_CONTROL 0xA203 -#define mmDB_SLICE_INFO__SI 0x3FCA -#define mmDB_SPS_INFO__SI 0x3FC9 -#define mmDB_SRAM_RM_CTL__SI 0x3FD0 -#define mmDB_SRESULTS_COMPARE_STATE0 0xA2B0 -#define mmDB_SRESULTS_COMPARE_STATE1 0xA2B1 -#define mmDB_STAT__SI 0x3FC3 -#define mmDB_STENCILREFMASK 0xA10C -#define mmDB_STENCILREFMASK_BF 0xA10D -#define mmDB_STENCIL_CLEAR 0xA00A -#define mmDB_STENCIL_CONTROL 0xA10B -#define mmDB_STENCIL_INFO 0xA011 -#define mmDB_STENCIL_READ_BASE 0xA013 -#define mmDB_STENCIL_WRITE_BASE 0xA015 -#define mmDB_SUBTILE_CONTROL 0x2616 -#define mmDB_TOP_Y_PIC__SI 0x3FC5 -#define mmDB_UPROC_STAT__SI 0x3FD5 -#define mmDB_VC1_SP_CONTEXT__SI 0x3FD1 -#define mmDB_WATERMARKS 0x2615 -#define mmDB_ZPASS_COUNT_HI__CI__VI 0xC3FF -#define mmDB_ZPASS_COUNT_HI__SI 0x261D -#define mmDB_ZPASS_COUNT_LOW__CI__VI 0xC3FE -#define mmDB_ZPASS_COUNT_LOW__SI 0x261C -#define mmDB_Z_INFO 0xA010 -#define mmDB_Z_READ_BASE 0xA012 -#define mmDB_Z_WRITE_BASE 0xA014 -#define mmDCCG_AUDIO_DTO0_CNTL__SI 0x0156 -#define mmDCCG_AUDIO_DTO0_LOAD__SI 0x0155 -#define mmDCCG_AUDIO_DTO0_MODULE__SI 0x0154 -#define mmDCCG_AUDIO_DTO0_PHASE__SI 0x0153 -#define mmDCCG_AUDIO_DTO_SELECT__SI 0x0157 -#define mmDCCG_CG_PLL_PIXCLK_SEL__SI 0x0149 -#define mmDCCG_DEBUG__SI 0x0152 -#define mmDCCG_GATE_DISABLE_CNTL__SI 0x011F -#define mmDCCG_TEST_CLK_SEL__SI 0x0147 -#define mmDCCG_TEST_DEBUG_DATA__SI 0x0159 -#define mmDCCG_TEST_DEBUG_INDEX__SI 0x0158 -#define mmDCCG_VPCLK_CNTL__SI 0x015E -#define mmDCDEBUG_BUS_CLK1_SEL__SI 0x1860 -#define mmDCDEBUG_BUS_CLK2_SEL__SI 0x1861 -#define mmDCDEBUG_BUS_CLK3_SEL__SI 0x1862 -#define mmDCDEBUG_BUS_CLK4_SEL__SI 0x1863 -#define mmDCDEBUG_DATA_TRIGGER_MASK__SI 0x1868 -#define mmDCDEBUG_DATA_TRIGGER_PATTERN__SI 0x1869 -#define mmDCDEBUG_EDGE_TRIGGER_MASK__SI 0x1866 -#define mmDCDEBUG_EDGE_TRIGGER_PATTERN__SI 0x1867 -#define mmDCDEBUG_OUT_CNTL__SI 0x186B -#define mmDCDEBUG_OUT_PIN_OVERRIDE__SI 0x186A -#define mmDCDEBUG_TRIGGER_CNTL__SI 0x1864 -#define mmDCDEBUG_TRIGGER_STAT__SI 0x1865 -#define mmDCFE0_CLOCK_ENABLE__SI 0x0130 -#define mmDCFE1_CLOCK_ENABLE__SI 0x0131 -#define mmDCFE2_CLOCK_ENABLE__SI 0x0132 -#define mmDCFE3_CLOCK_ENABLE__SI 0x0133 -#define mmDCFE4_CLOCK_ENABLE__SI 0x0134 -#define mmDCFE5_CLOCK_ENABLE__SI 0x0135 -#define mmDCIO_DAC0_DAC_AUTO_CALIB_CONTROL__SI 0x193A -#define mmDCIO_DAC0_DAC_BGADJ_CONTROL__SI 0x1938 -#define mmDCIO_DAC0_DAC_MACRO_CNTL__SI 0x1939 -#define mmDCIO_DAC0_DAC_TEST_ENABLE__SI 0x193B -#define mmDCIO_DAC1_DAC_AUTO_CALIB_CONTROL__SI 0x197A -#define mmDCIO_DAC1_DAC_BGADJ_CONTROL__SI 0x1978 -#define mmDCIO_DAC1_DAC_MACRO_CNTL__SI 0x1979 -#define mmDCIO_DAC1_DAC_TEST_ENABLE__SI 0x197B -#define mmDCIO_DEBUG__SI 0x196F -#define mmDCIO_IMPCAL_CNTL_AB__SI 0x194C -#define mmDCIO_IMPCAL_CNTL_CD__SI 0x194F -#define mmDCIO_IMPCAL_CNTL_EF__SI 0x1952 -#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION__SI 0x1984 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CONTROL1__SI 0x1980 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CONTROL2__SI 0x1981 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CONTROL3__SI 0x1982 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CONTROL4__SI 0x1983 -#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT__SI 0x1986 -#define mmDCIO_UNIPHY0_UNIPHY_TRANSMITTER_CONTROL__SI 0x1985 -#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION__SI 0x1990 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CONTROL1__SI 0x198C -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CONTROL2__SI 0x198D -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CONTROL3__SI 0x198E -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CONTROL4__SI 0x198F -#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT__SI 0x1992 -#define mmDCIO_UNIPHY1_UNIPHY_TRANSMITTER_CONTROL__SI 0x1991 -#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION__SI 0x199C -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CONTROL1__SI 0x1998 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CONTROL2__SI 0x1999 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CONTROL3__SI 0x199A -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CONTROL4__SI 0x199B -#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT__SI 0x199E -#define mmDCIO_UNIPHY2_UNIPHY_TRANSMITTER_CONTROL__SI 0x199D -#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION__SI 0x19C4 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CONTROL1__SI 0x19C0 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CONTROL2__SI 0x19C1 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CONTROL3__SI 0x19C2 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CONTROL4__SI 0x19C3 -#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT__SI 0x19C6 -#define mmDCIO_UNIPHY3_UNIPHY_TRANSMITTER_CONTROL__SI 0x19C5 -#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION__SI 0x19D0 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CONTROL1__SI 0x19CC -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CONTROL2__SI 0x19CD -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CONTROL3__SI 0x19CE -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CONTROL4__SI 0x19CF -#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT__SI 0x19D2 -#define mmDCIO_UNIPHY4_UNIPHY_TRANSMITTER_CONTROL__SI 0x19D1 -#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION__SI 0x19DC -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CONTROL1__SI 0x19D8 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CONTROL2__SI 0x19D9 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CONTROL3__SI 0x19DA -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CONTROL4__SI 0x19DB -#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT__SI 0x19DE -#define mmDCIO_UNIPHY5_UNIPHY_TRANSMITTER_CONTROL__SI 0x19DD -#define mmDCI_TEST_DEBUG_DATA__SI 0x0321 -#define mmDCI_TEST_DEBUG_INDEX__SI 0x0320 -#define mmDCP0_COLOR_MATRIX_COEF_1_1__SI 0x1A5A -#define mmDCP0_COLOR_MATRIX_COEF_1_2__SI 0x1A5B -#define mmDCP0_COLOR_MATRIX_COEF_1_3__SI 0x1A5C -#define mmDCP0_COLOR_MATRIX_COEF_1_4__SI 0x1A5D -#define mmDCP0_COLOR_MATRIX_COEF_2_1__SI 0x1A5E -#define mmDCP0_COLOR_MATRIX_COEF_2_2__SI 0x1A5F -#define mmDCP0_COLOR_MATRIX_COEF_2_3__SI 0x1A60 -#define mmDCP0_COLOR_MATRIX_COEF_2_4__SI 0x1A61 -#define mmDCP0_COLOR_MATRIX_COEF_3_1__SI 0x1A62 -#define mmDCP0_COLOR_MATRIX_COEF_3_2__SI 0x1A63 -#define mmDCP0_COLOR_MATRIX_COEF_3_3__SI 0x1A64 -#define mmDCP0_COLOR_MATRIX_COEF_3_4__SI 0x1A65 -#define mmDCP0_COLOR_SPACE_CONVERT__SI 0x1A0F -#define mmDCP0_CUR_COLOR1__SI 0x1A6C -#define mmDCP0_CUR_COLOR2__SI 0x1A6D -#define mmDCP0_CUR_CONTROL__SI 0x1A66 -#define mmDCP0_CUR_HOT_SPOT__SI 0x1A6B -#define mmDCP0_CUR_POSITION__SI 0x1A6A -#define mmDCP0_CUR_SIZE__SI 0x1A68 -#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH__SI 0x1A69 -#define mmDCP0_CUR_SURFACE_ADDRESS__SI 0x1A67 -#define mmDCP0_CUR_UPDATE__SI 0x1A6E -#define mmDCP0_DCP_CONTROL__SI 0x1A8E -#define mmDCP0_DCP_CRC_CONTROL__SI 0x1A87 -#define mmDCP0_DCP_CRC_CURRENT__SI 0x1A89 -#define mmDCP0_DCP_CRC_LAST__SI 0x1A8B -#define mmDCP0_DCP_CRC_MASK__SI 0x1A88 -#define mmDCP0_DCP_DEBUG__SI 0x1A8D -#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI 0x1A91 -#define mmDCP0_DCP_MULTI_CHIP_CNTL__SI 0x1A90 -#define mmDCP0_DCP_TEST_DEBUG_DATA__SI 0x1A96 -#define mmDCP0_DCP_TEST_DEBUG_INDEX__SI 0x1A95 -#define mmDCP0_DCP_TILING_CONFIG__SI 0x1A8F -#define mmDCP0_DC_LUT_30_COLOR__SI 0x1A7C -#define mmDCP0_DC_LUT_AUTOFILL__SI 0x1A7F -#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE__SI 0x1A81 -#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN__SI 0x1A82 -#define mmDCP0_DC_LUT_BLACK_OFFSET_RED__SI 0x1A83 -#define mmDCP0_DC_LUT_CONTROL__SI 0x1A80 -#define mmDCP0_DC_LUT_PWL_DATA__SI 0x1A7B -#define mmDCP0_DC_LUT_RW_INDEX__SI 0x1A79 -#define mmDCP0_DC_LUT_RW_MODE__SI 0x1A78 -#define mmDCP0_DC_LUT_SEQ_COLOR__SI 0x1A7A -#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE__SI 0x1A84 -#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN__SI 0x1A85 -#define mmDCP0_DC_LUT_WHITE_OFFSET_RED__SI 0x1A86 -#define mmDCP0_DC_LUT_WRITE_EN_MASK__SI 0x1A7E -#define mmDCP0_GRPH_ALPHA__SI 0x1A4E -#define mmDCP0_GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x1A59 -#define mmDCP0_GRPH_COMPRESS_PITCH__SI 0x1A1A -#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI 0x1A1B -#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS__SI 0x1A19 -#define mmDCP0_GRPH_CONTROL__SI 0x1A01 -#define mmDCP0_GRPH_CONTROL__VI 0x1A01 -#define mmDCP0_GRPH_DFQ_CONTROL__SI 0x1A14 -#define mmDCP0_GRPH_DFQ_STATUS__SI 0x1A15 -#define mmDCP0_GRPH_ENABLE__SI 0x1A00 -#define mmDCP0_GRPH_FLIP_CONTROL__SI 0x1A12 -#define mmDCP0_GRPH_FLIP_CONTROL__VI 0x1A12 -#define mmDCP0_GRPH_INTERRUPT_CONTROL__SI 0x1A17 -#define mmDCP0_GRPH_INTERRUPT_STATUS__SI 0x1A16 -#define mmDCP0_GRPH_KEY_RANGE_ALPHA__SI 0x1A54 -#define mmDCP0_GRPH_KEY_RANGE_BLUE__SI 0x1A53 -#define mmDCP0_GRPH_KEY_RANGE_GREEN__SI 0x1A52 -#define mmDCP0_GRPH_KEY_RANGE_RED__SI 0x1A51 -#define mmDCP0_GRPH_LUT_10BIT_BYPASS__SI 0x1A02 -#define mmDCP0_GRPH_PITCH__SI 0x1A06 -#define mmDCP0_GRPH_PITCH__VI 0x1A06 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI 0x1A07 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS__SI 0x1A04 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI 0x1A07 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS__VI 0x1A04 -#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI 0x1A08 -#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS__SI 0x1A05 -#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI 0x1A18 -#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE__SI 0x1A13 -#define mmDCP0_GRPH_SURFACE_OFFSET_X__SI 0x1A09 -#define mmDCP0_GRPH_SURFACE_OFFSET_Y__SI 0x1A0A -#define mmDCP0_GRPH_SWAP_CNTL__SI 0x1A03 -#define mmDCP0_GRPH_UPDATE__SI 0x1A11 -#define mmDCP0_GRPH_UPDATE__VI 0x1A11 -#define mmDCP0_GRPH_X_END__SI 0x1A0D -#define mmDCP0_GRPH_X_START__SI 0x1A0B -#define mmDCP0_GRPH_Y_END__SI 0x1A0E -#define mmDCP0_GRPH_Y_START__SI 0x1A0C -#define mmDCP0_ICON_COLOR1__SI 0x1A74 -#define mmDCP0_ICON_COLOR2__SI 0x1A75 -#define mmDCP0_ICON_CONTROL__SI 0x1A6F -#define mmDCP0_ICON_SIZE__SI 0x1A71 -#define mmDCP0_ICON_START_POSITION__SI 0x1A73 -#define mmDCP0_ICON_SURFACE_ADDRESS_HIGH__SI 0x1A72 -#define mmDCP0_ICON_SURFACE_ADDRESS__SI 0x1A70 -#define mmDCP0_ICON_UPDATE__SI 0x1A76 -#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL__SI 0x1A2C -#define mmDCP0_OVL_ALPHA_CONTROL__SI 0x1A50 -#define mmDCP0_OVL_ALPHA__SI 0x1A4F -#define mmDCP0_OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x1A10 -#define mmDCP0_OVL_CONTROL1__SI 0x1A1D -#define mmDCP0_OVL_CONTROL2__SI 0x1A1E -#define mmDCP0_OVL_DFQ_CONTROL__SI 0x1A29 -#define mmDCP0_OVL_DFQ_STATUS__SI 0x1A2A -#define mmDCP0_OVL_ENABLE__SI 0x1A1C -#define mmDCP0_OVL_END__SI 0x1A26 -#define mmDCP0_OVL_KEY_ALPHA__SI 0x1A58 -#define mmDCP0_OVL_KEY_CONTROL__SI 0x1A4D -#define mmDCP0_OVL_KEY_RANGE_BLUE_CB__SI 0x1A57 -#define mmDCP0_OVL_KEY_RANGE_GREEN_Y__SI 0x1A56 -#define mmDCP0_OVL_KEY_RANGE_RED_CR__SI 0x1A55 -#define mmDCP0_OVL_MATRIX_COEF_1_1__SI 0x1A2E -#define mmDCP0_OVL_MATRIX_COEF_1_2__SI 0x1A2F -#define mmDCP0_OVL_MATRIX_COEF_1_3__SI 0x1A30 -#define mmDCP0_OVL_MATRIX_COEF_1_4__SI 0x1A31 -#define mmDCP0_OVL_MATRIX_COEF_2_1__SI 0x1A32 -#define mmDCP0_OVL_MATRIX_COEF_2_2__SI 0x1A33 -#define mmDCP0_OVL_MATRIX_COEF_2_3__SI 0x1A34 -#define mmDCP0_OVL_MATRIX_COEF_2_4__SI 0x1A35 -#define mmDCP0_OVL_MATRIX_COEF_3_1__SI 0x1A36 -#define mmDCP0_OVL_MATRIX_COEF_3_2__SI 0x1A37 -#define mmDCP0_OVL_MATRIX_COEF_3_3__SI 0x1A38 -#define mmDCP0_OVL_MATRIX_COEF_3_4__SI 0x1A39 -#define mmDCP0_OVL_MATRIX_TRANSFORM_EN__SI 0x1A2D -#define mmDCP0_OVL_PITCH__SI 0x1A21 -#define mmDCP0_OVL_PWL_0TOF__SI 0x1A3B -#define mmDCP0_OVL_PWL_100TO13F__SI 0x1A41 -#define mmDCP0_OVL_PWL_10TO1F__SI 0x1A3C -#define mmDCP0_OVL_PWL_140TO17F__SI 0x1A42 -#define mmDCP0_OVL_PWL_180TO1BF__SI 0x1A43 -#define mmDCP0_OVL_PWL_1C0TO1FF__SI 0x1A44 -#define mmDCP0_OVL_PWL_200TO23F__SI 0x1A45 -#define mmDCP0_OVL_PWL_20TO3F__SI 0x1A3D -#define mmDCP0_OVL_PWL_240TO27F__SI 0x1A46 -#define mmDCP0_OVL_PWL_280TO2BF__SI 0x1A47 -#define mmDCP0_OVL_PWL_2C0TO2FF__SI 0x1A48 -#define mmDCP0_OVL_PWL_300TO33F__SI 0x1A49 -#define mmDCP0_OVL_PWL_340TO37F__SI 0x1A4A -#define mmDCP0_OVL_PWL_380TO3BF__SI 0x1A4B -#define mmDCP0_OVL_PWL_3C0TO3FF__SI 0x1A4C -#define mmDCP0_OVL_PWL_40TO7F__SI 0x1A3E -#define mmDCP0_OVL_PWL_80TOBF__SI 0x1A3F -#define mmDCP0_OVL_PWL_C0TOFF__SI 0x1A40 -#define mmDCP0_OVL_PWL_TRANSFORM_EN__SI 0x1A3A -#define mmDCP0_OVL_START__SI 0x1A25 -#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI 0x1A2B -#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH__SI 0x1A22 -#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE__SI 0x1A28 -#define mmDCP0_OVL_SURFACE_ADDRESS__SI 0x1A20 -#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH__VI 0x1A22 -#define mmDCP0_OVL_SURFACE_ADDRESS__VI 0x1A20 -#define mmDCP0_OVL_SURFACE_OFFSET_X__SI 0x1A23 -#define mmDCP0_OVL_SURFACE_OFFSET_Y__SI 0x1A24 -#define mmDCP0_OVL_SWAP_CNTL__SI 0x1A1F -#define mmDCP0_OVL_UPDATE__SI 0x1A27 -#define mmDCP1_COLOR_MATRIX_COEF_1_1__SI 0x1D5A -#define mmDCP1_COLOR_MATRIX_COEF_1_2__SI 0x1D5B -#define mmDCP1_COLOR_MATRIX_COEF_1_3__SI 0x1D5C -#define mmDCP1_COLOR_MATRIX_COEF_1_4__SI 0x1D5D -#define mmDCP1_COLOR_MATRIX_COEF_2_1__SI 0x1D5E -#define mmDCP1_COLOR_MATRIX_COEF_2_2__SI 0x1D5F -#define mmDCP1_COLOR_MATRIX_COEF_2_3__SI 0x1D60 -#define mmDCP1_COLOR_MATRIX_COEF_2_4__SI 0x1D61 -#define mmDCP1_COLOR_MATRIX_COEF_3_1__SI 0x1D62 -#define mmDCP1_COLOR_MATRIX_COEF_3_2__SI 0x1D63 -#define mmDCP1_COLOR_MATRIX_COEF_3_3__SI 0x1D64 -#define mmDCP1_COLOR_MATRIX_COEF_3_4__SI 0x1D65 -#define mmDCP1_COLOR_SPACE_CONVERT__SI 0x1D0F -#define mmDCP1_CUR_COLOR1__SI 0x1D6C -#define mmDCP1_CUR_COLOR2__SI 0x1D6D -#define mmDCP1_CUR_CONTROL__SI 0x1D66 -#define mmDCP1_CUR_HOT_SPOT__SI 0x1D6B -#define mmDCP1_CUR_POSITION__SI 0x1D6A -#define mmDCP1_CUR_SIZE__SI 0x1D68 -#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH__SI 0x1D69 -#define mmDCP1_CUR_SURFACE_ADDRESS__SI 0x1D67 -#define mmDCP1_CUR_UPDATE__SI 0x1D6E -#define mmDCP1_DCP_CONTROL__SI 0x1D8E -#define mmDCP1_DCP_CRC_CONTROL__SI 0x1D87 -#define mmDCP1_DCP_CRC_CURRENT__SI 0x1D89 -#define mmDCP1_DCP_CRC_LAST__SI 0x1D8B -#define mmDCP1_DCP_CRC_MASK__SI 0x1D88 -#define mmDCP1_DCP_DEBUG__SI 0x1D8D -#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI 0x1D91 -#define mmDCP1_DCP_MULTI_CHIP_CNTL__SI 0x1D90 -#define mmDCP1_DCP_TEST_DEBUG_DATA__SI 0x1D96 -#define mmDCP1_DCP_TEST_DEBUG_INDEX__SI 0x1D95 -#define mmDCP1_DCP_TILING_CONFIG__SI 0x1D8F -#define mmDCP1_DC_LUT_30_COLOR__SI 0x1D7C -#define mmDCP1_DC_LUT_AUTOFILL__SI 0x1D7F -#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE__SI 0x1D81 -#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN__SI 0x1D82 -#define mmDCP1_DC_LUT_BLACK_OFFSET_RED__SI 0x1D83 -#define mmDCP1_DC_LUT_CONTROL__SI 0x1D80 -#define mmDCP1_DC_LUT_PWL_DATA__SI 0x1D7B -#define mmDCP1_DC_LUT_RW_INDEX__SI 0x1D79 -#define mmDCP1_DC_LUT_RW_MODE__SI 0x1D78 -#define mmDCP1_DC_LUT_SEQ_COLOR__SI 0x1D7A -#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE__SI 0x1D84 -#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN__SI 0x1D85 -#define mmDCP1_DC_LUT_WHITE_OFFSET_RED__SI 0x1D86 -#define mmDCP1_DC_LUT_WRITE_EN_MASK__SI 0x1D7E -#define mmDCP1_GRPH_ALPHA__SI 0x1D4E -#define mmDCP1_GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x1D59 -#define mmDCP1_GRPH_COMPRESS_PITCH__SI 0x1D1A -#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI 0x1D1B -#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS__SI 0x1D19 -#define mmDCP1_GRPH_CONTROL__SI 0x1D01 -#define mmDCP1_GRPH_CONTROL__VI 0x1C01 -#define mmDCP1_GRPH_DFQ_CONTROL__SI 0x1D14 -#define mmDCP1_GRPH_DFQ_STATUS__SI 0x1D15 -#define mmDCP1_GRPH_ENABLE__SI 0x1D00 -#define mmDCP1_GRPH_FLIP_CONTROL__SI 0x1D12 -#define mmDCP1_GRPH_FLIP_CONTROL__VI 0x1C12 -#define mmDCP1_GRPH_INTERRUPT_CONTROL__SI 0x1D17 -#define mmDCP1_GRPH_INTERRUPT_STATUS__SI 0x1D16 -#define mmDCP1_GRPH_KEY_RANGE_ALPHA__SI 0x1D54 -#define mmDCP1_GRPH_KEY_RANGE_BLUE__SI 0x1D53 -#define mmDCP1_GRPH_KEY_RANGE_GREEN__SI 0x1D52 -#define mmDCP1_GRPH_KEY_RANGE_RED__SI 0x1D51 -#define mmDCP1_GRPH_LUT_10BIT_BYPASS__SI 0x1D02 -#define mmDCP1_GRPH_PITCH__SI 0x1D06 -#define mmDCP1_GRPH_PITCH__VI 0x1C06 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI 0x1D07 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS__SI 0x1D04 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI 0x1C07 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS__VI 0x1C04 -#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI 0x1D08 -#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS__SI 0x1D05 -#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI 0x1D18 -#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE__SI 0x1D13 -#define mmDCP1_GRPH_SURFACE_OFFSET_X__SI 0x1D09 -#define mmDCP1_GRPH_SURFACE_OFFSET_Y__SI 0x1D0A -#define mmDCP1_GRPH_SWAP_CNTL__SI 0x1D03 -#define mmDCP1_GRPH_UPDATE__SI 0x1D11 -#define mmDCP1_GRPH_UPDATE__VI 0x1C11 -#define mmDCP1_GRPH_X_END__SI 0x1D0D -#define mmDCP1_GRPH_X_START__SI 0x1D0B -#define mmDCP1_GRPH_Y_END__SI 0x1D0E -#define mmDCP1_GRPH_Y_START__SI 0x1D0C -#define mmDCP1_ICON_COLOR1__SI 0x1D74 -#define mmDCP1_ICON_COLOR2__SI 0x1D75 -#define mmDCP1_ICON_CONTROL__SI 0x1D6F -#define mmDCP1_ICON_SIZE__SI 0x1D71 -#define mmDCP1_ICON_START_POSITION__SI 0x1D73 -#define mmDCP1_ICON_SURFACE_ADDRESS_HIGH__SI 0x1D72 -#define mmDCP1_ICON_SURFACE_ADDRESS__SI 0x1D70 -#define mmDCP1_ICON_UPDATE__SI 0x1D76 -#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL__SI 0x1D2C -#define mmDCP1_OVL_ALPHA_CONTROL__SI 0x1D50 -#define mmDCP1_OVL_ALPHA__SI 0x1D4F -#define mmDCP1_OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x1D10 -#define mmDCP1_OVL_CONTROL1__SI 0x1D1D -#define mmDCP1_OVL_CONTROL2__SI 0x1D1E -#define mmDCP1_OVL_DFQ_CONTROL__SI 0x1D29 -#define mmDCP1_OVL_DFQ_STATUS__SI 0x1D2A -#define mmDCP1_OVL_ENABLE__SI 0x1D1C -#define mmDCP1_OVL_END__SI 0x1D26 -#define mmDCP1_OVL_KEY_ALPHA__SI 0x1D58 -#define mmDCP1_OVL_KEY_CONTROL__SI 0x1D4D -#define mmDCP1_OVL_KEY_RANGE_BLUE_CB__SI 0x1D57 -#define mmDCP1_OVL_KEY_RANGE_GREEN_Y__SI 0x1D56 -#define mmDCP1_OVL_KEY_RANGE_RED_CR__SI 0x1D55 -#define mmDCP1_OVL_MATRIX_COEF_1_1__SI 0x1D2E -#define mmDCP1_OVL_MATRIX_COEF_1_2__SI 0x1D2F -#define mmDCP1_OVL_MATRIX_COEF_1_3__SI 0x1D30 -#define mmDCP1_OVL_MATRIX_COEF_1_4__SI 0x1D31 -#define mmDCP1_OVL_MATRIX_COEF_2_1__SI 0x1D32 -#define mmDCP1_OVL_MATRIX_COEF_2_2__SI 0x1D33 -#define mmDCP1_OVL_MATRIX_COEF_2_3__SI 0x1D34 -#define mmDCP1_OVL_MATRIX_COEF_2_4__SI 0x1D35 -#define mmDCP1_OVL_MATRIX_COEF_3_1__SI 0x1D36 -#define mmDCP1_OVL_MATRIX_COEF_3_2__SI 0x1D37 -#define mmDCP1_OVL_MATRIX_COEF_3_3__SI 0x1D38 -#define mmDCP1_OVL_MATRIX_COEF_3_4__SI 0x1D39 -#define mmDCP1_OVL_MATRIX_TRANSFORM_EN__SI 0x1D2D -#define mmDCP1_OVL_PITCH__SI 0x1D21 -#define mmDCP1_OVL_PWL_0TOF__SI 0x1D3B -#define mmDCP1_OVL_PWL_100TO13F__SI 0x1D41 -#define mmDCP1_OVL_PWL_10TO1F__SI 0x1D3C -#define mmDCP1_OVL_PWL_140TO17F__SI 0x1D42 -#define mmDCP1_OVL_PWL_180TO1BF__SI 0x1D43 -#define mmDCP1_OVL_PWL_1C0TO1FF__SI 0x1D44 -#define mmDCP1_OVL_PWL_200TO23F__SI 0x1D45 -#define mmDCP1_OVL_PWL_20TO3F__SI 0x1D3D -#define mmDCP1_OVL_PWL_240TO27F__SI 0x1D46 -#define mmDCP1_OVL_PWL_280TO2BF__SI 0x1D47 -#define mmDCP1_OVL_PWL_2C0TO2FF__SI 0x1D48 -#define mmDCP1_OVL_PWL_300TO33F__SI 0x1D49 -#define mmDCP1_OVL_PWL_340TO37F__SI 0x1D4A -#define mmDCP1_OVL_PWL_380TO3BF__SI 0x1D4B -#define mmDCP1_OVL_PWL_3C0TO3FF__SI 0x1D4C -#define mmDCP1_OVL_PWL_40TO7F__SI 0x1D3E -#define mmDCP1_OVL_PWL_80TOBF__SI 0x1D3F -#define mmDCP1_OVL_PWL_C0TOFF__SI 0x1D40 -#define mmDCP1_OVL_PWL_TRANSFORM_EN__SI 0x1D3A -#define mmDCP1_OVL_START__SI 0x1D25 -#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI 0x1D2B -#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH__SI 0x1D22 -#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE__SI 0x1D28 -#define mmDCP1_OVL_SURFACE_ADDRESS__SI 0x1D20 -#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH__VI 0x1C22 -#define mmDCP1_OVL_SURFACE_ADDRESS__VI 0x1C20 -#define mmDCP1_OVL_SURFACE_OFFSET_X__SI 0x1D23 -#define mmDCP1_OVL_SURFACE_OFFSET_Y__SI 0x1D24 -#define mmDCP1_OVL_SWAP_CNTL__SI 0x1D1F -#define mmDCP1_OVL_UPDATE__SI 0x1D27 -#define mmDCP2_COLOR_MATRIX_COEF_1_1__SI 0x405A -#define mmDCP2_COLOR_MATRIX_COEF_1_2__SI 0x405B -#define mmDCP2_COLOR_MATRIX_COEF_1_3__SI 0x405C -#define mmDCP2_COLOR_MATRIX_COEF_1_4__SI 0x405D -#define mmDCP2_COLOR_MATRIX_COEF_2_1__SI 0x405E -#define mmDCP2_COLOR_MATRIX_COEF_2_2__SI 0x405F -#define mmDCP2_COLOR_MATRIX_COEF_2_3__SI 0x4060 -#define mmDCP2_COLOR_MATRIX_COEF_2_4__SI 0x4061 -#define mmDCP2_COLOR_MATRIX_COEF_3_1__SI 0x4062 -#define mmDCP2_COLOR_MATRIX_COEF_3_2__SI 0x4063 -#define mmDCP2_COLOR_MATRIX_COEF_3_3__SI 0x4064 -#define mmDCP2_COLOR_MATRIX_COEF_3_4__SI 0x4065 -#define mmDCP2_COLOR_SPACE_CONVERT__SI 0x400F -#define mmDCP2_CUR_COLOR1__SI 0x406C -#define mmDCP2_CUR_COLOR2__SI 0x406D -#define mmDCP2_CUR_CONTROL__SI 0x4066 -#define mmDCP2_CUR_HOT_SPOT__SI 0x406B -#define mmDCP2_CUR_POSITION__SI 0x406A -#define mmDCP2_CUR_SIZE__SI 0x4068 -#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH__SI 0x4069 -#define mmDCP2_CUR_SURFACE_ADDRESS__SI 0x4067 -#define mmDCP2_CUR_UPDATE__SI 0x406E -#define mmDCP2_DCP_CONTROL__SI 0x408E -#define mmDCP2_DCP_CRC_CONTROL__SI 0x4087 -#define mmDCP2_DCP_CRC_CURRENT__SI 0x4089 -#define mmDCP2_DCP_CRC_LAST__SI 0x408B -#define mmDCP2_DCP_CRC_MASK__SI 0x4088 -#define mmDCP2_DCP_DEBUG__SI 0x408D -#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI 0x4091 -#define mmDCP2_DCP_MULTI_CHIP_CNTL__SI 0x4090 -#define mmDCP2_DCP_TEST_DEBUG_DATA__SI 0x4096 -#define mmDCP2_DCP_TEST_DEBUG_INDEX__SI 0x4095 -#define mmDCP2_DCP_TILING_CONFIG__SI 0x408F -#define mmDCP2_DC_LUT_30_COLOR__SI 0x407C -#define mmDCP2_DC_LUT_AUTOFILL__SI 0x407F -#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE__SI 0x4081 -#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN__SI 0x4082 -#define mmDCP2_DC_LUT_BLACK_OFFSET_RED__SI 0x4083 -#define mmDCP2_DC_LUT_CONTROL__SI 0x4080 -#define mmDCP2_DC_LUT_PWL_DATA__SI 0x407B -#define mmDCP2_DC_LUT_RW_INDEX__SI 0x4079 -#define mmDCP2_DC_LUT_RW_MODE__SI 0x4078 -#define mmDCP2_DC_LUT_SEQ_COLOR__SI 0x407A -#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE__SI 0x4084 -#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN__SI 0x4085 -#define mmDCP2_DC_LUT_WHITE_OFFSET_RED__SI 0x4086 -#define mmDCP2_DC_LUT_WRITE_EN_MASK__SI 0x407E -#define mmDCP2_GRPH_ALPHA__SI 0x404E -#define mmDCP2_GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4059 -#define mmDCP2_GRPH_COMPRESS_PITCH__SI 0x401A -#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI 0x401B -#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS__SI 0x4019 -#define mmDCP2_GRPH_CONTROL__SI 0x4001 -#define mmDCP2_GRPH_CONTROL__VI 0x1E01 -#define mmDCP2_GRPH_DFQ_CONTROL__SI 0x4014 -#define mmDCP2_GRPH_DFQ_STATUS__SI 0x4015 -#define mmDCP2_GRPH_ENABLE__SI 0x4000 -#define mmDCP2_GRPH_FLIP_CONTROL__SI 0x4012 -#define mmDCP2_GRPH_FLIP_CONTROL__VI 0x1E12 -#define mmDCP2_GRPH_INTERRUPT_CONTROL__SI 0x4017 -#define mmDCP2_GRPH_INTERRUPT_STATUS__SI 0x4016 -#define mmDCP2_GRPH_KEY_RANGE_ALPHA__SI 0x4054 -#define mmDCP2_GRPH_KEY_RANGE_BLUE__SI 0x4053 -#define mmDCP2_GRPH_KEY_RANGE_GREEN__SI 0x4052 -#define mmDCP2_GRPH_KEY_RANGE_RED__SI 0x4051 -#define mmDCP2_GRPH_LUT_10BIT_BYPASS__SI 0x4002 -#define mmDCP2_GRPH_PITCH__SI 0x4006 -#define mmDCP2_GRPH_PITCH__VI 0x1E06 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI 0x4007 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS__SI 0x4004 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI 0x1E07 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS__VI 0x1E04 -#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI 0x4008 -#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS__SI 0x4005 -#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI 0x4018 -#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE__SI 0x4013 -#define mmDCP2_GRPH_SURFACE_OFFSET_X__SI 0x4009 -#define mmDCP2_GRPH_SURFACE_OFFSET_Y__SI 0x400A -#define mmDCP2_GRPH_SWAP_CNTL__SI 0x4003 -#define mmDCP2_GRPH_UPDATE__SI 0x4011 -#define mmDCP2_GRPH_UPDATE__VI 0x1E11 -#define mmDCP2_GRPH_X_END__SI 0x400D -#define mmDCP2_GRPH_X_START__SI 0x400B -#define mmDCP2_GRPH_Y_END__SI 0x400E -#define mmDCP2_GRPH_Y_START__SI 0x400C -#define mmDCP2_ICON_COLOR1__SI 0x4074 -#define mmDCP2_ICON_COLOR2__SI 0x4075 -#define mmDCP2_ICON_CONTROL__SI 0x406F -#define mmDCP2_ICON_SIZE__SI 0x4071 -#define mmDCP2_ICON_START_POSITION__SI 0x4073 -#define mmDCP2_ICON_SURFACE_ADDRESS_HIGH__SI 0x4072 -#define mmDCP2_ICON_SURFACE_ADDRESS__SI 0x4070 -#define mmDCP2_ICON_UPDATE__SI 0x4076 -#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL__SI 0x402C -#define mmDCP2_OVL_ALPHA_CONTROL__SI 0x4050 -#define mmDCP2_OVL_ALPHA__SI 0x404F -#define mmDCP2_OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4010 -#define mmDCP2_OVL_CONTROL1__SI 0x401D -#define mmDCP2_OVL_CONTROL2__SI 0x401E -#define mmDCP2_OVL_DFQ_CONTROL__SI 0x4029 -#define mmDCP2_OVL_DFQ_STATUS__SI 0x402A -#define mmDCP2_OVL_ENABLE__SI 0x401C -#define mmDCP2_OVL_END__SI 0x4026 -#define mmDCP2_OVL_KEY_ALPHA__SI 0x4058 -#define mmDCP2_OVL_KEY_CONTROL__SI 0x404D -#define mmDCP2_OVL_KEY_RANGE_BLUE_CB__SI 0x4057 -#define mmDCP2_OVL_KEY_RANGE_GREEN_Y__SI 0x4056 -#define mmDCP2_OVL_KEY_RANGE_RED_CR__SI 0x4055 -#define mmDCP2_OVL_MATRIX_COEF_1_1__SI 0x402E -#define mmDCP2_OVL_MATRIX_COEF_1_2__SI 0x402F -#define mmDCP2_OVL_MATRIX_COEF_1_3__SI 0x4030 -#define mmDCP2_OVL_MATRIX_COEF_1_4__SI 0x4031 -#define mmDCP2_OVL_MATRIX_COEF_2_1__SI 0x4032 -#define mmDCP2_OVL_MATRIX_COEF_2_2__SI 0x4033 -#define mmDCP2_OVL_MATRIX_COEF_2_3__SI 0x4034 -#define mmDCP2_OVL_MATRIX_COEF_2_4__SI 0x4035 -#define mmDCP2_OVL_MATRIX_COEF_3_1__SI 0x4036 -#define mmDCP2_OVL_MATRIX_COEF_3_2__SI 0x4037 -#define mmDCP2_OVL_MATRIX_COEF_3_3__SI 0x4038 -#define mmDCP2_OVL_MATRIX_COEF_3_4__SI 0x4039 -#define mmDCP2_OVL_MATRIX_TRANSFORM_EN__SI 0x402D -#define mmDCP2_OVL_PITCH__SI 0x4021 -#define mmDCP2_OVL_PWL_0TOF__SI 0x403B -#define mmDCP2_OVL_PWL_100TO13F__SI 0x4041 -#define mmDCP2_OVL_PWL_10TO1F__SI 0x403C -#define mmDCP2_OVL_PWL_140TO17F__SI 0x4042 -#define mmDCP2_OVL_PWL_180TO1BF__SI 0x4043 -#define mmDCP2_OVL_PWL_1C0TO1FF__SI 0x4044 -#define mmDCP2_OVL_PWL_200TO23F__SI 0x4045 -#define mmDCP2_OVL_PWL_20TO3F__SI 0x403D -#define mmDCP2_OVL_PWL_240TO27F__SI 0x4046 -#define mmDCP2_OVL_PWL_280TO2BF__SI 0x4047 -#define mmDCP2_OVL_PWL_2C0TO2FF__SI 0x4048 -#define mmDCP2_OVL_PWL_300TO33F__SI 0x4049 -#define mmDCP2_OVL_PWL_340TO37F__SI 0x404A -#define mmDCP2_OVL_PWL_380TO3BF__SI 0x404B -#define mmDCP2_OVL_PWL_3C0TO3FF__SI 0x404C -#define mmDCP2_OVL_PWL_40TO7F__SI 0x403E -#define mmDCP2_OVL_PWL_80TOBF__SI 0x403F -#define mmDCP2_OVL_PWL_C0TOFF__SI 0x4040 -#define mmDCP2_OVL_PWL_TRANSFORM_EN__SI 0x403A -#define mmDCP2_OVL_START__SI 0x4025 -#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI 0x402B -#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH__SI 0x4022 -#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE__SI 0x4028 -#define mmDCP2_OVL_SURFACE_ADDRESS__SI 0x4020 -#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH__VI 0x1E22 -#define mmDCP2_OVL_SURFACE_ADDRESS__VI 0x1E20 -#define mmDCP2_OVL_SURFACE_OFFSET_X__SI 0x4023 -#define mmDCP2_OVL_SURFACE_OFFSET_Y__SI 0x4024 -#define mmDCP2_OVL_SWAP_CNTL__SI 0x401F -#define mmDCP2_OVL_UPDATE__SI 0x4027 -#define mmDCP3_COLOR_MATRIX_COEF_1_1__SI 0x435A -#define mmDCP3_COLOR_MATRIX_COEF_1_2__SI 0x435B -#define mmDCP3_COLOR_MATRIX_COEF_1_3__SI 0x435C -#define mmDCP3_COLOR_MATRIX_COEF_1_4__SI 0x435D -#define mmDCP3_COLOR_MATRIX_COEF_2_1__SI 0x435E -#define mmDCP3_COLOR_MATRIX_COEF_2_2__SI 0x435F -#define mmDCP3_COLOR_MATRIX_COEF_2_3__SI 0x4360 -#define mmDCP3_COLOR_MATRIX_COEF_2_4__SI 0x4361 -#define mmDCP3_COLOR_MATRIX_COEF_3_1__SI 0x4362 -#define mmDCP3_COLOR_MATRIX_COEF_3_2__SI 0x4363 -#define mmDCP3_COLOR_MATRIX_COEF_3_3__SI 0x4364 -#define mmDCP3_COLOR_MATRIX_COEF_3_4__SI 0x4365 -#define mmDCP3_COLOR_SPACE_CONVERT__SI 0x430F -#define mmDCP3_CUR_COLOR1__SI 0x436C -#define mmDCP3_CUR_COLOR2__SI 0x436D -#define mmDCP3_CUR_CONTROL__SI 0x4366 -#define mmDCP3_CUR_HOT_SPOT__SI 0x436B -#define mmDCP3_CUR_POSITION__SI 0x436A -#define mmDCP3_CUR_SIZE__SI 0x4368 -#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH__SI 0x4369 -#define mmDCP3_CUR_SURFACE_ADDRESS__SI 0x4367 -#define mmDCP3_CUR_UPDATE__SI 0x436E -#define mmDCP3_DCP_CONTROL__SI 0x438E -#define mmDCP3_DCP_CRC_CONTROL__SI 0x4387 -#define mmDCP3_DCP_CRC_CURRENT__SI 0x4389 -#define mmDCP3_DCP_CRC_LAST__SI 0x438B -#define mmDCP3_DCP_CRC_MASK__SI 0x4388 -#define mmDCP3_DCP_DEBUG__SI 0x438D -#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI 0x4391 -#define mmDCP3_DCP_MULTI_CHIP_CNTL__SI 0x4390 -#define mmDCP3_DCP_TEST_DEBUG_DATA__SI 0x4396 -#define mmDCP3_DCP_TEST_DEBUG_INDEX__SI 0x4395 -#define mmDCP3_DCP_TILING_CONFIG__SI 0x438F -#define mmDCP3_DC_LUT_30_COLOR__SI 0x437C -#define mmDCP3_DC_LUT_AUTOFILL__SI 0x437F -#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE__SI 0x4381 -#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN__SI 0x4382 -#define mmDCP3_DC_LUT_BLACK_OFFSET_RED__SI 0x4383 -#define mmDCP3_DC_LUT_CONTROL__SI 0x4380 -#define mmDCP3_DC_LUT_PWL_DATA__SI 0x437B -#define mmDCP3_DC_LUT_RW_INDEX__SI 0x4379 -#define mmDCP3_DC_LUT_RW_MODE__SI 0x4378 -#define mmDCP3_DC_LUT_SEQ_COLOR__SI 0x437A -#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE__SI 0x4384 -#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN__SI 0x4385 -#define mmDCP3_DC_LUT_WHITE_OFFSET_RED__SI 0x4386 -#define mmDCP3_DC_LUT_WRITE_EN_MASK__SI 0x437E -#define mmDCP3_GRPH_ALPHA__SI 0x434E -#define mmDCP3_GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4359 -#define mmDCP3_GRPH_COMPRESS_PITCH__SI 0x431A -#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI 0x431B -#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS__SI 0x4319 -#define mmDCP3_GRPH_CONTROL__SI 0x4301 -#define mmDCP3_GRPH_CONTROL__VI 0x4001 -#define mmDCP3_GRPH_DFQ_CONTROL__SI 0x4314 -#define mmDCP3_GRPH_DFQ_STATUS__SI 0x4315 -#define mmDCP3_GRPH_ENABLE__SI 0x4300 -#define mmDCP3_GRPH_FLIP_CONTROL__SI 0x4312 -#define mmDCP3_GRPH_FLIP_CONTROL__VI 0x4012 -#define mmDCP3_GRPH_INTERRUPT_CONTROL__SI 0x4317 -#define mmDCP3_GRPH_INTERRUPT_STATUS__SI 0x4316 -#define mmDCP3_GRPH_KEY_RANGE_ALPHA__SI 0x4354 -#define mmDCP3_GRPH_KEY_RANGE_BLUE__SI 0x4353 -#define mmDCP3_GRPH_KEY_RANGE_GREEN__SI 0x4352 -#define mmDCP3_GRPH_KEY_RANGE_RED__SI 0x4351 -#define mmDCP3_GRPH_LUT_10BIT_BYPASS__SI 0x4302 -#define mmDCP3_GRPH_PITCH__SI 0x4306 -#define mmDCP3_GRPH_PITCH__VI 0x4006 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI 0x4307 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS__SI 0x4304 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI 0x4007 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS__VI 0x4004 -#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI 0x4308 -#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS__SI 0x4305 -#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI 0x4318 -#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE__SI 0x4313 -#define mmDCP3_GRPH_SURFACE_OFFSET_X__SI 0x4309 -#define mmDCP3_GRPH_SURFACE_OFFSET_Y__SI 0x430A -#define mmDCP3_GRPH_SWAP_CNTL__SI 0x4303 -#define mmDCP3_GRPH_UPDATE__SI 0x4311 -#define mmDCP3_GRPH_UPDATE__VI 0x4011 -#define mmDCP3_GRPH_X_END__SI 0x430D -#define mmDCP3_GRPH_X_START__SI 0x430B -#define mmDCP3_GRPH_Y_END__SI 0x430E -#define mmDCP3_GRPH_Y_START__SI 0x430C -#define mmDCP3_ICON_COLOR1__SI 0x4374 -#define mmDCP3_ICON_COLOR2__SI 0x4375 -#define mmDCP3_ICON_CONTROL__SI 0x436F -#define mmDCP3_ICON_SIZE__SI 0x4371 -#define mmDCP3_ICON_START_POSITION__SI 0x4373 -#define mmDCP3_ICON_SURFACE_ADDRESS_HIGH__SI 0x4372 -#define mmDCP3_ICON_SURFACE_ADDRESS__SI 0x4370 -#define mmDCP3_ICON_UPDATE__SI 0x4376 -#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL__SI 0x432C -#define mmDCP3_OVL_ALPHA_CONTROL__SI 0x4350 -#define mmDCP3_OVL_ALPHA__SI 0x434F -#define mmDCP3_OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4310 -#define mmDCP3_OVL_CONTROL1__SI 0x431D -#define mmDCP3_OVL_CONTROL2__SI 0x431E -#define mmDCP3_OVL_DFQ_CONTROL__SI 0x4329 -#define mmDCP3_OVL_DFQ_STATUS__SI 0x432A -#define mmDCP3_OVL_ENABLE__SI 0x431C -#define mmDCP3_OVL_END__SI 0x4326 -#define mmDCP3_OVL_KEY_ALPHA__SI 0x4358 -#define mmDCP3_OVL_KEY_CONTROL__SI 0x434D -#define mmDCP3_OVL_KEY_RANGE_BLUE_CB__SI 0x4357 -#define mmDCP3_OVL_KEY_RANGE_GREEN_Y__SI 0x4356 -#define mmDCP3_OVL_KEY_RANGE_RED_CR__SI 0x4355 -#define mmDCP3_OVL_MATRIX_COEF_1_1__SI 0x432E -#define mmDCP3_OVL_MATRIX_COEF_1_2__SI 0x432F -#define mmDCP3_OVL_MATRIX_COEF_1_3__SI 0x4330 -#define mmDCP3_OVL_MATRIX_COEF_1_4__SI 0x4331 -#define mmDCP3_OVL_MATRIX_COEF_2_1__SI 0x4332 -#define mmDCP3_OVL_MATRIX_COEF_2_2__SI 0x4333 -#define mmDCP3_OVL_MATRIX_COEF_2_3__SI 0x4334 -#define mmDCP3_OVL_MATRIX_COEF_2_4__SI 0x4335 -#define mmDCP3_OVL_MATRIX_COEF_3_1__SI 0x4336 -#define mmDCP3_OVL_MATRIX_COEF_3_2__SI 0x4337 -#define mmDCP3_OVL_MATRIX_COEF_3_3__SI 0x4338 -#define mmDCP3_OVL_MATRIX_COEF_3_4__SI 0x4339 -#define mmDCP3_OVL_MATRIX_TRANSFORM_EN__SI 0x432D -#define mmDCP3_OVL_PITCH__SI 0x4321 -#define mmDCP3_OVL_PWL_0TOF__SI 0x433B -#define mmDCP3_OVL_PWL_100TO13F__SI 0x4341 -#define mmDCP3_OVL_PWL_10TO1F__SI 0x433C -#define mmDCP3_OVL_PWL_140TO17F__SI 0x4342 -#define mmDCP3_OVL_PWL_180TO1BF__SI 0x4343 -#define mmDCP3_OVL_PWL_1C0TO1FF__SI 0x4344 -#define mmDCP3_OVL_PWL_200TO23F__SI 0x4345 -#define mmDCP3_OVL_PWL_20TO3F__SI 0x433D -#define mmDCP3_OVL_PWL_240TO27F__SI 0x4346 -#define mmDCP3_OVL_PWL_280TO2BF__SI 0x4347 -#define mmDCP3_OVL_PWL_2C0TO2FF__SI 0x4348 -#define mmDCP3_OVL_PWL_300TO33F__SI 0x4349 -#define mmDCP3_OVL_PWL_340TO37F__SI 0x434A -#define mmDCP3_OVL_PWL_380TO3BF__SI 0x434B -#define mmDCP3_OVL_PWL_3C0TO3FF__SI 0x434C -#define mmDCP3_OVL_PWL_40TO7F__SI 0x433E -#define mmDCP3_OVL_PWL_80TOBF__SI 0x433F -#define mmDCP3_OVL_PWL_C0TOFF__SI 0x4340 -#define mmDCP3_OVL_PWL_TRANSFORM_EN__SI 0x433A -#define mmDCP3_OVL_START__SI 0x4325 -#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI 0x432B -#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH__SI 0x4322 -#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE__SI 0x4328 -#define mmDCP3_OVL_SURFACE_ADDRESS__SI 0x4320 -#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH__VI 0x4022 -#define mmDCP3_OVL_SURFACE_ADDRESS__VI 0x4020 -#define mmDCP3_OVL_SURFACE_OFFSET_X__SI 0x4323 -#define mmDCP3_OVL_SURFACE_OFFSET_Y__SI 0x4324 -#define mmDCP3_OVL_SWAP_CNTL__SI 0x431F -#define mmDCP3_OVL_UPDATE__SI 0x4327 -#define mmDCP4_COLOR_MATRIX_COEF_1_1__SI 0x465A -#define mmDCP4_COLOR_MATRIX_COEF_1_2__SI 0x465B -#define mmDCP4_COLOR_MATRIX_COEF_1_3__SI 0x465C -#define mmDCP4_COLOR_MATRIX_COEF_1_4__SI 0x465D -#define mmDCP4_COLOR_MATRIX_COEF_2_1__SI 0x465E -#define mmDCP4_COLOR_MATRIX_COEF_2_2__SI 0x465F -#define mmDCP4_COLOR_MATRIX_COEF_2_3__SI 0x4660 -#define mmDCP4_COLOR_MATRIX_COEF_2_4__SI 0x4661 -#define mmDCP4_COLOR_MATRIX_COEF_3_1__SI 0x4662 -#define mmDCP4_COLOR_MATRIX_COEF_3_2__SI 0x4663 -#define mmDCP4_COLOR_MATRIX_COEF_3_3__SI 0x4664 -#define mmDCP4_COLOR_MATRIX_COEF_3_4__SI 0x4665 -#define mmDCP4_COLOR_SPACE_CONVERT__SI 0x460F -#define mmDCP4_CUR_COLOR1__SI 0x466C -#define mmDCP4_CUR_COLOR2__SI 0x466D -#define mmDCP4_CUR_CONTROL__SI 0x4666 -#define mmDCP4_CUR_HOT_SPOT__SI 0x466B -#define mmDCP4_CUR_POSITION__SI 0x466A -#define mmDCP4_CUR_SIZE__SI 0x4668 -#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH__SI 0x4669 -#define mmDCP4_CUR_SURFACE_ADDRESS__SI 0x4667 -#define mmDCP4_CUR_UPDATE__SI 0x466E -#define mmDCP4_DCP_CONTROL__SI 0x468E -#define mmDCP4_DCP_CRC_CONTROL__SI 0x4687 -#define mmDCP4_DCP_CRC_CURRENT__SI 0x4689 -#define mmDCP4_DCP_CRC_LAST__SI 0x468B -#define mmDCP4_DCP_CRC_MASK__SI 0x4688 -#define mmDCP4_DCP_DEBUG__SI 0x468D -#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI 0x4691 -#define mmDCP4_DCP_MULTI_CHIP_CNTL__SI 0x4690 -#define mmDCP4_DCP_TEST_DEBUG_DATA__SI 0x4696 -#define mmDCP4_DCP_TEST_DEBUG_INDEX__SI 0x4695 -#define mmDCP4_DCP_TILING_CONFIG__SI 0x468F -#define mmDCP4_DC_LUT_30_COLOR__SI 0x467C -#define mmDCP4_DC_LUT_AUTOFILL__SI 0x467F -#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE__SI 0x4681 -#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN__SI 0x4682 -#define mmDCP4_DC_LUT_BLACK_OFFSET_RED__SI 0x4683 -#define mmDCP4_DC_LUT_CONTROL__SI 0x4680 -#define mmDCP4_DC_LUT_PWL_DATA__SI 0x467B -#define mmDCP4_DC_LUT_RW_INDEX__SI 0x4679 -#define mmDCP4_DC_LUT_RW_MODE__SI 0x4678 -#define mmDCP4_DC_LUT_SEQ_COLOR__SI 0x467A -#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE__SI 0x4684 -#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN__SI 0x4685 -#define mmDCP4_DC_LUT_WHITE_OFFSET_RED__SI 0x4686 -#define mmDCP4_DC_LUT_WRITE_EN_MASK__SI 0x467E -#define mmDCP4_GRPH_ALPHA__SI 0x464E -#define mmDCP4_GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4659 -#define mmDCP4_GRPH_COMPRESS_PITCH__SI 0x461A -#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI 0x461B -#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS__SI 0x4619 -#define mmDCP4_GRPH_CONTROL__SI 0x4601 -#define mmDCP4_GRPH_CONTROL__VI 0x4201 -#define mmDCP4_GRPH_DFQ_CONTROL__SI 0x4614 -#define mmDCP4_GRPH_DFQ_STATUS__SI 0x4615 -#define mmDCP4_GRPH_ENABLE__SI 0x4600 -#define mmDCP4_GRPH_FLIP_CONTROL__SI 0x4612 -#define mmDCP4_GRPH_FLIP_CONTROL__VI 0x4212 -#define mmDCP4_GRPH_INTERRUPT_CONTROL__SI 0x4617 -#define mmDCP4_GRPH_INTERRUPT_STATUS__SI 0x4616 -#define mmDCP4_GRPH_KEY_RANGE_ALPHA__SI 0x4654 -#define mmDCP4_GRPH_KEY_RANGE_BLUE__SI 0x4653 -#define mmDCP4_GRPH_KEY_RANGE_GREEN__SI 0x4652 -#define mmDCP4_GRPH_KEY_RANGE_RED__SI 0x4651 -#define mmDCP4_GRPH_LUT_10BIT_BYPASS__SI 0x4602 -#define mmDCP4_GRPH_PITCH__SI 0x4606 -#define mmDCP4_GRPH_PITCH__VI 0x4206 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI 0x4607 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS__SI 0x4604 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI 0x4207 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS__VI 0x4204 -#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI 0x4608 -#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS__SI 0x4605 -#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI 0x4618 -#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE__SI 0x4613 -#define mmDCP4_GRPH_SURFACE_OFFSET_X__SI 0x4609 -#define mmDCP4_GRPH_SURFACE_OFFSET_Y__SI 0x460A -#define mmDCP4_GRPH_SWAP_CNTL__SI 0x4603 -#define mmDCP4_GRPH_UPDATE__SI 0x4611 -#define mmDCP4_GRPH_UPDATE__VI 0x4211 -#define mmDCP4_GRPH_X_END__SI 0x460D -#define mmDCP4_GRPH_X_START__SI 0x460B -#define mmDCP4_GRPH_Y_END__SI 0x460E -#define mmDCP4_GRPH_Y_START__SI 0x460C -#define mmDCP4_ICON_COLOR1__SI 0x4674 -#define mmDCP4_ICON_COLOR2__SI 0x4675 -#define mmDCP4_ICON_CONTROL__SI 0x466F -#define mmDCP4_ICON_SIZE__SI 0x4671 -#define mmDCP4_ICON_START_POSITION__SI 0x4673 -#define mmDCP4_ICON_SURFACE_ADDRESS_HIGH__SI 0x4672 -#define mmDCP4_ICON_SURFACE_ADDRESS__SI 0x4670 -#define mmDCP4_ICON_UPDATE__SI 0x4676 -#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL__SI 0x462C -#define mmDCP4_OVL_ALPHA_CONTROL__SI 0x4650 -#define mmDCP4_OVL_ALPHA__SI 0x464F -#define mmDCP4_OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4610 -#define mmDCP4_OVL_CONTROL1__SI 0x461D -#define mmDCP4_OVL_CONTROL2__SI 0x461E -#define mmDCP4_OVL_DFQ_CONTROL__SI 0x4629 -#define mmDCP4_OVL_DFQ_STATUS__SI 0x462A -#define mmDCP4_OVL_ENABLE__SI 0x461C -#define mmDCP4_OVL_END__SI 0x4626 -#define mmDCP4_OVL_KEY_ALPHA__SI 0x4658 -#define mmDCP4_OVL_KEY_CONTROL__SI 0x464D -#define mmDCP4_OVL_KEY_RANGE_BLUE_CB__SI 0x4657 -#define mmDCP4_OVL_KEY_RANGE_GREEN_Y__SI 0x4656 -#define mmDCP4_OVL_KEY_RANGE_RED_CR__SI 0x4655 -#define mmDCP4_OVL_MATRIX_COEF_1_1__SI 0x462E -#define mmDCP4_OVL_MATRIX_COEF_1_2__SI 0x462F -#define mmDCP4_OVL_MATRIX_COEF_1_3__SI 0x4630 -#define mmDCP4_OVL_MATRIX_COEF_1_4__SI 0x4631 -#define mmDCP4_OVL_MATRIX_COEF_2_1__SI 0x4632 -#define mmDCP4_OVL_MATRIX_COEF_2_2__SI 0x4633 -#define mmDCP4_OVL_MATRIX_COEF_2_3__SI 0x4634 -#define mmDCP4_OVL_MATRIX_COEF_2_4__SI 0x4635 -#define mmDCP4_OVL_MATRIX_COEF_3_1__SI 0x4636 -#define mmDCP4_OVL_MATRIX_COEF_3_2__SI 0x4637 -#define mmDCP4_OVL_MATRIX_COEF_3_3__SI 0x4638 -#define mmDCP4_OVL_MATRIX_COEF_3_4__SI 0x4639 -#define mmDCP4_OVL_MATRIX_TRANSFORM_EN__SI 0x462D -#define mmDCP4_OVL_PITCH__SI 0x4621 -#define mmDCP4_OVL_PWL_0TOF__SI 0x463B -#define mmDCP4_OVL_PWL_100TO13F__SI 0x4641 -#define mmDCP4_OVL_PWL_10TO1F__SI 0x463C -#define mmDCP4_OVL_PWL_140TO17F__SI 0x4642 -#define mmDCP4_OVL_PWL_180TO1BF__SI 0x4643 -#define mmDCP4_OVL_PWL_1C0TO1FF__SI 0x4644 -#define mmDCP4_OVL_PWL_200TO23F__SI 0x4645 -#define mmDCP4_OVL_PWL_20TO3F__SI 0x463D -#define mmDCP4_OVL_PWL_240TO27F__SI 0x4646 -#define mmDCP4_OVL_PWL_280TO2BF__SI 0x4647 -#define mmDCP4_OVL_PWL_2C0TO2FF__SI 0x4648 -#define mmDCP4_OVL_PWL_300TO33F__SI 0x4649 -#define mmDCP4_OVL_PWL_340TO37F__SI 0x464A -#define mmDCP4_OVL_PWL_380TO3BF__SI 0x464B -#define mmDCP4_OVL_PWL_3C0TO3FF__SI 0x464C -#define mmDCP4_OVL_PWL_40TO7F__SI 0x463E -#define mmDCP4_OVL_PWL_80TOBF__SI 0x463F -#define mmDCP4_OVL_PWL_C0TOFF__SI 0x4640 -#define mmDCP4_OVL_PWL_TRANSFORM_EN__SI 0x463A -#define mmDCP4_OVL_START__SI 0x4625 -#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI 0x462B -#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH__SI 0x4622 -#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE__SI 0x4628 -#define mmDCP4_OVL_SURFACE_ADDRESS__SI 0x4620 -#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH__VI 0x4222 -#define mmDCP4_OVL_SURFACE_ADDRESS__VI 0x4220 -#define mmDCP4_OVL_SURFACE_OFFSET_X__SI 0x4623 -#define mmDCP4_OVL_SURFACE_OFFSET_Y__SI 0x4624 -#define mmDCP4_OVL_SWAP_CNTL__SI 0x461F -#define mmDCP4_OVL_UPDATE__SI 0x4627 -#define mmDCP5_COLOR_MATRIX_COEF_1_1__SI 0x495A -#define mmDCP5_COLOR_MATRIX_COEF_1_2__SI 0x495B -#define mmDCP5_COLOR_MATRIX_COEF_1_3__SI 0x495C -#define mmDCP5_COLOR_MATRIX_COEF_1_4__SI 0x495D -#define mmDCP5_COLOR_MATRIX_COEF_2_1__SI 0x495E -#define mmDCP5_COLOR_MATRIX_COEF_2_2__SI 0x495F -#define mmDCP5_COLOR_MATRIX_COEF_2_3__SI 0x4960 -#define mmDCP5_COLOR_MATRIX_COEF_2_4__SI 0x4961 -#define mmDCP5_COLOR_MATRIX_COEF_3_1__SI 0x4962 -#define mmDCP5_COLOR_MATRIX_COEF_3_2__SI 0x4963 -#define mmDCP5_COLOR_MATRIX_COEF_3_3__SI 0x4964 -#define mmDCP5_COLOR_MATRIX_COEF_3_4__SI 0x4965 -#define mmDCP5_COLOR_SPACE_CONVERT__SI 0x490F -#define mmDCP5_CUR_COLOR1__SI 0x496C -#define mmDCP5_CUR_COLOR2__SI 0x496D -#define mmDCP5_CUR_CONTROL__SI 0x4966 -#define mmDCP5_CUR_HOT_SPOT__SI 0x496B -#define mmDCP5_CUR_POSITION__SI 0x496A -#define mmDCP5_CUR_SIZE__SI 0x4968 -#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH__SI 0x4969 -#define mmDCP5_CUR_SURFACE_ADDRESS__SI 0x4967 -#define mmDCP5_CUR_UPDATE__SI 0x496E -#define mmDCP5_DCP_CONTROL__SI 0x498E -#define mmDCP5_DCP_CRC_CONTROL__SI 0x4987 -#define mmDCP5_DCP_CRC_CURRENT__SI 0x4989 -#define mmDCP5_DCP_CRC_LAST__SI 0x498B -#define mmDCP5_DCP_CRC_MASK__SI 0x4988 -#define mmDCP5_DCP_DEBUG__SI 0x498D -#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI 0x4991 -#define mmDCP5_DCP_MULTI_CHIP_CNTL__SI 0x4990 -#define mmDCP5_DCP_TEST_DEBUG_DATA__SI 0x4996 -#define mmDCP5_DCP_TEST_DEBUG_INDEX__SI 0x4995 -#define mmDCP5_DCP_TILING_CONFIG__SI 0x498F -#define mmDCP5_DC_LUT_30_COLOR__SI 0x497C -#define mmDCP5_DC_LUT_AUTOFILL__SI 0x497F -#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE__SI 0x4981 -#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN__SI 0x4982 -#define mmDCP5_DC_LUT_BLACK_OFFSET_RED__SI 0x4983 -#define mmDCP5_DC_LUT_CONTROL__SI 0x4980 -#define mmDCP5_DC_LUT_PWL_DATA__SI 0x497B -#define mmDCP5_DC_LUT_RW_INDEX__SI 0x4979 -#define mmDCP5_DC_LUT_RW_MODE__SI 0x4978 -#define mmDCP5_DC_LUT_SEQ_COLOR__SI 0x497A -#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE__SI 0x4984 -#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN__SI 0x4985 -#define mmDCP5_DC_LUT_WHITE_OFFSET_RED__SI 0x4986 -#define mmDCP5_DC_LUT_WRITE_EN_MASK__SI 0x497E -#define mmDCP5_GRPH_ALPHA__SI 0x494E -#define mmDCP5_GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4959 -#define mmDCP5_GRPH_COMPRESS_PITCH__SI 0x491A -#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI 0x491B -#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS__SI 0x4919 -#define mmDCP5_GRPH_CONTROL__SI 0x4901 -#define mmDCP5_GRPH_CONTROL__VI 0x4401 -#define mmDCP5_GRPH_DFQ_CONTROL__SI 0x4914 -#define mmDCP5_GRPH_DFQ_STATUS__SI 0x4915 -#define mmDCP5_GRPH_ENABLE__SI 0x4900 -#define mmDCP5_GRPH_FLIP_CONTROL__SI 0x4912 -#define mmDCP5_GRPH_FLIP_CONTROL__VI 0x4412 -#define mmDCP5_GRPH_INTERRUPT_CONTROL__SI 0x4917 -#define mmDCP5_GRPH_INTERRUPT_STATUS__SI 0x4916 -#define mmDCP5_GRPH_KEY_RANGE_ALPHA__SI 0x4954 -#define mmDCP5_GRPH_KEY_RANGE_BLUE__SI 0x4953 -#define mmDCP5_GRPH_KEY_RANGE_GREEN__SI 0x4952 -#define mmDCP5_GRPH_KEY_RANGE_RED__SI 0x4951 -#define mmDCP5_GRPH_LUT_10BIT_BYPASS__SI 0x4902 -#define mmDCP5_GRPH_PITCH__SI 0x4906 -#define mmDCP5_GRPH_PITCH__VI 0x4406 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI 0x4907 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS__SI 0x4904 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI 0x4407 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS__VI 0x4404 -#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI 0x4908 -#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS__SI 0x4905 -#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI 0x4918 -#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE__SI 0x4913 -#define mmDCP5_GRPH_SURFACE_OFFSET_X__SI 0x4909 -#define mmDCP5_GRPH_SURFACE_OFFSET_Y__SI 0x490A -#define mmDCP5_GRPH_SWAP_CNTL__SI 0x4903 -#define mmDCP5_GRPH_UPDATE__SI 0x4911 -#define mmDCP5_GRPH_UPDATE__VI 0x4411 -#define mmDCP5_GRPH_X_END__SI 0x490D -#define mmDCP5_GRPH_X_START__SI 0x490B -#define mmDCP5_GRPH_Y_END__SI 0x490E -#define mmDCP5_GRPH_Y_START__SI 0x490C -#define mmDCP5_ICON_COLOR1__SI 0x4974 -#define mmDCP5_ICON_COLOR2__SI 0x4975 -#define mmDCP5_ICON_CONTROL__SI 0x496F -#define mmDCP5_ICON_SIZE__SI 0x4971 -#define mmDCP5_ICON_START_POSITION__SI 0x4973 -#define mmDCP5_ICON_SURFACE_ADDRESS_HIGH__SI 0x4972 -#define mmDCP5_ICON_SURFACE_ADDRESS__SI 0x4970 -#define mmDCP5_ICON_UPDATE__SI 0x4976 -#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL__SI 0x492C -#define mmDCP5_OVL_ALPHA_CONTROL__SI 0x4950 -#define mmDCP5_OVL_ALPHA__SI 0x494F -#define mmDCP5_OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x4910 -#define mmDCP5_OVL_CONTROL1__SI 0x491D -#define mmDCP5_OVL_CONTROL2__SI 0x491E -#define mmDCP5_OVL_DFQ_CONTROL__SI 0x4929 -#define mmDCP5_OVL_DFQ_STATUS__SI 0x492A -#define mmDCP5_OVL_ENABLE__SI 0x491C -#define mmDCP5_OVL_END__SI 0x4926 -#define mmDCP5_OVL_KEY_ALPHA__SI 0x4958 -#define mmDCP5_OVL_KEY_CONTROL__SI 0x494D -#define mmDCP5_OVL_KEY_RANGE_BLUE_CB__SI 0x4957 -#define mmDCP5_OVL_KEY_RANGE_GREEN_Y__SI 0x4956 -#define mmDCP5_OVL_KEY_RANGE_RED_CR__SI 0x4955 -#define mmDCP5_OVL_MATRIX_COEF_1_1__SI 0x492E -#define mmDCP5_OVL_MATRIX_COEF_1_2__SI 0x492F -#define mmDCP5_OVL_MATRIX_COEF_1_3__SI 0x4930 -#define mmDCP5_OVL_MATRIX_COEF_1_4__SI 0x4931 -#define mmDCP5_OVL_MATRIX_COEF_2_1__SI 0x4932 -#define mmDCP5_OVL_MATRIX_COEF_2_2__SI 0x4933 -#define mmDCP5_OVL_MATRIX_COEF_2_3__SI 0x4934 -#define mmDCP5_OVL_MATRIX_COEF_2_4__SI 0x4935 -#define mmDCP5_OVL_MATRIX_COEF_3_1__SI 0x4936 -#define mmDCP5_OVL_MATRIX_COEF_3_2__SI 0x4937 -#define mmDCP5_OVL_MATRIX_COEF_3_3__SI 0x4938 -#define mmDCP5_OVL_MATRIX_COEF_3_4__SI 0x4939 -#define mmDCP5_OVL_MATRIX_TRANSFORM_EN__SI 0x492D -#define mmDCP5_OVL_PITCH__SI 0x4921 -#define mmDCP5_OVL_PWL_0TOF__SI 0x493B -#define mmDCP5_OVL_PWL_100TO13F__SI 0x4941 -#define mmDCP5_OVL_PWL_10TO1F__SI 0x493C -#define mmDCP5_OVL_PWL_140TO17F__SI 0x4942 -#define mmDCP5_OVL_PWL_180TO1BF__SI 0x4943 -#define mmDCP5_OVL_PWL_1C0TO1FF__SI 0x4944 -#define mmDCP5_OVL_PWL_200TO23F__SI 0x4945 -#define mmDCP5_OVL_PWL_20TO3F__SI 0x493D -#define mmDCP5_OVL_PWL_240TO27F__SI 0x4946 -#define mmDCP5_OVL_PWL_280TO2BF__SI 0x4947 -#define mmDCP5_OVL_PWL_2C0TO2FF__SI 0x4948 -#define mmDCP5_OVL_PWL_300TO33F__SI 0x4949 -#define mmDCP5_OVL_PWL_340TO37F__SI 0x494A -#define mmDCP5_OVL_PWL_380TO3BF__SI 0x494B -#define mmDCP5_OVL_PWL_3C0TO3FF__SI 0x494C -#define mmDCP5_OVL_PWL_40TO7F__SI 0x493E -#define mmDCP5_OVL_PWL_80TOBF__SI 0x493F -#define mmDCP5_OVL_PWL_C0TOFF__SI 0x4940 -#define mmDCP5_OVL_PWL_TRANSFORM_EN__SI 0x493A -#define mmDCP5_OVL_START__SI 0x4925 -#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI 0x492B -#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH__SI 0x4922 -#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE__SI 0x4928 -#define mmDCP5_OVL_SURFACE_ADDRESS__SI 0x4920 -#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH__VI 0x4422 -#define mmDCP5_OVL_SURFACE_ADDRESS__VI 0x4420 -#define mmDCP5_OVL_SURFACE_OFFSET_X__SI 0x4923 -#define mmDCP5_OVL_SURFACE_OFFSET_Y__SI 0x4924 -#define mmDCP5_OVL_SWAP_CNTL__SI 0x491F -#define mmDCP5_OVL_UPDATE__SI 0x4927 -#define mmDCPLL_CNTL__SI 0x016A -#define mmDCPLL_DEBUG_CLK_SEL__SI 0x016D -#define mmDCPLL_DISPCLK_DTO_CNTL__SI 0x016C -#define mmDCPLL_FB_DIV__SI 0x0164 -#define mmDCPLL_PLL_CNTL__SI 0x0168 -#define mmDCPLL_POST_DIV_SRC__SI 0x0165 -#define mmDCPLL_POST_DIV__SI 0x0167 -#define mmDCPLL_REF_DIV_SRC__SI 0x0160 -#define mmDCPLL_REF_DIV__SI 0x0161 -#define mmDCPLL_UNLOCK_DETECT_CNTL__SI 0x0169 -#define mmDCPLL_UPDATE_CNTL__SI 0x0163 -#define mmDCPLL_UPDATE_LOCK__SI 0x0162 -#define mmDCPLL_VREG_CNTL__SI 0x016B -#define mmDCP_CONTROL__SI 0x1A8E -#define mmDCP_CRC_CONTROL__SI 0x1A87 -#define mmDCP_CRC_CURRENT__SI 0x1A89 -#define mmDCP_CRC_LAST__SI 0x1A8B -#define mmDCP_CRC_MASK__SI 0x1A88 -#define mmDCP_DEBUG__SI 0x1A8D -#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK__SI 0x1A91 -#define mmDCP_MULTI_CHIP_CNTL__SI 0x1A90 -#define mmDCP_RBBMIF_RDWR_TIMEOUT__SI 0x031D -#define mmDCP_TEST_DEBUG_DATA__SI 0x1A96 -#define mmDCP_TEST_DEBUG_INDEX__SI 0x1A95 -#define mmDCP_TILING_CONFIG__SI 0x1A8F -#define mmDC_ABM1_ACE_CNTL_MISC__SI 0x1641 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_0__SI 0x163A -#define mmDC_ABM1_ACE_OFFSET_SLOPE_1__SI 0x163B -#define mmDC_ABM1_ACE_OFFSET_SLOPE_2__SI 0x163C -#define mmDC_ABM1_ACE_OFFSET_SLOPE_3__SI 0x163D -#define mmDC_ABM1_ACE_OFFSET_SLOPE_4__SI 0x163E -#define mmDC_ABM1_ACE_THRES_12__SI 0x163F -#define mmDC_ABM1_ACE_THRES_34__SI 0x1640 -#define mmDC_ABM1_BL_MASTER_LOCK__SI 0x169C -#define mmDC_ABM1_CNTL__SI 0x1638 -#define mmDC_ABM1_DEBUG_MISC__SI 0x1649 -#define mmDC_ABM1_HGLS_REG_READ_PROGRESS__SI 0x164A -#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI 0x1659 -#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI 0x1656 -#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI 0x1657 -#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI 0x165A -#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI 0x1658 -#define mmDC_ABM1_HG_MISC_CTRL__SI 0x164B -#define mmDC_ABM1_HG_RESULT_10__SI 0x1664 -#define mmDC_ABM1_HG_RESULT_11__SI 0x1665 -#define mmDC_ABM1_HG_RESULT_12__SI 0x1666 -#define mmDC_ABM1_HG_RESULT_13__SI 0x1667 -#define mmDC_ABM1_HG_RESULT_14__SI 0x1668 -#define mmDC_ABM1_HG_RESULT_15__SI 0x1669 -#define mmDC_ABM1_HG_RESULT_16__SI 0x166A -#define mmDC_ABM1_HG_RESULT_17__SI 0x166B -#define mmDC_ABM1_HG_RESULT_18__SI 0x166C -#define mmDC_ABM1_HG_RESULT_19__SI 0x166D -#define mmDC_ABM1_HG_RESULT_1__SI 0x165B -#define mmDC_ABM1_HG_RESULT_20__SI 0x166E -#define mmDC_ABM1_HG_RESULT_21__SI 0x166F -#define mmDC_ABM1_HG_RESULT_22__SI 0x1670 -#define mmDC_ABM1_HG_RESULT_23__SI 0x1671 -#define mmDC_ABM1_HG_RESULT_24__SI 0x1672 -#define mmDC_ABM1_HG_RESULT_2__SI 0x165C -#define mmDC_ABM1_HG_RESULT_3__SI 0x165D -#define mmDC_ABM1_HG_RESULT_4__SI 0x165E -#define mmDC_ABM1_HG_RESULT_5__SI 0x165F -#define mmDC_ABM1_HG_RESULT_6__SI 0x1660 -#define mmDC_ABM1_HG_RESULT_7__SI 0x1661 -#define mmDC_ABM1_HG_RESULT_8__SI 0x1662 -#define mmDC_ABM1_HG_RESULT_9__SI 0x1663 -#define mmDC_ABM1_HG_SAMPLE_RATE__SI 0x1654 -#define mmDC_ABM1_IPCSC_COEFF_SEL__SI 0x1639 -#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI 0x164E -#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI 0x1653 -#define mmDC_ABM1_LS_MIN_MAX_LUMA__SI 0x164D -#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI 0x1651 -#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI 0x1652 -#define mmDC_ABM1_LS_OVR_SCAN_BIN__SI 0x1650 -#define mmDC_ABM1_LS_PIXEL_COUNT__SI 0x164F -#define mmDC_ABM1_LS_SAMPLE_RATE__SI 0x1655 -#define mmDC_ABM1_LS_SUM_OF_LUMA__SI 0x164C -#define mmDC_DISPCLK_PERFCOUNTER0_HI__SI 0x1877 -#define mmDC_DISPCLK_PERFCOUNTER0_LOW__SI 0x1878 -#define mmDC_DISPCLK_PERFCOUNTER0_SELECT__SI 0x1876 -#define mmDC_DISPCLK_PERFCOUNTER1_HI__SI 0x187A -#define mmDC_DISPCLK_PERFCOUNTER1_LOW__SI 0x187B -#define mmDC_DISPCLK_PERFCOUNTER1_SELECT__SI 0x1879 -#define mmDC_DMCU_SCRATCH__SI 0x1618 -#define mmDC_DOUT_DEBUG_MUX_CNTL__SI 0x1843 -#define mmDC_FID_CNT__SI 0x1ACF -#define mmDC_GENERICA__SI 0x1900 -#define mmDC_GENERICB__SI 0x1901 -#define mmDC_GPIO_DDC1_A__SI 0x190D -#define mmDC_GPIO_DDC1_EN__SI 0x190E -#define mmDC_GPIO_DDC1_MASK__SI 0x190C -#define mmDC_GPIO_DDC1_Y__SI 0x190F -#define mmDC_GPIO_DDC2_A__SI 0x1911 -#define mmDC_GPIO_DDC2_EN__SI 0x1912 -#define mmDC_GPIO_DDC2_MASK__SI 0x1910 -#define mmDC_GPIO_DDC2_Y__SI 0x1913 -#define mmDC_GPIO_DDC3_A__SI 0x1915 -#define mmDC_GPIO_DDC3_EN__SI 0x1916 -#define mmDC_GPIO_DDC3_MASK__SI 0x1914 -#define mmDC_GPIO_DDC3_Y__SI 0x1917 -#define mmDC_GPIO_DDC4_A__SI 0x1919 -#define mmDC_GPIO_DDC4_EN__SI 0x191A -#define mmDC_GPIO_DDC4_MASK__SI 0x1918 -#define mmDC_GPIO_DDC4_Y__SI 0x191B -#define mmDC_GPIO_DDC5_A__SI 0x191D -#define mmDC_GPIO_DDC5_EN__SI 0x191E -#define mmDC_GPIO_DDC5_MASK__SI 0x191C -#define mmDC_GPIO_DDC5_Y__SI 0x191F -#define mmDC_GPIO_DDC6_A__SI 0x1921 -#define mmDC_GPIO_DDC6_EN__SI 0x1922 -#define mmDC_GPIO_DDC6_MASK__SI 0x1920 -#define mmDC_GPIO_DDC6_Y__SI 0x1923 -#define mmDC_GPIO_DEBUG__SI 0x1946 -#define mmDC_GPIO_DVODATA_A__SI 0x1909 -#define mmDC_GPIO_DVODATA_EN__SI 0x190A -#define mmDC_GPIO_DVODATA_MASK__SI 0x1908 -#define mmDC_GPIO_DVODATA_Y__SI 0x190B -#define mmDC_GPIO_GENERIC_A__SI 0x1905 -#define mmDC_GPIO_GENERIC_EN__SI 0x1906 -#define mmDC_GPIO_GENERIC_MASK__SI 0x1904 -#define mmDC_GPIO_GENERIC_Y__SI 0x1907 -#define mmDC_GPIO_HPD_A__SI 0x192D -#define mmDC_GPIO_HPD_EN__SI 0x192E -#define mmDC_GPIO_HPD_MASK__SI 0x192C -#define mmDC_GPIO_HPD_Y__SI 0x192F -#define mmDC_GPIO_PAD_STRENGTH_1__SI 0x1944 -#define mmDC_GPIO_PAD_STRENGTH_2__SI 0x1945 -#define mmDC_GPIO_PWRSEQ_A__SI 0x1941 -#define mmDC_GPIO_PWRSEQ_EN__SI 0x1942 -#define mmDC_GPIO_PWRSEQ_MASK__SI 0x1940 -#define mmDC_GPIO_PWRSEQ_Y__SI 0x1943 -#define mmDC_GPIO_SYNCA_A__SI 0x1925 -#define mmDC_GPIO_SYNCA_EN__SI 0x1926 -#define mmDC_GPIO_SYNCA_MASK__SI 0x1924 -#define mmDC_GPIO_SYNCA_Y__SI 0x1927 -#define mmDC_GPIO_SYNCB_A__SI 0x1929 -#define mmDC_GPIO_SYNCB_EN__SI 0x192A -#define mmDC_GPIO_SYNCB_MASK__SI 0x1928 -#define mmDC_GPIO_SYNCB_Y__SI 0x192B -#define mmDC_GPU_TIMER_READ_CNTL__SI 0x1972 -#define mmDC_GPU_TIMER_READ__SI 0x1971 -#define mmDC_GPU_TIMER_START_POSITION__SI 0x1970 -#define mmDC_HPD1_CONTROL__SI 0x1809 -#define mmDC_HPD1_INT_CONTROL__SI 0x1808 -#define mmDC_HPD1_INT_STATUS__SI 0x1807 -#define mmDC_HPD2_CONTROL__SI 0x180C -#define mmDC_HPD2_INT_CONTROL__SI 0x180B -#define mmDC_HPD2_INT_STATUS__SI 0x180A -#define mmDC_HPD3_CONTROL__SI 0x180F -#define mmDC_HPD3_INT_CONTROL__SI 0x180E -#define mmDC_HPD3_INT_STATUS__SI 0x180D -#define mmDC_HPD4_CONTROL__SI 0x1812 -#define mmDC_HPD4_INT_CONTROL__SI 0x1811 -#define mmDC_HPD4_INT_STATUS__SI 0x1810 -#define mmDC_HPD5_CONTROL__SI 0x1815 -#define mmDC_HPD5_INT_CONTROL__SI 0x1814 -#define mmDC_HPD5_INT_STATUS__SI 0x1813 -#define mmDC_HPD6_CONTROL__SI 0x1818 -#define mmDC_HPD6_INT_CONTROL__SI 0x1817 -#define mmDC_HPD6_INT_STATUS__SI 0x1816 -#define mmDC_I2C_ARBITRATION__SI 0x181A -#define mmDC_I2C_CONTROL__SI 0x1819 -#define mmDC_I2C_DATA__SI 0x1833 -#define mmDC_I2C_DDC1_HW_STATUS__SI 0x181D -#define mmDC_I2C_DDC1_SETUP__SI 0x1824 -#define mmDC_I2C_DDC1_SPEED__SI 0x1823 -#define mmDC_I2C_DDC2_HW_STATUS__SI 0x181E -#define mmDC_I2C_DDC2_SETUP__SI 0x1826 -#define mmDC_I2C_DDC2_SPEED__SI 0x1825 -#define mmDC_I2C_DDC3_HW_STATUS__SI 0x181F -#define mmDC_I2C_DDC3_SETUP__SI 0x1828 -#define mmDC_I2C_DDC3_SPEED__SI 0x1827 -#define mmDC_I2C_DDC4_HW_STATUS__SI 0x1820 -#define mmDC_I2C_DDC4_SETUP__SI 0x182A -#define mmDC_I2C_DDC4_SPEED__SI 0x1829 -#define mmDC_I2C_DDC5_HW_STATUS__SI 0x1821 -#define mmDC_I2C_DDC5_SETUP__SI 0x182C -#define mmDC_I2C_DDC5_SPEED__SI 0x182B -#define mmDC_I2C_DDC6_HW_STATUS__SI 0x1822 -#define mmDC_I2C_DDC6_SETUP__SI 0x182E -#define mmDC_I2C_DDC6_SPEED__SI 0x182D -#define mmDC_I2C_INTERRUPT_CONTROL__SI 0x181B -#define mmDC_I2C_SW_STATUS__SI 0x181C -#define mmDC_I2C_TRANSACTION0__SI 0x182F -#define mmDC_I2C_TRANSACTION1__SI 0x1830 -#define mmDC_I2C_TRANSACTION2__SI 0x1831 -#define mmDC_I2C_TRANSACTION3__SI 0x1832 -#define mmDC_LB_BLACK_KEYER_B__SI 0x1AD3 -#define mmDC_LB_BLACK_KEYER_G__SI 0x1AD2 -#define mmDC_LB_BLACK_KEYER_R__SI 0x1AD1 -#define mmDC_LB_MEMORY_SPLIT__SI 0x1AC3 -#define mmDC_LB_MEM_SIZE__SI 0x1AC4 -#define mmDC_LUT_30_COLOR__SI 0x1A7C -#define mmDC_LUT_AUTOFILL__SI 0x1A7F -#define mmDC_LUT_BLACK_OFFSET_BLUE__SI 0x1A81 -#define mmDC_LUT_BLACK_OFFSET_GREEN__SI 0x1A82 -#define mmDC_LUT_BLACK_OFFSET_RED__SI 0x1A83 -#define mmDC_LUT_CONTROL__SI 0x1A80 -#define mmDC_LUT_PWL_DATA__SI 0x1A7B -#define mmDC_LUT_RW_INDEX__SI 0x1A79 -#define mmDC_LUT_RW_MODE__SI 0x1A78 -#define mmDC_LUT_SEQ_COLOR__SI 0x1A7A -#define mmDC_LUT_WHITE_OFFSET_BLUE__SI 0x1A84 -#define mmDC_LUT_WHITE_OFFSET_GREEN__SI 0x1A85 -#define mmDC_LUT_WHITE_OFFSET_RED__SI 0x1A86 -#define mmDC_LUT_WRITE_EN_MASK__SI 0x1A7E -#define mmDC_MVP_LB_CONTROL__SI 0x1ADB -#define mmDC_PAD_EXTERN_SIG__SI 0x1902 -#define mmDC_PERFMON_CNTL__SI 0x187C -#define mmDC_PINSTRAPS__SI 0x1954 -#define mmDC_REF_CLK_CNTL__SI 0x1903 -#define mmDC_SCLK_PERFCOUNTER0_HI__SI 0x1871 -#define mmDC_SCLK_PERFCOUNTER0_LOW__SI 0x1872 -#define mmDC_SCLK_PERFCOUNTER0_SELECT__SI 0x1870 -#define mmDC_SCLK_PERFCOUNTER1_HI__SI 0x1874 -#define mmDC_SCLK_PERFCOUNTER1_LOW__SI 0x1875 -#define mmDC_SCLK_PERFCOUNTER1_SELECT__SI 0x1873 -#define mmDC_STUTTER_CNTL__SI 0x1ACC -#define mmDC_STUTTER_STATUS__SI 0x1AF3 -#define mmDC_TEST_DEBUG_DATA__SI 0x186D -#define mmDC_TEST_DEBUG_INDEX__SI 0x186C -#define mmDC_TEST_DEBUG_VIP_CNTL__SI 0x02BB -#define mmDEBUG_DATA 0x203D -#define mmDEBUG_DRM_MASK_0__SI 0x380B -#define mmDEBUG_DRM_MASK_1__SI 0x380C -#define mmDEBUG_DRM_MASK_2__SI 0x380D -#define mmDEBUG_DRM_MASK_3__SI 0x380E -#define mmDEBUG_ENCRYP_COEF_0__SI 0x380F -#define mmDEBUG_ENCRYP_COEF_1__SI 0x3810 -#define mmDEBUG_ENCRYP_COEF_2__SI 0x3811 -#define mmDEBUG_ENCRYP_COEF_3__SI 0x3812 -#define mmDEBUG_INDEX 0x203C -#define mmDENTIST_DISPCLK_CNTL__SI 0x015F -#define mmDESKTOP_HEIGHT__SI 0x1AC1 -#define mmDIDT_IND_DATA__CI__VI 0x3281 -#define mmDIDT_IND_INDEX__CI__VI 0x3280 -#define mmDIG0_AFMT_60958_0__SI 0x1C41 -#define mmDIG0_AFMT_60958_1__SI 0x1C42 -#define mmDIG0_AFMT_60958_2__SI 0x1C48 -#define mmDIG0_AFMT_ACP__SI 0x1C15 -#define mmDIG0_AFMT_AUDIO_CRC_CONTROL__SI 0x1C43 -#define mmDIG0_AFMT_AUDIO_CRC_RESULT__SI 0x1C49 -#define mmDIG0_AFMT_AUDIO_INFO0__SI 0x1C3F -#define mmDIG0_AFMT_AUDIO_INFO1__SI 0x1C40 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2__SI 0x1C17 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL__SI 0x1C4B -#define mmDIG0_AFMT_AVI_INFO0__SI 0x1C21 -#define mmDIG0_AFMT_AVI_INFO1__SI 0x1C22 -#define mmDIG0_AFMT_AVI_INFO2__SI 0x1C23 -#define mmDIG0_AFMT_AVI_INFO3__SI 0x1C24 -#define mmDIG0_AFMT_GENERIC0_0__SI 0x1C28 -#define mmDIG0_AFMT_GENERIC0_1__SI 0x1C29 -#define mmDIG0_AFMT_GENERIC0_2__SI 0x1C2A -#define mmDIG0_AFMT_GENERIC0_3__SI 0x1C2B -#define mmDIG0_AFMT_GENERIC0_4__SI 0x1C2C -#define mmDIG0_AFMT_GENERIC0_5__SI 0x1C2D -#define mmDIG0_AFMT_GENERIC0_6__SI 0x1C2E -#define mmDIG0_AFMT_GENERIC0_7__SI 0x1C4E -#define mmDIG0_AFMT_GENERIC0_HDR__SI 0x1C27 -#define mmDIG0_AFMT_GENERIC1_0__SI 0x1C30 -#define mmDIG0_AFMT_GENERIC1_1__SI 0x1C31 -#define mmDIG0_AFMT_GENERIC1_2__SI 0x1C32 -#define mmDIG0_AFMT_GENERIC1_3__SI 0x1C33 -#define mmDIG0_AFMT_GENERIC1_4__SI 0x1C34 -#define mmDIG0_AFMT_GENERIC1_5__SI 0x1C35 -#define mmDIG0_AFMT_GENERIC1_6__SI 0x1C36 -#define mmDIG0_AFMT_GENERIC1_HDR__SI 0x1C2F -#define mmDIG0_AFMT_INFOFRAME_CONTROL0__SI 0x1C4D -#define mmDIG0_AFMT_INTERRUPT_STATUS__SI 0x1C14 -#define mmDIG0_AFMT_ISRC1_0__SI 0x1C18 -#define mmDIG0_AFMT_ISRC1_1__SI 0x1C19 -#define mmDIG0_AFMT_ISRC1_2__SI 0x1C1A -#define mmDIG0_AFMT_ISRC1_3__SI 0x1C1B -#define mmDIG0_AFMT_ISRC1_4__SI 0x1C1C -#define mmDIG0_AFMT_ISRC2_0__SI 0x1C1D -#define mmDIG0_AFMT_ISRC2_1__SI 0x1C1E -#define mmDIG0_AFMT_ISRC2_2__SI 0x1C1F -#define mmDIG0_AFMT_ISRC2_3__SI 0x1C20 -#define mmDIG0_AFMT_MPEG_INFO0__SI 0x1C25 -#define mmDIG0_AFMT_MPEG_INFO1__SI 0x1C26 -#define mmDIG0_AFMT_RAMP_CONTROL0__SI 0x1C44 -#define mmDIG0_AFMT_RAMP_CONTROL1__SI 0x1C45 -#define mmDIG0_AFMT_RAMP_CONTROL2__SI 0x1C46 -#define mmDIG0_AFMT_RAMP_CONTROL3__SI 0x1C47 -#define mmDIG0_AFMT_STATUS__SI 0x1C4A -#define mmDIG0_AFMT_VBI_PACKET_CONTROL__SI 0x1C4C -#define mmDIG0_DIG_CLOCK_PATTERN__SI 0x1C03 -#define mmDIG0_DIG_CNTL__SI 0x1C00 -#define mmDIG0_DIG_DEBUG__SI 0x1C06 -#define mmDIG0_DIG_OUTPUT_CRC_CNTL__SI 0x1C01 -#define mmDIG0_DIG_OUTPUT_CRC_RESULT__SI 0x1C02 -#define mmDIG0_DIG_RANDOM_PATTERN_SEED__SI 0x1C05 -#define mmDIG0_DIG_TEST_PATTERN__SI 0x1C04 -#define mmDIG0_HDCP_CONTROL__SI 0x1C54 -#define mmDIG0_HDCP_DEBUG_CONTROL__SI 0x1C55 -#define mmDIG0_HDCP_DEBUG__SI 0x1C75 -#define mmDIG0_HDCP_DP_STATUS__SI 0x1C74 -#define mmDIG0_HDCP_I2C_CONTROL_0__SI 0x1C58 -#define mmDIG0_HDCP_I2C_CONTROL_1__SI 0x1C59 -#define mmDIG0_HDCP_I2C_STATUS__SI 0x1C5A -#define mmDIG0_HDCP_INT_CONTROL__SI 0x1C56 -#define mmDIG0_HDCP_LINK0_STATUS__SI 0x1C57 -#define mmDIG0_HDCP_LINK1_STATUS__SI 0x1C5B -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA0__SI 0x1C5D -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA10__SI 0x1C68 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA11__SI 0x1C69 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA12__SI 0x1C6A -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA13__SI 0x1C6B -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA14__SI 0x1C6C -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA15_0__SI 0x1C6D -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA15_1__SI 0x1C6E -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA16__SI 0x1C6F -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA17__SI 0x1C70 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA18__SI 0x1C71 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA19__SI 0x1C72 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA1__SI 0x1C5E -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA20__SI 0x1C73 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA2_0__SI 0x1C5F -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA2_1__SI 0x1C60 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA3__SI 0x1C61 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA4__SI 0x1C62 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA5__SI 0x1C63 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA6__SI 0x1C64 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA7__SI 0x1C65 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA8__SI 0x1C66 -#define mmDIG0_HDCP_RECV_PORT_LOCAL_DATA9__SI 0x1C67 -#define mmDIG0_HDCP_RESET__SI 0x1C5C -#define mmDIG0_HDMI_ACR_32_0__SI 0x1C37 -#define mmDIG0_HDMI_ACR_32_1__SI 0x1C38 -#define mmDIG0_HDMI_ACR_44_0__SI 0x1C39 -#define mmDIG0_HDMI_ACR_44_1__SI 0x1C3A -#define mmDIG0_HDMI_ACR_48_0__SI 0x1C3B -#define mmDIG0_HDMI_ACR_48_1__SI 0x1C3C -#define mmDIG0_HDMI_ACR_PACKET_CONTROL__SI 0x1C0F -#define mmDIG0_HDMI_ACR_STATUS_0__SI 0x1C3D -#define mmDIG0_HDMI_ACR_STATUS_1__SI 0x1C3E -#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL__SI 0x1C0E -#define mmDIG0_HDMI_CONTROL__SI 0x1C0C -#define mmDIG0_HDMI_GC__SI 0x1C16 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL__SI 0x1C13 -#define mmDIG0_HDMI_INFOFRAME_CONTROL0__SI 0x1C11 -#define mmDIG0_HDMI_INFOFRAME_CONTROL1__SI 0x1C12 -#define mmDIG0_HDMI_STATUS__SI 0x1C0D -#define mmDIG0_HDMI_VBI_PACKET_CONTROL__SI 0x1C10 -#define mmDIG0_LVDS_DATA_CNTL__SI 0x1C8C -#define mmDIG0_SDVO_CNTL__SI 0x1C88 -#define mmDIG0_TMDS_CNTL__SI 0x1C7C -#define mmDIG0_TMDS_CONTROL0_FEEDBACK__SI 0x1C7E -#define mmDIG0_TMDS_CONTROL_CHAR__SI 0x1C7D -#define mmDIG0_TMDS_CTL0_1_GEN_CNTL__SI 0x1C86 -#define mmDIG0_TMDS_CTL2_3_GEN_CNTL__SI 0x1C87 -#define mmDIG0_TMDS_CTL_BITS__SI 0x1C83 -#define mmDIG0_TMDS_DCBALANCER_CONTROL__SI 0x1C84 -#define mmDIG0_TMDS_DEBUG__SI 0x1C82 -#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL__SI 0x1C7F -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1__SI 0x1C80 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3__SI 0x1C81 -#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR__SI 0x1C85 -#define mmDIG1_AFMT_60958_0__SI 0x1F41 -#define mmDIG1_AFMT_60958_1__SI 0x1F42 -#define mmDIG1_AFMT_60958_2__SI 0x1F48 -#define mmDIG1_AFMT_ACP__SI 0x1F15 -#define mmDIG1_AFMT_AUDIO_CRC_CONTROL__SI 0x1F43 -#define mmDIG1_AFMT_AUDIO_CRC_RESULT__SI 0x1F49 -#define mmDIG1_AFMT_AUDIO_INFO0__SI 0x1F3F -#define mmDIG1_AFMT_AUDIO_INFO1__SI 0x1F40 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2__SI 0x1F17 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL__SI 0x1F4B -#define mmDIG1_AFMT_AVI_INFO0__SI 0x1F21 -#define mmDIG1_AFMT_AVI_INFO1__SI 0x1F22 -#define mmDIG1_AFMT_AVI_INFO2__SI 0x1F23 -#define mmDIG1_AFMT_AVI_INFO3__SI 0x1F24 -#define mmDIG1_AFMT_GENERIC0_0__SI 0x1F28 -#define mmDIG1_AFMT_GENERIC0_1__SI 0x1F29 -#define mmDIG1_AFMT_GENERIC0_2__SI 0x1F2A -#define mmDIG1_AFMT_GENERIC0_3__SI 0x1F2B -#define mmDIG1_AFMT_GENERIC0_4__SI 0x1F2C -#define mmDIG1_AFMT_GENERIC0_5__SI 0x1F2D -#define mmDIG1_AFMT_GENERIC0_6__SI 0x1F2E -#define mmDIG1_AFMT_GENERIC0_7__SI 0x1F4E -#define mmDIG1_AFMT_GENERIC0_HDR__SI 0x1F27 -#define mmDIG1_AFMT_GENERIC1_0__SI 0x1F30 -#define mmDIG1_AFMT_GENERIC1_1__SI 0x1F31 -#define mmDIG1_AFMT_GENERIC1_2__SI 0x1F32 -#define mmDIG1_AFMT_GENERIC1_3__SI 0x1F33 -#define mmDIG1_AFMT_GENERIC1_4__SI 0x1F34 -#define mmDIG1_AFMT_GENERIC1_5__SI 0x1F35 -#define mmDIG1_AFMT_GENERIC1_6__SI 0x1F36 -#define mmDIG1_AFMT_GENERIC1_HDR__SI 0x1F2F -#define mmDIG1_AFMT_INFOFRAME_CONTROL0__SI 0x1F4D -#define mmDIG1_AFMT_INTERRUPT_STATUS__SI 0x1F14 -#define mmDIG1_AFMT_ISRC1_0__SI 0x1F18 -#define mmDIG1_AFMT_ISRC1_1__SI 0x1F19 -#define mmDIG1_AFMT_ISRC1_2__SI 0x1F1A -#define mmDIG1_AFMT_ISRC1_3__SI 0x1F1B -#define mmDIG1_AFMT_ISRC1_4__SI 0x1F1C -#define mmDIG1_AFMT_ISRC2_0__SI 0x1F1D -#define mmDIG1_AFMT_ISRC2_1__SI 0x1F1E -#define mmDIG1_AFMT_ISRC2_2__SI 0x1F1F -#define mmDIG1_AFMT_ISRC2_3__SI 0x1F20 -#define mmDIG1_AFMT_MPEG_INFO0__SI 0x1F25 -#define mmDIG1_AFMT_MPEG_INFO1__SI 0x1F26 -#define mmDIG1_AFMT_RAMP_CONTROL0__SI 0x1F44 -#define mmDIG1_AFMT_RAMP_CONTROL1__SI 0x1F45 -#define mmDIG1_AFMT_RAMP_CONTROL2__SI 0x1F46 -#define mmDIG1_AFMT_RAMP_CONTROL3__SI 0x1F47 -#define mmDIG1_AFMT_STATUS__SI 0x1F4A -#define mmDIG1_AFMT_VBI_PACKET_CONTROL__SI 0x1F4C -#define mmDIG1_DIG_CLOCK_PATTERN__SI 0x1F03 -#define mmDIG1_DIG_CNTL__SI 0x1F00 -#define mmDIG1_DIG_DEBUG__SI 0x1F06 -#define mmDIG1_DIG_OUTPUT_CRC_CNTL__SI 0x1F01 -#define mmDIG1_DIG_OUTPUT_CRC_RESULT__SI 0x1F02 -#define mmDIG1_DIG_RANDOM_PATTERN_SEED__SI 0x1F05 -#define mmDIG1_DIG_TEST_PATTERN__SI 0x1F04 -#define mmDIG1_HDCP_CONTROL__SI 0x1F54 -#define mmDIG1_HDCP_DEBUG_CONTROL__SI 0x1F55 -#define mmDIG1_HDCP_DEBUG__SI 0x1F75 -#define mmDIG1_HDCP_DP_STATUS__SI 0x1F74 -#define mmDIG1_HDCP_I2C_CONTROL_0__SI 0x1F58 -#define mmDIG1_HDCP_I2C_CONTROL_1__SI 0x1F59 -#define mmDIG1_HDCP_I2C_STATUS__SI 0x1F5A -#define mmDIG1_HDCP_INT_CONTROL__SI 0x1F56 -#define mmDIG1_HDCP_LINK0_STATUS__SI 0x1F57 -#define mmDIG1_HDCP_LINK1_STATUS__SI 0x1F5B -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA0__SI 0x1F5D -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA10__SI 0x1F68 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA11__SI 0x1F69 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA12__SI 0x1F6A -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA13__SI 0x1F6B -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA14__SI 0x1F6C -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA15_0__SI 0x1F6D -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA15_1__SI 0x1F6E -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA16__SI 0x1F6F -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA17__SI 0x1F70 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA18__SI 0x1F71 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA19__SI 0x1F72 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA1__SI 0x1F5E -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA20__SI 0x1F73 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA2_0__SI 0x1F5F -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA2_1__SI 0x1F60 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA3__SI 0x1F61 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA4__SI 0x1F62 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA5__SI 0x1F63 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA6__SI 0x1F64 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA7__SI 0x1F65 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA8__SI 0x1F66 -#define mmDIG1_HDCP_RECV_PORT_LOCAL_DATA9__SI 0x1F67 -#define mmDIG1_HDCP_RESET__SI 0x1F5C -#define mmDIG1_HDMI_ACR_32_0__SI 0x1F37 -#define mmDIG1_HDMI_ACR_32_1__SI 0x1F38 -#define mmDIG1_HDMI_ACR_44_0__SI 0x1F39 -#define mmDIG1_HDMI_ACR_44_1__SI 0x1F3A -#define mmDIG1_HDMI_ACR_48_0__SI 0x1F3B -#define mmDIG1_HDMI_ACR_48_1__SI 0x1F3C -#define mmDIG1_HDMI_ACR_PACKET_CONTROL__SI 0x1F0F -#define mmDIG1_HDMI_ACR_STATUS_0__SI 0x1F3D -#define mmDIG1_HDMI_ACR_STATUS_1__SI 0x1F3E -#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL__SI 0x1F0E -#define mmDIG1_HDMI_CONTROL__SI 0x1F0C -#define mmDIG1_HDMI_GC__SI 0x1F16 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL__SI 0x1F13 -#define mmDIG1_HDMI_INFOFRAME_CONTROL0__SI 0x1F11 -#define mmDIG1_HDMI_INFOFRAME_CONTROL1__SI 0x1F12 -#define mmDIG1_HDMI_STATUS__SI 0x1F0D -#define mmDIG1_HDMI_VBI_PACKET_CONTROL__SI 0x1F10 -#define mmDIG1_LVDS_DATA_CNTL__SI 0x1F8C -#define mmDIG1_SDVO_CNTL__SI 0x1F88 -#define mmDIG1_TMDS_CNTL__SI 0x1F7C -#define mmDIG1_TMDS_CONTROL0_FEEDBACK__SI 0x1F7E -#define mmDIG1_TMDS_CONTROL_CHAR__SI 0x1F7D -#define mmDIG1_TMDS_CTL0_1_GEN_CNTL__SI 0x1F86 -#define mmDIG1_TMDS_CTL2_3_GEN_CNTL__SI 0x1F87 -#define mmDIG1_TMDS_CTL_BITS__SI 0x1F83 -#define mmDIG1_TMDS_DCBALANCER_CONTROL__SI 0x1F84 -#define mmDIG1_TMDS_DEBUG__SI 0x1F82 -#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL__SI 0x1F7F -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1__SI 0x1F80 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3__SI 0x1F81 -#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR__SI 0x1F85 -#define mmDIG2_AFMT_60958_0__SI 0x4241 -#define mmDIG2_AFMT_60958_1__SI 0x4242 -#define mmDIG2_AFMT_60958_2__SI 0x4248 -#define mmDIG2_AFMT_ACP__SI 0x4215 -#define mmDIG2_AFMT_AUDIO_CRC_CONTROL__SI 0x4243 -#define mmDIG2_AFMT_AUDIO_CRC_RESULT__SI 0x4249 -#define mmDIG2_AFMT_AUDIO_INFO0__SI 0x423F -#define mmDIG2_AFMT_AUDIO_INFO1__SI 0x4240 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2__SI 0x4217 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL__SI 0x424B -#define mmDIG2_AFMT_AVI_INFO0__SI 0x4221 -#define mmDIG2_AFMT_AVI_INFO1__SI 0x4222 -#define mmDIG2_AFMT_AVI_INFO2__SI 0x4223 -#define mmDIG2_AFMT_AVI_INFO3__SI 0x4224 -#define mmDIG2_AFMT_GENERIC0_0__SI 0x4228 -#define mmDIG2_AFMT_GENERIC0_1__SI 0x4229 -#define mmDIG2_AFMT_GENERIC0_2__SI 0x422A -#define mmDIG2_AFMT_GENERIC0_3__SI 0x422B -#define mmDIG2_AFMT_GENERIC0_4__SI 0x422C -#define mmDIG2_AFMT_GENERIC0_5__SI 0x422D -#define mmDIG2_AFMT_GENERIC0_6__SI 0x422E -#define mmDIG2_AFMT_GENERIC0_7__SI 0x424E -#define mmDIG2_AFMT_GENERIC0_HDR__SI 0x4227 -#define mmDIG2_AFMT_GENERIC1_0__SI 0x4230 -#define mmDIG2_AFMT_GENERIC1_1__SI 0x4231 -#define mmDIG2_AFMT_GENERIC1_2__SI 0x4232 -#define mmDIG2_AFMT_GENERIC1_3__SI 0x4233 -#define mmDIG2_AFMT_GENERIC1_4__SI 0x4234 -#define mmDIG2_AFMT_GENERIC1_5__SI 0x4235 -#define mmDIG2_AFMT_GENERIC1_6__SI 0x4236 -#define mmDIG2_AFMT_GENERIC1_HDR__SI 0x422F -#define mmDIG2_AFMT_INFOFRAME_CONTROL0__SI 0x424D -#define mmDIG2_AFMT_INTERRUPT_STATUS__SI 0x4214 -#define mmDIG2_AFMT_ISRC1_0__SI 0x4218 -#define mmDIG2_AFMT_ISRC1_1__SI 0x4219 -#define mmDIG2_AFMT_ISRC1_2__SI 0x421A -#define mmDIG2_AFMT_ISRC1_3__SI 0x421B -#define mmDIG2_AFMT_ISRC1_4__SI 0x421C -#define mmDIG2_AFMT_ISRC2_0__SI 0x421D -#define mmDIG2_AFMT_ISRC2_1__SI 0x421E -#define mmDIG2_AFMT_ISRC2_2__SI 0x421F -#define mmDIG2_AFMT_ISRC2_3__SI 0x4220 -#define mmDIG2_AFMT_MPEG_INFO0__SI 0x4225 -#define mmDIG2_AFMT_MPEG_INFO1__SI 0x4226 -#define mmDIG2_AFMT_RAMP_CONTROL0__SI 0x4244 -#define mmDIG2_AFMT_RAMP_CONTROL1__SI 0x4245 -#define mmDIG2_AFMT_RAMP_CONTROL2__SI 0x4246 -#define mmDIG2_AFMT_RAMP_CONTROL3__SI 0x4247 -#define mmDIG2_AFMT_STATUS__SI 0x424A -#define mmDIG2_AFMT_VBI_PACKET_CONTROL__SI 0x424C -#define mmDIG2_DIG_CLOCK_PATTERN__SI 0x4203 -#define mmDIG2_DIG_CNTL__SI 0x4200 -#define mmDIG2_DIG_DEBUG__SI 0x4206 -#define mmDIG2_DIG_OUTPUT_CRC_CNTL__SI 0x4201 -#define mmDIG2_DIG_OUTPUT_CRC_RESULT__SI 0x4202 -#define mmDIG2_DIG_RANDOM_PATTERN_SEED__SI 0x4205 -#define mmDIG2_DIG_TEST_PATTERN__SI 0x4204 -#define mmDIG2_HDCP_CONTROL__SI 0x4254 -#define mmDIG2_HDCP_DEBUG_CONTROL__SI 0x4255 -#define mmDIG2_HDCP_DEBUG__SI 0x4275 -#define mmDIG2_HDCP_DP_STATUS__SI 0x4274 -#define mmDIG2_HDCP_I2C_CONTROL_0__SI 0x4258 -#define mmDIG2_HDCP_I2C_CONTROL_1__SI 0x4259 -#define mmDIG2_HDCP_I2C_STATUS__SI 0x425A -#define mmDIG2_HDCP_INT_CONTROL__SI 0x4256 -#define mmDIG2_HDCP_LINK0_STATUS__SI 0x4257 -#define mmDIG2_HDCP_LINK1_STATUS__SI 0x425B -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA0__SI 0x425D -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA10__SI 0x4268 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA11__SI 0x4269 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA12__SI 0x426A -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA13__SI 0x426B -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA14__SI 0x426C -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA15_0__SI 0x426D -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA15_1__SI 0x426E -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA16__SI 0x426F -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA17__SI 0x4270 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA18__SI 0x4271 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA19__SI 0x4272 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA1__SI 0x425E -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA20__SI 0x4273 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA2_0__SI 0x425F -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA2_1__SI 0x4260 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA3__SI 0x4261 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA4__SI 0x4262 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA5__SI 0x4263 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA6__SI 0x4264 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA7__SI 0x4265 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA8__SI 0x4266 -#define mmDIG2_HDCP_RECV_PORT_LOCAL_DATA9__SI 0x4267 -#define mmDIG2_HDCP_RESET__SI 0x425C -#define mmDIG2_HDMI_ACR_32_0__SI 0x4237 -#define mmDIG2_HDMI_ACR_32_1__SI 0x4238 -#define mmDIG2_HDMI_ACR_44_0__SI 0x4239 -#define mmDIG2_HDMI_ACR_44_1__SI 0x423A -#define mmDIG2_HDMI_ACR_48_0__SI 0x423B -#define mmDIG2_HDMI_ACR_48_1__SI 0x423C -#define mmDIG2_HDMI_ACR_PACKET_CONTROL__SI 0x420F -#define mmDIG2_HDMI_ACR_STATUS_0__SI 0x423D -#define mmDIG2_HDMI_ACR_STATUS_1__SI 0x423E -#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL__SI 0x420E -#define mmDIG2_HDMI_CONTROL__SI 0x420C -#define mmDIG2_HDMI_GC__SI 0x4216 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL__SI 0x4213 -#define mmDIG2_HDMI_INFOFRAME_CONTROL0__SI 0x4211 -#define mmDIG2_HDMI_INFOFRAME_CONTROL1__SI 0x4212 -#define mmDIG2_HDMI_STATUS__SI 0x420D -#define mmDIG2_HDMI_VBI_PACKET_CONTROL__SI 0x4210 -#define mmDIG2_LVDS_DATA_CNTL__SI 0x428C -#define mmDIG2_SDVO_CNTL__SI 0x4288 -#define mmDIG2_TMDS_CNTL__SI 0x427C -#define mmDIG2_TMDS_CONTROL0_FEEDBACK__SI 0x427E -#define mmDIG2_TMDS_CONTROL_CHAR__SI 0x427D -#define mmDIG2_TMDS_CTL0_1_GEN_CNTL__SI 0x4286 -#define mmDIG2_TMDS_CTL2_3_GEN_CNTL__SI 0x4287 -#define mmDIG2_TMDS_CTL_BITS__SI 0x4283 -#define mmDIG2_TMDS_DCBALANCER_CONTROL__SI 0x4284 -#define mmDIG2_TMDS_DEBUG__SI 0x4282 -#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL__SI 0x427F -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1__SI 0x4280 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3__SI 0x4281 -#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR__SI 0x4285 -#define mmDIG3_AFMT_60958_0__SI 0x4541 -#define mmDIG3_AFMT_60958_1__SI 0x4542 -#define mmDIG3_AFMT_60958_2__SI 0x4548 -#define mmDIG3_AFMT_ACP__SI 0x4515 -#define mmDIG3_AFMT_AUDIO_CRC_CONTROL__SI 0x4543 -#define mmDIG3_AFMT_AUDIO_CRC_RESULT__SI 0x4549 -#define mmDIG3_AFMT_AUDIO_INFO0__SI 0x453F -#define mmDIG3_AFMT_AUDIO_INFO1__SI 0x4540 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2__SI 0x4517 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL__SI 0x454B -#define mmDIG3_AFMT_AVI_INFO0__SI 0x4521 -#define mmDIG3_AFMT_AVI_INFO1__SI 0x4522 -#define mmDIG3_AFMT_AVI_INFO2__SI 0x4523 -#define mmDIG3_AFMT_AVI_INFO3__SI 0x4524 -#define mmDIG3_AFMT_GENERIC0_0__SI 0x4528 -#define mmDIG3_AFMT_GENERIC0_1__SI 0x4529 -#define mmDIG3_AFMT_GENERIC0_2__SI 0x452A -#define mmDIG3_AFMT_GENERIC0_3__SI 0x452B -#define mmDIG3_AFMT_GENERIC0_4__SI 0x452C -#define mmDIG3_AFMT_GENERIC0_5__SI 0x452D -#define mmDIG3_AFMT_GENERIC0_6__SI 0x452E -#define mmDIG3_AFMT_GENERIC0_7__SI 0x454E -#define mmDIG3_AFMT_GENERIC0_HDR__SI 0x4527 -#define mmDIG3_AFMT_GENERIC1_0__SI 0x4530 -#define mmDIG3_AFMT_GENERIC1_1__SI 0x4531 -#define mmDIG3_AFMT_GENERIC1_2__SI 0x4532 -#define mmDIG3_AFMT_GENERIC1_3__SI 0x4533 -#define mmDIG3_AFMT_GENERIC1_4__SI 0x4534 -#define mmDIG3_AFMT_GENERIC1_5__SI 0x4535 -#define mmDIG3_AFMT_GENERIC1_6__SI 0x4536 -#define mmDIG3_AFMT_GENERIC1_HDR__SI 0x452F -#define mmDIG3_AFMT_INFOFRAME_CONTROL0__SI 0x454D -#define mmDIG3_AFMT_INTERRUPT_STATUS__SI 0x4514 -#define mmDIG3_AFMT_ISRC1_0__SI 0x4518 -#define mmDIG3_AFMT_ISRC1_1__SI 0x4519 -#define mmDIG3_AFMT_ISRC1_2__SI 0x451A -#define mmDIG3_AFMT_ISRC1_3__SI 0x451B -#define mmDIG3_AFMT_ISRC1_4__SI 0x451C -#define mmDIG3_AFMT_ISRC2_0__SI 0x451D -#define mmDIG3_AFMT_ISRC2_1__SI 0x451E -#define mmDIG3_AFMT_ISRC2_2__SI 0x451F -#define mmDIG3_AFMT_ISRC2_3__SI 0x4520 -#define mmDIG3_AFMT_MPEG_INFO0__SI 0x4525 -#define mmDIG3_AFMT_MPEG_INFO1__SI 0x4526 -#define mmDIG3_AFMT_RAMP_CONTROL0__SI 0x4544 -#define mmDIG3_AFMT_RAMP_CONTROL1__SI 0x4545 -#define mmDIG3_AFMT_RAMP_CONTROL2__SI 0x4546 -#define mmDIG3_AFMT_RAMP_CONTROL3__SI 0x4547 -#define mmDIG3_AFMT_STATUS__SI 0x454A -#define mmDIG3_AFMT_VBI_PACKET_CONTROL__SI 0x454C -#define mmDIG3_DIG_CLOCK_PATTERN__SI 0x4503 -#define mmDIG3_DIG_CNTL__SI 0x4500 -#define mmDIG3_DIG_DEBUG__SI 0x4506 -#define mmDIG3_DIG_OUTPUT_CRC_CNTL__SI 0x4501 -#define mmDIG3_DIG_OUTPUT_CRC_RESULT__SI 0x4502 -#define mmDIG3_DIG_RANDOM_PATTERN_SEED__SI 0x4505 -#define mmDIG3_DIG_TEST_PATTERN__SI 0x4504 -#define mmDIG3_HDCP_CONTROL__SI 0x4554 -#define mmDIG3_HDCP_DEBUG_CONTROL__SI 0x4555 -#define mmDIG3_HDCP_DEBUG__SI 0x4575 -#define mmDIG3_HDCP_DP_STATUS__SI 0x4574 -#define mmDIG3_HDCP_I2C_CONTROL_0__SI 0x4558 -#define mmDIG3_HDCP_I2C_CONTROL_1__SI 0x4559 -#define mmDIG3_HDCP_I2C_STATUS__SI 0x455A -#define mmDIG3_HDCP_INT_CONTROL__SI 0x4556 -#define mmDIG3_HDCP_LINK0_STATUS__SI 0x4557 -#define mmDIG3_HDCP_LINK1_STATUS__SI 0x455B -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA0__SI 0x455D -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA10__SI 0x4568 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA11__SI 0x4569 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA12__SI 0x456A -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA13__SI 0x456B -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA14__SI 0x456C -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA15_0__SI 0x456D -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA15_1__SI 0x456E -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA16__SI 0x456F -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA17__SI 0x4570 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA18__SI 0x4571 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA19__SI 0x4572 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA1__SI 0x455E -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA20__SI 0x4573 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA2_0__SI 0x455F -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA2_1__SI 0x4560 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA3__SI 0x4561 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA4__SI 0x4562 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA5__SI 0x4563 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA6__SI 0x4564 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA7__SI 0x4565 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA8__SI 0x4566 -#define mmDIG3_HDCP_RECV_PORT_LOCAL_DATA9__SI 0x4567 -#define mmDIG3_HDCP_RESET__SI 0x455C -#define mmDIG3_HDMI_ACR_32_0__SI 0x4537 -#define mmDIG3_HDMI_ACR_32_1__SI 0x4538 -#define mmDIG3_HDMI_ACR_44_0__SI 0x4539 -#define mmDIG3_HDMI_ACR_44_1__SI 0x453A -#define mmDIG3_HDMI_ACR_48_0__SI 0x453B -#define mmDIG3_HDMI_ACR_48_1__SI 0x453C -#define mmDIG3_HDMI_ACR_PACKET_CONTROL__SI 0x450F -#define mmDIG3_HDMI_ACR_STATUS_0__SI 0x453D -#define mmDIG3_HDMI_ACR_STATUS_1__SI 0x453E -#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL__SI 0x450E -#define mmDIG3_HDMI_CONTROL__SI 0x450C -#define mmDIG3_HDMI_GC__SI 0x4516 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL__SI 0x4513 -#define mmDIG3_HDMI_INFOFRAME_CONTROL0__SI 0x4511 -#define mmDIG3_HDMI_INFOFRAME_CONTROL1__SI 0x4512 -#define mmDIG3_HDMI_STATUS__SI 0x450D -#define mmDIG3_HDMI_VBI_PACKET_CONTROL__SI 0x4510 -#define mmDIG3_LVDS_DATA_CNTL__SI 0x458C -#define mmDIG3_SDVO_CNTL__SI 0x4588 -#define mmDIG3_TMDS_CNTL__SI 0x457C -#define mmDIG3_TMDS_CONTROL0_FEEDBACK__SI 0x457E -#define mmDIG3_TMDS_CONTROL_CHAR__SI 0x457D -#define mmDIG3_TMDS_CTL0_1_GEN_CNTL__SI 0x4586 -#define mmDIG3_TMDS_CTL2_3_GEN_CNTL__SI 0x4587 -#define mmDIG3_TMDS_CTL_BITS__SI 0x4583 -#define mmDIG3_TMDS_DCBALANCER_CONTROL__SI 0x4584 -#define mmDIG3_TMDS_DEBUG__SI 0x4582 -#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL__SI 0x457F -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1__SI 0x4580 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3__SI 0x4581 -#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR__SI 0x4585 -#define mmDIG4_AFMT_60958_0__SI 0x4841 -#define mmDIG4_AFMT_60958_1__SI 0x4842 -#define mmDIG4_AFMT_60958_2__SI 0x4848 -#define mmDIG4_AFMT_ACP__SI 0x4815 -#define mmDIG4_AFMT_AUDIO_CRC_CONTROL__SI 0x4843 -#define mmDIG4_AFMT_AUDIO_CRC_RESULT__SI 0x4849 -#define mmDIG4_AFMT_AUDIO_INFO0__SI 0x483F -#define mmDIG4_AFMT_AUDIO_INFO1__SI 0x4840 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2__SI 0x4817 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL__SI 0x484B -#define mmDIG4_AFMT_AVI_INFO0__SI 0x4821 -#define mmDIG4_AFMT_AVI_INFO1__SI 0x4822 -#define mmDIG4_AFMT_AVI_INFO2__SI 0x4823 -#define mmDIG4_AFMT_AVI_INFO3__SI 0x4824 -#define mmDIG4_AFMT_GENERIC0_0__SI 0x4828 -#define mmDIG4_AFMT_GENERIC0_1__SI 0x4829 -#define mmDIG4_AFMT_GENERIC0_2__SI 0x482A -#define mmDIG4_AFMT_GENERIC0_3__SI 0x482B -#define mmDIG4_AFMT_GENERIC0_4__SI 0x482C -#define mmDIG4_AFMT_GENERIC0_5__SI 0x482D -#define mmDIG4_AFMT_GENERIC0_6__SI 0x482E -#define mmDIG4_AFMT_GENERIC0_7__SI 0x484E -#define mmDIG4_AFMT_GENERIC0_HDR__SI 0x4827 -#define mmDIG4_AFMT_GENERIC1_0__SI 0x4830 -#define mmDIG4_AFMT_GENERIC1_1__SI 0x4831 -#define mmDIG4_AFMT_GENERIC1_2__SI 0x4832 -#define mmDIG4_AFMT_GENERIC1_3__SI 0x4833 -#define mmDIG4_AFMT_GENERIC1_4__SI 0x4834 -#define mmDIG4_AFMT_GENERIC1_5__SI 0x4835 -#define mmDIG4_AFMT_GENERIC1_6__SI 0x4836 -#define mmDIG4_AFMT_GENERIC1_HDR__SI 0x482F -#define mmDIG4_AFMT_INFOFRAME_CONTROL0__SI 0x484D -#define mmDIG4_AFMT_INTERRUPT_STATUS__SI 0x4814 -#define mmDIG4_AFMT_ISRC1_0__SI 0x4818 -#define mmDIG4_AFMT_ISRC1_1__SI 0x4819 -#define mmDIG4_AFMT_ISRC1_2__SI 0x481A -#define mmDIG4_AFMT_ISRC1_3__SI 0x481B -#define mmDIG4_AFMT_ISRC1_4__SI 0x481C -#define mmDIG4_AFMT_ISRC2_0__SI 0x481D -#define mmDIG4_AFMT_ISRC2_1__SI 0x481E -#define mmDIG4_AFMT_ISRC2_2__SI 0x481F -#define mmDIG4_AFMT_ISRC2_3__SI 0x4820 -#define mmDIG4_AFMT_MPEG_INFO0__SI 0x4825 -#define mmDIG4_AFMT_MPEG_INFO1__SI 0x4826 -#define mmDIG4_AFMT_RAMP_CONTROL0__SI 0x4844 -#define mmDIG4_AFMT_RAMP_CONTROL1__SI 0x4845 -#define mmDIG4_AFMT_RAMP_CONTROL2__SI 0x4846 -#define mmDIG4_AFMT_RAMP_CONTROL3__SI 0x4847 -#define mmDIG4_AFMT_STATUS__SI 0x484A -#define mmDIG4_AFMT_VBI_PACKET_CONTROL__SI 0x484C -#define mmDIG4_DIG_CLOCK_PATTERN__SI 0x4803 -#define mmDIG4_DIG_CNTL__SI 0x4800 -#define mmDIG4_DIG_DEBUG__SI 0x4806 -#define mmDIG4_DIG_OUTPUT_CRC_CNTL__SI 0x4801 -#define mmDIG4_DIG_OUTPUT_CRC_RESULT__SI 0x4802 -#define mmDIG4_DIG_RANDOM_PATTERN_SEED__SI 0x4805 -#define mmDIG4_DIG_TEST_PATTERN__SI 0x4804 -#define mmDIG4_HDCP_CONTROL__SI 0x4854 -#define mmDIG4_HDCP_DEBUG_CONTROL__SI 0x4855 -#define mmDIG4_HDCP_DEBUG__SI 0x4875 -#define mmDIG4_HDCP_DP_STATUS__SI 0x4874 -#define mmDIG4_HDCP_I2C_CONTROL_0__SI 0x4858 -#define mmDIG4_HDCP_I2C_CONTROL_1__SI 0x4859 -#define mmDIG4_HDCP_I2C_STATUS__SI 0x485A -#define mmDIG4_HDCP_INT_CONTROL__SI 0x4856 -#define mmDIG4_HDCP_LINK0_STATUS__SI 0x4857 -#define mmDIG4_HDCP_LINK1_STATUS__SI 0x485B -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA0__SI 0x485D -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA10__SI 0x4868 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA11__SI 0x4869 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA12__SI 0x486A -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA13__SI 0x486B -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA14__SI 0x486C -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA15_0__SI 0x486D -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA15_1__SI 0x486E -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA16__SI 0x486F -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA17__SI 0x4870 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA18__SI 0x4871 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA19__SI 0x4872 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA1__SI 0x485E -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA20__SI 0x4873 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA2_0__SI 0x485F -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA2_1__SI 0x4860 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA3__SI 0x4861 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA4__SI 0x4862 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA5__SI 0x4863 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA6__SI 0x4864 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA7__SI 0x4865 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA8__SI 0x4866 -#define mmDIG4_HDCP_RECV_PORT_LOCAL_DATA9__SI 0x4867 -#define mmDIG4_HDCP_RESET__SI 0x485C -#define mmDIG4_HDMI_ACR_32_0__SI 0x4837 -#define mmDIG4_HDMI_ACR_32_1__SI 0x4838 -#define mmDIG4_HDMI_ACR_44_0__SI 0x4839 -#define mmDIG4_HDMI_ACR_44_1__SI 0x483A -#define mmDIG4_HDMI_ACR_48_0__SI 0x483B -#define mmDIG4_HDMI_ACR_48_1__SI 0x483C -#define mmDIG4_HDMI_ACR_PACKET_CONTROL__SI 0x480F -#define mmDIG4_HDMI_ACR_STATUS_0__SI 0x483D -#define mmDIG4_HDMI_ACR_STATUS_1__SI 0x483E -#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL__SI 0x480E -#define mmDIG4_HDMI_CONTROL__SI 0x480C -#define mmDIG4_HDMI_GC__SI 0x4816 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL__SI 0x4813 -#define mmDIG4_HDMI_INFOFRAME_CONTROL0__SI 0x4811 -#define mmDIG4_HDMI_INFOFRAME_CONTROL1__SI 0x4812 -#define mmDIG4_HDMI_STATUS__SI 0x480D -#define mmDIG4_HDMI_VBI_PACKET_CONTROL__SI 0x4810 -#define mmDIG4_LVDS_DATA_CNTL__SI 0x488C -#define mmDIG4_SDVO_CNTL__SI 0x4888 -#define mmDIG4_TMDS_CNTL__SI 0x487C -#define mmDIG4_TMDS_CONTROL0_FEEDBACK__SI 0x487E -#define mmDIG4_TMDS_CONTROL_CHAR__SI 0x487D -#define mmDIG4_TMDS_CTL0_1_GEN_CNTL__SI 0x4886 -#define mmDIG4_TMDS_CTL2_3_GEN_CNTL__SI 0x4887 -#define mmDIG4_TMDS_CTL_BITS__SI 0x4883 -#define mmDIG4_TMDS_DCBALANCER_CONTROL__SI 0x4884 -#define mmDIG4_TMDS_DEBUG__SI 0x4882 -#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL__SI 0x487F -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1__SI 0x4880 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3__SI 0x4881 -#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR__SI 0x4885 -#define mmDIG5_AFMT_60958_0__SI 0x4B41 -#define mmDIG5_AFMT_60958_1__SI 0x4B42 -#define mmDIG5_AFMT_60958_2__SI 0x4B48 -#define mmDIG5_AFMT_ACP__SI 0x4B15 -#define mmDIG5_AFMT_AUDIO_CRC_CONTROL__SI 0x4B43 -#define mmDIG5_AFMT_AUDIO_CRC_RESULT__SI 0x4B49 -#define mmDIG5_AFMT_AUDIO_INFO0__SI 0x4B3F -#define mmDIG5_AFMT_AUDIO_INFO1__SI 0x4B40 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2__SI 0x4B17 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL__SI 0x4B4B -#define mmDIG5_AFMT_AVI_INFO0__SI 0x4B21 -#define mmDIG5_AFMT_AVI_INFO1__SI 0x4B22 -#define mmDIG5_AFMT_AVI_INFO2__SI 0x4B23 -#define mmDIG5_AFMT_AVI_INFO3__SI 0x4B24 -#define mmDIG5_AFMT_GENERIC0_0__SI 0x4B28 -#define mmDIG5_AFMT_GENERIC0_1__SI 0x4B29 -#define mmDIG5_AFMT_GENERIC0_2__SI 0x4B2A -#define mmDIG5_AFMT_GENERIC0_3__SI 0x4B2B -#define mmDIG5_AFMT_GENERIC0_4__SI 0x4B2C -#define mmDIG5_AFMT_GENERIC0_5__SI 0x4B2D -#define mmDIG5_AFMT_GENERIC0_6__SI 0x4B2E -#define mmDIG5_AFMT_GENERIC0_7__SI 0x4B4E -#define mmDIG5_AFMT_GENERIC0_HDR__SI 0x4B27 -#define mmDIG5_AFMT_GENERIC1_0__SI 0x4B30 -#define mmDIG5_AFMT_GENERIC1_1__SI 0x4B31 -#define mmDIG5_AFMT_GENERIC1_2__SI 0x4B32 -#define mmDIG5_AFMT_GENERIC1_3__SI 0x4B33 -#define mmDIG5_AFMT_GENERIC1_4__SI 0x4B34 -#define mmDIG5_AFMT_GENERIC1_5__SI 0x4B35 -#define mmDIG5_AFMT_GENERIC1_6__SI 0x4B36 -#define mmDIG5_AFMT_GENERIC1_HDR__SI 0x4B2F -#define mmDIG5_AFMT_INFOFRAME_CONTROL0__SI 0x4B4D -#define mmDIG5_AFMT_INTERRUPT_STATUS__SI 0x4B14 -#define mmDIG5_AFMT_ISRC1_0__SI 0x4B18 -#define mmDIG5_AFMT_ISRC1_1__SI 0x4B19 -#define mmDIG5_AFMT_ISRC1_2__SI 0x4B1A -#define mmDIG5_AFMT_ISRC1_3__SI 0x4B1B -#define mmDIG5_AFMT_ISRC1_4__SI 0x4B1C -#define mmDIG5_AFMT_ISRC2_0__SI 0x4B1D -#define mmDIG5_AFMT_ISRC2_1__SI 0x4B1E -#define mmDIG5_AFMT_ISRC2_2__SI 0x4B1F -#define mmDIG5_AFMT_ISRC2_3__SI 0x4B20 -#define mmDIG5_AFMT_MPEG_INFO0__SI 0x4B25 -#define mmDIG5_AFMT_MPEG_INFO1__SI 0x4B26 -#define mmDIG5_AFMT_RAMP_CONTROL0__SI 0x4B44 -#define mmDIG5_AFMT_RAMP_CONTROL1__SI 0x4B45 -#define mmDIG5_AFMT_RAMP_CONTROL2__SI 0x4B46 -#define mmDIG5_AFMT_RAMP_CONTROL3__SI 0x4B47 -#define mmDIG5_AFMT_STATUS__SI 0x4B4A -#define mmDIG5_AFMT_VBI_PACKET_CONTROL__SI 0x4B4C -#define mmDIG5_DIG_CLOCK_PATTERN__SI 0x4B03 -#define mmDIG5_DIG_CNTL__SI 0x4B00 -#define mmDIG5_DIG_DEBUG__SI 0x4B06 -#define mmDIG5_DIG_OUTPUT_CRC_CNTL__SI 0x4B01 -#define mmDIG5_DIG_OUTPUT_CRC_RESULT__SI 0x4B02 -#define mmDIG5_DIG_RANDOM_PATTERN_SEED__SI 0x4B05 -#define mmDIG5_DIG_TEST_PATTERN__SI 0x4B04 -#define mmDIG5_HDCP_CONTROL__SI 0x4B54 -#define mmDIG5_HDCP_DEBUG_CONTROL__SI 0x4B55 -#define mmDIG5_HDCP_DEBUG__SI 0x4B75 -#define mmDIG5_HDCP_DP_STATUS__SI 0x4B74 -#define mmDIG5_HDCP_I2C_CONTROL_0__SI 0x4B58 -#define mmDIG5_HDCP_I2C_CONTROL_1__SI 0x4B59 -#define mmDIG5_HDCP_I2C_STATUS__SI 0x4B5A -#define mmDIG5_HDCP_INT_CONTROL__SI 0x4B56 -#define mmDIG5_HDCP_LINK0_STATUS__SI 0x4B57 -#define mmDIG5_HDCP_LINK1_STATUS__SI 0x4B5B -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA0__SI 0x4B5D -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA10__SI 0x4B68 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA11__SI 0x4B69 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA12__SI 0x4B6A -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA13__SI 0x4B6B -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA14__SI 0x4B6C -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA15_0__SI 0x4B6D -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA15_1__SI 0x4B6E -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA16__SI 0x4B6F -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA17__SI 0x4B70 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA18__SI 0x4B71 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA19__SI 0x4B72 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA1__SI 0x4B5E -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA20__SI 0x4B73 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA2_0__SI 0x4B5F -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA2_1__SI 0x4B60 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA3__SI 0x4B61 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA4__SI 0x4B62 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA5__SI 0x4B63 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA6__SI 0x4B64 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA7__SI 0x4B65 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA8__SI 0x4B66 -#define mmDIG5_HDCP_RECV_PORT_LOCAL_DATA9__SI 0x4B67 -#define mmDIG5_HDCP_RESET__SI 0x4B5C -#define mmDIG5_HDMI_ACR_32_0__SI 0x4B37 -#define mmDIG5_HDMI_ACR_32_1__SI 0x4B38 -#define mmDIG5_HDMI_ACR_44_0__SI 0x4B39 -#define mmDIG5_HDMI_ACR_44_1__SI 0x4B3A -#define mmDIG5_HDMI_ACR_48_0__SI 0x4B3B -#define mmDIG5_HDMI_ACR_48_1__SI 0x4B3C -#define mmDIG5_HDMI_ACR_PACKET_CONTROL__SI 0x4B0F -#define mmDIG5_HDMI_ACR_STATUS_0__SI 0x4B3D -#define mmDIG5_HDMI_ACR_STATUS_1__SI 0x4B3E -#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL__SI 0x4B0E -#define mmDIG5_HDMI_CONTROL__SI 0x4B0C -#define mmDIG5_HDMI_GC__SI 0x4B16 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL__SI 0x4B13 -#define mmDIG5_HDMI_INFOFRAME_CONTROL0__SI 0x4B11 -#define mmDIG5_HDMI_INFOFRAME_CONTROL1__SI 0x4B12 -#define mmDIG5_HDMI_STATUS__SI 0x4B0D -#define mmDIG5_HDMI_VBI_PACKET_CONTROL__SI 0x4B10 -#define mmDIG5_LVDS_DATA_CNTL__SI 0x4B8C -#define mmDIG5_SDVO_CNTL__SI 0x4B88 -#define mmDIG5_TMDS_CNTL__SI 0x4B7C -#define mmDIG5_TMDS_CONTROL0_FEEDBACK__SI 0x4B7E -#define mmDIG5_TMDS_CONTROL_CHAR__SI 0x4B7D -#define mmDIG5_TMDS_CTL0_1_GEN_CNTL__SI 0x4B86 -#define mmDIG5_TMDS_CTL2_3_GEN_CNTL__SI 0x4B87 -#define mmDIG5_TMDS_CTL_BITS__SI 0x4B83 -#define mmDIG5_TMDS_DCBALANCER_CONTROL__SI 0x4B84 -#define mmDIG5_TMDS_DEBUG__SI 0x4B82 -#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL__SI 0x4B7F -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1__SI 0x4B80 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3__SI 0x4B81 -#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR__SI 0x4B85 -#define mmDIGA_CLOCK_ENABLE__SI 0x0136 -#define mmDIGA_LINK_CNTL__SI 0x196B -#define mmDIGA_TRANSMITTER_ENABLE__SI 0x196D -#define mmDIGB_CLOCK_ENABLE__SI 0x0137 -#define mmDIGB_LINK_CNTL__SI 0x196C -#define mmDIGB_TRANSMITTER_ENABLE__SI 0x196E -#define mmDIGC_CLOCK_ENABLE__SI 0x0138 -#define mmDIGD_CLOCK_ENABLE__SI 0x0139 -#define mmDIGE_CLOCK_ENABLE__SI 0x013A -#define mmDIGF_CLOCK_ENABLE__SI 0x013B -#define mmDIG_CLOCK_PATTERN__SI 0x1C03 -#define mmDIG_CNTL__SI 0x1C00 -#define mmDIG_DEBUG__SI 0x1C06 -#define mmDIG_OUTPUT_CRC_CNTL__SI 0x1C01 -#define mmDIG_OUTPUT_CRC_RESULT__SI 0x1C02 -#define mmDIG_RANDOM_PATTERN_SEED__SI 0x1C05 -#define mmDIG_TEST_PATTERN__SI 0x1C04 -#define mmDISPCLK_CGTT_BLK_CTRL_REG__SI 0x0128 -#define mmDISPCLK_DCFE0_SOFT_RESET__SI 0x0140 -#define mmDISPCLK_DCFE1_SOFT_RESET__SI 0x0141 -#define mmDISPCLK_DCFE2_SOFT_RESET__SI 0x0142 -#define mmDISPCLK_DCFE3_SOFT_RESET__SI 0x0143 -#define mmDISPCLK_DCFE4_SOFT_RESET__SI 0x0144 -#define mmDISPCLK_DCFE5_SOFT_RESET__SI 0x0145 -#define mmDISPCLK_DCI_SOFT_RESET__SI 0x013C -#define mmDISPCLK_DCO_SOFT_RESET__SI 0x013D -#define mmDISPOUT_SOFT_RESET__SI 0x012F -#define mmDISP_INTERRUPT_STATUS_CONTINUE2__SI 0x183F -#define mmDISP_INTERRUPT_STATUS_CONTINUE__SI 0x183E -#define mmDISP_INTERRUPT_STATUS__SI 0x183D -#define mmDISP_TIMER_CONTROL__SI 0x1842 -#define mmDLL_CNTL__SI__CI 0x0AE9 -#define mmDMA_VIP0_TABLE_ADDR__SI 0x0288 -#define mmDMA_VIP1_TABLE_ADDR__SI 0x028C -#define mmDMA_VIP2_TABLE_ADDR__SI 0x0290 -#define mmDMA_VIP3_TABLE_ADDR__SI 0x0294 -#define mmDMA_VIPH0_ACTIVE__SI 0x0289 -#define mmDMA_VIPH0_COMMAND__SI 0x0280 -#define mmDMA_VIPH0_DESTINATION_ADDR_HIGH__SI 0x0299 -#define mmDMA_VIPH0_SOURCE_ADDR_HIGH__SI 0x0298 -#define mmDMA_VIPH0_TABLE_ADDR_HIGH__SI 0x028A -#define mmDMA_VIPH1_ACTIVE__SI 0x028D -#define mmDMA_VIPH1_COMMAND__SI 0x0281 -#define mmDMA_VIPH1_DESTINATION_ADDR_HIGH__SI 0x029B -#define mmDMA_VIPH1_SOURCE_ADDR_HIGH__SI 0x029A -#define mmDMA_VIPH1_TABLE_ADDR_HIGH__SI 0x028E -#define mmDMA_VIPH2_ACTIVE__SI 0x0291 -#define mmDMA_VIPH2_COMMAND__SI 0x0282 -#define mmDMA_VIPH2_DESTINATION_ADDR_HIGH__SI 0x029D -#define mmDMA_VIPH2_SOURCE_ADDR_HIGH__SI 0x029C -#define mmDMA_VIPH2_TABLE_ADDR_HIGH__SI 0x0292 -#define mmDMA_VIPH3_ACTIVE__SI 0x0295 -#define mmDMA_VIPH3_COMMAND__SI 0x0283 -#define mmDMA_VIPH3_DESTINATION_ADDR_HIGH__SI 0x029F -#define mmDMA_VIPH3_SOURCE_ADDR_HIGH__SI 0x029E -#define mmDMA_VIPH3_TABLE_ADDR_HIGH__SI 0x0296 -#define mmDMA_VIPH_ABORT__SI 0x02A2 -#define mmDMA_VIPH_CHUNK_0__SI 0x0286 -#define mmDMA_VIPH_CHUNK_1_VAL__SI 0x0287 -#define mmDMA_VIPH_MISC_CNTL__SI 0x0285 -#define mmDMA_VIPH_STATUS__SI 0x0284 -#define mmDMA_VIPH_WRCOMB__SI 0x02A4 -#define mmDMCU_CTRL__SI 0x1600 -#define mmDMCU_ERAM_RD_CTRL__SI 0x160B -#define mmDMCU_ERAM_RD_DATA__SI 0x160C -#define mmDMCU_ERAM_WR_CTRL__SI 0x1609 -#define mmDMCU_ERAM_WR_DATA__SI 0x160A -#define mmDMCU_EVENT_TRIGGER__SI 0x1611 -#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI 0x161A -#define mmDMCU_FW_CS_HI__SI 0x1606 -#define mmDMCU_FW_CS_LO__SI 0x1607 -#define mmDMCU_FW_END_ADDR__SI 0x1604 -#define mmDMCU_FW_ISR_START_ADDR__SI 0x1605 -#define mmDMCU_FW_START_ADDR__SI 0x1603 -#define mmDMCU_INTERRUPT_STATUS__SI 0x1614 -#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK__SI 0x1615 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK__SI 0x1616 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI 0x1617 -#define mmDMCU_INT_CNT__SI 0x1619 -#define mmDMCU_IRAM_RD_CTRL__SI 0x160F -#define mmDMCU_IRAM_RD_DATA__SI 0x1610 -#define mmDMCU_IRAM_WR_CTRL__SI 0x160D -#define mmDMCU_IRAM_WR_DATA__SI 0x160E -#define mmDMCU_PC_START_ADDR__SI 0x1602 -#define mmDMCU_RAM_ACCESS_CTRL__SI 0x1608 -#define mmDMCU_STATUS__SI 0x1601 -#define mmDMCU_TEST_DEBUG_DATA__SI 0x1627 -#define mmDMCU_TEST_DEBUG_INDEX__SI 0x1626 -#define mmDMCU_UC_CCR__SI 0x1613 -#define mmDMCU_UC_INTERNAL_INT_STATUS__SI 0x1612 -#define mmDMIF_ARBITRATION_CONTROL__SI 0x02F9 -#define mmDMIF_CONTROL__SI 0x02F6 -#define mmDMIF_HW_DEBUG__SI 0x02F8 -#define mmDMIF_MULTI_CHIP_CNTL__SI 0x02F5 -#define mmDMIF_STATUS__SI 0x02F7 -#define mmDMIF_TEST_DEBUG_DATA__SI 0x0313 -#define mmDMIF_TEST_DEBUG_INDEX__SI 0x0312 -#define mmDOUT_DEBUG__SI 0x184C -#define mmDOUT_POWER_MANAGEMENT_CNTL__SI 0x1841 -#define mmDOUT_SCRATCH0__SI 0x1844 -#define mmDOUT_SCRATCH1__SI 0x1845 -#define mmDOUT_SCRATCH2__SI 0x1846 -#define mmDOUT_SCRATCH3__SI 0x1847 -#define mmDOUT_SCRATCH4__SI 0x1848 -#define mmDOUT_SCRATCH5__SI 0x1849 -#define mmDOUT_SCRATCH6__SI 0x184A -#define mmDOUT_SCRATCH7__SI 0x184B -#define mmDOUT_TEST_DEBUG_DATA__SI 0x184E -#define mmDOUT_TEST_DEBUG_INDEX__SI 0x184D -#define mmDP0_DP_CONFIG__SI 0x1CC2 -#define mmDP0_DP_CP_DEBUG1__SI 0x1CDC -#define mmDP0_DP_CP_DEBUG2__SI 0x1CDD -#define mmDP0_DP_CP_LINK_VERIFICATION_PATTERN__SI 0x1CD9 -#define mmDP0_DP_DPHY_8B10B_CNTL__SI 0x1CD3 -#define mmDP0_DP_DPHY_CNTL__SI 0x1CD0 -#define mmDP0_DP_DPHY_CRC_CNTL__SI 0x1CD7 -#define mmDP0_DP_DPHY_CRC_EN__SI 0x1CD6 -#define mmDP0_DP_DPHY_CRC_RESULT__SI 0x1CD8 -#define mmDP0_DP_DPHY_FAST_TRAINING__SI 0x1CCE -#define mmDP0_DP_DPHY_INTERNAL_CTRL__SI 0x1CDE -#define mmDP0_DP_DPHY_PRBS_CNTL__SI 0x1CD4 -#define mmDP0_DP_DPHY_SCRAM_CNTL__SI 0x1CD5 -#define mmDP0_DP_DPHY_SYM__SI 0x1CD2 -#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL__SI 0x1CD1 -#define mmDP0_DP_IDLE_PATTERN_CNTL__SI 0x1CCC -#define mmDP0_DP_LINK_CNTL__SI 0x1CC0 -#define mmDP0_DP_PIXEL_FORMAT__SI 0x1CC1 -#define mmDP0_DP_SEC_ACP_HEADER__SI 0x1CAB -#define mmDP0_DP_SEC_AUD_M_READBACK__SI 0x1CA8 -#define mmDP0_DP_SEC_AUD_M__SI 0x1CA7 -#define mmDP0_DP_SEC_AUD_N_READBACK__SI 0x1CA6 -#define mmDP0_DP_SEC_AUD_N__SI 0x1CA5 -#define mmDP0_DP_SEC_CNTL__SI 0x1CA0 -#define mmDP0_DP_SEC_FRAMING1__SI 0x1CA1 -#define mmDP0_DP_SEC_FRAMING2__SI 0x1CA2 -#define mmDP0_DP_SEC_FRAMING3__SI 0x1CA3 -#define mmDP0_DP_SEC_FRAMING4__SI 0x1CA4 -#define mmDP0_DP_SEC_PACKET_CNTL__SI 0x1CAA -#define mmDP0_DP_SEC_TIMESTAMP__SI 0x1CA9 -#define mmDP0_DP_STEER_FIFO__SI 0x1CC4 -#define mmDP0_DP_TEST_DEBUG_DATA__SI 0x1CFD -#define mmDP0_DP_TEST_DEBUG_INDEX__SI 0x1CFC -#define mmDP0_DP_VID_INTERRUPT_CNTL__SI 0x1CCF -#define mmDP0_DP_VID_MSA_VBID__SI 0x1CCD -#define mmDP0_DP_VID_M__SI 0x1CCB -#define mmDP0_DP_VID_N__SI 0x1CCA -#define mmDP0_DP_VID_STREAM_CNTL__SI 0x1CC3 -#define mmDP0_DP_VID_TIMING__SI 0x1CC9 -#define mmDP1_DP_CONFIG__SI 0x1FC2 -#define mmDP1_DP_CP_DEBUG1__SI 0x1FDC -#define mmDP1_DP_CP_DEBUG2__SI 0x1FDD -#define mmDP1_DP_CP_LINK_VERIFICATION_PATTERN__SI 0x1FD9 -#define mmDP1_DP_DPHY_8B10B_CNTL__SI 0x1FD3 -#define mmDP1_DP_DPHY_CNTL__SI 0x1FD0 -#define mmDP1_DP_DPHY_CRC_CNTL__SI 0x1FD7 -#define mmDP1_DP_DPHY_CRC_EN__SI 0x1FD6 -#define mmDP1_DP_DPHY_CRC_RESULT__SI 0x1FD8 -#define mmDP1_DP_DPHY_FAST_TRAINING__SI 0x1FCE -#define mmDP1_DP_DPHY_INTERNAL_CTRL__SI 0x1FDE -#define mmDP1_DP_DPHY_PRBS_CNTL__SI 0x1FD4 -#define mmDP1_DP_DPHY_SCRAM_CNTL__SI 0x1FD5 -#define mmDP1_DP_DPHY_SYM__SI 0x1FD2 -#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL__SI 0x1FD1 -#define mmDP1_DP_IDLE_PATTERN_CNTL__SI 0x1FCC -#define mmDP1_DP_LINK_CNTL__SI 0x1FC0 -#define mmDP1_DP_PIXEL_FORMAT__SI 0x1FC1 -#define mmDP1_DP_SEC_ACP_HEADER__SI 0x1FAB -#define mmDP1_DP_SEC_AUD_M_READBACK__SI 0x1FA8 -#define mmDP1_DP_SEC_AUD_M__SI 0x1FA7 -#define mmDP1_DP_SEC_AUD_N_READBACK__SI 0x1FA6 -#define mmDP1_DP_SEC_AUD_N__SI 0x1FA5 -#define mmDP1_DP_SEC_CNTL__SI 0x1FA0 -#define mmDP1_DP_SEC_FRAMING1__SI 0x1FA1 -#define mmDP1_DP_SEC_FRAMING2__SI 0x1FA2 -#define mmDP1_DP_SEC_FRAMING3__SI 0x1FA3 -#define mmDP1_DP_SEC_FRAMING4__SI 0x1FA4 -#define mmDP1_DP_SEC_PACKET_CNTL__SI 0x1FAA -#define mmDP1_DP_SEC_TIMESTAMP__SI 0x1FA9 -#define mmDP1_DP_STEER_FIFO__SI 0x1FC4 -#define mmDP1_DP_TEST_DEBUG_DATA__SI 0x1FFD -#define mmDP1_DP_TEST_DEBUG_INDEX__SI 0x1FFC -#define mmDP1_DP_VID_INTERRUPT_CNTL__SI 0x1FCF -#define mmDP1_DP_VID_MSA_VBID__SI 0x1FCD -#define mmDP1_DP_VID_M__SI 0x1FCB -#define mmDP1_DP_VID_N__SI 0x1FCA -#define mmDP1_DP_VID_STREAM_CNTL__SI 0x1FC3 -#define mmDP1_DP_VID_TIMING__SI 0x1FC9 -#define mmDP2_DP_CONFIG__SI 0x42C2 -#define mmDP2_DP_CP_DEBUG1__SI 0x42DC -#define mmDP2_DP_CP_DEBUG2__SI 0x42DD -#define mmDP2_DP_CP_LINK_VERIFICATION_PATTERN__SI 0x42D9 -#define mmDP2_DP_DPHY_8B10B_CNTL__SI 0x42D3 -#define mmDP2_DP_DPHY_CNTL__SI 0x42D0 -#define mmDP2_DP_DPHY_CRC_CNTL__SI 0x42D7 -#define mmDP2_DP_DPHY_CRC_EN__SI 0x42D6 -#define mmDP2_DP_DPHY_CRC_RESULT__SI 0x42D8 -#define mmDP2_DP_DPHY_FAST_TRAINING__SI 0x42CE -#define mmDP2_DP_DPHY_INTERNAL_CTRL__SI 0x42DE -#define mmDP2_DP_DPHY_PRBS_CNTL__SI 0x42D4 -#define mmDP2_DP_DPHY_SCRAM_CNTL__SI 0x42D5 -#define mmDP2_DP_DPHY_SYM__SI 0x42D2 -#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL__SI 0x42D1 -#define mmDP2_DP_IDLE_PATTERN_CNTL__SI 0x42CC -#define mmDP2_DP_LINK_CNTL__SI 0x42C0 -#define mmDP2_DP_PIXEL_FORMAT__SI 0x42C1 -#define mmDP2_DP_SEC_ACP_HEADER__SI 0x42AB -#define mmDP2_DP_SEC_AUD_M_READBACK__SI 0x42A8 -#define mmDP2_DP_SEC_AUD_M__SI 0x42A7 -#define mmDP2_DP_SEC_AUD_N_READBACK__SI 0x42A6 -#define mmDP2_DP_SEC_AUD_N__SI 0x42A5 -#define mmDP2_DP_SEC_CNTL__SI 0x42A0 -#define mmDP2_DP_SEC_FRAMING1__SI 0x42A1 -#define mmDP2_DP_SEC_FRAMING2__SI 0x42A2 -#define mmDP2_DP_SEC_FRAMING3__SI 0x42A3 -#define mmDP2_DP_SEC_FRAMING4__SI 0x42A4 -#define mmDP2_DP_SEC_PACKET_CNTL__SI 0x42AA -#define mmDP2_DP_SEC_TIMESTAMP__SI 0x42A9 -#define mmDP2_DP_STEER_FIFO__SI 0x42C4 -#define mmDP2_DP_TEST_DEBUG_DATA__SI 0x42FD -#define mmDP2_DP_TEST_DEBUG_INDEX__SI 0x42FC -#define mmDP2_DP_VID_INTERRUPT_CNTL__SI 0x42CF -#define mmDP2_DP_VID_MSA_VBID__SI 0x42CD -#define mmDP2_DP_VID_M__SI 0x42CB -#define mmDP2_DP_VID_N__SI 0x42CA -#define mmDP2_DP_VID_STREAM_CNTL__SI 0x42C3 -#define mmDP2_DP_VID_TIMING__SI 0x42C9 -#define mmDP3_DP_CONFIG__SI 0x45C2 -#define mmDP3_DP_CP_DEBUG1__SI 0x45DC -#define mmDP3_DP_CP_DEBUG2__SI 0x45DD -#define mmDP3_DP_CP_LINK_VERIFICATION_PATTERN__SI 0x45D9 -#define mmDP3_DP_DPHY_8B10B_CNTL__SI 0x45D3 -#define mmDP3_DP_DPHY_CNTL__SI 0x45D0 -#define mmDP3_DP_DPHY_CRC_CNTL__SI 0x45D7 -#define mmDP3_DP_DPHY_CRC_EN__SI 0x45D6 -#define mmDP3_DP_DPHY_CRC_RESULT__SI 0x45D8 -#define mmDP3_DP_DPHY_FAST_TRAINING__SI 0x45CE -#define mmDP3_DP_DPHY_INTERNAL_CTRL__SI 0x45DE -#define mmDP3_DP_DPHY_PRBS_CNTL__SI 0x45D4 -#define mmDP3_DP_DPHY_SCRAM_CNTL__SI 0x45D5 -#define mmDP3_DP_DPHY_SYM__SI 0x45D2 -#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL__SI 0x45D1 -#define mmDP3_DP_IDLE_PATTERN_CNTL__SI 0x45CC -#define mmDP3_DP_LINK_CNTL__SI 0x45C0 -#define mmDP3_DP_PIXEL_FORMAT__SI 0x45C1 -#define mmDP3_DP_SEC_ACP_HEADER__SI 0x45AB -#define mmDP3_DP_SEC_AUD_M_READBACK__SI 0x45A8 -#define mmDP3_DP_SEC_AUD_M__SI 0x45A7 -#define mmDP3_DP_SEC_AUD_N_READBACK__SI 0x45A6 -#define mmDP3_DP_SEC_AUD_N__SI 0x45A5 -#define mmDP3_DP_SEC_CNTL__SI 0x45A0 -#define mmDP3_DP_SEC_FRAMING1__SI 0x45A1 -#define mmDP3_DP_SEC_FRAMING2__SI 0x45A2 -#define mmDP3_DP_SEC_FRAMING3__SI 0x45A3 -#define mmDP3_DP_SEC_FRAMING4__SI 0x45A4 -#define mmDP3_DP_SEC_PACKET_CNTL__SI 0x45AA -#define mmDP3_DP_SEC_TIMESTAMP__SI 0x45A9 -#define mmDP3_DP_STEER_FIFO__SI 0x45C4 -#define mmDP3_DP_TEST_DEBUG_DATA__SI 0x45FD -#define mmDP3_DP_TEST_DEBUG_INDEX__SI 0x45FC -#define mmDP3_DP_VID_INTERRUPT_CNTL__SI 0x45CF -#define mmDP3_DP_VID_MSA_VBID__SI 0x45CD -#define mmDP3_DP_VID_M__SI 0x45CB -#define mmDP3_DP_VID_N__SI 0x45CA -#define mmDP3_DP_VID_STREAM_CNTL__SI 0x45C3 -#define mmDP3_DP_VID_TIMING__SI 0x45C9 -#define mmDP4_DP_CONFIG__SI 0x48C2 -#define mmDP4_DP_CP_DEBUG1__SI 0x48DC -#define mmDP4_DP_CP_DEBUG2__SI 0x48DD -#define mmDP4_DP_CP_LINK_VERIFICATION_PATTERN__SI 0x48D9 -#define mmDP4_DP_DPHY_8B10B_CNTL__SI 0x48D3 -#define mmDP4_DP_DPHY_CNTL__SI 0x48D0 -#define mmDP4_DP_DPHY_CRC_CNTL__SI 0x48D7 -#define mmDP4_DP_DPHY_CRC_EN__SI 0x48D6 -#define mmDP4_DP_DPHY_CRC_RESULT__SI 0x48D8 -#define mmDP4_DP_DPHY_FAST_TRAINING__SI 0x48CE -#define mmDP4_DP_DPHY_INTERNAL_CTRL__SI 0x48DE -#define mmDP4_DP_DPHY_PRBS_CNTL__SI 0x48D4 -#define mmDP4_DP_DPHY_SCRAM_CNTL__SI 0x48D5 -#define mmDP4_DP_DPHY_SYM__SI 0x48D2 -#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL__SI 0x48D1 -#define mmDP4_DP_IDLE_PATTERN_CNTL__SI 0x48CC -#define mmDP4_DP_LINK_CNTL__SI 0x48C0 -#define mmDP4_DP_PIXEL_FORMAT__SI 0x48C1 -#define mmDP4_DP_SEC_ACP_HEADER__SI 0x48AB -#define mmDP4_DP_SEC_AUD_M_READBACK__SI 0x48A8 -#define mmDP4_DP_SEC_AUD_M__SI 0x48A7 -#define mmDP4_DP_SEC_AUD_N_READBACK__SI 0x48A6 -#define mmDP4_DP_SEC_AUD_N__SI 0x48A5 -#define mmDP4_DP_SEC_CNTL__SI 0x48A0 -#define mmDP4_DP_SEC_FRAMING1__SI 0x48A1 -#define mmDP4_DP_SEC_FRAMING2__SI 0x48A2 -#define mmDP4_DP_SEC_FRAMING3__SI 0x48A3 -#define mmDP4_DP_SEC_FRAMING4__SI 0x48A4 -#define mmDP4_DP_SEC_PACKET_CNTL__SI 0x48AA -#define mmDP4_DP_SEC_TIMESTAMP__SI 0x48A9 -#define mmDP4_DP_STEER_FIFO__SI 0x48C4 -#define mmDP4_DP_TEST_DEBUG_DATA__SI 0x48FD -#define mmDP4_DP_TEST_DEBUG_INDEX__SI 0x48FC -#define mmDP4_DP_VID_INTERRUPT_CNTL__SI 0x48CF -#define mmDP4_DP_VID_MSA_VBID__SI 0x48CD -#define mmDP4_DP_VID_M__SI 0x48CB -#define mmDP4_DP_VID_N__SI 0x48CA -#define mmDP4_DP_VID_STREAM_CNTL__SI 0x48C3 -#define mmDP4_DP_VID_TIMING__SI 0x48C9 -#define mmDP5_DP_CONFIG__SI 0x4BC2 -#define mmDP5_DP_CP_DEBUG1__SI 0x4BDC -#define mmDP5_DP_CP_DEBUG2__SI 0x4BDD -#define mmDP5_DP_CP_LINK_VERIFICATION_PATTERN__SI 0x4BD9 -#define mmDP5_DP_DPHY_8B10B_CNTL__SI 0x4BD3 -#define mmDP5_DP_DPHY_CNTL__SI 0x4BD0 -#define mmDP5_DP_DPHY_CRC_CNTL__SI 0x4BD7 -#define mmDP5_DP_DPHY_CRC_EN__SI 0x4BD6 -#define mmDP5_DP_DPHY_CRC_RESULT__SI 0x4BD8 -#define mmDP5_DP_DPHY_FAST_TRAINING__SI 0x4BCE -#define mmDP5_DP_DPHY_INTERNAL_CTRL__SI 0x4BDE -#define mmDP5_DP_DPHY_PRBS_CNTL__SI 0x4BD4 -#define mmDP5_DP_DPHY_SCRAM_CNTL__SI 0x4BD5 -#define mmDP5_DP_DPHY_SYM__SI 0x4BD2 -#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL__SI 0x4BD1 -#define mmDP5_DP_IDLE_PATTERN_CNTL__SI 0x4BCC -#define mmDP5_DP_LINK_CNTL__SI 0x4BC0 -#define mmDP5_DP_PIXEL_FORMAT__SI 0x4BC1 -#define mmDP5_DP_SEC_ACP_HEADER__SI 0x4BAB -#define mmDP5_DP_SEC_AUD_M_READBACK__SI 0x4BA8 -#define mmDP5_DP_SEC_AUD_M__SI 0x4BA7 -#define mmDP5_DP_SEC_AUD_N_READBACK__SI 0x4BA6 -#define mmDP5_DP_SEC_AUD_N__SI 0x4BA5 -#define mmDP5_DP_SEC_CNTL__SI 0x4BA0 -#define mmDP5_DP_SEC_FRAMING1__SI 0x4BA1 -#define mmDP5_DP_SEC_FRAMING2__SI 0x4BA2 -#define mmDP5_DP_SEC_FRAMING3__SI 0x4BA3 -#define mmDP5_DP_SEC_FRAMING4__SI 0x4BA4 -#define mmDP5_DP_SEC_PACKET_CNTL__SI 0x4BAA -#define mmDP5_DP_SEC_TIMESTAMP__SI 0x4BA9 -#define mmDP5_DP_STEER_FIFO__SI 0x4BC4 -#define mmDP5_DP_TEST_DEBUG_DATA__SI 0x4BFD -#define mmDP5_DP_TEST_DEBUG_INDEX__SI 0x4BFC -#define mmDP5_DP_VID_INTERRUPT_CNTL__SI 0x4BCF -#define mmDP5_DP_VID_MSA_VBID__SI 0x4BCD -#define mmDP5_DP_VID_M__SI 0x4BCB -#define mmDP5_DP_VID_N__SI 0x4BCA -#define mmDP5_DP_VID_STREAM_CNTL__SI 0x4BC3 -#define mmDP5_DP_VID_TIMING__SI 0x4BC9 -#define mmDP_AUX0_AUX_ARB_CONTROL__SI 0x1882 -#define mmDP_AUX0_AUX_CONTROL__SI 0x1880 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0__SI 0x188A -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1__SI 0x188B -#define mmDP_AUX0_AUX_DPHY_RX_STATUS__SI 0x188D -#define mmDP_AUX0_AUX_DPHY_TX_CONTROL__SI 0x1889 -#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL__SI 0x1888 -#define mmDP_AUX0_AUX_DPHY_TX_STATUS__SI 0x188C -#define mmDP_AUX0_AUX_INTERRUPT_CONTROL__SI 0x1883 -#define mmDP_AUX0_AUX_LS_DATA__SI 0x1887 -#define mmDP_AUX0_AUX_LS_STATUS__SI 0x1885 -#define mmDP_AUX0_AUX_SW_CONTROL__SI 0x1881 -#define mmDP_AUX0_AUX_SW_DATA__SI 0x1886 -#define mmDP_AUX0_AUX_SW_STATUS__SI 0x1884 -#define mmDP_AUX1_AUX_ARB_CONTROL__SI 0x1896 -#define mmDP_AUX1_AUX_CONTROL__SI 0x1894 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0__SI 0x189E -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1__SI 0x189F -#define mmDP_AUX1_AUX_DPHY_RX_STATUS__SI 0x18A1 -#define mmDP_AUX1_AUX_DPHY_TX_CONTROL__SI 0x189D -#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL__SI 0x189C -#define mmDP_AUX1_AUX_DPHY_TX_STATUS__SI 0x18A0 -#define mmDP_AUX1_AUX_INTERRUPT_CONTROL__SI 0x1897 -#define mmDP_AUX1_AUX_LS_DATA__SI 0x189B -#define mmDP_AUX1_AUX_LS_STATUS__SI 0x1899 -#define mmDP_AUX1_AUX_SW_CONTROL__SI 0x1895 -#define mmDP_AUX1_AUX_SW_DATA__SI 0x189A -#define mmDP_AUX1_AUX_SW_STATUS__SI 0x1898 -#define mmDP_AUX2_AUX_ARB_CONTROL__SI 0x18AA -#define mmDP_AUX2_AUX_CONTROL__SI 0x18A8 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0__SI 0x18B2 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1__SI 0x18B3 -#define mmDP_AUX2_AUX_DPHY_RX_STATUS__SI 0x18B5 -#define mmDP_AUX2_AUX_DPHY_TX_CONTROL__SI 0x18B1 -#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL__SI 0x18B0 -#define mmDP_AUX2_AUX_DPHY_TX_STATUS__SI 0x18B4 -#define mmDP_AUX2_AUX_INTERRUPT_CONTROL__SI 0x18AB -#define mmDP_AUX2_AUX_LS_DATA__SI 0x18AF -#define mmDP_AUX2_AUX_LS_STATUS__SI 0x18AD -#define mmDP_AUX2_AUX_SW_CONTROL__SI 0x18A9 -#define mmDP_AUX2_AUX_SW_DATA__SI 0x18AE -#define mmDP_AUX2_AUX_SW_STATUS__SI 0x18AC -#define mmDP_AUX3_AUX_ARB_CONTROL__SI 0x18C2 -#define mmDP_AUX3_AUX_CONTROL__SI 0x18C0 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0__SI 0x18CA -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1__SI 0x18CB -#define mmDP_AUX3_AUX_DPHY_RX_STATUS__SI 0x18CD -#define mmDP_AUX3_AUX_DPHY_TX_CONTROL__SI 0x18C9 -#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL__SI 0x18C8 -#define mmDP_AUX3_AUX_DPHY_TX_STATUS__SI 0x18CC -#define mmDP_AUX3_AUX_INTERRUPT_CONTROL__SI 0x18C3 -#define mmDP_AUX3_AUX_LS_DATA__SI 0x18C7 -#define mmDP_AUX3_AUX_LS_STATUS__SI 0x18C5 -#define mmDP_AUX3_AUX_SW_CONTROL__SI 0x18C1 -#define mmDP_AUX3_AUX_SW_DATA__SI 0x18C6 -#define mmDP_AUX3_AUX_SW_STATUS__SI 0x18C4 -#define mmDP_AUX4_AUX_ARB_CONTROL__SI 0x18D6 -#define mmDP_AUX4_AUX_CONTROL__SI 0x18D4 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0__SI 0x18DE -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1__SI 0x18DF -#define mmDP_AUX4_AUX_DPHY_RX_STATUS__SI 0x18E1 -#define mmDP_AUX4_AUX_DPHY_TX_CONTROL__SI 0x18DD -#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL__SI 0x18DC -#define mmDP_AUX4_AUX_DPHY_TX_STATUS__SI 0x18E0 -#define mmDP_AUX4_AUX_INTERRUPT_CONTROL__SI 0x18D7 -#define mmDP_AUX4_AUX_LS_DATA__SI 0x18DB -#define mmDP_AUX4_AUX_LS_STATUS__SI 0x18D9 -#define mmDP_AUX4_AUX_SW_CONTROL__SI 0x18D5 -#define mmDP_AUX4_AUX_SW_DATA__SI 0x18DA -#define mmDP_AUX4_AUX_SW_STATUS__SI 0x18D8 -#define mmDP_AUX5_AUX_ARB_CONTROL__SI 0x18EA -#define mmDP_AUX5_AUX_CONTROL__SI 0x18E8 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0__SI 0x18F2 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1__SI 0x18F3 -#define mmDP_AUX5_AUX_DPHY_RX_STATUS__SI 0x18F5 -#define mmDP_AUX5_AUX_DPHY_TX_CONTROL__SI 0x18F1 -#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL__SI 0x18F0 -#define mmDP_AUX5_AUX_DPHY_TX_STATUS__SI 0x18F4 -#define mmDP_AUX5_AUX_INTERRUPT_CONTROL__SI 0x18EB -#define mmDP_AUX5_AUX_LS_DATA__SI 0x18EF -#define mmDP_AUX5_AUX_LS_STATUS__SI 0x18ED -#define mmDP_AUX5_AUX_SW_CONTROL__SI 0x18E9 -#define mmDP_AUX5_AUX_SW_DATA__SI 0x18EE -#define mmDP_AUX5_AUX_SW_STATUS__SI 0x18EC -#define mmDP_CONFIG__SI 0x1CC2 -#define mmDP_CP_DEBUG1__SI 0x1CDC -#define mmDP_CP_DEBUG2__SI 0x1CDD -#define mmDP_CP_LINK_VERIFICATION_PATTERN__SI 0x1CD9 -#define mmDP_DPHY_8B10B_CNTL__SI 0x1CD3 -#define mmDP_DPHY_CNTL__SI 0x1CD0 -#define mmDP_DPHY_CRC_CNTL__SI 0x1CD7 -#define mmDP_DPHY_CRC_EN__SI 0x1CD6 -#define mmDP_DPHY_CRC_RESULT__SI 0x1CD8 -#define mmDP_DPHY_FAST_TRAINING__SI 0x1CCE -#define mmDP_DPHY_INTERNAL_CTRL__SI 0x1CDE -#define mmDP_DPHY_PRBS_CNTL__SI 0x1CD4 -#define mmDP_DPHY_SCRAM_CNTL__SI 0x1CD5 -#define mmDP_DPHY_SYM__SI 0x1CD2 -#define mmDP_DPHY_TRAINING_PATTERN_SEL__SI 0x1CD1 -#define mmDP_DTO0_MODULO__SI 0x0171 -#define mmDP_DTO0_PHASE__SI 0x0170 -#define mmDP_DTO1_MODULO__SI 0x0173 -#define mmDP_DTO1_PHASE__SI 0x0172 -#define mmDP_DTO2_MODULO__SI 0x0175 -#define mmDP_DTO2_PHASE__SI 0x0174 -#define mmDP_DTO3_MODULO__SI 0x0177 -#define mmDP_DTO3_PHASE__SI 0x0176 -#define mmDP_DTO4_MODULO__SI 0x0179 -#define mmDP_DTO4_PHASE__SI 0x0178 -#define mmDP_DTO5_MODULO__SI 0x017B -#define mmDP_DTO5_PHASE__SI 0x017A -#define mmDP_IDLE_PATTERN_CNTL__SI 0x1CCC -#define mmDP_LINK_CNTL__SI 0x1CC0 -#define mmDP_PIXEL_FORMAT__SI 0x1CC1 -#define mmDP_SEC_ACP_HEADER__SI 0x1CAB -#define mmDP_SEC_AUD_M_READBACK__SI 0x1CA8 -#define mmDP_SEC_AUD_M__SI 0x1CA7 -#define mmDP_SEC_AUD_N_READBACK__SI 0x1CA6 -#define mmDP_SEC_AUD_N__SI 0x1CA5 -#define mmDP_SEC_CNTL__SI 0x1CA0 -#define mmDP_SEC_FRAMING1__SI 0x1CA1 -#define mmDP_SEC_FRAMING2__SI 0x1CA2 -#define mmDP_SEC_FRAMING3__SI 0x1CA3 -#define mmDP_SEC_FRAMING4__SI 0x1CA4 -#define mmDP_SEC_PACKET_CNTL__SI 0x1CAA -#define mmDP_SEC_TIMESTAMP__SI 0x1CA9 -#define mmDP_STEER_FIFO__SI 0x1CC4 -#define mmDP_TEST_DEBUG_DATA__SI 0x1CFD -#define mmDP_TEST_DEBUG_INDEX__SI 0x1CFC -#define mmDP_VID_INTERRUPT_CNTL__SI 0x1CCF -#define mmDP_VID_MSA_VBID__SI 0x1CCD -#define mmDP_VID_M__SI 0x1CCB -#define mmDP_VID_N__SI 0x1CCA -#define mmDP_VID_STREAM_CNTL__SI 0x1CC3 -#define mmDP_VID_TIMING__SI 0x1CC9 -#define mmDRMDMA0_CONFIG__SI 0x0F93 -#define mmDRMDMA1_CLK_CTRL__SI 0x3630 -#define mmDRMDMA1_CNTL__SI 0x360B -#define mmDRMDMA1_CONFIG__SI 0x0F99 -#define mmDRMDMA1_CONTEXT_CNTL__SI 0x3617 -#define mmDRMDMA1_CRC_VALUE__SI 0x3632 -#define mmDRMDMA1_DRM1_CTRL__SI 0x3631 -#define mmDRMDMA1_DRM_COUNTERDATA0__SI 0x3623 -#define mmDRMDMA1_DRM_COUNTERDATA1__SI 0x3624 -#define mmDRMDMA1_DRM_COUNTERDATA2__SI 0x3625 -#define mmDRMDMA1_DRM_COUNTERDATA3__SI 0x3626 -#define mmDRMDMA1_DRM_COUNTERKEY0__SI 0x361F -#define mmDRMDMA1_DRM_COUNTERKEY1__SI 0x3620 -#define mmDRMDMA1_DRM_COUNTERKEY2__SI 0x3621 -#define mmDRMDMA1_DRM_COUNTERKEY3__SI 0x3622 -#define mmDRMDMA1_DRM_IVLOAD0__SI 0x3628 -#define mmDRMDMA1_DRM_IVLOAD1__SI 0x3629 -#define mmDRMDMA1_DRM_IVLOAD2__SI 0x362A -#define mmDRMDMA1_DRM_IVLOAD3__SI 0x362B -#define mmDRMDMA1_DRM_IVLOAD4__SI 0x362C -#define mmDRMDMA1_DRM_OFFSET__SI 0x3627 -#define mmDRMDMA1_DRM_UNROLLKEY__SI 0x362D -#define mmDRMDMA1_DRM_WRAPPEDKEY0__SI 0x361B -#define mmDRMDMA1_DRM_WRAPPEDKEY1__SI 0x361C -#define mmDRMDMA1_DRM_WRAPPEDKEY2__SI 0x361D -#define mmDRMDMA1_DRM_WRAPPEDKEY3__SI 0x361E -#define mmDRMDMA1_FAULT_ADDR_HI__SI 0x361A -#define mmDRMDMA1_FAULT_ADDR_LO__SI 0x3619 -#define mmDRMDMA1_FIFO_CNTL__SI 0x360C -#define mmDRMDMA1_IB_BASE_HI__SI 0x3615 -#define mmDRMDMA1_IB_BASE_LO__SI 0x3614 -#define mmDRMDMA1_IB_CNTL__SI 0x3609 -#define mmDRMDMA1_IB_OFFSET__SI 0x3613 -#define mmDRMDMA1_IB_RPTR__SI 0x360A -#define mmDRMDMA1_IB_SIZE__SI 0x3616 -#define mmDRMDMA1_PERF_CNTL__SI 0x360E -#define mmDRMDMA1_PERF_COUNT0__SI 0x360F -#define mmDRMDMA1_PERF_COUNT1__SI 0x3610 -#define mmDRMDMA1_PREEMPT__SI 0x3618 -#define mmDRMDMA1_PRIV_MODE__SI 0x362F -#define mmDRMDMA1_RB_BASE__SI 0x3601 -#define mmDRMDMA1_RB_CNTL__SI 0x3600 -#define mmDRMDMA1_RB_RPTR_ADDR_HI__SI 0x3607 -#define mmDRMDMA1_RB_RPTR_ADDR_LO__SI 0x3608 -#define mmDRMDMA1_RB_RPTR__SI 0x3602 -#define mmDRMDMA1_RB_WPTR_POLL_ADDR_HI__SI 0x3605 -#define mmDRMDMA1_RB_WPTR_POLL_ADDR_LO__SI 0x3606 -#define mmDRMDMA1_RB_WPTR_POLL_CNTL__SI 0x3604 -#define mmDRMDMA1_RB_WPTR__SI 0x3603 -#define mmDRMDMA1_SEM_INCOMPLETE_TIMER_CNTL__SI 0x3611 -#define mmDRMDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SI 0x3612 -#define mmDRMDMA1_STATUS_REG__SI 0x360D -#define mmDRMDMA1_TILING_CONFIG__SI 0x362E -#define mmDRMDMA_CLK_CTRL__SI 0x3430 -#define mmDRMDMA_CNTL__SI 0x340B -#define mmDRMDMA_CONTEXT_CNTL__SI 0x3417 -#define mmDRMDMA_CRC_VALUE__SI 0x3432 -#define mmDRMDMA_DRM1_CTRL__SI 0x3431 -#define mmDRMDMA_DRM_COUNTERDATA0__SI 0x3423 -#define mmDRMDMA_DRM_COUNTERDATA1__SI 0x3424 -#define mmDRMDMA_DRM_COUNTERDATA2__SI 0x3425 -#define mmDRMDMA_DRM_COUNTERDATA3__SI 0x3426 -#define mmDRMDMA_DRM_COUNTERKEY0__SI 0x341F -#define mmDRMDMA_DRM_COUNTERKEY1__SI 0x3420 -#define mmDRMDMA_DRM_COUNTERKEY2__SI 0x3421 -#define mmDRMDMA_DRM_COUNTERKEY3__SI 0x3422 -#define mmDRMDMA_DRM_IVLOAD0__SI 0x3428 -#define mmDRMDMA_DRM_IVLOAD1__SI 0x3429 -#define mmDRMDMA_DRM_IVLOAD2__SI 0x342A -#define mmDRMDMA_DRM_IVLOAD3__SI 0x342B -#define mmDRMDMA_DRM_IVLOAD4__SI 0x342C -#define mmDRMDMA_DRM_OFFSET__SI 0x3427 -#define mmDRMDMA_DRM_UNROLLKEY__SI 0x342D -#define mmDRMDMA_DRM_WRAPPEDKEY0__SI 0x341B -#define mmDRMDMA_DRM_WRAPPEDKEY1__SI 0x341C -#define mmDRMDMA_DRM_WRAPPEDKEY2__SI 0x341D -#define mmDRMDMA_DRM_WRAPPEDKEY3__SI 0x341E -#define mmDRMDMA_FAULT_ADDR_HI__SI 0x341A -#define mmDRMDMA_FAULT_ADDR_LO__SI 0x3419 -#define mmDRMDMA_FIFO_CNTL__SI 0x340C -#define mmDRMDMA_IB_BASE_HI__SI 0x3415 -#define mmDRMDMA_IB_BASE_LO__SI 0x3414 -#define mmDRMDMA_IB_CNTL__SI 0x3409 -#define mmDRMDMA_IB_OFFSET__SI 0x3413 -#define mmDRMDMA_IB_RPTR__SI 0x340A -#define mmDRMDMA_IB_SIZE__SI 0x3416 -#define mmDRMDMA_PERF_CNTL__SI 0x340E -#define mmDRMDMA_PERF_COUNT0__SI 0x340F -#define mmDRMDMA_PERF_COUNT1__SI 0x3410 -#define mmDRMDMA_PREEMPT__SI 0x3418 -#define mmDRMDMA_PRIV_MODE__SI 0x342F -#define mmDRMDMA_RB_BASE__SI 0x3401 -#define mmDRMDMA_RB_CNTL__SI 0x3400 -#define mmDRMDMA_RB_RPTR_ADDR_HI__SI 0x3407 -#define mmDRMDMA_RB_RPTR_ADDR_LO__SI 0x3408 -#define mmDRMDMA_RB_RPTR__SI 0x3402 -#define mmDRMDMA_RB_WPTR_POLL_ADDR_HI__SI 0x3405 -#define mmDRMDMA_RB_WPTR_POLL_ADDR_LO__SI 0x3406 -#define mmDRMDMA_RB_WPTR_POLL_CNTL__SI 0x3404 -#define mmDRMDMA_RB_WPTR__SI 0x3403 -#define mmDRMDMA_SEM_INCOMPLETE_TIMER_CNTL__SI 0x3411 -#define mmDRMDMA_SEM_WAIT_FAIL_TIMER_CNTL__SI 0x3412 -#define mmDRMDMA_STATUS_REG__SI 0x340D -#define mmDRMDMA_TILING_CONFIG__SI 0x342E -#define mmDRM_ARB_PRIORITY 0x1567 -#define mmDRM_BYTESWAP 0x1565 -#define mmDRM_DEBUG 0x1571 -#define mmDRM_HFS_CONT 0x1547 -#define mmDRM_HFS_HW_NONCE0 0x154D -#define mmDRM_HFS_HW_NONCE1 0x154E -#define mmDRM_HFS_HW_NONCE2 0x154F -#define mmDRM_HFS_HW_NONCE3 0x1550 -#define mmDRM_HFS_HW_RESULT0 0x1555 -#define mmDRM_HFS_HW_RESULT1 0x1556 -#define mmDRM_HFS_HW_RESULT2 0x1557 -#define mmDRM_HFS_HW_RESULT3 0x1558 -#define mmDRM_HFS_SECRET_SEL 0x1548 -#define mmDRM_HFS_START 0x1546 -#define mmDRM_HFS_SW_NONCE0 0x1549 -#define mmDRM_HFS_SW_NONCE1 0x154A -#define mmDRM_HFS_SW_NONCE2 0x154B -#define mmDRM_HFS_SW_NONCE3 0x154C -#define mmDRM_HFS_SW_RESULT0 0x1551 -#define mmDRM_HFS_SW_RESULT1 0x1552 -#define mmDRM_HFS_SW_RESULT2 0x1553 -#define mmDRM_HFS_SW_RESULT3 0x1554 -#define mmDRM_ID_EFUSE 0x155A -#define mmDRM_IH_CREDITS 0x1572 -#define mmDRM_INT_ACK 0x1575 -#define mmDRM_INT_MASK 0x1574 -#define mmDRM_INT_STATUS 0x1573 -#define mmDRM_KEYGEN_CONT 0x1541 -#define mmDRM_KEYGEN_RADDR 0x1542 -#define mmDRM_KEYGEN_RDATA 0x1543 -#define mmDRM_KEYGEN_START 0x1540 -#define mmDRM_KEYGEN_WADDR 0x1544 -#define mmDRM_KEYGEN_WDATA 0x1545 -#define mmDRM_PERFCOUNTER1_HI 0x156E -#define mmDRM_PERFCOUNTER1_LO 0x156D -#define mmDRM_PERFCOUNTER1_SELECT 0x156B -#define mmDRM_PERFCOUNTER2_HI 0x1570 -#define mmDRM_PERFCOUNTER2_LO 0x156F -#define mmDRM_PERFCOUNTER2_SELECT 0x156C -#define mmDRM_PERFMON_CNTL 0x156A -#define mmDRM_PROTO_ADDR 0x1577 -#define mmDRM_PROTO_DATA 0x1578 -#define mmDRM_RESET 0x1566 -#define mmDRM_SIG_FINISH 0x155C -#define mmDRM_SIG_INVALID 0x155F -#define mmDRM_SIG_RADDR 0x155D -#define mmDRM_SIG_RDATA 0x155E -#define mmDRM_SIG_RESULT0 0x1560 -#define mmDRM_SIG_RESULT1 0x1561 -#define mmDRM_SIG_RESULT2 0x1562 -#define mmDRM_SIG_RESULT3 0x1563 -#define mmDRM_SIG_START 0x155B -#define mmDRM_STATUS 0x1576 -#define mmDRM_TIMEOUT 0x1564 -#define mmDRM_TRNG_CNTL 0x1568 -#define mmDRM_TRNG_DATA 0x1569 -#define mmDTO_VCLK_DENOMIN__SI 0x014F -#define mmDTO_VCLK_INC_CORR__SI 0x0151 -#define mmDTO_VCLK_INC__SI 0x0150 -#define mmDVOACLKC_CNTL__SI 0x014E -#define mmDVOACLKC_MVP_CNTL__SI 0x014D -#define mmDVOACLKD_CNTL__SI 0x014C -#define mmDVO_CONTROL__SI 0x185B -#define mmDVO_CRC2_SIG_MASK__SI 0x185D -#define mmDVO_CRC2_SIG_RESULT__SI 0x185E -#define mmDVO_CRC_EN__SI 0x185C -#define mmDVO_ENABLE__SI 0x1858 -#define mmDVO_OUTPUT__SI 0x185A -#define mmDVO_SOURCE_SELECT__SI 0x1859 -#define mmDVO_STRENGTH_CONTROL__SI 0x195D -#define mmEXT1_DIFF_POST_DIV_CNTL__SI 0x0108 -#define mmEXT1_PPLL_CNTL__SI 0x0112 -#define mmEXT1_PPLL_FB_DIV__SI 0x010C -#define mmEXT1_PPLL_POST_DIV_SRC__SI 0x010E -#define mmEXT1_PPLL_POST_DIV__SI 0x010F -#define mmEXT1_PPLL_REF_DIV_SRC__SI 0x0100 -#define mmEXT1_PPLL_REF_DIV__SI 0x0101 -#define mmEXT1_PPLL_UPDATE_CNTL__SI 0x0103 -#define mmEXT1_PPLL_UPDATE_LOCK__SI 0x0102 -#define mmEXT2_DIFF_POST_DIV_CNTL__SI 0x0109 -#define mmEXT2_PPLL_CNTL__SI 0x0113 -#define mmEXT2_PPLL_FB_DIV__SI 0x010D -#define mmEXT2_PPLL_POST_DIV_SRC__SI 0x0110 -#define mmEXT2_PPLL_POST_DIV__SI 0x0111 -#define mmEXT2_PPLL_REF_DIV_SRC__SI 0x0104 -#define mmEXT2_PPLL_REF_DIV__SI 0x0105 -#define mmEXT2_PPLL_UPDATE_CNTL__SI 0x0107 -#define mmEXT2_PPLL_UPDATE_LOCK__SI 0x0106 -#define mmEXTERN_TRIG_CNTL__SI 0x0395 -#define mmEXT_OVERSCAN_LEFT_RIGHT__SI 0x1B5E -#define mmEXT_OVERSCAN_TOP_BOTTOM__SI 0x1B5F -#define mmFBC_CLIENT_REGION_MASK__SI 0x16EB -#define mmFBC_CNTL__SI 0x16D0 -#define mmFBC_COMP_CNTL__SI 0x16D4 -#define mmFBC_COMP_MODE__SI 0x16D5 -#define mmFBC_CSM_REGION_OFFSET_01__SI 0x16E9 -#define mmFBC_CSM_REGION_OFFSET_23__SI 0x16EA -#define mmFBC_DEBUG0__SI 0x16D6 -#define mmFBC_DEBUG1__SI 0x16D7 -#define mmFBC_DEBUG2__SI 0x16D8 -#define mmFBC_DEBUG_COMP__SI 0x16EC -#define mmFBC_DEBUG_CSR_RDATA__SI 0x16EE -#define mmFBC_DEBUG_CSR_WDATA__SI 0x16EF -#define mmFBC_DEBUG_CSR__SI 0x16ED -#define mmFBC_IDLE_FORCE_CLEAR_MASK__SI 0x16D2 -#define mmFBC_IDLE_MASK__SI 0x16D1 -#define mmFBC_IND_LUT0__SI 0x16D9 -#define mmFBC_IND_LUT10__SI 0x16E3 -#define mmFBC_IND_LUT11__SI 0x16E4 -#define mmFBC_IND_LUT12__SI 0x16E5 -#define mmFBC_IND_LUT13__SI 0x16E6 -#define mmFBC_IND_LUT14__SI 0x16E7 -#define mmFBC_IND_LUT15__SI 0x16E8 -#define mmFBC_IND_LUT1__SI 0x16DA -#define mmFBC_IND_LUT2__SI 0x16DB -#define mmFBC_IND_LUT3__SI 0x16DC -#define mmFBC_IND_LUT4__SI 0x16DD -#define mmFBC_IND_LUT5__SI 0x16DE -#define mmFBC_IND_LUT6__SI 0x16DF -#define mmFBC_IND_LUT7__SI 0x16E0 -#define mmFBC_IND_LUT8__SI 0x16E1 -#define mmFBC_IND_LUT9__SI 0x16E2 -#define mmFBC_MISC__SI 0x16F0 -#define mmFBC_START_STOP_DELAY__SI 0x16D3 -#define mmFBC_TEST_DEBUG_DATA__SI 0x16F5 -#define mmFBC_TEST_DEBUG_INDEX__SI 0x16F4 -#define mmFMT0_FMT_BIT_DEPTH_CONTROL__SI 0x1BF2 -#define mmFMT0_FMT_CLAMP_CNTL__SI 0x1BF9 -#define mmFMT0_FMT_CONTROL__SI 0x1BEE -#define mmFMT0_FMT_CRC_CNTL__SI 0x1BFA -#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI 0x1BFC -#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL__SI 0x1BFE -#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK__SI 0x1BFB -#define mmFMT0_FMT_CRC_SIG_RED_GREEN__SI 0x1BFD -#define mmFMT0_FMT_DEBUG_CNTL__SI 0x1BFF -#define mmFMT0_FMT_DITHER_RAND_B_SEED__SI 0x1BF5 -#define mmFMT0_FMT_DITHER_RAND_G_SEED__SI 0x1BF4 -#define mmFMT0_FMT_DITHER_RAND_R_SEED__SI 0x1BF3 -#define mmFMT0_FMT_DYNAMIC_EXP_CNTL__SI 0x1BED -#define mmFMT0_FMT_FORCE_DATA_0_1__SI 0x1BF0 -#define mmFMT0_FMT_FORCE_DATA_2_3__SI 0x1BF1 -#define mmFMT0_FMT_FORCE_OUTPUT_CNTL__SI 0x1BEF -#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI 0x1BF6 -#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x1BF7 -#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x1BF8 -#define mmFMT1_FMT_BIT_DEPTH_CONTROL__SI 0x1EF2 -#define mmFMT1_FMT_CLAMP_CNTL__SI 0x1EF9 -#define mmFMT1_FMT_CONTROL__SI 0x1EEE -#define mmFMT1_FMT_CRC_CNTL__SI 0x1EFA -#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI 0x1EFC -#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL__SI 0x1EFE -#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK__SI 0x1EFB -#define mmFMT1_FMT_CRC_SIG_RED_GREEN__SI 0x1EFD -#define mmFMT1_FMT_DEBUG_CNTL__SI 0x1EFF -#define mmFMT1_FMT_DITHER_RAND_B_SEED__SI 0x1EF5 -#define mmFMT1_FMT_DITHER_RAND_G_SEED__SI 0x1EF4 -#define mmFMT1_FMT_DITHER_RAND_R_SEED__SI 0x1EF3 -#define mmFMT1_FMT_DYNAMIC_EXP_CNTL__SI 0x1EED -#define mmFMT1_FMT_FORCE_DATA_0_1__SI 0x1EF0 -#define mmFMT1_FMT_FORCE_DATA_2_3__SI 0x1EF1 -#define mmFMT1_FMT_FORCE_OUTPUT_CNTL__SI 0x1EEF -#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI 0x1EF6 -#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x1EF7 -#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x1EF8 -#define mmFMT2_FMT_BIT_DEPTH_CONTROL__SI 0x41F2 -#define mmFMT2_FMT_CLAMP_CNTL__SI 0x41F9 -#define mmFMT2_FMT_CONTROL__SI 0x41EE -#define mmFMT2_FMT_CRC_CNTL__SI 0x41FA -#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI 0x41FC -#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL__SI 0x41FE -#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK__SI 0x41FB -#define mmFMT2_FMT_CRC_SIG_RED_GREEN__SI 0x41FD -#define mmFMT2_FMT_DEBUG_CNTL__SI 0x41FF -#define mmFMT2_FMT_DITHER_RAND_B_SEED__SI 0x41F5 -#define mmFMT2_FMT_DITHER_RAND_G_SEED__SI 0x41F4 -#define mmFMT2_FMT_DITHER_RAND_R_SEED__SI 0x41F3 -#define mmFMT2_FMT_DYNAMIC_EXP_CNTL__SI 0x41ED -#define mmFMT2_FMT_FORCE_DATA_0_1__SI 0x41F0 -#define mmFMT2_FMT_FORCE_DATA_2_3__SI 0x41F1 -#define mmFMT2_FMT_FORCE_OUTPUT_CNTL__SI 0x41EF -#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI 0x41F6 -#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x41F7 -#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x41F8 -#define mmFMT3_FMT_BIT_DEPTH_CONTROL__SI 0x44F2 -#define mmFMT3_FMT_CLAMP_CNTL__SI 0x44F9 -#define mmFMT3_FMT_CONTROL__SI 0x44EE -#define mmFMT3_FMT_CRC_CNTL__SI 0x44FA -#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI 0x44FC -#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL__SI 0x44FE -#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK__SI 0x44FB -#define mmFMT3_FMT_CRC_SIG_RED_GREEN__SI 0x44FD -#define mmFMT3_FMT_DEBUG_CNTL__SI 0x44FF -#define mmFMT3_FMT_DITHER_RAND_B_SEED__SI 0x44F5 -#define mmFMT3_FMT_DITHER_RAND_G_SEED__SI 0x44F4 -#define mmFMT3_FMT_DITHER_RAND_R_SEED__SI 0x44F3 -#define mmFMT3_FMT_DYNAMIC_EXP_CNTL__SI 0x44ED -#define mmFMT3_FMT_FORCE_DATA_0_1__SI 0x44F0 -#define mmFMT3_FMT_FORCE_DATA_2_3__SI 0x44F1 -#define mmFMT3_FMT_FORCE_OUTPUT_CNTL__SI 0x44EF -#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI 0x44F6 -#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x44F7 -#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x44F8 -#define mmFMT4_FMT_BIT_DEPTH_CONTROL__SI 0x47F2 -#define mmFMT4_FMT_CLAMP_CNTL__SI 0x47F9 -#define mmFMT4_FMT_CONTROL__SI 0x47EE -#define mmFMT4_FMT_CRC_CNTL__SI 0x47FA -#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI 0x47FC -#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL__SI 0x47FE -#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK__SI 0x47FB -#define mmFMT4_FMT_CRC_SIG_RED_GREEN__SI 0x47FD -#define mmFMT4_FMT_DEBUG_CNTL__SI 0x47FF -#define mmFMT4_FMT_DITHER_RAND_B_SEED__SI 0x47F5 -#define mmFMT4_FMT_DITHER_RAND_G_SEED__SI 0x47F4 -#define mmFMT4_FMT_DITHER_RAND_R_SEED__SI 0x47F3 -#define mmFMT4_FMT_DYNAMIC_EXP_CNTL__SI 0x47ED -#define mmFMT4_FMT_FORCE_DATA_0_1__SI 0x47F0 -#define mmFMT4_FMT_FORCE_DATA_2_3__SI 0x47F1 -#define mmFMT4_FMT_FORCE_OUTPUT_CNTL__SI 0x47EF -#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI 0x47F6 -#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x47F7 -#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x47F8 -#define mmFMT5_FMT_BIT_DEPTH_CONTROL__SI 0x4AF2 -#define mmFMT5_FMT_CLAMP_CNTL__SI 0x4AF9 -#define mmFMT5_FMT_CONTROL__SI 0x4AEE -#define mmFMT5_FMT_CRC_CNTL__SI 0x4AFA -#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI 0x4AFC -#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL__SI 0x4AFE -#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK__SI 0x4AFB -#define mmFMT5_FMT_CRC_SIG_RED_GREEN__SI 0x4AFD -#define mmFMT5_FMT_DEBUG_CNTL__SI 0x4AFF -#define mmFMT5_FMT_DITHER_RAND_B_SEED__SI 0x4AF5 -#define mmFMT5_FMT_DITHER_RAND_G_SEED__SI 0x4AF4 -#define mmFMT5_FMT_DITHER_RAND_R_SEED__SI 0x4AF3 -#define mmFMT5_FMT_DYNAMIC_EXP_CNTL__SI 0x4AED -#define mmFMT5_FMT_FORCE_DATA_0_1__SI 0x4AF0 -#define mmFMT5_FMT_FORCE_DATA_2_3__SI 0x4AF1 -#define mmFMT5_FMT_FORCE_OUTPUT_CNTL__SI 0x4AEF -#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI 0x4AF6 -#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x4AF7 -#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x4AF8 -#define mmFMT_BIT_DEPTH_CONTROL__SI 0x1BF2 -#define mmFMT_CLAMP_CNTL__SI 0x1BF9 -#define mmFMT_CONTROL__SI 0x1BEE -#define mmFMT_CRC_CNTL__SI 0x1BFA -#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK__SI 0x1BFC -#define mmFMT_CRC_SIG_BLUE_CONTROL__SI 0x1BFE -#define mmFMT_CRC_SIG_RED_GREEN_MASK__SI 0x1BFB -#define mmFMT_CRC_SIG_RED_GREEN__SI 0x1BFD -#define mmFMT_DEBUG_CNTL__SI 0x1BFF -#define mmFMT_DITHER_RAND_B_SEED__SI 0x1BF5 -#define mmFMT_DITHER_RAND_G_SEED__SI 0x1BF4 -#define mmFMT_DITHER_RAND_R_SEED__SI 0x1BF3 -#define mmFMT_DYNAMIC_EXP_CNTL__SI 0x1BED -#define mmFMT_FORCE_DATA_0_1__SI 0x1BF0 -#define mmFMT_FORCE_DATA_2_3__SI 0x1BF1 -#define mmFMT_FORCE_OUTPUT_CNTL__SI 0x1BEF -#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI 0x1BF6 -#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x1BF7 -#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x1BF8 -#define mmFREQ_CHANGE_TIMEOUT__SI 0x0208 -#define mmFWD_CHROMA_BOT_ADDR__SI 0x3890 -#define mmFWD_CHROMA_TOP_ADDR__SI 0x388F -#define mmFWD_LUMA_BOT_ADDR__SI 0x388E -#define mmFWD_LUMA_TOP_ADDR__SI 0x388D -#define mmGARLIC_FLUSH_ADDR_END_0__CI__VI 0x1403 -#define mmGARLIC_FLUSH_ADDR_END_1__CI__VI 0x1405 -#define mmGARLIC_FLUSH_ADDR_END_2__CI__VI 0x1407 -#define mmGARLIC_FLUSH_ADDR_END_3__CI__VI 0x1409 -#define mmGARLIC_FLUSH_ADDR_END_4__CI__VI 0x140B -#define mmGARLIC_FLUSH_ADDR_END_5__CI__VI 0x140D -#define mmGARLIC_FLUSH_ADDR_END_6__CI__VI 0x140F -#define mmGARLIC_FLUSH_ADDR_END_7__CI__VI 0x1411 -#define mmGARLIC_FLUSH_ADDR_START_0__CI__VI 0x1402 -#define mmGARLIC_FLUSH_ADDR_START_1__CI__VI 0x1404 -#define mmGARLIC_FLUSH_ADDR_START_2__CI__VI 0x1406 -#define mmGARLIC_FLUSH_ADDR_START_3__CI__VI 0x1408 -#define mmGARLIC_FLUSH_ADDR_START_4__CI__VI 0x140A -#define mmGARLIC_FLUSH_ADDR_START_5__CI__VI 0x140C -#define mmGARLIC_FLUSH_ADDR_START_6__CI__VI 0x140E -#define mmGARLIC_FLUSH_ADDR_START_7__CI__VI 0x1410 -#define mmGARLIC_FLUSH_CNTL__CI__VI 0x1401 -#define mmGARLIC_FLUSH_REQ__CI__VI 0x1412 -#define mmGB_ADDR_CONFIG 0x263E -#define mmGB_BACKEND_MAP 0x263F -#define mmGB_EDC_MODE 0x307E -#define mmGB_GPU_ID 0x2640 -#define mmGB_MACROTILE_MODE0__CI__VI 0x2664 -#define mmGB_MACROTILE_MODE10__CI__VI 0x266E -#define mmGB_MACROTILE_MODE11__CI__VI 0x266F -#define mmGB_MACROTILE_MODE12__CI__VI 0x2670 -#define mmGB_MACROTILE_MODE13__CI__VI 0x2671 -#define mmGB_MACROTILE_MODE14__CI__VI 0x2672 -#define mmGB_MACROTILE_MODE15__CI__VI 0x2673 -#define mmGB_MACROTILE_MODE1__CI__VI 0x2665 -#define mmGB_MACROTILE_MODE2__CI__VI 0x2666 -#define mmGB_MACROTILE_MODE3__CI__VI 0x2667 -#define mmGB_MACROTILE_MODE4__CI__VI 0x2668 -#define mmGB_MACROTILE_MODE5__CI__VI 0x2669 -#define mmGB_MACROTILE_MODE6__CI__VI 0x266A -#define mmGB_MACROTILE_MODE7__CI__VI 0x266B -#define mmGB_MACROTILE_MODE8__CI__VI 0x266C -#define mmGB_MACROTILE_MODE9__CI__VI 0x266D -#define mmGB_TILE_MODE0 0x2644 -#define mmGB_TILE_MODE1 0x2645 -#define mmGB_TILE_MODE10 0x264E -#define mmGB_TILE_MODE11 0x264F -#define mmGB_TILE_MODE12 0x2650 -#define mmGB_TILE_MODE13 0x2651 -#define mmGB_TILE_MODE14 0x2652 -#define mmGB_TILE_MODE15 0x2653 -#define mmGB_TILE_MODE16 0x2654 -#define mmGB_TILE_MODE17 0x2655 -#define mmGB_TILE_MODE18 0x2656 -#define mmGB_TILE_MODE19 0x2657 -#define mmGB_TILE_MODE2 0x2646 -#define mmGB_TILE_MODE20 0x2658 -#define mmGB_TILE_MODE21 0x2659 -#define mmGB_TILE_MODE22 0x265A -#define mmGB_TILE_MODE23 0x265B -#define mmGB_TILE_MODE24 0x265C -#define mmGB_TILE_MODE25 0x265D -#define mmGB_TILE_MODE26 0x265E -#define mmGB_TILE_MODE27 0x265F -#define mmGB_TILE_MODE28 0x2660 -#define mmGB_TILE_MODE29 0x2661 -#define mmGB_TILE_MODE3 0x2647 -#define mmGB_TILE_MODE30 0x2662 -#define mmGB_TILE_MODE31 0x2663 -#define mmGB_TILE_MODE4 0x2648 -#define mmGB_TILE_MODE5 0x2649 -#define mmGB_TILE_MODE6 0x264A -#define mmGB_TILE_MODE7 0x264B -#define mmGB_TILE_MODE8 0x264C -#define mmGB_TILE_MODE9 0x264D -#define mmGCK_SMC_IND_DATA__CI__VI 0x0081 -#define mmGCK_SMC_IND_DATA_alt_1__CI__VI 0x0083 -#define mmGCK_SMC_IND_DATA_alt_2__CI__VI 0x0085 -#define mmGCK_SMC_IND_DATA_alt_3__CI__VI 0x0087 -#define mmGCK_SMC_IND_INDEX__CI__VI 0x0080 -#define mmGCK_SMC_IND_INDEX_alt_1__CI__VI 0x0082 -#define mmGCK_SMC_IND_INDEX_alt_2__CI__VI 0x0084 -#define mmGCK_SMC_IND_INDEX_alt_3__CI__VI 0x0086 -#define mmGC_PRIV_MODE 0x3048 -#define mmGC_USER_PRIM_CONFIG__CI__VI 0x2241 -#define mmGC_USER_RB_BACKEND_DISABLE 0x26DF -#define mmGC_USER_RB_REDUNDANCY__CI__VI 0x26DE -#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 -#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x03A1 -#define mmGDS_ATOM_BASE__CI__VI 0xC40C -#define mmGDS_ATOM_BASE__SI 0x25CE -#define mmGDS_ATOM_CNTL__CI__VI 0xC40A -#define mmGDS_ATOM_CNTL__SI 0x25CC -#define mmGDS_ATOM_COMPLETE__CI__VI 0xC40B -#define mmGDS_ATOM_COMPLETE__SI 0x25CD -#define mmGDS_ATOM_DST__CI__VI 0xC410 -#define mmGDS_ATOM_DST__SI 0x25D2 -#define mmGDS_ATOM_OFFSET0__CI__VI 0xC40E -#define mmGDS_ATOM_OFFSET0__SI 0x25D0 -#define mmGDS_ATOM_OFFSET1__CI__VI 0xC40F -#define mmGDS_ATOM_OFFSET1__SI 0x25D1 -#define mmGDS_ATOM_OP__CI__VI 0xC411 -#define mmGDS_ATOM_OP__SI 0x25D3 -#define mmGDS_ATOM_READ0_U__CI__VI 0xC417 -#define mmGDS_ATOM_READ0_U__SI 0x25D9 -#define mmGDS_ATOM_READ0__CI__VI 0xC416 -#define mmGDS_ATOM_READ0__SI 0x25D8 -#define mmGDS_ATOM_READ1_U__CI__VI 0xC419 -#define mmGDS_ATOM_READ1_U__SI 0x25DB -#define mmGDS_ATOM_READ1__CI__VI 0xC418 -#define mmGDS_ATOM_READ1__SI 0x25DA -#define mmGDS_ATOM_SIZE__CI__VI 0xC40D -#define mmGDS_ATOM_SIZE__SI 0x25CF -#define mmGDS_ATOM_SRC0_U__CI__VI 0xC413 -#define mmGDS_ATOM_SRC0_U__SI 0x25D5 -#define mmGDS_ATOM_SRC0__CI__VI 0xC412 -#define mmGDS_ATOM_SRC0__SI 0x25D4 -#define mmGDS_ATOM_SRC1_U__CI__VI 0xC415 -#define mmGDS_ATOM_SRC1_U__SI 0x25D7 -#define mmGDS_ATOM_SRC1__CI__VI 0xC414 -#define mmGDS_ATOM_SRC1__SI 0x25D6 -#define mmGDS_CNTL_STATUS 0x25C1 -#define mmGDS_COMPUTE_MAX_WAVE_ID__CI__VI 0x3348 -#define mmGDS_CONFIG 0x25C0 -#define mmGDS_DEBUG_CNTL__CI__VI 0x25C8 -#define mmGDS_DEBUG_CNTL__SI 0x25DE -#define mmGDS_DEBUG_DATA__CI__VI 0x25C9 -#define mmGDS_DEBUG_DATA__SI 0x25DF -#define mmGDS_ENHANCE2__CI__VI 0x25C2 -#define mmGDS_ENHANCE__CI__VI 0x334B -#define mmGDS_ENHANCE__SI 0x25DC -#define mmGDS_GRBM_SECDED_CNT__CI 0x25C6 -#define mmGDS_GRBM_SECDED_CNT__SI 0x25E3 -#define mmGDS_GWS_RESET0__CI__VI 0x3344 -#define mmGDS_GWS_RESET1__CI__VI 0x3345 -#define mmGDS_GWS_RESOURCE_CNTL__CI__VI 0xC41A -#define mmGDS_GWS_RESOURCE_CNTL__SI 0x25E0 -#define mmGDS_GWS_RESOURCE_CNT__CI__VI 0xC41C -#define mmGDS_GWS_RESOURCE_RESET__CI__VI 0x3346 -#define mmGDS_GWS_RESOURCE__CI__VI 0xC41B -#define mmGDS_GWS_RESOURCE__SI 0x25E1 -#define mmGDS_GWS_VMID0__CI__VI 0x3320 -#define mmGDS_GWS_VMID10__CI__VI 0x332A -#define mmGDS_GWS_VMID11__CI__VI 0x332B -#define mmGDS_GWS_VMID12__CI__VI 0x332C -#define mmGDS_GWS_VMID13__CI__VI 0x332D -#define mmGDS_GWS_VMID14__CI__VI 0x332E -#define mmGDS_GWS_VMID15__CI__VI 0x332F -#define mmGDS_GWS_VMID1__CI__VI 0x3321 -#define mmGDS_GWS_VMID2__CI__VI 0x3322 -#define mmGDS_GWS_VMID3__CI__VI 0x3323 -#define mmGDS_GWS_VMID4__CI__VI 0x3324 -#define mmGDS_GWS_VMID5__CI__VI 0x3325 -#define mmGDS_GWS_VMID6__CI__VI 0x3326 -#define mmGDS_GWS_VMID7__CI__VI 0x3327 -#define mmGDS_GWS_VMID8__CI__VI 0x3328 -#define mmGDS_GWS_VMID9__CI__VI 0x3329 -#define mmGDS_OA_ADDRESS__CI__VI 0xC41F -#define mmGDS_OA_CGPG_RESTORE__CI__VI 0x334C -#define mmGDS_OA_CNTL__CI__VI 0xC41D -#define mmGDS_OA_COUNTER__CI__VI 0xC41E -#define mmGDS_OA_DED__CI 0x25C7 -#define mmGDS_OA_DED__SI 0x25E4 -#define mmGDS_OA_INCDEC__CI__VI 0xC420 -#define mmGDS_OA_RESET_MASK__CI__VI 0x3349 -#define mmGDS_OA_RESET__CI__VI 0x334A -#define mmGDS_OA_RING_SIZE__CI__VI 0xC421 -#define mmGDS_OA_VMID0__CI__VI 0x3330 -#define mmGDS_OA_VMID10__CI__VI 0x333A -#define mmGDS_OA_VMID11__CI__VI 0x333B -#define mmGDS_OA_VMID12__CI__VI 0x333C -#define mmGDS_OA_VMID13__CI__VI 0x333D -#define mmGDS_OA_VMID14__CI__VI 0x333E -#define mmGDS_OA_VMID15__CI__VI 0x333F -#define mmGDS_OA_VMID1__CI__VI 0x3331 -#define mmGDS_OA_VMID2__CI__VI 0x3332 -#define mmGDS_OA_VMID3__CI__VI 0x3333 -#define mmGDS_OA_VMID4__CI__VI 0x3334 -#define mmGDS_OA_VMID5__CI__VI 0x3335 -#define mmGDS_OA_VMID6__CI__VI 0x3336 -#define mmGDS_OA_VMID7__CI__VI 0x3337 -#define mmGDS_OA_VMID8__CI__VI 0x3338 -#define mmGDS_OA_VMID9__CI__VI 0x3339 -#define mmGDS_PERFCOUNTER0_HI__CI__VI 0xD281 -#define mmGDS_PERFCOUNTER0_HI__SI 0x25E7 -#define mmGDS_PERFCOUNTER0_LO__CI__VI 0xD280 -#define mmGDS_PERFCOUNTER0_LO__SI 0x25E6 -#define mmGDS_PERFCOUNTER0_SELECT1__CI__VI 0xDA84 -#define mmGDS_PERFCOUNTER0_SELECT__CI__VI 0xDA80 -#define mmGDS_PERFCOUNTER0_SELECT__SI 0x25E5 -#define mmGDS_PERFCOUNTER1_HI__CI__VI 0xD283 -#define mmGDS_PERFCOUNTER1_HI__SI 0x25EA -#define mmGDS_PERFCOUNTER1_LO__CI__VI 0xD282 -#define mmGDS_PERFCOUNTER1_LO__SI 0x25E9 -#define mmGDS_PERFCOUNTER1_SELECT__CI__VI 0xDA81 -#define mmGDS_PERFCOUNTER1_SELECT__SI 0x25E8 -#define mmGDS_PERFCOUNTER2_HI__CI__VI 0xD285 -#define mmGDS_PERFCOUNTER2_HI__SI 0x25ED -#define mmGDS_PERFCOUNTER2_LO__CI__VI 0xD284 -#define mmGDS_PERFCOUNTER2_LO__SI 0x25EC -#define mmGDS_PERFCOUNTER2_SELECT__CI__VI 0xDA82 -#define mmGDS_PERFCOUNTER2_SELECT__SI 0x25EB -#define mmGDS_PERFCOUNTER3_HI__CI__VI 0xD287 -#define mmGDS_PERFCOUNTER3_HI__SI 0x25F0 -#define mmGDS_PERFCOUNTER3_LO__CI__VI 0xD286 -#define mmGDS_PERFCOUNTER3_LO__SI 0x25EF -#define mmGDS_PERFCOUNTER3_SELECT__CI__VI 0xDA83 -#define mmGDS_PERFCOUNTER3_SELECT__SI 0x25EE -#define mmGDS_PROTECTION_FAULT__CI__VI 0x25C3 -#define mmGDS_RD_ADDR__CI__VI 0xC400 -#define mmGDS_RD_ADDR__SI 0x25C2 -#define mmGDS_RD_BURST_ADDR__CI__VI 0xC402 -#define mmGDS_RD_BURST_ADDR__SI 0x25C4 -#define mmGDS_RD_BURST_COUNT__CI__VI 0xC403 -#define mmGDS_RD_BURST_COUNT__SI 0x25C5 -#define mmGDS_RD_BURST_DATA__CI__VI 0xC404 -#define mmGDS_RD_BURST_DATA__SI 0x25C6 -#define mmGDS_RD_DATA__CI__VI 0xC401 -#define mmGDS_RD_DATA__SI 0x25C3 -#define mmGDS_SECDED_CNT__CI 0x25C5 -#define mmGDS_SECDED_CNT__SI 0x25E2 -#define mmGDS_VMID0_BASE__CI__VI 0x3300 -#define mmGDS_VMID0_SIZE__CI__VI 0x3301 -#define mmGDS_VMID10_BASE__CI__VI 0x3314 -#define mmGDS_VMID10_SIZE__CI__VI 0x3315 -#define mmGDS_VMID11_BASE__CI__VI 0x3316 -#define mmGDS_VMID11_SIZE__CI__VI 0x3317 -#define mmGDS_VMID12_BASE__CI__VI 0x3318 -#define mmGDS_VMID12_SIZE__CI__VI 0x3319 -#define mmGDS_VMID13_BASE__CI__VI 0x331A -#define mmGDS_VMID13_SIZE__CI__VI 0x331B -#define mmGDS_VMID14_BASE__CI__VI 0x331C -#define mmGDS_VMID14_SIZE__CI__VI 0x331D -#define mmGDS_VMID15_BASE__CI__VI 0x331E -#define mmGDS_VMID15_SIZE__CI__VI 0x331F -#define mmGDS_VMID1_BASE__CI__VI 0x3302 -#define mmGDS_VMID1_SIZE__CI__VI 0x3303 -#define mmGDS_VMID2_BASE__CI__VI 0x3304 -#define mmGDS_VMID2_SIZE__CI__VI 0x3305 -#define mmGDS_VMID3_BASE__CI__VI 0x3306 -#define mmGDS_VMID3_SIZE__CI__VI 0x3307 -#define mmGDS_VMID4_BASE__CI__VI 0x3308 -#define mmGDS_VMID4_SIZE__CI__VI 0x3309 -#define mmGDS_VMID5_BASE__CI__VI 0x330A -#define mmGDS_VMID5_SIZE__CI__VI 0x330B -#define mmGDS_VMID6_BASE__CI__VI 0x330C -#define mmGDS_VMID6_SIZE__CI__VI 0x330D -#define mmGDS_VMID7_BASE__CI__VI 0x330E -#define mmGDS_VMID7_SIZE__CI__VI 0x330F -#define mmGDS_VMID8_BASE__CI__VI 0x3310 -#define mmGDS_VMID8_SIZE__CI__VI 0x3311 -#define mmGDS_VMID9_BASE__CI__VI 0x3312 -#define mmGDS_VMID9_SIZE__CI__VI 0x3313 -#define mmGDS_VM_PROTECTION_FAULT__CI__VI 0x25C4 -#define mmGDS_WRITE_COMPLETE__CI__VI 0xC409 -#define mmGDS_WRITE_COMPLETE__SI 0x25CB -#define mmGDS_WR_ADDR__CI__VI 0xC405 -#define mmGDS_WR_ADDR__SI 0x25C7 -#define mmGDS_WR_BURST_ADDR__CI__VI 0xC407 -#define mmGDS_WR_BURST_ADDR__SI 0x25C9 -#define mmGDS_WR_BURST_DATA__CI__VI 0xC408 -#define mmGDS_WR_BURST_DATA__SI 0x25CA -#define mmGDS_WR_DATA__CI__VI 0xC406 -#define mmGDS_WR_DATA__SI 0x25C8 -#define mmGENENB__SI 0x00F0 -#define mmGENERAL_PWRMGT__SI 0x01E0 -#define mmGENERIC_I2C_CONTROL__SI 0x1834 -#define mmGENERIC_I2C_DATA__SI 0x183A -#define mmGENERIC_I2C_INTERRUPT_CONTROL__SI 0x1835 -#define mmGENERIC_I2C_PIN_DEBUG__SI 0x183C -#define mmGENERIC_I2C_PIN_SELECTION__SI 0x183B -#define mmGENERIC_I2C_SETUP__SI 0x1838 -#define mmGENERIC_I2C_SPEED__SI 0x1837 -#define mmGENERIC_I2C_STATUS__SI 0x1836 -#define mmGENERIC_I2C_TRANSACTION__SI 0x1839 -#define mmGENFC_RD__SI 0x00F2 -#define mmGENFC_WT__SI 0x00EE -#define mmGENFC_WT_alt_1__SI 0x00F6 -#define mmGENMO_RD__SI 0x00F3 -#define mmGENMO_WT__SI 0x00F0 -#define mmGENS0__SI 0x00F0 -#define mmGENS1__SI 0x00EE -#define mmGENS1_alt_1__SI 0x00F6 -#define mmGFX_COPY_STATE 0xA1F4 -#define mmGFX_PIPE_CONTROL__CI__VI 0x226D -#define mmGFX_PIPE_PRIORITY__CI 0xF87F -#define mmGFX_RLC_CONTROL__SI 0x0F91 -#define mmGMCON_DEBUG__CI__VI 0x0D5F -#define mmGMCON_MASK__CI__VI 0x0D52 -#define mmGMCON_MISC2__CI__VI 0x0D44 -#define mmGMCON_MISC3__CI__VI 0x0D51 -#define mmGMCON_MISC__CI__VI 0x0D43 -#define mmGMCON_PERF_MON_CNTL0__CI__VI 0x0D4A -#define mmGMCON_PERF_MON_CNTL1__CI__VI 0x0D4B -#define mmGMCON_PERF_MON_RSLT0__CI__VI 0x0D4C -#define mmGMCON_PERF_MON_RSLT1__CI__VI 0x0D4D -#define mmGMCON_PGFSM_CONFIG__CI__VI 0x0D4E -#define mmGMCON_PGFSM_READ__CI__VI 0x0D50 -#define mmGMCON_PGFSM_WRITE__CI__VI 0x0D4F -#define mmGMCON_RENG_EXECUTE__CI__VI 0x0D42 -#define mmGMCON_RENG_RAM_DATA__CI__VI 0x0D41 -#define mmGMCON_RENG_RAM_INDEX__CI__VI 0x0D40 -#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI 0x0D48 -#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI 0x0D49 -#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI 0x0D45 -#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI 0x0D46 -#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI 0x0D47 -#define mmGPIOPAD_A__CI__VI 0x0183 -#define mmGPIOPAD_A__SI 0x05E7 -#define mmGPIOPAD_EN__CI__VI 0x0184 -#define mmGPIOPAD_EN__SI 0x05E8 -#define mmGPIOPAD_EXTERN_TRIG_CNTL__CI__VI 0x018D -#define mmGPIOPAD_EXTERN_TRIG_CNTL__SI 0x05F1 -#define mmGPIOPAD_INT_EN__CI__VI 0x018A -#define mmGPIOPAD_INT_EN__SI 0x05EE -#define mmGPIOPAD_INT_POLARITY__CI__VI 0x018C -#define mmGPIOPAD_INT_POLARITY__SI 0x05F0 -#define mmGPIOPAD_INT_STAT_AK__CI__VI 0x0189 -#define mmGPIOPAD_INT_STAT_AK__SI 0x05ED -#define mmGPIOPAD_INT_STAT_EN__CI__VI 0x0187 -#define mmGPIOPAD_INT_STAT_EN__SI 0x05EB -#define mmGPIOPAD_INT_STAT__CI__VI 0x0188 -#define mmGPIOPAD_INT_STAT__SI 0x05EC -#define mmGPIOPAD_INT_TYPE__CI__VI 0x018B -#define mmGPIOPAD_INT_TYPE__SI 0x05EF -#define mmGPIOPAD_MASK__CI__VI 0x0182 -#define mmGPIOPAD_MASK__SI 0x05E6 -#define mmGPIOPAD_PD_EN__CI__VI 0x0193 -#define mmGPIOPAD_PD_EN__SI 0x05F4 -#define mmGPIOPAD_PINSTRAPS__CI__VI 0x0186 -#define mmGPIOPAD_PINSTRAPS__SI 0x05EA -#define mmGPIOPAD_PU_EN__CI__VI 0x0192 -#define mmGPIOPAD_PU_EN__SI 0x05F3 -#define mmGPIOPAD_RCVR_SEL__CI__VI 0x0191 -#define mmGPIOPAD_RCVR_SEL__SI 0x05F2 -#define mmGPIOPAD_STRENGTH__CI__VI 0x0181 -#define mmGPIOPAD_STRENGTH__SI 0x05E5 -#define mmGPIOPAD_SW_INT_STAT__CI__VI 0x0180 -#define mmGPIOPAD_SW_INT_STAT__SI 0x05E4 -#define mmGPIOPAD_Y__CI__VI 0x0185 -#define mmGPIOPAD_Y__SI 0x05E9 -#define mmGPU_GARLIC_FLUSH_DONE__CI__VI 0x1414 -#define mmGPU_GARLIC_FLUSH_REQ__CI__VI 0x1413 -#define mmGPU_HDP_FLUSH_DONE__CI__VI 0x1538 -#define mmGPU_HDP_FLUSH_REQ__CI__VI 0x1537 -#define mmGRBM_CNTL 0x2000 -#define mmGRBM_DEBUG 0x2014 -#define mmGRBM_DEBUG_CNTL 0x2009 -#define mmGRBM_DEBUG_DATA 0x200A -#define mmGRBM_DEBUG_SNAPSHOT 0x2015 -#define mmGRBM_GFX_CLKEN_CNTL 0x200C -#define mmGRBM_GFX_INDEX__CI__VI 0xC200 -#define mmGRBM_GFX_INDEX__SI 0x200B -#define mmGRBM_INT_CNTL 0x2018 -#define mmGRBM_NOWHERE 0x203F -#define mmGRBM_PERFCOUNTER0_HI__CI__VI 0xD041 -#define mmGRBM_PERFCOUNTER0_HI__SI 0x201F -#define mmGRBM_PERFCOUNTER0_LO__CI__VI 0xD040 -#define mmGRBM_PERFCOUNTER0_LO__SI 0x201E -#define mmGRBM_PERFCOUNTER0_SELECT__CI__VI 0xD840 -#define mmGRBM_PERFCOUNTER0_SELECT__SI 0x201C -#define mmGRBM_PERFCOUNTER1_HI__CI__VI 0xD044 -#define mmGRBM_PERFCOUNTER1_HI__SI 0x2021 -#define mmGRBM_PERFCOUNTER1_LO__CI__VI 0xD043 -#define mmGRBM_PERFCOUNTER1_LO__SI 0x2020 -#define mmGRBM_PERFCOUNTER1_SELECT__CI__VI 0xD841 -#define mmGRBM_PERFCOUNTER1_SELECT__SI 0x201D -#define mmGRBM_PWR_CNTL 0x2003 -#define mmGRBM_READ_ERROR 0x2016 -#define mmGRBM_READ_ERROR2__CI__VI 0x2017 -#define mmGRBM_SCRATCH_REG0 0x2040 -#define mmGRBM_SCRATCH_REG1 0x2041 -#define mmGRBM_SCRATCH_REG2 0x2042 -#define mmGRBM_SCRATCH_REG3 0x2043 -#define mmGRBM_SCRATCH_REG4 0x2044 -#define mmGRBM_SCRATCH_REG5 0x2045 -#define mmGRBM_SCRATCH_REG6 0x2046 -#define mmGRBM_SCRATCH_REG7 0x2047 -#define mmGRBM_SE0_PERFCOUNTER_HI__CI__VI 0xD046 -#define mmGRBM_SE0_PERFCOUNTER_HI__SI 0x202B -#define mmGRBM_SE0_PERFCOUNTER_LO__CI__VI 0xD045 -#define mmGRBM_SE0_PERFCOUNTER_LO__SI 0x202A -#define mmGRBM_SE0_PERFCOUNTER_SELECT__CI__VI 0xD842 -#define mmGRBM_SE0_PERFCOUNTER_SELECT__SI 0x2026 -#define mmGRBM_SE1_PERFCOUNTER_HI__CI__VI 0xD048 -#define mmGRBM_SE1_PERFCOUNTER_HI__SI 0x202D -#define mmGRBM_SE1_PERFCOUNTER_LO__CI__VI 0xD047 -#define mmGRBM_SE1_PERFCOUNTER_LO__SI 0x202C -#define mmGRBM_SE1_PERFCOUNTER_SELECT__CI__VI 0xD843 -#define mmGRBM_SE1_PERFCOUNTER_SELECT__SI 0x2027 -#define mmGRBM_SE2_PERFCOUNTER_HI__CI__VI 0xD04A -#define mmGRBM_SE2_PERFCOUNTER_LO__CI__VI 0xD049 -#define mmGRBM_SE2_PERFCOUNTER_SELECT__CI__VI 0xD844 -#define mmGRBM_SE3_PERFCOUNTER_HI__CI__VI 0xD04C -#define mmGRBM_SE3_PERFCOUNTER_LO__CI__VI 0xD04B -#define mmGRBM_SE3_PERFCOUNTER_SELECT__CI__VI 0xD845 -#define mmGRBM_SKEW_CNTL 0x2001 -#define mmGRBM_SOFT_RESET 0x2008 -#define mmGRBM_STATUS 0x2004 -#define mmGRBM_STATUS2 0x2002 -#define mmGRBM_STATUS_SE0 0x2005 -#define mmGRBM_STATUS_SE1 0x2006 -#define mmGRBM_STATUS_SE2__CI__VI 0x200E -#define mmGRBM_STATUS_SE3__CI__VI 0x200F -#define mmGRBM_WAIT_IDLE_CLOCKS 0x200D -#define mmGRPH8_DATA__SI 0x00F3 -#define mmGRPH8_IDX__SI 0x00F3 -#define mmGRPH_ALPHA__SI 0x1A4E -#define mmGRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x1A59 -#define mmGRPH_COMPRESS_PITCH__SI 0x1A1A -#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI 0x1A1B -#define mmGRPH_COMPRESS_SURFACE_ADDRESS__SI 0x1A19 -#define mmGRPH_CONTROL__SI 0x1A01 -#define mmGRPH_DFQ_CONTROL__SI 0x1A14 -#define mmGRPH_DFQ_STATUS__SI 0x1A15 -#define mmGRPH_ENABLE__SI 0x1A00 -#define mmGRPH_FLIP_CONTROL__SI 0x1A12 -#define mmGRPH_INTERRUPT_CONTROL__SI 0x1A17 -#define mmGRPH_INTERRUPT_STATUS__SI 0x1A16 -#define mmGRPH_KEY_RANGE_ALPHA__SI 0x1A54 -#define mmGRPH_KEY_RANGE_BLUE__SI 0x1A53 -#define mmGRPH_KEY_RANGE_GREEN__SI 0x1A52 -#define mmGRPH_KEY_RANGE_RED__SI 0x1A51 -#define mmGRPH_LUT_10BIT_BYPASS__SI 0x1A02 -#define mmGRPH_PITCH__SI 0x1A06 -#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 -#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 -#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI 0x1A08 -#define mmGRPH_SECONDARY_SURFACE_ADDRESS__SI 0x1A05 -#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE__SI 0x1A18 -#define mmGRPH_SURFACE_ADDRESS_INUSE__SI 0x1A13 -#define mmGRPH_SURFACE_OFFSET_X__SI 0x1A09 -#define mmGRPH_SURFACE_OFFSET_Y__SI 0x1A0A -#define mmGRPH_SWAP_CNTL__SI 0x1A03 -#define mmGRPH_UPDATE__SI 0x1A11 -#define mmGRPH_X_END__SI 0x1A0D -#define mmGRPH_X_START__SI 0x1A0B -#define mmGRPH_Y_END__SI 0x1A0E -#define mmGRPH_Y_START__SI 0x1A0C -#define mmGUI_SCRATCH_REG0__CI__VI 0xC040 -#define mmGUI_SCRATCH_REG0__SI 0x2140 -#define mmGUI_SCRATCH_REG1__CI__VI 0xC041 -#define mmGUI_SCRATCH_REG1__SI 0x2141 -#define mmGUI_SCRATCH_REG2__CI__VI 0xC042 -#define mmGUI_SCRATCH_REG2__SI 0x2142 -#define mmGUI_SCRATCH_REG3__CI__VI 0xC043 -#define mmGUI_SCRATCH_REG3__SI 0x2143 -#define mmGUI_SCRATCH_REG4__CI__VI 0xC044 -#define mmGUI_SCRATCH_REG4__SI 0x2144 -#define mmGUI_SCRATCH_REG5__CI__VI 0xC045 -#define mmGUI_SCRATCH_REG5__SI 0x2145 -#define mmGUI_SCRATCH_REG6__CI__VI 0xC046 -#define mmGUI_SCRATCH_REG6__SI 0x2146 -#define mmGUI_SCRATCH_REG7__CI__VI 0xC047 -#define mmGUI_SCRATCH_REG7__SI 0x2147 -#define mmHDCP_CONTROL__SI 0x1C54 -#define mmHDCP_DEBUG_CONTROL__SI 0x1C55 -#define mmHDCP_DEBUG__SI 0x1C75 -#define mmHDCP_DP_STATUS__SI 0x1C74 -#define mmHDCP_I2C_CONTROL_0__SI 0x1C58 -#define mmHDCP_I2C_CONTROL_1__SI 0x1C59 -#define mmHDCP_I2C_STATUS__SI 0x1C5A -#define mmHDCP_INT_CONTROL__SI 0x1C56 -#define mmHDCP_LINK0_STATUS__SI 0x1C57 -#define mmHDCP_LINK1_STATUS__SI 0x1C5B -#define mmHDCP_RECV_PORT_LOCAL_DATA0__SI 0x1C5D -#define mmHDCP_RECV_PORT_LOCAL_DATA10__SI 0x1C68 -#define mmHDCP_RECV_PORT_LOCAL_DATA11__SI 0x1C69 -#define mmHDCP_RECV_PORT_LOCAL_DATA12__SI 0x1C6A -#define mmHDCP_RECV_PORT_LOCAL_DATA13__SI 0x1C6B -#define mmHDCP_RECV_PORT_LOCAL_DATA14__SI 0x1C6C -#define mmHDCP_RECV_PORT_LOCAL_DATA15_0__SI 0x1C6D -#define mmHDCP_RECV_PORT_LOCAL_DATA15_1__SI 0x1C6E -#define mmHDCP_RECV_PORT_LOCAL_DATA16__SI 0x1C6F -#define mmHDCP_RECV_PORT_LOCAL_DATA17__SI 0x1C70 -#define mmHDCP_RECV_PORT_LOCAL_DATA18__SI 0x1C71 -#define mmHDCP_RECV_PORT_LOCAL_DATA19__SI 0x1C72 -#define mmHDCP_RECV_PORT_LOCAL_DATA1__SI 0x1C5E -#define mmHDCP_RECV_PORT_LOCAL_DATA20__SI 0x1C73 -#define mmHDCP_RECV_PORT_LOCAL_DATA2_0__SI 0x1C5F -#define mmHDCP_RECV_PORT_LOCAL_DATA2_1__SI 0x1C60 -#define mmHDCP_RECV_PORT_LOCAL_DATA3__SI 0x1C61 -#define mmHDCP_RECV_PORT_LOCAL_DATA4__SI 0x1C62 -#define mmHDCP_RECV_PORT_LOCAL_DATA5__SI 0x1C63 -#define mmHDCP_RECV_PORT_LOCAL_DATA6__SI 0x1C64 -#define mmHDCP_RECV_PORT_LOCAL_DATA7__SI 0x1C65 -#define mmHDCP_RECV_PORT_LOCAL_DATA8__SI 0x1C66 -#define mmHDCP_RECV_PORT_LOCAL_DATA9__SI 0x1C67 -#define mmHDCP_RESET__SI 0x1C5C -#define mmHDCP_SHA_CONTROL__SI 0x1800 -#define mmHDCP_SHA_DATA__SI 0x1802 -#define mmHDCP_SHA_DBG_M0_0__SI 0x1803 -#define mmHDCP_SHA_DBG_M0_1__SI 0x1804 -#define mmHDCP_SHA_STATUS__SI 0x1801 -#define mmHDMI_ACR_32_0__SI 0x1C37 -#define mmHDMI_ACR_32_1__SI 0x1C38 -#define mmHDMI_ACR_44_0__SI 0x1C39 -#define mmHDMI_ACR_44_1__SI 0x1C3A -#define mmHDMI_ACR_48_0__SI 0x1C3B -#define mmHDMI_ACR_48_1__SI 0x1C3C -#define mmHDMI_ACR_PACKET_CONTROL__SI 0x1C0F -#define mmHDMI_ACR_STATUS_0__SI 0x1C3D -#define mmHDMI_ACR_STATUS_1__SI 0x1C3E -#define mmHDMI_AUDIO_PACKET_CONTROL__SI 0x1C0E -#define mmHDMI_CONTROL__SI 0x1C0C -#define mmHDMI_GC__SI 0x1C16 -#define mmHDMI_GENERIC_PACKET_CONTROL__SI 0x1C13 -#define mmHDMI_INFOFRAME_CONTROL0__SI 0x1C11 -#define mmHDMI_INFOFRAME_CONTROL1__SI 0x1C12 -#define mmHDMI_STATUS__SI 0x1C0D -#define mmHDMI_VBI_PACKET_CONTROL__SI 0x1C10 -#define mmHDP_DEBUG0 0x0BCC -#define mmHDP_DEBUG1 0x0BCD -#define mmHDP_HOST_PATH_CNTL 0x0B00 -#define mmHDP_LAST_SURFACE_HIT 0x0BCE -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 -#define mmHDP_NONSURFACE_BASE 0x0B01 -#define mmHDP_NONSURFACE_INFO 0x0B02 -#define mmHDP_NONSURFACE_SIZE 0x0B03 -#define mmHDP_NONSURF_FLAGS 0x0BC9 -#define mmHDP_NONSURF_FLAGS_CLR 0x0BCA -#define mmHDP_OUTSTANDING_REQ 0x0BD1 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 -#define mmHDP_SC_MULTI_CHIP_CNTL 0x0BD0 -#define mmHDP_SURFACE0_BASE 0x0B07 -#define mmHDP_SURFACE0_INFO 0x0B08 -#define mmHDP_SURFACE0_LOWER_BOUND 0x0B05 -#define mmHDP_SURFACE0_SIZE 0x0B09 -#define mmHDP_SURFACE0_UPPER_BOUND 0x0B06 -#define mmHDP_SURFACE10_BASE 0x0B43 -#define mmHDP_SURFACE10_INFO 0x0B44 -#define mmHDP_SURFACE10_LOWER_BOUND 0x0B41 -#define mmHDP_SURFACE10_SIZE 0x0B45 -#define mmHDP_SURFACE10_UPPER_BOUND 0x0B42 -#define mmHDP_SURFACE11_BASE 0x0B49 -#define mmHDP_SURFACE11_INFO 0x0B4A -#define mmHDP_SURFACE11_LOWER_BOUND 0x0B47 -#define mmHDP_SURFACE11_SIZE 0x0B4B -#define mmHDP_SURFACE11_UPPER_BOUND 0x0B48 -#define mmHDP_SURFACE12_BASE 0x0B4F -#define mmHDP_SURFACE12_INFO 0x0B50 -#define mmHDP_SURFACE12_LOWER_BOUND 0x0B4D -#define mmHDP_SURFACE12_SIZE 0x0B51 -#define mmHDP_SURFACE12_UPPER_BOUND 0x0B4E -#define mmHDP_SURFACE13_BASE 0x0B55 -#define mmHDP_SURFACE13_INFO 0x0B56 -#define mmHDP_SURFACE13_LOWER_BOUND 0x0B53 -#define mmHDP_SURFACE13_SIZE 0x0B57 -#define mmHDP_SURFACE13_UPPER_BOUND 0x0B54 -#define mmHDP_SURFACE14_BASE 0x0B5B -#define mmHDP_SURFACE14_INFO 0x0B5C -#define mmHDP_SURFACE14_LOWER_BOUND 0x0B59 -#define mmHDP_SURFACE14_SIZE 0x0B5D -#define mmHDP_SURFACE14_UPPER_BOUND 0x0B5A -#define mmHDP_SURFACE15_BASE 0x0B61 -#define mmHDP_SURFACE15_INFO 0x0B62 -#define mmHDP_SURFACE15_LOWER_BOUND 0x0B5F -#define mmHDP_SURFACE15_SIZE 0x0B63 -#define mmHDP_SURFACE15_UPPER_BOUND 0x0B60 -#define mmHDP_SURFACE16_BASE 0x0B67 -#define mmHDP_SURFACE16_INFO 0x0B68 -#define mmHDP_SURFACE16_LOWER_BOUND 0x0B65 -#define mmHDP_SURFACE16_SIZE 0x0B69 -#define mmHDP_SURFACE16_UPPER_BOUND 0x0B66 -#define mmHDP_SURFACE17_BASE 0x0B6D -#define mmHDP_SURFACE17_INFO 0x0B6E -#define mmHDP_SURFACE17_LOWER_BOUND 0x0B6B -#define mmHDP_SURFACE17_SIZE 0x0B6F -#define mmHDP_SURFACE17_UPPER_BOUND 0x0B6C -#define mmHDP_SURFACE18_BASE 0x0B73 -#define mmHDP_SURFACE18_INFO 0x0B74 -#define mmHDP_SURFACE18_LOWER_BOUND 0x0B71 -#define mmHDP_SURFACE18_SIZE 0x0B75 -#define mmHDP_SURFACE18_UPPER_BOUND 0x0B72 -#define mmHDP_SURFACE19_BASE 0x0B79 -#define mmHDP_SURFACE19_INFO 0x0B7A -#define mmHDP_SURFACE19_LOWER_BOUND 0x0B77 -#define mmHDP_SURFACE19_SIZE 0x0B7B -#define mmHDP_SURFACE19_UPPER_BOUND 0x0B78 -#define mmHDP_SURFACE1_BASE 0x0B0D -#define mmHDP_SURFACE1_INFO 0x0B0E -#define mmHDP_SURFACE1_LOWER_BOUND 0x0B0B -#define mmHDP_SURFACE1_SIZE 0x0B0F -#define mmHDP_SURFACE1_UPPER_BOUND 0x0B0C -#define mmHDP_SURFACE20_BASE 0x0B7F -#define mmHDP_SURFACE20_INFO 0x0B80 -#define mmHDP_SURFACE20_LOWER_BOUND 0x0B7D -#define mmHDP_SURFACE20_SIZE 0x0B81 -#define mmHDP_SURFACE20_UPPER_BOUND 0x0B7E -#define mmHDP_SURFACE21_BASE 0x0B85 -#define mmHDP_SURFACE21_INFO 0x0B86 -#define mmHDP_SURFACE21_LOWER_BOUND 0x0B83 -#define mmHDP_SURFACE21_SIZE 0x0B87 -#define mmHDP_SURFACE21_UPPER_BOUND 0x0B84 -#define mmHDP_SURFACE22_BASE 0x0B8B -#define mmHDP_SURFACE22_INFO 0x0B8C -#define mmHDP_SURFACE22_LOWER_BOUND 0x0B89 -#define mmHDP_SURFACE22_SIZE 0x0B8D -#define mmHDP_SURFACE22_UPPER_BOUND 0x0B8A -#define mmHDP_SURFACE23_BASE 0x0B91 -#define mmHDP_SURFACE23_INFO 0x0B92 -#define mmHDP_SURFACE23_LOWER_BOUND 0x0B8F -#define mmHDP_SURFACE23_SIZE 0x0B93 -#define mmHDP_SURFACE23_UPPER_BOUND 0x0B90 -#define mmHDP_SURFACE24_BASE 0x0B97 -#define mmHDP_SURFACE24_INFO 0x0B98 -#define mmHDP_SURFACE24_LOWER_BOUND 0x0B95 -#define mmHDP_SURFACE24_SIZE 0x0B99 -#define mmHDP_SURFACE24_UPPER_BOUND 0x0B96 -#define mmHDP_SURFACE25_BASE 0x0B9D -#define mmHDP_SURFACE25_INFO 0x0B9E -#define mmHDP_SURFACE25_LOWER_BOUND 0x0B9B -#define mmHDP_SURFACE25_SIZE 0x0B9F -#define mmHDP_SURFACE25_UPPER_BOUND 0x0B9C -#define mmHDP_SURFACE26_BASE 0x0BA3 -#define mmHDP_SURFACE26_INFO 0x0BA4 -#define mmHDP_SURFACE26_LOWER_BOUND 0x0BA1 -#define mmHDP_SURFACE26_SIZE 0x0BA5 -#define mmHDP_SURFACE26_UPPER_BOUND 0x0BA2 -#define mmHDP_SURFACE27_BASE 0x0BA9 -#define mmHDP_SURFACE27_INFO 0x0BAA -#define mmHDP_SURFACE27_LOWER_BOUND 0x0BA7 -#define mmHDP_SURFACE27_SIZE 0x0BAB -#define mmHDP_SURFACE27_UPPER_BOUND 0x0BA8 -#define mmHDP_SURFACE28_BASE 0x0BAF -#define mmHDP_SURFACE28_INFO 0x0BB0 -#define mmHDP_SURFACE28_LOWER_BOUND 0x0BAD -#define mmHDP_SURFACE28_SIZE 0x0BB1 -#define mmHDP_SURFACE28_UPPER_BOUND 0x0BAE -#define mmHDP_SURFACE29_BASE 0x0BB5 -#define mmHDP_SURFACE29_INFO 0x0BB6 -#define mmHDP_SURFACE29_LOWER_BOUND 0x0BB3 -#define mmHDP_SURFACE29_SIZE 0x0BB7 -#define mmHDP_SURFACE29_UPPER_BOUND 0x0BB4 -#define mmHDP_SURFACE2_BASE 0x0B13 -#define mmHDP_SURFACE2_INFO 0x0B14 -#define mmHDP_SURFACE2_LOWER_BOUND 0x0B11 -#define mmHDP_SURFACE2_SIZE 0x0B15 -#define mmHDP_SURFACE2_UPPER_BOUND 0x0B12 -#define mmHDP_SURFACE30_BASE 0x0BBB -#define mmHDP_SURFACE30_INFO 0x0BBC -#define mmHDP_SURFACE30_LOWER_BOUND 0x0BB9 -#define mmHDP_SURFACE30_SIZE 0x0BBD -#define mmHDP_SURFACE30_UPPER_BOUND 0x0BBA -#define mmHDP_SURFACE31_BASE 0x0BC1 -#define mmHDP_SURFACE31_INFO 0x0BC2 -#define mmHDP_SURFACE31_LOWER_BOUND 0x0BBF -#define mmHDP_SURFACE31_SIZE 0x0BC3 -#define mmHDP_SURFACE31_UPPER_BOUND 0x0BC0 -#define mmHDP_SURFACE3_BASE 0x0B19 -#define mmHDP_SURFACE3_INFO 0x0B1A -#define mmHDP_SURFACE3_LOWER_BOUND 0x0B17 -#define mmHDP_SURFACE3_SIZE 0x0B1B -#define mmHDP_SURFACE3_UPPER_BOUND 0x0B18 -#define mmHDP_SURFACE4_BASE 0x0B1F -#define mmHDP_SURFACE4_INFO 0x0B20 -#define mmHDP_SURFACE4_LOWER_BOUND 0x0B1D -#define mmHDP_SURFACE4_SIZE 0x0B21 -#define mmHDP_SURFACE4_UPPER_BOUND 0x0B1E -#define mmHDP_SURFACE5_BASE 0x0B25 -#define mmHDP_SURFACE5_INFO 0x0B26 -#define mmHDP_SURFACE5_LOWER_BOUND 0x0B23 -#define mmHDP_SURFACE5_SIZE 0x0B27 -#define mmHDP_SURFACE5_UPPER_BOUND 0x0B24 -#define mmHDP_SURFACE6_BASE 0x0B2B -#define mmHDP_SURFACE6_INFO 0x0B2C -#define mmHDP_SURFACE6_LOWER_BOUND 0x0B29 -#define mmHDP_SURFACE6_SIZE 0x0B2D -#define mmHDP_SURFACE6_UPPER_BOUND 0x0B2A -#define mmHDP_SURFACE7_BASE 0x0B31 -#define mmHDP_SURFACE7_INFO 0x0B32 -#define mmHDP_SURFACE7_LOWER_BOUND 0x0B2F -#define mmHDP_SURFACE7_SIZE 0x0B33 -#define mmHDP_SURFACE7_UPPER_BOUND 0x0B30 -#define mmHDP_SURFACE8_BASE 0x0B37 -#define mmHDP_SURFACE8_INFO 0x0B38 -#define mmHDP_SURFACE8_LOWER_BOUND 0x0B35 -#define mmHDP_SURFACE8_SIZE 0x0B39 -#define mmHDP_SURFACE8_UPPER_BOUND 0x0B36 -#define mmHDP_SURFACE9_BASE 0x0B3D -#define mmHDP_SURFACE9_INFO 0x0B3E -#define mmHDP_SURFACE9_LOWER_BOUND 0x0B3B -#define mmHDP_SURFACE9_SIZE 0x0B3F -#define mmHDP_SURFACE9_UPPER_BOUND 0x0B3C -#define mmHDP_SURFACE_READ_FLAGS 0x0BC6 -#define mmHDP_SURFACE_READ_FLAGS_CLR 0x0BC8 -#define mmHDP_SURFACE_WRITE_FLAGS 0x0BC5 -#define mmHDP_SURFACE_WRITE_FLAGS_CLR 0x0BC7 -#define mmHDP_SW_SEMAPHORE 0x0BCB -#define mmHDP_TILING_CONFIG 0x0BCF -#define mmHDP_XDP_BUSY_STS 0x0C3E -#define mmHDP_XDP_CGTT_BLK_CTRL 0x0C33 -#define mmHDP_XDP_CHKN 0x0C40 -#define mmHDP_XDP_D2H_BAR_UPDATE 0x0C02 -#define mmHDP_XDP_D2H_FLUSH 0x0C01 -#define mmHDP_XDP_D2H_RSVD_10 0x0C0A -#define mmHDP_XDP_D2H_RSVD_11 0x0C0B -#define mmHDP_XDP_D2H_RSVD_12 0x0C0C -#define mmHDP_XDP_D2H_RSVD_13 0x0C0D -#define mmHDP_XDP_D2H_RSVD_14 0x0C0E -#define mmHDP_XDP_D2H_RSVD_15 0x0C0F -#define mmHDP_XDP_D2H_RSVD_16 0x0C10 -#define mmHDP_XDP_D2H_RSVD_17 0x0C11 -#define mmHDP_XDP_D2H_RSVD_18 0x0C12 -#define mmHDP_XDP_D2H_RSVD_19 0x0C13 -#define mmHDP_XDP_D2H_RSVD_20 0x0C14 -#define mmHDP_XDP_D2H_RSVD_21 0x0C15 -#define mmHDP_XDP_D2H_RSVD_22 0x0C16 -#define mmHDP_XDP_D2H_RSVD_23 0x0C17 -#define mmHDP_XDP_D2H_RSVD_24 0x0C18 -#define mmHDP_XDP_D2H_RSVD_25 0x0C19 -#define mmHDP_XDP_D2H_RSVD_26 0x0C1A -#define mmHDP_XDP_D2H_RSVD_27 0x0C1B -#define mmHDP_XDP_D2H_RSVD_28 0x0C1C -#define mmHDP_XDP_D2H_RSVD_29 0x0C1D -#define mmHDP_XDP_D2H_RSVD_3 0x0C03 -#define mmHDP_XDP_D2H_RSVD_30 0x0C1E -#define mmHDP_XDP_D2H_RSVD_31 0x0C1F -#define mmHDP_XDP_D2H_RSVD_32 0x0C20 -#define mmHDP_XDP_D2H_RSVD_33 0x0C21 -#define mmHDP_XDP_D2H_RSVD_34 0x0C22 -#define mmHDP_XDP_D2H_RSVD_4 0x0C04 -#define mmHDP_XDP_D2H_RSVD_5 0x0C05 -#define mmHDP_XDP_D2H_RSVD_6 0x0C06 -#define mmHDP_XDP_D2H_RSVD_7 0x0C07 -#define mmHDP_XDP_D2H_RSVD_8 0x0C08 -#define mmHDP_XDP_D2H_RSVD_9 0x0C09 -#define mmHDP_XDP_DBG_ADDR 0x0C41 -#define mmHDP_XDP_DBG_DATA 0x0C42 -#define mmHDP_XDP_DBG_MASK 0x0C43 -#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0C00 -#define mmHDP_XDP_DIRECT2HDP_LAST 0x0C23 -#define mmHDP_XDP_FLUSH_ARMED_STS 0x0C3C -#define mmHDP_XDP_FLUSH_CNTR0_STS 0x0C3D -#define mmHDP_XDP_HDP_IPH_CFG 0x0C31 -#define mmHDP_XDP_HDP_MBX_MC_CFG 0x0C2D -#define mmHDP_XDP_HDP_MC_CFG 0x0C2E -#define mmHDP_XDP_HST_CFG 0x0C2F -#define mmHDP_XDP_P2P_BAR0 0x0C34 -#define mmHDP_XDP_P2P_BAR1 0x0C35 -#define mmHDP_XDP_P2P_BAR2 0x0C36 -#define mmHDP_XDP_P2P_BAR3 0x0C37 -#define mmHDP_XDP_P2P_BAR4 0x0C38 -#define mmHDP_XDP_P2P_BAR5 0x0C39 -#define mmHDP_XDP_P2P_BAR6 0x0C3A -#define mmHDP_XDP_P2P_BAR7 0x0C3B -#define mmHDP_XDP_P2P_BAR_CFG 0x0C24 -#define mmHDP_XDP_P2P_MBX_ADDR0 0x0C26 -#define mmHDP_XDP_P2P_MBX_ADDR1 0x0C27 -#define mmHDP_XDP_P2P_MBX_ADDR2 0x0C28 -#define mmHDP_XDP_P2P_MBX_ADDR3 0x0C29 -#define mmHDP_XDP_P2P_MBX_ADDR4 0x0C2A -#define mmHDP_XDP_P2P_MBX_ADDR5 0x0C2B -#define mmHDP_XDP_P2P_MBX_ADDR6 0x0C2C -#define mmHDP_XDP_P2P_MBX_OFFSET 0x0C25 -#define mmHDP_XDP_SID_CFG 0x0C30 -#define mmHDP_XDP_SRBM_CFG 0x0C32 -#define mmHDP_XDP_STICKY 0x0C3F -#define mmHD_BACKPORCH_DUR__SI 0x17EC -#define mmHD_CGMS_TIMING__SI 0x17EE -#define mmHD_EMBEDDED_SYNC_CNTL__SI 0x17E8 -#define mmHD_INCR__SI 0x17E9 -#define mmHD_POS_SYNC_LEVEL__SI 0x17EB -#define mmHD_SERATION_DUR__SI 0x17ED -#define mmHD_TRILEVEL_DUR__SI 0x17EA -#define mmHOST_BUSNUM 0x153D -#define mmHW_DEBUG 0x1515 -#define mmI2C_CNTL_0__SI 0x02B8 -#define mmI2C_CNTL_1__SI 0x02B9 -#define mmI2C_DATA__SI 0x02BA -#define mmIA_CNTL_STATUS 0x2237 -#define mmIA_DEBUG_CNTL 0x223A -#define mmIA_DEBUG_DATA 0x223B -#define mmIA_ENHANCE 0xA29C -#define mmIA_MULTI_VGT_PARAM 0xA2AA -#define mmIA_PERFCOUNTER0_HI__CI__VI 0xD089 -#define mmIA_PERFCOUNTER0_HI__SI 0x2225 -#define mmIA_PERFCOUNTER0_LO__CI__VI 0xD088 -#define mmIA_PERFCOUNTER0_LO__SI 0x2224 -#define mmIA_PERFCOUNTER0_SELECT1__CI__VI 0xD888 -#define mmIA_PERFCOUNTER0_SELECT__CI__VI 0xD884 -#define mmIA_PERFCOUNTER0_SELECT__SI 0x2220 -#define mmIA_PERFCOUNTER1_HI__CI__VI 0xD08B -#define mmIA_PERFCOUNTER1_HI__SI 0x2227 -#define mmIA_PERFCOUNTER1_LO__CI__VI 0xD08A -#define mmIA_PERFCOUNTER1_LO__SI 0x2226 -#define mmIA_PERFCOUNTER1_SELECT__CI__VI 0xD885 -#define mmIA_PERFCOUNTER1_SELECT__SI 0x2221 -#define mmIA_PERFCOUNTER2_HI__CI__VI 0xD08D -#define mmIA_PERFCOUNTER2_HI__SI 0x2229 -#define mmIA_PERFCOUNTER2_LO__CI__VI 0xD08C -#define mmIA_PERFCOUNTER2_LO__SI 0x2228 -#define mmIA_PERFCOUNTER2_SELECT__CI__VI 0xD886 -#define mmIA_PERFCOUNTER2_SELECT__SI 0x2222 -#define mmIA_PERFCOUNTER3_HI__CI__VI 0xD08F -#define mmIA_PERFCOUNTER3_HI__SI 0x222B -#define mmIA_PERFCOUNTER3_LO__CI__VI 0xD08E -#define mmIA_PERFCOUNTER3_LO__SI 0x222A -#define mmIA_PERFCOUNTER3_SELECT__CI__VI 0xD887 -#define mmIA_PERFCOUNTER3_SELECT__SI 0x2223 -#define mmIA_VMID_OVERRIDE__SI__CI 0x2260 -#define mmICON_COLOR1__SI 0x1A74 -#define mmICON_COLOR2__SI 0x1A75 -#define mmICON_CONTROL__SI 0x1A6F -#define mmICON_SIZE__SI 0x1A71 -#define mmICON_START_POSITION__SI 0x1A73 -#define mmICON_SURFACE_ADDRESS_HIGH__SI 0x1A72 -#define mmICON_SURFACE_ADDRESS__SI 0x1A70 -#define mmICON_UPDATE__SI 0x1A76 -#define mmIDCT_AUTH0__SI 0x3C89 -#define mmIDCT_AUTH1__SI 0x3C8B -#define mmIDCT_AUTH2__SI 0x3C8D -#define mmIDCT_AUTH3__SI 0x3C8F -#define mmIDCT_AUTH_CONTROL0__SI 0x3C88 -#define mmIDCT_AUTH_CONTROL1__SI 0x3C8A -#define mmIDCT_AUTH_CONTROL2__SI 0x3C8C -#define mmIDCT_AUTH_CONTROL3__SI 0x3C8E -#define mmIDCT_COEF_BASE__SI 0x3809 -#define mmIDCT_COEF_DATA__SI 0x3807 -#define mmIDCT_CONFIG__SI 0x0F94 -#define mmIDCT_CONTROL__SI 0x380A -#define mmIDCT_CURRENT_MB_STATUS_DEBUG__SI 0x3CA0 -#define mmIDCT_DRM_CONTROL_STATUS__SI 0x3CA2 -#define mmIDCT_DRM_WR_CREDIT__SI 0x3CA1 -#define mmIDCT_EOB_ERROR_STATUS__SI 0x3801 -#define mmIDCT_PIO_MODE_XY__SI 0x3896 -#define mmIDCT_SCRAMBLE_SELECT__SI 0x3803 -#define mmIDCT_SCRATCH__SI 0x3804 -#define mmIDCT_SPAN__SI 0x3805 -#define mmIDCT_STATUS__SI 0x3808 -#define mmIDCT_STREAM_ID__SI 0x3802 -#define mmIDCT_TEST_DEBUG_DATA__SI 0x3C9C -#define mmIDCT_TEST_DEBUG_INDEX__SI 0x3C9B -#define mmIH_ADVFAULT_CNTL__SI__CI 0x0F8C -#define mmIH_PERFCOUNTER0_RESULT__CI 0x0F8A -#define mmIH_PERFCOUNTER1_RESULT__CI 0x0F8B -#define mmIH_PERFMON_CNTL__CI 0x0F89 -#define mmIH_PERF_CNTL__SI 0x0F89 -#define mmIH_PERF_COUNT0__SI 0x0F8A -#define mmIH_PERF_COUNT1__SI 0x0F8B -#define mmIH_VMID_0_LUT__CI 0x0F50 -#define mmIH_VMID_10_LUT__CI 0x0F5A -#define mmIH_VMID_11_LUT__CI 0x0F5B -#define mmIH_VMID_12_LUT__CI 0x0F5C -#define mmIH_VMID_13_LUT__CI 0x0F5D -#define mmIH_VMID_14_LUT__CI 0x0F5E -#define mmIH_VMID_15_LUT__CI 0x0F5F -#define mmIH_VMID_1_LUT__CI 0x0F51 -#define mmIH_VMID_2_LUT__CI 0x0F52 -#define mmIH_VMID_3_LUT__CI 0x0F53 -#define mmIH_VMID_4_LUT__CI 0x0F54 -#define mmIH_VMID_5_LUT__CI 0x0F55 -#define mmIH_VMID_6_LUT__CI 0x0F56 -#define mmIH_VMID_7_LUT__CI 0x0F57 -#define mmIH_VMID_8_LUT__CI 0x0F58 -#define mmIH_VMID_9_LUT__CI 0x0F59 -#define mmIMPCTL_RESET__CI__VI 0x14F5 -#define mmIM_INT_EN__SI 0x3E40 -#define mmIM_INT_STAT__SI 0x3E41 -#define mmINTERRUPT_CNTL 0x151A -#define mmINTERRUPT_CNTL2 0x151B -#define mmINT_MASK__SI 0x1AD0 -#define mmIOU_SMC_IND_DATA__CI__VI 0x0081 -#define mmIOU_SMC_IND_DATA_alt_1__CI__VI 0x0083 -#define mmIOU_SMC_IND_DATA_alt_2__CI__VI 0x0085 -#define mmIOU_SMC_IND_DATA_alt_3__CI__VI 0x0087 -#define mmIOU_SMC_IND_INDEX__CI__VI 0x0080 -#define mmIOU_SMC_IND_INDEX_alt_1__CI__VI 0x0082 -#define mmIOU_SMC_IND_INDEX_alt_2__CI__VI 0x0084 -#define mmIOU_SMC_IND_INDEX_alt_3__CI__VI 0x0086 -#define mmIT_BUF_SIZE__SI 0x3F44 -#define mmIT_CF_DAT__SI 0x3F49 -#define mmIT_CTL__SI 0x3F42 -#define mmIT_DEBUG_BUS__SI 0x3F53 -#define mmIT_DEBUG_INT_STAT__SI 0x3F4E -#define mmIT_HW_DEBUG__SI 0x3F52 -#define mmIT_INTRA_HOR_ADR__SI 0x3F45 -#define mmIT_INT_EN__SI 0x3F40 -#define mmIT_INT_STAT__SI 0x3F41 -#define mmIT_LMA_ADR__SI 0x3F4B -#define mmIT_LMA_CTL__SI 0x3F4A -#define mmIT_LMA_DAT__SI 0x3F4C -#define mmIT_PPS_INFO__SI 0x3F47 -#define mmIT_SLICE_INFO__SI 0x3F48 -#define mmIT_SPS_INFO__SI 0x3F46 -#define mmIT_SRAM_RM_CTL__SI 0x3F4D -#define mmIT_STAT__SI 0x3F43 -#define mmLB0_AVP_BCKN_OVL__SI 0x1AF5 -#define mmLB0_DATA_FORMAT__SI 0x1AC0 -#define mmLB0_DC_FID_CNT__SI 0x1ACF -#define mmLB0_DC_LB_BLACK_KEYER_B__SI 0x1AD3 -#define mmLB0_DC_LB_BLACK_KEYER_G__SI 0x1AD2 -#define mmLB0_DC_LB_BLACK_KEYER_R__SI 0x1AD1 -#define mmLB0_DC_LB_MEMORY_SPLIT__SI 0x1AC3 -#define mmLB0_DC_LB_MEM_SIZE__SI 0x1AC4 -#define mmLB0_DC_MVP_LB_CONTROL__SI 0x1ADB -#define mmLB0_DC_STUTTER_CNTL__SI 0x1ACC -#define mmLB0_DC_STUTTER_STATUS__SI 0x1AF3 -#define mmLB0_DESKTOP_HEIGHT__SI 0x1AC1 -#define mmLB0_INT_MASK__SI 0x1AD0 -#define mmLB0_LB_DEBUG_PRE_ECO__SI 0x1AFD -#define mmLB0_LB_DEBUG__SI 0x1AFC -#define mmLB0_LB_MAX_REQ_OUTSTANDING__SI 0x1AC8 -#define mmLB0_LB_SLOW_REQ_VAL__SI 0x1AC9 -#define mmLB0_LB_SYNC_RESET_SEL__SI 0x1ACA -#define mmLB0_LB_TEST_DEBUG_DATA__SI 0x1AFF -#define mmLB0_LB_TEST_DEBUG_INDEX__SI 0x1AFE -#define mmLB0_LB_URGENT_LEVEL_CNTL__SI 0x1AC5 -#define mmLB0_MCLK_CHG_CNT__SI 0x1ACB -#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL__SI 0x1AD9 -#define mmLB0_MVP_AFR_FLIP_MODE__SI 0x1AD8 -#define mmLB0_MVP_FLIP_LINE_NUM_INSERT__SI 0x1ADA -#define mmLB0_OVL_RT_BAND_POSITION__SI 0x1AD6 -#define mmLB0_OVL_RT_PROCEED_COND__SI 0x1AD7 -#define mmLB0_OVL_RT_SKEWCOMMAND__SI 0x1AD4 -#define mmLB0_OVL_RT_SKEWCONTROL__SI 0x1AD5 -#define mmLB0_OVL_RT_STAT__SI 0x1AF4 -#define mmLB0_PRIORITY_A_CNT__SI 0x1AC6 -#define mmLB0_PRIORITY_B_CNT__SI 0x1AC7 -#define mmLB0_REQ_FIFO_STAT__SI 0x1AF2 -#define mmLB0_SNAPSHOT_V_COUNTER__SI 0x1AED -#define mmLB0_STUTTER_A_CNT__SI 0x1ACD -#define mmLB0_STUTTER_B_CNT__SI 0x1ACE -#define mmLB0_UNDERFLOW_STATUS__SI 0x1AF0 -#define mmLB0_URGENCY_STAT__SI 0x1AF1 -#define mmLB0_VBLANK_STATUS__SI 0x1AEF -#define mmLB0_VLINE_START_END__SI 0x1AC2 -#define mmLB0_VLINE_STATUS__SI 0x1AEE -#define mmLB0_V_COUNTER__SI 0x1AEC -#define mmLB1_AVP_BCKN_OVL__SI 0x1DF5 -#define mmLB1_DATA_FORMAT__SI 0x1DC0 -#define mmLB1_DC_FID_CNT__SI 0x1DCF -#define mmLB1_DC_LB_BLACK_KEYER_B__SI 0x1DD3 -#define mmLB1_DC_LB_BLACK_KEYER_G__SI 0x1DD2 -#define mmLB1_DC_LB_BLACK_KEYER_R__SI 0x1DD1 -#define mmLB1_DC_LB_MEMORY_SPLIT__SI 0x1DC3 -#define mmLB1_DC_LB_MEM_SIZE__SI 0x1DC4 -#define mmLB1_DC_MVP_LB_CONTROL__SI 0x1DDB -#define mmLB1_DC_STUTTER_CNTL__SI 0x1DCC -#define mmLB1_DC_STUTTER_STATUS__SI 0x1DF3 -#define mmLB1_DESKTOP_HEIGHT__SI 0x1DC1 -#define mmLB1_INT_MASK__SI 0x1DD0 -#define mmLB1_LB_DEBUG_PRE_ECO__SI 0x1DFD -#define mmLB1_LB_DEBUG__SI 0x1DFC -#define mmLB1_LB_MAX_REQ_OUTSTANDING__SI 0x1DC8 -#define mmLB1_LB_SLOW_REQ_VAL__SI 0x1DC9 -#define mmLB1_LB_SYNC_RESET_SEL__SI 0x1DCA -#define mmLB1_LB_TEST_DEBUG_DATA__SI 0x1DFF -#define mmLB1_LB_TEST_DEBUG_INDEX__SI 0x1DFE -#define mmLB1_LB_URGENT_LEVEL_CNTL__SI 0x1DC5 -#define mmLB1_MCLK_CHG_CNT__SI 0x1DCB -#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL__SI 0x1DD9 -#define mmLB1_MVP_AFR_FLIP_MODE__SI 0x1DD8 -#define mmLB1_MVP_FLIP_LINE_NUM_INSERT__SI 0x1DDA -#define mmLB1_OVL_RT_BAND_POSITION__SI 0x1DD6 -#define mmLB1_OVL_RT_PROCEED_COND__SI 0x1DD7 -#define mmLB1_OVL_RT_SKEWCOMMAND__SI 0x1DD4 -#define mmLB1_OVL_RT_SKEWCONTROL__SI 0x1DD5 -#define mmLB1_OVL_RT_STAT__SI 0x1DF4 -#define mmLB1_PRIORITY_A_CNT__SI 0x1DC6 -#define mmLB1_PRIORITY_B_CNT__SI 0x1DC7 -#define mmLB1_REQ_FIFO_STAT__SI 0x1DF2 -#define mmLB1_SNAPSHOT_V_COUNTER__SI 0x1DED -#define mmLB1_STUTTER_A_CNT__SI 0x1DCD -#define mmLB1_STUTTER_B_CNT__SI 0x1DCE -#define mmLB1_UNDERFLOW_STATUS__SI 0x1DF0 -#define mmLB1_URGENCY_STAT__SI 0x1DF1 -#define mmLB1_VBLANK_STATUS__SI 0x1DEF -#define mmLB1_VLINE_START_END__SI 0x1DC2 -#define mmLB1_VLINE_STATUS__SI 0x1DEE -#define mmLB1_V_COUNTER__SI 0x1DEC -#define mmLB2_AVP_BCKN_OVL__SI 0x40F5 -#define mmLB2_DATA_FORMAT__SI 0x40C0 -#define mmLB2_DC_FID_CNT__SI 0x40CF -#define mmLB2_DC_LB_BLACK_KEYER_B__SI 0x40D3 -#define mmLB2_DC_LB_BLACK_KEYER_G__SI 0x40D2 -#define mmLB2_DC_LB_BLACK_KEYER_R__SI 0x40D1 -#define mmLB2_DC_LB_MEMORY_SPLIT__SI 0x40C3 -#define mmLB2_DC_LB_MEM_SIZE__SI 0x40C4 -#define mmLB2_DC_MVP_LB_CONTROL__SI 0x40DB -#define mmLB2_DC_STUTTER_CNTL__SI 0x40CC -#define mmLB2_DC_STUTTER_STATUS__SI 0x40F3 -#define mmLB2_DESKTOP_HEIGHT__SI 0x40C1 -#define mmLB2_INT_MASK__SI 0x40D0 -#define mmLB2_LB_DEBUG_PRE_ECO__SI 0x40FD -#define mmLB2_LB_DEBUG__SI 0x40FC -#define mmLB2_LB_MAX_REQ_OUTSTANDING__SI 0x40C8 -#define mmLB2_LB_SLOW_REQ_VAL__SI 0x40C9 -#define mmLB2_LB_SYNC_RESET_SEL__SI 0x40CA -#define mmLB2_LB_TEST_DEBUG_DATA__SI 0x40FF -#define mmLB2_LB_TEST_DEBUG_INDEX__SI 0x40FE -#define mmLB2_LB_URGENT_LEVEL_CNTL__SI 0x40C5 -#define mmLB2_MCLK_CHG_CNT__SI 0x40CB -#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL__SI 0x40D9 -#define mmLB2_MVP_AFR_FLIP_MODE__SI 0x40D8 -#define mmLB2_MVP_FLIP_LINE_NUM_INSERT__SI 0x40DA -#define mmLB2_OVL_RT_BAND_POSITION__SI 0x40D6 -#define mmLB2_OVL_RT_PROCEED_COND__SI 0x40D7 -#define mmLB2_OVL_RT_SKEWCOMMAND__SI 0x40D4 -#define mmLB2_OVL_RT_SKEWCONTROL__SI 0x40D5 -#define mmLB2_OVL_RT_STAT__SI 0x40F4 -#define mmLB2_PRIORITY_A_CNT__SI 0x40C6 -#define mmLB2_PRIORITY_B_CNT__SI 0x40C7 -#define mmLB2_REQ_FIFO_STAT__SI 0x40F2 -#define mmLB2_SNAPSHOT_V_COUNTER__SI 0x40ED -#define mmLB2_STUTTER_A_CNT__SI 0x40CD -#define mmLB2_STUTTER_B_CNT__SI 0x40CE -#define mmLB2_UNDERFLOW_STATUS__SI 0x40F0 -#define mmLB2_URGENCY_STAT__SI 0x40F1 -#define mmLB2_VBLANK_STATUS__SI 0x40EF -#define mmLB2_VLINE_START_END__SI 0x40C2 -#define mmLB2_VLINE_STATUS__SI 0x40EE -#define mmLB2_V_COUNTER__SI 0x40EC -#define mmLB3_AVP_BCKN_OVL__SI 0x43F5 -#define mmLB3_DATA_FORMAT__SI 0x43C0 -#define mmLB3_DC_FID_CNT__SI 0x43CF -#define mmLB3_DC_LB_BLACK_KEYER_B__SI 0x43D3 -#define mmLB3_DC_LB_BLACK_KEYER_G__SI 0x43D2 -#define mmLB3_DC_LB_BLACK_KEYER_R__SI 0x43D1 -#define mmLB3_DC_LB_MEMORY_SPLIT__SI 0x43C3 -#define mmLB3_DC_LB_MEM_SIZE__SI 0x43C4 -#define mmLB3_DC_MVP_LB_CONTROL__SI 0x43DB -#define mmLB3_DC_STUTTER_CNTL__SI 0x43CC -#define mmLB3_DC_STUTTER_STATUS__SI 0x43F3 -#define mmLB3_DESKTOP_HEIGHT__SI 0x43C1 -#define mmLB3_INT_MASK__SI 0x43D0 -#define mmLB3_LB_DEBUG_PRE_ECO__SI 0x43FD -#define mmLB3_LB_DEBUG__SI 0x43FC -#define mmLB3_LB_MAX_REQ_OUTSTANDING__SI 0x43C8 -#define mmLB3_LB_SLOW_REQ_VAL__SI 0x43C9 -#define mmLB3_LB_SYNC_RESET_SEL__SI 0x43CA -#define mmLB3_LB_TEST_DEBUG_DATA__SI 0x43FF -#define mmLB3_LB_TEST_DEBUG_INDEX__SI 0x43FE -#define mmLB3_LB_URGENT_LEVEL_CNTL__SI 0x43C5 -#define mmLB3_MCLK_CHG_CNT__SI 0x43CB -#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL__SI 0x43D9 -#define mmLB3_MVP_AFR_FLIP_MODE__SI 0x43D8 -#define mmLB3_MVP_FLIP_LINE_NUM_INSERT__SI 0x43DA -#define mmLB3_OVL_RT_BAND_POSITION__SI 0x43D6 -#define mmLB3_OVL_RT_PROCEED_COND__SI 0x43D7 -#define mmLB3_OVL_RT_SKEWCOMMAND__SI 0x43D4 -#define mmLB3_OVL_RT_SKEWCONTROL__SI 0x43D5 -#define mmLB3_OVL_RT_STAT__SI 0x43F4 -#define mmLB3_PRIORITY_A_CNT__SI 0x43C6 -#define mmLB3_PRIORITY_B_CNT__SI 0x43C7 -#define mmLB3_REQ_FIFO_STAT__SI 0x43F2 -#define mmLB3_SNAPSHOT_V_COUNTER__SI 0x43ED -#define mmLB3_STUTTER_A_CNT__SI 0x43CD -#define mmLB3_STUTTER_B_CNT__SI 0x43CE -#define mmLB3_UNDERFLOW_STATUS__SI 0x43F0 -#define mmLB3_URGENCY_STAT__SI 0x43F1 -#define mmLB3_VBLANK_STATUS__SI 0x43EF -#define mmLB3_VLINE_START_END__SI 0x43C2 -#define mmLB3_VLINE_STATUS__SI 0x43EE -#define mmLB3_V_COUNTER__SI 0x43EC -#define mmLB4_AVP_BCKN_OVL__SI 0x46F5 -#define mmLB4_DATA_FORMAT__SI 0x46C0 -#define mmLB4_DC_FID_CNT__SI 0x46CF -#define mmLB4_DC_LB_BLACK_KEYER_B__SI 0x46D3 -#define mmLB4_DC_LB_BLACK_KEYER_G__SI 0x46D2 -#define mmLB4_DC_LB_BLACK_KEYER_R__SI 0x46D1 -#define mmLB4_DC_LB_MEMORY_SPLIT__SI 0x46C3 -#define mmLB4_DC_LB_MEM_SIZE__SI 0x46C4 -#define mmLB4_DC_MVP_LB_CONTROL__SI 0x46DB -#define mmLB4_DC_STUTTER_CNTL__SI 0x46CC -#define mmLB4_DC_STUTTER_STATUS__SI 0x46F3 -#define mmLB4_DESKTOP_HEIGHT__SI 0x46C1 -#define mmLB4_INT_MASK__SI 0x46D0 -#define mmLB4_LB_DEBUG_PRE_ECO__SI 0x46FD -#define mmLB4_LB_DEBUG__SI 0x46FC -#define mmLB4_LB_MAX_REQ_OUTSTANDING__SI 0x46C8 -#define mmLB4_LB_SLOW_REQ_VAL__SI 0x46C9 -#define mmLB4_LB_SYNC_RESET_SEL__SI 0x46CA -#define mmLB4_LB_TEST_DEBUG_DATA__SI 0x46FF -#define mmLB4_LB_TEST_DEBUG_INDEX__SI 0x46FE -#define mmLB4_LB_URGENT_LEVEL_CNTL__SI 0x46C5 -#define mmLB4_MCLK_CHG_CNT__SI 0x46CB -#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL__SI 0x46D9 -#define mmLB4_MVP_AFR_FLIP_MODE__SI 0x46D8 -#define mmLB4_MVP_FLIP_LINE_NUM_INSERT__SI 0x46DA -#define mmLB4_OVL_RT_BAND_POSITION__SI 0x46D6 -#define mmLB4_OVL_RT_PROCEED_COND__SI 0x46D7 -#define mmLB4_OVL_RT_SKEWCOMMAND__SI 0x46D4 -#define mmLB4_OVL_RT_SKEWCONTROL__SI 0x46D5 -#define mmLB4_OVL_RT_STAT__SI 0x46F4 -#define mmLB4_PRIORITY_A_CNT__SI 0x46C6 -#define mmLB4_PRIORITY_B_CNT__SI 0x46C7 -#define mmLB4_REQ_FIFO_STAT__SI 0x46F2 -#define mmLB4_SNAPSHOT_V_COUNTER__SI 0x46ED -#define mmLB4_STUTTER_A_CNT__SI 0x46CD -#define mmLB4_STUTTER_B_CNT__SI 0x46CE -#define mmLB4_UNDERFLOW_STATUS__SI 0x46F0 -#define mmLB4_URGENCY_STAT__SI 0x46F1 -#define mmLB4_VBLANK_STATUS__SI 0x46EF -#define mmLB4_VLINE_START_END__SI 0x46C2 -#define mmLB4_VLINE_STATUS__SI 0x46EE -#define mmLB4_V_COUNTER__SI 0x46EC -#define mmLB5_AVP_BCKN_OVL__SI 0x49F5 -#define mmLB5_DATA_FORMAT__SI 0x49C0 -#define mmLB5_DC_FID_CNT__SI 0x49CF -#define mmLB5_DC_LB_BLACK_KEYER_B__SI 0x49D3 -#define mmLB5_DC_LB_BLACK_KEYER_G__SI 0x49D2 -#define mmLB5_DC_LB_BLACK_KEYER_R__SI 0x49D1 -#define mmLB5_DC_LB_MEMORY_SPLIT__SI 0x49C3 -#define mmLB5_DC_LB_MEM_SIZE__SI 0x49C4 -#define mmLB5_DC_MVP_LB_CONTROL__SI 0x49DB -#define mmLB5_DC_STUTTER_CNTL__SI 0x49CC -#define mmLB5_DC_STUTTER_STATUS__SI 0x49F3 -#define mmLB5_DESKTOP_HEIGHT__SI 0x49C1 -#define mmLB5_INT_MASK__SI 0x49D0 -#define mmLB5_LB_DEBUG_PRE_ECO__SI 0x49FD -#define mmLB5_LB_DEBUG__SI 0x49FC -#define mmLB5_LB_MAX_REQ_OUTSTANDING__SI 0x49C8 -#define mmLB5_LB_SLOW_REQ_VAL__SI 0x49C9 -#define mmLB5_LB_SYNC_RESET_SEL__SI 0x49CA -#define mmLB5_LB_TEST_DEBUG_DATA__SI 0x49FF -#define mmLB5_LB_TEST_DEBUG_INDEX__SI 0x49FE -#define mmLB5_LB_URGENT_LEVEL_CNTL__SI 0x49C5 -#define mmLB5_MCLK_CHG_CNT__SI 0x49CB -#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL__SI 0x49D9 -#define mmLB5_MVP_AFR_FLIP_MODE__SI 0x49D8 -#define mmLB5_MVP_FLIP_LINE_NUM_INSERT__SI 0x49DA -#define mmLB5_OVL_RT_BAND_POSITION__SI 0x49D6 -#define mmLB5_OVL_RT_PROCEED_COND__SI 0x49D7 -#define mmLB5_OVL_RT_SKEWCOMMAND__SI 0x49D4 -#define mmLB5_OVL_RT_SKEWCONTROL__SI 0x49D5 -#define mmLB5_OVL_RT_STAT__SI 0x49F4 -#define mmLB5_PRIORITY_A_CNT__SI 0x49C6 -#define mmLB5_PRIORITY_B_CNT__SI 0x49C7 -#define mmLB5_REQ_FIFO_STAT__SI 0x49F2 -#define mmLB5_SNAPSHOT_V_COUNTER__SI 0x49ED -#define mmLB5_STUTTER_A_CNT__SI 0x49CD -#define mmLB5_STUTTER_B_CNT__SI 0x49CE -#define mmLB5_UNDERFLOW_STATUS__SI 0x49F0 -#define mmLB5_URGENCY_STAT__SI 0x49F1 -#define mmLB5_VBLANK_STATUS__SI 0x49EF -#define mmLB5_VLINE_START_END__SI 0x49C2 -#define mmLB5_VLINE_STATUS__SI 0x49EE -#define mmLB5_V_COUNTER__SI 0x49EC -#define mmLB_DEBUG_PRE_ECO__SI 0x1AFD -#define mmLB_DEBUG__SI 0x1AFC -#define mmLB_MAX_REQ_OUTSTANDING__SI 0x1AC8 -#define mmLB_SLOW_REQ_VAL__SI 0x1AC9 -#define mmLB_SYNC_RESET_SEL__SI 0x1ACA -#define mmLB_TEST_DEBUG_DATA__SI 0x1AFF -#define mmLB_TEST_DEBUG_INDEX__SI 0x1AFE -#define mmLB_URGENT_LEVEL_CNTL__SI 0x1AC5 -#define mmLNCNT_CONTROL__CI 0x1487 -#define mmLUMA_BOT_ADDR__SI 0x388A -#define mmLUMA_TOP_ADDR__SI 0x3889 -#define mmLVDSA_PREEMPHASIS_CONTROL__SI 0x195F -#define mmLVDSA_TRANSMITTER_ADJUST__SI 0x195E -#define mmLVDSB_PREEMPHASIS_CONTROL__SI 0x1961 -#define mmLVDSB_TRANSMITTER_ADJUST__SI 0x1960 -#define mmLVDS_DATA_CNTL__SI 0x1C8C -#define mmLVTMA_PWRSEQ_CNTL__SI 0x1962 -#define mmLVTMA_PWRSEQ_DELAY1__SI 0x1965 -#define mmLVTMA_PWRSEQ_DELAY2__SI 0x1966 -#define mmLVTMA_PWRSEQ_REF_DIV__SI 0x1964 -#define mmLVTMA_PWRSEQ_STATE__SI 0x1963 -#define mmMASTER_COMM_CMD_REG__SI 0x161F -#define mmMASTER_COMM_CNTL_REG__SI 0x1620 -#define mmMASTER_COMM_DATA_REG1__SI 0x161C -#define mmMASTER_COMM_DATA_REG2__SI 0x161D -#define mmMASTER_COMM_DATA_REG3__SI 0x161E -#define mmMASTER_CREDIT_CNTL 0x1516 -#define mmMASTER_UPDATE_LOCK__SI 0x1BBD -#define mmMASTER_UPDATE_MODE__SI 0x1BBE -#define mmMB_DONE__SI 0x3882 -#define mmMCIF_CONTROL__SI 0x0314 -#define mmMCIF_TEST_DEBUG_DATA__SI 0x0317 -#define mmMCIF_TEST_DEBUG_INDEX__SI 0x0316 -#define mmMCIF_WRITE_COMBINE_CONTROL__SI 0x0315 -#define mmMCLK_CHG_CNT__SI 0x1ACB -#define mmMCLK_PWRMGT_CNTL__SI__CI 0x0AE8 -#define mmMC_ARB_ADDR_HASH 0x09DC -#define mmMC_ARB_ADDR_SWIZ0__CI__VI 0x09CB -#define mmMC_ARB_ADDR_SWIZ1__CI__VI 0x09CC -#define mmMC_ARB_AGE_CNTL__CI__VI 0x09BF -#define mmMC_ARB_AGE_RD 0x09E9 -#define mmMC_ARB_AGE_WR 0x09EA -#define mmMC_ARB_BANKMAP 0x09D7 -#define mmMC_ARB_BURST_TIME 0x0A02 -#define mmMC_ARB_BUSY_STATUS__CI__VI 0x09FD -#define mmMC_ARB_CAC_CNTL 0x09D4 -#define mmMC_ARB_CG 0x09FA -#define mmMC_ARB_DRAM_TIMING 0x09DD -#define mmMC_ARB_DRAM_TIMING2 0x09DE -#define mmMC_ARB_DRAM_TIMING2_1 0x09FF -#define mmMC_ARB_DRAM_TIMING2_2__SI 0x0A00 -#define mmMC_ARB_DRAM_TIMING2_3__SI 0x0A01 -#define mmMC_ARB_DRAM_TIMING_1 0x09FC -#define mmMC_ARB_DRAM_TIMING_2__SI 0x09FD -#define mmMC_ARB_DRAM_TIMING_3__SI 0x09FE -#define mmMC_ARB_FED_CNTL 0x09C1 -#define mmMC_ARB_GDEC_RD_CNTL 0x09EE -#define mmMC_ARB_GDEC_WR_CNTL 0x09EF -#define mmMC_ARB_GECC2 0x09C9 -#define mmMC_ARB_GECC2_CLI 0x09CA -#define mmMC_ARB_GECC2_DEBUG 0x09C4 -#define mmMC_ARB_GECC2_DEBUG2 0x09C5 -#define mmMC_ARB_GECC2_MISC 0x09C3 -#define mmMC_ARB_GECC2_STATUS 0x09C2 -#define mmMC_ARB_HARSH_BWCNT0_RD__CI__VI 0x0DCE -#define mmMC_ARB_HARSH_BWCNT0_WR__CI__VI 0x0DCF -#define mmMC_ARB_HARSH_BWCNT1_RD__CI__VI 0x0DD0 -#define mmMC_ARB_HARSH_BWCNT1_WR__CI__VI 0x0DD1 -#define mmMC_ARB_HARSH_BWPERIOD0_RD__CI__VI 0x0DCA -#define mmMC_ARB_HARSH_BWPERIOD0_WR__CI__VI 0x0DCB -#define mmMC_ARB_HARSH_BWPERIOD1_RD__CI__VI 0x0DCC -#define mmMC_ARB_HARSH_BWPERIOD1_WR__CI__VI 0x0DCD -#define mmMC_ARB_HARSH_CTL_RD__CI__VI 0x0DD6 -#define mmMC_ARB_HARSH_CTL_WR__CI__VI 0x0DD7 -#define mmMC_ARB_HARSH_EN_RD__CI__VI 0x0DC0 -#define mmMC_ARB_HARSH_EN_WR__CI__VI 0x0DC1 -#define mmMC_ARB_HARSH_SAT0_RD__CI__VI 0x0DD2 -#define mmMC_ARB_HARSH_SAT0_WR__CI__VI 0x0DD3 -#define mmMC_ARB_HARSH_SAT1_RD__CI__VI 0x0DD4 -#define mmMC_ARB_HARSH_SAT1_WR__CI__VI 0x0DD5 -#define mmMC_ARB_HARSH_TX_HI0_RD__CI__VI 0x0DC2 -#define mmMC_ARB_HARSH_TX_HI0_WR__CI__VI 0x0DC3 -#define mmMC_ARB_HARSH_TX_HI1_RD__CI__VI 0x0DC4 -#define mmMC_ARB_HARSH_TX_HI1_WR__CI__VI 0x0DC5 -#define mmMC_ARB_HARSH_TX_LO0_RD__CI__VI 0x0DC6 -#define mmMC_ARB_HARSH_TX_LO0_WR__CI__VI 0x0DC7 -#define mmMC_ARB_HARSH_TX_LO1_RD__CI__VI 0x0DC8 -#define mmMC_ARB_HARSH_TX_LO1_WR__CI__VI 0x0DC9 -#define mmMC_ARB_LAZY0_RD 0x09E5 -#define mmMC_ARB_LAZY0_WR 0x09E6 -#define mmMC_ARB_LAZY1_RD 0x09E7 -#define mmMC_ARB_LAZY1_WR 0x09E8 -#define mmMC_ARB_LM_RD 0x09F0 -#define mmMC_ARB_LM_WR 0x09F1 -#define mmMC_ARB_MAX_LAT_CID__CI__VI 0x09F6 -#define mmMC_ARB_MAX_LAT_RSLT0__CI__VI 0x09F7 -#define mmMC_ARB_MAX_LAT_RSLT1__CI__VI 0x09F8 -#define mmMC_ARB_MINCLKS 0x09DA -#define mmMC_ARB_MISC 0x09D6 -#define mmMC_ARB_MISC2 0x09D5 -#define mmMC_ARB_MISC3__CI__VI 0x09CD -#define mmMC_ARB_PERFCOUNTER0_CFG__CI__VI 0x07BC -#define mmMC_ARB_PERFCOUNTER1_CFG__CI__VI 0x07BD -#define mmMC_ARB_PERFCOUNTER2_CFG__CI__VI 0x07BE -#define mmMC_ARB_PERFCOUNTER3_CFG__CI__VI 0x07BF -#define mmMC_ARB_PERFCOUNTER_HI__CI__VI 0x07AE -#define mmMC_ARB_PERFCOUNTER_LO__CI__VI 0x07A6 -#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07D4 -#define mmMC_ARB_PERF_MON_CNTL0_ECC__CI 0x07DB -#define mmMC_ARB_PERF_MON_CNTL0__SI 0x09F6 -#define mmMC_ARB_PERF_MON_CNTL1__SI 0x09F7 -#define mmMC_ARB_PERF_MON_CNTL2__SI 0x09C6 -#define mmMC_ARB_PERF_MON_RSLT0__SI 0x09F8 -#define mmMC_ARB_PERF_MON_RSLT1__SI 0x09F9 -#define mmMC_ARB_PERF_MON_RSLT2__SI 0x09C7 -#define mmMC_ARB_PERF_MON_RSLT3__SI 0x09C8 -#define mmMC_ARB_PM_CNTL 0x09ED -#define mmMC_ARB_POP 0x09D9 -#define mmMC_ARB_RAMCFG 0x09D8 -#define mmMC_ARB_REFRESH_SCALE_CNTL__SI 0x018A -#define mmMC_ARB_REMREQ 0x09F2 -#define mmMC_ARB_REPLAY 0x09F3 -#define mmMC_ARB_RET_CREDITS2__CI__VI 0x09C0 -#define mmMC_ARB_RET_CREDITS_RD 0x09F4 -#define mmMC_ARB_RET_CREDITS_WR 0x09F5 -#define mmMC_ARB_RFSH_CNTL 0x09EB -#define mmMC_ARB_RFSH_RATE 0x09EC -#define mmMC_ARB_RSV0__SI 0x09CD -#define mmMC_ARB_RTT_CNTL0 0x09D0 -#define mmMC_ARB_RTT_CNTL1 0x09D1 -#define mmMC_ARB_RTT_CNTL2 0x09D2 -#define mmMC_ARB_RTT_DATA 0x09CF -#define mmMC_ARB_RTT_DEBUG 0x09D3 -#define mmMC_ARB_SCRAMBLE_KEY0 0x0A03 -#define mmMC_ARB_SCRAMBLE_KEY1 0x0A04 -#define mmMC_ARB_SPARE0__SI 0x09CB -#define mmMC_ARB_SPARE1__SI 0x09CC -#define mmMC_ARB_SQM_CNTL 0x09DB -#define mmMC_ARB_SSM__CI 0x09F9 -#define mmMC_ARB_TM_CNTL_RD 0x09E3 -#define mmMC_ARB_TM_CNTL_WR 0x09E4 -#define mmMC_ARB_WCDR__SI__CI 0x09FB -#define mmMC_ARB_WCDR_2__SI__CI 0x09CE -#define mmMC_ARB_WTM_CNTL_RD 0x09DF -#define mmMC_ARB_WTM_CNTL_WR 0x09E0 -#define mmMC_ARB_WTM_GRPWT_RD 0x09E1 -#define mmMC_ARB_WTM_GRPWT_WR 0x09E2 -#define mmMC_BIST_AUTO_CNTL__SI__CI 0x0A06 -#define mmMC_BIST_CMD_CNTL__SI__CI 0x0A8E -#define mmMC_BIST_CMP_CNTL__SI__CI 0x0A8D -#define mmMC_BIST_CMP_CNTL_2__SI__CI 0x0AB6 -#define mmMC_BIST_CNTL__SI__CI 0x0A05 -#define mmMC_BIST_DATA_MASK__SI__CI 0x0A12 -#define mmMC_BIST_DATA_WORD0__SI__CI 0x0A0A -#define mmMC_BIST_DATA_WORD1__SI__CI 0x0A0B -#define mmMC_BIST_DATA_WORD2__SI__CI 0x0A0C -#define mmMC_BIST_DATA_WORD3__SI__CI 0x0A0D -#define mmMC_BIST_DATA_WORD4__SI__CI 0x0A0E -#define mmMC_BIST_DATA_WORD5__SI__CI 0x0A0F -#define mmMC_BIST_DATA_WORD6__SI__CI 0x0A10 -#define mmMC_BIST_DATA_WORD7__SI__CI 0x0A11 -#define mmMC_BIST_DIR_CNTL__SI__CI 0x0A07 -#define mmMC_BIST_EADDR__SI__CI 0x0A09 -#define mmMC_BIST_MISMATCH_ADDR__SI__CI 0x0A13 -#define mmMC_BIST_RDATA_EDC__SI__CI 0x0A1D -#define mmMC_BIST_RDATA_MASK__SI__CI 0x0A1C -#define mmMC_BIST_RDATA_WORD0__SI__CI 0x0A14 -#define mmMC_BIST_RDATA_WORD1__SI__CI 0x0A15 -#define mmMC_BIST_RDATA_WORD2__SI__CI 0x0A16 -#define mmMC_BIST_RDATA_WORD3__SI__CI 0x0A17 -#define mmMC_BIST_RDATA_WORD4__SI__CI 0x0A18 -#define mmMC_BIST_RDATA_WORD5__SI__CI 0x0A19 -#define mmMC_BIST_RDATA_WORD6__SI__CI 0x0A1A -#define mmMC_BIST_RDATA_WORD7__SI__CI 0x0A1B -#define mmMC_BIST_SADDR__SI__CI 0x0A08 -#define mmMC_CG_CONFIG 0x096F -#define mmMC_CG_CONFIG_MCD 0x0829 -#define mmMC_CITF_CNTL 0x0970 -#define mmMC_CITF_CREDITS_ARB_RD 0x0972 -#define mmMC_CITF_CREDITS_ARB_WR 0x0973 -#define mmMC_CITF_CREDITS_VM 0x0971 -#define mmMC_CITF_CREDITS_XBAR 0x0989 -#define mmMC_CITF_DAGB_CNTL 0x0974 -#define mmMC_CITF_DAGB_DLY 0x0977 -#define mmMC_CITF_INT_CREDITS 0x0975 -#define mmMC_CITF_INT_CREDITS_WR__CI__VI 0x097D -#define mmMC_CITF_MISC_RD_CG 0x0992 -#define mmMC_CITF_MISC_VM_CG 0x0994 -#define mmMC_CITF_MISC_WR_CG 0x0993 -#define mmMC_CITF_PERFCOUNTER0_CFG__CI__VI 0x07B0 -#define mmMC_CITF_PERFCOUNTER1_CFG__CI__VI 0x07B1 -#define mmMC_CITF_PERFCOUNTER2_CFG__CI__VI 0x07B2 -#define mmMC_CITF_PERFCOUNTER3_CFG__CI__VI 0x07B3 -#define mmMC_CITF_PERFCOUNTER_HI__CI__VI 0x07A8 -#define mmMC_CITF_PERFCOUNTER_LO__CI__VI 0x07A0 -#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07CE -#define mmMC_CITF_PERF_MON_CNTL0__SI 0x098C -#define mmMC_CITF_PERF_MON_CNTL1__SI 0x098D -#define mmMC_CITF_PERF_MON_CNTL2 0x098E -#define mmMC_CITF_PERF_MON_RSLT0__SI 0x098F -#define mmMC_CITF_PERF_MON_RSLT1__SI 0x0990 -#define mmMC_CITF_PERF_MON_RSLT2 0x0991 -#define mmMC_CITF_REMREQ 0x097A -#define mmMC_CITF_RET_MODE 0x0976 -#define mmMC_CITF_WTM_RD_CNTL 0x097F -#define mmMC_CITF_WTM_WR_CNTL 0x0980 -#define mmMC_CITF_XTRA_ENABLE 0x096D -#define mmMC_CONFIG 0x0800 -#define mmMC_CONFIG_MCD 0x0828 -#define mmMC_DC_INTERFACE_NACK_STATUS__SI 0x031C -#define mmMC_DLB_CONFIG0__CI 0x0D93 -#define mmMC_DLB_CONFIG1__CI 0x0D94 -#define mmMC_DLB_MISCCTRL0__CI 0x0D90 -#define mmMC_DLB_MISCCTRL1__CI 0x0D91 -#define mmMC_DLB_MISCCTRL2__CI 0x0D92 -#define mmMC_DLB_SETUPFIFO__CI 0x0D97 -#define mmMC_DLB_SETUPSWEEP__CI 0x0D96 -#define mmMC_DLB_SETUP__CI 0x0D95 -#define mmMC_DLB_STATUS_MISC0__CI 0x0D9A -#define mmMC_DLB_STATUS_MISC1__CI 0x0D9B -#define mmMC_DLB_STATUS_MISC2__CI 0x0D9C -#define mmMC_DLB_STATUS_MISC3__CI 0x0D9D -#define mmMC_DLB_STATUS_MISC4__CI 0x0D9E -#define mmMC_DLB_STATUS_MISC5__CI 0x0D9F -#define mmMC_DLB_STATUS_MISC6__CI 0x0DA0 -#define mmMC_DLB_STATUS_MISC7__CI 0x0DA1 -#define mmMC_DLB_STATUS__CI 0x0D99 -#define mmMC_DLB_WRITE_MASK__CI 0x0D98 -#define mmMC_HUB_MISC_DBG__SI__CI 0x0831 -#define mmMC_HUB_MISC_FRAMING 0x0834 -#define mmMC_HUB_MISC_HUB_CG 0x082E -#define mmMC_HUB_MISC_IDLE_STATUS 0x0847 -#define mmMC_HUB_MISC_OVERRIDE 0x0833 -#define mmMC_HUB_MISC_POWER 0x082D -#define mmMC_HUB_MISC_SIP_CG 0x0830 -#define mmMC_HUB_MISC_STATUS 0x0832 -#define mmMC_HUB_MISC_VM_CG 0x082F -#define mmMC_HUB_PERFCOUNTER0_CFG__CI__VI 0x07B4 -#define mmMC_HUB_PERFCOUNTER1_CFG__CI__VI 0x07B5 -#define mmMC_HUB_PERFCOUNTER2_CFG__CI__VI 0x07B6 -#define mmMC_HUB_PERFCOUNTER3_CFG__CI__VI 0x07B7 -#define mmMC_HUB_PERFCOUNTER_HI__CI__VI 0x07A9 -#define mmMC_HUB_PERFCOUNTER_LO__CI__VI 0x07A1 -#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07CF -#define mmMC_HUB_RDREQ_ACPG_LIMIT__CI__VI 0x0849 -#define mmMC_HUB_RDREQ_ACPG__CI 0x0887 -#define mmMC_HUB_RDREQ_ACPO__CI 0x0888 -#define mmMC_HUB_RDREQ_CNTL 0x083B -#define mmMC_HUB_RDREQ_CPC__CI 0x085A -#define mmMC_HUB_RDREQ_CPF__CI 0x085B -#define mmMC_HUB_RDREQ_CPG__CI 0x0859 -#define mmMC_HUB_RDREQ_CP__SI 0x0859 -#define mmMC_HUB_RDREQ_CREDITS 0x0844 -#define mmMC_HUB_RDREQ_CREDITS2 0x0845 -#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x0848 -#define mmMC_HUB_RDREQ_DMIF__CI 0x0865 -#define mmMC_HUB_RDREQ_DMIF__SI 0x0863 -#define mmMC_HUB_RDREQ_DRMDMA0__SI 0x085A -#define mmMC_HUB_RDREQ_DRMDMA1__SI 0x085C -#define mmMC_HUB_RDREQ_GBL0 0x0856 -#define mmMC_HUB_RDREQ_GBL1 0x0857 -#define mmMC_HUB_RDREQ_HDP__CI 0x085E -#define mmMC_HUB_RDREQ_HDP__SI 0x085B -#define mmMC_HUB_RDREQ_IA0__CI 0x084F -#define mmMC_HUB_RDREQ_IA1__CI 0x0850 -#define mmMC_HUB_RDREQ_IA__CI 0x0864 -#define mmMC_HUB_RDREQ_MCDW 0x0851 -#define mmMC_HUB_RDREQ_MCDX 0x0852 -#define mmMC_HUB_RDREQ_MCDY 0x0853 -#define mmMC_HUB_RDREQ_MCDZ 0x0854 -#define mmMC_HUB_RDREQ_MCIF__CI 0x0866 -#define mmMC_HUB_RDREQ_MCIF__SI 0x0864 -#define mmMC_HUB_RDREQ_RLC__CI 0x085F -#define mmMC_HUB_RDREQ_RLC__SI 0x085D -#define mmMC_HUB_RDREQ_SAM__CI 0x0889 -#define mmMC_HUB_RDREQ_SDMA0__CI 0x085C -#define mmMC_HUB_RDREQ_SDMA1__CI 0x085D -#define mmMC_HUB_RDREQ_SEM__CI 0x0860 -#define mmMC_HUB_RDREQ_SEM__SI 0x085E -#define mmMC_HUB_RDREQ_SIP 0x0855 -#define mmMC_HUB_RDREQ_SMU 0x0858 -#define mmMC_HUB_RDREQ_STATUS 0x0839 -#define mmMC_HUB_RDREQ_UMC__CI 0x0862 -#define mmMC_HUB_RDREQ_UMC__SI 0x0860 -#define mmMC_HUB_RDREQ_UVD__CI 0x0863 -#define mmMC_HUB_RDREQ_UVD__SI 0x0861 -#define mmMC_HUB_RDREQ_VCEU__CI 0x0868 -#define mmMC_HUB_RDREQ_VCEU__SI 0x0866 -#define mmMC_HUB_RDREQ_VCE__CI 0x0861 -#define mmMC_HUB_RDREQ_VCE__SI 0x085F -#define mmMC_HUB_RDREQ_VGT__SI 0x0862 -#define mmMC_HUB_RDREQ_VMC__CI 0x0867 -#define mmMC_HUB_RDREQ_VMC__SI 0x0865 -#define mmMC_HUB_RDREQ_WTM_CNTL 0x083D -#define mmMC_HUB_RDREQ_XDMAM__CI 0x0886 -#define mmMC_HUB_RDREQ_XDMAM__SI 0x0882 -#define mmMC_HUB_SHARED_DAGB_DLY 0x0846 -#define mmMC_HUB_WDP_ACPG__CI 0x088A -#define mmMC_HUB_WDP_ACPO__CI 0x088B -#define mmMC_HUB_WDP_BP 0x0837 -#define mmMC_HUB_WDP_CNTL 0x0835 -#define mmMC_HUB_WDP_CPC__CI 0x086F -#define mmMC_HUB_WDP_CPF__CI 0x0870 -#define mmMC_HUB_WDP_CPG__CI 0x086E -#define mmMC_HUB_WDP_CP__SI 0x086C -#define mmMC_HUB_WDP_CREDITS 0x083F -#define mmMC_HUB_WDP_DRMDMA0__SI 0x087A -#define mmMC_HUB_WDP_DRMDMA1__SI 0x086D -#define mmMC_HUB_WDP_ERR 0x0836 -#define mmMC_HUB_WDP_GBL0 0x0841 -#define mmMC_HUB_WDP_GBL1 0x0842 -#define mmMC_HUB_WDP_HDP__CI 0x087C -#define mmMC_HUB_WDP_HDP__SI 0x0879 -#define mmMC_HUB_WDP_IH__CI 0x0875 -#define mmMC_HUB_WDP_IH__SI 0x0872 -#define mmMC_HUB_WDP_MCDW__CI 0x0869 -#define mmMC_HUB_WDP_MCDW__SI 0x0867 -#define mmMC_HUB_WDP_MCDX__CI 0x086A -#define mmMC_HUB_WDP_MCDX__SI 0x0868 -#define mmMC_HUB_WDP_MCDY__CI 0x086B -#define mmMC_HUB_WDP_MCDY__SI 0x0869 -#define mmMC_HUB_WDP_MCDZ__CI 0x086C -#define mmMC_HUB_WDP_MCDZ__SI 0x086A -#define mmMC_HUB_WDP_MCIF__CI 0x0872 -#define mmMC_HUB_WDP_MCIF__SI 0x086F -#define mmMC_HUB_WDP_MGPU__SI__CI 0x0843 -#define mmMC_HUB_WDP_MGPU2__SI__CI 0x0840 -#define mmMC_HUB_WDP_RLC__CI 0x0876 -#define mmMC_HUB_WDP_RLC__SI 0x0873 -#define mmMC_HUB_WDP_SAM__CI 0x088C -#define mmMC_HUB_WDP_SDMA0__CI 0x087D -#define mmMC_HUB_WDP_SDMA1__CI 0x087E -#define mmMC_HUB_WDP_SEM__CI 0x0877 -#define mmMC_HUB_WDP_SEM__SI 0x0874 -#define mmMC_HUB_WDP_SH0__CI 0x0871 -#define mmMC_HUB_WDP_SH0__SI 0x086E -#define mmMC_HUB_WDP_SH1__CI 0x0879 -#define mmMC_HUB_WDP_SH1__SI 0x0876 -#define mmMC_HUB_WDP_SH2__CI__VI 0x084D -#define mmMC_HUB_WDP_SH3__CI__VI 0x084E -#define mmMC_HUB_WDP_SIP__CI 0x086D -#define mmMC_HUB_WDP_SIP__SI 0x086B -#define mmMC_HUB_WDP_SMU__CI 0x0878 -#define mmMC_HUB_WDP_SMU__SI 0x0875 -#define mmMC_HUB_WDP_STATUS 0x0838 -#define mmMC_HUB_WDP_UMC__CI 0x087A -#define mmMC_HUB_WDP_UMC__SI 0x0877 -#define mmMC_HUB_WDP_UVD__CI 0x087B -#define mmMC_HUB_WDP_UVD__SI 0x0878 -#define mmMC_HUB_WDP_VCEU__CI 0x0883 -#define mmMC_HUB_WDP_VCEU__SI 0x087F -#define mmMC_HUB_WDP_VCE__CI 0x0873 -#define mmMC_HUB_WDP_VCE__SI 0x0870 -#define mmMC_HUB_WDP_WTM_CNTL 0x083E -#define mmMC_HUB_WDP_XDMAM__CI 0x0884 -#define mmMC_HUB_WDP_XDMAM__SI 0x0880 -#define mmMC_HUB_WDP_XDMA__CI 0x0885 -#define mmMC_HUB_WDP_XDMA__SI 0x0881 -#define mmMC_HUB_WDP_XDP__CI 0x0874 -#define mmMC_HUB_WDP_XDP__SI 0x0871 -#define mmMC_HUB_WRRET_CNTL 0x083C -#define mmMC_HUB_WRRET_MCDW__CI 0x087F -#define mmMC_HUB_WRRET_MCDW__SI 0x087B -#define mmMC_HUB_WRRET_MCDX__CI 0x0880 -#define mmMC_HUB_WRRET_MCDX__SI 0x087C -#define mmMC_HUB_WRRET_MCDY__CI 0x0881 -#define mmMC_HUB_WRRET_MCDY__SI 0x087D -#define mmMC_HUB_WRRET_MCDZ__CI 0x0882 -#define mmMC_HUB_WRRET_MCDZ__SI 0x087E -#define mmMC_HUB_WRRET_STATUS 0x083A -#define mmMC_IMP_CNTL__SI__CI 0x0A36 -#define mmMC_IMP_DEBUG__SI__CI 0x0A37 -#define mmMC_IMP_DQ_STATUS__SI__CI 0x0ABC -#define mmMC_IMP_STATUS__SI__CI 0x0A38 -#define mmMC_IO_APHY_STR_CNTL_D0__SI__CI 0x0A97 -#define mmMC_IO_APHY_STR_CNTL_D1__SI__CI 0x0A98 -#define mmMC_IO_CDRCNTL1_D0__SI__CI 0x0ADD -#define mmMC_IO_CDRCNTL1_D1__SI__CI 0x0ADE -#define mmMC_IO_CDRCNTL2_D0__SI__CI 0x0AE4 -#define mmMC_IO_CDRCNTL2_D1__SI__CI 0x0AE5 -#define mmMC_IO_CDRCNTL_D0__SI__CI 0x0A55 -#define mmMC_IO_CDRCNTL_D1__SI__CI 0x0A56 -#define mmMC_IO_DPHY_STR_CNTL_D0__SI__CI 0x0A4E -#define mmMC_IO_DPHY_STR_CNTL_D1__SI__CI 0x0A54 -#define mmMC_IO_PAD_CNTL__SI__CI 0x0A73 -#define mmMC_IO_PAD_CNTL_D0__SI__CI 0x0A74 -#define mmMC_IO_PAD_CNTL_D1__SI__CI 0x0A75 -#define mmMC_IO_RXCNTL1_DPHY0_D0__SI__CI 0x0ADF -#define mmMC_IO_RXCNTL1_DPHY0_D1__SI__CI 0x0AE1 -#define mmMC_IO_RXCNTL1_DPHY1_D0__SI__CI 0x0AE0 -#define mmMC_IO_RXCNTL1_DPHY1_D1__SI__CI 0x0AE2 -#define mmMC_IO_RXCNTL_DPHY0_D0__SI__CI 0x0A4C -#define mmMC_IO_RXCNTL_DPHY0_D1__SI__CI 0x0A52 -#define mmMC_IO_RXCNTL_DPHY1_D0__SI__CI 0x0A4D -#define mmMC_IO_RXCNTL_DPHY1_D1__SI__CI 0x0A53 -#define mmMC_IO_TXCNTL_APHY_D0__SI__CI 0x0A4B -#define mmMC_IO_TXCNTL_APHY_D1__SI__CI 0x0A51 -#define mmMC_IO_TXCNTL_DPHY0_D0__SI__CI 0x0A49 -#define mmMC_IO_TXCNTL_DPHY0_D1__SI__CI 0x0A4F -#define mmMC_IO_TXCNTL_DPHY1_D0__SI__CI 0x0A4A -#define mmMC_IO_TXCNTL_DPHY1_D1__SI__CI 0x0A50 -#define mmMC_MCBVM_PERFCOUNTER0_CFG__CI__VI 0x07C0 -#define mmMC_MCBVM_PERFCOUNTER1_CFG__CI__VI 0x07C1 -#define mmMC_MCBVM_PERFCOUNTER2_CFG__CI__VI 0x07C2 -#define mmMC_MCBVM_PERFCOUNTER3_CFG__CI__VI 0x07C3 -#define mmMC_MCBVM_PERFCOUNTER_HI__CI__VI 0x07AA -#define mmMC_MCBVM_PERFCOUNTER_LO__CI__VI 0x07A3 -#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07D1 -#define mmMC_MCDVM_PERFCOUNTER0_CFG__CI__VI 0x07C4 -#define mmMC_MCDVM_PERFCOUNTER1_CFG__CI__VI 0x07C5 -#define mmMC_MCDVM_PERFCOUNTER2_CFG__CI__VI 0x07C6 -#define mmMC_MCDVM_PERFCOUNTER3_CFG__CI__VI 0x07C7 -#define mmMC_MCDVM_PERFCOUNTER_HI__CI__VI 0x07AB -#define mmMC_MCDVM_PERFCOUNTER_LO__CI__VI 0x07A4 -#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07D2 -#define mmMC_MEM_POWER_LS 0x082A -#define mmMC_NPL_STATUS__SI__CI 0x0A76 -#define mmMC_PHY_TIMING_2__SI__CI 0x0ACE -#define mmMC_PHY_TIMING_D0__SI__CI 0x0ACC -#define mmMC_PHY_TIMING_D1__SI__CI 0x0ACD -#define mmMC_PMG_AUTO_CFG__SI__CI 0x0A35 -#define mmMC_PMG_AUTO_CMD__SI__CI 0x0A34 -#define mmMC_PMG_CFG__SI__CI 0x0A84 -#define mmMC_PMG_CMD_EMRS__SI__CI 0x0A83 -#define mmMC_PMG_CMD_MRS__SI__CI 0x0AAB -#define mmMC_PMG_CMD_MRS1__SI__CI 0x0AD1 -#define mmMC_PMG_CMD_MRS2__SI__CI 0x0AD7 -#define mmMC_RD_CB 0x0981 -#define mmMC_RD_DB 0x0982 -#define mmMC_RD_GRP_EXT 0x0978 -#define mmMC_RD_GRP_GFX 0x0803 -#define mmMC_RD_GRP_LCL 0x098A -#define mmMC_RD_GRP_OTH 0x0807 -#define mmMC_RD_GRP_SYS 0x0805 -#define mmMC_RD_HUB 0x0985 -#define mmMC_RD_TC0 0x0983 -#define mmMC_RD_TC1 0x0984 -#define mmMC_RPB_ARB_CNTL 0x0951 -#define mmMC_RPB_BIF_CNTL 0x0952 -#define mmMC_RPB_CID_QUEUE_EX 0x095A -#define mmMC_RPB_CID_QUEUE_EX_DATA 0x095B -#define mmMC_RPB_CID_QUEUE_RD 0x0957 -#define mmMC_RPB_CID_QUEUE_WR 0x0956 -#define mmMC_RPB_CONF 0x094D -#define mmMC_RPB_DBG1 0x094F -#define mmMC_RPB_EFF_CNTL 0x0950 -#define mmMC_RPB_IF_CONF 0x094E -#define mmMC_RPB_PERFCOUNTER0_CFG__CI__VI 0x07B8 -#define mmMC_RPB_PERFCOUNTER1_CFG__CI__VI 0x07B9 -#define mmMC_RPB_PERFCOUNTER2_CFG__CI__VI 0x07BA -#define mmMC_RPB_PERFCOUNTER3_CFG__CI__VI 0x07BB -#define mmMC_RPB_PERFCOUNTER_HI__CI__VI 0x07AC -#define mmMC_RPB_PERFCOUNTER_LO__CI__VI 0x07A2 -#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07D0 -#define mmMC_RPB_PERF_COUNTER_CNTL 0x0958 -#define mmMC_RPB_PERF_COUNTER_STATUS 0x0959 -#define mmMC_RPB_RD_SWITCH_CNTL 0x0955 -#define mmMC_RPB_WR_COMBINE_CNTL 0x0954 -#define mmMC_RPB_WR_SWITCH_CNTL 0x0953 -#define mmMC_SEQ_BIT_REMAP_B0_D0__SI__CI 0x0AA3 -#define mmMC_SEQ_BIT_REMAP_B0_D1__SI__CI 0x0AA7 -#define mmMC_SEQ_BIT_REMAP_B1_D0__SI__CI 0x0AA4 -#define mmMC_SEQ_BIT_REMAP_B1_D1__SI__CI 0x0AA8 -#define mmMC_SEQ_BIT_REMAP_B2_D0__SI__CI 0x0AA5 -#define mmMC_SEQ_BIT_REMAP_B2_D1__SI__CI 0x0AA9 -#define mmMC_SEQ_BIT_REMAP_B3_D0__SI__CI 0x0AA6 -#define mmMC_SEQ_BIT_REMAP_B3_D1__SI__CI 0x0AAA -#define mmMC_SEQ_BYTE_REMAP_D0__SI__CI 0x0A93 -#define mmMC_SEQ_BYTE_REMAP_D1__SI__CI 0x0A94 -#define mmMC_SEQ_CAS_TIMING__SI__CI 0x0A29 -#define mmMC_SEQ_CAS_TIMING_LP__SI__CI 0x0A9C -#define mmMC_SEQ_CG__SI__CI 0x0A9A -#define mmMC_SEQ_CMD__SI__CI 0x0A31 -#define mmMC_SEQ_CNTL__SI__CI 0x0A25 -#define mmMC_SEQ_CNTL_2__SI__CI 0x0AD4 -#define mmMC_SEQ_CNTL_3__CI 0x0D80 -#define mmMC_SEQ_DLL_STBY_LP__CI 0x0D8F -#define mmMC_SEQ_DLL_STBY__CI 0x0D8E -#define mmMC_SEQ_DRAM__SI__CI 0x0A26 -#define mmMC_SEQ_DRAM_2__SI__CI 0x0A27 -#define mmMC_SEQ_DRAM_ERROR_INSERTION__SI__CI 0x0ACB -#define mmMC_SEQ_FIFO_CTL__SI__CI 0x0A57 -#define mmMC_SEQ_G5PDX_CMD0_LP__CI 0x0D84 -#define mmMC_SEQ_G5PDX_CMD0__CI 0x0D83 -#define mmMC_SEQ_G5PDX_CMD1_LP__CI 0x0D86 -#define mmMC_SEQ_G5PDX_CMD1__CI 0x0D85 -#define mmMC_SEQ_G5PDX_CTRL_LP__CI 0x0D82 -#define mmMC_SEQ_G5PDX_CTRL__CI 0x0D81 -#define mmMC_SEQ_IO_DEBUG_DATA__SI__CI 0x0A92 -#define mmMC_SEQ_IO_DEBUG_INDEX__SI__CI 0x0A91 -#define mmMC_SEQ_IO_RDBI__SI__CI 0x0AB4 -#define mmMC_SEQ_IO_REDC__SI__CI 0x0AB5 -#define mmMC_SEQ_IO_RESERVE_D0__SI__CI 0x0AB7 -#define mmMC_SEQ_IO_RESERVE_D1__SI__CI 0x0AB8 -#define mmMC_SEQ_IO_RWORD0__SI__CI 0x0AAC -#define mmMC_SEQ_IO_RWORD1__SI__CI 0x0AAD -#define mmMC_SEQ_IO_RWORD2__SI__CI 0x0AAE -#define mmMC_SEQ_IO_RWORD3__SI__CI 0x0AAF -#define mmMC_SEQ_IO_RWORD4__SI__CI 0x0AB0 -#define mmMC_SEQ_IO_RWORD5__SI__CI 0x0AB1 -#define mmMC_SEQ_IO_RWORD6__SI__CI 0x0AB2 -#define mmMC_SEQ_IO_RWORD7__SI__CI 0x0AB3 -#define mmMC_SEQ_MISC0__SI__CI 0x0A80 -#define mmMC_SEQ_MISC1__SI__CI 0x0A81 -#define mmMC_SEQ_MISC3__SI__CI 0x0A8B -#define mmMC_SEQ_MISC4__SI__CI 0x0A8C -#define mmMC_SEQ_MISC5__SI__CI 0x0A95 -#define mmMC_SEQ_MISC6__SI__CI 0x0A96 -#define mmMC_SEQ_MISC7__SI__CI 0x0A99 -#define mmMC_SEQ_MISC8__SI__CI 0x0A5F -#define mmMC_SEQ_MISC9__SI__CI 0x0AE7 -#define mmMC_SEQ_MISC_TIMING__SI__CI 0x0A2A -#define mmMC_SEQ_MISC_TIMING2__SI__CI 0x0A2B -#define mmMC_SEQ_MISC_TIMING2_LP__SI__CI 0x0A9E -#define mmMC_SEQ_MISC_TIMING_LP__SI__CI 0x0A9D -#define mmMC_SEQ_MPLL_OVERRIDE__SI__CI 0x0A22 -#define mmMC_SEQ_PERF_CNTL__SI__CI 0x0A77 -#define mmMC_SEQ_PERF_CNTL_1__SI__CI 0x0AFD -#define mmMC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI 0x0A79 -#define mmMC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI 0x0A7A -#define mmMC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI 0x0A7B -#define mmMC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI 0x0A7C -#define mmMC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI 0x0AD9 -#define mmMC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI 0x0ADA -#define mmMC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI 0x0ADB -#define mmMC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI 0x0ADC -#define mmMC_SEQ_PERF_SEQ_CNT_A_I0__VI 0x0A79 -#define mmMC_SEQ_PERF_SEQ_CNT_A_I1__VI 0x0A7A -#define mmMC_SEQ_PERF_SEQ_CNT_B_I0__VI 0x0A7B -#define mmMC_SEQ_PERF_SEQ_CNT_B_I1__VI 0x0A7C -#define mmMC_SEQ_PERF_SEQ_CNT_C_I0__VI 0x0AD9 -#define mmMC_SEQ_PERF_SEQ_CNT_C_I1__VI 0x0ADA -#define mmMC_SEQ_PERF_SEQ_CNT_D_I0__VI 0x0ADB -#define mmMC_SEQ_PERF_SEQ_CNT_D_I1__VI 0x0ADC -#define mmMC_SEQ_PERF_SEQ_CTL__SI__CI 0x0A78 -#define mmMC_SEQ_PERF_SEQ_CTL__SI__VI 0x0A78 -#define mmMC_SEQ_PHYREG_BCAST__CI 0x0D89 -#define mmMC_SEQ_PMG_CMD_EMRS_LP__SI__CI 0x0AA1 -#define mmMC_SEQ_PMG_CMD_MRS1_LP__SI__CI 0x0AD2 -#define mmMC_SEQ_PMG_CMD_MRS2_LP__SI__CI 0x0AD8 -#define mmMC_SEQ_PMG_CMD_MRS_LP__SI__CI 0x0AA2 -#define mmMC_SEQ_PMG_DVS_CMD_LP__CI 0x0D8D -#define mmMC_SEQ_PMG_DVS_CMD__CI 0x0D8C -#define mmMC_SEQ_PMG_DVS_CTL_LP__CI 0x0D8B -#define mmMC_SEQ_PMG_DVS_CTL__CI 0x0D8A -#define mmMC_SEQ_PMG_PG_HWCNTL__SI__CI 0x0AB9 -#define mmMC_SEQ_PMG_PG_SWCNTL_0__SI__CI 0x0ABA -#define mmMC_SEQ_PMG_PG_SWCNTL_1__SI__CI 0x0ABB -#define mmMC_SEQ_PMG_TIMING__SI__CI 0x0A2C -#define mmMC_SEQ_PMG_TIMING_LP__SI__CI 0x0AD3 -#define mmMC_SEQ_RAS_TIMING__SI__CI 0x0A28 -#define mmMC_SEQ_RAS_TIMING_LP__SI__CI 0x0A9B -#define mmMC_SEQ_RD_CTL_D0__SI__CI 0x0A2D -#define mmMC_SEQ_RD_CTL_D0_LP__SI__CI 0x0AC7 -#define mmMC_SEQ_RD_CTL_D1__SI__CI 0x0A2E -#define mmMC_SEQ_RD_CTL_D1_LP__SI__CI 0x0AC8 -#define mmMC_SEQ_RESERVE_0_S__SI__CI 0x0A1E -#define mmMC_SEQ_RESERVE_1_S__SI__CI 0x0A1F -#define mmMC_SEQ_RESERVE_M__SI__CI 0x0A82 -#define mmMC_SEQ_RXFRAMING_BYTE0_D0__SI__CI 0x0A67 -#define mmMC_SEQ_RXFRAMING_BYTE0_D1__SI__CI 0x0A6D -#define mmMC_SEQ_RXFRAMING_BYTE1_D0__SI__CI 0x0A68 -#define mmMC_SEQ_RXFRAMING_BYTE1_D1__SI__CI 0x0A6E -#define mmMC_SEQ_RXFRAMING_BYTE2_D0__SI__CI 0x0A69 -#define mmMC_SEQ_RXFRAMING_BYTE2_D1__SI__CI 0x0A6F -#define mmMC_SEQ_RXFRAMING_BYTE3_D0__SI__CI 0x0A6A -#define mmMC_SEQ_RXFRAMING_BYTE3_D1__SI__CI 0x0A70 -#define mmMC_SEQ_RXFRAMING_DBI_D0__SI__CI 0x0A6B -#define mmMC_SEQ_RXFRAMING_DBI_D1__SI__CI 0x0A71 -#define mmMC_SEQ_RXFRAMING_EDC_D0__SI__CI 0x0A6C -#define mmMC_SEQ_RXFRAMING_EDC_D1__SI__CI 0x0A72 -#define mmMC_SEQ_SREG_READ__CI 0x0D87 -#define mmMC_SEQ_SREG_STATUS__CI 0x0D88 -#define mmMC_SEQ_STATUS_M__SI__CI 0x0A7D -#define mmMC_SEQ_STATUS_S__SI__CI 0x0A20 -#define mmMC_SEQ_SUP_CNTL__SI__CI 0x0A32 -#define mmMC_SEQ_SUP_DEC_STAT__SI__CI 0x0A88 -#define mmMC_SEQ_SUP_GP0_STAT__SI__CI 0x0A8F -#define mmMC_SEQ_SUP_GP1_STAT__SI__CI 0x0A90 -#define mmMC_SEQ_SUP_GP2_STAT__SI__CI 0x0A85 -#define mmMC_SEQ_SUP_GP3_STAT__SI__CI 0x0A86 -#define mmMC_SEQ_SUP_IR_STAT__SI__CI 0x0A87 -#define mmMC_SEQ_SUP_PGM__SI__CI 0x0A33 -#define mmMC_SEQ_SUP_PGM_STAT__SI__CI 0x0A89 -#define mmMC_SEQ_SUP_R_PGM__SI__CI 0x0A8A -#define mmMC_SEQ_TCG_CNTL__SI__CI 0x0ABD -#define mmMC_SEQ_TIMER_RD__SI__CI 0x0ACA -#define mmMC_SEQ_TIMER_WR__SI__CI 0x0AC9 -#define mmMC_SEQ_TRAIN_CAPTURE__SI__CI 0x0A3E -#define mmMC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI 0x0A3B -#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI 0x0AFE -#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI 0x0AFF -#define mmMC_SEQ_TRAIN_TIMING__SI__CI 0x0A40 -#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI 0x0A3F -#define mmMC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI 0x0A3A -#define mmMC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI 0x0A3C -#define mmMC_SEQ_TRAIN_WAKEUP_MASK__SI__CI 0x0A3D -#define mmMC_SEQ_TSM_BCNT__SI__CI 0x0AC2 -#define mmMC_SEQ_TSM_CTRL__SI__CI 0x0ABE -#define mmMC_SEQ_TSM_DBI__SI__CI 0x0AC6 -#define mmMC_SEQ_TSM_DEBUG_DATA__SI__CI 0x0AD0 -#define mmMC_SEQ_TSM_DEBUG_INDEX__SI__CI 0x0ACF -#define mmMC_SEQ_TSM_EDC__SI__CI 0x0AC5 -#define mmMC_SEQ_TSM_FLAG__SI__CI 0x0AC3 -#define mmMC_SEQ_TSM_GCNT__SI__CI 0x0ABF -#define mmMC_SEQ_TSM_MISC__SI__CI 0x0AE6 -#define mmMC_SEQ_TSM_NCNT__SI__CI 0x0AC1 -#define mmMC_SEQ_TSM_OCNT__SI__CI 0x0AC0 -#define mmMC_SEQ_TSM_UPDATE__SI__CI 0x0AC4 -#define mmMC_SEQ_TSM_WCDR__SI__CI 0x0AE3 -#define mmMC_SEQ_TXFRAMING_BYTE0_D0__SI__CI 0x0A58 -#define mmMC_SEQ_TXFRAMING_BYTE0_D1__SI__CI 0x0A60 -#define mmMC_SEQ_TXFRAMING_BYTE1_D0__SI__CI 0x0A59 -#define mmMC_SEQ_TXFRAMING_BYTE1_D1__SI__CI 0x0A61 -#define mmMC_SEQ_TXFRAMING_BYTE2_D0__SI__CI 0x0A5A -#define mmMC_SEQ_TXFRAMING_BYTE2_D1__SI__CI 0x0A62 -#define mmMC_SEQ_TXFRAMING_BYTE3_D0__SI__CI 0x0A5B -#define mmMC_SEQ_TXFRAMING_BYTE3_D1__SI__CI 0x0A63 -#define mmMC_SEQ_TXFRAMING_DBI_D0__SI__CI 0x0A5C -#define mmMC_SEQ_TXFRAMING_DBI_D1__SI__CI 0x0A64 -#define mmMC_SEQ_TXFRAMING_EDC_D0__SI__CI 0x0A5D -#define mmMC_SEQ_TXFRAMING_EDC_D1__SI__CI 0x0A65 -#define mmMC_SEQ_TXFRAMING_FCK_D0__SI__CI 0x0A5E -#define mmMC_SEQ_TXFRAMING_FCK_D1__SI__CI 0x0A66 -#define mmMC_SEQ_VENDOR_ID_I0__SI__CI 0x0A7E -#define mmMC_SEQ_VENDOR_ID_I1__SI__CI 0x0A7F -#define mmMC_SEQ_WCDR_CTRL__SI__CI 0x0A39 -#define mmMC_SEQ_WR_CTL_2__SI__CI 0x0AD5 -#define mmMC_SEQ_WR_CTL_2_LP__SI__CI 0x0AD6 -#define mmMC_SEQ_WR_CTL_D0__SI__CI 0x0A2F -#define mmMC_SEQ_WR_CTL_D0_LP__SI__CI 0x0A9F -#define mmMC_SEQ_WR_CTL_D1__SI__CI 0x0A30 -#define mmMC_SEQ_WR_CTL_D1_LP__SI__CI 0x0AA0 -#define mmMC_SHARED_BLACKOUT_CNTL 0x082B -#define mmMC_SHARED_CHMAP 0x0801 -#define mmMC_SHARED_CHREMAP 0x0802 -#define mmMC_TRAIN_EDCCDR_R_D0__SI__CI 0x0A41 -#define mmMC_TRAIN_EDCCDR_R_D1__SI__CI 0x0A42 -#define mmMC_TRAIN_EDC_STATUS_D0__SI__CI 0x0A45 -#define mmMC_TRAIN_EDC_STATUS_D1__SI__CI 0x0A48 -#define mmMC_TRAIN_PRBSERR_0_D0__SI__CI 0x0A43 -#define mmMC_TRAIN_PRBSERR_0_D1__SI__CI 0x0A46 -#define mmMC_TRAIN_PRBSERR_1_D0__SI__CI 0x0A44 -#define mmMC_TRAIN_PRBSERR_1_D1__SI__CI 0x0A47 -#define mmMC_TRAIN_PRBSERR_2_D0__SI__CI 0x0AFB -#define mmMC_TRAIN_PRBSERR_2_D1__SI__CI 0x0AFC -#define mmMC_VM_AGP_BASE 0x080C -#define mmMC_VM_AGP_BOT 0x080B -#define mmMC_VM_AGP_TOP 0x080A -#define mmMC_VM_DC_WRITE_CNTL 0x0810 -#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x0815 -#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x0811 -#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x0816 -#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x0812 -#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x0817 -#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x0813 -#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x0818 -#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x0814 -#define mmMC_VM_FB_LOCATION 0x0809 -#define mmMC_VM_FB_OFFSET 0x081A -#define mmMC_VM_L2_PERFCOUNTER0_CFG__CI__VI 0x07CC -#define mmMC_VM_L2_PERFCOUNTER1_CFG__CI__VI 0x07CD -#define mmMC_VM_L2_PERFCOUNTER_HI__CI__VI 0x07AD -#define mmMC_VM_L2_PERFCOUNTER_LO__CI__VI 0x07A5 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI 0x07D3 -#define mmMC_VM_MB_L1_TLB0_DEBUG 0x0891 -#define mmMC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__SI 0x0899 -#define mmMC_VM_MB_L1_TLB0_PERF_COUNTER_STATUS__SI 0x089D -#define mmMC_VM_MB_L1_TLB0_STATUS 0x0895 -#define mmMC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__SI 0x089A -#define mmMC_VM_MB_L1_TLB1_PERF_COUNTER_STATUS__SI 0x089E -#define mmMC_VM_MB_L1_TLB1_STATUS 0x0896 -#define mmMC_VM_MB_L1_TLB2_DEBUG 0x0893 -#define mmMC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__SI 0x089B -#define mmMC_VM_MB_L1_TLB2_PERF_COUNTER_STATUS__SI 0x089F -#define mmMC_VM_MB_L1_TLB2_STATUS 0x0897 -#define mmMC_VM_MB_L1_TLB3_DEBUG 0x08A5 -#define mmMC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__SI 0x08A7 -#define mmMC_VM_MB_L1_TLB3_PERF_COUNTER_STATUS__SI 0x08A8 -#define mmMC_VM_MB_L1_TLB3_STATUS 0x08A6 -#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x08A1 -#define mmMC_VM_MB_SECURE__SI 0x08A3 -#define mmMC_VM_MD_L1_TLB0_DEBUG 0x0998 -#define mmMC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__SI 0x099E -#define mmMC_VM_MD_L1_TLB0_PERF_COUNTER_STATUS__SI 0x09A1 -#define mmMC_VM_MD_L1_TLB0_STATUS 0x099B -#define mmMC_VM_MD_L1_TLB1_DEBUG 0x0999 -#define mmMC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__SI 0x099F -#define mmMC_VM_MD_L1_TLB1_PERF_COUNTER_STATUS__SI 0x09A2 -#define mmMC_VM_MD_L1_TLB1_STATUS 0x099C -#define mmMC_VM_MD_L1_TLB2_DEBUG 0x099A -#define mmMC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__SI 0x09A0 -#define mmMC_VM_MD_L1_TLB2_PERF_COUNTER_STATUS__SI 0x09A3 -#define mmMC_VM_MD_L1_TLB2_STATUS 0x099D -#define mmMC_VM_MD_L1_TLB3_DEBUG 0x09A7 -#define mmMC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__SI 0x09A9 -#define mmMC_VM_MD_L1_TLB3_PERF_COUNTER_STATUS__SI 0x09AA -#define mmMC_VM_MD_L1_TLB3_STATUS 0x09A8 -#define mmMC_VM_MD_L1_TLB4_DEBUG__SI 0x09AE -#define mmMC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__SI 0x09B2 -#define mmMC_VM_MD_L1_TLB4_PERF_COUNTER_STATUS__SI 0x09B4 -#define mmMC_VM_MD_L1_TLB4_STATUS__SI 0x09B0 -#define mmMC_VM_MD_L1_TLB5_DEBUG__SI 0x09AF -#define mmMC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__SI 0x09B3 -#define mmMC_VM_MD_L1_TLB5_PERF_COUNTER_STATUS__SI 0x09B5 -#define mmMC_VM_MD_L1_TLB5_STATUS__SI 0x09B1 -#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x09A4 -#define mmMC_VM_MD_SECURE__SI 0x09AB -#define mmMC_VM_MX_L1_TLB_CNTL 0x0819 -#define mmMC_VM_STEERING__CI__VI 0x081B -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x080F -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x080E -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x080D -#define mmMC_WR_CB 0x0986 -#define mmMC_WR_DB 0x0987 -#define mmMC_WR_GRP_EXT 0x0979 -#define mmMC_WR_GRP_GFX 0x0804 -#define mmMC_WR_GRP_LCL 0x098B -#define mmMC_WR_GRP_OTH 0x0808 -#define mmMC_WR_GRP_SYS 0x0806 -#define mmMC_WR_HUB 0x0988 -#define mmMC_WR_TC0 0x097B -#define mmMC_WR_TC1 0x097C -#define mmMC_XBAR_ADDR_DEC 0x0C80 -#define mmMC_XBAR_ARB 0x0C8D -#define mmMC_XBAR_ARB_MAX_BURST 0x0C8E -#define mmMC_XBAR_CHTRIREMAP 0x0C8B -#define mmMC_XBAR_PERF_MON_CNTL0__SI__CI 0x0C8F -#define mmMC_XBAR_PERF_MON_CNTL1__SI__CI 0x0C90 -#define mmMC_XBAR_PERF_MON_CNTL2__SI__CI 0x0C91 -#define mmMC_XBAR_PERF_MON_MAX_THSH__SI__CI 0x0C96 -#define mmMC_XBAR_PERF_MON_RSLT0__SI__CI 0x0C92 -#define mmMC_XBAR_PERF_MON_RSLT1__SI__CI 0x0C93 -#define mmMC_XBAR_PERF_MON_RSLT2__SI__CI 0x0C94 -#define mmMC_XBAR_PERF_MON_RSLT3__SI__CI 0x0C95 -#define mmMC_XBAR_RDREQ_CREDIT 0x0C83 -#define mmMC_XBAR_RDREQ_PRI_CREDIT 0x0C84 -#define mmMC_XBAR_RDRET_CREDIT1 0x0C87 -#define mmMC_XBAR_RDRET_CREDIT2 0x0C88 -#define mmMC_XBAR_RDRET_PRI_CREDIT1 0x0C89 -#define mmMC_XBAR_RDRET_PRI_CREDIT2 0x0C8A -#define mmMC_XBAR_REMOTE 0x0C81 -#define mmMC_XBAR_SPARE0 0x0C97 -#define mmMC_XBAR_SPARE1 0x0C98 -#define mmMC_XBAR_TWOCHAN 0x0C8C -#define mmMC_XBAR_WRREQ_CREDIT 0x0C82 -#define mmMC_XBAR_WRRET_CREDIT1 0x0C85 -#define mmMC_XBAR_WRRET_CREDIT2 0x0C86 -#define mmMC_XPB_CLG_CFG0 0x08E9 -#define mmMC_XPB_CLG_CFG1 0x08EA -#define mmMC_XPB_CLG_CFG10 0x08F3 -#define mmMC_XPB_CLG_CFG11 0x08F4 -#define mmMC_XPB_CLG_CFG12 0x08F5 -#define mmMC_XPB_CLG_CFG13 0x08F6 -#define mmMC_XPB_CLG_CFG14 0x08F7 -#define mmMC_XPB_CLG_CFG15 0x08F8 -#define mmMC_XPB_CLG_CFG16 0x08F9 -#define mmMC_XPB_CLG_CFG17 0x08FA -#define mmMC_XPB_CLG_CFG18 0x08FB -#define mmMC_XPB_CLG_CFG19 0x08FC -#define mmMC_XPB_CLG_CFG2 0x08EB -#define mmMC_XPB_CLG_CFG20 0x0928 -#define mmMC_XPB_CLG_CFG21 0x0929 -#define mmMC_XPB_CLG_CFG22 0x092A -#define mmMC_XPB_CLG_CFG23 0x092B -#define mmMC_XPB_CLG_CFG24 0x092C -#define mmMC_XPB_CLG_CFG25 0x092D -#define mmMC_XPB_CLG_CFG26 0x092E -#define mmMC_XPB_CLG_CFG27 0x092F -#define mmMC_XPB_CLG_CFG28 0x0930 -#define mmMC_XPB_CLG_CFG29 0x0931 -#define mmMC_XPB_CLG_CFG3 0x08EC -#define mmMC_XPB_CLG_CFG30 0x0932 -#define mmMC_XPB_CLG_CFG31 0x0933 -#define mmMC_XPB_CLG_CFG32 0x0936 -#define mmMC_XPB_CLG_CFG33 0x0937 -#define mmMC_XPB_CLG_CFG34 0x0938 -#define mmMC_XPB_CLG_CFG35 0x0939 -#define mmMC_XPB_CLG_CFG36 0x093A -#define mmMC_XPB_CLG_CFG4 0x08ED -#define mmMC_XPB_CLG_CFG5 0x08EE -#define mmMC_XPB_CLG_CFG6 0x08EF -#define mmMC_XPB_CLG_CFG7 0x08F0 -#define mmMC_XPB_CLG_CFG8 0x08F1 -#define mmMC_XPB_CLG_CFG9 0x08F2 -#define mmMC_XPB_CLG_EXTRA 0x08FD -#define mmMC_XPB_CLG_EXTRA_RD 0x0935 -#define mmMC_XPB_CLK_GAT 0x091E -#define mmMC_XPB_INTF_CFG 0x091F -#define mmMC_XPB_INTF_CFG2 0x0934 -#define mmMC_XPB_INTF_STS 0x0920 -#define mmMC_XPB_LB_ADDR 0x08FE -#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x0923 -#define mmMC_XPB_MISC_CFG 0x0927 -#define mmMC_XPB_P2P_BAR0 0x0904 -#define mmMC_XPB_P2P_BAR1 0x0905 -#define mmMC_XPB_P2P_BAR2 0x0906 -#define mmMC_XPB_P2P_BAR3 0x0907 -#define mmMC_XPB_P2P_BAR4 0x0908 -#define mmMC_XPB_P2P_BAR5 0x0909 -#define mmMC_XPB_P2P_BAR6 0x090A -#define mmMC_XPB_P2P_BAR7 0x090B -#define mmMC_XPB_P2P_BAR_CFG 0x0903 -#define mmMC_XPB_P2P_BAR_DEBUG 0x090D -#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x090E -#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x090F -#define mmMC_XPB_P2P_BAR_SETUP 0x090C -#define mmMC_XPB_PEER_SYS_BAR0 0x0910 -#define mmMC_XPB_PEER_SYS_BAR1 0x0911 -#define mmMC_XPB_PEER_SYS_BAR2 0x0912 -#define mmMC_XPB_PEER_SYS_BAR3 0x0913 -#define mmMC_XPB_PEER_SYS_BAR4 0x0914 -#define mmMC_XPB_PEER_SYS_BAR5 0x0915 -#define mmMC_XPB_PEER_SYS_BAR6 0x0916 -#define mmMC_XPB_PEER_SYS_BAR7 0x0917 -#define mmMC_XPB_PEER_SYS_BAR8 0x0918 -#define mmMC_XPB_PEER_SYS_BAR9 0x0919 -#define mmMC_XPB_PERF_KNOBS 0x0924 -#define mmMC_XPB_PIPE_STS 0x0921 -#define mmMC_XPB_RTR_DEST_MAP0 0x08DB -#define mmMC_XPB_RTR_DEST_MAP1 0x08DC -#define mmMC_XPB_RTR_DEST_MAP2 0x08DD -#define mmMC_XPB_RTR_DEST_MAP3 0x08DE -#define mmMC_XPB_RTR_DEST_MAP4 0x08DF -#define mmMC_XPB_RTR_DEST_MAP5 0x08E0 -#define mmMC_XPB_RTR_DEST_MAP6 0x08E1 -#define mmMC_XPB_RTR_DEST_MAP7 0x08E2 -#define mmMC_XPB_RTR_DEST_MAP8 0x08E3 -#define mmMC_XPB_RTR_DEST_MAP9 0x08E4 -#define mmMC_XPB_RTR_SRC_APRTR0 0x08CD -#define mmMC_XPB_RTR_SRC_APRTR1 0x08CE -#define mmMC_XPB_RTR_SRC_APRTR2 0x08CF -#define mmMC_XPB_RTR_SRC_APRTR3 0x08D0 -#define mmMC_XPB_RTR_SRC_APRTR4 0x08D1 -#define mmMC_XPB_RTR_SRC_APRTR5 0x08D2 -#define mmMC_XPB_RTR_SRC_APRTR6 0x08D3 -#define mmMC_XPB_RTR_SRC_APRTR7 0x08D4 -#define mmMC_XPB_RTR_SRC_APRTR8 0x08D5 -#define mmMC_XPB_RTR_SRC_APRTR9 0x08D6 -#define mmMC_XPB_STICKY 0x0925 -#define mmMC_XPB_STICKY_W1C 0x0926 -#define mmMC_XPB_SUB_CTRL 0x0922 -#define mmMC_XPB_UNC_THRESH_HST 0x08FF -#define mmMC_XPB_UNC_THRESH_SID 0x0900 -#define mmMC_XPB_WCB_CFG 0x0902 -#define mmMC_XPB_WCB_STS 0x0901 -#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x091A -#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x091B -#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x091C -#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x091D -#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x08E5 -#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x08E6 -#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x08E7 -#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x08E8 -#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x08D7 -#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x08D8 -#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x08D9 -#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x08DA -#define mmMEM_TYPE_CNTL__CI__VI 0x14E4 -#define mmMICROSECOND_TIME_BASE_DIV__SI 0x0148 -#define mmMM_CFGREGS_CNTL 0x1513 -#define mmMM_DATA 0x0001 -#define mmMM_INDEX 0x0000 -#define mmMM_INDEX_HI__CI__VI 0x0006 -#define mmMPLL_AD_FUNC_CNTL__SI__CI 0x0AF0 -#define mmMPLL_AD_STATUS__SI__CI 0x0AF6 -#define mmMPLL_BYPASSCLK_SEL__SI 0x0197 -#define mmMPLL_CNTL_MODE__SI__CI 0x0AEC -#define mmMPLL_CONTROL__SI__CI 0x0AF5 -#define mmMPLL_DQ_0_0_STATUS__SI__CI 0x0AF7 -#define mmMPLL_DQ_0_1_STATUS__SI__CI 0x0AF8 -#define mmMPLL_DQ_1_0_STATUS__SI__CI 0x0AF9 -#define mmMPLL_DQ_1_1_STATUS__SI__CI 0x0AFA -#define mmMPLL_DQ_FUNC_CNTL__SI__CI 0x0AF1 -#define mmMPLL_FUNC_CNTL__SI__CI 0x0AED -#define mmMPLL_FUNC_CNTL_1__SI__CI 0x0AEE -#define mmMPLL_FUNC_CNTL_2__SI__CI 0x0AEF -#define mmMPLL_SEQ_UCODE_1__SI__CI 0x0AEA -#define mmMPLL_SEQ_UCODE_2__SI__CI 0x0AEB -#define mmMPLL_SS1__SI__CI 0x0AF3 -#define mmMPLL_SS2__SI__CI 0x0AF4 -#define mmMPLL_TIME__SI__CI 0x0AF2 -#define mmMPRD_BUF_SIZE__SI 0x3888 -#define mmMPRD_BUF_WIDTH__SI 0x389C -#define mmMPRD_BYPASS_PITCH__SI 0x3895 -#define mmMPRD_CNTRL__SI 0x3880 -#define mmMPRD_DBW_BUF_SIZE__SI 0x3897 -#define mmMPRD_HW_DEBUG__SI 0x3883 -#define mmMPRD_OUTOFRANGE_PIXELS__SI 0x389D -#define mmMPRD_STATUS__SI 0x3881 -#define mmMP_BUF_MAP__SI 0x3FBC -#define mmMP_BUF_NUM__SI 0x3F8B -#define mmMP_BUF_SIZE__SI 0x3F86 -#define mmMP_CACHE_CTRL__SI 0x3FBD -#define mmMP_CACHE_PERF_COUNTER__SI 0x3FBE -#define mmMP_CACHE_SRAM_RM_CTL__SI 0x3FBF -#define mmMP_CF_DAT__SI 0x3F8C -#define mmMP_COL_INFO__SI 0x3F94 -#define mmMP_COL_PIC_BOTTOM__SI 0x3F93 -#define mmMP_COL_PIC_TOP__SI 0x3F92 -#define mmMP_CTL__SI 0x3F82 -#define mmMP_CURR_PIC_BOTTOM__SI 0x3F91 -#define mmMP_CURR_PIC_TOP__SI 0x3F90 -#define mmMP_DEBUG_INT_STAT__SI 0x3FB7 -#define mmMP_HW_DEBUG__SI 0x3FB6 -#define mmMP_INT_EN__SI 0x3F80 -#define mmMP_INT_STAT__SI 0x3F81 -#define mmMP_LISTX0_0__SI 0x3F95 -#define mmMP_LISTX0_10__SI 0x3F9F -#define mmMP_LISTX0_11__SI 0x3FA0 -#define mmMP_LISTX0_12__SI 0x3FA1 -#define mmMP_LISTX0_13__SI 0x3FA2 -#define mmMP_LISTX0_14__SI 0x3FA3 -#define mmMP_LISTX0_15__SI 0x3FA4 -#define mmMP_LISTX0_1__SI 0x3F96 -#define mmMP_LISTX0_2__SI 0x3F97 -#define mmMP_LISTX0_3__SI 0x3F98 -#define mmMP_LISTX0_4__SI 0x3F99 -#define mmMP_LISTX0_5__SI 0x3F9A -#define mmMP_LISTX0_6__SI 0x3F9B -#define mmMP_LISTX0_7__SI 0x3F9C -#define mmMP_LISTX0_8__SI 0x3F9D -#define mmMP_LISTX0_9__SI 0x3F9E -#define mmMP_LISTX1_0__SI 0x3FA5 -#define mmMP_LISTX1_10__SI 0x3FAF -#define mmMP_LISTX1_11__SI 0x3FB0 -#define mmMP_LISTX1_12__SI 0x3FB1 -#define mmMP_LISTX1_13__SI 0x3FB2 -#define mmMP_LISTX1_14__SI 0x3FB3 -#define mmMP_LISTX1_15__SI 0x3FB4 -#define mmMP_LISTX1_1__SI 0x3FA6 -#define mmMP_LISTX1_2__SI 0x3FA7 -#define mmMP_LISTX1_3__SI 0x3FA8 -#define mmMP_LISTX1_4__SI 0x3FA9 -#define mmMP_LISTX1_5__SI 0x3FAA -#define mmMP_LISTX1_6__SI 0x3FAB -#define mmMP_LISTX1_7__SI 0x3FAC -#define mmMP_LISTX1_8__SI 0x3FAD -#define mmMP_LISTX1_9__SI 0x3FAE -#define mmMP_LMA_ADR__SI 0x3F8E -#define mmMP_LMA_CTL__SI 0x3F8D -#define mmMP_LMA_DAT__SI 0x3F8F -#define mmMP_PPS_INFO__SI 0x3F89 -#define mmMP_SLICE_INFO__SI 0x3F8A -#define mmMP_SPS_INFO__SI 0x3F88 -#define mmMP_SRAM_RM_CTL__SI 0x3FB5 -#define mmMP_STAT__SI 0x3F83 -#define mmMP_VC1_DONE_CTXT__SI 0x3FBA -#define mmMP_VC1_PPS_INFO__SI 0x3FB8 -#define mmMP_VC1_REF_INFO__SI 0x3FB9 -#define mmMP_VC1_USE_HYBRIDPRED__SI 0x3FBB -#define mmMVP_AFR_FLIP_FIFO_CNTL__SI 0x1AD9 -#define mmMVP_AFR_FLIP_MODE__SI 0x1AD8 -#define mmMVP_BLACK_KEYER__SI 0x1686 -#define mmMVP_CONTROL1__SI 0x1680 -#define mmMVP_CONTROL2__SI 0x1681 -#define mmMVP_CONTROL3__SI 0x168A -#define mmMVP_CRC_CNTL__SI 0x1687 -#define mmMVP_CRC_RESULT_BLUE_GREEN__SI 0x1688 -#define mmMVP_CRC_RESULT_RED__SI 0x1689 -#define mmMVP_FIFO_CONTROL__SI 0x1682 -#define mmMVP_FIFO_STATUS__SI 0x1683 -#define mmMVP_FLIP_LINE_NUM_INSERT__SI 0x1ADA -#define mmMVP_INBAND_CNTL_CAP__SI 0x1685 -#define mmMVP_RECEIVE_CNT_CNTL1__SI 0x168B -#define mmMVP_RECEIVE_CNT_CNTL2__SI 0x168C -#define mmMVP_SLAVE_STATUS__SI 0x1684 -#define mmMVP_TEST_DEBUG_DATA__SI 0x168E -#define mmMVP_TEST_DEBUG_INDEX__SI 0x168D -#define mmNEW_REFCLKB_TIMER_1__CI 0x1484 -#define mmNEW_REFCLKB_TIMER__CI 0x1485 -#define mmOPEN_DRAIN_SELECT__SI 0x01EC -#define mmOVLSCL_EDGE_PIXEL_CNTL__SI 0x1A2C -#define mmOVL_ALPHA_CONTROL__SI 0x1A50 -#define mmOVL_ALPHA__SI 0x1A4F -#define mmOVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI 0x1A10 -#define mmOVL_CONTROL1__SI 0x1A1D -#define mmOVL_CONTROL2__SI 0x1A1E -#define mmOVL_DFQ_CONTROL__SI 0x1A29 -#define mmOVL_DFQ_STATUS__SI 0x1A2A -#define mmOVL_ENABLE__SI 0x1A1C -#define mmOVL_END__SI 0x1A26 -#define mmOVL_KEY_ALPHA__SI 0x1A58 -#define mmOVL_KEY_CONTROL__SI 0x1A4D -#define mmOVL_KEY_RANGE_BLUE_CB__SI 0x1A57 -#define mmOVL_KEY_RANGE_GREEN_Y__SI 0x1A56 -#define mmOVL_KEY_RANGE_RED_CR__SI 0x1A55 -#define mmOVL_MATRIX_COEF_1_1__SI 0x1A2E -#define mmOVL_MATRIX_COEF_1_2__SI 0x1A2F -#define mmOVL_MATRIX_COEF_1_3__SI 0x1A30 -#define mmOVL_MATRIX_COEF_1_4__SI 0x1A31 -#define mmOVL_MATRIX_COEF_2_1__SI 0x1A32 -#define mmOVL_MATRIX_COEF_2_2__SI 0x1A33 -#define mmOVL_MATRIX_COEF_2_3__SI 0x1A34 -#define mmOVL_MATRIX_COEF_2_4__SI 0x1A35 -#define mmOVL_MATRIX_COEF_3_1__SI 0x1A36 -#define mmOVL_MATRIX_COEF_3_2__SI 0x1A37 -#define mmOVL_MATRIX_COEF_3_3__SI 0x1A38 -#define mmOVL_MATRIX_COEF_3_4__SI 0x1A39 -#define mmOVL_MATRIX_TRANSFORM_EN__SI 0x1A2D -#define mmOVL_PITCH__SI 0x1A21 -#define mmOVL_PWL_0TOF__SI 0x1A3B -#define mmOVL_PWL_100TO13F__SI 0x1A41 -#define mmOVL_PWL_10TO1F__SI 0x1A3C -#define mmOVL_PWL_140TO17F__SI 0x1A42 -#define mmOVL_PWL_180TO1BF__SI 0x1A43 -#define mmOVL_PWL_1C0TO1FF__SI 0x1A44 -#define mmOVL_PWL_200TO23F__SI 0x1A45 -#define mmOVL_PWL_20TO3F__SI 0x1A3D -#define mmOVL_PWL_240TO27F__SI 0x1A46 -#define mmOVL_PWL_280TO2BF__SI 0x1A47 -#define mmOVL_PWL_2C0TO2FF__SI 0x1A48 -#define mmOVL_PWL_300TO33F__SI 0x1A49 -#define mmOVL_PWL_340TO37F__SI 0x1A4A -#define mmOVL_PWL_380TO3BF__SI 0x1A4B -#define mmOVL_PWL_3C0TO3FF__SI 0x1A4C -#define mmOVL_PWL_40TO7F__SI 0x1A3E -#define mmOVL_PWL_80TOBF__SI 0x1A3F -#define mmOVL_PWL_C0TOFF__SI 0x1A40 -#define mmOVL_PWL_TRANSFORM_EN__SI 0x1A3A -#define mmOVL_RT_BAND_POSITION__SI 0x1AD6 -#define mmOVL_RT_PROCEED_COND__SI 0x1AD7 -#define mmOVL_RT_SKEWCOMMAND__SI 0x1AD4 -#define mmOVL_RT_SKEWCONTROL__SI 0x1AD5 -#define mmOVL_RT_STAT__SI 0x1AF4 -#define mmOVL_START__SI 0x1A25 -#define mmOVL_SURFACE_ADDRESS 0x1A20 -#define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22 -#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE__SI 0x1A2B -#define mmOVL_SURFACE_ADDRESS_INUSE__SI 0x1A28 -#define mmOVL_SURFACE_OFFSET_X__SI 0x1A23 -#define mmOVL_SURFACE_OFFSET_Y__SI 0x1A24 -#define mmOVL_SWAP_CNTL__SI 0x1A1F -#define mmOVL_UPDATE__SI 0x1A27 -#define mmP1PLL_CNTL__SI 0x0114 -#define mmP1PLL_DEBUG_CLK_SEL__SI 0x014A -#define mmP1PLL_DS_CNTL__SI 0x015A -#define mmP1PLL_IDCLKA_CNTL__SI 0x0118 -#define mmP1PLL_INT_SS_CNTL__SI 0x0116 -#define mmP1PLL_UNLOCK_DETECT_CNTL__SI 0x010A -#define mmP1PLL_VREG_CNTL__SI 0x015C -#define mmP2PLL_CNTL__SI 0x0115 -#define mmP2PLL_DEBUG_CLK_SEL__SI 0x014B -#define mmP2PLL_DS_CNTL__SI 0x015B -#define mmP2PLL_IDCLKB_CNTL__SI 0x0119 -#define mmP2PLL_INT_SS_CNTL__SI 0x0117 -#define mmP2PLL_UNLOCK_DETECT_CNTL__SI 0x010B -#define mmP2PLL_VREG_CNTL__SI 0x015D -#define mmPAGE_MIRROR_CNTL__SI 0x0581 -#define mmPA_CL_CLIP_CNTL 0xA204 -#define mmPA_CL_CNTL_STATUS 0x2284 -#define mmPA_CL_ENHANCE 0x2285 -#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA2FC -#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA2FD -#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA2FA -#define mmPA_CL_GB_VERT_DISC_ADJ 0xA2FB -#define mmPA_CL_NANINF_CNTL 0xA208 -#define mmPA_CL_POINT_CULL_RAD 0xA1F8 -#define mmPA_CL_POINT_SIZE 0xA1F7 -#define mmPA_CL_POINT_X_RAD 0xA1F5 -#define mmPA_CL_POINT_Y_RAD 0xA1F6 -#define mmPA_CL_RESET_DEBUG__CI__VI 0x2286 -#define mmPA_CL_UCP_0_W 0xA172 -#define mmPA_CL_UCP_0_X 0xA16F -#define mmPA_CL_UCP_0_Y 0xA170 -#define mmPA_CL_UCP_0_Z 0xA171 -#define mmPA_CL_UCP_1_W 0xA176 -#define mmPA_CL_UCP_1_X 0xA173 -#define mmPA_CL_UCP_1_Y 0xA174 -#define mmPA_CL_UCP_1_Z 0xA175 -#define mmPA_CL_UCP_2_W 0xA17A -#define mmPA_CL_UCP_2_X 0xA177 -#define mmPA_CL_UCP_2_Y 0xA178 -#define mmPA_CL_UCP_2_Z 0xA179 -#define mmPA_CL_UCP_3_W 0xA17E -#define mmPA_CL_UCP_3_X 0xA17B -#define mmPA_CL_UCP_3_Y 0xA17C -#define mmPA_CL_UCP_3_Z 0xA17D -#define mmPA_CL_UCP_4_W 0xA182 -#define mmPA_CL_UCP_4_X 0xA17F -#define mmPA_CL_UCP_4_Y 0xA180 -#define mmPA_CL_UCP_4_Z 0xA181 -#define mmPA_CL_UCP_5_W 0xA186 -#define mmPA_CL_UCP_5_X 0xA183 -#define mmPA_CL_UCP_5_Y 0xA184 -#define mmPA_CL_UCP_5_Z 0xA185 -#define mmPA_CL_VPORT_XOFFSET 0xA110 -#define mmPA_CL_VPORT_XOFFSET_1 0xA116 -#define mmPA_CL_VPORT_XOFFSET_10 0xA14C -#define mmPA_CL_VPORT_XOFFSET_11 0xA152 -#define mmPA_CL_VPORT_XOFFSET_12 0xA158 -#define mmPA_CL_VPORT_XOFFSET_13 0xA15E -#define mmPA_CL_VPORT_XOFFSET_14 0xA164 -#define mmPA_CL_VPORT_XOFFSET_15 0xA16A -#define mmPA_CL_VPORT_XOFFSET_2 0xA11C -#define mmPA_CL_VPORT_XOFFSET_3 0xA122 -#define mmPA_CL_VPORT_XOFFSET_4 0xA128 -#define mmPA_CL_VPORT_XOFFSET_5 0xA12E -#define mmPA_CL_VPORT_XOFFSET_6 0xA134 -#define mmPA_CL_VPORT_XOFFSET_7 0xA13A -#define mmPA_CL_VPORT_XOFFSET_8 0xA140 -#define mmPA_CL_VPORT_XOFFSET_9 0xA146 -#define mmPA_CL_VPORT_XSCALE 0xA10F -#define mmPA_CL_VPORT_XSCALE_1 0xA115 -#define mmPA_CL_VPORT_XSCALE_10 0xA14B -#define mmPA_CL_VPORT_XSCALE_11 0xA151 -#define mmPA_CL_VPORT_XSCALE_12 0xA157 -#define mmPA_CL_VPORT_XSCALE_13 0xA15D -#define mmPA_CL_VPORT_XSCALE_14 0xA163 -#define mmPA_CL_VPORT_XSCALE_15 0xA169 -#define mmPA_CL_VPORT_XSCALE_2 0xA11B -#define mmPA_CL_VPORT_XSCALE_3 0xA121 -#define mmPA_CL_VPORT_XSCALE_4 0xA127 -#define mmPA_CL_VPORT_XSCALE_5 0xA12D -#define mmPA_CL_VPORT_XSCALE_6 0xA133 -#define mmPA_CL_VPORT_XSCALE_7 0xA139 -#define mmPA_CL_VPORT_XSCALE_8 0xA13F -#define mmPA_CL_VPORT_XSCALE_9 0xA145 -#define mmPA_CL_VPORT_YOFFSET 0xA112 -#define mmPA_CL_VPORT_YOFFSET_1 0xA118 -#define mmPA_CL_VPORT_YOFFSET_10 0xA14E -#define mmPA_CL_VPORT_YOFFSET_11 0xA154 -#define mmPA_CL_VPORT_YOFFSET_12 0xA15A -#define mmPA_CL_VPORT_YOFFSET_13 0xA160 -#define mmPA_CL_VPORT_YOFFSET_14 0xA166 -#define mmPA_CL_VPORT_YOFFSET_15 0xA16C -#define mmPA_CL_VPORT_YOFFSET_2 0xA11E -#define mmPA_CL_VPORT_YOFFSET_3 0xA124 -#define mmPA_CL_VPORT_YOFFSET_4 0xA12A -#define mmPA_CL_VPORT_YOFFSET_5 0xA130 -#define mmPA_CL_VPORT_YOFFSET_6 0xA136 -#define mmPA_CL_VPORT_YOFFSET_7 0xA13C -#define mmPA_CL_VPORT_YOFFSET_8 0xA142 -#define mmPA_CL_VPORT_YOFFSET_9 0xA148 -#define mmPA_CL_VPORT_YSCALE 0xA111 -#define mmPA_CL_VPORT_YSCALE_1 0xA117 -#define mmPA_CL_VPORT_YSCALE_10 0xA14D -#define mmPA_CL_VPORT_YSCALE_11 0xA153 -#define mmPA_CL_VPORT_YSCALE_12 0xA159 -#define mmPA_CL_VPORT_YSCALE_13 0xA15F -#define mmPA_CL_VPORT_YSCALE_14 0xA165 -#define mmPA_CL_VPORT_YSCALE_15 0xA16B -#define mmPA_CL_VPORT_YSCALE_2 0xA11D -#define mmPA_CL_VPORT_YSCALE_3 0xA123 -#define mmPA_CL_VPORT_YSCALE_4 0xA129 -#define mmPA_CL_VPORT_YSCALE_5 0xA12F -#define mmPA_CL_VPORT_YSCALE_6 0xA135 -#define mmPA_CL_VPORT_YSCALE_7 0xA13B -#define mmPA_CL_VPORT_YSCALE_8 0xA141 -#define mmPA_CL_VPORT_YSCALE_9 0xA147 -#define mmPA_CL_VPORT_ZOFFSET 0xA114 -#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A -#define mmPA_CL_VPORT_ZOFFSET_10 0xA150 -#define mmPA_CL_VPORT_ZOFFSET_11 0xA156 -#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C -#define mmPA_CL_VPORT_ZOFFSET_13 0xA162 -#define mmPA_CL_VPORT_ZOFFSET_14 0xA168 -#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E -#define mmPA_CL_VPORT_ZOFFSET_2 0xA120 -#define mmPA_CL_VPORT_ZOFFSET_3 0xA126 -#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C -#define mmPA_CL_VPORT_ZOFFSET_5 0xA132 -#define mmPA_CL_VPORT_ZOFFSET_6 0xA138 -#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E -#define mmPA_CL_VPORT_ZOFFSET_8 0xA144 -#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A -#define mmPA_CL_VPORT_ZSCALE 0xA113 -#define mmPA_CL_VPORT_ZSCALE_1 0xA119 -#define mmPA_CL_VPORT_ZSCALE_10 0xA14F -#define mmPA_CL_VPORT_ZSCALE_11 0xA155 -#define mmPA_CL_VPORT_ZSCALE_12 0xA15B -#define mmPA_CL_VPORT_ZSCALE_13 0xA161 -#define mmPA_CL_VPORT_ZSCALE_14 0xA167 -#define mmPA_CL_VPORT_ZSCALE_15 0xA16D -#define mmPA_CL_VPORT_ZSCALE_2 0xA11F -#define mmPA_CL_VPORT_ZSCALE_3 0xA125 -#define mmPA_CL_VPORT_ZSCALE_4 0xA12B -#define mmPA_CL_VPORT_ZSCALE_5 0xA131 -#define mmPA_CL_VPORT_ZSCALE_6 0xA137 -#define mmPA_CL_VPORT_ZSCALE_7 0xA13D -#define mmPA_CL_VPORT_ZSCALE_8 0xA143 -#define mmPA_CL_VPORT_ZSCALE_9 0xA149 -#define mmPA_CL_VS_OUT_CNTL 0xA207 -#define mmPA_CL_VTE_CNTL 0xA206 -#define mmPA_SC_AA_CONFIG 0xA2F8 -#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xA30E -#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xA30F -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xA2FE -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xA2FF -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xA300 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xA301 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xA306 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xA307 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xA308 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xA309 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xA302 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xA303 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xA304 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xA305 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xA30A -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xA30B -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xA30C -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xA30D -#define mmPA_SC_CENTROID_PRIORITY_0 0xA2F5 -#define mmPA_SC_CENTROID_PRIORITY_1 0xA2F6 -#define mmPA_SC_CLIPRECT_0_BR 0xA085 -#define mmPA_SC_CLIPRECT_0_TL 0xA084 -#define mmPA_SC_CLIPRECT_1_BR 0xA087 -#define mmPA_SC_CLIPRECT_1_TL 0xA086 -#define mmPA_SC_CLIPRECT_2_BR 0xA089 -#define mmPA_SC_CLIPRECT_2_TL 0xA088 -#define mmPA_SC_CLIPRECT_3_BR 0xA08B -#define mmPA_SC_CLIPRECT_3_TL 0xA08A -#define mmPA_SC_CLIPRECT_RULE 0xA083 -#define mmPA_SC_DEBUG_CNTL 0x22F6 -#define mmPA_SC_DEBUG_DATA 0x22F7 -#define mmPA_SC_EDGERULE 0xA08C -#define mmPA_SC_ENHANCE 0x22FC -#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 -#define mmPA_SC_FIFO_SIZE 0x22F3 -#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22C9 -#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091 -#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090 -#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI 0xC2AC -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI 0xC2A8 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI 0x22C1 -#define mmPA_SC_HP3D_TRAP_SCREEN_H__CI__VI 0xC2A9 -#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI 0xC2AB -#define mmPA_SC_HP3D_TRAP_SCREEN_V__CI__VI 0xC2AA -#define mmPA_SC_IF_FIFO_SIZE 0x22F5 -#define mmPA_SC_LINE_CNTL 0xA2F7 -#define mmPA_SC_LINE_STIPPLE 0xA283 -#define mmPA_SC_LINE_STIPPLE_STATE__CI__VI 0xC281 -#define mmPA_SC_LINE_STIPPLE_STATE__SI 0x22C4 -#define mmPA_SC_MODE_CNTL_0 0xA292 -#define mmPA_SC_MODE_CNTL_1 0xA293 -#define mmPA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI 0xC2A4 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI 0xC2A0 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI 0x22C0 -#define mmPA_SC_P3D_TRAP_SCREEN_H__CI__VI 0xC2A1 -#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI 0xC2A3 -#define mmPA_SC_P3D_TRAP_SCREEN_V__CI__VI 0xC2A2 -#define mmPA_SC_PERFCOUNTER0_HI__CI__VI 0xD141 -#define mmPA_SC_PERFCOUNTER0_HI__SI 0x22A9 -#define mmPA_SC_PERFCOUNTER0_LO__CI__VI 0xD140 -#define mmPA_SC_PERFCOUNTER0_LO__SI 0x22A8 -#define mmPA_SC_PERFCOUNTER0_SELECT1__CI__VI 0xD941 -#define mmPA_SC_PERFCOUNTER0_SELECT__CI__VI 0xD940 -#define mmPA_SC_PERFCOUNTER0_SELECT__SI 0x22A0 -#define mmPA_SC_PERFCOUNTER1_HI__CI__VI 0xD143 -#define mmPA_SC_PERFCOUNTER1_HI__SI 0x22AB -#define mmPA_SC_PERFCOUNTER1_LO__CI__VI 0xD142 -#define mmPA_SC_PERFCOUNTER1_LO__SI 0x22AA -#define mmPA_SC_PERFCOUNTER1_SELECT__CI__VI 0xD942 -#define mmPA_SC_PERFCOUNTER1_SELECT__SI 0x22A1 -#define mmPA_SC_PERFCOUNTER2_HI__CI__VI 0xD145 -#define mmPA_SC_PERFCOUNTER2_HI__SI 0x22AD -#define mmPA_SC_PERFCOUNTER2_LO__CI__VI 0xD144 -#define mmPA_SC_PERFCOUNTER2_LO__SI 0x22AC -#define mmPA_SC_PERFCOUNTER2_SELECT__CI__VI 0xD943 -#define mmPA_SC_PERFCOUNTER2_SELECT__SI 0x22A2 -#define mmPA_SC_PERFCOUNTER3_HI__CI__VI 0xD147 -#define mmPA_SC_PERFCOUNTER3_HI__SI 0x22AF -#define mmPA_SC_PERFCOUNTER3_LO__CI__VI 0xD146 -#define mmPA_SC_PERFCOUNTER3_LO__SI 0x22AE -#define mmPA_SC_PERFCOUNTER3_SELECT__CI__VI 0xD944 -#define mmPA_SC_PERFCOUNTER3_SELECT__SI 0x22A3 -#define mmPA_SC_PERFCOUNTER4_HI__CI__VI 0xD149 -#define mmPA_SC_PERFCOUNTER4_HI__SI 0x22B1 -#define mmPA_SC_PERFCOUNTER4_LO__CI__VI 0xD148 -#define mmPA_SC_PERFCOUNTER4_LO__SI 0x22B0 -#define mmPA_SC_PERFCOUNTER4_SELECT__CI__VI 0xD945 -#define mmPA_SC_PERFCOUNTER4_SELECT__SI 0x22A4 -#define mmPA_SC_PERFCOUNTER5_HI__CI__VI 0xD14B -#define mmPA_SC_PERFCOUNTER5_HI__SI 0x22B3 -#define mmPA_SC_PERFCOUNTER5_LO__CI__VI 0xD14A -#define mmPA_SC_PERFCOUNTER5_LO__SI 0x22B2 -#define mmPA_SC_PERFCOUNTER5_SELECT__CI__VI 0xD946 -#define mmPA_SC_PERFCOUNTER5_SELECT__SI 0x22A5 -#define mmPA_SC_PERFCOUNTER6_HI__CI__VI 0xD14D -#define mmPA_SC_PERFCOUNTER6_HI__SI 0x22B5 -#define mmPA_SC_PERFCOUNTER6_LO__CI__VI 0xD14C -#define mmPA_SC_PERFCOUNTER6_LO__SI 0x22B4 -#define mmPA_SC_PERFCOUNTER6_SELECT__CI__VI 0xD947 -#define mmPA_SC_PERFCOUNTER6_SELECT__SI 0x22A6 -#define mmPA_SC_PERFCOUNTER7_HI__CI__VI 0xD14F -#define mmPA_SC_PERFCOUNTER7_HI__SI 0x22B7 -#define mmPA_SC_PERFCOUNTER7_LO__CI__VI 0xD14E -#define mmPA_SC_PERFCOUNTER7_LO__SI 0x22B6 -#define mmPA_SC_PERFCOUNTER7_SELECT__CI__VI 0xD948 -#define mmPA_SC_PERFCOUNTER7_SELECT__SI 0x22A7 -#define mmPA_SC_RASTER_CONFIG 0xA0D4 -#define mmPA_SC_RASTER_CONFIG_1__CI__VI 0xA0D5 -#define mmPA_SC_SCREEN_EXTENT_CONTROL__CI__VI 0xA0D6 -#define mmPA_SC_SCREEN_EXTENT_MAX_0__CI__VI 0xC285 -#define mmPA_SC_SCREEN_EXTENT_MAX_1__CI__VI 0xC28B -#define mmPA_SC_SCREEN_EXTENT_MIN_0__CI__VI 0xC284 -#define mmPA_SC_SCREEN_EXTENT_MIN_1__CI__VI 0xC286 -#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D -#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C -#define mmPA_SC_TRAP_SCREEN_COUNT__CI__VI 0xC2B4 -#define mmPA_SC_TRAP_SCREEN_HV_EN__CI__VI 0xC2B0 -#define mmPA_SC_TRAP_SCREEN_HV_LOCK__CI__VI 0x22C2 -#define mmPA_SC_TRAP_SCREEN_H__CI__VI 0xC2B1 -#define mmPA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI 0xC2B3 -#define mmPA_SC_TRAP_SCREEN_V__CI__VI 0xC2B2 -#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095 -#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094 -#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9 -#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8 -#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB -#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA -#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD -#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC -#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF -#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE -#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1 -#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0 -#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3 -#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2 -#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097 -#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096 -#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099 -#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098 -#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B -#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A -#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D -#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C -#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F -#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E -#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1 -#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0 -#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3 -#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2 -#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5 -#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4 -#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7 -#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6 -#define mmPA_SC_VPORT_ZMAX_0 0xA0B5 -#define mmPA_SC_VPORT_ZMAX_1 0xA0B7 -#define mmPA_SC_VPORT_ZMAX_10 0xA0C9 -#define mmPA_SC_VPORT_ZMAX_11 0xA0CB -#define mmPA_SC_VPORT_ZMAX_12 0xA0CD -#define mmPA_SC_VPORT_ZMAX_13 0xA0CF -#define mmPA_SC_VPORT_ZMAX_14 0xA0D1 -#define mmPA_SC_VPORT_ZMAX_15 0xA0D3 -#define mmPA_SC_VPORT_ZMAX_2 0xA0B9 -#define mmPA_SC_VPORT_ZMAX_3 0xA0BB -#define mmPA_SC_VPORT_ZMAX_4 0xA0BD -#define mmPA_SC_VPORT_ZMAX_5 0xA0BF -#define mmPA_SC_VPORT_ZMAX_6 0xA0C1 -#define mmPA_SC_VPORT_ZMAX_7 0xA0C3 -#define mmPA_SC_VPORT_ZMAX_8 0xA0C5 -#define mmPA_SC_VPORT_ZMAX_9 0xA0C7 -#define mmPA_SC_VPORT_ZMIN_0 0xA0B4 -#define mmPA_SC_VPORT_ZMIN_1 0xA0B6 -#define mmPA_SC_VPORT_ZMIN_10 0xA0C8 -#define mmPA_SC_VPORT_ZMIN_11 0xA0CA -#define mmPA_SC_VPORT_ZMIN_12 0xA0CC -#define mmPA_SC_VPORT_ZMIN_13 0xA0CE -#define mmPA_SC_VPORT_ZMIN_14 0xA0D0 -#define mmPA_SC_VPORT_ZMIN_15 0xA0D2 -#define mmPA_SC_VPORT_ZMIN_2 0xA0B8 -#define mmPA_SC_VPORT_ZMIN_3 0xA0BA -#define mmPA_SC_VPORT_ZMIN_4 0xA0BC -#define mmPA_SC_VPORT_ZMIN_5 0xA0BE -#define mmPA_SC_VPORT_ZMIN_6 0xA0C0 -#define mmPA_SC_VPORT_ZMIN_7 0xA0C2 -#define mmPA_SC_VPORT_ZMIN_8 0xA0C4 -#define mmPA_SC_VPORT_ZMIN_9 0xA0C6 -#define mmPA_SC_WINDOW_OFFSET 0xA080 -#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082 -#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081 -#define mmPA_SU_CNTL_STATUS 0x2294 -#define mmPA_SU_DEBUG_CNTL 0x2280 -#define mmPA_SU_DEBUG_DATA 0x2281 -#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xA08D -#define mmPA_SU_LINE_CNTL 0xA282 -#define mmPA_SU_LINE_STIPPLE_CNTL 0xA209 -#define mmPA_SU_LINE_STIPPLE_SCALE 0xA20A -#define mmPA_SU_LINE_STIPPLE_VALUE__CI__VI 0xC280 -#define mmPA_SU_LINE_STIPPLE_VALUE__SI 0x2298 -#define mmPA_SU_PERFCOUNTER0_HI__CI__VI 0xD101 -#define mmPA_SU_PERFCOUNTER0_HI__SI 0x228D -#define mmPA_SU_PERFCOUNTER0_LO__CI__VI 0xD100 -#define mmPA_SU_PERFCOUNTER0_LO__SI 0x228C -#define mmPA_SU_PERFCOUNTER0_SELECT1__CI__VI 0xD901 -#define mmPA_SU_PERFCOUNTER0_SELECT__CI__VI 0xD900 -#define mmPA_SU_PERFCOUNTER0_SELECT__SI 0x2288 -#define mmPA_SU_PERFCOUNTER1_HI__CI__VI 0xD103 -#define mmPA_SU_PERFCOUNTER1_HI__SI 0x228F -#define mmPA_SU_PERFCOUNTER1_LO__CI__VI 0xD102 -#define mmPA_SU_PERFCOUNTER1_LO__SI 0x228E -#define mmPA_SU_PERFCOUNTER1_SELECT1__CI__VI 0xD903 -#define mmPA_SU_PERFCOUNTER1_SELECT__CI__VI 0xD902 -#define mmPA_SU_PERFCOUNTER1_SELECT__SI 0x2289 -#define mmPA_SU_PERFCOUNTER2_HI__CI__VI 0xD105 -#define mmPA_SU_PERFCOUNTER2_HI__SI 0x2291 -#define mmPA_SU_PERFCOUNTER2_LO__CI__VI 0xD104 -#define mmPA_SU_PERFCOUNTER2_LO__SI 0x2290 -#define mmPA_SU_PERFCOUNTER2_SELECT__CI__VI 0xD904 -#define mmPA_SU_PERFCOUNTER2_SELECT__SI 0x228A -#define mmPA_SU_PERFCOUNTER3_HI__CI__VI 0xD107 -#define mmPA_SU_PERFCOUNTER3_HI__SI 0x2293 -#define mmPA_SU_PERFCOUNTER3_LO__CI__VI 0xD106 -#define mmPA_SU_PERFCOUNTER3_LO__SI 0x2292 -#define mmPA_SU_PERFCOUNTER3_SELECT__CI__VI 0xD905 -#define mmPA_SU_PERFCOUNTER3_SELECT__SI 0x228B -#define mmPA_SU_POINT_MINMAX 0xA281 -#define mmPA_SU_POINT_SIZE 0xA280 -#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA2E3 -#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA2E2 -#define mmPA_SU_POLY_OFFSET_CLAMP 0xA2DF -#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA2DE -#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA2E1 -#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA2E0 -#define mmPA_SU_PRIM_FILTER_CNTL 0xA20B -#define mmPA_SU_SC_MODE_CNTL 0xA205 -#define mmPA_SU_VTX_CNTL 0xA2F9 -#define mmPCIE_DATA_2__CI__VI 0x000D -#define mmPCIE_DATA__CI__VI 0x000F -#define mmPCIE_DATA__SI 0x000D -#define mmPCIE_INDEX_2__CI__VI 0x000C -#define mmPCIE_INDEX__CI__VI 0x000E -#define mmPCIE_INDEX__SI 0x000C -#define mmPCIE_PORT_DATA__SI 0x000F -#define mmPCIE_PORT_INDEX__SI 0x000E -#define mmPEER0_FB_OFFSET_HI__CI__VI 0x14F3 -#define mmPEER0_FB_OFFSET_LO__CI__VI 0x14F2 -#define mmPEER1_FB_OFFSET_HI__CI__VI 0x14F1 -#define mmPEER1_FB_OFFSET_LO__CI__VI 0x14F0 -#define mmPEER2_FB_OFFSET_HI__CI__VI 0x14EF -#define mmPEER2_FB_OFFSET_LO__CI__VI 0x14EE -#define mmPEER3_FB_OFFSET_HI__CI__VI 0x14ED -#define mmPEER3_FB_OFFSET_LO__CI__VI 0x14EC -#define mmPEER_REG_RANGE0 0x153E -#define mmPEER_REG_RANGE1 0x153F -#define mmPHY_AUX_CNTL__SI 0x1953 -#define mmPHY_PAD_FORCE_DIS1__SI 0x1532 -#define mmPHY_PAD_FORCE_DIS2__SI 0x1533 -#define mmPHY_PAD_FORCE_EN1__SI 0x1530 -#define mmPHY_PAD_FORCE_EN2__SI 0x1531 -#define mmPHY_TESTMODES__SI 0x1518 -#define mmPIPE0_ARBITRATION_CONTROL1__SI 0x02FA -#define mmPIPE0_ARBITRATION_CONTROL2__SI 0x02FB -#define mmPIPE0_ARBITRATION_CONTROL3__SI 0x02FC -#define mmPIPE0_URGENCY_CONTROL__SI 0x02FD -#define mmPIPE1_ARBITRATION_CONTROL1__SI 0x02FE -#define mmPIPE1_ARBITRATION_CONTROL2__SI 0x02FF -#define mmPIPE1_ARBITRATION_CONTROL3__SI 0x0300 -#define mmPIPE1_URGENCY_CONTROL__SI 0x0301 -#define mmPIPE2_ARBITRATION_CONTROL1__SI 0x0302 -#define mmPIPE2_ARBITRATION_CONTROL2__SI 0x0303 -#define mmPIPE2_ARBITRATION_CONTROL3__SI 0x0304 -#define mmPIPE2_URGENCY_CONTROL__SI 0x0305 -#define mmPIPE3_ARBITRATION_CONTROL1__SI 0x0306 -#define mmPIPE3_ARBITRATION_CONTROL2__SI 0x0307 -#define mmPIPE3_ARBITRATION_CONTROL3__SI 0x0308 -#define mmPIPE3_URGENCY_CONTROL__SI 0x0309 -#define mmPIPE4_ARBITRATION_CONTROL1__SI 0x030A -#define mmPIPE4_ARBITRATION_CONTROL2__SI 0x030B -#define mmPIPE4_ARBITRATION_CONTROL3__SI 0x030C -#define mmPIPE4_URGENCY_CONTROL__SI 0x030D -#define mmPIPE5_ARBITRATION_CONTROL1__SI 0x030E -#define mmPIPE5_ARBITRATION_CONTROL2__SI 0x030F -#define mmPIPE5_ARBITRATION_CONTROL3__SI 0x0310 -#define mmPIPE5_URGENCY_CONTROL__SI 0x0311 -#define mmPIXCLK1_RESYNC_CNTL__SI 0x0126 -#define mmPIXCLK2_RESYNC_CNTL__SI 0x0127 -#define mmPLL_TEST_CNTL__SI 0x0199 -#define mmPRIORITY_A_CNT__SI 0x1AC6 -#define mmPRIORITY_B_CNT__SI 0x1AC7 -#define mmPWR_SMC_IND_DATA__CI__VI 0x0081 -#define mmPWR_SMC_IND_DATA_alt_1__CI__VI 0x0083 -#define mmPWR_SMC_IND_DATA_alt_2__CI__VI 0x0085 -#define mmPWR_SMC_IND_DATA_alt_3__CI__VI 0x0087 -#define mmPWR_SMC_IND_INDEX__CI__VI 0x0080 -#define mmPWR_SMC_IND_INDEX_alt_1__CI__VI 0x0082 -#define mmPWR_SMC_IND_INDEX_alt_2__CI__VI 0x0084 -#define mmPWR_SMC_IND_INDEX_alt_3__CI__VI 0x0086 -#define mmRAS_BCI_SIGNATURE0 0x339E -#define mmRAS_BCI_SIGNATURE1 0x339F -#define mmRAS_CB_SIGNATURE0 0x339D -#define mmRAS_DB_SIGNATURE0 0x338B -#define mmRAS_IA_SIGNATURE0 0x3397 -#define mmRAS_IA_SIGNATURE1 0x3398 -#define mmRAS_PA_SIGNATURE0 0x338C -#define mmRAS_SC_SIGNATURE0 0x338F -#define mmRAS_SC_SIGNATURE1 0x3390 -#define mmRAS_SC_SIGNATURE2 0x3391 -#define mmRAS_SC_SIGNATURE3 0x3392 -#define mmRAS_SC_SIGNATURE4 0x3393 -#define mmRAS_SC_SIGNATURE5 0x3394 -#define mmRAS_SC_SIGNATURE6 0x3395 -#define mmRAS_SC_SIGNATURE7 0x3396 -#define mmRAS_SIGNATURE_CONTROL 0x3380 -#define mmRAS_SIGNATURE_MASK 0x3381 -#define mmRAS_SPI_SIGNATURE0 0x3399 -#define mmRAS_SPI_SIGNATURE1 0x339A -#define mmRAS_SQ_SIGNATURE0__SI__CI 0x338E -#define mmRAS_SX_SIGNATURE0 0x3382 -#define mmRAS_SX_SIGNATURE1 0x3383 -#define mmRAS_SX_SIGNATURE2 0x3384 -#define mmRAS_SX_SIGNATURE3 0x3385 -#define mmRAS_TA_SIGNATURE0 0x339B -#define mmRAS_TD_SIGNATURE0 0x339C -#define mmRAS_VGT_SIGNATURE0 0x338D -#define mmRCU_ASIC_SERIAL_NUM0__SI 0x004D -#define mmRCU_ASIC_SERIAL_NUM1__SI 0x004E -#define mmRCU_DYN_RM2__SI 0x005B -#define mmRCU_DYN_RM__SI 0x005A -#define mmRCU_EFUSE_SCRATCH__SI 0x004A -#define mmRCU_FCTRL__SI 0x0044 -#define mmRCU_IND_DATA__SI 0x0041 -#define mmRCU_IND_INDEX__SI 0x0040 -#define mmRCU_MISC_CTRL__SI 0x0043 -#define mmRCU_SCRATCH_0__SI 0x0048 -#define mmRCU_SCRATCH_1__SI 0x0049 -#define mmRCU_SCRATCH_2__SI 0x004B -#define mmRCU_SPARE_EFUSE__SI 0x004F -#define mmRCU_STATUS__SI 0x0047 -#define mmRCU_UC_EVENTS__SI 0x0045 -#define mmRCU_UC_INT__SI 0x0042 -#define mmRCU_UC_ROMRD_INSTR__SI 0x005C -#define mmREQ_FIFO_STAT__SI 0x1AF2 -#define mmRE_CTL2_B__SI 0x3F26 -#define mmRE_CTL2__SI 0x3F1A -#define mmRE_CTL__SI 0x3F02 -#define mmRE_DEBUG_INT_STAT__SI 0x3F16 -#define mmRE_DEBUG_SI_B__SI 0x3F28 -#define mmRE_DEBUG_SI__SI 0x3F15 -#define mmRE_DECODE_CMD__SI 0x3F0F -#define mmRE_HW_DEBUG__SI 0x3F18 -#define mmRE_INT_EN__SI 0x3F00 -#define mmRE_INT_STAT__SI 0x3F01 -#define mmRE_LMA_ADR__SI 0x3F12 -#define mmRE_LMA_CTL__SI 0x3F11 -#define mmRE_LMA_DAT__SI 0x3F13 -#define mmRE_PES_CTL__SI 0x3F1E -#define mmRE_PES_DECODE_CMD__SI 0x3F1C -#define mmRE_PES_RESULT__SI 0x3F1D -#define mmRE_PES_SHIFTER_STAT__SI 0x3F1F -#define mmRE_PPS_INFO__SI 0x3F0C -#define mmRE_RESULT__SI 0x3F10 -#define mmRE_SHIFTER_B_STAT2__SI 0x3F27 -#define mmRE_SHIFTER_CTXT__SI 0x3F19 -#define mmRE_SHIFTER_STAT2__SI 0x3F1B -#define mmRE_SHIFTER_STAT__SI 0x3F0E -#define mmRE_SI_B_CTL__SI 0x3F21 -#define mmRE_SI_B_STAT__SI 0x3F22 -#define mmRE_SI_CTL__SI 0x3F05 -#define mmRE_SI_INT_CTL__SI 0x3F04 -#define mmRE_SI_STAT__SI 0x3F06 -#define mmRE_SLICE_INFO__SI 0x3F0D -#define mmRE_SPS_INFO__SI 0x3F0B -#define mmRE_SRAM_RM_CTL__SI 0x3F14 -#define mmRE_STAT__SI 0x3F03 -#define mmRI_CRC__SI 0x3E04 -#define mmRI_CTL__SI 0x3E02 -#define mmRI_DEBUG_INT_STAT__SI 0x3E03 -#define mmRI_INT_EN__SI 0x3E00 -#define mmRI_INT_STAT__SI 0x3E01 -#define mmRLC_AUTO_PG_CTRL__CI 0x3115 -#define mmRLC_AUTO_PG_CTRL__SI 0x310D -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT__CI 0x30E6 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT__SI 0x30D0 -#define mmRLC_CGCG_CGLS_CTRL__CI 0x3109 -#define mmRLC_CGCG_CGLS_CTRL__SI 0x3101 -#define mmRLC_CGCG_RAMP_CTRL__CI 0x310A -#define mmRLC_CGCG_RAMP_CTRL__SI 0x3102 -#define mmRLC_CGTT_MGCG_OVERRIDE__CI 0x3108 -#define mmRLC_CGTT_MGCG_OVERRIDE__SI 0x3100 -#define mmRLC_CLEARSTATE_RESTORE_BASE__SI 0x30C8 -#define mmRLC_CURRENT_CONTEXT__SI 0x30CD -#define mmRLC_CU_STATUS__CI 0x310E -#define mmRLC_CU_STATUS__SI 0x3106 -#define mmRLC_DEBUG_SELECT__CI 0x30C1 -#define mmRLC_DEBUG_SELECT__SI 0x30C9 -#define mmRLC_DEBUG__CI 0x30C2 -#define mmRLC_DEBUG__SI 0x30CA -#define mmRLC_DRIVER_CPDMA_STATUS__CI 0x30DE -#define mmRLC_DRIVER_CPDMA_STATUS__SI 0x30C7 -#define mmRLC_DRMDMA_CURRENT_CONTEXT__SI 0x30F5 -#define mmRLC_DRMDMA_HB_RPTR__SI 0x30F0 -#define mmRLC_DRMDMA_HB_WPTR_MSB_ADDR__SI 0x30EE -#define mmRLC_DRMDMA_HB_WPTR__SI 0x30EF -#define mmRLC_DRMDMA_RL_BASE__SI 0x30E9 -#define mmRLC_DRMDMA_RL_SIZE__SI 0x30EA -#define mmRLC_DYN_PG_REQUEST__CI 0x310C -#define mmRLC_DYN_PG_REQUEST__SI 0x3104 -#define mmRLC_DYN_PG_STATUS__CI 0x310B -#define mmRLC_DYN_PG_STATUS__SI 0x3103 -#define mmRLC_GCPM_GENERAL_0__SI 0x311B -#define mmRLC_GCPM_GENERAL_1__SI 0x311C -#define mmRLC_GCPM_GENERAL_2__SI 0x311D -#define mmRLC_GCPM_GENERAL_3__SI 0x311E -#define mmRLC_GCPM_GENERAL_4__SI 0x311F -#define mmRLC_GCPM_GENERAL_5__SI 0x3120 -#define mmRLC_GCPM_GENERAL_6__SI 0x3121 -#define mmRLC_GCPM_GENERAL_7__SI 0x3122 -#define mmRLC_GPM_CU_PD_TIMEOUT__CI 0x312B -#define mmRLC_GPM_DEBUG_SELECT__CI 0x30E0 -#define mmRLC_GPM_DEBUG__CI 0x30E1 -#define mmRLC_GPM_GENERAL_0__CI 0x3123 -#define mmRLC_GPM_GENERAL_1__CI 0x3124 -#define mmRLC_GPM_GENERAL_2__CI 0x3125 -#define mmRLC_GPM_GENERAL_3__CI 0x3126 -#define mmRLC_GPM_GENERAL_4__CI 0x3127 -#define mmRLC_GPM_GENERAL_5__CI 0x3128 -#define mmRLC_GPM_GENERAL_6__CI 0x3129 -#define mmRLC_GPM_GENERAL_7__CI 0x312A -#define mmRLC_GPM_LOG_ADDR__CI 0x3136 -#define mmRLC_GPM_LOG_CONT__CI 0x3138 -#define mmRLC_GPM_LOG_SIZE__CI 0x3137 -#define mmRLC_GPM_PERF_COUNT_0__CI 0x312F -#define mmRLC_GPM_PERF_COUNT_1__CI 0x3130 -#define mmRLC_GPM_SCRATCH_ADDR__CI 0x312C -#define mmRLC_GPM_SCRATCH_DATA__CI 0x312D -#define mmRLC_GPM_STAT__CI 0x3100 -#define mmRLC_GPM_THREAD_ENABLE__CI 0x3105 -#define mmRLC_GPM_THREAD_PRIORITY__CI 0x3104 -#define mmRLC_GPM_UCODE_ADDR__CI 0x30E2 -#define mmRLC_GPM_UCODE_DATA__CI 0x30E3 -#define mmRLC_GPM_VMID_THREAD0__CI 0x3106 -#define mmRLC_GPM_VMID_THREAD1__CI 0x3107 -#define mmRLC_GPR_REG1__CI 0x3139 -#define mmRLC_GPR_REG2__CI 0x313A -#define mmRLC_GPU_CLOCK_32_RES_SEL__CI 0x3101 -#define mmRLC_GPU_CLOCK_32_RES_SEL__SI 0x30D4 -#define mmRLC_GPU_CLOCK_32__CI 0x3102 -#define mmRLC_GPU_CLOCK_32__SI 0x30D5 -#define mmRLC_GPU_CLOCK_COUNT_LSB__CI 0x30E4 -#define mmRLC_GPU_CLOCK_COUNT_LSB__SI 0x30CE -#define mmRLC_GPU_CLOCK_COUNT_MSB__CI 0x30E5 -#define mmRLC_GPU_CLOCK_COUNT_MSB__SI 0x30CF -#define mmRLC_JUMP_TABLE_RESTORE__CI 0x30DE -#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__CI 0x3110 -#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__SI 0x3108 -#define mmRLC_LB_CNTL__CI 0x30D9 -#define mmRLC_LB_CNTL__SI 0x30C3 -#define mmRLC_LB_CNTR_INIT__CI 0x30DB -#define mmRLC_LB_CNTR_INIT__SI 0x30C6 -#define mmRLC_LB_CNTR_MAX__CI 0x30D2 -#define mmRLC_LB_CNTR_MAX__SI 0x30C5 -#define mmRLC_LB_INIT_CU_MASK__CI 0x310F -#define mmRLC_LB_INIT_CU_MASK__SI 0x3107 -#define mmRLC_LB_PARAMS__CI 0x3111 -#define mmRLC_LB_PARAMS__SI 0x3109 -#define mmRLC_LOAD_BALANCE_CNTR__CI 0x30DC -#define mmRLC_LOAD_BALANCE_CNTR__SI 0x30F6 -#define mmRLC_MAX_PG_CU__CI 0x3114 -#define mmRLC_MAX_PG_CU__SI 0x310C -#define mmRLC_MC_CNTL__CI 0x30C3 -#define mmRLC_MC_CNTL__SI 0x30D1 -#define mmRLC_MEM_SLP_CNTL__CI 0x30C6 -#define mmRLC_MEM_SLP_CNTL__SI 0x30D8 -#define mmRLC_PERFCOUNTER0_HI__CI__VI 0xD481 -#define mmRLC_PERFCOUNTER0_HI__SI 0x30DC -#define mmRLC_PERFCOUNTER0_LO__CI__VI 0xD480 -#define mmRLC_PERFCOUNTER0_LO__SI 0x30DB -#define mmRLC_PERFCOUNTER0_SELECT__CI__VI 0xDCC1 -#define mmRLC_PERFCOUNTER0_SELECT__SI 0x30DA -#define mmRLC_PERFCOUNTER1_HI__CI__VI 0xD483 -#define mmRLC_PERFCOUNTER1_HI__SI 0x30DF -#define mmRLC_PERFCOUNTER1_LO__CI__VI 0xD482 -#define mmRLC_PERFCOUNTER1_LO__SI 0x30DE -#define mmRLC_PERFCOUNTER1_SELECT__CI__VI 0xDCC2 -#define mmRLC_PERFCOUNTER1_SELECT__SI 0x30DD -#define mmRLC_PERFMON_CNTL__CI__VI 0xDCC0 -#define mmRLC_PERFMON_CNTL__SI 0x30D9 -#define mmRLC_PG_ALWAYS_ON_CU_MASK__CI 0x3113 -#define mmRLC_PG_ALWAYS_ON_CU_MASK__SI 0x310B -#define mmRLC_PG_CNTL__CI 0x3103 -#define mmRLC_PG_CNTL__SI 0x30D7 -#define mmRLC_PG_DELAY_2__CI 0x30DF -#define mmRLC_PG_DELAY__CI 0x310D -#define mmRLC_RL_BASE__SI 0x30C1 -#define mmRLC_RL_SIZE__SI 0x30C2 -#define mmRLC_SAFE_MODE__CI 0x313A -#define mmRLC_SAVE_AND_RESTORE_BASE__CI 0x30DD -#define mmRLC_SAVE_AND_RESTORE_BASE__SI 0x30C4 -#define mmRLC_SERDES_CU_MASTER_BUSY__CI 0x3121 -#define mmRLC_SERDES_MASTER_BUSY_0__SI 0x3119 -#define mmRLC_SERDES_MASTER_BUSY_1__SI 0x311A -#define mmRLC_SERDES_NONCU_MASTER_BUSY__CI 0x3122 -#define mmRLC_SERDES_RD_DATA_0__CI 0x311A -#define mmRLC_SERDES_RD_DATA_0__SI 0x3112 -#define mmRLC_SERDES_RD_DATA_1__CI 0x311B -#define mmRLC_SERDES_RD_DATA_1__SI 0x3113 -#define mmRLC_SERDES_RD_DATA_2__CI 0x311C -#define mmRLC_SERDES_RD_DATA_2__SI 0x3114 -#define mmRLC_SERDES_RD_MASTER_INDEX__CI 0x3119 -#define mmRLC_SERDES_RD_MASTER_INDEX__SI 0x3111 -#define mmRLC_SERDES_WR_CTRL__CI 0x311F -#define mmRLC_SERDES_WR_CTRL__SI 0x3117 -#define mmRLC_SERDES_WR_CU_MASTER_MASK__CI 0x311D -#define mmRLC_SERDES_WR_DATA__CI 0x3120 -#define mmRLC_SERDES_WR_DATA__SI 0x3118 -#define mmRLC_SERDES_WR_MASTER_MASK_0__SI 0x3115 -#define mmRLC_SERDES_WR_MASTER_MASK_1__SI 0x3116 -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK__CI 0x311E -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL__CI 0x3116 -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL__SI 0x310E -#define mmRLC_SMU_PG_CTRL__CI 0x3117 -#define mmRLC_SMU_PG_CTRL__SI 0x310F -#define mmRLC_SMU_PG_WAKE_UP_CTRL__CI 0x3118 -#define mmRLC_SMU_PG_WAKE_UP_CTRL__SI 0x3110 -#define mmRLC_SOFT_RESET_GPU__CI 0x30C5 -#define mmRLC_SOFT_RESET_GPU__SI 0x30D6 -#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI 0xDC8A -#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI 0xDC88 -#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI 0xDC89 -#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI 0xDC87 -#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI 0xDC8B -#define mmRLC_SPM_DEBUG_SELECT__CI 0x3134 -#define mmRLC_SPM_DEBUG__CI 0x3135 -#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI 0xDC8D -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI 0xDC9B -#define mmRLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI 0xDC9C -#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI 0xDC8E -#define mmRLC_SPM_INT_CNTL__CI 0x3132 -#define mmRLC_SPM_INT_STATUS__CI 0x3133 -#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI 0xDC8C -#define mmRLC_SPM_PERFMON_CNTL__CI__VI 0xDC80 -#define mmRLC_SPM_PERFMON_RING_BASE_HI__CI__VI 0xDC82 -#define mmRLC_SPM_PERFMON_RING_BASE_LO__CI__VI 0xDC81 -#define mmRLC_SPM_PERFMON_RING_SIZE__CI__VI 0xDC83 -#define mmRLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI 0xDC84 -#define mmRLC_SPM_RING_RDPTR__CI__VI 0xDC9D -#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI 0xDC90 -#define mmRLC_SPM_SEGMENT_THRESHOLD__CI__VI 0xDC9E -#define mmRLC_SPM_SE_MUXSEL_ADDR__CI__VI 0xDC85 -#define mmRLC_SPM_SE_MUXSEL_DATA__CI__VI 0xDC86 -#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI 0xDC97 -#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI 0xDC98 -#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI 0xDC9A -#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI 0xDC94 -#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI 0xDC92 -#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI 0xDC91 -#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI 0xDC93 -#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI 0xDC99 -#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI 0xDC95 -#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI 0xDC96 -#define mmRLC_SPM_VMID__CI 0x3131 -#define mmRLC_STATIC_PG_STATUS__CI 0x312E -#define mmRLC_STAT__CI 0x30C4 -#define mmRLC_STAT__SI 0x30D3 -#define mmRLC_THREAD1_DELAY__CI 0x3112 -#define mmRLC_THREAD1_DELAY__SI 0x310A -#define mmRLC_THREAD_ENABLE__SI 0x30E2 -#define mmRLC_THREAD_PRIORITY__SI 0x30E1 -#define mmRLC_TTOP_DELAY__SI 0x3105 -#define mmRLC_UCODE_ADDR__SI 0x30CB -#define mmRLC_UCODE_CNTL__CI 0x30E7 -#define mmRLC_UCODE_CNTL__SI 0x30D2 -#define mmRLC_UCODE_DATA__SI 0x30CC -#define mmRLC_VMID_THREAD1__SI 0x30EB -#define mmRLC_VMID_THREAD2__SI 0x30EC -#define mmRLC_VMID_THREAD3__SI 0x30ED -#define mmRLC_VMID__SI 0x30F7 -#define mmROM_CNTL__SI 0x0580 -#define mmROM_DATA__SI 0x002B -#define mmROM_INDEX__SI 0x002A -#define mmROM_SMC_IND_DATA__CI__VI 0x0081 -#define mmROM_SMC_IND_DATA_alt_1__CI__VI 0x0083 -#define mmROM_SMC_IND_DATA_alt_2__CI__VI 0x0085 -#define mmROM_SMC_IND_DATA_alt_3__CI__VI 0x0087 -#define mmROM_SMC_IND_INDEX__CI__VI 0x0080 -#define mmROM_SMC_IND_INDEX_alt_1__CI__VI 0x0082 -#define mmROM_SMC_IND_INDEX_alt_2__CI__VI 0x0084 -#define mmROM_SMC_IND_INDEX_alt_3__CI__VI 0x0086 -#define mmROM_START__SI 0x0585 -#define mmROM_STATUS__SI 0x0582 -#define mmROM_SW_CNTL__SI 0x0586 -#define mmROM_SW_COMMAND__SI 0x0588 -#define mmROM_SW_DATA_10__SI 0x0592 -#define mmROM_SW_DATA_11__SI 0x0593 -#define mmROM_SW_DATA_12__SI 0x0594 -#define mmROM_SW_DATA_13__SI 0x0595 -#define mmROM_SW_DATA_14__SI 0x0596 -#define mmROM_SW_DATA_15__SI 0x0597 -#define mmROM_SW_DATA_16__SI 0x0598 -#define mmROM_SW_DATA_17__SI 0x0599 -#define mmROM_SW_DATA_18__SI 0x059A -#define mmROM_SW_DATA_19__SI 0x059B -#define mmROM_SW_DATA_1__SI 0x0589 -#define mmROM_SW_DATA_20__SI 0x059C -#define mmROM_SW_DATA_21__SI 0x059D -#define mmROM_SW_DATA_22__SI 0x059E -#define mmROM_SW_DATA_23__SI 0x059F -#define mmROM_SW_DATA_24__SI 0x05A0 -#define mmROM_SW_DATA_25__SI 0x05A1 -#define mmROM_SW_DATA_26__SI 0x05A2 -#define mmROM_SW_DATA_27__SI 0x05A3 -#define mmROM_SW_DATA_28__SI 0x05A4 -#define mmROM_SW_DATA_29__SI 0x05A5 -#define mmROM_SW_DATA_2__SI 0x058A -#define mmROM_SW_DATA_30__SI 0x05A6 -#define mmROM_SW_DATA_31__SI 0x05A7 -#define mmROM_SW_DATA_32__SI 0x05A8 -#define mmROM_SW_DATA_33__SI 0x05A9 -#define mmROM_SW_DATA_34__SI 0x05AA -#define mmROM_SW_DATA_35__SI 0x05AB -#define mmROM_SW_DATA_36__SI 0x05AC -#define mmROM_SW_DATA_37__SI 0x05AD -#define mmROM_SW_DATA_38__SI 0x05AE -#define mmROM_SW_DATA_39__SI 0x05AF -#define mmROM_SW_DATA_3__SI 0x058B -#define mmROM_SW_DATA_40__SI 0x05B0 -#define mmROM_SW_DATA_41__SI 0x05B1 -#define mmROM_SW_DATA_42__SI 0x05B2 -#define mmROM_SW_DATA_43__SI 0x05B3 -#define mmROM_SW_DATA_44__SI 0x05B4 -#define mmROM_SW_DATA_45__SI 0x05B5 -#define mmROM_SW_DATA_46__SI 0x05B6 -#define mmROM_SW_DATA_47__SI 0x05B7 -#define mmROM_SW_DATA_48__SI 0x05B8 -#define mmROM_SW_DATA_49__SI 0x05B9 -#define mmROM_SW_DATA_4__SI 0x058C -#define mmROM_SW_DATA_50__SI 0x05BA -#define mmROM_SW_DATA_51__SI 0x05BB -#define mmROM_SW_DATA_52__SI 0x05BC -#define mmROM_SW_DATA_53__SI 0x05BD -#define mmROM_SW_DATA_54__SI 0x05BE -#define mmROM_SW_DATA_55__SI 0x05BF -#define mmROM_SW_DATA_56__SI 0x05C0 -#define mmROM_SW_DATA_57__SI 0x05C1 -#define mmROM_SW_DATA_58__SI 0x05C2 -#define mmROM_SW_DATA_59__SI 0x05C3 -#define mmROM_SW_DATA_5__SI 0x058D -#define mmROM_SW_DATA_60__SI 0x05C4 -#define mmROM_SW_DATA_61__SI 0x05C5 -#define mmROM_SW_DATA_62__SI 0x05C6 -#define mmROM_SW_DATA_63__SI 0x05C7 -#define mmROM_SW_DATA_64__SI 0x05C8 -#define mmROM_SW_DATA_6__SI 0x058E -#define mmROM_SW_DATA_7__SI 0x058F -#define mmROM_SW_DATA_8__SI 0x0590 -#define mmROM_SW_DATA_9__SI 0x0591 -#define mmROM_SW_STATUS__SI 0x0587 -#define mmS0_S1_VID_DC_SMIO_CNTL__SI 0x01ED -#define mmS0_VID_SMIO_CNTL__SI 0x01EA -#define mmS1_VID_SMIO_CNTL__SI 0x01EB -#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT__SI 0x1B5E -#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM__SI 0x1B5F -#define mmSCL0_SCL_ALU_CONTROL__SI 0x1B54 -#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL__SI 0x1B47 -#define mmSCL0_SCL_BYPASS_CONTROL__SI 0x1B45 -#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS__SI 0x1B55 -#define mmSCL0_SCL_COEF_RAM_SELECT__SI 0x1B40 -#define mmSCL0_SCL_COEF_RAM_TAP_DATA__SI 0x1B41 -#define mmSCL0_SCL_CONTROL__SI 0x1B44 -#define mmSCL0_SCL_CRC_CURRENT__SI 0x1B67 -#define mmSCL0_SCL_CRC_ENABLE__SI 0x1B64 -#define mmSCL0_SCL_CRC_LAST__SI 0x1B68 -#define mmSCL0_SCL_CRC_MASK__SI 0x1B66 -#define mmSCL0_SCL_CRC_SOURCE_SEL__SI 0x1B65 -#define mmSCL0_SCL_DEBUG__SI 0x1B6A -#define mmSCL0_SCL_DTMTEST_CNTL__SI 0x1B58 -#define mmSCL0_SCL_DTMTEST_CRC_BLUE__SI 0x1B59 -#define mmSCL0_SCL_DTMTEST_CRC_GREEN__SI 0x1B5A -#define mmSCL0_SCL_DTMTEST_CRC_RED__SI 0x1B5B -#define mmSCL0_SCL_F_SHARP_CONTROL__SI 0x1B53 -#define mmSCL0_SCL_HIGH_PASS_FILTER_CONTROL__SI 0x1B49 -#define mmSCL0_SCL_HORZ_FILTER_CONTROL__SI 0x1B4A -#define mmSCL0_SCL_HORZ_FILTER_INIT_CHROMA__SI 0x1B4D -#define mmSCL0_SCL_HORZ_FILTER_INIT_RGB_LUMA__SI 0x1B4C -#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SI 0x1B4B -#define mmSCL0_SCL_LOW_PASS_FILTER_CONTROL__SI 0x1B48 -#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL__SI 0x1B46 -#define mmSCL0_SCL_MODE_CHANGE_DET1__SI 0x1B60 -#define mmSCL0_SCL_MODE_CHANGE_DET2__SI 0x1B61 -#define mmSCL0_SCL_MODE_CHANGE_DET3__SI 0x1B62 -#define mmSCL0_SCL_MODE_CHANGE_MASK__SI 0x1B63 -#define mmSCL0_SCL_ONE_SHOT_WATERMARK__SI 0x1B56 -#define mmSCL0_SCL_SCALER_ENABLE__SI 0x1B42 -#define mmSCL0_SCL_TAP_CONTROL__SI 0x1B43 -#define mmSCL0_SCL_TEST_DEBUG_DATA__SI 0x1B6C -#define mmSCL0_SCL_TEST_DEBUG_INDEX__SI 0x1B6B -#define mmSCL0_SCL_UNDERFLOW_STATUS__SI 0x1B52 -#define mmSCL0_SCL_UPDATE__SI 0x1B51 -#define mmSCL0_SCL_VERT_FILTER_CONTROL__SI 0x1B4E -#define mmSCL0_SCL_VERT_FILTER_INIT_BOT__SI 0x1B57 -#define mmSCL0_SCL_VERT_FILTER_INIT__SI 0x1B50 -#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO__SI 0x1B4F -#define mmSCL0_VIEWPORT_SIZE__SI 0x1B5D -#define mmSCL0_VIEWPORT_START__SI 0x1B5C -#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT__SI 0x1E5E -#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM__SI 0x1E5F -#define mmSCL1_SCL_ALU_CONTROL__SI 0x1E54 -#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL__SI 0x1E47 -#define mmSCL1_SCL_BYPASS_CONTROL__SI 0x1E45 -#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS__SI 0x1E55 -#define mmSCL1_SCL_COEF_RAM_SELECT__SI 0x1E40 -#define mmSCL1_SCL_COEF_RAM_TAP_DATA__SI 0x1E41 -#define mmSCL1_SCL_CONTROL__SI 0x1E44 -#define mmSCL1_SCL_CRC_CURRENT__SI 0x1E67 -#define mmSCL1_SCL_CRC_ENABLE__SI 0x1E64 -#define mmSCL1_SCL_CRC_LAST__SI 0x1E68 -#define mmSCL1_SCL_CRC_MASK__SI 0x1E66 -#define mmSCL1_SCL_CRC_SOURCE_SEL__SI 0x1E65 -#define mmSCL1_SCL_DEBUG__SI 0x1E6A -#define mmSCL1_SCL_DTMTEST_CNTL__SI 0x1E58 -#define mmSCL1_SCL_DTMTEST_CRC_BLUE__SI 0x1E59 -#define mmSCL1_SCL_DTMTEST_CRC_GREEN__SI 0x1E5A -#define mmSCL1_SCL_DTMTEST_CRC_RED__SI 0x1E5B -#define mmSCL1_SCL_F_SHARP_CONTROL__SI 0x1E53 -#define mmSCL1_SCL_HIGH_PASS_FILTER_CONTROL__SI 0x1E49 -#define mmSCL1_SCL_HORZ_FILTER_CONTROL__SI 0x1E4A -#define mmSCL1_SCL_HORZ_FILTER_INIT_CHROMA__SI 0x1E4D -#define mmSCL1_SCL_HORZ_FILTER_INIT_RGB_LUMA__SI 0x1E4C -#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SI 0x1E4B -#define mmSCL1_SCL_LOW_PASS_FILTER_CONTROL__SI 0x1E48 -#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL__SI 0x1E46 -#define mmSCL1_SCL_MODE_CHANGE_DET1__SI 0x1E60 -#define mmSCL1_SCL_MODE_CHANGE_DET2__SI 0x1E61 -#define mmSCL1_SCL_MODE_CHANGE_DET3__SI 0x1E62 -#define mmSCL1_SCL_MODE_CHANGE_MASK__SI 0x1E63 -#define mmSCL1_SCL_ONE_SHOT_WATERMARK__SI 0x1E56 -#define mmSCL1_SCL_SCALER_ENABLE__SI 0x1E42 -#define mmSCL1_SCL_TAP_CONTROL__SI 0x1E43 -#define mmSCL1_SCL_TEST_DEBUG_DATA__SI 0x1E6C -#define mmSCL1_SCL_TEST_DEBUG_INDEX__SI 0x1E6B -#define mmSCL1_SCL_UNDERFLOW_STATUS__SI 0x1E52 -#define mmSCL1_SCL_UPDATE__SI 0x1E51 -#define mmSCL1_SCL_VERT_FILTER_CONTROL__SI 0x1E4E -#define mmSCL1_SCL_VERT_FILTER_INIT_BOT__SI 0x1E57 -#define mmSCL1_SCL_VERT_FILTER_INIT__SI 0x1E50 -#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO__SI 0x1E4F -#define mmSCL1_VIEWPORT_SIZE__SI 0x1E5D -#define mmSCL1_VIEWPORT_START__SI 0x1E5C -#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT__SI 0x415E -#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM__SI 0x415F -#define mmSCL2_SCL_ALU_CONTROL__SI 0x4154 -#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL__SI 0x4147 -#define mmSCL2_SCL_BYPASS_CONTROL__SI 0x4145 -#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS__SI 0x4155 -#define mmSCL2_SCL_COEF_RAM_SELECT__SI 0x4140 -#define mmSCL2_SCL_COEF_RAM_TAP_DATA__SI 0x4141 -#define mmSCL2_SCL_CONTROL__SI 0x4144 -#define mmSCL2_SCL_CRC_CURRENT__SI 0x4167 -#define mmSCL2_SCL_CRC_ENABLE__SI 0x4164 -#define mmSCL2_SCL_CRC_LAST__SI 0x4168 -#define mmSCL2_SCL_CRC_MASK__SI 0x4166 -#define mmSCL2_SCL_CRC_SOURCE_SEL__SI 0x4165 -#define mmSCL2_SCL_DEBUG__SI 0x416A -#define mmSCL2_SCL_DTMTEST_CNTL__SI 0x4158 -#define mmSCL2_SCL_DTMTEST_CRC_BLUE__SI 0x4159 -#define mmSCL2_SCL_DTMTEST_CRC_GREEN__SI 0x415A -#define mmSCL2_SCL_DTMTEST_CRC_RED__SI 0x415B -#define mmSCL2_SCL_F_SHARP_CONTROL__SI 0x4153 -#define mmSCL2_SCL_HIGH_PASS_FILTER_CONTROL__SI 0x4149 -#define mmSCL2_SCL_HORZ_FILTER_CONTROL__SI 0x414A -#define mmSCL2_SCL_HORZ_FILTER_INIT_CHROMA__SI 0x414D -#define mmSCL2_SCL_HORZ_FILTER_INIT_RGB_LUMA__SI 0x414C -#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SI 0x414B -#define mmSCL2_SCL_LOW_PASS_FILTER_CONTROL__SI 0x4148 -#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL__SI 0x4146 -#define mmSCL2_SCL_MODE_CHANGE_DET1__SI 0x4160 -#define mmSCL2_SCL_MODE_CHANGE_DET2__SI 0x4161 -#define mmSCL2_SCL_MODE_CHANGE_DET3__SI 0x4162 -#define mmSCL2_SCL_MODE_CHANGE_MASK__SI 0x4163 -#define mmSCL2_SCL_ONE_SHOT_WATERMARK__SI 0x4156 -#define mmSCL2_SCL_SCALER_ENABLE__SI 0x4142 -#define mmSCL2_SCL_TAP_CONTROL__SI 0x4143 -#define mmSCL2_SCL_TEST_DEBUG_DATA__SI 0x416C -#define mmSCL2_SCL_TEST_DEBUG_INDEX__SI 0x416B -#define mmSCL2_SCL_UNDERFLOW_STATUS__SI 0x4152 -#define mmSCL2_SCL_UPDATE__SI 0x4151 -#define mmSCL2_SCL_VERT_FILTER_CONTROL__SI 0x414E -#define mmSCL2_SCL_VERT_FILTER_INIT_BOT__SI 0x4157 -#define mmSCL2_SCL_VERT_FILTER_INIT__SI 0x4150 -#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO__SI 0x414F -#define mmSCL2_VIEWPORT_SIZE__SI 0x415D -#define mmSCL2_VIEWPORT_START__SI 0x415C -#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT__SI 0x445E -#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM__SI 0x445F -#define mmSCL3_SCL_ALU_CONTROL__SI 0x4454 -#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL__SI 0x4447 -#define mmSCL3_SCL_BYPASS_CONTROL__SI 0x4445 -#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS__SI 0x4455 -#define mmSCL3_SCL_COEF_RAM_SELECT__SI 0x4440 -#define mmSCL3_SCL_COEF_RAM_TAP_DATA__SI 0x4441 -#define mmSCL3_SCL_CONTROL__SI 0x4444 -#define mmSCL3_SCL_CRC_CURRENT__SI 0x4467 -#define mmSCL3_SCL_CRC_ENABLE__SI 0x4464 -#define mmSCL3_SCL_CRC_LAST__SI 0x4468 -#define mmSCL3_SCL_CRC_MASK__SI 0x4466 -#define mmSCL3_SCL_CRC_SOURCE_SEL__SI 0x4465 -#define mmSCL3_SCL_DEBUG__SI 0x446A -#define mmSCL3_SCL_DTMTEST_CNTL__SI 0x4458 -#define mmSCL3_SCL_DTMTEST_CRC_BLUE__SI 0x4459 -#define mmSCL3_SCL_DTMTEST_CRC_GREEN__SI 0x445A -#define mmSCL3_SCL_DTMTEST_CRC_RED__SI 0x445B -#define mmSCL3_SCL_F_SHARP_CONTROL__SI 0x4453 -#define mmSCL3_SCL_HIGH_PASS_FILTER_CONTROL__SI 0x4449 -#define mmSCL3_SCL_HORZ_FILTER_CONTROL__SI 0x444A -#define mmSCL3_SCL_HORZ_FILTER_INIT_CHROMA__SI 0x444D -#define mmSCL3_SCL_HORZ_FILTER_INIT_RGB_LUMA__SI 0x444C -#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SI 0x444B -#define mmSCL3_SCL_LOW_PASS_FILTER_CONTROL__SI 0x4448 -#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL__SI 0x4446 -#define mmSCL3_SCL_MODE_CHANGE_DET1__SI 0x4460 -#define mmSCL3_SCL_MODE_CHANGE_DET2__SI 0x4461 -#define mmSCL3_SCL_MODE_CHANGE_DET3__SI 0x4462 -#define mmSCL3_SCL_MODE_CHANGE_MASK__SI 0x4463 -#define mmSCL3_SCL_ONE_SHOT_WATERMARK__SI 0x4456 -#define mmSCL3_SCL_SCALER_ENABLE__SI 0x4442 -#define mmSCL3_SCL_TAP_CONTROL__SI 0x4443 -#define mmSCL3_SCL_TEST_DEBUG_DATA__SI 0x446C -#define mmSCL3_SCL_TEST_DEBUG_INDEX__SI 0x446B -#define mmSCL3_SCL_UNDERFLOW_STATUS__SI 0x4452 -#define mmSCL3_SCL_UPDATE__SI 0x4451 -#define mmSCL3_SCL_VERT_FILTER_CONTROL__SI 0x444E -#define mmSCL3_SCL_VERT_FILTER_INIT_BOT__SI 0x4457 -#define mmSCL3_SCL_VERT_FILTER_INIT__SI 0x4450 -#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO__SI 0x444F -#define mmSCL3_VIEWPORT_SIZE__SI 0x445D -#define mmSCL3_VIEWPORT_START__SI 0x445C -#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT__SI 0x475E -#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM__SI 0x475F -#define mmSCL4_SCL_ALU_CONTROL__SI 0x4754 -#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL__SI 0x4747 -#define mmSCL4_SCL_BYPASS_CONTROL__SI 0x4745 -#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS__SI 0x4755 -#define mmSCL4_SCL_COEF_RAM_SELECT__SI 0x4740 -#define mmSCL4_SCL_COEF_RAM_TAP_DATA__SI 0x4741 -#define mmSCL4_SCL_CONTROL__SI 0x4744 -#define mmSCL4_SCL_CRC_CURRENT__SI 0x4767 -#define mmSCL4_SCL_CRC_ENABLE__SI 0x4764 -#define mmSCL4_SCL_CRC_LAST__SI 0x4768 -#define mmSCL4_SCL_CRC_MASK__SI 0x4766 -#define mmSCL4_SCL_CRC_SOURCE_SEL__SI 0x4765 -#define mmSCL4_SCL_DEBUG__SI 0x476A -#define mmSCL4_SCL_DTMTEST_CNTL__SI 0x4758 -#define mmSCL4_SCL_DTMTEST_CRC_BLUE__SI 0x4759 -#define mmSCL4_SCL_DTMTEST_CRC_GREEN__SI 0x475A -#define mmSCL4_SCL_DTMTEST_CRC_RED__SI 0x475B -#define mmSCL4_SCL_F_SHARP_CONTROL__SI 0x4753 -#define mmSCL4_SCL_HIGH_PASS_FILTER_CONTROL__SI 0x4749 -#define mmSCL4_SCL_HORZ_FILTER_CONTROL__SI 0x474A -#define mmSCL4_SCL_HORZ_FILTER_INIT_CHROMA__SI 0x474D -#define mmSCL4_SCL_HORZ_FILTER_INIT_RGB_LUMA__SI 0x474C -#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO__SI 0x474B -#define mmSCL4_SCL_LOW_PASS_FILTER_CONTROL__SI 0x4748 -#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL__SI 0x4746 -#define mmSCL4_SCL_MODE_CHANGE_DET1__SI 0x4760 -#define mmSCL4_SCL_MODE_CHANGE_DET2__SI 0x4761 -#define mmSCL4_SCL_MODE_CHANGE_DET3__SI 0x4762 -#define mmSCL4_SCL_MODE_CHANGE_MASK__SI 0x4763 -#define mmSCL4_SCL_ONE_SHOT_WATERMARK__SI 0x4756 -#define mmSCL4_SCL_SCALER_ENABLE__SI 0x4742 -#define mmSCL4_SCL_TAP_CONTROL__SI 0x4743 -#define mmSCL4_SCL_TEST_DEBUG_DATA__SI 0x476C -#define mmSCL4_SCL_TEST_DEBUG_INDEX__SI 0x476B -#define mmSCL4_SCL_UNDERFLOW_STATUS__SI 0x4752 -#define mmSCL4_SCL_UPDATE__SI 0x4751 -#define mmSCL4_SCL_VERT_FILTER_CONTROL__SI 0x474E -#define mmSCL4_SCL_VERT_FILTER_INIT_BOT__SI 0x4757 -#define mmSCL4_SCL_VERT_FILTER_INIT__SI 0x4750 -#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO__SI 0x474F -#define mmSCL4_VIEWPORT_SIZE__SI 0x475D -#define mmSCL4_VIEWPORT_START__SI 0x475C -#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT__SI 0x4A5E -#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM__SI 0x4A5F -#define mmSCL5_SCL_ALU_CONTROL__SI 0x4A54 -#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL__SI 0x4A47 -#define mmSCL5_SCL_BYPASS_CONTROL__SI 0x4A45 -#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS__SI 0x4A55 -#define mmSCL5_SCL_COEF_RAM_SELECT__SI 0x4A40 -#define mmSCL5_SCL_COEF_RAM_TAP_DATA__SI 0x4A41 -#define mmSCL5_SCL_CONTROL__SI 0x4A44 -#define mmSCL5_SCL_CRC_CURRENT__SI 0x4A67 -#define mmSCL5_SCL_CRC_ENABLE__SI 0x4A64 -#define mmSCL5_SCL_CRC_LAST__SI 0x4A68 -#define mmSCL5_SCL_CRC_MASK__SI 0x4A66 -#define mmSCL5_SCL_CRC_SOURCE_SEL__SI 0x4A65 -#define mmSCL5_SCL_DEBUG__SI 0x4A6A -#define mmSCL5_SCL_DTMTEST_CNTL__SI 0x4A58 -#define mmSCL5_SCL_DTMTEST_CRC_BLUE__SI 0x4A59 -#define mmSCL5_SCL_DTMTEST_CRC_GREEN__SI 0x4A5A -#define mmSCL5_SCL_DTMTEST_CRC_RED__SI 0x4A5B -#define mmSCL5_SCL_F_SHARP_CONTROL__SI 0x4A53 -#define mmSCL5_SCL_HIGH_PASS_FILTER_CONTROL__SI 0x4A49 -#define mmSCL5_SCL_HORZ_FILTER_CONTROL__SI 0x4A4A -#define mmSCL5_SCL_HORZ_FILTER_INIT_CHROMA__SI 0x4A4D -#define mmSCL5_SCL_HORZ_FILTER_INIT_RGB_LUMA__SI 0x4A4C -#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO__SI 0x4A4B -#define mmSCL5_SCL_LOW_PASS_FILTER_CONTROL__SI 0x4A48 -#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL__SI 0x4A46 -#define mmSCL5_SCL_MODE_CHANGE_DET1__SI 0x4A60 -#define mmSCL5_SCL_MODE_CHANGE_DET2__SI 0x4A61 -#define mmSCL5_SCL_MODE_CHANGE_DET3__SI 0x4A62 -#define mmSCL5_SCL_MODE_CHANGE_MASK__SI 0x4A63 -#define mmSCL5_SCL_ONE_SHOT_WATERMARK__SI 0x4A56 -#define mmSCL5_SCL_SCALER_ENABLE__SI 0x4A42 -#define mmSCL5_SCL_TAP_CONTROL__SI 0x4A43 -#define mmSCL5_SCL_TEST_DEBUG_DATA__SI 0x4A6C -#define mmSCL5_SCL_TEST_DEBUG_INDEX__SI 0x4A6B -#define mmSCL5_SCL_UNDERFLOW_STATUS__SI 0x4A52 -#define mmSCL5_SCL_UPDATE__SI 0x4A51 -#define mmSCL5_SCL_VERT_FILTER_CONTROL__SI 0x4A4E -#define mmSCL5_SCL_VERT_FILTER_INIT_BOT__SI 0x4A57 -#define mmSCL5_SCL_VERT_FILTER_INIT__SI 0x4A50 -#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO__SI 0x4A4F -#define mmSCL5_VIEWPORT_SIZE__SI 0x4A5D -#define mmSCL5_VIEWPORT_START__SI 0x4A5C -#define mmSCLK_CGTT_BLK_CTRL_REG__SI 0x0129 -#define mmSCLK_DCI_SOFT_RESET__SI 0x013E -#define mmSCLK_DCO_SOFT_RESET__SI 0x013F -#define mmSCLK_PWRMGT_CNTL__SI 0x01E2 -#define mmSCL_ALU_CONTROL__SI 0x1B54 -#define mmSCL_AUTOMATIC_MODE_CONTROL__SI 0x1B47 -#define mmSCL_BYPASS_CONTROL__SI 0x1B45 -#define mmSCL_COEF_RAM_CONFLICT_STATUS__SI 0x1B55 -#define mmSCL_COEF_RAM_SELECT__SI 0x1B40 -#define mmSCL_COEF_RAM_TAP_DATA__SI 0x1B41 -#define mmSCL_CONTROL__SI 0x1B44 -#define mmSCL_CRC_CURRENT__SI 0x1B67 -#define mmSCL_CRC_ENABLE__SI 0x1B64 -#define mmSCL_CRC_LAST__SI 0x1B68 -#define mmSCL_CRC_MASK__SI 0x1B66 -#define mmSCL_CRC_SOURCE_SEL__SI 0x1B65 -#define mmSCL_DEBUG__SI 0x1B6A -#define mmSCL_DTMTEST_CNTL__SI 0x1B58 -#define mmSCL_DTMTEST_CRC_BLUE__SI 0x1B59 -#define mmSCL_DTMTEST_CRC_GREEN__SI 0x1B5A -#define mmSCL_DTMTEST_CRC_RED__SI 0x1B5B -#define mmSCL_F_SHARP_CONTROL__SI 0x1B53 -#define mmSCL_HIGH_PASS_FILTER_CONTROL__SI 0x1B49 -#define mmSCL_HORZ_FILTER_CONTROL__SI 0x1B4A -#define mmSCL_HORZ_FILTER_INIT_CHROMA__SI 0x1B4D -#define mmSCL_HORZ_FILTER_INIT_RGB_LUMA__SI 0x1B4C -#define mmSCL_HORZ_FILTER_SCALE_RATIO__SI 0x1B4B -#define mmSCL_LOW_PASS_FILTER_CONTROL__SI 0x1B48 -#define mmSCL_MANUAL_REPLICATE_CONTROL__SI 0x1B46 -#define mmSCL_MODE_CHANGE_DET1__SI 0x1B60 -#define mmSCL_MODE_CHANGE_DET2__SI 0x1B61 -#define mmSCL_MODE_CHANGE_DET3__SI 0x1B62 -#define mmSCL_MODE_CHANGE_MASK__SI 0x1B63 -#define mmSCL_ONE_SHOT_WATERMARK__SI 0x1B56 -#define mmSCL_RBBMIF_RDWR_TIMEOUT__SI 0x031A -#define mmSCL_SCALER_ENABLE__SI 0x1B42 -#define mmSCL_TAP_CONTROL__SI 0x1B43 -#define mmSCL_TEST_DEBUG_DATA__SI 0x1B6C -#define mmSCL_TEST_DEBUG_INDEX__SI 0x1B6B -#define mmSCL_UNDERFLOW_STATUS__SI 0x1B52 -#define mmSCL_UPDATE__SI 0x1B51 -#define mmSCL_VERT_FILTER_CONTROL__SI 0x1B4E -#define mmSCL_VERT_FILTER_INIT_BOT__SI 0x1B57 -#define mmSCL_VERT_FILTER_INIT__SI 0x1B50 -#define mmSCL_VERT_FILTER_SCALE_RATIO__SI 0x1B4F -#define mmSCRATCH_ADDR__CI__VI 0xC051 -#define mmSCRATCH_ADDR__SI 0x2151 -#define mmSCRATCH_REG0__CI__VI 0xC040 -#define mmSCRATCH_REG0__SI 0x2140 -#define mmSCRATCH_REG1__CI__VI 0xC041 -#define mmSCRATCH_REG1__SI 0x2141 -#define mmSCRATCH_REG2__CI__VI 0xC042 -#define mmSCRATCH_REG2__SI 0x2142 -#define mmSCRATCH_REG3__CI__VI 0xC043 -#define mmSCRATCH_REG3__SI 0x2143 -#define mmSCRATCH_REG4__CI__VI 0xC044 -#define mmSCRATCH_REG4__SI 0x2144 -#define mmSCRATCH_REG5__CI__VI 0xC045 -#define mmSCRATCH_REG5__SI 0x2145 -#define mmSCRATCH_REG6__CI__VI 0xC046 -#define mmSCRATCH_REG6__SI 0x2146 -#define mmSCRATCH_REG7__CI__VI 0xC047 -#define mmSCRATCH_REG7__SI 0x2147 -#define mmSCRATCH_UMSK__CI__VI 0xC050 -#define mmSCRATCH_UMSK__SI 0x2150 -#define mmSD1_CC_EDS_LEVEL_CNTL__SI 0x1705 -#define mmSD1_CHROMA_MOD_CNTL__SI 0x17BC -#define mmSD1_CHROMA_OFFSET__SI 0x17E4 -#define mmSD1_COL_SC_DENOMIN__SI 0x17BD -#define mmSD1_COL_SC_INC_CORR__SI 0x17BF -#define mmSD1_COL_SC_INC__SI 0x17BE -#define mmSD1_COL_SC_PHASE_CNTL__SI 0x17F5 -#define mmSD1_CRC_CNTL__SI 0x17C7 -#define mmSD1_CRTC_HV_START__SI 0x17E6 -#define mmSD1_CRTC_TV_FRAMESTART_CNTL__SI 0x17E7 -#define mmSD1_FORCE_DAC_DATA__SI 0x17B3 -#define mmSD1_LUMA_BLANK_SETUP_LEVELS__SI 0x17AA -#define mmSD1_LUMA_COMB_FILT_CNTL1__SI 0x17AE -#define mmSD1_LUMA_COMB_FILT_CNTL2__SI 0x17AF -#define mmSD1_LUMA_COMB_FILT_CNTL3__SI 0x17B0 -#define mmSD1_LUMA_COMB_FILT_CNTL4__SI 0x17B1 -#define mmSD1_LUMA_FILT_CNTL__SI 0x17AD -#define mmSD1_LUMA_OFFSET_LIMIT__SI 0x17E3 -#define mmSD1_LUMA_SYNC_TIP_LEVELS__SI 0x17AC -#define mmSD1_MAIN_CNTL2__SI 0x1780 -#define mmSD1_MAIN_CNTL__SI 0x177F -#define mmSD1_MV_AGC_CNTL__SI 0x17DA -#define mmSD1_MV_AGC_MAX_LEVELS__SI 0x17DB -#define mmSD1_MV_AGC_PAL_A_B_LEVELS__SI 0x17DC -#define mmSD1_MV_BLANK_SETUP_LEVELS__SI 0x17DD -#define mmSD1_MV_BP_LEVEL__SI 0x17DE -#define mmSD1_MV_N0_CONTROL__SI 0x17CB -#define mmSD1_MV_N10_PS_AGC__SI 0x17D0 -#define mmSD1_MV_N11_N12_PS_AGC__SI 0x17D1 -#define mmSD1_MV_N13_N14_PS_AGC_H_EN__SI 0x17D3 -#define mmSD1_MV_N15_BP_TIMING__SI 0x17D4 -#define mmSD1_MV_N16_CS_H_TIMING__SI 0x17D5 -#define mmSD1_MV_N17_TO_N19_CS__SI 0x17D6 -#define mmSD1_MV_N1_TO_N3_CS__SI 0x17CC -#define mmSD1_MV_N20_TO_N22_CS_RGB__SI 0x17D7 -#define mmSD1_MV_N4_TO_N7_CS__SI 0x17CD -#define mmSD1_MV_N8_PS_AGC__SI 0x17CE -#define mmSD1_MV_N9_PS_AGC__SI 0x17CF -#define mmSD1_MV_TIMING_INTERNAL_INIT__SI 0x17D9 -#define mmSD1_MV_V_PS_AGC_TIMING__SI 0x17D2 -#define mmSD1_MV_V_REDUCE_SYNC_ENDS__SI 0x17D8 -#define mmSD1_RGB_OR_PBPR_BLANK_LEVEL__SI 0x17AB -#define mmSD1_SCM_COL_SC_DENOMIN__SI 0x17C0 -#define mmSD1_SCM_COL_SC_INC_CORR__SI 0x17C2 -#define mmSD1_SCM_COL_SC_INC__SI 0x17C1 -#define mmSD1_SCM_DB_DR_SCALE_FACTORS__SI 0x17C4 -#define mmSD1_SCM_MAX_DTO_SWING__SI 0x17C6 -#define mmSD1_SCM_MIN_DTO_SWING__SI 0x17C5 -#define mmSD1_SCM_MOD_CNTL__SI 0x17C3 -#define mmSD1_SDTV0_DEBUG__SI 0x17CA -#define mmSD1_TIMING_H_134BIT__SI 0x171A -#define mmSD1_TIMING_H_20BIT__SI 0x170A -#define mmSD1_TIMING_H_ACTIVE_FILT_WINDOW1__SI 0x17A3 -#define mmSD1_TIMING_H_ACTIVE_FILT_WINDOW2__SI 0x17A4 -#define mmSD1_TIMING_H_ADV_ACTIVE__SI 0x1798 -#define mmSD1_TIMING_H_ADV_VBI_PASSTHRU__SI 0x179E -#define mmSD1_TIMING_H_BURST__SI 0x1791 -#define mmSD1_TIMING_H_CC_EDS__SI 0x1703 -#define mmSD1_TIMING_H_COUNT_INIT__SI 0x1785 -#define mmSD1_TIMING_H_COUNT__SI 0x1783 -#define mmSD1_TIMING_H_EQUALIZATION1__SI 0x1789 -#define mmSD1_TIMING_H_EQUALIZATION2__SI 0x178A -#define mmSD1_TIMING_H_HSYNC__SI 0x1788 -#define mmSD1_TIMING_H_RUNIN_FILT_WINDOW__SI 0x17A5 -#define mmSD1_TIMING_H_SERATION1__SI 0x178B -#define mmSD1_TIMING_H_SERATION2__SI 0x178C -#define mmSD1_TIMING_H_SETUP1__SI 0x1794 -#define mmSD1_TIMING_H_SETUP2__SI 0x1795 -#define mmSD1_TIMING_H_TOTAL__SI 0x1781 -#define mmSD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW__SI 0x17A2 -#define mmSD1_TIMING_H_VBI_PASSTHRU__SI 0x179F -#define mmSD1_TIMING_H_WSS__SI 0x1712 -#define mmSD1_TIMING_INTERNAL_INIT__SI 0x1787 -#define mmSD1_TIMING_V_134BIT__SI 0x1719 -#define mmSD1_TIMING_V_20BIT__SI 0x1709 -#define mmSD1_TIMING_V_ACTIVE1__SI 0x1799 -#define mmSD1_TIMING_V_ACTIVE2__SI 0x179A -#define mmSD1_TIMING_V_BURST1__SI 0x1792 -#define mmSD1_TIMING_V_BURST2__SI 0x1793 -#define mmSD1_TIMING_V_CC_EDS__SI 0x1702 -#define mmSD1_TIMING_V_EQUALIZATION1__SI 0x178D -#define mmSD1_TIMING_V_EQUALIZATION2__SI 0x178E -#define mmSD1_TIMING_V_F_COUNT_INIT__SI 0x1786 -#define mmSD1_TIMING_V_F_COUNT__SI 0x1784 -#define mmSD1_TIMING_V_F_TOTAL__SI 0x1782 -#define mmSD1_TIMING_V_SERATION1__SI 0x178F -#define mmSD1_TIMING_V_SERATION2__SI 0x1790 -#define mmSD1_TIMING_V_SETUP1__SI 0x1796 -#define mmSD1_TIMING_V_SETUP2__SI 0x1797 -#define mmSD1_TIMING_V_VBI_PASSTHRU1__SI 0x17A0 -#define mmSD1_TIMING_V_VBI_PASSTHRU2__SI 0x17A1 -#define mmSD1_TIMING_V_WSS__SI 0x1711 -#define mmSD1_TV_SOURCE_CONTROL__SI 0x17EF -#define mmSD1_UPSAMPLE_MODE__SI 0x17E5 -#define mmSD1_U_AND_V_GAIN_SETTINGS__SI 0x17A9 -#define mmSD1_U_V_BREAK_POINT_SETTINGS__SI 0x17A7 -#define mmSD1_VBI_134BIT_CNTL__SI 0x1718 -#define mmSD1_VBI_134BIT_DTO_CNTL__SI 0x1723 -#define mmSD1_VBI_134BIT_H_DATA__SI 0x171B -#define mmSD1_VBI_134BIT_NULL_PACKET_CNTL__SI 0x1722 -#define mmSD1_VBI_134BIT_P_DATA0__SI 0x171C -#define mmSD1_VBI_134BIT_P_DATA1__SI 0x171D -#define mmSD1_VBI_134BIT_P_DATA2__SI 0x171E -#define mmSD1_VBI_134BIT_P_DATA3__SI 0x171F -#define mmSD1_VBI_20BIT_CNTL__SI 0x1708 -#define mmSD1_VBI_20BIT_DTO_CNTL__SI 0x170B -#define mmSD1_VBI_20BIT_NULL_PACKET_CNTL__SI 0x170E -#define mmSD1_VBI_CC_CNTL__SI 0x1700 -#define mmSD1_VBI_CC_EDS_DTO_CNTL__SI 0x1706 -#define mmSD1_VBI_EDS_CNTL__SI 0x1701 -#define mmSD1_VBI_LEVEL_CNTL__SI 0x1724 -#define mmSD1_VBI_RUNIN_GAIN_CNTL__SI 0x1704 -#define mmSD1_VBI_WSS_CNTL__SI 0x1710 -#define mmSD1_VBI_WSS_DTO_CNTL__SI 0x1713 -#define mmSD1_VIDEO_PORT_SIG__SI 0x17C8 -#define mmSD1_VIDOUT_MUX_CNTL__SI 0x17B2 -#define mmSD1_Y_AND_PASSTHRU_GAIN_SETTINGS__SI 0x17A8 -#define mmSD1_Y_BREAK_POINT_SETTING__SI 0x17A6 -#define mmSDMA0_CHICKEN_BITS__CI__VI 0x3405 -#define mmSDMA0_CLK_CTRL__CI__VI 0x3403 -#define mmSDMA0_CNTL__CI__VI 0x3404 -#define mmSDMA0_CONFIG__CI 0x0F91 -#define mmSDMA0_F32_CNTL__CI__VI 0x3412 -#define mmSDMA0_FREEZE__CI__VI 0x3413 -#define mmSDMA0_GFX_APE1_CNTL__CI__VI 0x34A8 -#define mmSDMA0_GFX_CONTEXT_CNTL__CI__VI 0x3493 -#define mmSDMA0_GFX_CONTEXT_STATUS__CI__VI 0x3491 -#define mmSDMA0_GFX_DRM_COUNTERDATA0__CI__VI 0x349C -#define mmSDMA0_GFX_DRM_COUNTERDATA1__CI__VI 0x349D -#define mmSDMA0_GFX_DRM_COUNTERDATA2__CI__VI 0x349E -#define mmSDMA0_GFX_DRM_COUNTERDATA3__CI__VI 0x349F -#define mmSDMA0_GFX_DRM_COUNTERKEY0__CI__VI 0x3498 -#define mmSDMA0_GFX_DRM_COUNTERKEY1__CI__VI 0x3499 -#define mmSDMA0_GFX_DRM_COUNTERKEY2__CI__VI 0x349A -#define mmSDMA0_GFX_DRM_COUNTERKEY3__CI__VI 0x349B -#define mmSDMA0_GFX_DRM_IVLOAD0__CI__VI 0x34A1 -#define mmSDMA0_GFX_DRM_IVLOAD1__CI__VI 0x34A2 -#define mmSDMA0_GFX_DRM_IVLOAD2__CI__VI 0x34A3 -#define mmSDMA0_GFX_DRM_IVLOAD3__CI__VI 0x34A4 -#define mmSDMA0_GFX_DRM_IVLOAD4__CI__VI 0x34A5 -#define mmSDMA0_GFX_DRM_OFFSET__CI__VI 0x34A0 -#define mmSDMA0_GFX_DRM_UNROLLKEY__CI__VI 0x34A6 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY0__CI__VI 0x3494 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY1__CI__VI 0x3495 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY2__CI__VI 0x3496 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY3__CI__VI 0x3497 -#define mmSDMA0_GFX_IB_BASE_HI__CI__VI 0x348E -#define mmSDMA0_GFX_IB_BASE_LO__CI__VI 0x348D -#define mmSDMA0_GFX_IB_CNTL__CI__VI 0x348A -#define mmSDMA0_GFX_IB_OFFSET__CI__VI 0x348C -#define mmSDMA0_GFX_IB_RPTR__CI__VI 0x348B -#define mmSDMA0_GFX_IB_SIZE__CI__VI 0x348F -#define mmSDMA0_GFX_RB_BASE_HI__CI__VI 0x3482 -#define mmSDMA0_GFX_RB_BASE__CI__VI 0x3481 -#define mmSDMA0_GFX_RB_CNTL__CI__VI 0x3480 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI 0x3488 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI 0x3489 -#define mmSDMA0_GFX_RB_RPTR__CI__VI 0x3483 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI 0x3486 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI 0x3487 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI 0x3485 -#define mmSDMA0_GFX_RB_WPTR__CI__VI 0x3484 -#define mmSDMA0_GFX_SKIP_CNTL__CI__VI 0x3490 -#define mmSDMA0_GFX_VIRTUAL_ADDR__CI__VI 0x34A7 -#define mmSDMA0_HASH__CI__VI 0x3407 -#define mmSDMA0_IB_OFFSET_FETCH__CI__VI 0x340B -#define mmSDMA0_PERFCOUNTER0_RESULT__CI 0x3410 -#define mmSDMA0_PERFCOUNTER1_RESULT__CI 0x3411 -#define mmSDMA0_PERFMON_CNTL__CI 0x340F -#define mmSDMA0_PHASE0_QUANTUM__CI__VI 0x3414 -#define mmSDMA0_PHASE1_QUANTUM__CI__VI 0x3415 -#define mmSDMA0_POWER_CNTL__CI__VI 0x3402 -#define mmSDMA0_PROGRAM__CI__VI 0x340C -#define mmSDMA0_RB_RPTR_FETCH__CI__VI 0x340A -#define mmSDMA0_RLC0_APE1_CNTL__CI__VI 0x3528 -#define mmSDMA0_RLC0_CONTEXT_STATUS__CI__VI 0x3511 -#define mmSDMA0_RLC0_DOORBELL_LOG__CI__VI 0x3529 -#define mmSDMA0_RLC0_DOORBELL__CI__VI 0x3512 -#define mmSDMA0_RLC0_IB_BASE_HI__CI__VI 0x350E -#define mmSDMA0_RLC0_IB_BASE_LO__CI__VI 0x350D -#define mmSDMA0_RLC0_IB_CNTL__CI__VI 0x350A -#define mmSDMA0_RLC0_IB_OFFSET__CI__VI 0x350C -#define mmSDMA0_RLC0_IB_RPTR__CI__VI 0x350B -#define mmSDMA0_RLC0_IB_SIZE__CI__VI 0x350F -#define mmSDMA0_RLC0_RB_BASE_HI__CI__VI 0x3502 -#define mmSDMA0_RLC0_RB_BASE__CI__VI 0x3501 -#define mmSDMA0_RLC0_RB_CNTL__CI__VI 0x3500 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI 0x3508 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI 0x3509 -#define mmSDMA0_RLC0_RB_RPTR__CI__VI 0x3503 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI 0x3506 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI 0x3507 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI 0x3505 -#define mmSDMA0_RLC0_RB_WPTR__CI__VI 0x3504 -#define mmSDMA0_RLC0_SKIP_CNTL__CI__VI 0x3510 -#define mmSDMA0_RLC0_VIRTUAL_ADDR__CI__VI 0x3527 -#define mmSDMA0_RLC1_APE1_CNTL__CI__VI 0x35A8 -#define mmSDMA0_RLC1_CONTEXT_STATUS__CI__VI 0x3591 -#define mmSDMA0_RLC1_DOORBELL_LOG__CI__VI 0x35A9 -#define mmSDMA0_RLC1_DOORBELL__CI__VI 0x3592 -#define mmSDMA0_RLC1_IB_BASE_HI__CI__VI 0x358E -#define mmSDMA0_RLC1_IB_BASE_LO__CI__VI 0x358D -#define mmSDMA0_RLC1_IB_CNTL__CI__VI 0x358A -#define mmSDMA0_RLC1_IB_OFFSET__CI__VI 0x358C -#define mmSDMA0_RLC1_IB_RPTR__CI__VI 0x358B -#define mmSDMA0_RLC1_IB_SIZE__CI__VI 0x358F -#define mmSDMA0_RLC1_RB_BASE_HI__CI__VI 0x3582 -#define mmSDMA0_RLC1_RB_BASE__CI__VI 0x3581 -#define mmSDMA0_RLC1_RB_CNTL__CI__VI 0x3580 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI 0x3588 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI 0x3589 -#define mmSDMA0_RLC1_RB_RPTR__CI__VI 0x3583 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI 0x3586 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI 0x3587 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI 0x3585 -#define mmSDMA0_RLC1_RB_WPTR__CI__VI 0x3584 -#define mmSDMA0_RLC1_SKIP_CNTL__CI__VI 0x3590 -#define mmSDMA0_RLC1_VIRTUAL_ADDR__CI__VI 0x35A7 -#define mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI 0x3408 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI 0x3409 -#define mmSDMA0_STATUS1_REG__CI__VI 0x340E -#define mmSDMA0_STATUS_REG__CI__VI 0x340D -#define mmSDMA0_TILING_CONFIG__CI__VI 0x3406 -#define mmSDMA0_UCODE_ADDR__CI__VI 0x3400 -#define mmSDMA0_UCODE_DATA__CI__VI 0x3401 -#define mmSDMA1_CHICKEN_BITS__CI__VI 0x3605 -#define mmSDMA1_CLK_CTRL__CI__VI 0x3603 -#define mmSDMA1_CNTL__CI__VI 0x3604 -#define mmSDMA1_CONFIG__CI 0x0F92 -#define mmSDMA1_F32_CNTL__CI__VI 0x3612 -#define mmSDMA1_FREEZE__CI__VI 0x3613 -#define mmSDMA1_GFX_APE1_CNTL__CI__VI 0x36A8 -#define mmSDMA1_GFX_CONTEXT_CNTL__CI__VI 0x3693 -#define mmSDMA1_GFX_CONTEXT_STATUS__CI__VI 0x3691 -#define mmSDMA1_GFX_IB_BASE_HI__CI__VI 0x368E -#define mmSDMA1_GFX_IB_BASE_LO__CI__VI 0x368D -#define mmSDMA1_GFX_IB_CNTL__CI__VI 0x368A -#define mmSDMA1_GFX_IB_OFFSET__CI__VI 0x368C -#define mmSDMA1_GFX_IB_RPTR__CI__VI 0x368B -#define mmSDMA1_GFX_IB_SIZE__CI__VI 0x368F -#define mmSDMA1_GFX_RB_BASE_HI__CI__VI 0x3682 -#define mmSDMA1_GFX_RB_BASE__CI__VI 0x3681 -#define mmSDMA1_GFX_RB_CNTL__CI__VI 0x3680 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI 0x3688 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI 0x3689 -#define mmSDMA1_GFX_RB_RPTR__CI__VI 0x3683 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI 0x3686 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI 0x3687 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI 0x3685 -#define mmSDMA1_GFX_RB_WPTR__CI__VI 0x3684 -#define mmSDMA1_GFX_SKIP_CNTL__CI__VI 0x3690 -#define mmSDMA1_GFX_VIRTUAL_ADDR__CI__VI 0x36A7 -#define mmSDMA1_HASH__CI__VI 0x3607 -#define mmSDMA1_IB_OFFSET_FETCH__CI__VI 0x360B -#define mmSDMA1_PERFCOUNTER0_RESULT__CI 0x3610 -#define mmSDMA1_PERFCOUNTER1_RESULT__CI 0x3611 -#define mmSDMA1_PERFMON_CNTL__CI 0x360F -#define mmSDMA1_PHASE0_QUANTUM__CI__VI 0x3614 -#define mmSDMA1_PHASE1_QUANTUM__CI__VI 0x3615 -#define mmSDMA1_POWER_CNTL__CI__VI 0x3602 -#define mmSDMA1_PROGRAM__CI__VI 0x360C -#define mmSDMA1_RB_RPTR_FETCH__CI__VI 0x360A -#define mmSDMA1_RLC0_APE1_CNTL__CI__VI 0x3728 -#define mmSDMA1_RLC0_CONTEXT_STATUS__CI__VI 0x3711 -#define mmSDMA1_RLC0_DOORBELL_LOG__CI__VI 0x3729 -#define mmSDMA1_RLC0_DOORBELL__CI__VI 0x3712 -#define mmSDMA1_RLC0_IB_BASE_HI__CI__VI 0x370E -#define mmSDMA1_RLC0_IB_BASE_LO__CI__VI 0x370D -#define mmSDMA1_RLC0_IB_CNTL__CI__VI 0x370A -#define mmSDMA1_RLC0_IB_OFFSET__CI__VI 0x370C -#define mmSDMA1_RLC0_IB_RPTR__CI__VI 0x370B -#define mmSDMA1_RLC0_IB_SIZE__CI__VI 0x370F -#define mmSDMA1_RLC0_RB_BASE_HI__CI__VI 0x3702 -#define mmSDMA1_RLC0_RB_BASE__CI__VI 0x3701 -#define mmSDMA1_RLC0_RB_CNTL__CI__VI 0x3700 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI 0x3708 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI 0x3709 -#define mmSDMA1_RLC0_RB_RPTR__CI__VI 0x3703 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI 0x3706 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI 0x3707 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI 0x3705 -#define mmSDMA1_RLC0_RB_WPTR__CI__VI 0x3704 -#define mmSDMA1_RLC0_SKIP_CNTL__CI__VI 0x3710 -#define mmSDMA1_RLC0_VIRTUAL_ADDR__CI__VI 0x3727 -#define mmSDMA1_RLC1_APE1_CNTL__CI__VI 0x37A8 -#define mmSDMA1_RLC1_CONTEXT_STATUS__CI__VI 0x3791 -#define mmSDMA1_RLC1_DOORBELL_LOG__CI__VI 0x37A9 -#define mmSDMA1_RLC1_DOORBELL__CI__VI 0x3792 -#define mmSDMA1_RLC1_IB_BASE_HI__CI__VI 0x378E -#define mmSDMA1_RLC1_IB_BASE_LO__CI__VI 0x378D -#define mmSDMA1_RLC1_IB_CNTL__CI__VI 0x378A -#define mmSDMA1_RLC1_IB_OFFSET__CI__VI 0x378C -#define mmSDMA1_RLC1_IB_RPTR__CI__VI 0x378B -#define mmSDMA1_RLC1_IB_SIZE__CI__VI 0x378F -#define mmSDMA1_RLC1_RB_BASE_HI__CI__VI 0x3782 -#define mmSDMA1_RLC1_RB_BASE__CI__VI 0x3781 -#define mmSDMA1_RLC1_RB_CNTL__CI__VI 0x3780 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI 0x3788 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI 0x3789 -#define mmSDMA1_RLC1_RB_RPTR__CI__VI 0x3783 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI 0x3786 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI 0x3787 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI 0x3785 -#define mmSDMA1_RLC1_RB_WPTR__CI__VI 0x3784 -#define mmSDMA1_RLC1_SKIP_CNTL__CI__VI 0x3790 -#define mmSDMA1_RLC1_VIRTUAL_ADDR__CI__VI 0x37A7 -#define mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI 0x3608 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI 0x3609 -#define mmSDMA1_STATUS1_REG__CI__VI 0x360E -#define mmSDMA1_STATUS_REG__CI__VI 0x360D -#define mmSDMA1_TILING_CONFIG__CI__VI 0x3606 -#define mmSDMA1_UCODE_ADDR__CI__VI 0x3600 -#define mmSDMA1_UCODE_DATA__CI__VI 0x3601 -#define mmSDMA_CONFIG__CI 0x0F91 -#define mmSDMA_PGFSM_CONFIG__CI__VI 0x3417 -#define mmSDMA_PGFSM_READ__CI__VI 0x3419 -#define mmSDMA_PGFSM_WRITE__CI__VI 0x3418 -#define mmSDMA_POWER_GATING__CI__VI 0x3416 -#define mmSDVO_CNTL__SI 0x1C88 -#define mmSEM_CHICKEN_BITS__CI__VI 0x0F9E -#define mmSEM_EDC_CONFIG__CI__VI 0x0F9A -#define mmSEM_MAILBOX_CLIENTCONFIG__CI__VI 0x0F9B -#define mmSEM_MAILBOX_CLIENTCONFIG__SI 0x0F9A -#define mmSEM_MAILBOX_CONTROL__CI__VI 0x0F9D -#define mmSEM_MAILBOX_CONTROL__SI 0x0F9C -#define mmSEM_MAILBOX__CI__VI 0x0F9C -#define mmSEM_MAILBOX__SI 0x0F9B -#define mmSEM_MCIF_CONFIG 0x0F90 -#define mmSEM_STATUS__CI__VI 0x0F99 -#define mmSEQ8_DATA__SI 0x00F1 -#define mmSEQ8_IDX__SI 0x00F1 -#define mmSH_HIDDEN_PRIVATE_BASE_VMID__CI__VI 0x2580 -#define mmSH_MEM_APE1_BASE__CI__VI 0x230B -#define mmSH_MEM_APE1_LIMIT__CI__VI 0x230C -#define mmSH_MEM_BASES__CI__VI 0x230A -#define mmSH_MEM_CONFIG__CI__VI 0x230D -#define mmSH_STATIC_MEM_CONFIG__CI__VI 0x2581 -#define mmSLAVE_COMM_CMD_REG__SI 0x1624 -#define mmSLAVE_COMM_CNTL_REG__SI 0x1625 -#define mmSLAVE_COMM_DATA_REG1__SI 0x1621 -#define mmSLAVE_COMM_DATA_REG2__SI 0x1622 -#define mmSLAVE_COMM_DATA_REG3__SI 0x1623 -#define mmSLAVE_HANG_ERROR 0x153B -#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 -#define mmSLAVE_REQ_CREDIT_CNTL 0x1517 -#define mmSMBCLK_PAD_CNTL__CI 0x1523 -#define mmSMBDAT_PAD_CNTL__CI 0x1522 -#define mmSMBUS_SLV_CNTL__CI 0x14FD -#define mmSMC_ACP_RESP__CI__VI 0x00B4 -#define mmSMC_DBG_CNTL__CI__VI 0x00B3 -#define mmSMC_EVENT_CLEAR__SI 0x0213 -#define mmSMC_EVENT_PENDING__SI 0x0214 -#define mmSMC_EVENT_POLARITY__SI 0x0211 -#define mmSMC_EVENT_SENSE__SI 0x0212 -#define mmSMC_IND_ACCESS_CNTL__CI__VI 0x0090 -#define mmSMC_IND_ACCESS_CNTL__SI 0x008A -#define mmSMC_IND_DATA 0x0081 -#define mmSMC_IND_DATA_0__CI__VI 0x0081 -#define mmSMC_IND_DATA_1__CI__VI 0x0083 -#define mmSMC_IND_DATA_2__CI__VI 0x0085 -#define mmSMC_IND_DATA_3__CI__VI 0x0087 -#define mmSMC_IND_DATA_4__CI__VI 0x0089 -#define mmSMC_IND_DATA_5__CI__VI 0x008B -#define mmSMC_IND_DATA_6__CI__VI 0x008D -#define mmSMC_IND_DATA_7__CI__VI 0x008F -#define mmSMC_IND_DATA_alt_1 0x0083 -#define mmSMC_IND_DATA_alt_2 0x0085 -#define mmSMC_IND_DATA_alt_3 0x0087 -#define mmSMC_IND_INDEX 0x0080 -#define mmSMC_IND_INDEX_0__CI__VI 0x0080 -#define mmSMC_IND_INDEX_1__CI__VI 0x0082 -#define mmSMC_IND_INDEX_2__CI__VI 0x0084 -#define mmSMC_IND_INDEX_3__CI__VI 0x0086 -#define mmSMC_IND_INDEX_4__CI__VI 0x0088 -#define mmSMC_IND_INDEX_5__CI__VI 0x008A -#define mmSMC_IND_INDEX_6__CI__VI 0x008C -#define mmSMC_IND_INDEX_7__CI__VI 0x008E -#define mmSMC_IND_INDEX_alt_1 0x0082 -#define mmSMC_IND_INDEX_alt_2 0x0084 -#define mmSMC_IND_INDEX_alt_3 0x0086 -#define mmSMC_INT_GPIO_CLEAR__SI 0x020F -#define mmSMC_INT_GPIO_PENDING__SI 0x0210 -#define mmSMC_INT_GPIO_POLARITY__SI 0x020D -#define mmSMC_INT_GPIO_SENSE__SI 0x020E -#define mmSMC_INT_REQ__SI 0x0088 -#define mmSMC_INT_STATUS__SI 0x0089 -#define mmSMC_MESSAGE_0__CI__VI 0x0094 -#define mmSMC_MESSAGE_0__SI 0x008B -#define mmSMC_MESSAGE_10__CI__VI 0x00B9 -#define mmSMC_MESSAGE_11__CI__VI 0x00BB -#define mmSMC_MESSAGE_1__CI__VI 0x0096 -#define mmSMC_MESSAGE_1__SI 0x008D -#define mmSMC_MESSAGE_2__CI__VI 0x0098 -#define mmSMC_MESSAGE_3__CI__VI 0x009A -#define mmSMC_MESSAGE_4__CI__VI 0x009C -#define mmSMC_MESSAGE_5__CI__VI 0x009E -#define mmSMC_MESSAGE_6__CI__VI 0x00A0 -#define mmSMC_MESSAGE_7__CI__VI 0x00A2 -#define mmSMC_MESSAGE_8__CI__VI 0x00B5 -#define mmSMC_MESSAGE_9__CI__VI 0x00B7 -#define mmSMC_MSG_ARG_0__CI__VI 0x00A4 -#define mmSMC_MSG_ARG_10__CI__VI 0x00BF -#define mmSMC_MSG_ARG_11__CI 0x0091 -#define mmSMC_MSG_ARG_1__CI__VI 0x00A5 -#define mmSMC_MSG_ARG_2__CI__VI 0x00A6 -#define mmSMC_MSG_ARG_3__CI__VI 0x00A7 -#define mmSMC_MSG_ARG_4__CI__VI 0x00A8 -#define mmSMC_MSG_ARG_5__CI__VI 0x00A9 -#define mmSMC_MSG_ARG_6__CI__VI 0x00AA -#define mmSMC_MSG_ARG_7__CI__VI 0x00AB -#define mmSMC_MSG_ARG_8__CI__VI 0x00BD -#define mmSMC_MSG_ARG_9__CI__VI 0x00BE -#define mmSMC_MUTEX_0__CI__VI 0x00AC -#define mmSMC_MUTEX_1__CI__VI 0x00AD -#define mmSMC_MUTEX_2__CI__VI 0x00AE -#define mmSMC_MUTEX_3__CI__VI 0x00AF -#define mmSMC_RESP_0__CI__VI 0x0095 -#define mmSMC_RESP_0__SI 0x008C -#define mmSMC_RESP_10__CI__VI 0x00BA -#define mmSMC_RESP_11__CI__VI 0x00BC -#define mmSMC_RESP_1__CI__VI 0x0097 -#define mmSMC_RESP_1__SI 0x008E -#define mmSMC_RESP_2__CI__VI 0x0099 -#define mmSMC_RESP_3__CI__VI 0x009B -#define mmSMC_RESP_4__CI__VI 0x009D -#define mmSMC_RESP_5__CI__VI 0x009F -#define mmSMC_RESP_6__CI__VI 0x00A1 -#define mmSMC_RESP_7__CI__VI 0x00A3 -#define mmSMC_RESP_8__CI__VI 0x00B6 -#define mmSMC_RESP_9__CI__VI 0x00B8 -#define mmSMC_SCRATCH0__SI 0x0221 -#define mmSMC_SCRATCH10__SI 0x022B -#define mmSMC_SCRATCH11__SI 0x022C -#define mmSMC_SCRATCH12__SI 0x022D -#define mmSMC_SCRATCH1__SI 0x0222 -#define mmSMC_SCRATCH2__SI 0x0223 -#define mmSMC_SCRATCH3__SI 0x0224 -#define mmSMC_SCRATCH4__SI 0x0225 -#define mmSMC_SCRATCH5__SI 0x0226 -#define mmSMC_SCRATCH6__SI 0x0227 -#define mmSMC_SCRATCH7__SI 0x0228 -#define mmSMC_SCRATCH8__SI 0x0229 -#define mmSMC_SCRATCH9__SI 0x022A -#define mmSMC_SP__CI__VI 0x00B2 -#define mmSMC_SW_INT_CTXID__CI__VI 0x00B1 -#define mmSMC_SW_INT__CI__VI 0x00B0 -#define mmSMIO_ENABLE__SI 0x01E7 -#define mmSMU_SMC_IND_DATA__CI__VI 0x0081 -#define mmSMU_SMC_IND_DATA_alt_1__CI__VI 0x0083 -#define mmSMU_SMC_IND_DATA_alt_2__CI__VI 0x0085 -#define mmSMU_SMC_IND_DATA_alt_3__CI__VI 0x0087 -#define mmSMU_SMC_IND_INDEX__CI__VI 0x0080 -#define mmSMU_SMC_IND_INDEX_alt_1__CI__VI 0x0082 -#define mmSMU_SMC_IND_INDEX_alt_2__CI__VI 0x0084 -#define mmSMU_SMC_IND_INDEX_alt_3__CI__VI 0x0086 -#define mmSNAPSHOT_V_COUNTER__SI 0x1AED -#define mmSPI_ARB_CYCLES_0__CI__VI 0x31C1 -#define mmSPI_ARB_CYCLES_0__SI 0x243D -#define mmSPI_ARB_CYCLES_1__CI__VI 0x31C2 -#define mmSPI_ARB_CYCLES_1__SI 0x243E -#define mmSPI_ARB_PRIORITY__CI__VI 0x31C0 -#define mmSPI_ARB_PRIORITY__SI 0x243C -#define mmSPI_BARYC_CNTL 0xA1B8 -#define mmSPI_CDBG_SYS_CS0__CI__VI 0x31C5 -#define mmSPI_CDBG_SYS_CS1__CI__VI 0x31C6 -#define mmSPI_CDBG_SYS_GFX__CI__VI 0x31C3 -#define mmSPI_CDBG_SYS_HP3D__CI__VI 0x31C4 -#define mmSPI_COMPUTE_QUEUE_RESET__CI__VI 0x31DB -#define mmSPI_CONFIG_CNTL 0x2440 -#define mmSPI_CONFIG_CNTL_1 0x244F -#define mmSPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI 0x24DC -#define mmSPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI 0x24DD -#define mmSPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI 0x24DE -#define mmSPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI 0x24DF -#define mmSPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI 0x24E0 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI 0x24E1 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI 0x24E2 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI 0x24E3 -#define mmSPI_CSQ_WF_ACTIVE_STATUS__CI__VI 0x24DB -#define mmSPI_DEBUG_BUSY 0x2450 -#define mmSPI_DEBUG_CNTL 0x2441 -#define mmSPI_DEBUG_READ 0x2442 -#define mmSPI_DYN_GPR_LOCK_EN__SI 0x2437 -#define mmSPI_GDBG_TBA_HI__CI__VI 0x31D5 -#define mmSPI_GDBG_TBA_LO__CI__VI 0x31D4 -#define mmSPI_GDBG_TMA_HI__CI__VI 0x31D7 -#define mmSPI_GDBG_TMA_LO__CI__VI 0x31D6 -#define mmSPI_GDBG_TRAP_CONFIG__CI__VI 0x31D2 -#define mmSPI_GDBG_TRAP_DATA0__CI__VI 0x31D8 -#define mmSPI_GDBG_TRAP_DATA1__CI__VI 0x31D9 -#define mmSPI_GDBG_TRAP_MASK__CI__VI 0x31D3 -#define mmSPI_GDBG_WAVE_CNTL__CI__VI 0x31D1 -#define mmSPI_GDS_CREDITS 0x24D8 -#define mmSPI_INTERP_CONTROL_0 0xA1B5 -#define mmSPI_LB_CTR_CTRL 0x24D4 -#define mmSPI_LB_CU_MASK 0x24D5 -#define mmSPI_LB_DATA_REG 0x24D6 -#define mmSPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI 0x24F0 -#define mmSPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI 0x24ED -#define mmSPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI 0x24EC -#define mmSPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI 0x24EF -#define mmSPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI 0x24EE -#define mmSPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI 0x24F5 -#define mmSPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI 0x24F2 -#define mmSPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI 0x24F1 -#define mmSPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI 0x24F4 -#define mmSPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI 0x24F3 -#define mmSPI_PERFCOUNTER0_HI__CI__VI 0xD180 -#define mmSPI_PERFCOUNTER0_HI__SI 0x2447 -#define mmSPI_PERFCOUNTER0_LO__CI__VI 0xD181 -#define mmSPI_PERFCOUNTER0_LO__SI 0x2448 -#define mmSPI_PERFCOUNTER0_SELECT1__CI__VI 0xD984 -#define mmSPI_PERFCOUNTER0_SELECT__CI__VI 0xD980 -#define mmSPI_PERFCOUNTER0_SELECT__SI 0x2443 -#define mmSPI_PERFCOUNTER1_HI__CI__VI 0xD182 -#define mmSPI_PERFCOUNTER1_HI__SI 0x2449 -#define mmSPI_PERFCOUNTER1_LO__CI__VI 0xD183 -#define mmSPI_PERFCOUNTER1_LO__SI 0x244A -#define mmSPI_PERFCOUNTER1_SELECT1__CI__VI 0xD985 -#define mmSPI_PERFCOUNTER1_SELECT__CI__VI 0xD981 -#define mmSPI_PERFCOUNTER1_SELECT__SI 0x2444 -#define mmSPI_PERFCOUNTER2_HI__CI__VI 0xD184 -#define mmSPI_PERFCOUNTER2_HI__SI 0x244B -#define mmSPI_PERFCOUNTER2_LO__CI__VI 0xD185 -#define mmSPI_PERFCOUNTER2_LO__SI 0x244C -#define mmSPI_PERFCOUNTER2_SELECT1__CI__VI 0xD986 -#define mmSPI_PERFCOUNTER2_SELECT__CI__VI 0xD982 -#define mmSPI_PERFCOUNTER2_SELECT__SI 0x2445 -#define mmSPI_PERFCOUNTER3_HI__CI__VI 0xD186 -#define mmSPI_PERFCOUNTER3_HI__SI 0x244D -#define mmSPI_PERFCOUNTER3_LO__CI__VI 0xD187 -#define mmSPI_PERFCOUNTER3_LO__SI 0x244E -#define mmSPI_PERFCOUNTER3_SELECT1__CI__VI 0xD987 -#define mmSPI_PERFCOUNTER3_SELECT__CI__VI 0xD983 -#define mmSPI_PERFCOUNTER3_SELECT__SI 0x2446 -#define mmSPI_PERFCOUNTER4_HI__CI__VI 0xD188 -#define mmSPI_PERFCOUNTER4_LO__CI__VI 0xD189 -#define mmSPI_PERFCOUNTER4_SELECT__CI__VI 0xD988 -#define mmSPI_PERFCOUNTER5_HI__CI__VI 0xD18A -#define mmSPI_PERFCOUNTER5_LO__CI__VI 0xD18B -#define mmSPI_PERFCOUNTER5_SELECT__CI__VI 0xD989 -#define mmSPI_PERFCOUNTER_BINS__CI__VI 0xD98A -#define mmSPI_PERFCOUNTER_BINS__SI 0x243F -#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24D7 -#define mmSPI_PS_INPUT_ADDR 0xA1B4 -#define mmSPI_PS_INPUT_CNTL_0 0xA191 -#define mmSPI_PS_INPUT_CNTL_1 0xA192 -#define mmSPI_PS_INPUT_CNTL_10 0xA19B -#define mmSPI_PS_INPUT_CNTL_11 0xA19C -#define mmSPI_PS_INPUT_CNTL_12 0xA19D -#define mmSPI_PS_INPUT_CNTL_13 0xA19E -#define mmSPI_PS_INPUT_CNTL_14 0xA19F -#define mmSPI_PS_INPUT_CNTL_15 0xA1A0 -#define mmSPI_PS_INPUT_CNTL_16 0xA1A1 -#define mmSPI_PS_INPUT_CNTL_17 0xA1A2 -#define mmSPI_PS_INPUT_CNTL_18 0xA1A3 -#define mmSPI_PS_INPUT_CNTL_19 0xA1A4 -#define mmSPI_PS_INPUT_CNTL_2 0xA193 -#define mmSPI_PS_INPUT_CNTL_20 0xA1A5 -#define mmSPI_PS_INPUT_CNTL_21 0xA1A6 -#define mmSPI_PS_INPUT_CNTL_22 0xA1A7 -#define mmSPI_PS_INPUT_CNTL_23 0xA1A8 -#define mmSPI_PS_INPUT_CNTL_24 0xA1A9 -#define mmSPI_PS_INPUT_CNTL_25 0xA1AA -#define mmSPI_PS_INPUT_CNTL_26 0xA1AB -#define mmSPI_PS_INPUT_CNTL_27 0xA1AC -#define mmSPI_PS_INPUT_CNTL_28 0xA1AD -#define mmSPI_PS_INPUT_CNTL_29 0xA1AE -#define mmSPI_PS_INPUT_CNTL_3 0xA194 -#define mmSPI_PS_INPUT_CNTL_30 0xA1AF -#define mmSPI_PS_INPUT_CNTL_31 0xA1B0 -#define mmSPI_PS_INPUT_CNTL_4 0xA195 -#define mmSPI_PS_INPUT_CNTL_5 0xA196 -#define mmSPI_PS_INPUT_CNTL_6 0xA197 -#define mmSPI_PS_INPUT_CNTL_7 0xA198 -#define mmSPI_PS_INPUT_CNTL_8 0xA199 -#define mmSPI_PS_INPUT_CNTL_9 0xA19A -#define mmSPI_PS_INPUT_ENA 0xA1B3 -#define mmSPI_PS_IN_CONTROL 0xA1B6 -#define mmSPI_PS_MAX_WAVE_ID__CI__VI 0x243A -#define mmSPI_PS_MAX_WAVE_ID__SI 0x243B -#define mmSPI_RESET_DEBUG__CI__VI 0x31DA -#define mmSPI_RESOURCE_RESERVE_CU_0__CI__VI 0x31DC -#define mmSPI_RESOURCE_RESERVE_CU_10__CI__VI 0x31F0 -#define mmSPI_RESOURCE_RESERVE_CU_11__CI__VI 0x31F1 -#define mmSPI_RESOURCE_RESERVE_CU_1__CI__VI 0x31DD -#define mmSPI_RESOURCE_RESERVE_CU_2__CI__VI 0x31DE -#define mmSPI_RESOURCE_RESERVE_CU_3__CI__VI 0x31DF -#define mmSPI_RESOURCE_RESERVE_CU_4__CI__VI 0x31E0 -#define mmSPI_RESOURCE_RESERVE_CU_5__CI__VI 0x31E1 -#define mmSPI_RESOURCE_RESERVE_CU_6__CI__VI 0x31E2 -#define mmSPI_RESOURCE_RESERVE_CU_7__CI__VI 0x31E3 -#define mmSPI_RESOURCE_RESERVE_CU_8__CI__VI 0x31E4 -#define mmSPI_RESOURCE_RESERVE_CU_9__CI__VI 0x31E5 -#define mmSPI_RESOURCE_RESERVE_CU_AB_0__SI 0x24DB -#define mmSPI_RESOURCE_RESERVE_CU_AB_1__SI 0x24DC -#define mmSPI_RESOURCE_RESERVE_CU_AB_2__SI 0x24DD -#define mmSPI_RESOURCE_RESERVE_CU_AB_3__SI 0x24DE -#define mmSPI_RESOURCE_RESERVE_CU_AB_4__SI 0x24DF -#define mmSPI_RESOURCE_RESERVE_CU_AB_5__SI 0x24E0 -#define mmSPI_RESOURCE_RESERVE_CU_AB_6__SI 0x24E1 -#define mmSPI_RESOURCE_RESERVE_CU_AB_7__SI 0x24E2 -#define mmSPI_RESOURCE_RESERVE_EN_CU_0__CI__VI 0x31E6 -#define mmSPI_RESOURCE_RESERVE_EN_CU_10__CI__VI 0x31F2 -#define mmSPI_RESOURCE_RESERVE_EN_CU_11__CI__VI 0x31F3 -#define mmSPI_RESOURCE_RESERVE_EN_CU_1__CI__VI 0x31E7 -#define mmSPI_RESOURCE_RESERVE_EN_CU_2__CI__VI 0x31E8 -#define mmSPI_RESOURCE_RESERVE_EN_CU_3__CI__VI 0x31E9 -#define mmSPI_RESOURCE_RESERVE_EN_CU_4__CI__VI 0x31EA -#define mmSPI_RESOURCE_RESERVE_EN_CU_5__CI__VI 0x31EB -#define mmSPI_RESOURCE_RESERVE_EN_CU_6__CI__VI 0x31EC -#define mmSPI_RESOURCE_RESERVE_EN_CU_7__CI__VI 0x31ED -#define mmSPI_RESOURCE_RESERVE_EN_CU_8__CI__VI 0x31EE -#define mmSPI_RESOURCE_RESERVE_EN_CU_9__CI__VI 0x31EF -#define mmSPI_SHADER_COL_FORMAT 0xA1C5 -#define mmSPI_SHADER_LATE_ALLOC_VS__CI__VI 0x2C47 -#define mmSPI_SHADER_PGM_HI_ES 0x2CC9 -#define mmSPI_SHADER_PGM_HI_GS 0x2C89 -#define mmSPI_SHADER_PGM_HI_HS 0x2D09 -#define mmSPI_SHADER_PGM_HI_LS 0x2D49 -#define mmSPI_SHADER_PGM_HI_PS 0x2C09 -#define mmSPI_SHADER_PGM_HI_VS 0x2C49 -#define mmSPI_SHADER_PGM_LO_ES 0x2CC8 -#define mmSPI_SHADER_PGM_LO_GS 0x2C88 -#define mmSPI_SHADER_PGM_LO_HS 0x2D08 -#define mmSPI_SHADER_PGM_LO_LS 0x2D48 -#define mmSPI_SHADER_PGM_LO_PS 0x2C08 -#define mmSPI_SHADER_PGM_LO_VS 0x2C48 -#define mmSPI_SHADER_PGM_RSRC1_ES 0x2CCA -#define mmSPI_SHADER_PGM_RSRC1_GS 0x2C8A -#define mmSPI_SHADER_PGM_RSRC1_HS 0x2D0A -#define mmSPI_SHADER_PGM_RSRC1_LS 0x2D4A -#define mmSPI_SHADER_PGM_RSRC1_PS 0x2C0A -#define mmSPI_SHADER_PGM_RSRC1_VS 0x2C4A -#define mmSPI_SHADER_PGM_RSRC2_ES 0x2CCB -#define mmSPI_SHADER_PGM_RSRC2_ES_GS__CI__VI 0x2CBC -#define mmSPI_SHADER_PGM_RSRC2_ES_VS__CI__VI 0x2C7C -#define mmSPI_SHADER_PGM_RSRC2_GS 0x2C8B -#define mmSPI_SHADER_PGM_RSRC2_HS 0x2D0B -#define mmSPI_SHADER_PGM_RSRC2_LS 0x2D4B -#define mmSPI_SHADER_PGM_RSRC2_LS_ES__CI__VI 0x2CFD -#define mmSPI_SHADER_PGM_RSRC2_LS_HS__CI__VI 0x2D3D -#define mmSPI_SHADER_PGM_RSRC2_LS_VS__CI__VI 0x2C7D -#define mmSPI_SHADER_PGM_RSRC2_PS 0x2C0B -#define mmSPI_SHADER_PGM_RSRC2_VS 0x2C4B -#define mmSPI_SHADER_PGM_RSRC3_ES__CI__VI 0x2CC7 -#define mmSPI_SHADER_PGM_RSRC3_GS__CI__VI 0x2C87 -#define mmSPI_SHADER_PGM_RSRC3_HS__CI__VI 0x2D07 -#define mmSPI_SHADER_PGM_RSRC3_LS__CI__VI 0x2D47 -#define mmSPI_SHADER_PGM_RSRC3_PS__CI__VI 0x2C07 -#define mmSPI_SHADER_PGM_RSRC3_VS__CI__VI 0x2C46 -#define mmSPI_SHADER_POS_FORMAT 0xA1C3 -#define mmSPI_SHADER_TBA_HI_ES 0x2CC1 -#define mmSPI_SHADER_TBA_HI_GS 0x2C81 -#define mmSPI_SHADER_TBA_HI_HS 0x2D01 -#define mmSPI_SHADER_TBA_HI_LS 0x2D41 -#define mmSPI_SHADER_TBA_HI_PS 0x2C01 -#define mmSPI_SHADER_TBA_HI_VS 0x2C41 -#define mmSPI_SHADER_TBA_LO_ES 0x2CC0 -#define mmSPI_SHADER_TBA_LO_GS 0x2C80 -#define mmSPI_SHADER_TBA_LO_HS 0x2D00 -#define mmSPI_SHADER_TBA_LO_LS 0x2D40 -#define mmSPI_SHADER_TBA_LO_PS 0x2C00 -#define mmSPI_SHADER_TBA_LO_VS 0x2C40 -#define mmSPI_SHADER_TMA_HI_ES 0x2CC3 -#define mmSPI_SHADER_TMA_HI_GS 0x2C83 -#define mmSPI_SHADER_TMA_HI_HS 0x2D03 -#define mmSPI_SHADER_TMA_HI_LS 0x2D43 -#define mmSPI_SHADER_TMA_HI_PS 0x2C03 -#define mmSPI_SHADER_TMA_HI_VS 0x2C43 -#define mmSPI_SHADER_TMA_LO_ES 0x2CC2 -#define mmSPI_SHADER_TMA_LO_GS 0x2C82 -#define mmSPI_SHADER_TMA_LO_HS 0x2D02 -#define mmSPI_SHADER_TMA_LO_LS 0x2D42 -#define mmSPI_SHADER_TMA_LO_PS 0x2C02 -#define mmSPI_SHADER_TMA_LO_VS 0x2C42 -#define mmSPI_SHADER_USER_DATA_ES_0 0x2CCC -#define mmSPI_SHADER_USER_DATA_ES_1 0x2CCD -#define mmSPI_SHADER_USER_DATA_ES_10 0x2CD6 -#define mmSPI_SHADER_USER_DATA_ES_11 0x2CD7 -#define mmSPI_SHADER_USER_DATA_ES_12 0x2CD8 -#define mmSPI_SHADER_USER_DATA_ES_13 0x2CD9 -#define mmSPI_SHADER_USER_DATA_ES_14 0x2CDA -#define mmSPI_SHADER_USER_DATA_ES_15 0x2CDB -#define mmSPI_SHADER_USER_DATA_ES_2 0x2CCE -#define mmSPI_SHADER_USER_DATA_ES_3 0x2CCF -#define mmSPI_SHADER_USER_DATA_ES_4 0x2CD0 -#define mmSPI_SHADER_USER_DATA_ES_5 0x2CD1 -#define mmSPI_SHADER_USER_DATA_ES_6 0x2CD2 -#define mmSPI_SHADER_USER_DATA_ES_7 0x2CD3 -#define mmSPI_SHADER_USER_DATA_ES_8 0x2CD4 -#define mmSPI_SHADER_USER_DATA_ES_9 0x2CD5 -#define mmSPI_SHADER_USER_DATA_GS_0 0x2C8C -#define mmSPI_SHADER_USER_DATA_GS_1 0x2C8D -#define mmSPI_SHADER_USER_DATA_GS_10 0x2C96 -#define mmSPI_SHADER_USER_DATA_GS_11 0x2C97 -#define mmSPI_SHADER_USER_DATA_GS_12 0x2C98 -#define mmSPI_SHADER_USER_DATA_GS_13 0x2C99 -#define mmSPI_SHADER_USER_DATA_GS_14 0x2C9A -#define mmSPI_SHADER_USER_DATA_GS_15 0x2C9B -#define mmSPI_SHADER_USER_DATA_GS_2 0x2C8E -#define mmSPI_SHADER_USER_DATA_GS_3 0x2C8F -#define mmSPI_SHADER_USER_DATA_GS_4 0x2C90 -#define mmSPI_SHADER_USER_DATA_GS_5 0x2C91 -#define mmSPI_SHADER_USER_DATA_GS_6 0x2C92 -#define mmSPI_SHADER_USER_DATA_GS_7 0x2C93 -#define mmSPI_SHADER_USER_DATA_GS_8 0x2C94 -#define mmSPI_SHADER_USER_DATA_GS_9 0x2C95 -#define mmSPI_SHADER_USER_DATA_HS_0 0x2D0C -#define mmSPI_SHADER_USER_DATA_HS_1 0x2D0D -#define mmSPI_SHADER_USER_DATA_HS_10 0x2D16 -#define mmSPI_SHADER_USER_DATA_HS_11 0x2D17 -#define mmSPI_SHADER_USER_DATA_HS_12 0x2D18 -#define mmSPI_SHADER_USER_DATA_HS_13 0x2D19 -#define mmSPI_SHADER_USER_DATA_HS_14 0x2D1A -#define mmSPI_SHADER_USER_DATA_HS_15 0x2D1B -#define mmSPI_SHADER_USER_DATA_HS_2 0x2D0E -#define mmSPI_SHADER_USER_DATA_HS_3 0x2D0F -#define mmSPI_SHADER_USER_DATA_HS_4 0x2D10 -#define mmSPI_SHADER_USER_DATA_HS_5 0x2D11 -#define mmSPI_SHADER_USER_DATA_HS_6 0x2D12 -#define mmSPI_SHADER_USER_DATA_HS_7 0x2D13 -#define mmSPI_SHADER_USER_DATA_HS_8 0x2D14 -#define mmSPI_SHADER_USER_DATA_HS_9 0x2D15 -#define mmSPI_SHADER_USER_DATA_LS_0 0x2D4C -#define mmSPI_SHADER_USER_DATA_LS_1 0x2D4D -#define mmSPI_SHADER_USER_DATA_LS_10 0x2D56 -#define mmSPI_SHADER_USER_DATA_LS_11 0x2D57 -#define mmSPI_SHADER_USER_DATA_LS_12 0x2D58 -#define mmSPI_SHADER_USER_DATA_LS_13 0x2D59 -#define mmSPI_SHADER_USER_DATA_LS_14 0x2D5A -#define mmSPI_SHADER_USER_DATA_LS_15 0x2D5B -#define mmSPI_SHADER_USER_DATA_LS_2 0x2D4E -#define mmSPI_SHADER_USER_DATA_LS_3 0x2D4F -#define mmSPI_SHADER_USER_DATA_LS_4 0x2D50 -#define mmSPI_SHADER_USER_DATA_LS_5 0x2D51 -#define mmSPI_SHADER_USER_DATA_LS_6 0x2D52 -#define mmSPI_SHADER_USER_DATA_LS_7 0x2D53 -#define mmSPI_SHADER_USER_DATA_LS_8 0x2D54 -#define mmSPI_SHADER_USER_DATA_LS_9 0x2D55 -#define mmSPI_SHADER_USER_DATA_PS_0 0x2C0C -#define mmSPI_SHADER_USER_DATA_PS_1 0x2C0D -#define mmSPI_SHADER_USER_DATA_PS_10 0x2C16 -#define mmSPI_SHADER_USER_DATA_PS_11 0x2C17 -#define mmSPI_SHADER_USER_DATA_PS_12 0x2C18 -#define mmSPI_SHADER_USER_DATA_PS_13 0x2C19 -#define mmSPI_SHADER_USER_DATA_PS_14 0x2C1A -#define mmSPI_SHADER_USER_DATA_PS_15 0x2C1B -#define mmSPI_SHADER_USER_DATA_PS_2 0x2C0E -#define mmSPI_SHADER_USER_DATA_PS_3 0x2C0F -#define mmSPI_SHADER_USER_DATA_PS_4 0x2C10 -#define mmSPI_SHADER_USER_DATA_PS_5 0x2C11 -#define mmSPI_SHADER_USER_DATA_PS_6 0x2C12 -#define mmSPI_SHADER_USER_DATA_PS_7 0x2C13 -#define mmSPI_SHADER_USER_DATA_PS_8 0x2C14 -#define mmSPI_SHADER_USER_DATA_PS_9 0x2C15 -#define mmSPI_SHADER_USER_DATA_VS_0 0x2C4C -#define mmSPI_SHADER_USER_DATA_VS_1 0x2C4D -#define mmSPI_SHADER_USER_DATA_VS_10 0x2C56 -#define mmSPI_SHADER_USER_DATA_VS_11 0x2C57 -#define mmSPI_SHADER_USER_DATA_VS_12 0x2C58 -#define mmSPI_SHADER_USER_DATA_VS_13 0x2C59 -#define mmSPI_SHADER_USER_DATA_VS_14 0x2C5A -#define mmSPI_SHADER_USER_DATA_VS_15 0x2C5B -#define mmSPI_SHADER_USER_DATA_VS_2 0x2C4E -#define mmSPI_SHADER_USER_DATA_VS_3 0x2C4F -#define mmSPI_SHADER_USER_DATA_VS_4 0x2C50 -#define mmSPI_SHADER_USER_DATA_VS_5 0x2C51 -#define mmSPI_SHADER_USER_DATA_VS_6 0x2C52 -#define mmSPI_SHADER_USER_DATA_VS_7 0x2C53 -#define mmSPI_SHADER_USER_DATA_VS_8 0x2C54 -#define mmSPI_SHADER_USER_DATA_VS_9 0x2C55 -#define mmSPI_SHADER_Z_FORMAT 0xA1C4 -#define mmSPI_SLAVE_DEBUG_BUSY 0x24D3 -#define mmSPI_STATIC_THREAD_MGMT_1__SI 0x2438 -#define mmSPI_STATIC_THREAD_MGMT_2__SI 0x2439 -#define mmSPI_STATIC_THREAD_MGMT_3__SI 0x243A -#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24D9 -#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24DA -#define mmSPI_TMPRING_SIZE 0xA1BA -#define mmSPI_VS_OUT_CONFIG 0xA1B1 -#define mmSPI_WAVE_MGMT_1__SI 0xA1C1 -#define mmSPI_WAVE_MGMT_2__SI 0xA1C2 -#define mmSPI_WCL_PIPE_PERCENT_CS0__CI__VI 0x31C9 -#define mmSPI_WCL_PIPE_PERCENT_CS1__CI__VI 0x31CA -#define mmSPI_WCL_PIPE_PERCENT_CS2__CI__VI 0x31CB -#define mmSPI_WCL_PIPE_PERCENT_CS3__CI__VI 0x31CC -#define mmSPI_WCL_PIPE_PERCENT_CS4__CI__VI 0x31CD -#define mmSPI_WCL_PIPE_PERCENT_CS5__CI__VI 0x31CE -#define mmSPI_WCL_PIPE_PERCENT_CS6__CI__VI 0x31CF -#define mmSPI_WCL_PIPE_PERCENT_CS7__CI__VI 0x31D0 -#define mmSPI_WCL_PIPE_PERCENT_GFX__CI__VI 0x31C7 -#define mmSPI_WCL_PIPE_PERCENT_HP3D__CI__VI 0x31C8 -#define mmSPI_WF_LIFETIME_CNTL__CI__VI 0x24AA -#define mmSPI_WF_LIFETIME_DEBUG__CI__VI 0x24CA -#define mmSPI_WF_LIFETIME_LIMIT_0__CI__VI 0x24AB -#define mmSPI_WF_LIFETIME_LIMIT_1__CI__VI 0x24AC -#define mmSPI_WF_LIFETIME_LIMIT_2__CI__VI 0x24AD -#define mmSPI_WF_LIFETIME_LIMIT_3__CI__VI 0x24AE -#define mmSPI_WF_LIFETIME_LIMIT_4__CI__VI 0x24AF -#define mmSPI_WF_LIFETIME_LIMIT_5__CI__VI 0x24B0 -#define mmSPI_WF_LIFETIME_LIMIT_6__CI__VI 0x24B1 -#define mmSPI_WF_LIFETIME_LIMIT_7__CI__VI 0x24B2 -#define mmSPI_WF_LIFETIME_LIMIT_8__CI__VI 0x24B3 -#define mmSPI_WF_LIFETIME_LIMIT_9__CI__VI 0x24B4 -#define mmSPI_WF_LIFETIME_STATUS_0__CI__VI 0x24B5 -#define mmSPI_WF_LIFETIME_STATUS_10__CI__VI 0x24BF -#define mmSPI_WF_LIFETIME_STATUS_11__CI__VI 0x24C0 -#define mmSPI_WF_LIFETIME_STATUS_12__CI__VI 0x24C1 -#define mmSPI_WF_LIFETIME_STATUS_13__CI__VI 0x24C2 -#define mmSPI_WF_LIFETIME_STATUS_14__CI__VI 0x24C3 -#define mmSPI_WF_LIFETIME_STATUS_15__CI__VI 0x24C4 -#define mmSPI_WF_LIFETIME_STATUS_16__CI__VI 0x24C5 -#define mmSPI_WF_LIFETIME_STATUS_17__CI__VI 0x24C6 -#define mmSPI_WF_LIFETIME_STATUS_18__CI__VI 0x24C7 -#define mmSPI_WF_LIFETIME_STATUS_19__CI__VI 0x24C8 -#define mmSPI_WF_LIFETIME_STATUS_1__CI__VI 0x24B6 -#define mmSPI_WF_LIFETIME_STATUS_20__CI__VI 0x24C9 -#define mmSPI_WF_LIFETIME_STATUS_2__CI__VI 0x24B7 -#define mmSPI_WF_LIFETIME_STATUS_3__CI__VI 0x24B8 -#define mmSPI_WF_LIFETIME_STATUS_4__CI__VI 0x24B9 -#define mmSPI_WF_LIFETIME_STATUS_5__CI__VI 0x24BA -#define mmSPI_WF_LIFETIME_STATUS_6__CI__VI 0x24BB -#define mmSPI_WF_LIFETIME_STATUS_7__CI__VI 0x24BC -#define mmSPI_WF_LIFETIME_STATUS_8__CI__VI 0x24BD -#define mmSPI_WF_LIFETIME_STATUS_9__CI__VI 0x24BE -#define mmSPLL_CNTL_MODE__SI 0x0186 -#define mmSPLL_TIME__SI 0x0187 -#define mmSPMI_SMC_IND_DATA__CI__VI 0x0081 -#define mmSPMI_SMC_IND_DATA_alt_1__CI__VI 0x0083 -#define mmSPMI_SMC_IND_DATA_alt_2__CI__VI 0x0085 -#define mmSPMI_SMC_IND_DATA_alt_3__CI__VI 0x0087 -#define mmSPMI_SMC_IND_INDEX__CI__VI 0x0080 -#define mmSPMI_SMC_IND_INDEX_alt_1__CI__VI 0x0082 -#define mmSPMI_SMC_IND_INDEX_alt_2__CI__VI 0x0084 -#define mmSPMI_SMC_IND_INDEX_alt_3__CI__VI 0x0086 -#define mmSQC_CACHES__CI__VI 0xC348 -#define mmSQC_CACHES__SI 0x2302 -#define mmSQC_CONFIG 0x2301 -#define mmSQC_POLICY__CI 0x230E -#define mmSQC_SECDED_CNT__SI__CI 0x23A0 -#define mmSQC_VOLATILE__CI 0x230F -#define mmSQ_ALU_CLK_CTRL__CI__VI 0xF08E -#define mmSQ_ALU_CLK_CTRL__SI 0x2360 -#define mmSQ_BUF_RSRC_WORD0 0x23C0 -#define mmSQ_BUF_RSRC_WORD1 0x23C1 -#define mmSQ_BUF_RSRC_WORD2 0x23C2 -#define mmSQ_BUF_RSRC_WORD3 0x23C3 -#define mmSQ_CAC_MASK__SI 0x2394 -#define mmSQ_CMD_TIMESTAMP__CI__VI 0x2375 -#define mmSQ_CMD__CI__VI 0x237B -#define mmSQ_CONFIG 0x2300 -#define mmSQ_DEBUG_STS_GLOBAL 0x2309 -#define mmSQ_DEBUG_STS_GLOBAL2__CI__VI 0x2310 -#define mmSQ_DEBUG_STS_GLOBAL3__CI__VI 0x2311 -#define mmSQ_DED_CNT__SI__CI 0x23A2 -#define mmSQ_DED_INFO__SI__CI 0x23A3 -#define mmSQ_DS_0 0x237F -#define mmSQ_DS_1 0x237F -#define mmSQ_EXP_0 0x237F -#define mmSQ_EXP_1 0x237F -#define mmSQ_FIFO_SIZES 0x2305 -#define mmSQ_FLAT_0__CI__VI 0x237F -#define mmSQ_FLAT_1__CI__VI 0x237F -#define mmSQ_FLAT_SCRATCH_WORD0__CI__VI 0x23D0 -#define mmSQ_FLAT_SCRATCH_WORD1__CI__VI 0x23D1 -#define mmSQ_HV_VMID_CTRL__CI__VI 0xF840 -#define mmSQ_IMG_RSRC_WORD0 0x23C4 -#define mmSQ_IMG_RSRC_WORD1 0x23C5 -#define mmSQ_IMG_RSRC_WORD2 0x23C6 -#define mmSQ_IMG_RSRC_WORD3 0x23C7 -#define mmSQ_IMG_RSRC_WORD4 0x23C8 -#define mmSQ_IMG_RSRC_WORD5 0x23C9 -#define mmSQ_IMG_RSRC_WORD6 0x23CA -#define mmSQ_IMG_RSRC_WORD7 0x23CB -#define mmSQ_IMG_SAMP_WORD0 0x23CC -#define mmSQ_IMG_SAMP_WORD1 0x23CD -#define mmSQ_IMG_SAMP_WORD2 0x23CE -#define mmSQ_IMG_SAMP_WORD3 0x23CF -#define mmSQ_IND_CMD__SI__CI 0x237A -#define mmSQ_IND_DATA 0x2379 -#define mmSQ_IND_INDEX 0x2378 -#define mmSQ_INST 0x237F -#define mmSQ_INTERRUPT_AUTO_MASK__CI__VI 0x2314 -#define mmSQ_INTERRUPT_MSG_CTRL__CI__VI 0x2315 -#define mmSQ_LB_CTR_CTRL 0x2398 -#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 -#define mmSQ_LB_DATA_ALU_STALLS 0x239B -#define mmSQ_LB_DATA_TEX_CYCLES 0x239A -#define mmSQ_LB_DATA_TEX_STALLS 0x239C -#define mmSQ_LDS_CLK_CTRL__CI__VI 0xF090 -#define mmSQ_MIMG_0 0x237F -#define mmSQ_MIMG_1 0x237F -#define mmSQ_MTBUF_0 0x237F -#define mmSQ_MTBUF_1 0x237F -#define mmSQ_MUBUF_0 0x237F -#define mmSQ_MUBUF_1 0x237F -#define mmSQ_PERFCOUNTER0_HI__CI__VI 0xD1C1 -#define mmSQ_PERFCOUNTER0_HI__SI 0x2321 -#define mmSQ_PERFCOUNTER0_LO__CI__VI 0xD1C0 -#define mmSQ_PERFCOUNTER0_LO__SI 0x2320 -#define mmSQ_PERFCOUNTER0_SELECT__CI__VI 0xD9C0 -#define mmSQ_PERFCOUNTER0_SELECT__SI 0x2340 -#define mmSQ_PERFCOUNTER10_HI__CI__VI 0xD1D5 -#define mmSQ_PERFCOUNTER10_HI__SI 0x2335 -#define mmSQ_PERFCOUNTER10_LO__CI__VI 0xD1D4 -#define mmSQ_PERFCOUNTER10_LO__SI 0x2334 -#define mmSQ_PERFCOUNTER10_SELECT__CI__VI 0xD9CA -#define mmSQ_PERFCOUNTER10_SELECT__SI 0x234A -#define mmSQ_PERFCOUNTER11_HI__CI__VI 0xD1D7 -#define mmSQ_PERFCOUNTER11_HI__SI 0x2337 -#define mmSQ_PERFCOUNTER11_LO__CI__VI 0xD1D6 -#define mmSQ_PERFCOUNTER11_LO__SI 0x2336 -#define mmSQ_PERFCOUNTER11_SELECT__CI__VI 0xD9CB -#define mmSQ_PERFCOUNTER11_SELECT__SI 0x234B -#define mmSQ_PERFCOUNTER12_HI__CI__VI 0xD1D9 -#define mmSQ_PERFCOUNTER12_HI__SI 0x2339 -#define mmSQ_PERFCOUNTER12_LO__CI__VI 0xD1D8 -#define mmSQ_PERFCOUNTER12_LO__SI 0x2338 -#define mmSQ_PERFCOUNTER12_SELECT__CI__VI 0xD9CC -#define mmSQ_PERFCOUNTER12_SELECT__SI 0x234C -#define mmSQ_PERFCOUNTER13_HI__CI__VI 0xD1DB -#define mmSQ_PERFCOUNTER13_HI__SI 0x233B -#define mmSQ_PERFCOUNTER13_LO__CI__VI 0xD1DA -#define mmSQ_PERFCOUNTER13_LO__SI 0x233A -#define mmSQ_PERFCOUNTER13_SELECT__CI__VI 0xD9CD -#define mmSQ_PERFCOUNTER13_SELECT__SI 0x234D -#define mmSQ_PERFCOUNTER14_HI__CI__VI 0xD1DD -#define mmSQ_PERFCOUNTER14_HI__SI 0x233D -#define mmSQ_PERFCOUNTER14_LO__CI__VI 0xD1DC -#define mmSQ_PERFCOUNTER14_LO__SI 0x233C -#define mmSQ_PERFCOUNTER14_SELECT__CI__VI 0xD9CE -#define mmSQ_PERFCOUNTER14_SELECT__SI 0x234E -#define mmSQ_PERFCOUNTER15_HI__CI__VI 0xD1DF -#define mmSQ_PERFCOUNTER15_HI__SI 0x233F -#define mmSQ_PERFCOUNTER15_LO__CI__VI 0xD1DE -#define mmSQ_PERFCOUNTER15_LO__SI 0x233E -#define mmSQ_PERFCOUNTER15_SELECT__CI__VI 0xD9CF -#define mmSQ_PERFCOUNTER15_SELECT__SI 0x234F -#define mmSQ_PERFCOUNTER1_HI__CI__VI 0xD1C3 -#define mmSQ_PERFCOUNTER1_HI__SI 0x2323 -#define mmSQ_PERFCOUNTER1_LO__CI__VI 0xD1C2 -#define mmSQ_PERFCOUNTER1_LO__SI 0x2322 -#define mmSQ_PERFCOUNTER1_SELECT__CI__VI 0xD9C1 -#define mmSQ_PERFCOUNTER1_SELECT__SI 0x2341 -#define mmSQ_PERFCOUNTER2_HI__CI__VI 0xD1C5 -#define mmSQ_PERFCOUNTER2_HI__SI 0x2325 -#define mmSQ_PERFCOUNTER2_LO__CI__VI 0xD1C4 -#define mmSQ_PERFCOUNTER2_LO__SI 0x2324 -#define mmSQ_PERFCOUNTER2_SELECT__CI__VI 0xD9C2 -#define mmSQ_PERFCOUNTER2_SELECT__SI 0x2342 -#define mmSQ_PERFCOUNTER3_HI__CI__VI 0xD1C7 -#define mmSQ_PERFCOUNTER3_HI__SI 0x2327 -#define mmSQ_PERFCOUNTER3_LO__CI__VI 0xD1C6 -#define mmSQ_PERFCOUNTER3_LO__SI 0x2326 -#define mmSQ_PERFCOUNTER3_SELECT__CI__VI 0xD9C3 -#define mmSQ_PERFCOUNTER3_SELECT__SI 0x2343 -#define mmSQ_PERFCOUNTER4_HI__CI__VI 0xD1C9 -#define mmSQ_PERFCOUNTER4_HI__SI 0x2329 -#define mmSQ_PERFCOUNTER4_LO__CI__VI 0xD1C8 -#define mmSQ_PERFCOUNTER4_LO__SI 0x2328 -#define mmSQ_PERFCOUNTER4_SELECT__CI__VI 0xD9C4 -#define mmSQ_PERFCOUNTER4_SELECT__SI 0x2344 -#define mmSQ_PERFCOUNTER5_HI__CI__VI 0xD1CB -#define mmSQ_PERFCOUNTER5_HI__SI 0x232B -#define mmSQ_PERFCOUNTER5_LO__CI__VI 0xD1CA -#define mmSQ_PERFCOUNTER5_LO__SI 0x232A -#define mmSQ_PERFCOUNTER5_SELECT__CI__VI 0xD9C5 -#define mmSQ_PERFCOUNTER5_SELECT__SI 0x2345 -#define mmSQ_PERFCOUNTER6_HI__CI__VI 0xD1CD -#define mmSQ_PERFCOUNTER6_HI__SI 0x232D -#define mmSQ_PERFCOUNTER6_LO__CI__VI 0xD1CC -#define mmSQ_PERFCOUNTER6_LO__SI 0x232C -#define mmSQ_PERFCOUNTER6_SELECT__CI__VI 0xD9C6 -#define mmSQ_PERFCOUNTER6_SELECT__SI 0x2346 -#define mmSQ_PERFCOUNTER7_HI__CI__VI 0xD1CF -#define mmSQ_PERFCOUNTER7_HI__SI 0x232F -#define mmSQ_PERFCOUNTER7_LO__CI__VI 0xD1CE -#define mmSQ_PERFCOUNTER7_LO__SI 0x232E -#define mmSQ_PERFCOUNTER7_SELECT__CI__VI 0xD9C7 -#define mmSQ_PERFCOUNTER7_SELECT__SI 0x2347 -#define mmSQ_PERFCOUNTER8_HI__CI__VI 0xD1D1 -#define mmSQ_PERFCOUNTER8_HI__SI 0x2331 -#define mmSQ_PERFCOUNTER8_LO__CI__VI 0xD1D0 -#define mmSQ_PERFCOUNTER8_LO__SI 0x2330 -#define mmSQ_PERFCOUNTER8_SELECT__CI__VI 0xD9C8 -#define mmSQ_PERFCOUNTER8_SELECT__SI 0x2348 -#define mmSQ_PERFCOUNTER9_HI__CI__VI 0xD1D3 -#define mmSQ_PERFCOUNTER9_HI__SI 0x2333 -#define mmSQ_PERFCOUNTER9_LO__CI__VI 0xD1D2 -#define mmSQ_PERFCOUNTER9_LO__SI 0x2332 -#define mmSQ_PERFCOUNTER9_SELECT__CI__VI 0xD9C9 -#define mmSQ_PERFCOUNTER9_SELECT__SI 0x2349 -#define mmSQ_PERFCOUNTER_CTRL2__CI__VI 0xD9E2 -#define mmSQ_PERFCOUNTER_CTRL__CI__VI 0xD9E0 -#define mmSQ_PERFCOUNTER_CTRL__SI 0x2306 -#define mmSQ_PERFCOUNTER_MASK__CI__VI 0xD9E1 -#define mmSQ_POWER_THROTTLE2__CI__VI 0xF092 -#define mmSQ_POWER_THROTTLE2__SI 0x2397 -#define mmSQ_POWER_THROTTLE__CI__VI 0xF091 -#define mmSQ_POWER_THROTTLE__SI 0x2396 -#define mmSQ_RANDOM_WAVE_PRI 0x2303 -#define mmSQ_REG_CREDITS 0x2304 -#define mmSQ_REG_TIMESTAMP__CI__VI 0x2374 -#define mmSQ_SEC_CNT__SI__CI 0x23A1 -#define mmSQ_SMRD__SI__CI 0x237F -#define mmSQ_SOP1 0x237F -#define mmSQ_SOP2 0x237F -#define mmSQ_SOPC 0x237F -#define mmSQ_SOPK 0x237F -#define mmSQ_SOPP 0x237F -#define mmSQ_TEX_CLK_CTRL__CI__VI 0xF08F -#define mmSQ_TEX_CLK_CTRL__SI 0x2361 -#define mmSQ_THREAD_TRACE_BASE2__CI 0x2385 -#define mmSQ_THREAD_TRACE_CNTR 0x2390 -#define mmSQ_THREAD_TRACE_TOKEN_MASK2__CI 0x2386 -#define mmSQ_THREAD_TRACE_USERDATA_0__CI__VI 0xC340 -#define mmSQ_THREAD_TRACE_USERDATA_0__SI 0x2388 -#define mmSQ_THREAD_TRACE_USERDATA_1__CI__VI 0xC341 -#define mmSQ_THREAD_TRACE_USERDATA_1__SI 0x2389 -#define mmSQ_THREAD_TRACE_USERDATA_2__CI__VI 0xC342 -#define mmSQ_THREAD_TRACE_USERDATA_2__SI 0x238A -#define mmSQ_THREAD_TRACE_USERDATA_3__CI__VI 0xC343 -#define mmSQ_THREAD_TRACE_USERDATA_3__SI 0x238B -#define mmSQ_THREAD_TRACE_WORD_CMN 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23B1 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23B1 -#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_MISC 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23B1 -#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23B1 -#define mmSQ_THREAD_TRACE_WORD_TIME__SI 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23B0 -#define mmSQ_TIME_HI 0x237C -#define mmSQ_TIME_LO 0x237D -#define mmSQ_VINTRP 0x237F -#define mmSQ_VOP1 0x237F -#define mmSQ_VOP2 0x237F -#define mmSQ_VOP3_0 0x237F -#define mmSQ_VOP3_0_SDST_ENC 0x237F -#define mmSQ_VOP3_1 0x237F -#define mmSQ_VOPC 0x237F -#define mmSRBM_CHIP_REVISION 0x039B -#define mmSRBM_CNTL 0x0390 -#define mmSRBM_DEBUG 0x03A4 -#define mmSRBM_DEBUG_CNTL 0x0399 -#define mmSRBM_DEBUG_DATA 0x039A -#define mmSRBM_DEBUG_SNAPSHOT 0x03A5 -#define mmSRBM_DRMDMA_CLKEN_CNTL__SI 0x03B7 -#define mmSRBM_GFX_CNTL 0x0391 -#define mmSRBM_INT_ACK 0x03AA -#define mmSRBM_INT_CNTL 0x03A8 -#define mmSRBM_INT_STATUS 0x03A9 -#define mmSRBM_MC_CLKEN_CNTL__CI__VI 0x03B3 -#define mmSRBM_READ_ERROR 0x03A6 -#define mmSRBM_SAM_CLKEN_CNTL__CI__VI 0x03B8 -#define mmSRBM_SDMA_CLKEN_CNTL__CI__VI 0x03B7 -#define mmSRBM_SOFT_RESET 0x0398 -#define mmSRBM_STATUS 0x0394 -#define mmSRBM_STATUS2 0x0393 -#define mmSRBM_SYS_CLKEN_CNTL 0x03B4 -#define mmSRBM_UVD_CLKEN_CNTL 0x03B6 -#define mmSRBM_VCE_CLKEN_CNTL 0x03B5 -#define mmSTUTTER_A_CNT__SI 0x1ACD -#define mmSTUTTER_B_CNT__SI 0x1ACE -#define mmSX_DEBUG_1 0x2418 -#define mmSX_DEBUG_BUSY 0x2414 -#define mmSX_DEBUG_BUSY_2 0x2415 -#define mmSX_DEBUG_BUSY_3 0x2416 -#define mmSX_DEBUG_BUSY_4 0x2417 -#define mmSX_PERFCOUNTER0_HI__CI__VI 0xD241 -#define mmSX_PERFCOUNTER0_HI__SI 0x2421 -#define mmSX_PERFCOUNTER0_LO__CI__VI 0xD240 -#define mmSX_PERFCOUNTER0_LO__SI 0x2420 -#define mmSX_PERFCOUNTER0_SELECT1__CI__VI 0xDA44 -#define mmSX_PERFCOUNTER0_SELECT__CI__VI 0xDA40 -#define mmSX_PERFCOUNTER0_SELECT__SI 0x241C -#define mmSX_PERFCOUNTER1_HI__CI__VI 0xD243 -#define mmSX_PERFCOUNTER1_HI__SI 0x2423 -#define mmSX_PERFCOUNTER1_LO__CI__VI 0xD242 -#define mmSX_PERFCOUNTER1_LO__SI 0x2422 -#define mmSX_PERFCOUNTER1_SELECT1__CI__VI 0xDA45 -#define mmSX_PERFCOUNTER1_SELECT__CI__VI 0xDA41 -#define mmSX_PERFCOUNTER1_SELECT__SI 0x241D -#define mmSX_PERFCOUNTER2_HI__CI__VI 0xD245 -#define mmSX_PERFCOUNTER2_HI__SI 0x2425 -#define mmSX_PERFCOUNTER2_LO__CI__VI 0xD244 -#define mmSX_PERFCOUNTER2_LO__SI 0x2424 -#define mmSX_PERFCOUNTER2_SELECT__CI__VI 0xDA42 -#define mmSX_PERFCOUNTER2_SELECT__SI 0x241E -#define mmSX_PERFCOUNTER3_HI__CI__VI 0xD247 -#define mmSX_PERFCOUNTER3_HI__SI 0x2427 -#define mmSX_PERFCOUNTER3_LO__CI__VI 0xD246 -#define mmSX_PERFCOUNTER3_LO__SI 0x2426 -#define mmSX_PERFCOUNTER3_SELECT__CI__VI 0xDA43 -#define mmSX_PERFCOUNTER3_SELECT__SI 0x241F -#define mmTARGET_AND_CURRENT_PROFILE_INDEX_1__SI 0x021D -#define mmTARGET_AND_CURRENT_PROFILE_INDEX__SI 0x01E6 -#define mmTA_BC_BASE_ADDR 0xA020 -#define mmTA_BC_BASE_ADDR_HI__CI__VI 0xA021 -#define mmTA_CGTT_CTRL__CI__VI 0xF09D -#define mmTA_CGTT_CTRL__SI 0x2544 -#define mmTA_CNTL 0x2541 -#define mmTA_CNTL_AUX 0x2542 -#define mmTA_CS_BC_BASE_ADDR_HI__CI__VI 0xC381 -#define mmTA_CS_BC_BASE_ADDR__CI__VI 0xC380 -#define mmTA_CS_BC_BASE_ADDR__SI 0x2543 -#define mmTA_DEBUG_DATA 0x254D -#define mmTA_DEBUG_INDEX 0x254C -#define mmTA_PERFCOUNTER0_HI__CI__VI 0xD2C1 -#define mmTA_PERFCOUNTER0_HI__SI 0x2556 -#define mmTA_PERFCOUNTER0_LO__CI__VI 0xD2C0 -#define mmTA_PERFCOUNTER0_LO__SI 0x2555 -#define mmTA_PERFCOUNTER0_SELECT1__CI__VI 0xDAC1 -#define mmTA_PERFCOUNTER0_SELECT__CI__VI 0xDAC0 -#define mmTA_PERFCOUNTER0_SELECT__SI 0x2554 -#define mmTA_PERFCOUNTER1_HI__CI__VI 0xD2C3 -#define mmTA_PERFCOUNTER1_HI__SI 0x2562 -#define mmTA_PERFCOUNTER1_LO__CI__VI 0xD2C2 -#define mmTA_PERFCOUNTER1_LO__SI 0x2561 -#define mmTA_PERFCOUNTER1_SELECT__CI__VI 0xDAC2 -#define mmTA_PERFCOUNTER1_SELECT__SI 0x2560 -#define mmTA_RESERVED_010C__CI__VI 0x2543 -#define mmTA_SCRATCH 0x2564 -#define mmTA_STATUS 0x2548 -#define mmTCA_CGTT_SCLK_CTRL__CI__VI 0xF0AD -#define mmTCA_CGTT_SCLK_CTRL__SI 0x2BC1 -#define mmTCA_CTRL 0x2BC0 -#define mmTCA_PERFCOUNTER0_HI__CI__VI 0xD391 -#define mmTCA_PERFCOUNTER0_HI__SI 0x2BD2 -#define mmTCA_PERFCOUNTER0_LO__CI__VI 0xD390 -#define mmTCA_PERFCOUNTER0_LO__SI 0x2BD1 -#define mmTCA_PERFCOUNTER0_SELECT1__CI__VI 0xDB91 -#define mmTCA_PERFCOUNTER0_SELECT__CI__VI 0xDB90 -#define mmTCA_PERFCOUNTER0_SELECT__SI 0x2BD0 -#define mmTCA_PERFCOUNTER1_HI__CI__VI 0xD393 -#define mmTCA_PERFCOUNTER1_HI__SI 0x2BD5 -#define mmTCA_PERFCOUNTER1_LO__CI__VI 0xD392 -#define mmTCA_PERFCOUNTER1_LO__SI 0x2BD4 -#define mmTCA_PERFCOUNTER1_SELECT1__CI__VI 0xDB93 -#define mmTCA_PERFCOUNTER1_SELECT__CI__VI 0xDB92 -#define mmTCA_PERFCOUNTER1_SELECT__SI 0x2BD3 -#define mmTCA_PERFCOUNTER2_HI__CI__VI 0xD395 -#define mmTCA_PERFCOUNTER2_HI__SI 0x2BD8 -#define mmTCA_PERFCOUNTER2_LO__CI__VI 0xD394 -#define mmTCA_PERFCOUNTER2_LO__SI 0x2BD7 -#define mmTCA_PERFCOUNTER2_SELECT__CI__VI 0xDB94 -#define mmTCA_PERFCOUNTER2_SELECT__SI 0x2BD6 -#define mmTCA_PERFCOUNTER3_HI__CI__VI 0xD397 -#define mmTCA_PERFCOUNTER3_HI__SI 0x2BDB -#define mmTCA_PERFCOUNTER3_LO__CI__VI 0xD396 -#define mmTCA_PERFCOUNTER3_LO__SI 0x2BDA -#define mmTCA_PERFCOUNTER3_SELECT__CI__VI 0xDB95 -#define mmTCA_PERFCOUNTER3_SELECT__SI 0x2BD9 -#define mmTCC_CGTT_SCLK_CTRL__CI__VI 0xF0AC -#define mmTCC_CGTT_SCLK_CTRL__SI 0x2B81 -#define mmTCC_CTRL 0x2B80 -#define mmTCC_EDC_COUNTER__SI__CI 0x2B82 -#define mmTCC_PERFCOUNTER0_HI__CI__VI 0xD381 -#define mmTCC_PERFCOUNTER0_HI__SI 0x2B92 -#define mmTCC_PERFCOUNTER0_LO__CI__VI 0xD380 -#define mmTCC_PERFCOUNTER0_LO__SI 0x2B91 -#define mmTCC_PERFCOUNTER0_SELECT1__CI__VI 0xDB81 -#define mmTCC_PERFCOUNTER0_SELECT__CI__VI 0xDB80 -#define mmTCC_PERFCOUNTER0_SELECT__SI 0x2B90 -#define mmTCC_PERFCOUNTER1_HI__CI__VI 0xD383 -#define mmTCC_PERFCOUNTER1_HI__SI 0x2B95 -#define mmTCC_PERFCOUNTER1_LO__CI__VI 0xD382 -#define mmTCC_PERFCOUNTER1_LO__SI 0x2B94 -#define mmTCC_PERFCOUNTER1_SELECT1__CI__VI 0xDB83 -#define mmTCC_PERFCOUNTER1_SELECT__CI__VI 0xDB82 -#define mmTCC_PERFCOUNTER1_SELECT__SI 0x2B93 -#define mmTCC_PERFCOUNTER2_HI__CI__VI 0xD385 -#define mmTCC_PERFCOUNTER2_HI__SI 0x2B98 -#define mmTCC_PERFCOUNTER2_LO__CI__VI 0xD384 -#define mmTCC_PERFCOUNTER2_LO__SI 0x2B97 -#define mmTCC_PERFCOUNTER2_SELECT__CI__VI 0xDB84 -#define mmTCC_PERFCOUNTER2_SELECT__SI 0x2B96 -#define mmTCC_PERFCOUNTER3_HI__CI__VI 0xD387 -#define mmTCC_PERFCOUNTER3_HI__SI 0x2B9B -#define mmTCC_PERFCOUNTER3_LO__CI__VI 0xD386 -#define mmTCC_PERFCOUNTER3_LO__SI 0x2B9A -#define mmTCC_PERFCOUNTER3_SELECT__CI__VI 0xDB85 -#define mmTCC_PERFCOUNTER3_SELECT__SI 0x2B99 -#define mmTCC_REDUNDANCY__CI__VI 0x2B83 -#define mmTCI_CNTL_1 0x2B62 -#define mmTCI_CNTL_2 0x2B63 -#define mmTCI_STATUS 0x2B61 -#define mmTCP_ADDR_CONFIG 0x2B05 -#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2B16 -#define mmTCP_CHAN_STEER_HI 0x2B04 -#define mmTCP_CHAN_STEER_LO 0x2B03 -#define mmTCP_CNTL 0x2B02 -#define mmTCP_CREDIT 0x2B06 -#define mmTCP_DEBUG_DATA 0x2B08 -#define mmTCP_DEBUG_INDEX 0x2B07 -#define mmTCP_EDC_COUNTER__SI__CI 0x2B17 -#define mmTCP_INVALIDATE 0x2B00 -#define mmTCP_PERFCOUNTER0_HI__CI__VI 0xD341 -#define mmTCP_PERFCOUNTER0_HI__SI 0x2B0A -#define mmTCP_PERFCOUNTER0_LO__CI__VI 0xD340 -#define mmTCP_PERFCOUNTER0_LO__SI 0x2B0B -#define mmTCP_PERFCOUNTER0_SELECT1__CI__VI 0xDB41 -#define mmTCP_PERFCOUNTER0_SELECT__CI__VI 0xDB40 -#define mmTCP_PERFCOUNTER0_SELECT__SI 0x2B09 -#define mmTCP_PERFCOUNTER1_HI__CI__VI 0xD343 -#define mmTCP_PERFCOUNTER1_HI__SI 0x2B0D -#define mmTCP_PERFCOUNTER1_LO__CI__VI 0xD342 -#define mmTCP_PERFCOUNTER1_LO__SI 0x2B0E -#define mmTCP_PERFCOUNTER1_SELECT1__CI__VI 0xDB43 -#define mmTCP_PERFCOUNTER1_SELECT__CI__VI 0xDB42 -#define mmTCP_PERFCOUNTER1_SELECT__SI 0x2B0C -#define mmTCP_PERFCOUNTER2_HI__CI__VI 0xD345 -#define mmTCP_PERFCOUNTER2_HI__SI 0x2B10 -#define mmTCP_PERFCOUNTER2_LO__CI__VI 0xD344 -#define mmTCP_PERFCOUNTER2_LO__SI 0x2B11 -#define mmTCP_PERFCOUNTER2_SELECT__CI__VI 0xDB44 -#define mmTCP_PERFCOUNTER2_SELECT__SI 0x2B0F -#define mmTCP_PERFCOUNTER3_HI__CI__VI 0xD347 -#define mmTCP_PERFCOUNTER3_HI__SI 0x2B13 -#define mmTCP_PERFCOUNTER3_LO__CI__VI 0xD346 -#define mmTCP_PERFCOUNTER3_LO__SI 0x2B14 -#define mmTCP_PERFCOUNTER3_SELECT__CI__VI 0xDB45 -#define mmTCP_PERFCOUNTER3_SELECT__SI 0x2B12 -#define mmTCP_STATUS 0x2B01 -#define mmTCP_WATCH0_ADDR_H__CI__VI 0x32A0 -#define mmTCP_WATCH0_ADDR_L__CI__VI 0x32A1 -#define mmTCP_WATCH0_CNTL__CI__VI 0x32A2 -#define mmTCP_WATCH1_ADDR_H__CI__VI 0x32A3 -#define mmTCP_WATCH1_ADDR_L__CI__VI 0x32A4 -#define mmTCP_WATCH1_CNTL__CI__VI 0x32A5 -#define mmTCP_WATCH2_ADDR_H__CI__VI 0x32A6 -#define mmTCP_WATCH2_ADDR_L__CI__VI 0x32A7 -#define mmTCP_WATCH2_CNTL__CI__VI 0x32A8 -#define mmTCP_WATCH3_ADDR_H__CI__VI 0x32A9 -#define mmTCP_WATCH3_ADDR_L__CI__VI 0x32AA -#define mmTCP_WATCH3_CNTL__CI__VI 0x32AB -#define mmTCS_CGTT_SCLK_CTRL__CI 0xF0AE -#define mmTCS_CTRL__CI 0x2BE0 -#define mmTCS_PERFCOUNTER0_HI__CI 0xD3A1 -#define mmTCS_PERFCOUNTER0_LO__CI 0xD3A0 -#define mmTCS_PERFCOUNTER0_SELECT1__CI 0xDBA1 -#define mmTCS_PERFCOUNTER0_SELECT__CI 0xDBA0 -#define mmTCS_PERFCOUNTER1_HI__CI 0xD3A3 -#define mmTCS_PERFCOUNTER1_LO__CI 0xD3A2 -#define mmTCS_PERFCOUNTER1_SELECT__CI 0xDBA2 -#define mmTCS_PERFCOUNTER2_HI__CI 0xD3A5 -#define mmTCS_PERFCOUNTER2_LO__CI 0xD3A4 -#define mmTCS_PERFCOUNTER2_SELECT__CI 0xDBA3 -#define mmTCS_PERFCOUNTER3_HI__CI 0xD3A7 -#define mmTCS_PERFCOUNTER3_LO__CI 0xD3A6 -#define mmTCS_PERFCOUNTER3_SELECT__CI 0xDBA4 -#define mmTC_CFG_L1_LOAD_POLICY0__CI__VI 0x2B1A -#define mmTC_CFG_L1_LOAD_POLICY1__CI__VI 0x2B1B -#define mmTC_CFG_L1_STORE_POLICY__CI__VI 0x2B1C -#define mmTC_CFG_L1_VOLATILE__CI__VI 0x2B22 -#define mmTC_CFG_L2_ATOMIC_POLICY__CI__VI 0x2B21 -#define mmTC_CFG_L2_LOAD_POLICY0__CI__VI 0x2B1D -#define mmTC_CFG_L2_LOAD_POLICY1__CI__VI 0x2B1E -#define mmTC_CFG_L2_STORE_POLICY0__CI__VI 0x2B1F -#define mmTC_CFG_L2_STORE_POLICY1__CI__VI 0x2B20 -#define mmTC_CFG_L2_VOLATILE__CI__VI 0x2B23 -#define mmTD_CGTT_CTRL__CI__VI 0xF09C -#define mmTD_CGTT_CTRL__SI 0x2527 -#define mmTD_CNTL 0x2525 -#define mmTD_DEBUG_DATA 0x2529 -#define mmTD_DEBUG_INDEX 0x2528 -#define mmTD_PERFCOUNTER0_HI__CI__VI 0xD301 -#define mmTD_PERFCOUNTER0_HI__SI 0x252E -#define mmTD_PERFCOUNTER0_LO__CI__VI 0xD300 -#define mmTD_PERFCOUNTER0_LO__SI 0x252D -#define mmTD_PERFCOUNTER0_SELECT1__CI__VI 0xDB01 -#define mmTD_PERFCOUNTER0_SELECT__CI__VI 0xDB00 -#define mmTD_PERFCOUNTER0_SELECT__SI 0x252C -#define mmTD_PERFCOUNTER1_HI__CI__VI 0xD303 -#define mmTD_PERFCOUNTER1_LO__CI__VI 0xD302 -#define mmTD_PERFCOUNTER1_SELECT__CI__VI 0xDB02 -#define mmTD_SCRATCH__CI__VI 0x2533 -#define mmTD_SCRATCH__SI 0x2530 -#define mmTD_STATUS 0x2526 -#define mmTHERMAL_PROTECT_COUNTER__SI 0x01E1 -#define mmTHM_CLK_CNTL__SI 0x019A -#define mmTHM_CMON_CTRL2__SI 0x01E9 -#define mmTHM_CMON_CTRL__SI 0x01E8 -#define mmTHM_SMC_IND_DATA__CI 0x0081 -#define mmTHM_SMC_IND_DATA_alt_1__CI 0x0083 -#define mmTHM_SMC_IND_DATA_alt_2__CI 0x0085 -#define mmTHM_SMC_IND_DATA_alt_3__CI 0x0087 -#define mmTHM_SMC_IND_INDEX__CI 0x0080 -#define mmTHM_SMC_IND_INDEX_alt_1__CI 0x0082 -#define mmTHM_SMC_IND_INDEX_alt_2__CI 0x0084 -#define mmTHM_SMC_IND_INDEX_alt_3__CI 0x0086 -#define mmTHM_TMON0_CSR_RD__SI 0x01CB -#define mmTHM_TMON0_CSR_WR__SI 0x01CA -#define mmTHM_TMON0_CTRL2__SI 0x01D8 -#define mmTHM_TMON0_CTRL__SI 0x01C9 -#define mmTHM_TMON1_CSR_RD__SI 0x01CE -#define mmTHM_TMON1_CSR_WR__SI 0x01CD -#define mmTHM_TMON1_CTRL2__SI 0x01D9 -#define mmTHM_TMON1_CTRL__SI 0x01CC -#define mmTHM_TMON_CONFIG2__SI 0x01C8 -#define mmTHM_TMON_CONFIG__SI 0x01C7 -#define mmTMDS_CNTL__SI 0x1C7C -#define mmTMDS_CONTROL0_FEEDBACK__SI 0x1C7E -#define mmTMDS_CONTROL_CHAR__SI 0x1C7D -#define mmTMDS_CTL0_1_GEN_CNTL__SI 0x1C86 -#define mmTMDS_CTL2_3_GEN_CNTL__SI 0x1C87 -#define mmTMDS_CTL_BITS__SI 0x1C83 -#define mmTMDS_DCBALANCER_CONTROL__SI 0x1C84 -#define mmTMDS_DEBUG__SI 0x1C82 -#define mmTMDS_STEREOSYNC_CTL_SEL__SI 0x1C7F -#define mmTMDS_SYNC_CHAR_PATTERN_0_1__SI 0x1C80 -#define mmTMDS_SYNC_CHAR_PATTERN_2_3__SI 0x1C81 -#define mmTMDS_SYNC_DCBALANCE_CHAR__SI 0x1C85 -#define mmTST_MISC_CTRL 0x0062 -#define mmTST_TC_JTAG_0 0x0063 -#define mmTST_TC_JTAG_1 0x0064 -#define mmUNDERFLOW_STATUS__SI 0x1AF0 -#define mmUNIPHY_DATA_SYNCHRONIZATION__SI 0x1984 -#define mmUNIPHY_IMPCAL_LINKA__SI 0x1947 -#define mmUNIPHY_IMPCAL_LINKB__SI 0x1948 -#define mmUNIPHY_IMPCAL_LINKC__SI 0x194D -#define mmUNIPHY_IMPCAL_LINKD__SI 0x194E -#define mmUNIPHY_IMPCAL_LINKE__SI 0x1950 -#define mmUNIPHY_IMPCAL_LINKF__SI 0x1951 -#define mmUNIPHY_IMPCAL_PERIOD__SI 0x1949 -#define mmUNIPHY_MACRO_CONTROL1__SI 0x1980 -#define mmUNIPHY_MACRO_CONTROL2__SI 0x1981 -#define mmUNIPHY_MACRO_CONTROL3__SI 0x1982 -#define mmUNIPHY_MACRO_CONTROL4__SI 0x1983 -#define mmUNIPHY_REG_TEST_OUTPUT__SI 0x1986 -#define mmUNIPHY_TRANSMITTER_CONTROL__SI 0x1985 -#define mmURGENCY_STAT__SI 0x1AF1 -#define mmUSER_SQC_BANK_DISABLE 0x2308 -#define mmUVD_ADDR_MODE__SI 0x3D70 -#define mmUVD_CBUF_ID__SI 0x3DBC -#define mmUVD_CGC_CTRL__SI 0x3D2C -#define mmUVD_CGC_GATE__SI 0x3D2A -#define mmUVD_CGC_STATUS__SI 0x3D2B -#define mmUVD_CONFIG__CI 0x0F93 -#define mmUVD_CONFIG__SI 0x0F98 -#define mmUVD_CONTEXT_ID__SI 0x3DBD -#define mmUVD_CTX_DATA__SI 0x3D29 -#define mmUVD_CTX_INDEX__SI 0x3D28 -#define mmUVD_CXW_BLOCK_STATUS__SI 0x3DB9 -#define mmUVD_CXW_CNTL__SI 0x3DC0 -#define mmUVD_CXW_EN__SI 0x3DB4 -#define mmUVD_CXW_EVENT__SI 0x3DC1 -#define mmUVD_CXW_FINISHED__SI 0x3DB6 -#define mmUVD_CXW_INT_ID__SI 0x3DD3 -#define mmUVD_CXW_SAVE_AREA_ADDR__SI 0x3DBB -#define mmUVD_CXW_SAVE_AREA_SIZE__SI 0x3DBE -#define mmUVD_CXW_SCAN_AREA_OFFSET__SI 0x3DC2 -#define mmUVD_CXW_SE__SI 0x3DB5 -#define mmUVD_CXW_SHIFT_CNTL__SI 0x3DC3 -#define mmUVD_CXW_SHIFT_FINISHED__SI 0x3DB7 -#define mmUVD_CXW_START__SI 0x3DB8 -#define mmUVD_CXW_WR_INT_CTX_ID__SI 0x3D2F -#define mmUVD_CXW_WR_INT_ID__SI 0x3D2E -#define mmUVD_CXW_WR__SI 0x3D9F -#define mmUVD_DBW_BUF_SIZE__SI 0x3DD2 -#define mmUVD_DBW_CHROMA_ADR__SI 0x3DDB -#define mmUVD_DBW_CHROMA_BOT_ADR__SI 0x3DDC -#define mmUVD_DBW_LUMA_ADR__SI 0x3DCF -#define mmUVD_DBW_LUMA_BOT_ADR__SI 0x3DDA -#define mmUVD_DBW_MACRO_TILE_CONFIG__SI 0x3BD5 -#define mmUVD_DBW_MEM_ADDR_SEL_0__SI 0x3BD3 -#define mmUVD_DBW_MEM_ADDR_SEL_1__SI 0x3BD4 -#define mmUVD_DB_MACRO_TILE_CONFIG__SI 0x3DDF -#define mmUVD_DB_MEM_ADDR_SEL_0__SI 0x3DDD -#define mmUVD_DB_MEM_ADDR_SEL_1__SI 0x3DDE -#define mmUVD_DEBUG_CTRL__SI 0x3BFE -#define mmUVD_DEBUG_SCRATCH__SI 0x3D3F -#define mmUVD_DRM_CMD__SI 0x3DF4 -#define mmUVD_DRM_CNTDAT0__SI 0x3DEC -#define mmUVD_DRM_CNTDAT1__SI 0x3DED -#define mmUVD_DRM_CNTDAT2__SI 0x3DEE -#define mmUVD_DRM_CNTDAT3__SI 0x3DEF -#define mmUVD_DRM_CNTKEY0__SI 0x3DE8 -#define mmUVD_DRM_CNTKEY1__SI 0x3DE9 -#define mmUVD_DRM_CNTKEY2__SI 0x3DEA -#define mmUVD_DRM_CNTKEY3__SI 0x3DEB -#define mmUVD_DRM_KEY0__SI 0x3DE4 -#define mmUVD_DRM_KEY1__SI 0x3DE5 -#define mmUVD_DRM_KEY2__SI 0x3DE6 -#define mmUVD_DRM_KEY3__SI 0x3DE7 -#define mmUVD_DRM_OFFSET__SI 0x3DF3 -#define mmUVD_DRV_FW_MSG__SI 0x3D31 -#define mmUVD_DXVA_BUF_SIZE__SI 0x3BCC -#define mmUVD_ENGINE_CNTL__SI 0x3BC6 -#define mmUVD_FW_BYTECNT__SI 0x3D56 -#define mmUVD_FW_DEBUG_ADDR__SI 0x3D53 -#define mmUVD_FW_DEBUG_DATA__SI 0x3D54 -#define mmUVD_FW_DRV_MSG_ACK__SI 0x3D32 -#define mmUVD_FW_EXP_RESULT0__SI 0x3D4F -#define mmUVD_FW_EXP_RESULT1__SI 0x3D50 -#define mmUVD_FW_EXP_RESULT2__SI 0x3D51 -#define mmUVD_FW_EXP_RESULT3__SI 0x3D52 -#define mmUVD_FW_LENGTH__SI 0x3D48 -#define mmUVD_FW_NONCE0__SI 0x3D4B -#define mmUVD_FW_NONCE1__SI 0x3D4C -#define mmUVD_FW_NONCE2__SI 0x3D4D -#define mmUVD_FW_NONCE3__SI 0x3D4E -#define mmUVD_FW_PERIODIC_CNTL__SI 0x3D49 -#define mmUVD_FW_SELF_RECOVERY_CNTL__SI 0x3D4A -#define mmUVD_FW_START__SI 0x3D47 -#define mmUVD_FW_STATS__SI 0x3D55 -#define mmUVD_FW_STATUS__SI 0x3D57 -#define mmUVD_GPCOM_SYS_CMD__SI 0x3D7F -#define mmUVD_GPCOM_SYS_DATA0__SI 0x3D80 -#define mmUVD_GPCOM_SYS_DATA1__SI 0x3D81 -#define mmUVD_GPCOM_VCPU_CMD__SI 0x3BC3 -#define mmUVD_GPCOM_VCPU_DATA0__SI 0x3BC4 -#define mmUVD_GPCOM_VCPU_DATA1__SI 0x3BC5 -#define mmUVD_GP_SCRATCH0__SI 0x3D34 -#define mmUVD_GP_SCRATCH1__SI 0x3D35 -#define mmUVD_GP_SCRATCH2__SI 0x3D36 -#define mmUVD_GP_SCRATCH3__SI 0x3D37 -#define mmUVD_GP_SCRATCH4__SI 0x3D38 -#define mmUVD_GP_SCRATCH5__SI 0x3D39 -#define mmUVD_GP_SCRATCH6__SI 0x3D3A -#define mmUVD_GP_SCRATCH7__SI 0x3D3B -#define mmUVD_HEIGHT__SI 0x3DFE -#define mmUVD_JOB_DONE__SI 0x3DAE -#define mmUVD_JOB_START__SI 0x3DAD -#define mmUVD_LBSI_ADDR_0__SI 0x3DCA -#define mmUVD_LBSI_ADDR_1__SI 0x3DCB -#define mmUVD_LBSI_BURST_LEN__SI 0x3D5A -#define mmUVD_LBSI_CONFIG__SI 0x3DCE -#define mmUVD_LBSI_CURR_ADDR__SI 0x3D5B -#define mmUVD_LBSI_DRM_FLUSH_CTL_STATUS__SI 0x3D59 -#define mmUVD_LBSI_LEN_0__SI 0x3DCC -#define mmUVD_LBSI_LEN_1__SI 0x3DCD -#define mmUVD_LBSI_PF_BUFF_COUNT__SI 0x3D5C -#define mmUVD_LBSI_RE_WAIT_COUNT__SI 0x3BC7 -#define mmUVD_LMI_ADDR_EXT__SI 0x3D65 -#define mmUVD_LMI_AVG_LAT_CNTR__SI 0x3D24 -#define mmUVD_LMI_AXI_ERR_STATUS__SI 0x3D69 -#define mmUVD_LMI_CRC0__SI 0x3DD4 -#define mmUVD_LMI_CRC1__SI 0x3DD5 -#define mmUVD_LMI_CRC2__SI 0x3DD6 -#define mmUVD_LMI_CRC3__SI 0x3DD7 -#define mmUVD_LMI_CTRL2__SI 0x3D3D -#define mmUVD_LMI_CTRL__SI 0x3D66 -#define mmUVD_LMI_EXT40_ADDR__SI 0x3D26 -#define mmUVD_LMI_LAT_CNTR__SI 0x3D23 -#define mmUVD_LMI_LAT_CTRL__SI 0x3D22 -#define mmUVD_LMI_MC_CREDITS__SI 0x3DE3 -#define mmUVD_LMI_PERFMON_COUNT_HI__SI 0x3D6C -#define mmUVD_LMI_PERFMON_COUNT_LO__SI 0x3D6B -#define mmUVD_LMI_PERFMON_CTRL__SI 0x3D6A -#define mmUVD_LMI_SPH__SI 0x3D27 -#define mmUVD_LMI_STATUS__SI 0x3D67 -#define mmUVD_LMI_SWAP_CNTL__SI 0x3D6D -#define mmUVD_LMI_URGENT_CTRL__SI 0x3D64 -#define mmUVD_LMI_VCPU_VM__SI 0x3D3C -#define mmUVD_LMI_VM_CTRL__SI 0x3D68 -#define mmUVD_MACRO_TILE_CONFIG__SI 0x3DE2 -#define mmUVD_MASTINT_EN__SI 0x3D40 -#define mmUVD_MB_CTL_BUF_BASE__SI 0x3BCA -#define mmUVD_MEM_ADDR_SEL_0__SI 0x3DE0 -#define mmUVD_MEM_ADDR_SEL_1__SI 0x3DE1 -#define mmUVD_MPC_CHROMA_HITPEND__SI 0x3D76 -#define mmUVD_MPC_CHROMA_HIT__SI 0x3D75 -#define mmUVD_MPC_CHROMA_SRCH__SI 0x3D74 -#define mmUVD_MPC_CNTL__SI 0x3D77 -#define mmUVD_MPC_LUMA_HITPEND__SI 0x3D73 -#define mmUVD_MPC_LUMA_HIT__SI 0x3D72 -#define mmUVD_MPC_LUMA_SRCH__SI 0x3D71 -#define mmUVD_MPC_PERF0__SI 0x3D9C -#define mmUVD_MPC_PERF1__SI 0x3D9D -#define mmUVD_MPC_PITCH__SI 0x3D78 -#define mmUVD_MPC_SET_ALU__SI 0x3D7E -#define mmUVD_MPC_SET_MUXA0__SI 0x3D79 -#define mmUVD_MPC_SET_MUXA1__SI 0x3D7A -#define mmUVD_MPC_SET_MUXB0__SI 0x3D7B -#define mmUVD_MPC_SET_MUXB1__SI 0x3D7C -#define mmUVD_MPC_SET_MUX__SI 0x3D7D -#define mmUVD_MPEG2_CTRL__SI 0x3BC9 -#define mmUVD_MPEG2_ERROR__SI 0x3D30 -#define mmUVD_MPRD_INITIAL_XY__SI 0x3BC8 -#define mmUVD_MP_SWAP_CNTL__SI 0x3D6F -#define mmUVD_NO_OP__SI 0x3BFF -#define mmUVD_PICCOUNT__SI 0x3DFF -#define mmUVD_PIC_CTL_BUF_BASE__SI 0x3BCB -#define mmUVD_PITCH__SI 0x3DFC -#define mmUVD_PRIVILEGE_REG_MASK_1__SI 0x3DAC -#define mmUVD_PRIVILEGE_REG_MASK_IDCT__SI 0x3D25 -#define mmUVD_PWR_STATUS__SI 0x3BD6 -#define mmUVD_RBC_BDM_PRE__SI 0x3DF2 -#define mmUVD_RBC_BUF_STATUS__SI 0x3DF0 -#define mmUVD_RBC_CAM_DATA__SI 0x3DC8 -#define mmUVD_RBC_CAM_EN__SI 0x3DC6 -#define mmUVD_RBC_CAM_INDEX__SI 0x3DC7 -#define mmUVD_RBC_CXW_RELEASE__SI 0x3DF9 -#define mmUVD_RBC_IB_BASE__SI 0x3DA1 -#define mmUVD_RBC_IB_PRIVILEGE_REG_CHECK__SI 0x3DAB -#define mmUVD_RBC_IB_SIZE_UPDATE__SI 0x3DF1 -#define mmUVD_RBC_IB_SIZE__SI 0x3DA2 -#define mmUVD_RBC_PRIV_FAULT_REG__SI 0x3D3E -#define mmUVD_RBC_RB_BASE__SI 0x3DA3 -#define mmUVD_RBC_RB_CNTL__SI 0x3DA9 -#define mmUVD_RBC_RB_RPTR_ADDR__SI 0x3DAA -#define mmUVD_RBC_RB_RPTR__SI 0x3DA4 -#define mmUVD_RBC_RB_WPTR_CNTL__SI 0x3DA6 -#define mmUVD_RBC_RB_WPTR__SI 0x3DA5 -#define mmUVD_RBC_READ_REQ_URGENT_CNTL__SI 0x3DA7 -#define mmUVD_RBC_VCPU_ACCESS__SI 0x3DC9 -#define mmUVD_RBC_WPTR_POLL_ADDR__SI 0x3DD9 -#define mmUVD_RBC_WPTR_POLL_CNTL__SI 0x3DD8 -#define mmUVD_RBC_WPTR_STATUS__SI 0x3DA8 -#define mmUVD_RB_ARB_CTRL__SI 0x3D20 -#define mmUVD_REPLAY_OFFSET__SI 0x3DBF -#define mmUVD_RESERVED_0__SI 0x3BCD -#define mmUVD_RESERVED_1__SI 0x3BCE -#define mmUVD_RESERVED_2__SI 0x3BCF -#define mmUVD_RLC_CONTROL__SI 0x0F96 -#define mmUVD_SCRATCH_NP__SI 0x3BFC -#define mmUVD_SEMA_ADDR_HIGH__SI 0x3BC1 -#define mmUVD_SEMA_ADDR_LOW__SI 0x3BC0 -#define mmUVD_SEMA_CMD__SI 0x3BC2 -#define mmUVD_SEMA_CNTL__SI 0x3D00 -#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI 0x3DB3 -#define mmUVD_SEMA_TIMEOUT_STATUS__SI 0x3DB0 -#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI 0x3DB2 -#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI 0x3DB1 -#define mmUVD_SOFT_RESET__SI 0x3DA0 -#define mmUVD_STATUS__SI 0x3DAF -#define mmUVD_STOP_CONTEXT__SI 0x3DBA -#define mmUVD_SYS_INT_ACK__SI 0x3D43 -#define mmUVD_SYS_INT_EN__SI 0x3D41 -#define mmUVD_SYS_INT_STATUS__SI 0x3D42 -#define mmUVD_UDEC_ADR__SI 0x3D6E -#define mmUVD_UDEC_DBW_TILING_CONFIG__SI 0x3BD2 -#define mmUVD_UDEC_DB_TILING_CONFIG__SI 0x3BD1 -#define mmUVD_UDEC_TILING_CONFIG__SI 0x3BD0 -#define mmUVD_UMC_AVP_BLOCK_REQ__SI 0x3DC5 -#define mmUVD_UMC_AVP_CTL_CMD__SI 0x3DC4 -#define mmUVD_UMC_IDCT_BLOCK_REQ__SI 0x3DD1 -#define mmUVD_UMC_IDCT_CTL_CMD__SI 0x3DD0 -#define mmUVD_UMC_UVD_BLOCK_REQ__SI 0x3DF8 -#define mmUVD_UMC_UVD_CTL_CMD__SI 0x3DF7 -#define mmUVD_UVBASE__SI 0x3DFB -#define mmUVD_VCPU_CACHE_OFFSET0__SI 0x3D82 -#define mmUVD_VCPU_CACHE_OFFSET1__SI 0x3D84 -#define mmUVD_VCPU_CACHE_OFFSET2__SI 0x3D86 -#define mmUVD_VCPU_CACHE_OFFSET3__SI 0x3D88 -#define mmUVD_VCPU_CACHE_OFFSET4__SI 0x3D8A -#define mmUVD_VCPU_CACHE_OFFSET5__SI 0x3D8C -#define mmUVD_VCPU_CACHE_OFFSET6__SI 0x3D8E -#define mmUVD_VCPU_CACHE_OFFSET7__SI 0x3D90 -#define mmUVD_VCPU_CACHE_OFFSET8__SI 0x3D92 -#define mmUVD_VCPU_CACHE_SIZE0__SI 0x3D83 -#define mmUVD_VCPU_CACHE_SIZE1__SI 0x3D85 -#define mmUVD_VCPU_CACHE_SIZE2__SI 0x3D87 -#define mmUVD_VCPU_CACHE_SIZE3__SI 0x3D89 -#define mmUVD_VCPU_CACHE_SIZE4__SI 0x3D8B -#define mmUVD_VCPU_CACHE_SIZE5__SI 0x3D8D -#define mmUVD_VCPU_CACHE_SIZE6__SI 0x3D8F -#define mmUVD_VCPU_CACHE_SIZE7__SI 0x3D91 -#define mmUVD_VCPU_CACHE_SIZE8__SI 0x3D93 -#define mmUVD_VCPU_CNTL__SI 0x3D98 -#define mmUVD_VCPU_DBG__SI 0x3D9E -#define mmUVD_VCPU_INT_ACK__SI 0x3D46 -#define mmUVD_VCPU_INT_EN__SI 0x3D44 -#define mmUVD_VCPU_INT_ROUTE__SI 0x3D33 -#define mmUVD_VCPU_INT_STATUS__SI 0x3D45 -#define mmUVD_VCPU_NONCACHE_OFFSET0__SI 0x3D94 -#define mmUVD_VCPU_NONCACHE_OFFSET1__SI 0x3D96 -#define mmUVD_VCPU_NONCACHE_SIZE0__SI 0x3D95 -#define mmUVD_VCPU_NONCACHE_SIZE1__SI 0x3D97 -#define mmUVD_VCPU_PDEBUG_CCOUNT__SI 0x3BDF -#define mmUVD_VCPU_PDEBUG_DATA_H__SI 0x3BDA -#define mmUVD_VCPU_PDEBUG_DATA_L__SI 0x3BD9 -#define mmUVD_VCPU_PDEBUG_EPC__SI 0x3BDB -#define mmUVD_VCPU_PDEBUG_EXCCAUSE__SI 0x3BDD -#define mmUVD_VCPU_PDEBUG_ICOUNT__SI 0x3BDE -#define mmUVD_VCPU_PDEBUG_PSTATUS__SI 0x3BD8 -#define mmUVD_VCPU_PDEBUG_PS__SI 0x3BDC -#define mmUVD_VCPU_PRID__SI 0x3D99 -#define mmUVD_VCPU_TRCE_RD__SI 0x3D9B -#define mmUVD_VCPU_TRCE__SI 0x3D9A -#define mmUVD_WIDTH__SI 0x3DFD -#define mmUVD_YBASE__SI 0x3DFA -#define mmVBLANK_STATUS__SI 0x1AEF -#define mmVCE_CONFIG__CI 0x0F94 -#define mmVGA25_PPLL_CNTL__SI 0x00E7 -#define mmVGA25_PPLL_FB_DIV__SI 0x00DE -#define mmVGA25_PPLL_POST_DIV_SRC__SI 0x00E1 -#define mmVGA25_PPLL_POST_DIV__SI 0x00E2 -#define mmVGA25_PPLL_REF_DIV_SRC__SI 0x00D8 -#define mmVGA25_PPLL_REF_DIV__SI 0x00D9 -#define mmVGA28_PPLL_CNTL__SI 0x00E8 -#define mmVGA28_PPLL_FB_DIV__SI 0x00DF -#define mmVGA28_PPLL_POST_DIV_SRC__SI 0x00E3 -#define mmVGA28_PPLL_POST_DIV__SI 0x00E4 -#define mmVGA28_PPLL_REF_DIV_SRC__SI 0x00DA -#define mmVGA28_PPLL_REF_DIV__SI 0x00DB -#define mmVGA41_PPLL_CNTL__SI 0x00E9 -#define mmVGA41_PPLL_FB_DIV__SI 0x00E0 -#define mmVGA41_PPLL_POST_DIV_SRC__SI 0x00E5 -#define mmVGA41_PPLL_POST_DIV__SI 0x00E6 -#define mmVGA41_PPLL_REF_DIV_SRC__SI 0x00DC -#define mmVGA41_PPLL_REF_DIV__SI 0x00DD -#define mmVGA_CACHE_CONTROL__SI 0x00CB -#define mmVGA_COHERENCY_TIMER_CNTL__SI 0x1519 -#define mmVGA_DEBUG_READBACK_DATA__SI 0x00D7 -#define mmVGA_DEBUG_READBACK_INDEX__SI 0x00D6 -#define mmVGA_DISPBUF1_SURFACE_ADDR__SI 0x00C6 -#define mmVGA_DISPBUF2_SURFACE_ADDR__SI 0x00C8 -#define mmVGA_HDP_CONTROL__SI 0x00CA -#define mmVGA_HW_DEBUG__SI 0x00CF -#define mmVGA_INTERRUPT_CONTROL__SI 0x00D1 -#define mmVGA_INTERRUPT_STATUS__SI 0x00D3 -#define mmVGA_MAIN_CONTROL__SI 0x00D4 -#define mmVGA_MEMORY_BASE_ADDRESS_HIGH__SI 0x00C9 -#define mmVGA_MEMORY_BASE_ADDRESS__SI 0x00C4 -#define mmVGA_MEM_READ_PAGE_ADDR__SI 0x0013 -#define mmVGA_MEM_WRITE_PAGE_ADDR__SI 0x0012 -#define mmVGA_MODE_CONTROL__SI 0x00C2 -#define mmVGA_RENDER_CONTROL__SI 0x00C0 -#define mmVGA_SEQUENCER_RESET_CONTROL__SI 0x00C1 -#define mmVGA_SOURCE_SELECT__SI 0x00FC -#define mmVGA_STATUS_CLEAR__SI 0x00D2 -#define mmVGA_STATUS__SI 0x00D0 -#define mmVGA_SURFACE_PITCH_SELECT__SI 0x00C3 -#define mmVGA_TEST_CONTROL__SI 0x00D5 -#define mmVGA_TEST_DEBUG_DATA__SI 0x00C7 -#define mmVGA_TEST_DEBUG_INDEX__SI 0x00C5 -#define mmVGT_CACHE_INVALIDATION 0x2231 -#define mmVGT_CNTL_STATUS 0x223C -#define mmVGT_DEBUG_CNTL 0x2238 -#define mmVGT_DEBUG_DATA 0x2239 -#define mmVGT_DMA_BASE 0xA1FA -#define mmVGT_DMA_BASE_HI 0xA1F9 -#define mmVGT_DMA_CONTROL__CI__VI 0x2272 -#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222D -#define mmVGT_DMA_INDEX_TYPE 0xA29F -#define mmVGT_DMA_LS_HS_CONFIG__CI__VI 0x2273 -#define mmVGT_DMA_MAX_SIZE 0xA29E -#define mmVGT_DMA_NUM_INSTANCES 0xA2A2 -#define mmVGT_DMA_PRIMITIVE_TYPE__CI__VI 0x2271 -#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222E -#define mmVGT_DMA_SIZE 0xA29D -#define mmVGT_DRAW_INITIATOR 0xA1FC -#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222F -#define mmVGT_ENHANCE 0xA294 -#define mmVGT_ESGS_RING_ITEMSIZE 0xA2AB -#define mmVGT_ESGS_RING_SIZE__CI__VI 0xC240 -#define mmVGT_ESGS_RING_SIZE__SI 0x2232 -#define mmVGT_ES_PER_GS 0xA296 -#define mmVGT_EVENT_ADDRESS_REG 0xA1FE -#define mmVGT_EVENT_INITIATOR 0xA2A4 -#define mmVGT_FIFO_DEPTHS 0x2234 -#define mmVGT_GROUP_DECR 0xA28B -#define mmVGT_GROUP_FIRST_DECR 0xA28A -#define mmVGT_GROUP_PRIM_TYPE 0xA289 -#define mmVGT_GROUP_VECT_0_CNTL 0xA28C -#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E -#define mmVGT_GROUP_VECT_1_CNTL 0xA28D -#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F -#define mmVGT_GSVS_RING_ITEMSIZE 0xA2AC -#define mmVGT_GSVS_RING_OFFSET_1 0xA298 -#define mmVGT_GSVS_RING_OFFSET_2 0xA299 -#define mmVGT_GSVS_RING_OFFSET_3 0xA29A -#define mmVGT_GSVS_RING_SIZE__CI__VI 0xC241 -#define mmVGT_GSVS_RING_SIZE__SI 0x2233 -#define mmVGT_GS_INSTANCE_CNT 0xA2E4 -#define mmVGT_GS_MAX_VERT_OUT 0xA2CE -#define mmVGT_GS_MODE 0xA290 -#define mmVGT_GS_ONCHIP_CNTL__CI__VI 0xA291 -#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B -#define mmVGT_GS_PER_ES 0xA295 -#define mmVGT_GS_PER_VS 0xA297 -#define mmVGT_GS_VERTEX_REUSE 0x2235 -#define mmVGT_GS_VERT_ITEMSIZE 0xA2D7 -#define mmVGT_GS_VERT_ITEMSIZE_1 0xA2D8 -#define mmVGT_GS_VERT_ITEMSIZE_2 0xA2D9 -#define mmVGT_GS_VERT_ITEMSIZE_3 0xA2DA -#define mmVGT_HOS_CNTL 0xA285 -#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286 -#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287 -#define mmVGT_HOS_REUSE_DEPTH 0xA288 -#define mmVGT_HS_OFFCHIP_PARAM__CI__VI 0xC24F -#define mmVGT_HS_OFFCHIP_PARAM__SI 0x226C -#define mmVGT_IMMED_DATA 0xA1FD -#define mmVGT_INDEX_TYPE__CI__VI 0xC243 -#define mmVGT_INDEX_TYPE__SI 0x2257 -#define mmVGT_INDX_OFFSET 0xA102 -#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8 -#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9 -#define mmVGT_LAST_COPY_STATE 0x2230 -#define mmVGT_LS_HS_CONFIG 0xA2D6 -#define mmVGT_MAX_VTX_INDX 0xA100 -#define mmVGT_MC_LAT_CNTL 0x2236 -#define mmVGT_MIN_VTX_INDX 0xA101 -#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xA2A5 -#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103 -#define mmVGT_NUM_INDICES__CI__VI 0xC24C -#define mmVGT_NUM_INDICES__SI 0x225C -#define mmVGT_NUM_INSTANCES__CI__VI 0xC24D -#define mmVGT_NUM_INSTANCES__SI 0x225D -#define mmVGT_OUTPUT_PATH_CNTL 0xA284 -#define mmVGT_OUT_DEALLOC_CNTL 0xA317 -#define mmVGT_PERFCOUNTER0_HI__CI__VI 0xD091 -#define mmVGT_PERFCOUNTER0_HI__SI 0x224D -#define mmVGT_PERFCOUNTER0_LO__CI__VI 0xD090 -#define mmVGT_PERFCOUNTER0_LO__SI 0x224C -#define mmVGT_PERFCOUNTER0_SELECT1__CI__VI 0xD890 -#define mmVGT_PERFCOUNTER0_SELECT__CI__VI 0xD88C -#define mmVGT_PERFCOUNTER0_SELECT__SI 0x2248 -#define mmVGT_PERFCOUNTER1_HI__CI__VI 0xD093 -#define mmVGT_PERFCOUNTER1_HI__SI 0x224F -#define mmVGT_PERFCOUNTER1_LO__CI__VI 0xD092 -#define mmVGT_PERFCOUNTER1_LO__SI 0x224E -#define mmVGT_PERFCOUNTER1_SELECT1__CI__VI 0xD891 -#define mmVGT_PERFCOUNTER1_SELECT__CI__VI 0xD88D -#define mmVGT_PERFCOUNTER1_SELECT__SI 0x2249 -#define mmVGT_PERFCOUNTER2_HI__CI__VI 0xD095 -#define mmVGT_PERFCOUNTER2_HI__SI 0x2251 -#define mmVGT_PERFCOUNTER2_LO__CI__VI 0xD094 -#define mmVGT_PERFCOUNTER2_LO__SI 0x2250 -#define mmVGT_PERFCOUNTER2_SELECT__CI__VI 0xD88E -#define mmVGT_PERFCOUNTER2_SELECT__SI 0x224A -#define mmVGT_PERFCOUNTER3_HI__CI__VI 0xD097 -#define mmVGT_PERFCOUNTER3_HI__SI 0x2253 -#define mmVGT_PERFCOUNTER3_LO__CI__VI 0xD096 -#define mmVGT_PERFCOUNTER3_LO__SI 0x2252 -#define mmVGT_PERFCOUNTER3_SELECT__CI__VI 0xD88F -#define mmVGT_PERFCOUNTER3_SELECT__SI 0x224B -#define mmVGT_PERFCOUNTER_SEID_MASK__CI__VI 0xD894 -#define mmVGT_PERFCOUNTER_SEID_MASK__SI 0x2247 -#define mmVGT_PRIMITIVEID_EN 0xA2A1 -#define mmVGT_PRIMITIVEID_RESET 0xA2A3 -#define mmVGT_PRIMITIVE_TYPE__CI__VI 0xC242 -#define mmVGT_PRIMITIVE_TYPE__SI 0x2256 -#define mmVGT_RESET_DEBUG__CI__VI 0x2232 -#define mmVGT_REUSE_OFF 0xA2AD -#define mmVGT_SHADER_STAGES_EN 0xA2D5 -#define mmVGT_STRMOUT_BUFFER_CONFIG 0xA2E6 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0__CI__VI 0xC244 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0__SI 0x2258 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1__CI__VI 0xC245 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1__SI 0x2259 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2__CI__VI 0xC246 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2__SI 0x225A -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3__CI__VI 0xC247 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3__SI 0x225B -#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7 -#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB -#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF -#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3 -#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4 -#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8 -#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC -#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0 -#define mmVGT_STRMOUT_CONFIG 0xA2E5 -#define mmVGT_STRMOUT_DELAY__CI__VI 0x2233 -#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB -#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA -#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC -#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5 -#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9 -#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD -#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1 -#define mmVGT_SYS_CONFIG 0x2263 -#define mmVGT_TF_MEMORY_BASE__CI__VI 0xC250 -#define mmVGT_TF_MEMORY_BASE__SI 0x226E -#define mmVGT_TF_PARAM 0xA2DB -#define mmVGT_TF_RING_SIZE__CI__VI 0xC24E -#define mmVGT_TF_RING_SIZE__SI 0x2262 -#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316 -#define mmVGT_VS_MAX_WAVE_ID__CI__VI 0x2268 -#define mmVGT_VTX_CNT_EN 0xA2AE -#define mmVGT_VTX_VECT_EJECT_REG 0x222C -#define mmVID_BUFFER_CONTROL__SI 0x02C0 -#define mmVIEWPORT_SIZE__SI 0x1B5D -#define mmVIEWPORT_START__SI 0x1B5C -#define mmVIPH_CH0_ABCNT__SI 0x02EC -#define mmVIPH_CH0_ADDR__SI 0x02E4 -#define mmVIPH_CH0_DATA__SI 0x02E0 -#define mmVIPH_CH0_SBCNT__SI 0x02E8 -#define mmVIPH_CH1_ABCNT__SI 0x02ED -#define mmVIPH_CH1_ADDR__SI 0x02E5 -#define mmVIPH_CH1_DATA__SI 0x02E1 -#define mmVIPH_CH1_SBCNT__SI 0x02E9 -#define mmVIPH_CH2_ABCNT__SI 0x02EE -#define mmVIPH_CH2_ADDR__SI 0x02E6 -#define mmVIPH_CH2_DATA__SI 0x02E2 -#define mmVIPH_CH2_SBCNT__SI 0x02EA -#define mmVIPH_CH3_ABCNT__SI 0x02EF -#define mmVIPH_CH3_ADDR__SI 0x02E7 -#define mmVIPH_CH3_DATA__SI 0x02E3 -#define mmVIPH_CH3_SBCNT__SI 0x02EB -#define mmVIPH_CONTROL__SI 0x02F0 -#define mmVIPH_DMA_CHUNK__SI 0x02F2 -#define mmVIPH_DV_INT__SI 0x02F3 -#define mmVIPH_DV_LAT__SI 0x02F1 -#define mmVIPH_READ_URG__SI 0x02A9 -#define mmVIPH_REG_ADDR__SI 0x02DE -#define mmVIPH_REG_DATA__SI 0x02DF -#define mmVIPH_TIMEOUT_STAT__SI 0x02F4 -#define mmVIPH_WRCOMB_STALL__SI 0x02A7 -#define mmVIPH_WRCOMB_STAT0__SI 0x02A5 -#define mmVIPH_WRCOMB_STAT1__SI 0x02A6 -#define mmVIPPAD_A__SI 0x1959 -#define mmVIPPAD_EN__SI 0x195A -#define mmVIPPAD_MASK__SI 0x1958 -#define mmVIPPAD_PD_DIS__SI 0x1956 -#define mmVIPPAD_RECV__SI 0x1957 -#define mmVIPPAD_STRENGTH__SI 0x195C -#define mmVIPPAD_Y__SI 0x195B -#define mmVIP_DCCIF_CNTL__SI 0x02A3 -#define mmVIP_HW_DEBUG__SI 0x02BE -#define mmVIP_INT__SI 0x02BD -#define mmVIP_MCIF_CNTL__SI 0x02A8 -#define mmVLINE_START_END__SI 0x1AC2 -#define mmVLINE_STATUS__SI 0x1AEE -#define mmVM_CONTEXT0_CNTL 0x0504 -#define mmVM_CONTEXT0_CNTL2 0x050C -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x054F -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x055F -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x0557 -#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x053E -#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x0546 -#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI 0x0538 -#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x0536 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x0510 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x0511 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x0512 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x0513 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x0514 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x0515 -#define mmVM_CONTEXT1_CNTL 0x0505 -#define mmVM_CONTEXT1_CNTL2 0x050D -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x0550 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x0560 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x0558 -#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x053F -#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x0547 -#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI 0x0539 -#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x0537 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x0551 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x0552 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x0553 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x0554 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x0555 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x0556 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x050E -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x050F -#define mmVM_CONTEXTS_DISABLE 0x0535 -#define mmVM_DEBUG 0x056F -#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x0507 -#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0506 -#define mmVM_FAULT_CLIENT_ID 0x054E -#define mmVM_INVALIDATE_REQUEST 0x051E -#define mmVM_INVALIDATE_RESPONSE 0x051F -#define mmVM_L2_BANK_SELECT_MASKA 0x0572 -#define mmVM_L2_BANK_SELECT_MASKB 0x0573 -#define mmVM_L2_CG 0x0570 -#define mmVM_L2_CNTL 0x0500 -#define mmVM_L2_CNTL2 0x0501 -#define mmVM_L2_CNTL3 0x0502 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x0576 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x0575 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x0577 -#define mmVM_L2_PERF_COUNTER_CNTL__SI 0x0567 -#define mmVM_L2_PERF_COUNTER_STATUS__SI 0x0568 -#define mmVM_L2_STATUS 0x0503 -#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x0530 -#define mmVM_PRT_APERTURE0_LOW_ADDR 0x052C -#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x0531 -#define mmVM_PRT_APERTURE1_LOW_ADDR 0x052D -#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x0532 -#define mmVM_PRT_APERTURE2_LOW_ADDR 0x052E -#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x0533 -#define mmVM_PRT_APERTURE3_LOW_ADDR 0x052F -#define mmVM_PRT_CNTL 0x0534 -#define mmVM_SECURE_FAULT_CNTL 0x0508 -#define mmV_COUNTER__SI 0x1AEC -#define mmWAIT_UNTIL_POLL_CNTL__SI 0x2011 -#define mmWAIT_UNTIL_POLL_MASK__SI 0x2012 -#define mmWAIT_UNTIL_POLL_REFDATA__SI 0x2013 -#define mmWAIT_UNTIL__SI 0x2010 -#define mmWD_CNTL_STATUS__CI__VI 0x223F -#define mmWD_DEBUG_CNTL__CI__VI 0x223D -#define mmWD_DEBUG_DATA__CI__VI 0x223E -#define mmWD_ENHANCE__CI__VI 0xA2A0 -#define mmWD_PERFCOUNTER0_HI__CI__VI 0xD081 -#define mmWD_PERFCOUNTER0_LO__CI__VI 0xD080 -#define mmWD_PERFCOUNTER0_SELECT__CI__VI 0xD880 -#define mmWD_PERFCOUNTER1_HI__CI__VI 0xD083 -#define mmWD_PERFCOUNTER1_LO__CI__VI 0xD082 -#define mmWD_PERFCOUNTER1_SELECT__CI__VI 0xD881 -#define mmWD_PERFCOUNTER2_HI__CI__VI 0xD085 -#define mmWD_PERFCOUNTER2_LO__CI__VI 0xD084 -#define mmWD_PERFCOUNTER2_SELECT__CI__VI 0xD882 -#define mmWD_PERFCOUNTER3_HI__CI__VI 0xD087 -#define mmWD_PERFCOUNTER3_LO__CI__VI 0xD086 -#define mmWD_PERFCOUNTER3_SELECT__CI__VI 0xD883 -#define mmXDMA_SLV_FLIP_PENDING__CI 0x046C -#define mmXDMA_SLV_FLIP_PENDING__SI 0x0407 -#define pciADAPTER_ID 0x000B -#define pciADAPTER_ID_W 0x0013 -#define pciADAPTER_ID_W_alt_1 0x0013 -#define pciADAPTER_ID_W_alt_2 0x0013 -#define pciADAPTER_ID_W_alt_3__CI__VI 0x0013 -#define pciADAPTER_ID_alt_1 0x000B -#define pciADAPTER_ID_alt_2 0x000B -#define pciADAPTER_ID_alt_3__CI__VI 0x000B -#define pciBASE_ADDR_1 0x0004 -#define pciBASE_ADDR_1_alt_1 0x0004 -#define pciBASE_ADDR_1_alt_2 0x0004 -#define pciBASE_ADDR_1_alt_3__CI__VI 0x0004 -#define pciBASE_ADDR_2 0x0005 -#define pciBASE_ADDR_2_alt_1 0x0005 -#define pciBASE_ADDR_2_alt_2 0x0005 -#define pciBASE_ADDR_2_alt_3__CI__VI 0x0005 -#define pciBASE_ADDR_3 0x0006 -#define pciBASE_ADDR_3_alt_1 0x0006 -#define pciBASE_ADDR_3_alt_2 0x0006 -#define pciBASE_ADDR_3_alt_3__CI__VI 0x0006 -#define pciBASE_ADDR_4 0x0007 -#define pciBASE_ADDR_4_alt_1 0x0007 -#define pciBASE_ADDR_4_alt_2 0x0007 -#define pciBASE_ADDR_4_alt_3__CI__VI 0x0007 -#define pciBASE_ADDR_5 0x0008 -#define pciBASE_ADDR_5_alt_1 0x0008 -#define pciBASE_ADDR_5_alt_2 0x0008 -#define pciBASE_ADDR_5_alt_3__CI__VI 0x0008 -#define pciBASE_ADDR_6 0x0009 -#define pciBASE_ADDR_6_alt_1 0x0009 -#define pciBASE_ADDR_6_alt_2 0x0009 -#define pciBASE_ADDR_6_alt_3__CI__VI 0x0009 -#define pciBASE_CLASS 0x0002 -#define pciBASE_CLASS_alt_1 0x0002 -#define pciBASE_CLASS_alt_2 0x0002 -#define pciBASE_CLASS_alt_3__CI__VI 0x0002 -#define pciBIST 0x0003 -#define pciBIST_alt_1 0x0003 -#define pciBIST_alt_2 0x0003 -#define pciBIST_alt_3__CI__VI 0x0003 -#define pciCACHE_LINE 0x0003 -#define pciCACHE_LINE_alt_1 0x0003 -#define pciCACHE_LINE_alt_2 0x0003 -#define pciCACHE_LINE_alt_3__CI__VI 0x0003 -#define pciCAP_PTR 0x000D -#define pciCAP_PTR_alt_1 0x000D -#define pciCAP_PTR_alt_2 0x000D -#define pciCAP_PTR_alt_3__CI__VI 0x000D -#define pciCOMMAND 0x0001 -#define pciCOMMAND_alt_1 0x0001 -#define pciCOMMAND_alt_2 0x0001 -#define pciCOMMAND_alt_3__CI__VI 0x0001 -#define pciDEVICE_CAP 0x0017 -#define pciDEVICE_CAP2 0x001F -#define pciDEVICE_CAP2_alt_1 0x001F -#define pciDEVICE_CAP2_alt_2 0x001F -#define pciDEVICE_CAP2_alt_3__CI__VI 0x001F -#define pciDEVICE_CAP_alt_1 0x0017 -#define pciDEVICE_CAP_alt_2 0x0017 -#define pciDEVICE_CAP_alt_3__CI__VI 0x0017 -#define pciDEVICE_CNTL 0x0018 -#define pciDEVICE_CNTL2 0x0020 -#define pciDEVICE_CNTL2_alt_1 0x0020 -#define pciDEVICE_CNTL2_alt_2 0x0020 -#define pciDEVICE_CNTL2_alt_3__CI__VI 0x0020 -#define pciDEVICE_CNTL_alt_1 0x0018 -#define pciDEVICE_CNTL_alt_2 0x0018 -#define pciDEVICE_CNTL_alt_3__CI__VI 0x0018 -#define pciDEVICE_ID 0x0000 -#define pciDEVICE_ID_alt_1 0x0000 -#define pciDEVICE_ID_alt_2 0x0000 -#define pciDEVICE_ID_alt_3__CI__VI 0x0000 -#define pciDEVICE_STATUS 0x0018 -#define pciDEVICE_STATUS2 0x0020 -#define pciDEVICE_STATUS2_alt_1 0x0020 -#define pciDEVICE_STATUS2_alt_2 0x0020 -#define pciDEVICE_STATUS2_alt_3__CI__VI 0x0020 -#define pciDEVICE_STATUS_alt_1 0x0018 -#define pciDEVICE_STATUS_alt_2 0x0018 -#define pciDEVICE_STATUS_alt_3__CI__VI 0x0018 -#define pciHEADER 0x0003 -#define pciHEADER_alt_1 0x0003 -#define pciHEADER_alt_2 0x0003 -#define pciHEADER_alt_3__CI__VI 0x0003 -#define pciINTERRUPT_LINE 0x000F -#define pciINTERRUPT_LINE_alt_1 0x000F -#define pciINTERRUPT_LINE_alt_2 0x000F -#define pciINTERRUPT_LINE_alt_3__CI__VI 0x000F -#define pciINTERRUPT_PIN 0x000F -#define pciINTERRUPT_PIN_alt_1 0x000F -#define pciINTERRUPT_PIN_alt_2 0x000F -#define pciINTERRUPT_PIN_alt_3__CI__VI 0x000F -#define pciLATENCY 0x0003 -#define pciLATENCY_alt_1 0x0003 -#define pciLATENCY_alt_2 0x0003 -#define pciLATENCY_alt_3__CI__VI 0x0003 -#define pciLINK_CAP 0x0019 -#define pciLINK_CAP2 0x0021 -#define pciLINK_CAP2_alt_1 0x0021 -#define pciLINK_CAP2_alt_2 0x0021 -#define pciLINK_CAP2_alt_3__CI__VI 0x0021 -#define pciLINK_CAP_alt_1 0x0019 -#define pciLINK_CAP_alt_2 0x0019 -#define pciLINK_CAP_alt_3__CI__VI 0x0019 -#define pciLINK_CNTL 0x001A -#define pciLINK_CNTL2 0x0022 -#define pciLINK_CNTL2_alt_1 0x0022 -#define pciLINK_CNTL2_alt_2 0x0022 -#define pciLINK_CNTL2_alt_3__CI__VI 0x0022 -#define pciLINK_CNTL_alt_1 0x001A -#define pciLINK_CNTL_alt_2 0x001A -#define pciLINK_CNTL_alt_3__CI__VI 0x001A -#define pciLINK_STATUS 0x001A -#define pciLINK_STATUS2 0x0022 -#define pciLINK_STATUS2_alt_1 0x0022 -#define pciLINK_STATUS2_alt_2 0x0022 -#define pciLINK_STATUS2_alt_3__CI__VI 0x0022 -#define pciLINK_STATUS_alt_1 0x001A -#define pciLINK_STATUS_alt_2 0x001A -#define pciLINK_STATUS_alt_3__CI__VI 0x001A -#define pciMAX_LATENCY 0x000F -#define pciMAX_LATENCY_alt_1 0x000F -#define pciMAX_LATENCY_alt_2 0x000F -#define pciMAX_LATENCY_alt_3__CI__VI 0x000F -#define pciMIN_GRANT 0x000F -#define pciMIN_GRANT_alt_1 0x000F -#define pciMIN_GRANT_alt_2 0x000F -#define pciMIN_GRANT_alt_3__CI__VI 0x000F -#define pciMSI_CAP_LIST 0x0028 -#define pciMSI_CAP_LIST_alt_1 0x0028 -#define pciMSI_CAP_LIST_alt_2 0x0028 -#define pciMSI_CAP_LIST_alt_3__CI__VI 0x0028 -#define pciMSI_MSG_ADDR_HI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_1 0x002A -#define pciMSI_MSG_ADDR_HI_alt_2 0x002A -#define pciMSI_MSG_ADDR_HI_alt_3__CI__VI 0x002A -#define pciMSI_MSG_ADDR_LO 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_1 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_2 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_3__CI__VI 0x0029 -#define pciMSI_MSG_CNTL 0x0028 -#define pciMSI_MSG_CNTL_alt_1 0x0028 -#define pciMSI_MSG_CNTL_alt_2 0x0028 -#define pciMSI_MSG_CNTL_alt_3__CI__VI 0x0028 -#define pciMSI_MSG_DATA 0x002A -#define pciMSI_MSG_DATA_64 0x002B -#define pciMSI_MSG_DATA_64_alt_1 0x002B -#define pciMSI_MSG_DATA_64_alt_2 0x002B -#define pciMSI_MSG_DATA_64_alt_3__CI__VI 0x002B -#define pciMSI_MSG_DATA_alt_1 0x002A -#define pciMSI_MSG_DATA_alt_2 0x002A -#define pciMSI_MSG_DATA_alt_3__CI__VI 0x002A -#define pciPCIE_ACS_CAP__CI__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_1__CI__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_2__CI__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_3__CI__VI 0x00A9 -#define pciPCIE_ACS_CNTL__CI__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_1__CI__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_2__CI__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_3__CI__VI 0x00A9 -#define pciPCIE_ACS_ENH_CAP_LIST__CI__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_1__CI__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_2__CI__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_3__CI__VI 0x00A8 -#define pciPCIE_ADV_ERR_CAP_CNTL 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_1 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_2 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_3__CI__VI 0x005A -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_1 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_2 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_3__CI__VI 0x0054 -#define pciPCIE_ATS_CAP__CI__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_1__CI__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_2__CI__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_3__CI__VI 0x00AD -#define pciPCIE_ATS_CNTL__CI__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_1__CI__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_2__CI__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_3__CI__VI 0x00AD -#define pciPCIE_ATS_ENH_CAP_LIST__CI__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_1__CI__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_2__CI__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_3__CI__VI 0x00AC -#define pciPCIE_BAR1_CAP__CI__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_1__CI__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_2__CI__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_3__CI__VI 0x0081 -#define pciPCIE_BAR1_CNTL__CI__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_1__CI__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_2__CI__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_3__CI__VI 0x0082 -#define pciPCIE_BAR2_CAP__CI__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_1__CI__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_2__CI__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_3__CI__VI 0x0083 -#define pciPCIE_BAR2_CNTL__CI__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_1__CI__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_2__CI__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_3__CI__VI 0x0084 -#define pciPCIE_BAR3_CAP__CI__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_1__CI__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_2__CI__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_3__CI__VI 0x0085 -#define pciPCIE_BAR3_CNTL__CI__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_1__CI__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_2__CI__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_3__CI__VI 0x0086 -#define pciPCIE_BAR4_CAP__CI__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_1__CI__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_2__CI__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_3__CI__VI 0x0087 -#define pciPCIE_BAR4_CNTL__CI__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_1__CI__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_2__CI__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_3__CI__VI 0x0088 -#define pciPCIE_BAR5_CAP__CI__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_1__CI__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_2__CI__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_3__CI__VI 0x0089 -#define pciPCIE_BAR5_CNTL__CI__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_1__CI__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_2__CI__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_3__CI__VI 0x008A -#define pciPCIE_BAR6_CAP__CI__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_1__CI__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_2__CI__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_3__CI__VI 0x008B -#define pciPCIE_BAR6_CNTL__CI__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_1__CI__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_2__CI__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_3__CI__VI 0x008C -#define pciPCIE_BAR_ENH_CAP_LIST__CI__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_1__CI__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_2__CI__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_3__CI__VI 0x0080 -#define pciPCIE_CAC_DEVICE_CORRELATION__SI 0x0065 -#define pciPCIE_CAC_DEVICE_CORRELATION_alt_1__SI 0x0065 -#define pciPCIE_CAC_DEVICE_CORRELATION_alt_2__SI 0x0065 -#define pciPCIE_CAC_ENH_CAP_LIST__SI 0x0064 -#define pciPCIE_CAC_ENH_CAP_LIST_alt_1__SI 0x0064 -#define pciPCIE_CAC_ENH_CAP_LIST_alt_2__SI 0x0064 -#define pciPCIE_CAP 0x0016 -#define pciPCIE_CAP_LIST 0x0016 -#define pciPCIE_CAP_LIST_alt_1 0x0016 -#define pciPCIE_CAP_LIST_alt_2 0x0016 -#define pciPCIE_CAP_LIST_alt_3__CI__VI 0x0016 -#define pciPCIE_CAP_alt_1 0x0016 -#define pciPCIE_CAP_alt_2 0x0016 -#define pciPCIE_CAP_alt_3__CI__VI 0x0016 -#define pciPCIE_CORR_ERR_MASK 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_1 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_2 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_3__CI__VI 0x0059 -#define pciPCIE_CORR_ERR_STATUS 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_1 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_2 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_3__CI__VI 0x0058 -#define pciPCIE_DEV_SERIAL_NUM_DW1 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_1 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_2 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_3__CI__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW2 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_1 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_2 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_3__CI__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_1 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_2 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_3__CI__VI 0x0050 -#define pciPCIE_DPA_CAP__CI__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_1__CI__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_2__CI__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_3__CI__VI 0x0095 -#define pciPCIE_DPA_CNTL__CI__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_1__CI__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_2__CI__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_3__CI__VI 0x0097 -#define pciPCIE_DPA_ENH_CAP_LIST__CI__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_1__CI__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_2__CI__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_3__CI__VI 0x0094 -#define pciPCIE_DPA_LATENCY_INDICATOR__CI__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_1__CI__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_2__CI__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_3__CI__VI 0x0096 -#define pciPCIE_DPA_STATUS__CI__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_1__CI__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_2__CI__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_3__CI__VI 0x0097 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_1__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_2__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_3__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_1__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_2__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_3__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_1__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_2__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_3__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_1__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_2__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_3__CI__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_1__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_2__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_3__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_1__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_2__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_3__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_1__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_2__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_3__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_1__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_2__CI__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_3__CI__VI 0x0099 -#define pciPCIE_HDR_LOG0 0x005B -#define pciPCIE_HDR_LOG0_alt_1 0x005B -#define pciPCIE_HDR_LOG0_alt_2 0x005B -#define pciPCIE_HDR_LOG0_alt_3__CI__VI 0x005B -#define pciPCIE_HDR_LOG1 0x005C -#define pciPCIE_HDR_LOG1_alt_1 0x005C -#define pciPCIE_HDR_LOG1_alt_2 0x005C -#define pciPCIE_HDR_LOG1_alt_3__CI__VI 0x005C -#define pciPCIE_HDR_LOG2 0x005D -#define pciPCIE_HDR_LOG2_alt_1 0x005D -#define pciPCIE_HDR_LOG2_alt_2 0x005D -#define pciPCIE_HDR_LOG2_alt_3__CI__VI 0x005D -#define pciPCIE_HDR_LOG3 0x005E -#define pciPCIE_HDR_LOG3_alt_1 0x005E -#define pciPCIE_HDR_LOG3_alt_2 0x005E -#define pciPCIE_HDR_LOG3_alt_3__CI__VI 0x005E -#define pciPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_1__CI__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_2__CI__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_3__CI__VI 0x009F -#define pciPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A4 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A5 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A6 -#define pciPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_1__CI__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_2__CI__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_3__CI__VI 0x009F -#define pciPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A0 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A1 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A2 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_1__CI__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_2__CI__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_3__CI__VI 0x00A3 -#define pciPCIE_LANE_ERROR_STATUS__CI__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_1__CI__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_2__CI__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_3__CI__VI 0x009E -#define pciPCIE_LINK_CNTL3__CI__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_1__CI__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_2__CI__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_3__CI__VI 0x009D -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_1__CI__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_2__CI__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_3__CI__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_1__CI__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_2__CI__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_3__CI__VI 0x00B2 -#define pciPCIE_PAGE_REQ_CNTL__CI__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_1__CI__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_2__CI__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_3__CI__VI 0x00B1 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_1__CI__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_2__CI__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_3__CI__VI 0x00B0 -#define pciPCIE_PAGE_REQ_STATUS__CI__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_1__CI__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_2__CI__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_3__CI__VI 0x00B1 -#define pciPCIE_PASID_CAP__CI__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_1__CI__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_2__CI__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_3__CI__VI 0x00B5 -#define pciPCIE_PASID_CNTL__CI__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_1__CI__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_2__CI__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_3__CI__VI 0x00B5 -#define pciPCIE_PASID_ENH_CAP_LIST__CI__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_1__CI__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_2__CI__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_3__CI__VI 0x00B4 -#define pciPCIE_PORT_VC_CAP_REG1 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_1 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_2 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_3__CI__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG2 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_1 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_2 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_3__CI__VI 0x0046 -#define pciPCIE_PORT_VC_CNTL 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_1 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_2 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_3__CI__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_1 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_2 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_3__CI__VI 0x0047 -#define pciPCIE_PWR_BUDGET_CAP__CI__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_1__CI__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_2__CI__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_3__CI__VI 0x0093 -#define pciPCIE_PWR_BUDGET_DATA_SELECT__CI__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_1__CI__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_2__CI__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_3__CI__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA__CI__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_1__CI__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_2__CI__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_3__CI__VI 0x0092 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_1__CI__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_2__CI__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_3__CI__VI 0x0090 -#define pciPCIE_SECONDARY_ENH_CAP_LIST__CI__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_1__CI__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_2__CI__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_3__CI__VI 0x009C -#define pciPCIE_TLP_PREFIX_LOG0__CI__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_1__CI__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_2__CI__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_3__CI__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG1__CI__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_1__CI__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_2__CI__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_3__CI__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG2__CI__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_1__CI__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_2__CI__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_3__CI__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG3__CI__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_1__CI__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_2__CI__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_3__CI__VI 0x0065 -#define pciPCIE_TRUSTED_BASE_CLASS__SI 0x0000 -#define pciPCIE_TRUSTED_BASE_CLASS_alt_1__SI 0x0000 -#define pciPCIE_TRUSTED_BASE_CLASS_alt_2__SI 0x0000 -#define pciPCIE_TRUSTED_CAC_CAP_LIST__SI 0x0004 -#define pciPCIE_TRUSTED_CAC_CAP_LIST_alt_1__SI 0x0004 -#define pciPCIE_TRUSTED_CAC_CAP_LIST_alt_2__SI 0x0004 -#define pciPCIE_TRUSTED_CAC_DEVICE_CORRELATION__SI 0x0005 -#define pciPCIE_TRUSTED_CAC_DEVICE_CORRELATION_alt_1__SI 0x0005 -#define pciPCIE_TRUSTED_CAC_DEVICE_CORRELATION_alt_2__SI 0x0005 -#define pciPCIE_TRUSTED_FIRST_CAP_OFFSET__SI 0x0001 -#define pciPCIE_TRUSTED_FIRST_CAP_OFFSET_alt_1__SI 0x0001 -#define pciPCIE_TRUSTED_FIRST_CAP_OFFSET_alt_2__SI 0x0001 -#define pciPCIE_TRUSTED_PROG_INTERFACE__SI 0x0000 -#define pciPCIE_TRUSTED_PROG_INTERFACE_alt_1__SI 0x0000 -#define pciPCIE_TRUSTED_PROG_INTERFACE_alt_2__SI 0x0000 -#define pciPCIE_TRUSTED_SUB_CLASS__SI 0x0000 -#define pciPCIE_TRUSTED_SUB_CLASS_alt_1__SI 0x0000 -#define pciPCIE_TRUSTED_SUB_CLASS_alt_2__SI 0x0000 -#define pciPCIE_UNCORR_ERR_MASK 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_1 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_2 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_3__CI__VI 0x0056 -#define pciPCIE_UNCORR_ERR_SEVERITY 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_1 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_2 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_3__CI__VI 0x0057 -#define pciPCIE_UNCORR_ERR_STATUS 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_1 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_2 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_3__CI__VI 0x0055 -#define pciPCIE_VC0_RESOURCE_CAP 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_1 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_2 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_3__CI__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CNTL 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_1 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_2 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_3__CI__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_STATUS 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_1 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_2 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_3__CI__VI 0x004A -#define pciPCIE_VC1_RESOURCE_CAP 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_1 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_2 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_3__CI__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CNTL 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_1 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_2 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_3__CI__VI 0x004C -#define pciPCIE_VC1_RESOURCE_STATUS 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_1 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_2 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_3__CI__VI 0x004D -#define pciPCIE_VC_ENH_CAP_LIST 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_1 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_2 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_3__CI__VI 0x0044 -#define pciPCIE_VENDOR_SPECIFIC1 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_1 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_2 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_3__CI__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC2 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_1 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_2 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_3__CI__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_1 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_2 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_3__CI__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_HDR 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_1 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_2 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_3__CI__VI 0x0041 -#define pciPMI_CAP 0x0014 -#define pciPMI_CAP_LIST 0x0014 -#define pciPMI_CAP_LIST_alt_1 0x0014 -#define pciPMI_CAP_LIST_alt_2 0x0014 -#define pciPMI_CAP_LIST_alt_3__CI__VI 0x0014 -#define pciPMI_CAP_alt_1 0x0014 -#define pciPMI_CAP_alt_2 0x0014 -#define pciPMI_CAP_alt_3__CI__VI 0x0014 -#define pciPMI_STATUS_CNTL 0x0015 -#define pciPMI_STATUS_CNTL_alt_1 0x0015 -#define pciPMI_STATUS_CNTL_alt_2 0x0015 -#define pciPMI_STATUS_CNTL_alt_3__CI__VI 0x0015 -#define pciPROG_INTERFACE 0x0002 -#define pciPROG_INTERFACE_alt_1 0x0002 -#define pciPROG_INTERFACE_alt_2 0x0002 -#define pciPROG_INTERFACE_alt_3__CI__VI 0x0002 -#define pciREVISION_ID 0x0002 -#define pciREVISION_ID_alt_1 0x0002 -#define pciREVISION_ID_alt_2 0x0002 -#define pciREVISION_ID_alt_3__CI__VI 0x0002 -#define pciROM_BASE_ADDR 0x000C -#define pciROM_BASE_ADDR_alt_1 0x000C -#define pciROM_BASE_ADDR_alt_2 0x000C -#define pciROM_BASE_ADDR_alt_3__CI__VI 0x000C -#define pciSTATUS 0x0001 -#define pciSTATUS_alt_1 0x0001 -#define pciSTATUS_alt_2 0x0001 -#define pciSTATUS_alt_3__CI__VI 0x0001 -#define pciSUB_CLASS 0x0002 -#define pciSUB_CLASS_alt_1 0x0002 -#define pciSUB_CLASS_alt_2 0x0002 -#define pciSUB_CLASS_alt_3__CI__VI 0x0002 -#define pciVENDOR_CAP_LIST__CI__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_1__CI__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_2__CI__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_3__CI__VI 0x0012 -#define pciVENDOR_ID 0x0000 -#define pciVENDOR_ID_alt_1 0x0000 -#define pciVENDOR_ID_alt_2 0x0000 -#define pciVENDOR_ID_alt_3__CI__VI 0x0000 - -// Merged Defines - -#define cfgADAPTER_ID_W_alt_10__VI 0x0013 -#define cfgADAPTER_ID_W_alt_11__VI 0x0013 -#define cfgADAPTER_ID_W_alt_12__VI 0x0013 -#define cfgADAPTER_ID_W_alt_13__VI 0x0013 -#define cfgADAPTER_ID_W_alt_14__VI 0x0013 -#define cfgADAPTER_ID_W_alt_15__VI 0x0013 -#define cfgADAPTER_ID_W_alt_16__VI 0x0013 -#define cfgADAPTER_ID_W_alt_17__VI 0x0013 -#define cfgADAPTER_ID_W_alt_18__VI 0x0013 -#define cfgADAPTER_ID_W_alt_4__VI 0x0013 -#define cfgADAPTER_ID_W_alt_5__VI 0x0013 -#define cfgADAPTER_ID_W_alt_6__VI 0x0013 -#define cfgADAPTER_ID_W_alt_7__VI 0x0013 -#define cfgADAPTER_ID_W_alt_8__VI 0x0013 -#define cfgADAPTER_ID_W_alt_9__VI 0x0013 -#define cfgADAPTER_ID_alt_10__VI 0x000B -#define cfgADAPTER_ID_alt_11__VI 0x000B -#define cfgADAPTER_ID_alt_12__VI 0x000B -#define cfgADAPTER_ID_alt_13__VI 0x000B -#define cfgADAPTER_ID_alt_14__VI 0x000B -#define cfgADAPTER_ID_alt_15__VI 0x000B -#define cfgADAPTER_ID_alt_16__VI 0x000B -#define cfgADAPTER_ID_alt_17__VI 0x000B -#define cfgADAPTER_ID_alt_18__VI 0x000B -#define cfgADAPTER_ID_alt_4__VI 0x000B -#define cfgADAPTER_ID_alt_5__VI 0x000B -#define cfgADAPTER_ID_alt_6__VI 0x000B -#define cfgADAPTER_ID_alt_7__VI 0x000B -#define cfgADAPTER_ID_alt_8__VI 0x000B -#define cfgADAPTER_ID_alt_9__VI 0x000B -#define cfgBASE_ADDR_1_alt_10__VI 0x0004 -#define cfgBASE_ADDR_1_alt_11__VI 0x0004 -#define cfgBASE_ADDR_1_alt_12__VI 0x0004 -#define cfgBASE_ADDR_1_alt_13__VI 0x0004 -#define cfgBASE_ADDR_1_alt_14__VI 0x0004 -#define cfgBASE_ADDR_1_alt_15__VI 0x0004 -#define cfgBASE_ADDR_1_alt_16__VI 0x0004 -#define cfgBASE_ADDR_1_alt_17__VI 0x0004 -#define cfgBASE_ADDR_1_alt_18__VI 0x0004 -#define cfgBASE_ADDR_1_alt_4__VI 0x0004 -#define cfgBASE_ADDR_1_alt_5__VI 0x0004 -#define cfgBASE_ADDR_1_alt_6__VI 0x0004 -#define cfgBASE_ADDR_1_alt_7__VI 0x0004 -#define cfgBASE_ADDR_1_alt_8__VI 0x0004 -#define cfgBASE_ADDR_1_alt_9__VI 0x0004 -#define cfgBASE_ADDR_2_alt_10__VI 0x0005 -#define cfgBASE_ADDR_2_alt_11__VI 0x0005 -#define cfgBASE_ADDR_2_alt_12__VI 0x0005 -#define cfgBASE_ADDR_2_alt_13__VI 0x0005 -#define cfgBASE_ADDR_2_alt_14__VI 0x0005 -#define cfgBASE_ADDR_2_alt_15__VI 0x0005 -#define cfgBASE_ADDR_2_alt_16__VI 0x0005 -#define cfgBASE_ADDR_2_alt_17__VI 0x0005 -#define cfgBASE_ADDR_2_alt_18__VI 0x0005 -#define cfgBASE_ADDR_2_alt_4__VI 0x0005 -#define cfgBASE_ADDR_2_alt_5__VI 0x0005 -#define cfgBASE_ADDR_2_alt_6__VI 0x0005 -#define cfgBASE_ADDR_2_alt_7__VI 0x0005 -#define cfgBASE_ADDR_2_alt_8__VI 0x0005 -#define cfgBASE_ADDR_2_alt_9__VI 0x0005 -#define cfgBASE_ADDR_3_alt_10__VI 0x0006 -#define cfgBASE_ADDR_3_alt_11__VI 0x0006 -#define cfgBASE_ADDR_3_alt_12__VI 0x0006 -#define cfgBASE_ADDR_3_alt_13__VI 0x0006 -#define cfgBASE_ADDR_3_alt_14__VI 0x0006 -#define cfgBASE_ADDR_3_alt_15__VI 0x0006 -#define cfgBASE_ADDR_3_alt_16__VI 0x0006 -#define cfgBASE_ADDR_3_alt_17__VI 0x0006 -#define cfgBASE_ADDR_3_alt_18__VI 0x0006 -#define cfgBASE_ADDR_3_alt_4__VI 0x0006 -#define cfgBASE_ADDR_3_alt_5__VI 0x0006 -#define cfgBASE_ADDR_3_alt_6__VI 0x0006 -#define cfgBASE_ADDR_3_alt_7__VI 0x0006 -#define cfgBASE_ADDR_3_alt_8__VI 0x0006 -#define cfgBASE_ADDR_3_alt_9__VI 0x0006 -#define cfgBASE_ADDR_4_alt_10__VI 0x0007 -#define cfgBASE_ADDR_4_alt_11__VI 0x0007 -#define cfgBASE_ADDR_4_alt_12__VI 0x0007 -#define cfgBASE_ADDR_4_alt_13__VI 0x0007 -#define cfgBASE_ADDR_4_alt_14__VI 0x0007 -#define cfgBASE_ADDR_4_alt_15__VI 0x0007 -#define cfgBASE_ADDR_4_alt_16__VI 0x0007 -#define cfgBASE_ADDR_4_alt_17__VI 0x0007 -#define cfgBASE_ADDR_4_alt_18__VI 0x0007 -#define cfgBASE_ADDR_4_alt_4__VI 0x0007 -#define cfgBASE_ADDR_4_alt_5__VI 0x0007 -#define cfgBASE_ADDR_4_alt_6__VI 0x0007 -#define cfgBASE_ADDR_4_alt_7__VI 0x0007 -#define cfgBASE_ADDR_4_alt_8__VI 0x0007 -#define cfgBASE_ADDR_4_alt_9__VI 0x0007 -#define cfgBASE_ADDR_5_alt_10__VI 0x0008 -#define cfgBASE_ADDR_5_alt_11__VI 0x0008 -#define cfgBASE_ADDR_5_alt_12__VI 0x0008 -#define cfgBASE_ADDR_5_alt_13__VI 0x0008 -#define cfgBASE_ADDR_5_alt_14__VI 0x0008 -#define cfgBASE_ADDR_5_alt_15__VI 0x0008 -#define cfgBASE_ADDR_5_alt_16__VI 0x0008 -#define cfgBASE_ADDR_5_alt_17__VI 0x0008 -#define cfgBASE_ADDR_5_alt_18__VI 0x0008 -#define cfgBASE_ADDR_5_alt_4__VI 0x0008 -#define cfgBASE_ADDR_5_alt_5__VI 0x0008 -#define cfgBASE_ADDR_5_alt_6__VI 0x0008 -#define cfgBASE_ADDR_5_alt_7__VI 0x0008 -#define cfgBASE_ADDR_5_alt_8__VI 0x0008 -#define cfgBASE_ADDR_5_alt_9__VI 0x0008 -#define cfgBASE_ADDR_6_alt_10__VI 0x0009 -#define cfgBASE_ADDR_6_alt_11__VI 0x0009 -#define cfgBASE_ADDR_6_alt_12__VI 0x0009 -#define cfgBASE_ADDR_6_alt_13__VI 0x0009 -#define cfgBASE_ADDR_6_alt_14__VI 0x0009 -#define cfgBASE_ADDR_6_alt_15__VI 0x0009 -#define cfgBASE_ADDR_6_alt_16__VI 0x0009 -#define cfgBASE_ADDR_6_alt_17__VI 0x0009 -#define cfgBASE_ADDR_6_alt_18__VI 0x0009 -#define cfgBASE_ADDR_6_alt_4__VI 0x0009 -#define cfgBASE_ADDR_6_alt_5__VI 0x0009 -#define cfgBASE_ADDR_6_alt_6__VI 0x0009 -#define cfgBASE_ADDR_6_alt_7__VI 0x0009 -#define cfgBASE_ADDR_6_alt_8__VI 0x0009 -#define cfgBASE_ADDR_6_alt_9__VI 0x0009 -#define cfgBASE_CLASS_alt_10__VI 0x0002 -#define cfgBASE_CLASS_alt_11__VI 0x0002 -#define cfgBASE_CLASS_alt_12__VI 0x0002 -#define cfgBASE_CLASS_alt_13__VI 0x0002 -#define cfgBASE_CLASS_alt_14__VI 0x0002 -#define cfgBASE_CLASS_alt_15__VI 0x0002 -#define cfgBASE_CLASS_alt_16__VI 0x0002 -#define cfgBASE_CLASS_alt_17__VI 0x0002 -#define cfgBASE_CLASS_alt_18__VI 0x0002 -#define cfgBASE_CLASS_alt_4__VI 0x0002 -#define cfgBASE_CLASS_alt_5__VI 0x0002 -#define cfgBASE_CLASS_alt_6__VI 0x0002 -#define cfgBASE_CLASS_alt_7__VI 0x0002 -#define cfgBASE_CLASS_alt_8__VI 0x0002 -#define cfgBASE_CLASS_alt_9__VI 0x0002 -#define cfgBIST_alt_10__VI 0x0003 -#define cfgBIST_alt_11__VI 0x0003 -#define cfgBIST_alt_12__VI 0x0003 -#define cfgBIST_alt_13__VI 0x0003 -#define cfgBIST_alt_14__VI 0x0003 -#define cfgBIST_alt_15__VI 0x0003 -#define cfgBIST_alt_16__VI 0x0003 -#define cfgBIST_alt_17__VI 0x0003 -#define cfgBIST_alt_18__VI 0x0003 -#define cfgBIST_alt_4__VI 0x0003 -#define cfgBIST_alt_5__VI 0x0003 -#define cfgBIST_alt_6__VI 0x0003 -#define cfgBIST_alt_7__VI 0x0003 -#define cfgBIST_alt_8__VI 0x0003 -#define cfgBIST_alt_9__VI 0x0003 -#define cfgCACHE_LINE_alt_10__VI 0x0003 -#define cfgCACHE_LINE_alt_11__VI 0x0003 -#define cfgCACHE_LINE_alt_12__VI 0x0003 -#define cfgCACHE_LINE_alt_13__VI 0x0003 -#define cfgCACHE_LINE_alt_14__VI 0x0003 -#define cfgCACHE_LINE_alt_15__VI 0x0003 -#define cfgCACHE_LINE_alt_16__VI 0x0003 -#define cfgCACHE_LINE_alt_17__VI 0x0003 -#define cfgCACHE_LINE_alt_18__VI 0x0003 -#define cfgCACHE_LINE_alt_4__VI 0x0003 -#define cfgCACHE_LINE_alt_5__VI 0x0003 -#define cfgCACHE_LINE_alt_6__VI 0x0003 -#define cfgCACHE_LINE_alt_7__VI 0x0003 -#define cfgCACHE_LINE_alt_8__VI 0x0003 -#define cfgCACHE_LINE_alt_9__VI 0x0003 -#define cfgCAP_PTR_alt_10__VI 0x000D -#define cfgCAP_PTR_alt_11__VI 0x000D -#define cfgCAP_PTR_alt_12__VI 0x000D -#define cfgCAP_PTR_alt_13__VI 0x000D -#define cfgCAP_PTR_alt_14__VI 0x000D -#define cfgCAP_PTR_alt_15__VI 0x000D -#define cfgCAP_PTR_alt_16__VI 0x000D -#define cfgCAP_PTR_alt_17__VI 0x000D -#define cfgCAP_PTR_alt_18__VI 0x000D -#define cfgCAP_PTR_alt_4__VI 0x000D -#define cfgCAP_PTR_alt_5__VI 0x000D -#define cfgCAP_PTR_alt_6__VI 0x000D -#define cfgCAP_PTR_alt_7__VI 0x000D -#define cfgCAP_PTR_alt_8__VI 0x000D -#define cfgCAP_PTR_alt_9__VI 0x000D -#define cfgCOMMAND_alt_10__VI 0x0001 -#define cfgCOMMAND_alt_11__VI 0x0001 -#define cfgCOMMAND_alt_12__VI 0x0001 -#define cfgCOMMAND_alt_13__VI 0x0001 -#define cfgCOMMAND_alt_14__VI 0x0001 -#define cfgCOMMAND_alt_15__VI 0x0001 -#define cfgCOMMAND_alt_16__VI 0x0001 -#define cfgCOMMAND_alt_17__VI 0x0001 -#define cfgCOMMAND_alt_18__VI 0x0001 -#define cfgCOMMAND_alt_4__VI 0x0001 -#define cfgCOMMAND_alt_5__VI 0x0001 -#define cfgCOMMAND_alt_6__VI 0x0001 -#define cfgCOMMAND_alt_7__VI 0x0001 -#define cfgCOMMAND_alt_8__VI 0x0001 -#define cfgCOMMAND_alt_9__VI 0x0001 -#define cfgDEVICE_CAP2_alt_10__VI 0x001F -#define cfgDEVICE_CAP2_alt_11__VI 0x001F -#define cfgDEVICE_CAP2_alt_12__VI 0x001F -#define cfgDEVICE_CAP2_alt_13__VI 0x001F -#define cfgDEVICE_CAP2_alt_14__VI 0x001F -#define cfgDEVICE_CAP2_alt_15__VI 0x001F -#define cfgDEVICE_CAP2_alt_16__VI 0x001F -#define cfgDEVICE_CAP2_alt_17__VI 0x001F -#define cfgDEVICE_CAP2_alt_18__VI 0x001F -#define cfgDEVICE_CAP2_alt_4__VI 0x001F -#define cfgDEVICE_CAP2_alt_5__VI 0x001F -#define cfgDEVICE_CAP2_alt_6__VI 0x001F -#define cfgDEVICE_CAP2_alt_7__VI 0x001F -#define cfgDEVICE_CAP2_alt_8__VI 0x001F -#define cfgDEVICE_CAP2_alt_9__VI 0x001F -#define cfgDEVICE_CAP_alt_10__VI 0x0017 -#define cfgDEVICE_CAP_alt_11__VI 0x0017 -#define cfgDEVICE_CAP_alt_12__VI 0x0017 -#define cfgDEVICE_CAP_alt_13__VI 0x0017 -#define cfgDEVICE_CAP_alt_14__VI 0x0017 -#define cfgDEVICE_CAP_alt_15__VI 0x0017 -#define cfgDEVICE_CAP_alt_16__VI 0x0017 -#define cfgDEVICE_CAP_alt_17__VI 0x0017 -#define cfgDEVICE_CAP_alt_18__VI 0x0017 -#define cfgDEVICE_CAP_alt_4__VI 0x0017 -#define cfgDEVICE_CAP_alt_5__VI 0x0017 -#define cfgDEVICE_CAP_alt_6__VI 0x0017 -#define cfgDEVICE_CAP_alt_7__VI 0x0017 -#define cfgDEVICE_CAP_alt_8__VI 0x0017 -#define cfgDEVICE_CAP_alt_9__VI 0x0017 -#define cfgDEVICE_CNTL2_alt_10__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_11__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_12__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_13__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_14__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_15__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_16__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_17__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_18__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_4__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_5__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_6__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_7__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_8__VI 0x0020 -#define cfgDEVICE_CNTL2_alt_9__VI 0x0020 -#define cfgDEVICE_CNTL_alt_10__VI 0x0018 -#define cfgDEVICE_CNTL_alt_11__VI 0x0018 -#define cfgDEVICE_CNTL_alt_12__VI 0x0018 -#define cfgDEVICE_CNTL_alt_13__VI 0x0018 -#define cfgDEVICE_CNTL_alt_14__VI 0x0018 -#define cfgDEVICE_CNTL_alt_15__VI 0x0018 -#define cfgDEVICE_CNTL_alt_16__VI 0x0018 -#define cfgDEVICE_CNTL_alt_17__VI 0x0018 -#define cfgDEVICE_CNTL_alt_18__VI 0x0018 -#define cfgDEVICE_CNTL_alt_4__VI 0x0018 -#define cfgDEVICE_CNTL_alt_5__VI 0x0018 -#define cfgDEVICE_CNTL_alt_6__VI 0x0018 -#define cfgDEVICE_CNTL_alt_7__VI 0x0018 -#define cfgDEVICE_CNTL_alt_8__VI 0x0018 -#define cfgDEVICE_CNTL_alt_9__VI 0x0018 -#define cfgDEVICE_ID_alt_10__VI 0x0000 -#define cfgDEVICE_ID_alt_11__VI 0x0000 -#define cfgDEVICE_ID_alt_12__VI 0x0000 -#define cfgDEVICE_ID_alt_13__VI 0x0000 -#define cfgDEVICE_ID_alt_14__VI 0x0000 -#define cfgDEVICE_ID_alt_15__VI 0x0000 -#define cfgDEVICE_ID_alt_16__VI 0x0000 -#define cfgDEVICE_ID_alt_17__VI 0x0000 -#define cfgDEVICE_ID_alt_18__VI 0x0000 -#define cfgDEVICE_ID_alt_4__VI 0x0000 -#define cfgDEVICE_ID_alt_5__VI 0x0000 -#define cfgDEVICE_ID_alt_6__VI 0x0000 -#define cfgDEVICE_ID_alt_7__VI 0x0000 -#define cfgDEVICE_ID_alt_8__VI 0x0000 -#define cfgDEVICE_ID_alt_9__VI 0x0000 -#define cfgDEVICE_STATUS2_alt_10__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_11__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_12__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_13__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_14__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_15__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_16__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_17__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_18__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_4__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_5__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_6__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_7__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_8__VI 0x0020 -#define cfgDEVICE_STATUS2_alt_9__VI 0x0020 -#define cfgDEVICE_STATUS_alt_10__VI 0x0018 -#define cfgDEVICE_STATUS_alt_11__VI 0x0018 -#define cfgDEVICE_STATUS_alt_12__VI 0x0018 -#define cfgDEVICE_STATUS_alt_13__VI 0x0018 -#define cfgDEVICE_STATUS_alt_14__VI 0x0018 -#define cfgDEVICE_STATUS_alt_15__VI 0x0018 -#define cfgDEVICE_STATUS_alt_16__VI 0x0018 -#define cfgDEVICE_STATUS_alt_17__VI 0x0018 -#define cfgDEVICE_STATUS_alt_18__VI 0x0018 -#define cfgDEVICE_STATUS_alt_4__VI 0x0018 -#define cfgDEVICE_STATUS_alt_5__VI 0x0018 -#define cfgDEVICE_STATUS_alt_6__VI 0x0018 -#define cfgDEVICE_STATUS_alt_7__VI 0x0018 -#define cfgDEVICE_STATUS_alt_8__VI 0x0018 -#define cfgDEVICE_STATUS_alt_9__VI 0x0018 -#define cfgHEADER_alt_10__VI 0x0003 -#define cfgHEADER_alt_11__VI 0x0003 -#define cfgHEADER_alt_12__VI 0x0003 -#define cfgHEADER_alt_13__VI 0x0003 -#define cfgHEADER_alt_14__VI 0x0003 -#define cfgHEADER_alt_15__VI 0x0003 -#define cfgHEADER_alt_16__VI 0x0003 -#define cfgHEADER_alt_17__VI 0x0003 -#define cfgHEADER_alt_18__VI 0x0003 -#define cfgHEADER_alt_4__VI 0x0003 -#define cfgHEADER_alt_5__VI 0x0003 -#define cfgHEADER_alt_6__VI 0x0003 -#define cfgHEADER_alt_7__VI 0x0003 -#define cfgHEADER_alt_8__VI 0x0003 -#define cfgHEADER_alt_9__VI 0x0003 -#define cfgINTERRUPT_LINE_alt_10__VI 0x000F -#define cfgINTERRUPT_LINE_alt_11__VI 0x000F -#define cfgINTERRUPT_LINE_alt_12__VI 0x000F -#define cfgINTERRUPT_LINE_alt_13__VI 0x000F -#define cfgINTERRUPT_LINE_alt_14__VI 0x000F -#define cfgINTERRUPT_LINE_alt_15__VI 0x000F -#define cfgINTERRUPT_LINE_alt_16__VI 0x000F -#define cfgINTERRUPT_LINE_alt_17__VI 0x000F -#define cfgINTERRUPT_LINE_alt_18__VI 0x000F -#define cfgINTERRUPT_LINE_alt_4__VI 0x000F -#define cfgINTERRUPT_LINE_alt_5__VI 0x000F -#define cfgINTERRUPT_LINE_alt_6__VI 0x000F -#define cfgINTERRUPT_LINE_alt_7__VI 0x000F -#define cfgINTERRUPT_LINE_alt_8__VI 0x000F -#define cfgINTERRUPT_LINE_alt_9__VI 0x000F -#define cfgINTERRUPT_PIN_alt_10__VI 0x000F -#define cfgINTERRUPT_PIN_alt_11__VI 0x000F -#define cfgINTERRUPT_PIN_alt_12__VI 0x000F -#define cfgINTERRUPT_PIN_alt_13__VI 0x000F -#define cfgINTERRUPT_PIN_alt_14__VI 0x000F -#define cfgINTERRUPT_PIN_alt_15__VI 0x000F -#define cfgINTERRUPT_PIN_alt_16__VI 0x000F -#define cfgINTERRUPT_PIN_alt_17__VI 0x000F -#define cfgINTERRUPT_PIN_alt_18__VI 0x000F -#define cfgINTERRUPT_PIN_alt_4__VI 0x000F -#define cfgINTERRUPT_PIN_alt_5__VI 0x000F -#define cfgINTERRUPT_PIN_alt_6__VI 0x000F -#define cfgINTERRUPT_PIN_alt_7__VI 0x000F -#define cfgINTERRUPT_PIN_alt_8__VI 0x000F -#define cfgINTERRUPT_PIN_alt_9__VI 0x000F -#define cfgLATENCY_alt_10__VI 0x0003 -#define cfgLATENCY_alt_11__VI 0x0003 -#define cfgLATENCY_alt_12__VI 0x0003 -#define cfgLATENCY_alt_13__VI 0x0003 -#define cfgLATENCY_alt_14__VI 0x0003 -#define cfgLATENCY_alt_15__VI 0x0003 -#define cfgLATENCY_alt_16__VI 0x0003 -#define cfgLATENCY_alt_17__VI 0x0003 -#define cfgLATENCY_alt_18__VI 0x0003 -#define cfgLATENCY_alt_4__VI 0x0003 -#define cfgLATENCY_alt_5__VI 0x0003 -#define cfgLATENCY_alt_6__VI 0x0003 -#define cfgLATENCY_alt_7__VI 0x0003 -#define cfgLATENCY_alt_8__VI 0x0003 -#define cfgLATENCY_alt_9__VI 0x0003 -#define cfgLINK_CAP2_alt_10__VI 0x0021 -#define cfgLINK_CAP2_alt_11__VI 0x0021 -#define cfgLINK_CAP2_alt_12__VI 0x0021 -#define cfgLINK_CAP2_alt_13__VI 0x0021 -#define cfgLINK_CAP2_alt_14__VI 0x0021 -#define cfgLINK_CAP2_alt_15__VI 0x0021 -#define cfgLINK_CAP2_alt_16__VI 0x0021 -#define cfgLINK_CAP2_alt_17__VI 0x0021 -#define cfgLINK_CAP2_alt_18__VI 0x0021 -#define cfgLINK_CAP2_alt_4__VI 0x0021 -#define cfgLINK_CAP2_alt_5__VI 0x0021 -#define cfgLINK_CAP2_alt_6__VI 0x0021 -#define cfgLINK_CAP2_alt_7__VI 0x0021 -#define cfgLINK_CAP2_alt_8__VI 0x0021 -#define cfgLINK_CAP2_alt_9__VI 0x0021 -#define cfgLINK_CAP_alt_10__VI 0x0019 -#define cfgLINK_CAP_alt_11__VI 0x0019 -#define cfgLINK_CAP_alt_12__VI 0x0019 -#define cfgLINK_CAP_alt_13__VI 0x0019 -#define cfgLINK_CAP_alt_14__VI 0x0019 -#define cfgLINK_CAP_alt_15__VI 0x0019 -#define cfgLINK_CAP_alt_16__VI 0x0019 -#define cfgLINK_CAP_alt_17__VI 0x0019 -#define cfgLINK_CAP_alt_18__VI 0x0019 -#define cfgLINK_CAP_alt_4__VI 0x0019 -#define cfgLINK_CAP_alt_5__VI 0x0019 -#define cfgLINK_CAP_alt_6__VI 0x0019 -#define cfgLINK_CAP_alt_7__VI 0x0019 -#define cfgLINK_CAP_alt_8__VI 0x0019 -#define cfgLINK_CAP_alt_9__VI 0x0019 -#define cfgLINK_CNTL2_alt_10__VI 0x0022 -#define cfgLINK_CNTL2_alt_11__VI 0x0022 -#define cfgLINK_CNTL2_alt_12__VI 0x0022 -#define cfgLINK_CNTL2_alt_13__VI 0x0022 -#define cfgLINK_CNTL2_alt_14__VI 0x0022 -#define cfgLINK_CNTL2_alt_15__VI 0x0022 -#define cfgLINK_CNTL2_alt_16__VI 0x0022 -#define cfgLINK_CNTL2_alt_17__VI 0x0022 -#define cfgLINK_CNTL2_alt_18__VI 0x0022 -#define cfgLINK_CNTL2_alt_4__VI 0x0022 -#define cfgLINK_CNTL2_alt_5__VI 0x0022 -#define cfgLINK_CNTL2_alt_6__VI 0x0022 -#define cfgLINK_CNTL2_alt_7__VI 0x0022 -#define cfgLINK_CNTL2_alt_8__VI 0x0022 -#define cfgLINK_CNTL2_alt_9__VI 0x0022 -#define cfgLINK_CNTL_alt_10__VI 0x001A -#define cfgLINK_CNTL_alt_11__VI 0x001A -#define cfgLINK_CNTL_alt_12__VI 0x001A -#define cfgLINK_CNTL_alt_13__VI 0x001A -#define cfgLINK_CNTL_alt_14__VI 0x001A -#define cfgLINK_CNTL_alt_15__VI 0x001A -#define cfgLINK_CNTL_alt_16__VI 0x001A -#define cfgLINK_CNTL_alt_17__VI 0x001A -#define cfgLINK_CNTL_alt_18__VI 0x001A -#define cfgLINK_CNTL_alt_4__VI 0x001A -#define cfgLINK_CNTL_alt_5__VI 0x001A -#define cfgLINK_CNTL_alt_6__VI 0x001A -#define cfgLINK_CNTL_alt_7__VI 0x001A -#define cfgLINK_CNTL_alt_8__VI 0x001A -#define cfgLINK_CNTL_alt_9__VI 0x001A -#define cfgLINK_STATUS2_alt_10__VI 0x0022 -#define cfgLINK_STATUS2_alt_11__VI 0x0022 -#define cfgLINK_STATUS2_alt_12__VI 0x0022 -#define cfgLINK_STATUS2_alt_13__VI 0x0022 -#define cfgLINK_STATUS2_alt_14__VI 0x0022 -#define cfgLINK_STATUS2_alt_15__VI 0x0022 -#define cfgLINK_STATUS2_alt_16__VI 0x0022 -#define cfgLINK_STATUS2_alt_17__VI 0x0022 -#define cfgLINK_STATUS2_alt_18__VI 0x0022 -#define cfgLINK_STATUS2_alt_4__VI 0x0022 -#define cfgLINK_STATUS2_alt_5__VI 0x0022 -#define cfgLINK_STATUS2_alt_6__VI 0x0022 -#define cfgLINK_STATUS2_alt_7__VI 0x0022 -#define cfgLINK_STATUS2_alt_8__VI 0x0022 -#define cfgLINK_STATUS2_alt_9__VI 0x0022 -#define cfgLINK_STATUS_alt_10__VI 0x001A -#define cfgLINK_STATUS_alt_11__VI 0x001A -#define cfgLINK_STATUS_alt_12__VI 0x001A -#define cfgLINK_STATUS_alt_13__VI 0x001A -#define cfgLINK_STATUS_alt_14__VI 0x001A -#define cfgLINK_STATUS_alt_15__VI 0x001A -#define cfgLINK_STATUS_alt_16__VI 0x001A -#define cfgLINK_STATUS_alt_17__VI 0x001A -#define cfgLINK_STATUS_alt_18__VI 0x001A -#define cfgLINK_STATUS_alt_4__VI 0x001A -#define cfgLINK_STATUS_alt_5__VI 0x001A -#define cfgLINK_STATUS_alt_6__VI 0x001A -#define cfgLINK_STATUS_alt_7__VI 0x001A -#define cfgLINK_STATUS_alt_8__VI 0x001A -#define cfgLINK_STATUS_alt_9__VI 0x001A -#define cfgMAX_LATENCY_alt_10__VI 0x000F -#define cfgMAX_LATENCY_alt_11__VI 0x000F -#define cfgMAX_LATENCY_alt_12__VI 0x000F -#define cfgMAX_LATENCY_alt_13__VI 0x000F -#define cfgMAX_LATENCY_alt_14__VI 0x000F -#define cfgMAX_LATENCY_alt_15__VI 0x000F -#define cfgMAX_LATENCY_alt_16__VI 0x000F -#define cfgMAX_LATENCY_alt_17__VI 0x000F -#define cfgMAX_LATENCY_alt_18__VI 0x000F -#define cfgMAX_LATENCY_alt_4__VI 0x000F -#define cfgMAX_LATENCY_alt_5__VI 0x000F -#define cfgMAX_LATENCY_alt_6__VI 0x000F -#define cfgMAX_LATENCY_alt_7__VI 0x000F -#define cfgMAX_LATENCY_alt_8__VI 0x000F -#define cfgMAX_LATENCY_alt_9__VI 0x000F -#define cfgMIN_GRANT_alt_10__VI 0x000F -#define cfgMIN_GRANT_alt_11__VI 0x000F -#define cfgMIN_GRANT_alt_12__VI 0x000F -#define cfgMIN_GRANT_alt_13__VI 0x000F -#define cfgMIN_GRANT_alt_14__VI 0x000F -#define cfgMIN_GRANT_alt_15__VI 0x000F -#define cfgMIN_GRANT_alt_16__VI 0x000F -#define cfgMIN_GRANT_alt_17__VI 0x000F -#define cfgMIN_GRANT_alt_18__VI 0x000F -#define cfgMIN_GRANT_alt_4__VI 0x000F -#define cfgMIN_GRANT_alt_5__VI 0x000F -#define cfgMIN_GRANT_alt_6__VI 0x000F -#define cfgMIN_GRANT_alt_7__VI 0x000F -#define cfgMIN_GRANT_alt_8__VI 0x000F -#define cfgMIN_GRANT_alt_9__VI 0x000F -#define cfgMSI_CAP_LIST_alt_10__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_11__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_12__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_13__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_14__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_15__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_16__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_17__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_18__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_4__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_5__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_6__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_7__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_8__VI 0x0028 -#define cfgMSI_CAP_LIST_alt_9__VI 0x0028 -#define cfgMSI_MASK__VI 0x002B -#define cfgMSI_MASK_64__VI 0x002C -#define cfgMSI_MASK_64_alt_1__VI 0x002C -#define cfgMSI_MASK_64_alt_10__VI 0x002C -#define cfgMSI_MASK_64_alt_11__VI 0x002C -#define cfgMSI_MASK_64_alt_12__VI 0x002C -#define cfgMSI_MASK_64_alt_13__VI 0x002C -#define cfgMSI_MASK_64_alt_14__VI 0x002C -#define cfgMSI_MASK_64_alt_15__VI 0x002C -#define cfgMSI_MASK_64_alt_16__VI 0x002C -#define cfgMSI_MASK_64_alt_17__VI 0x002C -#define cfgMSI_MASK_64_alt_18__VI 0x002C -#define cfgMSI_MASK_64_alt_2__VI 0x002C -#define cfgMSI_MASK_64_alt_3__VI 0x002C -#define cfgMSI_MASK_64_alt_4__VI 0x002C -#define cfgMSI_MASK_64_alt_5__VI 0x002C -#define cfgMSI_MASK_64_alt_6__VI 0x002C -#define cfgMSI_MASK_64_alt_7__VI 0x002C -#define cfgMSI_MASK_64_alt_8__VI 0x002C -#define cfgMSI_MASK_64_alt_9__VI 0x002C -#define cfgMSI_MASK_alt_1__VI 0x002B -#define cfgMSI_MASK_alt_10__VI 0x002B -#define cfgMSI_MASK_alt_11__VI 0x002B -#define cfgMSI_MASK_alt_12__VI 0x002B -#define cfgMSI_MASK_alt_13__VI 0x002B -#define cfgMSI_MASK_alt_14__VI 0x002B -#define cfgMSI_MASK_alt_15__VI 0x002B -#define cfgMSI_MASK_alt_16__VI 0x002B -#define cfgMSI_MASK_alt_17__VI 0x002B -#define cfgMSI_MASK_alt_18__VI 0x002B -#define cfgMSI_MASK_alt_2__VI 0x002B -#define cfgMSI_MASK_alt_3__VI 0x002B -#define cfgMSI_MASK_alt_4__VI 0x002B -#define cfgMSI_MASK_alt_5__VI 0x002B -#define cfgMSI_MASK_alt_6__VI 0x002B -#define cfgMSI_MASK_alt_7__VI 0x002B -#define cfgMSI_MASK_alt_8__VI 0x002B -#define cfgMSI_MASK_alt_9__VI 0x002B -#define cfgMSI_MSG_ADDR_HI_alt_10__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_11__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_12__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_13__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_14__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_15__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_16__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_17__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_18__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_4__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_5__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_6__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_7__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_8__VI 0x002A -#define cfgMSI_MSG_ADDR_HI_alt_9__VI 0x002A -#define cfgMSI_MSG_ADDR_LO_alt_10__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_11__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_12__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_13__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_14__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_15__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_16__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_17__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_18__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_4__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_5__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_6__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_7__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_8__VI 0x0029 -#define cfgMSI_MSG_ADDR_LO_alt_9__VI 0x0029 -#define cfgMSI_MSG_CNTL_alt_10__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_11__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_12__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_13__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_14__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_15__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_16__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_17__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_18__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_4__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_5__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_6__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_7__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_8__VI 0x0028 -#define cfgMSI_MSG_CNTL_alt_9__VI 0x0028 -#define cfgMSI_MSG_DATA_64_alt_10__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_11__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_12__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_13__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_14__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_15__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_16__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_17__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_18__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_4__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_5__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_6__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_7__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_8__VI 0x002B -#define cfgMSI_MSG_DATA_64_alt_9__VI 0x002B -#define cfgMSI_MSG_DATA_alt_10__VI 0x002A -#define cfgMSI_MSG_DATA_alt_11__VI 0x002A -#define cfgMSI_MSG_DATA_alt_12__VI 0x002A -#define cfgMSI_MSG_DATA_alt_13__VI 0x002A -#define cfgMSI_MSG_DATA_alt_14__VI 0x002A -#define cfgMSI_MSG_DATA_alt_15__VI 0x002A -#define cfgMSI_MSG_DATA_alt_16__VI 0x002A -#define cfgMSI_MSG_DATA_alt_17__VI 0x002A -#define cfgMSI_MSG_DATA_alt_18__VI 0x002A -#define cfgMSI_MSG_DATA_alt_4__VI 0x002A -#define cfgMSI_MSG_DATA_alt_5__VI 0x002A -#define cfgMSI_MSG_DATA_alt_6__VI 0x002A -#define cfgMSI_MSG_DATA_alt_7__VI 0x002A -#define cfgMSI_MSG_DATA_alt_8__VI 0x002A -#define cfgMSI_MSG_DATA_alt_9__VI 0x002A -#define cfgMSI_PENDING__VI 0x002C -#define cfgMSI_PENDING_64__VI 0x002D -#define cfgMSI_PENDING_64_alt_1__VI 0x002D -#define cfgMSI_PENDING_64_alt_10__VI 0x002D -#define cfgMSI_PENDING_64_alt_11__VI 0x002D -#define cfgMSI_PENDING_64_alt_12__VI 0x002D -#define cfgMSI_PENDING_64_alt_13__VI 0x002D -#define cfgMSI_PENDING_64_alt_14__VI 0x002D -#define cfgMSI_PENDING_64_alt_15__VI 0x002D -#define cfgMSI_PENDING_64_alt_16__VI 0x002D -#define cfgMSI_PENDING_64_alt_17__VI 0x002D -#define cfgMSI_PENDING_64_alt_18__VI 0x002D -#define cfgMSI_PENDING_64_alt_2__VI 0x002D -#define cfgMSI_PENDING_64_alt_3__VI 0x002D -#define cfgMSI_PENDING_64_alt_4__VI 0x002D -#define cfgMSI_PENDING_64_alt_5__VI 0x002D -#define cfgMSI_PENDING_64_alt_6__VI 0x002D -#define cfgMSI_PENDING_64_alt_7__VI 0x002D -#define cfgMSI_PENDING_64_alt_8__VI 0x002D -#define cfgMSI_PENDING_64_alt_9__VI 0x002D -#define cfgMSI_PENDING_alt_1__VI 0x002C -#define cfgMSI_PENDING_alt_10__VI 0x002C -#define cfgMSI_PENDING_alt_11__VI 0x002C -#define cfgMSI_PENDING_alt_12__VI 0x002C -#define cfgMSI_PENDING_alt_13__VI 0x002C -#define cfgMSI_PENDING_alt_14__VI 0x002C -#define cfgMSI_PENDING_alt_15__VI 0x002C -#define cfgMSI_PENDING_alt_16__VI 0x002C -#define cfgMSI_PENDING_alt_17__VI 0x002C -#define cfgMSI_PENDING_alt_18__VI 0x002C -#define cfgMSI_PENDING_alt_2__VI 0x002C -#define cfgMSI_PENDING_alt_3__VI 0x002C -#define cfgMSI_PENDING_alt_4__VI 0x002C -#define cfgMSI_PENDING_alt_5__VI 0x002C -#define cfgMSI_PENDING_alt_6__VI 0x002C -#define cfgMSI_PENDING_alt_7__VI 0x002C -#define cfgMSI_PENDING_alt_8__VI 0x002C -#define cfgMSI_PENDING_alt_9__VI 0x002C -#define cfgPCIE_ACS_CAP_alt_10__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_11__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_12__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_13__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_14__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_15__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_16__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_17__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_18__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_4__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_5__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_6__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_7__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_8__VI 0x00A9 -#define cfgPCIE_ACS_CAP_alt_9__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_10__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_11__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_12__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_13__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_14__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_15__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_16__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_17__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_18__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_4__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_5__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_6__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_7__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_8__VI 0x00A9 -#define cfgPCIE_ACS_CNTL_alt_9__VI 0x00A9 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_10__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_11__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_12__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_13__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_14__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_15__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_16__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_17__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_18__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_4__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_5__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_6__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_7__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_8__VI 0x00A8 -#define cfgPCIE_ACS_ENH_CAP_LIST_alt_9__VI 0x00A8 -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_10__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_11__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_12__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_13__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_14__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_15__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_16__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_17__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_18__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_4__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_5__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_6__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_7__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_8__VI 0x005A -#define cfgPCIE_ADV_ERR_CAP_CNTL_alt_9__VI 0x005A -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_10__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_11__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_12__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_13__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_14__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_15__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_16__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_17__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_18__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_4__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_5__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_6__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_7__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_8__VI 0x0054 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_9__VI 0x0054 -#define cfgPCIE_ARI_CAP__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_1__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_10__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_11__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_12__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_13__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_14__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_15__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_16__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_17__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_18__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_2__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_3__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_4__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_5__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_6__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_7__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_8__VI 0x00CB -#define cfgPCIE_ARI_CAP_alt_9__VI 0x00CB -#define cfgPCIE_ARI_CNTL__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_1__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_10__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_11__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_12__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_13__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_14__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_15__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_16__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_17__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_18__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_2__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_3__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_4__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_5__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_6__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_7__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_8__VI 0x00CB -#define cfgPCIE_ARI_CNTL_alt_9__VI 0x00CB -#define cfgPCIE_ARI_ENH_CAP_LIST__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_1__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_10__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_11__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_12__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_13__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_14__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_15__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_16__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_17__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_18__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_2__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_3__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_4__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_5__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_6__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_7__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_8__VI 0x00CA -#define cfgPCIE_ARI_ENH_CAP_LIST_alt_9__VI 0x00CA -#define cfgPCIE_ATS_CAP_alt_10__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_11__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_12__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_13__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_14__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_15__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_16__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_17__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_18__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_4__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_5__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_6__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_7__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_8__VI 0x00AD -#define cfgPCIE_ATS_CAP_alt_9__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_10__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_11__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_12__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_13__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_14__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_15__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_16__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_17__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_18__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_4__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_5__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_6__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_7__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_8__VI 0x00AD -#define cfgPCIE_ATS_CNTL_alt_9__VI 0x00AD -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_10__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_11__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_12__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_13__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_14__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_15__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_16__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_17__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_18__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_4__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_5__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_6__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_7__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_8__VI 0x00AC -#define cfgPCIE_ATS_ENH_CAP_LIST_alt_9__VI 0x00AC -#define cfgPCIE_BAR1_CAP_alt_10__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_11__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_12__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_13__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_14__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_15__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_16__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_17__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_18__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_4__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_5__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_6__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_7__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_8__VI 0x0081 -#define cfgPCIE_BAR1_CAP_alt_9__VI 0x0081 -#define cfgPCIE_BAR1_CNTL_alt_10__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_11__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_12__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_13__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_14__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_15__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_16__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_17__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_18__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_4__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_5__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_6__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_7__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_8__VI 0x0082 -#define cfgPCIE_BAR1_CNTL_alt_9__VI 0x0082 -#define cfgPCIE_BAR2_CAP_alt_10__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_11__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_12__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_13__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_14__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_15__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_16__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_17__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_18__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_4__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_5__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_6__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_7__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_8__VI 0x0083 -#define cfgPCIE_BAR2_CAP_alt_9__VI 0x0083 -#define cfgPCIE_BAR2_CNTL_alt_10__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_11__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_12__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_13__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_14__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_15__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_16__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_17__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_18__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_4__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_5__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_6__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_7__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_8__VI 0x0084 -#define cfgPCIE_BAR2_CNTL_alt_9__VI 0x0084 -#define cfgPCIE_BAR3_CAP_alt_10__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_11__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_12__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_13__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_14__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_15__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_16__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_17__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_18__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_4__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_5__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_6__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_7__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_8__VI 0x0085 -#define cfgPCIE_BAR3_CAP_alt_9__VI 0x0085 -#define cfgPCIE_BAR3_CNTL_alt_10__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_11__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_12__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_13__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_14__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_15__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_16__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_17__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_18__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_4__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_5__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_6__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_7__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_8__VI 0x0086 -#define cfgPCIE_BAR3_CNTL_alt_9__VI 0x0086 -#define cfgPCIE_BAR4_CAP_alt_10__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_11__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_12__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_13__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_14__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_15__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_16__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_17__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_18__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_4__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_5__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_6__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_7__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_8__VI 0x0087 -#define cfgPCIE_BAR4_CAP_alt_9__VI 0x0087 -#define cfgPCIE_BAR4_CNTL_alt_10__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_11__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_12__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_13__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_14__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_15__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_16__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_17__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_18__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_4__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_5__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_6__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_7__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_8__VI 0x0088 -#define cfgPCIE_BAR4_CNTL_alt_9__VI 0x0088 -#define cfgPCIE_BAR5_CAP_alt_10__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_11__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_12__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_13__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_14__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_15__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_16__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_17__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_18__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_4__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_5__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_6__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_7__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_8__VI 0x0089 -#define cfgPCIE_BAR5_CAP_alt_9__VI 0x0089 -#define cfgPCIE_BAR5_CNTL_alt_10__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_11__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_12__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_13__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_14__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_15__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_16__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_17__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_18__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_4__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_5__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_6__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_7__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_8__VI 0x008A -#define cfgPCIE_BAR5_CNTL_alt_9__VI 0x008A -#define cfgPCIE_BAR6_CAP_alt_10__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_11__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_12__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_13__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_14__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_15__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_16__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_17__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_18__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_4__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_5__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_6__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_7__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_8__VI 0x008B -#define cfgPCIE_BAR6_CAP_alt_9__VI 0x008B -#define cfgPCIE_BAR6_CNTL_alt_10__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_11__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_12__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_13__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_14__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_15__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_16__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_17__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_18__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_4__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_5__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_6__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_7__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_8__VI 0x008C -#define cfgPCIE_BAR6_CNTL_alt_9__VI 0x008C -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_10__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_11__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_12__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_13__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_14__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_15__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_16__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_17__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_18__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_4__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_5__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_6__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_7__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_8__VI 0x0080 -#define cfgPCIE_BAR_ENH_CAP_LIST_alt_9__VI 0x0080 -#define cfgPCIE_CAP_LIST_alt_10__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_11__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_12__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_13__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_14__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_15__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_16__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_17__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_18__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_4__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_5__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_6__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_7__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_8__VI 0x0016 -#define cfgPCIE_CAP_LIST_alt_9__VI 0x0016 -#define cfgPCIE_CAP_alt_10__VI 0x0016 -#define cfgPCIE_CAP_alt_11__VI 0x0016 -#define cfgPCIE_CAP_alt_12__VI 0x0016 -#define cfgPCIE_CAP_alt_13__VI 0x0016 -#define cfgPCIE_CAP_alt_14__VI 0x0016 -#define cfgPCIE_CAP_alt_15__VI 0x0016 -#define cfgPCIE_CAP_alt_16__VI 0x0016 -#define cfgPCIE_CAP_alt_17__VI 0x0016 -#define cfgPCIE_CAP_alt_18__VI 0x0016 -#define cfgPCIE_CAP_alt_4__VI 0x0016 -#define cfgPCIE_CAP_alt_5__VI 0x0016 -#define cfgPCIE_CAP_alt_6__VI 0x0016 -#define cfgPCIE_CAP_alt_7__VI 0x0016 -#define cfgPCIE_CAP_alt_8__VI 0x0016 -#define cfgPCIE_CAP_alt_9__VI 0x0016 -#define cfgPCIE_CORR_ERR_MASK_alt_10__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_11__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_12__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_13__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_14__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_15__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_16__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_17__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_18__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_4__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_5__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_6__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_7__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_8__VI 0x0059 -#define cfgPCIE_CORR_ERR_MASK_alt_9__VI 0x0059 -#define cfgPCIE_CORR_ERR_STATUS_alt_10__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_11__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_12__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_13__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_14__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_15__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_16__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_17__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_18__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_4__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_5__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_6__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_7__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_8__VI 0x0058 -#define cfgPCIE_CORR_ERR_STATUS_alt_9__VI 0x0058 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_10__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_11__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_12__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_13__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_14__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_15__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_16__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_17__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_18__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_4__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_5__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_6__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_7__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_8__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_alt_9__VI 0x0051 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_10__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_11__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_12__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_13__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_14__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_15__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_16__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_17__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_18__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_4__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_5__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_6__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_7__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_8__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_alt_9__VI 0x0052 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_10__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_11__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_12__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_13__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_14__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_15__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_16__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_17__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_18__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_4__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_5__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_6__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_7__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_8__VI 0x0050 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_9__VI 0x0050 -#define cfgPCIE_DPA_CAP_alt_10__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_11__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_12__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_13__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_14__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_15__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_16__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_17__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_18__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_4__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_5__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_6__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_7__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_8__VI 0x0095 -#define cfgPCIE_DPA_CAP_alt_9__VI 0x0095 -#define cfgPCIE_DPA_CNTL_alt_10__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_11__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_12__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_13__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_14__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_15__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_16__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_17__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_18__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_4__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_5__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_6__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_7__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_8__VI 0x0097 -#define cfgPCIE_DPA_CNTL_alt_9__VI 0x0097 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_10__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_11__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_12__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_13__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_14__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_15__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_16__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_17__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_18__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_4__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_5__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_6__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_7__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_8__VI 0x0094 -#define cfgPCIE_DPA_ENH_CAP_LIST_alt_9__VI 0x0094 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_10__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_11__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_12__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_13__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_14__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_15__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_16__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_17__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_18__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_4__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_5__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_6__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_7__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_8__VI 0x0096 -#define cfgPCIE_DPA_LATENCY_INDICATOR_alt_9__VI 0x0096 -#define cfgPCIE_DPA_STATUS_alt_10__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_11__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_12__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_13__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_14__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_15__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_16__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_17__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_18__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_4__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_5__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_6__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_7__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_8__VI 0x0097 -#define cfgPCIE_DPA_STATUS_alt_9__VI 0x0097 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_10__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_11__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_12__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_13__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_14__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_15__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_16__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_17__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_18__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_4__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_5__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_6__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_7__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_8__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_9__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_10__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_11__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_12__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_13__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_14__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_15__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_16__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_17__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_18__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_4__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_5__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_6__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_7__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_8__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_9__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_10__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_11__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_12__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_13__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_14__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_15__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_16__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_17__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_18__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_4__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_5__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_6__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_7__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_8__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_9__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_10__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_11__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_12__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_13__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_14__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_15__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_16__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_17__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_18__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_4__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_5__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_6__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_7__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_8__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_9__VI 0x0098 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_10__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_11__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_12__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_13__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_14__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_15__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_16__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_17__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_18__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_4__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_5__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_6__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_7__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_8__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_9__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_10__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_11__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_12__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_13__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_14__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_15__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_16__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_17__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_18__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_4__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_5__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_6__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_7__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_8__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_9__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_10__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_11__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_12__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_13__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_14__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_15__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_16__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_17__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_18__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_4__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_5__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_6__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_7__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_8__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_9__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_10__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_11__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_12__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_13__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_14__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_15__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_16__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_17__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_18__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_4__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_5__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_6__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_7__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_8__VI 0x0099 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_9__VI 0x0099 -#define cfgPCIE_HDR_LOG0_alt_10__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_11__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_12__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_13__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_14__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_15__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_16__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_17__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_18__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_4__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_5__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_6__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_7__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_8__VI 0x005B -#define cfgPCIE_HDR_LOG0_alt_9__VI 0x005B -#define cfgPCIE_HDR_LOG1_alt_10__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_11__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_12__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_13__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_14__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_15__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_16__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_17__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_18__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_4__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_5__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_6__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_7__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_8__VI 0x005C -#define cfgPCIE_HDR_LOG1_alt_9__VI 0x005C -#define cfgPCIE_HDR_LOG2_alt_10__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_11__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_12__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_13__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_14__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_15__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_16__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_17__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_18__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_4__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_5__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_6__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_7__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_8__VI 0x005D -#define cfgPCIE_HDR_LOG2_alt_9__VI 0x005D -#define cfgPCIE_HDR_LOG3_alt_10__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_11__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_12__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_13__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_14__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_15__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_16__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_17__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_18__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_4__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_5__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_6__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_7__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_8__VI 0x005E -#define cfgPCIE_HDR_LOG3_alt_9__VI 0x005E -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_10__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_11__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_12__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_13__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_14__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_15__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_16__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_17__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_18__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_4__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_5__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_6__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_7__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_8__VI 0x009F -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_alt_9__VI 0x009F -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_10__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_11__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_12__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_13__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_14__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_15__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_16__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_17__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_18__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_4__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_5__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_6__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_7__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_8__VI 0x00A4 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_alt_9__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_10__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_11__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_12__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_13__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_14__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_15__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_16__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_17__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_18__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_4__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_5__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_6__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_7__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_8__VI 0x00A4 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_alt_9__VI 0x00A4 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_10__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_11__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_12__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_13__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_14__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_15__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_16__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_17__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_18__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_4__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_5__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_6__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_7__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_8__VI 0x00A5 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_alt_9__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_10__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_11__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_12__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_13__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_14__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_15__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_16__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_17__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_18__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_4__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_5__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_6__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_7__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_8__VI 0x00A5 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_alt_9__VI 0x00A5 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_10__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_11__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_12__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_13__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_14__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_15__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_16__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_17__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_18__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_4__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_5__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_6__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_7__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_8__VI 0x00A6 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_alt_9__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_10__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_11__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_12__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_13__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_14__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_15__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_16__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_17__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_18__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_4__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_5__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_6__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_7__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_8__VI 0x00A6 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_alt_9__VI 0x00A6 -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_10__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_11__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_12__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_13__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_14__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_15__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_16__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_17__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_18__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_4__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_5__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_6__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_7__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_8__VI 0x009F -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_alt_9__VI 0x009F -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_10__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_11__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_12__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_13__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_14__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_15__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_16__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_17__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_18__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_4__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_5__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_6__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_7__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_8__VI 0x00A0 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_alt_9__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_10__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_11__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_12__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_13__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_14__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_15__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_16__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_17__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_18__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_4__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_5__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_6__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_7__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_8__VI 0x00A0 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_alt_9__VI 0x00A0 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_10__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_11__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_12__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_13__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_14__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_15__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_16__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_17__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_18__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_4__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_5__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_6__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_7__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_8__VI 0x00A1 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_alt_9__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_10__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_11__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_12__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_13__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_14__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_15__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_16__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_17__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_18__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_4__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_5__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_6__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_7__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_8__VI 0x00A1 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_alt_9__VI 0x00A1 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_10__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_11__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_12__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_13__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_14__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_15__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_16__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_17__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_18__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_4__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_5__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_6__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_7__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_8__VI 0x00A2 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_alt_9__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_10__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_11__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_12__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_13__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_14__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_15__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_16__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_17__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_18__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_4__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_5__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_6__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_7__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_8__VI 0x00A2 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_alt_9__VI 0x00A2 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_10__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_11__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_12__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_13__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_14__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_15__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_16__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_17__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_18__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_4__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_5__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_6__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_7__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_8__VI 0x00A3 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_alt_9__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_10__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_11__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_12__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_13__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_14__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_15__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_16__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_17__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_18__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_4__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_5__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_6__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_7__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_8__VI 0x00A3 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_alt_9__VI 0x00A3 -#define cfgPCIE_LANE_ERROR_STATUS_alt_10__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_11__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_12__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_13__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_14__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_15__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_16__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_17__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_18__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_4__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_5__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_6__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_7__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_8__VI 0x009E -#define cfgPCIE_LANE_ERROR_STATUS_alt_9__VI 0x009E -#define cfgPCIE_LINK_CNTL3_alt_10__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_11__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_12__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_13__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_14__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_15__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_16__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_17__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_18__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_4__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_5__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_6__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_7__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_8__VI 0x009D -#define cfgPCIE_LINK_CNTL3_alt_9__VI 0x009D -#define cfgPCIE_LTR_CAP__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_1__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_10__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_11__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_12__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_13__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_14__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_15__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_16__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_17__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_18__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_2__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_3__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_4__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_5__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_6__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_7__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_8__VI 0x00C9 -#define cfgPCIE_LTR_CAP_alt_9__VI 0x00C9 -#define cfgPCIE_LTR_ENH_CAP_LIST__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_1__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_10__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_11__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_12__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_13__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_14__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_15__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_16__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_17__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_18__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_2__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_3__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_4__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_5__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_6__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_7__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_8__VI 0x00C8 -#define cfgPCIE_LTR_ENH_CAP_LIST_alt_9__VI 0x00C8 -#define cfgPCIE_MC_ADDR0__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_1__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_10__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_11__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_12__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_13__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_14__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_15__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_16__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_17__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_18__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_2__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_3__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_4__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_5__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_6__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_7__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_8__VI 0x00BE -#define cfgPCIE_MC_ADDR0_alt_9__VI 0x00BE -#define cfgPCIE_MC_ADDR1__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_1__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_10__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_11__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_12__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_13__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_14__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_15__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_16__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_17__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_18__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_2__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_3__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_4__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_5__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_6__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_7__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_8__VI 0x00BF -#define cfgPCIE_MC_ADDR1_alt_9__VI 0x00BF -#define cfgPCIE_MC_BLOCK_ALL0__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_1__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_10__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_11__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_12__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_13__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_14__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_15__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_16__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_17__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_18__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_2__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_3__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_4__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_5__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_6__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_7__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_8__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL0_alt_9__VI 0x00C2 -#define cfgPCIE_MC_BLOCK_ALL1__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_1__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_10__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_11__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_12__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_13__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_14__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_15__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_16__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_17__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_18__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_2__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_3__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_4__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_5__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_6__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_7__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_8__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_ALL1_alt_9__VI 0x00C3 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_1__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_10__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_11__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_12__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_13__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_14__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_15__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_16__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_17__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_18__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_2__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_3__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_4__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_5__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_6__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_7__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_8__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_alt_9__VI 0x00C4 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_1__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_10__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_11__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_12__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_13__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_14__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_15__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_16__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_17__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_18__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_2__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_3__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_4__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_5__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_6__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_7__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_8__VI 0x00C5 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_alt_9__VI 0x00C5 -#define cfgPCIE_MC_CAP__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_1__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_10__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_11__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_12__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_13__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_14__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_15__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_16__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_17__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_18__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_2__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_3__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_4__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_5__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_6__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_7__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_8__VI 0x00BD -#define cfgPCIE_MC_CAP_alt_9__VI 0x00BD -#define cfgPCIE_MC_CNTL__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_1__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_10__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_11__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_12__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_13__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_14__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_15__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_16__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_17__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_18__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_2__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_3__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_4__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_5__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_6__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_7__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_8__VI 0x00BD -#define cfgPCIE_MC_CNTL_alt_9__VI 0x00BD -#define cfgPCIE_MC_ENH_CAP_LIST__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_1__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_10__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_11__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_12__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_13__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_14__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_15__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_16__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_17__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_18__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_2__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_3__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_4__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_5__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_6__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_7__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_8__VI 0x00BC -#define cfgPCIE_MC_ENH_CAP_LIST_alt_9__VI 0x00BC -#define cfgPCIE_MC_RCV0__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_1__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_10__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_11__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_12__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_13__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_14__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_15__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_16__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_17__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_18__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_2__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_3__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_4__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_5__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_6__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_7__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_8__VI 0x00C0 -#define cfgPCIE_MC_RCV0_alt_9__VI 0x00C0 -#define cfgPCIE_MC_RCV1__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_1__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_10__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_11__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_12__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_13__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_14__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_15__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_16__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_17__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_18__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_2__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_3__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_4__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_5__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_6__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_7__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_8__VI 0x00C1 -#define cfgPCIE_MC_RCV1_alt_9__VI 0x00C1 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_10__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_11__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_12__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_13__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_14__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_15__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_16__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_17__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_18__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_4__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_5__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_6__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_7__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_8__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_9__VI 0x00B3 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_10__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_11__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_12__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_13__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_14__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_15__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_16__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_17__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_18__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_4__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_5__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_6__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_7__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_8__VI 0x00B2 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_9__VI 0x00B2 -#define cfgPCIE_PAGE_REQ_CNTL_alt_10__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_11__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_12__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_13__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_14__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_15__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_16__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_17__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_18__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_4__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_5__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_6__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_7__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_8__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_CNTL_alt_9__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_10__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_11__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_12__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_13__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_14__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_15__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_16__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_17__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_18__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_4__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_5__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_6__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_7__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_8__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_alt_9__VI 0x00B0 -#define cfgPCIE_PAGE_REQ_STATUS_alt_10__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_11__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_12__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_13__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_14__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_15__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_16__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_17__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_18__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_4__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_5__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_6__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_7__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_8__VI 0x00B1 -#define cfgPCIE_PAGE_REQ_STATUS_alt_9__VI 0x00B1 -#define cfgPCIE_PASID_CAP_alt_10__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_11__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_12__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_13__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_14__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_15__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_16__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_17__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_18__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_4__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_5__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_6__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_7__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_8__VI 0x00B5 -#define cfgPCIE_PASID_CAP_alt_9__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_10__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_11__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_12__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_13__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_14__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_15__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_16__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_17__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_18__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_4__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_5__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_6__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_7__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_8__VI 0x00B5 -#define cfgPCIE_PASID_CNTL_alt_9__VI 0x00B5 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_10__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_11__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_12__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_13__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_14__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_15__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_16__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_17__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_18__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_4__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_5__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_6__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_7__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_8__VI 0x00B4 -#define cfgPCIE_PASID_ENH_CAP_LIST_alt_9__VI 0x00B4 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_10__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_11__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_12__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_13__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_14__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_15__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_16__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_17__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_18__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_4__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_5__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_6__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_7__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_8__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG1_alt_9__VI 0x0045 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_10__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_11__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_12__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_13__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_14__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_15__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_16__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_17__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_18__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_4__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_5__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_6__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_7__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_8__VI 0x0046 -#define cfgPCIE_PORT_VC_CAP_REG2_alt_9__VI 0x0046 -#define cfgPCIE_PORT_VC_CNTL_alt_10__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_11__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_12__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_13__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_14__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_15__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_16__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_17__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_18__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_4__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_5__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_6__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_7__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_8__VI 0x0047 -#define cfgPCIE_PORT_VC_CNTL_alt_9__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_10__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_11__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_12__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_13__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_14__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_15__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_16__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_17__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_18__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_4__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_5__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_6__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_7__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_8__VI 0x0047 -#define cfgPCIE_PORT_VC_STATUS_alt_9__VI 0x0047 -#define cfgPCIE_PWR_BUDGET_CAP_alt_10__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_11__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_12__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_13__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_14__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_15__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_16__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_17__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_18__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_4__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_5__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_6__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_7__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_8__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_CAP_alt_9__VI 0x0093 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_10__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_11__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_12__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_13__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_14__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_15__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_16__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_17__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_18__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_4__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_5__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_6__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_7__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_8__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_alt_9__VI 0x0091 -#define cfgPCIE_PWR_BUDGET_DATA_alt_10__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_11__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_12__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_13__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_14__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_15__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_16__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_17__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_18__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_4__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_5__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_6__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_7__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_8__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_DATA_alt_9__VI 0x0092 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_10__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_11__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_12__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_13__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_14__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_15__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_16__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_17__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_18__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_4__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_5__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_6__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_7__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_8__VI 0x0090 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_9__VI 0x0090 -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_10__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_11__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_12__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_13__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_14__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_15__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_16__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_17__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_18__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_4__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_5__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_6__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_7__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_8__VI 0x009C -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_alt_9__VI 0x009C -#define cfgPCIE_SRIOV_CAP__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_1__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_10__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_11__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_12__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_13__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_14__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_15__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_16__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_17__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_18__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_2__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_3__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_4__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_5__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_6__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_7__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_8__VI 0x00CD -#define cfgPCIE_SRIOV_CAP_alt_9__VI 0x00CD -#define cfgPCIE_SRIOV_CONTROL__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_1__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_10__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_11__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_12__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_13__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_14__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_15__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_16__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_17__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_18__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_2__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_3__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_4__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_5__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_6__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_7__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_8__VI 0x00CE -#define cfgPCIE_SRIOV_CONTROL_alt_9__VI 0x00CE -#define cfgPCIE_SRIOV_ENH_CAP_LIST__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_1__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_10__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_11__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_12__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_13__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_14__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_15__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_16__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_17__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_18__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_2__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_3__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_4__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_5__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_6__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_7__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_8__VI 0x00CC -#define cfgPCIE_SRIOV_ENH_CAP_LIST_alt_9__VI 0x00CC -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_1__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_10__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_11__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_12__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_13__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_14__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_15__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_16__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_17__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_18__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_2__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_3__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_4__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_5__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_6__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_7__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_8__VI 0x00D1 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_alt_9__VI 0x00D1 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_1__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_10__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_11__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_12__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_13__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_14__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_15__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_16__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_17__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_18__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_2__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_3__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_4__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_5__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_6__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_7__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_8__VI 0x00D0 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_alt_9__VI 0x00D0 -#define cfgPCIE_SRIOV_INITIAL_VFS__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_1__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_10__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_11__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_12__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_13__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_14__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_15__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_16__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_17__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_18__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_2__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_3__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_4__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_5__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_6__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_7__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_8__VI 0x00CF -#define cfgPCIE_SRIOV_INITIAL_VFS_alt_9__VI 0x00CF -#define cfgPCIE_SRIOV_NUM_VFS__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_1__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_10__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_11__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_12__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_13__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_14__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_15__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_16__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_17__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_18__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_2__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_3__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_4__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_5__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_6__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_7__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_8__VI 0x00D0 -#define cfgPCIE_SRIOV_NUM_VFS_alt_9__VI 0x00D0 -#define cfgPCIE_SRIOV_STATUS__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_1__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_10__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_11__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_12__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_13__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_14__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_15__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_16__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_17__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_18__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_2__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_3__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_4__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_5__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_6__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_7__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_8__VI 0x00CE -#define cfgPCIE_SRIOV_STATUS_alt_9__VI 0x00CE -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_1__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_10__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_11__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_12__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_13__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_14__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_15__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_16__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_17__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_18__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_2__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_3__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_4__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_5__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_6__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_7__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_8__VI 0x00D3 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_9__VI 0x00D3 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_1__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_10__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_11__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_12__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_13__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_14__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_15__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_16__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_17__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_18__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_2__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_3__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_4__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_5__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_6__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_7__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_8__VI 0x00D4 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_9__VI 0x00D4 -#define cfgPCIE_SRIOV_TOTAL_VFS__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_1__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_10__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_11__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_12__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_13__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_14__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_15__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_16__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_17__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_18__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_2__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_3__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_4__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_5__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_6__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_7__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_8__VI 0x00CF -#define cfgPCIE_SRIOV_TOTAL_VFS_alt_9__VI 0x00CF -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_1__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_10__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_11__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_12__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_13__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_14__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_15__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_16__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_17__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_18__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_2__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_3__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_4__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_5__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_6__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_7__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_8__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_alt_9__VI 0x00D5 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_1__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_10__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_11__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_12__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_13__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_14__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_15__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_16__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_17__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_18__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_2__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_3__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_4__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_5__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_6__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_7__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_8__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_alt_9__VI 0x00D6 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_1__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_10__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_11__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_12__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_13__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_14__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_15__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_16__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_17__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_18__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_2__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_3__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_4__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_5__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_6__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_7__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_8__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_alt_9__VI 0x00D7 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_1__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_10__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_11__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_12__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_13__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_14__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_15__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_16__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_17__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_18__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_2__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_3__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_4__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_5__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_6__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_7__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_8__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_alt_9__VI 0x00D8 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_1__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_10__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_11__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_12__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_13__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_14__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_15__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_16__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_17__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_18__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_2__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_3__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_4__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_5__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_6__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_7__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_8__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_alt_9__VI 0x00D9 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_1__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_10__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_11__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_12__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_13__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_14__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_15__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_16__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_17__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_18__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_2__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_3__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_4__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_5__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_6__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_7__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_8__VI 0x00DA -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_alt_9__VI 0x00DA -#define cfgPCIE_SRIOV_VF_DEVICE_ID__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_1__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_10__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_11__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_12__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_13__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_14__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_15__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_16__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_17__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_18__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_2__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_3__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_4__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_5__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_6__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_7__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_8__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_alt_9__VI 0x00D2 -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_1__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_10__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_11__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_12__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_13__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_14__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_15__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_16__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_17__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_18__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_2__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_3__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_4__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_5__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_6__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_7__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_8__VI 0x00DB -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_9__VI 0x00DB -#define cfgPCIE_SRIOV_VF_STRIDE__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_1__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_10__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_11__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_12__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_13__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_14__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_15__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_16__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_17__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_18__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_2__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_3__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_4__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_5__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_6__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_7__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_8__VI 0x00D1 -#define cfgPCIE_SRIOV_VF_STRIDE_alt_9__VI 0x00D1 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_10__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_11__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_12__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_13__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_14__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_15__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_16__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_17__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_18__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_4__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_5__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_6__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_7__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_8__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG0_alt_9__VI 0x0062 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_10__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_11__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_12__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_13__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_14__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_15__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_16__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_17__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_18__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_4__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_5__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_6__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_7__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_8__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG1_alt_9__VI 0x0063 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_10__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_11__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_12__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_13__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_14__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_15__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_16__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_17__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_18__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_4__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_5__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_6__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_7__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_8__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG2_alt_9__VI 0x0064 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_10__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_11__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_12__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_13__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_14__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_15__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_16__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_17__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_18__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_4__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_5__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_6__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_7__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_8__VI 0x0065 -#define cfgPCIE_TLP_PREFIX_LOG3_alt_9__VI 0x0065 -#define cfgPCIE_TPH_REQR_CAP__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_1__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_10__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_11__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_12__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_13__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_14__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_15__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_16__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_17__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_18__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_2__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_3__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_4__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_5__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_6__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_7__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_8__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CAP_alt_9__VI 0x00B9 -#define cfgPCIE_TPH_REQR_CNTL__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_1__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_10__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_11__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_12__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_13__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_14__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_15__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_16__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_17__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_18__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_2__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_3__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_4__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_5__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_6__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_7__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_8__VI 0x00BA -#define cfgPCIE_TPH_REQR_CNTL_alt_9__VI 0x00BA -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_1__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_10__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_11__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_12__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_13__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_14__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_15__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_16__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_17__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_18__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_2__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_3__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_4__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_5__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_6__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_7__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_8__VI 0x00B8 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_alt_9__VI 0x00B8 -#define cfgPCIE_UNCORR_ERR_MASK_alt_10__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_11__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_12__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_13__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_14__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_15__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_16__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_17__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_18__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_4__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_5__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_6__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_7__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_8__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_MASK_alt_9__VI 0x0056 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_10__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_11__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_12__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_13__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_14__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_15__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_16__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_17__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_18__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_4__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_5__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_6__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_7__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_8__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_SEVERITY_alt_9__VI 0x0057 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_10__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_11__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_12__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_13__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_14__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_15__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_16__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_17__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_18__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_4__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_5__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_6__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_7__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_8__VI 0x0055 -#define cfgPCIE_UNCORR_ERR_STATUS_alt_9__VI 0x0055 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_10__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_11__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_12__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_13__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_14__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_15__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_16__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_17__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_18__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_4__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_5__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_6__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_7__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_8__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CAP_alt_9__VI 0x0048 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_10__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_11__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_12__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_13__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_14__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_15__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_16__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_17__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_18__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_4__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_5__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_6__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_7__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_8__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_CNTL_alt_9__VI 0x0049 -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_10__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_11__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_12__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_13__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_14__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_15__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_16__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_17__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_18__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_4__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_5__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_6__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_7__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_8__VI 0x004A -#define cfgPCIE_VC0_RESOURCE_STATUS_alt_9__VI 0x004A -#define cfgPCIE_VC1_RESOURCE_CAP_alt_10__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_11__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_12__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_13__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_14__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_15__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_16__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_17__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_18__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_4__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_5__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_6__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_7__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_8__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CAP_alt_9__VI 0x004B -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_10__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_11__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_12__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_13__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_14__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_15__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_16__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_17__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_18__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_4__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_5__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_6__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_7__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_8__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_CNTL_alt_9__VI 0x004C -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_10__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_11__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_12__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_13__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_14__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_15__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_16__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_17__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_18__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_4__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_5__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_6__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_7__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_8__VI 0x004D -#define cfgPCIE_VC1_RESOURCE_STATUS_alt_9__VI 0x004D -#define cfgPCIE_VC_ENH_CAP_LIST_alt_10__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_11__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_12__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_13__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_14__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_15__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_16__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_17__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_18__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_4__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_5__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_6__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_7__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_8__VI 0x0044 -#define cfgPCIE_VC_ENH_CAP_LIST_alt_9__VI 0x0044 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_10__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_11__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_12__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_13__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_14__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_15__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_16__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_17__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_18__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_4__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_5__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_6__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_7__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_8__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC1_alt_9__VI 0x0042 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_10__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_11__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_12__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_13__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_14__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_15__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_16__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_17__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_18__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_4__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_5__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_6__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_7__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_8__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC2_alt_9__VI 0x0043 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_1__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_10__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_11__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_12__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_13__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_14__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_15__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_16__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_17__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_18__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_2__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_3__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_4__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_5__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_6__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_7__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_8__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_9__VI 0x0100 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_10__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_11__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_12__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_13__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_14__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_15__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_16__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_17__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_18__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_4__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_5__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_6__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_7__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_8__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_9__VI 0x0040 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_1__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_10__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_11__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_12__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_13__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_14__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_15__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_16__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_17__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_18__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_2__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_3__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_4__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_5__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_6__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_7__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_8__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_9__VI 0x0105 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_1__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_10__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_11__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_12__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_13__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_14__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_15__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_16__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_17__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_18__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_2__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_3__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_4__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_5__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_6__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_7__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_8__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_9__VI 0x0101 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_10__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_11__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_12__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_13__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_14__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_15__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_16__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_17__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_18__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_4__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_5__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_6__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_7__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_8__VI 0x0041 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_alt_9__VI 0x0041 -#define cfgPMI_CAP_LIST_alt_10__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_11__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_12__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_13__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_14__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_15__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_16__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_17__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_18__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_4__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_5__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_6__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_7__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_8__VI 0x0014 -#define cfgPMI_CAP_LIST_alt_9__VI 0x0014 -#define cfgPMI_CAP_alt_10__VI 0x0014 -#define cfgPMI_CAP_alt_11__VI 0x0014 -#define cfgPMI_CAP_alt_12__VI 0x0014 -#define cfgPMI_CAP_alt_13__VI 0x0014 -#define cfgPMI_CAP_alt_14__VI 0x0014 -#define cfgPMI_CAP_alt_15__VI 0x0014 -#define cfgPMI_CAP_alt_16__VI 0x0014 -#define cfgPMI_CAP_alt_17__VI 0x0014 -#define cfgPMI_CAP_alt_18__VI 0x0014 -#define cfgPMI_CAP_alt_4__VI 0x0014 -#define cfgPMI_CAP_alt_5__VI 0x0014 -#define cfgPMI_CAP_alt_6__VI 0x0014 -#define cfgPMI_CAP_alt_7__VI 0x0014 -#define cfgPMI_CAP_alt_8__VI 0x0014 -#define cfgPMI_CAP_alt_9__VI 0x0014 -#define cfgPMI_STATUS_CNTL_alt_10__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_11__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_12__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_13__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_14__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_15__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_16__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_17__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_18__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_4__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_5__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_6__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_7__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_8__VI 0x0015 -#define cfgPMI_STATUS_CNTL_alt_9__VI 0x0015 -#define cfgPROG_INTERFACE_alt_10__VI 0x0002 -#define cfgPROG_INTERFACE_alt_11__VI 0x0002 -#define cfgPROG_INTERFACE_alt_12__VI 0x0002 -#define cfgPROG_INTERFACE_alt_13__VI 0x0002 -#define cfgPROG_INTERFACE_alt_14__VI 0x0002 -#define cfgPROG_INTERFACE_alt_15__VI 0x0002 -#define cfgPROG_INTERFACE_alt_16__VI 0x0002 -#define cfgPROG_INTERFACE_alt_17__VI 0x0002 -#define cfgPROG_INTERFACE_alt_18__VI 0x0002 -#define cfgPROG_INTERFACE_alt_4__VI 0x0002 -#define cfgPROG_INTERFACE_alt_5__VI 0x0002 -#define cfgPROG_INTERFACE_alt_6__VI 0x0002 -#define cfgPROG_INTERFACE_alt_7__VI 0x0002 -#define cfgPROG_INTERFACE_alt_8__VI 0x0002 -#define cfgPROG_INTERFACE_alt_9__VI 0x0002 -#define cfgREVISION_ID_alt_10__VI 0x0002 -#define cfgREVISION_ID_alt_11__VI 0x0002 -#define cfgREVISION_ID_alt_12__VI 0x0002 -#define cfgREVISION_ID_alt_13__VI 0x0002 -#define cfgREVISION_ID_alt_14__VI 0x0002 -#define cfgREVISION_ID_alt_15__VI 0x0002 -#define cfgREVISION_ID_alt_16__VI 0x0002 -#define cfgREVISION_ID_alt_17__VI 0x0002 -#define cfgREVISION_ID_alt_18__VI 0x0002 -#define cfgREVISION_ID_alt_4__VI 0x0002 -#define cfgREVISION_ID_alt_5__VI 0x0002 -#define cfgREVISION_ID_alt_6__VI 0x0002 -#define cfgREVISION_ID_alt_7__VI 0x0002 -#define cfgREVISION_ID_alt_8__VI 0x0002 -#define cfgREVISION_ID_alt_9__VI 0x0002 -#define cfgROM_BASE_ADDR_alt_10__VI 0x000C -#define cfgROM_BASE_ADDR_alt_11__VI 0x000C -#define cfgROM_BASE_ADDR_alt_12__VI 0x000C -#define cfgROM_BASE_ADDR_alt_13__VI 0x000C -#define cfgROM_BASE_ADDR_alt_14__VI 0x000C -#define cfgROM_BASE_ADDR_alt_15__VI 0x000C -#define cfgROM_BASE_ADDR_alt_16__VI 0x000C -#define cfgROM_BASE_ADDR_alt_17__VI 0x000C -#define cfgROM_BASE_ADDR_alt_18__VI 0x000C -#define cfgROM_BASE_ADDR_alt_4__VI 0x000C -#define cfgROM_BASE_ADDR_alt_5__VI 0x000C -#define cfgROM_BASE_ADDR_alt_6__VI 0x000C -#define cfgROM_BASE_ADDR_alt_7__VI 0x000C -#define cfgROM_BASE_ADDR_alt_8__VI 0x000C -#define cfgROM_BASE_ADDR_alt_9__VI 0x000C -#define cfgSTATUS_alt_10__VI 0x0001 -#define cfgSTATUS_alt_11__VI 0x0001 -#define cfgSTATUS_alt_12__VI 0x0001 -#define cfgSTATUS_alt_13__VI 0x0001 -#define cfgSTATUS_alt_14__VI 0x0001 -#define cfgSTATUS_alt_15__VI 0x0001 -#define cfgSTATUS_alt_16__VI 0x0001 -#define cfgSTATUS_alt_17__VI 0x0001 -#define cfgSTATUS_alt_18__VI 0x0001 -#define cfgSTATUS_alt_4__VI 0x0001 -#define cfgSTATUS_alt_5__VI 0x0001 -#define cfgSTATUS_alt_6__VI 0x0001 -#define cfgSTATUS_alt_7__VI 0x0001 -#define cfgSTATUS_alt_8__VI 0x0001 -#define cfgSTATUS_alt_9__VI 0x0001 -#define cfgSUB_CLASS_alt_10__VI 0x0002 -#define cfgSUB_CLASS_alt_11__VI 0x0002 -#define cfgSUB_CLASS_alt_12__VI 0x0002 -#define cfgSUB_CLASS_alt_13__VI 0x0002 -#define cfgSUB_CLASS_alt_14__VI 0x0002 -#define cfgSUB_CLASS_alt_15__VI 0x0002 -#define cfgSUB_CLASS_alt_16__VI 0x0002 -#define cfgSUB_CLASS_alt_17__VI 0x0002 -#define cfgSUB_CLASS_alt_18__VI 0x0002 -#define cfgSUB_CLASS_alt_4__VI 0x0002 -#define cfgSUB_CLASS_alt_5__VI 0x0002 -#define cfgSUB_CLASS_alt_6__VI 0x0002 -#define cfgSUB_CLASS_alt_7__VI 0x0002 -#define cfgSUB_CLASS_alt_8__VI 0x0002 -#define cfgSUB_CLASS_alt_9__VI 0x0002 -#define cfgVENDOR_CAP_LIST_alt_10__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_11__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_12__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_13__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_14__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_15__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_16__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_17__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_18__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_4__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_5__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_6__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_7__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_8__VI 0x0012 -#define cfgVENDOR_CAP_LIST_alt_9__VI 0x0012 -#define cfgVENDOR_ID_alt_10__VI 0x0000 -#define cfgVENDOR_ID_alt_11__VI 0x0000 -#define cfgVENDOR_ID_alt_12__VI 0x0000 -#define cfgVENDOR_ID_alt_13__VI 0x0000 -#define cfgVENDOR_ID_alt_14__VI 0x0000 -#define cfgVENDOR_ID_alt_15__VI 0x0000 -#define cfgVENDOR_ID_alt_16__VI 0x0000 -#define cfgVENDOR_ID_alt_17__VI 0x0000 -#define cfgVENDOR_ID_alt_18__VI 0x0000 -#define cfgVENDOR_ID_alt_4__VI 0x0000 -#define cfgVENDOR_ID_alt_5__VI 0x0000 -#define cfgVENDOR_ID_alt_6__VI 0x0000 -#define cfgVENDOR_ID_alt_7__VI 0x0000 -#define cfgVENDOR_ID_alt_8__VI 0x0000 -#define cfgVENDOR_ID_alt_9__VI 0x0000 -#define mmATC_ATS_FAULT_STATUS_INFO2__VI 0x0CD2 -#define mmATC_ATS_VMID_STATUS__VI 0x0D07 -#define mmATC_L1RD_DEBUG2_TLB__VI 0x0CE2 -#define mmATC_L1WR_DEBUG2_TLB__VI 0x0CE3 -#define mmATC_L2_CACHE_DATA0__VI 0x0CD9 -#define mmATC_L2_CACHE_DATA1__VI 0x0CDA -#define mmATC_L2_CACHE_DATA2__VI 0x0CDB -#define mmATC_L2_CNTL3__VI 0x0D08 -#define mmATC_L2_STATUS__VI 0x0D09 -#define mmATC_L2_STATUS2__VI 0x0D0A -#define mmBF_ANA_ISO_CNTL__VI 0x14C7 -#define mmBIF_ATOMIC_ERR_LOG__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_1__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_10__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_11__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_12__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_13__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_14__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_15__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_16__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_2__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_3__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_4__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_5__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_6__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_7__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_8__VI 0x1512 -#define mmBIF_ATOMIC_ERR_LOG_alt_9__VI 0x1512 -#define mmBIF_BME_STATUS__VI 0x1511 -#define mmBIF_BME_STATUS_alt_1__VI 0x1511 -#define mmBIF_BME_STATUS_alt_10__VI 0x1511 -#define mmBIF_BME_STATUS_alt_11__VI 0x1511 -#define mmBIF_BME_STATUS_alt_12__VI 0x1511 -#define mmBIF_BME_STATUS_alt_13__VI 0x1511 -#define mmBIF_BME_STATUS_alt_14__VI 0x1511 -#define mmBIF_BME_STATUS_alt_15__VI 0x1511 -#define mmBIF_BME_STATUS_alt_16__VI 0x1511 -#define mmBIF_BME_STATUS_alt_2__VI 0x1511 -#define mmBIF_BME_STATUS_alt_3__VI 0x1511 -#define mmBIF_BME_STATUS_alt_4__VI 0x1511 -#define mmBIF_BME_STATUS_alt_5__VI 0x1511 -#define mmBIF_BME_STATUS_alt_6__VI 0x1511 -#define mmBIF_BME_STATUS_alt_7__VI 0x1511 -#define mmBIF_BME_STATUS_alt_8__VI 0x1511 -#define mmBIF_BME_STATUS_alt_9__VI 0x1511 -#define mmBIF_CLK_CTRL__VI 0x14C5 -#define mmBIF_DOORBELL_APER_EN__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_1__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_10__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_11__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_12__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_13__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_14__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_15__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_16__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_2__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_3__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_4__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_5__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_6__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_7__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_8__VI 0x1501 -#define mmBIF_DOORBELL_APER_EN_alt_9__VI 0x1501 -#define mmBIF_DOORBELL_GBLAPER1_LOWER__VI 0x14FC -#define mmBIF_DOORBELL_GBLAPER1_UPPER__VI 0x14FD -#define mmBIF_DOORBELL_GBLAPER2_LOWER__VI 0x14FE -#define mmBIF_DOORBELL_GBLAPER2_UPPER__VI 0x14FF -#define mmBIF_GPUIOV_RESET_NOTIFICATION__VI 0x14D5 -#define mmBIF_GPUIOV_VM_INIT_STATUS__VI 0x14D6 -#define mmBIF_MM_INDACCESS_CNTL__VI 0x1500 -#define mmBIF_RB_BASE__VI 0x1531 -#define mmBIF_RB_CNTL__VI 0x1530 -#define mmBIF_RB_RPTR__VI 0x1532 -#define mmBIF_RB_WPTR__VI 0x1533 -#define mmBIF_RB_WPTR_ADDR_HI__VI 0x1534 -#define mmBIF_RB_WPTR_ADDR_LO__VI 0x1535 -#define mmBIF_RFE_MST_BX_CMDSTATUS__VI 0x1449 -#define mmBIF_RFE_MST_SMBUS_CMDSTATUS__VI 0x1448 -#define mmBIF_RFE_WARMRST_CNTL__VI 0x1459 -#define mmBIF_RLC_INTR_CNTL__VI 0x1510 -#define mmBIF_SMU_DATA__VI 0x143E -#define mmBIF_SMU_INDEX__VI 0x143D -#define mmBIF_VDDGFX_FB_CMP__VI 0x143C -#define mmBIF_VDDGFX_GFX0_LOWER__VI 0x1428 -#define mmBIF_VDDGFX_GFX0_UPPER__VI 0x1429 -#define mmBIF_VDDGFX_GFX1_LOWER__VI 0x142A -#define mmBIF_VDDGFX_GFX1_UPPER__VI 0x142B -#define mmBIF_VDDGFX_GFX2_LOWER__VI 0x142C -#define mmBIF_VDDGFX_GFX2_UPPER__VI 0x142D -#define mmBIF_VDDGFX_GFX3_LOWER__VI 0x142E -#define mmBIF_VDDGFX_GFX3_UPPER__VI 0x142F -#define mmBIF_VDDGFX_GFX4_LOWER__VI 0x1430 -#define mmBIF_VDDGFX_GFX4_UPPER__VI 0x1431 -#define mmBIF_VDDGFX_GFX5_LOWER__VI 0x1432 -#define mmBIF_VDDGFX_GFX5_UPPER__VI 0x1433 -#define mmBIF_VDDGFX_RSV1_LOWER__VI 0x1434 -#define mmBIF_VDDGFX_RSV1_UPPER__VI 0x1435 -#define mmBIF_VDDGFX_RSV2_LOWER__VI 0x1436 -#define mmBIF_VDDGFX_RSV2_UPPER__VI 0x1437 -#define mmBIF_VDDGFX_RSV3_LOWER__VI 0x1438 -#define mmBIF_VDDGFX_RSV3_UPPER__VI 0x1439 -#define mmBIF_VDDGFX_RSV4_LOWER__VI 0x143A -#define mmBIF_VDDGFX_RSV4_UPPER__VI 0x143B -#define mmBIF_VIRT_RESET_REQ__VI 0x14D2 -#define mmBX_RESET_CNTL__VI 0x1518 -#define mmCB_COLOR0_DCC_BASE__VI 0xA325 -#define mmCB_COLOR0_DCC_CONTROL__VI 0xA31E -#define mmCB_COLOR1_DCC_BASE__VI 0xA334 -#define mmCB_COLOR1_DCC_CONTROL__VI 0xA32D -#define mmCB_COLOR2_DCC_BASE__VI 0xA343 -#define mmCB_COLOR2_DCC_CONTROL__VI 0xA33C -#define mmCB_COLOR3_DCC_BASE__VI 0xA352 -#define mmCB_COLOR3_DCC_CONTROL__VI 0xA34B -#define mmCB_COLOR4_DCC_BASE__VI 0xA361 -#define mmCB_COLOR4_DCC_CONTROL__VI 0xA35A -#define mmCB_COLOR5_DCC_BASE__VI 0xA370 -#define mmCB_COLOR5_DCC_CONTROL__VI 0xA369 -#define mmCB_COLOR6_DCC_BASE__VI 0xA37F -#define mmCB_COLOR6_DCC_CONTROL__VI 0xA378 -#define mmCB_COLOR7_DCC_BASE__VI 0xA38E -#define mmCB_COLOR7_DCC_CONTROL__VI 0xA387 -#define mmCB_DCC_CONFIG__VI 0x2687 -#define mmCB_DCC_CONTROL__VI 0xA109 -#define mmCB_DEBUG_BUS_19__VI 0x26AB -#define mmCB_DEBUG_BUS_20__VI 0x26AC -#define mmCB_DEBUG_BUS_21__VI 0x26AD -#define mmCB_DEBUG_BUS_22__VI 0x26AE -#define mmCC_BIF_BX_PINSTRAP1__VI 0x1506 -#define mmCC_BIF_BX_PINSTRAP2__VI 0x1505 -#define mmCC_BIF_BX_STRAP2__VI 0x152A -#define mmCC_BIF_SMB_PINSTRAP0__VI 0x15E0 -#define mmCC_BIF_SMB_STRAP0__VI 0x15E1 -#define mmCC_BIF_SMB_STRAP1__VI 0x15FC -#define mmCC_BIF_SMB_STRAP2__VI 0x15FD -#define mmCC_BIF_SMB_STRAP3__VI 0x15FE -#define mmCC_BIF_SMB_STRAP4__VI 0x15FF -#define mmCC_GC_SHADER_RATE_CONFIG__VI 0x2312 -#define mmCG_FPS_CNT__VI 0x01B6 -#define mmCLKREQB_PERF_COUNTER__VI 0x1522 -#define mmCOMPUTE_DISPATCH_ID__VI 0x2E20 -#define mmCOMPUTE_NOWHERE__VI 0x2E7F -#define mmCOMPUTE_RELAUNCH__VI 0x2E22 -#define mmCOMPUTE_THREADGROUP_ID__VI 0x2E21 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI__VI 0x2E24 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO__VI 0x2E23 -#define mmCOMPUTE_WAVE_RESTORE_CONTROL__VI 0x2E25 -#define mmCONFIG_MEMSIZE_alt_1__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_10__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_11__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_12__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_13__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_14__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_15__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_16__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_2__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_3__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_4__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_5__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_6__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_7__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_8__VI 0x150A -#define mmCONFIG_MEMSIZE_alt_9__VI 0x150A -#define mmCP_ATCL1_CNTL__VI 0x303C -#define mmCP_CE_COMPLETION_STATUS__VI 0xC0ED -#define mmCP_CE_METADATA_BASE_ADDR__VI 0xC0F2 -#define mmCP_CE_METADATA_BASE_ADDR_HI__VI 0xC0F3 -#define mmCP_CE_RB_OFFSET__VI 0xC09B -#define mmCP_CE_UCODE_ADDR__SI__CI 0x305A -#define mmCP_CE_UCODE_ADDR__VI 0xF818 -#define mmCP_CE_UCODE_DATA__SI__CI 0x305B -#define mmCP_CE_UCODE_DATA__VI 0xF819 -#define mmCP_CPC_IC_BASE_CNTL__VI 0x30BB -#define mmCP_CPC_IC_BASE_HI__VI 0x30BA -#define mmCP_CPC_IC_BASE_LO__VI 0x30B9 -#define mmCP_CPC_IC_OP_CNTL__VI 0x30BC -#define mmCP_CPC_MGCG_SYNC_CNTL__VI 0x3036 -#define mmCP_DFY_CMD__VI 0x3034 -#define mmCP_DISPATCH_INDR_ADDR__VI 0xC0F6 -#define mmCP_DISPATCH_INDR_ADDR_HI__VI 0xC0F7 -#define mmCP_DRAW_INDX_INDR_ADDR__VI 0xC0F4 -#define mmCP_DRAW_INDX_INDR_ADDR_HI__VI 0xC0F5 -#define mmCP_DRAW_OBJECT__VI 0xD810 -#define mmCP_DRAW_OBJECT_COUNTER__VI 0xD811 -#define mmCP_DRAW_WINDOW_CNTL__VI 0xD815 -#define mmCP_DRAW_WINDOW_HI__VI 0xD813 -#define mmCP_DRAW_WINDOW_LO__VI 0xD814 -#define mmCP_DRAW_WINDOW_MASK_HI__VI 0xD812 -#define mmCP_EOP_DONE_CNTX_ID__VI 0xC0D7 -#define mmCP_GDS_BKUP_ADDR__VI 0xC0FB -#define mmCP_GDS_BKUP_ADDR_HI__VI 0xC0FC -#define mmCP_HPD_STATUS0__VI 0x3241 -#define mmCP_HQD_CNTL_STACK_OFFSET__VI 0x3273 -#define mmCP_HQD_CNTL_STACK_SIZE__VI 0x3274 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI__VI 0x3271 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO__VI 0x3270 -#define mmCP_HQD_CTX_SAVE_CONTROL__VI 0x3272 -#define mmCP_HQD_CTX_SAVE_SIZE__VI 0x3276 -#define mmCP_HQD_EOP_BASE_ADDR__VI 0x326A -#define mmCP_HQD_EOP_BASE_ADDR_HI__VI 0x326B -#define mmCP_HQD_EOP_CONTROL__VI 0x326C -#define mmCP_HQD_EOP_DONES__VI 0x327A -#define mmCP_HQD_EOP_EVENTS__VI 0x326F -#define mmCP_HQD_EOP_RPTR__VI 0x326D -#define mmCP_HQD_EOP_WPTR__VI 0x326E -#define mmCP_HQD_EOP_WPTR_MEM__VI 0x3279 -#define mmCP_HQD_ERROR__VI 0x3278 -#define mmCP_HQD_GDS_RESOURCE_STATE__VI 0x3277 -#define mmCP_HQD_HQ_CONTROL0__VI 0x3266 -#define mmCP_HQD_HQ_CONTROL1__VI 0x3269 -#define mmCP_HQD_HQ_STATUS0__VI 0x3265 -#define mmCP_HQD_HQ_STATUS1__VI 0x3268 -#define mmCP_HQD_OFFLOAD__VI 0x325E -#define mmCP_HQD_WG_STATE_OFFSET__VI 0x3275 -#define mmCP_HYP_CE_UCODE_ADDR__VI 0xF818 -#define mmCP_HYP_CE_UCODE_DATA__VI 0xF819 -#define mmCP_HYP_CONFIG_RANGE_BASE_1__VI 0xF804 -#define mmCP_HYP_CONFIG_RANGE_BASE_2__VI 0xF808 -#define mmCP_HYP_CONFIG_RANGE_END_1__VI 0xF805 -#define mmCP_HYP_CONFIG_RANGE_END_2__VI 0xF809 -#define mmCP_HYP_CONTEXT_RANGE_BASE__VI 0xF80A -#define mmCP_HYP_CONTEXT_RANGE_END__VI 0xF80B -#define mmCP_HYP_MEC1_UCODE_ADDR__VI 0xF81A -#define mmCP_HYP_MEC1_UCODE_DATA__VI 0xF81B -#define mmCP_HYP_MEC2_UCODE_ADDR__VI 0xF81C -#define mmCP_HYP_MEC2_UCODE_DATA__VI 0xF81D -#define mmCP_HYP_ME_UCODE_ADDR__VI 0xF816 -#define mmCP_HYP_ME_UCODE_DATA__VI 0xF817 -#define mmCP_HYP_PFP_UCODE_ADDR__VI 0xF814 -#define mmCP_HYP_PFP_UCODE_DATA__VI 0xF815 -#define mmCP_HYP_SHADER_RANGE_BASE__VI 0xF806 -#define mmCP_HYP_SHADER_RANGE_END__VI 0xF807 -#define mmCP_HYP_UCONFIG_RANGE_BASE__VI 0xF80C -#define mmCP_HYP_UCONFIG_RANGE_END__VI 0xF80D -#define mmCP_INDEX_BASE_ADDR__VI 0xC0F8 -#define mmCP_INDEX_BASE_ADDR_HI__VI 0xC0F9 -#define mmCP_INDEX_TYPE__VI 0xC0FA -#define mmCP_MEC1_F32_INT_DIS__VI 0x30BD -#define mmCP_MEC2_F32_INT_DIS__VI 0x30BE -#define mmCP_MEC_DOORBELL_RANGE_LOWER__VI 0x305C -#define mmCP_MEC_DOORBELL_RANGE_UPPER__VI 0x305D -#define mmCP_MEC_ME1_UCODE_ADDR__VI 0xF81A -#define mmCP_MEC_ME1_UCODE_DATA__VI 0xF81B -#define mmCP_MEC_ME2_UCODE_ADDR__VI 0xF81C -#define mmCP_MEC_ME2_UCODE_DATA__VI 0xF81D -#define mmCP_ME_RAM_DATA__SI__CI 0x3058 -#define mmCP_ME_RAM_DATA__VI 0xF817 -#define mmCP_ME_RAM_RADDR__SI__CI 0x3056 -#define mmCP_ME_RAM_RADDR__VI 0xF816 -#define mmCP_ME_RAM_WADDR__SI__CI 0x3057 -#define mmCP_ME_RAM_WADDR__VI 0xF816 -#define mmCP_PFP_COMPLETION_STATUS__VI 0xC0EC -#define mmCP_PFP_METADATA_BASE_ADDR__VI 0xC0F0 -#define mmCP_PFP_METADATA_BASE_ADDR_HI__VI 0xC0F1 -#define mmCP_PFP_UCODE_ADDR__SI__CI 0x3054 -#define mmCP_PFP_UCODE_ADDR__VI 0xF814 -#define mmCP_PFP_UCODE_DATA__SI__CI 0x3055 -#define mmCP_PFP_UCODE_DATA__VI 0xF815 -#define mmCP_PIPE_STATS_CONTROL__VI 0xC03D -#define mmCP_PQ_STATUS__VI 0x30B8 -#define mmCP_PRED_NOT_VISIBLE__VI 0xC0EE -#define mmCP_RB_DOORBELL_CONTROL__VI 0x3059 -#define mmCP_RB_DOORBELL_RANGE_LOWER__VI 0x305A -#define mmCP_RB_DOORBELL_RANGE_UPPER__VI 0x305B -#define mmCP_SAMPLE_STATUS__VI 0xC0FD -#define mmCP_STREAM_OUT_CONTROL__VI 0xC03E -#define mmCP_VMID_STATUS__VI 0x30BF -#define mmDBG_SMB_BYPASS_SRBM_ACCESS__VI 0x14EB -#define mmGARLIC_COHE_CP_DMA_ME_COMMAND__VI 0x141B -#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND__VI 0x141C -#define mmGARLIC_COHE_CP_DMA_PIO_COMMAND__VI 0x1424 -#define mmGARLIC_COHE_CP_RB0_WPTR__VI 0x1415 -#define mmGARLIC_COHE_CP_RB1_WPTR__VI 0x1416 -#define mmGARLIC_COHE_CP_RB2_WPTR__VI 0x1417 -#define mmGARLIC_COHE_GARLIC_FLUSH_REQ__VI 0x1425 -#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR__VI 0x141D -#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR__VI 0x141E -#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR__VI 0x1419 -#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR__VI 0x141A -#define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR__VI 0x1422 -#define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR__VI 0x1423 -#define mmGARLIC_COHE_UVD_RBC_RB_WPTR__VI 0x1418 -#define mmGARLIC_COHE_VCE_OUT_RB_WPTR__VI 0x141F -#define mmGARLIC_COHE_VCE_RB_WPTR__VI 0x1421 -#define mmGARLIC_COHE_VCE_RB_WPTR2__VI 0x1420 -#define mmGC_CAC_AGGR_LOWER__VI 0x3294 -#define mmGC_CAC_AGGR_UPPER__VI 0x3295 -#define mmGC_CAC_CGTT_CLK_CTRL__VI 0x3292 -#define mmGC_CAC_CTRL_1__VI 0x3290 -#define mmGC_CAC_CTRL_2__VI 0x3291 -#define mmGC_CAC_IND_DATA__VI 0x3299 -#define mmGC_CAC_IND_INDEX__VI 0x3298 -#define mmGC_CAC_LKG_AGGR_LOWER__VI 0x3296 -#define mmGC_CAC_LKG_AGGR_UPPER__VI 0x3297 -#define mmGC_USER_SHADER_RATE_CONFIG__VI 0x2313 -#define mmGDS_CS_CTXSW_CNT0__VI 0x334E -#define mmGDS_CS_CTXSW_CNT1__VI 0x334F -#define mmGDS_CS_CTXSW_CNT2__VI 0x3350 -#define mmGDS_CS_CTXSW_CNT3__VI 0x3351 -#define mmGDS_CS_CTXSW_STATUS__VI 0x334D -#define mmGDS_DSM_CNTL__VI 0x25CA -#define mmGDS_EDC_CNT__VI 0x25C5 -#define mmGDS_EDC_GRBM_CNT__VI 0x25C6 -#define mmGDS_EDC_OA_DED__VI 0x25C7 -#define mmGDS_GFX_CTXSW_STATUS__VI 0x3352 -#define mmGDS_PS0_CTXSW_CNT0__VI 0x3357 -#define mmGDS_PS0_CTXSW_CNT1__VI 0x3358 -#define mmGDS_PS0_CTXSW_CNT2__VI 0x3359 -#define mmGDS_PS0_CTXSW_CNT3__VI 0x335A -#define mmGDS_PS1_CTXSW_CNT0__VI 0x335B -#define mmGDS_PS1_CTXSW_CNT1__VI 0x335C -#define mmGDS_PS1_CTXSW_CNT2__VI 0x335D -#define mmGDS_PS1_CTXSW_CNT3__VI 0x335E -#define mmGDS_PS2_CTXSW_CNT0__VI 0x335F -#define mmGDS_PS2_CTXSW_CNT1__VI 0x3360 -#define mmGDS_PS2_CTXSW_CNT2__VI 0x3361 -#define mmGDS_PS2_CTXSW_CNT3__VI 0x3362 -#define mmGDS_PS3_CTXSW_CNT0__VI 0x3363 -#define mmGDS_PS3_CTXSW_CNT1__VI 0x3364 -#define mmGDS_PS3_CTXSW_CNT2__VI 0x3365 -#define mmGDS_PS3_CTXSW_CNT3__VI 0x3366 -#define mmGDS_PS4_CTXSW_CNT0__VI 0x3367 -#define mmGDS_PS4_CTXSW_CNT1__VI 0x3368 -#define mmGDS_PS4_CTXSW_CNT2__VI 0x3369 -#define mmGDS_PS4_CTXSW_CNT3__VI 0x336A -#define mmGDS_PS5_CTXSW_CNT0__VI 0x336B -#define mmGDS_PS5_CTXSW_CNT1__VI 0x336C -#define mmGDS_PS5_CTXSW_CNT2__VI 0x336D -#define mmGDS_PS5_CTXSW_CNT3__VI 0x336E -#define mmGDS_PS6_CTXSW_CNT0__VI 0x336F -#define mmGDS_PS6_CTXSW_CNT1__VI 0x3370 -#define mmGDS_PS6_CTXSW_CNT2__VI 0x3371 -#define mmGDS_PS6_CTXSW_CNT3__VI 0x3372 -#define mmGDS_PS7_CTXSW_CNT0__VI 0x3373 -#define mmGDS_PS7_CTXSW_CNT1__VI 0x3374 -#define mmGDS_PS7_CTXSW_CNT2__VI 0x3375 -#define mmGDS_PS7_CTXSW_CNT3__VI 0x3376 -#define mmGDS_VS_CTXSW_CNT0__VI 0x3353 -#define mmGDS_VS_CTXSW_CNT1__VI 0x3354 -#define mmGDS_VS_CTXSW_CNT2__VI 0x3355 -#define mmGDS_VS_CTXSW_CNT3__VI 0x3356 -#define mmGMCON_LPT_TARGET__VI 0x0D53 -#define mmGPU_BIST_CONTROL__VI 0xF835 -#define mmGPU_HDP_FLUSH_DONE_alt_1__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_10__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_11__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_12__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_13__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_14__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_15__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_16__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_2__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_3__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_4__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_5__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_6__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_7__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_8__VI 0x1538 -#define mmGPU_HDP_FLUSH_DONE_alt_9__VI 0x1538 -#define mmGPU_HDP_FLUSH_REQ_alt_1__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_10__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_11__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_12__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_13__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_14__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_15__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_16__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_2__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_3__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_4__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_5__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_6__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_7__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_8__VI 0x1537 -#define mmGPU_HDP_FLUSH_REQ_alt_9__VI 0x1537 -#define mmGRBM_CAM_DATA__SI__CI 0x3001 -#define mmGRBM_CAM_DATA__VI 0xF83F -#define mmGRBM_CAM_INDEX__SI__CI 0x3000 -#define mmGRBM_CAM_INDEX__VI 0xF83E -#define mmGRBM_CGTT_CLK_CNTL__VI 0x200B -#define mmGRBM_DSM_BYPASS__VI 0x201E -#define mmGRBM_HYP_CAM_DATA__VI 0xF83F -#define mmGRBM_HYP_CAM_INDEX__VI 0xF83E -#define mmGRBM_TRAP_ADDR__VI 0x201A -#define mmGRBM_TRAP_ADDR_MSK__VI 0x201B -#define mmGRBM_TRAP_OP__VI 0x2019 -#define mmGRBM_TRAP_WD__VI 0x201C -#define mmGRBM_TRAP_WD_MSK__VI 0x201D -#define mmGRBM_WRITE_ERROR__VI 0x201F -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_1__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_10__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_11__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_12__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_13__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_14__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_15__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_16__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_2__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_3__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_4__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_5__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_6__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_7__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_8__VI 0x1520 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_alt_9__VI 0x1520 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_1__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_10__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_11__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_12__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_13__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_14__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_15__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_16__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_2__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_3__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_4__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_5__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_6__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_7__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_8__VI 0x1528 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_alt_9__VI 0x1528 -#define mmIH_CNTL__SI__CI 0x0F86 -#define mmIH_CNTL__VI 0x0E36 -#define mmIH_DSM_MATCH_DATA_CONTROL__VI 0x0E41 -#define mmIH_DSM_MATCH_FIELD_CONTROL__VI 0x0E40 -#define mmIH_DSM_MATCH_VALUE_BIT_31_0__VI 0x0E3D -#define mmIH_DSM_MATCH_VALUE_BIT_63_32__VI 0x0E3E -#define mmIH_DSM_MATCH_VALUE_BIT_95_64__VI 0x0E3F -#define mmIH_LEVEL_STATUS__SI__CI 0x0F87 -#define mmIH_LEVEL_STATUS__VI 0x0E37 -#define mmIH_PERFCOUNTER0_RESULT__VI 0x0E3A -#define mmIH_PERFCOUNTER1_RESULT__VI 0x0E3B -#define mmIH_PERFMON_CNTL__VI 0x0E39 -#define mmIH_RB_BASE__SI__CI 0x0F81 -#define mmIH_RB_BASE__VI 0x0E31 -#define mmIH_RB_CNTL__SI__CI 0x0F80 -#define mmIH_RB_CNTL__VI 0x0E30 -#define mmIH_RB_RPTR__SI__CI 0x0F82 -#define mmIH_RB_RPTR__VI 0x0E32 -#define mmIH_RB_WPTR__SI__CI 0x0F83 -#define mmIH_RB_WPTR__VI 0x0E33 -#define mmIH_RB_WPTR_ADDR_HI__SI__CI 0x0F84 -#define mmIH_RB_WPTR_ADDR_HI__VI 0x0E34 -#define mmIH_RB_WPTR_ADDR_LO__SI__CI 0x0F85 -#define mmIH_RB_WPTR_ADDR_LO__VI 0x0E35 -#define mmIH_STATUS__SI__CI 0x0F88 -#define mmIH_STATUS__VI 0x0E38 -#define mmIH_VERSION__VI 0x0E48 -#define mmIH_VMID_0_LUT__VI 0x0E00 -#define mmIH_VMID_10_LUT__VI 0x0E0A -#define mmIH_VMID_11_LUT__VI 0x0E0B -#define mmIH_VMID_12_LUT__VI 0x0E0C -#define mmIH_VMID_13_LUT__VI 0x0E0D -#define mmIH_VMID_14_LUT__VI 0x0E0E -#define mmIH_VMID_15_LUT__VI 0x0E0F -#define mmIH_VMID_1_LUT__VI 0x0E01 -#define mmIH_VMID_2_LUT__VI 0x0E02 -#define mmIH_VMID_3_LUT__VI 0x0E03 -#define mmIH_VMID_4_LUT__VI 0x0E04 -#define mmIH_VMID_5_LUT__VI 0x0E05 -#define mmIH_VMID_6_LUT__VI 0x0E06 -#define mmIH_VMID_7_LUT__VI 0x0E07 -#define mmIH_VMID_8_LUT__VI 0x0E08 -#define mmIH_VMID_9_LUT__VI 0x0E09 -#define mmMAILBOX_CONTROL__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_1__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_10__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_11__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_12__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_13__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_14__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_15__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_16__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_2__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_3__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_4__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_5__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_6__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_7__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_8__VI 0x14D0 -#define mmMAILBOX_CONTROL_alt_9__VI 0x14D0 -#define mmMAILBOX_INDEX__VI 0x14C6 -#define mmMAILBOX_INT_CNTL__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_1__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_10__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_11__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_12__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_13__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_14__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_15__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_16__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_2__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_3__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_4__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_5__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_6__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_7__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_8__VI 0x14D1 -#define mmMAILBOX_INT_CNTL_alt_9__VI 0x14D1 -#define mmMAILBOX_MSGBUF_RCV_DW0__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_1__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_10__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_11__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_12__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_13__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_14__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_15__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_16__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_2__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_3__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_4__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_5__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_6__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_7__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_8__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW0_alt_9__VI 0x14CC -#define mmMAILBOX_MSGBUF_RCV_DW1__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_1__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_10__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_11__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_12__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_13__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_14__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_15__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_16__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_2__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_3__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_4__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_5__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_6__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_7__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_8__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW1_alt_9__VI 0x14CD -#define mmMAILBOX_MSGBUF_RCV_DW2__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_1__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_10__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_11__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_12__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_13__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_14__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_15__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_16__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_2__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_3__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_4__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_5__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_6__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_7__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_8__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW2_alt_9__VI 0x14CE -#define mmMAILBOX_MSGBUF_RCV_DW3__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_1__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_10__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_11__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_12__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_13__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_14__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_15__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_16__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_2__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_3__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_4__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_5__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_6__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_7__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_8__VI 0x14CF -#define mmMAILBOX_MSGBUF_RCV_DW3_alt_9__VI 0x14CF -#define mmMAILBOX_MSGBUF_TRN_DW0__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_1__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_10__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_11__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_12__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_13__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_14__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_15__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_16__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_2__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_3__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_4__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_5__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_6__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_7__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_8__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW0_alt_9__VI 0x14C8 -#define mmMAILBOX_MSGBUF_TRN_DW1__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_1__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_10__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_11__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_12__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_13__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_14__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_15__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_16__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_2__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_3__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_4__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_5__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_6__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_7__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_8__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW1_alt_9__VI 0x14C9 -#define mmMAILBOX_MSGBUF_TRN_DW2__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_1__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_10__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_11__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_12__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_13__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_14__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_15__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_16__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_2__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_3__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_4__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_5__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_6__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_7__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_8__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW2_alt_9__VI 0x14CA -#define mmMAILBOX_MSGBUF_TRN_DW3__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_1__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_10__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_11__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_12__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_13__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_14__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_15__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_16__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_2__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_3__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_4__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_5__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_6__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_7__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_8__VI 0x14CB -#define mmMAILBOX_MSGBUF_TRN_DW3_alt_9__VI 0x14CB -#define mmMC_ARB_ATOMIC__VI 0x09BE -#define mmMC_ARB_GRUB__VI 0x09C8 -#define mmMC_ARB_GRUB2__VI 0x0A01 -#define mmMC_ARB_GRUB_PRIORITY1_RD__VI 0x0DD8 -#define mmMC_ARB_GRUB_PRIORITY1_WR__VI 0x0DD9 -#define mmMC_ARB_GRUB_PRIORITY2_RD__VI 0x0DDA -#define mmMC_ARB_GRUB_PRIORITY2_WR__VI 0x0DDB -#define mmMC_ARB_GRUB_PROMOTE__VI 0x09CE -#define mmMC_ARB_GRUB_REALTIME_RD__VI 0x09F9 -#define mmMC_ARB_GRUB_REALTIME_WR__VI 0x09FB -#define mmMC_ARB_PERF_CID__VI 0x09C6 -#define mmMC_ARB_SNOOP__VI 0x09C7 -#define mmMC_CG_DATAPORT__SI__CI 0x0A21 -#define mmMC_CG_DATAPORT__VI 0x0A32 -#define mmMC_CITF_CREDITS_ARB_RD2__VI 0x097E -#define mmMC_FUS_ARB_GARLIC_CNTL__VI 0x0A20 -#define mmMC_FUS_ARB_GARLIC_ISOC_PRI__VI 0x0A1F -#define mmMC_FUS_ARB_GARLIC_WR_PRI__VI 0x0A21 -#define mmMC_FUS_ARB_GARLIC_WR_PRI2__VI 0x0A22 -#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING__VI 0x0A11 -#define mmMC_FUS_DRAM0_CS01_MASK__VI 0x0A0D -#define mmMC_FUS_DRAM0_CS0_BASE__VI 0x0A05 -#define mmMC_FUS_DRAM0_CS1_BASE__VI 0x0A07 -#define mmMC_FUS_DRAM0_CS23_MASK__VI 0x0A0F -#define mmMC_FUS_DRAM0_CS2_BASE__VI 0x0A09 -#define mmMC_FUS_DRAM0_CS3_BASE__VI 0x0A0B -#define mmMC_FUS_DRAM0_CTL_BASE__VI 0x0A13 -#define mmMC_FUS_DRAM0_CTL_LIMIT__VI 0x0A15 -#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING__VI 0x0A12 -#define mmMC_FUS_DRAM1_CS01_MASK__VI 0x0A0E -#define mmMC_FUS_DRAM1_CS0_BASE__VI 0x0A06 -#define mmMC_FUS_DRAM1_CS1_BASE__VI 0x0A08 -#define mmMC_FUS_DRAM1_CS23_MASK__VI 0x0A10 -#define mmMC_FUS_DRAM1_CS2_BASE__VI 0x0A0A -#define mmMC_FUS_DRAM1_CS3_BASE__VI 0x0A0C -#define mmMC_FUS_DRAM1_CTL_BASE__VI 0x0A14 -#define mmMC_FUS_DRAM1_CTL_LIMIT__VI 0x0A16 -#define mmMC_FUS_DRAM_APER_BASE__VI 0x0A1A -#define mmMC_FUS_DRAM_APER_DEF__VI 0x0A1E -#define mmMC_FUS_DRAM_APER_TOP__VI 0x0A1B -#define mmMC_FUS_DRAM_CTL_HIGH_01__VI 0x0A17 -#define mmMC_FUS_DRAM_CTL_HIGH_23__VI 0x0A18 -#define mmMC_FUS_DRAM_MODE__VI 0x0A19 -#define mmMC_GRUB_FEATURES__VI 0x0A36 -#define mmMC_GRUB_PERFCOUNTER0_CFG__VI 0x07E6 -#define mmMC_GRUB_PERFCOUNTER1_CFG__VI 0x07E7 -#define mmMC_GRUB_PERFCOUNTER_HI__VI 0x07E5 -#define mmMC_GRUB_PERFCOUNTER_LO__VI 0x07E4 -#define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL__VI 0x07E8 -#define mmMC_GRUB_POST_PROBE_DELAY__VI 0x0A34 -#define mmMC_GRUB_PROBE_CREDITS__VI 0x0A35 -#define mmMC_GRUB_PROBE_MAP__VI 0x0A33 -#define mmMC_GRUB_TCB_DATA_HI__VI 0x0A3A -#define mmMC_GRUB_TCB_DATA_LO__VI 0x0A39 -#define mmMC_GRUB_TCB_INDEX__VI 0x0A38 -#define mmMC_GRUB_TX_CREDITS__VI 0x0A37 -#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS__VI 0x084F -#define mmMC_HUB_RDREQ_ACPG__VI 0x0881 -#define mmMC_HUB_RDREQ_ACPO__VI 0x0882 -#define mmMC_HUB_RDREQ_BYPASS_GBL0__VI 0x084C -#define mmMC_HUB_RDREQ_DMIF__VI 0x0862 -#define mmMC_HUB_RDREQ_HDP__VI 0x085A -#define mmMC_HUB_RDREQ_ISP_CCPU__VI 0x0DE2 -#define mmMC_HUB_RDREQ_ISP_MPM__VI 0x0DE1 -#define mmMC_HUB_RDREQ_ISP_SPM__VI 0x0DE0 -#define mmMC_HUB_RDREQ_MCDS__VI 0x0DE7 -#define mmMC_HUB_RDREQ_MCDT__VI 0x0DE8 -#define mmMC_HUB_RDREQ_MCDU__VI 0x0DE9 -#define mmMC_HUB_RDREQ_MCDV__VI 0x0DEA -#define mmMC_HUB_RDREQ_MCIF__VI 0x0863 -#define mmMC_HUB_RDREQ_RLC__VI 0x085C -#define mmMC_HUB_RDREQ_SAMMSP__VI 0x0883 -#define mmMC_HUB_RDREQ_SDMA0__VI 0x0859 -#define mmMC_HUB_RDREQ_SDMA1__VI 0x085B -#define mmMC_HUB_RDREQ_SEM__VI 0x085D -#define mmMC_HUB_RDREQ_UMC__VI 0x085F -#define mmMC_HUB_RDREQ_UVD__VI 0x0860 -#define mmMC_HUB_RDREQ_VCE0__VI 0x085E -#define mmMC_HUB_RDREQ_VCE1__VI 0x0DFC -#define mmMC_HUB_RDREQ_VCEU0__VI 0x0865 -#define mmMC_HUB_RDREQ_VCEU1__VI 0x0DFD -#define mmMC_HUB_RDREQ_VMC__VI 0x0864 -#define mmMC_HUB_RDREQ_VP8__VI 0x0884 -#define mmMC_HUB_RDREQ_XDMAM__VI 0x0880 -#define mmMC_HUB_WDP_ACPG__VI 0x0885 -#define mmMC_HUB_WDP_ACPO__VI 0x0886 -#define mmMC_HUB_WDP_BP2__VI 0x0DFB -#define mmMC_HUB_WDP_BYPASS_GBL0__VI 0x084A -#define mmMC_HUB_WDP_BYPASS_GBL1__VI 0x084B -#define mmMC_HUB_WDP_CREDITS2__VI 0x0840 -#define mmMC_HUB_WDP_CREDITS_MCDS__VI 0x0DF7 -#define mmMC_HUB_WDP_CREDITS_MCDT__VI 0x0DF8 -#define mmMC_HUB_WDP_CREDITS_MCDU__VI 0x0DF9 -#define mmMC_HUB_WDP_CREDITS_MCDV__VI 0x0DFA -#define mmMC_HUB_WDP_CREDITS_MCDW__VI 0x0DF3 -#define mmMC_HUB_WDP_CREDITS_MCDX__VI 0x0DF4 -#define mmMC_HUB_WDP_CREDITS_MCDY__VI 0x0DF5 -#define mmMC_HUB_WDP_CREDITS_MCDZ__VI 0x0DF6 -#define mmMC_HUB_WDP_HDP__VI 0x0877 -#define mmMC_HUB_WDP_IH__VI 0x0870 -#define mmMC_HUB_WDP_ISP_CCPU__VI 0x0DE6 -#define mmMC_HUB_WDP_ISP_MPM__VI 0x0DE5 -#define mmMC_HUB_WDP_ISP_MPS__VI 0x0DE4 -#define mmMC_HUB_WDP_ISP_SPM__VI 0x0DE3 -#define mmMC_HUB_WDP_MCDS__VI 0x0DEB -#define mmMC_HUB_WDP_MCDT__VI 0x0DEC -#define mmMC_HUB_WDP_MCDU__VI 0x0DED -#define mmMC_HUB_WDP_MCDV__VI 0x0DEE -#define mmMC_HUB_WDP_MCDW__VI 0x0866 -#define mmMC_HUB_WDP_MCDX__VI 0x0867 -#define mmMC_HUB_WDP_MCDY__VI 0x0868 -#define mmMC_HUB_WDP_MCDZ__VI 0x0869 -#define mmMC_HUB_WDP_MCIF__VI 0x086D -#define mmMC_HUB_WDP_RLC__VI 0x0871 -#define mmMC_HUB_WDP_SAMMSP__VI 0x0887 -#define mmMC_HUB_WDP_SDMA0__VI 0x0878 -#define mmMC_HUB_WDP_SDMA1__VI 0x086B -#define mmMC_HUB_WDP_SEM__VI 0x0872 -#define mmMC_HUB_WDP_SH0__VI 0x086C -#define mmMC_HUB_WDP_SH1__VI 0x0874 -#define mmMC_HUB_WDP_SIP__VI 0x086A -#define mmMC_HUB_WDP_SMU__VI 0x0873 -#define mmMC_HUB_WDP_UMC__VI 0x0875 -#define mmMC_HUB_WDP_UVD__VI 0x0876 -#define mmMC_HUB_WDP_VCE0__VI 0x086E -#define mmMC_HUB_WDP_VCE1__VI 0x0DFE -#define mmMC_HUB_WDP_VCEU0__VI 0x087D -#define mmMC_HUB_WDP_VCEU1__VI 0x0DFF -#define mmMC_HUB_WDP_VP8__VI 0x0888 -#define mmMC_HUB_WDP_XDMA__VI 0x087F -#define mmMC_HUB_WDP_XDMAM__VI 0x087E -#define mmMC_HUB_WDP_XDP__VI 0x086F -#define mmMC_HUB_WRRET_MCDS__VI 0x0DEF -#define mmMC_HUB_WRRET_MCDT__VI 0x0DF0 -#define mmMC_HUB_WRRET_MCDU__VI 0x0DF1 -#define mmMC_HUB_WRRET_MCDV__VI 0x0DF2 -#define mmMC_HUB_WRRET_MCDW__VI 0x0879 -#define mmMC_HUB_WRRET_MCDX__VI 0x087A -#define mmMC_HUB_WRRET_MCDY__VI 0x087B -#define mmMC_HUB_WRRET_MCDZ__VI 0x087C -#define mmMC_RPB_TCI_CNTL__VI 0x095C -#define mmMC_RPB_TCI_CNTL2__VI 0x095D -#define mmMC_SHARED_ACTIVE_FCN_ID__VI 0x081F -#define mmMC_SHARED_CHREMAP2__VI 0x081C -#define mmMC_SHARED_VF_ENABLE__VI 0x081D -#define mmMC_SHARED_VIRT_RESET_REQ__VI 0x081E -#define mmMC_VM_FB_SIZE_OFFSET_VF0__VI 0xF980 -#define mmMC_VM_FB_SIZE_OFFSET_VF1__VI 0xF981 -#define mmMC_VM_FB_SIZE_OFFSET_VF10__VI 0xF98A -#define mmMC_VM_FB_SIZE_OFFSET_VF11__VI 0xF98B -#define mmMC_VM_FB_SIZE_OFFSET_VF12__VI 0xF98C -#define mmMC_VM_FB_SIZE_OFFSET_VF13__VI 0xF98D -#define mmMC_VM_FB_SIZE_OFFSET_VF14__VI 0xF98E -#define mmMC_VM_FB_SIZE_OFFSET_VF15__VI 0xF98F -#define mmMC_VM_FB_SIZE_OFFSET_VF2__VI 0xF982 -#define mmMC_VM_FB_SIZE_OFFSET_VF3__VI 0xF983 -#define mmMC_VM_FB_SIZE_OFFSET_VF4__VI 0xF984 -#define mmMC_VM_FB_SIZE_OFFSET_VF5__VI 0xF985 -#define mmMC_VM_FB_SIZE_OFFSET_VF6__VI 0xF986 -#define mmMC_VM_FB_SIZE_OFFSET_VF7__VI 0xF987 -#define mmMC_VM_FB_SIZE_OFFSET_VF8__VI 0xF988 -#define mmMC_VM_FB_SIZE_OFFSET_VF9__VI 0xF989 -#define mmMC_VM_MB_L1_TLB1_DEBUG__VI 0x0892 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2__VI 0xF995 -#define mmMC_VM_NB_MMIOBASE__VI 0xF990 -#define mmMC_VM_NB_MMIOLIMIT__VI 0xF991 -#define mmMC_VM_NB_PCI_ARB__VI 0xF993 -#define mmMC_VM_NB_PCI_CTRL__VI 0xF992 -#define mmMC_VM_NB_TOP_OF_DRAM3__VI 0xF997 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1__VI 0xF994 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2__VI 0xF996 -#define mmMC_XBAR_FIFO_MON_CNTL0__VI 0x0C8F -#define mmMC_XBAR_FIFO_MON_CNTL1__VI 0x0C90 -#define mmMC_XBAR_FIFO_MON_CNTL2__VI 0x0C91 -#define mmMC_XBAR_FIFO_MON_MAX_THSH__VI 0x0C96 -#define mmMC_XBAR_FIFO_MON_RSLT0__VI 0x0C92 -#define mmMC_XBAR_FIFO_MON_RSLT1__VI 0x0C93 -#define mmMC_XBAR_FIFO_MON_RSLT2__VI 0x0C94 -#define mmMC_XBAR_FIFO_MON_RSLT3__VI 0x0C95 -#define mmMM_DATA_alt_1__VI 0x0001 -#define mmMM_DATA_alt_10__VI 0x0001 -#define mmMM_DATA_alt_11__VI 0x0001 -#define mmMM_DATA_alt_12__VI 0x0001 -#define mmMM_DATA_alt_13__VI 0x0001 -#define mmMM_DATA_alt_14__VI 0x0001 -#define mmMM_DATA_alt_15__VI 0x0001 -#define mmMM_DATA_alt_16__VI 0x0001 -#define mmMM_DATA_alt_2__VI 0x0001 -#define mmMM_DATA_alt_3__VI 0x0001 -#define mmMM_DATA_alt_4__VI 0x0001 -#define mmMM_DATA_alt_5__VI 0x0001 -#define mmMM_DATA_alt_6__VI 0x0001 -#define mmMM_DATA_alt_7__VI 0x0001 -#define mmMM_DATA_alt_8__VI 0x0001 -#define mmMM_DATA_alt_9__VI 0x0001 -#define mmMM_INDEX_HI_alt_1__VI 0x0006 -#define mmMM_INDEX_HI_alt_10__VI 0x0006 -#define mmMM_INDEX_HI_alt_11__VI 0x0006 -#define mmMM_INDEX_HI_alt_12__VI 0x0006 -#define mmMM_INDEX_HI_alt_13__VI 0x0006 -#define mmMM_INDEX_HI_alt_14__VI 0x0006 -#define mmMM_INDEX_HI_alt_15__VI 0x0006 -#define mmMM_INDEX_HI_alt_16__VI 0x0006 -#define mmMM_INDEX_HI_alt_2__VI 0x0006 -#define mmMM_INDEX_HI_alt_3__VI 0x0006 -#define mmMM_INDEX_HI_alt_4__VI 0x0006 -#define mmMM_INDEX_HI_alt_5__VI 0x0006 -#define mmMM_INDEX_HI_alt_6__VI 0x0006 -#define mmMM_INDEX_HI_alt_7__VI 0x0006 -#define mmMM_INDEX_HI_alt_8__VI 0x0006 -#define mmMM_INDEX_HI_alt_9__VI 0x0006 -#define mmMM_INDEX_alt_1__VI 0x0000 -#define mmMM_INDEX_alt_10__VI 0x0000 -#define mmMM_INDEX_alt_11__VI 0x0000 -#define mmMM_INDEX_alt_12__VI 0x0000 -#define mmMM_INDEX_alt_13__VI 0x0000 -#define mmMM_INDEX_alt_14__VI 0x0000 -#define mmMM_INDEX_alt_15__VI 0x0000 -#define mmMM_INDEX_alt_16__VI 0x0000 -#define mmMM_INDEX_alt_2__VI 0x0000 -#define mmMM_INDEX_alt_3__VI 0x0000 -#define mmMM_INDEX_alt_4__VI 0x0000 -#define mmMM_INDEX_alt_5__VI 0x0000 -#define mmMM_INDEX_alt_6__VI 0x0000 -#define mmMM_INDEX_alt_7__VI 0x0000 -#define mmMM_INDEX_alt_8__VI 0x0000 -#define mmMM_INDEX_alt_9__VI 0x0000 -#define mmMP_FPS_CNT__VI 0x0235 -#define mmPA_SC_DSM_CNTL__VI 0x22FE -#define mmPA_SC_ENHANCE_1__VI 0x22FD -#define mmPA_SC_SHADER_CONTROL__VI 0xA310 -#define mmRAS_TA_SIGNATURE1__VI 0x33A0 -#define mmREMAP_HDP_MEM_FLUSH_CNTL__VI 0x1426 -#define mmREMAP_HDP_REG_FLUSH_CNTL__VI 0x1427 -#define mmRLC_AUTO_PG_CTRL__VI 0xEC55 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT__VI 0xEC26 -#define mmRLC_CGCG_CGLS_CTRL__VI 0xEC49 -#define mmRLC_CGCG_RAMP_CTRL__VI 0xEC4A -#define mmRLC_CGTT_MGCG_OVERRIDE__VI 0xEC48 -#define mmRLC_CLK_CNTL__VI 0xEC0B -#define mmRLC_CNTL__SI__CI 0x30C0 -#define mmRLC_CNTL__VI 0xEC00 -#define mmRLC_CP_RESPONSE0__VI 0xECA5 -#define mmRLC_CP_RESPONSE1__VI 0xECA6 -#define mmRLC_CP_RESPONSE2__VI 0xECA7 -#define mmRLC_CP_RESPONSE3__VI 0xECA8 -#define mmRLC_CP_SCHEDULERS__VI 0xECAA -#define mmRLC_CSIB_ADDR_HI__VI 0xECA3 -#define mmRLC_CSIB_ADDR_LO__VI 0xECA2 -#define mmRLC_CSIB_LENGTH__VI 0xECA4 -#define mmRLC_CU_STATUS__VI 0xEC4E -#define mmRLC_DEBE_0__VI 0xF837 -#define mmRLC_DEBE_1__VI 0xF838 -#define mmRLC_DEBE_2__VI 0xF839 -#define mmRLC_DEBE_3__VI 0xF83A -#define mmRLC_DEBE_WRITE_DIS__VI 0xF83B -#define mmRLC_DEBUG__VI 0xEC02 -#define mmRLC_DEBUG_SELECT__VI 0xEC01 -#define mmRLC_DYN_PG_REQUEST__VI 0xEC4C -#define mmRLC_DYN_PG_STATUS__VI 0xEC4B -#define mmRLC_GPM_DEBUG__VI 0xEC21 -#define mmRLC_GPM_DEBUG_SELECT__VI 0xEC20 -#define mmRLC_GPM_GENERAL_0__VI 0xEC63 -#define mmRLC_GPM_GENERAL_1__VI 0xEC64 -#define mmRLC_GPM_GENERAL_10__VI 0xECAF -#define mmRLC_GPM_GENERAL_11__VI 0xECB0 -#define mmRLC_GPM_GENERAL_12__VI 0xECB1 -#define mmRLC_GPM_GENERAL_2__VI 0xEC65 -#define mmRLC_GPM_GENERAL_3__VI 0xEC66 -#define mmRLC_GPM_GENERAL_4__VI 0xEC67 -#define mmRLC_GPM_GENERAL_5__VI 0xEC68 -#define mmRLC_GPM_GENERAL_6__VI 0xEC69 -#define mmRLC_GPM_GENERAL_7__VI 0xEC6A -#define mmRLC_GPM_GENERAL_8__VI 0xECAD -#define mmRLC_GPM_GENERAL_9__VI 0xECAE -#define mmRLC_GPM_INT_DISABLE_TH0__VI 0xEC7C -#define mmRLC_GPM_INT_DISABLE_TH1__VI 0xEC7D -#define mmRLC_GPM_INT_FORCE_TH0__VI 0xEC7E -#define mmRLC_GPM_INT_FORCE_TH1__VI 0xEC7F -#define mmRLC_GPM_LOG_CONT__VI 0xEC7B -#define mmRLC_GPM_LOG_SIZE__VI 0xEC77 -#define mmRLC_GPM_PERF_COUNT_0__VI 0xEC6F -#define mmRLC_GPM_PERF_COUNT_1__VI 0xEC70 -#define mmRLC_GPM_SCRATCH_ADDR__VI 0xEC6C -#define mmRLC_GPM_SCRATCH_DATA__VI 0xEC6D -#define mmRLC_GPM_STAT__VI 0xEC40 -#define mmRLC_GPM_THREAD_ENABLE__VI 0xEC45 -#define mmRLC_GPM_THREAD_PRIORITY__VI 0xEC44 -#define mmRLC_GPM_THREAD_RESET__VI 0xEC28 -#define mmRLC_GPM_UCODE_ADDR__VI 0xF83C -#define mmRLC_GPM_UCODE_DATA__VI 0xF83D -#define mmRLC_GPM_VMID_THREAD0__VI 0xEC46 -#define mmRLC_GPM_VMID_THREAD1__VI 0xEC47 -#define mmRLC_GPR_REG1__VI 0xEC79 -#define mmRLC_GPR_REG2__VI 0xEC7A -#define mmRLC_GPU_CLOCK_32__VI 0xEC42 -#define mmRLC_GPU_CLOCK_32_RES_SEL__VI 0xEC41 -#define mmRLC_GPU_CLOCK_COUNT_LSB__VI 0xEC24 -#define mmRLC_GPU_CLOCK_COUNT_MSB__VI 0xEC25 -#define mmRLC_GPU_IOV_ACTIVE_FCN_ID__VI 0xFB40 -#define mmRLC_GPU_IOV_RLC_RESPONSE__VI 0xFB4D -#define mmRLC_GPU_IOV_VF_ENABLE__VI 0xFB00 -#define mmRLC_JUMP_TABLE_RESTORE__VI 0xEC1E -#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__VI 0xEC50 -#define mmRLC_LB_CNTL__VI 0xEC19 -#define mmRLC_LB_CNTR_INIT__VI 0xEC1B -#define mmRLC_LB_CNTR_MAX__VI 0xEC12 -#define mmRLC_LB_INIT_CU_MASK__VI 0xEC4F -#define mmRLC_LB_PARAMS__VI 0xEC51 -#define mmRLC_LOAD_BALANCE_CNTR__VI 0xEC1C -#define mmRLC_MAX_PG_CU__VI 0xEC54 -#define mmRLC_MC_CNTL__VI 0xEC03 -#define mmRLC_MEM_SLP_CNTL__VI 0xEC06 -#define mmRLC_MGCG_CTRL__VI 0xEC1A -#define mmRLC_PERFMON_CLK_CNTL__VI 0xDCBF -#define mmRLC_PG_ALWAYS_ON_CU_MASK__VI 0xEC53 -#define mmRLC_PG_CNTL__VI 0xEC43 -#define mmRLC_PG_DELAY__VI 0xEC4D -#define mmRLC_PG_DELAY_2__VI 0xEC1F -#define mmRLC_PG_DELAY_3__VI 0xEC78 -#define mmRLC_RLCV_COMMAND__VI 0xEC0A -#define mmRLC_RLCV_SAFE_MODE__VI 0xEC08 -#define mmRLC_ROM_CNTL__VI 0xF836 -#define mmRLC_SAFE_MODE__VI 0xEC05 -#define mmRLC_SERDES_CU_MASTER_BUSY__VI 0xEC61 -#define mmRLC_SERDES_NONCU_MASTER_BUSY__VI 0xEC62 -#define mmRLC_SERDES_RD_DATA_0__VI 0xEC5A -#define mmRLC_SERDES_RD_DATA_1__VI 0xEC5B -#define mmRLC_SERDES_RD_DATA_2__VI 0xEC5C -#define mmRLC_SERDES_RD_MASTER_INDEX__VI 0xEC59 -#define mmRLC_SERDES_WR_CTRL__VI 0xEC5F -#define mmRLC_SERDES_WR_CU_MASTER_MASK__VI 0xEC5D -#define mmRLC_SERDES_WR_DATA__VI 0xEC60 -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK__VI 0xEC5E -#define mmRLC_SMU_ARGUMENT_1__VI 0xECAB -#define mmRLC_SMU_ARGUMENT_2__VI 0xECAC -#define mmRLC_SMU_COMMAND__VI 0xECA9 -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL__VI 0xEC56 -#define mmRLC_SMU_MESSAGE__VI 0xEC76 -#define mmRLC_SMU_RESP__VI 0x01BF -#define mmRLC_SMU_SAFE_MODE__VI 0xEC09 -#define mmRLC_SPM_DEBUG__VI 0xEC75 -#define mmRLC_SPM_DEBUG_SELECT__VI 0xEC74 -#define mmRLC_SPM_INT_CNTL__VI 0xEC72 -#define mmRLC_SPM_INT_STATUS__VI 0xEC73 -#define mmRLC_SPM_VMID__VI 0xEC71 -#define mmRLC_SRM_ARAM_ADDR__VI 0xEC83 -#define mmRLC_SRM_ARAM_DATA__VI 0xEC84 -#define mmRLC_SRM_CNTL__VI 0xEC80 -#define mmRLC_SRM_DEBUG__VI 0xEC82 -#define mmRLC_SRM_DEBUG_SELECT__VI 0xEC81 -#define mmRLC_SRM_DRAM_ADDR__VI 0xEC85 -#define mmRLC_SRM_DRAM_DATA__VI 0xEC86 -#define mmRLC_SRM_GPM_ABORT__VI 0xEC9C -#define mmRLC_SRM_GPM_COMMAND__VI 0xEC87 -#define mmRLC_SRM_GPM_COMMAND_STATUS__VI 0xEC88 -#define mmRLC_SRM_INDEX_CNTL_ADDR_0__VI 0xEC8B -#define mmRLC_SRM_INDEX_CNTL_ADDR_1__VI 0xEC8C -#define mmRLC_SRM_INDEX_CNTL_ADDR_2__VI 0xEC8D -#define mmRLC_SRM_INDEX_CNTL_ADDR_3__VI 0xEC8E -#define mmRLC_SRM_INDEX_CNTL_ADDR_4__VI 0xEC8F -#define mmRLC_SRM_INDEX_CNTL_ADDR_5__VI 0xEC90 -#define mmRLC_SRM_INDEX_CNTL_ADDR_6__VI 0xEC91 -#define mmRLC_SRM_INDEX_CNTL_ADDR_7__VI 0xEC92 -#define mmRLC_SRM_INDEX_CNTL_DATA_0__VI 0xEC93 -#define mmRLC_SRM_INDEX_CNTL_DATA_1__VI 0xEC94 -#define mmRLC_SRM_INDEX_CNTL_DATA_2__VI 0xEC95 -#define mmRLC_SRM_INDEX_CNTL_DATA_3__VI 0xEC96 -#define mmRLC_SRM_INDEX_CNTL_DATA_4__VI 0xEC97 -#define mmRLC_SRM_INDEX_CNTL_DATA_5__VI 0xEC98 -#define mmRLC_SRM_INDEX_CNTL_DATA_6__VI 0xEC99 -#define mmRLC_SRM_INDEX_CNTL_DATA_7__VI 0xEC9A -#define mmRLC_SRM_RLCV_COMMAND__VI 0xEC89 -#define mmRLC_SRM_RLCV_COMMAND_STATUS__VI 0xEC8A -#define mmRLC_SRM_STAT__VI 0xEC9B -#define mmRLC_STAT__VI 0xEC04 -#define mmRLC_STATIC_PG_STATUS__VI 0xEC6E -#define mmRLC_THREAD1_DELAY__VI 0xEC52 -#define mmRLC_UCODE_CNTL__VI 0xEC27 -#define mmSDMA0_ACTIVE_FCN_ID__VI 0x341F -#define mmSDMA0_ATOMIC_CNTL__VI 0x342E -#define mmSDMA0_ATOMIC_PREOP_HI__VI 0x3430 -#define mmSDMA0_ATOMIC_PREOP_LO__VI 0x342F -#define mmSDMA0_BA_THRESHOLD__VI 0x342B -#define mmSDMA0_CONTEXT_REG_TYPE0__VI 0x3478 -#define mmSDMA0_CONTEXT_REG_TYPE1__VI 0x3479 -#define mmSDMA0_CONTEXT_REG_TYPE2__VI 0x347A -#define mmSDMA0_EDC_CONFIG__VI 0x341A -#define mmSDMA0_GFX_CSA_ADDR_HI__VI 0x34AD -#define mmSDMA0_GFX_CSA_ADDR_LO__VI 0x34AC -#define mmSDMA0_GFX_DOORBELL__VI 0x3492 -#define mmSDMA0_GFX_DOORBELL_LOG__VI 0x34A9 -#define mmSDMA0_GFX_DUMMY_REG__VI 0x34B1 -#define mmSDMA0_GFX_IB_SUB_REMAIN__VI 0x34AF -#define mmSDMA0_GFX_MIDCMD_CNTL__VI 0x34C7 -#define mmSDMA0_GFX_MIDCMD_DATA0__VI 0x34C1 -#define mmSDMA0_GFX_MIDCMD_DATA1__VI 0x34C2 -#define mmSDMA0_GFX_MIDCMD_DATA2__VI 0x34C3 -#define mmSDMA0_GFX_MIDCMD_DATA3__VI 0x34C4 -#define mmSDMA0_GFX_MIDCMD_DATA4__VI 0x34C5 -#define mmSDMA0_GFX_MIDCMD_DATA5__VI 0x34C6 -#define mmSDMA0_GFX_PREEMPT__VI 0x34B0 -#define mmSDMA0_GFX_WATERMARK__VI 0x34AA -#define mmSDMA0_ID__VI 0x342C -#define mmSDMA0_PERFCOUNTER0_RESULT__VI 0x9001 -#define mmSDMA0_PERFCOUNTER1_RESULT__VI 0x9002 -#define mmSDMA0_PERFMON_CNTL__VI 0x9000 -#define mmSDMA0_PERF_REG_TYPE0__VI 0x3477 -#define mmSDMA0_PUB_REG_TYPE0__VI 0x347C -#define mmSDMA0_PUB_REG_TYPE1__VI 0x347D -#define mmSDMA0_RD_BURST_CNTL__VI 0x340F -#define mmSDMA0_RLC0_CSA_ADDR_HI__VI 0x352D -#define mmSDMA0_RLC0_CSA_ADDR_LO__VI 0x352C -#define mmSDMA0_RLC0_DUMMY_REG__VI 0x3531 -#define mmSDMA0_RLC0_IB_SUB_REMAIN__VI 0x352F -#define mmSDMA0_RLC0_MIDCMD_CNTL__VI 0x3547 -#define mmSDMA0_RLC0_MIDCMD_DATA0__VI 0x3541 -#define mmSDMA0_RLC0_MIDCMD_DATA1__VI 0x3542 -#define mmSDMA0_RLC0_MIDCMD_DATA2__VI 0x3543 -#define mmSDMA0_RLC0_MIDCMD_DATA3__VI 0x3544 -#define mmSDMA0_RLC0_MIDCMD_DATA4__VI 0x3545 -#define mmSDMA0_RLC0_MIDCMD_DATA5__VI 0x3546 -#define mmSDMA0_RLC0_PREEMPT__VI 0x3530 -#define mmSDMA0_RLC0_WATERMARK__VI 0x352A -#define mmSDMA0_RLC1_CSA_ADDR_HI__VI 0x35AD -#define mmSDMA0_RLC1_CSA_ADDR_LO__VI 0x35AC -#define mmSDMA0_RLC1_DUMMY_REG__VI 0x35B1 -#define mmSDMA0_RLC1_IB_SUB_REMAIN__VI 0x35AF -#define mmSDMA0_RLC1_MIDCMD_CNTL__VI 0x35C7 -#define mmSDMA0_RLC1_MIDCMD_DATA0__VI 0x35C1 -#define mmSDMA0_RLC1_MIDCMD_DATA1__VI 0x35C2 -#define mmSDMA0_RLC1_MIDCMD_DATA2__VI 0x35C3 -#define mmSDMA0_RLC1_MIDCMD_DATA3__VI 0x35C4 -#define mmSDMA0_RLC1_MIDCMD_DATA4__VI 0x35C5 -#define mmSDMA0_RLC1_MIDCMD_DATA5__VI 0x35C6 -#define mmSDMA0_RLC1_PREEMPT__VI 0x35B0 -#define mmSDMA0_RLC1_WATERMARK__VI 0x35AA -#define mmSDMA0_STATUS2_REG__VI 0x341E -#define mmSDMA0_VERSION__VI 0x342D -#define mmSDMA0_VF_ENABLE__VI 0x342A -#define mmSDMA0_VIRT_RESET_REQ__VI 0x3421 -#define mmSDMA0_VM_CNTL__VI 0x341B -#define mmSDMA0_VM_CTX_CNTL__VI 0x3420 -#define mmSDMA0_VM_CTX_HI__VI 0x341D -#define mmSDMA0_VM_CTX_LO__VI 0x341C -#define mmSDMA1_ACTIVE_FCN_ID__VI 0x361F -#define mmSDMA1_ATOMIC_CNTL__VI 0x362E -#define mmSDMA1_ATOMIC_PREOP_HI__VI 0x3630 -#define mmSDMA1_ATOMIC_PREOP_LO__VI 0x362F -#define mmSDMA1_BA_THRESHOLD__VI 0x362B -#define mmSDMA1_CONTEXT_REG_TYPE0__VI 0x3678 -#define mmSDMA1_CONTEXT_REG_TYPE1__VI 0x3679 -#define mmSDMA1_CONTEXT_REG_TYPE2__VI 0x367A -#define mmSDMA1_EDC_CONFIG__VI 0x361A -#define mmSDMA1_GFX_CSA_ADDR_HI__VI 0x36AD -#define mmSDMA1_GFX_CSA_ADDR_LO__VI 0x36AC -#define mmSDMA1_GFX_DOORBELL__VI 0x3692 -#define mmSDMA1_GFX_DOORBELL_LOG__VI 0x36A9 -#define mmSDMA1_GFX_DUMMY_REG__VI 0x36B1 -#define mmSDMA1_GFX_IB_SUB_REMAIN__VI 0x36AF -#define mmSDMA1_GFX_MIDCMD_CNTL__VI 0x36C7 -#define mmSDMA1_GFX_MIDCMD_DATA0__VI 0x36C1 -#define mmSDMA1_GFX_MIDCMD_DATA1__VI 0x36C2 -#define mmSDMA1_GFX_MIDCMD_DATA2__VI 0x36C3 -#define mmSDMA1_GFX_MIDCMD_DATA3__VI 0x36C4 -#define mmSDMA1_GFX_MIDCMD_DATA4__VI 0x36C5 -#define mmSDMA1_GFX_MIDCMD_DATA5__VI 0x36C6 -#define mmSDMA1_GFX_PREEMPT__VI 0x36B0 -#define mmSDMA1_GFX_WATERMARK__VI 0x36AA -#define mmSDMA1_ID__VI 0x362C -#define mmSDMA1_PERFCOUNTER0_RESULT__VI 0x9011 -#define mmSDMA1_PERFCOUNTER1_RESULT__VI 0x9012 -#define mmSDMA1_PERFMON_CNTL__VI 0x9010 -#define mmSDMA1_PERF_REG_TYPE0__VI 0x3677 -#define mmSDMA1_PUB_REG_TYPE0__VI 0x367C -#define mmSDMA1_PUB_REG_TYPE1__VI 0x367D -#define mmSDMA1_RD_BURST_CNTL__VI 0x360F -#define mmSDMA1_RLC0_CSA_ADDR_HI__VI 0x372D -#define mmSDMA1_RLC0_CSA_ADDR_LO__VI 0x372C -#define mmSDMA1_RLC0_DUMMY_REG__VI 0x3731 -#define mmSDMA1_RLC0_IB_SUB_REMAIN__VI 0x372F -#define mmSDMA1_RLC0_MIDCMD_CNTL__VI 0x3747 -#define mmSDMA1_RLC0_MIDCMD_DATA0__VI 0x3741 -#define mmSDMA1_RLC0_MIDCMD_DATA1__VI 0x3742 -#define mmSDMA1_RLC0_MIDCMD_DATA2__VI 0x3743 -#define mmSDMA1_RLC0_MIDCMD_DATA3__VI 0x3744 -#define mmSDMA1_RLC0_MIDCMD_DATA4__VI 0x3745 -#define mmSDMA1_RLC0_MIDCMD_DATA5__VI 0x3746 -#define mmSDMA1_RLC0_PREEMPT__VI 0x3730 -#define mmSDMA1_RLC0_WATERMARK__VI 0x372A -#define mmSDMA1_RLC1_CSA_ADDR_HI__VI 0x37AD -#define mmSDMA1_RLC1_CSA_ADDR_LO__VI 0x37AC -#define mmSDMA1_RLC1_DUMMY_REG__VI 0x37B1 -#define mmSDMA1_RLC1_IB_SUB_REMAIN__VI 0x37AF -#define mmSDMA1_RLC1_MIDCMD_CNTL__VI 0x37C7 -#define mmSDMA1_RLC1_MIDCMD_DATA0__VI 0x37C1 -#define mmSDMA1_RLC1_MIDCMD_DATA1__VI 0x37C2 -#define mmSDMA1_RLC1_MIDCMD_DATA2__VI 0x37C3 -#define mmSDMA1_RLC1_MIDCMD_DATA3__VI 0x37C4 -#define mmSDMA1_RLC1_MIDCMD_DATA4__VI 0x37C5 -#define mmSDMA1_RLC1_MIDCMD_DATA5__VI 0x37C6 -#define mmSDMA1_RLC1_PREEMPT__VI 0x37B0 -#define mmSDMA1_RLC1_WATERMARK__VI 0x37AA -#define mmSDMA1_STATUS2_REG__VI 0x361E -#define mmSDMA1_VERSION__VI 0x362D -#define mmSDMA1_VF_ENABLE__VI 0x362A -#define mmSDMA1_VIRT_RESET_REQ__VI 0x3621 -#define mmSDMA1_VM_CNTL__VI 0x361B -#define mmSDMA1_VM_CTX_CNTL__VI 0x3620 -#define mmSDMA1_VM_CTX_HI__VI 0x361D -#define mmSDMA1_VM_CTX_LO__VI 0x361C -#define mmSEM_ACTIVE_FCN_ID__VI 0x0F97 -#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA__VI 0x0F9F -#define mmSEM_PERFCOUNTER0_RESULT__VI 0x0F92 -#define mmSEM_PERFCOUNTER1_RESULT__VI 0x0F93 -#define mmSEM_PERFMON_CNTL__VI 0x0F91 -#define mmSEM_VF_ENABLE__VI 0x0F95 -#define mmSEM_VIRT_RESET_REQ__VI 0x0F98 -#define mmSE_CAC_CGTT_CLK_CTRL__VI 0x3293 -#define mmSMBCLK_PAD_CNTL__VI 0x15ED -#define mmSMBDAT_PAD_CNTL__VI 0x15EC -#define mmSMBUS_BACO_DUMMY__VI 0x15EB -#define mmSMBUS_BLKRD_CMD_CTRL0__VI 0x15E6 -#define mmSMBUS_BLKRD_CMD_CTRL1__VI 0x15E7 -#define mmSMBUS_BLKWR_CMD_CTRL0__VI 0x15E4 -#define mmSMBUS_BLKWR_CMD_CTRL1__VI 0x15E5 -#define mmSMBUS_CNTL0__VI 0x15E2 -#define mmSMBUS_CNTL1__VI 0x15E3 -#define mmSMBUS_TIMING_CNTL0__VI 0x15E8 -#define mmSMBUS_TIMING_CNTL1__VI 0x15E9 -#define mmSMBUS_TIMING_CNTL2__VI 0x15EA -#define mmSMBUS_TRIGGER_CNTL__VI 0x15EE -#define mmSMBUS_UDID_CNTL0__VI 0x15EF -#define mmSMBUS_UDID_CNTL1__VI 0x15F0 -#define mmSMBUS_UDID_CNTL2__VI 0x15F1 -#define mmSMC_MSG_ARG_11__VI 0x0093 -#define mmSMU_ACTIVE_FCN_ID__VI 0x01C2 -#define mmSMU_BIF_VDDGFX_PWR_STATUS__VI 0x14F8 -#define mmSMU_DC_CNTL__VI 0x01B7 -#define mmSMU_IND_DATA_0__VI 0x01A7 -#define mmSMU_IND_DATA_1__VI 0x01A9 -#define mmSMU_IND_DATA_2__VI 0x01AB -#define mmSMU_IND_DATA_3__VI 0x01AD -#define mmSMU_IND_DATA_4__VI 0x01AF -#define mmSMU_IND_DATA_5__VI 0x01B1 -#define mmSMU_IND_DATA_6__VI 0x01B3 -#define mmSMU_IND_DATA_7__VI 0x01B5 -#define mmSMU_IND_INDEX_0__VI 0x01A6 -#define mmSMU_IND_INDEX_1__VI 0x01A8 -#define mmSMU_IND_INDEX_2__VI 0x01AA -#define mmSMU_IND_INDEX_3__VI 0x01AC -#define mmSMU_IND_INDEX_4__VI 0x01AE -#define mmSMU_IND_INDEX_5__VI 0x01B0 -#define mmSMU_IND_INDEX_6__VI 0x01B2 -#define mmSMU_IND_INDEX_7__VI 0x01B4 -#define mmSMU_MP1_RLC2MP_RESP__VI 0x01F4 -#define mmSMU_MP1_SRBM2P_MSG_5__VI 0x01C5 -#define mmSMU_RLC_RESPONSE__VI 0xEC07 -#define mmSMU_UVD_CNTL__VI 0x01B9 -#define mmSMU_VCE_CNTL__VI 0x01B8 -#define mmSMU_VF_ENABLE__VI 0x01C0 -#define mmSMU_VIRT_RESET_REQ__VI 0x01C1 -#define mmSPI_COMPUTE_WF_CTX_SAVE__VI 0x31FC -#define mmSPI_CONFIG_CNTL_2__VI 0x2451 -#define mmSPI_DSM_CNTL__VI 0x2443 -#define mmSPI_EDC_CNT__VI 0x2444 -#define mmSPI_GFX_CNTL__VI 0x243C -#define mmSPI_RESOURCE_RESERVE_CU_12__VI 0x31F4 -#define mmSPI_RESOURCE_RESERVE_CU_13__VI 0x31F5 -#define mmSPI_RESOURCE_RESERVE_CU_14__VI 0x31F6 -#define mmSPI_RESOURCE_RESERVE_CU_15__VI 0x31F7 -#define mmSPI_RESOURCE_RESERVE_EN_CU_12__VI 0x31F8 -#define mmSPI_RESOURCE_RESERVE_EN_CU_13__VI 0x31F9 -#define mmSPI_RESOURCE_RESERVE_EN_CU_14__VI 0x31FA -#define mmSPI_RESOURCE_RESERVE_EN_CU_15__VI 0x31FB -#define mmSPI_START_PHASE__VI 0x243B -#define mmSQC_ATC_EDC_GATCL1_CNT__VI 0x23B3 -#define mmSQC_DSM_CNTL__VI 0x230F -#define mmSQC_EDC_CNT__VI 0x23A0 -#define mmSQC_GATCL1_CNTL__VI 0x23B2 -#define mmSQC_WRITEBACK__VI 0xC349 -#define mmSQ_DSM_CNTL__VI 0x2306 -#define mmSQ_EDC_DED_CNT__VI 0x23A2 -#define mmSQ_EDC_INFO__VI 0x23A3 -#define mmSQ_EDC_SEC_CNT__VI 0x23A1 -#define mmSQ_M0_GPR_IDX_WORD__VI 0x23D2 -#define mmSQ_SMEM_0__VI 0x237F -#define mmSQ_SMEM_1__VI 0x237F -#define mmSQ_THREAD_TRACE_BASE__SI__CI 0x2380 -#define mmSQ_THREAD_TRACE_BASE__VI 0xC330 -#define mmSQ_THREAD_TRACE_BASE2__VI 0xC337 -#define mmSQ_THREAD_TRACE_CTRL__SI__CI 0x238F -#define mmSQ_THREAD_TRACE_CTRL__VI 0xC335 -#define mmSQ_THREAD_TRACE_HIWATER__SI__CI 0x2392 -#define mmSQ_THREAD_TRACE_HIWATER__VI 0xC33B -#define mmSQ_THREAD_TRACE_MASK__SI__CI 0x2382 -#define mmSQ_THREAD_TRACE_MASK__VI 0xC332 -#define mmSQ_THREAD_TRACE_MODE__SI__CI 0x238E -#define mmSQ_THREAD_TRACE_MODE__VI 0xC336 -#define mmSQ_THREAD_TRACE_PERF_MASK__SI__CI 0x2384 -#define mmSQ_THREAD_TRACE_PERF_MASK__VI 0xC334 -#define mmSQ_THREAD_TRACE_SIZE__SI__CI 0x2381 -#define mmSQ_THREAD_TRACE_SIZE__VI 0xC331 -#define mmSQ_THREAD_TRACE_STATUS__SI__CI 0x238D -#define mmSQ_THREAD_TRACE_STATUS__VI 0xC33A -#define mmSQ_THREAD_TRACE_TOKEN_MASK__SI__CI 0x2383 -#define mmSQ_THREAD_TRACE_TOKEN_MASK__VI 0xC333 -#define mmSQ_THREAD_TRACE_TOKEN_MASK2__VI 0xC338 -#define mmSQ_THREAD_TRACE_WPTR__SI__CI 0x238C -#define mmSQ_THREAD_TRACE_WPTR__VI 0xC339 -#define mmSQ_VOP_DPP__VI 0x237F -#define mmSQ_VOP_SDWA__VI 0x237F -#define mmSQ_WREXEC_EXEC_HI__VI 0x23B1 -#define mmSQ_WREXEC_EXEC_LO__VI 0x23B1 -#define mmSRBM_BIF_PLT0__VI 0xFE1E -#define mmSRBM_BIF_PLT1__VI 0xFE1F -#define mmSRBM_CAM_DATA__SI__CI 0x0397 -#define mmSRBM_CAM_DATA__VI 0xFE35 -#define mmSRBM_CAM_INDEX__SI__CI 0x0396 -#define mmSRBM_CAM_INDEX__VI 0xFE34 -#define mmSRBM_CPU_PLT0__VI 0xFE00 -#define mmSRBM_CPU_PLT1__VI 0xFE01 -#define mmSRBM_DEBUG_SNAPSHOT2__VI 0x03AD -#define mmSRBM_DSM_TRIG_CNTL0__VI 0x03AF -#define mmSRBM_DSM_TRIG_CNTL1__VI 0x03B0 -#define mmSRBM_DSM_TRIG_MASK0__VI 0x03B1 -#define mmSRBM_DSM_TRIG_MASK1__VI 0x03B2 -#define mmSRBM_FIREWALL_ERROR_ADDR__VI 0x03AC -#define mmSRBM_FIREWALL_ERROR_SRC__VI 0x03AB -#define mmSRBM_GFX_CNTL_DATA__VI 0xFA2F -#define mmSRBM_GFX_CNTL_SELECT__VI 0xFA2E -#define mmSRBM_GRBM_PLT0__VI 0xFE0A -#define mmSRBM_GRBM_PLT1__VI 0xFE0B -#define mmSRBM_ISP_CLKEN_CNTL__VI 0x03B9 -#define mmSRBM_ISP_DOMAIN_ADDR0__VI 0xFA20 -#define mmSRBM_ISP_DOMAIN_ADDR1__VI 0xFA21 -#define mmSRBM_ISP_DOMAIN_ADDR2__VI 0xFA22 -#define mmSRBM_MC_DOMAIN_ADDR0__VI 0xFA00 -#define mmSRBM_MC_DOMAIN_ADDR1__VI 0xFA01 -#define mmSRBM_MC_DOMAIN_ADDR2__VI 0xFA02 -#define mmSRBM_MC_DOMAIN_ADDR3__VI 0xFA03 -#define mmSRBM_MC_DOMAIN_ADDR4__VI 0xFA04 -#define mmSRBM_MC_DOMAIN_ADDR5__VI 0xFA05 -#define mmSRBM_MC_DOMAIN_ADDR6__VI 0xFA06 -#define mmSRBM_PEER_PLT0__VI 0xFE02 -#define mmSRBM_PEER_PLT1__VI 0xFE03 -#define mmSRBM_PERFCOUNTER0_HI__SI__CI 0x0704 -#define mmSRBM_PERFCOUNTER0_HI__VI 0x7C04 -#define mmSRBM_PERFCOUNTER0_LO__SI__CI 0x0703 -#define mmSRBM_PERFCOUNTER0_LO__VI 0x7C03 -#define mmSRBM_PERFCOUNTER0_SELECT__SI__CI 0x0701 -#define mmSRBM_PERFCOUNTER0_SELECT__VI 0x7C01 -#define mmSRBM_PERFCOUNTER1_HI__SI__CI 0x0706 -#define mmSRBM_PERFCOUNTER1_HI__VI 0x7C06 -#define mmSRBM_PERFCOUNTER1_LO__SI__CI 0x0705 -#define mmSRBM_PERFCOUNTER1_LO__VI 0x7C05 -#define mmSRBM_PERFCOUNTER1_SELECT__SI__CI 0x0702 -#define mmSRBM_PERFCOUNTER1_SELECT__VI 0x7C02 -#define mmSRBM_PERFMON_CNTL__SI__CI 0x0700 -#define mmSRBM_PERFMON_CNTL__VI 0x7C00 -#define mmSRBM_PF_PLT0__VI 0xFE28 -#define mmSRBM_PF_PLT1__VI 0xFE29 -#define mmSRBM_READ_CNTL__VI 0x0392 -#define mmSRBM_READ_ERROR2__VI 0x03AE -#define mmSRBM_SDMA0_PLT0__VI 0xFE0C -#define mmSRBM_SDMA0_PLT1__VI 0xFE0D -#define mmSRBM_SDMA_DOMAIN_ADDR0__VI 0xFA10 -#define mmSRBM_SDMA_DOMAIN_ADDR1__VI 0xFA11 -#define mmSRBM_SDMA_DOMAIN_ADDR2__VI 0xFA12 -#define mmSRBM_SDMA_DOMAIN_ADDR3__VI 0xFA13 -#define mmSRBM_SMU_PLT0__VI 0xFE04 -#define mmSRBM_SMU_PLT1__VI 0xFE05 -#define mmSRBM_STATUS3__VI 0x0395 -#define mmSRBM_SYS_DOMAIN_ADDR0__VI 0xFA08 -#define mmSRBM_SYS_DOMAIN_ADDR1__VI 0xFA09 -#define mmSRBM_SYS_DOMAIN_ADDR2__VI 0xFA0A -#define mmSRBM_SYS_DOMAIN_ADDR3__VI 0xFA0B -#define mmSRBM_SYS_DOMAIN_ADDR4__VI 0xFA0C -#define mmSRBM_SYS_DOMAIN_ADDR5__VI 0xFA0D -#define mmSRBM_SYS_DOMAIN_ADDR6__VI 0xFA0E -#define mmSRBM_TST_PLT0__VI 0xFE14 -#define mmSRBM_TST_PLT1__VI 0xFE15 -#define mmSRBM_UVD_DOMAIN_ADDR0__VI 0xFA14 -#define mmSRBM_UVD_DOMAIN_ADDR1__VI 0xFA15 -#define mmSRBM_UVD_DOMAIN_ADDR2__VI 0xFA16 -#define mmSRBM_VCE_DOMAIN_ADDR0__VI 0xFA18 -#define mmSRBM_VCE_DOMAIN_ADDR1__VI 0xFA19 -#define mmSRBM_VCE_DOMAIN_ADDR2__VI 0xFA1A -#define mmSRBM_VF_ENABLE__VI 0xFA30 -#define mmSRBM_VF_PLT0__VI 0xFE2A -#define mmSRBM_VF_PLT1__VI 0xFE2B -#define mmSRBM_VIRHYP_PLT0__VI 0xFE24 -#define mmSRBM_VIRHYP_PLT1__VI 0xFE25 -#define mmSRBM_VIRT_CNTL__VI 0xFA31 -#define mmSRBM_VIRT_RESET_REQ__VI 0xFA32 -#define mmSRBM_VP8_CLKEN_CNTL__VI 0x03BA -#define mmSRBM_VP8_DOMAIN_ADDR0__VI 0xFA24 -#define mmSX_BLEND_OPT_CONTROL__VI 0xA1D7 -#define mmSX_BLEND_OPT_EPSILON__VI 0xA1D6 -#define mmSX_MRT0_BLEND_OPT__VI 0xA1D8 -#define mmSX_MRT1_BLEND_OPT__VI 0xA1D9 -#define mmSX_MRT2_BLEND_OPT__VI 0xA1DA -#define mmSX_MRT3_BLEND_OPT__VI 0xA1DB -#define mmSX_MRT4_BLEND_OPT__VI 0xA1DC -#define mmSX_MRT5_BLEND_OPT__VI 0xA1DD -#define mmSX_MRT6_BLEND_OPT__VI 0xA1DE -#define mmSX_MRT7_BLEND_OPT__VI 0xA1DF -#define mmSX_PS_DOWNCONVERT__VI 0xA1D5 -#define mmSYS_GRBM_GFX_INDEX_DATA__VI 0xFA2D -#define mmSYS_GRBM_GFX_INDEX_SELECT__VI 0xFA2C -#define mmTCC_DSM_CNTL__VI 0x2B85 -#define mmTCC_EDC_CNT__VI 0x2B82 -#define mmTCC_EXE_DISABLE__VI 0x2B84 -#define mmTCP_ATC_EDC_GATCL1_CNT__VI 0x32B1 -#define mmTCP_CNTL2__VI 0x32B4 -#define mmTCP_DSM_CNTL__VI 0x32B3 -#define mmTCP_EDC_CNT__VI 0x2B17 -#define mmTCP_GATCL1_CNTL__VI 0x32B0 -#define mmTCP_GATCL1_DSM_CNTL__VI 0x32B2 -#define mmTD_DSM_CNTL__VI 0x252F -#define mmVGT_DISPATCH_DRAW_INDEX__VI 0xA2DD -#define mmVGT_TESS_DISTRIBUTION__VI 0xA2D4 -#define mmVM_INIT_STATUS__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_1__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_10__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_11__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_12__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_13__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_14__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_15__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_16__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_2__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_3__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_4__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_5__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_6__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_7__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_8__VI 0x14D3 -#define mmVM_INIT_STATUS_alt_9__VI 0x14D3 -#define mmVM_L2_CNTL4__VI 0x0578 -#define mmWD_QOS__VI 0x2242 -#define pciADAPTER_ID_W_alt_10__VI 0x0013 -#define pciADAPTER_ID_W_alt_11__VI 0x0013 -#define pciADAPTER_ID_W_alt_12__VI 0x0013 -#define pciADAPTER_ID_W_alt_13__VI 0x0013 -#define pciADAPTER_ID_W_alt_14__VI 0x0013 -#define pciADAPTER_ID_W_alt_15__VI 0x0013 -#define pciADAPTER_ID_W_alt_16__VI 0x0013 -#define pciADAPTER_ID_W_alt_17__VI 0x0013 -#define pciADAPTER_ID_W_alt_18__VI 0x0013 -#define pciADAPTER_ID_W_alt_4__VI 0x0013 -#define pciADAPTER_ID_W_alt_5__VI 0x0013 -#define pciADAPTER_ID_W_alt_6__VI 0x0013 -#define pciADAPTER_ID_W_alt_7__VI 0x0013 -#define pciADAPTER_ID_W_alt_8__VI 0x0013 -#define pciADAPTER_ID_W_alt_9__VI 0x0013 -#define pciADAPTER_ID_alt_10__VI 0x000B -#define pciADAPTER_ID_alt_11__VI 0x000B -#define pciADAPTER_ID_alt_12__VI 0x000B -#define pciADAPTER_ID_alt_13__VI 0x000B -#define pciADAPTER_ID_alt_14__VI 0x000B -#define pciADAPTER_ID_alt_15__VI 0x000B -#define pciADAPTER_ID_alt_16__VI 0x000B -#define pciADAPTER_ID_alt_17__VI 0x000B -#define pciADAPTER_ID_alt_18__VI 0x000B -#define pciADAPTER_ID_alt_4__VI 0x000B -#define pciADAPTER_ID_alt_5__VI 0x000B -#define pciADAPTER_ID_alt_6__VI 0x000B -#define pciADAPTER_ID_alt_7__VI 0x000B -#define pciADAPTER_ID_alt_8__VI 0x000B -#define pciADAPTER_ID_alt_9__VI 0x000B -#define pciBASE_ADDR_1_alt_10__VI 0x0004 -#define pciBASE_ADDR_1_alt_11__VI 0x0004 -#define pciBASE_ADDR_1_alt_12__VI 0x0004 -#define pciBASE_ADDR_1_alt_13__VI 0x0004 -#define pciBASE_ADDR_1_alt_14__VI 0x0004 -#define pciBASE_ADDR_1_alt_15__VI 0x0004 -#define pciBASE_ADDR_1_alt_16__VI 0x0004 -#define pciBASE_ADDR_1_alt_17__VI 0x0004 -#define pciBASE_ADDR_1_alt_18__VI 0x0004 -#define pciBASE_ADDR_1_alt_4__VI 0x0004 -#define pciBASE_ADDR_1_alt_5__VI 0x0004 -#define pciBASE_ADDR_1_alt_6__VI 0x0004 -#define pciBASE_ADDR_1_alt_7__VI 0x0004 -#define pciBASE_ADDR_1_alt_8__VI 0x0004 -#define pciBASE_ADDR_1_alt_9__VI 0x0004 -#define pciBASE_ADDR_2_alt_10__VI 0x0005 -#define pciBASE_ADDR_2_alt_11__VI 0x0005 -#define pciBASE_ADDR_2_alt_12__VI 0x0005 -#define pciBASE_ADDR_2_alt_13__VI 0x0005 -#define pciBASE_ADDR_2_alt_14__VI 0x0005 -#define pciBASE_ADDR_2_alt_15__VI 0x0005 -#define pciBASE_ADDR_2_alt_16__VI 0x0005 -#define pciBASE_ADDR_2_alt_17__VI 0x0005 -#define pciBASE_ADDR_2_alt_18__VI 0x0005 -#define pciBASE_ADDR_2_alt_4__VI 0x0005 -#define pciBASE_ADDR_2_alt_5__VI 0x0005 -#define pciBASE_ADDR_2_alt_6__VI 0x0005 -#define pciBASE_ADDR_2_alt_7__VI 0x0005 -#define pciBASE_ADDR_2_alt_8__VI 0x0005 -#define pciBASE_ADDR_2_alt_9__VI 0x0005 -#define pciBASE_ADDR_3_alt_10__VI 0x0006 -#define pciBASE_ADDR_3_alt_11__VI 0x0006 -#define pciBASE_ADDR_3_alt_12__VI 0x0006 -#define pciBASE_ADDR_3_alt_13__VI 0x0006 -#define pciBASE_ADDR_3_alt_14__VI 0x0006 -#define pciBASE_ADDR_3_alt_15__VI 0x0006 -#define pciBASE_ADDR_3_alt_16__VI 0x0006 -#define pciBASE_ADDR_3_alt_17__VI 0x0006 -#define pciBASE_ADDR_3_alt_18__VI 0x0006 -#define pciBASE_ADDR_3_alt_4__VI 0x0006 -#define pciBASE_ADDR_3_alt_5__VI 0x0006 -#define pciBASE_ADDR_3_alt_6__VI 0x0006 -#define pciBASE_ADDR_3_alt_7__VI 0x0006 -#define pciBASE_ADDR_3_alt_8__VI 0x0006 -#define pciBASE_ADDR_3_alt_9__VI 0x0006 -#define pciBASE_ADDR_4_alt_10__VI 0x0007 -#define pciBASE_ADDR_4_alt_11__VI 0x0007 -#define pciBASE_ADDR_4_alt_12__VI 0x0007 -#define pciBASE_ADDR_4_alt_13__VI 0x0007 -#define pciBASE_ADDR_4_alt_14__VI 0x0007 -#define pciBASE_ADDR_4_alt_15__VI 0x0007 -#define pciBASE_ADDR_4_alt_16__VI 0x0007 -#define pciBASE_ADDR_4_alt_17__VI 0x0007 -#define pciBASE_ADDR_4_alt_18__VI 0x0007 -#define pciBASE_ADDR_4_alt_4__VI 0x0007 -#define pciBASE_ADDR_4_alt_5__VI 0x0007 -#define pciBASE_ADDR_4_alt_6__VI 0x0007 -#define pciBASE_ADDR_4_alt_7__VI 0x0007 -#define pciBASE_ADDR_4_alt_8__VI 0x0007 -#define pciBASE_ADDR_4_alt_9__VI 0x0007 -#define pciBASE_ADDR_5_alt_10__VI 0x0008 -#define pciBASE_ADDR_5_alt_11__VI 0x0008 -#define pciBASE_ADDR_5_alt_12__VI 0x0008 -#define pciBASE_ADDR_5_alt_13__VI 0x0008 -#define pciBASE_ADDR_5_alt_14__VI 0x0008 -#define pciBASE_ADDR_5_alt_15__VI 0x0008 -#define pciBASE_ADDR_5_alt_16__VI 0x0008 -#define pciBASE_ADDR_5_alt_17__VI 0x0008 -#define pciBASE_ADDR_5_alt_18__VI 0x0008 -#define pciBASE_ADDR_5_alt_4__VI 0x0008 -#define pciBASE_ADDR_5_alt_5__VI 0x0008 -#define pciBASE_ADDR_5_alt_6__VI 0x0008 -#define pciBASE_ADDR_5_alt_7__VI 0x0008 -#define pciBASE_ADDR_5_alt_8__VI 0x0008 -#define pciBASE_ADDR_5_alt_9__VI 0x0008 -#define pciBASE_ADDR_6_alt_10__VI 0x0009 -#define pciBASE_ADDR_6_alt_11__VI 0x0009 -#define pciBASE_ADDR_6_alt_12__VI 0x0009 -#define pciBASE_ADDR_6_alt_13__VI 0x0009 -#define pciBASE_ADDR_6_alt_14__VI 0x0009 -#define pciBASE_ADDR_6_alt_15__VI 0x0009 -#define pciBASE_ADDR_6_alt_16__VI 0x0009 -#define pciBASE_ADDR_6_alt_17__VI 0x0009 -#define pciBASE_ADDR_6_alt_18__VI 0x0009 -#define pciBASE_ADDR_6_alt_4__VI 0x0009 -#define pciBASE_ADDR_6_alt_5__VI 0x0009 -#define pciBASE_ADDR_6_alt_6__VI 0x0009 -#define pciBASE_ADDR_6_alt_7__VI 0x0009 -#define pciBASE_ADDR_6_alt_8__VI 0x0009 -#define pciBASE_ADDR_6_alt_9__VI 0x0009 -#define pciBASE_CLASS_alt_10__VI 0x0002 -#define pciBASE_CLASS_alt_11__VI 0x0002 -#define pciBASE_CLASS_alt_12__VI 0x0002 -#define pciBASE_CLASS_alt_13__VI 0x0002 -#define pciBASE_CLASS_alt_14__VI 0x0002 -#define pciBASE_CLASS_alt_15__VI 0x0002 -#define pciBASE_CLASS_alt_16__VI 0x0002 -#define pciBASE_CLASS_alt_17__VI 0x0002 -#define pciBASE_CLASS_alt_18__VI 0x0002 -#define pciBASE_CLASS_alt_4__VI 0x0002 -#define pciBASE_CLASS_alt_5__VI 0x0002 -#define pciBASE_CLASS_alt_6__VI 0x0002 -#define pciBASE_CLASS_alt_7__VI 0x0002 -#define pciBASE_CLASS_alt_8__VI 0x0002 -#define pciBASE_CLASS_alt_9__VI 0x0002 -#define pciBIST_alt_10__VI 0x0003 -#define pciBIST_alt_11__VI 0x0003 -#define pciBIST_alt_12__VI 0x0003 -#define pciBIST_alt_13__VI 0x0003 -#define pciBIST_alt_14__VI 0x0003 -#define pciBIST_alt_15__VI 0x0003 -#define pciBIST_alt_16__VI 0x0003 -#define pciBIST_alt_17__VI 0x0003 -#define pciBIST_alt_18__VI 0x0003 -#define pciBIST_alt_4__VI 0x0003 -#define pciBIST_alt_5__VI 0x0003 -#define pciBIST_alt_6__VI 0x0003 -#define pciBIST_alt_7__VI 0x0003 -#define pciBIST_alt_8__VI 0x0003 -#define pciBIST_alt_9__VI 0x0003 -#define pciCACHE_LINE_alt_10__VI 0x0003 -#define pciCACHE_LINE_alt_11__VI 0x0003 -#define pciCACHE_LINE_alt_12__VI 0x0003 -#define pciCACHE_LINE_alt_13__VI 0x0003 -#define pciCACHE_LINE_alt_14__VI 0x0003 -#define pciCACHE_LINE_alt_15__VI 0x0003 -#define pciCACHE_LINE_alt_16__VI 0x0003 -#define pciCACHE_LINE_alt_17__VI 0x0003 -#define pciCACHE_LINE_alt_18__VI 0x0003 -#define pciCACHE_LINE_alt_4__VI 0x0003 -#define pciCACHE_LINE_alt_5__VI 0x0003 -#define pciCACHE_LINE_alt_6__VI 0x0003 -#define pciCACHE_LINE_alt_7__VI 0x0003 -#define pciCACHE_LINE_alt_8__VI 0x0003 -#define pciCACHE_LINE_alt_9__VI 0x0003 -#define pciCAP_PTR_alt_10__VI 0x000D -#define pciCAP_PTR_alt_11__VI 0x000D -#define pciCAP_PTR_alt_12__VI 0x000D -#define pciCAP_PTR_alt_13__VI 0x000D -#define pciCAP_PTR_alt_14__VI 0x000D -#define pciCAP_PTR_alt_15__VI 0x000D -#define pciCAP_PTR_alt_16__VI 0x000D -#define pciCAP_PTR_alt_17__VI 0x000D -#define pciCAP_PTR_alt_18__VI 0x000D -#define pciCAP_PTR_alt_4__VI 0x000D -#define pciCAP_PTR_alt_5__VI 0x000D -#define pciCAP_PTR_alt_6__VI 0x000D -#define pciCAP_PTR_alt_7__VI 0x000D -#define pciCAP_PTR_alt_8__VI 0x000D -#define pciCAP_PTR_alt_9__VI 0x000D -#define pciCOMMAND_alt_10__VI 0x0001 -#define pciCOMMAND_alt_11__VI 0x0001 -#define pciCOMMAND_alt_12__VI 0x0001 -#define pciCOMMAND_alt_13__VI 0x0001 -#define pciCOMMAND_alt_14__VI 0x0001 -#define pciCOMMAND_alt_15__VI 0x0001 -#define pciCOMMAND_alt_16__VI 0x0001 -#define pciCOMMAND_alt_17__VI 0x0001 -#define pciCOMMAND_alt_18__VI 0x0001 -#define pciCOMMAND_alt_4__VI 0x0001 -#define pciCOMMAND_alt_5__VI 0x0001 -#define pciCOMMAND_alt_6__VI 0x0001 -#define pciCOMMAND_alt_7__VI 0x0001 -#define pciCOMMAND_alt_8__VI 0x0001 -#define pciCOMMAND_alt_9__VI 0x0001 -#define pciDEVICE_CAP2_alt_10__VI 0x001F -#define pciDEVICE_CAP2_alt_11__VI 0x001F -#define pciDEVICE_CAP2_alt_12__VI 0x001F -#define pciDEVICE_CAP2_alt_13__VI 0x001F -#define pciDEVICE_CAP2_alt_14__VI 0x001F -#define pciDEVICE_CAP2_alt_15__VI 0x001F -#define pciDEVICE_CAP2_alt_16__VI 0x001F -#define pciDEVICE_CAP2_alt_17__VI 0x001F -#define pciDEVICE_CAP2_alt_18__VI 0x001F -#define pciDEVICE_CAP2_alt_4__VI 0x001F -#define pciDEVICE_CAP2_alt_5__VI 0x001F -#define pciDEVICE_CAP2_alt_6__VI 0x001F -#define pciDEVICE_CAP2_alt_7__VI 0x001F -#define pciDEVICE_CAP2_alt_8__VI 0x001F -#define pciDEVICE_CAP2_alt_9__VI 0x001F -#define pciDEVICE_CAP_alt_10__VI 0x0017 -#define pciDEVICE_CAP_alt_11__VI 0x0017 -#define pciDEVICE_CAP_alt_12__VI 0x0017 -#define pciDEVICE_CAP_alt_13__VI 0x0017 -#define pciDEVICE_CAP_alt_14__VI 0x0017 -#define pciDEVICE_CAP_alt_15__VI 0x0017 -#define pciDEVICE_CAP_alt_16__VI 0x0017 -#define pciDEVICE_CAP_alt_17__VI 0x0017 -#define pciDEVICE_CAP_alt_18__VI 0x0017 -#define pciDEVICE_CAP_alt_4__VI 0x0017 -#define pciDEVICE_CAP_alt_5__VI 0x0017 -#define pciDEVICE_CAP_alt_6__VI 0x0017 -#define pciDEVICE_CAP_alt_7__VI 0x0017 -#define pciDEVICE_CAP_alt_8__VI 0x0017 -#define pciDEVICE_CAP_alt_9__VI 0x0017 -#define pciDEVICE_CNTL2_alt_10__VI 0x0020 -#define pciDEVICE_CNTL2_alt_11__VI 0x0020 -#define pciDEVICE_CNTL2_alt_12__VI 0x0020 -#define pciDEVICE_CNTL2_alt_13__VI 0x0020 -#define pciDEVICE_CNTL2_alt_14__VI 0x0020 -#define pciDEVICE_CNTL2_alt_15__VI 0x0020 -#define pciDEVICE_CNTL2_alt_16__VI 0x0020 -#define pciDEVICE_CNTL2_alt_17__VI 0x0020 -#define pciDEVICE_CNTL2_alt_18__VI 0x0020 -#define pciDEVICE_CNTL2_alt_4__VI 0x0020 -#define pciDEVICE_CNTL2_alt_5__VI 0x0020 -#define pciDEVICE_CNTL2_alt_6__VI 0x0020 -#define pciDEVICE_CNTL2_alt_7__VI 0x0020 -#define pciDEVICE_CNTL2_alt_8__VI 0x0020 -#define pciDEVICE_CNTL2_alt_9__VI 0x0020 -#define pciDEVICE_CNTL_alt_10__VI 0x0018 -#define pciDEVICE_CNTL_alt_11__VI 0x0018 -#define pciDEVICE_CNTL_alt_12__VI 0x0018 -#define pciDEVICE_CNTL_alt_13__VI 0x0018 -#define pciDEVICE_CNTL_alt_14__VI 0x0018 -#define pciDEVICE_CNTL_alt_15__VI 0x0018 -#define pciDEVICE_CNTL_alt_16__VI 0x0018 -#define pciDEVICE_CNTL_alt_17__VI 0x0018 -#define pciDEVICE_CNTL_alt_18__VI 0x0018 -#define pciDEVICE_CNTL_alt_4__VI 0x0018 -#define pciDEVICE_CNTL_alt_5__VI 0x0018 -#define pciDEVICE_CNTL_alt_6__VI 0x0018 -#define pciDEVICE_CNTL_alt_7__VI 0x0018 -#define pciDEVICE_CNTL_alt_8__VI 0x0018 -#define pciDEVICE_CNTL_alt_9__VI 0x0018 -#define pciDEVICE_ID_alt_10__VI 0x0000 -#define pciDEVICE_ID_alt_11__VI 0x0000 -#define pciDEVICE_ID_alt_12__VI 0x0000 -#define pciDEVICE_ID_alt_13__VI 0x0000 -#define pciDEVICE_ID_alt_14__VI 0x0000 -#define pciDEVICE_ID_alt_15__VI 0x0000 -#define pciDEVICE_ID_alt_16__VI 0x0000 -#define pciDEVICE_ID_alt_17__VI 0x0000 -#define pciDEVICE_ID_alt_18__VI 0x0000 -#define pciDEVICE_ID_alt_4__VI 0x0000 -#define pciDEVICE_ID_alt_5__VI 0x0000 -#define pciDEVICE_ID_alt_6__VI 0x0000 -#define pciDEVICE_ID_alt_7__VI 0x0000 -#define pciDEVICE_ID_alt_8__VI 0x0000 -#define pciDEVICE_ID_alt_9__VI 0x0000 -#define pciDEVICE_STATUS2_alt_10__VI 0x0020 -#define pciDEVICE_STATUS2_alt_11__VI 0x0020 -#define pciDEVICE_STATUS2_alt_12__VI 0x0020 -#define pciDEVICE_STATUS2_alt_13__VI 0x0020 -#define pciDEVICE_STATUS2_alt_14__VI 0x0020 -#define pciDEVICE_STATUS2_alt_15__VI 0x0020 -#define pciDEVICE_STATUS2_alt_16__VI 0x0020 -#define pciDEVICE_STATUS2_alt_17__VI 0x0020 -#define pciDEVICE_STATUS2_alt_18__VI 0x0020 -#define pciDEVICE_STATUS2_alt_4__VI 0x0020 -#define pciDEVICE_STATUS2_alt_5__VI 0x0020 -#define pciDEVICE_STATUS2_alt_6__VI 0x0020 -#define pciDEVICE_STATUS2_alt_7__VI 0x0020 -#define pciDEVICE_STATUS2_alt_8__VI 0x0020 -#define pciDEVICE_STATUS2_alt_9__VI 0x0020 -#define pciDEVICE_STATUS_alt_10__VI 0x0018 -#define pciDEVICE_STATUS_alt_11__VI 0x0018 -#define pciDEVICE_STATUS_alt_12__VI 0x0018 -#define pciDEVICE_STATUS_alt_13__VI 0x0018 -#define pciDEVICE_STATUS_alt_14__VI 0x0018 -#define pciDEVICE_STATUS_alt_15__VI 0x0018 -#define pciDEVICE_STATUS_alt_16__VI 0x0018 -#define pciDEVICE_STATUS_alt_17__VI 0x0018 -#define pciDEVICE_STATUS_alt_18__VI 0x0018 -#define pciDEVICE_STATUS_alt_4__VI 0x0018 -#define pciDEVICE_STATUS_alt_5__VI 0x0018 -#define pciDEVICE_STATUS_alt_6__VI 0x0018 -#define pciDEVICE_STATUS_alt_7__VI 0x0018 -#define pciDEVICE_STATUS_alt_8__VI 0x0018 -#define pciDEVICE_STATUS_alt_9__VI 0x0018 -#define pciHEADER_alt_10__VI 0x0003 -#define pciHEADER_alt_11__VI 0x0003 -#define pciHEADER_alt_12__VI 0x0003 -#define pciHEADER_alt_13__VI 0x0003 -#define pciHEADER_alt_14__VI 0x0003 -#define pciHEADER_alt_15__VI 0x0003 -#define pciHEADER_alt_16__VI 0x0003 -#define pciHEADER_alt_17__VI 0x0003 -#define pciHEADER_alt_18__VI 0x0003 -#define pciHEADER_alt_4__VI 0x0003 -#define pciHEADER_alt_5__VI 0x0003 -#define pciHEADER_alt_6__VI 0x0003 -#define pciHEADER_alt_7__VI 0x0003 -#define pciHEADER_alt_8__VI 0x0003 -#define pciHEADER_alt_9__VI 0x0003 -#define pciINTERRUPT_LINE_alt_10__VI 0x000F -#define pciINTERRUPT_LINE_alt_11__VI 0x000F -#define pciINTERRUPT_LINE_alt_12__VI 0x000F -#define pciINTERRUPT_LINE_alt_13__VI 0x000F -#define pciINTERRUPT_LINE_alt_14__VI 0x000F -#define pciINTERRUPT_LINE_alt_15__VI 0x000F -#define pciINTERRUPT_LINE_alt_16__VI 0x000F -#define pciINTERRUPT_LINE_alt_17__VI 0x000F -#define pciINTERRUPT_LINE_alt_18__VI 0x000F -#define pciINTERRUPT_LINE_alt_4__VI 0x000F -#define pciINTERRUPT_LINE_alt_5__VI 0x000F -#define pciINTERRUPT_LINE_alt_6__VI 0x000F -#define pciINTERRUPT_LINE_alt_7__VI 0x000F -#define pciINTERRUPT_LINE_alt_8__VI 0x000F -#define pciINTERRUPT_LINE_alt_9__VI 0x000F -#define pciINTERRUPT_PIN_alt_10__VI 0x000F -#define pciINTERRUPT_PIN_alt_11__VI 0x000F -#define pciINTERRUPT_PIN_alt_12__VI 0x000F -#define pciINTERRUPT_PIN_alt_13__VI 0x000F -#define pciINTERRUPT_PIN_alt_14__VI 0x000F -#define pciINTERRUPT_PIN_alt_15__VI 0x000F -#define pciINTERRUPT_PIN_alt_16__VI 0x000F -#define pciINTERRUPT_PIN_alt_17__VI 0x000F -#define pciINTERRUPT_PIN_alt_18__VI 0x000F -#define pciINTERRUPT_PIN_alt_4__VI 0x000F -#define pciINTERRUPT_PIN_alt_5__VI 0x000F -#define pciINTERRUPT_PIN_alt_6__VI 0x000F -#define pciINTERRUPT_PIN_alt_7__VI 0x000F -#define pciINTERRUPT_PIN_alt_8__VI 0x000F -#define pciINTERRUPT_PIN_alt_9__VI 0x000F -#define pciLATENCY_alt_10__VI 0x0003 -#define pciLATENCY_alt_11__VI 0x0003 -#define pciLATENCY_alt_12__VI 0x0003 -#define pciLATENCY_alt_13__VI 0x0003 -#define pciLATENCY_alt_14__VI 0x0003 -#define pciLATENCY_alt_15__VI 0x0003 -#define pciLATENCY_alt_16__VI 0x0003 -#define pciLATENCY_alt_17__VI 0x0003 -#define pciLATENCY_alt_18__VI 0x0003 -#define pciLATENCY_alt_4__VI 0x0003 -#define pciLATENCY_alt_5__VI 0x0003 -#define pciLATENCY_alt_6__VI 0x0003 -#define pciLATENCY_alt_7__VI 0x0003 -#define pciLATENCY_alt_8__VI 0x0003 -#define pciLATENCY_alt_9__VI 0x0003 -#define pciLINK_CAP2_alt_10__VI 0x0021 -#define pciLINK_CAP2_alt_11__VI 0x0021 -#define pciLINK_CAP2_alt_12__VI 0x0021 -#define pciLINK_CAP2_alt_13__VI 0x0021 -#define pciLINK_CAP2_alt_14__VI 0x0021 -#define pciLINK_CAP2_alt_15__VI 0x0021 -#define pciLINK_CAP2_alt_16__VI 0x0021 -#define pciLINK_CAP2_alt_17__VI 0x0021 -#define pciLINK_CAP2_alt_18__VI 0x0021 -#define pciLINK_CAP2_alt_4__VI 0x0021 -#define pciLINK_CAP2_alt_5__VI 0x0021 -#define pciLINK_CAP2_alt_6__VI 0x0021 -#define pciLINK_CAP2_alt_7__VI 0x0021 -#define pciLINK_CAP2_alt_8__VI 0x0021 -#define pciLINK_CAP2_alt_9__VI 0x0021 -#define pciLINK_CAP_alt_10__VI 0x0019 -#define pciLINK_CAP_alt_11__VI 0x0019 -#define pciLINK_CAP_alt_12__VI 0x0019 -#define pciLINK_CAP_alt_13__VI 0x0019 -#define pciLINK_CAP_alt_14__VI 0x0019 -#define pciLINK_CAP_alt_15__VI 0x0019 -#define pciLINK_CAP_alt_16__VI 0x0019 -#define pciLINK_CAP_alt_17__VI 0x0019 -#define pciLINK_CAP_alt_18__VI 0x0019 -#define pciLINK_CAP_alt_4__VI 0x0019 -#define pciLINK_CAP_alt_5__VI 0x0019 -#define pciLINK_CAP_alt_6__VI 0x0019 -#define pciLINK_CAP_alt_7__VI 0x0019 -#define pciLINK_CAP_alt_8__VI 0x0019 -#define pciLINK_CAP_alt_9__VI 0x0019 -#define pciLINK_CNTL2_alt_10__VI 0x0022 -#define pciLINK_CNTL2_alt_11__VI 0x0022 -#define pciLINK_CNTL2_alt_12__VI 0x0022 -#define pciLINK_CNTL2_alt_13__VI 0x0022 -#define pciLINK_CNTL2_alt_14__VI 0x0022 -#define pciLINK_CNTL2_alt_15__VI 0x0022 -#define pciLINK_CNTL2_alt_16__VI 0x0022 -#define pciLINK_CNTL2_alt_17__VI 0x0022 -#define pciLINK_CNTL2_alt_18__VI 0x0022 -#define pciLINK_CNTL2_alt_4__VI 0x0022 -#define pciLINK_CNTL2_alt_5__VI 0x0022 -#define pciLINK_CNTL2_alt_6__VI 0x0022 -#define pciLINK_CNTL2_alt_7__VI 0x0022 -#define pciLINK_CNTL2_alt_8__VI 0x0022 -#define pciLINK_CNTL2_alt_9__VI 0x0022 -#define pciLINK_CNTL_alt_10__VI 0x001A -#define pciLINK_CNTL_alt_11__VI 0x001A -#define pciLINK_CNTL_alt_12__VI 0x001A -#define pciLINK_CNTL_alt_13__VI 0x001A -#define pciLINK_CNTL_alt_14__VI 0x001A -#define pciLINK_CNTL_alt_15__VI 0x001A -#define pciLINK_CNTL_alt_16__VI 0x001A -#define pciLINK_CNTL_alt_17__VI 0x001A -#define pciLINK_CNTL_alt_18__VI 0x001A -#define pciLINK_CNTL_alt_4__VI 0x001A -#define pciLINK_CNTL_alt_5__VI 0x001A -#define pciLINK_CNTL_alt_6__VI 0x001A -#define pciLINK_CNTL_alt_7__VI 0x001A -#define pciLINK_CNTL_alt_8__VI 0x001A -#define pciLINK_CNTL_alt_9__VI 0x001A -#define pciLINK_STATUS2_alt_10__VI 0x0022 -#define pciLINK_STATUS2_alt_11__VI 0x0022 -#define pciLINK_STATUS2_alt_12__VI 0x0022 -#define pciLINK_STATUS2_alt_13__VI 0x0022 -#define pciLINK_STATUS2_alt_14__VI 0x0022 -#define pciLINK_STATUS2_alt_15__VI 0x0022 -#define pciLINK_STATUS2_alt_16__VI 0x0022 -#define pciLINK_STATUS2_alt_17__VI 0x0022 -#define pciLINK_STATUS2_alt_18__VI 0x0022 -#define pciLINK_STATUS2_alt_4__VI 0x0022 -#define pciLINK_STATUS2_alt_5__VI 0x0022 -#define pciLINK_STATUS2_alt_6__VI 0x0022 -#define pciLINK_STATUS2_alt_7__VI 0x0022 -#define pciLINK_STATUS2_alt_8__VI 0x0022 -#define pciLINK_STATUS2_alt_9__VI 0x0022 -#define pciLINK_STATUS_alt_10__VI 0x001A -#define pciLINK_STATUS_alt_11__VI 0x001A -#define pciLINK_STATUS_alt_12__VI 0x001A -#define pciLINK_STATUS_alt_13__VI 0x001A -#define pciLINK_STATUS_alt_14__VI 0x001A -#define pciLINK_STATUS_alt_15__VI 0x001A -#define pciLINK_STATUS_alt_16__VI 0x001A -#define pciLINK_STATUS_alt_17__VI 0x001A -#define pciLINK_STATUS_alt_18__VI 0x001A -#define pciLINK_STATUS_alt_4__VI 0x001A -#define pciLINK_STATUS_alt_5__VI 0x001A -#define pciLINK_STATUS_alt_6__VI 0x001A -#define pciLINK_STATUS_alt_7__VI 0x001A -#define pciLINK_STATUS_alt_8__VI 0x001A -#define pciLINK_STATUS_alt_9__VI 0x001A -#define pciMAX_LATENCY_alt_10__VI 0x000F -#define pciMAX_LATENCY_alt_11__VI 0x000F -#define pciMAX_LATENCY_alt_12__VI 0x000F -#define pciMAX_LATENCY_alt_13__VI 0x000F -#define pciMAX_LATENCY_alt_14__VI 0x000F -#define pciMAX_LATENCY_alt_15__VI 0x000F -#define pciMAX_LATENCY_alt_16__VI 0x000F -#define pciMAX_LATENCY_alt_17__VI 0x000F -#define pciMAX_LATENCY_alt_18__VI 0x000F -#define pciMAX_LATENCY_alt_4__VI 0x000F -#define pciMAX_LATENCY_alt_5__VI 0x000F -#define pciMAX_LATENCY_alt_6__VI 0x000F -#define pciMAX_LATENCY_alt_7__VI 0x000F -#define pciMAX_LATENCY_alt_8__VI 0x000F -#define pciMAX_LATENCY_alt_9__VI 0x000F -#define pciMIN_GRANT_alt_10__VI 0x000F -#define pciMIN_GRANT_alt_11__VI 0x000F -#define pciMIN_GRANT_alt_12__VI 0x000F -#define pciMIN_GRANT_alt_13__VI 0x000F -#define pciMIN_GRANT_alt_14__VI 0x000F -#define pciMIN_GRANT_alt_15__VI 0x000F -#define pciMIN_GRANT_alt_16__VI 0x000F -#define pciMIN_GRANT_alt_17__VI 0x000F -#define pciMIN_GRANT_alt_18__VI 0x000F -#define pciMIN_GRANT_alt_4__VI 0x000F -#define pciMIN_GRANT_alt_5__VI 0x000F -#define pciMIN_GRANT_alt_6__VI 0x000F -#define pciMIN_GRANT_alt_7__VI 0x000F -#define pciMIN_GRANT_alt_8__VI 0x000F -#define pciMIN_GRANT_alt_9__VI 0x000F -#define pciMSI_CAP_LIST_alt_10__VI 0x0028 -#define pciMSI_CAP_LIST_alt_11__VI 0x0028 -#define pciMSI_CAP_LIST_alt_12__VI 0x0028 -#define pciMSI_CAP_LIST_alt_13__VI 0x0028 -#define pciMSI_CAP_LIST_alt_14__VI 0x0028 -#define pciMSI_CAP_LIST_alt_15__VI 0x0028 -#define pciMSI_CAP_LIST_alt_16__VI 0x0028 -#define pciMSI_CAP_LIST_alt_17__VI 0x0028 -#define pciMSI_CAP_LIST_alt_18__VI 0x0028 -#define pciMSI_CAP_LIST_alt_4__VI 0x0028 -#define pciMSI_CAP_LIST_alt_5__VI 0x0028 -#define pciMSI_CAP_LIST_alt_6__VI 0x0028 -#define pciMSI_CAP_LIST_alt_7__VI 0x0028 -#define pciMSI_CAP_LIST_alt_8__VI 0x0028 -#define pciMSI_CAP_LIST_alt_9__VI 0x0028 -#define pciMSI_MASK__VI 0x002B -#define pciMSI_MASK_64__VI 0x002C -#define pciMSI_MASK_64_alt_1__VI 0x002C -#define pciMSI_MASK_64_alt_10__VI 0x002C -#define pciMSI_MASK_64_alt_11__VI 0x002C -#define pciMSI_MASK_64_alt_12__VI 0x002C -#define pciMSI_MASK_64_alt_13__VI 0x002C -#define pciMSI_MASK_64_alt_14__VI 0x002C -#define pciMSI_MASK_64_alt_15__VI 0x002C -#define pciMSI_MASK_64_alt_16__VI 0x002C -#define pciMSI_MASK_64_alt_17__VI 0x002C -#define pciMSI_MASK_64_alt_18__VI 0x002C -#define pciMSI_MASK_64_alt_2__VI 0x002C -#define pciMSI_MASK_64_alt_3__VI 0x002C -#define pciMSI_MASK_64_alt_4__VI 0x002C -#define pciMSI_MASK_64_alt_5__VI 0x002C -#define pciMSI_MASK_64_alt_6__VI 0x002C -#define pciMSI_MASK_64_alt_7__VI 0x002C -#define pciMSI_MASK_64_alt_8__VI 0x002C -#define pciMSI_MASK_64_alt_9__VI 0x002C -#define pciMSI_MASK_alt_1__VI 0x002B -#define pciMSI_MASK_alt_10__VI 0x002B -#define pciMSI_MASK_alt_11__VI 0x002B -#define pciMSI_MASK_alt_12__VI 0x002B -#define pciMSI_MASK_alt_13__VI 0x002B -#define pciMSI_MASK_alt_14__VI 0x002B -#define pciMSI_MASK_alt_15__VI 0x002B -#define pciMSI_MASK_alt_16__VI 0x002B -#define pciMSI_MASK_alt_17__VI 0x002B -#define pciMSI_MASK_alt_18__VI 0x002B -#define pciMSI_MASK_alt_2__VI 0x002B -#define pciMSI_MASK_alt_3__VI 0x002B -#define pciMSI_MASK_alt_4__VI 0x002B -#define pciMSI_MASK_alt_5__VI 0x002B -#define pciMSI_MASK_alt_6__VI 0x002B -#define pciMSI_MASK_alt_7__VI 0x002B -#define pciMSI_MASK_alt_8__VI 0x002B -#define pciMSI_MASK_alt_9__VI 0x002B -#define pciMSI_MSG_ADDR_HI_alt_10__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_11__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_12__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_13__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_14__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_15__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_16__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_17__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_18__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_4__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_5__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_6__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_7__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_8__VI 0x002A -#define pciMSI_MSG_ADDR_HI_alt_9__VI 0x002A -#define pciMSI_MSG_ADDR_LO_alt_10__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_11__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_12__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_13__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_14__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_15__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_16__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_17__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_18__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_4__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_5__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_6__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_7__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_8__VI 0x0029 -#define pciMSI_MSG_ADDR_LO_alt_9__VI 0x0029 -#define pciMSI_MSG_CNTL_alt_10__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_11__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_12__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_13__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_14__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_15__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_16__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_17__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_18__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_4__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_5__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_6__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_7__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_8__VI 0x0028 -#define pciMSI_MSG_CNTL_alt_9__VI 0x0028 -#define pciMSI_MSG_DATA_64_alt_10__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_11__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_12__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_13__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_14__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_15__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_16__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_17__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_18__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_4__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_5__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_6__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_7__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_8__VI 0x002B -#define pciMSI_MSG_DATA_64_alt_9__VI 0x002B -#define pciMSI_MSG_DATA_alt_10__VI 0x002A -#define pciMSI_MSG_DATA_alt_11__VI 0x002A -#define pciMSI_MSG_DATA_alt_12__VI 0x002A -#define pciMSI_MSG_DATA_alt_13__VI 0x002A -#define pciMSI_MSG_DATA_alt_14__VI 0x002A -#define pciMSI_MSG_DATA_alt_15__VI 0x002A -#define pciMSI_MSG_DATA_alt_16__VI 0x002A -#define pciMSI_MSG_DATA_alt_17__VI 0x002A -#define pciMSI_MSG_DATA_alt_18__VI 0x002A -#define pciMSI_MSG_DATA_alt_4__VI 0x002A -#define pciMSI_MSG_DATA_alt_5__VI 0x002A -#define pciMSI_MSG_DATA_alt_6__VI 0x002A -#define pciMSI_MSG_DATA_alt_7__VI 0x002A -#define pciMSI_MSG_DATA_alt_8__VI 0x002A -#define pciMSI_MSG_DATA_alt_9__VI 0x002A -#define pciMSI_PENDING__VI 0x002C -#define pciMSI_PENDING_64__VI 0x002D -#define pciMSI_PENDING_64_alt_1__VI 0x002D -#define pciMSI_PENDING_64_alt_10__VI 0x002D -#define pciMSI_PENDING_64_alt_11__VI 0x002D -#define pciMSI_PENDING_64_alt_12__VI 0x002D -#define pciMSI_PENDING_64_alt_13__VI 0x002D -#define pciMSI_PENDING_64_alt_14__VI 0x002D -#define pciMSI_PENDING_64_alt_15__VI 0x002D -#define pciMSI_PENDING_64_alt_16__VI 0x002D -#define pciMSI_PENDING_64_alt_17__VI 0x002D -#define pciMSI_PENDING_64_alt_18__VI 0x002D -#define pciMSI_PENDING_64_alt_2__VI 0x002D -#define pciMSI_PENDING_64_alt_3__VI 0x002D -#define pciMSI_PENDING_64_alt_4__VI 0x002D -#define pciMSI_PENDING_64_alt_5__VI 0x002D -#define pciMSI_PENDING_64_alt_6__VI 0x002D -#define pciMSI_PENDING_64_alt_7__VI 0x002D -#define pciMSI_PENDING_64_alt_8__VI 0x002D -#define pciMSI_PENDING_64_alt_9__VI 0x002D -#define pciMSI_PENDING_alt_1__VI 0x002C -#define pciMSI_PENDING_alt_10__VI 0x002C -#define pciMSI_PENDING_alt_11__VI 0x002C -#define pciMSI_PENDING_alt_12__VI 0x002C -#define pciMSI_PENDING_alt_13__VI 0x002C -#define pciMSI_PENDING_alt_14__VI 0x002C -#define pciMSI_PENDING_alt_15__VI 0x002C -#define pciMSI_PENDING_alt_16__VI 0x002C -#define pciMSI_PENDING_alt_17__VI 0x002C -#define pciMSI_PENDING_alt_18__VI 0x002C -#define pciMSI_PENDING_alt_2__VI 0x002C -#define pciMSI_PENDING_alt_3__VI 0x002C -#define pciMSI_PENDING_alt_4__VI 0x002C -#define pciMSI_PENDING_alt_5__VI 0x002C -#define pciMSI_PENDING_alt_6__VI 0x002C -#define pciMSI_PENDING_alt_7__VI 0x002C -#define pciMSI_PENDING_alt_8__VI 0x002C -#define pciMSI_PENDING_alt_9__VI 0x002C -#define pciPCIE_ACS_CAP_alt_10__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_11__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_12__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_13__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_14__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_15__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_16__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_17__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_18__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_4__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_5__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_6__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_7__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_8__VI 0x00A9 -#define pciPCIE_ACS_CAP_alt_9__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_10__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_11__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_12__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_13__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_14__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_15__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_16__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_17__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_18__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_4__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_5__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_6__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_7__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_8__VI 0x00A9 -#define pciPCIE_ACS_CNTL_alt_9__VI 0x00A9 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_10__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_11__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_12__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_13__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_14__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_15__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_16__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_17__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_18__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_4__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_5__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_6__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_7__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_8__VI 0x00A8 -#define pciPCIE_ACS_ENH_CAP_LIST_alt_9__VI 0x00A8 -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_10__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_11__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_12__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_13__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_14__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_15__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_16__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_17__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_18__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_4__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_5__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_6__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_7__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_8__VI 0x005A -#define pciPCIE_ADV_ERR_CAP_CNTL_alt_9__VI 0x005A -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_10__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_11__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_12__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_13__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_14__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_15__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_16__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_17__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_18__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_4__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_5__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_6__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_7__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_8__VI 0x0054 -#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST_alt_9__VI 0x0054 -#define pciPCIE_ARI_CAP__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_1__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_10__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_11__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_12__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_13__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_14__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_15__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_16__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_17__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_18__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_2__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_3__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_4__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_5__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_6__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_7__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_8__VI 0x00CB -#define pciPCIE_ARI_CAP_alt_9__VI 0x00CB -#define pciPCIE_ARI_CNTL__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_1__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_10__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_11__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_12__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_13__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_14__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_15__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_16__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_17__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_18__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_2__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_3__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_4__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_5__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_6__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_7__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_8__VI 0x00CB -#define pciPCIE_ARI_CNTL_alt_9__VI 0x00CB -#define pciPCIE_ARI_ENH_CAP_LIST__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_1__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_10__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_11__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_12__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_13__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_14__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_15__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_16__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_17__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_18__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_2__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_3__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_4__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_5__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_6__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_7__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_8__VI 0x00CA -#define pciPCIE_ARI_ENH_CAP_LIST_alt_9__VI 0x00CA -#define pciPCIE_ATS_CAP_alt_10__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_11__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_12__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_13__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_14__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_15__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_16__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_17__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_18__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_4__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_5__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_6__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_7__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_8__VI 0x00AD -#define pciPCIE_ATS_CAP_alt_9__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_10__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_11__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_12__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_13__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_14__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_15__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_16__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_17__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_18__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_4__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_5__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_6__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_7__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_8__VI 0x00AD -#define pciPCIE_ATS_CNTL_alt_9__VI 0x00AD -#define pciPCIE_ATS_ENH_CAP_LIST_alt_10__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_11__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_12__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_13__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_14__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_15__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_16__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_17__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_18__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_4__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_5__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_6__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_7__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_8__VI 0x00AC -#define pciPCIE_ATS_ENH_CAP_LIST_alt_9__VI 0x00AC -#define pciPCIE_BAR1_CAP_alt_10__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_11__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_12__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_13__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_14__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_15__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_16__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_17__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_18__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_4__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_5__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_6__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_7__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_8__VI 0x0081 -#define pciPCIE_BAR1_CAP_alt_9__VI 0x0081 -#define pciPCIE_BAR1_CNTL_alt_10__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_11__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_12__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_13__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_14__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_15__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_16__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_17__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_18__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_4__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_5__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_6__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_7__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_8__VI 0x0082 -#define pciPCIE_BAR1_CNTL_alt_9__VI 0x0082 -#define pciPCIE_BAR2_CAP_alt_10__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_11__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_12__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_13__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_14__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_15__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_16__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_17__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_18__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_4__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_5__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_6__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_7__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_8__VI 0x0083 -#define pciPCIE_BAR2_CAP_alt_9__VI 0x0083 -#define pciPCIE_BAR2_CNTL_alt_10__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_11__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_12__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_13__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_14__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_15__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_16__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_17__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_18__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_4__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_5__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_6__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_7__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_8__VI 0x0084 -#define pciPCIE_BAR2_CNTL_alt_9__VI 0x0084 -#define pciPCIE_BAR3_CAP_alt_10__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_11__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_12__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_13__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_14__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_15__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_16__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_17__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_18__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_4__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_5__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_6__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_7__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_8__VI 0x0085 -#define pciPCIE_BAR3_CAP_alt_9__VI 0x0085 -#define pciPCIE_BAR3_CNTL_alt_10__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_11__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_12__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_13__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_14__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_15__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_16__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_17__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_18__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_4__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_5__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_6__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_7__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_8__VI 0x0086 -#define pciPCIE_BAR3_CNTL_alt_9__VI 0x0086 -#define pciPCIE_BAR4_CAP_alt_10__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_11__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_12__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_13__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_14__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_15__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_16__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_17__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_18__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_4__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_5__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_6__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_7__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_8__VI 0x0087 -#define pciPCIE_BAR4_CAP_alt_9__VI 0x0087 -#define pciPCIE_BAR4_CNTL_alt_10__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_11__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_12__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_13__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_14__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_15__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_16__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_17__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_18__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_4__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_5__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_6__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_7__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_8__VI 0x0088 -#define pciPCIE_BAR4_CNTL_alt_9__VI 0x0088 -#define pciPCIE_BAR5_CAP_alt_10__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_11__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_12__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_13__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_14__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_15__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_16__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_17__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_18__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_4__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_5__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_6__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_7__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_8__VI 0x0089 -#define pciPCIE_BAR5_CAP_alt_9__VI 0x0089 -#define pciPCIE_BAR5_CNTL_alt_10__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_11__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_12__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_13__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_14__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_15__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_16__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_17__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_18__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_4__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_5__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_6__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_7__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_8__VI 0x008A -#define pciPCIE_BAR5_CNTL_alt_9__VI 0x008A -#define pciPCIE_BAR6_CAP_alt_10__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_11__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_12__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_13__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_14__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_15__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_16__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_17__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_18__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_4__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_5__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_6__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_7__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_8__VI 0x008B -#define pciPCIE_BAR6_CAP_alt_9__VI 0x008B -#define pciPCIE_BAR6_CNTL_alt_10__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_11__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_12__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_13__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_14__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_15__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_16__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_17__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_18__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_4__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_5__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_6__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_7__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_8__VI 0x008C -#define pciPCIE_BAR6_CNTL_alt_9__VI 0x008C -#define pciPCIE_BAR_ENH_CAP_LIST_alt_10__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_11__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_12__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_13__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_14__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_15__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_16__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_17__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_18__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_4__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_5__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_6__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_7__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_8__VI 0x0080 -#define pciPCIE_BAR_ENH_CAP_LIST_alt_9__VI 0x0080 -#define pciPCIE_CAP_LIST_alt_10__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_11__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_12__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_13__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_14__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_15__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_16__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_17__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_18__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_4__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_5__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_6__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_7__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_8__VI 0x0016 -#define pciPCIE_CAP_LIST_alt_9__VI 0x0016 -#define pciPCIE_CAP_alt_10__VI 0x0016 -#define pciPCIE_CAP_alt_11__VI 0x0016 -#define pciPCIE_CAP_alt_12__VI 0x0016 -#define pciPCIE_CAP_alt_13__VI 0x0016 -#define pciPCIE_CAP_alt_14__VI 0x0016 -#define pciPCIE_CAP_alt_15__VI 0x0016 -#define pciPCIE_CAP_alt_16__VI 0x0016 -#define pciPCIE_CAP_alt_17__VI 0x0016 -#define pciPCIE_CAP_alt_18__VI 0x0016 -#define pciPCIE_CAP_alt_4__VI 0x0016 -#define pciPCIE_CAP_alt_5__VI 0x0016 -#define pciPCIE_CAP_alt_6__VI 0x0016 -#define pciPCIE_CAP_alt_7__VI 0x0016 -#define pciPCIE_CAP_alt_8__VI 0x0016 -#define pciPCIE_CAP_alt_9__VI 0x0016 -#define pciPCIE_CORR_ERR_MASK_alt_10__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_11__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_12__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_13__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_14__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_15__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_16__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_17__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_18__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_4__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_5__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_6__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_7__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_8__VI 0x0059 -#define pciPCIE_CORR_ERR_MASK_alt_9__VI 0x0059 -#define pciPCIE_CORR_ERR_STATUS_alt_10__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_11__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_12__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_13__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_14__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_15__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_16__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_17__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_18__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_4__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_5__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_6__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_7__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_8__VI 0x0058 -#define pciPCIE_CORR_ERR_STATUS_alt_9__VI 0x0058 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_10__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_11__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_12__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_13__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_14__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_15__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_16__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_17__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_18__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_4__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_5__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_6__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_7__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_8__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW1_alt_9__VI 0x0051 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_10__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_11__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_12__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_13__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_14__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_15__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_16__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_17__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_18__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_4__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_5__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_6__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_7__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_8__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_DW2_alt_9__VI 0x0052 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_10__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_11__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_12__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_13__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_14__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_15__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_16__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_17__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_18__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_4__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_5__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_6__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_7__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_8__VI 0x0050 -#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_alt_9__VI 0x0050 -#define pciPCIE_DPA_CAP_alt_10__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_11__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_12__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_13__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_14__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_15__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_16__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_17__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_18__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_4__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_5__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_6__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_7__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_8__VI 0x0095 -#define pciPCIE_DPA_CAP_alt_9__VI 0x0095 -#define pciPCIE_DPA_CNTL_alt_10__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_11__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_12__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_13__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_14__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_15__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_16__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_17__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_18__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_4__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_5__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_6__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_7__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_8__VI 0x0097 -#define pciPCIE_DPA_CNTL_alt_9__VI 0x0097 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_10__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_11__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_12__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_13__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_14__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_15__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_16__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_17__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_18__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_4__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_5__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_6__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_7__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_8__VI 0x0094 -#define pciPCIE_DPA_ENH_CAP_LIST_alt_9__VI 0x0094 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_10__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_11__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_12__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_13__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_14__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_15__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_16__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_17__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_18__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_4__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_5__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_6__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_7__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_8__VI 0x0096 -#define pciPCIE_DPA_LATENCY_INDICATOR_alt_9__VI 0x0096 -#define pciPCIE_DPA_STATUS_alt_10__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_11__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_12__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_13__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_14__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_15__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_16__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_17__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_18__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_4__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_5__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_6__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_7__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_8__VI 0x0097 -#define pciPCIE_DPA_STATUS_alt_9__VI 0x0097 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_10__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_11__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_12__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_13__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_14__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_15__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_16__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_17__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_18__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_4__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_5__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_6__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_7__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_8__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0_alt_9__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_10__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_11__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_12__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_13__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_14__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_15__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_16__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_17__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_18__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_4__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_5__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_6__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_7__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_8__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1_alt_9__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_10__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_11__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_12__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_13__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_14__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_15__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_16__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_17__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_18__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_4__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_5__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_6__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_7__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_8__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2_alt_9__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_10__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_11__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_12__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_13__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_14__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_15__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_16__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_17__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_18__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_4__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_5__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_6__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_7__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_8__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3_alt_9__VI 0x0098 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_10__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_11__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_12__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_13__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_14__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_15__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_16__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_17__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_18__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_4__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_5__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_6__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_7__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_8__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4_alt_9__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_10__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_11__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_12__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_13__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_14__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_15__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_16__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_17__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_18__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_4__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_5__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_6__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_7__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_8__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5_alt_9__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_10__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_11__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_12__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_13__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_14__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_15__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_16__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_17__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_18__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_4__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_5__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_6__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_7__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_8__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6_alt_9__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_10__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_11__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_12__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_13__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_14__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_15__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_16__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_17__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_18__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_4__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_5__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_6__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_7__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_8__VI 0x0099 -#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7_alt_9__VI 0x0099 -#define pciPCIE_HDR_LOG0_alt_10__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_11__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_12__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_13__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_14__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_15__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_16__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_17__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_18__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_4__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_5__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_6__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_7__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_8__VI 0x005B -#define pciPCIE_HDR_LOG0_alt_9__VI 0x005B -#define pciPCIE_HDR_LOG1_alt_10__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_11__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_12__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_13__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_14__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_15__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_16__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_17__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_18__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_4__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_5__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_6__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_7__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_8__VI 0x005C -#define pciPCIE_HDR_LOG1_alt_9__VI 0x005C -#define pciPCIE_HDR_LOG2_alt_10__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_11__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_12__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_13__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_14__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_15__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_16__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_17__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_18__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_4__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_5__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_6__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_7__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_8__VI 0x005D -#define pciPCIE_HDR_LOG2_alt_9__VI 0x005D -#define pciPCIE_HDR_LOG3_alt_10__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_11__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_12__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_13__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_14__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_15__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_16__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_17__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_18__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_4__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_5__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_6__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_7__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_8__VI 0x005E -#define pciPCIE_HDR_LOG3_alt_9__VI 0x005E -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_10__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_11__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_12__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_13__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_14__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_15__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_16__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_17__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_18__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_4__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_5__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_6__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_7__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_8__VI 0x009F -#define pciPCIE_LANE_0_EQUALIZATION_CNTL_alt_9__VI 0x009F -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_10__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_11__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_12__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_13__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_14__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_15__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_16__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_17__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_18__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_4__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_5__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_6__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_7__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_8__VI 0x00A4 -#define pciPCIE_LANE_10_EQUALIZATION_CNTL_alt_9__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_10__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_11__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_12__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_13__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_14__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_15__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_16__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_17__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_18__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_4__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_5__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_6__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_7__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_8__VI 0x00A4 -#define pciPCIE_LANE_11_EQUALIZATION_CNTL_alt_9__VI 0x00A4 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_10__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_11__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_12__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_13__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_14__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_15__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_16__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_17__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_18__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_4__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_5__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_6__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_7__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_8__VI 0x00A5 -#define pciPCIE_LANE_12_EQUALIZATION_CNTL_alt_9__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_10__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_11__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_12__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_13__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_14__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_15__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_16__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_17__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_18__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_4__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_5__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_6__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_7__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_8__VI 0x00A5 -#define pciPCIE_LANE_13_EQUALIZATION_CNTL_alt_9__VI 0x00A5 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_10__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_11__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_12__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_13__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_14__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_15__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_16__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_17__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_18__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_4__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_5__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_6__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_7__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_8__VI 0x00A6 -#define pciPCIE_LANE_14_EQUALIZATION_CNTL_alt_9__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_10__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_11__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_12__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_13__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_14__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_15__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_16__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_17__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_18__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_4__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_5__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_6__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_7__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_8__VI 0x00A6 -#define pciPCIE_LANE_15_EQUALIZATION_CNTL_alt_9__VI 0x00A6 -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_10__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_11__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_12__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_13__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_14__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_15__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_16__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_17__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_18__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_4__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_5__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_6__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_7__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_8__VI 0x009F -#define pciPCIE_LANE_1_EQUALIZATION_CNTL_alt_9__VI 0x009F -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_10__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_11__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_12__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_13__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_14__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_15__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_16__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_17__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_18__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_4__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_5__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_6__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_7__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_8__VI 0x00A0 -#define pciPCIE_LANE_2_EQUALIZATION_CNTL_alt_9__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_10__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_11__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_12__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_13__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_14__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_15__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_16__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_17__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_18__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_4__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_5__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_6__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_7__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_8__VI 0x00A0 -#define pciPCIE_LANE_3_EQUALIZATION_CNTL_alt_9__VI 0x00A0 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_10__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_11__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_12__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_13__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_14__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_15__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_16__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_17__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_18__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_4__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_5__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_6__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_7__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_8__VI 0x00A1 -#define pciPCIE_LANE_4_EQUALIZATION_CNTL_alt_9__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_10__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_11__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_12__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_13__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_14__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_15__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_16__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_17__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_18__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_4__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_5__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_6__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_7__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_8__VI 0x00A1 -#define pciPCIE_LANE_5_EQUALIZATION_CNTL_alt_9__VI 0x00A1 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_10__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_11__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_12__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_13__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_14__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_15__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_16__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_17__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_18__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_4__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_5__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_6__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_7__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_8__VI 0x00A2 -#define pciPCIE_LANE_6_EQUALIZATION_CNTL_alt_9__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_10__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_11__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_12__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_13__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_14__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_15__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_16__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_17__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_18__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_4__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_5__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_6__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_7__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_8__VI 0x00A2 -#define pciPCIE_LANE_7_EQUALIZATION_CNTL_alt_9__VI 0x00A2 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_10__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_11__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_12__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_13__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_14__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_15__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_16__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_17__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_18__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_4__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_5__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_6__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_7__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_8__VI 0x00A3 -#define pciPCIE_LANE_8_EQUALIZATION_CNTL_alt_9__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_10__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_11__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_12__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_13__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_14__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_15__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_16__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_17__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_18__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_4__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_5__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_6__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_7__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_8__VI 0x00A3 -#define pciPCIE_LANE_9_EQUALIZATION_CNTL_alt_9__VI 0x00A3 -#define pciPCIE_LANE_ERROR_STATUS_alt_10__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_11__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_12__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_13__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_14__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_15__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_16__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_17__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_18__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_4__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_5__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_6__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_7__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_8__VI 0x009E -#define pciPCIE_LANE_ERROR_STATUS_alt_9__VI 0x009E -#define pciPCIE_LINK_CNTL3_alt_10__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_11__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_12__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_13__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_14__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_15__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_16__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_17__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_18__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_4__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_5__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_6__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_7__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_8__VI 0x009D -#define pciPCIE_LINK_CNTL3_alt_9__VI 0x009D -#define pciPCIE_LTR_CAP__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_1__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_10__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_11__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_12__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_13__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_14__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_15__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_16__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_17__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_18__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_2__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_3__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_4__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_5__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_6__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_7__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_8__VI 0x00C9 -#define pciPCIE_LTR_CAP_alt_9__VI 0x00C9 -#define pciPCIE_LTR_ENH_CAP_LIST__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_1__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_10__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_11__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_12__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_13__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_14__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_15__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_16__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_17__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_18__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_2__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_3__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_4__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_5__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_6__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_7__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_8__VI 0x00C8 -#define pciPCIE_LTR_ENH_CAP_LIST_alt_9__VI 0x00C8 -#define pciPCIE_MC_ADDR0__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_1__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_10__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_11__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_12__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_13__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_14__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_15__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_16__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_17__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_18__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_2__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_3__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_4__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_5__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_6__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_7__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_8__VI 0x00BE -#define pciPCIE_MC_ADDR0_alt_9__VI 0x00BE -#define pciPCIE_MC_ADDR1__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_1__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_10__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_11__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_12__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_13__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_14__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_15__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_16__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_17__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_18__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_2__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_3__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_4__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_5__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_6__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_7__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_8__VI 0x00BF -#define pciPCIE_MC_ADDR1_alt_9__VI 0x00BF -#define pciPCIE_MC_BLOCK_ALL0__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_1__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_10__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_11__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_12__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_13__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_14__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_15__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_16__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_17__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_18__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_2__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_3__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_4__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_5__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_6__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_7__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_8__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL0_alt_9__VI 0x00C2 -#define pciPCIE_MC_BLOCK_ALL1__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_1__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_10__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_11__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_12__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_13__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_14__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_15__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_16__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_17__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_18__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_2__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_3__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_4__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_5__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_6__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_7__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_8__VI 0x00C3 -#define pciPCIE_MC_BLOCK_ALL1_alt_9__VI 0x00C3 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_1__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_10__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_11__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_12__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_13__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_14__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_15__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_16__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_17__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_18__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_2__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_3__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_4__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_5__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_6__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_7__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_8__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_0_alt_9__VI 0x00C4 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_1__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_10__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_11__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_12__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_13__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_14__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_15__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_16__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_17__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_18__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_2__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_3__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_4__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_5__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_6__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_7__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_8__VI 0x00C5 -#define pciPCIE_MC_BLOCK_UNTRANSLATED_1_alt_9__VI 0x00C5 -#define pciPCIE_MC_CAP__VI 0x00BD -#define pciPCIE_MC_CAP_alt_1__VI 0x00BD -#define pciPCIE_MC_CAP_alt_10__VI 0x00BD -#define pciPCIE_MC_CAP_alt_11__VI 0x00BD -#define pciPCIE_MC_CAP_alt_12__VI 0x00BD -#define pciPCIE_MC_CAP_alt_13__VI 0x00BD -#define pciPCIE_MC_CAP_alt_14__VI 0x00BD -#define pciPCIE_MC_CAP_alt_15__VI 0x00BD -#define pciPCIE_MC_CAP_alt_16__VI 0x00BD -#define pciPCIE_MC_CAP_alt_17__VI 0x00BD -#define pciPCIE_MC_CAP_alt_18__VI 0x00BD -#define pciPCIE_MC_CAP_alt_2__VI 0x00BD -#define pciPCIE_MC_CAP_alt_3__VI 0x00BD -#define pciPCIE_MC_CAP_alt_4__VI 0x00BD -#define pciPCIE_MC_CAP_alt_5__VI 0x00BD -#define pciPCIE_MC_CAP_alt_6__VI 0x00BD -#define pciPCIE_MC_CAP_alt_7__VI 0x00BD -#define pciPCIE_MC_CAP_alt_8__VI 0x00BD -#define pciPCIE_MC_CAP_alt_9__VI 0x00BD -#define pciPCIE_MC_CNTL__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_1__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_10__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_11__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_12__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_13__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_14__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_15__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_16__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_17__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_18__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_2__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_3__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_4__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_5__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_6__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_7__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_8__VI 0x00BD -#define pciPCIE_MC_CNTL_alt_9__VI 0x00BD -#define pciPCIE_MC_ENH_CAP_LIST__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_1__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_10__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_11__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_12__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_13__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_14__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_15__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_16__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_17__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_18__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_2__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_3__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_4__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_5__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_6__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_7__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_8__VI 0x00BC -#define pciPCIE_MC_ENH_CAP_LIST_alt_9__VI 0x00BC -#define pciPCIE_MC_RCV0__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_1__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_10__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_11__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_12__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_13__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_14__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_15__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_16__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_17__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_18__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_2__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_3__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_4__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_5__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_6__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_7__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_8__VI 0x00C0 -#define pciPCIE_MC_RCV0_alt_9__VI 0x00C0 -#define pciPCIE_MC_RCV1__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_1__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_10__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_11__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_12__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_13__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_14__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_15__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_16__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_17__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_18__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_2__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_3__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_4__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_5__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_6__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_7__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_8__VI 0x00C1 -#define pciPCIE_MC_RCV1_alt_9__VI 0x00C1 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_10__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_11__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_12__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_13__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_14__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_15__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_16__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_17__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_18__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_4__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_5__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_6__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_7__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_8__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC_alt_9__VI 0x00B3 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_10__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_11__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_12__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_13__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_14__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_15__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_16__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_17__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_18__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_4__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_5__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_6__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_7__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_8__VI 0x00B2 -#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY_alt_9__VI 0x00B2 -#define pciPCIE_PAGE_REQ_CNTL_alt_10__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_11__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_12__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_13__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_14__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_15__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_16__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_17__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_18__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_4__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_5__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_6__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_7__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_8__VI 0x00B1 -#define pciPCIE_PAGE_REQ_CNTL_alt_9__VI 0x00B1 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_10__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_11__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_12__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_13__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_14__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_15__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_16__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_17__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_18__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_4__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_5__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_6__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_7__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_8__VI 0x00B0 -#define pciPCIE_PAGE_REQ_ENH_CAP_LIST_alt_9__VI 0x00B0 -#define pciPCIE_PAGE_REQ_STATUS_alt_10__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_11__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_12__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_13__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_14__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_15__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_16__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_17__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_18__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_4__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_5__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_6__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_7__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_8__VI 0x00B1 -#define pciPCIE_PAGE_REQ_STATUS_alt_9__VI 0x00B1 -#define pciPCIE_PASID_CAP_alt_10__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_11__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_12__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_13__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_14__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_15__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_16__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_17__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_18__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_4__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_5__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_6__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_7__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_8__VI 0x00B5 -#define pciPCIE_PASID_CAP_alt_9__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_10__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_11__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_12__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_13__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_14__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_15__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_16__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_17__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_18__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_4__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_5__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_6__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_7__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_8__VI 0x00B5 -#define pciPCIE_PASID_CNTL_alt_9__VI 0x00B5 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_10__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_11__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_12__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_13__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_14__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_15__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_16__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_17__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_18__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_4__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_5__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_6__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_7__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_8__VI 0x00B4 -#define pciPCIE_PASID_ENH_CAP_LIST_alt_9__VI 0x00B4 -#define pciPCIE_PORT_VC_CAP_REG1_alt_10__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_11__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_12__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_13__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_14__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_15__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_16__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_17__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_18__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_4__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_5__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_6__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_7__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_8__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG1_alt_9__VI 0x0045 -#define pciPCIE_PORT_VC_CAP_REG2_alt_10__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_11__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_12__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_13__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_14__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_15__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_16__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_17__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_18__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_4__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_5__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_6__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_7__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_8__VI 0x0046 -#define pciPCIE_PORT_VC_CAP_REG2_alt_9__VI 0x0046 -#define pciPCIE_PORT_VC_CNTL_alt_10__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_11__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_12__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_13__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_14__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_15__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_16__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_17__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_18__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_4__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_5__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_6__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_7__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_8__VI 0x0047 -#define pciPCIE_PORT_VC_CNTL_alt_9__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_10__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_11__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_12__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_13__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_14__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_15__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_16__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_17__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_18__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_4__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_5__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_6__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_7__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_8__VI 0x0047 -#define pciPCIE_PORT_VC_STATUS_alt_9__VI 0x0047 -#define pciPCIE_PWR_BUDGET_CAP_alt_10__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_11__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_12__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_13__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_14__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_15__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_16__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_17__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_18__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_4__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_5__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_6__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_7__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_8__VI 0x0093 -#define pciPCIE_PWR_BUDGET_CAP_alt_9__VI 0x0093 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_10__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_11__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_12__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_13__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_14__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_15__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_16__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_17__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_18__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_4__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_5__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_6__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_7__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_8__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_SELECT_alt_9__VI 0x0091 -#define pciPCIE_PWR_BUDGET_DATA_alt_10__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_11__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_12__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_13__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_14__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_15__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_16__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_17__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_18__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_4__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_5__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_6__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_7__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_8__VI 0x0092 -#define pciPCIE_PWR_BUDGET_DATA_alt_9__VI 0x0092 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_10__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_11__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_12__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_13__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_14__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_15__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_16__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_17__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_18__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_4__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_5__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_6__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_7__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_8__VI 0x0090 -#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST_alt_9__VI 0x0090 -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_10__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_11__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_12__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_13__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_14__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_15__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_16__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_17__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_18__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_4__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_5__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_6__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_7__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_8__VI 0x009C -#define pciPCIE_SECONDARY_ENH_CAP_LIST_alt_9__VI 0x009C -#define pciPCIE_SRIOV_CAP__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_1__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_10__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_11__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_12__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_13__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_14__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_15__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_16__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_17__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_18__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_2__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_3__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_4__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_5__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_6__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_7__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_8__VI 0x00CD -#define pciPCIE_SRIOV_CAP_alt_9__VI 0x00CD -#define pciPCIE_SRIOV_CONTROL__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_1__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_10__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_11__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_12__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_13__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_14__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_15__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_16__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_17__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_18__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_2__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_3__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_4__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_5__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_6__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_7__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_8__VI 0x00CE -#define pciPCIE_SRIOV_CONTROL_alt_9__VI 0x00CE -#define pciPCIE_SRIOV_ENH_CAP_LIST__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_1__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_10__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_11__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_12__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_13__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_14__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_15__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_16__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_17__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_18__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_2__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_3__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_4__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_5__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_6__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_7__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_8__VI 0x00CC -#define pciPCIE_SRIOV_ENH_CAP_LIST_alt_9__VI 0x00CC -#define pciPCIE_SRIOV_FIRST_VF_OFFSET__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_1__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_10__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_11__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_12__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_13__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_14__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_15__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_16__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_17__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_18__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_2__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_3__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_4__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_5__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_6__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_7__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_8__VI 0x00D1 -#define pciPCIE_SRIOV_FIRST_VF_OFFSET_alt_9__VI 0x00D1 -#define pciPCIE_SRIOV_FUNC_DEP_LINK__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_1__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_10__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_11__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_12__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_13__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_14__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_15__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_16__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_17__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_18__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_2__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_3__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_4__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_5__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_6__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_7__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_8__VI 0x00D0 -#define pciPCIE_SRIOV_FUNC_DEP_LINK_alt_9__VI 0x00D0 -#define pciPCIE_SRIOV_INITIAL_VFS__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_1__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_10__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_11__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_12__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_13__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_14__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_15__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_16__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_17__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_18__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_2__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_3__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_4__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_5__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_6__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_7__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_8__VI 0x00CF -#define pciPCIE_SRIOV_INITIAL_VFS_alt_9__VI 0x00CF -#define pciPCIE_SRIOV_NUM_VFS__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_1__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_10__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_11__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_12__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_13__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_14__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_15__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_16__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_17__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_18__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_2__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_3__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_4__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_5__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_6__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_7__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_8__VI 0x00D0 -#define pciPCIE_SRIOV_NUM_VFS_alt_9__VI 0x00D0 -#define pciPCIE_SRIOV_STATUS__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_1__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_10__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_11__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_12__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_13__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_14__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_15__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_16__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_17__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_18__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_2__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_3__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_4__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_5__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_6__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_7__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_8__VI 0x00CE -#define pciPCIE_SRIOV_STATUS_alt_9__VI 0x00CE -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_1__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_10__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_11__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_12__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_13__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_14__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_15__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_16__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_17__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_18__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_2__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_3__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_4__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_5__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_6__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_7__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_8__VI 0x00D3 -#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE_alt_9__VI 0x00D3 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_1__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_10__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_11__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_12__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_13__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_14__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_15__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_16__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_17__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_18__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_2__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_3__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_4__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_5__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_6__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_7__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_8__VI 0x00D4 -#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE_alt_9__VI 0x00D4 -#define pciPCIE_SRIOV_TOTAL_VFS__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_1__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_10__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_11__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_12__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_13__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_14__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_15__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_16__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_17__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_18__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_2__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_3__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_4__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_5__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_6__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_7__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_8__VI 0x00CF -#define pciPCIE_SRIOV_TOTAL_VFS_alt_9__VI 0x00CF -#define pciPCIE_SRIOV_VF_BASE_ADDR_0__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_1__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_10__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_11__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_12__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_13__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_14__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_15__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_16__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_17__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_18__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_2__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_3__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_4__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_5__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_6__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_7__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_8__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_0_alt_9__VI 0x00D5 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_1__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_10__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_11__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_12__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_13__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_14__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_15__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_16__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_17__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_18__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_2__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_3__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_4__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_5__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_6__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_7__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_8__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_1_alt_9__VI 0x00D6 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_1__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_10__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_11__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_12__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_13__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_14__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_15__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_16__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_17__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_18__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_2__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_3__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_4__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_5__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_6__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_7__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_8__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_2_alt_9__VI 0x00D7 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_1__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_10__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_11__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_12__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_13__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_14__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_15__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_16__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_17__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_18__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_2__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_3__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_4__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_5__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_6__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_7__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_8__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_3_alt_9__VI 0x00D8 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_1__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_10__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_11__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_12__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_13__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_14__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_15__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_16__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_17__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_18__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_2__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_3__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_4__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_5__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_6__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_7__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_8__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_4_alt_9__VI 0x00D9 -#define pciPCIE_SRIOV_VF_BASE_ADDR_5__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_1__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_10__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_11__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_12__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_13__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_14__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_15__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_16__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_17__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_18__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_2__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_3__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_4__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_5__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_6__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_7__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_8__VI 0x00DA -#define pciPCIE_SRIOV_VF_BASE_ADDR_5_alt_9__VI 0x00DA -#define pciPCIE_SRIOV_VF_DEVICE_ID__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_1__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_10__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_11__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_12__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_13__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_14__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_15__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_16__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_17__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_18__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_2__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_3__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_4__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_5__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_6__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_7__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_8__VI 0x00D2 -#define pciPCIE_SRIOV_VF_DEVICE_ID_alt_9__VI 0x00D2 -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_1__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_10__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_11__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_12__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_13__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_14__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_15__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_16__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_17__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_18__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_2__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_3__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_4__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_5__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_6__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_7__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_8__VI 0x00DB -#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_alt_9__VI 0x00DB -#define pciPCIE_SRIOV_VF_STRIDE__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_1__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_10__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_11__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_12__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_13__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_14__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_15__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_16__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_17__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_18__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_2__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_3__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_4__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_5__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_6__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_7__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_8__VI 0x00D1 -#define pciPCIE_SRIOV_VF_STRIDE_alt_9__VI 0x00D1 -#define pciPCIE_TLP_PREFIX_LOG0_alt_10__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_11__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_12__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_13__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_14__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_15__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_16__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_17__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_18__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_4__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_5__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_6__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_7__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_8__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG0_alt_9__VI 0x0062 -#define pciPCIE_TLP_PREFIX_LOG1_alt_10__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_11__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_12__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_13__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_14__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_15__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_16__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_17__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_18__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_4__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_5__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_6__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_7__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_8__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG1_alt_9__VI 0x0063 -#define pciPCIE_TLP_PREFIX_LOG2_alt_10__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_11__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_12__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_13__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_14__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_15__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_16__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_17__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_18__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_4__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_5__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_6__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_7__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_8__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG2_alt_9__VI 0x0064 -#define pciPCIE_TLP_PREFIX_LOG3_alt_10__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_11__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_12__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_13__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_14__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_15__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_16__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_17__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_18__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_4__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_5__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_6__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_7__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_8__VI 0x0065 -#define pciPCIE_TLP_PREFIX_LOG3_alt_9__VI 0x0065 -#define pciPCIE_TPH_REQR_CAP__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_1__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_10__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_11__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_12__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_13__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_14__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_15__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_16__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_17__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_18__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_2__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_3__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_4__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_5__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_6__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_7__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_8__VI 0x00B9 -#define pciPCIE_TPH_REQR_CAP_alt_9__VI 0x00B9 -#define pciPCIE_TPH_REQR_CNTL__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_1__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_10__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_11__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_12__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_13__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_14__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_15__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_16__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_17__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_18__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_2__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_3__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_4__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_5__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_6__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_7__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_8__VI 0x00BA -#define pciPCIE_TPH_REQR_CNTL_alt_9__VI 0x00BA -#define pciPCIE_TPH_REQR_ENH_CAP_LIST__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_1__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_10__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_11__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_12__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_13__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_14__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_15__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_16__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_17__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_18__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_2__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_3__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_4__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_5__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_6__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_7__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_8__VI 0x00B8 -#define pciPCIE_TPH_REQR_ENH_CAP_LIST_alt_9__VI 0x00B8 -#define pciPCIE_UNCORR_ERR_MASK_alt_10__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_11__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_12__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_13__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_14__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_15__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_16__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_17__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_18__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_4__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_5__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_6__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_7__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_8__VI 0x0056 -#define pciPCIE_UNCORR_ERR_MASK_alt_9__VI 0x0056 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_10__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_11__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_12__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_13__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_14__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_15__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_16__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_17__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_18__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_4__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_5__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_6__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_7__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_8__VI 0x0057 -#define pciPCIE_UNCORR_ERR_SEVERITY_alt_9__VI 0x0057 -#define pciPCIE_UNCORR_ERR_STATUS_alt_10__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_11__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_12__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_13__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_14__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_15__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_16__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_17__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_18__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_4__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_5__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_6__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_7__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_8__VI 0x0055 -#define pciPCIE_UNCORR_ERR_STATUS_alt_9__VI 0x0055 -#define pciPCIE_VC0_RESOURCE_CAP_alt_10__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_11__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_12__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_13__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_14__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_15__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_16__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_17__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_18__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_4__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_5__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_6__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_7__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_8__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CAP_alt_9__VI 0x0048 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_10__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_11__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_12__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_13__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_14__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_15__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_16__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_17__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_18__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_4__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_5__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_6__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_7__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_8__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_CNTL_alt_9__VI 0x0049 -#define pciPCIE_VC0_RESOURCE_STATUS_alt_10__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_11__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_12__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_13__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_14__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_15__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_16__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_17__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_18__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_4__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_5__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_6__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_7__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_8__VI 0x004A -#define pciPCIE_VC0_RESOURCE_STATUS_alt_9__VI 0x004A -#define pciPCIE_VC1_RESOURCE_CAP_alt_10__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_11__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_12__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_13__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_14__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_15__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_16__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_17__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_18__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_4__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_5__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_6__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_7__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_8__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CAP_alt_9__VI 0x004B -#define pciPCIE_VC1_RESOURCE_CNTL_alt_10__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_11__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_12__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_13__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_14__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_15__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_16__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_17__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_18__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_4__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_5__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_6__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_7__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_8__VI 0x004C -#define pciPCIE_VC1_RESOURCE_CNTL_alt_9__VI 0x004C -#define pciPCIE_VC1_RESOURCE_STATUS_alt_10__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_11__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_12__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_13__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_14__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_15__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_16__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_17__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_18__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_4__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_5__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_6__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_7__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_8__VI 0x004D -#define pciPCIE_VC1_RESOURCE_STATUS_alt_9__VI 0x004D -#define pciPCIE_VC_ENH_CAP_LIST_alt_10__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_11__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_12__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_13__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_14__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_15__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_16__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_17__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_18__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_4__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_5__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_6__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_7__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_8__VI 0x0044 -#define pciPCIE_VC_ENH_CAP_LIST_alt_9__VI 0x0044 -#define pciPCIE_VENDOR_SPECIFIC1_alt_10__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_11__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_12__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_13__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_14__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_15__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_16__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_17__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_18__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_4__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_5__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_6__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_7__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_8__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC1_alt_9__VI 0x0042 -#define pciPCIE_VENDOR_SPECIFIC2_alt_10__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_11__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_12__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_13__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_14__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_15__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_16__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_17__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_18__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_4__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_5__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_6__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_7__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_8__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC2_alt_9__VI 0x0043 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_1__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_10__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_11__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_12__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_13__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_14__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_15__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_16__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_17__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_18__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_2__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_3__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_4__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_5__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_6__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_7__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_8__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_alt_9__VI 0x0100 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_10__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_11__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_12__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_13__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_14__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_15__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_16__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_17__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_18__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_4__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_5__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_6__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_7__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_8__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_alt_9__VI 0x0040 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_1__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_10__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_11__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_12__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_13__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_14__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_15__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_16__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_17__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_18__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_2__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_3__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_4__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_5__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_6__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_7__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_8__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_alt_9__VI 0x0105 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_1__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_10__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_11__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_12__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_13__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_14__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_15__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_16__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_17__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_18__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_2__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_3__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_4__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_5__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_6__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_7__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_8__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_alt_9__VI 0x0101 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_10__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_11__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_12__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_13__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_14__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_15__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_16__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_17__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_18__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_4__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_5__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_6__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_7__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_8__VI 0x0041 -#define pciPCIE_VENDOR_SPECIFIC_HDR_alt_9__VI 0x0041 -#define pciPMI_CAP_LIST_alt_10__VI 0x0014 -#define pciPMI_CAP_LIST_alt_11__VI 0x0014 -#define pciPMI_CAP_LIST_alt_12__VI 0x0014 -#define pciPMI_CAP_LIST_alt_13__VI 0x0014 -#define pciPMI_CAP_LIST_alt_14__VI 0x0014 -#define pciPMI_CAP_LIST_alt_15__VI 0x0014 -#define pciPMI_CAP_LIST_alt_16__VI 0x0014 -#define pciPMI_CAP_LIST_alt_17__VI 0x0014 -#define pciPMI_CAP_LIST_alt_18__VI 0x0014 -#define pciPMI_CAP_LIST_alt_4__VI 0x0014 -#define pciPMI_CAP_LIST_alt_5__VI 0x0014 -#define pciPMI_CAP_LIST_alt_6__VI 0x0014 -#define pciPMI_CAP_LIST_alt_7__VI 0x0014 -#define pciPMI_CAP_LIST_alt_8__VI 0x0014 -#define pciPMI_CAP_LIST_alt_9__VI 0x0014 -#define pciPMI_CAP_alt_10__VI 0x0014 -#define pciPMI_CAP_alt_11__VI 0x0014 -#define pciPMI_CAP_alt_12__VI 0x0014 -#define pciPMI_CAP_alt_13__VI 0x0014 -#define pciPMI_CAP_alt_14__VI 0x0014 -#define pciPMI_CAP_alt_15__VI 0x0014 -#define pciPMI_CAP_alt_16__VI 0x0014 -#define pciPMI_CAP_alt_17__VI 0x0014 -#define pciPMI_CAP_alt_18__VI 0x0014 -#define pciPMI_CAP_alt_4__VI 0x0014 -#define pciPMI_CAP_alt_5__VI 0x0014 -#define pciPMI_CAP_alt_6__VI 0x0014 -#define pciPMI_CAP_alt_7__VI 0x0014 -#define pciPMI_CAP_alt_8__VI 0x0014 -#define pciPMI_CAP_alt_9__VI 0x0014 -#define pciPMI_STATUS_CNTL_alt_10__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_11__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_12__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_13__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_14__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_15__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_16__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_17__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_18__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_4__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_5__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_6__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_7__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_8__VI 0x0015 -#define pciPMI_STATUS_CNTL_alt_9__VI 0x0015 -#define pciPROG_INTERFACE_alt_10__VI 0x0002 -#define pciPROG_INTERFACE_alt_11__VI 0x0002 -#define pciPROG_INTERFACE_alt_12__VI 0x0002 -#define pciPROG_INTERFACE_alt_13__VI 0x0002 -#define pciPROG_INTERFACE_alt_14__VI 0x0002 -#define pciPROG_INTERFACE_alt_15__VI 0x0002 -#define pciPROG_INTERFACE_alt_16__VI 0x0002 -#define pciPROG_INTERFACE_alt_17__VI 0x0002 -#define pciPROG_INTERFACE_alt_18__VI 0x0002 -#define pciPROG_INTERFACE_alt_4__VI 0x0002 -#define pciPROG_INTERFACE_alt_5__VI 0x0002 -#define pciPROG_INTERFACE_alt_6__VI 0x0002 -#define pciPROG_INTERFACE_alt_7__VI 0x0002 -#define pciPROG_INTERFACE_alt_8__VI 0x0002 -#define pciPROG_INTERFACE_alt_9__VI 0x0002 -#define pciREVISION_ID_alt_10__VI 0x0002 -#define pciREVISION_ID_alt_11__VI 0x0002 -#define pciREVISION_ID_alt_12__VI 0x0002 -#define pciREVISION_ID_alt_13__VI 0x0002 -#define pciREVISION_ID_alt_14__VI 0x0002 -#define pciREVISION_ID_alt_15__VI 0x0002 -#define pciREVISION_ID_alt_16__VI 0x0002 -#define pciREVISION_ID_alt_17__VI 0x0002 -#define pciREVISION_ID_alt_18__VI 0x0002 -#define pciREVISION_ID_alt_4__VI 0x0002 -#define pciREVISION_ID_alt_5__VI 0x0002 -#define pciREVISION_ID_alt_6__VI 0x0002 -#define pciREVISION_ID_alt_7__VI 0x0002 -#define pciREVISION_ID_alt_8__VI 0x0002 -#define pciREVISION_ID_alt_9__VI 0x0002 -#define pciROM_BASE_ADDR_alt_10__VI 0x000C -#define pciROM_BASE_ADDR_alt_11__VI 0x000C -#define pciROM_BASE_ADDR_alt_12__VI 0x000C -#define pciROM_BASE_ADDR_alt_13__VI 0x000C -#define pciROM_BASE_ADDR_alt_14__VI 0x000C -#define pciROM_BASE_ADDR_alt_15__VI 0x000C -#define pciROM_BASE_ADDR_alt_16__VI 0x000C -#define pciROM_BASE_ADDR_alt_17__VI 0x000C -#define pciROM_BASE_ADDR_alt_18__VI 0x000C -#define pciROM_BASE_ADDR_alt_4__VI 0x000C -#define pciROM_BASE_ADDR_alt_5__VI 0x000C -#define pciROM_BASE_ADDR_alt_6__VI 0x000C -#define pciROM_BASE_ADDR_alt_7__VI 0x000C -#define pciROM_BASE_ADDR_alt_8__VI 0x000C -#define pciROM_BASE_ADDR_alt_9__VI 0x000C -#define pciSTATUS_alt_10__VI 0x0001 -#define pciSTATUS_alt_11__VI 0x0001 -#define pciSTATUS_alt_12__VI 0x0001 -#define pciSTATUS_alt_13__VI 0x0001 -#define pciSTATUS_alt_14__VI 0x0001 -#define pciSTATUS_alt_15__VI 0x0001 -#define pciSTATUS_alt_16__VI 0x0001 -#define pciSTATUS_alt_17__VI 0x0001 -#define pciSTATUS_alt_18__VI 0x0001 -#define pciSTATUS_alt_4__VI 0x0001 -#define pciSTATUS_alt_5__VI 0x0001 -#define pciSTATUS_alt_6__VI 0x0001 -#define pciSTATUS_alt_7__VI 0x0001 -#define pciSTATUS_alt_8__VI 0x0001 -#define pciSTATUS_alt_9__VI 0x0001 -#define pciSUB_CLASS_alt_10__VI 0x0002 -#define pciSUB_CLASS_alt_11__VI 0x0002 -#define pciSUB_CLASS_alt_12__VI 0x0002 -#define pciSUB_CLASS_alt_13__VI 0x0002 -#define pciSUB_CLASS_alt_14__VI 0x0002 -#define pciSUB_CLASS_alt_15__VI 0x0002 -#define pciSUB_CLASS_alt_16__VI 0x0002 -#define pciSUB_CLASS_alt_17__VI 0x0002 -#define pciSUB_CLASS_alt_18__VI 0x0002 -#define pciSUB_CLASS_alt_4__VI 0x0002 -#define pciSUB_CLASS_alt_5__VI 0x0002 -#define pciSUB_CLASS_alt_6__VI 0x0002 -#define pciSUB_CLASS_alt_7__VI 0x0002 -#define pciSUB_CLASS_alt_8__VI 0x0002 -#define pciSUB_CLASS_alt_9__VI 0x0002 -#define pciVENDOR_CAP_LIST_alt_10__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_11__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_12__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_13__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_14__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_15__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_16__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_17__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_18__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_4__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_5__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_6__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_7__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_8__VI 0x0012 -#define pciVENDOR_CAP_LIST_alt_9__VI 0x0012 -#define pciVENDOR_ID_alt_10__VI 0x0000 -#define pciVENDOR_ID_alt_11__VI 0x0000 -#define pciVENDOR_ID_alt_12__VI 0x0000 -#define pciVENDOR_ID_alt_13__VI 0x0000 -#define pciVENDOR_ID_alt_14__VI 0x0000 -#define pciVENDOR_ID_alt_15__VI 0x0000 -#define pciVENDOR_ID_alt_16__VI 0x0000 -#define pciVENDOR_ID_alt_17__VI 0x0000 -#define pciVENDOR_ID_alt_18__VI 0x0000 -#define pciVENDOR_ID_alt_4__VI 0x0000 -#define pciVENDOR_ID_alt_5__VI 0x0000 -#define pciVENDOR_ID_alt_6__VI 0x0000 -#define pciVENDOR_ID_alt_7__VI 0x0000 -#define pciVENDOR_ID_alt_8__VI 0x0000 -#define pciVENDOR_ID_alt_9__VI 0x0000 - -#endif // SI_CI_VI_merged_offset_HEADER diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_pm4_it_opcodes.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_pm4_it_opcodes.h deleted file mode 100644 index 5992db0e0b..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_pm4_it_opcodes.h +++ /dev/null @@ -1,141 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS AUTO-GENERATED BY PITGEN (vA) -// !!!! DO NOT EDIT BY HAND !!!! -////////////////////////////////////////////////////////////////////////////////// -// Project: 10xx or later -// Description: -// -// PM4 PacketType3 IT_OpCode Definitions -// Extracted From ME and PFP F32 Microcode Jump Tables: -// -////////////////////////////////////////////////////////////////////////////////// -// -// Trade secret of ATI Technologies, Inc. -// Copyright 1999, ATI Technologies, Inc., (unpublished) -// -// All rights reserved. This notice is intended as a precaution against -// inadvertent publication and does not imply publication or any waiver -// of confidentiality. The year included in the foregoing notice is the -// year of creation of the work. -////////////////////////////////////////////////////////////////////////////////// - -#ifndef PM4_IT_OPCODES_H -#define PM4_IT_OPCODES_H - -enum IT_OpCodeType { - IT_NOP = 0x10, - IT_SET_BASE = 0x11, - IT_CLEAR_STATE = 0x12, - IT_INDEX_BUFFER_SIZE = 0x13, - IT_DISPATCH_DIRECT = 0x15, - IT_DISPATCH_INDIRECT = 0x16, - IT_INDIRECT_BUFFER_END = 0x17, - IT_INDIRECT_BUFFER_CNST_END = 0x19, - IT_ALLOC_GDS__SI = 0x1B, - IT_WRITE_GDS_RAM__SI = 0x1C, - IT_ATOMIC_GDS = 0x1D, - IT_ATOMIC__SI__VI = 0x1E, - IT_OCCLUSION_QUERY = 0x1F, - IT_SET_PREDICATION = 0x20, - IT_REG_RMW = 0x21, - IT_COND_EXEC = 0x22, - IT_PRED_EXEC = 0x23, - IT_DRAW_INDIRECT = 0x24, - IT_DRAW_INDEX_INDIRECT = 0x25, - IT_INDEX_BASE = 0x26, - IT_DRAW_INDEX_2 = 0x27, - IT_CONTEXT_CONTROL = 0x28, - IT_INDEX_TYPE = 0x2A, - IT_DRAW_INDIRECT_MULTI = 0x2C, - IT_DRAW_INDEX_AUTO = 0x2D, - IT_DRAW_INDEX_IMMD__SI = 0x2E, - IT_NUM_INSTANCES = 0x2F, - IT_DRAW_INDEX_MULTI_AUTO = 0x30, - IT_INDIRECT_BUFFER_CNST_PRIV__SI = 0x31, - IT_INDIRECT_BUFFER_PRIV = 0x32, - IT_INDIRECT_BUFFER_CNST = 0x33, - IT_STRMOUT_BUFFER_UPDATE = 0x34, - IT_DRAW_INDEX_OFFSET_2 = 0x35, - IT_WRITE_DATA = 0x37, - IT_DRAW_INDEX_INDIRECT_MULTI = 0x38, - IT_MEM_SEMAPHORE = 0x39, - IT_MPEG_INDEX__SI = 0x3A, - IT_COPY_DW__SI__CI = 0x3B, - IT_WAIT_REG_MEM = 0x3C, - IT_MEM_WRITE__SI = 0x3D, - IT_INDIRECT_BUFFER = 0x3F, - IT_COPY_DATA = 0x40, - IT_CP_DMA = 0x41, - IT_PFP_SYNC_ME = 0x42, - IT_SURFACE_SYNC = 0x43, - IT_ME_INITIALIZE = 0x44, - IT_COND_WRITE = 0x45, - IT_EVENT_WRITE = 0x46, - IT_EVENT_WRITE_EOP = 0x47, - IT_EVENT_WRITE_EOS = 0x48, - IT_PREAMBLE_CNTL = 0x4A, - IT_GFX_CNTX_UPDATE = 0x52, - IT_BLK_CNTX_UPDATE = 0x53, - IT_INCR_UPDT_STATE = 0x55, - IT_ONE_REG_WRITE__SI = 0x57, - IT_LOAD_SH_REG = 0x5F, - IT_LOAD_CONFIG_REG = 0x60, - IT_LOAD_CONTEXT_REG = 0x61, - IT_SET_CONFIG_REG = 0x68, - IT_SET_CONTEXT_REG = 0x69, - IT_SET_SH_REG_DI = 0x72, - IT_SET_CONTEXT_REG_INDIRECT = 0x73, - IT_SET_SH_REG = 0x76, - IT_SET_SH_REG_OFFSET = 0x77, - IT_ME_WRITE__SI = 0x7A, - IT_PFP_WRITE__SI = 0x7B, - IT_SCRATCH_RAM_WRITE = 0x7D, - IT_SCRATCH_RAM_READ = 0x7E, - IT_CE_WRITE__SI = 0x7F, - IT_LOAD_CONST_RAM = 0x80, - IT_WRITE_CONST_RAM = 0x81, - IT_WRITE_CONST_RAM_OFFSET__SI = 0x82, - IT_DUMP_CONST_RAM = 0x83, - IT_INCREMENT_CE_COUNTER = 0x84, - IT_INCREMENT_DE_COUNTER = 0x85, - IT_WAIT_ON_CE_COUNTER = 0x86, - IT_WAIT_ON_DE_COUNTER__SI = 0x87, - IT_WAIT_ON_DE_COUNTER_DIFF = 0x88, - IT_SET_CE_DE_COUNTERS__SI = 0x89, - IT_WAIT_ON_AVAIL_BUFFER__SI = 0x8A, - IT_SWITCH_BUFFER = 0x8B, - IT_FORWARD_HEADER = 0x7C, - IT_ATOMIC_MEM__CI = 0x1E, - IT_DRAW_PREAMBLE__CI__VI = 0x36, - IT_RELEASE_MEM__CI__VI = 0x49, - IT_DMA_DATA__CI__VI = 0x50, - IT_ACQUIRE_MEM__CI__VI = 0x58, - IT_REWIND__CI__VI = 0x59, - IT_INTERRUPT__CI__VI = 0x5A, - IT_LOAD_UCONFIG_REG__CI__VI = 0x5E, - IT_SET_QUEUE_REG__CI__VI = 0x78, - IT_SET_UCONFIG_REG__CI__VI = 0x79, - IT_EOP_BUFFER_END__CI__VI = 0x18, - IT_INTR_BUFFER_END__CI__VI = 0x1A, - IT_RUN_LIST__CI = 0x3E, - IT_SET_RESOURCES__CI__VI = 0xA0, - IT_MAP_PROCESS__CI__VI = 0xA1, - IT_MAP_QUEUES__CI__VI = 0xA2, - IT_QUERY_STATUS__CI = 0xA3, - IT_UNMAP_QUEUES__CI = 0xA4, - IT_COND_PREEMPT__VI = 0x8E, - IT_DISPATCH_DRAW_PREAMBLE__VI = 0x8C, - IT_DISPATCH_DRAW__VI = 0x8D, - IT_DISPATCH_DRAW_PREAMBLE_ACE__VI = 0x8C, - IT_DISPATCH_DRAW_ACE__VI = 0x8D, - IT_PRIME_ATCL2__VI = 0x8E, - IT_UNMAP_QUEUES__VI = 0xA3, - IT_QUERY_STATUS__VI = 0xA4, - IT_RUN_LIST__VI = 0xA5, -}; - -#define PM4_TYPE_0 0 -#define PM4_TYPE_2 2 -#define PM4_TYPE_3 3 - -#endif // PM4_IT_OPCODES_H diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_pm4cmds.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_pm4cmds.h deleted file mode 100644 index c492f235ed..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_pm4cmds.h +++ /dev/null @@ -1,79 +0,0 @@ -/* -*************************************************************************************************** -* -* Trade secret of Advanced Micro Devices, Inc. -* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against inadvertent publication and -* does not imply publication or any waiver of confidentiality. The year included in the foregoing -* notice is the year of creation of the work. -* -*************************************************************************************************** -*/ - -#ifndef _SI_CI_VI_PM4CMDS_H_ -#define _SI_CI_VI_PM4CMDS_H_ - -/****************************************************************************** -* -* si_ci_vi_merged_pm4cmds.h -* -* SI PM4 definitions, typedefs, and enumerations. -* -******************************************************************************/ - -#include "si_pm4defs.h" -#include "si_ci_vi_merged_pm4_it_opcodes.h" - -// Wrapper on the new header-generation macro -#define PM4_CMD(op, count) PM4_TYPE_3_HDR(op, count, ShaderGraphics, PredDisable) - -// IT_DRAW_INDEX is replaced by IT_DRAW_INDEX_2 -#define PM4_CMD_DRAW_INDEX_2(count) PM4_CMD(IT_DRAW_INDEX_2, count) -#define PM4_CMD_DRAW_INDEX_AUTO(count) PM4_CMD(IT_DRAW_INDEX_AUTO, count) -#define PM4_CMD_DRAW_INDEX_IMMD_SI(count) PM4_CMD(IT_DRAW_INDEX_IMMD__SI, count) -#define PM4_CMD_DRAW_INDEX_TYPE(count) PM4_CMD(IT_INDEX_TYPE, count) -#define PM4_CMD_DRAW_NUM_INSTANCES(count) PM4_CMD(IT_NUM_INSTANCES, count) -#define PM4_CMD_DRAW_PREAMBLE(count) PM4_CMD(IT_DRAW_PREAMBLE__CI__VI, count) - -#define PM4_CMD_WAIT_REG_MEM(count) PM4_CMD(IT_WAIT_REG_MEM, count) -#define PM4_CMD_MEM_WRITE(count) PM4_CMD(IT_MEM_WRITE, count) -#define PM4_CMD_EVENT_WRITE(count) PM4_CMD(IT_EVENT_WRITE, count) -#define PM4_CMD_EVENT_WRITE_EOP(count) PM4_CMD(IT_EVENT_WRITE_EOP, count) -#define PM4_CMD_STRMOUT_BUFFER_UPDATE(count) PM4_CMD(IT_STRMOUT_BUFFER_UPDATE, count) -#define PM4_CMD_COPY_DATA(count) PM4_CMD(IT_COPY_DATA, count) -#define PM4_CMD_CP_DMA(count) PM4_CMD(IT_CP_DMA, count) -#define PM4_CMD_SET_PREDICATION(count) PM4_CMD(IT_SET_PREDICATION, count) -#define PM4_CMD_SURFACE_BASE_UPDATE(count) PM4_CMD(IT_SURFACE_BASE_UPDATE, count) -#define PM4_CMD_STRMOUT_BASE_UPDATE(count) PM4_CMD(IT_STRMOUT_BASE_UPDATE, count) -#define PM4_CMD_START_3D_CMDBUF(count) PM4_CMD(IT_START_3D_CMDBUF, count) -#define PM4_CMD_ROLL_CONTEXT(count) PM4_CMD(IT_ROLL_CONTEXT, count) -#define PM4_CMD_CONTEXT_CTL(count) PM4_CMD(IT_CONTEXT_CONTROL, count) -#define PM4_CMD_PRED_EXEC PM4_CMD(IT_PRED_EXEC, 2) -#define PM4_CMD_SURFACE_SYNC(count) PM4_CMD(IT_SURFACE_SYNC, count) - -#define PM4_CMD_LOAD_CONFIG_REG(count) PM4_CMD(IT_LOAD_CONFIG_REG, count) -#define PM4_CMD_LOAD_CONTEXT_REG(count) PM4_CMD(IT_LOAD_CONTEXT_REG, count) -#define PM4_CMD_LOAD_SH_REG(count) PM4_CMD(IT_LOAD_SH_REG, count) - -#define PM4_CMD_SET_CONFIG_REG(count) PM4_CMD(IT_SET_CONFIG_REG, count) -#define PM4_CMD_SET_CONTEXT_REG(count) PM4_CMD(IT_SET_CONTEXT_REG, count) -#define PM4_CMD_SET_SH_REG(count) PM4_CMD(IT_SET_SH_REG, count) - -#define PM4_CMD_INDIRECT_BUFFER_CNST_END(count) PM4_CMD(IT_INDIRECT_BUFFER_CNST_END, count) -#define PM4_CMD_INDIRECT_BUFFER_CNST_PRIV(count) PM4_CMD(IT_INDIRECT_BUFFER_CNST_PRIV, count) -#define PM4_CMD_INDIRECT_BUFFER_CNST(count) PM4_CMD(IT_INDIRECT_BUFFER_CNST, count) - -#define PM4_CMD_LOAD_CONST_RAM(count) PM4_CMD(IT_LOAD_CONST_RAM, count) -#define PM4_CMD_WRITE_CONST_RAM(count) PM4_CMD(IT_WRITE_CONST_RAM, count) -#define PM4_CMD_DUMP_CONST_RAM(count) PM4_CMD(IT_DUMP_CONST_RAM, count) - -#define PM4_CMD_INC_CE_COUNTER(count) PM4_CMD(IT_INCREMENT_CE_COUNTER, count) -#define PM4_CMD_INC_DE_COUNTER(count) PM4_CMD(IT_INCREMENT_DE_COUNTER, count) - -#define PM4_CMD_WAIT_ON_CE_COUNTER(count) PM4_CMD(IT_WAIT_ON_CE_COUNTER, count) -#define PM4_CMD_WAIT_ON_DE_COUNTER_DIFF(count) PM4_CMD(IT_WAIT_ON_DE_COUNTER_DIFF, count) - -#define PM4_CMD_WRITE_DATA(count) PM4_CMD(IT_WRITE_DATA, count) - -#endif // _SI_CI_VI_PM4CMDS_H_ diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_shift.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_shift.h deleted file mode 100644 index 88bdc9bce3..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_shift.h +++ /dev/null @@ -1,48643 +0,0 @@ -#if !defined SI_CI_VI_merged_shift_HEADER -#define SI_CI_VI_merged_shift_HEADER - - -// -// Source merge files: -// E:\MergedHeaders\SI+CI+Amur\Original\SICI/si_ci_merged_shift.h -// E:\MergedHeaders\SI+CI+Amur\Original\Amur/vi_shift.h -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -#define ABM_DEBUG_01__DBG_ABM_ENABLE_REQ__SHIFT__SI 0x0000000e -#define ABM_DEBUG_01__DBG_ABM_ENABLE_RESYNC__SHIFT__SI 0x0000000f -#define ABM_DEBUG_01__DBG_ABM_ON_CLOCK_RUNNING__SHIFT__SI 0x00000011 -#define ABM_DEBUG_01__DBG_ABM_SOURCE_SELECT__SHIFT__SI 0x00000010 -#define ABM_DEBUG_01__DBG_CRTC1_ABM_DATA_ACTIVE__SHIFT__SI 0x0000000a -#define ABM_DEBUG_01__DBG_CRTC1_ABM_G_COLOR__SHIFT__SI 0x00000000 -#define ABM_DEBUG_01__DBG_CRTC1_ABM_HBLANK__SHIFT__SI 0x00000009 -#define ABM_DEBUG_01__DBG_CRTC1_ABM_VBLANK__SHIFT__SI 0x00000008 -#define ABM_DEBUG_01__DBG_CRTC1_EN__SHIFT__SI 0x0000000b -#define ABM_DEBUG_01__DBG_CRTC1_VSYNC_POL__SHIFT__SI 0x0000000c -#define ABM_DEBUG_01__DBG_CRTC1_VSYNC__SHIFT__SI 0x0000000d -#define ABM_DEBUG_01__DBG_CRTC2_ABM_DATA_ACTIVE__SHIFT__SI 0x00000015 -#define ABM_DEBUG_01__DBG_CRTC2_ABM_G_COLOR__SHIFT__SI 0x00000018 -#define ABM_DEBUG_01__DBG_CRTC2_ABM_HBLANK__SHIFT__SI 0x00000016 -#define ABM_DEBUG_01__DBG_CRTC2_ABM_VBLANK__SHIFT__SI 0x00000017 -#define ABM_DEBUG_01__DBG_CRTC2_EN__SHIFT__SI 0x00000014 -#define ABM_DEBUG_01__DBG_CRTC2_VSYNC_POL__SHIFT__SI 0x00000013 -#define ABM_DEBUG_01__DBG_CRTC2_VSYNC__SHIFT__SI 0x00000012 -#define ABM_DEBUG_02__DBG_ABM_ENABLE_RESYNC__SHIFT__SI 0x00000014 -#define ABM_DEBUG_02__DBG_ABM_FMT_G_COLOR__SHIFT__SI 0x00000008 -#define ABM_DEBUG_02__DBG_ABM_SOURCE_SELECT__SHIFT__SI 0x00000013 -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_DATA_ACTIVE__SHIFT__SI 0x00000012 -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_G_COLOR__SHIFT__SI 0x00000000 -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_HBLANK__SHIFT__SI 0x00000011 -#define ABM_DEBUG_02__DBG_BYPASS_FMT1_VBLANK__SHIFT__SI 0x00000010 -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_DATA_ACTIVE__SHIFT__SI 0x00000015 -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_G_COLOR__SHIFT__SI 0x00000018 -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_HBLANK__SHIFT__SI 0x00000016 -#define ABM_DEBUG_02__DBG_BYPASS_FMT2_VBLANK__SHIFT__SI 0x00000017 -#define ABM_DEBUG_03__DBG_HG_BIN_SEL_VALID__SHIFT__SI 0x00000015 -#define ABM_DEBUG_03__DBG_HG_BIN_SEL__SHIFT__SI 0x00000010 -#define ABM_DEBUG_03__DBG_IPCSC_DATA_ACTIVE__SHIFT__SI 0x0000000d -#define ABM_DEBUG_03__DBG_IPCSC_HBLANK__SHIFT__SI 0x0000000c -#define ABM_DEBUG_03__DBG_IPCSC_IPCSC_SAFE_EN__SHIFT__SI 0x0000000a -#define ABM_DEBUG_03__DBG_IPCSC_LUMA_DATA__SHIFT__SI 0x00000000 -#define ABM_DEBUG_03__DBG_IPCSC_RGB_SEL__SHIFT__SI 0x0000000e -#define ABM_DEBUG_03__DBG_IPCSC_VBLANK__SHIFT__SI 0x0000000b -#define ABM_DEBUG_03__DBG_IPCSC_VMAX__SHIFT__SI 0x00000016 -#define ABM_DEBUG_04__DBG_BL_FRAME_COUNT__SHIFT__SI 0x0000000e -#define ABM_DEBUG_04__DBG_BL_INTERRUPT__SHIFT__SI 0x0000000d -#define ABM_DEBUG_04__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_04__DBG_HG_EN__SHIFT__SI 0x00000003 -#define ABM_DEBUG_04__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000005 -#define ABM_DEBUG_04__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_04__DBG_HG_INTERRUPT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_04__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_04__DBG_LS_EN__SHIFT__SI 0x00000016 -#define ABM_DEBUG_04__DBG_LS_FRAME_COUNT__SHIFT__SI 0x00000018 -#define ABM_DEBUG_04__DBG_LS_INTERRUPT__SHIFT__SI 0x00000017 -#define ABM_DEBUG_05__DBG_HG_BIN_SHIFT_FLAG_1_4__SHIFT__SI 0x0000000c -#define ABM_DEBUG_05__DBG_HG_BIN_SHIFT_INDEX_1_4__SHIFT__SI 0x00000010 -#define ABM_DEBUG_05__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_05__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_05__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_05__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_05__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_06__DBG_HG_BIN_SHIFT_FLAG_5_8__SHIFT__SI 0x0000000c -#define ABM_DEBUG_06__DBG_HG_BIN_SHIFT_INDEX_5_8__SHIFT__SI 0x00000010 -#define ABM_DEBUG_06__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_06__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_06__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_06__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_06__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_07__DBG_HG_BIN_SHIFT_FLAG_9_12__SHIFT__SI 0x0000000c -#define ABM_DEBUG_07__DBG_HG_BIN_SHIFT_INDEX_9_12__SHIFT__SI 0x00000010 -#define ABM_DEBUG_07__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_07__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_07__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_07__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_07__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_08__DBG_HG_BIN_SHIFT_FLAG_13_16__SHIFT__SI 0x0000000c -#define ABM_DEBUG_08__DBG_HG_BIN_SHIFT_INDEX_13_16__SHIFT__SI 0x00000010 -#define ABM_DEBUG_08__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_08__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_08__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_08__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_08__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_09__DBG_HG_BIN_SHIFT_FLAG_17_20__SHIFT__SI 0x0000000c -#define ABM_DEBUG_09__DBG_HG_BIN_SHIFT_INDEX_17_20__SHIFT__SI 0x00000010 -#define ABM_DEBUG_09__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_09__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_09__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_09__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_09__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_10__DBG_HG_BIN_SHIFT_FLAG_21_24__SHIFT__SI 0x0000000c -#define ABM_DEBUG_10__DBG_HG_BIN_SHIFT_INDEX_21_24__SHIFT__SI 0x00000010 -#define ABM_DEBUG_10__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_10__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_10__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_10__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_10__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_11__DBG_HG_BIN_SHIFT_FLAG_25_28__SHIFT__SI 0x0000000c -#define ABM_DEBUG_11__DBG_HG_BIN_SHIFT_INDEX_25_28__SHIFT__SI 0x00000010 -#define ABM_DEBUG_11__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_11__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_11__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_11__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_11__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_12__DBG_HG_BIN_SHIFT_FLAG_29_32__SHIFT__SI 0x0000000c -#define ABM_DEBUG_12__DBG_HG_BIN_SHIFT_INDEX_29_32__SHIFT__SI 0x00000010 -#define ABM_DEBUG_12__DBG_HG_DATA_ACTIVE__SHIFT__SI 0x00000002 -#define ABM_DEBUG_12__DBG_HG_FRAME_COUNT__SHIFT__SI 0x00000004 -#define ABM_DEBUG_12__DBG_HG_HBALNK__SHIFT__SI 0x00000001 -#define ABM_DEBUG_12__DBG_HG_UPDATE_DATA__SHIFT__SI 0x00000003 -#define ABM_DEBUG_12__DBG_HG_VBLANK__SHIFT__SI 0x00000000 -#define ABM_DEBUG_ID__ABM_DEBUG_ID__SHIFT__SI 0x00000000 -#define ABM_RBBMIF_RDWR_TIMEOUT__ABM_RBBMIF_RD_WR_TIMEOUT_DIS__SHIFT__SI 0x00000000 -#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT__CI 0x00000008 -#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT__CI 0x00000010 -#define ACTIVITY_MONITOR__ACTIVITY_READING_VALID__SHIFT__SI 0x00000010 -#define ACTIVITY_MONITOR__ACTIVITY_READING__SHIFT__SI 0x00000000 -#define ACTIVITY_THRESHOLDS__LOWERING__SHIFT__SI 0x00000010 -#define ACTIVITY_THRESHOLDS__RAISING__SHIFT__SI 0x00000000 -#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x00000010 -#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x00000000 -#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x00000010 -#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x00000000 -#define ADC_INT_CTRL__HI_THRESHOLD_INT_EN__SHIFT__CI__VI 0x0000000f -#define ADC_INT_CTRL__HI_THRESHOLD__SHIFT__CI__VI 0x00000000 -#define ADC_INT_CTRL__LO_THRESHOLD_INT_EN__SHIFT__CI__VI 0x0000001f -#define ADC_INT_CTRL__LO_THRESHOLD__SHIFT__CI__VI 0x00000010 -#define ADC_RANGE__ADC_MAX__SHIFT__CI__VI 0x00000000 -#define ADC_RANGE__ADC_MIN__SHIFT__CI__VI 0x00000010 -#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT__SI 0x00000000 -#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT__SI 0x00000001 -#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT__SI 0x00000008 -#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT__SI 0x00000014 -#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT__SI 0x0000001c -#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT__SI 0x00000002 -#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT__SI 0x00000003 -#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT__SI 0x00000006 -#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT__SI 0x00000018 -#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT__SI 0x00000010 -#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT__SI 0x00000014 -#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT__SI 0x00000004 -#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT__SI 0x00000000 -#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT__SI 0x00000010 -#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT__SI 0x00000012 -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT__SI 0x00000000 -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT__SI 0x00000004 -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT__SI 0x00000008 -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT__SI 0x0000000c -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT__SI 0x00000010 -#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT__SI 0x00000014 -#define AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT__SI 0x00000008 -#define AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT__SI 0x00000010 -#define AFMT_ACP__AFMT_ACP_TYPE__SHIFT__SI 0x00000000 -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT__SI 0x0000000c -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT__SI 0x00000004 -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT__SI 0x00000010 -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT__SI 0x00000000 -#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT__SI 0x00000008 -#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT__SI 0x00000000 -#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT__SI 0x00000008 -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT__SI 0x00000008 -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT__SI 0x00000010 -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT__SI 0x00000000 -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT__SI 0x0000000b -#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT__SI 0x00000018 -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT__SI 0x00000000 -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT__SI 0x0000000f -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT__SI 0x00000010 -#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT__SI 0x0000000b -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_CS_SOURCE__SHIFT__SI 0x00000004 -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT__SI 0x0000001c -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT__SI 0x00000008 -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT__SI 0x00000000 -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT__SI 0x00000001 -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT__SI 0x00000010 -#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT__SI 0x00000018 -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT__SI 0x0000001a -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT__SI 0x00000018 -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT__SI 0x00000017 -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_MASK__SHIFT__SI 0x00000016 -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT__SI 0x00000000 -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT__SI 0x0000000c -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT__SI 0x0000000e -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT__SI 0x0000001e -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_MASK__SHIFT__SI 0x0000001b -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_FORMAT_WTRIG_ACK__SHIFT__SI 0x0000001d -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_FORMAT_WTRIG_MASK__SHIFT__SI 0x0000001c -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT__SI 0x0000001f -#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT__SI 0x0000000b -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT__SI 0x0000000c -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT__SI 0x0000000a -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT__SI 0x00000000 -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT__SI 0x00000016 -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT__SI 0x0000001c -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT__SI 0x0000001f -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT__SI 0x00000014 -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT__SI 0x0000000f -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT__SI 0x0000001a -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT__SI 0x00000010 -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT__SI 0x00000018 -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT__SI 0x00000008 -#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT__SI 0x0000000d -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT__SI 0x0000000c -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT__SI 0x00000007 -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT__SI 0x00000008 -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT__SI 0x00000010 -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT__SI 0x00000000 -#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT__SI 0x0000000e -#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT__SI 0x00000000 -#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT__SI 0x00000010 -#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT__SI 0x00000000 -#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE0__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE1__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE2__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_0__AFMT_GENERIC0_BYTE3__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE4__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE5__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE6__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_1__AFMT_GENERIC0_BYTE7__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE10__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE11__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE8__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_2__AFMT_GENERIC0_BYTE9__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE12__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE13__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE14__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_3__AFMT_GENERIC0_BYTE15__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE16__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE17__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE18__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_4__AFMT_GENERIC0_BYTE19__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE20__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE21__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE22__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_5__AFMT_GENERIC0_BYTE23__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE24__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE25__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE26__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_6__AFMT_GENERIC0_BYTE27__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE28__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE29__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE30__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_7__AFMT_GENERIC0_BYTE31__SHIFT__SI 0x00000018 -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB0__SHIFT__SI 0x00000000 -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB1__SHIFT__SI 0x00000008 -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB2__SHIFT__SI 0x00000010 -#define AFMT_GENERIC0_HDR__AFMT_GENERIC0_HB3__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE0__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE1__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE2__SHIFT__SI 0x00000010 -#define AFMT_GENERIC1_0__AFMT_GENERIC1_BYTE3__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE4__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE5__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE6__SHIFT__SI 0x00000010 -#define AFMT_GENERIC1_1__AFMT_GENERIC1_BYTE7__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE10__SHIFT__SI 0x00000010 -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE11__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE8__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_2__AFMT_GENERIC1_BYTE9__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE12__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE13__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE14__SHIFT__SI 0x00000010 -#define AFMT_GENERIC1_3__AFMT_GENERIC1_BYTE15__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE16__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE17__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE18__SHIFT__SI 0x00000010 -#define AFMT_GENERIC1_4__AFMT_GENERIC1_BYTE19__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE20__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE21__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE22__SHIFT__SI 0x00000010 -#define AFMT_GENERIC1_5__AFMT_GENERIC1_BYTE23__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE24__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE25__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE26__SHIFT__SI 0x00000010 -#define AFMT_GENERIC1_6__AFMT_GENERIC1_BYTE27__SHIFT__SI 0x00000018 -#define AFMT_GENERIC1_HDR__AFMT_GENERIC1_HB0__SHIFT__SI 0x00000000 -#define AFMT_GENERIC1_HDR__AFMT_GENERIC1_HB1__SHIFT__SI 0x00000008 -#define AFMT_GENERIC1_HDR__AFMT_GENERIC1_HB2__SHIFT__SI 0x00000010 -#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT__SI 0x00000006 -#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT__SI 0x00000007 -#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT__SI 0x0000000a -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_ACK__SHIFT__SI 0x00000008 -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_INT__SHIFT__SI 0x00000002 -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_MASK__SHIFT__SI 0x00000004 -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED_CHG_OCCURRED__SHIFT__SI 0x00000001 -#define AFMT_INTERRUPT_STATUS__AFMT_AZ_HDCP_REQUIRED__SHIFT__SI 0x00000000 -#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT__SI 0x00000006 -#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT__SI 0x00000000 -#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT__SI 0x00000007 -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT__SI 0x00000000 -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT__SI 0x00000008 -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT__SI 0x00000010 -#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT__SI 0x00000018 -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT__SI 0x00000000 -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT__SI 0x00000008 -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT__SI 0x00000010 -#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT__SI 0x00000018 -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT__SI 0x00000010 -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT__SI 0x00000018 -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT__SI 0x00000000 -#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT__SI 0x00000008 -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT__SI 0x00000000 -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT__SI 0x00000008 -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT__SI 0x00000010 -#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT__SI 0x00000018 -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT__SI 0x00000000 -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT__SI 0x00000008 -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT__SI 0x00000010 -#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT__SI 0x00000018 -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT__SI 0x00000000 -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT__SI 0x00000008 -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT__SI 0x00000010 -#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT__SI 0x00000018 -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT__SI 0x00000000 -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT__SI 0x00000008 -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT__SI 0x00000010 -#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT__SI 0x00000018 -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT__SI 0x00000000 -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT__SI 0x00000008 -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT__SI 0x00000010 -#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT__SI 0x00000018 -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT__SI 0x00000000 -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT__SI 0x00000008 -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT__SI 0x00000010 -#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT__SI 0x00000018 -#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT__SI 0x0000000c -#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT__SI 0x00000000 -#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT__SI 0x00000008 -#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT__SI 0x0000001f -#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT__SI 0x00000000 -#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT__SI 0x00000018 -#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT__SI 0x00000000 -#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT__SI 0x00000000 -#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT__SI 0x00000000 -#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT__SI 0x00000004 -#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT__SI 0x00000018 -#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT__SI 0x0000001e -#define AFMT_STATUS__AFMT_AZ_FORMAT_WTRIG_INT__SHIFT__SI 0x0000001d -#define AFMT_STATUS__AFMT_AZ_FORMAT_WTRIG__SHIFT__SI 0x0000001c -#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT__SI 0x00000008 -#define AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT__SI 0x0000000d -#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT__SI 0x00000002 -#define ALU_ADDER_INPUTS__ID1C_ALU_ADDER_INPUT1__SHIFT__SI 0x00000000 -#define ALU_ADDER_INPUTS__ID1C_ALU_ADDER_INPUT2__SHIFT__SI 0x0000000e -#define ALU_ADDER_INPUTS__ID1C_ALU_CARRY__SHIFT__SI 0x0000001c -#define ALU_ADDER_INPUTS__ID1C_ALU_START_PULSE__SHIFT__SI 0x0000001e -#define ALU_ADDER_INPUTS__ID1C_ALU_STATE__SHIFT__SI 0x0000001d -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_CH_START_PHASE_H_INT__SHIFT__SI 0x0000001d -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_H_REP_FAC__SHIFT__SI 0x00000019 -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_HEIGHT__SHIFT__SI 0x0000000b -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_H_HALF_RES__SHIFT__SI 0x00000016 -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_ROTATE__SHIFT__SI 0x00000018 -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_V_HALF_RES__SHIFT__SI 0x00000017 -#define ALU_DISP_PARAM1__ID1D_ALU_DISP_VGA_WIDTH__SHIFT__SI 0x00000000 -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_H_FRAC__SHIFT__SI 0x00000008 -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_H_INT__SHIFT__SI 0x00000004 -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_V_FRAC_BOT__SHIFT__SI 0x00000019 -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_V_FRAC__SHIFT__SI 0x00000012 -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_START_PHASE_V_INT__SHIFT__SI 0x0000000f -#define ALU_DISP_PARAM2__ID1E_ALU_DISP_V_REP_FAC__SHIFT__SI 0x00000000 -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_H_REP_FAC__SHIFT__SI 0x00000003 -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_H_SHARP_FAC__SHIFT__SI 0x00000006 -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_START_PHASE_V_INT_BOT__SHIFT__SI 0x00000000 -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_TOP_OVERSCAN__SHIFT__SI 0x0000000c -#define ALU_DISP_PARAM3__ID1F_ALU_DISP_V_SHARP_FAC__SHIFT__SI 0x00000009 -#define ALU_DISP_PARAM3__ID1F_ALU_DxNUM_H_TAP__SHIFT__SI 0x0000001c -#define ALU_DISP_PARAM3__ID1F_ALU_DxNUM_TAP_CHROMA__SHIFT__SI 0x00000018 -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_ACTIVE__SHIFT__SI 0x00000019 -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DISP_LEFT_OVERSCAN__SHIFT__SI 0x00000000 -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DISP_RIGHT_OVESCAN__SHIFT__SI 0x0000000b -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DONE_PULSE__SHIFT__SI 0x0000001f -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_DONE__SHIFT__SI 0x00000018 -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_GRANTED__SHIFT__SI 0x00000016 -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_START_LINE_DEL__SHIFT__SI 0x0000001d -#define ALU_DISP_PARAM4_AND_STATE__ID20_ALU_START_LINE__SHIFT__SI 0x0000001b -#define ALU_DISP_PARAM5__ID23_ALU_DISP_BOT_OVERSCAN__SHIFT__SI 0x0000000e -#define ALU_DISP_PARAM5__ID23_DISP_EOL__SHIFT__SI 0x0000001e -#define ALU_DISP_PARAM5__ID23_DISP_SOF__SHIFT__SI 0x0000001f -#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT__CI__VI 0x00000008 -#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT__CI__VI 0x00000010 -#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT__CI__VI 0x00000002 -#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT__CI__VI 0x00000001 -#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT__CI__VI 0x00000002 -#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT__CI__VI 0x00000011 -#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT__CI__VI 0x0000000e -#define ATC_ATS_DEBUG__EXE_BIT__SHIFT__CI__VI 0x00000007 -#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT__CI__VI 0x00000001 -#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT__CI__VI 0x0000000f -#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT__CI__VI \ - 0x00000010 -#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT__CI__VI 0x0000000a -#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT__CI__VI 0x00000005 -#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT__CI__VI 0x00000008 -#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT__CI__VI 0x00000006 -#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT__CI__VI 0x00000009 -#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT__CI 0x00000002 -#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT__CI__VI 0x00000014 -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT__CI__VI 0x0000000a -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT__CI__VI 0x00000008 -#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT__CI__VI 0x00000010 -#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT__CI__VI 0x00000010 -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT__CI__VI 0x0000000f -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT__CI__VI 0x00000011 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT__CI__VI 0x00000018 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT__CI__VI 0x00000012 -#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT__CI__VI 0x00000013 -#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT__CI__VI 0x0000000a -#define ATC_ATS_STATUS__BUSY__SHIFT__CI__VI 0x00000000 -#define ATC_ATS_STATUS__CRASHED__SHIFT__CI__VI 0x00000001 -#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT__CI__VI 0x00000002 -#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT__CI__VI 0x0000000c -#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT__CI__VI 0x00000014 -#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT__CI__VI 0x0000001c -#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT__CI__VI 0x0000001f -#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT__CI__VI 0x00000000 -#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT__CI__VI 0x00000001 -#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT__CI__VI 0x00000004 -#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT__CI__VI 0x00000008 -#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT__CI__VI 0x0000001e -#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT__CI__VI 0x00000008 -#define ATC_L1RD_STATUS__BUSY__SHIFT__CI__VI 0x00000000 -#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT__CI__VI 0x00000001 -#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT__CI__VI 0x0000000c -#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT__CI__VI 0x00000014 -#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT__CI__VI 0x0000001c -#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT__CI__VI 0x0000001f -#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT__CI__VI 0x00000000 -#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT__CI__VI 0x00000001 -#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT__CI__VI 0x00000004 -#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT__CI__VI 0x00000008 -#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT__CI__VI 0x0000001e -#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT__CI__VI 0x00000008 -#define ATC_L1WR_STATUS__BUSY__SHIFT__CI__VI 0x00000000 -#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT__CI__VI 0x00000001 -#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT__CI__VI 0x00000000 -#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT__CI__VI 0x00000000 -#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT__CI__VI 0x00000002 -#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT__CI__VI 0x00000004 -#define ATC_L2_CNTL2__BANK_SELECT__SHIFT__CI__VI 0x00000000 -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT__CI__VI 0x00000008 -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT__CI__VI 0x00000009 -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT__CI__VI 0x00000006 -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT__CI__VI 0x0000000f -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT__CI__VI 0x0000000c -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT__CI__VI 0x00000008 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT__CI__VI 0x00000000 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT__CI__VI 0x00000009 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT__CI__VI 0x00000004 -#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT__CI__VI 0x0000000f -#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT__CI__VI 0x00000011 -#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT__CI__VI 0x0000000e -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT__CI 0x0000000b -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT__CI 0x0000000c -#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT__CI 0x0000000a -#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT__CI__VI 0x00000000 -#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT__CI__VI 0x00000005 -#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT__CI__VI 0x00000008 -#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT__CI__VI 0x00000009 -#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT__CI__VI 0x00000000 -#define ATC_MISC_CG__ENABLE__SHIFT__CI__VI 0x00000012 -#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT__CI__VI 0x00000013 -#define ATC_MISC_CG__OFFDLY__SHIFT__CI__VI 0x00000006 -#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT__CI__VI 0x00000000 -#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT__CI__VI 0x0000001f -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000000 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT__CI__VI 0x0000000a -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT__CI__VI 0x0000000b -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT__CI__VI 0x0000000c -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT__CI__VI 0x0000000d -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT__CI__VI 0x0000000e -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT__CI__VI 0x0000000f -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000001 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000002 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000003 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000004 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000005 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000006 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000007 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000008 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT__CI__VI 0x00000009 -#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT__CI__VI 0x00000000 -#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT__CI__VI 0x00000000 -#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT__CI__VI 0x00000000 -#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT__CI__VI 0x00000000 -#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT__CI__VI 0x00000000 -#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT__CI__VI 0x00000000 -#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT__CI__VI 0x00000000 -#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT__CI__VI 0x00000000 -#define ATTR00__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR01__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR02__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR03__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR04__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR05__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR06__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR07__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR08__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR09__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR0A__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR0B__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR0C__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR0D__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR0E__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR0F__ATTR_PAL__SHIFT__SI 0x00000000 -#define ATTR10__ATTR_BLINK_EN__SHIFT__SI 0x00000003 -#define ATTR10__ATTR_CSEL_EN__SHIFT__SI 0x00000007 -#define ATTR10__ATTR_GRPH_MODE__SHIFT__SI 0x00000000 -#define ATTR10__ATTR_LGRPH_EN__SHIFT__SI 0x00000002 -#define ATTR10__ATTR_MONO_EN__SHIFT__SI 0x00000001 -#define ATTR10__ATTR_PANTOPONLY__SHIFT__SI 0x00000005 -#define ATTR10__ATTR_PCLKBY2__SHIFT__SI 0x00000006 -#define ATTR11__ATTR_OVSC__SHIFT__SI 0x00000000 -#define ATTR12__ATTR_MAP_EN__SHIFT__SI 0x00000000 -#define ATTR12__ATTR_VSMUX__SHIFT__SI 0x00000004 -#define ATTR13__ATTR_PPAN__SHIFT__SI 0x00000000 -#define ATTR14__ATTR_CSEL1__SHIFT__SI 0x00000000 -#define ATTR14__ATTR_CSEL2__SHIFT__SI 0x00000002 -#define ATTRDR__ATTR_DATA__SHIFT__SI 0x00000000 -#define ATTRDW__ATTR_DATA__SHIFT__SI 0x00000000 -#define ATTRX__ATTR_IDX__SHIFT__SI 0x00000000 -#define ATTRX__ATTR_PAL_RW_ENB__SHIFT__SI 0x00000005 -#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI 0x00000018 -#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AUTH_STATE__STATE__SHIFT 0x00000000 -#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT__SI 0x0000000a -#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT__SI 0x00000009 -#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_POLARITY__SHIFT__SI 0x0000000c -#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT__SI 0x00000008 -#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT__SI 0x00000000 -#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT__SI 0x0000001c -#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT__SI 0x00000018 -#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT__SI 0x00000014 -#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT__SI 0x00000010 -#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT__SI 0x0000000a -#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT__SI 0x00000009 -#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_POLARITY__SHIFT__SI 0x0000000c -#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT__SI 0x00000008 -#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT__SI 0x00000000 -#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT__SI 0x0000001c -#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT__SI 0x00000018 -#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT__SI 0x00000014 -#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT__SI 0x00000010 -#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT__SI 0x00000000 -#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT__SI 0x00000019 -#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT__SI 0x00000018 -#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT__SI 0x00000018 -#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT__SI 0x0000000a -#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT__SI 0x00000008 -#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT__SI 0x00000002 -#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT__SI 0x00000011 -#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT__SI 0x00000010 -#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT__SI 0x00000010 -#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT__SI 0x0000001d -#define AUX_CONTROL__AUX_EN__SHIFT__SI 0x00000000 -#define AUX_CONTROL__AUX_HPD_SEL__SHIFT__SI 0x00000014 -#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT__SI 0x00000010 -#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT__SI 0x00000018 -#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT__SI 0x00000008 -#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT__SI 0x0000000c -#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT__SI 0x00000012 -#define AUX_CONTROL__AUX_TEST_MODE__SHIFT__SI 0x0000001c -#define AUX_CONTROL__SPARE_0__SHIFT__SI 0x0000001e -#define AUX_CONTROL__SPARE_1__SHIFT__SI 0x0000001f -#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT__SI 0x00000011 -#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT__SI 0x00000012 -#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT__SI 0x00000013 -#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT__SI 0x0000001c -#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT__SI 0x0000000c -#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT__SI 0x00000014 -#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT__SI 0x00000008 -#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT__SI 0x00000004 -#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT__SI 0x00000018 -#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT__SI 0x00000010 -#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT__SI 0x00000000 -#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT__SI 0x00000010 -#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT__SI 0x00000015 -#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT__SI 0x00000000 -#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT__SI 0x00000008 -#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT__SI 0x00000000 -#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT__SI 0x00000008 -#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT__SI 0x00000004 -#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT__SI 0x00000010 -#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT__SI 0x00000000 -#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT__SI 0x00000000 -#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT__SI 0x00000010 -#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT__SI 0x00000004 -#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT__SI 0x00000005 -#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT__SI 0x00000004 -#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT__SI 0x00000006 -#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT__SI 0x00000001 -#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT__SI 0x00000000 -#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT__SI 0x00000002 -#define AUX_LS_DATA__AUX_LS_DATA__SHIFT__SI 0x00000008 -#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT__SI 0x00000010 -#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT__SI 0x0000001d -#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT__SI 0x00000000 -#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT__SI 0x00000009 -#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT__SI 0x0000000b -#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT__SI 0x00000018 -#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT__SI 0x00000001 -#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT__SI 0x00000013 -#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT__SI 0x0000000e -#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT__SI 0x0000000c -#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT__SI 0x00000008 -#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT__SI 0x0000000a -#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT__SI 0x00000016 -#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT__SI 0x00000017 -#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT__SI 0x00000014 -#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT__SI 0x00000012 -#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT__SI 0x00000011 -#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT__SI 0x00000004 -#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT__SI 0x00000007 -#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT__SI 0x0000001f -#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT__SI 0x0000001e -#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT__SI 0x00000002 -#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT__SI 0x00000000 -#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT__SI 0x00000004 -#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT__SI 0x00000010 -#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT__SI 0x0000001f -#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT__SI 0x00000000 -#define AUX_SW_DATA__AUX_SW_DATA__SHIFT__SI 0x00000008 -#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT__SI 0x00000010 -#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT__SI 0x0000001e -#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT__SI 0x00000000 -#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT__SI 0x00000009 -#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT__SI 0x0000000b -#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT__SI 0x00000018 -#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT__SI 0x00000001 -#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT__SI 0x00000013 -#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT__SI 0x0000000e -#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT__SI 0x0000000c -#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT__SI 0x00000008 -#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT__SI 0x0000000a -#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT__SI 0x00000016 -#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT__SI 0x00000017 -#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT__SI 0x00000014 -#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT__SI 0x00000012 -#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT__SI 0x00000011 -#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT__SI 0x00000004 -#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT__SI 0x00000007 -#define AVP_BCKN_OVL__LINE_ADVANCED_CNT__SHIFT__SI 0x00000010 -#define AVP_BCKN_OVL__OVL_UPDATE_TAKEN__SHIFT__SI 0x00000001 -#define AVP_BCKN_OVL__OVL_VBLANK__SHIFT__SI 0x00000000 -#define AVP_CONFIG__AVP_RDREQ_URG__SHIFT__SI 0x00000008 -#define AVP_CONFIG__AVP_REQ_TRAN__SHIFT__SI 0x00000010 -#define AVP_RLC_CONTROL__RLC_REQ_ACK__SHIFT__SI 0x00000004 -#define AVP_RLC_CONTROL__RLC_REQ_TYPE__SHIFT__SI 0x00000000 -#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT__SI \ - 0x00000000 -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_DTO_SOURCE_SEL__SHIFT__SI 0x0000000c -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT__SI 0x00000008 -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FS_DIV_SEL__SHIFT__SI 0x00000004 -#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_XTAL_X2__SHIFT__SI 0x00000000 -#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT__SI 0x00000010 -#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT__SI 0x00000000 -#define AZALIA_BDL_DMA_CONTROL__DBL_DMA_ISOCHRONOUS__SHIFT__SI 0x00000004 -#define AZALIA_BDL_DMA_CONTROL__DBL_DMA_NON_SNOOP__SHIFT__SI 0x00000000 -#define AZALIA_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT__SI 0x00000004 -#define AZALIA_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT__SI 0x00000000 -#define AZALIA_CODEC_CONTROL__AZALIA_FORCE_CONSUMER_MODE__SHIFT__SI 0x00000000 -#define AZALIA_CODEC_CONTROL__WALL_CLOCKS_PER_WRITE_TRIGGER__SHIFT__SI 0x00000004 -#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT__SI 0x00000004 -#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT__SI 0x00000000 -#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT__SI 0x00000000 -#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT__SI 0x00000000 -#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT__SI 0x00000000 -#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT__SI 0x00000010 -#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT__SI 0x00000011 -#define AZALIA_DATA_DMA_CONTROL__DATA_BUFFER_SIZE_SEL__SHIFT__SI 0x0000000f -#define AZALIA_DATA_DMA_CONTROL__DATA_BUFFER_SIZE__SHIFT__SI 0x00000008 -#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT__SI 0x00000004 -#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_A__AZALIA_DEBUG_A__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_B__AZALIA_DEBUG_B__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_C__AZALIA_DEBUG_C__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_D__AZALIA_DEBUG_D__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_E__AZALIA_DEBUG_E__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_F__AZALIA_DEBUG_F__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_G__AZALIA_DEBUG_G__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_H__AZALIA_DEBUG_H__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_ID__AZALIA_DEBUG_ID__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_I__AZALIA_DEBUG_I__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_J__AZALIA_DEBUG_J__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_K__AZALIA_DEBUG_K__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_L__AZALIA_DEBUG_L__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_M__AZALIA_DEBUG_M__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_N__AZALIA_DEBUG_N__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_O__AZALIA_DEBUG_O__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_P__AZALIA_DEBUG_P__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_Q__AZALIA_DEBUG_Q__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_R__AZALIA_DEBUG_R__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG_S__AZALIA_DEBUG_S__SHIFT__SI 0x00000000 -#define AZALIA_DEBUG__AZALIA_DEBUG__SHIFT__SI 0x00000000 -#define AZALIA_DRM_COMMAND__COMMIT__SHIFT__SI 0x0000001f -#define AZALIA_DRM_COMMAND__GEN_MASK__SHIFT__SI 0x00000009 -#define AZALIA_DRM_COMMAND__PACKET_TYPE__SHIFT__SI 0x00000000 -#define AZALIA_DRM_COMMAND__UNWRAP_KEY__SHIFT__SI 0x00000008 -#define AZALIA_DRM_MASK_FIFO_STATUS__MASK_FIFO_ACK__SHIFT__SI 0x00000004 -#define AZALIA_DRM_MASK_FIFO_STATUS__MASK_FIFO_STATUS__SHIFT__SI 0x00000000 -#define AZALIA_DRM_PAYLOAD0__PAYLOAD0__SHIFT__SI 0x00000000 -#define AZALIA_DRM_PAYLOAD1__PAYLOAD1__SHIFT__SI 0x00000000 -#define AZALIA_DRM_PAYLOAD2__PAYLOAD2__SHIFT__SI 0x00000000 -#define AZALIA_DRM_PAYLOAD3__PAYLOAD3__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI \ - 0x00000009 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI \ - 0x0000000b -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI \ - 0x00000009 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI \ - 0x0000000b -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI \ - 0x00000005 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F0_CODEC_CONVERTER123_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID0__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID1__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID3__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID0__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID1__SHIFT__SI 0x0000000c -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID2__SHIFT__SI 0x00000014 -#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID3__SHIFT__SI 0x0000001c -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT__SI \ - 0x00000018 -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_INDEX__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__ACP_TYPE__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI \ - 0x00000018 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT__SI 0x0000001f -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT__SI 0x00000011 -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT__SI 0x00000012 -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT__SI 0x0000001b -#define AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE_CHANGED__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_CAPABLE__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_DISABLE_UR_CAPABLE__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_PIN0_CONTROL_DRM__DRM_ENABLE_UR_CAPABLE__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE_CHANGED__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_CAPABLE__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_DISABLE_UR_CAPABLE__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ENABLE_UR_CAPABLE__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_REQUIRED__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT__SI \ - 0x00000004 -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT__SI \ - 0x0000000c -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT__SI \ - 0x00000014 -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT__SI \ - 0x0000001c -#define AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT__SI \ - 0x00000018 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY0_ID__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY0_TYPE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY1_ID__SHIFT__SI 0x0000000a -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY1_TYPE__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY2_ID__SHIFT__SI 0x00000012 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY2_TYPE__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY3_ID__SHIFT__SI 0x0000001a -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__DISPLAY3_TYPE__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY4_ID__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY4_TYPE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY5_ID__SHIFT__SI 0x0000000a -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__DISPLAY5_TYPE__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER__NUMBER_OF_DISPLAY_ID__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI 0x00000009 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI 0x0000000b -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__HDMI__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT__SI 0x00000003 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT__SI 0x00000002 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI 0x00000009 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI 0x0000000b -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__HDMI__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT__SI 0x00000003 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT__SI 0x00000005 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT__SI \ - 0x00000002 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT__SI 0x00000004 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT__SI 0x00000001 -#define AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000008 -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000018 -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE0__SHIFT__SI 0x00000007 -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE1__SHIFT__SI 0x0000000f -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE2__SHIFT__SI 0x00000017 -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE3__SHIFT__SI 0x0000001f -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG0__SHIFT__SI 0x00000000 -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG1__SHIFT__SI 0x00000008 -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG2__SHIFT__SI 0x00000010 -#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG3__SHIFT__SI 0x00000018 -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE0__SHIFT__SI 0x00000006 -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE1__SHIFT__SI 0x0000000e -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE2__SHIFT__SI 0x00000016 -#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE3__SHIFT__SI 0x0000001e -#define AZALIA_F0_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__AZALIA_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT__SI \ - 0x00000000 -#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI \ - 0x00000009 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI \ - 0x00000009 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI \ - 0x00000009 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT__SI 0x0000000f -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__CC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__L__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__V__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI \ - 0x00000009 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI \ - 0x0000000b -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT__SI \ - 0x00000018 -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_DATA__ACP_DATA__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__ACP_INDEX__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__SUPPORTS_AI__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT__SI 0x00000010 -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT__SI \ - 0x00000018 -#define AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN0_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN0_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE_CHANGED__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_ACTIVE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_CAPABLE__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_DISABLE_UR_CAPABLE__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_PIN0_CONTROL_DRM__DRM_ENABLE_UR_CAPABLE__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HBR__HBR_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HBR__HBR_ENABLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE_CHANGED__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ACTIVE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_CAPABLE__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_DISABLE_UR_CAPABLE__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_ENABLE_UR_CAPABLE__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__HDCP_REQUIRED__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN0_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT__SI \ - 0x00000009 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN0_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_DATA__VIDEO_ID_DATA__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_INDEX__VIDEO_ID_INDEX__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI 0x00000009 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI 0x0000000b -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT__SI 0x00000010 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__HDMI__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN0_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F2_CODEC_PIN1_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN1_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN1_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI 0x00000009 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI 0x0000000b -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT__SI 0x00000010 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__HDMI__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN1_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F2_CODEC_PIN2_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN2_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN2_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI 0x00000009 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI 0x0000000b -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT__SI 0x00000010 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__HDMI__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN2_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT__SI 0x0000000c -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT__SI \ - 0x00000004 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT__SI \ - 0x00000014 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT__SI 0x00000018 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT__SI \ - 0x0000001e -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT__SI 0x0000001f -#define AZALIA_F2_CODEC_PIN3_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN3_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN3_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT__SI \ - 0x00000003 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT__SI \ - 0x00000010 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT__SI \ - 0x00000008 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT__SI 0x00000009 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000001 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT__SI 0x0000000b -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT__SI \ - 0x00000002 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT__SI \ - 0x0000000a -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT__SI \ - 0x00000006 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT__SI 0x00000014 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT__SI \ - 0x00000007 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT__SI 0x00000006 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT__SI 0x00000010 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__HDMI__SHIFT__SI 0x00000007 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT__SI 0x00000003 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT__SI 0x00000000 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT__SI 0x00000005 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT__SI 0x00000002 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT__SI 0x00000004 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT__SI 0x00000001 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT__SI 0x00000008 -#define AZALIA_F2_CODEC_PIN3_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT__SI \ - 0x00000000 -#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT__SI \ - 0x00000000 -#define AZALIA_HDCP_REQUIRED__HDCP_REQUIRED_BY_VIDEO_DRIVER__SHIFT__SI 0x00000000 -#define AZALIA_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT__SI 0x0000001f -#define AZALIA_HOT_PLUG_CONTROL__AZALIA_FORCE_CODEC_WAKE__SHIFT__SI 0x00000000 -#define AZALIA_HOT_PLUG_CONTROL__CODEC_HOT_PLUG_ENABLE__SHIFT__SI 0x0000000c -#define AZALIA_HOT_PLUG_CONTROL__FORCE_AUDIO_ENABLE_TO_HDMI__SHIFT__SI 0x00000010 -#define AZALIA_HOT_PLUG_CONTROL__FORCE_FIFO_ERROR__SHIFT__SI 0x00000015 -#define AZALIA_HOT_PLUG_CONTROL__IGNORE_CONTROLLER_CODEC_FORMAT_MISMATCH__SHIFT__SI 0x00000014 -#define AZALIA_HOT_PLUG_CONTROL__PIN0_AUDIO_ENABLED__SHIFT__SI 0x00000018 -#define AZALIA_HOT_PLUG_CONTROL__PIN0_JACK_DETECTION_ENABLE__SHIFT__SI 0x00000004 -#define AZALIA_HOT_PLUG_CONTROL__PIN0_UNSOLICITED_RESPONSE_ENABLE__SHIFT__SI 0x00000008 -#define AZALIA_HOT_PLUG_CONTROL__PIN1_AUDIO_ENABLED__SHIFT__SI 0x00000019 -#define AZALIA_HOT_PLUG_CONTROL__PIN1_JACK_DETECTION_ENABLE__SHIFT__SI 0x00000005 -#define AZALIA_HOT_PLUG_CONTROL__PIN1_UNSOLICITED_RESPONSE_ENABLE__SHIFT__SI 0x00000009 -#define AZALIA_HOT_PLUG_CONTROL__PIN2_AUDIO_ENABLED__SHIFT__SI 0x0000001a -#define AZALIA_HOT_PLUG_CONTROL__PIN2_JACK_DETECTION_ENABLE__SHIFT__SI 0x00000006 -#define AZALIA_HOT_PLUG_CONTROL__PIN2_UNSOLICITED_RESPONSE_ENABLE__SHIFT__SI 0x0000000a -#define AZALIA_HOT_PLUG_CONTROL__PIN3_AUDIO_ENABLED__SHIFT__SI 0x0000001b -#define AZALIA_HOT_PLUG_CONTROL__PIN3_JACK_DETECTION_ENABLE__SHIFT__SI 0x00000007 -#define AZALIA_HOT_PLUG_CONTROL__PIN3_UNSOLICITED_RESPONSE_ENABLE__SHIFT__SI 0x0000000b -#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT__SI 0x00000000 -#define AZALIA_POWER_MANAGEMENT_CONTROL__AZALIA_BUSY_CONTROL__SHIFT__SI 0x00000008 -#define AZALIA_POWER_MANAGEMENT_CONTROL__CODEC_WAKE_ON_POWER_TRANSITION__SHIFT__SI 0x00000004 -#define AZALIA_POWER_MANAGEMENT_CONTROL__D3_RESET_ENABLE__SHIFT__SI 0x0000000c -#define AZALIA_POWER_MANAGEMENT_CONTROL__RESET_ON_POWER_TRANSITION__SHIFT__SI 0x00000000 -#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT__SI 0x00000004 -#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT__SI 0x00000000 -#define AZALIA_RIRB_INTERRUPT_CONTROL__AZALIA_EMULATE_LINK_EN__SHIFT__SI 0x00000000 -#define AZALIA_RIRB_INTERRUPT_CONTROL__AZALIA_INTERRUPT_ON_INVALID_COMMAND__SHIFT__SI 0x00000008 -#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT__SI 0x00000000 -#define AZALIA_UNSOLICITED_RESPONSE__PIN0_UNSOLICITED_RESPONSE_FORCE__SHIFT__SI 0x0000001c -#define AZALIA_UNSOLICITED_RESPONSE__PIN1_UNSOLICITED_RESPONSE_FORCE__SHIFT__SI 0x0000001d -#define AZALIA_UNSOLICITED_RESPONSE__PIN2_UNSOLICITED_RESPONSE_FORCE__SHIFT__SI 0x0000001e -#define AZALIA_UNSOLICITED_RESPONSE__PIN3_UNSOLICITED_RESPONSE_FORCE__SHIFT__SI 0x0000001f -#define AZALIA_UNSOLICITED_RESPONSE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT__SI 0x00000000 -#define AZALIA_WALL_CLOCK_LOAD__AZALIA_WALL_CLOCK_LOAD__SHIFT__SI 0x00000000 -#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT__SI 0x00000000 -#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT__CI__VI 0x00000002 -#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT__CI__VI 0x00000001 -#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT__CI__VI 0x00000000 -#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT__CI__VI 0x00000007 -#define BACO_CNTL__BACO_BCLK_OFF__SHIFT__CI__VI 0x00000001 -#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT__CI__VI 0x00000011 -#define BACO_CNTL__BACO_EN__SHIFT__CI__VI 0x00000000 -#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT__CI__VI 0x00000005 -#define BACO_CNTL__BACO_ISO_DIS__SHIFT__CI__VI 0x00000002 -#define BACO_CNTL__BACO_MODE__SHIFT__CI__VI 0x00000006 -#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT__CI__VI 0x00000010 -#define BACO_CNTL__BACO_POWER_OFF__SHIFT__CI__VI 0x00000003 -#define BACO_CNTL__BACO_RESET_EN__SHIFT__CI__VI 0x00000004 -#define BACO_CNTL__PWRGOOD_BF__SHIFT__CI__VI 0x00000009 -#define BACO_CNTL__PWRGOOD_DVO__SHIFT__CI__VI 0x0000000c -#define BACO_CNTL__PWRGOOD_GPIO__SHIFT__CI__VI 0x0000000a -#define BACO_CNTL__PWRGOOD_MEM__SHIFT__CI__VI 0x0000000b -#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT__CI__VI 0x00000008 -#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x00000000 -#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x00000000 -#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x00000000 -#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x00000000 -#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x00000000 -#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x00000000 -#define BASE_CLASS__BASE_CLASS__SHIFT 0x00000000 -#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000 -#define BIF_AVP_FB_FLUSH__BIF_AVP_FB_FLUSH_DONE__SHIFT__SI 0x00000000 -#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT__CI__VI 0x00000000 -#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT__CI__VI 0x00000000 -#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT__CI 0x00000001 -#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT__CI 0x00000000 -#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x00000000 -#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x00000008 -#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x00000000 -#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x00000011 -#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x00000010 -#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x00000000 -#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x00000008 -#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x00000010 -#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x00000018 -#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x00000000 -#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x00000008 -#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x00000010 -#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x00000018 -#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x00000000 -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT__CI__VI 0x00000010 -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT__CI__VI 0x00000005 -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT__CI__VI 0x00000001 -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT__CI__VI 0x0000000a -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT__CI__VI 0x0000000f -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT__CI__VI 0x00000006 -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT__CI__VI 0x0000000b -#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT__SI__CI 0x00000000 -#define BIF_CLOCK_CNTL__TXCLK_PLL_SEL__SHIFT__SI 0x00000000 -#define BIF_CLOCK_CNTL__TXCLK_PLL_STATUS__SHIFT__SI 0x00000001 -#define BIF_CP_FB_FLUSH__BIF_CP_FB_FLUSH_DONE__SHIFT__SI 0x00000000 -#define BIF_DCT_FB_FLUSH__BIF_DCT_FB_FLUSH_DONE__SHIFT__SI 0x00000000 -#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x00000004 -#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x00000005 -#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x00000000 -#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x00000008 -#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x00000010 -#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x00000018 -#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x00000001 -#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x00000002 -#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x00000003 -#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x00000007 -#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x0000001e -#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x00000006 -#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x00000000 -#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x00000008 -#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x00000000 -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT__CI__VI 0x00000000 -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT__CI__VI 0x00000008 -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT__CI__VI 0x00000010 -#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT__CI__VI 0x00000018 -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT__CI__VI 0x00000000 -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT__CI__VI 0x00000008 -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT__CI__VI 0x00000010 -#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT__CI__VI 0x00000018 -#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT__CI__VI 0x00000003 -#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT__CI__VI 0x00000000 -#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT__CI__VI 0x00000001 -#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT__CI__VI 0x00000002 -#define BIF_FB_EN__FB_READ_EN__SHIFT 0x00000000 -#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x00000001 -#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT__CI__VI 0x00000003 -#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT__CI__VI 0x00000002 -#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT__CI__VI 0x00000008 -#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT__CI__VI 0x00000000 -#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT__CI__VI 0x00000007 -#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT__CI__VI 0x00000005 -#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT__CI__VI 0x00000006 -#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT__CI__VI 0x00000001 -#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT__CI__VI 0x00000004 -#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT__CI__VI 0x00000000 -#define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT__CI__VI 0x0000001d -#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT__CI__VI 0x00000004 -#define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT__CI__VI 0x00000007 -#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT__CI__VI 0x00000008 -#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT__CI__VI 0x0000000c -#define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT__CI__VI 0x00000000 -#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT__CI__VI 0x00000003 -#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT__CI__VI 0x0000001c -#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT__CI__VI 0x00000012 -#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT__CI__VI 0x00000013 -#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT__CI__VI 0x00000014 -#define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT__CI__VI 0x00000006 -#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT__CI__VI 0x0000000d -#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT__CI__VI 0x00000011 -#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT__CI__VI 0x0000000d -#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT__CI__VI 0x00000000 -#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT__CI__VI 0x0000000e -#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT__CI__VI 0x00000014 -#define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT__CI__VI 0x00000001 -#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT__CI__VI 0x00000008 -#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT__CI__VI 0x0000000f -#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT__CI__VI 0x00000002 -#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT__CI__VI 0x00000003 -#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT__CI__VI 0x0000001a -#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT__CI__VI 0x00000008 -#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT__CI__VI 0x0000000c -#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT__CI__VI 0x00000000 -#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT__CI__VI 0x00000003 -#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT__CI__VI 0x0000001c -#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT__CI__VI 0x00000012 -#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT__CI__VI 0x00000013 -#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT__CI__VI 0x00000014 -#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT__CI__VI 0x0000000d -#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT__CI__VI 0x00000011 -#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT__CI__VI 0x00000008 -#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT__CI__VI 0x0000000c -#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT__CI__VI 0x00000000 -#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT__CI__VI 0x00000003 -#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT__CI__VI 0x0000001c -#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT__CI__VI 0x00000012 -#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT__CI__VI 0x00000013 -#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT__CI__VI 0x00000014 -#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT__CI__VI 0x0000000d -#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT__CI__VI 0x00000011 -#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT__CI 0x00000000 -#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT__CI__VI 0x00000000 -#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT__CI__VI 0x00000000 -#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT__CI__VI 0x00000000 -#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT__CI__VI 0x00000001 -#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT__CI__VI 0x00000002 -#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT__CI__VI 0x00000008 -#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT__CI__VI 0x0000000d -#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT__CI 0x00000000 -#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT__CI 0x00000003 -#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT__CI 0x00000006 -#define BIF_PINSTRAP0__STRAP_BIF_AUDIO_EN__SHIFT__SI 0x00000001 -#define BIF_PINSTRAP0__STRAP_BIF_BIOS_ROM_EN__SHIFT__SI 0x00000011 -#define BIF_PINSTRAP0__STRAP_BIF_CLK_PM_EN__SHIFT__SI 0x0000000c -#define BIF_PINSTRAP0__STRAP_BIF_DBG_I2C_EN__SHIFT__SI 0x00000002 -#define BIF_PINSTRAP0__STRAP_BIF_ECN1P1_DIS__SHIFT__SI 0x00000013 -#define BIF_PINSTRAP0__STRAP_BIF_ERR_REPORTING_DIS__SHIFT__SI 0x0000000b -#define BIF_PINSTRAP0__STRAP_BIF_FORCE_COMPLIANCE_A__SHIFT__SI 0x00000008 -#define BIF_PINSTRAP0__STRAP_BIF_GEN2_EN_A__SHIFT__SI 0x00000003 -#define BIF_PINSTRAP0__STRAP_BIF_MEM_AP_SIZE__SHIFT__SI 0x0000000e -#define BIF_PINSTRAP0__STRAP_BIF_MSI_DIS__SHIFT__SI 0x0000000a -#define BIF_PINSTRAP0__STRAP_BIF_REG_AP_SIZE1__SHIFT__SI 0x00000009 -#define BIF_PINSTRAP0__STRAP_BIF_RESERVED0__SHIFT__SI 0x00000006 -#define BIF_PINSTRAP0__STRAP_BIF_RESERVED1__SHIFT__SI 0x00000007 -#define BIF_PINSTRAP0__STRAP_BIF_RESERVED2__SHIFT__SI 0x00000012 -#define BIF_PINSTRAP0__STRAP_BIF_RX_PLL_CALIB_BYPASS__SHIFT__SI 0x00000000 -#define BIF_PINSTRAP0__STRAP_BIF_VGA_DIS__SHIFT__SI 0x0000000d -#define BIF_PINSTRAP0__STRAP_PHY_TX_DEEMPH_EN__SHIFT__SI 0x00000004 -#define BIF_PINSTRAP0__STRAP_PHY_TX_PWRS_ENB__SHIFT__SI 0x00000005 -#define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT__CI__VI 0x00000000 -#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT__CI 0x00000002 -#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT__CI__VI 0x00000001 -#define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT__CI__VI 0x00000000 -#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT__CI 0x00000002 -#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT__CI__VI 0x00000001 -#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT__CI 0x00000002 -#define BIF_RESET_CNTL__RST_DONE__SHIFT__CI 0x00000001 -#define BIF_RESET_CNTL__STRAP_EN__SHIFT__CI 0x00000000 -#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT__CI 0x00000016 -#define BIF_RESET_EN__CFG_RESET_EN__SHIFT__SI__CI 0x00000006 -#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT__SI__CI 0x0000000c -#define BIF_RESET_EN__COR_RESET_EN__SHIFT__SI__CI 0x00000003 -#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT__SI__CI 0x00000012 -#define BIF_RESET_EN__DRV_RESET_EN__SHIFT__SI__CI 0x00000007 -#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT__CI 0x00000017 -#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT__CI 0x0000001a -#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT__CI 0x00000018 -#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT__CI 0x0000001c -#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT__CI 0x00000019 -#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT__CI 0x0000001e -#define BIF_RESET_EN__HOT_RESET_EN__SHIFT__SI__CI 0x00000009 -#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT__SI__CI 0x0000000a -#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT__SI__CI 0x0000000b -#define BIF_RESET_EN__PHY_RESET_EN__SHIFT__SI__CI 0x00000002 -#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT__CI 0x00000014 -#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT__CI 0x00000015 -#define BIF_RESET_EN__REG_RESET_EN__SHIFT__SI__CI 0x00000004 -#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT__SI__CI 0x00000008 -#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT__CI 0x00000001 -#define BIF_RESET_EN__STY_RESET_EN__SHIFT__SI__CI 0x00000005 -#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT__CI__VI 0x00000001 -#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_IMPRST_CNTL__REG_RST_warmRstImpEn__SHIFT__CI 0x00000001 -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT__CI 0x00000002 -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT__CI__VI 0x00000001 -#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT__CI__VI 0x00000001 -#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT__CI__VI 0x00000005 -#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT__CI__VI 0x00000004 -#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT__CI__VI 0x00000018 -#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT__CI__VI 0x00000008 -#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT__CI__VI 0x00000010 -#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT__CI__VI 0x00000018 -#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT__CI__VI 0x00000008 -#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT__CI__VI 0x00000010 -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT__CI__VI \ - 0x00000000 -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT__CI__VI \ - 0x00000008 -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT__CI__VI \ - 0x00000010 -#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT__CI__VI \ - 0x00000018 -#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT__CI__VI 0x00000001 -#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT__CI__VI 0x00000000 -#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT__CI__VI 0x0000001e -#define BIF_RFE_SOFTRST_CNTL__REG_RST_warmRstRfeEn__SHIFT__CI 0x0000001d -#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT__CI__VI 0x0000001f -#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x00000000 -#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x00000000 -#define BIF_SLAVE_PERF_COUNTER0__BIF_SLAVE_PERF_COUNTER0__SHIFT__SI 0x00000000 -#define BIF_SLAVE_PERF_COUNTER1__BIF_SLAVE_PERF_COUNTER1__SHIFT__SI 0x00000000 -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT0_EVENT_SEL__SHIFT__SI 0x00000008 -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT0_RESET__SHIFT__SI 0x00000001 -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT1_EVENT_SEL__SHIFT__SI 0x0000000d -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT1_RESET__SHIFT__SI 0x00000002 -#define BIF_SLAVE_PERF_COUNTER_CNTL__BIF_SLV_COUNT_EN__SHIFT__SI 0x00000000 -#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT__CI__VI 0x00000000 -#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT__CI 0x00000002 -#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT__CI 0x0000001e -#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT__CI 0x0000001f -#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT__CI 0x0000001e -#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT__CI 0x0000001f -#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT__CI 0x0000001e -#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT__CI 0x0000001f -#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT__CI 0x0000001e -#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT__CI 0x0000001f -#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT__CI 0x00000002 -#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT__CI 0x0000001e -#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT__CI 0x0000001f -#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT__CI 0x00000002 -#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT__CI 0x0000001d -#define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT__CI 0x00000002 -#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT__CI 0x0000001e -#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT__CI 0x0000001f -#define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT__CI 0x00000002 -#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT__CI 0x00000001 -#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT__CI 0x00000000 -#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT__CI 0x00000002 -#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT__CI__VI 0x00000000 -#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT__CI__VI 0x0000001f -#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT__CI__VI 0x00000000 -#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x00000000 -#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x00000000 -#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x00000000 -#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x00000000 -#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x00000000 -#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x00000000 -#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x00000000 -#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x00000000 -#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x00000000 -#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x00000000 -#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x00000000 -#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x00000000 -#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x00000000 -#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x00000000 -#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x00000000 -#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x00000000 -#define BIST__BIST_CAP__SHIFT 0x00000007 -#define BIST__BIST_COMP__SHIFT 0x00000000 -#define BIST__BIST_STRT__SHIFT 0x00000006 -#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT__SI 0x00000003 -#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT__SI 0x00000002 -#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT__SI 0x00000010 -#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT__SI 0x00000000 -#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT__SI 0x00000001 -#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT__SI 0x00000000 -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT__SI 0x0000001f -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT__SI \ - 0x00000010 -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT__SI \ - 0x00000001 -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT__SI 0x00000000 -#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT__SI \ - 0x00000008 -#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT__SI 0x00000000 -#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT__SI 0x00000000 -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT__SI 0x00000011 -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT__SI 0x0000001f -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT__SI 0x00000018 -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT__SI 0x00000000 -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT__SI 0x00000008 -#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT__SI 0x00000010 -#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT__SI 0x00000000 -#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT__SI 0x00000000 -#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT__SI 0x00000000 -#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT__SI 0x0000001e -#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT__SI 0x0000001f -#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT__SI 0x00000000 -#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT__SI 0x0000001c -#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT__SI 0x00000000 -#define BL_PWM_CNTL__BL_PWM_EN__SHIFT__SI 0x0000001f -#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT__SI 0x0000001e -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT__SI 0x00000011 -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT__SI 0x0000001f -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT__SI 0x00000018 -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT__SI 0x00000000 -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT__SI 0x00000008 -#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT__SI 0x00000010 -#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT__SI 0x00000010 -#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT__SI 0x00000000 -#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x00000008 -#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x00000001 -#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x00000000 -#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x00000004 -#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000005 -#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x00000002 -#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x00000003 -#define BUS_CNTL__RD_STALL_IO_WR__SHIFT__CI__VI 0x00000012 -#define BUS_CNTL__SET_AZ_TC__SHIFT 0x0000000a -#define BUS_CNTL__SET_MC_TC__SHIFT 0x0000000d -#define BUS_CNTL__VGA_COHE_SPEC_TIMER_DIS__SHIFT__SI 0x00000009 -#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x00000007 -#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x00000006 -#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x00000011 -#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x00000010 -#define BWD_CHROMA_BOT_ADDR__BWD_UV_BOT_BASE__SHIFT__SI 0x00000000 -#define BWD_CHROMA_TOP_ADDR__BWD_UV_TOP_BASE__SHIFT__SI 0x00000000 -#define BWD_LUMA_BOT_ADDR__BWD_Y_BOT_BASE__SHIFT__SI 0x00000000 -#define BWD_LUMA_TOP_ADDR__BWD_Y_TOP_BASE__SHIFT__SI 0x00000000 -#define BX_RESET_EN__COR_RESET_EN__SHIFT__CI__VI 0x00000000 -#define BX_RESET_EN__REG_RESET_EN__SHIFT__CI__VI 0x00000001 -#define BX_RESET_EN__STY_RESET_EN__SHIFT__CI__VI 0x00000002 -#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x00000000 -#define CAC_ACC_ACP0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_BIF0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DC0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DC1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DC2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_DC3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_IDLE_PWR0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_LOWER_CMON__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_0__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_10__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_11__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_12__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_13__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_14__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_15__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_1__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_2__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_3__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_4__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_5__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_6__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_7__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_8__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_LOWER_REGION_9__ACCUMULATOR_31_0__SHIFT__SI 0x00000000 -#define CAC_ACC_MCD0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_MCD1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_MCD2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_MCD3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_ACP0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_ACP0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_BCI0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_BCI0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_BCI1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_BCI1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_BIF0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_BIF0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_CB0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_CB0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_CB1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_CB1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_CB2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_CB2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_CB3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_CB3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_CP0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_CP0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_CP1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_CP1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_CP2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_CP2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DB0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DB0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DB1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DB1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DB2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DB2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DB3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DB3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DC0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DC0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DC1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DC1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DC2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DC2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_DC3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_DC3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_GDS0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_GDS0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_GDS1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_GDS1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_GDS2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_GDS2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_GDS3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_GDS3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_IA0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_IA0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_IDLE_PWR0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_IDLE_PWR0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_LDS0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_LDS0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_LDS1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_LDS1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_LDS2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_LDS2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_LDS3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_LDS3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_MCD0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_MCD0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_MCD1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_MCD1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_MCD2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_MCD2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_MCD3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_MCD3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_PA0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_PA0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_PA1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_PA1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SC0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SC0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPI0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPI0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPI1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPI1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPI2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPI2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPI3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPI3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPI4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPI4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPI5__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPI5__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM5__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM5__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM6__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM6__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SPIM7__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SPIM7__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ5__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ5__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ6__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ6__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ7__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ7__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SQ8__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SQ8__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SX0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SX0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SX1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SX1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_SX2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_SX2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TA0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TA0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCC0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCC0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCC1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCC1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCC2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCC2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCC3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCC3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCC4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCC4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCP0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCP0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCP1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCP1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCP2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCP2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCP3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCP3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TCP4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TCP4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TD0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TD0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TD1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TD1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TD2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TD2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TD3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TD3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TD4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TD4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_TD5__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_TD5__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD5__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD5__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD6__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD6__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_UVD7__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_UVD7__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VCE0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VCE0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VCE1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VCE1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VCE2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VCE2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VCE3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VCE3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VCE4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VCE4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VGT0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VGT0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VGT1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VGT1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_VGT2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_VGT2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_WD0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_WD0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_XDMA0__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_XDMA0__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_XDMA1__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_XDMA1__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_XDMA2__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_XDMA2__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_XDMA3__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_XDMA3__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_XDMA4__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_XDMA4__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_NW_XDMA5__ACCUMULATOR_OUT__SHIFT__CI 0x00000000 -#define CAC_ACC_NW_XDMA5__OVRFLOW__SHIFT__CI 0x0000001f -#define CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM5__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM6__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SPIM7__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT__CI 0x00000000 -#define CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SX1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_SX2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UPPER_CMON__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_0__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_10__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_11__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_12__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_13__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_14__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_15__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_1__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_2__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_3__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_4__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_5__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_6__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_7__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_8__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UPPER_REGION_9__ACCUMULATOR_40_32__SHIFT__SI 0x00000000 -#define CAC_ACC_UVD0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UVD1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UVD2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UVD3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UVD4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UVD5__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UVD6__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_UVD7__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VCE0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VCE1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VCE2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VCE3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VCE4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_XDMA0__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_XDMA1__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_XDMA2__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_XDMA3__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_XDMA4__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_ACC_XDMA5__ACCUMULATOR_31_0__SHIFT__CI 0x00000000 -#define CAC_AGGR_LOWER__AGGREGATE_31_0__SHIFT__SI__CI 0x00000000 -#define CAC_AGGR_UPPER__AGGREGATE_62_32__SHIFT__SI__CI 0x00000000 -#define CAC_AGGR_UPPER__AGGR_OVERFLOW__SHIFT__SI__CI 0x0000001f -#define CAC_OVRRD_ACP__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_ACP__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_BCI__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_BCI__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_BIF__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_BIF__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_BIF__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_CB__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_CB__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_CB__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_CP__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_CP__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_CP__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_DB__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_DB__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_DB__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_DC__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_DC__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_DC__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_GDS__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_GDS__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_IA__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_IA__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_IA__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_IDLE_PWR__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_IDLE_PWR__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_LDS__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_LDS__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_LDS__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_MCD__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_MCD__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_MC__OVRRD_SELECT__SHIFT__SI 0x00000000 -#define CAC_OVRRD_MC__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_PA__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_PA__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_PA__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_SC__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_SC__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_SC__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_SPIM__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_SPIM__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_SPI__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_SPI__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_SPI__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_SQ__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_SQ__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_SQ__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_SX__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_SX__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_SX__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_TA__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_TA__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_TA__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_TCC__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_TCC__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_TCC__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_TCP__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_TCP__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_TCP__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_TD__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_TD__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_UVD__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_UVD__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_UVD__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_VCE__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_VCE__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_VCE__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_VGT__OVRRD_SELECT__SHIFT__SI__CI 0x00000000 -#define CAC_OVRRD_VGT__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_VGT__OVRRD_VALUE__SHIFT__SI 0x00000008 -#define CAC_OVRRD_WD__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_WD__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_OVRRD_XDMA__OVRRD_SELECT__SHIFT__CI 0x00000000 -#define CAC_OVRRD_XDMA__OVRRD_VALUE__SHIFT__CI 0x00000010 -#define CAC_PCIE_LNCNT_0_ACC_SUM__LNCNT_acc_sum__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_0_TIME_STAMP__LNCNT_RdVld__SHIFT__CI 0x0000001f -#define CAC_PCIE_LNCNT_0_TIME_STAMP__LNCNT_time_stamp__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_1_ACC_SUM__LNCNT_acc_sum__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_1_TIME_STAMP__LNCNT_RdVld__SHIFT__CI 0x0000001f -#define CAC_PCIE_LNCNT_1_TIME_STAMP__LNCNT_time_stamp__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_2_ACC_SUM__LNCNT_acc_sum__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_2_TIME_STAMP__LNCNT_RdVld__SHIFT__CI 0x0000001f -#define CAC_PCIE_LNCNT_2_TIME_STAMP__LNCNT_time_stamp__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_3_ACC_SUM__LNCNT_acc_sum__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_3_TIME_STAMP__LNCNT_RdVld__SHIFT__CI 0x0000001f -#define CAC_PCIE_LNCNT_3_TIME_STAMP__LNCNT_time_stamp__SHIFT__CI 0x00000000 -#define CAC_PCIE_LNCNT_CNTL__LNCNT_read_req__SHIFT__CI 0x0000001f -#define CAC_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI 0x00000000 -#define CAC_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI 0x00000000 -#define CAC_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT__SI__CI 0x00000000 -#define CAC_THRESHOLD_LOWER__OCP_THRESHOLD__SHIFT__SI__CI 0x00000000 -#define CAC_THRESHOLD_UPPER__OCP_THRESHOLD__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_ACP_0__WEIGHT_ACP_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_BIF_0__WEIGHT_BIF_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_CP_1__WEIGHT_PA_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_DC_0__WEIGHT_DC_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_DC_0__WEIGHT_DC_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_DC_1__WEIGHT_DC_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_DC_1__WEIGHT_DC_SIG3__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_IDLE_PWR_0__WEIGHT_IDLE_PWR_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_MCD_0__WEIGHT_MCD_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_MCD_0__WEIGHT_MCD_SIG1__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_MCD_1__WEIGHT_MCD_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_MCD_1__WEIGHT_MCD_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_MC_0__WEIGHT_MC_SIG0__SHIFT__SI 0x00000000 -#define CAC_WEIGHT_MC_0__WEIGHT_MC_SIG1__SHIFT__SI 0x00000010 -#define CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1__SHIFT__SI 0x00000010 -#define CAC_WEIGHT_SPIM_0__WEIGHT_SPIM_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_SPIM_0__WEIGHT_SPIM_SIG1__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_SPIM_1__WEIGHT_SPIM_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_SPIM_1__WEIGHT_SPIM_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_SPIM_2__WEIGHT_SPIM_SIG4__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_SPIM_2__WEIGHT_SPIM_SIG5__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_SPIM_3__WEIGHT_SPIM_SIG6__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_SPIM_3__WEIGHT_SPIM_SIG7__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_SX_0__WEIGHT_SX_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_SX_1__WEIGHT_SX_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_UVD_0__WEIGHT_UVD_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_UVD_0__WEIGHT_UVD_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_UVD_1__WEIGHT_UVD_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_UVD_1__WEIGHT_UVD_SIG3__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_UVD_2__WEIGHT_UVD_SIG4__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_UVD_2__WEIGHT_UVD_SIG5__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_UVD_3__WEIGHT_UVD_SIG6__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_UVD_3__WEIGHT_UVD_SIG7__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_VCE_0__WEIGHT_VCE_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_VCE_0__WEIGHT_VCE_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_VCE_1__WEIGHT_VCE_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_VCE_1__WEIGHT_VCE_SIG3__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_VCE_2__WEIGHT_VCE_SIG4__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT__SI__CI 0x00000010 -#define CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT__SI__CI 0x00000000 -#define CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_XDMA_0__WEIGHT_XDMA_SIG0__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_XDMA_0__WEIGHT_XDMA_SIG1__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_XDMA_1__WEIGHT_XDMA_SIG2__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_XDMA_1__WEIGHT_XDMA_SIG3__SHIFT__CI 0x00000010 -#define CAC_WEIGHT_XDMA_2__WEIGHT_XDMA_SIG4__SHIFT__CI 0x00000000 -#define CAC_WEIGHT_XDMA_2__WEIGHT_XDMA_SIG5__SHIFT__CI 0x00000010 -#define CAP0_ANC0_OFFSET_HIGH__CAP_ANC0_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_ANC0_OFFSET__CAP_ANC0_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_ANC1_OFFSET_HIGH__CAP_ANC1_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_ANC1_OFFSET__CAP_ANC1_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_ANC2_OFFSET_HIGH__CAP_ANC2_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_ANC2_OFFSET__CAP_ANC2_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_ANC3_OFFSET_HIGH__CAP_ANC3_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_ANC3_OFFSET__CAP_ANC3_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_ANC_BUF01_BLOCK_CNT__CAP0_ANC_BUF0_BLOCK_CNT__SHIFT__SI 0x00000000 -#define CAP0_ANC_BUF01_BLOCK_CNT__CAP0_ANC_BUF1_BLOCK_CNT__SHIFT__SI 0x00000010 -#define CAP0_ANC_BUF23_BLOCK_CNT__CAP0_ANC_BUF2_BLOCK_CNT__SHIFT__SI 0x00000000 -#define CAP0_ANC_BUF23_BLOCK_CNT__CAP0_ANC_BUF3_BLOCK_CNT__SHIFT__SI 0x00000010 -#define CAP0_ANC_H_WINDOW__CAP_ANC_WIDTH__SHIFT__SI 0x00000000 -#define CAP0_BUF0_EVEN_OFFSET_HIGH__CAP_BUF0_EVEN_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_BUF0_EVEN_OFFSET__CAP_BUF0_EVEN_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_BUF0_OFFSET_HIGH__CAP_BUF0_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_BUF0_OFFSET__CAP_BUF0_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_BUF1_EVEN_OFFSET_HIGH__CAP_BUF1_EVEN_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_BUF1_EVEN_OFFSET__CAP_BUF1_EVEN_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_BUF1_OFFSET_HIGH__CAP_BUF1_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_BUF1_OFFSET__CAP_BUF1_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_BUF_PITCH__CAP_BUF_PITCH__SHIFT__SI 0x00000000 -#define CAP0_BUF_STATUS__CAP_ANC_BUF_STATUS__SHIFT__SI 0x0000000f -#define CAP0_BUF_STATUS__CAP_ANC_PRE_BUF_CNT__SHIFT__SI 0x00000010 -#define CAP0_BUF_STATUS__CAP_CAP_BUF_STATUS__SHIFT__SI 0x0000001e -#define CAP0_BUF_STATUS__CAP_CUR_ANC_BUF__SHIFT__SI 0x0000000d -#define CAP0_BUF_STATUS__CAP_CUR_FIELD__SHIFT__SI 0x00000005 -#define CAP0_BUF_STATUS__CAP_CUR_VBI_BUF__SHIFT__SI 0x00000008 -#define CAP0_BUF_STATUS__CAP_CUR_VID_BUF__SHIFT__SI 0x00000002 -#define CAP0_BUF_STATUS__CAP_PRE_ANC_BUF__SHIFT__SI 0x0000000b -#define CAP0_BUF_STATUS__CAP_PRE_FIELD__SHIFT__SI 0x00000004 -#define CAP0_BUF_STATUS__CAP_PRE_VBI_BUF__SHIFT__SI 0x00000006 -#define CAP0_BUF_STATUS__CAP_PRE_VID_BUF__SHIFT__SI 0x00000000 -#define CAP0_BUF_STATUS__CAP_VBI_BUF_STATUS__SHIFT__SI 0x0000000a -#define CAP0_BUF_STATUS__CAP_VIP_INC__SHIFT__SI 0x0000001c -#define CAP0_BUF_STATUS__CAP_VIP_PRE_REPEAT_FIELD__SHIFT__SI 0x0000001d -#define CAP0_BUF_STATUS__CAP_VIP_STATUS_STROBE__SHIFT__SI 0x0000001f -#define CAP0_CONFIG__CAP_ANC_DECODE_EN__SHIFT__SI 0x0000000c -#define CAP0_CONFIG__CAP_BUF_MODE__SHIFT__SI 0x00000007 -#define CAP0_CONFIG__CAP_BUF_TYPE__SHIFT__SI 0x00000004 -#define CAP0_CONFIG__CAP_FAKE_FIELD_EN__SHIFT__SI 0x00000010 -#define CAP0_CONFIG__CAP_FIELD_START_LINE_DIFF__SHIFT__SI 0x00000011 -#define CAP0_CONFIG__CAP_HDWNS_DEC__SHIFT__SI 0x0000001a -#define CAP0_CONFIG__CAP_HORZ_DOWN__SHIFT__SI 0x00000013 -#define CAP0_CONFIG__CAP_IMAGE_FLIP_EN__SHIFT__SI 0x0000001b -#define CAP0_CONFIG__CAP_INPUT_MODE__SHIFT__SI 0x00000000 -#define CAP0_CONFIG__CAP_MIRROR_EN__SHIFT__SI 0x00000009 -#define CAP0_CONFIG__CAP_ONESHOT_IMAGE_FLIP_EN__SHIFT__SI 0x0000001c -#define CAP0_CONFIG__CAP_ONESHOT_MIRROR_EN__SHIFT__SI 0x0000000a -#define CAP0_CONFIG__CAP_ONESHOT_MODE__SHIFT__SI 0x00000006 -#define CAP0_CONFIG__CAP_SOFT_PULL_DOWN_EN__SHIFT__SI 0x0000000e -#define CAP0_CONFIG__CAP_START_BUF_R__SHIFT__SI 0x00000002 -#define CAP0_CONFIG__CAP_START_BUF_W__SHIFT__SI 0x00000003 -#define CAP0_CONFIG__CAP_START_FIELD__SHIFT__SI 0x00000001 -#define CAP0_CONFIG__CAP_STREAM_FORMAT__SHIFT__SI 0x00000017 -#define CAP0_CONFIG__CAP_VBI_EN__SHIFT__SI 0x0000000d -#define CAP0_CONFIG__CAP_VERT_DOWN__SHIFT__SI 0x00000015 -#define CAP0_CONFIG__CAP_VIDEO_IN_FORMAT__SHIFT__SI 0x0000001d -#define CAP0_CONFIG__CAP_VIDEO_SIGNED_UV__SHIFT__SI 0x0000000b -#define CAP0_CONFIG__CAP_VIP_EXTEND_FLAG_EN__SHIFT__SI 0x0000000f -#define CAP0_CONFIG__VBI_HORZ_DOWN__SHIFT__SI 0x0000001e -#define CAP0_DEBUG__CAP_H_STATUS__SHIFT__SI 0x00000000 -#define CAP0_DEBUG__CAP_V_STATUS__SHIFT__SI 0x00000010 -#define CAP0_DEBUG__CAP_V_SYNC__SHIFT__SI 0x0000001c -#define CAP0_H_WINDOW__CAP_H_START__SHIFT__SI 0x00000000 -#define CAP0_H_WINDOW__CAP_H_WIDTH__SHIFT__SI 0x00000010 -#define CAP0_ONESHOT_BUF_OFFSET_HIGH__CAP_ONESHOT_BUF_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_ONESHOT_BUF_OFFSET__CAP_ONESHOT_BUF_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_PORT_MODE_CNTL__CAP_DDR_MODE__SHIFT__SI 0x00000003 -#define CAP0_PORT_MODE_CNTL__CAP_DDR_SYNC__SHIFT__SI 0x00000004 -#define CAP0_PORT_MODE_CNTL__CAP_PORT_BYTE_USED__SHIFT__SI 0x00000002 -#define CAP0_PORT_MODE_CNTL__CAP_PORT_WIDTH__SHIFT__SI 0x00000001 -#define CAP0_PORT_MODE_CNTL__MOBILE_DIS__SHIFT__SI 0x00000005 -#define CAP0_TRIG_CNTL__CAP_EN__SHIFT__SI 0x00000004 -#define CAP0_TRIG_CNTL__CAP_TRIGGER_R__SHIFT__SI 0x00000000 -#define CAP0_TRIG_CNTL__CAP_TRIGGER_W__SHIFT__SI 0x00000000 -#define CAP0_TRIG_CNTL__CAP_VSYNC_CLR__SHIFT__SI 0x00000010 -#define CAP0_TRIG_CNTL__CAP_VSYNC_CNT__SHIFT__SI 0x00000008 -#define CAP0_VBI0_OFFSET_HIGH__CAP_VBI0_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_VBI0_OFFSET__CAP_VBI0_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_VBI1_OFFSET_HIGH__CAP_VBI1_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_VBI1_OFFSET__CAP_VBI1_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_VBI2_OFFSET_HIGH__CAP_VBI2_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_VBI2_OFFSET__CAP_VBI2_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_VBI3_OFFSET_HIGH__CAP_VBI3_OFFSET_HIGH__SHIFT__SI 0x00000000 -#define CAP0_VBI3_OFFSET__CAP_VBI3_OFFSET__SHIFT__SI 0x00000000 -#define CAP0_VBI_H_WINDOW__CAP_VBI_H_START__SHIFT__SI 0x00000000 -#define CAP0_VBI_H_WINDOW__CAP_VBI_H_WIDTH__SHIFT__SI 0x00000010 -#define CAP0_VBI_V_WINDOW__CAP_VBI_V_END__SHIFT__SI 0x00000010 -#define CAP0_VBI_V_WINDOW__CAP_VBI_V_START__SHIFT__SI 0x00000000 -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_SYNC_EN__SHIFT__SI 0x00000005 -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_EOF__SHIFT__SI 0x00000001 -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_EOL__SHIFT__SI 0x00000002 -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_FIELD__SHIFT__SI 0x00000003 -#define CAP0_VIDEO_SYNC_TEST__CAP_TEST_VID_SOF__SHIFT__SI 0x00000000 -#define CAP0_V_WINDOW__CAP_V_END__SHIFT__SI 0x00000010 -#define CAP0_V_WINDOW__CAP_V_START__SHIFT__SI 0x00000000 -#define CAP0_WR_BUFFER_STAT__WR_ACK_REQ_AK__SHIFT__SI 0x0000000b -#define CAP0_WR_BUFFER_STAT__WR_ACK_REQ__SHIFT__SI 0x0000000b -#define CAP0_WR_BUFFER_STAT__WR_BUFFER_FULLNESS__SHIFT__SI 0x00000000 -#define CAP0_WR_BUFFER_STAT__WR_BUFFER_FULL_AK__SHIFT__SI 0x0000000a -#define CAP0_WR_BUFFER_STAT__WR_BUFFER_FULL__SHIFT__SI 0x0000000a -#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x00000000 -#define CAPTURE_START_STATUS__DACA_CAPTURE_START_AK__SHIFT__SI 0x00000006 -#define CAPTURE_START_STATUS__DACA_CAPTURE_START_INT_EN__SHIFT__SI 0x0000000c -#define CAPTURE_START_STATUS__DACA_CAPTURE_START__SHIFT__SI 0x00000000 -#define CAPTURE_START_STATUS__DACB_CAPTURE_START_AK__SHIFT__SI 0x00000007 -#define CAPTURE_START_STATUS__DACB_CAPTURE_START_INT_EN__SHIFT__SI 0x0000000d -#define CAPTURE_START_STATUS__DACB_CAPTURE_START__SHIFT__SI 0x00000001 -#define CAPTURE_START_STATUS__DIGA_CAPTURE_START_AK__SHIFT__SI 0x00000008 -#define CAPTURE_START_STATUS__DIGA_CAPTURE_START_INT_EN__SHIFT__SI 0x0000000e -#define CAPTURE_START_STATUS__DIGA_CAPTURE_START__SHIFT__SI 0x00000002 -#define CAPTURE_START_STATUS__DIGB_CAPTURE_START_AK__SHIFT__SI 0x00000009 -#define CAPTURE_START_STATUS__DIGB_CAPTURE_START_INT_EN__SHIFT__SI 0x0000000f -#define CAPTURE_START_STATUS__DIGB_CAPTURE_START__SHIFT__SI 0x00000003 -#define CAPTURE_START_STATUS__DVOA_CAPTURE_START_AK__SHIFT__SI 0x0000000a -#define CAPTURE_START_STATUS__DVOA_CAPTURE_START_INT_EN__SHIFT__SI 0x00000010 -#define CAPTURE_START_STATUS__DVOA_CAPTURE_START__SHIFT__SI 0x00000004 -#define CAP_DEBUG__CAP_EOF_AK__SHIFT__SI 0x0000000e -#define CAP_DEBUG__CAP_EOF_EN__SHIFT__SI 0x00000002 -#define CAP_DEBUG__CAP_EOF_MH_ACK_REQ_AK__SHIFT__SI 0x0000000f -#define CAP_DEBUG__CAP_EOF_MH_ACK_REQ_EN__SHIFT__SI 0x00000003 -#define CAP_DEBUG__CAP_EOF_MH_ACK_REQ_STATUS__SHIFT__SI 0x0000000b -#define CAP_DEBUG__CAP_EOF_STATUS__SHIFT__SI 0x0000000a -#define CAP_DEBUG__CAP_EOL_AK__SHIFT__SI 0x0000000c -#define CAP_DEBUG__CAP_EOL_EN__SHIFT__SI 0x00000000 -#define CAP_DEBUG__CAP_EOL_STATUS__SHIFT__SI 0x00000008 -#define CAP_DEBUG__CAP_SOF_AK__SHIFT__SI 0x0000000d -#define CAP_DEBUG__CAP_SOF_EN__SHIFT__SI 0x00000001 -#define CAP_DEBUG__CAP_SOF_STATUS__SHIFT__SI 0x00000009 -#define CAP_INT_CNTL__CAP0_ANC0_INT_EN__SHIFT__SI 0x00000007 -#define CAP_INT_CNTL__CAP0_ANC1_INT_EN__SHIFT__SI 0x00000008 -#define CAP_INT_CNTL__CAP0_ANC2_INT_EN__SHIFT__SI 0x0000000b -#define CAP_INT_CNTL__CAP0_ANC3_INT_EN__SHIFT__SI 0x0000000c -#define CAP_INT_CNTL__CAP0_BUF0_EVEN_INT_EN__SHIFT__SI 0x00000001 -#define CAP_INT_CNTL__CAP0_BUF0_INT_EN__SHIFT__SI 0x00000000 -#define CAP_INT_CNTL__CAP0_BUF1_EVEN_INT_EN__SHIFT__SI 0x00000003 -#define CAP_INT_CNTL__CAP0_BUF1_INT_EN__SHIFT__SI 0x00000002 -#define CAP_INT_CNTL__CAP0_BUF_INT_MUX__SHIFT__SI 0x0000000d -#define CAP_INT_CNTL__CAP0_ONESHOT_INT_EN__SHIFT__SI 0x00000006 -#define CAP_INT_CNTL__CAP0_VBI0_INT_EN__SHIFT__SI 0x00000004 -#define CAP_INT_CNTL__CAP0_VBI1_INT_EN__SHIFT__SI 0x00000005 -#define CAP_INT_CNTL__CAP0_VBI2_INT_EN__SHIFT__SI 0x00000009 -#define CAP_INT_CNTL__CAP0_VBI3_INT_EN__SHIFT__SI 0x0000000a -#define CAP_INT_STATUS__CAP0_ANC0_INT_AK__SHIFT__SI 0x00000007 -#define CAP_INT_STATUS__CAP0_ANC0_INT__SHIFT__SI 0x00000007 -#define CAP_INT_STATUS__CAP0_ANC1_INT_AK__SHIFT__SI 0x00000008 -#define CAP_INT_STATUS__CAP0_ANC1_INT__SHIFT__SI 0x00000008 -#define CAP_INT_STATUS__CAP0_ANC2_INT_AK__SHIFT__SI 0x0000000b -#define CAP_INT_STATUS__CAP0_ANC2_INT__SHIFT__SI 0x0000000b -#define CAP_INT_STATUS__CAP0_ANC3_INT_AK__SHIFT__SI 0x0000000c -#define CAP_INT_STATUS__CAP0_ANC3_INT__SHIFT__SI 0x0000000c -#define CAP_INT_STATUS__CAP0_BUF0_EVEN_INT_AK__SHIFT__SI 0x00000001 -#define CAP_INT_STATUS__CAP0_BUF0_EVEN_INT__SHIFT__SI 0x00000001 -#define CAP_INT_STATUS__CAP0_BUF0_INT_AK__SHIFT__SI 0x00000000 -#define CAP_INT_STATUS__CAP0_BUF0_INT__SHIFT__SI 0x00000000 -#define CAP_INT_STATUS__CAP0_BUF1_EVEN_INT_AK__SHIFT__SI 0x00000003 -#define CAP_INT_STATUS__CAP0_BUF1_EVEN_INT__SHIFT__SI 0x00000003 -#define CAP_INT_STATUS__CAP0_BUF1_INT_AK__SHIFT__SI 0x00000002 -#define CAP_INT_STATUS__CAP0_BUF1_INT__SHIFT__SI 0x00000002 -#define CAP_INT_STATUS__CAP0_ONESHOT_INT_AK__SHIFT__SI 0x00000006 -#define CAP_INT_STATUS__CAP0_ONESHOT_INT__SHIFT__SI 0x00000006 -#define CAP_INT_STATUS__CAP0_VBI0_INT_AK__SHIFT__SI 0x00000004 -#define CAP_INT_STATUS__CAP0_VBI0_INT__SHIFT__SI 0x00000004 -#define CAP_INT_STATUS__CAP0_VBI1_INT_AK__SHIFT__SI 0x00000005 -#define CAP_INT_STATUS__CAP0_VBI1_INT__SHIFT__SI 0x00000005 -#define CAP_INT_STATUS__CAP0_VBI2_INT_AK__SHIFT__SI 0x00000009 -#define CAP_INT_STATUS__CAP0_VBI2_INT__SHIFT__SI 0x00000009 -#define CAP_INT_STATUS__CAP0_VBI3_INT_AK__SHIFT__SI 0x0000000a -#define CAP_INT_STATUS__CAP0_VBI3_INT__SHIFT__SI 0x0000000a -#define CAP_PTR__CAP_PTR__SHIFT 0x00000000 -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f -#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 -#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 -#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 -#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a -#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 -#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 -#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000 -#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 -#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT__CI__VI 0x0000001a -#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x00000007 -#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT__CI__VI 0x00000014 -#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x00000000 -#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003 -#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004 -#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010 -#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT__SI__CI 0x00000003 -#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT__SI__CI 0x00000005 -#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT__SI__CI 0x00000004 -#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT__SI__CI 0x00000009 -#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT__SI__CI 0x00000008 -#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT__SI__CI 0x00000007 -#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT__SI__CI 0x0000000a -#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT__SI__CI 0x00000006 -#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT__SI__CI 0x00000001 -#define CB_DEBUG_BUS_13__MU_STATE__SHIFT__SI__CI 0x0000000b -#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT__SI__CI 0x00000000 -#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT__SI__CI 0x00000002 -#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT__SI__CI 0x00000004 -#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT__SI__CI 0x00000003 -#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT__SI__CI 0x00000008 -#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT__SI__CI 0x00000001 -#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT__SI__CI 0x00000002 -#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT__SI__CI 0x00000005 -#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT__SI__CI 0x00000006 -#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT__SI__CI 0x00000007 -#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT__SI__CI 0x00000000 -#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT__SI__CI 0x00000004 -#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT__SI__CI 0x00000006 -#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT__SI__CI 0x00000008 -#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT__SI__CI 0x00000005 -#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT__SI__CI 0x00000003 -#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT__SI__CI 0x00000002 -#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT__SI__CI 0x00000000 -#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT__SI__CI 0x00000007 -#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT__SI__CI 0x00000014 -#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT__SI__CI 0x00000016 -#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT__SI__CI 0x00000015 -#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT__SI__CI 0x00000006 -#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT__SI__CI 0x00000010 -#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT__SI__CI 0x00000000 -#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT__SI__CI 0x0000000a -#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT__SI__CI 0x00000003 -#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT__SI__CI 0x00000002 -#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT__SI__CI 0x00000000 -#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT__SI__CI 0x00000005 -#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT__SI__CI 0x00000001 -#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT__SI__CI 0x00000004 -#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT__SI__CI 0x00000007 -#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT__SI__CI 0x00000006 -#define CB_DEBUG_BUS_18__NOT_USED__SHIFT__SI__CI 0x00000000 -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b -#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x0000001a -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000 -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011 -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005 -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000 -#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT__CI 0x00000018 -#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT__SI 0x00000017 -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008 -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT__CI__VI 0x00000000 -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010 -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT__CI__VI 0x00000015 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016 -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT__CI__VI 0x00000012 -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017 -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006 -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014 -#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013 -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define CB_PERFCOUNTER0_SELECT0__FORMAT_FILTER_ENABLE__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER0_SELECT0__FORMAT_FILTER_SEL__SHIFT__SI 0x0000000d -#define CB_PERFCOUNTER0_SELECT0__OP_FILTER_ENABLE__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER0_SELECT0__OP_FILTER_SEL__SHIFT__SI 0x00000009 -#define CB_PERFCOUNTER0_SELECT0__PERF_SEL__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER0_SELECT1__CLEAR_FILTER_ENABLE__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER0_SELECT1__CLEAR_FILTER_SEL__SHIFT__SI 0x00000001 -#define CB_PERFCOUNTER0_SELECT1__MRT_FILTER_ENABLE__SHIFT__SI 0x00000002 -#define CB_PERFCOUNTER0_SELECT1__MRT_FILTER_SEL__SHIFT__SI 0x00000003 -#define CB_PERFCOUNTER0_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT__SI 0x0000000b -#define CB_PERFCOUNTER0_SELECT1__NUM_FRAGMENTS_FILTER_SEL__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER0_SELECT1__NUM_SAMPLES_FILTER_ENABLE__SHIFT__SI 0x00000007 -#define CB_PERFCOUNTER0_SELECT1__NUM_SAMPLES_FILTER_SEL__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define CB_PERFCOUNTER1_SELECT0__FORMAT_FILTER_ENABLE__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER1_SELECT0__FORMAT_FILTER_SEL__SHIFT__SI 0x0000000d -#define CB_PERFCOUNTER1_SELECT0__OP_FILTER_ENABLE__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER1_SELECT0__OP_FILTER_SEL__SHIFT__SI 0x00000009 -#define CB_PERFCOUNTER1_SELECT0__PERF_SEL__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER1_SELECT1__CLEAR_FILTER_ENABLE__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER1_SELECT1__CLEAR_FILTER_SEL__SHIFT__SI 0x00000001 -#define CB_PERFCOUNTER1_SELECT1__MRT_FILTER_ENABLE__SHIFT__SI 0x00000002 -#define CB_PERFCOUNTER1_SELECT1__MRT_FILTER_SEL__SHIFT__SI 0x00000003 -#define CB_PERFCOUNTER1_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT__SI 0x0000000b -#define CB_PERFCOUNTER1_SELECT1__NUM_FRAGMENTS_FILTER_SEL__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER1_SELECT1__NUM_SAMPLES_FILTER_ENABLE__SHIFT__SI 0x00000007 -#define CB_PERFCOUNTER1_SELECT1__NUM_SAMPLES_FILTER_SEL__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define CB_PERFCOUNTER2_SELECT0__FORMAT_FILTER_ENABLE__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER2_SELECT0__FORMAT_FILTER_SEL__SHIFT__SI 0x0000000d -#define CB_PERFCOUNTER2_SELECT0__OP_FILTER_ENABLE__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER2_SELECT0__OP_FILTER_SEL__SHIFT__SI 0x00000009 -#define CB_PERFCOUNTER2_SELECT0__PERF_SEL__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER2_SELECT1__CLEAR_FILTER_ENABLE__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER2_SELECT1__CLEAR_FILTER_SEL__SHIFT__SI 0x00000001 -#define CB_PERFCOUNTER2_SELECT1__MRT_FILTER_ENABLE__SHIFT__SI 0x00000002 -#define CB_PERFCOUNTER2_SELECT1__MRT_FILTER_SEL__SHIFT__SI 0x00000003 -#define CB_PERFCOUNTER2_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT__SI 0x0000000b -#define CB_PERFCOUNTER2_SELECT1__NUM_FRAGMENTS_FILTER_SEL__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER2_SELECT1__NUM_SAMPLES_FILTER_ENABLE__SHIFT__SI 0x00000007 -#define CB_PERFCOUNTER2_SELECT1__NUM_SAMPLES_FILTER_SEL__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define CB_PERFCOUNTER3_SELECT0__FORMAT_FILTER_ENABLE__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER3_SELECT0__FORMAT_FILTER_SEL__SHIFT__SI 0x0000000d -#define CB_PERFCOUNTER3_SELECT0__OP_FILTER_ENABLE__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER3_SELECT0__OP_FILTER_SEL__SHIFT__SI 0x00000009 -#define CB_PERFCOUNTER3_SELECT0__PERF_SEL__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER3_SELECT1__CLEAR_FILTER_ENABLE__SHIFT__SI 0x00000000 -#define CB_PERFCOUNTER3_SELECT1__CLEAR_FILTER_SEL__SHIFT__SI 0x00000001 -#define CB_PERFCOUNTER3_SELECT1__MRT_FILTER_ENABLE__SHIFT__SI 0x00000002 -#define CB_PERFCOUNTER3_SELECT1__MRT_FILTER_SEL__SHIFT__SI 0x00000003 -#define CB_PERFCOUNTER3_SELECT1__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT__SI 0x0000000b -#define CB_PERFCOUNTER3_SELECT1__NUM_FRAGMENTS_FILTER_SEL__SHIFT__SI 0x0000000c -#define CB_PERFCOUNTER3_SELECT1__NUM_SAMPLES_FILTER_ENABLE__SHIFT__SI 0x00000007 -#define CB_PERFCOUNTER3_SELECT1__NUM_SAMPLES_FILTER_SEL__SHIFT__SI 0x00000008 -#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT__CI__VI 0x0000000a -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT__CI__VI 0x0000000b -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT__CI__VI 0x00000004 -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT__CI__VI 0x00000005 -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT__CI__VI 0x0000000c -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT__CI__VI 0x0000000d -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT__CI__VI 0x00000015 -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT__CI__VI 0x00000016 -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT__CI__VI 0x00000011 -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT__CI__VI 0x00000012 -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT__CI__VI 0x00000000 -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT__CI__VI 0x00000001 -#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000 -#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004 -#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008 -#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c -#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010 -#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014 -#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018 -#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c -#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000 -#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004 -#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008 -#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c -#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010 -#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014 -#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018 -#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c -#define CCIPHER_A_IK0__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_IK1__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_IK2__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_IK3__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S0__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S10__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S11__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S12__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S13__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S14__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S15__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S16__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S17__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S18__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S19__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S1__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S20__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S21__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S22__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S23__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S24__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S25__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S26__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S27__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S28__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S29__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S2__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S30__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S31__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S3__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S4__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S5__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S6__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S7__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S8__RESERVED__SHIFT 0x00000000 -#define CCIPHER_A_S9__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_IK0__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_IK1__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_IK2__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_IK3__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S0__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S10__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S11__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S12__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S13__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S14__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S15__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S16__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S17__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S18__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S19__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S1__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S20__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S21__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S22__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S23__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S24__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S25__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S26__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S27__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S28__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S29__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S2__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S30__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S31__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S3__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S4__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S5__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S6__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S7__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S8__RESERVED__SHIFT 0x00000000 -#define CCIPHER_B_S9__RESERVED__SHIFT 0x00000000 -#define CC_BIF_AZALIA_ID__AZALIA_DID__SHIFT__SI 0x00000003 -#define CC_BIF_AZALIA_ID__STRAP_AZALIA_DID__SHIFT__CI 0x00000001 -#define CC_BIF_AZALIA_ID__STRAP_BIF_AZ_64BAR_EN_A__SHIFT__SI 0x0000000c -#define CC_BIF_AZALIA_ID__STRAP_BIF_AZ_NONLEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x0000000d -#define CC_BIF_AZALIA_ID__STRAP_BIF_F0_64BAR_EN_A__SHIFT__SI 0x0000000a -#define CC_BIF_AZALIA_ID__STRAP_BIF_F0_NONLEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x0000000b -#define CC_BIF_AZALIA_ID__STRAP_BIF_IO_BAR_DIS__SHIFT__SI 0x00000009 -#define CC_BIF_AZALIA_ID__STRAP_BIF_LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT__SI 0x00000007 -#define CC_BIF_AZALIA_ID__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A__SHIFT__SI 0x00000010 -#define CC_BIF_AZALIA_ID__STRAP_BIF_RXP_NAK_FIX_IN_MODE1_EN__SHIFT__SI 0x0000000e -#define CC_BIF_AZALIA_ID__STRAP_BIF_RXP_REALIGN_ON_EACH_TSX_OR_SKP__SHIFT__SI 0x0000000f -#define CC_BIF_AZALIA_ID__STRAP_BIF_SHUTOFF_PORTS_FOR_SYM_ERR__SHIFT__SI 0x00000008 -#define CC_BIF_AZALIA_ID__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_BIF_AZALIA_ID__WR_DIS__SHIFT__CI 0x00000000 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_AUDIO_EN_PIN__SHIFT__CI 0x00000010 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_BIOS_ROM_EN__SHIFT__CI 0x00000003 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_CEC_EN_PIN__SHIFT__CI 0x00000011 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_CLK_PM_EN__SHIFT__CI__VI 0x00000002 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_GEN3_EN_A__SHIFT__CI 0x00000001 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_MEM_AP_SIZE_PIN__SHIFT__CI 0x00000005 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_SMBUS_DIS__SHIFT__CI 0x00000004 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN__SHIFT__CI 0x00000009 -#define CC_BIF_BU_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING__SHIFT__CI 0x0000000b -#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT__CI__VI 0x00000001 -#define CC_BIF_BX_FUSESTRAP0__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_AUDIO_EN_PIN__SHIFT__CI 0x00000010 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_BIOS_ROM_EN__SHIFT__CI 0x00000003 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_CEC_EN_PIN__SHIFT__CI 0x00000011 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_CLK_PM_EN__SHIFT__CI__VI 0x00000002 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_GEN3_EN_A__SHIFT__CI__VI 0x00000001 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_MEM_AP_SIZE_PIN__SHIFT__CI 0x00000005 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_SMBUS_DIS__SHIFT__CI 0x00000004 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN__SHIFT__CI 0x00000009 -#define CC_BIF_BX_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING__SHIFT__CI 0x0000000b -#define CC_BIF_BX_STRAP0__STRAP_BIF_BAR_COMPLIANCE_EN__SHIFT__CI__VI 0x0000000d -#define CC_BIF_BX_STRAP0__STRAP_BIF_DEBUG_ACCESS__SHIFT__CI__VI 0x0000000b -#define CC_BIF_BX_STRAP0__STRAP_BIF_DOORBELL_APER_SIZE__SHIFT__CI__VI 0x0000000e -#define CC_BIF_BX_STRAP0__STRAP_BIF_DOORBELL_BAR_DIS__SHIFT__CI__VI 0x0000000c -#define CC_BIF_BX_STRAP0__STRAP_BIF_FB_ALWAYS_ON__SHIFT__CI__VI 0x00000008 -#define CC_BIF_BX_STRAP0__STRAP_BIF_FB_CPL_TYPE_SEL__SHIFT__CI__VI 0x00000009 -#define CC_BIF_BX_STRAP0__STRAP_BIF_MEM_AP_SIZE__SHIFT__CI__VI 0x00000003 -#define CC_BIF_BX_STRAP0__STRAP_BIF_REG_AP_SIZE__SHIFT__CI__VI 0x00000001 -#define CC_BIF_BX_STRAP0__STRAP_BIF_ROM_AP_SIZE__SHIFT__CI__VI 0x00000006 -#define CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT__CI 0x00000010 -#define CC_BIF_BX_STRAP1__STRAP_BIF_AUDIO_EN__SHIFT__CI 0x0000000d -#define CC_BIF_BX_STRAP1__STRAP_BIF_AZ_64BAR_DIS_A__SHIFT__CI 0x00000005 -#define CC_BIF_BX_STRAP1__STRAP_BIF_AZ_LEGACY_DEVICE_TYPE_DIS__SHIFT__CI 0x0000000a -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_64BAR_DIS_A__SHIFT__CI 0x00000003 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_BAR_EN__SHIFT__CI 0x00000006 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_DIS__SHIFT__CI 0x00000008 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_DIS__SHIFT__CI 0x00000009 -#define CC_BIF_BX_STRAP1__STRAP_BIF_IO_BAR_DIS__SHIFT__CI 0x00000001 -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT__CI 0x0000000b -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT__CI 0x00000007 -#define CC_BIF_BX_STRAP1__STRAP_BIF_VGA_DIS__SHIFT__CI 0x00000002 -#define CC_BIF_BX_STRAP1__STRAP_CEC_64BAR_DIS__SHIFT__CI 0x00000004 -#define CC_BIF_BX_STRAP1__STRAP_CEC_PME_SUPPORT_COMPLIANCE_DIS__SHIFT__CI 0x0000000c -#define CC_BIF_BX_STRAP1__STRAP_RESERVED__SHIFT__CI 0x0000000e -#define CC_BIF_EFUSE0__STRAP_BIF_ASPM_L0SL1_INACTIVITY_EN__SHIFT__SI 0x00000010 -#define CC_BIF_EFUSE0__STRAP_BIF_IMP_MANUAL_OVERRIDE__SHIFT__SI 0x00000001 -#define CC_BIF_EFUSE0__STRAP_BIF_PAD_RX_MANUAL_IMPEDANCE__SHIFT__SI 0x00000002 -#define CC_BIF_EFUSE0__STRAP_BIF_PAD_TX_MANUAL_IMPEDANCE__SHIFT__SI 0x00000006 -#define CC_BIF_EFUSE0__STRAP_PHY_G2PLL_CREN_MODE__SHIFT__SI 0x0000000c -#define CC_BIF_EFUSE0__STRAP_PHY_G2PLL_IDLEDET_TH__SHIFT__SI 0x0000000d -#define CC_BIF_EFUSE0__STRAP_PHY_GEN1_RX_CRFRSIZE__SHIFT__SI 0x0000001e -#define CC_BIF_EFUSE0__STRAP_PHY_GEN1_RX_CRFR_ON__SHIFT__SI 0x0000001d -#define CC_BIF_EFUSE0__STRAP_PHY_GEN2_RX_CRFRSIZE__SHIFT__SI 0x0000001b -#define CC_BIF_EFUSE0__STRAP_PHY_GEN2_RX_CRFR_ON__SHIFT__SI 0x00000011 -#define CC_BIF_EFUSE0__STRAP_PHY_GEN2_RX_CRPHSIZE__SHIFT__SI 0x00000012 -#define CC_BIF_EFUSE0__STRAP_PHY_RX_CLKG_EN__SHIFT__SI 0x0000000a -#define CC_BIF_EFUSE0__STRAP_PHY_RX_INCAL_FORCE__SHIFT__SI 0x0000000b -#define CC_BIF_EFUSE0__STRAP_PHY_TX_CLKG_EN__SHIFT__SI 0x00000014 -#define CC_BIF_EFUSE0__STRAP_PHY_TX_DEEMPH_STR__SHIFT__SI 0x00000017 -#define CC_BIF_EFUSE0__STRAP_PHY_TX_DRV_STR__SHIFT__SI 0x00000015 -#define CC_BIF_EFUSE0__STRAP_PHY_TX_TAPINV__SHIFT__SI 0x0000000f -#define CC_BIF_EFUSE0__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_BIF_EFUSE1__STRAP_BIF_AER_EN__SHIFT__SI 0x00000007 -#define CC_BIF_EFUSE1__STRAP_BIF_ECN1P1_DIS__SHIFT__SI 0x00000019 -#define CC_BIF_EFUSE1__STRAP_BIF_ELAST_WATERMARK__SHIFT__SI 0x00000011 -#define CC_BIF_EFUSE1__STRAP_BIF_ERR_REPORTING_DIS__SHIFT__SI 0x0000000c -#define CC_BIF_EFUSE1__STRAP_BIF_EXIT_LATENCY_A__SHIFT__SI 0x00000008 -#define CC_BIF_EFUSE1__STRAP_BIF_MSTCPL_TIMEOUT_EN__SHIFT__SI 0x00000010 -#define CC_BIF_EFUSE1__STRAP_BIF_PHY_RCVRDET_3NF__SHIFT__SI 0x00000016 -#define CC_BIF_EFUSE1__STRAP_BIF_PWRSAVE_PEIDL_GOOD__SHIFT__SI 0x00000004 -#define CC_BIF_EFUSE1__STRAP_BIF_RX_IGNORE_ALL_ERR__SHIFT__SI 0x00000001 -#define CC_BIF_EFUSE1__STRAP_BIF_SKIP_INTERVAL_A__SHIFT__SI 0x0000000d -#define CC_BIF_EFUSE1__STRAP_BIF_STAGGER_CNTL__SHIFT__SI 0x00000014 -#define CC_BIF_EFUSE1__STRAP_BIF_SYMALIGN_DIS_ELIDLE__SHIFT__SI 0x00000013 -#define CC_BIF_EFUSE1__STRAP_BIF_SYMALIGN_MODE__SHIFT__SI 0x00000005 -#define CC_BIF_EFUSE1__STRAP_BIF_TX_PDNB_MODE__SHIFT__SI 0x00000006 -#define CC_BIF_EFUSE1__STRAP_INC_PLLCAL_PHASE__SHIFT__SI 0x0000001a -#define CC_BIF_EFUSE1__STRAP_PHY_GEN1_PG2RX_EQ__SHIFT__SI 0x00000017 -#define CC_BIF_EFUSE1__STRAP_PHY_GEN1_RX_CRPHSIZE__SHIFT__SI 0x00000002 -#define CC_BIF_EFUSE1__STRAP_PHY_GEN2_PG2RX_EQ__SHIFT__SI 0x0000001e -#define CC_BIF_EFUSE1__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_BIF_EFUSE2__STRAP_BIF_2VC_EN__SHIFT__SI 0x00000018 -#define CC_BIF_EFUSE2__STRAP_BIF_BACKGROUND_IMP_CAL__SHIFT__SI 0x00000014 -#define CC_BIF_EFUSE2__STRAP_BIF_BYPASS_LDSK_TO_LC__SHIFT__SI 0x0000001a -#define CC_BIF_EFUSE2__STRAP_BIF_DEEMPH_BIF_SEL_A__SHIFT__SI 0x0000001c -#define CC_BIF_EFUSE2__STRAP_BIF_FB_ALWAYS_ON__SHIFT__SI 0x00000015 -#define CC_BIF_EFUSE2__STRAP_BIF_FB_CPL_TYPE_SEL__SHIFT__SI 0x00000016 -#define CC_BIF_EFUSE2__STRAP_BIF_GEN2_COMPLIANCE__SHIFT__SI 0x0000000c -#define CC_BIF_EFUSE2__STRAP_BIF_LC_CHECK_DATA_RATE__SHIFT__SI 0x0000000e -#define CC_BIF_EFUSE2__STRAP_BIF_LC_ELEC_IDLE_MODE_A__SHIFT__SI 0x0000000f -#define CC_BIF_EFUSE2__STRAP_BIF_LC_SELECT_DEEMPHASIS__SHIFT__SI 0x0000001b -#define CC_BIF_EFUSE2__STRAP_BIF_LC_UPCONFIGURE_DIS__SHIFT__SI 0x00000011 -#define CC_BIF_EFUSE2__STRAP_BIF_LC_UPCONFIGURE_SUPPORT__SHIFT__SI 0x00000012 -#define CC_BIF_EFUSE2__STRAP_BIF_LDSK_X1_BYPASS__SHIFT__SI 0x00000013 -#define CC_BIF_EFUSE2__STRAP_BIF_RXP_LAT_REDUCTION_DIS__SHIFT__SI 0x0000000d -#define CC_BIF_EFUSE2__STRAP_BIF_TARGET_LINK_SPEED_A__SHIFT__SI 0x00000019 -#define CC_BIF_EFUSE2__STRAP_BIF_VENDOR_ID__SHIFT__SI 0x0000001d -#define CC_BIF_EFUSE2__STRAP_PHY_CLK_TX_DRV_STR__SHIFT__SI 0x0000001e -#define CC_BIF_EFUSE2__STRAP_PHY_PLL_IBIAS__SHIFT__SI 0x00000005 -#define CC_BIF_EFUSE2__STRAP_PHY_TX_DEEMPH_STR74__SHIFT__SI 0x00000001 -#define CC_BIF_EFUSE2__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_BIF_ID_STRAPS__DEVICE_ID__SHIFT__SI 0x00000004 -#define CC_BIF_ID_STRAPS__MAJOR_REV_ID__SHIFT__SI 0x00000014 -#define CC_BIF_ID_STRAPS__MINOR_REV_ID__SHIFT__SI 0x00000018 -#define CC_BIF_ID_STRAPS__STRAP_BIF_F0_DEVICE_ID__SHIFT__CI 0x00000004 -#define CC_BIF_ID_STRAPS__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT__CI 0x00000014 -#define CC_BIF_ID_STRAPS__STRAP_BIF_F0_MINOR_REV_ID__SHIFT__CI 0x00000018 -#define CC_BIF_ID_STRAPS__STRAP_RESERVED_1__SHIFT__CI 0x00000001 -#define CC_BIF_ID_STRAPS__STRAP_RESERVED__SHIFT__CI 0x0000001c -#define CC_BIF_ID_STRAPS__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_BIF_ID_STRAPS__WR_DIS__SHIFT__CI 0x00000000 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_ASPM_L0SL1_INACTIVITY_EN__SHIFT__SI 0x00000001 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_BYPASS_SCRAMBLER__SHIFT__SI 0x00000000 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_ELAST_WATERMARK__SHIFT__SI 0x00000002 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_IMP_MANUAL_OVERRIDE__SHIFT__SI 0x00000006 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_PAD_RX_MANUAL_IMPEDANCE__SHIFT__SI 0x00000007 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_PAD_TX_MANUAL_IMPEDANCE__SHIFT__SI 0x0000000b -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_STAGGER_CNTL__SHIFT__SI 0x00000011 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_SYMALIGN_DIS_ELIDLE__SHIFT__SI 0x0000000f -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_TEST_TOGGLE_MODE__SHIFT__SI 0x00000004 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_TEST_TOGGLE_PATTERN__SHIFT__SI 0x00000005 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_BIF_TX_PDNB_MODE__SHIFT__SI 0x00000019 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_INC_PLLCAL_PHASE__SHIFT__SI 0x00000013 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_GEN1_RX_CRFRSIZE__SHIFT__SI 0x0000001b -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_GEN1_RX_CRFR_ON__SHIFT__SI 0x00000010 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_GEN1_RX_CRPHSIZE__SHIFT__SI 0x0000001d -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_CLKG_EN__SHIFT__SI 0x0000001a -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_INCAL_FORCE__SHIFT__SI 0x0000001f -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_LBACK_EN__SHIFT__SI 0x00000017 -#define CC_BIF_ROMSTRAP0__ROMSTRAP_PHY_RX_TOGGLE_EN__SHIFT__SI 0x00000018 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_AER_EN__SHIFT__SI 0x0000001f -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_BACKGROUND_IMP_CAL__SHIFT__SI 0x0000000f -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_PHY_RCVRDET_3NF__SHIFT__SI 0x0000000e -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_PWRSAVE_PEIDL_GOOD__SHIFT__SI 0x00000010 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_QUICKSIM_START__SHIFT__SI 0x0000000b -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_SKIP_INTERVAL_A__SHIFT__SI 0x00000015 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_BIF_SYMALIGN_MODE__SHIFT__SI 0x00000011 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_G2PLL_CREN_MODE__SHIFT__SI 0x00000000 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_G2PLL_IDLEDET_TH__SHIFT__SI 0x00000001 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_GEN1_PG2RX_EQ__SHIFT__SI 0x0000001d -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_PLL_IBIAS__SHIFT__SI 0x00000003 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_RX_TEST_EN_INVERT__SHIFT__SI 0x0000000a -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_TX_CLKG_EN__SHIFT__SI 0x00000018 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_TX_DEEMPH_STR__SHIFT__SI 0x00000019 -#define CC_BIF_ROMSTRAP1__ROMSTRAP_PHY_TX_DRV_STR__SHIFT__SI 0x0000000c -#define CC_BIF_ROMSTRAP1__ROMSTRAP_YTSX_COUNT__SHIFT__SI 0x00000012 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_AUDIO_EN__SHIFT__SI 0x0000001a -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_BYPASS_RCVR_DET_A__SHIFT__SI 0x0000001f -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_CFG_REG_RESET_ONLY__SHIFT__SI 0x0000001d -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_COMPLIANCE_DIS_A__SHIFT__SI 0x00000018 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_DUALFUNC_DISPLAY_EN__SHIFT__SI 0x00000019 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_ECN1P1_EN__SHIFT__SI 0x00000006 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_EXIT_LATENCY_A__SHIFT__SI 0x00000000 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_F0_64BAR_EN_A__SHIFT__SI 0x00000005 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_F0_NONLEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x00000004 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_F0_VC_EN__SHIFT__SI 0x0000001c -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_LINK_DOWN_RESET_EN__SHIFT__SI 0x0000001e -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_MEM_AP_SIZE__SHIFT__SI 0x00000007 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_MSI_DIS__SHIFT__SI 0x0000001b -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_REG_AP_SIZE1__SHIFT__SI 0x0000000a -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_ROM_AP_SIZE__SHIFT__SI 0x0000000b -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_BE_ERR__SHIFT__SI 0x0000000e -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT__SI 0x0000000f -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_CFG_UR__SHIFT__SI 0x00000010 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT__SI 0x00000011 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_EP_ERR__SHIFT__SI 0x00000012 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_IO_ERR__SHIFT__SI 0x00000013 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_IO_UR__SHIFT__SI 0x00000014 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT__SI 0x0000000d -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT__SI 0x00000015 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT__SI 0x00000016 -#define CC_BIF_ROMSTRAP2__ROMSTRAP_BIF_RX_IGNORE_TC_ERR__SHIFT__SI 0x00000017 -#define CC_BIF_ROMSTRAP3__ROMSTRAP_BIF_SUBSYS_ID__SHIFT__SI 0x00000010 -#define CC_BIF_ROMSTRAP3__ROMSTRAP_BIF_SUBSYS_VEN_ID__SHIFT__SI 0x00000000 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT__SI 0x0000001f -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_AZ_64BAR_EN_A__SHIFT__SI 0x00000017 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_AZ_NONLEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x00000016 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_FORCE_CDR_MODE__SHIFT__SI 0x0000000d -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_FORCE_GEN2_MODE__SHIFT__SI 0x0000000c -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_GEN2_COMPLIANCE__SHIFT__SI 0x0000001c -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_CDR_SET_TYPE__SHIFT__SI 0x0000000e -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_CDR_TEST_OFF__SHIFT__SI 0x00000010 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_CHECK_DATA_RATE__SHIFT__SI 0x0000001e -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT__SI 0x00000014 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A__SHIFT__SI 0x0000001a -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_RXP_LAT_REDUCTION_DIS__SHIFT__SI 0x0000001d -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_RXP_NAK_FIX_IN_MODE1_EN__SHIFT__SI 0x00000018 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_RXP_REALIGN_ON_EACH_TSX_OR_SKP__SHIFT__SI 0x00000019 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_SHUTOFF_PORTS_FOR_SYM_ERR__SHIFT__SI 0x00000015 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_BIF_VGA_DIS__SHIFT__SI 0x0000001b -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_CLK_TX_DRV_STR__SHIFT__SI 0x00000012 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_PG2RX_EQ__SHIFT__SI 0x0000000a -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_RX_CRFRSIZE__SHIFT__SI 0x00000006 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_RX_CRFR_ON__SHIFT__SI 0x00000005 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_GEN2_RX_CRPHSIZE__SHIFT__SI 0x00000008 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_TX_DEEMPH_STR74__SHIFT__SI 0x00000000 -#define CC_BIF_ROMSTRAP4__ROMSTRAP_PHY_TX_TAPINV__SHIFT__SI 0x00000004 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_2VC_EN__SHIFT__SI 0x00000015 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_BYPASS_LDSK_TO_LC__SHIFT__SI 0x00000017 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_DEBUG_ACCESS__SHIFT__SI 0x00000016 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_DEEMPH_BIF_SEL_A__SHIFT__SI 0x00000019 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_FB_ALWAYS_ON__SHIFT__SI 0x00000012 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_FB_CPL_TYPE_SEL__SHIFT__SI 0x00000013 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_FORCE_COMPLIANCE_A__SHIFT__SI 0x0000001e -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_IO_BAR_DIS__SHIFT__SI 0x0000001d -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LANE_NEGOTIATION__SHIFT__SI 0x00000004 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_ELEC_IDLE_MODE_A__SHIFT__SI 0x00000000 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_INIT_SPEED_NEG_IN_L0s_EN_A__SHIFT__SI 0x00000002 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_INIT_SPEED_NEG_IN_L1_EN_A__SHIFT__SI 0x00000003 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_SELECT_DEEMPHASIS__SHIFT__SI 0x00000018 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_TEST_TIMER_SEL_A__SHIFT__SI 0x00000007 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_UPCONFIGURE_DIS__SHIFT__SI 0x00000009 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LC_UPCONFIGURE_SUPPORT__SHIFT__SI 0x0000000a -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_LDSK_X1_BYPASS__SHIFT__SI 0x0000000b -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_MSTCPL_TIMEOUT_EN__SHIFT__SI 0x0000000c -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_PARALLEL_LBACK_EN__SHIFT__SI 0x0000001f -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_P_SYMSYNC_BYPASS_MODE__SHIFT__SI 0x0000000e -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_P_SYMSYNC_ENABLE_IN_GEN1__SHIFT__SI 0x0000000f -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_RST_PDNB_REG_ON_CALRST__SHIFT__SI 0x0000001c -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_TARGET_LINK_SPEED_A__SHIFT__SI 0x0000000d -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_TX_TEST_ALL__SHIFT__SI 0x00000010 -#define CC_BIF_ROMSTRAP5__ROMSTRAP_BIF_VENDOR_ID__SHIFT__SI 0x0000001a -#define CC_BIF_ROMSTRAP5__ROMSTRAP_PHY_CALIB_RST__SHIFT__SI 0x0000001b -#define CC_BIF_SECURE_CNTL__SECURE_ID__SHIFT__CI__VI 0x00000010 -#define CC_BIF_SECURE_CNTL__SECURE_LVL__SHIFT__CI__VI 0x00000008 -#define CC_BIF_SECURE_CNTL__WR_DIS__SHIFT__CI__VI 0x00000000 -#define CC_BIF_STRAP0__STRAP_BIF_2VC_EN__SHIFT__CI 0x0000000c -#define CC_BIF_STRAP0__STRAP_BIF_ASPM_L0SL1_INACTIVITY_EN__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP0__STRAP_BIF_ECN1P1_DIS__SHIFT__CI 0x0000001e -#define CC_BIF_STRAP0__STRAP_BIF_F0_CPL_ABORT_ERR_EN__SHIFT__CI 0x0000001f -#define CC_BIF_STRAP0__STRAP_BIF_FORCE_COMPLIANCE_A__SHIFT__CI 0x0000001d -#define CC_BIF_STRAP0__STRAP_BIF_GEN2_COMPLIANCE_DIS__SHIFT__CI 0x0000000e -#define CC_BIF_STRAP0__STRAP_BIF_LC_BYPASS_EQ_A__SHIFT__CI 0x00000006 -#define CC_BIF_STRAP0__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_A__SHIFT__CI 0x00000005 -#define CC_BIF_STRAP0__STRAP_BIF_LC_CHECK_DATA_RATE_DIS__SHIFT__CI 0x0000001c -#define CC_BIF_STRAP0__STRAP_BIF_LC_ELEC_IDLE_MODE_A__SHIFT__CI 0x00000003 -#define CC_BIF_STRAP0__STRAP_BIF_LC_EQ_SEARCH_MODE_A__SHIFT__CI 0x00000007 -#define CC_BIF_STRAP0__STRAP_BIF_LC_SELECT_DEEMPHASIS__SHIFT__CI 0x00000019 -#define CC_BIF_STRAP0__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A__SHIFT__CI 0x00000002 -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_NONDIS__SHIFT__CI 0x0000001b -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_SUPPORT__SHIFT__CI 0x0000001a -#define CC_BIF_STRAP0__STRAP_BIF_MSTCPL_TIMEOUT_EN__SHIFT__CI 0x0000000d -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT__CI 0x00000011 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT__CI 0x00000012 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CFG_UR__SHIFT__CI 0x00000017 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT__CI 0x00000013 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT__CI 0x00000010 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_IO_UR__SHIFT__CI 0x00000018 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT__CI 0x00000014 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT__CI 0x00000015 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT__CI 0x00000016 -#define CC_BIF_STRAP0__STRAP_BIF_RX_PLL_CALIB_BYPASS__SHIFT__CI 0x0000000f -#define CC_BIF_STRAP0__STRAP_BIF_SKIP_INTERVAL_A__SHIFT__CI 0x00000009 -#define CC_BIF_STRAP1__STRAP_BIF_ECRC_CHECK_EN__SHIFT__CI 0x00000019 -#define CC_BIF_STRAP1__STRAP_BIF_ECRC_GEN_EN__SHIFT__CI__VI 0x00000015 -#define CC_BIF_STRAP1__STRAP_BIF_F0_MAX_PAYLOAD_SUPPORT_DIS__SHIFT__CI 0x0000001b -#define CC_BIF_STRAP1__STRAP_BIF_F0_PWR_EN__SHIFT__CI__VI 0x00000012 -#define CC_BIF_STRAP1__STRAP_BIF_F0_SUBSYS_ID__SHIFT__CI__VI 0x00000001 -#define CC_BIF_STRAP1__STRAP_BIF_F1_CPL_ABORT_ERR_EN__SHIFT__CI__VI 0x00000011 -#define CC_BIF_STRAP1__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT__CI__VI 0x00000013 -#define CC_BIF_STRAP1__STRAP_BIF_LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT__CI__VI 0x00000016 -#define CC_BIF_STRAP1__STRAP_BIF_MSI_DIS__SHIFT__CI 0x0000001a -#define CC_BIF_STRAP1__STRAP_BIF_SYMALIGN_HW_DEBUG__SHIFT__CI__VI 0x00000014 -#define CC_BIF_STRAP1__STRAP_BIF_SYMALIGN_MODE__SHIFT__CI 0x00000018 -#define CC_BIF_STRAP1__STRAP_BIF_VENDOR_ID__SHIFT__CI 0x00000017 -#define CC_BIF_STRAP1__STRAP_B_PCB_DIS0__SHIFT__CI 0x0000001c -#define CC_BIF_STRAP1__STRAP_B_PCB_DIS1__SHIFT__CI 0x0000001d -#define CC_BIF_STRAP1__STRAP_B_PCB_DRV_STR__SHIFT__CI 0x0000001e -#define CC_BIF_STRAP2__STRAP_BIF_AER_EN__SHIFT__CI 0x0000000c -#define CC_BIF_STRAP2__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT__CI 0x0000001a -#define CC_BIF_STRAP2__STRAP_BIF_BYPASS_RCVR_DET_A__SHIFT__CI 0x0000000b -#define CC_BIF_STRAP2__STRAP_BIF_BYPASS_SCRAMBLER__SHIFT__CI 0x00000010 -#define CC_BIF_STRAP2__STRAP_BIF_CFG_REG_RESET_ONLY__SHIFT__CI 0x0000001c -#define CC_BIF_STRAP2__STRAP_BIF_COMPLIANCE_DIS_A__SHIFT__CI 0x0000000a -#define CC_BIF_STRAP2__STRAP_BIF_ERR_REPORTING_DIS__SHIFT__CI 0x0000001b -#define CC_BIF_STRAP2__STRAP_BIF_EXTENDED_TAG_ECN_EN__SHIFT__CI 0x0000001f -#define CC_BIF_STRAP2__STRAP_BIF_F0_POISONED_ADVISORY_NONFATAL_DIS__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP2__STRAP_BIF_F0_VC_EN__SHIFT__CI 0x0000000d -#define CC_BIF_STRAP2__STRAP_BIF_F1_POISONED_ADVISORY_NONFATAL_DIS__SHIFT__CI 0x00000002 -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_CDR_MODE__SHIFT__CI 0x00000014 -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_GEN2_MODE__SHIFT__CI 0x00000013 -#define CC_BIF_STRAP2__STRAP_BIF_LANE_NEGOTIATION_A__SHIFT__CI 0x00000007 -#define CC_BIF_STRAP2__STRAP_BIF_LC_CDR_SET_TYPE__SHIFT__CI 0x00000011 -#define CC_BIF_STRAP2__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L0s_EN_A__SHIFT__CI 0x00000004 -#define CC_BIF_STRAP2__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L1_EN_A__SHIFT__CI 0x00000003 -#define CC_BIF_STRAP2__STRAP_BIF_LC_TEST_TIMER_SEL_A__SHIFT__CI 0x00000005 -#define CC_BIF_STRAP2__STRAP_BIF_LINK_DOWN_RESET_EN__SHIFT__CI 0x0000001d -#define CC_BIF_STRAP2__STRAP_BIF_PARALLEL_LBACK_EN__SHIFT__CI 0x00000018 -#define CC_BIF_STRAP2__STRAP_BIF_QUICKSIM_START__SHIFT__CI 0x0000001e -#define CC_BIF_STRAP2__STRAP_BIF_RST_PDNB_REG_ON_CALRST__SHIFT__CI 0x00000017 -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_MODE__SHIFT__CI 0x0000000e -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_PATTERN__SHIFT__CI 0x0000000f -#define CC_BIF_STRAP2__STRAP_BIF_TX_TEST_ALL__SHIFT__CI 0x00000015 -#define CC_BIF_STRAP2__STRAP_PHY_CALIB_RST__SHIFT__CI 0x00000019 -#define CC_BIF_STRAP3__STRAP_BIF_FLR_EN__SHIFT__CI 0x0000001d -#define CC_BIF_STRAP3__STRAP_BIF_FORCE_GEN3_MODE__SHIFT__CI 0x00000017 -#define CC_BIF_STRAP3__STRAP_BIF_GEN3_COMPLIANCE_DIS__SHIFT__CI 0x0000001e -#define CC_BIF_STRAP3__STRAP_BIF_INTERNAL_ERR_EN__SHIFT__CI 0x0000001c -#define CC_BIF_STRAP3__STRAP_BIF_LC_CDR_TEST_OFF__SHIFT__CI 0x00000014 -#define CC_BIF_STRAP3__STRAP_BIF_NO_SOFT_RESET__SHIFT__CI 0x00000016 -#define CC_BIF_STRAP3__STRAP_BIF_SUBSYS_VEN_ID__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP3__STRAP_PIF_OPO_TRIGGER_MUX_SEL__SHIFT__CI 0x0000001f -#define CC_BIF_STRAP3__STRAP_PIF_RXDETECT_OVERRIDE_EN__SHIFT__CI 0x00000018 -#define CC_BIF_STRAP3__STRAP_PIF_SERIAL_CFG_ENABLE__SHIFT__CI 0x00000019 -#define CC_BIF_STRAP3__STRAP_PLL_CMP_FREQ_MODE__SHIFT__CI 0x0000001a -#define CC_BIF_STRAP3__STRAP_YTSX_COUNT__SHIFT__CI 0x00000011 -#define CC_BIF_STRAP4__STRAP_BIF_GEN2_EN_A__SHIFT__CI 0x0000001c -#define CC_BIF_STRAP4__STRAP_BIF_LC_AUTO_DISABLE_GEN2_EN_A__SHIFT__CI 0x00000019 -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_0__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_1__SHIFT__CI 0x00000009 -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_2__SHIFT__CI 0x00000011 -#define CC_BIF_STRAP4__STRAP_BIF_TARGET_LINK_SPEED_A__SHIFT__CI 0x0000001a -#define CC_BIF_STRAP5__STRAP_BIF_F0_PAGE_REQ_EN__SHIFT__CI__VI 0x0000001a -#define CC_BIF_STRAP5__STRAP_BIF_F0_PASID_EN__SHIFT__CI__VI 0x0000001b -#define CC_BIF_STRAP5__STRAP_BIF_GASKET_SLV_COMB_DIS__SHIFT__CI 0x0000001f -#define CC_BIF_STRAP5__STRAP_BIF_PASID_EXE_PERMISSION_SUPPORTED__SHIFT__CI__VI 0x0000001c -#define CC_BIF_STRAP5__STRAP_BIF_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT__CI__VI 0x0000001e -#define CC_BIF_STRAP5__STRAP_BIF_PASID_PRIV_MODE_SUPPORTED__SHIFT__CI__VI 0x0000001d -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_3__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_4__SHIFT__CI 0x00000009 -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_5__SHIFT__CI 0x00000011 -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_SYSTEM_ALLOCATED__SHIFT__CI__VI 0x00000019 -#define CC_BIF_STRAP6__STRAP_BIF_F0_DPA_EN__SHIFT__CI 0x00000008 -#define CC_BIF_STRAP6__STRAP_BIF_F2_CPL_ABORT_ERR_EN__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP6__STRAP_BIF_F2_POISONED_ADVISORY_NONFATAL_DIS__SHIFT__CI 0x00000002 -#define CC_BIF_STRAP6__STRAP_BIF_L0S_ACCEPTABLE_LATENCY__SHIFT__CI 0x0000001d -#define CC_BIF_STRAP6__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT__CI 0x00000017 -#define CC_BIF_STRAP6__STRAP_BIF_L1_EXIT_LATENCY__SHIFT__CI 0x0000001a -#define CC_BIF_STRAP6__STRAP_BIF_LC_EQ_FS_A__SHIFT__CI 0x00000010 -#define CC_BIF_STRAP6__STRAP_BIF_LC_EQ_LF_A__SHIFT__CI 0x0000000a -#define CC_BIF_STRAP6__STRAP_BIF_LC_X12_NEGOTIATION_DIS_A__SHIFT__CI 0x00000016 -#define CC_BIF_STRAP6__STRAP_CHIP_BIF_MODE__SHIFT__CI 0x00000009 -#define CC_BIF_STRAP6__STRAP_PIF_PLL_RAMP_UP_TIME__SHIFT__CI 0x00000005 -#define CC_BIF_STRAP6__STRAP_PIF_RXDETECT_SAMPL_TIME__SHIFT__CI 0x00000003 -#define CC_BIF_STRAP7__STRAP_BIF_E2E_PREFIX_EN_A__SHIFT__CI 0x0000000e -#define CC_BIF_STRAP7__STRAP_BIF_EXTENDED_FMT_SUPPORTED_A__SHIFT__CI 0x0000000f -#define CC_BIF_STRAP7__STRAP_BIF_F0_ATS_EN__SHIFT__CI 0x00000016 -#define CC_BIF_STRAP7__STRAP_BIF_INITIAL_N_FTS__SHIFT__CI 0x00000006 -#define CC_BIF_STRAP7__STRAP_BIF_L1_ACCEPTABLE_LATENCY__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP7__STRAP_BIF_MAX_PASID_WIDTH__SHIFT__CI 0x00000011 -#define CC_BIF_STRAP7__STRAP_BIF_PASID_PREFIX_SUPPORTED__SHIFT__CI 0x00000010 -#define CC_BIF_STRAP7__STRAP_BIF_PM_SUPPORT__SHIFT__CI 0x00000004 -#define CC_BIF_STRAP8__STRAP_RESERVE__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP9__STRAP_BIF_AUDIO_EN__SHIFT__CI 0x0000000d -#define CC_BIF_STRAP9__STRAP_BIF_AZ_64BAR_DIS_A__SHIFT__CI 0x00000005 -#define CC_BIF_STRAP9__STRAP_BIF_AZ_LEGACY_DEVICE_TYPE_DIS__SHIFT__CI 0x0000000a -#define CC_BIF_STRAP9__STRAP_BIF_F0_64BAR_DIS_A__SHIFT__CI 0x00000003 -#define CC_BIF_STRAP9__STRAP_BIF_F0_BAR_EN__SHIFT__CI 0x00000006 -#define CC_BIF_STRAP9__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_DIS__SHIFT__CI 0x00000008 -#define CC_BIF_STRAP9__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_DIS__SHIFT__CI 0x00000009 -#define CC_BIF_STRAP9__STRAP_BIF_IO_BAR_DIS__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP9__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT__CI 0x0000000b -#define CC_BIF_STRAP9__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT__CI 0x00000007 -#define CC_BIF_STRAP9__STRAP_BIF_VGA_DIS__SHIFT__CI 0x00000002 -#define CC_BIF_STRAP9__STRAP_CEC_64BAR_DIS__SHIFT__CI 0x00000004 -#define CC_BIF_STRAP9__STRAP_CEC_PME_SUPPORT_COMPLIANCE_DIS__SHIFT__CI 0x0000000c -#define CC_BIF_STRAP9__STRAP_RESERVED__SHIFT__CI 0x0000000e -#define CC_BIF_STRAP_FUSE0__STRAP_BIF_EP_MODE__SHIFT__CI 0x00000012 -#define CC_BIF_STRAP_FUSE0__STRAP_BIF_KILL_GEN3__SHIFT__CI 0x00000011 -#define CC_BIF_STRAP_FUSE0__STRAP_CEC_ID__SHIFT__CI 0x00000001 -#define CC_BIF_STRAP_FUSE0__STRAP_RESERVED__SHIFT__CI 0x00000013 -#define CC_BIF_STRAP_FUSE0__WR_DIS__SHIFT__CI 0x00000000 -#define CC_CAC_CMON__CMON_ADC_GAIN_ADJ__SHIFT__CI 0x00000007 -#define CC_CAC_CMON__CMON_BGADJ__SHIFT__CI 0x00000001 -#define CC_CAC_CMON__IDSC_FADC_ADJ__SHIFT__CI 0x00000010 -#define CC_CAC_CMON__IDSC_FX_ADJ__SHIFT__CI 0x0000000c -#define CC_CAC_CMON__WRITE_DIS__SHIFT__CI 0x00000000 -#define CC_DC_MISC_STRAPS__DACA_BGADJ__SHIFT__SI 0x00000014 -#define CC_DC_MISC_STRAPS__DACB_BGADJ__SHIFT__SI 0x0000001a -#define CC_DC_MISC_STRAPS__HDCP_DEBUG_ENABLE__SHIFT__SI 0x00000007 -#define CC_DC_MISC_STRAPS__HDCP_DIS__SHIFT__SI 0x00000003 -#define CC_DC_MISC_STRAPS__HDCP_KEYS_INVALID__SHIFT__SI 0x00000005 -#define CC_DC_MISC_STRAPS__HDMI_DISABLE__SHIFT__SI 0x00000006 -#define CC_DC_MISC_STRAPS__MACROVISION_DIS__SHIFT__SI 0x00000004 -#define CC_DC_MISC_STRAPS__MOBILE_DIS__SHIFT__SI 0x00000001 -#define CC_DC_MISC_STRAPS__SPARE1__SHIFT__SI 0x00000008 -#define CC_DC_MISC_STRAPS__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c -#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004 -#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014 -#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018 -#define CC_DRM_ID_STRAPS__WRITE_DIS__SHIFT 0x00000000 -#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT__CI__VI 0x00000001 -#define CC_GC_EDC_CONFIG__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT__CI__VI 0x00000010 -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT__CI__VI 0x00000018 -#define CC_GC_PRIM_CONFIG__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_GC_SHADER_ARRAY_CONFIG__DIS_DPFP__SHIFT__SI 0x00000001 -#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT__CI 0x00000001 -#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT__CI 0x00000004 -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 -#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT__CI 0x00000003 -#define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT__CI__VI 0x00000001 -#define CC_GIO_IOCCFG_FUSES__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT__CI__VI 0x00000001 -#define CC_GIO_IOC_FUSES__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_GNB_SECURE_SPARE__DCE_SCAN_DISABLE__SHIFT__CI__VI 0x00000001 -#define CC_GNB_SECURE_SPARE__GNB_SECURE_SPARE__SHIFT__CI__VI 0x00000002 -#define CC_GNB_SECURE_SPARE__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x00000001 -#define CC_MC_MAX_CHANNEL__WRITE_DISABLE__SHIFT 0x00000000 -#define CC_PWR_DYN_GF_RM__GF_PDP_RME__SHIFT__CI__VI 0x0000001b -#define CC_PWR_DYN_GF_RM__GF_PDP_RM__SHIFT__CI__VI 0x00000008 -#define CC_PWR_DYN_GF_RM__GF_RF2P_RME__SHIFT__CI__VI 0x00000007 -#define CC_PWR_DYN_GF_RM__GF_RF2P_RM__SHIFT__CI__VI 0x00000000 -#define CC_PWR_DYN_RM1__BF_HD1P_RMEN__SHIFT__CI__VI 0x00000002 -#define CC_PWR_DYN_RM1__BF_HD1P_RM__SHIFT__CI__VI 0x00000000 -#define CC_PWR_DYN_RM1__BF_PDP_RMEN__SHIFT__CI__VI 0x00000005 -#define CC_PWR_DYN_RM1__BF_PDP_RM__SHIFT__CI__VI 0x00000003 -#define CC_PWR_DYN_RM1__BF_RF2P_RMEN__SHIFT__CI__VI 0x00000008 -#define CC_PWR_DYN_RM1__BF_RF2P_RM__SHIFT__CI__VI 0x00000006 -#define CC_PWR_DYN_RM1__GFX_HD1P_RMEN__SHIFT__CI__VI 0x0000000b -#define CC_PWR_DYN_RM1__GFX_HD1P_RM__SHIFT__CI__VI 0x00000009 -#define CC_PWR_DYN_RM1__GFX_PDP_RMEN__SHIFT__CI__VI 0x0000000e -#define CC_PWR_DYN_RM1__GFX_PDP_RM__SHIFT__CI__VI 0x0000000c -#define CC_PWR_DYN_RM1__GFX_RF2P_RMEN__SHIFT__CI__VI 0x00000011 -#define CC_PWR_DYN_RM1__GFX_RF2P_RM__SHIFT__CI__VI 0x0000000f -#define CC_PWR_DYN_RM1__UVD_HD1P_RMEN__SHIFT__CI__VI 0x00000014 -#define CC_PWR_DYN_RM1__UVD_HD1P_RM__SHIFT__CI__VI 0x00000012 -#define CC_PWR_DYN_RM1__UVD_PDP_RMEN__SHIFT__CI__VI 0x00000017 -#define CC_PWR_DYN_RM1__UVD_PDP_RM__SHIFT__CI__VI 0x00000015 -#define CC_PWR_DYN_RM1__UVD_RF2P_RMEN__SHIFT__CI__VI 0x0000001a -#define CC_PWR_DYN_RM1__UVD_RF2P_RM__SHIFT__CI__VI 0x00000018 -#define CC_PWR_DYN_RM__DT_HD1P_RMEN__SHIFT__CI__VI 0x00000014 -#define CC_PWR_DYN_RM__DT_HD1P_RM__SHIFT__CI__VI 0x00000012 -#define CC_PWR_DYN_RM__DT_PDP_RMEN__SHIFT__CI__VI 0x00000017 -#define CC_PWR_DYN_RM__DT_PDP_RM__SHIFT__CI__VI 0x00000015 -#define CC_PWR_DYN_RM__DT_RF2P_RMEN__SHIFT__CI__VI 0x0000001a -#define CC_PWR_DYN_RM__DT_RF2P_RM__SHIFT__CI__VI 0x00000018 -#define CC_PWR_DYN_RM__MC_HD1P_RMEN__SHIFT__CI__VI 0x0000000b -#define CC_PWR_DYN_RM__MC_HD1P_RM__SHIFT__CI__VI 0x00000009 -#define CC_PWR_DYN_RM__MC_PDP_RMEN__SHIFT__CI__VI 0x0000000e -#define CC_PWR_DYN_RM__MC_PDP_RM__SHIFT__CI__VI 0x0000000c -#define CC_PWR_DYN_RM__MC_RF2P_RMEN__SHIFT__CI__VI 0x00000011 -#define CC_PWR_DYN_RM__MC_RF2P_RM__SHIFT__CI__VI 0x0000000f -#define CC_PWR_DYN_RM__RM_REG_SEL__SHIFT__CI__VI 0x0000001b -#define CC_PWR_DYN_RM__SYS_HD1P_RMEN__SHIFT__CI__VI 0x00000002 -#define CC_PWR_DYN_RM__SYS_HD1P_RM__SHIFT__CI__VI 0x00000000 -#define CC_PWR_DYN_RM__SYS_PDP_RMEN__SHIFT__CI__VI 0x00000005 -#define CC_PWR_DYN_RM__SYS_PDP_RM__SHIFT__CI__VI 0x00000003 -#define CC_PWR_DYN_RM__SYS_RF2P_RMEN__SHIFT__CI__VI 0x00000008 -#define CC_PWR_DYN_RM__SYS_RF2P_RM__SHIFT__CI__VI 0x00000006 -#define CC_PWR_GF_RM__GF_PDP_RME__SHIFT__CI__VI 0x0000001c -#define CC_PWR_GF_RM__GF_PDP_RM__SHIFT__CI__VI 0x00000009 -#define CC_PWR_GF_RM__GF_RF2P_RME__SHIFT__CI__VI 0x00000008 -#define CC_PWR_GF_RM__GF_RF2P_RM__SHIFT__CI__VI 0x00000001 -#define CC_PWR_GF_RM__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_PWR_RM0__DT_HD1P_RMEN__SHIFT__CI__VI 0x00000015 -#define CC_PWR_RM0__DT_HD1P_RM__SHIFT__CI__VI 0x00000013 -#define CC_PWR_RM0__DT_PDP_RMEN__SHIFT__CI__VI 0x00000018 -#define CC_PWR_RM0__DT_PDP_RM__SHIFT__CI__VI 0x00000016 -#define CC_PWR_RM0__DT_RF2P_RMEN__SHIFT__CI__VI 0x0000001b -#define CC_PWR_RM0__DT_RF2P_RM__SHIFT__CI__VI 0x00000019 -#define CC_PWR_RM0__MC_HD1P_RMEN__SHIFT__CI__VI 0x0000000c -#define CC_PWR_RM0__MC_HD1P_RM__SHIFT__CI__VI 0x0000000a -#define CC_PWR_RM0__MC_PDP_RMEN__SHIFT__CI__VI 0x0000000f -#define CC_PWR_RM0__MC_PDP_RM__SHIFT__CI__VI 0x0000000d -#define CC_PWR_RM0__MC_RF2P_RMEN__SHIFT__CI__VI 0x00000012 -#define CC_PWR_RM0__MC_RF2P_RM__SHIFT__CI__VI 0x00000010 -#define CC_PWR_RM0__RM_FUSE_SEL__SHIFT__CI__VI 0x0000001c -#define CC_PWR_RM0__SYS_HD1P_RMEN__SHIFT__CI__VI 0x00000003 -#define CC_PWR_RM0__SYS_HD1P_RM__SHIFT__CI__VI 0x00000001 -#define CC_PWR_RM0__SYS_PDP_RMEN__SHIFT__CI__VI 0x00000006 -#define CC_PWR_RM0__SYS_PDP_RM__SHIFT__CI__VI 0x00000004 -#define CC_PWR_RM0__SYS_RF2P_RMEN__SHIFT__CI__VI 0x00000009 -#define CC_PWR_RM0__SYS_RF2P_RM__SHIFT__CI__VI 0x00000007 -#define CC_PWR_RM0__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_PWR_RM1__BF_HD1P_RMEN__SHIFT__CI__VI 0x00000003 -#define CC_PWR_RM1__BF_HD1P_RM__SHIFT__CI__VI 0x00000001 -#define CC_PWR_RM1__BF_PDP_RMEN__SHIFT__CI__VI 0x00000006 -#define CC_PWR_RM1__BF_PDP_RM__SHIFT__CI__VI 0x00000004 -#define CC_PWR_RM1__BF_RF2P_RMEN__SHIFT__CI__VI 0x00000009 -#define CC_PWR_RM1__BF_RF2P_RM__SHIFT__CI__VI 0x00000007 -#define CC_PWR_RM1__GFX_HD1P_RMEN__SHIFT__CI__VI 0x0000000c -#define CC_PWR_RM1__GFX_HD1P_RM__SHIFT__CI__VI 0x0000000a -#define CC_PWR_RM1__GFX_PDP_RMEN__SHIFT__CI__VI 0x0000000f -#define CC_PWR_RM1__GFX_PDP_RM__SHIFT__CI__VI 0x0000000d -#define CC_PWR_RM1__GFX_RF2P_RMEN__SHIFT__CI__VI 0x00000012 -#define CC_PWR_RM1__GFX_RF2P_RM__SHIFT__CI__VI 0x00000010 -#define CC_PWR_RM1__UVD_HD1P_RMEN__SHIFT__CI__VI 0x00000015 -#define CC_PWR_RM1__UVD_HD1P_RM__SHIFT__CI__VI 0x00000013 -#define CC_PWR_RM1__UVD_PDP_RMEN__SHIFT__CI__VI 0x00000018 -#define CC_PWR_RM1__UVD_PDP_RM__SHIFT__CI__VI 0x00000016 -#define CC_PWR_RM1__UVD_RF2P_RMEN__SHIFT__CI__VI 0x0000001b -#define CC_PWR_RM1__UVD_RF2P_RM__SHIFT__CI__VI 0x00000019 -#define CC_PWR_RM1__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 -#define CC_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT 0x00000000 -#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000 -#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004 -#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008 -#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c -#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010 -#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014 -#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018 -#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT__CI__VI 0x0000000c -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT__CI__VI 0x00000014 -#define CC_RB_REDUNDANCY__EN_REDUNDANCY__SHIFT__SI 0x0000001f -#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT__CI__VI 0x00000008 -#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT__CI__VI 0x00000010 -#define CC_RB_REDUNDANCY__FAILED_RB__SHIFT__SI 0x00000010 -#define CC_RB_REDUNDANCY__WRITE_DIS__SHIFT 0x00000000 -#define CC_RCU_CG_STRAPS__CTF_DISABLE__SHIFT__SI 0x00000012 -#define CC_RCU_CG_STRAPS__FDO_INIT_SPINUP_DUTY__SHIFT__SI 0x00000019 -#define CC_RCU_CG_STRAPS__FDO_INIT_SPINUP_TIME__SHIFT__SI 0x00000016 -#define CC_RCU_CG_STRAPS__FDO_INIT_STATIC_DUTY__SHIFT__SI 0x0000001c -#define CC_RCU_CG_STRAPS__SPARE__SHIFT__SI 0x00000015 -#define CC_RCU_CG_STRAPS__UNUSED__SHIFT__SI 0x00000001 -#define CC_RCU_CG_STRAPS__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_RCU_CMON_STRAPS__CMON_ADC_GAIN_ADJ__SHIFT__SI 0x00000006 -#define CC_RCU_CMON_STRAPS__CMON_BGADJ__SHIFT__SI 0x00000000 -#define CC_RCU_DC_MISC_STRAPS__AZ_AUD_PIN_DIS__SHIFT__SI 0x0000001a -#define CC_RCU_DC_MISC_STRAPS__DACA_BGADJ__SHIFT__SI 0x00000014 -#define CC_RCU_DC_MISC_STRAPS__DC_CP_DEBUG_DIS__SHIFT__SI 0x00000003 -#define CC_RCU_DC_MISC_STRAPS__DC_WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_RCU_DC_MISC_STRAPS__HDCP_DEBUG_ENABLE__SHIFT__SI 0x00000007 -#define CC_RCU_DC_MISC_STRAPS__HDCP_DIS__SHIFT__SI 0x00000002 -#define CC_RCU_DC_MISC_STRAPS__HDCP_KEYS_INVALID__SHIFT__SI 0x00000004 -#define CC_RCU_DC_MISC_STRAPS__HDMI_DISABLE__SHIFT__SI 0x00000005 -#define CC_RCU_DC_MISC_STRAPS__SPARE__SHIFT__SI 0x00000001 -#define CC_RCU_DC_MISC_STRAPS__UNUSED__SHIFT__SI 0x00000008 -#define CC_RCU_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT__SI 0x00000001 -#define CC_RCU_DC_PIPE_DIS__DC_WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_RCU_DYN_RM2__BF_HD1P_RMEN__SHIFT__SI 0x00000002 -#define CC_RCU_DYN_RM2__BF_HD1P_RM__SHIFT__SI 0x00000000 -#define CC_RCU_DYN_RM2__BF_PDP_RMEN__SHIFT__SI 0x00000005 -#define CC_RCU_DYN_RM2__BF_PDP_RM__SHIFT__SI 0x00000003 -#define CC_RCU_DYN_RM2__BF_RF2P_RMEN__SHIFT__SI 0x00000008 -#define CC_RCU_DYN_RM2__BF_RF2P_RM__SHIFT__SI 0x00000006 -#define CC_RCU_DYN_RM2__GFX_HD1P_RMEN__SHIFT__SI 0x0000000b -#define CC_RCU_DYN_RM2__GFX_HD1P_RM__SHIFT__SI 0x00000009 -#define CC_RCU_DYN_RM2__GFX_PDP_RMEN__SHIFT__SI 0x0000000e -#define CC_RCU_DYN_RM2__GFX_PDP_RM__SHIFT__SI 0x0000000c -#define CC_RCU_DYN_RM2__GFX_RF2P_RMEN__SHIFT__SI 0x00000011 -#define CC_RCU_DYN_RM2__GFX_RF2P_RM__SHIFT__SI 0x0000000f -#define CC_RCU_DYN_RM2__UVD_HD1P_RMEN__SHIFT__SI 0x00000014 -#define CC_RCU_DYN_RM2__UVD_HD1P_RM__SHIFT__SI 0x00000012 -#define CC_RCU_DYN_RM2__UVD_PDP_RMEN__SHIFT__SI 0x00000017 -#define CC_RCU_DYN_RM2__UVD_PDP_RM__SHIFT__SI 0x00000015 -#define CC_RCU_DYN_RM2__UVD_RF2P_RMEN__SHIFT__SI 0x0000001a -#define CC_RCU_DYN_RM2__UVD_RF2P_RM__SHIFT__SI 0x00000018 -#define CC_RCU_DYN_RM__DC_HD1P_RMEN__SHIFT__SI 0x00000014 -#define CC_RCU_DYN_RM__DC_HD1P_RM__SHIFT__SI 0x00000012 -#define CC_RCU_DYN_RM__DC_PDP_RMEN__SHIFT__SI 0x00000017 -#define CC_RCU_DYN_RM__DC_PDP_RM__SHIFT__SI 0x00000015 -#define CC_RCU_DYN_RM__DC_RF2P_RMEN__SHIFT__SI 0x0000001a -#define CC_RCU_DYN_RM__DC_RF2P_RM__SHIFT__SI 0x00000018 -#define CC_RCU_DYN_RM__MC_HD1P_RMEN__SHIFT__SI 0x0000000b -#define CC_RCU_DYN_RM__MC_HD1P_RM__SHIFT__SI 0x00000009 -#define CC_RCU_DYN_RM__MC_PDP_RMEN__SHIFT__SI 0x0000000e -#define CC_RCU_DYN_RM__MC_PDP_RM__SHIFT__SI 0x0000000c -#define CC_RCU_DYN_RM__MC_RF2P_RMEN__SHIFT__SI 0x00000011 -#define CC_RCU_DYN_RM__MC_RF2P_RM__SHIFT__SI 0x0000000f -#define CC_RCU_DYN_RM__SYS_HD1P_RMEN__SHIFT__SI 0x00000002 -#define CC_RCU_DYN_RM__SYS_HD1P_RM__SHIFT__SI 0x00000000 -#define CC_RCU_DYN_RM__SYS_PDP_RMEN__SHIFT__SI 0x00000005 -#define CC_RCU_DYN_RM__SYS_PDP_RM__SHIFT__SI 0x00000003 -#define CC_RCU_DYN_RM__SYS_RF2P_RMEN__SHIFT__SI 0x00000008 -#define CC_RCU_DYN_RM__SYS_RF2P_RM__SHIFT__SI 0x00000006 -#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT__CI 0x00000014 -#define CC_RCU_FUSES__CC_WRITE_DISABLE__SHIFT__CI__VI 0x00000003 -#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT__CI__VI 0x00000005 -#define CC_RCU_FUSES__DC_WRITE_DIS__SHIFT__CI__VI 0x0000000c -#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT__CI__VI 0x00000002 -#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT__CI__VI 0x00000006 -#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT__CI 0x00000018 -#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT__CI__VI 0x00000004 -#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT__CI 0x00000010 -#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT__CI 0x00000011 -#define CC_RCU_FUSES__GPU_DIS__SHIFT__CI__VI 0x00000001 -#define CC_RCU_FUSES__GPU_ID_WRITE_DIS__SHIFT__CI__VI 0x0000000b -#define CC_RCU_FUSES__HDCP_FUSE_DISABLE__SHIFT__CI__VI 0x0000000d -#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT__CI__VI 0x00000008 -#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT__CI 0x00000016 -#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT__CI 0x00000017 -#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT__CI 0x0000000e -#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT__CI__VI 0x00000009 -#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT__CI__VI 0x0000000a -#define CC_RCU_FUSES__RCU_SPARE__SHIFT__CI 0x00000019 -#define CC_RCU_FUSES__RED_WRITE_DIS__SHIFT__CI 0x00000015 -#define CC_RCU_FUSES__ROM_DIS__SHIFT__CI__VI 0x00000007 -#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT__CI 0x00000013 -#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT__CI 0x0000000f -#define CC_RCU_FUSES__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT__CI 0x00000012 -#define CC_RCU_ID_STRAPS__ATI_REV_ID__SHIFT__SI 0x0000001c -#define CC_RCU_ID_STRAPS__DEVICE_ID__SHIFT__SI 0x00000004 -#define CC_RCU_ID_STRAPS__MAJOR_REV_ID__SHIFT__SI 0x00000014 -#define CC_RCU_ID_STRAPS__MINOR_REV_ID__SHIFT__SI 0x00000018 -#define CC_RCU_ID_STRAPS__Reserved__SHIFT__SI 0x00000001 -#define CC_RCU_ID_STRAPS__WRITE_DIS__SHIFT__SI 0x00000000 -#define CC_RCU_MISC_STRAPS__LEAKAGE_ID__SHIFT__SI 0x00000004 -#define CC_RCU_MISC_STRAPS__PACKAGE_ID__SHIFT__SI 0x00000000 -#define CC_RCU_MISC_STRAPS__SPARE__SHIFT__SI 0x00000010 -#define CC_RCU_MISC_STRAPS__UNUSED__SHIFT__SI 0x0000000e -#define CC_RCU_TMON_STRAPS__TMON0_BGADJ__SHIFT__SI 0x00000000 -#define CC_RCU_TMON_STRAPS__TMON1_BGADJ__SHIFT__SI 0x00000008 -#define CC_RCU_TMON_STRAPS__TMON2_BGADJ__SHIFT__SI 0x00000010 -#define CC_RCU_TMON_STRAPS__TMON3_BGADJ__SHIFT__SI 0x00000018 -#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT__CI__VI 0x00000000 -#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT__CI__VI 0x00000008 -#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT__CI__VI 0x00000010 -#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT__CI__VI 0x00000018 -#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT__CI__VI 0x0000001d -#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT__CI__VI 0x0000001c -#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT__CI__VI 0x00000001 -#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT__CI__VI 0x00000012 -#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT__CI__VI 0x00000017 -#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT__CI__VI 0x00000014 -#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT__CI__VI 0x00000015 -#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT__CI__VI 0x00000016 -#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT__CI__VI 0x00000013 -#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT__CI__VI 0x00000009 -#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT__CI__VI 0x00000002 -#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT__CI__VI 0x0000000b -#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT__CI__VI 0x0000001b -#define CC_SMU_MISC_FUSES__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT__CI__VI 0x0000000c -#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT__CI__VI 0x0000000d -#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT__CI__VI 0x0000001a -#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT__CI__VI 0x00000016 -#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT__CI__VI 0x00000017 -#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT__CI__VI 0x00000018 -#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT__CI__VI 0x0000000a -#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT__CI__VI 0x00000008 -#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT__CI__VI 0x00000007 -#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT__CI__VI 0x00000001 -#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT__CI__VI 0x00000006 -#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT__CI__VI 0x0000000e -#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT__CI__VI 0x0000000b -#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT__CI__VI 0x00000009 -#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT__CI__VI 0x00000019 -#define CC_SMU_TST_EFUSE1_MISC__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 -#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 -#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT__CI__VI 0x00000018 -#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT__CI__VI 0x0000001c -#define CC_SQC_BANK_DISABLE__WRITE_DIS__SHIFT 0x00000000 -#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 -#define CC_SYS_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT 0x00000000 -#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY__SHIFT__SI__CI 0x0000001f -#define CC_SYS_RB_REDUNDANCY__FAILED_RB__SHIFT__SI__CI 0x00000010 -#define CC_SYS_RB_REDUNDANCY__WRITE_DIS__SHIFT 0x00000000 -#define CC_THM_FDO__FDO_INIT_SPINUP_DUTY__SHIFT__CI 0x00000004 -#define CC_THM_FDO__FDO_INIT_SPINUP_TIME__SHIFT__CI 0x00000001 -#define CC_THM_FDO__FDO_INIT_STATIC_DUTY__SHIFT__CI 0x00000007 -#define CC_THM_FDO__FUSES_PROGRAMMED__SHIFT__CI 0x0000000a -#define CC_THM_FDO__UNUSED__SHIFT__CI 0x0000001f -#define CC_THM_FDO__WRITE_DIS__SHIFT__CI 0x00000000 -#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT__CI 0x00000019 -#define CC_THM_STRAPS0__NUM_ACQ__SHIFT__CI 0x00000012 -#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT__CI 0x00000001 -#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT__CI 0x0000001a -#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT__CI 0x00000009 -#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT__CI 0x0000001b -#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT__CI 0x0000001c -#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT__CI 0x0000001d -#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT__CI 0x00000015 -#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT__CI 0x00000011 -#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT__CI 0x00000018 -#define CC_THM_STRAPS0__UNUSED__SHIFT__CI 0x0000001f -#define CC_THM_STRAPS0__WRITE_DIS__SHIFT__CI 0x00000000 -#define CC_THM_STRAPS1__TMON2_BGADJ__SHIFT__CI 0x00000001 -#define CC_THM_STRAPS1__TMON3_BGADJ__SHIFT__CI 0x00000009 -#define CC_THM_STRAPS1__UNUSED__SHIFT__CI 0x0000001f -#define CC_THM_STRAPS1__WRITE_DIS__SHIFT__CI 0x00000000 -#define CC_TST_EFUSE0_RM__HD_FUSE__SHIFT 0x00000011 -#define CC_TST_EFUSE0_RM__PDP_FUSE__SHIFT 0x00000001 -#define CC_TST_EFUSE0_RM__RF_FUSE__SHIFT 0x00000018 -#define CC_TST_EFUSE0_RM__RME_FUSE__SHIFT 0x0000001f -#define CC_TST_EFUSE0_RM__WRITE_DIS__SHIFT 0x00000000 -#define CC_TST_EFUSE1_MISC__GPU_DISABLE__SHIFT 0x00000003 -#define CC_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x00000001 -#define CC_TST_EFUSE1_MISC__INTERNAL_GFX_DISABLE__SHIFT 0x00000004 -#define CC_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x00000002 -#define CC_TST_EFUSE1_MISC__WRITE_DIS__SHIFT 0x00000000 -#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT__CI__VI 0x00000004 -#define CC_TST_ID_STRAPS__GPU_ID_WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT__CI__VI 0x00000014 -#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT__CI__VI 0x00000018 -#define CEC_ADDR__LOGIC_ADDR0__SHIFT__CI__VI 0x00000000 -#define CEC_ADDR__LOGIC_ADDR1__SHIFT__CI__VI 0x00000004 -#define CEC_ADDR__LOGIC_ADDR2__SHIFT__CI__VI 0x00000008 -#define CEC_ADDR__PHYSICAL_ADDR__SHIFT__CI__VI 0x00000010 -#define CEC_CONTROL__BACO_D0_PME_INTX_SEL__SHIFT__CI__VI 0x00000004 -#define CEC_CONTROL__CEC_ENABLE__SHIFT__CI__VI 0x00000000 -#define CEC_CONTROL__INTX_FUNC_NUM__SHIFT__CI__VI 0x0000000a -#define CEC_CONTROL__INT_MSG_TYPE__SHIFT__CI__VI 0x00000005 -#define CEC_CONTROL__PME_FUNC_NUM__SHIFT__CI__VI 0x00000002 -#define CEC_CONTROL__SAMPLE_CLK_SRC_SEL__SHIFT__CI__VI 0x00000008 -#define CEC_CONTROL__TX_SEND_ENABLE__SHIFT__CI__VI 0x00000001 -#define CEC_DATA_LENGTH__RX_DATA_LENGTH__SHIFT__CI__VI 0x00000004 -#define CEC_DATA_LENGTH__TX_DATA_LENGTH__SHIFT__CI__VI 0x00000000 -#define CEC_HPD_CONTROL__HPD_CONNECTION_TIMER__SHIFT__CI__VI 0x00000001 -#define CEC_HPD_CONTROL__HPD_EN__SHIFT__CI__VI 0x00000000 -#define CEC_HPD_CONTROL__HPD_RX_INT_TIMER__SHIFT__CI__VI 0x00000010 -#define CEC_HPD_TOGGLE_FILT_CONTROL__HPD_CONNECT_INT_DELAY__SHIFT__CI__VI 0x00000000 -#define CEC_HPD_TOGGLE_FILT_CONTROL__HPD_DISCONNECT_INT_DELAY__SHIFT__CI__VI 0x00000008 -#define CEC_INT_EN__BLOCK_ALL_BROADCAST_EN__SHIFT__CI__VI 0x00000002 -#define CEC_INT_EN__BLOCK_PART_BROADCAST_EN__SHIFT__CI__VI 0x00000001 -#define CEC_INT_EN__CEC_LINE_ERR_EN__SHIFT__CI__VI 0x00000000 -#define CEC_INT_EN__DEST_MISMATCH_EN__SHIFT__CI__VI 0x00000007 -#define CEC_INT_EN__HPD_INT_EN__SHIFT__CI__VI 0x00000008 -#define CEC_INT_EN__HPD_UNPLUG_INT_EN__SHIFT__CI__VI 0x00000009 -#define CEC_INT_EN__LOST_ARB_ERR_EN__SHIFT__CI__VI 0x00000006 -#define CEC_INT_EN__PHYSICAL_ADDRESS_INT_EN__SHIFT__CI__VI 0x0000000a -#define CEC_INT_EN__RETRY_FAILED_EN__SHIFT__CI__VI 0x00000003 -#define CEC_INT_EN__RX_IOC_EN__SHIFT__CI__VI 0x00000005 -#define CEC_INT_EN__TX_IOC_EN__SHIFT__CI__VI 0x00000004 -#define CEC_MISC__RETRY_COUNTER__SHIFT__CI__VI 0x00000000 -#define CEC_PAD_CNTL__CEC_PAD_A__SHIFT__CI__VI 0x00000000 -#define CEC_PAD_CNTL__CEC_PAD_CNTL_EN__SHIFT__CI__VI 0x0000000c -#define CEC_PAD_CNTL__CEC_PAD_MODE__SHIFT__CI__VI 0x00000002 -#define CEC_PAD_CNTL__CEC_PAD_SCHMEN__SHIFT__CI__VI 0x0000000b -#define CEC_PAD_CNTL__CEC_PAD_SEL__SHIFT__CI__VI 0x00000001 -#define CEC_PAD_CNTL__CEC_PAD_SLEWN__SHIFT__CI__VI 0x00000009 -#define CEC_PAD_CNTL__CEC_PAD_SN0__SHIFT__CI__VI 0x00000005 -#define CEC_PAD_CNTL__CEC_PAD_SN1__SHIFT__CI__VI 0x00000006 -#define CEC_PAD_CNTL__CEC_PAD_SN2__SHIFT__CI__VI 0x00000007 -#define CEC_PAD_CNTL__CEC_PAD_SN3__SHIFT__CI__VI 0x00000008 -#define CEC_PAD_CNTL__CEC_PAD_SPARE__SHIFT__CI__VI 0x00000003 -#define CEC_PAD_CNTL__CEC_PAD_WAKE__SHIFT__CI__VI 0x0000000a -#define CEC_RX_DATA_0__RX_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_RX_DATA_0__RX_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_RX_DATA_0__RX_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_RX_DATA_0__RX_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_RX_DATA_1__RX_BYTE_4__SHIFT__CI__VI 0x00000000 -#define CEC_RX_DATA_1__RX_BYTE_5__SHIFT__CI__VI 0x00000008 -#define CEC_RX_DATA_1__RX_BYTE_6__SHIFT__CI__VI 0x00000010 -#define CEC_RX_DATA_1__RX_BYTE_7__SHIFT__CI__VI 0x00000018 -#define CEC_RX_DATA_2__RX_BYTE_8__SHIFT__CI__VI 0x00000000 -#define CEC_RX_DATA_2__RX_BYTE_9__SHIFT__CI__VI 0x00000008 -#define CEC_RX_DATA_2__RX_BYTE_A__SHIFT__CI__VI 0x00000010 -#define CEC_RX_DATA_2__RX_BYTE_B__SHIFT__CI__VI 0x00000018 -#define CEC_RX_DATA_3__RX_BYTE_C__SHIFT__CI__VI 0x00000000 -#define CEC_RX_DATA_3__RX_BYTE_D__SHIFT__CI__VI 0x00000008 -#define CEC_RX_DATA_3__RX_BYTE_E__SHIFT__CI__VI 0x00000010 -#define CEC_RX_DATA_3__RX_BYTE_F__SHIFT__CI__VI 0x00000018 -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_SCRATCH_REG_0__SCRATCH_REG0_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_SCRATCH_REG_1__SCRATCH_REG1_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_SCRATCH_REG_2__SCRATCH_REG2_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_SCRATCH_REG_3__SCRATCH_REG3_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_SCRATCH_REG_4__SCRATCH_REG4_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_SCRATCH_REG_5__SCRATCH_REG5_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_STATUS__CEC_RESET_DONE__SHIFT__CI__VI 0x0000000e -#define CEC_STATUS__DEST_MISMATCH__SHIFT__CI__VI 0x00000007 -#define CEC_STATUS__HPD_CONNECTION_STATUS__SHIFT__CI__VI 0x00000008 -#define CEC_STATUS__HPD_PLUG_EVENT__SHIFT__CI__VI 0x00000009 -#define CEC_STATUS__HPD_UNPLUG_EVENT__SHIFT__CI__VI 0x0000000a -#define CEC_STATUS__LINE_ERROR__SHIFT__CI__VI 0x00000001 -#define CEC_STATUS__LOST_ARB_ERR__SHIFT__CI__VI 0x00000006 -#define CEC_STATUS__PHYSICAL_ADDRESS_ALLO_EVENT__SHIFT__CI__VI 0x0000000c -#define CEC_STATUS__PHYSICAL_ADDRESS_LOSE_EVENT__SHIFT__CI__VI 0x0000000d -#define CEC_STATUS__PHYSICAL_ADDRESS_READY__SHIFT__CI__VI 0x0000000b -#define CEC_STATUS__RETRY_FAILED__SHIFT__CI__VI 0x00000003 -#define CEC_STATUS__RX_BUFFER_BUSY__SHIFT__CI__VI 0x00000000 -#define CEC_STATUS__RX_IOC__SHIFT__CI__VI 0x00000005 -#define CEC_STATUS__TX_IOC__SHIFT__CI__VI 0x00000004 -#define CEC_SW_OPCODE_0__WAKE_OPCODE_0__SHIFT__CI__VI 0x00000000 -#define CEC_SW_OPCODE_0__WAKE_OPCODE_1__SHIFT__CI__VI 0x00000008 -#define CEC_SW_OPCODE_0__WAKE_OPCODE_2__SHIFT__CI__VI 0x00000010 -#define CEC_SW_OPCODE_0__WAKE_OPCODE_3__SHIFT__CI__VI 0x00000018 -#define CEC_SW_OPCODE_1__WAKE_OPCODE_4__SHIFT__CI__VI 0x00000000 -#define CEC_SW_OPCODE_1__WAKE_OPCODE_5__SHIFT__CI__VI 0x00000008 -#define CEC_SW_OPCODE_1__WAKE_OPCODE_6__SHIFT__CI__VI 0x00000010 -#define CEC_SW_OPCODE_1__WAKE_OPCODE_7__SHIFT__CI__VI 0x00000018 -#define CEC_TX_DATA_0__TX_BYTE_0__SHIFT__CI__VI 0x00000000 -#define CEC_TX_DATA_0__TX_BYTE_1__SHIFT__CI__VI 0x00000008 -#define CEC_TX_DATA_0__TX_BYTE_2__SHIFT__CI__VI 0x00000010 -#define CEC_TX_DATA_0__TX_BYTE_3__SHIFT__CI__VI 0x00000018 -#define CEC_TX_DATA_1__TX_BYTE_4__SHIFT__CI__VI 0x00000000 -#define CEC_TX_DATA_1__TX_BYTE_5__SHIFT__CI__VI 0x00000008 -#define CEC_TX_DATA_1__TX_BYTE_6__SHIFT__CI__VI 0x00000010 -#define CEC_TX_DATA_1__TX_BYTE_7__SHIFT__CI__VI 0x00000018 -#define CEC_TX_DATA_2__TX_BYTE_8__SHIFT__CI__VI 0x00000000 -#define CEC_TX_DATA_2__TX_BYTE_9__SHIFT__CI__VI 0x00000008 -#define CEC_TX_DATA_2__TX_BYTE_A__SHIFT__CI__VI 0x00000010 -#define CEC_TX_DATA_2__TX_BYTE_B__SHIFT__CI__VI 0x00000018 -#define CEC_TX_DATA_3__TX_BYTE_C__SHIFT__CI__VI 0x00000000 -#define CEC_TX_DATA_3__TX_BYTE_D__SHIFT__CI__VI 0x00000008 -#define CEC_TX_DATA_3__TX_BYTE_E__SHIFT__CI__VI 0x00000010 -#define CEC_TX_DATA_3__TX_BYTE_F__SHIFT__CI__VI 0x00000018 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT__CI__VI 0x00000010 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT__CI__VI 0x00000010 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT__CI__VI 0x00000010 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT__CI__VI 0x00000010 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT__CI__VI 0x00000000 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT__CI__VI 0x00000010 -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT__CI__VI 0x00000000 -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT__CI__VI 0x00000010 -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT__CI__VI 0x00000000 -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT__CI__VI 0x00000010 -#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT__CI__VI 0x00000000 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000018 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__CI__VI 0x0000001a -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__CI__VI 0x00000017 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT__CI__VI 0x00000010 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__CI__VI 0x0000000a -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT__CI__VI 0x00000000 -#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008 -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000 -#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000 -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C0_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C0_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C0_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C0_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C0_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C0_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C0_TA_SQC_CTRL_REG__SQC__SHIFT__SI 0x00000010 -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C0_TA_SQC_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C0_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C0_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C1_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C1_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C1_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C1_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C1_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C1_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C1_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C1_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C1_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C1_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C2_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C2_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C2_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C2_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C2_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C2_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C2_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C2_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C2_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C2_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C3_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C3_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C3_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C3_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C3_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C3_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C3_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C3_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C3_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C3_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C4_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C4_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C4_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C4_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C4_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C4_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C4_TA_SQC_CTRL_REG__SQC__SHIFT__SI 0x00000010 -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C4_TA_SQC_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C4_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C4_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C5_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C5_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C5_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C5_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C5_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C5_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C5_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C5_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C5_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C5_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C6_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C6_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C6_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C6_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C6_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C6_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C6_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C6_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C6_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C6_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C7_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C7_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S0C7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C7_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S0C7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C7_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S0C7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C7_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S0C7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C7_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S0C7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C7_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C7_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S0C7_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S0C7_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C0_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C0_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C0_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C0_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C0_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C0_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C0_TA_SQC_CTRL_REG__SQC__SHIFT__SI 0x00000010 -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C0_TA_SQC_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C0_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C0_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C1_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C1_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C1_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C1_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C1_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C1_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C1_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C1_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C1_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C1_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C2_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C2_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C2_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C2_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C2_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C2_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C2_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C2_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C2_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C2_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C3_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C3_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C3_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C3_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C3_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C3_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C3_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C3_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C3_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C3_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C4_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C4_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C4_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C4_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C4_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C4_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C4_TA_SQC_CTRL_REG__SQC__SHIFT__SI 0x00000010 -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C4_TA_SQC_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C4_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C4_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C5_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C5_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C5_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C5_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C5_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C5_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C5_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C5_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C5_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C5_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C6_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C6_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C6_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C6_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C6_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C6_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C6_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C6_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C6_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C6_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C7_LDS_SQ_CTRL_REG__LDS__SHIFT__SI 0x00000000 -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C7_LDS_SQ_CTRL_REG__SQ__SHIFT__SI 0x00000010 -#define CGTS_S1C7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C7_SP0_CTRL_REG__SP00__SHIFT__SI 0x00000000 -#define CGTS_S1C7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C7_SP0_CTRL_REG__SP01__SHIFT__SI 0x00000010 -#define CGTS_S1C7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C7_SP1_CTRL_REG__SP10__SHIFT__SI 0x00000000 -#define CGTS_S1C7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C7_SP1_CTRL_REG__SP11__SHIFT__SI 0x00000010 -#define CGTS_S1C7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C7_TA_CTRL_REG__TA_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C7_TA_CTRL_REG__TA__SHIFT__SI 0x00000000 -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT__SI 0x00000018 -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT__SI 0x0000001a -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT__SI 0x00000017 -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000001b -#define CGTS_S1C7_TD_TCP_CTRL_REG__TCP__SHIFT__SI 0x00000010 -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT__SI 0x00000008 -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT__SI 0x0000000a -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT__SI 0x00000007 -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT__SI 0x0000000b -#define CGTS_S1C7_TD_TCP_CTRL_REG__TD__SHIFT__SI 0x00000000 -#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010 -#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016 -#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018 -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000 -#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015 -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014 -#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011 -#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 -#define CGTS_TCC_DISABLE__WRITE_DIS__SHIFT 0x00000000 -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019 -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018 -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f -#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c -#define CGTT_BIF_CLK_CTRL0__OFF_HYSTERESIS__SHIFT__SI 0x00000004 -#define CGTT_BIF_CLK_CTRL0__ON_DELAY__SHIFT__SI 0x00000000 -#define CGTT_BIF_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT__SI 0x0000001f -#define CGTT_BIF_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT__SI 0x0000001e -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT__CI__VI 0x00000004 -#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT__CI__VI 0x00000000 -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT__CI__VI 0x0000001e -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT__CI__VI 0x0000001f -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT__CI__VI 0x00000004 -#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT__CI__VI 0x00000000 -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT__CI__VI 0x0000001e -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT__CI__VI 0x0000001f -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f -#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_IA_CLK_CTRL__ADC_OVERRIDE__SHIFT__SI 0x0000001c -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT__CI__VI 0x0000001e -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT__SI 0x0000001d -#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 -#define CGTT_IA_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT__SI 0x0000001e -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT__CI__VI 0x0000001d -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT__CI__VI 0x0000001c -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d -#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x00000019 -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b -#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x0000001a -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f -#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT__SI__CI 0x00000018 -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT__SI__CI 0x00000018 -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT__SI__CI 0x00000018 -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT__SI__CI 0x00000018 -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e -#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT__SI__CI 0x0000001c -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT__CI 0x0000001c -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT__CI__VI 0x0000001d -#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT__CI__VI 0x0000001a -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT__CI__VI 0x00000004 -#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT__CI__VI 0x00000000 -#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT__CI__VI 0x00000019 -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT__CI__VI 0x0000001e -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT__CI__VI 0x0000001f -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT__CI__VI 0x0000001b -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT__CI__VI 0x00000018 -#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_ACLK_STATUS__ACLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000001 -#define CG_ACLK_STATUS__ACLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT__CI__VI 0x00000000 -#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT__CI__VI 0x00000007 -#define CG_AM_0_BUSY_CNT__AM_0_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_1_BUSY_CNT__AM_1_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_2_BUSY_CNT__AM_2_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_3_BUSY_CNT__AM_3_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_4_BUSY_CNT__AM_4_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_5_BUSY_CNT__AM_5_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_6_BUSY_CNT__AM_6_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_7_BUSY_CNT__AM_7_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_CNTL__START_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AM_CNTL__START_SCLK_CNT__SHIFT__CI__VI 0x00000001 -#define CG_AM_SATURATION_LIMIT__AM_SATURATION_LIMIT__SHIFT__CI__VI 0x00000000 -#define CG_AM_SCLK_CNT__AM_SCLK_CNT__SHIFT__CI__VI 0x00000000 -#define CG_AZ_REQ_AND_RSP__CG_CLIENT_REQ__SHIFT 0x00000000 -#define CG_AZ_REQ_AND_RSP__CG_CLIENT_RESP__SHIFT 0x00000008 -#define CG_AZ_REQ_AND_RSP__CLIENT_CG_REQ__SHIFT 0x00000010 -#define CG_AZ_REQ_AND_RSP__CLIENT_CG_RESP__SHIFT 0x00000018 -#define CG_AZ_STATUS__BUSY__SHIFT__CI__VI 0x00000000 -#define CG_BIF_REQ_AND_RSP__CG_CLIENT_REQ__SHIFT__CI__VI 0x00000000 -#define CG_BIF_REQ_AND_RSP__CG_CLIENT_RESP__SHIFT__CI__VI 0x00000008 -#define CG_BIF_REQ_AND_RSP__CLIENT_CG_REQ__SHIFT 0x00000010 -#define CG_BIF_REQ_AND_RSP__CLIENT_CG_RESP__SHIFT 0x00000018 -#define CG_BUSY_SAMPLING_PARAMETERS__BUSY_SAMPLING_PERIOD__SHIFT__SI 0x00000000 -#define CG_BUSY_SAMPLING_PARAMETERS__BUSY_SAMPLING_UNIT__SHIFT__SI 0x00000010 -#define CG_CAC_CTRL_2__CAC_ENABLE__SHIFT__CI 0x00000000 -#define CG_CAC_CTRL__CAC_ENABLE__SHIFT__SI 0x00000008 -#define CG_CAC_CTRL__CAC_WINDOW__SHIFT__SI__CI 0x00000000 -#define CG_CAC_CTRL__OCP_CAC_WINDOW__SHIFT__SI 0x00000009 -#define CG_CAC_CTRL__OCP_OUT_SEL__SHIFT__CI 0x0000001f -#define CG_CAC_CTRL__OCP_OUT_SEL__SHIFT__SI 0x00000019 -#define CG_CAC_CTRL__OCP_SAMPLE_WINDOW_SIZE__SHIFT__CI 0x0000001b -#define CG_CAC_CTRL__OCP_SAMPLE_WINDOW_SIZE__SHIFT__SI 0x00000015 -#define CG_CGLS_TILE_0__OVERRIDE__SHIFT__SI 0x00000000 -#define CG_CGTT_LOCAL_0__OVERRIDE__SHIFT__SI 0x00000000 -#define CG_CGTT_LOCAL_1__OVERRIDE__SHIFT__SI 0x00000000 -#define CG_CGTT_OVERRIDE_0__CG_ROM_cgtt_sclk_override__SHIFT__CI__VI 0x00000005 -#define CG_CGTT_OVERRIDE_0__CG_SMU_cgtt_refclk_override__SHIFT__CI__VI 0x00000002 -#define CG_CGTT_OVERRIDE_0__CG_SMU_cgtt_sclk_override__SHIFT__CI__VI 0x00000000 -#define CG_CHRONO_31_0__CG_CHRONO_31_0__SHIFT 0x00000000 -#define CG_CHRONO_63_32__CG_CHRONO_63_32__SHIFT 0x00000000 -#define CG_CLIENT_HS_CNTL__RESERVED__SHIFT__CI__VI 0x00000002 -#define CG_CLIENT_HS_CNTL__SKIP_DC_HS__SHIFT__CI__VI 0x00000001 -#define CG_CLIENT_HS_CNTL__SKIP_VCE_HS__SHIFT__CI__VI 0x00000000 -#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT__CI__VI 0x00000018 -#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT__CI__VI 0x00000016 -#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT__CI__VI 0x00000000 -#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT__CI__VI 0x00000003 -#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT__CI__VI 0x00000008 -#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT__CI__VI 0x00000015 -#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT__CI__VI 0x00000014 -#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT__CI__VI 0x00000013 -#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT__CI__VI 0x00000012 -#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT__CI__VI 0x00000011 -#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT__CI__VI 0x00000010 -#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT__CI__VI 0x0000000f -#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT__CI__VI 0x0000000e -#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT__CI__VI 0x00000002 -#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT__SI 0x0000000d -#define CG_CLKPIN_CNTL__CLK_SPARE__SHIFT__SI 0x00000018 -#define CG_CLKPIN_CNTL__CML_CTRL__SHIFT__SI 0x00000016 -#define CG_CLKPIN_CNTL__ENABLE_XCLK__SHIFT__SI 0x00000000 -#define CG_CLKPIN_CNTL__MUX_TCLK_TO_XCLK__SHIFT__SI 0x00000008 -#define CG_CLKPIN_CNTL__WRITE_DISABLE__SHIFT__CI__VI 0x00000000 -#define CG_CLKPIN_CNTL__XO_IN2_BIDIR_CML_OE__SHIFT__SI 0x00000015 -#define CG_CLKPIN_CNTL__XO_IN2_CML_RXEN__SHIFT__SI 0x00000014 -#define CG_CLKPIN_CNTL__XO_IN2_ICORE_CLK_OE__SHIFT__SI 0x00000013 -#define CG_CLKPIN_CNTL__XO_IN2_OSCIN_EN__SHIFT__SI 0x00000012 -#define CG_CLKPIN_CNTL__XO_IN_BIDIR_CML_OE__SHIFT__SI 0x00000011 -#define CG_CLKPIN_CNTL__XO_IN_CML_RXEN__SHIFT__SI 0x00000010 -#define CG_CLKPIN_CNTL__XO_IN_ICORE_CLK_OE__SHIFT__SI 0x0000000f -#define CG_CLKPIN_CNTL__XO_IN_OSCIN_EN__SHIFT__SI 0x0000000e -#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT__CI__VI 0x00000001 -#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT__SI 0x00000009 -#define CG_CLK_DIVIDER_STATUS_0__DCLK_DIVIDER_STATUS__SHIFT__CI__VI 0x00000010 -#define CG_CLK_DIVIDER_STATUS_0__LCLK_DIVIDER_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_CLK_DIVIDER_STATUS_0__SCLK_DIVIDER_STATUS__SHIFT__CI__VI 0x00000008 -#define CG_CLK_DIVIDER_STATUS_0__VCLK_DIVIDER_STATUS__SHIFT__CI__VI 0x00000018 -#define CG_CLK_DIVIDER_STATUS_1__ACLK_DIVIDER_STATUS__SHIFT__CI__VI 0x00000008 -#define CG_CLK_DIVIDER_STATUS_1__ECLK_DIVIDER_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_CLK_DIVIDER_STATUS_1__EVCLK_DIVIDER_STATUS__SHIFT__CI__VI 0x00000016 -#define CG_CLK_DIVIDER_STATUS_1__SAMCLK_DIVIDER_STATUS__SHIFT__CI__VI 0x0000000f -#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000001 -#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_DC_REQ_AND_RSP__CG_CLIENT_REQ__SHIFT__SI 0x00000000 -#define CG_DC_REQ_AND_RSP__CG_CLIENT_RESP__SHIFT__SI 0x00000008 -#define CG_DC_REQ_AND_RSP__CLIENT_CG_REQ__SHIFT__SI 0x00000010 -#define CG_DC_REQ_AND_RSP__CLIENT_CG_RESP__SHIFT__SI 0x00000018 -#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT__CI__VI 0x00000000 -#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT__SI 0x00000018 -#define CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT__SI 0x00000000 -#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT__SI 0x0000001a -#define CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT__SI 0x00000002 -#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT__CI__VI 0x00000018 -#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT__CI__VI 0x00000000 -#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x00000004 -#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x0000001c -#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x00000014 -#define CG_DISPLAY_GAP_COUNTER__VBI_PREDICTION_COUNT__SHIFT__CI 0x00000000 -#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_ECLK_OVERCLOCKING_ATTEMPTS__ACLK_ATTEMPTS__SHIFT__CI__VI 0x00000010 -#define CG_ECLK_OVERCLOCKING_ATTEMPTS__ECLK_ATTEMPTS__SHIFT__CI__VI 0x00000000 -#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000001 -#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_EVCLK_CNTL__EVCLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_EVCLK_CNTL__EVCLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_EVCLK_CNTL__EVCLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_EVCLK_CNTL__EVCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_EVCLK_STATUS__EVCLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000001 -#define CG_EVCLK_STATUS__EVCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT__SI__CI 0x00000008 -#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT__SI__CI 0x00000011 -#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT__SI__CI 0x00000010 -#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT__SI__CI 0x00000017 -#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT__SI__CI 0x00000018 -#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT__SI__CI 0x00000000 -#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT__SI__CI 0x0000001e -#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT__SI__CI 0x00000000 -#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT__SI__CI 0x00000008 -#define CG_FDO_CTRL1__M__SHIFT__SI__CI 0x00000010 -#define CG_FDO_CTRL1__RESERVED__SHIFT__SI__CI 0x00000018 -#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT__SI__CI 0x00000008 -#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT__SI__CI 0x0000000b -#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT__SI__CI 0x00000019 -#define CG_FDO_CTRL2__TMAX__SHIFT__SI__CI 0x00000011 -#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT__SI__CI 0x0000000e -#define CG_FDO_CTRL2__TMIN__SHIFT__SI__CI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_0__DOWN_TREND_COEFFICIENT_0__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_0__UP_TREND_COEFFICIENT_0__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_10__DOWN_TREND_COEFFICIENT_10__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_10__UP_TREND_COEFFICIENT_10__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_11__DOWN_TREND_COEFFICIENT_11__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_11__UP_TREND_COEFFICIENT_11__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_12__DOWN_TREND_COEFFICIENT_12__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_12__UP_TREND_COEFFICIENT_12__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_13__DOWN_TREND_COEFFICIENT_13__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_13__UP_TREND_COEFFICIENT_13__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_14__DOWN_TREND_COEFFICIENT_14__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_14__UP_TREND_COEFFICIENT_14__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_1__DOWN_TREND_COEFFICIENT_1__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_1__UP_TREND_COEFFICIENT_1__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_2__DOWN_TREND_COEFFICIENT_2__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_2__UP_TREND_COEFFICIENT_2__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_3__DOWN_TREND_COEFFICIENT_3__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_3__UP_TREND_COEFFICIENT_3__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_4__DOWN_TREND_COEFFICIENT_4__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_4__UP_TREND_COEFFICIENT_4__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_5__DOWN_TREND_COEFFICIENT_5__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_5__UP_TREND_COEFFICIENT_5__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_6__DOWN_TREND_COEFFICIENT_6__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_6__UP_TREND_COEFFICIENT_6__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_7__DOWN_TREND_COEFFICIENT_7__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_7__UP_TREND_COEFFICIENT_7__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_8__DOWN_TREND_COEFFICIENT_8__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_8__UP_TREND_COEFFICIENT_8__SHIFT__SI 0x00000000 -#define CG_FIR_FILTER_COEFF_TAP_9__DOWN_TREND_COEFFICIENT_9__SHIFT__SI 0x0000000a -#define CG_FIR_FILTER_COEFF_TAP_9__UP_TREND_COEFFICIENT_9__SHIFT__SI 0x00000000 -#define CG_FPS_CNT__FPS_CNT__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_FREQ_TRAN_VOTING__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000002 -#define CG_FREQ_TRAN_VOTING__BIF_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000003 -#define CG_FREQ_TRAN_VOTING__DRMDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000016 -#define CG_FREQ_TRAN_VOTING__DRMDMA_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000017 -#define CG_FREQ_TRAN_VOTING__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x0000000c -#define CG_FREQ_TRAN_VOTING__DRM_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x0000000d -#define CG_FREQ_TRAN_VOTING__GFX_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000000 -#define CG_FREQ_TRAN_VOTING__GFX_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000001 -#define CG_FREQ_TRAN_VOTING__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000004 -#define CG_FREQ_TRAN_VOTING__HDP_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000005 -#define CG_FREQ_TRAN_VOTING__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000010 -#define CG_FREQ_TRAN_VOTING__IDCT_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000011 -#define CG_FREQ_TRAN_VOTING__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000008 -#define CG_FREQ_TRAN_VOTING__IH_SEM_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000009 -#define CG_FREQ_TRAN_VOTING__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x0000000a -#define CG_FREQ_TRAN_VOTING__PDMA_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x0000000b -#define CG_FREQ_TRAN_VOTING__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000006 -#define CG_FREQ_TRAN_VOTING__ROM_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000007 -#define CG_FREQ_TRAN_VOTING__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x00000018 -#define CG_FREQ_TRAN_VOTING__UVD_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x00000019 -#define CG_FREQ_TRAN_VOTING__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT__SI 0x0000001a -#define CG_FREQ_TRAN_VOTING__VCE_STATIC_SCREEN_VOTE_EN__SHIFT__SI 0x0000001b -#define CG_GFXCLK_ON_OFF_RAMP__PULSE_HIGH_CNT__SHIFT__SI 0x00000000 -#define CG_GFXCLK_ON_OFF_RAMP__STEP_DELAY_CNT__SHIFT__SI 0x00000009 -#define CG_GFXCLK_ON_OFF_RAMP__STEP_UNIT__SHIFT__SI 0x00000017 -#define CG_GFX_IDLE_THRESHOLDS__CG_GFX_IDLE_CLK_STOP_THRESHOLD__SHIFT__SI 0x00000000 -#define CG_GFX_IDLE_THRESHOLDS__CG_GFX_IDLE_PWR_OFF_THRESHOLD__SHIFT__SI 0x00000010 -#define CG_IND_ADDR__CG_IND_ADDR__SHIFT__SI 0x00000000 -#define CG_IND_DATA__CG_IND_DATA__SHIFT__SI 0x00000000 -#define CG_INTERRUPT_STATUS__ACTIVITY_TRIGGER_MASK__SHIFT 0x00000008 -#define CG_INTERRUPT_STATUS__ACTIVITY_TRIGGER__SHIFT 0x00000002 -#define CG_INTERRUPT_STATUS__CTXSW_TRIGGER_MASK__SHIFT 0x00000007 -#define CG_INTERRUPT_STATUS__CTXSW_TRIGGER__SHIFT 0x00000001 -#define CG_INTERRUPT_STATUS__RESERVED_0__SHIFT__CI__VI 0x00000004 -#define CG_INTERRUPT_STATUS__RESERVED_1__SHIFT__CI__VI 0x0000000a -#define CG_INTERRUPT_STATUS__SMC_MSG_INT__SHIFT 0x0000000c -#define CG_INTERRUPT_STATUS__SMC_MSG_MASK__SHIFT 0x0000000d -#define CG_INTERRUPT_STATUS__SRBM_TRIGGER_MASK__SHIFT 0x0000000e -#define CG_INTERRUPT_STATUS__STATIC_SCREEN_DETECTION_MASK__SHIFT 0x00000009 -#define CG_INTERRUPT_STATUS__STATIC_SCREEN_DETECTION__SHIFT 0x00000003 -#define CG_INTERRUPT_STATUS__THERMAL_TRIGGER_MASK__SHIFT 0x00000006 -#define CG_INTERRUPT_STATUS__THERMAL_TRIGGER__SHIFT 0x00000000 -#define CG_LCLK_CNTL__LCLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_LCLK_CNTL__LCLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_LCLK_CNTL__LCLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_LCLK_CNTL__LCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_LCLK_STATUS__LCLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000001 -#define CG_LCLK_STATUS__LCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_MISC_REG_2__IH_MAX_CREDITS__SHIFT 0x00000000 -#define CG_MISC_REG__CLK_OBSRV_SEL1__SHIFT 0x00000000 -#define CG_MISC_REG__CLK_OBSRV_SEL2__SHIFT 0x00000008 -#define CG_MISC_REG__CLK_OBSRV_SEL_MODE__SHIFT__CI__VI 0x0000001b -#define CG_MISC_REG__SYNCHRONIZER_COUNTER__SHIFT 0x0000001c -#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT__SI__CI 0x00000014 -#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT__SI__CI 0x00000009 -#define CG_MULT_THERMAL_CTRL__TS_CLAMP__SHIFT__SI 0x00000008 -#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT__SI__CI 0x00000000 -#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT__SI__CI 0x00000004 -#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT__SI__CI 0x00000000 -#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT__SI__CI 0x00000009 -#define CG_PROG_CNTR_STATUS_REG__CYCLES_CNT__SHIFT__SI 0x00000000 -#define CG_PROG_CNTR_STATUS_REG__TIMES_CNT__SHIFT__SI 0x0000000e -#define CG_PROG_CNTR__CNTR_EN__SHIFT__SI 0x00000012 -#define CG_PROG_CNTR__DPM_STATE__SHIFT__SI 0x00000016 -#define CG_PROG_CNTR__PERIOD_CNT__SHIFT__SI 0x00000000 -#define CG_PROG_CNTR__STATE_SELECT__SHIFT__SI 0x00000013 -#define CG_PROG_CNTR__UNIT_CNT__SHIFT__SI 0x0000000e -#define CG_SAMCLK_CNTL__SAMCLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_SAMCLK_CNTL__SAMCLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_SAMCLK_CNTL__SAMCLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_SAMCLK_CNTL__SAMCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_SAMCLK_OVERCLOCKING_ATTEMPTS__EVCLK_ATTEMPTS__SHIFT__CI__VI 0x00000010 -#define CG_SAMCLK_OVERCLOCKING_ATTEMPTS__SAMCLK_ATTEMPTS__SHIFT__CI__VI 0x00000000 -#define CG_SAMCLK_STATUS__SAMCLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000001 -#define CG_SAMCLK_STATUS__SAMCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_SCLK_CNTL__SCLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_SCLK_CNTL__SCLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_SCLK_CNTL__SCLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_SCLK_CNTL__SCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_SCLK_LCLK_OVERCLOCKING_ATTEMPTS__LCLK_ATTEMPTS__SHIFT__CI__VI 0x00000010 -#define CG_SCLK_LCLK_OVERCLOCKING_ATTEMPTS__SCLK_ATTEMPTS__SHIFT__CI__VI 0x00000000 -#define CG_SCLK_STATUS__SCLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000003 -#define CG_SCLK_STATUS__SCLK_FORCE_STATUS__SHIFT__CI__VI 0x00000001 -#define CG_SCLK_STATUS__SCLK_OVERCLK_DETECT__SHIFT__CI__VI 0x00000002 -#define CG_SCLK_STATUS__SCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_IDLE_AUTOCLEAR__SHIFT__SI 0x00000011 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_IDLE_CLEAR__SHIFT__SI 0x00000012 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_IDLE__SHIFT__SI 0x00000010 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_OCP_AUTOCLEAR__SHIFT__SI 0x00000001 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_OCP_CLEAR__SHIFT__SI 0x00000002 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_OCP__SHIFT__SI 0x00000000 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_AUTOCLEAR__SHIFT__SI 0x00000009 -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR__SHIFT__SI 0x0000000a -#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS__SHIFT__SI 0x00000008 -#define CG_SPLL_AUTOSCALE_STATUS__AUTOSCALE_ON_IDLE_ACTIVE__SHIFT__SI 0x00000002 -#define CG_SPLL_AUTOSCALE_STATUS__AUTOSCALE_ON_OCP_ACTIVE__SHIFT__SI 0x00000000 -#define CG_SPLL_AUTOSCALE_STATUS__AUTOSCALE_ON_SS_ACTIVE__SHIFT__SI 0x00000001 -#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x00000000 -#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x0000001a -#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x00000019 -#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x0000001c -#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKR_UPDATE__SHIFT__SI__CI 0x0000001d -#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x00000017 -#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0x0000000b -#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x00000018 -#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x0000001b -#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x0000001c -#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000 -#define CG_SPLL_FUNC_CNTL_4__BG_PDN__SHIFT__SI__CI 0x00000016 -#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x00000018 -#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x00000017 -#define CG_SPLL_FUNC_CNTL_4__SPLL_REG_BIAS__SHIFT__SI__CI 0x00000012 -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x0000001a -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x00000000 -#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x0000001c -#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x00000019 -#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x0000001f -#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x00000015 -#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x00000006 -#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x00000008 -#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x00000000 -#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x00000002 -#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x00000009 -#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x00000004 -#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x00000001 -#define CG_SPLL_FUNC_CNTL_5__SCLK_DFS_BYPASS_EN__SHIFT__CI 0x0000000a -#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT__CI__VI 0x00000000 -#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT__CI__VI 0x00000008 -#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x00000003 -#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x00000002 -#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x00000000 -#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP__SHIFT__SI__CI 0x00000001 -#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x00000000 -#define CG_SPLL_SPREAD_SPECTRUM__BWADJ__SHIFT__SI__CI 0x00000010 -#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x00000004 -#define CG_SPLL_SPREAD_SPECTRUM__SPARE__SHIFT__SI__CI 0x00000002 -#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x00000000 -#define CG_SPLL_STATUS__GPLL_OPWRGOOD_ISO_ENB__SHIFT__CI__VI 0x00000016 -#define CG_SPLL_STATUS__GPLL_OPWRGOOD_S__SHIFT__CI__VI 0x00000015 -#define CG_SPLL_STATUS__GPLL_OPWRGOOD_V__SHIFT__CI__VI 0x00000014 -#define CG_SPLL_STATUS__SPLL_BABYSTEP_DONE__SHIFT 0x00000003 -#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x00000001 -#define CG_SPLL_STATUS__SPLL_CLKF_ACK__SHIFT 0x00000008 -#define CG_SPLL_STATUS__SPLL_CLKPB_ACK__SHIFT 0x0000000a -#define CG_SPLL_STATUS__SPLL_CLKR_ACK__SHIFT__SI__CI 0x00000009 -#define CG_SPLL_STATUS__SPLL_CTLACK__SHIFT 0x00000000 -#define CG_SPLL_STATUS__SPLL_INTRESET__SHIFT 0x0000000b -#define CG_SPLL_STATUS__SPLL_OSPARE__SHIFT 0x00000010 -#define CG_SPLL_STATUS__SPLL_STATE__SHIFT 0x00000004 -#define CG_SPLL_STATUS__SPLL_UNLOCK_STICKY__SHIFT 0x00000007 -#define CG_SPLL_STATUS__SPLL_UNLOCK__SHIFT 0x00000002 -#define CG_SPLL_STATUS__SPLL_VCTRLADC__SHIFT 0x0000000c -#define CG_SPMICLK_CNTL__SPMICLK_DIVIDER_EN__SHIFT__CI__VI 0x00000003 -#define CG_SPMICLK_CNTL__SPMICLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_STATIC_SCREEN_CTRL__ACP_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000007 -#define CG_STATIC_SCREEN_CTRL__AVP_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000000d -#define CG_STATIC_SCREEN_CTRL__BIF_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_STATIC_SCREEN_CTRL__DC_AZ_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000000b -#define CG_STATIC_SCREEN_CTRL__DRM_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_STATIC_SCREEN_CTRL__GRBM_0_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000000e -#define CG_STATIC_SCREEN_CTRL__GRBM_10_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000018 -#define CG_STATIC_SCREEN_CTRL__GRBM_11_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000019 -#define CG_STATIC_SCREEN_CTRL__GRBM_12_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000001a -#define CG_STATIC_SCREEN_CTRL__GRBM_13_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000001b -#define CG_STATIC_SCREEN_CTRL__GRBM_14_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000001c -#define CG_STATIC_SCREEN_CTRL__GRBM_15_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000001d -#define CG_STATIC_SCREEN_CTRL__GRBM_1_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000000f -#define CG_STATIC_SCREEN_CTRL__GRBM_2_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000010 -#define CG_STATIC_SCREEN_CTRL__GRBM_3_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000011 -#define CG_STATIC_SCREEN_CTRL__GRBM_4_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000012 -#define CG_STATIC_SCREEN_CTRL__GRBM_5_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000013 -#define CG_STATIC_SCREEN_CTRL__GRBM_6_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000014 -#define CG_STATIC_SCREEN_CTRL__GRBM_7_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000015 -#define CG_STATIC_SCREEN_CTRL__GRBM_8_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000016 -#define CG_STATIC_SCREEN_CTRL__GRBM_9_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000017 -#define CG_STATIC_SCREEN_CTRL__HDP_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_STATIC_SCREEN_CTRL__IDCT_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000006 -#define CG_STATIC_SCREEN_CTRL__IH_SEM_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_STATIC_SCREEN_CTRL__PDMA_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_STATIC_SCREEN_CTRL__RLC_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000001e -#define CG_STATIC_SCREEN_CTRL__ROM_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_STATIC_SCREEN_CTRL__SAM_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000000c -#define CG_STATIC_SCREEN_CTRL__SDMA_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000008 -#define CG_STATIC_SCREEN_CTRL__UVD_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x00000009 -#define CG_STATIC_SCREEN_CTRL__VCE_STATIC_SCREEN_VOTE_EN__SHIFT__CI__VI 0x0000000a -#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x00000010 -#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x00000000 -#define CG_SW_INT_CTXID__CTXID__SHIFT__SI 0x00000000 -#define CG_SW_INT__ID__SHIFT__SI 0x00000000 -#define CG_SW_INT__VALID__SHIFT__SI 0x00000008 -#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT__SI__CI 0x00000000 -#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT__SI__CI 0x00000003 -#define CG_TACH_STATUS__TACH_PERIOD__SHIFT__SI__CI 0x00000000 -#define CG_TARG_REF_CLK_CNTL__TARG_REF_CLK_DIVIDER_EN__SHIFT__CI__VI 0x00000003 -#define CG_TARG_REF_CLK_CNTL__TARG_REF_CLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT__SI__CI 0x0000001a -#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT__SI__CI 0x00000019 -#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT__SI__CI 0x0000000e -#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT__SI__CI 0x00000000 -#define CG_THERMAL_CTRL__RESERVED__SHIFT__SI__CI 0x00000016 -#define CG_THERMAL_CTRL__SPARE__SHIFT__SI__CI 0x00000004 -#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT__SI__CI 0x00000003 -#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT__CI__VI 0x00000000 -#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT__CI__VI 0x00000008 -#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT__CI__VI 0x00000010 -#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT__CI__VI 0x0000001c -#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT__CI__VI 0x00000018 -#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT__CI__VI 0x00000019 -#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT__CI__VI 0x0000001b -#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT__CI__VI 0x0000001a -#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT__CI__VI 0x00000003 -#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT__CI__VI 0x00000000 -#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT__CI__VI 0x00000004 -#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT__CI__VI 0x00000001 -#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT__CI__VI 0x00000005 -#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT__CI__VI 0x00000002 -#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT__CI__VI 0x00000000 -#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT__CI__VI 0x00000001 -#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT__CI__VI 0x00000003 -#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT__CI__VI 0x00000002 -#define CG_THERMAL_INT__CTF_DELAY__SHIFT__SI 0x0000001c -#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT__SI__CI 0x00000000 -#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT__SI__CI 0x00000008 -#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT__SI__CI 0x00000010 -#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT__SI__CI 0x00000018 -#define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT__SI__CI 0x00000000 -#define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT__SI__CI 0x00000010 -#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT__SI__CI 0x00000009 -#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT__SI__CI 0x00000012 -#define CG_THERMAL_STATUS__SPARE__SHIFT__SI__CI 0x00000000 -#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT__SI__CI 0x00000011 -#define CG_TIMESTAMP_HIGH__CG_HIGH__SHIFT__SI 0x00000000 -#define CG_TIMESTAMP_LOW__CG_LOW__SHIFT__SI 0x00000000 -#define CG_ULV_CONTROL__BIF_ULV_VOTE_EN__SHIFT__SI 0x00000005 -#define CG_ULV_CONTROL__DRMDMA_ULV_VOTE_EN__SHIFT__SI 0x0000000c -#define CG_ULV_CONTROL__DRM_ULV_VOTE_EN__SHIFT__SI 0x0000000a -#define CG_ULV_CONTROL__FORCE_ULV_INTERRUPT__SHIFT 0x0000001e -#define CG_ULV_CONTROL__GFXCLK_GATING_STATUS__SHIFT__CI__VI 0x00000016 -#define CG_ULV_CONTROL__GFXCLK_RECHK_WAIT__SHIFT__CI__VI 0x00000018 -#define CG_ULV_CONTROL__GFX_ULV_VOTE_EN__SHIFT__SI 0x00000004 -#define CG_ULV_CONTROL__HDP_ULV_VOTE_EN__SHIFT__SI 0x00000006 -#define CG_ULV_CONTROL__HW_ULV_DETECT__SHIFT 0x00000017 -#define CG_ULV_CONTROL__IDCT_ULV_VOTE_EN__SHIFT__SI 0x0000000b -#define CG_ULV_CONTROL__IH_SEM_ULV_VOTE_EN__SHIFT__SI 0x00000008 -#define CG_ULV_CONTROL__INHIBIT_GFXCLK_STATUS__SHIFT__CI__VI 0x00000015 -#define CG_ULV_CONTROL__PDMA_ULV_VOTE_EN__SHIFT__SI 0x00000009 -#define CG_ULV_CONTROL__ROM_ULV_VOTE_EN__SHIFT__SI 0x00000007 -#define CG_ULV_CONTROL__SMC_ULV_STATE__SHIFT 0x0000001f -#define CG_ULV_CONTROL__ULV_EN__SHIFT 0x00000000 -#define CG_ULV_CONTROL__UVD_ULV_VOTE_EN__SHIFT__SI 0x0000000d -#define CG_ULV_CONTROL__VCE_ULV_VOTE_EN__SHIFT__SI 0x0000000e -#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x00000010 -#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x00000000 -#define CG_ULV_VOTING__ACP_ULV_VOTE_EN__SHIFT__CI 0x00000007 -#define CG_ULV_VOTING__AVP_ULV_VOTE_EN__SHIFT__CI 0x0000000d -#define CG_ULV_VOTING__BIF_ULV_VOTE_EN__SHIFT__CI__VI 0x00000000 -#define CG_ULV_VOTING__DC_AZ_ULV_VOTE_EN__SHIFT__CI 0x0000000b -#define CG_ULV_VOTING__DRM_ULV_VOTE_EN__SHIFT__CI__VI 0x00000005 -#define CG_ULV_VOTING__GRBM_0_ULV_VOTE_EN__SHIFT__CI 0x0000000e -#define CG_ULV_VOTING__GRBM_10_ULV_VOTE_EN__SHIFT__CI 0x00000018 -#define CG_ULV_VOTING__GRBM_11_ULV_VOTE_EN__SHIFT__CI 0x00000019 -#define CG_ULV_VOTING__GRBM_12_ULV_VOTE_EN__SHIFT__CI 0x0000001a -#define CG_ULV_VOTING__GRBM_13_ULV_VOTE_EN__SHIFT__CI 0x0000001b -#define CG_ULV_VOTING__GRBM_14_ULV_VOTE_EN__SHIFT__CI 0x0000001c -#define CG_ULV_VOTING__GRBM_15_ULV_VOTE_EN__SHIFT__CI 0x0000001d -#define CG_ULV_VOTING__GRBM_1_ULV_VOTE_EN__SHIFT__CI 0x0000000f -#define CG_ULV_VOTING__GRBM_2_ULV_VOTE_EN__SHIFT__CI 0x00000010 -#define CG_ULV_VOTING__GRBM_3_ULV_VOTE_EN__SHIFT__CI 0x00000011 -#define CG_ULV_VOTING__GRBM_4_ULV_VOTE_EN__SHIFT__CI 0x00000012 -#define CG_ULV_VOTING__GRBM_5_ULV_VOTE_EN__SHIFT__CI 0x00000013 -#define CG_ULV_VOTING__GRBM_6_ULV_VOTE_EN__SHIFT__CI 0x00000014 -#define CG_ULV_VOTING__GRBM_7_ULV_VOTE_EN__SHIFT__CI 0x00000015 -#define CG_ULV_VOTING__GRBM_8_ULV_VOTE_EN__SHIFT__CI 0x00000016 -#define CG_ULV_VOTING__GRBM_9_ULV_VOTE_EN__SHIFT__CI 0x00000017 -#define CG_ULV_VOTING__HDP_ULV_VOTE_EN__SHIFT__CI__VI 0x00000001 -#define CG_ULV_VOTING__IDCT_ULV_VOTE_EN__SHIFT__CI 0x00000006 -#define CG_ULV_VOTING__IH_SEM_ULV_VOTE_EN__SHIFT__CI__VI 0x00000003 -#define CG_ULV_VOTING__PDMA_ULV_VOTE_EN__SHIFT__CI__VI 0x00000004 -#define CG_ULV_VOTING__RLC_ULV_VOTE_EN__SHIFT__CI 0x0000001e -#define CG_ULV_VOTING__ROM_ULV_VOTE_EN__SHIFT__CI__VI 0x00000002 -#define CG_ULV_VOTING__SAM_ULV_VOTE_EN__SHIFT__CI 0x0000000c -#define CG_ULV_VOTING__SDMA_ULV_VOTE_EN__SHIFT__CI 0x00000008 -#define CG_ULV_VOTING__UVD_ULV_VOTE_EN__SHIFT__CI 0x00000009 -#define CG_ULV_VOTING__VCE_ULV_VOTE_EN__SHIFT__CI 0x0000000a -#define CG_UPLL_FUNC_CNTL_2__DCLK_SRC_SEL__SHIFT__SI 0x00000019 -#define CG_UPLL_FUNC_CNTL_2__UPLL_ENSAT__SHIFT__SI 0x00000013 -#define CG_UPLL_FUNC_CNTL_2__UPLL_FASTEN__SHIFT__SI 0x00000012 -#define CG_UPLL_FUNC_CNTL_2__UPLL_LEGACY_PDIV__SHIFT__SI 0x00000011 -#define CG_UPLL_FUNC_CNTL_2__UPLL_PDIV_A__SHIFT__SI 0x00000000 -#define CG_UPLL_FUNC_CNTL_2__UPLL_PDIV_B__SHIFT__SI 0x00000008 -#define CG_UPLL_FUNC_CNTL_2__UPLL_TEST__SHIFT__SI 0x0000001e -#define CG_UPLL_FUNC_CNTL_2__UPLL_UNLOCK_CLEAR__SHIFT__SI 0x0000001f -#define CG_UPLL_FUNC_CNTL_2__VCLK_SRC_SEL__SHIFT__SI 0x00000014 -#define CG_UPLL_FUNC_CNTL_3__UPLL_DITHEN__SHIFT__SI 0x0000001c -#define CG_UPLL_FUNC_CNTL_3__UPLL_FB_DIV__SHIFT__SI 0x00000000 -#define CG_UPLL_FUNC_CNTL_4__BG_PDN__SHIFT__SI 0x00000016 -#define CG_UPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT__SI 0x00000015 -#define CG_UPLL_FUNC_CNTL_4__UPLL_FBCLK_SEL__SHIFT__SI 0x00000018 -#define CG_UPLL_FUNC_CNTL_4__UPLL_ILOCK__SHIFT__SI 0x00000017 -#define CG_UPLL_FUNC_CNTL_4__UPLL_REG_BIAS__SHIFT__SI 0x00000012 -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_EN__SHIFT__SI 0x00000006 -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_EXT_SEL__SHIFT__SI 0x00000004 -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_EXT__SHIFT__SI 0x0000001a -#define CG_UPLL_FUNC_CNTL_4__UPLL_SCLK_TEST_SEL__SHIFT__SI 0x00000000 -#define CG_UPLL_FUNC_CNTL_4__UPLL_SPARE_EXT__SHIFT__SI 0x0000001c -#define CG_UPLL_FUNC_CNTL_4__UPLL_SPARE__SHIFT__SI 0x00000008 -#define CG_UPLL_FUNC_CNTL_4__UPLL_VCTRLADC_EN__SHIFT__SI 0x00000019 -#define CG_UPLL_FUNC_CNTL_4__UPLL_VTOI_BIAS_CNTL__SHIFT__SI 0x0000001f -#define CG_UPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT__SI 0x00000006 -#define CG_UPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT__SI 0x00000008 -#define CG_UPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT__SI 0x00000000 -#define CG_UPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT__SI 0x00000002 -#define CG_UPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT__SI 0x00000009 -#define CG_UPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT__SI 0x00000004 -#define CG_UPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT__SI 0x00000001 -#define CG_UPLL_FUNC_CNTL__UPLL_BYPASS_EN__SHIFT__SI 0x00000002 -#define CG_UPLL_FUNC_CNTL__UPLL_CLKF_UPDATE__SHIFT__SI 0x00000006 -#define CG_UPLL_FUNC_CNTL__UPLL_CLKR_UPDATE__SHIFT__SI 0x00000007 -#define CG_UPLL_FUNC_CNTL__UPLL_CTLACK2__SHIFT__SI 0x0000001f -#define CG_UPLL_FUNC_CNTL__UPLL_CTLACK__SHIFT__SI 0x0000001e -#define CG_UPLL_FUNC_CNTL__UPLL_CTLREQ__SHIFT__SI 0x00000003 -#define CG_UPLL_FUNC_CNTL__UPLL_REFCLK_SEL__SHIFT__SI 0x00000004 -#define CG_UPLL_FUNC_CNTL__UPLL_REF_DIV__SHIFT__SI 0x00000010 -#define CG_UPLL_FUNC_CNTL__UPLL_RESET_EN__SHIFT__SI 0x00000008 -#define CG_UPLL_FUNC_CNTL__UPLL_RESET__SHIFT__SI 0x00000000 -#define CG_UPLL_FUNC_CNTL__UPLL_SLEEP__SHIFT__SI 0x00000001 -#define CG_UPLL_FUNC_CNTL__UPLL_VCO_MODE__SHIFT__SI 0x00000009 -#define CG_UPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT__SI 0x00000000 -#define CG_UPLL_SPREAD_SPECTRUM__BWADJ__SHIFT__SI 0x00000010 -#define CG_UPLL_SPREAD_SPECTRUM__CLKS__SHIFT__SI 0x00000004 -#define CG_UPLL_SPREAD_SPECTRUM__SPARE__SHIFT__SI 0x00000002 -#define CG_UPLL_SPREAD_SPECTRUM__SSEN__SHIFT__SI 0x00000000 -#define CG_UPLL_STATUS__UPLL_CLKF_ACK__SHIFT__SI 0x00000002 -#define CG_UPLL_STATUS__UPLL_CLKR_ACK__SHIFT__SI 0x00000003 -#define CG_UPLL_STATUS__UPLL_CTLACK_A__SHIFT__SI 0x00000000 -#define CG_UPLL_STATUS__UPLL_CTLACK_B__SHIFT__SI 0x00000001 -#define CG_UPLL_STATUS__UPLL_INTRESET__SHIFT__SI 0x0000000c -#define CG_UPLL_STATUS__UPLL_OSPARE__SHIFT__SI 0x00000008 -#define CG_UPLL_STATUS__UPLL_UNLOCK_STICKY__SHIFT__SI 0x00000011 -#define CG_UPLL_STATUS__UPLL_UNLOCK__SHIFT__SI 0x00000010 -#define CG_UPLL_STATUS__UPLL_VCTRLADC__SHIFT__SI 0x00000004 -#define CG_VCEPLL_FUNC_CNTL_2__ECCLK_SRC_SEL__SHIFT__SI 0x00000019 -#define CG_VCEPLL_FUNC_CNTL_2__EVCLK_SRC_SEL__SHIFT__SI 0x00000014 -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_ENSAT__SHIFT__SI 0x00000013 -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_FASTEN__SHIFT__SI 0x00000012 -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_LEGACY_PDIV__SHIFT__SI 0x00000011 -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_A__SHIFT__SI 0x00000000 -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_B__SHIFT__SI 0x00000008 -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_TEST__SHIFT__SI 0x0000001e -#define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_UNLOCK_CLEAR__SHIFT__SI 0x0000001f -#define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_DITHEN__SHIFT__SI 0x0000001c -#define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_FB_DIV__SHIFT__SI 0x00000000 -#define CG_VCEPLL_FUNC_CNTL_4__BG_PDN__SHIFT__SI 0x00000016 -#define CG_VCEPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT__SI 0x00000015 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_FBCLK_SEL__SHIFT__SI 0x00000018 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_ILOCK__SHIFT__SI 0x00000017 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_REG_BIAS__SHIFT__SI 0x00000012 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EN__SHIFT__SI 0x00000006 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT_SEL__SHIFT__SI 0x00000004 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT__SHIFT__SI 0x0000001a -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_TEST_SEL__SHIFT__SI 0x00000000 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE_EXT__SHIFT__SI 0x0000001c -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE__SHIFT__SI 0x00000008 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VCTRLADC_EN__SHIFT__SI 0x00000019 -#define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VTOI_BIAS_CNTL__SHIFT__SI 0x0000001f -#define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT__SI 0x00000006 -#define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT__SI 0x00000008 -#define CG_VCEPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT__SI 0x00000000 -#define CG_VCEPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT__SI 0x00000002 -#define CG_VCEPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT__SI 0x00000009 -#define CG_VCEPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT__SI 0x00000004 -#define CG_VCEPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT__SI 0x00000001 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_BYPASS_EN__SHIFT__SI 0x00000002 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKF_UPDATE__SHIFT__SI 0x00000006 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKR_UPDATE__SHIFT__SI 0x00000007 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK2__SHIFT__SI 0x0000001f -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK__SHIFT__SI 0x0000001e -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLREQ__SHIFT__SI 0x00000003 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_REFCLK_SEL__SHIFT__SI 0x00000004 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_REF_DIV__SHIFT__SI 0x00000010 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET_EN__SHIFT__SI 0x00000008 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET__SHIFT__SI 0x00000000 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_SLEEP__SHIFT__SI 0x00000001 -#define CG_VCEPLL_FUNC_CNTL__VCEPLL_VCO_MODE__SHIFT__SI 0x00000009 -#define CG_VCEPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT__SI 0x00000000 -#define CG_VCEPLL_SPREAD_SPECTRUM__BWADJ__SHIFT__SI 0x00000010 -#define CG_VCEPLL_SPREAD_SPECTRUM__CLKS__SHIFT__SI 0x00000004 -#define CG_VCEPLL_SPREAD_SPECTRUM__SPARE__SHIFT__SI 0x00000002 -#define CG_VCEPLL_SPREAD_SPECTRUM__SSEN__SHIFT__SI 0x00000000 -#define CG_VCEPLL_STATUS__VCEPLL_CLKF_ACK__SHIFT__SI 0x00000002 -#define CG_VCEPLL_STATUS__VCEPLL_CLKR_ACK__SHIFT__SI 0x00000003 -#define CG_VCEPLL_STATUS__VCEPLL_CTLACK_A__SHIFT__SI 0x00000000 -#define CG_VCEPLL_STATUS__VCEPLL_CTLACK_B__SHIFT__SI 0x00000001 -#define CG_VCEPLL_STATUS__VCEPLL_INTRESET__SHIFT__SI 0x0000000c -#define CG_VCEPLL_STATUS__VCEPLL_OSPARE__SHIFT__SI 0x00000008 -#define CG_VCEPLL_STATUS__VCEPLL_UNLOCK_STICKY__SHIFT__SI 0x00000011 -#define CG_VCEPLL_STATUS__VCEPLL_UNLOCK__SHIFT__SI 0x00000010 -#define CG_VCEPLL_STATUS__VCEPLL_VCTRLADC__SHIFT__SI 0x00000004 -#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT__CI__VI 0x0000000a -#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT__CI__VI 0x00000008 -#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT__CI__VI 0x00000009 -#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define CG_VCLK_DCLK_OVERCLOCKING_ATTEMPTS__DCLK_ATTEMPTS__SHIFT__CI__VI 0x00000010 -#define CG_VCLK_DCLK_OVERCLOCKING_ATTEMPTS__VCLK_ATTEMPTS__SHIFT__CI__VI 0x00000000 -#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT__CI__VI 0x00000001 -#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define CG_WRM_RST_CNTL__CNT__SHIFT__CI__VI 0x00000000 -#define CHROMA_BOT_ADDR__UV_BOT_BASE__SHIFT__SI 0x00000000 -#define CHROMA_TOP_ADDR__UV_TOP_BASE__SHIFT__SI 0x00000000 -#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define CLIENT0_BM__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CD0__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CD1__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CD2__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CD3__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CK0__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CK1__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CK2__RESERVED__SHIFT 0x00000000 -#define CLIENT0_CK3__RESERVED__SHIFT 0x00000000 -#define CLIENT0_K0__RESERVED__SHIFT 0x00000000 -#define CLIENT0_K1__RESERVED__SHIFT 0x00000000 -#define CLIENT0_K2__RESERVED__SHIFT 0x00000000 -#define CLIENT0_K3__RESERVED__SHIFT 0x00000000 -#define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000 -#define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000 -#define CLIENT1_BM__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CD0__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CD1__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CD2__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CD3__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CK0__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CK1__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CK2__RESERVED__SHIFT 0x00000000 -#define CLIENT1_CK3__RESERVED__SHIFT 0x00000000 -#define CLIENT1_K0__RESERVED__SHIFT 0x00000000 -#define CLIENT1_K1__RESERVED__SHIFT 0x00000000 -#define CLIENT1_K2__RESERVED__SHIFT 0x00000000 -#define CLIENT1_K3__RESERVED__SHIFT 0x00000000 -#define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000 -#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000 -#define CLIENT2_BM__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CD0__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CD1__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CD2__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CD3__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CK0__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CK1__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CK2__RESERVED__SHIFT 0x00000000 -#define CLIENT2_CK3__RESERVED__SHIFT 0x00000000 -#define CLIENT2_K0__RESERVED__SHIFT 0x00000000 -#define CLIENT2_K1__RESERVED__SHIFT 0x00000000 -#define CLIENT2_K2__RESERVED__SHIFT 0x00000000 -#define CLIENT2_K3__RESERVED__SHIFT 0x00000000 -#define CLIENT2_OFFSET__RESERVED__SHIFT 0x00000000 -#define CLIENT2_STATUS__RESERVED__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009 -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003 -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002 -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005 -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f -#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005 -#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003 -#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004 -#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f -#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT__CI__VI 0x00000000 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT__CI__VI 0x0000000c -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT__CI__VI 0x00000002 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT__CI__VI 0x0000000b -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT__CI__VI 0x00000001 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT__CI__VI 0x00000009 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT__CI__VI 0x00000005 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT__CI__VI 0x00000006 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT__CI__VI 0x00000007 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT__CI__VI 0x00000008 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT__CI__VI 0x00000003 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT__CI__VI 0x0000000a -#define CLOCK_POWER_CONTROL_5__Nb_Load_Line_Trim__SHIFT__CI__VI 0x00000002 -#define CLOCK_POWER_CONTROL_5__Nb_Offset_Trim__SHIFT__CI__VI 0x00000000 -#define CLOCK_POWER_CONTROL_5__Nb_Psi1__SHIFT__CI__VI 0x00000005 -#define CLOCK_POWER_CONTROL_5__Nb_Tfn__SHIFT__CI__VI 0x00000006 -#define CLOCK_POWER_CONTROL_5__RESERVED__SHIFT__CI__VI 0x00000007 -#define CMON_REGION_LOWER__CMON_REGION_31_0__SHIFT__SI__CI 0x00000000 -#define CMON_REGION_UPPER__CMON_REGION_40_32__SHIFT__SI__CI 0x00000000 -#define CMON_REG__ADC_DOUT__SHIFT__SI 0x00000014 -#define CMON_REG__ADC_MAX__SHIFT__SI 0x00000000 -#define CMON_REG__ADC_MIN__SHIFT__SI 0x0000000a -#define CM_ARB_READ_CTL__ARB_TYPE__SHIFT__SI 0x00000000 -#define CM_ARB_READ_CTL__MAX_REQ__SHIFT__SI 0x00000009 -#define CM_ARB_READ_CTL__PRIORITY_ONE__SHIFT__SI 0x00000003 -#define CM_ARB_READ_CTL__PRIORITY_THREE__SHIFT__SI 0x00000007 -#define CM_ARB_READ_CTL__PRIORITY_TWO__SHIFT__SI 0x00000005 -#define CM_ARB_READ_CTL__PRIORITY_ZERO__SHIFT__SI 0x00000001 -#define CM_ARB_WRITE_CTL__ARB_TYPE__SHIFT__SI 0x00000000 -#define CM_ARB_WRITE_CTL__PRIORITY_ONE__SHIFT__SI 0x00000003 -#define CM_ARB_WRITE_CTL__PRIORITY_TWO__SHIFT__SI 0x00000005 -#define CM_ARB_WRITE_CTL__PRIORITY_ZERO__SHIFT__SI 0x00000001 -#define CM_BITPLANE_MODE__CM_BITPLANE_COLSKIP__SHIFT__SI 0x00000001 -#define CM_BITPLANE_MODE__CM_BITPLANE_MODE__SHIFT__SI 0x00000000 -#define CM_BLK_STAT__DB_READ__SHIFT__SI 0x00000018 -#define CM_BLK_STAT__IT_DONE__SHIFT__SI 0x00000008 -#define CM_BLK_STAT__MP_DONE__SHIFT__SI 0x00000010 -#define CM_BLK_STAT__RE_DONE__SHIFT__SI 0x00000000 -#define CM_BUF_EMPTY__COLOC_BUF_EMPTY__SHIFT__SI 0x00000010 -#define CM_BUF_EMPTY__CURRENT_BUF_EMPTY__SHIFT__SI 0x00000000 -#define CM_BUF_EMPTY__TOP_BUF_EMPTY__SHIFT__SI 0x00000008 -#define CM_COLOC_ADR__COLOC_ADR__SHIFT__SI 0x00000006 -#define CM_COLOC_LOC__COLOC_MB_NR_ONE__SHIFT__SI 0x0000000e -#define CM_COLOC_LOC__COLOC_MB_NR_ZERO__SHIFT__SI 0x00000000 -#define CM_COLOC_SCAN_INFO__CURRENT_MB_NR__SHIFT__SI 0x00000010 -#define CM_COLOC_SCAN_INFO__MB_X__SHIFT__SI 0x00000000 -#define CM_COLOC_SCAN_INFO__MB_Y__SHIFT__SI 0x00000008 -#define CM_COLOC_STAT__COLOC_STAT__SHIFT__SI 0x00000000 -#define CM_CTL__CTXT_FMT__SHIFT__SI 0x00000006 -#define CM_CTL__MEM_TIMEOUT_TIME__SHIFT__SI 0x00000014 -#define CM_CTL__NSG_MODE__SHIFT__SI 0x00000004 -#define CM_CTL__STANDARD__SHIFT__SI 0x00000000 -#define CM_CTL__STD_VERSION__SHIFT__SI 0x00000008 -#define CM_CTL__SW_MRST__SHIFT__SI 0x0000001e -#define CM_CTL__SW_RRST__SHIFT__SI 0x0000001d -#define CM_CTL__SW_SRST__SHIFT__SI 0x0000001f -#define CM_CTXT_ADR__CTXT_ADR__SHIFT__SI 0x00000006 -#define CM_CTXT_FMO_MBNR__MB_NR__SHIFT__SI 0x00000000 -#define CM_CTXT_TOP_FMO__D_OR_B__SHIFT__SI 0x0000000f -#define CM_CTXT_TOP_FMO__MB_NR__SHIFT__SI 0x00000000 -#define CM_CTXT_TOP_PREFETCH__NUM_TOP_PREFETCH__SHIFT__SI 0x00000000 -#define CM_CURRENT_STAT__CURRENT_NOT_COMMIT__SHIFT__SI 0x00000000 -#define CM_CURRENT_STAT__CURRENT_STAT__SHIFT__SI 0x00000008 -#define CM_DEBUG_INT_STAT__BITPLANE_ERR__SHIFT__SI 0x00000009 -#define CM_DEBUG_INT_STAT__BOGUS_ADDRESS__SHIFT__SI 0x00000004 -#define CM_DEBUG_INT_STAT__BUFNUM_ERR__SHIFT__SI 0x00000003 -#define CM_DEBUG_INT_STAT__DONE__SHIFT__SI 0x00000000 -#define CM_DEBUG_INT_STAT__MEM_RD_FIFO_OVERFLOW__SHIFT__SI 0x00000006 -#define CM_DEBUG_INT_STAT__MEM_RD_FIFO_UNDERFLOW__SHIFT__SI 0x00000005 -#define CM_DEBUG_INT_STAT__MEM_RD_TIMEOUT__SHIFT__SI 0x00000001 -#define CM_DEBUG_INT_STAT__MEM_WR_FIFO_OVERFLOW__SHIFT__SI 0x00000008 -#define CM_DEBUG_INT_STAT__MEM_WR_FIFO_UNDERFLOW__SHIFT__SI 0x00000007 -#define CM_DEBUG_INT_STAT__MEM_WR_TIMEOUT__SHIFT__SI 0x00000002 -#define CM_FW_ADR__ADR__SHIFT__SI 0x00000000 -#define CM_FW_CTL__ACCESS_MODE__SHIFT__SI 0x00000000 -#define CM_FW_CTL__AUTO_INC__SHIFT__SI 0x00000001 -#define CM_FW_LOWER_DAT__DAT__SHIFT__SI 0x00000000 -#define CM_FW_UPPER_DAT__DAT__SHIFT__SI 0x00000000 -#define CM_HW_DEBUG__DAT__SHIFT__SI 0x00000000 -#define CM_INIT_TOP_BUF_NUM__TOP_BUF_NUM__SHIFT__SI 0x00000000 -#define CM_INT_EN__BITPLANE_ERR__SHIFT__SI 0x00000009 -#define CM_INT_EN__BOGUS_ADDRESS__SHIFT__SI 0x00000004 -#define CM_INT_EN__BUFNUM_ERR__SHIFT__SI 0x00000003 -#define CM_INT_EN__DONE_EN__SHIFT__SI 0x00000000 -#define CM_INT_EN__MEM_RD_FIFO_OVERFLOW__SHIFT__SI 0x00000006 -#define CM_INT_EN__MEM_RD_FIFO_UNDERFLOW__SHIFT__SI 0x00000005 -#define CM_INT_EN__MEM_RD_TIMEOUT__SHIFT__SI 0x00000001 -#define CM_INT_EN__MEM_WR_FIFO_OVERFLOW__SHIFT__SI 0x00000008 -#define CM_INT_EN__MEM_WR_FIFO_UNDERFLOW__SHIFT__SI 0x00000007 -#define CM_INT_EN__MEM_WR_TIMEOUT__SHIFT__SI 0x00000002 -#define CM_INT_STAT__BITPLANE_ERR__SHIFT__SI 0x00000009 -#define CM_INT_STAT__BOGUS_ADDRESS__SHIFT__SI 0x00000004 -#define CM_INT_STAT__BUFNUM_ERR__SHIFT__SI 0x00000003 -#define CM_INT_STAT__DONE__SHIFT__SI 0x00000000 -#define CM_INT_STAT__MEM_RD_FIFO_OVERFLOW__SHIFT__SI 0x00000006 -#define CM_INT_STAT__MEM_RD_FIFO_UNDERFLOW__SHIFT__SI 0x00000005 -#define CM_INT_STAT__MEM_RD_TIMEOUT__SHIFT__SI 0x00000001 -#define CM_INT_STAT__MEM_WR_FIFO_OVERFLOW__SHIFT__SI 0x00000008 -#define CM_INT_STAT__MEM_WR_FIFO_UNDERFLOW__SHIFT__SI 0x00000007 -#define CM_INT_STAT__MEM_WR_TIMEOUT__SHIFT__SI 0x00000002 -#define CM_LMA_ADR__ADR__SHIFT__SI 0x00000000 -#define CM_LMA_CTL__ACCESS_MODE__SHIFT__SI 0x00000000 -#define CM_LMA_CTL__AUTO_INC__SHIFT__SI 0x00000006 -#define CM_LMA_CTL__LMA_DEBUG__SHIFT__SI 0x00000007 -#define CM_LMA_CTL__MEMORY_SELECT__SHIFT__SI 0x00000001 -#define CM_LMA_DAT__DAT__SHIFT__SI 0x00000000 -#define CM_QWORD8_BOTTOM__QWORD8_BOTTOM__SHIFT__SI 0x00000000 -#define CM_QWORD8_TOP__QWORD8_TOP__SHIFT__SI 0x00000000 -#define CM_RELEASE__CURR_BUF_NUM__SHIFT__SI 0x00000000 -#define CM_SLICE_INFO__COLOC_CFG__SHIFT__SI 0x00000001 -#define CM_SLICE_INFO__MBAFF_FRAME_FLAG__SHIFT__SI 0x00000000 -#define CM_SPS_INFO__PIC_HEIGHT__SHIFT__SI 0x00000008 -#define CM_SPS_INFO__PIC_SIZE__SHIFT__SI 0x00000010 -#define CM_SPS_INFO__PIC_WIDTH__SHIFT__SI 0x00000000 -#define CM_SRAM_RM_CTL__CM_M328X064H1M04S00_RME__SHIFT__SI 0x00000004 -#define CM_SRAM_RM_CTL__CM_M328X064H1M04S00_RM__SHIFT__SI 0x00000000 -#define CM_STAT__READING_CTXT_BUSY__SHIFT__SI 0x00000001 -#define CM_STAT__WRITING_CTXT_BUSY__SHIFT__SI 0x00000000 -#define CM_TOP_STAT__TOP_STAT__SHIFT__SI 0x00000000 -#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT__CI__VI 0x00000004 -#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT__CI__VI 0x00000003 -#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT__CI__VI 0x00000000 -#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT__CI__VI 0x00000002 -#define CNB_PWRMGT_CNTL__SPARE__SHIFT__CI__VI 0x00000005 -#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000 -#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000 -#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000 -#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000 -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT__CI__VI 0x00000000 -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT__CI__VI 0x00000000 -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT__CI__VI 0x00000000 -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT__CI__VI 0x00000000 -#define COLOR_MATRIX_COEF_1_1__COLOR_MATRIX_COEF_1_1__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_1_1__COLOR_MATRIX_SIGN_1_1__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_1_2__COLOR_MATRIX_COEF_1_2__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_1_2__COLOR_MATRIX_SIGN_1_2__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_1_3__COLOR_MATRIX_COEF_1_3__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_1_3__COLOR_MATRIX_SIGN_1_3__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_1_4__COLOR_MATRIX_COEF_1_4__SHIFT__SI 0x00000008 -#define COLOR_MATRIX_COEF_1_4__COLOR_MATRIX_SIGN_1_4__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_2_1__COLOR_MATRIX_COEF_2_1__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_2_1__COLOR_MATRIX_SIGN_2_1__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_2_2__COLOR_MATRIX_COEF_2_2__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_2_2__COLOR_MATRIX_SIGN_2_2__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_2_3__COLOR_MATRIX_COEF_2_3__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_2_3__COLOR_MATRIX_SIGN_2_3__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_2_4__COLOR_MATRIX_COEF_2_4__SHIFT__SI 0x00000008 -#define COLOR_MATRIX_COEF_2_4__COLOR_MATRIX_SIGN_2_4__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_3_1__COLOR_MATRIX_COEF_3_1__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_3_1__COLOR_MATRIX_SIGN_3_1__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_3_2__COLOR_MATRIX_COEF_3_2__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_3_2__COLOR_MATRIX_SIGN_3_2__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_3_3__COLOR_MATRIX_COEF_3_3__SHIFT__SI 0x00000000 -#define COLOR_MATRIX_COEF_3_3__COLOR_MATRIX_SIGN_3_3__SHIFT__SI 0x0000001f -#define COLOR_MATRIX_COEF_3_4__COLOR_MATRIX_COEF_3_4__SHIFT__SI 0x00000008 -#define COLOR_MATRIX_COEF_3_4__COLOR_MATRIX_SIGN_3_4__SHIFT__SI 0x0000001f -#define COLOR_SPACE_CONVERT__COLOR_SUBSAMPLE_CRCB_MODE__SHIFT__SI 0x00000000 -#define COMMAND__AD_STEPPING__SHIFT 0x00000007 -#define COMMAND__BUS_MASTER_EN__SHIFT 0x00000002 -#define COMMAND__FAST_B2B_EN__SHIFT 0x00000009 -#define COMMAND__INT_DIS__SHIFT 0x0000000a -#define COMMAND__IO_ACCESS_EN__SHIFT 0x00000000 -#define COMMAND__MEM_ACCESS_EN__SHIFT 0x00000001 -#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x00000004 -#define COMMAND__PAL_SNOOP_EN__SHIFT 0x00000005 -#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x00000006 -#define COMMAND__SERR_EN__SHIFT 0x00000008 -#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x00000003 -#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000 -#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000 -#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000 -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000 -#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT__CI__VI 0x0000000c -#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT__CI__VI 0x00000007 -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT__CI__VI 0x00000004 -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT__CI__VI 0x00000006 -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001 -#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT__CI__VI 0x0000000e -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT__CI__VI 0x0000000a -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT__CI__VI 0x00000005 -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT__CI__VI 0x0000000b -#define COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT__SI 0x00000000 -#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT__CI__VI 0x00000002 -#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT__CI__VI 0x00000003 -#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT__CI__VI 0x00000004 -#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT__CI__VI 0x00000000 -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000 -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010 -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000 -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010 -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000 -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010 -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT__CI__VI 0x00000000 -#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000 -#define COMPUTE_PGM_HI__INST_ATC__SHIFT__CI__VI 0x00000008 -#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000 -#define COMPUTE_PGM_RSRC1__BULKY__SHIFT__CI__VI 0x00000018 -#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT__CI__VI 0x00000019 -#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016 -#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015 -#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c -#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017 -#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a -#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014 -#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006 -#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000 -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT__CI__VI 0x0000000d -#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018 -#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f -#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000 -#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007 -#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008 -#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009 -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006 -#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001 -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT__CI__VI 0x00000000 -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT__CI__VI 0x00000018 -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT__CI__VI 0x00000017 -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010 -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016 -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000 -#define COMPUTE_RESTART_X__RESTART__SHIFT__CI__VI 0x00000000 -#define COMPUTE_RESTART_Y__RESTART__SHIFT__CI__VI 0x00000000 -#define COMPUTE_RESTART_Z__RESTART__SHIFT__CI__VI 0x00000000 -#define COMPUTE_START_X__START__SHIFT 0x00000000 -#define COMPUTE_START_Y__START__SHIFT 0x00000000 -#define COMPUTE_START_Z__START__SHIFT 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT__CI__VI 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT__CI__VI 0x00000010 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT__CI__VI 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT__CI__VI 0x00000010 -#define COMPUTE_TBA_HI__DATA__SHIFT 0x00000000 -#define COMPUTE_TBA_LO__DATA__SHIFT 0x00000000 -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT__CI__VI 0x00000000 -#define COMPUTE_TMA_HI__DATA__SHIFT 0x00000000 -#define COMPUTE_TMA_LO__DATA__SHIFT 0x00000000 -#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c -#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000 -#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000 -#define COMPUTE_VMID__DATA__SHIFT 0x00000000 -#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x00000000 -#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x00000000 -#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x00000002 -#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x00000003 -#define CONFIG_CNTL__VGA_DIS__SHIFT 0x00000001 -#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x00000000 -#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x00000000 -#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x00000000 -#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT__SI 0x00000000 -#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT__SI 0x00000001 -#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT__SI 0x00000007 -#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT__SI 0x00000000 -#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT__SI 0x0000000f -#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT__SI 0x00000000 -#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT__SI 0x00000004 -#define CORB_SIZE__CORB_SIZE__SHIFT__SI 0x00000000 -#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT__SI 0x00000000 -#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT__SI 0x00000000 -#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT__SI 0x00000000 -#define CORE_PERF_BOOST_CONTROL__Apm_Master_En__SHIFT__CI__VI 0x00000007 -#define CORE_PERF_BOOST_CONTROL__Boost_Lock__SHIFT__CI__VI 0x0000001f -#define CORE_PERF_BOOST_CONTROL__Boost_Source__SHIFT__CI__VI 0x00000000 -#define CORE_PERF_BOOST_CONTROL__Num_Boost_States__SHIFT__CI__VI 0x00000002 -#define CORE_PERF_BOOST_CONTROL__RESERVED_1__SHIFT__CI__VI 0x00000005 -#define CORE_PERF_BOOST_CONTROL__RESERVED__SHIFT__CI__VI 0x00000008 -#define CORE_PERF_BOOST_CONTROL__Tdp_Limit_Pstate__SHIFT__CI__VI 0x0000001c -#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT__CI 0x00000008 -#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT__CI 0x00000010 -#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT__CI 0x00000008 -#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT__CI 0x00000010 -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT__CI__VI 0x00000000 -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT__CI 0x00000008 -#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT__CI 0x00000010 -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define CPU_INT_ARGUMENT__DATA__SHIFT__CI__VI 0x00000000 -#define CPU_INT_REQ__INT_TOGGLE__SHIFT__CI__VI 0x00000000 -#define CPU_INT_REQ__SERVICE_INDEX__SHIFT__CI__VI 0x00000001 -#define CPU_INT_RESPONSE__DATA__SHIFT__CI__VI 0x00000000 -#define CPU_INT_STATUS__INT_ACK__SHIFT__CI__VI 0x00000000 -#define CPU_INT_STATUS__INT_DONE__SHIFT__CI__VI 0x00000001 -#define CPU_TDP_LIMIT_0__Cmp_Unit_Tdp_Limit_0__SHIFT__CI__VI 0x00000010 -#define CPU_TDP_LIMIT_0__Node_Tdp_Limit__SHIFT__CI__VI 0x00000000 -#define CPU_TDP_LIMIT_0__RESERVED_1__SHIFT__CI__VI 0x0000000c -#define CPU_TDP_LIMIT_0__RESERVED__SHIFT__CI__VI 0x00000018 -#define CPU_TDP_LIMIT_1__Cmp_Unit_Tdp_Limit_1__SHIFT__CI__VI 0x00000000 -#define CPU_TDP_LIMIT_1__RESERVED__SHIFT__CI__VI 0x00000008 -#define CPU_TDP_RUN_AVG__RESERVED__SHIFT__CI__VI 0x0000001a -#define CPU_TDP_RUN_AVG__Run_Avg_Range__SHIFT__CI__VI 0x00000000 -#define CPU_TDP_RUN_AVG__Tdp_Run_Avg_Acc_Cap__SHIFT__CI__VI 0x00000004 -#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d -#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010 -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000 -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002 -#define CP_APPEND_DATA__DATA__SHIFT 0x00000000 -#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x00000000 -#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x00000000 -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000 -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000 -#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016 -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006 -#define CP_BUSY_STAT__CS_CONTEXT_BUSY__SHIFT__SI 0x00000010 -#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012 -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f -#define CP_BUSY_STAT__INDR1_FETCHING_DATA__SHIFT__SI 0x00000002 -#define CP_BUSY_STAT__INDR2_FETCHING_DATA__SHIFT__SI 0x00000003 -#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011 -#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008 -#define CP_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT__SI 0x0000000b -#define CP_BUSY_STAT__PENDING_CMD_BUFFERS__SHIFT__SI 0x00000005 -#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007 -#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014 -#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015 -#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a -#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009 -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000 -#define CP_BUSY_STAT__RING_FETCHING_DATA__SHIFT__SI 0x00000001 -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e -#define CP_BUSY_STAT__STATE_FETCHING_DATA__SHIFT__SI 0x00000004 -#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013 -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010 -#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000 -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000 -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT__CI__VI 0x00000002 -#define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT__CI__VI 0x00000003 -#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT__CI__VI 0x00000000 -#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT__CI__VI 0x00000001 -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000 -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 -#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT__CI__VI 0x00000000 -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 -#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT__CI__VI 0x00000000 -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000 -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005 -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000 -#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT__CI__VI 0x00000000 -#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT__CI__VI 0x00000000 -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000 -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010 -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000 -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010 -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000 -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010 -#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 -#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 -#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 -#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 -#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT__CI__VI 0x0000000c -#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 -#define CP_CNTL__NOT_USED__SHIFT__SI 0x00000000 -#define CP_CNTX_STAT__ACTIVE_CS0_CONTEXTS__SHIFT__SI 0x00000000 -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014 -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT__CI__VI 0x00000000 -#define CP_CNTX_STAT__APPEND_CNTX_ACTIVE__SHIFT__SI 0x0000000c -#define CP_CNTX_STAT__CURRENT_CS0_CONTEXT__SHIFT__SI 0x00000008 -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT__CI__VI 0x00000008 -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT__CI__VI 0x00000000 -#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000 -#define CP_COHER_CNTL2__VMID__SHIFT__SI 0x00000000 -#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006 -#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007 -#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008 -#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009 -#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a -#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b -#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c -#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d -#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019 -#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a -#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e -#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000 -#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001 -#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013 -#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015 -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT__CI__VI 0x0000001c -#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016 -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT__CI__VI 0x0000000f -#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017 -#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT__CI 0x00000010 -#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT__CI__VI 0x00000012 -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT__CI__VI 0x00000000 -#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000 -#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000 -#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000 -#define CP_COHER_STATUS__MEID__SHIFT__CI__VI 0x00000018 -#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x0000001e -#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f -#define CP_CONFIG__CP_RDREQ_URG__SHIFT__SI 0x00000008 -#define CP_CONFIG__CP_REQ_TRAN__SHIFT__SI 0x00000010 -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT__CI__VI 0x00000004 -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT__CI__VI 0x00000000 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT__CI__VI 0x00000014 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT__CI__VI 0x00000010 -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT__CI__VI 0x00000008 -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT__CI__VI 0x00000004 -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT__CI__VI 0x00000006 -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT__CI__VI 0x00000005 -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT__CI__VI 0x00000000 -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT__CI__VI 0x00000003 -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT__CI__VI 0x00000002 -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT__CI__VI 0x00000009 -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT__CI__VI 0x0000000a -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT__CI__VI 0x0000000b -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT__CI__VI 0x0000000c -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT__CI__VI 0x0000000d -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT__CI__VI 0x00000001 -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT__CI__VI 0x00000007 -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT__CI__VI 0x00000018 -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT__CI__VI 0x00000014 -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT__CI__VI 0x00000016 -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT__CI__VI 0x00000015 -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT__CI__VI 0x00000010 -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT__CI__VI 0x00000013 -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT__CI__VI 0x00000012 -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT__CI__VI 0x00000019 -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT__CI__VI 0x0000001a -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT__CI__VI 0x0000001b -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT__CI__VI 0x0000001c -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT__CI__VI 0x0000001d -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT__CI__VI 0x00000011 -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT__CI__VI 0x00000017 -#define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT__CI__VI 0x00000000 -#define CP_CPC_DEBUG_DATA__DEBUG_DATA__SHIFT__CI__VI 0x00000000 -#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT__CI__VI 0x0000001d -#define CP_CPC_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT__CI__VI 0x00000000 -#define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT__CI__VI 0x0000001a -#define CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT__CI__VI 0x00000016 -#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT__CI__VI 0x00000019 -#define CP_CPC_DEBUG__PRIV_VIOLATION_CNTL__SHIFT__CI__VI 0x0000001b -#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT__CI__VI 0x00000018 -#define CP_CPC_DEBUG__VMID_VIOLATION_CNTL__SHIFT__CI__VI 0x0000000f -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT__CI__VI 0x00000000 -#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT__CI 0x00000000 -#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT__CI__VI 0x00000000 -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT__CI__VI 0x00000000 -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT__CI__VI 0x00000000 -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT__CI__VI 0x00000008 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT__CI 0x0000000b -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT__CI 0x0000000c -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT__CI__VI 0x0000000a -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT__CI__VI 0x00000009 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT__CI__VI 0x0000000d -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT__CI__VI 0x00000010 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT__CI 0x00000013 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT__CI 0x00000014 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT__CI__VI 0x00000012 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT__CI__VI 0x00000011 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT__CI__VI 0x00000015 -#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT__CI 0x00000000 -#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT__CI 0x00000001 -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT__CI__VI 0x00000004 -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT__CI__VI 0x00000003 -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT__CI__VI 0x00000006 -#define CP_CPC_STATUS__CPC_BUSY__SHIFT__CI__VI 0x0000001f -#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT__CI__VI 0x0000001e -#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT__CI__VI 0x0000001d -#define CP_CPC_STATUS__DC0_BUSY__SHIFT__CI__VI 0x00000002 -#define CP_CPC_STATUS__DC1_BUSY__SHIFT__CI__VI 0x00000003 -#define CP_CPC_STATUS__MEC1_BUSY__SHIFT__CI__VI 0x00000000 -#define CP_CPC_STATUS__MEC2_BUSY__SHIFT__CI__VI 0x00000001 -#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT__CI 0x00000008 -#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT__CI 0x00000009 -#define CP_CPC_STATUS__QU_BUSY__SHIFT__CI__VI 0x0000000c -#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT__CI__VI 0x00000004 -#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT__CI__VI 0x00000005 -#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT__CI__VI 0x00000006 -#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT__CI__VI 0x00000007 -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT__CI__VI 0x0000000b -#define CP_CPC_STATUS__TCIU_BUSY__SHIFT__CI__VI 0x0000000a -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT__CI__VI 0x00000007 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT__CI__VI 0x00000005 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT__CI__VI 0x00000006 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT__CI__VI 0x00000002 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT__CI__VI 0x00000003 -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT__CI__VI 0x00000008 -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT__CI__VI 0x00000001 -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT__CI__VI 0x00000004 -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT__CI__VI 0x0000000b -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT__CI__VI 0x00000016 -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT__CI__VI 0x0000000c -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT__CI__VI 0x0000000e -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT__CI__VI 0x00000015 -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT__CI__VI 0x00000017 -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT__CI__VI 0x0000001f -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT__CI__VI 0x00000013 -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT__CI__VI 0x00000014 -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT__CI__VI 0x0000000d -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT__CI__VI 0x00000011 -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT__CI__VI 0x0000001e -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT__CI__VI 0x00000012 -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT__CI__VI 0x00000018 -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT__CI__VI 0x00000019 -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT__CI__VI 0x0000001c -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT__CI__VI 0x0000001a -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT__CI__VI 0x0000001b -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT__CI__VI 0x00000010 -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT__CI__VI 0x0000000f -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT__CI__VI 0x0000001d -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT__CI__VI 0x00000009 -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT__CI__VI 0x00000000 -#define CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT__CI__VI 0x00000000 -#define CP_CPF_DEBUG_DATA__DEBUG_DATA__SHIFT__CI__VI 0x00000000 -#define CP_CPF_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT__CI__VI 0x00000000 -#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT__CI__VI 0x00000019 -#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT__CI__VI 0x00000018 -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT__CI__VI 0x00000001 -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT__CI__VI 0x00000002 -#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT__CI 0x00000004 -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT__CI__VI 0x00000000 -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT__CI__VI 0x00000003 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT__CI__VI 0x00000005 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT__CI__VI 0x00000006 -#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT__CI__VI 0x0000001e -#define CP_CPF_STATUS__CPF_BUSY__SHIFT__CI__VI 0x0000001f -#define CP_CPF_STATUS__CSF_BUSY__SHIFT__CI__VI 0x00000001 -#define CP_CPF_STATUS__HQD_BUSY__SHIFT__CI__VI 0x0000000f -#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT__CI__VI 0x0000000d -#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT__CI 0x00000002 -#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT__CI 0x00000003 -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT__CI__VI 0x00000000 -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT__CI__VI 0x00000004 -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT__CI__VI 0x0000000a -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT__CI__VI 0x0000000b -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT__CI__VI 0x00000009 -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT__CI__VI 0x00000006 -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT__CI__VI 0x00000007 -#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT__CI__VI 0x00000005 -#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT__CI__VI 0x00000008 -#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT__CI__VI 0x0000000c -#define CP_CPF_STATUS__TCIU_BUSY__SHIFT__CI__VI 0x0000000e -#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x00000000 -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008 -#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x00000000 -#define CP_DEBUG_CNTL__CP_DEBUG_INDX__SHIFT__SI 0x00000000 -#define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT__CI__VI 0x00000000 -#define CP_DEBUG_DATA__DATA__SHIFT__SI 0x00000000 -#define CP_DEBUG_DATA__DEBUG_DATA__SHIFT__CI__VI 0x00000000 -#define CP_DEBUG__BUSY_EXTENDER__SHIFT__CI__VI 0x00000013 -#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT__CI__VI 0x0000001e -#define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT__CI__VI 0x0000001d -#define CP_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT__CI__VI 0x00000006 -#define CP_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT 0x00000000 -#define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT__CI__VI 0x0000001a -#define CP_DEBUG__INTERRUPT_DISABLE__SHIFT__CI__VI 0x00000016 -#define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x00000019 -#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 -#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT__SI 0x0000001a -#define CP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0000001b -#define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT 0x00000010 -#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x00000018 -#define CP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x0000000f -#define CP_DEVICE_ID__DEVICE_ID__SHIFT__CI__VI 0x00000000 -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT__CI__VI 0x00000000 -#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT__CI__VI 0x00000005 -#define CP_DFY_CNTL__ATC__SHIFT__CI 0x0000000b -#define CP_DFY_CNTL__POLICY__SHIFT__CI 0x00000008 -#define CP_DFY_CNTL__VOL__SHIFT__CI 0x0000000a -#define CP_DFY_DATA_0__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_10__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_11__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_12__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_13__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_14__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_15__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_1__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_2__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_3__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_4__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_5__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_6__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_7__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_8__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_DATA_9__DATA__SHIFT__CI__VI 0x00000000 -#define CP_DFY_STAT__BURST_COUNT__SHIFT__CI__VI 0x00000000 -#define CP_DFY_STAT__BUSY__SHIFT__CI__VI 0x0000001f -#define CP_DFY_STAT__TAGS_PENDING__SHIFT__CI__VI 0x00000010 -#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010 -#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004 -#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e -#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c -#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d -#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000 -#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d -#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b -#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x00000015 -#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x00000018 -#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e -#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c -#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a -#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x00000016 -#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT__CI__VI 0x00000018 -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT__CI__VI 0x00000019 -#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT__CI__VI 0x00000014 -#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT__CI 0x0000001b -#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT__CI__VI 0x0000000c -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT__CI__VI 0x0000000d -#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT__CI__VI 0x0000001d -#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT__CI 0x0000000f -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 -#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000 -#define CP_DMA_ME_SRC_ADDR_HI__DST_SELECT__SHIFT__SI 0x00000014 -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 -#define CP_DMA_ME_SRC_ADDR_HI__SRC_SELECT__SHIFT__SI 0x0000001d -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 -#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000 -#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d -#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b -#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x00000015 -#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x00000018 -#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e -#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c -#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a -#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x00000016 -#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT__CI__VI 0x00000018 -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT__CI__VI 0x00000019 -#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT__CI__VI 0x00000014 -#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT__CI 0x0000001b -#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT__CI__VI 0x0000000c -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT__CI__VI 0x0000000d -#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT__CI__VI 0x0000001d -#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT__CI 0x0000000f -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 -#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000 -#define CP_DMA_PFP_SRC_ADDR_HI__DST_SELECT__SHIFT__SI 0x00000014 -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_SELECT__SHIFT__SI 0x0000001d -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 -#define CP_DMA_PIO_COMMAND__BYTE_COUNT__SHIFT 0x00000000 -#define CP_DMA_PIO_COMMAND__DAIC__SHIFT 0x0000001d -#define CP_DMA_PIO_COMMAND__DAS__SHIFT 0x0000001b -#define CP_DMA_PIO_COMMAND__DIS_WC__SHIFT 0x00000015 -#define CP_DMA_PIO_COMMAND__DST_SWAP__SHIFT 0x00000018 -#define CP_DMA_PIO_COMMAND__RAW_WAIT__SHIFT 0x0000001e -#define CP_DMA_PIO_COMMAND__SAIC__SHIFT 0x0000001c -#define CP_DMA_PIO_COMMAND__SAS__SHIFT 0x0000001a -#define CP_DMA_PIO_COMMAND__SRC_SWAP__SHIFT 0x00000016 -#define CP_DMA_PIO_CONTROL__DST_ATC__SHIFT__CI__VI 0x00000018 -#define CP_DMA_PIO_CONTROL__DST_CACHE_POLICY__SHIFT__CI__VI 0x00000019 -#define CP_DMA_PIO_CONTROL__DST_SELECT__SHIFT__CI__VI 0x00000014 -#define CP_DMA_PIO_CONTROL__DST_VOLATILE__SHIFT__CI 0x0000001b -#define CP_DMA_PIO_CONTROL__SRC_ATC__SHIFT__CI__VI 0x0000000c -#define CP_DMA_PIO_CONTROL__SRC_CACHE_POLICY__SHIFT__CI__VI 0x0000000d -#define CP_DMA_PIO_CONTROL__SRC_SELECT__SHIFT__CI__VI 0x0000001d -#define CP_DMA_PIO_CONTROL__SRC_VOLATILE__SHIFT__CI 0x0000000f -#define CP_DMA_PIO_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 -#define CP_DMA_PIO_DST_ADDR__DST_ADDR__SHIFT 0x00000000 -#define CP_DMA_PIO_SRC_ADDR_HI__DST_SELECT__SHIFT__SI 0x00000014 -#define CP_DMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 -#define CP_DMA_PIO_SRC_ADDR_HI__SRC_SELECT__SHIFT__SI 0x0000001d -#define CP_DMA_PIO_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c -#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT__SI__CI 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT__SI__CI 0x00000004 -#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT__SI__CI 0x0000000a -#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT__SI__CI 0x00000010 -#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT__SI__CI 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT__SI__CI 0x00000004 -#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT__SI__CI 0x0000000a -#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT__SI__CI 0x00000010 -#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT__SI__CI 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT__SI__CI 0x00000004 -#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT__SI__CI 0x0000000a -#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT__SI__CI 0x00000010 -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT__SI__CI 0x00000004 -#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT__SI__CI 0x0000000a -#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010 -#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT__CI__VI 0x00000000 -#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT__CI__VI 0x00000000 -#define CP_EOP_DONE_ADDR_HI__EOP_DONE_ADDR_HI__SHIFT__SI 0x00000000 -#define CP_EOP_DONE_ADDR_HI__EOP_DONE_DATA_SEL__SHIFT__SI 0x0000001d -#define CP_EOP_DONE_ADDR_HI__EOP_DONE_INT_SEL__SHIFT__SI 0x00000018 -#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT__CI__VI 0x00000002 -#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT__CI 0x00000000 -#define CP_EOP_DONE_ADDR_LO__EOP_DONE_ADDR_LO__SHIFT__SI 0x00000002 -#define CP_EOP_DONE_ADDR_LO__EOP_DONE_ADDR_SWAP__SHIFT__SI 0x00000000 -#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT__CI__VI 0x00000000 -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT__CI__VI 0x0000001d -#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT__CI__VI 0x00000010 -#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT__CI__VI 0x00000018 -#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT__CI__VI 0x00000000 -#define CP_EOP_DONE_DATA_HI__EOP_DONE_DATA_HI__SHIFT__SI 0x00000000 -#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT__CI__VI 0x00000000 -#define CP_EOP_DONE_DATA_LO__EOP_DONE_DATA_LO__SHIFT__SI 0x00000000 -#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT__CI__VI 0x00000019 -#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT__CI 0x0000001b -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT__CI__VI 0x0000000c -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT__CI__VI 0x00000000 -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000 -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000 -#define CP_FETCHER_SOURCE__ME_SRC__SHIFT__CI 0x00000000 -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000 -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000 -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000 -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010 -#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000 -#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT__CI 0x00000000 -#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT__CI 0x00000000 -#define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT__CI 0x00000018 -#define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT__CI 0x00000017 -#define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT__CI 0x00000000 -#define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT__CI 0x0000001a -#define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT__CI 0x0000001c -#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT__CI 0x0000001f -#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT__CI 0x0000000d -#define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT__CI 0x00000008 -#define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT__CI 0x00000009 -#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT__CI 0x0000000e -#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT__CI 0x0000000c -#define CP_HPD_EOP_VMID__VMID__SHIFT__CI 0x00000000 -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT__CI__VI 0x00000010 -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT__CI__VI 0x00000000 -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT__CI__VI 0x00000008 -#define CP_HQD_ACTIVE__ACTIVE__SHIFT__CI__VI 0x00000000 -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT__CI__VI 0x00000008 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT__CI__VI 0x00000000 -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT__CI__VI 0x00000004 -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT__CI__VI 0x00000000 -#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT__CI 0x00000002 -#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT__CI 0x00000000 -#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT__CI 0x00000009 -#define CP_HQD_HQ_SCHEDULER0__RSVR_31_10__SHIFT__CI 0x0000000a -#define CP_HQD_HQ_SCHEDULER0__RSV_6_4__SHIFT__CI 0x00000004 -#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT__CI 0x00000007 -#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT__CI 0x00000008 -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT__CI__VI 0x00000000 -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT__CI__VI 0x00000000 -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT__CI__VI 0x00000002 -#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT__CI__VI 0x00000017 -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT__CI__VI 0x0000001e -#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT__CI__VI 0x00000000 -#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT__CI 0x0000001a -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT__CI__VI 0x00000014 -#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT__CI__VI 0x0000001f -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT__CI__VI 0x00000000 -#define CP_HQD_IQ_RPTR__OFFSET__SHIFT__CI__VI 0x00000000 -#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT__CI__VI 0x0000001f -#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT__CI__VI 0x00000010 -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT__CI__VI 0x0000000c -#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT__CI__VI 0x00000017 -#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT__CI 0x0000001a -#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT__CI__VI 0x0000001e -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT__CI__VI 0x0000001d -#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT__CI__VI 0x00000008 -#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT__CI__VI 0x00000000 -#define CP_HQD_MSG_TYPE__ACTION__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT__CI__VI 0x0000001f -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT__CI__VI 0x00000008 -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PQ_BASE__ADDR__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT__CI 0x00000010 -#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT__CI__VI 0x0000001f -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT__CI__VI 0x00000014 -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT__CI__VI 0x0000001b -#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT__CI__VI 0x00000017 -#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT__CI 0x0000001a -#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT__CI__VI 0x0000001e -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT__CI__VI 0x0000001d -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT__CI__VI 0x00000008 -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT__CI__VI 0x0000001c -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT__CI__VI 0x0000001e -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT__CI__VI 0x0000001f -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT__CI__VI 0x00000002 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT__CI__VI 0x0000001d -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT__CI__VI 0x0000001c -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT__CI__VI 0x00000002 -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT__CI__VI 0x00000000 -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT__CI__VI 0x00000002 -#define CP_HQD_PQ_WPTR__OFFSET__SHIFT__CI__VI 0x00000000 -#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT__CI__VI 0x00000008 -#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT__CI__VI 0x00000000 -#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT__CI__VI 0x00000004 -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT__CI__VI 0x00000000 -#define CP_HQD_SEMA_CMD__RESULT__SHIFT__CI__VI 0x00000001 -#define CP_HQD_SEMA_CMD__RETRY__SHIFT__CI__VI 0x00000000 -#define CP_HQD_VMID__IB_VMID__SHIFT__CI__VI 0x00000008 -#define CP_HQD_VMID__VMID__SHIFT__CI__VI 0x00000000 -#define CP_HQD_VMID__VQID__SHIFT__CI__VI 0x00000010 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL0__SHIFT__CI__VI 0x00000000 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL10__SHIFT__CI__VI 0x00000014 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL11__SHIFT__CI__VI 0x00000016 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL12__SHIFT__CI__VI 0x00000018 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL13__SHIFT__CI__VI 0x0000001a -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL14__SHIFT__CI__VI 0x0000001c -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL15__SHIFT__CI__VI 0x0000001e -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL1__SHIFT__CI__VI 0x00000002 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL2__SHIFT__CI__VI 0x00000004 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL3__SHIFT__CI__VI 0x00000006 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL4__SHIFT__CI__VI 0x00000008 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL5__SHIFT__CI__VI 0x0000000a -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL6__SHIFT__CI__VI 0x0000000c -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL7__SHIFT__CI__VI 0x0000000e -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL8__SHIFT__CI__VI 0x00000010 -#define CP_HYP_REG_PRIV_LEVEL_A__PRIV_LEVEL9__SHIFT__CI__VI 0x00000012 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL16__SHIFT__CI__VI 0x00000000 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL17__SHIFT__CI__VI 0x00000002 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL18__SHIFT__CI__VI 0x00000004 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL19__SHIFT__CI__VI 0x00000006 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL20__SHIFT__CI__VI 0x00000008 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL21__SHIFT__CI__VI 0x0000000a -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL22__SHIFT__CI__VI 0x0000000c -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL23__SHIFT__CI__VI 0x0000000e -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL24__SHIFT__CI__VI 0x00000010 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL25__SHIFT__CI__VI 0x00000012 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL26__SHIFT__CI__VI 0x00000014 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL27__SHIFT__CI__VI 0x00000016 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL28__SHIFT__CI__VI 0x00000018 -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL29__SHIFT__CI__VI 0x0000001a -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL30__SHIFT__CI__VI 0x0000001c -#define CP_HYP_REG_PRIV_LEVEL_B__PRIV_LEVEL31__SHIFT__CI__VI 0x0000001e -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL32__SHIFT__CI__VI 0x00000000 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL33__SHIFT__CI__VI 0x00000002 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL34__SHIFT__CI__VI 0x00000004 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL35__SHIFT__CI__VI 0x00000006 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL36__SHIFT__CI__VI 0x00000008 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL37__SHIFT__CI__VI 0x0000000a -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL38__SHIFT__CI__VI 0x0000000c -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL39__SHIFT__CI__VI 0x0000000e -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL40__SHIFT__CI__VI 0x00000010 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL41__SHIFT__CI__VI 0x00000012 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL42__SHIFT__CI__VI 0x00000014 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL43__SHIFT__CI__VI 0x00000016 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL44__SHIFT__CI__VI 0x00000018 -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL45__SHIFT__CI__VI 0x0000001a -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL46__SHIFT__CI__VI 0x0000001c -#define CP_HYP_REG_PRIV_LEVEL_C__PRIV_LEVEL47__SHIFT__CI__VI 0x0000001e -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL48__SHIFT__CI__VI 0x00000000 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL49__SHIFT__CI__VI 0x00000002 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL50__SHIFT__CI__VI 0x00000004 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL51__SHIFT__CI__VI 0x00000006 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL52__SHIFT__CI__VI 0x00000008 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL53__SHIFT__CI__VI 0x0000000a -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL54__SHIFT__CI__VI 0x0000000c -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL55__SHIFT__CI__VI 0x0000000e -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL56__SHIFT__CI__VI 0x00000010 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL57__SHIFT__CI__VI 0x00000012 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL58__SHIFT__CI__VI 0x00000014 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL59__SHIFT__CI__VI 0x00000016 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL60__SHIFT__CI__VI 0x00000018 -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL61__SHIFT__CI__VI 0x0000001a -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL62__SHIFT__CI__VI 0x0000001c -#define CP_HYP_REG_PRIV_LEVEL_D__PRIV_LEVEL63__SHIFT__CI__VI 0x0000001e -#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 -#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 -#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 -#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000 -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000 -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000 -#define CP_IB1_PRIV_BASE_HI__IB1_PRIV_BASE_HI__SHIFT 0x00000000 -#define CP_IB1_PRIV_BASE_LO__IB1_PRIV_BASE_LO__SHIFT 0x00000002 -#define CP_IB1_PRIV_BUFSZ__IB1_PRIV_BUFSZ__SHIFT 0x00000000 -#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 -#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 -#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 -#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000 -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000 -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000 -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL_RING0__CP_RINGID0_INT_ENABLE__SHIFT__SI 0x0000001f -#define CP_INT_CNTL_RING0__CP_RINGID1_INT_ENABLE__SHIFT__SI 0x0000001e -#define CP_INT_CNTL_RING0__CP_RINGID2_INT_ENABLE__SHIFT__SI 0x0000001d -#define CP_INT_CNTL_RING0__GDS_ALLOC_ERROR_INT_ENABLE__SHIFT__SI 0x0000000f -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL_RING0__SEM_SIG_INCOMPLETE_INT_ENABLE__SHIFT__SI 0x00000010 -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL_RING0__WAITMEM_SEM_INT_ENABLE__SHIFT__SI 0x00000015 -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL_RING1__CP_RINGID0_INT_ENABLE__SHIFT__SI 0x0000001f -#define CP_INT_CNTL_RING1__CP_RINGID1_INT_ENABLE__SHIFT__SI 0x0000001e -#define CP_INT_CNTL_RING1__CP_RINGID2_INT_ENABLE__SHIFT__SI 0x0000001d -#define CP_INT_CNTL_RING1__GDS_ALLOC_ERROR_INT_ENABLE__SHIFT__SI 0x0000000f -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL_RING1__SEM_SIG_INCOMPLETE_INT_ENABLE__SHIFT__SI 0x00000010 -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL_RING1__WAITMEM_SEM_INT_ENABLE__SHIFT__SI 0x00000015 -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL_RING2__CP_RINGID0_INT_ENABLE__SHIFT__SI 0x0000001f -#define CP_INT_CNTL_RING2__CP_RINGID1_INT_ENABLE__SHIFT__SI 0x0000001e -#define CP_INT_CNTL_RING2__CP_RINGID2_INT_ENABLE__SHIFT__SI 0x0000001d -#define CP_INT_CNTL_RING2__GDS_ALLOC_ERROR_INT_ENABLE__SHIFT__SI 0x0000000f -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL_RING2__SEM_SIG_INCOMPLETE_INT_ENABLE__SHIFT__SI 0x00000010 -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL_RING2__WAITMEM_SEM_INT_ENABLE__SHIFT__SI 0x00000015 -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL__CP_RINGID0_INT_ENABLE__SHIFT__SI 0x0000001f -#define CP_INT_CNTL__CP_RINGID1_INT_ENABLE__SHIFT__SI 0x0000001e -#define CP_INT_CNTL__CP_RINGID2_INT_ENABLE__SHIFT__SI 0x0000001d -#define CP_INT_CNTL__GDS_ALLOC_ERROR_INT_ENABLE__SHIFT__SI 0x0000000f -#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL__SEM_SIG_INCOMPLETE_INT_ENABLE__SHIFT__SI 0x00000010 -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL__WAITMEM_SEM_INT_ENABLE__SHIFT__SI 0x00000015 -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT__SI__CI 0x00000013 -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS_RING0__CP_RINGID0_INT_STAT__SHIFT__SI 0x0000001f -#define CP_INT_STATUS_RING0__CP_RINGID1_INT_STAT__SHIFT__SI 0x0000001e -#define CP_INT_STATUS_RING0__CP_RINGID2_INT_STAT__SHIFT__SI 0x0000001d -#define CP_INT_STATUS_RING0__GDS_ALLOC_ERROR_INT_STAT__SHIFT__SI 0x0000000f -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT__CI__VI 0x0000001f -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT__CI__VI 0x0000001e -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT__CI__VI 0x0000001d -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS_RING0__SEM_SIG_INCOMPLETE_INT_STAT__SHIFT__SI 0x00000010 -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS_RING0__WAITMEM_SEM_INT_STAT__SHIFT__SI 0x00000015 -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS_RING1__CP_RINGID0_INT_STAT__SHIFT__SI 0x0000001f -#define CP_INT_STATUS_RING1__CP_RINGID1_INT_STAT__SHIFT__SI 0x0000001e -#define CP_INT_STATUS_RING1__CP_RINGID2_INT_STAT__SHIFT__SI 0x0000001d -#define CP_INT_STATUS_RING1__GDS_ALLOC_ERROR_INT_STAT__SHIFT__SI 0x0000000f -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT__CI__VI 0x0000001f -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT__CI__VI 0x0000001e -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT__CI__VI 0x0000001d -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS_RING1__SEM_SIG_INCOMPLETE_INT_STAT__SHIFT__SI 0x00000010 -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS_RING1__WAITMEM_SEM_INT_STAT__SHIFT__SI 0x00000015 -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS_RING2__CP_RINGID0_INT_STAT__SHIFT__SI 0x0000001f -#define CP_INT_STATUS_RING2__CP_RINGID1_INT_STAT__SHIFT__SI 0x0000001e -#define CP_INT_STATUS_RING2__CP_RINGID2_INT_STAT__SHIFT__SI 0x0000001d -#define CP_INT_STATUS_RING2__GDS_ALLOC_ERROR_INT_STAT__SHIFT__SI 0x0000000f -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT__CI__VI 0x0000001f -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT__CI__VI 0x0000001e -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT__CI__VI 0x0000001d -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS_RING2__SEM_SIG_INCOMPLETE_INT_STAT__SHIFT__SI 0x00000010 -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS_RING2__WAITMEM_SEM_INT_STAT__SHIFT__SI 0x00000015 -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS__CP_RINGID0_INT_STAT__SHIFT__SI 0x0000001f -#define CP_INT_STATUS__CP_RINGID1_INT_STAT__SHIFT__SI 0x0000001e -#define CP_INT_STATUS__CP_RINGID2_INT_STAT__SHIFT__SI 0x0000001d -#define CP_INT_STATUS__GDS_ALLOC_ERROR_INT_STAT__SHIFT__SI 0x0000000f -#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT__CI__VI 0x0000001f -#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT__CI__VI 0x0000001e -#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT__CI__VI 0x0000001d -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS__SEM_SIG_INCOMPLETE_INT_STAT__SHIFT__SI 0x00000010 -#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS__WAITMEM_SEM_INT_STAT__SHIFT__SI 0x00000015 -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013 -#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014 -#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e -#define CP_INT_STAT_DEBUG__CP_RINGID0_INT_ASSERTED__SHIFT__SI 0x0000001f -#define CP_INT_STAT_DEBUG__CP_RINGID1_INT_ASSERTED__SHIFT__SI 0x0000001e -#define CP_INT_STAT_DEBUG__CP_RINGID2_INT_ASSERTED__SHIFT__SI 0x0000001d -#define CP_INT_STAT_DEBUG__GDS_ALLOC_ERROR_INT_ASSERTED__SHIFT__SI 0x0000000f -#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT__CI__VI 0x0000001f -#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT__CI__VI 0x0000001e -#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT__CI__VI 0x0000001d -#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018 -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016 -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017 -#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b -#define CP_INT_STAT_DEBUG__SEM_SIG_INCOMPLETE_INT_ASSERTED__SHIFT__SI 0x00000010 -#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a -#define CP_INT_STAT_DEBUG__WAITMEM_SEM_INT_ASSERTED__SHIFT__SI 0x00000015 -#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011 -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT__CI__VI 0x00000008 -#define CP_IQ_WAIT_TIME1__GWS__SHIFT__CI__VI 0x00000018 -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT__CI__VI 0x00000000 -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT__CI__VI 0x00000010 -#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT__CI__VI 0x00000018 -#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT__CI__VI 0x00000000 -#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT__CI__VI 0x00000008 -#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT__CI__VI 0x00000010 -#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT__CI__VI 0x00000000 -#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT__SI__CI 0x00000000 -#define CP_MC_RD_RETURN_TAGS__READ_RETURN_NACK__SHIFT__SI 0x00000010 -#define CP_MC_RD_RETURN_TAGS__READ_RETURN_TAG__SHIFT__SI 0x00000000 -#define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT__CI 0x00000000 -#define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT__CI 0x00000010 -#define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT__CI 0x00000000 -#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME0_PIPE0_VMID__VMID__SHIFT__CI__VI 0x00000000 -#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME0_PIPE1_VMID__VMID__SHIFT__CI__VI 0x00000000 -#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT__CI__VI 0x00000000 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT__CI__VI 0x00000008 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT__CI__VI 0x00000010 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT__CI__VI 0x00000018 -#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT__CI__VI 0x0000000e -#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT__CI__VI 0x0000000d -#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT__CI__VI 0x0000001f -#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT__CI__VI 0x0000001e -#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT__CI__VI 0x0000001d -#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT__CI__VI 0x00000018 -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT__CI__VI 0x00000017 -#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT__CI__VI 0x0000001b -#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT__CI__VI 0x0000001a -#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT__CI__VI 0x00000000 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT__CI__VI 0x00000008 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT__CI__VI 0x00000010 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT__CI__VI 0x00000018 -#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT__CI__VI 0x0000000e -#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT__CI__VI 0x0000000d -#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT__CI__VI 0x0000001f -#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT__CI__VI 0x0000001e -#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT__CI__VI 0x0000001d -#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT__CI__VI 0x00000018 -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT__CI__VI 0x00000017 -#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT__CI__VI 0x0000001b -#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT__CI__VI 0x0000001a -#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000000e -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT__CI__VI 0x0000000d -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT__CI__VI 0x0000001f -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT__CI__VI 0x0000001e -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT__CI__VI 0x0000001d -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT__CI__VI 0x00000018 -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT__CI__VI 0x00000017 -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT__CI__VI 0x0000001b -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT__CI__VI 0x0000001a -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT__CI__VI 0x00000011 -#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT__CI__VI 0x00000000 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT__CI__VI 0x00000000 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT__CI__VI 0x00000008 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT__CI__VI 0x00000010 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT__CI__VI 0x00000018 -#define CP_MEC1_F32_INTERRUPT__ECC_ROQ_FED_INT__SHIFT__CI 0x00000000 -#define CP_MEC1_F32_INTERRUPT__MEC_F32_INT_3__SHIFT__CI 0x00000003 -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT__CI__VI 0x00000001 -#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT__CI__VI 0x00000002 -#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT__CI__VI 0x00000000 -#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT__CI__VI 0x00000000 -#define CP_MEC2_F32_INTERRUPT__ECC_ROQ_FED_INT__SHIFT__CI 0x00000000 -#define CP_MEC2_F32_INTERRUPT__MEC_F32_INT_3__SHIFT__CI 0x00000003 -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT__CI__VI 0x00000001 -#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT__CI__VI 0x00000002 -#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT__CI__VI 0x00000000 -#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT__CI__VI 0x00000000 -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT__CI__VI 0x00000004 -#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT__CI__VI 0x0000001e -#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT__CI__VI 0x0000001f -#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT__CI__VI 0x0000001c -#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT__CI__VI 0x0000001d -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT__CI__VI 0x00000000 -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT__CI__VI 0x00000000 -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT__CI__VI 0x00000000 -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT__CI__VI 0x00000000 -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT__CI__VI 0x00000000 -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT__CI__VI 0x00000000 -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008 -#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 -#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 -#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 -#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 -#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 -#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT__CI__VI 0x00000000 -#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000 -#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008 -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018 -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT__CI__VI 0x00000004 -#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019 -#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT__CI__VI 0x00000008 -#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d -#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT__CI__VI 0x00000006 -#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b -#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT__CI__VI 0x00000000 -#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT__CI__VI 0x00000002 -#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT__CI__VI 0x00000003 -#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT__CI__VI 0x00000001 -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000 -#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT__CI__VI 0x00000000 -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000 -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002 -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x00000000 -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000 -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002 -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x00000000 -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000 -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000 -#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT__SI__CI 0x00000000 -#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT__CI__VI 0x00000000 -#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 -#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 -#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT__CI__VI 0x00000000 -#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT__CI__VI 0x00000002 -#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_MQD_CONTROL__MQD_ATC__SHIFT__CI__VI 0x00000017 -#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT__CI 0x0000001a -#define CP_MQD_CONTROL__PRIV_STATE__SHIFT__CI__VI 0x00000008 -#define CP_MQD_CONTROL__VMID__SHIFT__CI__VI 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000 -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000 -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000 -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000 -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000 -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000 -#define CP_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT__SI 0x00000000 -#define CP_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT__SI 0x00000000 -#define CP_PERFCOUNTER_SELECT__PERF_SEL__SHIFT__SI 0x00000000 -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a -#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT__CI__VI 0x00000004 -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT__CI__VI 0x00000000 -#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT__CI__VI 0x00000003 -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT__CI__VI 0x00000001 -#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT__CI__VI 0x00000002 -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT__CI__VI 0x00000000 -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT__CI__VI 0x00000000 -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000 -#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000 -#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT__CI__VI 0x00000000 -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001 -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000 -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018 -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010 -#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT__CI 0x0000000f -#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT__CI__VI 0x00000000 -#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 -#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 -#define CP_PIPEID__PIPE_ID__SHIFT__CI__VI 0x00000000 -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000 -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002 -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT__SI__CI 0x00000000 -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT__CI__VI 0x00000000 -#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT__CI__VI 0x0000001f -#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT__CI__VI 0x00000000 -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT__CI__VI 0x0000001e -#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x00000000 -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT__CI__VI 0x00000000 -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT__CI__VI 0x00000000 -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT__CI__VI 0x00000000 -#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT__CI__VI 0x00000002 -#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT__CI 0x00000014 -#define CP_PRT_LOD_STATS_CNTL2__MC_PRIV_MODE__SHIFT__CI 0x00000016 -#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT__CI__VI 0x00000017 -#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT__CI__VI 0x00000013 -#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT__CI__VI 0x0000000a -#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT__CI__VI 0x00000012 -#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT__CI 0x00000000 -#define CP_PWR_CNTL__TCIU_HALT__SHIFT__SI 0x00000000 -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000 -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008 -#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT__CI__VI 0x00000000 -#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000 -#define CP_RB0_CNTL__CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_RB0_CNTL__ENA_WPTR_POLL__SHIFT__SI 0x00000018 -#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f -#define CP_RB0_CNTL__RB_VOLATILE__SHIFT__CI 0x0000001a -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 -#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 -#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000 -#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000 -#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT__CI__VI 0x00000000 -#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000 -#define CP_RB1_CNTL__CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f -#define CP_RB1_CNTL__RB_VOLATILE__SHIFT__CI 0x0000001a -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 -#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 -#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000 -#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000 -#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000 -#define CP_RB2_CNTL__CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f -#define CP_RB2_CNTL__RB_VOLATILE__SHIFT__CI 0x0000001a -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 -#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 -#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000 -#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000 -#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000 -#define CP_RB_CNTL__CACHE_POLICY__SHIFT__CI__VI 0x00000018 -#define CP_RB_CNTL__ENA_WPTR_POLL__SHIFT__SI 0x00000018 -#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f -#define CP_RB_CNTL__RB_VOLATILE__SHIFT__CI 0x0000001a -#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000 -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 -#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 -#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 -#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 -#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000 -#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008 -#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010 -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 -#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT__CI 0x00000000 -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT__SI__VI 0x00000000 -#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT__CI 0x00000002 -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT__SI__VI 0x00000002 -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000 -#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 -#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000 -#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000 -#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000 -#define CP_RINGID__RINGID__SHIFT 0x00000000 -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 -#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010 -#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018 -#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000 -#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008 -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000 -#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008 -#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010 -#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000 -#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018 -#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010 -#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000 -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x00000000 -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x00000010 -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x00000000 -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x00000010 -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x00000000 -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x00000010 -#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT__CI__VI 0x00000000 -#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT__CI__VI 0x00000008 -#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000 -#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000 -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000 -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x00000000 -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT__CI__VI 0x00000000 -#define CP_SC_PSINVOC_COUNT1_HI__PSINVOC_COUNT1_HI__SHIFT__SI 0x00000000 -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT__CI__VI 0x00000000 -#define CP_SC_PSINVOC_COUNT1_LO__PSINVOC_COUNT1_LO__SHIFT__SI 0x00000000 -#define CP_SEM_INCOMPLETE_TIMER_CNTL__SIGNAL_TIMER_CNTL__SHIFT__SI 0x00000000 -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x00000000 -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0x0000000a -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0x0000000b -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x0000000d -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x0000000c -#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT__SI__CI 0x0000000e -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0x0000000f -#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT__SI__CI 0x00000010 -#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT__SI__CI 0x00000011 -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x00000000 -#define CP_STALLED_STAT1__RBIU_TO_EOPD_NOT_RDY_TO_RCV__SHIFT__SI 0x00000006 -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x00000004 -#define CP_STALLED_STAT1__RBIU_TO_PSTAT_NOT_RDY_TO_RCV__SHIFT__SI 0x00000009 -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x00000002 -#define CP_STALLED_STAT1__RBIU_TO_STRMO_NOT_RDY_TO_RCV__SHIFT__SI 0x00000008 -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT__CI__VI 0x0000001d -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT__SI 0x0000001c -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT__CI__VI 0x0000001c -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x0000001b -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x0000001a -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x00000017 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x00000018 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x00000019 -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x0000001c -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x00000019 -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x0000001a -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x0000001d -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x0000001b -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x00000015 -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x00000016 -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0x0000000b -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000010 -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0x0000000c -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0x0000000d -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0x0000000e -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x00000012 -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0x0000000f -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0x0000000a -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x00000009 -#define CP_STALLED_STAT2__PFP_HALTED_BY_INSTR_VIOLATION__SHIFT__SI 0x00000003 -#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT__SI__CI 0x00000006 -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x00000005 -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT__CI__VI 0x00000014 -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT__CI__VI 0x00000013 -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x00000001 -#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT__SI__CI 0x00000007 -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x00000002 -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x00000004 -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x00000008 -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x00000018 -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000011 -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x00000017 -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x0000001f -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x0000001e -#define CP_STALLED_STAT3__CE_HALTED_BY_INSTR_VIOLATION__SHIFT__SI 0x00000009 -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000006 -#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT__SI__CI 0x00000008 -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x00000004 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x00000001 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x00000003 -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x00000005 -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000007 -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0x0000000a -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0x0000000b -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x00000002 -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0x0000000d -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0x0000000c -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0x0000000e -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0x0000000f -#define CP_STAT__CE_BUSY__SHIFT 0x0000001a -#define CP_STAT__CPC_CPG_BUSY__SHIFT__CI__VI 0x00000019 -#define CP_STAT__CP_BUSY__SHIFT 0x0000001f -#define CP_STAT__CSF_ARBITER_BUSY__SHIFT__SI 0x00000005 -#define CP_STAT__CSF_BUSY__SHIFT__SI 0x00000006 -#define CP_STAT__CSF_INDIRECT1_BUSY__SHIFT__SI 0x00000002 -#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT__SI 0x00000003 -#define CP_STAT__CSF_RING_BUSY__SHIFT__SI 0x00000000 -#define CP_STAT__CSF_STATE_BUSY__SHIFT__SI 0x00000004 -#define CP_STAT__CSF_WPTR_POLL_BUSY__SHIFT__SI 0x00000001 -#define CP_STAT__DC_BUSY__SHIFT__CI__VI 0x0000000d -#define CP_STAT__DMA_BUSY__SHIFT 0x00000016 -#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x00000014 -#define CP_STAT__MEQ_BUSY__SHIFT 0x00000010 -#define CP_STAT__ME_BUSY__SHIFT 0x00000011 -#define CP_STAT__MIU_RDREQ_BUSY__SHIFT__SI__CI 0x00000007 -#define CP_STAT__MIU_WRREQ_BUSY__SHIFT__SI__CI 0x00000008 -#define CP_STAT__PFP_BUSY__SHIFT 0x0000000f -#define CP_STAT__QUERY_BUSY__SHIFT 0x00000012 -#define CP_STAT__RCIU_BUSY__SHIFT 0x00000017 -#define CP_STAT__ROQ_ALIGN_BUSY__SHIFT__SI 0x0000000e -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000001d -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000001e -#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x0000001c -#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0x0000000a -#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0x0000000b -#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x00000009 -#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0x0000000c -#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x00000018 -#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x00000013 -#define CP_STAT__SURFACE_PROBE_BUSY__SHIFT__SI 0x00000019 -#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x00000015 -#define CP_STAT__TCIU_BUSY__SHIFT 0x0000001b -#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x00000000 -#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x00000000 -#define CP_STQ_STAT__STQ_WPTR__SHIFT__SI 0x00000010 -#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x00000000 -#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x00000008 -#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x00000010 -#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT__CI__VI 0x00000000 -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x00000000 -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x00000002 -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT__SI__CI 0x00000000 -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x00000000 -#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x00000000 -#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x00000002 -#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x00000000 -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x00000000 -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x00000000 -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x00000000 -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x00000000 -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x00000000 -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x00000000 -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x00000000 -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x00000000 -#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT__CI__VI 0x00000000 -#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT__CI 0x00000010 -#define CP_VMID_RESET__RESET_REQUEST__SHIFT__CI__VI 0x00000000 -#define CP_VMID_RESET__RESET_STATUS__SHIFT__CI__VI 0x00000010 -#define CP_VMID__VMID__SHIFT 0x00000000 -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x00000000 -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 -#define CP_WAIT_SEM_STATUS__WAIT_PENDING__SHIFT__CI 0x00000002 -#define CP_WAIT_SEM_STATUS__WAIT_STATUS__SHIFT__CI 0x00000000 -#define CRT00__H_TOTAL__SHIFT__SI 0x00000000 -#define CRT01__H_DISP_END__SHIFT__SI 0x00000000 -#define CRT02__H_BLANK_START__SHIFT__SI 0x00000000 -#define CRT03__CR10CR11_R_DIS_B__SHIFT__SI 0x00000007 -#define CRT03__H_BLANK_END__SHIFT__SI 0x00000000 -#define CRT03__H_DE_SKEW__SHIFT__SI 0x00000005 -#define CRT04__H_SYNC_START__SHIFT__SI 0x00000000 -#define CRT05__H_BLANK_END_B5__SHIFT__SI 0x00000007 -#define CRT05__H_SYNC_END__SHIFT__SI 0x00000000 -#define CRT05__H_SYNC_SKEW__SHIFT__SI 0x00000005 -#define CRT06__V_TOTAL__SHIFT__SI 0x00000000 -#define CRT07__LINE_CMP_B8__SHIFT__SI 0x00000004 -#define CRT07__V_BLANK_START_B8__SHIFT__SI 0x00000003 -#define CRT07__V_DISP_END_B8__SHIFT__SI 0x00000001 -#define CRT07__V_DISP_END_B9__SHIFT__SI 0x00000006 -#define CRT07__V_SYNC_START_B8__SHIFT__SI 0x00000002 -#define CRT07__V_SYNC_START_B9__SHIFT__SI 0x00000007 -#define CRT07__V_TOTAL_B8__SHIFT__SI 0x00000000 -#define CRT07__V_TOTAL_B9__SHIFT__SI 0x00000005 -#define CRT08__BYTE_PAN__SHIFT__SI 0x00000005 -#define CRT08__ROW_SCAN_START__SHIFT__SI 0x00000000 -#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT__SI 0x00000007 -#define CRT09__LINE_CMP_B9__SHIFT__SI 0x00000006 -#define CRT09__MAX_ROW_SCAN__SHIFT__SI 0x00000000 -#define CRT09__V_BLANK_START_B9__SHIFT__SI 0x00000005 -#define CRT0A__CURSOR_DISABLE__SHIFT__SI 0x00000005 -#define CRT0A__CURSOR_START__SHIFT__SI 0x00000000 -#define CRT0B__CURSOR_END__SHIFT__SI 0x00000000 -#define CRT0B__CURSOR_SKEW__SHIFT__SI 0x00000005 -#define CRT0C__DISP_START__SHIFT__SI 0x00000000 -#define CRT0D__DISP_START__SHIFT__SI 0x00000000 -#define CRT0E__CURSOR_LOC_HI__SHIFT__SI 0x00000000 -#define CRT0F__CURSOR_LOC_LO__SHIFT__SI 0x00000000 -#define CRT10__V_SYNC_START__SHIFT__SI 0x00000000 -#define CRT11__C0T7_WR_ONLY__SHIFT__SI 0x00000007 -#define CRT11__SEL5_REFRESH_CYC__SHIFT__SI 0x00000006 -#define CRT11__V_INTR_CLR__SHIFT__SI 0x00000004 -#define CRT11__V_INTR_EN__SHIFT__SI 0x00000005 -#define CRT11__V_SYNC_END__SHIFT__SI 0x00000000 -#define CRT12__V_DISP_END__SHIFT__SI 0x00000000 -#define CRT13__DISP_PITCH__SHIFT__SI 0x00000000 -#define CRT14__ADDR_CNT_BY4__SHIFT__SI 0x00000005 -#define CRT14__DOUBLE_WORD__SHIFT__SI 0x00000006 -#define CRT14__UNDRLN_LOC__SHIFT__SI 0x00000000 -#define CRT15__V_BLANK_START__SHIFT__SI 0x00000000 -#define CRT16__V_BLANK_END__SHIFT__SI 0x00000000 -#define CRT17__ADDR_CNT_BY2__SHIFT__SI 0x00000003 -#define CRT17__BYTE_MODE__SHIFT__SI 0x00000006 -#define CRT17__CRTC_SYNC_EN__SHIFT__SI 0x00000007 -#define CRT17__RA0_AS_A13B__SHIFT__SI 0x00000000 -#define CRT17__RA1_AS_A14B__SHIFT__SI 0x00000001 -#define CRT17__VCOUNT_BY2__SHIFT__SI 0x00000002 -#define CRT17__WRAP_A15TOA0__SHIFT__SI 0x00000005 -#define CRT18__LINE_CMP__SHIFT__SI 0x00000000 -#define CRT1E__GRPH_DEC_RD1__SHIFT__SI 0x00000001 -#define CRT1F__GRPH_DEC_RD0__SHIFT__SI 0x00000000 -#define CRT22__GRPH_LATCH_DATA__SHIFT__SI 0x00000000 -#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT__SI 0x00000000 -#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT__SI 0x00000001 -#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT__SI 0x00000000 -#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT__SI 0x00000001 -#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT__SI 0x00000000 -#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT__SI 0x00000001 -#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT__SI 0x00000000 -#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT__SI 0x00000001 -#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT__SI 0x00000000 -#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT__SI 0x00000001 -#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT__SI 0x00000000 -#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT__SI 0x00000001 -#define CRTC8_DATA__VCRTC_DATA__SHIFT__SI 0x00000000 -#define CRTC8_IDX__VCRTC_IDX__SHIFT__SI 0x00000000 -#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT__SI 0x00000000 -#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT__SI 0x00000010 -#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT__SI 0x00000000 -#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT__SI 0x0000000a -#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT__SI 0x00000014 -#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT__SI 0x00000008 -#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT__SI 0x00000010 -#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT__SI 0x00000000 -#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT__SI 0x00000000 -#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT__SI 0x0000000a -#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT__SI 0x00000014 -#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT__SI 0x00000010 -#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT__SI 0x00000008 -#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT__SI 0x00000018 -#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT__SI 0x0000000d -#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT__SI 0x00000014 -#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT__SI 0x00000000 -#define CRTC_CONTROL__CRTC_PREFETCH_EN__SHIFT__SI 0x0000001c -#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT__SI 0x0000001d -#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT__SI 0x0000000c -#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT__SI 0x00000004 -#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT__SI 0x00000000 -#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT__SI 0x00000001 -#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_01__ID48_CRTC_BLANK__SHIFT__SI 0x0000001b -#define CRTC_DEBUG_01__ID48_CRTC_DATA_ACTIVE__SHIFT__SI 0x0000001a -#define CRTC_DEBUG_01__ID48_CRTC_FREEZE__SHIFT__SI 0x0000001d -#define CRTC_DEBUG_01__ID48_CRTC_HSYNC_A__SHIFT__SI 0x00000018 -#define CRTC_DEBUG_01__ID48_CRTC_HSYNC_B__SHIFT__SI 0x0000001e -#define CRTC_DEBUG_01__ID48_CRTC_H_COUNT__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_01__ID48_CRTC_STEREOSYNC__SHIFT__SI 0x0000001c -#define CRTC_DEBUG_01__ID48_CRTC_VSYNC_A__SHIFT__SI 0x00000019 -#define CRTC_DEBUG_01__ID48_CRTC_VSYNC_B__SHIFT__SI 0x0000001f -#define CRTC_DEBUG_01__ID48_CRTC_V_COUNT__SHIFT__SI 0x0000000c -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_EOL__SHIFT__SI 0x0000000e -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_HALF_H_TOTAL__SHIFT__SI 0x00000010 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_HTOTAL_BY_8__SHIFT__SI 0x00000011 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_ACTIVE_END__SHIFT__SI 0x0000000a -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_ACTIVE_START__SHIFT__SI 0x00000009 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_BLANK_END__SHIFT__SI 0x00000007 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_BLANK_START__SHIFT__SI 0x00000006 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_CAPTURESTART_A__SHIFT__SI 0x0000000c -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_CAPTURESTART_B__SHIFT__SI 0x0000000d -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_A_END__SHIFT__SI 0x00000001 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_A_START__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_B_END__SHIFT__SI 0x00000004 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_SYNC_B_START__SHIFT__SI 0x00000003 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_H_TV_FRAMESTART__SHIFT__SI 0x00000012 -#define CRTC_DEBUG_02__ID49_CRTC_EVENT_SOL__SHIFT__SI 0x0000000f -#define CRTC_DEBUG_02__ID49_CRTC_H_ACTIVE__SHIFT__SI 0x0000000b -#define CRTC_DEBUG_02__ID49_CRTC_H_BLANK__SHIFT__SI 0x00000008 -#define CRTC_DEBUG_02__ID49_CRTC_H_COUNT_ADV_EN__SHIFT__SI 0x00000013 -#define CRTC_DEBUG_02__ID49_CRTC_H_COUNT__SHIFT__SI 0x00000014 -#define CRTC_DEBUG_02__ID49_CRTC_H_SYNC_A__SHIFT__SI 0x00000002 -#define CRTC_DEBUG_02__ID49_CRTC_H_SYNC_B__SHIFT__SI 0x00000005 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_END_LINE__SHIFT__SI 0x00000011 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_HALF_H_TOTAL__SHIFT__SI 0x00000003 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_START_LINE__SHIFT__SI 0x00000010 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_ACTIVE_END__SHIFT__SI 0x00000009 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_ACTIVE_START__SHIFT__SI 0x00000008 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_BLANK_END__SHIFT__SI 0x00000006 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_BLANK_START__SHIFT__SI 0x00000005 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_CAPTURESTART_A__SHIFT__SI 0x0000000b -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_CAPTURESTART_B__SHIFT__SI 0x0000000f -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_A_END__SHIFT__SI 0x00000001 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_A_START__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_B_END__SHIFT__SI 0x0000000d -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_SYNC_B_START__SHIFT__SI 0x0000000c -#define CRTC_DEBUG_03__ID4A_CRTC_EVENT_V_TV_FRAMESTART__SHIFT__SI 0x00000012 -#define CRTC_DEBUG_03__ID4A_CRTC_FIELD_NUMBER_EARLY__SHIFT__SI 0x00000002 -#define CRTC_DEBUG_03__ID4A_CRTC_V_ACTIVE__SHIFT__SI 0x0000000a -#define CRTC_DEBUG_03__ID4A_CRTC_V_BLANK__SHIFT__SI 0x00000007 -#define CRTC_DEBUG_03__ID4A_CRTC_V_COUNT__SHIFT__SI 0x00000014 -#define CRTC_DEBUG_03__ID4A_CRTC_V_SYNC_A__SHIFT__SI 0x00000004 -#define CRTC_DEBUG_03__ID4A_CRTC_V_SYNC_B__SHIFT__SI 0x0000000e -#define CRTC_DEBUG_03__ID4A_CRTC_V_UPDATE__SHIFT__SI 0x00000013 -#define CRTC_DEBUG_04__ID4B_CRTC_BLANK_EN__SHIFT__SI 0x00000017 -#define CRTC_DEBUG_04__ID4B_CRTC_BLANK__SHIFT__SI 0x0000001b -#define CRTC_DEBUG_04__ID4B_CRTC_CRTC_EN__SHIFT__SI 0x0000000c -#define CRTC_DEBUG_04__ID4B_CRTC_DATA_ACTIVE__SHIFT__SI 0x0000001e -#define CRTC_DEBUG_04__ID4B_CRTC_EVENT_HALF_H_TOTAL__SHIFT__SI 0x00000002 -#define CRTC_DEBUG_04__ID4B_CRTC_EVENT_V_BLANK_START__SHIFT__SI 0x00000004 -#define CRTC_DEBUG_04__ID4B_CRTC_EVENT_V_TOTAL__SHIFT__SI 0x00000003 -#define CRTC_DEBUG_04__ID4B_CRTC_FIELD_NUMBER_EARLY__SHIFT__SI 0x0000000f -#define CRTC_DEBUG_04__ID4B_CRTC_FIELD_NUMBER__SHIFT__SI 0x00000010 -#define CRTC_DEBUG_04__ID4B_CRTC_FORCE_NEXT_FIELD_EVEN__SHIFT__SI 0x0000000e -#define CRTC_DEBUG_04__ID4B_CRTC_FORCE_NEXT_FIELD_ODD__SHIFT__SI 0x0000000d -#define CRTC_DEBUG_04__ID4B_CRTC_FREEZE__SHIFT__SI 0x00000018 -#define CRTC_DEBUG_04__ID4B_CRTC_H_BLANK__SHIFT__SI 0x00000019 -#define CRTC_DEBUG_04__ID4B_CRTC_H_DATA_ACTIVE__SHIFT__SI 0x0000001c -#define CRTC_DEBUG_04__ID4B_CRTC_H_TV_FRAMESTART__SHIFT__SI 0x00000014 -#define CRTC_DEBUG_04__ID4B_CRTC_H_UPDATE_EVENT__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_04__ID4B_CRTC_INTERLACE_SELECT__SHIFT__SI 0x00000011 -#define CRTC_DEBUG_04__ID4B_CRTC_READ_REQUEST__SHIFT__SI 0x0000001f -#define CRTC_DEBUG_04__ID4B_CRTC_STEREOSYNC_OUTPUT__SHIFT__SI 0x00000009 -#define CRTC_DEBUG_04__ID4B_CRTC_STEREOSYNC_SELECT__SHIFT__SI 0x00000008 -#define CRTC_DEBUG_04__ID4B_CRTC_STEREO_CURRENT_EYE__SHIFT__SI 0x0000000a -#define CRTC_DEBUG_04__ID4B_CRTC_TV_FRAMESTART_FREQ_COUNT__SHIFT__SI 0x00000012 -#define CRTC_DEBUG_04__ID4B_CRTC_TV_FRAMESTART__SHIFT__SI 0x00000016 -#define CRTC_DEBUG_04__ID4B_CRTC_V_BLANK__SHIFT__SI 0x0000001a -#define CRTC_DEBUG_04__ID4B_CRTC_V_DATA_ACTIVE__SHIFT__SI 0x0000001d -#define CRTC_DEBUG_04__ID4B_CRTC_V_TV_FRAMESTART__SHIFT__SI 0x00000015 -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_EVENT__SHIFT__SI 0x00000001 -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_MODE_1__SHIFT__SI 0x00000005 -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_MODE_2__SHIFT__SI 0x00000006 -#define CRTC_DEBUG_04__ID4B_CRTC_V_UPDATE_MODE_3__SHIFT__SI 0x00000007 -#define CRTC_DEBUG_05__ID4C_CRTC_BLANK_DATA_EN_UPDATE_ENABLE__SHIFT__SI 0x0000001b -#define CRTC_DEBUG_05__ID4C_CRTC_BLANK_EN__SHIFT__SI 0x0000001c -#define CRTC_DEBUG_05__ID4C_CRTC_CRTCREGS_DISP_READ_REQUEST_DIS__SHIFT__SI 0x0000001d -#define CRTC_DEBUG_05__ID4C_CRTC_CRTC_EN__SHIFT__SI 0x00000016 -#define CRTC_DEBUG_05__ID4C_CRTC_CURRENT_CRTC_STATE__SHIFT__SI 0x00000014 -#define CRTC_DEBUG_05__ID4C_CRTC_CURRENT_STATE_SM_PCLK__SHIFT__SI 0x00000009 -#define CRTC_DEBUG_05__ID4C_CRTC_CURRENT_STATE_SM_SCLK__SHIFT__SI 0x0000000a -#define CRTC_DEBUG_05__ID4C_CRTC_DISP_READ_REQUEST_DIS__SHIFT__SI 0x0000001e -#define CRTC_DEBUG_05__ID4C_CRTC_EVENT_H_SYNC_A_START__SHIFT__SI 0x00000018 -#define CRTC_DEBUG_05__ID4C_CRTC_EVENT_V_BLANK_START__SHIFT__SI 0x00000019 -#define CRTC_DEBUG_05__ID4C_CRTC_EXTEND_CRTC_EN__SHIFT__SI 0x00000017 -#define CRTC_DEBUG_05__ID4C_CRTC_H_SYNC_A_POL__SHIFT__SI 0x0000000f -#define CRTC_DEBUG_05__ID4C_CRTC_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000011 -#define CRTC_DEBUG_05__ID4C_CRTC_RESET_SM_SCLK__SHIFT__SI 0x00000002 -#define CRTC_DEBUG_05__ID4C_CRTC_SYNC_POLARITY_SEL__SHIFT__SI 0x0000000e -#define CRTC_DEBUG_05__ID4C_CRTC_TIMING_SEL__SHIFT__SI 0x00000012 -#define CRTC_DEBUG_05__ID4C_CRTC_TOP_OVERSCAN_ODD__SHIFT__SI 0x0000000c -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_DONE__SHIFT__SI 0x00000003 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_ENABLE_PCLK__SHIFT__SI 0x00000008 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_ENABLE_SCLK__SHIFT__SI 0x00000005 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_ENABLE__SHIFT__SI 0x00000013 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_EVENT__SHIFT__SI 0x00000007 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_INSTANTLY__SHIFT__SI 0x00000006 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_LOCK_ORED__SHIFT__SI 0x00000001 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_PENDING__SHIFT__SI 0x00000004 -#define CRTC_DEBUG_05__ID4C_CRTC_UPDATE_VGA_CUR_BUF__SHIFT__SI 0x0000001a -#define CRTC_DEBUG_05__ID4C_CRTC_V_SYNC_A_POL__SHIFT__SI 0x00000010 -#define CRTC_DEBUG_05__ID4C_CRTC_V_SYNC_A_SEL__SHIFT__SI 0x0000000d -#define CRTC_DEBUG_05__ID4C_CRTC_V_UPDATE__SHIFT__SI 0x0000001f -#define CRTC_DEBUG_05__ID4C_CRTC_WTRIG_ORED__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_06__ID4D_CRTC_AUTO_FORCE_VSYNC_NEXT_LINE__SHIFT__SI 0x0000000f -#define CRTC_DEBUG_06__ID4D_CRTC_FIELD_NUMBER_EARLY__SHIFT__SI 0x0000001f -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_PCLK__SHIFT__SI 0x0000000e -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_SCLK__SHIFT__SI 0x00000007 -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT__SI 0x00000011 -#define CRTC_DEBUG_06__ID4D_CRTC_FORCE_VSYNC_NEXT_LINE__SHIFT__SI 0x00000010 -#define CRTC_DEBUG_06__ID4D_CRTC_FRAME_COUNT__SHIFT__SI 0x00000009 -#define CRTC_DEBUG_06__ID4D_CRTC_H_SYNC_A__SHIFT__SI 0x00000012 -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN_PCLK__SHIFT__SI 0x0000001a -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN_SCLK__SHIFT__SI 0x00000019 -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD_PCLK__SHIFT__SI 0x00000018 -#define CRTC_DEBUG_06__ID4D_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD_SCLK__SHIFT__SI 0x00000008 -#define CRTC_DEBUG_06__ID4D_CRTC_LATCH_IN_COUNT__SHIFT__SI 0x0000001c -#define CRTC_DEBUG_06__ID4D_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_PCLK__SHIFT__SI 0x0000000d -#define CRTC_DEBUG_06__ID4D_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_SCLK__SHIFT__SI 0x0000000c -#define CRTC_DEBUG_06__ID4D_CRTC_RBBMIF_READ_READY__SHIFT__SI 0x0000001e -#define CRTC_DEBUG_06__ID4D_CRTC_READ_READY_COUNT__SHIFT__SI 0x0000001d -#define CRTC_DEBUG_06__ID4D_CRTC_RESET_FRAME_COUNT_PCLK__SHIFT__SI 0x00000005 -#define CRTC_DEBUG_06__ID4D_CRTC_RESET_FRAME_COUNT_SCLK__SHIFT__SI 0x00000004 -#define CRTC_DEBUG_06__ID4D_CRTC_RTRIG_PRE_COUNT__SHIFT__SI 0x0000001b -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_CLEAR_PCLK__SHIFT__SI 0x00000003 -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_CLEAR_SCLK__SHIFT__SI 0x00000002 -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_MANUAL_TRIGGER_PCLK__SHIFT__SI 0x00000001 -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_MANUAL_TRIGGER_SCLK__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_06__ID4D_CRTC_SNAPSHOT_OCCURRED__SHIFT__SI 0x00000006 -#define CRTC_DEBUG_06__ID4D_CRTC_V_COUNT__SHIFT__SI 0x00000014 -#define CRTC_DEBUG_06__ID4D_CRTC_V_SYNC_A__SHIFT__SI 0x00000013 -#define CRTC_DEBUG_07__ID55_CRTC_VTOTAL_MAX__SHIFT__SI 0x0000000d -#define CRTC_DEBUG_07__ID55_CRTC_VTOTAL_MIN__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_08__ID56_CRTC_FBC_SURFACE_INV_EVENT__SHIFT__SI 0x00000008 -#define CRTC_DEBUG_08__ID56_CRTC_LOCK_VCOUNT_ON_EVENT__SHIFT__SI 0x00000005 -#define CRTC_DEBUG_08__ID56_CRTC_LOCK_VCOUNT_ON_VSYNC__SHIFT__SI 0x00000004 -#define CRTC_DEBUG_08__ID56_CRTC_MC_HIT_REGION_EVENT__SHIFT__SI 0x00000007 -#define CRTC_DEBUG_08__ID56_CRTC_MC_MEM_WRITE_EVENT__SHIFT__SI 0x00000006 -#define CRTC_DEBUG_08__ID56_CRTC_VSYNC_NOM_INT__SHIFT__SI 0x0000000a -#define CRTC_DEBUG_08__ID56_CRTC_VSYNC_NOM__SHIFT__SI 0x00000009 -#define CRTC_DEBUG_08__ID56_CRTC_VTOTAL_MIN_EVENT_INT__SHIFT__SI 0x00000003 -#define CRTC_DEBUG_08__ID56_CRTC_VTOTAL_MIN_EVENT__SHIFT__SI 0x00000002 -#define CRTC_DEBUG_08__ID56_CRTC_VTOTAL_TRIG_OCCURED__SHIFT__SI 0x00000001 -#define CRTC_DEBUG_08__ID56_CRTC_V_TOTAL_MIN_TRIG__SHIFT__SI 0x00000000 -#define CRTC_DEBUG_BITS__CRTC_DEBUG_BITS__SHIFT__SI 0x00000000 -#define CRTC_DEBUG__ID4E_CRTC_FORCE_H_COUNT__SHIFT__SI 0x0000001e -#define CRTC_DEBUG__ID4E_CRTC_FORCE_V_COUNT__SHIFT__SI 0x0000000f -#define CRTC_DEBUG__ID4E_CRTC_H_COUNT__SHIFT__SI 0x00000016 -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_DELAY_COUNT__SHIFT__SI 0x00000006 -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_FALLING_EDGE__SHIFT__SI 0x00000003 -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_FREQUENCY_COUNT__SHIFT__SI 0x00000004 -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A_RISING_EDGE__SHIFT__SI 0x00000002 -#define CRTC_DEBUG__ID4E_CRTC_TRIG_A__SHIFT__SI 0x00000000 -#define CRTC_DEBUG__ID4E_CRTC_TRIG_B__SHIFT__SI 0x00000001 -#define CRTC_DEBUG__ID4E_CRTC_V_COUNT__SHIFT__SI 0x00000010 -#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT__SI 0x00000010 -#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT__SI 0x00000008 -#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_BLANK__SHIFT__SI 0x00000001 -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_ACTIVE__SHIFT__SI 0x00000000 -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_B__SHIFT__SI 0x00000016 -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_G__SHIFT__SI 0x0000000c -#define CRTC_DOUT_INTERFACE_01__ID43_CRTC_DOUT_DATA_R__SHIFT__SI 0x00000002 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_BLANK__SHIFT__SI 0x00000004 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_CAPTURESTART_A__SHIFT__SI 0x00000002 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_CAPTURESTART_B__SHIFT__SI 0x0000000a -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_DATA_ACTIVE__SHIFT__SI 0x00000003 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_FIELD_NUMBER__SHIFT__SI 0x00000006 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_FREEZE__SHIFT__SI 0x00000007 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_HSYNC_A__SHIFT__SI 0x00000000 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_HSYNC_B__SHIFT__SI 0x00000008 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_STEREOSYNC__SHIFT__SI 0x00000005 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_VSYNC_A__SHIFT__SI 0x00000001 -#define CRTC_DOUT_INTERFACE_02__ID45_CRTC_DOUT_VSYNC_B__SHIFT__SI 0x00000009 -#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT__SI 0x00000001 -#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT__SI 0x00000000 -#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT__SI 0x00000010 -#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT__SI 0x00000000 -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT__SI 0x00000010 -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT__SI 0x00000018 -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT__SI 0x00000008 -#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT__SI 0x00000000 -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT__SI 0x00000018 -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT__SI 0x00000000 -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT__SI 0x00000010 -#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT__SI 0x00000008 -#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT__SI 0x00000010 -#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT__SI 0x00000000 -#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT__SI 0x00000010 -#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT__SI 0x00000011 -#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT__SI 0x00000000 -#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT__SI 0x00000010 -#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT__SI 0x00000000 -#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT__SI 0x00000010 -#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT__SI 0x00000011 -#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT__SI 0x00000000 -#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT__SI 0x00000010 -#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT__SI 0x00000000 -#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT__SI 0x00000000 -#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT__SI 0x00000000 -#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT__SI 0x00000010 -#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT__SI 0x00000000 -#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT__SI 0x00000001 -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT__SI 0x00000008 -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT__SI 0x00000009 -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT__SI 0x00000010 -#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT__SI 0x00000011 -#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT__SI 0x00000000 -#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT__SI 0x00000001 -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT__SI 0x00000018 -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT__SI 0x0000001a -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT__SI 0x00000019 -#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT__SI 0x0000001b -#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT__SI 0x0000001c -#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT__SI 0x0000001d -#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT__SI 0x00000004 -#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT__SI 0x00000005 -#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT__SI 0x00000000 -#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT__SI 0x00000000 -#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT__SI \ - 0x00000000 -#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT__SI 0x00000008 -#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT__SI 0x00000000 -#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT__SI 0x00000014 -#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT__SI 0x00000004 -#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT__SI 0x00000010 -#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT__SI 0x00000000 -#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT__SI 0x00000000 -#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT__SI 0x00000000 -#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT__SI 0x0000000a -#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT__SI 0x00000014 -#define CRTC_PIXCLK_DTO_MODULO__CRTC_PIXCLK_DTO_MODULO__SHIFT__SI 0x00000000 -#define CRTC_PIXCLK_DTO_PHASE__CRTC_PIXCLK_DTO_PHASE__SHIFT__SI 0x00000000 -#define CRTC_PIXEL_DATA_READBACK__CRTC_PIXEL_DATA_BLUE_CB__SHIFT__SI 0x00000000 -#define CRTC_PIXEL_DATA_READBACK__CRTC_PIXEL_DATA_GREEN_Y__SHIFT__SI 0x0000000a -#define CRTC_PIXEL_DATA_READBACK__CRTC_PIXEL_DATA_RED_CR__SHIFT__SI 0x00000014 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_END_LINE__SHIFT__SI 0x00000004 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_EOL__SHIFT__SI 0x00000003 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_HTOTAL_BY_8__SHIFT__SI 0x00000007 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_INTERLACE_SELECT__SHIFT__SI 0x00000008 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_READ_REQUEST_DIS__SHIFT__SI 0x00000000 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_READ_REQUEST__SHIFT__SI 0x00000001 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_SOL__SHIFT__SI 0x00000005 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_START_LINE__SHIFT__SI 0x00000002 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_STEREO_SELECT__SHIFT__SI 0x00000009 -#define CRTC_SCL_INTERFACE__ID42_CRTC_SCL_V_UPDATE__SHIFT__SI 0x00000006 -#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT__SI 0x00000000 -#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT__SI 0x00000000 -#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT__SI 0x00000010 -#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT__SI 0x00000000 -#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT__SI 0x00000001 -#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT__SI 0x00000002 -#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT__SI 0x00000000 -#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT__SI 0x00000008 -#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT__SI 0x00000000 -#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT__SI 0x00000000 -#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT__SI 0x00000000 -#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT__SI 0x00000010 -#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT__SI 0x00000000 -#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT__SI 0x00000000 -#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT__SI 0x00000011 -#define CRTC_STATUS__CRTC_H_BLANK__SHIFT__SI 0x00000010 -#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT__SI 0x00000012 -#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT__SI 0x00000001 -#define CRTC_STATUS__CRTC_V_BLANK__SHIFT__SI 0x00000000 -#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT__SI 0x00000004 -#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT__SI 0x00000002 -#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT__SI 0x00000003 -#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT__SI 0x00000018 -#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT__SI 0x00000008 -#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT__SI 0x00000010 -#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT__SI 0x00000000 -#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT__SI 0x00000000 -#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT__SI 0x00000018 -#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT__SI 0x00000008 -#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT__SI 0x00000010 -#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT__SI 0x00000000 -#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT__SI 0x00000010 -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT__SI 0x00000018 -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT__SI 0x00000010 -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT__SI 0x00000000 -#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT__SI 0x00000008 -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT__SI 0x0000000c -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT__SI 0x00000000 -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT__SI 0x00000004 -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT__SI 0x00000010 -#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT__SI 0x00000008 -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT__SI 0x0000001f -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT__SI 0x00000018 -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT__SI 0x00000010 -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT__SI 0x00000014 -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT__SI 0x00000009 -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT__SI 0x0000000b -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT__SI 0x00000004 -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT__SI 0x0000000a -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT__SI 0x00000008 -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT__SI 0x0000000c -#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT__SI 0x00000000 -#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT__SI 0x00000000 -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT__SI 0x0000001f -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT__SI 0x00000018 -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT__SI 0x00000010 -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT__SI 0x00000014 -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT__SI 0x00000009 -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT__SI 0x0000000b -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT__SI 0x00000004 -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT__SI 0x0000000a -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT__SI 0x00000008 -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT__SI 0x0000000c -#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT__SI 0x00000000 -#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT__SI 0x00000000 -#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT__SI 0x00000000 -#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT__SI 0x00000010 -#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT__SI 0x00000000 -#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT__SI 0x00000010 -#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT__SI 0x00000008 -#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT__SI 0x00000000 -#define CRTC_VGA_INTERFACE__ID46_CRTC_VGA_CUR_BUF__SHIFT__SI 0x00000008 -#define CRTC_VGA_INTERFACE__ID46_CRTC_VGA_NODISPLAY__SHIFT__SI 0x0000000a -#define CRTC_VGA_INTERFACE__ID46_CRTC_VGA_RENDER_SYNC__SHIFT__SI 0x00000009 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_BUF_CNTL__SHIFT__SI 0x00000007 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_CRTC_EN__SHIFT__SI 0x00000000 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_DISP_EN__SHIFT__SI 0x00000001 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_MODE_EN__SHIFT__SI 0x00000002 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000004 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_SYNC_POLARITY_SEL__SHIFT__SI 0x00000005 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_TIMING_SEL__SHIFT__SI 0x00000003 -#define CRTC_VGA_INTERFACE__ID46_VGA_CRTC_V_SYNC_SEL__SHIFT__SI 0x00000006 -#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT__SI 0x00000000 -#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT__SI 0x00000004 -#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT__SI 0x00000000 -#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT__SI 0x00000010 -#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT__SI 0x00000000 -#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT__SI 0x00000000 -#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT__SI 0x00000010 -#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT__SI 0x00000000 -#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT__SI 0x00000000 -#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT__SI 0x00000010 -#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT__SI 0x00000000 -#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT__SI 0x00000008 -#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT__SI 0x0000000c -#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT__SI 0x00000010 -#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT__SI 0x00000004 -#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT__SI 0x00000000 -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT__SI 0x00000008 -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT__SI 0x00000004 -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT__SI 0x0000000c -#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT__SI 0x00000000 -#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT__SI 0x00000000 -#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT__SI 0x00000000 -#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT__SI 0x00000000 -#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT__SI 0x00000008 -#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT__SI 0x00000000 -#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT__CI__VI 0x00000000 -#define CSPRIV_CONNECT__QUEUE_ID__SHIFT__CI__VI 0x00000015 -#define CSPRIV_CONNECT__UNORD_DISP__SHIFT__CI__VI 0x0000001f -#define CSPRIV_CONNECT__VMID__SHIFT__CI__VI 0x0000001a -#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT__CI__VI 0x00000000 -#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT__CI__VI 0x00000000 -#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT__CI__VI 0x00000000 -#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT__CI__VI 0x00000000 -#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT__CI__VI 0x0000001c -#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT__CI__VI 0x0000001b -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT__CI__VI 0x00000018 -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT__CI__VI 0x00000019 -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT__CI__VI 0x0000001a -#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT__CI__VI 0x0000000c -#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT__CI__VI 0x00000000 -#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 -#define CURRENT_PG_STATUS__ACP_PG_status__SHIFT__CI__VI 0x00000000 -#define CURRENT_PG_STATUS__CHUB_PG_status__SHIFT__CI__VI 0x0000000c -#define CURRENT_PG_STATUS__DC_pipe0_PG_status__SHIFT__CI__VI 0x00000005 -#define CURRENT_PG_STATUS__DC_pipe1_PG_status__SHIFT__CI__VI 0x00000006 -#define CURRENT_PG_STATUS__DC_pipe2_PG_status__SHIFT__CI__VI 0x00000007 -#define CURRENT_PG_STATUS__DC_pipe3_PG_status__SHIFT__CI__VI 0x00000008 -#define CURRENT_PG_STATUS__DC_pipe4_PG_status__SHIFT__CI__VI 0x00000009 -#define CURRENT_PG_STATUS__DC_pipe5_PG_status__SHIFT__CI__VI 0x0000000a -#define CURRENT_PG_STATUS__IOMMU_PG_status__SHIFT__CI__VI 0x0000000b -#define CURRENT_PG_STATUS__MC_PG_status__SHIFT__CI__VI 0x0000000d -#define CURRENT_PG_STATUS__PCIE_PG_status__SHIFT__CI__VI 0x00000004 -#define CURRENT_PG_STATUS__SAM_PG_status__SHIFT__CI__VI 0x00000003 -#define CURRENT_PG_STATUS__SDMA_PG_status__SHIFT__CI__VI 0x0000000e -#define CURRENT_PG_STATUS__UVD_PG_status__SHIFT__CI__VI 0x00000002 -#define CURRENT_PG_STATUS__VCE_PG_status__SHIFT__CI__VI 0x00000001 -#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT__SI 0x00000000 -#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT__SI 0x00000008 -#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT__SI 0x00000010 -#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT__SI 0x00000000 -#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT__SI 0x00000008 -#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT__SI 0x00000010 -#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT__SI 0x00000010 -#define CUR_CONTROL__CURSOR_EN__SHIFT__SI 0x00000000 -#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT__SI 0x00000014 -#define CUR_CONTROL__CURSOR_MODE__SHIFT__SI 0x00000008 -#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT__SI 0x00000010 -#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT__SI 0x00000000 -#define CUR_POSITION__CURSOR_X_POSITION__SHIFT__SI 0x00000010 -#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT__SI 0x00000000 -#define CUR_SIZE__CURSOR_HEIGHT__SHIFT__SI 0x00000000 -#define CUR_SIZE__CURSOR_WIDTH__SHIFT__SI 0x00000010 -#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT__SI 0x00000000 -#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT__SI 0x00000000 -#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT__SI 0x00000018 -#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT__SI 0x00000010 -#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT__SI 0x00000001 -#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT__SI 0x00000000 -#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000010 -#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT__SI 0x00000018 -#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT__SI 0x00000009 -#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT__SI 0x00000008 -#define D1_PROTECTION__D1_DP_ENC_REQUIRED__SHIFT__SI 0x00000001 -#define D1_PROTECTION__D1_NO_DVO_OUT__SHIFT__SI 0x00000002 -#define D1_PROTECTION__D1_NO_LVDS_OUT__SHIFT__SI 0x00000004 -#define D1_PROTECTION__D1_NO_SDVO_OUT__SHIFT__SI 0x00000003 -#define D1_PROTECTION__D1_NO_VGA_OUT__SHIFT__SI 0x00000005 -#define D1_PROTECTION__D1_TMDS_ENC_REQUIRED__SHIFT__SI 0x00000000 -#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT__SI 0x00000000 -#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000010 -#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT__SI 0x00000018 -#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT__SI 0x00000009 -#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT__SI 0x00000008 -#define D2_PROTECTION__D2_DP_ENC_REQUIRED__SHIFT__SI 0x00000001 -#define D2_PROTECTION__D2_NO_DVO_OUT__SHIFT__SI 0x00000002 -#define D2_PROTECTION__D2_NO_LVDS_OUT__SHIFT__SI 0x00000004 -#define D2_PROTECTION__D2_NO_SDVO_OUT__SHIFT__SI 0x00000003 -#define D2_PROTECTION__D2_NO_VGA_OUT__SHIFT__SI 0x00000005 -#define D2_PROTECTION__D2_TMDS_ENC_REQUIRED__SHIFT__SI 0x00000000 -#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT__SI 0x00000000 -#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000010 -#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT__SI 0x00000018 -#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT__SI 0x00000009 -#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT__SI 0x00000008 -#define D3_PROTECTION__D3_DP_ENC_REQUIRED__SHIFT__SI 0x00000001 -#define D3_PROTECTION__D3_NO_DVO_OUT__SHIFT__SI 0x00000002 -#define D3_PROTECTION__D3_NO_LVDS_OUT__SHIFT__SI 0x00000004 -#define D3_PROTECTION__D3_NO_SDVO_OUT__SHIFT__SI 0x00000003 -#define D3_PROTECTION__D3_NO_VGA_OUT__SHIFT__SI 0x00000005 -#define D3_PROTECTION__D3_TMDS_ENC_REQUIRED__SHIFT__SI 0x00000000 -#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT__SI 0x00000000 -#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000010 -#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT__SI 0x00000018 -#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT__SI 0x00000009 -#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT__SI 0x00000008 -#define D4_PROTECTION__D4_DP_ENC_REQUIRED__SHIFT__SI 0x00000001 -#define D4_PROTECTION__D4_NO_DVO_OUT__SHIFT__SI 0x00000002 -#define D4_PROTECTION__D4_NO_LVDS_OUT__SHIFT__SI 0x00000004 -#define D4_PROTECTION__D4_NO_SDVO_OUT__SHIFT__SI 0x00000003 -#define D4_PROTECTION__D4_NO_VGA_OUT__SHIFT__SI 0x00000005 -#define D4_PROTECTION__D4_TMDS_ENC_REQUIRED__SHIFT__SI 0x00000000 -#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT__SI 0x00000000 -#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000010 -#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT__SI 0x00000018 -#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT__SI 0x00000009 -#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT__SI 0x00000008 -#define D5_PROTECTION__D5_DP_ENC_REQUIRED__SHIFT__SI 0x00000001 -#define D5_PROTECTION__D5_NO_DVO_OUT__SHIFT__SI 0x00000002 -#define D5_PROTECTION__D5_NO_LVDS_OUT__SHIFT__SI 0x00000004 -#define D5_PROTECTION__D5_NO_SDVO_OUT__SHIFT__SI 0x00000003 -#define D5_PROTECTION__D5_NO_VGA_OUT__SHIFT__SI 0x00000005 -#define D5_PROTECTION__D5_TMDS_ENC_REQUIRED__SHIFT__SI 0x00000000 -#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT__SI 0x00000000 -#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT__SI 0x00000010 -#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT__SI 0x00000018 -#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT__SI 0x00000009 -#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT__SI 0x00000008 -#define D6_PROTECTION__D6_DP_ENC_REQUIRED__SHIFT__SI 0x00000001 -#define D6_PROTECTION__D6_NO_DVO_OUT__SHIFT__SI 0x00000002 -#define D6_PROTECTION__D6_NO_LVDS_OUT__SHIFT__SI 0x00000004 -#define D6_PROTECTION__D6_NO_SDVO_OUT__SHIFT__SI 0x00000003 -#define D6_PROTECTION__D6_NO_VGA_OUT__SHIFT__SI 0x00000005 -#define D6_PROTECTION__D6_TMDS_ENC_REQUIRED__SHIFT__SI 0x00000000 -#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT__SI 0x00000000 -#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT__SI 0x00000008 -#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT__SI 0x00000000 -#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT__SI 0x00000008 -#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT__SI 0x00000010 -#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT__SI 0x00000008 -#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT__SI 0x00000000 -#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT__SI 0x00000000 -#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT__SI 0x00000010 -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT__SI 0x00000018 -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT__SI 0x00000004 -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT__SI 0x00000010 -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT__SI 0x00000008 -#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT__SI 0x00000000 -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_COMPLETE__SHIFT__SI 0x0000001c -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_DACADJ_EN__SHIFT__SI 0x00000002 -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_EN__SHIFT__SI 0x00000001 -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_INITB__SHIFT__SI 0x00000000 -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_MASK__SHIFT__SI 0x00000014 -#define DAC_AUTO_CALIB_CONTROL__DAC_CAL_WAIT_ADJUST__SHIFT__SI 0x00000004 -#define DAC_BGADJ_CONTROL__DAC_BGADJ_SRC__SHIFT__SI 0x00000004 -#define DAC_BGADJ_CONTROL__DAC_BGADJ_TESTEN__SHIFT__SI 0x00000000 -#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT__SI 0x00000012 -#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT__SI 0x00000000 -#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT__SI 0x00000008 -#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT__SI 0x00000011 -#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT__SI 0x00000010 -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT__SI 0x00000001 -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT__SI 0x00000002 -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT__SI 0x00000003 -#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT__SI 0x00000000 -#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT__SI 0x00000000 -#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT__SI 0x00000008 -#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT__SI 0x00000010 -#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT__SI 0x00000000 -#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT__SI 0x00000008 -#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT__SI 0x00000010 -#define DAC_CRC_EN__DAC_CRC_EN__SHIFT__SI 0x00000000 -#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT__SI 0x00000000 -#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT__SI 0x00000000 -#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT__SI 0x00000000 -#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT__SI 0x0000000a -#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT__SI 0x00000014 -#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT__SI 0x00000000 -#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT__SI 0x0000000a -#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT__SI 0x00000014 -#define DAC_DATA__DAC_DATA__SHIFT__SI 0x00000000 -#define DAC_DEBUG1__DOUT_DAC_BLANKb__SHIFT__SI 0x00000001 -#define DAC_DEBUG1__DOUT_DAC_BLUE__SHIFT__SI 0x00000002 -#define DAC_DEBUG1__DOUT_DAC_GREEN__SHIFT__SI 0x0000000c -#define DAC_DEBUG1__DOUT_DAC_PIXCLK__SHIFT__SI 0x00000000 -#define DAC_DEBUG1__DOUT_DAC_RED__SHIFT__SI 0x00000016 -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_BGSLEEP_PU_OR__SHIFT__SI 0x0000000f -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_DAC_PIN_PD_OR__SHIFT__SI 0x00000011 -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_DAC_PIN_PU_OR__SHIFT__SI 0x00000010 -#define DAC_DEBUG2__DOUT_DAC_AUTODETECT_STATE__SHIFT__SI 0x0000000c -#define DAC_DEBUG2__DOUT_DAC_BDACPD__SHIFT__SI 0x0000001a -#define DAC_DEBUG2__DOUT_DAC_BGSLEEP__SHIFT__SI 0x00000019 -#define DAC_DEBUG2__DOUT_DAC_BLANKb__SHIFT__SI 0x00000001 -#define DAC_DEBUG2__DOUT_DAC_CAPTURE_START__SHIFT__SI 0x00000006 -#define DAC_DEBUG2__DOUT_DAC_DATA_SOURCE_ENABLED__SHIFT__SI 0x00000015 -#define DAC_DEBUG2__DOUT_DAC_DETECT__SHIFT__SI 0x0000001d -#define DAC_DEBUG2__DOUT_DAC_FIELD_NUMBER__SHIFT__SI 0x00000007 -#define DAC_DEBUG2__DOUT_DAC_GDACPD__SHIFT__SI 0x0000001b -#define DAC_DEBUG2__DOUT_DAC_HSYNC_EN__SHIFT__SI 0x00000003 -#define DAC_DEBUG2__DOUT_DAC_HSYNC__SHIFT__SI 0x00000002 -#define DAC_DEBUG2__DOUT_DAC_MON_2__SHIFT__SI 0x0000001f -#define DAC_DEBUG2__DOUT_DAC_MON_3__SHIFT__SI 0x0000001e -#define DAC_DEBUG2__DOUT_DAC_NBLANK__SHIFT__SI 0x00000017 -#define DAC_DEBUG2__DOUT_DAC_PEDESTAL__SHIFT__SI 0x00000018 -#define DAC_DEBUG2__DOUT_DAC_PIXCLK__SHIFT__SI 0x00000000 -#define DAC_DEBUG2__DOUT_DAC_PIXCLKa__SHIFT__SI 0x00000016 -#define DAC_DEBUG2__DOUT_DAC_RDACPD__SHIFT__SI 0x0000001c -#define DAC_DEBUG2__DOUT_DAC_SCLK__SHIFT__SI 0x0000000b -#define DAC_DEBUG2__DOUT_DAC_SOURCE_SEL__SHIFT__SI 0x00000009 -#define DAC_DEBUG2__DOUT_DAC_STEREOSYNC__SHIFT__SI 0x00000008 -#define DAC_DEBUG2__DOUT_DAC_VSYNC_EN__SHIFT__SI 0x00000005 -#define DAC_DEBUG2__DOUT_DAC_VSYNC__SHIFT__SI 0x00000004 -#define DAC_DEBUG2__DOUT_DAC_iBDACDET_from_macro__SHIFT__SI 0x00000012 -#define DAC_DEBUG2__DOUT_DAC_iGDACDET_from_macro__SHIFT__SI 0x00000013 -#define DAC_DEBUG2__DOUT_DAC_iRDACDET_from_macro__SHIFT__SI 0x00000014 -#define DAC_DEBUG3__DAC_DEBUG3__SHIFT__SI 0x00000000 -#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT__SI 0x00000000 -#define DAC_ENABLE__DAC_ENABLE__SHIFT__SI 0x00000000 -#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT__SI 0x00000000 -#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT__SI 0x00000000 -#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT__SI 0x00000018 -#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT__SI 0x00000008 -#define DAC_MACRO_CNTL__DAC_ANALOG_MONITOR__SHIFT__SI 0x00000018 -#define DAC_MACRO_CNTL__DAC_BANDGAP_ADJUSTMENT__SHIFT__SI 0x00000010 -#define DAC_MACRO_CNTL__DAC_COREMON__SHIFT__SI 0x0000001c -#define DAC_MACRO_CNTL__DAC_WHITE_FINE_CONTROL__SHIFT__SI 0x00000008 -#define DAC_MACRO_CNTL__DAC_WHITE_LEVEL__SHIFT__SI 0x00000000 -#define DAC_MASK__DAC_MASK__SHIFT__SI 0x00000000 -#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT__SI 0x00000008 -#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT__SI 0x00000010 -#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT__SI 0x00000018 -#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT__SI 0x00000000 -#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT__SI 0x00000000 -#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT__SI 0x00000010 -#define DAC_R_INDEX__DAC_R_INDEX__SHIFT__SI 0x00000000 -#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT__SI 0x00000000 -#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT__SI 0x00000003 -#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT__SI 0x00000000 -#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT__SI 0x00000000 -#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT__SI 0x00000010 -#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT__SI 0x00000008 -#define DAC_TEST_ENABLE__DAC_TEST_ENABLE__SHIFT__SI 0x00000000 -#define DAC_W_INDEX__DAC_W_INDEX__SHIFT__SI 0x00000000 -#define DATA_FORMAT__ALLOW_REQ_MODE_1_2__SHIFT__SI 0x0000001c -#define DATA_FORMAT__ALWAYS_SCL_RTS_HI__SHIFT__SI 0x00000008 -#define DATA_FORMAT__INTERLEAVE_EN__SHIFT__SI 0x00000000 -#define DATA_FORMAT__PREFETCH__SHIFT__SI 0x0000000c -#define DATA_FORMAT__REQUEST_MODE__SHIFT__SI 0x00000018 -#define DATA_FORMAT__RESET_REQ_AT_EOL__SHIFT__SI 0x00000004 -#define DATA_FORMAT__SOF_READ_PT__SHIFT__SI 0x00000010 -#define DBG_BUS_OUT1__DBG_BUS_OUT__SHIFT 0x00000000 -#define DBG_BUS_OUT1__DBG_CNTL_OUT__SHIFT 0x00000018 -#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT__CI 0x00000001 -#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT__CI 0x00000000 -#define DBG_CHAIN_CONTROL__DBG_BLOCK_SEL__SHIFT 0x00000000 -#define DBG_CHAIN_CONTROL__DBG_CHAN_SEL__SHIFT 0x00000017 -#define DBG_CHAIN_CONTROL__DBG_CONTROL_LOAD__SHIFT 0x00000018 -#define DBG_CHAIN_CONTROL__DBG_GROUP_SEL__SHIFT 0x0000000c -#define DBG_CHAIN_CONTROL__DBG_MUX_SEL__SHIFT 0x00000016 -#define DBG_CHAIN_CONTROL__DBG_OUTPUT_SEL__SHIFT 0x00000013 -#define DBG_FBC_COMP_DEBUG__DBG_FBC_COMP_DEBUG__SHIFT__SI 0x00000000 -#define DBG_FBC_CTL23__DBG_FBC_CTL2__SHIFT__SI 0x00000000 -#define DBG_FBC_CTL23__DBG_FBC_CTL3__SHIFT__SI 0x0000000c -#define DBG_FBC_DECOMP_CTL_DEBUG__DBG_FBC_DECOMP_CTL_DEBUG__SHIFT__SI 0x00000000 -#define DBW_CHROMA_BOT_ADDR__DBW_UV_BOT_BASE__SHIFT__SI 0x00000000 -#define DBW_CHROMA_TOP_ADDR__DBW_UV_TOP_BASE__SHIFT__SI 0x00000000 -#define DBW_LUMA_BOT_ADDR__DBW_Y_BOT_BASE__SHIFT__SI 0x00000000 -#define DBW_LUMA_TOP_ADDR__DBW_Y_TOP_BASE__SHIFT__SI 0x00000000 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000000 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000008 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000000a -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000000c -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000000e -#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x00000010 -#define DB_BUF_SIZE__HEIGHT__SHIFT__SI 0x00000014 -#define DB_BUF_SIZE__PITCH__SHIFT__SI 0x00000004 -#define DB_CF_DAT__DAT__SHIFT__SI 0x00000000 -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x00000000 -#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x0000000c -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT__CI__VI 0x00000014 -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x00000001 -#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x00000004 -#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT__CI__VI 0x00000010 -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT__CI__VI 0x00000018 -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT__CI__VI 0x0000001c -#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT__CI__VI 0x0000000c -#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT__CI__VI 0x00000008 -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x00000000 -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0x0000000a -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x00000018 -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x00000005 -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x00000000 -#define DB_CTL__CTXT_FMT__SHIFT__SI 0x00000006 -#define DB_CTL__DB_BIG_ENDIAN__SHIFT__SI 0x0000000a -#define DB_CTL__MEM_TIMEOUT_TIME__SHIFT__SI 0x00000014 -#define DB_CTL__NSG_MODE__SHIFT__SI 0x00000004 -#define DB_CTL__STANDARD__SHIFT__SI 0x00000000 -#define DB_CTL__STD_VERSION__SHIFT__SI 0x0000000e -#define DB_CTL__SW_MEM_RST__SHIFT__SI 0x0000001c -#define DB_CTL__SW_MRST__SHIFT__SI 0x0000001e -#define DB_CTL__SW_RRST__SHIFT__SI 0x0000001d -#define DB_CTL__SW_SRST__SHIFT__SI 0x0000001f -#define DB_CTL__TILE_FMT__SHIFT__SI 0x0000000c -#define DB_CTL__USE_DB_VC1_SP_CONTEXT__SHIFT__SI 0x0000000b -#define DB_CTL__UV_FMT__SHIFT__SI 0x0000000d -#define DB_CTL__VC1_PROFILE__SHIFT__SI 0x00000008 -#define DB_DBG_CTL__DBG_ALL_TOP_WRITES__SHIFT__SI 0x00000002 -#define DB_DBG_CTL__DBG_DIS_STAGEA__SHIFT__SI 0x00000000 -#define DB_DBG_CTL__DBG_DIS_STAGEB__SHIFT__SI 0x00000001 -#define DB_DBG_STAT__STATE_DBFSM__SHIFT__SI 0x00000000 -#define DB_DBG_STAT__TEST_DEBUG_REG__SHIFT__SI 0x00000005 -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x00000000 -#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x00000009 -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x00000012 -#define DB_DEBUG2__DISABLE_HTILE_BASE_MATCH_STATE_LOAD__SHIFT__SI 0x0000001e -#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x00000010 -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x00000011 -#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x00000008 -#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x00000007 -#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x00000005 -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x0000001d -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x00000013 -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT__CI__VI 0x0000001e -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT__SI 0x0000001f -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x00000002 -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x00000001 -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0x0000000e -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT__CI__VI 0x0000001f -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004 -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x00000003 -#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x00000006 -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x0000001c -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0x0000000f -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT__CI__VI 0x00000010 -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT__SI 0x00000011 -#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT__CI 0x0000001e -#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT__SI 0x0000001a -#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT__CI__VI 0x00000019 -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT__CI__VI 0x00000018 -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x00000004 -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT__CI__VI 0x00000014 -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT__SI 0x00000015 -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT__CI__VI 0x0000000d -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT__SI 0x0000000e -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT__CI__VI 0x0000000f -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT__SI 0x00000010 -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT__CI__VI 0x0000000e -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT__SI 0x0000000f -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT__CI__VI 0x00000012 -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT__SI 0x00000013 -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT__CI__VI 0x0000000c -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT__SI 0x0000000d -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT__CI__VI 0x0000001b -#define DB_DEBUG3__DISABLE_PC_WC_ZF_COLLISION_DETECTION_FIX__SHIFT__SI 0x00000018 -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT__CI__VI 0x00000017 -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT__CI__VI 0x0000000a -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT__SI 0x0000000b -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT__CI__VI 0x00000009 -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT__SI 0x0000000a -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x00000007 -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT__CI__VI 0x00000013 -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT__SI 0x00000014 -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x00000003 -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x00000008 -#define DB_DEBUG3__DISALLOW_REG_READS_IF_HARVESTED__SHIFT__SI 0x00000019 -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT__CI__VI 0x0000001d -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT__CI__VI 0x0000001c -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT__CI__VI 0x0000001a -#define DB_DEBUG3__ENABLE_HIZ_TILE_ZRANGE_FOR_SRC_QTILES__SHIFT__SI 0x00000009 -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT__CI__VI 0x0000000b -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT__SI 0x0000000c -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT__CI__VI 0x00000015 -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT__SI 0x00000016 -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT__CI__VI 0x00000016 -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT__SI 0x00000017 -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x00000005 -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x00000006 -#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x00000002 -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT__CI__VI 0x00000011 -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT__SI 0x00000012 -#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT__CI 0x00000004 -#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT__SI__VI 0x00000006 -#define DB_DEBUG4__DISABLE_PARTIAL_CONVERTED_FROM_SINGLE_FIX__SHIFT__SI 0x00000004 -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT__CI__VI 0x00000003 -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT__SI 0x00000005 -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x00000001 -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x00000000 -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x00000002 -#define DB_DEBUG4__DISABLE_REZ_SINGLE_STENCIL_FIX__SHIFT__SI 0x00000003 -#define DB_DEBUG_INT_STAT__CTXT_TIMEOUT__SHIFT__SI 0x00000003 -#define DB_DEBUG_INT_STAT__DBFSM_DONE__SHIFT__SI 0x00000000 -#define DB_DEBUG_INT_STAT__ERRDET__SHIFT__SI 0x00000004 -#define DB_DEBUG_INT_STAT__MEM_TIMEOUT__SHIFT__SI 0x00000002 -#define DB_DEBUG_INT_STAT__PKT_ERR__SHIFT__SI 0x00000001 -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x00000001 -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0x0000000f -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0x0000000e -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x00000006 -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x00000013 -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0x0000000a -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0x0000000c -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x00000008 -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x00000007 -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x00000010 -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x00000000 -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x00000018 -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x00000012 -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x0000001e -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x0000001f -#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x00000011 -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x00000017 -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x00000003 -#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x00000002 -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x0000001d -#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x00000004 -#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x00000015 -#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x0000001c -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x00000016 -#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x00000000 -#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x00000000 -#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x00000003 -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x0000001f -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x0000001e -#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x00000014 -#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x00000008 -#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x00000000 -#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x00000004 -#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x00000001 -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 -#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x00000000 -#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT__CI__VI 0x00000004 -#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT__CI__VI 0x0000000f -#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT__CI__VI 0x0000000d -#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000011 -#define DB_DEPTH_INFO__NUM_BANKS__SHIFT__CI__VI 0x00000013 -#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT__CI__VI 0x00000008 -#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0x0000000b -#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x00000000 -#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x00000000 -#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x00000000 -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x00000019 -#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x00000018 -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x00000015 -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0x0000000c -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x0000001b -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x00000010 -#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x00000011 -#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x00000012 -#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x00000013 -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x00000008 -#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x00000000 -#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x00000018 -#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x00000004 -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x00000014 -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_CB_REPVAL__SHIFT__SI 0x00000004 -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_CR_REPVAL__SHIFT__SI 0x0000000c -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_FADE_BLACK__SHIFT__SI 0x00000003 -#define DB_ERRCONCEAL_CONTROL__ERRCONCEAL_MODE__SHIFT__SI 0x00000000 -#define DB_ERRDET_CONTROL__ERR_AIDB_ENABLE__SHIFT__SI 0x00000019 -#define DB_ERRDET_CONTROL__ERR_AIDB_THRESH__SHIFT__SI 0x00000000 -#define DB_ERRDET_CONTROL__ERR_CONCEAL_ENABLE__SHIFT__SI 0x0000001a -#define DB_ERRDET_CONTROL__ERR_GREY_THRESH__SHIFT__SI 0x00000010 -#define DB_ERRDET__ERR_FOUND__SHIFT__SI 0x00000010 -#define DB_ERRDET__ERR_TYPE__SHIFT__SI 0x00000011 -#define DB_ERRDET__ERR_X_COORD__SHIFT__SI 0x00000000 -#define DB_ERRDET__ERR_Y_COORD__SHIFT__SI 0x00000008 -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x00000015 -#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a -#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x00000000 -#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x00000005 -#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x00000010 -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x00000000 -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x00000008 -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x0000000f -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x00000019 -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x00000000 -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x00000015 -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x00000007 -#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x0000000e -#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x00000019 -#define DB_GREY_LEVELS__CBCR_HI__SHIFT__SI 0x00000008 -#define DB_GREY_LEVELS__CBCR_LO__SHIFT__SI 0x00000000 -#define DB_GREY_LEVELS__LUMA_HI__SHIFT__SI 0x00000018 -#define DB_GREY_LEVELS__LUMA_LO__SHIFT__SI 0x00000010 -#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x00000000 -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x00000010 -#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x00000001 -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x00000002 -#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x00000000 -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0x0000000a -#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x00000004 -#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x00000003 -#define DB_HW_DEBUG__DB_HW_DEBUG__SHIFT__SI 0x00000000 -#define DB_INTRA_HOR_ADR__INTRA_HOR_ADR__SHIFT__SI 0x00000006 -#define DB_INT_EN__CTXT_TIMEOUT_EN__SHIFT__SI 0x00000003 -#define DB_INT_EN__DBFSM_DONE_EN__SHIFT__SI 0x00000000 -#define DB_INT_EN__ERRDET_EN__SHIFT__SI 0x00000004 -#define DB_INT_EN__MEM_TIMEOUT_EN__SHIFT__SI 0x00000002 -#define DB_INT_EN__PKT_ERR_EN__SHIFT__SI 0x00000001 -#define DB_INT_STAT__CTXT_TIMEOUT__SHIFT__SI 0x00000003 -#define DB_INT_STAT__DBFSM_DONE__SHIFT__SI 0x00000000 -#define DB_INT_STAT__ERRDET__SHIFT__SI 0x00000004 -#define DB_INT_STAT__MEM_TIMEOUT__SHIFT__SI 0x00000002 -#define DB_INT_STAT__PKT_ERR__SHIFT__SI 0x00000001 -#define DB_LMA_ADR__ADR__SHIFT__SI 0x00000000 -#define DB_LMA_CTL__ACCESS_MODE__SHIFT__SI 0x00000000 -#define DB_LMA_CTL__AUTO_INC__SHIFT__SI 0x00000006 -#define DB_LMA_CTL__MEMORY_SELECT__SHIFT__SI 0x00000001 -#define DB_LMA_DAT__DAT__SHIFT__SI 0x00000000 -#define DB_LUMA_ADR__LUMA_ADR__SHIFT__SI 0x00000006 -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT__CI__VI 0x00000000 -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT__CI__VI 0x00000000 -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT__CI__VI 0x00000000 -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT__CI__VI 0x00000000 -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT__CI__VI 0x00000000 -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT__CI__VI 0x00000000 -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT__CI__VI 0x00000000 -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT__CI__VI 0x00000000 -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x00000010 -#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x00000018 -#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x00000000 -#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x00000008 -#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x00000000 -#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x00000000 -#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x00000000 -#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x00000000 -#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x00000000 -#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x00000007 -#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x00000008 -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000000 -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x00000006 -#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x00000002 -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x00000004 -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x00000001 -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x00000005 -#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x00000003 -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x00000008 -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x0000000a -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x00000007 -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT__CI__VI 0x00000017 -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x00000009 -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000006 -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000005 -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT__CI__VI 0x00000012 -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT__CI__VI 0x0000000f -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT__CI__VI 0x0000000c -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x00000000 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x00000002 -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT__CI__VI 0x00000016 -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT__CI__VI 0x00000015 -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT__CI__VI 0x0000000b -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x00000012 -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x0000001a -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x00000010 -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x00000008 -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x00000007 -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0x0000000a -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x0000000d -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x00000002 -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x00000004 -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x00000000 -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0x0000000f -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x00000006 -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x0000001c -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0x0000000c -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x0000001e -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x0000001b -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x00000013 -#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0x0000000b -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x0000001d -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x00000011 -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x00000015 -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x00000009 -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x0000001f -#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT__CI__VI 0x00000000 -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0x0000000b -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x0000000d -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x00000007 -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0x0000000c -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x00000009 -#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0x0000000a -#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x00000006 -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x00000008 -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x00000002 -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x00000001 -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x00000000 -#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x00000004 -#define DB_SLICE_INFO__LOOPFILTER__SHIFT__SI 0x0000000d -#define DB_SLICE_INFO__MBAFF_FRAME_FLAG__SHIFT__SI 0x00000006 -#define DB_SLICE_INFO__PICTURE_STRUCTURE__SHIFT__SI 0x00000003 -#define DB_SLICE_INFO__PQUANT__SHIFT__SI 0x00000007 -#define DB_SLICE_INFO__SLICE_TYPE__SHIFT__SI 0x00000000 -#define DB_SPS_INFO__CHROMA_FORMAT_IDC__SHIFT__SI 0x00000015 -#define DB_SPS_INFO__MAX_X_MB__SHIFT__SI 0x00000004 -#define DB_SPS_INFO__MAX_Y_MB__SHIFT__SI 0x0000000c -#define DB_SRAM_RM_CTL__DB_M032X064R2M01S00_RME__SHIFT__SI 0x00000004 -#define DB_SRAM_RM_CTL__DB_M032X064R2M01S00_RM__SHIFT__SI 0x00000000 -#define DB_SRAM_RM_CTL__DB_M088X064R2M01S00_RME__SHIFT__SI 0x0000000e -#define DB_SRAM_RM_CTL__DB_M088X064R2M01S00_RM__SHIFT__SI 0x0000000a -#define DB_SRAM_RM_CTL__DB_M096X032R2M02S00_RME__SHIFT__SI 0x00000009 -#define DB_SRAM_RM_CTL__DB_M096X032R2M02S00_RM__SHIFT__SI 0x00000005 -#define DB_SRAM_RM_CTL__DB_WRM__SHIFT__SI 0x0000000f -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x00000000 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0x0000000c -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x00000004 -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x00000018 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x00000000 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0x0000000c -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x00000004 -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x00000018 -#define DB_STAT__BUSY__SHIFT__SI 0x00000000 -#define DB_STAT__MEM_BUSY__SHIFT__SI 0x00000001 -#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x00000018 -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x00000000 -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 -#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 -#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x00000018 -#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x00000000 -#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 -#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x00000000 -#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0x0000000c -#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x00000000 -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x00000014 -#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x00000008 -#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x00000010 -#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x00000004 -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b -#define DB_STENCIL_INFO__FORMAT__SHIFT 0x00000000 -#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 -#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT__CI__VI 0x0000000d -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x0000001d -#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x00000000 -#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x00000000 -#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x00000010 -#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x00000012 -#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x00000000 -#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x00000002 -#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x00000004 -#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x00000006 -#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x00000008 -#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0x0000000a -#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0x0000000c -#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0x0000000e -#define DB_TOP_Y_PIC__TOP_Y_PIC__SHIFT__SI 0x00000000 -#define DB_UPROC_STAT__PKT_COUNT__SHIFT__SI 0x00000000 -#define DB_UPROC_STAT__PKT_LEVEL__SHIFT__SI 0x00000008 -#define DB_UPROC_STAT__PKT_OFLOW__SHIFT__SI 0x0000000c -#define DB_UPROC_STAT__PKT_UFLOW__SHIFT__SI 0x0000000d -#define DB_VC1_SP_CONTEXT__INTRA_CURR__SHIFT__SI 0x00000001 -#define DB_VC1_SP_CONTEXT__INTRA_TOP__SHIFT__SI 0x00000007 -#define DB_VC1_SP_CONTEXT__INTRA_ULEFT__SHIFT__SI 0x0000000b -#define DB_VC1_SP_CONTEXT__OVERLAP__SHIFT__SI 0x00000000 -#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x0000001e -#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x0000001f -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x00000014 -#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x00000005 -#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x00000000 -#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x0000000f -#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x0000001b -#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0x0000000b -#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x0000001c -#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x0000001d -#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x00000000 -#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x00000000 -#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b -#define DB_Z_INFO__FORMAT__SHIFT 0x00000000 -#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x00000002 -#define DB_Z_INFO__READ_SIZE__SHIFT 0x0000001c -#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 -#define DB_Z_INFO__TILE_SPLIT__SHIFT__CI__VI 0x0000000d -#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x0000001d -#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x0000001f -#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x00000000 -#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x00000000 -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_BASE__SHIFT__SI 0x00000014 -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_DIV__SHIFT__SI 0x0000001c -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_EN__SHIFT__SI 0x00000010 -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_DBG_MULTI__SHIFT__SI 0x00000018 -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_FS_DIV_SEL__SHIFT__SI 0x00000004 -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT__SI 0x00000003 -#define DCCG_AUDIO_DTO0_CNTL__DCCG_AUDIO_DTO0_WALLCLOCK_RATIO__SHIFT__SI 0x00000000 -#define DCCG_AUDIO_DTO0_LOAD__DCCG_AUDIO_DTO0_LOAD_VALUE__SHIFT__SI 0x00000000 -#define DCCG_AUDIO_DTO0_LOAD__DCCG_AUDIO_DTO0_LOAD__SHIFT__SI 0x0000001f -#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT__SI 0x00000000 -#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT__SI 0x00000000 -#define DCCG_AUDIO_DTO_SELECT__DCCG_AUDIO_DTO_SEL__SHIFT__SI 0x00000000 -#define DCCG_CG_PLL_PIXCLK_SEL__DCCG_CG_PLL_PIXCLK_SEL__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_01__IDA0_P1PLL_FB_DIV_CHANGED__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_01__IDA0_P1PLL_FB_DIV_CONV__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_01__IDA0_P1PLL_FB_DIV_FRACT_CONV__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_01__IDA0_P1PLL_HSYNC__SHIFT__SI 0x0000001c -#define DCCG_DEBUG_01__IDA0_P1PLL_REF_DIV_CHANGED__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_ACK__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_CURRENT_STATE__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_ENABLE__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_PENDING__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_01__IDA0_P1PLL_UPDATE_REQ__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_01__IDA0_P1PLL_VGA_TIMING_MODE__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_12__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_13__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_ANTI_RUN_CLK__SHIFT__SI 0x0000001d -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_B_PCOUNT__SHIFT__SI 0x0000001a -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_B_PVCO_CAL1__SHIFT__SI 0x0000001b -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_B_PVCO_CAL2__SHIFT__SI 0x0000001c -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_CALIB_PLL_CALIB_DONE__SHIFT__SI 0x00000019 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_DIVUP_UPDATE_ACK__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_DIVUP_UPDATE_REQ__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_ALLOW_UPDATE__SHIFT__SI 0x00000013 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_CURRENT_STATE__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_SLIP_ACK_FRACT_FB__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_FB_START_SLIP_FRACT_FB__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_HSYNC_DIV_DONE__SHIFT__SI 0x00000015 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_HSYNC__SHIFT__SI 0x00000016 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_POST_DIV_VAL0__SHIFT__SI 0x00000014 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_PPLL_HSYNC__SHIFT__SI 0x00000017 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_PDIV_STATE__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_REFDIV_PLL_LOCKED_REG__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_02__IDA1_P1PLL_DEBUG_REFDIV_SAFE_TO_UPDATE__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_02__IDA1_P1PLL_PFD_DOWN__SHIFT__SI 0x0000001f -#define DCCG_DEBUG_02__IDA1_P1PLL_PFD_UP__SHIFT__SI 0x0000001e -#define DCCG_DEBUG_03__IDA2_P2PLL_FB_DIV_CHANGED__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_03__IDA2_P2PLL_FB_DIV_CONV__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_03__IDA2_P2PLL_FB_DIV_FRACT_CONV__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_03__IDA2_P2PLL_HSYNC__SHIFT__SI 0x0000001c -#define DCCG_DEBUG_03__IDA2_P2PLL_REF_DIV_CHANGED__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_ACK__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_CURRENT_STATE__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_ENABLE__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_PENDING__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_03__IDA2_P2PLL_UPDATE_REQ__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_03__IDA2_P2PLL_VGA_TIMING_MODE__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_04__IDA1_P2PLL_DEBUG_12__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_04__IDA1_P2PLL_DEBUG_13__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_ANTI_RUN_CLK__SHIFT__SI 0x0000001d -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_B_PCOUNT__SHIFT__SI 0x0000001a -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_B_PVCO_CAL1__SHIFT__SI 0x0000001b -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_B_PVCO_CAL2__SHIFT__SI 0x0000001c -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_CALIB_PLL_CALIB_DONE__SHIFT__SI 0x00000019 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_DIVUP_UPDATE_ACK__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_DIVUP_UPDATE_REQ__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_ALLOW_UPDATE__SHIFT__SI 0x00000013 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_CURRENT_STATE__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_SLIP_ACK_FRACT_FB__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_FB_START_SLIP_FRACT_FB__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_HSYNC_DIV_DONE__SHIFT__SI 0x00000015 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_HSYNC__SHIFT__SI 0x00000016 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_POST_DIV_VAL0__SHIFT__SI 0x00000014 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_PPLL_HSYNC__SHIFT__SI 0x00000017 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_PDIV_STATE__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_REFDIV_PLL_LOCKED_REG__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_04__IDA3_P2PLL_DEBUG_REFDIV_SAFE_TO_UPDATE__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_04__IDA3_P2PLL_PFD_DOWN__SHIFT__SI 0x0000001f -#define DCCG_DEBUG_04__IDA3_P2PLL_PFD_UP__SHIFT__SI 0x0000001e -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_PRE_RUN__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_RUN_REG__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_RUN__SHIFT__SI 0x00000006 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_CLK_SRC_MUX_SEL__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_GLITCH_END__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_SRC_SEL_CHANGE__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC1_STOP_FOR_GLITCH__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_PRE_RUN__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_RUN_REG__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_RUN__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_CLK_SRC_MUX_SEL__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_GLITCH_END__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_SRC_SEL_CHANGE__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_CRTC2_STOP_FOR_GLITCH__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_DEFAULT_MVP_CLK_A__SHIFT__SI 0x00000013 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_DEFAULT_MVP_CLK_B__SHIFT__SI 0x0000001b -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_A_DUPLICATE__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_A__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_B_DUPLICATE__SHIFT__SI 0x00000019 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_INPUT_MVP_CLK_B__SHIFT__SI 0x00000011 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MULTI_CHAIN_SCAN_MODE__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_A_MUX_SEL__SHIFT__SI 0x00000015 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_A__SHIFT__SI 0x00000017 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_B_MUX_SEL__SHIFT__SI 0x0000001d -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_MVP_CLK_B__SHIFT__SI 0x0000001f -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_PCLK_CRTC1_DUPLICATE__SHIFT__SI 0x0000001c -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_PCLK_CRTC1__SHIFT__SI 0x00000014 -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_SINGLE_CHAIN_SCAN_MODE__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_TEST_TCK_DUPLICATE__SHIFT__SI 0x0000001a -#define DCCG_DEBUG_05__IDA4_PIXCLKGEN_TEST_TCK__SHIFT__SI 0x00000012 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_DACA_CLK_SRC__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_DACB_CLK_SRC__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_DVOA_CLK_SRC__SHIFT__SI 0x00000017 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_HDMI0_CLK_SRC__SHIFT__SI 0x00000014 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_HDMI1_CLK_SRC__SHIFT__SI 0x0000001a -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_LVTMA_CLK_SRC__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC1_CLOCK_ON__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC1_ENABLE_IN_TV_MODE__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC1_ENABLE__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC2_CLOCK_ON__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC2_ENABLE_IN_TV_MODE__SHIFT__SI 0x00000006 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_CRTC2_ENABLE__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACA_CLOCK_ON__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACA_ENABLE__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACB_CLOCK_ON__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DACB_ENABLE__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DVOA_CLOCK_ON__SHIFT__SI 0x00000019 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_DVOA_ENABLE__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI0_CLOCK_ON__SHIFT__SI 0x00000016 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI0_ENABLE__SHIFT__SI 0x00000015 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI1_CLOCK_ON__SHIFT__SI 0x0000001c -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_HDMI1_ENABLE__SHIFT__SI 0x0000001b -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_LVTMA_CLOCK_ON__SHIFT__SI 0x00000013 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_LVTMA_ENABLE__SHIFT__SI 0x00000011 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_TMDSA_CLOCK_ON__SHIFT__SI 0x00000012 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_PCLK_TMDSA_ENABLE__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_TMDSA_CLK_SRC__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_TVCLK_CRTC1_ENABLE__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_06__IDA5_PIXCLKGEN_TVCLK_CRTC2_ENABLE__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_G_SCL1_CLOCK_ON__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_G_SCL2_CLOCK_ON__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_R_CLOCK_ON__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_R_RBBMIF_CLOCK_ON__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_DISP_CLK_R_TVOUT_CLOCK_ON__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_DISP_CLK_SCL1_BUSY__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_DISP_CLK_SCL2_BUSY__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_REGCLK_DISP_BUSY__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_GATED_REGCLK_TVOUT_BUSY__SHIFT__SI 0x00000006 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_PM_DISABLE__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_RBBM_REGCLK_ACTIVE__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_07__IDA6_DISP_CLK_GATER_R_RBBMIF_BUSY__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_DISPOUT_SOFT_RESET__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_08__IDA7_DISP_CLK_G_SCL1_RST__SHIFT__SI 0x00000006 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_G_SCL2_RST__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_ALU_RST__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_DCO_RST__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_DISPOUT_RST__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_SCL1_RST__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_P_SCL2_RST__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_R_RBBMIF_RST__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_08__IDA7_DISP_CLK_R_RST__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_08__IDA7_DISP_CLK_R_TVOUT_RST__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_SCALER_ALU_SOFT_RESET__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_SCL1_SOFT_RESET__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_08__IDA7_DISP_CLK_SCL2_SOFT_RESET__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_08__IDA7_PCLK_HDMI1_RST__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_08__IDA7_PCLK_HDMI1_SOFT_RESET__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_08__IDA7_RBBM_DISP_SOFT_RESET__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_09__IDA8_DVO_EN__SHIFT__SI 0x0000001b -#define DCCG_DEBUG_09__IDA8_DVO_ON_COUNT__SHIFT__SI 0x0000001c -#define DCCG_DEBUG_09__IDA8_DVO_SETTINGS_CHANGED__SHIFT__SI 0x00000017 -#define DCCG_DEBUG_09__IDA8_DVO_SETTING_COUNT__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC1_RST__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC1_SOFT_RESET__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC2_RST__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_09__IDA8_PCLK_CRTC2_SOFT_RESET__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_09__IDA8_PCLK_DACA_RST__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_09__IDA8_PCLK_DACA_SOFT_RESET__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_09__IDA8_PCLK_DACB_RST__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_09__IDA8_PCLK_DACB_SOFT_RESET__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_09__IDA8_PCLK_DVOA_RST__SHIFT__SI 0x00000015 -#define DCCG_DEBUG_09__IDA8_PCLK_DVOA_SOFT_RESET__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_09__IDA8_PCLK_HDMI0_RST__SHIFT__SI 0x00000014 -#define DCCG_DEBUG_09__IDA8_PCLK_HDMI0_SOFT_RESET__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_DSYNC_RST__SHIFT__SI 0x00000013 -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_DSYNC_SOFT_RESET__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_RST__SHIFT__SI 0x00000012 -#define DCCG_DEBUG_09__IDA8_PCLK_LVTMA_SOFT_RESET__SHIFT__SI 0x00000006 -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_DSYNC_RST__SHIFT__SI 0x00000011 -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_DSYNC_SOFT_RESET__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_RST__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_09__IDA8_PCLK_TMDSA_SOFT_RESET__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_09__IDA8_PIX1CLK_RST__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_09__IDA8_PIX2CLK_RST__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_09__IDA8_RST_DVOCLK_D__SHIFT__SI 0x00000016 -#define DCCG_DEBUG_09__IDA8_SOFT_RST_DVOCLK__SHIFT__SI 0x0000001f -#define DCCG_DEBUG_10__IDA9_CLK_RESET_DVOCLK_RESET__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_A_RST__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_A__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_B_RST__SHIFT__SI 0x00000011 -#define DCCG_DEBUG_10__IDA9_CLK_RESET_MVP_CLK_B__SHIFT__SI 0x00000012 -#define DCCG_DEBUG_10__IDA9_CLK_RESET_PRE_MVP_CLK_A_RST__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_10__IDA9_CLK_RESET_PRE_MVP_CLK_B_RST__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_CLK_SRC_SEL__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLKC_IN_PHASE__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLKD_IN_PHASE__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLK_C_CLOCK_ON__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_DVOCLK_D_CLOCK_ON__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_SINGLE_CHANNEL_DDR__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_10__IDA9_DVOCLKGEN_TEST_MODE__SHIFT__SI 0x00000006 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_DENOMINATOR_COUNT__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_DTO_EN__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_PCLK_TV_RST__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_CLK_SRC_SEL__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_DATA_SRC_SEL__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_EN__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_TV_VCLK_EN__SHIFT__SI 0x00000005 -#define DCCG_DEBUG_11__IDAA_TVCLKGEN_UPSAMPLER_PHASE__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_12__IDAB_ONESHOT_CLOCKING_MODE__SHIFT__SI 0x00000018 -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_ONE_SHOT_STOP__SHIFT__SI 0x00000002 -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_RUN_CLK__SHIFT__SI 0x00000001 -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_RUN_CLOCK_COUNT__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_TRIGGER_EVENT_OCCURRED__SHIFT__SI 0x00000003 -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_WTRIG_PRE_DCCG_ONE_SHOT_RUN_CLK__SHIFT__SI 0x0000001b -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX1CLK_WTRIG_RUN_CLK_CURRENT_CLK__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_ONE_SHOT_STOP__SHIFT__SI 0x0000000e -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_RUN_CLK__SHIFT__SI 0x0000000d -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_RUN_CLOCK_COUNT__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_TRIGGER_EVENT_OCCURRED__SHIFT__SI 0x0000000f -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_WTRIG_PRE_DCCG_ONE_SHOT_RUN_CLK__SHIFT__SI 0x0000001d -#define DCCG_DEBUG_12__IDAB_ONESHOT_PIX2CLK_WTRIG_RUN_CLK_CURRENT_CLK__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_12__IDAB_ONESHOT_TRIGGER_EN__SHIFT__SI 0x0000001a -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC_COARSE_SKEW__SHIFT__SI 0x00000016 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC_DLY_0__SHIFT__SI 0x0000001d -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC_FINE_SKEW__SHIFT__SI 0x0000001a -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKC__SHIFT__SI 0x0000001e -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD_COARSE_SKEW__SHIFT__SI 0x00000000 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD_DLY_0__SHIFT__SI 0x00000007 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD_FINE_SKEW__SHIFT__SI 0x00000004 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_DVOCLKD__SHIFT__SI 0x00000008 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_COARSE_ADJUST_EN__SHIFT__SI 0x0000000a -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_COARSE_SKEW__SHIFT__SI 0x0000000c -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_DLY_0__SHIFT__SI 0x00000014 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_FINE_ADJUST_EN__SHIFT__SI 0x0000000b -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_FINE_SKEW__SHIFT__SI 0x00000010 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC_IN_PHASE__SHIFT__SI 0x00000013 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_MVP_DVOCLKC__SHIFT__SI 0x00000015 -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_TST_DVOCLK_DUPLICATE__SHIFT__SI 0x0000001f -#define DCCG_DEBUG_13__IDAF_DVOCLKGEN_TST_DVOCLK__SHIFT__SI 0x00000009 -#define DCCG_DEBUG_BLOCK_ID__DCCG_DEBUG_BLOCK_ID__SHIFT__SI 0x00000000 -#define DCCG_DEBUG__DCCG_DEBUG__SHIFT__SI 0x00000000 -#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT__SI 0x00000004 -#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT__SI 0x00000005 -#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT__SI 0x00000000 -#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT__SI 0x00000001 -#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT__SI 0x00000006 -#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT__SI 0x00000010 -#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT__SI 0x00000008 -#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT__SI 0x00000009 -#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT__SI 0x0000000a -#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT__SI 0x0000000b -#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT__SI 0x0000000c -#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT__SI 0x0000000d -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT__SI 0x00000010 -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT__SI 0x00000000 -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT__SI 0x00000018 -#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT__SI 0x00000008 -#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT__SI 0x00000000 -#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT__SI 0x00000000 -#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT__SI 0x00000000 -#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT__SI 0x00000000 -#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT__SI 0x00000000 -#define DCDEBUG_DATA_TRIGGER_MASK__DCDEBUG_DATA_TRIGGER_MASK__SHIFT__SI 0x00000000 -#define DCDEBUG_DATA_TRIGGER_PATTERN__DCDEBUG_DATA_TRIGGER_PATTERN__SHIFT__SI 0x00000000 -#define DCDEBUG_EDGE_TRIGGER_MASK__DCDEBUG_EDGE_TRIGGER_MASK__SHIFT__SI 0x00000000 -#define DCDEBUG_EDGE_TRIGGER_PATTERN__DCDEBUG_EDGE_TRIGGER_PATTERN__SHIFT__SI 0x00000000 -#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT__SI 0x00000000 -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT__SI 0x00000005 -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT__SI 0x00000006 -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT__SI 0x00000014 -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT__SI 0x00000007 -#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT__SI 0x00000008 -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT__SI 0x0000000c -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT__SI 0x00000000 -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT__SI 0x00000004 -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT__SI 0x0000001c -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT__SI 0x00000010 -#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT__SI 0x00000014 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_EXTERNAL_TRIGGER_IN_EN__SHIFT__SI 0x00000010 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_EXTERNAL_TRIGGER_IN_PIN__SHIFT__SI 0x00000014 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_EXTERNAL_TRIGGER_IN_POL__SHIFT__SI 0x00000011 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_EN__SHIFT__SI 0x00000000 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_INT_EN__SHIFT__SI 0x00000008 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_ONE_SHOT_CLOCK__SHIFT__SI 0x00000004 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_STATUS_OUT_EN__SHIFT__SI 0x00000018 -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_STATUS_OUT_PIN__SHIFT__SI 0x0000001c -#define DCDEBUG_TRIGGER_CNTL__DCDEBUG_TRIGGER_STATUS_OUT_POL__SHIFT__SI 0x00000019 -#define DCDEBUG_TRIGGER_STAT__DCDEBUG_TRIGGER_ACK__SHIFT__SI 0x00000001 -#define DCDEBUG_TRIGGER_STAT__DCDEBUG_TRIGGER_STATUS_STICKY__SHIFT__SI 0x00000004 -#define DCDEBUG_TRIGGER_STAT__DCDEBUG_TRIGGER_STATUS__SHIFT__SI 0x00000000 -#define DCFE0_CLOCK_ENABLE__DCFE0_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DCFE1_CLOCK_ENABLE__DCFE1_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DCFE2_CLOCK_ENABLE__DCFE2_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DCFE3_CLOCK_ENABLE__DCFE3_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DCFE4_CLOCK_ENABLE__DCFE4_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DCFE5_CLOCK_ENABLE__DCFE5_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT__SI 0x0000000e -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT__SI 0x0000000d -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT__SI 0x0000000f -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT__SI 0x00000013 -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT__SI 0x00000010 -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT__SI 0x00000014 -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT__SI 0x00000016 -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT__SI 0x00000015 -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT__SI 0x0000001a -#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT__SI 0x0000001b -#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT__SI 0x00000012 -#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT__SI 0x00000017 -#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT__SI 0x00000011 -#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT__SI 0x00000019 -#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT__SI 0x00000018 -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT__SI 0x0000000c -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT__SI 0x00000000 -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT__SI 0x00000006 -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT__SI 0x00000004 -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT__SI 0x0000000a -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT__SI 0x00000002 -#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT__SI 0x00000008 -#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT__SI 0x00000000 -#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT__SI 0x00000000 -#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT__SI 0x00000000 -#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT__SI 0x00000000 -#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT__SI 0x00000000 -#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT__SI 0x00000000 -#define DCIO_DEBUG__DCIO_DEBUG__SHIFT__SI 0x00000000 -#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT__SI 0x00000000 -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT__SI 0x0000000c -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_RESET_PM_MASK__SHIFT__SI 0x00000004 -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT__SI 0x00000005 -#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT__SI 0x00000008 -#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT__SI 0x00000000 -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT__SI 0x0000000c -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_RESET_PM_MASK__SHIFT__SI 0x00000004 -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT__SI 0x00000005 -#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT__SI 0x00000008 -#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT__SI 0x00000000 -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT__SI 0x0000000c -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_RESET_PM_MASK__SHIFT__SI 0x00000004 -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT__SI 0x00000005 -#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT__SI 0x00000008 -#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DCPLL_CNTL__DCPLL_ANTI_GLITCH_RESET__SHIFT__SI 0x0000000d -#define DCPLL_CNTL__DCPLL_BYPASS_CAL__SHIFT__SI 0x00000002 -#define DCPLL_CNTL__DCPLL_CALIB_DONE__SHIFT__SI 0x00000014 -#define DCPLL_CNTL__DCPLL_CALREF__SHIFT__SI 0x00000008 -#define DCPLL_CNTL__DCPLL_CAL_BYPASS_REFDIV__SHIFT__SI 0x0000000a -#define DCPLL_CNTL__DCPLL_DEBUG_SIGNALS_ENABLE__SHIFT__SI 0x0000000e -#define DCPLL_CNTL__DCPLL_DIFF_REC_ENABLE__SHIFT__SI 0x0000000c -#define DCPLL_CNTL__DCPLL_DIRECT_CLOCK_2X__SHIFT__SI 0x0000001f -#define DCPLL_CNTL__DCPLL_DVOCLK_SRC__SHIFT__SI 0x0000001e -#define DCPLL_CNTL__DCPLL_LOCKED__SHIFT__SI 0x00000015 -#define DCPLL_CNTL__DCPLL_LOCK_FREQ_SEL__SHIFT__SI 0x00000013 -#define DCPLL_CNTL__DCPLL_LVTMCLK_SRC__SHIFT__SI 0x0000001a -#define DCPLL_CNTL__DCPLL_PCIE_REFCLK_DISABLE__SHIFT__SI 0x0000000b -#define DCPLL_CNTL__DCPLL_PIXCLK_SRC__SHIFT__SI 0x0000001c -#define DCPLL_CNTL__DCPLL_PWRMGT_TURN_OFF_PLL__SHIFT__SI 0x00000010 -#define DCPLL_CNTL__DCPLL_RESET__SHIFT__SI 0x00000000 -#define DCPLL_CNTL__DCPLL_SLEEP__SHIFT__SI 0x00000001 -#define DCPLL_CNTL__DCPLL_TIMING_MODE_STATUS__SHIFT__SI 0x00000018 -#define DCPLL_CNTL__DCPLL_VCOREF__SHIFT__SI 0x00000004 -#define DCPLL_DEBUG_CLK_SEL__DCPLL_DEBUG_CLK_SEL__SHIFT__SI 0x00000008 -#define DCPLL_DISPCLK_DTO_CNTL__DCPLL_DISPCLK_DTO_DIS__SHIFT__SI 0x0000000c -#define DCPLL_DISPCLK_DTO_CNTL__DCPLL_DISPCLK_DTO_PHASE__SHIFT__SI 0x00000000 -#define DCPLL_FB_DIV__DCPLL_FB_DIV_FRACTION_CNTL__SHIFT__SI 0x00000004 -#define DCPLL_FB_DIV__DCPLL_FB_DIV_FRACTION__SHIFT__SI 0x00000000 -#define DCPLL_FB_DIV__DCPLL_FB_DIV__SHIFT__SI 0x00000010 -#define DCPLL_PLL_CNTL__DCPLL_CP__SHIFT__SI 0x00000008 -#define DCPLL_PLL_CNTL__DCPLL_IBIAS__SHIFT__SI 0x00000018 -#define DCPLL_PLL_CNTL__DCPLL_LF_MODE__SHIFT__SI 0x0000000c -#define DCPLL_PLL_CNTL__DCPLL_PLL_CTL__SHIFT__SI 0x00000000 -#define DCPLL_POST_DIV_SRC__DCPLL_POST_DIV_SRC__SHIFT__SI 0x00000000 -#define DCPLL_POST_DIV__DCPLL_POST_DIV__SHIFT__SI 0x00000000 -#define DCPLL_REF_DIV_SRC__DCPLL_REF_DIV_SRC__SHIFT__SI 0x00000000 -#define DCPLL_REF_DIV__DCPLL_CALIBRATION_REF_DIV__SHIFT__SI 0x0000000c -#define DCPLL_REF_DIV__DCPLL_REF_DIV__SHIFT__SI 0x00000000 -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_DETECT_ENABLE__SHIFT__SI 0x00000000 -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_DOWN_CNTL__SHIFT__SI 0x00000008 -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_DUTY_CYCLE_SELECT__SHIFT__SI 0x00000001 -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_STICKY_CLEAR__SHIFT__SI 0x00000003 -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_STICKY_STATUS__SHIFT__SI 0x00000002 -#define DCPLL_UNLOCK_DETECT_CNTL__DCPLL_UNLOCK_UP_CNTL__SHIFT__SI 0x00000004 -#define DCPLL_UPDATE_CNTL__DCPLL_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define DCPLL_UPDATE_CNTL__DCPLL_UPDATE_POINT__SHIFT__SI 0x00000008 -#define DCPLL_UPDATE_LOCK__DCPLL_UPDATE_LOCK__SHIFT__SI 0x00000000 -#define DCPLL_VREG_CNTL__DCPLL_VREG_BIAS__SHIFT__SI 0x00000018 -#define DCPLL_VREG_CNTL__DCPLL_VREG_CNTL__SHIFT__SI 0x00000000 -#define DCPLL_VREG_CNTL__DCPLL_VREG_POWER_DOWN__SHIFT__SI 0x0000001d -#define DCP_CONTROL__MAX_REQ_BUF_SIZE__SHIFT__SI 0x00000000 -#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT__SI 0x00000000 -#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT__SI 0x00000008 -#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT__SI 0x00000002 -#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT__SI 0x00000000 -#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT__SI 0x00000000 -#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT__SI 0x00000000 -#define DCP_DEBUG_ID__DCP_DEBUG_ID__SHIFT__SI 0x00000000 -#define DCP_DEBUG__DCP_DEBUG__SHIFT__SI 0x00000000 -#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT__SI 0x00000000 -#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT__SI 0x00000004 -#define DCP_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT__SI 0x00000000 -#define DCP_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT__SI 0x00000003 -#define DCP_RBBMIF_RDWR_TIMEOUT__AZ_RBBMIF_RD_WR_TIMEOUT_DIS__SHIFT__SI 0x00000002 -#define DCP_RBBMIF_RDWR_TIMEOUT__DCP_RBBMIF_RD_WR_TIMEOUT_DIS__SHIFT__SI 0x00000000 -#define DCP_RBBMIF_RDWR_TIMEOUT__VGA_RBBMIF_RD_WR_TIMEOUT_DIS__SHIFT__SI 0x00000001 -#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DCP_TILING_CONFIG__BANK_SWAPS__SHIFT__SI 0x0000000b -#define DCP_TILING_CONFIG__BANK_TILING__SHIFT__SI 0x00000004 -#define DCP_TILING_CONFIG__GROUP_SIZE__SHIFT__SI 0x00000006 -#define DCP_TILING_CONFIG__PIPE_TILING__SHIFT__SI 0x00000001 -#define DCP_TILING_CONFIG__ROW_TILING__SHIFT__SI 0x00000008 -#define DCP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT__SI 0x0000000e -#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT__SI 0x00000008 -#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT__SI 0x00000010 -#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT__SI 0x00000010 -#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT__SI 0x00000010 -#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT__SI 0x00000010 -#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT__SI 0x00000010 -#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT__SI 0x00000010 -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT__SI 0x0000001e -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT__SI 0x0000001c -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT__SI 0x0000001d -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT__SI 0x00000000 -#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT__SI 0x00000010 -#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_CNTL__ABM1_EN__SHIFT__SI 0x00000000 -#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT__SI 0x00000008 -#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT__SI 0x00000010 -#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT__SI 0x00000000 -#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT__SI 0x00000008 -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT__SI 0x00000002 -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT__SI 0x0000001f -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT__SI 0x0000000a -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT__SI 0x00000000 -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT__SI 0x00000010 -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT__SI 0x00000008 -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT__SI 0x00000001 -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT__SI 0x00000018 -#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT__SI 0x00000009 -#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT__SI 0x0000001b -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT__SI 0x0000001d -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT__SI 0x0000001c -#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT__SI 0x0000001e -#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT__SI 0x0000001a -#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT__SI 0x00000010 -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT__SI 0x0000000c -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT__SI 0x00000008 -#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT__SI 0x00000014 -#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT__SI \ - 0x00000010 -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT__SI 0x00000001 -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT__SI 0x00000000 -#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT__SI 0x00000008 -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT__SI 0x00000000 -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT__SI 0x00000008 -#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT__SI 0x00000010 -#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT__SI 0x00000010 -#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT__SI 0x00000010 -#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT__SI 0x00000010 -#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT__SI 0x0000001f -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT__SI \ - 0x00000010 -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT__SI 0x00000001 -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT__SI 0x00000000 -#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT__SI 0x00000008 -#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT__SI 0x00000000 -#define DC_DISPCLK_PERFCOUNTER0_HI__DC_DISPCLK_PERFCOUNTER0_HI__SHIFT__SI 0x00000000 -#define DC_DISPCLK_PERFCOUNTER0_LOW__DC_DISPCLK_PERFCOUNTER0_LOW__SHIFT__SI 0x00000000 -#define DC_DISPCLK_PERFCOUNTER0_SELECT__DC_DISPCLK_PERFCOUNTER0_MODE__SHIFT__SI 0x00000010 -#define DC_DISPCLK_PERFCOUNTER0_SELECT__DC_DISPCLK_PERFCOUNTER0_SELECT__SHIFT__SI 0x00000000 -#define DC_DISPCLK_PERFCOUNTER1_HI__DC_DISPCLK_PERFCOUNTER1_HI__SHIFT__SI 0x00000000 -#define DC_DISPCLK_PERFCOUNTER1_LOW__DC_DISPCLK_PERFCOUNTER1_LOW__SHIFT__SI 0x00000000 -#define DC_DISPCLK_PERFCOUNTER1_SELECT__DC_DISPCLK_PERFCOUNTER1_MODE__SHIFT__SI 0x00000010 -#define DC_DISPCLK_PERFCOUNTER1_SELECT__DC_DISPCLK_PERFCOUNTER1_SELECT__SHIFT__SI 0x00000000 -#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT__SI 0x00000000 -#define DC_DOUT_DEBUG_MUX_CNTL__DAC_MUX_SELECT__SHIFT__SI 0x00000000 -#define DC_DOUT_DEBUG_MUX_CNTL__DC_I2C_MUX_SELECT__SHIFT__SI 0x00000010 -#define DC_DOUT_DEBUG_MUX_CNTL__TMDS_DVO_MUX_SELECT__SHIFT__SI 0x00000008 -#define DC_FID_CNT__FID_ON_MARK__SHIFT__SI 0x00000000 -#define DC_GENERICA__GENERICA_EN__SHIFT__SI 0x00000000 -#define DC_GENERICA__GENERICA_SEL__SHIFT__SI 0x00000008 -#define DC_GENERICB__GENERICB_EN__SHIFT__SI 0x00000000 -#define DC_GENERICB__GENERICB_SEL__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT__SI 0x00000014 -#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT__SI 0x00000010 -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT__SI 0x00000004 -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT__SI 0x00000018 -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT__SI 0x0000000c -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT__SI 0x0000001c -#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT__SI 0x00000014 -#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT__SI 0x00000010 -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT__SI 0x00000004 -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT__SI 0x00000018 -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT__SI 0x0000000c -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT__SI 0x0000001c -#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT__SI 0x00000014 -#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT__SI 0x00000010 -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT__SI 0x00000004 -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT__SI 0x00000018 -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT__SI 0x0000000c -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT__SI 0x0000001c -#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT__SI 0x00000014 -#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT__SI 0x00000010 -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT__SI 0x00000004 -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT__SI 0x00000018 -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT__SI 0x0000000c -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT__SI 0x0000001c -#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT__SI 0x00000014 -#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT__SI 0x00000010 -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT__SI 0x00000004 -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT__SI 0x00000018 -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT__SI 0x0000000c -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT__SI 0x0000001c -#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT__SI 0x00000014 -#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT__SI 0x00000010 -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT__SI 0x00000004 -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT__SI 0x00000018 -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT__SI 0x0000000c -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT__SI 0x0000001c -#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT__SI 0x00000008 -#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT__SI 0x00000000 -#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT__SI 0x0000001c -#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT__SI 0x00000018 -#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT__SI 0x00000000 -#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT__SI 0x0000001e -#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT__SI 0x0000001c -#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT__SI 0x00000018 -#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT__SI 0x0000001e -#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT__SI 0x0000001c -#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT__SI 0x00000018 -#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT__SI 0x0000001e -#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT__SI 0x0000001c -#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT__SI 0x00000018 -#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT__SI 0x0000001e -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT__SI 0x00000000 -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT__SI 0x00000008 -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT__SI 0x00000010 -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT__SI 0x00000014 -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT__SI 0x00000015 -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT__SI 0x00000016 -#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT__SI 0x00000017 -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT__SI 0x00000010 -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT__SI 0x00000014 -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT__SI 0x00000015 -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT__SI 0x00000016 -#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT__SI 0x00000017 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT__SI 0x00000001 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT__SI 0x00000002 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT__SI 0x00000004 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT__SI 0x00000005 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT__SI 0x00000009 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT__SI 0x0000000a -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT__SI 0x0000000c -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT__SI 0x0000000d -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT__SI 0x00000010 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT__SI 0x00000011 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT__SI 0x00000012 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT__SI 0x00000014 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT__SI 0x00000015 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT__SI 0x00000016 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT__SI 0x00000018 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT__SI 0x00000019 -#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT__SI 0x0000001a -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT__SI 0x00000010 -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT__SI 0x00000014 -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT__SI 0x00000015 -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT__SI 0x00000016 -#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT__SI 0x00000017 -#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT__SI 0x00000000 -#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT__SI 0x00000008 -#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT__SI 0x00000010 -#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT__SI 0x00000018 -#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT__SI 0x0000001a -#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT__SI 0x0000001c -#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT__SI 0x00000010 -#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT__SI 0x00000018 -#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT__SI 0x0000001a -#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT__SI 0x0000001c -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT__SI 0x00000004 -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT__SI 0x00000010 -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT__SI 0x00000018 -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT__SI 0x0000001a -#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT__SI 0x0000001c -#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT__SI 0x00000010 -#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT__SI 0x00000018 -#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT__SI 0x0000001a -#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT__SI 0x0000001c -#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT__SI 0x00000018 -#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT__SI 0x0000001c -#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT__SI 0x00000010 -#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT__SI 0x00000014 -#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT__SI 0x00000000 -#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT__SI 0x00000004 -#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT__SI 0x00000000 -#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT__SI 0x00000008 -#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT__SI 0x00000010 -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT__SI 0x00000010 -#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT__SI 0x00000001 -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT__SI 0x00000004 -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT__SI 0x0000000c -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT__SI 0x00000010 -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT__SI 0x00000014 -#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT__SI 0x00000016 -#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT__SI 0x00000010 -#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT__SI 0x00000008 -#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT__SI 0x00000004 -#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT__SI 0x0000000c -#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT__SI 0x00000008 -#define DC_GPIO_SYNCB_A__DC_GPIO_HSYNCB_A__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCB_A__DC_GPIO_VSYNCB_A__SHIFT__SI 0x00000008 -#define DC_GPIO_SYNCB_EN__DC_GPIO_HSYNCB_EN__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCB_EN__DC_GPIO_VSYNCB_EN__SHIFT__SI 0x00000008 -#define DC_GPIO_SYNCB_MASK__DC_GPIO_HSYNCB_MASK__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCB_MASK__DC_GPIO_HSYNCB_PD_DIS__SHIFT__SI 0x00000004 -#define DC_GPIO_SYNCB_MASK__DC_GPIO_HSYNCB_RECV__SHIFT__SI 0x00000006 -#define DC_GPIO_SYNCB_MASK__DC_GPIO_VSYNCB_MASK__SHIFT__SI 0x00000008 -#define DC_GPIO_SYNCB_MASK__DC_GPIO_VSYNCB_PD_DIS__SHIFT__SI 0x0000000c -#define DC_GPIO_SYNCB_MASK__DC_GPIO_VSYNCB_RECV__SHIFT__SI 0x0000000e -#define DC_GPIO_SYNCB_Y__DC_GPIO_HSYNCB_Y__SHIFT__SI 0x00000000 -#define DC_GPIO_SYNCB_Y__DC_GPIO_VSYNCB_Y__SHIFT__SI 0x00000008 -#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT__SI 0x00000000 -#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT__SI 0x00000000 -#define DC_GPU_TIMER_START_POSITION__DC_GPU_TIMER_START_POSITION_P_FLIP__SHIFT__SI 0x00000010 -#define DC_GPU_TIMER_START_POSITION__DC_GPU_TIMER_START_POSITION_V_UPDATE__SHIFT__SI 0x00000000 -#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT__SI 0x00000000 -#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT__SI 0x0000001c -#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT__SI 0x00000010 -#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT__SI 0x00000000 -#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT__SI 0x00000010 -#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT__SI 0x00000008 -#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT__SI 0x00000014 -#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT__SI 0x00000018 -#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT__SI 0x00000000 -#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT__SI 0x00000008 -#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT__SI 0x00000001 -#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT__SI 0x00000000 -#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT__SI 0x0000001c -#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT__SI 0x00000010 -#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT__SI 0x00000000 -#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT__SI 0x00000010 -#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT__SI 0x00000008 -#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT__SI 0x00000014 -#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT__SI 0x00000018 -#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT__SI 0x00000000 -#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT__SI 0x00000008 -#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT__SI 0x00000001 -#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT__SI 0x00000000 -#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT__SI 0x0000001c -#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT__SI 0x00000010 -#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT__SI 0x00000000 -#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT__SI 0x00000010 -#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT__SI 0x00000008 -#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT__SI 0x00000014 -#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT__SI 0x00000018 -#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT__SI 0x00000000 -#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT__SI 0x00000008 -#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT__SI 0x00000001 -#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT__SI 0x00000000 -#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT__SI 0x0000001c -#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT__SI 0x00000010 -#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT__SI 0x00000000 -#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT__SI 0x00000010 -#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT__SI 0x00000008 -#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT__SI 0x00000014 -#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT__SI 0x00000018 -#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT__SI 0x00000000 -#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT__SI 0x00000008 -#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT__SI 0x00000001 -#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT__SI 0x00000000 -#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT__SI 0x0000001c -#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT__SI 0x00000010 -#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT__SI 0x00000000 -#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT__SI 0x00000010 -#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT__SI 0x00000008 -#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT__SI 0x00000014 -#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT__SI 0x00000018 -#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT__SI 0x00000000 -#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT__SI 0x00000008 -#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT__SI 0x00000001 -#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT__SI 0x00000000 -#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT__SI 0x0000001c -#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT__SI 0x00000010 -#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT__SI 0x00000000 -#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT__SI 0x00000010 -#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT__SI 0x00000008 -#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT__SI 0x00000014 -#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT__SI 0x00000018 -#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT__SI 0x00000000 -#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT__SI 0x00000008 -#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT__SI 0x00000001 -#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT__SI 0x00000008 -#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT__SI 0x0000000c -#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT__SI 0x00000019 -#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT__SI 0x00000018 -#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT__SI 0x00000004 -#define DC_I2C_ARBITRATION__DC_I2C_NO_RESTART_SW_GO__SHIFT__SI 0x00000005 -#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT__SI 0x00000002 -#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT__SI 0x00000015 -#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT__SI 0x00000000 -#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT__SI 0x00000014 -#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT__SI 0x0000001f -#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT__SI 0x00000008 -#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT__SI 0x00000000 -#define DC_I2C_CONTROL__DC_I2C_SDVO_ADDR_SEL__SHIFT__SI 0x00000006 -#define DC_I2C_CONTROL__DC_I2C_SDVO_EN__SHIFT__SI 0x00000004 -#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT__SI 0x00000002 -#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT__SI 0x00000001 -#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT__SI 0x00000003 -#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT__SI 0x00000014 -#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT__SI 0x00000000 -#define DC_I2C_DATA__DC_I2C_DATA__SHIFT__SI 0x00000008 -#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT__SI 0x0000001f -#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT__SI 0x00000010 -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT__SI 0x00000003 -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT__SI 0x00000010 -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT__SI 0x00000000 -#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT__SI 0x00000011 -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT__SI 0x00000007 -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT__SI 0x00000000 -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT__SI 0x00000001 -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT__SI 0x00000010 -#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT__SI 0x00000018 -#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT__SI 0x00000004 -#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT__SI 0x00000010 -#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT__SI 0x00000000 -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT__SI 0x00000003 -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT__SI 0x00000010 -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT__SI 0x00000000 -#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT__SI 0x00000011 -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT__SI 0x00000007 -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT__SI 0x00000000 -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT__SI 0x00000001 -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT__SI 0x00000010 -#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT__SI 0x00000018 -#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT__SI 0x00000004 -#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT__SI 0x00000010 -#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT__SI 0x00000000 -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT__SI 0x00000003 -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT__SI 0x00000010 -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT__SI 0x00000000 -#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT__SI 0x00000011 -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT__SI 0x00000007 -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT__SI 0x00000000 -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT__SI 0x00000001 -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT__SI 0x00000010 -#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT__SI 0x00000018 -#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT__SI 0x00000004 -#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT__SI 0x00000010 -#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT__SI 0x00000000 -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT__SI 0x00000003 -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT__SI 0x00000010 -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT__SI 0x00000000 -#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT__SI 0x00000011 -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT__SI 0x00000007 -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT__SI 0x00000000 -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT__SI 0x00000001 -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT__SI 0x00000010 -#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT__SI 0x00000018 -#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT__SI 0x00000004 -#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT__SI 0x00000010 -#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT__SI 0x00000000 -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT__SI 0x00000003 -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT__SI 0x00000010 -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT__SI 0x00000000 -#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT__SI 0x00000011 -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT__SI 0x00000007 -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT__SI 0x00000000 -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT__SI 0x00000001 -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT__SI 0x00000010 -#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT__SI 0x00000018 -#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT__SI 0x00000004 -#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT__SI 0x00000010 -#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT__SI 0x00000000 -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT__SI 0x00000003 -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT__SI 0x00000010 -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT__SI 0x00000000 -#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT__SI 0x00000011 -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT__SI 0x00000007 -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT__SI 0x00000000 -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT__SI 0x00000001 -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT__SI 0x00000010 -#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT__SI 0x00000018 -#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT__SI 0x00000004 -#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT__SI 0x00000010 -#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT__SI 0x00000000 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT__SI 0x00000005 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT__SI 0x00000004 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT__SI 0x00000006 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT__SI 0x00000009 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT__SI 0x00000008 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT__SI 0x0000000a -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT__SI 0x0000000d -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT__SI 0x0000000c -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT__SI 0x0000000e -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT__SI 0x00000011 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT__SI 0x00000010 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT__SI 0x00000012 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT__SI 0x00000015 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT__SI 0x00000014 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT__SI 0x00000016 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT__SI 0x00000019 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT__SI 0x00000018 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT__SI 0x0000001a -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT__SI 0x00000001 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT__SI 0x00000000 -#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT__SI 0x00000002 -#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT__SI 0x00000004 -#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT__SI 0x00000007 -#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT__SI 0x00000002 -#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT__SI 0x00000006 -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT__SI 0x0000000c -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT__SI 0x0000000d -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT__SI 0x0000000e -#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT__SI 0x0000000f -#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT__SI 0x00000012 -#define DC_I2C_SW_STATUS__DC_I2C_SW_SDVO_NACK__SHIFT__SI 0x0000000a -#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT__SI 0x00000000 -#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT__SI 0x00000008 -#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT__SI 0x00000005 -#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT__SI 0x00000010 -#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT__SI 0x00000000 -#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT__SI 0x0000000c -#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT__SI 0x0000000d -#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT__SI 0x00000008 -#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT__SI 0x00000010 -#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT__SI 0x00000000 -#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT__SI 0x0000000c -#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT__SI 0x0000000d -#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT__SI 0x00000008 -#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT__SI 0x00000010 -#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT__SI 0x00000000 -#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT__SI 0x0000000c -#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT__SI 0x0000000d -#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT__SI 0x00000008 -#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT__SI 0x00000010 -#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT__SI 0x00000000 -#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT__SI 0x0000000c -#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT__SI 0x0000000d -#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT__SI 0x00000008 -#define DC_LB_BLACK_KEYER_B__DC_LB_BLACK_KEYER_B__SHIFT__SI 0x00000006 -#define DC_LB_BLACK_KEYER_G__DC_LB_BLACK_KEYER_G__SHIFT__SI 0x00000006 -#define DC_LB_BLACK_KEYER_R__DC_LB_BLACK_KEYER_R__SHIFT__SI 0x00000006 -#define DC_LB_MEMORY_SPLIT__DC_LB_DISP1_END_ADR__SHIFT__SI 0x00000004 -#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_SPLIT_MODE__SHIFT__SI 0x00000002 -#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_SPLIT__SHIFT__SI 0x00000000 -#define DC_LB_MEMORY_SPLIT__DC_LB_SIZE_3840__SHIFT__SI 0x0000001c -#define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS__SHIFT__SI 0x00000010 -#define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE__SHIFT__SI 0x00000000 -#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT__SI 0x00000000 -#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT__SI 0x0000000a -#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT__SI 0x00000014 -#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT__SI 0x00000001 -#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT__SI 0x00000000 -#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT__SI 0x00000000 -#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT__SI 0x00000000 -#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT__SI 0x00000000 -#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT__SI 0x00000005 -#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT__SI 0x00000004 -#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT__SI 0x0000000d -#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT__SI 0x0000000c -#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT__SI 0x00000015 -#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT__SI 0x00000014 -#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT__SI 0x00000000 -#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT__SI 0x00000008 -#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT__SI 0x00000010 -#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT__SI 0x00000000 -#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT__SI 0x00000010 -#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT__SI 0x00000000 -#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT__SI 0x00000000 -#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT__SI 0x00000000 -#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT__SI 0x00000000 -#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT__SI 0x00000000 -#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT__SI 0x00000000 -#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT__SI 0x00000000 -#define DC_MVP_LB_CONTROL__DC_MVP_DFQ_EN__SHIFT__SI 0x00000012 -#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT__SI 0x0000001f -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT__SI 0x0000001c -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT__SI 0x0000000c -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT__SI 0x00000010 -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT__SI 0x00000008 -#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT__SI 0x00000014 -#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT__SI 0x00000000 -#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT__SI 0x00000000 -#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT__SI 0x00000004 -#define DC_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT__SI 0x00000008 -#define DC_PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT__SI 0x00000004 -#define DC_PERFMON_CNTL__PERFMON_STATE__SHIFT__SI 0x00000000 -#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT__SI 0x0000000e -#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT__SI 0x00000010 -#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT__SI 0x0000000d -#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_SOFT__SHIFT__SI 0x0000000c -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_64BAR_EN_A__SHIFT__SI 0x00000002 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_AUDIO_EN__SHIFT__SI 0x00000004 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_CLK_PM_EN__SHIFT__SI 0x00000008 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_ECN1P1_DIS__SHIFT__SI 0x00000001 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_ERR_REPORTING_DIS__SHIFT__SI 0x00000007 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_IO_BAR_DIS__SHIFT__SI 0x00000000 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_MSI_DIS__SHIFT__SI 0x00000006 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_NONLEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x00000003 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_REG_AP_SIZE_1__SHIFT__SI 0x00000005 -#define DC_PINSTRAPS__DC_PINSTRAPS_STRAP_BIF_VGA_DIS__SHIFT__SI 0x00000009 -#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_STRAP_DIS__SHIFT__SI 0x0000000a -#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT__SI 0x0000000b -#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT__SI 0x00000000 -#define DC_REF_CLK_CNTL__HSYNCB_OUTPUT_SEL__SHIFT__SI 0x00000008 -#define DC_SCLK_PERFCOUNTER0_HI__DC_SCLK_PERFCOUNTER0_HI__SHIFT__SI 0x00000000 -#define DC_SCLK_PERFCOUNTER0_LOW__DC_SCLK_PERFCOUNTER0_LOW__SHIFT__SI 0x00000000 -#define DC_SCLK_PERFCOUNTER0_SELECT__DC_SCLK_PERFCOUNTER0_MODE__SHIFT__SI 0x00000010 -#define DC_SCLK_PERFCOUNTER0_SELECT__DC_SCLK_PERFCOUNTER0_SELECT__SHIFT__SI 0x00000000 -#define DC_SCLK_PERFCOUNTER1_HI__DC_SCLK_PERFCOUNTER1_HI__SHIFT__SI 0x00000000 -#define DC_SCLK_PERFCOUNTER1_LOW__DC_SCLK_PERFCOUNTER1_LOW__SHIFT__SI 0x00000000 -#define DC_SCLK_PERFCOUNTER1_SELECT__DC_SCLK_PERFCOUNTER1_MODE__SHIFT__SI 0x00000010 -#define DC_SCLK_PERFCOUNTER1_SELECT__DC_SCLK_PERFCOUNTER1_SELECT__SHIFT__SI 0x00000000 -#define DC_STUTTER_CNTL__ALLOW_DISABLE_LB_REQ_IN_STUTTER__SHIFT__SI 0x0000000e -#define DC_STUTTER_CNTL__DC_ALLOW_NB_PSTATES_FORCE_ONE__SHIFT__SI 0x00000019 -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ALWAYS_ON_A__SHIFT__SI 0x00000007 -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ALWAYS_ON_B__SHIFT__SI 0x00000008 -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ENABLE_A__SHIFT__SI 0x00000005 -#define DC_STUTTER_CNTL__DC_MCLK_CHG_ENABLE_B__SHIFT__SI 0x00000006 -#define DC_STUTTER_CNTL__DC_STUTTER_ALWAYS_ON_A__SHIFT__SI 0x00000002 -#define DC_STUTTER_CNTL__DC_STUTTER_ALWAYS_ON_B__SHIFT__SI 0x00000003 -#define DC_STUTTER_CNTL__DC_STUTTER_ENABLE_A__SHIFT__SI 0x00000000 -#define DC_STUTTER_CNTL__DC_STUTTER_ENABLE_B__SHIFT__SI 0x00000001 -#define DC_STUTTER_CNTL__DC_STUTTER_HTIU_FORCE_ONE__SHIFT__SI 0x00000004 -#define DC_STUTTER_CNTL__DISABLE_WM_HIGH_IN_VNONACTIVE__SHIFT__SI 0x0000000c -#define DC_STUTTER_CNTL__DISP_URGENT_WHEN_NOT_ALLOW_STOP__SHIFT__SI 0x00000015 -#define DC_STUTTER_CNTL__ENABLE_2LINE_IN_COMPRESS_MODE__SHIFT__SI 0x00000018 -#define DC_STUTTER_CNTL__ENABLE_4LINE_UNCOMPRESS_MODE__SHIFT__SI 0x00000017 -#define DC_STUTTER_CNTL__IGNORE_CURSOR__SHIFT__SI 0x00000012 -#define DC_STUTTER_CNTL__IGNORE_ICON__SHIFT__SI 0x0000000f -#define DC_STUTTER_CNTL__INCLUDE_AZALIA_IN_STUTTER__SHIFT__SI 0x0000000b -#define DC_STUTTER_CNTL__NO_ALLOW_STOP_IN_START_LINE__SHIFT__SI 0x00000014 -#define DC_STUTTER_CNTL__STUTTER_FID_IN_COMPRESS_MODE__SHIFT__SI 0x00000016 -#define DC_STUTTER_CNTL__STUTTER_ON_MODE__SHIFT__SI 0x00000009 -#define DC_STUTTER_CNTL__USE_CPU_IDLE_IN_STUTTER__SHIFT__SI 0x0000000a -#define DC_STUTTER_STATUS__DC_CG_DISP1_VBI__SHIFT__SI 0x0000000c -#define DC_STUTTER_STATUS__DC_CG_DISP2_VBI__SHIFT__SI 0x0000000d -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_OCCURRED_ACK__SHIFT__SI 0x00000008 -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_OCCURRED__SHIFT__SI 0x00000004 -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_PERF_CNT_ACK__SHIFT__SI 0x00000010 -#define DC_STUTTER_STATUS__DC_CG_WM_HIGH_STATUS__SHIFT__SI 0x00000000 -#define DC_STUTTER_STATUS__DC_CG_WM_MCHANGE_OCCURRED_ACK__SHIFT__SI 0x00000009 -#define DC_STUTTER_STATUS__DC_CG_WM_MCHANGE_OCCURRED__SHIFT__SI 0x00000005 -#define DC_STUTTER_STATUS__DC_CG_WM_MCHANGE_STATUS__SHIFT__SI 0x00000001 -#define DC_STUTTER_STATUS__DC_STUTTER_MODE_EXTRA_PORTS__SHIFT__SI 0x00000018 -#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DC_TEST_DEBUG_VIP_CNTL__DC_TEST_DEBUG_VIP_BLOCK_SEL__SHIFT__SI 0x00000008 -#define DC_TEST_DEBUG_VIP_CNTL__DC_TEST_DEBUG_VIP_GROUP_SEL__SHIFT__SI 0x00000010 -#define DC_TEST_DEBUG_VIP_CNTL__DC_TEST_DEBUG_VIP_LEGACY_TEST_EN__SHIFT__SI 0x00000001 -#define DDIA_DEBUG1__DOUT_DDIA_PIXCLK__SHIFT__SI 0x00000000 -#define DDIA_DEBUG1__DOUT_DDIA_RAND_BLANKb_IN__SHIFT__SI 0x00000013 -#define DDIA_DEBUG1__DOUT_DDIA_RAND_CAP_START_IN__SHIFT__SI 0x00000001 -#define DDIA_DEBUG1__DOUT_DDIA_RAND_COLOR_IN__SHIFT__SI 0x00000002 -#define DDIA_DEBUG1__DOUT_DDIA_RAND_COLOR_OUT__SHIFT__SI 0x00000016 -#define DDIA_DEBUG1__DOUT_DDIA_RAND_HSYNC_IN__SHIFT__SI 0x00000014 -#define DDIA_DEBUG1__DOUT_DDIA_RAND_RANDOM_NUMBER__SHIFT__SI 0x0000000c -#define DDIA_DEBUG1__DOUT_DDIA_RAND_VSYNC_IN__SHIFT__SI 0x00000015 -#define DDIA_DEBUG1__DOUT_DDIA_TRUNC_SIZE__SHIFT__SI 0x00000010 -#define DDIA_DEBUG2__DOUT_DDIA_FM_BLANKb_IN__SHIFT__SI 0x00000013 -#define DDIA_DEBUG2__DOUT_DDIA_FM_CAP_START_IN__SHIFT__SI 0x00000001 -#define DDIA_DEBUG2__DOUT_DDIA_FM_COLOR_IN__SHIFT__SI 0x00000002 -#define DDIA_DEBUG2__DOUT_DDIA_FM_COLOR_OUT__SHIFT__SI 0x00000016 -#define DDIA_DEBUG2__DOUT_DDIA_FM_GL10_ON__SHIFT__SI 0x0000000e -#define DDIA_DEBUG2__DOUT_DDIA_FM_GL4_ON__SHIFT__SI 0x0000000c -#define DDIA_DEBUG2__DOUT_DDIA_FM_GL7_ON__SHIFT__SI 0x0000000d -#define DDIA_DEBUG2__DOUT_DDIA_FM_HSYNC_IN__SHIFT__SI 0x00000014 -#define DDIA_DEBUG2__DOUT_DDIA_FM_LINE_ACTIVE__SHIFT__SI 0x0000000f -#define DDIA_DEBUG2__DOUT_DDIA_FM_LINE_END__SHIFT__SI 0x00000010 -#define DDIA_DEBUG2__DOUT_DDIA_FM_VSYNC_IN__SHIFT__SI 0x00000015 -#define DDIA_DEBUG2__DOUT_DDIA_PIXCLK__SHIFT__SI 0x00000000 -#define DDIA_DEBUG2__DOUT_DDIA_RAND_SIZE__SHIFT__SI 0x00000011 -#define DDIA_DEBUG3__DOUT_DDIA_422_BLANKb_IN__SHIFT__SI 0x00000001 -#define DDIA_DEBUG3__DOUT_DDIA_422_COLOR_IN__SHIFT__SI 0x00000002 -#define DDIA_DEBUG3__DOUT_DDIA_422_COLOR_OUT__SHIFT__SI 0x0000000d -#define DDIA_DEBUG3__DOUT_DDIA_422_PHASE__SHIFT__SI 0x0000000c -#define DDIA_DEBUG3__DOUT_DDIA_CAP_START_TO_HDCP__SHIFT__SI 0x00000017 -#define DDIA_DEBUG3__DOUT_DDIA_DATA_TO_HDCP__SHIFT__SI 0x00000018 -#define DDIA_DEBUG3__DOUT_DDIA_PIXCLK__SHIFT__SI 0x00000000 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_COLOR_DE__SHIFT__SI 0x00000016 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_COLOR_IN__SHIFT__SI 0x00000004 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_COLOR_OUT__SHIFT__SI 0x0000000e -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL0_OUT__SHIFT__SI 0x00000019 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL1_OUT__SHIFT__SI 0x0000001a -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL2_OUT__SHIFT__SI 0x0000001b -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_CTL3_OUT__SHIFT__SI 0x0000001c -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_DE_IN__SHIFT__SI 0x00000003 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_HSYNC_IN__SHIFT__SI 0x00000001 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_HSYNC_OUT__SHIFT__SI 0x00000017 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_PLCTL0_IN__SHIFT__SI 0x0000000d -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_PLDEVS_OUT__SHIFT__SI 0x0000001d -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_STEREOSYNC_IN__SHIFT__SI 0x0000000c -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_VSYNC_IN__SHIFT__SI 0x00000002 -#define DDIA_DEBUG4__DOUT_DDIA_DATACP_VSYNC_OUT__SHIFT__SI 0x00000018 -#define DDIA_DEBUG4__DOUT_DDIA_PIXCLK__SHIFT__SI 0x00000000 -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_CHAR_A_IN__SHIFT__SI 0x00000001 -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_CHAR_B_IN__SHIFT__SI 0x00000002 -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_DCB__SHIFT__SI 0x0000000c -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_DE_IN__SHIFT__SI 0x00000003 -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_IN__SHIFT__SI 0x00000004 -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_COLOR_TX__SHIFT__SI 0x00000016 -#define DDIA_DEBUG5__DOUT_DDIA_ENCODER_DE_TX__SHIFT__SI 0x00000015 -#define DDIA_DEBUG5__DOUT_DDIA_PIXCLK__SHIFT__SI 0x00000000 -#define DDIA_DEBUG6__DOUT_DDIA_PIXCLK__SHIFT__SI 0x00000000 -#define DDIA_DEBUG6__DOUT_DDIA_TX_COLOR_DE_IN__SHIFT__SI 0x00000001 -#define DDIA_DEBUG6__DOUT_DDIA_TX_COLOR_IN__SHIFT__SI 0x00000002 -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL0_IN__SHIFT__SI 0x0000000c -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL1_IN__SHIFT__SI 0x0000000d -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL2_IN__SHIFT__SI 0x0000000e -#define DDIA_DEBUG6__DOUT_DDIA_TX_CTL3_IN__SHIFT__SI 0x0000000f -#define DDIA_DEBUG6__DOUT_DDIA_TX_HSYNC_IN__SHIFT__SI 0x00000014 -#define DDIA_DEBUG6__DOUT_DDIA_TX_PLPIXA_OUT__SHIFT__SI 0x00000016 -#define DDIA_DEBUG6__DOUT_DDIA_TX_VSYNC_IN__SHIFT__SI 0x00000015 -#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 -#define DEBUG_DRM_MASK_0__DRM_RTN_MASK0__SHIFT__SI 0x00000000 -#define DEBUG_DRM_MASK_1__DRM_RTN_MASK1__SHIFT__SI 0x00000000 -#define DEBUG_DRM_MASK_2__DRM_RTN_MASK2__SHIFT__SI 0x00000000 -#define DEBUG_DRM_MASK_3__DRM_RTN_MASK3__SHIFT__SI 0x00000000 -#define DEBUG_ENCRYP_COEF_0__ENCRYP_COEF0__SHIFT__SI 0x00000000 -#define DEBUG_ENCRYP_COEF_1__ENCRYP_COEF1__SHIFT__SI 0x00000000 -#define DEBUG_ENCRYP_COEF_2__ENCRYP_COEF2__SHIFT__SI 0x00000000 -#define DEBUG_ENCRYP_COEF_3__ENCRYP_COEF3__SHIFT__SI 0x00000000 -#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x00000000 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT__SI 0x00000011 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT__SI 0x00000010 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT__SI 0x00000012 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT__SI 0x00000008 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT__SI 0x00000000 -#define DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT__SI 0x00000000 -#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT__CI__VI 0x00000005 -#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUP__SHIFT__SI 0x00000004 -#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT__CI__VI 0x00000000 -#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUP__SHIFT__SI 0x00000000 -#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT__CI__VI 0x00000015 -#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT__CI__VI 0x00000014 -#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT__CI__VI 0x00000016 -#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x00000012 -#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x0000001a -#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x00000005 -#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x0000001c -#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x00000006 -#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x00000009 -#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x00000000 -#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x00000003 -#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0x0000000f -#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT__CI__VI 0x00000005 -#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x00000004 -#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x00000000 -#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT__CI__VI 0x0000000f -#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0x0000000a -#define DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT__SI 0x0000000f -#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x00000000 -#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x00000008 -#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x00000002 -#define DEVICE_CNTL__INITIATE_FLR__SHIFT__CI__VI 0x0000000f -#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x00000005 -#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT__CI__VI 0x0000000c -#define DEVICE_CNTL__MAX_REQUEST_SIZE__SHIFT__SI 0x0000000c -#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x00000001 -#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0x0000000b -#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x00000009 -#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x00000004 -#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x00000003 -#define DEVICE_ID__DEVICE_ID__SHIFT 0x00000000 -#define DEVICE_STATUS2__RESERVED__SHIFT 0x00000000 -#define DEVICE_STATUS__AUX_PWR__SHIFT 0x00000004 -#define DEVICE_STATUS__CORR_ERR__SHIFT 0x00000000 -#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x00000002 -#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x00000001 -#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x00000005 -#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x00000003 -#define DFT_CLK_STOP_COUNTER_LSB__DELAY__SHIFT__CI__VI 0x00000000 -#define DFT_CLK_STOP_COUNTER_MSB__DELAY__SHIFT__CI__VI 0x00000000 -#define DFT_CLK_STOP_COUNTER_MSB__ENABLE__SHIFT__CI__VI 0x0000001c -#define DFT_CLK_STOP_COUNTER_MSB__LOAD__SHIFT__CI__VI 0x0000001d -#define DFT_CLK_STOP_COUNTER_MSB__MISC__SHIFT__CI__VI 0x0000001e -#define DFT_CLK_STOP__MAGIC_CODE__SHIFT__CI__VI 0x00000000 -#define DH_TEST__DH_TEST__SHIFT 0x00000000 -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT__CI__VI 0x00000005 -#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT__CI__VI 0x00000000 -#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT__CI__VI 0x00000004 -#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT__CI__VI 0x00000002 -#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT__CI__VI 0x00000001 -#define DIDT_DB_CTRL1__MAX_POWER__SHIFT__CI__VI 0x00000010 -#define DIDT_DB_CTRL1__MIN_POWER__SHIFT__CI__VI 0x00000000 -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT__CI__VI 0x0000001b -#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT__CI__VI 0x00000000 -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT__CI__VI 0x00000010 -#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT__CI__VI 0x00000000 -#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT__CI__VI 0x00000008 -#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT__CI__VI 0x00000010 -#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT__CI__VI 0x00000018 -#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT__CI__VI 0x00000000 -#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT__CI__VI 0x00000008 -#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT__CI__VI 0x00000010 -#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT__CI__VI 0x00000018 -#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT__CI__VI 0x00000010 -#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT__CI__VI 0x00000018 -#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT__CI__VI 0x00000000 -#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT__CI__VI 0x00000008 -#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT__CI__VI 0x00000000 -#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT__CI__VI 0x00000000 -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT__CI__VI 0x00000005 -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT__CI__VI 0x00000000 -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT__CI__VI 0x00000004 -#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT__CI__VI 0x00000002 -#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT__CI__VI 0x00000001 -#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT__CI__VI 0x00000010 -#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT__CI__VI 0x00000000 -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT__CI__VI 0x0000001b -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT__CI__VI 0x00000000 -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT__CI__VI 0x00000010 -#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT__CI__VI 0x00000000 -#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT__CI__VI 0x00000008 -#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT__CI__VI 0x00000010 -#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT__CI__VI 0x00000018 -#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT__CI__VI 0x00000000 -#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT__CI__VI 0x00000008 -#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT__CI__VI 0x00000010 -#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT__CI__VI 0x00000018 -#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT__CI__VI 0x00000010 -#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT__CI__VI 0x00000018 -#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT__CI__VI 0x00000000 -#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT__CI__VI 0x00000008 -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT__CI__VI 0x00000005 -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT__CI__VI 0x00000000 -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT__CI__VI 0x00000004 -#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT__CI__VI 0x00000002 -#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT__CI__VI 0x00000001 -#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT__CI__VI 0x00000010 -#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT__CI__VI 0x00000000 -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT__CI__VI 0x0000001b -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT__CI__VI 0x00000000 -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT__CI__VI 0x00000010 -#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT__CI__VI 0x00000000 -#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT__CI__VI 0x00000008 -#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT__CI__VI 0x00000010 -#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT__CI__VI 0x00000018 -#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT__CI__VI 0x00000000 -#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT__CI__VI 0x00000008 -#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT__CI__VI 0x00000010 -#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT__CI__VI 0x00000018 -#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT__CI__VI 0x00000010 -#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT__CI__VI 0x00000018 -#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT__CI__VI 0x00000000 -#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT__CI__VI 0x00000008 -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT__CI__VI 0x00000005 -#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT__CI__VI 0x00000000 -#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT__CI__VI 0x00000004 -#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT__CI__VI 0x00000002 -#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT__CI__VI 0x00000001 -#define DIDT_TD_CTRL1__MAX_POWER__SHIFT__CI__VI 0x00000010 -#define DIDT_TD_CTRL1__MIN_POWER__SHIFT__CI__VI 0x00000000 -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT__CI__VI 0x0000001b -#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT__CI__VI 0x00000000 -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT__CI__VI 0x00000010 -#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT__CI__VI 0x00000000 -#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT__CI__VI 0x00000008 -#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT__CI__VI 0x00000010 -#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT__CI__VI 0x00000018 -#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT__CI__VI 0x00000000 -#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT__CI__VI 0x00000008 -#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT__CI__VI 0x00000010 -#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT__CI__VI 0x00000018 -#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT__CI__VI 0x00000010 -#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT__CI__VI 0x00000018 -#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT__CI__VI 0x00000000 -#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT__CI__VI 0x00000008 -#define DIGA_CLOCK_ENABLE__DIGA_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_CAPTURE_START__SHIFT__SI 0x00000017 -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_COLOR_IN__SHIFT__SI 0x00000002 -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_COLOR_OUT__SHIFT__SI 0x00000018 -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_HBLANKB__SHIFT__SI 0x00000001 -#define DIGA_DEBUG3__DOUT_DIGA_MAPPER_PHASE__SHIFT__SI 0x00000000 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_COLOR_DE__SHIFT__SI 0x00000016 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_COLOR_IN__SHIFT__SI 0x00000004 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_COLOR_OUT__SHIFT__SI 0x0000000e -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL0_OUT__SHIFT__SI 0x00000019 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL1_OUT__SHIFT__SI 0x0000001a -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL2_OUT__SHIFT__SI 0x0000001b -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_CTL3_OUT__SHIFT__SI 0x0000001c -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_DE_IN__SHIFT__SI 0x00000003 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_HSYNC_IN__SHIFT__SI 0x00000001 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_HSYNC_OUT__SHIFT__SI 0x00000017 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_PLCTL0_IN__SHIFT__SI 0x0000000d -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_PLDEVS_OUT__SHIFT__SI 0x0000001d -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_STEREOSYNC_IN__SHIFT__SI 0x0000000c -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_VSYNC_IN__SHIFT__SI 0x00000002 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_DATACP_VSYNC_OUT__SHIFT__SI 0x00000018 -#define DIGA_DEBUG4__DOUT_DIGA_TMDS_PIXCLK__SHIFT__SI 0x00000000 -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_CHAR_A_IN__SHIFT__SI 0x00000001 -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_CHAR_B_IN__SHIFT__SI 0x00000002 -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_DCB__SHIFT__SI 0x0000000c -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_DE_IN__SHIFT__SI 0x00000003 -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_IN__SHIFT__SI 0x00000004 -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_COLOR_TX__SHIFT__SI 0x00000016 -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_ENCODER_DE_TX__SHIFT__SI 0x00000015 -#define DIGA_DEBUG5__DOUT_DIGA_TMDS_PIXCLK__SHIFT__SI 0x00000000 -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_PIXCLK__SHIFT__SI 0x00000000 -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_COLOR_DE_IN__SHIFT__SI 0x00000001 -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_COLOR_IN__SHIFT__SI 0x00000002 -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL0_IN__SHIFT__SI 0x0000000c -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL1_IN__SHIFT__SI 0x0000000d -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL2_IN__SHIFT__SI 0x0000000e -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_CTL3_IN__SHIFT__SI 0x0000000f -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_HSYNC_IN__SHIFT__SI 0x00000014 -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_PLPIXA_OUT__SHIFT__SI 0x00000016 -#define DIGA_DEBUG6__DOUT_DIGA_TMDS_TX_VSYNC_IN__SHIFT__SI 0x00000015 -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_DE__SHIFT__SI 0x0000000d -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_HALF_CLK_PHASE__SHIFT__SI 0x0000000e -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_PANEL_COLOR_IN__SHIFT__SI 0x00000004 -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_PANEL_DE_IN__SHIFT__SI 0x00000001 -#define DIGA_DEBUG7__DOUT_DIGA_LVDS_TEST_DATA__SHIFT__SI 0x00000010 -#define DIGA_DEBUG7__DOUT_DIGA_PIXCLK1__SHIFT__SI 0x0000000c -#define DIGA_DEBUG7__DOUT_DIGA_PIXCLK__SHIFT__SI 0x00000000 -#define DIGA_DEBUG7__DOUT_DIGA_PM_PWRSEQ_TARGET_STATE__SHIFT__SI 0x00000018 -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_BLON__SHIFT__SI 0x0000001e -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_DIGON__SHIFT__SI 0x0000001d -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_DONE__SHIFT__SI 0x0000001f -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_REF__SHIFT__SI 0x0000001a -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_SYNCEN__SHIFT__SI 0x0000001c -#define DIGA_DEBUG7__DOUT_DIGA_PWRSEQ_TARGET_STATE__SHIFT__SI 0x00000019 -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DCLOCK1__SHIFT__SI 0x0000000f -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DCLOCK__SHIFT__SI 0x00000003 -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DE1__SHIFT__SI 0x0000000d -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DE__SHIFT__SI 0x00000001 -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DTMG_CTL2__SHIFT__SI 0x0000001c -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_DTMG__SHIFT__SI 0x00000018 -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_ENABLE_DCLOCK1__SHIFT__SI 0x0000000e -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_ENABLE_DCLOCK__SHIFT__SI 0x00000002 -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_HSYNC_CTL0__SHIFT__SI 0x0000001e -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_HSYNC__SHIFT__SI 0x0000001a -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_LINK0_COLOR__SHIFT__SI 0x00000004 -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_LINK1_COLOR__SHIFT__SI 0x00000010 -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_VSYNC_CTL1__SHIFT__SI 0x0000001d -#define DIGA_DEBUG8__DOUT_DIGA_LVDS_VSYNC__SHIFT__SI 0x00000019 -#define DIGA_DEBUG8__DOUT_DIGA_PIXCLK1__SHIFT__SI 0x0000000c -#define DIGA_DEBUG8__DOUT_DIGA_PIXCLK__SHIFT__SI 0x00000000 -#define DIGA_HDCP_DEBUG_INFO__DIGA_HDCP_DEBUG_INFO__SHIFT__SI 0x00000000 -#define DIGA_LINK_CNTL__DIGA_CHANNEL0_INVERT__SHIFT__SI 0x0000000c -#define DIGA_LINK_CNTL__DIGA_CHANNEL1_INVERT__SHIFT__SI 0x0000000d -#define DIGA_LINK_CNTL__DIGA_CHANNEL2_INVERT__SHIFT__SI 0x0000000e -#define DIGA_LINK_CNTL__DIGA_CHANNEL3_INVERT__SHIFT__SI 0x0000000f -#define DIGA_LINK_CNTL__DIGA_MINIMUM_PIXVLD_LOW_DURATION__SHIFT__SI 0x00000008 -#define DIGA_LINK_CNTL__DIGA_PFREQCHG__SHIFT__SI 0x00000000 -#define DIGA_LINK_CNTL__DIGA_PIXVLD_RESET__SHIFT__SI 0x00000004 -#define DIGA_LINK_CNTL__DIGA_XBAR_SELECT__SHIFT__SI 0x00000010 -#define DIGA_TRANSMITTER_ENABLE__DIGA_CLK_EN__SHIFT__SI 0x00000008 -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE0EN__SHIFT__SI 0x00000000 -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE1EN__SHIFT__SI 0x00000001 -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE2EN__SHIFT__SI 0x00000002 -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANE3EN__SHIFT__SI 0x00000003 -#define DIGA_TRANSMITTER_ENABLE__DIGA_LANEEN_HPD_MASK__SHIFT__SI 0x00000010 -#define DIGB_CLOCK_ENABLE__DIGB_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_CAPTURE_START__SHIFT__SI 0x00000017 -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_COLOR_IN__SHIFT__SI 0x00000002 -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_COLOR_OUT__SHIFT__SI 0x00000018 -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_HBLANKB__SHIFT__SI 0x00000001 -#define DIGB_DEBUG3__DOUT_DIGB_MAPPER_PHASE__SHIFT__SI 0x00000000 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_COLOR_DE__SHIFT__SI 0x00000016 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_COLOR_IN__SHIFT__SI 0x00000004 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_COLOR_OUT__SHIFT__SI 0x0000000e -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL0_OUT__SHIFT__SI 0x00000019 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL1_OUT__SHIFT__SI 0x0000001a -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL2_OUT__SHIFT__SI 0x0000001b -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_CTL3_OUT__SHIFT__SI 0x0000001c -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_DE_IN__SHIFT__SI 0x00000003 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_HSYNC_IN__SHIFT__SI 0x00000001 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_HSYNC_OUT__SHIFT__SI 0x00000017 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_PLCTL0_IN__SHIFT__SI 0x0000000d -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_PLDEVS_OUT__SHIFT__SI 0x0000001d -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_STEREOSYNC_IN__SHIFT__SI 0x0000000c -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_VSYNC_IN__SHIFT__SI 0x00000002 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_DATACP_VSYNC_OUT__SHIFT__SI 0x00000018 -#define DIGB_DEBUG4__DOUT_DIGB_TMDS_PIXCLK__SHIFT__SI 0x00000000 -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_CHAR_A_IN__SHIFT__SI 0x00000001 -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_CHAR_B_IN__SHIFT__SI 0x00000002 -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_DCB__SHIFT__SI 0x0000000c -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_DE_IN__SHIFT__SI 0x00000003 -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_IN__SHIFT__SI 0x00000004 -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_COLOR_TX__SHIFT__SI 0x00000016 -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_ENCODER_DE_TX__SHIFT__SI 0x00000015 -#define DIGB_DEBUG5__DOUT_DIGB_TMDS_PIXCLK__SHIFT__SI 0x00000000 -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_PIXCLK__SHIFT__SI 0x00000000 -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_COLOR_DE_IN__SHIFT__SI 0x00000001 -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_COLOR_IN__SHIFT__SI 0x00000002 -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL0_IN__SHIFT__SI 0x0000000c -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL1_IN__SHIFT__SI 0x0000000d -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL2_IN__SHIFT__SI 0x0000000e -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_CTL3_IN__SHIFT__SI 0x0000000f -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_HSYNC_IN__SHIFT__SI 0x00000014 -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_PLPIXA_OUT__SHIFT__SI 0x00000016 -#define DIGB_DEBUG6__DOUT_DIGB_TMDS_TX_VSYNC_IN__SHIFT__SI 0x00000015 -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_DE__SHIFT__SI 0x0000000d -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_HALF_CLK_PHASE__SHIFT__SI 0x0000000e -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_PANEL_COLOR_IN__SHIFT__SI 0x00000004 -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_PANEL_DE_IN__SHIFT__SI 0x00000001 -#define DIGB_DEBUG7__DOUT_DIGB_LVDS_TEST_DATA__SHIFT__SI 0x00000010 -#define DIGB_DEBUG7__DOUT_DIGB_PIXCLK1__SHIFT__SI 0x0000000c -#define DIGB_DEBUG7__DOUT_DIGB_PIXCLK__SHIFT__SI 0x00000000 -#define DIGB_DEBUG7__DOUT_DIGB_PM_PWRSEQ_TARGET_STATE__SHIFT__SI 0x00000018 -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_BLON__SHIFT__SI 0x0000001e -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_DIGON__SHIFT__SI 0x0000001d -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_DONE__SHIFT__SI 0x0000001f -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_REF__SHIFT__SI 0x0000001a -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_SYNCEN__SHIFT__SI 0x0000001c -#define DIGB_DEBUG7__DOUT_DIGB_PWRSEQ_TARGET_STATE__SHIFT__SI 0x00000019 -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DCLOCK1__SHIFT__SI 0x0000000f -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DCLOCK__SHIFT__SI 0x00000003 -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DE1__SHIFT__SI 0x0000000d -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DE__SHIFT__SI 0x00000001 -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DTMG_CTL2__SHIFT__SI 0x0000001c -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_DTMG__SHIFT__SI 0x00000018 -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_ENABLE_DCLOCK1__SHIFT__SI 0x0000000e -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_ENABLE_DCLOCK__SHIFT__SI 0x00000002 -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_HSYNC_CTL0__SHIFT__SI 0x0000001e -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_HSYNC__SHIFT__SI 0x0000001a -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_LINK0_COLOR__SHIFT__SI 0x00000004 -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_LINK1_COLOR__SHIFT__SI 0x00000010 -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_VSYNC_CTL1__SHIFT__SI 0x0000001d -#define DIGB_DEBUG8__DOUT_DIGB_LVDS_VSYNC__SHIFT__SI 0x00000019 -#define DIGB_DEBUG8__DOUT_DIGB_PIXCLK1__SHIFT__SI 0x0000000c -#define DIGB_DEBUG8__DOUT_DIGB_PIXCLK__SHIFT__SI 0x00000000 -#define DIGB_HDCP_DEBUG_INFO__DIGB_HDCP_DEBUG_INFO__SHIFT__SI 0x00000000 -#define DIGB_LINK_CNTL__DIGB_CHANNEL0_INVERT__SHIFT__SI 0x0000000c -#define DIGB_LINK_CNTL__DIGB_CHANNEL1_INVERT__SHIFT__SI 0x0000000d -#define DIGB_LINK_CNTL__DIGB_CHANNEL2_INVERT__SHIFT__SI 0x0000000e -#define DIGB_LINK_CNTL__DIGB_CHANNEL3_INVERT__SHIFT__SI 0x0000000f -#define DIGB_LINK_CNTL__DIGB_MINIMUM_PIXVLD_LOW_DURATION__SHIFT__SI 0x00000008 -#define DIGB_LINK_CNTL__DIGB_PFREQCHG__SHIFT__SI 0x00000000 -#define DIGB_LINK_CNTL__DIGB_PIXVLD_RESET__SHIFT__SI 0x00000004 -#define DIGB_LINK_CNTL__DIGB_XBAR_SELECT__SHIFT__SI 0x00000010 -#define DIGB_TRANSMITTER_ENABLE__DIGB_CLK_EN__SHIFT__SI 0x00000008 -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE0EN__SHIFT__SI 0x00000000 -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE1EN__SHIFT__SI 0x00000001 -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE2EN__SHIFT__SI 0x00000002 -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANE3EN__SHIFT__SI 0x00000003 -#define DIGB_TRANSMITTER_ENABLE__DIGB_LANEEN_HPD_MASK__SHIFT__SI 0x00000010 -#define DIGC_CLOCK_ENABLE__DIGC_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DIGD_CLOCK_ENABLE__DIGD_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DIGE_CLOCK_ENABLE__DIGE_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DIGF_CLOCK_ENABLE__DIGF_CLOCK_ENABLE__SHIFT__SI 0x00000000 -#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT__SI 0x00000000 -#define DIG_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT__SI 0x00000010 -#define DIG_CNTL__DIG_ENABLE__SHIFT__SI 0x00000008 -#define DIG_CNTL__DIG_HPD_SELECT__SHIFT__SI 0x0000001c -#define DIG_CNTL__DIG_MODE__SHIFT__SI 0x0000000c -#define DIG_CNTL__DIG_RB_SWITCH_EN__SHIFT__SI 0x00000014 -#define DIG_CNTL__DIG_SOURCE_SELECT__SHIFT__SI 0x00000000 -#define DIG_CNTL__DIG_START__SHIFT__SI 0x0000000a -#define DIG_CNTL__DIG_STEREOSYNC_SELECT__SHIFT__SI 0x00000004 -#define DIG_CNTL__DIG_SWAP__SHIFT__SI 0x00000012 -#define DIG_DEBUG__DIG_DEBUG__SHIFT__SI 0x00000000 -#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT__SI 0x00000008 -#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT__SI 0x00000000 -#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT__SI 0x00000004 -#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT__SI 0x00000000 -#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT__SI 0x00000000 -#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT__SI 0x00000018 -#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT__SI 0x00000001 -#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT__SI 0x00000004 -#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT__SI 0x00000005 -#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT__SI 0x00000010 -#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT__SI 0x00000006 -#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT__SI 0x00000000 -#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT__SI 0x00000008 -#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT__SI 0x00000002 -#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT__SI 0x00000004 -#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT__SI 0x00000000 -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_CRTC0_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_DCP0_PIXPIPE_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_DCP0_REQ_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_SCL0_ALU_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCFE0_SOFT_RESET__DISPCLK_SCL0_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_CRTC1_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_DCP1_PIXPIPE_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_DCP1_REQ_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_SCL1_ALU_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCFE1_SOFT_RESET__DISPCLK_SCL1_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_CRTC2_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_DCP2_PIXPIPE_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_DCP2_REQ_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_SCL2_ALU_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCFE2_SOFT_RESET__DISPCLK_SCL2_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_CRTC3_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_DCP3_PIXPIPE_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_DCP3_REQ_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_SCL3_ALU_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCFE3_SOFT_RESET__DISPCLK_SCL3_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_CRTC4_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_DCP4_PIXPIPE_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_DCP4_REQ_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_SCL4_ALU_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCFE4_SOFT_RESET__DISPCLK_SCL4_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_CRTC5_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_DCP5_PIXPIPE_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_DCP5_REQ_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_SCL5_ALU_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCFE5_SOFT_RESET__DISPCLK_SCL5_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF0_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF1_SOFT_RESET__SHIFT__SI 0x00000005 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF2_SOFT_RESET__SHIFT__SI 0x00000006 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF3_SOFT_RESET__SHIFT__SI 0x00000007 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF4_SOFT_RESET__SHIFT__SI 0x00000008 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_DMIF5_SOFT_RESET__SHIFT__SI 0x00000009 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_FBC_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_M_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_VGA_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCI_SOFT_RESET__DISPCLK_VIP_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_ABM_SOFT_RESET__SHIFT__SI 0x00000015 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DACA_SOFT_RESET__SHIFT__SI 0x00000010 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DACB_SOFT_RESET__SHIFT__SI 0x00000011 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGA_SOFT_RESET__SHIFT__SI 0x00000008 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGB_SOFT_RESET__SHIFT__SI 0x00000009 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGC_SOFT_RESET__SHIFT__SI 0x0000000a -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGD_SOFT_RESET__SHIFT__SI 0x0000000b -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGE_SOFT_RESET__SHIFT__SI 0x0000000c -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DIGF_SOFT_RESET__SHIFT__SI 0x0000000d -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DISPOUT_SOFT_RESET__SHIFT__SI 0x00000014 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_DVO_SOFT_RESET__SHIFT__SI 0x00000012 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT0_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT1_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT2_SOFT_RESET__SHIFT__SI 0x00000002 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT3_SOFT_RESET__SHIFT__SI 0x00000003 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT4_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPCLK_DCO_SOFT_RESET__DISPCLK_FMT5_SOFT_RESET__SHIFT__SI 0x00000005 -#define DISPOUT_DEBUG_ID__DEBUG_ID__SHIFT__SI 0x00000000 -#define DISPOUT_SOFT_RESET__DACACLK_SOFT_RESET__SHIFT__SI 0x00000000 -#define DISPOUT_SOFT_RESET__DACBCLK_SOFT_RESET__SHIFT__SI 0x00000001 -#define DISPOUT_SOFT_RESET__DVO_ENABLE_RST__SHIFT__SI 0x00000003 -#define DISPOUT_SOFT_RESET__MVP_CLKA_SOFT_RESET__SHIFT__SI 0x00000010 -#define DISPOUT_SOFT_RESET__MVP_CLKB_SOFT_RESET__SHIFT__SI 0x00000011 -#define DISPOUT_SOFT_RESET__PCLK_TVOUT_SOFT_RESET__SHIFT__SI 0x00000014 -#define DISPOUT_SOFT_RESET__SOFT_RESET_DVO__SHIFT__SI 0x00000002 -#define DISPOUT_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT__SI 0x0000001c -#define DISPOUT_SOFT_RESET__SYMCLKA_DSYNC_SOFT_RESET__SHIFT__SI 0x00000005 -#define DISPOUT_SOFT_RESET__SYMCLKA_SOFT_RESET__SHIFT__SI 0x00000004 -#define DISPOUT_SOFT_RESET__SYMCLKB_DSYNC_SOFT_RESET__SHIFT__SI 0x00000007 -#define DISPOUT_SOFT_RESET__SYMCLKB_SOFT_RESET__SHIFT__SI 0x00000006 -#define DISPOUT_SOFT_RESET__SYMCLKC_DSYNC_SOFT_RESET__SHIFT__SI 0x00000009 -#define DISPOUT_SOFT_RESET__SYMCLKC_SOFT_RESET__SHIFT__SI 0x00000008 -#define DISPOUT_SOFT_RESET__SYMCLKD_DSYNC_SOFT_RESET__SHIFT__SI 0x0000000b -#define DISPOUT_SOFT_RESET__SYMCLKD_SOFT_RESET__SHIFT__SI 0x0000000a -#define DISPOUT_SOFT_RESET__SYMCLKE_DSYNC_SOFT_RESET__SHIFT__SI 0x0000000d -#define DISPOUT_SOFT_RESET__SYMCLKE_SOFT_RESET__SHIFT__SI 0x0000000c -#define DISPOUT_SOFT_RESET__SYMCLKF_DSYNC_SOFT_RESET__SHIFT__SI 0x0000000f -#define DISPOUT_SOFT_RESET__SYMCLKF_SOFT_RESET__SHIFT__SI 0x0000000e -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX1_LS_DONE_INTERRUPT__SHIFT__SI 0x00000006 -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX1_SW_DONE_INTERRUPT__SHIFT__SI 0x00000005 -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX2_LS_DONE_INTERRUPT__SHIFT__SI 0x00000008 -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX2_SW_DONE_INTERRUPT__SHIFT__SI 0x00000007 -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT__SI 0x0000000a -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT__SI 0x00000009 -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX4_LS_DONE_INTERRUPT__SHIFT__SI 0x0000000c -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX4_SW_DONE_INTERRUPT__SHIFT__SI 0x0000000b -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX5_LS_DONE_INTERRUPT__SHIFT__SI 0x00000010 -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX5_SW_DONE_INTERRUPT__SHIFT__SI 0x0000000f -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX6_LS_DONE_INTERRUPT__SHIFT__SI 0x00000012 -#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX6_SW_DONE_INTERRUPT__SHIFT__SI 0x00000011 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DACA_CAPTURE_START_INTERRUPT__SHIFT__SI 0x00000017 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DACB_CAPTURE_START_INTERRUPT__SHIFT__SI 0x00000018 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT__SI 0x00000000 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD5_INTERRUPT__SHIFT__SI 0x00000013 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD5_RX_INTERRUPT__SHIFT__SI 0x00000014 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD6_INTERRUPT__SHIFT__SI 0x00000015 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD6_RX_INTERRUPT__SHIFT__SI 0x00000016 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_CAPTURE_START_INTERRUPT__SHIFT__SI 0x00000019 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT__SI \ - 0x0000000d -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT__SHIFT__SI 0x00000002 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT__SI 0x00000001 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_CAPTURE_START_INTERRUPT__SHIFT__SI 0x0000001a -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT__SI \ - 0x0000000e -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT__SHIFT__SI 0x00000004 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT__SI 0x00000003 -#define DISP_INTERRUPT_STATUS_CONTINUE2__DVOA_CAPTURE_START_INTERRUPT__SHIFT__SI 0x0000001b -#define DISP_INTERRUPT_STATUS_CONTINUE__D1MODE_DATA_UNDERFLOW_INTERRUPT__SHIFT__SI 0x00000010 -#define DISP_INTERRUPT_STATUS_CONTINUE__D1MODE_REQUEST_UNDERFLOW_INTERRUPT__SHIFT__SI 0x00000011 -#define DISP_INTERRUPT_STATUS_CONTINUE__D1SCL_DATA_UNDERFLOW_INTERRUPT__SHIFT__SI 0x00000012 -#define DISP_INTERRUPT_STATUS_CONTINUE__D1SCL_HOST_CONFLICT_INTERRUPT__SHIFT__SI 0x00000013 -#define DISP_INTERRUPT_STATUS_CONTINUE__D2MODE_DATA_UNDERFLOW_INTERRUPT__SHIFT__SI 0x00000014 -#define DISP_INTERRUPT_STATUS_CONTINUE__D2MODE_REQUEST_UNDERFLOW_INTERRUPT__SHIFT__SI 0x00000015 -#define DISP_INTERRUPT_STATUS_CONTINUE__D2SCL_DATA_UNDERFLOW_INTERRUPT__SHIFT__SI 0x00000016 -#define DISP_INTERRUPT_STATUS_CONTINUE__D2SCL_HOST_CONFLICT_INTERRUPT__SHIFT__SI 0x00000017 -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD1_RX_INTERRUPT__SHIFT__SI 0x0000001d -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT__SI 0x0000001e -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD3_INTERRUPT__SHIFT__SI 0x0000001c -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD4_INTERRUPT__SHIFT__SI 0x0000000e -#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD4_RX_INTERRUPT__SHIFT__SI 0x0000000f -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_AUTH_FAIL_INTERRUPT__SHIFT__SI 0x00000005 -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT__SI 0x00000004 -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT__SI 0x00000007 -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGA_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT__SI 0x00000006 -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_FAIL_INTERRUPT__SHIFT__SI 0x00000009 -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT__SI 0x00000008 -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT__SI 0x0000000b -#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT__SI 0x0000000a -#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT__SI 0x0000001f -#define DISP_INTERRUPT_STATUS_CONTINUE__DMCU_SCP_INT__SHIFT__SI 0x00000001 -#define DISP_INTERRUPT_STATUS_CONTINUE__HDMI0_ERROR_INTERRUPT__SHIFT__SI 0x0000001a -#define DISP_INTERRUPT_STATUS_CONTINUE__HDMI1_ERROR_INTERRUPT__SHIFT__SI 0x0000001b -#define DISP_INTERRUPT_STATUS_CONTINUE__MVP_FIFO_ERROR_INTERRUPT__SHIFT__SI 0x00000018 -#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT__SI 0x0000001e -#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT__SI 0x0000001c -#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT__SI 0x0000001d -#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT__SI 0x00000008 -#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT__SI 0x00000007 -#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT__SI 0x00000019 -#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT__SI 0x00000006 -#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT__SI 0x00000009 -#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT__SI 0x0000000a -#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT__SI 0x00000017 -#define DISP_INTERRUPT_STATUS__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT__SI 0x0000000d -#define DISP_INTERRUPT_STATUS__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT__SI 0x0000000c -#define DISP_INTERRUPT_STATUS__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT__SI 0x0000001a -#define DISP_INTERRUPT_STATUS__CRTC2_SNAPSHOT_INTERRUPT__SHIFT__SI 0x0000000b -#define DISP_INTERRUPT_STATUS__CRTC2_TRIGA_INTERRUPT__SHIFT__SI 0x0000000e -#define DISP_INTERRUPT_STATUS__CRTC2_TRIGB_INTERRUPT__SHIFT__SI 0x0000000f -#define DISP_INTERRUPT_STATUS__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT__SI 0x00000018 -#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT__SI 0x00000010 -#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT__SI 0x00000011 -#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT__SI 0x00000012 -#define DISP_INTERRUPT_STATUS__DC_HPD2_INTERRUPT__SHIFT__SI 0x00000013 -#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT__SI 0x00000015 -#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT__SI 0x00000014 -#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT__SI 0x0000001f -#define DISP_INTERRUPT_STATUS__DISP_TIMER_INTERRUPT__SHIFT__SI 0x00000016 -#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT__SI 0x0000001b -#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT__SI 0x00000004 -#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT__SI 0x00000002 -#define DISP_INTERRUPT_STATUS__LB_D2_VBLANK_INTERRUPT__SHIFT__SI 0x00000005 -#define DISP_INTERRUPT_STATUS__LB_D2_VLINE_INTERRUPT__SHIFT__SI 0x00000003 -#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT__SI 0x00000000 -#define DISP_INTERRUPT_STATUS__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT__SI 0x00000001 -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT__SI 0x00000000 -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT__SI 0x00000019 -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT__SI 0x0000001b -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT__SI 0x0000001a -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT__SI 0x0000001d -#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT__SI 0x0000001c -#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT__SI 0x0000001e -#define DLL_CNTL__DLL_LOCK_TIME__SHIFT__SI__CI 0x0000000c -#define DLL_CNTL__DLL_RESET_TIME__SHIFT__SI__CI 0x00000000 -#define DLL_CNTL__MRDCK0_BYPASS__SHIFT__SI__CI 0x00000018 -#define DLL_CNTL__MRDCK1_BYPASS__SHIFT__SI__CI 0x00000019 -#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT__SI 0x00000000 -#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT__SI 0x00000007 -#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT__SI \ - 0x00000001 -#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT__SI 0x00000000 -#define DMA_VIP0_TABLE_ADDR__DMA_VIPH_TABLE_ADDR__SHIFT__SI 0x00000000 -#define DMA_VIP1_TABLE_ADDR__DMA_VIPH_TABLE_ADDR__SHIFT__SI 0x00000000 -#define DMA_VIP2_TABLE_ADDR__DMA_VIPH_TABLE_ADDR__SHIFT__SI 0x00000000 -#define DMA_VIP3_TABLE_ADDR__DMA_VIPH_TABLE_ADDR__SHIFT__SI 0x00000000 -#define DMA_VIPH0_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT__SHIFT__SI 0x00000000 -#define DMA_VIPH0_COMMAND__BYTE_COUNT__SHIFT__SI 0x00000000 -#define DMA_VIPH0_COMMAND__DEST_OFFSET_HOLD__SHIFT__SI 0x0000001d -#define DMA_VIPH0_COMMAND__END_OF_LIST_STATUS__SHIFT__SI 0x0000001f -#define DMA_VIPH0_COMMAND__INTERRUPT_DIS__SHIFT__SI 0x0000001e -#define DMA_VIPH0_COMMAND__SOURCE_OFFSET_HOLD__SHIFT__SI 0x0000001c -#define DMA_VIPH0_COMMAND__SWAP_CONTROL__SHIFT__SI 0x00000018 -#define DMA_VIPH0_COMMAND__TRANSFER_DEST__SHIFT__SI 0x0000001b -#define DMA_VIPH0_COMMAND__TRANSFER_SOURCE__SHIFT__SI 0x0000001a -#define DMA_VIPH0_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH0_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH0_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH1_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT__SHIFT__SI 0x00000000 -#define DMA_VIPH1_COMMAND__BYTE_COUNT__SHIFT__SI 0x00000000 -#define DMA_VIPH1_COMMAND__DEST_OFFSET_HOLD__SHIFT__SI 0x0000001d -#define DMA_VIPH1_COMMAND__END_OF_LIST_STATUS__SHIFT__SI 0x0000001f -#define DMA_VIPH1_COMMAND__INTERRUPT_DIS__SHIFT__SI 0x0000001e -#define DMA_VIPH1_COMMAND__SOURCE_OFFSET_HOLD__SHIFT__SI 0x0000001c -#define DMA_VIPH1_COMMAND__SWAP_CONTROL__SHIFT__SI 0x00000018 -#define DMA_VIPH1_COMMAND__TRANSFER_DEST__SHIFT__SI 0x0000001b -#define DMA_VIPH1_COMMAND__TRANSFER_SOURCE__SHIFT__SI 0x0000001a -#define DMA_VIPH1_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH1_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH1_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH2_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT__SHIFT__SI 0x00000000 -#define DMA_VIPH2_COMMAND__BYTE_COUNT__SHIFT__SI 0x00000000 -#define DMA_VIPH2_COMMAND__DEST_OFFSET_HOLD__SHIFT__SI 0x0000001d -#define DMA_VIPH2_COMMAND__END_OF_LIST_STATUS__SHIFT__SI 0x0000001f -#define DMA_VIPH2_COMMAND__INTERRUPT_DIS__SHIFT__SI 0x0000001e -#define DMA_VIPH2_COMMAND__SOURCE_OFFSET_HOLD__SHIFT__SI 0x0000001c -#define DMA_VIPH2_COMMAND__SWAP_CONTROL__SHIFT__SI 0x00000018 -#define DMA_VIPH2_COMMAND__TRANSFER_DEST__SHIFT__SI 0x0000001b -#define DMA_VIPH2_COMMAND__TRANSFER_SOURCE__SHIFT__SI 0x0000001a -#define DMA_VIPH2_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH2_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH2_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH3_ACTIVE__DMA_VIPH_TABLE_ADDR_ACT__SHIFT__SI 0x00000000 -#define DMA_VIPH3_COMMAND__BYTE_COUNT__SHIFT__SI 0x00000000 -#define DMA_VIPH3_COMMAND__DEST_OFFSET_HOLD__SHIFT__SI 0x0000001d -#define DMA_VIPH3_COMMAND__END_OF_LIST_STATUS__SHIFT__SI 0x0000001f -#define DMA_VIPH3_COMMAND__INTERRUPT_DIS__SHIFT__SI 0x0000001e -#define DMA_VIPH3_COMMAND__SOURCE_OFFSET_HOLD__SHIFT__SI 0x0000001c -#define DMA_VIPH3_COMMAND__SWAP_CONTROL__SHIFT__SI 0x00000018 -#define DMA_VIPH3_COMMAND__TRANSFER_DEST__SHIFT__SI 0x0000001b -#define DMA_VIPH3_COMMAND__TRANSFER_SOURCE__SHIFT__SI 0x0000001a -#define DMA_VIPH3_DESTINATION_ADDR_HIGH__DMA_VIPH_DESTINATION_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH3_SOURCE_ADDR_HIGH__DMA_VIPH_SOURCE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH3_TABLE_ADDR_HIGH__DMA_VIPH_TABLE_ADDR_HIGH__SHIFT__SI 0x00000000 -#define DMA_VIPH_ABORT__DMA_VIPH0_ABORT_EN__SHIFT__SI 0x00000003 -#define DMA_VIPH_ABORT__DMA_VIPH0_RESET__SHIFT__SI 0x00000014 -#define DMA_VIPH_ABORT__DMA_VIPH1_ABORT_EN__SHIFT__SI 0x00000007 -#define DMA_VIPH_ABORT__DMA_VIPH1_RESET__SHIFT__SI 0x00000015 -#define DMA_VIPH_ABORT__DMA_VIPH2_ABORT_EN__SHIFT__SI 0x0000000b -#define DMA_VIPH_ABORT__DMA_VIPH2_RESET__SHIFT__SI 0x00000016 -#define DMA_VIPH_ABORT__DMA_VIPH3_ABORT_EN__SHIFT__SI 0x0000000f -#define DMA_VIPH_ABORT__DMA_VIPH3_RESET__SHIFT__SI 0x00000017 -#define DMA_VIPH_CHUNK_0__DMA_VIPH0_NOCHUNK__SHIFT__SI 0x0000001f -#define DMA_VIPH_CHUNK_0__DMA_VIPH0_TABLE_SWAP__SHIFT__SI 0x00000006 -#define DMA_VIPH_CHUNK_0__DMA_VIPH1_NOCHUNK__SHIFT__SI 0x0000001e -#define DMA_VIPH_CHUNK_0__DMA_VIPH1_TABLE_SWAP__SHIFT__SI 0x00000004 -#define DMA_VIPH_CHUNK_0__DMA_VIPH2_NOCHUNK__SHIFT__SI 0x0000001d -#define DMA_VIPH_CHUNK_0__DMA_VIPH2_TABLE_SWAP__SHIFT__SI 0x00000002 -#define DMA_VIPH_CHUNK_0__DMA_VIPH3_NOCHUNK__SHIFT__SI 0x0000001c -#define DMA_VIPH_CHUNK_0__DMA_VIPH3_TABLE_SWAP__SHIFT__SI 0x00000000 -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP0_CHUNK__SHIFT__SI 0x00000000 -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP1_CHUNK__SHIFT__SI 0x00000008 -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP2_CHUNK__SHIFT__SI 0x00000010 -#define DMA_VIPH_CHUNK_1_VAL__DMA_VIP3_CHUNK__SHIFT__SI 0x00000018 -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_READ_TIMEOUT_STATUS__SHIFT__SI 0x00000008 -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_READ_TIMEOUT_TO_PRIORITY_EN__SHIFT__SI 0x00000007 -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_READ_TIMER__SHIFT__SI 0x00000000 -#define DMA_VIPH_MISC_CNTL__DMA_VIPH_URGENT_EN__SHIFT__SI 0x00000009 -#define DMA_VIPH_STATUS__DMA_VIPH0_ACTIVE__SHIFT__SI 0x00000018 -#define DMA_VIPH_STATUS__DMA_VIPH0_AVAIL__SHIFT__SI 0x00000000 -#define DMA_VIPH_STATUS__DMA_VIPH0_CURRENT__SHIFT__SI 0x00000010 -#define DMA_VIPH_STATUS__DMA_VIPH1_ACTIVE__SHIFT__SI 0x00000019 -#define DMA_VIPH_STATUS__DMA_VIPH1_AVAIL__SHIFT__SI 0x00000004 -#define DMA_VIPH_STATUS__DMA_VIPH1_CURRENT__SHIFT__SI 0x00000012 -#define DMA_VIPH_STATUS__DMA_VIPH2_ACTIVE__SHIFT__SI 0x0000001a -#define DMA_VIPH_STATUS__DMA_VIPH2_AVAIL__SHIFT__SI 0x00000008 -#define DMA_VIPH_STATUS__DMA_VIPH2_CURRENT__SHIFT__SI 0x00000014 -#define DMA_VIPH_STATUS__DMA_VIPH3_ACTIVE__SHIFT__SI 0x0000001b -#define DMA_VIPH_STATUS__DMA_VIPH3_AVAIL__SHIFT__SI 0x0000000c -#define DMA_VIPH_STATUS__DMA_VIPH3_CURRENT__SHIFT__SI 0x00000016 -#define DMA_VIPH_STATUS__VIP_RBBM_H0DMA_IDLE__SHIFT__SI 0x0000001c -#define DMA_VIPH_STATUS__VIP_RBBM_H1DMA_IDLE__SHIFT__SI 0x0000001d -#define DMA_VIPH_STATUS__VIP_RBBM_H2DMA_IDLE__SHIFT__SI 0x0000001e -#define DMA_VIPH_STATUS__VIP_RBBM_H3DMA_IDLE__SHIFT__SI 0x0000001f -#define DMA_VIPH_WRCOMB__VIPDMA_WRCOMB_BYPASS__SHIFT__SI 0x00000011 -#define DMA_VIPH_WRCOMB__VIPDMA_WRCOMB_TIMEOUT__SHIFT__SI 0x00000000 -#define DMA_VIPH_WRCOMB__WRCOMB_STAT_EN__SHIFT__SI 0x00000012 -#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT__SI 0x00000002 -#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT__SI 0x00000003 -#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT__SI 0x00000001 -#define DMCU_CTRL__RESET_UC__SHIFT__SI 0x00000000 -#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT__SI 0x00000016 -#define DMCU_DEBUG_00__DBG_DMCU_abm1_dmcu_bl_update_interrupt__SHIFT__SI 0x0000000a -#define DMCU_DEBUG_00__DBG_DMCU_abm1_dmcu_hg_ready_interrupt__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_00__DBG_DMCU_abm1_dmcu_ls_ready_interrupt__SHIFT__SI 0x00000009 -#define DMCU_DEBUG_00__DBG_DMCU_ack__SHIFT__SI 0x0000000e -#define DMCU_DEBUG_00__DBG_DMCU_ihc_abm1_bl_update_interrupt__SHIFT__SI 0x00000007 -#define DMCU_DEBUG_00__DBG_DMCU_ihc_abm1_hg_ready_interrupt__SHIFT__SI 0x00000005 -#define DMCU_DEBUG_00__DBG_DMCU_ihc_abm1_ls_ready_interrupt__SHIFT__SI 0x00000006 -#define DMCU_DEBUG_00__DBG_DMCU_ihc_dmcu_internal_interrupt__SHIFT__SI 0x00000003 -#define DMCU_DEBUG_00__DBG_DMCU_ihc_scp_interrput__SHIFT__SI 0x00000004 -#define DMCU_DEBUG_00__DBG_DMCU_mcp_intc_interrupt__SHIFT__SI 0x0000000b -#define DMCU_DEBUG_00__DBG_DMCU_pwr__SHIFT__SI 0x0000000d -#define DMCU_DEBUG_00__DBG_DMCU_scp_intc_interrupt__SHIFT__SI 0x0000000c -#define DMCU_DEBUG_00__DBG_DMCU_uc_irq_n__SHIFT__SI 0x00000002 -#define DMCU_DEBUG_00__DBG_DMCU_uc_rst_n__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_00__DBG_DMCU_uc_xirq_n__SHIFT__SI 0x00000001 -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_addr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_as__SHIFT__SI 0x0000000b -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_cs__SHIFT__SI 0x0000000a -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_data_out__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_rd__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_01__DBG_DMCU_uc_eramarb_mem_wr__SHIFT__SI 0x00000009 -#define DMCU_DEBUG_02__DBG_DMCU_eramarb_uc_mem_data_in__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_addr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_as__SHIFT__SI 0x0000000b -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_cs__SHIFT__SI 0x0000000a -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_rd__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_02__DBG_DMCU_uc_eramarb_mem_wr__SHIFT__SI 0x00000009 -#define DMCU_DEBUG_03__DBG_DMCU_iramarb_uc_mem_data_in__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_addr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_as__SHIFT__SI 0x0000000b -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_cs__SHIFT__SI 0x0000000a -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_data_out__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_rd__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_03__DBG_DMCU_uc_iramarb_mem_wr__SHIFT__SI 0x00000009 -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_we__SHIFT__SI 0x0000000f -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_wem__SHIFT__SI 0x00000013 -#define DMCU_DEBUG_04__DBG_DMCU_DMCU_DCMEM_eram_wr_data__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_04__DBG_DMCU_eram_xa_ctrl_ReqHandlerState__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_04__DBG_DMCU_eramarb_eramxac_rtr__SHIFT__SI 0x0000000d -#define DMCU_DEBUG_04__DBG_DMCU_eramxac_eramarb_rts__SHIFT__SI 0x0000000e -#define DMCU_DEBUG_05__DBG_DMCU_DCMEM_DMCU_eram_rd_data__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_05__DBG_DMCU_DMCU_DCMEM_eram_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_05__DBG_DMCU_DMCU_DCMEM_eram_we__SHIFT__SI 0x0000000f -#define DMCU_DEBUG_05__DBG_DMCU_eram_xa_ctrl_ReqHandlerState__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_05__DBG_DMCU_eramarb_eramxac_rtr__SHIFT__SI 0x0000000d -#define DMCU_DEBUG_05__DBG_DMCU_eramxac_eramarb_rts__SHIFT__SI 0x0000000e -#define DMCU_DEBUG_06__DBG_DMCU_DMCU_DCMEM_eram_wr_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_07__DBG_DMCU_DMCU_DCMEM_eram_wem__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_08__DBG_DMCU_DCMEM_DMCU_eram_rd_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_we__SHIFT__SI 0x0000000f -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_wem__SHIFT__SI 0x00000013 -#define DMCU_DEBUG_09__DBG_DMCU_DMCU_DCMEM_iram_wr_data__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_09__DBG_DMCU_iram_xa_ctrl_ReqHandlerState__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_0A__DBG_DMCU_DCMEM_DMCU_iram_rd_data__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_0A__DBG_DMCU_DMCU_DCMEM_iram_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_0B__DBG_DMCU_DMCU_DCMEM_eram_wr_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_ctrl_wr_accepted__SHIFT__SI 0x00000013 -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_ctrl_wr_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_ctrl_wr_be__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_0C__DBG_DMCU_dmcu_intreg_wr_data__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_0D__DBG_DMCU_dmcu_intreg_wr_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_ctrl_rd_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_ctrl_rd_data_valid__SHIFT__SI 0x0000001f -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_ctrl_wait4rd_return_data__SHIFT__SI 0x0000001e -#define DMCU_DEBUG_0E__DBG_DMCU_dmcu_intreg_rd_data__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_0F__DBG_DMCU_dmcu_intreg_rd_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_a__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_be__SHIFT__SI 0x00000013 -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_rts__SHIFT__SI 0x00000011 -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_wd__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_10__DBG_DMCU_DMCU_RBBMARB_we__SHIFT__SI 0x00000012 -#define DMCU_DEBUG_10__DBG_DMCU_RBBMARB_DMCU_rtr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_a__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_be__SHIFT__SI 0x00000016 -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_re__SHIFT__SI 0x00000012 -#define DMCU_DEBUG_11__DBG_DMCU_DMCU_RBBMARB_rts__SHIFT__SI 0x00000011 -#define DMCU_DEBUG_11__DBG_DMCU_RBBMARB_DMCU_rdo__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_11__DBG_DMCU_RBBMARB_DMCU_rtr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_11__DBG_DMCU_rbbm_if_ReqFifoDeqState__SHIFT__SI 0x00000013 -#define DMCU_DEBUG_12__DBG_DMCU_DMCU_RBBMARB_wd__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_13__DBG_DMCU_RBBMARB_DMCU_rdo__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_ReqEnq_DataDeq_State__SHIFT__SI 0x00000004 -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_din__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_empty__SHIFT__SI 0x00000003 -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_full__SHIFT__SI 0x00000002 -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_q__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_re__SHIFT__SI 0x00000001 -#define DMCU_DEBUG_14__DBG_DMCU_rbbm_if_rddatafifo_we__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_ReqEnq_DataDeq_State__SHIFT__SI 0x00000004 -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_din__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_empty__SHIFT__SI 0x00000003 -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_full__SHIFT__SI 0x00000002 -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_q__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_re__SHIFT__SI 0x00000001 -#define DMCU_DEBUG_15__DBG_DMCU_rbbm_if_req_fifo_we__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Addr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Be__SHIFT__SI 0x00000004 -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Complete__SHIFT__SI 0x0000000e -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Req__SHIFT__SI 0x0000000d -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_WriteData__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_16__DBG_DMCU_MBUS_Write__SHIFT__SI 0x0000000f -#define DMCU_DEBUG_16__DBG_DMCU_mbus_if_DcregAccessState__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_16__DBG_DMCU_pending_req_on_mbus__SHIFT__SI 0x0000000c -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Addr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Be__SHIFT__SI 0x00000004 -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Complete__SHIFT__SI 0x0000000e -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_ReadData__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Req__SHIFT__SI 0x0000000d -#define DMCU_DEBUG_17__DBG_DMCU_MBUS_Write__SHIFT__SI 0x0000000f -#define DMCU_DEBUG_17__DBG_DMCU_mbus_if_DcregAccessState__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_17__DBG_DMCU_pending_req_on_mbus__SHIFT__SI 0x0000000c -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_eramarb_mem_dec__SHIFT__SI 0x00000006 -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_iramarb_mem_dec__SHIFT__SI 0x00000007 -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_dcreg_dec__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_interrupt_status_reg_dec__SHIFT__SI 0x00000005 -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_rd_ctrl_dec__SHIFT__SI 0x00000003 -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_rd_data_dec__SHIFT__SI 0x00000004 -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_wr_ctrl_dec__SHIFT__SI 0x00000001 -#define DMCU_DEBUG_18__DBG_DMCU_addrdec_mbusif_intreg_wr_data_dec__SHIFT__SI 0x00000002 -#define DMCU_DEBUG_19__DBG_DMCU_MBUS_WriteData__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_20__DBG_DMCU_MBUS_ReadData__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_21__DBG_DMCU_eram_xa_ctrl_ReqHandlerState__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_21__DBG_DMCU_iram_xa_ctrl_ReqHandlerState__SHIFT__SI 0x00000003 -#define DMCU_DEBUG_21__DBG_DMCU_mbus_if_DcregAccessState__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_21__DBG_DMCU_rbbm_if_ReqEnq_DataDeq_State__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_21__DBG_DMCU_rbbm_if_ReqFifoDeqState__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_22__DBG_DMCU_sfr_addr__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_22__DBG_DMCU_sfr_data_in__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_22__DBG_DMCU_sfr_data_out__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_22__DBG_DMCU_sfr_rd__SHIFT__SI 0x00000011 -#define DMCU_DEBUG_22__DBG_DMCU_sfr_wp__SHIFT__SI 0x00000012 -#define DMCU_DEBUG_22__DBG_DMCU_sfr_wr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_23__DBG_DMCU_DMCU_DCMEM_eram_last_rd_addr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_23__DBG_DMCU_DMCU_DCMEM_eram_last_wr_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_24__DBG_DMCU_DMCU_DCMEM_eram_last_wr_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_25__DBG_DMCU_DMCU_DCMEM_eram_last_wr_wem__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_26__DBG_DMCU_DCMEM_DMCU_eram_last_rd_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_27__DBG_DMCU_DMCU_DCMEM_iram_last_rd_addr__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_27__DBG_DMCU_DMCU_DCMEM_iram_last_wr_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_28__DBG_DMCU_DCMEM_DMCU_iram_last_rd_data__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_28__DBG_DMCU_DMCU_DCMEM_iram_last_wem__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_28__DBG_DMCU_DMCU_DCMEM_iram_last_wr_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_29__DBG_DMCU_DMCU_RBBMARB_last_rd_addr__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_29__DBG_DMCU_DMCU_RBBMARB_last_wr_addr__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_2A__DBG_DMCU_DMCU_RBBMARB_last_wr_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_2B__DBG_DMCU_DMCU_RBBMARB_last_wr_be__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_2C__DBG_DMCU_RBBMARB_DMCU_last_rd_data__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_32__DBG_DMCU_uc_pc__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_32__DBG_DMCU_uc_sp__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_33__DBG_DMCU_uc_index_x__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_33__DBG_DMCU_uc_index_y__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_34__DBG_DMCU_uc_accumulator_a__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_34__DBG_DMCU_uc_accumulator_b__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_35__DBG_DMCU_uc_mathareg__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_35__DBG_DMCU_uc_mathbreg__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_36__DBG_DMCU_uc_mathcreg__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_c__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_h__SHIFT__SI 0x00000002 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_i__SHIFT__SI 0x00000001 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_n__SHIFT__SI 0x00000003 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_s__SHIFT__SI 0x00000004 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_v__SHIFT__SI 0x00000005 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_x__SHIFT__SI 0x00000006 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_x_override__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_37__DBG_DMCU_uc_ccr_z__SHIFT__SI 0x00000007 -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch1__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch2__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch3__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_38__DBG_DMCU_sfr_scratch4__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch5__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch6__SHIFT__SI 0x00000008 -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch7__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_39__DBG_DMCU_sfr_scratch8__SHIFT__SI 0x00000018 -#define DMCU_DEBUG_3A__DBG_DMCU_sfr_disable_irq_to_uc__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_3A__DBG_DMCU_sfr_disable_xirq_to_uc__SHIFT__SI 0x00000001 -#define DMCU_DEBUG_CONSTANT__DBG_DMCU_5a5a__SHIFT__SI 0x00000000 -#define DMCU_DEBUG_CONSTANT__DBG_DMCU_beef__SHIFT__SI 0x00000010 -#define DMCU_DEBUG_ID__DMCU_DEBUG_ID__SHIFT__SI 0x00000000 -#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT__SI 0x00000000 -#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT__SI 0x00000010 -#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT__SI 0x00000014 -#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT__SI 0x00000000 -#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT__SI 0x00000000 -#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT__SI 0x00000010 -#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT__SI 0x00000014 -#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT__SI 0x00000000 -#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT__SI 0x00000000 -#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT__SI 0x00000017 -#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT__SI 0x00000010 -#define DMCU_EVENT_TRIGGER__UC_PWR_UP_DOWN_COMPLETE_STATUS__SHIFT__SI 0x0000001f -#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT__SI 0x00000002 -#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT__SI 0x00000000 -#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT__SI 0x00000000 -#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT__SI 0x00000000 -#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT__SI 0x00000000 -#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT__SI 0x00000008 -#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT__SI 0x00000000 -#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT__SI 0x00000008 -#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT__SI 0x00000000 -#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT__SI 0x00000008 -#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT__SI 0x00000002 -#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT__SI 0x00000002 -#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT__SI 0x00000000 -#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT__SI 0x00000000 -#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT__SI 0x00000001 -#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT__SI 0x00000001 -#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT__SI 0x00000008 -#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT__SI 0x00000008 -#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT__SI 0x00000003 -#define DMCU_INTERRUPT_STATUS__PM_PWR_DOWN_INT_CLEAR__SHIFT__SI 0x00000005 -#define DMCU_INTERRUPT_STATUS__PM_PWR_DOWN_INT_OCCURRED__SHIFT__SI 0x00000005 -#define DMCU_INTERRUPT_STATUS__PM_PWR_UP_INT_CLEAR__SHIFT__SI 0x00000004 -#define DMCU_INTERRUPT_STATUS__PM_PWR_UP_INT_OCCURRED__SHIFT__SI 0x00000004 -#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT__SI 0x00000009 -#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT__SI 0x0000000a -#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT__SI 0x0000000a -#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT__SI 0x0000000b -#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT__SI 0x0000000b -#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT__SI 0x00000006 -#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT__SI 0x00000006 -#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT__SI 0x00000007 -#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT__SI 0x00000007 -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT__SI 0x00000002 -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT__SI 0x00000000 -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT__SI 0x00000001 -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT__SI 0x00000009 -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT__SI 0x0000000a -#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT__SI 0x0000000b -#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT__SI 0x00000002 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT__SI 0x00000000 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT__SI 0x00000001 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT__SI 0x00000008 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT__SI 0x00000003 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__PM_PWR_DOWN_INT_TO_UC_EN__SHIFT__SI 0x00000005 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__PM_PWR_UP_INT_TO_UC_EN__SHIFT__SI 0x00000004 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT__SI 0x00000006 -#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT__SI 0x00000007 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000002 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000000 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000001 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000008 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000003 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__PM_PWR_DOWN_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000005 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__PM_PWR_UP_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000004 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000006 -#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT__SI 0x00000007 -#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT__SI 0x00000010 -#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT__SI 0x00000000 -#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT__SI 0x00000008 -#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT__SI 0x00000000 -#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT__SI 0x00000000 -#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT__SI 0x00000000 -#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT__SI 0x00000000 -#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT__SI 0x00000000 -#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT__SI 0x00000008 -#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT__SI 0x00000001 -#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT__SI 0x00000000 -#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT__SI 0x00000003 -#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT__SI 0x00000002 -#define DMCU_STATUS__DMCU_RBBMIF_RD_WR_TIMEOUT_DIS__SHIFT__SI 0x0000001f -#define DMCU_STATUS__UC_IN_RESET__SHIFT__SI 0x00000000 -#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT__SI 0x00000002 -#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT__SI 0x00000001 -#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DMCU_UC_CCR__UC_CCR_C__SHIFT__SI 0x00000000 -#define DMCU_UC_CCR__UC_CCR_H__SHIFT__SI 0x00000005 -#define DMCU_UC_CCR__UC_CCR_I__SHIFT__SI 0x00000004 -#define DMCU_UC_CCR__UC_CCR_N__SHIFT__SI 0x00000003 -#define DMCU_UC_CCR__UC_CCR_S__SHIFT__SI 0x00000007 -#define DMCU_UC_CCR__UC_CCR_V__SHIFT__SI 0x00000001 -#define DMCU_UC_CCR__UC_CCR_X_OVERRIDE__SHIFT__SI 0x00000008 -#define DMCU_UC_CCR__UC_CCR_X__SHIFT__SI 0x00000006 -#define DMCU_UC_CCR__UC_CCR_Z__SHIFT__SI 0x00000002 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT__SI 0x00000003 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT__SI 0x00000000 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT__SI 0x0000000e -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT__SI 0x0000000f -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT__SI 0x00000009 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT__SI 0x00000002 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT__SI 0x0000000d -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT__SI 0x0000000c -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT__SI 0x0000000b -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT__SI \ - 0x0000000a -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT__SI 0x00000007 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT__SI 0x00000006 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT__SI 0x00000005 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT__SI 0x00000004 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT__SI 0x00000008 -#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT__SI 0x00000001 -#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT__SI 0x00000000 -#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT__SI 0x00000000 -#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT__SI 0x00000008 -#define DMIF_DEBUG00__DMIF_DCP_debug00_cmd_grph_req_cnt__SHIFT__SI 0x0000000c -#define DMIF_DEBUG00__DMIF_DCP_debug00_cmd_new_chunk_for_wr__SHIFT__SI 0x00000019 -#define DMIF_DEBUG00__DMIF_DCP_debug00_cmd_ovl_req_cnt__SHIFT__SI 0x00000013 -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_cmd_state__SHIFT__SI 0x00000008 -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_display1_update__SHIFT__SI 0x00000001 -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_display2_update__SHIFT__SI 0x00000002 -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_req__SHIFT__SI 0x00000003 -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_size__SHIFT__SI 0x00000004 -#define DMIF_DEBUG00__DMIF_DCP_debug00_dcp_dmif_surface__SHIFT__SI 0x00000006 -#define DMIF_DEBUG00__DMIF_DCP_debug00_dmif_dcp_req_fifo_empty__SHIFT__SI 0x00000000 -#define DMIF_DEBUG01__DMIF_DCP_debug01_cmd_q_mc_dmif_rdrtr__SHIFT__SI 0x00000000 -#define DMIF_DEBUG01__DMIF_DCP_debug01_dcp_dmif_urgent__SHIFT__SI 0x0000000f -#define DMIF_DEBUG01__DMIF_DCP_debug01_dcp_dmif_urglevel__SHIFT__SI 0x00000010 -#define DMIF_DEBUG01__DMIF_DCP_debug01_dmif_mc_rdreq__SHIFT__SI 0x00000001 -#define DMIF_DEBUG01__DMIF_DCP_debug01_dmif_mc_rdtag__SHIFT__SI 0x00000002 -#define DMIF_DEBUG02__DMIF_DCP_debug02_chunk_readout__SHIFT__SI 0x00000006 -#define DMIF_DEBUG02__DMIF_DCP_debug02_grph_chunk_reading__SHIFT__SI 0x00000004 -#define DMIF_DEBUG02__DMIF_DCP_debug02_grph_new_chunk_for_wr__SHIFT__SI 0x00000000 -#define DMIF_DEBUG02__DMIF_DCP_debug02_grph_new_chunk_for_wr_taken__SHIFT__SI 0x00000002 -#define DMIF_DEBUG02__DMIF_DCP_debug02_ovl_chunk_reading__SHIFT__SI 0x00000005 -#define DMIF_DEBUG02__DMIF_DCP_debug02_ovl_new_chunk_for_wr__SHIFT__SI 0x00000001 -#define DMIF_DEBUG02__DMIF_DCP_debug02_ovl_new_chunk_for_wr_taken__SHIFT__SI 0x00000003 -#define DMIF_DEBUG03__DMIF_DCP_debug03_dcp_dmif_req__SHIFT__SI 0x00000000 -#define DMIF_DEBUG03__DMIF_DCP_debug03_dcp_dmif_size__SHIFT__SI 0x00000001 -#define DMIF_DEBUG03__DMIF_DCP_debug03_dcp_dmif_surface__SHIFT__SI 0x00000003 -#define DMIF_DEBUG03__DMIF_DCP_debug03_q_mc_dmif_rdtag__SHIFT__SI 0x00000006 -#define DMIF_DEBUG03__DMIF_DCP_debug03_q_mc_dmif_rdtid__SHIFT__SI 0x00000013 -#define DMIF_DEBUG03__DMIF_DCP_debug03_q_mc_dmif_xfc__SHIFT__SI 0x00000005 -#define DMIF_DEBUG03__DMIF_DCP_debug03_wr_addr__SHIFT__SI 0x00000016 -#define DMIF_DEBUG04__DMIF_DCP_debug04_dcp_dmif_grph_rtr__SHIFT__SI 0x00000018 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_chunk_sending__SHIFT__SI 0x00000016 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_dcp_data_buff_sel__SHIFT__SI 0x00000012 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_dcp_data_sel__SHIFT__SI 0x00000014 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_last_pix_in_ow__SHIFT__SI 0x00000011 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_pix_en__SHIFT__SI 0x00000015 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_addr__SHIFT__SI 0x00000008 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_data_valid__SHIFT__SI 0x00000010 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_en__SHIFT__SI 0x00000000 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rd_req_cnt__SHIFT__SI 0x00000001 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_rts__SHIFT__SI 0x00000017 -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_send_pix_cnt__SHIFT__SI 0x0000001b -#define DMIF_DEBUG04__DMIF_DCP_debug04_grph_send_pix_depth__SHIFT__SI 0x00000019 -#define DMIF_DEBUG05__DMIF_DCP_debug05_dcp_dmif_ovl_rtr__SHIFT__SI 0x00000017 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_chunk_sending__SHIFT__SI 0x00000015 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_dcp_data_buff_sel__SHIFT__SI 0x00000011 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_dcp_data_sel__SHIFT__SI 0x00000013 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_last_pix_in_ow__SHIFT__SI 0x00000010 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_pix_en__SHIFT__SI 0x00000014 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_addr__SHIFT__SI 0x00000007 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_data_valid__SHIFT__SI 0x0000000f -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_en__SHIFT__SI 0x00000000 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rd_req_cnt__SHIFT__SI 0x00000001 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_rts__SHIFT__SI 0x00000016 -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_send_pix_cnt__SHIFT__SI 0x0000001a -#define DMIF_DEBUG05__DMIF_DCP_debug05_ovl_send_pix_depth__SHIFT__SI 0x00000018 -#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT__SI 0x00000000 -#define DMIF_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT__SI 0x00000000 -#define DMIF_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT__SI 0x00000003 -#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT__SI 0x00000008 -#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT__SI 0x00000010 -#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT__SI 0x00000011 -#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT__SI 0x00000000 -#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DOUT_DEBUG__DOUT_DEBUG__SHIFT__SI 0x00000000 -#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT__SI 0x00000015 -#define DOUT_POWER_MANAGEMENT_CNTL__PM_CURRENT_STATE__SHIFT__SI 0x0000001c -#define DOUT_POWER_MANAGEMENT_CNTL__PM_DP_SW_FAST_TRAINING_ONLY__SHIFT__SI 0x00000016 -#define DOUT_POWER_MANAGEMENT_CNTL__PM_NO_DP_SUPPORT_DEBUG__SHIFT__SI 0x00000014 -#define DOUT_POWER_MANAGEMENT_CNTL__PM_PWRDN_PPLL_VREG__SHIFT__SI 0x00000018 -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_BUSY_OFF__SHIFT__SI 0x00000000 -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_DMCU_OFF__SHIFT__SI 0x00000005 -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_PPLL_OFF__SHIFT__SI 0x00000008 -#define DOUT_POWER_MANAGEMENT_CNTL__PWRDN_WAIT_PWRSEQ_OFF__SHIFT__SI 0x00000004 -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_APLL_ON__SHIFT__SI 0x0000000c -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_DMCU_ON__SHIFT__SI 0x00000011 -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_MEM_INIT_DONE__SHIFT__SI 0x00000010 -#define DOUT_POWER_MANAGEMENT_CNTL__PWRUP_WAIT_PPLL_ON__SHIFT__SI 0x00000009 -#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT__SI 0x00000000 -#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT__SI 0x00000000 -#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT__SI 0x00000000 -#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT__SI 0x00000000 -#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT__SI 0x00000000 -#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT__SI 0x00000000 -#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT__SI 0x00000000 -#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT__SI 0x00000000 -#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT__SI 0x00000000 -#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT__SI 0x00000000 -#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT__SI 0x00000000 -#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT__SI 0x00000000 -#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT__SI 0x00000000 -#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT__SI 0x00000000 -#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT__SI 0x00000000 -#define DP_CONFIG__DP_UDI_LANES__SHIFT__SI 0x00000000 -#define DP_CP_DEBUG1__DP_CP_DEBUG1__SHIFT__SI 0x00000000 -#define DP_CP_DEBUG2__DP_CP_DEBUG2__SHIFT__SI 0x00000000 -#define DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN__SHIFT__SI 0x00000000 -#define DP_DEBUG_A__DP_DEBUG_A__SHIFT__SI 0x00000000 -#define DP_DEBUG_B__DP_DEBUG_B__SHIFT__SI 0x00000000 -#define DP_DEBUG_C__DP_DEBUG_C__SHIFT__SI 0x00000000 -#define DP_DEBUG_D__DP_DEBUG_D__SHIFT__SI 0x00000000 -#define DP_DEBUG_E__DP_DEBUG_E__SHIFT__SI 0x00000000 -#define DP_DEBUG_F__DP_DEBUG_F__SHIFT__SI 0x00000000 -#define DP_DEBUG_G__DP_DEBUG_G__SHIFT__SI 0x00000000 -#define DP_DEBUG_H__DP_DEBUG_H__SHIFT__SI 0x00000000 -#define DP_DEBUG_ID__DP_DEBUG_ID__SHIFT__SI 0x00000000 -#define DP_DEBUG_Q__DP_DEBUG_Q__SHIFT__SI 0x00000000 -#define DP_DEBUG_R__DP_DEBUG_R__SHIFT__SI 0x00000000 -#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT__SI 0x00000010 -#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT__SI 0x00000008 -#define DP_DPHY_8B10B_CNTL__DPHY_8b10b_CUR_DISP__SHIFT__SI 0x00000018 -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT__SI 0x00000000 -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT__SI 0x00000001 -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT__SI 0x00000002 -#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT__SI 0x00000003 -#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT__SI 0x00000010 -#define DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT__SI 0x00000008 -#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT__SI 0x00000018 -#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT__SI 0x00000000 -#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT__SI 0x00000010 -#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT__SI 0x00000004 -#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT__SI 0x00000004 -#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT__SI 0x00000000 -#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT__SI 0x00000000 -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT__SI 0x00000005 -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT__SI 0x00000006 -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT__SI 0x00000004 -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT__SI 0x00000008 -#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT__SI 0x00000014 -#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT__SI 0x00000000 -#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT__SI 0x00000001 -#define DP_DPHY_INTERNAL_CTRL__DPHY_LANE_REVERSE_EN__SHIFT__SI 0x00000004 -#define DP_DPHY_INTERNAL_CTRL__DPHY_SCRAMBLER_RESET_CTRL__SHIFT__SI 0x00000000 -#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT__SI 0x00000000 -#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT__SI 0x00000008 -#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT__SI 0x00000004 -#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT__SI 0x00000004 -#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT__SI 0x00000008 -#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT__SI 0x00000000 -#define DP_DPHY_SYM__DPHY_SYM1__SHIFT__SI 0x00000000 -#define DP_DPHY_SYM__DPHY_SYM2__SHIFT__SI 0x0000000a -#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT__SI 0x00000000 -#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT__SI 0x00000000 -#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT__SI 0x00000000 -#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT__SI 0x00000000 -#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT__SI 0x00000000 -#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT__SI 0x00000000 -#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT__SI 0x00000000 -#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT__SI 0x00000000 -#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT__SI 0x00000000 -#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT__SI 0x00000000 -#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT__SI 0x00000000 -#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT__SI 0x00000000 -#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT__SI 0x00000000 -#define DP_IDLE_PATTERN_CNTL__DP_IDLE_BS_INTERVAL__SHIFT__SI 0x00000000 -#define DP_IDLE_PATTERN_CNTL__DP_VBID_DISABLE__SHIFT__SI 0x00000018 -#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT__SI 0x00000011 -#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT__SI 0x00000008 -#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT__SI 0x00000004 -#define DP_LINK_CNTL__DP_POWER_MANAGEMENT_EN__SHIFT__SI 0x00000010 -#define DP_LINK_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT__SI 0x0000000c -#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT__SI 0x00000018 -#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT__SI 0x00000008 -#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT__SI 0x00000000 -#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT__SI 0x00000010 -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_HB1__SHIFT__SI 0x00000000 -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_HB2__SHIFT__SI 0x00000008 -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_HB3__SHIFT__SI 0x00000010 -#define DP_SEC_ACP_HEADER__DP_SEC_ACP_TYPE_LOCATION__SHIFT__SI 0x00000018 -#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT__SI 0x00000000 -#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT__SI 0x00000000 -#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT__SI 0x00000000 -#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT__SI 0x00000000 -#define DP_SEC_AUD_N__DP_SEC_N_BASE_MULTIPLE__SHIFT__SI 0x00000018 -#define DP_SEC_AUD_N__DP_SEC_SS_EN__SHIFT__SI 0x0000001c -#define DP_SEC_CNTL__DP_SEC_ACP_ENABLE__SHIFT__SI 0x00000010 -#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT__SI 0x0000000c -#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT__SI 0x00000004 -#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT__SI 0x00000008 -#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT__SI 0x00000018 -#define DP_SEC_CNTL__DP_SEC_GSP_ENABLE__SHIFT__SI 0x00000014 -#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT__SI 0x0000001c -#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT__SI 0x00000000 -#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT__SI 0x00000000 -#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT__SI 0x00000010 -#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT__SI 0x00000010 -#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT__SI 0x00000000 -#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT__SI 0x00000000 -#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT__SI 0x00000010 -#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT__SI 0x0000001d -#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT__SI 0x0000001c -#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT__SI 0x00000018 -#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT__SI 0x00000014 -#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT__SI 0x00000000 -#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT__SI 0x00000004 -#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT__SI 0x00000008 -#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT__SI 0x00000000 -#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT__SI 0x00000000 -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT__SI 0x00000006 -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT__SI 0x00000004 -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT__SI 0x00000005 -#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT__SI 0x00000007 -#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT__SI 0x00000001 -#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT__SI 0x00000000 -#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT__SI 0x00000002 -#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT__SI 0x00000000 -#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT__SI 0x00000010 -#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT__SI 0x00000018 -#define DP_VID_M__DP_VID_M__SHIFT__SI 0x00000000 -#define DP_VID_N__DP_VID_N__SHIFT__SI 0x00000000 -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT__SI 0x00000014 -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT__SI 0x00000008 -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT__SI 0x00000000 -#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT__SI 0x00000010 -#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT__SI 0x00000008 -#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT__SI 0x00000018 -#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT__SI 0x00000000 -#define DRMDMA0_CONFIG__DRMDMA_RDREQ_URG__SHIFT__SI 0x00000008 -#define DRMDMA0_CONFIG__DRMDMA_REQ_TRAN__SHIFT__SI 0x00000010 -#define DRMDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT__SI 0x00000004 -#define DRMDMA1_CLK_CTRL__ON_DELAY__SHIFT__SI 0x00000000 -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT__SI 0x0000001f -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT__SI 0x0000001e -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT__SI 0x0000001d -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT__SI 0x0000001c -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT__SI 0x0000001b -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT__SI 0x0000001a -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT__SI 0x00000019 -#define DRMDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT__SI 0x00000018 -#define DRMDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT__SI 0x0000001c -#define DRMDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT__SI 0x00000003 -#define DRMDMA1_CNTL__DRM_CREDIT__SHIFT__SI 0x00000008 -#define DRMDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT__SI 0x00000004 -#define DRMDMA1_CNTL__IB_PREEMPT_ENABLE__SHIFT__SI 0x0000001d -#define DRMDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT__SI 0x00000017 -#define DRMDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT__SI 0x0000000d -#define DRMDMA1_CNTL__MC_WR_CLEAN_CNT__SHIFT__SI 0x00000012 -#define DRMDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT__SI 0x00000001 -#define DRMDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT__SI 0x00000002 -#define DRMDMA1_CNTL__SLOW_TILED_WRITE_MODE__SHIFT__SI 0x0000001f -#define DRMDMA1_CNTL__TRAP_ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA1_CONFIG__DRMDMA_RDREQ_URG__SHIFT__SI 0x00000008 -#define DRMDMA1_CONFIG__DRMDMA_REQ_TRAN__SHIFT__SI 0x00000010 -#define DRMDMA1_CONTEXT_CNTL__RESTORE_COUNT__SHIFT__SI 0x00000000 -#define DRMDMA1_CONTEXT_CNTL__RESUME_CTX__SHIFT__SI 0x00000010 -#define DRMDMA1_CONTEXT_CNTL__SESSION_SEL__SHIFT__SI 0x00000018 -#define DRMDMA1_CRC_VALUE__CRC_VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM1_CTRL__DRM1_CREDIT__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERDATA0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERDATA1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERDATA2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERDATA3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERKEY0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERKEY1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERKEY2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_COUNTERKEY3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_IVLOAD0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_IVLOAD1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_IVLOAD2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_IVLOAD3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_IVLOAD4__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_OFFSET__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_UNROLLKEY__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_WRAPPEDKEY0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_WRAPPEDKEY1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_WRAPPEDKEY2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_DRM_WRAPPEDKEY3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA1_FAULT_ADDR_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA1_FAULT_ADDR_LO__ADDR__SHIFT__SI 0x0000000c -#define DRMDMA1_FIFO_CNTL__CG_STATUS_OUTPUT__SHIFT__SI 0x00000017 -#define DRMDMA1_FIFO_CNTL__COPY_OVERLAP_ENABLE__SHIFT__SI 0x00000010 -#define DRMDMA1_FIFO_CNTL__DATA_FIFO_SIZE__SHIFT__SI 0x00000004 -#define DRMDMA1_FIFO_CNTL__DRM_FIFO_SIZE__SHIFT__SI 0x0000000a -#define DRMDMA1_FIFO_CNTL__GPU_ID__SHIFT__SI 0x0000000c -#define DRMDMA1_FIFO_CNTL__IB_FIFO_SIZE__SHIFT__SI 0x00000002 -#define DRMDMA1_FIFO_CNTL__MC_VMID_FORCE__SHIFT__SI 0x00000016 -#define DRMDMA1_FIFO_CNTL__MC_VMID__SHIFT__SI 0x00000012 -#define DRMDMA1_FIFO_CNTL__MC_WR_ADDR_FIFO_SIZE__SHIFT__SI 0x00000006 -#define DRMDMA1_FIFO_CNTL__MC_WR_DATA_FIFO_SIZE__SHIFT__SI 0x00000008 -#define DRMDMA1_FIFO_CNTL__RB_FIFO_SIZE__SHIFT__SI 0x00000000 -#define DRMDMA1_FIFO_CNTL__WRITE_OVERLAP_ENABLE__SHIFT__SI 0x00000011 -#define DRMDMA1_IB_BASE_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA1_IB_BASE_LO__ADDR__SHIFT__SI 0x00000005 -#define DRMDMA1_IB_CNTL__IB_ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA1_IB_CNTL__IB_SWAP_ENABLE__SHIFT__SI 0x00000004 -#define DRMDMA1_IB_OFFSET__OFFSET__SHIFT__SI 0x00000000 -#define DRMDMA1_IB_RPTR__OFFSET__SHIFT__SI 0x00000002 -#define DRMDMA1_IB_SIZE__SIZE__SHIFT__SI 0x00000000 -#define DRMDMA1_PERF_CNTL__CLEAR0__SHIFT__SI 0x00000001 -#define DRMDMA1_PERF_CNTL__CLEAR1__SHIFT__SI 0x00000009 -#define DRMDMA1_PERF_CNTL__ENABLE0__SHIFT__SI 0x00000000 -#define DRMDMA1_PERF_CNTL__ENABLE1__SHIFT__SI 0x00000008 -#define DRMDMA1_PERF_CNTL__SELECT0__SHIFT__SI 0x00000002 -#define DRMDMA1_PERF_CNTL__SELECT1__SHIFT__SI 0x0000000a -#define DRMDMA1_PERF_COUNT0__PERF_COUNT__SHIFT__SI 0x00000000 -#define DRMDMA1_PERF_COUNT1__PERF_COUNT__SHIFT__SI 0x00000000 -#define DRMDMA1_PREEMPT__PREEMPT__SHIFT__SI 0x00000000 -#define DRMDMA1_PRIV_MODE__MC_PRIV_MODE__SHIFT__SI 0x00000000 -#define DRMDMA1_PRIV_MODE__MEM_POWER_OVERRIDE__SHIFT__SI 0x00000008 -#define DRMDMA1_RB_BASE__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA1_RB_CNTL__RB_ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA1_RB_CNTL__RB_SIZE__SHIFT__SI 0x00000001 -#define DRMDMA1_RB_CNTL__RB_SWAP_ENABLE__SHIFT__SI 0x00000009 -#define DRMDMA1_RB_CNTL__RB_TRAN__SHIFT__SI 0x00000008 -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__SI 0x0000000c -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__SI 0x0000000d -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__SI 0x00000010 -#define DRMDMA1_RB_CNTL__RPTR_WRITEBACK_TRAN__SHIFT__SI 0x0000000e -#define DRMDMA1_RB_RPTR_ADDR_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA1_RB_RPTR_ADDR_LO__ADDR__SHIFT__SI 0x00000002 -#define DRMDMA1_RB_RPTR__OFFSET__SHIFT__SI 0x00000002 -#define DRMDMA1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__SI 0x00000002 -#define DRMDMA1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__SI 0x00000004 -#define DRMDMA1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__SI 0x00000010 -#define DRMDMA1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__SI 0x00000001 -#define DRMDMA1_RB_WPTR_POLL_CNTL__TRAN__SHIFT__SI 0x00000002 -#define DRMDMA1_RB_WPTR__OFFSET__SHIFT__SI 0x00000002 -#define DRMDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT__SI 0x00000000 -#define DRMDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT__SI 0x00000000 -#define DRMDMA1_STATUS_REG__DRM_IDLE__SHIFT__SI 0x00000017 -#define DRMDMA1_STATUS_REG__DRM_MASK_FULL__SHIFT__SI 0x00000018 -#define DRMDMA1_STATUS_REG__DRM_REQ_STALL__SHIFT__SI 0x00000019 -#define DRMDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT__SI 0x0000000b -#define DRMDMA1_STATUS_REG__EX_IDLE__SHIFT__SI 0x0000000a -#define DRMDMA1_STATUS_REG__IB_CMD_FULL__SHIFT__SI 0x00000007 -#define DRMDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT__SI 0x00000006 -#define DRMDMA1_STATUS_REG__IDLE__SHIFT__SI 0x00000000 -#define DRMDMA1_STATUS_REG__INT_IDLE__SHIFT__SI 0x0000001e -#define DRMDMA1_STATUS_REG__INT_REQ_STALL__SHIFT__SI 0x0000001f -#define DRMDMA1_STATUS_REG__MC_RD_IDLE__SHIFT__SI 0x00000013 -#define DRMDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT__SI 0x00000016 -#define DRMDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT__SI 0x00000015 -#define DRMDMA1_STATUS_REG__MC_RD_STALL__SHIFT__SI 0x00000014 -#define DRMDMA1_STATUS_REG__MC_WR_AFIFO_FULL__SHIFT__SI 0x0000000e -#define DRMDMA1_STATUS_REG__MC_WR_CLEAN_PENDING__SHIFT__SI 0x00000011 -#define DRMDMA1_STATUS_REG__MC_WR_CLEAN_STALL__SHIFT__SI 0x00000012 -#define DRMDMA1_STATUS_REG__MC_WR_DFIFO_FULL__SHIFT__SI 0x0000000f -#define DRMDMA1_STATUS_REG__MC_WR_IDLE__SHIFT__SI 0x0000000d -#define DRMDMA1_STATUS_REG__MC_WR_STALL__SHIFT__SI 0x00000010 -#define DRMDMA1_STATUS_REG__RB_CMD_FULL__SHIFT__SI 0x00000005 -#define DRMDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT__SI 0x00000004 -#define DRMDMA1_STATUS_REG__RB_EMPTY__SHIFT__SI 0x00000002 -#define DRMDMA1_STATUS_REG__RB_FULL__SHIFT__SI 0x00000003 -#define DRMDMA1_STATUS_REG__RD_DATA_FULL__SHIFT__SI 0x00000009 -#define DRMDMA1_STATUS_REG__RD_DATA_IDLE__SHIFT__SI 0x00000008 -#define DRMDMA1_STATUS_REG__REG_IDLE__SHIFT__SI 0x00000001 -#define DRMDMA1_STATUS_REG__SEM_IDLE__SHIFT__SI 0x0000001a -#define DRMDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT__SI 0x0000001b -#define DRMDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT__SI 0x0000001c -#define DRMDMA1_STATUS_REG__TILE_IDLE__SHIFT__SI 0x0000000c -#define DRMDMA1_TILING_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT__SI 0x00000008 -#define DRMDMA1_TILING_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT__SI 0x00000018 -#define DRMDMA1_TILING_CONFIG__NUM_GPUS__SHIFT__SI 0x00000014 -#define DRMDMA1_TILING_CONFIG__NUM_LOWER_PIPES__SHIFT__SI 0x0000001e -#define DRMDMA1_TILING_CONFIG__NUM_PIPES__SHIFT__SI 0x00000000 -#define DRMDMA1_TILING_CONFIG__NUM_SHADER_ENGINES__SHIFT__SI 0x0000000c -#define DRMDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT__SI 0x00000004 -#define DRMDMA1_TILING_CONFIG__ROW_SIZE__SHIFT__SI 0x0000001c -#define DRMDMA1_TILING_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT__SI 0x00000010 -#define DRMDMA_CLK_CTRL__OFF_HYSTERESIS__SHIFT__SI 0x00000004 -#define DRMDMA_CLK_CTRL__ON_DELAY__SHIFT__SI 0x00000000 -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT__SI 0x0000001f -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT__SI 0x0000001e -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT__SI 0x0000001d -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT__SI 0x0000001c -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT__SI 0x0000001b -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT__SI 0x0000001a -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT__SI 0x00000019 -#define DRMDMA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT__SI 0x00000018 -#define DRMDMA_CNTL__CTXEMPTY_INT_ENABLE__SHIFT__SI 0x0000001c -#define DRMDMA_CNTL__DATA_SWAP_ENABLE__SHIFT__SI 0x00000003 -#define DRMDMA_CNTL__DRM_CREDIT__SHIFT__SI 0x00000008 -#define DRMDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT__SI 0x00000004 -#define DRMDMA_CNTL__IB_PREEMPT_ENABLE__SHIFT__SI 0x0000001d -#define DRMDMA_CNTL__MC_RDREQ_CREDIT__SHIFT__SI 0x00000017 -#define DRMDMA_CNTL__MC_WRREQ_CREDIT__SHIFT__SI 0x0000000d -#define DRMDMA_CNTL__MC_WR_CLEAN_CNT__SHIFT__SI 0x00000012 -#define DRMDMA_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT__SI 0x00000001 -#define DRMDMA_CNTL__SEM_WAIT_INT_ENABLE__SHIFT__SI 0x00000002 -#define DRMDMA_CNTL__SLOW_TILED_WRITE_MODE__SHIFT__SI 0x0000001f -#define DRMDMA_CNTL__TRAP_ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA_CONTEXT_CNTL__RESTORE_COUNT__SHIFT__SI 0x00000000 -#define DRMDMA_CONTEXT_CNTL__RESUME_CTX__SHIFT__SI 0x00000010 -#define DRMDMA_CONTEXT_CNTL__SESSION_SEL__SHIFT__SI 0x00000018 -#define DRMDMA_CRC_VALUE__CRC_VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM1_CTRL__DRM1_CREDIT__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERDATA0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERDATA1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERDATA2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERDATA3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERKEY0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERKEY1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERKEY2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_COUNTERKEY3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_IVLOAD0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_IVLOAD1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_IVLOAD2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_IVLOAD3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_IVLOAD4__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_OFFSET__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_UNROLLKEY__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_WRAPPEDKEY0__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_WRAPPEDKEY1__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_WRAPPEDKEY2__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_DRM_WRAPPEDKEY3__VALUE__SHIFT__SI 0x00000000 -#define DRMDMA_FAULT_ADDR_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA_FAULT_ADDR_LO__ADDR__SHIFT__SI 0x0000000c -#define DRMDMA_FIFO_CNTL__CG_STATUS_OUTPUT__SHIFT__SI 0x00000017 -#define DRMDMA_FIFO_CNTL__COPY_OVERLAP_ENABLE__SHIFT__SI 0x00000010 -#define DRMDMA_FIFO_CNTL__DATA_FIFO_SIZE__SHIFT__SI 0x00000004 -#define DRMDMA_FIFO_CNTL__DRM_FIFO_SIZE__SHIFT__SI 0x0000000a -#define DRMDMA_FIFO_CNTL__GPU_ID__SHIFT__SI 0x0000000c -#define DRMDMA_FIFO_CNTL__IB_FIFO_SIZE__SHIFT__SI 0x00000002 -#define DRMDMA_FIFO_CNTL__MC_WR_ADDR_FIFO_SIZE__SHIFT__SI 0x00000006 -#define DRMDMA_FIFO_CNTL__MC_WR_DATA_FIFO_SIZE__SHIFT__SI 0x00000008 -#define DRMDMA_FIFO_CNTL__RB_FIFO_SIZE__SHIFT__SI 0x00000000 -#define DRMDMA_FIFO_CNTL__WRITE_OVERLAP_ENABLE__SHIFT__SI 0x00000011 -#define DRMDMA_IB_BASE_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA_IB_BASE_LO__ADDR__SHIFT__SI 0x00000005 -#define DRMDMA_IB_CNTL__CMD_VMID_FORCE__SHIFT__SI 0x0000001f -#define DRMDMA_IB_CNTL__CMD_VMID__SHIFT__SI 0x00000018 -#define DRMDMA_IB_CNTL__IB_ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA_IB_CNTL__IB_SWAP_ENABLE__SHIFT__SI 0x00000004 -#define DRMDMA_IB_OFFSET__OFFSET__SHIFT__SI 0x00000000 -#define DRMDMA_IB_RPTR__OFFSET__SHIFT__SI 0x00000002 -#define DRMDMA_IB_SIZE__SIZE__SHIFT__SI 0x00000000 -#define DRMDMA_PERF_CNTL__CLEAR0__SHIFT__SI 0x00000001 -#define DRMDMA_PERF_CNTL__CLEAR1__SHIFT__SI 0x00000009 -#define DRMDMA_PERF_CNTL__ENABLE0__SHIFT__SI 0x00000000 -#define DRMDMA_PERF_CNTL__ENABLE1__SHIFT__SI 0x00000008 -#define DRMDMA_PERF_CNTL__SELECT0__SHIFT__SI 0x00000002 -#define DRMDMA_PERF_CNTL__SELECT1__SHIFT__SI 0x0000000a -#define DRMDMA_PERF_COUNT0__PERF_COUNT__SHIFT__SI 0x00000000 -#define DRMDMA_PERF_COUNT1__PERF_COUNT__SHIFT__SI 0x00000000 -#define DRMDMA_PREEMPT__PREEMPT__SHIFT__SI 0x00000000 -#define DRMDMA_PRIV_MODE__MC_PRIV_MODE__SHIFT__SI 0x00000000 -#define DRMDMA_PRIV_MODE__MEM_POWER_OVERRIDE__SHIFT__SI 0x00000008 -#define DRMDMA_RB_BASE__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA_RB_CNTL__RB_ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA_RB_CNTL__RB_SIZE__SHIFT__SI 0x00000001 -#define DRMDMA_RB_CNTL__RB_SWAP_ENABLE__SHIFT__SI 0x00000009 -#define DRMDMA_RB_CNTL__RB_TRAN__SHIFT__SI 0x00000008 -#define DRMDMA_RB_CNTL__RB_VMID__SHIFT__SI 0x00000018 -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__SI 0x0000000c -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__SI 0x0000000d -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__SI 0x00000010 -#define DRMDMA_RB_CNTL__RPTR_WRITEBACK_TRAN__SHIFT__SI 0x0000000e -#define DRMDMA_RB_RPTR_ADDR_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA_RB_RPTR_ADDR_LO__ADDR__SHIFT__SI 0x00000002 -#define DRMDMA_RB_RPTR__OFFSET__SHIFT__SI 0x00000002 -#define DRMDMA_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__SI 0x00000000 -#define DRMDMA_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__SI 0x00000002 -#define DRMDMA_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__SI 0x00000000 -#define DRMDMA_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__SI 0x00000004 -#define DRMDMA_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__SI 0x00000010 -#define DRMDMA_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__SI 0x00000001 -#define DRMDMA_RB_WPTR_POLL_CNTL__TRAN__SHIFT__SI 0x00000002 -#define DRMDMA_RB_WPTR__OFFSET__SHIFT__SI 0x00000002 -#define DRMDMA_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT__SI 0x00000000 -#define DRMDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT__SI 0x00000000 -#define DRMDMA_STATUS_REG__DRM_IDLE__SHIFT__SI 0x00000017 -#define DRMDMA_STATUS_REG__DRM_MASK_FULL__SHIFT__SI 0x00000018 -#define DRMDMA_STATUS_REG__DRM_REQ_STALL__SHIFT__SI 0x00000019 -#define DRMDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT__SI 0x0000000b -#define DRMDMA_STATUS_REG__EX_IDLE__SHIFT__SI 0x0000000a -#define DRMDMA_STATUS_REG__IB_CMD_FULL__SHIFT__SI 0x00000007 -#define DRMDMA_STATUS_REG__IB_CMD_IDLE__SHIFT__SI 0x00000006 -#define DRMDMA_STATUS_REG__IDLE__SHIFT__SI 0x00000000 -#define DRMDMA_STATUS_REG__INT_IDLE__SHIFT__SI 0x0000001e -#define DRMDMA_STATUS_REG__INT_REQ_STALL__SHIFT__SI 0x0000001f -#define DRMDMA_STATUS_REG__MC_RD_IDLE__SHIFT__SI 0x00000013 -#define DRMDMA_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT__SI 0x00000016 -#define DRMDMA_STATUS_REG__MC_RD_RET_STALL__SHIFT__SI 0x00000015 -#define DRMDMA_STATUS_REG__MC_RD_STALL__SHIFT__SI 0x00000014 -#define DRMDMA_STATUS_REG__MC_WR_AFIFO_FULL__SHIFT__SI 0x0000000e -#define DRMDMA_STATUS_REG__MC_WR_CLEAN_PENDING__SHIFT__SI 0x00000011 -#define DRMDMA_STATUS_REG__MC_WR_CLEAN_STALL__SHIFT__SI 0x00000012 -#define DRMDMA_STATUS_REG__MC_WR_DFIFO_FULL__SHIFT__SI 0x0000000f -#define DRMDMA_STATUS_REG__MC_WR_IDLE__SHIFT__SI 0x0000000d -#define DRMDMA_STATUS_REG__MC_WR_STALL__SHIFT__SI 0x00000010 -#define DRMDMA_STATUS_REG__RB_CMD_FULL__SHIFT__SI 0x00000005 -#define DRMDMA_STATUS_REG__RB_CMD_IDLE__SHIFT__SI 0x00000004 -#define DRMDMA_STATUS_REG__RB_EMPTY__SHIFT__SI 0x00000002 -#define DRMDMA_STATUS_REG__RB_FULL__SHIFT__SI 0x00000003 -#define DRMDMA_STATUS_REG__RD_DATA_FULL__SHIFT__SI 0x00000009 -#define DRMDMA_STATUS_REG__RD_DATA_IDLE__SHIFT__SI 0x00000008 -#define DRMDMA_STATUS_REG__REG_IDLE__SHIFT__SI 0x00000001 -#define DRMDMA_STATUS_REG__SEM_IDLE__SHIFT__SI 0x0000001a -#define DRMDMA_STATUS_REG__SEM_REQ_STALL__SHIFT__SI 0x0000001b -#define DRMDMA_STATUS_REG__SEM_RESP_STATE__SHIFT__SI 0x0000001c -#define DRMDMA_STATUS_REG__TILE_IDLE__SHIFT__SI 0x0000000c -#define DRMDMA_TILING_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT__SI 0x00000008 -#define DRMDMA_TILING_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT__SI 0x00000018 -#define DRMDMA_TILING_CONFIG__NUM_GPUS__SHIFT__SI 0x00000014 -#define DRMDMA_TILING_CONFIG__NUM_LOWER_PIPES__SHIFT__SI 0x0000001e -#define DRMDMA_TILING_CONFIG__NUM_PIPES__SHIFT__SI 0x00000000 -#define DRMDMA_TILING_CONFIG__NUM_SHADER_ENGINES__SHIFT__SI 0x0000000c -#define DRMDMA_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT__SI 0x00000004 -#define DRMDMA_TILING_CONFIG__ROW_SIZE__SHIFT__SI 0x0000001c -#define DRMDMA_TILING_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT__SI 0x00000010 -#define DRM_ARB_PRIORITY__SLOT0__SHIFT 0x00000000 -#define DRM_ARB_PRIORITY__SLOT1__SHIFT 0x00000004 -#define DRM_ARB_PRIORITY__SLOT2__SHIFT 0x00000008 -#define DRM_ARB_PRIORITY__SLOT3__SHIFT 0x0000000c -#define DRM_ARB_PRIORITY__SLOT4__SHIFT 0x00000010 -#define DRM_ARB_PRIORITY__SLOT5__SHIFT 0x00000014 -#define DRM_ARB_PRIORITY__SLOT6__SHIFT 0x00000018 -#define DRM_ARB_PRIORITY__SLOT7__SHIFT 0x0000001c -#define DRM_BYTESWAP__CLIENT0_BYTESWAP__SHIFT 0x00000008 -#define DRM_BYTESWAP__CLIENT1_BYTESWAP__SHIFT 0x00000010 -#define DRM_BYTESWAP__CLIENT2_BYTESWAP__SHIFT 0x00000000 -#define DRM_DEBUG_ID__DRM_DEBUG_ID__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX0__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX1__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX2__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX3__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX4__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX5__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX6__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG_INDEX7__DRM_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define DRM_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x00000018 -#define DRM_DEBUG__DEBUG_UNUSED_0__SHIFT 0x00000000 -#define DRM_DEBUG__DEBUG_UNUSED_1__SHIFT 0x0000001d -#define DRM_HFS_CONT__RESERVED__SHIFT 0x00000000 -#define DRM_HFS_HW_NONCE0__HW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_HW_NONCE1__HW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_HW_NONCE2__HW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_HW_NONCE3__HW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_HW_RESULT0__HW_RESULT__SHIFT 0x00000000 -#define DRM_HFS_HW_RESULT1__HW_RESULT__SHIFT 0x00000000 -#define DRM_HFS_HW_RESULT2__HW_RESULT__SHIFT 0x00000000 -#define DRM_HFS_HW_RESULT3__HW_RESULT__SHIFT 0x00000000 -#define DRM_HFS_SECRET_SEL__SEL0__SHIFT 0x00000000 -#define DRM_HFS_SECRET_SEL__SEL1__SHIFT 0x00000008 -#define DRM_HFS_SECRET_SEL__SEL2__SHIFT 0x00000010 -#define DRM_HFS_SECRET_SEL__SEL3__SHIFT 0x00000018 -#define DRM_HFS_START__HFS_TYPE__SHIFT 0x00000000 -#define DRM_HFS_SW_NONCE0__SW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_SW_NONCE1__SW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_SW_NONCE2__SW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_SW_NONCE3__SW_NONCE__SHIFT 0x00000000 -#define DRM_HFS_SW_RESULT0__SW_RESULT__SHIFT 0x00000000 -#define DRM_HFS_SW_RESULT1__SW_RESULT__SHIFT 0x00000000 -#define DRM_HFS_SW_RESULT2__SW_RESULT__SHIFT 0x00000000 -#define DRM_HFS_SW_RESULT3__SW_RESULT__SHIFT 0x00000000 -#define DRM_ID_EFUSE__DEBUG_MODE__SHIFT 0x00000000 -#define DRM_ID_EFUSE__HFS_FAIL__SHIFT 0x00000001 -#define DRM_ID_EFUSE__HFS_ID__SHIFT 0x00000003 -#define DRM_ID_EFUSE__HFS_WAY__SHIFT 0x00000002 -#define DRM_IH_CREDITS__IH_CREDITS__SHIFT 0x00000000 -#define DRM_INT_ACK__DH1_DONE__SHIFT 0x00000000 -#define DRM_INT_ACK__DH2_DONE__SHIFT 0x00000001 -#define DRM_INT_ACK__HFS_DONE__SHIFT 0x00000002 -#define DRM_INT_ACK__INVALID_CLIENT0__SHIFT 0x00000009 -#define DRM_INT_ACK__INVALID_CLIENT1__SHIFT 0x0000000a -#define DRM_INT_ACK__INVALID_CLIENT2__SHIFT 0x00000008 -#define DRM_INT_ACK__SIG_DONE__SHIFT 0x00000003 -#define DRM_INT_ACK__SIG_VALID__SHIFT 0x00000004 -#define DRM_INT_ACK__TIMEOUT_CLIENT0__SHIFT 0x00000006 -#define DRM_INT_ACK__TIMEOUT_CLIENT1__SHIFT 0x00000007 -#define DRM_INT_ACK__TIMEOUT_CLIENT2__SHIFT 0x00000005 -#define DRM_INT_MASK__DH1_DONE__SHIFT 0x00000000 -#define DRM_INT_MASK__DH2_DONE__SHIFT 0x00000001 -#define DRM_INT_MASK__HFS_DONE__SHIFT 0x00000002 -#define DRM_INT_MASK__INVALID_CLIENT0__SHIFT 0x00000009 -#define DRM_INT_MASK__INVALID_CLIENT1__SHIFT 0x0000000a -#define DRM_INT_MASK__INVALID_CLIENT2__SHIFT 0x00000008 -#define DRM_INT_MASK__SIG_DONE__SHIFT 0x00000003 -#define DRM_INT_MASK__SIG_VALID__SHIFT 0x00000004 -#define DRM_INT_MASK__TIMEOUT_CLIENT0__SHIFT 0x00000006 -#define DRM_INT_MASK__TIMEOUT_CLIENT1__SHIFT 0x00000007 -#define DRM_INT_MASK__TIMEOUT_CLIENT2__SHIFT 0x00000005 -#define DRM_INT_STATUS__DH1_DONE__SHIFT 0x00000000 -#define DRM_INT_STATUS__DH2_DONE__SHIFT 0x00000001 -#define DRM_INT_STATUS__HFS_DONE__SHIFT 0x00000002 -#define DRM_INT_STATUS__INVALID_CLIENT0__SHIFT 0x00000009 -#define DRM_INT_STATUS__INVALID_CLIENT1__SHIFT 0x0000000a -#define DRM_INT_STATUS__INVALID_CLIENT2__SHIFT 0x00000008 -#define DRM_INT_STATUS__SIG_DONE__SHIFT 0x00000003 -#define DRM_INT_STATUS__SIG_VALID__SHIFT 0x00000004 -#define DRM_INT_STATUS__TIMEOUT_CLIENT0__SHIFT 0x00000006 -#define DRM_INT_STATUS__TIMEOUT_CLIENT1__SHIFT 0x00000007 -#define DRM_INT_STATUS__TIMEOUT_CLIENT2__SHIFT 0x00000005 -#define DRM_KEYGEN_CONT__RESERVED__SHIFT 0x00000000 -#define DRM_KEYGEN_RADDR__RADDR__SHIFT 0x00000000 -#define DRM_KEYGEN_RDATA__RDATA__SHIFT 0x00000000 -#define DRM_KEYGEN_START__RESERVED__SHIFT 0x00000000 -#define DRM_KEYGEN_WADDR__WADDR__SHIFT 0x00000000 -#define DRM_KEYGEN_WDATA__WDATA__SHIFT 0x00000000 -#define DRM_PERFCOUNTER1_HI__HI__SHIFT 0x00000000 -#define DRM_PERFCOUNTER1_LO__LO__SHIFT 0x00000000 -#define DRM_PERFCOUNTER1_SELECT__PERFCOUNTER1_SELECT__SHIFT 0x00000000 -#define DRM_PERFCOUNTER2_HI__HI__SHIFT 0x00000000 -#define DRM_PERFCOUNTER2_LO__LO__SHIFT 0x00000000 -#define DRM_PERFCOUNTER2_SELECT__PERFCOUNTER2_SELECT__SHIFT 0x00000000 -#define DRM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 -#define DRM_PROTO_ADDR__ADDR__SHIFT 0x00000000 -#define DRM_PROTO_DATA__DATA__SHIFT 0x00000000 -#define DRM_RESET__CLIENT0_RESET__SHIFT 0x00000008 -#define DRM_RESET__CLIENT1_RESET__SHIFT 0x00000010 -#define DRM_RESET__CLIENT2_RESET__SHIFT 0x00000000 -#define DRM_SIG_FINISH__RESERVED__SHIFT 0x00000000 -#define DRM_SIG_INVALID__INVALID__SHIFT 0x00000000 -#define DRM_SIG_RADDR__ADDR__SHIFT 0x00000000 -#define DRM_SIG_RDATA__DATA__SHIFT 0x00000000 -#define DRM_SIG_RESULT0__RESULT__SHIFT 0x00000000 -#define DRM_SIG_RESULT1__RESULT__SHIFT 0x00000000 -#define DRM_SIG_RESULT2__RESULT__SHIFT 0x00000000 -#define DRM_SIG_RESULT3__RESULT__SHIFT 0x00000000 -#define DRM_SIG_START__NONCE__SHIFT 0x00000000 -#define DRM_STATUS__AUTH_STATE__SHIFT 0x00000019 -#define DRM_STATUS__CLIENT0_BUSY__SHIFT 0x00000004 -#define DRM_STATUS__CLIENT0_PARSE_BUSY__SHIFT 0x0000000b -#define DRM_STATUS__CLIENT1_BUSY__SHIFT 0x00000002 -#define DRM_STATUS__CLIENT1_PARSE_BUSY__SHIFT 0x00000009 -#define DRM_STATUS__CLIENT2_BUSY__SHIFT 0x00000003 -#define DRM_STATUS__CLIENT2_PARSE_BUSY__SHIFT 0x0000000a -#define DRM_STATUS__DH_ACTIVE__SHIFT 0x00000014 -#define DRM_STATUS__DH_BUSY1__SHIFT 0x00000008 -#define DRM_STATUS__DH_BUSY2__SHIFT 0x00000007 -#define DRM_STATUS__DH_DONE__SHIFT 0x00000011 -#define DRM_STATUS__DRM_BUSY__SHIFT 0x00000000 -#define DRM_STATUS__DRM_INIT__SHIFT 0x00000012 -#define DRM_STATUS__HFS_ACTIVE__SHIFT 0x00000015 -#define DRM_STATUS__HFS_BUSY__SHIFT 0x00000006 -#define DRM_STATUS__HFS_DONE__SHIFT 0x00000010 -#define DRM_STATUS__HFS_PASS__SHIFT 0x00000018 -#define DRM_STATUS__SIG_ACTIVE__SHIFT 0x00000016 -#define DRM_STATUS__SIG_BUSY__SHIFT 0x00000005 -#define DRM_STATUS__SIG_RD_BUSY__SHIFT 0x0000000c -#define DRM_STATUS__TRNG_BUSY__SHIFT 0x00000001 -#define DRM_TIMEOUT__CLIENT0_TIMEOUT__SHIFT 0x00000008 -#define DRM_TIMEOUT__CLIENT1_TIMEOUT__SHIFT 0x00000010 -#define DRM_TIMEOUT__CLIENT2_TIMEOUT__SHIFT 0x00000000 -#define DRM_TRNG_CNTL__EN_LFSR__SHIFT 0x00000001 -#define DRM_TRNG_CNTL__EN_OSC__SHIFT 0x00000000 -#define DRM_TRNG_CNTL__EN_OUT__SHIFT 0x00000008 -#define DRM_TRNG_DATA__RNG_VAL__SHIFT 0x00000000 -#define DTO_VCLK_DENOMIN__DTO_EN__SHIFT__SI 0x0000001f -#define DTO_VCLK_DENOMIN__DTO_VCLK_DENOMIN__SHIFT__SI 0x00000000 -#define DTO_VCLK_INC_CORR__DTO_VCLK_INC_CORR__SHIFT__SI 0x00000000 -#define DTO_VCLK_INC__DTO_VCLK_INC__SHIFT__SI 0x00000000 -#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT__SI 0x00000011 -#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT__SI 0x00000008 -#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT__SI 0x00000010 -#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT__SI 0x00000000 -#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT__SI 0x00000012 -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT__SI 0x00000011 -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT__SI 0x00000008 -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT__SI 0x00000010 -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT__SI 0x00000000 -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT__SI 0x00000012 -#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT__SI 0x00000014 -#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT__SI 0x00000018 -#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT__SI 0x0000001c -#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT__SI 0x00000011 -#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT__SI 0x00000008 -#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT__SI 0x00000010 -#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT__SI 0x00000000 -#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT__SI 0x00000012 -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_CAPTURE_START__SHIFT__SI 0x00000017 -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_COLOR_IN__SHIFT__SI 0x00000002 -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_COLOR_OUT__SHIFT__SI 0x00000018 -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_HBLANKB__SHIFT__SI 0x00000001 -#define DVOA_DEBUG3__DOUT_DVOA_MAPPER_PHASE__SHIFT__SI 0x00000000 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_DISP_IO_DVOCLK__SHIFT__SI 0x00000003 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_READ_ADD_INC__SHIFT__SI 0x00000000 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_READ_ADD__SHIFT__SI 0x00000005 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_START_DVOCLK_Q__SHIFT__SI 0x00000002 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_START_DVOCLK_RISE__SHIFT__SI 0x00000004 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_START_PIXCLK__SHIFT__SI 0x00000001 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS1_WRITE_ADD__SHIFT__SI 0x00000007 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_DE_IN__SHIFT__SI 0x00000014 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_FRAMEPULSE_IN__SHIFT__SI 0x00000010 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_HSYNC_IN__SHIFT__SI 0x00000012 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_PHASE__SHIFT__SI 0x00000015 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_START__SHIFT__SI 0x00000013 -#define DVOA_DEBUG4__DOUT_DVOA_CHANNEL_BUS2_VSYNC_IN__SHIFT__SI 0x00000011 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_CAP_START_IN__SHIFT__SI 0x00000016 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_COLOR_IN__SHIFT__SI 0x00000004 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DE_IN__SHIFT__SI 0x00000003 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DISP_IO_DVOCLK__SHIFT__SI 0x00000011 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DVOCLK_C__SHIFT__SI 0x00000018 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_DVOCLK_D__SHIFT__SI 0x00000019 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_HSYNC_IN__SHIFT__SI 0x00000001 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_PHASE__SHIFT__SI 0x0000000c -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_READ_ADD_INC__SHIFT__SI 0x00000017 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_READ_ADD__SHIFT__SI 0x0000000f -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START_DVOCLK_RISE__SHIFT__SI 0x00000015 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START_DVOCLK__SHIFT__SI 0x00000014 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START_PIXCLK__SHIFT__SI 0x00000013 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_START__SHIFT__SI 0x00000012 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_VSYNC_IN__SHIFT__SI 0x00000002 -#define DVOA_DEBUG5__DOUT_DVOA_CHANNEL_WRITE_ADD__SHIFT__SI 0x0000000d -#define DVOA_DEBUG5__DOUT_DVOA_PIXCLK__SHIFT__SI 0x00000000 -#define DVOA_DEBUG6__DOUT_DVOA_CAP_START_ON_DVOCLK__SHIFT__SI 0x0000001c -#define DVOA_DEBUG6__DOUT_DVOA_DVOCLK__SHIFT__SI 0x00000000 -#define DVOA_DEBUG6__DOUT_DVOA_DVOCNTL__SHIFT__SI 0x00000001 -#define DVOA_DEBUG6__DOUT_DVOA_DVODATA__SHIFT__SI 0x00000004 -#define DVOA_DEBUG6__DOUT_DVOA_STEREOSYNC_ON_DVOCLK__SHIFT__SI 0x0000001d -#define DVOA_DEBUG7__DOUT_DVOA_DDR_DVOCLK_DUPLICATE__SHIFT__SI 0x0000000c -#define DVOA_DEBUG7__DOUT_DVOA_DDR_DVOCLK__SHIFT__SI 0x00000000 -#define DVOA_DEBUG7__DOUT_DVOA_DDR_MVP_DVOCLK_DUPLICATE__SHIFT__SI 0x00000010 -#define DVOA_DEBUG7__DOUT_DVOA_DDR_MVP_DVOCLK__SHIFT__SI 0x00000004 -#define DVOA_DEBUG7__DOUT_DVOA_DVOCNTL_D__SHIFT__SI 0x00000001 -#define DVOA_DEBUG7__DOUT_DVOA_DVO_DE__SHIFT__SI 0x0000000d -#define DVOA_DEBUG7__DOUT_DVOA_DVO_HSYNC__SHIFT__SI 0x0000000e -#define DVOA_DEBUG7__DOUT_DVOA_DVO_VSYNC__SHIFT__SI 0x0000000f -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVOCNTL_D__SHIFT__SI 0x00000005 -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVO_DE__SHIFT__SI 0x00000011 -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVO_HSYNC__SHIFT__SI 0x00000012 -#define DVOA_DEBUG7__DOUT_DVOA_MVP_DVO_VSYNC__SHIFT__SI 0x00000013 -#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT__SI 0x00000018 -#define DVO_CONTROL__DVO_CTL3__SHIFT__SI 0x0000001f -#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT__SI 0x00000008 -#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT__SI 0x00000012 -#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT__SI 0x00000000 -#define DVO_CONTROL__DVO_REORDER_BITS__SHIFT__SI 0x0000001c -#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT__SI 0x00000010 -#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT__SI 0x00000001 -#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT__SI 0x00000011 -#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT__SI 0x00000000 -#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT__SI 0x00000000 -#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT__SI 0x00000010 -#define DVO_ENABLE__DVO_ENABLE__SHIFT__SI 0x00000000 -#define DVO_ENABLE__DVO_PIXEL_ENCODING__SHIFT__SI 0x00000008 -#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT__SI 0x00000008 -#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT__SI 0x00000000 -#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT__SI 0x00000000 -#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT__SI 0x00000010 -#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT__SI 0x0000000c -#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT__SI 0x00000008 -#define DVO_STRENGTH_CONTROL__DVOCLK_SRN__SHIFT__SI 0x00000019 -#define DVO_STRENGTH_CONTROL__DVOCLK_SRP__SHIFT__SI 0x00000018 -#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT__SI 0x0000001c -#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT__SI 0x0000001d -#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT__SI 0x00000004 -#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT__SI 0x00000000 -#define DVO_STRENGTH_CONTROL__DVO_SRN__SHIFT__SI 0x00000011 -#define DVO_STRENGTH_CONTROL__DVO_SRP__SHIFT__SI 0x00000010 -#define EFUSE_STATUS__CCF0_VALID__SHIFT__CI 0x00000000 -#define EFUSE_STATUS__RF0__SHIFT__CI 0x00000010 -#define EXP0__RESERVED__SHIFT 0x00000000 -#define EXP1__RESERVED__SHIFT 0x00000000 -#define EXP2__RESERVED__SHIFT 0x00000000 -#define EXP3__RESERVED__SHIFT 0x00000000 -#define EXP4__RESERVED__SHIFT 0x00000000 -#define EXP5__RESERVED__SHIFT 0x00000000 -#define EXP6__RESERVED__SHIFT 0x00000000 -#define EXP7__RESERVED__SHIFT 0x00000000 -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_DRIVER_ENABLE__SHIFT__SI 0x00000008 -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_POST_DIV_FORCE__SHIFT__SI 0x00000010 -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_POST_DIV_RESET__SHIFT__SI 0x00000000 -#define EXT1_DIFF_POST_DIV_CNTL__EXT1_DIFF_POST_DIV_SELECT__SHIFT__SI 0x00000004 -#define EXT1_PPLL_CNTL__EXT1_PPLL_CP__SHIFT__SI 0x00000008 -#define EXT1_PPLL_CNTL__EXT1_PPLL_CTL__SHIFT__SI 0x00000000 -#define EXT1_PPLL_CNTL__EXT1_PPLL_IBIAS__SHIFT__SI 0x00000018 -#define EXT1_PPLL_CNTL__EXT1_PPLL_LF_MODE__SHIFT__SI 0x0000000c -#define EXT1_PPLL_FB_DIV__EXT1_PPLL_FB_DIV_FRACTION_CNTL__SHIFT__SI 0x00000004 -#define EXT1_PPLL_FB_DIV__EXT1_PPLL_FB_DIV_FRACTION__SHIFT__SI 0x00000000 -#define EXT1_PPLL_FB_DIV__EXT1_PPLL_FB_DIV__SHIFT__SI 0x00000010 -#define EXT1_PPLL_POST_DIV_SRC__EXT1_PPLL_POST_DIV_SRC__SHIFT__SI 0x00000000 -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV_HSYNC_EDGE__SHIFT__SI 0x00000011 -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV_HSYNC_EN__SHIFT__SI 0x00000010 -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV_HSYNC__SHIFT__SI 0x00000014 -#define EXT1_PPLL_POST_DIV__EXT1_PPLL_POST_DIV__SHIFT__SI 0x00000000 -#define EXT1_PPLL_REF_DIV_SRC__EXT1_PPLL_REF_DIV_SRC__SHIFT__SI 0x00000000 -#define EXT1_PPLL_REF_DIV__EXT1_PPLL_CALIBRATION_REF_DIV__SHIFT__SI 0x0000000c -#define EXT1_PPLL_REF_DIV__EXT1_PPLL_REF_DIV__SHIFT__SI 0x00000000 -#define EXT1_PPLL_UPDATE_CNTL__EXT1_PPLL_AUTO_RESET_DISABLE__SHIFT__SI 0x00000010 -#define EXT1_PPLL_UPDATE_CNTL__EXT1_PPLL_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define EXT1_PPLL_UPDATE_CNTL__EXT1_PPLL_UPDATE_POINT__SHIFT__SI 0x00000008 -#define EXT1_PPLL_UPDATE_LOCK__EXT1_PPLL_UPDATE_LOCK__SHIFT__SI 0x00000000 -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_DRIVER_ENABLE__SHIFT__SI 0x00000008 -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_POST_DIV_FORCE__SHIFT__SI 0x00000010 -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_POST_DIV_RESET__SHIFT__SI 0x00000000 -#define EXT2_DIFF_POST_DIV_CNTL__EXT2_DIFF_POST_DIV_SELECT__SHIFT__SI 0x00000004 -#define EXT2_PPLL_CNTL__EXT2_PPLL_CP__SHIFT__SI 0x00000008 -#define EXT2_PPLL_CNTL__EXT2_PPLL_CTL__SHIFT__SI 0x00000000 -#define EXT2_PPLL_CNTL__EXT2_PPLL_IBIAS__SHIFT__SI 0x00000018 -#define EXT2_PPLL_CNTL__EXT2_PPLL_LF_MODE__SHIFT__SI 0x0000000c -#define EXT2_PPLL_FB_DIV__EXT2_PPLL_FB_DIV_FRACTION_CNTL__SHIFT__SI 0x00000004 -#define EXT2_PPLL_FB_DIV__EXT2_PPLL_FB_DIV_FRACTION__SHIFT__SI 0x00000000 -#define EXT2_PPLL_FB_DIV__EXT2_PPLL_FB_DIV__SHIFT__SI 0x00000010 -#define EXT2_PPLL_POST_DIV_SRC__EXT2_PPLL_POST_DIV_SRC__SHIFT__SI 0x00000000 -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV_HSYNC_EDGE__SHIFT__SI 0x00000011 -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV_HSYNC_EN__SHIFT__SI 0x00000010 -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV_HSYNC__SHIFT__SI 0x00000014 -#define EXT2_PPLL_POST_DIV__EXT2_PPLL_POST_DIV__SHIFT__SI 0x00000000 -#define EXT2_PPLL_REF_DIV_SRC__EXT2_PPLL_REF_DIV_SRC__SHIFT__SI 0x00000000 -#define EXT2_PPLL_REF_DIV__EXT2_PPLL_CALIBRATION_REF_DIV__SHIFT__SI 0x0000000c -#define EXT2_PPLL_REF_DIV__EXT2_PPLL_REF_DIV__SHIFT__SI 0x00000000 -#define EXT2_PPLL_UPDATE_CNTL__EXT2_PPLL_AUTO_RESET_DISABLE__SHIFT__SI 0x00000010 -#define EXT2_PPLL_UPDATE_CNTL__EXT2_PPLL_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define EXT2_PPLL_UPDATE_CNTL__EXT2_PPLL_UPDATE_POINT__SHIFT__SI 0x00000008 -#define EXT2_PPLL_UPDATE_LOCK__EXT2_PPLL_UPDATE_LOCK__SHIFT__SI 0x00000000 -#define EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT__SI 0x00000000 -#define EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT__SI 0x00000001 -#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT__SI 0x00000010 -#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT__SI 0x00000000 -#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT__SI 0x00000000 -#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT__SI 0x00000010 -#define FAST_AES0__RESERVED__SHIFT 0x00000000 -#define FAST_AES1__RESERVED__SHIFT 0x00000000 -#define FAST_AES2__RESERVED__SHIFT 0x00000000 -#define FAST_AES3__RESERVED__SHIFT 0x00000000 -#define FAST_AES4__RESERVED__SHIFT 0x00000000 -#define FAST_AES5__RESERVED__SHIFT 0x00000000 -#define FAST_AES6__RESERVED__SHIFT 0x00000000 -#define FAST_AES7__RESERVED__SHIFT 0x00000000 -#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT__SI 0x00000010 -#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT__SI 0x00000010 -#define FBC_CNTL__FBC_EN__SHIFT__SI 0x0000001f -#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT__SI 0x00000000 -#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT__SI 0x00000019 -#define FBC_CNTL__FBC_SRC_SEL__SHIFT__SI 0x00000001 -#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT__SI 0x00000010 -#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT__SI 0x00000011 -#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT__SI 0x00000012 -#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT__SI 0x00000013 -#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT__SI 0x00000014 -#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT__SI 0x00000000 -#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT__SI 0x00000008 -#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT__SI 0x0000000a -#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT__SI 0x00000009 -#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT__SI 0x0000000b -#define FBC_COMP_MODE__FBC_IND_EN__SHIFT__SI 0x00000010 -#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT__SI 0x00000000 -#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT__SI 0x00000000 -#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT__SI 0x00000010 -#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT__SI 0x00000000 -#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT__SI 0x00000010 -#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT__SI 0x00000010 -#define FBC_DEBUG0__FBC_DEBUG0__SHIFT__SI 0x00000011 -#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT__SI 0x00000018 -#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT__SI 0x00000000 -#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT__SI 0x00000008 -#define FBC_DEBUG1__FBC_DEBUG1__SHIFT__SI 0x00000000 -#define FBC_DEBUG2__FBC_DEBUG2__SHIFT__SI 0x00000000 -#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT__SI 0x00000004 -#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT__SI 0x00000008 -#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT__SI 0x00000003 -#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT__SI 0x00000000 -#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT__SI 0x00000000 -#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT__SI 0x00000000 -#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT__SI 0x00000000 -#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT__SI 0x0000001f -#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT__SI 0x00000000 -#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT__SI 0x00000000 -#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT__SI 0x00000000 -#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT__SI 0x00000000 -#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT__SI 0x00000000 -#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT__SI 0x00000000 -#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT__SI 0x00000000 -#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT__SI 0x00000000 -#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT__SI 0x00000000 -#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT__SI 0x00000000 -#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT__SI 0x00000000 -#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT__SI 0x00000000 -#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT__SI 0x00000000 -#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT__SI 0x00000000 -#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT__SI 0x00000000 -#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT__SI 0x00000000 -#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT__SI 0x00000000 -#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT__SI 0x00000000 -#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT__SI 0x00000010 -#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT__SI 0x00000000 -#define FBC_MISC__FBC_DIVIDE_X__SHIFT__SI 0x00000008 -#define FBC_MISC__FBC_DIVIDE_Y__SHIFT__SI 0x0000000a -#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT__SI 0x00000004 -#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT__SI 0x00000003 -#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT__SI 0x0000000c -#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT__SI 0x0000000b -#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT__SI 0x00000002 -#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT__SI 0x00000008 -#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT__SI 0x00000000 -#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT__SI 0x00000007 -#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT__CI 0x00000000 -#define FIRMWARE_FLAGS__RESERVED__SHIFT__CI 0x00000001 -#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT__CI 0x00000018 -#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT__SI 0x0000001a -#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT__SI 0x0000001c -#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT__SI 0x0000001e -#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT__SI 0x0000000d -#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT__SI 0x0000000f -#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT__SI 0x0000000e -#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT__SI 0x0000000c -#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT__SI 0x00000008 -#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT__SI 0x00000009 -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT__SI 0x00000014 -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT__SI 0x00000010 -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT__SI 0x00000015 -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT__SI 0x00000019 -#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT__SI 0x00000018 -#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT__SI 0x00000004 -#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT__SI 0x00000000 -#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT__SI 0x00000010 -#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT__SI 0x00000000 -#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT__SI 0x00000010 -#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT__SI 0x00000004 -#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT__SI 0x00000000 -#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT__SI 0x00000014 -#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT__SI 0x00000018 -#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT__SI 0x0000000c -#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT__SI 0x00000008 -#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT__SI 0x00000010 -#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT__SI 0x00000000 -#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT__SI 0x00000010 -#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT__SI 0x00000000 -#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT__SI 0x00000010 -#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT__SI 0x00000010 -#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT__SI 0x00000000 -#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT__SI 0x00000010 -#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT__SI 0x00000000 -#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT__SI 0x00000000 -#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT__SI 0x00000000 -#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT__SI 0x00000000 -#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT__SI 0x00000000 -#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT__SI 0x00000000 -#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT__SI 0x00000004 -#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT__SI 0x00000000 -#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT__SI 0x00000010 -#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT__SI 0x00000000 -#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT__SI 0x00000010 -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT__SI 0x00000000 -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT__SI 0x00000010 -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT__SI 0x00000008 -#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT__SI 0x0000000c -#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT__SI \ - 0x00000004 -#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT__SI \ - 0x00000000 -#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT__SI \ - 0x00000000 -#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT__SI \ - 0x00000000 -#define FREQ_CHANGE_TIMEOUT__FC_TIMEOUT_UNIT__SHIFT__SI 0x00000010 -#define FREQ_CHANGE_TIMEOUT__FC_TIMEOUT__SHIFT__SI 0x00000000 -#define FWD_CHROMA_BOT_ADDR__FWD_UV_BOT_BASE__SHIFT__SI 0x00000000 -#define FWD_CHROMA_TOP_ADDR__FWD_UV_TOP_BASE__SHIFT__SI 0x00000000 -#define FWD_LUMA_BOT_ADDR__FWD_Y_BOT_BASE__SHIFT__SI 0x00000000 -#define FWD_LUMA_TOP_ADDR__FWD_Y_TOP_BASE__SHIFT__SI 0x00000000 -#define FW_CHRONO_31_0__FW_CHRONO_31_0__SHIFT__CI__VI 0x00000000 -#define FW_CHRONO_63_32__FW_CHRONO_63_32__SHIFT__CI__VI 0x00000000 -#define FW_DBG_COUNTER_1__COUNT1__SHIFT__CI__VI 0x00000000 -#define FW_DBG_COUNTER_1__COUNT2__SHIFT__CI__VI 0x00000010 -#define FW_DBG_COUNTER_2__COUNT1__SHIFT__CI__VI 0x00000000 -#define FW_DBG_COUNTER_2__COUNT2__SHIFT__CI__VI 0x00000010 -#define FW_DBG_SIGNAL_1__DATA__SHIFT__CI__VI 0x00000000 -#define FW_DBG_SIGNAL_2__DATA__SHIFT__CI__VI 0x00000000 -#define FW_PC_WATCH_1__ADDR__SHIFT__CI__VI 0x00000000 -#define FW_PC_WATCH_2__ADDR__SHIFT__CI__VI 0x00000010 -#define FW_PC_WATCH_3__ADDR__SHIFT__CI__VI 0x00000000 -#define FW_PC_WATCH_4__ADDR__SHIFT__CI__VI 0x00000010 -#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT__CI__VI 0x00000006 -#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT__CI__VI 0x00000007 -#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT__CI__VI 0x00000000 -#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT__CI__VI 0x00000001 -#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT__CI__VI 0x00000002 -#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT__CI__VI 0x0000001f -#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT__CI__VI 0x00000010 -#define GARLIC_FLUSH_CNTL__DOORBELL__SHIFT__CI 0x0000000d -#define GARLIC_FLUSH_CNTL__SDMA1_RB_WPTR__SHIFT__CI 0x00000005 -#define GARLIC_FLUSH_CNTL__SDMA_RB_WPTR__SHIFT__CI 0x00000004 -#define GARLIC_FLUSH_CNTL__SPU_RBI_WPTR__SHIFT__CI 0x00000008 -#define GARLIC_FLUSH_CNTL__SPU_RBO_WPTR__SHIFT__CI 0x00000009 -#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT__CI__VI 0x00000003 -#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT__CI__VI 0x0000000a -#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT__CI__VI 0x0000000b -#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT__CI__VI 0x0000000c -#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT__CI__VI 0x00000000 -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 -#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e -#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 -#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 -#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x00000000 -#define GB_EDC_MODE__BYPASS__SHIFT 0x0000001f -#define GB_EDC_MODE__DED_MODE__SHIFT 0x00000014 -#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x00000010 -#define GB_EDC_MODE__PROP_FED__SHIFT 0x0000001d -#define GB_GPU_ID__GPU_ID__SHIFT 0x00000000 -#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT__CI__VI 0x00000002 -#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT__CI__VI 0x00000000 -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT__CI__VI 0x00000004 -#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT__CI__VI 0x00000006 -#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE0__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE0__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE0__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE0__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE0__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE10__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE10__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE10__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE10__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE10__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE11__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE11__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE11__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE11__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE11__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE12__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE12__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE12__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE12__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE12__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE13__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE13__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE13__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE13__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE13__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE14__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE14__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE14__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE14__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE14__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE15__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE15__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE15__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE15__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE15__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE16__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE16__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE16__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE16__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE16__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE17__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE17__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE17__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE17__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE17__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE18__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE18__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE18__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE18__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE18__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE19__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE19__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE19__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE19__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE19__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE1__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE1__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE1__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE1__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE1__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE20__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE20__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE20__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE20__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE20__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE21__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE21__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE21__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE21__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE21__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE22__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE22__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE22__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE22__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE22__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE23__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE23__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE23__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE23__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE23__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE24__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE24__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE24__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE24__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE24__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE25__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE25__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE25__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE25__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE25__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE26__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE26__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE26__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE26__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE26__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE27__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE27__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE27__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE27__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE27__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE28__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE28__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE28__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE28__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE28__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE29__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE29__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE29__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE29__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE29__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE2__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE2__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE2__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE2__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE2__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE30__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE30__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE30__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE30__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE30__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE31__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE31__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE31__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE31__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE31__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE3__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE3__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE3__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE3__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE3__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE4__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE4__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE4__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE4__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE4__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE5__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE5__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE5__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE5__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE5__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE6__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE6__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE6__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE6__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE6__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE7__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE7__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE7__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE7__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE7__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE8__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE8__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE8__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE8__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE8__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE9__BANK_HEIGHT__SHIFT__SI 0x00000010 -#define GB_TILE_MODE9__BANK_WIDTH__SHIFT__SI 0x0000000e -#define GB_TILE_MODE9__MACRO_TILE_ASPECT__SHIFT__SI 0x00000012 -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT__CI__VI 0x00000016 -#define GB_TILE_MODE9__MICRO_TILE_MODE__SHIFT__SI 0x00000000 -#define GB_TILE_MODE9__NUM_BANKS__SHIFT__SI 0x00000014 -#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT__CI__VI 0x00000019 -#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0x0000000b -#define GCK_ACLK_FUSES__AClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_ACLK_FUSES__AClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_ACLK_FUSES__AClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_ACLK_FUSES__AClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GCK_ACLK_FUSES__StartupAClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_DCLK_FUSES__DClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_DCLK_FUSES__DClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_DCLK_FUSES__DClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_DCLK_FUSES__DClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GCK_DCLK_FUSES__StartupDClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_DISPCLK_FUSES__DispClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_DISPCLK_FUSES__DispClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_DISPCLK_FUSES__DispClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_DISPCLK_FUSES__DispClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GCK_DISPCLK_FUSES__StartupDispClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_DPREFCLK_FUSES__DpRefClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_DPREFCLK_FUSES__DpRefClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_DPREFCLK_FUSES__DpRefClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_DPREFCLK_FUSES__DpRefClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GCK_DPREFCLK_FUSES__StartupDpRefClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_ECLK_FUSES__EClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_ECLK_FUSES__EClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_ECLK_FUSES__EClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_ECLK_FUSES__EClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GCK_ECLK_FUSES__StartupEClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_CLKF_UPDATE__SHIFT__CI 0x0000001e -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_CLKR_UPDATE__SHIFT__CI 0x0000001f -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_FB_DIV__SHIFT__CI__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL_2__GPUPLL_RESET_EN__SHIFT__CI 0x0000001d -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_BG_PDN__SHIFT__CI 0x00000016 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_FBCLK_SEL__SHIFT__CI__VI 0x00000018 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_ILOCK__SHIFT__CI__VI 0x00000017 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_REG_BIAS__SHIFT__CI 0x00000012 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EN__SHIFT__CI 0x00000006 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EXT_SEL__SHIFT__CI 0x00000004 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EXT__SHIFT__CI__VI 0x0000001a -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_TEST_SEL__SHIFT__CI__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SPARE_EXT__SHIFT__CI__VI 0x0000001c -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SPARE__SHIFT__CI 0x00000008 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_TEST_FRAC_BYPASS__SHIFT__CI 0x00000015 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_VCTRLADC_EN__SHIFT__CI__VI 0x00000019 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_VTOI_BIAS_CNTL__SHIFT__CI__VI 0x0000001f -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_FAST_LOCK_CNTRL__SHIFT__CI__VI 0x00000006 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_FAST_LOCK_EN__SHIFT__CI__VI 0x00000008 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_FBDIV_SSC_BYPASS__SHIFT__CI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_PFD_RESET_CNTRL__SHIFT__CI__VI 0x00000002 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_RESET_ANTI_MUX__SHIFT__CI__VI 0x00000009 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_RESET_TIMER__SHIFT__CI__VI 0x00000004 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_RISEFBVCO_EN__SHIFT__CI__VI 0x00000001 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_BYPASS_EN__SHIFT__CI 0x00000018 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_DITHEN__SHIFT__CI__VI 0x00000009 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_INIT_RESET_TIMER__SHIFT__CI 0x0000000b -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_REFCLK_DIV__SHIFT__CI__VI 0x00000003 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_RESET__SHIFT__CI 0x00000017 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_SLEEP__SHIFT__CI 0x0000001a -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_SW_DIR_CONTROL__SHIFT__CI__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_UNLOCK_CLEAR__SHIFT__CI 0x0000001b -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_VCOMODE__SHIFT__CI__VI 0x00000001 -#define GCK_GPUPLL_SPREAD_SPECTRUM_2__GPUPLL_CLKV__SHIFT__CI__VI 0x00000000 -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_BWADJ__SHIFT__CI 0x00000010 -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_CLKS__SHIFT__CI__VI 0x00000004 -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_SSEN__SHIFT__CI__VI 0x00000000 -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_SS_SPARE__SHIFT__CI 0x00000002 -#define GCK_GPUPLL_STATUS__GPUPLL_CLKF_ACK__SHIFT__CI__VI 0x00000002 -#define GCK_GPUPLL_STATUS__GPUPLL_CLKR_ACK__SHIFT__CI 0x00000003 -#define GCK_GPUPLL_STATUS__GPUPLL_CTLACK_A__SHIFT__CI 0x00000000 -#define GCK_GPUPLL_STATUS__GPUPLL_CTLACK_B__SHIFT__CI 0x00000001 -#define GCK_GPUPLL_STATUS__GPUPLL_INTRESET__SHIFT__CI__VI 0x0000000c -#define GCK_GPUPLL_STATUS__GPUPLL_OSPARE__SHIFT__CI__VI 0x00000008 -#define GCK_GPUPLL_STATUS__GPUPLL_UNLOCK_STICKY__SHIFT__CI__VI 0x00000011 -#define GCK_GPUPLL_STATUS__GPUPLL_UNLOCK__SHIFT__CI__VI 0x00000010 -#define GCK_GPUPLL_STATUS__GPUPLL_VCTRLADC__SHIFT__CI__VI 0x00000004 -#define GCK_MISC_2__miscRegisters__SHIFT__CI__VI 0x00000005 -#define GCK_MISC_FUSES__FastClkRampDis__SHIFT__CI__VI 0x00000000 -#define GCK_MISC_FUSES__WRCKDid__SHIFT__CI__VI 0x00000001 -#define GCK_MISC_FUSES__WRITE_DIS__SHIFT__CI__VI 0x0000001f -#define GCK_MISC__EnableACLKInBypass__SHIFT__CI__VI 0x00000005 -#define GCK_MISC__EnableDCLKInBypass__SHIFT__CI__VI 0x00000000 -#define GCK_MISC__EnableDISPCLKInBypass__SHIFT__CI__VI 0x00000003 -#define GCK_MISC__EnableDPREFCLKInBypass__SHIFT__CI__VI 0x00000004 -#define GCK_MISC__EnableECLKInBypass__SHIFT__CI__VI 0x00000002 -#define GCK_MISC__EnableEVCLKInBypass__SHIFT__CI__VI 0x00000007 -#define GCK_MISC__EnableSAMCLKInBypass__SHIFT__CI__VI 0x00000006 -#define GCK_MISC__EnableVCLKInBypass__SHIFT__CI__VI 0x00000001 -#define GCK_MISC__miscRegisters__SHIFT__CI 0x00000008 -#define GCK_PLL_CONTROL__BypassClocks__SHIFT__CI__VI 0x00000005 -#define GCK_PLL_CONTROL__PllBGPwrDn__SHIFT__CI__VI 0x00000001 -#define GCK_PLL_CONTROL__PllLockEn__SHIFT__CI__VI 0x00000004 -#define GCK_PLL_CONTROL__PllPwrDnReg__SHIFT__CI__VI 0x00000000 -#define GCK_PLL_CONTROL__PllReset__SHIFT__CI__VI 0x00000003 -#define GCK_PLL_CONTROL__TogglePllFbReq__SHIFT__CI__VI 0x00000006 -#define GCK_PLL_DGCK_CNTL__PLL_REFCLK_SEL__SHIFT__CI__VI 0x0000001a -#define GCK_PLL_FUSES__GckFuseProg__SHIFT__CI__VI 0x00000000 -#define GCK_PLL_FUSES__MainPllBGCal__SHIFT__CI__VI 0x00000012 -#define GCK_PLL_FUSES__MainPllBGRefAdj__SHIFT__CI__VI 0x0000000d -#define GCK_PLL_FUSES__MainPllDutyCycleAdj__SHIFT__CI__VI 0x00000016 -#define GCK_PLL_FUSES__MainPllFracDiv__SHIFT__CI__VI 0x0000001a -#define GCK_PLL_FUSES__MainPllOTAHalfGain__SHIFT__CI__VI 0x0000001e -#define GCK_PLL_FUSES__MainPllOpFreqIdMax__SHIFT__CI__VI 0x00000007 -#define GCK_PLL_FUSES__MainPllOpFreqIdStartup__SHIFT__CI__VI 0x00000001 -#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT__CI 0x00000008 -#define GCK_PLL_TEST_CNTL__TEST_COUNT__SHIFT__CI 0x00000011 -#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT__CI 0x00000010 -#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT__CI 0x00000004 -#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT__CI 0x0000000f -#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT__CI__VI 0x00000000 -#define GCK_SAMCLK_FUSES__SAMClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_SAMCLK_FUSES__SAMClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_SAMCLK_FUSES__SAMClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_SAMCLK_FUSES__SAMClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GCK_SAMCLK_FUSES__StartupSAMClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_SCLK_FUSES__MinSClkDid__SHIFT__CI__VI 0x00000012 -#define GCK_SCLK_FUSES__SClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_SCLK_FUSES__SClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_SCLK_FUSES__SClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_SCLK_FUSES__SClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GCK_SCLK_FUSES__StartupSClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define GCK_SPLL_FUSES__SPLLFreqIdMax__SHIFT__CI__VI 0x00000007 -#define GCK_SPLL_FUSES__SPLLFreqIdStartup__SHIFT__CI__VI 0x00000001 -#define GCK_SPLL_FUSES__SPllMiscFuseCtl__SHIFT__CI__VI 0x00000012 -#define GCK_SPLL_FUSES__SPllRefAdj__SHIFT__CI__VI 0x0000000d -#define GCK_SPLL_FUSES__UseSPll__SHIFT__CI__VI 0x00000000 -#define GCK_VCLK_FUSES__StartupVClkDid__SHIFT__CI__VI 0x00000000 -#define GCK_VCLK_FUSES__VClkADCA__SHIFT__CI__VI 0x00000007 -#define GCK_VCLK_FUSES__VClkDDCA__SHIFT__CI__VI 0x0000000b -#define GCK_VCLK_FUSES__VClkDiDtFloor__SHIFT__CI__VI 0x00000010 -#define GCK_VCLK_FUSES__VClkDiDtWait__SHIFT__CI__VI 0x0000000d -#define GC_PRIV_MODE__MC_PRIV_MODE__SHIFT 0x00000000 -#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT__CI__VI 0x00000010 -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT__CI__VI 0x00000018 -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT__CI__VI 0x0000000c -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT__CI__VI 0x00000014 -#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT__CI__VI 0x00000008 -#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT__CI__VI 0x00000010 -#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT__CI 0x00000001 -#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT__CI 0x00000004 -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 -#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT__CI 0x00000003 -#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 -#define GDS_ATOM_BASE__BASE__SHIFT 0x00000000 -#define GDS_ATOM_BASE__UNUSED__SHIFT 0x00000010 -#define GDS_ATOM_CNTL__AINC__SHIFT 0x00000000 -#define GDS_ATOM_CNTL__DMODE__SHIFT 0x00000008 -#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x00000006 -#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x00000000 -#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x00000001 -#define GDS_ATOM_DST__DST__SHIFT 0x00000000 -#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x00000000 -#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x00000008 -#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x00000000 -#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x00000008 -#define GDS_ATOM_OP__OP__SHIFT 0x00000000 -#define GDS_ATOM_OP__UNUSED__SHIFT 0x00000008 -#define GDS_ATOM_READ0_U__DATA__SHIFT 0x00000000 -#define GDS_ATOM_READ0__DATA__SHIFT 0x00000000 -#define GDS_ATOM_READ1_U__DATA__SHIFT 0x00000000 -#define GDS_ATOM_READ1__DATA__SHIFT 0x00000000 -#define GDS_ATOM_SIZE__SIZE__SHIFT 0x00000000 -#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x00000010 -#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x00000000 -#define GDS_ATOM_SRC0__DATA__SHIFT 0x00000000 -#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x00000000 -#define GDS_ATOM_SRC1__DATA__SHIFT 0x00000000 -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x00000004 -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x00000003 -#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x00000006 -#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005 -#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x00000000 -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x00000001 -#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x00000002 -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT__CI__VI 0x00000000 -#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x00000001 -#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003 -#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005 -#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x00000007 -#define GDS_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x00000000 -#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x00000005 -#define GDS_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define GDS_DEBUG_REG0__buff_write__SHIFT__CI__VI 0x00000011 -#define GDS_DEBUG_REG0__cstate__SHIFT__CI__VI 0x0000000d -#define GDS_DEBUG_REG0__flush_request__SHIFT__CI__VI 0x00000012 -#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT__CI__VI 0x0000000c -#define GDS_DEBUG_REG0__se0_VGT_rdreq_addr__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG0__se0_re0__SHIFT__SI 0x0000000a -#define GDS_DEBUG_REG0__se0_re1__SHIFT__SI 0x00000009 -#define GDS_DEBUG_REG0__se0_re2__SHIFT__SI 0x00000008 -#define GDS_DEBUG_REG0__se0_re3__SHIFT__SI 0x00000007 -#define GDS_DEBUG_REG0__se0_simd_id__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG0__se0_wave_fifo_empty__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG0__se0_wave_fifo_full__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG0__se0_wave_id__SHIFT__SI 0x0000000b -#define GDS_DEBUG_REG0__spare1__SHIFT 0x00000000 -#define GDS_DEBUG_REG0__spare__SHIFT__CI__VI 0x00000016 -#define GDS_DEBUG_REG0__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT__CI__VI 0x00000014 -#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT__CI__VI 0x00000015 -#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT__CI__VI 0x00000013 -#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT__CI__VI 0x00000007 -#define GDS_DEBUG_REG0__write_buff_valid__SHIFT__CI__VI 0x00000006 -#define GDS_DEBUG_REG10__se1_cmd_broadcast__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG10__se1_cmd_eog__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG10__se1_cmd_gpr_dst__SHIFT__SI 0x0000000b -#define GDS_DEBUG_REG10__se1_cmd_last_quad__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG10__se1_cmd_read_op__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG10__se1_cmd_ret_data_op__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG10__se1_cmd_wave_id__SHIFT__SI 0x00000003 -#define GDS_DEBUG_REG10__se1_launch_phase__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG10__se1_mem_data_rdy__SHIFT__SI 0x00000002 -#define GDS_DEBUG_REG10__se1_send_rddone__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG10__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG1__VGT_write_buff_valid__SHIFT__SI 0x00000006 -#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT__CI__VI 0x00000015 -#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT__CI__VI 0x00000014 -#define GDS_DEBUG_REG1__awaiting_data__SHIFT__CI__VI 0x00000013 -#define GDS_DEBUG_REG1__buff_write__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG1__buffer_invalid__SHIFT__CI__VI 0x00000017 -#define GDS_DEBUG_REG1__buffer_loaded__SHIFT__CI__VI 0x00000016 -#define GDS_DEBUG_REG1__cstate__SHIFT__SI 0x0000000d -#define GDS_DEBUG_REG1__data_ready__SHIFT__CI__VI 0x00000012 -#define GDS_DEBUG_REG1__flush_request__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG1__last_pixel_ptr__SHIFT__SI 0x0000000c -#define GDS_DEBUG_REG1__pixel_addr__SHIFT__CI__VI 0x00000002 -#define GDS_DEBUG_REG1__pixel_vld__SHIFT__CI__VI 0x00000011 -#define GDS_DEBUG_REG1__spare1__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG1__spare__SHIFT 0x00000018 -#define GDS_DEBUG_REG1__tag_hit__SHIFT__CI__VI 0x00000000 -#define GDS_DEBUG_REG1__tag_miss__SHIFT__CI__VI 0x00000001 -#define GDS_DEBUG_REG1__wbuf_fifo_empty__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG1__wbuf_fifo_full__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG1__wr_buffer_wr_complete__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG1__wr_pixel_nxt_ptr__SHIFT__SI 0x00000007 -#define GDS_DEBUG_REG2__addr_fifo_empty__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG2__addr_fifo_full__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG2__app_sel__SHIFT__CI__VI 0x00000004 -#define GDS_DEBUG_REG2__awaiting_data__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG2__buffer_invalid__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG2__buffer_loaded__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG2__cmd_write__SHIFT__CI__VI 0x00000003 -#define GDS_DEBUG_REG2__data_ready__SHIFT__SI 0x00000012 -#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT__CI__VI 0x00000001 -#define GDS_DEBUG_REG2__ds_full__SHIFT__CI__VI 0x00000000 -#define GDS_DEBUG_REG2__ord_idx_free__SHIFT__CI__VI 0x00000002 -#define GDS_DEBUG_REG2__pixel_addr__SHIFT__SI 0x00000002 -#define GDS_DEBUG_REG2__pixel_vld__SHIFT__SI 0x00000011 -#define GDS_DEBUG_REG2__req__SHIFT__CI__VI 0x00000008 -#define GDS_DEBUG_REG2__spare__SHIFT__CI__VI 0x00000017 -#define GDS_DEBUG_REG2__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG2__tag_hit__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG2__tag_miss__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT__CI__VI 0x0000000b -#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT__CI__VI 0x00000000 -#define GDS_DEBUG_REG3__pipe_stall__SHIFT__SI 0x00000003 -#define GDS_DEBUG_REG3__pipe_waddr__SHIFT__SI 0x00000004 -#define GDS_DEBUG_REG3__pipe_we__SHIFT__SI 0x0000000d -#define GDS_DEBUG_REG3__se0_ord_valid__SHIFT__SI 0x0000000e -#define GDS_DEBUG_REG3__spare1__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG3__spare__SHIFT__CI__VI 0x0000000f -#define GDS_DEBUG_REG3__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG3__wave_id_ack__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG3__wave_id_valid__SHIFT__SI 0x00000002 -#define GDS_DEBUG_REG3__wc_se_sel__SHIFT__SI 0x0000000f -#define GDS_DEBUG_REG3__wc_wave_id__SHIFT__SI 0x00000010 -#define GDS_DEBUG_REG4__cmd_write__SHIFT__CI__VI 0x00000011 -#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT__CI__VI 0x00000010 -#define GDS_DEBUG_REG4__cur_reso__SHIFT__CI__VI 0x00000003 -#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT__CI__VI 0x0000000d -#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT__CI__VI 0x0000000f -#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT__CI__VI 0x0000000c -#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT__CI__VI 0x0000000e -#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT__CI__VI 0x0000000a -#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT__CI__VI 0x0000000b -#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT__CI__VI 0x00000009 -#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT__CI__VI 0x00000013 -#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT__CI__VI 0x00000012 -#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT__CI__VI 0x00000015 -#define GDS_DEBUG_REG4__gws_busy__SHIFT__CI__VI 0x00000000 -#define GDS_DEBUG_REG4__gws_out_stall__SHIFT__CI__VI 0x00000002 -#define GDS_DEBUG_REG4__gws_req__SHIFT__CI__VI 0x00000001 -#define GDS_DEBUG_REG4__ram_gws_re__SHIFT__CI__VI 0x00000016 -#define GDS_DEBUG_REG4__ram_gws_we__SHIFT__CI__VI 0x00000017 -#define GDS_DEBUG_REG4__ram_read_busy__SHIFT__CI__VI 0x00000014 -#define GDS_DEBUG_REG4__se0_bcast_fifo_empty__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG4__se0_bcast_fifo_full__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG4__se0_bcast_first_we__SHIFT__SI 0x00000011 -#define GDS_DEBUG_REG4__se0_bcast_phase__SHIFT__SI 0x0000000d -#define GDS_DEBUG_REG4__se0_bcast_sp_id__SHIFT__SI 0x0000000f -#define GDS_DEBUG_REG4__se0_gds_cmd_ret__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG4__se0_gds_op__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG4__se0_gds_ord_append__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG4__se0_last_qpipe_active__SHIFT__SI 0x00000002 -#define GDS_DEBUG_REG4__se0_sp0_active__SHIFT__SI 0x00000006 -#define GDS_DEBUG_REG4__se0_sp1_active__SHIFT__SI 0x00000005 -#define GDS_DEBUG_REG4__se0_sp2_active__SHIFT__SI 0x00000004 -#define GDS_DEBUG_REG4__se0_sp3_active__SHIFT__SI 0x00000003 -#define GDS_DEBUG_REG4__se0_two_addr_req__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG4__se0_uav_active__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG4__se0_uav_id__SHIFT__SI 0x00000007 -#define GDS_DEBUG_REG4__se0_uav_st_ptr__SHIFT__SI 0x0000000a -#define GDS_DEBUG_REG4__spare__SHIFT 0x00000018 -#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT__CI__VI 0x00000002 -#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT__CI__VI 0x00000003 -#define GDS_DEBUG_REG5__dec_error__SHIFT__CI__VI 0x00000001 -#define GDS_DEBUG_REG5__error_ds_address__SHIFT__CI__VI 0x00000008 -#define GDS_DEBUG_REG5__se0_bcast_fifo_empty__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG5__se0_gpr_dst_q__SHIFT__SI 0x00000003 -#define GDS_DEBUG_REG5__se0_instr_fifo_empty__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG5__se0_instr_fifo_full__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG5__se0_instr_fifo_re__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG5__se0_instr_fifo_we__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG5__se0_read_line_ns__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG5__se0_wave_id_q__SHIFT__SI 0x0000000b -#define GDS_DEBUG_REG5__spare1__SHIFT__CI__VI 0x00000016 -#define GDS_DEBUG_REG5__spare__SHIFT__CI__VI 0x00000005 -#define GDS_DEBUG_REG5__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT__CI__VI 0x00000004 -#define GDS_DEBUG_REG5__write_dis__SHIFT__CI__VI 0x00000000 -#define GDS_DEBUG_REG6__counters_busy__SHIFT__CI__VI 0x00000005 -#define GDS_DEBUG_REG6__counters_enabled__SHIFT__CI__VI 0x00000001 -#define GDS_DEBUG_REG6__oa_busy__SHIFT__CI__VI 0x00000000 -#define GDS_DEBUG_REG6__se0_cmd_broadcast__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG6__se0_cmd_eog__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG6__se0_cmd_gpr_dst__SHIFT__SI 0x0000000b -#define GDS_DEBUG_REG6__se0_cmd_last_quad__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG6__se0_cmd_read_op__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG6__se0_cmd_ret_data_op__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG6__se0_cmd_wave_id__SHIFT__SI 0x00000003 -#define GDS_DEBUG_REG6__se0_launch_phase__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG6__se0_mem_data_rdy__SHIFT__SI 0x00000002 -#define GDS_DEBUG_REG6__se0_send_rddone__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG6__spare__SHIFT__CI__VI 0x00000015 -#define GDS_DEBUG_REG6__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG7__se1_VGT_rdreq_addr__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG7__se1_re0__SHIFT__SI 0x0000000a -#define GDS_DEBUG_REG7__se1_re1__SHIFT__SI 0x00000009 -#define GDS_DEBUG_REG7__se1_re2__SHIFT__SI 0x00000008 -#define GDS_DEBUG_REG7__se1_re3__SHIFT__SI 0x00000007 -#define GDS_DEBUG_REG7__se1_simd_id__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG7__se1_wave_fifo_empty__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG7__se1_wave_fifo_full__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG7__se1_wave_id__SHIFT__SI 0x0000000b -#define GDS_DEBUG_REG7__spare1__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG7__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG8__se1_bcast_fifo_empty__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG8__se1_bcast_fifo_full__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG8__se1_bcast_first_we__SHIFT__SI 0x00000011 -#define GDS_DEBUG_REG8__se1_bcast_phase__SHIFT__SI 0x0000000d -#define GDS_DEBUG_REG8__se1_bcast_sp_id__SHIFT__SI 0x0000000f -#define GDS_DEBUG_REG8__se1_gds_cmd_ret__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG8__se1_gds_op__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG8__se1_gds_ord_append__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG8__se1_last_qpipe_active__SHIFT__SI 0x00000002 -#define GDS_DEBUG_REG8__se1_sp0_active__SHIFT__SI 0x00000006 -#define GDS_DEBUG_REG8__se1_sp1_active__SHIFT__SI 0x00000005 -#define GDS_DEBUG_REG8__se1_sp2_active__SHIFT__SI 0x00000004 -#define GDS_DEBUG_REG8__se1_sp3_active__SHIFT__SI 0x00000003 -#define GDS_DEBUG_REG8__se1_two_addr_req__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG8__se1_uav_active__SHIFT__SI 0x00000001 -#define GDS_DEBUG_REG8__se1_uav_id__SHIFT__SI 0x00000007 -#define GDS_DEBUG_REG8__se1_uav_st_ptr__SHIFT__SI 0x0000000a -#define GDS_DEBUG_REG8__spare__SHIFT__SI 0x00000018 -#define GDS_DEBUG_REG9__se1_bcast_fifo_empty__SHIFT__SI 0x00000013 -#define GDS_DEBUG_REG9__se1_gpr_dst_q__SHIFT__SI 0x00000003 -#define GDS_DEBUG_REG9__se1_instr_fifo_empty__SHIFT__SI 0x00000016 -#define GDS_DEBUG_REG9__se1_instr_fifo_full__SHIFT__SI 0x00000017 -#define GDS_DEBUG_REG9__se1_instr_fifo_re__SHIFT__SI 0x00000014 -#define GDS_DEBUG_REG9__se1_instr_fifo_we__SHIFT__SI 0x00000015 -#define GDS_DEBUG_REG9__se1_read_line_ns__SHIFT__SI 0x00000000 -#define GDS_DEBUG_REG9__se1_wave_id_q__SHIFT__SI 0x0000000b -#define GDS_DEBUG_REG9__spare__SHIFT__SI 0x00000018 -#define GDS_ENHANCE2__MISC__SHIFT__CI__VI 0x00000000 -#define GDS_ENHANCE2__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT__CI__VI 0x00000010 -#define GDS_ENHANCE__CGPG_RESTORE__SHIFT__CI__VI 0x00000011 -#define GDS_ENHANCE__MISC__SHIFT 0x00000000 -#define GDS_ENHANCE__UNUSED__SHIFT__CI__VI 0x00000012 -#define GDS_ENHANCE__UNUSED__SHIFT__SI 0x00000010 -#define GDS_GRBM_SECDED_CNT__DED__SHIFT__CI 0x00000000 -#define GDS_GRBM_SECDED_CNT__DED__SHIFT__SI 0x00000010 -#define GDS_GRBM_SECDED_CNT__SEC__SHIFT__CI 0x00000010 -#define GDS_GRBM_SECDED_CNT__SEC__SHIFT__SI 0x00000000 -#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT__CI__VI 0x0000000a -#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT__CI__VI 0x0000000b -#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT__CI__VI 0x0000000c -#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT__CI__VI 0x0000000d -#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT__CI__VI 0x0000000e -#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT__CI__VI 0x0000000f -#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT__CI__VI 0x00000011 -#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT__CI__VI 0x00000012 -#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT__CI__VI 0x00000013 -#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT__CI__VI 0x00000001 -#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT__CI__VI 0x00000014 -#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT__CI__VI 0x00000015 -#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT__CI__VI 0x00000016 -#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT__CI__VI 0x00000017 -#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT__CI__VI 0x00000018 -#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT__CI__VI 0x00000019 -#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT__CI__VI 0x0000001a -#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT__CI__VI 0x0000001b -#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT__CI__VI 0x0000001c -#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT__CI__VI 0x0000001d -#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT__CI__VI 0x00000002 -#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT__CI__VI 0x0000001e -#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT__CI__VI 0x0000001f -#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT__CI__VI 0x00000003 -#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT__CI__VI 0x00000004 -#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT__CI__VI 0x00000005 -#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT__CI__VI 0x00000006 -#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT__CI__VI 0x00000007 -#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT__CI__VI 0x00000008 -#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT__CI__VI 0x00000009 -#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT__CI__VI 0x00000001 -#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT__CI__VI 0x00000002 -#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT__CI__VI 0x00000003 -#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT__CI__VI 0x00000004 -#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT__CI__VI 0x00000005 -#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT__CI__VI 0x00000006 -#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT__CI__VI 0x00000007 -#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT__CI__VI 0x00000008 -#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT__CI__VI 0x00000009 -#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT__CI__VI 0x0000000a -#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT__CI__VI 0x0000000b -#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT__CI__VI 0x0000000c -#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT__CI__VI 0x0000000d -#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT__CI__VI 0x0000000e -#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT__CI__VI 0x0000000f -#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT__CI__VI 0x00000011 -#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT__CI__VI 0x00000012 -#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT__CI__VI 0x00000013 -#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT__CI__VI 0x00000014 -#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT__CI__VI 0x00000015 -#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT__CI__VI 0x00000016 -#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT__CI__VI 0x00000017 -#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT__CI__VI 0x00000018 -#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT__CI__VI 0x00000019 -#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT__CI__VI 0x0000001a -#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT__CI__VI 0x0000001b -#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT__CI__VI 0x0000001c -#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT__CI__VI 0x0000001d -#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT__CI__VI 0x0000001e -#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT__CI__VI 0x0000001f -#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x00000000 -#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x00000006 -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT__CI__VI 0x00000008 -#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x00000001 -#define GDS_GWS_RESOURCE__DED__SHIFT 0x0000000e -#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x00000000 -#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x00000010 -#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT__CI__VI 0x0000000f -#define GDS_GWS_RESOURCE__TYPE__SHIFT 0x0000000d -#define GDS_GWS_RESOURCE__UNUSED__SHIFT__SI 0x0000000f -#define GDS_GWS_VMID0__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID0__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID10__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID10__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID11__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID11__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID12__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID12__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID13__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID13__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID14__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID14__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID15__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID15__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID1__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID1__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID2__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID2__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID3__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID3__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID4__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID4__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID5__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID5__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID6__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID6__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID7__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID7__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID8__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID8__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_GWS_VMID9__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_GWS_VMID9__SIZE__SHIFT__CI__VI 0x00000010 -#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT__CI 0x00000010 -#define GDS_OA_ADDRESS__CRAWLER__SHIFT__CI 0x00000014 -#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT__CI__VI 0x00000000 -#define GDS_OA_ADDRESS__ENABLE__SHIFT__CI__VI 0x0000001f -#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT__CI__VI 0x0000001e -#define GDS_OA_ADDRESS__UNUSED__SHIFT__CI 0x00000018 -#define GDS_OA_CGPG_RESTORE__MEID__SHIFT__CI__VI 0x00000008 -#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT__CI__VI 0x0000000c -#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT__CI 0x00000010 -#define GDS_OA_CGPG_RESTORE__VMID__SHIFT__CI__VI 0x00000000 -#define GDS_OA_CNTL__INDEX__SHIFT__CI__VI 0x00000000 -#define GDS_OA_CNTL__UNUSED__SHIFT__CI__VI 0x00000004 -#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT__CI__VI 0x00000000 -#define GDS_OA_DED__ME0_CS_DED__SHIFT__CI 0x00000002 -#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT__CI 0x00000000 -#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT__CI 0x00000001 -#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT__CI 0x00000004 -#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT__CI 0x00000005 -#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT__CI 0x00000006 -#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT__CI 0x00000007 -#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT__CI 0x00000008 -#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT__CI 0x00000009 -#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT__CI 0x0000000a -#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT__CI 0x0000000b -#define GDS_OA_DED__PIPE0_DED__SHIFT__SI 0x00000000 -#define GDS_OA_DED__PIPE1_DED__SHIFT__SI 0x00000001 -#define GDS_OA_DED__PIPE2_DED__SHIFT__SI 0x00000002 -#define GDS_OA_DED__PIPE3_DED__SHIFT__SI 0x00000003 -#define GDS_OA_DED__UNUSED0__SHIFT__CI 0x00000003 -#define GDS_OA_DED__UNUSED1__SHIFT__CI 0x0000000c -#define GDS_OA_DED__UNUSED__SHIFT__SI 0x00000004 -#define GDS_OA_INCDEC__INCDEC__SHIFT__CI__VI 0x0000001f -#define GDS_OA_INCDEC__VALUE__SHIFT__CI__VI 0x00000000 -#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT__CI__VI 0x00000002 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT__CI__VI 0x00000000 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT__CI__VI 0x00000001 -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT__CI__VI 0x00000004 -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT__CI__VI 0x00000005 -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT__CI__VI 0x00000006 -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT__CI__VI 0x00000007 -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT__CI__VI 0x00000008 -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT__CI__VI 0x00000009 -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT__CI__VI 0x0000000a -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT__CI__VI 0x0000000b -#define GDS_OA_RESET_MASK__UNUSED0__SHIFT__CI__VI 0x00000003 -#define GDS_OA_RESET_MASK__UNUSED1__SHIFT__CI__VI 0x0000000c -#define GDS_OA_RESET__PIPE_ID__SHIFT__CI__VI 0x00000008 -#define GDS_OA_RESET__RESET__SHIFT__CI__VI 0x00000000 -#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID0__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID0__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID10__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID10__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID11__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID11__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID12__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID12__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID13__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID13__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID14__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID14__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID15__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID15__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID1__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID1__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID2__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID2__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID3__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID3__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID4__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID4__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID5__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID5__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID6__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID6__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID7__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID7__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID8__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID8__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_OA_VMID9__MASK__SHIFT__CI__VI 0x00000000 -#define GDS_OA_VMID9__UNUSED__SHIFT__CI__VI 0x00000010 -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT__CI__VI 0x00000000 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT__CI__VI 0x0000000a -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT__CI__VI 0x00000010 -#define GDS_PROTECTION_FAULT__CU_ID__SHIFT__CI__VI 0x00000006 -#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT__CI__VI 0x00000001 -#define GDS_PROTECTION_FAULT__GRBM__SHIFT__CI__VI 0x00000002 -#define GDS_PROTECTION_FAULT__SH_ID__SHIFT__CI__VI 0x00000003 -#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT__CI__VI 0x0000000a -#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT__CI__VI 0x0000000c -#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x00000000 -#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x00000000 -#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x00000000 -#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x00000000 -#define GDS_RD_DATA__READ_DATA__SHIFT 0x00000000 -#define GDS_SECDED_CNT__DED__SHIFT__CI 0x00000000 -#define GDS_SECDED_CNT__DED__SHIFT__SI 0x00000010 -#define GDS_SECDED_CNT__SEC__SHIFT__CI 0x00000010 -#define GDS_SECDED_CNT__SEC__SHIFT__SI 0x00000000 -#define GDS_VMID0_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID0_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID10_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID10_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID11_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID11_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID12_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID12_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID13_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID13_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID14_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID14_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID15_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID15_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID1_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID1_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID2_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID2_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID3_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID3_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID4_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID4_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID5_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID5_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID6_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID6_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID7_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID7_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID8_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID8_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID9_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define GDS_VMID9_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT__CI__VI 0x00000010 -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT__CI__VI 0x00000001 -#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT__CI__VI 0x00000004 -#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT__CI__VI 0x00000002 -#define GDS_VM_PROTECTION_FAULT__OA__SHIFT__CI__VI 0x00000003 -#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT__CI__VI 0x00000008 -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x00000000 -#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x00000000 -#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x00000000 -#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x00000000 -#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x00000000 -#define GENENB__BLK_IO_BASE__SHIFT__SI 0x00000000 -#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT__CI__VI 0x00000013 -#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x00000017 -#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x00000000 -#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT__CI__VI 0x0000000e -#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT__CI__VI 0x0000000f -#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT__CI__VI 0x00000011 -#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT__CI__VI 0x00000010 -#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT__CI__VI 0x00000008 -#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT__CI__VI 0x00000009 -#define GENERAL_PWRMGT__MC_ALLOW_STOP__SHIFT__SI 0x0000001e -#define GENERAL_PWRMGT__SPARE11__SHIFT 0x0000000b -#define GENERAL_PWRMGT__SPARE18__SHIFT 0x00000012 -#define GENERAL_PWRMGT__SPARE19__SHIFT__SI 0x00000013 -#define GENERAL_PWRMGT__SPARE20__SHIFT__SI 0x00000014 -#define GENERAL_PWRMGT__SPARE27__SHIFT__CI__VI 0x0000001b -#define GENERAL_PWRMGT__SPARE__SHIFT__CI__VI 0x0000001c -#define GENERAL_PWRMGT__SPARE__SHIFT__SI 0x0000001b -#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x00000001 -#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x00000006 -#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x00000002 -#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x00000003 -#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0x0000000a -#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT__SI 0x0000001f -#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT__SI 0x00000000 -#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT__SI 0x00000002 -#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT__SI 0x00000001 -#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT__SI 0x00000000 -#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT__SI 0x00000008 -#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT__SI 0x0000001f -#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT__SI 0x00000010 -#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT__SI 0x00000001 -#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT__SI 0x00000000 -#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT__SI 0x00000002 -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT__SI 0x00000002 -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT__SI 0x00000001 -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT__SI 0x00000000 -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT__SI 0x00000006 -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT__SI 0x00000005 -#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT__SI 0x00000004 -#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT__SI 0x00000000 -#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT__SI 0x00000008 -#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT__SI 0x00000007 -#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT__SI 0x00000000 -#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT__SI 0x00000001 -#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT__SI 0x00000018 -#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT__SI 0x00000004 -#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT__SI 0x00000010 -#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT__SI 0x00000000 -#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT__SI 0x00000005 -#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT__SI 0x00000004 -#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT__SI 0x0000000a -#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT__SI 0x00000000 -#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT__SI 0x00000009 -#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT__SI 0x00000006 -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT__SI 0x00000009 -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT__SI 0x00000010 -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT__SI 0x00000000 -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT__SI 0x0000000c -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT__SI 0x00000008 -#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT__SI 0x0000000d -#define GENFC_RD__VSYNC_SEL_R__SHIFT__SI 0x00000003 -#define GENFC_WT__VSYNC_SEL_W__SHIFT__SI 0x00000003 -#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT__SI 0x00000000 -#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT__SI 0x00000005 -#define GENMO_RD__VGA_CKSEL__SHIFT__SI 0x00000002 -#define GENMO_RD__VGA_HSYNC_POL__SHIFT__SI 0x00000006 -#define GENMO_RD__VGA_RAM_EN__SHIFT__SI 0x00000001 -#define GENMO_RD__VGA_VSYNC_POL__SHIFT__SI 0x00000007 -#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT__SI 0x00000000 -#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT__SI 0x00000005 -#define GENMO_WT__VGA_CKSEL__SHIFT__SI 0x00000002 -#define GENMO_WT__VGA_HSYNC_POL__SHIFT__SI 0x00000006 -#define GENMO_WT__VGA_RAM_EN__SHIFT__SI 0x00000001 -#define GENMO_WT__VGA_VSYNC_POL__SHIFT__SI 0x00000007 -#define GENS0__CRT_INTR__SHIFT__SI 0x00000007 -#define GENS0__SENSE_SWITCH__SHIFT__SI 0x00000004 -#define GENS1__NO_DISPLAY__SHIFT__SI 0x00000000 -#define GENS1__PIXEL_READ_BACK__SHIFT__SI 0x00000004 -#define GENS1__VGA_VSTATUS__SHIFT__SI 0x00000003 -#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT__CI__VI 0x00000010 -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT__CI__VI 0x00000000 -#define GFX_PIPE_CONTROL__RESERVED__SHIFT__CI__VI 0x0000000d -#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT__CI 0x00000000 -#define GFX_RLC_CONTROL__RLC_REQ_ACK__SHIFT__SI 0x00000004 -#define GFX_RLC_CONTROL__RLC_REQ_TYPE__SHIFT__SI 0x00000000 -#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT__SI 0x00000003 -#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT__SI 0x00000008 -#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT__SI 0x0000000c -#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT__SI 0x00000001 -#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT__SI 0x00000000 -#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT__SI 0x00000008 -#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT__SI 0x00000000 -#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT__SI 0x00000001 -#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT__SI 0x00000001 -#define GMCON_DEBUG__GFX_CLEAR__SHIFT__CI__VI 0x00000001 -#define GMCON_DEBUG__GFX_STALL__SHIFT__CI__VI 0x00000000 -#define GMCON_DEBUG__MISC_FLAGS__SHIFT__CI 0x00000002 -#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT__CI__VI 0x00000000 -#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT__CI__VI 0x00000001 -#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT__CI__VI 0x00000002 -#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT__CI__VI 0x00000003 -#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT__CI__VI 0x00000004 -#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT__CI 0x00000000 -#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT__CI 0x00000003 -#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT__CI__VI 0x0000000b -#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT__CI__VI 0x0000001e -#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT__CI__VI 0x0000001d -#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT__CI 0x00000011 -#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT__CI__VI 0x00000006 -#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT__CI__VI 0x0000001f -#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT__CI__VI 0x00000000 -#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT__CI 0x00000006 -#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT__CI 0x00000019 -#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT__CI 0x0000001a -#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT__CI 0x0000000c -#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT__CI 0x00000018 -#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT__CI__VI 0x0000001c -#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT__CI__VI 0x0000001b -#define GMCON_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT__CI__VI 0x00000000 -#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT__CI__VI 0x0000000a -#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT__CI__VI 0x0000000b -#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT__CI__VI 0x0000000c -#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT__CI__VI 0x00000019 -#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT__CI__VI 0x0000001a -#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT__CI__VI 0x0000001f -#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT__CI__VI 0x00000011 -#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT__CI__VI 0x00000016 -#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT__CI__VI 0x00000015 -#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT__CI__VI 0x00000018 -#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT__CI__VI 0x00000017 -#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT__CI__VI 0x00000013 -#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT__CI__VI 0x00000010 -#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT__CI__VI 0x0000001c -#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT__CI__VI 0x00000018 -#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT__CI__VI 0x00000000 -#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT__CI__VI 0x0000001a -#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT__CI__VI 0x0000000c -#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT__CI__VI 0x00000012 -#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT__CI 0x00000018 -#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT__CI__VI 0x00000006 -#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT__CI__VI 0x0000000c -#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT__CI__VI 0x00000000 -#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT__CI__VI 0x00000000 -#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT__CI__VI 0x00000000 -#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT__CI__VI 0x00000000 -#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT__CI__VI 0x0000000a -#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT__CI__VI 0x0000000b -#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT__CI__VI 0x00000008 -#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT__CI__VI 0x00000009 -#define GMCON_PGFSM_CONFIG__READ__SHIFT__CI__VI 0x0000000d -#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT__CI__VI 0x0000001c -#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT__CI__VI 0x0000000e -#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define GMCON_PGFSM_CONFIG__WRITE__SHIFT__CI__VI 0x0000000c -#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT__CI__VI 0x00000018 -#define GMCON_PGFSM_READ__READ_VALUE__SHIFT__CI__VI 0x00000000 -#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT__CI__VI 0x0000001c -#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT__CI__VI 0x00000000 -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT__CI__VI 0x0000000c -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT__CI__VI 0x00000016 -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT__CI__VI 0x00000002 -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT__CI__VI 0x00000001 -#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT__CI__VI 0x00000000 -#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT__CI__VI 0x00000000 -#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT__CI__VI 0x00000000 -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT__CI__VI 0x00000000 -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT__CI__VI 0x00000010 -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT__CI__VI 0x00000000 -#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT__CI__VI 0x00000010 -#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT__CI__VI 0x00000000 -#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT__CI__VI 0x00000010 -#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT__CI__VI 0x00000000 -#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT__CI__VI 0x00000010 -#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT__CI__VI 0x00000000 -#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT__CI__VI 0x00000010 -#define GPIOPAD_A__GPIO_A__SHIFT 0x00000000 -#define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000 -#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005 -#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x00000006 -#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x00000000 -#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000 -#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f -#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000 -#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008 -#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009 -#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f -#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000 -#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f -#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000 -#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f -#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000 -#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f -#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000 -#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008 -#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009 -#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000 -#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x00000000 -#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x00000000 -#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x00000004 -#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000 -#define GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_0__SHIFT__CI__VI 0x00000000 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_1__SHIFT__CI__VI 0x00000001 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_2__SHIFT__CI__VI 0x00000002 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_3__SHIFT__CI__VI 0x00000003 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_4__SHIFT__CI__VI 0x00000004 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_5__SHIFT__CI__VI 0x00000005 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_6__SHIFT__CI__VI 0x00000006 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_7__SHIFT__CI__VI 0x00000007 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_8__SHIFT__CI__VI 0x00000008 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_9__SHIFT__CI__VI 0x00000009 -#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT__CI__VI 0x00000000 -#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT__CI__VI 0x00000001 -#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT__CI__VI 0x00000002 -#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT__CI__VI 0x00000003 -#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT__CI__VI 0x00000004 -#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT__CI__VI 0x00000005 -#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT__CI__VI 0x00000006 -#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT__CI__VI 0x00000007 -#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT__CI__VI 0x00000008 -#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT__CI__VI 0x00000009 -#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT__CI__VI 0x0000000a -#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT__CI__VI 0x0000000b -#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT__CI__VI 0x00000000 -#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT__CI__VI 0x00000001 -#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT__CI__VI 0x00000002 -#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT__CI__VI 0x00000003 -#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT__CI__VI 0x00000004 -#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT__CI__VI 0x00000005 -#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT__CI__VI 0x00000006 -#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT__CI__VI 0x00000007 -#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT__CI__VI 0x00000008 -#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT__CI__VI 0x00000009 -#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT__CI__VI 0x0000000a -#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT__CI__VI 0x0000000b -#define GPU_HDP_FLUSH_DONE__CP0__SHIFT__CI__VI 0x00000000 -#define GPU_HDP_FLUSH_DONE__CP1__SHIFT__CI__VI 0x00000001 -#define GPU_HDP_FLUSH_DONE__CP2__SHIFT__CI__VI 0x00000002 -#define GPU_HDP_FLUSH_DONE__CP3__SHIFT__CI__VI 0x00000003 -#define GPU_HDP_FLUSH_DONE__CP4__SHIFT__CI__VI 0x00000004 -#define GPU_HDP_FLUSH_DONE__CP5__SHIFT__CI__VI 0x00000005 -#define GPU_HDP_FLUSH_DONE__CP6__SHIFT__CI__VI 0x00000006 -#define GPU_HDP_FLUSH_DONE__CP7__SHIFT__CI__VI 0x00000007 -#define GPU_HDP_FLUSH_DONE__CP8__SHIFT__CI__VI 0x00000008 -#define GPU_HDP_FLUSH_DONE__CP9__SHIFT__CI__VI 0x00000009 -#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT__CI__VI 0x0000000a -#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT__CI__VI 0x0000000b -#define GPU_HDP_FLUSH_REQ__CP0__SHIFT__CI__VI 0x00000000 -#define GPU_HDP_FLUSH_REQ__CP1__SHIFT__CI__VI 0x00000001 -#define GPU_HDP_FLUSH_REQ__CP2__SHIFT__CI__VI 0x00000002 -#define GPU_HDP_FLUSH_REQ__CP3__SHIFT__CI__VI 0x00000003 -#define GPU_HDP_FLUSH_REQ__CP4__SHIFT__CI__VI 0x00000004 -#define GPU_HDP_FLUSH_REQ__CP5__SHIFT__CI__VI 0x00000005 -#define GPU_HDP_FLUSH_REQ__CP6__SHIFT__CI__VI 0x00000006 -#define GPU_HDP_FLUSH_REQ__CP7__SHIFT__CI__VI 0x00000007 -#define GPU_HDP_FLUSH_REQ__CP8__SHIFT__CI__VI 0x00000008 -#define GPU_HDP_FLUSH_REQ__CP9__SHIFT__CI__VI 0x00000009 -#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT__CI__VI 0x0000000a -#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT__CI__VI 0x0000000b -#define GRA00__GRPH_SET_RESET0__SHIFT__SI 0x00000000 -#define GRA00__GRPH_SET_RESET1__SHIFT__SI 0x00000001 -#define GRA00__GRPH_SET_RESET2__SHIFT__SI 0x00000002 -#define GRA00__GRPH_SET_RESET3__SHIFT__SI 0x00000003 -#define GRA01__GRPH_SET_RESET_ENA0__SHIFT__SI 0x00000000 -#define GRA01__GRPH_SET_RESET_ENA1__SHIFT__SI 0x00000001 -#define GRA01__GRPH_SET_RESET_ENA2__SHIFT__SI 0x00000002 -#define GRA01__GRPH_SET_RESET_ENA3__SHIFT__SI 0x00000003 -#define GRA02__GRPH_CCOMP__SHIFT__SI 0x00000000 -#define GRA03__GRPH_FN_SEL__SHIFT__SI 0x00000003 -#define GRA03__GRPH_ROTATE__SHIFT__SI 0x00000000 -#define GRA04__GRPH_RMAP__SHIFT__SI 0x00000000 -#define GRA05__CGA_ODDEVEN__SHIFT__SI 0x00000004 -#define GRA05__GRPH_OES__SHIFT__SI 0x00000005 -#define GRA05__GRPH_PACK__SHIFT__SI 0x00000006 -#define GRA05__GRPH_READ1__SHIFT__SI 0x00000003 -#define GRA05__GRPH_WRITE_MODE__SHIFT__SI 0x00000000 -#define GRA06__GRPH_ADRSEL__SHIFT__SI 0x00000002 -#define GRA06__GRPH_GRAPHICS__SHIFT__SI 0x00000000 -#define GRA06__GRPH_ODDEVEN__SHIFT__SI 0x00000001 -#define GRA07__GRPH_XCARE0__SHIFT__SI 0x00000000 -#define GRA07__GRPH_XCARE1__SHIFT__SI 0x00000001 -#define GRA07__GRPH_XCARE2__SHIFT__SI 0x00000002 -#define GRA07__GRPH_XCARE3__SHIFT__SI 0x00000003 -#define GRA08__GRPH_BMSK__SHIFT__SI 0x00000000 -#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 -#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 -#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 -#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 -#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x00000000 -#define GRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT__CI__VI 0x00000000 -#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT__CI__VI 0x00000001 -#define GRBM_DEBUG_SNAPSHOT__CP_RDY__SHIFT__SI 0x00000003 -#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT__CI__VI 0x00000005 -#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT__SI 0x00000009 -#define GRBM_DEBUG_SNAPSHOT__IA_RING0_RDY__SHIFT__SI 0x00000006 -#define GRBM_DEBUG_SNAPSHOT__IA_RING1_RDY__SHIFT__SI 0x00000007 -#define GRBM_DEBUG_SNAPSHOT__IA_RING2_RDY__SHIFT__SI 0x00000008 -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT__CI__VI 0x00000006 -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT__CI__VI 0x0000000e -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT__CI__VI 0x00000007 -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT__CI__VI 0x0000000f -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING0_RDY0__SHIFT__SI 0x0000000a -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING0_RDY1__SHIFT__SI 0x0000000c -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING1_RDY1__SHIFT__SI 0x0000000d -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_RING2_RDY1__SHIFT__SI 0x0000000e -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT__CI__VI 0x00000008 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT__CI__VI 0x00000010 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT__CI__VI 0x00000009 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT__CI__VI 0x00000011 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING0_RDY0__SHIFT__SI 0x0000000b -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING0_RDY1__SHIFT__SI 0x0000000f -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING1_RDY1__SHIFT__SI 0x00000010 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_RING2_RDY1__SHIFT__SI 0x00000011 -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT__CI__VI 0x0000000a -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT__CI__VI 0x00000012 -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT__CI__VI 0x0000000b -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT__CI__VI 0x00000013 -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT__CI__VI 0x0000000c -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT__CI__VI 0x00000014 -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT__CI__VI 0x0000000d -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT__CI__VI 0x00000015 -#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT__CI__VI 0x00000002 -#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT__SI 0x00000001 -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT__CI__VI 0x00000003 -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT__CI__VI 0x00000004 -#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000006 -#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x0000000c -#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x00000008 -#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x00000005 -#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000001 -#define GRBM_DEBUG__OVERRIDE_WU__SHIFT__SI 0x00000000 -#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000007 -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x0000001e -#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x00000000 -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x0000001f -#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x00000010 -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x0000001d -#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x00000008 -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x00000013 -#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x00000000 -#define GRBM_NOWHERE__DATA__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000001c -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000001c -#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT__SI__CI 0x00000000 -#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT__SI__CI 0x00000004 -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT__CI__VI 0x00000013 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT__CI__VI 0x00000014 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT__CI__VI 0x00000015 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT__CI__VI 0x00000016 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT__CI__VI 0x00000017 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT__CI__VI 0x00000018 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT__CI__VI 0x00000019 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT__CI__VI 0x0000001a -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT__CI__VI 0x0000001b -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT__CI__VI 0x0000001c -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT__CI__VI 0x0000001d -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT__CI__VI 0x0000001e -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT__CI__VI 0x0000001f -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT__CI__VI 0x00000012 -#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT__CI__VI 0x00000011 -#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 -#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f -#define GRBM_READ_ERROR__READ_MEID__SHIFT__CI__VI 0x00000016 -#define GRBM_READ_ERROR__READ_PIPEID__SHIFT__CI__VI 0x00000014 -#define GRBM_READ_ERROR__READ_REQUESTER_GDS_DMA__SHIFT__SI 0x00000017 -#define GRBM_READ_ERROR__READ_REQUESTER_RING0_CF__SHIFT__SI 0x0000001a -#define GRBM_READ_ERROR__READ_REQUESTER_RING0_PF__SHIFT__SI 0x0000001b -#define GRBM_READ_ERROR__READ_REQUESTER_RING1__SHIFT__SI 0x00000019 -#define GRBM_READ_ERROR__READ_REQUESTER_RING2__SHIFT__SI 0x00000018 -#define GRBM_READ_ERROR__READ_REQUESTER_RLC__SHIFT__SI 0x00000016 -#define GRBM_READ_ERROR__READ_REQUESTER_SRBM__SHIFT__SI 0x0000001c -#define GRBM_READ_ERROR__READ_REQUESTER_WU_POLL__SHIFT__SI 0x0000001e -#define GRBM_READ_ERROR__READ_RINGID__SHIFT__SI 0x00000014 -#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 -#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 -#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 -#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 -#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 -#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 -#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 -#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000015 -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000012 -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000b -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000011 -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000a -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000014 -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000010 -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000f -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000d -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000c -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000013 -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000015 -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000012 -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000b -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000011 -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000a -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000014 -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000010 -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000f -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000d -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x0000000c -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT__CI__VI 0x00000013 -#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000006 -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 -#define GRBM_SOFT_RESET__SOFT_RESET_BCI__SHIFT__SI 0x00000007 -#define GRBM_SOFT_RESET__SOFT_RESET_CB__SHIFT__SI 0x00000001 -#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT__CI__VI 0x00000012 -#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT__CI__VI 0x00000011 -#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT__CI__VI 0x00000013 -#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 -#define GRBM_SOFT_RESET__SOFT_RESET_DB__SHIFT__SI 0x00000003 -#define GRBM_SOFT_RESET__SOFT_RESET_GDS__SHIFT__SI 0x00000004 -#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT__CI__VI 0x00000010 -#define GRBM_SOFT_RESET__SOFT_RESET_IA__SHIFT__SI 0x0000000f -#define GRBM_SOFT_RESET__SOFT_RESET_PA__SHIFT__SI 0x00000005 -#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x00000002 -#define GRBM_SOFT_RESET__SOFT_RESET_SC__SHIFT__SI 0x00000006 -#define GRBM_SOFT_RESET__SOFT_RESET_SPI__SHIFT__SI 0x00000008 -#define GRBM_SOFT_RESET__SOFT_RESET_SX__SHIFT__SI 0x0000000a -#define GRBM_SOFT_RESET__SOFT_RESET_TA__SHIFT__SI 0x0000000c -#define GRBM_SOFT_RESET__SOFT_RESET_TC__SHIFT__SI 0x0000000b -#define GRBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT__SI 0x0000000e -#define GRBM_STATUS2__CPC_BUSY__SHIFT__CI__VI 0x0000001d -#define GRBM_STATUS2__CPF_BUSY__SHIFT__CI__VI 0x0000001c -#define GRBM_STATUS2__CPG_BUSY__SHIFT__CI__VI 0x0000001e -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT__CI__VI 0x00000004 -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT__CI__VI 0x00000000 -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT__CI__VI 0x00000005 -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT__CI__VI 0x00000006 -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT__CI__VI 0x00000007 -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT__CI__VI 0x00000008 -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT__CI__VI 0x00000009 -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT__CI__VI 0x0000000a -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT__CI__VI 0x0000000b -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT__CI__VI 0x0000000c -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT__CI__VI 0x0000000d -#define GRBM_STATUS2__RLC_BUSY__SHIFT__CI__VI 0x00000018 -#define GRBM_STATUS2__RLC_BUSY__SHIFT__SI 0x00000008 -#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT__CI__VI 0x0000000e -#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT__SI 0x00000000 -#define GRBM_STATUS2__TC_BUSY__SHIFT__CI__VI 0x00000019 -#define GRBM_STATUS2__TC_BUSY__SHIFT__SI 0x00000009 -#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x0000001f -#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x00000002 -#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x00000001 -#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x0000001b -#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x0000001f -#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x00000002 -#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x00000001 -#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x0000001b -#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT__CI__VI 0x00000016 -#define GRBM_STATUS_SE2__CB_BUSY__SHIFT__CI__VI 0x0000001f -#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT__CI__VI 0x00000002 -#define GRBM_STATUS_SE2__DB_BUSY__SHIFT__CI__VI 0x0000001e -#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT__CI__VI 0x00000001 -#define GRBM_STATUS_SE2__PA_BUSY__SHIFT__CI__VI 0x00000018 -#define GRBM_STATUS_SE2__SC_BUSY__SHIFT__CI__VI 0x0000001d -#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT__CI__VI 0x0000001b -#define GRBM_STATUS_SE2__SX_BUSY__SHIFT__CI__VI 0x0000001a -#define GRBM_STATUS_SE2__TA_BUSY__SHIFT__CI__VI 0x00000019 -#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT__CI__VI 0x00000017 -#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT__CI__VI 0x00000016 -#define GRBM_STATUS_SE3__CB_BUSY__SHIFT__CI__VI 0x0000001f -#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT__CI__VI 0x00000002 -#define GRBM_STATUS_SE3__DB_BUSY__SHIFT__CI__VI 0x0000001e -#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT__CI__VI 0x00000001 -#define GRBM_STATUS_SE3__PA_BUSY__SHIFT__CI__VI 0x00000018 -#define GRBM_STATUS_SE3__SC_BUSY__SHIFT__CI__VI 0x0000001d -#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT__CI__VI 0x0000001b -#define GRBM_STATUS_SE3__SX_BUSY__SHIFT__CI__VI 0x0000001a -#define GRBM_STATUS_SE3__TA_BUSY__SHIFT__CI__VI 0x00000019 -#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT__CI__VI 0x00000017 -#define GRBM_STATUS__BCI_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS__CB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS__CB_CLEAN__SHIFT 0x0000000d -#define GRBM_STATUS__CF_RQ_PENDING__SHIFT__SI 0x00000007 -#define GRBM_STATUS__CMDFIFO_AVAIL__SHIFT__SI 0x00000000 -#define GRBM_STATUS__CP_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x0000001c -#define GRBM_STATUS__DB_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS__DB_CLEAN__SHIFT 0x0000000c -#define GRBM_STATUS__GDS_BUSY__SHIFT 0x0000000f -#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x00000009 -#define GRBM_STATUS__GRBM_EE_BUSY__SHIFT__SI 0x0000000a -#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f -#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x00000012 -#define GRBM_STATUS__IA_BUSY__SHIFT 0x00000013 -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT__CI__VI 0x00000007 -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT__CI__VI 0x00000000 -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT__CI__VI 0x00000008 -#define GRBM_STATUS__PA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS__PF_RQ_PENDING__SHIFT__SI 0x00000008 -#define GRBM_STATUS__RING1_RQ_PENDING__SHIFT__SI 0x00000006 -#define GRBM_STATUS__RING2_RQ_PENDING__SHIFT__SI 0x00000004 -#define GRBM_STATUS__SC_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS__SPI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x00000005 -#define GRBM_STATUS__SX_BUSY__SHIFT 0x00000014 -#define GRBM_STATUS__TA_BUSY__SHIFT 0x0000000e -#define GRBM_STATUS__VGT_BUSY__SHIFT 0x00000011 -#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT__CI__VI 0x00000010 -#define GRBM_STATUS__WD_BUSY__SHIFT__CI__VI 0x00000015 -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x00000000 -#define GRPH8_DATA__GRPH_DATA__SHIFT__SI 0x00000000 -#define GRPH8_IDX__GRPH_IDX__SHIFT__SI 0x00000000 -#define GRPH_ALPHA__GRPH_ALPHA__SHIFT__SI 0x00000000 -#define GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__GRPH_COLOR_MATRIX_TRANSFORMATION_EN__SHIFT__SI \ - 0x00000000 -#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT__SI 0x00000006 -#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT__SI 0x00000000 -#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT__SI 0x00000008 -#define GRPH_CONTROL__GRPH_16BIT_ALPHA_MODE__SHIFT__SI 0x00000018 -#define GRPH_CONTROL__GRPH_16BIT_FIXED_ALPHA_RANGE__SHIFT__SI 0x0000001c -#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT__SI 0x00000010 -#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT__SI 0x00000014 -#define GRPH_CONTROL__GRPH_DEPTH__SHIFT__SI 0x00000000 -#define GRPH_CONTROL__GRPH_FORMAT__SHIFT__SI 0x00000008 -#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT__SI 0x00000011 -#define GRPH_CONTROL__GRPH_TILE_COMPACT_EN__SHIFT__SI 0x0000000c -#define GRPH_CONTROL__GRPH_Z__SHIFT__SI 0x00000004 -#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT__SI 0x00000008 -#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT__SI 0x00000000 -#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT__SI 0x00000004 -#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT__SI 0x00000009 -#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT__SI 0x00000008 -#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT__SI 0x00000000 -#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT__SI 0x00000004 -#define GRPH_ENABLE__GRPH_ENABLE__SHIFT__SI 0x00000000 -#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT__SI 0x00000000 -#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT__SI 0x00000000 -#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT__SI 0x00000008 -#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT__SI 0x00000008 -#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT__SI 0x00000000 -#define GRPH_KEY_RANGE_ALPHA__GRPH_KEY_ALPHA_HIGH__SHIFT__SI 0x00000010 -#define GRPH_KEY_RANGE_ALPHA__GRPH_KEY_ALPHA_LOW__SHIFT__SI 0x00000000 -#define GRPH_KEY_RANGE_BLUE__GRPH_KEY_BLUE_HIGH__SHIFT__SI 0x00000010 -#define GRPH_KEY_RANGE_BLUE__GRPH_KEY_BLUE_LOW__SHIFT__SI 0x00000000 -#define GRPH_KEY_RANGE_GREEN__GRPH_KEY_GREEN_HIGH__SHIFT__SI 0x00000010 -#define GRPH_KEY_RANGE_GREEN__GRPH_KEY_GREEN_LOW__SHIFT__SI 0x00000000 -#define GRPH_KEY_RANGE_RED__GRPH_KEY_RED_HIGH__SHIFT__SI 0x00000010 -#define GRPH_KEY_RANGE_RED__GRPH_KEY_RED_LOW__SHIFT__SI 0x00000000 -#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT__SI 0x00000010 -#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT__SI 0x00000008 -#define GRPH_PITCH__GRPH_PITCH__SHIFT__SI 0x00000000 -#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT__SI 0x00000000 -#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT__SI 0x00000000 -#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT__SI 0x00000008 -#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT__SI \ - 0x00000000 -#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT__SI 0x00000000 -#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT__SI 0x00000008 -#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT__SI 0x00000000 -#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT__SI 0x00000008 -#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT__SI 0x00000000 -#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT__SI 0x00000000 -#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT__SI 0x0000000a -#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT__SI 0x00000008 -#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT__SI 0x00000000 -#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT__SI 0x00000006 -#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT__SI 0x00000004 -#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT__SI 0x00000018 -#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT__SI 0x00000001 -#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT__SI 0x0000001c -#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT__SI 0x00000002 -#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT__SI 0x00000003 -#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT__SI 0x00000010 -#define GRPH_X_END__GRPH_X_END__SHIFT__SI 0x00000000 -#define GRPH_X_START__GRPH_X_START__SHIFT__SI 0x00000000 -#define GRPH_Y_END__GRPH_Y_END__SHIFT__SI 0x00000000 -#define GRPH_Y_START__GRPH_Y_START__SHIFT__SI 0x00000000 -#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 -#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 -#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 -#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 -#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 -#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 -#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 -#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 -#define HDCP_CONTROL__HDCP_ENABLE__SHIFT__SI 0x00000000 -#define HDCP_CONTROL__HDCP_ENCRYPTION_ENABLE__SHIFT__SI 0x00000008 -#define HDCP_CONTROL__HDCP_SHORT_OESS_ON__SHIFT__SI 0x00000010 -#define HDCP_DEBUG_CONTROL__HDCP_ADVANCE_CIPHER_ON_AVMUTE__SHIFT__SI 0x00000012 -#define HDCP_DEBUG_CONTROL__HDCP_BLANK_ALL_PACKETS_ON_ENC_ENB__SHIFT__SI 0x00000007 -#define HDCP_DEBUG_CONTROL__HDCP_DEBUG_RNG_CIPHER__SHIFT__SI 0x00000002 -#define HDCP_DEBUG_CONTROL__HDCP_DISABLE_RI_CHECK_IN_ADVANCE_CIPHER_ENC_DIS__SHIFT__SI 0x00000005 -#define HDCP_DEBUG_CONTROL__HDCP_EESS_WHEN_AVMUTE__SHIFT__SI 0x00000013 -#define HDCP_DEBUG_CONTROL__HDCP_EESS_WHEN_UNAUTHENTICATED__SHIFT__SI 0x00000015 -#define HDCP_DEBUG_CONTROL__HDCP_FRAMECOUNT_START_VAL__SHIFT__SI 0x00000018 -#define HDCP_DEBUG_CONTROL__HDCP_FRAMES_TO_PJ_CHECK__SHIFT__SI 0x00000010 -#define HDCP_DEBUG_CONTROL__HDCP_FRAMES_TO_RI_CHECK__SHIFT__SI 0x0000000c -#define HDCP_DEBUG_CONTROL__HDCP_FRAME_COUNT_SELECT__SHIFT__SI 0x00000001 -#define HDCP_DEBUG_CONTROL__HDCP_IGNORED_PJ_CHECK_TIMEOUT__SHIFT__SI 0x00000017 -#define HDCP_DEBUG_CONTROL__HDCP_IGNORED_RI_CHECK_TIMEOUT__SHIFT__SI 0x00000016 -#define HDCP_DEBUG_CONTROL__HDCP_IGNORE_HPD_DISCONNECT__SHIFT__SI 0x00000004 -#define HDCP_DEBUG_CONTROL__HDCP_MAX_PJ_MISMATCH_COUNT_RESET__SHIFT__SI 0x0000000b -#define HDCP_DEBUG_CONTROL__HDCP_MAX_PJ_MISMATCH_COUNT__SHIFT__SI 0x00000008 -#define HDCP_DEBUG_CONTROL__HDCP_NO_DEFERRED_ENC_DIS__SHIFT__SI 0x0000000e -#define HDCP_DEBUG_CONTROL__HDCP_RAISE_URG_2_FRAMES_EARLY__SHIFT__SI 0x00000006 -#define HDCP_DEBUG_CONTROL__HDCP_SW_I2C_XFER_REQ_TIMEOUT_DISABLE__SHIFT__SI 0x00000014 -#define HDCP_DEBUG_CONTROL__HDCP_SYNC_KEY_READ__SHIFT__SI 0x00000003 -#define HDCP_DEBUG_CONTROL__HDCP_USER_DEFINED_AN__SHIFT__SI 0x00000000 -#define HDCP_DEBUG__HDCP_DEBUG__SHIFT__SI 0x00000000 -#define HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK__SHIFT__SI 0x00000001 -#define HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE__SHIFT__SI 0x00000000 -#define HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT__SHIFT__SI 0x00000008 -#define HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE__SHIFT__SI 0x00000000 -#define HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET__SHIFT__SI 0x00000002 -#define HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK__SHIFT__SI 0x00000000 -#define HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT__SHIFT__SI 0x00000014 -#define HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY__SHIFT__SI 0x00000018 -#define HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE__SHIFT__SI 0x00000001 -#define HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE__SHIFT__SI 0x00000008 -#define HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ__SHIFT__SI 0x00000018 -#define HDCP_I2C_STATUS__HDCP_I2C_ABORTED__SHIFT__SI 0x0000000c -#define HDCP_I2C_STATUS__HDCP_I2C_FAILED__SHIFT__SI 0x00000010 -#define HDCP_I2C_STATUS__HDCP_I2C_NACK0__SHIFT__SI 0x0000000e -#define HDCP_I2C_STATUS__HDCP_I2C_NACK1__SHIFT__SI 0x0000000f -#define HDCP_I2C_STATUS__HDCP_I2C_RETRIES__SHIFT__SI 0x00000014 -#define HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT__SHIFT__SI 0x0000000d -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE__SHIFT__SI 0x0000000a -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED__SHIFT__SI 0x00000002 -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE__SHIFT__SI 0x00000006 -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG__SHIFT__SI 0x00000005 -#define HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ__SHIFT__SI 0x00000004 -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK__SHIFT__SI 0x00000005 -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK__SHIFT__SI 0x00000007 -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT__SHIFT__SI 0x00000004 -#define HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK__SHIFT__SI 0x00000006 -#define HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK__SHIFT__SI 0x00000001 -#define HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT__SHIFT__SI 0x00000000 -#define HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK__SHIFT__SI 0x00000002 -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK__SHIFT__SI 0x0000000d -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT__SHIFT__SI 0x0000000c -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK__SHIFT__SI 0x0000000e -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK__SHIFT__SI 0x00000009 -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT__SHIFT__SI 0x00000008 -#define HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK__SHIFT__SI 0x0000000a -#define HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY__SHIFT__SI 0x00000008 -#define HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY__SHIFT__SI 0x00000009 -#define HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO__SHIFT__SI 0x00000004 -#define HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL__SHIFT__SI 0x00000002 -#define HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS__SHIFT__SI 0x00000000 -#define HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE__SHIFT__SI 0x0000001c -#define HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT__SHIFT__SI 0x00000010 -#define HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE__SHIFT__SI 0x00000018 -#define HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES__SHIFT__SI 0x0000000c -#define HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES__SHIFT__SI 0x00000014 -#define HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY__SHIFT__SI 0x00000008 -#define HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY__SHIFT__SI 0x00000009 -#define HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO__SHIFT__SI 0x00000004 -#define HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL__SHIFT__SI 0x00000002 -#define HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS__SHIFT__SI 0x00000000 -#define HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE__SHIFT__SI 0x0000001c -#define HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT__SHIFT__SI 0x00000010 -#define HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE__SHIFT__SI 0x00000018 -#define HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES__SHIFT__SI 0x0000000c -#define HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS__SHIFT__SI 0x00000008 -#define HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO__SHIFT__SI 0x00000008 -#define HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO__SHIFT__SI 0x00000008 -#define HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1__SHIFT__SI 0x00000000 -#define HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2__SHIFT__SI 0x00000000 -#define HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE__SHIFT__SI 0x00000000 -#define HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE__SHIFT__SI 0x00000001 -#define HDCP_SHA_CONTROL__HDCP_DEBUG_EN__SHIFT__SI 0x0000001f -#define HDCP_SHA_CONTROL__HDCP_SHA_DBG_EN__SHIFT__SI 0x00000008 -#define HDCP_SHA_CONTROL__HDCP_SHA_DBG_NO_APPEND_BYTES__SHIFT__SI 0x0000000c -#define HDCP_SHA_CONTROL__HDCP_SHA_RESET__SHIFT__SI 0x00000000 -#define HDCP_SHA_CONTROL__HDCP_SHA_SELECT__SHIFT__SI 0x00000004 -#define HDCP_SHA_DATA__HDCP_SHA_DATA_DONE__SHIFT__SI 0x00000000 -#define HDCP_SHA_DATA__HDCP_SHA_DATA__SHIFT__SI 0x00000010 -#define HDCP_SHA_DBG_M0_0__HDCP_SHA_DBG_M0_0__SHIFT__SI 0x00000000 -#define HDCP_SHA_DBG_M0_1__HDCP_SHA_DBG_M0_1__SHIFT__SI 0x00000000 -#define HDCP_SHA_STATUS__HDCP_SHA_BLOCK_DONE__SHIFT__SI 0x00000000 -#define HDCP_SHA_STATUS__HDCP_SHA_BUSY__SHIFT__SI 0x00000014 -#define HDCP_SHA_STATUS__HDCP_SHA_COMP_DONE__SHIFT__SI 0x00000004 -#define HDCP_SHA_STATUS__HDCP_SHA_DBG_V_MATCHES__SHIFT__SI 0x00000018 -#define HDCP_SHA_STATUS__HDCP_SHA_M0_INVALID__SHIFT__SI 0x00000010 -#define HDCP_SHA_STATUS__HDCP_SHA_OVERFLOW__SHIFT__SI 0x00000008 -#define HDCP_SHA_STATUS__HDCP_SHA_WRITE_ERROR__SHIFT__SI 0x0000000c -#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT__SI 0x0000000c -#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT__SI 0x00000000 -#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT__SI 0x0000000c -#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT__SI 0x00000000 -#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT__SI 0x0000000c -#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT__SI 0x00000000 -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT__SI 0x0000001f -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT__SI 0x0000000c -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT__SI 0x00000001 -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT__SI 0x00000010 -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT__SI 0x00000004 -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT__SI 0x00000000 -#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT__SI 0x00000008 -#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT__SI 0x0000000c -#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT__SI 0x00000000 -#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT__SI 0x00000004 -#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT__SI 0x00000010 -#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT__SI 0x00000008 -#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT__SI 0x0000001c -#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT__SI 0x00000018 -#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT__SI 0x00000008 -#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT__SI 0x00000009 -#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT__SI 0x00000000 -#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT__SI 0x00000004 -#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT__SI 0x00000004 -#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT__SI 0x00000002 -#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT__SI 0x00000000 -#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT__SI 0x0000000c -#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT__SI 0x00000008 -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC0_CONT__SHIFT__SI 0x00000001 -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC0_LINE__SHIFT__SI 0x00000010 -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC0_SEND__SHIFT__SI 0x00000000 -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC1_CONT__SHIFT__SI 0x00000005 -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC1_LINE__SHIFT__SI 0x00000018 -#define HDMI_GENERIC_PACKET_CONTROL__HDMI_GENERIC1_SEND__SHIFT__SI 0x00000004 -#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT__SI 0x00000005 -#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT__SI 0x00000004 -#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT__SI 0x00000001 -#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT__SI 0x00000000 -#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT__SI 0x00000009 -#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT__SI 0x00000008 -#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT__SI 0x00000008 -#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT__SI 0x00000000 -#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT__SI 0x00000010 -#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT__SI 0x00000000 -#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT__SI 0x00000010 -#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT__SI 0x0000001b -#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT__SI 0x00000014 -#define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT__SI 0x00000018 -#define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT__SI 0x0000000c -#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT__SI 0x00000005 -#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT__SI 0x00000004 -#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT__SI 0x00000009 -#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT__SI 0x00000010 -#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT__SI 0x00000008 -#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT__SI 0x00000000 -#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x00000000 -#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x00000000 -#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x0000001d -#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x00000000 -#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x00000016 -#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x00000017 -#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x0000001f -#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000003 -#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0x0000000b -#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x00000018 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x00000015 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013 -#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x0000001e -#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x00000009 -#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x00000000 -#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x00000000 -#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x00000000 -#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x00000005 -#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0x0000000f -#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x00000001 -#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x00000000 -#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x00000001 -#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x00000000 -#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x00000008 -#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x00000000 -#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x00000000 -#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x00000000 -#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x00000003 -#define HDP_SURFACE0_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE0_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE0_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE0_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE0_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE0_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE0_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE0_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE0_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE0_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE0_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE0_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE0_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE10_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE10_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE10_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE10_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE10_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE10_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE10_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE10_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE10_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE10_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE10_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE10_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE10_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE11_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE11_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE11_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE11_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE11_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE11_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE11_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE11_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE11_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE11_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE11_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE11_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE11_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE12_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE12_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE12_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE12_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE12_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE12_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE12_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE12_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE12_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE12_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE12_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE12_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE12_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE13_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE13_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE13_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE13_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE13_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE13_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE13_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE13_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE13_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE13_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE13_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE13_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE13_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE14_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE14_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE14_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE14_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE14_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE14_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE14_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE14_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE14_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE14_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE14_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE14_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE14_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE15_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE15_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE15_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE15_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE15_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE15_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE15_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE15_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE15_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE15_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE15_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE15_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE15_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE16_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE16_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE16_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE16_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE16_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE16_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE16_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE16_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE16_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE16_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE16_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE16_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE16_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE17_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE17_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE17_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE17_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE17_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE17_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE17_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE17_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE17_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE17_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE17_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE17_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE17_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE18_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE18_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE18_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE18_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE18_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE18_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE18_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE18_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE18_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE18_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE18_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE18_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE18_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE19_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE19_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE19_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE19_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE19_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE19_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE19_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE19_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE19_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE19_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE19_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE19_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE19_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE1_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE1_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE1_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE1_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE1_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE1_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE1_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE1_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE1_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE1_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE1_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE1_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE1_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE20_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE20_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE20_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE20_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE20_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE20_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE20_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE20_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE20_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE20_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE20_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE20_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE20_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE21_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE21_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE21_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE21_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE21_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE21_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE21_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE21_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE21_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE21_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE21_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE21_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE21_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE22_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE22_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE22_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE22_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE22_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE22_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE22_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE22_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE22_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE22_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE22_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE22_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE22_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE23_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE23_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE23_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE23_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE23_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE23_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE23_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE23_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE23_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE23_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE23_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE23_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE23_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE24_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE24_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE24_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE24_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE24_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE24_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE24_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE24_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE24_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE24_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE24_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE24_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE24_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE25_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE25_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE25_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE25_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE25_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE25_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE25_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE25_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE25_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE25_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE25_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE25_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE25_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE26_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE26_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE26_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE26_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE26_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE26_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE26_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE26_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE26_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE26_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE26_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE26_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE26_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE27_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE27_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE27_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE27_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE27_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE27_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE27_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE27_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE27_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE27_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE27_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE27_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE27_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE28_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE28_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE28_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE28_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE28_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE28_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE28_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE28_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE28_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE28_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE28_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE28_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE28_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE29_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE29_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE29_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE29_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE29_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE29_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE29_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE29_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE29_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE29_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE29_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE29_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE29_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE2_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE2_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE2_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE2_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE2_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE2_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE2_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE2_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE2_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE2_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE2_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE2_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE2_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE30_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE30_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE30_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE30_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE30_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE30_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE30_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE30_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE30_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE30_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE30_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE30_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE30_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE31_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE31_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE31_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE31_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE31_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE31_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE31_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE31_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE31_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE31_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE31_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE31_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE31_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE3_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE3_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE3_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE3_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE3_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE3_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE3_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE3_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE3_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE3_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE3_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE3_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE3_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE4_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE4_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE4_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE4_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE4_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE4_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE4_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE4_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE4_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE4_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE4_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE4_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE4_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE5_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE5_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE5_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE5_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE5_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE5_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE5_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE5_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE5_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE5_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE5_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE5_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE5_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE6_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE6_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE6_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE6_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE6_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE6_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE6_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE6_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE6_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE6_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE6_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE6_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE6_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE7_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE7_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE7_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE7_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE7_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE7_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE7_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE7_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE7_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE7_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE7_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE7_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE7_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE8_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE8_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE8_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE8_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE8_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE8_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE8_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE8_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE8_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE8_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE8_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE8_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE8_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE9_BASE__SURF_BASE__SHIFT 0x00000000 -#define HDP_SURFACE9_INFO__SURF_ADDR_TYPE__SHIFT 0x00000000 -#define HDP_SURFACE9_INFO__SURF_ARRAY_MODE__SHIFT 0x00000001 -#define HDP_SURFACE9_INFO__SURF_ENDIAN__SHIFT 0x00000005 -#define HDP_SURFACE9_INFO__SURF_PIXEL_SIZE__SHIFT 0x00000007 -#define HDP_SURFACE9_INFO__SURF_PRIV__SHIFT 0x0000000f -#define HDP_SURFACE9_INFO__SURF_SAMPLE_NUM__SHIFT 0x0000000a -#define HDP_SURFACE9_INFO__SURF_SAMPLE_SIZE__SHIFT 0x0000000d -#define HDP_SURFACE9_INFO__SURF_TILE_COMPACT__SHIFT 0x00000010 -#define HDP_SURFACE9_LOWER_BOUND__SURF_LOWER__SHIFT 0x00000000 -#define HDP_SURFACE9_SIZE__SURF_PITCH_TILE_MAX__SHIFT 0x00000000 -#define HDP_SURFACE9_SIZE__SURF_SLICE_TILE_MAX__SHIFT 0x0000000a -#define HDP_SURFACE9_UPPER_BOUND__SURF_UPPER__SHIFT 0x00000000 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x00000000 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF10_READ_FLAG_CLR__SHIFT 0x0000000a -#define HDP_SURFACE_READ_FLAGS_CLR__SURF11_READ_FLAG_CLR__SHIFT 0x0000000b -#define HDP_SURFACE_READ_FLAGS_CLR__SURF12_READ_FLAG_CLR__SHIFT 0x0000000c -#define HDP_SURFACE_READ_FLAGS_CLR__SURF13_READ_FLAG_CLR__SHIFT 0x0000000d -#define HDP_SURFACE_READ_FLAGS_CLR__SURF14_READ_FLAG_CLR__SHIFT 0x0000000e -#define HDP_SURFACE_READ_FLAGS_CLR__SURF15_READ_FLAG_CLR__SHIFT 0x0000000f -#define HDP_SURFACE_READ_FLAGS_CLR__SURF16_READ_FLAG_CLR__SHIFT 0x00000010 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF17_READ_FLAG_CLR__SHIFT 0x00000011 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF18_READ_FLAG_CLR__SHIFT 0x00000012 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF19_READ_FLAG_CLR__SHIFT 0x00000013 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x00000001 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF20_READ_FLAG_CLR__SHIFT 0x00000014 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF21_READ_FLAG_CLR__SHIFT 0x00000015 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF22_READ_FLAG_CLR__SHIFT 0x00000016 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF23_READ_FLAG_CLR__SHIFT 0x00000017 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF24_READ_FLAG_CLR__SHIFT 0x00000018 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF25_READ_FLAG_CLR__SHIFT 0x00000019 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF26_READ_FLAG_CLR__SHIFT 0x0000001a -#define HDP_SURFACE_READ_FLAGS_CLR__SURF27_READ_FLAG_CLR__SHIFT 0x0000001b -#define HDP_SURFACE_READ_FLAGS_CLR__SURF28_READ_FLAG_CLR__SHIFT 0x0000001c -#define HDP_SURFACE_READ_FLAGS_CLR__SURF29_READ_FLAG_CLR__SHIFT 0x0000001d -#define HDP_SURFACE_READ_FLAGS_CLR__SURF2_READ_FLAG_CLR__SHIFT 0x00000002 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF30_READ_FLAG_CLR__SHIFT 0x0000001e -#define HDP_SURFACE_READ_FLAGS_CLR__SURF31_READ_FLAG_CLR__SHIFT 0x0000001f -#define HDP_SURFACE_READ_FLAGS_CLR__SURF3_READ_FLAG_CLR__SHIFT 0x00000003 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF4_READ_FLAG_CLR__SHIFT 0x00000004 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF5_READ_FLAG_CLR__SHIFT 0x00000005 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF6_READ_FLAG_CLR__SHIFT 0x00000006 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF7_READ_FLAG_CLR__SHIFT 0x00000007 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF8_READ_FLAG_CLR__SHIFT 0x00000008 -#define HDP_SURFACE_READ_FLAGS_CLR__SURF9_READ_FLAG_CLR__SHIFT 0x00000009 -#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x00000000 -#define HDP_SURFACE_READ_FLAGS__SURF10_READ_FLAG__SHIFT 0x0000000a -#define HDP_SURFACE_READ_FLAGS__SURF11_READ_FLAG__SHIFT 0x0000000b -#define HDP_SURFACE_READ_FLAGS__SURF12_READ_FLAG__SHIFT 0x0000000c -#define HDP_SURFACE_READ_FLAGS__SURF13_READ_FLAG__SHIFT 0x0000000d -#define HDP_SURFACE_READ_FLAGS__SURF14_READ_FLAG__SHIFT 0x0000000e -#define HDP_SURFACE_READ_FLAGS__SURF15_READ_FLAG__SHIFT 0x0000000f -#define HDP_SURFACE_READ_FLAGS__SURF16_READ_FLAG__SHIFT 0x00000010 -#define HDP_SURFACE_READ_FLAGS__SURF17_READ_FLAG__SHIFT 0x00000011 -#define HDP_SURFACE_READ_FLAGS__SURF18_READ_FLAG__SHIFT 0x00000012 -#define HDP_SURFACE_READ_FLAGS__SURF19_READ_FLAG__SHIFT 0x00000013 -#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x00000001 -#define HDP_SURFACE_READ_FLAGS__SURF20_READ_FLAG__SHIFT 0x00000014 -#define HDP_SURFACE_READ_FLAGS__SURF21_READ_FLAG__SHIFT 0x00000015 -#define HDP_SURFACE_READ_FLAGS__SURF22_READ_FLAG__SHIFT 0x00000016 -#define HDP_SURFACE_READ_FLAGS__SURF23_READ_FLAG__SHIFT 0x00000017 -#define HDP_SURFACE_READ_FLAGS__SURF24_READ_FLAG__SHIFT 0x00000018 -#define HDP_SURFACE_READ_FLAGS__SURF25_READ_FLAG__SHIFT 0x00000019 -#define HDP_SURFACE_READ_FLAGS__SURF26_READ_FLAG__SHIFT 0x0000001a -#define HDP_SURFACE_READ_FLAGS__SURF27_READ_FLAG__SHIFT 0x0000001b -#define HDP_SURFACE_READ_FLAGS__SURF28_READ_FLAG__SHIFT 0x0000001c -#define HDP_SURFACE_READ_FLAGS__SURF29_READ_FLAG__SHIFT 0x0000001d -#define HDP_SURFACE_READ_FLAGS__SURF2_READ_FLAG__SHIFT 0x00000002 -#define HDP_SURFACE_READ_FLAGS__SURF30_READ_FLAG__SHIFT 0x0000001e -#define HDP_SURFACE_READ_FLAGS__SURF31_READ_FLAG__SHIFT 0x0000001f -#define HDP_SURFACE_READ_FLAGS__SURF3_READ_FLAG__SHIFT 0x00000003 -#define HDP_SURFACE_READ_FLAGS__SURF4_READ_FLAG__SHIFT 0x00000004 -#define HDP_SURFACE_READ_FLAGS__SURF5_READ_FLAG__SHIFT 0x00000005 -#define HDP_SURFACE_READ_FLAGS__SURF6_READ_FLAG__SHIFT 0x00000006 -#define HDP_SURFACE_READ_FLAGS__SURF7_READ_FLAG__SHIFT 0x00000007 -#define HDP_SURFACE_READ_FLAGS__SURF8_READ_FLAG__SHIFT 0x00000008 -#define HDP_SURFACE_READ_FLAGS__SURF9_READ_FLAG__SHIFT 0x00000009 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x00000000 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF10_WRITE_FLAG_CLR__SHIFT 0x0000000a -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF11_WRITE_FLAG_CLR__SHIFT 0x0000000b -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF12_WRITE_FLAG_CLR__SHIFT 0x0000000c -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF13_WRITE_FLAG_CLR__SHIFT 0x0000000d -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF14_WRITE_FLAG_CLR__SHIFT 0x0000000e -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF15_WRITE_FLAG_CLR__SHIFT 0x0000000f -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF16_WRITE_FLAG_CLR__SHIFT 0x00000010 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF17_WRITE_FLAG_CLR__SHIFT 0x00000011 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF18_WRITE_FLAG_CLR__SHIFT 0x00000012 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF19_WRITE_FLAG_CLR__SHIFT 0x00000013 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x00000001 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF20_WRITE_FLAG_CLR__SHIFT 0x00000014 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF21_WRITE_FLAG_CLR__SHIFT 0x00000015 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF22_WRITE_FLAG_CLR__SHIFT 0x00000016 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF23_WRITE_FLAG_CLR__SHIFT 0x00000017 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF24_WRITE_FLAG_CLR__SHIFT 0x00000018 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF25_WRITE_FLAG_CLR__SHIFT 0x00000019 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF26_WRITE_FLAG_CLR__SHIFT 0x0000001a -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF27_WRITE_FLAG_CLR__SHIFT 0x0000001b -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF28_WRITE_FLAG_CLR__SHIFT 0x0000001c -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF29_WRITE_FLAG_CLR__SHIFT 0x0000001d -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF2_WRITE_FLAG_CLR__SHIFT 0x00000002 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF30_WRITE_FLAG_CLR__SHIFT 0x0000001e -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF31_WRITE_FLAG_CLR__SHIFT 0x0000001f -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF3_WRITE_FLAG_CLR__SHIFT 0x00000003 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF4_WRITE_FLAG_CLR__SHIFT 0x00000004 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF5_WRITE_FLAG_CLR__SHIFT 0x00000005 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF6_WRITE_FLAG_CLR__SHIFT 0x00000006 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF7_WRITE_FLAG_CLR__SHIFT 0x00000007 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF8_WRITE_FLAG_CLR__SHIFT 0x00000008 -#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF9_WRITE_FLAG_CLR__SHIFT 0x00000009 -#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x00000000 -#define HDP_SURFACE_WRITE_FLAGS__SURF10_WRITE_FLAG__SHIFT 0x0000000a -#define HDP_SURFACE_WRITE_FLAGS__SURF11_WRITE_FLAG__SHIFT 0x0000000b -#define HDP_SURFACE_WRITE_FLAGS__SURF12_WRITE_FLAG__SHIFT 0x0000000c -#define HDP_SURFACE_WRITE_FLAGS__SURF13_WRITE_FLAG__SHIFT 0x0000000d -#define HDP_SURFACE_WRITE_FLAGS__SURF14_WRITE_FLAG__SHIFT 0x0000000e -#define HDP_SURFACE_WRITE_FLAGS__SURF15_WRITE_FLAG__SHIFT 0x0000000f -#define HDP_SURFACE_WRITE_FLAGS__SURF16_WRITE_FLAG__SHIFT 0x00000010 -#define HDP_SURFACE_WRITE_FLAGS__SURF17_WRITE_FLAG__SHIFT 0x00000011 -#define HDP_SURFACE_WRITE_FLAGS__SURF18_WRITE_FLAG__SHIFT 0x00000012 -#define HDP_SURFACE_WRITE_FLAGS__SURF19_WRITE_FLAG__SHIFT 0x00000013 -#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x00000001 -#define HDP_SURFACE_WRITE_FLAGS__SURF20_WRITE_FLAG__SHIFT 0x00000014 -#define HDP_SURFACE_WRITE_FLAGS__SURF21_WRITE_FLAG__SHIFT 0x00000015 -#define HDP_SURFACE_WRITE_FLAGS__SURF22_WRITE_FLAG__SHIFT 0x00000016 -#define HDP_SURFACE_WRITE_FLAGS__SURF23_WRITE_FLAG__SHIFT 0x00000017 -#define HDP_SURFACE_WRITE_FLAGS__SURF24_WRITE_FLAG__SHIFT 0x00000018 -#define HDP_SURFACE_WRITE_FLAGS__SURF25_WRITE_FLAG__SHIFT 0x00000019 -#define HDP_SURFACE_WRITE_FLAGS__SURF26_WRITE_FLAG__SHIFT 0x0000001a -#define HDP_SURFACE_WRITE_FLAGS__SURF27_WRITE_FLAG__SHIFT 0x0000001b -#define HDP_SURFACE_WRITE_FLAGS__SURF28_WRITE_FLAG__SHIFT 0x0000001c -#define HDP_SURFACE_WRITE_FLAGS__SURF29_WRITE_FLAG__SHIFT 0x0000001d -#define HDP_SURFACE_WRITE_FLAGS__SURF2_WRITE_FLAG__SHIFT 0x00000002 -#define HDP_SURFACE_WRITE_FLAGS__SURF30_WRITE_FLAG__SHIFT 0x0000001e -#define HDP_SURFACE_WRITE_FLAGS__SURF31_WRITE_FLAG__SHIFT 0x0000001f -#define HDP_SURFACE_WRITE_FLAGS__SURF3_WRITE_FLAG__SHIFT 0x00000003 -#define HDP_SURFACE_WRITE_FLAGS__SURF4_WRITE_FLAG__SHIFT 0x00000004 -#define HDP_SURFACE_WRITE_FLAGS__SURF5_WRITE_FLAG__SHIFT 0x00000005 -#define HDP_SURFACE_WRITE_FLAGS__SURF6_WRITE_FLAG__SHIFT 0x00000006 -#define HDP_SURFACE_WRITE_FLAGS__SURF7_WRITE_FLAG__SHIFT 0x00000007 -#define HDP_SURFACE_WRITE_FLAGS__SURF8_WRITE_FLAG__SHIFT 0x00000008 -#define HDP_SURFACE_WRITE_FLAGS__SURF9_WRITE_FLAG__SHIFT 0x00000009 -#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x00000000 -#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0x0000000b -#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x00000004 -#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x00000006 -#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x00000001 -#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x00000008 -#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0x0000000e -#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x00000000 -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x00000000 -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x00000004 -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0x0000000c -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x0000001e -#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x0000001f -#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x00000000 -#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008 -#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x00000010 -#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x00000018 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x00000000 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x00000014 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x00000010 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x00000012 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x00000000 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x00000008 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x00000004 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x00000013 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x00000014 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x00000010 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x00000011 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0x0000000b -#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x00000010 -#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x00000000 -#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x00000010 -#define HDP_XDP_DBG_DATA__STS__SHIFT 0x00000000 -#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x00000010 -#define HDP_XDP_DBG_MASK__STS__SHIFT 0x00000000 -#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x00000000 -#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x00000000 -#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x00000000 -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0x0000000c -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000000 -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000006 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x00000000 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x00000001 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x00000003 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x00000000 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x00000001 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x00000003 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x00000014 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x00000004 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x00000005 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x00000007 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0x0000000e -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x00000008 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x00000000 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 -#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x00000010 -#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x00000014 -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x00000000 -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x00000004 -#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x00000001 -#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x00000000 -#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x00000001 -#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x00000000 -#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x00000001 -#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x00000000 -#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x00000001 -#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x00000000 -#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x00000001 -#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x00000000 -#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x00000001 -#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x00000000 -#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x00000001 -#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x00000000 -#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x00000000 -#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x00000003 -#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x00000000 -#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 -#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x00000000 -#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x00000006 -#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x00000007 -#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x00000000 -#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x00000010 -#define HD_BACKPORCH_DUR__HD_BP_DUR_PBPR__SHIFT__SI 0x00000010 -#define HD_BACKPORCH_DUR__HD_BP_DUR_Y__SHIFT__SI 0x00000000 -#define HD_CGMS_TIMING__HD_CGMS_EN__SHIFT__SI 0x0000001f -#define HD_CGMS_TIMING__HD_CGMS_RB_EN__SHIFT__SI 0x0000001d -#define HD_CGMS_TIMING__HD_CGMS_VEND__SHIFT__SI 0x00000010 -#define HD_CGMS_TIMING__HD_CGMS_WIDTH__SHIFT__SI 0x00000000 -#define HD_CGMS_TIMING__HD_CGMS_YG_EN__SHIFT__SI 0x0000001e -#define HD_EMBEDDED_SYNC_CNTL__HD_DEBUG0__SHIFT__SI 0x00000010 -#define HD_EMBEDDED_SYNC_CNTL__HD_EMBED_SYNC_EN_PB_B__SHIFT__SI 0x00000001 -#define HD_EMBEDDED_SYNC_CNTL__HD_EMBED_SYNC_EN_PR_R__SHIFT__SI 0x00000002 -#define HD_EMBEDDED_SYNC_CNTL__HD_EMBED_SYNC_EN_Y_G__SHIFT__SI 0x00000000 -#define HD_EMBEDDED_SYNC_CNTL__HD_TRILEVEL_SYNC_EN__SHIFT__SI 0x00000003 -#define HD_INCR__HD_INCR_PB_B_PR_R__SHIFT__SI 0x00000010 -#define HD_INCR__HD_INCR_Y_G__SHIFT__SI 0x00000000 -#define HD_POS_SYNC_LEVEL__HD_POS_SYNC_LEVEL_PB_B_PR_R__SHIFT__SI 0x00000010 -#define HD_POS_SYNC_LEVEL__HD_POS_SYNC_LEVEL_Y_G__SHIFT__SI 0x00000000 -#define HD_SERATION_DUR__HD_SER_DUR_PBPR__SHIFT__SI 0x00000010 -#define HD_SERATION_DUR__HD_SER_DUR_Y__SHIFT__SI 0x00000000 -#define HD_TRILEVEL_DUR__HD_TRILEVEL_DUR_PBPR__SHIFT__SI 0x00000010 -#define HD_TRILEVEL_DUR__HD_TRILEVEL_DUR_Y__SHIFT__SI 0x00000000 -#define HEADER__DEVICE_TYPE__SHIFT 0x00000007 -#define HEADER__HEADER_TYPE__SHIFT 0x00000000 -#define HFS_SEED0__RESERVED__SHIFT 0x00000000 -#define HFS_SEED1__RESERVED__SHIFT 0x00000000 -#define HFS_SEED2__RESERVED__SHIFT 0x00000000 -#define HFS_SEED3__RESERVED__SHIFT 0x00000000 -#define HOST_BUSNUM__HOST_ID__SHIFT 0x00000000 -#define HPD_DEBUG__DOUT_HPD_DEBUG__SHIFT__SI 0x00000000 -#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f -#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x00000010 -#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x00000011 -#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x00000012 -#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x00000013 -#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x00000014 -#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x00000015 -#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x00000016 -#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x00000017 -#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x00000018 -#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x00000019 -#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x0000001a -#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x0000001b -#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x0000001c -#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x0000001d -#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x0000001e -#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x0000001f -#define I2C_CNTL_0__I2C_ABORT__SHIFT__SI 0x0000000b -#define I2C_CNTL_0__I2C_DONE__SHIFT__SI 0x00000000 -#define I2C_CNTL_0__I2C_DRIVE_EN__SHIFT__SI 0x00000006 -#define I2C_CNTL_0__I2C_DRIVE_SEL__SHIFT__SI 0x00000007 -#define I2C_CNTL_0__I2C_GO__SHIFT__SI 0x0000000c -#define I2C_CNTL_0__I2C_HALT__SHIFT__SI 0x00000002 -#define I2C_CNTL_0__I2C_NACK__SHIFT__SI 0x00000001 -#define I2C_CNTL_0__I2C_PRESCALE__SHIFT__SI 0x00000010 -#define I2C_CNTL_0__I2C_RECEIVE__SHIFT__SI 0x0000000a -#define I2C_CNTL_0__I2C_SOFT_RST__SHIFT__SI 0x00000005 -#define I2C_CNTL_0__I2C_START__SHIFT__SI 0x00000008 -#define I2C_CNTL_0__I2C_STOP__SHIFT__SI 0x00000009 -#define I2C_CNTL_1__I2C_ADDR_COUNT__SHIFT__SI 0x00000004 -#define I2C_CNTL_1__I2C_DATA_COUNT__SHIFT__SI 0x00000000 -#define I2C_CNTL_1__I2C_EN__SHIFT__SI 0x00000011 -#define I2C_CNTL_1__I2C_INTRA_BYTE_DELAY__SHIFT__SI 0x00000008 -#define I2C_CNTL_1__I2C_SEL__SHIFT__SI 0x00000010 -#define I2C_CNTL_1__I2C_TIME_LIMIT__SHIFT__SI 0x00000018 -#define I2C_DATA__I2C_DATA__SHIFT__SI 0x00000000 -#define I2C_DEBUG_BUS__DOUT_HPD_DEBUG_EXTN__SHIFT__SI 0x00000000 -#define I2C_DEBUG_BUS__DOUT_I2C_DEBUG_BUS__SHIFT__SI 0x00000018 -#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x00000004 -#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x00000000 -#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x00000001 -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x00000002 -#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x00000003 -#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x00000000 -#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x00000006 -#define IA_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define IA_DEBUG_REG0__SPARE0__SHIFT__CI__VI 0x00000004 -#define IA_DEBUG_REG0__SPARE1__SHIFT__CI__VI 0x00000009 -#define IA_DEBUG_REG0__SPARE2__SHIFT__CI__VI 0x0000000e -#define IA_DEBUG_REG0__SPARE3__SHIFT__CI__VI 0x0000001a -#define IA_DEBUG_REG0__SPARE3__SHIFT__SI 0x00000014 -#define IA_DEBUG_REG0__SPARE4__SHIFT__CI__VI 0x0000001b -#define IA_DEBUG_REG0__SPARE5__SHIFT__CI__VI 0x0000001e -#define IA_DEBUG_REG0__SPARE6__SHIFT__CI__VI 0x0000001f -#define IA_DEBUG_REG0__adc_busy_r0__SHIFT__SI 0x00000017 -#define IA_DEBUG_REG0__adc_busy_r1__SHIFT__SI 0x00000016 -#define IA_DEBUG_REG0__adc_busy_r2__SHIFT__SI 0x00000015 -#define IA_DEBUG_REG0__core_clk_busy__SHIFT__CI__VI 0x00000019 -#define IA_DEBUG_REG0__core_clk_busy__SHIFT__SI 0x0000001a -#define IA_DEBUG_REG0__dma_busy__SHIFT 0x00000006 -#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT__CI__VI 0x0000000c -#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0x0000000a -#define IA_DEBUG_REG0__dma_req_busy__SHIFT__CI__VI 0x00000005 -#define IA_DEBUG_REG0__dma_request_busy__SHIFT__SI 0x00000005 -#define IA_DEBUG_REG0__grp_busy__SHIFT 0x00000008 -#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT__CI__VI 0x0000000d -#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0x0000000b -#define IA_DEBUG_REG0__grp_rbiu_di_read__SHIFT__SI 0x00000013 -#define IA_DEBUG_REG0__ia_busy__SHIFT 0x00000002 -#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x00000000 -#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x00000003 -#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x00000001 -#define IA_DEBUG_REG0__input_clk_busy__SHIFT__SI 0x00000019 -#define IA_DEBUG_REG0__inval_clk_busy__SHIFT__SI 0x0000001b -#define IA_DEBUG_REG0__invld_busy__SHIFT__SI 0x00000009 -#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x00000007 -#define IA_DEBUG_REG0__rbiu_busy__SHIFT__SI 0x00000004 -#define IA_DEBUG_REG0__rbiu_di_fifo_empty__SHIFT__SI 0x0000000e -#define IA_DEBUG_REG0__rbiu_di_fifo_full__SHIFT__SI 0x0000000f -#define IA_DEBUG_REG0__rbiu_dr_fifo_empty__SHIFT__SI 0x00000010 -#define IA_DEBUG_REG0__rbiu_dr_fifo_full__SHIFT__SI 0x00000011 -#define IA_DEBUG_REG0__rbiu_grp_di_valid__SHIFT__SI 0x00000012 -#define IA_DEBUG_REG0__rbiu_im_fifo_empty__SHIFT__SI 0x0000000c -#define IA_DEBUG_REG0__rbiu_im_fifo_full__SHIFT__SI 0x0000000d -#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 -#define IA_DEBUG_REG0__sclk_adc_vld__SHIFT__SI 0x0000001e -#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d -#define IA_DEBUG_REG0__sclk_input_vld__SHIFT__SI 0x0000001f -#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x0000001c -#define IA_DEBUG_REG1__SPARE0__SHIFT__SI 0x0000001a -#define IA_DEBUG_REG1__current_data_valid__SHIFT__CI__VI 0x0000001c -#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT__CI__VI 0x00000008 -#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT__CI__VI 0x00000009 -#define IA_DEBUG_REG1__disp_initiator_valid_q__SHIFT__SI 0x0000001f -#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT__CI__VI 0x00000005 -#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT__CI__VI 0x0000000e -#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT__CI__VI 0x0000000f -#define IA_DEBUG_REG1__dma_grp_valid__SHIFT__CI__VI 0x0000001a -#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT__CI__VI 0x00000000 -#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT__CI__VI 0x00000001 -#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT__CI__VI 0x0000000d -#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT__CI__VI 0x0000001e -#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT__CI__VI 0x00000003 -#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT__CI__VI 0x00000010 -#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT__CI__VI 0x00000011 -#define IA_DEBUG_REG1__dma_req_path_q__SHIFT__CI__VI 0x00000007 -#define IA_DEBUG_REG1__dma_request_valid_q__SHIFT__SI 0x00000007 -#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT__CI__VI 0x0000001f -#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT__CI__VI 0x00000018 -#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT__CI__VI 0x00000019 -#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT__CI__VI 0x0000000b -#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT__CI__VI 0x00000004 -#define IA_DEBUG_REG1__draw_initiator_valid_q__SHIFT__SI 0x00000004 -#define IA_DEBUG_REG1__event_addr_valid_q__SHIFT__SI 0x00000006 -#define IA_DEBUG_REG1__event_initiator_valid_q__SHIFT__SI 0x00000005 -#define IA_DEBUG_REG1__free_cnt_q__SHIFT__SI 0x00000014 -#define IA_DEBUG_REG1__grbm_fifo_empty__SHIFT__SI 0x00000000 -#define IA_DEBUG_REG1__grbm_fifo_full__SHIFT__SI 0x00000001 -#define IA_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT__SI 0x0000000c -#define IA_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT__SI 0x00000011 -#define IA_DEBUG_REG1__grbm_fifo_re__SHIFT__SI 0x00000003 -#define IA_DEBUG_REG1__grbm_fifo_we__SHIFT__SI 0x00000002 -#define IA_DEBUG_REG1__grp_dma_read__SHIFT__CI__VI 0x0000001b -#define IA_DEBUG_REG1__immed_data_valid_q__SHIFT__SI 0x00000008 -#define IA_DEBUG_REG1__indx_offset_valid_q__SHIFT__SI 0x0000000b -#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT__CI__VI 0x0000000c -#define IA_DEBUG_REG1__max_indx_valid_q__SHIFT__SI 0x0000000a -#define IA_DEBUG_REG1__min_indx_valid_q__SHIFT__SI 0x00000009 -#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT__CI__VI 0x0000001d -#define IA_DEBUG_REG1__rbiu_di_fifo_we__SHIFT__SI 0x0000001c -#define IA_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT__SI 0x0000001d -#define IA_DEBUG_REG1__rbiu_im_fifo_we__SHIFT__SI 0x0000001e -#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT__CI__VI 0x0000000a -#define IA_DEBUG_REG1__stage2_dr__SHIFT__CI__VI 0x00000012 -#define IA_DEBUG_REG1__stage2_rtr__SHIFT__CI__VI 0x00000013 -#define IA_DEBUG_REG1__stage3_dr__SHIFT__CI__VI 0x00000014 -#define IA_DEBUG_REG1__stage3_rtr__SHIFT__CI__VI 0x00000015 -#define IA_DEBUG_REG1__stage4_dr__SHIFT__CI__VI 0x00000016 -#define IA_DEBUG_REG1__stage4_rtr__SHIFT__CI__VI 0x00000017 -#define IA_DEBUG_REG1__start_new_packet__SHIFT__CI__VI 0x00000002 -#define IA_DEBUG_REG2__bfa_dma_rdreq_freeze__SHIFT__SI 0x0000000b -#define IA_DEBUG_REG2__current_data_valid__SHIFT__SI 0x0000001c -#define IA_DEBUG_REG2__dma_bfa_rdreq_frozen__SHIFT__SI 0x0000000a -#define IA_DEBUG_REG2__dma_busy__SHIFT__SI 0x00000000 -#define IA_DEBUG_REG2__dma_data_fifo_empty_q__SHIFT__SI 0x0000000e -#define IA_DEBUG_REG2__dma_data_fifo_full__SHIFT__SI 0x0000000f -#define IA_DEBUG_REG2__dma_grp_valid__SHIFT__SI 0x0000001a -#define IA_DEBUG_REG2__dma_mask_fifo_empty__SHIFT__SI 0x0000000d -#define IA_DEBUG_REG2__dma_rdreq_dr_q__SHIFT__SI 0x00000003 -#define IA_DEBUG_REG2__dma_skid_fifo_empty__SHIFT__SI 0x00000018 -#define IA_DEBUG_REG2__dma_skid_fifo_full__SHIFT__SI 0x00000019 -#define IA_DEBUG_REG2__grp_dma_read__SHIFT__SI 0x0000001b -#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT__CI__VI 0x0000001c -#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT__CI__VI 0x00000008 -#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT__CI__VI 0x00000009 -#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT__CI__VI 0x00000005 -#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT__CI__VI 0x0000000e -#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT__CI__VI 0x0000000f -#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT__CI__VI 0x0000001a -#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT__CI__VI 0x00000000 -#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT__CI__VI 0x00000001 -#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT__CI__VI 0x0000000d -#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT__CI__VI 0x0000001e -#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT__CI__VI 0x00000003 -#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT__CI__VI 0x00000010 -#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT__CI__VI 0x00000011 -#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT__CI__VI 0x00000007 -#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT__CI__VI 0x0000001f -#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT__CI__VI 0x00000018 -#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT__CI__VI 0x00000019 -#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT__CI__VI 0x0000000b -#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT__CI__VI 0x00000004 -#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT__CI__VI 0x0000001b -#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT__CI__VI 0x0000000c -#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT__CI__VI 0x0000001d -#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT__CI__VI 0x0000000a -#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT__CI__VI 0x00000012 -#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT__CI__VI 0x00000013 -#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT__CI__VI 0x00000014 -#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT__CI__VI 0x00000015 -#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT__CI__VI 0x00000016 -#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT__CI__VI 0x00000017 -#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT__CI__VI 0x00000002 -#define IA_DEBUG_REG2__instances_remaining__SHIFT__SI 0x0000001f -#define IA_DEBUG_REG2__last_rdreq_in_dma_op__SHIFT__SI 0x0000000c -#define IA_DEBUG_REG2__mask_kill__SHIFT__SI 0x0000001e -#define IA_DEBUG_REG2__mc_rdreq_sent_cnt_q__SHIFT__SI 0x00000004 -#define IA_DEBUG_REG2__rbiu_dma_valid__SHIFT__SI 0x00000001 -#define IA_DEBUG_REG2__rbiu_read__SHIFT__SI 0x00000002 -#define IA_DEBUG_REG2__reserved__SHIFT__SI 0x00000010 -#define IA_DEBUG_REG2__second_128bit_read__SHIFT__SI 0x0000001d -#define IA_DEBUG_REG2__stage2_dr__SHIFT__SI 0x00000012 -#define IA_DEBUG_REG2__stage2_rtr__SHIFT__SI 0x00000013 -#define IA_DEBUG_REG2__stage3_dr__SHIFT__SI 0x00000014 -#define IA_DEBUG_REG2__stage3_rtr__SHIFT__SI 0x00000015 -#define IA_DEBUG_REG2__stage4_dr__SHIFT__SI 0x00000016 -#define IA_DEBUG_REG2__stage4_rtr__SHIFT__SI 0x00000017 -#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT__CI__VI 0x0000001d -#define IA_DEBUG_REG3__SPARE__SHIFT__SI 0x0000001e -#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT__CI__VI 0x0000001f -#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT__CI__VI 0x0000001e -#define IA_DEBUG_REG3__adc_spi_freeze_r0__SHIFT__SI 0x00000009 -#define IA_DEBUG_REG3__adc_spi_freeze_r1__SHIFT__SI 0x00000013 -#define IA_DEBUG_REG3__adc_spi_freeze_r2__SHIFT__SI 0x0000001d -#define IA_DEBUG_REG3__csinvoc_en_r0__SHIFT__SI 0x00000003 -#define IA_DEBUG_REG3__csinvoc_en_r1__SHIFT__SI 0x0000000d -#define IA_DEBUG_REG3__csinvoc_en_r2__SHIFT__SI 0x00000017 -#define IA_DEBUG_REG3__current_state_r0__SHIFT__SI 0x00000000 -#define IA_DEBUG_REG3__current_state_r1__SHIFT__SI 0x0000000a -#define IA_DEBUG_REG3__current_state_r2__SHIFT__SI 0x00000014 -#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT__CI__VI 0x0000001a -#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT__CI__VI 0x0000001b -#define IA_DEBUG_REG3__dispatch_init_force_start_at_000_r0__SHIFT__SI 0x00000005 -#define IA_DEBUG_REG3__dispatch_init_force_start_at_000_r1__SHIFT__SI 0x0000000f -#define IA_DEBUG_REG3__dispatch_init_force_start_at_000_r2__SHIFT__SI 0x00000019 -#define IA_DEBUG_REG3__dispatch_init_ordered_append_enbl_r0__SHIFT__SI 0x00000006 -#define IA_DEBUG_REG3__dispatch_init_ordered_append_enbl_r1__SHIFT__SI 0x00000010 -#define IA_DEBUG_REG3__dispatch_init_ordered_append_enbl_r2__SHIFT__SI 0x0000001a -#define IA_DEBUG_REG3__dispatch_init_partial_tg_en_r0__SHIFT__SI 0x00000004 -#define IA_DEBUG_REG3__dispatch_init_partial_tg_en_r1__SHIFT__SI 0x0000000e -#define IA_DEBUG_REG3__dispatch_init_partial_tg_en_r2__SHIFT__SI 0x00000018 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT__CI__VI 0x00000003 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT__CI__VI 0x00000002 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT__CI__VI 0x00000001 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT__CI__VI 0x00000004 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT__CI__VI 0x00000000 -#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT__CI__VI 0x0000000b -#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT__CI__VI 0x0000000a -#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT__CI__VI 0x00000009 -#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT__CI__VI 0x0000000c -#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT__CI__VI 0x00000008 -#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT__CI__VI 0x0000000f -#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT__CI__VI 0x00000005 -#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT__CI__VI 0x0000000d -#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT__CI__VI 0x00000012 -#define IA_DEBUG_REG3__kill_threadgroup_r0__SHIFT__SI 0x00000008 -#define IA_DEBUG_REG3__kill_threadgroup_r1__SHIFT__SI 0x00000012 -#define IA_DEBUG_REG3__kill_threadgroup_r2__SHIFT__SI 0x0000001c -#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT__CI__VI 0x0000001c -#define IA_DEBUG_REG3__mc_out_rtr__SHIFT__CI__VI 0x0000000e -#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT__CI__VI 0x00000006 -#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT__CI__VI 0x00000014 -#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT__CI__VI 0x00000015 -#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT__CI__VI 0x00000016 -#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT__CI__VI 0x00000017 -#define IA_DEBUG_REG3__pipe0_dr__SHIFT__CI__VI 0x00000010 -#define IA_DEBUG_REG3__pipe0_rtr__SHIFT__CI__VI 0x00000011 -#define IA_DEBUG_REG3__reset_wave_id_r0__SHIFT__SI 0x00000007 -#define IA_DEBUG_REG3__reset_wave_id_r1__SHIFT__SI 0x00000011 -#define IA_DEBUG_REG3__reset_wave_id_r2__SHIFT__SI 0x0000001b -#define IA_DEBUG_REG3__send_pipe1_req__SHIFT__CI__VI 0x00000007 -#define IA_DEBUG_REG3__tc_out_rtr__SHIFT__CI__VI 0x00000013 -#define IA_DEBUG_REG3__tc_req_count_q__SHIFT__CI__VI 0x00000018 -#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x0000001f -#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x00000014 -#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT__CI__VI 0x0000001d -#define IA_DEBUG_REG4__di_first_group_of_inst_q__SHIFT__SI 0x0000001d -#define IA_DEBUG_REG4__di_major_mode_p1_q_0__SHIFT__SI 0x00000010 -#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT__CI__VI 0x00000010 -#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x0000001a -#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x00000015 -#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x00000019 -#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x00000018 -#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x00000006 -#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x00000007 -#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x00000011 -#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0x0000000f -#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0x0000000e -#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT__CI__VI 0x0000001e -#define IA_DEBUG_REG4__last_shift_of_instance__SHIFT__SI 0x0000001e -#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x00000000 -#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x00000008 -#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x00000001 -#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x00000009 -#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x00000002 -#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0x0000000a -#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x00000003 -#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0x0000000b -#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x00000004 -#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0x0000000c -#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x00000005 -#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0x0000000d -#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x0000001c -#define IA_DEBUG_REG5__current_instance_q_15_0__SHIFT__SI 0x00000010 -#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x00000000 -#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT__CI__VI 0x0000001f -#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT__CI__VI 0x0000001e -#define IA_DEBUG_REG5__instanceid_13_0__SHIFT__CI__VI 0x00000010 -#define IA_DEBUG_REG6__after_group_partial__SHIFT__CI__VI 0x00000016 -#define IA_DEBUG_REG6__after_prim_partial__SHIFT__SI 0x00000016 -#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0x0000000f -#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x00000000 -#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x00000004 -#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x00000008 -#define IA_DEBUG_REG6__extract_group__SHIFT 0x00000017 -#define IA_DEBUG_REG6__first_group_partial__SHIFT__CI__VI 0x0000000d -#define IA_DEBUG_REG6__first_prim_partial__SHIFT__SI 0x0000000d -#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT__CI__VI 0x00000018 -#define IA_DEBUG_REG6__next_group_partial__SHIFT__CI__VI 0x00000015 -#define IA_DEBUG_REG6__next_prim_partial__SHIFT__SI 0x00000015 -#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x00000010 -#define IA_DEBUG_REG6__second_group_partial__SHIFT__CI__VI 0x0000000e -#define IA_DEBUG_REG6__second_prim_partial__SHIFT__SI 0x0000000e -#define IA_DEBUG_REG6__shifter_load_needed__SHIFT__SI 0x0000001e -#define IA_DEBUG_REG6__shifter_space_avail__SHIFT__SI 0x0000001d -#define IA_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT__SI 0x0000001f -#define IA_DEBUG_REG6__shifter_word_count_q__SHIFT__SI 0x00000018 -#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x00000019 -#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x0000001a -#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x0000001b -#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT__CI__VI 0x00000017 -#define IA_DEBUG_REG7__last_group_of_inst_p2_q__SHIFT__SI 0x00000017 -#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x00000014 -#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x00000000 -#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x00000018 -#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x0000001f -#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x0000001e -#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x0000001d -#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x0000001c -#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0x0000000c -#define IA_DEBUG_REG7__shift_vect1_comp_en_p2_q__SHIFT__SI 0x00000008 -#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x00000010 -#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT__CI__VI 0x00000008 -#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x00000004 -#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x00000000 -#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x0000001c -#define IA_DEBUG_REG8__grp_continued__SHIFT 0x0000000b -#define IA_DEBUG_REG8__grp_eop__SHIFT 0x00000019 -#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x0000001a -#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x0000001b -#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x00000018 -#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x00000015 -#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0x0000000c -#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0x0000000f -#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x00000008 -#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0x0000000a -#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x00000009 -#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x00000007 -#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x00000005 -#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x00000006 -#define IA_DEBUG_REG9__SPARE0__SHIFT__CI__VI 0x0000000e -#define IA_DEBUG_REG9__SPARE1__SHIFT__CI__VI 0x0000000f -#define IA_DEBUG_REG9__disp_se_switch_p6__SHIFT__SI 0x0000000e -#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0x0000000a -#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x00000009 -#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x00000001 -#define IA_DEBUG_REG9__gfx_send_to_se1_p5_q__SHIFT__SI 0x0000000d -#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT__CI__VI 0x00000012 -#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT__CI__VI 0x00000013 -#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x00000003 -#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x00000002 -#define IA_DEBUG_REG9__other_se_empty_packet_p6__SHIFT__SI 0x0000000f -#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x00000005 -#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x00000007 -#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x00000004 -#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x00000008 -#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x00000006 -#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x00000011 -#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0x0000000b -#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0x0000000c -#define IA_DEBUG_REG9__prim_counter_q__SHIFT__CI__VI 0x00000014 -#define IA_DEBUG_REG9__prim_counter_q__SHIFT__SI 0x00000012 -#define IA_DEBUG_REG9__send_to_se1_p5_q__SHIFT__SI 0x00000000 -#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT__CI__VI 0x00000000 -#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT__CI__VI 0x00000010 -#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT__CI__VI 0x0000000d -#define IA_DEBUG_REG9__valid_eop_switch_p6__SHIFT__SI 0x00000010 -#define IA_ENHANCE__MISC__SHIFT 0x00000000 -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x00000012 -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x00000010 -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x00000000 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x00000013 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x00000011 -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT__CI__VI 0x00000014 -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c -#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c -#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c -#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_VMID_OVERRIDE__ENABLE__SHIFT__SI__CI 0x00000000 -#define IA_VMID_OVERRIDE__VMID__SHIFT__SI__CI 0x00000001 -#define ICON_COLOR1__ICON_COLOR1_BLUE__SHIFT__SI 0x00000000 -#define ICON_COLOR1__ICON_COLOR1_GREEN__SHIFT__SI 0x00000008 -#define ICON_COLOR1__ICON_COLOR1_RED__SHIFT__SI 0x00000010 -#define ICON_COLOR2__ICON_COLOR2_BLUE__SHIFT__SI 0x00000000 -#define ICON_COLOR2__ICON_COLOR2_GREEN__SHIFT__SI 0x00000008 -#define ICON_COLOR2__ICON_COLOR2_RED__SHIFT__SI 0x00000010 -#define ICON_CONTROL__ICON_2X_MAGNIFY__SHIFT__SI 0x00000010 -#define ICON_CONTROL__ICON_ENABLE__SHIFT__SI 0x00000000 -#define ICON_CONTROL__ICON_FORCE_MC_ON__SHIFT__SI 0x00000014 -#define ICON_SIZE__ICON_HEIGHT__SHIFT__SI 0x00000000 -#define ICON_SIZE__ICON_WIDTH__SHIFT__SI 0x00000010 -#define ICON_START_POSITION__ICON_X_POSITION__SHIFT__SI 0x00000010 -#define ICON_START_POSITION__ICON_Y_POSITION__SHIFT__SI 0x00000000 -#define ICON_SURFACE_ADDRESS_HIGH__ICON_SURFACE_ADDRESS_HIGH__SHIFT__SI 0x00000000 -#define ICON_SURFACE_ADDRESS__ICON_SURFACE_ADDRESS__SHIFT__SI 0x00000000 -#define ICON_UPDATE__ICON_DISABLE_MULTIPLE_UPDATE__SHIFT__SI 0x00000018 -#define ICON_UPDATE__ICON_UPDATE_LOCK__SHIFT__SI 0x00000010 -#define ICON_UPDATE__ICON_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define ICON_UPDATE__ICON_UPDATE_TAKEN__SHIFT__SI 0x00000001 -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_DATA_SEND__SHIFT__SI 0x0000001f -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_EOC__SHIFT__SI 0x0000001e -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_P0_B_CB__SHIFT__SI 0x00000014 -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_P0_G_Y__SHIFT__SI 0x0000000a -#define ID00_DCP_LB_DATA_P0__ID00_DCP_LB_P0_R_CR__SHIFT__SI 0x00000000 -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_DISPNUM__SHIFT__SI 0x0000001e -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_P1_B_CB__SHIFT__SI 0x00000014 -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_P1_G_Y__SHIFT__SI 0x0000000a -#define ID01_DCP_LB_DATA_P1__ID01_DCP_LB_P1_R_CR__SHIFT__SI 0x00000000 -#define ID01_DCP_LB_DATA_P1__ID01_LB_DCP_SOF2__SHIFT__SI 0x0000001f -#define ID02_DCP_DMIF_GRPH_DATA_LOW_p0__ID02_DMIF_DCP_grph_data_LOW_p0__SHIFT__SI 0x00000000 -#define ID03_DCP_DMIF_GRPH_DATA_HIGH_p0__ID03_DMIF_DCP_grph_data_HIGH_p0__SHIFT__SI 0x00000000 -#define ID04_DCP_DMIF_GRPH_DATA_LOW_p1__ID04_DMIF_DCP_grph_data_LOW_p1__SHIFT__SI 0x00000000 -#define ID05_DCP_DMIF_GRPH_DATA_HIGH_p1__ID05_DMIF_DCP_grph_data_HIGH_p1__SHIFT__SI 0x00000000 -#define ID06_DCP_DMIF_OVLDATA_p0__ID06_DMIF_DCP_ovl_data_p0__SHIFT__SI 0x00000000 -#define ID07_DCP_DMIF_OVLDATA_p1__ID07_DMIF_DCP_ovl_data_p1__SHIFT__SI 0x00000000 -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_DCP_LB_RTR__SHIFT__SI 0x0000001e -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_CHUNKSIZE__SHIFT__SI 0x0000001b -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_DISPNUM__SHIFT__SI 0x00000007 -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_L0_TAG__SHIFT__SI 0x00000000 -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_L1_TAG__SHIFT__SI 0x00000003 -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_LAST_CHUNK_OF_LINE__SHIFT__SI 0x0000001c -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_NOT_LAST_LINE_PAIR__SHIFT__SI 0x0000001d -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_RTS__SHIFT__SI 0x00000006 -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_SOF1__SHIFT__SI 0x0000001f -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_X__SHIFT__SI 0x00000008 -#define ID08_DCP_LB_CHUNK_REQUEST__ID08_LB_DCP_Y__SHIFT__SI 0x0000000e -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_req__SHIFT__SI 0x00000014 -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_size__SHIFT__SI 0x00000015 -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_surface__SHIFT__SI 0x00000018 -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_x__SHIFT__SI 0x00000000 -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DCP_DMIF_y__SHIFT__SI 0x00000007 -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_DMIF_DCP_req_fifo_empty__SHIFT__SI 0x00000017 -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D1_START_LINE__SHIFT__SI 0x0000001a -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D1_STEREO_SELECT__SHIFT__SI 0x0000001c -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D1_V_UPDATE__SHIFT__SI 0x0000001e -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D2_START_LINE__SHIFT__SI 0x0000001b -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D2_STEREO_SELECT__SHIFT__SI 0x0000001d -#define ID09_DCP_DMIF_CHUNK_REQUEST__ID09_LB_DCP_D2_V_UPDATE__SHIFT__SI 0x0000001f -#define ID10_DCP_DCCIF_DATA__ID10_CRTC1_DCP_htotal_by_8__SHIFT__SI 0x00000010 -#define ID10_DCP_DCCIF_DATA__ID10_CRTC2_DCP_htotal_by_8__SHIFT__SI 0x00000011 -#define ID10_DCP_DCCIF_DATA__ID10_DCCG_SCLK_G_DCP_clock_on__SHIFT__SI 0x0000000d -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_CLIENT_RTAG__SHIFT__SI 0x00000003 -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_CLIENT_R_ID__SHIFT__SI 0x0000000b -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_CLIENT_VALID__SHIFT__SI 0x00000002 -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_DCP_CURSOR_RRTR__SHIFT__SI 0x00000001 -#define ID10_DCP_DCCIF_DATA__ID10_DCCIF_DCP_ICON_RRTR__SHIFT__SI 0x00000000 -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_grph_rtr__SHIFT__SI 0x00000013 -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_ovl_rtr__SHIFT__SI 0x00000014 -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_req__SHIFT__SI 0x00000015 -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_size__SHIFT__SI 0x00000016 -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_urgent__SHIFT__SI 0x0000001f -#define ID10_DCP_DCCIF_DATA__ID10_DCP_DMIF_x__SHIFT__SI 0x00000018 -#define ID10_DCP_DCCIF_DATA__ID10_DMIF_DCP_busy__SHIFT__SI 0x0000000f -#define ID10_DCP_DCCIF_DATA__ID10_LB_DCP_URGENT__SHIFT__SI 0x00000012 -#define ID10_DCP_DCCIF_DATA__ID10_LB_DCP_WR_busy__SHIFT__SI 0x0000000e -#define ID11_DCP_DCCIF_REQUEST__ID11_DCP_ICON_DCCIF_ID__SHIFT__SI 0x0000001d -#define ID11_DCP_DCCIF_REQUEST__ID11_DCP_ICON_DCCIF_RADDR__SHIFT__SI 0x00000001 -#define ID11_DCP_DCCIF_REQUEST__ID11_DCP_ICON_DCCIF_RREQ__SHIFT__SI 0x00000000 -#define ID12_DCP_DCCIF_REQUEST__ID12_DCP_CURSOR_DCCIF_ID__SHIFT__SI 0x0000001d -#define ID12_DCP_DCCIF_REQUEST__ID12_DCP_CURSOR_DCCIF_RADDR__SHIFT__SI 0x00000001 -#define ID12_DCP_DCCIF_REQUEST__ID12_DCP_CURSOR_DCCIF_RREQ__SHIFT__SI 0x00000000 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_CURSOR_DCCIF_RTAG__SHIFT__SI 0x00000008 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_CURSOR_DCCIF_URGENT__SHIFT__SI 0x00000011 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_CURSOR_EN_p0__SHIFT__SI 0x00000019 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_CURSOR_EN_p1__SHIFT__SI 0x0000001a -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_GRPH_EN_p0__SHIFT__SI 0x00000015 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_GRPH_EN_p1__SHIFT__SI 0x00000016 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_G_O_REQUEST_STATE__SHIFT__SI 0x0000001d -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_ICON_EN_p0__SHIFT__SI 0x0000001b -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_ICON_EN_p1__SHIFT__SI 0x0000001c -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_OVL_EN_p0__SHIFT__SI 0x00000017 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_DEBUG_OVL_EN_p1__SHIFT__SI 0x00000018 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_ICON_DCCIF_RTAG__SHIFT__SI 0x00000000 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_ICON_DCCIF_URGENT__SHIFT__SI 0x00000012 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_PER_lut_host_rw__SHIFT__SI 0x00000013 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_PER_lut_rw_by_host__SHIFT__SI 0x00000014 -#define ID13_DCP_DCCIF_REQUEST__ID13_DCP_RBBMIF_ready__SHIFT__SI 0x00000010 -#define ID14_DCP_DMIF_STATUS__ID14_DCP_d1req_pipe_idle__SHIFT__SI 0x00000000 -#define ID14_DCP_DMIF_STATUS__ID14_DCP_d2req_pipe_idle__SHIFT__SI 0x00000001 -#define ID14_DCP_DMIF_STATUS__ID15_DMIF_dmif_req_pipe_idle__SHIFT__SI 0x00000010 -#define ID14_DMIF_STATUS__ID14_DCP_d1req_pipe_idle__SHIFT__SI 0x00000000 -#define ID14_DMIF_STATUS__ID14_DCP_d2req_pipe_idle__SHIFT__SI 0x00000001 -#define ID14_DMIF_STATUS__ID15_DMIF_DCP_debug_mc_max_latency_overflow__SHIFT__SI 0x00000019 -#define ID14_DMIF_STATUS__ID15_DMIF_DCP_debug_mc_min_latency_overflow__SHIFT__SI 0x00000018 -#define ID14_DMIF_STATUS__ID15_DMIF_dmif_req_pipe_idle__SHIFT__SI 0x00000010 -#define ID15_DMIF_MC_LATENCY__ID15_DMIF_DCP_debug_mc_max_latency__SHIFT__SI 0x00000010 -#define ID15_DMIF_MC_LATENCY__ID15_DMIF_DCP_debug_mc_min_latency__SHIFT__SI 0x00000000 -#define ID16_MCIF_MC_LATENCY__ID16_MCIF_DCP_debug_mc_max_latency_overflow__SHIFT__SI 0x00000019 -#define ID16_MCIF_MC_LATENCY__ID16_MCIF_DCP_debug_mc_min_latency_overflow__SHIFT__SI 0x00000018 -#define ID17_MCIF_MC_LATENCY__ID17_MCIF_DCP_debug_mc_max_latency__SHIFT__SI 0x00000010 -#define ID17_MCIF_MC_LATENCY__ID17_MCIF_DCP_debug_mc_min_latency__SHIFT__SI 0x00000000 -#define ID18_D1GRPH_PRIMARY_SURFACE_ADDRESS__ID18_D1GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT__SI \ - 0x00000000 -#define ID19_D1GRPH_SECONDARY_SURFACE_ADDRESS__ID19_D1GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT__SI \ - 0x00000000 -#define ID20_D1OVL_SURFACE_ADDRESS__ID20_D1OVL_SURFACE_ADDRESS__SHIFT__SI 0x00000000 -#define ID21_D1GRPH_COMPRESS_SURFACE_ADDRESS__ID21_D1GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT__SI \ - 0x00000000 -#define ID22_D1CURSOR_SURFACE_ADDRESS__ID22_D1CURSOR_SURFACE_ADDRESS__SHIFT__SI 0x00000000 -#define ID23_D1ICON_SURFACE_ADDRESS__ID23_D1ICON_SURFACE_ADDRESS__SHIFT__SI 0x00000000 -#define ID30_DCCARB_VIP_R_ADDR__ID30_DCCARB_VIP_R_ADDR__SHIFT__SI 0x00000000 -#define ID31_DCCARB_DCT_R_ADDR__ID31_DCCARB_DCT_R_ADDR__SHIFT__SI 0x00000000 -#define ID34_DCCARB_FBC_R_ADDR__ID34_DCCARB_FBC_R_ADDR__SHIFT__SI 0x00000000 -#define ID35_DCCARB_VGA_W_ADDR__ID35_DCCARB_VGA_W_ADDR__SHIFT__SI 0x00000000 -#define ID36_DCCARB_FBC_W_ADDR__ID36_DCCARB_FBC_W_ADDR__SHIFT__SI 0x00000000 -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_MC_RDREQ_FREE__SHIFT__SI 0x00000001 -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_MC_RDREQ_SEND__SHIFT__SI 0x00000000 -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_TAP_RDNFO_ASK__SHIFT__SI 0x00000004 -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_TAP_RDNFO_GO__SHIFT__SI 0x00000005 -#define ID37_MC_IF_DEBUG_01__ID37_DMIF_TAP_RDREQ_SEND__SHIFT__SI 0x00000003 -#define ID37_MC_IF_DEBUG_01__ID37_MC_DMIF_RDRET_VLD__SHIFT__SI 0x00000002 -#define ID37_MC_IF_DEBUG_01__ID37_MC_VIP_WRCLEAN_PHASE__SHIFT__SI 0x0000000f -#define ID37_MC_IF_DEBUG_01__ID37_TAP_DMIF_RDRET_NACK__SHIFT__SI 0x00000007 -#define ID37_MC_IF_DEBUG_01__ID37_TAP_DMIF_RDRET_VLD__SHIFT__SI 0x00000006 -#define ID37_MC_IF_DEBUG_01__ID37_TAP_VIP_WRRET_NACK__SHIFT__SI 0x00000015 -#define ID37_MC_IF_DEBUG_01__ID37_TAP_VIP_WRRET_VLD__SHIFT__SI 0x00000014 -#define ID37_MC_IF_DEBUG_01__ID37_VIP_MC_WRREQ_FREE__SHIFT__SI 0x0000000d -#define ID37_MC_IF_DEBUG_01__ID37_VIP_MC_WRREQ_PHASE__SHIFT__SI 0x0000000e -#define ID37_MC_IF_DEBUG_01__ID37_VIP_MC_WRREQ_SEND__SHIFT__SI 0x0000000c -#define ID37_MC_IF_DEBUG_01__ID37_VIP_TAP_WRNFO_ASK__SHIFT__SI 0x00000012 -#define ID37_MC_IF_DEBUG_01__ID37_VIP_TAP_WRNFO_GO__SHIFT__SI 0x00000013 -#define ID37_MC_IF_DEBUG_01__ID37_VIP_TAP_WRREQ_SEND__SHIFT__SI 0x00000011 -#define ID38_MC_IF_DEBUG_02__ID38_DMIF_MC_RDREQ_ADDR__SHIFT__SI 0x00000000 -#define ID39_MC_IF_DEBUG_03__ID39_DMIF_TAP_RDREQ_ADDR__SHIFT__SI 0x00000000 -#define ID40_MC_IF_DEBUG_04__ID40_VIP_MC_WRREQ_ADDR__SHIFT__SI 0x00000000 -#define ID41_MC_IF_DEBUG_05__ID41_VIP_TAP_WRREQ_ADDR__SHIFT__SI 0x00000000 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_RDREQ_FREE__SHIFT__SI 0x00000001 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_RDREQ_SEND__SHIFT__SI 0x00000000 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_WRREQ_FREE__SHIFT__SI 0x0000000d -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_WRREQ_PHASE__SHIFT__SI 0x0000000e -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_MC_WRREQ_SEND__SHIFT__SI 0x0000000c -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_RDNFO_ASK__SHIFT__SI 0x00000004 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_RDNFO_GO__SHIFT__SI 0x00000005 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_RDREQ_SEND__SHIFT__SI 0x00000003 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_WRNFO_ASK__SHIFT__SI 0x00000012 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_WRNFO_GO__SHIFT__SI 0x00000013 -#define ID42_MC_IF_DEBUG_06__ID42_MCIF_TAP_WRREQ_SEND__SHIFT__SI 0x00000011 -#define ID42_MC_IF_DEBUG_06__ID42_MC_MCIF_RDRET_VLD__SHIFT__SI 0x00000002 -#define ID42_MC_IF_DEBUG_06__ID42_MC_MCIF_WRCLEAN_PHASE__SHIFT__SI 0x0000000f -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_RDRET_NACK__SHIFT__SI 0x00000007 -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_RDRET_VLD__SHIFT__SI 0x00000006 -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_WRRET_NACK__SHIFT__SI 0x00000015 -#define ID42_MC_IF_DEBUG_06__ID42_TAP_MCIF_WRRET_VLD__SHIFT__SI 0x00000014 -#define ID43_MC_IF_DEBUG_07__ID43_MCIF_MC_RDREQ_ADDR__SHIFT__SI 0x00000000 -#define ID44_MC_IF_DEBUG_08__ID44_MCIF_TAP_RDREQ_ADDR__SHIFT__SI 0x00000000 -#define ID45_MC_IF_DEBUG_09__ID45_MCIF_MC_WRREQ_ADDR__SHIFT__SI 0x00000000 -#define ID46_MC_IF_DEBUG_10__ID46_MCIF_TAP_WRREQ_ADDR__SHIFT__SI 0x00000000 -#define IDCT_AUTH0__AUTH0__SHIFT__SI 0x00000000 -#define IDCT_AUTH1__AUTH1__SHIFT__SI 0x00000000 -#define IDCT_AUTH2__AUTH2__SHIFT__SI 0x00000000 -#define IDCT_AUTH3__AUTH3__SHIFT__SI 0x00000000 -#define IDCT_AUTH_CONTROL0__CONTROL0_BITS__SHIFT__SI 0x00000000 -#define IDCT_AUTH_CONTROL1__CONTROL1_BITS__SHIFT__SI 0x00000000 -#define IDCT_AUTH_CONTROL2__CONTROL2_BITS__SHIFT__SI 0x00000000 -#define IDCT_AUTH_CONTROL3__CONTROL3_BITS__SHIFT__SI 0x00000000 -#define IDCT_COEF_BASE__IDCT_COEF_MEM_LOCATION__SHIFT__SI 0x00000000 -#define IDCT_COEF_DATA__IDCT_COEF_DATA__SHIFT__SI 0x00000000 -#define IDCT_CONFIG__IDCT_RDREQ_URG__SHIFT__SI 0x00000008 -#define IDCT_CONFIG__IDCT_REQ_TRAN__SHIFT__SI 0x00000010 -#define IDCT_CONTROL__COEF_FETCH_WATERMARK__SHIFT__SI 0x0000001a -#define IDCT_CONTROL__COEF_SWAP__SHIFT__SI 0x00000018 -#define IDCT_CONTROL__DCT_CORE_BYPASS__SHIFT__SI 0x00000011 -#define IDCT_CONTROL__DRM_MASK_DEBUG_EN__SHIFT__SI 0x0000001e -#define IDCT_CONTROL__IDCT_248_MODE__SHIFT__SI 0x0000000d -#define IDCT_CONTROL__IDCT_CTL_INTRA__SHIFT__SI 0x00000005 -#define IDCT_CONTROL__IDCT_CTL_SCAN_PATTERN__SHIFT__SI 0x00000003 -#define IDCT_CONTROL__IDCT_DECRYP_SEL__SHIFT__SI 0x00000009 -#define IDCT_CONTROL__IDCT_FIELD_ENCODING__SHIFT__SI 0x0000000b -#define IDCT_CONTROL__IDCT_MISMATCH_CONTROL__SHIFT__SI 0x00000010 -#define IDCT_CONTROL__IDCT_SCRAMBLE__SHIFT__SI 0x0000000a -#define IDCT_CONTROL__IDCT_ZERO_ON_ERROR__SHIFT__SI 0x0000000c -#define IDCT_CURRENT_MB_STATUS_DEBUG__CURRENT_MACROBLOCK_NUMBER__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_00__DEBUG00_SCRAM_IDCT3A__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_01__DEBUG01_SCRAM_IDCT3B__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_02__DEBUG02_SCRAM_IDCT3C__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_03__DEBUG03_SCRAM_IDCT3D__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_04__DEBUG04_DEZIGZAG__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_05__DEBUG05_INTER_BUF__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_06__DEBUG06_OUT_BUF__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_0A__DEBUG0A_IDCT_RD_CTRL_DEBUG_1__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_0A__DEBUG0A_IDCT_RD_CTRL_DEBUG_2__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_0B__DEBUG0B_IDCT_RD_CTRL_DEBUG_3__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_0B__DEBUG0B_IDCT_RD_CTRL_DEBUG_4__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_0C__DEBUG0C_IDCT_RD_CTRL_DEBUG_5__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_0C__DEBUG0C_IDCT_RD_CTRL_DEBUG_6__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_18__DEBUG18_IDCT_RD_CTRL_DEBUG_7__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_18__DEBUG18_IDCT_RD_CTRL_DEBUG_8__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_19__DEBUG19_IDCT_RD_CTRL_DEBUG_10__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_19__DEBUG19_IDCT_RD_CTRL_DEBUG_9__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_20__DEBUG20_IDCT_RD_CTRL_DEBUG_11__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_20__DEBUG20_IDCT_RD_CTRL_DEBUG_12__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_21__DEBUG21_IDCT_RD_CTRL_DEBUG_13__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_21__DEBUG21_IDCT_RD_CTRL_DEBUG_14__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_22__DEBUG22_IDCT_RD_CTRL_DEBUG_15__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_23__DEBUG23_IDCT_DRM_IF_DEBUG_1__SHIFT__SI 0x00000000 -#define IDCT_DEBUG_23__DEBUG23_IDCT_DRM_IF_DEBUG_2__SHIFT__SI 0x0000000c -#define IDCT_DEBUG_24__DEBUG24_IDCT_DRM_IF_DEBUG_3__SHIFT__SI 0x00000000 -#define IDCT_DRM_CONTROL_STATUS__DRM_VCPU_FLUSHED__SHIFT__SI 0x00000000 -#define IDCT_DRM_CONTROL_STATUS__DRM_VCPU_STOP_FLUSH__SHIFT__SI 0x00000001 -#define IDCT_DRM_WR_CREDIT__DRM_WR_CREDIT__SHIFT__SI 0x00000000 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_00__SHIFT__SI 0x00000000 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_01__SHIFT__SI 0x00000001 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_02__SHIFT__SI 0x00000002 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_03__SHIFT__SI 0x00000003 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_04__SHIFT__SI 0x00000004 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_05__SHIFT__SI 0x00000005 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_06__SHIFT__SI 0x00000006 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_07__SHIFT__SI 0x00000007 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_08__SHIFT__SI 0x00000008 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_09__SHIFT__SI 0x00000009 -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_10__SHIFT__SI 0x0000000a -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_11__SHIFT__SI 0x0000000b -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_12__SHIFT__SI 0x0000000c -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_13__SHIFT__SI 0x0000000d -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_14__SHIFT__SI 0x0000000e -#define IDCT_EOB_ERROR_STATUS__IDCT_EOB_ERROR_15__SHIFT__SI 0x0000000f -#define IDCT_IDLE_DEBUG__CMDIF_CTRL_IDLE_STAT__SHIFT__SI 0x0000000a -#define IDCT_IDLE_DEBUG__DEZIGZAG_IDLE_STAT__SHIFT__SI 0x0000001c -#define IDCT_IDLE_DEBUG__DRM_IF_IDLE_STAT__SHIFT__SI 0x0000001e -#define IDCT_IDLE_DEBUG__IDCT_END_OF_STREAM_STAT__SHIFT__SI 0x00000004 -#define IDCT_IDLE_DEBUG__IDCT_IDLE_STAT__SHIFT__SI 0x00000000 -#define IDCT_IDLE_DEBUG__INTER_BUF_IDLE_STAT__SHIFT__SI 0x0000001b -#define IDCT_IDLE_DEBUG__OUT_BUF_IDLE_STAT__SHIFT__SI 0x0000001a -#define IDCT_IDLE_DEBUG__XDCT_COEF_RDER_IDLE_STAT__SHIFT__SI 0x00000019 -#define IDCT_PIO_MODE_XY__IDCT_PIO_SCREEN_X__SHIFT__SI 0x00000000 -#define IDCT_PIO_MODE_XY__IDCT_PIO_SCREEN_Y__SHIFT__SI 0x00000010 -#define IDCT_SCRAMBLE_SELECT__IDCT_SCRAMBLE_SELECT__SHIFT__SI 0x00000000 -#define IDCT_SCRATCH__IDCT_SCRATCH__SHIFT__SI 0x00000000 -#define IDCT_SPAN__IDCT_SPAN__SHIFT__SI 0x00000000 -#define IDCT_STATUS__IDCT_ERROR_00__SHIFT__SI 0x00000000 -#define IDCT_STATUS__IDCT_ERROR_01__SHIFT__SI 0x00000001 -#define IDCT_STATUS__IDCT_ERROR_02__SHIFT__SI 0x00000002 -#define IDCT_STATUS__IDCT_ERROR_03__SHIFT__SI 0x00000003 -#define IDCT_STATUS__IDCT_ERROR_04__SHIFT__SI 0x00000004 -#define IDCT_STATUS__IDCT_ERROR_05__SHIFT__SI 0x00000005 -#define IDCT_STATUS__IDCT_ERROR_06__SHIFT__SI 0x00000006 -#define IDCT_STATUS__IDCT_ERROR_07__SHIFT__SI 0x00000007 -#define IDCT_STATUS__IDCT_ERROR_08__SHIFT__SI 0x00000008 -#define IDCT_STATUS__IDCT_ERROR_09__SHIFT__SI 0x00000009 -#define IDCT_STATUS__IDCT_ERROR_10__SHIFT__SI 0x0000000a -#define IDCT_STATUS__IDCT_ERROR_11__SHIFT__SI 0x0000000b -#define IDCT_STATUS__IDCT_ERROR_12__SHIFT__SI 0x0000000c -#define IDCT_STATUS__IDCT_ERROR_13__SHIFT__SI 0x0000000d -#define IDCT_STATUS__IDCT_ERROR_14__SHIFT__SI 0x0000000e -#define IDCT_STATUS__IDCT_ERROR_15__SHIFT__SI 0x0000000f -#define IDCT_STATUS__IDCT_IDLE__SHIFT__SI 0x0000001f -#define IDCT_STATUS__IDCT_PIO_READY__SHIFT__SI 0x0000001e -#define IDCT_STREAM_ID__STREAM_ID__SHIFT__SI 0x00000000 -#define IDCT_TEST_DEBUG_DATA__IDCT_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define IDCT_TEST_DEBUG_INDEX__IDCT_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define IDDCCIF00_DBG_DCCIF_A__DBG_DCCIF_A__SHIFT__SI 0x00000000 -#define IDDCCIF01_DBG_DCCIF_B__DBG_DCCIF_B__SHIFT__SI 0x00000000 -#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT__SI 0x00000000 -#define IDDCCIF03_DBG_DCCIF_D__DBG_DCCIF_D__SHIFT__SI 0x00000000 -#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT__SI 0x00000000 -#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT__SI 0x00000000 -#define IDDCCIF06_DBG_DCCIF_G__DBG_DCCIF_G__SHIFT__SI 0x00000000 -#define IDDCCIF07_DBG_DCCIF_H__DBG_DCCIF_H__SHIFT__SI 0x00000000 -#define IDDCCIF08_DBG_DCCIF_I__DBG_DCCIF_I__SHIFT__SI 0x00000000 -#define IDDCCIF09_DBG_DCCIF_J__DBG_DCCIF_J__SHIFT__SI 0x00000000 -#define IDDCCIF10_DBG_DCCIF_K__DBG_DCCIF_K__SHIFT__SI 0x00000000 -#define IDDCCIF11_DBG_DCCIF_L__DBG_DCCIF_L__SHIFT__SI 0x00000000 -#define IDSC_REG__CLK_SELECT__SHIFT__CI 0x0000001e -#define IDSC_REG__CMON_ADC_DOUT__SHIFT__CI 0x00000014 -#define IDSC_REG__CMON_ADC_MAX__SHIFT__CI 0x00000000 -#define IDSC_REG__CMON_ADC_MIN__SHIFT__CI 0x0000000a -#define IDSC_REG__FULL_TEST_MODE__SHIFT__CI 0x0000001f -#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT__SI__CI 0x00000008 -#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT__SI__CI 0x00000010 -#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT__SI__CI 0x00000003 -#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT__SI__CI 0x00000004 -#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT__SI__CI 0x00000000 -#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x00000008 -#define IH_CNTL__ENABLE_INTR__SHIFT 0x00000000 -#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0x0000000a -#define IH_CNTL__MC_SWAP__SHIFT 0x00000001 -#define IH_CNTL__MC_TRAN__SHIFT__SI__CI 0x00000003 -#define IH_CNTL__MC_VMID__SHIFT__CI__VI 0x00000019 -#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x0000000f -#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014 -#define IH_CNTL__RPTR_REARM__SHIFT 0x00000004 -#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x00000004 -#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x00000000 -#define IH_LEVEL_STATUS__DRM_STATUS__SHIFT 0x00000001 -#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x00000002 -#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x00000003 -#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT__CI__VI 0x00000005 -#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT__CI__VI 0x00000000 -#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT__CI__VI 0x00000000 -#define IH_PERFMON_CNTL__CLEAR0__SHIFT__CI__VI 0x00000001 -#define IH_PERFMON_CNTL__CLEAR1__SHIFT__CI__VI 0x00000009 -#define IH_PERFMON_CNTL__ENABLE0__SHIFT__CI__VI 0x00000000 -#define IH_PERFMON_CNTL__ENABLE1__SHIFT__CI__VI 0x00000008 -#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT__CI__VI 0x00000002 -#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define IH_PERF_CNTL__CLEAR0__SHIFT__SI 0x00000001 -#define IH_PERF_CNTL__CLEAR1__SHIFT__SI 0x00000009 -#define IH_PERF_CNTL__ENABLE0__SHIFT__SI 0x00000000 -#define IH_PERF_CNTL__ENABLE1__SHIFT__SI 0x00000008 -#define IH_PERF_CNTL__SELECT0__SHIFT__SI 0x00000002 -#define IH_PERF_CNTL__SELECT1__SHIFT__SI 0x0000000a -#define IH_PERF_COUNT0__PERF_COUNT__SHIFT__SI 0x00000000 -#define IH_PERF_COUNT1__PERF_COUNT__SHIFT__SI 0x00000000 -#define IH_RB_BASE__ADDR__SHIFT 0x00000000 -#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000006 -#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007 -#define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f -#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010 -#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008 -#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009 -#define IH_RB_RPTR__OFFSET__SHIFT 0x00000002 -#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000 -#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002 -#define IH_RB_WPTR__OFFSET__SHIFT 0x00000002 -#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000 -#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a -#define IH_STATUS__IDLE__SHIFT 0x00000000 -#define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001 -#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008 -#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009 -#define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006 -#define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007 -#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004 -#define IH_STATUS__RB_FULL__SHIFT 0x00000003 -#define IH_STATUS__RB_IDLE__SHIFT 0x00000002 -#define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005 -#define IH_VMID_0_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_10_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_11_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_12_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_13_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_14_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_15_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_1_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_2_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_3_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_4_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_5_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_6_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_7_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_8_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IH_VMID_9_LUT__PASID__SHIFT__CI__VI 0x00000000 -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT__SI 0x00000000 -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT__SI 0x00000000 -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT__SI \ - 0x0000001c -#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT__SI \ - 0x00000000 -#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT__SI 0x00000000 -#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT__SI 0x00000001 -#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT__SI 0x00000000 -#define IMPCTL_RESET__IMP_SW_RESET__SHIFT__CI__VI 0x00000000 -#define IM_INT_EN__CM_INT_EN__SHIFT__SI 0x00000002 -#define IM_INT_EN__DB_INT_EN__SHIFT__SI 0x00000006 -#define IM_INT_EN__IT_INT_EN__SHIFT__SI 0x00000004 -#define IM_INT_EN__MI_INT_EN__SHIFT__SI 0x00000001 -#define IM_INT_EN__MP_INT_EN__SHIFT__SI 0x00000005 -#define IM_INT_EN__PES_INT_EN__SHIFT__SI 0x00000007 -#define IM_INT_EN__RE_INT_EN__SHIFT__SI 0x00000003 -#define IM_INT_EN__RI_INT_EN__SHIFT__SI 0x00000000 -#define IM_INT_STAT__CM_INT__SHIFT__SI 0x00000002 -#define IM_INT_STAT__DB_INT__SHIFT__SI 0x00000006 -#define IM_INT_STAT__IT_INT__SHIFT__SI 0x00000004 -#define IM_INT_STAT__MI_INT__SHIFT__SI 0x00000001 -#define IM_INT_STAT__MP_INT__SHIFT__SI 0x00000005 -#define IM_INT_STAT__PES_INT__SHIFT__SI 0x00000007 -#define IM_INT_STAT__RE_INT__SHIFT__SI 0x00000003 -#define IM_INT_STAT__RI_INT__SHIFT__SI 0x00000000 -#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT__SI 0x00000000 -#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x00000000 -#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x00000009 -#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x00000008 -#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x00000001 -#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x00000000 -#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x00000004 -#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x00000003 -#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0x0000000d -#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT__SI 0x0000001e -#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT__SI 0x0000001f -#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE__SHIFT__SI 0x00000000 -#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x00000000 -#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x00000000 -#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT__SI 0x0000001e -#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT__SI 0x0000001f -#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS__SHIFT__SI 0x00000000 -#define INT_MASK__VBLANK_CP_SEL__SHIFT__SI 0x0000001e -#define INT_MASK__VBLANK_INT_MASK__SHIFT__SI 0x00000000 -#define INT_MASK__VLINE_INT_MASK__SHIFT__SI 0x00000004 -#define IOU_MISC_STATUS__IOC_GPU_DIS__SHIFT__CI__VI 0x00000000 -#define IOU_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define IOU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define IT_BUF_SIZE__PITCH__SHIFT__SI 0x00000004 -#define IT_CF_DAT__COMMAND_DAT__SHIFT__SI 0x00000000 -#define IT_CTL__FLUSH_MB__SHIFT__SI 0x0000001c -#define IT_CTL__MEM_TIMEOUT__SHIFT__SI 0x00000014 -#define IT_CTL__NSG_MODE__SHIFT__SI 0x00000004 -#define IT_CTL__STANDARD__SHIFT__SI 0x00000000 -#define IT_CTL__STD_VERSION__SHIFT__SI 0x00000010 -#define IT_CTL__SW_MRST__SHIFT__SI 0x0000001e -#define IT_CTL__SW_RRST__SHIFT__SI 0x0000001d -#define IT_CTL__SW_SRST__SHIFT__SI 0x0000001f -#define IT_CTL__TBYPS__SHIFT__SI 0x00000006 -#define IT_DEBUG_BUS__DAT__SHIFT__SI 0x00000000 -#define IT_DEBUG_INT_STAT__CTXT_READ_RDY__SHIFT__SI 0x00000002 -#define IT_DEBUG_INT_STAT__CTXT_READ_TIMEOUT__SHIFT__SI 0x00000005 -#define IT_DEBUG_INT_STAT__CTXT_WRITE_DONE__SHIFT__SI 0x00000003 -#define IT_DEBUG_INT_STAT__CTXT_WRITE_TIMEOUT__SHIFT__SI 0x00000006 -#define IT_DEBUG_INT_STAT__DONE__SHIFT__SI 0x00000000 -#define IT_DEBUG_INT_STAT__HOR_CHROMAPRED_ERR__SHIFT__SI 0x0000000d -#define IT_DEBUG_INT_STAT__HOR_PRED16_ERR__SHIFT__SI 0x0000000a -#define IT_DEBUG_INT_STAT__ILLEGAL_4X4_PREDMODE_ERR__SHIFT__SI 0x00000008 -#define IT_DEBUG_INT_STAT__ILLEGAL_CHROMAPRED_ERR__SHIFT__SI 0x0000000f -#define IT_DEBUG_INT_STAT__MB_PROC_DONE__SHIFT__SI 0x00000001 -#define IT_DEBUG_INT_STAT__MEM_READ_TIMEOUT__SHIFT__SI 0x00000004 -#define IT_DEBUG_INT_STAT__MEM_WRITE_TIMEOUT__SHIFT__SI 0x00000010 -#define IT_DEBUG_INT_STAT__PLANE_CHROMAPRED_ERR__SHIFT__SI 0x0000000c -#define IT_DEBUG_INT_STAT__PLANE_PRED16_ERR__SHIFT__SI 0x0000000b -#define IT_DEBUG_INT_STAT__RD_NEIGHBOUR_ERR__SHIFT__SI 0x00000007 -#define IT_DEBUG_INT_STAT__RE_IT_OVERFLOW_ERR__SHIFT__SI 0x00000012 -#define IT_DEBUG_INT_STAT__RE_IT_UNDERFLOW_ERR__SHIFT__SI 0x00000011 -#define IT_DEBUG_INT_STAT__VERT_CHROMAPRED_ERR__SHIFT__SI 0x0000000e -#define IT_DEBUG_INT_STAT__VERT_PRED16_ERR__SHIFT__SI 0x00000009 -#define IT_HW_DEBUG__DAT__SHIFT__SI 0x00000000 -#define IT_INTRA_HOR_ADR__HOR_ADR_RESERVE_HI__SHIFT__SI 0x0000001e -#define IT_INTRA_HOR_ADR__HOR_ADR_RESERVE_LO__SHIFT__SI 0x00000000 -#define IT_INTRA_HOR_ADR__INTRA_HOR_ADR__SHIFT__SI 0x00000006 -#define IT_INT_EN__CTXT_READ_RDY_EN__SHIFT__SI 0x00000002 -#define IT_INT_EN__CTXT_READ_TIMEOUT_EN__SHIFT__SI 0x00000005 -#define IT_INT_EN__CTXT_WRITE_DONE_EN__SHIFT__SI 0x00000003 -#define IT_INT_EN__CTXT_WRITE_TIMEOUT_EN__SHIFT__SI 0x00000006 -#define IT_INT_EN__DONE_EN__SHIFT__SI 0x00000000 -#define IT_INT_EN__HOR_CHROMAPRED_ERR_EN__SHIFT__SI 0x0000000d -#define IT_INT_EN__HOR_PRED16_ERR_EN__SHIFT__SI 0x0000000a -#define IT_INT_EN__ILLEGAL_4X4_PREDMODE_ERR_EN__SHIFT__SI 0x00000008 -#define IT_INT_EN__ILLEGAL_CHROMAPRED_ERR_EN__SHIFT__SI 0x0000000f -#define IT_INT_EN__MB_PROC_DONE_EN__SHIFT__SI 0x00000001 -#define IT_INT_EN__MEM_READ_TIMEOUT_EN__SHIFT__SI 0x00000004 -#define IT_INT_EN__MEM_WRITE_TIMEOUT_EN__SHIFT__SI 0x00000010 -#define IT_INT_EN__PLANE_CHROMAPRED_ERR_EN__SHIFT__SI 0x0000000c -#define IT_INT_EN__PLANE_PRED16_ERR_EN__SHIFT__SI 0x0000000b -#define IT_INT_EN__RD_NEIGHBOUR_ERR_EN__SHIFT__SI 0x00000007 -#define IT_INT_EN__RE_IT_OVERFLOW_ERR_EN__SHIFT__SI 0x00000012 -#define IT_INT_EN__RE_IT_UNDERFLOW_ERR_EN__SHIFT__SI 0x00000011 -#define IT_INT_EN__VERT_CHROMAPRED_ERR_EN__SHIFT__SI 0x0000000e -#define IT_INT_EN__VERT_PRED16_ERR_EN__SHIFT__SI 0x00000009 -#define IT_INT_STAT__CTXT_READ_RDY__SHIFT__SI 0x00000002 -#define IT_INT_STAT__CTXT_READ_TIMEOUT__SHIFT__SI 0x00000005 -#define IT_INT_STAT__CTXT_WRITE_DONE__SHIFT__SI 0x00000003 -#define IT_INT_STAT__CTXT_WRITE_TIMEOUT__SHIFT__SI 0x00000006 -#define IT_INT_STAT__DONE__SHIFT__SI 0x00000000 -#define IT_INT_STAT__HOR_CHROMAPRED_ERR__SHIFT__SI 0x0000000d -#define IT_INT_STAT__HOR_PRED16_ERR__SHIFT__SI 0x0000000a -#define IT_INT_STAT__ILLEGAL_4X4_PREDMODE_ERR__SHIFT__SI 0x00000008 -#define IT_INT_STAT__ILLEGAL_CHROMAPRED_ERR__SHIFT__SI 0x0000000f -#define IT_INT_STAT__MB_PROC_DONE__SHIFT__SI 0x00000001 -#define IT_INT_STAT__MEM_READ_TIMEOUT__SHIFT__SI 0x00000004 -#define IT_INT_STAT__MEM_WRITE_TIMEOUT__SHIFT__SI 0x00000010 -#define IT_INT_STAT__PLANE_CHROMAPRED_ERR__SHIFT__SI 0x0000000c -#define IT_INT_STAT__PLANE_PRED16_ERR__SHIFT__SI 0x0000000b -#define IT_INT_STAT__RD_NEIGHBOUR_ERR__SHIFT__SI 0x00000007 -#define IT_INT_STAT__RE_IT_OVERFLOW_ERR__SHIFT__SI 0x00000012 -#define IT_INT_STAT__RE_IT_UNDERFLOW_ERR__SHIFT__SI 0x00000011 -#define IT_INT_STAT__VERT_CHROMAPRED_ERR__SHIFT__SI 0x0000000e -#define IT_INT_STAT__VERT_PRED16_ERR__SHIFT__SI 0x00000009 -#define IT_LMA_ADR__LMA_ADR__SHIFT__SI 0x00000000 -#define IT_LMA_CTL__ACCESS_MODE__SHIFT__SI 0x00000000 -#define IT_LMA_CTL__AUTO_INCREMENT__SHIFT__SI 0x00000006 -#define IT_LMA_CTL__MEMORY_SELECT__SHIFT__SI 0x00000001 -#define IT_LMA_DAT__LMA_DAT__SHIFT__SI 0x00000000 -#define IT_PPS_INFO__CONSTRAINED_INTRA_PRED_FLAG__SHIFT__SI 0x00000000 -#define IT_PPS_INFO__FCM__SHIFT__SI 0x0000000d -#define IT_PPS_INFO__FMO__SHIFT__SI 0x0000000c -#define IT_PPS_INFO__INTERLACED__SHIFT__SI 0x0000000b -#define IT_PPS_INFO__NON_UNIFORM__SHIFT__SI 0x00000007 -#define IT_PPS_INFO__PQUANT__SHIFT__SI 0x00000001 -#define IT_PPS_INFO__PTYPE__SHIFT__SI 0x00000008 -#define IT_SLICE_INFO__MBAFF_FRAME_FLAG__SHIFT__SI 0x00000000 -#define IT_SPS_INFO__CHROMA_FORMAT_IDC__SHIFT__SI 0x0000001c -#define IT_SPS_INFO__PIC_HEIGHT__SHIFT__SI 0x00000010 -#define IT_SPS_INFO__PIC_WIDTH__SHIFT__SI 0x00000000 -#define IT_SPS_INFO__PROFILE__SHIFT__SI 0x0000001d -#define IT_SRAM_RM_CTL__IT_M032X064R2M01S00_RME__SHIFT__SI 0x00000009 -#define IT_SRAM_RM_CTL__IT_M032X064R2M01S00_RM__SHIFT__SI 0x00000005 -#define IT_SRAM_RM_CTL__IT_M128X016R2M01S00_RME__SHIFT__SI 0x00000013 -#define IT_SRAM_RM_CTL__IT_M128X016R2M01S00_RM__SHIFT__SI 0x0000000f -#define IT_SRAM_RM_CTL__IT_M224X008H1M08S00_RME__SHIFT__SI 0x00000004 -#define IT_SRAM_RM_CTL__IT_M224X008H1M08S00_RM__SHIFT__SI 0x00000000 -#define IT_SRAM_RM_CTL__IT_M384X010R2M04S00_RME__SHIFT__SI 0x0000000e -#define IT_SRAM_RM_CTL__IT_M384X010R2M04S00_RM__SHIFT__SI 0x0000000a -#define IT_SRAM_RM_CTL__IT_WRM__SHIFT__SI 0x00000014 -#define IT_STAT__CTXT_RD_BUSY__SHIFT__SI 0x00000003 -#define IT_STAT__DECODE_MBP_BUSY__SHIFT__SI 0x00000001 -#define IT_STAT__DECODE_TPACKET_BUSY__SHIFT__SI 0x00000000 -#define IT_STAT__IPRED_CHROMA_PEL_BUSY__SHIFT__SI 0x00000007 -#define IT_STAT__IPRED_CHROMA_PRED_BUSY__SHIFT__SI 0x00000008 -#define IT_STAT__IPRED_LUMA_PEL_BUSY__SHIFT__SI 0x00000005 -#define IT_STAT__IPRED_LUMA_PRED_BUSY__SHIFT__SI 0x00000006 -#define IT_STAT__OUTPUT_BUSY__SHIFT__SI 0x00000009 -#define IT_STAT__PREFETCH_BUSY__SHIFT__SI 0x0000000a -#define IT_STAT__RUN_BUSY__SHIFT__SI 0x00000002 -#define IT_STAT__TRANS_CHROMA_BUSY__SHIFT__SI 0x00000004 -#define IT_STAT__VC1_COMPUTE_BUSY__SHIFT__SI 0x0000000b -#define IT_STAT__VC1_MEMWRITE_BUSY__SHIFT__SI 0x0000000c -#define KEFUSE0__RESERVED__SHIFT 0x00000000 -#define KEFUSE1__RESERVED__SHIFT 0x00000000 -#define KEFUSE2__RESERVED__SHIFT 0x00000000 -#define KEFUSE3__RESERVED__SHIFT 0x00000000 -#define KHFS0__RESERVED__SHIFT 0x00000000 -#define KHFS1__RESERVED__SHIFT 0x00000000 -#define KHFS2__RESERVED__SHIFT 0x00000000 -#define KHFS3__RESERVED__SHIFT 0x00000000 -#define KSESSION0__RESERVED__SHIFT 0x00000000 -#define KSESSION1__RESERVED__SHIFT 0x00000000 -#define KSESSION2__RESERVED__SHIFT 0x00000000 -#define KSESSION3__RESERVED__SHIFT 0x00000000 -#define KSIG0__RESERVED__SHIFT 0x00000000 -#define KSIG1__RESERVED__SHIFT 0x00000000 -#define KSIG2__RESERVED__SHIFT 0x00000000 -#define KSIG3__RESERVED__SHIFT 0x00000000 -#define LATENCY__LATENCY_TIMER__SHIFT 0x00000000 -#define LB_DCP_WRITE__ID92_DATA_AVAIL__SHIFT__SI 0x00000007 -#define LB_DCP_WRITE__ID92_DCP_DISP_NUM__SHIFT__SI 0x00000012 -#define LB_DCP_WRITE__ID92_DCP_TAG__SHIFT__SI 0x0000000c -#define LB_DCP_WRITE__ID92_EOC_W__SHIFT__SI 0x0000000f -#define LB_DCP_WRITE__ID92_EOC__SHIFT__SI 0x00000013 -#define LB_DCP_WRITE__ID92_FIFO_READ_SEL__SHIFT__SI 0x0000000a -#define LB_DCP_WRITE__ID92_IGNORE__SHIFT__SI 0x00000002 -#define LB_DCP_WRITE__ID92_LB_DISP_NUM__SHIFT__SI 0x00000011 -#define LB_DCP_WRITE__ID92_REQ__SHIFT__SI 0x00000010 -#define LB_DCP_WRITE__ID92_ROW_ADR__SHIFT__SI 0x00000001 -#define LB_DCP_WRITE__ID92_ROW_READ_SEL__SHIFT__SI 0x00000009 -#define LB_DCP_WRITE__ID92_SEND__SHIFT__SI 0x00000003 -#define LB_DCP_WRITE__ID92_SOF1__SHIFT__SI 0x00000000 -#define LB_DCP_WRITE__ID92_SOF2__SHIFT__SI 0x0000000b -#define LB_DCP_WRITE__ID92_WEN__SHIFT__SI 0x00000008 -#define LB_DCP_WRITE__ID92_WORD_ADR__SHIFT__SI 0x00000004 -#define LB_DCP_WRITE__ID92_WRITE_ADR__SHIFT__SI 0x00000014 -#define LB_DEBUG_ID__LB_DEBUG_ID__SHIFT__SI 0x00000000 -#define LB_DEBUG_PRE_ECO__DISABLE_LB_MEM_ADR_CLAMPING__SHIFT__SI 0x0000000c -#define LB_DEBUG_PRE_ECO__DISABLE_LB_RTR_USE_MEM_LEVEL_OLD__SHIFT__SI 0x00000005 -#define LB_DEBUG_PRE_ECO__DISABLE_NEW_LEVEL__SHIFT__SI 0x00000004 -#define LB_DEBUG_PRE_ECO__DISABLE_NEW_WCONTROL_INTERLEAVE__SHIFT__SI 0x00000000 -#define LB_DEBUG_PRE_ECO__DISABLE_NEW_WPOINTER__SHIFT__SI 0x00000008 -#define LB_DEBUG_PRE_ECO__DISABLE_RND_SCR_SCALE_EN__SHIFT__SI 0x00000010 -#define LB_DEBUG_PRE_ECO__LB_DEBUG_PRE_ECO__SHIFT__SI 0x00000011 -#define LB_DEBUG__LB_DEBUG__SHIFT__SI 0x00000000 -#define LB_DISP1_ALU__ID95_DISP1_EOL_Q__SHIFT__SI 0x00000000 -#define LB_DISP1_ALU__ID95_DISP1_LC_FRAME_BUSY__SHIFT__SI 0x00000004 -#define LB_DISP1_ALU__ID95_DISP1_LC_FRAME_DONE__SHIFT__SI 0x00000008 -#define LB_DISP1_ALU__ID95_DISP1_LC_LINE_BUSY__SHIFT__SI 0x00000003 -#define LB_DISP1_ALU__ID95_DISP1_LC_LINE_DONE__SHIFT__SI 0x00000007 -#define LB_DISP1_ALU__ID95_DISP1_RT_FRAME_CAL_BUSY__SHIFT__SI 0x00000002 -#define LB_DISP1_ALU__ID95_DISP1_RT_FRAME_CAL_DONE__SHIFT__SI 0x00000006 -#define LB_DISP1_ALU__ID95_DISP1_RT_LINE_CAL_BUSY__SHIFT__SI 0x00000001 -#define LB_DISP1_ALU__ID95_DISP1_RT_LINE_CAL_DONE__SHIFT__SI 0x00000005 -#define LB_DISP1_ALU__ID95_DISP1_SOF__SHIFT__SI 0x0000000c -#define LB_DISP1_ALU__ID95_DISP1_STATE__SHIFT__SI 0x00000009 -#define LB_DISP1_ALU__ID95_DISP1_SUM__SHIFT__SI 0x00000011 -#define LB_DISP1_ALU__ID95_DISP1_S__SHIFT__SI 0x0000000d -#define LB_DISP1_PARAM__ID97_DISP1_END_SIZE__SHIFT__SI 0x00000010 -#define LB_DISP1_PARAM__ID97_DISP1_END_TAP_CYCLE__SHIFT__SI 0x0000001d -#define LB_DISP1_PARAM__ID97_DISP1_LAST_LINE__SHIFT__SI 0x0000001e -#define LB_DISP1_PARAM__ID97_DISP1_NUMS_LINE_AVAIL__SHIFT__SI 0x0000000b -#define LB_DISP1_PARAM__ID97_DISP1_PITCH__SHIFT__SI 0x00000000 -#define LB_DISP1_PARAM__ID97_DISP1_READ_CYCLE__SHIFT__SI 0x0000000f -#define LB_DISP1_PARAM__ID97_DISP1_READ_PIXEL_COUNTER__SHIFT__SI 0x00000018 -#define LB_DISP1_PARAM__ID97_DISP1_SEND_FOR_THE_NXT_LINE__SHIFT__SI 0x0000001f -#define LB_DISP1_PARAM__ID97_DISP1_SEND__SHIFT__SI 0x0000001c -#define LB_DISP1_PARAM__ID97_DISP1_SOF__SHIFT__SI 0x00000013 -#define LB_DISP1_PARAM__ID97_DISP1_WRITE_CYCLE__SHIFT__SI 0x0000000e -#define LB_DISP1_PARAM__ID97_DISP1_WRITE_PIXEL_COUNTER__SHIFT__SI 0x00000014 -#define LB_DISP1_REQ__ID90_DISP1_CHUNCK_LOC_STATE__SHIFT__SI 0x00000009 -#define LB_DISP1_REQ__ID90_DISP1_DCP_ACK__SHIFT__SI 0x0000001c -#define LB_DISP1_REQ__ID90_DISP1_EOL__SHIFT__SI 0x00000003 -#define LB_DISP1_REQ__ID90_DISP1_INIT__SHIFT__SI 0x0000001e -#define LB_DISP1_REQ__ID90_DISP1_NUM_LINE_TOBE_SERVICED__SHIFT__SI 0x00000005 -#define LB_DISP1_REQ__ID90_DISP1_PULSE_ALL_LINE_SERV__SHIFT__SI 0x0000001f -#define LB_DISP1_REQ__ID90_DISP1_READ_POINTER__SHIFT__SI 0x0000000e -#define LB_DISP1_REQ__ID90_DISP1_REQ_POINTER__SHIFT__SI 0x00000014 -#define LB_DISP1_REQ__ID90_DISP1_REQ__SHIFT__SI 0x00000008 -#define LB_DISP1_REQ__ID90_DISP1_RESET_REQ__SHIFT__SI 0x0000001b -#define LB_DISP1_REQ__ID90_DISP1_SOF__SHIFT__SI 0x00000004 -#define LB_DISP1_REQ__ID90_DISP1_TAG__SHIFT__SI 0x0000000b -#define LB_DISP1_REQ__ID90_DISP1_TAP_SHIFT__SHIFT__SI 0x00000000 -#define LB_DISP2_ALU__ID96_DISP2_EOL_Q__SHIFT__SI 0x00000000 -#define LB_DISP2_ALU__ID96_DISP2_LC_FRAME_BUSY__SHIFT__SI 0x00000004 -#define LB_DISP2_ALU__ID96_DISP2_LC_FRAME_DONE__SHIFT__SI 0x00000008 -#define LB_DISP2_ALU__ID96_DISP2_LC_LINE_BUSY__SHIFT__SI 0x00000003 -#define LB_DISP2_ALU__ID96_DISP2_LC_LINE_DONE__SHIFT__SI 0x00000007 -#define LB_DISP2_ALU__ID96_DISP2_RT_FRAME_CAL_BUSY__SHIFT__SI 0x00000002 -#define LB_DISP2_ALU__ID96_DISP2_RT_FRAME_CAL_DONE__SHIFT__SI 0x00000006 -#define LB_DISP2_ALU__ID96_DISP2_RT_LINE_CAL_BUSY__SHIFT__SI 0x00000001 -#define LB_DISP2_ALU__ID96_DISP2_RT_LINE_CAL_DONE__SHIFT__SI 0x00000005 -#define LB_DISP2_ALU__ID96_DISP2_SOF__SHIFT__SI 0x0000000c -#define LB_DISP2_ALU__ID96_DISP2_STATE__SHIFT__SI 0x00000009 -#define LB_DISP2_ALU__ID96_DISP2_SUM__SHIFT__SI 0x00000011 -#define LB_DISP2_ALU__ID96_DISP2_S__SHIFT__SI 0x0000000d -#define LB_DISP2_PARAM__ID98_DISP2_END_SIZE__SHIFT__SI 0x00000010 -#define LB_DISP2_PARAM__ID98_DISP2_END_TAP_CYCLE__SHIFT__SI 0x0000001d -#define LB_DISP2_PARAM__ID98_DISP2_LAST_LINE__SHIFT__SI 0x0000001e -#define LB_DISP2_PARAM__ID98_DISP2_NUMS_LINE_AVAIL__SHIFT__SI 0x0000000b -#define LB_DISP2_PARAM__ID98_DISP2_PITCH__SHIFT__SI 0x00000000 -#define LB_DISP2_PARAM__ID98_DISP2_READ_CYCLE__SHIFT__SI 0x0000000f -#define LB_DISP2_PARAM__ID98_DISP2_READ_PIXEL_COUNTER__SHIFT__SI 0x00000018 -#define LB_DISP2_PARAM__ID98_DISP2_SEND_FOR_THE_NXT_LINE__SHIFT__SI 0x0000001f -#define LB_DISP2_PARAM__ID98_DISP2_SEND__SHIFT__SI 0x0000001c -#define LB_DISP2_PARAM__ID98_DISP2_SOF__SHIFT__SI 0x00000013 -#define LB_DISP2_PARAM__ID98_DISP2_WRITE_CYCLE__SHIFT__SI 0x0000000e -#define LB_DISP2_PARAM__ID98_DISP2_WRITE_PIXEL_COUNTER__SHIFT__SI 0x00000014 -#define LB_DISP2_REQ__ID91_DISP2_CHUNCK_LOC_STATE__SHIFT__SI 0x00000009 -#define LB_DISP2_REQ__ID91_DISP2_DCP_ACK__SHIFT__SI 0x0000001c -#define LB_DISP2_REQ__ID91_DISP2_EOL__SHIFT__SI 0x00000003 -#define LB_DISP2_REQ__ID91_DISP2_INIT__SHIFT__SI 0x0000001e -#define LB_DISP2_REQ__ID91_DISP2_NUM_LINE_TOBE_SERVICED__SHIFT__SI 0x00000005 -#define LB_DISP2_REQ__ID91_DISP2_PULSE_ALL_LINE_SERV__SHIFT__SI 0x0000001f -#define LB_DISP2_REQ__ID91_DISP2_READ_POINTER__SHIFT__SI 0x0000000e -#define LB_DISP2_REQ__ID91_DISP2_REQ_POINTER__SHIFT__SI 0x00000014 -#define LB_DISP2_REQ__ID91_DISP2_REQ__SHIFT__SI 0x00000008 -#define LB_DISP2_REQ__ID91_DISP2_RESET_REQ__SHIFT__SI 0x0000001b -#define LB_DISP2_REQ__ID91_DISP2_SOF__SHIFT__SI 0x00000004 -#define LB_DISP2_REQ__ID91_DISP2_TAG__SHIFT__SI 0x0000000b -#define LB_DISP2_REQ__ID91_DISP2_TAP_SHIFT__SHIFT__SI 0x00000000 -#define LB_MAX_REQ_OUTSTANDING__LB_MAX_REQ_OUTSTANDING__SHIFT__SI 0x00000000 -#define LB_MCLK_CHG_DBG1__IDA3_DC_CG_DISP1_WM_MCLK_CHG_CNT_OVERFLOW__SHIFT__SI 0x0000001f -#define LB_MCLK_CHG_DBG1__IDA3_DC_CG_DISP1_WM_MCLK_CHG_MAX_CNT__SHIFT__SI 0x00000000 -#define LB_MCLK_CHG_DBG1__IDA3_DC_CG_DISP1_WM_MCLK_CHG_MIN_CNT__SHIFT__SI 0x00000010 -#define LB_MCLK_CHG_DBG2__IDA4_DC_CG_DISP2_WM_MCLK_CHG_CNT_OVERFLOW__SHIFT__SI 0x0000001f -#define LB_MCLK_CHG_DBG2__IDA4_DC_CG_DISP2_WM_MCLK_CHG_MAX_CNT__SHIFT__SI 0x00000000 -#define LB_MCLK_CHG_DBG2__IDA4_DC_CG_DISP2_WM_MCLK_CHG_MIN_CNT__SHIFT__SI 0x00000010 -#define LB_MVP_DEBUG1__IDE7_CRTC1_LB_MVP_AFR_HSYNC_SWITCH_DONE__SHIFT__SI 0x0000000d -#define LB_MVP_DEBUG1__IDE7_D1_AFR_FIFO_EMPTY_COND__SHIFT__SI 0x0000001e -#define LB_MVP_DEBUG1__IDE7_D1_AFR_FIFO_EMPTY__SHIFT__SI 0x0000001c -#define LB_MVP_DEBUG1__IDE7_D1_FLIP_NOW_OCCURRED1__SHIFT__SI 0x0000000a -#define LB_MVP_DEBUG1__IDE7_D1_FLIP_NOW__SHIFT__SI 0x00000016 -#define LB_MVP_DEBUG1__IDE7_D1_FLIP_REQUEST__SHIFT__SI 0x00000010 -#define LB_MVP_DEBUG1__IDE7_D1_HSYNC_FLIP_NOW__SHIFT__SI 0x00000006 -#define LB_MVP_DEBUG1__IDE7_D1_SWAP_LOCK_IN__SHIFT__SI 0x00000014 -#define LB_MVP_DEBUG1__IDE7_D1_SWAP_LOCK_OUT__SHIFT__SI 0x00000002 -#define LB_MVP_DEBUG1__IDE7_D1_SWAP_LOCK__SHIFT__SI 0x00000000 -#define LB_MVP_DEBUG1__IDE7_D1_UPDATE_PENDING__SHIFT__SI 0x00000012 -#define LB_MVP_DEBUG1__IDE7_D1_VSYNC_FLIP_NOW__SHIFT__SI 0x00000008 -#define LB_MVP_DEBUG1__IDE7_D1_V_UPDATE__SHIFT__SI 0x00000018 -#define LB_MVP_DEBUG1__IDE7_D2_AFR_FIFO_EMPTY_COND__SHIFT__SI 0x0000001f -#define LB_MVP_DEBUG1__IDE7_D2_AFR_FIFO_EMPTY__SHIFT__SI 0x0000001d -#define LB_MVP_DEBUG1__IDE7_D2_FLIP_NOW_OCCURRED1__SHIFT__SI 0x0000000b -#define LB_MVP_DEBUG1__IDE7_D2_FLIP_NOW__SHIFT__SI 0x00000017 -#define LB_MVP_DEBUG1__IDE7_D2_FLIP_REQUEST__SHIFT__SI 0x00000011 -#define LB_MVP_DEBUG1__IDE7_D2_HSYNC_FLIP_NOW__SHIFT__SI 0x00000007 -#define LB_MVP_DEBUG1__IDE7_D2_SWAP_LOCK_IN__SHIFT__SI 0x00000015 -#define LB_MVP_DEBUG1__IDE7_D2_SWAP_LOCK_OUT__SHIFT__SI 0x00000003 -#define LB_MVP_DEBUG1__IDE7_D2_SWAP_LOCK__SHIFT__SI 0x00000001 -#define LB_MVP_DEBUG1__IDE7_D2_UPDATE_PENDING__SHIFT__SI 0x00000013 -#define LB_MVP_DEBUG1__IDE7_D2_VSYNC_FLIP_NOW__SHIFT__SI 0x00000009 -#define LB_MVP_DEBUG1__IDE7_D2_V_UPDATE__SHIFT__SI 0x00000019 -#define LB_MVP_DEBUG1__IDE7_LATCH_D1_Y_AFTER_VBLANK__SHIFT__SI 0x0000000e -#define LB_MVP_DEBUG1__IDE7_LATCH_D2_Y_AFTER_VBLANK__SHIFT__SI 0x0000000f -#define LB_MVP_DEBUG1__IDE7_LB_CRTC1_MVP_AFR_HSYNC_SWITCH__SHIFT__SI 0x0000000c -#define LB_MVP_DEBUG1__IDE7_LB_DCP_D1_ALLOW_FLIP__SHIFT__SI 0x00000004 -#define LB_MVP_DEBUG1__IDE7_LB_DCP_D2_ALLOW_FLIP__SHIFT__SI 0x00000005 -#define LB_MVP_DEBUG1__IDE7_WTRIG_POST_FLD_D1_MVP_AFR_FLIP_MODE__SHIFT__SI 0x0000001a -#define LB_MVP_DEBUG1__IDE7_WTRIG_POST_FLD_D2_MVP_AFR_FLIP_MODE__SHIFT__SI 0x0000001b -#define LB_MVP_DEBUG2__IDE8_CRTC1_LB_MVP_FLIP_LINE_NUMBER__SHIFT__SI 0x00000000 -#define LB_MVP_DEBUG2__IDE8_CRTC2_LB_MVP_FLIP_LINE_NUMBER__SHIFT__SI 0x0000000d -#define LB_MVP_DEBUG3__IDE9_D1_FLIP_REQUEST__SHIFT__SI 0x0000001e -#define LB_MVP_DEBUG3__IDE9_D2_FLIP_REQUEST__SHIFT__SI 0x0000001f -#define LB_MVP_DEBUG3__IDE9_LB_CRTC1_MVP_FLIP_LINE_NUMBER__SHIFT__SI 0x00000000 -#define LB_MVP_DEBUG3__IDE9_LB_CRTC1_MVP_FLIP_QUEUE_STATUS__SHIFT__SI 0x0000001a -#define LB_MVP_DEBUG3__IDE9_LB_CRTC2_MVP_FLIP_LINE_NUMBER__SHIFT__SI 0x0000000d -#define LB_MVP_DEBUG3__IDE9_LB_CRTC2_MVP_FLIP_QUEUE_STATUS__SHIFT__SI 0x0000001c -#define LB_MVP_DEBUG4__IDEA_LAST_D1_Y__SHIFT__SI 0x00000000 -#define LB_MVP_DEBUG4__IDEA_LAST_D2_Y__SHIFT__SI 0x0000000d -#define LB_MVP_DEBUG5__IDEB_D1_MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT__SI 0x00000000 -#define LB_MVP_DEBUG5__IDEB_D2_MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT__SI 0x00000004 -#define LB_MVP_DEBUG5__IDEB_LB_DCP_MVP_REQ__SHIFT__SI 0x00000017 -#define LB_MVP_DEBUG5__IDEB_LB_MVP_LAST_CHUNK__SHIFT__SI 0x00000015 -#define LB_MVP_DEBUG5__IDEB_LB_MVP_REQ_DISPNUM__SHIFT__SI 0x00000016 -#define LB_MVP_DEBUG5__IDEB_LB_MVP_Y__SHIFT__SI 0x00000008 -#define LB_NEW_LEVEL1__ID81_DISP1_3RD_LINE_WRITE_LEVEL__SHIFT__SI 0x00000012 -#define LB_NEW_LEVEL1__ID81_DISP1_NEXT_LINE_SEND_DONE__SHIFT__SI 0x0000001c -#define LB_NEW_LEVEL1__ID81_DISP1_READ_WRITE_LEVEL__SHIFT__SI 0x00000000 -#define LB_NEW_LEVEL1__ID81_DISP1_SEND_FOR_NEXT_LINE__SHIFT__SI 0x0000001e -#define LB_NEW_LEVEL1__ID81_DISP1_SEND_FOR_THIRD_LINE__SHIFT__SI 0x0000001f -#define LB_NEW_LEVEL1__ID81_DISP1_THIRD_LINE_SEND_DONE__SHIFT__SI 0x0000001d -#define LB_NEW_LEVEL1__ID81_DISP1_THIS_LINE_SEND_DONE__SHIFT__SI 0x0000001b -#define LB_NEW_LEVEL1__ID81_DISP1_WRITE_ONLY_LEVEL__SHIFT__SI 0x00000009 -#define LB_NEW_LEVEL2__ID82_DISP2_3RD_LINE_WRITE_LEVEL__SHIFT__SI 0x00000012 -#define LB_NEW_LEVEL2__ID82_DISP2_NEXT_LINE_SEND_DONE__SHIFT__SI 0x0000001c -#define LB_NEW_LEVEL2__ID82_DISP2_READ_WRITE_LEVEL__SHIFT__SI 0x00000000 -#define LB_NEW_LEVEL2__ID82_DISP2_SEND_FOR_NEXT_LINE__SHIFT__SI 0x0000001e -#define LB_NEW_LEVEL2__ID82_DISP2_SEND_FOR_THIRD_LINE__SHIFT__SI 0x0000001f -#define LB_NEW_LEVEL2__ID82_DISP2_THIRD_LINE_SEND_DONE__SHIFT__SI 0x0000001d -#define LB_NEW_LEVEL2__ID82_DISP2_THIS_LINE_SEND_DONE__SHIFT__SI 0x0000001b -#define LB_NEW_LEVEL2__ID82_DISP2_WRITE_ONLY_LEVEL__SHIFT__SI 0x00000009 -#define LB_NEW_STATUS1__ID80_CURSOR_ICON_ALLOW_STUTTER__SHIFT__SI 0x0000001a -#define LB_NEW_STATUS1__ID80_DC_CG_DISP1_VBI__SHIFT__SI 0x0000001e -#define LB_NEW_STATUS1__ID80_DC_CG_DISP2_VBI__SHIFT__SI 0x0000001f -#define LB_NEW_STATUS1__ID80_DC_CG_WM_HIGH_OCCURRED__SHIFT__SI 0x00000017 -#define LB_NEW_STATUS1__ID80_DC_CG_WM_HIGH_STATUS__SHIFT__SI 0x00000016 -#define LB_NEW_STATUS1__ID80_DC_CG_WM_MCHANGE_OCCURRED__SHIFT__SI 0x0000001d -#define LB_NEW_STATUS1__ID80_DC_CG_WM_MCHANGE_STATUS__SHIFT__SI 0x0000001c -#define LB_NEW_STATUS1__ID80_DISP1_MODE_PREFETCH__SHIFT__SI 0x00000000 -#define LB_NEW_STATUS1__ID80_DISP1_NEW_LINE_RECEIVED__SHIFT__SI 0x00000018 -#define LB_NEW_STATUS1__ID80_DISP1_NUM_PARTITIONS__SHIFT__SI 0x00000002 -#define LB_NEW_STATUS1__ID80_DISP1_REQ_FIFO_LEVEL__SHIFT__SI 0x0000000a -#define LB_NEW_STATUS1__ID80_DISP2_MODE_PREFETCH__SHIFT__SI 0x00000001 -#define LB_NEW_STATUS1__ID80_DISP2_NEW_LINE_RECEIVED__SHIFT__SI 0x00000019 -#define LB_NEW_STATUS1__ID80_DISP2_NUM_PARTITIONS__SHIFT__SI 0x00000006 -#define LB_NEW_STATUS1__ID80_DISP2_REQ_FIFO_LEVEL__SHIFT__SI 0x00000010 -#define LB_SCL1_READ__ID93_DISP1_BLACK_STATE__SHIFT__SI 0x00000011 -#define LB_SCL1_READ__ID93_DISP1_EOL__SHIFT__SI 0x00000001 -#define LB_SCL1_READ__ID93_DISP1_FIRST_LINE__SHIFT__SI 0x0000000d -#define LB_SCL1_READ__ID93_DISP1_LAST_LINE__SHIFT__SI 0x00000010 -#define LB_SCL1_READ__ID93_DISP1_LINE_SEL__SHIFT__SI 0x0000000a -#define LB_SCL1_READ__ID93_DISP1_NUM_TAP_IGNORE__SHIFT__SI 0x00000005 -#define LB_SCL1_READ__ID93_DISP1_READ_ADR__SHIFT__SI 0x00000015 -#define LB_SCL1_READ__ID93_DISP1_RTR__SHIFT__SI 0x00000008 -#define LB_SCL1_READ__ID93_DISP1_RTS__SHIFT__SI 0x00000009 -#define LB_SCL1_READ__ID93_DISP1_SOF__SHIFT__SI 0x00000000 -#define LB_SCL1_READ__ID93_DISP1_TAP_SHIFT__SHIFT__SI 0x00000002 -#define LB_SCL1_READ__ID93_DISP1_TAP__SHIFT__SI 0x00000012 -#define LB_SCL2_READ__ID94_DISP2_BLACK_STATE__SHIFT__SI 0x00000011 -#define LB_SCL2_READ__ID94_DISP2_EOL__SHIFT__SI 0x00000001 -#define LB_SCL2_READ__ID94_DISP2_FIRST_LINE__SHIFT__SI 0x0000000d -#define LB_SCL2_READ__ID94_DISP2_LAST_LINE__SHIFT__SI 0x00000010 -#define LB_SCL2_READ__ID94_DISP2_LINE_SEL__SHIFT__SI 0x0000000a -#define LB_SCL2_READ__ID94_DISP2_NUM_TAP_IGNORE__SHIFT__SI 0x00000005 -#define LB_SCL2_READ__ID94_DISP2_READ_ADR__SHIFT__SI 0x00000015 -#define LB_SCL2_READ__ID94_DISP2_RTR__SHIFT__SI 0x00000008 -#define LB_SCL2_READ__ID94_DISP2_RTS__SHIFT__SI 0x00000009 -#define LB_SCL2_READ__ID94_DISP2_SOF__SHIFT__SI 0x00000000 -#define LB_SCL2_READ__ID94_DISP2_TAP_SHIFT__SHIFT__SI 0x00000002 -#define LB_SCL2_READ__ID94_DISP2_TAP__SHIFT__SI 0x00000012 -#define LB_SLOW_REQ_VAL__LB_SLOW_REQ_VAL__SHIFT__SI 0x00000000 -#define LB_STUTTER_DBG1__IDA0_DC_CG_DISP1_WM_HIGH_CNT_OVERFLOW__SHIFT__SI 0x0000001f -#define LB_STUTTER_DBG1__IDA0_DC_CG_DISP1_WM_HIGH_MAX_CNT__SHIFT__SI 0x00000000 -#define LB_STUTTER_DBG1__IDA0_DC_CG_DISP1_WM_HIGH_MIN_CNT__SHIFT__SI 0x00000010 -#define LB_STUTTER_DBG2__IDA1_DC_CG_DISP2_WM_HIGH_CNT_OVERFLOW__SHIFT__SI 0x0000001f -#define LB_STUTTER_DBG2__IDA1_DC_CG_DISP2_WM_HIGH_MAX_CNT__SHIFT__SI 0x00000000 -#define LB_STUTTER_DBG2__IDA1_DC_CG_DISP2_WM_HIGH_MIN_CNT__SHIFT__SI 0x00000010 -#define LB_STUTTER_DBG3__IDA2_D1_WM_ABOVE_STUTTER_ON__SHIFT__SI 0x0000001a -#define LB_STUTTER_DBG3__IDA2_D1_WM_BELOW_STUTTER_OFF__SHIFT__SI 0x00000018 -#define LB_STUTTER_DBG3__IDA2_D2_WM_ABOVE_STUTTER_ON__SHIFT__SI 0x0000001b -#define LB_STUTTER_DBG3__IDA2_D2_WM_BELOW_STUTTER_OFF__SHIFT__SI 0x00000019 -#define LB_STUTTER_DBG3__IDA2_DC_CG_DISP1_WM_HIGH__SHIFT__SI 0x00000000 -#define LB_STUTTER_DBG3__IDA2_DC_CG_DISP2_WM_HIGH__SHIFT__SI 0x0000000c -#define LB_STUTTER_DBG3__IDA2_DISP1_COMP_LEVEL_ALLOW_STOP__SHIFT__SI 0x00000008 -#define LB_STUTTER_DBG3__IDA2_DISP1_CURSOR_ICON_ALLOW_STOP__SHIFT__SI 0x00000006 -#define LB_STUTTER_DBG3__IDA2_DISP1_FID_ALLOW_STOP__SHIFT__SI 0x00000007 -#define LB_STUTTER_DBG3__IDA2_DISP1_LEVEL_ALLOW_STOP__SHIFT__SI 0x00000002 -#define LB_STUTTER_DBG3__IDA2_DISP1_NEW_LINE_RECVD__SHIFT__SI 0x00000005 -#define LB_STUTTER_DBG3__IDA2_DISP1_OUTPUT_LINE_RECVD__SHIFT__SI 0x00000001 -#define LB_STUTTER_DBG3__IDA2_DISP1_UNCOMP_LINE_RECVD__SHIFT__SI 0x00000003 -#define LB_STUTTER_DBG3__IDA2_DISP1_WM_MCLK_CHG__SHIFT__SI 0x0000001c -#define LB_STUTTER_DBG3__IDA2_DISP2_COMP_LEVEL_ALLOW_STOP__SHIFT__SI 0x00000014 -#define LB_STUTTER_DBG3__IDA2_DISP2_CURSOR_ICON_ALLOW_STOP__SHIFT__SI 0x00000012 -#define LB_STUTTER_DBG3__IDA2_DISP2_FID_ALLOW_STOP__SHIFT__SI 0x00000013 -#define LB_STUTTER_DBG3__IDA2_DISP2_LEVEL_ALLOW_STOP__SHIFT__SI 0x0000000e -#define LB_STUTTER_DBG3__IDA2_DISP2_NEW_LINE_RECVD__SHIFT__SI 0x00000011 -#define LB_STUTTER_DBG3__IDA2_DISP2_OUTPUT_LINE_RECVD__SHIFT__SI 0x0000000d -#define LB_STUTTER_DBG3__IDA2_DISP2_UNCOMP_LINE_RECVD__SHIFT__SI 0x0000000f -#define LB_STUTTER_DBG3__IDA2_DISP2_WM_MCLK_CHG__SHIFT__SI 0x0000001d -#define LB_STUTTER_DBG3__IDA2_LINE_RECEIVED1__SHIFT__SI 0x0000000a -#define LB_STUTTER_DBG3__IDA2_LINE_RECEIVED2__SHIFT__SI 0x00000016 -#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT__SI 0x00000000 -#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define LB_URGENCY__ID99_DISP1_URGENCY_FLAG__SHIFT__SI 0x00000000 -#define LB_URGENCY__ID99_DISP1_URGLEVEL__SHIFT__SI 0x00000001 -#define LB_URGENCY__ID99_DISP2_URGENCY_FLAG__SHIFT__SI 0x00000008 -#define LB_URGENCY__ID99_DISP2_URGLEVEL__SHIFT__SI 0x00000009 -#define LB_URGENCY__ID99_LB_DCP_URGENCY_FLAG__SHIFT__SI 0x00000010 -#define LB_URGENCY__ID99_LB_DCP_URGLEVEL_DEBUG__SHIFT__SI 0x00000019 -#define LB_URGENCY__ID99_LB_DCP_URGLEVEL__SHIFT__SI 0x00000011 -#define LB_URGENT_LEVEL_CNTL__CURR_PRIORITY_MARK__SHIFT__SI 0x00000000 -#define LB_URGENT_LEVEL_CNTL__LB_MAX_URGENT_WHEN_UNDERFLOW__SHIFT__SI 0x0000001f -#define LB_URGENT_LEVEL_CNTL__LB_URGENT_LEVEL_SEL__SHIFT__SI 0x0000000f -#define LCAC_CPL_CB_CNTL__CPL_CB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_CB_CNTL__CPL_CB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_CB_OVR_SEL__CPL_CB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_CB_OVR_VAL__CPL_CB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT__CI 0x00000000 -#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT__CI 0x00000001 -#define LCAC_CPL_DB_CNTL__CPL_DB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_DB_CNTL__CPL_DB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_DB_OVR_SEL__CPL_DB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_DB_OVR_VAL__CPL_DB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_LDS_CNTL__CPL_LDS_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_LDS_CNTL__CPL_LDS_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_LDS_OVR_SEL__CPL_LDS_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_LDS_OVR_VAL__CPL_LDS_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_MC_CNTL__CPL_MC_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_MC_CNTL__CPL_MC_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_MC_OVR_SEL__CPL_MC_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_MC_OVR_VAL__CPL_MC_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT__CI 0x00000000 -#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT__CI 0x00000000 -#define LCAC_CPL_PA_CNTL__CPL_PA_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_PA_CNTL__CPL_PA_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_PA_OVR_SEL__CPL_PA_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_PA_OVR_VAL__CPL_PA_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SC_CNTL__CPL_SC_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_SC_CNTL__CPL_SC_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_SC_OVR_SEL__CPL_SC_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SC_OVR_VAL__CPL_SC_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SPI_CNTL__CPL_SPI_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_SPI_CNTL__CPL_SPI_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_SPI_OVR_SEL__CPL_SPI_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SPI_OVR_VAL__CPL_SPI_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SQ_CNTL__CPL_SQ_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_SQ_CNTL__CPL_SQ_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_SQ_OVR_SEL__CPL_SQ_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SQ_OVR_VAL__CPL_SQ_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SX_CNTL__CPL_SX_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_SX_CNTL__CPL_SX_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_SX_OVR_SEL__CPL_SX_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_SX_OVR_VAL__CPL_SX_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_TA_CNTL__CPL_TA_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_TA_CNTL__CPL_TA_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_TA_OVR_SEL__CPL_TA_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_TA_OVR_VAL__CPL_TA_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_TCC_CNTL__CPL_TCC_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_TCC_CNTL__CPL_TCC_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_TCC_OVR_SEL__CPL_TCC_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_TCC_OVR_VAL__CPL_TCC_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_TCP_CNTL__CPL_TCP_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_TCP_CNTL__CPL_TCP_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_TCP_OVR_SEL__CPL_TCP_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_TCP_OVR_VAL__CPL_TCP_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_CPL_VGT_CNTL__CPL_VGT_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_CPL_VGT_CNTL__CPL_VGT_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_CPL_VGT_OVR_SEL__CPL_VGT_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_CPL_VGT_OVR_VAL__CPL_VGT_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT__SI__CI 0x00000000 -#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT__SI__CI 0x00000001 -#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT__SI__CI 0x00000000 -#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT__SI__CI 0x00000001 -#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT__SI__CI 0x00000000 -#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT__SI__CI 0x00000001 -#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT__SI__CI 0x00000000 -#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT__SI__CI 0x00000001 -#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT__SI__CI 0x00000000 -#define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX0_CB_CNTL__SX0_CB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX0_CB_CNTL__SX0_CB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX0_CB_OVR_SEL__SX0_CB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX0_CB_OVR_VAL__SX0_CB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT__CI 0x00000000 -#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT__CI 0x00000001 -#define LCAC_SX0_DB_CNTL__SX0_DB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX0_DB_CNTL__SX0_DB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX0_DB_OVR_SEL__SX0_DB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX0_DB_OVR_VAL__SX0_DB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX0_LDS_CNTL__SX0_LDS_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX0_LDS_CNTL__SX0_LDS_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX0_LDS_OVR_SEL__SX0_LDS_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX0_LDS_OVR_VAL__SX0_LDS_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT__CI 0x00000000 -#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT__CI 0x00000000 -#define LCAC_SX0_TA_CNTL__SX0_TA_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX0_TA_CNTL__SX0_TA_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX0_TA_OVR_SEL__SX0_TA_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX0_TA_OVR_VAL__SX0_TA_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX0_TCC_CNTL__SX0_TCC_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX0_TCC_CNTL__SX0_TCC_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX0_TCC_OVR_SEL__SX0_TCC_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX0_TCC_OVR_VAL__SX0_TCC_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX0_TCP_CNTL__SX0_TCP_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX0_TCP_CNTL__SX0_TCP_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX0_TCP_OVR_SEL__SX0_TCP_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX0_TCP_OVR_VAL__SX0_TCP_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX1_CB_CNTL__SX1_CB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX1_CB_CNTL__SX1_CB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX1_CB_OVR_SEL__SX1_CB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX1_CB_OVR_VAL__SX1_CB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX1_CNTL__SX1_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_SX1_CNTL__SX1_ENABLE__SHIFT__CI 0x00000000 -#define LCAC_SX1_CNTL__SX1_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_SX1_CNTL__SX1_THRESHOLD__SHIFT__CI 0x00000001 -#define LCAC_SX1_DB_CNTL__SX1_DB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX1_DB_CNTL__SX1_DB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX1_DB_OVR_SEL__SX1_DB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX1_DB_OVR_VAL__SX1_DB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX1_LDS_CNTL__SX1_LDS_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX1_LDS_CNTL__SX1_LDS_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX1_LDS_OVR_SEL__SX1_LDS_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX1_LDS_OVR_VAL__SX1_LDS_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX1_OVR_SEL__SX1_OVR_SEL__SHIFT__CI 0x00000000 -#define LCAC_SX1_OVR_VAL__SX1_OVR_VAL__SHIFT__CI 0x00000000 -#define LCAC_SX1_TA_CNTL__SX1_TA_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX1_TA_CNTL__SX1_TA_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX1_TA_OVR_SEL__SX1_TA_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX1_TA_OVR_VAL__SX1_TA_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX1_TCC_CNTL__SX1_TCC_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX1_TCC_CNTL__SX1_TCC_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX1_TCC_OVR_SEL__SX1_TCC_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX1_TCC_OVR_VAL__SX1_TCC_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX1_TCP_CNTL__SX1_TCP_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX1_TCP_CNTL__SX1_TCP_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX1_TCP_OVR_SEL__SX1_TCP_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX1_TCP_OVR_VAL__SX1_TCP_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX2_CB_CNTL__SX2_CB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX2_CB_CNTL__SX2_CB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX2_CB_OVR_SEL__SX2_CB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX2_CB_OVR_VAL__SX2_CB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX2_CNTL__SX2_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_SX2_CNTL__SX2_ENABLE__SHIFT__CI 0x00000000 -#define LCAC_SX2_CNTL__SX2_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_SX2_CNTL__SX2_THRESHOLD__SHIFT__CI 0x00000001 -#define LCAC_SX2_DB_CNTL__SX2_DB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX2_DB_CNTL__SX2_DB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX2_DB_OVR_SEL__SX2_DB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX2_DB_OVR_VAL__SX2_DB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX2_LDS_CNTL__SX2_LDS_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX2_LDS_CNTL__SX2_LDS_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX2_LDS_OVR_SEL__SX2_LDS_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX2_LDS_OVR_VAL__SX2_LDS_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX2_OVR_SEL__SX2_OVR_SEL__SHIFT__CI 0x00000000 -#define LCAC_SX2_OVR_VAL__SX2_OVR_VAL__SHIFT__CI 0x00000000 -#define LCAC_SX2_TA_CNTL__SX2_TA_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX2_TA_CNTL__SX2_TA_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX2_TA_OVR_SEL__SX2_TA_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX2_TA_OVR_VAL__SX2_TA_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX2_TCC_CNTL__SX2_TCC_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX2_TCC_CNTL__SX2_TCC_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX2_TCC_OVR_SEL__SX2_TCC_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX2_TCC_OVR_VAL__SX2_TCC_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX2_TCP_CNTL__SX2_TCP_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX2_TCP_CNTL__SX2_TCP_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX2_TCP_OVR_SEL__SX2_TCP_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX2_TCP_OVR_VAL__SX2_TCP_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX3_CB_CNTL__SX3_CB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX3_CB_CNTL__SX3_CB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX3_CB_OVR_SEL__SX3_CB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX3_CB_OVR_VAL__SX3_CB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX3_CNTL__SX3_BLOCK_ID__SHIFT__CI 0x00000011 -#define LCAC_SX3_CNTL__SX3_ENABLE__SHIFT__CI 0x00000000 -#define LCAC_SX3_CNTL__SX3_SIGNAL_ID__SHIFT__CI 0x00000016 -#define LCAC_SX3_CNTL__SX3_THRESHOLD__SHIFT__CI 0x00000001 -#define LCAC_SX3_DB_CNTL__SX3_DB_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX3_DB_CNTL__SX3_DB_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX3_DB_OVR_SEL__SX3_DB_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX3_DB_OVR_VAL__SX3_DB_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX3_LDS_CNTL__SX3_LDS_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX3_LDS_CNTL__SX3_LDS_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX3_LDS_OVR_SEL__SX3_LDS_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX3_LDS_OVR_VAL__SX3_LDS_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX3_OVR_SEL__SX3_OVR_SEL__SHIFT__CI 0x00000000 -#define LCAC_SX3_OVR_VAL__SX3_OVR_VAL__SHIFT__CI 0x00000000 -#define LCAC_SX3_TA_CNTL__SX3_TA_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX3_TA_CNTL__SX3_TA_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX3_TA_OVR_SEL__SX3_TA_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX3_TA_OVR_VAL__SX3_TA_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX3_TCC_CNTL__SX3_TCC_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX3_TCC_CNTL__SX3_TCC_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX3_TCC_OVR_SEL__SX3_TCC_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX3_TCC_OVR_VAL__SX3_TCC_OVR_VAL__SHIFT__SI 0x00000000 -#define LCAC_SX3_TCP_CNTL__SX3_TCP_ENABLE__SHIFT__SI 0x00000000 -#define LCAC_SX3_TCP_CNTL__SX3_TCP_THRESHOLD__SHIFT__SI 0x00000001 -#define LCAC_SX3_TCP_OVR_SEL__SX3_TCP_OVR_SEL__SHIFT__SI 0x00000000 -#define LCAC_SX3_TCP_OVR_VAL__SX3_TCP_OVR_VAL__SHIFT__SI 0x00000000 -#define LCLK_ACTIVITY_CNT_CNTL__START_ACTIVITY_CNT__SHIFT__CI__VI 0x00000000 -#define LCLK_ACTIVITY_CNT_STATUS__ACTIVITY_CNT_VALID__SHIFT__CI__VI 0x0000001f -#define LCLK_ACTIVITY_CNT_STATUS__ACTIVITY_CNT__SHIFT__CI__VI 0x00000000 -#define LCLK_AM_CNTL__ACTIVITY_CNT_RST__SHIFT__CI__VI 0x00000000 -#define LCLK_AM_CNTL__BUSY_CNT_RESOLUTION__SHIFT__CI__VI 0x00000006 -#define LCLK_AM_CNTL__BUSY_CNT_SEL__SHIFT__CI__VI 0x00000003 -#define LCLK_AM_CNTL__EN_BIF_CNT__SHIFT__CI__VI 0x00000008 -#define LCLK_AM_CNTL__EN_ORB_DS_CNT__SHIFT__CI__VI 0x0000000a -#define LCLK_AM_CNTL__EN_ORB_US_CNT__SHIFT__CI__VI 0x00000009 -#define LCLK_AM_CNTL__PERIOD_CNT_RST__SHIFT__CI__VI 0x00000001 -#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT__CI__VI 0x00000001 -#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT__CI__VI 0x00000014 -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT__CI__VI 0x0000000c -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT__CI__VI 0x0000000b -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT__CI__VI 0x0000000a -#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT__CI__VI 0x0000000d -#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT__CI__VI 0x00000002 -#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT__CI__VI 0x0000000e -#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT__CI__VI 0x00000011 -#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT__CI__VI 0x00000010 -#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT__CI__VI 0x00000013 -#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT__CI__VI 0x00000012 -#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT__CI__VI 0x0000000f -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT__CI__VI 0x00000006 -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT__CI__VI 0x00000007 -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT__CI__VI 0x00000008 -#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT__CI__VI 0x00000009 -#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT__CI 0x00000015 -#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT__CI__VI 0x00000000 -#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT__CI__VI 0x00000004 -#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT__CI__VI 0x00000005 -#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT__CI__VI 0x00000000 -#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT__CI__VI 0x0000001f -#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT__CI__VI 0x00000004 -#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT__CI__VI 0x00000003 -#define LCLK_PERIOD_CNT_STATUS__PERIOD_CNT__SHIFT__CI__VI 0x00000000 -#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT__CI__VI 0x00000008 -#define LINK_CAP2__RESERVED__SHIFT__CI__VI 0x00000009 -#define LINK_CAP2__RESERVED__SHIFT__SI 0x00000000 -#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT__CI__VI 0x00000001 -#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT__CI__VI 0x00000016 -#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x00000012 -#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x00000014 -#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0x0000000c -#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0x0000000f -#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x00000015 -#define LINK_CAP__LINK_SPEED__SHIFT 0x00000000 -#define LINK_CAP__LINK_WIDTH__SHIFT 0x00000004 -#define LINK_CAP__PM_SUPPORT__SHIFT 0x0000000a -#define LINK_CAP__PORT_NUMBER__SHIFT 0x00000018 -#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x00000013 -#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0x0000000c -#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0x0000000b -#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x00000004 -#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0x0000000a -#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x00000005 -#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x00000006 -#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x00000000 -#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x00000007 -#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x00000008 -#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x00000006 -#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x00000007 -#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x00000009 -#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0x0000000b -#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0x0000000a -#define LINK_CNTL__LINK_DIS__SHIFT 0x00000004 -#define LINK_CNTL__PM_CONTROL__SHIFT 0x00000000 -#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x00000003 -#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x00000005 -#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x00000000 -#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT__CI__VI 0x00000001 -#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT__CI__VI 0x00000002 -#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT__CI__VI 0x00000003 -#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT__CI__VI 0x00000004 -#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT__CI__VI 0x00000005 -#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x00000000 -#define LINK_STATUS__DL_ACTIVE__SHIFT 0x0000000d -#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x0000000f -#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x0000000e -#define LINK_STATUS__LINK_TRAINING__SHIFT 0x0000000b -#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x00000004 -#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x0000000c -#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT__CI 0x00000000 -#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT__CI 0x00000001 -#define LPML_SCALAR_1__Lmpl1__SHIFT__CI 0x00000000 -#define LPML_SCALAR_1__Lmpl2__SHIFT__CI 0x00000006 -#define LPML_SCALAR_1__Lmpl3__SHIFT__CI 0x0000000c -#define LPML_SCALAR_1__Lmpl4__SHIFT__CI 0x00000012 -#define LPML_SCALAR_1__Lmpl5__SHIFT__CI 0x00000018 -#define LPML_SCALAR_1__RESERVED__SHIFT__CI__VI 0x0000001e -#define LPML_SCALAR_2__Lmpl0__SHIFT__CI 0x0000000c -#define LPML_SCALAR_2__Lmpl6__SHIFT__CI 0x00000000 -#define LPML_SCALAR_2__Lmpl7__SHIFT__CI 0x00000006 -#define LPML_SCALAR_2__RESERVED__SHIFT__CI__VI 0x00000012 -#define LPMV_SCALAR_1__Lmpv1__SHIFT__CI 0x00000000 -#define LPMV_SCALAR_1__Lmpv2__SHIFT__CI 0x00000006 -#define LPMV_SCALAR_1__Lmpv3__SHIFT__CI 0x0000000c -#define LPMV_SCALAR_1__Lmpv4__SHIFT__CI 0x00000012 -#define LPMV_SCALAR_1__Lmpv5__SHIFT__CI 0x00000018 -#define LPMV_SCALAR_1__RESERVED__SHIFT__CI__VI 0x0000001e -#define LPMV_SCALAR_2__Lmpv0__SHIFT__CI 0x0000000c -#define LPMV_SCALAR_2__Lmpv6__SHIFT__CI 0x00000000 -#define LPMV_SCALAR_2__Lmpv7__SHIFT__CI 0x00000006 -#define LPMV_SCALAR_2__Lpm_Trigger__SHIFT__CI__VI 0x0000001f -#define LPMV_SCALAR_2__RESERVED__SHIFT__CI__VI 0x00000012 -#define LUMA_BOT_ADDR__Y_BOT_BASE__SHIFT__SI 0x00000000 -#define LUMA_TOP_ADDR__Y_TOP_BASE__SHIFT__SI 0x00000000 -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_CLK_PREMPHEN__SHIFT__SI 0x00000000 -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_CLK_PREMPH_DT__SHIFT__SI 0x00000008 -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_CLK_PREMPH_STR__SHIFT__SI 0x00000004 -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_DAT_PREMPHEN__SHIFT__SI 0x00000010 -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_DAT_PREMPH_DT__SHIFT__SI 0x00000018 -#define LVDSA_PREEMPHASIS_CONTROL__LVDSA_DAT_PREMPH_STR__SHIFT__SI 0x00000014 -#define LVDSA_TRANSMITTER_ADJUST__LVDSA_NTXVS__SHIFT__SI 0x00000008 -#define LVDSA_TRANSMITTER_ADJUST__LVDSA_PTXVS__SHIFT__SI 0x00000010 -#define LVDSA_TRANSMITTER_ADJUST__LVDSA_TXOP__SHIFT__SI 0x00000000 -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_CLK_PREMPHEN__SHIFT__SI 0x00000000 -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_CLK_PREMPH_DT__SHIFT__SI 0x00000008 -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_CLK_PREMPH_STR__SHIFT__SI 0x00000004 -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_DAT_PREMPHEN__SHIFT__SI 0x00000010 -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_DAT_PREMPH_DT__SHIFT__SI 0x00000018 -#define LVDSB_PREEMPHASIS_CONTROL__LVDSB_DAT_PREMPH_STR__SHIFT__SI 0x00000014 -#define LVDSB_TRANSMITTER_ADJUST__LVDSB_NTXVS__SHIFT__SI 0x00000008 -#define LVDSB_TRANSMITTER_ADJUST__LVDSB_PTXVS__SHIFT__SI 0x00000010 -#define LVDSB_TRANSMITTER_ADJUST__LVDSB_TXOP__SHIFT__SI 0x00000000 -#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT__SI 0x00000000 -#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT__SI 0x00000004 -#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT__SI 0x00000008 -#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT__SI 0x0000000a -#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT__SI 0x00000009 -#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT__SI 0x0000000c -#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT__SI 0x00000012 -#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT__SI 0x00000010 -#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT__SI 0x00000011 -#define LVTMA_PWRSEQ_CNTL__LVTMA_BGSLEEP__SHIFT__SI 0x00000005 -#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT__SI 0x00000019 -#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT__SI 0x0000001a -#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT__SI 0x00000018 -#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT__SI 0x00000011 -#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT__SI 0x00000012 -#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT__SI 0x00000010 -#define LVTMA_PWRSEQ_CNTL__LVTMA_PLL_ENABLE_PWRSEQ_MASK__SHIFT__SI 0x00000002 -#define LVTMA_PWRSEQ_CNTL__LVTMA_PLL_RESET_PWRSEQ_MASK__SHIFT__SI 0x00000003 -#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT__SI 0x00000001 -#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT__SI 0x00000000 -#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT__SI 0x00000004 -#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT__SI 0x00000009 -#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT__SI 0x0000000a -#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT__SI 0x00000008 -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT__SI 0x00000010 -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT__SI 0x00000018 -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT__SI 0x00000000 -#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT__SI 0x00000008 -#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT__SI 0x00000000 -#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT__SI 0x00000010 -#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT__SI 0x00000000 -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT__SI 0x00000003 -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT__SI 0x00000001 -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT__SI 0x00000004 -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT__SI 0x00000008 -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT__SI 0x00000002 -#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT__SI 0x00000000 -#define LX0__RESERVED__SHIFT 0x00000000 -#define LX1__RESERVED__SHIFT 0x00000000 -#define LX2__RESERVED__SHIFT 0x00000000 -#define LX3__RESERVED__SHIFT 0x00000000 -#define MAJOR_VERSION__MAJOR_VERSION__SHIFT__SI 0x00000000 -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT__SI 0x00000000 -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT__SI 0x00000008 -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT__SI 0x00000010 -#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT__SI 0x00000018 -#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT__SI 0x00000000 -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT__SI 0x00000000 -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT__SI 0x00000008 -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT__SI 0x00000010 -#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT__SI 0x00000018 -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT__SI 0x00000000 -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT__SI 0x00000008 -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT__SI 0x00000010 -#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT__SI 0x00000018 -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT__SI 0x00000000 -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT__SI 0x00000008 -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT__SI 0x00000010 -#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT__SI 0x00000018 -#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x00000010 -#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x00000000 -#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT__SI 0x00000000 -#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT__SI 0x00000010 -#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT__SI 0x00000000 -#define MAX_LATENCY__MAX_LAT__SHIFT 0x00000000 -#define MB_DONE__MB_X__SHIFT__SI 0x00000000 -#define MB_DONE__MB_Y__SHIFT__SI 0x00000010 -#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT__SI 0x00000004 -#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT__SI 0x00000010 -#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT__SI 0x00000000 -#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT__SI 0x0000001e -#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT__SI 0x0000001f -#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT__SI 0x00000018 -#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT__SI 0x00000008 -#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT__SI 0x00000000 -#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT__SI 0x00000008 -#define MCLK_AM_CNTL__CLEAR_MCLK_AM_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define MCLK_AM_CNTL__CLEAR_MCLK_AM_SCLK_CNT__SHIFT__CI__VI 0x00000001 -#define MCLK_AM_CNTL__START_MCLK_AM_BUSY_CNT__SHIFT__CI__VI 0x00000002 -#define MCLK_AM_CNTL__START_MCLK_AM_SCLK_CNT__SHIFT__CI__VI 0x00000003 -#define MCLK_AM_PERIOD_CNT__AM_MCLK_PERIOD_CNT__SHIFT__CI__VI 0x00000000 -#define MCLK_AM_READ_CNT__AM_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define MCLK_AM_WRITE_CNT__AM_BUSY_CNT__SHIFT__CI__VI 0x00000000 -#define MCLK_CHG_CNT__MCLK_CHG_MARK_A__SHIFT__SI 0x00000000 -#define MCLK_CHG_CNT__MCLK_CHG_MARK_B__SHIFT__SI 0x00000010 -#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT__SI__CI 0x00000018 -#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT__SI__CI 0x00000006 -#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT__SI__CI 0x00000000 -#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT__SI__CI 0x00000007 -#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT__SI__CI 0x00000008 -#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT__SI__CI 0x00000010 -#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT__SI__CI 0x00000009 -#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT__SI__CI 0x00000011 -#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x00000000 -#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x00000004 -#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0x0000000c -#define MC_ARB_ADDR_SWIZ0__A10__SHIFT__CI__VI 0x00000008 -#define MC_ARB_ADDR_SWIZ0__A11__SHIFT__CI__VI 0x0000000c -#define MC_ARB_ADDR_SWIZ0__A12__SHIFT__CI__VI 0x00000010 -#define MC_ARB_ADDR_SWIZ0__A13__SHIFT__CI__VI 0x00000014 -#define MC_ARB_ADDR_SWIZ0__A14__SHIFT__CI__VI 0x00000018 -#define MC_ARB_ADDR_SWIZ0__A15__SHIFT__CI__VI 0x0000001c -#define MC_ARB_ADDR_SWIZ0__A8__SHIFT__CI__VI 0x00000000 -#define MC_ARB_ADDR_SWIZ0__A9__SHIFT__CI__VI 0x00000004 -#define MC_ARB_ADDR_SWIZ1__A16__SHIFT__CI__VI 0x00000000 -#define MC_ARB_ADDR_SWIZ1__A17__SHIFT__CI__VI 0x00000004 -#define MC_ARB_ADDR_SWIZ1__A18__SHIFT__CI__VI 0x00000008 -#define MC_ARB_ADDR_SWIZ1__A19__SHIFT__CI__VI 0x0000000c -#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT__CI__VI 0x00000010 -#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT__CI__VI 0x00000013 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT__CI__VI 0x00000001 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT__CI__VI 0x00000002 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT__CI__VI 0x00000003 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT__CI__VI 0x00000004 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT__CI__VI 0x00000005 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT__CI__VI 0x00000006 -#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT__CI__VI 0x00000007 -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT__CI__VI 0x00000008 -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT__CI__VI 0x00000009 -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT__CI__VI 0x0000000a -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT__CI__VI 0x0000000b -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT__CI__VI 0x0000000c -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT__CI__VI 0x0000000d -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT__CI__VI 0x0000000e -#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT__CI__VI 0x0000000f -#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x00000018 -#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x00000019 -#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x0000001a -#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x0000001b -#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x0000001c -#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x0000001d -#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x0000001e -#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x0000001f -#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x00000010 -#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x00000011 -#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x00000012 -#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x00000013 -#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x00000014 -#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x00000015 -#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x00000016 -#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x00000017 -#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x00000000 -#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x00000002 -#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x00000004 -#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x00000006 -#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x00000008 -#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0x0000000a -#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0x0000000c -#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0x0000000e -#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x00000018 -#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x00000019 -#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x0000001a -#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x0000001b -#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x0000001c -#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x0000001d -#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x0000001e -#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x0000001f -#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x00000010 -#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x00000011 -#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x00000012 -#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x00000013 -#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x00000014 -#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x00000015 -#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x00000016 -#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x00000017 -#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x00000000 -#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x00000002 -#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x00000004 -#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x00000006 -#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x00000008 -#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0x0000000a -#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0x0000000c -#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0x0000000e -#define MC_ARB_BANKMAP__BANK0__SHIFT 0x00000000 -#define MC_ARB_BANKMAP__BANK1__SHIFT 0x00000004 -#define MC_ARB_BANKMAP__BANK2__SHIFT 0x00000008 -#define MC_ARB_BANKMAP__BANK3__SHIFT 0x0000000c -#define MC_ARB_BANKMAP__RANK__SHIFT 0x00000010 -#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x00000000 -#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x00000005 -#define MC_ARB_BURST_TIME__STATE2__SHIFT 0x0000000a -#define MC_ARB_BURST_TIME__STATE3__SHIFT 0x0000000f -#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT__CI__VI 0x00000014 -#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT__CI__VI 0x00000015 -#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT__CI__VI 0x00000016 -#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT__CI__VI 0x00000017 -#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT__CI__VI 0x00000004 -#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT__CI__VI 0x00000005 -#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT__CI__VI 0x00000006 -#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT__CI__VI 0x00000007 -#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT__CI__VI 0x00000001 -#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT__CI__VI 0x00000002 -#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT__CI__VI 0x00000003 -#define MC_ARB_BUSY_STATUS__POP0__SHIFT__CI__VI 0x0000000c -#define MC_ARB_BUSY_STATUS__POP1__SHIFT__CI__VI 0x0000000d -#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT__CI__VI 0x00000012 -#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT__CI__VI 0x00000013 -#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT__CI__VI 0x0000001c -#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT__CI__VI 0x0000001d -#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT__CI__VI 0x0000001e -#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT__CI__VI 0x0000001f -#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT__CI__VI 0x00000010 -#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT__CI__VI 0x00000011 -#define MC_ARB_BUSY_STATUS__RTT0__SHIFT__CI__VI 0x0000001a -#define MC_ARB_BUSY_STATUS__RTT1__SHIFT__CI__VI 0x0000001b -#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT__CI__VI 0x0000000e -#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT__CI__VI 0x0000000f -#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT__CI 0x00000018 -#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT__CI 0x00000019 -#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT__CI__VI 0x00000008 -#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT__CI__VI 0x00000009 -#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT__CI__VI 0x0000000a -#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT__CI__VI 0x0000000b -#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0x0000000d -#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x00000000 -#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x00000001 -#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x00000007 -#define MC_ARB_CG__ARB_CG_REQ__SHIFT__SI 0x00000010 -#define MC_ARB_CG__ARB_CG_RESP__SHIFT__SI 0x00000018 -#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x00000000 -#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x00000008 -#define MC_ARB_CG__RSV_0__SHIFT__CI__VI 0x00000010 -#define MC_ARB_CG__RSV_1__SHIFT__CI__VI 0x00000018 -#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x00000018 -#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x00000000 -#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x00000008 -#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x00000010 -#define MC_ARB_DRAM_TIMING2_2__BUS_TURN__SHIFT__SI 0x00000018 -#define MC_ARB_DRAM_TIMING2_2__RAS2RAS__SHIFT__SI 0x00000000 -#define MC_ARB_DRAM_TIMING2_2__RP__SHIFT__SI 0x00000008 -#define MC_ARB_DRAM_TIMING2_2__WRPLUSRP__SHIFT__SI 0x00000010 -#define MC_ARB_DRAM_TIMING2_3__BUS_TURN__SHIFT__SI 0x00000018 -#define MC_ARB_DRAM_TIMING2_3__RAS2RAS__SHIFT__SI 0x00000000 -#define MC_ARB_DRAM_TIMING2_3__RP__SHIFT__SI 0x00000008 -#define MC_ARB_DRAM_TIMING2_3__WRPLUSRP__SHIFT__SI 0x00000010 -#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x00000018 -#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x00000000 -#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x00000008 -#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x00000010 -#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x00000000 -#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x00000008 -#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x00000010 -#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x00000018 -#define MC_ARB_DRAM_TIMING_2__ACTRD__SHIFT__SI 0x00000000 -#define MC_ARB_DRAM_TIMING_2__ACTWR__SHIFT__SI 0x00000008 -#define MC_ARB_DRAM_TIMING_2__RASMACTRD__SHIFT__SI 0x00000010 -#define MC_ARB_DRAM_TIMING_2__RASMACTWR__SHIFT__SI 0x00000018 -#define MC_ARB_DRAM_TIMING_3__ACTRD__SHIFT__SI 0x00000000 -#define MC_ARB_DRAM_TIMING_3__ACTWR__SHIFT__SI 0x00000008 -#define MC_ARB_DRAM_TIMING_3__RASMACTRD__SHIFT__SI 0x00000010 -#define MC_ARB_DRAM_TIMING_3__RASMACTWR__SHIFT__SI 0x00000018 -#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x00000000 -#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x00000008 -#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x00000010 -#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x00000018 -#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT__CI__VI 0x00000007 -#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x00000004 -#define MC_ARB_FED_CNTL__MODE__SHIFT 0x00000000 -#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT__CI__VI 0x00000005 -#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT__CI__VI 0x00000006 -#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x00000002 -#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x00000000 -#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x00000004 -#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a -#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x00000008 -#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x00000009 -#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x00000000 -#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x00000004 -#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a -#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x00000008 -#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x00000009 -#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x00000000 -#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x00000008 -#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x00000010 -#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x00000018 -#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x00000008 -#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x00000010 -#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x00000018 -#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x00000000 -#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x00000003 -#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x00000002 -#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x00000000 -#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x00000005 -#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT__CI__VI 0x00000004 -#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT__CI__VI 0x00000005 -#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT__CI 0x00000007 -#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT__CI__VI 0x00000006 -#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x00000000 -#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x00000008 -#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0x0000000c -#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x00000000 -#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x00000004 -#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0x0000000a -#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0x0000000e -#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x00000002 -#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x00000006 -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT__CI__VI 0x00000018 -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT__CI__VI 0x0000001c -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT__CI__VI 0x00000010 -#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT__CI__VI 0x00000014 -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT__CI__VI 0x00000019 -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT__CI__VI 0x0000001d -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT__CI__VI 0x00000011 -#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT__CI__VI 0x00000015 -#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x00000003 -#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x00000007 -#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0x0000000b -#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT__CI__VI 0x0000000f -#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT__CI__VI 0x00000012 -#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT__CI__VI 0x00000016 -#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT__CI__VI 0x0000001a -#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x00000009 -#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0x0000000d -#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x00000001 -#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x00000005 -#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0x0000000e -#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0x0000000f -#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x00000001 -#define MC_ARB_GECC2__ENABLE__SHIFT 0x00000000 -#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x00000005 -#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x00000007 -#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x00000003 -#define MC_ARB_GECC2__READ_ERR__SHIFT 0x0000000b -#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT__CI__VI 0x00000016 -#define MC_ARB_GECC2__WRADDR_CONV__SHIFT__CI__VI 0x00000015 -#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT__CI__VI 0x00000009 -#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT__CI__VI 0x0000000b -#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT__CI__VI 0x0000000e -#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT__CI__VI 0x00000016 -#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT__CI__VI 0x0000000c -#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT__CI__VI 0x0000000a -#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT__CI__VI 0x00000009 -#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT__CI__VI 0x0000000b -#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT__CI__VI 0x0000000e -#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT__CI__VI 0x00000016 -#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT__CI__VI 0x0000000c -#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT__CI__VI 0x0000000a -#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT__CI__VI 0x00000000 -#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT__CI__VI 0x00000008 -#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT__CI__VI 0x00000010 -#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT__CI__VI 0x00000018 -#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x00000000 -#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x00000008 -#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x00000010 -#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x00000018 -#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x00000000 -#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x00000008 -#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x00000010 -#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x00000018 -#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x00000000 -#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x00000008 -#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x00000010 -#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x00000018 -#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x00000000 -#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x00000008 -#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x00000010 -#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x00000018 -#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x00000015 -#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x00000012 -#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 -#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x00000014 -#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x00000010 -#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x00000008 -#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x00000000 -#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x00000011 -#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x00000015 -#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x00000012 -#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 -#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x00000014 -#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x00000010 -#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x00000008 -#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x00000000 -#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x00000011 -#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT__CI__VI 0x00000000 -#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT__CI__VI 0x00000008 -#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT__CI__VI 0x00000012 -#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT__CI__VI 0x00000013 -#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT__CI__VI 0x00000010 -#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT__CI__VI 0x00000011 -#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT__CI__VI 0x00000000 -#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT__CI__VI 0x00000000 -#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x00000010 -#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x00000000 -#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT__CI__VI 0x00000011 -#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x00000008 -#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x0000001d -#define MC_ARB_MISC2__GECC_RST__SHIFT 0x00000013 -#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x00000014 -#define MC_ARB_MISC2__GECC__SHIFT 0x00000012 -#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0x0000000b -#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0x0000000d -#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0x0000000c -#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0x0000000e -#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x0000001c -#define MC_ARB_MISC2__SCRAMBLE_2D__SHIFT 0x00000003 -#define MC_ARB_MISC2__SCRAMBLE_ENABLE__SHIFT 0x00000000 -#define MC_ARB_MISC2__SCRAMBLE_MIX__SHIFT 0x00000001 -#define MC_ARB_MISC2__SCRAMBLE_WITH_ADDR__SHIFT 0x00000002 -#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x0000001e -#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x00000015 -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x00000006 -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x00000007 -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x00000008 -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x00000009 -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0x0000000a -#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x00000005 -#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x0000001f -#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x00000019 -#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT__CI__VI 0x00000000 -#define MC_ARB_MISC3__TBD_FIELD__SHIFT__CI 0x00000001 -#define MC_ARB_MISC__ACPURG_STALL__SHIFT__CI__VI 0x0000001f -#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x00000014 -#define MC_ARB_MISC__CALI_RATES__SHIFT 0x00000015 -#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x00000003 -#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x00000017 -#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x00000018 -#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x00000019 -#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x0000001a -#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT__CI__VI 0x0000001e -#define MC_ARB_MISC__HARSHNESS__SHIFT 0x0000000b -#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x00000001 -#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x00000013 -#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x00000000 -#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x00000002 -#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT__CI 0x00000000 -#define MC_ARB_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT__SI 0x0000001c -#define MC_ARB_PERF_MON_CNTL0__START_MODE__SHIFT__SI 0x00000018 -#define MC_ARB_PERF_MON_CNTL0__START_THRESH__SHIFT__SI 0x00000000 -#define MC_ARB_PERF_MON_CNTL0__STOP_MODE__SHIFT__SI 0x0000001a -#define MC_ARB_PERF_MON_CNTL0__STOP_THRESH__SHIFT__SI 0x0000000c -#define MC_ARB_PERF_MON_CNTL1__MON0_ID__SHIFT__SI 0x00000012 -#define MC_ARB_PERF_MON_CNTL1__MON1_ID__SHIFT__SI 0x00000018 -#define MC_ARB_PERF_MON_CNTL1__START_TRIG_ID__SHIFT__SI 0x00000006 -#define MC_ARB_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT__SI 0x0000000c -#define MC_ARB_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT__SI 0x00000000 -#define MC_ARB_PERF_MON_CNTL2__MON0_ID_HI__SHIFT__SI 0x00000010 -#define MC_ARB_PERF_MON_CNTL2__MON1_ID_HI__SHIFT__SI 0x00000012 -#define MC_ARB_PERF_MON_CNTL2__MON2_ID__SHIFT__SI 0x00000000 -#define MC_ARB_PERF_MON_CNTL2__MON3_ID__SHIFT__SI 0x00000008 -#define MC_ARB_PERF_MON_CNTL2__START_TRIG_ID_HI__SHIFT__SI 0x00000016 -#define MC_ARB_PERF_MON_CNTL2__STOP_TRIG_ID_HI__SHIFT__SI 0x00000018 -#define MC_ARB_PERF_MON_CNTL2__THRESH_CNTR_ID_HI__SHIFT__SI 0x00000014 -#define MC_ARB_PERF_MON_RSLT0__COUNT__SHIFT__SI 0x00000000 -#define MC_ARB_PERF_MON_RSLT1__COUNT__SHIFT__SI 0x00000000 -#define MC_ARB_PERF_MON_RSLT2__COUNT__SHIFT__SI 0x00000000 -#define MC_ARB_PERF_MON_RSLT3__COUNT__SHIFT__SI 0x00000000 -#define MC_ARB_PM_CNTL__ALLOW_STOP_SEL0__SHIFT__SI 0x00000018 -#define MC_ARB_PM_CNTL__ALLOW_STOP_SEL1__SHIFT__SI 0x00000019 -#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x00000005 -#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x00000014 -#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x00000006 -#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x00000012 -#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x00000013 -#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x00000000 -#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x00000002 -#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x00000003 -#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x00000008 -#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x00000007 -#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b -#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0x0000000a -#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f -#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0x0000000e -#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d -#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0x0000000c -#define MC_ARB_PM_CNTL__RSV_0__SHIFT__CI 0x00000010 -#define MC_ARB_PM_CNTL__RSV_1__SHIFT__CI 0x00000018 -#define MC_ARB_PM_CNTL__RSV_2__SHIFT__CI 0x00000019 -#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x00000004 -#define MC_ARB_PM_CNTL__STUTTER_MODE__SHIFT__SI 0x00000010 -#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x00000013 -#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x00000000 -#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x00000012 -#define MC_ARB_POP__POP_DEPTH__SHIFT 0x00000002 -#define MC_ARB_POP__QUICK_STOP__SHIFT 0x00000011 -#define MC_ARB_POP__SKID_DEPTH__SHIFT 0x0000000c -#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x00000001 -#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0x0000000f -#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x00000006 -#define MC_ARB_RAMCFG__BURSTLENGTH__SHIFT__SI 0x00000009 -#define MC_ARB_RAMCFG__BURST_TIME__SHIFT__SI 0x0000000d -#define MC_ARB_RAMCFG__CHANSIZE_OVERRIDE__SHIFT__SI 0x0000000b -#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x00000008 -#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x00000000 -#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x00000006 -#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0x0000000c -#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x00000002 -#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x00000003 -#define MC_ARB_RAMCFG__REQUEST_512B__SHIFT__SI 0x0000000a -#define MC_ARB_RAMCFG__RSV_1__SHIFT__CI__VI 0x00000009 -#define MC_ARB_RAMCFG__RSV_2__SHIFT__CI__VI 0x0000000a -#define MC_ARB_RAMCFG__RSV_3__SHIFT__CI__VI 0x0000000b -#define MC_ARB_RAMCFG__RSV_4__SHIFT__CI__VI 0x0000000d -#define MC_ARB_REFRESH_SCALE_CNTL__MC_ARB_REFRESH_SCALE__SHIFT__SI 0x00000008 -#define MC_ARB_REFRESH_SCALE_CNTL__MC_WAIT_PERIOD__SHIFT__SI 0x00000000 -#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x00000000 -#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x00000014 -#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x00000010 -#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x00000008 -#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x00000007 -#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x00000008 -#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x00000006 -#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x00000000 -#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x00000001 -#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x00000005 -#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT__CI__VI 0x0000000f -#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x00000004 -#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x00000003 -#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x00000002 -#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT__CI__VI 0x00000000 -#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x00000010 -#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x00000008 -#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x00000000 -#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x00000018 -#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x00000008 -#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x00000000 -#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x00000010 -#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x00000018 -#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0x0000000b -#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x00000000 -#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x00000001 -#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x00000006 -#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x00000000 -#define MC_ARB_RFSH_RATE__POWERMODE1__SHIFT__SI 0x00000008 -#define MC_ARB_RFSH_RATE__POWERMODE2__SHIFT__SI 0x00000010 -#define MC_ARB_RFSH_RATE__POWERMODE3__SHIFT__SI 0x00000018 -#define MC_ARB_RSV0__TBD_FIELD__SHIFT__SI 0x00000000 -#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x00000008 -#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x00000009 -#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0x0000000a -#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x00000018 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0x0000000f -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x00000010 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x00000011 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x00000012 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x00000013 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x00000014 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x00000015 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x00000016 -#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x00000017 -#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x00000000 -#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x00000004 -#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x00000005 -#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x00000019 -#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x00000001 -#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0x0000000e -#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x00000002 -#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x00000006 -#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0x0000000b -#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x00000007 -#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0x0000000d -#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x00000006 -#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x00000014 -#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x00000019 -#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x00000000 -#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x0000001e -#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x00000005 -#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0x0000000d -#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0x0000000c -#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x00000006 -#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x00000000 -#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x00000000 -#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x00000000 -#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x00000002 -#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x00000004 -#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x00000011 -#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0x0000000c -#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x00000019 -#define MC_ARB_SCRAMBLE_KEY0__KEY__SHIFT 0x00000000 -#define MC_ARB_SCRAMBLE_KEY1__KEY__SHIFT 0x00000000 -#define MC_ARB_SPARE0__BIT__SHIFT__SI 0x00000000 -#define MC_ARB_SPARE1__BIT__SHIFT__SI 0x00000000 -#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x00000008 -#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x00000000 -#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x00000018 -#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x00000010 -#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT__CI__VI 0x00000009 -#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT__CI__VI 0x0000000a -#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT__SI 0x00000009 -#define MC_ARB_SSM__FORMAT__SHIFT__CI 0x00000000 -#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x00000001 -#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x00000000 -#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x00000004 -#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x00000003 -#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x00000001 -#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x00000000 -#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x00000004 -#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x00000003 -#define MC_ARB_WCDR_2__DEBUG_0__SHIFT__SI__CI 0x00000009 -#define MC_ARB_WCDR_2__DEBUG_1__SHIFT__SI__CI 0x0000000a -#define MC_ARB_WCDR_2__DEBUG_2__SHIFT__SI__CI 0x0000000b -#define MC_ARB_WCDR_2__DEBUG_3__SHIFT__SI__CI 0x0000000c -#define MC_ARB_WCDR_2__DEBUG_4__SHIFT__SI__CI 0x0000000d -#define MC_ARB_WCDR_2__DEBUG_5__SHIFT__SI__CI 0x0000000e -#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT__SI__CI 0x00000000 -#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT__SI__CI 0x00000004 -#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT__SI__CI 0x0000000d -#define MC_ARB_WCDR__IDLE_BURST__SHIFT__SI__CI 0x00000007 -#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT__SI__CI 0x00000010 -#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT__SI__CI 0x00000000 -#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT__SI__CI 0x00000002 -#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT__SI__CI 0x0000000e -#define MC_ARB_WCDR__SEQ_IDLE__SHIFT__SI__CI 0x00000001 -#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT__SI__CI 0x00000011 -#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT__SI__CI 0x00000019 -#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT__SI__CI 0x0000001b -#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT__SI__CI 0x0000001a -#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT__SI__CI 0x00000016 -#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT__SI__CI 0x00000012 -#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT__SI__CI 0x0000001c -#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT__CI__VI 0x0000000b -#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT__CI__VI 0x0000000c -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 -#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a -#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT__CI__VI 0x0000000d -#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x00000002 -#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x00000000 -#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT__CI__VI 0x0000000b -#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT__CI__VI 0x0000000c -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 -#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a -#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT__CI__VI 0x0000000d -#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x00000002 -#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x00000000 -#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x00000000 -#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x00000002 -#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x00000004 -#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x00000006 -#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x00000008 -#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0x0000000a -#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0x0000000c -#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0x0000000e -#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x00000010 -#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x00000000 -#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x00000002 -#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x00000004 -#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x00000006 -#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x00000008 -#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0x0000000a -#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0x0000000c -#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0x0000000e -#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x00000010 -#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT__SI__CI 0x00000004 -#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT__SI__CI 0x00000019 -#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT__SI__CI 0x00000008 -#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT__SI__CI 0x00000018 -#define MC_BIST_AUTO_CNTL__MOP__SHIFT__SI__CI 0x00000000 -#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT__SI__CI 0x00000002 -#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT__SI__CI 0x00000010 -#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT__SI__CI 0x00000001 -#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT__SI__CI 0x00000011 -#define MC_BIST_CMD_CNTL__DONE__SHIFT__SI__CI 0x0000001f -#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT__SI__CI 0x0000001c -#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT__SI__CI 0x0000001d -#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT__SI__CI 0x00000004 -#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT__SI__CI 0x00000012 -#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT__SI__CI 0x00000003 -#define MC_BIST_CMD_CNTL__RESET__SHIFT__SI__CI 0x00000000 -#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT__SI__CI 0x0000001e -#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT__SI__CI 0x00000008 -#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT__SI__CI 0x00000000 -#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT__SI__CI 0x00000014 -#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT__SI__CI 0x0000000c -#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT__SI__CI 0x00000004 -#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT__SI__CI 0x00000000 -#define MC_BIST_CMP_CNTL__CMP__SHIFT__SI__CI 0x00000010 -#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT__SI__CI 0x00000014 -#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT__SI__CI 0x0000000d -#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT__SI__CI 0x00000012 -#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT__SI__CI 0x00000013 -#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT__SI__CI 0x0000000e -#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT__SI__CI 0x0000000f -#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT__SI__CI 0x0000000c -#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT__SI__CI 0x00000016 -#define MC_BIST_CNTL__ADR_MODE__SHIFT__SI__CI 0x00000005 -#define MC_BIST_CNTL__DAT_MODE__SHIFT__SI__CI 0x00000006 -#define MC_BIST_CNTL__DONE__SHIFT__SI__CI 0x0000001e -#define MC_BIST_CNTL__ENABLE_D0__SHIFT__SI__CI 0x0000000c -#define MC_BIST_CNTL__ENABLE_D1__SHIFT__SI__CI 0x0000000d -#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT__SI__CI 0x0000000e -#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT__SI__CI 0x0000001f -#define MC_BIST_CNTL__LOOP_CNT__SHIFT__SI__CI 0x00000010 -#define MC_BIST_CNTL__LOOP__SHIFT__SI__CI 0x0000000a -#define MC_BIST_CNTL__MOP_MODE__SHIFT__SI__CI 0x00000004 -#define MC_BIST_CNTL__PTR_RST_D0__SHIFT__SI__CI 0x00000002 -#define MC_BIST_CNTL__PTR_RST_D1__SHIFT__SI__CI 0x00000003 -#define MC_BIST_CNTL__RESET__SHIFT__SI__CI 0x00000000 -#define MC_BIST_CNTL__RUN__SHIFT__SI__CI 0x00000001 -#define MC_BIST_DATA_MASK__MASK__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD0__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD1__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD2__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD3__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD4__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD5__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD6__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DATA_WORD7__DATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT__SI__CI 0x00000006 -#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT__SI__CI 0x00000008 -#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT__SI__CI 0x00000005 -#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT__SI__CI 0x00000007 -#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT__SI__CI 0x00000009 -#define MC_BIST_DIR_CNTL__EOB__SHIFT__SI__CI 0x00000003 -#define MC_BIST_DIR_CNTL__MOP3__SHIFT__SI__CI 0x0000000a -#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT__SI__CI 0x00000004 -#define MC_BIST_DIR_CNTL__MOP__SHIFT__SI__CI 0x00000000 -#define MC_BIST_EADDR__BANK__SHIFT__SI__CI 0x00000018 -#define MC_BIST_EADDR__COLH__SHIFT__SI__CI 0x0000001d -#define MC_BIST_EADDR__COL__SHIFT__SI__CI 0x00000000 -#define MC_BIST_EADDR__RANK__SHIFT__SI__CI 0x0000001c -#define MC_BIST_EADDR__ROWH__SHIFT__SI__CI 0x0000001e -#define MC_BIST_EADDR__ROW__SHIFT__SI__CI 0x0000000a -#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT__SI__CI 0x00000018 -#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT__SI__CI 0x0000001d -#define MC_BIST_MISMATCH_ADDR__COL__SHIFT__SI__CI 0x00000000 -#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT__SI__CI 0x0000001c -#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT__SI__CI 0x0000001e -#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT__SI__CI 0x0000000a -#define MC_BIST_RDATA_EDC__EDC__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_MASK__MASK__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD0__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD1__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD2__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD3__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD4__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD5__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD6__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_RDATA_WORD7__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_BIST_SADDR__BANK__SHIFT__SI__CI 0x00000018 -#define MC_BIST_SADDR__COLH__SHIFT__SI__CI 0x0000001d -#define MC_BIST_SADDR__COL__SHIFT__SI__CI 0x00000000 -#define MC_BIST_SADDR__RANK__SHIFT__SI__CI 0x0000001c -#define MC_BIST_SADDR__ROWH__SHIFT__SI__CI 0x0000001e -#define MC_BIST_SADDR__ROW__SHIFT__SI__CI 0x0000000a -#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0x0000000d -#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 -#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 -#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 -#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 -#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 -#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 -#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 -#define MC_CG_CONFIG__INDEX__SHIFT 0x00000006 -#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 -#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 -#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 -#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 -#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004 -#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x00000000 -#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT__CI__VI 0x00000007 -#define MC_CITF_CNTL__DUMMY__SHIFT__SI 0x00000007 -#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x00000003 -#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x00000004 -#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x00000002 -#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x00000006 -#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT__CI 0x00000008 -#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x00000019 -#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x00000018 -#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x00000008 -#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x00000000 -#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x00000010 -#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT__CI 0x00000011 -#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x00000008 -#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x00000000 -#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x00000000 -#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x00000006 -#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x00000000 -#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x00000008 -#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x00000001 -#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT__CI__VI 0x00000006 -#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x00000005 -#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x00000000 -#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x00000010 -#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x00000000 -#define MC_CITF_DAGB_DLY__POS__SHIFT 0x00000018 -#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT__CI__VI 0x00000000 -#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT__CI__VI 0x00000006 -#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x00000012 -#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0x0000000c -#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x00000018 -#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x00000000 -#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x00000012 -#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x00000006 -#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x00000000 -#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0x0000000c -#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x00000012 -#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 -#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x00000000 -#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c -#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x00000012 -#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x00000006 -#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x00000000 -#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0x0000000c -#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define MC_CITF_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT__SI 0x0000001c -#define MC_CITF_PERF_MON_CNTL0__START_MODE__SHIFT__SI 0x00000018 -#define MC_CITF_PERF_MON_CNTL0__START_THRESH__SHIFT__SI 0x00000000 -#define MC_CITF_PERF_MON_CNTL0__STOP_MODE__SHIFT__SI 0x0000001a -#define MC_CITF_PERF_MON_CNTL0__STOP_THRESH__SHIFT__SI 0x0000000c -#define MC_CITF_PERF_MON_CNTL1__MON0_ID__SHIFT__SI 0x00000012 -#define MC_CITF_PERF_MON_CNTL1__MON1_ID__SHIFT__SI 0x00000018 -#define MC_CITF_PERF_MON_CNTL1__START_TRIG_ID__SHIFT__SI 0x00000006 -#define MC_CITF_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT__SI 0x0000000c -#define MC_CITF_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT__SI 0x00000000 -#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x00000000 -#define MC_CITF_PERF_MON_CNTL2__MON0_ID6__SHIFT__SI 0x0000000c -#define MC_CITF_PERF_MON_CNTL2__MON1_ID6__SHIFT__SI 0x0000000d -#define MC_CITF_PERF_MON_CNTL2__START_TRIG_ID6__SHIFT__SI 0x0000000a -#define MC_CITF_PERF_MON_CNTL2__STOP_TRIG_ID6__SHIFT__SI 0x0000000b -#define MC_CITF_PERF_MON_CNTL2__THRESH_CNTR_ID6__SHIFT__SI 0x00000009 -#define MC_CITF_PERF_MON_RSLT0__COUNT__SHIFT__SI 0x00000000 -#define MC_CITF_PERF_MON_RSLT1__COUNT__SHIFT__SI 0x00000000 -#define MC_CITF_PERF_MON_RSLT2__RSLT1_HIGH__SHIFT__SI 0x00000000 -#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0x0000000e -#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x00000000 -#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x00000007 -#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x00000000 -#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x00000001 -#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x00000004 -#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x00000005 -#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x00000002 -#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x00000003 -#define MC_CITF_WTM_RD_CNTL__DIABLE_LOCAL__SHIFT__SI 0x00000019 -#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT__CI__VI 0x00000019 -#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 -#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 -#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 -#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 -#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 -#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c -#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f -#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 -#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 -#define MC_CITF_WTM_WR_CNTL__DIABLE_LOCAL__SHIFT__SI 0x00000019 -#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT__CI__VI 0x00000019 -#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 -#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 -#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 -#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 -#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 -#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c -#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f -#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 -#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 -#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x00000008 -#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT__CI__VI 0x00000019 -#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT__CI__VI 0x0000000d -#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT__CI__VI 0x0000001b -#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT__CI__VI 0x00000011 -#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x00000000 -#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x00000001 -#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT__CI__VI 0x0000001a -#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT__CI__VI 0x0000000f -#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT__CI__VI 0x00000013 -#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x00000002 -#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x00000003 -#define MC_CITF_XTRA_ENABLE__DUMMY0__SHIFT__SI 0x00000006 -#define MC_CITF_XTRA_ENABLE__DUMMY1__SHIFT__SI 0x00000007 -#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT__CI__VI 0x00000015 -#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT__CI__VI 0x00000017 -#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x00000004 -#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT__CI__VI 0x0000001d -#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0x0000000c -#define MC_CITF_XTRA_ENABLE__TC3_RD__SHIFT__SI 0x00000005 -#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 -#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 -#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 -#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 -#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 -#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 -#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x0000001f -#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 -#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x0000001f -#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 -#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 -#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 -#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 -#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT__SI 0x00000004 -#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT__SI 0x00000000 -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT__SI 0x00000014 -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT__SI 0x00000010 -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT__SI 0x0000001c -#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT__SI 0x00000018 -#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT__SI 0x0000000c -#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT__SI 0x00000008 -#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT__CI 0x00000002 -#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT__CI 0x00000000 -#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT__CI 0x00000001 -#define MC_DLB_CONFIG0__MASK__SHIFT__CI 0x00000004 -#define MC_DLB_CONFIG0__PTR__SHIFT__CI 0x00000008 -#define MC_DLB_CONFIG1__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT__CI 0x00000003 -#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT__CI 0x00000004 -#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT__CI 0x00000001 -#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT__CI 0x00000002 -#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT__CI 0x00000008 -#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT__CI 0x00000000 -#define MC_DLB_MISCCTRL0__UDD__SHIFT__CI 0x00000010 -#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT__CI 0x00000000 -#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT__CI 0x0000001a -#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT__CI 0x00000012 -#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT__CI 0x00000013 -#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT__CI 0x00000011 -#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT__CI 0x00000000 -#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT__CI 0x0000001d -#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT__CI 0x0000001c -#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT__CI 0x0000001e -#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT__CI 0x00000015 -#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT__CI 0x00000014 -#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT__CI 0x00000018 -#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT__CI 0x00000002 -#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT__CI 0x0000000a -#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT__CI 0x00000006 -#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT__CI 0x00000001 -#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT__CI 0x00000008 -#define MC_DLB_SETUPFIFO__STROBE__SHIFT__CI 0x00000010 -#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT__CI 0x00000004 -#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT__CI 0x00000003 -#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT__CI 0x00000000 -#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT__CI 0x00000001 -#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT__CI 0x00000004 -#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT__CI 0x00000008 -#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT__CI 0x00000000 -#define MC_DLB_SETUPSWEEP__MASTER__SHIFT__CI 0x00000002 -#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT__CI 0x00000010 -#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT__CI 0x00000003 -#define MC_DLB_SETUP__DLB_EN__SHIFT__CI 0x00000000 -#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT__CI 0x00000001 -#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT__CI 0x00000004 -#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT__CI 0x00000002 -#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT__CI 0x00000018 -#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT__CI 0x00000006 -#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT__CI 0x00000005 -#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT__CI 0x00000007 -#define MC_DLB_SETUP__QDR_MODE__SHIFT__CI 0x00000008 -#define MC_DLB_SETUP__RXTXLP_EN__SHIFT__CI 0x0000001f -#define MC_DLB_STATUS_MISC0__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS_MISC1__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS_MISC2__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS_MISC3__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS_MISC4__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS_MISC5__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS_MISC6__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS_MISC7__DATA__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS__LOCK__SHIFT__CI 0x00000004 -#define MC_DLB_STATUS__STICK_ERROR__SHIFT__CI 0x00000000 -#define MC_DLB_STATUS__SWEEP_DONE__SHIFT__CI 0x00000008 -#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT__CI 0x00000000 -#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT__CI 0x00000018 -#define MC_HUB_MISC_DBG__CTRL0__SHIFT__CI 0x00000008 -#define MC_HUB_MISC_DBG__CTRL1__SHIFT__CI 0x0000000d -#define MC_HUB_MISC_DBG__SELECT0__SHIFT__SI__CI 0x00000000 -#define MC_HUB_MISC_DBG__SELECT1__SHIFT__SI__CI 0x00000004 -#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x00000000 -#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x00000012 -#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x00000006 -#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x00000000 -#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0x0000000c -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT__CI 0x00000018 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT__CI 0x00000019 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT__CI 0x0000001a -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT__SI 0x00000000 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT__CI 0x0000001b -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT__SI 0x00000001 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT__CI__VI 0x00000008 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT__SI 0x0000000a -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT__CI__VI 0x00000009 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT__SI 0x0000000b -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA0_READ__SHIFT__SI 0x00000008 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA0_WRITE__SHIFT__SI 0x00000009 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA1_READ__SHIFT__SI 0x00000004 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DRMDMA1_WRITE__SHIFT__SI 0x00000005 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT__CI__VI 0x00000000 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT__SI 0x00000002 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT__SI 0x00000003 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT__CI__VI 0x0000000e -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT__SI 0x00000010 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT__CI__VI 0x0000000f -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT__SI 0x00000011 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT__CI 0x00000014 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT__CI 0x00000015 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT__CI__VI 0x00000010 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT__SI 0x00000012 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT__CI__VI 0x00000011 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT__SI 0x00000013 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT__CI__VI 0x00000002 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT__SI 0x00000006 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT__CI__VI 0x00000003 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT__SI 0x00000007 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT__CI__VI 0x00000004 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT__CI__VI 0x00000005 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT__CI__VI 0x00000006 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT__CI__VI 0x00000007 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT__CI__VI 0x0000000c -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT__SI 0x0000000e -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT__CI__VI 0x0000000d -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT__SI 0x0000000f -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT__CI__VI 0x0000000a -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT__SI 0x0000000c -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT__CI__VI 0x0000000b -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT__SI 0x0000000d -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT__CI 0x00000016 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT__SI 0x00000018 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT__CI 0x00000017 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT__SI 0x00000019 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VGT_READ__SHIFT__SI 0x00000016 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VGT_WRITE__SHIFT__SI 0x00000017 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT__CI__VI 0x00000012 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT__SI 0x00000014 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT__CI__VI 0x00000013 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT__SI 0x00000015 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT__CI 0x0000001c -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT__SI__VI 0x0000001a -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT__CI 0x0000001d -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT__SI__VI 0x0000001b -#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x00000000 -#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x00000003 -#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x00000002 -#define MC_HUB_MISC_POWER__SS_STUTTER_MODE__SHIFT__SI 0x00000005 -#define MC_HUB_MISC_POWER__STUTTER_LPT_MODE__SHIFT__SI 0x00000006 -#define MC_HUB_MISC_POWER__STUTTER_MODE__SHIFT__SI 0x00000000 -#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x00000012 -#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x00000006 -#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x00000000 -#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0x0000000c -#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x00000000 -#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x00000001 -#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x00000012 -#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 -#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x00000000 -#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c -#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT__CI__VI 0x00000002 -#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT__CI__VI 0x00000010 -#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT__CI__VI 0x00000011 -#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT__CI__VI 0x00000012 -#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT__CI__VI 0x00000013 -#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT__CI__VI 0x00000010 -#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT__CI__VI 0x00000011 -#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT__CI__VI 0x00000012 -#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT__CI__VI 0x00000013 -#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT__CI 0x00000014 -#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000002 -#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000003 -#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x00000005 -#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x00000007 -#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x00000008 -#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x00000000 -#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_RDREQ_CP__BLACKOUT_EXEMPT__SHIFT__SI 0x00000003 -#define MC_HUB_RDREQ_CP__ENABLE__SHIFT__SI 0x00000000 -#define MC_HUB_RDREQ_CP__LAZY_TIMER__SHIFT__SI 0x0000000b -#define MC_HUB_RDREQ_CP__MAXBURST__SHIFT__SI 0x00000007 -#define MC_HUB_RDREQ_CP__PRESCALE__SHIFT__SI 0x00000001 -#define MC_HUB_RDREQ_CP__STALL_MODE__SHIFT__SI 0x00000004 -#define MC_HUB_RDREQ_CP__STALL_OVERRIDE_WTM__SHIFT__SI 0x0000000f -#define MC_HUB_RDREQ_CP__STALL_OVERRIDE__SHIFT__SI 0x00000006 -#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x00000010 -#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x00000018 -#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x00000000 -#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x00000008 -#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x00000002 -#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_DRMDMA0__BLACKOUT_EXEMPT__SHIFT__SI 0x00000003 -#define MC_HUB_RDREQ_DRMDMA0__ENABLE__SHIFT__SI 0x00000000 -#define MC_HUB_RDREQ_DRMDMA0__LAZY_TIMER__SHIFT__SI 0x0000000b -#define MC_HUB_RDREQ_DRMDMA0__MAXBURST__SHIFT__SI 0x00000007 -#define MC_HUB_RDREQ_DRMDMA0__PRESCALE__SHIFT__SI 0x00000001 -#define MC_HUB_RDREQ_DRMDMA0__STALL_MODE__SHIFT__SI 0x00000004 -#define MC_HUB_RDREQ_DRMDMA0__STALL_OVERRIDE_WTM__SHIFT__SI 0x0000000f -#define MC_HUB_RDREQ_DRMDMA0__STALL_OVERRIDE__SHIFT__SI 0x00000006 -#define MC_HUB_RDREQ_DRMDMA1__BLACKOUT_EXEMPT__SHIFT__SI 0x00000003 -#define MC_HUB_RDREQ_DRMDMA1__ENABLE__SHIFT__SI 0x00000000 -#define MC_HUB_RDREQ_DRMDMA1__LAZY_TIMER__SHIFT__SI 0x0000000b -#define MC_HUB_RDREQ_DRMDMA1__MAXBURST__SHIFT__SI 0x00000007 -#define MC_HUB_RDREQ_DRMDMA1__PRESCALE__SHIFT__SI 0x00000001 -#define MC_HUB_RDREQ_DRMDMA1__STALL_MODE__SHIFT__SI 0x00000004 -#define MC_HUB_RDREQ_DRMDMA1__STALL_OVERRIDE_WTM__SHIFT__SI 0x0000000f -#define MC_HUB_RDREQ_DRMDMA1__STALL_OVERRIDE__SHIFT__SI 0x00000006 -#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x00000000 -#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x00000000 -#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_RDREQ_IA__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0x0000000b -#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x00000002 -#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x00000012 -#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x00000007 -#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT__SI__CI 0x00000019 -#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0x0000000b -#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x00000002 -#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x00000012 -#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x00000007 -#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT__SI__CI 0x00000019 -#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0x0000000b -#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x00000002 -#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x00000012 -#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x00000007 -#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT__SI__CI 0x00000019 -#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0x0000000b -#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x00000002 -#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x00000012 -#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x00000007 -#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT__SI__CI 0x00000019 -#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x00000000 -#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x00000008 -#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT__SI__CI 0x00000007 -#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 -#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 -#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 -#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 -#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x00000000 -#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x00000010 -#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT__SI__CI 0x00000003 -#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT__SI__CI 0x00000000 -#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT__SI__CI 0x0000000b -#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT__SI__CI 0x00000007 -#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT__SI__CI 0x00000001 -#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT__SI__CI 0x00000004 -#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT__SI__CI 0x0000000f -#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT__SI__CI 0x00000006 -#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT__SI__CI 0x00000003 -#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT__SI__CI 0x00000000 -#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT__SI__CI 0x0000000b -#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT__SI__CI 0x00000007 -#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT__SI__CI 0x00000001 -#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT__SI__CI 0x00000004 -#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT__SI__CI 0x0000000f -#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT__SI__CI 0x00000006 -#define MC_HUB_RDREQ_VGT__BLACKOUT_EXEMPT__SHIFT__SI 0x00000003 -#define MC_HUB_RDREQ_VGT__ENABLE__SHIFT__SI 0x00000000 -#define MC_HUB_RDREQ_VGT__LAZY_TIMER__SHIFT__SI 0x0000000b -#define MC_HUB_RDREQ_VGT__MAXBURST__SHIFT__SI 0x00000007 -#define MC_HUB_RDREQ_VGT__PRESCALE__SHIFT__SI 0x00000001 -#define MC_HUB_RDREQ_VGT__STALL_MODE__SHIFT__SI 0x00000004 -#define MC_HUB_RDREQ_VGT__STALL_OVERRIDE_WTM__SHIFT__SI 0x0000000f -#define MC_HUB_RDREQ_VGT__STALL_OVERRIDE__SHIFT__SI 0x00000006 -#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 -#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 -#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 -#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c -#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f -#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 -#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 -#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x00000000 -#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x00000010 -#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x00000000 -#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x00000018 -#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT__CI__VI 0x00000010 -#define MC_HUB_WDP_ACPG__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT__CI__VI 0x00000011 -#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT__CI__VI 0x00000012 -#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT__CI__VI 0x00000013 -#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT__CI__VI 0x00000010 -#define MC_HUB_WDP_ACPO__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT__CI__VI 0x00000011 -#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT__CI__VI 0x00000012 -#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT__CI__VI 0x00000013 -#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_BP__RDRET__SHIFT 0x00000001 -#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x00000012 -#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x00000005 -#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x0000000d -#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x0000000e -#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0x0000000f -#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x00000012 -#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x00000010 -#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000001 -#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000002 -#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x00000003 -#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x00000011 -#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x00000013 -#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 -#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x00000014 -#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_WDP_CPC__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_WDP_CPC__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_WDP_CPC__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_WDP_CPF__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_WDP_CPF__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_WDP_CPF__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_WDP_CPG__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_WDP_CPG__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_WDP_CPG__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_WDP_CP__BLACKOUT_EXEMPT__SHIFT__SI 0x00000003 -#define MC_HUB_WDP_CP__ENABLE__SHIFT__SI 0x00000000 -#define MC_HUB_WDP_CP__LAZY_TIMER__SHIFT__SI 0x0000000b -#define MC_HUB_WDP_CP__MAXBURST__SHIFT__SI 0x00000007 -#define MC_HUB_WDP_CP__PRESCALE__SHIFT__SI 0x00000001 -#define MC_HUB_WDP_CP__STALL_MODE__SHIFT__SI 0x00000004 -#define MC_HUB_WDP_CP__STALL_OVERRIDE_WTM__SHIFT__SI 0x0000000f -#define MC_HUB_WDP_CP__STALL_OVERRIDE__SHIFT__SI 0x00000006 -#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x00000010 -#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x00000018 -#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x00000000 -#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x00000008 -#define MC_HUB_WDP_DRMDMA0__BLACKOUT_EXEMPT__SHIFT__SI 0x00000003 -#define MC_HUB_WDP_DRMDMA0__ENABLE__SHIFT__SI 0x00000000 -#define MC_HUB_WDP_DRMDMA0__LAZY_TIMER__SHIFT__SI 0x0000000b -#define MC_HUB_WDP_DRMDMA0__MAXBURST__SHIFT__SI 0x00000007 -#define MC_HUB_WDP_DRMDMA0__PRESCALE__SHIFT__SI 0x00000001 -#define MC_HUB_WDP_DRMDMA0__STALL_MODE__SHIFT__SI 0x00000004 -#define MC_HUB_WDP_DRMDMA0__STALL_OVERRIDE_WTM__SHIFT__SI 0x0000000f -#define MC_HUB_WDP_DRMDMA0__STALL_OVERRIDE__SHIFT__SI 0x00000006 -#define MC_HUB_WDP_DRMDMA1__BLACKOUT_EXEMPT__SHIFT__SI 0x00000003 -#define MC_HUB_WDP_DRMDMA1__ENABLE__SHIFT__SI 0x00000000 -#define MC_HUB_WDP_DRMDMA1__LAZY_TIMER__SHIFT__SI 0x0000000b -#define MC_HUB_WDP_DRMDMA1__MAXBURST__SHIFT__SI 0x00000007 -#define MC_HUB_WDP_DRMDMA1__PRESCALE__SHIFT__SI 0x00000001 -#define MC_HUB_WDP_DRMDMA1__STALL_MODE__SHIFT__SI 0x00000004 -#define MC_HUB_WDP_DRMDMA1__STALL_OVERRIDE_WTM__SHIFT__SI 0x0000000f -#define MC_HUB_WDP_DRMDMA1__STALL_OVERRIDE__SHIFT__SI 0x00000006 -#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x00000000 -#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x00000001 -#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x00000004 -#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x00000000 -#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x00000010 -#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x00000008 -#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x00000004 -#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x00000000 -#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x00000010 -#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x00000008 -#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x00000018 -#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x00000007 -#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0x0000000d -#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x00000002 -#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x00000011 -#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x00000018 -#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x00000007 -#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0x0000000d -#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x00000002 -#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x00000011 -#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x00000018 -#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x00000007 -#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0x0000000d -#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x00000002 -#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x00000011 -#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x00000018 -#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x00000007 -#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 -#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0x0000000d -#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x00000003 -#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x00000002 -#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x00000011 -#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_MGPU2__CID2__SHIFT__SI__CI 0x00000000 -#define MC_HUB_WDP_MGPU__CID__SHIFT__SI__CI 0x00000008 -#define MC_HUB_WDP_MGPU__ENABLE__SHIFT__SI__CI 0x00000017 -#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT__SI__CI 0x00000010 -#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT__SI__CI 0x00000018 -#define MC_HUB_WDP_MGPU__STOR__SHIFT__SI__CI 0x00000000 -#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT__CI 0x00000003 -#define MC_HUB_WDP_SAM__ENABLE__SHIFT__CI 0x00000000 -#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT__CI 0x0000000b -#define MC_HUB_WDP_SAM__MAXBURST__SHIFT__CI 0x00000007 -#define MC_HUB_WDP_SAM__PRESCALE__SHIFT__CI 0x00000001 -#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT__CI 0x00000004 -#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT__CI 0x0000000f -#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT__CI 0x00000006 -#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_WDP_SH2__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_WDP_SH2__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_WDP_SH2__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT__CI__VI 0x00000003 -#define MC_HUB_WDP_SH3__ENABLE__SHIFT__CI__VI 0x00000000 -#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT__CI__VI 0x0000000b -#define MC_HUB_WDP_SH3__MAXBURST__SHIFT__CI__VI 0x00000007 -#define MC_HUB_WDP_SH3__PRESCALE__SHIFT__CI__VI 0x00000001 -#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT__CI__VI 0x00000004 -#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT__CI__VI 0x0000000f -#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT__CI__VI 0x00000006 -#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x00000002 -#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x00000000 -#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 -#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT__SI 0x0000000b -#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 -#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT__SI 0x0000000c -#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 -#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT__SI 0x0000000d -#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 -#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT__SI 0x0000000e -#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x00000000 -#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x00000010 -#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT__SI__CI 0x00000003 -#define MC_HUB_WDP_VCEU__ENABLE__SHIFT__SI__CI 0x00000000 -#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT__SI__CI 0x0000000b -#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT__SI__CI 0x00000007 -#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT__SI__CI 0x00000001 -#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT__SI__CI 0x00000004 -#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT__SI__CI 0x0000000f -#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT__SI__CI 0x00000006 -#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT__SI__CI 0x00000003 -#define MC_HUB_WDP_VCE__ENABLE__SHIFT__SI__CI 0x00000000 -#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT__SI__CI 0x0000000b -#define MC_HUB_WDP_VCE__MAXBURST__SHIFT__SI__CI 0x00000007 -#define MC_HUB_WDP_VCE__PRESCALE__SHIFT__SI__CI 0x00000001 -#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT__SI__CI 0x00000004 -#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT__SI__CI 0x0000000f -#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT__SI__CI 0x00000006 -#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 -#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 -#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 -#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 -#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c -#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f -#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 -#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 -#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 -#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 -#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x00000000 -#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0x0000000b -#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x00000007 -#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x00000001 -#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x00000004 -#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x00000015 -#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x00000001 -#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x00000016 -#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x0000001e -#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x0000001f -#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x00000000 -#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x00000001 -#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x00000000 -#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x00000001 -#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x00000000 -#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x00000001 -#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x00000000 -#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x00000001 -#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x00000000 -#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x00000000 -#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x00000001 -#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x00000002 -#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x00000003 -#define MC_IMP_CNTL__CAL_PWRON__SHIFT__SI__CI 0x0000001f -#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT__SI__CI 0x00000006 -#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT__SI__CI 0x00000005 -#define MC_IMP_CNTL__CAL_VREF__SHIFT__SI__CI 0x00000010 -#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT__SI__CI 0x0000001d -#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT__SI__CI 0x0000001e -#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT__SI__CI 0x00000009 -#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT__SI__CI 0x0000000d -#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT__SI__CI 0x00000000 -#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT__SI__CI 0x00000008 -#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT__SI__CI 0x0000001f -#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT__SI__CI 0x0000001c -#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT__SI__CI 0x0000001e -#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT__SI__CI 0x0000001d -#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT__SI__CI 0x00000010 -#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT__SI__CI 0x00000008 -#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT__SI__CI 0x00000000 -#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT__SI__CI 0x00000008 -#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT__SI__CI 0x00000000 -#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT__SI__CI 0x00000018 -#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT__SI__CI 0x00000010 -#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT__SI__CI 0x00000018 -#define MC_IMP_STATUS__NSTR_CAL__SHIFT__SI__CI 0x00000010 -#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT__SI__CI 0x00000008 -#define MC_IMP_STATUS__PSTR_CAL__SHIFT__SI__CI 0x00000000 -#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT__SI__CI 0x0000001a -#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT__SI__CI 0x0000001c -#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT__SI__CI 0x0000001d -#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT__SI__CI 0x00000006 -#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT__SI__CI 0x00000000 -#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT__SI__CI 0x0000000c -#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT__SI__CI 0x00000018 -#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT__SI__CI 0x00000019 -#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT__SI__CI 0x0000001a -#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT__SI__CI 0x0000001c -#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT__SI__CI 0x0000001d -#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT__SI__CI 0x00000006 -#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT__SI__CI 0x00000000 -#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT__SI__CI 0x0000000c -#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT__SI__CI 0x00000018 -#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT__SI__CI 0x00000019 -#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT__SI__CI 0x00000000 -#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT__SI__CI 0x00000008 -#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT__SI__CI 0x00000010 -#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT__SI__CI 0x00000018 -#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT__SI__CI 0x00000000 -#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT__SI__CI 0x00000008 -#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT__SI__CI 0x00000010 -#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT__SI__CI 0x00000018 -#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT__SI__CI 0x00000000 -#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT__SI__CI 0x00000001 -#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT__SI__CI 0x00000002 -#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT__SI__CI 0x00000003 -#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT__SI__CI 0x00000004 -#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT__SI__CI 0x00000005 -#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT__CI 0x00000010 -#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT__CI 0x00000008 -#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT__CI 0x0000000c -#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT__SI__CI 0x00000006 -#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT__SI__CI 0x00000007 -#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT__SI__CI 0x00000000 -#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT__SI__CI 0x00000001 -#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT__SI__CI 0x00000002 -#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT__SI__CI 0x00000003 -#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT__SI__CI 0x00000004 -#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT__SI__CI 0x00000005 -#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT__CI 0x00000010 -#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT__CI 0x00000008 -#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT__CI 0x0000000c -#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT__SI__CI 0x00000006 -#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT__SI__CI 0x00000007 -#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT__SI__CI 0x00000016 -#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT__SI__CI 0x00000017 -#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT__SI__CI 0x0000001c -#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT__SI__CI 0x0000001d -#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT__SI__CI 0x00000014 -#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT__SI__CI 0x00000015 -#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT__SI__CI 0x0000001e -#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT__SI__CI 0x0000001f -#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT__SI__CI 0x0000000a -#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT__SI__CI 0x0000000b -#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT__SI__CI 0x00000008 -#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT__SI__CI 0x00000009 -#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT__SI__CI 0x0000000c -#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT__SI__CI 0x00000010 -#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT__SI__CI 0x00000000 -#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT__SI__CI 0x00000004 -#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT__SI__CI 0x0000001a -#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT__SI__CI 0x0000001b -#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT__SI__CI 0x00000018 -#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT__SI__CI 0x00000019 -#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT__SI__CI 0x00000016 -#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT__SI__CI 0x00000017 -#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT__SI__CI 0x0000001c -#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT__SI__CI 0x0000001d -#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT__SI__CI 0x00000014 -#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT__SI__CI 0x00000015 -#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT__SI__CI 0x0000001e -#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT__SI__CI 0x0000001f -#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT__SI__CI 0x0000000a -#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT__SI__CI 0x0000000b -#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT__SI__CI 0x00000008 -#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT__SI__CI 0x00000009 -#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT__SI__CI 0x0000000c -#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT__SI__CI 0x00000010 -#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT__SI__CI 0x00000000 -#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT__SI__CI 0x00000004 -#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT__SI__CI 0x0000001a -#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT__SI__CI 0x0000001b -#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT__SI__CI 0x00000018 -#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT__SI__CI 0x00000019 -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT__SI__CI 0x00000000 -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT__SI__CI 0x00000008 -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT__SI__CI 0x00000010 -#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT__SI__CI 0x00000018 -#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT__CI 0x0000001e -#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT__SI__CI 0x0000001a -#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT__SI__CI 0x0000001c -#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT__SI__CI 0x0000001d -#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT__SI__CI 0x00000006 -#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT__SI__CI 0x00000012 -#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT__SI__CI 0x00000000 -#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT__SI__CI 0x0000000c -#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT__SI__CI 0x00000018 -#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT__SI__CI 0x00000019 -#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT__CI 0x0000001e -#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT__SI__CI 0x0000001a -#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT__SI__CI 0x0000001c -#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT__SI__CI 0x0000001d -#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT__SI__CI 0x00000006 -#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT__SI__CI 0x00000012 -#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT__SI__CI 0x00000000 -#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT__SI__CI 0x0000000c -#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT__SI__CI 0x00000018 -#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT__SI__CI 0x00000019 -#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT__SI__CI 0x00000014 -#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT__SI__CI 0x00000016 -#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT__SI__CI 0x00000018 -#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT__SI__CI 0x00000015 -#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT__SI__CI 0x00000004 -#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT__SI__CI 0x00000002 -#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT__SI__CI 0x00000003 -#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT__SI__CI 0x0000001d -#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT__SI__CI 0x0000000d -#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT__SI__CI 0x0000000c -#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT__SI__CI 0x0000000b -#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT__SI__CI 0x0000000a -#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT__SI__CI 0x0000001e -#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT__SI__CI 0x00000009 -#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT__SI__CI 0x00000007 -#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT__SI__CI 0x00000008 -#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT__SI__CI 0x0000001b -#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT__SI__CI 0x0000001f -#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT__SI__CI 0x0000001c -#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT__SI__CI 0x0000000e -#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT__SI__CI 0x0000000f -#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT__SI__CI 0x00000014 -#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT__SI__CI 0x00000016 -#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT__SI__CI 0x00000018 -#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT__SI__CI 0x00000015 -#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT__SI__CI 0x00000004 -#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT__SI__CI 0x00000002 -#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT__SI__CI 0x00000003 -#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT__SI__CI 0x00000000 -#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT__SI__CI 0x00000001 -#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT__SI__CI 0x0000001d -#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT__SI__CI 0x0000000d -#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT__SI__CI 0x0000000c -#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT__SI__CI 0x0000000b -#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT__SI__CI 0x0000000a -#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT__SI__CI 0x0000001e -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT__SI__CI 0x00000009 -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT__SI__CI 0x00000007 -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT__SI__CI 0x00000008 -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT__SI__CI 0x00000005 -#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT__SI__CI 0x00000006 -#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT__SI__CI 0x0000001b -#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT__SI__CI 0x0000001f -#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT__SI__CI 0x0000001c -#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT__SI__CI 0x0000000e -#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT__SI__CI 0x0000000f -#define MC_IO_PAD_CNTL__ATBEN__SHIFT__SI__CI 0x00000018 -#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT__SI__CI 0x0000001f -#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT__SI__CI 0x0000001e -#define MC_IO_PAD_CNTL__ATBSEL__SHIFT__SI__CI 0x00000014 -#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT__SI__CI 0x00000008 -#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT__SI__CI 0x00000000 -#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT__SI__CI 0x00000012 -#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT__SI__CI 0x00000013 -#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT__SI__CI 0x00000011 -#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT__CI 0x00000015 -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT__CI 0x00000013 -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT__CI 0x00000014 -#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT__SI__CI 0x00000019 -#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT__CI 0x00000016 -#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT__CI 0x00000017 -#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT__SI__CI 0x00000011 -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTRACK01_0__SHIFT__SI 0x00000017 -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTRACK01_1__SHIFT__SI 0x00000018 -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXPWRON_B0__SHIFT__SI 0x00000013 -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXPWRON_B1__SHIFT__SI 0x00000014 -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXSEL_B0__SHIFT__SI 0x00000015 -#define MC_IO_RXCNTL1_DPHY0_D0__WCDRTXSEL_B1__SHIFT__SI 0x00000016 -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT__CI 0x00000015 -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT__CI 0x00000013 -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT__CI 0x00000014 -#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT__SI__CI 0x00000019 -#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT__CI 0x00000016 -#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT__CI 0x00000017 -#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT__SI__CI 0x00000011 -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTRACK01_0__SHIFT__SI 0x00000017 -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTRACK01_1__SHIFT__SI 0x00000018 -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXPWRON_B0__SHIFT__SI 0x00000013 -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXPWRON_B1__SHIFT__SI 0x00000014 -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXSEL_B0__SHIFT__SI 0x00000015 -#define MC_IO_RXCNTL1_DPHY0_D1__WCDRTXSEL_B1__SHIFT__SI 0x00000016 -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT__CI 0x00000015 -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT__CI 0x00000013 -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT__CI 0x00000014 -#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT__SI__CI 0x00000019 -#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT__CI 0x00000016 -#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT__CI 0x00000017 -#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT__SI__CI 0x00000011 -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTRACK01_0__SHIFT__SI 0x00000017 -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTRACK01_1__SHIFT__SI 0x00000018 -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXPWRON_B0__SHIFT__SI 0x00000013 -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXPWRON_B1__SHIFT__SI 0x00000014 -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXSEL_B0__SHIFT__SI 0x00000015 -#define MC_IO_RXCNTL1_DPHY1_D0__WCDRTXSEL_B1__SHIFT__SI 0x00000016 -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT__CI 0x00000015 -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT__CI 0x00000013 -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT__CI 0x00000014 -#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT__SI__CI 0x00000019 -#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT__CI 0x00000016 -#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT__CI 0x00000017 -#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT__SI__CI 0x00000011 -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTRACK01_0__SHIFT__SI 0x00000017 -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTRACK01_1__SHIFT__SI 0x00000018 -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXPWRON_B0__SHIFT__SI 0x00000013 -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXPWRON_B1__SHIFT__SI 0x00000014 -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXSEL_B0__SHIFT__SI 0x00000015 -#define MC_IO_RXCNTL1_DPHY1_D1__WCDRTXSEL_B1__SHIFT__SI 0x00000016 -#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT__SI__CI 0x00000014 -#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT__SI__CI 0x00000018 -#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT__SI__CI 0x0000001e -#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT__SI__CI 0x00000002 -#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT__SI__CI 0x0000001d -#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT__SI__CI 0x00000007 -#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT__SI__CI 0x00000006 -#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT__SI__CI 0x0000000c -#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT__SI__CI 0x00000003 -#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT__SI__CI 0x00000014 -#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT__SI__CI 0x00000018 -#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT__SI__CI 0x0000001e -#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT__SI__CI 0x00000002 -#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT__SI__CI 0x0000001d -#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT__SI__CI 0x00000007 -#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT__SI__CI 0x00000006 -#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT__SI__CI 0x0000000c -#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT__SI__CI 0x00000003 -#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT__SI__CI 0x00000014 -#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT__SI__CI 0x00000018 -#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT__SI__CI 0x0000001e -#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT__SI__CI 0x00000002 -#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT__SI__CI 0x0000001d -#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT__SI__CI 0x00000007 -#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT__SI__CI 0x00000006 -#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT__SI__CI 0x0000000c -#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT__SI__CI 0x00000003 -#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT__SI__CI 0x00000010 -#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT__SI__CI 0x00000014 -#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT__SI__CI 0x00000018 -#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT__SI__CI 0x0000001c -#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT__SI__CI 0x0000001e -#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT__SI__CI 0x00000002 -#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT__SI__CI 0x0000001d -#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT__SI__CI 0x00000004 -#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT__SI__CI 0x00000007 -#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT__SI__CI 0x00000006 -#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT__SI__CI 0x00000012 -#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT__SI__CI 0x0000000c -#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT__SI__CI 0x00000008 -#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT__SI__CI 0x00000003 -#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT__SI__CI 0x00000010 -#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT__SI__CI 0x0000001e -#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT__SI__CI 0x0000001f -#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT__SI__CI 0x00000002 -#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT__SI__CI 0x00000006 -#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT__SI__CI 0x00000004 -#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT__SI__CI 0x00000014 -#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT__SI__CI 0x00000010 -#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT__SI__CI 0x0000000d -#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT__SI__CI 0x00000008 -#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT__SI__CI 0x00000005 -#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT__SI__CI 0x00000018 -#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT__SI__CI 0x0000000c -#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT__SI__CI 0x0000001b -#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT__SI__CI 0x0000001a -#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT__SI__CI 0x00000007 -#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT__SI__CI 0x00000019 -#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT__SI__CI 0x00000017 -#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT__SI__CI 0x0000001e -#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT__SI__CI 0x0000001f -#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT__SI__CI 0x00000002 -#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT__SI__CI 0x00000006 -#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT__SI__CI 0x00000004 -#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT__SI__CI 0x00000014 -#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT__SI__CI 0x00000010 -#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT__SI__CI 0x0000000d -#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT__SI__CI 0x00000008 -#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT__SI__CI 0x00000005 -#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT__SI__CI 0x00000018 -#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT__SI__CI 0x0000000c -#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT__SI__CI 0x0000001b -#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT__SI__CI 0x0000001a -#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT__SI__CI 0x00000007 -#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT__SI__CI 0x00000019 -#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT__SI__CI 0x00000017 -#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT__SI__CI 0x00000002 -#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT__SI__CI 0x00000019 -#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT__SI__CI 0x00000006 -#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT__SI__CI 0x00000004 -#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT__SI__CI 0x00000014 -#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT__SI__CI 0x0000000c -#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT__SI__CI 0x00000010 -#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT__SI__CI 0x0000001b -#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT__SI__CI 0x00000008 -#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT__SI__CI 0x00000005 -#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT__SI__CI 0x00000018 -#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT__SI__CI 0x0000001c -#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT__SI__CI 0x0000001a -#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT__SI__CI 0x00000007 -#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT__SI__CI 0x00000002 -#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT__SI__CI 0x00000019 -#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT__SI__CI 0x00000006 -#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT__SI__CI 0x00000004 -#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT__SI__CI 0x00000014 -#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT__SI__CI 0x0000000c -#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT__SI__CI 0x00000010 -#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT__SI__CI 0x0000001b -#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT__SI__CI 0x00000008 -#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT__SI__CI 0x00000005 -#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT__SI__CI 0x00000018 -#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT__SI__CI 0x0000001c -#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT__SI__CI 0x0000001a -#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT__SI__CI 0x00000007 -#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT__SI__CI 0x00000002 -#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT__SI__CI 0x00000019 -#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT__SI__CI 0x00000006 -#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT__SI__CI 0x00000004 -#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT__SI__CI 0x00000014 -#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT__SI__CI 0x0000000c -#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT__SI__CI 0x00000010 -#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT__SI__CI 0x0000001b -#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT__SI__CI 0x00000008 -#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT__SI__CI 0x00000005 -#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT__SI__CI 0x00000018 -#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT__SI__CI 0x0000001c -#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT__SI__CI 0x0000001a -#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT__SI__CI 0x00000007 -#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT__SI__CI 0x00000000 -#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT__SI__CI 0x00000002 -#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT__SI__CI 0x00000019 -#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT__SI__CI 0x00000006 -#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT__SI__CI 0x00000004 -#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT__SI__CI 0x00000014 -#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT__SI__CI 0x0000000c -#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT__SI__CI 0x00000010 -#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT__SI__CI 0x0000001b -#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT__SI__CI 0x00000008 -#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT__SI__CI 0x00000005 -#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT__SI__CI 0x00000018 -#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT__SI__CI 0x0000001c -#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT__SI__CI 0x0000001a -#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT__SI__CI 0x00000007 -#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006 -#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000 -#define MC_NPL_STATUS__D0_NDELAY__SHIFT__SI__CI 0x00000002 -#define MC_NPL_STATUS__D0_NEARLY__SHIFT__SI__CI 0x00000005 -#define MC_NPL_STATUS__D0_PDELAY__SHIFT__SI__CI 0x00000000 -#define MC_NPL_STATUS__D0_PEARLY__SHIFT__SI__CI 0x00000004 -#define MC_NPL_STATUS__D1_NDELAY__SHIFT__SI__CI 0x00000008 -#define MC_NPL_STATUS__D1_NEARLY__SHIFT__SI__CI 0x0000000b -#define MC_NPL_STATUS__D1_PDELAY__SHIFT__SI__CI 0x00000006 -#define MC_NPL_STATUS__D1_PEARLY__SHIFT__SI__CI 0x0000000a -#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT__SI__CI 0x00000012 -#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT__SI__CI 0x00000013 -#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT__SI__CI 0x00000000 -#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT__SI__CI 0x0000000c -#define MC_PHY_TIMING_2__RXC0_INV__SHIFT__SI__CI 0x00000008 -#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT__SI__CI 0x0000000d -#define MC_PHY_TIMING_2__RXC1_INV__SHIFT__SI__CI 0x00000009 -#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT__CI 0x00000018 -#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT__CI 0x00000019 -#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT__SI__CI 0x0000000e -#define MC_PHY_TIMING_2__TXC0_INV__SHIFT__SI__CI 0x0000000a -#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT__SI__CI 0x0000000f -#define MC_PHY_TIMING_2__TXC1_INV__SHIFT__SI__CI 0x0000000b -#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT__SI__CI 0x00000010 -#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT__SI__CI 0x00000011 -#define MC_PHY_TIMING_2__WR_DLY__SHIFT__SI__CI 0x00000014 -#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT__SI__CI 0x00000000 -#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT__SI__CI 0x00000004 -#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT__SI__CI 0x00000008 -#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT__SI__CI 0x0000000c -#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT__SI__CI 0x00000010 -#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT__SI__CI 0x00000014 -#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT__SI__CI 0x00000018 -#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT__SI__CI 0x0000001c -#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT__SI__CI 0x00000000 -#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT__SI__CI 0x00000004 -#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT__SI__CI 0x00000008 -#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT__SI__CI 0x0000000c -#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT__SI__CI 0x00000010 -#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT__SI__CI 0x00000014 -#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT__SI__CI 0x00000018 -#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT__SI__CI 0x0000001c -#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT__SI__CI 0x00000018 -#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT__SI__CI 0x0000000b -#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT__SI__CI 0x00000010 -#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT__SI__CI 0x0000000d -#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT__SI__CI 0x0000000c -#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT__SI__CI 0x00000001 -#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT__SI__CI 0x00000016 -#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT__SI__CI 0x0000000a -#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT__SI__CI 0x0000000f -#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT__SI__CI 0x00000017 -#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT__SI__CI 0x00000008 -#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT__SI__CI 0x00000009 -#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT__SI__CI 0x0000000e -#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT__SI__CI 0x00000000 -#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT__SI__CI 0x00000002 -#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT__SI__CI 0x00000014 -#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT__SI__CI 0x00000004 -#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT__CI 0x00000015 -#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_PMG_AUTO_CMD__ADR__SHIFT__SI__CI 0x00000000 -#define MC_PMG_CFG__DPM_WAKE__SHIFT__SI__CI 0x0000000a -#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT__SI__CI 0x00000016 -#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT__SI__CI 0x00000010 -#define MC_PMG_CFG__PREA_SRX__SHIFT__SI__CI 0x0000000d -#define MC_PMG_CFG__RFS_SRX__SHIFT__SI__CI 0x0000000c -#define MC_PMG_CFG__RST_EMRS__SHIFT__SI__CI 0x00000002 -#define MC_PMG_CFG__RST_MRS1__SHIFT__SI__CI 0x00000008 -#define MC_PMG_CFG__RST_MRS2__SHIFT__SI__CI 0x00000009 -#define MC_PMG_CFG__RST_MRS__SHIFT__SI__CI 0x00000001 -#define MC_PMG_CFG__RXPDNB__SHIFT__SI__CI 0x00000019 -#define MC_PMG_CFG__SYC_CLK__SHIFT__SI__CI 0x00000000 -#define MC_PMG_CFG__TRI_MIO__SHIFT__SI__CI 0x00000003 -#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT__SI__CI 0x00000014 -#define MC_PMG_CFG__XSR_TMR__SHIFT__SI__CI 0x00000004 -#define MC_PMG_CFG__YCLK_ON__SHIFT__CI 0x00000015 -#define MC_PMG_CFG__ZQCL_SEND__SHIFT__SI__CI 0x0000001a -#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_PMG_CMD_EMRS__ADR__SHIFT__SI__CI 0x00000000 -#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_PMG_CMD_EMRS__CSB__SHIFT__SI__CI 0x00000015 -#define MC_PMG_CMD_EMRS__END__SHIFT__SI__CI 0x00000014 -#define MC_PMG_CMD_EMRS__MOP__SHIFT__SI__CI 0x00000010 -#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_PMG_CMD_MRS1__ADR__SHIFT__SI__CI 0x00000000 -#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_PMG_CMD_MRS1__CSB__SHIFT__SI__CI 0x00000015 -#define MC_PMG_CMD_MRS1__END__SHIFT__SI__CI 0x00000014 -#define MC_PMG_CMD_MRS1__MOP__SHIFT__SI__CI 0x00000010 -#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_PMG_CMD_MRS2__ADR__SHIFT__SI__CI 0x00000000 -#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_PMG_CMD_MRS2__CSB__SHIFT__SI__CI 0x00000015 -#define MC_PMG_CMD_MRS2__END__SHIFT__SI__CI 0x00000014 -#define MC_PMG_CMD_MRS2__MOP__SHIFT__SI__CI 0x00000010 -#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_PMG_CMD_MRS__ADR__SHIFT__SI__CI 0x00000000 -#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_PMG_CMD_MRS__CSB__SHIFT__SI__CI 0x00000015 -#define MC_PMG_CMD_MRS__END__SHIFT__SI__CI 0x00000014 -#define MC_PMG_CMD_MRS__MOP__SHIFT__SI__CI 0x00000010 -#define MC_PWRMGT__MC_PULSE_EN__SHIFT__CI__VI 0x0000000a -#define MC_PWRMGT__MC_PULSE_PERIOD__SHIFT__CI__VI 0x00000000 -#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_RD_CB__DUMMY__SHIFT__SI 0x00000010 -#define MC_RD_CB__ENABLE__SHIFT 0x00000000 -#define MC_RD_CB__LAZY_TIMER__SHIFT 0x0000000b -#define MC_RD_CB__MAX_BURST__SHIFT 0x00000007 -#define MC_RD_CB__PRESCALE__SHIFT 0x00000001 -#define MC_RD_CB__STALL_MODE__SHIFT 0x00000004 -#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_RD_DB__DUMMY__SHIFT__SI 0x00000010 -#define MC_RD_DB__ENABLE__SHIFT 0x00000000 -#define MC_RD_DB__LAZY_TIMER__SHIFT 0x0000000b -#define MC_RD_DB__MAX_BURST__SHIFT 0x00000007 -#define MC_RD_DB__PRESCALE__SHIFT 0x00000001 -#define MC_RD_DB__STALL_MODE__SHIFT 0x00000004 -#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x00000000 -#define MC_RD_GRP_EXT__TC0__SHIFT 0x00000004 -#define MC_RD_GRP_GFX__ACPG__SHIFT__CI__VI 0x0000000c -#define MC_RD_GRP_GFX__ACPO__SHIFT__CI__VI 0x00000010 -#define MC_RD_GRP_GFX__CP__SHIFT 0x00000000 -#define MC_RD_GRP_GFX__IA__SHIFT__CI__VI 0x00000008 -#define MC_RD_GRP_GFX__SH0__SHIFT__SI 0x00000004 -#define MC_RD_GRP_GFX__SH1__SHIFT__SI 0x0000000c -#define MC_RD_GRP_GFX__SH__SHIFT__CI__VI 0x00000004 -#define MC_RD_GRP_GFX__VGT__SHIFT__SI 0x00000008 -#define MC_RD_GRP_GFX__XDMAM__SHIFT__CI 0x00000014 -#define MC_RD_GRP_GFX__XDMAM__SHIFT__SI 0x00000010 -#define MC_RD_GRP_LCL__CB0__SHIFT 0x0000000c -#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x00000010 -#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x00000014 -#define MC_RD_GRP_LCL__DB0__SHIFT 0x00000018 -#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x0000001c -#define MC_RD_GRP_OTH__DRMDMA0__SHIFT__SI 0x00000004 -#define MC_RD_GRP_OTH__HDP__SHIFT 0x00000008 -#define MC_RD_GRP_OTH__SAM__SHIFT__CI 0x0000001c -#define MC_RD_GRP_OTH__SDMA0__SHIFT__CI__VI 0x00000004 -#define MC_RD_GRP_OTH__SEM__SHIFT 0x0000000c -#define MC_RD_GRP_OTH__SPU__SHIFT__SI 0x0000001c -#define MC_RD_GRP_OTH__UMC__SHIFT 0x00000010 -#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 -#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x00000018 -#define MC_RD_GRP_OTH__UVD__SHIFT 0x00000014 -#define MC_RD_GRP_SYS__DMIF__SHIFT 0x0000000c -#define MC_RD_GRP_SYS__DRMDMA1__SHIFT__SI 0x00000008 -#define MC_RD_GRP_SYS__MCIF__SHIFT 0x00000010 -#define MC_RD_GRP_SYS__RLC__SHIFT 0x00000000 -#define MC_RD_GRP_SYS__SDMA1__SHIFT__CI__VI 0x00000008 -#define MC_RD_GRP_SYS__SMU__SHIFT 0x00000014 -#define MC_RD_GRP_SYS__VCEU__SHIFT 0x0000001c -#define MC_RD_GRP_SYS__VCE__SHIFT 0x00000018 -#define MC_RD_GRP_SYS__VMC__SHIFT 0x00000004 -#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_RD_HUB__DUMMY__SHIFT__SI 0x00000010 -#define MC_RD_HUB__ENABLE__SHIFT 0x00000000 -#define MC_RD_HUB__LAZY_TIMER__SHIFT 0x0000000b -#define MC_RD_HUB__MAX_BURST__SHIFT 0x00000007 -#define MC_RD_HUB__PRESCALE__SHIFT 0x00000001 -#define MC_RD_HUB__STALL_MODE__SHIFT 0x00000004 -#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_RD_TC0__DUMMY__SHIFT__SI 0x00000010 -#define MC_RD_TC0__ENABLE__SHIFT 0x00000000 -#define MC_RD_TC0__LAZY_TIMER__SHIFT 0x0000000b -#define MC_RD_TC0__MAX_BURST__SHIFT 0x00000007 -#define MC_RD_TC0__PRESCALE__SHIFT 0x00000001 -#define MC_RD_TC0__STALL_MODE__SHIFT 0x00000004 -#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_RD_TC1__DUMMY__SHIFT__SI 0x00000010 -#define MC_RD_TC1__ENABLE__SHIFT 0x00000000 -#define MC_RD_TC1__LAZY_TIMER__SHIFT 0x0000000b -#define MC_RD_TC1__MAX_BURST__SHIFT 0x00000007 -#define MC_RD_TC1__PRESCALE__SHIFT 0x00000001 -#define MC_RD_TC1__STALL_MODE__SHIFT 0x00000004 -#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x00000010 -#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x00000008 -#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x00000000 -#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x00000000 -#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x00000008 -#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x00000010 -#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x00000000 -#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x00000001 -#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x00000000 -#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x00000000 -#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0x0000000a -#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x00000008 -#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x00000000 -#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0x0000000b -#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x00000008 -#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x0000000d -#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x00000009 -#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x00000010 -#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x00000011 -#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0x0000000f -#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x00000014 -#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x00000008 -#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x00000000 -#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x00000008 -#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x00000000 -#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x00000008 -#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x00000000 -#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x00000003 -#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x00000002 -#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x00000005 -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x00000009 -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0x0000000e -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x00000013 -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x00000018 -#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 -#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x00000004 -#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x00000000 -#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 -#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 -#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 -#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 -#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x00000007 -#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x00000000 -#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x00000003 -#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x00000001 -#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 -#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 -#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 -#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 -#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_CAS_TIMING__TCL__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_CAS_TIMING__TR2R__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_CAS_TIMING__TR2W__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_CAS_TIMING__TW2R__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_CMD__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_CMD__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_CMD__ADR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_CMD__CHAN0__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_CMD__CHAN1__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_CMD__CSB__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_CMD__END__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_CMD__MOP__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT__CI 0x00000000 -#define MC_SEQ_CNTL_2__DRST_PD__SHIFT__CI 0x00000005 -#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_CNTL_2__DRST_PU__SHIFT__CI 0x00000004 -#define MC_SEQ_CNTL_2__PIPE_DELAY_IN_1_D0__SHIFT__SI 0x00000001 -#define MC_SEQ_CNTL_2__PIPE_DELAY_IN_1_D1__SHIFT__SI 0x00000003 -#define MC_SEQ_CNTL_2__PIPE_DELAY_OUT_1_D0__SHIFT__SI 0x00000000 -#define MC_SEQ_CNTL_2__PIPE_DELAY_OUT_1_D1__SHIFT__SI 0x00000002 -#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT__SI__CI 0x00000016 -#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_CNTL_3__CAC_EN__SHIFT__CI 0x0000001f -#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT__CI 0x00000015 -#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT__CI 0x00000018 -#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT__CI 0x00000017 -#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT__CI 0x00000014 -#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT__CI 0x0000001e -#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT__CI 0x00000003 -#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT__CI 0x00000009 -#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT__CI 0x00000000 -#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT__CI 0x00000006 -#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT__CI 0x00000016 -#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT__CI 0x0000000c -#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT__CI 0x0000000d -#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT__CI 0x00000010 -#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_CNTL__DAT_INV__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_CNTL__MSK_DF1__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_CNTL__PIPE_DELAY_IN_D0__SHIFT__SI 0x0000000b -#define MC_SEQ_CNTL__PIPE_DELAY_IN_D1__SHIFT__SI 0x0000000d -#define MC_SEQ_CNTL__PIPE_DELAY_OUT_D0__SHIFT__SI 0x0000000a -#define MC_SEQ_CNTL__PIPE_DELAY_OUT_D1__SHIFT__SI 0x0000000c -#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_CNTL__SAFE_MODE__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT__CI 0x00000005 -#define MC_SEQ_DLL_STBY_LP__EN__SHIFT__CI 0x00000000 -#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT__CI 0x00000018 -#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT__CI 0x00000003 -#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT__CI 0x00000004 -#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT__CI 0x00000008 -#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT__CI 0x00000010 -#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT__CI 0x0000000c -#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT__CI 0x00000001 -#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT__CI 0x00000002 -#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT__CI 0x00000005 -#define MC_SEQ_DLL_STBY__EN__SHIFT__CI 0x00000000 -#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT__CI 0x00000018 -#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT__CI 0x00000003 -#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT__CI 0x00000004 -#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT__CI 0x00000008 -#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT__CI 0x00000010 -#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT__CI 0x0000000c -#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT__CI 0x00000001 -#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT__CI 0x00000002 -#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT__SI__CI 0x0000001a -#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_DRAM_2__CS_BY16__SHIFT__SI__CI 0x0000001f -#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT__SI__CI 0x0000001b -#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_DRAM_2__DLL_EST__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_DRAM_2__DQM_EST__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_DRAM_2__PLL_EST__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_DRAM_2__RD_DQS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_DRAM_2__WR_DQS__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_DRAM__ADR_2CK__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_DRAM__ADR_DF1__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_DRAM__ADR_MUX__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_DRAM__AP8__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_DRAM__BO4__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_DRAM__CKE_ACT__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_DRAM__CKE_DYN__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_DRAM__DAT_DF1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_DRAM__DAT_INV__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_DRAM__DLL_CLR__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_DRAM__DLL_CNT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_DRAM__DQM_ACT__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_DRAM__DQM_DF1__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_DRAM__DQS_DF1__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_DRAM__INV_ACM__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_DRAM__ODT_ACT__SHIFT__SI__CI 0x0000001b -#define MC_SEQ_DRAM__ODT_ENB__SHIFT__SI__CI 0x0000001a -#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT__CI 0x0000001f -#define MC_SEQ_DRAM__RST_CTL__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_DRAM__STB_CNT__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_DRAM__TRI_CKE__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT__CI 0x0000001c -#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT__CI 0x00000014 -#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT__CI 0x00000018 -#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT__CI 0x00000000 -#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT__CI 0x00000000 -#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT__CI 0x00000000 -#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT__CI 0x00000000 -#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT__CI 0x00000000 -#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT__CI 0x00000001 -#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT__CI 0x00000014 -#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT__CI 0x0000000c -#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT__CI 0x00000004 -#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT__CI 0x00000010 -#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT__CI 0x00000002 -#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT__CI 0x00000003 -#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT__CI 0x00000000 -#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT__CI 0x00000001 -#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT__CI 0x00000014 -#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT__CI 0x0000000c -#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT__CI 0x00000004 -#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT__CI 0x00000010 -#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT__CI 0x00000002 -#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT__CI 0x00000003 -#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RDBI__MASK__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_REDC__EDC__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_IO_RWORD0__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RWORD1__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RWORD2__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RWORD3__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RWORD4__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RWORD5__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RWORD6__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_IO_RWORD7__RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC0__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC1__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC3__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC4__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC5__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC6__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC7__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC8__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC9__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_MISC_TIMING2__FAW__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_MISC_TIMING__TRFC__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MISC_TIMING__TRP__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_PERF_CNTL__CNTL__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT__CI 0x0000000f -#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT__CI 0x00000000 -#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT__CI 0x00000001 -#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT__CI 0x00000007 -#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT__CI 0x0000000d -#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT__CI 0x0000000e -#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT__CI 0x00000009 -#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT__CI 0x00000008 -#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT__CI 0x0000000a -#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT__CI 0x0000000c -#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT__CI 0x0000000b -#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT__CI 0x00000018 -#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT__CI 0x00000017 -#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT__CI 0x00000000 -#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT__CI 0x00000013 -#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT__CI 0x00000015 -#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT__CI 0x00000014 -#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT__CI 0x00000010 -#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT__CI 0x00000018 -#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT__CI 0x00000017 -#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT__CI 0x00000000 -#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT__CI 0x00000013 -#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT__CI 0x00000015 -#define MC_SEQ_PMG_DVS_CMD__END__SHIFT__CI 0x00000014 -#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT__CI 0x00000010 -#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT__CI 0x00000000 -#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT__CI 0x00000001 -#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT__CI 0x00000000 -#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT__CI 0x00000001 -#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT__SI__CI 0x0000001f -#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT__SI__CI 0x0000001f -#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT__CI 0x00000018 -#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT__CI 0x00000018 -#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_PMG_TIMING__TCKE__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RAS_TIMING__TRC__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RAS_TIMING__TRRD__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_SREG_READ__DATA__SHIFT__CI 0x00000000 -#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT__CI 0x00000000 -#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT__CI 0x00000008 -#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT__CI 0x0000000c -#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT__CI 0x0000001b -#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT__CI 0x0000001c -#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT__SI__CI 0x0000001a -#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_STATUS_M__SLF_D0__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_STATUS_M__SLF_D1__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_SUP_CNTL__RUN__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_PGM__CNTL__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_SUP_R_PGM__PGM__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT__SI__CI 0x0000001a -#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TCG_CNTL__DONE__SHIFT__SI__CI 0x0000001f -#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT__SI__CI 0x00000016 -#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT__CI 0x0000001d -#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT__CI 0x0000001c -#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TCG_CNTL__MOP__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TCG_CNTL__RESET__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_TCG_CNTL__START__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TIMER_RD__COUNTER__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TIMER_WR__COUNTER__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT__SI__CI 0x00000016 -#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT__CI 0x0000001a -#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT__CI 0x0000001b -#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT__SI__CI 0x00000016 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT__CI 0x0000001a -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT__CI 0x0000001b -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT__SI__CI 0x0000001a -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT__SI__CI 0x0000001b -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT__SI__CI 0x00000016 -#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT__SI__CI 0x0000001f -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT__SI__CI 0x00000016 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT__CI 0x0000001a -#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT__CI 0x0000001b -#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT__SI__CI 0x00000012 -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT__SI__CI 0x00000013 -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT__SI__CI 0x00000016 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT__SI__CI 0x00000019 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT__SI__CI 0x00000017 -#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT__CI 0x0000001a -#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT__CI 0x0000001b -#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT__SI__CI 0x00000011 -#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_TSM_CTRL__DONE0__SHIFT__CI 0x0000000c -#define MC_SEQ_TSM_CTRL__DONE1__SHIFT__CI 0x0000000d -#define MC_SEQ_TSM_CTRL__DONE__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT__CI 0x0000000b -#define MC_SEQ_TSM_CTRL__ERR__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_TSM_CTRL__INVERT__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT__SI__CI 0x00000007 -#define MC_SEQ_TSM_CTRL__POINTER__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_TSM_CTRL__START__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_CTRL__STEP__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TSM_DBI__DBI__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_EDC__EDC__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TSM_GCNT__TESTS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT__CI 0x00000014 -#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT__CI 0x0000001a -#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_NCNT__TESTS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TSM_OCNT__TESTS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TSM_WCDR__WCDR__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT__SI__CI 0x0000000e -#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT__SI__CI 0x00000015 -#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT__SI__CI 0x0000000d -#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT__SI__CI 0x0000000f -#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT__SI__CI 0x00000003 -#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT__SI__CI 0x00000001 -#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT__SI__CI 0x00000002 -#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT__SI__CI 0x00000005 -#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT__SI__CI 0x00000006 -#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT__SI__CI 0x00000014 -#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT__SI__CI 0x0000000a -#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT__SI__CI 0x0000001d -#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT__SI__CI 0x0000000b -#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT__SI__CI 0x0000001e -#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT__SI__CI 0x00000009 -#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT__SI__CI 0x00000000 -#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT__SI__CI 0x00000004 -#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT__SI__CI 0x00000008 -#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT__SI__CI 0x00000018 -#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT__SI__CI 0x0000001c -#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT__SI__CI 0x0000000c -#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT__SI__CI 0x00000010 -#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT__SI__CI 0x00000014 -#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x00000000 -#define MC_SHARED_BLACKOUT_CNTL__GFX_CLEAR__SHIFT__SI 0x00000005 -#define MC_SHARED_BLACKOUT_CNTL__GFX_STALL__SHIFT__SI 0x00000004 -#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x00000000 -#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x00000004 -#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x00000008 -#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0x0000000c -#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x00000000 -#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT__SI__CI 0x00000008 -#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT__SI__CI 0x00000010 -#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT__SI__CI 0x00000018 -#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT__SI__CI 0x00000008 -#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT__SI__CI 0x00000010 -#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT__SI__CI 0x00000018 -#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT__SI__CI 0x00000010 -#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT__SI__CI 0x00000010 -#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT__SI__CI 0x00000004 -#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT__SI__CI 0x0000001c -#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT__SI__CI 0x0000001d -#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT__SI__CI 0x0000001e -#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT__SI__CI 0x0000000c -#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT__SI__CI 0x00000008 -#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT__SI__CI 0x00000004 -#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT__SI__CI 0x0000001c -#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT__SI__CI 0x0000001d -#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT__SI__CI 0x0000001e -#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT__SI__CI 0x0000000c -#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT__SI__CI 0x00000008 -#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT__SI__CI 0x0000001c -#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT__SI__CI 0x00000010 -#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT__SI__CI 0x0000000a -#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT__SI__CI 0x00000001 -#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT__SI__CI 0x00000008 -#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT__SI__CI 0x00000004 -#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT__SI__CI 0x00000009 -#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT__SI__CI 0x0000000b -#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT__SI__CI 0x0000001c -#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT__SI__CI 0x00000010 -#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT__SI__CI 0x0000000a -#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT__SI__CI 0x00000001 -#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT__SI__CI 0x00000008 -#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT__SI__CI 0x00000000 -#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT__SI__CI 0x00000004 -#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT__SI__CI 0x00000009 -#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT__SI__CI 0x0000000b -#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT__SI__CI 0x00000010 -#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT__SI__CI 0x00000018 -#define MC_TSM_DEBUG_BKPT__DATA__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_FLAG__DATA__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_GCNT__DATA__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_MISC__FLAG__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT__SI__CI 0x00000008 -#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT__SI__CI 0x0000000c -#define MC_TSM_DEBUG_ST01__DATA__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_ST23__DATA__SHIFT__SI__CI 0x00000000 -#define MC_TSM_DEBUG_ST45__DATA__SHIFT__SI__CI 0x00000000 -#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x00000000 -#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x00000000 -#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x00000008 -#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x00000009 -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x00000002 -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x00000004 -#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x00000006 -#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 -#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x00000000 -#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x00000010 -#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT__CI__VI 0x0000001d -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT__CI__VI 0x0000001c -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__CI__VI 0x00000018 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__CI__VI 0x00000008 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__CI__VI 0x00000010 -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT__CI__VI 0x00000000 -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT__CI__VI 0x00000000 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__CI__VI 0x00000019 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__CI__VI 0x00000018 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__CI__VI 0x00000000 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__CI__VI 0x00000008 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__CI__VI 0x0000001a -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__CI__VI 0x00000010 -#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c -#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 -#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f -#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT__CI__VI 0x00000013 -#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MB_L1_TLB0_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MB_L1_TLB1_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c -#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 -#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f -#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT__CI__VI 0x00000013 -#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MB_L1_TLB2_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c -#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 -#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f -#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT__CI__VI 0x00000013 -#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MB_L1_TLB3_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 -#define MC_VM_MB_SECURE__ENABLE_INSECURE_READS_WHEN_SECURE__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c -#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 -#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f -#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT__CI__VI 0x00000013 -#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MD_L1_TLB0_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c -#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 -#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f -#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT__CI__VI 0x00000013 -#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MD_L1_TLB1_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c -#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 -#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f -#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT__CI__VI 0x00000013 -#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MD_L1_TLB2_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c -#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 -#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f -#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT__CI__VI 0x00000013 -#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MD_L1_TLB3_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 -#define MC_VM_MD_L1_TLB4_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT__SI 0x0000000c -#define MC_VM_MD_L1_TLB4_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT__SI 0x00000009 -#define MC_VM_MD_L1_TLB4_DEBUG__INVALIDATE_L1_TLB__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB4_DEBUG__L1_TLB_DEBUG__SHIFT__SI 0x0000000f -#define MC_VM_MD_L1_TLB4_DEBUG__SEND_FREE_AT_RTN__SHIFT__SI 0x00000008 -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MD_L1_TLB4_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB4_STATUS__BUSY__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB5_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT__SI 0x0000000c -#define MC_VM_MD_L1_TLB5_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT__SI 0x00000009 -#define MC_VM_MD_L1_TLB5_DEBUG__INVALIDATE_L1_TLB__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB5_DEBUG__L1_TLB_DEBUG__SHIFT__SI 0x0000000f -#define MC_VM_MD_L1_TLB5_DEBUG__SEND_FREE_AT_RTN__SHIFT__SI 0x00000008 -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__CLEAR_ALL_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000004 -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__CLEAR_SELECTED_L1_PERFORMANCE_COUNTER__SHIFT__SI \ - 0x00000003 -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__ENABLE_L1_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__L1_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000005 -#define MC_VM_MD_L1_TLB5_PERF_COUNTER_STATUS__L1_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define MC_VM_MD_L1_TLB5_STATUS__BUSY__SHIFT__SI 0x00000000 -#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 -#define MC_VM_MD_SECURE__ENABLE_INSECURE_READS_WHEN_SECURE__SHIFT__SI 0x00000000 -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x00000007 -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x00000006 -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x00000001 -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x00000003 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x00000005 -#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT__CI__VI 0x00000000 -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_WR_CB__DUMMY__SHIFT__SI 0x00000010 -#define MC_WR_CB__ENABLE__SHIFT 0x00000000 -#define MC_WR_CB__LAZY_TIMER__SHIFT 0x0000000b -#define MC_WR_CB__MAX_BURST__SHIFT 0x00000007 -#define MC_WR_CB__PRESCALE__SHIFT 0x00000001 -#define MC_WR_CB__STALL_MODE__SHIFT 0x00000004 -#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_WR_DB__DUMMY__SHIFT__SI 0x00000010 -#define MC_WR_DB__ENABLE__SHIFT 0x00000000 -#define MC_WR_DB__LAZY_TIMER__SHIFT 0x0000000b -#define MC_WR_DB__MAX_BURST__SHIFT 0x00000007 -#define MC_WR_DB__PRESCALE__SHIFT 0x00000001 -#define MC_WR_DB__STALL_MODE__SHIFT 0x00000004 -#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x00000000 -#define MC_WR_GRP_EXT__TC0__SHIFT 0x00000004 -#define MC_WR_GRP_GFX__ACPG__SHIFT__CI__VI 0x00000008 -#define MC_WR_GRP_GFX__ACPO__SHIFT__CI__VI 0x0000000c -#define MC_WR_GRP_GFX__CP__SHIFT 0x00000000 -#define MC_WR_GRP_GFX__SH0__SHIFT__SI 0x00000004 -#define MC_WR_GRP_GFX__SH1__SHIFT__SI 0x00000008 -#define MC_WR_GRP_GFX__SH__SHIFT__CI__VI 0x00000004 -#define MC_WR_GRP_GFX__XDMAM__SHIFT__CI 0x00000014 -#define MC_WR_GRP_GFX__XDMAM__SHIFT__SI 0x00000010 -#define MC_WR_GRP_GFX__XDMA__SHIFT__CI 0x00000010 -#define MC_WR_GRP_GFX__XDMA__SHIFT__SI 0x0000000c -#define MC_WR_GRP_LCL__BCAST0__SHIFT__SI 0x00000018 -#define MC_WR_GRP_LCL__CB0__SHIFT 0x00000000 -#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x00000004 -#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x00000008 -#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x0000001c -#define MC_WR_GRP_LCL__DB0__SHIFT 0x0000000c -#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x00000010 -#define MC_WR_GRP_LCL__SX0__SHIFT 0x00000014 -#define MC_WR_GRP_OTH__DRMDMA0__SHIFT__SI 0x00000004 -#define MC_WR_GRP_OTH__HDP__SHIFT 0x00000008 -#define MC_WR_GRP_OTH__SDMA0__SHIFT__CI__VI 0x00000004 -#define MC_WR_GRP_OTH__SEM__SHIFT 0x0000000c -#define MC_WR_GRP_OTH__UMC__SHIFT 0x00000010 -#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 -#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x0000001c -#define MC_WR_GRP_OTH__UVD__SHIFT 0x00000014 -#define MC_WR_GRP_OTH__XDP__SHIFT 0x00000018 -#define MC_WR_GRP_SYS__DRMDMA1__SHIFT__SI 0x00000010 -#define MC_WR_GRP_SYS__IH__SHIFT 0x00000000 -#define MC_WR_GRP_SYS__MCIF__SHIFT 0x00000004 -#define MC_WR_GRP_SYS__RLC__SHIFT 0x00000008 -#define MC_WR_GRP_SYS__SAM__SHIFT__CI 0x0000000c -#define MC_WR_GRP_SYS__SDMA1__SHIFT__CI__VI 0x00000014 -#define MC_WR_GRP_SYS__SMU__SHIFT__CI__VI 0x00000010 -#define MC_WR_GRP_SYS__SMU__SHIFT__SI 0x00000014 -#define MC_WR_GRP_SYS__SPU__SHIFT__SI 0x0000000c -#define MC_WR_GRP_SYS__VCEU__SHIFT 0x0000001c -#define MC_WR_GRP_SYS__VCE__SHIFT 0x00000018 -#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_WR_HUB__DUMMY__SHIFT__SI 0x00000010 -#define MC_WR_HUB__ENABLE__SHIFT 0x00000000 -#define MC_WR_HUB__LAZY_TIMER__SHIFT 0x0000000b -#define MC_WR_HUB__MAX_BURST__SHIFT 0x00000007 -#define MC_WR_HUB__PRESCALE__SHIFT 0x00000001 -#define MC_WR_HUB__STALL_MODE__SHIFT 0x00000004 -#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_WR_TC0__DUMMY__SHIFT__SI 0x00000010 -#define MC_WR_TC0__ENABLE__SHIFT 0x00000000 -#define MC_WR_TC0__LAZY_TIMER__SHIFT 0x0000000b -#define MC_WR_TC0__MAX_BURST__SHIFT 0x00000007 -#define MC_WR_TC0__PRESCALE__SHIFT 0x00000001 -#define MC_WR_TC0__STALL_MODE__SHIFT 0x00000004 -#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 -#define MC_WR_TC1__DUMMY__SHIFT__SI 0x00000010 -#define MC_WR_TC1__ENABLE__SHIFT 0x00000000 -#define MC_WR_TC1__LAZY_TIMER__SHIFT 0x0000000b -#define MC_WR_TC1__MAX_BURST__SHIFT 0x00000007 -#define MC_WR_TC1__PRESCALE__SHIFT 0x00000001 -#define MC_WR_TC1__STALL_MODE__SHIFT 0x00000004 -#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f -#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x00000006 -#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x00000001 -#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x00000000 -#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x00000003 -#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x00000002 -#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x00000000 -#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x00000004 -#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x00000008 -#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0x0000000c -#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x00000010 -#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x00000014 -#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x00000018 -#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x0000001c -#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x00000002 -#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x00000001 -#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x00000000 -#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x00000000 -#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x00000002 -#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x00000004 -#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT__SI__CI 0x0000001c -#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT__SI__CI 0x00000018 -#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT__SI__CI 0x0000001a -#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT__SI__CI 0x0000000c -#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT__SI__CI 0x00000008 -#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT__SI__CI 0x00000010 -#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT__SI__CI 0x00000008 -#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT__SI__CI 0x00000010 -#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT__SI__CI 0x00000018 -#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT__SI__CI 0x00000008 -#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT__SI__CI 0x00000010 -#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT__SI__CI 0x00000018 -#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT__SI__CI 0x00000000 -#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x00000000 -#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x00000008 -#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x00000010 -#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x00000018 -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x00000000 -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x00000008 -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x00000010 -#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x00000018 -#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x00000000 -#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x00000008 -#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x00000010 -#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x00000018 -#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x00000010 -#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x00000000 -#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x00000008 -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x00000000 -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x00000008 -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x00000010 -#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x00000018 -#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x00000000 -#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x00000008 -#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x00000001 -#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x00000000 -#define MC_XBAR_SPARE0__BIT__SHIFT 0x00000000 -#define MC_XBAR_SPARE1__BIT__SHIFT 0x00000000 -#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x00000001 -#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x00000003 -#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x00000000 -#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x00000000 -#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x00000008 -#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x00000010 -#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x00000018 -#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x00000000 -#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x00000008 -#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x00000010 -#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x00000018 -#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x00000000 -#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x00000008 -#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0x0000000a -#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x00000004 -#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x00000007 -#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0x0000000e -#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x00000000 -#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x00000000 -#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x00000011 -#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x00000008 -#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x00000010 -#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x00000019 -#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x00000000 -#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x00000011 -#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x00000008 -#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x00000010 -#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x00000019 -#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x00000012 -#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x00000013 -#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x00000006 -#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x00000000 -#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0x0000000c -#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x00000000 -#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x00000019 -#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x0000001a -#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x00000017 -#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x00000018 -#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x00000008 -#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x00000000 -#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x0000001e -#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x0000001f -#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x00000010 -#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x0000001b -#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x0000001d -#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x00000012 -#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x00000011 -#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x00000010 -#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0x0000000f -#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x00000013 -#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x00000000 -#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x00000008 -#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x00000000 -#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x00000014 -#define MC_XPB_LB_ADDR__MASK0__SHIFT 0x0000000a -#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x0000001a -#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x00000000 -#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x00000000 -#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x00000008 -#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x00000010 -#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x00000018 -#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x0000001f -#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR0__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR1__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR2__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR3__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR4__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR5__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR6__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR7__VALID__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0x0000000b -#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0x0000000a -#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x00000004 -#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x00000007 -#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x00000006 -#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x00000009 -#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0x0000000c -#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x00000010 -#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0x0000000e -#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x00000008 -#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0x0000000f -#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x00000000 -#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0x0000000d -#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0x0000000c -#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x00000000 -#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x00000002 -#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x00000000 -#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x00000000 -#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x00000006 -#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0x0000000c -#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x00000017 -#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x00000000 -#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000001 -#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x00000015 -#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0x0000000f -#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x00000011 -#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x00000013 -#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000008 -#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x00000016 -#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x00000010 -#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x00000012 -#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x00000014 -#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x00000000 -#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x00000000 -#define MC_XPB_STICKY__BITS__SHIFT 0x00000000 -#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x00000013 -#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0x0000000a -#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x00000010 -#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0x0000000f -#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0x0000000d -#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0x0000000c -#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0x0000000b -#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x00000011 -#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x00000012 -#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0x0000000e -#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x00000001 -#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x00000008 -#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x00000004 -#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x00000006 -#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x00000003 -#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x00000002 -#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x00000007 -#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x00000005 -#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x00000009 -#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x00000000 -#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x00000000 -#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x00000006 -#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0x0000000c -#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x00000000 -#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x00000006 -#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0x0000000c -#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x00000010 -#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x00000012 -#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x00000000 -#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x00000000 -#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000010 -#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000017 -#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 -#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 -#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 -#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 -#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 -#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 -#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 -#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 -#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a -#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 -#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 -#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 -#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 -#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 -#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 -#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT__CI__VI 0x00000000 -#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT__SI 0x00000014 -#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT__SI 0x00000000 -#define MICROSECOND_TIME_BASE_DIV__PPLL_REFCLK_SEL__SHIFT__SI 0x00000018 -#define MICROSECOND_TIME_BASE_DIV__PPLL_REFCLK_SOFT_RESET__SHIFT__SI 0x0000001c -#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT__SI 0x00000011 -#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT__SI 0x00000008 -#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT__SI 0x00000010 -#define MINOR_VERSION__MINOR_VERSION__SHIFT__SI 0x00000000 -#define MIN_GRANT__MIN_GNT__SHIFT 0x00000000 -#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT__CI__VI 0x00000000 -#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT__CI__VI 0x00000010 -#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT__CI__VI 0x00000008 -#define MLPS0_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT__SHIFT__CI__VI 0x0000000f -#define MLPS0_DEBUG_BUS_SIGNALS__INT_OSC_CLK__SHIFT__CI__VI 0x00000006 -#define MLPS0_DEBUG_BUS_SIGNALS__RES_OUT__SHIFT__CI__VI 0x00000000 -#define MLPS0_DEBUG_BUS_SIGNALS__SPARE__SHIFT__CI__VI 0x00000007 -#define MLPS0_DEBUG_BUS_SIGNALS__STRAP_OUTA__SHIFT__CI__VI 0x00000010 -#define MLPS0_DEBUG_BUS_SIGNALS__STRAP_OUTB__SHIFT__CI__VI 0x00000015 -#define MLPS0_DEBUG_BUS_SIGNALS__STRAP_OUTC__SHIFT__CI__VI 0x0000001a -#define MLPS0_DEBUG_BUS_SIGNALS__Y__SHIFT__CI__VI 0x00000005 -#define MLPS1_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT__SHIFT__CI__VI 0x0000000f -#define MLPS1_DEBUG_BUS_SIGNALS__INT_OSC_CLK__SHIFT__CI__VI 0x00000006 -#define MLPS1_DEBUG_BUS_SIGNALS__RES_OUT__SHIFT__CI__VI 0x00000000 -#define MLPS1_DEBUG_BUS_SIGNALS__SPARE__SHIFT__CI__VI 0x00000007 -#define MLPS1_DEBUG_BUS_SIGNALS__STRAP_OUTA__SHIFT__CI__VI 0x00000010 -#define MLPS1_DEBUG_BUS_SIGNALS__STRAP_OUTB__SHIFT__CI__VI 0x00000015 -#define MLPS1_DEBUG_BUS_SIGNALS__STRAP_OUTC__SHIFT__CI__VI 0x0000001a -#define MLPS1_DEBUG_BUS_SIGNALS__Y__SHIFT__CI__VI 0x00000005 -#define MLPS2_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT__SHIFT__CI__VI 0x0000000f -#define MLPS2_DEBUG_BUS_SIGNALS__INT_OSC_CLK__SHIFT__CI__VI 0x00000006 -#define MLPS2_DEBUG_BUS_SIGNALS__RES_OUT__SHIFT__CI__VI 0x00000000 -#define MLPS2_DEBUG_BUS_SIGNALS__SPARE__SHIFT__CI__VI 0x00000007 -#define MLPS2_DEBUG_BUS_SIGNALS__STRAP_OUTA__SHIFT__CI__VI 0x00000010 -#define MLPS2_DEBUG_BUS_SIGNALS__STRAP_OUTB__SHIFT__CI__VI 0x00000015 -#define MLPS2_DEBUG_BUS_SIGNALS__STRAP_OUTC__SHIFT__CI__VI 0x0000001a -#define MLPS2_DEBUG_BUS_SIGNALS__Y__SHIFT__CI__VI 0x00000005 -#define MLPS3_DEBUG_BUS_SIGNALS__CAP_SENSE_ENABLE_OUT__SHIFT__CI__VI 0x0000000f -#define MLPS3_DEBUG_BUS_SIGNALS__INT_OSC_CLK__SHIFT__CI__VI 0x00000006 -#define MLPS3_DEBUG_BUS_SIGNALS__RES_OUT__SHIFT__CI__VI 0x00000000 -#define MLPS3_DEBUG_BUS_SIGNALS__SPARE__SHIFT__CI__VI 0x00000007 -#define MLPS3_DEBUG_BUS_SIGNALS__STRAP_OUTA__SHIFT__CI__VI 0x00000010 -#define MLPS3_DEBUG_BUS_SIGNALS__STRAP_OUTB__SHIFT__CI__VI 0x00000015 -#define MLPS3_DEBUG_BUS_SIGNALS__STRAP_OUTC__SHIFT__CI__VI 0x0000001a -#define MLPS3_DEBUG_BUS_SIGNALS__Y__SHIFT__CI__VI 0x00000005 -#define MLPSPAD_PINSTRAPS__MLPS_EFUSE_RD_DISABLE__SHIFT__CI 0x0000000d -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_0__SHIFT__CI__VI 0x00000000 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_10__SHIFT__CI__VI 0x0000000a -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_11__SHIFT__CI__VI 0x0000000b -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_12__SHIFT__CI__VI 0x0000000c -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_14__SHIFT__CI__VI 0x0000000e -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_16__SHIFT__CI__VI 0x00000010 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_17__SHIFT__CI__VI 0x00000011 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_18__SHIFT__CI__VI 0x00000012 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_19__SHIFT__CI__VI 0x00000013 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_1__SHIFT__CI__VI 0x00000001 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_20__SHIFT__CI__VI 0x00000014 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_21__SHIFT__CI__VI 0x00000015 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_22__SHIFT__CI__VI 0x00000016 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_23__SHIFT__CI__VI 0x00000017 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_24__SHIFT__CI__VI 0x00000018 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_25__SHIFT__CI__VI 0x00000019 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_26__SHIFT__CI__VI 0x0000001a -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_27__SHIFT__CI__VI 0x0000001b -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_28__SHIFT__CI__VI 0x0000001c -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_29__SHIFT__CI__VI 0x0000001d -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_2__SHIFT__CI__VI 0x00000002 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_30__SHIFT__CI__VI 0x0000001e -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_31__SHIFT__CI__VI 0x0000001f -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_3__SHIFT__CI__VI 0x00000003 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_4__SHIFT__CI__VI 0x00000004 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_5__SHIFT__CI__VI 0x00000005 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_6__SHIFT__CI__VI 0x00000006 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_7__SHIFT__CI__VI 0x00000007 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_8__SHIFT__CI__VI 0x00000008 -#define MLPSPAD_PINSTRAPS__MLPS_ROM_EXIST__SHIFT__CI 0x0000000f -#define MLPSPAD_PINSTRAPS__MLPS_ROM_REPAIR__SHIFT__CI 0x00000009 -#define MLPS_CNTL__ADC_ENB__SHIFT__CI__VI 0x00000000 -#define MLPS_CNTL__DIFF_REC_EN__SHIFT__CI__VI 0x00000001 -#define MLPS_CNTL__SPARE__SHIFT__CI__VI 0x00000003 -#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x00000000 -#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x00000003 -#define MM_DATA__MM_DATA__SHIFT 0x00000000 -#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT__CI__VI 0x00000000 -#define MM_INDEX__MM_APER__SHIFT 0x0000001f -#define MM_INDEX__MM_OFFSET__SHIFT 0x00000000 -#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT__SI__CI 0x00000003 -#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT__SI__CI 0x00000000 -#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT__SI__CI 0x00000012 -#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT__SI__CI 0x00000013 -#define MPLL_AD_STATUS__OINT_RESET__SHIFT__SI__CI 0x00000011 -#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT__SI__CI 0x00000004 -#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT__SI__CI 0x00000007 -#define MPLL_AD_STATUS__VCTRLADC__SHIFT__SI__CI 0x00000000 -#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x00000008 -#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT__SI__CI 0x00000015 -#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT__SI__CI 0x00000014 -#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT__SI__CI 0x00000011 -#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT__SI__CI 0x0000001f -#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT__SI__CI 0x00000000 -#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT__SI__CI 0x00000010 -#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT__SI__CI 0x0000000e -#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT__SI__CI 0x0000000b -#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT__SI__CI 0x00000008 -#define MPLL_CNTL_MODE__QDR__SHIFT__SI__CI 0x0000000d -#define MPLL_CNTL_MODE__SPARE_1__SHIFT__SI__CI 0x0000000c -#define MPLL_CNTL_MODE__SPARE_2__SHIFT__SI__CI 0x00000017 -#define MPLL_CNTL_MODE__SPARE_3__SHIFT__SI__CI 0x0000001c -#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT__SI__CI 0x0000001a -#define MPLL_CNTL_MODE__SS_SSEN__SHIFT__SI__CI 0x00000018 -#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT__SI__CI 0x0000001b -#define MPLL_CONTROL__AD_BG_PWRON__SHIFT__SI__CI 0x0000000c -#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT__SI__CI 0x0000000d -#define MPLL_CONTROL__AD_PLL_RESET__SHIFT__SI__CI 0x0000000e -#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT__SI__CI 0x00000010 -#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT__SI__CI 0x00000011 -#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT__SI__CI 0x00000012 -#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT__SI__CI 0x00000014 -#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT__SI__CI 0x00000015 -#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT__SI__CI 0x00000016 -#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT__SI__CI 0x00000018 -#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT__SI__CI 0x00000019 -#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT__SI__CI 0x0000001a -#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT__SI__CI 0x0000001c -#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT__SI__CI 0x0000001d -#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT__SI__CI 0x0000001e -#define MPLL_CONTROL__GDDR_PWRON__SHIFT__SI__CI 0x00000000 -#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT__SI__CI 0x00000002 -#define MPLL_CONTROL__REFCLK_PWRON__SHIFT__SI__CI 0x00000001 -#define MPLL_CONTROL__SPARE_AD_0__SHIFT__SI__CI 0x0000000f -#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT__SI__CI 0x00000013 -#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT__SI__CI 0x00000017 -#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT__SI__CI 0x0000001b -#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT__SI__CI 0x0000001f -#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT__SI__CI 0x00000012 -#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT__SI__CI 0x00000013 -#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT__SI__CI 0x00000011 -#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT__SI__CI 0x00000004 -#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT__SI__CI 0x00000007 -#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT__SI__CI 0x00000000 -#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT__SI__CI 0x00000012 -#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT__SI__CI 0x00000013 -#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT__SI__CI 0x00000011 -#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT__SI__CI 0x00000004 -#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT__SI__CI 0x00000007 -#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT__SI__CI 0x00000000 -#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT__SI__CI 0x00000012 -#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT__SI__CI 0x00000013 -#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT__SI__CI 0x00000011 -#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT__SI__CI 0x00000004 -#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT__SI__CI 0x00000007 -#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT__SI__CI 0x00000000 -#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT__SI__CI 0x00000012 -#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT__SI__CI 0x00000013 -#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT__SI__CI 0x00000011 -#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT__SI__CI 0x00000004 -#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT__SI__CI 0x00000007 -#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT__SI__CI 0x00000000 -#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT__SI__CI 0x00000003 -#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT__SI__CI 0x00000005 -#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT__SI__CI 0x00000000 -#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT__SI__CI 0x00000004 -#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT__SI__CI 0x00000004 -#define MPLL_FUNC_CNTL_1__CLKF__SHIFT__SI__CI 0x00000010 -#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT__SI__CI 0x00000002 -#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT__SI__CI 0x0000001c -#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT__SI__CI 0x00000000 -#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT__SI__CI 0x00000011 -#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT__SI__CI 0x0000001b -#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT__CI 0x00000010 -#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT__SI__CI 0x00000014 -#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT__SI__CI 0x00000007 -#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT__SI__CI 0x0000000c -#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT__CI 0x0000000f -#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT__SI__CI 0x00000002 -#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT__SI__CI 0x0000000a -#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT__CI 0x0000000e -#define MPLL_FUNC_CNTL_2__SPARE_0__SHIFT__SI 0x0000000e -#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT__SI__CI 0x00000003 -#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT__SI__CI 0x00000004 -#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT__SI__CI 0x00000006 -#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT__SI__CI 0x00000005 -#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT__SI__CI 0x00000009 -#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT__SI__CI 0x00000008 -#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT__SI__CI 0x00000001 -#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT__SI__CI 0x00000000 -#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT__SI__CI 0x00000008 -#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT__SI__CI 0x00000010 -#define MPLL_FUNC_CNTL__BWCTRL__SHIFT__SI__CI 0x00000014 -#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT__SI__CI 0x0000001e -#define MPLL_FUNC_CNTL__SPARE_0__SHIFT__SI__CI 0x00000005 -#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT__SI__CI 0x00000000 -#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT__SI__CI 0x00000004 -#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT__SI__CI 0x00000008 -#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT__SI__CI 0x0000000c -#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT__SI__CI 0x00000010 -#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT__SI__CI 0x00000014 -#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT__SI__CI 0x00000018 -#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT__SI__CI 0x0000001c -#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT__SI__CI 0x00000008 -#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT__SI__CI 0x0000000c -#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT__SI__CI 0x00000010 -#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT__SI__CI 0x00000014 -#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT__SI__CI 0x00000018 -#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT__SI__CI 0x0000001c -#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT__SI__CI 0x00000000 -#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT__SI__CI 0x00000004 -#define MPLL_SS1__CLKV__SHIFT__SI__CI 0x00000000 -#define MPLL_SS1__SPARE__SHIFT__SI__CI 0x0000001a -#define MPLL_SS2__CLKS__SHIFT__SI__CI 0x00000000 -#define MPLL_SS2__SPARE__SHIFT__SI__CI 0x0000000c -#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT__SI__CI 0x00000000 -#define MPLL_TIME__MPLL_RESET_TIME__SHIFT__SI__CI 0x00000010 -#define MPRD_BUF_SIZE__HEIGHT__SHIFT__SI 0x00000010 -#define MPRD_BUF_SIZE__PITCH__SHIFT__SI 0x00000000 -#define MPRD_BUF_WIDTH__WIDTH__SHIFT__SI 0x00000000 -#define MPRD_BYPASS_PITCH__INTRA_SURFACE_PITCH__SHIFT__SI 0x00000000 -#define MPRD_BYPASS_PITCH__NON_INTRA_SURFACE_PITCH__SHIFT__SI 0x00000010 -#define MPRD_CNTRL__ADDR_MODE__SHIFT__SI 0x00000002 -#define MPRD_CNTRL__BYPASS_SWAP_UV__SHIFT__SI 0x00000003 -#define MPRD_CNTRL__DROP_REF_BUF_WRITES_DIS__SHIFT__SI 0x0000000b -#define MPRD_CNTRL__DROP_REF_BUF_WRITES__SHIFT__SI 0x0000000a -#define MPRD_CNTRL__IDCT_OVERFLOW_DISCARD_DIS__SHIFT__SI 0x00000004 -#define MPRD_CNTRL__MPRD_DBW_ADDR_MODE__SHIFT__SI 0x00000007 -#define MPRD_CNTRL__MPRD_DBW_EN__SHIFT__SI 0x00000005 -#define MPRD_CNTRL__MPRD_DBW_FIELD_FORMAT__SHIFT__SI 0x00000006 -#define MPRD_CNTRL__OP_MODE__SHIFT__SI 0x00000000 -#define MPRD_CNTRL__WRITE_CLEAN_TIMER__SHIFT__SI 0x0000000d -#define MPRD_CNTRL__WRPATH_MEM_PTR_RESET__SHIFT__SI 0x0000000c -#define MPRD_DBW_BUF_SIZE__DBW_HEIGHT__SHIFT__SI 0x00000010 -#define MPRD_DBW_BUF_SIZE__DBW_PITCH__SHIFT__SI 0x00000000 -#define MPRD_HW_DEBUG__MPRD_HW_DEBUG__SHIFT__SI 0x00000000 -#define MPRD_OUTOFRANGE_PIXELS__CHROMA_PIXELS__SHIFT__SI 0x00000008 -#define MPRD_OUTOFRANGE_PIXELS__LUMA_PIXELS__SHIFT__SI 0x00000000 -#define MPRD_STATUS__IDCT_MB_OUT_OF_SYNC__SHIFT__SI 0x00000002 -#define MPRD_STATUS__IDCT_OVERFLOW_ERROR__SHIFT__SI 0x00000004 -#define MPRD_STATUS__IDCT_PEL_OUT_OF_SYNC__SHIFT__SI 0x00000003 -#define MPRD_STATUS__IDCT_PIO_MODE_DONE__SHIFT__SI 0x00000005 -#define MPRD_STATUS__MPRD_BUSY__SHIFT__SI 0x00000000 -#define MPRD_STATUS__VCPU_COMMAND_ERROR__SHIFT__SI 0x00000001 -#define MP_BUF_MAP__BUF_MAP__SHIFT__SI 0x00000000 -#define MP_BUF_NUM__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_BUF_SIZE__HEIGHT__SHIFT__SI 0x00000014 -#define MP_BUF_SIZE__PITCH__SHIFT__SI 0x00000004 -#define MP_CACHE_CTRL__BYPASS__SHIFT__SI 0x00000000 -#define MP_CACHE_CTRL__COUNTER_SELECT__SHIFT__SI 0x00000003 -#define MP_CACHE_CTRL__ENABLE_COUNT__SHIFT__SI 0x00000001 -#define MP_CACHE_CTRL__READ_COUNTER__SHIFT__SI 0x00000002 -#define MP_CACHE_PERF_COUNTER__PERF_COUNTER__SHIFT__SI 0x00000000 -#define MP_CACHE_SRAM_RM_CTL__MP_M024X216R2M01S00_RME__SHIFT__SI 0x00000009 -#define MP_CACHE_SRAM_RM_CTL__MP_M024X216R2M01S00_RM__SHIFT__SI 0x00000005 -#define MP_CACHE_SRAM_RM_CTL__MP_M128X075R2M01S00_RME__SHIFT__SI 0x0000001d -#define MP_CACHE_SRAM_RM_CTL__MP_M128X075R2M01S00_RM__SHIFT__SI 0x00000019 -#define MP_CACHE_SRAM_RM_CTL__MP_M144X020R2M04S00_RME__SHIFT__SI 0x00000013 -#define MP_CACHE_SRAM_RM_CTL__MP_M144X020R2M04S00_RM__SHIFT__SI 0x0000000f -#define MP_CACHE_SRAM_RM_CTL__MP_M192X033R2M02S00_RME__SHIFT__SI 0x0000000e -#define MP_CACHE_SRAM_RM_CTL__MP_M192X033R2M02S00_RM__SHIFT__SI 0x0000000a -#define MP_CACHE_SRAM_RM_CTL__MP_M192X068R2M02S00_RME__SHIFT__SI 0x00000018 -#define MP_CACHE_SRAM_RM_CTL__MP_M192X068R2M02S00_RM__SHIFT__SI 0x00000014 -#define MP_CACHE_SRAM_RM_CTL__MP_M768X128H1M04S00_RME__SHIFT__SI 0x00000004 -#define MP_CACHE_SRAM_RM_CTL__MP_M768X128H1M04S00_RM__SHIFT__SI 0x00000000 -#define MP_CF_DAT__DAT__SHIFT__SI 0x00000000 -#define MP_COL_INFO__CODED_FRAME__SHIFT__SI 0x00000002 -#define MP_COL_INFO__LONG_TERM__SHIFT__SI 0x00000003 -#define MP_COL_INFO__MBAFF_FRAME_FLAG__SHIFT__SI 0x00000004 -#define MP_COL_INFO__STRUCTURE__SHIFT__SI 0x00000000 -#define MP_COL_PIC_BOTTOM__POC__SHIFT__SI 0x00000000 -#define MP_COL_PIC_TOP__POC__SHIFT__SI 0x00000000 -#define MP_CTL__CTXT_FMT__SHIFT__SI 0x00000006 -#define MP_CTL__FULL_PEL_FILT__SHIFT__SI 0x00000008 -#define MP_CTL__NSG_MODE__SHIFT__SI 0x00000004 -#define MP_CTL__STANDARD__SHIFT__SI 0x00000000 -#define MP_CTL__SW_MRST__SHIFT__SI 0x0000001e -#define MP_CTL__SW_RRST__SHIFT__SI 0x0000001d -#define MP_CTL__SW_SRST__SHIFT__SI 0x0000001f -#define MP_CTL__TILE_FMT__SHIFT__SI 0x0000000c -#define MP_CTL__TIMEOUT_TIME__SHIFT__SI 0x00000014 -#define MP_CTL__TRCK_MODE__SHIFT__SI 0x00000009 -#define MP_CTL__UV_FMT__SHIFT__SI 0x0000000d -#define MP_CURR_PIC_BOTTOM__POC__SHIFT__SI 0x00000000 -#define MP_CURR_PIC_TOP__POC__SHIFT__SI 0x00000000 -#define MP_DEBUG_INT_STAT__CFIFO_LESS_ERROR__SHIFT__SI 0x00000004 -#define MP_DEBUG_INT_STAT__CFIFO_MORE_ERROR__SHIFT__SI 0x00000003 -#define MP_DEBUG_INT_STAT__CTXT_READ_TIMEOUT__SHIFT__SI 0x00000013 -#define MP_DEBUG_INT_STAT__CTXT_WRITE_TIMEOUT__SHIFT__SI 0x00000014 -#define MP_DEBUG_INT_STAT__DONE__SHIFT__SI 0x00000000 -#define MP_DEBUG_INT_STAT__DPB_ILLEGAL_ENTRY__SHIFT__SI 0x00000006 -#define MP_DEBUG_INT_STAT__MC_FIFO_OVF__SHIFT__SI 0x00000015 -#define MP_DEBUG_INT_STAT__NON_CONFORMANT_ERROR__SHIFT__SI 0x00000008 -#define MP_DEBUG_INT_STAT__PEL_COORD_FIFO_OVF__SHIFT__SI 0x00000017 -#define MP_DEBUG_INT_STAT__PEL_COORD_FIFO_UDF__SHIFT__SI 0x00000016 -#define MP_DEBUG_INT_STAT__POC_ILLEGAL_ENTRY__SHIFT__SI 0x00000005 -#define MP_DEBUG_INT_STAT__REF_PEL_FIFO_OVF__SHIFT__SI 0x00000002 -#define MP_DEBUG_INT_STAT__TEMPORAL_ERR__SHIFT__SI 0x00000001 -#define MP_DEBUG_INT_STAT__VC1_ERR_DMV_TIMEOUT__SHIFT__SI 0x00000010 -#define MP_DEBUG_INT_STAT__VC1_ERR_MB4MV_BFRAME__SHIFT__SI 0x0000000b -#define MP_DEBUG_INT_STAT__VC1_ERR_MB4MV__SHIFT__SI 0x0000000c -#define MP_DEBUG_INT_STAT__VC1_ERR_MBFLAG__SHIFT__SI 0x0000000e -#define MP_DEBUG_INT_STAT__VC1_ERR_MBX__SHIFT__SI 0x00000009 -#define MP_DEBUG_INT_STAT__VC1_ERR_MBY__SHIFT__SI 0x0000000a -#define MP_DEBUG_INT_STAT__VC1_ERR_MVSW__SHIFT__SI 0x0000000f -#define MP_DEBUG_INT_STAT__VC1_ERR_NO_HYBRID__SHIFT__SI 0x00000011 -#define MP_DEBUG_INT_STAT__VC1_ERR_PFRAME_MBDIR__SHIFT__SI 0x0000000d -#define MP_DEBUG_INT_STAT__VC1_ERR_PRED_RANGE__SHIFT__SI 0x00000012 -#define MP_DEBUG_INT_STAT__WGT_ILLEGAL_ENTRY__SHIFT__SI 0x00000007 -#define MP_HW_DEBUG__DAT__SHIFT__SI 0x00000000 -#define MP_INT_EN__CFIFO_LESS_ERROR_EN__SHIFT__SI 0x00000004 -#define MP_INT_EN__CFIFO_MORE_ERROR_EN__SHIFT__SI 0x00000003 -#define MP_INT_EN__CTXT_READ_TIMEOUT_EN__SHIFT__SI 0x00000013 -#define MP_INT_EN__CTXT_WRITE_TIMEOUT_EN__SHIFT__SI 0x00000014 -#define MP_INT_EN__DONE_EN__SHIFT__SI 0x00000000 -#define MP_INT_EN__DPB_ILLEGAL_ENTRY_EN__SHIFT__SI 0x00000006 -#define MP_INT_EN__MC_FIFO_OVF_EN__SHIFT__SI 0x00000015 -#define MP_INT_EN__NON_CONFORMANT_ERROR_EN__SHIFT__SI 0x00000008 -#define MP_INT_EN__PEL_COORD_FIFO_OVF_EN__SHIFT__SI 0x00000017 -#define MP_INT_EN__PEL_COORD_FIFO_UDF_EN__SHIFT__SI 0x00000016 -#define MP_INT_EN__POC_ILLEGAL_ENTRY_EN__SHIFT__SI 0x00000005 -#define MP_INT_EN__REF_PEL_FIFO_OVF_EN__SHIFT__SI 0x00000002 -#define MP_INT_EN__TEMPORAL_ERR_EN__SHIFT__SI 0x00000001 -#define MP_INT_EN__VC1_ERR_DMV_TIMEOUT_EN__SHIFT__SI 0x00000010 -#define MP_INT_EN__VC1_ERR_MB4MV_BFRAME_EN__SHIFT__SI 0x0000000b -#define MP_INT_EN__VC1_ERR_MB4MV_EN__SHIFT__SI 0x0000000c -#define MP_INT_EN__VC1_ERR_MBFLAG_EN__SHIFT__SI 0x0000000e -#define MP_INT_EN__VC1_ERR_MBX_EN__SHIFT__SI 0x00000009 -#define MP_INT_EN__VC1_ERR_MBY_EN__SHIFT__SI 0x0000000a -#define MP_INT_EN__VC1_ERR_MVSW_EN__SHIFT__SI 0x0000000f -#define MP_INT_EN__VC1_ERR_NO_HYBRID_EN__SHIFT__SI 0x00000011 -#define MP_INT_EN__VC1_ERR_PFRAME_MBDIR_EN__SHIFT__SI 0x0000000d -#define MP_INT_EN__VC1_ERR_PRED_RANGE_EN__SHIFT__SI 0x00000012 -#define MP_INT_EN__WGT_ILLEGAL_ENTRY_EN__SHIFT__SI 0x00000007 -#define MP_INT_STAT__CFIFO_LESS_ERROR__SHIFT__SI 0x00000004 -#define MP_INT_STAT__CFIFO_MORE_ERROR__SHIFT__SI 0x00000003 -#define MP_INT_STAT__CTXT_READ_TIMEOUT__SHIFT__SI 0x00000013 -#define MP_INT_STAT__CTXT_WRITE_TIMEOUT__SHIFT__SI 0x00000014 -#define MP_INT_STAT__DONE__SHIFT__SI 0x00000000 -#define MP_INT_STAT__DPB_ILLEGAL_ENTRY__SHIFT__SI 0x00000006 -#define MP_INT_STAT__MC_FIFO_OVF__SHIFT__SI 0x00000015 -#define MP_INT_STAT__NON_CONFORMANT_ERROR__SHIFT__SI 0x00000008 -#define MP_INT_STAT__PEL_COORD_FIFO_OVF__SHIFT__SI 0x00000017 -#define MP_INT_STAT__PEL_COORD_FIFO_UDF__SHIFT__SI 0x00000016 -#define MP_INT_STAT__POC_ILLEGAL_ENTRY__SHIFT__SI 0x00000005 -#define MP_INT_STAT__REF_PEL_FIFO_OVF__SHIFT__SI 0x00000002 -#define MP_INT_STAT__TEMPORAL_ERR__SHIFT__SI 0x00000001 -#define MP_INT_STAT__VC1_ERR_DMV_TIMEOUT__SHIFT__SI 0x00000010 -#define MP_INT_STAT__VC1_ERR_MB4MV_BFRAME__SHIFT__SI 0x0000000b -#define MP_INT_STAT__VC1_ERR_MB4MV__SHIFT__SI 0x0000000c -#define MP_INT_STAT__VC1_ERR_MBFLAG__SHIFT__SI 0x0000000e -#define MP_INT_STAT__VC1_ERR_MBX__SHIFT__SI 0x00000009 -#define MP_INT_STAT__VC1_ERR_MBY__SHIFT__SI 0x0000000a -#define MP_INT_STAT__VC1_ERR_MVSW__SHIFT__SI 0x0000000f -#define MP_INT_STAT__VC1_ERR_NO_HYBRID__SHIFT__SI 0x00000011 -#define MP_INT_STAT__VC1_ERR_PFRAME_MBDIR__SHIFT__SI 0x0000000d -#define MP_INT_STAT__VC1_ERR_PRED_RANGE__SHIFT__SI 0x00000012 -#define MP_INT_STAT__WGT_ILLEGAL_ENTRY__SHIFT__SI 0x00000007 -#define MP_LISTX0_0__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_0__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_0__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_0__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_0__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_0__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_10__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_10__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_10__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_10__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_10__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_10__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_11__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_11__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_11__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_11__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_11__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_11__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_12__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_12__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_12__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_12__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_12__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_12__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_13__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_13__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_13__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_13__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_13__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_13__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_14__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_14__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_14__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_14__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_14__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_14__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_15__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_15__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_15__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_15__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_15__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_15__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_1__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_1__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_1__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_1__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_1__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_1__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_2__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_2__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_2__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_2__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_2__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_2__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_3__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_3__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_3__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_3__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_3__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_3__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_4__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_4__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_4__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_4__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_4__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_4__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_5__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_5__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_5__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_5__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_5__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_5__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_6__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_6__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_6__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_6__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_6__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_6__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_7__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_7__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_7__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_7__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_7__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_7__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_8__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_8__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_8__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_8__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_8__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_8__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX0_9__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX0_9__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX0_9__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX0_9__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX0_9__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX0_9__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_0__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_0__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_0__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_0__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_0__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_0__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_10__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_10__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_10__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_10__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_10__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_10__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_11__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_11__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_11__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_11__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_11__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_11__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_12__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_12__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_12__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_12__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_12__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_12__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_13__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_13__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_13__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_13__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_13__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_13__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_14__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_14__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_14__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_14__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_14__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_14__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_15__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_15__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_15__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_15__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_15__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_15__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_1__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_1__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_1__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_1__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_1__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_1__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_2__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_2__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_2__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_2__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_2__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_2__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_3__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_3__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_3__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_3__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_3__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_3__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_4__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_4__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_4__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_4__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_4__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_4__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_5__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_5__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_5__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_5__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_5__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_5__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_6__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_6__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_6__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_6__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_6__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_6__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_7__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_7__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_7__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_7__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_7__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_7__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_8__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_8__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_8__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_8__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_8__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_8__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LISTX1_9__BUF_NUM2__SHIFT__SI 0x00000008 -#define MP_LISTX1_9__BUF_NUM__SHIFT__SI 0x00000000 -#define MP_LISTX1_9__LONG_TERM2__SHIFT__SI 0x0000000f -#define MP_LISTX1_9__LONG_TERM__SHIFT__SI 0x00000007 -#define MP_LISTX1_9__STRUCTURE2__SHIFT__SI 0x0000000d -#define MP_LISTX1_9__STRUCTURE__SHIFT__SI 0x00000005 -#define MP_LMA_ADR__ADR__SHIFT__SI 0x00000000 -#define MP_LMA_CTL__ACCESS_MODE__SHIFT__SI 0x00000000 -#define MP_LMA_CTL__AUTO_INC__SHIFT__SI 0x00000006 -#define MP_LMA_CTL__MEMORY_SELECT__SHIFT__SI 0x00000001 -#define MP_LMA_DAT__DAT__SHIFT__SI 0x00000000 -#define MP_PPS_INFO__APPLY_WEIGHTS__SHIFT__SI 0x00000000 -#define MP_PPS_INFO__DIV_REF_IDX__SHIFT__SI 0x00000001 -#define MP_PPS_INFO__FIELD_PIC_FLAG__SHIFT__SI 0x00000010 -#define MP_PPS_INFO__NUM_REF_IDX_L0_ACTIVE__SHIFT__SI 0x00000002 -#define MP_PPS_INFO__NUM_REF_IDX_L1_ACTIVE__SHIFT__SI 0x00000008 -#define MP_PPS_INFO__RANGERED_UP_DOWN__SHIFT__SI 0x00000011 -#define MP_PPS_INFO__STRUCTURE__SHIFT__SI 0x0000000e -#define MP_PPS_INFO__TRCK_MODE_VAL__SHIFT__SI 0x00000013 -#define MP_SLICE_INFO__CHROMA_LOG2_WEIGHT_DENOM__SHIFT__SI 0x00000004 -#define MP_SLICE_INFO__DIRECT_SPATIAL_MV_PRED_FLAG__SHIFT__SI 0x00000009 -#define MP_SLICE_INFO__LUMA_LOG2_WEIGHT_DENOM__SHIFT__SI 0x00000001 -#define MP_SLICE_INFO__MBAFF_FRAME_FLAG__SHIFT__SI 0x00000000 -#define MP_SLICE_INFO__WEIGHTED_BIPRED_IDC__SHIFT__SI 0x00000007 -#define MP_SPS_INFO__CHROMA_FORMAT_IDC__SHIFT__SI 0x0000001c -#define MP_SPS_INFO__DIRECT_8X8_INFERENCE_FLAG__SHIFT__SI 0x0000001e -#define MP_SPS_INFO__FRAME_MBS_ONLY_FLAG__SHIFT__SI 0x0000001d -#define MP_SPS_INFO__PIC_HEIGHT__SHIFT__SI 0x00000010 -#define MP_SPS_INFO__PIC_WIDTH__SHIFT__SI 0x00000000 -#define MP_SRAM_RM_CTL__MP_M064X016H1M04S00_RME__SHIFT__SI 0x00000004 -#define MP_SRAM_RM_CTL__MP_M064X016H1M04S00_RM__SHIFT__SI 0x00000000 -#define MP_SRAM_RM_CTL__MP_M064X027H1M04S00_RME__SHIFT__SI 0x00000009 -#define MP_SRAM_RM_CTL__MP_M064X027H1M04S00_RM__SHIFT__SI 0x00000005 -#define MP_SRAM_RM_CTL__MP_M064X040R2M01S00_RME__SHIFT__SI 0x00000013 -#define MP_SRAM_RM_CTL__MP_M064X040R2M01S00_RM__SHIFT__SI 0x0000000f -#define MP_SRAM_RM_CTL__MP_M096X032R2M02S00_RME__SHIFT__SI 0x0000000e -#define MP_SRAM_RM_CTL__MP_M096X032R2M02S00_RM__SHIFT__SI 0x0000000a -#define MP_SRAM_RM_CTL__MP_WRM__SHIFT__SI 0x00000014 -#define MP_STAT__BUSY__SHIFT__SI 0x00000000 -#define MP_STAT__MEM_TRANS_PEND__SHIFT__SI 0x00000001 -#define MP_STAT__MP_DB_TRANS__SHIFT__SI 0x00000002 -#define MP_VC1_DONE_CTXT__DONE_CTXT__SHIFT__SI 0x00000000 -#define MP_VC1_PPS_INFO__B_FRAME__SHIFT__SI 0x0000001d -#define MP_VC1_PPS_INFO__FASTUVMC__SHIFT__SI 0x00000014 -#define MP_VC1_PPS_INFO__FIELD_PIC_FLAG__SHIFT__SI 0x00000001 -#define MP_VC1_PPS_INFO__LUMSCALE__SHIFT__SI 0x00000006 -#define MP_VC1_PPS_INFO__MVMODE__SHIFT__SI 0x00000003 -#define MP_VC1_PPS_INFO__MVRANGE__SHIFT__SI 0x00000012 -#define MP_VC1_PPS_INFO__PROFILE__SHIFT__SI 0x0000001e -#define MP_VC1_PPS_INFO__RNDFLAG__SHIFT__SI 0x00000005 -#define MP_VC1_PPS_INFO__SCALE_FACTOR__SHIFT__SI 0x00000015 -#define MP_VC1_PPS_INFO__TOP_FIELD_FIRST__SHIFT__SI 0x00000000 -#define MP_VC1_REF_INFO__NUMREF__SHIFT__SI 0x00000005 -#define MP_VC1_REF_INFO__REFDIST__SHIFT__SI 0x00000000 -#define MP_VC1_REF_INFO__REF_PIC_FLAG__SHIFT__SI 0x00000004 -#define MP_VC1_USE_HYBRIDPRED__DONE_HYBRIDPRED__SHIFT__SI 0x00000000 -#define MP_VC1_USE_HYBRIDPRED__INTRA__SHIFT__SI 0x00000002 -#define MP_VC1_USE_HYBRIDPRED__USE_HYBRIDPRED__SHIFT__SI 0x00000001 -#define MSI_CAP_LIST__CAP_ID__SHIFT 0x00000000 -#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x00000008 -#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x00000000 -#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x00000002 -#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x00000007 -#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x00000000 -#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x00000001 -#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x00000004 -#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x00000000 -#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x00000000 -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT__SI 0x00000000 -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT__SI 0x0000000c -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT__SI 0x00000008 -#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT__SI 0x00000004 -#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT__SI 0x00000000 -#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT__SI 0x00000014 -#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT__SI 0x0000000a -#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT__SI 0x00000000 -#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT__SI 0x0000001c -#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT__SI 0x0000000a -#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT__SI 0x00000010 -#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT__SI 0x00000018 -#define MVP_CONTROL1__MVP_EN__SHIFT__SI 0x00000000 -#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT__SI 0x00000014 -#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT__SI 0x00000004 -#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT__SI 0x00000009 -#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT__SI 0x00000008 -#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT__SI 0x0000000c -#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT__SI 0x0000001e -#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT__SI 0x0000001f -#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT__SI 0x00000010 -#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT__SI 0x00000014 -#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT__SI 0x00000008 -#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT__SI 0x0000000c -#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT__SI 0x00000000 -#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT__SI 0x00000004 -#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT__SI 0x0000001c -#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT__SI 0x00000018 -#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT__SI 0x00000004 -#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT__SI 0x00000008 -#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT__SI 0x00000014 -#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT__SI 0x0000001c -#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT__SI 0x0000000c -#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT__SI 0x00000010 -#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT__SI 0x00000000 -#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT__SI 0x00000018 -#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT__SI 0x00000000 -#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT__SI 0x0000001d -#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT__SI 0x0000001c -#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT__SI 0x00000008 -#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT__SI 0x00000010 -#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT__SI 0x0000001e -#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT__SI 0x00000000 -#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT__SI 0x00000010 -#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT__SI 0x00000000 -#define MVP_DEBUG_01__IDDC_MVP_DATA_ACTIVE_D1__SHIFT__SI 0x00000016 -#define MVP_DEBUG_01__IDDC_MVP_DATA_ACTIVE__SHIFT__SI 0x0000000a -#define MVP_DEBUG_01__IDDC_MVP_DEGAMMA_RED_PIXEL_FROM_MASTER__SHIFT__SI 0x0000000c -#define MVP_DEBUG_01__IDDC_MVP_MASTER_RED_PIXEL_BEFORE_ADDER__SHIFT__SI 0x00000017 -#define MVP_DEBUG_01__IDDC_MVP_RED_PIXEL_FROM_MASTER__SHIFT__SI 0x00000000 -#define MVP_DEBUG_02__IDDD_MVP_DATA_ACTIVE_D1__SHIFT__SI 0x00000016 -#define MVP_DEBUG_02__IDDD_MVP_DATA_ACTIVE__SHIFT__SI 0x0000000a -#define MVP_DEBUG_02__IDDD_MVP_DEGAMMA_RED_PIXEL_FROM_SLAVE__SHIFT__SI 0x0000000c -#define MVP_DEBUG_02__IDDD_MVP_RED_PIXEL_FROM_SLAVE__SHIFT__SI 0x00000000 -#define MVP_DEBUG_02__IDDD_MVP_SLAVE_RED_PIXEL_BEFORE_ADDER__SHIFT__SI 0x00000017 -#define MVP_DEBUG_03__IDDE_MVP_DATA_ACTIVE_D1_DUPLICATE__SHIFT__SI 0x00000016 -#define MVP_DEBUG_03__IDDE_MVP_DATA_ACTIVE_D1__SHIFT__SI 0x0000000a -#define MVP_DEBUG_03__IDDE_MVP_DATA_ACTIVE_D3__SHIFT__SI 0x0000001f -#define MVP_DEBUG_03__IDDE_MVP_MASTER_RED_PIXEL_BEFORE_ADDER__SHIFT__SI 0x00000000 -#define MVP_DEBUG_03__IDDE_MVP_RED_PIXEL_AFTER_ADDER__SHIFT__SI 0x00000017 -#define MVP_DEBUG_03__IDDE_MVP_SLAVE_RED_PIXEL_BEFORE_ADDER__SHIFT__SI 0x0000000c -#define MVP_DEBUG_04__IDDF_MVP_DATA_ACTIVE_D3_DUPLICATE__SHIFT__SI 0x00000017 -#define MVP_DEBUG_04__IDDF_MVP_DATA_ACTIVE_D3__SHIFT__SI 0x0000000a -#define MVP_DEBUG_04__IDDF_MVP_RED_PIXEL_AFTER_ADDER__SHIFT__SI 0x00000000 -#define MVP_DEBUG_04__IDDF_MVP_RED_PIXEL_AFTER_KEYER_ADJUST__SHIFT__SI 0x0000000c -#define MVP_DEBUG_05__IDE0_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_CAPTURE__SHIFT__SI 0x00000008 -#define MVP_DEBUG_05__IDE0_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT__SHIFT__SI 0x0000001e -#define MVP_DEBUG_05__IDE0_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_REQUEST__SHIFT__SI 0x0000000e -#define MVP_DEBUG_05__IDE0_MVP_ENABLE__SHIFT__SI 0x00000000 -#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT__SI 0x00000001 -#define MVP_DEBUG_05__IDE0_MVP_HEAD_SLAVE_GPU_INBAND_OUT_MODE__SHIFT__SI 0x00000018 -#define MVP_DEBUG_05__IDE0_MVP_HSYNC_FLIP_ENABLE__SHIFT__SI 0x00000006 -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE_CONDITION_DUPLICATE__SHIFT__SI 0x00000011 -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE_CONDITION__SHIFT__SI 0x00000005 -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE_POSITION__SHIFT__SI 0x00000007 -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_CAPTURE__SHIFT__SI 0x0000000a -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT_CONDITION__SHIFT__SI 0x0000001a -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT_HORIZONTAL_POSITION__SHIFT__SI 0x0000001b -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT_POSITION__SHIFT__SI 0x0000001c -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_INSERT__SHIFT__SI 0x0000001d -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_REQUEST_HORIZONTAL_POSITION__SHIFT__SI 0x0000000c -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_REQUEST_POSITION__SHIFT__SI 0x0000000d -#define MVP_DEBUG_05__IDE0_MVP_INBAND_CHAR_REQUEST__SHIFT__SI 0x00000010 -#define MVP_DEBUG_05__IDE0_MVP_MASTER_GPU_IGNORE_INBAND_CHAR__SHIFT__SI 0x00000003 -#define MVP_DEBUG_05__IDE0_MVP_MIDDLE_SLAVE_GPU_PASS_INBAND_CHAR__SHIFT__SI 0x00000004 -#define MVP_DEBUG_05__IDE0_MVP_MIXER_FIFO_READ_EN__SHIFT__SI 0x00000012 -#define MVP_DEBUG_05__IDE0_MVP_MIXER_MODE__SHIFT__SI 0x00000015 -#define MVP_DEBUG_05__IDE0_MVP_PIXEL_SELECT_IN_AFR_DRIVER_MODE__SHIFT__SI 0x00000013 -#define MVP_DEBUG_05__IDE0_MVP_PIXEL_SELECT_IN_AFR_SWITCH_MODE__SHIFT__SI 0x00000014 -#define MVP_DEBUG_05__IDE0_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_CAPTURE__SHIFT__SI 0x00000009 -#define MVP_DEBUG_05__IDE0_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT__SHIFT__SI 0x0000001f -#define MVP_DEBUG_05__IDE0_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_REQUEST__SHIFT__SI 0x0000000f -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS_IN_HSYNC_FLIP_MODE_DUPLICATE__SHIFT__SI \ - 0x00000013 -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS_IN_HSYNC_FLIP_MODE__SHIFT__SI 0x00000005 -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS_IN_VSYNC_FLIP_MODE__SHIFT__SI 0x00000003 -#define MVP_DEBUG_06__IDE1_MVP_AFR_FLIP_QUEUE_STATUS__SHIFT__SI 0x00000007 -#define MVP_DEBUG_06__IDE1_MVP_AFR_HSYNC_SWITCH_DONE__SHIFT__SI 0x00000015 -#define MVP_DEBUG_06__IDE1_MVP_AFR_HSYNC_SWITCH__SHIFT__SI 0x00000012 -#define MVP_DEBUG_06__IDE1_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT__SHIFT__SI 0x0000001a -#define MVP_DEBUG_06__IDE1_MVP_FLIP_CONTROL_CHAR_CAPTURED_DUPLICATE__SHIFT__SI 0x0000000d -#define MVP_DEBUG_06__IDE1_MVP_FLIP_CONTROL_CHAR_CAPTURED__SHIFT__SI 0x00000001 -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW_ASSERT_POSITION__SHIFT__SI 0x00000019 -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW_DEASSERT_POSITION__SHIFT__SI 0x0000001b -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW_STATUS__SHIFT__SI 0x0000001e -#define MVP_DEBUG_06__IDE1_MVP_FLIP_NOW__SHIFT__SI 0x0000001f -#define MVP_DEBUG_06__IDE1_MVP_FLIP_REQUEST_CAPTURE_POSITION__SHIFT__SI 0x0000001c -#define MVP_DEBUG_06__IDE1_MVP_FLIP_REQUEST_OCCURRED__SHIFT__SI 0x00000017 -#define MVP_DEBUG_06__IDE1_MVP_FLIP_REQUEST__SHIFT__SI 0x0000001d -#define MVP_DEBUG_06__IDE1_MVP_HSYNC_FLIP_ENABLE_DUPLICATE__SHIFT__SI 0x00000018 -#define MVP_DEBUG_06__IDE1_MVP_HSYNC_FLIP_ENABLE__SHIFT__SI 0x00000009 -#define MVP_DEBUG_06__IDE1_MVP_INBAND_CHAR_CAPTURE_DUPLICATE__SHIFT__SI 0x0000000c -#define MVP_DEBUG_06__IDE1_MVP_INBAND_CHAR_CAPTURE__SHIFT__SI 0x00000000 -#define MVP_DEBUG_06__IDE1_MVP_INPUT_FLIP_REQUEST__SHIFT__SI 0x00000016 -#define MVP_DEBUG_06__IDE1_MVP_PIXEL_SELECT_IN_AFR_SWITCH_MODE__SHIFT__SI 0x0000000a -#define MVP_DEBUG_06__IDE1_MVP_TEMPORARY_AFR_FLIP_QUEUE_STATUS__SHIFT__SI 0x0000000f -#define MVP_DEBUG_06__IDE1_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_CAPTURE__SHIFT__SI 0x00000011 -#define MVP_DEBUG_07__IDE2_MVP_FLIP_NOW_ASSERT_POSITION__SHIFT__SI 0x0000001e -#define MVP_DEBUG_07__IDE2_MVP_FLIP_REQUEST__SHIFT__SI 0x0000001d -#define MVP_DEBUG_07__IDE2_MVP_INBAND_CHAR_INSERT__SHIFT__SI 0x00000018 -#define MVP_DEBUG_07__IDE2_MVP_INBAND_CHAR__SHIFT__SI 0x00000000 -#define MVP_DEBUG_07__IDE2_MVP_SLAVE_AFR_FLIP_QUEUE_STATUS__SHIFT__SI 0x00000019 -#define MVP_DEBUG_07__IDE2_MVP_SLAVE_FLIP_CONTROL_CHAR__SHIFT__SI 0x0000001b -#define MVP_DEBUG_08__IDE3_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT__SHIFT__SI 0x00000001 -#define MVP_DEBUG_08__IDE3_MVP_FLIP_LINE_NUMBER__SHIFT__SI 0x0000000d -#define MVP_DEBUG_08__IDE3_MVP_FLIP_NOW_ASSERT_POSITION_DUPLICATE__SHIFT__SI 0x0000000c -#define MVP_DEBUG_08__IDE3_MVP_FLIP_NOW_ASSERT_POSITION__SHIFT__SI 0x00000002 -#define MVP_DEBUG_08__IDE3_MVP_HSYNC_FLIP_ENABLE__SHIFT__SI 0x00000000 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT__SHIFT__SI 0x00000009 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_ENABLE__SHIFT__SI 0x00000000 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_LINE_NUMBER__SHIFT__SI 0x00000015 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW_ASSERT_DUPLICATE__SHIFT__SI 0x00000014 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW_ASSERT_POSITION__SHIFT__SI 0x00000011 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW_ASSERT__SHIFT__SI 0x00000012 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_NOW__SHIFT__SI 0x00000013 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_REQUEST_CAPTURE_POSITION__SHIFT__SI 0x0000000d -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_REQUEST_OCCURRED__SHIFT__SI 0x0000000f -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_FLIP_REQUEST__SHIFT__SI 0x0000000e -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT__SI 0x00000001 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_HSYNC_FLIP_ENABLE__SHIFT__SI 0x0000000c -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT_CONDITION__SHIFT__SI 0x00000005 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT_HORIZONTAL_POSITION__SHIFT__SI 0x00000006 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT_POSITION__SHIFT__SI 0x00000007 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_CHAR_INSERT__SHIFT__SI 0x00000008 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INBAND_OUT_MODE__SHIFT__SI 0x00000003 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_INPUT_FLIP_REQUEST__SHIFT__SI 0x00000010 -#define MVP_DEBUG_09__IDE4_CRTC2_MVP_V_BLANK_ALIGN_WITH_INBAND_CHAR_INSERT__SHIFT__SI 0x0000000a -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_FLIP_REQUEST__SHIFT__SI 0x00000002 -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_INBAND_CHAR__SHIFT__SI 0x00000008 -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_INBAND_OUT_MODE__SHIFT__SI 0x00000000 -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_SLAVE_AFR_FLIP_QUEUE_STATUS__SHIFT__SI 0x00000005 -#define MVP_DEBUG_10__IDE5_CRTC2_MVP_SLAVE_FLIP_CONTROL_CHAR__SHIFT__SI 0x00000003 -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_MASTER_TRANSITION_OCCURRED__SHIFT__SI \ - 0x00000011 -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_MASTER_TRANSITION__SHIFT__SI 0x0000000f -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_MASTER__SHIFT__SI 0x0000000d -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_SLAVE_TRANSITION_OCCURRED__SHIFT__SI \ - 0x00000010 -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_SLAVE_TRANSITION__SHIFT__SI 0x0000000e -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_FROM_SLAVE__SHIFT__SI 0x0000000c -#define MVP_DEBUG_11__IDE6_MVP_AFR_FLIP_QUEUE_STATUS_TRANSITION_FROM_BOTH_MASTER_AND_SLAVE__SHIFT__SI \ - 0x00000012 -#define MVP_DEBUG_11__IDE6_MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT__SI 0x00000015 -#define MVP_DEBUG_11__IDE6_MVP_BLANK_FALLING_EDGE__SHIFT__SI 0x00000001 -#define MVP_DEBUG_11__IDE6_MVP_HSYNC_FLIP_ENABLE__SHIFT__SI 0x00000002 -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_EN__SHIFT__SI 0x00000006 -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_DOUBLE_BUFFERED__SHIFT__SI 0x00000005 -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_INPUT__SHIFT__SI 0x00000004 -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SLAVE_SEL_IN_AFR_MANUAL_SWITCH_MODE__SHIFT__SI 0x00000013 -#define MVP_DEBUG_11__IDE6_MVP_MIXER_SOURCE_SELECT_UPDATE_POSITION__SHIFT__SI 0x00000003 -#define MVP_DEBUG_11__IDE6_MVP_PIXEL_SELECT_IN_AFR_DRIVER_MODE__SHIFT__SI 0x00000007 -#define MVP_DEBUG_11__IDE6_MVP_PIXEL_SELECT_IN_AFR_MANUAL_SWITCH_MODE__SHIFT__SI 0x00000014 -#define MVP_DEBUG_11__IDE6_MVP_V_BLANK_FALLING_EDGE__SHIFT__SI 0x00000000 -#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT__SI 0x00000000 -#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT__SI 0x00000001 -#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT__SI 0x00000000 -#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT__SI 0x00000001 -#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT__SI 0x0000001a -#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT__SI 0x00000019 -#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT__SI 0x0000001b -#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT__SI 0x00000014 -#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT__SI 0x00000013 -#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT__SI 0x00000000 -#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT__SI 0x00000011 -#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT__SI 0x00000010 -#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT__SI 0x00000012 -#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT__SI 0x0000000f -#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT__SI 0x0000000e -#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT__SI 0x0000000b -#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT__SI 0x0000000c -#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT__SI 0x0000000a -#define MVP_DEBUG_14__IDEE_START_READ__SHIFT__SI 0x00000009 -#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT__SI 0x0000000d -#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT__SI 0x00000003 -#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT__SI 0x00000006 -#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT__SI 0x00000004 -#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT__SI 0x00000000 -#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT__SI 0x00000003 -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT__SI 0x00000002 -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT__SI 0x00000001 -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT__SI 0x00000004 -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT__SI 0x0000000c -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT__SI 0x00000000 -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT__SI 0x0000000d -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT__SI 0x00000010 -#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT__SI 0x00000018 -#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT__SI 0x00000001 -#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT__SI 0x00000002 -#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT__SI 0x00000000 -#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT__SI 0x00000010 -#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT__SI 0x00000008 -#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT__SI 0x00000000 -#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT__SI 0x0000001f -#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT__SI 0x0000001e -#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT__SI 0x00000000 -#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT__SI 0x00000010 -#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT__SI 0x0000000c -#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT__SI 0x00000008 -#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT__SI 0x0000001c -#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT__SI 0x00000018 -#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT__SI 0x00000014 -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT__SI 0x0000001e -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT__SI 0x00000000 -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT__SI 0x00000008 -#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT__SI 0x00000018 -#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT__SI 0x00000000 -#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT__SI 0x00000008 -#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT__SI 0x00000004 -#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT__SI 0x0000001f -#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT__SI 0x00000010 -#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT__SI 0x00000000 -#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT__SI 0x0000001f -#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT__SI 0x00000000 -#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT__SI 0x00000010 -#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT__SI 0x00000000 -#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define NB_PSTATE_CONTROL__Mem_Pstate_Dis__SHIFT__CI__VI 0x0000001f -#define NB_PSTATE_CONTROL__Nb_Pstate_Gnb_Slow_Dis__SHIFT__CI__VI 0x00000017 -#define NB_PSTATE_CONTROL__Nb_Pstate_Hi_Res__SHIFT__CI__VI 0x0000001b -#define NB_PSTATE_CONTROL__Nb_Pstate_Hi__SHIFT__CI__VI 0x00000006 -#define NB_PSTATE_CONTROL__Nb_Pstate_Lo_Res__SHIFT__CI__VI 0x00000018 -#define NB_PSTATE_CONTROL__Nb_Pstate_Lo__SHIFT__CI__VI 0x00000003 -#define NB_PSTATE_CONTROL__Nb_Pstate_Max_Val__SHIFT__CI__VI 0x00000000 -#define NB_PSTATE_CONTROL__Nb_Pstate_Threshold__SHIFT__CI__VI 0x00000009 -#define NB_PSTATE_CONTROL__RESERVED_1__SHIFT__CI__VI 0x0000000f -#define NB_PSTATE_CONTROL__RESERVED_2__SHIFT__CI__VI 0x0000000c -#define NB_PSTATE_CONTROL__RESERVED_3__SHIFT__CI__VI 0x00000008 -#define NB_PSTATE_CONTROL__RESERVED_4__SHIFT__CI__VI 0x00000005 -#define NB_PSTATE_CONTROL__RESERVED_5__SHIFT__CI__VI 0x00000002 -#define NB_PSTATE_CONTROL__RESERVED__SHIFT__CI__VI 0x0000001e -#define NB_PSTATE_CONTROL__Sw_Nb_Pstate_Dis_On_p0__SHIFT__CI__VI 0x0000000d -#define NB_PSTATE_CONTROL__Sw_Nb_Pstate_Lo_Dis__SHIFT__CI__VI 0x0000000e -#define NB_PSTATE_STATUS__Cur_Nb_Did__SHIFT__CI__VI 0x00000009 -#define NB_PSTATE_STATUS__Cur_Nb_Fid__SHIFT__CI__VI 0x00000003 -#define NB_PSTATE_STATUS__Curr_Mem_Pstate__SHIFT__CI__VI 0x00000018 -#define NB_PSTATE_STATUS__Curr_Nb_Pstate__SHIFT__CI__VI 0x00000013 -#define NB_PSTATE_STATUS__Curr_Nb_Vid_6_0__SHIFT__CI__VI 0x0000000c -#define NB_PSTATE_STATUS__Curr_Nb_Vid_7__SHIFT__CI__VI 0x00000017 -#define NB_PSTATE_STATUS__Nb_Pstate_Dis__SHIFT__CI__VI 0x00000000 -#define NB_PSTATE_STATUS__RESERVED_1__SHIFT__CI__VI 0x00000015 -#define NB_PSTATE_STATUS__RESERVED_2__SHIFT__CI__VI 0x0000000a -#define NB_PSTATE_STATUS__RESERVED__SHIFT__CI__VI 0x00000019 -#define NB_PSTATE_STATUS__Startup_Nb_Pstate__SHIFT__CI__VI 0x00000001 -#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT__CI 0x00000000 -#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT__CI 0x0000000a -#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT__CI 0x00000015 -#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT__CI 0x00000000 -#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT__CI 0x00000001 -#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x00000000 -#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x0000001f -#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT__SI 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT__SI \ - 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT__SI \ - 0x00000007 -#define OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT__SI \ - 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT__SI \ - 0x0000001a -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT__SI \ - 0x00000004 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT__SI 0x0000001c -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT__SI \ - 0x00000003 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT__SI 0x0000001b -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__FIFO_READY__SHIFT__SI 0x0000001d -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT__SI \ - 0x00000002 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT__SI 0x00000014 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STREAM_RESET__SHIFT__SI 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STREAM_RUN__SHIFT__SI 0x00000001 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT__SI 0x00000010 -#define OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT__SI 0x00000012 -#define OUTPUT_STREAM_DESCRIPTOR_0_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT__SI 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_FIFO_SIZE__FIFO_SIZE__SHIFT__SI 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__BITS_PER_SAMPLE__SHIFT__SI 0x00000004 -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__NUMBER_OF_CHANNELS__SHIFT__SI 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT__SI 0x00000008 -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT__SI 0x0000000b -#define OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SAMPLE_BASE_RATE__SHIFT__SI 0x0000000e -#define OUTPUT_STREAM_DESCRIPTOR_0_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT__SI 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT__SI \ - 0x00000000 -#define OUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT__SI \ - 0x00000000 -#define OVLSCL_DEBUG0__OVLSCL_DEBUG0__SHIFT__SI 0x00000000 -#define OVLSCL_DEBUG1__OVLSCL_DEBUG1__SHIFT__SI 0x00000000 -#define OVLSCL_DEBUG2__OVLSCL_DEBUG2__SHIFT__SI 0x00000000 -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT__SI 0x00000000 -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT__SI 0x0000000a -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT__SI 0x00000014 -#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT__SI 0x0000001f -#define OVL_ALPHA_CONTROL__OVL_ALPHA_INV__SHIFT__SI 0x00000010 -#define OVL_ALPHA_CONTROL__OVL_ALPHA_MODE__SHIFT__SI 0x00000000 -#define OVL_ALPHA_CONTROL__OVL_ALPHA_PREMULT__SHIFT__SI 0x00000008 -#define OVL_ALPHA__OVL_ALPHA__SHIFT__SI 0x00000000 -#define OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SHIFT__SI \ - 0x00000000 -#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT__SI 0x00000010 -#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT__SI 0x00000014 -#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT__SI 0x00000018 -#define OVL_CONTROL1__OVL_DEPTH__SHIFT__SI 0x00000000 -#define OVL_CONTROL1__OVL_FORMAT__SHIFT__SI 0x00000008 -#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT__SI 0x00000011 -#define OVL_CONTROL1__OVL_TILE_COMPACT_EN__SHIFT__SI 0x0000000c -#define OVL_CONTROL1__OVL_Z__SHIFT__SI 0x00000004 -#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT__SI 0x00000000 -#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT__SI 0x00000008 -#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT__SI 0x00000000 -#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT__SI 0x00000004 -#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT__SI 0x00000000 -#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT__SI 0x00000009 -#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT__SI 0x00000008 -#define OVL_ENABLE__OVLSCL_EN__SHIFT__SI 0x00000008 -#define OVL_ENABLE__OVL_ENABLE__SHIFT__SI 0x00000000 -#define OVL_END__OVL_X_END__SHIFT__SI 0x00000010 -#define OVL_END__OVL_Y_END__SHIFT__SI 0x00000000 -#define OVL_KEY_ALPHA__OVL_KEY_ALPHA_HIGH__SHIFT__SI 0x00000010 -#define OVL_KEY_ALPHA__OVL_KEY_ALPHA_LOW__SHIFT__SI 0x00000000 -#define OVL_KEY_CONTROL__GRPH_KEY_FUNCTION__SHIFT__SI 0x00000000 -#define OVL_KEY_CONTROL__OVL_KEY_COMPARE_MIX__SHIFT__SI 0x00000010 -#define OVL_KEY_CONTROL__OVL_KEY_FUNCTION__SHIFT__SI 0x00000008 -#define OVL_KEY_RANGE_BLUE_CB__OVL_KEY_BLUE_CB_HIGH__SHIFT__SI 0x00000010 -#define OVL_KEY_RANGE_BLUE_CB__OVL_KEY_BLUE_CB_LOW__SHIFT__SI 0x00000000 -#define OVL_KEY_RANGE_GREEN_Y__OVL_KEY_GREEN_Y_HIGH__SHIFT__SI 0x00000010 -#define OVL_KEY_RANGE_GREEN_Y__OVL_KEY_GREEN_Y_LOW__SHIFT__SI 0x00000000 -#define OVL_KEY_RANGE_RED_CR__OVL_KEY_RED_CR_HIGH__SHIFT__SI 0x00000010 -#define OVL_KEY_RANGE_RED_CR__OVL_KEY_RED_CR_LOW__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_1_1__OVL_MATRIX_COEF_1_1__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_1_1__OVL_MATRIX_SIGN_1_1__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_1_2__OVL_MATRIX_COEF_1_2__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_1_2__OVL_MATRIX_SIGN_1_2__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_1_3__OVL_MATRIX_COEF_1_3__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_1_3__OVL_MATRIX_SIGN_1_3__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_1_4__OVL_MATRIX_COEF_1_4__SHIFT__SI 0x00000008 -#define OVL_MATRIX_COEF_1_4__OVL_MATRIX_SIGN_1_4__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_2_1__OVL_MATRIX_COEF_2_1__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_2_1__OVL_MATRIX_SIGN_2_1__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_2_2__OVL_MATRIX_COEF_2_2__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_2_2__OVL_MATRIX_SIGN_2_2__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_2_3__OVL_MATRIX_COEF_2_3__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_2_3__OVL_MATRIX_SIGN_2_3__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_2_4__OVL_MATRIX_COEF_2_4__SHIFT__SI 0x00000008 -#define OVL_MATRIX_COEF_2_4__OVL_MATRIX_SIGN_2_4__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_3_1__OVL_MATRIX_COEF_3_1__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_3_1__OVL_MATRIX_SIGN_3_1__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_3_2__OVL_MATRIX_COEF_3_2__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_3_2__OVL_MATRIX_SIGN_3_2__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_3_3__OVL_MATRIX_COEF_3_3__SHIFT__SI 0x00000000 -#define OVL_MATRIX_COEF_3_3__OVL_MATRIX_SIGN_3_3__SHIFT__SI 0x0000001f -#define OVL_MATRIX_COEF_3_4__OVL_MATRIX_COEF_3_4__SHIFT__SI 0x00000008 -#define OVL_MATRIX_COEF_3_4__OVL_MATRIX_SIGN_3_4__SHIFT__SI 0x0000001f -#define OVL_MATRIX_TRANSFORM_EN__OVL_MATRIX_TRANSFORM_EN__SHIFT__SI 0x00000000 -#define OVL_PITCH__OVL_PITCH__SHIFT__SI 0x00000000 -#define OVL_PWL_0TOF__OVL_PWL_0TOF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_0TOF__OVL_PWL_0TOF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_100TO13F__OVL_PWL_100TO13F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_100TO13F__OVL_PWL_100TO13F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_10TO1F__OVL_PWL_10TO1F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_10TO1F__OVL_PWL_10TO1F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_140TO17F__OVL_PWL_140TO17F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_140TO17F__OVL_PWL_140TO17F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_180TO1BF__OVL_PWL_180TO1BF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_180TO1BF__OVL_PWL_180TO1BF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_1C0TO1FF__OVL_PWL_1C0TO1FF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_1C0TO1FF__OVL_PWL_1C0TO1FF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_200TO23F__OVL_PWL_200TO23F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_200TO23F__OVL_PWL_200TO23F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_20TO3F__OVL_PWL_20TO3F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_20TO3F__OVL_PWL_20TO3F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_240TO27F__OVL_PWL_240TO27F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_240TO27F__OVL_PWL_240TO27F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_280TO2BF__OVL_PWL_280TO2BF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_280TO2BF__OVL_PWL_280TO2BF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_2C0TO2FF__OVL_PWL_2C0TO2FF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_2C0TO2FF__OVL_PWL_2C0TO2FF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_300TO33F__OVL_PWL_300TO33F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_300TO33F__OVL_PWL_300TO33F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_340TO37F__OVL_PWL_340TO37F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_340TO37F__OVL_PWL_340TO37F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_380TO3BF__OVL_PWL_380TO3BF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_380TO3BF__OVL_PWL_380TO3BF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_3C0TO3FF__OVL_PWL_3C0TO3FF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_3C0TO3FF__OVL_PWL_3C0TO3FF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_40TO7F__OVL_PWL_40TO7F_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_40TO7F__OVL_PWL_40TO7F_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_80TOBF__OVL_PWL_80TOBF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_80TOBF__OVL_PWL_80TOBF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_C0TOFF__OVL_PWL_C0TOFF_OFFSET__SHIFT__SI 0x00000000 -#define OVL_PWL_C0TOFF__OVL_PWL_C0TOFF_SLOPE__SHIFT__SI 0x00000010 -#define OVL_PWL_TRANSFORM_EN__OVL_PWL_TRANSFORM_EN__SHIFT__SI 0x00000000 -#define OVL_RT_BAND_POSITION__OVL_RT_BTM_SCAN__SHIFT__SI 0x00000010 -#define OVL_RT_BAND_POSITION__OVL_RT_TOP_SCAN__SHIFT__SI 0x00000000 -#define OVL_RT_PROCEED_COND__OVL_RT_CLEAR_GOBBLE_GO__SHIFT__SI 0x0000000e -#define OVL_RT_PROCEED_COND__OVL_RT_PROCEED_ON_EOF_DISABLE__SHIFT__SI 0x00000008 -#define OVL_RT_PROCEED_COND__OVL_RT_REDUCE_DELAY__SHIFT__SI 0x00000000 -#define OVL_RT_PROCEED_COND__OVL_RT_RT_FLIP__SHIFT__SI 0x00000004 -#define OVL_RT_PROCEED_COND__OVL_RT_TEAR_PROOF_HEIGHT__SHIFT__SI 0x00000010 -#define OVL_RT_PROCEED_COND__OVL_RT_WITH_HELD_ON_SOF__SHIFT__SI 0x0000000c -#define OVL_RT_SKEWCOMMAND__OVL_RT_CLEAR_GOBBLE_COUNT__SHIFT__SI 0x00000000 -#define OVL_RT_SKEWCOMMAND__OVL_RT_CLEAR_SUBMIT_COUNT__SHIFT__SI 0x00000008 -#define OVL_RT_SKEWCOMMAND__OVL_RT_GOBBLE_COUNT__SHIFT__SI 0x00000010 -#define OVL_RT_SKEWCOMMAND__OVL_RT_INC_GOBBLE_COUNT__SHIFT__SI 0x00000004 -#define OVL_RT_SKEWCOMMAND__OVL_RT_INC_SUBMIT_COUNT__SHIFT__SI 0x0000000c -#define OVL_RT_SKEWCOMMAND__OVL_RT_SUBMIT_COUNT__SHIFT__SI 0x00000018 -#define OVL_RT_SKEWCONTROL__OVL_RT_CAPS__SHIFT__SI 0x00000000 -#define OVL_RT_SKEWCONTROL__OVL_RT_SKEW_MAX__SHIFT__SI 0x00000004 -#define OVL_RT_STAT__OVL_LINE_COUNTER__SHIFT__SI 0x00000014 -#define OVL_RT_STAT__OVL_RT_BAND_INVISIBLE__SHIFT__SI 0x00000008 -#define OVL_RT_STAT__OVL_RT_BAND_SYNC__SHIFT__SI 0x00000009 -#define OVL_RT_STAT__OVL_RT_EOF_PRPCEED__SHIFT__SI 0x0000000a -#define OVL_RT_STAT__OVL_RT_FIP_PROCEED_ACK__SHIFT__SI 0x00000000 -#define OVL_RT_STAT__OVL_RT_FIP_PROCEED__SHIFT__SI 0x0000000b -#define OVL_RT_STAT__OVL_RT_FRAME_SYNC_ACK__SHIFT__SI 0x00000001 -#define OVL_RT_STAT__OVL_RT_FRAME_SYNC__SHIFT__SI 0x0000000c -#define OVL_RT_STAT__OVL_RT_GOBBLE_GO__SHIFT__SI 0x0000000d -#define OVL_RT_STAT__OVL_RT_NEW_SUBMIT__SHIFT__SI 0x0000000e -#define OVL_RT_STAT__OVL_RT_OVL_ENDED__SHIFT__SI 0x00000010 -#define OVL_RT_STAT__OVL_RT_OVL_START_ACK__SHIFT__SI 0x00000002 -#define OVL_RT_STAT__OVL_RT_OVL_START__SHIFT__SI 0x0000000f -#define OVL_RT_STAT__OVL_RT_SAFE_ZONE__SHIFT__SI 0x00000011 -#define OVL_RT_STAT__OVL_RT_SWITCH_REGIONS__SHIFT__SI 0x00000012 -#define OVL_RT_STAT__OVL_SKEW_MAX_REACHED__SHIFT__SI 0x00000013 -#define OVL_START__OVL_X_START__SHIFT__SI 0x00000010 -#define OVL_START__OVL_Y_START__SHIFT__SI 0x00000000 -#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT__SI 0x00000000 -#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT__SI 0x00000000 -#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT__SI 0x00000008 -#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT__SI 0x00000000 -#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT__SI 0x00000008 -#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT__SI 0x00000000 -#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT__SI 0x00000000 -#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT__SI 0x0000000a -#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT__SI 0x00000008 -#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT__SI 0x00000000 -#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT__SI 0x00000006 -#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT__SI 0x00000004 -#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT__SI 0x00000018 -#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT__SI 0x00000010 -#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT__SI 0x00000001 -#define P1PLL_CNTL__P1PLL_ANTI_GLITCH_RESET__SHIFT__SI 0x0000000d -#define P1PLL_CNTL__P1PLL_BYPASS_CAL__SHIFT__SI 0x00000002 -#define P1PLL_CNTL__P1PLL_CALIB_DONE__SHIFT__SI 0x00000014 -#define P1PLL_CNTL__P1PLL_CALREF__SHIFT__SI 0x00000008 -#define P1PLL_CNTL__P1PLL_CAL_BYPASS_REFDIV__SHIFT__SI 0x0000000a -#define P1PLL_CNTL__P1PLL_DEBUG_SIGNALS_ENABLE__SHIFT__SI 0x0000000e -#define P1PLL_CNTL__P1PLL_DIFF_REC_ENABLE__SHIFT__SI 0x0000000c -#define P1PLL_CNTL__P1PLL_DIRECT_CLOCK_2X__SHIFT__SI 0x0000001f -#define P1PLL_CNTL__P1PLL_DVOCLK_SRC__SHIFT__SI 0x0000001e -#define P1PLL_CNTL__P1PLL_LOCKED__SHIFT__SI 0x00000015 -#define P1PLL_CNTL__P1PLL_LOCK_FREQ_SEL__SHIFT__SI 0x00000013 -#define P1PLL_CNTL__P1PLL_LVTMCLK_SRC__SHIFT__SI 0x0000001a -#define P1PLL_CNTL__P1PLL_PCIE_REFCLK_DISABLE__SHIFT__SI 0x0000000b -#define P1PLL_CNTL__P1PLL_PIXCLK_SRC__SHIFT__SI 0x0000001c -#define P1PLL_CNTL__P1PLL_PWRMGT_TURN_OFF_PLL__SHIFT__SI 0x00000010 -#define P1PLL_CNTL__P1PLL_RESET__SHIFT__SI 0x00000000 -#define P1PLL_CNTL__P1PLL_SLEEP__SHIFT__SI 0x00000001 -#define P1PLL_CNTL__P1PLL_TIMING_MODE_STATUS__SHIFT__SI 0x00000018 -#define P1PLL_CNTL__P1PLL_VCOREF__SHIFT__SI 0x00000004 -#define P1PLL_DEBUG_CLK_SEL__P1PLL_DEBUG_CLK_SEL__SHIFT__SI 0x00000000 -#define P1PLL_DS_CNTL__P1PLL_DS_FRAC__SHIFT__SI 0x00000000 -#define P1PLL_DS_CNTL__P1PLL_DS_MODE__SHIFT__SI 0x00000012 -#define P1PLL_DS_CNTL__P1PLL_DS_ORDER__SHIFT__SI 0x00000010 -#define P1PLL_DS_CNTL__P1PLL_DS_PRBS_EN__SHIFT__SI 0x00000013 -#define P1PLL_IDCLKA_CNTL__P1PLL_IDCLKA_SRCSEL_FORCE_ENABLE__SHIFT__SI 0x00000008 -#define P1PLL_IDCLKA_CNTL__P1PLL_IDCLKA_SRCSEL_FORCE_VALUE__SHIFT__SI 0x0000000c -#define P1PLL_IDCLKA_CNTL__P1PLL_IDCLKA_SRCSEL__SHIFT__SI 0x00000000 -#define P1PLL_IDCLKA_CNTL__P1PLL_LVTMCLK_SRC_FORCE_ENABLE__SHIFT__SI 0x00000010 -#define P1PLL_IDCLKA_CNTL__P1PLL_LVTMCLK_SRC_FORCE_VALUE__SHIFT__SI 0x00000014 -#define P1PLL_INT_SS_CNTL__P1PLL_SS_AMOUNT_FBDIV__SHIFT__SI 0x00000000 -#define P1PLL_INT_SS_CNTL__P1PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT__SI 0x00000008 -#define P1PLL_INT_SS_CNTL__P1PLL_SS_MODE__SHIFT__SI 0x0000000d -#define P1PLL_INT_SS_CNTL__P1PLL_SS_STEP_SIZE_DSFRAC__SHIFT__SI 0x00000010 -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_DETECT_ENABLE__SHIFT__SI 0x00000000 -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_DOWN_CNTL__SHIFT__SI 0x00000008 -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_DUTY_CYCLE_SELECT__SHIFT__SI 0x00000001 -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_STICKY_CLEAR__SHIFT__SI 0x00000003 -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_STICKY_STATUS__SHIFT__SI 0x00000002 -#define P1PLL_UNLOCK_DETECT_CNTL__P1PLL_UNLOCK_UP_CNTL__SHIFT__SI 0x00000004 -#define P1PLL_VREG_CNTL__P1PLL_VREG_BIAS__SHIFT__SI 0x00000018 -#define P1PLL_VREG_CNTL__P1PLL_VREG_CNTL__SHIFT__SI 0x00000000 -#define P1PLL_VREG_CNTL__P1PLL_VREG_POWER_DOWN__SHIFT__SI 0x0000001d -#define P2PLL_CNTL__P2PLL_ANTI_GLITCH_RESET__SHIFT__SI 0x0000000d -#define P2PLL_CNTL__P2PLL_BYPASS_CAL__SHIFT__SI 0x00000002 -#define P2PLL_CNTL__P2PLL_CALIB_DONE__SHIFT__SI 0x00000014 -#define P2PLL_CNTL__P2PLL_CALREF__SHIFT__SI 0x00000008 -#define P2PLL_CNTL__P2PLL_CAL_BYPASS_REFDIV__SHIFT__SI 0x0000000a -#define P2PLL_CNTL__P2PLL_DEBUG_SIGNALS_ENABLE__SHIFT__SI 0x0000000e -#define P2PLL_CNTL__P2PLL_DIFF_REC_ENABLE__SHIFT__SI 0x0000000c -#define P2PLL_CNTL__P2PLL_DIRECT_CLOCK_2X__SHIFT__SI 0x0000001f -#define P2PLL_CNTL__P2PLL_DVOCLK_SRC__SHIFT__SI 0x0000001e -#define P2PLL_CNTL__P2PLL_LOCKED__SHIFT__SI 0x00000015 -#define P2PLL_CNTL__P2PLL_LOCK_FREQ_SEL__SHIFT__SI 0x00000013 -#define P2PLL_CNTL__P2PLL_LVTMCLK_SRC__SHIFT__SI 0x0000001a -#define P2PLL_CNTL__P2PLL_PCIE_REFCLK_DISABLE__SHIFT__SI 0x0000000b -#define P2PLL_CNTL__P2PLL_PIXCLK_SRC__SHIFT__SI 0x0000001c -#define P2PLL_CNTL__P2PLL_PWRMGT_TURN_OFF_PLL__SHIFT__SI 0x00000010 -#define P2PLL_CNTL__P2PLL_RESET__SHIFT__SI 0x00000000 -#define P2PLL_CNTL__P2PLL_SLEEP__SHIFT__SI 0x00000001 -#define P2PLL_CNTL__P2PLL_TIMING_MODE_STATUS__SHIFT__SI 0x00000018 -#define P2PLL_CNTL__P2PLL_VCOREF__SHIFT__SI 0x00000004 -#define P2PLL_DEBUG_CLK_SEL__P2PLL_DEBUG_CLK_SEL__SHIFT__SI 0x00000008 -#define P2PLL_DS_CNTL__P2PLL_DS_FRAC__SHIFT__SI 0x00000000 -#define P2PLL_DS_CNTL__P2PLL_DS_MODE__SHIFT__SI 0x00000012 -#define P2PLL_DS_CNTL__P2PLL_DS_ORDER__SHIFT__SI 0x00000010 -#define P2PLL_DS_CNTL__P2PLL_DS_PRBS_EN__SHIFT__SI 0x00000013 -#define P2PLL_IDCLKB_CNTL__P2PLL_IDCLKB_SRCSEL_FORCE_ENABLE__SHIFT__SI 0x00000008 -#define P2PLL_IDCLKB_CNTL__P2PLL_IDCLKB_SRCSEL_FORCE_VALUE__SHIFT__SI 0x0000000c -#define P2PLL_IDCLKB_CNTL__P2PLL_IDCLKB_SRCSEL__SHIFT__SI 0x00000000 -#define P2PLL_IDCLKB_CNTL__P2PLL_LVTMCLK_SRC_FORCE_ENABLE__SHIFT__SI 0x00000010 -#define P2PLL_IDCLKB_CNTL__P2PLL_LVTMCLK_SRC_FORCE_VALUE__SHIFT__SI 0x00000014 -#define P2PLL_INT_SS_CNTL__P2PLL_SS_AMOUNT_FBDIV__SHIFT__SI 0x00000000 -#define P2PLL_INT_SS_CNTL__P2PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT__SI 0x00000008 -#define P2PLL_INT_SS_CNTL__P2PLL_SS_MODE__SHIFT__SI 0x0000000d -#define P2PLL_INT_SS_CNTL__P2PLL_SS_STEP_SIZE_DSFRAC__SHIFT__SI 0x00000010 -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_DETECT_ENABLE__SHIFT__SI 0x00000000 -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_DOWN_CNTL__SHIFT__SI 0x00000008 -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_DUTY_CYCLE_SELECT__SHIFT__SI 0x00000001 -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_STICKY_CLEAR__SHIFT__SI 0x00000003 -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_STICKY_STATUS__SHIFT__SI 0x00000002 -#define P2PLL_UNLOCK_DETECT_CNTL__P2PLL_UNLOCK_UP_CNTL__SHIFT__SI 0x00000004 -#define P2PLL_VREG_CNTL__P2PLL_VREG_BIAS__SHIFT__SI 0x00000018 -#define P2PLL_VREG_CNTL__P2PLL_VREG_CNTL__SHIFT__SI 0x00000000 -#define P2PLL_VREG_CNTL__P2PLL_VREG_POWER_DOWN__SHIFT__SI 0x0000001d -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x00000000 -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x00000019 -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x00000018 -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x0000001a -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 -#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x00000018 -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x00000016 -#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0x0000000e -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0x0000000d -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x00000011 -#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000 -#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x00000001 -#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x00000002 -#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x00000003 -#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x00000004 -#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x00000005 -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x00000019 -#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x0000001b -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x0000001a -#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x00000003 -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 -#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f -#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e -#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d -#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c -#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001 -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x00000004 -#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x00000005 -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0x0000000e -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0x0000000d -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0x0000000c -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x00000009 -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x00000008 -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0x0000000b -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0x0000000a -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x00000003 -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x00000014 -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x00000002 -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x00000006 -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x00000007 -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x00000000 -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x00000004 -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x00000001 -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x00000005 -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT__CI__VI 0x00000000 -#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x00000000 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x00000001 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x00000002 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x00000003 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x00000004 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x00000005 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x00000006 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x00000007 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x00000008 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x00000009 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0x0000000a -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0x0000000b -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0x0000000c -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0x0000000d -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0x0000000e -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0x0000000f -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x00000011 -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x00000019 -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x00000014 -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x00000010 -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x00000012 -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x00000013 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x00000016 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x00000017 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x00000018 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x00000015 -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 -#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a -#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 -#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x00000004 -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x00000018 -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x00000014 -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x00000000 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x00000010 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x00000000 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x0000001c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x0000001c -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x00000000 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x00000004 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x00000008 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0x0000000c -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x00000010 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x00000014 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x00000018 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x0000001c -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x00000008 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0x0000000c -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x00000010 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x00000014 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x00000018 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x0000001c -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x00000000 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x00000004 -#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x00000000 -#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 -#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x00000000 -#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x00000002 -#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x00000000 -#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x00000002 -#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x0000001c -#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0x0000000c -#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x00000012 -#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x00000018 -#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x00000004 -#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x00000008 -#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x00000000 -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x00000002 -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x00000009 -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT__CI__VI 0x0000001c -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT__CI__VI 0x0000000e -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT__CI__VI \ - 0x00000019 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT__CI__VI 0x00000015 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT__CI__VI 0x00000017 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT__CI__VI 0x00000012 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT__CI__VI 0x00000010 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT__CI__VI 0x00000016 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT__CI__VI 0x00000013 -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT__CI__VI 0x0000000d -#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x00000006 -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x00000005 -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x00000001 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT__CI__VI 0x0000000a -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT__CI__VI 0x0000000b -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT__CI__VI 0x0000000c -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT__CI__VI 0x0000001d -#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f -#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e -#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT__SI 0x0000001d -#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT__SI 0x0000001c -#define PA_SC_ENHANCE__ECO_SPARE4__SHIFT__SI 0x0000001b -#define PA_SC_ENHANCE__ECO_SPARE5__SHIFT__SI 0x0000001a -#define PA_SC_ENHANCE__ECO_SPARE6__SHIFT__SI 0x00000019 -#define PA_SC_ENHANCE__ECO_SPARE7__SHIFT__SI 0x00000018 -#define PA_SC_ENHANCE__ECO_SPARE8__SHIFT__SI 0x0000000c -#define PA_SC_ENHANCE__ECO_SPARE9__SHIFT__SI 0x0000000b -#define PA_SC_ENHANCE__ECO_SPAREA__SHIFT__SI 0x0000000a -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x00000003 -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x00000004 -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT__CI__VI 0x0000000f -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT__CI__VI 0x00000018 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT__CI__VI 0x00000011 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT__CI__VI 0x00000014 -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x00000000 -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT__CI__VI 0x0000001b -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT__CI__VI 0x0000001a -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x00000008 -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x00000000 -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x00000006 -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x00000017 -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x00000000 -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0x0000000f -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x00000000 -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x00000010 -#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT__CI__VI 0x00000000 -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT__CI__VI 0x00000000 -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT__CI__VI 0x00000001 -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT__CI__VI 0x00000000 -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT__CI__VI 0x00000000 -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT__CI__VI 0x00000000 -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT__CI__VI 0x00000000 -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x00000012 -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x00000006 -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x00000000 -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0x0000000c -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0x0000000c -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 -#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0x0000000b -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d -#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x00000002 -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x00000000 -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x00000003 -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x00000001 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x00000019 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x0000001a -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x00000013 -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x00000014 -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0x0000000f -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0x0000000e -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x00000018 -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x00000012 -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x00000011 -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x0000001b -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x0000001c -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x00000010 -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x00000007 -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x00000009 -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0x0000000a -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x00000008 -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x00000002 -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x00000001 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x00000003 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x00000004 -#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x00000000 -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0x0000000b -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0x0000000c -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0x0000000d -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT__CI__VI 0x00000000 -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT__CI__VI 0x00000000 -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT__CI__VI 0x00000001 -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT__CI__VI 0x00000000 -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT__CI__VI 0x00000000 -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT__CI__VI 0x00000000 -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT__CI__VI 0x00000000 -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT__CI__VI 0x00000000 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT__CI__VI 0x00000002 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT__CI__VI 0x00000004 -#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x00000008 -#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT__CI__VI 0x0000000e -#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0x0000000a -#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0x0000000c -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x00000000 -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x00000002 -#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x00000004 -#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x00000006 -#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x00000007 -#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x00000010 -#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x00000012 -#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x00000014 -#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x00000018 -#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x0000001a -#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x0000001c -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT__CI__VI 0x00000000 -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT__CI__VI 0x00000002 -#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT__CI__VI 0x00000000 -#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT__CI__VI 0x00000010 -#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT__CI__VI 0x00000000 -#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT__CI__VI 0x00000010 -#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT__CI__VI 0x00000000 -#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT__CI__VI 0x00000010 -#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT__CI__VI 0x00000000 -#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT__CI__VI 0x00000010 -#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT__CI__VI 0x00000000 -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT__CI__VI 0x00000000 -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT__CI__VI 0x00000001 -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT__CI__VI 0x00000000 -#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT__CI__VI 0x00000000 -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT__CI__VI 0x00000000 -#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT__CI__VI 0x00000000 -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x00000000 -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 -#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 -#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f -#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f -#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 -#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x00000000 -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x00000010 -#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x00000004 -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x00000002 -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x00000003 -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x00000000 -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x00000000 -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 -#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 -#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 -#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x00000000 -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x00000008 -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x00000000 -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x00000005 -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x00000001 -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x00000006 -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x00000002 -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x00000008 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x00000007 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x00000003 -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x00000004 -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x00000000 -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT__CI__VI 0x0000001e -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT__CI__VI 0x0000001f -#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 -#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 -#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 -#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 -#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 -#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 -#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 -#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT__CI__VI 0x00000000 -#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT__CI__VI 0x00000001 -#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT__CI__VI 0x00000008 -#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT__CI__VI 0x00000017 -#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT__CI__VI 0x00000007 -#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT__CI__VI 0x00000015 -#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT__CI__VI 0x00000016 -#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT__CI__VI 0x00000014 -#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT__CI__VI 0x00000000 -#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT__CI__VI 0x00000018 -#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT__CI__VI 0x00000010 -#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT__CI__VI 0x00000008 -#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT__CI__VI 0x00000000 -#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT__CI__VI 0x00000014 -#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT__CI__VI 0x00000011 -#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT__CI__VI 0x00000000 -#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT__CI__VI 0x00000000 -#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT__CI__VI 0x00000010 -#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT__CI__VI 0x00000008 -#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT__CI__VI 0x00000010 -#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT__CI__VI 0x00000014 -#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT__CI__VI 0x00000017 -#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT__CI__VI 0x00000018 -#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT__CI__VI 0x00000019 -#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT__CI__VI 0x0000001a -#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT__CI__VI 0x0000001e -#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT__CI__VI 0x0000001f -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT__CI__VI 0x00000001 -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT__CI__VI 0x00000007 -#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT__CI__VI 0x00000008 -#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT__CI__VI 0x0000000e -#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT__CI__VI 0x0000000f -#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT__CI__VI 0x00000016 -#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT__CI__VI 0x00000017 -#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT__CI__VI 0x0000001e -#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT__CI__VI 0x00000001 -#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT__CI__VI 0x00000008 -#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT__CI__VI 0x00000009 -#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT__CI__VI 0x00000010 -#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT__CI__VI 0x00000011 -#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT__CI__VI 0x00000018 -#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT__CI__VI 0x00000019 -#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT__CI__VI 0x00000005 -#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT__CI__VI 0x00000007 -#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT__CI__VI 0x00000009 -#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT__CI__VI 0x0000000e -#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT__CI__VI 0x0000000c -#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT__CI__VI 0x0000000b -#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT__CI__VI 0x00000012 -#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT__CI__VI 0x0000001f -#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT__CI__VI 0x00000016 -#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT__CI__VI 0x00000017 -#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT__CI__VI 0x0000001b -#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT__CI__VI 0x0000001c -#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT__CI__VI 0x00000015 -#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT__CI__VI 0x00000016 -#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT__CI__VI 0x00000012 -#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT__CI__VI 0x00000010 -#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT__CI__VI 0x0000001a -#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT__CI__VI 0x0000001c -#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT__CI__VI 0x0000001b -#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT__CI__VI 0x00000010 -#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT__CI__VI 0x0000000f -#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT__CI__VI 0x00000010 -#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT__CI__VI 0x00000002 -#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT__CI__VI 0x00000003 -#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000000 -#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT__CI 0x00000003 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT__CI 0x00000004 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT__CI__VI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT__CI__VI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT__CI__VI 0x00000008 -#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT__CI__VI 0x0000000c -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT__CI__VI 0x0000000c -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT__CI__VI 0x0000000d -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT__CI__VI 0x0000000e -#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT__CI__VI 0x0000000f -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT__CI__VI 0x00000012 -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT__CI__VI 0x00000016 -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT__CI__VI 0x0000001a -#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT__CI__VI 0x0000001e -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT__CI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT__CI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT__CI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT__CI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT__CI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT__CI 0x0000001c -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT__CI__VI 0x0000000c -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT__CI__VI 0x0000000d -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT__CI__VI 0x0000000e -#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT__CI__VI 0x0000000f -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT__CI__VI 0x00000012 -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT__CI__VI 0x00000016 -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT__CI__VI 0x0000001a -#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT__CI__VI 0x0000001e -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT__CI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT__CI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT__CI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT__CI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT__CI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT__CI 0x0000001c -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT__CI__VI 0x0000000e -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT__CI__VI 0x0000000f -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT__CI__VI 0x0000000c -#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT__CI__VI 0x0000000d -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT__CI__VI 0x0000001a -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT__CI__VI 0x0000001e -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT__CI__VI 0x00000012 -#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT__CI__VI 0x00000016 -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT__CI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT__CI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT__CI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT__CI 0x0000001c -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT__CI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT__CI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT__CI__VI 0x0000000c -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT__CI__VI 0x0000000d -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT__CI__VI 0x0000000e -#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT__CI__VI 0x0000000f -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT__CI__VI 0x00000012 -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT__CI__VI 0x00000016 -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT__CI__VI 0x0000001a -#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT__CI__VI 0x0000001e -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT__CI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT__CI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT__CI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT__CI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT__CI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT__CI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT__CI 0x0000001c -#define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT__CI 0x00000000 -#define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT__CI 0x00000001 -#define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT__CI 0x00000002 -#define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT__CI 0x00000003 -#define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT__CI 0x00000004 -#define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT__CI 0x00000005 -#define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT__CI 0x00000006 -#define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT__CI 0x00000007 -#define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT__CI 0x00000008 -#define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT__CI 0x00000009 -#define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT__CI 0x0000000a -#define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT__CI 0x0000000b -#define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT__CI 0x0000000c -#define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT__CI 0x0000000d -#define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT__CI 0x0000000e -#define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT__CI 0x0000000f -#define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT__CI 0x00000010 -#define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT__CI 0x00000011 -#define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT__CI 0x00000012 -#define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT__CI 0x00000013 -#define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT__CI 0x00000014 -#define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT__CI 0x00000015 -#define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT__CI 0x00000016 -#define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT__CI 0x00000017 -#define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT__CI 0x00000018 -#define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT__CI 0x00000019 -#define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT__CI 0x0000001a -#define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT__CI 0x0000001b -#define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT__CI 0x0000001c -#define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT__CI 0x0000001d -#define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT__CI 0x0000001e -#define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT__CI 0x0000001f -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT__CI 0x00000007 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT__CI 0x00000008 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT__CI 0x00000012 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT__CI 0x00000013 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT__CI 0x00000014 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT__CI 0x00000015 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT__CI 0x00000016 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT__CI 0x00000017 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT__CI 0x00000009 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT__CI 0x0000000a -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT__CI 0x0000000b -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT__CI 0x0000000c -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT__CI 0x0000000d -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT__CI 0x0000000e -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT__CI 0x0000000f -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT__CI 0x00000010 -#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT__CI 0x00000011 -#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT__CI 0x00000001 -#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT__CI 0x00000018 -#define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT__CI 0x00000001 -#define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT__CI 0x00000005 -#define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT__CI 0x00000009 -#define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT__CI 0x0000000d -#define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT__CI 0x00000008 -#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT__CI 0x00000014 -#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT__CI 0x00000004 -#define PB0_PIF_CNTL__ENABLE_CT_TRIGGER_CLKEN_FIX__SHIFT__CI 0x0000001e -#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT__CI 0x00000017 -#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT__CI 0x0000001c -#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT__CI 0x0000001d -#define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT__CI 0x00000011 -#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT__CI 0x00000003 -#define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT__CI 0x00000002 -#define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT__CI 0x0000000a -#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT__CI 0x00000006 -#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT__CI 0x00000007 -#define PB0_PIF_CNTL__RXEN_GATER__SHIFT__CI 0x00000018 -#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT__CI 0x0000000b -#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT__CI 0x00000000 -#define PB0_PIF_CNTL__TXGND_TIME__SHIFT__CI 0x00000010 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT__CI 0x00000000 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT__CI 0x00000001 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT__CI 0x00000002 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT__CI 0x00000003 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT__CI 0x00000004 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT__CI 0x00000005 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT__CI 0x00000006 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT__CI 0x00000007 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT__CI 0x00000008 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT__CI 0x00000009 -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT__CI 0x0000000a -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT__CI 0x0000000b -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT__CI 0x0000000c -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT__CI 0x0000000d -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT__CI 0x0000000e -#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT__CI 0x0000000f -#define PB0_PIF_PAIRING__MULTI_PIF__SHIFT__CI 0x00000019 -#define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT__CI 0x00000014 -#define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT__CI 0x00000005 -#define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT__CI 0x00000006 -#define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT__CI 0x00000007 -#define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT__CI 0x00000000 -#define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT__CI 0x00000001 -#define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT__CI 0x00000002 -#define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT__CI 0x00000003 -#define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT__CI 0x00000004 -#define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT__CI 0x0000000a -#define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT__CI 0x0000000b -#define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT__CI 0x00000008 -#define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT__CI 0x00000009 -#define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT__CI 0x00000011 -#define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT__CI 0x00000010 -#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT__CI 0x00000001 -#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT__CI 0x00000008 -#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT__CI 0x00000009 -#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT__CI 0x0000000e -#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT__CI 0x0000000f -#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT__CI 0x00000004 -#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT__CI 0x00000005 -#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT__CI 0x0000000a -#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT__CI 0x0000000b -#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT__CI 0x00000000 -#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT__CI 0x00000001 -#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT__CI 0x00000003 -#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT__CI 0x0000001c -#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT__CI 0x0000001d -#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT__CI 0x0000000a -#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT__CI 0x00000007 -#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT__CI 0x00000018 -#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT__CI 0x00000004 -#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT__CI 0x00000010 -#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT__CI 0x00000000 -#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT__CI 0x00000003 -#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT__CI 0x0000001c -#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT__CI 0x0000001d -#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT__CI 0x0000000a -#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT__CI 0x00000007 -#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT__CI 0x00000018 -#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT__CI 0x00000004 -#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT__CI 0x00000010 -#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT__CI 0x00000000 -#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT__CI 0x00000003 -#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT__CI 0x0000001c -#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT__CI 0x0000001d -#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT__CI 0x0000000a -#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT__CI 0x00000007 -#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT__CI 0x00000018 -#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT__CI 0x00000004 -#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT__CI 0x00000010 -#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT__CI 0x00000000 -#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT__CI 0x00000003 -#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT__CI 0x0000001c -#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT__CI 0x0000001d -#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT__CI 0x0000000a -#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT__CI 0x00000007 -#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT__CI 0x00000018 -#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT__CI 0x00000004 -#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT__CI 0x00000010 -#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT__CI 0x00000000 -#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT__CI__VI 0x00000000 -#define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT__CI 0x00000000 -#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT__CI 0x00000004 -#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT__CI 0x00000005 -#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT__CI 0x00000002 -#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT__CI 0x00000003 -#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT__CI 0x00000010 -#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT__CI 0x0000001a -#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT__CI 0x0000001b -#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT__CI 0x0000001c -#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT__CI 0x0000001d -#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT__CI 0x0000001e -#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT__CI 0x0000001f -#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT__CI 0x00000011 -#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT__CI 0x00000012 -#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT__CI 0x00000013 -#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT__CI 0x00000014 -#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT__CI 0x00000015 -#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT__CI 0x00000016 -#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT__CI 0x00000017 -#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT__CI 0x00000018 -#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT__CI 0x00000019 -#define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT__CI 0x00000008 -#define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT__CI 0x00000009 -#define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT__CI 0x0000000a -#define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT__CI 0x0000000b -#define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT__CI 0x0000000c -#define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT__CI 0x0000000d -#define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT__CI 0x0000000e -#define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT__CI 0x0000000f -#define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT__CI 0x00000001 -#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT__CI 0x00000006 -#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT__CI 0x00000000 -#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT__CI 0x00000004 -#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT__CI 0x00000005 -#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT__CI 0x00000002 -#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT__CI 0x00000003 -#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT__CI 0x00000008 -#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT__CI 0x00000001 -#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT__CI 0x00000006 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT__CI 0x00000000 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT__CI 0x0000000a -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT__CI 0x0000000b -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT__CI 0x0000000c -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT__CI 0x0000000d -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT__CI 0x0000000e -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT__CI 0x0000000f -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT__CI 0x00000001 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT__CI 0x00000002 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT__CI 0x00000003 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT__CI 0x00000004 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT__CI 0x00000005 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT__CI 0x00000006 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT__CI 0x00000007 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT__CI 0x00000008 -#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT__CI 0x00000009 -#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT__CI__VI 0x00000000 -#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT__CI__VI 0x00000002 -#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT__CI__VI 0x00000003 -#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x00000003 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT__CI__VI 0x00000007 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000009 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000008 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT__CI__VI 0x00000012 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT__CI__VI 0x0000000a -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x0000001c -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x00000013 -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT__CI__VI 0x0000001f -#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT__CI__VI 0x0000001d -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT__CI__VI 0x00000003 -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT__CI__VI 0x00000012 -#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT__CI__VI 0x0000000e -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000005 -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000007 -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000006 -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x00000009 -#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x00000008 -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT__CI__VI 0x00000000 -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT__CI__VI 0x00000002 -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT__CI__VI 0x00000003 -#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT__CI__VI 0x0000000b -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x00000008 -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT__CI__VI 0x0000000c -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT__CI__VI 0x00000009 -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT__CI__VI 0x0000000e -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT__CI__VI 0x0000000d -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT__CI__VI 0x0000001c -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT__CI__VI 0x0000000f -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x0000001f -#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x0000001e -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT__CI__VI 0x00000016 -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT__CI__VI 0x00000013 -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT__CI__VI 0x00000005 -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT__CI__VI 0x00000008 -#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT__CI__VI 0x00000006 -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT__CI__VI 0x0000000a -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000009 -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT__CI__VI 0x0000000c -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x0000000b -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x0000000e -#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x0000000d -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT__CI 0x00000008 -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x00000009 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x0000000a -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000000b -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000014 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000015 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x0000000c -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x0000000d -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000000e -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000016 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000017 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000008 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x00000001 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x00000002 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000003 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000010 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000011 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x00000004 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x00000005 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000006 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000012 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000013 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000007 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT__CI__VI 0x0000000a -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT__CI 0x0000001e -#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT__CI__VI 0x0000001e -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT__CI__VI 0x00000004 -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT__CI__VI 0x00000008 -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT__CI__VI 0x0000000c -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT__CI__VI 0x00000010 -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT__CI__VI 0x00000018 -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT__CI__VI 0x00000019 -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT__CI__VI 0x0000001a -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT__CI__VI 0x0000001b -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT__CI__VI 0x0000001c -#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT__CI__VI 0x0000001d -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT__CI__VI 0x0000000c -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT__CI__VI 0x00000010 -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT__CI__VI 0x00000018 -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT__CI__VI 0x0000001a -#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT__CI__VI 0x0000001c -#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT__CI__VI 0x0000001e -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT__CI__VI 0x00000001 -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT__CI__VI 0x00000002 -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT__CI__VI 0x00000018 -#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT__CI__VI 0x0000001c -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT__CI__VI 0x00000003 -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT__CI__VI 0x00000006 -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT__CI__VI 0x00000018 -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT__CI__VI 0x0000001c -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT__CI__VI 0x00000009 -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT__CI__VI 0x0000000c -#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT__CI__VI 0x0000000f -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT__CI__VI 0x00000005 -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT__CI__VI 0x0000000a -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT__CI__VI 0x0000000f -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT__CI__VI 0x00000010 -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT__CI__VI 0x00000011 -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT__CI__VI 0x00000012 -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT__CI__VI 0x00000013 -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT__CI__VI 0x0000001b -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT__CI__VI 0x0000001c -#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT__CI__VI 0x0000001d -#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT__CI__VI 0x0000001e -#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000001b -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT__CI__VI 0x00000004 -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT__CI__VI 0x00000008 -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT__CI__VI 0x0000000c -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT__CI__VI 0x00000010 -#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT__CI__VI 0x00000018 -#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000001a -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT__CI__VI 0x00000012 -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT__CI__VI 0x00000015 -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT__CI__VI 0x00000018 -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT__CI__VI 0x0000001b -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT__CI__VI 0x0000001c -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT__CI__VI 0x0000001d -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT__CI__VI 0x00000004 -#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT__CI__VI 0x00000008 -#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT__CI__VI 0x0000000c -#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000000d -#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT__CI 0x00000011 -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT__CI__VI 0x0000001f -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT__CI__VI 0x0000001e -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT__CI__VI 0x00000003 -#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT__CI__VI 0x00000002 -#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT__CI__VI 0x0000001d -#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT__CI__VI 0x0000001c -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x00000008 -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x00000006 -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT__CI__VI 0x0000000a -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT__CI__VI 0x0000000c -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT__CI__VI 0x0000000b -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x0000000e -#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x0000000d -#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT__CI__VI 0x00000010 -#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT__CI__VI 0x0000000f -#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000012 -#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000011 -#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000014 -#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000013 -#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000016 -#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000015 -#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT__CI__VI 0x00000018 -#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT__CI__VI 0x00000017 -#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT__CI 0x00000004 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT__CI 0x00000007 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT__CI 0x00000005 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT__CI 0x00000006 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT__CI 0x0000000c -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT__CI 0x0000000f -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT__CI 0x0000000d -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT__CI 0x0000000e -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT__CI 0x00000010 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT__CI 0x00000013 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT__CI 0x00000011 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT__CI 0x00000012 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT__CI 0x00000014 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT__CI 0x00000017 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT__CI 0x00000015 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT__CI 0x00000016 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT__CI 0x00000008 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT__CI 0x0000000b -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT__CI 0x00000009 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT__CI 0x0000000a -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT__CI 0x00000003 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT__CI 0x00000004 -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT__CI 0x00000004 -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT__CI 0x00000004 -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT__CI 0x00000004 -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT__CI 0x00000004 -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT__CI 0x00000004 -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT__CI 0x00000004 -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT__CI 0x00000004 -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT__CI 0x00000004 -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT__CI 0x00000004 -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT__CI 0x00000004 -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT__CI 0x00000004 -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT__CI 0x00000004 -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT__CI 0x00000004 -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT__CI 0x00000004 -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT__CI__VI 0x00000000 -#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT__CI__VI 0x0000000d -#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT__CI__VI 0x0000000a -#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT__CI__VI 0x0000000c -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT__CI__VI 0x00000003 -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT__CI__VI 0x00000007 -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT__CI__VI 0x00000008 -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT__CI__VI 0x00000009 -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT__CI 0x00000004 -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT__CI__VI 0x00000000 -#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT__CI__VI 0x00000005 -#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT__CI__VI 0x0000000f -#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT__CI__VI 0x00000015 -#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT__CI__VI 0x00000014 -#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT__CI__VI 0x00000003 -#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT__CI__VI 0x00000002 -#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT__CI__VI 0x00000010 -#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT__CI__VI 0x0000000e -#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT__CI__VI 0x00000001 -#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT__CI__VI 0x00000007 -#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT__CI__VI 0x0000000c -#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT__CI__VI 0x0000000d -#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT__CI__VI 0x00000001 -#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT__CI__VI 0x00000002 -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT__CI__VI 0x00000001 -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT__CI__VI 0x00000004 -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT__CI__VI 0x00000010 -#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT__CI__VI 0x0000000f -#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT__CI__VI 0x00000018 -#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT__CI__VI 0x0000000d -#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT__CI__VI 0x00000008 -#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT__CI__VI 0x0000000a -#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT__CI__VI 0x00000006 -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT__CI__VI 0x0000000c -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT__CI__VI 0x00000005 -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT__CI__VI 0x00000010 -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT__CI__VI 0x00000007 -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT__CI__VI 0x00000014 -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT__CI__VI 0x00000018 -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT__CI__VI 0x0000001f -#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT__CI__VI 0x00000001 -#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT__CI__VI 0x0000001c -#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT__CI__VI 0x00000005 -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT__CI__VI 0x0000000f -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT__CI__VI 0x0000000b -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT__CI__VI 0x00000001 -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT__CI__VI 0x00000019 -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT__CI__VI 0x0000001d -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT__CI__VI 0x00000007 -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT__CI__VI 0x00000008 -#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT__CI__VI 0x0000001f -#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT__CI__VI 0x00000002 -#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT__CI__VI 0x0000001d -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT__CI__VI 0x00000001 -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT__CI__VI 0x00000005 -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT__CI__VI 0x00000009 -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT__CI__VI 0x0000000e -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT__CI__VI 0x00000013 -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT__CI__VI 0x00000017 -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT__CI__VI 0x0000001b -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT__CI__VI 0x0000001c -#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT__CI__VI 0x0000001e -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT__CI__VI 0x0000000c -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT__CI__VI 0x0000000d -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT__CI__VI 0x0000000f -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT__CI__VI 0x00000010 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT__CI__VI 0x00000011 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT__CI__VI 0x00000012 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT__CI__VI 0x00000013 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT__CI__VI 0x00000001 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT__CI__VI 0x00000014 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT__CI__VI 0x00000015 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT__CI__VI 0x00000016 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT__CI__VI 0x00000017 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT__CI__VI 0x00000018 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT__CI__VI 0x00000019 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT__CI__VI 0x0000001a -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT__CI__VI 0x0000001b -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT__CI__VI 0x0000001c -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT__CI__VI 0x0000001d -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT__CI__VI 0x00000002 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT__CI__VI 0x0000001e -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT__CI__VI 0x0000001f -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT__CI__VI 0x00000006 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT__CI__VI 0x00000007 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT__CI__VI 0x00000001 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT__CI__VI 0x00000002 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT__CI__VI 0x00000006 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT__CI__VI 0x00000007 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT__CI__VI 0x0000000c -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT__CI__VI 0x0000000d -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT__CI__VI 0x0000000f -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT__CI__VI 0x00000010 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT__CI__VI 0x00000011 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT__CI__VI 0x00000012 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT__CI__VI 0x00000013 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT__CI__VI 0x00000014 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT__CI__VI 0x00000015 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT__CI__VI 0x00000016 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT__CI__VI 0x00000017 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT__CI__VI 0x00000018 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT__CI__VI 0x00000019 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT__CI__VI 0x0000001a -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT__CI__VI 0x0000001b -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT__CI__VI 0x0000001c -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT__CI__VI 0x0000001d -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT__CI__VI 0x0000001e -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT__CI__VI 0x0000001f -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT__CI__VI 0x00000001 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT__CI__VI 0x00000002 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT__CI__VI 0x00000006 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT__CI__VI 0x00000007 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT__CI__VI 0x0000000c -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT__CI__VI 0x0000000d -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT__CI__VI 0x0000000f -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT__CI__VI 0x00000010 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT__CI__VI 0x00000011 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT__CI__VI 0x00000012 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT__CI__VI 0x00000013 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT__CI__VI 0x00000014 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT__CI__VI 0x00000015 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT__CI__VI 0x00000016 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT__CI__VI 0x00000017 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT__CI__VI 0x00000018 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT__CI__VI 0x00000019 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT__CI__VI 0x0000001a -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT__CI__VI 0x0000001b -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT__CI__VI 0x0000001c -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT__CI__VI 0x0000001d -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT__CI__VI 0x0000001e -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT__CI__VI 0x0000001f -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT__CI__VI 0x00000006 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT__CI__VI 0x00000007 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT__CI__VI 0x0000000c -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT__CI__VI 0x0000000d -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT__CI__VI 0x00000001 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT__CI__VI 0x00000002 -#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT__CI__VI 0x00000016 -#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT__CI__VI 0x00000015 -#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT__CI__VI 0x00000013 -#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT__CI__VI 0x00000017 -#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT__CI 0x00000018 -#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT__CI__VI 0x00000014 -#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT__CI__VI 0x00000011 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT__CI__VI 0x0000001e -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT__CI__VI 0x0000000c -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT__CI__VI 0x0000000d -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT__CI__VI 0x0000000f -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT__CI__VI 0x00000001 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT__CI__VI 0x00000002 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT__CI__VI 0x00000006 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT__CI__VI 0x00000007 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT__CI__VI 0x00000010 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT__CI__VI 0x00000015 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT__CI__VI 0x00000016 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT__CI__VI 0x00000017 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT__CI__VI 0x00000011 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT__CI__VI 0x00000012 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT__CI__VI 0x00000013 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT__CI__VI 0x00000014 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT__CI__VI 0x00000018 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT__CI__VI 0x0000001b -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT__CI__VI 0x00000019 -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT__CI__VI 0x0000001a -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT__CI__VI 0x0000001c -#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT__CI__VI 0x0000001d -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x0000000d -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT__CI__VI 0x00000013 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000014 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x00000019 -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x0000001a -#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT__CI__VI 0x0000001e -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT__CI__VI 0x00000006 -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000007 -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x0000000c -#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT__CI__VI 0x0000000d -#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT__CI__VI 0x00000019 -#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT__CI__VI 0x0000000f -#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT__CI__VI 0x0000001b -#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT__CI__VI 0x0000001a -#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT__CI__VI 0x0000001d -#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT__CI__VI 0x0000001c -#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT__CI__VI 0x0000001f -#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT__CI__VI 0x0000001e -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x0000000c -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000010 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000014 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000019 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT__CI__VI 0x0000000b -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT__CI__VI 0x00000003 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT__CI__VI 0x00000002 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT__CI__VI 0x00000007 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT__CI__VI 0x00000006 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x0000000a -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x0000000e -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000012 -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000017 -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x0000001c -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000008 -#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000005 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT__CI 0x00000008 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT__CI 0x0000000b -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT__CI 0x00000009 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT__CI 0x0000000a -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT__CI 0x0000000c -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT__CI 0x0000000f -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT__CI 0x0000000d -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT__CI 0x0000000e -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT__CI 0x00000004 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT__CI 0x00000007 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT__CI 0x00000005 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT__CI 0x00000006 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT__CI 0x00000003 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT__CI 0x00000003 -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT__CI 0x00000003 -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT__CI 0x00000003 -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT__CI 0x00000003 -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT__CI 0x00000003 -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT__CI 0x00000003 -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT__CI 0x00000003 -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT__CI 0x00000003 -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT__CI 0x00000003 -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT__CI 0x00000003 -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT__CI 0x00000003 -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT__CI 0x00000003 -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT__CI 0x00000003 -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT__CI 0x00000003 -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT__CI 0x00000003 -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT__CI__VI 0x00000001 -#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT__CI__VI 0x00000000 -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT__CI__VI 0x00000003 -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT__CI__VI 0x00000002 -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT__CI__VI 0x00000005 -#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT__CI__VI 0x00000006 -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT__CI__VI 0x00000008 -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT__CI__VI 0x0000000a -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT__CI__VI 0x00000007 -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT__CI 0x00000003 -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT__CI__VI 0x00000004 -#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT__CI__VI 0x00000000 -#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT__CI__VI 0x00000000 -#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT__CI__VI 0x00000001 -#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT__CI__VI 0x00000008 -#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT__CI__VI 0x00000017 -#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT__CI__VI 0x00000007 -#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT__CI__VI 0x00000015 -#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT__CI__VI 0x00000016 -#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT__CI__VI 0x00000014 -#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT__CI__VI 0x00000000 -#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT__CI__VI 0x00000018 -#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT__CI__VI 0x00000010 -#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT__CI__VI 0x00000008 -#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT__CI__VI 0x00000000 -#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT__CI__VI 0x00000014 -#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT__CI__VI 0x00000011 -#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT__CI__VI 0x00000000 -#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT__CI__VI 0x00000000 -#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT__CI__VI 0x00000010 -#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT__CI__VI 0x00000008 -#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT__CI__VI 0x00000010 -#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT__CI__VI 0x00000014 -#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT__CI__VI 0x00000017 -#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT__CI__VI 0x00000018 -#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT__CI__VI 0x00000019 -#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT__CI__VI 0x0000001a -#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT__CI__VI 0x0000001e -#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT__CI__VI 0x0000001f -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT__CI__VI 0x00000001 -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT__CI__VI 0x00000007 -#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT__CI__VI 0x00000008 -#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT__CI__VI 0x0000000e -#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT__CI__VI 0x0000000f -#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT__CI__VI 0x00000016 -#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT__CI__VI 0x00000017 -#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT__CI__VI 0x0000001e -#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT__CI__VI 0x00000001 -#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT__CI__VI 0x00000008 -#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT__CI__VI 0x00000009 -#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT__CI__VI 0x00000010 -#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT__CI__VI 0x00000011 -#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT__CI__VI 0x00000018 -#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT__CI__VI 0x00000019 -#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT__CI__VI 0x00000005 -#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT__CI__VI 0x00000007 -#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT__CI__VI 0x00000009 -#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT__CI__VI 0x0000000e -#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT__CI__VI 0x0000000c -#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT__CI__VI 0x0000000b -#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT__CI__VI 0x00000012 -#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT__CI__VI 0x0000001f -#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT__CI__VI 0x00000016 -#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT__CI__VI 0x00000017 -#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT__CI__VI 0x0000001b -#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT__CI__VI 0x0000001c -#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT__CI__VI 0x00000015 -#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT__CI__VI 0x00000016 -#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT__CI__VI 0x00000012 -#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT__CI__VI 0x00000010 -#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT__CI__VI 0x0000001a -#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT__CI__VI 0x0000001c -#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT__CI__VI 0x0000001b -#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT__CI__VI 0x00000010 -#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT__CI__VI 0x0000000f -#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT__CI__VI 0x00000010 -#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT__CI__VI 0x00000002 -#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT__CI__VI 0x00000003 -#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000000 -#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT__CI 0x00000003 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT__CI 0x00000004 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT__CI__VI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT__CI__VI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT__CI__VI 0x00000008 -#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT__CI__VI 0x0000000c -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT__CI__VI 0x0000000c -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT__CI__VI 0x0000000d -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT__CI__VI 0x0000000e -#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT__CI__VI 0x0000000f -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT__CI__VI 0x00000012 -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT__CI__VI 0x00000016 -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT__CI__VI 0x0000001a -#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT__CI__VI 0x0000001e -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT__CI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT__CI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT__CI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT__CI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT__CI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT__CI 0x0000001c -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT__CI__VI 0x0000000c -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT__CI__VI 0x0000000d -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT__CI__VI 0x0000000e -#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT__CI__VI 0x0000000f -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT__CI__VI 0x00000012 -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT__CI__VI 0x00000016 -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT__CI__VI 0x0000001a -#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT__CI__VI 0x0000001e -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT__CI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT__CI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT__CI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT__CI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT__CI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT__CI 0x0000001c -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT__CI__VI 0x0000000e -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT__CI__VI 0x0000000f -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT__CI__VI 0x0000000c -#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT__CI__VI 0x0000000d -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT__CI__VI 0x0000001a -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT__CI__VI 0x0000001e -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT__CI__VI 0x00000012 -#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT__CI__VI 0x00000016 -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT__CI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT__CI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT__CI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT__CI 0x0000001c -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT__CI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT__CI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT__CI__VI 0x0000000c -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT__CI__VI 0x0000000d -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT__CI__VI 0x0000000e -#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT__CI__VI 0x0000000f -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT__CI__VI 0x00000012 -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT__CI__VI 0x00000016 -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT__CI__VI 0x0000001a -#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT__CI__VI 0x0000001e -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT__CI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT__CI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT__CI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT__CI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT__CI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT__CI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT__CI 0x0000001c -#define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT__CI 0x00000000 -#define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT__CI 0x00000001 -#define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT__CI 0x00000002 -#define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT__CI 0x00000003 -#define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT__CI 0x00000004 -#define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT__CI 0x00000005 -#define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT__CI 0x00000006 -#define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT__CI 0x00000007 -#define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT__CI 0x00000008 -#define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT__CI 0x00000009 -#define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT__CI 0x0000000a -#define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT__CI 0x0000000b -#define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT__CI 0x0000000c -#define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT__CI 0x0000000d -#define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT__CI 0x0000000e -#define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT__CI 0x0000000f -#define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT__CI 0x00000010 -#define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT__CI 0x00000011 -#define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT__CI 0x00000012 -#define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT__CI 0x00000013 -#define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT__CI 0x00000014 -#define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT__CI 0x00000015 -#define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT__CI 0x00000016 -#define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT__CI 0x00000017 -#define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT__CI 0x00000018 -#define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT__CI 0x00000019 -#define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT__CI 0x0000001a -#define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT__CI 0x0000001b -#define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT__CI 0x0000001c -#define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT__CI 0x0000001d -#define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT__CI 0x0000001e -#define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT__CI 0x0000001f -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT__CI 0x00000007 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT__CI 0x00000008 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT__CI 0x00000012 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT__CI 0x00000013 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT__CI 0x00000014 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT__CI 0x00000015 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT__CI 0x00000016 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT__CI 0x00000017 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT__CI 0x00000009 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT__CI 0x0000000a -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT__CI 0x0000000b -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT__CI 0x0000000c -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT__CI 0x0000000d -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT__CI 0x0000000e -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT__CI 0x0000000f -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT__CI 0x00000010 -#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT__CI 0x00000011 -#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT__CI 0x00000001 -#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT__CI 0x00000018 -#define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT__CI 0x00000001 -#define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT__CI 0x00000005 -#define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT__CI 0x00000009 -#define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT__CI 0x0000000d -#define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT__CI 0x00000008 -#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT__CI 0x00000014 -#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT__CI 0x00000004 -#define PB1_PIF_CNTL__ENABLE_CT_TRIGGER_CLKEN_FIX__SHIFT__CI 0x0000001e -#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT__CI 0x00000017 -#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT__CI 0x0000001c -#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT__CI 0x0000001d -#define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT__CI 0x00000011 -#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT__CI 0x00000003 -#define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT__CI 0x00000002 -#define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT__CI 0x0000000a -#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT__CI 0x00000006 -#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT__CI 0x00000007 -#define PB1_PIF_CNTL__RXEN_GATER__SHIFT__CI 0x00000018 -#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT__CI 0x0000000b -#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT__CI 0x00000000 -#define PB1_PIF_CNTL__TXGND_TIME__SHIFT__CI 0x00000010 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT__CI 0x00000000 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT__CI 0x00000001 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT__CI 0x00000002 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT__CI 0x00000003 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT__CI 0x00000004 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT__CI 0x00000005 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT__CI 0x00000006 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT__CI 0x00000007 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT__CI 0x00000008 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT__CI 0x00000009 -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT__CI 0x0000000a -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT__CI 0x0000000b -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT__CI 0x0000000c -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT__CI 0x0000000d -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT__CI 0x0000000e -#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT__CI 0x0000000f -#define PB1_PIF_PAIRING__MULTI_PIF__SHIFT__CI 0x00000019 -#define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT__CI 0x00000014 -#define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT__CI 0x00000005 -#define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT__CI 0x00000006 -#define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT__CI 0x00000007 -#define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT__CI 0x00000000 -#define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT__CI 0x00000001 -#define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT__CI 0x00000002 -#define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT__CI 0x00000003 -#define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT__CI 0x00000004 -#define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT__CI 0x0000000a -#define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT__CI 0x0000000b -#define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT__CI 0x00000008 -#define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT__CI 0x00000009 -#define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT__CI 0x00000011 -#define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT__CI 0x00000010 -#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT__CI 0x00000001 -#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT__CI 0x00000008 -#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT__CI 0x00000009 -#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT__CI 0x0000000e -#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT__CI 0x0000000f -#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT__CI 0x00000004 -#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT__CI 0x00000005 -#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT__CI 0x0000000a -#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT__CI 0x0000000b -#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT__CI 0x00000000 -#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT__CI 0x00000001 -#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT__CI 0x00000003 -#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT__CI 0x0000001c -#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT__CI 0x0000001d -#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT__CI 0x0000000a -#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT__CI 0x00000007 -#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT__CI 0x00000018 -#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT__CI 0x00000004 -#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT__CI 0x00000010 -#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT__CI 0x00000000 -#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT__CI 0x00000003 -#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT__CI 0x0000001c -#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT__CI 0x0000001d -#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT__CI 0x0000000a -#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT__CI 0x00000007 -#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT__CI 0x00000018 -#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT__CI 0x00000004 -#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT__CI 0x00000010 -#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT__CI 0x00000000 -#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT__CI 0x00000003 -#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT__CI 0x0000001c -#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT__CI 0x0000001d -#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT__CI 0x0000000a -#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT__CI 0x00000007 -#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT__CI 0x00000018 -#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT__CI 0x00000004 -#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT__CI 0x00000010 -#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT__CI 0x00000000 -#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT__CI 0x00000003 -#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT__CI 0x0000001c -#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT__CI 0x0000001d -#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT__CI 0x0000000a -#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT__CI 0x00000007 -#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT__CI 0x00000018 -#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT__CI 0x00000004 -#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT__CI 0x00000010 -#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT__CI 0x00000000 -#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT__CI__VI 0x00000000 -#define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT__CI 0x00000000 -#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT__CI 0x00000004 -#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT__CI 0x00000005 -#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT__CI 0x00000002 -#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT__CI 0x00000003 -#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT__CI 0x00000010 -#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT__CI 0x0000001a -#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT__CI 0x0000001b -#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT__CI 0x0000001c -#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT__CI 0x0000001d -#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT__CI 0x0000001e -#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT__CI 0x0000001f -#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT__CI 0x00000011 -#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT__CI 0x00000012 -#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT__CI 0x00000013 -#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT__CI 0x00000014 -#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT__CI 0x00000015 -#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT__CI 0x00000016 -#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT__CI 0x00000017 -#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT__CI 0x00000018 -#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT__CI 0x00000019 -#define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT__CI 0x00000008 -#define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT__CI 0x00000009 -#define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT__CI 0x0000000a -#define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT__CI 0x0000000b -#define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT__CI 0x0000000c -#define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT__CI 0x0000000d -#define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT__CI 0x0000000e -#define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT__CI 0x0000000f -#define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT__CI 0x00000001 -#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT__CI 0x00000006 -#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT__CI 0x00000000 -#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT__CI 0x00000004 -#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT__CI 0x00000005 -#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT__CI 0x00000002 -#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT__CI 0x00000003 -#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT__CI 0x00000008 -#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT__CI 0x00000001 -#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT__CI 0x00000006 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT__CI 0x00000000 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT__CI 0x0000000a -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT__CI 0x0000000b -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT__CI 0x0000000c -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT__CI 0x0000000d -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT__CI 0x0000000e -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT__CI 0x0000000f -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT__CI 0x00000001 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT__CI 0x00000002 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT__CI 0x00000003 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT__CI 0x00000004 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT__CI 0x00000005 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT__CI 0x00000006 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT__CI 0x00000007 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT__CI 0x00000008 -#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT__CI 0x00000009 -#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT__CI__VI 0x00000000 -#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT__CI__VI 0x00000002 -#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT__CI__VI 0x00000003 -#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x00000003 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT__CI__VI 0x00000007 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000009 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000008 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT__CI__VI 0x00000012 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT__CI__VI 0x0000000a -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x0000001c -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x00000013 -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT__CI__VI 0x0000001f -#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT__CI__VI 0x0000001d -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT__CI__VI 0x00000003 -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT__CI__VI 0x00000012 -#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT__CI__VI 0x0000000e -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000005 -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000007 -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000006 -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x00000009 -#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x00000008 -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT__CI__VI 0x00000000 -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT__CI__VI 0x00000002 -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT__CI__VI 0x00000003 -#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT__CI__VI 0x0000000b -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x00000008 -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT__CI__VI 0x0000000c -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT__CI__VI 0x00000009 -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT__CI__VI 0x0000000e -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT__CI__VI 0x0000000d -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT__CI__VI 0x0000001c -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT__CI__VI 0x0000000f -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT__CI__VI 0x0000001f -#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT__CI__VI 0x0000001e -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT__CI__VI 0x00000016 -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT__CI__VI 0x00000013 -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT__CI__VI 0x00000005 -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT__CI__VI 0x00000008 -#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT__CI__VI 0x00000006 -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT__CI__VI 0x0000000a -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000009 -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT__CI__VI 0x0000000c -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT__CI__VI 0x0000000b -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x0000000e -#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x0000000d -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT__CI 0x00000008 -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT__CI 0x00000001 -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT__CI 0x00000000 -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x00000009 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x0000000a -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000000b -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000014 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000015 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x0000000c -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x0000000d -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000000e -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000016 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000017 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000008 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x00000001 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x00000002 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000003 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000010 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000011 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT__CI__VI 0x00000004 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT__CI__VI 0x00000005 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000006 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT__CI 0x00000012 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT__CI 0x00000013 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x00000007 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT__CI__VI 0x0000000a -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT__CI 0x0000001e -#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT__CI__VI 0x0000001e -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT__CI__VI 0x00000004 -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT__CI__VI 0x00000008 -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT__CI__VI 0x0000000c -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT__CI__VI 0x00000010 -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT__CI__VI 0x00000018 -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT__CI__VI 0x00000019 -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT__CI__VI 0x0000001a -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT__CI__VI 0x0000001b -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT__CI__VI 0x0000001c -#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT__CI__VI 0x0000001d -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT__CI__VI 0x0000000c -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT__CI__VI 0x00000010 -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT__CI__VI 0x00000018 -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT__CI__VI 0x0000001a -#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT__CI__VI 0x0000001c -#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT__CI__VI 0x0000001e -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT__CI__VI 0x00000001 -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT__CI__VI 0x00000002 -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT__CI__VI 0x00000018 -#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT__CI__VI 0x0000001c -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT__CI__VI 0x00000003 -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT__CI__VI 0x00000006 -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT__CI__VI 0x00000018 -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT__CI__VI 0x0000001c -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT__CI__VI 0x00000009 -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT__CI__VI 0x0000000c -#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT__CI__VI 0x0000000f -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT__CI__VI 0x00000005 -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT__CI__VI 0x0000000a -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT__CI__VI 0x0000000f -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT__CI__VI 0x00000010 -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT__CI__VI 0x00000011 -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT__CI__VI 0x00000012 -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT__CI__VI 0x00000013 -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT__CI__VI 0x0000001b -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT__CI__VI 0x0000001c -#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT__CI__VI 0x0000001d -#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT__CI__VI 0x0000001e -#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000001b -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT__CI__VI 0x00000004 -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT__CI__VI 0x00000008 -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT__CI__VI 0x0000000c -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT__CI__VI 0x00000010 -#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT__CI__VI 0x00000018 -#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000001a -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT__CI__VI 0x00000012 -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT__CI__VI 0x00000015 -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT__CI__VI 0x00000018 -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT__CI__VI 0x0000001b -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT__CI__VI 0x0000001c -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT__CI__VI 0x0000001d -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT__CI__VI 0x00000004 -#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT__CI__VI 0x00000008 -#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT__CI__VI 0x0000000c -#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT__CI__VI 0x0000000d -#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT__CI 0x00000011 -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT__CI__VI 0x0000001f -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT__CI__VI 0x0000001e -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT__CI__VI 0x00000003 -#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT__CI__VI 0x00000002 -#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT__CI__VI 0x0000001d -#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT__CI__VI 0x0000001c -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x00000008 -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x00000006 -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT__CI__VI 0x0000000a -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT__CI__VI 0x0000000c -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT__CI__VI 0x0000000b -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x0000000e -#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x0000000d -#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT__CI__VI 0x00000010 -#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT__CI__VI 0x0000000f -#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000012 -#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000011 -#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000014 -#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000013 -#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT__CI__VI 0x00000016 -#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT__CI__VI 0x00000015 -#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT__CI__VI 0x00000018 -#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT__CI__VI 0x00000017 -#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT__CI 0x00000004 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT__CI 0x00000007 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT__CI 0x00000005 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT__CI 0x00000006 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT__CI 0x0000000c -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT__CI 0x0000000f -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT__CI 0x0000000d -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT__CI 0x0000000e -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT__CI 0x00000010 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT__CI 0x00000013 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT__CI 0x00000011 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT__CI 0x00000012 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT__CI 0x00000014 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT__CI 0x00000017 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT__CI 0x00000015 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT__CI 0x00000016 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT__CI 0x00000008 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT__CI 0x0000000b -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT__CI 0x00000009 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT__CI 0x0000000a -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT__CI 0x00000003 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT__CI 0x00000004 -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT__CI 0x00000004 -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT__CI 0x00000004 -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT__CI 0x00000004 -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT__CI 0x00000004 -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT__CI 0x00000004 -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT__CI 0x00000004 -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT__CI 0x00000004 -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT__CI 0x00000004 -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT__CI 0x00000004 -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT__CI 0x00000004 -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT__CI 0x00000004 -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT__CI 0x00000004 -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT__CI 0x00000004 -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT__CI 0x00000004 -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT__CI__VI 0x00000000 -#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT__CI__VI 0x0000000d -#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT__CI__VI 0x0000000a -#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT__CI__VI 0x0000000c -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT__CI__VI 0x00000003 -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT__CI__VI 0x00000007 -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT__CI__VI 0x00000008 -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT__CI__VI 0x00000009 -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT__CI 0x00000004 -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT__CI__VI 0x00000000 -#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT__CI__VI 0x00000005 -#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT__CI__VI 0x0000000f -#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT__CI__VI 0x00000015 -#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT__CI__VI 0x00000014 -#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT__CI__VI 0x00000003 -#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT__CI__VI 0x00000002 -#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT__CI__VI 0x00000010 -#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT__CI__VI 0x0000000e -#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT__CI__VI 0x00000001 -#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT__CI__VI 0x00000007 -#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT__CI__VI 0x0000000c -#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT__CI__VI 0x0000000d -#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT__CI__VI 0x00000001 -#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT__CI__VI 0x00000002 -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT__CI__VI 0x00000001 -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT__CI__VI 0x00000004 -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT__CI__VI 0x00000010 -#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT__CI__VI 0x0000000f -#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT__CI__VI 0x00000018 -#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT__CI__VI 0x0000000d -#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT__CI__VI 0x00000008 -#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT__CI__VI 0x0000000a -#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT__CI__VI 0x00000006 -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT__CI__VI 0x0000000c -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT__CI__VI 0x00000005 -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT__CI__VI 0x00000010 -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT__CI__VI 0x00000007 -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT__CI__VI 0x00000014 -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT__CI__VI 0x00000018 -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT__CI__VI 0x0000001f -#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT__CI__VI 0x00000001 -#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT__CI__VI 0x0000001c -#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT__CI__VI 0x00000005 -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT__CI__VI 0x0000000f -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT__CI__VI 0x0000000b -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT__CI__VI 0x00000001 -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT__CI__VI 0x00000019 -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT__CI__VI 0x0000001d -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT__CI__VI 0x00000007 -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT__CI__VI 0x00000008 -#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT__CI__VI 0x0000001f -#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT__CI__VI 0x00000002 -#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT__CI__VI 0x0000001d -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT__CI__VI 0x00000001 -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT__CI__VI 0x00000005 -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT__CI__VI 0x00000009 -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT__CI__VI 0x0000000e -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT__CI__VI 0x00000013 -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT__CI__VI 0x00000017 -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT__CI__VI 0x0000001b -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT__CI__VI 0x0000001c -#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT__CI__VI 0x0000001e -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT__CI__VI 0x0000000c -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT__CI__VI 0x0000000d -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT__CI__VI 0x0000000f -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT__CI__VI 0x00000010 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT__CI__VI 0x00000011 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT__CI__VI 0x00000012 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT__CI__VI 0x00000013 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT__CI__VI 0x00000001 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT__CI__VI 0x00000014 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT__CI__VI 0x00000015 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT__CI__VI 0x00000016 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT__CI__VI 0x00000017 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT__CI__VI 0x00000018 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT__CI__VI 0x00000019 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT__CI__VI 0x0000001a -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT__CI__VI 0x0000001b -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT__CI__VI 0x0000001c -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT__CI__VI 0x0000001d -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT__CI__VI 0x00000002 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT__CI__VI 0x0000001e -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT__CI__VI 0x0000001f -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT__CI__VI 0x00000006 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT__CI__VI 0x00000007 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT__CI__VI 0x00000001 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT__CI__VI 0x00000002 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT__CI__VI 0x00000006 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT__CI__VI 0x00000007 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT__CI__VI 0x0000000c -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT__CI__VI 0x0000000d -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT__CI__VI 0x0000000f -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT__CI__VI 0x00000010 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT__CI__VI 0x00000011 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT__CI__VI 0x00000012 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT__CI__VI 0x00000013 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT__CI__VI 0x00000014 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT__CI__VI 0x00000015 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT__CI__VI 0x00000016 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT__CI__VI 0x00000017 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT__CI__VI 0x00000018 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT__CI__VI 0x00000019 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT__CI__VI 0x0000001a -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT__CI__VI 0x0000001b -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT__CI__VI 0x0000001c -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT__CI__VI 0x0000001d -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT__CI__VI 0x0000001e -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT__CI__VI 0x0000001f -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT__CI__VI 0x00000001 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT__CI__VI 0x00000002 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT__CI__VI 0x00000006 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT__CI__VI 0x00000007 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT__CI__VI 0x0000000c -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT__CI__VI 0x0000000d -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT__CI__VI 0x0000000f -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT__CI__VI 0x00000010 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT__CI__VI 0x00000011 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT__CI__VI 0x00000012 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT__CI__VI 0x00000013 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT__CI__VI 0x00000014 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT__CI__VI 0x00000015 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT__CI__VI 0x00000016 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT__CI__VI 0x00000017 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT__CI__VI 0x00000018 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT__CI__VI 0x00000019 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT__CI__VI 0x0000001a -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT__CI__VI 0x0000001b -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT__CI__VI 0x0000001c -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT__CI__VI 0x0000001d -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT__CI__VI 0x0000001e -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT__CI__VI 0x0000001f -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT__CI__VI 0x00000006 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT__CI__VI 0x00000007 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT__CI__VI 0x0000000c -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT__CI__VI 0x0000000d -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT__CI__VI 0x00000001 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT__CI__VI 0x00000002 -#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT__CI__VI 0x00000016 -#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT__CI__VI 0x00000015 -#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT__CI__VI 0x00000013 -#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT__CI__VI 0x00000017 -#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT__CI 0x00000018 -#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT__CI__VI 0x00000014 -#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT__CI__VI 0x00000011 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT__CI__VI 0x0000001e -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT__CI__VI 0x0000000c -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT__CI__VI 0x0000000d -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT__CI__VI 0x0000000f -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT__CI__VI 0x00000001 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT__CI__VI 0x00000002 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT__CI__VI 0x00000006 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT__CI__VI 0x00000007 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT__CI__VI 0x00000010 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT__CI__VI 0x00000015 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT__CI__VI 0x00000016 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT__CI__VI 0x00000017 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT__CI__VI 0x00000011 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT__CI__VI 0x00000012 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT__CI__VI 0x00000013 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT__CI__VI 0x00000014 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT__CI__VI 0x00000018 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT__CI__VI 0x0000001b -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT__CI__VI 0x00000019 -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT__CI__VI 0x0000001a -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT__CI__VI 0x0000001c -#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT__CI__VI 0x0000001d -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x0000000d -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT__CI__VI 0x00000013 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000014 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x00000019 -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x0000001a -#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT__CI__VI 0x0000001e -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT__CI__VI 0x00000006 -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT__CI__VI 0x00000007 -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT__CI__VI 0x0000000c -#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT__CI__VI 0x0000000d -#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT__CI__VI 0x00000019 -#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT__CI__VI 0x0000000f -#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT__CI__VI 0x0000001b -#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT__CI__VI 0x0000001a -#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT__CI__VI 0x0000001d -#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT__CI__VI 0x0000001c -#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT__CI__VI 0x0000001f -#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT__CI__VI 0x0000001e -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x0000000c -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000010 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000014 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000019 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT__CI__VI 0x0000000b -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT__CI__VI 0x00000003 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT__CI__VI 0x00000002 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT__CI__VI 0x00000007 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT__CI__VI 0x00000006 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT__CI__VI 0x00000001 -#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x0000000a -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x0000000e -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000012 -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000017 -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x0000001c -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000008 -#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT__CI__VI 0x00000009 -#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000000 -#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000004 -#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT__CI__VI 0x00000005 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT__CI 0x00000008 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT__CI 0x0000000b -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT__CI 0x00000009 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT__CI 0x0000000a -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT__CI 0x0000000c -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT__CI 0x0000000f -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT__CI 0x0000000d -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT__CI 0x0000000e -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT__CI 0x00000004 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT__CI 0x00000007 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT__CI 0x00000005 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT__CI 0x00000006 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT__CI 0x00000000 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT__CI 0x00000003 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT__CI 0x00000001 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT__CI 0x00000002 -#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT__CI 0x00000003 -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT__CI 0x00000003 -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT__CI 0x00000003 -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT__CI 0x00000003 -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT__CI 0x00000003 -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT__CI 0x00000003 -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT__CI 0x00000003 -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT__CI 0x00000003 -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT__CI 0x00000003 -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT__CI 0x00000003 -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT__CI 0x00000003 -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT__CI 0x00000003 -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT__CI 0x00000003 -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT__CI 0x00000003 -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT__CI 0x00000003 -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT__CI__VI 0x00000001 -#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT__CI__VI 0x00000000 -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT__CI__VI 0x00000003 -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT__CI__VI 0x00000002 -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT__CI__VI 0x00000005 -#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT__CI__VI 0x00000006 -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT__CI__VI 0x00000008 -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT__CI__VI 0x0000000a -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT__CI__VI 0x00000007 -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT__CI 0x00000003 -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT__CI__VI 0x00000004 -#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT__CI__VI 0x00000000 -#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT__CI__VI 0x00000010 -#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT__CI__VI 0x00000008 -#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT__CI__VI 0x00000000 -#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f -#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT__CI__VI 0x00000010 -#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT__CI__VI 0x00000012 -#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_NS__SHIFT__SI 0x00000010 -#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x00000008 -#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x00000001 -#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x00000002 -#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x00000003 -#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x00000005 -#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT__CI__VI 0x00000004 -#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT__CI__VI 0x00000006 -#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT__SI 0x00000004 -#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x00000000 -#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x00000000 -#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x00000000 -#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x0000000f -#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0x0000000b -#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0x0000000c -#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0x0000000d -#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x00000000 -#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x00000010 -#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x00000002 -#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x00000004 -#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0x0000000e -#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x00000006 -#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x00000008 -#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT__CI__VI 0x00000001 -#define PCIEP_STRAP_MISC__STRAP_EXIT_LATENCY__SHIFT__SI 0x00000000 -#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT__CI__VI 0x00000002 -#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT__CI__VI 0x00000005 -#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT__CI__VI 0x00000003 -#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT__CI__VI 0x00000000 -#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT__SI 0x00000004 -#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT__CI__VI 0x00000006 -#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT__CI__VI 0x00000008 -#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT__CI__VI 0x00000003 -#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT__CI__VI 0x00000005 -#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT__CI__VI 0x00000002 -#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT__CI__VI 0x00000000 -#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT__CI__VI 0x00000001 -#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT__CI__VI 0x00000004 -#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT__CI__VI 0x00000006 -#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT__CI__VI 0x00000003 -#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT__CI__VI 0x00000005 -#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT__CI__VI 0x00000002 -#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT__CI__VI 0x00000000 -#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT__CI__VI 0x00000001 -#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT__CI__VI 0x00000004 -#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x00000007 -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x00000008 -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x00000005 -#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x00000006 -#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x00000000 -#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT__CI__VI 0x00000009 -#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT__CI__VI 0x0000000a -#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT__CI 0x0000000f -#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x00000000 -#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x00000010 -#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x00000014 -#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT__CI__VI 0x00000000 -#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT__CI__VI 0x00000005 -#define PCIE_ATS_CAP__RR_PROTECTION_FAULT__SHIFT__CI 0x00000006 -#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT__CI__VI 0x0000000f -#define PCIE_ATS_CNTL__STU__SHIFT__CI__VI 0x00000000 -#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT__CI__VI 0x00000000 -#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT__CI__VI 0x00000008 -#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT__CI__VI 0x00000005 -#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT__CI__VI 0x00000000 -#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT__CI__VI 0x00000008 -#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT__CI__VI 0x00000005 -#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT__CI__VI 0x00000000 -#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT__CI__VI 0x00000008 -#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT__CI__VI 0x00000005 -#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT__CI__VI 0x00000000 -#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT__CI__VI 0x00000008 -#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT__CI__VI 0x00000005 -#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT__CI__VI 0x00000000 -#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT__CI__VI 0x00000008 -#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT__CI__VI 0x00000005 -#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT__CI__VI 0x00000000 -#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT__CI__VI 0x00000008 -#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT__CI__VI 0x00000005 -#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_BUS_CNTL__BUS_DBL_RESYNC__SHIFT__SI 0x00000000 -#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x00000007 -#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000006 -#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT__CI__VI 0x0000000c -#define PCIE_B_P90_CNTL__B_P90IMP_BACKUP__SHIFT__SI 0x00000000 -#define PCIE_B_P90_CNTL__B_P90PLL_BACKUP__SHIFT__SI 0x0000000c -#define PCIE_CAC_DEVICE_CORRELATION__DEVICE_CORRELATION__SHIFT__SI 0x00000000 -#define PCIE_CAC_ENH_CAP_LIST__CAP_ID__SHIFT__SI 0x00000000 -#define PCIE_CAC_ENH_CAP_LIST__CAP_VER__SHIFT__SI 0x00000010 -#define PCIE_CAC_ENH_CAP_LIST__NEXT_PTR__SHIFT__SI 0x00000014 -#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x00000000 -#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x00000008 -#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x00000004 -#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x00000009 -#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x00000008 -#define PCIE_CAP__TCS_ROUTING_SUPPORTED__SHIFT__SI 0x0000000e -#define PCIE_CAP__VERSION__SHIFT 0x00000000 -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT__CI__VI 0x00000001 -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT__SI 0x00000000 -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT__CI__VI 0x00000002 -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT__CI__VI 0x00000000 -#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT__SI 0x00000001 -#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x00000004 -#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT__CI__VI 0x0000000d -#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x00000009 -#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x00000003 -#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x00000002 -#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0x0000000a -#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0x0000000b -#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT__CI__VI 0x0000000c -#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x00000008 -#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x00000006 -#define PCIE_CI_CNTL__CI_SLV_REQ_DELAY_EN__SHIFT__SI 0x00000018 -#define PCIE_CI_CNTL__CI_SLV_REQ_DELAY_TIMER__SHIFT__SI 0x00000019 -#define PCIE_CI_CNTL__TX_SLV_CPL_DELAY_EN__SHIFT__SI 0x0000000d -#define PCIE_CI_CNTL__TX_SLV_CPL_DELAY_TIMER__SHIFT__SI 0x0000000e -#define PCIE_CI_MST_C_RTR_TIMEOUT_CNTL__CI_MST_C_RTR_TIMEOUT_RST__SHIFT__SI 0x00000000 -#define PCIE_CI_MST_C_RTR_TIMEOUT_CNTL__CI_MST_C_RTR_TIMEOUT_VALUE__SHIFT__SI 0x00000004 -#define PCIE_CI_MST_R_RTR_TIMEOUT_CNTL__CI_MST_R_RTR_TIMEOUT_RST__SHIFT__SI 0x00000000 -#define PCIE_CI_MST_R_RTR_TIMEOUT_CNTL__CI_MST_R_RTR_TIMEOUT_VALUE__SHIFT__SI 0x00000004 -#define PCIE_CI_SLV_R_RTR_TIMEOUT_CNTL__CI_SLV_R_RTR_TIMEOUT_RST__SHIFT__SI 0x00000000 -#define PCIE_CI_SLV_R_RTR_TIMEOUT_CNTL__CI_SLV_R_RTR_TIMEOUT_VALUE__SHIFT__SI 0x00000004 -#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT__CI__VI 0x00000012 -#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT__CI__VI 0x00000016 -#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT__CI__VI 0x00000013 -#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT__CI__VI 0x00000017 -#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT__CI__VI 0x00000018 -#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT__CI__VI 0x00000011 -#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT__CI__VI 0x00000015 -#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT__CI__VI 0x00000010 -#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT__CI__VI 0x00000014 -#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x00000006 -#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x00000000 -#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x00000001 -#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x00000000 -#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT__CI__VI 0x00000001 -#define PCIE_CNTL__LC_PREVENT_SPD_CHG_OVERLAP__SHIFT__SI 0x00000017 -#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x00000009 -#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT__CI__VI 0x00000008 -#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT__CI__VI 0x00000017 -#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x0000001f -#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT__CI__VI 0x0000001e -#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT__CI__VI 0x0000000f -#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT__SI__CI 0x00000014 -#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x00000013 -#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x00000011 -#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x00000010 -#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x00000012 -#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x00000015 -#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x00000016 -#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0x0000000a -#define PCIE_CNTL__RX_SB_COMPLETE_FULL_FIX__SHIFT__SI 0x0000000d -#define PCIE_CNTL__RX_SB_REJECT_IF_FULL__SHIFT__SI 0x0000000e -#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x00000018 -#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x00000007 -#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT__CI__VI 0x00000019 -#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT__CI__VI 0x00000010 -#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT__CI__VI 0x00000014 -#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT__CI__VI 0x00000018 -#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT__CI__VI 0x00000011 -#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT__CI__VI 0x00000015 -#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x00000000 -#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0x0000000d -#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x00000007 -#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x00000006 -#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT__CI__VI 0x0000000e -#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT__CI__VI 0x0000000f -#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x00000000 -#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x00000008 -#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0x0000000c -#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x0000000d -#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x00000007 -#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x00000006 -#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT__CI__VI 0x0000000e -#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT__CI__VI 0x0000000f -#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x00000000 -#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x00000008 -#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0x0000000c -#define PCIE_DATA_2__PCIE_DATA__SHIFT__CI__VI 0x00000000 -#define PCIE_DATA__PCIE_DATA__SHIFT 0x00000000 -#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x00000010 -#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x00000000 -#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x00000008 -#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x00000000 -#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x00000000 -#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x00000000 -#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x00000010 -#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x00000014 -#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT__CI__VI 0x0000000c -#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT__CI__VI 0x00000008 -#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT__CI__VI 0x00000010 -#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT__CI__VI 0x00000018 -#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT__CI__VI 0x00000008 -#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT__CI__VI 0x0000000b -#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT__CI__VI 0x0000000c -#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT__CI__VI 0x0000000d -#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT__CI__VI 0x00000008 -#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT__CI__VI 0x0000000f -#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT__CI__VI 0x0000000e -#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT__CI__VI 0x00000010 -#define PCIE_ERR_CNTL__ERR_GEN_INTERRUPT__SHIFT__SI 0x00000001 -#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x00000000 -#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT__CI__VI 0x00000002 -#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT__CI__VI 0x00000007 -#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT__CI__VI 0x00000005 -#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT__CI__VI 0x00000001 -#define PCIE_ERR_CNTL__SYM_UNLOCKED_EN__SHIFT__SI 0x00000002 -#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT__CI__VI 0x00000006 -#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT__CI__VI 0x00000004 -#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT__CI__VI 0x0000000c -#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT__CI__VI 0x00000008 -#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT__CI__VI 0x00000010 -#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT__CI__VI 0x00000018 -#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x00000000 -#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x00000008 -#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x00000000 -#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x00000008 -#define PCIE_FC_P__PD_CREDITS__SHIFT 0x00000000 -#define PCIE_FC_P__PH_CREDITS__SHIFT 0x00000008 -#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x00000000 -#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x00000000 -#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x00000000 -#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x00000000 -#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f -#define PCIE_I2C_DEBUG_BUS__DEBUG_BUS_BLK1__SHIFT 0x00000018 -#define PCIE_I2C_DEBUG_BUS__DEBUG_BUS_BLK2__SHIFT 0x00000019 -#define PCIE_I2C_DEBUG_BUS__DEBUG_EN__SHIFT 0x0000001a -#define PCIE_I2C_DEBUG_BUS__DEBUG_MULTIBLOCK_EN__SHIFT 0x0000001b -#define PCIE_I2C_DEBUG_BUS__DEBUG_MUX_BLK1__SHIFT 0x0000000c -#define PCIE_I2C_DEBUG_BUS__DEBUG_MUX_BLK2__SHIFT 0x00000012 -#define PCIE_I2C_DEBUG_BUS__DEBUG_RESERVE__SHIFT 0x0000001c -#define PCIE_I2C_DEBUG_BUS__DEBUG_SEL_BLK1__SHIFT 0x00000000 -#define PCIE_I2C_DEBUG_BUS__DEBUG_SEL_BLK2__SHIFT 0x00000006 -#define PCIE_I2C_REG_ADDR_EXPAND__BDI2C_CPLDATA_RTN_EXPAND__SHIFT__SI 0x00000011 -#define PCIE_I2C_REG_ADDR_EXPAND__BDREG_CPLDATA_RTN_EXPAND__SHIFT__SI 0x00000015 -#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x00000000 -#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x00000000 -#define PCIE_INDEX_2__PCIE_INDEX__SHIFT__CI__VI 0x00000000 -#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x00000000 -#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x00000000 -#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x00000002 -#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x00000007 -#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x00000004 -#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x00000001 -#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x00000006 -#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT__CI__VI 0x00000008 -#define PCIE_INT_CNTL__SLOT_POWER_CHG_INT_EN__SHIFT__SI 0x00000005 -#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x00000003 -#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x00000000 -#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x00000002 -#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x00000007 -#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x00000004 -#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x00000001 -#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x00000006 -#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT__CI__VI 0x00000008 -#define PCIE_INT_STATUS__SLOT_POWER_CHG_INT_STATUS__SHIFT__SI 0x00000005 -#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x00000003 -#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x00000004 -#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT__CI__VI 0x0000000f -#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT__CI__VI 0x0000000c -#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT__CI__VI 0x00000008 -#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT__CI__VI 0x00000000 -#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT__CI__VI 0x00000010 -#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x00000000 -#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x00000005 -#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x00000001 -#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0x0000000a -#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x00000006 -#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x00000009 -#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x00000008 -#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x00000003 -#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x00000004 -#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x00000007 -#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x00000002 -#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x00000018 -#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x00000000 -#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0x0000000c -#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x00000011 -#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x00000012 -#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x00000016 -#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x00000014 -#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x00000013 -#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x00000010 -#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x0000001a -#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0x0000000e -#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x0000001f -#define PCIE_LC_CNTL2__LC_ENABLE_RX_CR_EN_DEASSERTION__SHIFT__SI 0x0000001c -#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0x0000000c -#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0x0000000b -#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x0000001b -#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0x0000000a -#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x00000007 -#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x00000008 -#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT__CI__VI 0x0000001c -#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x00000019 -#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x00000015 -#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x00000006 -#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x0000001d -#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x00000000 -#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x00000017 -#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0x0000000d -#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x00000009 -#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT__CI__VI 0x00000012 -#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT__CI__VI 0x00000013 -#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT__CI__VI 0x00000006 -#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT__CI__VI 0x00000008 -#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT__CI__VI 0x00000010 -#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT__CI__VI 0x00000009 -#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x00000004 -#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT__CI__VI 0x00000017 -#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT__CI__VI 0x0000000c -#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT__CI__VI 0x0000000e -#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT__CI__VI 0x0000000a -#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT__CI__VI 0x00000015 -#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT__CI__VI 0x0000001e -#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT__CI__VI 0x00000018 -#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT__CI__VI 0x00000011 -#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT__CI__VI 0x0000001f -#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x00000003 -#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT__CI__VI 0x0000000b -#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x00000005 -#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT__CI__VI 0x00000016 -#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x00000001 -#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x00000000 -#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT__CI__VI 0x0000001a -#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT__CI__VI 0x00000010 -#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT__CI__VI 0x00000004 -#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT__CI__VI 0x00000008 -#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT__CI__VI 0x00000018 -#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT__CI__VI 0x00000006 -#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT__CI__VI 0x00000011 -#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT__CI__VI 0x00000012 -#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT__CI__VI 0x00000007 -#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT__CI__VI 0x00000017 -#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT__CI__VI 0x0000000e -#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT__CI__VI 0x00000005 -#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT__CI__VI 0x0000000d -#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT__CI__VI 0x00000000 -#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT__CI__VI 0x0000000f -#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT__CI__VI 0x00000016 -#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT__CI__VI 0x0000000b -#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT__CI__VI 0x0000000c -#define PCIE_LC_CNTL4__LC_USC_SET_EQ_VARIABLE__SHIFT__CI 0x0000000a -#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT__CI__VI 0x00000000 -#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT__CI__VI 0x00000006 -#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT__CI__VI 0x0000000c -#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT__CI__VI 0x00000012 -#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x00000004 -#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x00000018 -#define PCIE_LC_CNTL__LC_CM_HI_ENABLE_COUNT__SHIFT__SI 0x00000000 -#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x00000019 -#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x0000001b -#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x0000001c -#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x00000001 -#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x0000001e -#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x0000001d -#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x00000014 -#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x0000001f -#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x00000011 -#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x00000008 -#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x00000017 -#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0x0000000c -#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x00000012 -#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x00000010 -#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x00000003 -#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x00000002 -#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x00000015 -#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x00000016 -#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT__CI__VI 0x00000000 -#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT__CI__VI 0x00000007 -#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT__CI__VI 0x0000000d -#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT__CI__VI 0x00000001 -#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x00000000 -#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x00000010 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x00000010 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT__CI__VI 0x00000013 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT__CI__VI 0x00000012 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT__CI__VI 0x00000015 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT__CI__VI 0x00000017 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x00000011 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x00000004 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x00000000 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x00000007 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x00000008 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0x0000000a -#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x00000009 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0x0000000b -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0x0000000f -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0x0000000e -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT__CI__VI 0x00000014 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0x0000000d -#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0x0000000c -#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x00000018 -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x00000009 -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x00000010 -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x00000008 -#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x00000000 -#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT__CI__VI 0x00000011 -#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT__SI 0x00000016 -#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT__CI__VI 0x00000016 -#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT__SI 0x00000019 -#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT__CI__VI 0x0000001a -#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT__SI 0x0000001c -#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT__CI__VI 0x00000010 -#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT__SI 0x00000015 -#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT__CI__VI 0x0000000d -#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT__SI 0x0000000b -#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT__CI__VI 0x00000018 -#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT__SI 0x0000001b -#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT__CI__VI 0x0000001f -#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT__CI__VI 0x0000001e -#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT__CI__VI 0x0000000f -#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT__SI 0x00000014 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT__CI__VI 0x00000008 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT__SI 0x00000006 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT__CI__VI 0x00000006 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT__SI 0x00000004 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT__CI__VI 0x00000007 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT__SI 0x00000005 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT__CI__VI 0x00000005 -#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT__SI 0x00000003 -#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x00000000 -#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT__CI__VI 0x00000001 -#define PCIE_LC_SPEED_CNTL__LC_GO_TO_RECOVERY__SHIFT__SI 0x00000012 -#define PCIE_LC_SPEED_CNTL__LC_HW_VOLTAGE_IF_CONTROL__SHIFT__SI 0x0000000c -#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT__CI__VI 0x00000009 -#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT__SI 0x00000007 -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT__CI__VI 0x0000001c -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT__SI 0x0000001e -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT__CI__VI 0x0000001d -#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT__SI 0x0000001f -#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT__CI__VI 0x0000001b -#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT__SI 0x0000001d -#define PCIE_LC_SPEED_CNTL__LC_N_EIE_SEL__SHIFT__SI 0x00000013 -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT__CI__VI 0x00000012 -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT__SI 0x00000017 -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT__CI__VI 0x00000014 -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT__CI__VI 0x00000013 -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT__SI 0x00000018 -#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT__CI__VI 0x00000015 -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT__CI__VI 0x0000000a -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT__SI 0x00000008 -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT__CI__VI 0x0000000c -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT__SI 0x0000000a -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT__CI__VI 0x00000017 -#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT__SI 0x0000001a -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT__CI__VI 0x00000002 -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT__SI 0x00000001 -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT__CI__VI 0x00000003 -#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT__SI 0x00000002 -#define PCIE_LC_SPEED_CNTL__LC_VOLTAGE_TIMER_SEL__SHIFT__SI 0x0000000e -#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x00000000 -#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x00000008 -#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x00000010 -#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x00000018 -#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x00000000 -#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x00000008 -#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x00000010 -#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x00000018 -#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x00000000 -#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x00000008 -#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x00000010 -#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x00000018 -#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x00000000 -#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x00000008 -#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x00000010 -#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x00000018 -#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x00000010 -#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x00000018 -#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x00000000 -#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x00000008 -#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x00000000 -#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x00000008 -#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x00000010 -#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x00000018 -#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x00000000 -#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x00000008 -#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x00000010 -#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x00000018 -#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x00000000 -#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x00000008 -#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x00000010 -#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x00000018 -#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x00000000 -#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x00000008 -#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x00000010 -#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x00000018 -#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x00000000 -#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x00000008 -#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x00000010 -#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x00000018 -#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x00000000 -#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x00000008 -#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x00000010 -#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x00000018 -#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x00000000 -#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x00000008 -#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x00000010 -#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x00000018 -#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x00000005 -#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x00000002 -#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x00000000 -#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x00000001 -#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x00000000 -#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x00000010 -#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT__CI__VI 0x0000001c -#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x00000016 -#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x00000011 -#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x00000004 -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_1__SHIFT__SI 0x0000001b -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_2__SHIFT__CI 0x0000001d -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_2__SHIFT__SI 0x0000001c -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_3__SHIFT__CI 0x0000001e -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_3__SHIFT__SI 0x0000001d -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_4__SHIFT__CI 0x0000001f -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_4__SHIFT__SI 0x0000001e -#define PCIE_LC_TRAINING_CNTL__LC_DEBUG_5__SHIFT__SI 0x0000001f -#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT__CI__VI 0x0000000d -#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x00000018 -#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x00000019 -#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0x0000000b -#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x00000010 -#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT__CI__VI 0x00000013 -#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0x0000000c -#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x00000006 -#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x00000007 -#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT__CI__VI 0x00000014 -#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x00000005 -#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x00000008 -#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x0000001a -#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT__CI__VI 0x0000001b -#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x00000015 -#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x00000000 -#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x00000012 -#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT__CI__VI 0x00000001 -#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT__CI__VI 0x00000000 -#define PCIE_LINK_CNTL3__RESERVED__SHIFT__CI__VI 0x00000002 -#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT__CI__VI 0x00000000 -#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT__CI__VI 0x00000000 -#define PCIE_P90RX_PRBS10_CNTL__P90RX_PRBS10_CLR__SHIFT__SI 0x00000000 -#define PCIE_P90RX_PRBS10_CNTL__P90TX_PRBS10_EN__SHIFT__SI 0x00000010 -#define PCIE_P90_BRX_PRBS10_ER__P90_BRX_PRBS10_ER__SHIFT__SI 0x00000000 -#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT__CI__VI 0x00000000 -#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT__CI__VI 0x00000001 -#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT__CI__VI 0x00000000 -#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT__CI__VI 0x00000008 -#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT__CI__VI 0x00000001 -#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT__CI__VI 0x00000008 -#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT__CI__VI 0x00000001 -#define PCIE_PASID_CAP__PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT__CI 0x00000003 -#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT__CI__VI 0x00000002 -#define PCIE_PASID_CAP__PASID_TLP_PREFIX_SUPPORTED__SHIFT__CI 0x00000000 -#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT__CI__VI 0x00000000 -#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT__CI__VI 0x00000001 -#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT__CI__VI 0x00000002 -#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x00000004 -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014 -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x00000004 -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014 -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x00000008 -#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x00000010 -#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x00000018 -#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x00000000 -#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x00000008 -#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x00000000 -#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x00000000 -#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x00000000 -#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x00000000 -#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x00000000 -#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x00000000 -#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x00000000 -#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x00000000 -#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x00000000 -#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x00000000 -#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x00000000 -#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x00000000 -#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x00000000 -#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x00000000 -#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x00000000 -#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x00000002 -#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x00000001 -#define PCIE_PERF_LATENCY_CNTL__CFG_IO_REQ__SHIFT__SI 0x0000000b -#define PCIE_PERF_LATENCY_CNTL__CPL_MODE__SHIFT__SI 0x0000000e -#define PCIE_PERF_LATENCY_CNTL__MEM_REQ__SHIFT__SI 0x0000000a -#define PCIE_PERF_LATENCY_CNTL__NO_SNOOP__SHIFT__SI 0x00000009 -#define PCIE_PERF_LATENCY_CNTL__PORT_MODE__SHIFT__SI 0x00000007 -#define PCIE_PERF_LATENCY_CNTL__PORT_NUM__SHIFT__SI 0x00000004 -#define PCIE_PERF_LATENCY_CNTL__REQ_ID_MODE__SHIFT__SI 0x0000000c -#define PCIE_PERF_LATENCY_CNTL__SNOOP__SHIFT__SI 0x00000008 -#define PCIE_PERF_LATENCY_CNTL__TAG_MODE__SHIFT__SI 0x0000000d -#define PCIE_PERF_LATENCY_CNTL__TIMER_EN__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_CNTL__TIMER_RESET__SHIFT__SI 0x00000002 -#define PCIE_PERF_LATENCY_CNTL__TIMER_SHADOW_WR__SHIFT__SI 0x00000001 -#define PCIE_PERF_LATENCY_CNTL__TRAFFIC_CLASS__SHIFT__SI 0x00000010 -#define PCIE_PERF_LATENCY_COUNTER0__NUM_REQ__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_COUNTER1__NUM_EXCEED__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_MAX__PEAK__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_MAX__REQUESTER_ID__SHIFT__SI 0x00000010 -#define PCIE_PERF_LATENCY_REQ_ID__REQUESTER_ID__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_REQ_ID__REQUESTER_MASK__SHIFT__SI 0x00000010 -#define PCIE_PERF_LATENCY_TAG__TAG_MASK__SHIFT__SI 0x00000008 -#define PCIE_PERF_LATENCY_TAG__TAG__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_THRESHOLD__THRESHOLD__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_TIMER_HI__TIMER_HI__SHIFT__SI 0x00000000 -#define PCIE_PERF_LATENCY_TIMER_LO__TIMER_LO__SHIFT__SI 0x00000000 -#define PCIE_PERF_MAS_ACC_END_LO__PERF_MAS_ACC_END_LO__SHIFT__SI 0x00000002 -#define PCIE_PERF_MAS_ACC_START_END_HI__PERF_MAS_ACC_END_HI__SHIFT__SI 0x00000008 -#define PCIE_PERF_MAS_ACC_START_END_HI__PERF_MAS_ACC_START_HI__SHIFT__SI 0x00000000 -#define PCIE_PERF_MAS_ACC_START_LO__PERF_MAS_ACC_START_LO__SHIFT__SI 0x00000002 -#define PCIE_PERF_SLV_ACC_HI__PERF_SLV_ACC_HI__SHIFT__SI 0x00000000 -#define PCIE_PERF_SLV_ACC_LO__PERF_SLV_ACC_LO__SHIFT__SI 0x00000002 -#define PCIE_PI_RCVL0S_FTS_DET__PI_RCVL0S_FTS_DET_MAX__SHIFT__SI 0x00000010 -#define PCIE_PI_RCVL0S_FTS_DET__PI_RCVL0S_FTS_DET_MIN__SHIFT__SI 0x00000001 -#define PCIE_PI_RCVL0S_FTS_DET__PI_RCVL0S_FTS_DET_RST__SHIFT__SI 0x00000000 -#define PCIE_PORT_DATA__PCIE_DATA__SHIFT__SI 0x00000000 -#define PCIE_PORT_INDEX__PCIE_INDEX__SHIFT__SI 0x00000000 -#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x00000000 -#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x00000004 -#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0x0000000a -#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x00000008 -#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x00000000 -#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x00000018 -#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x00000000 -#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x00000001 -#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x00000000 -#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x00000010 -#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x00000000 -#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x00000000 -#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x00000000 -#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x00000000 -#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x00000000 -#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x00000010 -#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT__CI__VI 0x0000000e -#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x00000000 -#define PCIE_PRBS_MISC__PRBS_GEN2_SPEED__SHIFT__SI 0x0000000f -#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x00000001 -#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x00000000 -#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x00000010 -#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x00000000 -#define PCIE_PRBS_USER_PATTERN__PRBS_USER_DEFINE_PATTERN__SHIFT__SI 0x00000000 -#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT__CI__VI 0x00000000 -#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT__CI__VI 0x00000000 -#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT__CI__VI 0x00000000 -#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT__CI__VI 0x00000000 -#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT__CI__VI 0x00000008 -#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT__CI__VI 0x0000000d -#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT__CI__VI 0x0000000a -#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT__CI__VI 0x00000012 -#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT__CI__VI 0x0000000f -#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_0__SHIFT__SI 0x00000010 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_10__SHIFT__SI 0x0000001a -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_11__SHIFT__SI 0x0000001b -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_12__SHIFT__SI 0x0000001c -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_13__SHIFT__SI 0x0000001d -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_14__SHIFT__SI 0x0000001e -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_15__SHIFT__SI 0x0000001f -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_1__SHIFT__SI 0x00000011 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_2__SHIFT__SI 0x00000012 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_3__SHIFT__SI 0x00000013 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_4__SHIFT__SI 0x00000014 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_5__SHIFT__SI 0x00000015 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_6__SHIFT__SI 0x00000016 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_7__SHIFT__SI 0x00000017 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_8__SHIFT__SI 0x00000018 -#define PCIE_P_BUF_STATUS__P_DESKEW_BUF_OVERFLOW_9__SHIFT__SI 0x00000019 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_0__SHIFT__SI 0x00000000 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_10__SHIFT__SI 0x0000000a -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_11__SHIFT__SI 0x0000000b -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_12__SHIFT__SI 0x0000000c -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_13__SHIFT__SI 0x0000000d -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_14__SHIFT__SI 0x0000000e -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_15__SHIFT__SI 0x0000000f -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_1__SHIFT__SI 0x00000001 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_2__SHIFT__SI 0x00000002 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_3__SHIFT__SI 0x00000003 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_4__SHIFT__SI 0x00000004 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_5__SHIFT__SI 0x00000005 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_6__SHIFT__SI 0x00000006 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_7__SHIFT__SI 0x00000007 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_8__SHIFT__SI 0x00000008 -#define PCIE_P_BUF_STATUS__P_ELASTIC_BUF_OVERFLOW_9__SHIFT__SI 0x00000009 -#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT__CI__VI 0x00000000 -#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT__CI__VI 0x00000010 -#define PCIE_P_CNTL__B_PG2RX_CR_EN_MODE__SHIFT__SI 0x0000001e -#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT__CI__VI 0x00000010 -#define PCIE_P_CNTL__LC_RXP_DONT_ALIGN_ON_TSx__SHIFT__SI 0x0000001d -#define PCIE_P_CNTL__PI_RXEN_GATER__SHIFT__SI 0x00000018 -#define PCIE_P_CNTL__PI_SYMALIGN_DIS_ELIDLE__SHIFT__SI 0x00000007 -#define PCIE_P_CNTL__P_ALLOW_PRX_FRONTEND_SHUTOFF__SHIFT__SI 0x0000000c -#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0x0000000d -#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT__CI__VI 0x0000000c -#define PCIE_P_CNTL__P_EBUF_SYNC_MODE__SHIFT__SI 0x0000000a -#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT__CI__VI 0x00000003 -#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0x0000000e -#define PCIE_P_CNTL__P_ENABLE_PLL_LOCKING_IN_QUICKSIM__SHIFT__SI 0x00000002 -#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT__CI__VI 0x00000004 -#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT__CI__VI 0x00000006 -#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT__CI__VI 0x00000007 -#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT__CI__VI 0x00000005 -#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT__CI__VI 0x00000008 -#define PCIE_P_CNTL__P_LDSK_MASK_RCVR_ELEC_IDLE__SHIFT__SI 0x0000000b -#define PCIE_P_CNTL__P_MASK_RCVR_EIDLE_EN__SHIFT__SI 0x00000008 -#define PCIE_P_CNTL__P_PLL_BUF_PDNB__SHIFT__SI 0x00000004 -#define PCIE_P_CNTL__P_PLL_PDNB__SHIFT__SI 0x00000009 -#define PCIE_P_CNTL__P_PLL_PWRDN_IN_L1L23__SHIFT__SI 0x00000003 -#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x00000000 -#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT__CI__VI 0x00000002 -#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x00000001 -#define PCIE_P_CNTL__P_TXCLK_RCV_PWRDN__SHIFT__SI 0x00000006 -#define PCIE_P_CNTL__P_TXCLK_SND_PWRDN__SHIFT__SI 0x00000005 -#define PCIE_P_CNTL__RXP_NAK_FIX_IN_MODE1_EN__SHIFT__SI 0x0000001f -#define PCIE_P_CNTL__RXP_REALIGN_ON_EACH_TSX_OR_SKP__SHIFT__SI 0x0000001c -#define PCIE_P_CNTL__RXP_XBAR_MUX0__SHIFT__SI 0x00000010 -#define PCIE_P_CNTL__RXP_XBAR_MUX1__SHIFT__SI 0x00000012 -#define PCIE_P_CNTL__RXP_XBAR_MUX2__SHIFT__SI 0x00000014 -#define PCIE_P_CNTL__RXP_XBAR_MUX3__SHIFT__SI 0x00000016 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_0__SHIFT__SI 0x00000000 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_10__SHIFT__SI 0x0000000a -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_11__SHIFT__SI 0x0000000b -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_12__SHIFT__SI 0x0000000c -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_13__SHIFT__SI 0x0000000d -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_14__SHIFT__SI 0x0000000e -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_15__SHIFT__SI 0x0000000f -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_1__SHIFT__SI 0x00000001 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_2__SHIFT__SI 0x00000002 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_3__SHIFT__SI 0x00000003 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_4__SHIFT__SI 0x00000004 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_5__SHIFT__SI 0x00000005 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_6__SHIFT__SI 0x00000006 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_7__SHIFT__SI 0x00000007 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_8__SHIFT__SI 0x00000008 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_9__SHIFT__SI 0x00000009 -#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT__CI__VI 0x00000000 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_0__SHIFT__SI 0x00000010 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_10__SHIFT__SI 0x0000001a -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_11__SHIFT__SI 0x0000001b -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_12__SHIFT__SI 0x0000001c -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_13__SHIFT__SI 0x0000001d -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_14__SHIFT__SI 0x0000001e -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_15__SHIFT__SI 0x0000001f -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_1__SHIFT__SI 0x00000011 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_2__SHIFT__SI 0x00000012 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_3__SHIFT__SI 0x00000013 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_4__SHIFT__SI 0x00000014 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_5__SHIFT__SI 0x00000015 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_6__SHIFT__SI 0x00000016 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_7__SHIFT__SI 0x00000017 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_8__SHIFT__SI 0x00000018 -#define PCIE_P_DECODER_STATUS__P_DISPARITY_ERR_9__SHIFT__SI 0x00000019 -#define PCIE_P_DECODE_ERR_CNTL__CODE_ERR_CNT_RESET__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNTL__DISPARITY_ERR_CNT_RESET__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_0__CODE_ERR_CNT_0__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_0__DISPARITY_ERR_CNT_0__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_10__CODE_ERR_CNT_10__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_10__DISPARITY_ERR_CNT_10__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_11__CODE_ERR_CNT_11__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_11__DISPARITY_ERR_CNT_11__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_12__CODE_ERR_CNT_12__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_12__DISPARITY_ERR_CNT_12__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_13__CODE_ERR_CNT_13__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_13__DISPARITY_ERR_CNT_13__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_14__CODE_ERR_CNT_14__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_14__DISPARITY_ERR_CNT_14__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_15__CODE_ERR_CNT_15__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_15__DISPARITY_ERR_CNT_15__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_1__CODE_ERR_CNT_1__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_1__DISPARITY_ERR_CNT_1__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_2__CODE_ERR_CNT_2__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_2__DISPARITY_ERR_CNT_2__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_3__CODE_ERR_CNT_3__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_3__DISPARITY_ERR_CNT_3__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_4__CODE_ERR_CNT_4__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_4__DISPARITY_ERR_CNT_4__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_5__CODE_ERR_CNT_5__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_5__DISPARITY_ERR_CNT_5__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_6__CODE_ERR_CNT_6__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_6__DISPARITY_ERR_CNT_6__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_7__CODE_ERR_CNT_7__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_7__DISPARITY_ERR_CNT_7__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_8__CODE_ERR_CNT_8__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_8__DISPARITY_ERR_CNT_8__SHIFT__SI 0x00000010 -#define PCIE_P_DECODE_ERR_CNT_9__CODE_ERR_CNT_9__SHIFT__SI 0x00000000 -#define PCIE_P_DECODE_ERR_CNT_9__DISPARITY_ERR_CNT_9__SHIFT__SI 0x00000010 -#define PCIE_P_IMP_CNTL_STRENGTH__PI_HALT_IMP_CAL__SHIFT__SI 0x0000001c -#define PCIE_P_IMP_CNTL_STRENGTH__P_PAD_MANUAL_OVERRIDE__SHIFT__SI 0x0000001f -#define PCIE_P_IMP_CNTL_STRENGTH__P_RX_IMP_CNTL_READ_BACK__SHIFT__SI 0x00000008 -#define PCIE_P_IMP_CNTL_STRENGTH__P_RX_IMP_CNTL__SHIFT__SI 0x00000018 -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_IMP_CNTL_READ_BACK__SHIFT__SI 0x00000004 -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_IMP_CNTL__SHIFT__SI 0x00000014 -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_STR_CNTL_READ_BACK__SHIFT__SI 0x00000000 -#define PCIE_P_IMP_CNTL_STRENGTH__P_TX_STR_CNTL__SHIFT__SI 0x00000010 -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_DEC_THRESHOLD__SHIFT__SI 0x00000018 -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_INC_THRESHOLD__SHIFT__SI 0x00000010 -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_SAMPLE_DELAY__SHIFT__SI 0x00000008 -#define PCIE_P_IMP_CNTL_UPDATE__P_IMP_PAD_UPDATE_RATE__SHIFT__SI 0x00000000 -#define PCIE_P_MISC_DEBUG_STATUS__P_HW_DEBUG__SHIFT__SI 0x00000004 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_0__SHIFT__SI 0x00000010 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_10__SHIFT__SI 0x0000001a -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_11__SHIFT__SI 0x0000001b -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_12__SHIFT__SI 0x0000001c -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_13__SHIFT__SI 0x0000001d -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_14__SHIFT__SI 0x0000001e -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_15__SHIFT__SI 0x0000001f -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_1__SHIFT__SI 0x00000011 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_2__SHIFT__SI 0x00000012 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_3__SHIFT__SI 0x00000013 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_4__SHIFT__SI 0x00000014 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_5__SHIFT__SI 0x00000015 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_6__SHIFT__SI 0x00000016 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_7__SHIFT__SI 0x00000017 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_8__SHIFT__SI 0x00000018 -#define PCIE_P_MISC_DEBUG_STATUS__P_INSERT_ERROR_9__SHIFT__SI 0x00000019 -#define PCIE_P_MISC_DEBUG_STATUS__P_LANE_REVERSAL__SHIFT__SI 0x00000002 -#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT__CI__VI 0x00000000 -#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT__CI__VI 0x00000010 -#define PCIE_P_PAD_FORCE_DIS__B_PBG_PDNB_FDIS__SHIFT__SI 0x00000019 -#define PCIE_P_PAD_FORCE_DIS__B_PIMP_RX_PDNB_FDIS__SHIFT__SI 0x0000001b -#define PCIE_P_PAD_FORCE_DIS__B_PIMP_TX_PDNB_FDIS__SHIFT__SI 0x0000001a -#define PCIE_P_PAD_FORCE_DIS__B_PI_DREN_FDIS__SHIFT__SI 0x00000018 -#define PCIE_P_PAD_FORCE_DIS__B_PPLL_BUF_PDNB_FDIS__SHIFT__SI 0x00000014 -#define PCIE_P_PAD_FORCE_DIS__B_PPLL_PDNB_FDIS__SHIFT__SI 0x00000010 -#define PCIE_P_PAD_FORCE_DIS__B_PRX_PDNB_FDIS__SHIFT__SI 0x00000008 -#define PCIE_P_PAD_FORCE_DIS__B_PTX_PDNB_FDIS__SHIFT__SI 0x00000000 -#define PCIE_P_PAD_FORCE_EN__B_PBG_PDNB_FEN__SHIFT__SI 0x00000019 -#define PCIE_P_PAD_FORCE_EN__B_PIMP_RX_PDNB_FEN__SHIFT__SI 0x0000001b -#define PCIE_P_PAD_FORCE_EN__B_PIMP_TX_PDNB_FEN__SHIFT__SI 0x0000001a -#define PCIE_P_PAD_FORCE_EN__B_PI_DREN_FEN__SHIFT__SI 0x00000018 -#define PCIE_P_PAD_FORCE_EN__B_PPLL_BUF_PDNB_FEN__SHIFT__SI 0x00000014 -#define PCIE_P_PAD_FORCE_EN__B_PPLL_PDNB_FEN__SHIFT__SI 0x00000010 -#define PCIE_P_PAD_FORCE_EN__B_PRX_PDNB_FEN__SHIFT__SI 0x00000008 -#define PCIE_P_PAD_FORCE_EN__B_PTX_PDNB_FEN__SHIFT__SI 0x00000000 -#define PCIE_P_PAD_MISC_CNTL__P_LINK_RETRAIN_ON_ERR_EN__SHIFT__SI 0x00000003 -#define PCIE_P_PAD_MISC_CNTL__P_PAD_IMP_DUMMYOUT__SHIFT__SI 0x00000001 -#define PCIE_P_PAD_MISC_CNTL__P_PAD_IMP_TESTOUT__SHIFT__SI 0x00000002 -#define PCIE_P_PAD_MISC_CNTL__P_PAD_I_DUMMYOUT__SHIFT__SI 0x00000000 -#define PCIE_P_PAD_MISC_CNTL__P_PLLCAL_INC_LOWER_PHASE__SHIFT__SI 0x00000004 -#define PCIE_P_PLL_CNTL__P_CALREF__SHIFT__SI 0x00000002 -#define PCIE_P_PLL_CNTL__P_VCOREF__SHIFT__SI 0x00000000 -#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x00000001 -#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x00000000 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_0__SHIFT__SI 0x00000010 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_10__SHIFT__SI 0x0000001a -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_11__SHIFT__SI 0x0000001b -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_12__SHIFT__SI 0x0000001c -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_13__SHIFT__SI 0x0000001d -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_14__SHIFT__SI 0x0000001e -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_15__SHIFT__SI 0x0000001f -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_1__SHIFT__SI 0x00000011 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_2__SHIFT__SI 0x00000012 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_3__SHIFT__SI 0x00000013 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_4__SHIFT__SI 0x00000014 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_5__SHIFT__SI 0x00000015 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_6__SHIFT__SI 0x00000016 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_7__SHIFT__SI 0x00000017 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_8__SHIFT__SI 0x00000018 -#define PCIE_P_RCVR_DEBUG_CNTL__P_CORRUPT_SYMBOL_9__SHIFT__SI 0x00000019 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_0__SHIFT__SI 0x00000000 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_10__SHIFT__SI 0x0000000a -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_11__SHIFT__SI 0x0000000b -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_12__SHIFT__SI 0x0000000c -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_13__SHIFT__SI 0x0000000d -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_14__SHIFT__SI 0x0000000e -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_15__SHIFT__SI 0x0000000f -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_1__SHIFT__SI 0x00000001 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_2__SHIFT__SI 0x00000002 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_3__SHIFT__SI 0x00000003 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_4__SHIFT__SI 0x00000004 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_5__SHIFT__SI 0x00000005 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_6__SHIFT__SI 0x00000006 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_7__SHIFT__SI 0x00000007 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_8__SHIFT__SI 0x00000008 -#define PCIE_P_RCVR_DEBUG_CNTL__P_FORCE_SYMBOL_UNLOCK_9__SHIFT__SI 0x00000009 -#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT__CI__VI 0x00000008 -#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT__CI__VI 0x00000000 -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_DCB_ERR_RETRAIN__SHIFT__SI 0x00000019 -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_THRESH_CLEARSKP__SHIFT__SI 0x00000018 -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_THRESH_CODE_ERR__SHIFT__SI 0x00000008 -#define PCIE_P_RXP_ERR_RETRAIN_CTL__P_RXP_THRESH_DISP_ERR__SHIFT__SI 0x00000000 -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_DEC_THRESHOLD__SHIFT__SI 0x00000018 -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_INC_THRESHOLD__SHIFT__SI 0x00000010 -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_SAMPLE_DELAY__SHIFT__SI 0x00000008 -#define PCIE_P_STR_CNTL_UPDATE__P_STR_PAD_UPDATE_RATE__SHIFT__SI 0x00000000 -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_BYPASS_MODE__SHIFT__SI 0x00000014 -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_ELECT_IDLE_DET_EN__SHIFT__SI 0x00000000 -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_ENABLE_IN_GEN1__SHIFT__SI 0x00000015 -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_M_GOOD__SHIFT__SI 0x00000002 -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_N_BAD__SHIFT__SI 0x0000000a -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_PAD_MODE__SHIFT__SI 0x00000012 -#define PCIE_P_SYMSYNC_CTL__P_SYMSYNC_SYNC_MODE__SHIFT__SI 0x00000001 -#define PCIE_REG_R_RTR_TIMEOUT_CNTL__REG_R_RTR_TIMEOUT_RST__SHIFT__SI 0x00000000 -#define PCIE_REG_R_RTR_TIMEOUT_CNTL__REG_R_RTR_TIMEOUT_VALUE__SHIFT__SI 0x00000004 -#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x00000000 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_C_RTR_ERROR__SHIFT__SI 0x00000002 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_C_RTR_STATUS__SHIFT__SI 0x00000012 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_R_RTR_ERROR__SHIFT__SI 0x00000001 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_MST_R_RTR_STATUS__SHIFT__SI 0x00000011 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_SLV_R_RTR_ERROR__SHIFT__SI 0x00000000 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__CI_SLV_R_RTR_STATUS__SHIFT__SI 0x00000010 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__REG_R_RTR_ERROR__SHIFT__SI 0x00000003 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__REG_R_RTR_STATUS__SHIFT__SI 0x00000013 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__TX_SLVCPL_TIMEOUT_ERROR__SHIFT__SI 0x00000004 -#define PCIE_RTR_CPL_TIMEOUT_STATUS__TX_SLVCPL_TIMEOUT_STATUS__SHIFT__SI 0x00000014 -#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT__CI__VI 0x00000003 -#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT__CI__VI 0x00000000 -#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT__CI__VI 0x00000005 -#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT__CI__VI 0x00000004 -#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT__CI__VI 0x00000001 -#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT__CI__VI 0x00000002 -#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT__CI__VI 0x00000004 -#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT__CI__VI 0x00000003 -#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT__CI__VI 0x00000002 -#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT__CI__VI 0x00000000 -#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT__CI__VI 0x00000001 -#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0x0000000f -#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0x0000000e -#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT__CI__VI 0x0000000c -#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x00000001 -#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x00000004 -#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0x0000000a -#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT__CI__VI 0x00000017 -#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x00000005 -#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x00000003 -#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x00000006 -#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT__CI__VI 0x00000018 -#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x00000000 -#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0x0000000b -#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x00000007 -#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT__CI__VI 0x00000016 -#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x00000008 -#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x00000002 -#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT__CI__VI 0x00000019 -#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT__CI__VI 0x00000015 -#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x00000009 -#define PCIE_RX_CNTL__RX_IGNORE_VEND0_UR__SHIFT__SI 0x0000000c -#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0x0000000d -#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x00000014 -#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x00000013 -#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x00000010 -#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x00000000 -#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x00000010 -#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x00000000 -#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x00000010 -#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x00000000 -#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x00000010 -#define PCIE_RX_CREDITS_RECEIVED_CPL__RX_CREDITS_RECEIVED_CPLD__SHIFT__SI 0x00000000 -#define PCIE_RX_CREDITS_RECEIVED_CPL__RX_CREDITS_RECEIVED_CPLH__SHIFT__SI 0x00000010 -#define PCIE_RX_CREDITS_RECEIVED_NP__RX_CREDITS_RECEIVED_NPD__SHIFT__SI 0x00000000 -#define PCIE_RX_CREDITS_RECEIVED_NP__RX_CREDITS_RECEIVED_NPH__SHIFT__SI 0x00000010 -#define PCIE_RX_CREDITS_RECEIVED_P__RX_CREDITS_RECEIVED_PD__SHIFT__SI 0x00000000 -#define PCIE_RX_CREDITS_RECEIVED_P__RX_CREDITS_RECEIVED_PH__SHIFT__SI 0x00000010 -#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT__CI__VI 0x00000000 -#define PCIE_RX_LASTACK_SEQNUM__RX_LASTACK_SEQNUM__SHIFT__SI 0x00000000 -#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x00000000 -#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x00000000 -#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x00000000 -#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x00000000 -#define PCIE_RX_NUM_NACK_GENERATED__RX_NUM_NACK_GENERATED__SHIFT__SI 0x00000000 -#define PCIE_RX_NUM_NACK__RX_NUM_NACK__SHIFT__SI 0x00000000 -#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT__CI__VI 0x00000000 -#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT__CI__VI 0x00000000 -#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x00000000 -#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x00000018 -#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x00000000 -#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT__CI__VI 0x00000010 -#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000014 -#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT__CI__VI 0x00000006 -#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT__CI__VI 0x00000005 -#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT__CI__VI 0x0000000a -#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT__CI__VI 0x00000007 -#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT__CI__VI 0x00000009 -#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT__CI__VI 0x00000004 -#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT__CI__VI 0x00000000 -#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT__CI__VI 0x00000001 -#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT__CI 0x0000000d -#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT__CI__VI 0x00000002 -#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT__CI__VI 0x0000000b -#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT__CI__VI 0x0000000c -#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT__CI__VI 0x00000008 -#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT__CI__VI 0x00000003 -#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT__CI__VI 0x00000006 -#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT__CI__VI 0x00000005 -#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT__CI__VI 0x0000000a -#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT__CI__VI 0x00000007 -#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT__CI__VI 0x00000009 -#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT__CI__VI 0x00000004 -#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT__CI 0x00000000 -#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT__CI__VI 0x00000001 -#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT__CI__VI 0x00000002 -#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT__CI__VI 0x0000000b -#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT__CI__VI 0x0000000c -#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT__CI__VI 0x00000008 -#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT__CI__VI 0x00000003 -#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT__CI__VI 0x00000006 -#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT__CI__VI 0x00000005 -#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT__CI__VI 0x0000000a -#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT__CI__VI 0x00000007 -#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT__CI__VI 0x00000009 -#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT__CI__VI 0x00000004 -#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT__CI 0x00000000 -#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT__CI__VI 0x00000001 -#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT__CI__VI 0x00000002 -#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT__CI__VI 0x0000000b -#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT__CI__VI 0x0000000c -#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT__CI__VI 0x00000008 -#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT__CI__VI 0x00000003 -#define PCIE_STRAP_F3__RESERVED__SHIFT__CI__VI 0x00000000 -#define PCIE_STRAP_F4__RESERVED__SHIFT__CI__VI 0x00000000 -#define PCIE_STRAP_F5__RESERVED__SHIFT__CI__VI 0x00000000 -#define PCIE_STRAP_F6__RESERVED__SHIFT__CI__VI 0x00000000 -#define PCIE_STRAP_F7__RESERVED__SHIFT__CI__VI 0x00000000 -#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x00000007 -#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x00000000 -#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x00000001 -#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT__CI__VI 0x00000003 -#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x00000002 -#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT__CI__VI 0x00000004 -#define PCIE_STRAP_MISC__RESERVED1__SHIFT__SI 0x00000004 -#define PCIE_STRAP_MISC__RESERVED2__SHIFT__SI 0x0000001b -#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT 0x00000006 -#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x00000018 -#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x00000019 -#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x0000001a -#define PCIE_STRAP_MISC__STRAP_F0_AER_EN__SHIFT__SI 0x00000008 -#define PCIE_STRAP_MISC__STRAP_F0_EN__SHIFT__SI 0x00000009 -#define PCIE_STRAP_MISC__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x0000000c -#define PCIE_STRAP_MISC__STRAP_F0_MSI_EN__SHIFT__SI 0x0000000a -#define PCIE_STRAP_MISC__STRAP_F0_VC_EN__SHIFT__SI 0x0000000b -#define PCIE_STRAP_MISC__STRAP_F1_AER_EN__SHIFT__SI 0x0000000d -#define PCIE_STRAP_MISC__STRAP_F1_EN__SHIFT__SI 0x0000000e -#define PCIE_STRAP_MISC__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x00000011 -#define PCIE_STRAP_MISC__STRAP_F1_MSI_EN__SHIFT__SI 0x0000000f -#define PCIE_STRAP_MISC__STRAP_F1_VC_EN__SHIFT__SI 0x00000010 -#define PCIE_STRAP_MISC__STRAP_F2_AER_EN__SHIFT__SI 0x00000012 -#define PCIE_STRAP_MISC__STRAP_F2_EN__SHIFT__SI 0x00000013 -#define PCIE_STRAP_MISC__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT__SI 0x00000016 -#define PCIE_STRAP_MISC__STRAP_F2_MSI_EN__SHIFT__SI 0x00000014 -#define PCIE_STRAP_MISC__STRAP_F2_VC_EN__SHIFT__SI 0x00000015 -#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT__CI__VI 0x0000001e -#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT__SI__CI 0x00000000 -#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT__CI__VI 0x00000008 -#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x0000001d -#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT__CI__VI 0x0000000d -#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT__CI__VI 0x0000000f -#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT__CI__VI 0x0000000e -#define PCIE_STRAP_MISC__STRAP_PASID_TLP_PREFIX_SUPPORTED__SHIFT__CI 0x00000007 -#define PCIE_STRAP_MISC__STRAP_PHY_RCVRDET_3NF__SHIFT__SI 0x00000007 -#define PCIE_STRAP_MISC__STRAP_PWRSAVE_PEIDL_GOOD__SHIFT__SI 0x00000005 -#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x0000001c -#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT__CI__VI 0x00000004 -#define PCIE_STRAP_PI__STRAP_BACKGROUND_IMP_CAL__SHIFT__SI 0x00000001 -#define PCIE_STRAP_PI__STRAP_BYPASS_LDSK_TO_LC__SHIFT__SI 0x0000001f -#define PCIE_STRAP_PI__STRAP_ELAST_WATERMARK__SHIFT__SI 0x0000000b -#define PCIE_STRAP_PI__STRAP_EXTDEV_EN__SHIFT__SI 0x0000001a -#define PCIE_STRAP_PI__STRAP_IMP_MANUAL_OVERRIDE__SHIFT__SI 0x00000002 -#define PCIE_STRAP_PI__STRAP_INC_PLLCAL_PHASE__SHIFT__SI 0x00000015 -#define PCIE_STRAP_PI__STRAP_INIT_REAL_PES_MODE__SHIFT__SI 0x00000014 -#define PCIE_STRAP_PI__STRAP_LDSK_X1_BYPASS__SHIFT__SI 0x0000000e -#define PCIE_STRAP_PI__STRAP_PAD_RX_MANUAL_IMPEDANCE__SHIFT__SI 0x00000003 -#define PCIE_STRAP_PI__STRAP_PAD_TX_MANUAL_IMPEDANCE__SHIFT__SI 0x00000007 -#define PCIE_STRAP_PI__STRAP_PHY_RX_INCAL_FORCE__SHIFT__SI 0x00000019 -#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x00000000 -#define PCIE_STRAP_PI__STRAP_RXP_LAT_REDUCTION_DIS__SHIFT__SI 0x0000000d -#define PCIE_STRAP_PI__STRAP_SHUTOFF_PORTS_FOR_SYM_ERR__SHIFT__SI 0x0000001e -#define PCIE_STRAP_PI__STRAP_STAGGER_CNTL__SHIFT__SI 0x0000000f -#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x0000001d -#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x0000001c -#define PCIE_STRAP_PI__STRAP_TX_PDNB_MODE__SHIFT__SI 0x00000011 -#define PCIE_STRAP_PI__STRAP_VCO_MODE__SHIFT__SI 0x00000012 -#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT__CI__VI 0x00000000 -#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT__CI__VI 0x00000000 -#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT__CI__VI 0x00000000 -#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT__CI__VI 0x00000000 -#define PCIE_TRUSTED_BASE_CLASS__BASE_CLASS__SHIFT__SI 0x00000000 -#define PCIE_TRUSTED_CAC_CAP_LIST__CAP_ID__SHIFT__SI 0x00000000 -#define PCIE_TRUSTED_CAC_CAP_LIST__CAP_VER__SHIFT__SI 0x00000010 -#define PCIE_TRUSTED_CAC_CAP_LIST__NEXT_PTR__SHIFT__SI 0x00000014 -#define PCIE_TRUSTED_CAC_DEVICE_CORRELATION__DEVICE_CORRELATION__SHIFT__SI 0x00000000 -#define PCIE_TRUSTED_FIRST_CAP_OFFSET__FIRST_CAP_OFFSET__SHIFT__SI 0x00000000 -#define PCIE_TRUSTED_PROG_INTERFACE__PROG_INTERFACE__SHIFT__SI 0x00000000 -#define PCIE_TRUSTED_SUB_CLASS__SUB_CLASS__SHIFT__SI 0x00000000 -#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT__CI__VI 0x0000000c -#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT__SI 0x00000008 -#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x00000000 -#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x00000016 -#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x00000014 -#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT__CI__VI 0x00000018 -#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT__CI__VI 0x00000019 -#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT__CI__VI 0x0000001a -#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT__CI__VI 0x00000017 -#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_SEL__SHIFT__SI 0x00000018 -#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT__SHIFT__SI 0x0000001a -#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT__CI__VI 0x0000000f -#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT__SI 0x00000013 -#define PCIE_TX_CNTL__TX_GAP_BTW_PKTS__SHIFT__SI 0x00000010 -#define PCIE_TX_CNTL__TX_GENERATE_CRC_ERR__SHIFT__SI 0x0000000f -#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x00000015 -#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0x0000000e -#define PCIE_TX_CNTL__TX_REPLAY_NUM_COUNT__SHIFT__SI 0x00000000 -#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0x0000000c -#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0x0000000a -#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x00000000 -#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x00000010 -#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x00000000 -#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x00000010 -#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x00000000 -#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x00000010 -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT__CI__VI 0x00000008 -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT__CI__VI 0x00000018 -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT__CI__VI 0x00000004 -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT__CI__VI 0x00000014 -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT__CI__VI 0x00000000 -#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT__CI__VI 0x00000010 -#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x00000000 -#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x00000010 -#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x00000000 -#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x00000010 -#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x00000000 -#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x00000010 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x00000014 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x00000015 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x00000012 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x00000013 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x00000010 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x00000011 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x00000004 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x00000005 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x00000002 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x00000003 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x00000000 -#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x00000001 -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT__CI__VI 0x00000004 -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT__CI__VI 0x00000002 -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT__CI__VI 0x00000000 -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT__CI__VI 0x00000008 -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT__CI__VI 0x00000006 -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT__CI__VI 0x0000000c -#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT__CI__VI 0x0000000a -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT__CI__VI 0x00000004 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT__CI__VI 0x00000002 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT__CI__VI 0x00000000 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT__CI__VI 0x00000008 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT__CI__VI 0x00000006 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT__CI__VI 0x0000000c -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT__CI__VI 0x0000000a -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT__CI__VI 0x00000014 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT__CI__VI 0x00000012 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT__CI__VI 0x00000010 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT__CI__VI 0x00000018 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT__CI__VI 0x00000016 -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT__CI__VI 0x0000001c -#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT__CI__VI 0x0000001a -#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x00000000 -#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x00000000 -#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x00000000 -#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x00000000 -#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x00000000 -#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0x0000000f -#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x00000010 -#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x00000008 -#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x00000003 -#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x00000000 -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_CPL_ACK_EN__SHIFT__SI 0x00000017 -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_CPL_ACK__SHIFT__SI 0x00000010 -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_NP_ACK_EN__SHIFT__SI 0x0000000f -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_NP_ACK__SHIFT__SI 0x00000008 -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_NP_VC1_ACK_EN__SHIFT__SI 0x0000000e -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x0000001f -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x0000001e -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x00000018 -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_P_ACK_EN__SHIFT__SI 0x00000007 -#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_P_ACK__SHIFT__SI 0x00000000 -#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x00000010 -#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x00000000 -#define PCIE_TX_SLVCPL_TIMEOUT_CNTL__TX_SLVCPL_TIMEOUT_RST__SHIFT__SI 0x00000000 -#define PCIE_TX_SLVCPL_TIMEOUT_CNTL__TX_SLVCPL_TIMEOUT_VALUE__SHIFT__SI 0x00000004 -#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x00000000 -#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x00000015 -#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT__CI__VI 0x00000018 -#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0x0000000f -#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0x0000000e -#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x00000004 -#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x00000013 -#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0x0000000d -#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x00000012 -#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT__CI__VI 0x00000017 -#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0x0000000c -#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x00000011 -#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x00000005 -#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT__CI__VI 0x00000019 -#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT__CI__VI 0x00000016 -#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x00000010 -#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x00000014 -#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x00000015 -#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT__CI__VI 0x00000018 -#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0x0000000f -#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0x0000000e -#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x00000004 -#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x00000013 -#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0x0000000d -#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x00000012 -#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT__CI__VI 0x00000017 -#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0x0000000c -#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x00000011 -#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x00000005 -#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT__CI__VI 0x00000019 -#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT__CI__VI 0x00000016 -#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x00000010 -#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x00000014 -#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x00000015 -#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT__CI__VI 0x00000018 -#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0x0000000f -#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0x0000000e -#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x00000004 -#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x00000013 -#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0x0000000d -#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x00000012 -#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT__CI__VI 0x00000017 -#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0x0000000c -#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x00000011 -#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x00000005 -#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT__CI__VI 0x00000019 -#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT__CI__VI 0x00000016 -#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x00000010 -#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x00000014 -#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x00000010 -#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x00000000 -#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x00000018 -#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0x0000000f -#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x00000010 -#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x00000011 -#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x00000000 -#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x00000001 -#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x0000001f -#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x00000018 -#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x00000000 -#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x00000001 -#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x00000010 -#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x00000000 -#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x00000018 -#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0x0000000f -#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x00000010 -#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x00000011 -#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x00000000 -#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x00000001 -#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x0000001f -#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x00000018 -#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x00000000 -#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x00000001 -#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x00000000 -#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x00000010 -#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x00000014 -#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x00000000 -#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x00000000 -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x00000000 -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x00000010 -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x00000014 -#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x00000000 -#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x00000014 -#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x00000010 -#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x00000003 -#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x00000000 -#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x00000002 -#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x00000001 -#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x00000006 -#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x00000004 -#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x00000005 -#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT__CI__VI 0x00000000 -#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT__CI__VI 0x0000001f -#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT__CI__VI 0x00000000 -#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT__CI__VI 0x00000000 -#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT__CI__VI 0x0000001f -#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT__CI__VI 0x00000000 -#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT__CI__VI 0x00000000 -#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT__CI__VI 0x0000001f -#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT__CI__VI 0x00000000 -#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT__CI__VI 0x00000000 -#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT__CI__VI 0x0000001f -#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT__CI__VI 0x00000000 -#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x00000010 -#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x00000000 -#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x00000010 -#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x00000000 -#define PERF_MON_CTRL_1__CHAN_1_MODE__SHIFT__CI__VI 0x00000018 -#define PERF_MON_CTRL_1__CHAN_1_PERIODIC__SHIFT__CI__VI 0x00000014 -#define PERF_MON_CTRL_1__CHAN_1_SEL__SHIFT__CI__VI 0x00000000 -#define PERF_MON_CTRL_1__CHAN_2_MODE__SHIFT__CI__VI 0x0000001b -#define PERF_MON_CTRL_1__CHAN_2_PERIODIC__SHIFT__CI__VI 0x00000015 -#define PERF_MON_CTRL_1__CHAN_2_SEL__SHIFT__CI__VI 0x00000005 -#define PERF_MON_CTRL_1__CHAN_3_PERIODIC__SHIFT__CI__VI 0x00000016 -#define PERF_MON_CTRL_1__CHAN_3_SEL__SHIFT__CI__VI 0x0000000a -#define PERF_MON_CTRL_1__CHAN_4_PERIODIC__SHIFT__CI__VI 0x00000017 -#define PERF_MON_CTRL_1__CHAN_4_SEL__SHIFT__CI__VI 0x0000000f -#define PERF_MON_CTRL_1__RESERVED__SHIFT__CI__VI 0x0000001e -#define PERF_MON_CTRL_2__CHAN_3_MODE__SHIFT__CI__VI 0x00000016 -#define PERF_MON_CTRL_2__CHAN_4_MODE__SHIFT__CI__VI 0x00000019 -#define PERF_MON_CTRL_2__ENABLE__SHIFT__CI__VI 0x00000014 -#define PERF_MON_CTRL_2__PERIOD__SHIFT__CI__VI 0x00000000 -#define PERF_MON_CTRL_2__RESERVED__SHIFT__CI__VI 0x0000001c -#define PERF_MON_CTRL_2__RESET__SHIFT__CI__VI 0x00000015 -#define PERF_MON_CTRL_2__UNIT__SHIFT__CI__VI 0x00000010 -#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT__SI 0x00000010 -#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT__SI 0x0000000c -#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT__SI 0x0000000e -#define PHY_PAD_FORCE_DIS1__B_PIMP_RX_PDNB_DIS__SHIFT__SI 0x00000005 -#define PHY_PAD_FORCE_DIS1__B_PIMP_TX_PDNB_DIS__SHIFT__SI 0x00000004 -#define PHY_PAD_FORCE_DIS1__B_PPLL_BUF_PDNB_DIS__SHIFT__SI 0x00000002 -#define PHY_PAD_FORCE_DIS1__B_PPLL_PDNB_DIS__SHIFT__SI 0x00000000 -#define PHY_PAD_FORCE_DIS1__B_PRX_FRONTEND_DIS__SHIFT__SI 0x00000006 -#define PHY_PAD_FORCE_DIS2__B_PRX_PDNB_DIS__SHIFT__SI 0x00000010 -#define PHY_PAD_FORCE_DIS2__B_PTX_PDNB_DIS__SHIFT__SI 0x00000000 -#define PHY_PAD_FORCE_EN1__B_PIMP_RX_PDNB_EN__SHIFT__SI 0x00000005 -#define PHY_PAD_FORCE_EN1__B_PIMP_TX_PDNB_EN__SHIFT__SI 0x00000004 -#define PHY_PAD_FORCE_EN1__B_PPLL_BUF_PDNB_EN__SHIFT__SI 0x00000002 -#define PHY_PAD_FORCE_EN1__B_PPLL_PDNB_EN__SHIFT__SI 0x00000000 -#define PHY_PAD_FORCE_EN1__B_PRX_FRONTEND_EN__SHIFT__SI 0x00000006 -#define PHY_PAD_FORCE_EN2__B_PRX_PDNB_EN__SHIFT__SI 0x00000000 -#define PHY_PAD_FORCE_EN2__B_PTX_PDNB_EN__SHIFT__SI 0x00000010 -#define PHY_TESTMODES__HISPEED_BYPASS_EN__SHIFT__SI 0x00000000 -#define PHY_TESTMODES__LOCK_DETECT_EN_0__SHIFT__SI 0x00000006 -#define PHY_TESTMODES__LOCK_DETECT_EN_1__SHIFT__SI 0x00000007 -#define PHY_TESTMODES__SELECT_OUTPUT__SHIFT__SI 0x00000002 -#define PHY_TESTMODES__SWAP_OUTPUT__SHIFT__SI 0x00000001 -#define PIPE0_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE0_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT__SI 0x00000000 -#define PIPE0_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE0_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE0_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT__SI 0x00000010 -#define PIPE0_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT__SI 0x00000000 -#define PIPE1_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE1_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT__SI 0x00000000 -#define PIPE1_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE1_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE1_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT__SI 0x00000010 -#define PIPE1_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT__SI 0x00000000 -#define PIPE2_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE2_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT__SI 0x00000000 -#define PIPE2_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE2_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE2_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT__SI 0x00000010 -#define PIPE2_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT__SI 0x00000000 -#define PIPE3_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE3_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT__SI 0x00000000 -#define PIPE3_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE3_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE3_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT__SI 0x00000010 -#define PIPE3_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT__SI 0x00000000 -#define PIPE4_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE4_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT__SI 0x00000000 -#define PIPE4_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE4_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE4_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT__SI 0x00000010 -#define PIPE4_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT__SI 0x00000000 -#define PIPE5_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE5_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT__SI 0x00000000 -#define PIPE5_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE5_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT__SI 0x00000010 -#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT__SI 0x00000000 -#define PIPE5_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT__SI 0x00000010 -#define PIPE5_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT__SI 0x00000000 -#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT__SI 0x00000004 -#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT__SI 0x00000000 -#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT__SI 0x00000004 -#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT__SI 0x00000000 -#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x00000008 -#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x00000011 -#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x00000004 -#define PLL_TEST_CNTL__TST_RESET__SHIFT 0x0000000f -#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x00000000 -#define PMI_CAP_LIST__CAP_ID__SHIFT 0x00000000 -#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x00000008 -#define PMI_CAP__AUX_CURRENT__SHIFT 0x00000006 -#define PMI_CAP__D1_SUPPORT__SHIFT 0x00000009 -#define PMI_CAP__D2_SUPPORT__SHIFT 0x0000000a -#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x00000005 -#define PMI_CAP__PME_CLOCK__SHIFT 0x00000003 -#define PMI_CAP__PME_SUPPORT__SHIFT 0x0000000b -#define PMI_CAP__VERSION__SHIFT 0x00000000 -#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x00000016 -#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x00000017 -#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0x0000000d -#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x00000009 -#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x00000003 -#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x00000008 -#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0x0000000f -#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x00000018 -#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x00000000 -#define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON__SHIFT__SI 0x00000014 -#define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK__SHIFT__SI 0x00000018 -#define PRIORITY_A_CNT__PRIORITY_A_OFF__SHIFT__SI 0x00000010 -#define PRIORITY_A_CNT__PRIORITY_MARK_A__SHIFT__SI 0x00000000 -#define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON__SHIFT__SI 0x00000014 -#define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK__SHIFT__SI 0x00000018 -#define PRIORITY_B_CNT__PRIORITY_B_OFF__SHIFT__SI 0x00000010 -#define PRIORITY_B_CNT__PRIORITY_MARK_B__SHIFT__SI 0x00000000 -#define PROCESSOR_TDP__Base_Tdp__SHIFT__CI__VI 0x00000010 -#define PROCESSOR_TDP__Processor_Tdp__SHIFT__CI__VI 0x00000000 -#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x00000000 -#define PSTATE_STATUS__Cmp_Unit0_Pstate__SHIFT__CI__VI 0x00000000 -#define PSTATE_STATUS__Cmp_Unit1_Pstate__SHIFT__CI__VI 0x00000004 -#define PSTATE_STATUS__Curr_Core_Vid_Pstate__SHIFT__CI__VI 0x00000017 -#define PSTATE_STATUS__Curr_Nb_Vid_Pstate__SHIFT__CI__VI 0x0000001a -#define PSTATE_STATUS__Pwr_Mgmt_Req_Act1__SHIFT__CI__VI 0x0000001e -#define PSTATE_STATUS__Pwr_Mgmt_Req_Act2__SHIFT__CI__VI 0x0000001f -#define PSTATE_STATUS__Pwr_Mgmt_Req_Wait__SHIFT__CI__VI 0x0000001c -#define PSTATE_STATUS__RESERVED_1__SHIFT__CI__VI 0x00000003 -#define PSTATE_STATUS__RESERVED__SHIFT__CI__VI 0x00000007 -#define PSTATE_STATUS__Vid_Transition_Act__SHIFT__CI__VI 0x0000001d -#define PWR_BIF_SSA__WAKE_UP__SHIFT__CI__VI 0x00000000 -#define PWR_EVENT_CLEAR__AZALIA__SHIFT__CI__VI 0x0000000a -#define PWR_EVENT_CLEAR__BIF__SHIFT__CI__VI 0x0000000b -#define PWR_EVENT_CLEAR__DC__SHIFT__CI__VI 0x0000000c -#define PWR_EVENT_CLEAR__DISPLAY_GAP__SHIFT__CI__VI 0x00000009 -#define PWR_EVENT_CLEAR__MCB__SHIFT__CI__VI 0x00000008 -#define PWR_EVENT_CLEAR__MCD0__SHIFT__CI__VI 0x00000000 -#define PWR_EVENT_CLEAR__MCD1__SHIFT__CI__VI 0x00000001 -#define PWR_EVENT_CLEAR__MCD2__SHIFT__CI__VI 0x00000002 -#define PWR_EVENT_CLEAR__MCD3__SHIFT__CI__VI 0x00000003 -#define PWR_EVENT_CLEAR__MCD4__SHIFT__CI__VI 0x00000004 -#define PWR_EVENT_CLEAR__MCD5__SHIFT__CI__VI 0x00000005 -#define PWR_EVENT_CLEAR__MCD6__SHIFT__CI__VI 0x00000006 -#define PWR_EVENT_CLEAR__MCD7__SHIFT__CI__VI 0x00000007 -#define PWR_EVENT_CLEAR__UVD__SHIFT__CI__VI 0x0000000e -#define PWR_EVENT_CLEAR__VCE__SHIFT__CI__VI 0x0000000d -#define PWR_EVENT_PENDING__AZALIA__SHIFT__CI__VI 0x0000000a -#define PWR_EVENT_PENDING__BIF__SHIFT__CI__VI 0x0000000b -#define PWR_EVENT_PENDING__DC__SHIFT__CI__VI 0x0000000c -#define PWR_EVENT_PENDING__DISPLAY_GAP__SHIFT__CI__VI 0x00000009 -#define PWR_EVENT_PENDING__MCB__SHIFT__CI__VI 0x00000008 -#define PWR_EVENT_PENDING__MCD0__SHIFT__CI__VI 0x00000000 -#define PWR_EVENT_PENDING__MCD1__SHIFT__CI__VI 0x00000001 -#define PWR_EVENT_PENDING__MCD2__SHIFT__CI__VI 0x00000002 -#define PWR_EVENT_PENDING__MCD3__SHIFT__CI__VI 0x00000003 -#define PWR_EVENT_PENDING__MCD4__SHIFT__CI__VI 0x00000004 -#define PWR_EVENT_PENDING__MCD5__SHIFT__CI__VI 0x00000005 -#define PWR_EVENT_PENDING__MCD6__SHIFT__CI__VI 0x00000006 -#define PWR_EVENT_PENDING__MCD7__SHIFT__CI__VI 0x00000007 -#define PWR_EVENT_PENDING__UVD__SHIFT__CI__VI 0x0000000e -#define PWR_EVENT_PENDING__VCE__SHIFT__CI__VI 0x0000000d -#define PWR_EVENT_POLARITY__AZALIA__SHIFT__CI__VI 0x0000000a -#define PWR_EVENT_POLARITY__BIF__SHIFT__CI__VI 0x0000000b -#define PWR_EVENT_POLARITY__DC__SHIFT__CI__VI 0x0000000c -#define PWR_EVENT_POLARITY__DISPLAY_GAP__SHIFT__CI__VI 0x00000009 -#define PWR_EVENT_POLARITY__MCB__SHIFT__CI__VI 0x00000008 -#define PWR_EVENT_POLARITY__MCD0__SHIFT__CI__VI 0x00000000 -#define PWR_EVENT_POLARITY__MCD1__SHIFT__CI__VI 0x00000001 -#define PWR_EVENT_POLARITY__MCD2__SHIFT__CI__VI 0x00000002 -#define PWR_EVENT_POLARITY__MCD3__SHIFT__CI__VI 0x00000003 -#define PWR_EVENT_POLARITY__MCD4__SHIFT__CI__VI 0x00000004 -#define PWR_EVENT_POLARITY__MCD5__SHIFT__CI__VI 0x00000005 -#define PWR_EVENT_POLARITY__MCD6__SHIFT__CI__VI 0x00000006 -#define PWR_EVENT_POLARITY__MCD7__SHIFT__CI__VI 0x00000007 -#define PWR_EVENT_POLARITY__UVD__SHIFT__CI__VI 0x0000000e -#define PWR_EVENT_POLARITY__VCE__SHIFT__CI__VI 0x0000000d -#define PWR_EVENT_SENSE__AZALIA__SHIFT__CI__VI 0x0000000a -#define PWR_EVENT_SENSE__BIF__SHIFT__CI__VI 0x0000000b -#define PWR_EVENT_SENSE__DC__SHIFT__CI__VI 0x0000000c -#define PWR_EVENT_SENSE__DISPLAY_GAP__SHIFT__CI__VI 0x00000009 -#define PWR_EVENT_SENSE__MCB__SHIFT__CI__VI 0x00000008 -#define PWR_EVENT_SENSE__MCD0__SHIFT__CI__VI 0x00000000 -#define PWR_EVENT_SENSE__MCD1__SHIFT__CI__VI 0x00000001 -#define PWR_EVENT_SENSE__MCD2__SHIFT__CI__VI 0x00000002 -#define PWR_EVENT_SENSE__MCD3__SHIFT__CI__VI 0x00000003 -#define PWR_EVENT_SENSE__MCD4__SHIFT__CI__VI 0x00000004 -#define PWR_EVENT_SENSE__MCD5__SHIFT__CI__VI 0x00000005 -#define PWR_EVENT_SENSE__MCD6__SHIFT__CI__VI 0x00000006 -#define PWR_EVENT_SENSE__MCD7__SHIFT__CI__VI 0x00000007 -#define PWR_EVENT_SENSE__UVD__SHIFT__CI__VI 0x0000000e -#define PWR_EVENT_SENSE__VCE__SHIFT__CI__VI 0x0000000d -#define PWR_IDSC_CTRL2__CMON_ADC_RANGE_RST__SHIFT__CI 0x00000001 -#define PWR_IDSC_CTRL2__CMON_INPUT_SEL__SHIFT__CI 0x00000002 -#define PWR_IDSC_CTRL2__CMON_RESET__SHIFT__CI 0x00000000 -#define PWR_IDSC_CTRL2__IDSC_DCM_OVERRIDE__SHIFT__CI 0x00000008 -#define PWR_IDSC_CTRL2__IDSC_DVID__SHIFT__CI 0x00000017 -#define PWR_IDSC_CTRL2__IDSC_EFUSE_READY__SHIFT__CI 0x00000004 -#define PWR_IDSC_CTRL2__IDSC_FADC_ADJ__SHIFT__CI 0x0000000d -#define PWR_IDSC_CTRL2__IDSC_FADC_CALIBRATE__SHIFT__CI 0x00000011 -#define PWR_IDSC_CTRL2__IDSC_FX_ADJ__SHIFT__CI 0x00000012 -#define PWR_IDSC_CTRL2__IDSC_FX_CALIBRATE__SHIFT__CI 0x00000016 -#define PWR_IDSC_CTRL2__IDSC_LEGACY_MODE__SHIFT__CI 0x00000003 -#define PWR_IDSC_CTRL2__IDSC_MCLK_FREQ__SHIFT__CI 0x00000009 -#define PWR_IDSC_CTRL2__IDSC_SWITCHING_FREQ__SHIFT__CI 0x00000006 -#define PWR_IDSC_CTRL2__IDSC_TWO_PHASE__SHIFT__CI 0x00000005 -#define PWR_IDSC_CTRL__CMON_ADC_CFG__SHIFT__CI 0x0000000c -#define PWR_IDSC_CTRL__CMON_ADC_GAIN_ADJ_MODE__SHIFT__CI 0x0000001f -#define PWR_IDSC_CTRL__CMON_ADC_GAIN_ADJ__SHIFT__CI 0x00000007 -#define PWR_IDSC_CTRL__CMON_BGADJ_MODE__SHIFT__CI 0x0000001e -#define PWR_IDSC_CTRL__CMON_BGADJ__SHIFT__CI 0x00000001 -#define PWR_IDSC_CTRL__CMON_DAC_BYPASS__SHIFT__CI 0x00000012 -#define PWR_IDSC_CTRL__CMON_OFFSET_CAN_EN__SHIFT__CI 0x0000001c -#define PWR_IDSC_CTRL__CMON_PDB__SHIFT__CI 0x00000000 -#define PWR_IDSC_CTRL__CMON_SELF_CAL_EN__SHIFT__CI 0x0000001d -#define PWR_IDSC_CTRL__CMON_TESTCNTL__SHIFT__CI 0x0000000e -#define PWR_INT_GPIO_CLEAR__INT_GPIO_CLEAR__SHIFT__CI__VI 0x00000000 -#define PWR_INT_GPIO_PENDING__INT_GPIO_PENDING__SHIFT__CI__VI 0x00000000 -#define PWR_INT_GPIO_POLARITY__INT_GPIO_POLARITY__SHIFT__CI__VI 0x00000000 -#define PWR_INT_GPIO_SENSE__INT_GPIO_SENSE__SHIFT__CI__VI 0x00000000 -#define PWR_MM_CNTL__CG_DCO_CLK_SLOW__SHIFT__CI__VI 0x00000001 -#define PWR_MM_CNTL__CG_VCE_CLK_SLOW__SHIFT__CI__VI 0x00000000 -#define PWR_MM_CNTL__DCO_CG_CLK_SLOW_ACK__SHIFT__CI__VI 0x0000000f -#define PWR_MM_CNTL__DC_SMU_EVENT_INTERRUPT__SHIFT__CI__VI 0x00000002 -#define PWR_MM_CNTL__UVD_CG_CLK_SWITCH_ACK__SHIFT__CI__VI 0x00000010 -#define PWR_MM_CNTL__VCE_CG_CLK_SLOW_ACK__SHIFT__CI__VI 0x0000000e -#define PWR_MM_CNTL__VCE_CG_CLK_SWITCH_ACK__SHIFT__CI__VI 0x00000011 -#define PWR_RLC_CNTL__RLC_CGCG_OVERRIDE_OFF__SHIFT__CI__VI 0x00000000 -#define PWR_RLC_CNTL__RLC_CGCG_OVERRIDE_ON__SHIFT__CI__VI 0x00000001 -#define PWR_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define PWR_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_CNTL__CNTR_EN__SHIFT__CI__VI 0x00000012 -#define PWR_STAT_CNTR_CNTL__DIVIDE__SHIFT__CI__VI 0x00000018 -#define PWR_STAT_CNTR_CNTL__DPM_STATE__SHIFT__CI__VI 0x00000013 -#define PWR_STAT_CNTR_CNTL__PERIOD_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_CNTL__SEL__SHIFT__CI__VI 0x0000001c -#define PWR_STAT_CNTR_CNTL__UNIT_CNT__SHIFT__CI__VI 0x0000000e -#define PWR_STAT_CNTR_EVENT_0__EVENT_0_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_1__EVENT_1_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_2__EVENT_2_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_3__EVENT_3_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_4__EVENT_4_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_5__EVENT_5_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_6__EVENT_6_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_7__EVENT_7_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_EVENT_8__EVENT_8_TIMES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_CNTR_TIME__BUF_EMPTY__SHIFT__CI__VI 0x0000001f -#define PWR_STAT_CNTR_TIME__BUF_POP__SHIFT__CI__VI 0x0000001e -#define PWR_STAT_CNTR_TIME__EVENT_CYCLES_CNT__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_0_SELECT__SHIFT__CI__VI 0x00000005 -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_1_SELECT__SHIFT__CI__VI 0x00000008 -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_2_SELECT__SHIFT__CI__VI 0x0000000b -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_3_SELECT__SHIFT__CI__VI 0x0000000e -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_4_SELECT__SHIFT__CI__VI 0x00000011 -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_5_SELECT__SHIFT__CI__VI 0x00000014 -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_6_SELECT__SHIFT__CI__VI 0x00000017 -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_7_SELECT__SHIFT__CI__VI 0x0000001a -#define PWR_STAT_EVENT_SEL_CNTL__EVENT_8_SELECT__SHIFT__CI__VI 0x0000001d -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_0__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_1__SHIFT__CI__VI 0x00000004 -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_2__SHIFT__CI__VI 0x00000008 -#define PWR_STAT_GFX_CU_EVENT_CNTL__GFX_CU_EVENT_SELECT_3__SHIFT__CI__VI 0x0000000c -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_0__SHIFT__CI__VI 0x00000000 -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_1__SHIFT__CI__VI 0x00000005 -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_2__SHIFT__CI__VI 0x0000000a -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_3__SHIFT__CI__VI 0x0000000f -#define PWR_STAT_GFX_NONCU_EVENT_CNTL__GFX_NONCU_EVENT_SELECT_4__SHIFT__CI__VI 0x00000014 -#define PWR_SVI2_PLANE1_LOAD__LOADLINE__SHIFT__CI 0x00000000 -#define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT__CI 0x00000006 -#define PWR_SVI2_PLANE1_LOAD__PSI0_VID__SHIFT__CI 0x00000007 -#define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT__CI 0x00000005 -#define PWR_SVI2_PLANE1_LOAD__WAIT_VID_COMP_DIS__SHIFT__CI 0x0000000f -#define PWR_SVI2_PLANE2_LOAD__LOADLINE__SHIFT__CI 0x00000000 -#define PWR_SVI2_PLANE2_LOAD__PSI0_EN__SHIFT__CI 0x00000006 -#define PWR_SVI2_PLANE2_LOAD__PSI0_VID__SHIFT__CI 0x00000007 -#define PWR_SVI2_PLANE2_LOAD__PSI1__SHIFT__CI 0x00000005 -#define PWR_SVI2_STATUS__DELAY_CNT_BUSY__SHIFT__CI 0x00000012 -#define PWR_SVI2_STATUS__PLANE1_VID__SHIFT__CI 0x00000000 -#define PWR_SVI2_STATUS__PLANE2_VID__SHIFT__CI 0x00000008 -#define PWR_SVI2_STATUS__SVI2_BUSY__SHIFT__CI 0x00000011 -#define PWR_SVI2_STATUS__VID_CHANGE_BUSY__SHIFT__CI 0x00000010 -#define PWR_SVI2_TELEMETRY_1__IDD_INFO__SHIFT__CI 0x00000000 -#define PWR_SVI2_TELEMETRY_1__VDD_INFO__SHIFT__CI 0x00000010 -#define PWR_SVI2_TELEMETRY_2__IDD_INFO__SHIFT__CI 0x00000000 -#define PWR_SVI2_TELEMETRY_2__VDD_INFO__SHIFT__CI 0x00000010 -#define PWR_SVI2_TFN__SVI2_HIGH_FREQ_SEL__SHIFT__CI 0x00000002 -#define PWR_SVI2_TFN__TFN_CTRL__SHIFT__CI 0x00000000 -#define PWR_SVI2_THERM_CNTL__THERM_TRIP__SHIFT__CI 0x00000008 -#define PWR_SVI2_THERM_CNTL__THERM_VID__SHIFT__CI 0x00000000 -#define PWR_SVI2_VID__NB_VSTIME__SHIFT__CI 0x0000000b -#define PWR_SVI2_VID__SEND_VID_EN__SHIFT__CI 0x0000000a -#define PWR_SVI2_VID__SVID_CODE__SHIFT__CI 0x00000000 -#define PWR_SVI2_VID__VID_PLANE__SHIFT__CI 0x00000008 -#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 -#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 -#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x00000000 -#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x00000000 -#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x00000000 -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x00000000 -#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 -#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT__SI__CI 0x00000000 -#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 -#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 -#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 -#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 -#define RCU_ASIC_SERIAL_NUM0__BITS31_0__SHIFT__SI 0x00000000 -#define RCU_ASIC_SERIAL_NUM1__BITS49_32__SHIFT__SI 0x00000000 -#define RCU_BACKUP_STRAP0__BITS__SHIFT__SI 0x00000000 -#define RCU_BACKUP_STRAP1__BITS__SHIFT__SI 0x00000000 -#define RCU_BACKUP_STRAP2__BITS__SHIFT__SI 0x00000000 -#define RCU_BACKUP_STRAP3__BITS__SHIFT__SI 0x00000000 -#define RCU_CC_ATC_FUSE__TRANSLATE_SECURE__SHIFT__SI 0x00000001 -#define RCU_CC_ATC_FUSE__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_AZALIA_ID__BITS__SHIFT__SI 0x00000003 -#define RCU_CC_BIF_AZALIA_ID__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_ID_STRAPS__SPARE__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_ATI_REV_ID__SHIFT__SI 0x0000001c -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_F0_DEVICE_ID__SHIFT__SI 0x00000004 -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT__SI 0x00000014 -#define RCU_CC_BIF_ID_STRAPS__STRAP_BIF_F0_MINOR_REV_ID__SHIFT__SI 0x00000018 -#define RCU_CC_BIF_ID_STRAPS__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_SECURE_CNTL__SECURE_ID__SHIFT__SI 0x00000010 -#define RCU_CC_BIF_SECURE_CNTL__SECURE_LVL__SHIFT__SI 0x00000008 -#define RCU_CC_BIF_SECURE_CNTL__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP0__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP0__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP10__BITS24_5__SHIFT__SI 0x00000005 -#define RCU_CC_BIF_STRAP10__BITS3_2__SHIFT__SI 0x00000002 -#define RCU_CC_BIF_STRAP10__UNUSED31_25__SHIFT__SI 0x00000019 -#define RCU_CC_BIF_STRAP10__UNUSED4__SHIFT__SI 0x00000004 -#define RCU_CC_BIF_STRAP10__UNUSED__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP10__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP11__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP11__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP12__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP12__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP13__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP13__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP14__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP14__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP1__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP1__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP2__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP2__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP3__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP3__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP4__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP4__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP5__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP5__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP6__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP6__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP7__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP7__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP8__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP8__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP9__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP9__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_BIF_STRAP_FUSE0__BITS__SHIFT__SI 0x00000001 -#define RCU_CC_BIF_STRAP_FUSE0__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_DC_AUDIO__AUD_PORT_CONN_OVR__SHIFT__SI 0x00000003 -#define RCU_CC_DC_AUDIO__AUD_PORT_CONN__SHIFT__SI 0x00000000 -#define RCU_CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT__SI 0x00000001 -#define RCU_CC_DC_PIPE_DIS__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_GC_RB_REDUNDANCY0__EN_RB_REDUNDANCY_SE0__SHIFT__SI 0x0000001f -#define RCU_CC_GC_RB_REDUNDANCY0__FAILED_RB_SE0__SHIFT__SI 0x00000010 -#define RCU_CC_GC_RB_REDUNDANCY0__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_GC_RB_REDUNDANCY1__EN_RB_REDUNDANCY_SE1__SHIFT__SI 0x0000001f -#define RCU_CC_GC_RB_REDUNDANCY1__FAILED_RB_SE1__SHIFT__SI 0x00000010 -#define RCU_CC_GC_RB_REDUNDANCY1__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG0__DIS_DPFP__SHIFT__SI 0x00000001 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG0__INACTIVE_COMPUTE_UNITS_SE0_SH0__SHIFT__SI 0x00000010 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG0__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG1__DIS_DPFP__SHIFT__SI 0x00000001 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG1__INACTIVE_COMPUTE_UNITS_SE0_SH1__SHIFT__SI 0x00000010 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG1__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG2__DIS_DPFP__SHIFT__SI 0x00000001 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG2__INACTIVE_COMPUTE_UNITS_SE1_SH0__SHIFT__SI 0x00000010 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG2__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG3__DIS_DPFP__SHIFT__SI 0x00000001 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG3__INACTIVE_COMPUTE_UNITS_SE1_SH1__SHIFT__SI 0x00000010 -#define RCU_CC_GC_SHADER_ARRAY_CONFIG3__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_MC_MAX_CHANNEL__MAX_CHANNELS__SHIFT__SI 0x00000001 -#define RCU_CC_MC_MAX_CHANNEL__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_RB_BACKEND_DISABLE0__RB_BACKEND_DISABLE_SE0_SH0__SHIFT__SI 0x00000010 -#define RCU_CC_RB_BACKEND_DISABLE0__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_RB_BACKEND_DISABLE1__RB_BACKEND_DISABLE_SE0_SH1__SHIFT__SI 0x00000010 -#define RCU_CC_RB_BACKEND_DISABLE1__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_RB_BACKEND_DISABLE2__RB_BACKEND_DISABLE_SE1_SH0__SHIFT__SI 0x00000010 -#define RCU_CC_RB_BACKEND_DISABLE2__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_RB_BACKEND_DISABLE3__RB_BACKEND_DISABLE_SE1_SH1__SHIFT__SI 0x00000010 -#define RCU_CC_RB_BACKEND_DISABLE3__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_TCC_DISABLE__TCC_DISABLE__SHIFT__SI 0x00000010 -#define RCU_CC_TCC_DISABLE__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_CC_UVD_DISABLE__UVD_DISABLE__SHIFT__SI 0x00000001 -#define RCU_CC_UVD_DISABLE__WRITE_DIS__SHIFT__SI 0x00000000 -#define RCU_DYN_RM2__BF_HD1P_RMEN__SHIFT__SI 0x00000002 -#define RCU_DYN_RM2__BF_HD1P_RM__SHIFT__SI 0x00000000 -#define RCU_DYN_RM2__BF_PDP_RMEN__SHIFT__SI 0x00000005 -#define RCU_DYN_RM2__BF_PDP_RM__SHIFT__SI 0x00000003 -#define RCU_DYN_RM2__BF_RF2P_RMEN__SHIFT__SI 0x00000008 -#define RCU_DYN_RM2__BF_RF2P_RM__SHIFT__SI 0x00000006 -#define RCU_DYN_RM2__GFX_HD1P_RMEN__SHIFT__SI 0x0000000b -#define RCU_DYN_RM2__GFX_HD1P_RM__SHIFT__SI 0x00000009 -#define RCU_DYN_RM2__GFX_PDP_RMEN__SHIFT__SI 0x0000000e -#define RCU_DYN_RM2__GFX_PDP_RM__SHIFT__SI 0x0000000c -#define RCU_DYN_RM2__GFX_RF2P_RMEN__SHIFT__SI 0x00000011 -#define RCU_DYN_RM2__GFX_RF2P_RM__SHIFT__SI 0x0000000f -#define RCU_DYN_RM2__UVD_HD1P_RMEN__SHIFT__SI 0x00000014 -#define RCU_DYN_RM2__UVD_HD1P_RM__SHIFT__SI 0x00000012 -#define RCU_DYN_RM2__UVD_PDP_RMEN__SHIFT__SI 0x00000017 -#define RCU_DYN_RM2__UVD_PDP_RM__SHIFT__SI 0x00000015 -#define RCU_DYN_RM2__UVD_RF2P_RMEN__SHIFT__SI 0x0000001a -#define RCU_DYN_RM2__UVD_RF2P_RM__SHIFT__SI 0x00000018 -#define RCU_DYN_RM__DT_HD1P_RMEN__SHIFT__SI 0x00000014 -#define RCU_DYN_RM__DT_HD1P_RM__SHIFT__SI 0x00000012 -#define RCU_DYN_RM__DT_PDP_RMEN__SHIFT__SI 0x00000017 -#define RCU_DYN_RM__DT_PDP_RM__SHIFT__SI 0x00000015 -#define RCU_DYN_RM__DT_RF2P_RMEN__SHIFT__SI 0x0000001a -#define RCU_DYN_RM__DT_RF2P_RM__SHIFT__SI 0x00000018 -#define RCU_DYN_RM__MC_HD1P_RMEN__SHIFT__SI 0x0000000b -#define RCU_DYN_RM__MC_HD1P_RM__SHIFT__SI 0x00000009 -#define RCU_DYN_RM__MC_PDP_RMEN__SHIFT__SI 0x0000000e -#define RCU_DYN_RM__MC_PDP_RM__SHIFT__SI 0x0000000c -#define RCU_DYN_RM__MC_RF2P_RMEN__SHIFT__SI 0x00000011 -#define RCU_DYN_RM__MC_RF2P_RM__SHIFT__SI 0x0000000f -#define RCU_DYN_RM__RM_REG_SEL__SHIFT__SI 0x0000001b -#define RCU_DYN_RM__SYS_HD1P_RMEN__SHIFT__SI 0x00000002 -#define RCU_DYN_RM__SYS_HD1P_RM__SHIFT__SI 0x00000000 -#define RCU_DYN_RM__SYS_PDP_RMEN__SHIFT__SI 0x00000005 -#define RCU_DYN_RM__SYS_PDP_RM__SHIFT__SI 0x00000003 -#define RCU_DYN_RM__SYS_RF2P_RMEN__SHIFT__SI 0x00000008 -#define RCU_DYN_RM__SYS_RF2P_RM__SHIFT__SI 0x00000006 -#define RCU_EFUSE_SCRATCH__GENERIC_BIOS_SCRATCH__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS0__EFUSE_BITS31_0__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS10__EFUSE_BITS351_320__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS11__EFUSE_BITS383_352__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS12__EFUSE_BITS415_384__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS13__EFUSE_BITS447_416__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS14__EFUSE_BITS479_448__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS15__EFUSE_BITS511_480__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS16__EFUSE_BITS543_512__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS17__EFUSE_BITS575_544__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS18__EFUSE_BITS607_576__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS19__EFUSE_BITS639_608__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS1__EFUSE_BITS63_32__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS20__EFUSE_BITS671_640__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS21__EFUSE_BITS703_672__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS22__EFUSE_BITS735_704__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS23__EFUSE_BITS767_736__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS24__EFUSE_BITS799_768__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS25__EFUSE_BITS831_800__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS26__EFUSE_BITS863_832__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS27__EFUSE_BITS895_864__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS28__EFUSE_BITS927_896__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS29__EFUSE_BITS959_928__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS2__EFUSE_BITS95_64__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS30__EFUSE_BITS991_960__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS31__EFUSE_BITS1023_992__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS32__EFUSE_BITS1055_1024__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS33__EFUSE_BITS1087_1056__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS34__EFUSE_BITS1119_1088__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS35__EFUSE_BITS1151_1120__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS36__EFUSE_BITS1183_1152__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS37__EFUSE_BITS1215_1184__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS38__EFUSE_BITS1247_1216__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS39__EFUSE_BITS1279_1248__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS3__EFUSE_BITS127_96__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS40__EFUSE_BITS1311_1280__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS4__EFUSE_BITS159_128__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS5__EFUSE_BITS191_160__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS6__EFUSE_BITS223_192__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS7__EFUSE_BITS255_224__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS8__EFUSE_BITS287_256__SHIFT__SI 0x00000000 -#define RCU_EFUSE_STRAPS9__EFUSE_BITS319_288__SHIFT__SI 0x00000000 -#define RCU_FCTRL__DRM_START__SHIFT__SI 0x00000000 -#define RCU_FCTRL__EFUSE_PD__SHIFT__SI 0x00000002 -#define RCU_FCTRL__FSM_RST__SHIFT__SI 0x00000003 -#define RCU_FCTRL__HDCP_START__SHIFT__SI 0x00000001 -#define RCU_FCTRL__SPARE2__SHIFT__SI 0x00000006 -#define RCU_FCTRL__TCLK_DIS__SHIFT__SI 0x00000005 -#define RCU_FCTRL__UVD_START__SHIFT__SI 0x00000004 -#define RCU_IND_DATA__RCU_IND_DATA__SHIFT__SI 0x00000000 -#define RCU_IND_INDEX__RCU_IND_ADDR__SHIFT__SI 0x00000000 -#define RCU_MISC_CTRL__BIF_RST_DIS__SHIFT__SI 0x00000002 -#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT__CI__VI 0x00000010 -#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT__CI__VI 0x00000011 -#define RCU_MISC_CTRL__CG_RST_GLB_REQ_DIS__SHIFT__SI 0x00000005 -#define RCU_MISC_CTRL__DRV_RST_MODE__SHIFT__SI 0x00000000 -#define RCU_MISC_CTRL__FCTRL_IDLE_DIS__SHIFT__SI 0x00000007 -#define RCU_MISC_CTRL__HDCP_START__SHIFT__CI__VI 0x00000015 -#define RCU_MISC_CTRL__IGNORE_CG_ACK__SHIFT__SI 0x00000001 -#define RCU_MISC_CTRL__IGNORE_DRM_RD_DONE__SHIFT__SI 0x00000009 -#define RCU_MISC_CTRL__JTAG_SRBM_DIS__SHIFT__SI 0x00000003 -#define RCU_MISC_CTRL__MEM_REP_4BIFRST_DIS__SHIFT__SI 0x00000008 -#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT__CI__VI 0x00000004 -#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT__CI__VI 0x00000008 -#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT__CI__VI 0x00000001 -#define RCU_MISC_CTRL__REG_HDCP_FUSE_DISABLE__SHIFT__CI__VI 0x00000007 -#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT__CI__VI 0x00000003 -#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT__CI__VI 0x00000005 -#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT__CI__VI 0x00000017 -#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT__SI 0x0000000a -#define RCU_MISC_CTRL__SAMU_START__SHIFT__CI__VI 0x00000016 -#define RCU_MISC_CTRL__SPARE__SHIFT__SI 0x00000006 -#define RCU_MISC_CTRL__TST_TCLK_SLOW_EN__SHIFT__SI 0x00000004 -#define RCU_PCIECONFIG__PCIE_gfx_early_reset__SHIFT__CI__VI 0x00000000 -#define RCU_PCIECONFIG__PCIE_gfx_hard_reset__SHIFT__CI__VI 0x00000001 -#define RCU_PCIECONFIG__PCIE_reset_override__SHIFT__CI__VI 0x00000002 -#define RCU_ROM_BIF_STRAP0__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP0__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP10__BITS24_5__SHIFT__SI 0x00000005 -#define RCU_ROM_BIF_STRAP10__BITS3_2__SHIFT__SI 0x00000002 -#define RCU_ROM_BIF_STRAP10__UNUSED31_25__SHIFT__SI 0x00000019 -#define RCU_ROM_BIF_STRAP10__UNUSED4__SHIFT__SI 0x00000004 -#define RCU_ROM_BIF_STRAP10__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP11__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP11__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP12__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP12__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP13__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP13__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP14__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP14__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP1__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP1__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP2__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP2__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP3__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP3__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP4__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP4__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP5__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP5__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP6__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP6__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP7__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP7__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP8__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP8__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_BIF_STRAP9__BITS__SHIFT__SI 0x00000001 -#define RCU_ROM_BIF_STRAP9__UNUSED__SHIFT__SI 0x00000000 -#define RCU_ROM_MSC_STRAPS0__ATI_REV_ID__SHIFT__SI 0x00000019 -#define RCU_ROM_MSC_STRAPS0__DEVICE_ID__SHIFT__SI 0x00000009 -#define RCU_ROM_MSC_STRAPS0__HDCP_DIS__SHIFT__SI 0x00000002 -#define RCU_ROM_MSC_STRAPS0__MC_ATC__SHIFT__SI 0x00000008 -#define RCU_ROM_MSC_STRAPS0__ROM_VALID__SHIFT__SI 0x0000001d -#define RCU_ROM_MSC_STRAPS0__SPARE__SHIFT__SI 0x00000001 -#define RCU_ROM_MSC_STRAPS0__UVD_DISABLE__SHIFT__SI 0x00000003 -#define RCU_ROM_MSC_STRAPS1__INACTIVE_COMPUTE_UNITS_SE0_SH0__SHIFT__SI 0x00000000 -#define RCU_ROM_MSC_STRAPS1__INACTIVE_COMPUTE_UNITS_SE0_SH1__SHIFT__SI 0x00000010 -#define RCU_ROM_MSC_STRAPS2__INACTIVE_COMPUTE_UNITS_SE1_SH0__SHIFT__SI 0x00000000 -#define RCU_ROM_MSC_STRAPS2__INACTIVE_COMPUTE_UNITS_SE1_SH1__SHIFT__SI 0x00000010 -#define RCU_ROM_MSC_STRAPS3__AUD_PORT_CONN_OVR__SHIFT__SI 0x00000013 -#define RCU_ROM_MSC_STRAPS3__AUD_PORT_CONN__SHIFT__SI 0x00000010 -#define RCU_ROM_MSC_STRAPS3__BITS__SHIFT__SI 0x00000014 -#define RCU_ROM_MSC_STRAPS3__VM_SECURE_ID__SHIFT__SI 0x00000000 -#define RCU_ROM_MSC_STRAPS4__EN_RB_REDUNDANCY_SE0__SHIFT__SI 0x00000016 -#define RCU_ROM_MSC_STRAPS4__EN_RB_REDUNDANCY_SE1__SHIFT__SI 0x00000017 -#define RCU_ROM_MSC_STRAPS4__FAILED_RB_SE0__SHIFT__SI 0x00000010 -#define RCU_ROM_MSC_STRAPS4__FAILED_RB_SE1__SHIFT__SI 0x00000013 -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE0_SH0__SHIFT__SI 0x00000000 -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE0_SH1__SHIFT__SI 0x00000004 -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE1_SH0__SHIFT__SI 0x00000008 -#define RCU_ROM_MSC_STRAPS4__RB_BACKEND_DISABLE_SE1_SH1__SHIFT__SI 0x0000000c -#define RCU_ROM_MSC_STRAPS5__TCC_DISABLE__SHIFT__SI 0x00000000 -#define RCU_ROM_MSC_STRAPS5__UNUSED__SHIFT__SI 0x00000010 -#define RCU_ROM_SPARE_STRAP0__BITS__SHIFT__SI 0x00000000 -#define RCU_ROM_SPARE_STRAP1__BITS__SHIFT__SI 0x00000000 -#define RCU_ROM_SPARE_STRAP2__BITS__SHIFT__SI 0x00000000 -#define RCU_ROM_SPARE_STRAP3__BITS__SHIFT__SI 0x00000000 -#define RCU_SCRATCH_0__SCRATCH_0__SHIFT__SI 0x00000000 -#define RCU_SCRATCH_1__SCRATCH_1__SHIFT__SI 0x00000000 -#define RCU_SCRATCH_2__SCRATCH_2__SHIFT__SI 0x00000000 -#define RCU_SPARE_EFUSE__WORD_READ__SHIFT__SI 0x00000000 -#define RCU_STATUS__BIF_RST_COUNT__SHIFT__SI 0x00000008 -#define RCU_STATUS__EFUSE_RF__SHIFT__SI 0x00000004 -#define RCU_STATUS__FCTRL_SPARE_RD_VLD__SHIFT__SI 0x00000007 -#define RCU_STATUS__FUSES_PROGRAMMED__SHIFT__SI 0x0000001c -#define RCU_STATUS__RCU_UC_PC__SHIFT__SI 0x00000010 -#define RCU_STATUS__UVD_SMU_EFUSE_RDY__SHIFT__SI 0x00000006 -#define RCU_SYSRESET__ACP_hard_resetb__SHIFT__CI 0x00000015 -#define RCU_SYSRESET__BIF_cec_hard_resetb__SHIFT__CI__VI 0x0000000f -#define RCU_SYSRESET__DC_az_hard_resetb__SHIFT__CI 0x00000011 -#define RCU_SYSRESET__GCK_hard_resetb__SHIFT__CI__VI 0x00000000 -#define RCU_SYSRESET__GIO_rst_early_resetb__SHIFT__CI__VI 0x00000004 -#define RCU_SYSRESET__GIO_rst_hard_resetb__SHIFT__CI__VI 0x00000008 -#define RCU_SYSRESET__IOMMU_hard_resetb__SHIFT__CI 0x00000018 -#define RCU_SYSRESET__PCIE_powergood__SHIFT__CI__VI 0x0000000a -#define RCU_SYSRESET__RB0_hard_resetb__SHIFT__CI 0x00000016 -#define RCU_SYSRESET__RB1_hard_resetb__SHIFT__CI 0x00000017 -#define RCU_SYSRESET__TARG_early_resetb__SHIFT__CI__VI 0x00000005 -#define RCU_SYSRESET__UVD_hard_resetb__SHIFT__CI 0x00000013 -#define RCU_SYSRESET__VCE_hard_resetb__SHIFT__CI 0x00000014 -#define RCU_SYSRESET__VDDC_hard_resetb__SHIFT__CI__VI 0x00000010 -#define RCU_UC_EVENTS_DATA__BIF_STRAPS_WRITTEN__SHIFT__SI 0x00000010 -#define RCU_UC_EVENTS_DATA__CC_EFUSE_BYTE1_RDVLD__SHIFT__SI 0x00000002 -#define RCU_UC_EVENTS_DATA__CC_EFUSE_RDVLD__SHIFT__SI 0x00000003 -#define RCU_UC_EVENTS_DATA__CONFIG_DONE__SHIFT__SI 0x00000005 -#define RCU_UC_EVENTS_DATA__DRM_EFUSE_RD_DONE__SHIFT__SI 0x00000009 -#define RCU_UC_EVENTS_DATA__HARD_RST_DONE__SHIFT__SI 0x00000004 -#define RCU_UC_EVENTS_DATA__MEM_HARDREP_DONE__SHIFT__SI 0x00000008 -#define RCU_UC_EVENTS_DATA__PINSTRAP_CC_BYPASS__SHIFT__SI 0x00000001 -#define RCU_UC_EVENTS_DATA__PINSTRAP_MEM_HARDREP__SHIFT__SI 0x00000006 -#define RCU_UC_EVENTS_DATA__PINSTRAP_ROMEXIST__SHIFT__SI 0x00000000 -#define RCU_UC_EVENTS_DATA__UC_FLAG__SHIFT__SI 0x0000000a -#define RCU_UC_EVENTS_DATA__UC_SET_EVENT__SHIFT__SI 0x00000011 -#define RCU_UC_EVENTS_DATA__UVD_RD_DONE__SHIFT__SI 0x0000000c -#define RCU_UC_EVENTS__BIF_STRAPS_WRITTEN__SHIFT__SI 0x00000010 -#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT__CI__VI 0x00000009 -#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT__CI__VI 0x0000000a -#define RCU_UC_EVENTS__CC_EFUSE_BYTE1_RDVLD__SHIFT__SI 0x00000002 -#define RCU_UC_EVENTS__CC_EFUSE_FDO_RDVLD__SHIFT__SI 0x0000000e -#define RCU_UC_EVENTS__CC_EFUSE_RDVLD__SHIFT__SI 0x00000003 -#define RCU_UC_EVENTS__CC_EFUSE_RM_RDVLD__SHIFT__SI 0x0000000d -#define RCU_UC_EVENTS__CONFIG_DONE__SHIFT__SI 0x00000005 -#define RCU_UC_EVENTS__DRM_EFUSE_RD_DONE__SHIFT__SI 0x00000009 -#define RCU_UC_EVENTS__FCH_HALT__SHIFT__CI__VI 0x0000000b -#define RCU_UC_EVENTS__FCH_LOCKDOWN_WRITE_DIS__SHIFT__CI__VI 0x0000000c -#define RCU_UC_EVENTS__HARD_RST_DONE__SHIFT__SI 0x00000004 -#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT__CI__VI 0x00000010 -#define RCU_UC_EVENTS__MEM_HARDREP_DONE__SHIFT__SI 0x00000008 -#define RCU_UC_EVENTS__PINSTRAP_CC_BYPASS__SHIFT__SI 0x00000001 -#define RCU_UC_EVENTS__PINSTRAP_MEM_HARDREP__SHIFT__SI 0x00000006 -#define RCU_UC_EVENTS__PINSTRAP_ROMEXIST__SHIFT__SI 0x00000000 -#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT__CI__VI 0x00000011 -#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT__CI__VI 0x00000012 -#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT__CI__VI 0x00000013 -#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT__CI__VI 0x0000000d -#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT__CI__VI 0x00000000 -#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT__CI__VI 0x00000003 -#define RCU_UC_EVENTS__TP_Tester__SHIFT__CI__VI 0x00000006 -#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT__CI__VI 0x00000001 -#define RCU_UC_EVENTS__UC_FLAG__SHIFT__SI 0x0000000a -#define RCU_UC_EVENTS__UC_SET_EVENT__SHIFT__SI 0x00000011 -#define RCU_UC_EVENTS__UVD_RD_DONE__SHIFT__SI 0x0000000c -#define RCU_UC_EVENTS__boot_seq_done__SHIFT__CI__VI 0x00000007 -#define RCU_UC_EVENTS__drv_rst_mode__SHIFT__CI__VI 0x00000002 -#define RCU_UC_EVENTS__lm32_irq31_sel__SHIFT__CI__VI 0x00000018 -#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT__CI__VI 0x00000008 -#define RCU_UC_INT__DRV_ADDR__SHIFT__SI 0x0000000e -#define RCU_UC_INT__INT_ADDR__SHIFT__SI 0x00000005 -#define RCU_UC_INT__INT_EN__SHIFT__SI 0x00000000 -#define RCU_UC_INT__INT_TRIG__SHIFT__SI 0x00000001 -#define RCU_UC_INT__VC3D_ADDR__SHIFT__SI 0x00000017 -#define RCU_UC_ROMRD_INSTR__ROM_DATA__SHIFT__SI 0x00000010 -#define RCU_UC_ROMRD_INSTR__ROM_INDEX__SHIFT__SI 0x00000000 -#define REQ_FIFO_STAT__REQ_FIFO_LEVEL__SHIFT__SI 0x00000000 -#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT__SI 0x00000000 -#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x00000004 -#define REVISION_ID__MINOR_REV_ID__SHIFT 0x00000000 -#define RE_CTL2_B__DISABLE_SHIFTER_BIT_CNT_B__SHIFT__SI 0x0000001f -#define RE_CTL2_B__MAX_BYTES_B__SHIFT__SI 0x00000000 -#define RE_CTL2_B__SHIFTER_BIT_CNT_RST_B__SHIFT__SI 0x0000001e -#define RE_CTL2_B__SW_FEED_EMPTY_B__SHIFT__SI 0x0000001d -#define RE_CTL2__DISABLE_SHIFTER_BIT_CNT__SHIFT__SI 0x0000001f -#define RE_CTL2__MAX_BYTES__SHIFT__SI 0x00000000 -#define RE_CTL2__SHIFTER_BIT_CNT_RST__SHIFT__SI 0x0000001e -#define RE_CTL2__SW_FEED_EMPTY__SHIFT__SI 0x0000001d -#define RE_CTL__EMU_REMOVE_DIS_B__SHIFT__SI 0x0000000f -#define RE_CTL__EMU_REMOVE_DIS__SHIFT__SI 0x00000005 -#define RE_CTL__PURGE_DIS__SHIFT__SI 0x0000000e -#define RE_CTL__QUEUE_BYPASS__SHIFT__SI 0x00000018 -#define RE_CTL__QUEUE_TIMEOUT_COUNT__SHIFT__SI 0x00000008 -#define RE_CTL__QUEUE_TIMEOUT_EN__SHIFT__SI 0x00000006 -#define RE_CTL__REG_CMD_RESULT__SHIFT__SI 0x00000004 -#define RE_CTL__RE_PURGE_COUNT__SHIFT__SI 0x00000010 -#define RE_CTL__STANDARD__SHIFT__SI 0x00000000 -#define RE_CTL__STREAM_B_SEL__SHIFT__SI 0x00000007 -#define RE_CTL__SW_BRST_B__SHIFT__SI 0x0000001b -#define RE_CTL__SW_BRST__SHIFT__SI 0x0000001e -#define RE_CTL__SW_RRST2_B__SHIFT__SI 0x0000001a -#define RE_CTL__SW_RRST2__SHIFT__SI 0x0000001c -#define RE_CTL__SW_RRST__SHIFT__SI 0x0000001d -#define RE_CTL__SW_SRST__SHIFT__SI 0x0000001f -#define RE_DEBUG_INT_STAT__BIN_IDX_ERR__SHIFT__SI 0x0000000c -#define RE_DEBUG_INT_STAT__CABAC_INIT_DONE__SHIFT__SI 0x00000000 -#define RE_DEBUG_INT_STAT__FEED_EMPTY_ERR__SHIFT__SI 0x0000000b -#define RE_DEBUG_INT_STAT__LP_DEC_ERR__SHIFT__SI 0x00000004 -#define RE_DEBUG_INT_STAT__MB_RES_DONE__SHIFT__SI 0x00000002 -#define RE_DEBUG_INT_STAT__OVERRUN_ERR__SHIFT__SI 0x00000008 -#define RE_DEBUG_INT_STAT__PES_SC_FOUND__SHIFT__SI 0x0000000d -#define RE_DEBUG_INT_STAT__QUEUE_TIMEOUT_ERR__SHIFT__SI 0x0000000e -#define RE_DEBUG_INT_STAT__RB_DEC_ERR__SHIFT__SI 0x00000006 -#define RE_DEBUG_INT_STAT__SHIFTER_OVERRUN_ERR__SHIFT__SI 0x0000000a -#define RE_DEBUG_INT_STAT__SI_B__SHIFT__SI 0x0000000f -#define RE_DEBUG_INT_STAT__SI__SHIFT__SI 0x00000001 -#define RE_DEBUG_INT_STAT__T1TC_DEC_ERR__SHIFT__SI 0x00000003 -#define RE_DEBUG_INT_STAT__TIMEOUT_ERR__SHIFT__SI 0x00000009 -#define RE_DEBUG_INT_STAT__TZ_DEC_ERR__SHIFT__SI 0x00000005 -#define RE_DEBUG_INT_STAT__UE_DEC_ERR__SHIFT__SI 0x00000007 -#define RE_DEBUG_SI_B__DAT__SHIFT__SI 0x00000000 -#define RE_DEBUG_SI__DAT__SHIFT__SI 0x00000000 -#define RE_DECODE_CMD__MBPART_IDX__SHIFT__SI 0x0000001c -#define RE_DECODE_CMD__NUM_OF_FIXED_BIT__SHIFT__SI 0x00000008 -#define RE_DECODE_CMD__SE_ID__SHIFT__SI 0x00000000 -#define RE_DECODE_CMD__SUBMBPART_IDX__SHIFT__SI 0x0000001e -#define RE_HW_DEBUG__DAT__SHIFT__SI 0x00000000 -#define RE_INT_EN__BIN_IDX_ERR_EN__SHIFT__SI 0x0000000c -#define RE_INT_EN__CABAC_INIT_DONE_EN__SHIFT__SI 0x00000000 -#define RE_INT_EN__FEED_EMPTY_ERR_EN__SHIFT__SI 0x0000000b -#define RE_INT_EN__LP_DEC_ERR_EN__SHIFT__SI 0x00000004 -#define RE_INT_EN__MB_RES_DONE_EN__SHIFT__SI 0x00000002 -#define RE_INT_EN__OVERRUN_ERR_EN__SHIFT__SI 0x00000008 -#define RE_INT_EN__PES_SC_FOUND_EN__SHIFT__SI 0x0000000d -#define RE_INT_EN__QUEUE_TIMEOUT_ERR_EN__SHIFT__SI 0x0000000e -#define RE_INT_EN__RB_DEC_ERR_EN__SHIFT__SI 0x00000006 -#define RE_INT_EN__SHIFTER_OVERRUN_ERR_EN__SHIFT__SI 0x0000000a -#define RE_INT_EN__SI_B_EN__SHIFT__SI 0x0000000f -#define RE_INT_EN__SI_EN__SHIFT__SI 0x00000001 -#define RE_INT_EN__T1TC_DEC_ERR_EN__SHIFT__SI 0x00000003 -#define RE_INT_EN__TIMEOUT_ERR_EN__SHIFT__SI 0x00000009 -#define RE_INT_EN__TZ_DEC_ERR_EN__SHIFT__SI 0x00000005 -#define RE_INT_EN__UE_DEC_ERR_EN__SHIFT__SI 0x00000007 -#define RE_INT_STAT__BIN_IDX_ERR__SHIFT__SI 0x0000000c -#define RE_INT_STAT__CABAC_INIT_DONE__SHIFT__SI 0x00000000 -#define RE_INT_STAT__FEED_EMPTY_ERR__SHIFT__SI 0x0000000b -#define RE_INT_STAT__LP_DEC_ERR__SHIFT__SI 0x00000004 -#define RE_INT_STAT__MB_RES_DONE__SHIFT__SI 0x00000002 -#define RE_INT_STAT__OVERRUN_ERR__SHIFT__SI 0x00000008 -#define RE_INT_STAT__PES_SC_FOUND__SHIFT__SI 0x0000000d -#define RE_INT_STAT__QUEUE_TIMEOUT_ERR__SHIFT__SI 0x0000000e -#define RE_INT_STAT__RB_DEC_ERR__SHIFT__SI 0x00000006 -#define RE_INT_STAT__SHIFTER_OVERRUN_ERR__SHIFT__SI 0x0000000a -#define RE_INT_STAT__SI_B__SHIFT__SI 0x0000000f -#define RE_INT_STAT__SI__SHIFT__SI 0x00000001 -#define RE_INT_STAT__T1TC_DEC_ERR__SHIFT__SI 0x00000003 -#define RE_INT_STAT__TIMEOUT_ERR__SHIFT__SI 0x00000009 -#define RE_INT_STAT__TZ_DEC_ERR__SHIFT__SI 0x00000005 -#define RE_INT_STAT__UE_DEC_ERR__SHIFT__SI 0x00000007 -#define RE_LMA_ADR__ADR__SHIFT__SI 0x00000000 -#define RE_LMA_CTL__ACCESS_MODE__SHIFT__SI 0x00000000 -#define RE_LMA_CTL__AUTO_INC__SHIFT__SI 0x00000006 -#define RE_LMA_CTL__MEMORY_SELECT__SHIFT__SI 0x00000001 -#define RE_LMA_DAT__DAT__SHIFT__SI 0x00000000 -#define RE_PES_CTL__EMU_MASK_RST_B__SHIFT__SI 0x00000012 -#define RE_PES_CTL__EMU_MASK_RST__SHIFT__SI 0x00000002 -#define RE_PES_CTL__PES_SC_NBL_ONLY_B__SHIFT__SI 0x00000011 -#define RE_PES_CTL__PES_SC_NBL_ONLY__SHIFT__SI 0x00000001 -#define RE_PES_CTL__PES_SC_SUFFIX_B__SHIFT__SI 0x00000018 -#define RE_PES_CTL__PES_SC_SUFFIX__SHIFT__SI 0x00000008 -#define RE_PES_CTL__PES_STREAM_B__SHIFT__SI 0x00000010 -#define RE_PES_CTL__PES_STREAM__SHIFT__SI 0x00000000 -#define RE_PES_DECODE_CMD__PES_NUM_OF_FIXED_BIT__SHIFT__SI 0x00000008 -#define RE_PES_DECODE_CMD__PES_SE_ID__SHIFT__SI 0x00000000 -#define RE_PES_RESULT__PES_SYMBOL__SHIFT__SI 0x00000000 -#define RE_PES_SHIFTER_STAT__PES_BIT_POS_B__SHIFT__SI 0x00000018 -#define RE_PES_SHIFTER_STAT__PES_BIT_POS__SHIFT__SI 0x00000008 -#define RE_PES_SHIFTER_STAT__PES_SHIFTER_REFILL_B__SHIFT__SI 0x00000017 -#define RE_PES_SHIFTER_STAT__PES_SHIFTER_REFILL__SHIFT__SI 0x00000007 -#define RE_PES_SHIFTER_STAT__PES_VALID_BITS_B__SHIFT__SI 0x00000010 -#define RE_PES_SHIFTER_STAT__PES_VALID_BITS__SHIFT__SI 0x00000000 -#define RE_PPS_INFO__CABAC_ENTROPY_FLAG__SHIFT__SI 0x00000000 -#define RE_PPS_INFO__NUM_REF_IDX_L0_ACTIVE_GT1__SHIFT__SI 0x00000001 -#define RE_PPS_INFO__NUM_REF_IDX_L1_ACTIVE_GT1__SHIFT__SI 0x00000002 -#define RE_PPS_INFO__PIC_HEIGHT7_3__SHIFT__SI 0x00000003 -#define RE_PPS_INFO__PIC_HEIGHT_DIV3__SHIFT__SI 0x00000010 -#define RE_PPS_INFO__PIC_HEIGHT_MOD3__SHIFT__SI 0x00000016 -#define RE_PPS_INFO__PIC_WIDTH_DIV3__SHIFT__SI 0x00000018 -#define RE_PPS_INFO__PIC_WIDTH_MOD3__SHIFT__SI 0x0000001e -#define RE_PPS_INFO__PIC_WIDTH__SHIFT__SI 0x00000008 -#define RE_RESULT__SYMBOL__SHIFT__SI 0x00000000 -#define RE_SHIFTER_B_STAT2__BIT_POS_B__SHIFT__SI 0x0000001d -#define RE_SHIFTER_B_STAT2__SHIFTER_BIT_CNT_B__SHIFT__SI 0x00000000 -#define RE_SHIFTER_CTXT__DAT__SHIFT__SI 0x00000000 -#define RE_SHIFTER_STAT2__BIT_POS__SHIFT__SI 0x0000001d -#define RE_SHIFTER_STAT2__SHIFTER_BIT_CNT__SHIFT__SI 0x00000000 -#define RE_SHIFTER_STAT__SHIFTER_REFILL_B__SHIFT__SI 0x00000017 -#define RE_SHIFTER_STAT__SHIFTER_REFILL__SHIFT__SI 0x00000007 -#define RE_SHIFTER_STAT__VALID_BITS_B__SHIFT__SI 0x00000010 -#define RE_SHIFTER_STAT__VALID_BITS__SHIFT__SI 0x00000000 -#define RE_SHIFTER_STAT__VLD_BITS_BEFORE_SC_B__SHIFT__SI 0x00000018 -#define RE_SHIFTER_STAT__VLD_BITS_BEFORE_SC__SHIFT__SI 0x00000008 -#define RE_SI_B_CTL__BURST_SIZE_B__SHIFT__SI 0x00000014 -#define RE_SI_B_CTL__CLEAN_SHUTDOWN_EN_B__SHIFT__SI 0x0000000c -#define RE_SI_B_CTL__DEBUG_BUS_SELECT_B__SHIFT__SI 0x00000010 -#define RE_SI_B_CTL__DISABLE_PARTIAL_DWORD_OUT_B__SHIFT__SI 0x00000003 -#define RE_SI_B_CTL__DISCARD_DATA_IN_B__SHIFT__SI 0x00000009 -#define RE_SI_B_CTL__DISCONNECT_CLIENT_READ_B__SHIFT__SI 0x0000000a -#define RE_SI_B_CTL__DISCONNECT_SI_WRITE_B__SHIFT__SI 0x0000000b -#define RE_SI_B_CTL__ENDIAN_B__SHIFT__SI 0x00000004 -#define RE_SI_B_CTL__FIRST_BYTE_START_LOC_B__SHIFT__SI 0x00000001 -#define RE_SI_B_CTL__REQUEST_EN_B__SHIFT__SI 0x00000000 -#define RE_SI_B_CTL__RESET_DATA_PATH_B__SHIFT__SI 0x0000000e -#define RE_SI_B_CTL__RESET_GLOBAL_B__SHIFT__SI 0x0000000f -#define RE_SI_B_CTL__RESET_REQ_CNTRL_B__SHIFT__SI 0x0000000d -#define RE_SI_B_CTL__STREAM_ID_B__SHIFT__SI 0x00000005 -#define RE_SI_B_CTL__STREAM_ID_EN_B__SHIFT__SI 0x00000008 -#define RE_SI_B_STAT__ALL_TRANSFER_DONE_STATUS_B__SHIFT__SI 0x00000004 -#define RE_SI_B_STAT__BYTE_CNT_ERR_B__SHIFT__SI 0x00000001 -#define RE_SI_B_STAT__CLIENT_RESPONSE_STATUS_B__SHIFT__SI 0x00000006 -#define RE_SI_B_STAT__CLIENT_STATUS_B__SHIFT__SI 0x00000008 -#define RE_SI_B_STAT__DEPTH_DATA_FIFO_B__SHIFT__SI 0x00000016 -#define RE_SI_B_STAT__DROP_DATA_FIFO_FULL_ERR_B__SHIFT__SI 0x00000007 -#define RE_SI_B_STAT__DWORD_MISALIGN_ERR_B__SHIFT__SI 0x00000000 -#define RE_SI_B_STAT__DWORD_PACKER_VALID_B__SHIFT__SI 0x0000000a -#define RE_SI_B_STAT__NUM_OUTSTAND_BYTES_B__SHIFT__SI 0x0000000b -#define RE_SI_B_STAT__NUM_OUTSTAND_REQ_B__SHIFT__SI 0x00000013 -#define RE_SI_B_STAT__RECEIVED_FIRST_BYTE_STATUS_B__SHIFT__SI 0x00000005 -#define RE_SI_B_STAT__REQ_CNT_ERR_B__SHIFT__SI 0x00000002 -#define RE_SI_B_STAT__SPACE_CNT_ERR_B__SHIFT__SI 0x00000003 -#define RE_SI_CTL__BURST_SIZE__SHIFT__SI 0x00000014 -#define RE_SI_CTL__CLEAN_SHUTDOWN_EN__SHIFT__SI 0x0000000c -#define RE_SI_CTL__DEBUG_BUS_SELECT__SHIFT__SI 0x00000010 -#define RE_SI_CTL__DISABLE_PARTIAL_DWORD_OUT__SHIFT__SI 0x00000003 -#define RE_SI_CTL__DISCARD_DATA_IN__SHIFT__SI 0x00000009 -#define RE_SI_CTL__DISCONNECT_CLIENT_READ__SHIFT__SI 0x0000000a -#define RE_SI_CTL__DISCONNECT_SI_WRITE__SHIFT__SI 0x0000000b -#define RE_SI_CTL__ENDIAN__SHIFT__SI 0x00000004 -#define RE_SI_CTL__FIRST_BYTE_START_LOC__SHIFT__SI 0x00000001 -#define RE_SI_CTL__REQUEST_EN__SHIFT__SI 0x00000000 -#define RE_SI_CTL__RESET_DATA_PATH__SHIFT__SI 0x0000000e -#define RE_SI_CTL__RESET_GLOBAL__SHIFT__SI 0x0000000f -#define RE_SI_CTL__RESET_REQ_CNTRL__SHIFT__SI 0x0000000d -#define RE_SI_CTL__STREAM_ID_EN__SHIFT__SI 0x00000008 -#define RE_SI_CTL__STREAM_ID__SHIFT__SI 0x00000005 -#define RE_SI_INT_CTL__SI_INT_MASK_B__SHIFT__SI 0x00000010 -#define RE_SI_INT_CTL__SI_INT_MASK__SHIFT__SI 0x00000000 -#define RE_SI_STAT__ALL_TRANSFER_DONE_STATUS__SHIFT__SI 0x00000004 -#define RE_SI_STAT__BYTE_CNT_ERR__SHIFT__SI 0x00000001 -#define RE_SI_STAT__CLIENT_RESPONSE_STATUS__SHIFT__SI 0x00000006 -#define RE_SI_STAT__CLIENT_STATUS__SHIFT__SI 0x00000008 -#define RE_SI_STAT__DEPTH_DATA_FIFO__SHIFT__SI 0x00000016 -#define RE_SI_STAT__DROP_DATA_FIFO_FULL_ERR__SHIFT__SI 0x00000007 -#define RE_SI_STAT__DWORD_MISALIGN_ERR__SHIFT__SI 0x00000000 -#define RE_SI_STAT__DWORD_PACKER_VALID__SHIFT__SI 0x0000000a -#define RE_SI_STAT__NUM_OUTSTAND_BYTES__SHIFT__SI 0x0000000b -#define RE_SI_STAT__NUM_OUTSTAND_REQ__SHIFT__SI 0x00000013 -#define RE_SI_STAT__RECEIVED_FIRST_BYTE_STATUS__SHIFT__SI 0x00000005 -#define RE_SI_STAT__REQ_CNT_ERR__SHIFT__SI 0x00000002 -#define RE_SI_STAT__SPACE_CNT_ERR__SHIFT__SI 0x00000003 -#define RE_SLICE_INFO__CABAC_INIT_IDC__SHIFT__SI 0x00000004 -#define RE_SLICE_INFO__MBAFF_FRAME_FLAG__SHIFT__SI 0x00000003 -#define RE_SLICE_INFO__NON_FMO__SHIFT__SI 0x00000006 -#define RE_SLICE_INFO__SLICE_NUM__SHIFT__SI 0x00000010 -#define RE_SLICE_INFO__SLICE_QPY__SHIFT__SI 0x00000008 -#define RE_SLICE_INFO__SLICE_TYPE__SHIFT__SI 0x00000000 -#define RE_SLICE_INFO__VC1_PQINDEXGT8__SHIFT__SI 0x00000018 -#define RE_SLICE_INFO__VC1_TTFRM__SHIFT__SI 0x0000001e -#define RE_SLICE_INFO__VC1_TTMBF__SHIFT__SI 0x0000001d -#define RE_SLICE_INFO__VC1_TXACFRM2__SHIFT__SI 0x0000001b -#define RE_SLICE_INFO__VC1_TXACFRM__SHIFT__SI 0x00000019 -#define RE_SPS_INFO__CHROMA_FORMAT_IDC__SHIFT__SI 0x00000000 -#define RE_SPS_INFO__MULTI_SC_DIS__SHIFT__SI 0x00000009 -#define RE_SPS_INFO__QI_ERR_EN__SHIFT__SI 0x00000008 -#define RE_SPS_INFO__SC_NOSTOP_DIS__SHIFT__SI 0x0000000a -#define RE_SPS_INFO__STD_VERSION__SHIFT__SI 0x00000004 -#define RE_SPS_INFO__VC1_DQUANT__SHIFT__SI 0x00000001 -#define RE_SPS_INFO__VC1_VSTRANSFORM__SHIFT__SI 0x00000003 -#define RE_SRAM_RM_CTL__RE_M064X039R2M01S00_RME__SHIFT__SI 0x0000000e -#define RE_SRAM_RM_CTL__RE_M064X039R2M01S00_RM__SHIFT__SI 0x0000000a -#define RE_SRAM_RM_CTL__RE_M144X015R2M04S00_RME__SHIFT__SI 0x00000009 -#define RE_SRAM_RM_CTL__RE_M144X015R2M04S00_RM__SHIFT__SI 0x00000005 -#define RE_SRAM_RM_CTL__RE_M464X008R2M04S00_RME__SHIFT__SI 0x00000004 -#define RE_SRAM_RM_CTL__RE_M464X008R2M04S00_RM__SHIFT__SI 0x00000000 -#define RE_SRAM_RM_CTL__RE_WRM__SHIFT__SI 0x0000000f -#define RE_STAT__CABAC_CTL_BUSY__SHIFT__SI 0x00000001 -#define RE_STAT__CABAC_INIT_BUSY__SHIFT__SI 0x00000000 -#define RE_STAT__CABAC_MVD_BUSY__SHIFT__SI 0x00000002 -#define RE_STAT__CABAC_RES_BUSY__SHIFT__SI 0x00000003 -#define RE_STAT__CAVLC_RES_BUSY__SHIFT__SI 0x00000004 -#define RE_STAT__CTXT_INTF_BUSY__SHIFT__SI 0x00000006 -#define RE_STAT__REFILL_SI_FIFO_NOT_EMPTY__SHIFT__SI 0x00000009 -#define RE_STAT__RE_COMMANDS_BUSY__SHIFT__SI 0x00000008 -#define RE_STAT__RE_PES_COMMANDS_BUSY__SHIFT__SI 0x0000000a -#define RE_STAT__RLVL_ENC_BUSY__SHIFT__SI 0x00000005 -#define RE_STAT__SEARCH_START_BUSY__SHIFT__SI 0x00000007 -#define RINGOSC_MASK__MASK__SHIFT 0x00000000 -#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT__SI 0x00000000 -#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT__SI 0x00000002 -#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT__SI 0x00000001 -#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT__SI 0x00000007 -#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT__SI 0x00000000 -#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT__SI 0x00000004 -#define RIRB_SIZE__RIRB_SIZE__SHIFT__SI 0x00000000 -#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT__SI 0x00000000 -#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT__SI 0x00000002 -#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT__SI 0x00000000 -#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT__SI 0x0000000f -#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT__SI 0x00000000 -#define RI_CRC__CRC__SHIFT__SI 0x00000000 -#define RI_CTL__BUS_TIMEOUT_DIS__SHIFT__SI 0x0000000b -#define RI_CTL__BUS_TIMEOUT_LIMIT__SHIFT__SI 0x00000003 -#define RI_CTL__CRC_SEL__SHIFT__SI 0x0000000c -#define RI_CTL__DEBUG_BUS_SEL__SHIFT__SI 0x00000008 -#define RI_CTL__RD_DELAY__SHIFT__SI 0x00000000 -#define RI_DEBUG_INT_STAT__BUS_TIMEOUT_ERR__SHIFT__SI 0x00000000 -#define RI_INT_EN__BUS_TIMEOUT_ERR_EN__SHIFT__SI 0x00000000 -#define RI_INT_STAT__BUS_TIMEOUT_ERR__SHIFT__SI 0x00000000 -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x00000001 -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x00000000 -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x00000002 -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x00000003 -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x00000013 -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x00000000 -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x00000001 -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x0000001b -#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x00000000 -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x00000008 -#define RLC_CGCG_CGLS_CTRL__CGCG_GRBM_CRDT_DELAY__SHIFT__SI 0x00000010 -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x0000001c -#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x00000001 -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x00000002 -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x0000001d -#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT__SI__CI 0x0000001f -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x00000000 -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x00000004 -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x00000010 -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x0000001c -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x00000008 -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0x0000000c -#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x00000000 -#define RLC_CLEARSTATE_RESTORE_BASE__BASE__SHIFT__SI 0x00000000 -#define RLC_CNTL__FORCE_RETRY__SHIFT 0x00000001 -#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x00000002 -#define RLC_CNTL__RESERVED__SHIFT 0x00000008 -#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x00000000 -#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x00000003 -#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x00000004 -#define RLC_CURRENT_CONTEXT__CURRENT_CONTEXT__SHIFT__SI 0x00000000 -#define RLC_CURRENT_CONTEXT__RESERVED__SHIFT__SI 0x0000001c -#define RLC_CU_STATUS__WORK_PENDING_SE0_SH0__SHIFT__SI 0x00000000 -#define RLC_CU_STATUS__WORK_PENDING_SE0_SH1__SHIFT__SI 0x00000008 -#define RLC_CU_STATUS__WORK_PENDING_SE1_SH0__SHIFT__SI 0x00000010 -#define RLC_CU_STATUS__WORK_PENDING_SE1_SH1__SHIFT__SI 0x00000018 -#define RLC_CU_STATUS__WORK_PENDING__SHIFT__CI__VI 0x00000000 -#define RLC_DEBUG_SELECT__F32_SELECT__SHIFT__SI 0x00000008 -#define RLC_DEBUG_SELECT__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_DEBUG_SELECT__RESERVED__SHIFT__SI 0x0000000f -#define RLC_DEBUG_SELECT__SCRATCH_RAM_ONLY__SHIFT__SI 0x0000000e -#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x00000000 -#define RLC_DEBUG__DATA__SHIFT 0x00000000 -#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT__SI__CI 0x00000004 -#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT__SI__CI 0x00000000 -#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT__SI__CI 0x00000001 -#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT__SI__CI 0x00000005 -#define RLC_DRMDMA_CURRENT_CONTEXT__CURRENT_CONTEXT__SHIFT__SI 0x00000000 -#define RLC_DRMDMA_CURRENT_CONTEXT__RESERVED__SHIFT__SI 0x0000001c -#define RLC_DRMDMA_HB_RPTR__HB_RPTR__SHIFT__SI 0x00000000 -#define RLC_DRMDMA_HB_WPTR_MSB_ADDR__HB_WPTR_MSB_ADDR__SHIFT__SI 0x00000000 -#define RLC_DRMDMA_HB_WPTR_MSB_ADDR__RESERVED__SHIFT__SI 0x00000008 -#define RLC_DRMDMA_HB_WPTR__HB_WPTR__SHIFT__SI 0x00000000 -#define RLC_DRMDMA_RL_BASE__RL_BASE__SHIFT__SI 0x00000000 -#define RLC_DRMDMA_RL_SIZE__RESERVED__SHIFT__SI 0x00000004 -#define RLC_DRMDMA_RL_SIZE__RL_SIZE__SHIFT__SI 0x00000000 -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE0_SH0__SHIFT__SI 0x00000000 -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE0_SH1__SHIFT__SI 0x00000008 -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE1_SH0__SHIFT__SI 0x00000010 -#define RLC_DYN_PG_REQUEST__DYN_PG_CU_MASK_SE1_SH1__SHIFT__SI 0x00000018 -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE0_SH0__SHIFT__SI 0x00000000 -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE0_SH1__SHIFT__SI 0x00000008 -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE1_SH0__SHIFT__SI 0x00000010 -#define RLC_DYN_PG_STATUS__DYN_PG_CU_STATUS_SE1_SH1__SHIFT__SI 0x00000018 -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_GCPM_GENERAL_0__DATA__SHIFT__SI 0x00000000 -#define RLC_GCPM_GENERAL_1__DATA__SHIFT__SI 0x00000000 -#define RLC_GCPM_GENERAL_2__DATA__SHIFT__SI 0x00000000 -#define RLC_GCPM_GENERAL_3__DATA__SHIFT__SI 0x00000000 -#define RLC_GCPM_GENERAL_4__DATA__SHIFT__SI 0x00000000 -#define RLC_GCPM_GENERAL_5__DATA__SHIFT__SI 0x00000000 -#define RLC_GCPM_GENERAL_6__DATA__SHIFT__SI 0x00000000 -#define RLC_GCPM_GENERAL_7__DATA__SHIFT__SI 0x00000000 -#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT__CI 0x00000000 -#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT__CI 0x00000008 -#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_DEBUG__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_0__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_1__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_2__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_3__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_4__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_5__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_6__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_GENERAL_7__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_LOG_ADDR__ADDR__SHIFT__CI 0x00000000 -#define RLC_GPM_LOG_CONT__CONT__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_LOG_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT__CI__VI 0x0000000c -#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT__CI__VI 0x00000014 -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT__CI__VI 0x00000010 -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT__CI__VI 0x00000015 -#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT__CI__VI 0x00000004 -#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT__CI__VI 0x00000008 -#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT__CI__VI 0x00000012 -#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT__CI__VI 0x0000000c -#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT__CI__VI 0x00000014 -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT__CI__VI 0x00000010 -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT__CI__VI 0x00000015 -#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT__CI__VI 0x00000004 -#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT__CI__VI 0x00000008 -#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT__CI__VI 0x00000012 -#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT__CI__VI 0x00000009 -#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT__CI__VI 0x00000002 -#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT__CI__VI 0x00000003 -#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT__CI__VI 0x00000001 -#define RLC_GPM_STAT__RESERVED__SHIFT__CI 0x00000004 -#define RLC_GPM_STAT__RLC_BUSY__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT__CI__VI 0x00000004 -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT__CI__VI 0x00000001 -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT__CI__VI 0x00000002 -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT__CI__VI 0x00000003 -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT__CI__VI 0x00000008 -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT__CI__VI 0x00000010 -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT__CI__VI 0x00000018 -#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT__CI__VI 0x0000000c -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_VMID_THREAD0__RESERVED__SHIFT__CI 0x00000004 -#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT__CI__VI 0x00000000 -#define RLC_GPM_VMID_THREAD1__RESERVED__SHIFT__CI 0x00000004 -#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT__CI__VI 0x00000000 -#define RLC_GPR_REG1__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPR_REG2__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x00000006 -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000 -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x00000000 -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x00000000 -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x00000000 -#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT__CI__VI 0x00000000 -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE0_SH0_CU_MASK__SHIFT__SI 0x00000000 -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE0_SH1_CU_MASK__SHIFT__SI 0x00000008 -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE1_SH0_CU_MASK__SHIFT__SI 0x00000010 -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__SE1_SH1_CU_MASK__SHIFT__SI 0x00000018 -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT__CI__VI 0x00000004 -#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x00000001 -#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x00000003 -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x00000002 -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x00000000 -#define RLC_LB_CNTL__RESERVED__SHIFT__CI__VI 0x0000000c -#define RLC_LB_CNTL__RESERVED__SHIFT__SI 0x00000004 -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x00000000 -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x00000000 -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_LB_INIT_CU_MASK__SE0_SH0_CU_MASK__SHIFT__SI 0x00000000 -#define RLC_LB_INIT_CU_MASK__SE0_SH1_CU_MASK__SHIFT__SI 0x00000008 -#define RLC_LB_INIT_CU_MASK__SE1_SH0_CU_MASK__SHIFT__SI 0x00000010 -#define RLC_LB_INIT_CU_MASK__SE1_SH1_CU_MASK__SHIFT__SI 0x00000018 -#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x00000001 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x00000008 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x00000010 -#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x00000000 -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x00000000 -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x00000000 -#define RLC_MAX_PG_CU__SPARE__SHIFT 0x00000008 -#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x0000001c -#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x00000014 -#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x0000001b -#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x00000018 -#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x0000001a -#define RLC_MC_CNTL__RESERVED_B__SHIFT 0x0000000d -#define RLC_MC_CNTL__RESERVED__SHIFT 0x0000001d -#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x00000004 -#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x00000005 -#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x00000009 -#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x00000003 -#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x00000000 -#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x00000002 -#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 -#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x00000001 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x00000000 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x00000010 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x00000008 -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a -#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_PG_ALWAYS_ON_CU_MASK__SE0_SH1_AON_CU_MASK__SHIFT__SI 0x00000008 -#define RLC_PG_ALWAYS_ON_CU_MASK__SE0_SHO_AON_CU_MASK__SHIFT__SI 0x00000000 -#define RLC_PG_ALWAYS_ON_CU_MASK__SE1_SH1_AON_CU_MASK__SHIFT__SI 0x00000018 -#define RLC_PG_ALWAYS_ON_CU_MASK__SE1_SHO_AON_CU_MASK__SHIFT__SI 0x00000010 -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT__CI__VI 0x00000010 -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x00000002 -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x00000000 -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x00000001 -#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT__CI 0x00000018 -#define RLC_PG_CNTL__RESERVED1__SHIFT__CI 0x00000013 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT__CI__VI 0x00000012 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT__CI__VI 0x00000011 -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x00000003 -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT__CI__VI 0x00000010 -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT__CI__VI 0x00000008 -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT__CI__VI 0x00000000 -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT__CI__VI 0x00000010 -#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT__CI__VI 0x00000018 -#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT__CI__VI 0x00000008 -#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_RL_BASE__RL_BASE__SHIFT__SI 0x00000000 -#define RLC_RL_SIZE__RESERVED__SHIFT__SI 0x00000004 -#define RLC_RL_SIZE__RL_SIZE__SHIFT__SI 0x00000000 -#define RLC_SAFE_MODE__MESSAGE__SHIFT__CI__VI 0x00000001 -#define RLC_SAFE_MODE__REQ__SHIFT__CI 0x00000000 -#define RLC_SAFE_MODE__RESERVED__SHIFT__CI 0x00000005 -#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT__SI__CI 0x00000000 -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT__CI__VI 0x00000000 -#define RLC_SERDES_MASTER_BUSY_0__BUSY_MASK__SHIFT__SI 0x00000000 -#define RLC_SERDES_MASTER_BUSY_1__BUSY_MASK__SHIFT__SI 0x00000000 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT__CI__VI 0x00000010 -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT__CI 0x00000017 -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT__CI__VI 0x00000000 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT__CI 0x00000013 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT__CI 0x00000014 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT__CI 0x00000015 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT__CI 0x00000016 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT__CI 0x00000011 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT__CI 0x00000012 -#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x00000000 -#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x00000000 -#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x00000000 -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT__CI__VI 0x00000000 -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT__CI 0x0000000e -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_INDEX__SHIFT__SI 0x0000000c -#define RLC_SERDES_RD_MASTER_INDEX__MASTER_INDEX__SHIFT__SI 0x00000000 -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT__CI__VI 0x0000000b -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT__CI__VI 0x00000006 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT__CI__VI 0x00000009 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT__CI__VI 0x0000000a -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT__CI__VI 0x00000004 -#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT__CI 0x00000010 -#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT__SI 0x0000000e -#define RLC_SERDES_RD_MASTER_INDEX__TTOP_INDEX__SHIFT__SI 0x00000006 -#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT__CI__VI 0x00000000 -#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT__CI 0x00000014 -#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT__CI 0x00000015 -#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT__CI 0x00000011 -#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT__CI 0x00000010 -#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT__CI 0x00000013 -#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT__CI 0x00000012 -#define RLC_SERDES_WR_CTRL__CTRL__SHIFT__SI 0x00000000 -#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT__CI 0x00000016 -#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT__CI 0x00000017 -#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT__CI__VI 0x0000000a -#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT__CI__VI 0x0000000b -#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT__CI__VI 0x00000008 -#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT__CI__VI 0x00000009 -#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT__CI__VI 0x0000000d -#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT__CI__VI 0x0000001c -#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT__CI 0x0000000e -#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT__CI 0x00000018 -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT__CI__VI 0x0000000c -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x00000000 -#define RLC_SERDES_WR_MASTER_MASK_0__MASTER_MASK__SHIFT__SI 0x00000000 -#define RLC_SERDES_WR_MASTER_MASK_1__MASTER_MASK__SHIFT__SI 0x00000000 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT__CI__VI 0x00000010 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT__CI 0x00000017 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT__CI 0x00000013 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT__CI 0x00000014 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT__CI 0x00000015 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT__CI 0x00000016 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT__CI 0x00000011 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT__CI 0x00000012 -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x00000001 -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x00000000 -#define RLC_SMU_PG_CTRL__SPARE__SHIFT__SI__CI 0x00000001 -#define RLC_SMU_PG_CTRL__START_PG__SHIFT__SI__CI 0x00000000 -#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT__SI__CI 0x00000001 -#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT__SI__CI 0x00000000 -#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT__SI__CI 0x00000001 -#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT__SI__CI 0x00000000 -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT__CI__VI 0x0000000f -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT__CI__VI 0x00000010 -#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_DEBUG__DATA__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_INT_CNTL__RESERVED__SHIFT__CI__VI 0x00000001 -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_INT_STATUS__RESERVED__SHIFT__CI__VI 0x00000001 -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT__CI__VI 0x0000000c -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT__CI__VI 0x00000010 -#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT__CI__VI 0x0000000e -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT__CI__VI 0x00000010 -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT__CI__VI 0x0000000b -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT__CI__VI 0x0000001f -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT__CI__VI 0x00000010 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT__CI__VI 0x00000015 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT__CI__VI 0x0000001a -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI 0x00000000 -#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI 0x00000008 -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT__CI__VI 0x00000000 -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT__CI__VI 0x00000008 -#define RLC_SPM_VMID__RESERVED__SHIFT__CI__VI 0x00000004 -#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT__CI__VI 0x00000000 -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT__CI__VI 0x00000000 -#define RLC_STAT__GFX_CLOCK_STATUS__SHIFT__SI 0x00000002 -#define RLC_STAT__GFX_LS_STATUS__SHIFT__SI 0x00000003 -#define RLC_STAT__GFX_POWER_STATUS__SHIFT__SI 0x00000001 -#define RLC_STAT__RESERVED__SHIFT__CI 0x00000003 -#define RLC_STAT__RESERVED__SHIFT__SI__VI 0x00000004 -#define RLC_STAT__RLC_BUSY__SHIFT 0x00000000 -#define RLC_STAT__RLC_GPM_BUSY__SHIFT__CI__VI 0x00000001 -#define RLC_STAT__RLC_SPM_BUSY__SHIFT__CI__VI 0x00000002 -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x00000000 -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x00000008 -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x00000010 -#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x00000018 -#define RLC_THREAD_ENABLE__RESERVED__SHIFT__SI 0x00000004 -#define RLC_THREAD_ENABLE__THREAD0_ENABLE__SHIFT__SI 0x00000000 -#define RLC_THREAD_ENABLE__THREAD1_ENABLE__SHIFT__SI 0x00000001 -#define RLC_THREAD_ENABLE__THREAD2_ENABLE__SHIFT__SI 0x00000002 -#define RLC_THREAD_ENABLE__THREAD3_ENABLE__SHIFT__SI 0x00000003 -#define RLC_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT__SI 0x00000000 -#define RLC_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT__SI 0x00000008 -#define RLC_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT__SI 0x00000010 -#define RLC_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT__SI 0x00000018 -#define RLC_TTOP_DELAY__MEM_SLEEP_DELAY__SHIFT__SI 0x00000018 -#define RLC_TTOP_DELAY__POWER_DOWN_DELAY__SHIFT__SI 0x00000008 -#define RLC_TTOP_DELAY__POWER_UP_DELAY__SHIFT__SI 0x00000000 -#define RLC_TTOP_DELAY__TILE_TOP_PRO_DELAY__SHIFT__SI 0x00000010 -#define RLC_UCODE_ADDR__RESERVED__SHIFT__SI 0x0000000c -#define RLC_UCODE_ADDR__UCODE_ADDR__SHIFT__SI 0x00000000 -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x00000000 -#define RLC_UCODE_DATA__UCODE_DATA__SHIFT__SI 0x00000000 -#define RLC_VMID_THREAD1__RESERVED__SHIFT__SI 0x00000004 -#define RLC_VMID_THREAD1__RLC_VMID__SHIFT__SI 0x00000000 -#define RLC_VMID_THREAD2__RESERVED__SHIFT__SI 0x00000004 -#define RLC_VMID_THREAD2__RLC_VMID__SHIFT__SI 0x00000000 -#define RLC_VMID_THREAD3__RESERVED__SHIFT__SI 0x00000004 -#define RLC_VMID_THREAD3__RLC_VMID__SHIFT__SI 0x00000000 -#define RLC_VMID__RESERVED__SHIFT__SI 0x00000004 -#define RLC_VMID__RLC_VMID__SHIFT__SI 0x00000000 -#define ROLLING_WINDOW_CAC_AGGR_LOWER__AGGREGATE_31_0__SHIFT__SI__CI 0x00000000 -#define ROLLING_WINDOW_CAC_AGGR_UPPER__AGGREGATE_43_32__SHIFT__SI 0x00000000 -#define ROLLING_WINDOW_CAC_AGGR_UPPER__AGGREGATE_47_32__SHIFT__CI 0x00000000 -#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x00000000 -#define ROM_CC_BIF_PINSTRAP__BIF_BIOS_ROM_EN__SHIFT__CI__VI 0x00000003 -#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT__CI__VI 0x00000002 -#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_EN_A__SHIFT__CI__VI 0x00000001 -#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_PIN__SHIFT__CI__VI 0x00000005 -#define ROM_CC_BIF_PINSTRAP__BIF_SMBUS_DIS__SHIFT__CI__VI 0x00000004 -#define ROM_CC_BIF_PINSTRAP__BIF_TX_CFG_DRV_FULL_SWING__SHIFT__CI__VI 0x0000000b -#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_PIN__SHIFT__CI__VI 0x00000009 -#define ROM_CC_STRAP_PIN_REG0__BPHYC_STRAP_TX_DEEMPH_EN__SHIFT__CI__VI 0x00000001 -#define ROM_CC_STRAP_PIN_REG0__BPHYC_STRAP_TX_FULL_SWING__SHIFT__CI__VI 0x00000002 -#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x00000002 -#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x00000010 -#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x00000008 -#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x00000001 -#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x0000001c -#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x00000018 -#define ROM_DATA__ROM_DATA__SHIFT 0x00000000 -#define ROM_INDEX__ROM_INDEX__SHIFT 0x00000000 -#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define ROM_START__ROM_START__SHIFT 0x00000000 -#define ROM_STATUS__ROM_BUSY__SHIFT 0x00000000 -#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x00000010 -#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x00000000 -#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x00000012 -#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x00000008 -#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x00000000 -#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x00000000 -#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x00000000 -#define S0_S1_VID_DC_SMIO_CNTL__S0_SCL_DATA__SHIFT 0x00000010 -#define S0_S1_VID_DC_SMIO_CNTL__S0_SDA_DATA__SHIFT 0x00000000 -#define S0_S1_VID_DC_SMIO_CNTL__S1_SCL_DATA__SHIFT 0x00000011 -#define S0_S1_VID_DC_SMIO_CNTL__S1_SDA_DATA__SHIFT 0x00000001 -#define S0_S1_VID_DC_SMIO_CNTL__SCL_EN__SHIFT 0x00000018 -#define S0_S1_VID_DC_SMIO_CNTL__SDA_EN__SHIFT 0x00000008 -#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x00000000 -#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x00000000 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DCCIF_DC_BUSY__SHIFT__SI 0x00000006 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DCP_CURSOR_BUSY__SHIFT__SI 0x00000004 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DCP_ICON_BUSY__SHIFT__SI 0x00000005 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_G_DCP_CLOCK_ON__SHIFT__SI 0x00000013 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_G_SCL12_CLOCK_ON__SHIFT__SI 0x00000015 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_G_VGA_CLOCK_ON__SHIFT__SI 0x0000000f -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_M_CLOCK_ON__SHIFT__SI 0x00000008 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_CLOCK_ON__SHIFT__SI 0x0000000a -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_RBBMIF_BUSY__SHIFT__SI 0x00000002 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_RBBMIF_CLOCK_ON__SHIFT__SI 0x00000003 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_DISP_CLK_R_VGA_CLOCK_ON__SHIFT__SI 0x00000010 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_DISP_CLK_G_DCP_BUSY__SHIFT__SI 0x00000011 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_DISP_CLK_G_VGA_BUSY__SHIFT__SI 0x0000000d -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_DISP_CLK_R_VGA_BUSY__SHIFT__SI 0x0000000c -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_MEMCLK_BUSY__SHIFT__SI 0x00000007 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_GATED_REGCLK_DISP_BUSY__SHIFT__SI 0x00000009 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_PM_DISABLE__SHIFT__SI 0x00000000 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RBBMIF_VGAREG_BUSY__SHIFT__SI 0x0000000b -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RBBM_REGCLK_ACTIVE__SHIFT__SI 0x00000001 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RUN_CLK_DEBUG_DCP_DISP_CLK__SHIFT__SI 0x00000012 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RUN_CLK_DEBUG_SCL_DISP_CLK__SHIFT__SI 0x00000014 -#define SCG_DEBUG_01__IDA0_DISP_CLK_GATER_RUN_CLK_DEBUG_VGA_DISP_CLK__SHIFT__SI 0x0000000e -#define SCG_DEBUG_02__IDA1_DISP_CLK_DCCIF_SOFT_RESET__SHIFT__SI 0x0000000d -#define SCG_DEBUG_02__IDA1_DISP_CLK_DCP_PIXPIPE_SOFT_RESET__SHIFT__SI 0x00000011 -#define SCG_DEBUG_02__IDA1_DISP_CLK_DCP_REQ_SOFT_RESET__SHIFT__SI 0x0000000f -#define SCG_DEBUG_02__IDA1_DISP_CLK_G_DCP_RST__SHIFT__SI 0x00000012 -#define SCG_DEBUG_02__IDA1_DISP_CLK_G_VGA_RST__SHIFT__SI 0x00000004 -#define SCG_DEBUG_02__IDA1_DISP_CLK_M_DCCIF_RST__SHIFT__SI 0x0000000e -#define SCG_DEBUG_02__IDA1_DISP_CLK_P_DCP_RST__SHIFT__SI 0x00000010 -#define SCG_DEBUG_02__IDA1_DISP_CLK_P_DC_RST__SHIFT__SI 0x0000000b -#define SCG_DEBUG_02__IDA1_DISP_CLK_P_VGA_RST__SHIFT__SI 0x00000002 -#define SCG_DEBUG_02__IDA1_DISP_CLK_R_RBBMIF_RST__SHIFT__SI 0x0000000a -#define SCG_DEBUG_02__IDA1_DISP_CLK_R_RST__SHIFT__SI 0x0000000c -#define SCG_DEBUG_02__IDA1_DISP_CLK_R_VGA_RST__SHIFT__SI 0x00000003 -#define SCG_DEBUG_02__IDA1_DISP_CLK_VGA_SOFT_RESET__SHIFT__SI 0x00000001 -#define SCG_DEBUG_02__IDA1_RBBM_DISP_SOFT_RESET__SHIFT__SI 0x00000009 -#define SCG_DEBUG_02__IDA1_RBBM_VGA_SOFT_RESET__SHIFT__SI 0x00000000 -#define SCG_DEBUG_03__IDA2_ONESHOT_CLOCKING_MODE__SHIFT__SI 0x00000018 -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_ONE_SHOT_STOP__SHIFT__SI 0x00000002 -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_RUN_CLK__SHIFT__SI 0x00000001 -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_RUN_CLOCK_COUNT__SHIFT__SI 0x00000004 -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_TRIGGER_EVENT_OCCURRED__SHIFT__SI 0x00000003 -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_WTRIG_PRE_SCG_ONE_SHOT_RUN_CLK__SHIFT__SI 0x0000001b -#define SCG_DEBUG_03__IDA2_ONESHOT_DCP_WTRIG_RUN_CLK_CURRENT_CLK__SHIFT__SI 0x00000000 -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_ONE_SHOT_STOP__SHIFT__SI 0x0000000e -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_RUN_CLK__SHIFT__SI 0x0000000d -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_RUN_CLOCK_COUNT__SHIFT__SI 0x00000010 -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_TRIGGER_EVENT_OCCURRED__SHIFT__SI 0x0000000f -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_WTRIG_PRE_DCCG_ONE_SHOT_RUN_CLK__SHIFT__SI 0x0000001c -#define SCG_DEBUG_03__IDA2_ONESHOT_SCL_WTRIG_RUN_CLK_CURRENT_CLK__SHIFT__SI 0x0000000c -#define SCG_DEBUG_03__IDA2_ONESHOT_TRIGGER_EN__SHIFT__SI 0x0000001a -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_ONE_SHOT_STOP__SHIFT__SI 0x00000002 -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_RUN_CLK__SHIFT__SI 0x00000001 -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_RUN_CLOCK_COUNT__SHIFT__SI 0x00000004 -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_TRIGGER_EVENT_OCCURRED__SHIFT__SI 0x00000003 -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_WTRIG_PRE_SCG_ONE_SHOT_RUN_CLK__SHIFT__SI 0x0000000c -#define SCG_DEBUG_04__IDA3_ONESHOT_VGA_WTRIG_RUN_CLK_CURRENT_CLK__SHIFT__SI 0x00000000 -#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT__SI 0x00000004 -#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT__SI 0x00000000 -#define SCLK_DCI_SOFT_RESET__SCLK_AZ_SOFT_RESET__SHIFT__SI 0x00000001 -#define SCLK_DCI_SOFT_RESET__SCLK_DCI_SOFT_RESET__SHIFT__SI 0x00000000 -#define SCLK_DCO_SOFT_RESET__SCLK_DIGA_SOFT_RESET__SHIFT__SI 0x00000000 -#define SCLK_DCO_SOFT_RESET__SCLK_DIGB_SOFT_RESET__SHIFT__SI 0x00000001 -#define SCLK_DCO_SOFT_RESET__SCLK_DIGC_SOFT_RESET__SHIFT__SI 0x00000002 -#define SCLK_DCO_SOFT_RESET__SCLK_DIGD_SOFT_RESET__SHIFT__SI 0x00000003 -#define SCLK_DCO_SOFT_RESET__SCLK_DIGE_SOFT_RESET__SHIFT__SI 0x00000004 -#define SCLK_DCO_SOFT_RESET__SCLK_DIGF_SOFT_RESET__SHIFT__SI 0x00000005 -#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT__CI__VI 0x00000009 -#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT__CI__VI 0x00000008 -#define SCLK_DEEP_SLEEP_CNTL2__DRM_BUSY_MASK__SHIFT__CI__VI 0x00000005 -#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT__CI__VI 0x00000001 -#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT__CI__VI 0x00000006 -#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT__CI__VI 0x00000003 -#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT__CI__VI 0x00000018 -#define SCLK_DEEP_SLEEP_CNTL2__LB_UNDERFLOW_PROTECT_EN__SHIFT__CI__VI 0x00000014 -#define SCLK_DEEP_SLEEP_CNTL2__MC2SRBM_BUSY_MASK__SHIFT__CI 0x0000000e -#define SCLK_DEEP_SLEEP_CNTL2__MC3SRBM_BUSY_MASK__SHIFT__CI 0x0000000f -#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT__CI__VI 0x00000004 -#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT__CI__VI 0x00000000 -#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT__CI__VI 0x00000002 -#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT__CI__VI 0x0000000c -#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT__CI__VI 0x0000000d -#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT__CI__VI 0x00000007 -#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT__CI__VI 0x00000015 -#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT__CI__VI 0x0000000a -#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT__CI__VI 0x0000000b -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000000 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT__CI__VI 0x0000000a -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT__CI__VI 0x0000000b -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT__CI__VI 0x0000000c -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT__CI__VI 0x0000000d -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT__CI__VI 0x0000000e -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT__CI__VI 0x0000000f -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000001 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000002 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000003 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000004 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000005 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000006 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000007 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000008 -#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT__CI__VI 0x00000009 -#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT__CI__VI 0x00000012 -#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT__CI__VI 0x0000001e -#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT__CI__VI 0x00000013 -#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT__CI__VI 0x0000001b -#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT__CI__VI 0x00000000 -#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT__CI__VI 0x0000001f -#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT__CI__VI 0x0000001a -#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT__CI__VI 0x00000004 -#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT__CI__VI 0x0000001c -#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT__CI__VI 0x00000015 -#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT__CI__VI 0x00000016 -#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT__CI__VI 0x00000017 -#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT__CI__VI 0x00000003 -#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT__CI__VI 0x00000010 -#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT__CI__VI 0x00000011 -#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT__CI__VI 0x00000019 -#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT__CI__VI 0x00000018 -#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT__CI__VI 0x00000014 -#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT__CI__VI 0x0000001d -#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT__CI__VI 0x00000000 -#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT__CI__VI 0x00000003 -#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT__CI__VI 0x00000011 -#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT__CI__VI 0x00000010 -#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT__CI__VI 0x00000014 -#define SCLK_MIN_DIV__FRACV__SHIFT__CI__VI 0x00000000 -#define SCLK_MIN_DIV__INTV__SHIFT__CI__VI 0x0000000c -#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT__CI__VI 0x0000000f -#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT__CI__VI 0x00000016 -#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT__CI__VI 0x00000017 -#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT__CI__VI 0x00000015 -#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x00000007 -#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0x0000000e -#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT__CI__VI 0x00000002 -#define SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL__SHIFT__SI 0x00000005 -#define SCLK_PWRMGT_CNTL__FIR_RESET__SHIFT__SI 0x00000004 -#define SCLK_PWRMGT_CNTL__FIR_TREND_MODE__SHIFT__SI 0x00000006 -#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x0000001c -#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x0000001d -#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0x0000000a -#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x00000008 -#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0x0000000b -#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0x0000000c -#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0x0000000d -#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x00000009 -#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT__CI__VI 0x0000001e -#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT__CI__VI 0x0000001f -#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x00000010 -#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT__CI__VI 0x00000006 -#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT__CI__VI 0x00000018 -#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT__CI__VI 0x00000004 -#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT__CI__VI 0x00000005 -#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x00000001 -#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x00000000 -#define SCLK_PWRMGT_CNTL__SPARE__SHIFT__SI 0x00000002 -#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT__CI__VI 0x00000019 -#define SCLK_STARTUP_DID__SCLK_STARTUP_DID__SHIFT__CI__VI 0x00000000 -#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT__SI 0x00000000 -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_HORZ_CALC_AUTO_COEF_EN__SHIFT__SI 0x00000018 -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_HORZ_CALC_AUTO_RATIO_EN__SHIFT__SI 0x00000010 -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_VERT_CALC_AUTO_COEF_EN__SHIFT__SI 0x00000008 -#define SCL_AUTOMATIC_MODE_CONTROL__SCL_VERT_CALC_AUTO_RATIO_EN__SHIFT__SI 0x00000000 -#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT__SI 0x00000000 -#define SCL_COEFRAM__ID09_SCL_HOST_CR_FILTER_OFFSET__SHIFT__SI 0x00000005 -#define SCL_COEFRAM__ID09_SCL_HOST_CR_FILTER_TYPE__SHIFT__SI 0x00000003 -#define SCL_COEFRAM__ID09_SCL_HOST_CR_REQUEST_TYPE__SHIFT__SI 0x00000001 -#define SCL_COEFRAM__ID09_SCL_HOST_CR_REQUEST__SHIFT__SI 0x00000000 -#define SCL_COEFRAM__ID09_SCL_SCL_CR_FILTER_OFFSET_0__SHIFT__SI 0x00000011 -#define SCL_COEFRAM__ID09_SCL_SCL_CR_FILTER_OFFSET_1__SHIFT__SI 0x0000001a -#define SCL_COEFRAM__ID09_SCL_SCL_CR_FILTER_TYPE_0__SHIFT__SI 0x0000000f -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_0__SHIFT__SI 0x0000000c -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_1__SHIFT__SI 0x00000017 -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_TYPE_0__SHIFT__SI 0x0000000d -#define SCL_COEFRAM__ID09_SCL_SCL_CR_REQUEST_TYPE_1__SHIFT__SI 0x00000018 -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT__SI 0x00000008 -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT__SI 0x00000000 -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT__SI 0x00000010 -#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT__SI 0x0000000c -#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT__SI 0x00000010 -#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT__SI 0x00000008 -#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT__SI 0x00000000 -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT__SI 0x0000000f -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT__SI 0x00000000 -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT__SI 0x0000001f -#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT__SI 0x00000010 -#define SCL_CONTROL1__ID00_SCL_ADVANCE_FILTER_POS__SHIFT__SI 0x00000017 -#define SCL_CONTROL1__ID00_SCL_BFILT_BFKP_STATE__SHIFT__SI 0x0000000c -#define SCL_CONTROL1__ID00_SCL_BFILT_POS_STATE__SHIFT__SI 0x0000000e -#define SCL_CONTROL1__ID00_SCL_CLOCK_V_ACTIVE__SHIFT__SI 0x0000001c -#define SCL_CONTROL1__ID00_SCL_COEFRAM_BUSY__SHIFT__SI 0x0000001e -#define SCL_CONTROL1__ID00_SCL_H_FILT_POS_STATE__SHIFT__SI 0x0000000a -#define SCL_CONTROL1__ID00_SCL_H_READ_PTR_INIT_STATE__SHIFT__SI 0x00000011 -#define SCL_CONTROL1__ID00_SCL_H_SCALE_ACTIVE__SHIFT__SI 0x00000014 -#define SCL_CONTROL1__ID00_SCL_H_SOURCE_ACTIVE__SHIFT__SI 0x00000013 -#define SCL_CONTROL1__ID00_SCL_LB_EOL__SHIFT__SI 0x00000016 -#define SCL_CONTROL1__ID00_SCL_LB_SOF__SHIFT__SI 0x00000015 -#define SCL_CONTROL1__ID00_SCL_LC_STATE__SHIFT__SI 0x00000000 -#define SCL_CONTROL1__ID00_SCL_SCALE_ACTIVE__SHIFT__SI 0x0000001d -#define SCL_CONTROL1__ID00_SCL_SCLK_G_SCL_ON__SHIFT__SI 0x0000001f -#define SCL_CONTROL1__ID00_SCL_VCG_REQUEST_DONE__SHIFT__SI 0x0000001b -#define SCL_CONTROL1__ID00_SCL_VCOEFGEN_STATE__SHIFT__SI 0x00000018 -#define SCL_CONTROL1__ID00_SCL_V_FILT_POS_STATE__SHIFT__SI 0x00000008 -#define SCL_CONTROL2__ID01_SCL_END_LINE__SHIFT__SI 0x00000015 -#define SCL_CONTROL2__ID01_SCL_LB_EOL__SHIFT__SI 0x00000011 -#define SCL_CONTROL2__ID01_SCL_LB_SOF__SHIFT__SI 0x00000010 -#define SCL_CONTROL2__ID01_SCL_RBBMIF_READY__SHIFT__SI 0x0000000f -#define SCL_CONTROL2__ID01_SCL_READY_STATE__SHIFT__SI 0x0000000c -#define SCL_CONTROL2__ID01_SCL_START_LINE__SHIFT__SI 0x00000014 -#define SCL_CONTROL2__ID01_SCL_V_UPDATE__SHIFT__SI 0x00000000 -#define SCL_CONTROL__SCL_SWAP_RED_BLUE__SHIFT__SI 0x00000010 -#define SCL_CRC_CURRENT__SCL_CRC_CURRENT__SHIFT__SI 0x00000000 -#define SCL_CRC_ENABLE__SCL_CRC_ENABLE__SHIFT__SI 0x00000000 -#define SCL_CRC_LAST__SCL_CRC_LAST__SHIFT__SI 0x00000000 -#define SCL_CRC_MASK__SCL_CRC_MASK__SHIFT__SI 0x00000000 -#define SCL_CRC_SOURCE_SEL__SCL_CRC_SOURCE_SEL__SHIFT__SI 0x00000000 -#define SCL_CRTC_INTERFACE__ID03_CRTC_SCL_READ_REQUEST__SHIFT__SI 0x00000000 -#define SCL_CRTC_INTERFACE__ID03_SCL_CRTC_PIX_B_CB__SHIFT__SI 0x00000015 -#define SCL_CRTC_INTERFACE__ID03_SCL_CRTC_PIX_G_Y__SHIFT__SI 0x00000001 -#define SCL_CRTC_INTERFACE__ID03_SCL_CRTC_PIX_R_CR__SHIFT__SI 0x0000000b -#define SCL_CRTC_INTERFACE__ID03_SCL_LB_EOL__SHIFT__SI 0x0000001f -#define SCL_DEBUG_ID__SCL_DEBUG_ID__SHIFT__SI 0x00000000 -#define SCL_DEBUG__SCL_DEBUG__SHIFT__SI 0x00000000 -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_CONT_EN__SHIFT__SI 0x00000008 -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_DE_ONLY__SHIFT__SI 0x00000010 -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_EN__SHIFT__SI 0x00000004 -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_CRC_LINE_EN__SHIFT__SI 0x0000000c -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_EN__SHIFT__SI 0x00000000 -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_LINE_WIDTH_EXCEEDED_ACK__SHIFT__SI 0x00000018 -#define SCL_DTMTEST_CNTL__SCL_DTMTEST_LINE_WIDTH_EXCEEDED__SHIFT__SI 0x00000014 -#define SCL_DTMTEST_CRC_BLUE__SCL_DTMTEST_CRC_BLUE_MASK__SHIFT__SI 0x00000000 -#define SCL_DTMTEST_CRC_BLUE__SCL_DTMTEST_CRC_SIG_BLUE__SHIFT__SI 0x00000010 -#define SCL_DTMTEST_CRC_GREEN__SCL_DTMTEST_CRC_GREEN_MASK__SHIFT__SI 0x00000000 -#define SCL_DTMTEST_CRC_GREEN__SCL_DTMTEST_CRC_SIG_GREEN__SHIFT__SI 0x00000010 -#define SCL_DTMTEST_CRC_RED__SCL_DTMTEST_CRC_RED_MASK__SHIFT__SI 0x00000000 -#define SCL_DTMTEST_CRC_RED__SCL_DTMTEST_CRC_SIG_RED__SHIFT__SI 0x00000010 -#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT__SI 0x00000004 -#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT__SI 0x00000000 -#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT__SI 0x0000000c -#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT__SI 0x00000008 -#define SCL_HFILT_COEF__ID08_SCL_ADVANCE_FILTER_POS__SHIFT__SI 0x00000015 -#define SCL_HFILT_COEF__ID08_SCL_HCG_HF_COEF_RGB_Y_0__SHIFT__SI 0x00000000 -#define SCL_HFILT_COEF__ID08_SCL_HCG_HF_COEF_RGB_Y_1__SHIFT__SI 0x0000000c -#define SCL_HFILT_COEF__ID08_SCL_H_SCALE_ACTIVE__SHIFT__SI 0x00000016 -#define SCL_HFILT_COEF__ID08_SCL_LB_EOL__SHIFT__SI 0x00000017 -#define SCL_HFILT_COEF__ID08_SCL_SOURCE_X_COUNT_Y_LSB7__SHIFT__SI 0x00000018 -#define SCL_HFILT_IO__ID07_SCL_ADVANCE_FILTER_POS__SHIFT__SI 0x0000001c -#define SCL_HFILT_IO__ID07_SCL_HF_RF_G_Y__SHIFT__SI 0x00000002 -#define SCL_HFILT_IO__ID07_SCL_HF_RF_READY__SHIFT__SI 0x00000000 -#define SCL_HFILT_IO__ID07_SCL_H_PIX_VALID__SHIFT__SI 0x00000018 -#define SCL_HFILT_IO__ID07_SCL_H_SCALE_ACTIVE__SHIFT__SI 0x0000001d -#define SCL_HFILT_IO__ID07_SCL_H_SOURCE_ACTIVE__SHIFT__SI 0x00000019 -#define SCL_HFILT_IO__ID07_SCL_LB_EOL__SHIFT__SI 0x00000017 -#define SCL_HFILT_IO__ID07_SCL_NUM_BLACK_PIX_C__SHIFT__SI 0x00000011 -#define SCL_HFILT_IO__ID07_SCL_NUM_BLACK_PIX_Y__SHIFT__SI 0x0000000c -#define SCL_HFILT_IO__ID07_SCL_RF_HF_SEND__SHIFT__SI 0x00000001 -#define SCL_HFILT_IO__ID07_SCL_SCLK_G_SCL_ON__SHIFT__SI 0x0000001f -#define SCL_HFILT_IO__ID07_SCL_SOURCE_LINE_ENDED__SHIFT__SI 0x0000001a -#define SCL_HIGH_PASS_FILTER_CONTROL__SCL_HP_SCALE_FACTOR_FRAC__SHIFT__SI 0x0000000b -#define SCL_HIGH_PASS_FILTER_CONTROL__SCL_HP_SCALE_FACTOR_INT__SHIFT__SI 0x00000010 -#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_ALPHA_COEF_EN__SHIFT__SI 0x00000008 -#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_ALPHA_COEF_MODE__SHIFT__SI 0x00000010 -#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT__SI 0x00000000 -#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR__SHIFT__SI 0x00000000 -#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR__SHIFT__SI 0x00000010 -#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y__SHIFT__SI 0x00000000 -#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y__SHIFT__SI 0x00000010 -#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT__SI 0x00000000 -#define SCL_H_COUNTERS__ID0B_SCL_HACCUM_C__SHIFT__SI 0x0000000c -#define SCL_H_COUNTERS__ID0B_SCL_HACCUM_Y__SHIFT__SI 0x00000000 -#define SCL_H_COUNTERS__ID0B_SCL_LB_EOL__SHIFT__SI 0x0000001f -#define SCL_H_COUNTERS__ID0B_SCL_LB_SOF__SHIFT__SI 0x0000001e -#define SCL_H_COUNTERS__ID0B_SCL_SOURCE_X_COUNT_MSB6__SHIFT__SI 0x00000018 -#define SCL_LB_INTERFACE__ID02_LB_SCL_RTR__SHIFT__SI 0x00000003 -#define SCL_LB_INTERFACE__ID02_LB_SCL_TAPNUM__SHIFT__SI 0x0000000c -#define SCL_LB_INTERFACE__ID02_SCL_ALU_AUTOCAL_DONE__SHIFT__SI 0x00000012 -#define SCL_LB_INTERFACE__ID02_SCL_LB_EOL__SHIFT__SI 0x00000001 -#define SCL_LB_INTERFACE__ID02_SCL_LB_NUMTAP_IGNORE__SHIFT__SI 0x00000008 -#define SCL_LB_INTERFACE__ID02_SCL_LB_RND_SCR__SHIFT__SI 0x0000000f -#define SCL_LB_INTERFACE__ID02_SCL_LB_RTS__SHIFT__SI 0x00000002 -#define SCL_LB_INTERFACE__ID02_SCL_LB_SHIFT_IN_BLACK__SHIFT__SI 0x00000007 -#define SCL_LB_INTERFACE__ID02_SCL_LB_SOF__SHIFT__SI 0x00000000 -#define SCL_LB_INTERFACE__ID02_SCL_LB_TAP_SHIFT__SHIFT__SI 0x00000004 -#define SCL_LOW_PASS_FILTER_CONTROL__SCL_LP_SCALE_FACTOR_FRAC__SHIFT__SI 0x0000000b -#define SCL_LOW_PASS_FILTER_CONTROL__SCL_LP_SCALE_FACTOR_INT__SHIFT__SI 0x00000010 -#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT__SI 0x00000008 -#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT__SI 0x00000000 -#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT__SI 0x00000007 -#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT__SI 0x00000004 -#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT__SI 0x00000000 -#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT__SI 0x00000000 -#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT__SI 0x00000000 -#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT__SI 0x00000010 -#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT__SI 0x00000000 -#define SCL_ONE_SHOT_WATERMARK__SCL_ONE_SHOT_WATERMARK__SHIFT__SI 0x00000000 -#define SCL_RBBMIF_RDWR_TIMEOUT__DISP_RBBMIF_RD_WR_TIMEOUT_DIS__SHIFT__SI 0x00000000 -#define SCL_READBBUF_IO__ID04_SCL_H_REPLICATION_FACTOR__SHIFT__SI 0x00000010 -#define SCL_READBBUF_IO__ID04_SCL_H_SOURCE_ACTIVE__SHIFT__SI 0x00000014 -#define SCL_READBBUF_IO__ID04_SCL_LB_EOL__SHIFT__SI 0x00000017 -#define SCL_READBBUF_IO__ID04_SCL_PIX_ADVANCE__SHIFT__SI 0x0000001c -#define SCL_READBBUF_IO__ID04_SCL_RB_RF_PIX_G__SHIFT__SI 0x00000002 -#define SCL_READBBUF_IO__ID04_SCL_RB_RF_READY__SHIFT__SI 0x00000000 -#define SCL_READBBUF_IO__ID04_SCL_RB_VF_READY__SHIFT__SI 0x0000000c -#define SCL_READBBUF_IO__ID04_SCL_RF_RB_SEND__SHIFT__SI 0x00000001 -#define SCL_READBBUF_IO__ID04_SCL_VF_RB_SEND__SHIFT__SI 0x0000000d -#define SCL_READBBUF_IO__ID04_SCL_V_SCALE_ACTIVE__SHIFT__SI 0x00000018 -#define SCL_SCALER_ENABLE__SCL_SCALE_EN__SHIFT__SI 0x00000000 -#define SCL_TAP_CONTROL__SCL_HORZ_NUM_OF_TAPS__SHIFT__SI 0x00000008 -#define SCL_TAP_CONTROL__SCL_VERT_NUM_OF_TAPS__SHIFT__SI 0x00000000 -#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_ACK__SHIFT__SI 0x00000008 -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_FLAG__SHIFT__SI 0x00000000 -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_INT_STATUS__SHIFT__SI 0x00000010 -#define SCL_UNDERFLOW_STATUS__SCL_DATA_UNDERFLOW_MASK__SHIFT__SI 0x0000000c -#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT__SI 0x00000010 -#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT__SI 0x00000000 -#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT__SI 0x00000008 -#define SCL_VERT_FILTER_CONTROL__SCL_BAND_FILTER_BYPASS__SHIFT__SI 0x00000018 -#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_ALPHA_COEF_EN__SHIFT__SI 0x00000008 -#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_ALPHA_COEF_MODE__SHIFT__SI 0x00000010 -#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT__SI 0x00000000 -#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT__SI 0x00000000 -#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT__SI 0x00000010 -#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT__SI 0x00000000 -#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT__SI 0x00000010 -#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT__SI 0x00000000 -#define SCL_VFILT_COEF__ID06_SCL_LB_EOL__SHIFT__SI 0x00000017 -#define SCL_VFILT_COEF__ID06_SCL_VCG_REQUEST_DONE__SHIFT__SI 0x00000018 -#define SCL_VFILT_COEF__ID06_SCL_VCG_VF_COEF_HP__SHIFT__SI 0x0000000c -#define SCL_VFILT_COEF__ID06_SCL_VCG_VF_COEF_LP__SHIFT__SI 0x00000000 -#define SCL_VFILT_IO__ID05_SCL_HF_VF_SEND__SHIFT__SI 0x00000001 -#define SCL_VFILT_IO__ID05_SCL_LB_EOL__SHIFT__SI 0x00000017 -#define SCL_VFILT_IO__ID05_SCL_PIPE_START_TAPNUM__SHIFT__SI 0x00000014 -#define SCL_VFILT_IO__ID05_SCL_SCLK_G_SCL_ON__SHIFT__SI 0x0000001f -#define SCL_VFILT_IO__ID05_SCL_VF_HF_PIX_G_Y__SHIFT__SI 0x00000002 -#define SCL_VFILT_IO__ID05_SCL_VF_HF_READY__SHIFT__SI 0x00000000 -#define SCL_VFILT_IO__ID05_SCL_V_PIX_VALID__SHIFT__SI 0x00000010 -#define SCL_V_COUNTERS__ID0A_SCL_LB_EOL__SHIFT__SI 0x00000011 -#define SCL_V_COUNTERS__ID0A_SCL_LB_SOF__SHIFT__SI 0x00000010 -#define SCL_V_COUNTERS__ID0A_SCL_SOURCE_Y_COUNT__SHIFT__SI 0x00000013 -#define SCL_V_COUNTERS__ID0A_SCL_VACCUM__SHIFT__SI 0x00000000 -#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT__CI__VI 0x00000000 -#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT__SI 0x00000000 -#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 -#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 -#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 -#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 -#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 -#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 -#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 -#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 -#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT__CI__VI 0x00000010 -#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT__CI__VI 0x00000000 -#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT__SI 0x00000010 -#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT__SI 0x00000000 -#define SD1_CC_EDS_LEVEL_CNTL__SD1_VBI_CC_EDS_LEVEL__SHIFT__SI 0x00000000 -#define SD1_CHROMA_MOD_CNTL__SD1_CHROMA_PRE_MOD_DELAY_EN__SHIFT__SI 0x0000001b -#define SD1_CHROMA_MOD_CNTL__SD1_COL_SC_SECOND_CORR_EN__SHIFT__SI 0x0000001a -#define SD1_CHROMA_MOD_CNTL__SD1_FORCE_BLACK_WHITE__SHIFT__SI 0x0000001d -#define SD1_CHROMA_MOD_CNTL__SD1_FORCE_BURST_ALWAYS__SHIFT__SI 0x0000001e -#define SD1_CHROMA_MOD_CNTL__SD1_UVFLT_EN__SHIFT__SI 0x0000001f -#define SD1_CHROMA_MOD_CNTL__SD1_U_BURST_LEVEL__SHIFT__SI 0x00000000 -#define SD1_CHROMA_MOD_CNTL__SD1_V_BURST_LEVEL__SHIFT__SI 0x00000010 -#define SD1_CHROMA_OFFSET__SD1_CHROMA_OFFSET__SHIFT__SI 0x00000000 -#define SD1_COL_SC_DENOMIN__SD1_COL_SC_DENOMIN__SHIFT__SI 0x00000000 -#define SD1_COL_SC_INC_CORR__SD1_COL_SC_INC_CORR__SHIFT__SI 0x00000000 -#define SD1_COL_SC_INC__SD1_COL_SC_INC__SHIFT__SI 0x00000000 -#define SD1_COL_SC_PHASE_CNTL__SD1_COL_SC_PHASE_INIT__SHIFT__SI 0x00000000 -#define SD1_CRC_CNTL__SD1_CRC_DATAIN_SEL__SHIFT__SI 0x00000004 -#define SD1_CRC_CNTL__SD1_CRC_EN__SHIFT__SI 0x00000000 -#define SD1_CRC_CNTL__SD1_PROGRESSIVE_MODE_CRC__SHIFT__SI 0x00000008 -#define SD1_CRC_CNTL__SD1_RST_SC_ON_FSYNC_4CRC__SHIFT__SI 0x00000007 -#define SD1_CRTC_HV_START__SD1_CRTC_H_START__SHIFT__SI 0x00000000 -#define SD1_CRTC_HV_START__SD1_CRTC_V_START__SHIFT__SI 0x00000010 -#define SD1_CRTC_TV_FRAMESTART_CNTL__SD1_CRTC_TV_FRAMESTART_FREQ__SHIFT__SI 0x00000000 -#define SD1_FORCE_DAC_DATA__SD1_FORCE_DAC_DATA__SHIFT__SI 0x00000000 -#define SD1_LUMA_BLANK_SETUP_LEVELS__SD1_BLANK_LEVEL__SHIFT__SI 0x00000000 -#define SD1_LUMA_BLANK_SETUP_LEVELS__SD1_SETUP_LEVEL__SHIFT__SI 0x00000010 -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_COMB_EN__SHIFT__SI 0x00000000 -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_COMB_LINE_SEL__SHIFT__SI 0x00000008 -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_DISABLE_FIRST_LAST__SHIFT__SI 0x00000001 -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_P2__SHIFT__SI 0x00000010 -#define SD1_LUMA_COMB_FILT_CNTL1__SD1_P3__SHIFT__SI 0x00000018 -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P4__SHIFT__SI 0x00000000 -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P5__SHIFT__SI 0x00000008 -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P6__SHIFT__SI 0x00000010 -#define SD1_LUMA_COMB_FILT_CNTL2__SD1_P7__SHIFT__SI 0x00000018 -#define SD1_LUMA_COMB_FILT_CNTL3__SD1_P10__SHIFT__SI 0x00000000 -#define SD1_LUMA_COMB_FILT_CNTL3__SD1_P8__SHIFT__SI 0x00000008 -#define SD1_LUMA_COMB_FILT_CNTL3__SD1_P9__SHIFT__SI 0x00000014 -#define SD1_LUMA_COMB_FILT_CNTL4__SD1_FORCE_P9__SHIFT__SI 0x00000008 -#define SD1_LUMA_COMB_FILT_CNTL4__SD1_P11__SHIFT__SI 0x00000000 -#define SD1_LUMA_FILT_CNTL__SD1_COMPY_OUT_BLEND__SHIFT__SI 0x00000008 -#define SD1_LUMA_FILT_CNTL__SD1_COMP_PASSTHRU_BLEND__SHIFT__SI 0x00000010 -#define SD1_LUMA_FILT_CNTL__SD1_INSIDE_ACTIVE_SLEW_EN__SHIFT__SI 0x00000019 -#define SD1_LUMA_FILT_CNTL__SD1_LUMA_DITHER_SEL__SHIFT__SI 0x0000001c -#define SD1_LUMA_FILT_CNTL__SD1_OUTSIDE_ACTIVE_SLEW_EN__SHIFT__SI 0x00000018 -#define SD1_LUMA_FILT_CNTL__SD1_SVIDY_OUT_BLEND__SHIFT__SI 0x0000000c -#define SD1_LUMA_FILT_CNTL__SD1_SVID_PASSTHRU_BLEND__SHIFT__SI 0x00000014 -#define SD1_LUMA_FILT_CNTL__SD1_YFLT_EN__SHIFT__SI 0x00000000 -#define SD1_LUMA_OFFSET_LIMIT__SD1_LUMA_LIMIT__SHIFT__SI 0x0000000c -#define SD1_LUMA_OFFSET_LIMIT__SD1_LUMA_OFFSET__SHIFT__SI 0x00000000 -#define SD1_LUMA_OFFSET_LIMIT__SD1_YC_OFFSET_LIMIT_BYPASS__SHIFT__SI 0x00000018 -#define SD1_LUMA_SYNC_TIP_LEVELS__SD1_PBPR_SYNC_TIP_LEVEL__SHIFT__SI 0x00000010 -#define SD1_LUMA_SYNC_TIP_LEVELS__SD1_Y_SYNC_TIP_LEVEL__SHIFT__SI 0x00000000 -#define SD1_MAIN_CNTL2__SD1_HDTV_SEL__SHIFT__SI 0x00000001 -#define SD1_MAIN_CNTL2__SD1_IKOS_CAP_FRAME_PULSE__SHIFT__SI 0x00000002 -#define SD1_MAIN_CNTL2__SD1_TVOUT_EN__SHIFT__SI 0x00000000 -#define SD1_MAIN_CNTL2__TVOUT_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT__SI 0x0000001f -#define SD1_MAIN_CNTL__SD1_ALT_PHASE_EN__SHIFT__SI 0x00000006 -#define SD1_MAIN_CNTL__SD1_ALT_PHASE_RST_ON_SYNC__SHIFT__SI 0x0000001a -#define SD1_MAIN_CNTL__SD1_BLANK_ON_RB_SEL__SHIFT__SI 0x0000000f -#define SD1_MAIN_CNTL__SD1_FIELD_SYNC_CNTL__SHIFT__SI 0x00000004 -#define SD1_MAIN_CNTL__SD1_FIELD_SYNC_TRIGGER__SHIFT__SI 0x00000003 -#define SD1_MAIN_CNTL__SD1_INVERT_ALT_LINE__SHIFT__SI 0x00000007 -#define SD1_MAIN_CNTL__SD1_MISC_DOUBLEB_REGS_CNTL__SHIFT__SI 0x00000009 -#define SD1_MAIN_CNTL__SD1_MISC_REGS_LOCK__SHIFT__SI 0x00000008 -#define SD1_MAIN_CNTL__SD1_PATTERN_GEN_EN__SHIFT__SI 0x00000010 -#define SD1_MAIN_CNTL__SD1_PATTERN_GEN_SEL__SHIFT__SI 0x00000011 -#define SD1_MAIN_CNTL__SD1_PIX_DELAY_SEL__SHIFT__SI 0x0000001b -#define SD1_MAIN_CNTL__SD1_PIX_DELAY__SHIFT__SI 0x00000014 -#define SD1_MAIN_CNTL__SD1_RESET_SCPHASE_TRIGGER__SHIFT__SI 0x00000002 -#define SD1_MAIN_CNTL__SD1_RESYNC_ALWAYS__SHIFT__SI 0x00000001 -#define SD1_MAIN_CNTL__SD1_RGB_OUTPUT_EN__SHIFT__SI 0x0000000e -#define SD1_MAIN_CNTL__SD1_TV_ASYNC_RST__SHIFT__SI 0x00000000 -#define SD1_MAIN_CNTL__SD1_U_1024_DATAIN_EN__SHIFT__SI 0x0000001e -#define SD1_MAIN_CNTL__SD1_VBI_PASSTHRU_EN__SHIFT__SI 0x0000000b -#define SD1_MAIN_CNTL__SD1_V_1024_DATAIN_EN__SHIFT__SI 0x0000001f -#define SD1_MAIN_CNTL__SD1_YPBPR_480I_EN__SHIFT__SI 0x0000000c -#define SD1_MAIN_CNTL__SD1_YPBPR_480P_EN__SHIFT__SI 0x0000000d -#define SD1_MAIN_CNTL__SD1_Y_1024_DATAIN_EN__SHIFT__SI 0x0000001c -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_AMPL_STEP__SHIFT__SI 0x00000000 -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_CYC_50HZ_EN__SHIFT__SI 0x00000009 -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_CYC_TMODE_EN__SHIFT__SI 0x00000008 -#define SD1_MV_AGC_CNTL__SD1_MV_AGC_PULSATE_EN__SHIFT__SI 0x0000000a -#define SD1_MV_AGC_CNTL__SD1_MV_OVRB_EN__SHIFT__SI 0x00000018 -#define SD1_MV_AGC_CNTL__SD1_MV_OVRB_LEVEL__SHIFT__SI 0x00000010 -#define SD1_MV_AGC_MAX_LEVELS__SD1_MV_AGC_AMPL_MAX__SHIFT__SI 0x00000000 -#define SD1_MV_AGC_MAX_LEVELS__SD1_MV_PBPR_EN__SHIFT__SI 0x0000001f -#define SD1_MV_AGC_PAL_A_B_LEVELS__SD1_MV_AGC_AMPL_A__SHIFT__SI 0x00000000 -#define SD1_MV_AGC_PAL_A_B_LEVELS__SD1_MV_AGC_AMPL_B__SHIFT__SI 0x00000010 -#define SD1_MV_BLANK_SETUP_LEVELS__SD1_MV_BLANK_LEVEL__SHIFT__SI 0x00000000 -#define SD1_MV_BLANK_SETUP_LEVELS__SD1_MV_SETUP_LEVEL__SHIFT__SI 0x00000010 -#define SD1_MV_BP_LEVEL__SD1_MV_BP_LEVEL__SHIFT__SI 0x00000000 -#define SD1_MV_N0_CONTROL__SD1_MV_DOUBLEB_REGS_CNTL__SHIFT__SI 0x00000009 -#define SD1_MV_N0_CONTROL__SD1_MV_N0_CONTROL__SHIFT__SI 0x00000000 -#define SD1_MV_N0_CONTROL__SD1_MV_REGS_LOCK__SHIFT__SI 0x00000008 -#define SD1_MV_N10_PS_AGC__SD1_MV_N10_A_PS_SPACE__SHIFT__SI 0x00000000 -#define SD1_MV_N10_PS_AGC__SD1_MV_N10_B_PS_SPACE__SHIFT__SI 0x00000008 -#define SD1_MV_N11_N12_PS_AGC__SD1_MV_N11_PS_AGC_LINE_SEL__SHIFT__SI 0x00000000 -#define SD1_MV_N11_N12_PS_AGC__SD1_MV_N12_PS_AGC_LINE_FORMAT__SHIFT__SI 0x00000010 -#define SD1_MV_N13_N14_PS_AGC_H_EN__SD1_MV_N13_A_PS_AGC_H_EN__SHIFT__SI 0x00000000 -#define SD1_MV_N13_N14_PS_AGC_H_EN__SD1_MV_N14_B_PS_AGC_H_EN__SHIFT__SI 0x00000008 -#define SD1_MV_N15_BP_TIMING__SD1_MV_H_BP_DUR__SHIFT__SI 0x00000008 -#define SD1_MV_N15_BP_TIMING__SD1_MV_N15_NUM_OF_BP_LINES__SHIFT__SI 0x00000000 -#define SD1_MV_N15_BP_TIMING__SD1_MV_V_BP_START_PRE_VSYNC1__SHIFT__SI 0x00000010 -#define SD1_MV_N15_BP_TIMING__SD1_MV_V_BP_START_PRE_VSYNC2__SHIFT__SI 0x00000011 -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_CS_BURST_ADVANCE_DUR__SHIFT__SI 0x00000000 -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_CS_MODIFY_4FALL_DEL__SHIFT__SI 0x00000010 -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_CS_UVFILT_RISE_DEL__SHIFT__SI 0x00000008 -#define SD1_MV_N16_CS_H_TIMING__SD1_MV_N16_CS_BURST_ADV_EN__SHIFT__SI 0x00000017 -#define SD1_MV_N17_TO_N19_CS__SD1_MV_N17_CS_ZONE1_DUR__SHIFT__SI 0x00000000 -#define SD1_MV_N17_TO_N19_CS__SD1_MV_N18_CS_ZONE2_DUR__SHIFT__SI 0x00000008 -#define SD1_MV_N17_TO_N19_CS__SD1_MV_N19_CS_ZONE3_DUR__SHIFT__SI 0x00000010 -#define SD1_MV_N1_TO_N3_CS__SD1_MV_N1_FIRST_CS_LINE_F1__SHIFT__SI 0x00000000 -#define SD1_MV_N1_TO_N3_CS__SD1_MV_N2_FIRST_CS_SPACE_F1__SHIFT__SI 0x00000008 -#define SD1_MV_N1_TO_N3_CS__SD1_MV_N3_FIRST_CS_LINE_F2__SHIFT__SI 0x00000010 -#define SD1_MV_N20_TO_N22_CS_RGB__SD1_MV_N20_CS_ZONE_PHASES__SHIFT__SI 0x00000000 -#define SD1_MV_N20_TO_N22_CS_RGB__SD1_MV_N21_CS_LINE_PHASES__SHIFT__SI 0x00000008 -#define SD1_MV_N20_TO_N22_CS_RGB__SD1_MV_N22_RGB_COPY_PROTECT__SHIFT__SI 0x00000014 -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N4_FIRST_CS_SPACE_F2__SHIFT__SI 0x00000000 -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N5_OTHER_CS_SPACE__SHIFT__SI 0x00000008 -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N6_NUM_OF_CS__SHIFT__SI 0x00000010 -#define SD1_MV_N4_TO_N7_CS__SD1_MV_N7_NUM_LINES_PER_CS__SHIFT__SI 0x00000018 -#define SD1_MV_N8_PS_AGC__SD1_MV_H_AGC_DUR__SHIFT__SI 0x00000010 -#define SD1_MV_N8_PS_AGC__SD1_MV_N8_A_PS_DUR__SHIFT__SI 0x00000000 -#define SD1_MV_N8_PS_AGC__SD1_MV_N8_B_PS_DUR__SHIFT__SI 0x00000008 -#define SD1_MV_N9_PS_AGC__SD1_MV_N9_A_FIRST_PS_START__SHIFT__SI 0x00000000 -#define SD1_MV_N9_PS_AGC__SD1_MV_N9_B_FIRST_PS_START__SHIFT__SI 0x00000010 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_H_MV_VBI_INIT__SHIFT__SI 0x00000002 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_BP_INIT__SHIFT__SI 0x00000000 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_BURST_INIT__SHIFT__SI 0x00000003 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_COUNT_INIT__SHIFT__SI 0x00000004 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_LINE_COUNT_INIT__SHIFT__SI 0x00000008 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_CS_START_INIT__SHIFT__SI 0x0000000c -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_PS_AGC_INIT__SHIFT__SI 0x00000018 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_PS_AGC_LINE_COUNT_INIT__SHIFT__SI 0x0000001c -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_PS_AGC_PALX_LO_INIT__SHIFT__SI 0x00000019 -#define SD1_MV_TIMING_INTERNAL_INIT__SD1_V_MV_VBI_INIT__SHIFT__SI 0x00000001 -#define SD1_MV_V_PS_AGC_TIMING__SD1_MV_V_PS_AGC_START1__SHIFT__SI 0x00000000 -#define SD1_MV_V_PS_AGC_TIMING__SD1_MV_V_PS_AGC_START2__SHIFT__SI 0x0000000c -#define SD1_MV_V_PS_AGC_TIMING__SD1_MV_V_PS_STATE_X_HI_DUR__SHIFT__SI 0x00000018 -#define SD1_MV_V_REDUCE_SYNC_ENDS__SD1_MV_VBI_END1__SHIFT__SI 0x00000000 -#define SD1_MV_V_REDUCE_SYNC_ENDS__SD1_MV_VBI_END2__SHIFT__SI 0x0000000f -#define SD1_RGB_OR_PBPR_BLANK_LEVEL__SD1_RGB_OR_PBPR_BLANK_LEVEL__SHIFT__SI 0x00000000 -#define SD1_SCM_COL_SC_DENOMIN__SD1_SCM_COL_SC_DENOMIN__SHIFT__SI 0x00000000 -#define SD1_SCM_COL_SC_INC_CORR__SD1_SCM_COL_SC_INC_CORR__SHIFT__SI 0x00000000 -#define SD1_SCM_COL_SC_INC__SD1_SCM_COL_SC_INC__SHIFT__SI 0x00000000 -#define SD1_SCM_DB_DR_SCALE_FACTORS__SD1_SCM_DB_SCALE_FACTOR__SHIFT__SI 0x00000000 -#define SD1_SCM_DB_DR_SCALE_FACTORS__SD1_SCM_DR_SCALE_FACTOR__SHIFT__SI 0x00000010 -#define SD1_SCM_MAX_DTO_SWING__SD1_SCM_MAX_DTO_SWING__SHIFT__SI 0x00000000 -#define SD1_SCM_MIN_DTO_SWING__SD1_SCM_MIN_DTO_SWING__SHIFT__SI 0x00000000 -#define SD1_SCM_MOD_CNTL__SD1_INVERT_SCM_3LINE__SHIFT__SI 0x0000001b -#define SD1_SCM_MOD_CNTL__SD1_SCM_2LINE_EN__SHIFT__SI 0x0000001e -#define SD1_SCM_MOD_CNTL__SD1_SCM_3LINE_INIT__SHIFT__SI 0x0000001c -#define SD1_SCM_MOD_CNTL__SD1_SCM_BURST_GAIN__SHIFT__SI 0x00000000 -#define SD1_SCM_MOD_CNTL__SD1_SCM_DTO_LIMIT_EN__SHIFT__SI 0x0000001f -#define SD1_SCM_MOD_CNTL__SD1_SCM_ENABLE__SHIFT__SI 0x00000018 -#define SD1_SCM_MOD_CNTL__SD1_SCM_INVERT_PHASE_EN__SHIFT__SI 0x0000001a -#define SD1_SCM_MOD_CNTL__SD1_SCM_NOTCH_TUNER__SHIFT__SI 0x00000010 -#define SD1_SCM_MOD_CNTL__SD1_SCM_RST_DTO_ON_BLANK__SHIFT__SI 0x00000019 -#define SD1_SDTV0_DEBUG__SD1_SDTV0_DEBUG__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_134BIT__SD1_H_134BIT_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_20BIT__SD1_H_20BIT_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW1__SD1_H_ACTIVE_FILT_END1__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW1__SD1_H_ACTIVE_FILT_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW2__SD1_H_ACTIVE_FILT_END2__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_ACTIVE_FILT_WINDOW2__SD1_H_ACTIVE_FILT_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_ADV_ACTIVE__SD1_H_ADV_ACTIVE_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_ADV_ACTIVE__SD1_H_ADV_ACTIVE_START2__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_ADV_VBI_PASSTHRU__SD1_H_ADV_VBI_PASSTHRU_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_BURST__SD1_H_BURST_DUR__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_BURST__SD1_H_BURST_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_CC_EDS__SD1_H_CC_OR_EDS_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_COUNT_INIT__SD1_H_COUNT_INIT__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_COUNT__SD1_H_COUNT__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_EQUALIZATION1__SD1_H_EQ_PULSE_END1__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_EQUALIZATION1__SD1_H_EQ_PULSE_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_EQUALIZATION2__SD1_H_EQ_PULSE_END2__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_EQUALIZATION2__SD1_H_EQ_PULSE_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_HSYNC__SD1_H_HSYNC_END__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_HSYNC__SD1_H_HSYNC_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_RUNIN_FILT_WINDOW__SD1_H_RUNIN_FILT_END__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_RUNIN_FILT_WINDOW__SD1_H_RUNIN_FILT_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_SERATION1__SD1_H_SER_PULSE_END1__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_SERATION1__SD1_H_SER_PULSE_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_SERATION2__SD1_H_SER_PULSE_END2__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_SERATION2__SD1_H_SER_PULSE_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_SETUP1__SD1_H_SETUP_END1__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_SETUP1__SD1_H_SETUP_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_SETUP2__SD1_H_SETUP_END2__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_SETUP2__SD1_H_SETUP_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_TOTAL__SD1_H_TOTAL__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW__SD1_H_VBI_PASSTHRU_FILT_END__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW__SD1_H_VBI_PASSTHRU_FILT_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_VBI_PASSTHRU__SD1_H_VBI_PASSTHRU_END__SHIFT__SI 0x00000010 -#define SD1_TIMING_H_VBI_PASSTHRU__SD1_H_VBI_PASSTHRU_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_H_WSS__SD1_H_WSS_START__SHIFT__SI 0x00000000 -#define SD1_TIMING_INTERNAL_INIT__SD1_H_BURST_INIT__SHIFT__SI 0x00000006 -#define SD1_TIMING_INTERNAL_INIT__SD1_H_EQ_PULSE_INIT__SHIFT__SI 0x00000002 -#define SD1_TIMING_INTERNAL_INIT__SD1_H_HSYNC_INIT__SHIFT__SI 0x00000000 -#define SD1_TIMING_INTERNAL_INIT__SD1_H_SER_PULSE_INIT__SHIFT__SI 0x00000003 -#define SD1_TIMING_INTERNAL_INIT__SD1_H_SETUP_INIT__SHIFT__SI 0x00000008 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_ACTIVE_INIT__SHIFT__SI 0x0000000a -#define SD1_TIMING_INTERNAL_INIT__SD1_V_BURST_INIT__SHIFT__SI 0x00000007 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_CC_LINE_INIT__SHIFT__SI 0x0000000c -#define SD1_TIMING_INTERNAL_INIT__SD1_V_EDS_LINE_INIT__SHIFT__SI 0x0000000e -#define SD1_TIMING_INTERNAL_INIT__SD1_V_EQ_SER_INIT__SHIFT__SI 0x00000004 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F1_134BIT_LINE_INIT__SHIFT__SI 0x00000014 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F1_20BIT_LINE_INIT__SHIFT__SI 0x00000010 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F2_134BIT_LINE_INIT__SHIFT__SI 0x00000015 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_F2_20BIT_LINE_INIT__SHIFT__SI 0x00000011 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_HSYNC_INIT__SHIFT__SI 0x00000001 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_SER_INIT__SHIFT__SI 0x00000005 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_SETUP_INIT__SHIFT__SI 0x00000009 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_VBI_PASSTHRU_INIT__SHIFT__SI 0x00000013 -#define SD1_TIMING_INTERNAL_INIT__SD1_V_WSS_LINE_INIT__SHIFT__SI 0x00000012 -#define SD1_TIMING_V_134BIT__SD1_V_134BIT1_LINE__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_134BIT__SD1_V_134BIT2_LINE__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_20BIT__SD1_V_20BIT1_LINE__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_20BIT__SD1_V_20BIT2_LINE__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_ACTIVE1__SD1_V_ACTIVE_END1__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_ACTIVE1__SD1_V_ACTIVE_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_ACTIVE2__SD1_V_ACTIVE_END2__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_ACTIVE2__SD1_V_ACTIVE_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_BURST1__SD1_ALT_BURST_BLANK_EN__SHIFT__SI 0x0000001c -#define SD1_TIMING_V_BURST1__SD1_ALT_V_BURST_END1__SHIFT__SI 0x0000001e -#define SD1_TIMING_V_BURST1__SD1_ALT_V_BURST_START1__SHIFT__SI 0x0000001d -#define SD1_TIMING_V_BURST1__SD1_V_BURST_END1__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_BURST1__SD1_V_BURST_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_BURST2__SD1_ALT_V_BURST_END2__SHIFT__SI 0x0000001d -#define SD1_TIMING_V_BURST2__SD1_ALT_V_BURST_START2__SHIFT__SI 0x0000001c -#define SD1_TIMING_V_BURST2__SD1_V_BURST_END2__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_BURST2__SD1_V_BURST_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_CC_EDS__SD1_V_CC_LINE__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_CC_EDS__SD1_V_EDS_LINE__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_EQUALIZATION1__SD1_V_EQ_PULSE_DUR1__SHIFT__SI 0x0000000f -#define SD1_TIMING_V_EQUALIZATION1__SD1_V_EQ_PULSE_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_EQUALIZATION2__SD1_V_EQ_PULSE_DUR2__SHIFT__SI 0x0000000f -#define SD1_TIMING_V_EQUALIZATION2__SD1_V_EQ_PULSE_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_F_COUNT_INIT__SD1_F_COUNT_INIT__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_F_COUNT_INIT__SD1_V_COUNT_INIT__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_F_COUNT__SD1_F_COUNT__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_F_COUNT__SD1_V_COUNT__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_F_TOTAL__SD1_F_TOTAL__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_F_TOTAL__SD1_V_TOTAL__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_SERATION1__SD1_V_SER_PULSE_DUR1__SHIFT__SI 0x0000000f -#define SD1_TIMING_V_SERATION1__SD1_V_SER_PULSE_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_SERATION2__SD1_V_SER_PULSE_DUR2__SHIFT__SI 0x0000000f -#define SD1_TIMING_V_SERATION2__SD1_V_SER_PULSE_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_SETUP1__SD1_V_SETUP_END1__SHIFT__SI 0x0000000f -#define SD1_TIMING_V_SETUP1__SD1_V_SETUP_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_SETUP2__SD1_V_SETUP_END2__SHIFT__SI 0x0000000f -#define SD1_TIMING_V_SETUP2__SD1_V_SETUP_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_VBI_PASSTHRU1__SD1_V_VBI_PASSTHRU_END1__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_VBI_PASSTHRU1__SD1_V_VBI_PASSTHRU_START1__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_VBI_PASSTHRU2__SD1_V_VBI_PASSTHRU_END2__SHIFT__SI 0x00000010 -#define SD1_TIMING_V_VBI_PASSTHRU2__SD1_V_VBI_PASSTHRU_START2__SHIFT__SI 0x00000000 -#define SD1_TIMING_V_WSS__SD1_V_WSS_LINE__SHIFT__SI 0x00000000 -#define SD1_TV_SOURCE_CONTROL__SD1_TV_DATA_SOURCE__SHIFT__SI 0x00000000 -#define SD1_UPSAMPLE_MODE__SD1_FOUR_TAP_MODE__SHIFT__SI 0x00000000 -#define SD1_UPSAMPLE_MODE__SD1_UPSAMP_PICK_NEAR__SHIFT__SI 0x00000004 -#define SD1_U_AND_V_GAIN_SETTINGS__SD1_U_GAIN__SHIFT__SI 0x00000000 -#define SD1_U_AND_V_GAIN_SETTINGS__SD1_V_GAIN__SHIFT__SI 0x00000010 -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_U_BREAK_EN__SHIFT__SI 0x0000000c -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_U_GAIN_LIMIT__SHIFT__SI 0x00000000 -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_V_BREAK_EN__SHIFT__SI 0x0000001c -#define SD1_U_V_BREAK_POINT_SETTINGS__SD1_V_GAIN_LIMIT__SHIFT__SI 0x00000010 -#define SD1_VBI_134BIT_CNTL__SD1_134BIT_FIELD1_EN__SHIFT__SI 0x0000001e -#define SD1_VBI_134BIT_CNTL__SD1_134BIT_FIELD2_EN__SHIFT__SI 0x0000001f -#define SD1_VBI_134BIT_CNTL__SD1_134BIT_SAME_DATA_EN__SHIFT__SI 0x00000014 -#define SD1_VBI_134BIT_CNTL__SD1_VBI_134BIT_END_STATUS__SHIFT__SI 0x0000001a -#define SD1_VBI_134BIT_CNTL__SD1_VBI_134BIT_WT_ACK__SHIFT__SI 0x00000019 -#define SD1_VBI_134BIT_CNTL__SD1_VBI_134BIT_WT__SHIFT__SI 0x00000018 -#define SD1_VBI_134BIT_DTO_CNTL__SD1_VBI_134BIT_DTO_P__SHIFT__SI 0x00000000 -#define SD1_VBI_134BIT_H_DATA__SD1_VBI_134BIT_H_DATA__SHIFT__SI 0x00000000 -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_CGMSA__SHIFT__SI 0x0000000c -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_CRC__SHIFT__SI 0x00000010 -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_DIS__SHIFT__SI 0x00000000 -#define SD1_VBI_134BIT_NULL_PACKET_CNTL__SD1_VBI_134BIT_PROG_NULL_HEADER__SHIFT__SI 0x00000004 -#define SD1_VBI_134BIT_P_DATA0__SD1_VBI_134BIT_P_DATA0__SHIFT__SI 0x00000000 -#define SD1_VBI_134BIT_P_DATA1__SD1_VBI_134BIT_P_DATA1__SHIFT__SI 0x00000000 -#define SD1_VBI_134BIT_P_DATA2__SD1_VBI_134BIT_P_DATA2__SHIFT__SI 0x00000000 -#define SD1_VBI_134BIT_P_DATA3__SD1_VBI_134BIT_P_DATA3__SHIFT__SI 0x00000000 -#define SD1_VBI_20BIT_CNTL__SD1_20BIT_FIELD1_EN__SHIFT__SI 0x0000001e -#define SD1_VBI_20BIT_CNTL__SD1_20BIT_FIELD2_EN__SHIFT__SI 0x0000001f -#define SD1_VBI_20BIT_CNTL__SD1_20BIT_SAME_DATA_EN__SHIFT__SI 0x00000014 -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_DATA__SHIFT__SI 0x00000000 -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_END_STATUS__SHIFT__SI 0x0000001a -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_WT_ACK__SHIFT__SI 0x00000019 -#define SD1_VBI_20BIT_CNTL__SD1_VBI_20BIT_WT__SHIFT__SI 0x00000018 -#define SD1_VBI_20BIT_DTO_CNTL__SD1_VBI_20BIT_DTO_P__SHIFT__SI 0x00000000 -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_CGMSA__SHIFT__SI 0x0000000c -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_CRC__SHIFT__SI 0x00000010 -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_DIS__SHIFT__SI 0x00000000 -#define SD1_VBI_20BIT_NULL_PACKET_CNTL__SD1_VBI_20BIT_PROG_NULL_HEADER__SHIFT__SI 0x00000004 -#define SD1_VBI_CC_CNTL__SD1_CC_EN__SHIFT__SI 0x0000001f -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_DATA__SHIFT__SI 0x00000000 -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_END_STATUS__SHIFT__SI 0x0000001a -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_WT_ACK__SHIFT__SI 0x00000019 -#define SD1_VBI_CC_CNTL__SD1_VBI_CC_WT__SHIFT__SI 0x00000018 -#define SD1_VBI_CC_EDS_DTO_CNTL__SD1_VBI_CC_EDS_DTO_P__SHIFT__SI 0x00000000 -#define SD1_VBI_EDS_CNTL__SD1_EDS_EN__SHIFT__SI 0x0000001f -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_DATA__SHIFT__SI 0x00000000 -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_END_STATUS__SHIFT__SI 0x0000001a -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_WT_ACK__SHIFT__SI 0x00000019 -#define SD1_VBI_EDS_CNTL__SD1_VBI_EDS_WT__SHIFT__SI 0x00000018 -#define SD1_VBI_LEVEL_CNTL__SD1_VBI_134BIT_LEVEL__SHIFT__SI 0x00000018 -#define SD1_VBI_LEVEL_CNTL__SD1_VBI_20BIT_LEVEL__SHIFT__SI 0x00000008 -#define SD1_VBI_LEVEL_CNTL__SD1_VBI_WSS_LEVEL__SHIFT__SI 0x00000010 -#define SD1_VBI_RUNIN_GAIN_CNTL__SD1_VBI_CC_EDS_RUNIN_GAIN__SHIFT__SI 0x00000000 -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_DATA__SHIFT__SI 0x00000000 -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_END_STATUS__SHIFT__SI 0x0000001a -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_WT_ACK__SHIFT__SI 0x00000019 -#define SD1_VBI_WSS_CNTL__SD1_VBI_WSS_WT__SHIFT__SI 0x00000018 -#define SD1_VBI_WSS_CNTL__SD1_WSS_EN__SHIFT__SI 0x0000001f -#define SD1_VBI_WSS_DTO_CNTL__SD1_VBI_WSS_DTO_P__SHIFT__SI 0x00000000 -#define SD1_VIDEO_PORT_SIG__SD1_CRC_SIG__SHIFT__SI 0x00000000 -#define SD1_VIDOUT_MUX_CNTL__SD1_ENCODER_BYPASS_EN__SHIFT__SI 0x0000001c -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_OUTPUT_DITHER_SEL__SHIFT__SI 0x0000001e -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX0_EN__SHIFT__SI 0x00000000 -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX0__SHIFT__SI 0x00000004 -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX1_EN__SHIFT__SI 0x00000001 -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX1__SHIFT__SI 0x00000008 -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX2_EN__SHIFT__SI 0x00000002 -#define SD1_VIDOUT_MUX_CNTL__SD1_VIDEO_SELECT_MUX2__SHIFT__SI 0x0000000c -#define SD1_Y_AND_PASSTHRU_GAIN_SETTINGS__SD1_VBI_PASSTHRU_GAIN__SHIFT__SI 0x00000010 -#define SD1_Y_AND_PASSTHRU_GAIN_SETTINGS__SD1_Y_GAIN__SHIFT__SI 0x00000000 -#define SD1_Y_BREAK_POINT_SETTING__SD1_Y_BREAK_EN__SHIFT__SI 0x00000010 -#define SD1_Y_BREAK_POINT_SETTING__SD1_Y_GAIN_LIMIT__SHIFT__SI 0x00000000 -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT__CI__VI 0x00000017 -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT__CI__VI 0x00000010 -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT__CI__VI 0x00000014 -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT__CI__VI 0x00000004 -#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT__CI__VI 0x00000000 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT__CI__VI 0x0000001f -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT__CI__VI 0x0000001e -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT__CI__VI 0x0000001d -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT__CI__VI 0x0000001c -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT__CI__VI 0x0000001b -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT__CI__VI 0x0000001a -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT__CI__VI 0x00000019 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT__CI__VI 0x00000018 -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT__CI__VI 0x00000012 -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT__CI__VI 0x0000001c -#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT__CI__VI 0x00000003 -#define SDMA0_CNTL__DRM_CREDIT__SHIFT__CI__VI 0x00000006 -#define SDMA0_CNTL__ECC_ENABLE__SHIFT__CI 0x0000001e -#define SDMA0_CNTL__ECC_INT_ENABLE__SHIFT__CI 0x0000001f -#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT__CI__VI 0x00000016 -#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT__CI__VI 0x0000000b -#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT__CI 0x00000001 -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT__CI__VI 0x00000002 -#define SDMA0_CNTL__TRAP_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_CONFIG__SDMA_RDREQ_URG__SHIFT__CI 0x00000008 -#define SDMA0_CONFIG__SDMA_REQ_TRAN__SHIFT__CI 0x00000010 -#define SDMA0_F32_CNTL__HALT__SHIFT__CI__VI 0x00000000 -#define SDMA0_F32_CNTL__STEP__SHIFT__CI__VI 0x00000001 -#define SDMA0_FREEZE__FREEZE__SHIFT__CI__VI 0x00000004 -#define SDMA0_FREEZE__FROZEN__SHIFT__CI__VI 0x00000005 -#define SDMA0_FREEZE__PREEMPT__SHIFT__CI 0x00000000 -#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT__CI__VI 0x00000010 -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT__CI__VI 0x00000010 -#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT__CI__VI 0x00000018 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT__CI__VI 0x00000007 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT__CI__VI 0x00000008 -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT__CI__VI 0x00000004 -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT__CI__VI 0x00000003 -#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERDATA0__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERDATA1__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERDATA2__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERDATA3__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERKEY0__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERKEY1__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERKEY2__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_COUNTERKEY3__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_IVLOAD0__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_IVLOAD1__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_IVLOAD2__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_IVLOAD3__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_IVLOAD4__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_OFFSET__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_UNROLLKEY__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_WRAPPEDKEY0__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_WRAPPEDKEY1__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_WRAPPEDKEY2__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_DRM_WRAPPEDKEY3__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT__CI__VI 0x00000005 -#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT__CI__VI 0x00000010 -#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_IB_CNTL__IB_PRIV__SHIFT__CI__VI 0x0000001f -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT__CI__VI 0x00000008 -#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_RB_BASE__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT__CI__VI 0x00000017 -#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT__CI__VI 0x00000001 -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT__CI__VI 0x00000009 -#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT__CI__VI 0x00000018 -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__CI__VI 0x0000000c -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__CI__VI 0x0000000d -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__CI__VI 0x00000010 -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__CI__VI 0x00000004 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__CI__VI 0x00000010 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__CI__VI 0x00000001 -#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT__CI__VI 0x00000000 -#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT__CI__VI 0x00000004 -#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT__CI__VI 0x00000008 -#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT__CI__VI 0x0000001e -#define SDMA0_HASH__BANK_BITS__SHIFT__CI__VI 0x00000004 -#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT__CI__VI 0x0000000c -#define SDMA0_HASH__CHANNEL_BITS__SHIFT__CI__VI 0x00000000 -#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT__CI__VI 0x00000008 -#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT__CI__VI 0x00000001 -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT__CI__VI 0x00000009 -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT__CI__VI 0x00000000 -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT__CI__VI 0x00000008 -#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT__CI__VI 0x00000002 -#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT__CI__VI 0x0000001e -#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT__CI__VI 0x00000000 -#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT__CI__VI 0x00000008 -#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT__CI__VI 0x0000001e -#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT__CI__VI 0x00000000 -#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT__CI__VI 0x00000008 -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define SDMA0_PROGRAM__STREAM__SHIFT__CI__VI 0x00000000 -#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT__CI__VI 0x00000007 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT__CI__VI 0x00000008 -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT__CI__VI 0x00000003 -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT__CI__VI 0x0000001e -#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT__CI__VI 0x0000001c -#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT__CI__VI 0x00000005 -#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_IB_CNTL__IB_PRIV__SHIFT__CI__VI 0x0000001f -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT__CI__VI 0x00000008 -#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT__CI__VI 0x00000017 -#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT__CI__VI 0x00000001 -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT__CI__VI 0x00000009 -#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT__CI__VI 0x00000018 -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__CI__VI 0x0000000c -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__CI__VI 0x0000000d -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__CI__VI 0x00000001 -#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT__CI__VI 0x00000008 -#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT__CI__VI 0x0000001e -#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT__CI__VI 0x00000007 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT__CI__VI 0x00000008 -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT__CI__VI 0x00000003 -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT__CI__VI 0x0000001e -#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT__CI__VI 0x0000001c -#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT__CI__VI 0x00000005 -#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_IB_CNTL__IB_PRIV__SHIFT__CI__VI 0x0000001f -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT__CI__VI 0x00000008 -#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT__CI__VI 0x00000017 -#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT__CI__VI 0x00000001 -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT__CI__VI 0x00000009 -#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT__CI__VI 0x00000018 -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__CI__VI 0x0000000c -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__CI__VI 0x0000000d -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__CI__VI 0x00000010 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__CI__VI 0x00000001 -#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT__CI__VI 0x00000000 -#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT__CI__VI 0x00000004 -#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT__CI__VI 0x00000008 -#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT__CI__VI 0x0000001e -#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT__CI 0x00000000 -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT__CI__VI 0x00000000 -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT__CI__VI 0x0000000a -#define SDMA0_STATUS1_REG__CE_DRM1_FULL__SHIFT__CI__VI 0x0000000c -#define SDMA0_STATUS1_REG__CE_DRM1_IDLE__SHIFT__CI__VI 0x00000008 -#define SDMA0_STATUS1_REG__CE_DRM_FULL__SHIFT__CI__VI 0x0000000b -#define SDMA0_STATUS1_REG__CE_DRM_IDLE__SHIFT__CI__VI 0x00000007 -#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT__CI__VI 0x00000006 -#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT__CI__VI 0x0000000e -#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT__CI__VI 0x0000000d -#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT__CI__VI 0x00000005 -#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT__CI__VI 0x00000004 -#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT__CI__VI 0x00000011 -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT__CI__VI 0x00000003 -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT__CI__VI 0x00000001 -#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT__CI__VI 0x00000012 -#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT__CI__VI 0x00000008 -#define SDMA0_STATUS_REG__DRM_IDLE__SHIFT__CI__VI 0x00000017 -#define SDMA0_STATUS_REG__DRM_MASK_FULL__SHIFT__CI__VI 0x00000018 -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT__CI__VI 0x0000000b -#define SDMA0_STATUS_REG__EX_IDLE__SHIFT__CI__VI 0x0000000a -#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT__CI__VI 0x00000007 -#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT__CI__VI 0x00000006 -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT__CI__VI 0x00000012 -#define SDMA0_STATUS_REG__IDLE__SHIFT__CI__VI 0x00000000 -#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT__CI__VI 0x00000009 -#define SDMA0_STATUS_REG__INT_IDLE__SHIFT__CI__VI 0x0000001e -#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT__CI__VI 0x0000001f -#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT__CI__VI 0x00000013 -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT__CI__VI 0x00000016 -#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT__CI__VI 0x00000015 -#define SDMA0_STATUS_REG__MC_WR_AFIFO_FULL__SHIFT__CI 0x0000000e -#define SDMA0_STATUS_REG__MC_WR_DFIFO_FULL__SHIFT__CI 0x0000000f -#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT__CI__VI 0x0000000d -#define SDMA0_STATUS_REG__PACKET_READY__SHIFT__CI__VI 0x0000000c -#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT__CI__VI 0x00000019 -#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT__CI__VI 0x00000005 -#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT__CI__VI 0x00000004 -#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT__CI__VI 0x00000002 -#define SDMA0_STATUS_REG__RB_FULL__SHIFT__CI__VI 0x00000003 -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT__CI__VI 0x00000011 -#define SDMA0_STATUS_REG__REG_IDLE__SHIFT__CI__VI 0x00000001 -#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT__CI__VI 0x0000001a -#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT__CI__VI 0x0000001b -#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT__CI__VI 0x0000001c -#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT__CI__VI 0x00000004 -#define SDMA0_UCODE_ADDR__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA0_UCODE_DATA__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT__CI__VI 0x00000017 -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT__CI__VI 0x00000010 -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT__CI__VI 0x00000014 -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT__CI__VI 0x00000004 -#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT__CI__VI 0x00000000 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT__CI__VI 0x0000001f -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT__CI__VI 0x0000001e -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT__CI__VI 0x0000001d -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT__CI__VI 0x0000001c -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT__CI__VI 0x0000001b -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT__CI__VI 0x0000001a -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT__CI__VI 0x00000019 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT__CI__VI 0x00000018 -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT__CI__VI 0x00000012 -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT__CI__VI 0x0000001c -#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT__CI__VI 0x00000003 -#define SDMA1_CNTL__DRM_CREDIT__SHIFT__CI__VI 0x00000006 -#define SDMA1_CNTL__ECC_ENABLE__SHIFT__CI 0x0000001e -#define SDMA1_CNTL__ECC_INT_ENABLE__SHIFT__CI 0x0000001f -#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT__CI__VI 0x0000001d -#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT__CI__VI 0x00000016 -#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT__CI__VI 0x0000000b -#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT__CI 0x00000001 -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT__CI__VI 0x00000002 -#define SDMA1_CNTL__TRAP_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT__CI 0x00000008 -#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT__CI 0x00000010 -#define SDMA1_F32_CNTL__HALT__SHIFT__CI__VI 0x00000000 -#define SDMA1_F32_CNTL__STEP__SHIFT__CI__VI 0x00000001 -#define SDMA1_FREEZE__FREEZE__SHIFT__CI__VI 0x00000004 -#define SDMA1_FREEZE__FROZEN__SHIFT__CI__VI 0x00000005 -#define SDMA1_FREEZE__PREEMPT__SHIFT__CI 0x00000000 -#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT__CI__VI 0x00000010 -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT__CI__VI 0x00000010 -#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT__CI__VI 0x00000018 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT__CI__VI 0x00000007 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT__CI__VI 0x00000008 -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT__CI__VI 0x00000004 -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT__CI__VI 0x00000003 -#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT__CI__VI 0x00000005 -#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT__CI__VI 0x00000010 -#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_IB_CNTL__IB_PRIV__SHIFT__CI__VI 0x0000001f -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT__CI__VI 0x00000008 -#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_RB_BASE__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT__CI__VI 0x00000017 -#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT__CI__VI 0x00000001 -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT__CI__VI 0x00000009 -#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT__CI__VI 0x00000018 -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__CI__VI 0x0000000c -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__CI__VI 0x0000000d -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__CI__VI 0x00000010 -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__CI__VI 0x00000004 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__CI__VI 0x00000010 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__CI__VI 0x00000001 -#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT__CI__VI 0x00000000 -#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT__CI__VI 0x00000004 -#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT__CI__VI 0x00000008 -#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT__CI__VI 0x0000001e -#define SDMA1_HASH__BANK_BITS__SHIFT__CI__VI 0x00000004 -#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT__CI__VI 0x0000000c -#define SDMA1_HASH__CHANNEL_BITS__SHIFT__CI__VI 0x00000000 -#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT__CI__VI 0x00000008 -#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT__CI__VI 0x00000001 -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT__CI__VI 0x00000009 -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT__CI__VI 0x00000000 -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT__CI__VI 0x00000008 -#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT__CI__VI 0x00000002 -#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT__CI__VI 0x0000001e -#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT__CI__VI 0x00000000 -#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT__CI__VI 0x00000008 -#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT__CI__VI 0x0000001e -#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT__CI__VI 0x00000000 -#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT__CI__VI 0x00000008 -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define SDMA1_PROGRAM__STREAM__SHIFT__CI__VI 0x00000000 -#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT__CI__VI 0x00000007 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT__CI__VI 0x00000008 -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT__CI__VI 0x00000003 -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT__CI__VI 0x0000001e -#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT__CI__VI 0x0000001c -#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT__CI__VI 0x00000005 -#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_IB_CNTL__IB_PRIV__SHIFT__CI__VI 0x0000001f -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT__CI__VI 0x00000008 -#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT__CI__VI 0x00000017 -#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT__CI__VI 0x00000001 -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT__CI__VI 0x00000009 -#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT__CI__VI 0x00000018 -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__CI__VI 0x0000000c -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__CI__VI 0x0000000d -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__CI__VI 0x00000001 -#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT__CI__VI 0x00000008 -#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT__CI__VI 0x0000001e -#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT__CI__VI 0x00000007 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT__CI__VI 0x00000008 -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT__CI__VI 0x00000003 -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT__CI__VI 0x0000001e -#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT__CI__VI 0x0000001c -#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT__CI__VI 0x00000005 -#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_IB_CNTL__IB_PRIV__SHIFT__CI__VI 0x0000001f -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT__CI__VI 0x00000008 -#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT__CI__VI 0x00000017 -#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT__CI__VI 0x00000001 -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT__CI__VI 0x00000009 -#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT__CI__VI 0x00000018 -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT__CI__VI 0x0000000c -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT__CI__VI 0x0000000d -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__CI__VI 0x00000010 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT__CI__VI 0x00000001 -#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT__CI__VI 0x00000002 -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT__CI__VI 0x00000000 -#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT__CI__VI 0x00000004 -#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT__CI__VI 0x00000008 -#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT__CI__VI 0x0000001e -#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT__CI 0x00000000 -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT__CI__VI 0x00000000 -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT__CI__VI 0x0000000a -#define SDMA1_STATUS1_REG__CE_DRM1_FULL__SHIFT__CI__VI 0x0000000c -#define SDMA1_STATUS1_REG__CE_DRM1_IDLE__SHIFT__CI__VI 0x00000008 -#define SDMA1_STATUS1_REG__CE_DRM_FULL__SHIFT__CI__VI 0x0000000b -#define SDMA1_STATUS1_REG__CE_DRM_IDLE__SHIFT__CI__VI 0x00000007 -#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT__CI__VI 0x00000006 -#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT__CI__VI 0x0000000e -#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT__CI__VI 0x0000000d -#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT__CI__VI 0x00000005 -#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT__CI__VI 0x00000004 -#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT__CI__VI 0x00000011 -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT__CI__VI 0x00000003 -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT__CI__VI 0x00000002 -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT__CI__VI 0x00000001 -#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT__CI__VI 0x00000012 -#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT__CI__VI 0x00000008 -#define SDMA1_STATUS_REG__DRM_IDLE__SHIFT__CI__VI 0x00000017 -#define SDMA1_STATUS_REG__DRM_MASK_FULL__SHIFT__CI__VI 0x00000018 -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT__CI__VI 0x0000000b -#define SDMA1_STATUS_REG__EX_IDLE__SHIFT__CI__VI 0x0000000a -#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT__CI__VI 0x00000007 -#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT__CI__VI 0x00000006 -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT__CI__VI 0x00000012 -#define SDMA1_STATUS_REG__IDLE__SHIFT__CI__VI 0x00000000 -#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT__CI__VI 0x00000009 -#define SDMA1_STATUS_REG__INT_IDLE__SHIFT__CI__VI 0x0000001e -#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT__CI__VI 0x0000001f -#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT__CI__VI 0x00000013 -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT__CI__VI 0x00000016 -#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT__CI__VI 0x00000015 -#define SDMA1_STATUS_REG__MC_WR_AFIFO_FULL__SHIFT__CI 0x0000000e -#define SDMA1_STATUS_REG__MC_WR_DFIFO_FULL__SHIFT__CI 0x0000000f -#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT__CI__VI 0x0000000d -#define SDMA1_STATUS_REG__PACKET_READY__SHIFT__CI__VI 0x0000000c -#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT__CI__VI 0x00000019 -#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT__CI__VI 0x00000005 -#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT__CI__VI 0x00000004 -#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT__CI__VI 0x00000002 -#define SDMA1_STATUS_REG__RB_FULL__SHIFT__CI__VI 0x00000003 -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT__CI__VI 0x00000011 -#define SDMA1_STATUS_REG__REG_IDLE__SHIFT__CI__VI 0x00000001 -#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT__CI__VI 0x0000001a -#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT__CI__VI 0x0000001b -#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT__CI__VI 0x0000001c -#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT__CI__VI 0x00000004 -#define SDMA1_UCODE_ADDR__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA1_UCODE_DATA__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT__CI 0x00000008 -#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT__CI 0x00000010 -#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT__CI__VI 0x00000000 -#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT__CI__VI 0x0000000a -#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT__CI__VI 0x0000000b -#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT__CI__VI 0x00000008 -#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT__CI__VI 0x00000009 -#define SDMA_PGFSM_CONFIG__READ__SHIFT__CI__VI 0x0000000d -#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT__CI__VI 0x0000001c -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT__CI__VI 0x0000001b -#define SDMA_PGFSM_CONFIG__WRITE__SHIFT__CI__VI 0x0000000c -#define SDMA_PGFSM_READ__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA_PGFSM_WRITE__VALUE__SHIFT__CI__VI 0x00000000 -#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT__CI__VI 0x00000001 -#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT__CI__VI 0x00000000 -#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT__CI__VI 0x00000004 -#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT__CI__VI 0x00000002 -#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT__CI__VI 0x00000008 -#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT__CI__VI 0x00000014 -#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT__CI__VI 0x00000006 -#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT__CI__VI 0x00000007 -#define SDVO_CNTL__SDVO_REARRANGER_EN__SHIFT__SI 0x00000008 -#define SDVO_CNTL__SDVO_REPL_MODE_SELECT__SHIFT__SI 0x00000000 -#define SDVO_CNTL__SDVO_SYNC_PHASE__SHIFT__SI 0x0000000c -#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT__CI__VI 0x00000001 -#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT__CI__VI 0x00000000 -#define SEM_EDC_CONFIG__DIS_EDC__SHIFT__CI__VI 0x00000001 -#define SEM_EDC_CONFIG__WRITE_DIS__SHIFT__CI__VI 0x00000000 -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000 -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003 -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006 -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009 -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA0_CLIENT0__SHIFT__SI 0x0000000c -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA0_CLIENT1__SHIFT__SI 0x0000000f -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA1_CLIENT0__SHIFT__SI 0x00000012 -#define SEM_MAILBOX_CLIENTCONFIG__DRMDMA1_CLIENT1__SHIFT__SI 0x00000015 -#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT__CI__VI 0x00000012 -#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT__CI__VI 0x0000000c -#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT__CI__VI 0x0000000f -#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT__CI__VI 0x00000015 -#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008 -#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x00000000 -#define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000008 -#define SEM_MAILBOX__SIDEPORT__SHIFT 0x00000000 -#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT__CI__VI 0x00000008 -#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000 -#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT__CI__VI 0x00000002 -#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT__CI__VI 0x00000005 -#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT__CI__VI 0x0000000c -#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT__CI__VI 0x0000000d -#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT__CI__VI 0x00000002 -#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT__CI__VI 0x00000006 -#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT__CI__VI 0x00000003 -#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT__CI__VI 0x00000007 -#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT__CI__VI 0x00000008 -#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT__CI__VI 0x00000009 -#define SEM_STATUS__SEM_IDLE__SHIFT__CI__VI 0x00000000 -#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT__CI__VI 0x00000001 -#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT__CI__VI 0x0000000a -#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT__CI__VI 0x0000000b -#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT__CI__VI 0x00000004 -#define SEQ00__SEQ_RST0B__SHIFT__SI 0x00000000 -#define SEQ00__SEQ_RST1B__SHIFT__SI 0x00000001 -#define SEQ01__SEQ_DOT8__SHIFT__SI 0x00000000 -#define SEQ01__SEQ_MAXBW__SHIFT__SI 0x00000005 -#define SEQ01__SEQ_PCLKBY2__SHIFT__SI 0x00000003 -#define SEQ01__SEQ_SHIFT2__SHIFT__SI 0x00000002 -#define SEQ01__SEQ_SHIFT4__SHIFT__SI 0x00000004 -#define SEQ02__SEQ_MAP0_EN__SHIFT__SI 0x00000000 -#define SEQ02__SEQ_MAP1_EN__SHIFT__SI 0x00000001 -#define SEQ02__SEQ_MAP2_EN__SHIFT__SI 0x00000002 -#define SEQ02__SEQ_MAP3_EN__SHIFT__SI 0x00000003 -#define SEQ03__SEQ_FONT_A0__SHIFT__SI 0x00000005 -#define SEQ03__SEQ_FONT_A1__SHIFT__SI 0x00000002 -#define SEQ03__SEQ_FONT_A2__SHIFT__SI 0x00000003 -#define SEQ03__SEQ_FONT_B0__SHIFT__SI 0x00000004 -#define SEQ03__SEQ_FONT_B1__SHIFT__SI 0x00000000 -#define SEQ03__SEQ_FONT_B2__SHIFT__SI 0x00000001 -#define SEQ04__SEQ_256K__SHIFT__SI 0x00000001 -#define SEQ04__SEQ_CHAIN__SHIFT__SI 0x00000003 -#define SEQ04__SEQ_ODDEVEN__SHIFT__SI 0x00000002 -#define SEQ8_DATA__SEQ_DATA__SHIFT__SI 0x00000000 -#define SEQ8_IDX__SEQ_IDX__SHIFT__SI 0x00000000 -#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x0000001f -#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x0000001c -#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x00000016 -#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000e -#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000015 -#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000f -#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x00000013 -#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x0000001d -#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000008 -#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x00000000 -#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x00000010 -#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x00000012 -#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000014 -#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000002 -#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x0000001e -#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x00000010 -#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x00000000 -#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x00000010 -#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x00000000 -#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x00000010 -#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x00000000 -#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 -#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000f -#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000013 -#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000014 -#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000018 -#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001f -#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001d -#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000e -#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x00000010 -#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x0000001a -#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000017 -#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000e -#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 -#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x0000001f -#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x0000001c -#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x0000001e -#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT__CI__VI 0x00000000 -#define SH_MEM_APE1_BASE__BASE__SHIFT__CI__VI 0x00000000 -#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT__CI__VI 0x00000000 -#define SH_MEM_BASES__PRIVATE_BASE__SHIFT__CI__VI 0x00000000 -#define SH_MEM_BASES__SHARED_BASE__SHIFT__CI__VI 0x00000010 -#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT__CI 0x00000002 -#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT__CI 0x00000007 -#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT__CI 0x00000004 -#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT__CI 0x00000001 -#define SH_MEM_CONFIG__PTR32__SHIFT__CI 0x00000000 -#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT__CI__VI 0x00000001 -#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT__CI__VI 0x00000003 -#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT__CI__VI 0x00000005 -#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT__CI__VI 0x00000008 -#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT__CI__VI 0x00000000 -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT__SI 0x00000000 -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT__SI 0x00000008 -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT__SI 0x00000010 -#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT__SI 0x00000018 -#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT__SI 0x00000008 -#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT__SI 0x00000000 -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT__SI 0x00000000 -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT__SI 0x00000008 -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT__SI 0x00000010 -#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT__SI 0x00000018 -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT__SI 0x00000000 -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT__SI 0x00000008 -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT__SI 0x00000010 -#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT__SI 0x00000018 -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT__SI 0x00000000 -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT__SI 0x00000008 -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT__SI 0x00000010 -#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT__SI 0x00000018 -#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x00000004 -#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT__CI__VI 0x00000005 -#define SLAVE_HANG_ERROR__CFG_HANG_ERROR__SHIFT__CI 0x00000006 -#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT__CI__VI 0x00000008 -#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT__CI__VI 0x00000009 -#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x00000001 -#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x00000003 -#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x00000000 -#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x00000002 -#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT__CI__VI 0x00000007 -#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_EN__SHIFT__SI 0x00000000 -#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x00000001 -#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x00000014 -#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0x0000000a -#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0x0000000f -#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x00000000 -#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x00000005 -#define SLOW_AES0__RESERVED__SHIFT 0x00000000 -#define SLOW_AES1__RESERVED__SHIFT 0x00000000 -#define SLOW_AES2__RESERVED__SHIFT 0x00000000 -#define SLOW_AES3__RESERVED__SHIFT 0x00000000 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT__CI__VI 0x00000000 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT__CI__VI 0x0000000c -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT__CI__VI 0x00000002 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT__CI__VI 0x0000000b -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT__CI__VI 0x00000001 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT__CI 0x00000009 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT__CI__VI 0x00000005 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT__CI__VI 0x00000006 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT__CI__VI 0x00000007 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT__CI__VI 0x00000008 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT__CI__VI 0x00000003 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT__CI__VI 0x0000000a -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT__CI__VI 0x00000000 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT__CI__VI 0x0000000c -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT__CI__VI 0x00000002 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT__CI__VI 0x0000000b -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT__CI__VI 0x00000001 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT__CI 0x00000009 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT__CI__VI 0x00000005 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT__CI__VI 0x00000006 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT__CI__VI 0x00000007 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT__CI__VI 0x00000008 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT__CI__VI 0x00000003 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT__CI__VI 0x0000000a -#define SMBUS_SLV_CNTL__SMB_SLV_ADR__SHIFT__CI 0x00000001 -#define SMBUS_SLV_CNTL__SMB_SOFT_RESET__SHIFT__CI 0x00000000 -#define SMC_ACP_RESP__ACK__SHIFT__CI__VI 0x00000000 -#define SMC_ACP_RESP__SCRATCH__SHIFT__CI__VI 0x00000008 -#define SMC_DBG_CNTL__DBG_CODE__SHIFT__CI__VI 0x00000000 -#define SMC_DBG_CNTL__SINGLE_STEP__SHIFT__CI__VI 0x00000008 -#define SMC_DEBUG_BUS__DEBUG_EN__SHIFT__SI 0x00000000 -#define SMC_DMA_CAPTURE_EN__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_0__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_1__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_2__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_3__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_CAPT_7__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_0__DMA_BUSY__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_0__RSVD__SHIFT 0x00000001 -#define SMC_DMA_CORE_STATUS_1__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_2__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_3__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_CORE_STATUS_7__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_0__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_1__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_2__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_3__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_CAPT_7__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_0__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_1__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_2__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_3__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DEVQ_STATUS_7__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_0__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_1__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_2__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_3__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_CAPT_7__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_0__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_1__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_2__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_3__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_DMEM_STATUS_7__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_CAPT_1__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_CAPT_2__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_CAPT_3__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_CAPT_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_CAPT_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_CAPT_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_CAPT_7__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_0__START_ADDR__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_1__END_ADDR__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_2__WR_ADDR__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_3__RD_ADDR__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_4__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_5__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_6__RSVD__SHIFT 0x00000000 -#define SMC_DMA_IMEMQ_STATUS_7__RSVD__SHIFT 0x00000000 -#define SMC_DRAM_ACCESS_CNTL__allow_dram_access__SHIFT__CI__VI 0x00000000 -#define SMC_DRAM_CNTL_RDREQ_ADDR__addr__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__addr_47_40__SHIFT__CI__VI 0x00000018 -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__mask__SHIFT 0x00000010 -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__reserved__SHIFT__SI 0x00000018 -#define SMC_DRAM_CNTL_RDREQ_CNTL_0__tag__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__atc__SHIFT__CI__VI 0x00000013 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__cid__SHIFT 0x00000008 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__priv__SHIFT 0x00000005 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__reserved__SHIFT__CI__VI 0x00000014 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__reserved__SHIFT__SI 0x00000013 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__stall__SHIFT 0x00000004 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__swap__SHIFT 0x00000006 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__urg__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDREQ_CNTL_1__vmid__SHIFT 0x00000010 -#define SMC_DRAM_CNTL_RDRET_DATA_0_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_0_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_0_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_0_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_0_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_0_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_0_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_0_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_1_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_2_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_3_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_4_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_5_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_6_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_0__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_1__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_2__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_3__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_4__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_5__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_6__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_DATA_7_7__DATA__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_NACK__nack_0__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_NACK__nack_1__SHIFT 0x00000002 -#define SMC_DRAM_CNTL_RDRET_NACK__nack_2__SHIFT 0x00000004 -#define SMC_DRAM_CNTL_RDRET_NACK__nack_3__SHIFT 0x00000006 -#define SMC_DRAM_CNTL_RDRET_NACK__nack_4__SHIFT 0x00000008 -#define SMC_DRAM_CNTL_RDRET_NACK__nack_5__SHIFT 0x0000000a -#define SMC_DRAM_CNTL_RDRET_NACK__nack_6__SHIFT 0x0000000c -#define SMC_DRAM_CNTL_RDRET_NACK__nack_7__SHIFT 0x0000000e -#define SMC_DRAM_CNTL_RDRET_NACK__reserved__SHIFT 0x00000010 -#define SMC_DRAM_CNTL_RDRET_VALID__reserved__SHIFT 0x00000008 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_0__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_1__SHIFT 0x00000001 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_2__SHIFT 0x00000002 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_3__SHIFT 0x00000003 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_4__SHIFT 0x00000004 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_5__SHIFT 0x00000005 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_6__SHIFT 0x00000006 -#define SMC_DRAM_CNTL_RDRET_VALID__vld_7__SHIFT 0x00000007 -#define SMC_DRAM_CNTL_WRREQ_CNTL__atc__SHIFT__CI__VI 0x0000001d -#define SMC_DRAM_CNTL_WRREQ_CNTL__cid__SHIFT 0x00000010 -#define SMC_DRAM_CNTL_WRREQ_CNTL__priv__SHIFT 0x0000000f -#define SMC_DRAM_CNTL_WRREQ_CNTL__stall__SHIFT 0x0000000e -#define SMC_DRAM_CNTL_WRREQ_CNTL__swap__SHIFT 0x00000018 -#define SMC_DRAM_CNTL_WRREQ_CNTL__tag__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_CNTL__urg__SHIFT 0x0000000a -#define SMC_DRAM_CNTL_WRREQ_CNTL__vmid__SHIFT 0x0000001a -#define SMC_DRAM_CNTL_WRREQ_DATA_0__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_DATA_1__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_DATA_2__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_DATA_3__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_DATA_4__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_DATA_5__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_DATA_6__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_DATA_7__data__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_39_37__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_40__SHIFT__CI__VI 0x00000003 -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT__CI__VI 0x0000000b -#define SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT__SI 0x00000003 -#define SMC_DRAM_CNTL_WRREQ_LOW_ADDR__addr__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_MASK__mask__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_STATUS__credit_counter__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty__SHIFT 0x00000008 -#define SMC_DRAM_CNTL_WRREQ_STATUS__reserved0__SHIFT 0x00000005 -#define SMC_DRAM_CNTL_WRREQ_STATUS__reserved1__SHIFT 0x00000009 -#define SMC_DRAM_CNTL_WRREQ_STATUS__reserved2__SHIFT 0x00000014 -#define SMC_DRAM_CNTL_WRREQ_STATUS__tag_pointer__SHIFT 0x00000010 -#define SMC_DRAM_CNTL_WRRET_STATUS_0__nack__SHIFT 0x00000001 -#define SMC_DRAM_CNTL_WRRET_STATUS_0__reserved__SHIFT 0x00000003 -#define SMC_DRAM_CNTL_WRRET_STATUS_0__tag__SHIFT 0x00000010 -#define SMC_DRAM_CNTL_WRRET_STATUS_0__valid__SHIFT 0x00000000 -#define SMC_DRAM_CNTL_WRRET_STATUS_1__nack__SHIFT__SI 0x00000001 -#define SMC_DRAM_CNTL_WRRET_STATUS_1__reserved__SHIFT__SI 0x00000003 -#define SMC_DRAM_CNTL_WRRET_STATUS_1__tag__SHIFT__SI 0x00000010 -#define SMC_DRAM_CNTL_WRRET_STATUS_1__valid__SHIFT__SI 0x00000000 -#define SMC_DRAM_CNTL_WRRET_STATUS_2__nack__SHIFT__SI 0x00000001 -#define SMC_DRAM_CNTL_WRRET_STATUS_2__reserved__SHIFT__SI 0x00000003 -#define SMC_DRAM_CNTL_WRRET_STATUS_2__tag__SHIFT__SI 0x00000010 -#define SMC_DRAM_CNTL_WRRET_STATUS_2__valid__SHIFT__SI 0x00000000 -#define SMC_DRAM_CNTL_WRRET_STATUS_3__nack__SHIFT__SI 0x00000001 -#define SMC_DRAM_CNTL_WRRET_STATUS_3__reserved__SHIFT__SI 0x00000003 -#define SMC_DRAM_CNTL_WRRET_STATUS_3__tag__SHIFT__SI 0x00000010 -#define SMC_DRAM_CNTL_WRRET_STATUS_3__valid__SHIFT__SI 0x00000000 -#define SMC_EVENT_CLEAR__AZALIA__SHIFT__SI 0x00000001 -#define SMC_EVENT_CLEAR__BIF__SHIFT__SI 0x00000002 -#define SMC_EVENT_CLEAR__DC__SHIFT__SI 0x00000003 -#define SMC_EVENT_CLEAR__DISPLAY_GAP__SHIFT__SI 0x00000000 -#define SMC_EVENT_CLEAR__MCB__SHIFT__SI 0x00000004 -#define SMC_EVENT_CLEAR__MCD0__SHIFT__SI 0x00000005 -#define SMC_EVENT_CLEAR__MCD1__SHIFT__SI 0x00000006 -#define SMC_EVENT_CLEAR__MCD2__SHIFT__SI 0x00000007 -#define SMC_EVENT_CLEAR__MCD3__SHIFT__SI 0x00000008 -#define SMC_EVENT_PENDING__AZALIA__SHIFT__SI 0x00000001 -#define SMC_EVENT_PENDING__BIF__SHIFT__SI 0x00000002 -#define SMC_EVENT_PENDING__DC__SHIFT__SI 0x00000003 -#define SMC_EVENT_PENDING__DISPLAY_GAP__SHIFT__SI 0x00000000 -#define SMC_EVENT_PENDING__MCB__SHIFT__SI 0x00000004 -#define SMC_EVENT_PENDING__MCD0__SHIFT__SI 0x00000005 -#define SMC_EVENT_PENDING__MCD1__SHIFT__SI 0x00000006 -#define SMC_EVENT_PENDING__MCD2__SHIFT__SI 0x00000007 -#define SMC_EVENT_PENDING__MCD3__SHIFT__SI 0x00000008 -#define SMC_EVENT_POLARITY__AZALIA__SHIFT__SI 0x00000001 -#define SMC_EVENT_POLARITY__BIF__SHIFT__SI 0x00000002 -#define SMC_EVENT_POLARITY__DC__SHIFT__SI 0x00000003 -#define SMC_EVENT_POLARITY__DISPLAY_GAP__SHIFT__SI 0x00000000 -#define SMC_EVENT_POLARITY__MCB__SHIFT__SI 0x00000004 -#define SMC_EVENT_POLARITY__MCD0__SHIFT__SI 0x00000005 -#define SMC_EVENT_POLARITY__MCD1__SHIFT__SI 0x00000006 -#define SMC_EVENT_POLARITY__MCD2__SHIFT__SI 0x00000007 -#define SMC_EVENT_POLARITY__MCD3__SHIFT__SI 0x00000008 -#define SMC_EVENT_SENSE__AZALIA__SHIFT__SI 0x00000001 -#define SMC_EVENT_SENSE__BIF__SHIFT__SI 0x00000002 -#define SMC_EVENT_SENSE__DC__SHIFT__SI 0x00000003 -#define SMC_EVENT_SENSE__DISPLAY_GAP__SHIFT__SI 0x00000000 -#define SMC_EVENT_SENSE__MCB__SHIFT__SI 0x00000004 -#define SMC_EVENT_SENSE__MCD0__SHIFT__SI 0x00000005 -#define SMC_EVENT_SENSE__MCD1__SHIFT__SI 0x00000006 -#define SMC_EVENT_SENSE__MCD2__SHIFT__SI 0x00000007 -#define SMC_EVENT_SENSE__MCD3__SHIFT__SI 0x00000008 -#define SMC_HOST_MSG__SMC_HOST_msg__SHIFT 0x00000000 -#define SMC_HOST_RESP__SMC_HOST_resp__SHIFT 0x00000000 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x00000000 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT__CI__VI 0x00000001 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT__SI 0x00000008 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT__CI__VI 0x00000002 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT__SI 0x00000010 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT__CI__VI 0x00000003 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT__SI 0x00000018 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT__CI__VI 0x00000004 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT__CI__VI 0x00000005 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT__CI__VI 0x00000006 -#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT__CI__VI 0x00000007 -#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x00000000 -#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x00000000 -#define SMC_INTR_CNTL_INTR_ID__INTR_ID__SHIFT 0x00000000 -#define SMC_INTR_CNTL_INTR_ID__RESERVED__SHIFT 0x00000008 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_10__SHIFT 0x0000000a -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_11__SHIFT 0x0000000b -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_12__SHIFT 0x0000000c -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_13__SHIFT 0x0000000d -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_14__SHIFT 0x0000000e -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_15__SHIFT 0x0000000f -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_16__SHIFT 0x00000010 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_17__SHIFT 0x00000011 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_18__SHIFT 0x00000012 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_19__SHIFT 0x00000013 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_20__SHIFT 0x00000014 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_21__SHIFT 0x00000015 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_22__SHIFT 0x00000016 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_23__SHIFT 0x00000017 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_24__SHIFT 0x00000018 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_25__SHIFT 0x00000019 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_26__SHIFT 0x0000001a -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_27__SHIFT 0x0000001b -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_28__SHIFT 0x0000001c -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_29__SHIFT 0x0000001d -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_30__SHIFT 0x0000001e -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_31__SHIFT 0x0000001f -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_7__SHIFT 0x00000007 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_8__SHIFT 0x00000008 -#define SMC_INTR_CNTL_LEVEL_0__INTR_TRIGGER_9__SHIFT 0x00000009 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_10__SHIFT 0x0000000a -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_11__SHIFT 0x0000000b -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_12__SHIFT 0x0000000c -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_13__SHIFT 0x0000000d -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_14__SHIFT 0x0000000e -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_15__SHIFT 0x0000000f -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_16__SHIFT 0x00000010 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_17__SHIFT 0x00000011 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_18__SHIFT 0x00000012 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_19__SHIFT 0x00000013 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_1__SHIFT 0x00000001 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_20__SHIFT 0x00000014 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_21__SHIFT 0x00000015 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_22__SHIFT 0x00000016 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_23__SHIFT 0x00000017 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_24__SHIFT 0x00000018 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_25__SHIFT 0x00000019 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_26__SHIFT 0x0000001a -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_27__SHIFT 0x0000001b -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_28__SHIFT 0x0000001c -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_29__SHIFT 0x0000001d -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_2__SHIFT 0x00000002 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_30__SHIFT 0x0000001e -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_31__SHIFT 0x0000001f -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_3__SHIFT 0x00000003 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_4__SHIFT 0x00000004 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_5__SHIFT 0x00000005 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_6__SHIFT 0x00000006 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_7__SHIFT 0x00000007 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_8__SHIFT 0x00000008 -#define SMC_INTR_CNTL_LEVEL_1__INTR_TRIGGER_9__SHIFT 0x00000009 -#define SMC_INTR_CNTL_LINE__INTR_LINE__SHIFT 0x00000000 -#define SMC_INTR_CNTL_LINE__RESERVED__SHIFT 0x00000001 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_10__SHIFT 0x0000000a -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_11__SHIFT 0x0000000b -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_12__SHIFT 0x0000000c -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_13__SHIFT 0x0000000d -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_14__SHIFT 0x0000000e -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_15__SHIFT 0x0000000f -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_16__SHIFT 0x00000010 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_17__SHIFT 0x00000011 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_18__SHIFT 0x00000012 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_19__SHIFT 0x00000013 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_1__SHIFT 0x00000001 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_20__SHIFT 0x00000014 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_21__SHIFT 0x00000015 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_22__SHIFT 0x00000016 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_23__SHIFT 0x00000017 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_24__SHIFT 0x00000018 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_25__SHIFT 0x00000019 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_26__SHIFT 0x0000001a -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_27__SHIFT 0x0000001b -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_28__SHIFT 0x0000001c -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_29__SHIFT 0x0000001d -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_2__SHIFT 0x00000002 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_30__SHIFT 0x0000001e -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_31__SHIFT 0x0000001f -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_3__SHIFT 0x00000003 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_4__SHIFT 0x00000004 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_5__SHIFT 0x00000005 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_6__SHIFT 0x00000006 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_7__SHIFT 0x00000007 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_8__SHIFT 0x00000008 -#define SMC_INTR_CNTL_MASK_0__INTR_MASK_9__SHIFT 0x00000009 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_10__SHIFT 0x0000000a -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_11__SHIFT 0x0000000b -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_12__SHIFT 0x0000000c -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_13__SHIFT 0x0000000d -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_14__SHIFT 0x0000000e -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_15__SHIFT 0x0000000f -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_16__SHIFT 0x00000010 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_17__SHIFT 0x00000011 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_18__SHIFT 0x00000012 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_19__SHIFT 0x00000013 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_1__SHIFT 0x00000001 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_20__SHIFT 0x00000014 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_21__SHIFT 0x00000015 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_22__SHIFT 0x00000016 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_23__SHIFT 0x00000017 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_24__SHIFT 0x00000018 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_25__SHIFT 0x00000019 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_26__SHIFT 0x0000001a -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_27__SHIFT 0x0000001b -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_28__SHIFT 0x0000001c -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_29__SHIFT 0x0000001d -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_2__SHIFT 0x00000002 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_30__SHIFT 0x0000001e -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_31__SHIFT 0x0000001f -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_3__SHIFT 0x00000003 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_4__SHIFT 0x00000004 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_5__SHIFT 0x00000005 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_6__SHIFT 0x00000006 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_7__SHIFT 0x00000007 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_8__SHIFT 0x00000008 -#define SMC_INTR_CNTL_MASK_1__INTR_MASK_9__SHIFT 0x00000009 -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_0__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_10__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_11__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_12__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_13__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_14__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_15__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_1__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_2__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_3__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_4__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_5__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_6__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_7__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_8__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_1__SHIFT 0x00000008 -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_2__SHIFT 0x00000010 -#define SMC_INTR_CNTL_PRIORITY_9__INTR_PRIORITY_3__SHIFT 0x00000018 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_10__SHIFT 0x0000000a -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_11__SHIFT 0x0000000b -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_12__SHIFT 0x0000000c -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_13__SHIFT 0x0000000d -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_14__SHIFT 0x0000000e -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_15__SHIFT 0x0000000f -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_16__SHIFT 0x00000010 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_17__SHIFT 0x00000011 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_18__SHIFT 0x00000012 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_19__SHIFT 0x00000013 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_1__SHIFT 0x00000001 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_20__SHIFT 0x00000014 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_21__SHIFT 0x00000015 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_22__SHIFT 0x00000016 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_23__SHIFT 0x00000017 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_24__SHIFT 0x00000018 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_25__SHIFT 0x00000019 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_26__SHIFT 0x0000001a -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_27__SHIFT 0x0000001b -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_28__SHIFT 0x0000001c -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_29__SHIFT 0x0000001d -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_2__SHIFT 0x00000002 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_30__SHIFT 0x0000001e -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_31__SHIFT 0x0000001f -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_3__SHIFT 0x00000003 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_4__SHIFT 0x00000004 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_5__SHIFT 0x00000005 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_6__SHIFT 0x00000006 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_7__SHIFT 0x00000007 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_8__SHIFT 0x00000008 -#define SMC_INTR_CNTL_STATUS_0__INTR_FLAG_9__SHIFT 0x00000009 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_0__SHIFT 0x00000000 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_10__SHIFT 0x0000000a -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_11__SHIFT 0x0000000b -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_12__SHIFT 0x0000000c -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_13__SHIFT 0x0000000d -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_14__SHIFT 0x0000000e -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_15__SHIFT 0x0000000f -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_16__SHIFT 0x00000010 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_17__SHIFT 0x00000011 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_18__SHIFT 0x00000012 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_19__SHIFT 0x00000013 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_1__SHIFT 0x00000001 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_20__SHIFT 0x00000014 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_21__SHIFT 0x00000015 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_22__SHIFT 0x00000016 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_23__SHIFT 0x00000017 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_24__SHIFT 0x00000018 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_25__SHIFT 0x00000019 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_26__SHIFT 0x0000001a -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_27__SHIFT 0x0000001b -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_28__SHIFT 0x0000001c -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_29__SHIFT 0x0000001d -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_2__SHIFT 0x00000002 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_30__SHIFT 0x0000001e -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_31__SHIFT 0x0000001f -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_3__SHIFT 0x00000003 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_4__SHIFT 0x00000004 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_5__SHIFT 0x00000005 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_6__SHIFT 0x00000006 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_7__SHIFT 0x00000007 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_8__SHIFT 0x00000008 -#define SMC_INTR_CNTL_STATUS_1__INTR_FLAG_9__SHIFT 0x00000009 -#define SMC_INT_GPIO_CLEAR__INT_GPIO_CLEAR__SHIFT__SI 0x00000000 -#define SMC_INT_GPIO_PENDING__INT_GPIO_PENDING__SHIFT__SI 0x00000000 -#define SMC_INT_GPIO_POLARITY__INT_GPIO_POLARITY__SHIFT__SI 0x00000000 -#define SMC_INT_GPIO_SENSE__INT_GPIO_SENSE__SHIFT__SI 0x00000000 -#define SMC_INT_REQ__INT_REQ__SHIFT__SI 0x00000000 -#define SMC_INT_REQ__RESERVED__SHIFT__SI 0x00000001 -#define SMC_INT_REQ__SERV_INDEX__SHIFT__SI 0x00000010 -#define SMC_INT_STATUS__INT_ACK__SHIFT__SI 0x00000000 -#define SMC_INT_STATUS__INT_DONE__SHIFT__SI 0x00000001 -#define SMC_LM32_ADDER0__operand_0__SHIFT 0x00000000 -#define SMC_LM32_ADDER1__operand_1__SHIFT 0x00000000 -#define SMC_LM32_ADDER2__result__SHIFT 0x00000000 -#define SMC_LM32_ARITH_MISC__adder_carry_n__SHIFT 0x00000001 -#define SMC_LM32_ARITH_MISC__adder_op__SHIFT 0x00000000 -#define SMC_LM32_ARITH_MISC__adder_overflow__SHIFT 0x00000002 -#define SMC_LM32_ARITH_MISC__mc_arith_divide__SHIFT 0x00000003 -#define SMC_LM32_ARITH_MISC__mc_arith_divide_by_0__SHIFT 0x00000005 -#define SMC_LM32_ARITH_MISC__mc_arith_modulus__SHIFT 0x00000004 -#define SMC_LM32_BP0__BP_ADDR__SHIFT 0x00000002 -#define SMC_LM32_BP0__BP_EN__SHIFT 0x00000000 -#define SMC_LM32_BP1__BP_ADDR__SHIFT 0x00000002 -#define SMC_LM32_BP1__BP_EN__SHIFT 0x00000000 -#define SMC_LM32_BP2__BP_ADDR__SHIFT 0x00000002 -#define SMC_LM32_BP2__BP_EN__SHIFT 0x00000000 -#define SMC_LM32_BP3__BP_ADDR__SHIFT 0x00000002 -#define SMC_LM32_BP3__BP_EN__SHIFT 0x00000000 -#define SMC_LM32_DC__C0__SHIFT 0x00000002 -#define SMC_LM32_DC__C1__SHIFT 0x00000004 -#define SMC_LM32_DC__C2__SHIFT 0x00000006 -#define SMC_LM32_DC__C3__SHIFT 0x00000008 -#define SMC_LM32_DC__REMAP_EXCEPTIONS__SHIFT 0x00000001 -#define SMC_LM32_DC__SINGLE_STEP__SHIFT 0x00000000 -#define SMC_LM32_DEBA__DEBA__SHIFT 0x00000008 -#define SMC_LM32_GPR_0__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_10__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_11__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_12__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_13__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_14__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_15__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_16__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_17__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_18__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_19__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_1__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_20__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_21__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_22__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_23__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_24__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_25__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_26__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_27__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_28__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_29__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_2__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_30__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_31__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_3__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_4__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_5__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_6__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_7__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_8__gpr__SHIFT 0x00000000 -#define SMC_LM32_GPR_9__gpr__SHIFT 0x00000000 -#define SMC_LM32_MC_ARITH__result__SHIFT 0x00000000 -#define SMC_LM32_MULTIPLIER__result__SHIFT 0x00000000 -#define SMC_LM32_MULT_MC0__operand_0__SHIFT 0x00000000 -#define SMC_LM32_MULT_MC1__operand_1__SHIFT 0x00000000 -#define SMC_LM32_WP0__WP_ADDR__SHIFT 0x00000000 -#define SMC_LM32_WP1__WP_ADDR__SHIFT 0x00000000 -#define SMC_LM32_WP2__WP_ADDR__SHIFT 0x00000000 -#define SMC_LM32_WP3__WP_ADDR__SHIFT 0x00000000 -#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x00000000 -#define SMC_MESSAGE_10__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_11__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x00000000 -#define SMC_MESSAGE_2__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_3__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_4__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_5__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_6__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_7__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_8__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MESSAGE_9__SMC_MSG__SHIFT__CI__VI 0x00000000 -#define SMC_MISC_HANDSHAKE__CGPG_DONE__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT__CI__VI 0x00000000 -#define SMC_MUTEX_0__MUTEX_0__SHIFT__CI__VI 0x00000000 -#define SMC_MUTEX_1__MUTEX__SHIFT__CI__VI 0x00000000 -#define SMC_MUTEX_2__MUTEX__SHIFT__CI__VI 0x00000000 -#define SMC_MUTEX_3__MUTEX__SHIFT__CI__VI 0x00000000 -#define SMC_PC_A__smc_pc_a__SHIFT__CI__VI 0x00000000 -#define SMC_PC_C__smc_pc_c__SHIFT__CI__VI 0x00000000 -#define SMC_PC_D__smc_pc_d__SHIFT__CI__VI 0x00000000 -#define SMC_PC_F__smc_pc_f__SHIFT__CI__VI 0x00000000 -#define SMC_PC_M__smc_pc_m__SHIFT__CI__VI 0x00000000 -#define SMC_PC_TRACE_0_BR_INST__branch_instruction_0__SHIFT 0x00000000 -#define SMC_PC_TRACE_0_BR_TAR__branch_target_0__SHIFT 0x00000000 -#define SMC_PC_TRACE_1_BR_INST__branch_instruction_1__SHIFT 0x00000000 -#define SMC_PC_TRACE_1_BR_TAR__branch_target_1__SHIFT 0x00000000 -#define SMC_PC_TRACE_2_BR_INST__branch_instruction_2__SHIFT 0x00000000 -#define SMC_PC_TRACE_2_BR_TAR__branch_target_2__SHIFT 0x00000000 -#define SMC_PC_TRACE_3_BR_INST__branch_instruction_3__SHIFT 0x00000000 -#define SMC_PC_TRACE_3_BR_TAR__branch_target_3__SHIFT 0x00000000 -#define SMC_PC_W__smc_pc_w__SHIFT__CI__VI 0x00000000 -#define SMC_PC_X__smc_pc_x__SHIFT__CI__VI 0x00000000 -#define SMC_PC__smc_pc__SHIFT__SI 0x00000000 -#define SMC_RAMFLOP_0__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_10__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_11__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_12__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_13__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_14__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_15__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_16__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_17__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_18__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_19__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_1__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_20__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_21__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_22__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_23__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_24__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_25__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_26__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_27__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_28__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_29__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_2__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_30__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_31__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_3__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_4__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_5__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_6__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_7__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_8__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RAMFLOP_9__DATA__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_0__SMC_RESP__SHIFT 0x00000000 -#define SMC_RESP_10__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_11__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_1__SMC_RESP__SHIFT 0x00000000 -#define SMC_RESP_2__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_3__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_4__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_5__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_6__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_7__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_8__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_RESP_9__SMC_RESP__SHIFT__CI__VI 0x00000000 -#define SMC_SCRATCH0__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH10__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH11__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH12__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH1__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH2__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH3__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH4__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH5__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH6__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH7__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH8__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x00000000 -#define SMC_SP__SP__SHIFT__CI__VI 0x00000000 -#define SMC_SRBM_CREDITS__CREDIT_NUM__SHIFT 0x00000000 -#define SMC_SW_INT_CTXID__CTXID__SHIFT__CI__VI 0x00000000 -#define SMC_SW_INT__ID__SHIFT__CI__VI 0x00000000 -#define SMC_SW_INT__VALID__SHIFT__CI__VI 0x00000008 -#define SMC_SYSCON_ACP_RESP__ACK__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_ACP_RESP__SCRATCH__SHIFT__CI__VI 0x00000008 -#define SMC_SYSCON_DBG_CNTL__DBG_CODE__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_DBG_CNTL__SINGLE_STEP__SHIFT__CI__VI 0x00000008 -#define SMC_SYSCON_GPIO_IN_0__gpio_in__SHIFT 0x00000000 -#define SMC_SYSCON_GPIO_IN_1__gpio_in__SHIFT 0x00000000 -#define SMC_SYSCON_GPIO_IN_2__gpio_in__SHIFT 0x00000000 -#define SMC_SYSCON_GPIO_IN_3__gpio_in__SHIFT 0x00000000 -#define SMC_SYSCON_GPIO_OUT_0__gpio_out__SHIFT 0x00000000 -#define SMC_SYSCON_GPIO_OUT_1__gpio_out__SHIFT 0x00000000 -#define SMC_SYSCON_GPIO_OUT_2__gpio_out__SHIFT 0x00000000 -#define SMC_SYSCON_GPIO_OUT_3__gpio_out__SHIFT 0x00000000 -#define SMC_SYSCON_HOST_RAM_PWRDN_0_1__host_ram_pwrdn_0_reg__SHIFT__SI 0x00000000 -#define SMC_SYSCON_HOST_RAM_PWRDN_0_1__host_ram_pwrdn_1_reg__SHIFT__SI 0x00000010 -#define SMC_SYSCON_HOST_RAM_PWRDN_0__host_ram_pwrdn_0_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_HOST_RAM_PWRDN_1__host_ram_pwrdn_1_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_HOST_RAM_PWRDN_2_3__host_ram_pwrdn_2_reg__SHIFT__SI 0x00000000 -#define SMC_SYSCON_HOST_RAM_PWRDN_2_3__host_ram_pwrdn_3_reg__SHIFT__SI 0x00000010 -#define SMC_SYSCON_HOST_RAM_PWRDN_2__host_ram_pwrdn_2_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_HOST_RAM_PWRDN_3__host_ram_pwrdn_3_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_HOST_RAM_PWRDN_4__host_ram_pwrdn_4_reg__SHIFT 0x00000000 -#define SMC_SYSCON_INTR_SERVICE_INDEX__drv_service_index__SHIFT__SI 0x00000000 -#define SMC_SYSCON_INTR_STATUS__drv_intr_req_ack__SHIFT__SI 0x00000000 -#define SMC_SYSCON_INTR_STATUS__drv_intr_req_done__SHIFT__SI 0x00000008 -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_auto_cg_en__SHIFT 0x00000001 -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_auto_cg_timeout__SHIFT 0x00000008 -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_ck_disable__SHIFT 0x00000000 -#define SMC_SYSCON_LM32_CLOCK_CNTL_0__lm32_cken__SHIFT 0x00000018 -#define SMC_SYSCON_LM32_CLOCK_CNTL_1__lm32_auto_ck_disable__SHIFT 0x00000000 -#define SMC_SYSCON_LM32_CLOCK_CNTL_2__lm32_wake_on_irq__SHIFT 0x00000000 -#define SMC_SYSCON_LM32_RESET_CNTL__ColdReset__SHIFT__SI 0x0000001f -#define SMC_SYSCON_LM32_RESET_CNTL__RegReset__SHIFT 0x0000001e -#define SMC_SYSCON_LM32_RESET_CNTL__lm32_rst_reg__SHIFT 0x00000000 -#define SMC_SYSCON_LM32_RESET_CNTL__srbm_soft_rst_override__SHIFT__CI__VI 0x00000001 -#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_0__smc_msg__SHIFT 0x00000000 -#define SMC_SYSCON_MSG_10__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_11__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_1__smc_msg__SHIFT 0x00000000 -#define SMC_SYSCON_MSG_2__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_3__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_4__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_5__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_6__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_7__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_8__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_9__smc_msg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_10__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_11__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_1__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_2__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_3__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_4__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_5__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_6__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_7__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_8__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_ARG_9__smc_msg_arg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_0__smc_resp__SHIFT 0x00000000 -#define SMC_SYSCON_MSG_RESP_10__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_11__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_1__smc_resp__SHIFT 0x00000000 -#define SMC_SYSCON_MSG_RESP_2__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_3__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_4__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_5__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_6__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_7__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_8__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSG_RESP_9__smc_resp__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MSTRCFG_0__mbus2_mstr_cg_override__SHIFT 0x0000001e -#define SMC_SYSCON_MSTRCFG_0__mbus2_mstr_disable__SHIFT 0x0000001f -#define SMC_SYSCON_MSTRCFG_0__mbus2_mstr_pri__SHIFT 0x00000000 -#define SMC_SYSCON_MSTRCFG_1__mbus2_mstr_cg_override__SHIFT 0x0000001e -#define SMC_SYSCON_MSTRCFG_1__mbus2_mstr_disable__SHIFT 0x0000001f -#define SMC_SYSCON_MSTRCFG_1__mbus2_mstr_pri__SHIFT 0x00000000 -#define SMC_SYSCON_MSTRCFG_2__mbus2_mstr_cg_override__SHIFT 0x0000001e -#define SMC_SYSCON_MSTRCFG_2__mbus2_mstr_disable__SHIFT 0x0000001f -#define SMC_SYSCON_MSTRCFG_2__mbus2_mstr_pri__SHIFT 0x00000000 -#define SMC_SYSCON_MSTRCFG_3__mbus2_mstr_cg_override__SHIFT 0x0000001e -#define SMC_SYSCON_MSTRCFG_3__mbus2_mstr_disable__SHIFT 0x0000001f -#define SMC_SYSCON_MSTRCFG_3__mbus2_mstr_pri__SHIFT 0x00000000 -#define SMC_SYSCON_MSTRCFG_4__mbus2_mstr_cg_override__SHIFT 0x0000001e -#define SMC_SYSCON_MSTRCFG_4__mbus2_mstr_disable__SHIFT 0x0000001f -#define SMC_SYSCON_MSTRCFG_4__mbus2_mstr_pri__SHIFT 0x00000000 -#define SMC_SYSCON_MSTRCFG_5__mbus2_mstr_cg_override__SHIFT__CI__VI 0x0000001e -#define SMC_SYSCON_MSTRCFG_5__mbus2_mstr_disable__SHIFT__CI__VI 0x0000001f -#define SMC_SYSCON_MSTRCFG_5__mbus2_mstr_pri__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MUTEX_0__MUTEX_0__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MUTEX_1__MUTEX_1__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MUTEX_2__MUTEX_2__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_MUTEX_3__MUTEX_3__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_RAM_CFG__MEB_timeout__SHIFT 0x00000008 -#define SMC_SYSCON_RAM_CFG__ram_arb_scheme__SHIFT 0x00000000 -#define SMC_SYSCON_RAM_CFG__ram_read_pipeline__SHIFT 0x00000001 -#define SMC_SYSCON_SLVCFG__mbus2_slv_cg_en__SHIFT 0x0000001f -#define SMC_SYSCON_SLVCFG__mbus2_slv_cg_timeout__SHIFT 0x00000000 -#define SMC_SYSCON_SP__SP__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_UC_RAM_PWRDN_0_1__uc_ram_pwrdn_0_reg__SHIFT__SI 0x00000000 -#define SMC_SYSCON_UC_RAM_PWRDN_0_1__uc_ram_pwrdn_1_reg__SHIFT__SI 0x00000010 -#define SMC_SYSCON_UC_RAM_PWRDN_0__uc_ram_pwrdn_0_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_UC_RAM_PWRDN_1__uc_ram_pwrdn_1_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_UC_RAM_PWRDN_2_3__uc_ram_pwrdn_2_reg__SHIFT__SI 0x00000000 -#define SMC_SYSCON_UC_RAM_PWRDN_2_3__uc_ram_pwrdn_3_reg__SHIFT__SI 0x00000010 -#define SMC_SYSCON_UC_RAM_PWRDN_2__uc_ram_pwrdn_2_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_UC_RAM_PWRDN_3__uc_ram_pwrdn_3_reg__SHIFT__CI__VI 0x00000000 -#define SMC_SYSCON_UC_RAM_PWRDN_4__uc_ram_pwrdn_4_reg__SHIFT 0x00000000 -#define SMC_TIMER_0_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_0_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_0_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_0_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_0_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_0_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_0_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_0_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_0_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_0_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_0_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_0_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_0_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_0_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_0_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_0_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_0_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_0_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_0_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_0_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_0_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_0_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_0_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_0_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_0_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_0_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_0_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_0_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_1_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_1_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_1_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_1_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_1_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_1_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_1_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_1_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_1_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_1_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_1_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_1_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_1_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_1_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_1_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_1_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_1_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_1_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_1_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_1_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_1_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_1_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_1_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_1_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_1_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_1_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_1_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_1_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_2_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_2_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_2_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_2_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_2_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_2_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_2_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_2_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_2_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_2_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_2_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_2_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_2_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_2_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_2_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_2_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_2_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_2_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_2_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_2_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_2_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_2_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_2_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_2_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_2_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_2_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_2_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_2_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_3_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_3_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_3_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_3_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_3_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_3_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_3_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_3_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_3_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_3_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_3_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_3_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_3_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_3_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_3_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_3_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_3_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_3_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_3_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_3_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_3_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_3_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_3_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_3_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_3_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_3_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_3_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_3_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_4_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_4_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_4_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_4_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_4_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_4_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_4_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_4_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_4_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_4_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_4_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_4_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_4_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_4_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_4_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_4_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_4_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_4_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_4_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_4_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_4_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_4_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_4_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_4_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_4_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_4_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_4_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_4_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_5_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_5_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_5_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_5_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_5_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_5_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_5_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_5_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_5_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_5_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_5_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_5_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_5_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_5_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_5_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_5_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_5_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_5_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_5_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_5_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_5_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_5_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_5_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_5_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_5_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_5_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_5_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_5_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_6_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_6_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_6_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_6_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_6_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_6_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_6_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_6_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_6_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_6_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_6_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_6_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_6_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_6_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_6_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_6_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_6_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_6_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_6_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_6_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_6_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_6_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_6_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_6_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_6_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_6_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_6_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_6_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_7_0_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_7_1_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_7_2_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_7_3_OCMP__DATA__SHIFT 0x00000000 -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_7_CMP_AUTOINC__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_7_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 -#define SMC_TIMER_7_CNT__VALUE__SHIFT 0x00000000 -#define SMC_TIMER_7_CTRL_0__CLEAR__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_7_CTRL_0__CLEAR__SHIFT__SI 0x00000008 -#define SMC_TIMER_7_CTRL_0__DEC__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_7_CTRL_0__DEC__SHIFT__SI 0x00000010 -#define SMC_TIMER_7_CTRL_0__PULSE_COUNT_MODE__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_7_CTRL_0__PULSE_COUNT_MODE__SHIFT__SI 0x00000018 -#define SMC_TIMER_7_CTRL_0__START__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_7_CTRL_0__START__SHIFT__SI 0x00000000 -#define SMC_TIMER_7_CTRL_1__PWM_OUTPUT_EN__SHIFT__CI__VI 0x00000018 -#define SMC_TIMER_7_CTRL_1__PWM_OUTPUT_EN__SHIFT__SI 0x00000000 -#define SMC_TIMER_7_CTRL_1__RESERVED__SHIFT__CI__VI 0x00000000 -#define SMC_TIMER_7_CTRL_1__RESERVED__SHIFT__SI 0x00000011 -#define SMC_TIMER_7_CTRL_1__TIMER_SATURATION_EN__SHIFT__CI__VI 0x00000008 -#define SMC_TIMER_7_CTRL_1__TIMER_SATURATION_EN__SHIFT__SI 0x00000010 -#define SMC_TIMER_7_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__CI__VI 0x00000010 -#define SMC_TIMER_7_CTRL_1__TIME_SLICE_MODE_EN__SHIFT__SI 0x00000008 -#define SMC_TIMER_7_INTERRUPT__ENABLE_0__SHIFT 0x00000000 -#define SMC_TIMER_7_INTERRUPT__ENABLE_1__SHIFT 0x00000001 -#define SMC_TIMER_7_INTERRUPT__ENABLE_2__SHIFT 0x00000002 -#define SMC_TIMER_7_INTERRUPT__ENABLE_3__SHIFT 0x00000003 -#define SMC_TIMER_7_INTERRUPT__RESERVED__SHIFT 0x00000004 -#define SMC_UART_CFG__clk_div__SHIFT__SI__CI 0x00000000 -#define SMC_UART_CG_CNTL__rx_clk_en_override__SHIFT__CI 0x00000001 -#define SMC_UART_CG_CNTL__tx_clk_en_override__SHIFT__CI 0x00000000 -#define SMC_UART_RXQ_STATUS__rx_byte__SHIFT__SI__CI 0x00000000 -#define SMC_UART_RXQ_STATUS__rx_frame_error__SHIFT__SI__CI 0x00000008 -#define SMC_UART_RXQ_STATUS__rxq_count__SHIFT__SI__CI 0x0000000c -#define SMC_UART_RXQ_STATUS__rxq_empty__SHIFT__SI__CI 0x00000009 -#define SMC_UART_RXQ_STATUS__rxq_full__SHIFT__SI__CI 0x0000000a -#define SMC_UART_RXQ_STATUS__rxq_overflow__SHIFT__SI__CI 0x0000000b -#define SMC_UART_RX_CFG__internal_loopback__SHIFT__SI__CI 0x00000001 -#define SMC_UART_RX_CFG__rx_ena__SHIFT__SI__CI 0x00000000 -#define SMC_UART_TX_Q__tx_byte__SHIFT__SI__CI 0x00000000 -#define SMC_UART_TX_STATUS__txq_count__SHIFT__SI__CI 0x00000000 -#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x00000000 -#define SMU_AUTH_STATUS__SMU_AUTH_DONE__SHIFT__CI__VI 0x00000000 -#define SMU_AUTH_STATUS__SMU_AUTH_PASS__SHIFT__CI__VI 0x00000001 -#define SMU_BLOCKED_DATA__blocked_data__SHIFT__CI__VI 0x00000000 -#define SMU_BRIDGE_MSTRCFG__mbus2_mstr_cg_override__SHIFT__CI__VI 0x0000001e -#define SMU_BRIDGE_MSTRCFG__mbus2_mstr_disable__SHIFT__CI__VI 0x0000001f -#define SMU_BRIDGE_MSTRCFG__mbus2_mstr_pri__SHIFT__CI__VI 0x00000000 -#define SMU_CABLESAFE__CABLESAFE__SHIFT__CI__VI 0x00000000 -#define SMU_DFT_MISC__PCIE_DTM_XFER_PHY__SHIFT__CI__VI 0x00000001 -#define SMU_DFT_MISC__PCIE_DTM_XFER_WRP__SHIFT__CI__VI 0x00000000 -#define SMU_DMA_ACTIVE_SAMPLE__ENABLE__SHIFT__CI__VI 0x00000000 -#define SMU_DMA_ACTIVE_SAMPLE__PERIOD__SHIFT__CI__VI 0x00000010 -#define SMU_DMA_ACTIVE_SAMPLE__TRAN_CNT__SHIFT__CI__VI 0x00000008 -#define SMU_EFUSE_0__EFUSE_DATA__SHIFT__CI__VI 0x00000000 -#define SMU_FIRMWARE_AUTH__SMU_AUTH_IN_PROG__SHIFT__CI__VI 0x00000000 -#define SMU_FIRMWARE_AUTH__SMU_AUTH_counter__SHIFT__CI__VI 0x00000008 -#define SMU_FIRMWARE_AUTH__SMU_KEY_RD_DONE__SHIFT__CI__VI 0x00000001 -#define SMU_FIRMWARE_AUTH__SMU_KEY_SEL__SHIFT__CI__VI 0x00000011 -#define SMU_FIRMWARE_AUTH__SMU_PROTECTED_MODE__SHIFT__CI__VI 0x00000010 -#define SMU_FIRMWARE_AUTH__SMU_SRAM_RD_BLOCK_EN__SHIFT__CI__VI 0x00000003 -#define SMU_FIRMWARE_AUTH__SMU_SRAM_WR_BLOCK_EN__SHIFT__CI__VI 0x00000004 -#define SMU_GPIOPAD_A__GPIO_A__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT__CI__VI 0x00000005 -#define SMU_GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT__CI__VI 0x0000001f -#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT__CI__VI 0x0000001f -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT__CI__VI 0x0000000a -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT__CI__VI 0x0000000b -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT__CI__VI 0x0000000c -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT__CI__VI 0x0000000d -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT__CI__VI 0x0000000e -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT__CI__VI 0x0000000f -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT__CI__VI 0x00000010 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT__CI__VI 0x00000011 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT__CI__VI 0x00000012 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT__CI__VI 0x00000013 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT__CI__VI 0x00000001 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT__CI__VI 0x00000014 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT__CI__VI 0x00000015 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT__CI__VI 0x00000016 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT__CI__VI 0x00000017 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT__CI__VI 0x00000018 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT__CI__VI 0x00000019 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT__CI__VI 0x0000001a -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT__CI__VI 0x0000001b -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT__CI__VI 0x0000001c -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT__CI__VI 0x00000002 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT__CI__VI 0x00000003 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT__CI__VI 0x00000004 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT__CI__VI 0x00000005 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT__CI__VI 0x00000006 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT__CI__VI 0x00000007 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT__CI__VI 0x00000008 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT__CI__VI 0x00000009 -#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT__CI__VI 0x0000001f -#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT__CI__VI 0x0000001f -#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT__CI__VI 0x0000001f -#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT__CI__VI 0x0000001f -#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT__CI__VI 0x0000000a -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT__CI__VI 0x0000000b -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT__CI__VI 0x0000000c -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT__CI__VI 0x0000000d -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT__CI__VI 0x0000000e -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT__CI__VI 0x0000000f -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT__CI__VI 0x00000010 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT__CI__VI 0x00000011 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT__CI__VI 0x00000012 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT__CI__VI 0x00000013 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT__CI__VI 0x00000001 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT__CI__VI 0x00000014 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT__CI__VI 0x00000015 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT__CI__VI 0x00000016 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT__CI__VI 0x00000017 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT__CI__VI 0x00000018 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT__CI__VI 0x00000019 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT__CI__VI 0x0000001a -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT__CI__VI 0x0000001b -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT__CI__VI 0x0000001c -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT__CI__VI 0x0000001d -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT__CI__VI 0x00000002 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT__CI__VI 0x0000001e -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT__CI__VI 0x00000003 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT__CI__VI 0x00000004 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT__CI__VI 0x00000005 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT__CI__VI 0x00000006 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT__CI__VI 0x00000007 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT__CI__VI 0x00000008 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT__CI__VI 0x00000009 -#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT__CI__VI 0x00000004 -#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT__CI__VI 0x00000000 -#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT__CI__VI 0x00000000 -#define SMU_IOC_CTRL__IOC_mst_busy__SHIFT__CI__VI 0x00000004 -#define SMU_IOC_CTRL__IOC_mst_debug_rst__SHIFT__CI__VI 0x00000006 -#define SMU_IOC_CTRL__IOC_mst_disabled__SHIFT__CI__VI 0x00000005 -#define SMU_IOC_CTRL__IOC_mst_force_active__SHIFT__CI__VI 0x00000002 -#define SMU_IOC_CTRL__IOC_mst_rdValid__SHIFT__CI__VI 0x00000003 -#define SMU_IOC_CTRL__IOC_mst_send__SHIFT__CI__VI 0x00000000 -#define SMU_IOC_CTRL__IOC_mst_stop__SHIFT__CI__VI 0x00000001 -#define SMU_IOC_CTRL__IOC_mst_stop_ack__SHIFT__CI__VI 0x00000007 -#define SMU_IOC_MSTRCFG__mbus2_mstr_cg_override__SHIFT__CI__VI 0x0000001e -#define SMU_IOC_MSTRCFG__mbus2_mstr_disable__SHIFT__CI__VI 0x0000001f -#define SMU_IOC_MSTRCFG__mbus2_mstr_pri__SHIFT__CI__VI 0x00000000 -#define SMU_IOC_PHASE1__BiuCqfC_AltReqAddrLo__SHIFT__CI__VI 0x00000003 -#define SMU_IOC_PHASE1__BiuCqfC_AltReqRdCmd__SHIFT__CI__VI 0x00000002 -#define SMU_IOC_PHASE1__BiuCqfC_AwqReqCommit__SHIFT__CI__VI 0x00000001 -#define SMU_IOC_PHASE2__BiuCqfC_AltReqAddrHi__SHIFT__CI__VI 0x00000000 -#define SMU_IOC_PHASE2__BiuCqfC_AltReqMask__SHIFT__CI__VI 0x00000008 -#define SMU_IOC_PHASE3__BiuDbfC_C2aDataOut__SHIFT__CI__VI 0x00000000 -#define SMU_IOC_RDDATA__IOC_mst_rdData__SHIFT__CI__VI 0x00000000 -#define SMU_KEY_READ_STATUS__HDCP_KEY_RD_STATUS__SHIFT__CI__VI 0x00000000 -#define SMU_KEY_READ_STATUS__SAMU_KEY_RD_STATUS__SHIFT__CI__VI 0x00000008 -#define SMU_LCLK_CNTL__LCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define SMU_LCLK_STATUS__LCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT__CI__VI 0x00000000 -#define SMU_MISC_STATUS__SOC_DEBUG_ENABLE__SHIFT__CI__VI 0x00000001 -#define SMU_PM_MISC__AllCpusInCC6IntCtrl__SHIFT__CI__VI 0x00000010 -#define SMU_PM_MISC__MemPsIntCtrl__SHIFT__CI__VI 0x0000000e -#define SMU_PM_MISC__PM_AllCpusInCC6__SHIFT__CI__VI 0x00000000 -#define SMU_PM_MISC__PM_CommitSelfRefr__SHIFT__CI__VI 0x00000002 -#define SMU_PM_MISC__PM_HtcActive__SHIFT__CI__VI 0x0000000c -#define SMU_PM_MISC__PM_MemPs__SHIFT__CI__VI 0x0000000d -#define SMU_PM_MISC__PM_NbPs__SHIFT__CI__VI 0x00000001 -#define SMU_PM_MISC__PM_PreSelfRefresh__SHIFT__CI__VI 0x0000000a -#define SMU_PM_MISC__PM_ReqNbPstate__SHIFT__CI__VI 0x0000000b -#define SMU_PM_MISC__SPARE__SHIFT__CI__VI 0x00000012 -#define SMU_PM_SIGNALS_OVERRIDE__PM_AllCpusInCC6_ovrd__SHIFT__CI__VI 0x00000000 -#define SMU_PM_SIGNALS_OVERRIDE__RESERVED__SHIFT__CI__VI 0x00000001 -#define SMU_PSTATE_CONTROL__RESERVED__SHIFT__CI__VI 0x00000004 -#define SMU_PSTATE_CONTROL__Smu_Pstate_Limit_En__SHIFT__CI__VI 0x00000000 -#define SMU_PSTATE_CONTROL__Smu_Pstate_Limit__SHIFT__CI__VI 0x00000001 -#define SMU_RST_CTRL__DIST_BIF_STRAP_ON_DRV_RST__SHIFT__CI__VI 0x0000001e -#define SMU_RST_CTRL__DIST_BIF_STRAP_ON_LINK_RST__SHIFT__CI__VI 0x0000001f -#define SMU_RST_CTRL__FusesValPwrOk_STATUS__SHIFT__CI__VI 0x00000010 -#define SMU_RST_CTRL__GCK_early_resetb__SHIFT__CI__VI 0x00000008 -#define SMU_RST_CTRL__IRESET_STATUS__SHIFT__CI__VI 0x00000011 -#define SMU_RST_CTRL__SMU_RESET_STATUS__SHIFT__CI__VI 0x00000012 -#define SMU_RST_CTRL__SMU_RST_SEL__SHIFT__CI__VI 0x00000000 -#define SMU_RST_OVERRIDE__FusesValPwrOk_OVERRIDE__SHIFT__CI__VI 0x00000002 -#define SMU_RST_OVERRIDE__IRESET_OVERRIDE__SHIFT__CI__VI 0x00000004 -#define SMU_RST_OVERRIDE__SMU_RST_OVERRIDE__SHIFT__CI__VI 0x00000000 -#define SMU_SCLK_CNTL__SCLK_DIVIDER__SHIFT__CI__VI 0x00000000 -#define SMU_SCLK_STATUS__SCLK_STATUS__SHIFT__CI__VI 0x00000000 -#define SMU_SCRATCH0__SCRATCH_VALUE__SHIFT__CI__VI 0x00000000 -#define SMU_SCRATCH_A__SMU_SCRATCH_A__SHIFT__CI__VI 0x00000000 -#define SMU_SCRATCH_B__SMU_SCRATCH_B__SHIFT__CI__VI 0x00000000 -#define SMU_SCRATCH_C__SMU_SCRATCH_C__SHIFT__CI__VI 0x00000000 -#define SMU_SECURE_KEY_0__SMU_SECURE_KEY_0__SHIFT__CI__VI 0x00000000 -#define SMU_SECURE_KEY_1__SMU_SECURE_KEY_1__SHIFT__CI__VI 0x00000000 -#define SMU_SECURE_KEY_2__SMU_SECURE_KEY_2__SHIFT__CI__VI 0x00000000 -#define SMU_SECURE_KEY_3__SMU_SECURE_KEY_3__SHIFT__CI__VI 0x00000000 -#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SMU_SRAM_BLOCK_READ_HIGH_ADDR__sram_high_read_addr__SHIFT__CI__VI 0x00000000 -#define SMU_SRAM_BLOCK_READ_LOW_ADDR__sram_low_read_addr__SHIFT__CI__VI 0x00000000 -#define SMU_SRAM_BLOCK_WRITE_HIGH_ADDR__sram_high_write_addr__SHIFT__CI__VI 0x00000000 -#define SMU_SRAM_BLOCK_WRITE_LOW_ADDR__sram_low_write_addr__SHIFT__CI__VI 0x00000000 -#define SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT__SI 0x00000000 -#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x00000000 -#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x00000010 -#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x00000000 -#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT__CI__VI 0x00000010 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT__CI__VI 0x00000000 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT__CI__VI 0x00000003 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT__CI__VI 0x00000006 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT__CI__VI 0x00000009 -#define SPI_ARB_PRIORITY__RING_ORDER_TS0__SHIFT__SI 0x00000000 -#define SPI_ARB_PRIORITY__RING_ORDER_TS1__SHIFT__SI 0x00000003 -#define SPI_ARB_PRIORITY__RING_ORDER_TS2__SHIFT__SI 0x00000006 -#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT__CI__VI 0x0000000c -#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT__CI__VI 0x0000000e -#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT__CI__VI 0x00000010 -#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT__CI__VI 0x00000012 -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x00000018 -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x00000008 -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0x0000000c -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x00000000 -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x00000004 -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x00000010 -#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x00000014 -#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT__CI__VI 0x00000000 -#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT__CI__VI 0x00000008 -#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT__CI__VI 0x00000010 -#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT__CI__VI 0x00000018 -#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT__CI__VI 0x00000000 -#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT__CI__VI 0x00000008 -#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT__CI__VI 0x00000010 -#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT__CI__VI 0x00000018 -#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT__CI__VI 0x00000006 -#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT__CI__VI 0x00000003 -#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT__CI__VI 0x00000002 -#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT__CI__VI 0x00000004 -#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT__CI__VI 0x00000005 -#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT__CI__VI 0x00000000 -#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT__CI__VI 0x00000001 -#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT__CI__VI 0x00000003 -#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT__CI__VI 0x00000002 -#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT__CI__VI 0x00000004 -#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT__CI__VI 0x00000005 -#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT__CI__VI 0x00000000 -#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT__CI__VI 0x00000001 -#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT__CI__VI 0x00000000 -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x00000008 -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x00000004 -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT__CI__VI 0x0000000a -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT__CI__VI 0x00000009 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x00000006 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x00000010 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x00000007 -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x00000000 -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x00000019 -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x00000018 -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x00000015 -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x00000000 -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x0000001a -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT__CI__VI 0x0000001b -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT__CI__VI 0x00000000 -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT__CI__VI 0x00000000 -#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT__CI__VI 0x00000008 -#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT__SI 0x00000007 -#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT__CI__VI 0x00000009 -#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT__SI 0x00000008 -#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT__CI__VI 0x0000000a -#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT__SI 0x00000009 -#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT__CI__VI 0x0000000b -#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT__CI__VI 0x0000000c -#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT__CI__VI 0x0000000d -#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT__CI__VI 0x0000000e -#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT__CI__VI 0x0000000f -#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT__CI__VI 0x00000007 -#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x00000002 -#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT__CI__VI 0x00000015 -#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT__SI 0x0000000f -#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT__CI__VI 0x00000016 -#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT__SI 0x00000010 -#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x00000003 -#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x00000001 -#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT__CI__VI 0x00000010 -#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT__SI 0x0000000a -#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT__CI__VI 0x00000011 -#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT__SI 0x0000000b -#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x00000000 -#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT__CI__VI 0x00000014 -#define SPI_DEBUG_BUSY__PC_POSB_BUSY__SHIFT__SI 0x0000000e -#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x00000005 -#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x00000006 -#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT__CI__VI 0x00000012 -#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT__SI 0x0000000c -#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT__CI__VI 0x00000013 -#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT__SI 0x0000000d -#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT__CI__VI 0x00000017 -#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT__SI 0x00000011 -#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x00000004 -#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x00000000 -#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT__CI__VI 0x00000004 -#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT__SI 0x00000005 -#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT__CI__VI 0x00000019 -#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x0000001f -#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x00000010 -#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0x0000000a -#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x00000001 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x00000011 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x00000012 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x00000013 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x00000014 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x00000015 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x00000016 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x00000017 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x00000018 -#define SPI_DEBUG_READ__DATA__SHIFT 0x00000000 -#define SPI_DYN_GPR_LOCK_EN__ES_LOW_THRESHOLD__SHIFT__SI 0x00000008 -#define SPI_DYN_GPR_LOCK_EN__GS_LOW_THRESHOLD__SHIFT__SI 0x00000004 -#define SPI_DYN_GPR_LOCK_EN__HS_LOW_THRESHOLD__SHIFT__SI 0x0000000c -#define SPI_DYN_GPR_LOCK_EN__LS_LOW_THRESHOLD__SHIFT__SI 0x00000010 -#define SPI_DYN_GPR_LOCK_EN__VS_LOW_THRESHOLD__SHIFT__SI 0x00000000 -#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT__CI__VI 0x00000007 -#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT__CI__VI 0x00000008 -#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT__CI__VI 0x00000002 -#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT__CI__VI 0x00000009 -#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT__CI__VI 0x00000004 -#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT__CI__VI 0x0000000f -#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT__CI__VI 0x00000010 -#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT__CI__VI 0x00000000 -#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT__CI__VI 0x00000009 -#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT__CI__VI 0x00000000 -#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x00000008 -#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x00000000 -#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x00000010 -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x00000000 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x00000001 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0x0000000b -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x00000002 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x00000005 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x00000008 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0x0000000e -#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x00000000 -#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x00000000 -#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x00000000 -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT__CI__VI 0x00000006 -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT__CI__VI 0x00000000 -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT__CI__VI 0x00000006 -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT__CI__VI 0x00000000 -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x00000004 -#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x00000000 -#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0x0000000c -#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x00000008 -#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x00000014 -#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x00000010 -#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x0000001c -#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x00000018 -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x00000000 -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0x0000000d -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0x0000000c -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x00000005 -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x00000006 -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x00000001 -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x00000002 -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x00000000 -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0x0000000f -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0x0000000b -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x00000008 -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x00000009 -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0x0000000a -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT__CI__VI 0x00000012 -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0x0000000d -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0x0000000c -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x00000005 -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x00000006 -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x00000001 -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x00000002 -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x00000000 -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0x0000000f -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0x0000000b -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x00000008 -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x00000009 -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0x0000000a -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0x0000000e -#define SPI_PS_IN_CONTROL__FOG_ADDR__SHIFT__SI 0x00000007 -#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000 -#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x00000006 -#define SPI_PS_IN_CONTROL__PASS_FOG_THROUGH_PS__SHIFT__SI 0x0000000f -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT__CI__VI 0x00000002 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT__CI__VI 0x00000001 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT__CI__VI 0x00000004 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT__CI__VI 0x00000003 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT__CI__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT__CI__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT__CI__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT__CI__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_AB_0__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_0__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_0__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_0__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_0__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_0__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_0__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_0__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_0__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_0__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_0__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_0__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_CU_AB_1__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_1__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_1__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_1__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_1__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_1__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_1__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_1__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_1__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_1__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_1__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_1__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_CU_AB_2__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_2__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_2__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_2__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_2__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_2__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_2__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_2__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_2__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_2__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_2__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_2__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_CU_AB_3__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_3__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_3__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_3__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_3__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_3__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_3__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_3__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_3__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_3__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_3__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_3__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_CU_AB_4__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_4__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_4__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_4__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_4__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_4__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_4__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_4__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_4__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_4__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_4__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_4__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_CU_AB_5__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_5__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_5__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_5__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_5__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_5__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_5__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_5__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_5__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_5__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_5__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_5__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_CU_AB_6__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_6__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_6__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_6__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_6__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_6__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_6__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_6__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_6__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_6__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_6__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_6__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_CU_AB_7__EN_A__SHIFT__SI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_AB_7__EN_B__SHIFT__SI 0x0000001f -#define SPI_RESOURCE_RESERVE_CU_AB_7__LDS_A__SHIFT__SI 0x0000000a -#define SPI_RESOURCE_RESERVE_CU_AB_7__LDS_B__SHIFT__SI 0x0000001a -#define SPI_RESOURCE_RESERVE_CU_AB_7__SGPR_A__SHIFT__SI 0x00000007 -#define SPI_RESOURCE_RESERVE_CU_AB_7__SGPR_B__SHIFT__SI 0x00000017 -#define SPI_RESOURCE_RESERVE_CU_AB_7__TYPE_A__SHIFT__SI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_AB_7__TYPE_B__SHIFT__SI 0x00000010 -#define SPI_RESOURCE_RESERVE_CU_AB_7__VGPR_A__SHIFT__SI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_AB_7__VGPR_B__SHIFT__SI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_AB_7__WAVES_A__SHIFT__SI 0x0000000d -#define SPI_RESOURCE_RESERVE_CU_AB_7__WAVES_B__SHIFT__SI 0x0000001d -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT__CI__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT__CI__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT__CI__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT__CI__VI 0x00000001 -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x00000000 -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x00000004 -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x00000008 -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0x0000000c -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x00000010 -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x00000014 -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x00000018 -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x0000001c -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT__CI__VI 0x0000001b -#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT__CI__VI 0x0000001e -#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x0000001a -#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT__CI__VI 0x00000019 -#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT__CI__VI 0x0000001c -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT__CI__VI 0x00000018 -#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT__CI__VI 0x0000001b -#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT__CI__VI 0x0000001a -#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT__CI__VI 0x0000001d -#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT__CI__VI 0x00000019 -#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT__CI__VI 0x0000001c -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT__CI__VI 0x0000001b -#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT__CI__VI 0x0000001e -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x0000001a -#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT__CI__VI 0x00000008 -#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT__CI__VI 0x00000014 -#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT__CI__VI 0x00000007 -#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT__CI__VI 0x00000006 -#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT__CI__VI 0x00000001 -#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT__CI__VI 0x00000008 -#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT__CI__VI 0x00000014 -#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT__CI__VI 0x00000007 -#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT__CI__VI 0x00000006 -#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT__CI__VI 0x00000001 -#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x00000008 -#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT__CI__VI 0x00000014 -#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x00000009 -#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x00000008 -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT__CI__VI 0x00000007 -#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT__CI__VI 0x00000006 -#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT__CI__VI 0x00000001 -#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT__CI__VI 0x00000007 -#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT__CI__VI 0x00000006 -#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT__CI__VI 0x00000001 -#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT__CI__VI 0x00000007 -#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT__CI__VI 0x00000006 -#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT__CI__VI 0x00000001 -#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x00000008 -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0x0000000d -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x00000008 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x00000009 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0x0000000b -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT__CI__VI 0x00000016 -#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT__CI__VI 0x00000016 -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT__CI__VI 0x00000006 -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT__CI__VI 0x00000016 -#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT__CI__VI 0x00000016 -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT__CI__VI 0x00000000 -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT__CI__VI 0x00000016 -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT__CI__VI 0x00000010 -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x00000000 -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x00000004 -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x00000008 -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0x0000000c -#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x00000000 -#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x00000000 -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x00000000 -#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x00000002 -#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x00000015 -#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x00000003 -#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x00000001 -#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x00000000 -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x00000009 -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x0000000a -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0x0000000b -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0x0000000c -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0x0000000d -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0x0000000e -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0x0000000f -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x00000010 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x00000005 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x00000006 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x00000007 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x00000008 -#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x00000004 -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x00000011 -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x00000012 -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x00000013 -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x00000014 -#define SPI_STATIC_THREAD_MGMT_1__PS_CU_EN__SHIFT__SI 0x00000000 -#define SPI_STATIC_THREAD_MGMT_1__VS_CU_EN__SHIFT__SI 0x00000010 -#define SPI_STATIC_THREAD_MGMT_2__ES_CU_EN__SHIFT__SI 0x00000010 -#define SPI_STATIC_THREAD_MGMT_2__GS_CU_EN__SHIFT__SI 0x00000000 -#define SPI_STATIC_THREAD_MGMT_3__LSHS_CU_EN__SHIFT__SI 0x00000000 -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x00000000 -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x00000010 -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x00000000 -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x00000010 -#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c -#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x00000000 -#define SPI_VS_OUT_CONFIG__VS_EXPORTS_FOG__SHIFT__SI 0x00000007 -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x00000001 -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x00000006 -#define SPI_VS_OUT_CONFIG__VS_OUT_FOG_VEC_ADDR__SHIFT__SI 0x00000008 -#define SPI_WAVE_MGMT_1__NUM_ES_WAVES__SHIFT__SI 0x00000012 -#define SPI_WAVE_MGMT_1__NUM_GS_WAVES__SHIFT__SI 0x0000000c -#define SPI_WAVE_MGMT_1__NUM_HS_WAVES__SHIFT__SI 0x00000018 -#define SPI_WAVE_MGMT_1__NUM_PS_WAVES__SHIFT__SI 0x00000000 -#define SPI_WAVE_MGMT_1__NUM_VS_WAVES__SHIFT__SI 0x00000006 -#define SPI_WAVE_MGMT_2__NUM_LS_WAVES__SHIFT__SI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_CNTL__EN__SHIFT__CI__VI 0x00000004 -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT__CI__VI 0x0000001f -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT__CI__VI 0x00000000 -#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0x0000000c -#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x00000004 -#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x00000003 -#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x00000001 -#define SPLL_CNTL_MODE__SPLL_REFCLK_SEL__SHIFT__SI 0x0000001a -#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x0000001c -#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x00000000 -#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0x0000000a -#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x00000002 -#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x0000001d -#define SPLL_TIME__SPLL_LOCK_TIME__SHIFT 0x00000000 -#define SPLL_TIME__SPLL_RESET_TIME__SHIFT 0x00000010 -#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT__CI__VI 0x00000001 -#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED__SHIFT__CI__VI 0x00000000 -#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT__CI__VI 0x00000002 -#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT__CI 0x00000001 -#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED__SHIFT__CI 0x00000000 -#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT__CI 0x00000002 -#define SPMI_CONFIG_0_0__SPMI_ENABLE__SHIFT__CI 0x00000000 -#define SPMI_CONFIG_0_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT__CI 0x00000016 -#define SPMI_CONFIG_0_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT__CI 0x00000011 -#define SPMI_CONFIG_0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT__CI 0x00000002 -#define SPMI_CONFIG_0_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT__CI 0x00000007 -#define SPMI_CONFIG_0_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT__CI 0x0000000c -#define SPMI_CONFIG_0_1__SPMI_CHAIN_SIZE__SHIFT__CI 0x00000005 -#define SPMI_CONFIG_0_1__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT__CI 0x00000000 -#define SPMI_CONFIG_1_0__SPMI_ENABLE__SHIFT__CI 0x00000000 -#define SPMI_CONFIG_1_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT__CI 0x00000016 -#define SPMI_CONFIG_1_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT__CI 0x00000011 -#define SPMI_CONFIG_1_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT__CI 0x00000002 -#define SPMI_CONFIG_1_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT__CI 0x00000007 -#define SPMI_CONFIG_1_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT__CI 0x0000000c -#define SPMI_CONFIG_1_1__SPMI_CHAIN_SIZE__SHIFT__CI 0x00000005 -#define SPMI_CONFIG_1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT__CI 0x00000000 -#define SPMI_FSM_BUSY_0__FSM_BUSY__SHIFT__CI__VI 0x00000000 -#define SPMI_FSM_BUSY_1__FSM_BUSY__SHIFT__CI 0x00000000 -#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER__SHIFT__CI__VI 0x00000000 -#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER__SHIFT__CI 0x00000000 -#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER__SHIFT__CI__VI 0x00000000 -#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER__SHIFT__CI 0x00000000 -#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER__SHIFT__CI__VI 0x00000000 -#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER__SHIFT__CI 0x00000000 -#define SPMI_IND_ADDR__SPMI_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SPMI_IND_DATA__SPMI_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT__CI__VI 0x00000000 -#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT__CI 0x00000000 -#define SPMI_PATH_0__PATH_ENABLE_ACK__SHIFT__CI__VI 0x00000001 -#define SPMI_PATH_0__PATH_ENABLE_REQ__SHIFT__CI__VI 0x00000000 -#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear__SHIFT__CI__VI 0x00000004 -#define SPMI_PATH_1__PATH_ENABLE_ACK__SHIFT__CI 0x00000001 -#define SPMI_PATH_1__PATH_ENABLE_REQ__SHIFT__CI 0x00000000 -#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear__SHIFT__CI 0x00000004 -#define SPMI_RESET__ASYNC_RESET_0__SHIFT__CI__VI 0x00000000 -#define SPMI_RESET__ASYNC_RESET_1__SHIFT__CI 0x00000001 -#define SPMI_RESET__SYNC_RESET__SHIFT__CI 0x00000002 -#define SPMI_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI__VI 0x00000000 -#define SPMI_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI__VI 0x00000000 -#define SPMI_SRAM_ADDRESS__SRAM_ADDRESS__SHIFT__CI__VI 0x00000000 -#define SPMI_SRAM_DATA__SRAM_DATA__SHIFT__CI__VI 0x00000000 -#define SPMI_TIMER__PERIOD__SHIFT__CI 0x00000000 -#define SQC_CACHES__DATA_INVALIDATE__SHIFT__SI__CI 0x00000001 -#define SQC_CACHES__INST_INVALIDATE__SHIFT__SI__CI 0x00000000 -#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT__CI 0x00000002 -#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x00000002 -#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x00000007 -#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x00000008 -#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x00000006 -#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x00000009 -#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0x0000000a -#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x00000000 -#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x00000004 -#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT__CI__VI 0x0000000b -#define SQC_POLICY__DATA_L1_POLICY_0__SHIFT__CI 0x00000000 -#define SQC_POLICY__DATA_L1_POLICY_1__SHIFT__CI 0x00000001 -#define SQC_POLICY__DATA_L1_POLICY_2__SHIFT__CI 0x00000002 -#define SQC_POLICY__DATA_L1_POLICY_3__SHIFT__CI 0x00000003 -#define SQC_POLICY__DATA_L1_POLICY_4__SHIFT__CI 0x00000004 -#define SQC_POLICY__DATA_L1_POLICY_5__SHIFT__CI 0x00000005 -#define SQC_POLICY__DATA_L1_POLICY_6__SHIFT__CI 0x00000006 -#define SQC_POLICY__DATA_L1_POLICY_7__SHIFT__CI 0x00000007 -#define SQC_POLICY__DATA_L2_POLICY_0__SHIFT__CI 0x00000008 -#define SQC_POLICY__DATA_L2_POLICY_1__SHIFT__CI 0x0000000a -#define SQC_POLICY__DATA_L2_POLICY_2__SHIFT__CI 0x0000000c -#define SQC_POLICY__DATA_L2_POLICY_3__SHIFT__CI 0x0000000e -#define SQC_POLICY__DATA_L2_POLICY_4__SHIFT__CI 0x00000010 -#define SQC_POLICY__DATA_L2_POLICY_5__SHIFT__CI 0x00000012 -#define SQC_POLICY__DATA_L2_POLICY_6__SHIFT__CI 0x00000014 -#define SQC_POLICY__DATA_L2_POLICY_7__SHIFT__CI 0x00000016 -#define SQC_POLICY__INST_L2_POLICY__SHIFT__CI 0x00000018 -#define SQC_SECDED_CNT__DATA_DED__SHIFT__SI__CI 0x00000018 -#define SQC_SECDED_CNT__DATA_SEC__SHIFT__SI__CI 0x00000010 -#define SQC_SECDED_CNT__INST_DED__SHIFT__SI__CI 0x00000008 -#define SQC_SECDED_CNT__INST_SEC__SHIFT__SI__CI 0x00000000 -#define SQC_VOLATILE__DATA_L1__SHIFT__CI 0x00000000 -#define SQC_VOLATILE__DATA_L2__SHIFT__CI 0x00000004 -#define SQC_VOLATILE__INST_L2__SHIFT__CI 0x00000008 -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x0000001e -#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x00000010 -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x0000001f -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x00000017 -#define SQ_BUF_RSRC_WORD3__ATC__SHIFT__CI__VI 0x00000018 -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0x0000000f -#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 -#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 -#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x00000013 -#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x00000019 -#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x0000001a -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x00000015 -#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT__CI__VI 0x0000001b -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0x0000000c -#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x0000001e -#define SQ_CAC_MASK__GPR__SHIFT__SI 0x00000002 -#define SQ_CAC_MASK__VALU_MUL__SHIFT__SI 0x00000001 -#define SQ_CAC_MASK__VALU__SHIFT__SI 0x00000000 -#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT__CI__VI 0x00000000 -#define SQ_CMD__CHECK_VMID__SHIFT__CI__VI 0x00000007 -#define SQ_CMD__CMD__SHIFT__CI__VI 0x00000000 -#define SQ_CMD__MODE__SHIFT__CI__VI 0x00000004 -#define SQ_CMD__QUEUE_ID__SHIFT__CI__VI 0x00000018 -#define SQ_CMD__SIMD_ID__SHIFT__CI__VI 0x00000014 -#define SQ_CMD__TRAP_ID__SHIFT__CI 0x00000008 -#define SQ_CMD__VM_ID__SHIFT__CI__VI 0x0000001c -#define SQ_CMD__WAVE_ID__SHIFT__CI__VI 0x00000010 -#define SQ_CONFIG__DEBUG_EN__SHIFT 0x00000008 -#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT__SI__CI 0x0000000a -#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT__SI__CI 0x00000009 -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT__CI__VI 0x0000000f -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT__CI__VI 0x0000000d -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT__CI__VI 0x0000000e -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT__CI__VI 0x0000000c -#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT__CI 0x0000000b -#define SQ_CONFIG__UNUSED__SHIFT 0x00000000 -#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x00000000 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT__CI__VI 0x00000000 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT__CI__VI 0x00000008 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT__CI__VI 0x00000018 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT__CI__VI 0x00000010 -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT__CI__VI 0x00000000 -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT__CI__VI 0x00000004 -#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 -#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT__CI__VI 0x00000001 -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 -#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 -#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004 -#define SQ_DED_CNT__LDS_DED__SHIFT__SI__CI 0x00000000 -#define SQ_DED_CNT__SGPR_DED__SHIFT__SI__CI 0x00000008 -#define SQ_DED_CNT__VGPR_DED__SHIFT__SI__CI 0x00000010 -#define SQ_DED_INFO__RING_ID__SHIFT__SI 0x0000000d -#define SQ_DED_INFO__SIMD_ID__SHIFT__SI__CI 0x00000004 -#define SQ_DED_INFO__SOURCE__SHIFT__SI__CI 0x00000006 -#define SQ_DED_INFO__VM_ID__SHIFT__SI__CI 0x00000009 -#define SQ_DED_INFO__WAVE_ID__SHIFT__SI__CI 0x00000000 -#define SQ_DS_0__ENCODING__SHIFT 0x0000001a -#define SQ_DS_0__OFFSET0__SHIFT 0x00000000 -#define SQ_DS_0__OFFSET1__SHIFT 0x00000008 -#define SQ_DS_1__ADDR__SHIFT 0x00000000 -#define SQ_DS_1__DATA0__SHIFT 0x00000008 -#define SQ_DS_1__DATA1__SHIFT 0x00000010 -#define SQ_DS_1__VDST__SHIFT 0x00000018 -#define SQ_EXP_0__COMPR__SHIFT 0x0000000a -#define SQ_EXP_0__DONE__SHIFT 0x0000000b -#define SQ_EXP_0__ENCODING__SHIFT 0x0000001a -#define SQ_EXP_0__EN__SHIFT 0x00000000 -#define SQ_EXP_0__TGT__SHIFT 0x00000004 -#define SQ_EXP_0__VM__SHIFT 0x0000000c -#define SQ_EXP_1__VSRC0__SHIFT 0x00000000 -#define SQ_EXP_1__VSRC1__SHIFT 0x00000008 -#define SQ_EXP_1__VSRC2__SHIFT 0x00000010 -#define SQ_EXP_1__VSRC3__SHIFT 0x00000018 -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x00000010 -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x00000000 -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x00000008 -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x00000012 -#define SQ_FLAT_0__ENCODING__SHIFT__CI__VI 0x0000001a -#define SQ_FLAT_0__GLC__SHIFT__CI__VI 0x00000010 -#define SQ_FLAT_0__OP__SHIFT__CI__VI 0x00000012 -#define SQ_FLAT_0__SLC__SHIFT__CI__VI 0x00000011 -#define SQ_FLAT_1__ADDR__SHIFT__CI__VI 0x00000000 -#define SQ_FLAT_1__DATA__SHIFT__CI__VI 0x00000008 -#define SQ_FLAT_1__TFE__SHIFT__CI__VI 0x00000017 -#define SQ_FLAT_1__VDST__SHIFT__CI__VI 0x00000018 -#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT__CI__VI 0x00000000 -#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT__CI__VI 0x00000000 -#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT__CI__VI 0x00000004 -#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT__CI__VI 0x00000000 -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x00000014 -#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x00000008 -#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT__CI__VI 0x0000001e -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x0000001a -#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0x0000000e -#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x0000001f -#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x0000001c -#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD3__ATC__SHIFT__CI__VI 0x0000001b -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0x0000000c -#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 -#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x00000010 -#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT__CI__VI 0x0000001a -#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x00000019 -#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x00000014 -#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x0000001c -#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0x0000000d -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0x0000000d -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT__CI__VI 0x0000000c -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT__CI__VI 0x00000014 -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT__CI 0x00000015 -#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT__SI__CI 0x00000000 -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x00000015 -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x00000010 -#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x00000003 -#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x00000006 -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0x0000000c -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x0000001c -#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x0000001d -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x00000014 -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0x0000000f -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x00000009 -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x00000013 -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x0000001b -#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0x0000000c -#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x00000018 -#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x0000001c -#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x0000001d -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x0000001e -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0x0000000e -#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x0000001a -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x0000001c -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x00000014 -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x00000016 -#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x00000018 -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x0000001e -#define SQ_IND_CMD__CMD__SHIFT__SI 0x00000000 -#define SQ_IND_CMD__MODE__SHIFT__SI 0x00000004 -#define SQ_IND_CMD__TRAP_ID__SHIFT__SI 0x00000008 -#define SQ_IND_CMD__VM_ID__SHIFT__SI 0x0000001c -#define SQ_IND_DATA__DATA__SHIFT 0x00000000 -#define SQ_IND_INDEX__AUTO_INCR__SHIFT__CI__VI 0x0000000c -#define SQ_IND_INDEX__FORCE_READ__SHIFT__CI__VI 0x0000000d -#define SQ_IND_INDEX__INDEX__SHIFT 0x00000010 -#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0x0000000e -#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004 -#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x00000006 -#define SQ_IND_INDEX__UNINDEXED__SHIFT 0x0000000f -#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x00000000 -#define SQ_INST__ENCODING__SHIFT 0x00000000 -#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT__CI__VI 0x00000000 -#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT__CI__VI 0x00000000 -#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT__CI__VI 0x00000004 -#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x0000001a -#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT__CI__VI 0x00000005 -#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT__CI__VI 0x00000006 -#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT__CI__VI 0x00000007 -#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT__CI__VI 0x00000003 -#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT__CI__VI 0x00000018 -#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT__SI 0x00000019 -#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT__CI__VI 0x00000002 -#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT__CI__VI 0x00000001 -#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x0000001a -#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT__CI__VI 0x00000018 -#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT__SI 0x00000019 -#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x00000014 -#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x0000001a -#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT__CI__VI 0x00000009 -#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT__CI__VI 0x00000018 -#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT__SI 0x00000019 -#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT__CI__VI 0x00000008 -#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT__SI 0x00000018 -#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x00000012 -#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0x0000000a -#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x0000000e -#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x00000002 -#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x00000001 -#define SQ_LB_CTR_CTRL__START__SHIFT 0x00000000 -#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x00000000 -#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x00000000 -#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x00000000 -#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x00000000 -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT__CI__VI 0x00000000 -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT__CI__VI 0x00000010 -#define SQ_MIMG_0__DA__SHIFT 0x0000000e -#define SQ_MIMG_0__DMASK__SHIFT 0x00000008 -#define SQ_MIMG_0__ENCODING__SHIFT 0x0000001a -#define SQ_MIMG_0__GLC__SHIFT 0x0000000d -#define SQ_MIMG_0__LWE__SHIFT 0x00000011 -#define SQ_MIMG_0__OP__SHIFT 0x00000012 -#define SQ_MIMG_0__R128__SHIFT 0x0000000f -#define SQ_MIMG_0__SLC__SHIFT 0x00000019 -#define SQ_MIMG_0__TFE__SHIFT 0x00000010 -#define SQ_MIMG_0__UNORM__SHIFT 0x0000000c -#define SQ_MIMG_1__SRSRC__SHIFT 0x00000010 -#define SQ_MIMG_1__SSAMP__SHIFT 0x00000015 -#define SQ_MIMG_1__VADDR__SHIFT 0x00000000 -#define SQ_MIMG_1__VDATA__SHIFT 0x00000008 -#define SQ_MTBUF_0__ADDR64__SHIFT__SI__CI 0x0000000f -#define SQ_MTBUF_0__DFMT__SHIFT 0x00000013 -#define SQ_MTBUF_0__ENCODING__SHIFT 0x0000001a -#define SQ_MTBUF_0__GLC__SHIFT 0x0000000e -#define SQ_MTBUF_0__IDXEN__SHIFT 0x0000000d -#define SQ_MTBUF_0__NFMT__SHIFT 0x00000017 -#define SQ_MTBUF_0__OFFEN__SHIFT 0x0000000c -#define SQ_MTBUF_0__OFFSET__SHIFT 0x00000000 -#define SQ_MTBUF_1__SLC__SHIFT 0x00000016 -#define SQ_MTBUF_1__SOFFSET__SHIFT 0x00000018 -#define SQ_MTBUF_1__SRSRC__SHIFT 0x00000010 -#define SQ_MTBUF_1__TFE__SHIFT 0x00000017 -#define SQ_MTBUF_1__VADDR__SHIFT 0x00000000 -#define SQ_MTBUF_1__VDATA__SHIFT 0x00000008 -#define SQ_MUBUF_0__ADDR64__SHIFT__SI__CI 0x0000000f -#define SQ_MUBUF_0__ENCODING__SHIFT 0x0000001a -#define SQ_MUBUF_0__GLC__SHIFT 0x0000000e -#define SQ_MUBUF_0__IDXEN__SHIFT 0x0000000d -#define SQ_MUBUF_0__LDS__SHIFT 0x00000010 -#define SQ_MUBUF_0__OFFEN__SHIFT 0x0000000c -#define SQ_MUBUF_0__OFFSET__SHIFT 0x00000000 -#define SQ_MUBUF_0__OP__SHIFT 0x00000012 -#define SQ_MUBUF_1__SLC__SHIFT__SI__CI 0x00000016 -#define SQ_MUBUF_1__SOFFSET__SHIFT 0x00000018 -#define SQ_MUBUF_1__SRSRC__SHIFT 0x00000010 -#define SQ_MUBUF_1__TFE__SHIFT 0x00000017 -#define SQ_MUBUF_1__VADDR__SHIFT 0x00000000 -#define SQ_MUBUF_1__VDATA__SHIFT 0x00000008 -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x0000001c -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT__CI__VI 0x00000014 -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT__CI__VI 0x0000000c -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT__CI__VI 0x00000000 -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x00000008 -#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x00000006 -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0x0000000d -#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x00000003 -#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x00000002 -#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x00000004 -#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x00000005 -#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x00000000 -#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x00000001 -#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT__CI__VI 0x00000000 -#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT__CI__VI 0x00000010 -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x0000001f -#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x00000010 -#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x00000000 -#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x0000001e -#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x00000000 -#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0x0000000a -#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x00000007 -#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x00000008 -#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT__CI__VI 0x0000001f -#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT__CI__VI 0x0000001e -#define SQ_REG_CREDITS__REG_BUSY__SHIFT__CI__VI 0x0000001c -#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x00000000 -#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT__CI__VI 0x0000001d -#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT__CI__VI 0x00000000 -#define SQ_SEC_CNT__LDS_SEC__SHIFT__SI__CI 0x00000000 -#define SQ_SEC_CNT__SGPR_SEC__SHIFT__SI__CI 0x00000008 -#define SQ_SEC_CNT__VGPR_SEC__SHIFT__SI__CI 0x00000010 -#define SQ_SMRD__ENCODING__SHIFT__SI__CI 0x0000001b -#define SQ_SMRD__IMM__SHIFT__SI__CI 0x00000008 -#define SQ_SMRD__OFFSET__SHIFT__SI__CI 0x00000000 -#define SQ_SMRD__OP__SHIFT__SI__CI 0x00000016 -#define SQ_SMRD__SBASE__SHIFT__SI__CI 0x00000009 -#define SQ_SMRD__SDST__SHIFT__SI__CI 0x0000000f -#define SQ_SOP1__ENCODING__SHIFT 0x00000017 -#define SQ_SOP1__OP__SHIFT 0x00000008 -#define SQ_SOP1__SDST__SHIFT 0x00000010 -#define SQ_SOP1__SSRC0__SHIFT 0x00000000 -#define SQ_SOP2__ENCODING__SHIFT 0x0000001e -#define SQ_SOP2__OP__SHIFT 0x00000017 -#define SQ_SOP2__SDST__SHIFT 0x00000010 -#define SQ_SOP2__SSRC0__SHIFT 0x00000000 -#define SQ_SOP2__SSRC1__SHIFT 0x00000008 -#define SQ_SOPC__ENCODING__SHIFT 0x00000017 -#define SQ_SOPC__OP__SHIFT 0x00000010 -#define SQ_SOPC__SSRC0__SHIFT 0x00000000 -#define SQ_SOPC__SSRC1__SHIFT 0x00000008 -#define SQ_SOPK__ENCODING__SHIFT 0x0000001c -#define SQ_SOPK__OP__SHIFT 0x00000017 -#define SQ_SOPK__SDST__SHIFT 0x00000010 -#define SQ_SOPK__SIMM16__SHIFT 0x00000000 -#define SQ_SOPP__ENCODING__SHIFT 0x00000017 -#define SQ_SOPP__OP__SHIFT 0x00000010 -#define SQ_SOPP__SIMM16__SHIFT 0x00000000 -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT__CI 0x00000004 -#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x0000001f -#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT__SI__CI 0x00000010 -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT__CI__VI 0x00000007 -#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x00000008 -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT__CI__VI 0x0000000e -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT__CI__VI 0x0000000f -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x00000019 -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x00000017 -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x0000001e -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x0000001b -#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x00000012 -#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0x0000000f -#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x00000003 -#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x00000015 -#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x0000001a -#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x0000001d -#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x0000001f -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x0000001e -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x0000001f -#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x0000001d -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT__CI__VI 0x00000018 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT__SI__CI 0x0000000b -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x00000008 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x00000012 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x00000014 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x00000016 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x00000018 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x0000001a -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT__CI__VI 0x0000000d -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT__SI 0x00000006 -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT__CI__VI 0x0000000c -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT__SI 0x00000005 -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x00000019 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x00000013 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__DISPATCHER__SHIFT__SI 0x00000005 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT__CI__VI 0x00000007 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT__CI__VI 0x00000005 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT__CI__VI 0x00000009 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0x0000000f -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT__CI__VI 0x00000010 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT__CI__VI 0x00000007 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT__CI__VI 0x00000005 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT__CI__VI 0x00000009 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT__CI__VI 0x00000004 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIME__PACKET_LOST__SHIFT__SI 0x0000000f -#define SQ_THREAD_TRACE_WORD_TIME__TIME_DELTA__SHIFT__SI 0x00000004 -#define SQ_THREAD_TRACE_WORD_TIME__TIME_RESET__SHIFT__SI 0x0000000e -#define SQ_THREAD_TRACE_WORD_TIME__TOKEN_TYPE__SHIFT__SI 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x00000016 -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x0000001d -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x00000015 -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x0000001e -#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x00000000 -#define SQ_TIME_HI__TIME__SHIFT 0x00000000 -#define SQ_TIME_LO__TIME__SHIFT 0x00000000 -#define SQ_VINTRP__ATTRCHAN__SHIFT 0x00000008 -#define SQ_VINTRP__ATTR__SHIFT 0x0000000a -#define SQ_VINTRP__ENCODING__SHIFT 0x0000001a -#define SQ_VINTRP__OP__SHIFT 0x00000010 -#define SQ_VINTRP__VDST__SHIFT 0x00000012 -#define SQ_VINTRP__VSRC__SHIFT 0x00000000 -#define SQ_VOP1__ENCODING__SHIFT 0x00000019 -#define SQ_VOP1__OP__SHIFT 0x00000009 -#define SQ_VOP1__SRC0__SHIFT 0x00000000 -#define SQ_VOP1__VDST__SHIFT 0x00000011 -#define SQ_VOP2__ENCODING__SHIFT 0x0000001f -#define SQ_VOP2__OP__SHIFT 0x00000019 -#define SQ_VOP2__SRC0__SHIFT 0x00000000 -#define SQ_VOP2__VDST__SHIFT 0x00000011 -#define SQ_VOP2__VSRC1__SHIFT 0x00000009 -#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x0000001a -#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x00000008 -#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x00000000 -#define SQ_VOP3_0__ABS__SHIFT 0x00000008 -#define SQ_VOP3_0__ENCODING__SHIFT 0x0000001a -#define SQ_VOP3_0__VDST__SHIFT 0x00000000 -#define SQ_VOP3_1__NEG__SHIFT 0x0000001d -#define SQ_VOP3_1__OMOD__SHIFT 0x0000001b -#define SQ_VOP3_1__SRC0__SHIFT 0x00000000 -#define SQ_VOP3_1__SRC1__SHIFT 0x00000009 -#define SQ_VOP3_1__SRC2__SHIFT 0x00000012 -#define SQ_VOPC__ENCODING__SHIFT 0x00000019 -#define SQ_VOPC__OP__SHIFT 0x00000011 -#define SQ_VOPC__SRC0__SHIFT 0x00000000 -#define SQ_VOPC__VSRC1__SHIFT 0x00000009 -#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x00000000 -#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x00000000 -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x00000010 -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x00000018 -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x00000000 -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x00000008 -#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x00000008 -#define SQ_WAVE_HW_ID__ME_ID__SHIFT__CI__VI 0x0000001e -#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT__CI__VI 0x00000006 -#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT__CI__VI 0x00000018 -#define SQ_WAVE_HW_ID__RING_ID__SHIFT__SI 0x00000018 -#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0x0000000d -#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0x0000000c -#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x00000004 -#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x0000001b -#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x00000010 -#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x00000014 -#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x00000000 -#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x00000008 -#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x00000000 -#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0x0000000a -#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x00000010 -#define SQ_WAVE_IB_DBG0__KILL__SHIFT__CI 0x0000001b -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT__CI 0x0000001c -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x00000004 -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x00000005 -#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x00000003 -#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x00000004 -#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x00000008 -#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT__CI__VI 0x0000000c -#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT__SI 0x0000000d -#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x00000000 -#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x00000000 -#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x00000000 -#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x00000000 -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0x0000000c -#define SQ_WAVE_M0__M0__SHIFT 0x00000000 -#define SQ_WAVE_MODE__CSP__SHIFT 0x0000001d -#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0x0000000b -#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x00000008 -#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0x0000000c -#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x00000004 -#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x00000000 -#define SQ_WAVE_MODE__IEEE__SHIFT 0x00000009 -#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0x0000000a -#define SQ_WAVE_MODE__VSKIP__SHIFT 0x0000001c -#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x00000000 -#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x00000000 -#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT__CI__VI 0x00000015 -#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT__CI__VI 0x00000014 -#define SQ_WAVE_STATUS__DATA_ATC__SHIFT__CI 0x00000016 -#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT__CI 0x00000018 -#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x00000011 -#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x00000009 -#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x00000008 -#define SQ_WAVE_STATUS__HALT__SHIFT 0x0000000d -#define SQ_WAVE_STATUS__INST_ATC__SHIFT__CI__VI 0x00000017 -#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0x0000000c -#define SQ_WAVE_STATUS__IN_TG__SHIFT 0x0000000b -#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT__CI__VI 0x0000001b -#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x00000013 -#define SQ_WAVE_STATUS__PRIV__SHIFT 0x00000005 -#define SQ_WAVE_STATUS__SCC__SHIFT 0x00000000 -#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x00000012 -#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x00000001 -#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x00000006 -#define SQ_WAVE_STATUS__TRAP__SHIFT 0x0000000e -#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0x0000000f -#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x00000007 -#define SQ_WAVE_STATUS__VALID__SHIFT 0x00000010 -#define SQ_WAVE_STATUS__VCCZ__SHIFT 0x0000000a -#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT__SI__CI 0x00000003 -#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x00000000 -#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x00000000 -#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x00000000 -#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x00000000 -#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x0000001d -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x00000010 -#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x00000000 -#define SQ_WAVE_TTMP0__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP10__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP11__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP1__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP2__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP3__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP4__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP5__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP6__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP7__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP8__DATA__SHIFT 0x00000000 -#define SQ_WAVE_TTMP9__DATA__SHIFT 0x00000000 -#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 -#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 -#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 -#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000 -#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT__CI__VI 0x00000011 -#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x00000010 -#define SRBM_CNTL__READ_TIMEOUT__SHIFT__SI__CI 0x00000000 -#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x00000000 -#define SRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT__CI__VI 0x00000004 -#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x00000007 -#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x00000006 -#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x00000005 -#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x00000000 -#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x0000001c -#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x0000001b -#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x0000001a -#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x00000019 -#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x00000018 -#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x00000017 -#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x00000016 -#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x00000015 -#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x00000014 -#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x00000013 -#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x00000012 -#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x00000011 -#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x00000010 -#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0x0000000f -#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0x0000000e -#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0x0000000d -#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT__SI__CI 0x0000000c -#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0x0000000b -#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT__CI 0x00000001 -#define SRBM_DEBUG_SNAPSHOT__SAM_RDY__SHIFT__CI 0x00000003 -#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT__CI__VI 0x00000002 -#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x00000009 -#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT__SI__CI 0x0000001d -#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x00000008 -#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT__SI__CI 0x0000000a -#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000001 -#define SRBM_DEBUG__DRMDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT__SI 0x00000007 -#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000000 -#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT__CI__VI 0x00000008 -#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT__CI__VI 0x00000009 -#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT__CI__VI 0x00000007 -#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000002 -#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000004 -#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000006 -#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000005 -#define SRBM_DRMDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT__SI 0x00000008 -#define SRBM_DRMDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT__SI 0x00000000 -#define SRBM_GFX_CNTL__MEID__SHIFT__CI__VI 0x00000002 -#define SRBM_GFX_CNTL__PIPEID__SHIFT__CI__VI 0x00000000 -#define SRBM_GFX_CNTL__QUEUEID__SHIFT__CI__VI 0x00000008 -#define SRBM_GFX_CNTL__RINGID__SHIFT__SI 0x00000000 -#define SRBM_GFX_CNTL__VMID__SHIFT 0x00000004 -#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 -#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 -#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 -#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT__CI__VI 0x00000008 -#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT__CI__VI 0x00000000 -#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x00000000 -#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x00000000 -#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 -#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 -#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 -#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a -#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 -#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 -#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f -#define SRBM_READ_ERROR__READ_REQUESTER_ACP__SHIFT__CI 0x0000001b -#define SRBM_READ_ERROR__READ_REQUESTER_DRMDMA1__SHIFT__SI 0x00000015 -#define SRBM_READ_ERROR__READ_REQUESTER_DRMDMA__SHIFT__SI 0x0000001c -#define SRBM_READ_ERROR__READ_REQUESTER_DRM__SHIFT 0x0000001e -#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x00000019 -#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x00000018 -#define SRBM_READ_ERROR__READ_REQUESTER_SAM__SHIFT__CI 0x00000017 -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT__CI__VI 0x00000015 -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT__CI__VI 0x0000001c -#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x0000001a -#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x00000016 -#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x0000001d -#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT__SI__CI 0x00000014 -#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT__CI__VI 0x00000008 -#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT__CI__VI 0x00000000 -#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT__CI__VI 0x00000008 -#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT__CI__VI 0x00000000 -#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT__CI__VI 0x0000001a -#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x00000001 -#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT__CI__VI 0x0000000c -#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x00000005 -#define SRBM_SOFT_RESET__SOFT_RESET_DRMDMA1__SHIFT__SI 0x00000006 -#define SRBM_SOFT_RESET__SOFT_RESET_DRMDMA__SHIFT__SI 0x00000014 -#define SRBM_SOFT_RESET__SOFT_RESET_DRM__SHIFT 0x00000007 -#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x00000008 -#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x00000009 -#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0x0000000a -#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0x0000000b -#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT__SI__CI 0x00000017 -#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x00000016 -#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0x0000000e -#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT__CI 0x00000004 -#define SRBM_SOFT_RESET__SOFT_RESET_SAM__SHIFT__CI 0x0000001b -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT__CI__VI 0x00000006 -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT__CI__VI 0x00000014 -#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0x0000000f -#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT__CI__VI 0x00000010 -#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x00000015 -#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x00000012 -#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT__SI__CI 0x00000018 -#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x00000011 -#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x00000019 -#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT__SI__CI 0x00000013 -#define SRBM_STATUS2__CHUB_BUSY__SHIFT__CI__VI 0x00000009 -#define SRBM_STATUS2__DRMDMA1_BUSY__SHIFT__SI 0x00000006 -#define SRBM_STATUS2__DRMDMA1_RQ_PENDING__SHIFT__SI 0x00000002 -#define SRBM_STATUS2__DRMDMA_BUSY__SHIFT__SI 0x00000005 -#define SRBM_STATUS2__DRMDMA_RQ_PENDING__SHIFT__SI 0x00000000 -#define SRBM_STATUS2__SDMA1_BUSY__SHIFT__CI__VI 0x00000006 -#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT__CI__VI 0x00000002 -#define SRBM_STATUS2__SDMA_BUSY__SHIFT__CI__VI 0x00000005 -#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT__CI__VI 0x00000000 -#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x00000001 -#define SRBM_STATUS2__VCE_BUSY__SHIFT__SI__CI 0x00000007 -#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT__SI__CI 0x00000003 -#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x00000008 -#define SRBM_STATUS2__XSP_BUSY__SHIFT__SI__CI 0x00000004 -#define SRBM_STATUS__ACP_BUSY__SHIFT__CI__VI 0x00000010 -#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT__CI__VI 0x00000003 -#define SRBM_STATUS__BIF_BUSY__SHIFT 0x0000001d -#define SRBM_STATUS__DRM_BUSY__SHIFT 0x00000012 -#define SRBM_STATUS__DRM_RQ_PENDING__SHIFT 0x00000000 -#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x00000005 -#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x00000006 -#define SRBM_STATUS__IH_BUSY__SHIFT 0x00000011 -#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT__SI__CI 0x00000007 -#define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009 -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a -#define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b -#define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c -#define SRBM_STATUS__SAM_BUSY__SHIFT__CI 0x00000014 -#define SRBM_STATUS__SAM_RQ_PENDING__SHIFT__CI 0x00000002 -#define SRBM_STATUS__SEM_BUSY__SHIFT 0x0000000e -#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x00000004 -#define SRBM_STATUS__UVD_BUSY__SHIFT 0x00000013 -#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x00000001 -#define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008 -#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 -#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 -#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 -#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 -#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 -#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 -#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT__SI 0x00000000 -#define STATUS__CAP_LIST__SHIFT 0x00000004 -#define STATUS__DEVSEL_TIMING__SHIFT 0x00000009 -#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x00000007 -#define STATUS__INT_STATUS__SHIFT 0x00000003 -#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x00000008 -#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0x0000000f -#define STATUS__PCI_66_EN__SHIFT 0x00000005 -#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x0000000d -#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x0000000c -#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x0000000e -#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x0000000b -#define STATUS__UDF_EN__SHIFT__SI__CI 0x00000006 -#define STREAM_SYNCHRONIZATION__STREAM_SYNCHRONIZATION__SHIFT__SI 0x00000000 -#define STUTTER_A_CNT__STUTTER_OFF_MARK_A__SHIFT__SI 0x00000010 -#define STUTTER_A_CNT__STUTTER_ON_MARK_A__SHIFT__SI 0x00000000 -#define STUTTER_B_CNT__STUTTER_OFF_MARK_B__SHIFT__SI 0x00000010 -#define STUTTER_B_CNT__STUTTER_ON_MARK_B__SHIFT__SI 0x00000000 -#define SUB_CLASS__SUB_CLASS__SHIFT 0x00000000 -#define SVI2_NB_STATUS__Nb_Curr_Tel__SHIFT__CI__VI 0x00000000 -#define SVI2_NB_STATUS__Nb_Volt_Tel__SHIFT__CI__VI 0x00000010 -#define SVI2_NB_STATUS__RESERVED_1__SHIFT__CI__VI 0x00000008 -#define SVI2_NB_STATUS__RESERVED__SHIFT__CI__VI 0x00000019 -#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x00000006 -#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x0000001f -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001a -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000010 -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x0000000c -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x0000001c -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000009 -#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 -#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x0000001c -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x00000018 -#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x00000010 -#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x0000000f -#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0x0000000a -#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x00000007 -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x00000017 -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x00000016 -#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000010 -#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000000f -#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000007 -#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000009 -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x0000001a -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000017 -#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x0000000e -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001d -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x0000001f -#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x00000015 -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0x0000000d -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0x0000000c -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000019 -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x0000001a -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x0000001e -#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x00000017 -#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000008 -#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x00000018 -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x0000001b -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x0000001c -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x0000001f -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x0000001e -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x0000001d -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x0000001c -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x0000001b -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x0000001a -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x00000019 -#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x00000017 -#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x00000018 -#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x00000016 -#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x00000014 -#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x00000015 -#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x00000013 -#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT__CI__VI 0x00000011 -#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT__CI__VI 0x00000012 -#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT__CI__VI 0x00000010 -#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT__CI__VI 0x0000000e -#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT__CI__VI 0x0000000f -#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT__CI__VI 0x0000000d -#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0x0000000a -#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0x0000000b -#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x00000009 -#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x00000007 -#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x00000008 -#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT__CI__VI 0x00000006 -#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT__CI__VI 0x00000004 -#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT__CI__VI 0x00000005 -#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT__CI__VI 0x00000003 -#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT__CI__VI 0x00000001 -#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT__CI__VI 0x00000002 -#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_2__RESERVED1__SHIFT__SI 0x00000001 -#define SX_DEBUG_BUSY_2__RESERVED2__SHIFT__SI 0x0000000d -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x0000001f -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x0000001e -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x0000001d -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x0000001c -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x0000001b -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x0000001a -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x00000019 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x00000018 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x00000017 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x00000016 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x00000015 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x00000014 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x00000013 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x00000012 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x00000011 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x00000010 -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x0000000f -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x0000000e -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x0000000d -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x0000000b -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x0000000a -#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x00000009 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x00000008 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x00000007 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x00000006 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x00000005 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x00000004 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x00000003 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x00000002 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x00000001 -#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x00000018 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x00000017 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x00000016 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x00000015 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x00000014 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x00000013 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x00000012 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x00000011 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x00000010 -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x0000000f -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x0000000e -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x0000000d -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x0000000b -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x0000000a -#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x00000009 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x00000008 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x00000007 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x00000006 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x00000005 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x00000004 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x00000003 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x00000002 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x00000001 -#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x00000019 -#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x0000001f -#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x0000001e -#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x00000002 -#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x0000001b -#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x00000013 -#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x00000012 -#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x00000011 -#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x00000010 -#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0x0000000f -#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0x0000000e -#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0x0000000d -#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0x0000000b -#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0x0000000a -#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x00000009 -#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x00000008 -#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x00000007 -#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x00000006 -#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x00000005 -#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x00000004 -#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x00000000 -#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x00000014 -#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x00000001 -#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x00000003 -#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x0000001d -#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x0000001c -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x0000001a -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x00000019 -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x00000018 -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x00000017 -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x00000016 -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x00000015 -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT__CI__VI 0x00000000 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT__CI__VI 0x0000000a -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT__CI__VI 0x00000000 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT__CI__VI 0x0000000a -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT__CI__VI 0x0000000a -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x00000008 -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018 -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x00000000 -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x00000010 -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0x0000000c -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x0000001c -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x00000004 -#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x00000014 -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x00000004 -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT__CI__VI 0x0000001a -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x00000008 -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x00000010 -#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_VID_INDEX__SHIFT__SI 0x0000001c -#define TARGET_AND_CURRENT_PROFILE_INDEX__SPARE__SHIFT__SI 0x0000001a -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x00000000 -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT__CI__VI 0x0000001d -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0x0000000c -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x00000015 -#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_VID_INDEX__SHIFT__SI 0x0000001e -#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT__CI__VI 0x00000000 -#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 -#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x00000010 -#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x00000010 -#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0x0000000d -#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x00000016 -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT__CI__VI 0x00000000 -#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 -#define TA_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define TA_DEBUG_INDEX__INDEX__SHIFT 0x00000000 -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TA_RESERVED_010C__Unused__SHIFT__CI__VI 0x00000000 -#define TA_SCRATCH__SCRATCH__SHIFT 0x00000000 -#define TA_STATUS__AL_BUSY__SHIFT 0x0000001e -#define TA_STATUS__BUSY__SHIFT 0x0000001f -#define TA_STATUS__FA_BUSY__SHIFT 0x0000001d -#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x00000015 -#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x00000014 -#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x00000016 -#define TA_STATUS__FG_BUSY__SHIFT 0x00000019 -#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0x0000000d -#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0x0000000c -#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0x0000000e -#define TA_STATUS__FL_BUSY__SHIFT 0x0000001b -#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x00000011 -#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x00000010 -#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x00000012 -#define TA_STATUS__IN_BUSY__SHIFT 0x00000018 -#define TA_STATUS__LA_BUSY__SHIFT 0x0000001a -#define TA_STATUS__TA_BUSY__SHIFT 0x0000001c -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x00000000 -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x00000018 -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x0000001c -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x00000018 -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x0000001c -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TCC_CTRL__CACHE_SIZE__SHIFT 0x00000000 -#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x00000010 -#define TCC_CTRL__RATE__SHIFT 0x00000002 -#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0x0000000c -#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT__CI__VI 0x00000014 -#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x00000004 -#define TCC_EDC_COUNTER__DED_COUNT__SHIFT__SI__CI 0x00000010 -#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT__SI__CI 0x00000000 -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x00000018 -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x0000001c -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x00000018 -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x0000001c -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_REDUNDANCY__MC_SEL0__SHIFT__CI__VI 0x00000000 -#define TCC_REDUNDANCY__MC_SEL1__SHIFT__CI__VI 0x00000001 -#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x00000010 -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x00000000 -#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x00000018 -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x00000000 -#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x00000001 -#define TCI_STATUS__TCI_BUSY__SHIFT 0x00000000 -#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x00000006 -#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x00000004 -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x00000000 -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x00000009 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x00000008 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x00000018 -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x00000000 -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x00000010 -#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x00000000 -#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x00000004 -#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x00000008 -#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0x0000000c -#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x00000010 -#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x00000014 -#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x00000018 -#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x0000001c -#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x00000000 -#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x00000004 -#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x00000008 -#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0x0000000c -#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x00000010 -#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x00000014 -#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x00000018 -#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x0000001c -#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x0000001c -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT__CI__VI 0x00000005 -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT__CI__VI 0x00000004 -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x00000016 -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0x0000000f -#define TCP_CNTL__FORCE_HIT__SHIFT 0x00000000 -#define TCP_CNTL__FORCE_MISS__SHIFT 0x00000001 -#define TCP_CNTL__INV_ALL_VMIDS__SHIFT__CI__VI 0x0000001d -#define TCP_CNTL__L1_SIZE__SHIFT 0x00000002 -#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x00000000 -#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x00000010 -#define TCP_CREDIT__TD_CREDIT__SHIFT 0x0000001d -#define TCP_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define TCP_DEBUG_INDEX__INDEX__SHIFT 0x00000000 -#define TCP_EDC_COUNTER__DED_COUNT__SHIFT__SI__CI 0x00000010 -#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT__SI__CI 0x00000000 -#define TCP_INVALIDATE__START__SHIFT 0x00000000 -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_STATUS__TCP_BUSY__SHIFT 0x00000000 -#define TCP_WATCH0_ADDR_H__ADDR__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH0_ADDR_L__ADDR__SHIFT__CI__VI 0x00000006 -#define TCP_WATCH0_CNTL__MASK__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH0_CNTL__MODE__SHIFT__CI__VI 0x0000001d -#define TCP_WATCH0_CNTL__VALID__SHIFT__CI__VI 0x0000001f -#define TCP_WATCH0_CNTL__VMID__SHIFT__CI__VI 0x00000018 -#define TCP_WATCH1_ADDR_H__ADDR__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH1_ADDR_L__ADDR__SHIFT__CI__VI 0x00000006 -#define TCP_WATCH1_CNTL__MASK__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH1_CNTL__MODE__SHIFT__CI__VI 0x0000001d -#define TCP_WATCH1_CNTL__VALID__SHIFT__CI__VI 0x0000001f -#define TCP_WATCH1_CNTL__VMID__SHIFT__CI__VI 0x00000018 -#define TCP_WATCH2_ADDR_H__ADDR__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH2_ADDR_L__ADDR__SHIFT__CI__VI 0x00000006 -#define TCP_WATCH2_CNTL__MASK__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH2_CNTL__MODE__SHIFT__CI__VI 0x0000001d -#define TCP_WATCH2_CNTL__VALID__SHIFT__CI__VI 0x0000001f -#define TCP_WATCH2_CNTL__VMID__SHIFT__CI__VI 0x00000018 -#define TCP_WATCH3_ADDR_H__ADDR__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH3_ADDR_L__ADDR__SHIFT__CI__VI 0x00000006 -#define TCP_WATCH3_CNTL__MASK__SHIFT__CI__VI 0x00000000 -#define TCP_WATCH3_CNTL__MODE__SHIFT__CI__VI 0x0000001d -#define TCP_WATCH3_CNTL__VALID__SHIFT__CI__VI 0x0000001f -#define TCP_WATCH3_CNTL__VMID__SHIFT__CI__VI 0x00000018 -#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT__CI 0x00000004 -#define TCS_CGTT_SCLK_CTRL__ON_DELAY__SHIFT__CI 0x00000000 -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT__CI 0x0000001f -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT__CI 0x0000001e -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT__CI 0x0000001d -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT__CI 0x0000001c -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT__CI 0x0000001b -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT__CI 0x0000001a -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT__CI 0x00000019 -#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT__CI 0x00000018 -#define TCS_CTRL__RATE__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI 0x00000018 -#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI 0x0000001c -#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI 0x0000000a -#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI 0x00000014 -#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI 0x00000018 -#define TCS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT__CI 0x0000001c -#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI 0x0000000a -#define TCS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI 0x00000014 -#define TCS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT__CI 0x0000001c -#define TCS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT__CI 0x00000014 -#define TCS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT__CI 0x0000001c -#define TCS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT__CI 0x00000000 -#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT__CI 0x00000014 -#define TCS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT__CI 0x0000001c -#define TCS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT__CI 0x00000000 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT__CI__VI 0x0000000b -#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT__CI__VI 0x0000000d -#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT__CI__VI 0x0000000f -#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT__CI__VI 0x00000011 -#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT__CI__VI 0x00000013 -#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT__CI__VI 0x00000001 -#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT__CI__VI 0x00000015 -#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT__CI__VI 0x00000017 -#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT__CI__VI 0x00000019 -#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT__CI__VI 0x0000001b -#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT__CI__VI 0x0000001d -#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT__CI__VI 0x0000001f -#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT__CI__VI 0x00000003 -#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT__CI__VI 0x00000005 -#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT__CI__VI 0x00000007 -#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT__CI__VI 0x00000009 -#define TC_CFG_L1_VOLATILE__VOL__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT__CI__VI 0x00000000 -#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT__CI__VI 0x00000002 -#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT__CI__VI 0x00000004 -#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT__CI__VI 0x00000006 -#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT__CI__VI 0x00000008 -#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT__CI__VI 0x0000000a -#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT__CI__VI 0x0000000c -#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT__CI__VI 0x0000000e -#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT__CI__VI 0x00000010 -#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT__CI__VI 0x00000012 -#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT__CI__VI 0x00000014 -#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT__CI__VI 0x00000016 -#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT__CI__VI 0x00000018 -#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT__CI__VI 0x0000001a -#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT__CI__VI 0x0000001c -#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT__CI__VI 0x0000001e -#define TC_CFG_L2_VOLATILE__VOL__SHIFT__CI__VI 0x00000000 -#define TDP_ACC_CORE_0__Cmp_Unit_Tdp_Margin_Acc__SHIFT__CI__VI 0x00000000 -#define TDP_ACC_CORE_0__Cmp_Unit_Tdp_Sample_Cnt__SHIFT__CI__VI 0x00000018 -#define TDP_ACC_CORE_0__RESERVED__SHIFT__CI__VI 0x00000015 -#define TDP_ACC_CORE_1__Cmp_Unit_Tdp_Margin_Acc__SHIFT__CI__VI 0x00000000 -#define TDP_ACC_CORE_1__Cmp_Unit_Tdp_Sample_Cnt__SHIFT__CI__VI 0x00000018 -#define TDP_ACC_CORE_1__RESERVED__SHIFT__CI__VI 0x00000015 -#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f -#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT__CI__VI 0x00000014 -#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x00000009 -#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x00000013 -#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x00000010 -#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0x0000000b -#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x00000012 -#define TD_CNTL__PAD_STALL_EN__SHIFT 0x00000008 -#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT__CI__VI 0x0000000f -#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x00000000 -#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x00000004 -#define TD_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define TD_DEBUG_INDEX__INDEX__SHIFT 0x00000000 -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define TD_SCRATCH__SCRATCH__SHIFT 0x00000000 -#define TD_STATUS__BUSY__SHIFT 0x0000001f -#define THERMAL_PROTECT_COUNTER__THERMAL_PROTECT_COUNTER__SHIFT__SI 0x00000000 -#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x00000000 -#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x00000008 -#define THM_CMON_CTRL2__ADC_RANGE_RST__SHIFT__SI 0x00000000 -#define THM_CMON_CTRL__ADC_CFG__SHIFT__SI 0x0000000b -#define THM_CMON_CTRL__ADC_GAIN_ADJ_MODE__SHIFT__SI 0x0000001e -#define THM_CMON_CTRL__ADC_GAIN_ADJ__SHIFT__SI 0x00000007 -#define THM_CMON_CTRL__BGADJ_MODE__SHIFT__SI 0x0000001d -#define THM_CMON_CTRL__BGADJ__SHIFT__SI 0x00000001 -#define THM_CMON_CTRL__CMON_RESET__SHIFT__SI 0x0000001f -#define THM_CMON_CTRL__DAC_BYPASS__SHIFT__SI 0x00000011 -#define THM_CMON_CTRL__OFFSET_CAN_EN__SHIFT__SI 0x0000001b -#define THM_CMON_CTRL__PDB__SHIFT__SI 0x00000000 -#define THM_CMON_CTRL__SELF_CAL_EN__SHIFT__SI 0x0000001c -#define THM_CMON_CTRL__TESTCNTL__SHIFT__SI 0x0000000d -#define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT__CI 0x00000000 -#define THM_CTF_STATUS__CTF_THRESHOLD_EXCEEDED__SHIFT__CI 0x00000000 -#define THM_CTF_STATUS__CTF_TRIGGERED__SHIFT__CI 0x00000001 -#define THM_SMC_IND_DATA__SMC_IND_DATA__SHIFT__CI 0x00000000 -#define THM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT__CI 0x00000000 -#define THM_SW_TEMP__SW_TEMP__SHIFT__CI 0x00000000 -#define THM_TMON0_CSR_RD__READ_DATA__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_CSR_WR__CSR_ADDR__SHIFT__SI__CI 0x00000002 -#define THM_TMON0_CSR_WR__CSR_READ__SHIFT__SI__CI 0x00000001 -#define THM_TMON0_CSR_WR__CSR_WRITE__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_CSR_WR__SPARE__SHIFT__SI__CI 0x00000018 -#define THM_TMON0_CSR_WR__WRITE_DATA__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT__SI__CI 0x00000010 -#define THM_TMON0_CTRL__BGADJ_MODE__SHIFT__SI__CI 0x00000009 -#define THM_TMON0_CTRL__BGADJ__SHIFT__SI__CI 0x00000001 -#define THM_TMON0_CTRL__DEBUG_MODE__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_CTRL__INT_MEAS_EN__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_CTRL__POWER_DOWN__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_CTRL__TMON_PAUSE__SHIFT__SI__CI 0x0000000a -#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT__SI__CI 0x00000005 -#define THM_TMON0_INT_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_INT_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_INT_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL0_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL0_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL10_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL10_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL11_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL11_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL12_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL12_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL13_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL13_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL14_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL14_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL15_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL15_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL1_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL1_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL2_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL2_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL3_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL3_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL4_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL4_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL5_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL5_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL6_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL6_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL7_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL7_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL8_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL8_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIL9_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIL9_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR0_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR0_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR10_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR10_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR11_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR11_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR12_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR12_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR13_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR13_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR14_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR14_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR15_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR15_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR1_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR1_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR2_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR2_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR3_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR3_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR4_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR4_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR5_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR5_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR6_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR6_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR7_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR7_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR8_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR8_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON0_RDIR9_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON0_RDIR9_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_CSR_RD__READ_DATA__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_CSR_WR__CSR_ADDR__SHIFT__SI__CI 0x00000002 -#define THM_TMON1_CSR_WR__CSR_READ__SHIFT__SI__CI 0x00000001 -#define THM_TMON1_CSR_WR__CSR_WRITE__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_CSR_WR__SPARE__SHIFT__SI__CI 0x00000018 -#define THM_TMON1_CSR_WR__WRITE_DATA__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_CTRL2__RDIL_PRESENT__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_CTRL2__RDIR_PRESENT__SHIFT__SI__CI 0x00000010 -#define THM_TMON1_CTRL__BGADJ_MODE__SHIFT__SI__CI 0x00000009 -#define THM_TMON1_CTRL__BGADJ__SHIFT__SI__CI 0x00000001 -#define THM_TMON1_CTRL__DEBUG_MODE__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_CTRL__INT_MEAS_EN__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_CTRL__POWER_DOWN__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_CTRL__TMON_PAUSE__SHIFT__SI__CI 0x0000000a -#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT__SI__CI 0x00000005 -#define THM_TMON1_INT_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_INT_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_INT_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL0_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL0_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL10_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL10_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL11_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL11_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL12_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL12_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL13_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL13_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL14_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL14_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL15_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL15_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL1_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL1_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL2_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL2_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL3_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL3_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL4_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL4_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL5_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL5_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL6_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL6_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL7_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL7_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL8_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL8_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIL9_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIL9_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR0_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR0_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR10_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR10_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR11_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR11_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR12_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR12_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR13_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR13_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR14_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR14_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR15_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR15_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR1_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR1_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR2_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR2_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR3_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR3_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR4_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR4_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR5_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR5_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR6_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR6_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR7_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR7_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR8_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR8_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT__SI__CI 0x0000000c -#define THM_TMON1_RDIR9_DATA__VALID__SHIFT__SI__CI 0x0000000b -#define THM_TMON1_RDIR9_DATA__Z__SHIFT__SI__CI 0x00000000 -#define THM_TMON_CONFIG2__A__SHIFT__SI__CI 0x00000000 -#define THM_TMON_CONFIG2__B__SHIFT__SI__CI 0x0000000c -#define THM_TMON_CONFIG2__C__SHIFT__SI__CI 0x00000012 -#define THM_TMON_CONFIG2__K__SHIFT__SI__CI 0x0000001d -#define THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT__CI 0x00000005 -#define THM_TMON_CONFIG__DEBUG_BUS_EN__SHIFT__SI 0x00000005 -#define THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT__SI__CI 0x00000003 -#define THM_TMON_CONFIG__NUM_ACQ__SHIFT__SI__CI 0x00000000 -#define THM_TMON_CONFIG__RDI_INTERLEAVE__SHIFT__SI__CI 0x00000004 -#define THM_TMON_CONFIG__Z__SHIFT__SI__CI 0x00000015 -#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT__SI 0x00000008 -#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT__SI 0x00000004 -#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT__SI 0x00000000 -#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT__SI 0x00000008 -#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT__SI 0x00000000 -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT__SI 0x00000000 -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT__SI 0x00000001 -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT__SI 0x00000002 -#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT__SI 0x00000003 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT__SI 0x0000001f -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT__SI 0x00000004 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT__SI 0x00000007 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT__SI 0x00000008 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT__SI 0x00000000 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT__SI 0x0000000b -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT__SI 0x0000000c -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT__SI 0x0000000a -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT__SI 0x00000014 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT__SI 0x00000017 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT__SI 0x00000018 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT__SI 0x00000010 -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT__SI 0x0000001b -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT__SI 0x0000001c -#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT__SI 0x0000001a -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT__SI 0x00000004 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT__SI 0x00000007 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT__SI 0x00000008 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT__SI 0x00000000 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT__SI 0x0000000b -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT__SI 0x0000000c -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT__SI 0x0000000a -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT__SI 0x00000014 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT__SI 0x00000017 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT__SI 0x00000018 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT__SI 0x00000010 -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT__SI 0x0000001b -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT__SI 0x0000001c -#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT__SI 0x0000001a -#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT__SI 0x00000000 -#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT__SI 0x00000008 -#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT__SI 0x00000010 -#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT__SI 0x00000018 -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT__SI 0x00000000 -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT__SI 0x00000018 -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT__SI 0x00000008 -#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT__SI 0x00000010 -#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT__SI 0x00000004 -#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT__SI 0x00000019 -#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT__SI 0x00000018 -#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT__SI 0x00000000 -#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT__SI 0x00000009 -#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT__SI 0x00000008 -#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT__SI 0x00000011 -#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT__SI 0x00000010 -#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT__SI 0x00000000 -#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT__SI 0x00000000 -#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT__SI 0x00000010 -#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT__SI 0x00000000 -#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT__SI 0x00000010 -#define TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT__SI 0x00000000 -#define TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT__SI 0x00000010 -#define TST_MISC_CTRL__BITS31_4__SHIFT 0x00000004 -#define TST_MISC_CTRL__JTAG_SRBM_DIS__SHIFT 0x00000001 -#define TST_MISC_CTRL__TST_CNB_DONE__SHIFT 0x00000003 -#define TST_MISC_CTRL__TST_SMSCLK_DIS__SHIFT 0x00000002 -#define TST_MISC_CTRL__TST_TCLK_SLOW_EN__SHIFT 0x00000000 -#define TST_TC_JTAG_0__TST_TC_MODE__SHIFT 0x00000010 -#define TST_TC_JTAG_0__TST_TC_TDI__SHIFT 0x00000008 -#define TST_TC_JTAG_0__TST_TC_TDO_MASK__SHIFT 0x00000018 -#define TST_TC_JTAG_0__TST_TC_TMS__SHIFT 0x00000000 -#define TST_TC_JTAG_1__TC_TST_DONE__SHIFT 0x0000001f -#define TST_TC_JTAG_1__TC_TST_TDO__SHIFT 0x00000000 -#define UART_CLK_GPIO_SEL__CLK_OBSERVE_GPIO__SHIFT 0x0000000a -#define UART_CLK_GPIO_SEL__UART_RX_GPIO__SHIFT 0x00000005 -#define UART_CLK_GPIO_SEL__UART_TX_GPIO__SHIFT 0x00000000 -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_ACK__SHIFT__SI 0x00000008 -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_FLAG__SHIFT__SI 0x00000000 -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_INT_STATUS__SHIFT__SI 0x00000018 -#define UNDERFLOW_STATUS__DATA_UNDERFLOW_MASK__SHIFT__SI 0x00000010 -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_ACK__SHIFT__SI 0x00000009 -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_FLAG__SHIFT__SI 0x00000001 -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_INT_STATUS__SHIFT__SI 0x00000019 -#define UNDERFLOW_STATUS__REQUEST_UNDERFLOW_MASK__SHIFT__SI 0x00000011 -#define UNDERFLOW_STATUS__UNDERFLOW_MASK_NO_RTS_ACTIVE__SHIFT__SI 0x00000012 -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT__SI 0x00000000 -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT__SI 0x00000006 -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT__SI 0x00000004 -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT__SI 0x00000010 -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT__SI 0x0000000c -#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT__SI 0x00000008 -#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT__SI 0x0000000a -#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT__SI 0x00000009 -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT__SI 0x00000008 -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKA__SHIFT__SI 0x0000000c -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT__SI 0x00000000 -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT__SI 0x0000001c -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT__SI 0x00000018 -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT__SI 0x00000014 -#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT__SI 0x00000010 -#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT__SI 0x0000000a -#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT__SI 0x00000009 -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT__SI 0x00000008 -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKB__SHIFT__SI 0x0000000c -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT__SI 0x00000000 -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT__SI 0x0000001c -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT__SI 0x00000018 -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT__SI 0x00000014 -#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT__SI 0x00000010 -#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT__SI 0x0000000a -#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT__SI 0x00000009 -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT__SI 0x00000008 -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKC__SHIFT__SI 0x0000000c -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT__SI 0x00000000 -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT__SI 0x0000001c -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT__SI 0x00000018 -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT__SI 0x00000014 -#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT__SI 0x00000010 -#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT__SI 0x0000000a -#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT__SI 0x00000009 -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT__SI 0x00000008 -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKD__SHIFT__SI 0x0000000c -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT__SI 0x00000000 -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT__SI 0x0000001c -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT__SI 0x00000018 -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT__SI 0x00000014 -#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT__SI 0x00000010 -#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT__SI 0x0000000a -#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT__SI 0x00000009 -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT__SI 0x00000008 -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKE__SHIFT__SI 0x0000000c -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT__SI 0x00000000 -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT__SI 0x0000001c -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT__SI 0x00000018 -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT__SI 0x00000014 -#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT__SI 0x00000010 -#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT__SI 0x0000000a -#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT__SI 0x00000009 -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT__SI 0x00000008 -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_POLARITY_LINKF__SHIFT__SI 0x0000000c -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT__SI 0x00000000 -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT__SI 0x0000001c -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT__SI 0x00000018 -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT__SI 0x00000014 -#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT__SI 0x00000010 -#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT__SI 0x00000000 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT__SI 0x00000002 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT__SI 0x00000006 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT__SI 0x0000000a -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT__SI 0x0000000e -#define UNIPHY_MACRO_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT__SI 0x00000012 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS0__SHIFT__SI 0x00000000 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS1__SHIFT__SI 0x00000004 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS2__SHIFT__SI 0x00000008 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS3__SHIFT__SI 0x0000000c -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS4__SHIFT__SI 0x00000010 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS_STR_EN__SHIFT__SI 0x00000014 -#define UNIPHY_MACRO_CONTROL1__UNIPHY_TX_VS_STR__SHIFT__SI 0x00000018 -#define UNIPHY_MACRO_CONTROL2__UNIPHY_BGADJ__SHIFT__SI 0x0000000c -#define UNIPHY_MACRO_CONTROL2__UNIPHY_BGPDN__SHIFT__SI 0x0000001c -#define UNIPHY_MACRO_CONTROL2__UNIPHY_RESERVED__SHIFT__SI 0x00000000 -#define UNIPHY_MACRO_CONTROL2__UNIPHY_TX_VS_ADJ__SHIFT__SI 0x00000014 -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_BUF_PDNB__SHIFT__SI 0x00000000 -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_CLKF__SHIFT__SI 0x00000008 -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_CLKR__SHIFT__SI 0x00000010 -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_INT_CP_CNTL__SHIFT__SI 0x00000018 -#define UNIPHY_MACRO_CONTROL3__UNIPHY_P90PLL_PROP_CP_CNTL__SHIFT__SI 0x0000001c -#define UNIPHY_MACRO_CONTROL3__UNIPHY_PHYPLL_PDIV_SEL__SHIFT__SI 0x00000014 -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT__SI 0x00000000 -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT__SI 0x00000002 -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT__SI 0x00000004 -#define UNIPHY_MACRO_CONTROL4__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT__SI 0x00000006 -#define UNIPHY_MACRO_CONTROL4__UNIPHY_P90PLL_RESET_EN__SHIFT__SI 0x0000000c -#define UNIPHY_MACRO_CONTROL4__UNIPHY_P90PLL_TCLK_10X_SRC__SHIFT__SI 0x0000000d -#define UNIPHY_MACRO_CONTROL4__UNIPHY_PBYPASS__SHIFT__SI 0x0000000f -#define UNIPHY_MACRO_CONTROL4__UNIPHY_PG2PLL_VCTRLADC_EN__SHIFT__SI 0x00000014 -#define UNIPHY_MACRO_CONTROL4__UNIPHY_PTCLK_10X_EN__SHIFT__SI 0x00000011 -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_BG2PLL_VCTRLADC__SHIFT__SI 0x00000018 -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_EN__SHIFT__SI 0x0000000c -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_4__SHIFT__SI 0x0000001d -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT__SI 0x00000010 -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT__SI 0x0000000d -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_GEN_STATUS_4__SHIFT__SI 0x0000001e -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_GEN_STATUS__SHIFT__SI 0x00000014 -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_P90_BPLL_INTRESET__SHIFT__SI 0x0000001c -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT__SI 0x00000000 -#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TX__SHIFT__SI 0x00000004 -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_CLKINV__SHIFT__SI 0x0000000c -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_IDCLK_SEL__SHIFT__SI 0x00000008 -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_IDSCKSEL__SHIFT__SI 0x00000004 -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_INCOHERENT_BY2__SHIFT__SI 0x00000010 -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_ITCLKSEL__SHIFT__SI 0x0000001e -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_ITMDS_INCO_EN__SHIFT__SI 0x0000001c -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_PLL_ENABLE__SHIFT__SI 0x00000000 -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_PLL_PWRUP_SEQ_EN__SHIFT__SI 0x00000006 -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_PLL_RESET__SHIFT__SI 0x00000001 -#define UNIPHY_TRANSMITTER_CONTROL__UNIPHY_VCO_MODE__SHIFT__SI 0x00000014 -#define URGENCY_STAT__MEMORY_LEVEL__SHIFT__SI 0x00000008 -#define URGENCY_STAT__URGENCY_STAT__SHIFT__SI 0x00000000 -#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 -#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 -#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT__CI__VI 0x00000018 -#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT__CI__VI 0x0000001c -#define UVD_ADDR_MODE__ADDR_MODE_DBW_EN__SHIFT__SI 0x00000004 -#define UVD_ADDR_MODE__ADDR_MODE_DBW__SHIFT__SI 0x00000002 -#define UVD_ADDR_MODE__ADDR_MODE_DB__SHIFT__SI 0x00000005 -#define UVD_ADDR_MODE__ADDR_MODE__SHIFT__SI 0x00000000 -#define UVD_ADDR_MODE__ARRAY_MODE__SHIFT__SI 0x00000009 -#define UVD_ADDR_MODE__DBW_ARRAY_MODE__SHIFT__SI 0x0000000d -#define UVD_ADDR_MODE__DBW_FIELD_FORMAT__SHIFT__SI 0x00000008 -#define UVD_ADDR_MODE__DB_ARRAY_MODE__SHIFT__SI 0x00000011 -#define UVD_ADDR_MODE__DB_MP_ADDR_MODE_DECOUPLE__SHIFT__SI 0x00000007 -#define UVD_ADDR_MODE__USE_ADDR_MACRO__SHIFT__SI 0x00000015 -#define UVD_AVP_COOKIE_ID__ID__SHIFT__SI 0x00000000 -#define UVD_AVP_CSA_ADDR__ADDR__SHIFT__SI 0x00000000 -#define UVD_AVP_CSA_SIZE__SIZE__SHIFT__SI 0x00000000 -#define UVD_AVP_EXT_INT_CTX_ID__CTX_ID__SHIFT__SI 0x00000000 -#define UVD_AVP_EXT_INT_ID__ID__SHIFT__SI 0x00000000 -#define UVD_AVP_FCS_STATUS__STATUS__SHIFT__SI 0x00000000 -#define UVD_AVP_IDLE_COOKIE_ID__ID__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_HB_BASE__HB_BASE__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_HB_CNTL__HB_BUFSZ__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_HB_RPTR__HB_RPTR__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_HB_WPTR_LSB_ADDR__HB_WPTR_LSB_ADDR__SHIFT__SI 0x00000002 -#define UVD_AVP_RLC_HB_WPTR_MSB_ADDR__HB_WPTR_MSB_ADDR__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_HB_WPTR__HB_WPTR__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_RL_BASE__RL_BASE__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_RL_SIZE__RL_SIZE__SHIFT__SI 0x00000000 -#define UVD_AVP_RLC_SCRATCH__SCRATCH__SHIFT__SI 0x00000000 -#define UVD_CBUF_ID__CBUF_ID__SHIFT__SI 0x00000000 -#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT__SI 0x0000000c -#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT__SI 0x00000008 -#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT__SI 0x00000000 -#define UVD_CGC_CTRL__IDCT_MODE__SHIFT__SI 0x00000017 -#define UVD_CGC_CTRL__LBSI_MODE__SHIFT__SI 0x0000001a -#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT__SI 0x00000015 -#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT__SI 0x00000016 -#define UVD_CGC_CTRL__MPC_MODE__SHIFT__SI 0x00000019 -#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT__SI 0x00000012 -#define UVD_CGC_CTRL__MPRD_MODE__SHIFT__SI 0x00000018 -#define UVD_CGC_CTRL__RBC_MODE__SHIFT__SI 0x00000014 -#define UVD_CGC_CTRL__REGS_MODE__SHIFT__SI 0x00000013 -#define UVD_CGC_CTRL__SYS_MODE__SHIFT__SI 0x00000010 -#define UVD_CGC_CTRL__UDEC_MODE__SHIFT__SI 0x00000011 -#define UVD_CGC_GATE__IDCT__SHIFT__SI 0x00000007 -#define UVD_CGC_GATE__LBSI__SHIFT__SI 0x0000000a -#define UVD_CGC_GATE__LMI_MC__SHIFT__SI 0x00000005 -#define UVD_CGC_GATE__LMI_UMC__SHIFT__SI 0x00000006 -#define UVD_CGC_GATE__MPC__SHIFT__SI 0x00000009 -#define UVD_CGC_GATE__MPEG2__SHIFT__SI 0x00000002 -#define UVD_CGC_GATE__MPRD__SHIFT__SI 0x00000008 -#define UVD_CGC_GATE__RBC__SHIFT__SI 0x00000004 -#define UVD_CGC_GATE__REGS__SHIFT__SI 0x00000003 -#define UVD_CGC_GATE__SYS__SHIFT__SI 0x00000000 -#define UVD_CGC_GATE__UDEC__SHIFT__SI 0x00000001 -#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT__SI 0x0000000e -#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT__SI 0x0000000f -#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT__SI 0x00000015 -#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT__SI 0x00000016 -#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT__SI 0x0000000c -#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT__SI 0x0000000d -#define UVD_CGC_STATUS__MPC_DCLK__SHIFT__SI 0x00000014 -#define UVD_CGC_STATUS__MPC_SCLK__SHIFT__SI 0x00000013 -#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT__SI 0x00000007 -#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT__SI 0x00000006 -#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT__SI 0x00000008 -#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT__SI 0x00000011 -#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT__SI 0x00000010 -#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT__SI 0x00000012 -#define UVD_CGC_STATUS__RBC_SCLK__SHIFT__SI 0x0000000b -#define UVD_CGC_STATUS__REGS_SCLK__SHIFT__SI 0x00000009 -#define UVD_CGC_STATUS__REGS_VCLK__SHIFT__SI 0x0000000a -#define UVD_CGC_STATUS__SYS_DCLK__SHIFT__SI 0x00000001 -#define UVD_CGC_STATUS__SYS_SCLK__SHIFT__SI 0x00000000 -#define UVD_CGC_STATUS__SYS_VCLK__SHIFT__SI 0x00000002 -#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT__SI 0x00000004 -#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT__SI 0x00000003 -#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT__SI 0x00000005 -#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT__SI__CI 0x00000008 -#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT__SI__CI 0x00000010 -#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT__SI 0x00000000 -#define UVD_COOKIE_ID__ID__SHIFT__SI 0x00000000 -#define UVD_CSA_ADDR__ADDR__SHIFT__SI 0x00000000 -#define UVD_CSA_SIZE__SIZE__SHIFT__SI 0x00000000 -#define UVD_CTX_DATA__DATA__SHIFT__SI 0x00000000 -#define UVD_CTX_INDEX__INDEX__SHIFT__SI 0x00000000 -#define UVD_CXW_BLOCK_STATUS__LBSI_IDLE__SHIFT__SI 0x00000001 -#define UVD_CXW_BLOCK_STATUS__LMI_IDLE__SHIFT__SI 0x00000002 -#define UVD_CXW_BLOCK_STATUS__VCPU_IDLE__SHIFT__SI 0x00000000 -#define UVD_CXW_CNTL__EXTERNAL_CXW_EN__SHIFT__SI 0x00000001 -#define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN__SHIFT__SI 0x00000005 -#define UVD_CXW_CNTL__HOST_CXW_EN__SHIFT__SI 0x00000000 -#define UVD_CXW_CNTL__HOST_CXW_INT_EN__SHIFT__SI 0x00000004 -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_EN__SHIFT__SI 0x00000002 -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_IDCT_EN__SHIFT__SI 0x00000008 -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_IDCT_INT_EN__SHIFT__SI 0x0000000a -#define UVD_CXW_CNTL__REG_PRIVILEGE_FAULT_CXW_INT_EN__SHIFT__SI 0x00000006 -#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN__SHIFT__SI 0x00000003 -#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN__SHIFT__SI 0x00000007 -#define UVD_CXW_EN__CXW_ENABLE__SHIFT__SI 0x00000000 -#define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED__SHIFT__SI 0x00000001 -#define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED__SHIFT__SI 0x00000000 -#define UVD_CXW_EVENT__REG_PRIVILEGE_FAULT_EVENT_IDCT_OCCURRED__SHIFT__SI 0x00000006 -#define UVD_CXW_EVENT__REG_PRIVILEGE_FAULT_EVENT_OCCURRED__SHIFT__SI 0x00000002 -#define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT__SI 0x00000005 -#define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED__SHIFT__SI 0x00000004 -#define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT__SI 0x00000003 -#define UVD_CXW_FINISHED__CXW_FINISHED__SHIFT__SI 0x00000000 -#define UVD_CXW_INT_ID__ID__SHIFT__SI 0x00000000 -#define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR__SHIFT__SI 0x00000006 -#define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE__SHIFT__SI 0x00000000 -#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE__SHIFT__SI 0x0000001a -#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE__SHIFT__SI 0x0000001b -#define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET__SHIFT__SI 0x00000000 -#define UVD_CXW_SE__CXW_SCAN_ENABLE__SHIFT__SI 0x00000000 -#define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL__SHIFT__SI 0x00000000 -#define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT__SHIFT__SI 0x00000001 -#define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED__SHIFT__SI 0x00000000 -#define UVD_CXW_START__START_CXW__SHIFT__SI 0x00000000 -#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT__SI 0x00000000 -#define UVD_CXW_WR_INT_ID__ID__SHIFT__SI 0x00000000 -#define UVD_CXW_WR__DAT__SHIFT__SI 0x00000000 -#define UVD_CXW_WR__STAT__SHIFT__SI 0x0000001f -#define UVD_DBW_BUF_SIZE__PITCH__SHIFT__SI 0x00000004 -#define UVD_DBW_CHROMA_ADR__CHROMA_ADR__SHIFT__SI 0x00000006 -#define UVD_DBW_CHROMA_BOT_ADR__CHROMA_BOT_ADR__SHIFT__SI 0x00000006 -#define UVD_DBW_LUMA_ADR__LUMA_ADR__SHIFT__SI 0x00000006 -#define UVD_DBW_LUMA_BOT_ADR__LUMA_BOT_ADR__SHIFT__SI 0x00000006 -#define UVD_DBW_MACRO_TILE_CONFIG__CHROMA_INVERT_BANK__SHIFT__SI 0x00000004 -#define UVD_DBW_MACRO_TILE_CONFIG__CHROMA_INVERT_CHAN__SHIFT__SI 0x00000006 -#define UVD_DBW_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_6__SHIFT__SI 0x00000000 -#define UVD_DBW_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_7__SHIFT__SI 0x00000001 -#define UVD_DBW_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_8__SHIFT__SI 0x00000002 -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_10_SEL__SHIFT__SI 0x00000010 -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_11_SEL__SHIFT__SI 0x00000014 -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_12_SEL__SHIFT__SI 0x00000018 -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_13_SEL__SHIFT__SI 0x0000001c -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_6_SEL__SHIFT__SI 0x00000000 -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_7_SEL__SHIFT__SI 0x00000004 -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_8_SEL__SHIFT__SI 0x00000008 -#define UVD_DBW_MEM_ADDR_SEL_0__MEM_ADDR_9_SEL__SHIFT__SI 0x0000000c -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_14_SEL__SHIFT__SI 0x00000000 -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_15_SEL__SHIFT__SI 0x00000004 -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_16_SEL__SHIFT__SI 0x00000008 -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_17_SEL__SHIFT__SI 0x0000000c -#define UVD_DBW_MEM_ADDR_SEL_1__MEM_ADDR_18_SEL__SHIFT__SI 0x00000010 -#define UVD_DB_MACRO_TILE_CONFIG__CHROMA_INVERT_BANK__SHIFT__SI 0x00000004 -#define UVD_DB_MACRO_TILE_CONFIG__CHROMA_INVERT_CHAN__SHIFT__SI 0x00000006 -#define UVD_DB_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_6__SHIFT__SI 0x00000000 -#define UVD_DB_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_7__SHIFT__SI 0x00000001 -#define UVD_DB_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_8__SHIFT__SI 0x00000002 -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_10_SEL__SHIFT__SI 0x00000010 -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_11_SEL__SHIFT__SI 0x00000014 -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_12_SEL__SHIFT__SI 0x00000018 -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_13_SEL__SHIFT__SI 0x0000001c -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_6_SEL__SHIFT__SI 0x00000000 -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_7_SEL__SHIFT__SI 0x00000004 -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_8_SEL__SHIFT__SI 0x00000008 -#define UVD_DB_MEM_ADDR_SEL_0__MEM_ADDR_9_SEL__SHIFT__SI 0x0000000c -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_14_SEL__SHIFT__SI 0x00000000 -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_15_SEL__SHIFT__SI 0x00000004 -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_16_SEL__SHIFT__SI 0x00000008 -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_17_SEL__SHIFT__SI 0x0000000c -#define UVD_DB_MEM_ADDR_SEL_1__MEM_ADDR_18_SEL__SHIFT__SI 0x00000010 -#define UVD_DEBUG_CTRL__SEL0__SHIFT__SI 0x00000000 -#define UVD_DEBUG_CTRL__SEL1__SHIFT__SI 0x00000008 -#define UVD_DEBUG_CTRL__SWAP_MODE__SHIFT__SI 0x0000001e -#define UVD_DEBUG_SCRATCH__DATA_00__SHIFT__SI 0x00000000 -#define UVD_DEBUG_SCRATCH__DATA_01__SHIFT__SI 0x00000001 -#define UVD_DEBUG_SCRATCH__DATA_02__SHIFT__SI 0x00000002 -#define UVD_DEBUG_SCRATCH__DATA_03__SHIFT__SI 0x00000003 -#define UVD_DEBUG_SCRATCH__DATA_04__SHIFT__SI 0x00000004 -#define UVD_DEBUG_SCRATCH__DATA_05__SHIFT__SI 0x00000005 -#define UVD_DEBUG_SCRATCH__DATA_06__SHIFT__SI 0x00000006 -#define UVD_DEBUG_SCRATCH__DATA_07__SHIFT__SI 0x00000007 -#define UVD_DEBUG_SCRATCH__DATA_08__SHIFT__SI 0x00000008 -#define UVD_DEBUG_SCRATCH__DATA_09__SHIFT__SI 0x00000009 -#define UVD_DEBUG_SCRATCH__DATA_10__SHIFT__SI 0x0000000a -#define UVD_DEBUG_SCRATCH__DATA_11__SHIFT__SI 0x0000000b -#define UVD_DEBUG_SCRATCH__DATA_12__SHIFT__SI 0x0000000c -#define UVD_DEBUG_SCRATCH__DATA_13__SHIFT__SI 0x0000000d -#define UVD_DEBUG_SCRATCH__DATA_14__SHIFT__SI 0x0000000e -#define UVD_DEBUG_SCRATCH__DATA_15__SHIFT__SI 0x0000000f -#define UVD_DEBUG_SCRATCH__DATA_16__SHIFT__SI 0x00000010 -#define UVD_DEBUG_SCRATCH__DATA_17__SHIFT__SI 0x00000011 -#define UVD_DEBUG_SCRATCH__DATA_18__SHIFT__SI 0x00000012 -#define UVD_DEBUG_SCRATCH__DATA_19__SHIFT__SI 0x00000013 -#define UVD_DEBUG_SCRATCH__DATA_20__SHIFT__SI 0x00000014 -#define UVD_DEBUG_SCRATCH__DATA_21__SHIFT__SI 0x00000015 -#define UVD_DEBUG_SCRATCH__DATA_22__SHIFT__SI 0x00000016 -#define UVD_DEBUG_SCRATCH__DATA_23__SHIFT__SI 0x00000017 -#define UVD_DEBUG_SCRATCH__DATA_24__SHIFT__SI 0x00000018 -#define UVD_DEBUG_SCRATCH__DATA_25__SHIFT__SI 0x00000019 -#define UVD_DEBUG_SCRATCH__DATA_26__SHIFT__SI 0x0000001a -#define UVD_DEBUG_SCRATCH__DATA_27__SHIFT__SI 0x0000001b -#define UVD_DEBUG_SCRATCH__DATA_28__SHIFT__SI 0x0000001c -#define UVD_DEBUG_SCRATCH__DATA_29__SHIFT__SI 0x0000001d -#define UVD_DEBUG_SCRATCH__DATA_30__SHIFT__SI 0x0000001e -#define UVD_DEBUG_SCRATCH__DATA_31__SHIFT__SI 0x0000001f -#define UVD_DRM_CMD__CMD__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTDAT0__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTDAT1__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTDAT2__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTDAT3__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTKEY0__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTKEY1__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTKEY2__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_CNTKEY3__CNT__SHIFT__SI 0x00000000 -#define UVD_DRM_KEY0__KEY__SHIFT__SI 0x00000000 -#define UVD_DRM_KEY1__KEY__SHIFT__SI 0x00000000 -#define UVD_DRM_KEY2__KEY__SHIFT__SI 0x00000000 -#define UVD_DRM_KEY3__KEY__SHIFT__SI 0x00000000 -#define UVD_DRM_OFFSET__OFFSET__SHIFT__SI 0x00000000 -#define UVD_DRV_FW_MSG__MSG__SHIFT__SI 0x00000000 -#define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT__SI 0x00000010 -#define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT__SI 0x00000000 -#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT__SI 0x00000001 -#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT__SI 0x00000000 -#define UVD_FCS_AVP_SYS_INT_ACK__BLOCK_ACK__SHIFT__SI 0x00000001 -#define UVD_FCS_AVP_SYS_INT_ACK__CONTEXT_IDLE__SHIFT__SI 0x00000002 -#define UVD_FCS_AVP_SYS_INT_ACK__CTL_ACK__SHIFT__SI 0x00000000 -#define UVD_FCS_AVP_SYS_INT_ACK__EXT_INT__SHIFT__SI 0x00000003 -#define UVD_FCS_AVP_SYS_INT_ACK__NEW_RL__SHIFT__SI 0x00000004 -#define UVD_FCS_AVP_SYS_INT_EN__BLOCK_ACK__SHIFT__SI 0x00000001 -#define UVD_FCS_AVP_SYS_INT_EN__CONTEXT_IDLE__SHIFT__SI 0x00000002 -#define UVD_FCS_AVP_SYS_INT_EN__CTL_ACK__SHIFT__SI 0x00000000 -#define UVD_FCS_AVP_SYS_INT_EN__EXT_INT__SHIFT__SI 0x00000003 -#define UVD_FCS_AVP_SYS_INT_EN__NEW_RL__SHIFT__SI 0x00000004 -#define UVD_FCS_AVP_SYS_INT_STAT__BLOCK_ACK__SHIFT__SI 0x00000001 -#define UVD_FCS_AVP_SYS_INT_STAT__CONTEXT_IDLE__SHIFT__SI 0x00000002 -#define UVD_FCS_AVP_SYS_INT_STAT__CTL_ACK__SHIFT__SI 0x00000000 -#define UVD_FCS_AVP_SYS_INT_STAT__EXT_INT__SHIFT__SI 0x00000003 -#define UVD_FCS_AVP_SYS_INT_STAT__NEW_RL__SHIFT__SI 0x00000004 -#define UVD_FCS_AVP_VCPU_INT_ACK__BLOCK_ACK__SHIFT__SI 0x00000001 -#define UVD_FCS_AVP_VCPU_INT_ACK__CONTEXT_IDLE__SHIFT__SI 0x00000002 -#define UVD_FCS_AVP_VCPU_INT_ACK__CTL_ACK__SHIFT__SI 0x00000000 -#define UVD_FCS_AVP_VCPU_INT_ACK__EXT_INT__SHIFT__SI 0x00000003 -#define UVD_FCS_AVP_VCPU_INT_ACK__NEW_RL__SHIFT__SI 0x00000004 -#define UVD_FCS_AVP_VCPU_INT_EN__BLOCK_ACK__SHIFT__SI 0x00000001 -#define UVD_FCS_AVP_VCPU_INT_EN__CONTEXT_IDLE__SHIFT__SI 0x00000002 -#define UVD_FCS_AVP_VCPU_INT_EN__CTL_ACK__SHIFT__SI 0x00000000 -#define UVD_FCS_AVP_VCPU_INT_EN__EXT_INT__SHIFT__SI 0x00000003 -#define UVD_FCS_AVP_VCPU_INT_EN__NEW_RL__SHIFT__SI 0x00000004 -#define UVD_FCS_AVP_VCPU_INT_STAT__BLOCK_ACK__SHIFT__SI 0x00000001 -#define UVD_FCS_AVP_VCPU_INT_STAT__CONTEXT_IDLE__SHIFT__SI 0x00000002 -#define UVD_FCS_AVP_VCPU_INT_STAT__CTL_ACK__SHIFT__SI 0x00000000 -#define UVD_FCS_AVP_VCPU_INT_STAT__EXT_INT__SHIFT__SI 0x00000003 -#define UVD_FCS_AVP_VCPU_INT_STAT__NEW_RL__SHIFT__SI 0x00000004 -#define UVD_FCS_CTRL__ADM_MODE__SHIFT__SI 0x00000000 -#define UVD_FCS_STATUS__STATUS__SHIFT__SI 0x00000000 -#define UVD_FCS_SYS_INT_ACK__GPF__SHIFT__SI 0x00000007 -#define UVD_FCS_SYS_INT_ACK__HOST_CXW__SHIFT__SI 0x00000005 -#define UVD_FCS_SYS_INT_ACK__IDLE_CXW__SHIFT__SI 0x00000006 -#define UVD_FCS_SYS_INT_ACK__NEW_RL__SHIFT__SI 0x00000008 -#define UVD_FCS_SYS_INT_ACK__RBC_PRIV_FAULT_IDCT__SHIFT__SI 0x00000004 -#define UVD_FCS_SYS_INT_ACK__RBC_PRIV_FAULT__SHIFT__SI 0x00000003 -#define UVD_FCS_SYS_INT_ACK__SEMA_SIG_INC_TIMEOUT__SHIFT__SI 0x00000002 -#define UVD_FCS_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT__SHIFT__SI 0x00000001 -#define UVD_FCS_SYS_INT_ACK__SEMA_WAIT_INC_TIMEOUT__SHIFT__SI 0x00000000 -#define UVD_FCS_SYS_INT_EN__GPF__SHIFT__SI 0x00000007 -#define UVD_FCS_SYS_INT_EN__HOST_CXW__SHIFT__SI 0x00000005 -#define UVD_FCS_SYS_INT_EN__IDLE_CXW__SHIFT__SI 0x00000006 -#define UVD_FCS_SYS_INT_EN__NEW_RL__SHIFT__SI 0x00000008 -#define UVD_FCS_SYS_INT_EN__RBC_PRIV_FAULT_IDCT__SHIFT__SI 0x00000004 -#define UVD_FCS_SYS_INT_EN__RBC_PRIV_FAULT__SHIFT__SI 0x00000003 -#define UVD_FCS_SYS_INT_EN__SEMA_SIG_INC_TIMEOUT__SHIFT__SI 0x00000002 -#define UVD_FCS_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT__SHIFT__SI 0x00000001 -#define UVD_FCS_SYS_INT_EN__SEMA_WAIT_INC_TIMEOUT__SHIFT__SI 0x00000000 -#define UVD_FCS_SYS_INT_STAT__GPF__SHIFT__SI 0x00000007 -#define UVD_FCS_SYS_INT_STAT__HOST_CXW__SHIFT__SI 0x00000005 -#define UVD_FCS_SYS_INT_STAT__IDLE_CXW__SHIFT__SI 0x00000006 -#define UVD_FCS_SYS_INT_STAT__NEW_RL__SHIFT__SI 0x00000008 -#define UVD_FCS_SYS_INT_STAT__RBC_PRIV_FAULT_IDCT__SHIFT__SI 0x00000004 -#define UVD_FCS_SYS_INT_STAT__RBC_PRIV_FAULT__SHIFT__SI 0x00000003 -#define UVD_FCS_SYS_INT_STAT__SEMA_SIG_INC_TIMEOUT__SHIFT__SI 0x00000002 -#define UVD_FCS_SYS_INT_STAT__SEMA_WAIT_FAULT_TIMEOUT__SHIFT__SI 0x00000001 -#define UVD_FCS_SYS_INT_STAT__SEMA_WAIT_INC_TIMEOUT__SHIFT__SI 0x00000000 -#define UVD_FCS_VCPU_INT_ACK__GPF__SHIFT__SI 0x00000007 -#define UVD_FCS_VCPU_INT_ACK__HOST_CXW__SHIFT__SI 0x00000005 -#define UVD_FCS_VCPU_INT_ACK__IDLE_CXW__SHIFT__SI 0x00000006 -#define UVD_FCS_VCPU_INT_ACK__NEW_RL__SHIFT__SI 0x00000008 -#define UVD_FCS_VCPU_INT_ACK__RBC_PRIV_FAULT_IDCT__SHIFT__SI 0x00000004 -#define UVD_FCS_VCPU_INT_ACK__RBC_PRIV_FAULT__SHIFT__SI 0x00000003 -#define UVD_FCS_VCPU_INT_ACK__SEMA_SIG_INC_TIMEOUT__SHIFT__SI 0x00000002 -#define UVD_FCS_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT__SHIFT__SI 0x00000001 -#define UVD_FCS_VCPU_INT_ACK__SEMA_WAIT_INC_TIMEOUT__SHIFT__SI 0x00000000 -#define UVD_FCS_VCPU_INT_EN__GPF__SHIFT__SI 0x00000007 -#define UVD_FCS_VCPU_INT_EN__HOST_CXW__SHIFT__SI 0x00000005 -#define UVD_FCS_VCPU_INT_EN__IDLE_CXW__SHIFT__SI 0x00000006 -#define UVD_FCS_VCPU_INT_EN__NEW_RL__SHIFT__SI 0x00000008 -#define UVD_FCS_VCPU_INT_EN__RBC_PRIV_FAULT_IDCT__SHIFT__SI 0x00000004 -#define UVD_FCS_VCPU_INT_EN__RBC_PRIV_FAULT__SHIFT__SI 0x00000003 -#define UVD_FCS_VCPU_INT_EN__SEMA_SIG_INC_TIMEOUT__SHIFT__SI 0x00000002 -#define UVD_FCS_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT__SHIFT__SI 0x00000001 -#define UVD_FCS_VCPU_INT_EN__SEMA_WAIT_INC_TIMEOUT__SHIFT__SI 0x00000000 -#define UVD_FCS_VCPU_INT_STAT__GPF__SHIFT__SI 0x00000007 -#define UVD_FCS_VCPU_INT_STAT__HOST_CXW__SHIFT__SI 0x00000005 -#define UVD_FCS_VCPU_INT_STAT__IDLE_CXW__SHIFT__SI 0x00000006 -#define UVD_FCS_VCPU_INT_STAT__NEW_RL__SHIFT__SI 0x00000008 -#define UVD_FCS_VCPU_INT_STAT__RBC_PRIV_FAULT_IDCT__SHIFT__SI 0x00000004 -#define UVD_FCS_VCPU_INT_STAT__RBC_PRIV_FAULT__SHIFT__SI 0x00000003 -#define UVD_FCS_VCPU_INT_STAT__SEMA_SIG_INC_TIMEOUT__SHIFT__SI 0x00000002 -#define UVD_FCS_VCPU_INT_STAT__SEMA_WAIT_FAULT_TIMEOUT__SHIFT__SI 0x00000001 -#define UVD_FCS_VCPU_INT_STAT__SEMA_WAIT_INC_TIMEOUT__SHIFT__SI 0x00000000 -#define UVD_FW_BYTECNT__BYTECNT__SHIFT__SI 0x00000000 -#define UVD_FW_DEBUG_ADDR__DEBUG_ADDR__SHIFT__SI 0x00000000 -#define UVD_FW_DEBUG_DATA__DEBUG_DATA__SHIFT__SI 0x00000000 -#define UVD_FW_DRV_MSG_ACK__ACK__SHIFT__SI 0x00000000 -#define UVD_FW_EXP_RESULT0__RESULT0__SHIFT__SI 0x00000000 -#define UVD_FW_EXP_RESULT1__RESULT1__SHIFT__SI 0x00000000 -#define UVD_FW_EXP_RESULT2__RESULT2__SHIFT__SI 0x00000000 -#define UVD_FW_EXP_RESULT3__RESULT3__SHIFT__SI 0x00000000 -#define UVD_FW_LENGTH__LENGTH__SHIFT__SI 0x00000000 -#define UVD_FW_NONCE0__NONCE0__SHIFT__SI 0x00000000 -#define UVD_FW_NONCE1__NONCE1__SHIFT__SI 0x00000000 -#define UVD_FW_NONCE2__NONCE2__SHIFT__SI 0x00000000 -#define UVD_FW_NONCE3__NONCE3__SHIFT__SI 0x00000000 -#define UVD_FW_PERIODIC_CNTL__BUSY_EN__SHIFT__SI 0x00000002 -#define UVD_FW_PERIODIC_CNTL__RATE__SHIFT__SI 0x00000008 -#define UVD_FW_PERIODIC_CNTL__TIMER_DEC_PERIOD__SHIFT__SI 0x00000003 -#define UVD_FW_PERIODIC_CNTL__TIMER_DEFAULT__SHIFT__SI 0x0000000f -#define UVD_FW_PERIODIC_CNTL__TIMER_EN__SHIFT__SI 0x00000001 -#define UVD_FW_SELF_RECOVERY_CNTL__FW_SLF_RCV_RETRY__SHIFT__SI 0x00000009 -#define UVD_FW_SELF_RECOVERY_CNTL__FW_WATCHDOG_TIMER__SHIFT__SI 0x00000000 -#define UVD_FW_START__KEYSEL__SHIFT__SI 0x00000000 -#define UVD_FW_STATS__NUM_RUNS__SHIFT__SI 0x00000000 -#define UVD_FW_STATUS__ACTIVE__SHIFT__SI 0x00000001 -#define UVD_FW_STATUS__BUSY__SHIFT__SI 0x00000000 -#define UVD_FW_STATUS__DONE__SHIFT__SI 0x00000008 -#define UVD_FW_STATUS__EFUSE_CFG__SHIFT__SI 0x00000018 -#define UVD_FW_STATUS__EFUSE_DROP__SHIFT__SI 0x00000017 -#define UVD_FW_STATUS__EFUSE_ERR__SHIFT__SI 0x00000016 -#define UVD_FW_STATUS__EFUSE_RDY__SHIFT__SI 0x00000015 -#define UVD_FW_STATUS__FAIL__SHIFT__SI 0x00000011 -#define UVD_FW_STATUS__INVALID_0_PADDING__SHIFT__SI 0x00000013 -#define UVD_FW_STATUS__INVALID_LEN__SHIFT__SI 0x00000012 -#define UVD_FW_STATUS__INVALID_NONCE__SHIFT__SI 0x00000014 -#define UVD_FW_STATUS__PASS__SHIFT__SI 0x00000010 -#define UVD_FW_STATUS__SEND_EFUSE_REQ__SHIFT__SI 0x00000002 -#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT__SI 0x00000000 -#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT__SI 0x0000001f -#define UVD_GPCOM_SYS_CMD__CMD__SHIFT__SI 0x00000001 -#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT__SI 0x00000000 -#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT__SI 0x00000000 -#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT__SI 0x00000000 -#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT__SI 0x0000001f -#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT__SI 0x00000001 -#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT__SI 0x00000000 -#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT__SI 0x00000000 -#define UVD_GPF_STATUS__UMC_RD__SHIFT__SI 0x00000006 -#define UVD_GPF_STATUS__UMC_WR__SHIFT__SI 0x00000004 -#define UVD_GPF_STATUS__UVD_RD__SHIFT__SI 0x00000002 -#define UVD_GPF_STATUS__UVD_WR__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH0__DATA__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH1__DATA__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH2__DATA__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH3__DATA__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH4__DATA__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH5__DATA__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH6__DATA__SHIFT__SI 0x00000000 -#define UVD_GP_SCRATCH7__DATA__SHIFT__SI 0x00000000 -#define UVD_HEIGHT__DUM__SHIFT__SI 0x00000000 -#define UVD_IDLE_COOKIE_ID__ID__SHIFT__SI 0x00000000 -#define UVD_JOB_DONE__JOB_DONE__SHIFT__SI 0x00000000 -#define UVD_JOB_START__JOB_START__SHIFT__SI 0x00000000 -#define UVD_LBSI_ADDR_0__ADDR__SHIFT__SI 0x00000006 -#define UVD_LBSI_ADDR_0__BYTE_SWAP__SHIFT__SI 0x00000000 -#define UVD_LBSI_ADDR_0__FILL__SHIFT__SI 0x00000003 -#define UVD_LBSI_ADDR_0__VADDR__SHIFT__SI 0x00000002 -#define UVD_LBSI_ADDR_1__ADDR__SHIFT__SI 0x00000006 -#define UVD_LBSI_ADDR_1__BYTE_SWAP__SHIFT__SI 0x00000000 -#define UVD_LBSI_ADDR_1__FILL__SHIFT__SI 0x00000003 -#define UVD_LBSI_ADDR_1__VADDR__SHIFT__SI 0x00000002 -#define UVD_LBSI_BURST_LEN__BURST_LEN__SHIFT__SI 0x00000014 -#define UVD_LBSI_CONFIG__CONFIG__SHIFT__SI 0x00000000 -#define UVD_LBSI_CURR_ADDR__CURR_ADDR__SHIFT__SI 0x00000006 -#define UVD_LBSI_DRM_FLUSH_CTL_STATUS__LBSI_DRM_VCPU_RDY_TO_RST__SHIFT__SI 0x00000000 -#define UVD_LBSI_DRM_FLUSH_CTL_STATUS__LBSI_DRM_VCPU_STOP_REQ__SHIFT__SI 0x00000001 -#define UVD_LBSI_LEN_0__LEN__SHIFT__SI 0x00000000 -#define UVD_LBSI_LEN_0__STAT_0__SHIFT__SI 0x00000018 -#define UVD_LBSI_LEN_0__STAT_1__SHIFT__SI 0x0000001c -#define UVD_LBSI_LEN_1__LEN__SHIFT__SI 0x00000000 -#define UVD_LBSI_LEN_1__STAT_0__SHIFT__SI 0x00000018 -#define UVD_LBSI_LEN_1__STAT_1__SHIFT__SI 0x0000001c -#define UVD_LBSI_PF_BUFF_COUNT__ACTIVE_STREAM__SHIFT__SI 0x0000001a -#define UVD_LBSI_PF_BUFF_COUNT__NUM_BUFFERS__SHIFT__SI 0x0000001b -#define UVD_LBSI_PF_BUFF_COUNT__PEND_COUNT__SHIFT__SI 0x0000001c -#define UVD_LBSI_PF_BUFF_COUNT__PF_BYTE_COUNT__SHIFT__SI 0x00000000 -#define UVD_LBSI_RE_WAIT_COUNT__COUNT__SHIFT__SI 0x00000000 -#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT__SI 0x00000004 -#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT__SI 0x00000008 -#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT__SI 0x00000000 -#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT__SI 0x0000000c -#define UVD_LMI_ARB_CTRL__CM_RD_WAIT_EN__SHIFT__SI 0x00000009 -#define UVD_LMI_ARB_CTRL__CM_WR_WAIT_EN__SHIFT__SI 0x00000019 -#define UVD_LMI_ARB_CTRL__DBW_WR_WAIT_EN__SHIFT__SI 0x0000001b -#define UVD_LMI_ARB_CTRL__DB_RD_WAIT_EN__SHIFT__SI 0x0000000a -#define UVD_LMI_ARB_CTRL__DB_WR_WAIT_EN__SHIFT__SI 0x0000001a -#define UVD_LMI_ARB_CTRL__IDCT_RD_WAIT_EN__SHIFT__SI 0x0000000b -#define UVD_LMI_ARB_CTRL__IT_RD_WAIT_EN__SHIFT__SI 0x00000008 -#define UVD_LMI_ARB_CTRL__IT_WR_WAIT_EN__SHIFT__SI 0x00000018 -#define UVD_LMI_ARB_CTRL__LBSI_RD_WAIT_EN__SHIFT__SI 0x0000000d -#define UVD_LMI_ARB_CTRL__MPC_RD_WAIT_EN__SHIFT__SI 0x0000000c -#define UVD_LMI_ARB_CTRL__RBC_RD_WAIT_EN__SHIFT__SI 0x0000000e -#define UVD_LMI_ARB_CTRL__RD_WAIT_TIMER__SHIFT__SI 0x00000000 -#define UVD_LMI_ARB_CTRL__WR_WAIT_TIMER__SHIFT__SI 0x00000010 -#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT__SI 0x00000008 -#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT__SI 0x00000010 -#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT__SI 0x00000000 -#define UVD_LMI_AXI_ERR_STATUS__AXI_ERR_ADDR_LSBS__SHIFT__SI 0x00000004 -#define UVD_LMI_AXI_ERR_STATUS__AXI_ERR_AWRITE__SHIFT__SI 0x00000007 -#define UVD_LMI_AXI_ERR_STATUS__AXI_ERR_LEN__SHIFT__SI 0x00000000 -#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT__SI 0x00000002 -#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT__SI 0x00000003 -#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT__SI 0x00000000 -#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT__SI 0x00000001 -#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT__SI 0x00000004 -#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT__SI 0x00000005 -#define UVD_LMI_CLEAN_STATUS__CM_RD__SHIFT__SI 0x00000001 -#define UVD_LMI_CLEAN_STATUS__CM_WR__SHIFT__SI 0x00000011 -#define UVD_LMI_CLEAN_STATUS__DBW_WR__SHIFT__SI 0x00000013 -#define UVD_LMI_CLEAN_STATUS__DB_RD__SHIFT__SI 0x00000002 -#define UVD_LMI_CLEAN_STATUS__DB_WR__SHIFT__SI 0x00000012 -#define UVD_LMI_CLEAN_STATUS__FWV_RD__SHIFT__SI 0x00000008 -#define UVD_LMI_CLEAN_STATUS__IDCT_RD__SHIFT__SI 0x00000003 -#define UVD_LMI_CLEAN_STATUS__IT_RD__SHIFT__SI 0x00000000 -#define UVD_LMI_CLEAN_STATUS__IT_WR__SHIFT__SI 0x00000010 -#define UVD_LMI_CLEAN_STATUS__LBSI_RD__SHIFT__SI 0x00000005 -#define UVD_LMI_CLEAN_STATUS__MPC_RD__SHIFT__SI 0x00000004 -#define UVD_LMI_CLEAN_STATUS__RBC_RD__SHIFT__SI 0x00000006 -#define UVD_LMI_CLEAN_STATUS__SPH_WR__SHIFT__SI 0x00000015 -#define UVD_LMI_CLEAN_STATUS__VCPU_RD__SHIFT__SI 0x00000007 -#define UVD_LMI_CLEAN_STATUS__VCPU_WR__SHIFT__SI 0x00000014 -#define UVD_LMI_CRC0__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CRC1__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CRC2__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CRC3__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CRC4__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CRC5__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CRC6__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CRC7__CRC32__SHIFT__SI 0x00000000 -#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT__SI 0x00000002 -#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT__SI 0x00000007 -#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT__SI 0x00000003 -#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT__SI 0x00000004 -#define UVD_LMI_CTRL2__SPH_DIS__SHIFT__SI 0x00000000 -#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT__SI 0x00000008 -#define UVD_LMI_CTRL2__STALL_ARB__SHIFT__SI 0x00000001 -#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT__SI 0x0000000b -#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT__SI 0x00000016 -#define UVD_LMI_CTRL__CRC_RESET__SHIFT__SI 0x0000000e -#define UVD_LMI_CTRL__CRC_SEL__SHIFT__SI 0x0000000f -#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT__SI 0x0000000d -#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT__SI 0x00000017 -#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT__SI 0x00000018 -#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT__SI 0x00000014 -#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT__SI 0x00000019 -#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT__SI 0x0000000c -#define UVD_LMI_CTRL__REQ_MODE__SHIFT__SI 0x00000009 -#define UVD_LMI_CTRL__RFU__SHIFT__SI 0x0000001a -#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT__SI 0x00000015 -#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT__SI 0x00000008 -#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT__SI 0x00000000 -#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT__SI 0x00000000 -#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT__SI 0x00000010 -#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT__SI 0x0000001f -#define UVD_LMI_ISOC_CTRL__CM_EN__SHIFT__SI 0x00000005 -#define UVD_LMI_ISOC_CTRL__DB_EN__SHIFT__SI 0x00000006 -#define UVD_LMI_ISOC_CTRL__FWV_EN__SHIFT__SI 0x0000000c -#define UVD_LMI_ISOC_CTRL__IDCT_EN__SHIFT__SI 0x00000007 -#define UVD_LMI_ISOC_CTRL__IT_EN__SHIFT__SI 0x00000004 -#define UVD_LMI_ISOC_CTRL__LBSI_EN__SHIFT__SI 0x00000009 -#define UVD_LMI_ISOC_CTRL__MPC_EN__SHIFT__SI 0x00000008 -#define UVD_LMI_ISOC_CTRL__RANGE1_EN__SHIFT__SI 0x00000000 -#define UVD_LMI_ISOC_CTRL__RANGE2_EN__SHIFT__SI 0x00000001 -#define UVD_LMI_ISOC_CTRL__RBC_EN__SHIFT__SI 0x0000000a -#define UVD_LMI_ISOC_CTRL__VCPU_EN__SHIFT__SI 0x0000000b -#define UVD_LMI_ISOC_PREF_BASE1__ADDR__SHIFT__SI 0x00000000 -#define UVD_LMI_ISOC_PREF_BASE2__ADDR__SHIFT__SI 0x00000000 -#define UVD_LMI_ISOC_PREF_LIMIT1__ADDR__SHIFT__SI 0x00000000 -#define UVD_LMI_ISOC_PREF_LIMIT2__ADDR__SHIFT__SI 0x00000000 -#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT__SI 0x00000000 -#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT__SI 0x00000008 -#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT__SI 0x0000000a -#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT__SI 0x00000008 -#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT__SI 0x00000009 -#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT__SI 0x0000000b -#define UVD_LMI_LAT_CTRL__SCALE__SHIFT__SI 0x00000000 -#define UVD_LMI_LAT_CTRL__SKIP__SHIFT__SI 0x00000010 -#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT__SI 0x00000010 -#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT__SI 0x00000018 -#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT__SI 0x00000000 -#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT__SI 0x00000008 -#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT__SI 0x00000000 -#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT__SI 0x00000000 -#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT__SI 0x00000008 -#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT__SI 0x00000000 -#define UVD_LMI_RD_BURST_CTRL__CM__SHIFT__SI 0x00000004 -#define UVD_LMI_RD_BURST_CTRL__DB__SHIFT__SI 0x00000008 -#define UVD_LMI_RD_BURST_CTRL__IDCT__SHIFT__SI 0x0000000c -#define UVD_LMI_RD_BURST_CTRL__IT__SHIFT__SI 0x00000000 -#define UVD_LMI_RD_BURST_CTRL__LBSI__SHIFT__SI 0x00000014 -#define UVD_LMI_RD_BURST_CTRL__MPC__SHIFT__SI 0x00000010 -#define UVD_LMI_RD_BURST_CTRL__RBC__SHIFT__SI 0x00000018 -#define UVD_LMI_SPH__ADDR__SHIFT__SI 0x00000000 -#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT__SI 0x0000001f -#define UVD_LMI_SPH__STS_VALID__SHIFT__SI 0x0000001e -#define UVD_LMI_SPH__STS__SHIFT__SI 0x0000001c -#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT__SI 0x0000000c -#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT__SI 0x0000000d -#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT__SI 0x00000007 -#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT__SI 0x00000008 -#define UVD_LMI_STATUS__READ_CLEAN__SHIFT__SI 0x00000000 -#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT__SI 0x0000000b -#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT__SI 0x00000009 -#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT__SI 0x00000004 -#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT__SI 0x0000000a -#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT__SI 0x00000006 -#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT__SI 0x00000005 -#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT__SI 0x00000003 -#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT__SI 0x00000002 -#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT__SI 0x00000001 -#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT__SI 0x0000000a -#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT__SI 0x00000012 -#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT__SI 0x00000018 -#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT__SI 0x0000000e -#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT__SI 0x00000010 -#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT__SI 0x00000002 -#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT__SI 0x0000000c -#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT__SI 0x00000016 -#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT__SI 0x00000000 -#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT__SI 0x00000004 -#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT__SI 0x0000001a -#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT__SI 0x00000006 -#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT__SI 0x00000008 -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT__SI 0x00000001 -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT__SI 0x00000002 -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT__SI 0x00000009 -#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT__SI 0x0000000a -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT__SI 0x00000011 -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT__SI 0x00000012 -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT__SI 0x00000019 -#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT__SI 0x0000001a -#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT__SI 0x00000000 -#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT__SI 0x00000008 -#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT__SI 0x00000010 -#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT__SI 0x00000018 -#define UVD_LMI_UVD_SWAP__CM_RD__SHIFT__SI 0x00000002 -#define UVD_LMI_UVD_SWAP__CM_WR__SHIFT__SI 0x00000014 -#define UVD_LMI_UVD_SWAP__DBW_WR__SHIFT__SI 0x00000018 -#define UVD_LMI_UVD_SWAP__DB_RD__SHIFT__SI 0x00000004 -#define UVD_LMI_UVD_SWAP__DB_WR__SHIFT__SI 0x00000016 -#define UVD_LMI_UVD_SWAP__FWV_RD__SHIFT__SI 0x00000010 -#define UVD_LMI_UVD_SWAP__IDCT_RD__SHIFT__SI 0x00000006 -#define UVD_LMI_UVD_SWAP__IT_RD__SHIFT__SI 0x00000000 -#define UVD_LMI_UVD_SWAP__IT_WR__SHIFT__SI 0x00000012 -#define UVD_LMI_UVD_SWAP__LBSI_RD__SHIFT__SI 0x0000000a -#define UVD_LMI_UVD_SWAP__MPC_RD__SHIFT__SI 0x00000008 -#define UVD_LMI_UVD_SWAP__RBC_RD__SHIFT__SI 0x0000000c -#define UVD_LMI_UVD_SWAP__VCPU_RD__SHIFT__SI 0x0000000e -#define UVD_LMI_UVD_SWAP__VCPU_WR__SHIFT__SI 0x0000001a -#define UVD_LMI_VCPU_VM1__ENABLE__SHIFT__SI 0x0000001f -#define UVD_LMI_VCPU_VM1__LOWER_RANGE__SHIFT__SI 0x00000000 -#define UVD_LMI_VCPU_VM1__UPPER_RANGE__SHIFT__SI 0x0000000c -#define UVD_LMI_VCPU_VM__ENABLE__SHIFT__SI 0x0000001f -#define UVD_LMI_VCPU_VM__LOWER_RANGE__SHIFT__SI 0x00000000 -#define UVD_LMI_VCPU_VM__UPPER_RANGE__SHIFT__SI 0x0000000c -#define UVD_LMI_VM_CTRL__CM_VM__SHIFT__SI 0x00000001 -#define UVD_LMI_VM_CTRL__CSM_VM__SHIFT__SI 0x00000007 -#define UVD_LMI_VM_CTRL__DBW_VM__SHIFT__SI 0x0000000a -#define UVD_LMI_VM_CTRL__DB_VM__SHIFT__SI 0x00000004 -#define UVD_LMI_VM_CTRL__IB_VM__SHIFT__SI 0x00000006 -#define UVD_LMI_VM_CTRL__IT_VM__SHIFT__SI 0x00000002 -#define UVD_LMI_VM_CTRL__MP_VM__SHIFT__SI 0x00000003 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_CSM__SHIFT__SI 0x00000011 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_DBW__SHIFT__SI 0x00000013 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_IB__SHIFT__SI 0x00000019 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_LBSI__SHIFT__SI 0x00000014 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_RB_RPTR__SHIFT__SI 0x00000018 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_RB_WR__SHIFT__SI 0x00000017 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_RB__SHIFT__SI 0x00000016 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_UDEC__SHIFT__SI 0x00000012 -#define UVD_LMI_VM_CTRL__PRIV_CLIENT_VCPU__SHIFT__SI 0x00000010 -#define UVD_LMI_VM_CTRL__RB_RPTR_VM__SHIFT__SI 0x0000000b -#define UVD_LMI_VM_CTRL__RB_VM__SHIFT__SI 0x00000005 -#define UVD_LMI_VM_CTRL__RB_WR_VM__SHIFT__SI 0x00000008 -#define UVD_LMI_VM_CTRL__VCPU_VM__SHIFT__SI 0x00000000 -#define UVD_LMI_WR_BURST_CTRL__CM__SHIFT__SI 0x00000004 -#define UVD_LMI_WR_BURST_CTRL__DBW__SHIFT__SI 0x0000000c -#define UVD_LMI_WR_BURST_CTRL__DB__SHIFT__SI 0x00000008 -#define UVD_LMI_WR_BURST_CTRL__IT__SHIFT__SI 0x00000000 -#define UVD_LMI_WR_COMB_CTRL__CM_MAX__SHIFT__SI 0x0000000c -#define UVD_LMI_WR_COMB_CTRL__CM_TIMER__SHIFT__SI 0x00000008 -#define UVD_LMI_WR_COMB_CTRL__DBW_MAX__SHIFT__SI 0x0000001c -#define UVD_LMI_WR_COMB_CTRL__DBW_TIMER__SHIFT__SI 0x00000018 -#define UVD_LMI_WR_COMB_CTRL__DB_MAX__SHIFT__SI 0x00000014 -#define UVD_LMI_WR_COMB_CTRL__DB_TIMER__SHIFT__SI 0x00000010 -#define UVD_LMI_WR_COMB_CTRL__IT_MAX__SHIFT__SI 0x00000004 -#define UVD_LMI_WR_COMB_CTRL__IT_TIMER__SHIFT__SI 0x00000000 -#define UVD_MACRO_TILE_CONFIG__CHROMA_INVERT_BANK__SHIFT__SI 0x00000004 -#define UVD_MACRO_TILE_CONFIG__CHROMA_INVERT_CHAN__SHIFT__SI 0x00000006 -#define UVD_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_6__SHIFT__SI 0x00000000 -#define UVD_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_7__SHIFT__SI 0x00000001 -#define UVD_MACRO_TILE_CONFIG__SEL_UVD_MEM_ADDR_8__SHIFT__SI 0x00000002 -#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT__SI 0x00000004 -#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT__SI 0x00000000 -#define UVD_MASTINT_EN__SYS_EN__SHIFT__SI 0x00000002 -#define UVD_MASTINT_EN__VCPU_EN__SHIFT__SI 0x00000001 -#define UVD_MB_CTL_BUF_BASE__BASE__SHIFT__SI 0x00000000 -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_10_SEL__SHIFT__SI 0x00000010 -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_11_SEL__SHIFT__SI 0x00000014 -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_12_SEL__SHIFT__SI 0x00000018 -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_13_SEL__SHIFT__SI 0x0000001c -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_6_SEL__SHIFT__SI 0x00000000 -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_7_SEL__SHIFT__SI 0x00000004 -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_8_SEL__SHIFT__SI 0x00000008 -#define UVD_MEM_ADDR_SEL_0__MEM_ADDR_9_SEL__SHIFT__SI 0x0000000c -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_14_SEL__SHIFT__SI 0x00000000 -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_15_SEL__SHIFT__SI 0x00000004 -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_16_SEL__SHIFT__SI 0x00000008 -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_17_SEL__SHIFT__SI 0x0000000c -#define UVD_MEM_ADDR_SEL_1__MEM_ADDR_18_SEL__SHIFT__SI 0x00000010 -#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT__SI 0x00000000 -#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT__SI 0x00000000 -#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT__SI 0x00000000 -#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT__SI 0x00000010 -#define UVD_MPC_CNTL__DBG_MUX__SHIFT__SI 0x00000008 -#define UVD_MPC_CNTL__PERF_RST__SHIFT__SI 0x00000006 -#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT__SI 0x00000003 -#define UVD_MPC_CNTL__URGENT_EN__SHIFT__SI 0x00000012 -#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT__SI 0x00000000 -#define UVD_MPC_LUMA_HIT__CNTR__SHIFT__SI 0x00000000 -#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT__SI 0x00000000 -#define UVD_MPC_PERF0__MAX_LAT__SHIFT__SI 0x00000000 -#define UVD_MPC_PERF1__AVE_LAT__SHIFT__SI 0x00000000 -#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR0__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR10__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR11__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR12__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR13__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR14__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR15__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR16__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR1__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR2__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR3__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR4__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR5__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR6__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR7__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR8__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_BAR9__ADDR__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_PIC_ADDR_CONF__ADDR_40BIT_TRANSLATE_EN__SHIFT__SI 0x0000001f -#define UVD_MPC_REF_PIC_ADDR_CONF__INDEX_BITS__SHIFT__SI 0x00000000 -#define UVD_MPC_REF_PIC_ADDR_CONF__OFFSET_BITS__SHIFT__SI 0x00000004 -#define UVD_MPC_SET_ALU__FUNCT__SHIFT__SI 0x00000000 -#define UVD_MPC_SET_ALU__OPERAND__SHIFT__SI 0x00000004 -#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT__SI 0x00000000 -#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT__SI 0x00000006 -#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT__SI 0x0000000c -#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT__SI 0x00000012 -#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT__SI 0x00000018 -#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT__SI 0x00000000 -#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT__SI 0x00000006 -#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT__SI 0x0000000c -#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT__SI 0x00000000 -#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT__SI 0x00000006 -#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT__SI 0x0000000c -#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT__SI 0x00000012 -#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT__SI 0x00000018 -#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT__SI 0x00000000 -#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT__SI 0x00000006 -#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT__SI 0x0000000c -#define UVD_MPC_SET_MUX__SET_0__SHIFT__SI 0x00000000 -#define UVD_MPC_SET_MUX__SET_1__SHIFT__SI 0x00000003 -#define UVD_MPC_SET_MUX__SET_2__SHIFT__SI 0x00000006 -#define UVD_MPEG2_CTRL__EN__SHIFT__SI 0x00000000 -#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT__SI 0x00000010 -#define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT__SI 0x00000001 -#define UVD_MPEG2_ERROR__STATUS__SHIFT__SI 0x00000000 -#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT__SI 0x00000000 -#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT__SI 0x00000010 -#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT__SI 0x00000000 -#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT__SI 0x00000014 -#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT__SI 0x00000016 -#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT__SI 0x00000018 -#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT__SI 0x0000001a -#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT__SI 0x0000001c -#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT__SI 0x0000001e -#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT__SI 0x00000002 -#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT__SI 0x00000004 -#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT__SI 0x00000006 -#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT__SI 0x00000008 -#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT__SI 0x0000000a -#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT__SI 0x0000000c -#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT__SI 0x0000000e -#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT__SI 0x00000010 -#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT__SI 0x00000012 -#define UVD_NO_OP__NO_OP__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_CONF__CONCATENATE__SHIFT__SI 0x00000010 -#define UVD_PERF_BANK_CONF__PEEK__SHIFT__SI 0x00000008 -#define UVD_PERF_BANK_CONF__RESET__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT0__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT1__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT2__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT3__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT4__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT5__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT6__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_COUNT7__COUNT__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_EVENT_SEL0__SEL0__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_EVENT_SEL0__SEL1__SHIFT__SI 0x00000008 -#define UVD_PERF_BANK_EVENT_SEL0__SEL2__SHIFT__SI 0x00000010 -#define UVD_PERF_BANK_EVENT_SEL0__SEL3__SHIFT__SI 0x00000018 -#define UVD_PERF_BANK_EVENT_SEL1__SEL4__SHIFT__SI 0x00000000 -#define UVD_PERF_BANK_EVENT_SEL1__SEL5__SHIFT__SI 0x00000008 -#define UVD_PERF_BANK_EVENT_SEL1__SEL6__SHIFT__SI 0x00000010 -#define UVD_PERF_BANK_EVENT_SEL1__SEL7__SHIFT__SI 0x00000018 -#define UVD_PICCOUNT__DUM__SHIFT__SI 0x00000000 -#define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT__SI 0x00000000 -#define UVD_PITCH__DUM__SHIFT__SI 0x00000000 -#define UVD_PRIVILEGE_REG_MASK_1__RBC_PRIVILEGE_REG_MASK__SHIFT__SI 0x00000000 -#define UVD_PRIVILEGE_REG_MASK_IDCT__MASK__SHIFT__SI 0x00000000 -#define UVD_PWR_STATUS__STATUS__SHIFT__SI 0x00000000 -#define UVD_RBC_BDM_PRE__BDM_ENABLE__SHIFT__SI 0x00000000 -#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT__SI 0x00000013 -#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT__SI 0x00000008 -#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT__SI 0x00000019 -#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT__SI 0x00000010 -#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT__SI 0x00000000 -#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT__SI 0x00000016 -#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP__SHIFT__SI 0x00000010 -#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG__SHIFT__SI 0x00000000 -#define UVD_RBC_CAM_EN__RBC_CAM_EN__SHIFT__SI 0x00000000 -#define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX__SHIFT__SI 0x00000000 -#define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC__SHIFT__SI 0x00000000 -#define UVD_RBC_IB_BASE__IB_BASE__SHIFT__SI 0x00000006 -#define UVD_RBC_IB_PRIVILEGE_REG_CHECK__IB_PRIVILEGE_REG_CHECK_EN__SHIFT__SI 0x00000000 -#define UVD_RBC_IB_PRIVILEGE_REG_CHECK__IB_PRIVILEGE_REG_CHECK_IDCT_EN__SHIFT__SI 0x00000001 -#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT__SI 0x00000004 -#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT__SI 0x00000004 -#define UVD_RBC_PRIV_FAULT_REG__IDCTPDEC_REG__SHIFT__SI 0x00000012 -#define UVD_RBC_PRIV_FAULT_REG__UVDDEC_REG__SHIFT__SI 0x00000002 -#define UVD_RBC_RB_BASE__RB_BASE__SHIFT__SI 0x00000006 -#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT__SI 0x00000008 -#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT__SI 0x00000000 -#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT__SI 0x00000010 -#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT__SI 0x00000018 -#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT__SI 0x0000001c -#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT__SI 0x00000014 -#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT__SI 0x00000000 -#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT__SI 0x00000004 -#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT__SI 0x00000000 -#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT__SI 0x00000004 -#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT__SI 0x00000000 -#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT__SI 0x00000000 -#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT__SI 0x00000002 -#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT__SI 0x00000010 -#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT__SI 0x00000000 -#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT__SI 0x00000004 -#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT__SI 0x00000005 -#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT__SI 0x00000004 -#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT__SI 0x00000001 -#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT__SI 0x00000000 -#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT__SI 0x00000003 -#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT__SI 0x00000002 -#define UVD_REPLAY_OFFSET__REPLAY_OFFSET__SHIFT__SI 0x00000000 -#define UVD_RESERVED_0__RESERVED__SHIFT__SI 0x00000000 -#define UVD_RESERVED_1__RESERVED__SHIFT__SI 0x00000000 -#define UVD_RESERVED_2__RESERVED__SHIFT__SI 0x00000000 -#define UVD_RLC_CONTROL__RLC_REQ_ACK__SHIFT__SI 0x00000004 -#define UVD_RLC_CONTROL__RLC_REQ_TYPE__SHIFT__SI 0x00000000 -#define UVD_RLC_HB_BASE__HB_BASE__SHIFT__SI 0x00000000 -#define UVD_RLC_HB_CNTL__HB_BUFSZ__SHIFT__SI 0x00000000 -#define UVD_RLC_HB_RPTR__HB_RPTR__SHIFT__SI 0x00000000 -#define UVD_RLC_HB_WPTR_LSB_ADDR__HB_WPTR_LSB_ADDR__SHIFT__SI 0x00000002 -#define UVD_RLC_HB_WPTR_MSB_ADDR__HB_WPTR_MSB_ADDR__SHIFT__SI 0x00000000 -#define UVD_RLC_HB_WPTR__HB_WPTR__SHIFT__SI 0x00000000 -#define UVD_RLC_RL_BASE__RL_BASE__SHIFT__SI 0x00000000 -#define UVD_RLC_RL_SIZE__RL_SIZE__SHIFT__SI 0x00000000 -#define UVD_RLC_SCRATCH__SCRATCH__SHIFT__SI 0x00000000 -#define UVD_RMAP_CONF__CLOSED_ENTRY__SHIFT__SI 0x00000000 -#define UVD_RMAP_CONF__MAPUV_FLAG__SHIFT__SI 0x00000008 -#define UVD_RMAP_CONF__MAPUV__SHIFT__SI 0x00000009 -#define UVD_RMAP_CONF__MAPY_FLAG__SHIFT__SI 0x00000004 -#define UVD_RMAP_CONF__MAPY__SHIFT__SI 0x00000005 -#define UVD_SCRATCH_NP__DATA__SHIFT__SI 0x00000000 -#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT__SI 0x00000000 -#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT__SI 0x00000000 -#define UVD_SEMA_CMD__MODE__SHIFT__SI 0x00000006 -#define UVD_SEMA_CMD__REQ_CMD__SHIFT__SI 0x00000000 -#define UVD_SEMA_CMD__WR_PHASE__SHIFT__SI 0x00000004 -#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT__SI 0x00000001 -#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT__SI 0x00000000 -#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT__SI 0x00000018 -#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT__SI 0x00000001 -#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT__SI 0x00000000 -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT__SI 0x00000002 -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT__SI 0x00000003 -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT__SI 0x00000001 -#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT__SI 0x00000000 -#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT__SI 0x00000018 -#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT__SI 0x00000001 -#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT__SI 0x00000000 -#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT__SI 0x00000018 -#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT__SI 0x00000001 -#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT__SI 0x00000000 -#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT__SI 0x00000005 -#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT__SI 0x00000006 -#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT__SI 0x00000009 -#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT__SI 0x0000000c -#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT__SI 0x0000000a -#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT__SI 0x00000001 -#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT__SI 0x00000002 -#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT__SI 0x0000000d -#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT__SI 0x00000008 -#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT__SI 0x0000000b -#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT__SI 0x00000000 -#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT__SI 0x0000000e -#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT__SI 0x00000007 -#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT__SI 0x00000004 -#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT__SI 0x00000003 -#define UVD_STATUS__AVP_BLOCK_ACK__SHIFT__SI 0x0000000d -#define UVD_STATUS__AVP_BUSY__SHIFT__SI 0x00000008 -#define UVD_STATUS__AVP_CTL_ACK__SHIFT__SI 0x0000000a -#define UVD_STATUS__DRM_BUSY__SHIFT__SI 0x00000011 -#define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT__SI 0x0000000e -#define UVD_STATUS__IDCT_BUSY__SHIFT__SI 0x00000009 -#define UVD_STATUS__IDCT_CTL_ACK__SHIFT__SI 0x0000000b -#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT__SI 0x00000010 -#define UVD_STATUS__RBC_BUSY__SHIFT__SI 0x00000000 -#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT__SI 0x0000001f -#define UVD_STATUS__UVD_BLOCK_ACK__SHIFT__SI 0x0000000f -#define UVD_STATUS__UVD_CTL_ACK__SHIFT__SI 0x0000000c -#define UVD_STATUS__VCPU_REPORT__SHIFT__SI 0x00000001 -#define UVD_STOP_CONTEXT__CONTEXT_MODE__SHIFT__SI 0x00000001 -#define UVD_STOP_CONTEXT__STOP_CONTEXT__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_00__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_01__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_02__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_03__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_04__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_05__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_06__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_07__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_08__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_09__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_10__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_11__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_12__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_13__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_14__DATA__SHIFT__SI 0x00000000 -#define UVD_SW_SCRATCH_15__DATA__SHIFT__SI 0x00000000 -#define UVD_SYS_INT_ACK__CXW_FINISHED_ACK__SHIFT__SI 0x00000011 -#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT__SI 0x00000003 -#define UVD_SYS_INT_ACK__FCS_ACK__SHIFT__SI 0x0000001a -#define UVD_SYS_INT_ACK__FWV_STATUS_ACK__SHIFT__SI 0x0000000f -#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT__SI 0x00000018 -#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT__SI 0x00000010 -#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT__SI 0x0000000b -#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT__SI 0x0000000e -#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT__SI 0x0000000d -#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT__SI 0x00000019 -#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT__SI 0x0000001d -#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT__SI 0x00000006 -#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT__SI 0x00000016 -#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT__SI 0x00000002 -#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT__SI 0x00000017 -#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT__SI 0x00000001 -#define UVD_SYS_INT_ACK__SEMA_WAIT_INCOMPLETE_TIMEOUT_ACK__SHIFT__SI 0x00000000 -#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT__SI 0x0000000c -#define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK__SHIFT__SI 0x00000008 -#define UVD_SYS_INT_ACK__WPTR_IDLE_ACK__SHIFT__SI 0x00000015 -#define UVD_SYS_INT_EN__CXW_FINISHED_EN__SHIFT__SI 0x00000011 -#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT__SI 0x00000003 -#define UVD_SYS_INT_EN__FCS_EN__SHIFT__SI 0x0000001a -#define UVD_SYS_INT_EN__FWV_STATUS_EN__SHIFT__SI 0x0000000f -#define UVD_SYS_INT_EN__IDCT_EN__SHIFT__SI 0x00000018 -#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT__SI 0x00000010 -#define UVD_SYS_INT_EN__LBSI_EN__SHIFT__SI 0x0000000b -#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT__SI 0x0000000e -#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT__SI 0x0000000d -#define UVD_SYS_INT_EN__MPRD_EN__SHIFT__SI 0x00000019 -#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT__SI 0x0000001d -#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT__SI 0x00000006 -#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT__SI 0x00000016 -#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT__SI 0x00000002 -#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT__SI 0x00000017 -#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT__SI 0x00000001 -#define UVD_SYS_INT_EN__SEMA_WAIT_INCOMPLETE_TIMEOUT_EN__SHIFT__SI 0x00000000 -#define UVD_SYS_INT_EN__UDEC_EN__SHIFT__SI 0x0000000c -#define UVD_SYS_INT_EN__UVD_HOST_CXW_EN__SHIFT__SI 0x00000008 -#define UVD_SYS_INT_EN__WPTR_IDLE_EN__SHIFT__SI 0x00000015 -#define UVD_SYS_INT_STATUS__CXW_FINISHED_INT__SHIFT__SI 0x00000011 -#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT__SI 0x00000003 -#define UVD_SYS_INT_STATUS__FCS_INT__SHIFT__SI 0x0000001a -#define UVD_SYS_INT_STATUS__FWV_STATUS_INT__SHIFT__SI 0x0000000f -#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT__SI 0x00000012 -#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT__SI 0x00000018 -#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT__SI 0x00000010 -#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT__SI 0x0000000b -#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT__SI 0x0000000e -#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT__SI 0x0000000d -#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT__SI 0x0000001d -#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT__SI 0x00000019 -#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT__SHIFT__SI 0x00000016 -#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT__SI 0x00000006 -#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT__SI 0x00000002 -#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT__SI 0x00000017 -#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT__SI 0x00000001 -#define UVD_SYS_INT_STATUS__SEMA_WAIT_INCOMPLETE_TIMEOUT_INT__SHIFT__SI 0x00000000 -#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT__SI 0x0000000c -#define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT__SHIFT__SI 0x00000008 -#define UVD_SYS_INT_STATUS__WPTR_IDLE_INT__SHIFT__SI 0x00000015 -#define UVD_UDEC_ADR__SYNC_RE__SHIFT__SI 0x00000007 -#define UVD_UDEC_DBW_TILING_CONFIG__BANK_SWAPS__SHIFT__SI 0x0000000b -#define UVD_UDEC_DBW_TILING_CONFIG__BANK_TILING__SHIFT__SI 0x00000004 -#define UVD_UDEC_DBW_TILING_CONFIG__GROUP_SIZE__SHIFT__SI 0x00000006 -#define UVD_UDEC_DBW_TILING_CONFIG__PIPE_TILING__SHIFT__SI 0x00000001 -#define UVD_UDEC_DBW_TILING_CONFIG__ROW_TILING__SHIFT__SI 0x00000008 -#define UVD_UDEC_DBW_TILING_CONFIG__SAMPLE_SPLIT__SHIFT__SI 0x0000000e -#define UVD_UDEC_DB_TILING_CONFIG__BANK_SWAPS__SHIFT__SI 0x0000000b -#define UVD_UDEC_DB_TILING_CONFIG__BANK_TILING__SHIFT__SI 0x00000004 -#define UVD_UDEC_DB_TILING_CONFIG__GROUP_SIZE__SHIFT__SI 0x00000006 -#define UVD_UDEC_DB_TILING_CONFIG__PIPE_TILING__SHIFT__SI 0x00000001 -#define UVD_UDEC_DB_TILING_CONFIG__ROW_TILING__SHIFT__SI 0x00000008 -#define UVD_UDEC_DB_TILING_CONFIG__SAMPLE_SPLIT__SHIFT__SI 0x0000000e -#define UVD_UDEC_DEBUG_MUX__MUX__SHIFT__SI 0x00000000 -#define UVD_UDEC_TILING_CONFIG__BANK_SWAPS__SHIFT__SI 0x0000000b -#define UVD_UDEC_TILING_CONFIG__BANK_TILING__SHIFT__SI 0x00000004 -#define UVD_UDEC_TILING_CONFIG__GROUP_SIZE__SHIFT__SI 0x00000006 -#define UVD_UDEC_TILING_CONFIG__PIPE_TILING__SHIFT__SI 0x00000001 -#define UVD_UDEC_TILING_CONFIG__ROW_TILING__SHIFT__SI 0x00000008 -#define UVD_UDEC_TILING_CONFIG__SAMPLE_SPLIT__SHIFT__SI 0x0000000e -#define UVD_UMC_AVP_BLOCK_REQ__CMC_BLOCK_REQ__SHIFT__SI 0x00000000 -#define UVD_UMC_AVP_CTL_CMD__CMC_REQ__SHIFT__SI 0x00000000 -#define UVD_UMC_IDCT_BLOCK_REQ__CMC_BLOCK_REQ__SHIFT__SI 0x00000000 -#define UVD_UMC_IDCT_CTL_CMD__CMC_REQ__SHIFT__SI 0x00000000 -#define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ__SHIFT__SI 0x00000000 -#define UVD_UMC_UVD_CTL_CMD__CMC_REQ__SHIFT__SI 0x00000000 -#define UVD_UVBASE__DUM__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT__SI 0x00000000 -#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT__SI 0x00000000 -#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT__SI 0x00000008 -#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT__SI 0x00000004 -#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT__SI 0x00000011 -#define UVD_VCPU_CNTL__CLK_EN__SHIFT__SI 0x00000009 -#define UVD_VCPU_CNTL__DBG_MUX__SHIFT__SI 0x0000000d -#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT__SI 0x00000000 -#define UVD_VCPU_CNTL__JTAG_EN__SHIFT__SI 0x00000010 -#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT__SI 0x00000005 -#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT__SI 0x00000006 -#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT__SI 0x00000007 -#define UVD_VCPU_CNTL__TIE_Q_NO_FLOP__SHIFT__SI 0x00000013 -#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT__SI 0x00000012 -#define UVD_VCPU_CNTL__TRCE_EN__SHIFT__SI 0x0000000a -#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT__SI 0x0000000b -#define UVD_VCPU_DBG__DBG_RD__SHIFT__SI 0x00000000 -#define UVD_VCPU_INT_ACK__AVP_BLOCK_ACK_ACK__SHIFT__SI 0x00000007 -#define UVD_VCPU_INT_ACK__AVP_CTL_ACK_ACK__SHIFT__SI 0x00000003 -#define UVD_VCPU_INT_ACK__CXW_FINISHED_ACK__SHIFT__SI 0x00000013 -#define UVD_VCPU_INT_ACK__CXW_START_ACK__SHIFT__SI 0x00000012 -#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT__SI 0x0000001f -#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT__SI 0x0000001e -#define UVD_VCPU_INT_ACK__FWV_STATUS_ACK__SHIFT__SI 0x0000000f -#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT__SI 0x00000018 -#define UVD_VCPU_INT_ACK__IDCT_BLOCK_ACK_ACK__SHIFT__SI 0x00000009 -#define UVD_VCPU_INT_ACK__IDCT_CTL_ACK_ACK__SHIFT__SI 0x00000004 -#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT__SI 0x00000011 -#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT__SI 0x0000000b -#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT__SI 0x0000000e -#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT__SI 0x0000000d -#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT__SI 0x00000019 -#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT__SI 0x0000001d -#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT__SI 0x00000006 -#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT__SI 0x00000016 -#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT__SI 0x00000010 -#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT__SI 0x00000002 -#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT__SI 0x00000017 -#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT__SI 0x00000001 -#define UVD_VCPU_INT_ACK__SEMA_WAIT_INCOMPLETE_TIMEOUT_ACK__SHIFT__SI 0x00000000 -#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT__SI 0x0000000c -#define UVD_VCPU_INT_ACK__UVD_BLOCK_ACK_ACK__SHIFT__SI 0x0000000a -#define UVD_VCPU_INT_ACK__UVD_CTL_ACK_ACK__SHIFT__SI 0x00000005 -#define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK__SHIFT__SI 0x00000008 -#define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK__SHIFT__SI 0x00000015 -#define UVD_VCPU_INT_EN__AVP_BLOCK_ACK_EN__SHIFT__SI 0x00000007 -#define UVD_VCPU_INT_EN__AVP_CTL_ACK_EN__SHIFT__SI 0x00000003 -#define UVD_VCPU_INT_EN__CXW_FINISHED_EN__SHIFT__SI 0x00000013 -#define UVD_VCPU_INT_EN__CXW_START_EN__SHIFT__SI 0x00000012 -#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT__SI 0x0000001f -#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT__SI 0x0000001e -#define UVD_VCPU_INT_EN__FWV_STATUS_EN__SHIFT__SI 0x0000000f -#define UVD_VCPU_INT_EN__IDCT_BLOCK_ACK_EN__SHIFT__SI 0x00000009 -#define UVD_VCPU_INT_EN__IDCT_CTL_ACK_EN__SHIFT__SI 0x00000004 -#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT__SI 0x00000018 -#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT__SI 0x00000011 -#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT__SI 0x0000000b -#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT__SI 0x0000000e -#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT__SI 0x0000000d -#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT__SI 0x00000019 -#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT__SI 0x0000001d -#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT__SI 0x00000006 -#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT__SI 0x00000016 -#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT__SI 0x00000010 -#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT__SI 0x00000002 -#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT__SI 0x00000017 -#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT__SI 0x00000001 -#define UVD_VCPU_INT_EN__SEMA_WAIT_INCOMPLETE_TIMEOUT_EN__SHIFT__SI 0x00000000 -#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT__SI 0x0000000c -#define UVD_VCPU_INT_EN__UVD_BLOCK_ACK_EN__SHIFT__SI 0x0000000a -#define UVD_VCPU_INT_EN__UVD_CTL_ACK_EN__SHIFT__SI 0x00000005 -#define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN__SHIFT__SI 0x00000008 -#define UVD_VCPU_INT_EN__WPTR_IDLE_EN__SHIFT__SI 0x00000015 -#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT__SI 0x00000000 -#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT__SI 0x00000001 -#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT__SI 0x00000002 -#define UVD_VCPU_INT_STATUS__AVP_BLOCK_ACK_INT__SHIFT__SI 0x00000007 -#define UVD_VCPU_INT_STATUS__AVP_CTL_ACK_INT__SHIFT__SI 0x00000003 -#define UVD_VCPU_INT_STATUS__CXW_FINISHED_INT__SHIFT__SI 0x00000013 -#define UVD_VCPU_INT_STATUS__CXW_START_INT__SHIFT__SI 0x00000012 -#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT__SI 0x0000001f -#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT__SI 0x0000001e -#define UVD_VCPU_INT_STATUS__FWV_STATUS_INT__SHIFT__SI 0x0000000f -#define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT__SI 0x00000014 -#define UVD_VCPU_INT_STATUS__IDCT_BLOCK_ACK_INT__SHIFT__SI 0x00000009 -#define UVD_VCPU_INT_STATUS__IDCT_CTL_ACK_INT__SHIFT__SI 0x00000004 -#define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT__SI 0x00000018 -#define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT__SI 0x00000011 -#define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT__SI 0x0000000b -#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT__SI 0x0000000e -#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT__SI 0x0000000d -#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT__SI 0x0000001d -#define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT__SI 0x00000019 -#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT__SHIFT__SI 0x00000016 -#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT__SI 0x00000006 -#define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT__SI 0x00000010 -#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT__SI 0x00000002 -#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT__SI 0x00000017 -#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT__SI 0x00000001 -#define UVD_VCPU_INT_STATUS__SEMA_WAIT_INCOMPLETE_TIMEOUT_INT__SHIFT__SI 0x00000000 -#define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT__SI 0x0000000c -#define UVD_VCPU_INT_STATUS__UVD_BLOCK_ACK_INT__SHIFT__SI 0x0000000a -#define UVD_VCPU_INT_STATUS__UVD_CTL_ACK_INT__SHIFT__SI 0x00000005 -#define UVD_VCPU_INT_STATUS__UVD_HOST_CXW_INT__SHIFT__SI 0x00000008 -#define UVD_VCPU_INT_STATUS__WPTR_IDLE_INT__SHIFT__SI 0x00000015 -#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT__SI 0x00000000 -#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT__SI 0x00000000 -#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT__SI 0x00000000 -#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_CCOUNT__CCOUNT__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_DATA_H__DATA_H__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_DATA_L__DATA_L__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_EPC__EPC__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_EXCCAUSE__EXCCAUSE__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_ICOUNT__ICOUNT__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_PSTATUS__PSTATUS__SHIFT__SI 0x00000000 -#define UVD_VCPU_PDEBUG_PS__PS__SHIFT__SI 0x00000000 -#define UVD_VCPU_PRID__PRID__SHIFT__SI 0x00000000 -#define UVD_VCPU_TRCE_RD__DATA__SHIFT__SI 0x00000000 -#define UVD_VCPU_TRCE__PC__SHIFT__SI 0x00000000 -#define UVD_WIDTH__DUM__SHIFT__SI 0x00000000 -#define UVD_YBASE__DUM__SHIFT__SI 0x00000000 -#define VBLANK_STATUS__VBLANK_ACK__SHIFT__SI 0x00000004 -#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT__SI 0x00000011 -#define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT__SI 0x00000010 -#define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT__SI 0x00000000 -#define VBLANK_STATUS__VBLANK_STAT__SHIFT__SI 0x0000000c -#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT__CI 0x00000008 -#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT__CI 0x00000010 -#define VENDOR_CAP_LIST__CAP_ID__SHIFT__CI__VI 0x00000000 -#define VENDOR_CAP_LIST__LENGTH__SHIFT__CI__VI 0x00000010 -#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT__CI__VI 0x00000008 -#define VENDOR_ID__VENDOR_ID__SHIFT 0x00000000 -#define VGA25_PPLL_CNTL__VGA25_PPLL_CP__SHIFT__SI 0x00000008 -#define VGA25_PPLL_CNTL__VGA25_PPLL_CTL__SHIFT__SI 0x00000000 -#define VGA25_PPLL_CNTL__VGA25_PPLL_IBIAS__SHIFT__SI 0x00000018 -#define VGA25_PPLL_CNTL__VGA25_PPLL_LF_MODE__SHIFT__SI 0x0000000c -#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT__SI 0x00000004 -#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT__SI 0x00000000 -#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT__SI 0x00000010 -#define VGA25_PPLL_POST_DIV_SRC__VGA25_PPLL_POST_DIV_SRC__SHIFT__SI 0x00000000 -#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV__SHIFT__SI 0x00000000 -#define VGA25_PPLL_REF_DIV_SRC__VGA25_PPLL_REF_DIV_SRC__SHIFT__SI 0x00000000 -#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT__SI 0x00000000 -#define VGA28_PPLL_CNTL__VGA28_PPLL_CP__SHIFT__SI 0x00000008 -#define VGA28_PPLL_CNTL__VGA28_PPLL_CTL__SHIFT__SI 0x00000000 -#define VGA28_PPLL_CNTL__VGA28_PPLL_IBIAS__SHIFT__SI 0x00000018 -#define VGA28_PPLL_CNTL__VGA28_PPLL_LF_MODE__SHIFT__SI 0x0000000c -#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT__SI 0x00000004 -#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT__SI 0x00000000 -#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT__SI 0x00000010 -#define VGA28_PPLL_POST_DIV_SRC__VGA28_PPLL_POST_DIV_SRC__SHIFT__SI 0x00000000 -#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV__SHIFT__SI 0x00000000 -#define VGA28_PPLL_REF_DIV_SRC__VGA28_PPLL_REF_DIV_SRC__SHIFT__SI 0x00000000 -#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT__SI 0x00000000 -#define VGA41_PPLL_CNTL__VGA41_PPLL_CP__SHIFT__SI 0x00000008 -#define VGA41_PPLL_CNTL__VGA41_PPLL_CTL__SHIFT__SI 0x00000000 -#define VGA41_PPLL_CNTL__VGA41_PPLL_IBIAS__SHIFT__SI 0x00000018 -#define VGA41_PPLL_CNTL__VGA41_PPLL_LF_MODE__SHIFT__SI 0x0000000c -#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT__SI 0x00000004 -#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT__SI 0x00000000 -#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT__SI 0x00000010 -#define VGA41_PPLL_POST_DIV_SRC__VGA41_PPLL_POST_DIV_SRC__SHIFT__SI 0x00000000 -#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV__SHIFT__SI 0x00000000 -#define VGA41_PPLL_REF_DIV_SRC__VGA41_PPLL_REF_DIV_SRC__SHIFT__SI 0x00000000 -#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT__SI 0x00000000 -#define VGADCCIF_HOSTIF_R_ADDR__VGADCCIF_HOSTIF_R_ADDR__SHIFT__SI 0x00000000 -#define VGADCCIF_HOSTIF_W_ADDR__VGADCCIF_HOSTIF_W_ADDR__SHIFT__SI 0x00000000 -#define VGADCCIF_RENDERIF_R_ADDR__VGADCCIF_RENDERIF_R_ADDR__SHIFT__SI 0x00000000 -#define VGADCCIF_RENDERIF_W_ADDR__VGADCCIF_RENDERIF_W_ADDR__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_A__DBG_DCCIF_A__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_B__DBG_DCCIF_B__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_D__DBG_DCCIF_D__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_G__DBG_DCCIF_G__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_H__DBG_DCCIF_H__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_I__DBG_DCCIF_I__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_J__DBG_DCCIF_J__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_K__DBG_DCCIF_K__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_L__DBG_DCCIF_L__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_M__DBG_DCCIF_M__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_N__DBG_DCCIF_N__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_O__DBG_DCCIF_O__SHIFT__SI 0x00000000 -#define VGADCC_DBG_DCCIF_P__DBG_DCCIF_P__SHIFT__SI 0x00000000 -#define VGA_ADDR__ADDRESGEN_STATE__SHIFT__SI 0x00000000 -#define VGA_ADDR__ADDRESSGEN_A__SHIFT__SI 0x0000000a -#define VGA_ADDR__VGARENDER_ADDRSOPSTART__SHIFT__SI 0x00000005 -#define VGA_ADDR__VGARENDER_ADDRSOP__SHIFT__SI 0x00000006 -#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT__SI 0x00000014 -#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT__SI 0x00000018 -#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT__SI 0x00000010 -#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT__SI 0x00000008 -#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT__SI 0x00000000 -#define VGA_COHERENCY_TIMER_CNTL__VGA_COHE_SPEC_TIMER_SEL__SHIFT__SI 0x00000000 -#define VGA_CRTC__VGA_CRTC_CUR_STATE__SHIFT__SI 0x00000002 -#define VGA_CRTC__VGA_REG_CUROP__SHIFT__SI 0x00000016 -#define VGA_CRTC__VGA_REG_GEN_STATE__SHIFT__SI 0x00000007 -#define VGA_CRTC__VGA_REG_RDY__SHIFT__SI 0x00000001 -#define VGA_CRTC__VGA_REG_SUM__SHIFT__SI 0x0000000b -#define VGA_CRTC__VGA_START_REG_TRAN__SHIFT__SI 0x00000000 -#define VGA_DEBUG_ID__VGA_DEBUG_ID__SHIFT__SI 0x00000000 -#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT__SI 0x00000000 -#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT__SI 0x00000000 -#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT__SI 0x00000000 -#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT__SI 0x00000000 -#define VGA_GRAPH__ADDRESSGEN_ADDRSOPDONE__SHIFT__SI 0x00000016 -#define VGA_GRAPH__DCCIF_VGA_WACK__SHIFT__SI 0x00000015 -#define VGA_GRAPH__GFXPIXGEN_ENDOFCHAR__SHIFT__SI 0x00000013 -#define VGA_GRAPH__GFXPIXGEN_PIXGENDONE__SHIFT__SI 0x00000014 -#define VGA_GRAPH__GFXRENDERSUP_ADDPITCH__SHIFT__SI 0x00000018 -#define VGA_GRAPH__GFXRENDERSUP_ADDRSEL__SHIFT__SI 0x00000011 -#define VGA_GRAPH__GFXRENDERSUP_BUFOFFSET__SHIFT__SI 0x0000000e -#define VGA_GRAPH__GFXRENDERSUP_DWB_RST_WR_A__SHIFT__SI 0x0000001d -#define VGA_GRAPH__GFXRENDERSUP_DWORD_BUFFER_RDY__SHIFT__SI 0x0000001c -#define VGA_GRAPH__GFXRENDERSUP_DWORD_BUFFER_WEN__SHIFT__SI 0x0000001f -#define VGA_GRAPH__GFXRENDERSUP_FIRSTANDLASTPIX__SHIFT__SI 0x0000000b -#define VGA_GRAPH__GFXRENDERSUP_FIRSTCHARINLINE__SHIFT__SI 0x00000009 -#define VGA_GRAPH__GFXRENDERSUP_LASTCHARINLINE__SHIFT__SI 0x0000000a -#define VGA_GRAPH__GFXRENDERSUP_LAST_LINE_RENDERED__SHIFT__SI 0x0000001b -#define VGA_GRAPH__GFXRENDERSUP_LC__SHIFT__SI 0x00000017 -#define VGA_GRAPH__GFXRENDERSUP_PIXELWRITER_NXTWRADDRS__SHIFT__SI 0x0000001e -#define VGA_GRAPH__GFXRENDERSUP_RENDER_END__SHIFT__SI 0x0000001a -#define VGA_GRAPH__GFXRENDERSUP_STARTGFXPIXGEN__SHIFT__SI 0x00000008 -#define VGA_GRAPH__GFX_GEN_STATE__SHIFT__SI 0x00000000 -#define VGA_GRAPH__GFX_LINE_GEN_STATE__SHIFT__SI 0x00000004 -#define VGA_GRAPH__VGADCC_RD_RTR__SHIFT__SI 0x00000019 -#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT__SI 0x00000004 -#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT__SI 0x00000000 -#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT__SI 0x00000008 -#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT__SI 0x00000010 -#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT__SI 0x00000018 -#define VGA_HDP__BIF_VGA_A__SHIFT__SI 0x0000000e -#define VGA_HDP__BIF_VGA_BE__SHIFT__SI 0x00000001 -#define VGA_HDP__BIF_VGA_OP__SHIFT__SI 0x0000001e -#define VGA_HDP__BIF_VGA_SEND__SHIFT__SI 0x00000000 -#define VGA_HDP__BIF_VGA_WD__SHIFT__SI 0x00000007 -#define VGA_HDP__VGA_BIF_CLEAN__SHIFT__SI 0x0000000d -#define VGA_HDP__VGA_BIF_RD_VALID__SHIFT__SI 0x0000001f -#define VGA_HDP__VGA_BIF_RTR__SHIFT__SI 0x0000001d -#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT__SI 0x00000000 -#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT__SI 0x00000010 -#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT__SI 0x00000000 -#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT__SI 0x00000018 -#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT__SI 0x00000008 -#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT__SI 0x00000002 -#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT__SI 0x00000000 -#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT__SI 0x00000003 -#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT__SI 0x00000001 -#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT__SI 0x00000000 -#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT__SI 0x0000001d -#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT__SI 0x0000001f -#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT__SI 0x00000018 -#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT__SI 0x00000010 -#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT__SI 0x0000001a -#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT__SI 0x00000008 -#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT__SI 0x0000001b -#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT__SI 0x00000003 -#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT__SI 0x00000005 -#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT__SI 0x0000001c -#define VGA_MAIN__DISP_CUR_BUFF_FOLLOWS_VGA__SHIFT__SI 0x0000000f -#define VGA_MAIN__VGA_BLINK_PHASE__SHIFT__SI 0x00000013 -#define VGA_MAIN__VGA_BUF_CNTL__SHIFT__SI 0x0000001b -#define VGA_MAIN__VGA_CG_BUSY__SHIFT__SI 0x00000009 -#define VGA_MAIN__VGA_CUR_BUF1__SHIFT__SI 0x0000000a -#define VGA_MAIN__VGA_CUR_BUF2__SHIFT__SI 0x0000000b -#define VGA_MAIN__VGA_DATA_CHANGED__SHIFT__SI 0x00000004 -#define VGA_MAIN__VGA_DISP_BUF_CNTL__SHIFT__SI 0x0000000e -#define VGA_MAIN__VGA_ENER_END_OR_TIMEOUT__SHIFT__SI 0x00000017 -#define VGA_MAIN__VGA_FORCE_BLANK__SHIFT__SI 0x00000006 -#define VGA_MAIN__VGA_MAIN_CUR_STATE__SHIFT__SI 0x00000000 -#define VGA_MAIN__VGA_ONLY_UPDATE_REG__SHIFT__SI 0x00000005 -#define VGA_MAIN__VGA_OVERSCAN_UPDATE__SHIFT__SI 0x00000019 -#define VGA_MAIN__VGA_RENDERATTR_BUSY__SHIFT__SI 0x00000012 -#define VGA_MAIN__VGA_RENDER_BUFF_SEL__SHIFT__SI 0x0000001f -#define VGA_MAIN__VGA_RENDER_SYNC1__SHIFT__SI 0x0000001c -#define VGA_MAIN__VGA_RENDER_SYNC2__SHIFT__SI 0x0000001d -#define VGA_MAIN__VGA_RENDER_SYNC__SHIFT__SI 0x00000008 -#define VGA_MAIN__VGA_STARTCLK__SHIFT__SI 0x00000010 -#define VGA_MAIN__VGA_START_REG_TRAN__SHIFT__SI 0x00000007 -#define VGA_MAIN__VGA_START_RENDER__SHIFT__SI 0x0000001e -#define VGA_MAIN__VGA_UDPATE_REG__SHIFT__SI 0x00000011 -#define VGA_MAIN__VGA_VSYNC_TIMEOUT__SHIFT__SI 0x00000018 -#define VGA_MAIN__VGA_XTAL_REF_CLK__SHIFT__SI 0x00000015 -#define VGA_MAIN__VSYNC_BOTH_GEN_STATE__SHIFT__SI 0x0000000c -#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT__SI 0x00000000 -#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT__SI 0x00000000 -#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT__SI 0x00000000 -#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT__SI 0x00000010 -#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT__SI 0x00000000 -#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT__SI 0x00000010 -#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT__SI 0x00000008 -#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT__SI 0x00000000 -#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT__SI 0x00000004 -#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT__SI 0x00000010 -#define VGA_REG__VGA_GATED_CLOCK_RUNNING__SHIFT__SI 0x0000001b -#define VGA_REG__VGA_I_RBBM_WD__SHIFT__SI 0x0000001c -#define VGA_REG__VGA_RBBMIF_ADDR__SHIFT__SI 0x0000000e -#define VGA_REG__VGA_RBBMIF_BE__SHIFT__SI 0x00000016 -#define VGA_REG__VGA_RBBMIF_RDY0__SHIFT__SI 0x0000001a -#define VGA_REG__VGA_RBBMIF_RSTR__SHIFT__SI 0x0000000d -#define VGA_REG__VGA_RBBMIF_WSTR__SHIFT__SI 0x0000000c -#define VGA_REG__VGA_REG_RDY_I__SHIFT__SI 0x00000004 -#define VGA_REG__VGA_REG_REQ_O__SHIFT__SI 0x00000008 -#define VGA_REG__VGA_REG_WAIT_STATE__SHIFT__SI 0x00000000 -#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT__SI 0x00000019 -#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT__SI 0x00000005 -#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT__SI 0x00000000 -#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT__SI 0x00000007 -#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT__SI 0x00000008 -#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT__SI 0x00000018 -#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT__SI 0x00000010 -#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT__SI 0x00000000 -#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT__SI \ - 0x00000008 -#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT__SI 0x00000001 -#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT__SI \ - 0x00000009 -#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT__SI 0x00000002 -#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT__SI \ - 0x0000000a -#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT__SI 0x00000003 -#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT__SI \ - 0x0000000b -#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT__SI 0x00000004 -#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT__SI \ - 0x0000000c -#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT__SI 0x00000005 -#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT__SI \ - 0x0000000d -#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT__SI 0x00000010 -#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT__SI 0x00000012 -#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT__SI 0x00000011 -#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT__SI 0x00000000 -#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT__SI 0x00000008 -#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT__SI 0x00000010 -#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT__SI 0x00000000 -#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT__SI 0x00000018 -#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT__SI 0x00000008 -#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT__SI 0x00000002 -#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT__SI 0x00000000 -#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT__SI 0x00000003 -#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT__SI 0x00000001 -#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT__SI 0x00000008 -#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT__SI 0x00000000 -#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT__SI 0x00000000 -#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT__SI 0x00000018 -#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT__SI 0x00000010 -#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT__SI 0x00000008 -#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT__SI 0x00000000 -#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT__SI 0x00000000 -#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT__SI 0x00000008 -#define VGA_TEXT__TXTBLKGEN_FIRSTCHARINBUF__SHIFT__SI 0x0000000f -#define VGA_TEXT__TXTBLKGEN_FONTRDINDEX__SHIFT__SI 0x0000000d -#define VGA_TEXT__TXTBLKGEN_FONTREQUEST__SHIFT__SI 0x0000000c -#define VGA_TEXT__TXTBLKGEN_GENDONE__SHIFT__SI 0x0000000b -#define VGA_TEXT__TXTBLKGEN_LASTCHARDONE__SHIFT__SI 0x00000016 -#define VGA_TEXT__TXTBLKGEN_LASTCHARINBUF__SHIFT__SI 0x00000012 -#define VGA_TEXT__TXTBLKGEN_NXTCHARINROWREQ__SHIFT__SI 0x00000015 -#define VGA_TEXT__TXTRENDERSUP_DWB_RST_WR_A__SHIFT__SI 0x0000001d -#define VGA_TEXT__TXTRENDERSUP_DWORD_BUFFER_RDY__SHIFT__SI 0x0000001c -#define VGA_TEXT__TXTRENDERSUP_DWORD_BUFFER_WEN__SHIFT__SI 0x0000001f -#define VGA_TEXT__TXTRENDERSUP_FIRSTCHARINROW__SHIFT__SI 0x00000008 -#define VGA_TEXT__TXTRENDERSUP_LASTCHARINROW__SHIFT__SI 0x00000009 -#define VGA_TEXT__TXTRENDERSUP_LASTLINERENDERED__SHIFT__SI 0x00000018 -#define VGA_TEXT__TXTRENDERSUP_LASTLINE__SHIFT__SI 0x0000001a -#define VGA_TEXT__TXTRENDERSUP_PIXELWRITER_NXTWRADDRS__SHIFT__SI 0x0000001e -#define VGA_TEXT__TXTRENDERSUP_RDSEND__SHIFT__SI 0x00000017 -#define VGA_TEXT__TXTRENDERSUP_STARTGEN__SHIFT__SI 0x0000000a -#define VGA_TEXT__TXTRENDERSUP_TOPTXTLINE__SHIFT__SI 0x00000019 -#define VGA_TEXT__TXT_GEN_STATE__SHIFT__SI 0x00000000 -#define VGA_TEXT__TXT_LINE_GEN_STATE__SHIFT__SI 0x00000004 -#define VGA_VGADCCIF__VGADCCIF_VGAHDP_D_RDY__SHIFT__SI 0x00000008 -#define VGA_VGADCCIF__VGADCCIF_VGAHDP_R_RTR__SHIFT__SI 0x00000007 -#define VGA_VGADCCIF__VGADCCIF_VGAHDP_W_RTR__SHIFT__SI 0x00000005 -#define VGA_VGADCCIF__VGADCCIF_VGARENDER_VALID__SHIFT__SI 0x00000012 -#define VGA_VGADCCIF__VGADCC_VGA_R_RTR__SHIFT__SI 0x0000001e -#define VGA_VGADCCIF__VGADCC_VGA_TAG__SHIFT__SI 0x00000015 -#define VGA_VGADCCIF__VGADCC_VGA_VALID__SHIFT__SI 0x00000016 -#define VGA_VGADCCIF__VGADCC_VGA_WACK__SHIFT__SI 0x00000013 -#define VGA_VGADCCIF__VGADCC_VGA_W_RTR__SHIFT__SI 0x00000018 -#define VGA_VGADCCIF__VGAHDP_MULTIPLEX_READBUFFER_RD_SEND__SHIFT__SI 0x0000000c -#define VGA_VGADCCIF__VGAHDP_NULL_BYTE_ENABLE_READ__SHIFT__SI 0x00000009 -#define VGA_VGADCCIF__VGAHDP_READ_OUTSTANDING__SHIFT__SI 0x0000000b -#define VGA_VGADCCIF__VGAHDP_VGADCCIF_R_SEND__SHIFT__SI 0x00000006 -#define VGA_VGADCCIF__VGAHDP_VGADCCIF_WM__SHIFT__SI 0x00000000 -#define VGA_VGADCCIF__VGAHDP_VGADCCIF_W_SEND__SHIFT__SI 0x00000004 -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_R_RTR__SHIFT__SI 0x00000011 -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_R_SEND__SHIFT__SI 0x00000010 -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_WACK_REQ__SHIFT__SI 0x0000000f -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_W_RTR__SHIFT__SI 0x0000000e -#define VGA_VGADCCIF__VGARENDER_VGADCCIF_W_SEND__SHIFT__SI 0x0000000d -#define VGA_VGADCCIF__VGA_BIF_RD_VALID__SHIFT__SI 0x0000001f -#define VGA_VGADCCIF__VGA_DCCIF_WPHASE1_CLEAN__SHIFT__SI 0x0000000a -#define VGA_VGADCCIF__VGA_VGADCC_R_REQ__SHIFT__SI 0x0000001d -#define VGA_VGADCCIF__VGA_VGADCC_TAG__SHIFT__SI 0x00000014 -#define VGA_VGADCCIF__VGA_VGADCC_W_BE__SHIFT__SI 0x00000019 -#define VGA_VGADCCIF__VGA_VGADCC_W_REQ__SHIFT__SI 0x00000017 -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x00000006 -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x00000000 -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0x0000000b -#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x00000010 -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0x0000000c -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0x0000000d -#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x00000009 -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x00000005 -#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 -#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x00000007 -#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x00000008 -#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000002 -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000001 -#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x00000006 -#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000003 -#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x00000009 -#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x00000004 -#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000005 -#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 -#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x00000006 -#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 -#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x0000001f -#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x00000012 -#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x0000001c -#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x00000019 -#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x00000014 -#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x00000007 -#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x00000006 -#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x00000005 -#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x00000004 -#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x00000003 -#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x00000001 -#define VGT_DEBUG_REG0__cm_busy__SHIFT 0x0000000f -#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x00000015 -#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a -#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x00000011 -#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x00000010 -#define VGT_DEBUG_REG0__gs_busy__SHIFT 0x0000000c -#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x0000001b -#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x00000017 -#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x00000008 -#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0x0000000a -#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0x0000000d -#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 -#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d -#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x0000001e -#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x00000016 -#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x00000013 -#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0x0000000b -#define VGT_DEBUG_REG0__tm_busy__SHIFT 0x0000000e -#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x00000002 -#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x00000000 -#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x00000009 -#define VGT_DEBUG_REG10__SPARE2__SHIFT__CI__VI 0x00000009 -#define VGT_DEBUG_REG10__SPARE4__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x00000017 -#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0x0000000d -#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT__CI__VI 0x00000007 -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0x0000000b -#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x00000012 -#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x00000005 -#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0x0000000b -#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0x0000000c -#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0x0000000a -#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x00000014 -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x00000003 -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x0000001b -#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x00000009 -#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x0000001e -#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x00000015 -#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x00000010 -#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x00000013 -#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x00000008 -#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x0000001f -#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x0000001d -#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x00000007 -#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x00000006 -#define VGT_DEBUG_REG11__tm_busy__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG11__tm_busy_q__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG11__tm_noif_busy__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG11__tm_out_busy__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x00000011 -#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x00000018 -#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x00000016 -#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x00000017 -#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x00000004 -#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x0000001c -#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x00000019 -#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x0000001a -#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x0000001f -#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x00000003 -#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x0000001e -#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x0000001a -#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x00000019 -#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x00000018 -#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x00000003 -#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x00000012 -#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x00000017 -#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x00000016 -#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x0000001e -#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x0000001c -#define VGT_DEBUG_REG14__SPARE2__SHIFT 0x0000000c -#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x00000000 -#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x00000007 -#define VGT_DEBUG_REG14__SPARE__SHIFT 0x00000016 -#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x0000001f -#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x00000019 -#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x00000005 -#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0x0000000b -#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x00000004 -#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x0000001d -#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x0000001b -#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x00000015 -#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x0000001a -#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x00000006 -#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x00000009 -#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x00000014 -#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x0000001d -#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG15__cm_busy__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG15__cm_busy_q__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG15__counters_busy__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG15__counters_busy_q__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG15__counters_full__SHIFT 0x00000004 -#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x0000001c -#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x00000002 -#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x00000003 -#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x00000017 -#define VGT_DEBUG_REG16__SPARE29__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x00000000 -#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x00000019 -#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x00000001 -#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0x0000000d -#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x0000001c -#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x0000001f -#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x0000001e -#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x00000010 -#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x00000005 -#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x00000006 -#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x00000009 -#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x00000008 -#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0x0000000a -#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x00000007 -#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT__CI__VI 0x0000001d -#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x00000012 -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0x0000000c -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x00000006 -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x00000000 -#define VGT_DEBUG_REG18__SPARE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT__CI__VI 0x0000001d -#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT__CI__VI 0x00000017 -#define VGT_DEBUG_REG18__eop_r0_q__SHIFT__CI__VI 0x00000016 -#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT__CI__VI 0x0000001b -#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT__CI__VI 0x0000001c -#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG18__indx0_new_d__SHIFT__CI__VI 0x0000000d -#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT__CI__VI 0x00000011 -#define VGT_DEBUG_REG18__indx1_new_d__SHIFT__CI__VI 0x0000000e -#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG18__indx2_new_d__SHIFT__CI__VI 0x0000000f -#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT__CI__VI 0x00000014 -#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT__CI__VI 0x00000015 -#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT__CI__VI 0x00000006 -#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT__CI__VI 0x00000007 -#define VGT_DEBUG_REG18__pipe0_dr__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG18__pipe1_dr__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT__CI__VI 0x00000013 -#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG18__valid_indices__SHIFT__CI__VI 0x0000000b -#define VGT_DEBUG_REG18__vr_grp_read__SHIFT__CI__VI 0x00000003 -#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0x0000000d -#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x00000013 -#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x00000012 -#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x00000010 -#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x00000011 -#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x00000014 -#define VGT_DEBUG_REG19__filter_event__SHIFT 0x0000001f -#define VGT_DEBUG_REG19__hold_prim__SHIFT 0x0000000b -#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x0000001e -#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x0000001c -#define VGT_DEBUG_REG19__pa_clipp_fifo_busy__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG19__pa_clips_fifo_busy__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG19__pa_clipv_fifo_busy__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT__CI__VI 0x0000000a -#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x00000002 -#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x00000003 -#define VGT_DEBUG_REG19__separate_out_busy__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG19__separate_out_indx_busy__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT__CI__VI 0x00000009 -#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x00000009 -#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x00000015 -#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x00000013 -#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x00000011 -#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x00000008 -#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x00000017 -#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x00000019 -#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x00000007 -#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x00000006 -#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x00000005 -#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x00000004 -#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x00000003 -#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x00000002 -#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x00000001 -#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x00000000 -#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x0000001c -#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x0000001e -#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x0000001b -#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x0000001d -#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x0000001f -#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x0000001a -#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0x0000000c -#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0x0000000e -#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0x0000000a -#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000014 -#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000016 -#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0x0000000d -#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000f -#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000018 -#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000010 -#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000012 -#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0x0000000b -#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x00000011 -#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x0000001e -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x00000010 -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x00000000 -#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x0000001f -#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x0000001d -#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x00000018 -#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x0000001e -#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0x0000000d -#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x00000001 -#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x00000007 -#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x00000010 -#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x00000015 -#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x00000000 -#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x00000006 -#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x0000001c -#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x0000001f -#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x0000001d -#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x00000008 -#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x00000003 -#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x00000009 -#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x00000004 -#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0x0000000a -#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x00000019 -#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x00000005 -#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0x0000000b -#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x00000017 -#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x00000000 -#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x00000002 -#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x00000004 -#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x00000006 -#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x00000008 -#define VGT_DEBUG_REG22__cm_state21__SHIFT 0x0000000a -#define VGT_DEBUG_REG22__cm_state22__SHIFT 0x0000000c -#define VGT_DEBUG_REG22__cm_state23__SHIFT 0x0000000e -#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x00000010 -#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x00000012 -#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x00000014 -#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x00000016 -#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x00000018 -#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x0000001a -#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x0000001c -#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x0000001e -#define VGT_DEBUG_REG23__SPARE__SHIFT 0x00000018 -#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x00000000 -#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x00000009 -#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0x0000000a -#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x00000003 -#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x00000002 -#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x00000001 -#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0x0000000d -#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x00000008 -#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x00000007 -#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x00000006 -#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x00000005 -#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x0000001a -#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x00000000 -#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x0000001f -#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x0000001e -#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x00000000 -#define VGT_DEBUG_REG26__SPARE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG26__cm_state0__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG26__cm_state10__SHIFT__CI__VI 0x00000014 -#define VGT_DEBUG_REG26__cm_state11__SHIFT__CI__VI 0x00000016 -#define VGT_DEBUG_REG26__cm_state12__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG26__cm_state13__SHIFT__CI__VI 0x0000001a -#define VGT_DEBUG_REG26__cm_state14__SHIFT__CI__VI 0x0000001c -#define VGT_DEBUG_REG26__cm_state15__SHIFT__CI__VI 0x0000001e -#define VGT_DEBUG_REG26__cm_state1__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG26__cm_state2__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG26__cm_state3__SHIFT__CI__VI 0x00000006 -#define VGT_DEBUG_REG26__cm_state4__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG26__cm_state5__SHIFT__CI__VI 0x0000000a -#define VGT_DEBUG_REG26__cm_state6__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG26__cm_state7__SHIFT__CI__VI 0x0000000e -#define VGT_DEBUG_REG26__cm_state8__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG26__cm_state9__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x00000001 -#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x00000005 -#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x00000010 -#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x00000008 -#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x00000012 -#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x0000001f -#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x00000000 -#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x00000006 -#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x00000003 -#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x00000017 -#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x00000016 -#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x00000010 -#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x00000014 -#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x00000013 -#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x00000009 -#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x00000008 -#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0x0000000a -#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x0000001e -#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x0000001c -#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x00000019 -#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x0000001a -#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x0000001d -#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x0000001f -#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x00000017 -#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x00000016 -#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x00000010 -#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x00000014 -#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x00000013 -#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x00000009 -#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x00000008 -#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0x0000000a -#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x0000001e -#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x0000001c -#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x00000019 -#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x0000001a -#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x0000001d -#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x0000001f -#define VGT_DEBUG_REG2__SPARE__SHIFT__CI__VI 0x0000001d -#define VGT_DEBUG_REG2__SPARE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG2__grpModBusy__SHIFT__CI__VI 0x00000007 -#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT__CI__VI 0x0000000d -#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT__CI__VI 0x00000013 -#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT__CI__VI 0x0000000a -#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT__CI__VI 0x0000000b -#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT__CI__VI 0x00000011 -#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT__CI__VI 0x00000006 -#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT__CI__VI 0x0000001b -#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT__CI__VI 0x0000000e -#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT__CI__VI 0x00000003 -#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT__CI__VI 0x00000009 -#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT__CI__VI 0x0000000f -#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT__CI__VI 0x0000001c -#define VGT_DEBUG_REG2__ls_sh_id__SHIFT__CI__VI 0x0000001a -#define VGT_DEBUG_REG2__p0_dr__SHIFT__CI__VI 0x00000016 -#define VGT_DEBUG_REG2__p0_rtr__SHIFT__CI__VI 0x00000014 -#define VGT_DEBUG_REG2__p0_rts__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG2__p1_dr__SHIFT__CI__VI 0x00000017 -#define VGT_DEBUG_REG2__p1_rtr__SHIFT__CI__VI 0x00000015 -#define VGT_DEBUG_REG2__p1_rts__SHIFT__CI__VI 0x00000019 -#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG30__SPARE__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT__CI 0x00000018 -#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT__CI 0x00000003 -#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT__CI 0x0000001b -#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT__CI 0x0000001a -#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT__CI 0x00000019 -#define VGT_DEBUG_REG30__grpModBusy__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG30__hsInputFifoEmpty__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG30__hsInputFifoFull__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG30__hsTifFifoEmpty__SHIFT__SI 0x0000000d -#define VGT_DEBUG_REG30__hsTifFifoFull__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG30__hsVertFifoEmpty__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG30__hsVertFifoFull__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG30__hsWaveFifoEmpty__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG30__hsWaveFifoFull__SHIFT__SI 0x00000011 -#define VGT_DEBUG_REG30__hs_grp_busy__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG30__hs_noif_busy__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG30__hs_te11_tess_input_rts__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT__CI 0x00000013 -#define VGT_DEBUG_REG30__lsFwaveFlag__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG30__lsVertFifoEmpty__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG30__lsVertFifoFull__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG30__lsVertIfBusy_0__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG30__lsWaveFifoEmpty__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG30__lsWaveFifoFull__SHIFT__SI 0x0000000f -#define VGT_DEBUG_REG30__lsWaveIfBusy_0__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG30__lsWaveSendFlush__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG30__ls_sh_id__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG30__p0_dr__SHIFT__SI 0x00000016 -#define VGT_DEBUG_REG30__p0_rtr__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG30__p0_rts__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG30__p1_dr__SHIFT__SI 0x00000017 -#define VGT_DEBUG_REG30__p1_rtr__SHIFT__SI 0x00000015 -#define VGT_DEBUG_REG30__p1_rts__SHIFT__SI 0x00000019 -#define VGT_DEBUG_REG30__pipe0_dr__SHIFT__CI 0x00000000 -#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT__CI 0x00000004 -#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT__CI 0x00000001 -#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT__CI 0x00000005 -#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT__CI 0x00000006 -#define VGT_DEBUG_REG30__pipe2_dr__SHIFT__CI 0x00000002 -#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT__CI 0x00000007 -#define VGT_DEBUG_REG30__pipe4_dr__SHIFT__CI 0x0000001e -#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT__CI 0x0000001f -#define VGT_DEBUG_REG30__te11_hs_tess_input_rtr__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT__CI 0x00000010 -#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT__CI 0x00000014 -#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT__CI 0x0000001c -#define VGT_DEBUG_REG30__tfmmIsBusy__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT__CI 0x00000009 -#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT__CI 0x00000008 -#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT__CI 0x0000000a -#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT__CI 0x0000000b -#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT__CI 0x0000000c -#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT__CI 0x0000000d -#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT__CI 0x0000000e -#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT__CI 0x0000000f -#define VGT_DEBUG_REG31__hsWaveRelInd__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT__CI__VI 0x0000001f -#define VGT_DEBUG_REG31__lsPatchCnt__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG31__lsTgRelInd__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG31__lsWaveRelInd__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT__CI__VI 0x0000001e -#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT__CI__VI 0x00000016 -#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT__CI__VI 0x00000017 -#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT__CI__VI 0x00000014 -#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT__CI__VI 0x00000015 -#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT__CI__VI 0x00000019 -#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT__CI__VI 0x0000001c -#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT__CI__VI 0x0000001a -#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT__CI__VI 0x0000001d -#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT__CI__VI 0x0000001b -#define VGT_DEBUG_REG31__pipe0_dr__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT__CI__VI 0x00000003 -#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT__CI__VI 0x0000000d -#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT__CI__VI 0x00000007 -#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT__CI__VI 0x0000000f -#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT__CI__VI 0x00000006 -#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT__CI__VI 0x0000000e -#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT__CI__VI 0x00000009 -#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT__CI__VI 0x00000011 -#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT__CI__VI 0x0000000b -#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT__CI__VI 0x00000013 -#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT__CI__VI 0x0000000a -#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG32__SPARE__SHIFT__CI__VI 0x0000001c -#define VGT_DEBUG_REG32__SPARE__SHIFT__SI 0x0000001f -#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT__CI__VI 0x00000007 -#define VGT_DEBUG_REG32__fifos_rtr__SHIFT__CI__VI 0x0000001b -#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT__CI__VI 0x0000000a -#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT__CI__VI 0x00000009 -#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG32__hsCpCnt__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG32__hsFwaveFlag__SHIFT__SI 0x0000001e -#define VGT_DEBUG_REG32__hsPatchCnt__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG32__hsPrimId_15_0__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG32__hsWaveSendFlush__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT__CI__VI 0x00000019 -#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT__CI__VI 0x00000006 -#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT__CI__VI 0x0000000b -#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT__CI__VI 0x00000003 -#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT__CI__VI 0x0000001a -#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT__CI__VI 0x00000011 -#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT__CI__VI 0x00000014 -#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT__CI__VI 0x00000016 -#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT__CI__VI 0x00000015 -#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT__CI__VI 0x00000013 -#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT__CI__VI 0x00000017 -#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT__CI__VI 0x0000000f -#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT__CI__VI 0x0000000e -#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG33__SPARE1__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG33__SPARE2__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG33__SPARE3__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG33__SPARE4__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT__CI__VI 0x0000001f -#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT__CI__VI 0x0000001e -#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT__CI__VI 0x0000001d -#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT__CI__VI 0x00000013 -#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT__CI__VI 0x00000011 -#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT__CI__VI 0x0000000f -#define VGT_DEBUG_REG33__hsVertCreditCnt_0__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG33__hsWaveCreditCnt_0__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT__CI__VI 0x00000014 -#define VGT_DEBUG_REG33__lsVertCreditCnt_0__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG33__lsWaveCreditCnt_0__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG33__pipe1_dr__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG33__pipe2_dr__SHIFT__CI__VI 0x00000003 -#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT__CI__VI 0x00000007 -#define VGT_DEBUG_REG33__pipe3_dr__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT__CI__VI 0x00000009 -#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT__CI__VI 0x0000000b -#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT__CI__VI 0x00000006 -#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT__CI__VI 0x00000017 -#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT__CI__VI 0x0000000a -#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT__CI__VI 0x00000016 -#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT__CI__VI 0x0000000d -#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT__CI__VI 0x00000015 -#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT__CI__VI 0x0000001c -#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT__CI__VI 0x0000001a -#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT__CI__VI 0x0000000e -#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT__CI__VI 0x00000017 -#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT__CI__VI 0x00000016 -#define VGT_DEBUG_REG34__con_state_q__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG34__debug_BASE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG34__debug_SIZE__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT__CI__VI 0x00000014 -#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT__CI__VI 0x00000013 -#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT__CI__VI 0x00000011 -#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT__CI__VI 0x00000015 -#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT__CI__VI 0x0000000e -#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT__CI__VI 0x0000000f -#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT__CI__VI 0x00000009 -#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT__CI__VI 0x0000000b -#define VGT_DEBUG_REG34__pipe1_dr__SHIFT__CI__VI 0x0000000a -#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT__CI__VI 0x0000001e -#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT__CI__VI 0x0000001b -#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT__CI__VI 0x0000001c -#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT__CI__VI 0x00000019 -#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT__CI__VI 0x0000001a -#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT__CI__VI 0x0000001d -#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT__CI__VI 0x0000000d -#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT__CI__VI 0x00000006 -#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT__CI__VI 0x00000007 -#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG34__second_cycle_q__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT__CI__VI 0x0000001f -#define VGT_DEBUG_REG35__SPARE__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT__CI 0x0000001f -#define VGT_DEBUG_REG35__TF_addr__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT__CI 0x0000001e -#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT__CI 0x0000001d -#define VGT_DEBUG_REG35__debug_tfmmFifoEmpty__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG35__debug_tfmmFifoFull__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT__CI 0x00000012 -#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT__CI 0x0000001c -#define VGT_DEBUG_REG35__hs_pipe0_dr__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG35__hs_pipe0_rtr__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG35__hs_pipe1_rtr__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT__CI 0x0000000b -#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT__CI 0x00000013 -#define VGT_DEBUG_REG35__pipe0_dr__SHIFT__CI 0x00000000 -#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT__CI 0x00000002 -#define VGT_DEBUG_REG35__pipe1_dr__SHIFT__CI 0x00000001 -#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT__CI 0x00000003 -#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT__CI 0x0000001b -#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT__CI 0x0000000c -#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT__CI 0x00000006 -#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT__CI 0x00000014 -#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT__CI 0x00000007 -#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT__CI 0x00000008 -#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT__CI 0x00000009 -#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT__CI 0x00000004 -#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT__CI 0x00000005 -#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT__CI 0x0000000a -#define VGT_DEBUG_REG36__cm_state0__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG36__cm_state10__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG36__cm_state11__SHIFT__SI 0x00000016 -#define VGT_DEBUG_REG36__cm_state12__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG36__cm_state13__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG36__cm_state14__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG36__cm_state15__SHIFT__SI 0x0000001e -#define VGT_DEBUG_REG36__cm_state1__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG36__cm_state2__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG36__cm_state3__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG36__cm_state4__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG36__cm_state5__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG36__cm_state6__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG36__cm_state7__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG36__cm_state8__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG36__cm_state9__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG37__dynamic_hs_p0_q__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG37__event_or_null_p1__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG37__first_data_chunk_invalid_p0_q__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG37__first_data_ret_of_req_p0_q__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG37__first_fetch_of_tg_p0_q__SHIFT__SI 0x00000019 -#define VGT_DEBUG_REG37__last_tf_of_tg__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG37__pipe0_dr__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG37__pipe0_rtr__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG37__pipe0_tf_dr__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG37__pipe1_rtr__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG37__pipe1_tf_rtr__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG37__pipe2_dr__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG37__pipe2_rtr__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG37__pipe4_dr__SHIFT__SI 0x0000001e -#define VGT_DEBUG_REG37__pipe4_rtr__SHIFT__SI 0x0000001f -#define VGT_DEBUG_REG37__tf_fetch_state_q__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG37__tf_pointer_p0_q__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG37__tf_xfer_count_p2_q__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG37__ttp_patch_fifo_empty__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG37__ttp_patch_fifo_full__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG37__ttp_tf0_fifo_empty__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG37__ttp_tf1_fifo_empty__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG37__ttp_tf2_fifo_empty__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG37__ttp_tf3_fifo_empty__SHIFT__SI 0x0000000d -#define VGT_DEBUG_REG37__ttp_tf4_fifo_empty__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG37__ttp_tf5_fifo_empty__SHIFT__SI 0x0000000f -#define VGT_DEBUG_REG38__inner_ring_done_q__SHIFT__SI 0x0000001f -#define VGT_DEBUG_REG38__outer_ring_done_q__SHIFT__SI 0x0000001e -#define VGT_DEBUG_REG38__pg_con_inner_point1_rts__SHIFT__SI 0x00000016 -#define VGT_DEBUG_REG38__pg_con_inner_point2_rts__SHIFT__SI 0x00000017 -#define VGT_DEBUG_REG38__pg_con_outer_point1_rts__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG38__pg_con_outer_point2_rts__SHIFT__SI 0x00000015 -#define VGT_DEBUG_REG38__pg_edge_fifo_empty__SHIFT__SI 0x00000019 -#define VGT_DEBUG_REG38__pg_edge_fifo_full__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG38__pg_inner3_perp_fifo_empty__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG38__pg_inner_perp_fifo_full__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG38__pg_patch_fifo_empty__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG38__pg_patch_fifo_full__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG38__pipe0_dr__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG38__pipe0_rtr__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG38__pipe1_inner_dr__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG38__pipe1_outer_dr__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG38__pipe2_inner_dr__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG38__pipe2_inner_rtr__SHIFT__SI 0x0000000d -#define VGT_DEBUG_REG38__pipe2_outer_dr__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG38__pipe2_outer_rtr__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG38__pipe3_inner_dr__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG38__pipe3_inner_rtr__SHIFT__SI 0x0000000f -#define VGT_DEBUG_REG38__pipe3_outer_dr__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG38__pipe3_outer_rtr__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG38__pipe4_inner_dr__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG38__pipe4_inner_rtr__SHIFT__SI 0x00000011 -#define VGT_DEBUG_REG38__pipe4_outer_dr__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG38__pipe4_outer_rtr__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG38__pipe5_inner_dr__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG38__pipe5_inner_rtr__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG38__pipe5_outer_dr__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG38__pipe5_outer_rtr__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG39__SPARE__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG39__event_flag_p5_q__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG39__event_null_special_p0_q__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG39__fifos_rtr__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG39__first_point_of_edge_p5_q__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG39__first_point_of_patch_p5_q__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG39__first_ring_of_patch__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG39__inner2_fifos_rtr__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG39__inner_fifos_rtr__SHIFT__SI 0x00000019 -#define VGT_DEBUG_REG39__last_edge_of_inner_ring__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG39__last_edge_of_outer_ring__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG39__last_patch_of_tg_p0_q__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG39__last_patch_of_tg_p5_q__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG39__last_point_of_inner_edge__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG39__last_point_of_outer_edge__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG39__last_ring_of_patch__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG39__outer_fifos_rtr__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG39__pg_edge_fifo2_full__SHIFT__SI 0x00000011 -#define VGT_DEBUG_REG39__pg_edge_fifo3_full__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG39__pg_inner2_point_fifo_full__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG39__pg_inner3_point_fifo_full__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG39__pg_inner_point_fifo_full__SHIFT__SI 0x00000016 -#define VGT_DEBUG_REG39__pg_outer2_point_fifo_full__SHIFT__SI 0x00000015 -#define VGT_DEBUG_REG39__pg_outer3_point_fifo_full__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG39__pg_outer_point_fifo_full__SHIFT__SI 0x00000017 -#define VGT_DEBUG_REG39__pipe5_inner2_rtr__SHIFT__SI 0x0000000f -#define VGT_DEBUG_REG39__pipe5_inner3_rtr__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG39__tess_topology_p5_q__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG3__SPARE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT__CI__VI 0x0000001a -#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT__CI__VI 0x00000012 -#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT__CI__VI 0x0000000c -#define VGT_DEBUG_REG40__con_prim_fifo_empty__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG40__con_prim_fifo_full__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG40__con_ring1_busy__SHIFT__SI 0x0000001f -#define VGT_DEBUG_REG40__con_ring2_busy__SHIFT__SI 0x0000001e -#define VGT_DEBUG_REG40__con_ring3_busy__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG40__con_vert_fifo_empty__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG40__con_vert_fifo_full__SHIFT__SI 0x00000011 -#define VGT_DEBUG_REG40__first_prim_of_patch_q__SHIFT__SI 0x0000000f -#define VGT_DEBUG_REG40__last_patch_of_tg_p0_q__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG40__pipe0_patch_dr__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG40__pipe0_patch_rtr__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG40__pipe1_dr__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG40__pipe1_patch_rtr__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG40__pipe2_dr__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG40__pipe2_rtr__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG40__pipe3_dr__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG40__pipe3_rtr__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG40__ring1_in_sync_q__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG40__ring1_pipe1_dr__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG40__ring1_valid_p2__SHIFT__SI 0x00000017 -#define VGT_DEBUG_REG40__ring2_in_sync_q__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG40__ring2_pipe1_dr__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG40__ring2_valid_p2__SHIFT__SI 0x00000016 -#define VGT_DEBUG_REG40__ring3_in_sync_q__SHIFT__SI 0x0000000d -#define VGT_DEBUG_REG40__ring3_pipe1_dr__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG40__ring3_valid_p2__SHIFT__SI 0x00000015 -#define VGT_DEBUG_REG40__te11_out_vert_gs_en__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG40__tess_topology_p0_q__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG40__tess_type_p0_q__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG40__tm_te11_event_rtr__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG41__advance_inner_point_p1__SHIFT__SI 0x00000017 -#define VGT_DEBUG_REG41__advance_outer_point_p1__SHIFT__SI 0x00000016 -#define VGT_DEBUG_REG41__con_state_q__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG41__first_ring_of_patch_p0_q__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG41__last_edge_of_outer_ring_p0_q__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG41__last_point_of_inner_ring_p1__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG41__last_point_of_outer_ring_p1__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG41__last_ring_of_patch_p0_q__SHIFT__SI 0x00000011 -#define VGT_DEBUG_REG41__next_ring_is_rect_p0_q__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG41__outer_edge_tf_eq_one_p0_q__SHIFT__SI 0x00000015 -#define VGT_DEBUG_REG41__outer_parity_p0_q__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG41__parallel_parity_p0_q__SHIFT__SI 0x0000000f -#define VGT_DEBUG_REG41__pipe0_edge_dr__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG41__pipe0_edge_rtr__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG41__pipe0_patch_dr__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG41__pipe0_patch_rtr__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG41__pipe1_dr__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG41__pipe1_edge_rtr__SHIFT__SI 0x0000001e -#define VGT_DEBUG_REG41__pipe1_inner1_rtr__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG41__pipe1_inner2_rtr__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG41__pipe1_outer1_rtr__SHIFT__SI 0x00000019 -#define VGT_DEBUG_REG41__pipe1_outer2_rtr__SHIFT__SI 0x0000001a -#define VGT_DEBUG_REG41__pipe1_patch_rtr__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG41__pipe1_rtr__SHIFT__SI 0x0000000d -#define VGT_DEBUG_REG41__process_tri_1st_2nd_half_p0_q__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG41__process_tri_center_poly_p0_q__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG41__process_tri_middle_p0_q__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG41__second_cycle_q__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG41__use_stored_inner_q_ring1__SHIFT__SI 0x0000001f -#define VGT_DEBUG_REG42__TC_VGT_rdret_data_in__SHIFT__SI 0x0000001f -#define VGT_DEBUG_REG42__VGT_TC_rdnfo_stall_out__SHIFT__SI 0x0000001e -#define VGT_DEBUG_REG42__VGT_TC_rdreq_send_out__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG42__event_flag_p1_q__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG42__first_req_of_tg_p1_q__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG42__last_req_of_tg_p2__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG42__null_flag_p1_q__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG42__pipe0_dr__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG42__pipe0_rtr__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG42__pipe1_dr__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG42__pipe1_rtr__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG42__second_tf_ret_data_q__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG42__spi_vgt_hs_done_cnt_q__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG42__tf_data_fifo_busy_q__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG42__tf_data_fifo_cnt_q__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG42__tf_data_fifo_rtr_q__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG42__tf_skid_fifo_empty__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG42__tf_skid_fifo_full__SHIFT__SI 0x00000009 -#define VGT_DEBUG_REG42__tfreq_tg_fifo_empty__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG42__tfreq_tg_fifo_full__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG42__vgt_tc_rdreq_rtr_q__SHIFT__SI 0x0000000a -#define VGT_DEBUG_REG4__SPARE__SHIFT__CI__VI 0x0000001f -#define VGT_DEBUG_REG4__SPARE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG4__hsCpCnt__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT__CI__VI 0x0000001e -#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT__CI__VI 0x0000001d -#define VGT_DEBUG_REG5__SPARE1__SHIFT__CI__VI 0x00000018 -#define VGT_DEBUG_REG5__SPARE2__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG5__SPARE3__SHIFT__CI__VI 0x00000008 -#define VGT_DEBUG_REG5__SPARE4__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG5__SPARE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT__CI__VI 0x0000000b -#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT__CI__VI 0x00000003 -#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT__CI__VI 0x0000001b -#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT__CI__VI 0x00000013 -#define VGT_DEBUG_REG6__SPARE__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG6__debug_BASE__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG6__debug_SIZE__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG7__SPARE__SHIFT__CI__VI 0x00000005 -#define VGT_DEBUG_REG7__TF_addr__SHIFT__CI__VI 0x00000010 -#define VGT_DEBUG_REG7__components_valid_r0_q__SHIFT__SI 0x0000001d -#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG7__eject_vtx_vect_r1_d__SHIFT__SI 0x00000017 -#define VGT_DEBUG_REG7__eop_r0_q__SHIFT__SI 0x00000016 -#define VGT_DEBUG_REG7__grp_vr_valid__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG7__gs_scenario_a_r0_q__SHIFT__SI 0x0000001b -#define VGT_DEBUG_REG7__gs_scenario_b_r0_q__SHIFT__SI 0x0000001c -#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT__CI__VI 0x00000002 -#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT__CI__VI 0x00000003 -#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT__CI__VI 0x00000004 -#define VGT_DEBUG_REG7__indices_to_send_q__SHIFT__SI 0x00000008 -#define VGT_DEBUG_REG7__indx0_hit_d__SHIFT__SI 0x00000012 -#define VGT_DEBUG_REG7__indx0_new_d__SHIFT__SI 0x0000000d -#define VGT_DEBUG_REG7__indx1_hit_d__SHIFT__SI 0x00000011 -#define VGT_DEBUG_REG7__indx1_new_d__SHIFT__SI 0x0000000e -#define VGT_DEBUG_REG7__indx2_hit_d__SHIFT__SI 0x00000010 -#define VGT_DEBUG_REG7__indx2_new_d__SHIFT__SI 0x0000000f -#define VGT_DEBUG_REG7__last_group_of_instance_r0_q__SHIFT__SI 0x00000014 -#define VGT_DEBUG_REG7__last_indx_of_prim__SHIFT__SI 0x0000000c -#define VGT_DEBUG_REG7__null_primitive_r0_q__SHIFT__SI 0x00000015 -#define VGT_DEBUG_REG7__out_vr_indx_read__SHIFT__SI 0x00000006 -#define VGT_DEBUG_REG7__out_vr_prim_read__SHIFT__SI 0x00000007 -#define VGT_DEBUG_REG7__pipe0_dr__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG7__pipe0_rtr__SHIFT__SI 0x00000004 -#define VGT_DEBUG_REG7__pipe1_dr__SHIFT__SI 0x00000002 -#define VGT_DEBUG_REG7__pipe1_rtr__SHIFT__SI 0x00000005 -#define VGT_DEBUG_REG7__st_vertex_reuse_off_r0_q__SHIFT__SI 0x00000013 -#define VGT_DEBUG_REG7__sub_prim_type_r0_q__SHIFT__SI 0x00000018 -#define VGT_DEBUG_REG7__valid_indices__SHIFT__SI 0x0000000b -#define VGT_DEBUG_REG7__vr_grp_read__SHIFT__SI 0x00000003 -#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0x0000000e -#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x00000019 -#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0x0000000f -#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x00000011 -#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x00000018 -#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x00000012 -#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0x0000000a -#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x00000002 -#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x00000017 -#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG8__rcm_busy__SHIFT__SI 0x00000000 -#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT__CI__VI 0x00000000 -#define VGT_DEBUG_REG8__rcm_noif_busy__SHIFT__SI 0x00000001 -#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT__CI__VI 0x00000001 -#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x00000003 -#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x0000001c -#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x0000001d -#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x0000001e -#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x0000001f -#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x00000015 -#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x00000010 -#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x00000014 -#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x00000008 -#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x0000001e -#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x00000004 -#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x00000005 -#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x00000006 -#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x00000019 -#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x00000007 -#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x00000003 -#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x0000001a -#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0x0000000a -#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x00000017 -#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x0000001f -#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x00000009 -#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x00000008 -#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x00000002 -#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x0000001d -#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x0000001c -#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x00000000 -#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT__CI__VI 0x00000011 -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT__CI__VI 0x00000000 -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT__CI__VI 0x00000014 -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x00000000 -#define VGT_DMA_INDEX_TYPE__ATC__SHIFT__CI 0x00000008 -#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT__CI__VI 0x00000004 -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 -#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT__CI__VI 0x00000009 -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT__CI__VI 0x00000006 -#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT__CI__VI 0x0000000a -#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x00000002 -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT__CI__VI 0x00000008 -#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x00000000 -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT__CI__VI 0x00000000 -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x00000000 -#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x00000000 -#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x00000002 -#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x00000005 -#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000000 -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x00000004 -#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x00000006 -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x00000000 -#define VGT_ENHANCE__MISC__SHIFT 0x00000000 -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 -#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 -#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x00000000 -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x00000000 -#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x00000012 -#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x0000001b -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x00000008 -#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x00000007 -#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT__SI__CI 0x00000016 -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x00000000 -#define VGT_GROUP_DECR__DECR__SHIFT 0x00000000 -#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x00000000 -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x00000010 -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x00000000 -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0x0000000e -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0x0000000f -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x00000003 -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x00000000 -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x00000001 -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x00000002 -#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x00000010 -#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x00000008 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x00000018 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x00000000 -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x00000008 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x00000010 -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x00000003 -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x00000000 -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x00000001 -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x00000002 -#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x00000010 -#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x00000008 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x00000018 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x00000000 -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x00000008 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x00000010 -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 -#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x00000000 -#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x00000000 -#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x00000000 -#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 -#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x00000002 -#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x00000000 -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x00000000 -#define VGT_GS_MODE__COMPUTE_MODE__SHIFT__SI__CI 0x0000000e -#define VGT_GS_MODE__CUT_MODE__SHIFT 0x00000004 -#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT__SI__CI 0x00000010 -#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0x0000000d -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x00000013 -#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT__SI__CI 0x0000000f -#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0x0000000b -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x00000014 -#define VGT_GS_MODE__MODE__SHIFT 0x00000000 -#define VGT_GS_MODE__ONCHIP__SHIFT__CI__VI 0x00000015 -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x00000011 -#define VGT_GS_MODE__RESERVED_0__SHIFT 0x00000003 -#define VGT_GS_MODE__RESERVED_1__SHIFT 0x00000006 -#define VGT_GS_MODE__RESERVED_2__SHIFT 0x0000000c -#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x00000012 -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT__CI__VI 0x00000000 -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT__CI__VI 0x0000000b -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x00000008 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x00000010 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x00000016 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x00000000 -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x0000001f -#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x00000000 -#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x00000000 -#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x00000000 -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x00000000 -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x00000000 -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x00000000 -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 -#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x00000000 -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x00000000 -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x00000000 -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x00000000 -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x00000000 -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT__CI__VI 0x00000009 -#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 -#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 -#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x00000000 -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x00000000 -#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 -#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x00000008 -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0x0000000e -#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x00000000 -#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x00000000 -#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x00000000 -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 -#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x00000000 -#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x00000000 -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT__CI__VI 0x0000001c -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT__CI__VI 0x00000018 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT__CI__VI 0x00000000 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT__CI__VI 0x0000000a -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT__CI__VI 0x00000014 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT__CI__VI 0x00000018 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT__CI__VI 0x0000000a -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x00000000 -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x00000001 -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x00000000 -#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x00000000 -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x00000000 -#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT__CI__VI 0x00000000 -#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT__CI__VI 0x00000001 -#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT__CI__VI 0x00000002 -#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x00000000 -#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x00000008 -#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x00000003 -#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x00000005 -#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x00000002 -#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x00000000 -#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x00000006 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x00000004 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x00000008 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0x0000000c -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x00000008 -#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x00000004 -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x00000000 -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x00000001 -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x00000002 -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x00000003 -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x0000001f -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT__CI__VI 0x00000008 -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT__CI__VI 0x0000000b -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT__CI__VI 0x0000000e -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT__CI__VI 0x00000011 -#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT__CI__VI 0x00000000 -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x00000000 -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x00000000 -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x00000000 -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x00000000 -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x00000000 -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x00000000 -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x00000000 -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x00000007 -#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x00000000 -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x00000001 -#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x00000000 -#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x00000009 -#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0x0000000e -#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0x0000000a -#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x00000002 -#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT__CI__VI 0x0000000f -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x00000008 -#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x00000005 -#define VGT_TF_PARAM__TYPE__SHIFT 0x00000000 -#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x00000000 -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT__CI__VI 0x00000000 -#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x00000000 -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 -#define VID_BUFFER_CONTROL__CAP0_ANC_VBI_QUAD_BUF__SHIFT__SI 0x00000011 -#define VID_BUFFER_CONTROL__CAP0_BUFFER_EMPTY__SHIFT__SI 0x00000018 -#define VID_BUFFER_CONTROL__CAP0_BUFFER_WATER_MARK__SHIFT__SI 0x00000000 -#define VID_BUFFER_CONTROL__CAP_SWAP__SHIFT__SI 0x00000015 -#define VID_BUFFER_CONTROL__CAP_URGENT_EN__SHIFT__SI 0x0000001f -#define VID_BUFFER_CONTROL__FULL_BUFFER_EN__SHIFT__SI 0x00000010 -#define VID_BUFFER_CONTROL__VID_BUFFER_RESET__SHIFT__SI 0x00000014 -#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT__SI 0x00000000 -#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT__SI 0x00000010 -#define VIEWPORT_START__VIEWPORT_X_START__SHIFT__SI 0x00000010 -#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT__SI 0x00000000 -#define VIPH_CH0_ABCNT__VIPH_CH0_ACNT__SHIFT__SI 0x00000000 -#define VIPH_CH0_ADDR__VIPH_CH0_AD__SHIFT__SI 0x00000000 -#define VIPH_CH0_DATA__VIPH_CH0_DT__SHIFT__SI 0x00000000 -#define VIPH_CH0_SBCNT__VIPH_CH0_SCNT__SHIFT__SI 0x00000000 -#define VIPH_CH1_ABCNT__VIPH_CH1_ACNT__SHIFT__SI 0x00000000 -#define VIPH_CH1_ADDR__VIPH_CH1_AD__SHIFT__SI 0x00000000 -#define VIPH_CH1_DATA__VIPH_CH1_DT__SHIFT__SI 0x00000000 -#define VIPH_CH1_SBCNT__VIPH_CH1_SCNT__SHIFT__SI 0x00000000 -#define VIPH_CH2_ABCNT__VIPH_CH2_ACNT__SHIFT__SI 0x00000000 -#define VIPH_CH2_ADDR__VIPH_CH2_AD__SHIFT__SI 0x00000000 -#define VIPH_CH2_DATA__VIPH_CH2_DT__SHIFT__SI 0x00000000 -#define VIPH_CH2_SBCNT__VIPH_CH2_SCNT__SHIFT__SI 0x00000000 -#define VIPH_CH3_ABCNT__VIPH_CH3_ACNT__SHIFT__SI 0x00000000 -#define VIPH_CH3_ADDR__VIPH_CH3_AD__SHIFT__SI 0x00000000 -#define VIPH_CH3_DATA__VIPH_CH3_DT__SHIFT__SI 0x00000000 -#define VIPH_CH3_SBCNT__VIPH_CH3_SCNT__SHIFT__SI 0x00000000 -#define VIPH_CONTROL__VIPH_CLK_SEL__SHIFT__SI 0x00000000 -#define VIPH_CONTROL__VIPH_DMA_MODE__SHIFT__SI 0x00000014 -#define VIPH_CONTROL__VIPH_DV0_WID__SHIFT__SI 0x00000018 -#define VIPH_CONTROL__VIPH_DV1_WID__SHIFT__SI 0x00000019 -#define VIPH_CONTROL__VIPH_DV2_WID__SHIFT__SI 0x0000001a -#define VIPH_CONTROL__VIPH_DV3_WID__SHIFT__SI 0x0000001b -#define VIPH_CONTROL__VIPH_EN__SHIFT__SI 0x00000015 -#define VIPH_CONTROL__VIPH_INT_SEL__SHIFT__SI 0x0000001e -#define VIPH_CONTROL__VIPH_MAX_WAIT__SHIFT__SI 0x00000010 -#define VIPH_CONTROL__VIPH_PWR_DOWN_AK__SHIFT__SI 0x0000001c -#define VIPH_CONTROL__VIPH_PWR_DOWN__SHIFT__SI 0x0000001c -#define VIPH_CONTROL__VIPH_REG_RDY__SHIFT__SI 0x0000000d -#define VIPH_CONTROL__VIPH_VIPCLK_DIS__SHIFT__SI 0x0000001d -#define VIPH_CONTROL__VIP_DEVICE_STRAP_DIS__SHIFT__SI 0x0000001f -#define VIPH_CONTROL__VIP_DEVICE__SHIFT__SI 0x00000017 -#define VIPH_DMA_CHUNK__VIPH_CH0_ABORT__SHIFT__SI 0x00000010 -#define VIPH_DMA_CHUNK__VIPH_CH0_CHUNK__SHIFT__SI 0x00000000 -#define VIPH_DMA_CHUNK__VIPH_CH1_ABORT__SHIFT__SI 0x00000011 -#define VIPH_DMA_CHUNK__VIPH_CH1_CHUNK__SHIFT__SI 0x00000004 -#define VIPH_DMA_CHUNK__VIPH_CH2_ABORT__SHIFT__SI 0x00000012 -#define VIPH_DMA_CHUNK__VIPH_CH2_CHUNK__SHIFT__SI 0x00000006 -#define VIPH_DMA_CHUNK__VIPH_CH3_ABORT__SHIFT__SI 0x00000013 -#define VIPH_DMA_CHUNK__VIPH_CH3_CHUNK__SHIFT__SI 0x00000008 -#define VIPH_DV_INT__VIPH_DV0_AK__SHIFT__SI 0x00000004 -#define VIPH_DV_INT__VIPH_DV0_INT_EN__SHIFT__SI 0x00000000 -#define VIPH_DV_INT__VIPH_DV0_INT__SHIFT__SI 0x00000004 -#define VIPH_DV_INT__VIPH_DV1_AK__SHIFT__SI 0x00000005 -#define VIPH_DV_INT__VIPH_DV1_INT_EN__SHIFT__SI 0x00000001 -#define VIPH_DV_INT__VIPH_DV1_INT__SHIFT__SI 0x00000005 -#define VIPH_DV_INT__VIPH_DV2_AK__SHIFT__SI 0x00000006 -#define VIPH_DV_INT__VIPH_DV2_INT_EN__SHIFT__SI 0x00000002 -#define VIPH_DV_INT__VIPH_DV2_INT__SHIFT__SI 0x00000006 -#define VIPH_DV_INT__VIPH_DV3_AK__SHIFT__SI 0x00000007 -#define VIPH_DV_INT__VIPH_DV3_INT_EN__SHIFT__SI 0x00000003 -#define VIPH_DV_INT__VIPH_DV3_INT__SHIFT__SI 0x00000007 -#define VIPH_DV_LAT__VIPH_DV0_LAT__SHIFT__SI 0x00000010 -#define VIPH_DV_LAT__VIPH_DV1_LAT__SHIFT__SI 0x00000014 -#define VIPH_DV_LAT__VIPH_DV2_LAT__SHIFT__SI 0x00000018 -#define VIPH_DV_LAT__VIPH_DV3_LAT__SHIFT__SI 0x0000001c -#define VIPH_DV_LAT__VIPH_TIME_UNIT__SHIFT__SI 0x00000000 -#define VIPH_READ_URG__VIPH_CH0_RURG__SHIFT__SI 0x00000000 -#define VIPH_READ_URG__VIPH_CH1_RURG__SHIFT__SI 0x00000008 -#define VIPH_READ_URG__VIPH_CH2_RURG__SHIFT__SI 0x00000010 -#define VIPH_READ_URG__VIPH_CH3_RURG__SHIFT__SI 0x00000018 -#define VIPH_REG_ADDR__VIPH_REG_AD__SHIFT__SI 0x00000000 -#define VIPH_REG_DATA__VIPH_REG_DT_R__SHIFT__SI 0x00000000 -#define VIPH_REG_DATA__VIPH_REG_DT_W__SHIFT__SI 0x00000000 -#define VIPH_TIMEOUT_STAT__VIPH_AUTO_INT_AK__SHIFT__SI 0x00000005 -#define VIPH_TIMEOUT_STAT__VIPH_AUTO_INT_MASK__SHIFT__SI 0x0000000d -#define VIPH_TIMEOUT_STAT__VIPH_AUTO_INT_STAT__SHIFT__SI 0x00000005 -#define VIPH_TIMEOUT_STAT__VIPH_DV0_INT_MASK__SHIFT__SI 0x00000010 -#define VIPH_TIMEOUT_STAT__VIPH_DV1_INT_MASK__SHIFT__SI 0x00000011 -#define VIPH_TIMEOUT_STAT__VIPH_DV2_INT_MASK__SHIFT__SI 0x00000012 -#define VIPH_TIMEOUT_STAT__VIPH_DV3_INT_MASK__SHIFT__SI 0x00000013 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_AK__SHIFT__SI 0x00000000 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_MASK__SHIFT__SI 0x00000008 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_STAT__SHIFT__SI 0x00000000 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_AK__SHIFT__SI 0x00000001 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_MASK__SHIFT__SI 0x00000009 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_STAT__SHIFT__SI 0x00000001 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_AK__SHIFT__SI 0x00000002 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_MASK__SHIFT__SI 0x0000000a -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_STAT__SHIFT__SI 0x00000002 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_AK__SHIFT__SI 0x00000003 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_MASK__SHIFT__SI 0x0000000b -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_STAT__SHIFT__SI 0x00000003 -#define VIPH_TIMEOUT_STAT__VIPH_INTPIN_EN__SHIFT__SI 0x00000014 -#define VIPH_TIMEOUT_STAT__VIPH_INTPIN_INT__SHIFT__SI 0x00000015 -#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS__SHIFT__SI 0x00000018 -#define VIPH_TIMEOUT_STAT__VIPH_REG_AK__SHIFT__SI 0x00000004 -#define VIPH_TIMEOUT_STAT__VIPH_REG_MASK__SHIFT__SI 0x0000000c -#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT__SHIFT__SI 0x00000004 -#define VIPH_TIMEOUT_STAT__VIP_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT__SI 0x0000001f -#define VIPH_WRCOMB_STALL__VIPH_WRCOMB_STALL_AK__SHIFT__SI 0x00000000 -#define VIPH_WRCOMB_STALL__VIPH_WRCOMB_STALL__SHIFT__SI 0x00000000 -#define VIPH_WRCOMB_STAT0__THR_CNT__SHIFT__SI 0x00000000 -#define VIPH_WRCOMB_STAT0__TOUT_CNT__SHIFT__SI 0x00000010 -#define VIPH_WRCOMB_STAT1__CHS_CNT__SHIFT__SI 0x00000010 -#define VIPH_WRCOMB_STAT1__DONE_CNT__SHIFT__SI 0x00000000 -#define VIPPAD_A__VIPPAD_A_DVALID__SHIFT__SI 0x00000011 -#define VIPPAD_A__VIPPAD_A_PSYNC__SHIFT__SI 0x00000012 -#define VIPPAD_A__VIPPAD_A_SCL__SHIFT__SI 0x00000000 -#define VIPPAD_A__VIPPAD_A_SDA__SHIFT__SI 0x00000001 -#define VIPPAD_A__VIPPAD_A_VHAD__SHIFT__SI 0x00000002 -#define VIPPAD_A__VIPPAD_A_VID__SHIFT__SI 0x00000008 -#define VIPPAD_A__VIPPAD_A_VIPCLK__SHIFT__SI 0x00000005 -#define VIPPAD_A__VIPPAD_A_VPCLK0__SHIFT__SI 0x00000010 -#define VIPPAD_A__VIPPAD_A_VPHCTL__SHIFT__SI 0x00000004 -#define VIPPAD_EN__VIPPAD_EN_DVALID__SHIFT__SI 0x00000011 -#define VIPPAD_EN__VIPPAD_EN_PSYNC__SHIFT__SI 0x00000012 -#define VIPPAD_EN__VIPPAD_EN_SCL__SHIFT__SI 0x00000000 -#define VIPPAD_EN__VIPPAD_EN_SDA__SHIFT__SI 0x00000001 -#define VIPPAD_EN__VIPPAD_EN_VHAD__SHIFT__SI 0x00000002 -#define VIPPAD_EN__VIPPAD_EN_VID__SHIFT__SI 0x00000008 -#define VIPPAD_EN__VIPPAD_EN_VIPCLK__SHIFT__SI 0x00000005 -#define VIPPAD_EN__VIPPAD_EN_VPCLK0__SHIFT__SI 0x00000010 -#define VIPPAD_EN__VIPPAD_EN_VPHCTL__SHIFT__SI 0x00000004 -#define VIPPAD_MASK__VIPPAD_MASK_DVALID__SHIFT__SI 0x00000011 -#define VIPPAD_MASK__VIPPAD_MASK_PSYNC__SHIFT__SI 0x00000012 -#define VIPPAD_MASK__VIPPAD_MASK_SCL__SHIFT__SI 0x00000000 -#define VIPPAD_MASK__VIPPAD_MASK_SDA__SHIFT__SI 0x00000001 -#define VIPPAD_MASK__VIPPAD_MASK_VHAD__SHIFT__SI 0x00000002 -#define VIPPAD_MASK__VIPPAD_MASK_VID__SHIFT__SI 0x00000008 -#define VIPPAD_MASK__VIPPAD_MASK_VIPCLK__SHIFT__SI 0x00000005 -#define VIPPAD_MASK__VIPPAD_MASK_VPCLK0__SHIFT__SI 0x00000010 -#define VIPPAD_MASK__VIPPAD_MASK_VPHCTL__SHIFT__SI 0x00000004 -#define VIPPAD_PD_DIS__VIPPAD_DVALID_PD_DIS__SHIFT__SI 0x00000011 -#define VIPPAD_PD_DIS__VIPPAD_PSYNC_PD_DIS__SHIFT__SI 0x00000012 -#define VIPPAD_PD_DIS__VIPPAD_SCL_PD_DIS__SHIFT__SI 0x00000000 -#define VIPPAD_PD_DIS__VIPPAD_SDA_PD_DIS__SHIFT__SI 0x00000001 -#define VIPPAD_PD_DIS__VIPPAD_VHAD_PD_DIS__SHIFT__SI 0x00000002 -#define VIPPAD_PD_DIS__VIPPAD_VID_PD_DIS__SHIFT__SI 0x00000008 -#define VIPPAD_PD_DIS__VIPPAD_VIPCLK_PD_DIS__SHIFT__SI 0x00000005 -#define VIPPAD_PD_DIS__VIPPAD_VPCLK0_PD_DIS__SHIFT__SI 0x00000010 -#define VIPPAD_PD_DIS__VIPPAD_VPHCTL_PD_DIS__SHIFT__SI 0x00000004 -#define VIPPAD_RECV__VIPPAD_DVALID_RECV__SHIFT__SI 0x00000011 -#define VIPPAD_RECV__VIPPAD_PSYNC_RECV__SHIFT__SI 0x00000012 -#define VIPPAD_RECV__VIPPAD_SCL_RECV__SHIFT__SI 0x00000000 -#define VIPPAD_RECV__VIPPAD_SDA_RECV__SHIFT__SI 0x00000001 -#define VIPPAD_RECV__VIPPAD_VHAD_RECV__SHIFT__SI 0x00000002 -#define VIPPAD_RECV__VIPPAD_VID_RECV__SHIFT__SI 0x00000008 -#define VIPPAD_RECV__VIPPAD_VIPCLK_RECV__SHIFT__SI 0x00000005 -#define VIPPAD_RECV__VIPPAD_VPCLK0_RECV__SHIFT__SI 0x00000010 -#define VIPPAD_RECV__VIPPAD_VPHCTL_RECV__SHIFT__SI 0x00000004 -#define VIPPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT__SI 0x00000000 -#define VIPPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT__SI 0x00000004 -#define VIPPAD_STRENGTH__VIDCAP_STRENGTH_SN__SHIFT__SI 0x00000018 -#define VIPPAD_STRENGTH__VIDCAP_STRENGTH_SP__SHIFT__SI 0x0000001c -#define VIPPAD_STRENGTH__VIPHCLK_STRENGTH_SN__SHIFT__SI 0x00000010 -#define VIPPAD_STRENGTH__VIPHCLK_STRENGTH_SP__SHIFT__SI 0x00000014 -#define VIPPAD_STRENGTH__VIPHDAT_STRENGTH_SN__SHIFT__SI 0x00000008 -#define VIPPAD_STRENGTH__VIPHDAT_STRENGTH_SP__SHIFT__SI 0x0000000c -#define VIPPAD_Y__VIPPAD_Y_DVALID__SHIFT__SI 0x00000011 -#define VIPPAD_Y__VIPPAD_Y_PSYNC__SHIFT__SI 0x00000012 -#define VIPPAD_Y__VIPPAD_Y_SCL__SHIFT__SI 0x00000000 -#define VIPPAD_Y__VIPPAD_Y_SDA__SHIFT__SI 0x00000001 -#define VIPPAD_Y__VIPPAD_Y_VHAD__SHIFT__SI 0x00000002 -#define VIPPAD_Y__VIPPAD_Y_VID__SHIFT__SI 0x00000008 -#define VIPPAD_Y__VIPPAD_Y_VIPCLK__SHIFT__SI 0x00000005 -#define VIPPAD_Y__VIPPAD_Y_VPCLK0__SHIFT__SI 0x00000010 -#define VIPPAD_Y__VIPPAD_Y_VPHCTL__SHIFT__SI 0x00000004 -#define VIP_DCCIF_CNTL__VIP_DCCIF_ALIGN64BYTE__SHIFT__SI 0x00000008 -#define VIP_DCCIF_CNTL__VIP_DCCIF_TIMEOUT__SHIFT__SI 0x00000000 -#define VIP_DCCIF_CNTL__VIP_DCCIF_W256ONLY__SHIFT__SI 0x0000000c -#define VIP_HW_DEBUG__VIPDMA_MH_ACK_REQ_AK__SHIFT__SI 0x00000005 -#define VIP_HW_DEBUG__VIPDMA_MH_ACK_REQ_EN__SHIFT__SI 0x00000003 -#define VIP_HW_DEBUG__VIPDMA_MH_ACK_REQ_STATUS__SHIFT__SI 0x00000004 -#define VIP_HW_DEBUG__VIP_HW_0_DEBUG__SHIFT__SI 0x00000000 -#define VIP_HW_DEBUG__VIP_HW_1_DEBUG__SHIFT__SI 0x00000001 -#define VIP_HW_DEBUG__VIP_HW_2_DEBUG__SHIFT__SI 0x00000002 -#define VIP_HW_DEBUG__VIP_HW_6_DEBUG__SHIFT__SI 0x00000006 -#define VIP_HW_DEBUG__VIP_HW_7_DEBUG__SHIFT__SI 0x00000007 -#define VIP_HW_DEBUG__VIP_HW_8_DEBUG__SHIFT__SI 0x00000008 -#define VIP_HW_DEBUG__VIP_HW_9_DEBUG__SHIFT__SI 0x00000009 -#define VIP_HW_DEBUG__VIP_HW_A_DEBUG__SHIFT__SI 0x0000000a -#define VIP_HW_DEBUG__VIP_HW_B_DEBUG__SHIFT__SI 0x0000000b -#define VIP_HW_DEBUG__VIP_HW_C_DEBUG__SHIFT__SI 0x0000000c -#define VIP_HW_DEBUG__VIP_HW_D_DEBUG__SHIFT__SI 0x0000000d -#define VIP_HW_DEBUG__VIP_HW_E_DEBUG__SHIFT__SI 0x0000000e -#define VIP_HW_DEBUG__VIP_HW_F_DEBUG__SHIFT__SI 0x0000000f -#define VIP_INT__CAP0_INT_ACTIVE__SHIFT__SI 0x0000000e -#define VIP_INT__DMA_VIPH0_INT_AK__SHIFT__SI 0x00000010 -#define VIP_INT__DMA_VIPH0_INT_EN__SHIFT__SI 0x00000000 -#define VIP_INT__DMA_VIPH0_INT__SHIFT__SI 0x00000008 -#define VIP_INT__DMA_VIPH1_INT_AK__SHIFT__SI 0x00000011 -#define VIP_INT__DMA_VIPH1_INT_EN__SHIFT__SI 0x00000001 -#define VIP_INT__DMA_VIPH1_INT__SHIFT__SI 0x00000009 -#define VIP_INT__DMA_VIPH2_INT_AK__SHIFT__SI 0x00000012 -#define VIP_INT__DMA_VIPH2_INT_EN__SHIFT__SI 0x00000002 -#define VIP_INT__DMA_VIPH2_INT__SHIFT__SI 0x0000000a -#define VIP_INT__DMA_VIPH3_INT_AK__SHIFT__SI 0x00000013 -#define VIP_INT__DMA_VIPH3_INT_EN__SHIFT__SI 0x00000003 -#define VIP_INT__DMA_VIPH3_INT__SHIFT__SI 0x0000000b -#define VIP_INT__I2C_INT_AK__SHIFT__SI 0x00000014 -#define VIP_INT__I2C_INT_EN__SHIFT__SI 0x00000004 -#define VIP_INT__I2C_INT__SHIFT__SI 0x0000000c -#define VIP_INT__VIPDMA_BUF_INT_MUX__SHIFT__SI 0x00000015 -#define VIP_INT__VIPH_INT_EN__SHIFT__SI 0x00000005 -#define VIP_INT__VIPH_INT__SHIFT__SI 0x0000000d -#define VIP_MCIF_CNTL__CAPTURE_WPRIV__SHIFT__SI 0x00000011 -#define VIP_MCIF_CNTL__CAPTURE_WTRAN__SHIFT__SI 0x00000010 -#define VIP_MCIF_CNTL__VIPH_CH0_RPRIV__SHIFT__SI 0x00000003 -#define VIP_MCIF_CNTL__VIPH_CH0_RTRAN__SHIFT__SI 0x00000001 -#define VIP_MCIF_CNTL__VIPH_CH0_WPRIV__SHIFT__SI 0x00000002 -#define VIP_MCIF_CNTL__VIPH_CH0_WTRAN__SHIFT__SI 0x00000000 -#define VIP_MCIF_CNTL__VIPH_CH1_RPRIV__SHIFT__SI 0x00000007 -#define VIP_MCIF_CNTL__VIPH_CH1_RTRAN__SHIFT__SI 0x00000005 -#define VIP_MCIF_CNTL__VIPH_CH1_WPRIV__SHIFT__SI 0x00000006 -#define VIP_MCIF_CNTL__VIPH_CH1_WTRAN__SHIFT__SI 0x00000004 -#define VIP_MCIF_CNTL__VIPH_CH2_RPRIV__SHIFT__SI 0x0000000b -#define VIP_MCIF_CNTL__VIPH_CH2_RTRAN__SHIFT__SI 0x00000009 -#define VIP_MCIF_CNTL__VIPH_CH2_WPRIV__SHIFT__SI 0x0000000a -#define VIP_MCIF_CNTL__VIPH_CH2_WTRAN__SHIFT__SI 0x00000008 -#define VIP_MCIF_CNTL__VIPH_CH3_RPRIV__SHIFT__SI 0x0000000f -#define VIP_MCIF_CNTL__VIPH_CH3_RTRAN__SHIFT__SI 0x0000000d -#define VIP_MCIF_CNTL__VIPH_CH3_WPRIV__SHIFT__SI 0x0000000e -#define VIP_MCIF_CNTL__VIPH_CH3_WTRAN__SHIFT__SI 0x0000000c -#define VLINE_START_END__VLINE_END__SHIFT__SI 0x00000010 -#define VLINE_START_END__VLINE_INV__SHIFT__SI 0x0000001f -#define VLINE_START_END__VLINE_START__SHIFT__SI 0x00000000 -#define VLINE_STATUS__VLINE_ACK__SHIFT__SI 0x00000004 -#define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT__SI 0x00000011 -#define VLINE_STATUS__VLINE_INTERRUPT__SHIFT__SI 0x00000010 -#define VLINE_STATUS__VLINE_OCCURRED__SHIFT__SI 0x00000000 -#define VLINE_STATUS__VLINE_STAT__SHIFT__SI 0x0000000c -#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 -#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 -#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT \ - 0x00000001 -#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT \ - 0x00000002 -#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b -#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT__SI__CI 0x00000016 -#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT__SI__CI 0x00000015 -#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT__SI__CI 0x00000017 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000001d -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000001c -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 -#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 -#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT__CI__VI 0x00000000 -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 -#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 -#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 -#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT \ - 0x00000001 -#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT \ - 0x00000002 -#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b -#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT__SI__CI 0x00000016 -#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT__SI__CI 0x00000015 -#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT__SI__CI 0x00000017 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000001d -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000001c -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 -#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 -#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT__CI__VI 0x00000000 -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 -#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x00000000 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0x0000000a -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0x0000000b -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0x0000000c -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0x0000000d -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0x0000000e -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0x0000000f -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x00000001 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x00000002 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x00000003 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x00000004 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x00000005 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x00000006 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x00000007 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x00000008 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x00000009 -#define VM_DEBUG__FLAGS__SHIFT 0x00000000 -#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x00000000 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x00000001 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x00000002 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x00000000 -#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x00000009 -#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x00000000 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x00000000 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0x0000000a -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0x0000000b -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0x0000000c -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0x0000000d -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0x0000000e -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0x0000000f -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x00000001 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x00000002 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x00000003 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x00000004 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x00000005 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x00000006 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x00000007 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x00000008 -#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x00000009 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x00000000 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0x0000000a -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0x0000000b -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0x0000000c -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0x0000000d -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0x0000000e -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0x0000000f -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x00000001 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x00000002 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x00000003 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x00000004 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x00000005 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x00000006 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x00000007 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x00000008 -#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x00000009 -#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x00000000 -#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x00000000 -#define VM_L2_CG__ENABLE__SHIFT 0x00000012 -#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define VM_L2_CG__OFFDLY__SHIFT 0x00000006 -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x00000016 -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x00000015 -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x00000000 -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x0000001a -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x00000001 -#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x00000017 -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT__CI__VI 0x0000001c -#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x00000000 -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x00000015 -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x0000001c -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x00000014 -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x00000018 -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x0000001d -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x0000000f -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x00000006 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x00000008 -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT__CI__VI 0x0000001e -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x00000013 -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0x0000000f -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT__CI__VI 0x0000000b -#define VM_L2_CNTL__ENABLE_INSECURE_READS_WHEN_SECURE__SHIFT__SI 0x0000000b -#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x00000000 -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x00000001 -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x0000000a -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x00000009 -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x00000015 -#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001a -#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001c -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x00000004 -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x00000002 -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0x0000000c -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x00000008 -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x00000012 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x00000000 -#define VM_L2_PERF_COUNTER_CNTL__CLEAR_ALL_L2_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000006 -#define VM_L2_PERF_COUNTER_CNTL__CLEAR_SELECTED_L2_PERFORMANCE_COUNTER__SHIFT__SI 0x00000005 -#define VM_L2_PERF_COUNTER_CNTL__ENABLE_L2_PERFORMANCE_COUNTERS__SHIFT__SI 0x00000008 -#define VM_L2_PERF_COUNTER_CNTL__L2_PERFORMANCE_COUNTER_SELECT__SHIFT__SI 0x00000000 -#define VM_L2_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT__SI 0x00000007 -#define VM_L2_PERF_COUNTER_STATUS__L2_PERFORMANCE_COUNTER__SHIFT__SI 0x00000000 -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x00000001 -#define VM_L2_STATUS__L2_BUSY__SHIFT 0x00000000 -#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 -#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT__SI 0x00000000 -#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT__CI__VI 0x00000000 -#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT__CI__VI 0x00000004 -#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003 -#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002 -#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT__CI__VI 0x00000006 -#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT__SI 0x00000001 -#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT__CI__VI 0x00000001 -#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT__CI__VI 0x00000005 -#define VM_SECURE_FAULT_CNTL__ALLOW_CLIENTS_TO_ACCESS_MAPPED_SYSTEM_MEMORY__SHIFT 0x00000002 -#define VM_SECURE_FAULT_CNTL__ALLOW_RLC_TO_ACCESS_FB__SHIFT 0x00000001 -#define VM_SECURE_FAULT_CNTL__ENABLE_VM_SECURE_FAULT__SHIFT 0x00000000 -#define V_COUNTER__V_COUNTER__SHIFT__SI 0x00000000 -#define WAIT_UNTIL_POLL_CNTL__POLL_ADDR__SHIFT__SI 0x00000000 -#define WAIT_UNTIL_POLL_CNTL__POLL_COMPARE_FUNCTION__SHIFT__SI 0x00000010 -#define WAIT_UNTIL_POLL_CNTL__POLL_INTERVAL__SHIFT__SI 0x00000014 -#define WAIT_UNTIL_POLL_MASK__POLL_MASK__SHIFT__SI 0x00000000 -#define WAIT_UNTIL_POLL_REFDATA__POLL_REFDATA__SHIFT__SI 0x00000000 -#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT__SI 0x00000014 -#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT__SI 0x00000011 -#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT__SI 0x0000000f -#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT__SI 0x0000000a -#define WAIT_UNTIL__WAIT_CP_DMA_IDLE__SHIFT__SI 0x00000008 -#define WAIT_UNTIL__WAIT_EXTERN_SIG__SHIFT__SI 0x00000013 -#define WAIT_UNTIL__WAIT_RING1__SHIFT__SI 0x0000001f -#define WAIT_UNTIL__WAIT_RING2__SHIFT__SI 0x0000001e -#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT__SI 0x00000000 -#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT__SI 0x00000000 -#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT__SI 0x00000000 -#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT__CI__VI 0x00000003 -#define WD_CNTL_STATUS__WD_BUSY__SHIFT__CI__VI 0x00000000 -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT__CI__VI 0x00000002 -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT__CI__VI 0x00000001 -#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT__CI__VI 0x00000006 -#define WD_DEBUG_DATA__DATA__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_REG0__SPARE2__SHIFT__CI__VI 0x0000000c -#define WD_DEBUG_REG0__SPARE3__SHIFT__CI__VI 0x00000010 -#define WD_DEBUG_REG0__core_clk_busy__SHIFT__CI__VI 0x0000001a -#define WD_DEBUG_REG0__input_clk_busy__SHIFT__CI__VI 0x00000019 -#define WD_DEBUG_REG0__rbiu_busy__SHIFT__CI__VI 0x00000004 -#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT__CI__VI 0x00000011 -#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT__CI__VI 0x0000000b -#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT__CI__VI 0x0000000d -#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT__CI__VI 0x0000000a -#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT__CI__VI 0x00000012 -#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT__CI__VI 0x0000000e -#define WD_DEBUG_REG0__reg_clk_busy__SHIFT__CI__VI 0x00000018 -#define WD_DEBUG_REG0__sclk_core_vld__SHIFT__CI__VI 0x0000001e -#define WD_DEBUG_REG0__sclk_input_vld__SHIFT__CI__VI 0x0000001d -#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT__CI__VI 0x0000001c -#define WD_DEBUG_REG0__se0_synced_q__SHIFT__CI__VI 0x00000014 -#define WD_DEBUG_REG0__se1_synced_q__SHIFT__CI__VI 0x00000015 -#define WD_DEBUG_REG0__se2_synced_q__SHIFT__CI__VI 0x00000016 -#define WD_DEBUG_REG0__se3_synced_q__SHIFT__CI__VI 0x00000017 -#define WD_DEBUG_REG0__spl_di_busy__SHIFT__CI__VI 0x00000006 -#define WD_DEBUG_REG0__spl_dma_busy__SHIFT__CI__VI 0x00000005 -#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT__CI__VI 0x00000009 -#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT__CI__VI 0x00000013 -#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT__CI__VI 0x0000000f -#define WD_DEBUG_REG0__vgt0_active_q__SHIFT__CI__VI 0x00000007 -#define WD_DEBUG_REG0__vgt1_active_q__SHIFT__CI__VI 0x00000008 -#define WD_DEBUG_REG0__vgt2_active_q__SHIFT__CI__VI 0x0000001b -#define WD_DEBUG_REG0__vgt3_active_q__SHIFT__CI__VI 0x0000001f -#define WD_DEBUG_REG0__wd_busy__SHIFT__CI__VI 0x00000002 -#define WD_DEBUG_REG0__wd_busy_extended__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT__CI__VI 0x00000003 -#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT__CI__VI 0x00000001 -#define WD_DEBUG_REG1__SPARE0__SHIFT__CI__VI 0x00000008 -#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT__CI__VI 0x00000007 -#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT__CI__VI 0x00000004 -#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT__CI__VI 0x00000006 -#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT__CI__VI 0x00000005 -#define WD_DEBUG_REG1__free_cnt_q__SHIFT__CI__VI 0x00000014 -#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT__CI__VI 0x00000001 -#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT__CI__VI 0x0000000c -#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT__CI__VI 0x00000011 -#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT__CI__VI 0x00000003 -#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT__CI__VI 0x00000002 -#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT__CI__VI 0x0000000b -#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT__CI__VI 0x0000000a -#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT__CI__VI 0x00000009 -#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT__CI__VI 0x0000001c -#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT__CI__VI 0x0000001d -#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT__CI__VI 0x0000001a -#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT__CI__VI 0x0000001e -#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT__CI__VI 0x0000001f -#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT__CI__VI 0x0000001b -#define WD_DEBUG_REG2__SPARE0__SHIFT__CI__VI 0x00000008 -#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT__CI__VI 0x00000007 -#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT__CI__VI 0x00000004 -#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT__CI__VI 0x00000006 -#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT__CI__VI 0x00000005 -#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT__CI__VI 0x00000014 -#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT__CI__VI 0x00000001 -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT__CI__VI 0x0000000c -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT__CI__VI 0x00000011 -#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT__CI__VI 0x00000003 -#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT__CI__VI 0x00000002 -#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT__CI__VI 0x0000000b -#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT__CI__VI 0x0000000a -#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT__CI__VI 0x00000009 -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT__CI__VI 0x0000001c -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT__CI__VI 0x0000001d -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT__CI__VI 0x0000001a -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT__CI__VI 0x0000001e -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT__CI__VI 0x0000001f -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT__CI__VI 0x0000001b -#define WD_DEBUG_REG3__SPARE0__SHIFT__CI__VI 0x00000001 -#define WD_DEBUG_REG3__SPARE1__SHIFT__CI__VI 0x00000017 -#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT__CI__VI 0x00000019 -#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT__CI__VI 0x00000013 -#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT__CI__VI 0x00000012 -#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT__CI__VI 0x00000018 -#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT__CI__VI 0x00000011 -#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT__CI__VI 0x00000010 -#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT__CI__VI 0x00000008 -#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT__CI__VI 0x0000000c -#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT__CI__VI 0x0000000b -#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT__CI__VI 0x0000001b -#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT__CI__VI 0x0000000a -#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT__CI__VI 0x00000014 -#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT__CI__VI 0x0000000f -#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT__CI__VI 0x00000016 -#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT__CI__VI 0x00000015 -#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT__CI__VI 0x0000000e -#define WD_DEBUG_REG3__out_of_range_p4__SHIFT__CI__VI 0x0000000d -#define WD_DEBUG_REG3__pipe0_dr__SHIFT__CI__VI 0x00000002 -#define WD_DEBUG_REG3__pipe0_rtr__SHIFT__CI__VI 0x00000003 -#define WD_DEBUG_REG3__pipe1_dr__SHIFT__CI__VI 0x00000004 -#define WD_DEBUG_REG3__pipe1_rtr__SHIFT__CI__VI 0x00000005 -#define WD_DEBUG_REG3__pipe3_dr__SHIFT__CI__VI 0x0000001c -#define WD_DEBUG_REG3__pipe3_rtr__SHIFT__CI__VI 0x0000001d -#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT__CI__VI 0x0000001a -#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT__CI__VI 0x0000001e -#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT__CI__VI 0x0000001f -#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT__CI__VI 0x00000006 -#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT__CI__VI 0x00000007 -#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT__CI__VI 0x0000001d -#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT__CI__VI 0x0000001c -#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT__CI__VI 0x0000000d -#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT__CI__VI 0x0000000c -#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT__CI__VI 0x00000010 -#define WD_DEBUG_REG4__di_type_p0__SHIFT__CI__VI 0x0000000e -#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT__CI__VI 0x00000013 -#define WD_DEBUG_REG4__dual_ia_mode__SHIFT__CI__VI 0x0000001f -#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT__CI__VI 0x0000001a -#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT__CI__VI 0x0000001b -#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT__CI__VI 0x00000015 -#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT__CI__VI 0x00000017 -#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT__CI__VI 0x00000016 -#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT__CI__VI 0x00000018 -#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT__CI__VI 0x00000019 -#define WD_DEBUG_REG4__pipe0_dr__SHIFT__CI__VI 0x00000004 -#define WD_DEBUG_REG4__pipe0_rtr__SHIFT__CI__VI 0x00000005 -#define WD_DEBUG_REG4__pipe1_dr__SHIFT__CI__VI 0x00000006 -#define WD_DEBUG_REG4__pipe1_rtr__SHIFT__CI__VI 0x00000007 -#define WD_DEBUG_REG4__pipe2_dr__SHIFT__CI__VI 0x00000008 -#define WD_DEBUG_REG4__pipe2_rtr__SHIFT__CI__VI 0x00000009 -#define WD_DEBUG_REG4__pipe3_ld__SHIFT__CI__VI 0x0000000a -#define WD_DEBUG_REG4__pipe3_rtr__SHIFT__CI__VI 0x0000000b -#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT__CI__VI 0x00000002 -#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT__CI__VI 0x00000014 -#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT__CI__VI 0x0000001e -#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT__CI__VI 0x00000001 -#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT__CI__VI 0x00000003 -#define WD_DEBUG_REG5__SPARE0__SHIFT__CI__VI 0x00000001 -#define WD_DEBUG_REG5__SPARE1__SHIFT__CI__VI 0x00000017 -#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT__CI__VI 0x00000019 -#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT__CI__VI 0x00000013 -#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT__CI__VI 0x00000012 -#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT__CI__VI 0x00000018 -#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT__CI__VI 0x00000011 -#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT__CI__VI 0x00000010 -#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT__CI__VI 0x00000008 -#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT__CI__VI 0x0000000c -#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT__CI__VI 0x0000000b -#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT__CI__VI 0x0000001b -#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT__CI__VI 0x0000000a -#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT__CI__VI 0x00000014 -#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT__CI__VI 0x0000000f -#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT__CI__VI 0x00000016 -#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT__CI__VI 0x00000015 -#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT__CI__VI 0x0000000e -#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT__CI__VI 0x0000000d -#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT__CI__VI 0x00000002 -#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT__CI__VI 0x00000003 -#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT__CI__VI 0x00000004 -#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT__CI__VI 0x00000005 -#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT__CI__VI 0x0000001c -#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT__CI__VI 0x0000001d -#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT__CI__VI 0x00000000 -#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT__CI__VI 0x0000001a -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT__CI__VI 0x0000001e -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT__CI__VI 0x0000001f -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT__CI__VI 0x00000006 -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT__CI__VI 0x00000007 -#define WD_ENHANCE__MISC__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT__CI__VI 0x00000000 -#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT__CI__VI 0x0000001c -#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT__CI__VI 0x00000000 - -// Merged Defines - -#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT__VI 0x00000012 -#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT__VI 0x00000001 -#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT__VI 0x00000000 -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT__VI 0x00000000 -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT__VI 0x0000000a -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT__VI 0x0000000b -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT__VI 0x0000000c -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT__VI 0x0000000d -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT__VI 0x0000000e -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT__VI 0x0000000f -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT__VI 0x00000001 -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT__VI 0x00000002 -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT__VI 0x00000003 -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT__VI 0x00000004 -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT__VI 0x00000005 -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT__VI 0x00000006 -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT__VI 0x00000007 -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT__VI 0x00000008 -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT__VI 0x00000009 -#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT__VI 0x0000000f -#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT__VI 0x0000000e -#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT__VI 0x0000000d -#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT__VI 0x0000000c -#define ATC_L1RD_DEBUG2_TLB__L2_XNACK_RETRY_PERIOD__SHIFT__VI 0x00000000 -#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT__VI 0x00000011 -#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT__VI 0x0000000c -#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT__VI 0x0000000f -#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT__VI 0x0000000e -#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT__VI 0x0000000d -#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT__VI 0x0000000c -#define ATC_L1WR_DEBUG2_TLB__L2_XNACK_RETRY_PERIOD__SHIFT__VI 0x00000000 -#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT__VI 0x00000011 -#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT__VI 0x0000000c -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT__VI 0x00000002 -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT__VI 0x00000001 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT__VI 0x00000000 -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT__VI 0x00000014 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT__VI 0x00000000 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT__VI 0x00000000 -#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT__VI 0x0000000d -#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT__VI 0x00000007 -#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT__VI 0x00000000 -#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT__VI 0x00000008 -#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT__VI 0x0000000e -#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT__VI 0x00000017 -#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT__VI 0x0000001f -#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT__VI 0x0000000a -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT__VI 0x0000000b -#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT__VI 0x00000013 -#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT__VI 0x00000019 -#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT__VI 0x00000008 -#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT__VI 0x0000001f -#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT__VI 0x0000001e -#define ATC_L2_DEBUG__CACHE_READ__SHIFT__VI 0x0000001d -#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT__VI 0x00000018 -#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT__VI 0x0000001b -#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT__VI 0x00000007 -#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT__VI 0x00000000 -#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT__VI 0x00000003 -#define ATC_L2_STATUS__BUSY__SHIFT__VI 0x00000000 -#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT__VI 0x00000001 -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT__VI 0x0000001e -#define BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT__VI 0x00000004 -#define BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT__VI 0x00000012 -#define BACO_CNTL__PWRGOOD_IDSC__SHIFT__VI 0x0000000d -#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT__VI 0x00000000 -#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT__VI 0x00000001 -#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT__VI 0x00000010 -#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT__VI 0x00000011 -#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT__VI 0x00000000 -#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT__VI 0x00000001 -#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT__VI 0x00000010 -#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT__VI 0x00000000 -#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM__SHIFT__VI 0x00000011 -#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT__VI 0x00000001 -#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT__VI 0x00000000 -#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT__VI 0x00000000 -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT__VI 0x00000018 -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT__VI 0x00000019 -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT__VI 0x0000001a -#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT__VI 0x0000001b -#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT__VI 0x00000010 -#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT__VI 0x00000005 -#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT__VI 0x00000004 -#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT__VI 0x0000001f -#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT__VI 0x00000002 -#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT__VI 0x00000002 -#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT__VI 0x0000001f -#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT__VI 0x00000002 -#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT__VI 0x00000002 -#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT__VI 0x0000000b -#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT__VI 0x0000000d -#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT__VI 0x0000000e -#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT__VI 0x0000000a -#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT__VI 0x0000000c -#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT__VI 0x0000000f -#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT__VI 0x00000009 -#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT__VI 0x00000000 -#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT__VI 0x00000000 -#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT__VI 0x00000001 -#define BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT__VI 0x00000000 -#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT__VI 0x00000003 -#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd__SHIFT__VI 0x00000002 -#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT__VI 0x00000003 -#define BIF_PWDN_STATUS__SMBUS_REG_pw_status__SHIFT__VI 0x00000002 -#define BIF_RB_BASE__ADDR__SHIFT__VI 0x00000000 -#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT__VI 0x00000011 -#define BIF_RB_CNTL__RB_ENABLE__SHIFT__VI 0x00000000 -#define BIF_RB_CNTL__RB_SIZE__SHIFT__VI 0x00000001 -#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT__VI 0x0000001f -#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT__VI 0x00000008 -#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT__VI 0x00000009 -#define BIF_RB_RPTR__OFFSET__SHIFT__VI 0x00000002 -#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT__VI 0x00000002 -#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT__VI 0x00000000 -#define BIF_RB_WPTR__OFFSET__SHIFT__VI 0x00000002 -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT__VI 0x00000003 -#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst__SHIFT__VI 0x00000002 -#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer__SHIFT__VI 0x00000000 -#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer__SHIFT__VI 0x00000008 -#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer__SHIFT__VI 0x00000010 -#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout__SHIFT__VI 0x00000018 -#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT__VI 0x00000001 -#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT__VI 0x00000000 -#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT__VI 0x00000000 -#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT__VI 0x00000002 -#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT__VI 0x00000000 -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT__VI 0x00000001 -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT__VI 0x00000004 -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT__VI 0x00000005 -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT__VI 0x00000003 -#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT__VI 0x0000001e -#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT__VI 0x00000002 -#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT__VI 0x0000001f -#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT__VI 0x00000002 -#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT__VI 0x0000001f -#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT__VI 0x00000000 -#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT__VI 0x00000000 -#define BX_RESET_EN__FLR_TIMER_SEL__SHIFT__VI 0x00000009 -#define BX_RESET_EN__FLR_TWICE_EN__SHIFT__VI 0x00000008 -#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT__VI 0x00000000 -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT__VI 0x00000007 -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT__VI 0x00000009 -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT__VI 0x00000001 -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT__VI 0x0000000e -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT__VI 0x0000000a -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000005 -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000002 -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT__VI 0x00000004 -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT__VI 0x0000001d -#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT__VI 0x0000001c -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT__VI 0x0000001b -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT__VI 0x00000000 -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT__VI 0x00000018 -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT__VI 0x0000001c -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT__VI 0x00000008 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT__VI 0x00000006 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT__VI 0x00000000 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000005 -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT__VI 0x00000010 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT__VI 0x00000000 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT__VI 0x00000001 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_10__CORE_SCLK_VLD__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_10__REG_SCLK0_VLD__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_10__REG_SCLK1_VLD__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_17__MU_STATE__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_19__DC_READY__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_19__DD_READY__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_1__CB_BUSY__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_3__CC_RB_FULL__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_3__CC_SF_FULL__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_3__CM_CACHE_HIT__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_3__CM_TQ_FULL__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_3__LQUAD_NO_TILE__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_4__CC_CACHE_HIT__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_4__CM_CACHE_STALL__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_4__FC_CACHE_HIT__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_4__FC_CACHE_STALL__SHIFT__VI 0x00000010 -#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL__SHIFT__VI 0x00000002 -#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH__SHIFT__VI 0x00000011 -#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_5__CC_CACHE_STALL__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED__SHIFT__VI 0x00000012 -#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL__SHIFT__VI 0x00000001 -#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST__SHIFT__VI 0x00000005 -#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT__SHIFT__VI 0x00000009 -#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST__SHIFT__VI 0x00000003 -#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST__SHIFT__VI 0x00000006 -#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST__SHIFT__VI 0x00000004 -#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST__SHIFT__VI 0x00000007 -#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT__VI 0x0000000b -#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT__VI 0x00000008 -#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT__VI 0x00000000 -#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC__SHIFT__VI 0x0000000a -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL__SHIFT__VI 0x0000000f -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT__SHIFT__VI 0x00000013 -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD__SHIFT__VI 0x0000000e -#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE__SHIFT__VI 0x00000014 -#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SHIFT__VI 0x0000000d -#define CB_DEBUG_BUS_9__EVENT_ALL__SHIFT__VI 0x00000015 -#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS__SHIFT__VI 0x00000016 -#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE__SHIFT__VI 0x00000017 -#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT__SHIFT__VI 0x0000000c -#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT__SHIFT__VI 0x0000000b -#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT__VI 0x0000001c -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT__VI 0x00000018 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT__VI 0x00000005 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT__VI 0x00000007 -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT__VI 0x0000000b -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT__VI 0x00000002 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT__VI 0x00000004 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT__VI 0x00000008 -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT__VI 0x00000003 -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT__VI 0x0000000c -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT__VI 0x0000000a -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT__VI 0x00000001 -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT__VI 0x00000009 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_GEN3_EN_PIN_A__SHIFT__VI 0x00000001 -#define CC_BIF_BU_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN__SHIFT__VI 0x00000004 -#define CC_BIF_BU_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING__SHIFT__VI 0x00000005 -#define CC_BIF_BX_PINSTRAP0__STRAP_BIF_VGA_DIS_PIN__SHIFT__VI 0x00000004 -#define CC_BIF_BX_PINSTRAP0__STRAP_TX_CFG_DRV_FULL_SWING__SHIFT__VI 0x00000005 -#define CC_BIF_BX_PINSTRAP1__STRAP_BIF_AUDIO_EN_PIN__SHIFT__VI 0x00000001 -#define CC_BIF_BX_PINSTRAP1__STRAP_BIF_CEC_EN_PIN__SHIFT__VI 0x00000002 -#define CC_BIF_BX_PINSTRAP2__STRAP_BIF_BIOS_ROM_EN__SHIFT__VI 0x00000004 -#define CC_BIF_BX_PINSTRAP2__STRAP_BIF_MEM_AP_SIZE_PIN__SHIFT__VI 0x00000001 -#define CC_BIF_BX_STRAP0__STRAP_BIF_AUDIO_EN__SHIFT__VI 0x00000019 -#define CC_BIF_BX_STRAP0__STRAP_BIF_AZ_64BAR_DIS_A__SHIFT__VI 0x0000001c -#define CC_BIF_BX_STRAP0__STRAP_BIF_F0_64BAR_DIS_A__SHIFT__VI 0x0000001a -#define CC_BIF_BX_STRAP0__STRAP_BIF_IO_BAR_DIS__SHIFT__VI 0x00000011 -#define CC_BIF_BX_STRAP0__STRAP_BIF_LFB_ERRMSG_EN__SHIFT__VI 0x0000001e -#define CC_BIF_BX_STRAP0__STRAP_BIF_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT__VI 0x00000010 -#define CC_BIF_BX_STRAP0__STRAP_BIF_VF_DOORBELL_APER_SIZE__SHIFT__VI 0x00000017 -#define CC_BIF_BX_STRAP0__STRAP_BIF_VF_MEM_AP_SIZE__SHIFT__VI 0x00000012 -#define CC_BIF_BX_STRAP0__STRAP_BIF_VF_REG_AP_SIZE__SHIFT__VI 0x00000015 -#define CC_BIF_BX_STRAP0__STRAP_BIF_XSTCLK_SWITCH_OVERRIDE__SHIFT__VI 0x0000001d -#define CC_BIF_BX_STRAP0__STRAP_CEC_64BAR_DIS__SHIFT__VI 0x0000001b -#define CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT__VI 0x0000001f -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_BAR_EN__SHIFT__VI 0x00000008 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_EN__SHIFT__VI 0x00000002 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F0_MSI_PERVECTOR_MASK_CAP__SHIFT__VI 0x00000015 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F1_LEGACY_DEVICE_TYPE_EN__SHIFT__VI 0x00000003 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F1_MSI_PERVECTOR_MASK_CAP__SHIFT__VI 0x00000016 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_EN__SHIFT__VI 0x00000004 -#define CC_BIF_BX_STRAP1__STRAP_BIF_F2_MSI_PERVECTOR_MASK_CAP__SHIFT__VI 0x00000017 -#define CC_BIF_BX_STRAP1__STRAP_BIF_MAX_PASID_WIDTH__SHIFT__VI 0x0000000d -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT__VI 0x00000007 -#define CC_BIF_BX_STRAP1__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT__VI 0x00000006 -#define CC_BIF_BX_STRAP1__STRAP_BIF_SRIOV_EN__SHIFT__VI 0x00000018 -#define CC_BIF_BX_STRAP1__STRAP_BIF_VGA_DIS__SHIFT__VI 0x00000001 -#define CC_BIF_BX_STRAP1__STRAP_CEC_PME_SUPPORT_EN__SHIFT__VI 0x00000014 -#define CC_BIF_BX_STRAP1__STRAP_GPU_PME_SUPPORT_EN__SHIFT__VI 0x00000013 -#define CC_BIF_BX_STRAP1__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT__VI 0x00000005 -#define CC_BIF_BX_STRAP1__STRAP_RESERVED__SHIFT__VI 0x00000019 -#define CC_BIF_BX_STRAP2__STRAP_BIF_IOV_LKRST_DIS__SHIFT__VI 0x00000001 -#define CC_BIF_BX_STRAP2__STRAP_BIF_MSI_CLR_PENDING_EN__SHIFT__VI 0x00000002 -#define CC_BIF_BX_STRAP2__STRAP_RESERVED__SHIFT__VI 0x00000003 -#define CC_BIF_HARDCODE_STRAPS0__STRAP_BIF_F2_BASE_CLASS__SHIFT__VI 0x00000015 -#define CC_BIF_HARDCODE_STRAPS1__STRAP_BIF_F1_BASE_CLASS__SHIFT__VI 0x00000005 -#define CC_BIF_HARDCODE_STRAPS1__STRAP_BIF_MST_ADR64_EN__SHIFT__VI 0x0000001f -#define CC_BIF_HARDCODE_STRAPS3__STRAP_BIF_F0_BASE_CLASS__SHIFT__VI 0x00000000 -#define CC_BIF_SMB_PINSTRAP0__STRAP_BIF_SMBUS_DIS__SHIFT__VI 0x00000001 -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_ARP_DIS__SHIFT__VI 0x00000001 -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_BACKUP_EN__SHIFT__VI 0x00000006 -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_FILTER_DIS__SHIFT__VI 0x00000007 -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_HOLD_SMBCLK_LOW_DIS__SHIFT__VI 0x00000003 -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_NOTIFY_ARP_MST_DIS__SHIFT__VI 0x00000004 -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_THM_OVERRIDE_DIS__SHIFT__VI 0x00000002 -#define CC_BIF_SMB_STRAP0__STRAP_BIF_SMBUS_UDID_RAN_NUM_DIS__SHIFT__VI 0x00000008 -#define CC_BIF_SMB_STRAP1__STRAP_BIF_F0_DEVICE_ID__SHIFT__VI 0x00000004 -#define CC_BIF_SMB_STRAP1__STRAP_BIF_F0_MINOR_REV_ID__SHIFT__VI 0x00000018 -#define CC_BIF_SMB_STRAP2__STRAP_BIF_F0_SUBSYS_ID__SHIFT__VI 0x00000001 -#define CC_BIF_SMB_STRAP3__STRAP_BIF_F0_SUBSYS_VEN_ID__SHIFT__VI 0x00000006 -#define CC_BIF_SMB_STRAP4__STRAP_BIF_VENDOR_ID__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP0__STRAP_BIF_2VC_EN__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP0__STRAP_BIF_ECN1P1_EN__SHIFT__VI 0x00000010 -#define CC_BIF_STRAP0__STRAP_BIF_F0_CPL_ABORT_ERR_EN__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP0__STRAP_BIF_GEN2_COMPLIANCE__SHIFT__VI 0x00000011 -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_SpareRegs__SHIFT__VI 0x00000015 -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_TxFifoBypass__SHIFT__VI 0x00000012 -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_TxFifoDelay2__SHIFT__VI 0x00000014 -#define CC_BIF_STRAP0__STRAP_BIF_GSKT_TxFifoDelay__SHIFT__VI 0x00000013 -#define CC_BIF_STRAP0__STRAP_BIF_LC_CHECK_DATA_RATE__SHIFT__VI 0x0000000f -#define CC_BIF_STRAP0__STRAP_BIF_LC_SELECT_DEEMPHASIS__SHIFT__VI 0x0000000c -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_DIS__SHIFT__VI 0x0000000e -#define CC_BIF_STRAP0__STRAP_BIF_LC_UPCONFIGURE_SUPPORT__SHIFT__VI 0x0000000d -#define CC_BIF_STRAP0__STRAP_BIF_MSTCPL_TIMEOUT_EN__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT__VI 0x00000006 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT__VI 0x00000007 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT__VI 0x00000008 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT__VI 0x00000005 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT__VI 0x00000009 -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT__VI 0x0000000a -#define CC_BIF_STRAP0__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT__VI 0x0000000b -#define CC_BIF_STRAP0__STRAP_RESERVED_0__SHIFT__VI 0x0000001a -#define CC_BIF_STRAP10_A__STRAP_BIF_BCH_ECC_EN_A__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP10_A__STRAP_BIF_BYPASS_RCVR_DET_A__SHIFT__VI 0x00000009 -#define CC_BIF_STRAP10_A__STRAP_BIF_COMPLIANCE_DIS_A__SHIFT__VI 0x00000008 -#define CC_BIF_STRAP10_A__STRAP_BIF_FORCE_COMPLIANCE_A__SHIFT__VI 0x00000005 -#define CC_BIF_STRAP10_A__STRAP_BIF_GEN2_EN_A__SHIFT__VI 0x0000000b -#define CC_BIF_STRAP10_A__STRAP_BIF_LANE_NEGOTIATION_A__SHIFT__VI 0x0000000e -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_A__SHIFT__VI 0x0000000a -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_A__SHIFT__VI \ - 0x0000001a -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_BYPASS_EQ_A__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_A__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_ELEC_IDLE_MODE_A__SHIFT__VI 0x00000011 -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_EQ_SEARCH_MODE_A__SHIFT__VI 0x00000015 -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L0s_EN_A__SHIFT__VI 0x00000007 -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_INIT_SPEED_NEG_IN_L1_EN_A__SHIFT__VI 0x00000006 -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_SPC_MODE_2P5GT_A__SHIFT__VI 0x0000001c -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_SPC_MODE_5GT_A__SHIFT__VI 0x0000001d -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_SPC_MODE_8GT_A__SHIFT__VI 0x0000001e -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_A__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP10_A__STRAP_BIF_LC_TEST_TIMER_SEL_A__SHIFT__VI 0x0000000c -#define CC_BIF_STRAP10_A__STRAP_BIF_SKIP_INTERVAL_A__SHIFT__VI 0x00000017 -#define CC_BIF_STRAP10_A__STRAP_BIF_TARGET_LINK_SPEED_A__SHIFT__VI 0x00000013 -#define CC_BIF_STRAP11_A__STRAP_BIF_FTS_yTSx_COUNT_A__SHIFT__VI 0x0000000f -#define CC_BIF_STRAP11_A__STRAP_BIF_L1_ACCEPTABLE_LATENCY_A__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP11_A__STRAP_BIF_L1_EXIT_LATENCY_A__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP11_A__STRAP_BIF_LC_L0S_INACTIVITY_A__SHIFT__VI 0x00000015 -#define CC_BIF_STRAP11_A__STRAP_BIF_LC_L1_INACTIVITY_A__SHIFT__VI 0x00000011 -#define CC_BIF_STRAP11_A__STRAP_BIF_LONG_yTSx_COUNT_A__SHIFT__VI 0x00000009 -#define CC_BIF_STRAP11_A__STRAP_BIF_MED_yTSx_COUNT_A__SHIFT__VI 0x0000000b -#define CC_BIF_STRAP11_A__STRAP_BIF_PM_SUPPORT_A__SHIFT__VI 0x00000007 -#define CC_BIF_STRAP11_A__STRAP_BIF_SHORT_yTSx_COUNT_A__SHIFT__VI 0x0000000d -#define CC_BIF_STRAP11_A__STRAP_RESERVED_11_A__SHIFT__VI 0x00000019 -#define CC_BIF_STRAP1__STRAP_BIF_ECRC_CHECK_EN__SHIFT__VI 0x00000018 -#define CC_BIF_STRAP1__STRAP_BIF_F0_ATS_EN__SHIFT__VI 0x0000001d -#define CC_BIF_STRAP1__STRAP_BIF_F2_POISONED_ADVISORY_NONFATAL__SHIFT__VI 0x0000001f -#define CC_BIF_STRAP1__STRAP_BIF_MSI_EN__SHIFT__VI 0x0000001e -#define CC_BIF_STRAP1__STRAP_BIF_SYMALIGN_MODE__SHIFT__VI 0x00000017 -#define CC_BIF_STRAP2__STRAP_BIF_AER_EN__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP2__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT__VI 0x00000008 -#define CC_BIF_STRAP2__STRAP_BIF_BYPASS_SCRAMBLER__SHIFT__VI 0x00000005 -#define CC_BIF_STRAP2__STRAP_BIF_ERR_REPORTING_DIS__SHIFT__VI 0x00000009 -#define CC_BIF_STRAP2__STRAP_BIF_EXTENDED_TAG_ECN_EN__SHIFT__VI 0x0000000a -#define CC_BIF_STRAP2__STRAP_BIF_F0_MSI_MULTI_CAP__SHIFT__VI 0x00000017 -#define CC_BIF_STRAP2__STRAP_BIF_F0_POISONED_ADVISORY_NONFATAL__SHIFT__VI 0x0000000b -#define CC_BIF_STRAP2__STRAP_BIF_F0_VC_EN__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP2__STRAP_BIF_F1_MSI_MULTI_CAP__SHIFT__VI 0x0000001a -#define CC_BIF_STRAP2__STRAP_BIF_F1_POISONED_ADVISORY_NONFATAL__SHIFT__VI 0x0000000c -#define CC_BIF_STRAP2__STRAP_BIF_F2_MSI_MULTI_CAP__SHIFT__VI 0x0000001d -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_CDR_MODE__SHIFT__VI 0x00000007 -#define CC_BIF_STRAP2__STRAP_BIF_FORCE_GEN2_MODE__SHIFT__VI 0x00000006 -#define CC_BIF_STRAP2__STRAP_BIF_LC_CDR_SET_TYPE__SHIFT__VI 0x0000000f -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F0_ATOMIC_64BIT_EN__SHIFT__VI 0x00000014 -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT__VI 0x00000011 -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F1_ATOMIC_64BIT_EN__SHIFT__VI 0x00000015 -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F1_ATOMIC_EN__SHIFT__VI 0x00000012 -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F2_ATOMIC_64BIT_EN__SHIFT__VI 0x00000016 -#define CC_BIF_STRAP2__STRAP_BIF_STRAP_F2_ATOMIC_EN__SHIFT__VI 0x00000013 -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_MODE__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP2__STRAP_BIF_TEST_TOGGLE_PATTERN__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP2__STRAP_BIF_TX_TEST_ALL__SHIFT__VI 0x0000000d -#define CC_BIF_STRAP3__STRAP_BIF_FLR_EN__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP3__STRAP_BIF_FORCE_GEN3_MODE__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP3__STRAP_BIF_GEN3_COMPLIANCE__SHIFT__VI 0x00000005 -#define CC_BIF_STRAP3__STRAP_BIF_INTERNAL_ERR_EN__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP3__STRAP_BIF_LC_CDR_TEST_OFF_ENCODE__SHIFT__VI 0x00000016 -#define CC_BIF_STRAP3__STRAP_BIF_NO_SOFT_RESET__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP3__STRAP_BIF_SRIOV_EN__SHIFT__VI 0x0000001a -#define CC_BIF_STRAP3__STRAP_BIF_SUBSYS_VEN_ID__SHIFT__VI 0x00000006 -#define CC_BIF_STRAP3__STRAP_BIF_TOTAL_VFS__SHIFT__VI 0x0000001b -#define CC_BIF_STRAP3__STRAP_PLL_CMP_FREQ_MODE__SHIFT__VI 0x00000018 -#define CC_BIF_STRAP4__STRAP_BIF_F0_MAX_PAYLOAD_SUPPORT__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP4__STRAP_BIF_LTR_SUPPORTED__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP4__STRAP_BIF_OBFF_SUPPORTED__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_8T0_0__SHIFT__VI 0x00000007 -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_8T0_1__SHIFT__VI 0x0000000f -#define CC_BIF_STRAP4__STRAP_BIF_PWR_BUDGET_DATA_8T0_2__SHIFT__VI 0x00000017 -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_8T0_3__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_8T0_4__SHIFT__VI 0x00000009 -#define CC_BIF_STRAP5__STRAP_BIF_PWR_BUDGET_DATA_8T0_5__SHIFT__VI 0x00000011 -#define CC_BIF_STRAP6__STRAP_BIF_F0_DPA_EN__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP6__STRAP_BIF_F2_CPL_ABORT_ERR_EN__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP6__STRAP_BIF_VENDOR_ID__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP6__STRAP_RESERVED_6__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP7__STRAP_BIF_F0_BAR_EN__SHIFT__VI 0x00000008 -#define CC_BIF_STRAP7__STRAP_BIF_F0_LEGACY_DEVICE_TYPE_EN__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP7__STRAP_BIF_F1_LEGACY_DEVICE_TYPE_EN__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP7__STRAP_BIF_F2_LEGACY_DEVICE_TYPE_EN__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP7__STRAP_BIF_MAX_PASID_WIDTH__SHIFT__VI 0x0000000d -#define CC_BIF_STRAP7__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT__VI 0x00000007 -#define CC_BIF_STRAP7__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT__VI 0x00000006 -#define CC_BIF_STRAP7__STRAP_BIF_VGA_DIS__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP7__STRAP_CEC_PME_SUPPORT_EN__SHIFT__VI 0x00000014 -#define CC_BIF_STRAP7__STRAP_GPU_PME_SUPPORT_EN__SHIFT__VI 0x00000013 -#define CC_BIF_STRAP7__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT__VI 0x00000005 -#define CC_BIF_STRAP7__STRAP_RESERVED__SHIFT__VI 0x00000015 -#define CC_BIF_STRAP8__STRAP_BIF_ARI_EN__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP8__STRAP_BIF_CFG_REG_RESET_ONLY__SHIFT__VI 0x00000012 -#define CC_BIF_STRAP8__STRAP_BIF_F0_ACS_EN__SHIFT__VI 0x0000000e -#define CC_BIF_STRAP8__STRAP_BIF_F0_DSN_EN__SHIFT__VI 0x0000000b -#define CC_BIF_STRAP8__STRAP_BIF_F1_ACS_EN__SHIFT__VI 0x0000000f -#define CC_BIF_STRAP8__STRAP_BIF_F1_BAR_EN__SHIFT__VI 0x00000009 -#define CC_BIF_STRAP8__STRAP_BIF_F1_DPA_EN__SHIFT__VI 0x00000005 -#define CC_BIF_STRAP8__STRAP_BIF_F1_DSN_EN__SHIFT__VI 0x0000000c -#define CC_BIF_STRAP8__STRAP_BIF_F1_PWR_EN__SHIFT__VI 0x00000007 -#define CC_BIF_STRAP8__STRAP_BIF_F1_VC_EN__SHIFT__VI 0x00000003 -#define CC_BIF_STRAP8__STRAP_BIF_F2_ACS_EN__SHIFT__VI 0x00000010 -#define CC_BIF_STRAP8__STRAP_BIF_F2_BAR_EN__SHIFT__VI 0x0000000a -#define CC_BIF_STRAP8__STRAP_BIF_F2_DPA_EN__SHIFT__VI 0x00000006 -#define CC_BIF_STRAP8__STRAP_BIF_F2_DSN_EN__SHIFT__VI 0x0000000d -#define CC_BIF_STRAP8__STRAP_BIF_F2_PWR_EN__SHIFT__VI 0x00000008 -#define CC_BIF_STRAP8__STRAP_BIF_F2_VC_EN__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP8__STRAP_BIF_LINK_DOWN_RESET_EN__SHIFT__VI 0x00000013 -#define CC_BIF_STRAP8__STRAP_BIF_MC_EN__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP8__STRAP_PHY_CALIB_RST__SHIFT__VI 0x00000011 -#define CC_BIF_STRAP8__STRAP_RESERVED_8__SHIFT__VI 0x00000014 -#define CC_BIF_STRAP9_A__STRAP_BIF_E2E_PREFIX_EN_A__SHIFT__VI 0x00000001 -#define CC_BIF_STRAP9_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_A__SHIFT__VI 0x00000002 -#define CC_BIF_STRAP9_A__STRAP_BIF_INITIAL_N_FTS_A__SHIFT__VI 0x00000010 -#define CC_BIF_STRAP9_A__STRAP_BIF_L0S_ACCEPTABLE_LATENCY_A__SHIFT__VI 0x00000018 -#define CC_BIF_STRAP9_A__STRAP_BIF_L0S_EXIT_LATENCY_A__SHIFT__VI 0x0000001b -#define CC_BIF_STRAP9_A__STRAP_BIF_LC_EQ_FS_A__SHIFT__VI 0x0000000a -#define CC_BIF_STRAP9_A__STRAP_BIF_LC_EQ_LF_A__SHIFT__VI 0x00000004 -#define CC_BIF_STRAP9_A__STRAP_BIF_LC_X12_NEGOTIATION_DIS_A__SHIFT__VI 0x00000003 -#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT__VI 0x00000001 -#define CC_FCTRL_FUSES__WRITE_DIS__SHIFT__VI 0x00000000 -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT__VI 0x00000001 -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT__VI 0x00000004 -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT__VI 0x00000003 -#define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS__SHIFT__VI 0x00000000 -#define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT__VI 0x00000006 -#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT__VI 0x00000008 -#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT__VI 0x00000004 -#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT__VI 0x00000001 -#define CC_HARVEST_FUSES__WRITE_DIS__SHIFT__VI 0x00000000 -#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT__VI 0x00000013 -#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT__VI 0x00000017 -#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT__VI 0x0000000f -#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT__VI 0x00000010 -#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT__VI 0x00000015 -#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT__VI 0x00000016 -#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT__VI 0x00000019 -#define CC_RCU_FUSES__RCU_SPARE__SHIFT__VI 0x0000001a -#define CC_RCU_FUSES__RED_WRITE_DIS__SHIFT__VI 0x00000014 -#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT__VI 0x00000012 -#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT__VI 0x0000000e -#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT__VI 0x00000018 -#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT__VI 0x00000011 -#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT__VI 0x0000000c -#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT__VI 0x00000014 -#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT__VI 0x00000008 -#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT__VI 0x00000010 -#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT__VI 0x0000001c -#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT__VI 0x00000000 -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT__VI 0x0000001d -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT__VI 0x0000001d -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT__VI 0x0000001d -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT__VI 0x0000001d -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT__VI 0x0000001c -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT__VI 0x0000001d -#define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT__VI 0x00000018 -#define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT__VI 0x00000018 -#define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT__VI 0x00000018 -#define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT__VI 0x00000018 -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT__VI 0x0000001c -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT__VI 0x0000001c -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIR_CNTL_DIVIDER__SHIFT__VI 0x0000000a -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIR_CNTL_EN__SHIFT__VI 0x00000008 -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIR_CNTL_TOG__SHIFT__VI 0x00000009 -#define CG_ACLK_DIV_CNTL__ACLK_DIV_DIVIDER__SHIFT__VI 0x00000000 -#define CG_ACLK_DIV_PSPCLK_OVERCLOCKING_ATTEMPTS__ACLK_DIV_ATTEMPTS__SHIFT__VI 0x00000000 -#define CG_ACLK_DIV_PSPCLK_OVERCLOCKING_ATTEMPTS__PSPCLK_ATTEMPTS__SHIFT__VI 0x00000010 -#define CG_ACLK_DIV_STATUS__ACLK_DIV_DIR_CNTL_DONETOG__SHIFT__VI 0x00000001 -#define CG_ACLK_DIV_STATUS__ACLK_DIV_STATUS__SHIFT__VI 0x00000000 -#define CG_CGTT_OVERRIDE_0__CG_SMU_cgtt_lclk_override__SHIFT__VI 0x00000001 -#define CG_CLK_DIVIDER_STATUS_2__ACLK_DIV_DIVIDER_STATUS__SHIFT__VI 0x00000000 -#define CG_CLK_DIVIDER_STATUS_2__PSPCLK_DIVIDER_STATUS__SHIFT__VI 0x00000008 -#define CG_PSPCLK_CNTL__PSPCLK_DIR_CNTL_DIVIDER__SHIFT__VI 0x0000000a -#define CG_PSPCLK_CNTL__PSPCLK_DIR_CNTL_EN__SHIFT__VI 0x00000008 -#define CG_PSPCLK_CNTL__PSPCLK_DIR_CNTL_TOG__SHIFT__VI 0x00000009 -#define CG_PSPCLK_CNTL__PSPCLK_DIVIDER__SHIFT__VI 0x00000000 -#define CG_PSPCLK_STATUS__PSPCLK_DIR_CNTL_DONETOG__SHIFT__VI 0x00000001 -#define CG_PSPCLK_STATUS__PSPCLK_STATUS__SHIFT__VI 0x00000000 -#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT__VI 0x00000016 -#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT__VI 0x0000001e -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT__SI__CI 0x00000006 -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT__VI 0x00000007 -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT__SI__CI 0x00000004 -#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT__VI 0x00000005 -#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT__SI__CI 0x00000008 -#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT__VI 0x0000000a -#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN__SHIFT__VI 0x00000009 -#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS__SHIFT__VI 0x0000000b -#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN__SHIFT__VI 0x0000000a -#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT__VI 0x00000019 -#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT__VI 0x00000011 -#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT__VI 0x00000015 -#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT__VI 0x00000010 -#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT__VI 0x00000000 -#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ__SHIFT__SI__CI 0x0000001c -#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ__SHIFT__VI 0x0000000e -#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON__SHIFT__VI 0x0000000d -#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT__VI 0x00000004 -#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT__VI 0x0000001c -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT__VI 0x0000000c -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT__VI 0x0000000b -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT__SI__CI 0x00000014 -#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT__VI 0x00000012 -#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT__VI 0x00000001 -#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT__SI__CI 0x00000004 -#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT__VI 0x00000005 -#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS__SHIFT__VI 0x00000019 -#define CG_SPLL_STATUS__SPLL_DIVA_ACK__SHIFT__VI 0x00000019 -#define CG_SPLL_STATUS__SPLL_LOCK_TIMER_DONE__SHIFT__VI 0x00000018 -#define CG_SPLL_STATUS__SPLL_OTEST_LOCK__SHIFT__VI 0x00000017 -#define CG_ULV_VOTING__ACP_ULV_VOTE_EN__SHIFT__VI 0x00000006 -#define CG_ULV_VOTING__DC_AZ_ULV_VOTE_EN__SHIFT__VI 0x0000000a -#define CG_ULV_VOTING__GRBM_0_ULV_VOTE_EN__SHIFT__VI 0x0000000c -#define CG_ULV_VOTING__GRBM_10_ULV_VOTE_EN__SHIFT__VI 0x00000016 -#define CG_ULV_VOTING__GRBM_11_ULV_VOTE_EN__SHIFT__VI 0x00000017 -#define CG_ULV_VOTING__GRBM_12_ULV_VOTE_EN__SHIFT__VI 0x00000018 -#define CG_ULV_VOTING__GRBM_13_ULV_VOTE_EN__SHIFT__VI 0x00000019 -#define CG_ULV_VOTING__GRBM_14_ULV_VOTE_EN__SHIFT__VI 0x0000001a -#define CG_ULV_VOTING__GRBM_15_ULV_VOTE_EN__SHIFT__VI 0x0000001b -#define CG_ULV_VOTING__GRBM_1_ULV_VOTE_EN__SHIFT__VI 0x0000000d -#define CG_ULV_VOTING__GRBM_2_ULV_VOTE_EN__SHIFT__VI 0x0000000e -#define CG_ULV_VOTING__GRBM_3_ULV_VOTE_EN__SHIFT__VI 0x0000000f -#define CG_ULV_VOTING__GRBM_4_ULV_VOTE_EN__SHIFT__VI 0x00000010 -#define CG_ULV_VOTING__GRBM_5_ULV_VOTE_EN__SHIFT__VI 0x00000011 -#define CG_ULV_VOTING__GRBM_6_ULV_VOTE_EN__SHIFT__VI 0x00000012 -#define CG_ULV_VOTING__GRBM_7_ULV_VOTE_EN__SHIFT__VI 0x00000013 -#define CG_ULV_VOTING__GRBM_8_ULV_VOTE_EN__SHIFT__VI 0x00000014 -#define CG_ULV_VOTING__GRBM_9_ULV_VOTE_EN__SHIFT__VI 0x00000015 -#define CG_ULV_VOTING__RLC_ULV_VOTE_EN__SHIFT__VI 0x0000001c -#define CG_ULV_VOTING__SAM_ULV_VOTE_EN__SHIFT__VI 0x0000000b -#define CG_ULV_VOTING__SDMA_ULV_VOTE_EN__SHIFT__VI 0x00000007 -#define CG_ULV_VOTING__UVD_ULV_VOTE_EN__SHIFT__VI 0x00000008 -#define CG_ULV_VOTING__VCE_ULV_VOTE_EN__SHIFT__VI 0x00000009 -#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT__VI 0x0000000d -#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT__VI 0x00000018 -#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT__VI 0x00000000 -#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT__VI 0x00000000 -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT__VI 0x00000005 -#define COMPUTE_NOWHERE__DATA__SHIFT__VI 0x00000000 -#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT__VI 0x0000001e -#define COMPUTE_RELAUNCH__IS_STATE__SHIFT__VI 0x0000001f -#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT__VI 0x00000000 -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT__VI 0x00000000 -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT__VI 0x00000000 -#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT__VI 0x00000000 -#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT__VI 0x00000001 -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT__VI 0x0000001c -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT__VI 0x00000011 -#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT__VI 0x00000000 -#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT__VI 0x00000009 -#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT__VI 0x0000000e -#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT__VI 0x00000015 -#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT__VI 0x00000014 -#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT__VI 0x0000000f -#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT__VI 0x00000008 -#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT__VI 0x0000000d -#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT__VI 0x00000016 -#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT__VI 0x00000017 -#define CPM_CONTROL__SPARE_REGS__SHIFT__VI 0x00000018 -#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT__VI 0x00000001 -#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT__VI 0x0000000a -#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT__VI 0x00000004 -#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT__VI 0x00000005 -#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT__VI 0x00000002 -#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT__VI 0x0000000b -#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT__VI 0x00000010 -#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT__VI 0x00000003 -#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT__VI 0x00000007 -#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT__VI 0x00000006 -#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT__VI 0x0000000c -#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT__VI 0x00000019 -#define CP_APPEND_ADDR_HI__MTYPE__SHIFT__VI 0x0000001b -#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT__VI 0x00000000 -#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT__VI 0x00000000 -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT__VI 0x00000000 -#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT__VI 0x00000000 -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT__VI 0x0000001e -#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT__VI 0x0000001f -#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT__VI 0x00000003 -#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT__VI 0x00000002 -#define CP_CPC_DEBUG__BUSY_EXTENDER__SHIFT__VI 0x00000013 -#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT__VI 0x00000015 -#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT__VI 0x00000017 -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT__VI 0x00000018 -#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT__VI 0x0000001b -#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT__VI 0x00000000 -#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT__VI 0x00000000 -#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT__VI 0x0000000c -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT__VI 0x00000005 -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT__VI 0x00000000 -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT__VI 0x00000004 -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT__VI 0x00000000 -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT__VI 0x00000008 -#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT__VI 0x00000018 -#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT__VI 0x00000016 -#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT__VI 0x00000017 -#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT__VI 0x0000000d -#define CP_CPF_DEBUG__BUSY_EXTENDER__SHIFT__VI 0x00000013 -#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT__VI 0x00000009 -#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT__VI 0x00000007 -#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT__VI 0x00000008 -#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT__VI 0x00000011 -#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT__VI 0x0000001b -#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT__VI 0x0000001a -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT__VI 0x0000001c -#define CP_CPF_STATUS__PRT_BUSY__SHIFT__VI 0x00000010 -#define CP_DFY_CMD__OFFSET__SHIFT__VI 0x00000000 -#define CP_DFY_CMD__SIZE__SHIFT__VI 0x00000010 -#define CP_DFY_CNTL__ENABLE__SHIFT__VI 0x0000001f -#define CP_DFY_CNTL__LFSR_RESET__SHIFT__VI 0x0000001c -#define CP_DFY_CNTL__MODE__SHIFT__VI 0x0000001d -#define CP_DFY_CNTL__MTYPE__SHIFT__VI 0x00000002 -#define CP_DFY_CNTL__POLICY__SHIFT__VI 0x00000000 -#define CP_DFY_CNTL__WRITE_DIS__SHIFT__VI 0x0000001b -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT__VI 0x00000000 -#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT__VI 0x00000016 -#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT__VI 0x0000000a -#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT__VI 0x00000016 -#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT__VI 0x0000000a -#define CP_DMA_PIO_CONTROL__DST_MTYPE__SHIFT__VI 0x00000016 -#define CP_DMA_PIO_CONTROL__SRC_MTYPE__SHIFT__VI 0x0000000a -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT__VI 0x00000000 -#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT__VI 0x00000000 -#define CP_DRAW_OBJECT__OBJECT__SHIFT__VI 0x00000000 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT__VI 0x00000002 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT__VI 0x00000000 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT__VI 0x00000001 -#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT__VI 0x00000008 -#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT__VI 0x00000000 -#define CP_DRAW_WINDOW_LO__MAX__SHIFT__VI 0x00000010 -#define CP_DRAW_WINDOW_LO__MIN__SHIFT__VI 0x00000000 -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT__VI 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT__VI 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT__VI 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT__VI 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT__VI 0x00000004 -#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT__VI 0x00000008 -#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT__VI 0x0000000a -#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT__VI 0x0000000c -#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT__VI 0x00000000 -#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT__VI 0x0000001b -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT__VI 0x00000000 -#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT__VI 0x00000005 -#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT__VI 0x00000008 -#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT__VI 0x00000000 -#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT__VI 0x00000001 -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT__VI 0x00000002 -#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT__VI 0x0000000c -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT__VI 0x0000000c -#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT__VI 0x00000000 -#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT__VI 0x00000001 -#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT__VI 0x00000003 -#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT__VI 0x0000000c -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT__VI 0x0000000a -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT__VI 0x00000009 -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT__VI 0x00000000 -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT__VI 0x00000000 -#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT__VI 0x00000018 -#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT__VI 0x00000017 -#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT__VI 0x00000000 -#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT__VI 0x0000000f -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT__VI 0x0000001f -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT__VI 0x0000000d -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT__VI 0x00000008 -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT__VI 0x0000000e -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT__VI 0x0000000c -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT__VI 0x0000001d -#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT__VI 0x00000000 -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT__VI 0x00000010 -#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT__VI 0x00000000 -#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT__VI 0x0000001f -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT__VI 0x0000001e -#define CP_HQD_EOP_RPTR__RPTR__SHIFT__VI 0x00000000 -#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT__VI 0x00000000 -#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT__VI 0x00000010 -#define CP_HQD_EOP_WPTR__WPTR__SHIFT__VI 0x00000000 -#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT__VI 0x00000000 -#define CP_HQD_ERROR__SUA_ERROR__SHIFT__VI 0x00000004 -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT__VI 0x0000000c -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT__VI 0x00000004 -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT__VI 0x00000001 -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT__VI 0x00000000 -#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT__VI 0x00000000 -#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT__VI 0x00000000 -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT__VI 0x00000000 -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT__VI 0x00000002 -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT__VI 0x00000000 -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT__VI 0x00000009 -#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT__VI 0x0000000a -#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT__VI 0x00000004 -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT__VI 0x00000007 -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT__VI 0x00000008 -#define CP_HQD_HQ_STATUS1__STATUS__SHIFT__VI 0x00000000 -#define CP_HQD_IB_CONTROL__MTYPE__SHIFT__VI 0x0000001b -#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT__VI 0x0000000e -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT__VI 0x0000000b -#define CP_HQD_IQ_TIMER__MTYPE__SHIFT__VI 0x0000001b -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT__VI 0x00000016 -#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT__VI 0x00000004 -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT__VI 0x00000001 -#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT__VI 0x00000000 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT__VI 0x00000005 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT__VI 0x00000004 -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT__VI 0x0000001e -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT__VI 0x0000001d -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT__VI 0x0000001c -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT__VI 0x00000011 -#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT__VI 0x0000000f -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT__VI 0x00000019 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT__VI 0x00000001 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT__VI 0x00000017 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT__VI 0x00000000 -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT__VI 0x0000001f -#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT__VI 0x00000002 -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT__VI 0x00000000 -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT__VI 0x00000000 -#define CP_HYP_CONFIG_RANGE_BASE_1__BASE__SHIFT__VI 0x00000000 -#define CP_HYP_CONFIG_RANGE_BASE_2__BASE__SHIFT__VI 0x00000000 -#define CP_HYP_CONFIG_RANGE_END_1__END__SHIFT__VI 0x00000000 -#define CP_HYP_CONFIG_RANGE_END_2__END__SHIFT__VI 0x00000000 -#define CP_HYP_CONTEXT_RANGE_BASE__BASE__SHIFT__VI 0x00000000 -#define CP_HYP_CONTEXT_RANGE_END__END__SHIFT__VI 0x00000000 -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT__VI 0x00000000 -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT__VI 0x00000000 -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT__VI 0x00000000 -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT__VI 0x00000000 -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT__VI 0x00000000 -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT__VI 0x00000000 -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT__VI 0x00000000 -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT__VI 0x00000000 -#define CP_HYP_SHADER_RANGE_BASE__BASE__SHIFT__VI 0x00000000 -#define CP_HYP_SHADER_RANGE_END__END__SHIFT__VI 0x00000000 -#define CP_HYP_UCONFIG_RANGE_BASE__BASE__SHIFT__VI 0x00000000 -#define CP_HYP_UCONFIG_RANGE_END__END__SHIFT__VI 0x00000000 -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT__VI 0x00000000 -#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT__VI 0x00000000 -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT__VI 0x00000012 -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT__VI 0x0000000b -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT__VI 0x00000015 -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT__VI 0x00000012 -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT__VI 0x0000000b -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT__VI 0x00000015 -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT__VI 0x00000012 -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT__VI 0x0000000b -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT__VI 0x00000015 -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT__VI 0x00000012 -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT__VI 0x0000000b -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT__VI 0x00000015 -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT__VI 0x00000012 -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT__VI 0x0000000b -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT__VI 0x00000013 -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT__VI 0x00000015 -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT__VI 0x00000012 -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT__VI 0x0000000b -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT__VI 0x00000015 -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT__VI 0x00000012 -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT__VI 0x0000000b -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT__VI 0x00000015 -#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT__VI 0x00000012 -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT__VI 0x0000000b -#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT__VI 0x00000015 -#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT__VI 0x00000012 -#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT__VI 0x0000000b -#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT__VI 0x00000015 -#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT__VI 0x0000000c -#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT__VI 0x0000000c -#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT__VI 0x0000000f -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT__VI 0x0000000c -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT__VI 0x0000000f -#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT__VI 0x00000008 -#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT__VI 0x00000004 -#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT__VI 0x00000000 -#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT__VI 0x00000005 -#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT__VI 0x00000003 -#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT__VI 0x00000009 -#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT__VI 0x00000007 -#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT__VI 0x00000006 -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT__VI 0x00000008 -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT__VI 0x00000004 -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT__VI 0x00000000 -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT__VI 0x00000005 -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT__VI 0x00000003 -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT__VI 0x00000009 -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT__VI 0x00000001 -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT__VI 0x00000002 -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT__VI 0x00000007 -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT__VI 0x00000006 -#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT__VI 0x00000008 -#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT__VI 0x00000004 -#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT__VI 0x00000000 -#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT__VI 0x00000005 -#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT__VI 0x00000003 -#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT__VI 0x00000009 -#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT__VI 0x00000007 -#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT__VI 0x00000006 -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT__VI 0x00000008 -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT__VI 0x00000004 -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT__VI 0x00000000 -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT__VI 0x00000005 -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT__VI 0x00000003 -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT__VI 0x00000009 -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT__VI 0x00000001 -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT__VI 0x00000002 -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT__VI 0x00000007 -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT__VI 0x00000006 -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT__VI 0x00000010 -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT__VI 0x00000011 -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT__VI 0x00000012 -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT__VI 0x00000013 -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT__VI 0x00000014 -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT__VI 0x00000015 -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT__VI 0x00000002 -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT__VI 0x00000002 -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT__VI 0x00000007 -#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT__VI 0x00000010 -#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT__VI 0x00000014 -#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT__VI 0x00000012 -#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT__VI 0x00000016 -#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT__VI 0x00000014 -#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT__VI 0x00000016 -#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT__VI 0x00000014 -#define CP_ME_PREEMPTION__OBSOLETE__SHIFT__VI 0x00000000 -#define CP_MQD_CONTROL__MTYPE__SHIFT__VI 0x0000001b -#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT__VI 0x0000000d -#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT__VI 0x0000000c -#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT__VI 0x00000000 -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT__VI 0x00000000 -#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT__VI 0x00000019 -#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT__VI 0x0000001b -#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT__VI 0x00000001 -#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT__VI 0x00000000 -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT__VI 0x00000000 -#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT__VI 0x0000001c -#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT__VI 0x0000001e -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT__VI 0x00000008 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT__VI 0x00000009 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT__VI 0x0000000a -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT__VI 0x0000000b -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT__VI 0x00000010 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT__VI 0x00000011 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT__VI 0x00000012 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT__VI 0x00000013 -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT__VI 0x00000000 -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT__VI 0x00000001 -#define CP_RB0_CNTL__BUF_SWAP__SHIFT__SI__CI 0x00000010 -#define CP_RB0_CNTL__BUF_SWAP__SHIFT__VI 0x00000011 -#define CP_RB0_CNTL__MTYPE__SHIFT__VI 0x0000000f -#define CP_RB1_CNTL__MTYPE__SHIFT__VI 0x0000000f -#define CP_RB2_CNTL__MTYPE__SHIFT__VI 0x0000000f -#define CP_RB_CNTL__BUF_SWAP__SHIFT__SI__CI 0x00000010 -#define CP_RB_CNTL__BUF_SWAP__SHIFT__VI 0x00000011 -#define CP_RB_CNTL__MTYPE__SHIFT__VI 0x0000000f -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT__VI 0x0000001e -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT__VI 0x0000001f -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT__VI 0x00000002 -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT__VI 0x00000002 -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT__VI 0x00000002 -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT__VI 0x00000007 -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT__VI 0x00000006 -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT__VI 0x00000002 -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT__VI 0x00000005 -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT__VI 0x00000003 -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT__VI 0x00000001 -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT__VI 0x00000004 -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT__VI 0x00000000 -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT__VI 0x0000000e -#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT__VI 0x00000014 -#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT__VI 0x00000012 -#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT__VI 0x00000013 -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT__VI 0x00000011 -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT__VI 0x00000010 -#define CP_STAT__ATCL2IU_BUSY__SHIFT__VI 0x0000000e -#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT__VI 0x00000019 -#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT__VI 0x0000001b -#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT__VI 0x00000010 -#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT__VI 0x00000010 -#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT__VI 0x00000000 -#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_APER_AD__SHIFT__VI 0x00000001 -#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT__VI 0x00000000 -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT__VI 0x0000001e -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT__VI 0x0000001f -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT__VI 0x00000004 -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT__VI 0x00000005 -#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT__VI 0x00000011 -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT__VI 0x0000000c -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT__VI 0x0000000f -#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT__VI 0x0000001e -#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT__VI 0x0000001e -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT__VI 0x00000017 -#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT__VI 0x00000007 -#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT__VI 0x00000008 -#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT__VI 0x00000006 -#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT__VI 0x00000009 -#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT__VI 0x0000000b -#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT__VI 0x0000000a -#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT__VI 0x00000012 -#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT__VI 0x0000000c -#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT__VI 0x00000007 -#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT__VI 0x00000006 -#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT__VI 0x00000009 -#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT__VI 0x00000008 -#define DEVICE_CNTL2__LTR_EN__SHIFT__VI 0x0000000a -#define DEVICE_CNTL2__OBFF_EN__SHIFT__VI 0x0000000d -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT__VI 0x00000005 -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT__VI 0x00000000 -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT__VI 0x00000004 -#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT__VI 0x00000002 -#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT__VI 0x00000006 -#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT__VI 0x00000001 -#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT__VI 0x00000010 -#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT__VI 0x00000000 -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT__VI 0x0000001b -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT__VI 0x00000000 -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT__VI 0x00000010 -#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT__VI 0x0000000e -#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT__VI 0x0000001a -#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT__VI 0x0000001f -#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT__VI 0x00000010 -#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT__VI 0x00000000 -#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT__VI 0x00000000 -#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT__VI 0x00000008 -#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT__VI 0x00000010 -#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT__VI 0x00000018 -#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT__VI 0x00000000 -#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT__VI 0x00000008 -#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT__VI 0x00000010 -#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT__VI 0x00000018 -#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT__VI 0x00000010 -#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT__VI 0x00000018 -#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT__VI 0x00000000 -#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT__VI 0x00000008 -#define DIDT_DB_CTRL0__UNUSED_0__SHIFT__VI 0x00000006 -#define DIDT_DB_CTRL2__UNUSED_0__SHIFT__VI 0x0000000e -#define DIDT_DB_CTRL2__UNUSED_1__SHIFT__VI 0x0000001a -#define DIDT_DB_CTRL2__UNUSED_2__SHIFT__VI 0x0000001f -#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT__VI 0x00000010 -#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT__VI 0x00000000 -#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT__VI 0x00000006 -#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT__VI 0x0000000e -#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT__VI 0x0000001a -#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT__VI 0x0000001f -#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT__VI 0x00000010 -#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT__VI 0x00000000 -#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT__VI 0x00000006 -#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT__VI 0x0000000e -#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT__VI 0x0000001a -#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT__VI 0x0000001f -#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT__VI 0x00000010 -#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT__VI 0x00000000 -#define DIDT_TD_CTRL0__UNUSED_0__SHIFT__VI 0x00000006 -#define DIDT_TD_CTRL2__UNUSED_0__SHIFT__VI 0x0000000e -#define DIDT_TD_CTRL2__UNUSED_1__SHIFT__VI 0x0000001a -#define DIDT_TD_CTRL2__UNUSED_2__SHIFT__VI 0x0000001f -#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT__VI 0x00000010 -#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT__VI 0x00000000 -#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT__VI 0x00000002 -#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT__VI 0x0000000f -#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT__VI 0x0000000d -#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT__VI 0x0000001e -#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT__VI 0x00000008 -#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT__VI 0x00000009 -#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT__VI 0x00000004 -#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT__VI 0x00000005 -#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT__VI 0x00000011 -#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT__VI 0x00000012 -#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT__VI 0x0000000e -#define GCK_ACLK_DIV_FUSES__AClkDivADCA__SHIFT__VI 0x00000007 -#define GCK_ACLK_DIV_FUSES__AClkDivDDCA__SHIFT__VI 0x0000000b -#define GCK_ACLK_DIV_FUSES__AClkDivDiDtFloor__SHIFT__VI 0x00000010 -#define GCK_ACLK_DIV_FUSES__AClkDivDiDtWait__SHIFT__VI 0x0000000d -#define GCK_ACLK_DIV_FUSES__StartupAClkDivDid__SHIFT__VI 0x00000000 -#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT__VI 0x00000015 -#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT__VI 0x0000001b -#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT__VI 0x00000009 -#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT__VI 0x0000000f -#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT__VI 0x00000012 -#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT__VI 0x00000000 -#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT__VI 0x00000006 -#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT__VI 0x00000018 -#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT__VI 0x00000003 -#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT__VI 0x0000000c -#define GCK_ADFS_CLK_BYPASS_CNTL2__PSPCLK_BYPASS_CNTL__SHIFT__VI 0x00000000 -#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT__VI 0x00000007 -#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT__VI 0x00000008 -#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT__VI 0x00000003 -#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT__VI 0x00000005 -#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT__VI 0x00000006 -#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT__VI 0x00000000 -#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT__VI 0x00000002 -#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT__VI 0x00000001 -#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT__VI 0x00000009 -#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT__VI 0x0000000a -#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT__VI 0x0000000b -#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT__VI 0x00000004 -#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT__VI 0x0000000c -#define GCK_GPUPLL_DGCK_CNTL_1__GPUPLL_LOCK_TIMER__SHIFT__VI 0x00000010 -#define GCK_GPUPLL_DGCK_CNTL_1__GPUPLL_PWRON_TIMER__SHIFT__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_CLKF_UPDATE__SHIFT__VI 0x00000001 -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_MIN_PWRDN_TIMER__SHIFT__VI 0x00000003 -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_RESET_EN__SHIFT__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL_3__GPUPLL_TEST_UNLOCK_CLR__SHIFT__VI 0x00000002 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_BG_PWRON__SHIFT__VI 0x00000016 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EN__SHIFT__VI 0x0000000b -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SCLK_EXT_SEL__SHIFT__VI 0x00000005 -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SPARE__SHIFT__VI 0x0000000e -#define GCK_GPUPLL_DGCK_CNTL_4__GPUPLL_SSAMP_EN__SHIFT__VI 0x0000000d -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_LF_CNTR__SHIFT__VI 0x00000019 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_VCTL_CNTRL_IN__SHIFT__VI 0x00000011 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_VCTL_CNTRL_OUT__SHIFT__VI 0x00000015 -#define GCK_GPUPLL_DGCK_CNTL_5__GPUPLL_VCTL_EN__SHIFT__VI 0x00000010 -#define GCK_GPUPLL_DGCK_CNTL_6__GPUPLL_FBDIV_SSC_BYPASS__SHIFT__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL_6__GPUPLL_TEST_FRAC_BYPASS__SHIFT__VI 0x00000001 -#define GCK_GPUPLL_DGCK_CNTL_7__GPUPLL_BW_CNTRL__SHIFT__VI 0x00000000 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_BYPASS_EN__SHIFT__VI 0x0000001a -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_INIT_RESET_TIMER__SHIFT__VI 0x0000000d -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_OTEST_LOCK_EN__SHIFT__VI 0x0000001d -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_PWRON__SHIFT__VI 0x0000001b -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_REG_BIAS__SHIFT__VI 0x0000000a -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_RESET__SHIFT__VI 0x00000019 -#define GCK_GPUPLL_DGCK_CNTL__GPUPLL_UNLOCK_CLEAR__SHIFT__VI 0x0000001c -#define GCK_GPUPLL_SPREAD_SPECTRUM__GPUPLL_BGADJ__SHIFT__VI 0x00000010 -#define GCK_GPUPLL_STATUS__GPUPLL_LOCK_TIMER_DONE__SHIFT__VI 0x00000018 -#define GCK_GPUPLL_STATUS__GPUPLL_OPWRGOOD_ISO_ENB__SHIFT__VI 0x00000016 -#define GCK_GPUPLL_STATUS__GPUPLL_OPWRGOOD_S__SHIFT__VI 0x00000015 -#define GCK_GPUPLL_STATUS__GPUPLL_OPWRGOOD_V__SHIFT__VI 0x00000014 -#define GCK_GPUPLL_STATUS__GPUPLL_OTEST_LOCK__SHIFT__VI 0x00000017 -#define GCK_LCLK_FUSES__LClkADCA__SHIFT__VI 0x00000007 -#define GCK_LCLK_FUSES__LClkDDCA__SHIFT__VI 0x0000000b -#define GCK_LCLK_FUSES__LClkDiDtFloor__SHIFT__VI 0x00000010 -#define GCK_LCLK_FUSES__LClkDiDtWait__SHIFT__VI 0x0000000d -#define GCK_LCLK_FUSES__StartupLClkDid__SHIFT__VI 0x00000000 -#define GCK_MISC_FUSES__PSP_ENABLE__SHIFT__VI 0x0000001e -#define GCK_MISC_FUSES__WRITE_DIS_MASK__SHIFT__VI 0x00000006 -#define GCK_MISC__EnableACLK_DIVInBypass__SHIFT__VI 0x00000009 -#define GCK_MISC__EnablePSPCLKInBypass__SHIFT__VI 0x0000000a -#define GCK_MISC__PostDivCntlDis__SHIFT__VI 0x0000000b -#define GCK_MISC__Reserved__SHIFT__VI 0x00000008 -#define GCK_MISC__miscRegisters__SHIFT__VI 0x0000000c -#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT__VI 0x00000011 -#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT__VI 0x0000000a -#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT__VI 0x00000012 -#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT__VI 0x00000005 -#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT__VI 0x00000011 -#define GCK_PSPCLK_FUSES__PspClkADCA__SHIFT__VI 0x00000007 -#define GCK_PSPCLK_FUSES__PspClkDDCA__SHIFT__VI 0x0000000b -#define GCK_PSPCLK_FUSES__PspClkDiDtFloor__SHIFT__VI 0x00000010 -#define GCK_PSPCLK_FUSES__PspClkDiDtWait__SHIFT__VI 0x0000000d -#define GCK_PSPCLK_FUSES__StartupPspClkDid__SHIFT__VI 0x00000000 -#define GCK_RESET_TMR_FUSES__Start_GPUPLL_INIT_RESET_TIMER__SHIFT__VI 0x00000010 -#define GCK_RESET_TMR_FUSES__Start_GPUPLL_PWRON_TIMER__SHIFT__VI 0x00000000 -#define GCK_SPARE_1__GCK_SPARE_1__SHIFT__VI 0x00000000 -#define GCK_TPLL_FUSES__Start_GPUPLL_BGADJ__SHIFT__VI 0x0000000c -#define GCK_TPLL_FUSES__Start_GPUPLL_BW_CNTRL__SHIFT__VI 0x00000000 -#define GCK_TPLL_FUSES__Start_GPUPLL_REG_BIAS__SHIFT__VI 0x00000015 -#define GCK_TPLL_FUSES__Start_GPUPLL_VCOMODE__SHIFT__VI 0x00000013 -#define GCK_TPLL_FUSES__Start_PFD_RESET_CNTRL__SHIFT__VI 0x00000011 -#define GCK_TPLL_FUSES__Start_VTOI_BIAS_CNTL__SHIFT__VI 0x00000010 -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG4__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG5__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG6__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_CU_LKG7__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_GCATCL20__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_NONCU_LKG0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_NONCU_LKG1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_NONCU_LKG2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_NONCU_LKG3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_NONCU_LKG4__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_NONCU_LKG5__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_NONCU_LKG6__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT__VI 0x00000008 -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT__VI 0x00000000 -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT__VI 0x00000004 -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT__VI 0x00000000 -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT__VI 0x0000001e -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT__VI 0x0000001f -#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT__VI 0x00000011 -#define GC_CAC_CNTL__CAC_ENABLE__SHIFT__VI 0x00000000 -#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT__VI 0x00000017 -#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT__VI 0x00000001 -#define GC_CAC_CNTL__UNUSED_0__SHIFT__VI 0x0000001f -#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT__VI 0x00000000 -#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT__VI 0x00000018 -#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT__VI 0x00000000 -#define GC_CAC_CTRL_2__UNUSED_0__SHIFT__VI 0x00000001 -#define GC_CAC_IND_DATA__CAC_IND_DATA__SHIFT__VI 0x00000000 -#define GC_CAC_IND_INDEX__CAC_IND_ADDR__SHIFT__VI 0x00000000 -#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT__VI 0x00000000 -#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_CU_LKG__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_CU_LKG__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_GCATCL2__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_GCATCL2__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_NONCU_LKG__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_NONCU_LKG__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT__VI 0x00000000 -#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT__VI 0x00000010 -#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT__VI 0x00000000 -#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_BCI_0__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CU_LKG_0__WEIGHT_CU_LKG_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CU_LKG_0__WEIGHT_CU_LKG_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CU_LKG_1__WEIGHT_CU_LKG_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CU_LKG_1__WEIGHT_CU_LKG_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CU_LKG_2__WEIGHT_CU_LKG_SIG4__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CU_LKG_2__WEIGHT_CU_LKG_SIG5__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_CU_LKG_3__WEIGHT_CU_LKG_SIG6__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_CU_LKG_3__WEIGHT_CU_LKG_SIG7__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_GCATCL2_0__WEIGHT_GCATCL2_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_GCATCL2_0__unused__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_NONCU_LKG_0__WEIGHT_NONCU_LKG_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_NONCU_LKG_0__WEIGHT_NONCU_LKG_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_NONCU_LKG_1__WEIGHT_NONCU_LKG_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_NONCU_LKG_1__WEIGHT_NONCU_LKG_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_NONCU_LKG_2__WEIGHT_NONCU_LKG_SIG4__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_NONCU_LKG_2__WEIGHT_NONCU_LKG_SIG5__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_NONCU_LKG_3__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_NONCU_LKG_3__WEIGHT_NONCU_LKG_SIG6__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT__VI 0x00000000 -#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT__VI 0x00000010 -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT__VI 0x00000000 -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT__VI 0x00000001 -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT__VI 0x00000004 -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT__VI 0x00000003 -#define GDS_ATOM_CNTL__UNUSED2__SHIFT__SI__CI 0x00000009 -#define GDS_ATOM_CNTL__UNUSED2__SHIFT__VI 0x0000000a -#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT__VI 0x0000000b -#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT__VI 0x0000000c -#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT__VI 0x0000000d -#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT__VI 0x0000000e -#define GDS_CNTL_STATUS__DS_BUSY__SHIFT__VI 0x00000008 -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT__VI 0x00000007 -#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT__VI 0x00000009 -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT__VI 0x0000000a -#define GDS_CS_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_CS_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_CS_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_CS_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_CS_CTXSW_STATUS__R__SHIFT__VI 0x00000000 -#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT__VI 0x00000002 -#define GDS_CS_CTXSW_STATUS__W__SHIFT__VI 0x00000001 -#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT__VI 0x00000002 -#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT__VI 0x00000005 -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT__VI 0x00000000 -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT__VI 0x00000001 -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT__VI 0x00000003 -#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT__VI 0x00000004 -#define GDS_DSM_CNTL__UNUSED__SHIFT__VI 0x00000006 -#define GDS_EDC_CNT__DED__SHIFT__VI 0x00000000 -#define GDS_EDC_CNT__SEC__SHIFT__VI 0x00000010 -#define GDS_EDC_CNT__SED__SHIFT__VI 0x00000008 -#define GDS_EDC_GRBM_CNT__DED__SHIFT__VI 0x00000000 -#define GDS_EDC_GRBM_CNT__SEC__SHIFT__VI 0x00000010 -#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT__VI 0x00000002 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT__VI 0x00000000 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT__VI 0x00000001 -#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT__VI 0x00000004 -#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT__VI 0x00000005 -#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT__VI 0x00000006 -#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT__VI 0x00000007 -#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT__VI 0x00000008 -#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT__VI 0x00000009 -#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT__VI 0x0000000a -#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT__VI 0x0000000b -#define GDS_EDC_OA_DED__UNUSED0__SHIFT__VI 0x00000003 -#define GDS_EDC_OA_DED__UNUSED1__SHIFT__VI 0x0000000c -#define GDS_GFX_CTXSW_STATUS__R__SHIFT__VI 0x00000000 -#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT__VI 0x00000002 -#define GDS_GFX_CTXSW_STATUS__W__SHIFT__VI 0x00000001 -#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT__SI__CI 0x0000001c -#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT__VI 0x0000001d -#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT__SI__CI 0x0000001b -#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT__VI 0x0000001c -#define GDS_GWS_RESOURCE__UNUSED1__SHIFT__SI__CI 0x0000001d -#define GDS_GWS_RESOURCE__UNUSED1__SHIFT__VI 0x0000001e -#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT__VI 0x00000014 -#define GDS_OA_ADDRESS__CRAWLER__SHIFT__VI 0x00000010 -#define GDS_OA_ADDRESS__UNUSED__SHIFT__VI 0x00000016 -#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT__VI 0x00000010 -#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT__VI 0x00000014 -#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GDS_VS_CTXSW_CNT0__PTR__SHIFT__VI 0x00000010 -#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT__VI 0x00000000 -#define GDS_VS_CTXSW_CNT1__PTR__SHIFT__VI 0x00000010 -#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT__VI 0x00000000 -#define GDS_VS_CTXSW_CNT2__PTR__SHIFT__VI 0x00000010 -#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT__VI 0x00000000 -#define GDS_VS_CTXSW_CNT3__PTR__SHIFT__VI 0x00000010 -#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT__VI 0x00000000 -#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT__VI 0x00000002 -#define GMCON_DEBUG__MISC_FLAGS__SHIFT__VI 0x00000008 -#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT__VI 0x00000003 -#define GMCON_DEBUG__STCTRL_ST__SHIFT__VI 0x00000004 -#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT__VI 0x00000000 -#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT__VI 0x00000000 -#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT__VI 0x00000011 -#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT__VI 0x00000008 -#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT__VI 0x0000001d -#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT__VI 0x0000001e -#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT__VI 0x00000010 -#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT__VI 0x0000001c -#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT__VI 0x0000001e -#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT__VI 0x0000001f -#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT__VI 0x0000001d -#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT__VI 0x00000019 -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_10__SHIFT__VI 0x0000000a -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_11__SHIFT__VI 0x0000000b -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_12__SHIFT__VI 0x0000000c -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_13__SHIFT__VI 0x0000000d -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_14__SHIFT__VI 0x0000000e -#define GPIO_MLPS_PINSTRAPS__GPIO_MLPS_PINSTRAP_15__SHIFT__VI 0x0000000f -#define GPU_BIST_CONTROL__CP_DFY_CNTL_WRITE_DIS__SHIFT__VI 0x00000006 -#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT__VI 0x00000002 -#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT__VI 0x00000018 -#define GPU_BIST_CONTROL__RESERVED__SHIFT__VI 0x00000007 -#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT__VI 0x00000001 -#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT__VI 0x00000000 -#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT__VI 0x0000000c -#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT__VI 0x0000000d -#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT__VI 0x0000000c -#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT__VI 0x0000000d -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT__VI 0x00000004 -#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT__VI 0x00000000 -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT__VI 0x0000001e -#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT__VI 0x0000001f -#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT__VI 0x0000001f -#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT__VI 0x0000000d -#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT__VI 0x00000000 -#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT__VI 0x00000002 -#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT__VI 0x00000000 -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT__VI 0x00000010 -#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT__VI 0x00000000 -#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT__VI 0x0000000f -#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT__VI 0x00000000 -#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT__VI 0x00000004 -#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT__VI 0x0000000e -#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT__VI 0x00000002 -#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT__VI 0x00000006 -#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT__VI 0x00000014 -#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT__VI 0x0000001a -#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT__VI 0x00000000 -#define GRBM_TRAP_ADDR__DATA__SHIFT__VI 0x00000000 -#define GRBM_TRAP_OP__RW__SHIFT__VI 0x00000000 -#define GRBM_TRAP_WD_MSK__DATA__SHIFT__VI 0x00000000 -#define GRBM_TRAP_WD__DATA__SHIFT__VI 0x00000000 -#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT__VI 0x0000001f -#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT__VI 0x00000016 -#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT__VI 0x00000014 -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT__VI 0x00000000 -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT__VI 0x00000001 -#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT__VI 0x00000002 -#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT__VI 0x00000005 -#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT__VI 0x0000000c -#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT__VI 0x0000000d -#define GSKT_CONTROL__GSKT_SpareRegs__SHIFT__VI 0x00000003 -#define GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT__VI 0x00000000 -#define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT__VI 0x00000002 -#define GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT__VI 0x00000001 -#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT__VI 0x0000001c -#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT__VI 0x00000000 -#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT__VI 0x00000005 -#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT__VI 0x00000003 -#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT__VI 0x00000000 -#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT__VI 0x00000002 -#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT__VI 0x00000004 -#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT__VI 0x00000000 -#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT__VI 0x00000000 -#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT__VI 0x00000000 -#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT__VI 0x00000012 -#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT__VI 0x00000013 -#define IH_VERSION__VALUE__SHIFT__VI 0x00000000 -#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT__VI 0x0000000f -#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT__VI 0x00000003 -#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT__VI 0x00000016 -#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT__VI 0x00000015 -#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT__VI 0x00000010 -#define LM_CONTROL__LoopbackFifoPtr__SHIFT__VI 0x00000008 -#define LM_CONTROL__LoopbackHalfRate__SHIFT__VI 0x00000006 -#define LM_CONTROL__LoopbackSelect__SHIFT__VI 0x00000001 -#define LM_CONTROL__PRBSPCIeLbSelect__SHIFT__VI 0x00000005 -#define LM_LANEENABLE__LANE_enable__SHIFT__VI 0x00000000 -#define LM_PCIERXMUX0__RXLANE0__SHIFT__VI 0x00000000 -#define LM_PCIERXMUX0__RXLANE1__SHIFT__VI 0x00000008 -#define LM_PCIERXMUX0__RXLANE2__SHIFT__VI 0x00000010 -#define LM_PCIERXMUX0__RXLANE3__SHIFT__VI 0x00000018 -#define LM_PCIERXMUX1__RXLANE4__SHIFT__VI 0x00000000 -#define LM_PCIERXMUX1__RXLANE5__SHIFT__VI 0x00000008 -#define LM_PCIERXMUX1__RXLANE6__SHIFT__VI 0x00000010 -#define LM_PCIERXMUX1__RXLANE7__SHIFT__VI 0x00000018 -#define LM_PCIERXMUX2__RXLANE10__SHIFT__VI 0x00000010 -#define LM_PCIERXMUX2__RXLANE11__SHIFT__VI 0x00000018 -#define LM_PCIERXMUX2__RXLANE8__SHIFT__VI 0x00000000 -#define LM_PCIERXMUX2__RXLANE9__SHIFT__VI 0x00000008 -#define LM_PCIERXMUX3__RXLANE12__SHIFT__VI 0x00000000 -#define LM_PCIERXMUX3__RXLANE13__SHIFT__VI 0x00000008 -#define LM_PCIERXMUX3__RXLANE14__SHIFT__VI 0x00000010 -#define LM_PCIERXMUX3__RXLANE15__SHIFT__VI 0x00000018 -#define LM_PCIETXMUX0__TXLANE0__SHIFT__VI 0x00000000 -#define LM_PCIETXMUX0__TXLANE1__SHIFT__VI 0x00000008 -#define LM_PCIETXMUX0__TXLANE2__SHIFT__VI 0x00000010 -#define LM_PCIETXMUX0__TXLANE3__SHIFT__VI 0x00000018 -#define LM_PCIETXMUX1__TXLANE4__SHIFT__VI 0x00000000 -#define LM_PCIETXMUX1__TXLANE5__SHIFT__VI 0x00000008 -#define LM_PCIETXMUX1__TXLANE6__SHIFT__VI 0x00000010 -#define LM_PCIETXMUX1__TXLANE7__SHIFT__VI 0x00000018 -#define LM_PCIETXMUX2__TXLANE10__SHIFT__VI 0x00000010 -#define LM_PCIETXMUX2__TXLANE11__SHIFT__VI 0x00000018 -#define LM_PCIETXMUX2__TXLANE8__SHIFT__VI 0x00000000 -#define LM_PCIETXMUX2__TXLANE9__SHIFT__VI 0x00000008 -#define LM_PCIETXMUX3__TXLANE12__SHIFT__VI 0x00000000 -#define LM_PCIETXMUX3__TXLANE13__SHIFT__VI 0x00000008 -#define LM_PCIETXMUX3__TXLANE14__SHIFT__VI 0x00000010 -#define LM_PCIETXMUX3__TXLANE15__SHIFT__VI 0x00000018 -#define LM_POWERCONTROL1__LMDeemph0__SHIFT__VI 0x00000008 -#define LM_POWERCONTROL1__LMDeemph1__SHIFT__VI 0x00000011 -#define LM_POWERCONTROL1__LMDeemph2__SHIFT__VI 0x0000001a -#define LM_POWERCONTROL1__LMLaneUnused0__SHIFT__VI 0x00000006 -#define LM_POWERCONTROL1__LMLaneUnused1__SHIFT__VI 0x0000000f -#define LM_POWERCONTROL1__LMLaneUnused2__SHIFT__VI 0x00000018 -#define LM_POWERCONTROL1__LMSkipBit0__SHIFT__VI 0x00000005 -#define LM_POWERCONTROL1__LMSkipBit1__SHIFT__VI 0x0000000e -#define LM_POWERCONTROL1__LMSkipBit2__SHIFT__VI 0x00000017 -#define LM_POWERCONTROL1__LMTxClkEn0__SHIFT__VI 0x00000001 -#define LM_POWERCONTROL1__LMTxClkEn1__SHIFT__VI 0x0000000a -#define LM_POWERCONTROL1__LMTxClkEn2__SHIFT__VI 0x00000013 -#define LM_POWERCONTROL1__LMTxEn0__SHIFT__VI 0x00000000 -#define LM_POWERCONTROL1__LMTxEn1__SHIFT__VI 0x00000009 -#define LM_POWERCONTROL1__LMTxEn2__SHIFT__VI 0x00000012 -#define LM_POWERCONTROL1__LMTxMargin0__SHIFT__VI 0x00000002 -#define LM_POWERCONTROL1__LMTxMargin1__SHIFT__VI 0x0000000b -#define LM_POWERCONTROL1__LMTxMargin2__SHIFT__VI 0x00000014 -#define LM_POWERCONTROL1__LMTxMarginEn0__SHIFT__VI 0x00000007 -#define LM_POWERCONTROL1__LMTxMarginEn1__SHIFT__VI 0x00000010 -#define LM_POWERCONTROL1__LMTxMarginEn2__SHIFT__VI 0x00000019 -#define LM_POWERCONTROL1__TxCoeffID0__SHIFT__VI 0x0000001b -#define LM_POWERCONTROL1__TxCoeffID1__SHIFT__VI 0x0000001d -#define LM_POWERCONTROL2__LMDeemph3__SHIFT__VI 0x00000008 -#define LM_POWERCONTROL2__LMLaneUnused3__SHIFT__VI 0x00000006 -#define LM_POWERCONTROL2__LMSkipBit3__SHIFT__VI 0x00000005 -#define LM_POWERCONTROL2__LMTxClkEn3__SHIFT__VI 0x00000001 -#define LM_POWERCONTROL2__LMTxEn3__SHIFT__VI 0x00000000 -#define LM_POWERCONTROL2__LMTxMargin3__SHIFT__VI 0x00000002 -#define LM_POWERCONTROL2__LMTxMarginEn3__SHIFT__VI 0x00000007 -#define LM_POWERCONTROL2__TxCoeff0__SHIFT__VI 0x0000000d -#define LM_POWERCONTROL2__TxCoeff1__SHIFT__VI 0x00000013 -#define LM_POWERCONTROL2__TxCoeff2__SHIFT__VI 0x00000019 -#define LM_POWERCONTROL2__TxCoeffID2__SHIFT__VI 0x00000009 -#define LM_POWERCONTROL2__TxCoeffID3__SHIFT__VI 0x0000000b -#define LM_POWERCONTROL3__RxEqCtl0__SHIFT__VI 0x00000006 -#define LM_POWERCONTROL3__RxEqCtl1__SHIFT__VI 0x0000000c -#define LM_POWERCONTROL3__RxEqCtl2__SHIFT__VI 0x00000012 -#define LM_POWERCONTROL3__RxEqCtl3__SHIFT__VI 0x00000018 -#define LM_POWERCONTROL3__TxCoeff3__SHIFT__VI 0x00000000 -#define LM_POWERCONTROL4__LaneNum0__SHIFT__VI 0x0000000c -#define LM_POWERCONTROL4__LaneNum1__SHIFT__VI 0x00000010 -#define LM_POWERCONTROL4__LaneNum2__SHIFT__VI 0x00000014 -#define LM_POWERCONTROL4__LaneNum3__SHIFT__VI 0x00000018 -#define LM_POWERCONTROL4__LinkNum0__SHIFT__VI 0x00000000 -#define LM_POWERCONTROL4__LinkNum1__SHIFT__VI 0x00000003 -#define LM_POWERCONTROL4__LinkNum2__SHIFT__VI 0x00000006 -#define LM_POWERCONTROL4__LinkNum3__SHIFT__VI 0x00000009 -#define LM_POWERCONTROL4__SpcMode0__SHIFT__VI 0x0000001c -#define LM_POWERCONTROL4__SpcMode1__SHIFT__VI 0x0000001d -#define LM_POWERCONTROL4__SpcMode2__SHIFT__VI 0x0000001e -#define LM_POWERCONTROL4__SpcMode3__SHIFT__VI 0x0000001f -#define LM_POWERCONTROL__LMLinkSpeed0__SHIFT__VI 0x00000006 -#define LM_POWERCONTROL__LMLinkSpeed1__SHIFT__VI 0x0000000e -#define LM_POWERCONTROL__LMLinkSpeed2__SHIFT__VI 0x00000016 -#define LM_POWERCONTROL__LMLinkSpeed3__SHIFT__VI 0x0000001e -#define LM_POWERCONTROL__LMRxPhyCmd0__SHIFT__VI 0x00000003 -#define LM_POWERCONTROL__LMRxPhyCmd1__SHIFT__VI 0x0000000b -#define LM_POWERCONTROL__LMRxPhyCmd2__SHIFT__VI 0x00000013 -#define LM_POWERCONTROL__LMRxPhyCmd3__SHIFT__VI 0x0000001b -#define LM_POWERCONTROL__LMTxPhyCmd0__SHIFT__VI 0x00000000 -#define LM_POWERCONTROL__LMTxPhyCmd1__SHIFT__VI 0x00000008 -#define LM_POWERCONTROL__LMTxPhyCmd2__SHIFT__VI 0x00000010 -#define LM_POWERCONTROL__LMTxPhyCmd3__SHIFT__VI 0x00000018 -#define LM_PRBSCONTROL__LMLaneDegrade0__SHIFT__VI 0x0000001c -#define LM_PRBSCONTROL__LMLaneDegrade1__SHIFT__VI 0x0000001d -#define LM_PRBSCONTROL__LMLaneDegrade2__SHIFT__VI 0x0000001e -#define LM_PRBSCONTROL__LMLaneDegrade3__SHIFT__VI 0x0000001f -#define LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT__VI 0x00000000 -#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT__VI 0x00000001 -#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT__VI 0x00000002 -#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT__VI 0x00000003 -#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT__VI 0x00000004 -#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT__VI 0x00000000 -#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT__VI 0x00000000 -#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT__VI 0x00000004 -#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT__VI 0x00000000 -#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT__VI 0x00000010 -#define LNC_BW_WACC__LNC_BW_WACC__SHIFT__VI 0x00000000 -#define LNC_CMN_WACC__LNC_CMN_WACC__SHIFT__VI 0x00000000 -#define LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT__VI 0x00000000 -#define LPML_SCALAR_1__Lpml1__SHIFT__VI 0x00000000 -#define LPML_SCALAR_1__Lpml2__SHIFT__VI 0x00000006 -#define LPML_SCALAR_1__Lpml3__SHIFT__VI 0x0000000c -#define LPML_SCALAR_1__Lpml4__SHIFT__VI 0x00000012 -#define LPML_SCALAR_1__Lpml5__SHIFT__VI 0x00000018 -#define LPML_SCALAR_2__Lpml0__SHIFT__VI 0x0000000c -#define LPML_SCALAR_2__Lpml6__SHIFT__VI 0x00000000 -#define LPML_SCALAR_2__Lpml7__SHIFT__VI 0x00000006 -#define LPMV_SCALAR_1__Lpmv1__SHIFT__VI 0x00000000 -#define LPMV_SCALAR_1__Lpmv2__SHIFT__VI 0x00000006 -#define LPMV_SCALAR_1__Lpmv3__SHIFT__VI 0x0000000c -#define LPMV_SCALAR_1__Lpmv4__SHIFT__VI 0x00000012 -#define LPMV_SCALAR_1__Lpmv5__SHIFT__VI 0x00000018 -#define LPMV_SCALAR_2__Lpmv0__SHIFT__VI 0x0000000c -#define LPMV_SCALAR_2__Lpmv6__SHIFT__VI 0x00000000 -#define LPMV_SCALAR_2__Lpmv7__SHIFT__VI 0x00000006 -#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT__VI 0x00000003 -#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT__VI 0x00000002 -#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT__VI 0x00000001 -#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT__VI 0x00000000 -#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT__VI 0x00000000 -#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT__VI 0x00000001 -#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT__VI 0x00000000 -#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT__VI 0x00000018 -#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT__VI 0x00000019 -#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT__VI 0x00000016 -#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT__VI 0x00000017 -#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT__VI 0x00000008 -#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT__VI 0x00000007 -#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT__VI 0x00000004 -#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT__VI 0x00000003 -#define MC_ARB_ATOMIC__TC_GRP__SHIFT__VI 0x00000000 -#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT__VI 0x00000018 -#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT__VI 0x00000019 -#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT__VI 0x0000000c -#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT__VI 0x0000000a -#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT__VI 0x0000000d -#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT__VI 0x00000007 -#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT__VI 0x00000008 -#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT__VI 0x0000000b -#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT__VI 0x00000009 -#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT__VI 0x00000011 -#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT__VI 0x00000015 -#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT__VI 0x00000016 -#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT__VI 0x00000017 -#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT__VI 0x00000012 -#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT__VI 0x00000013 -#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT__VI 0x00000014 -#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT__VI 0x0000000e -#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT__VI 0x00000002 -#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT__VI 0x00000004 -#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT__VI 0x00000006 -#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT__VI 0x0000000a -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT__VI 0x00000014 -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT__VI 0x00000016 -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT__VI 0x00000012 -#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT__VI 0x0000001a -#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT__VI 0x0000001c -#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT__VI 0x0000000c -#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT__VI 0x0000001e -#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT__VI 0x00000012 -#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT__VI 0x00000014 -#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT__VI 0x00000002 -#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT__VI 0x00000004 -#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT__VI 0x00000006 -#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT__VI 0x0000000a -#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT__VI 0x0000000c -#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT__VI 0x00000016 -#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT__VI 0x0000001a -#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT__VI 0x0000001c -#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT__VI 0x0000000e -#define MC_ARB_GRUB_PRIORITY1_WR__VCE__SHIFT__VI 0x0000001e -#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT__VI 0x0000000c -#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT__VI 0x0000001c -#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT__VI 0x0000001e -#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT__VI 0x0000000a -#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT__VI 0x00000016 -#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT__VI 0x00000002 -#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT__VI 0x0000000e -#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT__VI 0x00000012 -#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT__VI 0x00000014 -#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB_PRIORITY2_RD__VCEU__SHIFT__VI 0x00000006 -#define MC_ARB_GRUB_PRIORITY2_RD__VCE__SHIFT__VI 0x00000004 -#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT__VI 0x0000001a -#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT__VI 0x0000000a -#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT__VI 0x0000001c -#define MC_ARB_GRUB_PRIORITY2_WR__RSV3__SHIFT__VI 0x0000001e -#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT__VI 0x00000002 -#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT__VI 0x00000016 -#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT__VI 0x0000000c -#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT__VI 0x00000012 -#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT__VI 0x0000000e -#define MC_ARB_GRUB_PRIORITY2_WR__VCEU__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT__VI 0x0000001a -#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT__VI 0x00000006 -#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT__VI 0x00000004 -#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT__VI 0x00000014 -#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT__VI 0x00000009 -#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT__VI 0x00000001 -#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT__VI 0x00000002 -#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT__VI 0x00000003 -#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT__VI 0x00000004 -#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT__VI 0x00000005 -#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT__VI 0x0000000b -#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT__VI 0x0000000c -#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT__VI 0x0000000d -#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT__VI 0x0000000a -#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT__VI 0x00000017 -#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT__VI 0x00000007 -#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT__VI 0x0000001f -#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT__VI 0x0000000e -#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT__VI 0x0000000f -#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT__VI 0x0000001d -#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT__VI 0x00000016 -#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT__VI 0x00000011 -#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT__VI 0x0000001c -#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT__VI 0x00000012 -#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT__VI 0x00000006 -#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT__VI 0x0000001a -#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT__VI 0x0000001b -#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT__VI 0x00000019 -#define MC_ARB_GRUB_REALTIME_RD__VCEU__SHIFT__VI 0x00000014 -#define MC_ARB_GRUB_REALTIME_RD__VCE__SHIFT__VI 0x00000013 -#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT__VI 0x0000001e -#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT__VI 0x00000015 -#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT__VI 0x00000009 -#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT__VI 0x0000000a -#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT__VI 0x00000001 -#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT__VI 0x00000002 -#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT__VI 0x00000003 -#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT__VI 0x00000004 -#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT__VI 0x00000005 -#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT__VI 0x00000006 -#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT__VI 0x00000015 -#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT__VI 0x0000001c -#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT__VI 0x0000001e -#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT__VI 0x0000000b -#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT__VI 0x0000000c -#define MC_ARB_GRUB_REALTIME_WR__RSV2__SHIFT__VI 0x0000001f -#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT__VI 0x00000011 -#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT__VI 0x00000014 -#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT__VI 0x0000000d -#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT__VI 0x0000001b -#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT__VI 0x0000000e -#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT__VI 0x00000007 -#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT__VI 0x00000016 -#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT__VI 0x00000018 -#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT__VI 0x00000019 -#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT__VI 0x00000017 -#define MC_ARB_GRUB_REALTIME_WR__VCEU__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB_REALTIME_WR__VCE__SHIFT__VI 0x0000000f -#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT__VI 0x0000001d -#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT__VI 0x00000013 -#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT__VI 0x00000012 -#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT__VI 0x0000001a -#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT__VI 0x00000010 -#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT__VI 0x00000008 -#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT__VI 0x00000000 -#define MC_ARB_GRUB__REG_RD_SEL__SHIFT__VI 0x0000001a -#define MC_ARB_GRUB__REG_WR_EN__SHIFT__VI 0x00000018 -#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT__VI 0x00000018 -#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT__VI 0x00000002 -#define MC_ARB_MISC3__CHAN4_EN__SHIFT__VI 0x00000001 -#define MC_ARB_MISC3__TBD_FIELD__SHIFT__VI 0x00000005 -#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT__VI 0x00000004 -#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT__VI 0x00000003 -#define MC_ARB_PERF_CID__CH0_EN__SHIFT__VI 0x00000010 -#define MC_ARB_PERF_CID__CH0__SHIFT__VI 0x00000000 -#define MC_ARB_PERF_CID__CH1_EN__SHIFT__VI 0x00000011 -#define MC_ARB_PERF_CID__CH1__SHIFT__VI 0x00000008 -#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT__VI 0x00000010 -#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT__VI 0x00000011 -#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT__VI 0x00000018 -#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT__VI 0x00000019 -#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT__VI 0x00000018 -#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT__VI 0x0000000a -#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT__VI 0x0000000f -#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT__VI 0x0000000e -#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT__VI 0x0000000b -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT__VI 0x00000008 -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT__VI 0x00000009 -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT__VI 0x0000000c -#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT__VI 0x0000000d -#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT__VI 0x00000010 -#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT__VI 0x0000001c -#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT__VI 0x0000000e -#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT__VI 0x0000000d -#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT__VI 0x0000000c -#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT__VI 0x00000010 -#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT__VI 0x00000018 -#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT__VI 0x0000000b -#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT__VI 0x00000008 -#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT__VI 0x0000000f -#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT__VI 0x0000000c -#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT__VI 0x00000003 -#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT__VI 0x00000000 -#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT__VI 0x00000007 -#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT__VI 0x00000004 -#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT__VI 0x00000006 -#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT__VI 0x00000007 -#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT__VI 0x0000000b -#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT__VI 0x00000009 -#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT__VI 0x00000000 -#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT__SI__CI 0x00000010 -#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT__VI 0x00000018 -#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT__VI 0x00000019 -#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT__VI 0x00000010 -#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT__VI 0x00000011 -#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT__SI__CI 0x00000006 -#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT__VI 0x00000001 -#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT__SI__CI 0x0000000c -#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT__VI 0x00000007 -#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT__VI 0x00000012 -#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT__SI__CI 0x00000007 -#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT__VI 0x00000002 -#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT__SI__CI 0x0000000d -#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT__VI 0x00000008 -#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT__SI__CI 0x0000000e -#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT__VI 0x00000009 -#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT__VI 0x0000000e -#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT__SI__CI 0x00000008 -#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT__VI 0x00000003 -#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT__SI__CI 0x00000010 -#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT__VI 0x0000000b -#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT__VI 0x0000000f -#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT__SI__CI 0x0000000a -#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT__VI 0x00000005 -#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT__SI__CI 0x00000011 -#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT__VI 0x0000000c -#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT__VI 0x00000010 -#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT__SI__CI 0x0000000f -#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT__VI 0x0000000a -#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT__SI__CI 0x00000012 -#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT__VI 0x0000000d -#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT__SI__CI 0x00000009 -#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT__VI 0x00000004 -#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT__SI__CI 0x0000000b -#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT__VI 0x00000006 -#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT__VI 0x00000006 -#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT__VI 0x0000000c -#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT__VI 0x0000000d -#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT__VI 0x00000006 -#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT__VI 0x00000007 -#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT__VI 0x0000000b -#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT__VI 0x00000004 -#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT__VI 0x00000005 -#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT__VI 0x00000006 -#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT__VI 0x00000007 -#define MC_CONFIG__MC_RD_ENABLE__SHIFT__SI__CI 0x00000004 -#define MC_CONFIG__MC_RD_ENABLE__SHIFT__VI 0x00000008 -#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT__VI 0x00000010 -#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT__VI 0x0000000f -#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT__VI 0x00000011 -#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT__VI 0x0000001a -#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT__VI 0x00000000 -#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT__VI 0x00000008 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT__VI 0x0000000e -#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT__VI 0x00000007 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT__VI 0x00000003 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT__VI 0x00000008 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT__VI 0x00000004 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT__VI 0x00000000 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT__VI 0x00000018 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT__VI 0x0000000b -#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT__VI 0x0000001d -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT__VI 0x00000012 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT__VI 0x00000015 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT__VI 0x00000014 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT__VI 0x00000017 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT__VI 0x0000000f -#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT__VI 0x00000010 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT__VI 0x00000013 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT__VI 0x00000016 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT__VI 0x0000000c -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT__VI 0x00000009 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT__VI 0x00000005 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT__VI 0x00000001 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT__VI 0x0000000d -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT__VI 0x0000000a -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT__VI 0x00000006 -#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT__VI 0x00000002 -#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT__VI 0x00000004 -#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT__VI 0x00000002 -#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT__VI 0x00000000 -#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT__VI 0x00000000 -#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT__VI 0x00000006 -#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT__VI 0x00000002 -#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT__VI 0x00000008 -#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT__VI 0x00000012 -#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT__VI 0x0000001a -#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT__VI 0x00000010 -#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT__VI 0x00000014 -#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT__VI 0x00000016 -#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT__VI 0x00000018 -#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT__VI 0x00000004 -#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT__VI 0x0000000c -#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT__VI 0x0000000e -#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT__VI 0x0000001e -#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT__VI 0x0000001c -#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT__VI 0x0000000a -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT__VI 0x00000009 -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT__VI 0x00000008 -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT__VI 0x00000004 -#define MC_FUS_DRAM0_CS01_MASK__ADDRMASK21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM0_CS01_MASK__ADDRMASK38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM0_CS23_MASK__ADDRMASK21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM0_CS23_MASK__ADDRMASK38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM0_CTL_BASE__DCTADRMAPVAL__SHIFT__VI 0x0000001d -#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT__VI 0x00000007 -#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT__VI 0x00000003 -#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT__VI 0x0000001c -#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT__VI 0x00000015 -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT__VI 0x00000009 -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT__VI 0x00000008 -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT__VI 0x00000004 -#define MC_FUS_DRAM1_CS01_MASK__ADDRMASK21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM1_CS01_MASK__ADDRMASK38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM1_CS23_MASK__ADDRMASK21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM1_CS23_MASK__ADDRMASK38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT__VI 0x00000005 -#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT__VI 0x00000013 -#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM1_CTL_BASE__DCTADRMAPVAL__SHIFT__VI 0x0000001d -#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT__VI 0x00000007 -#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT__VI 0x00000003 -#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT__VI 0x0000001c -#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT__VI 0x00000015 -#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT__VI 0x0000001c -#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT__VI 0x0000000c -#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT__VI 0x0000000c -#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT__VI 0x00000000 -#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT__VI 0x00000006 -#define MC_FUS_DRAM_MODE__DRAMTYPE__SHIFT__VI 0x00000003 -#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY__SHIFT__VI 0x00000004 -#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE__SHIFT__VI 0x00000003 -#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL__SHIFT__VI 0x0000000e -#define MC_GRUB_FEATURES__ARB_STALL_EN__SHIFT__VI 0x0000000a -#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL__SHIFT__VI 0x0000000c -#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL__SHIFT__VI 0x00000012 -#define MC_GRUB_FEATURES__CREDIT_STALL_EN__SHIFT__VI 0x0000000b -#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL__SHIFT__VI 0x00000010 -#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE__SHIFT__VI 0x00000002 -#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE__SHIFT__VI 0x00000005 -#define MC_GRUB_FEATURES__RT_BYPASS_OFF__SHIFT__VI 0x00000006 -#define MC_GRUB_FEATURES__SCLK_CG_DISABLE__SHIFT__VI 0x00000001 -#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE__SHIFT__VI 0x00000007 -#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE__SHIFT__VI 0x00000008 -#define MC_GRUB_FEATURES__WR_COMBINE_OFF__SHIFT__VI 0x00000000 -#define MC_GRUB_FEATURES__WR_REORDER_OFF__SHIFT__VI 0x00000014 -#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR__SHIFT__VI 0x0000001d -#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE__SHIFT__VI 0x0000001c -#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT__VI 0x00000018 -#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT__VI 0x00000008 -#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT__VI 0x00000000 -#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR__SHIFT__VI 0x0000001d -#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE__SHIFT__VI 0x0000001c -#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT__VI 0x00000018 -#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT__VI 0x00000008 -#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT__VI 0x00000000 -#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT__VI 0x00000010 -#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT__VI 0x00000000 -#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT__VI 0x00000000 -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT__VI 0x00000019 -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT__VI 0x00000018 -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT__VI 0x00000000 -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT__VI 0x00000008 -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT__VI 0x0000001a -#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT__VI 0x00000010 -#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY__SHIFT__VI 0x00000008 -#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY__SHIFT__VI 0x00000010 -#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY__SHIFT__VI 0x00000000 -#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI__SHIFT__VI 0x00000008 -#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO__SHIFT__VI 0x00000000 -#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL__SHIFT__VI 0x0000000f -#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH__SHIFT__VI 0x00000010 -#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH__SHIFT__VI 0x00000014 -#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP__SHIFT__VI 0x00000008 -#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP__SHIFT__VI 0x00000000 -#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP__SHIFT__VI 0x00000009 -#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP__SHIFT__VI 0x00000002 -#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP__SHIFT__VI 0x0000000a -#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP__SHIFT__VI 0x00000004 -#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP__SHIFT__VI 0x0000000b -#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP__SHIFT__VI 0x00000006 -#define MC_GRUB_TCB_DATA_HI__DATA__SHIFT__VI 0x00000000 -#define MC_GRUB_TCB_DATA_LO__DATA__SHIFT__VI 0x00000000 -#define MC_GRUB_TCB_INDEX__INDEX__SHIFT__VI 0x00000000 -#define MC_GRUB_TCB_INDEX__RD_EN__SHIFT__VI 0x0000000a -#define MC_GRUB_TCB_INDEX__TCB0_WR_EN__SHIFT__VI 0x00000008 -#define MC_GRUB_TCB_INDEX__TCB1_WR_EN__SHIFT__VI 0x00000009 -#define MC_GRUB_TCB_INDEX__TCB_SEL__SHIFT__VI 0x0000000b -#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE__SHIFT__VI 0x0000000c -#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE__SHIFT__VI 0x00000010 -#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT__SHIFT__VI 0x00000000 -#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE__SHIFT__VI 0x00000008 -#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH__SHIFT__VI 0x00000014 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT__VI 0x0000000b -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT__VI 0x00000004 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT__VI 0x00000000 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT__VI 0x00000007 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT__VI 0x0000000e -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT__VI 0x00000008 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT__VI 0x00000001 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT__VI 0x0000000c -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT__VI 0x00000002 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT__VI 0x00000003 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT__VI 0x00000006 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT__VI 0x00000005 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT__VI 0x0000000a -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT__VI 0x00000009 -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT__VI 0x0000000f -#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT__VI 0x0000000d -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT__VI 0x00000016 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT__VI 0x00000017 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT__VI 0x0000001c -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT__VI 0x0000001d -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT__VI 0x00000018 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT__VI 0x00000019 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT__VI 0x00000014 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT__VI 0x00000015 -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT__VI 0x0000001e -#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT__VI 0x0000001f -#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT__VI 0x00000012 -#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT__SI__CI 0x0000000d -#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT__VI 0x00000013 -#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT__VI 0x00000002 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT__VI 0x00000007 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT__VI 0x00000008 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT__SI__CI 0x00000002 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT__VI 0x00000003 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT__SI__CI 0x00000003 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT__VI 0x00000004 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT__SI__CI 0x00000004 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT__VI 0x00000005 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT__SI__CI 0x00000005 -#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT__VI 0x00000006 -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT__VI 0x0000000e -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT__SI__CI 0x00000008 -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT__VI 0x0000000c -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT__SI__CI 0x00000009 -#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT__VI 0x0000000d -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT__VI 0x0000000b -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT__SI__CI 0x00000006 -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT__VI 0x00000009 -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT__SI__CI 0x00000007 -#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT__VI 0x0000000a -#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT__SI__CI 0x0000000c -#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT__VI 0x00000011 -#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT__SI__CI 0x0000000a -#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT__VI 0x0000000f -#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT__SI__CI 0x0000000b -#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT__VI 0x00000009 -#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT__VI 0x00000018 -#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT__SI__CI 0x00000009 -#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT__VI 0x0000000d -#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT__SI__CI 0x0000000a -#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT__VI 0x0000000e -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT__SI__CI 0x00000011 -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT__VI 0x00000015 -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT__SI__CI 0x00000012 -#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT__VI 0x00000016 -#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT__VI 0x0000001b -#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT__VI 0x00000009 -#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT__VI 0x0000000a -#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT__VI 0x0000000c -#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT__SI__CI 0x00000013 -#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT__VI 0x00000017 -#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT__VI 0x0000001a -#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT__SI__CI 0x00000000 -#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT__VI 0x00000008 -#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT__VI 0x00000008 -#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT__VI 0x00000008 -#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT__VI 0x00000011 -#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT__VI 0x00000012 -#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT__VI 0x00000013 -#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT__VI 0x00000011 -#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT__VI 0x00000012 -#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT__VI 0x00000013 -#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT__VI 0x00000011 -#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT__VI 0x00000012 -#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT__VI 0x00000013 -#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_MCDS__BUS__SHIFT__VI 0x00000002 -#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT__VI 0x00000012 -#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_MCDT__BUS__SHIFT__VI 0x00000002 -#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT__VI 0x00000012 -#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_MCDU__BUS__SHIFT__VI 0x00000002 -#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT__VI 0x00000012 -#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_MCDV__BUS__SHIFT__VI 0x00000002 -#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT__VI 0x00000012 -#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT__VI 0x00000019 -#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT__SI__CI 0x00000007 -#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT__SI__CI 0x00000006 -#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT__VI 0x0000000a -#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT__SI__CI 0x00000005 -#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT__VI 0x00000009 -#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT__SI__CI 0x0000000a -#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT__VI 0x0000000e -#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT__SI__CI 0x00000009 -#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT__VI 0x0000000d -#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT__SI__CI 0x00000008 -#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT__VI 0x0000000c -#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT__VI 0x00000005 -#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT__VI 0x00000008 -#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT__SI__CI 0x0000000b -#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000011 -#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000011 -#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000011 -#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000011 -#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_BP2__RDRET__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT__VI 0x00000009 -#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT__VI 0x00000018 -#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT__VI 0x00000009 -#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT__VI 0x00000018 -#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT__VI 0x00000017 -#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT__VI 0x00000015 -#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT__VI 0x00000016 -#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT__VI 0x00000008 -#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT__VI 0x00000012 -#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT__VI 0x00000013 -#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT__VI 0x00000012 -#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT__VI 0x00000013 -#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT__VI 0x00000012 -#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT__VI 0x00000013 -#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT__VI 0x00000012 -#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT__VI 0x00000013 -#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT__VI 0x00000018 -#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_MCDS__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT__VI 0x0000000d -#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT__VI 0x00000002 -#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT__VI 0x00000018 -#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_MCDT__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT__VI 0x0000000d -#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT__VI 0x00000002 -#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT__VI 0x00000018 -#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_MCDU__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT__VI 0x0000000d -#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT__VI 0x00000002 -#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT__VI 0x00000018 -#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_MCDV__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT__VI 0x0000000d -#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT__VI 0x00000002 -#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT__SI__CI 0x00000007 -#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT__VI 0x00000013 -#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT__SI__CI 0x00000006 -#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT__VI 0x00000012 -#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT__SI__CI 0x00000005 -#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT__SI__CI 0x0000000a -#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT__VI 0x00000016 -#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT__SI__CI 0x00000009 -#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT__VI 0x00000015 -#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT__SI__CI 0x00000008 -#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT__VI 0x00000014 -#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT__VI 0x00000005 -#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT__VI 0x0000000d -#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT__VI 0x0000000e -#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT__VI 0x00000008 -#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT__VI 0x00000009 -#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT__VI 0x0000000a -#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT__VI 0x0000000c -#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_VCE0__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000011 -#define MC_HUB_WDP_VCE1__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT__VI 0x00000003 -#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WDP_VP8__ENABLE__SHIFT__VI 0x00000000 -#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT__VI 0x0000000b -#define MC_HUB_WDP_VP8__MAXBURST__SHIFT__VI 0x00000007 -#define MC_HUB_WDP_VP8__PRESCALE__SHIFT__VI 0x00000001 -#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT__VI 0x00000004 -#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT__VI 0x0000000f -#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT__VI 0x00000006 -#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT__VI 0x00000010 -#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT__VI 0x00000001 -#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT__VI 0x00000000 -#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT__VI 0x00000001 -#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT__VI 0x00000000 -#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT__VI 0x00000001 -#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT__VI 0x00000000 -#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT__VI 0x00000001 -#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT__VI 0x00000000 -#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT__VI 0x00000004 -#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT__VI 0x00000005 -#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT__VI 0x00000006 -#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT__VI 0x00000007 -#define MC_RD_GRP_GFX__ISP__SHIFT__VI 0x00000014 -#define MC_RD_GRP_GFX__VP8__SHIFT__VI 0x00000018 -#define MC_RD_GRP_GFX__XDMAM__SHIFT__VI 0x0000001c -#define MC_RD_GRP_OTH__SAMMSP__SHIFT__VI 0x0000001c -#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT__VI 0x00000006 -#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT__VI 0x00000001 -#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT__VI 0x00000005 -#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT__VI 0x00000004 -#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT__VI 0x00000000 -#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT__VI 0x00000003 -#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT__VI 0x00000000 -#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT__VI 0x00000018 -#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT__VI 0x00000010 -#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT__VI 0x00000001 -#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT__VI 0x00000008 -#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT__VI 0x00000004 -#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT__VI 0x00000003 -#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT__VI 0x00000000 -#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT__VI 0x0000001f -#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT__VI 0x00000004 -#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT__VI 0x00000003 -#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT__VI 0x0000000c -#define MC_SHARED_CHMAP__CHAN3__SHIFT__VI 0x00000010 -#define MC_SHARED_CHMAP__CHAN4__SHIFT__VI 0x00000014 -#define MC_SHARED_CHREMAP2__CHAN10__SHIFT__VI 0x00000008 -#define MC_SHARED_CHREMAP2__CHAN11__SHIFT__VI 0x0000000c -#define MC_SHARED_CHREMAP2__CHAN12__SHIFT__VI 0x00000010 -#define MC_SHARED_CHREMAP2__CHAN13__SHIFT__VI 0x00000014 -#define MC_SHARED_CHREMAP2__CHAN14__SHIFT__VI 0x00000018 -#define MC_SHARED_CHREMAP2__CHAN15__SHIFT__VI 0x0000001c -#define MC_SHARED_CHREMAP2__CHAN8__SHIFT__VI 0x00000000 -#define MC_SHARED_CHREMAP2__CHAN9__SHIFT__VI 0x00000004 -#define MC_SHARED_CHREMAP__CHAN1__SHIFT__SI__CI 0x00000003 -#define MC_SHARED_CHREMAP__CHAN1__SHIFT__VI 0x00000004 -#define MC_SHARED_CHREMAP__CHAN2__SHIFT__SI__CI 0x00000006 -#define MC_SHARED_CHREMAP__CHAN2__SHIFT__VI 0x00000008 -#define MC_SHARED_CHREMAP__CHAN3__SHIFT__SI__CI 0x00000009 -#define MC_SHARED_CHREMAP__CHAN3__SHIFT__VI 0x0000000c -#define MC_SHARED_CHREMAP__CHAN4__SHIFT__SI__CI 0x0000000c -#define MC_SHARED_CHREMAP__CHAN4__SHIFT__VI 0x00000010 -#define MC_SHARED_CHREMAP__CHAN5__SHIFT__SI__CI 0x0000000f -#define MC_SHARED_CHREMAP__CHAN5__SHIFT__VI 0x00000014 -#define MC_SHARED_CHREMAP__CHAN6__SHIFT__SI__CI 0x00000012 -#define MC_SHARED_CHREMAP__CHAN6__SHIFT__VI 0x00000018 -#define MC_SHARED_CHREMAP__CHAN7__SHIFT__SI__CI 0x00000015 -#define MC_SHARED_CHREMAP__CHAN7__SHIFT__VI 0x0000001c -#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT__VI 0x00000000 -#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT__VI 0x0000001f -#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT__VI 0x00000010 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT__VI 0x00000000 -#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT__VI 0x0000000c -#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT__VI 0x00000009 -#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT__VI 0x00000000 -#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT__VI 0x0000000f -#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT__VI 0x00000013 -#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT__VI 0x00000008 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT__VI 0x00000000 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT__VI 0x00000017 -#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT__VI 0x00000000 -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT__VI 0x00000000 -#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT__VI 0x00000003 -#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT__VI 0x00000017 -#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT__VI 0x0000001f -#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT__VI 0x00000000 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT__VI 0x00000017 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT__VI 0x00000000 -#define MC_WR_GRP_GFX__ISP__SHIFT__VI 0x00000010 -#define MC_WR_GRP_GFX__VP8__SHIFT__VI 0x00000014 -#define MC_WR_GRP_GFX__XDMAM__SHIFT__VI 0x0000001c -#define MC_WR_GRP_GFX__XDMA__SHIFT__VI 0x00000018 -#define MC_WR_GRP_SYS__SAMMSP__SHIFT__VI 0x0000000c -#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT__VI 0x00000003 -#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT__VI 0x00000004 -#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT__VI 0x0000001c -#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT__VI 0x00000018 -#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT__VI 0x00000000 -#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT__VI 0x0000001a -#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT__VI 0x0000000c -#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT__VI 0x00000008 -#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT__VI 0x00000010 -#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT__VI 0x00000000 -#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT__VI 0x00000000 -#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT__VI 0x00000008 -#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT__VI 0x00000010 -#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT__VI 0x00000018 -#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT__VI 0x00000000 -#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT__VI 0x00000008 -#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT__VI 0x00000010 -#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT__VI 0x00000018 -#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT__VI 0x00000000 -#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT__VI 0x00000000 -#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT__VI 0x00000000 -#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT__VI 0x00000000 -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_13__SHIFT__VI 0x0000000d -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_15__SHIFT__VI 0x0000000f -#define MLPSPAD_PINSTRAPS__MLPS_PINSTRAP_9__SHIFT__VI 0x00000009 -#define MP_FPS_CNT__FPS_CNT__SHIFT__VI 0x00000000 -#define MSI_MASK_64__MSI_MASK_64__SHIFT__VI 0x00000000 -#define MSI_MASK__MSI_MASK__SHIFT__VI 0x00000000 -#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT__VI 0x00000008 -#define MSI_PENDING_64__MSI_PENDING_64__SHIFT__VI 0x00000000 -#define MSI_PENDING__MSI_PENDING__SHIFT__VI 0x00000000 -#define ORB_IF_config__wait_for_xfer_done__SHIFT__VI 0x00000000 -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT__VI 0x0000001a -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT__VI 0x00000000 -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT__VI 0x00000001 -#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT__VI 0x00000004 -#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT__VI 0x00000005 -#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT__VI 0x00000006 -#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT__VI 0x00000007 -#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING__SHIFT__VI 0x00000003 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT__VI 0x00000000 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT__VI 0x00000001 -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT__VI 0x00000000 -#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT__VI 0x00000002 -#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT__VI 0x00000003 -#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT__VI 0x00000004 -#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT__VI 0x00000005 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT__VI 0x00000003 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT__VI 0x00000004 -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT__VI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT__VI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT__VI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT__VI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT__VI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT__VI 0x0000001c -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT__VI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT__VI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT__VI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT__VI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT__VI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT__VI 0x0000001c -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT__VI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT__VI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT__VI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT__VI 0x0000001c -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT__VI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT__VI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT__VI 0x00000002 -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT__VI 0x00000001 -#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT__VI 0x00000000 -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT__VI 0x00000010 -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT__VI 0x00000014 -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT__VI 0x00000018 -#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT__VI 0x0000001c -#define PB0_HW_DEBUG__HW_00_DEBUG__SHIFT__VI 0x00000000 -#define PB0_HW_DEBUG__HW_01_DEBUG__SHIFT__VI 0x00000001 -#define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT__VI 0x00000002 -#define PB0_HW_DEBUG__HW_03_DEBUG__SHIFT__VI 0x00000003 -#define PB0_HW_DEBUG__HW_04_DEBUG__SHIFT__VI 0x00000004 -#define PB0_HW_DEBUG__HW_05_DEBUG__SHIFT__VI 0x00000005 -#define PB0_HW_DEBUG__HW_06_DEBUG__SHIFT__VI 0x00000006 -#define PB0_HW_DEBUG__HW_07_DEBUG__SHIFT__VI 0x00000007 -#define PB0_HW_DEBUG__HW_08_DEBUG__SHIFT__VI 0x00000008 -#define PB0_HW_DEBUG__HW_09_DEBUG__SHIFT__VI 0x00000009 -#define PB0_HW_DEBUG__HW_10_DEBUG__SHIFT__VI 0x0000000a -#define PB0_HW_DEBUG__HW_11_DEBUG__SHIFT__VI 0x0000000b -#define PB0_HW_DEBUG__HW_12_DEBUG__SHIFT__VI 0x0000000c -#define PB0_HW_DEBUG__HW_13_DEBUG__SHIFT__VI 0x0000000d -#define PB0_HW_DEBUG__HW_14_DEBUG__SHIFT__VI 0x0000000e -#define PB0_HW_DEBUG__HW_15_DEBUG__SHIFT__VI 0x0000000f -#define PB0_HW_DEBUG__HW_16_DEBUG__SHIFT__VI 0x00000010 -#define PB0_HW_DEBUG__HW_17_DEBUG__SHIFT__VI 0x00000011 -#define PB0_HW_DEBUG__HW_18_DEBUG__SHIFT__VI 0x00000012 -#define PB0_HW_DEBUG__HW_19_DEBUG__SHIFT__VI 0x00000013 -#define PB0_HW_DEBUG__HW_20_DEBUG__SHIFT__VI 0x00000014 -#define PB0_HW_DEBUG__HW_21_DEBUG__SHIFT__VI 0x00000015 -#define PB0_HW_DEBUG__HW_22_DEBUG__SHIFT__VI 0x00000016 -#define PB0_HW_DEBUG__HW_23_DEBUG__SHIFT__VI 0x00000017 -#define PB0_HW_DEBUG__HW_24_DEBUG__SHIFT__VI 0x00000018 -#define PB0_HW_DEBUG__HW_25_DEBUG__SHIFT__VI 0x00000019 -#define PB0_HW_DEBUG__HW_26_DEBUG__SHIFT__VI 0x0000001a -#define PB0_HW_DEBUG__HW_27_DEBUG__SHIFT__VI 0x0000001b -#define PB0_HW_DEBUG__HW_28_DEBUG__SHIFT__VI 0x0000001c -#define PB0_HW_DEBUG__HW_29_DEBUG__SHIFT__VI 0x0000001d -#define PB0_HW_DEBUG__HW_30_DEBUG__SHIFT__VI 0x0000001e -#define PB0_HW_DEBUG__HW_31_DEBUG__SHIFT__VI 0x0000001f -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT__VI 0x00000010 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_10__SHIFT__VI 0x0000001a -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_11__SHIFT__VI 0x0000001b -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_12__SHIFT__VI 0x0000001c -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_13__SHIFT__VI 0x0000001d -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_14__SHIFT__VI 0x0000001e -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_15__SHIFT__VI 0x0000001f -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT__VI 0x00000011 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT__VI 0x00000012 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT__VI 0x00000013 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT__VI 0x00000014 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT__VI 0x00000015 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT__VI 0x00000016 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT__VI 0x00000017 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_8__SHIFT__VI 0x00000018 -#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_9__SHIFT__VI 0x00000019 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT__VI 0x00000000 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_10__SHIFT__VI 0x0000000a -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_11__SHIFT__VI 0x0000000b -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_12__SHIFT__VI 0x0000000c -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_13__SHIFT__VI 0x0000000d -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_14__SHIFT__VI 0x0000000e -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_15__SHIFT__VI 0x0000000f -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT__VI 0x00000001 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT__VI 0x00000002 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT__VI 0x00000003 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT__VI 0x00000004 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT__VI 0x00000005 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT__VI 0x00000006 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT__VI 0x00000007 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_8__SHIFT__VI 0x00000008 -#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_9__SHIFT__VI 0x00000009 -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT__VI 0x00000000 -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT__VI 0x00000005 -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT__VI 0x00000004 -#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT__VI 0x00000002 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT__VI 0x00000010 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_10__SHIFT__VI 0x0000001a -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_11__SHIFT__VI 0x0000001b -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_12__SHIFT__VI 0x0000001c -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_13__SHIFT__VI 0x0000001d -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_14__SHIFT__VI 0x0000001e -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_15__SHIFT__VI 0x0000001f -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT__VI 0x00000011 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT__VI 0x00000012 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT__VI 0x00000013 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT__VI 0x00000014 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT__VI 0x00000015 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT__VI 0x00000016 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT__VI 0x00000017 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_8__SHIFT__VI 0x00000018 -#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_9__SHIFT__VI 0x00000019 -#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT__VI 0x00000001 -#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT__VI 0x00000006 -#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT__VI 0x00000002 -#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT__VI 0x00000007 -#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT__VI 0x00000009 -#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT__VI 0x00000000 -#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT__VI 0x00000003 -#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT__VI 0x00000001 -#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT__VI 0x00000004 -#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT__VI 0x00000002 -#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT__VI 0x00000003 -#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT__VI 0x00000000 -#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT__VI 0x00000014 -#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT__VI 0x00000005 -#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT__VI 0x00000006 -#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT__VI 0x00000007 -#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT__VI 0x00000000 -#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT__VI 0x00000001 -#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT__VI 0x00000002 -#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT__VI 0x00000003 -#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT__VI 0x00000004 -#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT__VI 0x0000000a -#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT__VI 0x0000000b -#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT__VI 0x00000008 -#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT__VI 0x00000009 -#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT__VI 0x00000011 -#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT__VI 0x00000010 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT__VI 0x00000010 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT__VI 0x00000000 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_10__SHIFT__VI 0x0000000a -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_11__SHIFT__VI 0x0000000b -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_12__SHIFT__VI 0x0000000c -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_13__SHIFT__VI 0x0000000d -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_14__SHIFT__VI 0x0000000e -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_15__SHIFT__VI 0x0000000f -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT__VI 0x00000001 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT__VI 0x00000002 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT__VI 0x00000003 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT__VI 0x00000004 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT__VI 0x00000005 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT__VI 0x00000006 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT__VI 0x00000007 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_8__SHIFT__VI 0x00000008 -#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_9__SHIFT__VI 0x00000009 -#define PB0_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT__VI 0x00000000 -#define PB0_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT__VI 0x00000001 -#define PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT__VI 0x00000002 -#define PB0_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT__VI 0x00000003 -#define PB0_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT__VI 0x00000004 -#define PB0_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT__VI 0x00000005 -#define PB0_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT__VI 0x00000006 -#define PB0_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT__VI 0x00000007 -#define PB0_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT__VI 0x00000008 -#define PB0_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT__VI 0x00000009 -#define PB0_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT__VI 0x0000000a -#define PB0_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT__VI 0x0000000b -#define PB0_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT__VI 0x0000000c -#define PB0_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT__VI 0x0000000d -#define PB0_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT__VI 0x0000000e -#define PB0_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE0_OVRD2__RXPWR_0__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE0_OVRD2__TXPWR_0__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT__VI 0x00000004 -#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE1_OVRD2__RXPWR_1__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE1_OVRD2__TXPWR_1__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT__VI 0x00000004 -#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE2_OVRD2__RXPWR_2__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE2_OVRD2__TXPWR_2__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT__VI 0x00000004 -#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE3_OVRD2__RXPWR_3__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE3_OVRD2__TXPWR_3__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT__VI 0x00000004 -#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE4_OVRD2__RXPWR_4__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE4_OVRD2__TXPWR_4__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT__VI 0x00000004 -#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE5_OVRD2__RXPWR_5__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE5_OVRD2__TXPWR_5__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT__VI 0x00000004 -#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE6_OVRD2__RXPWR_6__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE6_OVRD2__TXPWR_6__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT__VI 0x00000004 -#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT__VI 0x00000018 -#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT__VI 0x0000001a -#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT__VI 0x00000012 -#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT__VI 0x00000013 -#define PB0_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT__VI 0x00000014 -#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT__VI 0x00000016 -#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT__VI 0x00000017 -#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT__VI 0x00000015 -#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE7_OVRD2__RXPWR_7__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE7_OVRD2__TXPWR_7__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT__VI 0x00000010 -#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT__VI 0x00000011 -#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT__VI 0x0000000e -#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT__VI 0x0000000f -#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT__VI 0x00000008 -#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT__VI 0x00000009 -#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT__VI 0x00000001 -#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT__VI 0x00000000 -#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT__VI 0x00000002 -#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT__VI 0x0000000a -#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT__VI 0x0000000c -#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT__VI 0x0000000d -#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT__VI 0x0000000b -#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT__VI 0x00000007 -#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT__VI 0x00000006 -#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT__VI 0x00000003 -#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT__VI 0x00000005 -#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT__VI 0x00000004 -#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT__VI 0x00000018 -#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT__VI 0x00000011 -#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT__VI 0x00000015 -#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT__VI 0x00000013 -#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT__VI 0x00000010 -#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT__VI 0x00000006 -#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT__VI 0x00000019 -#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT__VI 0x0000001b -#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT__VI 0x00000000 -#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT__VI 0x00000003 -#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT__VI 0x00000017 -#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT__VI 0x00000018 -#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT__VI 0x00000015 -#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT__VI 0x00000009 -#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT__VI 0x0000000f -#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT__VI 0x00000006 -#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT__VI 0x00000012 -#define PB0_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT__VI 0x00000000 -#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT__VI 0x00000003 -#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT__VI 0x00000016 -#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT__VI 0x0000000c -#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT__VI 0x00000019 -#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT__VI 0x00000005 -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT__VI 0x0000000c -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT__VI 0x0000000d -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT__VI 0x0000000e -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT__VI 0x0000000f -#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT__VI 0x00000010 -#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT__VI 0x00000006 -#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT__VI 0x0000000a -#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT__VI 0x0000000b -#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT__VI 0x00000008 -#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT__VI 0x00000002 -#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT__VI 0x00000004 -#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT__VI 0x00000001 -#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT__VI 0x00000003 -#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT__VI 0x00000006 -#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT__VI 0x00000019 -#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT__VI 0x00000015 -#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT__VI 0x00000011 -#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT__VI 0x00000010 -#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT__VI 0x0000001a -#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT__VI 0x00000016 -#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT__VI 0x00000000 -#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT__VI 0x00000003 -#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT__VI 0x00000015 -#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT__VI 0x00000009 -#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT__VI 0x0000000f -#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT__VI 0x00000006 -#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT__VI 0x00000012 -#define PB0_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT__VI 0x00000000 -#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT__VI 0x00000003 -#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT__VI 0x00000016 -#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT__VI 0x0000000c -#define PB0_PIF_TX_CTRL__TX_PWR_GATING_IN_L1__SHIFT__VI 0x00000017 -#define PB0_PIF_TX_CTRL__TX_PWR_GATING_IN_UNUSED__SHIFT__VI 0x00000018 -#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT__VI 0x00000008 -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT__VI 0x00000008 -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT__VI 0x00000008 -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT__VI 0x00000008 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT__VI 0x00000011 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT__VI 0x00000012 -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT__VI 0x0000000f -#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT__VI 0x00000010 -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT__VI 0x00000003 -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT__VI 0x00000005 -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT__VI 0x00000007 -#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT__VI 0x00000009 -#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT__VI 0x0000000c -#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT__VI 0x0000000e -#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT__VI 0x00000010 -#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT__VI 0x0000001f -#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT__VI 0x0000001c -#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT__VI 0x0000001d -#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT__VI 0x0000000e -#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT__VI 0x00000011 -#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT__VI 0x00000010 -#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT__VI 0x00000000 -#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT__VI 0x00000002 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT__VI 0x00000004 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT__VI 0x00000007 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT__VI 0x00000005 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT__VI 0x00000006 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT__VI 0x0000000c -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT__VI 0x0000000f -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT__VI 0x0000000d -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT__VI 0x0000000e -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT__VI 0x00000010 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT__VI 0x00000013 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT__VI 0x00000011 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT__VI 0x00000012 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT__VI 0x00000008 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT__VI 0x0000000b -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT__VI 0x00000009 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT__VI 0x0000000a -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT__VI 0x00000014 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT__VI 0x00000017 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT__VI 0x00000015 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT__VI 0x00000016 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT__VI 0x00000003 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT__VI 0x00000006 -#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT__VI 0x0000000a -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT__VI 0x00000006 -#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT__VI 0x0000000a -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT__VI 0x00000006 -#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT__VI 0x0000000a -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT__VI 0x00000006 -#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT__VI 0x0000000a -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT__VI 0x00000006 -#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT__VI 0x0000000a -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT__VI 0x00000006 -#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT__VI 0x0000000a -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT__VI 0x00000006 -#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT__VI 0x0000000a -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT__VI 0x00000006 -#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT__VI 0x0000000a -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT__VI 0x00000006 -#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT__VI 0x0000000a -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT__VI 0x00000006 -#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT__VI 0x0000000a -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT__VI 0x00000006 -#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT__VI 0x0000000a -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT__VI 0x00000006 -#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT__VI 0x0000000a -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT__VI 0x00000006 -#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT__VI 0x0000000a -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT__VI 0x00000006 -#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT__VI 0x0000000a -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT__VI 0x00000006 -#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT__VI 0x0000000a -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT__VI 0x00000006 -#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT__VI 0x0000000a -#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT__VI 0x00000004 -#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT__VI 0x00000001 -#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT__VI 0x00000007 -#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT__VI 0x0000000b -#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_PWRON_IN_RAMPDOWN__SHIFT__VI 0x0000000d -#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT__VI 0x0000000a -#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT__VI 0x00000005 -#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT__VI 0x00000003 -#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT__VI 0x00000008 -#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT__VI 0x00000007 -#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT__VI 0x00000002 -#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT__VI 0x0000001c -#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT__VI 0x0000001d -#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT__VI 0x0000001e -#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT__VI 0x00000005 -#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT__VI 0x00000009 -#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT__VI 0x0000000b -#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT__VI 0x00000018 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT__VI 0x00000008 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT__VI 0x0000000b -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT__VI 0x00000009 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT__VI 0x0000000a -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT__VI 0x0000000c -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT__VI 0x0000000f -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT__VI 0x0000000d -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT__VI 0x0000000e -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT__VI 0x00000003 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT__VI 0x00000002 -#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT__VI 0x00000003 -#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT__VI 0x00000004 -#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT__VI 0x00000005 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT__VI 0x00000003 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT__VI 0x00000004 -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT__VI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT__VI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT__VI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT__VI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT__VI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT__VI 0x0000001c -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT__VI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT__VI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT__VI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT__VI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT__VI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT__VI 0x0000001c -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT__VI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT__VI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT__VI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT__VI 0x0000001c -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT__VI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT__VI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT__VI 0x00000002 -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT__VI 0x00000001 -#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT__VI 0x00000000 -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT__VI 0x00000010 -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT__VI 0x00000014 -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT__VI 0x00000018 -#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT__VI 0x0000001c -#define PB1_HW_DEBUG__HW_00_DEBUG__SHIFT__VI 0x00000000 -#define PB1_HW_DEBUG__HW_01_DEBUG__SHIFT__VI 0x00000001 -#define PB1_HW_DEBUG__HW_02_DEBUG__SHIFT__VI 0x00000002 -#define PB1_HW_DEBUG__HW_03_DEBUG__SHIFT__VI 0x00000003 -#define PB1_HW_DEBUG__HW_04_DEBUG__SHIFT__VI 0x00000004 -#define PB1_HW_DEBUG__HW_05_DEBUG__SHIFT__VI 0x00000005 -#define PB1_HW_DEBUG__HW_06_DEBUG__SHIFT__VI 0x00000006 -#define PB1_HW_DEBUG__HW_07_DEBUG__SHIFT__VI 0x00000007 -#define PB1_HW_DEBUG__HW_08_DEBUG__SHIFT__VI 0x00000008 -#define PB1_HW_DEBUG__HW_09_DEBUG__SHIFT__VI 0x00000009 -#define PB1_HW_DEBUG__HW_10_DEBUG__SHIFT__VI 0x0000000a -#define PB1_HW_DEBUG__HW_11_DEBUG__SHIFT__VI 0x0000000b -#define PB1_HW_DEBUG__HW_12_DEBUG__SHIFT__VI 0x0000000c -#define PB1_HW_DEBUG__HW_13_DEBUG__SHIFT__VI 0x0000000d -#define PB1_HW_DEBUG__HW_14_DEBUG__SHIFT__VI 0x0000000e -#define PB1_HW_DEBUG__HW_15_DEBUG__SHIFT__VI 0x0000000f -#define PB1_HW_DEBUG__HW_16_DEBUG__SHIFT__VI 0x00000010 -#define PB1_HW_DEBUG__HW_17_DEBUG__SHIFT__VI 0x00000011 -#define PB1_HW_DEBUG__HW_18_DEBUG__SHIFT__VI 0x00000012 -#define PB1_HW_DEBUG__HW_19_DEBUG__SHIFT__VI 0x00000013 -#define PB1_HW_DEBUG__HW_20_DEBUG__SHIFT__VI 0x00000014 -#define PB1_HW_DEBUG__HW_21_DEBUG__SHIFT__VI 0x00000015 -#define PB1_HW_DEBUG__HW_22_DEBUG__SHIFT__VI 0x00000016 -#define PB1_HW_DEBUG__HW_23_DEBUG__SHIFT__VI 0x00000017 -#define PB1_HW_DEBUG__HW_24_DEBUG__SHIFT__VI 0x00000018 -#define PB1_HW_DEBUG__HW_25_DEBUG__SHIFT__VI 0x00000019 -#define PB1_HW_DEBUG__HW_26_DEBUG__SHIFT__VI 0x0000001a -#define PB1_HW_DEBUG__HW_27_DEBUG__SHIFT__VI 0x0000001b -#define PB1_HW_DEBUG__HW_28_DEBUG__SHIFT__VI 0x0000001c -#define PB1_HW_DEBUG__HW_29_DEBUG__SHIFT__VI 0x0000001d -#define PB1_HW_DEBUG__HW_30_DEBUG__SHIFT__VI 0x0000001e -#define PB1_HW_DEBUG__HW_31_DEBUG__SHIFT__VI 0x0000001f -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT__VI 0x00000010 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_10__SHIFT__VI 0x0000001a -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_11__SHIFT__VI 0x0000001b -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_12__SHIFT__VI 0x0000001c -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_13__SHIFT__VI 0x0000001d -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_14__SHIFT__VI 0x0000001e -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_15__SHIFT__VI 0x0000001f -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT__VI 0x00000011 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT__VI 0x00000012 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT__VI 0x00000013 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT__VI 0x00000014 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT__VI 0x00000015 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT__VI 0x00000016 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT__VI 0x00000017 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_8__SHIFT__VI 0x00000018 -#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_9__SHIFT__VI 0x00000019 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT__VI 0x00000000 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_10__SHIFT__VI 0x0000000a -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_11__SHIFT__VI 0x0000000b -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_12__SHIFT__VI 0x0000000c -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_13__SHIFT__VI 0x0000000d -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_14__SHIFT__VI 0x0000000e -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_15__SHIFT__VI 0x0000000f -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT__VI 0x00000001 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT__VI 0x00000002 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT__VI 0x00000003 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT__VI 0x00000004 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT__VI 0x00000005 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT__VI 0x00000006 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT__VI 0x00000007 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_8__SHIFT__VI 0x00000008 -#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_9__SHIFT__VI 0x00000009 -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT__VI 0x00000000 -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT__VI 0x00000005 -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT__VI 0x00000004 -#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT__VI 0x00000002 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT__VI 0x00000010 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_10__SHIFT__VI 0x0000001a -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_11__SHIFT__VI 0x0000001b -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_12__SHIFT__VI 0x0000001c -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_13__SHIFT__VI 0x0000001d -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_14__SHIFT__VI 0x0000001e -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_15__SHIFT__VI 0x0000001f -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT__VI 0x00000011 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT__VI 0x00000012 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT__VI 0x00000013 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT__VI 0x00000014 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT__VI 0x00000015 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT__VI 0x00000016 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT__VI 0x00000017 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_8__SHIFT__VI 0x00000018 -#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_9__SHIFT__VI 0x00000019 -#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT__VI 0x00000001 -#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT__VI 0x00000006 -#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT__VI 0x00000002 -#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT__VI 0x00000007 -#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT__VI 0x00000009 -#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT__VI 0x00000000 -#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT__VI 0x00000003 -#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT__VI 0x00000001 -#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT__VI 0x00000004 -#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT__VI 0x00000002 -#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT__VI 0x00000003 -#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT__VI 0x00000000 -#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT__VI 0x00000014 -#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT__VI 0x00000005 -#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT__VI 0x00000006 -#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT__VI 0x00000007 -#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT__VI 0x00000000 -#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT__VI 0x00000001 -#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT__VI 0x00000002 -#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT__VI 0x00000003 -#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT__VI 0x00000004 -#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT__VI 0x0000000a -#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT__VI 0x0000000b -#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT__VI 0x00000008 -#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT__VI 0x00000009 -#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT__VI 0x00000011 -#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT__VI 0x00000010 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT__VI 0x00000010 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT__VI 0x00000000 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_10__SHIFT__VI 0x0000000a -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_11__SHIFT__VI 0x0000000b -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_12__SHIFT__VI 0x0000000c -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_13__SHIFT__VI 0x0000000d -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_14__SHIFT__VI 0x0000000e -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_15__SHIFT__VI 0x0000000f -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT__VI 0x00000001 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT__VI 0x00000002 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT__VI 0x00000003 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT__VI 0x00000004 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT__VI 0x00000005 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT__VI 0x00000006 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT__VI 0x00000007 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_8__SHIFT__VI 0x00000008 -#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_9__SHIFT__VI 0x00000009 -#define PB1_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT__VI 0x00000000 -#define PB1_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT__VI 0x00000001 -#define PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT__VI 0x00000002 -#define PB1_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT__VI 0x00000003 -#define PB1_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT__VI 0x00000004 -#define PB1_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT__VI 0x00000005 -#define PB1_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT__VI 0x00000006 -#define PB1_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT__VI 0x00000007 -#define PB1_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT__VI 0x00000008 -#define PB1_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT__VI 0x00000009 -#define PB1_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT__VI 0x0000000a -#define PB1_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT__VI 0x0000000b -#define PB1_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT__VI 0x0000000c -#define PB1_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT__VI 0x0000000d -#define PB1_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT__VI 0x0000000e -#define PB1_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE0_OVRD2__RXPWR_0__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE0_OVRD2__TXPWR_0__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT__VI 0x00000004 -#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE1_OVRD2__RXPWR_1__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE1_OVRD2__TXPWR_1__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT__VI 0x00000004 -#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE2_OVRD2__RXPWR_2__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE2_OVRD2__TXPWR_2__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT__VI 0x00000004 -#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE3_OVRD2__RXPWR_3__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE3_OVRD2__TXPWR_3__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT__VI 0x00000004 -#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE4_OVRD2__RXPWR_4__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE4_OVRD2__TXPWR_4__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT__VI 0x00000004 -#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE5_OVRD2__RXPWR_5__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE5_OVRD2__TXPWR_5__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT__VI 0x00000004 -#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE6_OVRD2__RXPWR_6__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE6_OVRD2__TXPWR_6__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT__VI 0x00000004 -#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT__VI 0x00000018 -#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT__VI 0x0000001a -#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT__VI 0x00000012 -#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT__VI 0x00000013 -#define PB1_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT__VI 0x00000014 -#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT__VI 0x00000016 -#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT__VI 0x00000017 -#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT__VI 0x00000015 -#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE7_OVRD2__RXPWR_7__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE7_OVRD2__TXPWR_7__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT__VI 0x00000010 -#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT__VI 0x00000011 -#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT__VI 0x0000000e -#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT__VI 0x0000000f -#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT__VI 0x00000008 -#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT__VI 0x00000009 -#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT__VI 0x00000001 -#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT__VI 0x00000000 -#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT__VI 0x00000002 -#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT__VI 0x0000000a -#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT__VI 0x0000000c -#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT__VI 0x0000000d -#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT__VI 0x0000000b -#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT__VI 0x00000007 -#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT__VI 0x00000006 -#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT__VI 0x00000003 -#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT__VI 0x00000005 -#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT__VI 0x00000004 -#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT__VI 0x00000018 -#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT__VI 0x00000011 -#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT__VI 0x00000015 -#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT__VI 0x00000013 -#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT__VI 0x00000010 -#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT__VI 0x00000006 -#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT__VI 0x00000019 -#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT__VI 0x0000001b -#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT__VI 0x00000000 -#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT__VI 0x00000003 -#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT__VI 0x00000017 -#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT__VI 0x00000018 -#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT__VI 0x00000015 -#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT__VI 0x00000009 -#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT__VI 0x0000000f -#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT__VI 0x00000006 -#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT__VI 0x00000012 -#define PB1_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT__VI 0x00000000 -#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT__VI 0x00000003 -#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT__VI 0x00000016 -#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT__VI 0x0000000c -#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT__VI 0x00000019 -#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT__VI 0x00000005 -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT__VI 0x0000000c -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT__VI 0x0000000d -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT__VI 0x0000000e -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT__VI 0x0000000f -#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT__VI 0x00000010 -#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT__VI 0x00000006 -#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT__VI 0x0000000a -#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT__VI 0x0000000b -#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT__VI 0x00000008 -#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT__VI 0x00000002 -#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT__VI 0x00000004 -#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT__VI 0x00000001 -#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT__VI 0x00000003 -#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT__VI 0x00000006 -#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT__VI 0x00000019 -#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT__VI 0x00000015 -#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT__VI 0x00000011 -#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT__VI 0x00000010 -#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT__VI 0x0000001a -#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT__VI 0x00000016 -#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT__VI 0x00000000 -#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT__VI 0x00000003 -#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT__VI 0x00000015 -#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT__VI 0x00000009 -#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT__VI 0x0000000f -#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT__VI 0x00000006 -#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT__VI 0x00000012 -#define PB1_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT__VI 0x00000000 -#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT__VI 0x00000003 -#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT__VI 0x00000016 -#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT__VI 0x0000000c -#define PB1_PIF_TX_CTRL__TX_PWR_GATING_IN_L1__SHIFT__VI 0x00000017 -#define PB1_PIF_TX_CTRL__TX_PWR_GATING_IN_UNUSED__SHIFT__VI 0x00000018 -#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT__VI 0x00000008 -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT__VI 0x00000008 -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT__VI 0x00000008 -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT__VI 0x00000001 -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT__VI 0x00000000 -#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT__VI 0x00000008 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT__VI 0x00000011 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT__VI 0x00000012 -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT__VI 0x0000000f -#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT__VI 0x00000010 -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT__VI 0x00000003 -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT__VI 0x00000005 -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT__VI 0x00000007 -#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT__VI 0x00000009 -#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT__VI 0x0000000c -#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT__VI 0x0000000e -#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT__VI 0x00000010 -#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT__VI 0x0000001f -#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT__VI 0x0000001c -#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT__VI 0x0000001d -#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT__VI 0x0000000e -#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT__VI 0x00000011 -#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT__VI 0x00000010 -#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT__VI 0x00000000 -#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT__VI 0x00000002 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT__VI 0x00000004 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT__VI 0x00000007 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT__VI 0x00000005 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT__VI 0x00000006 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT__VI 0x0000000c -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT__VI 0x0000000f -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT__VI 0x0000000d -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT__VI 0x0000000e -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT__VI 0x00000010 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT__VI 0x00000013 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT__VI 0x00000011 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT__VI 0x00000012 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT__VI 0x00000008 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT__VI 0x0000000b -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT__VI 0x00000009 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT__VI 0x0000000a -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT__VI 0x00000014 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT__VI 0x00000017 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT__VI 0x00000015 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT__VI 0x00000016 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT__VI 0x00000003 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT__VI 0x00000006 -#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT__VI 0x0000000a -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT__VI 0x00000006 -#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT__VI 0x0000000a -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT__VI 0x00000006 -#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT__VI 0x0000000a -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT__VI 0x00000006 -#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT__VI 0x0000000a -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT__VI 0x00000006 -#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT__VI 0x0000000a -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT__VI 0x00000006 -#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT__VI 0x0000000a -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT__VI 0x00000006 -#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT__VI 0x0000000a -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT__VI 0x00000006 -#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT__VI 0x0000000a -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT__VI 0x00000006 -#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT__VI 0x0000000a -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT__VI 0x00000006 -#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT__VI 0x0000000a -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT__VI 0x00000006 -#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT__VI 0x0000000a -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT__VI 0x00000006 -#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT__VI 0x0000000a -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT__VI 0x00000006 -#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT__VI 0x0000000a -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT__VI 0x00000006 -#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT__VI 0x0000000a -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT__VI 0x00000006 -#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT__VI 0x0000000a -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT__VI 0x00000006 -#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT__VI 0x0000000a -#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT__VI 0x00000004 -#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT__VI 0x00000001 -#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT__VI 0x00000007 -#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT__VI 0x0000000b -#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_PWRON_IN_RAMPDOWN__SHIFT__VI 0x0000000d -#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT__VI 0x0000000a -#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT__VI 0x00000005 -#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT__VI 0x00000003 -#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT__VI 0x00000008 -#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT__VI 0x00000007 -#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT__VI 0x00000002 -#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT__VI 0x0000001c -#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT__VI 0x0000001d -#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT__VI 0x0000001e -#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT__VI 0x00000005 -#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT__VI 0x00000009 -#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT__VI 0x0000000b -#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT__VI 0x00000018 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT__VI 0x00000008 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT__VI 0x0000000b -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT__VI 0x00000009 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT__VI 0x0000000a -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT__VI 0x0000000c -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT__VI 0x0000000f -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT__VI 0x0000000d -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT__VI 0x0000000e -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT__VI 0x00000000 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT__VI 0x00000003 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT__VI 0x00000001 -#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT__VI 0x00000002 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT__VI 0x00000010 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT__VI 0x0000000e -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT__VI 0x00000006 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT__VI 0x00000004 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT__VI 0x00000016 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT__VI 0x0000000c -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT__VI 0x00000002 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT__VI 0x00000014 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT__VI 0x00000000 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT__VI 0x0000000a -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT__VI 0x00000008 -#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT__VI 0x00000012 -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT__VI 0x00000004 -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT__VI 0x00000006 -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT__VI 0x00000010 -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT__VI 0x00000012 -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT__VI 0x0000000a -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT__VI 0x00000000 -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT__VI 0x0000000c -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT__VI 0x00000002 -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT__VI 0x0000000e -#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT__VI 0x00000008 -#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT__VI 0x00000000 -#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT__VI 0x0000000b -#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT__VI 0x00000001 -#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT__VI 0x00000000 -#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT__VI 0x00000008 -#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT__VI 0x00000001 -#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT__VI 0x00000004 -#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT__VI 0x00000000 -#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT__VI 0x00000000 -#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT__VI 0x00000010 -#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT__VI 0x00000014 -#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT__VI 0x00000006 -#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT__VI 0x0000001e -#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT__VI 0x0000001f -#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT__VI 0x0000001d -#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT__VI 0x0000000d -#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT__VI 0x0000000e -#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT__VI 0x0000000b -#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT__VI 0x0000000c -#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT__VI 0x00000014 -#define PCIE_EFUSE2__PCIE_EFUSE2__SHIFT__VI 0x00000000 -#define PCIE_EFUSE3__PCIE_EFUSE3__SHIFT__VI 0x00000000 -#define PCIE_EFUSE4__PCIE_EFUSE4__SHIFT__VI 0x00000000 -#define PCIE_EFUSE5__PCIE_EFUSE5__SHIFT__VI 0x00000000 -#define PCIE_EFUSE__PCIE_EFUSE__SHIFT__VI 0x00000000 -#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT__VI 0x00000011 -#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT__VI 0x00000012 -#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT__VI 0x00000008 -#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT__VI 0x00000000 -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT__VI 0x0000000a -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT__VI 0x00000016 -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT__VI 0x00000010 -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT__VI 0x00000004 -#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT__VI 0x00000000 -#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT__VI 0x00000019 -#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT__VI 0x00000003 -#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT__VI 0x00000002 -#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT__VI 0x0000000a -#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT__VI 0x0000001a -#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT__VI 0x00000018 -#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT__VI 0x00000000 -#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT__VI 0x00000002 -#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT__VI 0x00000004 -#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT__VI 0x00000013 -#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT__VI 0x00000014 -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT__VI 0x00000000 -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT__VI 0x00000007 -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT__VI 0x0000000d -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT__VI 0x00000001 -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT__VI 0x00000013 -#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT__VI 0x00000019 -#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT__VI 0x00000018 -#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT__VI 0x0000001e -#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT__VI 0x0000000f -#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT__VI 0x0000001d -#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT__VI 0x0000000e -#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT__VI 0x0000001a -#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT__VI 0x00000010 -#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT__VI 0x0000000a -#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT__VI 0x00000000 -#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT__VI 0x00000000 -#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT__VI 0x00000010 -#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT__VI 0x00000014 -#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT__VI 0x0000000c -#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT__VI 0x00000000 -#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT__VI 0x00000000 -#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT__VI 0x00000000 -#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT__VI 0x00000000 -#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT__VI 0x00000000 -#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT__VI 0x00000000 -#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT__VI 0x0000000f -#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT__VI 0x00000000 -#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT__VI 0x00000008 -#define PCIE_MC_CNTL__MC_ENABLE__SHIFT__VI 0x0000000f -#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT__VI 0x00000000 -#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT__VI 0x00000000 -#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT__VI 0x00000010 -#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT__VI 0x00000014 -#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT__VI 0x00000000 -#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT__VI 0x00000000 -#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT__VI 0x00000013 -#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT__VI 0x00000012 -#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT__VI 0x00000011 -#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT__VI 0x00000002 -#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT__VI 0x00000010 -#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT__VI 0x00000014 -#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT__VI 0x00000000 -#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT__VI 0x00000003 -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT__VI 0x00000004 -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT__VI 0x00000008 -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT__VI 0x0000000c -#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT__VI 0x00000001 -#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT__VI 0x0000000f -#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT__SI__CI 0x00000004 -#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT__VI 0x00000005 -#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT__SI__CI 0x00000005 -#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT__VI 0x00000006 -#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT__SI__CI 0x00000007 -#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT__VI 0x00000008 -#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT__SI__CI 0x00000003 -#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT__VI 0x00000004 -#define PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT__VI 0x00000010 -#define PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT__VI 0x00000000 -#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT__VI 0x00000008 -#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT__VI 0x00000010 -#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT__VI 0x00000009 -#define PCIE_RX_CNTL__RX_TPH_DIS__SHIFT__VI 0x0000001a -#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT__VI 0x00000001 -#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT__VI 0x00000015 -#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT__VI 0x00000004 -#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT__VI 0x00000001 -#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT__VI 0x00000002 -#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT__VI 0x00000003 -#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT__VI 0x00000010 -#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT__VI 0x00000014 -#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT__VI 0x00000000 -#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT__VI \ - 0x00000000 -#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT__VI 0x00000000 -#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT__VI 0x00000013 -#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT__VI 0x00000012 -#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT__VI 0x00000014 -#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT__VI 0x0000000f -#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT__VI 0x0000000d -#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT__VI 0x0000000e -#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT__VI 0x00000011 -#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT__VI 0x00000015 -#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT__VI 0x0000001b -#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT__VI 0x00000010 -#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT__VI 0x00000018 -#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT__VI 0x00000013 -#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT__VI 0x00000012 -#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT__VI 0x00000014 -#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT__VI 0x0000000f -#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT__VI 0x0000000d -#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT__VI 0x0000000e -#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT__VI 0x00000015 -#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT__VI 0x0000001b -#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT__VI 0x00000010 -#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT__VI 0x00000013 -#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT__VI 0x00000012 -#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT__VI 0x00000014 -#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT__VI 0x0000000f -#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT__VI 0x0000000d -#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT__VI 0x0000000e -#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT__VI 0x00000015 -#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT__VI 0x0000001b -#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT__VI 0x00000010 -#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT__VI 0x0000001f -#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT__VI 0x00000002 -#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT__VI 0x00000008 -#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT__VI 0x00000001 -#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT__VI 0x00000000 -#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT__VI 0x00000009 -#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT__VI 0x00000010 -#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT__VI 0x00000008 -#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT__VI 0x00000000 -#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT__VI 0x00000000 -#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT__VI 0x00000010 -#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT__VI 0x00000014 -#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT__VI 0x0000000e -#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT__VI 0x0000000a -#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT__VI 0x0000000d -#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT__VI 0x00000007 -#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT__VI 0x0000000f -#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT__VI 0x00000003 -#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT__VI 0x00000006 -#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT__VI 0x00000000 -#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT__VI 0x00000010 -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT__VI 0x00000000 -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT__VI 0x00000010 -#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT__VI 0x00000014 -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT__VI 0x00000000 -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT__VI 0x00000000 -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT__VI 0x00000014 -#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT__VI 0x00000010 -#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT__VI 0x00000000 -#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT__VI 0x00000001 -#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT__VI 0x00000002 -#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT__VI 0x00000008 -#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT__VI 0x00000007 -#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT__VI 0x00000004 -#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT__VI 0x00000000 -#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT__VI 0x00000000 -#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT__VI 0x00000000 -#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT__VI 0x00000000 -#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT__VI 0x00000000 -#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT__VI 0x00000001 -#define PWR_OBSRV_CNTL__NONCLK_OBSRV_SEL1__SHIFT__VI 0x00000000 -#define PWR_OBSRV_CNTL__NONCLK_OBSRV_SEL2__SHIFT__VI 0x00000008 -#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT__VI 0x00000000 -#define RCU_SYSRESET__ACP_hard_resetb__SHIFT__VI 0x0000001b -#define RCU_SYSRESET__DC_az_hard_resetb__SHIFT__VI 0x00000012 -#define RCU_SYSRESET__IOMMU_hard_resetb__SHIFT__VI 0x0000001c -#define RCU_SYSRESET__UVD_hard_resetb__SHIFT__VI 0x00000018 -#define RCU_SYSRESET__VCE_hard_resetb__SHIFT__VI 0x00000019 -#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT__VI 0x00000000 -#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT__VI 0x00000000 -#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT__VI 0x00000000 -#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT__VI 0x00000000 -#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT__VI 0x00000002 -#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT__VI 0x00000002 -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT__VI 0x0000001f -#define RLC_CLK_CNTL__RESERVED__SHIFT__VI 0x00000002 -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT__VI 0x00000001 -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT__VI 0x00000000 -#define RLC_CP_RESPONSE0__RESPONSE__SHIFT__VI 0x00000000 -#define RLC_CP_RESPONSE1__RESPONSE__SHIFT__VI 0x00000000 -#define RLC_CP_RESPONSE2__RESPONSE__SHIFT__VI 0x00000000 -#define RLC_CP_RESPONSE3__RESPONSE__SHIFT__VI 0x00000000 -#define RLC_CP_SCHEDULERS__scheduler0__SHIFT__VI 0x00000000 -#define RLC_CP_SCHEDULERS__scheduler1__SHIFT__VI 0x00000008 -#define RLC_CP_SCHEDULERS__scheduler2__SHIFT__VI 0x00000010 -#define RLC_CP_SCHEDULERS__scheduler3__SHIFT__VI 0x00000018 -#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_CSIB_LENGTH__LENGTH__SHIFT__VI 0x00000000 -#define RLC_DEBE_0__SE0_SH0_CU_CONFIG__SHIFT__VI 0x00000000 -#define RLC_DEBE_0__SE1_SH0_CU_CONFIG__SHIFT__VI 0x0000000c -#define RLC_DEBE_0__SE2_SH0_CU_CONFIG_PART_1__SHIFT__VI 0x00000018 -#define RLC_DEBE_1__SE2_SH0_CU_CONFIG_PART_2__SHIFT__VI 0x00000000 -#define RLC_DEBE_1__SE3_SH0_CU_CONFIG__SHIFT__VI 0x00000004 -#define RLC_DEBE_1__TCC_CONFIG__SHIFT__VI 0x00000010 -#define RLC_DEBE_2__DCE_CONFIG__SHIFT__VI 0x0000001a -#define RLC_DEBE_2__PRIM_CONFIG__SHIFT__VI 0x00000014 -#define RLC_DEBE_2__SE0_RB_CONFIG__SHIFT__VI 0x00000000 -#define RLC_DEBE_2__SE1_RB_CONFIG__SHIFT__VI 0x00000004 -#define RLC_DEBE_2__SE2_RB_CONFIG__SHIFT__VI 0x00000008 -#define RLC_DEBE_2__SE3_RB_CONFIG__SHIFT__VI 0x0000000c -#define RLC_DEBE_2__SPARE_RB_CONFIG__SHIFT__VI 0x00000010 -#define RLC_DEBE_3__ACP_CONFIG__SHIFT__VI 0x00000003 -#define RLC_DEBE_3__RESERVED__SHIFT__VI 0x00000007 -#define RLC_DEBE_3__UVD_CONFIG__SHIFT__VI 0x00000000 -#define RLC_DEBE_3__VCE_CONFIG__SHIFT__VI 0x00000001 -#define RLC_DEBE_WRITE_DIS__ACP_WRITE_DIS__SHIFT__VI 0x00000007 -#define RLC_DEBE_WRITE_DIS__CU_WRITE_DIS__SHIFT__VI 0x00000000 -#define RLC_DEBE_WRITE_DIS__DCE_WRITE_DIS__SHIFT__VI 0x00000004 -#define RLC_DEBE_WRITE_DIS__PRIM_WRITE_DIS__SHIFT__VI 0x00000003 -#define RLC_DEBE_WRITE_DIS__RB_WRITE_DIS__SHIFT__VI 0x00000002 -#define RLC_DEBE_WRITE_DIS__RESERVED__SHIFT__VI 0x00000008 -#define RLC_DEBE_WRITE_DIS__TCC_WRITE_DIS__SHIFT__VI 0x00000001 -#define RLC_DEBE_WRITE_DIS__UVD_WRITE_DIS__SHIFT__VI 0x00000005 -#define RLC_DEBE_WRITE_DIS__VCE_WRITE_DIS__SHIFT__VI 0x00000006 -#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT__VI 0x00000008 -#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT__VI 0x0000000a -#define RLC_GPM_GENERAL_10__DATA__SHIFT__VI 0x00000000 -#define RLC_GPM_GENERAL_11__DATA__SHIFT__VI 0x00000000 -#define RLC_GPM_GENERAL_12__DATA__SHIFT__VI 0x00000000 -#define RLC_GPM_GENERAL_8__DATA__SHIFT__VI 0x00000000 -#define RLC_GPM_GENERAL_9__DATA__SHIFT__VI 0x00000000 -#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT__VI 0x00000000 -#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT__VI 0x00000000 -#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT__VI 0x00000000 -#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT__VI 0x00000000 -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT__VI 0x00000011 -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT__VI 0x0000000c -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT__VI 0x00000008 -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT__VI 0x00000006 -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT__VI 0x00000005 -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT__VI 0x00000010 -#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT__VI 0x0000000f -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT__VI 0x0000000b -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT__VI 0x00000007 -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT__VI 0x00000004 -#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT__VI 0x00000018 -#define RLC_GPM_STAT__RESERVED__SHIFT__VI 0x00000012 -#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT__VI 0x0000000a -#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT__VI 0x00000009 -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT__VI 0x0000000e -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT__VI 0x0000000d -#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT__VI 0x00000004 -#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT__VI 0x00000000 -#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT__VI 0x00000001 -#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT__VI 0x00000002 -#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT__VI 0x00000003 -#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT__VI 0x00000004 -#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT__VI 0x0000000b -#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT__VI 0x00000008 -#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT__VI 0x00000004 -#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT__VI 0x0000000b -#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT__VI 0x00000008 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT__VI 0x0000001f -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT__VI 0x00000004 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT__VI 0x00000000 -#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT__VI 0x00000000 -#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT__VI 0x00000001 -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT__VI 0x00000000 -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT__VI 0x00000010 -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT__VI 0x00000007 -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT__VI 0x0000000f -#define RLC_MGCG_CTRL__MGCG_EN__SHIFT__VI 0x00000000 -#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT__VI 0x00000007 -#define RLC_MGCG_CTRL__ON_DELAY__SHIFT__VI 0x00000003 -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT__VI 0x00000010 -#define RLC_MGCG_CTRL__SILICON_EN__SHIFT__VI 0x00000001 -#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT__VI 0x00000002 -#define RLC_MGCG_CTRL__SPARE__SHIFT__VI 0x00000011 -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT__VI 0x00000000 -#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT__VI 0x0000000f -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT__VI 0x00000004 -#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT__VI 0x0000000e -#define RLC_PG_CNTL__RESERVED1__SHIFT__VI 0x00000014 -#define RLC_PG_CNTL__RESERVED__SHIFT__SI__CI 0x00000004 -#define RLC_PG_CNTL__RESERVED__SHIFT__VI 0x00000005 -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT__VI 0x00000013 -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT__VI 0x00000000 -#define RLC_PG_DELAY_3__RESERVED__SHIFT__VI 0x00000008 -#define RLC_RLCV_COMMAND__CMD__SHIFT__VI 0x00000000 -#define RLC_RLCV_COMMAND__RESERVED__SHIFT__VI 0x00000004 -#define RLC_RLCV_SAFE_MODE__CMD__SHIFT__VI 0x00000000 -#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT__VI 0x00000001 -#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT__VI 0x00000005 -#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT__VI 0x0000000c -#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT__VI 0x00000008 -#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT__VI 0x00000004 -#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT__VI 0x00000002 -#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT__VI 0x00000003 -#define RLC_ROM_CNTL__RESERVED__SHIFT__VI 0x00000005 -#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT__VI 0x00000001 -#define RLC_ROM_CNTL__USE_ROM__SHIFT__VI 0x00000000 -#define RLC_SAFE_MODE__CMD__SHIFT__VI 0x00000000 -#define RLC_SAFE_MODE__RESERVED1__SHIFT__VI 0x00000005 -#define RLC_SAFE_MODE__RESERVED__SHIFT__VI 0x0000000c -#define RLC_SAFE_MODE__RESPONSE__SHIFT__VI 0x00000008 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT__VI 0x00000011 -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT__VI 0x00000018 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT__VI 0x00000014 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT__VI 0x00000015 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT__VI 0x00000016 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT__VI 0x00000017 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT__VI 0x00000012 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT__VI 0x00000013 -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT__VI 0x0000000f -#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT__VI 0x00000011 -#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT__VI 0x00000010 -#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT__VI 0x0000000e -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT__VI 0x0000001b -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT__VI 0x0000000f -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT__VI 0x0000001a -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT__VI 0x00000011 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT__VI 0x00000018 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT__VI 0x00000014 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT__VI 0x00000015 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT__VI 0x00000016 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT__VI 0x00000017 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT__VI 0x00000012 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT__VI 0x00000013 -#define RLC_SMU_ARGUMENT_1__ARG__SHIFT__VI 0x00000000 -#define RLC_SMU_ARGUMENT_2__ARG__SHIFT__VI 0x00000000 -#define RLC_SMU_COMMAND__CMD__SHIFT__VI 0x00000000 -#define RLC_SMU_MESSAGE__CMD__SHIFT__VI 0x00000000 -#define RLC_SMU_RESP__CONTENT__SHIFT__VI 0x00000000 -#define RLC_SMU_SAFE_MODE__CMD__SHIFT__VI 0x00000000 -#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT__VI 0x00000001 -#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT__VI 0x00000005 -#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT__VI 0x0000000c -#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT__VI 0x00000008 -#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT__VI 0x00000000 -#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT__VI 0x0000000a -#define RLC_SRM_ARAM_DATA__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT__VI 0x00000001 -#define RLC_SRM_CNTL__RESERVED__SHIFT__VI 0x00000002 -#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT__VI 0x00000000 -#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT__VI 0x00000008 -#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT__VI 0x00000000 -#define RLC_SRM_DEBUG__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT__VI 0x00000000 -#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT__VI 0x0000000a -#define RLC_SRM_DRAM_DATA__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_GPM_ABORT__ABORT__SHIFT__VI 0x00000000 -#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT__VI 0x00000001 -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT__VI 0x00000000 -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT__VI 0x00000001 -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT__VI 0x00000002 -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT__VI 0x0000001f -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT__VI 0x00000002 -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT__VI 0x00000001 -#define RLC_SRM_GPM_COMMAND__OP__SHIFT__VI 0x00000000 -#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT__VI 0x0000001d -#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT__VI 0x00000005 -#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT__VI 0x00000011 -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT__VI 0x00000010 -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT__VI 0x00000000 -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT__VI 0x00000000 -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT__VI 0x00000001 -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT__VI 0x00000002 -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT__VI 0x0000001f -#define RLC_SRM_RLCV_COMMAND__OP__SHIFT__VI 0x00000000 -#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT__VI 0x0000001c -#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT__VI 0x00000001 -#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT__VI 0x00000004 -#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT__VI 0x00000010 -#define RLC_SRM_STAT__RESERVED__SHIFT__VI 0x00000001 -#define RLC_SRM_STAT__SRM_STATUS__SHIFT__VI 0x00000000 -#define RLC_STAT__RLC_SRM_BUSY__SHIFT__VI 0x00000003 -#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT__VI 0x0000000e -#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT__VI 0x00000000 -#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT__VI 0x0000001f -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT__VI 0x0000001f -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT__VI 0x00000000 -#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT__VI 0x00000000 -#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT__VI 0x00000000 -#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT__VI 0x00000000 -#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT__VI 0x00000010 -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT__VI 0x0000001a -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT__VI 0x0000001c -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT__VI 0x0000001e -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT__VI 0x00000002 -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT__VI 0x00000001 -#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT__VI 0x00000001 -#define SDMA0_CNTL__DRM_RESTORE_ENABLE__SHIFT__VI 0x00000013 -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT__VI 0x0000001e -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT__VI 0x00000005 -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT__VI 0x00000011 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT__VI 0x00000013 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT__VI 0x00000011 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT__VI 0x00000012 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA0__SHIFT__VI 0x0000001c -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA1__SHIFT__VI 0x0000001d -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA2__SHIFT__VI 0x0000001e -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA3__SHIFT__VI 0x0000001f -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY0__SHIFT__VI 0x00000018 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY1__SHIFT__VI 0x00000019 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY2__SHIFT__VI 0x0000001a -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY3__SHIFT__VI 0x0000001b -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY0__SHIFT__VI 0x00000014 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY1__SHIFT__VI 0x00000015 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY2__SHIFT__VI 0x00000016 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY3__SHIFT__VI 0x00000017 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT__VI 0x0000000e -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT__VI 0x0000000d -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT__VI 0x0000000a -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT__VI 0x0000000c -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT__VI 0x0000000b -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT__VI 0x0000000f -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT__VI 0x00000002 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT__VI 0x00000001 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT__VI 0x00000000 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT__VI 0x00000008 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT__VI 0x00000009 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT__VI 0x00000003 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT__VI 0x00000006 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT__VI 0x00000007 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT__VI 0x00000005 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT__VI 0x00000004 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT__VI 0x00000010 -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT__VI 0x00000012 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT__VI 0x00000008 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT__VI 0x0000000d -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT__VI 0x0000000c -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT__VI 0x00000009 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD0__SHIFT__VI 0x00000001 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD1__SHIFT__VI 0x00000002 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD2__SHIFT__VI 0x00000003 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD3__SHIFT__VI 0x00000004 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD4__SHIFT__VI 0x00000005 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_OFFSET__SHIFT__VI 0x00000000 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_UNROLLKEY__SHIFT__VI 0x00000006 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT__VI 0x00000011 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT__VI 0x0000000f -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT__VI 0x00000010 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT__VI 0x00000007 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT__VI 0x0000000a -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT__VI 0x0000000b -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT__VI 0x0000000e -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT__VI 0x00000007 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT__VI 0x00000006 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT__VI 0x00000000 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT__VI 0x00000001 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT__VI 0x00000002 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT__VI 0x00000003 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT__VI 0x00000004 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT__VI 0x00000005 -#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT__VI 0x00000001 -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT__VI 0x00000002 -#define SDMA0_EDC_CONFIG__WRITE_DIS__SHIFT__VI 0x00000000 -#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT__VI 0x00000002 -#define SDMA0_FREEZE__F32_FREEZE__SHIFT__VI 0x00000006 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT__VI 0x00000009 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT__VI 0x0000000a -#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT__VI 0x00000002 -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT__VI 0x00000000 -#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT__VI 0x00000002 -#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT__VI 0x0000001e -#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT__VI 0x0000001c -#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT__VI 0x00000000 -#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT__VI 0x00000000 -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT__VI 0x00000000 -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT__VI 0x00000008 -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT__VI 0x00000001 -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT__VI 0x00000000 -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT__VI 0x00000004 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT__VI 0x00000000 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT__VI 0x00000000 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT__VI 0x00000000 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT__VI 0x00000000 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT__VI 0x00000000 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT__VI 0x00000000 -#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT__VI 0x00000000 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT__VI 0x00000002 -#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT__VI 0x00000001 -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT__VI 0x00000000 -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT__VI 0x00000010 -#define SDMA0_ID__DEVICE_ID__SHIFT__VI 0x00000000 -#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT__VI 0x00000003 -#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT__VI 0x00000001 -#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT__VI 0x00000002 -#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT__VI 0x00000000 -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_S1__SHIFT__VI 0x0000000c -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_S2__SHIFT__VI 0x00000012 -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT__VI 0x0000000a -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT__VI 0x00000009 -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT__VI 0x0000000b -#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT__VI 0x00000010 -#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT__VI 0x00000011 -#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT__VI 0x0000001e -#define SDMA0_PUB_REG_TYPE0__SDMA0_ATOMIC_CNTL__SHIFT__VI 0x0000001d -#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT__VI 0x0000001b -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT__VI 0x00000005 -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT__VI 0x00000003 -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT__VI 0x00000004 -#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT__VI 0x0000001c -#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT__VI 0x0000001a -#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT__VI 0x00000012 -#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT__VI 0x00000013 -#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT__VI 0x00000007 -#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT__VI 0x0000000b -#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT__VI 0x00000014 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT__VI 0x00000015 -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT__VI 0x00000002 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT__VI 0x0000000c -#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT__VI 0x0000000a -#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT__VI 0x0000000f -#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT__VI 0x00000009 -#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT__VI 0x0000000e -#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT__VI 0x0000000d -#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT__VI 0x00000006 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT__VI 0x00000000 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT__VI 0x00000001 -#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT__VI 0x00000017 -#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT__VI 0x00000019 -#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT__VI 0x00000018 -#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT__VI 0x00000016 -#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT__VI 0x00000005 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT__VI 0x00000003 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT__VI 0x00000000 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT__VI 0x00000004 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT__VI 0x00000002 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT__VI 0x00000001 -#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT__VI 0x00000009 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT__VI 0x0000000a -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT__VI 0x00000002 -#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT__VI 0x00000008 -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT__VI 0x00000001 -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT__VI 0x00000004 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT__VI 0x00000002 -#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT__VI 0x00000001 -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT__VI 0x00000000 -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT__VI 0x00000010 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT__VI 0x00000009 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT__VI 0x0000000a -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT__VI 0x00000002 -#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT__VI 0x00000008 -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT__VI 0x00000001 -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT__VI 0x00000004 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT__VI 0x00000002 -#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT__VI 0x00000001 -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT__VI 0x00000000 -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT__VI 0x00000010 -#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT__VI 0x00000009 -#define SDMA0_STATUS2_REG__CMD_OP__SHIFT__VI 0x00000010 -#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT__VI 0x00000002 -#define SDMA0_STATUS2_REG__ID__SHIFT__VI 0x00000000 -#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT__VI 0x0000000f -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT__VI 0x00000014 -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT__VI 0x00000010 -#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT__VI 0x0000000e -#define SDMA0_VERSION__VALUE__SHIFT__VI 0x00000000 -#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT__VI 0x00000000 -#define SDMA0_VIRT_RESET_REQ__PF__SHIFT__VI 0x0000001f -#define SDMA0_VIRT_RESET_REQ__VF__SHIFT__VI 0x00000000 -#define SDMA0_VM_CNTL__CMD__SHIFT__VI 0x00000000 -#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT__VI 0x00000000 -#define SDMA0_VM_CTX_CNTL__VMID__SHIFT__VI 0x00000004 -#define SDMA0_VM_CTX_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA0_VM_CTX_LO__ADDR__SHIFT__VI 0x00000002 -#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT__VI 0x00000000 -#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT__VI 0x0000001f -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT__VI 0x0000001f -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT__VI 0x00000000 -#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT__VI 0x00000000 -#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT__VI 0x00000000 -#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT__VI 0x00000000 -#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT__VI 0x00000010 -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT__VI 0x0000001a -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT__VI 0x0000001c -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT__VI 0x0000001e -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT__VI 0x00000002 -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT__VI 0x00000001 -#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT__VI 0x00000001 -#define SDMA1_CNTL__DRM_RESTORE_ENABLE__SHIFT__VI 0x00000013 -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT__VI 0x0000001e -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT__VI 0x00000005 -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT__VI 0x00000011 -#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT__VI 0x00000014 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT__VI 0x00000013 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT__VI 0x00000011 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT__VI 0x00000012 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT__VI 0x0000000e -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT__VI 0x0000000d -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT__VI 0x0000000a -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT__VI 0x0000000c -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT__VI 0x0000000b -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT__VI 0x0000000f -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT__VI 0x00000002 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT__VI 0x00000001 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT__VI 0x00000000 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT__VI 0x00000008 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT__VI 0x00000009 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT__VI 0x00000003 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT__VI 0x00000006 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT__VI 0x00000007 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT__VI 0x00000005 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT__VI 0x00000004 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT__VI 0x00000010 -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT__VI 0x00000012 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT__VI 0x00000008 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT__VI 0x0000000d -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT__VI 0x0000000c -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT__VI 0x00000009 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT__VI 0x00000011 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT__VI 0x0000000f -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT__VI 0x00000010 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT__VI 0x00000007 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT__VI 0x0000000a -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT__VI 0x00000000 -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT__VI 0x0000000b -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT__VI 0x0000000e -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT__VI 0x00000007 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT__VI 0x00000006 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT__VI 0x00000000 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT__VI 0x00000001 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT__VI 0x00000002 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT__VI 0x00000003 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT__VI 0x00000004 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT__VI 0x00000005 -#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT__VI 0x00000001 -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT__VI 0x00000002 -#define SDMA1_EDC_CONFIG__WRITE_DIS__SHIFT__VI 0x00000000 -#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT__VI 0x00000002 -#define SDMA1_FREEZE__F32_FREEZE__SHIFT__VI 0x00000006 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT__VI 0x00000009 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT__VI 0x0000000a -#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT__VI 0x00000002 -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT__VI 0x00000000 -#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT__VI 0x00000002 -#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT__VI 0x0000001e -#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT__VI 0x0000001c -#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT__VI 0x00000000 -#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT__VI 0x00000000 -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT__VI 0x00000000 -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT__VI 0x00000008 -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT__VI 0x00000001 -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT__VI 0x00000000 -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT__VI 0x00000004 -#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT__VI 0x00000000 -#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT__VI 0x00000000 -#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT__VI 0x00000000 -#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT__VI 0x00000000 -#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT__VI 0x00000000 -#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT__VI 0x00000000 -#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT__VI 0x00000000 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT__VI 0x00000002 -#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT__VI 0x00000001 -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT__VI 0x00000000 -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT__VI 0x00000010 -#define SDMA1_ID__DEVICE_ID__SHIFT__VI 0x00000000 -#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT__VI 0x00000003 -#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT__VI 0x00000001 -#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT__VI 0x00000002 -#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT__VI 0x00000000 -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_S1__SHIFT__VI 0x0000000c -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_S2__SHIFT__VI 0x00000012 -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT__VI 0x0000000a -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT__VI 0x00000009 -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT__VI 0x0000000b -#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT__VI 0x00000010 -#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT__VI 0x00000011 -#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT__VI 0x0000001e -#define SDMA1_PUB_REG_TYPE0__SDMA1_ATOMIC_CNTL__SHIFT__VI 0x0000001d -#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT__VI 0x0000001b -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT__VI 0x00000005 -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT__VI 0x00000003 -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT__VI 0x00000004 -#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT__VI 0x0000001c -#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT__VI 0x0000001a -#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT__VI 0x00000012 -#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT__VI 0x00000013 -#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT__VI 0x00000007 -#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT__VI 0x0000000b -#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT__VI 0x00000014 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT__VI 0x00000015 -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT__VI 0x00000002 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT__VI 0x0000000c -#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT__VI 0x0000000a -#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT__VI 0x0000000f -#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT__VI 0x00000009 -#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT__VI 0x0000000e -#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT__VI 0x0000000d -#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT__VI 0x00000006 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT__VI 0x00000000 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT__VI 0x00000001 -#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT__VI 0x00000016 -#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT__VI 0x00000005 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT__VI 0x00000003 -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT__VI 0x00000000 -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT__VI 0x00000004 -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT__VI 0x00000002 -#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT__VI 0x00000001 -#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT__VI 0x00000009 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT__VI 0x0000000a -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT__VI 0x00000002 -#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT__VI 0x00000008 -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT__VI 0x00000001 -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT__VI 0x00000004 -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT__VI 0x00000002 -#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT__VI 0x00000001 -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT__VI 0x00000000 -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT__VI 0x00000010 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT__VI 0x00000009 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT__VI 0x0000000a -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT__VI 0x00000002 -#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT__VI 0x00000008 -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT__VI 0x00000001 -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT__VI 0x00000004 -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT__VI 0x00000002 -#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT__VI 0x00000001 -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT__VI 0x00000000 -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT__VI 0x00000010 -#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT__VI 0x00000009 -#define SDMA1_STATUS2_REG__CMD_OP__SHIFT__VI 0x00000010 -#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT__VI 0x00000002 -#define SDMA1_STATUS2_REG__ID__SHIFT__VI 0x00000000 -#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT__VI 0x0000000f -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT__VI 0x00000014 -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT__VI 0x00000010 -#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT__VI 0x0000000e -#define SDMA1_VERSION__VALUE__SHIFT__VI 0x00000000 -#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT__VI 0x00000000 -#define SDMA1_VIRT_RESET_REQ__PF__SHIFT__VI 0x0000001f -#define SDMA1_VIRT_RESET_REQ__VF__SHIFT__VI 0x00000000 -#define SDMA1_VM_CNTL__CMD__SHIFT__VI 0x00000000 -#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT__VI 0x00000000 -#define SDMA1_VM_CTX_CNTL__VMID__SHIFT__VI 0x00000004 -#define SDMA1_VM_CTX_HI__ADDR__SHIFT__VI 0x00000000 -#define SDMA1_VM_CTX_LO__ADDR__SHIFT__VI 0x00000002 -#define SEM_ACTIVE_FCN_ID__VFID__SHIFT__VI 0x00000000 -#define SEM_ACTIVE_FCN_ID__VF__SHIFT__VI 0x0000001f -#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT__VI 0x00000007 -#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT__VI 0x0000000c -#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT__VI 0x00000002 -#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT__VI 0x00000003 -#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT__VI 0x00000008 -#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT__VI 0x00000006 -#define SEM_CHICKEN_BITS__SIGNAL_FAIL__SHIFT__VI 0x00000005 -#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT__VI 0x00000000 -#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT__VI 0x00000018 -#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT__VI 0x00000010 -#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT__VI 0x00000018 -#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT__VI 0x00000010 -#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT__VI 0x00000000 -#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT__VI 0x00000000 -#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT__VI 0x00000001 -#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT__VI 0x0000000b -#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT__VI 0x00000000 -#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT__VI 0x0000000a -#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT__VI 0x00000002 -#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT__VI 0x0000000c -#define SEM_STATUS__ATC_REQ_PENDING__SHIFT__VI 0x0000000f -#define SEM_STATUS__SWITCH_READY__SHIFT__VI 0x0000001f -#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT__VI 0x0000000e -#define SEM_VF_ENABLE__VALUE__SHIFT__VI 0x00000000 -#define SEM_VIRT_RESET_REQ__PF__SHIFT__VI 0x0000001f -#define SEM_VIRT_RESET_REQ__VF__SHIFT__VI 0x00000000 -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT__VI 0x00000004 -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT__VI 0x00000000 -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT__VI 0x0000001e -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT__VI 0x0000001f -#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT__VI 0x00000000 -#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT__VI 0x00000003 -#define SH_MEM_CONFIG__APE1_ATC__SHIFT__VI 0x0000000b -#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT__VI 0x00000008 -#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT__VI 0x00000005 -#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT__VI 0x00000002 -#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT__VI 0x00000019 -#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEW__SHIFT__VI 0x00000009 -#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEW__SHIFT__VI 0x00000009 -#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT__VI 0x00000000 -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT__VI 0x00000000 -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT__VI 0x00000008 -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT__VI 0x00000010 -#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT__VI 0x00000018 -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT__VI 0x00000000 -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT__VI 0x00000008 -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT__VI 0x00000010 -#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT__VI 0x00000018 -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT__VI 0x00000000 -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT__VI 0x00000008 -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT__VI 0x00000010 -#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT__VI 0x00000018 -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT__VI 0x00000000 -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT__VI 0x00000008 -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT__VI 0x00000010 -#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT__VI 0x00000018 -#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT__VI 0x00000008 -#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT__VI 0x00000001 -#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT__VI 0x00000010 -#define SMBUS_CNTL0__THM_READY__SHIFT__VI 0x00000014 -#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT__VI 0x00000009 -#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT__VI 0x00000001 -#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT__VI 0x00000000 -#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT__VI 0x00000016 -#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT__VI 0x00000000 -#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT__VI 0x00000014 -#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT__VI 0x00000005 -#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT__VI 0x00000000 -#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT__VI 0x0000000b -#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT__VI 0x0000000d -#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT__VI 0x00000000 -#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT__VI 0x00000008 -#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT__VI 0x00000000 -#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT__VI 0x00000000 -#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT__VI 0x0000001f -#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT__VI 0x00000000 -#define SMBUS_UDID_CNTL2__ASF__SHIFT__VI 0x00000009 -#define SMBUS_UDID_CNTL2__IPMI__SHIFT__VI 0x0000000a -#define SMBUS_UDID_CNTL2__OEM__SHIFT__VI 0x00000008 -#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT__VI 0x00000000 -#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT__VI 0x00000004 -#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT__VI 0x00000001 -#define SMU_ACTIVE_FCN_ID__VFID__SHIFT__VI 0x00000000 -#define SMU_ACTIVE_FCN_ID__VF__SHIFT__VI 0x0000001f -#define SMU_AUTH_INPUT_DATA__AUTH_START_ADDR__SHIFT__VI 0x00000000 -#define SMU_AUTH_INPUT_DATA__AUTO_START__SHIFT__VI 0x0000001f -#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT__VI 0x00000000 -#define SMU_CG_FPS_CNT__FPS_CNT__SHIFT__VI 0x00000000 -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cmp_Unit0_Pstate__SHIFT__VI 0x00000000 -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cmp_Unit1_Pstate__SHIFT__VI 0x00000004 -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cur_Core_Vid_Pstate__SHIFT__VI 0x00000017 -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Cur_Nb_Vid_Pstate__SHIFT__VI 0x0000001a -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Pwr_Mgmt_Req_Act1__SHIFT__VI 0x0000001e -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Pwr_Mgmt_Req_Act2__SHIFT__VI 0x0000001f -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Pwr_Mgmt_Req_Wait__SHIFT__VI 0x0000001c -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__RESERVED0__SHIFT__VI 0x00000007 -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__RESERVED1__SHIFT__VI 0x00000003 -#define SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__Vid_Transition_Act__SHIFT__VI 0x0000001d -#define SMU_DC_CNTL__CG_DCO_CLK_SLOW__SHIFT__VI 0x00000000 -#define SMU_DC_CNTL__DCO_CG_CLK_SLOW_ACK__SHIFT__VI 0x00000002 -#define SMU_DC_CNTL__DC_SMU_EVENT_INTERRUPT__SHIFT__VI 0x00000001 -#define SMU_DMA_ACTIVE_SAMPLE__SB_CORE_SEL__SHIFT__VI 0x0000000c -#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT__VI 0x00000000 -#define SMU_MP1_RLC2MP_RESP__CONTENT__SHIFT__VI 0x00000000 -#define SMU_MP1_SRBM2P_MSG_5__CONTENT__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_0__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_100__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_101__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_102__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_103__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_104__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_105__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_106__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_107__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_108__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_109__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_10__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_110__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_111__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_112__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_113__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_114__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_115__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_116__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_117__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_118__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_119__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_11__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_120__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_121__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_122__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_123__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_124__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_125__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_126__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_127__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_12__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_13__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_14__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_15__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_16__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_17__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_18__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_19__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_1__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_20__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_21__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_22__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_23__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_24__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_25__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_26__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_27__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_28__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_29__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_2__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_30__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_31__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_32__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_33__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_34__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_35__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_36__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_37__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_38__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_39__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_3__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_40__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_41__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_42__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_43__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_44__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_45__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_46__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_47__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_48__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_49__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_4__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_50__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_51__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_52__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_53__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_54__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_55__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_56__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_57__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_58__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_59__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_5__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_60__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_61__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_62__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_63__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_64__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_65__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_66__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_67__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_68__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_69__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_6__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_70__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_71__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_72__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_73__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_74__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_75__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_76__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_77__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_78__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_79__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_7__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_80__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_81__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_82__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_83__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_84__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_85__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_86__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_87__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_88__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_89__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_8__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_90__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_91__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_92__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_93__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_94__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_95__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_96__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_97__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_98__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_99__DATA__SHIFT__VI 0x00000000 -#define SMU_PM_STATUS_9__DATA__SHIFT__VI 0x00000000 -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_COMPUTE_UNIT_0__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_COMPUTE_UNIT_0__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_COMPUTE_UNIT_0__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_COMPUTE_UNIT_0__RESERVED0__SHIFT__VI 0x0000001d -#define SMU_PSTATE_COMPUTE_UNIT_0__RESERVED1__SHIFT__VI 0x00000011 -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_COMPUTE_UNIT_1__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_COMPUTE_UNIT_1__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_COMPUTE_UNIT_1__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_COMPUTE_UNIT_1__RESERVED0__SHIFT__VI 0x0000001d -#define SMU_PSTATE_COMPUTE_UNIT_1__RESERVED1__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_0__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_0__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_0__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_0__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_0__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_0__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_1__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_1__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_1__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_1__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_1__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_1__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_2__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_2__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_2__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_2__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_2__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_2__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_3__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_3__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_3__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_3__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_3__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_3__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_4__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_4__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_4__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_4__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_4__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_4__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_5__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_5__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_5__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_5__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_5__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_5__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_6__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_6__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_6__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_6__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_6__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_6__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Did__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Fid__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Vid7__SHIFT__VI 0x0000001c -#define SMU_PSTATE_CONFIGURATION_7__Cpu_Vid_6_0__SHIFT__VI 0x00000009 -#define SMU_PSTATE_CONFIGURATION_7__IddDiv__SHIFT__VI 0x00000019 -#define SMU_PSTATE_CONFIGURATION_7__IddValue__SHIFT__VI 0x00000011 -#define SMU_PSTATE_CONFIGURATION_7__Nb_Pstate__SHIFT__VI 0x00000010 -#define SMU_PSTATE_CONFIGURATION_7__Pstate_En__SHIFT__VI 0x0000001b -#define SMU_PSTATE_CONFIGURATION_7__RESERVED__SHIFT__VI 0x0000001d -#define SMU_PSTATE_CONFIGURATION__Priority_Selector__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONFIGURATION__Pstate_CC6_Exit__SHIFT__VI 0x00000002 -#define SMU_PSTATE_CONFIGURATION__Pstate_Req_Exit__SHIFT__VI 0x00000001 -#define SMU_PSTATE_CONFIGURATION__RESERVED__SHIFT__VI 0x00000003 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit0_Smu_Pstate_Active__SHIFT__VI 0x00000001 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit0_Smu_Pstate_Request__SHIFT__VI 0x00000000 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit1_Smu_Pstate_Active__SHIFT__VI 0x00000003 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit1_Smu_Pstate_Request__SHIFT__VI 0x00000002 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit2_Smu_Pstate_Active__SHIFT__VI 0x00000005 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit2_Smu_Pstate_Request__SHIFT__VI 0x00000004 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit3_Smu_Pstate_Active__SHIFT__VI 0x00000007 -#define SMU_PSTATE_CONTROL_AND_STATUS__Cmp_Unit3_Smu_Pstate_Request__SHIFT__VI 0x00000006 -#define SMU_PSTATE_CONTROL_AND_STATUS__RESERVED__SHIFT__VI 0x00000008 -#define SMU_RLC_RESPONSE__RESP__SHIFT__VI 0x00000000 -#define SMU_TCON_0__TCON_DATA__SHIFT__VI 0x00000000 -#define SMU_TP_SHORT_INIT__RESERVED__SHIFT__VI 0x00000008 -#define SMU_TP_SHORT_INIT__TP_SHORT_INIT__SHIFT__VI 0x00000000 -#define SMU_UVD_CNTL__UVD_CG_CLK_SWITCH_ACK__SHIFT__VI 0x00000000 -#define SMU_VCE_CNTL__VCE_CG_CLK_SLOW_ACK__SHIFT__VI 0x00000000 -#define SMU_VCE_CNTL__VCE_CG_CLK_SWITCH_ACK__SHIFT__VI 0x00000001 -#define SMU_VF_ENABLE__VF_ENABLE__SHIFT__VI 0x00000000 -#define SMU_VIRT_RESET_REQ__PF__SHIFT__VI 0x0000001f -#define SMU_VIRT_RESET_REQ__VF__SHIFT__VI 0x00000000 -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT__VI 0x00000002 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT__VI 0x00000001 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT__VI 0x0000001e -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT__VI 0x00000000 -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT__VI 0x0000001f -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT__VI 0x00000004 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT__VI 0x00000000 -#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT__VI 0x00000002 -#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT__VI 0x00000000 -#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT__VI 0x00000001 -#define SPI_DSM_CNTL__UNUSED__SHIFT__VI 0x00000003 -#define SPI_EDC_CNT__SED__SHIFT__VI 0x00000000 -#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT__VI 0x00000001 -#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT__VI 0x00000000 -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT__VI 0x00000018 -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT__VI 0x00000019 -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT__VI 0x00000015 -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT__VI 0x00000013 -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT__VI 0x00000017 -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT__VI 0x00000014 -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT__VI 0x0000000f -#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT__VI 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT__VI 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT__VI 0x0000000c -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT__VI 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT__VI 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT__VI 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT__VI 0x00000018 -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT__VI 0x00000001 -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT__VI 0x00000018 -#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT__VI 0x0000001a -#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT__VI 0x0000001a -#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT__VI 0x0000000a -#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT__VI 0x0000001a -#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT__VI 0x00000016 -#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT__VI 0x00000002 -#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT__VI 0x00000000 -#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT__VI 0x00000004 -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT__VI 0x00000011 -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT__VI 0x00000016 -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT__VI 0x0000000c -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT__VI 0x00000007 -#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT__VI 0x00000011 -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT__VI 0x00000016 -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT__VI 0x0000000c -#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT__VI 0x00000007 -#define SPMI_CONFIG0_0__SPMI_ENABLE__SHIFT__VI 0x00000000 -#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT__VI 0x00000016 -#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT__VI 0x00000011 -#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT__VI 0x00000002 -#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT__VI 0x00000007 -#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT__VI 0x0000000c -#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE__SHIFT__VI 0x00000005 -#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT__VI 0x00000000 -#define SPMI_FORCE_CLOCK_GATERS__CLOCK_GATER_0_FORCE__SHIFT__VI 0x00000000 -#define SPMI_FORCE_CLOCK_GATERS__SRAM_CLOCK_GATER_FORCE__SHIFT__VI 0x00000008 -#define SPMI_RESET__SYNC_RESET__SHIFT__VI 0x0000001f -#define SPMI_SPARE_EX__SPARE_DATA_EX__SHIFT__VI 0x00000000 -#define SPMI_SPARE__SPARE_DATA__SHIFT__VI 0x00000000 -#define SPMI_SRAM_CLK_GATER__SRAM_CLK_GATER_EN__SHIFT__VI 0x00000000 -#define SPMI_SRAM_CLK_GATER__SRAM_CLK_GATER_TIMER__SHIFT__VI 0x00000001 -#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT__VI 0x00000010 -#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT__VI 0x00000000 -#define SQC_CACHES__COMPLETE__SHIFT__VI 0x00000010 -#define SQC_CACHES__INVALIDATE__SHIFT__VI 0x00000002 -#define SQC_CACHES__TARGET_DATA__SHIFT__VI 0x00000001 -#define SQC_CACHES__TARGET_INST__SHIFT__VI 0x00000000 -#define SQC_CACHES__VOL__SHIFT__VI 0x00000004 -#define SQC_CACHES__WRITEBACK__SHIFT__VI 0x00000003 -#define SQC_CONFIG__EVICT_LRU__SHIFT__VI 0x0000000c -#define SQC_CONFIG__FORCE_1_BANK__SHIFT__VI 0x0000000f -#define SQC_CONFIG__FORCE_2_BANK__SHIFT__VI 0x0000000e -#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT__VI 0x00000010 -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT__VI 0x00000011 -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT__VI 0x00000014 -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT__VI 0x00000017 -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT__VI 0x0000001a -#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT__VI 0x0000001d -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT__VI 0x00000002 -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT__VI 0x00000005 -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT__VI 0x00000008 -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT__VI 0x0000000b -#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT__VI 0x0000000e -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT__VI 0x0000000f -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT__VI 0x00000012 -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT__VI 0x00000015 -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT__VI 0x00000018 -#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT__VI 0x0000001b -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT__VI 0x00000000 -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT__VI 0x00000003 -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT__VI 0x00000006 -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT__VI 0x00000009 -#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT__VI 0x0000000c -#define SQC_EDC_CNT__DATA_DED__SHIFT__VI 0x00000018 -#define SQC_EDC_CNT__DATA_SEC__SHIFT__VI 0x00000010 -#define SQC_EDC_CNT__INST_DED__SHIFT__VI 0x00000008 -#define SQC_EDC_CNT__INST_SEC__SHIFT__VI 0x00000000 -#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT__VI 0x00000014 -#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT__VI 0x00000013 -#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT__VI 0x00000012 -#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT__VI 0x00000017 -#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT__VI 0x00000015 -#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT__VI 0x0000001b -#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT__VI 0x0000001a -#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT__VI 0x00000019 -#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT__VI 0x0000001e -#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT__VI 0x0000001c -#define SQC_GATCL1_CNTL__RESERVED__SHIFT__VI 0x00000000 -#define SQC_WRITEBACK__DIRTY__SHIFT__VI 0x00000001 -#define SQC_WRITEBACK__DWB__SHIFT__VI 0x00000000 -#define SQ_CMD__DATA__SHIFT__VI 0x00000008 -#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT__VI 0x0000000a -#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT__VI 0x00000009 -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT__VI 0x00000011 -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT__VI 0x00000010 -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT__VI 0x00000012 -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT__VI 0x00000013 -#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT__VI 0x00000015 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT__VI 0x00000012 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT__VI 0x00000015 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT__VI 0x00000010 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT__VI 0x00000011 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT__VI 0x00000013 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT__VI 0x00000014 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT__VI 0x00000008 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT__VI 0x00000009 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT__VI 0x00000018 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT__VI 0x00000019 -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT__VI 0x0000000a -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT__VI 0x00000002 -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT__VI 0x00000003 -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT__VI 0x0000001a -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT__VI 0x00000000 -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT__VI 0x00000001 -#define SQ_DS_0__GDS__SHIFT__SI__CI 0x00000011 -#define SQ_DS_0__GDS__SHIFT__VI 0x00000010 -#define SQ_DS_0__OP__SHIFT__SI__CI 0x00000012 -#define SQ_DS_0__OP__SHIFT__VI 0x00000011 -#define SQ_EDC_DED_CNT__LDS_DED__SHIFT__VI 0x00000000 -#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT__VI 0x00000008 -#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT__VI 0x00000010 -#define SQ_EDC_INFO__SIMD_ID__SHIFT__VI 0x00000004 -#define SQ_EDC_INFO__SOURCE__SHIFT__VI 0x00000006 -#define SQ_EDC_INFO__VM_ID__SHIFT__VI 0x00000009 -#define SQ_EDC_INFO__WAVE_ID__SHIFT__VI 0x00000000 -#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT__VI 0x00000000 -#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT__VI 0x00000008 -#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT__VI 0x00000010 -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT__VI 0x00000016 -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT__VI 0x00000017 -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT__VI 0x00000015 -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT__VI 0x00000018 -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT__VI 0x0000001c -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT__VI 0x00000000 -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT__VI 0x0000001f -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT__VI 0x0000001f -#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT__VI 0x00000000 -#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT__VI 0x0000000f -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT__VI 0x0000000c -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT__VI 0x0000000d -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT__VI 0x0000000e -#define SQ_MIMG_1__D16__SHIFT__VI 0x0000001f -#define SQ_MTBUF_0__OP__SHIFT__SI__CI 0x00000010 -#define SQ_MTBUF_0__OP__SHIFT__VI 0x0000000f -#define SQ_MUBUF_0__SLC__SHIFT__VI 0x00000011 -#define SQ_SMEM_0__ENCODING__SHIFT__VI 0x0000001a -#define SQ_SMEM_0__GLC__SHIFT__VI 0x00000010 -#define SQ_SMEM_0__IMM__SHIFT__VI 0x00000011 -#define SQ_SMEM_0__OP__SHIFT__VI 0x00000012 -#define SQ_SMEM_0__SBASE__SHIFT__VI 0x00000000 -#define SQ_SMEM_0__SDATA__SHIFT__VI 0x00000006 -#define SQ_SMEM_1__OFFSET__SHIFT__VI 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT__SI__CI 0x0000000c -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT__VI 0x0000000b -#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT__VI 0x0000000f -#define SQ_VOP3_0_SDST_ENC__OP__SHIFT__SI__CI 0x00000011 -#define SQ_VOP3_0_SDST_ENC__OP__SHIFT__VI 0x00000010 -#define SQ_VOP3_0__CLAMP__SHIFT__SI__CI 0x0000000b -#define SQ_VOP3_0__CLAMP__SHIFT__VI 0x0000000f -#define SQ_VOP3_0__OP__SHIFT__SI__CI 0x00000011 -#define SQ_VOP3_0__OP__SHIFT__VI 0x00000010 -#define SQ_VOP_DPP__BANK_MASK__SHIFT__VI 0x00000018 -#define SQ_VOP_DPP__BOUND_CTRL__SHIFT__VI 0x00000013 -#define SQ_VOP_DPP__DPP_CTRL__SHIFT__VI 0x00000008 -#define SQ_VOP_DPP__ROW_MASK__SHIFT__VI 0x0000001c -#define SQ_VOP_DPP__SRC0_ABS__SHIFT__VI 0x00000015 -#define SQ_VOP_DPP__SRC0_NEG__SHIFT__VI 0x00000014 -#define SQ_VOP_DPP__SRC0__SHIFT__VI 0x00000000 -#define SQ_VOP_DPP__SRC1_ABS__SHIFT__VI 0x00000017 -#define SQ_VOP_DPP__SRC1_NEG__SHIFT__VI 0x00000016 -#define SQ_VOP_SDWA__CLAMP__SHIFT__VI 0x0000000d -#define SQ_VOP_SDWA__DST_SEL__SHIFT__VI 0x00000008 -#define SQ_VOP_SDWA__DST_UNUSED__SHIFT__VI 0x0000000b -#define SQ_VOP_SDWA__SRC0_ABS__SHIFT__VI 0x00000015 -#define SQ_VOP_SDWA__SRC0_NEG__SHIFT__VI 0x00000014 -#define SQ_VOP_SDWA__SRC0_SEL__SHIFT__VI 0x00000010 -#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT__VI 0x00000013 -#define SQ_VOP_SDWA__SRC0__SHIFT__VI 0x00000000 -#define SQ_VOP_SDWA__SRC1_ABS__SHIFT__VI 0x0000001d -#define SQ_VOP_SDWA__SRC1_NEG__SHIFT__VI 0x0000001c -#define SQ_VOP_SDWA__SRC1_SEL__SHIFT__VI 0x00000018 -#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT__VI 0x0000001b -#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT__SI__CI 0x00000016 -#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT__VI 0x00000018 -#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT__SI__CI 0x00000019 -#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT__VI 0x0000001b -#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT__SI__CI 0x00000018 -#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT__VI 0x0000001a -#define SQ_WAVE_IB_DBG0__KILL__SHIFT__VI 0x0000001d -#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT__SI__CI 0x00000013 -#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT__VI 0x00000014 -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT__VI 0x0000001e -#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT__VI 0x00000000 -#define SQ_WAVE_IB_DBG1__QCNT__SHIFT__VI 0x00000008 -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT__VI 0x00000002 -#define SQ_WAVE_IB_DBG1__XCNT__SHIFT__VI 0x00000004 -#define SQ_WAVE_IB_DBG1__XNACK__SHIFT__VI 0x00000001 -#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT__VI 0x0000000f -#define SQ_WAVE_IB_STS__RCNT__SHIFT__VI 0x00000010 -#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT__VI 0x0000001b -#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT__VI 0x00000016 -#define SQ_WAVE_STATUS__USER_PRIO__SHIFT__VI 0x00000003 -#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT__VI 0x0000000a -#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT__VI 0x00000000 -#define SQ_WREXEC_EXEC_HI__ATC__SHIFT__VI 0x0000001b -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT__VI 0x0000001a -#define SQ_WREXEC_EXEC_HI__MSB__SHIFT__VI 0x0000001f -#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT__VI 0x0000001c -#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_BIF_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_BIF_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_BIF_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_BIF_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_BIF_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_BIF_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_BIF_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_BIF_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_BIF_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_BIF_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_BIF_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_BIF_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_BIF_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_BIF_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_BIF_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_BIF_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_BIF_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_BIF_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_BIF_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_BIF_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_BIF_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_BIF_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_BIF_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_BIF_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_BIF_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_BIF_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_BIF_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_BIF_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_BIF_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_BIF_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_BIF_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_BIF_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_BIF_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_BIF_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_BIF_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_BIF_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_BIF_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_BIF_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_BIF_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_BIF_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_BIF_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_BIF_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_BIF_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_BIF_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_BIF_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_BIF_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_BIF_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_BIF_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_BIF_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_BIF_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_BIF_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_BIF_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_BIF_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_BIF_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_BIF_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_BIF_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_BIF_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_BIF_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_BIF_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_BIF_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_BIF_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_BIF_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_BIF_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_BIF_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT__SHIFT__VI 0x00000013 -#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT__VI 0x00000012 -#define SRBM_CPU_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_CPU_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_CPU_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_CPU_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_CPU_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_CPU_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_CPU_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_CPU_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_CPU_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_CPU_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_CPU_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_CPU_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_CPU_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_CPU_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_CPU_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_CPU_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_CPU_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_CPU_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_CPU_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_CPU_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_CPU_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_CPU_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_CPU_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_CPU_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_CPU_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_CPU_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_CPU_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_CPU_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_CPU_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_CPU_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_CPU_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_CPU_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_CPU_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_CPU_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_CPU_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_CPU_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_CPU_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_CPU_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_CPU_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_CPU_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_CPU_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_CPU_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_CPU_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_CPU_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_CPU_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_CPU_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_CPU_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_CPU_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_CPU_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_CPU_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_CPU_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_CPU_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_CPU_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_CPU_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_CPU_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_CPU_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_CPU_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_CPU_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_CPU_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_CPU_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_CPU_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_CPU_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_CPU_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_CPU_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT__VI 0x00000000 -#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT__VI 0x00000001 -#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT__VI 0x0000001f -#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT__VI 0x0000000c -#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT__VI 0x00000003 -#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT__VI 0x0000001e -#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT__VI 0x0000001d -#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT__VI 0x0000000a -#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT__VI 0x0000000a -#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT__VI 0x0000000b -#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT__VI 0x00000000 -#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT__VI 0x00000010 -#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT__VI 0x00000000 -#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT__VI 0x00000000 -#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT__VI 0x00000010 -#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT__VI 0x00000000 -#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT__VI 0x00000002 -#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT__VI 0x00000014 -#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT__VI 0x00000013 -#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT__VI 0x0000001f -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT__VI 0x00000001 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT__VI 0x00000014 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT__VI 0x00000000 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT__VI 0x0000000f -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_DRM__SHIFT__VI 0x00000004 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT__VI 0x0000000c -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT__VI 0x00000010 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT__VI 0x0000000e -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT__VI 0x00000012 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT__VI 0x00000003 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT__VI 0x00000002 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT__VI 0x00000009 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT__VI 0x00000008 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT__VI 0x00000007 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT__VI 0x00000006 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT__VI 0x00000013 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT__VI 0x0000000d -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT__VI 0x00000005 -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT__VI 0x0000000a -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT__VI 0x0000000b -#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT__VI 0x00000011 -#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT__VI 0x0000001a -#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT__VI 0x00000018 -#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT__VI 0x00000019 -#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT__VI 0x0000001c -#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT__VI 0x0000001b -#define SRBM_GFX_CNTL_DATA__MEID__SHIFT__VI 0x00000002 -#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT__VI 0x00000000 -#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT__VI 0x00000008 -#define SRBM_GFX_CNTL_DATA__VMID__SHIFT__VI 0x00000004 -#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT__VI 0x00000000 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_GRBM_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_GRBM_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_GRBM_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_GRBM_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_GRBM_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_GRBM_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_GRBM_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_GRBM_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_GRBM_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_GRBM_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_GRBM_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_GRBM_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_GRBM_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_GRBM_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_GRBM_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_GRBM_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_GRBM_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_GRBM_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_GRBM_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_GRBM_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_GRBM_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_GRBM_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_GRBM_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_GRBM_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_GRBM_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT__VI 0x00000001 -#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT__VI 0x00000001 -#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT__VI 0x00000001 -#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT__VI 0x00000008 -#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT__VI 0x00000000 -#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_PEER_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_PEER_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_PEER_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_PEER_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_PEER_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_PEER_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_PEER_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_PEER_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_PEER_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_PEER_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_PEER_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_PEER_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_PEER_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_PEER_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_PEER_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_PEER_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_PEER_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_PEER_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_PEER_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_PEER_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_PEER_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_PEER_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_PEER_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_PEER_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_PEER_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_PEER_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_PEER_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_PEER_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_PEER_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_PEER_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_PEER_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_PEER_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_PEER_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_PEER_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_PEER_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_PEER_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_PEER_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_PEER_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_PEER_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_PEER_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_PEER_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_PEER_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_PEER_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_PEER_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_PEER_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_PEER_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_PEER_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_PEER_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_PEER_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_PEER_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_PEER_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_PEER_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_PEER_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_PEER_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_PEER_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_PEER_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_PEER_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_PEER_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_PEER_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_PEER_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_PEER_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_PEER_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_PEER_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_PEER_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_PF_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_PF_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_PF_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_PF_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_PF_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_PF_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_PF_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_PF_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_PF_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_PF_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_PF_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_PF_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_PF_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_PF_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_PF_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_PF_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_PF_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_PF_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_PF_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_PF_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_PF_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_PF_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_PF_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_PF_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_PF_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_PF_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_PF_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_PF_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_PF_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_PF_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_PF_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_PF_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_PF_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_PF_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_PF_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_PF_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_PF_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_PF_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_PF_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_PF_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_PF_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_PF_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_PF_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_PF_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_PF_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_PF_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_PF_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_PF_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_PF_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_PF_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_PF_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_PF_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_PF_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_PF_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_PF_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_PF_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_PF_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_PF_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_PF_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_PF_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_PF_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_PF_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_PF_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_PF_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT__VI 0x00000000 -#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT__VI 0x00000000 -#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT__VI 0x00000001 -#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT__VI 0x00000002 -#define SRBM_READ_ERROR2__READ_VFID__SHIFT__VI 0x00000018 -#define SRBM_READ_ERROR2__READ_VF__SHIFT__VI 0x00000017 -#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT__VI 0x00000017 -#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT__VI 0x0000001b -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT__VI 0x00000013 -#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT__VI 0x00000012 -#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT__VI 0x00000014 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_SDMA0_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_SDMA0_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SMU_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_SMU_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_SMU_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_SMU_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_SMU_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_SMU_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_SMU_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_SMU_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_SMU_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_SMU_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_SMU_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_SMU_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_SMU_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_SMU_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_SMU_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_SMU_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_SMU_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_SMU_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_SMU_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_SMU_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_SMU_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_SMU_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_SMU_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_SMU_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_SMU_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_SMU_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_SMU_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_SMU_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_SMU_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_SMU_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_SMU_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_SMU_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_SMU_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_SMU_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_SMU_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_SMU_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_SMU_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_SMU_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_SMU_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_SMU_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_SMU_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_SMU_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_SMU_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_SMU_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_SMU_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_SMU_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_SMU_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_SMU_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_SMU_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_SMU_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_SMU_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_SMU_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_SMU_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_SMU_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_SMU_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_SMU_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_SMU_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_SMU_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_SMU_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_SMU_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_SMU_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_SMU_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_SMU_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_SMU_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT__VI 0x00000000 -#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT__VI 0x0000000d -#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT__VI 0x00000004 -#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT__VI 0x0000001d -#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT__VI 0x0000001e -#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT__VI 0x00000017 -#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT__VI 0x0000001b -#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT__VI 0x0000001c -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT__VI 0x00000003 -#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT__VI 0x00000002 -#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT__VI 0x00000018 -#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT__VI 0x0000001f -#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT__VI 0x00000013 -#define SRBM_STATUS2__ISP_BUSY__SHIFT__VI 0x0000000d -#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT__VI 0x00000013 -#define SRBM_STATUS2__ODE_BUSY__SHIFT__VI 0x0000000f -#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT__VI 0x0000000c -#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT__VI 0x00000012 -#define SRBM_STATUS2__SDMA2_BUSY__SHIFT__VI 0x0000000a -#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT__VI 0x00000010 -#define SRBM_STATUS2__SDMA3_BUSY__SHIFT__VI 0x0000000b -#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT__VI 0x00000011 -#define SRBM_STATUS2__VCE0_BUSY__SHIFT__VI 0x00000007 -#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT__VI 0x00000003 -#define SRBM_STATUS2__VCE1_BUSY__SHIFT__VI 0x0000000e -#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT__VI 0x00000014 -#define SRBM_STATUS2__VP8_BUSY__SHIFT__VI 0x00000004 -#define SRBM_STATUS3__MCC0_BUSY__SHIFT__VI 0x00000000 -#define SRBM_STATUS3__MCC1_BUSY__SHIFT__VI 0x00000001 -#define SRBM_STATUS3__MCC2_BUSY__SHIFT__VI 0x00000002 -#define SRBM_STATUS3__MCC3_BUSY__SHIFT__VI 0x00000003 -#define SRBM_STATUS3__MCC4_BUSY__SHIFT__VI 0x00000004 -#define SRBM_STATUS3__MCC5_BUSY__SHIFT__VI 0x00000005 -#define SRBM_STATUS3__MCC6_BUSY__SHIFT__VI 0x00000006 -#define SRBM_STATUS3__MCC7_BUSY__SHIFT__VI 0x00000007 -#define SRBM_STATUS3__MCD0_BUSY__SHIFT__VI 0x00000008 -#define SRBM_STATUS3__MCD1_BUSY__SHIFT__VI 0x00000009 -#define SRBM_STATUS3__MCD2_BUSY__SHIFT__VI 0x0000000a -#define SRBM_STATUS3__MCD3_BUSY__SHIFT__VI 0x0000000b -#define SRBM_STATUS3__MCD4_BUSY__SHIFT__VI 0x0000000c -#define SRBM_STATUS3__MCD5_BUSY__SHIFT__VI 0x0000000d -#define SRBM_STATUS3__MCD6_BUSY__SHIFT__VI 0x0000000e -#define SRBM_STATUS3__MCD7_BUSY__SHIFT__VI 0x0000000f -#define SRBM_STATUS3__SECURE_MODE__SHIFT__VI 0x00000010 -#define SRBM_STATUS__GCATCL2_BUSY__SHIFT__VI 0x00000015 -#define SRBM_STATUS__OSATCL2_BUSY__SHIFT__VI 0x00000016 -#define SRBM_STATUS__SAMMSP_BUSY__SHIFT__VI 0x00000014 -#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT__VI 0x00000002 -#define SRBM_STATUS__VMC1_BUSY__SHIFT__VI 0x0000000d -#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_TST_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_TST_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_TST_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_TST_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_TST_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_TST_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_TST_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_TST_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_TST_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_TST_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_TST_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_TST_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_TST_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_TST_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_TST_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_TST_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_TST_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_TST_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_TST_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_TST_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_TST_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_TST_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_TST_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_TST_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_TST_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_TST_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_TST_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_TST_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_TST_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_TST_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_TST_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_TST_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_TST_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_TST_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_TST_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_TST_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_TST_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_TST_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_TST_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_TST_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_TST_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_TST_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_TST_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_TST_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_TST_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_TST_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_TST_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_TST_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_TST_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_TST_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_TST_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_TST_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_TST_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_TST_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_TST_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_TST_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_TST_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_TST_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_TST_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_TST_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_TST_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_TST_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_TST_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_TST_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT__VI 0x00000000 -#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT__VI 0x00000000 -#define SRBM_VF_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_VF_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_VF_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_VF_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_VF_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_VF_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_VF_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_VF_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_VF_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_VF_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_VF_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_VF_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_VF_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_VF_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_VF_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_VF_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_VF_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_VF_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_VF_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_VF_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_VF_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_VF_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_VF_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_VF_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_VF_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_VF_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_VF_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_VF_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_VF_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_VF_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_VF_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_VF_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_VF_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_VF_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_VF_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_VF_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_VF_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_VF_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_VF_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_VF_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_VF_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_VF_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_VF_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_VF_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_VF_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_VF_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_VF_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_VF_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_VF_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_VF_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_VF_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_VF_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_VF_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_VF_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_VF_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_VF_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_VF_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_VF_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_VF_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_VF_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_VF_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_VF_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_VF_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_VF_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE0__SHIFT__VI 0x00000000 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE10__SHIFT__VI 0x0000000a -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE11__SHIFT__VI 0x0000000b -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE12__SHIFT__VI 0x0000000c -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE13__SHIFT__VI 0x0000000d -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE14__SHIFT__VI 0x0000000e -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE15__SHIFT__VI 0x0000000f -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE16__SHIFT__VI 0x00000010 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE17__SHIFT__VI 0x00000011 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE18__SHIFT__VI 0x00000012 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE19__SHIFT__VI 0x00000013 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE1__SHIFT__VI 0x00000001 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE20__SHIFT__VI 0x00000014 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE21__SHIFT__VI 0x00000015 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE22__SHIFT__VI 0x00000016 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE23__SHIFT__VI 0x00000017 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE24__SHIFT__VI 0x00000018 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE25__SHIFT__VI 0x00000019 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE26__SHIFT__VI 0x0000001a -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE27__SHIFT__VI 0x0000001b -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE28__SHIFT__VI 0x0000001c -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE29__SHIFT__VI 0x0000001d -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE2__SHIFT__VI 0x00000002 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE30__SHIFT__VI 0x0000001e -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE31__SHIFT__VI 0x0000001f -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE3__SHIFT__VI 0x00000003 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE4__SHIFT__VI 0x00000004 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE5__SHIFT__VI 0x00000005 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE6__SHIFT__VI 0x00000006 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE7__SHIFT__VI 0x00000007 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE8__SHIFT__VI 0x00000008 -#define SRBM_VIRHYP_PLT0__PERMISSION_PAGE9__SHIFT__VI 0x00000009 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE32__SHIFT__VI 0x00000000 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE33__SHIFT__VI 0x00000001 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE34__SHIFT__VI 0x00000002 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE35__SHIFT__VI 0x00000003 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE36__SHIFT__VI 0x00000004 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE37__SHIFT__VI 0x00000005 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE38__SHIFT__VI 0x00000006 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE39__SHIFT__VI 0x00000007 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE40__SHIFT__VI 0x00000008 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE41__SHIFT__VI 0x00000009 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE42__SHIFT__VI 0x0000000a -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE43__SHIFT__VI 0x0000000b -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE44__SHIFT__VI 0x0000000c -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE45__SHIFT__VI 0x0000000d -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE46__SHIFT__VI 0x0000000e -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE47__SHIFT__VI 0x0000000f -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE48__SHIFT__VI 0x00000010 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE49__SHIFT__VI 0x00000011 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE50__SHIFT__VI 0x00000012 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE51__SHIFT__VI 0x00000013 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE52__SHIFT__VI 0x00000014 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE53__SHIFT__VI 0x00000015 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE54__SHIFT__VI 0x00000016 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE55__SHIFT__VI 0x00000017 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE56__SHIFT__VI 0x00000018 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE57__SHIFT__VI 0x00000019 -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE58__SHIFT__VI 0x0000001a -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE59__SHIFT__VI 0x0000001b -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE60__SHIFT__VI 0x0000001c -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE61__SHIFT__VI 0x0000001d -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE62__SHIFT__VI 0x0000001e -#define SRBM_VIRHYP_PLT1__PERMISSION_PAGE63__SHIFT__VI 0x0000001f -#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT__VI 0x00000000 -#define SRBM_VIRT_RESET_REQ__PF__SHIFT__VI 0x0000001f -#define SRBM_VIRT_RESET_REQ__VF__SHIFT__VI 0x00000000 -#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT__VI 0x00000008 -#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT__VI 0x00000000 -#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT__VI 0x00000010 -#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT__VI 0x00000000 -#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT__VI 0x00000011 -#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT__VI 0x00000016 -#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT__VI 0x00000012 -#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT__VI 0x00000010 -#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT__VI 0x00000014 -#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT__VI 0x00000013 -#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT__VI 0x00000015 -#define SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT__VI 0x0000000f -#define SWRST_COMMAND_1__CMDCFGEN__SHIFT__VI 0x0000001d -#define SWRST_COMMAND_1__RESETCPM__SHIFT__VI 0x0000000f -#define SWRST_COMMAND_1__RESETHLTR__SHIFT__VI 0x0000000e -#define SWRST_COMMAND_1__RESETIMPARB0__SHIFT__VI 0x00000014 -#define SWRST_COMMAND_1__RESETIMPARB1__SHIFT__VI 0x00000015 -#define SWRST_COMMAND_1__RESETLANEMUX__SHIFT__VI 0x00000002 -#define SWRST_COMMAND_1__RESETLC__SHIFT__VI 0x00000006 -#define SWRST_COMMAND_1__RESETMNTR__SHIFT__VI 0x0000000d -#define SWRST_COMMAND_1__RESETPHY0__SHIFT__VI 0x00000018 -#define SWRST_COMMAND_1__RESETPHY1__SHIFT__VI 0x00000019 -#define SWRST_COMMAND_1__RESETPIF0__SHIFT__VI 0x00000010 -#define SWRST_COMMAND_1__RESETPIF1__SHIFT__VI 0x00000011 -#define SWRST_COMMAND_1__RESETPRBS__SHIFT__VI 0x00000001 -#define SWRST_COMMAND_1__RESETSRBM0__SHIFT__VI 0x00000004 -#define SWRST_COMMAND_1__RESETSRBM1__SHIFT__VI 0x00000005 -#define SWRST_COMMAND_1__RESETWRAPREGS__SHIFT__VI 0x00000003 -#define SWRST_COMMAND_1__SWITCHCLK__SHIFT__VI 0x00000000 -#define SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT__VI 0x00000008 -#define SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT__VI 0x00000009 -#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT__VI 0x0000001c -#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT__VI 0x00000001 -#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT__VI 0x00000000 -#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT__VI 0x00000010 -#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT__VI 0x00000011 -#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT__VI 0x00000011 -#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT__VI 0x00000016 -#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT__VI 0x00000012 -#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT__VI 0x00000010 -#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT__VI 0x00000014 -#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT__VI 0x00000013 -#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT__VI 0x00000015 -#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT__VI 0x0000000f -#define SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT__VI 0x0000001d -#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT__VI 0x0000000f -#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT__VI 0x0000000e -#define SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT__VI 0x00000014 -#define SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT__VI 0x00000015 -#define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT__VI 0x00000002 -#define SWRST_CONTROL_1__RESETLC_RCEN__SHIFT__VI 0x00000006 -#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT__VI 0x0000000d -#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT__VI 0x00000018 -#define SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT__VI 0x00000019 -#define SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT__VI 0x00000010 -#define SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT__VI 0x00000011 -#define SWRST_CONTROL_1__RESETPRBS_RCEN__SHIFT__VI 0x00000001 -#define SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT__VI 0x00000004 -#define SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT__VI 0x00000005 -#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT__VI 0x00000003 -#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT__VI 0x0000001c -#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT__VI 0x00000000 -#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT__VI 0x00000008 -#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT__VI 0x00000009 -#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT__VI 0x00000011 -#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT__VI 0x00000016 -#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT__VI 0x00000012 -#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT__VI 0x00000010 -#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT__VI 0x00000014 -#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT__VI 0x00000013 -#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT__VI 0x00000015 -#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT__VI 0x0000000f -#define SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT__VI 0x0000001d -#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT__VI 0x0000000f -#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT__VI 0x0000000e -#define SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT__VI 0x00000014 -#define SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT__VI 0x00000015 -#define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT__VI 0x00000002 -#define SWRST_CONTROL_3__RESETLC_ATEN__SHIFT__VI 0x00000006 -#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT__VI 0x0000000d -#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT__VI 0x00000018 -#define SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT__VI 0x00000019 -#define SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT__VI 0x00000010 -#define SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT__VI 0x00000011 -#define SWRST_CONTROL_3__RESETPRBS_ATEN__SHIFT__VI 0x00000001 -#define SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT__VI 0x00000004 -#define SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT__VI 0x00000005 -#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT__VI 0x00000003 -#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT__VI 0x0000001c -#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT__VI 0x00000000 -#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT__VI 0x00000008 -#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT__VI 0x00000009 -#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT__VI 0x00000011 -#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT__VI 0x00000016 -#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT__VI 0x00000012 -#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT__VI 0x00000010 -#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT__VI 0x00000014 -#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT__VI 0x00000013 -#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT__VI 0x00000015 -#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT__VI 0x0000000e -#define SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT__VI 0x0000001d -#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT__VI 0x0000000f -#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT__VI 0x0000000e -#define SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT__VI 0x00000014 -#define SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT__VI 0x00000015 -#define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT__VI 0x00000002 -#define SWRST_CONTROL_5__WRRESETLC_EN__SHIFT__VI 0x00000006 -#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT__VI 0x0000000d -#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT__VI 0x00000018 -#define SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT__VI 0x00000019 -#define SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT__VI 0x00000010 -#define SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT__VI 0x00000011 -#define SWRST_CONTROL_5__WRRESETPRBS_EN__SHIFT__VI 0x00000001 -#define SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT__VI 0x00000004 -#define SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT__VI 0x00000005 -#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT__VI 0x00000003 -#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT__VI 0x0000001c -#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT__VI 0x00000000 -#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT__VI 0x00000008 -#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT__VI 0x00000009 -#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT__VI 0x00000008 -#define SWRST_CONTROL_6__WARMRESET_EN__SHIFT__VI 0x00000000 -#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT__VI 0x00000000 -#define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT__VI 0x00000002 -#define SWRST_EP_COMMAND_0__EP_FLR0_RESET__SHIFT__VI 0x00000010 -#define SWRST_EP_COMMAND_0__EP_FLR1_RESET__SHIFT__VI 0x00000011 -#define SWRST_EP_COMMAND_0__EP_FLR2_RESET__SHIFT__VI 0x00000012 -#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT__VI 0x00000008 -#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT__VI 0x0000000a -#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT__VI 0x00000009 -#define SWRST_EP_COMMAND_0__EP_SOFT_RESET__SHIFT__VI 0x00000001 -#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT__VI 0x00000000 -#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN__SHIFT__VI 0x00000013 -#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT__VI 0x00000002 -#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN__SHIFT__VI 0x00000010 -#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN__SHIFT__VI 0x00000011 -#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN__SHIFT__VI 0x00000012 -#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST__SHIFT__VI 0x00000014 -#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT__VI 0x00000008 -#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT__VI 0x0000000a -#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT__VI 0x00000009 -#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN__SHIFT__VI 0x00000001 -#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT__VI 0x00000001 -#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT__VI 0x0000000a -#define SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT__VI 0x00000010 -#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT__VI 0x00000011 -#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT__VI 0x0000000c -#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN__SHIFT__VI 0x0000001c -#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR__SHIFT__VI 0x0000001d -#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT__VI 0x00000009 -#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT__VI 0x0000000e -#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT__VI 0x0000000d -#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT__VI 0x00000000 -#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT__VI 0x00000002 -#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT__VI 0x00000008 -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT__VI 0x00000001 -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT__VI 0x00000000 -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT__VI 0x00000005 -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT__VI 0x00000004 -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT__VI 0x00000009 -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT__VI 0x00000008 -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT__VI 0x0000000d -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT__VI 0x0000000c -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT__VI 0x00000011 -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT__VI 0x00000010 -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT__VI 0x00000015 -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT__VI 0x00000014 -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT__VI 0x00000019 -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT__VI 0x00000018 -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT__VI 0x0000001d -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT__VI 0x0000001c -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT__VI 0x0000001f -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT__VI 0x00000000 -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT__VI 0x00000004 -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT__VI 0x00000008 -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT__VI 0x0000000c -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT__VI 0x00000010 -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT__VI 0x00000014 -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT__VI 0x00000018 -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT__VI 0x0000001c -#define SX_DEBUG_1__DEBUG_DATA__SHIFT__SI__CI 0x00000007 -#define SX_DEBUG_1__DEBUG_DATA__SHIFT__VI 0x0000000d -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT__VI 0x00000009 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT__VI 0x0000000a -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT__VI 0x00000008 -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT__VI 0x0000000c -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT__VI 0x0000000b -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT__VI 0x00000018 -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT__VI 0x00000014 -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT__VI 0x00000010 -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT__VI 0x00000008 -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT__VI 0x00000004 -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT__VI 0x00000000 -#define SX_PS_DOWNCONVERT__MRT0__SHIFT__VI 0x00000000 -#define SX_PS_DOWNCONVERT__MRT1__SHIFT__VI 0x00000004 -#define SX_PS_DOWNCONVERT__MRT2__SHIFT__VI 0x00000008 -#define SX_PS_DOWNCONVERT__MRT3__SHIFT__VI 0x0000000c -#define SX_PS_DOWNCONVERT__MRT4__SHIFT__VI 0x00000010 -#define SX_PS_DOWNCONVERT__MRT5__SHIFT__VI 0x00000014 -#define SX_PS_DOWNCONVERT__MRT6__SHIFT__VI 0x00000018 -#define SX_PS_DOWNCONVERT__MRT7__SHIFT__VI 0x0000001c -#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT__VI 0x0000001e -#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT__VI 0x00000000 -#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT__VI 0x0000001f -#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT__VI 0x00000010 -#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT__VI 0x0000001d -#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT__VI 0x00000008 -#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT__VI 0x00000000 -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT__VI 0x00000013 -#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT__VI 0x00000011 -#define TA_CNTL_AUX__ANISO_TAP__SHIFT__VI 0x00000012 -#define TA_CNTL_AUX__D16_PACK_DISABLE__SHIFT__VI 0x00000004 -#define TA_CNTL_AUX__RESERVED__SHIFT__VI 0x00000001 -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT__VI 0x00000000 -#define TA_CNTL__FX_XNACK_CREDIT__SHIFT__VI 0x00000000 -#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT__VI 0x00000009 -#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT__VI 0x0000001a -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT__VI 0x0000001c -#define TCC_CTRL__MDC_SIZE__SHIFT__VI 0x00000018 -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT__VI 0x00000008 -#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT__VI 0x00000000 -#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT__VI 0x00000002 -#define TCC_EDC_CNT__DED_COUNT__SHIFT__VI 0x00000010 -#define TCC_EDC_CNT__SEC_COUNT__SHIFT__VI 0x00000000 -#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT__VI 0x00000001 -#define TCC_EXE_DISABLE__WRITE_DIS__SHIFT__VI 0x00000000 -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT__VI 0x00000000 -#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT__VI 0x00000000 -#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT__VI 0x00000000 -#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT__VI 0x00000002 -#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT__VI 0x00000003 -#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT__VI 0x00000005 -#define TCP_EDC_CNT__DED_COUNT__SHIFT__VI 0x00000010 -#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT__VI 0x00000008 -#define TCP_EDC_CNT__SEC_COUNT__SHIFT__VI 0x00000000 -#define TCP_EDC_CNT__UNUSED__SHIFT__VI 0x00000018 -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT__VI 0x0000001b -#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT__VI 0x0000001a -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT__VI 0x00000019 -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT__VI 0x0000001e -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT__VI 0x0000001c -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT__VI 0x00000000 -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT__VI 0x00000001 -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT__VI 0x00000002 -#define TCP_STATUS__ADRS_BUSY__SHIFT__VI 0x00000002 -#define TCP_STATUS__CNTRL_BUSY__SHIFT__VI 0x00000004 -#define TCP_STATUS__FORMAT_BUSY__SHIFT__VI 0x00000007 -#define TCP_STATUS__INPUT_BUSY__SHIFT__VI 0x00000001 -#define TCP_STATUS__LFIFO_BUSY__SHIFT__VI 0x00000005 -#define TCP_STATUS__READ_BUSY__SHIFT__VI 0x00000006 -#define TCP_STATUS__TAGRAMS_BUSY__SHIFT__VI 0x00000003 -#define TCP_WATCH0_CNTL__ATC__SHIFT__VI 0x0000001c -#define TCP_WATCH1_CNTL__ATC__SHIFT__VI 0x0000001c -#define TCP_WATCH2_CNTL__ATC__SHIFT__VI 0x0000001c -#define TCP_WATCH3_CNTL__ATC__SHIFT__VI 0x0000001c -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT__VI 0x00000017 -#define TD_CNTL__DISABLE_D16_PACKING__SHIFT__VI 0x00000016 -#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT__VI 0x00000015 -#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT__VI 0x00000002 -#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT__VI 0x00000000 -#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT__VI 0x00000001 -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT__VI 0x00000004 -#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT__VI 0x00000000 -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT__VI 0x00000000 -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT__VI 0x00000009 -#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT__VI 0x0000000b -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT__VI 0x00000016 -#define VGT_GS_MODE__RESERVED_3__SHIFT__VI 0x0000000e -#define VGT_GS_MODE__RESERVED_4__SHIFT__VI 0x0000000f -#define VGT_GS_MODE__RESERVED_5__SHIFT__VI 0x00000010 -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT__VI 0x00000009 -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT__VI 0x0000000a -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT__VI 0x0000000b -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT__VI 0x0000000c -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT__VI 0x00000000 -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT__VI 0x00000010 -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT__VI 0x00000008 -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT__VI 0x00000018 -#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT__VI 0x00000011 -#define VGT_TF_PARAM__MTYPE__SHIFT__VI 0x00000013 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT__VI 0x00000016 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT__VI 0x00000015 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT__VI 0x00000017 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT__VI 0x00000016 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT__VI 0x00000015 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT__VI 0x00000017 -#define VM_INIT_STATUS__VM_INIT_STATUS__SHIFT__VI 0x00000000 -#define VM_L2_CG__OVERRIDE__SHIFT__VI 0x00000014 -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT__VI 0x00000000 -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT__VI 0x00000006 -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_SHARED__SHIFT__VI 0x00000007 -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_SNOOP__SHIFT__VI 0x00000008 -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT__VI 0x00000009 -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_SHARED__SHIFT__VI 0x0000000a -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_SNOOP__SHIFT__VI 0x0000000b -#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT__VI 0x00000008 -#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT__VI 0x00000009 -#define WD_DEBUG_REG10__eop_p1_q__SHIFT__VI 0x0000000f -#define WD_DEBUG_REG10__eopg_p1_q__SHIFT__VI 0x0000000e -#define WD_DEBUG_REG10__is_event_p1_q__SHIFT__VI 0x0000000d -#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT__VI 0x0000000c -#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT__VI 0x0000000b -#define WD_DEBUG_REG10__patch_accum_q__SHIFT__VI 0x00000010 -#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT__VI 0x0000000a -#define WD_DEBUG_REG10__pipe0_dr__SHIFT__VI 0x00000004 -#define WD_DEBUG_REG10__pipe0_rtr__SHIFT__VI 0x00000006 -#define WD_DEBUG_REG10__pipe1_dr__SHIFT__VI 0x00000005 -#define WD_DEBUG_REG10__pipe1_rtr__SHIFT__VI 0x00000007 -#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT__VI 0x00000003 -#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT__VI 0x00000002 -#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT__VI 0x00000001 -#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT__VI 0x00000000 -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT__VI 0x00000019 -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT__VI 0x00000018 -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT__VI 0x0000001b -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT__VI 0x0000001a -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT__VI 0x0000001d -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT__VI 0x0000001c -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT__VI 0x0000001f -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT__VI 0x0000001e -#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT__VI 0x00000000 -#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT__VI 0x00000000 -#define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in__SHIFT__VI 0x00000004 -#define WD_DEBUG_REG7__SPARE1__SHIFT__VI 0x00000008 -#define WD_DEBUG_REG7__SPARE2__SHIFT__VI 0x0000000c -#define WD_DEBUG_REG7__SPARE5__SHIFT__VI 0x00000013 -#define WD_DEBUG_REG7__SPARE6__SHIFT__VI 0x00000018 -#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT__VI 0x0000001e -#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT__VI 0x0000001d -#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT__VI 0x00000015 -#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT__VI 0x00000014 -#define WD_DEBUG_REG7__se1_thdgrp_eop__SHIFT__VI 0x00000017 -#define WD_DEBUG_REG7__se1_thdgrp_is_event__SHIFT__VI 0x00000016 -#define WD_DEBUG_REG7__te11_arb_busy__SHIFT__VI 0x0000001f -#define WD_DEBUG_REG7__te11_arb_state_q__SHIFT__VI 0x00000010 -#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT__VI 0x0000001c -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT__VI 0x00000002 -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT__VI 0x00000003 -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT__VI 0x00000001 -#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty__SHIFT__VI 0x00000006 -#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full__SHIFT__VI 0x00000007 -#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re__SHIFT__VI 0x00000005 -#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT__VI 0x0000001f -#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT__VI 0x0000001e -#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT__VI 0x0000001d -#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT__VI 0x00000012 -#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT__VI 0x0000001c -#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT__VI 0x0000000b -#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT__VI 0x00000013 -#define WD_DEBUG_REG8__pipe0_dr__SHIFT__VI 0x00000000 -#define WD_DEBUG_REG8__pipe0_rtr__SHIFT__VI 0x00000002 -#define WD_DEBUG_REG8__pipe1_dr__SHIFT__VI 0x00000001 -#define WD_DEBUG_REG8__pipe1_rtr__SHIFT__VI 0x00000003 -#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT__VI 0x0000000c -#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT__VI 0x0000001b -#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT__VI 0x00000006 -#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT__VI 0x00000014 -#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT__VI 0x00000007 -#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT__VI 0x00000008 -#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT__VI 0x00000009 -#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT__VI 0x00000004 -#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT__VI 0x00000005 -#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT__VI 0x0000000a -#define WD_DEBUG_REG9__SPARE0__SHIFT__VI 0x0000000b -#define WD_DEBUG_REG9__SPARE1__SHIFT__VI 0x0000001b -#define WD_DEBUG_REG9__SPARE2__SHIFT__VI 0x0000001c -#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT__VI 0x00000018 -#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT__VI 0x00000003 -#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT__VI 0x00000019 -#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT__VI 0x00000013 -#define WD_DEBUG_REG9__mem_is_even__SHIFT__VI 0x0000001a -#define WD_DEBUG_REG9__pipe0_dr__SHIFT__VI 0x00000000 -#define WD_DEBUG_REG9__pipe0_rtr__SHIFT__VI 0x00000004 -#define WD_DEBUG_REG9__pipe1_rtr__SHIFT__VI 0x00000005 -#define WD_DEBUG_REG9__pipe2_dr__SHIFT__VI 0x00000002 -#define WD_DEBUG_REG9__pipe2_rtr__SHIFT__VI 0x00000007 -#define WD_DEBUG_REG9__pipe4_dr__SHIFT__VI 0x0000001e -#define WD_DEBUG_REG9__pipe4_rtr__SHIFT__VI 0x0000001f -#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT__VI 0x00000001 -#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT__VI 0x00000006 -#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT__VI 0x00000010 -#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT__VI 0x00000014 -#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT__VI 0x00000009 -#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT__VI 0x00000008 -#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT__VI 0x0000000a -#define WD_QOS__DRAW_STALL__SHIFT__VI 0x00000000 - -#endif // SI_CI_VI_merged_shift_HEADER diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_sq_reg.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_sq_reg.h deleted file mode 100644 index cf629314c1..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_sq_reg.h +++ /dev/null @@ -1,15476 +0,0 @@ -#if !defined SI_CI_VI_merged_sq_reg_HEADER -#define SI_CI_VI_merged_sq_reg_HEADER - - -// -// Source merge files: -// E:\MergedHeaders\SI+CI+Amur\Original\SICI/si_ci_merged_sq_reg.h -// E:\MergedHeaders\SI+CI+Amur\Original\Amur/vi_sq_reg.h -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -#define CC_SQC_BANK_DISABLE_DEFAULT 0x00000000 -#define CC_SQC_BANK_DISABLE_REG_SIZE 32 -#define CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK 0x000f0000 -#define CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SHIFT 16 -#define CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SIZE 4 -#define CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK 0x00f00000 -#define CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SHIFT 20 -#define CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SIZE 4 -#define CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK__CI__VI 0x0f000000 -#define CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SHIFT__CI__VI 24 -#define CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SIZE__CI__VI 4 -#define CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK__CI__VI 0xf0000000 -#define CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SHIFT__CI__VI 28 -#define CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SIZE__CI__VI 4 -#define CC_SQC_BANK_DISABLE_WRITE_DIS_MASK 0x00000001 -#define CC_SQC_BANK_DISABLE_WRITE_DIS_SHIFT 0x00000000 -#define CC_SQC_BANK_DISABLE_WRITE_DIS_SIZE 1 -#define CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_MASK 0x40000000 -#define CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_SHIFT 30 -#define CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_SIZE 1 -#define CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_MASK 0x00000ff0 -#define CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_SHIFT 4 -#define CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_SIZE 8 -#define CGTT_SQG_CLK_CTRL_ON_DELAY_MASK 0x0000000f -#define CGTT_SQG_CLK_CTRL_ON_DELAY_SHIFT 0x00000000 -#define CGTT_SQG_CLK_CTRL_ON_DELAY_SIZE 4 -#define CGTT_SQG_CLK_CTRL_REG_OVERRIDE_MASK 0x80000000 -#define CGTT_SQG_CLK_CTRL_REG_OVERRIDE_SHIFT 31 -#define CGTT_SQG_CLK_CTRL_REG_OVERRIDE_SIZE 1 -#define CGTT_SQG_CLK_CTRL_REG_SIZE 32 -#define CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_MASK 0x40000000 -#define CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_SHIFT 30 -#define CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_SIZE 1 -#define CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_MASK 0x00000ff0 -#define CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_SHIFT 4 -#define CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_SIZE 8 -#define CGTT_SQ_CLK_CTRL_ON_DELAY_MASK 0x0000000f -#define CGTT_SQ_CLK_CTRL_ON_DELAY_SHIFT 0x00000000 -#define CGTT_SQ_CLK_CTRL_ON_DELAY_SIZE 4 -#define CGTT_SQ_CLK_CTRL_REG_OVERRIDE_MASK 0x80000000 -#define CGTT_SQ_CLK_CTRL_REG_OVERRIDE_SHIFT 31 -#define CGTT_SQ_CLK_CTRL_REG_OVERRIDE_SIZE 1 -#define CGTT_SQ_CLK_CTRL_REG_SIZE 32 -#define INST_ID_ECC_INTERRUPT_MSG__CI__VI 0xfffffff0 -#define INST_ID_HOST_REG_TRAP_MSG__CI__VI 0xfffffffe -#define INST_ID_HW_TRAP__CI__VI 0xfffffff2 -#define INST_ID_KILL_SEQ__CI__VI 0xfffffff3 -#define INST_ID_TTRACE_NEW_PC_MSG__CI__VI 0xfffffff1 -#define SH_MEM_APE1_BASE_BASE_MASK__CI__VI 0xffffffff -#define SH_MEM_APE1_BASE_BASE_SHIFT__CI__VI 0x00000000 -#define SH_MEM_APE1_BASE_BASE_SIZE__CI__VI 32 -#define SH_MEM_APE1_BASE_DEFAULT__CI__VI 0x00000001 -#define SH_MEM_APE1_BASE_REG_SIZE__CI__VI 32 -#define SH_MEM_APE1_LIMIT_DEFAULT__CI__VI 0x00000000 -#define SH_MEM_APE1_LIMIT_LIMIT_MASK__CI__VI 0xffffffff -#define SH_MEM_APE1_LIMIT_LIMIT_SHIFT__CI__VI 0x00000000 -#define SH_MEM_APE1_LIMIT_LIMIT_SIZE__CI__VI 32 -#define SH_MEM_APE1_LIMIT_REG_SIZE__CI__VI 32 -#define SH_MEM_BASES_DEFAULT__CI__VI 0x00000000 -#define SH_MEM_BASES_PRIVATE_BASE_MASK__CI__VI 0x0000ffff -#define SH_MEM_BASES_PRIVATE_BASE_SHIFT__CI__VI 0x00000000 -#define SH_MEM_BASES_PRIVATE_BASE_SIZE__CI__VI 16 -#define SH_MEM_BASES_REG_SIZE__CI__VI 32 -#define SH_MEM_BASES_SHARED_BASE_MASK__CI__VI 0xffff0000 -#define SH_MEM_BASES_SHARED_BASE_SHIFT__CI__VI 16 -#define SH_MEM_BASES_SHARED_BASE_SIZE__CI__VI 16 -#define SH_MEM_CONFIG_ALIGNMENT_MODE_MASK__CI 0x0000000c -#define SH_MEM_CONFIG_ALIGNMENT_MODE_SHIFT__CI 2 -#define SH_MEM_CONFIG_ALIGNMENT_MODE_SIZE__CI__VI 2 -#define SH_MEM_CONFIG_APE1_MTYPE_MASK__CI 0x00000380 -#define SH_MEM_CONFIG_APE1_MTYPE_SHIFT__CI 7 -#define SH_MEM_CONFIG_APE1_MTYPE_SIZE__CI__VI 3 -#define SH_MEM_CONFIG_DEFAULT_MTYPE_MASK__CI 0x00000070 -#define SH_MEM_CONFIG_DEFAULT_MTYPE_SHIFT__CI 4 -#define SH_MEM_CONFIG_DEFAULT_MTYPE_SIZE__CI__VI 3 -#define SH_MEM_CONFIG_DEFAULT__CI__VI 0x00000000 -#define SH_MEM_CONFIG_PRIVATE_ATC_MASK__CI 0x00000002 -#define SH_MEM_CONFIG_PRIVATE_ATC_SHIFT__CI 1 -#define SH_MEM_CONFIG_PRIVATE_ATC_SIZE__CI__VI 1 -#define SH_MEM_CONFIG_PTR32_MASK__CI 0x00000001 -#define SH_MEM_CONFIG_PTR32_SHIFT__CI 0x00000000 -#define SH_MEM_CONFIG_PTR32_SIZE__CI 1 -#define SH_MEM_CONFIG_REG_SIZE__CI__VI 32 -#define SQC_CACHES_DATA_INVALIDATE_MASK__SI__CI 0x00000002 -#define SQC_CACHES_DATA_INVALIDATE_SHIFT__SI__CI 1 -#define SQC_CACHES_DATA_INVALIDATE_SIZE__SI__CI 1 -#define SQC_CACHES_DEFAULT 0x00000000 -#define SQC_CACHES_INST_INVALIDATE_MASK__SI__CI 0x00000001 -#define SQC_CACHES_INST_INVALIDATE_SHIFT__SI__CI 0x00000000 -#define SQC_CACHES_INST_INVALIDATE_SIZE__SI__CI 1 -#define SQC_CACHES_INVALIDATE_VOLATILE_MASK__CI 0x00000004 -#define SQC_CACHES_INVALIDATE_VOLATILE_SHIFT__CI 2 -#define SQC_CACHES_INVALIDATE_VOLATILE_SIZE__CI 1 -#define SQC_CACHES_REG_SIZE 32 -#define SQC_CONFIG_DATA_CACHE_SIZE_MASK 0x0000000c -#define SQC_CONFIG_DATA_CACHE_SIZE_SHIFT 2 -#define SQC_CONFIG_DATA_CACHE_SIZE_SIZE 2 -#define SQC_CONFIG_FORCE_ALWAYS_MISS_MASK 0x00000080 -#define SQC_CONFIG_FORCE_ALWAYS_MISS_SHIFT 7 -#define SQC_CONFIG_FORCE_ALWAYS_MISS_SIZE 1 -#define SQC_CONFIG_FORCE_IN_ORDER_MASK 0x00000100 -#define SQC_CONFIG_FORCE_IN_ORDER_SHIFT 8 -#define SQC_CONFIG_FORCE_IN_ORDER_SIZE 1 -#define SQC_CONFIG_HIT_FIFO_DEPTH_MASK 0x00000040 -#define SQC_CONFIG_HIT_FIFO_DEPTH_SHIFT 6 -#define SQC_CONFIG_HIT_FIFO_DEPTH_SIZE 1 -#define SQC_CONFIG_IDENTITY_HASH_BANK_MASK 0x00000200 -#define SQC_CONFIG_IDENTITY_HASH_BANK_SHIFT 9 -#define SQC_CONFIG_IDENTITY_HASH_BANK_SIZE 1 -#define SQC_CONFIG_IDENTITY_HASH_SET_MASK 0x00000400 -#define SQC_CONFIG_IDENTITY_HASH_SET_SHIFT 10 -#define SQC_CONFIG_IDENTITY_HASH_SET_SIZE 1 -#define SQC_CONFIG_INST_CACHE_SIZE_MASK 0x00000003 -#define SQC_CONFIG_INST_CACHE_SIZE_SHIFT 0x00000000 -#define SQC_CONFIG_INST_CACHE_SIZE_SIZE 2 -#define SQC_CONFIG_MISS_FIFO_DEPTH_MASK 0x00000030 -#define SQC_CONFIG_MISS_FIFO_DEPTH_SHIFT 4 -#define SQC_CONFIG_MISS_FIFO_DEPTH_SIZE 2 -#define SQC_CONFIG_PER_VMID_INV_DISABLE_MASK__CI__VI 0x00000800 -#define SQC_CONFIG_PER_VMID_INV_DISABLE_SHIFT__CI__VI 11 -#define SQC_CONFIG_PER_VMID_INV_DISABLE_SIZE__CI__VI 1 -#define SQC_CONFIG_REG_SIZE 32 -#define SQC_POLICY_DATA_L1_POLICY_0_MASK__CI 0x00000001 -#define SQC_POLICY_DATA_L1_POLICY_0_SHIFT__CI 0x00000000 -#define SQC_POLICY_DATA_L1_POLICY_0_SIZE__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_1_MASK__CI 0x00000002 -#define SQC_POLICY_DATA_L1_POLICY_1_SHIFT__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_1_SIZE__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_2_MASK__CI 0x00000004 -#define SQC_POLICY_DATA_L1_POLICY_2_SHIFT__CI 2 -#define SQC_POLICY_DATA_L1_POLICY_2_SIZE__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_3_MASK__CI 0x00000008 -#define SQC_POLICY_DATA_L1_POLICY_3_SHIFT__CI 3 -#define SQC_POLICY_DATA_L1_POLICY_3_SIZE__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_4_MASK__CI 0x00000010 -#define SQC_POLICY_DATA_L1_POLICY_4_SHIFT__CI 4 -#define SQC_POLICY_DATA_L1_POLICY_4_SIZE__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_5_MASK__CI 0x00000020 -#define SQC_POLICY_DATA_L1_POLICY_5_SHIFT__CI 5 -#define SQC_POLICY_DATA_L1_POLICY_5_SIZE__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_6_MASK__CI 0x00000040 -#define SQC_POLICY_DATA_L1_POLICY_6_SHIFT__CI 6 -#define SQC_POLICY_DATA_L1_POLICY_6_SIZE__CI 1 -#define SQC_POLICY_DATA_L1_POLICY_7_MASK__CI 0x00000080 -#define SQC_POLICY_DATA_L1_POLICY_7_SHIFT__CI 7 -#define SQC_POLICY_DATA_L1_POLICY_7_SIZE__CI 1 -#define SQC_POLICY_DATA_L2_POLICY_0_MASK__CI 0x00000300 -#define SQC_POLICY_DATA_L2_POLICY_0_SHIFT__CI 8 -#define SQC_POLICY_DATA_L2_POLICY_0_SIZE__CI 2 -#define SQC_POLICY_DATA_L2_POLICY_1_MASK__CI 0x00000c00 -#define SQC_POLICY_DATA_L2_POLICY_1_SHIFT__CI 10 -#define SQC_POLICY_DATA_L2_POLICY_1_SIZE__CI 2 -#define SQC_POLICY_DATA_L2_POLICY_2_MASK__CI 0x00003000 -#define SQC_POLICY_DATA_L2_POLICY_2_SHIFT__CI 12 -#define SQC_POLICY_DATA_L2_POLICY_2_SIZE__CI 2 -#define SQC_POLICY_DATA_L2_POLICY_3_MASK__CI 0x0000c000 -#define SQC_POLICY_DATA_L2_POLICY_3_SHIFT__CI 14 -#define SQC_POLICY_DATA_L2_POLICY_3_SIZE__CI 2 -#define SQC_POLICY_DATA_L2_POLICY_4_MASK__CI 0x00030000 -#define SQC_POLICY_DATA_L2_POLICY_4_SHIFT__CI 16 -#define SQC_POLICY_DATA_L2_POLICY_4_SIZE__CI 2 -#define SQC_POLICY_DATA_L2_POLICY_5_MASK__CI 0x000c0000 -#define SQC_POLICY_DATA_L2_POLICY_5_SHIFT__CI 18 -#define SQC_POLICY_DATA_L2_POLICY_5_SIZE__CI 2 -#define SQC_POLICY_DATA_L2_POLICY_6_MASK__CI 0x00300000 -#define SQC_POLICY_DATA_L2_POLICY_6_SHIFT__CI 20 -#define SQC_POLICY_DATA_L2_POLICY_6_SIZE__CI 2 -#define SQC_POLICY_DATA_L2_POLICY_7_MASK__CI 0x00c00000 -#define SQC_POLICY_DATA_L2_POLICY_7_SHIFT__CI 22 -#define SQC_POLICY_DATA_L2_POLICY_7_SIZE__CI 2 -#define SQC_POLICY_DEFAULT__CI 0x00808000 -#define SQC_POLICY_INST_L2_POLICY_MASK__CI 0x03000000 -#define SQC_POLICY_INST_L2_POLICY_SHIFT__CI 24 -#define SQC_POLICY_INST_L2_POLICY_SIZE__CI 2 -#define SQC_POLICY_REG_SIZE__CI 32 -#define SQC_SECDED_CNT_DATA_DED_MASK__SI__CI 0xff000000 -#define SQC_SECDED_CNT_DATA_DED_SHIFT__SI__CI 24 -#define SQC_SECDED_CNT_DATA_DED_SIZE__SI__CI 8 -#define SQC_SECDED_CNT_DATA_SEC_MASK__SI__CI 0x00ff0000 -#define SQC_SECDED_CNT_DATA_SEC_SHIFT__SI__CI 16 -#define SQC_SECDED_CNT_DATA_SEC_SIZE__SI__CI 8 -#define SQC_SECDED_CNT_DEFAULT__SI__CI 0x00000000 -#define SQC_SECDED_CNT_INST_DED_MASK__SI__CI 0x0000ff00 -#define SQC_SECDED_CNT_INST_DED_SHIFT__SI__CI 8 -#define SQC_SECDED_CNT_INST_DED_SIZE__SI__CI 8 -#define SQC_SECDED_CNT_INST_SEC_MASK__SI__CI 0x000000ff -#define SQC_SECDED_CNT_INST_SEC_SHIFT__SI__CI 0x00000000 -#define SQC_SECDED_CNT_INST_SEC_SIZE__SI__CI 8 -#define SQC_SECDED_CNT_REG_SIZE__SI__CI 32 -#define SQC_VOLATILE_DATA_L1_MASK__CI 0x0000000f -#define SQC_VOLATILE_DATA_L1_SHIFT__CI 0x00000000 -#define SQC_VOLATILE_DATA_L1_SIZE__CI 4 -#define SQC_VOLATILE_DATA_L2_MASK__CI 0x000000f0 -#define SQC_VOLATILE_DATA_L2_SHIFT__CI 4 -#define SQC_VOLATILE_DATA_L2_SIZE__CI 4 -#define SQC_VOLATILE_DEFAULT__CI 0x0000004e -#define SQC_VOLATILE_INST_L2_MASK__CI 0x00000100 -#define SQC_VOLATILE_INST_L2_SHIFT__CI 8 -#define SQC_VOLATILE_INST_L2_SIZE__CI 1 -#define SQC_VOLATILE_REG_SIZE__CI 32 -#define SQDEC_BEGIN 0x00002300 -#define SQDEC_END 0x000023ff -#define SQGFXUDEC_BEGIN__CI 0x0000c340 -#define SQGFXUDEC_END__CI__VI 0x0000c380 -#define SQIND_GLOBAL_REGS_OFFSET 0x00000000 -#define SQIND_GLOBAL_REGS_SIZE 0x00000008 -#define SQIND_LOCAL_REGS_OFFSET 0x00000008 -#define SQIND_LOCAL_REGS_SIZE 0x00000008 -#define SQIND_WAVE_HWREGS_OFFSET 0x00000010 -#define SQIND_WAVE_HWREGS_SIZE 0x000001f0 -#define SQIND_WAVE_SGPRS_OFFSET 0x00000200 -#define SQIND_WAVE_SGPRS_SIZE 0x00000200 -#define SQPERFDDEC_BEGIN__CI__VI 0x0000d1c0 -#define SQPERFDDEC_END__CI__VI 0x0000d240 -#define SQPERFSDEC_BEGIN__CI__VI 0x0000d9c0 -#define SQPERFSDEC_END__CI__VI 0x0000da40 -#define SQPWRDEC_BEGIN__CI__VI 0x0000f08c -#define SQPWRDEC_END__CI__VI 0x0000f094 -#define SQ_ALU_CLK_CTRL_DEFAULT 0x00000000 -#define SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_MASK 0x0000ffff -#define SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT 0x00000000 -#define SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_SIZE 16 -#define SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_MASK 0xffff0000 -#define SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT 16 -#define SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_SIZE 16 -#define SQ_ALU_CLK_CTRL_REG_SIZE 32 -#define SQ_BUF_RSRC_WORD0_BASE_ADDRESS_MASK 0xffffffff -#define SQ_BUF_RSRC_WORD0_BASE_ADDRESS_SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD0_BASE_ADDRESS_SIZE 32 -#define SQ_BUF_RSRC_WORD0_REG_SIZE 32 -#define SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_MASK 0x0000ffff -#define SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_SIZE 16 -#define SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_MASK 0x40000000 -#define SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_SHIFT 30 -#define SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_SIZE 1 -#define SQ_BUF_RSRC_WORD1_REG_SIZE 32 -#define SQ_BUF_RSRC_WORD1_STRIDE_MASK 0x3fff0000 -#define SQ_BUF_RSRC_WORD1_STRIDE_SHIFT 16 -#define SQ_BUF_RSRC_WORD1_STRIDE_SIZE 14 -#define SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_MASK 0x80000000 -#define SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_SHIFT 31 -#define SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_SIZE 1 -#define SQ_BUF_RSRC_WORD2_NUM_RECORDS_MASK 0xffffffff -#define SQ_BUF_RSRC_WORD2_NUM_RECORDS_SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD2_NUM_RECORDS_SIZE 32 -#define SQ_BUF_RSRC_WORD2_REG_SIZE 32 -#define SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_MASK 0x00800000 -#define SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_SHIFT 23 -#define SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_SIZE 1 -#define SQ_BUF_RSRC_WORD3_ATC_MASK__CI__VI 0x01000000 -#define SQ_BUF_RSRC_WORD3_ATC_SHIFT__CI__VI 24 -#define SQ_BUF_RSRC_WORD3_ATC_SIZE__CI__VI 1 -#define SQ_BUF_RSRC_WORD3_DATA_FORMAT_MASK 0x00078000 -#define SQ_BUF_RSRC_WORD3_DATA_FORMAT_SHIFT 15 -#define SQ_BUF_RSRC_WORD3_DATA_FORMAT_SIZE 4 -#define SQ_BUF_RSRC_WORD3_DST_SEL_W_MASK 0x00000e00 -#define SQ_BUF_RSRC_WORD3_DST_SEL_W_SHIFT 9 -#define SQ_BUF_RSRC_WORD3_DST_SEL_W_SIZE 3 -#define SQ_BUF_RSRC_WORD3_DST_SEL_X_MASK 0x00000007 -#define SQ_BUF_RSRC_WORD3_DST_SEL_X_SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD3_DST_SEL_X_SIZE 3 -#define SQ_BUF_RSRC_WORD3_DST_SEL_Y_MASK 0x00000038 -#define SQ_BUF_RSRC_WORD3_DST_SEL_Y_SHIFT 3 -#define SQ_BUF_RSRC_WORD3_DST_SEL_Y_SIZE 3 -#define SQ_BUF_RSRC_WORD3_DST_SEL_Z_MASK 0x000001c0 -#define SQ_BUF_RSRC_WORD3_DST_SEL_Z_SHIFT 6 -#define SQ_BUF_RSRC_WORD3_DST_SEL_Z_SIZE 3 -#define SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_MASK 0x00180000 -#define SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_SHIFT 19 -#define SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_SIZE 2 -#define SQ_BUF_RSRC_WORD3_HASH_ENABLE_MASK 0x02000000 -#define SQ_BUF_RSRC_WORD3_HASH_ENABLE_SHIFT 25 -#define SQ_BUF_RSRC_WORD3_HASH_ENABLE_SIZE 1 -#define SQ_BUF_RSRC_WORD3_HEAP_MASK 0x04000000 -#define SQ_BUF_RSRC_WORD3_HEAP_SHIFT 26 -#define SQ_BUF_RSRC_WORD3_HEAP_SIZE 1 -#define SQ_BUF_RSRC_WORD3_INDEX_STRIDE_MASK 0x00600000 -#define SQ_BUF_RSRC_WORD3_INDEX_STRIDE_SHIFT 21 -#define SQ_BUF_RSRC_WORD3_INDEX_STRIDE_SIZE 2 -#define SQ_BUF_RSRC_WORD3_MTYPE_MASK__CI__VI 0x38000000 -#define SQ_BUF_RSRC_WORD3_MTYPE_SHIFT__CI__VI 27 -#define SQ_BUF_RSRC_WORD3_MTYPE_SIZE__CI__VI 3 -#define SQ_BUF_RSRC_WORD3_NUM_FORMAT_MASK 0x00007000 -#define SQ_BUF_RSRC_WORD3_NUM_FORMAT_SHIFT 12 -#define SQ_BUF_RSRC_WORD3_NUM_FORMAT_SIZE 3 -#define SQ_BUF_RSRC_WORD3_REG_SIZE 32 -#define SQ_BUF_RSRC_WORD3_TYPE_MASK 0xc0000000 -#define SQ_BUF_RSRC_WORD3_TYPE_SHIFT 30 -#define SQ_BUF_RSRC_WORD3_TYPE_SIZE 2 -#define SQ_CAC_MASK_DEFAULT__SI 0x00000007 -#define SQ_CAC_MASK_GPR_MASK__SI 0x00000004 -#define SQ_CAC_MASK_GPR_SHIFT__SI 2 -#define SQ_CAC_MASK_GPR_SIZE__SI 1 -#define SQ_CAC_MASK_REG_SIZE__SI 32 -#define SQ_CAC_MASK_VALU_MASK__SI 0x00000001 -#define SQ_CAC_MASK_VALU_MUL_MASK__SI 0x00000002 -#define SQ_CAC_MASK_VALU_MUL_SHIFT__SI 1 -#define SQ_CAC_MASK_VALU_MUL_SIZE__SI 1 -#define SQ_CAC_MASK_VALU_SHIFT__SI 0x00000000 -#define SQ_CAC_MASK_VALU_SIZE__SI 1 -#define SQ_CMD_CHECK_VMID_MASK__CI__VI 0x00000080 -#define SQ_CMD_CHECK_VMID_SHIFT__CI__VI 7 -#define SQ_CMD_CHECK_VMID_SIZE__CI__VI 1 -#define SQ_CMD_CMD_MASK__CI__VI 0x00000007 -#define SQ_CMD_CMD_SHIFT__CI__VI 0x00000000 -#define SQ_CMD_CMD_SIZE__CI__VI 3 -#define SQ_CMD_DEFAULT__CI 0x00000000 -#define SQ_CMD_MODE_MASK__CI__VI 0x00000070 -#define SQ_CMD_MODE_SHIFT__CI__VI 4 -#define SQ_CMD_MODE_SIZE__CI__VI 3 -#define SQ_CMD_QUEUE_ID_MASK__CI__VI 0x07000000 -#define SQ_CMD_QUEUE_ID_SHIFT__CI__VI 24 -#define SQ_CMD_QUEUE_ID_SIZE__CI__VI 3 -#define SQ_CMD_REG_SIZE__CI__VI 32 -#define SQ_CMD_SIMD_ID_MASK__CI__VI 0x00300000 -#define SQ_CMD_SIMD_ID_SHIFT__CI__VI 20 -#define SQ_CMD_SIMD_ID_SIZE__CI__VI 2 -#define SQ_CMD_TIMESTAMP_DEFAULT__CI__VI 0x00000000 -#define SQ_CMD_TIMESTAMP_REG_SIZE__CI__VI 32 -#define SQ_CMD_TIMESTAMP_TIMESTAMP_MASK__CI__VI 0x000000ff -#define SQ_CMD_TIMESTAMP_TIMESTAMP_SHIFT__CI__VI 0x00000000 -#define SQ_CMD_TIMESTAMP_TIMESTAMP_SIZE__CI__VI 8 -#define SQ_CMD_TRAP_ID_MASK__CI 0x00000700 -#define SQ_CMD_TRAP_ID_SHIFT__CI 8 -#define SQ_CMD_TRAP_ID_SIZE__CI 3 -#define SQ_CMD_VM_ID_MASK__CI__VI 0xf0000000 -#define SQ_CMD_VM_ID_SHIFT__CI__VI 28 -#define SQ_CMD_VM_ID_SIZE__CI__VI 4 -#define SQ_CMD_WAVE_ID_MASK__CI__VI 0x000f0000 -#define SQ_CMD_WAVE_ID_SHIFT__CI__VI 16 -#define SQ_CMD_WAVE_ID_SIZE__CI__VI 4 -#define SQ_CONFIG_DEBUG_EN_MASK 0x00000100 -#define SQ_CONFIG_DEBUG_EN_SHIFT 8 -#define SQ_CONFIG_DEBUG_EN_SIZE 1 -#define SQ_CONFIG_DISABLE_IB_DEP_CHECK_MASK__SI__CI 0x00000400 -#define SQ_CONFIG_DISABLE_IB_DEP_CHECK_SHIFT__SI__CI 10 -#define SQ_CONFIG_DISABLE_IB_DEP_CHECK_SIZE__SI__CI 1 -#define SQ_CONFIG_DISABLE_SCA_BYPASS_MASK__SI__CI 0x00000200 -#define SQ_CONFIG_DISABLE_SCA_BYPASS_SHIFT__SI__CI 9 -#define SQ_CONFIG_DISABLE_SCA_BYPASS_SIZE__SI__CI 1 -#define SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_MASK__CI__VI 0x00008000 -#define SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_SHIFT__CI__VI 15 -#define SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_SIZE__CI__VI 1 -#define SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_MASK__CI__VI 0x00002000 -#define SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_SHIFT__CI__VI 13 -#define SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_SIZE__CI__VI 1 -#define SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_MASK__CI__VI 0x00004000 -#define SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_SHIFT__CI__VI 14 -#define SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_SIZE__CI__VI 1 -#define SQ_CONFIG_EARLY_TA_DONE_DISABLE_MASK__CI__VI 0x00001000 -#define SQ_CONFIG_EARLY_TA_DONE_DISABLE_SHIFT__CI__VI 12 -#define SQ_CONFIG_EARLY_TA_DONE_DISABLE_SIZE__CI__VI 1 -#define SQ_CONFIG_ENABLE_SOFT_CLAUSE_MASK__CI 0x00000800 -#define SQ_CONFIG_ENABLE_SOFT_CLAUSE_SHIFT__CI 11 -#define SQ_CONFIG_ENABLE_SOFT_CLAUSE_SIZE__CI 1 -#define SQ_CONFIG_REG_SIZE 32 -#define SQ_CONFIG_UNUSED_MASK 0x000000ff -#define SQ_CONFIG_UNUSED_SHIFT 0x00000000 -#define SQ_CONFIG_UNUSED_SIZE 8 -#define SQ_DEBUG_CTRL_LOCAL_REG_SIZE 32 -#define SQ_DEBUG_CTRL_LOCAL_UNUSED_MASK 0x000000ff -#define SQ_DEBUG_CTRL_LOCAL_UNUSED_SHIFT 0x00000000 -#define SQ_DEBUG_CTRL_LOCAL_UNUSED_SIZE 8 -#define SQ_DEBUG_STS_GLOBAL2_DEFAULT__CI__VI 0x00000000 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_MASK__CI__VI 0x000000ff -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_SHIFT__CI__VI 0x00000000 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_SIZE__CI__VI 8 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_MASK__CI__VI 0x0000ff00 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_SHIFT__CI__VI 8 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_SIZE__CI__VI 8 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_MASK__CI__VI 0xff000000 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_SHIFT__CI__VI 24 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_SIZE__CI__VI 8 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_MASK__CI__VI 0x00ff0000 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_SHIFT__CI__VI 16 -#define SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_SIZE__CI__VI 8 -#define SQ_DEBUG_STS_GLOBAL2_REG_SIZE__CI__VI 32 -#define SQ_DEBUG_STS_GLOBAL3_DEFAULT__CI__VI 0x00000000 -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_MASK__CI__VI 0x0000000f -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_SHIFT__CI__VI 0x00000000 -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_SIZE__CI__VI 4 -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_MASK__CI 0x000000f0 -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_SHIFT__CI__VI 4 -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_SIZE__CI 4 -#define SQ_DEBUG_STS_GLOBAL3_REG_SIZE__CI__VI 32 -#define SQ_DEBUG_STS_GLOBAL_BUSY_MASK 0x00000001 -#define SQ_DEBUG_STS_GLOBAL_BUSY_SHIFT 0x00000000 -#define SQ_DEBUG_STS_GLOBAL_BUSY_SIZE 1 -#define SQ_DEBUG_STS_GLOBAL_DEFAULT 0x00000000 -#define SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_MASK__CI__VI 0x00000002 -#define SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_SHIFT__CI__VI 1 -#define SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_SIZE__CI__VI 1 -#define SQ_DEBUG_STS_GLOBAL_REG_SIZE 32 -#define SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_MASK 0x0000fff0 -#define SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_SHIFT 4 -#define SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_SIZE 12 -#define SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_MASK 0x0fff0000 -#define SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_SHIFT 16 -#define SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_SIZE 12 -#define SQ_DEBUG_STS_LOCAL_BUSY_MASK 0x00000001 -#define SQ_DEBUG_STS_LOCAL_BUSY_SHIFT 0x00000000 -#define SQ_DEBUG_STS_LOCAL_BUSY_SIZE 1 -#define SQ_DEBUG_STS_LOCAL_DEFAULT 0x00000000 -#define SQ_DEBUG_STS_LOCAL_REG_SIZE 32 -#define SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_MASK 0x000003f0 -#define SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_SHIFT 4 -#define SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_SIZE 6 -#define SQ_DED_CNT_DEFAULT__SI__CI 0x00000000 -#define SQ_DED_CNT_LDS_DED_MASK__SI__CI 0x0000003f -#define SQ_DED_CNT_LDS_DED_SHIFT__SI__CI 0x00000000 -#define SQ_DED_CNT_LDS_DED_SIZE__SI__CI 6 -#define SQ_DED_CNT_REG_SIZE__SI__CI 32 -#define SQ_DED_CNT_SGPR_DED_MASK__SI__CI 0x00001f00 -#define SQ_DED_CNT_SGPR_DED_SHIFT__SI__CI 8 -#define SQ_DED_CNT_SGPR_DED_SIZE__SI__CI 5 -#define SQ_DED_CNT_VGPR_DED_MASK__SI__CI 0x01ff0000 -#define SQ_DED_CNT_VGPR_DED_SHIFT__SI__CI 16 -#define SQ_DED_CNT_VGPR_DED_SIZE__SI__CI 9 -#define SQ_DED_INFO_DEFAULT__SI__CI 0x00000000 -#define SQ_DED_INFO_REG_SIZE__SI__CI 32 -#define SQ_DED_INFO_RING_ID_MASK__SI 0x0000e000 -#define SQ_DED_INFO_RING_ID_SHIFT__SI 13 -#define SQ_DED_INFO_RING_ID_SIZE__SI 3 -#define SQ_DED_INFO_SIMD_ID_MASK__SI__CI 0x00000030 -#define SQ_DED_INFO_SIMD_ID_SHIFT__SI__CI 4 -#define SQ_DED_INFO_SIMD_ID_SIZE__SI__CI 2 -#define SQ_DED_INFO_SOURCE_MASK__SI__CI 0x000001c0 -#define SQ_DED_INFO_SOURCE_SHIFT__SI__CI 6 -#define SQ_DED_INFO_SOURCE_SIZE__SI__CI 3 -#define SQ_DED_INFO_VM_ID_MASK__SI__CI 0x00001e00 -#define SQ_DED_INFO_VM_ID_SHIFT__SI__CI 9 -#define SQ_DED_INFO_VM_ID_SIZE__SI__CI 4 -#define SQ_DED_INFO_WAVE_ID_MASK__SI__CI 0x0000000f -#define SQ_DED_INFO_WAVE_ID_SHIFT__SI__CI 0x00000000 -#define SQ_DED_INFO_WAVE_ID_SIZE__SI__CI 4 -#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 -#define SQ_DISPATCHER_GFX_MIN 0x00000010 -#define SQ_EX_MODE_EXCP_ADDR_WATCH__CI__VI 0x00000007 -#define SQ_EX_MODE_EXCP_DIV0__CI__VI 0x00000002 -#define SQ_EX_MODE_EXCP_INEXACT__CI__VI 0x00000005 -#define SQ_EX_MODE_EXCP_INPUT_DENORM__CI__VI 0x00000001 -#define SQ_EX_MODE_EXCP_INT_DIV0__CI__VI 0x00000006 -#define SQ_EX_MODE_EXCP_INVALID__CI__VI 0x00000000 -#define SQ_EX_MODE_EXCP_MEM_VIOL__CI__VI 0x00000008 -#define SQ_EX_MODE_EXCP_OVERFLOW__CI__VI 0x00000003 -#define SQ_EX_MODE_EXCP_UNDERFLOW__CI__VI 0x00000004 -#define SQ_EX_MODE_EXCP_VALU_BASE__CI__VI 0x00000000 -#define SQ_EX_MODE_EXCP_VALU_SIZE__CI__VI 0x00000007 -#define SQ_FIFO_SIZES_EXPORT_BUF_SIZE_MASK 0x00030000 -#define SQ_FIFO_SIZES_EXPORT_BUF_SIZE_SHIFT 16 -#define SQ_FIFO_SIZES_EXPORT_BUF_SIZE_SIZE 2 -#define SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_MASK 0x0000000f -#define SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_SHIFT 0x00000000 -#define SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_SIZE 4 -#define SQ_FIFO_SIZES_REG_SIZE 32 -#define SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_MASK 0x00000f00 -#define SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_SHIFT 8 -#define SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_SIZE 4 -#define SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_MASK 0x000c0000 -#define SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_SHIFT 18 -#define SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_SIZE 2 -#define SQ_FLAT_SCRATCH_WORD0_DEFAULT__CI 0x00000000 -#define SQ_FLAT_SCRATCH_WORD0_REG_SIZE__CI__VI 32 -#define SQ_FLAT_SCRATCH_WORD0_SIZE_MASK__CI__VI 0x0007ffff -#define SQ_FLAT_SCRATCH_WORD0_SIZE_SHIFT__CI__VI 0x00000000 -#define SQ_FLAT_SCRATCH_WORD0_SIZE_SIZE__CI__VI 19 -#define SQ_FLAT_SCRATCH_WORD1_DEFAULT__CI 0x00000000 -#define SQ_FLAT_SCRATCH_WORD1_OFFSET_MASK__CI__VI 0x00ffffff -#define SQ_FLAT_SCRATCH_WORD1_OFFSET_SHIFT__CI__VI 0x00000000 -#define SQ_FLAT_SCRATCH_WORD1_OFFSET_SIZE__CI__VI 24 -#define SQ_FLAT_SCRATCH_WORD1_REG_SIZE__CI__VI 32 -#define SQ_GFXDEC_BEGIN 0x0000a000 -#define SQ_GFXDEC_END 0x0000c000 -#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a -#define SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_MASK__CI__VI 0x000ffff0 -#define SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_SHIFT__CI__VI 4 -#define SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_SIZE__CI__VI 16 -#define SQ_HV_VMID_CTRL_DEFAULT_VMID_MASK__CI__VI 0x0000000f -#define SQ_HV_VMID_CTRL_DEFAULT_VMID_SHIFT__CI__VI 0x00000000 -#define SQ_HV_VMID_CTRL_DEFAULT_VMID_SIZE__CI__VI 4 -#define SQ_HV_VMID_CTRL_DEFAULT__CI__VI 0x000fffff -#define SQ_HV_VMID_CTRL_REG_SIZE__CI__VI 32 -#define SQ_IMG_RSRC_WORD0_BASE_ADDRESS_MASK 0xffffffff -#define SQ_IMG_RSRC_WORD0_BASE_ADDRESS_SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD0_BASE_ADDRESS_SIZE 32 -#define SQ_IMG_RSRC_WORD0_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_MASK 0x000000ff -#define SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_SIZE 8 -#define SQ_IMG_RSRC_WORD1_DATA_FORMAT_MASK 0x03f00000 -#define SQ_IMG_RSRC_WORD1_DATA_FORMAT_SHIFT 20 -#define SQ_IMG_RSRC_WORD1_DATA_FORMAT_SIZE 6 -#define SQ_IMG_RSRC_WORD1_MIN_LOD_MASK 0x000fff00 -#define SQ_IMG_RSRC_WORD1_MIN_LOD_SHIFT 8 -#define SQ_IMG_RSRC_WORD1_MIN_LOD_SIZE 12 -#define SQ_IMG_RSRC_WORD1_MTYPE_MASK__CI__VI 0xc0000000 -#define SQ_IMG_RSRC_WORD1_MTYPE_SHIFT__CI__VI 30 -#define SQ_IMG_RSRC_WORD1_MTYPE_SIZE__CI__VI 2 -#define SQ_IMG_RSRC_WORD1_NUM_FORMAT_MASK 0x3c000000 -#define SQ_IMG_RSRC_WORD1_NUM_FORMAT_SHIFT 26 -#define SQ_IMG_RSRC_WORD1_NUM_FORMAT_SIZE 4 -#define SQ_IMG_RSRC_WORD1_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD2_HEIGHT_MASK 0x0fffc000 -#define SQ_IMG_RSRC_WORD2_HEIGHT_SHIFT 14 -#define SQ_IMG_RSRC_WORD2_HEIGHT_SIZE 14 -#define SQ_IMG_RSRC_WORD2_INTERLACED_MASK 0x80000000 -#define SQ_IMG_RSRC_WORD2_INTERLACED_SHIFT 31 -#define SQ_IMG_RSRC_WORD2_INTERLACED_SIZE 1 -#define SQ_IMG_RSRC_WORD2_PERF_MOD_MASK 0x70000000 -#define SQ_IMG_RSRC_WORD2_PERF_MOD_SHIFT 28 -#define SQ_IMG_RSRC_WORD2_PERF_MOD_SIZE 3 -#define SQ_IMG_RSRC_WORD2_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD2_WIDTH_MASK 0x00003fff -#define SQ_IMG_RSRC_WORD2_WIDTH_SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD2_WIDTH_SIZE 14 -#define SQ_IMG_RSRC_WORD3_ATC_MASK__CI__VI 0x08000000 -#define SQ_IMG_RSRC_WORD3_ATC_SHIFT__CI__VI 27 -#define SQ_IMG_RSRC_WORD3_ATC_SIZE__CI__VI 1 -#define SQ_IMG_RSRC_WORD3_BASE_LEVEL_MASK 0x0000f000 -#define SQ_IMG_RSRC_WORD3_BASE_LEVEL_SHIFT 12 -#define SQ_IMG_RSRC_WORD3_BASE_LEVEL_SIZE 4 -#define SQ_IMG_RSRC_WORD3_DST_SEL_W_MASK 0x00000e00 -#define SQ_IMG_RSRC_WORD3_DST_SEL_W_SHIFT 9 -#define SQ_IMG_RSRC_WORD3_DST_SEL_W_SIZE 3 -#define SQ_IMG_RSRC_WORD3_DST_SEL_X_MASK 0x00000007 -#define SQ_IMG_RSRC_WORD3_DST_SEL_X_SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD3_DST_SEL_X_SIZE 3 -#define SQ_IMG_RSRC_WORD3_DST_SEL_Y_MASK 0x00000038 -#define SQ_IMG_RSRC_WORD3_DST_SEL_Y_SHIFT 3 -#define SQ_IMG_RSRC_WORD3_DST_SEL_Y_SIZE 3 -#define SQ_IMG_RSRC_WORD3_DST_SEL_Z_MASK 0x000001c0 -#define SQ_IMG_RSRC_WORD3_DST_SEL_Z_SHIFT 6 -#define SQ_IMG_RSRC_WORD3_DST_SEL_Z_SIZE 3 -#define SQ_IMG_RSRC_WORD3_LAST_LEVEL_MASK 0x000f0000 -#define SQ_IMG_RSRC_WORD3_LAST_LEVEL_SHIFT 16 -#define SQ_IMG_RSRC_WORD3_LAST_LEVEL_SIZE 4 -#define SQ_IMG_RSRC_WORD3_MTYPE_MASK__CI__VI 0x04000000 -#define SQ_IMG_RSRC_WORD3_MTYPE_SHIFT__CI__VI 26 -#define SQ_IMG_RSRC_WORD3_MTYPE_SIZE__CI__VI 1 -#define SQ_IMG_RSRC_WORD3_POW2_PAD_MASK 0x02000000 -#define SQ_IMG_RSRC_WORD3_POW2_PAD_SHIFT 25 -#define SQ_IMG_RSRC_WORD3_POW2_PAD_SIZE 1 -#define SQ_IMG_RSRC_WORD3_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD3_TILING_INDEX_MASK 0x01f00000 -#define SQ_IMG_RSRC_WORD3_TILING_INDEX_SHIFT 20 -#define SQ_IMG_RSRC_WORD3_TILING_INDEX_SIZE 5 -#define SQ_IMG_RSRC_WORD3_TYPE_MASK 0xf0000000 -#define SQ_IMG_RSRC_WORD3_TYPE_SHIFT 28 -#define SQ_IMG_RSRC_WORD3_TYPE_SIZE 4 -#define SQ_IMG_RSRC_WORD4_DEPTH_MASK 0x00001fff -#define SQ_IMG_RSRC_WORD4_DEPTH_SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD4_DEPTH_SIZE 13 -#define SQ_IMG_RSRC_WORD4_PITCH_MASK 0x07ffe000 -#define SQ_IMG_RSRC_WORD4_PITCH_SHIFT 13 -#define SQ_IMG_RSRC_WORD4_PITCH_SIZE 14 -#define SQ_IMG_RSRC_WORD4_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD5_BASE_ARRAY_MASK 0x00001fff -#define SQ_IMG_RSRC_WORD5_BASE_ARRAY_SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD5_BASE_ARRAY_SIZE 13 -#define SQ_IMG_RSRC_WORD5_LAST_ARRAY_MASK 0x03ffe000 -#define SQ_IMG_RSRC_WORD5_LAST_ARRAY_SHIFT 13 -#define SQ_IMG_RSRC_WORD5_LAST_ARRAY_SIZE 13 -#define SQ_IMG_RSRC_WORD5_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_MASK__CI__VI 0x000ff000 -#define SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_SHIFT__CI__VI 12 -#define SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_SIZE__CI__VI 8 -#define SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_MASK__CI__VI 0x00100000 -#define SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_SHIFT__CI__VI 20 -#define SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_SIZE__CI__VI 1 -#define SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_MASK 0x00000fff -#define SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_SIZE 12 -#define SQ_IMG_RSRC_WORD6_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD6_UNUNSED_MASK__CI 0xffe00000 -#define SQ_IMG_RSRC_WORD6_UNUNSED_SHIFT__CI 21 -#define SQ_IMG_RSRC_WORD6_UNUNSED_SIZE__CI 11 -#define SQ_IMG_RSRC_WORD7_REG_SIZE 32 -#define SQ_IMG_RSRC_WORD7_UNUNSED_MASK__SI__CI 0xffffffff -#define SQ_IMG_RSRC_WORD7_UNUNSED_SHIFT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD7_UNUNSED_SIZE__SI__CI 32 -#define SQ_IMG_SAMP_WORD0_ANISO_BIAS_MASK 0x07e00000 -#define SQ_IMG_SAMP_WORD0_ANISO_BIAS_SHIFT 21 -#define SQ_IMG_SAMP_WORD0_ANISO_BIAS_SIZE 6 -#define SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_MASK 0x00070000 -#define SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_SHIFT 16 -#define SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_SIZE 3 -#define SQ_IMG_SAMP_WORD0_CLAMP_X_MASK 0x00000007 -#define SQ_IMG_SAMP_WORD0_CLAMP_X_SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD0_CLAMP_X_SIZE 3 -#define SQ_IMG_SAMP_WORD0_CLAMP_Y_MASK 0x00000038 -#define SQ_IMG_SAMP_WORD0_CLAMP_Y_SHIFT 3 -#define SQ_IMG_SAMP_WORD0_CLAMP_Y_SIZE 3 -#define SQ_IMG_SAMP_WORD0_CLAMP_Z_MASK 0x000001c0 -#define SQ_IMG_SAMP_WORD0_CLAMP_Z_SHIFT 6 -#define SQ_IMG_SAMP_WORD0_CLAMP_Z_SIZE 3 -#define SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_MASK 0x00007000 -#define SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_SHIFT 12 -#define SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_SIZE 3 -#define SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_MASK 0x10000000 -#define SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_SHIFT 28 -#define SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_SIZE 1 -#define SQ_IMG_SAMP_WORD0_FILTER_MODE_MASK 0x60000000 -#define SQ_IMG_SAMP_WORD0_FILTER_MODE_SHIFT 29 -#define SQ_IMG_SAMP_WORD0_FILTER_MODE_SIZE 2 -#define SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_MASK 0x00100000 -#define SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_SHIFT 20 -#define SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_SIZE 1 -#define SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_MASK 0x00008000 -#define SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_SHIFT 15 -#define SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_SIZE 1 -#define SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_MASK 0x00000e00 -#define SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_SHIFT 9 -#define SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_SIZE 3 -#define SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_MASK 0x00080000 -#define SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_SHIFT 19 -#define SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_SIZE 1 -#define SQ_IMG_SAMP_WORD0_REG_SIZE 32 -#define SQ_IMG_SAMP_WORD0_TRUNC_COORD_MASK 0x08000000 -#define SQ_IMG_SAMP_WORD0_TRUNC_COORD_SHIFT 27 -#define SQ_IMG_SAMP_WORD0_TRUNC_COORD_SIZE 1 -#define SQ_IMG_SAMP_WORD1_MAX_LOD_MASK 0x00fff000 -#define SQ_IMG_SAMP_WORD1_MAX_LOD_SHIFT 12 -#define SQ_IMG_SAMP_WORD1_MAX_LOD_SIZE 12 -#define SQ_IMG_SAMP_WORD1_MIN_LOD_MASK 0x00000fff -#define SQ_IMG_SAMP_WORD1_MIN_LOD_SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD1_MIN_LOD_SIZE 12 -#define SQ_IMG_SAMP_WORD1_PERF_MIP_MASK 0x0f000000 -#define SQ_IMG_SAMP_WORD1_PERF_MIP_SHIFT 24 -#define SQ_IMG_SAMP_WORD1_PERF_MIP_SIZE 4 -#define SQ_IMG_SAMP_WORD1_PERF_Z_MASK 0xf0000000 -#define SQ_IMG_SAMP_WORD1_PERF_Z_SHIFT 28 -#define SQ_IMG_SAMP_WORD1_PERF_Z_SIZE 4 -#define SQ_IMG_SAMP_WORD1_REG_SIZE 32 -#define SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_MASK 0x20000000 -#define SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_SHIFT 29 -#define SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_SIZE 1 -#define SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_MASK 0x40000000 -#define SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_SHIFT 30 -#define SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_SIZE 1 -#define SQ_IMG_SAMP_WORD2_LOD_BIAS_MASK 0x00003fff -#define SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_MASK 0x000fc000 -#define SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_SHIFT 14 -#define SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_SIZE 6 -#define SQ_IMG_SAMP_WORD2_LOD_BIAS_SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD2_LOD_BIAS_SIZE 14 -#define SQ_IMG_SAMP_WORD2_MIP_FILTER_MASK 0x0c000000 -#define SQ_IMG_SAMP_WORD2_MIP_FILTER_SHIFT 26 -#define SQ_IMG_SAMP_WORD2_MIP_FILTER_SIZE 2 -#define SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_MASK 0x10000000 -#define SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_SHIFT 28 -#define SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_SIZE 1 -#define SQ_IMG_SAMP_WORD2_REG_SIZE 32 -#define SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_MASK 0x00300000 -#define SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_SHIFT 20 -#define SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_SIZE 2 -#define SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_MASK 0x00c00000 -#define SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_SHIFT 22 -#define SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_SIZE 2 -#define SQ_IMG_SAMP_WORD2_Z_FILTER_MASK 0x03000000 -#define SQ_IMG_SAMP_WORD2_Z_FILTER_SHIFT 24 -#define SQ_IMG_SAMP_WORD2_Z_FILTER_SIZE 2 -#define SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_MASK 0x00000fff -#define SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_SIZE 12 -#define SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_MASK 0xc0000000 -#define SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_SHIFT 30 -#define SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_SIZE 2 -#define SQ_IMG_SAMP_WORD3_REG_SIZE 32 -#define SQ_IND_CMD_CMD_MASK__SI 0x00000007 -#define SQ_IND_CMD_CMD_SHIFT__SI 0x00000000 -#define SQ_IND_CMD_CMD_SIZE__SI 3 -#define SQ_IND_CMD_DEFAULT__SI__CI 0x00000000 -#define SQ_IND_CMD_MODE_MASK__SI 0x00000030 -#define SQ_IND_CMD_MODE_SHIFT__SI 4 -#define SQ_IND_CMD_MODE_SIZE__SI 2 -#define SQ_IND_CMD_REG_SIZE__SI__CI 32 -#define SQ_IND_CMD_TRAP_ID_MASK__SI 0x00000700 -#define SQ_IND_CMD_TRAP_ID_SHIFT__SI 8 -#define SQ_IND_CMD_TRAP_ID_SIZE__SI 3 -#define SQ_IND_CMD_VM_ID_MASK__SI 0xf0000000 -#define SQ_IND_CMD_VM_ID_SHIFT__SI 28 -#define SQ_IND_CMD_VM_ID_SIZE__SI 4 -#define SQ_IND_DATA_DATA_MASK 0xffffffff -#define SQ_IND_DATA_DATA_SHIFT 0x00000000 -#define SQ_IND_DATA_DATA_SIZE 32 -#define SQ_IND_DATA_REG_SIZE 32 -#define SQ_IND_INDEX_AUTO_INCR_MASK__CI__VI 0x00001000 -#define SQ_IND_INDEX_AUTO_INCR_SHIFT__CI__VI 12 -#define SQ_IND_INDEX_AUTO_INCR_SIZE__CI__VI 1 -#define SQ_IND_INDEX_DEFAULT 0x00000000 -#define SQ_IND_INDEX_FORCE_READ_MASK__CI__VI 0x00002000 -#define SQ_IND_INDEX_FORCE_READ_SHIFT__CI__VI 13 -#define SQ_IND_INDEX_FORCE_READ_SIZE__CI__VI 1 -#define SQ_IND_INDEX_INDEX_MASK 0xffff0000 -#define SQ_IND_INDEX_INDEX_SHIFT 16 -#define SQ_IND_INDEX_INDEX_SIZE 16 -#define SQ_IND_INDEX_READ_TIMEOUT_MASK 0x00004000 -#define SQ_IND_INDEX_READ_TIMEOUT_SHIFT 14 -#define SQ_IND_INDEX_READ_TIMEOUT_SIZE 1 -#define SQ_IND_INDEX_REG_SIZE 32 -#define SQ_IND_INDEX_SIMD_ID_MASK 0x00000030 -#define SQ_IND_INDEX_SIMD_ID_SHIFT 4 -#define SQ_IND_INDEX_SIMD_ID_SIZE 2 -#define SQ_IND_INDEX_THREAD_ID_MASK 0x00000fc0 -#define SQ_IND_INDEX_THREAD_ID_SHIFT 6 -#define SQ_IND_INDEX_THREAD_ID_SIZE 6 -#define SQ_IND_INDEX_UNINDEXED_MASK 0x00008000 -#define SQ_IND_INDEX_UNINDEXED_SHIFT 15 -#define SQ_IND_INDEX_UNINDEXED_SIZE 1 -#define SQ_IND_INDEX_WAVE_ID_MASK 0x0000000f -#define SQ_IND_INDEX_WAVE_ID_SHIFT 0x00000000 -#define SQ_IND_INDEX_WAVE_ID_SIZE 4 -#define SQ_INTERRUPT_AUTO_MASK_DEFAULT__CI__VI 0x00ffffff -#define SQ_INTERRUPT_AUTO_MASK_MASK_MASK__CI__VI 0x00ffffff -#define SQ_INTERRUPT_AUTO_MASK_MASK_SHIFT__CI__VI 0x00000000 -#define SQ_INTERRUPT_AUTO_MASK_MASK_SIZE__CI__VI 24 -#define SQ_INTERRUPT_AUTO_MASK_REG_SIZE__CI__VI 32 -#define SQ_INTERRUPT_ID__SI__CI 0x000000ef -#define SQ_INTERRUPT_MSG_CTRL_DEFAULT__CI__VI 0x00000000 -#define SQ_INTERRUPT_MSG_CTRL_REG_SIZE__CI__VI 32 -#define SQ_INTERRUPT_MSG_CTRL_STALL_MASK__CI__VI 0x00000001 -#define SQ_INTERRUPT_MSG_CTRL_STALL_SHIFT__CI__VI 0x00000000 -#define SQ_INTERRUPT_MSG_CTRL_STALL_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_MASK__CI__VI 0x00000010 -#define SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_SHIFT__CI__VI 4 -#define SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_ENCODING_MASK 0x0c000000 -#define SQ_INTERRUPT_WORD_AUTO_ENCODING_SHIFT 26 -#define SQ_INTERRUPT_WORD_AUTO_ENCODING_SIZE 2 -#define SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_MASK__CI__VI 0x00000020 -#define SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_SHIFT__CI__VI 5 -#define SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_MASK__CI__VI 0x00000040 -#define SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_SHIFT__CI__VI 6 -#define SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_MASK__CI__VI 0x00000080 -#define SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_SHIFT__CI__VI 7 -#define SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_REG_SIZE 28 -#define SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_MASK__CI__VI 0x00000008 -#define SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_SHIFT__CI__VI 3 -#define SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_SE_ID_MASK__CI__VI 0x03000000 -#define SQ_INTERRUPT_WORD_AUTO_SE_ID_MASK__SI 0x02000000 -#define SQ_INTERRUPT_WORD_AUTO_SE_ID_SHIFT__CI__VI 24 -#define SQ_INTERRUPT_WORD_AUTO_SE_ID_SHIFT__SI 25 -#define SQ_INTERRUPT_WORD_AUTO_SE_ID_SIZE__CI__VI 2 -#define SQ_INTERRUPT_WORD_AUTO_SE_ID_SIZE__SI 1 -#define SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_MASK__CI__VI 0x00000004 -#define SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_SHIFT__CI__VI 2 -#define SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_MASK 0x00000001 -#define SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_SIZE 1 -#define SQ_INTERRUPT_WORD_AUTO_WLT_MASK__CI__VI 0x00000002 -#define SQ_INTERRUPT_WORD_AUTO_WLT_SHIFT__CI__VI 1 -#define SQ_INTERRUPT_WORD_AUTO_WLT_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_CMN_ENCODING_MASK 0x0c000000 -#define SQ_INTERRUPT_WORD_CMN_ENCODING_SHIFT 26 -#define SQ_INTERRUPT_WORD_CMN_ENCODING_SIZE 2 -#define SQ_INTERRUPT_WORD_CMN_REG_SIZE 28 -#define SQ_INTERRUPT_WORD_CMN_SE_ID_MASK__CI__VI 0x03000000 -#define SQ_INTERRUPT_WORD_CMN_SE_ID_MASK__SI 0x02000000 -#define SQ_INTERRUPT_WORD_CMN_SE_ID_SHIFT__CI__VI 24 -#define SQ_INTERRUPT_WORD_CMN_SE_ID_SHIFT__SI 25 -#define SQ_INTERRUPT_WORD_CMN_SE_ID_SIZE__CI__VI 2 -#define SQ_INTERRUPT_WORD_CMN_SE_ID_SIZE__SI 1 -#define SQ_INTERRUPT_WORD_WAVE_CU_ID_MASK 0x00f00000 -#define SQ_INTERRUPT_WORD_WAVE_CU_ID_SHIFT 20 -#define SQ_INTERRUPT_WORD_WAVE_CU_ID_SIZE 4 -#define SQ_INTERRUPT_WORD_WAVE_DATA_MASK 0x000000ff -#define SQ_INTERRUPT_WORD_WAVE_DATA_SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_WAVE_DATA_SIZE 8 -#define SQ_INTERRUPT_WORD_WAVE_ENCODING_MASK 0x0c000000 -#define SQ_INTERRUPT_WORD_WAVE_ENCODING_SHIFT 26 -#define SQ_INTERRUPT_WORD_WAVE_ENCODING_SIZE 2 -#define SQ_INTERRUPT_WORD_WAVE_PRIV_MASK__CI__VI 0x00000200 -#define SQ_INTERRUPT_WORD_WAVE_PRIV_SHIFT__CI__VI 9 -#define SQ_INTERRUPT_WORD_WAVE_PRIV_SIZE__CI__VI 1 -#define SQ_INTERRUPT_WORD_WAVE_REG_SIZE 28 -#define SQ_INTERRUPT_WORD_WAVE_SE_ID_MASK__CI__VI 0x03000000 -#define SQ_INTERRUPT_WORD_WAVE_SE_ID_MASK__SI 0x02000000 -#define SQ_INTERRUPT_WORD_WAVE_SE_ID_SHIFT__CI__VI 24 -#define SQ_INTERRUPT_WORD_WAVE_SE_ID_SHIFT__SI 25 -#define SQ_INTERRUPT_WORD_WAVE_SE_ID_SIZE__CI__VI 2 -#define SQ_INTERRUPT_WORD_WAVE_SE_ID_SIZE__SI 1 -#define SQ_INTERRUPT_WORD_WAVE_SH_ID_MASK__CI__VI 0x00000100 -#define SQ_INTERRUPT_WORD_WAVE_SH_ID_MASK__SI 0x01000000 -#define SQ_INTERRUPT_WORD_WAVE_SH_ID_SHIFT__CI__VI 8 -#define SQ_INTERRUPT_WORD_WAVE_SH_ID_SHIFT__SI 24 -#define SQ_INTERRUPT_WORD_WAVE_SH_ID_SIZE 1 -#define SQ_INTERRUPT_WORD_WAVE_SIMD_ID_MASK 0x000c0000 -#define SQ_INTERRUPT_WORD_WAVE_SIMD_ID_SHIFT 18 -#define SQ_INTERRUPT_WORD_WAVE_SIMD_ID_SIZE 2 -#define SQ_INTERRUPT_WORD_WAVE_VM_ID_MASK 0x00003c00 -#define SQ_INTERRUPT_WORD_WAVE_VM_ID_SHIFT 10 -#define SQ_INTERRUPT_WORD_WAVE_VM_ID_SIZE 4 -#define SQ_INTERRUPT_WORD_WAVE_WAVE_ID_MASK 0x0003c000 -#define SQ_INTERRUPT_WORD_WAVE_WAVE_ID_SHIFT 14 -#define SQ_INTERRUPT_WORD_WAVE_WAVE_ID_SIZE 4 -#define SQ_LB_CTR_CTRL_CLEAR_MASK 0x00000004 -#define SQ_LB_CTR_CTRL_CLEAR_SHIFT 2 -#define SQ_LB_CTR_CTRL_CLEAR_SIZE 1 -#define SQ_LB_CTR_CTRL_DEFAULT 0x00000000 -#define SQ_LB_CTR_CTRL_LOAD_MASK 0x00000002 -#define SQ_LB_CTR_CTRL_LOAD_SHIFT 1 -#define SQ_LB_CTR_CTRL_LOAD_SIZE 1 -#define SQ_LB_CTR_CTRL_REG_SIZE 32 -#define SQ_LB_CTR_CTRL_START_MASK 0x00000001 -#define SQ_LB_CTR_CTRL_START_SHIFT 0x00000000 -#define SQ_LB_CTR_CTRL_START_SIZE 1 -#define SQ_LB_DATA_ALU_CYCLES_DATA_MASK 0xffffffff -#define SQ_LB_DATA_ALU_CYCLES_DATA_SHIFT 0x00000000 -#define SQ_LB_DATA_ALU_CYCLES_DATA_SIZE 32 -#define SQ_LB_DATA_ALU_CYCLES_DEFAULT 0x00000000 -#define SQ_LB_DATA_ALU_CYCLES_REG_SIZE 32 -#define SQ_LB_DATA_ALU_STALLS_DATA_MASK 0xffffffff -#define SQ_LB_DATA_ALU_STALLS_DATA_SHIFT 0x00000000 -#define SQ_LB_DATA_ALU_STALLS_DATA_SIZE 32 -#define SQ_LB_DATA_ALU_STALLS_DEFAULT 0x00000000 -#define SQ_LB_DATA_ALU_STALLS_REG_SIZE 32 -#define SQ_LB_DATA_TEX_CYCLES_DATA_MASK 0xffffffff -#define SQ_LB_DATA_TEX_CYCLES_DATA_SHIFT 0x00000000 -#define SQ_LB_DATA_TEX_CYCLES_DATA_SIZE 32 -#define SQ_LB_DATA_TEX_CYCLES_DEFAULT 0x00000000 -#define SQ_LB_DATA_TEX_CYCLES_REG_SIZE 32 -#define SQ_LB_DATA_TEX_STALLS_DATA_MASK 0xffffffff -#define SQ_LB_DATA_TEX_STALLS_DATA_SHIFT 0x00000000 -#define SQ_LB_DATA_TEX_STALLS_DATA_SIZE 32 -#define SQ_LB_DATA_TEX_STALLS_DEFAULT 0x00000000 -#define SQ_LB_DATA_TEX_STALLS_REG_SIZE 32 -#define SQ_LDS_CLK_CTRL_DEFAULT__CI__VI 0x00000000 -#define SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_MASK__CI__VI 0x0000ffff -#define SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT__CI__VI 0x00000000 -#define SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_SIZE__CI__VI 16 -#define SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_MASK__CI__VI 0xffff0000 -#define SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT__CI__VI 16 -#define SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_SIZE__CI__VI 16 -#define SQ_LDS_CLK_CTRL_REG_SIZE__CI__VI 32 -#define SQ_MAX_PGM_SGPRS 0x00000068 -#define SQ_MAX_PGM_VGPRS 0x00000100 -#define SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER0_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER0_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER0_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER0_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER0_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER0_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER0_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER0_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER0_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER0_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER0_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER0_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER0_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER0_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER10_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER10_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER10_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER10_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER10_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER10_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER10_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER10_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER10_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER10_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER10_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER10_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER10_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER10_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER10_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER10_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER10_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER10_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER10_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER11_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER11_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER11_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER11_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER11_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER11_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER11_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER11_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER11_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER11_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER11_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER11_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER11_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER11_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER11_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER11_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER11_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER11_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER11_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER12_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER12_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER12_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER12_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER12_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER12_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER12_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER12_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER12_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER12_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER12_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER12_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER12_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER12_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER12_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER12_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER12_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER12_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER12_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER13_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER13_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER13_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER13_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER13_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER13_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER13_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER13_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER13_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER13_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER13_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER13_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER13_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER13_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER13_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER13_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER13_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER13_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER13_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER14_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER14_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER14_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER14_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER14_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER14_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER14_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER14_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER14_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER14_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER14_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER14_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER14_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER14_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER14_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER14_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER14_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER14_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER14_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER15_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER15_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER15_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER15_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER15_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER15_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER15_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER15_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER15_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER15_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER15_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER15_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER15_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER15_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER15_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER15_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER15_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER15_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER15_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER1_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER1_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER1_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER1_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER1_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER1_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER1_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER1_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER1_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER1_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER1_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER1_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER1_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER1_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER2_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER2_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER2_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER2_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER2_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER2_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER2_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER2_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER2_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER2_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER2_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER2_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER2_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER2_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER3_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER3_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER3_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER3_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER3_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER3_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER3_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER3_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER3_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER3_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER3_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER3_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER3_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER3_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER4_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER4_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER4_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER4_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER4_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER4_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER4_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER4_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER4_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER4_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER4_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER4_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER4_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER4_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER4_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER4_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER4_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER4_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER4_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER5_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER5_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER5_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER5_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER5_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER5_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER5_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER5_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER5_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER5_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER5_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER5_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER5_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER5_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER5_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER5_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER5_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER5_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER5_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER6_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER6_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER6_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER6_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER6_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER6_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER6_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER6_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER6_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER6_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER6_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER6_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER6_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER6_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER6_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER6_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER6_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER6_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER6_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER7_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER7_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER7_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER7_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER7_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER7_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER7_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER7_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER7_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER7_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER7_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER7_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER7_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER7_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER7_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER7_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER7_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER7_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER7_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER8_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER8_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER8_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER8_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER8_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER8_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER8_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER8_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER8_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER8_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER8_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER8_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER8_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER8_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER8_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER8_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER8_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER8_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER8_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0xffffffff -#define SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0x00000000 -#define SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 32 -#define SQ_PERFCOUNTER9_HI_REG_SIZE 32 -#define SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_MASK 0xffffffff -#define SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_SHIFT 0x00000000 -#define SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_SIZE 32 -#define SQ_PERFCOUNTER9_LO_REG_SIZE 32 -#define SQ_PERFCOUNTER9_SELECT_DEFAULT__CI__VI 0x0f0ff000 -#define SQ_PERFCOUNTER9_SELECT_DEFAULT__SI 0x0f000000 -#define SQ_PERFCOUNTER9_SELECT_PERF_MODE_MASK 0xf0000000 -#define SQ_PERFCOUNTER9_SELECT_PERF_MODE_SHIFT 28 -#define SQ_PERFCOUNTER9_SELECT_PERF_MODE_SIZE 4 -#define SQ_PERFCOUNTER9_SELECT_PERF_SEL_MASK__CI 0x000000ff -#define SQ_PERFCOUNTER9_SELECT_PERF_SEL_MASK__SI__VI 0x000001ff -#define SQ_PERFCOUNTER9_SELECT_PERF_SEL_SHIFT 0x00000000 -#define SQ_PERFCOUNTER9_SELECT_PERF_SEL_SIZE__CI 8 -#define SQ_PERFCOUNTER9_SELECT_PERF_SEL_SIZE__SI__VI 9 -#define SQ_PERFCOUNTER9_SELECT_REG_SIZE 32 -#define SQ_PERFCOUNTER9_SELECT_SIMD_MASK_MASK 0x0f000000 -#define SQ_PERFCOUNTER9_SELECT_SIMD_MASK_SHIFT 24 -#define SQ_PERFCOUNTER9_SELECT_SIMD_MASK_SIZE 4 -#define SQ_PERFCOUNTER9_SELECT_SPM_MODE_MASK__CI__VI 0x00f00000 -#define SQ_PERFCOUNTER9_SELECT_SPM_MODE_SHIFT__CI__VI 20 -#define SQ_PERFCOUNTER9_SELECT_SPM_MODE_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_MASK__CI__VI 0x0000f000 -#define SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_SHIFT__CI__VI 12 -#define SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_MASK__CI__VI 0x000f0000 -#define SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_SIZE__CI__VI 4 -#define SQ_PERFCOUNTER_CTRL2_DEFAULT__CI__VI 0x00000000 -#define SQ_PERFCOUNTER_CTRL2_FORCE_EN_MASK__CI__VI 0x00000001 -#define SQ_PERFCOUNTER_CTRL2_FORCE_EN_SHIFT__CI__VI 0x00000000 -#define SQ_PERFCOUNTER_CTRL2_FORCE_EN_SIZE__CI__VI 1 -#define SQ_PERFCOUNTER_CTRL2_REG_SIZE__CI__VI 32 -#define SQ_PERFCOUNTER_CTRL_CNTR_RATE_MASK 0x00001f00 -#define SQ_PERFCOUNTER_CTRL_CNTR_RATE_SHIFT 8 -#define SQ_PERFCOUNTER_CTRL_CNTR_RATE_SIZE 5 -#define SQ_PERFCOUNTER_CTRL_CS_EN_MASK 0x00000040 -#define SQ_PERFCOUNTER_CTRL_CS_EN_SHIFT 6 -#define SQ_PERFCOUNTER_CTRL_CS_EN_SIZE 1 -#define SQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000 -#define SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_MASK 0x00002000 -#define SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_SHIFT 13 -#define SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_SIZE 1 -#define SQ_PERFCOUNTER_CTRL_ES_EN_MASK 0x00000008 -#define SQ_PERFCOUNTER_CTRL_ES_EN_SHIFT 3 -#define SQ_PERFCOUNTER_CTRL_ES_EN_SIZE 1 -#define SQ_PERFCOUNTER_CTRL_GS_EN_MASK 0x00000004 -#define SQ_PERFCOUNTER_CTRL_GS_EN_SHIFT 2 -#define SQ_PERFCOUNTER_CTRL_GS_EN_SIZE 1 -#define SQ_PERFCOUNTER_CTRL_HS_EN_MASK 0x00000010 -#define SQ_PERFCOUNTER_CTRL_HS_EN_SHIFT 4 -#define SQ_PERFCOUNTER_CTRL_HS_EN_SIZE 1 -#define SQ_PERFCOUNTER_CTRL_LS_EN_MASK 0x00000020 -#define SQ_PERFCOUNTER_CTRL_LS_EN_SHIFT 5 -#define SQ_PERFCOUNTER_CTRL_LS_EN_SIZE 1 -#define SQ_PERFCOUNTER_CTRL_PS_EN_MASK 0x00000001 -#define SQ_PERFCOUNTER_CTRL_PS_EN_SHIFT 0x00000000 -#define SQ_PERFCOUNTER_CTRL_PS_EN_SIZE 1 -#define SQ_PERFCOUNTER_CTRL_REG_SIZE 32 -#define SQ_PERFCOUNTER_CTRL_VS_EN_MASK 0x00000002 -#define SQ_PERFCOUNTER_CTRL_VS_EN_SHIFT 1 -#define SQ_PERFCOUNTER_CTRL_VS_EN_SIZE 1 -#define SQ_PERFCOUNTER_MASK_DEFAULT__CI__VI 0xffffffff -#define SQ_PERFCOUNTER_MASK_REG_SIZE__CI__VI 32 -#define SQ_PERFCOUNTER_MASK_SH0_MASK_MASK__CI__VI 0x0000ffff -#define SQ_PERFCOUNTER_MASK_SH0_MASK_SHIFT__CI__VI 0x00000000 -#define SQ_PERFCOUNTER_MASK_SH0_MASK_SIZE__CI__VI 16 -#define SQ_PERFCOUNTER_MASK_SH1_MASK_MASK__CI__VI 0xffff0000 -#define SQ_PERFCOUNTER_MASK_SH1_MASK_SHIFT__CI__VI 16 -#define SQ_PERFCOUNTER_MASK_SH1_MASK_SIZE__CI__VI 16 -#define SQ_POWER_THROTTLE2_DEFAULT 0x18800004 -#define SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 -#define SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_SHIFT 27 -#define SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_SIZE 4 -#define SQ_POWER_THROTTLE2_MAX_POWER_DELTA_MASK 0x00003fff -#define SQ_POWER_THROTTLE2_MAX_POWER_DELTA_SHIFT 0x00000000 -#define SQ_POWER_THROTTLE2_MAX_POWER_DELTA_SIZE 14 -#define SQ_POWER_THROTTLE2_REG_SIZE 32 -#define SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000 -#define SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_SHIFT 16 -#define SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_SIZE 10 -#define SQ_POWER_THROTTLE2_USE_REF_CLOCK_MASK 0x80000000 -#define SQ_POWER_THROTTLE2_USE_REF_CLOCK_SHIFT 31 -#define SQ_POWER_THROTTLE2_USE_REF_CLOCK_SIZE 1 -#define SQ_POWER_THROTTLE_DEFAULT 0x3fff3fff -#define SQ_POWER_THROTTLE_MAX_POWER_MASK 0x3fff0000 -#define SQ_POWER_THROTTLE_MAX_POWER_SHIFT 16 -#define SQ_POWER_THROTTLE_MAX_POWER_SIZE 14 -#define SQ_POWER_THROTTLE_MIN_POWER_MASK 0x00003fff -#define SQ_POWER_THROTTLE_MIN_POWER_SHIFT 0x00000000 -#define SQ_POWER_THROTTLE_MIN_POWER_SIZE 14 -#define SQ_POWER_THROTTLE_PHASE_OFFSET_MASK 0xc0000000 -#define SQ_POWER_THROTTLE_PHASE_OFFSET_SHIFT 30 -#define SQ_POWER_THROTTLE_PHASE_OFFSET_SIZE 2 -#define SQ_POWER_THROTTLE_REG_SIZE 32 -#define SQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f -#define SQ_RANDOM_WAVE_PRI_REG_SIZE 32 -#define SQ_RANDOM_WAVE_PRI_RET_MASK 0x0000007f -#define SQ_RANDOM_WAVE_PRI_RET_SHIFT 0x00000000 -#define SQ_RANDOM_WAVE_PRI_RET_SIZE 7 -#define SQ_RANDOM_WAVE_PRI_RNG_MASK 0x001ffc00 -#define SQ_RANDOM_WAVE_PRI_RNG_SHIFT 10 -#define SQ_RANDOM_WAVE_PRI_RNG_SIZE 11 -#define SQ_RANDOM_WAVE_PRI_RUI_MASK 0x00000380 -#define SQ_RANDOM_WAVE_PRI_RUI_SHIFT 7 -#define SQ_RANDOM_WAVE_PRI_RUI_SIZE 3 -#define SQ_REG_CREDITS_CMD_CREDITS_MASK 0x00000f00 -#define SQ_REG_CREDITS_CMD_CREDITS_SHIFT 8 -#define SQ_REG_CREDITS_CMD_CREDITS_SIZE 4 -#define SQ_REG_CREDITS_CMD_OVERFLOW_MASK__CI__VI 0x80000000 -#define SQ_REG_CREDITS_CMD_OVERFLOW_SHIFT__CI__VI 31 -#define SQ_REG_CREDITS_CMD_OVERFLOW_SIZE__CI__VI 1 -#define SQ_REG_CREDITS_DEFAULT__CI__VI 0x00000820 -#define SQ_REG_CREDITS_DEFAULT__SI 0x00000832 -#define SQ_REG_CREDITS_IMMED_OVERFLOW_MASK__CI__VI 0x40000000 -#define SQ_REG_CREDITS_IMMED_OVERFLOW_SHIFT__CI__VI 30 -#define SQ_REG_CREDITS_IMMED_OVERFLOW_SIZE__CI__VI 1 -#define SQ_REG_CREDITS_REG_BUSY_MASK__CI__VI 0x10000000 -#define SQ_REG_CREDITS_REG_BUSY_SHIFT__CI__VI 28 -#define SQ_REG_CREDITS_REG_BUSY_SIZE__CI__VI 1 -#define SQ_REG_CREDITS_REG_SIZE 32 -#define SQ_REG_CREDITS_SRBM_CREDITS_MASK 0x0000003f -#define SQ_REG_CREDITS_SRBM_CREDITS_SHIFT 0x00000000 -#define SQ_REG_CREDITS_SRBM_CREDITS_SIZE 6 -#define SQ_REG_CREDITS_SRBM_OVERFLOW_MASK__CI__VI 0x20000000 -#define SQ_REG_CREDITS_SRBM_OVERFLOW_SHIFT__CI__VI 29 -#define SQ_REG_CREDITS_SRBM_OVERFLOW_SIZE__CI__VI 1 -#define SQ_REG_TIMESTAMP_DEFAULT__CI__VI 0x00000000 -#define SQ_REG_TIMESTAMP_REG_SIZE__CI__VI 32 -#define SQ_REG_TIMESTAMP_TIMESTAMP_MASK__CI__VI 0x000000ff -#define SQ_REG_TIMESTAMP_TIMESTAMP_SHIFT__CI__VI 0x00000000 -#define SQ_REG_TIMESTAMP_TIMESTAMP_SIZE__CI__VI 8 -#define SQ_SEC_CNT_DEFAULT__SI__CI 0x00000000 -#define SQ_SEC_CNT_LDS_SEC_MASK__SI__CI 0x0000003f -#define SQ_SEC_CNT_LDS_SEC_SHIFT__SI__CI 0x00000000 -#define SQ_SEC_CNT_LDS_SEC_SIZE__SI__CI 6 -#define SQ_SEC_CNT_REG_SIZE__SI__CI 32 -#define SQ_SEC_CNT_SGPR_SEC_MASK__SI__CI 0x00001f00 -#define SQ_SEC_CNT_SGPR_SEC_SHIFT__SI__CI 8 -#define SQ_SEC_CNT_SGPR_SEC_SIZE__SI__CI 5 -#define SQ_SEC_CNT_VGPR_SEC_MASK__SI__CI 0x01ff0000 -#define SQ_SEC_CNT_VGPR_SEC_SHIFT__SI__CI 16 -#define SQ_SEC_CNT_VGPR_SEC_SIZE__SI__CI 9 -#define SQ_TEX_CLK_CTRL_DEFAULT 0x00000000 -#define SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_MASK 0x0000ffff -#define SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT 0x00000000 -#define SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_SIZE 16 -#define SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_MASK 0xffff0000 -#define SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT 16 -#define SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_SIZE 16 -#define SQ_TEX_CLK_CTRL_REG_SIZE 32 -#define SQ_THREAD_TRACE_BASE2_ADDR_HI_MASK__CI__VI 0x0000000f -#define SQ_THREAD_TRACE_BASE2_ADDR_HI_SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_BASE2_ADDR_HI_SIZE__CI__VI 4 -#define SQ_THREAD_TRACE_BASE2_ATC_MASK__CI 0x00000010 -#define SQ_THREAD_TRACE_BASE2_ATC_SHIFT__CI 4 -#define SQ_THREAD_TRACE_BASE2_ATC_SIZE__CI 1 -#define SQ_THREAD_TRACE_BASE2_DEFAULT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_BASE2_REG_SIZE__CI__VI 32 -#define SQ_THREAD_TRACE_BASE_ADDR_MASK 0xffffffff -#define SQ_THREAD_TRACE_BASE_ADDR_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_BASE_ADDR_SIZE 32 -#define SQ_THREAD_TRACE_BASE_DEFAULT 0x00000000 -#define SQ_THREAD_TRACE_BASE_REG_SIZE 32 -#define SQ_THREAD_TRACE_CNTR_CNTR_MASK 0xffffffff -#define SQ_THREAD_TRACE_CNTR_CNTR_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_CNTR_CNTR_SIZE 32 -#define SQ_THREAD_TRACE_CNTR_DEFAULT 0x00000000 -#define SQ_THREAD_TRACE_CNTR_REG_SIZE 32 -#define SQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000 -#define SQ_THREAD_TRACE_CTRL_REG_SIZE 32 -#define SQ_THREAD_TRACE_CTRL_RESET_BUFFER_MASK 0x80000000 -#define SQ_THREAD_TRACE_CTRL_RESET_BUFFER_SHIFT 31 -#define SQ_THREAD_TRACE_CTRL_RESET_BUFFER_SIZE 1 -#define SQ_THREAD_TRACE_HIWATER_DEFAULT 0x00000000 -#define SQ_THREAD_TRACE_HIWATER_HIWATER_MASK 0x00000007 -#define SQ_THREAD_TRACE_HIWATER_HIWATER_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_HIWATER_HIWATER_SIZE 3 -#define SQ_THREAD_TRACE_HIWATER_REG_SIZE 32 -#define SQ_THREAD_TRACE_LFSR_CS__SI__CI 0x00008097 -#define SQ_THREAD_TRACE_LFSR_ES__SI__CI 0x00008029 -#define SQ_THREAD_TRACE_LFSR_GS__SI__CI 0x0000801f -#define SQ_THREAD_TRACE_LFSR_HS__SI__CI 0x0000805e -#define SQ_THREAD_TRACE_LFSR_LS__SI__CI 0x0000806b -#define SQ_THREAD_TRACE_LFSR_PS__SI__CI 0x00008016 -#define SQ_THREAD_TRACE_LFSR_VS__SI__CI 0x0000801c -#define SQ_THREAD_TRACE_MASK_CU_SEL_MASK 0x0000001f -#define SQ_THREAD_TRACE_MASK_CU_SEL_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_MASK_CU_SEL_SIZE 5 -#define SQ_THREAD_TRACE_MASK_DEFAULT__CI 0xffffcf80 -#define SQ_THREAD_TRACE_MASK_DEFAULT__SI 0xffff0f00 -#define SQ_THREAD_TRACE_MASK_RANDOM_SEED_MASK__SI__CI 0xffff0000 -#define SQ_THREAD_TRACE_MASK_RANDOM_SEED_SHIFT__SI__CI 16 -#define SQ_THREAD_TRACE_MASK_RANDOM_SEED_SIZE__SI__CI 16 -#define SQ_THREAD_TRACE_MASK_REG_SIZE 32 -#define SQ_THREAD_TRACE_MASK_REG_STALL_EN_MASK__CI__VI 0x00000080 -#define SQ_THREAD_TRACE_MASK_REG_STALL_EN_SHIFT__CI__VI 7 -#define SQ_THREAD_TRACE_MASK_REG_STALL_EN_SIZE__CI__VI 1 -#define SQ_THREAD_TRACE_MASK_SH_SEL_MASK 0x00000020 -#define SQ_THREAD_TRACE_MASK_SH_SEL_SHIFT 5 -#define SQ_THREAD_TRACE_MASK_SH_SEL_SIZE 1 -#define SQ_THREAD_TRACE_MASK_SIMD_EN_MASK 0x00000f00 -#define SQ_THREAD_TRACE_MASK_SIMD_EN_SHIFT 8 -#define SQ_THREAD_TRACE_MASK_SIMD_EN_SIZE 4 -#define SQ_THREAD_TRACE_MASK_SPI_STALL_EN_MASK__CI__VI 0x00004000 -#define SQ_THREAD_TRACE_MASK_SPI_STALL_EN_SHIFT__CI__VI 14 -#define SQ_THREAD_TRACE_MASK_SPI_STALL_EN_SIZE__CI__VI 1 -#define SQ_THREAD_TRACE_MASK_SQ_STALL_EN_MASK__CI__VI 0x00008000 -#define SQ_THREAD_TRACE_MASK_SQ_STALL_EN_SHIFT__CI__VI 15 -#define SQ_THREAD_TRACE_MASK_SQ_STALL_EN_SIZE__CI__VI 1 -#define SQ_THREAD_TRACE_MASK_VM_ID_MASK_MASK 0x00003000 -#define SQ_THREAD_TRACE_MASK_VM_ID_MASK_SHIFT 12 -#define SQ_THREAD_TRACE_MASK_VM_ID_MASK_SIZE 2 -#define SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_MASK 0x02000000 -#define SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_SHIFT 25 -#define SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_SIZE 1 -#define SQ_THREAD_TRACE_MODE_CAPTURE_MODE_MASK 0x01800000 -#define SQ_THREAD_TRACE_MODE_CAPTURE_MODE_SHIFT 23 -#define SQ_THREAD_TRACE_MODE_CAPTURE_MODE_SIZE 2 -#define SQ_THREAD_TRACE_MODE_DEFAULT 0x02049249 -#define SQ_THREAD_TRACE_MODE_INTERRUPT_EN_MASK 0x40000000 -#define SQ_THREAD_TRACE_MODE_INTERRUPT_EN_SHIFT 30 -#define SQ_THREAD_TRACE_MODE_INTERRUPT_EN_SIZE 1 -#define SQ_THREAD_TRACE_MODE_ISSUE_MASK_MASK 0x18000000 -#define SQ_THREAD_TRACE_MODE_ISSUE_MASK_SHIFT 27 -#define SQ_THREAD_TRACE_MODE_ISSUE_MASK_SIZE 2 -#define SQ_THREAD_TRACE_MODE_MASK_CS_MASK 0x001c0000 -#define SQ_THREAD_TRACE_MODE_MASK_CS_SHIFT 18 -#define SQ_THREAD_TRACE_MODE_MASK_CS_SIZE 3 -#define SQ_THREAD_TRACE_MODE_MASK_ES_MASK 0x00000e00 -#define SQ_THREAD_TRACE_MODE_MASK_ES_SHIFT 9 -#define SQ_THREAD_TRACE_MODE_MASK_ES_SIZE 3 -#define SQ_THREAD_TRACE_MODE_MASK_GS_MASK 0x000001c0 -#define SQ_THREAD_TRACE_MODE_MASK_GS_SHIFT 6 -#define SQ_THREAD_TRACE_MODE_MASK_GS_SIZE 3 -#define SQ_THREAD_TRACE_MODE_MASK_HS_MASK 0x00007000 -#define SQ_THREAD_TRACE_MODE_MASK_HS_SHIFT 12 -#define SQ_THREAD_TRACE_MODE_MASK_HS_SIZE 3 -#define SQ_THREAD_TRACE_MODE_MASK_LS_MASK 0x00038000 -#define SQ_THREAD_TRACE_MODE_MASK_LS_SHIFT 15 -#define SQ_THREAD_TRACE_MODE_MASK_LS_SIZE 3 -#define SQ_THREAD_TRACE_MODE_MASK_PS_MASK 0x00000007 -#define SQ_THREAD_TRACE_MODE_MASK_PS_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_MODE_MASK_PS_SIZE 3 -#define SQ_THREAD_TRACE_MODE_MASK_VS_MASK 0x00000038 -#define SQ_THREAD_TRACE_MODE_MASK_VS_SHIFT 3 -#define SQ_THREAD_TRACE_MODE_MASK_VS_SIZE 3 -#define SQ_THREAD_TRACE_MODE_MODE_MASK 0x00600000 -#define SQ_THREAD_TRACE_MODE_MODE_SHIFT 21 -#define SQ_THREAD_TRACE_MODE_MODE_SIZE 2 -#define SQ_THREAD_TRACE_MODE_PRIV_MASK 0x04000000 -#define SQ_THREAD_TRACE_MODE_PRIV_SHIFT 26 -#define SQ_THREAD_TRACE_MODE_PRIV_SIZE 1 -#define SQ_THREAD_TRACE_MODE_REG_SIZE 32 -#define SQ_THREAD_TRACE_MODE_TEST_MODE_MASK 0x20000000 -#define SQ_THREAD_TRACE_MODE_TEST_MODE_SHIFT 29 -#define SQ_THREAD_TRACE_MODE_TEST_MODE_SIZE 1 -#define SQ_THREAD_TRACE_MODE_WRAP_MASK 0x80000000 -#define SQ_THREAD_TRACE_MODE_WRAP_SHIFT 31 -#define SQ_THREAD_TRACE_MODE_WRAP_SIZE 1 -#define SQ_THREAD_TRACE_PERF_MASK_DEFAULT 0xffffffff -#define SQ_THREAD_TRACE_PERF_MASK_REG_SIZE 32 -#define SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_MASK 0x0000ffff -#define SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_SIZE 16 -#define SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_MASK 0xffff0000 -#define SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_SHIFT 16 -#define SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_SIZE 16 -#define SQ_THREAD_TRACE_SIZE_DEFAULT 0x00000000 -#define SQ_THREAD_TRACE_SIZE_REG_SIZE 32 -#define SQ_THREAD_TRACE_SIZE_SIZE_MASK 0x003fffff -#define SQ_THREAD_TRACE_SIZE_SIZE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_SIZE_SIZE_SIZE 22 -#define SQ_THREAD_TRACE_STATUS_BUSY_MASK 0x40000000 -#define SQ_THREAD_TRACE_STATUS_BUSY_SHIFT 30 -#define SQ_THREAD_TRACE_STATUS_BUSY_SIZE 1 -#define SQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000 -#define SQ_THREAD_TRACE_STATUS_FINISH_DONE_MASK__CI__VI 0x03ff0000 -#define SQ_THREAD_TRACE_STATUS_FINISH_DONE_MASK__SI 0x00070000 -#define SQ_THREAD_TRACE_STATUS_FINISH_DONE_SHIFT 16 -#define SQ_THREAD_TRACE_STATUS_FINISH_DONE_SIZE__CI__VI 10 -#define SQ_THREAD_TRACE_STATUS_FINISH_DONE_SIZE__SI 3 -#define SQ_THREAD_TRACE_STATUS_FINISH_PENDING_MASK__CI__VI 0x000003ff -#define SQ_THREAD_TRACE_STATUS_FINISH_PENDING_MASK__SI 0x00000007 -#define SQ_THREAD_TRACE_STATUS_FINISH_PENDING_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_STATUS_FINISH_PENDING_SIZE__CI__VI 10 -#define SQ_THREAD_TRACE_STATUS_FINISH_PENDING_SIZE__SI 3 -#define SQ_THREAD_TRACE_STATUS_FULL_MASK 0x80000000 -#define SQ_THREAD_TRACE_STATUS_FULL_SHIFT 31 -#define SQ_THREAD_TRACE_STATUS_FULL_SIZE 1 -#define SQ_THREAD_TRACE_STATUS_NEW_BUF_MASK 0x20000000 -#define SQ_THREAD_TRACE_STATUS_NEW_BUF_SHIFT 29 -#define SQ_THREAD_TRACE_STATUS_NEW_BUF_SIZE 1 -#define SQ_THREAD_TRACE_STATUS_REG_SIZE 32 -#define SQ_THREAD_TRACE_TIME_UNIT 0x00000004 -#define SQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT__CI 0x0000ffff -#define SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_MASK__CI 0x0000ffff -#define SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_SIZE__CI 16 -#define SQ_THREAD_TRACE_TOKEN_MASK2_REG_SIZE__CI__VI 32 -#define SQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00ffffff -#define SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_MASK__CI__VI 0x01000000 -#define SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_SHIFT__CI__VI 24 -#define SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_SIZE__CI__VI 1 -#define SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_MASK 0x00ff0000 -#define SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_SHIFT 16 -#define SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_SIZE 8 -#define SQ_THREAD_TRACE_TOKEN_MASK_REG_SIZE 32 -#define SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_MASK 0x0000ffff -#define SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_SIZE 16 -#define SQ_THREAD_TRACE_USERDATA_0_DATA_MASK 0xffffffff -#define SQ_THREAD_TRACE_USERDATA_0_DATA_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_0_DATA_SIZE 32 -#define SQ_THREAD_TRACE_USERDATA_0_REG_SIZE 32 -#define SQ_THREAD_TRACE_USERDATA_1_DATA_MASK 0xffffffff -#define SQ_THREAD_TRACE_USERDATA_1_DATA_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_1_DATA_SIZE 32 -#define SQ_THREAD_TRACE_USERDATA_1_REG_SIZE 32 -#define SQ_THREAD_TRACE_USERDATA_2_DATA_MASK 0xffffffff -#define SQ_THREAD_TRACE_USERDATA_2_DATA_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_2_DATA_SIZE 32 -#define SQ_THREAD_TRACE_USERDATA_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_USERDATA_3_DATA_MASK 0xffffffff -#define SQ_THREAD_TRACE_USERDATA_3_DATA_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_3_DATA_SIZE 32 -#define SQ_THREAD_TRACE_USERDATA_3_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_CMN_REG_SIZE 16 -#define SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_MASK 0x0000fc00 -#define SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_SHIFT 10 -#define SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_SIZE 6 -#define SQ_THREAD_TRACE_WORD_EVENT_REG_SIZE 16 -#define SQ_THREAD_TRACE_WORD_EVENT_SH_ID_MASK 0x00000020 -#define SQ_THREAD_TRACE_WORD_EVENT_SH_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_EVENT_SH_ID_SIZE 1 -#define SQ_THREAD_TRACE_WORD_EVENT_STAGE_MASK 0x000001c0 -#define SQ_THREAD_TRACE_WORD_EVENT_STAGE_SHIFT 6 -#define SQ_THREAD_TRACE_WORD_EVENT_STAGE_SIZE 3 -#define SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_MASK 0xffff0000 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_SHIFT 16 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_SIZE 16 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_MASK 0x00000600 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_SHIFT 9 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_SIZE 2 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_MASK 0x000001e0 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_MASK 0x00ffffff -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_SIZE 24 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_INST_REG_SIZE 16 -#define SQ_THREAD_TRACE_WORD_INST_SIMD_ID_MASK 0x00000600 -#define SQ_THREAD_TRACE_WORD_INST_SIMD_ID_SHIFT 9 -#define SQ_THREAD_TRACE_WORD_INST_SIMD_ID_SIZE 2 -#define SQ_THREAD_TRACE_WORD_INST_SIZE_MASK__SI__CI 0x00000800 -#define SQ_THREAD_TRACE_WORD_INST_SIZE_SHIFT__SI__CI 11 -#define SQ_THREAD_TRACE_WORD_INST_SIZE_SIZE__SI__CI 1 -#define SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_MASK 0x000003c0 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_SHIFT 6 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_MASK 0xffff0000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_SHIFT 16 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_SIZE 16 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_MASK 0x00000020 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_SIZE 1 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_MASK 0x0000c000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_SHIFT 14 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_SIZE 2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_MASK 0x00003c00 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_SHIFT 10 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_MASK 0x0000ffff -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_SIZE 16 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_REG_SIZE 16 -#define SQ_THREAD_TRACE_WORD_INST_WAVE_ID_MASK 0x000001e0 -#define SQ_THREAD_TRACE_WORD_INST_WAVE_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_INST_WAVE_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST0_MASK 0x00000300 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST0_SHIFT 8 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST0_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST1_MASK 0x00000c00 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST1_SHIFT 10 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST1_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST2_MASK 0x00003000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST2_SHIFT 12 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST2_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST3_MASK 0x0000c000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST3_SHIFT 14 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST3_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST4_MASK 0x00030000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST4_SHIFT 16 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST4_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST5_MASK 0x000c0000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST5_SHIFT 18 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST5_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST6_MASK 0x00300000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST6_SHIFT 20 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST6_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST7_MASK 0x00c00000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST7_SHIFT 22 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST7_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST8_MASK 0x03000000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST8_SHIFT 24 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST8_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST9_MASK 0x0c000000 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST9_SHIFT 26 -#define SQ_THREAD_TRACE_WORD_ISSUE_INST9_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_MASK 0x00000060 -#define SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_SIZE 2 -#define SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_MASK__CI__VI 0x0000e000 -#define SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_MASK__SI 0x000000c0 -#define SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_SHIFT__CI__VI 13 -#define SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_SHIFT__SI 6 -#define SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_SIZE__CI__VI 3 -#define SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_SIZE__SI 2 -#define SQ_THREAD_TRACE_WORD_MISC_REG_SIZE 16 -#define SQ_THREAD_TRACE_WORD_MISC_SH_ID_MASK__CI__VI 0x00001000 -#define SQ_THREAD_TRACE_WORD_MISC_SH_ID_MASK__SI 0x00000020 -#define SQ_THREAD_TRACE_WORD_MISC_SH_ID_SHIFT__CI__VI 12 -#define SQ_THREAD_TRACE_WORD_MISC_SH_ID_SHIFT__SI 5 -#define SQ_THREAD_TRACE_WORD_MISC_SH_ID_SIZE 1 -#define SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_MASK__CI__VI 0x00000ff0 -#define SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_MASK__SI 0x00000010 -#define SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_SIZE__CI__VI 8 -#define SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_SIZE__SI 1 -#define SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_MASK 0x01fff000 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_SHIFT 12 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_SIZE 13 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_MASK 0xfe000000 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_SHIFT 25 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_SIZE 7 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_MASK 0x00000c00 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_SHIFT 10 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_SIZE 2 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_MASK 0x000003c0 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_SHIFT 6 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_MASK 0x00000020 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_SIZE 1 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_MASK 0x0000003f -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_SIZE 6 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_MASK 0x0007ffc0 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_SHIFT 6 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_SIZE 13 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_MASK 0xfff80000 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_SHIFT 19 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_SIZE 13 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_DISPATCHER_MASK__SI 0x000003e0 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_DISPATCHER_SHIFT__SI 5 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_DISPATCHER_SIZE__SI 5 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_MASK__CI__VI 0x00000180 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_SHIFT__CI__VI 7 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_SIZE__CI__VI 2 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_MASK__CI__VI 0x00000060 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_SHIFT__CI__VI 5 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_SIZE__CI__VI 2 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_MASK 0xffff0000 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_SHIFT 16 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_SIZE 16 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_MASK__CI__VI 0x00000200 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_SHIFT__CI__VI 9 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_SIZE__CI__VI 1 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_MASK 0x00008000 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_SHIFT 15 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_SIZE 1 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_MASK 0x00004000 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_SHIFT 14 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_SIZE 1 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_MASK 0x00001c00 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_SHIFT 10 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_SIZE 3 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_MASK 0xffffffff -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_SIZE 32 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_MASK__CI__VI 0xffff0000 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_SHIFT__CI__VI 16 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_SIZE__CI__VI 16 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_MASK__CI__VI 0x00000180 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_SHIFT__CI__VI 7 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_SIZE__CI__VI 2 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_MASK__CI__VI 0x00000060 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_SHIFT__CI__VI 5 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_SIZE__CI__VI 2 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_MASK__CI__VI 0x0000fe00 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_SHIFT__CI__VI 9 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_SIZE__CI__VI 7 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_SIZE__CI__VI 32 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_MASK__CI__VI 0x00000010 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_SHIFT__CI__VI 4 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_SIZE__CI__VI 1 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_MASK__CI__VI 0x0000000f -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_SIZE__CI__VI 4 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_MASK__CI__VI 0x0000ffff -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_SHIFT__CI__VI 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_SIZE__CI__VI 16 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_REG_SIZE__CI__VI 32 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_MASK 0xffff0000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_SHIFT 16 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_SIZE 16 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_MASK 0xffffffff -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_SIZE 32 -#define SQ_THREAD_TRACE_WORD_TIME_DEFAULT__SI 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIME_PACKET_LOST_MASK__SI 0x00008000 -#define SQ_THREAD_TRACE_WORD_TIME_PACKET_LOST_SHIFT__SI 15 -#define SQ_THREAD_TRACE_WORD_TIME_PACKET_LOST_SIZE__SI 1 -#define SQ_THREAD_TRACE_WORD_TIME_REG_SIZE__SI 16 -#define SQ_THREAD_TRACE_WORD_TIME_TIME_DELTA_MASK__SI 0x00003ff0 -#define SQ_THREAD_TRACE_WORD_TIME_TIME_DELTA_SHIFT__SI 4 -#define SQ_THREAD_TRACE_WORD_TIME_TIME_DELTA_SIZE__SI 10 -#define SQ_THREAD_TRACE_WORD_TIME_TIME_RESET_MASK__SI 0x00004000 -#define SQ_THREAD_TRACE_WORD_TIME_TIME_RESET_SHIFT__SI 14 -#define SQ_THREAD_TRACE_WORD_TIME_TIME_RESET_SIZE__SI 1 -#define SQ_THREAD_TRACE_WORD_TIME_TOKEN_TYPE_MASK__SI 0x0000000f -#define SQ_THREAD_TRACE_WORD_TIME_TOKEN_TYPE_SHIFT__SI 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIME_TOKEN_TYPE_SIZE__SI 4 -#define SQ_THREAD_TRACE_WORD_WAVE_CU_ID_MASK 0x000003c0 -#define SQ_THREAD_TRACE_WORD_WAVE_CU_ID_SHIFT 6 -#define SQ_THREAD_TRACE_WORD_WAVE_CU_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_WAVE_REG_SIZE 16 -#define SQ_THREAD_TRACE_WORD_WAVE_SH_ID_MASK 0x00000020 -#define SQ_THREAD_TRACE_WORD_WAVE_SH_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_WAVE_SH_ID_SIZE 1 -#define SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_MASK 0x0000c000 -#define SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_SHIFT 14 -#define SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_SIZE 2 -#define SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_MASK 0x1fc00000 -#define SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_SHIFT 22 -#define SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_SIZE 7 -#define SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_MASK 0x000003c0 -#define SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_SHIFT 6 -#define SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_MASK 0x001f0000 -#define SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_SHIFT 16 -#define SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_SIZE 5 -#define SQ_THREAD_TRACE_WORD_WAVE_START_REG_SIZE 32 -#define SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_MASK 0x00000020 -#define SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_SHIFT 5 -#define SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_SIZE 1 -#define SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_MASK 0x0000c000 -#define SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_SHIFT 14 -#define SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_SIZE 2 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_MASK 0xe0000000 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_SHIFT 29 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_SIZE 3 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000 -#define SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_SHIFT 21 -#define SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_SIZE 1 -#define SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_MASK 0x00003c00 -#define SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_SHIFT 10 -#define SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_SIZE 4 -#define SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_MASK 0x00000010 -#define SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_SHIFT 4 -#define SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_SIZE 1 -#define SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_MASK 0x0000000f -#define SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_SIZE 4 -#define SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_MASK 0x00003c00 -#define SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_SHIFT 10 -#define SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_SIZE 4 -#define SQ_THREAD_TRACE_WPTR_READ_OFFSET_MASK 0xc0000000 -#define SQ_THREAD_TRACE_WPTR_READ_OFFSET_SHIFT 30 -#define SQ_THREAD_TRACE_WPTR_READ_OFFSET_SIZE 2 -#define SQ_THREAD_TRACE_WPTR_REG_SIZE 32 -#define SQ_THREAD_TRACE_WPTR_WPTR_MASK 0x3fffffff -#define SQ_THREAD_TRACE_WPTR_WPTR_SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WPTR_WPTR_SIZE 30 -#define SQ_TIME_HI_DEFAULT 0x00000000 -#define SQ_TIME_HI_REG_SIZE 32 -#define SQ_TIME_HI_TIME_MASK 0xffffffff -#define SQ_TIME_HI_TIME_SHIFT 0x00000000 -#define SQ_TIME_HI_TIME_SIZE 32 -#define SQ_TIME_LO_DEFAULT 0x00000000 -#define SQ_TIME_LO_REG_SIZE 32 -#define SQ_TIME_LO_TIME_MASK 0xffffffff -#define SQ_TIME_LO_TIME_SHIFT 0x00000000 -#define SQ_TIME_LO_TIME_SIZE 32 -#define SQ_WAVE_EXEC_HI_EXEC_HI_MASK 0xffffffff -#define SQ_WAVE_EXEC_HI_EXEC_HI_SHIFT 0x00000000 -#define SQ_WAVE_EXEC_HI_EXEC_HI_SIZE 32 -#define SQ_WAVE_EXEC_HI_REG_SIZE 32 -#define SQ_WAVE_EXEC_LO_EXEC_LO_MASK 0xffffffff -#define SQ_WAVE_EXEC_LO_EXEC_LO_SHIFT 0x00000000 -#define SQ_WAVE_EXEC_LO_EXEC_LO_SIZE 32 -#define SQ_WAVE_EXEC_LO_REG_SIZE 32 -#define SQ_WAVE_GPR_ALLOC_REG_SIZE 32 -#define SQ_WAVE_GPR_ALLOC_SGPR_BASE_MASK 0x003f0000 -#define SQ_WAVE_GPR_ALLOC_SGPR_BASE_SHIFT 16 -#define SQ_WAVE_GPR_ALLOC_SGPR_BASE_SIZE 6 -#define SQ_WAVE_GPR_ALLOC_SGPR_SIZE_MASK 0x0f000000 -#define SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT 24 -#define SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE 4 -#define SQ_WAVE_GPR_ALLOC_VGPR_BASE_MASK 0x0000003f -#define SQ_WAVE_GPR_ALLOC_VGPR_BASE_SHIFT 0x00000000 -#define SQ_WAVE_GPR_ALLOC_VGPR_BASE_SIZE 6 -#define SQ_WAVE_GPR_ALLOC_VGPR_SIZE_MASK 0x00003f00 -#define SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT 8 -#define SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE 6 -#define SQ_WAVE_HW_ID_CU_ID_MASK 0x00000f00 -#define SQ_WAVE_HW_ID_CU_ID_SHIFT 8 -#define SQ_WAVE_HW_ID_CU_ID_SIZE 4 -#define SQ_WAVE_HW_ID_ME_ID_MASK__CI__VI 0xc0000000 -#define SQ_WAVE_HW_ID_ME_ID_SHIFT__CI__VI 30 -#define SQ_WAVE_HW_ID_ME_ID_SIZE__CI__VI 2 -#define SQ_WAVE_HW_ID_PIPE_ID_MASK__CI__VI 0x000000c0 -#define SQ_WAVE_HW_ID_PIPE_ID_SHIFT__CI__VI 6 -#define SQ_WAVE_HW_ID_PIPE_ID_SIZE__CI__VI 2 -#define SQ_WAVE_HW_ID_QUEUE_ID_MASK__CI__VI 0x07000000 -#define SQ_WAVE_HW_ID_QUEUE_ID_SHIFT__CI__VI 24 -#define SQ_WAVE_HW_ID_QUEUE_ID_SIZE__CI__VI 3 -#define SQ_WAVE_HW_ID_REG_SIZE 32 -#define SQ_WAVE_HW_ID_RING_ID_MASK__SI 0x07000000 -#define SQ_WAVE_HW_ID_RING_ID_SHIFT__SI 24 -#define SQ_WAVE_HW_ID_RING_ID_SIZE__SI 3 -#define SQ_WAVE_HW_ID_SE_ID_MASK__CI__VI 0x00006000 -#define SQ_WAVE_HW_ID_SE_ID_MASK__SI 0x00002000 -#define SQ_WAVE_HW_ID_SE_ID_SHIFT 13 -#define SQ_WAVE_HW_ID_SE_ID_SIZE__CI__VI 2 -#define SQ_WAVE_HW_ID_SE_ID_SIZE__SI 1 -#define SQ_WAVE_HW_ID_SH_ID_MASK 0x00001000 -#define SQ_WAVE_HW_ID_SH_ID_SHIFT 12 -#define SQ_WAVE_HW_ID_SH_ID_SIZE 1 -#define SQ_WAVE_HW_ID_SIMD_ID_MASK 0x00000030 -#define SQ_WAVE_HW_ID_SIMD_ID_SHIFT 4 -#define SQ_WAVE_HW_ID_SIMD_ID_SIZE 2 -#define SQ_WAVE_HW_ID_STATE_ID_MASK 0x38000000 -#define SQ_WAVE_HW_ID_STATE_ID_SHIFT 27 -#define SQ_WAVE_HW_ID_STATE_ID_SIZE 3 -#define SQ_WAVE_HW_ID_TG_ID_MASK 0x000f0000 -#define SQ_WAVE_HW_ID_TG_ID_SHIFT 16 -#define SQ_WAVE_HW_ID_TG_ID_SIZE 4 -#define SQ_WAVE_HW_ID_VM_ID_MASK 0x00f00000 -#define SQ_WAVE_HW_ID_VM_ID_SHIFT 20 -#define SQ_WAVE_HW_ID_VM_ID_SIZE 4 -#define SQ_WAVE_HW_ID_WAVE_ID_MASK 0x0000000f -#define SQ_WAVE_HW_ID_WAVE_ID_SHIFT 0x00000000 -#define SQ_WAVE_HW_ID_WAVE_ID_SIZE 4 -#define SQ_WAVE_IB_DBG0_ECC_ST_SIZE 2 -#define SQ_WAVE_IB_DBG0_HYB_CNT_SIZE 2 -#define SQ_WAVE_IB_DBG0_IBUF_RPTR_MASK 0x00000300 -#define SQ_WAVE_IB_DBG0_IBUF_RPTR_SHIFT 8 -#define SQ_WAVE_IB_DBG0_IBUF_RPTR_SIZE 2 -#define SQ_WAVE_IB_DBG0_IBUF_ST_MASK 0x00000007 -#define SQ_WAVE_IB_DBG0_IBUF_ST_SHIFT 0x00000000 -#define SQ_WAVE_IB_DBG0_IBUF_ST_SIZE 3 -#define SQ_WAVE_IB_DBG0_IBUF_WPTR_MASK 0x00000c00 -#define SQ_WAVE_IB_DBG0_IBUF_WPTR_SHIFT 10 -#define SQ_WAVE_IB_DBG0_IBUF_WPTR_SIZE 2 -#define SQ_WAVE_IB_DBG0_INST_STR_ST_SHIFT 16 -#define SQ_WAVE_IB_DBG0_IS_HYB_SIZE 1 -#define SQ_WAVE_IB_DBG0_KILL_MASK__CI 0x08000000 -#define SQ_WAVE_IB_DBG0_KILL_SHIFT__CI 27 -#define SQ_WAVE_IB_DBG0_KILL_SIZE__CI__VI 1 -#define SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_MASK__CI 0x10000000 -#define SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_SHIFT__CI 28 -#define SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_SIZE__CI__VI 1 -#define SQ_WAVE_IB_DBG0_NEED_NEXT_DW_MASK 0x00000010 -#define SQ_WAVE_IB_DBG0_NEED_NEXT_DW_SHIFT 4 -#define SQ_WAVE_IB_DBG0_NEED_NEXT_DW_SIZE 1 -#define SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_MASK 0x000000e0 -#define SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_SHIFT 5 -#define SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_SIZE 3 -#define SQ_WAVE_IB_DBG0_PC_INVALID_MASK 0x00000008 -#define SQ_WAVE_IB_DBG0_PC_INVALID_SHIFT 3 -#define SQ_WAVE_IB_DBG0_PC_INVALID_SIZE 1 -#define SQ_WAVE_IB_DBG0_REG_SIZE 32 -#define SQ_WAVE_IB_STS_DEFAULT 0x00000000 -#define SQ_WAVE_IB_STS_EXP_CNT_MASK 0x00000070 -#define SQ_WAVE_IB_STS_EXP_CNT_SHIFT 4 -#define SQ_WAVE_IB_STS_EXP_CNT_SIZE 3 -#define SQ_WAVE_IB_STS_LGKM_CNT_MASK__CI__VI 0x00000f00 -#define SQ_WAVE_IB_STS_LGKM_CNT_MASK__SI 0x00001f00 -#define SQ_WAVE_IB_STS_LGKM_CNT_SHIFT 8 -#define SQ_WAVE_IB_STS_LGKM_CNT_SIZE__CI__VI 4 -#define SQ_WAVE_IB_STS_LGKM_CNT_SIZE__SI 5 -#define SQ_WAVE_IB_STS_REG_SIZE 32 -#define SQ_WAVE_IB_STS_VALU_CNT_MASK__CI__VI 0x00007000 -#define SQ_WAVE_IB_STS_VALU_CNT_MASK__SI 0x0000e000 -#define SQ_WAVE_IB_STS_VALU_CNT_SHIFT__CI__VI 12 -#define SQ_WAVE_IB_STS_VALU_CNT_SHIFT__SI 13 -#define SQ_WAVE_IB_STS_VALU_CNT_SIZE 3 -#define SQ_WAVE_IB_STS_VM_CNT_MASK 0x0000000f -#define SQ_WAVE_IB_STS_VM_CNT_SHIFT 0x00000000 -#define SQ_WAVE_IB_STS_VM_CNT_SIZE 4 -#define SQ_WAVE_INST_DW0_INST_DW0_MASK 0xffffffff -#define SQ_WAVE_INST_DW0_INST_DW0_SHIFT 0x00000000 -#define SQ_WAVE_INST_DW0_INST_DW0_SIZE 32 -#define SQ_WAVE_INST_DW0_REG_SIZE 32 -#define SQ_WAVE_INST_DW1_INST_DW1_MASK 0xffffffff -#define SQ_WAVE_INST_DW1_INST_DW1_SHIFT 0x00000000 -#define SQ_WAVE_INST_DW1_INST_DW1_SIZE 32 -#define SQ_WAVE_INST_DW1_REG_SIZE 32 -#define SQ_WAVE_LDS_ALLOC_LDS_BASE_MASK 0x000000ff -#define SQ_WAVE_LDS_ALLOC_LDS_BASE_SHIFT 0x00000000 -#define SQ_WAVE_LDS_ALLOC_LDS_BASE_SIZE 8 -#define SQ_WAVE_LDS_ALLOC_LDS_SIZE_MASK 0x001ff000 -#define SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT 12 -#define SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE 9 -#define SQ_WAVE_LDS_ALLOC_REG_SIZE 32 -#define SQ_WAVE_M0_M0_MASK 0xffffffff -#define SQ_WAVE_M0_M0_SHIFT 0x00000000 -#define SQ_WAVE_M0_M0_SIZE 32 -#define SQ_WAVE_M0_REG_SIZE 32 -#define SQ_WAVE_MODE_CSP_MASK 0xe0000000 -#define SQ_WAVE_MODE_CSP_SHIFT 29 -#define SQ_WAVE_MODE_CSP_SIZE 3 -#define SQ_WAVE_MODE_DEBUG_EN_MASK 0x00000800 -#define SQ_WAVE_MODE_DEBUG_EN_SHIFT 11 -#define SQ_WAVE_MODE_DEBUG_EN_SIZE 1 -#define SQ_WAVE_MODE_DX10_CLAMP_MASK 0x00000100 -#define SQ_WAVE_MODE_DX10_CLAMP_SHIFT 8 -#define SQ_WAVE_MODE_DX10_CLAMP_SIZE 1 -#define SQ_WAVE_MODE_EXCP_EN_MASK__CI__VI 0x001ff000 -#define SQ_WAVE_MODE_EXCP_EN_MASK__SI 0x0007f000 -#define SQ_WAVE_MODE_EXCP_EN_SHIFT 12 -#define SQ_WAVE_MODE_EXCP_EN_SIZE__CI__VI 9 -#define SQ_WAVE_MODE_EXCP_EN_SIZE__SI 7 -#define SQ_WAVE_MODE_FP_DENORM_MASK 0x000000f0 -#define SQ_WAVE_MODE_FP_DENORM_SHIFT 4 -#define SQ_WAVE_MODE_FP_DENORM_SIZE 4 -#define SQ_WAVE_MODE_FP_ROUND_MASK 0x0000000f -#define SQ_WAVE_MODE_FP_ROUND_SHIFT 0x00000000 -#define SQ_WAVE_MODE_FP_ROUND_SIZE 4 -#define SQ_WAVE_MODE_IEEE_MASK 0x00000200 -#define SQ_WAVE_MODE_IEEE_SHIFT 9 -#define SQ_WAVE_MODE_IEEE_SIZE 1 -#define SQ_WAVE_MODE_LOD_CLAMPED_MASK 0x00000400 -#define SQ_WAVE_MODE_LOD_CLAMPED_SHIFT 10 -#define SQ_WAVE_MODE_LOD_CLAMPED_SIZE 1 -#define SQ_WAVE_MODE_REG_SIZE 32 -#define SQ_WAVE_MODE_VSKIP_MASK 0x10000000 -#define SQ_WAVE_MODE_VSKIP_SHIFT 28 -#define SQ_WAVE_MODE_VSKIP_SIZE 1 -#define SQ_WAVE_PC_HI_PC_HI_SHIFT 0x00000000 -#define SQ_WAVE_PC_HI_REG_SIZE 32 -#define SQ_WAVE_PC_LO_PC_LO_MASK 0xffffffff -#define SQ_WAVE_PC_LO_PC_LO_SHIFT 0x00000000 -#define SQ_WAVE_PC_LO_PC_LO_SIZE 32 -#define SQ_WAVE_PC_LO_REG_SIZE 32 -#define SQ_WAVE_STATUS_COND_DBG_SYS_MASK__CI__VI 0x00200000 -#define SQ_WAVE_STATUS_COND_DBG_SYS_SHIFT__CI__VI 21 -#define SQ_WAVE_STATUS_COND_DBG_SYS_SIZE__CI__VI 1 -#define SQ_WAVE_STATUS_COND_DBG_USER_MASK__CI__VI 0x00100000 -#define SQ_WAVE_STATUS_COND_DBG_USER_SHIFT__CI__VI 20 -#define SQ_WAVE_STATUS_COND_DBG_USER_SIZE__CI__VI 1 -#define SQ_WAVE_STATUS_DATA_ATC_MASK__CI 0x00400000 -#define SQ_WAVE_STATUS_DATA_ATC_SHIFT__CI 22 -#define SQ_WAVE_STATUS_DATA_ATC_SIZE__CI 1 -#define SQ_WAVE_STATUS_DISPATCH_CACHE_CTRL_MASK__CI 0x07000000 -#define SQ_WAVE_STATUS_DISPATCH_CACHE_CTRL_SHIFT__CI 24 -#define SQ_WAVE_STATUS_DISPATCH_CACHE_CTRL_SIZE__CI 3 -#define SQ_WAVE_STATUS_ECC_ERR_MASK 0x00020000 -#define SQ_WAVE_STATUS_ECC_ERR_SHIFT 17 -#define SQ_WAVE_STATUS_ECC_ERR_SIZE 1 -#define SQ_WAVE_STATUS_EXECZ_MASK 0x00000200 -#define SQ_WAVE_STATUS_EXECZ_SHIFT 9 -#define SQ_WAVE_STATUS_EXECZ_SIZE 1 -#define SQ_WAVE_STATUS_EXPORT_RDY_MASK 0x00000100 -#define SQ_WAVE_STATUS_EXPORT_RDY_SHIFT 8 -#define SQ_WAVE_STATUS_EXPORT_RDY_SIZE 1 -#define SQ_WAVE_STATUS_HALT_MASK 0x00002000 -#define SQ_WAVE_STATUS_HALT_SHIFT 13 -#define SQ_WAVE_STATUS_HALT_SIZE 1 -#define SQ_WAVE_STATUS_INST_ATC_MASK__CI__VI 0x00800000 -#define SQ_WAVE_STATUS_INST_ATC_SHIFT__CI__VI 23 -#define SQ_WAVE_STATUS_INST_ATC_SIZE__CI__VI 1 -#define SQ_WAVE_STATUS_IN_BARRIER_MASK 0x00001000 -#define SQ_WAVE_STATUS_IN_BARRIER_SHIFT 12 -#define SQ_WAVE_STATUS_IN_BARRIER_SIZE 1 -#define SQ_WAVE_STATUS_IN_TG_MASK 0x00000800 -#define SQ_WAVE_STATUS_IN_TG_SHIFT 11 -#define SQ_WAVE_STATUS_IN_TG_SIZE 1 -#define SQ_WAVE_STATUS_MUST_EXPORT_MASK__CI__VI 0x08000000 -#define SQ_WAVE_STATUS_MUST_EXPORT_SHIFT__CI__VI 27 -#define SQ_WAVE_STATUS_MUST_EXPORT_SIZE__CI__VI 1 -#define SQ_WAVE_STATUS_PERF_EN_MASK 0x00080000 -#define SQ_WAVE_STATUS_PERF_EN_SHIFT 19 -#define SQ_WAVE_STATUS_PERF_EN_SIZE 1 -#define SQ_WAVE_STATUS_PRIV_MASK 0x00000020 -#define SQ_WAVE_STATUS_PRIV_SHIFT 5 -#define SQ_WAVE_STATUS_PRIV_SIZE 1 -#define SQ_WAVE_STATUS_REG_SIZE 32 -#define SQ_WAVE_STATUS_SCC_MASK 0x00000001 -#define SQ_WAVE_STATUS_SCC_SHIFT 0x00000000 -#define SQ_WAVE_STATUS_SCC_SIZE 1 -#define SQ_WAVE_STATUS_SKIP_EXPORT_MASK 0x00040000 -#define SQ_WAVE_STATUS_SKIP_EXPORT_SHIFT 18 -#define SQ_WAVE_STATUS_SKIP_EXPORT_SIZE 1 -#define SQ_WAVE_STATUS_SPI_PRIO_MASK 0x00000006 -#define SQ_WAVE_STATUS_SPI_PRIO_SHIFT 1 -#define SQ_WAVE_STATUS_SPI_PRIO_SIZE 2 -#define SQ_WAVE_STATUS_TRAP_EN_MASK 0x00000040 -#define SQ_WAVE_STATUS_TRAP_EN_SHIFT 6 -#define SQ_WAVE_STATUS_TRAP_EN_SIZE 1 -#define SQ_WAVE_STATUS_TRAP_MASK 0x00004000 -#define SQ_WAVE_STATUS_TRAP_SHIFT 14 -#define SQ_WAVE_STATUS_TRAP_SIZE 1 -#define SQ_WAVE_STATUS_TTRACE_CU_EN_MASK 0x00008000 -#define SQ_WAVE_STATUS_TTRACE_CU_EN_SHIFT 15 -#define SQ_WAVE_STATUS_TTRACE_CU_EN_SIZE 1 -#define SQ_WAVE_STATUS_TTRACE_EN_MASK 0x00000080 -#define SQ_WAVE_STATUS_TTRACE_EN_SHIFT 7 -#define SQ_WAVE_STATUS_TTRACE_EN_SIZE 1 -#define SQ_WAVE_STATUS_VALID_MASK 0x00010000 -#define SQ_WAVE_STATUS_VALID_SHIFT 16 -#define SQ_WAVE_STATUS_VALID_SIZE 1 -#define SQ_WAVE_STATUS_VCCZ_MASK 0x00000400 -#define SQ_WAVE_STATUS_VCCZ_SHIFT 10 -#define SQ_WAVE_STATUS_VCCZ_SIZE 1 -#define SQ_WAVE_STATUS_WAVE_PRIO_MASK__SI__CI 0x00000018 -#define SQ_WAVE_STATUS_WAVE_PRIO_SHIFT__SI__CI 3 -#define SQ_WAVE_STATUS_WAVE_PRIO_SIZE__SI__CI 2 -#define SQ_WAVE_TBA_HI_ADDR_HI_MASK 0x000000ff -#define SQ_WAVE_TBA_HI_ADDR_HI_SHIFT 0x00000000 -#define SQ_WAVE_TBA_HI_ADDR_HI_SIZE 8 -#define SQ_WAVE_TBA_HI_REG_SIZE 32 -#define SQ_WAVE_TBA_LO_ADDR_LO_MASK 0xffffffff -#define SQ_WAVE_TBA_LO_ADDR_LO_SHIFT 0x00000000 -#define SQ_WAVE_TBA_LO_ADDR_LO_SIZE 32 -#define SQ_WAVE_TBA_LO_REG_SIZE 32 -#define SQ_WAVE_TMA_HI_ADDR_HI_MASK 0x000000ff -#define SQ_WAVE_TMA_HI_ADDR_HI_SHIFT 0x00000000 -#define SQ_WAVE_TMA_HI_ADDR_HI_SIZE 8 -#define SQ_WAVE_TMA_HI_REG_SIZE 32 -#define SQ_WAVE_TMA_LO_ADDR_LO_MASK 0xffffffff -#define SQ_WAVE_TMA_LO_ADDR_LO_SHIFT 0x00000000 -#define SQ_WAVE_TMA_LO_ADDR_LO_SIZE 32 -#define SQ_WAVE_TMA_LO_REG_SIZE 32 -#define SQ_WAVE_TRAPSTS_DP_RATE_MASK 0xe0000000 -#define SQ_WAVE_TRAPSTS_DP_RATE_SHIFT 29 -#define SQ_WAVE_TRAPSTS_DP_RATE_SIZE 3 -#define SQ_WAVE_TRAPSTS_EXCP_CYCLE_MASK 0x003f0000 -#define SQ_WAVE_TRAPSTS_EXCP_CYCLE_SHIFT 16 -#define SQ_WAVE_TRAPSTS_EXCP_CYCLE_SIZE 6 -#define SQ_WAVE_TRAPSTS_EXCP_MASK__CI__VI 0x000001ff -#define SQ_WAVE_TRAPSTS_EXCP_MASK__SI 0x0000007f -#define SQ_WAVE_TRAPSTS_EXCP_SHIFT 0x00000000 -#define SQ_WAVE_TRAPSTS_EXCP_SIZE__CI__VI 9 -#define SQ_WAVE_TRAPSTS_EXCP_SIZE__SI 7 -#define SQ_WAVE_TRAPSTS_REG_SIZE 32 -#define SQ_WAVE_TTMP0_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP0_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP0_DATA_SIZE 32 -#define SQ_WAVE_TTMP0_REG_SIZE 32 -#define SQ_WAVE_TTMP10_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP10_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP10_DATA_SIZE 32 -#define SQ_WAVE_TTMP10_REG_SIZE 32 -#define SQ_WAVE_TTMP11_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP11_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP11_DATA_SIZE 32 -#define SQ_WAVE_TTMP11_REG_SIZE 32 -#define SQ_WAVE_TTMP1_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP1_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP1_DATA_SIZE 32 -#define SQ_WAVE_TTMP1_REG_SIZE 32 -#define SQ_WAVE_TTMP2_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP2_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP2_DATA_SIZE 32 -#define SQ_WAVE_TTMP2_REG_SIZE 32 -#define SQ_WAVE_TTMP3_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP3_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP3_DATA_SIZE 32 -#define SQ_WAVE_TTMP3_REG_SIZE 32 -#define SQ_WAVE_TTMP4_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP4_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP4_DATA_SIZE 32 -#define SQ_WAVE_TTMP4_REG_SIZE 32 -#define SQ_WAVE_TTMP5_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP5_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP5_DATA_SIZE 32 -#define SQ_WAVE_TTMP5_REG_SIZE 32 -#define SQ_WAVE_TTMP6_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP6_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP6_DATA_SIZE 32 -#define SQ_WAVE_TTMP6_REG_SIZE 32 -#define SQ_WAVE_TTMP7_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP7_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP7_DATA_SIZE 32 -#define SQ_WAVE_TTMP7_REG_SIZE 32 -#define SQ_WAVE_TTMP8_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP8_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP8_DATA_SIZE 32 -#define SQ_WAVE_TTMP8_REG_SIZE 32 -#define SQ_WAVE_TTMP9_DATA_MASK 0xffffffff -#define SQ_WAVE_TTMP9_DATA_SHIFT 0x00000000 -#define SQ_WAVE_TTMP9_DATA_SIZE 32 -#define SQ_WAVE_TTMP9_REG_SIZE 32 -#define SQ_WAVE_TYPE_PS0 0x00000000 -#define USER_SQC_BANK_DISABLE_DEFAULT 0x00000000 -#define USER_SQC_BANK_DISABLE_REG_SIZE 32 -#define USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK 0x000f0000 -#define USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SHIFT 16 -#define USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SIZE 4 -#define USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK 0x00f00000 -#define USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SHIFT 20 -#define USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SIZE 4 -#define USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK__CI__VI 0x0f000000 -#define USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SHIFT__CI__VI 24 -#define USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SIZE__CI__VI 4 -#define USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK__CI__VI 0xf0000000 -#define USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SHIFT__CI__VI 28 -#define USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SIZE__CI__VI 4 - -// Merged Defines - -#define CC_GC_SHADER_RATE_CONFIG_DEFAULT__VI 0x00000010 -#define CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_MASK__VI 0x00000006 -#define CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_SHIFT__VI 1 -#define CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_SIZE__VI 2 -#define CC_GC_SHADER_RATE_CONFIG_GET_DPFP_RATE__VI(cc_gc_shader_rate_config) \ - ((cc_gc_shader_rate_config & CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_MASK) >> \ - CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_GET_HALF_LDS__VI(cc_gc_shader_rate_config) \ - ((cc_gc_shader_rate_config & CC_GC_SHADER_RATE_CONFIG_HALF_LDS_MASK) >> \ - CC_GC_SHADER_RATE_CONFIG_HALF_LDS_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_GET_SQC_BALANCE_DISABLE__VI(cc_gc_shader_rate_config) \ - ((cc_gc_shader_rate_config & CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK) >> \ - CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_GET_WRITE_DIS__VI(cc_gc_shader_rate_config) \ - ((cc_gc_shader_rate_config & CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_MASK) >> \ - CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_HALF_LDS_MASK__VI 0x00000010 -#define CC_GC_SHADER_RATE_CONFIG_HALF_LDS_SHIFT__VI 4 -#define CC_GC_SHADER_RATE_CONFIG_HALF_LDS_SIZE__VI 1 -#define CC_GC_SHADER_RATE_CONFIG_MASK__VI \ - (CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_MASK | CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_MASK | \ - CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK | CC_GC_SHADER_RATE_CONFIG_HALF_LDS_MASK) - -#define CC_GC_SHADER_RATE_CONFIG_REG_SIZE__VI 32 -#define CC_GC_SHADER_RATE_CONFIG_SET_DPFP_RATE__VI(cc_gc_shader_rate_config_reg, dpfp_rate) \ - cc_gc_shader_rate_config_reg = \ - (cc_gc_shader_rate_config_reg & ~CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_MASK) | \ - (dpfp_rate << CC_GC_SHADER_RATE_CONFIG_DPFP_RATE_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_SET_HALF_LDS__VI(cc_gc_shader_rate_config_reg, half_lds) \ - cc_gc_shader_rate_config_reg = \ - (cc_gc_shader_rate_config_reg & ~CC_GC_SHADER_RATE_CONFIG_HALF_LDS_MASK) | \ - (half_lds << CC_GC_SHADER_RATE_CONFIG_HALF_LDS_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_SET_SQC_BALANCE_DISABLE__VI(cc_gc_shader_rate_config_reg, \ - sqc_balance_disable) \ - cc_gc_shader_rate_config_reg = \ - (cc_gc_shader_rate_config_reg & ~CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK) | \ - (sqc_balance_disable << CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_SET_WRITE_DIS__VI(cc_gc_shader_rate_config_reg, write_dis) \ - cc_gc_shader_rate_config_reg = \ - (cc_gc_shader_rate_config_reg & ~CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_MASK) | \ - (write_dis << CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_SHIFT) - -#define CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK__VI 0x00000008 -#define CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SHIFT__VI 3 -#define CC_GC_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SIZE__VI 1 -#define CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_MASK__VI 0x00000001 -#define CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_SHIFT__VI 0x00000000 -#define CC_GC_SHADER_RATE_CONFIG_WRITE_DIS_SIZE__VI 1 -#define CC_SQC_BANK_DISABLE_GET_SQC0_BANK_DISABLE__VI(cc_sqc_bank_disable) \ - ((cc_sqc_bank_disable & CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK) >> \ - CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_GET_SQC1_BANK_DISABLE__VI(cc_sqc_bank_disable) \ - ((cc_sqc_bank_disable & CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK) >> \ - CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_GET_SQC2_BANK_DISABLE__VI(cc_sqc_bank_disable) \ - ((cc_sqc_bank_disable & CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK) >> \ - CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_GET_SQC3_BANK_DISABLE__VI(cc_sqc_bank_disable) \ - ((cc_sqc_bank_disable & CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK) >> \ - CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_GET_WRITE_DIS__VI(cc_sqc_bank_disable) \ - ((cc_sqc_bank_disable & CC_SQC_BANK_DISABLE_WRITE_DIS_MASK) >> \ - CC_SQC_BANK_DISABLE_WRITE_DIS_SHIFT) - -#define CC_SQC_BANK_DISABLE_MASK__VI \ - (CC_SQC_BANK_DISABLE_WRITE_DIS_MASK | CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK | \ - CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK | CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK | \ - CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK) - -#define CC_SQC_BANK_DISABLE_SET_SQC0_BANK_DISABLE__VI(cc_sqc_bank_disable_reg, sqc0_bank_disable) \ - cc_sqc_bank_disable_reg = \ - (cc_sqc_bank_disable_reg & ~CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK) | \ - (sqc0_bank_disable << CC_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_SET_SQC1_BANK_DISABLE__VI(cc_sqc_bank_disable_reg, sqc1_bank_disable) \ - cc_sqc_bank_disable_reg = \ - (cc_sqc_bank_disable_reg & ~CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK) | \ - (sqc1_bank_disable << CC_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_SET_SQC2_BANK_DISABLE__VI(cc_sqc_bank_disable_reg, sqc2_bank_disable) \ - cc_sqc_bank_disable_reg = \ - (cc_sqc_bank_disable_reg & ~CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK) | \ - (sqc2_bank_disable << CC_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_SET_SQC3_BANK_DISABLE__VI(cc_sqc_bank_disable_reg, sqc3_bank_disable) \ - cc_sqc_bank_disable_reg = \ - (cc_sqc_bank_disable_reg & ~CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK) | \ - (sqc3_bank_disable << CC_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SHIFT) - -#define CC_SQC_BANK_DISABLE_SET_WRITE_DIS__VI(cc_sqc_bank_disable_reg, write_dis) \ - cc_sqc_bank_disable_reg = (cc_sqc_bank_disable_reg & ~CC_SQC_BANK_DISABLE_WRITE_DIS_MASK) | \ - (write_dis << CC_SQC_BANK_DISABLE_WRITE_DIS_SHIFT) - -#define CGTT_SQG_CLK_CTRL_DEFAULT__SI__CI 0x00000200 -#define CGTT_SQG_CLK_CTRL_DEFAULT__VI 0x00000100 -#define CGTT_SQG_CLK_CTRL_GET_CORE_OVERRIDE__VI(cgtt_sqg_clk_ctrl) \ - ((cgtt_sqg_clk_ctrl & CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_MASK) >> \ - CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_GET_OFF_HYSTERESIS__VI(cgtt_sqg_clk_ctrl) \ - ((cgtt_sqg_clk_ctrl & CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_MASK) >> \ - CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_SHIFT) - -#define CGTT_SQG_CLK_CTRL_GET_ON_DELAY__VI(cgtt_sqg_clk_ctrl) \ - ((cgtt_sqg_clk_ctrl & CGTT_SQG_CLK_CTRL_ON_DELAY_MASK) >> CGTT_SQG_CLK_CTRL_ON_DELAY_SHIFT) - -#define CGTT_SQG_CLK_CTRL_GET_PERFMON_OVERRIDE__VI(cgtt_sqg_clk_ctrl) \ - ((cgtt_sqg_clk_ctrl & CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_MASK) >> \ - CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_GET_REG_OVERRIDE__VI(cgtt_sqg_clk_ctrl) \ - ((cgtt_sqg_clk_ctrl & CGTT_SQG_CLK_CTRL_REG_OVERRIDE_MASK) >> \ - CGTT_SQG_CLK_CTRL_REG_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_GET_TTRACE_OVERRIDE__VI(cgtt_sqg_clk_ctrl) \ - ((cgtt_sqg_clk_ctrl & CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_MASK) >> \ - CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_MASK__VI \ - (CGTT_SQG_CLK_CTRL_ON_DELAY_MASK | CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_MASK | \ - CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_MASK | CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_MASK | \ - CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_MASK | CGTT_SQG_CLK_CTRL_REG_OVERRIDE_MASK) - -#define CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_MASK__VI 0x20000000 -#define CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_SHIFT__VI 29 -#define CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_SIZE__VI 1 -#define CGTT_SQG_CLK_CTRL_SET_CORE_OVERRIDE__VI(cgtt_sqg_clk_ctrl_reg, core_override) \ - cgtt_sqg_clk_ctrl_reg = (cgtt_sqg_clk_ctrl_reg & ~CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_MASK) | \ - (core_override << CGTT_SQG_CLK_CTRL_CORE_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_SET_OFF_HYSTERESIS__VI(cgtt_sqg_clk_ctrl_reg, off_hysteresis) \ - cgtt_sqg_clk_ctrl_reg = (cgtt_sqg_clk_ctrl_reg & ~CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_MASK) | \ - (off_hysteresis << CGTT_SQG_CLK_CTRL_OFF_HYSTERESIS_SHIFT) - -#define CGTT_SQG_CLK_CTRL_SET_ON_DELAY__VI(cgtt_sqg_clk_ctrl_reg, on_delay) \ - cgtt_sqg_clk_ctrl_reg = (cgtt_sqg_clk_ctrl_reg & ~CGTT_SQG_CLK_CTRL_ON_DELAY_MASK) | \ - (on_delay << CGTT_SQG_CLK_CTRL_ON_DELAY_SHIFT) - -#define CGTT_SQG_CLK_CTRL_SET_PERFMON_OVERRIDE__VI(cgtt_sqg_clk_ctrl_reg, perfmon_override) \ - cgtt_sqg_clk_ctrl_reg = (cgtt_sqg_clk_ctrl_reg & ~CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_MASK) | \ - (perfmon_override << CGTT_SQG_CLK_CTRL_PERFMON_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_SET_REG_OVERRIDE__VI(cgtt_sqg_clk_ctrl_reg, reg_override) \ - cgtt_sqg_clk_ctrl_reg = (cgtt_sqg_clk_ctrl_reg & ~CGTT_SQG_CLK_CTRL_REG_OVERRIDE_MASK) | \ - (reg_override << CGTT_SQG_CLK_CTRL_REG_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_SET_TTRACE_OVERRIDE__VI(cgtt_sqg_clk_ctrl_reg, ttrace_override) \ - cgtt_sqg_clk_ctrl_reg = (cgtt_sqg_clk_ctrl_reg & ~CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_MASK) | \ - (ttrace_override << CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_SHIFT) - -#define CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_MASK__VI 0x10000000 -#define CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_SHIFT__VI 28 -#define CGTT_SQG_CLK_CTRL_TTRACE_OVERRIDE_SIZE__VI 1 -#define CGTT_SQ_CLK_CTRL_DEFAULT__SI__CI 0x00000200 -#define CGTT_SQ_CLK_CTRL_DEFAULT__VI 0x00000100 -#define CGTT_SQ_CLK_CTRL_GET_CORE_OVERRIDE__VI(cgtt_sq_clk_ctrl) \ - ((cgtt_sq_clk_ctrl & CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_MASK) >> CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_SHIFT) - -#define CGTT_SQ_CLK_CTRL_GET_OFF_HYSTERESIS__VI(cgtt_sq_clk_ctrl) \ - ((cgtt_sq_clk_ctrl & CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_MASK) >> \ - CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_SHIFT) - -#define CGTT_SQ_CLK_CTRL_GET_ON_DELAY__VI(cgtt_sq_clk_ctrl) \ - ((cgtt_sq_clk_ctrl & CGTT_SQ_CLK_CTRL_ON_DELAY_MASK) >> CGTT_SQ_CLK_CTRL_ON_DELAY_SHIFT) - -#define CGTT_SQ_CLK_CTRL_GET_PERFMON_OVERRIDE__VI(cgtt_sq_clk_ctrl) \ - ((cgtt_sq_clk_ctrl & CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_MASK) >> \ - CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_SHIFT) - -#define CGTT_SQ_CLK_CTRL_GET_REG_OVERRIDE__VI(cgtt_sq_clk_ctrl) \ - ((cgtt_sq_clk_ctrl & CGTT_SQ_CLK_CTRL_REG_OVERRIDE_MASK) >> CGTT_SQ_CLK_CTRL_REG_OVERRIDE_SHIFT) - -#define CGTT_SQ_CLK_CTRL_MASK__VI \ - (CGTT_SQ_CLK_CTRL_ON_DELAY_MASK | CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_MASK | \ - CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_MASK | CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_MASK | \ - CGTT_SQ_CLK_CTRL_REG_OVERRIDE_MASK) - -#define CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_MASK__VI 0x20000000 -#define CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_SHIFT__VI 29 -#define CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_SIZE__VI 1 -#define CGTT_SQ_CLK_CTRL_SET_CORE_OVERRIDE__VI(cgtt_sq_clk_ctrl_reg, core_override) \ - cgtt_sq_clk_ctrl_reg = (cgtt_sq_clk_ctrl_reg & ~CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_MASK) | \ - (core_override << CGTT_SQ_CLK_CTRL_CORE_OVERRIDE_SHIFT) - -#define CGTT_SQ_CLK_CTRL_SET_OFF_HYSTERESIS__VI(cgtt_sq_clk_ctrl_reg, off_hysteresis) \ - cgtt_sq_clk_ctrl_reg = (cgtt_sq_clk_ctrl_reg & ~CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_MASK) | \ - (off_hysteresis << CGTT_SQ_CLK_CTRL_OFF_HYSTERESIS_SHIFT) - -#define CGTT_SQ_CLK_CTRL_SET_ON_DELAY__VI(cgtt_sq_clk_ctrl_reg, on_delay) \ - cgtt_sq_clk_ctrl_reg = (cgtt_sq_clk_ctrl_reg & ~CGTT_SQ_CLK_CTRL_ON_DELAY_MASK) | \ - (on_delay << CGTT_SQ_CLK_CTRL_ON_DELAY_SHIFT) - -#define CGTT_SQ_CLK_CTRL_SET_PERFMON_OVERRIDE__VI(cgtt_sq_clk_ctrl_reg, perfmon_override) \ - cgtt_sq_clk_ctrl_reg = (cgtt_sq_clk_ctrl_reg & ~CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_MASK) | \ - (perfmon_override << CGTT_SQ_CLK_CTRL_PERFMON_OVERRIDE_SHIFT) - -#define CGTT_SQ_CLK_CTRL_SET_REG_OVERRIDE__VI(cgtt_sq_clk_ctrl_reg, reg_override) \ - cgtt_sq_clk_ctrl_reg = (cgtt_sq_clk_ctrl_reg & ~CGTT_SQ_CLK_CTRL_REG_OVERRIDE_MASK) | \ - (reg_override << CGTT_SQ_CLK_CTRL_REG_OVERRIDE_SHIFT) - -#define GC_USER_SHADER_RATE_CONFIG_DEFAULT__VI 0x00000010 -#define GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_MASK__VI 0x00000006 -#define GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_SHIFT__VI 1 -#define GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_SIZE__VI 2 -#define GC_USER_SHADER_RATE_CONFIG_GET_DPFP_RATE__VI(gc_user_shader_rate_config) \ - ((gc_user_shader_rate_config & GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_MASK) >> \ - GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_SHIFT) - -#define GC_USER_SHADER_RATE_CONFIG_GET_HALF_LDS__VI(gc_user_shader_rate_config) \ - ((gc_user_shader_rate_config & GC_USER_SHADER_RATE_CONFIG_HALF_LDS_MASK) >> \ - GC_USER_SHADER_RATE_CONFIG_HALF_LDS_SHIFT) - -#define GC_USER_SHADER_RATE_CONFIG_GET_SQC_BALANCE_DISABLE__VI(gc_user_shader_rate_config) \ - ((gc_user_shader_rate_config & GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK) >> \ - GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SHIFT) - -#define GC_USER_SHADER_RATE_CONFIG_HALF_LDS_MASK__VI 0x00000010 -#define GC_USER_SHADER_RATE_CONFIG_HALF_LDS_SHIFT__VI 4 -#define GC_USER_SHADER_RATE_CONFIG_HALF_LDS_SIZE__VI 1 -#define GC_USER_SHADER_RATE_CONFIG_MASK__VI \ - (GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_MASK | \ - GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK | GC_USER_SHADER_RATE_CONFIG_HALF_LDS_MASK) - -#define GC_USER_SHADER_RATE_CONFIG_REG_SIZE__VI 32 -#define GC_USER_SHADER_RATE_CONFIG_SET_DPFP_RATE__VI(gc_user_shader_rate_config_reg, dpfp_rate) \ - gc_user_shader_rate_config_reg = \ - (gc_user_shader_rate_config_reg & ~GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_MASK) | \ - (dpfp_rate << GC_USER_SHADER_RATE_CONFIG_DPFP_RATE_SHIFT) - -#define GC_USER_SHADER_RATE_CONFIG_SET_HALF_LDS__VI(gc_user_shader_rate_config_reg, half_lds) \ - gc_user_shader_rate_config_reg = \ - (gc_user_shader_rate_config_reg & ~GC_USER_SHADER_RATE_CONFIG_HALF_LDS_MASK) | \ - (half_lds << GC_USER_SHADER_RATE_CONFIG_HALF_LDS_SHIFT) - -#define GC_USER_SHADER_RATE_CONFIG_SET_SQC_BALANCE_DISABLE__VI(gc_user_shader_rate_config_reg, \ - sqc_balance_disable) \ - gc_user_shader_rate_config_reg = \ - (gc_user_shader_rate_config_reg & ~GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK) | \ - (sqc_balance_disable << GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SHIFT) - -#define GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_MASK__VI 0x00000008 -#define GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SHIFT__VI 3 -#define GC_USER_SHADER_RATE_CONFIG_SQC_BALANCE_DISABLE_SIZE__VI 1 -#define INST_ID_PRIV_START__VI 0x80000000 -#define INST_ID_SPI_WREXEC__VI 0xfffffff4 -#define SH_MEM_APE1_BASE_GET_BASE__VI(sh_mem_ape1_base) \ - ((sh_mem_ape1_base & SH_MEM_APE1_BASE_BASE_MASK) >> SH_MEM_APE1_BASE_BASE_SHIFT) - -#define SH_MEM_APE1_BASE_MASK__VI (SH_MEM_APE1_BASE_BASE_MASK) - -#define SH_MEM_APE1_BASE_SET_BASE__VI(sh_mem_ape1_base_reg, base) \ - sh_mem_ape1_base_reg = \ - (sh_mem_ape1_base_reg & ~SH_MEM_APE1_BASE_BASE_MASK) | (base << SH_MEM_APE1_BASE_BASE_SHIFT) - -#define SH_MEM_APE1_LIMIT_GET_LIMIT__VI(sh_mem_ape1_limit) \ - ((sh_mem_ape1_limit & SH_MEM_APE1_LIMIT_LIMIT_MASK) >> SH_MEM_APE1_LIMIT_LIMIT_SHIFT) - -#define SH_MEM_APE1_LIMIT_MASK__VI (SH_MEM_APE1_LIMIT_LIMIT_MASK) - -#define SH_MEM_APE1_LIMIT_SET_LIMIT__VI(sh_mem_ape1_limit_reg, limit) \ - sh_mem_ape1_limit_reg = (sh_mem_ape1_limit_reg & ~SH_MEM_APE1_LIMIT_LIMIT_MASK) | \ - (limit << SH_MEM_APE1_LIMIT_LIMIT_SHIFT) - -#define SH_MEM_BASES_GET_PRIVATE_BASE__VI(sh_mem_bases) \ - ((sh_mem_bases & SH_MEM_BASES_PRIVATE_BASE_MASK) >> SH_MEM_BASES_PRIVATE_BASE_SHIFT) - -#define SH_MEM_BASES_GET_SHARED_BASE__VI(sh_mem_bases) \ - ((sh_mem_bases & SH_MEM_BASES_SHARED_BASE_MASK) >> SH_MEM_BASES_SHARED_BASE_SHIFT) - -#define SH_MEM_BASES_MASK__VI (SH_MEM_BASES_PRIVATE_BASE_MASK | SH_MEM_BASES_SHARED_BASE_MASK) - -#define SH_MEM_BASES_SET_PRIVATE_BASE__VI(sh_mem_bases_reg, private_base) \ - sh_mem_bases_reg = (sh_mem_bases_reg & ~SH_MEM_BASES_PRIVATE_BASE_MASK) | \ - (private_base << SH_MEM_BASES_PRIVATE_BASE_SHIFT) - -#define SH_MEM_BASES_SET_SHARED_BASE__VI(sh_mem_bases_reg, shared_base) \ - sh_mem_bases_reg = (sh_mem_bases_reg & ~SH_MEM_BASES_SHARED_BASE_MASK) | \ - (shared_base << SH_MEM_BASES_SHARED_BASE_SHIFT) - -#define SH_MEM_CONFIG_ADDRESS_MODE_MASK__VI 0x00000003 -#define SH_MEM_CONFIG_ADDRESS_MODE_SHIFT__VI 0x00000000 -#define SH_MEM_CONFIG_ADDRESS_MODE_SIZE__VI 2 -#define SH_MEM_CONFIG_ALIGNMENT_MODE_MASK__VI 0x00000018 -#define SH_MEM_CONFIG_ALIGNMENT_MODE_SHIFT__VI 3 -#define SH_MEM_CONFIG_APE1_ATC_MASK__VI 0x00000800 -#define SH_MEM_CONFIG_APE1_ATC_SHIFT__VI 11 -#define SH_MEM_CONFIG_APE1_ATC_SIZE__VI 1 -#define SH_MEM_CONFIG_APE1_MTYPE_MASK__VI 0x00000700 -#define SH_MEM_CONFIG_APE1_MTYPE_SHIFT__VI 8 -#define SH_MEM_CONFIG_DEFAULT_MTYPE_MASK__VI 0x000000e0 -#define SH_MEM_CONFIG_DEFAULT_MTYPE_SHIFT__VI 5 -#define SH_MEM_CONFIG_GET_ADDRESS_MODE__VI(sh_mem_config) \ - ((sh_mem_config & SH_MEM_CONFIG_ADDRESS_MODE_MASK) >> SH_MEM_CONFIG_ADDRESS_MODE_SHIFT) - -#define SH_MEM_CONFIG_GET_ALIGNMENT_MODE__VI(sh_mem_config) \ - ((sh_mem_config & SH_MEM_CONFIG_ALIGNMENT_MODE_MASK) >> SH_MEM_CONFIG_ALIGNMENT_MODE_SHIFT) - -#define SH_MEM_CONFIG_GET_APE1_ATC__VI(sh_mem_config) \ - ((sh_mem_config & SH_MEM_CONFIG_APE1_ATC_MASK) >> SH_MEM_CONFIG_APE1_ATC_SHIFT) - -#define SH_MEM_CONFIG_GET_APE1_MTYPE__VI(sh_mem_config) \ - ((sh_mem_config & SH_MEM_CONFIG_APE1_MTYPE_MASK) >> SH_MEM_CONFIG_APE1_MTYPE_SHIFT) - -#define SH_MEM_CONFIG_GET_DEFAULT_MTYPE__VI(sh_mem_config) \ - ((sh_mem_config & SH_MEM_CONFIG_DEFAULT_MTYPE_MASK) >> SH_MEM_CONFIG_DEFAULT_MTYPE_SHIFT) - -#define SH_MEM_CONFIG_GET_PRIVATE_ATC__VI(sh_mem_config) \ - ((sh_mem_config & SH_MEM_CONFIG_PRIVATE_ATC_MASK) >> SH_MEM_CONFIG_PRIVATE_ATC_SHIFT) - -#define SH_MEM_CONFIG_MASK__VI \ - (SH_MEM_CONFIG_ADDRESS_MODE_MASK | SH_MEM_CONFIG_PRIVATE_ATC_MASK | \ - SH_MEM_CONFIG_ALIGNMENT_MODE_MASK | SH_MEM_CONFIG_DEFAULT_MTYPE_MASK | \ - SH_MEM_CONFIG_APE1_MTYPE_MASK | SH_MEM_CONFIG_APE1_ATC_MASK) - -#define SH_MEM_CONFIG_PRIVATE_ATC_MASK__VI 0x00000004 -#define SH_MEM_CONFIG_PRIVATE_ATC_SHIFT__VI 2 -#define SH_MEM_CONFIG_SET_ADDRESS_MODE__VI(sh_mem_config_reg, address_mode) \ - sh_mem_config_reg = (sh_mem_config_reg & ~SH_MEM_CONFIG_ADDRESS_MODE_MASK) | \ - (address_mode << SH_MEM_CONFIG_ADDRESS_MODE_SHIFT) - -#define SH_MEM_CONFIG_SET_ALIGNMENT_MODE__VI(sh_mem_config_reg, alignment_mode) \ - sh_mem_config_reg = (sh_mem_config_reg & ~SH_MEM_CONFIG_ALIGNMENT_MODE_MASK) | \ - (alignment_mode << SH_MEM_CONFIG_ALIGNMENT_MODE_SHIFT) - -#define SH_MEM_CONFIG_SET_APE1_ATC__VI(sh_mem_config_reg, ape1_atc) \ - sh_mem_config_reg = (sh_mem_config_reg & ~SH_MEM_CONFIG_APE1_ATC_MASK) | \ - (ape1_atc << SH_MEM_CONFIG_APE1_ATC_SHIFT) - -#define SH_MEM_CONFIG_SET_APE1_MTYPE__VI(sh_mem_config_reg, ape1_mtype) \ - sh_mem_config_reg = (sh_mem_config_reg & ~SH_MEM_CONFIG_APE1_MTYPE_MASK) | \ - (ape1_mtype << SH_MEM_CONFIG_APE1_MTYPE_SHIFT) - -#define SH_MEM_CONFIG_SET_DEFAULT_MTYPE__VI(sh_mem_config_reg, default_mtype) \ - sh_mem_config_reg = (sh_mem_config_reg & ~SH_MEM_CONFIG_DEFAULT_MTYPE_MASK) | \ - (default_mtype << SH_MEM_CONFIG_DEFAULT_MTYPE_SHIFT) - -#define SH_MEM_CONFIG_SET_PRIVATE_ATC__VI(sh_mem_config_reg, private_atc) \ - sh_mem_config_reg = (sh_mem_config_reg & ~SH_MEM_CONFIG_PRIVATE_ATC_MASK) | \ - (private_atc << SH_MEM_CONFIG_PRIVATE_ATC_SHIFT) - -#define SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_MASK__VI 0x00ff0000 -#define SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_SHIFT__VI 16 -#define SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_SIZE__VI 8 -#define SQC_ATC_EDC_GATCL1_CNT_DEFAULT__VI 0x00000000 -#define SQC_ATC_EDC_GATCL1_CNT_GET_DCACHE_DATA_SEC__VI(sqc_atc_edc_gatcl1_cnt) \ - ((sqc_atc_edc_gatcl1_cnt & SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_MASK) >> \ - SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_SHIFT) - -#define SQC_ATC_EDC_GATCL1_CNT_GET_ICACHE_DATA_SEC__VI(sqc_atc_edc_gatcl1_cnt) \ - ((sqc_atc_edc_gatcl1_cnt & SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_MASK) >> \ - SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_SHIFT) - -#define SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_MASK__VI 0x000000ff -#define SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_SHIFT__VI 0x00000000 -#define SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_SIZE__VI 8 -#define SQC_ATC_EDC_GATCL1_CNT_MASK__VI \ - (SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_MASK | SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_MASK) - -#define SQC_ATC_EDC_GATCL1_CNT_REG_SIZE__VI 32 -#define SQC_ATC_EDC_GATCL1_CNT_SET_DCACHE_DATA_SEC__VI(sqc_atc_edc_gatcl1_cnt_reg, \ - dcache_data_sec) \ - sqc_atc_edc_gatcl1_cnt_reg = \ - (sqc_atc_edc_gatcl1_cnt_reg & ~SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_MASK) | \ - (dcache_data_sec << SQC_ATC_EDC_GATCL1_CNT_DCACHE_DATA_SEC_SHIFT) - -#define SQC_ATC_EDC_GATCL1_CNT_SET_ICACHE_DATA_SEC__VI(sqc_atc_edc_gatcl1_cnt_reg, \ - icache_data_sec) \ - sqc_atc_edc_gatcl1_cnt_reg = \ - (sqc_atc_edc_gatcl1_cnt_reg & ~SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_MASK) | \ - (icache_data_sec << SQC_ATC_EDC_GATCL1_CNT_ICACHE_DATA_SEC_SHIFT) - -#define SQC_CACHES_COMPLETE_MASK__VI 0x00010000 -#define SQC_CACHES_COMPLETE_SHIFT__VI 16 -#define SQC_CACHES_COMPLETE_SIZE__VI 1 -#define SQC_CACHES_GET_COMPLETE__VI(sqc_caches) \ - ((sqc_caches & SQC_CACHES_COMPLETE_MASK) >> SQC_CACHES_COMPLETE_SHIFT) - -#define SQC_CACHES_GET_INVALIDATE__VI(sqc_caches) \ - ((sqc_caches & SQC_CACHES_INVALIDATE_MASK) >> SQC_CACHES_INVALIDATE_SHIFT) - -#define SQC_CACHES_GET_TARGET_DATA__VI(sqc_caches) \ - ((sqc_caches & SQC_CACHES_TARGET_DATA_MASK) >> SQC_CACHES_TARGET_DATA_SHIFT) - -#define SQC_CACHES_GET_TARGET_INST__VI(sqc_caches) \ - ((sqc_caches & SQC_CACHES_TARGET_INST_MASK) >> SQC_CACHES_TARGET_INST_SHIFT) - -#define SQC_CACHES_GET_VOL__VI(sqc_caches) \ - ((sqc_caches & SQC_CACHES_VOL_MASK) >> SQC_CACHES_VOL_SHIFT) - -#define SQC_CACHES_GET_WRITEBACK__VI(sqc_caches) \ - ((sqc_caches & SQC_CACHES_WRITEBACK_MASK) >> SQC_CACHES_WRITEBACK_SHIFT) - -#define SQC_CACHES_INVALIDATE_MASK__VI 0x00000004 -#define SQC_CACHES_INVALIDATE_SHIFT__VI 2 -#define SQC_CACHES_INVALIDATE_SIZE__VI 1 -#define SQC_CACHES_MASK__VI \ - (SQC_CACHES_TARGET_INST_MASK | SQC_CACHES_TARGET_DATA_MASK | SQC_CACHES_INVALIDATE_MASK | \ - SQC_CACHES_WRITEBACK_MASK | SQC_CACHES_VOL_MASK | SQC_CACHES_COMPLETE_MASK) - -#define SQC_CACHES_SET_COMPLETE__VI(sqc_caches_reg, complete) \ - sqc_caches_reg = \ - (sqc_caches_reg & ~SQC_CACHES_COMPLETE_MASK) | (complete << SQC_CACHES_COMPLETE_SHIFT) - -#define SQC_CACHES_SET_INVALIDATE__VI(sqc_caches_reg, invalidate) \ - sqc_caches_reg = \ - (sqc_caches_reg & ~SQC_CACHES_INVALIDATE_MASK) | (invalidate << SQC_CACHES_INVALIDATE_SHIFT) - -#define SQC_CACHES_SET_TARGET_DATA__VI(sqc_caches_reg, target_data) \ - sqc_caches_reg = (sqc_caches_reg & ~SQC_CACHES_TARGET_DATA_MASK) | \ - (target_data << SQC_CACHES_TARGET_DATA_SHIFT) - -#define SQC_CACHES_SET_TARGET_INST__VI(sqc_caches_reg, target_inst) \ - sqc_caches_reg = (sqc_caches_reg & ~SQC_CACHES_TARGET_INST_MASK) | \ - (target_inst << SQC_CACHES_TARGET_INST_SHIFT) - -#define SQC_CACHES_SET_VOL__VI(sqc_caches_reg, vol) \ - sqc_caches_reg = (sqc_caches_reg & ~SQC_CACHES_VOL_MASK) | (vol << SQC_CACHES_VOL_SHIFT) - -#define SQC_CACHES_SET_WRITEBACK__VI(sqc_caches_reg, writeback) \ - sqc_caches_reg = \ - (sqc_caches_reg & ~SQC_CACHES_WRITEBACK_MASK) | (writeback << SQC_CACHES_WRITEBACK_SHIFT) - -#define SQC_CACHES_TARGET_DATA_MASK__VI 0x00000002 -#define SQC_CACHES_TARGET_DATA_SHIFT__VI 1 -#define SQC_CACHES_TARGET_DATA_SIZE__VI 1 -#define SQC_CACHES_TARGET_INST_MASK__VI 0x00000001 -#define SQC_CACHES_TARGET_INST_SHIFT__VI 0x00000000 -#define SQC_CACHES_TARGET_INST_SIZE__VI 1 -#define SQC_CACHES_VOL_MASK__VI 0x00000010 -#define SQC_CACHES_VOL_SHIFT__VI 4 -#define SQC_CACHES_VOL_SIZE__VI 1 -#define SQC_CACHES_WRITEBACK_MASK__VI 0x00000008 -#define SQC_CACHES_WRITEBACK_SHIFT__VI 3 -#define SQC_CACHES_WRITEBACK_SIZE__VI 1 -#define SQC_CONFIG_DEFAULT__SI__CI 0x00000000 -#define SQC_CONFIG_DEFAULT__VI 0x000a2000 -#define SQC_CONFIG_EVICT_LRU_MASK__VI 0x00003000 -#define SQC_CONFIG_EVICT_LRU_SHIFT__VI 12 -#define SQC_CONFIG_EVICT_LRU_SIZE__VI 2 -#define SQC_CONFIG_FORCE_1_BANK_MASK__VI 0x00008000 -#define SQC_CONFIG_FORCE_1_BANK_SHIFT__VI 15 -#define SQC_CONFIG_FORCE_1_BANK_SIZE__VI 1 -#define SQC_CONFIG_FORCE_2_BANK_MASK__VI 0x00004000 -#define SQC_CONFIG_FORCE_2_BANK_SHIFT__VI 14 -#define SQC_CONFIG_FORCE_2_BANK_SIZE__VI 1 -#define SQC_CONFIG_GET_DATA_CACHE_SIZE__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_DATA_CACHE_SIZE_MASK) >> SQC_CONFIG_DATA_CACHE_SIZE_SHIFT) - -#define SQC_CONFIG_GET_EVICT_LRU__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_EVICT_LRU_MASK) >> SQC_CONFIG_EVICT_LRU_SHIFT) - -#define SQC_CONFIG_GET_FORCE_1_BANK__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_FORCE_1_BANK_MASK) >> SQC_CONFIG_FORCE_1_BANK_SHIFT) - -#define SQC_CONFIG_GET_FORCE_2_BANK__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_FORCE_2_BANK_MASK) >> SQC_CONFIG_FORCE_2_BANK_SHIFT) - -#define SQC_CONFIG_GET_FORCE_ALWAYS_MISS__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_FORCE_ALWAYS_MISS_MASK) >> SQC_CONFIG_FORCE_ALWAYS_MISS_SHIFT) - -#define SQC_CONFIG_GET_FORCE_IN_ORDER__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_FORCE_IN_ORDER_MASK) >> SQC_CONFIG_FORCE_IN_ORDER_SHIFT) - -#define SQC_CONFIG_GET_HIT_FIFO_DEPTH__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_HIT_FIFO_DEPTH_MASK) >> SQC_CONFIG_HIT_FIFO_DEPTH_SHIFT) - -#define SQC_CONFIG_GET_IDENTITY_HASH_BANK__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_IDENTITY_HASH_BANK_MASK) >> SQC_CONFIG_IDENTITY_HASH_BANK_SHIFT) - -#define SQC_CONFIG_GET_IDENTITY_HASH_SET__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_IDENTITY_HASH_SET_MASK) >> SQC_CONFIG_IDENTITY_HASH_SET_SHIFT) - -#define SQC_CONFIG_GET_INST_CACHE_SIZE__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_INST_CACHE_SIZE_MASK) >> SQC_CONFIG_INST_CACHE_SIZE_SHIFT) - -#define SQC_CONFIG_GET_LS_DISABLE_CLOCKS__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_LS_DISABLE_CLOCKS_MASK) >> SQC_CONFIG_LS_DISABLE_CLOCKS_SHIFT) - -#define SQC_CONFIG_GET_MISS_FIFO_DEPTH__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_MISS_FIFO_DEPTH_MASK) >> SQC_CONFIG_MISS_FIFO_DEPTH_SHIFT) - -#define SQC_CONFIG_GET_PER_VMID_INV_DISABLE__VI(sqc_config) \ - ((sqc_config & SQC_CONFIG_PER_VMID_INV_DISABLE_MASK) >> SQC_CONFIG_PER_VMID_INV_DISABLE_SHIFT) - -#define SQC_CONFIG_LS_DISABLE_CLOCKS_MASK__VI 0x00ff0000 -#define SQC_CONFIG_LS_DISABLE_CLOCKS_SHIFT__VI 16 -#define SQC_CONFIG_LS_DISABLE_CLOCKS_SIZE__VI 8 -#define SQC_CONFIG_MASK__VI \ - (SQC_CONFIG_INST_CACHE_SIZE_MASK | SQC_CONFIG_DATA_CACHE_SIZE_MASK | \ - SQC_CONFIG_MISS_FIFO_DEPTH_MASK | SQC_CONFIG_HIT_FIFO_DEPTH_MASK | \ - SQC_CONFIG_FORCE_ALWAYS_MISS_MASK | SQC_CONFIG_FORCE_IN_ORDER_MASK | \ - SQC_CONFIG_IDENTITY_HASH_BANK_MASK | SQC_CONFIG_IDENTITY_HASH_SET_MASK | \ - SQC_CONFIG_PER_VMID_INV_DISABLE_MASK | SQC_CONFIG_EVICT_LRU_MASK | \ - SQC_CONFIG_FORCE_2_BANK_MASK | SQC_CONFIG_FORCE_1_BANK_MASK | \ - SQC_CONFIG_LS_DISABLE_CLOCKS_MASK) - -#define SQC_CONFIG_SET_DATA_CACHE_SIZE__VI(sqc_config_reg, data_cache_size) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_DATA_CACHE_SIZE_MASK) | \ - (data_cache_size << SQC_CONFIG_DATA_CACHE_SIZE_SHIFT) - -#define SQC_CONFIG_SET_EVICT_LRU__VI(sqc_config_reg, evict_lru) \ - sqc_config_reg = \ - (sqc_config_reg & ~SQC_CONFIG_EVICT_LRU_MASK) | (evict_lru << SQC_CONFIG_EVICT_LRU_SHIFT) - -#define SQC_CONFIG_SET_FORCE_1_BANK__VI(sqc_config_reg, force_1_bank) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_FORCE_1_BANK_MASK) | \ - (force_1_bank << SQC_CONFIG_FORCE_1_BANK_SHIFT) - -#define SQC_CONFIG_SET_FORCE_2_BANK__VI(sqc_config_reg, force_2_bank) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_FORCE_2_BANK_MASK) | \ - (force_2_bank << SQC_CONFIG_FORCE_2_BANK_SHIFT) - -#define SQC_CONFIG_SET_FORCE_ALWAYS_MISS__VI(sqc_config_reg, force_always_miss) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_FORCE_ALWAYS_MISS_MASK) | \ - (force_always_miss << SQC_CONFIG_FORCE_ALWAYS_MISS_SHIFT) - -#define SQC_CONFIG_SET_FORCE_IN_ORDER__VI(sqc_config_reg, force_in_order) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_FORCE_IN_ORDER_MASK) | \ - (force_in_order << SQC_CONFIG_FORCE_IN_ORDER_SHIFT) - -#define SQC_CONFIG_SET_HIT_FIFO_DEPTH__VI(sqc_config_reg, hit_fifo_depth) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_HIT_FIFO_DEPTH_MASK) | \ - (hit_fifo_depth << SQC_CONFIG_HIT_FIFO_DEPTH_SHIFT) - -#define SQC_CONFIG_SET_IDENTITY_HASH_BANK__VI(sqc_config_reg, identity_hash_bank) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_IDENTITY_HASH_BANK_MASK) | \ - (identity_hash_bank << SQC_CONFIG_IDENTITY_HASH_BANK_SHIFT) - -#define SQC_CONFIG_SET_IDENTITY_HASH_SET__VI(sqc_config_reg, identity_hash_set) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_IDENTITY_HASH_SET_MASK) | \ - (identity_hash_set << SQC_CONFIG_IDENTITY_HASH_SET_SHIFT) - -#define SQC_CONFIG_SET_INST_CACHE_SIZE__VI(sqc_config_reg, inst_cache_size) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_INST_CACHE_SIZE_MASK) | \ - (inst_cache_size << SQC_CONFIG_INST_CACHE_SIZE_SHIFT) - -#define SQC_CONFIG_SET_LS_DISABLE_CLOCKS__VI(sqc_config_reg, ls_disable_clocks) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_LS_DISABLE_CLOCKS_MASK) | \ - (ls_disable_clocks << SQC_CONFIG_LS_DISABLE_CLOCKS_SHIFT) - -#define SQC_CONFIG_SET_MISS_FIFO_DEPTH__VI(sqc_config_reg, miss_fifo_depth) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_MISS_FIFO_DEPTH_MASK) | \ - (miss_fifo_depth << SQC_CONFIG_MISS_FIFO_DEPTH_SHIFT) - -#define SQC_CONFIG_SET_PER_VMID_INV_DISABLE__VI(sqc_config_reg, per_vmid_inv_disable) \ - sqc_config_reg = (sqc_config_reg & ~SQC_CONFIG_PER_VMID_INV_DISABLE_MASK) | \ - (per_vmid_inv_disable << SQC_CONFIG_PER_VMID_INV_DISABLE_SHIFT) - -#define SQC_DSM_CNTL_DEFAULT__VI 0x00000000 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_MASK__VI 0x00020000 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_SHIFT__VI 17 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_MASK__VI 0x00100000 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_SHIFT__VI 20 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_MASK__VI 0x00800000 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_SHIFT__VI 23 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_MASK__VI 0x04000000 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_SHIFT__VI 26 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_MASK__VI 0x20000000 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_SHIFT__VI 29 -#define SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_MASK__VI 0x00000004 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_SHIFT__VI 2 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_MASK__VI 0x00000020 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_SHIFT__VI 5 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_MASK__VI 0x00000100 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_SHIFT__VI 8 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_MASK__VI 0x00000800 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_SHIFT__VI 11 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_SIZE__VI 1 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_MASK__VI 0x00004000 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_SHIFT__VI 14 -#define SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_SIZE__VI 1 -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_DCACHE_BANKA__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_DCACHE_BANKB__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_DCACHE_BANKC__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_DCACHE_BANKD__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_DCACHE_GATCL1__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_ICACHE_BANKA__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_ICACHE_BANKB__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_ICACHE_BANKC__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_ICACHE_BANKD__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_GET_EN_SINGLE_WR_ICACHE_GATCL1__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_MASK) >> \ - SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_DCACHE_BANKA__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_DCACHE_BANKB__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_DCACHE_BANKC__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_DCACHE_BANKD__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_DCACHE_GATCL1__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_ICACHE_BANKA__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_ICACHE_BANKB__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_ICACHE_BANKC__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_ICACHE_BANKD__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_GET_SEL_DATA_ICACHE_GATCL1__VI(sqc_dsm_cntl) \ - ((sqc_dsm_cntl & SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_MASK) >> \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_SHIFT) - -#define SQC_DSM_CNTL_MASK__VI \ - (SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_MASK | \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_MASK | \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_MASK | \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_MASK | \ - SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_MASK | \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_MASK | \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_MASK | \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_MASK | \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_MASK | \ - SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_MASK | SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_MASK) - -#define SQC_DSM_CNTL_REG_SIZE__VI 32 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_MASK__VI 0x00018000 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_SHIFT__VI 15 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_MASK__VI 0x000c0000 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_SHIFT__VI 18 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_MASK__VI 0x00600000 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_SHIFT__VI 21 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_MASK__VI 0x03000000 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_SHIFT__VI 24 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_MASK__VI 0x18000000 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_SHIFT__VI 27 -#define SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_MASK__VI 0x00000003 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_SHIFT__VI 0x00000000 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_MASK__VI 0x00000018 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_SHIFT__VI 3 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_MASK__VI 0x000000c0 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_SHIFT__VI 6 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_MASK__VI 0x00000600 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_SHIFT__VI 9 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_SIZE__VI 2 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_MASK__VI 0x00003000 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_SHIFT__VI 12 -#define SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_SIZE__VI 2 -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_DCACHE_BANKA__VI(sqc_dsm_cntl_reg, \ - en_single_wr_dcache_banka) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_MASK) | \ - (en_single_wr_dcache_banka << SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_DCACHE_BANKB__VI(sqc_dsm_cntl_reg, \ - en_single_wr_dcache_bankb) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_MASK) | \ - (en_single_wr_dcache_bankb << SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_DCACHE_BANKC__VI(sqc_dsm_cntl_reg, \ - en_single_wr_dcache_bankc) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_MASK) | \ - (en_single_wr_dcache_bankc << SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_DCACHE_BANKD__VI(sqc_dsm_cntl_reg, \ - en_single_wr_dcache_bankd) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_MASK) | \ - (en_single_wr_dcache_bankd << SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_DCACHE_GATCL1__VI(sqc_dsm_cntl_reg, \ - en_single_wr_dcache_gatcl1) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_MASK) | \ - (en_single_wr_dcache_gatcl1 << SQC_DSM_CNTL_EN_SINGLE_WR_DCACHE_GATCL1_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_ICACHE_BANKA__VI(sqc_dsm_cntl_reg, \ - en_single_wr_icache_banka) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_MASK) | \ - (en_single_wr_icache_banka << SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_ICACHE_BANKB__VI(sqc_dsm_cntl_reg, \ - en_single_wr_icache_bankb) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_MASK) | \ - (en_single_wr_icache_bankb << SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_ICACHE_BANKC__VI(sqc_dsm_cntl_reg, \ - en_single_wr_icache_bankc) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_MASK) | \ - (en_single_wr_icache_bankc << SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_ICACHE_BANKD__VI(sqc_dsm_cntl_reg, \ - en_single_wr_icache_bankd) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_MASK) | \ - (en_single_wr_icache_bankd << SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_SET_EN_SINGLE_WR_ICACHE_GATCL1__VI(sqc_dsm_cntl_reg, \ - en_single_wr_icache_gatcl1) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_MASK) | \ - (en_single_wr_icache_gatcl1 << SQC_DSM_CNTL_EN_SINGLE_WR_ICACHE_GATCL1_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_DCACHE_BANKA__VI(sqc_dsm_cntl_reg, sel_data_dcache_banka) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_MASK) | \ - (sel_data_dcache_banka << SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_DCACHE_BANKB__VI(sqc_dsm_cntl_reg, sel_data_dcache_bankb) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_MASK) | \ - (sel_data_dcache_bankb << SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_DCACHE_BANKC__VI(sqc_dsm_cntl_reg, sel_data_dcache_bankc) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_MASK) | \ - (sel_data_dcache_bankc << SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_DCACHE_BANKD__VI(sqc_dsm_cntl_reg, sel_data_dcache_bankd) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_MASK) | \ - (sel_data_dcache_bankd << SQC_DSM_CNTL_SEL_DATA_DCACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_DCACHE_GATCL1__VI(sqc_dsm_cntl_reg, sel_data_dcache_gatcl1) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_MASK) | \ - (sel_data_dcache_gatcl1 << SQC_DSM_CNTL_SEL_DATA_DCACHE_GATCL1_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_ICACHE_BANKA__VI(sqc_dsm_cntl_reg, sel_data_icache_banka) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_MASK) | \ - (sel_data_icache_banka << SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKA_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_ICACHE_BANKB__VI(sqc_dsm_cntl_reg, sel_data_icache_bankb) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_MASK) | \ - (sel_data_icache_bankb << SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKB_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_ICACHE_BANKC__VI(sqc_dsm_cntl_reg, sel_data_icache_bankc) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_MASK) | \ - (sel_data_icache_bankc << SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKC_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_ICACHE_BANKD__VI(sqc_dsm_cntl_reg, sel_data_icache_bankd) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_MASK) | \ - (sel_data_icache_bankd << SQC_DSM_CNTL_SEL_DATA_ICACHE_BANKD_SHIFT) - -#define SQC_DSM_CNTL_SET_SEL_DATA_ICACHE_GATCL1__VI(sqc_dsm_cntl_reg, sel_data_icache_gatcl1) \ - sqc_dsm_cntl_reg = (sqc_dsm_cntl_reg & ~SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_MASK) | \ - (sel_data_icache_gatcl1 << SQC_DSM_CNTL_SEL_DATA_ICACHE_GATCL1_SHIFT) - -#define SQC_EDC_CNT_DATA_DED_MASK__VI 0xff000000 -#define SQC_EDC_CNT_DATA_DED_SHIFT__VI 24 -#define SQC_EDC_CNT_DATA_DED_SIZE__VI 8 -#define SQC_EDC_CNT_DATA_SEC_MASK__VI 0x00ff0000 -#define SQC_EDC_CNT_DATA_SEC_SHIFT__VI 16 -#define SQC_EDC_CNT_DATA_SEC_SIZE__VI 8 -#define SQC_EDC_CNT_DEFAULT__VI 0x00000000 -#define SQC_EDC_CNT_GET_DATA_DED__VI(sqc_edc_cnt) \ - ((sqc_edc_cnt & SQC_EDC_CNT_DATA_DED_MASK) >> SQC_EDC_CNT_DATA_DED_SHIFT) - -#define SQC_EDC_CNT_GET_DATA_SEC__VI(sqc_edc_cnt) \ - ((sqc_edc_cnt & SQC_EDC_CNT_DATA_SEC_MASK) >> SQC_EDC_CNT_DATA_SEC_SHIFT) - -#define SQC_EDC_CNT_GET_INST_DED__VI(sqc_edc_cnt) \ - ((sqc_edc_cnt & SQC_EDC_CNT_INST_DED_MASK) >> SQC_EDC_CNT_INST_DED_SHIFT) - -#define SQC_EDC_CNT_GET_INST_SEC__VI(sqc_edc_cnt) \ - ((sqc_edc_cnt & SQC_EDC_CNT_INST_SEC_MASK) >> SQC_EDC_CNT_INST_SEC_SHIFT) - -#define SQC_EDC_CNT_INST_DED_MASK__VI 0x0000ff00 -#define SQC_EDC_CNT_INST_DED_SHIFT__VI 8 -#define SQC_EDC_CNT_INST_DED_SIZE__VI 8 -#define SQC_EDC_CNT_INST_SEC_MASK__VI 0x000000ff -#define SQC_EDC_CNT_INST_SEC_SHIFT__VI 0x00000000 -#define SQC_EDC_CNT_INST_SEC_SIZE__VI 8 -#define SQC_EDC_CNT_MASK__VI \ - (SQC_EDC_CNT_INST_SEC_MASK | SQC_EDC_CNT_INST_DED_MASK | SQC_EDC_CNT_DATA_SEC_MASK | \ - SQC_EDC_CNT_DATA_DED_MASK) - -#define SQC_EDC_CNT_REG_SIZE__VI 32 -#define SQC_EDC_CNT_SET_DATA_DED__VI(sqc_edc_cnt_reg, data_ded) \ - sqc_edc_cnt_reg = \ - (sqc_edc_cnt_reg & ~SQC_EDC_CNT_DATA_DED_MASK) | (data_ded << SQC_EDC_CNT_DATA_DED_SHIFT) - -#define SQC_EDC_CNT_SET_DATA_SEC__VI(sqc_edc_cnt_reg, data_sec) \ - sqc_edc_cnt_reg = \ - (sqc_edc_cnt_reg & ~SQC_EDC_CNT_DATA_SEC_MASK) | (data_sec << SQC_EDC_CNT_DATA_SEC_SHIFT) - -#define SQC_EDC_CNT_SET_INST_DED__VI(sqc_edc_cnt_reg, inst_ded) \ - sqc_edc_cnt_reg = \ - (sqc_edc_cnt_reg & ~SQC_EDC_CNT_INST_DED_MASK) | (inst_ded << SQC_EDC_CNT_INST_DED_SHIFT) - -#define SQC_EDC_CNT_SET_INST_SEC__VI(sqc_edc_cnt_reg, inst_sec) \ - sqc_edc_cnt_reg = \ - (sqc_edc_cnt_reg & ~SQC_EDC_CNT_INST_SEC_MASK) | (inst_sec << SQC_EDC_CNT_INST_SEC_SHIFT) - -#define SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_MASK__VI 0x00100000 -#define SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_SHIFT__VI 20 -#define SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_SIZE__VI 1 -#define SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_MASK__VI 0x00080000 -#define SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_SHIFT__VI 19 -#define SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_SIZE__VI 1 -#define SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_MASK__VI 0x00040000 -#define SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_SHIFT__VI 18 -#define SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_SIZE__VI 1 -#define SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK__VI 0x01800000 -#define SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_SHIFT__VI 23 -#define SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_SIZE__VI 2 -#define SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK__VI 0x00600000 -#define SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_SHIFT__VI 21 -#define SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_SIZE__VI 2 -#define SQC_GATCL1_CNTL_DEFAULT__VI 0x00000000 -#define SQC_GATCL1_CNTL_GET_DCACHE_FORCE_IN_ORDER__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_MASK) >> \ - SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_SHIFT) - -#define SQC_GATCL1_CNTL_GET_DCACHE_FORCE_MISS__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_MASK) >> \ - SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_SHIFT) - -#define SQC_GATCL1_CNTL_GET_DCACHE_INVALIDATE_ALL_VMID__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_MASK) >> \ - SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_SHIFT) - -#define SQC_GATCL1_CNTL_GET_DCACHE_REDUCE_CACHE_SIZE_BY_2__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK) >> \ - SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_GET_DCACHE_REDUCE_FIFO_DEPTH_BY_2__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK) >> \ - SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_GET_ICACHE_FORCE_IN_ORDER__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_MASK) >> \ - SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_SHIFT) - -#define SQC_GATCL1_CNTL_GET_ICACHE_FORCE_MISS__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_MASK) >> \ - SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_SHIFT) - -#define SQC_GATCL1_CNTL_GET_ICACHE_INVALIDATE_ALL_VMID__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_MASK) >> \ - SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_SHIFT) - -#define SQC_GATCL1_CNTL_GET_ICACHE_REDUCE_CACHE_SIZE_BY_2__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK) >> \ - SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_GET_ICACHE_REDUCE_FIFO_DEPTH_BY_2__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK) >> \ - SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_GET_RESERVED__VI(sqc_gatcl1_cntl) \ - ((sqc_gatcl1_cntl & SQC_GATCL1_CNTL_RESERVED_MASK) >> SQC_GATCL1_CNTL_RESERVED_SHIFT) - -#define SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_MASK__VI 0x08000000 -#define SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_SHIFT__VI 27 -#define SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_SIZE__VI 1 -#define SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_MASK__VI 0x04000000 -#define SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_SHIFT__VI 26 -#define SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_SIZE__VI 1 -#define SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_MASK__VI 0x02000000 -#define SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_SHIFT__VI 25 -#define SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_SIZE__VI 1 -#define SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK__VI 0xc0000000 -#define SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_SHIFT__VI 30 -#define SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_SIZE__VI 2 -#define SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK__VI 0x30000000 -#define SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_SHIFT__VI 28 -#define SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_SIZE__VI 2 -#define SQC_GATCL1_CNTL_MASK__VI \ - (SQC_GATCL1_CNTL_RESERVED_MASK | SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_MASK | \ - SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_MASK | SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_MASK | \ - SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK | \ - SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK | \ - SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_MASK | SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_MASK | \ - SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_MASK | \ - SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK | \ - SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK) - -#define SQC_GATCL1_CNTL_REG_SIZE__VI 32 -#define SQC_GATCL1_CNTL_RESERVED_MASK__VI 0x0003ffff -#define SQC_GATCL1_CNTL_RESERVED_SHIFT__VI 0x00000000 -#define SQC_GATCL1_CNTL_RESERVED_SIZE__VI 18 -#define SQC_GATCL1_CNTL_SET_DCACHE_FORCE_IN_ORDER__VI(sqc_gatcl1_cntl_reg, dcache_force_in_order) \ - sqc_gatcl1_cntl_reg = (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_MASK) | \ - (dcache_force_in_order << SQC_GATCL1_CNTL_DCACHE_FORCE_IN_ORDER_SHIFT) - -#define SQC_GATCL1_CNTL_SET_DCACHE_FORCE_MISS__VI(sqc_gatcl1_cntl_reg, dcache_force_miss) \ - sqc_gatcl1_cntl_reg = (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_MASK) | \ - (dcache_force_miss << SQC_GATCL1_CNTL_DCACHE_FORCE_MISS_SHIFT) - -#define SQC_GATCL1_CNTL_SET_DCACHE_INVALIDATE_ALL_VMID__VI(sqc_gatcl1_cntl_reg, \ - dcache_invalidate_all_vmid) \ - sqc_gatcl1_cntl_reg = (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_MASK) | \ - (dcache_invalidate_all_vmid << SQC_GATCL1_CNTL_DCACHE_INVALIDATE_ALL_VMID_SHIFT) - -#define SQC_GATCL1_CNTL_SET_DCACHE_REDUCE_CACHE_SIZE_BY_2__VI(sqc_gatcl1_cntl_reg, \ - dcache_reduce_cache_size_by_2) \ - sqc_gatcl1_cntl_reg = \ - (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK) | \ - (dcache_reduce_cache_size_by_2 << SQC_GATCL1_CNTL_DCACHE_REDUCE_CACHE_SIZE_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_SET_DCACHE_REDUCE_FIFO_DEPTH_BY_2__VI(sqc_gatcl1_cntl_reg, \ - dcache_reduce_fifo_depth_by_2) \ - sqc_gatcl1_cntl_reg = \ - (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK) | \ - (dcache_reduce_fifo_depth_by_2 << SQC_GATCL1_CNTL_DCACHE_REDUCE_FIFO_DEPTH_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_SET_ICACHE_FORCE_IN_ORDER__VI(sqc_gatcl1_cntl_reg, icache_force_in_order) \ - sqc_gatcl1_cntl_reg = (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_MASK) | \ - (icache_force_in_order << SQC_GATCL1_CNTL_ICACHE_FORCE_IN_ORDER_SHIFT) - -#define SQC_GATCL1_CNTL_SET_ICACHE_FORCE_MISS__VI(sqc_gatcl1_cntl_reg, icache_force_miss) \ - sqc_gatcl1_cntl_reg = (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_MASK) | \ - (icache_force_miss << SQC_GATCL1_CNTL_ICACHE_FORCE_MISS_SHIFT) - -#define SQC_GATCL1_CNTL_SET_ICACHE_INVALIDATE_ALL_VMID__VI(sqc_gatcl1_cntl_reg, \ - icache_invalidate_all_vmid) \ - sqc_gatcl1_cntl_reg = (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_MASK) | \ - (icache_invalidate_all_vmid << SQC_GATCL1_CNTL_ICACHE_INVALIDATE_ALL_VMID_SHIFT) - -#define SQC_GATCL1_CNTL_SET_ICACHE_REDUCE_CACHE_SIZE_BY_2__VI(sqc_gatcl1_cntl_reg, \ - icache_reduce_cache_size_by_2) \ - sqc_gatcl1_cntl_reg = \ - (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK) | \ - (icache_reduce_cache_size_by_2 << SQC_GATCL1_CNTL_ICACHE_REDUCE_CACHE_SIZE_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_SET_ICACHE_REDUCE_FIFO_DEPTH_BY_2__VI(sqc_gatcl1_cntl_reg, \ - icache_reduce_fifo_depth_by_2) \ - sqc_gatcl1_cntl_reg = \ - (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK) | \ - (icache_reduce_fifo_depth_by_2 << SQC_GATCL1_CNTL_ICACHE_REDUCE_FIFO_DEPTH_BY_2_SHIFT) - -#define SQC_GATCL1_CNTL_SET_RESERVED__VI(sqc_gatcl1_cntl_reg, reserved) \ - sqc_gatcl1_cntl_reg = (sqc_gatcl1_cntl_reg & ~SQC_GATCL1_CNTL_RESERVED_MASK) | \ - (reserved << SQC_GATCL1_CNTL_RESERVED_SHIFT) - -#define SQC_WRITEBACK_DEFAULT__VI 0x00000000 -#define SQC_WRITEBACK_DIRTY_MASK__VI 0x00000002 -#define SQC_WRITEBACK_DIRTY_SHIFT__VI 1 -#define SQC_WRITEBACK_DIRTY_SIZE__VI 1 -#define SQC_WRITEBACK_DWB_MASK__VI 0x00000001 -#define SQC_WRITEBACK_DWB_SHIFT__VI 0x00000000 -#define SQC_WRITEBACK_DWB_SIZE__VI 1 -#define SQC_WRITEBACK_GET_DIRTY__VI(sqc_writeback) \ - ((sqc_writeback & SQC_WRITEBACK_DIRTY_MASK) >> SQC_WRITEBACK_DIRTY_SHIFT) - -#define SQC_WRITEBACK_GET_DWB__VI(sqc_writeback) \ - ((sqc_writeback & SQC_WRITEBACK_DWB_MASK) >> SQC_WRITEBACK_DWB_SHIFT) - -#define SQC_WRITEBACK_MASK__VI (SQC_WRITEBACK_DWB_MASK | SQC_WRITEBACK_DIRTY_MASK) - -#define SQC_WRITEBACK_REG_SIZE__VI 32 -#define SQC_WRITEBACK_SET_DIRTY__VI(sqc_writeback_reg, dirty) \ - sqc_writeback_reg = \ - (sqc_writeback_reg & ~SQC_WRITEBACK_DIRTY_MASK) | (dirty << SQC_WRITEBACK_DIRTY_SHIFT) - -#define SQC_WRITEBACK_SET_DWB__VI(sqc_writeback_reg, dwb) \ - sqc_writeback_reg = \ - (sqc_writeback_reg & ~SQC_WRITEBACK_DWB_MASK) | (dwb << SQC_WRITEBACK_DWB_SHIFT) - -#define SQGFXUDEC_BEGIN__VI 0x0000c330 -#define SQ_ALU_CLK_CTRL_GET_FORCE_CU_ON_SH0__VI(sq_alu_clk_ctrl) \ - ((sq_alu_clk_ctrl & SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_MASK) >> \ - SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT) - -#define SQ_ALU_CLK_CTRL_GET_FORCE_CU_ON_SH1__VI(sq_alu_clk_ctrl) \ - ((sq_alu_clk_ctrl & SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_MASK) >> \ - SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT) - -#define SQ_ALU_CLK_CTRL_MASK__VI \ - (SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_MASK | SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_MASK) - -#define SQ_ALU_CLK_CTRL_SET_FORCE_CU_ON_SH0__VI(sq_alu_clk_ctrl_reg, force_cu_on_sh0) \ - sq_alu_clk_ctrl_reg = (sq_alu_clk_ctrl_reg & ~SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_MASK) | \ - (force_cu_on_sh0 << SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT) - -#define SQ_ALU_CLK_CTRL_SET_FORCE_CU_ON_SH1__VI(sq_alu_clk_ctrl_reg, force_cu_on_sh1) \ - sq_alu_clk_ctrl_reg = (sq_alu_clk_ctrl_reg & ~SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_MASK) | \ - (force_cu_on_sh1 << SQ_ALU_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT) - -#define SQ_BUF_RSRC_WORD0_DEFAULT__SI__CI 0x00000000 -#define SQ_BUF_RSRC_WORD0_DEFAULT__VI 0xcdcdcdcd -#define SQ_BUF_RSRC_WORD0_GET_BASE_ADDRESS__VI(sq_buf_rsrc_word0) \ - ((sq_buf_rsrc_word0 & SQ_BUF_RSRC_WORD0_BASE_ADDRESS_MASK) >> \ - SQ_BUF_RSRC_WORD0_BASE_ADDRESS_SHIFT) - -#define SQ_BUF_RSRC_WORD0_MASK__VI (SQ_BUF_RSRC_WORD0_BASE_ADDRESS_MASK) - -#define SQ_BUF_RSRC_WORD0_SET_BASE_ADDRESS__VI(sq_buf_rsrc_word0_reg, base_address) \ - sq_buf_rsrc_word0_reg = (sq_buf_rsrc_word0_reg & ~SQ_BUF_RSRC_WORD0_BASE_ADDRESS_MASK) | \ - (base_address << SQ_BUF_RSRC_WORD0_BASE_ADDRESS_SHIFT) - -#define SQ_BUF_RSRC_WORD1_DEFAULT__SI__CI 0x00000000 -#define SQ_BUF_RSRC_WORD1_DEFAULT__VI 0xcdcdcdcd -#define SQ_BUF_RSRC_WORD1_GET_BASE_ADDRESS_HI__VI(sq_buf_rsrc_word1) \ - ((sq_buf_rsrc_word1 & SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_MASK) >> \ - SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_SHIFT) - -#define SQ_BUF_RSRC_WORD1_GET_CACHE_SWIZZLE__VI(sq_buf_rsrc_word1) \ - ((sq_buf_rsrc_word1 & SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_MASK) >> \ - SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_SHIFT) - -#define SQ_BUF_RSRC_WORD1_GET_STRIDE__VI(sq_buf_rsrc_word1) \ - ((sq_buf_rsrc_word1 & SQ_BUF_RSRC_WORD1_STRIDE_MASK) >> SQ_BUF_RSRC_WORD1_STRIDE_SHIFT) - -#define SQ_BUF_RSRC_WORD1_GET_SWIZZLE_ENABLE__VI(sq_buf_rsrc_word1) \ - ((sq_buf_rsrc_word1 & SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_MASK) >> \ - SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_SHIFT) - -#define SQ_BUF_RSRC_WORD1_MASK__VI \ - (SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_MASK | SQ_BUF_RSRC_WORD1_STRIDE_MASK | \ - SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_MASK | SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_MASK) - -#define SQ_BUF_RSRC_WORD1_SET_BASE_ADDRESS_HI__VI(sq_buf_rsrc_word1_reg, base_address_hi) \ - sq_buf_rsrc_word1_reg = (sq_buf_rsrc_word1_reg & ~SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_MASK) | \ - (base_address_hi << SQ_BUF_RSRC_WORD1_BASE_ADDRESS_HI_SHIFT) - -#define SQ_BUF_RSRC_WORD1_SET_CACHE_SWIZZLE__VI(sq_buf_rsrc_word1_reg, cache_swizzle) \ - sq_buf_rsrc_word1_reg = (sq_buf_rsrc_word1_reg & ~SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_MASK) | \ - (cache_swizzle << SQ_BUF_RSRC_WORD1_CACHE_SWIZZLE_SHIFT) - -#define SQ_BUF_RSRC_WORD1_SET_STRIDE__VI(sq_buf_rsrc_word1_reg, stride) \ - sq_buf_rsrc_word1_reg = (sq_buf_rsrc_word1_reg & ~SQ_BUF_RSRC_WORD1_STRIDE_MASK) | \ - (stride << SQ_BUF_RSRC_WORD1_STRIDE_SHIFT) - -#define SQ_BUF_RSRC_WORD1_SET_SWIZZLE_ENABLE__VI(sq_buf_rsrc_word1_reg, swizzle_enable) \ - sq_buf_rsrc_word1_reg = (sq_buf_rsrc_word1_reg & ~SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_MASK) | \ - (swizzle_enable << SQ_BUF_RSRC_WORD1_SWIZZLE_ENABLE_SHIFT) - -#define SQ_BUF_RSRC_WORD2_DEFAULT__SI__CI 0x00000000 -#define SQ_BUF_RSRC_WORD2_DEFAULT__VI 0xcdcdcdcd -#define SQ_BUF_RSRC_WORD2_GET_NUM_RECORDS__VI(sq_buf_rsrc_word2) \ - ((sq_buf_rsrc_word2 & SQ_BUF_RSRC_WORD2_NUM_RECORDS_MASK) >> SQ_BUF_RSRC_WORD2_NUM_RECORDS_SHIFT) - -#define SQ_BUF_RSRC_WORD2_MASK__VI (SQ_BUF_RSRC_WORD2_NUM_RECORDS_MASK) - -#define SQ_BUF_RSRC_WORD2_SET_NUM_RECORDS__VI(sq_buf_rsrc_word2_reg, num_records) \ - sq_buf_rsrc_word2_reg = (sq_buf_rsrc_word2_reg & ~SQ_BUF_RSRC_WORD2_NUM_RECORDS_MASK) | \ - (num_records << SQ_BUF_RSRC_WORD2_NUM_RECORDS_SHIFT) - -#define SQ_BUF_RSRC_WORD3_DEFAULT__SI__CI 0x00000000 -#define SQ_BUF_RSRC_WORD3_DEFAULT__VI 0xcdcdcdcd -#define SQ_BUF_RSRC_WORD3_GET_ADD_TID_ENABLE__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_MASK) >> \ - SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_ATC__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_ATC_MASK) >> SQ_BUF_RSRC_WORD3_ATC_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_DATA_FORMAT__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_DATA_FORMAT_MASK) >> SQ_BUF_RSRC_WORD3_DATA_FORMAT_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_DST_SEL_W__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_DST_SEL_W_MASK) >> SQ_BUF_RSRC_WORD3_DST_SEL_W_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_DST_SEL_X__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_DST_SEL_X_MASK) >> SQ_BUF_RSRC_WORD3_DST_SEL_X_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_DST_SEL_Y__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_DST_SEL_Y_MASK) >> SQ_BUF_RSRC_WORD3_DST_SEL_Y_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_DST_SEL_Z__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_DST_SEL_Z_MASK) >> SQ_BUF_RSRC_WORD3_DST_SEL_Z_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_ELEMENT_SIZE__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_MASK) >> \ - SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_HASH_ENABLE__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_HASH_ENABLE_MASK) >> SQ_BUF_RSRC_WORD3_HASH_ENABLE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_HEAP__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_HEAP_MASK) >> SQ_BUF_RSRC_WORD3_HEAP_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_INDEX_STRIDE__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_INDEX_STRIDE_MASK) >> \ - SQ_BUF_RSRC_WORD3_INDEX_STRIDE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_MTYPE__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_MTYPE_MASK) >> SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_NUM_FORMAT__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_NUM_FORMAT_MASK) >> SQ_BUF_RSRC_WORD3_NUM_FORMAT_SHIFT) - -#define SQ_BUF_RSRC_WORD3_GET_TYPE__VI(sq_buf_rsrc_word3) \ - ((sq_buf_rsrc_word3 & SQ_BUF_RSRC_WORD3_TYPE_MASK) >> SQ_BUF_RSRC_WORD3_TYPE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_MASK__VI \ - (SQ_BUF_RSRC_WORD3_DST_SEL_X_MASK | SQ_BUF_RSRC_WORD3_DST_SEL_Y_MASK | \ - SQ_BUF_RSRC_WORD3_DST_SEL_Z_MASK | SQ_BUF_RSRC_WORD3_DST_SEL_W_MASK | \ - SQ_BUF_RSRC_WORD3_NUM_FORMAT_MASK | SQ_BUF_RSRC_WORD3_DATA_FORMAT_MASK | \ - SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_MASK | SQ_BUF_RSRC_WORD3_INDEX_STRIDE_MASK | \ - SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_MASK | SQ_BUF_RSRC_WORD3_ATC_MASK | \ - SQ_BUF_RSRC_WORD3_HASH_ENABLE_MASK | SQ_BUF_RSRC_WORD3_HEAP_MASK | \ - SQ_BUF_RSRC_WORD3_MTYPE_MASK | SQ_BUF_RSRC_WORD3_TYPE_MASK) - -#define SQ_BUF_RSRC_WORD3_SET_ADD_TID_ENABLE__VI(sq_buf_rsrc_word3_reg, add_tid_enable) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_MASK) | \ - (add_tid_enable << SQ_BUF_RSRC_WORD3_ADD_TID_ENABLE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_ATC__VI(sq_buf_rsrc_word3_reg, atc) \ - sq_buf_rsrc_word3_reg = \ - (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_ATC_MASK) | (atc << SQ_BUF_RSRC_WORD3_ATC_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_DATA_FORMAT__VI(sq_buf_rsrc_word3_reg, data_format) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_DATA_FORMAT_MASK) | \ - (data_format << SQ_BUF_RSRC_WORD3_DATA_FORMAT_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_DST_SEL_W__VI(sq_buf_rsrc_word3_reg, dst_sel_w) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_DST_SEL_W_MASK) | \ - (dst_sel_w << SQ_BUF_RSRC_WORD3_DST_SEL_W_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_DST_SEL_X__VI(sq_buf_rsrc_word3_reg, dst_sel_x) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_DST_SEL_X_MASK) | \ - (dst_sel_x << SQ_BUF_RSRC_WORD3_DST_SEL_X_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_DST_SEL_Y__VI(sq_buf_rsrc_word3_reg, dst_sel_y) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_DST_SEL_Y_MASK) | \ - (dst_sel_y << SQ_BUF_RSRC_WORD3_DST_SEL_Y_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_DST_SEL_Z__VI(sq_buf_rsrc_word3_reg, dst_sel_z) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_DST_SEL_Z_MASK) | \ - (dst_sel_z << SQ_BUF_RSRC_WORD3_DST_SEL_Z_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_ELEMENT_SIZE__VI(sq_buf_rsrc_word3_reg, element_size) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_MASK) | \ - (element_size << SQ_BUF_RSRC_WORD3_ELEMENT_SIZE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_HASH_ENABLE__VI(sq_buf_rsrc_word3_reg, hash_enable) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_HASH_ENABLE_MASK) | \ - (hash_enable << SQ_BUF_RSRC_WORD3_HASH_ENABLE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_HEAP__VI(sq_buf_rsrc_word3_reg, heap) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_HEAP_MASK) | \ - (heap << SQ_BUF_RSRC_WORD3_HEAP_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_INDEX_STRIDE__VI(sq_buf_rsrc_word3_reg, index_stride) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_INDEX_STRIDE_MASK) | \ - (index_stride << SQ_BUF_RSRC_WORD3_INDEX_STRIDE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_MTYPE__VI(sq_buf_rsrc_word3_reg, mtype) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_MTYPE_MASK) | \ - (mtype << SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_NUM_FORMAT__VI(sq_buf_rsrc_word3_reg, num_format) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_NUM_FORMAT_MASK) | \ - (num_format << SQ_BUF_RSRC_WORD3_NUM_FORMAT_SHIFT) - -#define SQ_BUF_RSRC_WORD3_SET_TYPE__VI(sq_buf_rsrc_word3_reg, type) \ - sq_buf_rsrc_word3_reg = (sq_buf_rsrc_word3_reg & ~SQ_BUF_RSRC_WORD3_TYPE_MASK) | \ - (type << SQ_BUF_RSRC_WORD3_TYPE_SHIFT) - -#define SQ_CMD_DATA_MASK__VI 0x00000700 -#define SQ_CMD_DATA_SHIFT__VI 8 -#define SQ_CMD_DATA_SIZE__VI 3 -#define SQ_CMD_DEFAULT__VI 0xc50d05c5 -#define SQ_CMD_GET_CHECK_VMID__VI(sq_cmd) \ - ((sq_cmd & SQ_CMD_CHECK_VMID_MASK) >> SQ_CMD_CHECK_VMID_SHIFT) - -#define SQ_CMD_GET_CMD__VI(sq_cmd) ((sq_cmd & SQ_CMD_CMD_MASK) >> SQ_CMD_CMD_SHIFT) - -#define SQ_CMD_GET_DATA__VI(sq_cmd) ((sq_cmd & SQ_CMD_DATA_MASK) >> SQ_CMD_DATA_SHIFT) - -#define SQ_CMD_GET_MODE__VI(sq_cmd) ((sq_cmd & SQ_CMD_MODE_MASK) >> SQ_CMD_MODE_SHIFT) - -#define SQ_CMD_GET_QUEUE_ID__VI(sq_cmd) ((sq_cmd & SQ_CMD_QUEUE_ID_MASK) >> SQ_CMD_QUEUE_ID_SHIFT) - -#define SQ_CMD_GET_SIMD_ID__VI(sq_cmd) ((sq_cmd & SQ_CMD_SIMD_ID_MASK) >> SQ_CMD_SIMD_ID_SHIFT) - -#define SQ_CMD_GET_VM_ID__VI(sq_cmd) ((sq_cmd & SQ_CMD_VM_ID_MASK) >> SQ_CMD_VM_ID_SHIFT) - -#define SQ_CMD_GET_WAVE_ID__VI(sq_cmd) ((sq_cmd & SQ_CMD_WAVE_ID_MASK) >> SQ_CMD_WAVE_ID_SHIFT) - -#define SQ_CMD_MASK__VI \ - (SQ_CMD_CMD_MASK | SQ_CMD_MODE_MASK | SQ_CMD_CHECK_VMID_MASK | SQ_CMD_DATA_MASK | \ - SQ_CMD_WAVE_ID_MASK | SQ_CMD_SIMD_ID_MASK | SQ_CMD_QUEUE_ID_MASK | SQ_CMD_VM_ID_MASK) - -#define SQ_CMD_SET_CHECK_VMID__VI(sq_cmd_reg, check_vmid) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_CHECK_VMID_MASK) | (check_vmid << SQ_CMD_CHECK_VMID_SHIFT) - -#define SQ_CMD_SET_CMD__VI(sq_cmd_reg, cmd) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_CMD_MASK) | (cmd << SQ_CMD_CMD_SHIFT) - -#define SQ_CMD_SET_DATA__VI(sq_cmd_reg, data) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_DATA_MASK) | (data << SQ_CMD_DATA_SHIFT) - -#define SQ_CMD_SET_MODE__VI(sq_cmd_reg, mode) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_MODE_MASK) | (mode << SQ_CMD_MODE_SHIFT) - -#define SQ_CMD_SET_QUEUE_ID__VI(sq_cmd_reg, queue_id) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_QUEUE_ID_MASK) | (queue_id << SQ_CMD_QUEUE_ID_SHIFT) - -#define SQ_CMD_SET_SIMD_ID__VI(sq_cmd_reg, simd_id) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_SIMD_ID_MASK) | (simd_id << SQ_CMD_SIMD_ID_SHIFT) - -#define SQ_CMD_SET_VM_ID__VI(sq_cmd_reg, vm_id) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_VM_ID_MASK) | (vm_id << SQ_CMD_VM_ID_SHIFT) - -#define SQ_CMD_SET_WAVE_ID__VI(sq_cmd_reg, wave_id) \ - sq_cmd_reg = (sq_cmd_reg & ~SQ_CMD_WAVE_ID_MASK) | (wave_id << SQ_CMD_WAVE_ID_SHIFT) - -#define SQ_CMD_TIMESTAMP_GET_TIMESTAMP__VI(sq_cmd_timestamp) \ - ((sq_cmd_timestamp & SQ_CMD_TIMESTAMP_TIMESTAMP_MASK) >> SQ_CMD_TIMESTAMP_TIMESTAMP_SHIFT) - -#define SQ_CMD_TIMESTAMP_MASK__VI (SQ_CMD_TIMESTAMP_TIMESTAMP_MASK) - -#define SQ_CMD_TIMESTAMP_SET_TIMESTAMP__VI(sq_cmd_timestamp_reg, timestamp) \ - sq_cmd_timestamp_reg = (sq_cmd_timestamp_reg & ~SQ_CMD_TIMESTAMP_TIMESTAMP_MASK) | \ - (timestamp << SQ_CMD_TIMESTAMP_TIMESTAMP_SHIFT) - -#define SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_MASK__VI 0x00000400 -#define SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_SHIFT__VI 10 -#define SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_SIZE__VI 1 -#define SQ_CONFIG_DEBUG_SINGLE_MEMOP_MASK__VI 0x00000200 -#define SQ_CONFIG_DEBUG_SINGLE_MEMOP_SHIFT__VI 9 -#define SQ_CONFIG_DEBUG_SINGLE_MEMOP_SIZE__VI 1 -#define SQ_CONFIG_DEFAULT__SI__CI 0x00000000 -#define SQ_CONFIG_DEFAULT__VI 0x01180000 -#define SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_MASK__VI 0x00020000 -#define SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_SHIFT__VI 17 -#define SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_SIZE__VI 1 -#define SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_MASK__VI 0x00010000 -#define SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_SHIFT__VI 16 -#define SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_SIZE__VI 1 -#define SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK__VI 0x00040000 -#define SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_SHIFT__VI 18 -#define SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_SIZE__VI 1 -#define SQ_CONFIG_GET_DEBUG_EN__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DEBUG_EN_MASK) >> SQ_CONFIG_DEBUG_EN_SHIFT) - -#define SQ_CONFIG_GET_DEBUG_ONE_INST_CLAUSE__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_MASK) >> SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_SHIFT) - -#define SQ_CONFIG_GET_DEBUG_SINGLE_MEMOP__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DEBUG_SINGLE_MEMOP_MASK) >> SQ_CONFIG_DEBUG_SINGLE_MEMOP_SHIFT) - -#define SQ_CONFIG_GET_DISABLE_SMEM_SOFT_CLAUSE__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_MASK) >> \ - SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_SHIFT) - -#define SQ_CONFIG_GET_DISABLE_VMEM_SOFT_CLAUSE__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_MASK) >> \ - SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_SHIFT) - -#define SQ_CONFIG_GET_DUA_FLAT_LDS_PINGPONG_DISABLE__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_MASK) >> \ - SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_SHIFT) - -#define SQ_CONFIG_GET_DUA_FLAT_LOCK_ENABLE__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_MASK) >> SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_SHIFT) - -#define SQ_CONFIG_GET_DUA_LDS_BYPASS_DISABLE__VI(sq_config) \ - ((sq_config & SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_MASK) >> SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_SHIFT) - -#define SQ_CONFIG_GET_EARLY_TA_DONE_DISABLE__VI(sq_config) \ - ((sq_config & SQ_CONFIG_EARLY_TA_DONE_DISABLE_MASK) >> SQ_CONFIG_EARLY_TA_DONE_DISABLE_SHIFT) - -#define SQ_CONFIG_GET_ENABLE_HIPRIO_ON_EXP_RDY_VS__VI(sq_config) \ - ((sq_config & SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK) >> \ - SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_SHIFT) - -#define SQ_CONFIG_GET_PRIO_VAL_ON_EXP_RDY_VS__VI(sq_config) \ - ((sq_config & SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_MASK) >> SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_SHIFT) - -#define SQ_CONFIG_GET_REPLAY_SLEEP_CNT__VI(sq_config) \ - ((sq_config & SQ_CONFIG_REPLAY_SLEEP_CNT_MASK) >> SQ_CONFIG_REPLAY_SLEEP_CNT_SHIFT) - -#define SQ_CONFIG_GET_UNUSED__VI(sq_config) \ - ((sq_config & SQ_CONFIG_UNUSED_MASK) >> SQ_CONFIG_UNUSED_SHIFT) - -#define SQ_CONFIG_MASK__VI \ - (SQ_CONFIG_UNUSED_MASK | SQ_CONFIG_DEBUG_EN_MASK | SQ_CONFIG_DEBUG_SINGLE_MEMOP_MASK | \ - SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_MASK | SQ_CONFIG_EARLY_TA_DONE_DISABLE_MASK | \ - SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_MASK | SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_MASK | \ - SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_MASK | SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_MASK | \ - SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_MASK | SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK | \ - SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_MASK | SQ_CONFIG_REPLAY_SLEEP_CNT_MASK) - -#define SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_MASK__VI 0x00180000 -#define SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_SHIFT__VI 19 -#define SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_SIZE__VI 2 -#define SQ_CONFIG_REPLAY_SLEEP_CNT_MASK__VI 0x01e00000 -#define SQ_CONFIG_REPLAY_SLEEP_CNT_SHIFT__VI 21 -#define SQ_CONFIG_REPLAY_SLEEP_CNT_SIZE__VI 4 -#define SQ_CONFIG_SET_DEBUG_EN__VI(sq_config_reg, debug_en) \ - sq_config_reg = \ - (sq_config_reg & ~SQ_CONFIG_DEBUG_EN_MASK) | (debug_en << SQ_CONFIG_DEBUG_EN_SHIFT) - -#define SQ_CONFIG_SET_DEBUG_ONE_INST_CLAUSE__VI(sq_config_reg, debug_one_inst_clause) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_MASK) | \ - (debug_one_inst_clause << SQ_CONFIG_DEBUG_ONE_INST_CLAUSE_SHIFT) - -#define SQ_CONFIG_SET_DEBUG_SINGLE_MEMOP__VI(sq_config_reg, debug_single_memop) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_DEBUG_SINGLE_MEMOP_MASK) | \ - (debug_single_memop << SQ_CONFIG_DEBUG_SINGLE_MEMOP_SHIFT) - -#define SQ_CONFIG_SET_DISABLE_SMEM_SOFT_CLAUSE__VI(sq_config_reg, disable_smem_soft_clause) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_MASK) | \ - (disable_smem_soft_clause << SQ_CONFIG_DISABLE_SMEM_SOFT_CLAUSE_SHIFT) - -#define SQ_CONFIG_SET_DISABLE_VMEM_SOFT_CLAUSE__VI(sq_config_reg, disable_vmem_soft_clause) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_MASK) | \ - (disable_vmem_soft_clause << SQ_CONFIG_DISABLE_VMEM_SOFT_CLAUSE_SHIFT) - -#define SQ_CONFIG_SET_DUA_FLAT_LDS_PINGPONG_DISABLE__VI(sq_config_reg, \ - dua_flat_lds_pingpong_disable) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_MASK) | \ - (dua_flat_lds_pingpong_disable << SQ_CONFIG_DUA_FLAT_LDS_PINGPONG_DISABLE_SHIFT) - -#define SQ_CONFIG_SET_DUA_FLAT_LOCK_ENABLE__VI(sq_config_reg, dua_flat_lock_enable) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_MASK) | \ - (dua_flat_lock_enable << SQ_CONFIG_DUA_FLAT_LOCK_ENABLE_SHIFT) - -#define SQ_CONFIG_SET_DUA_LDS_BYPASS_DISABLE__VI(sq_config_reg, dua_lds_bypass_disable) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_MASK) | \ - (dua_lds_bypass_disable << SQ_CONFIG_DUA_LDS_BYPASS_DISABLE_SHIFT) - -#define SQ_CONFIG_SET_EARLY_TA_DONE_DISABLE__VI(sq_config_reg, early_ta_done_disable) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_EARLY_TA_DONE_DISABLE_MASK) | \ - (early_ta_done_disable << SQ_CONFIG_EARLY_TA_DONE_DISABLE_SHIFT) - -#define SQ_CONFIG_SET_ENABLE_HIPRIO_ON_EXP_RDY_VS__VI(sq_config_reg, enable_hiprio_on_exp_rdy_vs) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK) | \ - (enable_hiprio_on_exp_rdy_vs << SQ_CONFIG_ENABLE_HIPRIO_ON_EXP_RDY_VS_SHIFT) - -#define SQ_CONFIG_SET_PRIO_VAL_ON_EXP_RDY_VS__VI(sq_config_reg, prio_val_on_exp_rdy_vs) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_MASK) | \ - (prio_val_on_exp_rdy_vs << SQ_CONFIG_PRIO_VAL_ON_EXP_RDY_VS_SHIFT) - -#define SQ_CONFIG_SET_REPLAY_SLEEP_CNT__VI(sq_config_reg, replay_sleep_cnt) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_REPLAY_SLEEP_CNT_MASK) | \ - (replay_sleep_cnt << SQ_CONFIG_REPLAY_SLEEP_CNT_SHIFT) - -#define SQ_CONFIG_SET_UNUSED__VI(sq_config_reg, unused) \ - sq_config_reg = (sq_config_reg & ~SQ_CONFIG_UNUSED_MASK) | (unused << SQ_CONFIG_UNUSED_SHIFT) - -#define SQ_DEBUG_CTRL_LOCAL_DEFAULT__SI__CI 0x00000000 -#define SQ_DEBUG_CTRL_LOCAL_DEFAULT__VI 0x000000cd -#define SQ_DEBUG_CTRL_LOCAL_GET_UNUSED__VI(sq_debug_ctrl_local) \ - ((sq_debug_ctrl_local & SQ_DEBUG_CTRL_LOCAL_UNUSED_MASK) >> SQ_DEBUG_CTRL_LOCAL_UNUSED_SHIFT) - -#define SQ_DEBUG_CTRL_LOCAL_MASK__VI (SQ_DEBUG_CTRL_LOCAL_UNUSED_MASK) - -#define SQ_DEBUG_CTRL_LOCAL_SET_UNUSED__VI(sq_debug_ctrl_local_reg, unused) \ - sq_debug_ctrl_local_reg = (sq_debug_ctrl_local_reg & ~SQ_DEBUG_CTRL_LOCAL_UNUSED_MASK) | \ - (unused << SQ_DEBUG_CTRL_LOCAL_UNUSED_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_GET_FIFO_LEVEL_GFX0__VI(sq_debug_sts_global2) \ - ((sq_debug_sts_global2 & SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_MASK) >> \ - SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_GET_FIFO_LEVEL_GFX1__VI(sq_debug_sts_global2) \ - ((sq_debug_sts_global2 & SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_MASK) >> \ - SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_GET_FIFO_LEVEL_HOST__VI(sq_debug_sts_global2) \ - ((sq_debug_sts_global2 & SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_MASK) >> \ - SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_GET_FIFO_LEVEL_IMMED__VI(sq_debug_sts_global2) \ - ((sq_debug_sts_global2 & SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_MASK) >> \ - SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_MASK__VI \ - (SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_MASK | SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_MASK | \ - SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_MASK | SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_MASK) - -#define SQ_DEBUG_STS_GLOBAL2_SET_FIFO_LEVEL_GFX0__VI(sq_debug_sts_global2_reg, fifo_level_gfx0) \ - sq_debug_sts_global2_reg = \ - (sq_debug_sts_global2_reg & ~SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_MASK) | \ - (fifo_level_gfx0 << SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX0_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_SET_FIFO_LEVEL_GFX1__VI(sq_debug_sts_global2_reg, fifo_level_gfx1) \ - sq_debug_sts_global2_reg = \ - (sq_debug_sts_global2_reg & ~SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_MASK) | \ - (fifo_level_gfx1 << SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_GFX1_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_SET_FIFO_LEVEL_HOST__VI(sq_debug_sts_global2_reg, fifo_level_host) \ - sq_debug_sts_global2_reg = \ - (sq_debug_sts_global2_reg & ~SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_MASK) | \ - (fifo_level_host << SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_HOST_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL2_SET_FIFO_LEVEL_IMMED__VI(sq_debug_sts_global2_reg, fifo_level_immed) \ - sq_debug_sts_global2_reg = \ - (sq_debug_sts_global2_reg & ~SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_MASK) | \ - (fifo_level_immed << SQ_DEBUG_STS_GLOBAL2_FIFO_LEVEL_IMMED_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_MASK__VI 0x000003f0 -#define SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_SIZE__VI 6 -#define SQ_DEBUG_STS_GLOBAL3_GET_FIFO_LEVEL_HOST_CMD__VI(sq_debug_sts_global3) \ - ((sq_debug_sts_global3 & SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_MASK) >> \ - SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL3_GET_FIFO_LEVEL_HOST_REG__VI(sq_debug_sts_global3) \ - ((sq_debug_sts_global3 & SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_MASK) >> \ - SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL3_MASK__VI \ - (SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_MASK | SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_MASK) - -#define SQ_DEBUG_STS_GLOBAL3_SET_FIFO_LEVEL_HOST_CMD__VI(sq_debug_sts_global3_reg, \ - fifo_level_host_cmd) \ - sq_debug_sts_global3_reg = \ - (sq_debug_sts_global3_reg & ~SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_MASK) | \ - (fifo_level_host_cmd << SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_CMD_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL3_SET_FIFO_LEVEL_HOST_REG__VI(sq_debug_sts_global3_reg, \ - fifo_level_host_reg) \ - sq_debug_sts_global3_reg = \ - (sq_debug_sts_global3_reg & ~SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_MASK) | \ - (fifo_level_host_reg << SQ_DEBUG_STS_GLOBAL3_FIFO_LEVEL_HOST_REG_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_GET_BUSY__VI(sq_debug_sts_global) \ - ((sq_debug_sts_global & SQ_DEBUG_STS_GLOBAL_BUSY_MASK) >> SQ_DEBUG_STS_GLOBAL_BUSY_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_GET_INTERRUPT_MSG_BUSY__VI(sq_debug_sts_global) \ - ((sq_debug_sts_global & SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_MASK) >> \ - SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_GET_WAVE_LEVEL_SH0__VI(sq_debug_sts_global) \ - ((sq_debug_sts_global & SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_MASK) >> \ - SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_GET_WAVE_LEVEL_SH1__VI(sq_debug_sts_global) \ - ((sq_debug_sts_global & SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_MASK) >> \ - SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_MASK__VI \ - (SQ_DEBUG_STS_GLOBAL_BUSY_MASK | SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_MASK | \ - SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_MASK | SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_MASK) - -#define SQ_DEBUG_STS_GLOBAL_SET_BUSY__VI(sq_debug_sts_global_reg, busy) \ - sq_debug_sts_global_reg = (sq_debug_sts_global_reg & ~SQ_DEBUG_STS_GLOBAL_BUSY_MASK) | \ - (busy << SQ_DEBUG_STS_GLOBAL_BUSY_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_SET_INTERRUPT_MSG_BUSY__VI(sq_debug_sts_global_reg, \ - interrupt_msg_busy) \ - sq_debug_sts_global_reg = \ - (sq_debug_sts_global_reg & ~SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_MASK) | \ - (interrupt_msg_busy << SQ_DEBUG_STS_GLOBAL_INTERRUPT_MSG_BUSY_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_SET_WAVE_LEVEL_SH0__VI(sq_debug_sts_global_reg, wave_level_sh0) \ - sq_debug_sts_global_reg = (sq_debug_sts_global_reg & ~SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_MASK) | \ - (wave_level_sh0 << SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH0_SHIFT) - -#define SQ_DEBUG_STS_GLOBAL_SET_WAVE_LEVEL_SH1__VI(sq_debug_sts_global_reg, wave_level_sh1) \ - sq_debug_sts_global_reg = (sq_debug_sts_global_reg & ~SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_MASK) | \ - (wave_level_sh1 << SQ_DEBUG_STS_GLOBAL_WAVE_LEVEL_SH1_SHIFT) - -#define SQ_DEBUG_STS_LOCAL_GET_BUSY__VI(sq_debug_sts_local) \ - ((sq_debug_sts_local & SQ_DEBUG_STS_LOCAL_BUSY_MASK) >> SQ_DEBUG_STS_LOCAL_BUSY_SHIFT) - -#define SQ_DEBUG_STS_LOCAL_GET_WAVE_LEVEL__VI(sq_debug_sts_local) \ - ((sq_debug_sts_local & SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_MASK) >> SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_SHIFT) - -#define SQ_DEBUG_STS_LOCAL_MASK__VI \ - (SQ_DEBUG_STS_LOCAL_BUSY_MASK | SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_MASK) - -#define SQ_DEBUG_STS_LOCAL_SET_BUSY__VI(sq_debug_sts_local_reg, busy) \ - sq_debug_sts_local_reg = (sq_debug_sts_local_reg & ~SQ_DEBUG_STS_LOCAL_BUSY_MASK) | \ - (busy << SQ_DEBUG_STS_LOCAL_BUSY_SHIFT) - -#define SQ_DEBUG_STS_LOCAL_SET_WAVE_LEVEL__VI(sq_debug_sts_local_reg, wave_level) \ - sq_debug_sts_local_reg = (sq_debug_sts_local_reg & ~SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_MASK) | \ - (wave_level << SQ_DEBUG_STS_LOCAL_WAVE_LEVEL_SHIFT) - -#define SQ_DSM_CNTL_DEFAULT__VI 0x00000000 -#define SQ_DSM_CNTL_GET_LDS_ENABLE_SINGLE_WRITE01__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_MASK) >> \ - SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_SHIFT) - -#define SQ_DSM_CNTL_GET_LDS_ENABLE_SINGLE_WRITE23__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_MASK) >> \ - SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_LDS_IRRITATOR_DATA0__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_LDS_IRRITATOR_DATA1__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_LDS_IRRITATOR_DATA2__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_LDS_IRRITATOR_DATA3__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_SGPR_IRRITATOR_DATA0__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_SGPR_IRRITATOR_DATA1__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_SP_IRRITATOR_DATA0__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_SHIFT) - -#define SQ_DSM_CNTL_GET_SEL_DSM_SP_IRRITATOR_DATA1__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_MASK) >> \ - SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_SHIFT) - -#define SQ_DSM_CNTL_GET_SGPR_ENABLE_SINGLE_WRITE__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_MASK) >> \ - SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_SHIFT) - -#define SQ_DSM_CNTL_GET_SPI_BACKPRESSURE_0__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SPI_BACKPRESSURE_0_MASK) >> SQ_DSM_CNTL_SPI_BACKPRESSURE_0_SHIFT) - -#define SQ_DSM_CNTL_GET_SPI_BACKPRESSURE_1__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SPI_BACKPRESSURE_1_MASK) >> SQ_DSM_CNTL_SPI_BACKPRESSURE_1_SHIFT) - -#define SQ_DSM_CNTL_GET_SP_ENABLE_SINGLE_WRITE__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_MASK) >> \ - SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_SHIFT) - -#define SQ_DSM_CNTL_GET_WAVEFRONT_STALL_0__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_WAVEFRONT_STALL_0_MASK) >> SQ_DSM_CNTL_WAVEFRONT_STALL_0_SHIFT) - -#define SQ_DSM_CNTL_GET_WAVEFRONT_STALL_1__VI(sq_dsm_cntl) \ - ((sq_dsm_cntl & SQ_DSM_CNTL_WAVEFRONT_STALL_1_MASK) >> SQ_DSM_CNTL_WAVEFRONT_STALL_1_SHIFT) - -#define SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_MASK__VI 0x00040000 -#define SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_SHIFT__VI 18 -#define SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_SIZE__VI 1 -#define SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_MASK__VI 0x00200000 -#define SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_SHIFT__VI 21 -#define SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_SIZE__VI 1 -#define SQ_DSM_CNTL_MASK__VI \ - (SQ_DSM_CNTL_WAVEFRONT_STALL_0_MASK | SQ_DSM_CNTL_WAVEFRONT_STALL_1_MASK | \ - SQ_DSM_CNTL_SPI_BACKPRESSURE_0_MASK | SQ_DSM_CNTL_SPI_BACKPRESSURE_1_MASK | \ - SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_MASK | SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_MASK | \ - SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_MASK | SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_MASK | \ - SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_MASK | SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_MASK | \ - SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_MASK | SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_MASK | \ - SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_MASK | SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_MASK | \ - SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_MASK | SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_MASK) - -#define SQ_DSM_CNTL_REG_SIZE__VI 32 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_MASK__VI 0x00010000 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_SHIFT__VI 16 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_SIZE__VI 1 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_MASK__VI 0x00020000 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_SHIFT__VI 17 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_SIZE__VI 1 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_MASK__VI 0x00080000 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_SHIFT__VI 19 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_SIZE__VI 1 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_MASK__VI 0x00100000 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_SHIFT__VI 20 -#define SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_SIZE__VI 1 -#define SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_MASK__VI 0x00000100 -#define SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_SHIFT__VI 8 -#define SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_SIZE__VI 1 -#define SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_MASK__VI 0x00000200 -#define SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_SHIFT__VI 9 -#define SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_SIZE__VI 1 -#define SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_MASK__VI 0x01000000 -#define SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_SHIFT__VI 24 -#define SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_SIZE__VI 1 -#define SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_MASK__VI 0x02000000 -#define SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_SHIFT__VI 25 -#define SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_SIZE__VI 1 -#define SQ_DSM_CNTL_SET_LDS_ENABLE_SINGLE_WRITE01__VI(sq_dsm_cntl_reg, lds_enable_single_write01) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_MASK) | \ - (lds_enable_single_write01 << SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE01_SHIFT) - -#define SQ_DSM_CNTL_SET_LDS_ENABLE_SINGLE_WRITE23__VI(sq_dsm_cntl_reg, lds_enable_single_write23) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_MASK) | \ - (lds_enable_single_write23 << SQ_DSM_CNTL_LDS_ENABLE_SINGLE_WRITE23_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_LDS_IRRITATOR_DATA0__VI(sq_dsm_cntl_reg, \ - sel_dsm_lds_irritator_data0) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_MASK) | \ - (sel_dsm_lds_irritator_data0 << SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA0_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_LDS_IRRITATOR_DATA1__VI(sq_dsm_cntl_reg, \ - sel_dsm_lds_irritator_data1) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_MASK) | \ - (sel_dsm_lds_irritator_data1 << SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA1_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_LDS_IRRITATOR_DATA2__VI(sq_dsm_cntl_reg, \ - sel_dsm_lds_irritator_data2) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_MASK) | \ - (sel_dsm_lds_irritator_data2 << SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA2_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_LDS_IRRITATOR_DATA3__VI(sq_dsm_cntl_reg, \ - sel_dsm_lds_irritator_data3) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_MASK) | \ - (sel_dsm_lds_irritator_data3 << SQ_DSM_CNTL_SEL_DSM_LDS_IRRITATOR_DATA3_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_SGPR_IRRITATOR_DATA0__VI(sq_dsm_cntl_reg, \ - sel_dsm_sgpr_irritator_data0) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_MASK) | \ - (sel_dsm_sgpr_irritator_data0 << SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA0_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_SGPR_IRRITATOR_DATA1__VI(sq_dsm_cntl_reg, \ - sel_dsm_sgpr_irritator_data1) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_MASK) | \ - (sel_dsm_sgpr_irritator_data1 << SQ_DSM_CNTL_SEL_DSM_SGPR_IRRITATOR_DATA1_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_SP_IRRITATOR_DATA0__VI(sq_dsm_cntl_reg, \ - sel_dsm_sp_irritator_data0) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_MASK) | \ - (sel_dsm_sp_irritator_data0 << SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA0_SHIFT) - -#define SQ_DSM_CNTL_SET_SEL_DSM_SP_IRRITATOR_DATA1__VI(sq_dsm_cntl_reg, \ - sel_dsm_sp_irritator_data1) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_MASK) | \ - (sel_dsm_sp_irritator_data1 << SQ_DSM_CNTL_SEL_DSM_SP_IRRITATOR_DATA1_SHIFT) - -#define SQ_DSM_CNTL_SET_SGPR_ENABLE_SINGLE_WRITE__VI(sq_dsm_cntl_reg, sgpr_enable_single_write) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_MASK) | \ - (sgpr_enable_single_write << SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_SHIFT) - -#define SQ_DSM_CNTL_SET_SPI_BACKPRESSURE_0__VI(sq_dsm_cntl_reg, spi_backpressure_0) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SPI_BACKPRESSURE_0_MASK) | \ - (spi_backpressure_0 << SQ_DSM_CNTL_SPI_BACKPRESSURE_0_SHIFT) - -#define SQ_DSM_CNTL_SET_SPI_BACKPRESSURE_1__VI(sq_dsm_cntl_reg, spi_backpressure_1) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SPI_BACKPRESSURE_1_MASK) | \ - (spi_backpressure_1 << SQ_DSM_CNTL_SPI_BACKPRESSURE_1_SHIFT) - -#define SQ_DSM_CNTL_SET_SP_ENABLE_SINGLE_WRITE__VI(sq_dsm_cntl_reg, sp_enable_single_write) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_MASK) | \ - (sp_enable_single_write << SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_SHIFT) - -#define SQ_DSM_CNTL_SET_WAVEFRONT_STALL_0__VI(sq_dsm_cntl_reg, wavefront_stall_0) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_WAVEFRONT_STALL_0_MASK) | \ - (wavefront_stall_0 << SQ_DSM_CNTL_WAVEFRONT_STALL_0_SHIFT) - -#define SQ_DSM_CNTL_SET_WAVEFRONT_STALL_1__VI(sq_dsm_cntl_reg, wavefront_stall_1) \ - sq_dsm_cntl_reg = (sq_dsm_cntl_reg & ~SQ_DSM_CNTL_WAVEFRONT_STALL_1_MASK) | \ - (wavefront_stall_1 << SQ_DSM_CNTL_WAVEFRONT_STALL_1_SHIFT) - -#define SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_MASK__VI 0x00000400 -#define SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_SHIFT__VI 10 -#define SQ_DSM_CNTL_SGPR_ENABLE_SINGLE_WRITE_SIZE__VI 1 -#define SQ_DSM_CNTL_SPI_BACKPRESSURE_0_MASK__VI 0x00000004 -#define SQ_DSM_CNTL_SPI_BACKPRESSURE_0_SHIFT__VI 2 -#define SQ_DSM_CNTL_SPI_BACKPRESSURE_0_SIZE__VI 1 -#define SQ_DSM_CNTL_SPI_BACKPRESSURE_1_MASK__VI 0x00000008 -#define SQ_DSM_CNTL_SPI_BACKPRESSURE_1_SHIFT__VI 3 -#define SQ_DSM_CNTL_SPI_BACKPRESSURE_1_SIZE__VI 1 -#define SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_MASK__VI 0x04000000 -#define SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_SHIFT__VI 26 -#define SQ_DSM_CNTL_SP_ENABLE_SINGLE_WRITE_SIZE__VI 1 -#define SQ_DSM_CNTL_WAVEFRONT_STALL_0_MASK__VI 0x00000001 -#define SQ_DSM_CNTL_WAVEFRONT_STALL_0_SHIFT__VI 0x00000000 -#define SQ_DSM_CNTL_WAVEFRONT_STALL_0_SIZE__VI 1 -#define SQ_DSM_CNTL_WAVEFRONT_STALL_1_MASK__VI 0x00000002 -#define SQ_DSM_CNTL_WAVEFRONT_STALL_1_SHIFT__VI 1 -#define SQ_DSM_CNTL_WAVEFRONT_STALL_1_SIZE__VI 1 -#define SQ_EDC_DED_CNT_DEFAULT__VI 0x00000000 -#define SQ_EDC_DED_CNT_GET_LDS_DED__VI(sq_edc_ded_cnt) \ - ((sq_edc_ded_cnt & SQ_EDC_DED_CNT_LDS_DED_MASK) >> SQ_EDC_DED_CNT_LDS_DED_SHIFT) - -#define SQ_EDC_DED_CNT_GET_SGPR_DED__VI(sq_edc_ded_cnt) \ - ((sq_edc_ded_cnt & SQ_EDC_DED_CNT_SGPR_DED_MASK) >> SQ_EDC_DED_CNT_SGPR_DED_SHIFT) - -#define SQ_EDC_DED_CNT_GET_VGPR_DED__VI(sq_edc_ded_cnt) \ - ((sq_edc_ded_cnt & SQ_EDC_DED_CNT_VGPR_DED_MASK) >> SQ_EDC_DED_CNT_VGPR_DED_SHIFT) - -#define SQ_EDC_DED_CNT_LDS_DED_MASK__VI 0x000000ff -#define SQ_EDC_DED_CNT_LDS_DED_SHIFT__VI 0x00000000 -#define SQ_EDC_DED_CNT_LDS_DED_SIZE__VI 8 -#define SQ_EDC_DED_CNT_MASK__VI \ - (SQ_EDC_DED_CNT_LDS_DED_MASK | SQ_EDC_DED_CNT_SGPR_DED_MASK | SQ_EDC_DED_CNT_VGPR_DED_MASK) - -#define SQ_EDC_DED_CNT_REG_SIZE__VI 32 -#define SQ_EDC_DED_CNT_SET_LDS_DED__VI(sq_edc_ded_cnt_reg, lds_ded) \ - sq_edc_ded_cnt_reg = (sq_edc_ded_cnt_reg & ~SQ_EDC_DED_CNT_LDS_DED_MASK) | \ - (lds_ded << SQ_EDC_DED_CNT_LDS_DED_SHIFT) - -#define SQ_EDC_DED_CNT_SET_SGPR_DED__VI(sq_edc_ded_cnt_reg, sgpr_ded) \ - sq_edc_ded_cnt_reg = (sq_edc_ded_cnt_reg & ~SQ_EDC_DED_CNT_SGPR_DED_MASK) | \ - (sgpr_ded << SQ_EDC_DED_CNT_SGPR_DED_SHIFT) - -#define SQ_EDC_DED_CNT_SET_VGPR_DED__VI(sq_edc_ded_cnt_reg, vgpr_ded) \ - sq_edc_ded_cnt_reg = (sq_edc_ded_cnt_reg & ~SQ_EDC_DED_CNT_VGPR_DED_MASK) | \ - (vgpr_ded << SQ_EDC_DED_CNT_VGPR_DED_SHIFT) - -#define SQ_EDC_DED_CNT_SGPR_DED_MASK__VI 0x0000ff00 -#define SQ_EDC_DED_CNT_SGPR_DED_SHIFT__VI 8 -#define SQ_EDC_DED_CNT_SGPR_DED_SIZE__VI 8 -#define SQ_EDC_DED_CNT_VGPR_DED_MASK__VI 0x00ff0000 -#define SQ_EDC_DED_CNT_VGPR_DED_SHIFT__VI 16 -#define SQ_EDC_DED_CNT_VGPR_DED_SIZE__VI 8 -#define SQ_EDC_INFO_DEFAULT__VI 0x00000000 -#define SQ_EDC_INFO_GET_SIMD_ID__VI(sq_edc_info) \ - ((sq_edc_info & SQ_EDC_INFO_SIMD_ID_MASK) >> SQ_EDC_INFO_SIMD_ID_SHIFT) - -#define SQ_EDC_INFO_GET_SOURCE__VI(sq_edc_info) \ - ((sq_edc_info & SQ_EDC_INFO_SOURCE_MASK) >> SQ_EDC_INFO_SOURCE_SHIFT) - -#define SQ_EDC_INFO_GET_VM_ID__VI(sq_edc_info) \ - ((sq_edc_info & SQ_EDC_INFO_VM_ID_MASK) >> SQ_EDC_INFO_VM_ID_SHIFT) - -#define SQ_EDC_INFO_GET_WAVE_ID__VI(sq_edc_info) \ - ((sq_edc_info & SQ_EDC_INFO_WAVE_ID_MASK) >> SQ_EDC_INFO_WAVE_ID_SHIFT) - -#define SQ_EDC_INFO_MASK__VI \ - (SQ_EDC_INFO_WAVE_ID_MASK | SQ_EDC_INFO_SIMD_ID_MASK | SQ_EDC_INFO_SOURCE_MASK | \ - SQ_EDC_INFO_VM_ID_MASK) - -#define SQ_EDC_INFO_REG_SIZE__VI 32 -#define SQ_EDC_INFO_SET_SIMD_ID__VI(sq_edc_info_reg, simd_id) \ - sq_edc_info_reg = \ - (sq_edc_info_reg & ~SQ_EDC_INFO_SIMD_ID_MASK) | (simd_id << SQ_EDC_INFO_SIMD_ID_SHIFT) - -#define SQ_EDC_INFO_SET_SOURCE__VI(sq_edc_info_reg, source) \ - sq_edc_info_reg = \ - (sq_edc_info_reg & ~SQ_EDC_INFO_SOURCE_MASK) | (source << SQ_EDC_INFO_SOURCE_SHIFT) - -#define SQ_EDC_INFO_SET_VM_ID__VI(sq_edc_info_reg, vm_id) \ - sq_edc_info_reg = (sq_edc_info_reg & ~SQ_EDC_INFO_VM_ID_MASK) | (vm_id << SQ_EDC_INFO_VM_ID_SHIFT) - -#define SQ_EDC_INFO_SET_WAVE_ID__VI(sq_edc_info_reg, wave_id) \ - sq_edc_info_reg = \ - (sq_edc_info_reg & ~SQ_EDC_INFO_WAVE_ID_MASK) | (wave_id << SQ_EDC_INFO_WAVE_ID_SHIFT) - -#define SQ_EDC_INFO_SIMD_ID_MASK__VI 0x00000030 -#define SQ_EDC_INFO_SIMD_ID_SHIFT__VI 4 -#define SQ_EDC_INFO_SIMD_ID_SIZE__VI 2 -#define SQ_EDC_INFO_SOURCE_MASK__VI 0x000001c0 -#define SQ_EDC_INFO_SOURCE_SHIFT__VI 6 -#define SQ_EDC_INFO_SOURCE_SIZE__VI 3 -#define SQ_EDC_INFO_VM_ID_MASK__VI 0x00001e00 -#define SQ_EDC_INFO_VM_ID_SHIFT__VI 9 -#define SQ_EDC_INFO_VM_ID_SIZE__VI 4 -#define SQ_EDC_INFO_WAVE_ID_MASK__VI 0x0000000f -#define SQ_EDC_INFO_WAVE_ID_SHIFT__VI 0x00000000 -#define SQ_EDC_INFO_WAVE_ID_SIZE__VI 4 -#define SQ_EDC_SEC_CNT_DEFAULT__VI 0x00000000 -#define SQ_EDC_SEC_CNT_GET_LDS_SEC__VI(sq_edc_sec_cnt) \ - ((sq_edc_sec_cnt & SQ_EDC_SEC_CNT_LDS_SEC_MASK) >> SQ_EDC_SEC_CNT_LDS_SEC_SHIFT) - -#define SQ_EDC_SEC_CNT_GET_SGPR_SEC__VI(sq_edc_sec_cnt) \ - ((sq_edc_sec_cnt & SQ_EDC_SEC_CNT_SGPR_SEC_MASK) >> SQ_EDC_SEC_CNT_SGPR_SEC_SHIFT) - -#define SQ_EDC_SEC_CNT_GET_VGPR_SEC__VI(sq_edc_sec_cnt) \ - ((sq_edc_sec_cnt & SQ_EDC_SEC_CNT_VGPR_SEC_MASK) >> SQ_EDC_SEC_CNT_VGPR_SEC_SHIFT) - -#define SQ_EDC_SEC_CNT_LDS_SEC_MASK__VI 0x000000ff -#define SQ_EDC_SEC_CNT_LDS_SEC_SHIFT__VI 0x00000000 -#define SQ_EDC_SEC_CNT_LDS_SEC_SIZE__VI 8 -#define SQ_EDC_SEC_CNT_MASK__VI \ - (SQ_EDC_SEC_CNT_LDS_SEC_MASK | SQ_EDC_SEC_CNT_SGPR_SEC_MASK | SQ_EDC_SEC_CNT_VGPR_SEC_MASK) - -#define SQ_EDC_SEC_CNT_REG_SIZE__VI 32 -#define SQ_EDC_SEC_CNT_SET_LDS_SEC__VI(sq_edc_sec_cnt_reg, lds_sec) \ - sq_edc_sec_cnt_reg = (sq_edc_sec_cnt_reg & ~SQ_EDC_SEC_CNT_LDS_SEC_MASK) | \ - (lds_sec << SQ_EDC_SEC_CNT_LDS_SEC_SHIFT) - -#define SQ_EDC_SEC_CNT_SET_SGPR_SEC__VI(sq_edc_sec_cnt_reg, sgpr_sec) \ - sq_edc_sec_cnt_reg = (sq_edc_sec_cnt_reg & ~SQ_EDC_SEC_CNT_SGPR_SEC_MASK) | \ - (sgpr_sec << SQ_EDC_SEC_CNT_SGPR_SEC_SHIFT) - -#define SQ_EDC_SEC_CNT_SET_VGPR_SEC__VI(sq_edc_sec_cnt_reg, vgpr_sec) \ - sq_edc_sec_cnt_reg = (sq_edc_sec_cnt_reg & ~SQ_EDC_SEC_CNT_VGPR_SEC_MASK) | \ - (vgpr_sec << SQ_EDC_SEC_CNT_VGPR_SEC_SHIFT) - -#define SQ_EDC_SEC_CNT_SGPR_SEC_MASK__VI 0x0000ff00 -#define SQ_EDC_SEC_CNT_SGPR_SEC_SHIFT__VI 8 -#define SQ_EDC_SEC_CNT_SGPR_SEC_SIZE__VI 8 -#define SQ_EDC_SEC_CNT_VGPR_SEC_MASK__VI 0x00ff0000 -#define SQ_EDC_SEC_CNT_VGPR_SEC_SHIFT__VI 16 -#define SQ_EDC_SEC_CNT_VGPR_SEC_SIZE__VI 8 -#define SQ_FIFO_SIZES_DEFAULT__SI__CI 0x00000f0f -#define SQ_FIFO_SIZES_DEFAULT__VI 0x00000f01 -#define SQ_FIFO_SIZES_GET_EXPORT_BUF_SIZE__VI(sq_fifo_sizes) \ - ((sq_fifo_sizes & SQ_FIFO_SIZES_EXPORT_BUF_SIZE_MASK) >> SQ_FIFO_SIZES_EXPORT_BUF_SIZE_SHIFT) - -#define SQ_FIFO_SIZES_GET_INTERRUPT_FIFO_SIZE__VI(sq_fifo_sizes) \ - ((sq_fifo_sizes & SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_MASK) >> \ - SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_SHIFT) - -#define SQ_FIFO_SIZES_GET_TTRACE_FIFO_SIZE__VI(sq_fifo_sizes) \ - ((sq_fifo_sizes & SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_MASK) >> SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_SHIFT) - -#define SQ_FIFO_SIZES_GET_VMEM_DATA_FIFO_SIZE__VI(sq_fifo_sizes) \ - ((sq_fifo_sizes & SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_MASK) >> \ - SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_SHIFT) - -#define SQ_FIFO_SIZES_MASK__VI \ - (SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_MASK | SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_MASK | \ - SQ_FIFO_SIZES_EXPORT_BUF_SIZE_MASK | SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_MASK) - -#define SQ_FIFO_SIZES_SET_EXPORT_BUF_SIZE__VI(sq_fifo_sizes_reg, export_buf_size) \ - sq_fifo_sizes_reg = (sq_fifo_sizes_reg & ~SQ_FIFO_SIZES_EXPORT_BUF_SIZE_MASK) | \ - (export_buf_size << SQ_FIFO_SIZES_EXPORT_BUF_SIZE_SHIFT) - -#define SQ_FIFO_SIZES_SET_INTERRUPT_FIFO_SIZE__VI(sq_fifo_sizes_reg, interrupt_fifo_size) \ - sq_fifo_sizes_reg = (sq_fifo_sizes_reg & ~SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_MASK) | \ - (interrupt_fifo_size << SQ_FIFO_SIZES_INTERRUPT_FIFO_SIZE_SHIFT) - -#define SQ_FIFO_SIZES_SET_TTRACE_FIFO_SIZE__VI(sq_fifo_sizes_reg, ttrace_fifo_size) \ - sq_fifo_sizes_reg = (sq_fifo_sizes_reg & ~SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_MASK) | \ - (ttrace_fifo_size << SQ_FIFO_SIZES_TTRACE_FIFO_SIZE_SHIFT) - -#define SQ_FIFO_SIZES_SET_VMEM_DATA_FIFO_SIZE__VI(sq_fifo_sizes_reg, vmem_data_fifo_size) \ - sq_fifo_sizes_reg = (sq_fifo_sizes_reg & ~SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_MASK) | \ - (vmem_data_fifo_size << SQ_FIFO_SIZES_VMEM_DATA_FIFO_SIZE_SHIFT) - -#define SQ_FLAT_SCRATCH_WORD0_DEFAULT__VI 0x0005cdcd -#define SQ_FLAT_SCRATCH_WORD0_GET_SIZE__VI(sq_flat_scratch_word0) \ - ((sq_flat_scratch_word0 & SQ_FLAT_SCRATCH_WORD0_SIZE_MASK) >> SQ_FLAT_SCRATCH_WORD0_SIZE_SHIFT) - -#define SQ_FLAT_SCRATCH_WORD0_MASK__VI (SQ_FLAT_SCRATCH_WORD0_SIZE_MASK) - -#define SQ_FLAT_SCRATCH_WORD0_SET_SIZE__VI(sq_flat_scratch_word0_reg, size) \ - sq_flat_scratch_word0_reg = (sq_flat_scratch_word0_reg & ~SQ_FLAT_SCRATCH_WORD0_SIZE_MASK) | \ - (size << SQ_FLAT_SCRATCH_WORD0_SIZE_SHIFT) - -#define SQ_FLAT_SCRATCH_WORD1_DEFAULT__VI 0x00cdcdcd -#define SQ_FLAT_SCRATCH_WORD1_GET_OFFSET__VI(sq_flat_scratch_word1) \ - ((sq_flat_scratch_word1 & SQ_FLAT_SCRATCH_WORD1_OFFSET_MASK) >> \ - SQ_FLAT_SCRATCH_WORD1_OFFSET_SHIFT) - -#define SQ_FLAT_SCRATCH_WORD1_MASK__VI (SQ_FLAT_SCRATCH_WORD1_OFFSET_MASK) - -#define SQ_FLAT_SCRATCH_WORD1_SET_OFFSET__VI(sq_flat_scratch_word1_reg, offset) \ - sq_flat_scratch_word1_reg = (sq_flat_scratch_word1_reg & ~SQ_FLAT_SCRATCH_WORD1_OFFSET_MASK) | \ - (offset << SQ_FLAT_SCRATCH_WORD1_OFFSET_SHIFT) - -#define SQ_HV_VMID_CTRL_GET_ALLOWED_VMID_MASK__VI(sq_hv_vmid_ctrl) \ - ((sq_hv_vmid_ctrl & SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_MASK) >> \ - SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_SHIFT) - -#define SQ_HV_VMID_CTRL_GET_DEFAULT_VMID__VI(sq_hv_vmid_ctrl) \ - ((sq_hv_vmid_ctrl & SQ_HV_VMID_CTRL_DEFAULT_VMID_MASK) >> SQ_HV_VMID_CTRL_DEFAULT_VMID_SHIFT) - -#define SQ_HV_VMID_CTRL_MASK__VI \ - (SQ_HV_VMID_CTRL_DEFAULT_VMID_MASK | SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_MASK) - -#define SQ_HV_VMID_CTRL_SET_ALLOWED_VMID_MASK__VI(sq_hv_vmid_ctrl_reg, allowed_vmid_mask) \ - sq_hv_vmid_ctrl_reg = (sq_hv_vmid_ctrl_reg & ~SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_MASK) | \ - (allowed_vmid_mask << SQ_HV_VMID_CTRL_ALLOWED_VMID_MASK_SHIFT) - -#define SQ_HV_VMID_CTRL_SET_DEFAULT_VMID__VI(sq_hv_vmid_ctrl_reg, default_vmid) \ - sq_hv_vmid_ctrl_reg = (sq_hv_vmid_ctrl_reg & ~SQ_HV_VMID_CTRL_DEFAULT_VMID_MASK) | \ - (default_vmid << SQ_HV_VMID_CTRL_DEFAULT_VMID_SHIFT) - -#define SQ_IMG_RSRC_WORD0_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD0_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_RSRC_WORD0_GET_BASE_ADDRESS__VI(sq_img_rsrc_word0) \ - ((sq_img_rsrc_word0 & SQ_IMG_RSRC_WORD0_BASE_ADDRESS_MASK) >> \ - SQ_IMG_RSRC_WORD0_BASE_ADDRESS_SHIFT) - -#define SQ_IMG_RSRC_WORD0_MASK__VI (SQ_IMG_RSRC_WORD0_BASE_ADDRESS_MASK) - -#define SQ_IMG_RSRC_WORD0_SET_BASE_ADDRESS__VI(sq_img_rsrc_word0_reg, base_address) \ - sq_img_rsrc_word0_reg = (sq_img_rsrc_word0_reg & ~SQ_IMG_RSRC_WORD0_BASE_ADDRESS_MASK) | \ - (base_address << SQ_IMG_RSRC_WORD0_BASE_ADDRESS_SHIFT) - -#define SQ_IMG_RSRC_WORD1_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD1_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_RSRC_WORD1_GET_BASE_ADDRESS_HI__VI(sq_img_rsrc_word1) \ - ((sq_img_rsrc_word1 & SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_MASK) >> \ - SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_SHIFT) - -#define SQ_IMG_RSRC_WORD1_GET_DATA_FORMAT__VI(sq_img_rsrc_word1) \ - ((sq_img_rsrc_word1 & SQ_IMG_RSRC_WORD1_DATA_FORMAT_MASK) >> SQ_IMG_RSRC_WORD1_DATA_FORMAT_SHIFT) - -#define SQ_IMG_RSRC_WORD1_GET_MIN_LOD__VI(sq_img_rsrc_word1) \ - ((sq_img_rsrc_word1 & SQ_IMG_RSRC_WORD1_MIN_LOD_MASK) >> SQ_IMG_RSRC_WORD1_MIN_LOD_SHIFT) - -#define SQ_IMG_RSRC_WORD1_GET_MTYPE__VI(sq_img_rsrc_word1) \ - ((sq_img_rsrc_word1 & SQ_IMG_RSRC_WORD1_MTYPE_MASK) >> SQ_IMG_RSRC_WORD1_MTYPE_SHIFT) - -#define SQ_IMG_RSRC_WORD1_GET_NUM_FORMAT__VI(sq_img_rsrc_word1) \ - ((sq_img_rsrc_word1 & SQ_IMG_RSRC_WORD1_NUM_FORMAT_MASK) >> SQ_IMG_RSRC_WORD1_NUM_FORMAT_SHIFT) - -#define SQ_IMG_RSRC_WORD1_MASK__VI \ - (SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_MASK | SQ_IMG_RSRC_WORD1_MIN_LOD_MASK | \ - SQ_IMG_RSRC_WORD1_DATA_FORMAT_MASK | SQ_IMG_RSRC_WORD1_NUM_FORMAT_MASK | \ - SQ_IMG_RSRC_WORD1_MTYPE_MASK) - -#define SQ_IMG_RSRC_WORD1_SET_BASE_ADDRESS_HI__VI(sq_img_rsrc_word1_reg, base_address_hi) \ - sq_img_rsrc_word1_reg = (sq_img_rsrc_word1_reg & ~SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_MASK) | \ - (base_address_hi << SQ_IMG_RSRC_WORD1_BASE_ADDRESS_HI_SHIFT) - -#define SQ_IMG_RSRC_WORD1_SET_DATA_FORMAT__VI(sq_img_rsrc_word1_reg, data_format) \ - sq_img_rsrc_word1_reg = (sq_img_rsrc_word1_reg & ~SQ_IMG_RSRC_WORD1_DATA_FORMAT_MASK) | \ - (data_format << SQ_IMG_RSRC_WORD1_DATA_FORMAT_SHIFT) - -#define SQ_IMG_RSRC_WORD1_SET_MIN_LOD__VI(sq_img_rsrc_word1_reg, min_lod) \ - sq_img_rsrc_word1_reg = (sq_img_rsrc_word1_reg & ~SQ_IMG_RSRC_WORD1_MIN_LOD_MASK) | \ - (min_lod << SQ_IMG_RSRC_WORD1_MIN_LOD_SHIFT) - -#define SQ_IMG_RSRC_WORD1_SET_MTYPE__VI(sq_img_rsrc_word1_reg, mtype) \ - sq_img_rsrc_word1_reg = (sq_img_rsrc_word1_reg & ~SQ_IMG_RSRC_WORD1_MTYPE_MASK) | \ - (mtype << SQ_IMG_RSRC_WORD1_MTYPE_SHIFT) - -#define SQ_IMG_RSRC_WORD1_SET_NUM_FORMAT__VI(sq_img_rsrc_word1_reg, num_format) \ - sq_img_rsrc_word1_reg = (sq_img_rsrc_word1_reg & ~SQ_IMG_RSRC_WORD1_NUM_FORMAT_MASK) | \ - (num_format << SQ_IMG_RSRC_WORD1_NUM_FORMAT_SHIFT) - -#define SQ_IMG_RSRC_WORD2_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD2_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_RSRC_WORD2_GET_HEIGHT__VI(sq_img_rsrc_word2) \ - ((sq_img_rsrc_word2 & SQ_IMG_RSRC_WORD2_HEIGHT_MASK) >> SQ_IMG_RSRC_WORD2_HEIGHT_SHIFT) - -#define SQ_IMG_RSRC_WORD2_GET_INTERLACED__VI(sq_img_rsrc_word2) \ - ((sq_img_rsrc_word2 & SQ_IMG_RSRC_WORD2_INTERLACED_MASK) >> SQ_IMG_RSRC_WORD2_INTERLACED_SHIFT) - -#define SQ_IMG_RSRC_WORD2_GET_PERF_MOD__VI(sq_img_rsrc_word2) \ - ((sq_img_rsrc_word2 & SQ_IMG_RSRC_WORD2_PERF_MOD_MASK) >> SQ_IMG_RSRC_WORD2_PERF_MOD_SHIFT) - -#define SQ_IMG_RSRC_WORD2_GET_WIDTH__VI(sq_img_rsrc_word2) \ - ((sq_img_rsrc_word2 & SQ_IMG_RSRC_WORD2_WIDTH_MASK) >> SQ_IMG_RSRC_WORD2_WIDTH_SHIFT) - -#define SQ_IMG_RSRC_WORD2_MASK__VI \ - (SQ_IMG_RSRC_WORD2_WIDTH_MASK | SQ_IMG_RSRC_WORD2_HEIGHT_MASK | \ - SQ_IMG_RSRC_WORD2_PERF_MOD_MASK | SQ_IMG_RSRC_WORD2_INTERLACED_MASK) - -#define SQ_IMG_RSRC_WORD2_SET_HEIGHT__VI(sq_img_rsrc_word2_reg, height) \ - sq_img_rsrc_word2_reg = (sq_img_rsrc_word2_reg & ~SQ_IMG_RSRC_WORD2_HEIGHT_MASK) | \ - (height << SQ_IMG_RSRC_WORD2_HEIGHT_SHIFT) - -#define SQ_IMG_RSRC_WORD2_SET_INTERLACED__VI(sq_img_rsrc_word2_reg, interlaced) \ - sq_img_rsrc_word2_reg = (sq_img_rsrc_word2_reg & ~SQ_IMG_RSRC_WORD2_INTERLACED_MASK) | \ - (interlaced << SQ_IMG_RSRC_WORD2_INTERLACED_SHIFT) - -#define SQ_IMG_RSRC_WORD2_SET_PERF_MOD__VI(sq_img_rsrc_word2_reg, perf_mod) \ - sq_img_rsrc_word2_reg = (sq_img_rsrc_word2_reg & ~SQ_IMG_RSRC_WORD2_PERF_MOD_MASK) | \ - (perf_mod << SQ_IMG_RSRC_WORD2_PERF_MOD_SHIFT) - -#define SQ_IMG_RSRC_WORD2_SET_WIDTH__VI(sq_img_rsrc_word2_reg, width) \ - sq_img_rsrc_word2_reg = (sq_img_rsrc_word2_reg & ~SQ_IMG_RSRC_WORD2_WIDTH_MASK) | \ - (width << SQ_IMG_RSRC_WORD2_WIDTH_SHIFT) - -#define SQ_IMG_RSRC_WORD3_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD3_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_RSRC_WORD3_GET_ATC__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_ATC_MASK) >> SQ_IMG_RSRC_WORD3_ATC_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_BASE_LEVEL__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_BASE_LEVEL_MASK) >> SQ_IMG_RSRC_WORD3_BASE_LEVEL_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_DST_SEL_W__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_DST_SEL_W_MASK) >> SQ_IMG_RSRC_WORD3_DST_SEL_W_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_DST_SEL_X__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_DST_SEL_X_MASK) >> SQ_IMG_RSRC_WORD3_DST_SEL_X_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_DST_SEL_Y__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_DST_SEL_Y_MASK) >> SQ_IMG_RSRC_WORD3_DST_SEL_Y_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_DST_SEL_Z__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_DST_SEL_Z_MASK) >> SQ_IMG_RSRC_WORD3_DST_SEL_Z_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_LAST_LEVEL__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_LAST_LEVEL_MASK) >> SQ_IMG_RSRC_WORD3_LAST_LEVEL_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_MTYPE__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_MTYPE_MASK) >> SQ_IMG_RSRC_WORD3_MTYPE_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_POW2_PAD__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_POW2_PAD_MASK) >> SQ_IMG_RSRC_WORD3_POW2_PAD_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_TILING_INDEX__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_TILING_INDEX_MASK) >> \ - SQ_IMG_RSRC_WORD3_TILING_INDEX_SHIFT) - -#define SQ_IMG_RSRC_WORD3_GET_TYPE__VI(sq_img_rsrc_word3) \ - ((sq_img_rsrc_word3 & SQ_IMG_RSRC_WORD3_TYPE_MASK) >> SQ_IMG_RSRC_WORD3_TYPE_SHIFT) - -#define SQ_IMG_RSRC_WORD3_MASK__VI \ - (SQ_IMG_RSRC_WORD3_DST_SEL_X_MASK | SQ_IMG_RSRC_WORD3_DST_SEL_Y_MASK | \ - SQ_IMG_RSRC_WORD3_DST_SEL_Z_MASK | SQ_IMG_RSRC_WORD3_DST_SEL_W_MASK | \ - SQ_IMG_RSRC_WORD3_BASE_LEVEL_MASK | SQ_IMG_RSRC_WORD3_LAST_LEVEL_MASK | \ - SQ_IMG_RSRC_WORD3_TILING_INDEX_MASK | SQ_IMG_RSRC_WORD3_POW2_PAD_MASK | \ - SQ_IMG_RSRC_WORD3_MTYPE_MASK | SQ_IMG_RSRC_WORD3_ATC_MASK | SQ_IMG_RSRC_WORD3_TYPE_MASK) - -#define SQ_IMG_RSRC_WORD3_SET_ATC__VI(sq_img_rsrc_word3_reg, atc) \ - sq_img_rsrc_word3_reg = \ - (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_ATC_MASK) | (atc << SQ_IMG_RSRC_WORD3_ATC_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_BASE_LEVEL__VI(sq_img_rsrc_word3_reg, base_level) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_BASE_LEVEL_MASK) | \ - (base_level << SQ_IMG_RSRC_WORD3_BASE_LEVEL_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_DST_SEL_W__VI(sq_img_rsrc_word3_reg, dst_sel_w) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_DST_SEL_W_MASK) | \ - (dst_sel_w << SQ_IMG_RSRC_WORD3_DST_SEL_W_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_DST_SEL_X__VI(sq_img_rsrc_word3_reg, dst_sel_x) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_DST_SEL_X_MASK) | \ - (dst_sel_x << SQ_IMG_RSRC_WORD3_DST_SEL_X_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_DST_SEL_Y__VI(sq_img_rsrc_word3_reg, dst_sel_y) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_DST_SEL_Y_MASK) | \ - (dst_sel_y << SQ_IMG_RSRC_WORD3_DST_SEL_Y_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_DST_SEL_Z__VI(sq_img_rsrc_word3_reg, dst_sel_z) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_DST_SEL_Z_MASK) | \ - (dst_sel_z << SQ_IMG_RSRC_WORD3_DST_SEL_Z_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_LAST_LEVEL__VI(sq_img_rsrc_word3_reg, last_level) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_LAST_LEVEL_MASK) | \ - (last_level << SQ_IMG_RSRC_WORD3_LAST_LEVEL_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_MTYPE__VI(sq_img_rsrc_word3_reg, mtype) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_MTYPE_MASK) | \ - (mtype << SQ_IMG_RSRC_WORD3_MTYPE_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_POW2_PAD__VI(sq_img_rsrc_word3_reg, pow2_pad) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_POW2_PAD_MASK) | \ - (pow2_pad << SQ_IMG_RSRC_WORD3_POW2_PAD_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_TILING_INDEX__VI(sq_img_rsrc_word3_reg, tiling_index) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_TILING_INDEX_MASK) | \ - (tiling_index << SQ_IMG_RSRC_WORD3_TILING_INDEX_SHIFT) - -#define SQ_IMG_RSRC_WORD3_SET_TYPE__VI(sq_img_rsrc_word3_reg, type) \ - sq_img_rsrc_word3_reg = (sq_img_rsrc_word3_reg & ~SQ_IMG_RSRC_WORD3_TYPE_MASK) | \ - (type << SQ_IMG_RSRC_WORD3_TYPE_SHIFT) - -#define SQ_IMG_RSRC_WORD4_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD4_DEFAULT__VI 0x05cdcdcd -#define SQ_IMG_RSRC_WORD4_GET_DEPTH__VI(sq_img_rsrc_word4) \ - ((sq_img_rsrc_word4 & SQ_IMG_RSRC_WORD4_DEPTH_MASK) >> SQ_IMG_RSRC_WORD4_DEPTH_SHIFT) - -#define SQ_IMG_RSRC_WORD4_GET_PITCH__VI(sq_img_rsrc_word4) \ - ((sq_img_rsrc_word4 & SQ_IMG_RSRC_WORD4_PITCH_MASK) >> SQ_IMG_RSRC_WORD4_PITCH_SHIFT) - -#define SQ_IMG_RSRC_WORD4_MASK__VI (SQ_IMG_RSRC_WORD4_DEPTH_MASK | SQ_IMG_RSRC_WORD4_PITCH_MASK) - -#define SQ_IMG_RSRC_WORD4_SET_DEPTH__VI(sq_img_rsrc_word4_reg, depth) \ - sq_img_rsrc_word4_reg = (sq_img_rsrc_word4_reg & ~SQ_IMG_RSRC_WORD4_DEPTH_MASK) | \ - (depth << SQ_IMG_RSRC_WORD4_DEPTH_SHIFT) - -#define SQ_IMG_RSRC_WORD4_SET_PITCH__VI(sq_img_rsrc_word4_reg, pitch) \ - sq_img_rsrc_word4_reg = (sq_img_rsrc_word4_reg & ~SQ_IMG_RSRC_WORD4_PITCH_MASK) | \ - (pitch << SQ_IMG_RSRC_WORD4_PITCH_SHIFT) - -#define SQ_IMG_RSRC_WORD5_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD5_DEFAULT__VI 0x01cdcdcd -#define SQ_IMG_RSRC_WORD5_GET_BASE_ARRAY__VI(sq_img_rsrc_word5) \ - ((sq_img_rsrc_word5 & SQ_IMG_RSRC_WORD5_BASE_ARRAY_MASK) >> SQ_IMG_RSRC_WORD5_BASE_ARRAY_SHIFT) - -#define SQ_IMG_RSRC_WORD5_GET_LAST_ARRAY__VI(sq_img_rsrc_word5) \ - ((sq_img_rsrc_word5 & SQ_IMG_RSRC_WORD5_LAST_ARRAY_MASK) >> SQ_IMG_RSRC_WORD5_LAST_ARRAY_SHIFT) - -#define SQ_IMG_RSRC_WORD5_MASK__VI \ - (SQ_IMG_RSRC_WORD5_BASE_ARRAY_MASK | SQ_IMG_RSRC_WORD5_LAST_ARRAY_MASK) - -#define SQ_IMG_RSRC_WORD5_SET_BASE_ARRAY__VI(sq_img_rsrc_word5_reg, base_array) \ - sq_img_rsrc_word5_reg = (sq_img_rsrc_word5_reg & ~SQ_IMG_RSRC_WORD5_BASE_ARRAY_MASK) | \ - (base_array << SQ_IMG_RSRC_WORD5_BASE_ARRAY_SHIFT) - -#define SQ_IMG_RSRC_WORD5_SET_LAST_ARRAY__VI(sq_img_rsrc_word5_reg, last_array) \ - sq_img_rsrc_word5_reg = (sq_img_rsrc_word5_reg & ~SQ_IMG_RSRC_WORD5_LAST_ARRAY_MASK) | \ - (last_array << SQ_IMG_RSRC_WORD5_LAST_ARRAY_SHIFT) - -#define SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_MASK__VI 0x00400000 -#define SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_SHIFT__VI 22 -#define SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_SIZE__VI 1 -#define SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_MASK__VI 0x00800000 -#define SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_SHIFT__VI 23 -#define SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_SIZE__VI 1 -#define SQ_IMG_RSRC_WORD6_COMPRESSION_EN_MASK__VI 0x00200000 -#define SQ_IMG_RSRC_WORD6_COMPRESSION_EN_SHIFT__VI 21 -#define SQ_IMG_RSRC_WORD6_COMPRESSION_EN_SIZE__VI 1 -#define SQ_IMG_RSRC_WORD6_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD6_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_RSRC_WORD6_GET_ALPHA_IS_ON_MSB__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_MASK) >> \ - SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_SHIFT) - -#define SQ_IMG_RSRC_WORD6_GET_COLOR_TRANSFORM__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_MASK) >> \ - SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_SHIFT) - -#define SQ_IMG_RSRC_WORD6_GET_COMPRESSION_EN__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_COMPRESSION_EN_MASK) >> \ - SQ_IMG_RSRC_WORD6_COMPRESSION_EN_SHIFT) - -#define SQ_IMG_RSRC_WORD6_GET_COUNTER_BANK_ID__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_MASK) >> \ - SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_SHIFT) - -#define SQ_IMG_RSRC_WORD6_GET_LOD_HDW_CNT_EN__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_MASK) >> \ - SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_SHIFT) - -#define SQ_IMG_RSRC_WORD6_GET_LOST_ALPHA_BITS__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_MASK) >> \ - SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_SHIFT) - -#define SQ_IMG_RSRC_WORD6_GET_LOST_COLOR_BITS__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_MASK) >> \ - SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_SHIFT) - -#define SQ_IMG_RSRC_WORD6_GET_MIN_LOD_WARN__VI(sq_img_rsrc_word6) \ - ((sq_img_rsrc_word6 & SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_MASK) >> \ - SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_SHIFT) - -#define SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_MASK__VI 0x0f000000 -#define SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_SHIFT__VI 24 -#define SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_SIZE__VI 4 -#define SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_MASK__VI 0xf0000000 -#define SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_SHIFT__VI 28 -#define SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_SIZE__VI 4 -#define SQ_IMG_RSRC_WORD6_MASK__VI \ - (SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_MASK | SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_MASK | \ - SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_MASK | SQ_IMG_RSRC_WORD6_COMPRESSION_EN_MASK | \ - SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_MASK | SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_MASK | \ - SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_MASK | SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_MASK) - -#define SQ_IMG_RSRC_WORD6_SET_ALPHA_IS_ON_MSB__VI(sq_img_rsrc_word6_reg, alpha_is_on_msb) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_MASK) | \ - (alpha_is_on_msb << SQ_IMG_RSRC_WORD6_ALPHA_IS_ON_MSB_SHIFT) - -#define SQ_IMG_RSRC_WORD6_SET_COLOR_TRANSFORM__VI(sq_img_rsrc_word6_reg, color_transform) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_MASK) | \ - (color_transform << SQ_IMG_RSRC_WORD6_COLOR_TRANSFORM_SHIFT) - -#define SQ_IMG_RSRC_WORD6_SET_COMPRESSION_EN__VI(sq_img_rsrc_word6_reg, compression_en) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_COMPRESSION_EN_MASK) | \ - (compression_en << SQ_IMG_RSRC_WORD6_COMPRESSION_EN_SHIFT) - -#define SQ_IMG_RSRC_WORD6_SET_COUNTER_BANK_ID__VI(sq_img_rsrc_word6_reg, counter_bank_id) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_MASK) | \ - (counter_bank_id << SQ_IMG_RSRC_WORD6_COUNTER_BANK_ID_SHIFT) - -#define SQ_IMG_RSRC_WORD6_SET_LOD_HDW_CNT_EN__VI(sq_img_rsrc_word6_reg, lod_hdw_cnt_en) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_MASK) | \ - (lod_hdw_cnt_en << SQ_IMG_RSRC_WORD6_LOD_HDW_CNT_EN_SHIFT) - -#define SQ_IMG_RSRC_WORD6_SET_LOST_ALPHA_BITS__VI(sq_img_rsrc_word6_reg, lost_alpha_bits) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_MASK) | \ - (lost_alpha_bits << SQ_IMG_RSRC_WORD6_LOST_ALPHA_BITS_SHIFT) - -#define SQ_IMG_RSRC_WORD6_SET_LOST_COLOR_BITS__VI(sq_img_rsrc_word6_reg, lost_color_bits) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_MASK) | \ - (lost_color_bits << SQ_IMG_RSRC_WORD6_LOST_COLOR_BITS_SHIFT) - -#define SQ_IMG_RSRC_WORD6_SET_MIN_LOD_WARN__VI(sq_img_rsrc_word6_reg, min_lod_warn) \ - sq_img_rsrc_word6_reg = (sq_img_rsrc_word6_reg & ~SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_MASK) | \ - (min_lod_warn << SQ_IMG_RSRC_WORD6_MIN_LOD_WARN_SHIFT) - -#define SQ_IMG_RSRC_WORD7_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_RSRC_WORD7_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_RSRC_WORD7_GET_META_DATA_ADDRESS__VI(sq_img_rsrc_word7) \ - ((sq_img_rsrc_word7 & SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_MASK) >> \ - SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_SHIFT) - -#define SQ_IMG_RSRC_WORD7_MASK__VI (SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_MASK) - -#define SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_MASK__VI 0xffffffff -#define SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_SHIFT__VI 0x00000000 -#define SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_SIZE__VI 32 -#define SQ_IMG_RSRC_WORD7_SET_META_DATA_ADDRESS__VI(sq_img_rsrc_word7_reg, meta_data_address) \ - sq_img_rsrc_word7_reg = (sq_img_rsrc_word7_reg & ~SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_MASK) | \ - (meta_data_address << SQ_IMG_RSRC_WORD7_META_DATA_ADDRESS_SHIFT) - -#define SQ_IMG_SAMP_WORD0_COMPAT_MODE_MASK__VI 0x80000000 -#define SQ_IMG_SAMP_WORD0_COMPAT_MODE_SHIFT__VI 31 -#define SQ_IMG_SAMP_WORD0_COMPAT_MODE_SIZE__VI 1 -#define SQ_IMG_SAMP_WORD0_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_SAMP_WORD0_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_SAMP_WORD0_GET_ANISO_BIAS__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_ANISO_BIAS_MASK) >> SQ_IMG_SAMP_WORD0_ANISO_BIAS_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_ANISO_THRESHOLD__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_MASK) >> \ - SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_CLAMP_X__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_CLAMP_X_MASK) >> SQ_IMG_SAMP_WORD0_CLAMP_X_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_CLAMP_Y__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_CLAMP_Y_MASK) >> SQ_IMG_SAMP_WORD0_CLAMP_Y_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_CLAMP_Z__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_CLAMP_Z_MASK) >> SQ_IMG_SAMP_WORD0_CLAMP_Z_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_COMPAT_MODE__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_COMPAT_MODE_MASK) >> SQ_IMG_SAMP_WORD0_COMPAT_MODE_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_DEPTH_COMPARE_FUNC__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_MASK) >> \ - SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_DISABLE_CUBE_WRAP__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_MASK) >> \ - SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_FILTER_MODE__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_FILTER_MODE_MASK) >> SQ_IMG_SAMP_WORD0_FILTER_MODE_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_FORCE_DEGAMMA__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_MASK) >> \ - SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_FORCE_UNNORMALIZED__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_MASK) >> \ - SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_MAX_ANISO_RATIO__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_MASK) >> \ - SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_MC_COORD_TRUNC__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_MASK) >> \ - SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_SHIFT) - -#define SQ_IMG_SAMP_WORD0_GET_TRUNC_COORD__VI(sq_img_samp_word0) \ - ((sq_img_samp_word0 & SQ_IMG_SAMP_WORD0_TRUNC_COORD_MASK) >> SQ_IMG_SAMP_WORD0_TRUNC_COORD_SHIFT) - -#define SQ_IMG_SAMP_WORD0_MASK__VI \ - (SQ_IMG_SAMP_WORD0_CLAMP_X_MASK | SQ_IMG_SAMP_WORD0_CLAMP_Y_MASK | \ - SQ_IMG_SAMP_WORD0_CLAMP_Z_MASK | SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_MASK | \ - SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_MASK | SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_MASK | \ - SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_MASK | SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_MASK | \ - SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_MASK | SQ_IMG_SAMP_WORD0_ANISO_BIAS_MASK | \ - SQ_IMG_SAMP_WORD0_TRUNC_COORD_MASK | SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_MASK | \ - SQ_IMG_SAMP_WORD0_FILTER_MODE_MASK | SQ_IMG_SAMP_WORD0_COMPAT_MODE_MASK) - -#define SQ_IMG_SAMP_WORD0_SET_ANISO_BIAS__VI(sq_img_samp_word0_reg, aniso_bias) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_ANISO_BIAS_MASK) | \ - (aniso_bias << SQ_IMG_SAMP_WORD0_ANISO_BIAS_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_ANISO_THRESHOLD__VI(sq_img_samp_word0_reg, aniso_threshold) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_MASK) | \ - (aniso_threshold << SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_CLAMP_X__VI(sq_img_samp_word0_reg, clamp_x) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_CLAMP_X_MASK) | \ - (clamp_x << SQ_IMG_SAMP_WORD0_CLAMP_X_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_CLAMP_Y__VI(sq_img_samp_word0_reg, clamp_y) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_CLAMP_Y_MASK) | \ - (clamp_y << SQ_IMG_SAMP_WORD0_CLAMP_Y_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_CLAMP_Z__VI(sq_img_samp_word0_reg, clamp_z) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_CLAMP_Z_MASK) | \ - (clamp_z << SQ_IMG_SAMP_WORD0_CLAMP_Z_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_COMPAT_MODE__VI(sq_img_samp_word0_reg, compat_mode) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_COMPAT_MODE_MASK) | \ - (compat_mode << SQ_IMG_SAMP_WORD0_COMPAT_MODE_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_DEPTH_COMPARE_FUNC__VI(sq_img_samp_word0_reg, depth_compare_func) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_MASK) | \ - (depth_compare_func << SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_DISABLE_CUBE_WRAP__VI(sq_img_samp_word0_reg, disable_cube_wrap) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_MASK) | \ - (disable_cube_wrap << SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_FILTER_MODE__VI(sq_img_samp_word0_reg, filter_mode) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_FILTER_MODE_MASK) | \ - (filter_mode << SQ_IMG_SAMP_WORD0_FILTER_MODE_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_FORCE_DEGAMMA__VI(sq_img_samp_word0_reg, force_degamma) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_MASK) | \ - (force_degamma << SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_FORCE_UNNORMALIZED__VI(sq_img_samp_word0_reg, force_unnormalized) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_MASK) | \ - (force_unnormalized << SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_MAX_ANISO_RATIO__VI(sq_img_samp_word0_reg, max_aniso_ratio) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_MASK) | \ - (max_aniso_ratio << SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_MC_COORD_TRUNC__VI(sq_img_samp_word0_reg, mc_coord_trunc) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_MASK) | \ - (mc_coord_trunc << SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_SHIFT) - -#define SQ_IMG_SAMP_WORD0_SET_TRUNC_COORD__VI(sq_img_samp_word0_reg, trunc_coord) \ - sq_img_samp_word0_reg = (sq_img_samp_word0_reg & ~SQ_IMG_SAMP_WORD0_TRUNC_COORD_MASK) | \ - (trunc_coord << SQ_IMG_SAMP_WORD0_TRUNC_COORD_SHIFT) - -#define SQ_IMG_SAMP_WORD1_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_SAMP_WORD1_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_SAMP_WORD1_GET_MAX_LOD__VI(sq_img_samp_word1) \ - ((sq_img_samp_word1 & SQ_IMG_SAMP_WORD1_MAX_LOD_MASK) >> SQ_IMG_SAMP_WORD1_MAX_LOD_SHIFT) - -#define SQ_IMG_SAMP_WORD1_GET_MIN_LOD__VI(sq_img_samp_word1) \ - ((sq_img_samp_word1 & SQ_IMG_SAMP_WORD1_MIN_LOD_MASK) >> SQ_IMG_SAMP_WORD1_MIN_LOD_SHIFT) - -#define SQ_IMG_SAMP_WORD1_GET_PERF_MIP__VI(sq_img_samp_word1) \ - ((sq_img_samp_word1 & SQ_IMG_SAMP_WORD1_PERF_MIP_MASK) >> SQ_IMG_SAMP_WORD1_PERF_MIP_SHIFT) - -#define SQ_IMG_SAMP_WORD1_GET_PERF_Z__VI(sq_img_samp_word1) \ - ((sq_img_samp_word1 & SQ_IMG_SAMP_WORD1_PERF_Z_MASK) >> SQ_IMG_SAMP_WORD1_PERF_Z_SHIFT) - -#define SQ_IMG_SAMP_WORD1_MASK__VI \ - (SQ_IMG_SAMP_WORD1_MIN_LOD_MASK | SQ_IMG_SAMP_WORD1_MAX_LOD_MASK | \ - SQ_IMG_SAMP_WORD1_PERF_MIP_MASK | SQ_IMG_SAMP_WORD1_PERF_Z_MASK) - -#define SQ_IMG_SAMP_WORD1_SET_MAX_LOD__VI(sq_img_samp_word1_reg, max_lod) \ - sq_img_samp_word1_reg = (sq_img_samp_word1_reg & ~SQ_IMG_SAMP_WORD1_MAX_LOD_MASK) | \ - (max_lod << SQ_IMG_SAMP_WORD1_MAX_LOD_SHIFT) - -#define SQ_IMG_SAMP_WORD1_SET_MIN_LOD__VI(sq_img_samp_word1_reg, min_lod) \ - sq_img_samp_word1_reg = (sq_img_samp_word1_reg & ~SQ_IMG_SAMP_WORD1_MIN_LOD_MASK) | \ - (min_lod << SQ_IMG_SAMP_WORD1_MIN_LOD_SHIFT) - -#define SQ_IMG_SAMP_WORD1_SET_PERF_MIP__VI(sq_img_samp_word1_reg, perf_mip) \ - sq_img_samp_word1_reg = (sq_img_samp_word1_reg & ~SQ_IMG_SAMP_WORD1_PERF_MIP_MASK) | \ - (perf_mip << SQ_IMG_SAMP_WORD1_PERF_MIP_SHIFT) - -#define SQ_IMG_SAMP_WORD1_SET_PERF_Z__VI(sq_img_samp_word1_reg, perf_z) \ - sq_img_samp_word1_reg = (sq_img_samp_word1_reg & ~SQ_IMG_SAMP_WORD1_PERF_Z_MASK) | \ - (perf_z << SQ_IMG_SAMP_WORD1_PERF_Z_SHIFT) - -#define SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_MASK__VI 0x80000000 -#define SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_SHIFT__VI 31 -#define SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_SIZE__VI 1 -#define SQ_IMG_SAMP_WORD2_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_SAMP_WORD2_DEFAULT__VI 0xcdcdcdcd -#define SQ_IMG_SAMP_WORD2_GET_ANISO_OVERRIDE__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_MASK) >> \ - SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_DISABLE_LSB_CEIL__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_MASK) >> \ - SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_FILTER_PREC_FIX__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_MASK) >> \ - SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_LOD_BIAS__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_LOD_BIAS_MASK) >> SQ_IMG_SAMP_WORD2_LOD_BIAS_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_LOD_BIAS_SEC__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_MASK) >> \ - SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_MIP_FILTER__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_MIP_FILTER_MASK) >> SQ_IMG_SAMP_WORD2_MIP_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_MIP_POINT_PRECLAMP__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_MASK) >> \ - SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_XY_MAG_FILTER__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_MASK) >> \ - SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_XY_MIN_FILTER__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_MASK) >> \ - SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD2_GET_Z_FILTER__VI(sq_img_samp_word2) \ - ((sq_img_samp_word2 & SQ_IMG_SAMP_WORD2_Z_FILTER_MASK) >> SQ_IMG_SAMP_WORD2_Z_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD2_MASK__VI \ - (SQ_IMG_SAMP_WORD2_LOD_BIAS_MASK | SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_MASK | \ - SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_MASK | SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_MASK | \ - SQ_IMG_SAMP_WORD2_Z_FILTER_MASK | SQ_IMG_SAMP_WORD2_MIP_FILTER_MASK | \ - SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_MASK | SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_MASK | \ - SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_MASK | SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_MASK) - -#define SQ_IMG_SAMP_WORD2_SET_ANISO_OVERRIDE__VI(sq_img_samp_word2_reg, aniso_override) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_MASK) | \ - (aniso_override << SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_DISABLE_LSB_CEIL__VI(sq_img_samp_word2_reg, disable_lsb_ceil) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_MASK) | \ - (disable_lsb_ceil << SQ_IMG_SAMP_WORD2_DISABLE_LSB_CEIL_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_FILTER_PREC_FIX__VI(sq_img_samp_word2_reg, filter_prec_fix) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_MASK) | \ - (filter_prec_fix << SQ_IMG_SAMP_WORD2_FILTER_PREC_FIX_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_LOD_BIAS__VI(sq_img_samp_word2_reg, lod_bias) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_LOD_BIAS_MASK) | \ - (lod_bias << SQ_IMG_SAMP_WORD2_LOD_BIAS_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_LOD_BIAS_SEC__VI(sq_img_samp_word2_reg, lod_bias_sec) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_MASK) | \ - (lod_bias_sec << SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_MIP_FILTER__VI(sq_img_samp_word2_reg, mip_filter) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_MIP_FILTER_MASK) | \ - (mip_filter << SQ_IMG_SAMP_WORD2_MIP_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_MIP_POINT_PRECLAMP__VI(sq_img_samp_word2_reg, mip_point_preclamp) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_MASK) | \ - (mip_point_preclamp << SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_XY_MAG_FILTER__VI(sq_img_samp_word2_reg, xy_mag_filter) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_MASK) | \ - (xy_mag_filter << SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_XY_MIN_FILTER__VI(sq_img_samp_word2_reg, xy_min_filter) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_MASK) | \ - (xy_min_filter << SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD2_SET_Z_FILTER__VI(sq_img_samp_word2_reg, z_filter) \ - sq_img_samp_word2_reg = (sq_img_samp_word2_reg & ~SQ_IMG_SAMP_WORD2_Z_FILTER_MASK) | \ - (z_filter << SQ_IMG_SAMP_WORD2_Z_FILTER_SHIFT) - -#define SQ_IMG_SAMP_WORD3_DEFAULT__SI__CI 0x00000000 -#define SQ_IMG_SAMP_WORD3_DEFAULT__VI 0xc0000dcd -#define SQ_IMG_SAMP_WORD3_GET_BORDER_COLOR_PTR__VI(sq_img_samp_word3) \ - ((sq_img_samp_word3 & SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_MASK) >> \ - SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_SHIFT) - -#define SQ_IMG_SAMP_WORD3_GET_BORDER_COLOR_TYPE__VI(sq_img_samp_word3) \ - ((sq_img_samp_word3 & SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_MASK) >> \ - SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_SHIFT) - -#define SQ_IMG_SAMP_WORD3_MASK__VI \ - (SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_MASK | SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_MASK) - -#define SQ_IMG_SAMP_WORD3_SET_BORDER_COLOR_PTR__VI(sq_img_samp_word3_reg, border_color_ptr) \ - sq_img_samp_word3_reg = (sq_img_samp_word3_reg & ~SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_MASK) | \ - (border_color_ptr << SQ_IMG_SAMP_WORD3_BORDER_COLOR_PTR_SHIFT) - -#define SQ_IMG_SAMP_WORD3_SET_BORDER_COLOR_TYPE__VI(sq_img_samp_word3_reg, border_color_type) \ - sq_img_samp_word3_reg = (sq_img_samp_word3_reg & ~SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_MASK) | \ - (border_color_type << SQ_IMG_SAMP_WORD3_BORDER_COLOR_TYPE_SHIFT) - -#define SQ_IND_DATA_DEFAULT__SI__CI 0x00000000 -#define SQ_IND_DATA_DEFAULT__VI 0xcdcdcdcd -#define SQ_IND_DATA_GET_DATA__VI(sq_ind_data) \ - ((sq_ind_data & SQ_IND_DATA_DATA_MASK) >> SQ_IND_DATA_DATA_SHIFT) - -#define SQ_IND_DATA_MASK__VI (SQ_IND_DATA_DATA_MASK) - -#define SQ_IND_DATA_SET_DATA__VI(sq_ind_data_reg, data) \ - sq_ind_data_reg = (sq_ind_data_reg & ~SQ_IND_DATA_DATA_MASK) | (data << SQ_IND_DATA_DATA_SHIFT) - -#define SQ_IND_INDEX_GET_AUTO_INCR__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_AUTO_INCR_MASK) >> SQ_IND_INDEX_AUTO_INCR_SHIFT) - -#define SQ_IND_INDEX_GET_FORCE_READ__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_FORCE_READ_MASK) >> SQ_IND_INDEX_FORCE_READ_SHIFT) - -#define SQ_IND_INDEX_GET_INDEX__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_INDEX_MASK) >> SQ_IND_INDEX_INDEX_SHIFT) - -#define SQ_IND_INDEX_GET_READ_TIMEOUT__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_READ_TIMEOUT_MASK) >> SQ_IND_INDEX_READ_TIMEOUT_SHIFT) - -#define SQ_IND_INDEX_GET_SIMD_ID__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_SIMD_ID_MASK) >> SQ_IND_INDEX_SIMD_ID_SHIFT) - -#define SQ_IND_INDEX_GET_THREAD_ID__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_THREAD_ID_MASK) >> SQ_IND_INDEX_THREAD_ID_SHIFT) - -#define SQ_IND_INDEX_GET_UNINDEXED__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_UNINDEXED_MASK) >> SQ_IND_INDEX_UNINDEXED_SHIFT) - -#define SQ_IND_INDEX_GET_WAVE_ID__VI(sq_ind_index) \ - ((sq_ind_index & SQ_IND_INDEX_WAVE_ID_MASK) >> SQ_IND_INDEX_WAVE_ID_SHIFT) - -#define SQ_IND_INDEX_MASK__VI \ - (SQ_IND_INDEX_WAVE_ID_MASK | SQ_IND_INDEX_SIMD_ID_MASK | SQ_IND_INDEX_THREAD_ID_MASK | \ - SQ_IND_INDEX_AUTO_INCR_MASK | SQ_IND_INDEX_FORCE_READ_MASK | SQ_IND_INDEX_READ_TIMEOUT_MASK | \ - SQ_IND_INDEX_UNINDEXED_MASK | SQ_IND_INDEX_INDEX_MASK) - -#define SQ_IND_INDEX_SET_AUTO_INCR__VI(sq_ind_index_reg, auto_incr) \ - sq_ind_index_reg = (sq_ind_index_reg & ~SQ_IND_INDEX_AUTO_INCR_MASK) | \ - (auto_incr << SQ_IND_INDEX_AUTO_INCR_SHIFT) - -#define SQ_IND_INDEX_SET_FORCE_READ__VI(sq_ind_index_reg, force_read) \ - sq_ind_index_reg = (sq_ind_index_reg & ~SQ_IND_INDEX_FORCE_READ_MASK) | \ - (force_read << SQ_IND_INDEX_FORCE_READ_SHIFT) - -#define SQ_IND_INDEX_SET_INDEX__VI(sq_ind_index_reg, index) \ - sq_ind_index_reg = \ - (sq_ind_index_reg & ~SQ_IND_INDEX_INDEX_MASK) | (index << SQ_IND_INDEX_INDEX_SHIFT) - -#define SQ_IND_INDEX_SET_READ_TIMEOUT__VI(sq_ind_index_reg, read_timeout) \ - sq_ind_index_reg = (sq_ind_index_reg & ~SQ_IND_INDEX_READ_TIMEOUT_MASK) | \ - (read_timeout << SQ_IND_INDEX_READ_TIMEOUT_SHIFT) - -#define SQ_IND_INDEX_SET_SIMD_ID__VI(sq_ind_index_reg, simd_id) \ - sq_ind_index_reg = \ - (sq_ind_index_reg & ~SQ_IND_INDEX_SIMD_ID_MASK) | (simd_id << SQ_IND_INDEX_SIMD_ID_SHIFT) - -#define SQ_IND_INDEX_SET_THREAD_ID__VI(sq_ind_index_reg, thread_id) \ - sq_ind_index_reg = (sq_ind_index_reg & ~SQ_IND_INDEX_THREAD_ID_MASK) | \ - (thread_id << SQ_IND_INDEX_THREAD_ID_SHIFT) - -#define SQ_IND_INDEX_SET_UNINDEXED__VI(sq_ind_index_reg, unindexed) \ - sq_ind_index_reg = (sq_ind_index_reg & ~SQ_IND_INDEX_UNINDEXED_MASK) | \ - (unindexed << SQ_IND_INDEX_UNINDEXED_SHIFT) - -#define SQ_IND_INDEX_SET_WAVE_ID__VI(sq_ind_index_reg, wave_id) \ - sq_ind_index_reg = \ - (sq_ind_index_reg & ~SQ_IND_INDEX_WAVE_ID_MASK) | (wave_id << SQ_IND_INDEX_WAVE_ID_SHIFT) - -#define SQ_INTERRUPT_AUTO_MASK_GET_MASK__VI(sq_interrupt_auto_mask) \ - ((sq_interrupt_auto_mask & SQ_INTERRUPT_AUTO_MASK_MASK_MASK) >> SQ_INTERRUPT_AUTO_MASK_MASK_SHIFT) - -#define SQ_INTERRUPT_AUTO_MASK_MASK__VI (SQ_INTERRUPT_AUTO_MASK_MASK_MASK) - -#define SQ_INTERRUPT_AUTO_MASK_SET_MASK__VI(sq_interrupt_auto_mask_reg, mask) \ - sq_interrupt_auto_mask_reg = (sq_interrupt_auto_mask_reg & ~SQ_INTERRUPT_AUTO_MASK_MASK_MASK) | \ - (mask << SQ_INTERRUPT_AUTO_MASK_MASK_SHIFT) - -#define SQ_INTERRUPT_MSG_CTRL_GET_STALL__VI(sq_interrupt_msg_ctrl) \ - ((sq_interrupt_msg_ctrl & SQ_INTERRUPT_MSG_CTRL_STALL_MASK) >> SQ_INTERRUPT_MSG_CTRL_STALL_SHIFT) - -#define SQ_INTERRUPT_MSG_CTRL_MASK__VI (SQ_INTERRUPT_MSG_CTRL_STALL_MASK) - -#define SQ_INTERRUPT_MSG_CTRL_SET_STALL__VI(sq_interrupt_msg_ctrl_reg, stall) \ - sq_interrupt_msg_ctrl_reg = (sq_interrupt_msg_ctrl_reg & ~SQ_INTERRUPT_MSG_CTRL_STALL_MASK) | \ - (stall << SQ_INTERRUPT_MSG_CTRL_STALL_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_DEFAULT__SI__CI 0x00000000 -#define SQ_INTERRUPT_WORD_AUTO_DEFAULT__VI 0x0d0000cd -#define SQ_INTERRUPT_WORD_AUTO_GET_CMD_TIMESTAMP__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_ENCODING__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_ENCODING_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_ENCODING_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_HOST_CMD_OVERFLOW__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_HOST_REG_OVERFLOW__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_IMMED_OVERFLOW__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_REG_TIMESTAMP__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_SE_ID__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_SE_ID_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_SE_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_THREAD_TRACE__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_THREAD_TRACE_BUF_FULL__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_MASK) >> \ - SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_GET_WLT__VI(sq_interrupt_word_auto) \ - ((sq_interrupt_word_auto & SQ_INTERRUPT_WORD_AUTO_WLT_MASK) >> SQ_INTERRUPT_WORD_AUTO_WLT_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_MASK__VI \ - (SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_MASK | SQ_INTERRUPT_WORD_AUTO_WLT_MASK | \ - SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_MASK | SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_MASK | \ - SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_MASK | SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_MASK | \ - SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_MASK | SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_MASK | \ - SQ_INTERRUPT_WORD_AUTO_SE_ID_MASK | SQ_INTERRUPT_WORD_AUTO_ENCODING_MASK) - -#define SQ_INTERRUPT_WORD_AUTO_SET_CMD_TIMESTAMP__VI(sq_interrupt_word_auto_reg, cmd_timestamp) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_MASK) | \ - (cmd_timestamp << SQ_INTERRUPT_WORD_AUTO_CMD_TIMESTAMP_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_ENCODING__VI(sq_interrupt_word_auto_reg, encoding) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_ENCODING_MASK) | \ - (encoding << SQ_INTERRUPT_WORD_AUTO_ENCODING_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_HOST_CMD_OVERFLOW__VI(sq_interrupt_word_auto_reg, \ - host_cmd_overflow) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_MASK) | \ - (host_cmd_overflow << SQ_INTERRUPT_WORD_AUTO_HOST_CMD_OVERFLOW_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_HOST_REG_OVERFLOW__VI(sq_interrupt_word_auto_reg, \ - host_reg_overflow) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_MASK) | \ - (host_reg_overflow << SQ_INTERRUPT_WORD_AUTO_HOST_REG_OVERFLOW_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_IMMED_OVERFLOW__VI(sq_interrupt_word_auto_reg, immed_overflow) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_MASK) | \ - (immed_overflow << SQ_INTERRUPT_WORD_AUTO_IMMED_OVERFLOW_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_REG_TIMESTAMP__VI(sq_interrupt_word_auto_reg, reg_timestamp) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_MASK) | \ - (reg_timestamp << SQ_INTERRUPT_WORD_AUTO_REG_TIMESTAMP_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_SE_ID__VI(sq_interrupt_word_auto_reg, se_id) \ - sq_interrupt_word_auto_reg = (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_SE_ID_MASK) | \ - (se_id << SQ_INTERRUPT_WORD_AUTO_SE_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_THREAD_TRACE__VI(sq_interrupt_word_auto_reg, thread_trace) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_MASK) | \ - (thread_trace << SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_THREAD_TRACE_BUF_FULL__VI(sq_interrupt_word_auto_reg, \ - thread_trace_buf_full) \ - sq_interrupt_word_auto_reg = \ - (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_MASK) | \ - (thread_trace_buf_full << SQ_INTERRUPT_WORD_AUTO_THREAD_TRACE_BUF_FULL_SHIFT) - -#define SQ_INTERRUPT_WORD_AUTO_SET_WLT__VI(sq_interrupt_word_auto_reg, wlt) \ - sq_interrupt_word_auto_reg = (sq_interrupt_word_auto_reg & ~SQ_INTERRUPT_WORD_AUTO_WLT_MASK) | \ - (wlt << SQ_INTERRUPT_WORD_AUTO_WLT_SHIFT) - -#define SQ_INTERRUPT_WORD_CMN_DEFAULT__SI__CI 0x00000000 -#define SQ_INTERRUPT_WORD_CMN_DEFAULT__VI 0x0d000000 -#define SQ_INTERRUPT_WORD_CMN_GET_ENCODING__VI(sq_interrupt_word_cmn) \ - ((sq_interrupt_word_cmn & SQ_INTERRUPT_WORD_CMN_ENCODING_MASK) >> \ - SQ_INTERRUPT_WORD_CMN_ENCODING_SHIFT) - -#define SQ_INTERRUPT_WORD_CMN_GET_SE_ID__VI(sq_interrupt_word_cmn) \ - ((sq_interrupt_word_cmn & SQ_INTERRUPT_WORD_CMN_SE_ID_MASK) >> SQ_INTERRUPT_WORD_CMN_SE_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_CMN_MASK__VI \ - (SQ_INTERRUPT_WORD_CMN_SE_ID_MASK | SQ_INTERRUPT_WORD_CMN_ENCODING_MASK) - -#define SQ_INTERRUPT_WORD_CMN_SET_ENCODING__VI(sq_interrupt_word_cmn_reg, encoding) \ - sq_interrupt_word_cmn_reg = (sq_interrupt_word_cmn_reg & ~SQ_INTERRUPT_WORD_CMN_ENCODING_MASK) | \ - (encoding << SQ_INTERRUPT_WORD_CMN_ENCODING_SHIFT) - -#define SQ_INTERRUPT_WORD_CMN_SET_SE_ID__VI(sq_interrupt_word_cmn_reg, se_id) \ - sq_interrupt_word_cmn_reg = (sq_interrupt_word_cmn_reg & ~SQ_INTERRUPT_WORD_CMN_SE_ID_MASK) | \ - (se_id << SQ_INTERRUPT_WORD_CMN_SE_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_DEFAULT__SI__CI 0x00000000 -#define SQ_INTERRUPT_WORD_WAVE_DEFAULT__VI 0x0dcdcdcd -#define SQ_INTERRUPT_WORD_WAVE_GET_CU_ID__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_CU_ID_MASK) >> \ - SQ_INTERRUPT_WORD_WAVE_CU_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_DATA__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_DATA_MASK) >> SQ_INTERRUPT_WORD_WAVE_DATA_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_ENCODING__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_ENCODING_MASK) >> \ - SQ_INTERRUPT_WORD_WAVE_ENCODING_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_PRIV__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_PRIV_MASK) >> SQ_INTERRUPT_WORD_WAVE_PRIV_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_SE_ID__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_SE_ID_MASK) >> \ - SQ_INTERRUPT_WORD_WAVE_SE_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_SH_ID__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_SH_ID_MASK) >> \ - SQ_INTERRUPT_WORD_WAVE_SH_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_SIMD_ID__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_SIMD_ID_MASK) >> \ - SQ_INTERRUPT_WORD_WAVE_SIMD_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_VM_ID__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_VM_ID_MASK) >> \ - SQ_INTERRUPT_WORD_WAVE_VM_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_GET_WAVE_ID__VI(sq_interrupt_word_wave) \ - ((sq_interrupt_word_wave & SQ_INTERRUPT_WORD_WAVE_WAVE_ID_MASK) >> \ - SQ_INTERRUPT_WORD_WAVE_WAVE_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_MASK__VI \ - (SQ_INTERRUPT_WORD_WAVE_DATA_MASK | SQ_INTERRUPT_WORD_WAVE_SH_ID_MASK | \ - SQ_INTERRUPT_WORD_WAVE_PRIV_MASK | SQ_INTERRUPT_WORD_WAVE_VM_ID_MASK | \ - SQ_INTERRUPT_WORD_WAVE_WAVE_ID_MASK | SQ_INTERRUPT_WORD_WAVE_SIMD_ID_MASK | \ - SQ_INTERRUPT_WORD_WAVE_CU_ID_MASK | SQ_INTERRUPT_WORD_WAVE_SE_ID_MASK | \ - SQ_INTERRUPT_WORD_WAVE_ENCODING_MASK) - -#define SQ_INTERRUPT_WORD_WAVE_SET_CU_ID__VI(sq_interrupt_word_wave_reg, cu_id) \ - sq_interrupt_word_wave_reg = (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_CU_ID_MASK) | \ - (cu_id << SQ_INTERRUPT_WORD_WAVE_CU_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_DATA__VI(sq_interrupt_word_wave_reg, data) \ - sq_interrupt_word_wave_reg = (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_DATA_MASK) | \ - (data << SQ_INTERRUPT_WORD_WAVE_DATA_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_ENCODING__VI(sq_interrupt_word_wave_reg, encoding) \ - sq_interrupt_word_wave_reg = \ - (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_ENCODING_MASK) | \ - (encoding << SQ_INTERRUPT_WORD_WAVE_ENCODING_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_PRIV__VI(sq_interrupt_word_wave_reg, priv) \ - sq_interrupt_word_wave_reg = (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_PRIV_MASK) | \ - (priv << SQ_INTERRUPT_WORD_WAVE_PRIV_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_SE_ID__VI(sq_interrupt_word_wave_reg, se_id) \ - sq_interrupt_word_wave_reg = (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_SE_ID_MASK) | \ - (se_id << SQ_INTERRUPT_WORD_WAVE_SE_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_SH_ID__VI(sq_interrupt_word_wave_reg, sh_id) \ - sq_interrupt_word_wave_reg = (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_SH_ID_MASK) | \ - (sh_id << SQ_INTERRUPT_WORD_WAVE_SH_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_SIMD_ID__VI(sq_interrupt_word_wave_reg, simd_id) \ - sq_interrupt_word_wave_reg = \ - (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_SIMD_ID_MASK) | \ - (simd_id << SQ_INTERRUPT_WORD_WAVE_SIMD_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_VM_ID__VI(sq_interrupt_word_wave_reg, vm_id) \ - sq_interrupt_word_wave_reg = (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_VM_ID_MASK) | \ - (vm_id << SQ_INTERRUPT_WORD_WAVE_VM_ID_SHIFT) - -#define SQ_INTERRUPT_WORD_WAVE_SET_WAVE_ID__VI(sq_interrupt_word_wave_reg, wave_id) \ - sq_interrupt_word_wave_reg = \ - (sq_interrupt_word_wave_reg & ~SQ_INTERRUPT_WORD_WAVE_WAVE_ID_MASK) | \ - (wave_id << SQ_INTERRUPT_WORD_WAVE_WAVE_ID_SHIFT) - -#define SQ_LB_CTR_CTRL_GET_CLEAR__VI(sq_lb_ctr_ctrl) \ - ((sq_lb_ctr_ctrl & SQ_LB_CTR_CTRL_CLEAR_MASK) >> SQ_LB_CTR_CTRL_CLEAR_SHIFT) - -#define SQ_LB_CTR_CTRL_GET_LOAD__VI(sq_lb_ctr_ctrl) \ - ((sq_lb_ctr_ctrl & SQ_LB_CTR_CTRL_LOAD_MASK) >> SQ_LB_CTR_CTRL_LOAD_SHIFT) - -#define SQ_LB_CTR_CTRL_GET_START__VI(sq_lb_ctr_ctrl) \ - ((sq_lb_ctr_ctrl & SQ_LB_CTR_CTRL_START_MASK) >> SQ_LB_CTR_CTRL_START_SHIFT) - -#define SQ_LB_CTR_CTRL_MASK__VI \ - (SQ_LB_CTR_CTRL_START_MASK | SQ_LB_CTR_CTRL_LOAD_MASK | SQ_LB_CTR_CTRL_CLEAR_MASK) - -#define SQ_LB_CTR_CTRL_SET_CLEAR__VI(sq_lb_ctr_ctrl_reg, clear) \ - sq_lb_ctr_ctrl_reg = \ - (sq_lb_ctr_ctrl_reg & ~SQ_LB_CTR_CTRL_CLEAR_MASK) | (clear << SQ_LB_CTR_CTRL_CLEAR_SHIFT) - -#define SQ_LB_CTR_CTRL_SET_LOAD__VI(sq_lb_ctr_ctrl_reg, load) \ - sq_lb_ctr_ctrl_reg = \ - (sq_lb_ctr_ctrl_reg & ~SQ_LB_CTR_CTRL_LOAD_MASK) | (load << SQ_LB_CTR_CTRL_LOAD_SHIFT) - -#define SQ_LB_CTR_CTRL_SET_START__VI(sq_lb_ctr_ctrl_reg, start) \ - sq_lb_ctr_ctrl_reg = \ - (sq_lb_ctr_ctrl_reg & ~SQ_LB_CTR_CTRL_START_MASK) | (start << SQ_LB_CTR_CTRL_START_SHIFT) - -#define SQ_LB_DATA_ALU_CYCLES_GET_DATA__VI(sq_lb_data_alu_cycles) \ - ((sq_lb_data_alu_cycles & SQ_LB_DATA_ALU_CYCLES_DATA_MASK) >> SQ_LB_DATA_ALU_CYCLES_DATA_SHIFT) - -#define SQ_LB_DATA_ALU_CYCLES_MASK__VI (SQ_LB_DATA_ALU_CYCLES_DATA_MASK) - -#define SQ_LB_DATA_ALU_CYCLES_SET_DATA__VI(sq_lb_data_alu_cycles_reg, data) \ - sq_lb_data_alu_cycles_reg = (sq_lb_data_alu_cycles_reg & ~SQ_LB_DATA_ALU_CYCLES_DATA_MASK) | \ - (data << SQ_LB_DATA_ALU_CYCLES_DATA_SHIFT) - -#define SQ_LB_DATA_ALU_STALLS_GET_DATA__VI(sq_lb_data_alu_stalls) \ - ((sq_lb_data_alu_stalls & SQ_LB_DATA_ALU_STALLS_DATA_MASK) >> SQ_LB_DATA_ALU_STALLS_DATA_SHIFT) - -#define SQ_LB_DATA_ALU_STALLS_MASK__VI (SQ_LB_DATA_ALU_STALLS_DATA_MASK) - -#define SQ_LB_DATA_ALU_STALLS_SET_DATA__VI(sq_lb_data_alu_stalls_reg, data) \ - sq_lb_data_alu_stalls_reg = (sq_lb_data_alu_stalls_reg & ~SQ_LB_DATA_ALU_STALLS_DATA_MASK) | \ - (data << SQ_LB_DATA_ALU_STALLS_DATA_SHIFT) - -#define SQ_LB_DATA_TEX_CYCLES_GET_DATA__VI(sq_lb_data_tex_cycles) \ - ((sq_lb_data_tex_cycles & SQ_LB_DATA_TEX_CYCLES_DATA_MASK) >> SQ_LB_DATA_TEX_CYCLES_DATA_SHIFT) - -#define SQ_LB_DATA_TEX_CYCLES_MASK__VI (SQ_LB_DATA_TEX_CYCLES_DATA_MASK) - -#define SQ_LB_DATA_TEX_CYCLES_SET_DATA__VI(sq_lb_data_tex_cycles_reg, data) \ - sq_lb_data_tex_cycles_reg = (sq_lb_data_tex_cycles_reg & ~SQ_LB_DATA_TEX_CYCLES_DATA_MASK) | \ - (data << SQ_LB_DATA_TEX_CYCLES_DATA_SHIFT) - -#define SQ_LB_DATA_TEX_STALLS_GET_DATA__VI(sq_lb_data_tex_stalls) \ - ((sq_lb_data_tex_stalls & SQ_LB_DATA_TEX_STALLS_DATA_MASK) >> SQ_LB_DATA_TEX_STALLS_DATA_SHIFT) - -#define SQ_LB_DATA_TEX_STALLS_MASK__VI (SQ_LB_DATA_TEX_STALLS_DATA_MASK) - -#define SQ_LB_DATA_TEX_STALLS_SET_DATA__VI(sq_lb_data_tex_stalls_reg, data) \ - sq_lb_data_tex_stalls_reg = (sq_lb_data_tex_stalls_reg & ~SQ_LB_DATA_TEX_STALLS_DATA_MASK) | \ - (data << SQ_LB_DATA_TEX_STALLS_DATA_SHIFT) - -#define SQ_LDS_CLK_CTRL_GET_FORCE_CU_ON_SH0__VI(sq_lds_clk_ctrl) \ - ((sq_lds_clk_ctrl & SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_MASK) >> \ - SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT) - -#define SQ_LDS_CLK_CTRL_GET_FORCE_CU_ON_SH1__VI(sq_lds_clk_ctrl) \ - ((sq_lds_clk_ctrl & SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_MASK) >> \ - SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT) - -#define SQ_LDS_CLK_CTRL_MASK__VI \ - (SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_MASK | SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_MASK) - -#define SQ_LDS_CLK_CTRL_SET_FORCE_CU_ON_SH0__VI(sq_lds_clk_ctrl_reg, force_cu_on_sh0) \ - sq_lds_clk_ctrl_reg = (sq_lds_clk_ctrl_reg & ~SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_MASK) | \ - (force_cu_on_sh0 << SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT) - -#define SQ_LDS_CLK_CTRL_SET_FORCE_CU_ON_SH1__VI(sq_lds_clk_ctrl_reg, force_cu_on_sh1) \ - sq_lds_clk_ctrl_reg = (sq_lds_clk_ctrl_reg & ~SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_MASK) | \ - (force_cu_on_sh1 << SQ_LDS_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_DEFAULT__VI 0x0000c0cd -#define SQ_M0_GPR_IDX_WORD_GET_INDEX__VI(sq_m0_gpr_idx_word) \ - ((sq_m0_gpr_idx_word & SQ_M0_GPR_IDX_WORD_INDEX_MASK) >> SQ_M0_GPR_IDX_WORD_INDEX_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_GET_VDST_REL__VI(sq_m0_gpr_idx_word) \ - ((sq_m0_gpr_idx_word & SQ_M0_GPR_IDX_WORD_VDST_REL_MASK) >> SQ_M0_GPR_IDX_WORD_VDST_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_GET_VSRC0_REL__VI(sq_m0_gpr_idx_word) \ - ((sq_m0_gpr_idx_word & SQ_M0_GPR_IDX_WORD_VSRC0_REL_MASK) >> SQ_M0_GPR_IDX_WORD_VSRC0_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_GET_VSRC1_REL__VI(sq_m0_gpr_idx_word) \ - ((sq_m0_gpr_idx_word & SQ_M0_GPR_IDX_WORD_VSRC1_REL_MASK) >> SQ_M0_GPR_IDX_WORD_VSRC1_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_GET_VSRC2_REL__VI(sq_m0_gpr_idx_word) \ - ((sq_m0_gpr_idx_word & SQ_M0_GPR_IDX_WORD_VSRC2_REL_MASK) >> SQ_M0_GPR_IDX_WORD_VSRC2_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_INDEX_MASK__VI 0x000000ff -#define SQ_M0_GPR_IDX_WORD_INDEX_SHIFT__VI 0x00000000 -#define SQ_M0_GPR_IDX_WORD_INDEX_SIZE__VI 8 -#define SQ_M0_GPR_IDX_WORD_MASK__VI \ - (SQ_M0_GPR_IDX_WORD_INDEX_MASK | SQ_M0_GPR_IDX_WORD_VSRC0_REL_MASK | \ - SQ_M0_GPR_IDX_WORD_VSRC1_REL_MASK | SQ_M0_GPR_IDX_WORD_VSRC2_REL_MASK | \ - SQ_M0_GPR_IDX_WORD_VDST_REL_MASK) - -#define SQ_M0_GPR_IDX_WORD_REG_SIZE__VI 32 -#define SQ_M0_GPR_IDX_WORD_SET_INDEX__VI(sq_m0_gpr_idx_word_reg, index) \ - sq_m0_gpr_idx_word_reg = (sq_m0_gpr_idx_word_reg & ~SQ_M0_GPR_IDX_WORD_INDEX_MASK) | \ - (index << SQ_M0_GPR_IDX_WORD_INDEX_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_SET_VDST_REL__VI(sq_m0_gpr_idx_word_reg, vdst_rel) \ - sq_m0_gpr_idx_word_reg = (sq_m0_gpr_idx_word_reg & ~SQ_M0_GPR_IDX_WORD_VDST_REL_MASK) | \ - (vdst_rel << SQ_M0_GPR_IDX_WORD_VDST_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_SET_VSRC0_REL__VI(sq_m0_gpr_idx_word_reg, vsrc0_rel) \ - sq_m0_gpr_idx_word_reg = (sq_m0_gpr_idx_word_reg & ~SQ_M0_GPR_IDX_WORD_VSRC0_REL_MASK) | \ - (vsrc0_rel << SQ_M0_GPR_IDX_WORD_VSRC0_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_SET_VSRC1_REL__VI(sq_m0_gpr_idx_word_reg, vsrc1_rel) \ - sq_m0_gpr_idx_word_reg = (sq_m0_gpr_idx_word_reg & ~SQ_M0_GPR_IDX_WORD_VSRC1_REL_MASK) | \ - (vsrc1_rel << SQ_M0_GPR_IDX_WORD_VSRC1_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_SET_VSRC2_REL__VI(sq_m0_gpr_idx_word_reg, vsrc2_rel) \ - sq_m0_gpr_idx_word_reg = (sq_m0_gpr_idx_word_reg & ~SQ_M0_GPR_IDX_WORD_VSRC2_REL_MASK) | \ - (vsrc2_rel << SQ_M0_GPR_IDX_WORD_VSRC2_REL_SHIFT) - -#define SQ_M0_GPR_IDX_WORD_VDST_REL_MASK__VI 0x00008000 -#define SQ_M0_GPR_IDX_WORD_VDST_REL_SHIFT__VI 15 -#define SQ_M0_GPR_IDX_WORD_VDST_REL_SIZE__VI 1 -#define SQ_M0_GPR_IDX_WORD_VSRC0_REL_MASK__VI 0x00001000 -#define SQ_M0_GPR_IDX_WORD_VSRC0_REL_SHIFT__VI 12 -#define SQ_M0_GPR_IDX_WORD_VSRC0_REL_SIZE__VI 1 -#define SQ_M0_GPR_IDX_WORD_VSRC1_REL_MASK__VI 0x00002000 -#define SQ_M0_GPR_IDX_WORD_VSRC1_REL_SHIFT__VI 13 -#define SQ_M0_GPR_IDX_WORD_VSRC1_REL_SIZE__VI 1 -#define SQ_M0_GPR_IDX_WORD_VSRC2_REL_MASK__VI 0x00004000 -#define SQ_M0_GPR_IDX_WORD_VSRC2_REL_SHIFT__VI 14 -#define SQ_M0_GPR_IDX_WORD_VSRC2_REL_SIZE__VI 1 -#define SQ_PERFCOUNTER0_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER0_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter0_hi) \ - ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER0_HI_MASK__VI (SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter0_hi_reg, perfcounter_hi) \ - sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER0_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER0_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER0_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter0_lo) \ - ((sq_perfcounter0_lo & SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER0_LO_MASK__VI (SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER0_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter0_lo_reg, perfcounter_lo) \ - sq_perfcounter0_lo_reg = (sq_perfcounter0_lo_reg & ~SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER0_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_GET_PERF_MODE__VI(sq_perfcounter0_select) \ - ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER0_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL__VI(sq_perfcounter0_select) \ - ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_GET_SIMD_MASK__VI(sq_perfcounter0_select) \ - ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER0_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_GET_SPM_MODE__VI(sq_perfcounter0_select) \ - ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER0_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter0_select) \ - ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter0_select) \ - ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_MASK__VI \ - (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER0_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER0_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER0_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER0_SELECT_SET_PERF_MODE__VI(sq_perfcounter0_select_reg, perf_mode) \ - sq_perfcounter0_select_reg = \ - (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER0_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL__VI(sq_perfcounter0_select_reg, perf_sel) \ - sq_perfcounter0_select_reg = \ - (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_SET_SIMD_MASK__VI(sq_perfcounter0_select_reg, simd_mask) \ - sq_perfcounter0_select_reg = \ - (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER0_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_SET_SPM_MODE__VI(sq_perfcounter0_select_reg, spm_mode) \ - sq_perfcounter0_select_reg = \ - (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER0_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter0_select_reg, sqc_bank_mask) \ - sq_perfcounter0_select_reg = \ - (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER0_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER0_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter0_select_reg, \ - sqc_client_mask) \ - sq_perfcounter0_select_reg = \ - (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER0_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER10_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER10_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter10_hi) \ - ((sq_perfcounter10_hi & SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER10_HI_MASK__VI (SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter10_hi_reg, perfcounter_hi) \ - sq_perfcounter10_hi_reg = (sq_perfcounter10_hi_reg & ~SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER10_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER10_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER10_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter10_lo) \ - ((sq_perfcounter10_lo & SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER10_LO_MASK__VI (SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER10_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter10_lo_reg, perfcounter_lo) \ - sq_perfcounter10_lo_reg = (sq_perfcounter10_lo_reg & ~SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER10_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_GET_PERF_MODE__VI(sq_perfcounter10_select) \ - ((sq_perfcounter10_select & SQ_PERFCOUNTER10_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER10_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_GET_PERF_SEL__VI(sq_perfcounter10_select) \ - ((sq_perfcounter10_select & SQ_PERFCOUNTER10_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER10_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_GET_SIMD_MASK__VI(sq_perfcounter10_select) \ - ((sq_perfcounter10_select & SQ_PERFCOUNTER10_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER10_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_GET_SPM_MODE__VI(sq_perfcounter10_select) \ - ((sq_perfcounter10_select & SQ_PERFCOUNTER10_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER10_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter10_select) \ - ((sq_perfcounter10_select & SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter10_select) \ - ((sq_perfcounter10_select & SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_MASK__VI \ - (SQ_PERFCOUNTER10_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER10_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER10_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER10_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER10_SELECT_SET_PERF_MODE__VI(sq_perfcounter10_select_reg, perf_mode) \ - sq_perfcounter10_select_reg = \ - (sq_perfcounter10_select_reg & ~SQ_PERFCOUNTER10_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER10_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_SET_PERF_SEL__VI(sq_perfcounter10_select_reg, perf_sel) \ - sq_perfcounter10_select_reg = \ - (sq_perfcounter10_select_reg & ~SQ_PERFCOUNTER10_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER10_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_SET_SIMD_MASK__VI(sq_perfcounter10_select_reg, simd_mask) \ - sq_perfcounter10_select_reg = \ - (sq_perfcounter10_select_reg & ~SQ_PERFCOUNTER10_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER10_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_SET_SPM_MODE__VI(sq_perfcounter10_select_reg, spm_mode) \ - sq_perfcounter10_select_reg = \ - (sq_perfcounter10_select_reg & ~SQ_PERFCOUNTER10_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER10_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter10_select_reg, sqc_bank_mask) \ - sq_perfcounter10_select_reg = \ - (sq_perfcounter10_select_reg & ~SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER10_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER10_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter10_select_reg, \ - sqc_client_mask) \ - sq_perfcounter10_select_reg = \ - (sq_perfcounter10_select_reg & ~SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER10_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER11_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER11_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter11_hi) \ - ((sq_perfcounter11_hi & SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER11_HI_MASK__VI (SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter11_hi_reg, perfcounter_hi) \ - sq_perfcounter11_hi_reg = (sq_perfcounter11_hi_reg & ~SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER11_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER11_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER11_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter11_lo) \ - ((sq_perfcounter11_lo & SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER11_LO_MASK__VI (SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER11_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter11_lo_reg, perfcounter_lo) \ - sq_perfcounter11_lo_reg = (sq_perfcounter11_lo_reg & ~SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER11_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_GET_PERF_MODE__VI(sq_perfcounter11_select) \ - ((sq_perfcounter11_select & SQ_PERFCOUNTER11_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER11_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_GET_PERF_SEL__VI(sq_perfcounter11_select) \ - ((sq_perfcounter11_select & SQ_PERFCOUNTER11_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER11_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_GET_SIMD_MASK__VI(sq_perfcounter11_select) \ - ((sq_perfcounter11_select & SQ_PERFCOUNTER11_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER11_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_GET_SPM_MODE__VI(sq_perfcounter11_select) \ - ((sq_perfcounter11_select & SQ_PERFCOUNTER11_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER11_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter11_select) \ - ((sq_perfcounter11_select & SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter11_select) \ - ((sq_perfcounter11_select & SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_MASK__VI \ - (SQ_PERFCOUNTER11_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER11_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER11_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER11_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER11_SELECT_SET_PERF_MODE__VI(sq_perfcounter11_select_reg, perf_mode) \ - sq_perfcounter11_select_reg = \ - (sq_perfcounter11_select_reg & ~SQ_PERFCOUNTER11_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER11_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_SET_PERF_SEL__VI(sq_perfcounter11_select_reg, perf_sel) \ - sq_perfcounter11_select_reg = \ - (sq_perfcounter11_select_reg & ~SQ_PERFCOUNTER11_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER11_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_SET_SIMD_MASK__VI(sq_perfcounter11_select_reg, simd_mask) \ - sq_perfcounter11_select_reg = \ - (sq_perfcounter11_select_reg & ~SQ_PERFCOUNTER11_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER11_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_SET_SPM_MODE__VI(sq_perfcounter11_select_reg, spm_mode) \ - sq_perfcounter11_select_reg = \ - (sq_perfcounter11_select_reg & ~SQ_PERFCOUNTER11_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER11_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter11_select_reg, sqc_bank_mask) \ - sq_perfcounter11_select_reg = \ - (sq_perfcounter11_select_reg & ~SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER11_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER11_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter11_select_reg, \ - sqc_client_mask) \ - sq_perfcounter11_select_reg = \ - (sq_perfcounter11_select_reg & ~SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER11_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER12_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER12_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER12_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter12_hi) \ - ((sq_perfcounter12_hi & SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER12_HI_MASK__VI (SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER12_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter12_hi_reg, perfcounter_hi) \ - sq_perfcounter12_hi_reg = (sq_perfcounter12_hi_reg & ~SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER12_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER12_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER12_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER12_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter12_lo) \ - ((sq_perfcounter12_lo & SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER12_LO_MASK__VI (SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER12_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter12_lo_reg, perfcounter_lo) \ - sq_perfcounter12_lo_reg = (sq_perfcounter12_lo_reg & ~SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER12_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_GET_PERF_MODE__VI(sq_perfcounter12_select) \ - ((sq_perfcounter12_select & SQ_PERFCOUNTER12_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER12_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_GET_PERF_SEL__VI(sq_perfcounter12_select) \ - ((sq_perfcounter12_select & SQ_PERFCOUNTER12_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER12_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_GET_SIMD_MASK__VI(sq_perfcounter12_select) \ - ((sq_perfcounter12_select & SQ_PERFCOUNTER12_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER12_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_GET_SPM_MODE__VI(sq_perfcounter12_select) \ - ((sq_perfcounter12_select & SQ_PERFCOUNTER12_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER12_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter12_select) \ - ((sq_perfcounter12_select & SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter12_select) \ - ((sq_perfcounter12_select & SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_MASK__VI \ - (SQ_PERFCOUNTER12_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER12_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER12_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER12_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER12_SELECT_SET_PERF_MODE__VI(sq_perfcounter12_select_reg, perf_mode) \ - sq_perfcounter12_select_reg = \ - (sq_perfcounter12_select_reg & ~SQ_PERFCOUNTER12_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER12_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_SET_PERF_SEL__VI(sq_perfcounter12_select_reg, perf_sel) \ - sq_perfcounter12_select_reg = \ - (sq_perfcounter12_select_reg & ~SQ_PERFCOUNTER12_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER12_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_SET_SIMD_MASK__VI(sq_perfcounter12_select_reg, simd_mask) \ - sq_perfcounter12_select_reg = \ - (sq_perfcounter12_select_reg & ~SQ_PERFCOUNTER12_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER12_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_SET_SPM_MODE__VI(sq_perfcounter12_select_reg, spm_mode) \ - sq_perfcounter12_select_reg = \ - (sq_perfcounter12_select_reg & ~SQ_PERFCOUNTER12_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER12_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter12_select_reg, sqc_bank_mask) \ - sq_perfcounter12_select_reg = \ - (sq_perfcounter12_select_reg & ~SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER12_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER12_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter12_select_reg, \ - sqc_client_mask) \ - sq_perfcounter12_select_reg = \ - (sq_perfcounter12_select_reg & ~SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER12_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER13_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER13_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER13_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter13_hi) \ - ((sq_perfcounter13_hi & SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER13_HI_MASK__VI (SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER13_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter13_hi_reg, perfcounter_hi) \ - sq_perfcounter13_hi_reg = (sq_perfcounter13_hi_reg & ~SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER13_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER13_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER13_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER13_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter13_lo) \ - ((sq_perfcounter13_lo & SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER13_LO_MASK__VI (SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER13_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter13_lo_reg, perfcounter_lo) \ - sq_perfcounter13_lo_reg = (sq_perfcounter13_lo_reg & ~SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER13_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_GET_PERF_MODE__VI(sq_perfcounter13_select) \ - ((sq_perfcounter13_select & SQ_PERFCOUNTER13_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER13_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_GET_PERF_SEL__VI(sq_perfcounter13_select) \ - ((sq_perfcounter13_select & SQ_PERFCOUNTER13_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER13_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_GET_SIMD_MASK__VI(sq_perfcounter13_select) \ - ((sq_perfcounter13_select & SQ_PERFCOUNTER13_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER13_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_GET_SPM_MODE__VI(sq_perfcounter13_select) \ - ((sq_perfcounter13_select & SQ_PERFCOUNTER13_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER13_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter13_select) \ - ((sq_perfcounter13_select & SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter13_select) \ - ((sq_perfcounter13_select & SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_MASK__VI \ - (SQ_PERFCOUNTER13_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER13_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER13_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER13_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER13_SELECT_SET_PERF_MODE__VI(sq_perfcounter13_select_reg, perf_mode) \ - sq_perfcounter13_select_reg = \ - (sq_perfcounter13_select_reg & ~SQ_PERFCOUNTER13_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER13_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_SET_PERF_SEL__VI(sq_perfcounter13_select_reg, perf_sel) \ - sq_perfcounter13_select_reg = \ - (sq_perfcounter13_select_reg & ~SQ_PERFCOUNTER13_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER13_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_SET_SIMD_MASK__VI(sq_perfcounter13_select_reg, simd_mask) \ - sq_perfcounter13_select_reg = \ - (sq_perfcounter13_select_reg & ~SQ_PERFCOUNTER13_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER13_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_SET_SPM_MODE__VI(sq_perfcounter13_select_reg, spm_mode) \ - sq_perfcounter13_select_reg = \ - (sq_perfcounter13_select_reg & ~SQ_PERFCOUNTER13_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER13_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter13_select_reg, sqc_bank_mask) \ - sq_perfcounter13_select_reg = \ - (sq_perfcounter13_select_reg & ~SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER13_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER13_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter13_select_reg, \ - sqc_client_mask) \ - sq_perfcounter13_select_reg = \ - (sq_perfcounter13_select_reg & ~SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER13_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER14_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER14_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER14_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter14_hi) \ - ((sq_perfcounter14_hi & SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER14_HI_MASK__VI (SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER14_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter14_hi_reg, perfcounter_hi) \ - sq_perfcounter14_hi_reg = (sq_perfcounter14_hi_reg & ~SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER14_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER14_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER14_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER14_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter14_lo) \ - ((sq_perfcounter14_lo & SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER14_LO_MASK__VI (SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER14_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter14_lo_reg, perfcounter_lo) \ - sq_perfcounter14_lo_reg = (sq_perfcounter14_lo_reg & ~SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER14_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_GET_PERF_MODE__VI(sq_perfcounter14_select) \ - ((sq_perfcounter14_select & SQ_PERFCOUNTER14_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER14_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_GET_PERF_SEL__VI(sq_perfcounter14_select) \ - ((sq_perfcounter14_select & SQ_PERFCOUNTER14_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER14_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_GET_SIMD_MASK__VI(sq_perfcounter14_select) \ - ((sq_perfcounter14_select & SQ_PERFCOUNTER14_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER14_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_GET_SPM_MODE__VI(sq_perfcounter14_select) \ - ((sq_perfcounter14_select & SQ_PERFCOUNTER14_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER14_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter14_select) \ - ((sq_perfcounter14_select & SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter14_select) \ - ((sq_perfcounter14_select & SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_MASK__VI \ - (SQ_PERFCOUNTER14_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER14_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER14_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER14_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER14_SELECT_SET_PERF_MODE__VI(sq_perfcounter14_select_reg, perf_mode) \ - sq_perfcounter14_select_reg = \ - (sq_perfcounter14_select_reg & ~SQ_PERFCOUNTER14_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER14_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_SET_PERF_SEL__VI(sq_perfcounter14_select_reg, perf_sel) \ - sq_perfcounter14_select_reg = \ - (sq_perfcounter14_select_reg & ~SQ_PERFCOUNTER14_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER14_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_SET_SIMD_MASK__VI(sq_perfcounter14_select_reg, simd_mask) \ - sq_perfcounter14_select_reg = \ - (sq_perfcounter14_select_reg & ~SQ_PERFCOUNTER14_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER14_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_SET_SPM_MODE__VI(sq_perfcounter14_select_reg, spm_mode) \ - sq_perfcounter14_select_reg = \ - (sq_perfcounter14_select_reg & ~SQ_PERFCOUNTER14_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER14_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter14_select_reg, sqc_bank_mask) \ - sq_perfcounter14_select_reg = \ - (sq_perfcounter14_select_reg & ~SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER14_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER14_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter14_select_reg, \ - sqc_client_mask) \ - sq_perfcounter14_select_reg = \ - (sq_perfcounter14_select_reg & ~SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER14_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER15_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER15_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER15_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter15_hi) \ - ((sq_perfcounter15_hi & SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER15_HI_MASK__VI (SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER15_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter15_hi_reg, perfcounter_hi) \ - sq_perfcounter15_hi_reg = (sq_perfcounter15_hi_reg & ~SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER15_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER15_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER15_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER15_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter15_lo) \ - ((sq_perfcounter15_lo & SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER15_LO_MASK__VI (SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER15_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter15_lo_reg, perfcounter_lo) \ - sq_perfcounter15_lo_reg = (sq_perfcounter15_lo_reg & ~SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER15_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_GET_PERF_MODE__VI(sq_perfcounter15_select) \ - ((sq_perfcounter15_select & SQ_PERFCOUNTER15_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER15_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_GET_PERF_SEL__VI(sq_perfcounter15_select) \ - ((sq_perfcounter15_select & SQ_PERFCOUNTER15_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER15_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_GET_SIMD_MASK__VI(sq_perfcounter15_select) \ - ((sq_perfcounter15_select & SQ_PERFCOUNTER15_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER15_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_GET_SPM_MODE__VI(sq_perfcounter15_select) \ - ((sq_perfcounter15_select & SQ_PERFCOUNTER15_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER15_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter15_select) \ - ((sq_perfcounter15_select & SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter15_select) \ - ((sq_perfcounter15_select & SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_MASK__VI \ - (SQ_PERFCOUNTER15_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER15_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER15_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER15_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER15_SELECT_SET_PERF_MODE__VI(sq_perfcounter15_select_reg, perf_mode) \ - sq_perfcounter15_select_reg = \ - (sq_perfcounter15_select_reg & ~SQ_PERFCOUNTER15_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER15_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_SET_PERF_SEL__VI(sq_perfcounter15_select_reg, perf_sel) \ - sq_perfcounter15_select_reg = \ - (sq_perfcounter15_select_reg & ~SQ_PERFCOUNTER15_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER15_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_SET_SIMD_MASK__VI(sq_perfcounter15_select_reg, simd_mask) \ - sq_perfcounter15_select_reg = \ - (sq_perfcounter15_select_reg & ~SQ_PERFCOUNTER15_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER15_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_SET_SPM_MODE__VI(sq_perfcounter15_select_reg, spm_mode) \ - sq_perfcounter15_select_reg = \ - (sq_perfcounter15_select_reg & ~SQ_PERFCOUNTER15_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER15_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter15_select_reg, sqc_bank_mask) \ - sq_perfcounter15_select_reg = \ - (sq_perfcounter15_select_reg & ~SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER15_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER15_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter15_select_reg, \ - sqc_client_mask) \ - sq_perfcounter15_select_reg = \ - (sq_perfcounter15_select_reg & ~SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER15_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER1_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER1_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter1_hi) \ - ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER1_HI_MASK__VI (SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter1_hi_reg, perfcounter_hi) \ - sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER1_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER1_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER1_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter1_lo) \ - ((sq_perfcounter1_lo & SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER1_LO_MASK__VI (SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER1_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter1_lo_reg, perfcounter_lo) \ - sq_perfcounter1_lo_reg = (sq_perfcounter1_lo_reg & ~SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER1_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_GET_PERF_MODE__VI(sq_perfcounter1_select) \ - ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER1_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL__VI(sq_perfcounter1_select) \ - ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_GET_SIMD_MASK__VI(sq_perfcounter1_select) \ - ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER1_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_GET_SPM_MODE__VI(sq_perfcounter1_select) \ - ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER1_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter1_select) \ - ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter1_select) \ - ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_MASK__VI \ - (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER1_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER1_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER1_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER1_SELECT_SET_PERF_MODE__VI(sq_perfcounter1_select_reg, perf_mode) \ - sq_perfcounter1_select_reg = \ - (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER1_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL__VI(sq_perfcounter1_select_reg, perf_sel) \ - sq_perfcounter1_select_reg = \ - (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_SET_SIMD_MASK__VI(sq_perfcounter1_select_reg, simd_mask) \ - sq_perfcounter1_select_reg = \ - (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER1_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_SET_SPM_MODE__VI(sq_perfcounter1_select_reg, spm_mode) \ - sq_perfcounter1_select_reg = \ - (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER1_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter1_select_reg, sqc_bank_mask) \ - sq_perfcounter1_select_reg = \ - (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER1_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER1_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter1_select_reg, \ - sqc_client_mask) \ - sq_perfcounter1_select_reg = \ - (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER1_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER2_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER2_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter2_hi) \ - ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER2_HI_MASK__VI (SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter2_hi_reg, perfcounter_hi) \ - sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER2_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER2_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER2_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter2_lo) \ - ((sq_perfcounter2_lo & SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER2_LO_MASK__VI (SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER2_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter2_lo_reg, perfcounter_lo) \ - sq_perfcounter2_lo_reg = (sq_perfcounter2_lo_reg & ~SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER2_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_GET_PERF_MODE__VI(sq_perfcounter2_select) \ - ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER2_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL__VI(sq_perfcounter2_select) \ - ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_GET_SIMD_MASK__VI(sq_perfcounter2_select) \ - ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER2_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_GET_SPM_MODE__VI(sq_perfcounter2_select) \ - ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER2_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter2_select) \ - ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter2_select) \ - ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_MASK__VI \ - (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER2_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER2_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER2_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER2_SELECT_SET_PERF_MODE__VI(sq_perfcounter2_select_reg, perf_mode) \ - sq_perfcounter2_select_reg = \ - (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER2_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL__VI(sq_perfcounter2_select_reg, perf_sel) \ - sq_perfcounter2_select_reg = \ - (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_SET_SIMD_MASK__VI(sq_perfcounter2_select_reg, simd_mask) \ - sq_perfcounter2_select_reg = \ - (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER2_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_SET_SPM_MODE__VI(sq_perfcounter2_select_reg, spm_mode) \ - sq_perfcounter2_select_reg = \ - (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER2_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter2_select_reg, sqc_bank_mask) \ - sq_perfcounter2_select_reg = \ - (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER2_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER2_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter2_select_reg, \ - sqc_client_mask) \ - sq_perfcounter2_select_reg = \ - (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER2_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER3_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER3_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter3_hi) \ - ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER3_HI_MASK__VI (SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter3_hi_reg, perfcounter_hi) \ - sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER3_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER3_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER3_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter3_lo) \ - ((sq_perfcounter3_lo & SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER3_LO_MASK__VI (SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER3_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter3_lo_reg, perfcounter_lo) \ - sq_perfcounter3_lo_reg = (sq_perfcounter3_lo_reg & ~SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER3_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_GET_PERF_MODE__VI(sq_perfcounter3_select) \ - ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER3_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL__VI(sq_perfcounter3_select) \ - ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_GET_SIMD_MASK__VI(sq_perfcounter3_select) \ - ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER3_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_GET_SPM_MODE__VI(sq_perfcounter3_select) \ - ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER3_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter3_select) \ - ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter3_select) \ - ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_MASK__VI \ - (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER3_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER3_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER3_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER3_SELECT_SET_PERF_MODE__VI(sq_perfcounter3_select_reg, perf_mode) \ - sq_perfcounter3_select_reg = \ - (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER3_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL__VI(sq_perfcounter3_select_reg, perf_sel) \ - sq_perfcounter3_select_reg = \ - (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_SET_SIMD_MASK__VI(sq_perfcounter3_select_reg, simd_mask) \ - sq_perfcounter3_select_reg = \ - (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER3_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_SET_SPM_MODE__VI(sq_perfcounter3_select_reg, spm_mode) \ - sq_perfcounter3_select_reg = \ - (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER3_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter3_select_reg, sqc_bank_mask) \ - sq_perfcounter3_select_reg = \ - (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER3_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER3_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter3_select_reg, \ - sqc_client_mask) \ - sq_perfcounter3_select_reg = \ - (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER3_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER4_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER4_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter4_hi) \ - ((sq_perfcounter4_hi & SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER4_HI_MASK__VI (SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter4_hi_reg, perfcounter_hi) \ - sq_perfcounter4_hi_reg = (sq_perfcounter4_hi_reg & ~SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER4_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER4_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER4_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter4_lo) \ - ((sq_perfcounter4_lo & SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER4_LO_MASK__VI (SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER4_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter4_lo_reg, perfcounter_lo) \ - sq_perfcounter4_lo_reg = (sq_perfcounter4_lo_reg & ~SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER4_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_GET_PERF_MODE__VI(sq_perfcounter4_select) \ - ((sq_perfcounter4_select & SQ_PERFCOUNTER4_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER4_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_GET_PERF_SEL__VI(sq_perfcounter4_select) \ - ((sq_perfcounter4_select & SQ_PERFCOUNTER4_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER4_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_GET_SIMD_MASK__VI(sq_perfcounter4_select) \ - ((sq_perfcounter4_select & SQ_PERFCOUNTER4_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER4_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_GET_SPM_MODE__VI(sq_perfcounter4_select) \ - ((sq_perfcounter4_select & SQ_PERFCOUNTER4_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER4_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter4_select) \ - ((sq_perfcounter4_select & SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter4_select) \ - ((sq_perfcounter4_select & SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_MASK__VI \ - (SQ_PERFCOUNTER4_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER4_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER4_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER4_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER4_SELECT_SET_PERF_MODE__VI(sq_perfcounter4_select_reg, perf_mode) \ - sq_perfcounter4_select_reg = \ - (sq_perfcounter4_select_reg & ~SQ_PERFCOUNTER4_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER4_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_SET_PERF_SEL__VI(sq_perfcounter4_select_reg, perf_sel) \ - sq_perfcounter4_select_reg = \ - (sq_perfcounter4_select_reg & ~SQ_PERFCOUNTER4_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER4_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_SET_SIMD_MASK__VI(sq_perfcounter4_select_reg, simd_mask) \ - sq_perfcounter4_select_reg = \ - (sq_perfcounter4_select_reg & ~SQ_PERFCOUNTER4_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER4_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_SET_SPM_MODE__VI(sq_perfcounter4_select_reg, spm_mode) \ - sq_perfcounter4_select_reg = \ - (sq_perfcounter4_select_reg & ~SQ_PERFCOUNTER4_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER4_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter4_select_reg, sqc_bank_mask) \ - sq_perfcounter4_select_reg = \ - (sq_perfcounter4_select_reg & ~SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER4_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER4_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter4_select_reg, \ - sqc_client_mask) \ - sq_perfcounter4_select_reg = \ - (sq_perfcounter4_select_reg & ~SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER4_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER5_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER5_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter5_hi) \ - ((sq_perfcounter5_hi & SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER5_HI_MASK__VI (SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter5_hi_reg, perfcounter_hi) \ - sq_perfcounter5_hi_reg = (sq_perfcounter5_hi_reg & ~SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER5_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER5_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER5_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter5_lo) \ - ((sq_perfcounter5_lo & SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER5_LO_MASK__VI (SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER5_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter5_lo_reg, perfcounter_lo) \ - sq_perfcounter5_lo_reg = (sq_perfcounter5_lo_reg & ~SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER5_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_GET_PERF_MODE__VI(sq_perfcounter5_select) \ - ((sq_perfcounter5_select & SQ_PERFCOUNTER5_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER5_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_GET_PERF_SEL__VI(sq_perfcounter5_select) \ - ((sq_perfcounter5_select & SQ_PERFCOUNTER5_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER5_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_GET_SIMD_MASK__VI(sq_perfcounter5_select) \ - ((sq_perfcounter5_select & SQ_PERFCOUNTER5_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER5_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_GET_SPM_MODE__VI(sq_perfcounter5_select) \ - ((sq_perfcounter5_select & SQ_PERFCOUNTER5_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER5_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter5_select) \ - ((sq_perfcounter5_select & SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter5_select) \ - ((sq_perfcounter5_select & SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_MASK__VI \ - (SQ_PERFCOUNTER5_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER5_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER5_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER5_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER5_SELECT_SET_PERF_MODE__VI(sq_perfcounter5_select_reg, perf_mode) \ - sq_perfcounter5_select_reg = \ - (sq_perfcounter5_select_reg & ~SQ_PERFCOUNTER5_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER5_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_SET_PERF_SEL__VI(sq_perfcounter5_select_reg, perf_sel) \ - sq_perfcounter5_select_reg = \ - (sq_perfcounter5_select_reg & ~SQ_PERFCOUNTER5_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER5_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_SET_SIMD_MASK__VI(sq_perfcounter5_select_reg, simd_mask) \ - sq_perfcounter5_select_reg = \ - (sq_perfcounter5_select_reg & ~SQ_PERFCOUNTER5_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER5_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_SET_SPM_MODE__VI(sq_perfcounter5_select_reg, spm_mode) \ - sq_perfcounter5_select_reg = \ - (sq_perfcounter5_select_reg & ~SQ_PERFCOUNTER5_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER5_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter5_select_reg, sqc_bank_mask) \ - sq_perfcounter5_select_reg = \ - (sq_perfcounter5_select_reg & ~SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER5_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER5_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter5_select_reg, \ - sqc_client_mask) \ - sq_perfcounter5_select_reg = \ - (sq_perfcounter5_select_reg & ~SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER5_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER6_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER6_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter6_hi) \ - ((sq_perfcounter6_hi & SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER6_HI_MASK__VI (SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter6_hi_reg, perfcounter_hi) \ - sq_perfcounter6_hi_reg = (sq_perfcounter6_hi_reg & ~SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER6_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER6_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER6_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter6_lo) \ - ((sq_perfcounter6_lo & SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER6_LO_MASK__VI (SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER6_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter6_lo_reg, perfcounter_lo) \ - sq_perfcounter6_lo_reg = (sq_perfcounter6_lo_reg & ~SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER6_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_GET_PERF_MODE__VI(sq_perfcounter6_select) \ - ((sq_perfcounter6_select & SQ_PERFCOUNTER6_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER6_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_GET_PERF_SEL__VI(sq_perfcounter6_select) \ - ((sq_perfcounter6_select & SQ_PERFCOUNTER6_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER6_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_GET_SIMD_MASK__VI(sq_perfcounter6_select) \ - ((sq_perfcounter6_select & SQ_PERFCOUNTER6_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER6_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_GET_SPM_MODE__VI(sq_perfcounter6_select) \ - ((sq_perfcounter6_select & SQ_PERFCOUNTER6_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER6_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter6_select) \ - ((sq_perfcounter6_select & SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter6_select) \ - ((sq_perfcounter6_select & SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_MASK__VI \ - (SQ_PERFCOUNTER6_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER6_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER6_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER6_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER6_SELECT_SET_PERF_MODE__VI(sq_perfcounter6_select_reg, perf_mode) \ - sq_perfcounter6_select_reg = \ - (sq_perfcounter6_select_reg & ~SQ_PERFCOUNTER6_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER6_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_SET_PERF_SEL__VI(sq_perfcounter6_select_reg, perf_sel) \ - sq_perfcounter6_select_reg = \ - (sq_perfcounter6_select_reg & ~SQ_PERFCOUNTER6_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER6_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_SET_SIMD_MASK__VI(sq_perfcounter6_select_reg, simd_mask) \ - sq_perfcounter6_select_reg = \ - (sq_perfcounter6_select_reg & ~SQ_PERFCOUNTER6_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER6_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_SET_SPM_MODE__VI(sq_perfcounter6_select_reg, spm_mode) \ - sq_perfcounter6_select_reg = \ - (sq_perfcounter6_select_reg & ~SQ_PERFCOUNTER6_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER6_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter6_select_reg, sqc_bank_mask) \ - sq_perfcounter6_select_reg = \ - (sq_perfcounter6_select_reg & ~SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER6_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER6_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter6_select_reg, \ - sqc_client_mask) \ - sq_perfcounter6_select_reg = \ - (sq_perfcounter6_select_reg & ~SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER6_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER7_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER7_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter7_hi) \ - ((sq_perfcounter7_hi & SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER7_HI_MASK__VI (SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter7_hi_reg, perfcounter_hi) \ - sq_perfcounter7_hi_reg = (sq_perfcounter7_hi_reg & ~SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER7_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER7_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER7_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter7_lo) \ - ((sq_perfcounter7_lo & SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER7_LO_MASK__VI (SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER7_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter7_lo_reg, perfcounter_lo) \ - sq_perfcounter7_lo_reg = (sq_perfcounter7_lo_reg & ~SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER7_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_GET_PERF_MODE__VI(sq_perfcounter7_select) \ - ((sq_perfcounter7_select & SQ_PERFCOUNTER7_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER7_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_GET_PERF_SEL__VI(sq_perfcounter7_select) \ - ((sq_perfcounter7_select & SQ_PERFCOUNTER7_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER7_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_GET_SIMD_MASK__VI(sq_perfcounter7_select) \ - ((sq_perfcounter7_select & SQ_PERFCOUNTER7_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER7_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_GET_SPM_MODE__VI(sq_perfcounter7_select) \ - ((sq_perfcounter7_select & SQ_PERFCOUNTER7_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER7_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter7_select) \ - ((sq_perfcounter7_select & SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter7_select) \ - ((sq_perfcounter7_select & SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_MASK__VI \ - (SQ_PERFCOUNTER7_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER7_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER7_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER7_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER7_SELECT_SET_PERF_MODE__VI(sq_perfcounter7_select_reg, perf_mode) \ - sq_perfcounter7_select_reg = \ - (sq_perfcounter7_select_reg & ~SQ_PERFCOUNTER7_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER7_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_SET_PERF_SEL__VI(sq_perfcounter7_select_reg, perf_sel) \ - sq_perfcounter7_select_reg = \ - (sq_perfcounter7_select_reg & ~SQ_PERFCOUNTER7_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER7_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_SET_SIMD_MASK__VI(sq_perfcounter7_select_reg, simd_mask) \ - sq_perfcounter7_select_reg = \ - (sq_perfcounter7_select_reg & ~SQ_PERFCOUNTER7_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER7_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_SET_SPM_MODE__VI(sq_perfcounter7_select_reg, spm_mode) \ - sq_perfcounter7_select_reg = \ - (sq_perfcounter7_select_reg & ~SQ_PERFCOUNTER7_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER7_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter7_select_reg, sqc_bank_mask) \ - sq_perfcounter7_select_reg = \ - (sq_perfcounter7_select_reg & ~SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER7_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER7_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter7_select_reg, \ - sqc_client_mask) \ - sq_perfcounter7_select_reg = \ - (sq_perfcounter7_select_reg & ~SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER7_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER8_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER8_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter8_hi) \ - ((sq_perfcounter8_hi & SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER8_HI_MASK__VI (SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter8_hi_reg, perfcounter_hi) \ - sq_perfcounter8_hi_reg = (sq_perfcounter8_hi_reg & ~SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER8_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER8_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER8_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter8_lo) \ - ((sq_perfcounter8_lo & SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER8_LO_MASK__VI (SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER8_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter8_lo_reg, perfcounter_lo) \ - sq_perfcounter8_lo_reg = (sq_perfcounter8_lo_reg & ~SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER8_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_GET_PERF_MODE__VI(sq_perfcounter8_select) \ - ((sq_perfcounter8_select & SQ_PERFCOUNTER8_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER8_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_GET_PERF_SEL__VI(sq_perfcounter8_select) \ - ((sq_perfcounter8_select & SQ_PERFCOUNTER8_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER8_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_GET_SIMD_MASK__VI(sq_perfcounter8_select) \ - ((sq_perfcounter8_select & SQ_PERFCOUNTER8_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER8_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_GET_SPM_MODE__VI(sq_perfcounter8_select) \ - ((sq_perfcounter8_select & SQ_PERFCOUNTER8_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER8_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter8_select) \ - ((sq_perfcounter8_select & SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter8_select) \ - ((sq_perfcounter8_select & SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_MASK__VI \ - (SQ_PERFCOUNTER8_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER8_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER8_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER8_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER8_SELECT_SET_PERF_MODE__VI(sq_perfcounter8_select_reg, perf_mode) \ - sq_perfcounter8_select_reg = \ - (sq_perfcounter8_select_reg & ~SQ_PERFCOUNTER8_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER8_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_SET_PERF_SEL__VI(sq_perfcounter8_select_reg, perf_sel) \ - sq_perfcounter8_select_reg = \ - (sq_perfcounter8_select_reg & ~SQ_PERFCOUNTER8_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER8_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_SET_SIMD_MASK__VI(sq_perfcounter8_select_reg, simd_mask) \ - sq_perfcounter8_select_reg = \ - (sq_perfcounter8_select_reg & ~SQ_PERFCOUNTER8_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER8_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_SET_SPM_MODE__VI(sq_perfcounter8_select_reg, spm_mode) \ - sq_perfcounter8_select_reg = \ - (sq_perfcounter8_select_reg & ~SQ_PERFCOUNTER8_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER8_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter8_select_reg, sqc_bank_mask) \ - sq_perfcounter8_select_reg = \ - (sq_perfcounter8_select_reg & ~SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER8_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER8_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter8_select_reg, \ - sqc_client_mask) \ - sq_perfcounter8_select_reg = \ - (sq_perfcounter8_select_reg & ~SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER8_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER9_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER9_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI__VI(sq_perfcounter9_hi) \ - ((sq_perfcounter9_hi & SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> \ - SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER9_HI_MASK__VI (SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) - -#define SQ_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI__VI(sq_perfcounter9_hi_reg, perfcounter_hi) \ - sq_perfcounter9_hi_reg = (sq_perfcounter9_hi_reg & ~SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | \ - (perfcounter_hi << SQ_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) - -#define SQ_PERFCOUNTER9_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_PERFCOUNTER9_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_PERFCOUNTER9_LO_GET_PERFCOUNTER_LO__VI(sq_perfcounter9_lo) \ - ((sq_perfcounter9_lo & SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_MASK) >> \ - SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER9_LO_MASK__VI (SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_MASK) - -#define SQ_PERFCOUNTER9_LO_SET_PERFCOUNTER_LO__VI(sq_perfcounter9_lo_reg, perfcounter_lo) \ - sq_perfcounter9_lo_reg = (sq_perfcounter9_lo_reg & ~SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_MASK) | \ - (perfcounter_lo << SQ_PERFCOUNTER9_LO_PERFCOUNTER_LO_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_GET_PERF_MODE__VI(sq_perfcounter9_select) \ - ((sq_perfcounter9_select & SQ_PERFCOUNTER9_SELECT_PERF_MODE_MASK) >> \ - SQ_PERFCOUNTER9_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_GET_PERF_SEL__VI(sq_perfcounter9_select) \ - ((sq_perfcounter9_select & SQ_PERFCOUNTER9_SELECT_PERF_SEL_MASK) >> \ - SQ_PERFCOUNTER9_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_GET_SIMD_MASK__VI(sq_perfcounter9_select) \ - ((sq_perfcounter9_select & SQ_PERFCOUNTER9_SELECT_SIMD_MASK_MASK) >> \ - SQ_PERFCOUNTER9_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_GET_SPM_MODE__VI(sq_perfcounter9_select) \ - ((sq_perfcounter9_select & SQ_PERFCOUNTER9_SELECT_SPM_MODE_MASK) >> \ - SQ_PERFCOUNTER9_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_GET_SQC_BANK_MASK__VI(sq_perfcounter9_select) \ - ((sq_perfcounter9_select & SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_MASK) >> \ - SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_GET_SQC_CLIENT_MASK__VI(sq_perfcounter9_select) \ - ((sq_perfcounter9_select & SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_MASK) >> \ - SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_MASK__VI \ - (SQ_PERFCOUNTER9_SELECT_PERF_SEL_MASK | SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_MASK | \ - SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_MASK | SQ_PERFCOUNTER9_SELECT_SPM_MODE_MASK | \ - SQ_PERFCOUNTER9_SELECT_SIMD_MASK_MASK | SQ_PERFCOUNTER9_SELECT_PERF_MODE_MASK) - -#define SQ_PERFCOUNTER9_SELECT_SET_PERF_MODE__VI(sq_perfcounter9_select_reg, perf_mode) \ - sq_perfcounter9_select_reg = \ - (sq_perfcounter9_select_reg & ~SQ_PERFCOUNTER9_SELECT_PERF_MODE_MASK) | \ - (perf_mode << SQ_PERFCOUNTER9_SELECT_PERF_MODE_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_SET_PERF_SEL__VI(sq_perfcounter9_select_reg, perf_sel) \ - sq_perfcounter9_select_reg = \ - (sq_perfcounter9_select_reg & ~SQ_PERFCOUNTER9_SELECT_PERF_SEL_MASK) | \ - (perf_sel << SQ_PERFCOUNTER9_SELECT_PERF_SEL_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_SET_SIMD_MASK__VI(sq_perfcounter9_select_reg, simd_mask) \ - sq_perfcounter9_select_reg = \ - (sq_perfcounter9_select_reg & ~SQ_PERFCOUNTER9_SELECT_SIMD_MASK_MASK) | \ - (simd_mask << SQ_PERFCOUNTER9_SELECT_SIMD_MASK_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_SET_SPM_MODE__VI(sq_perfcounter9_select_reg, spm_mode) \ - sq_perfcounter9_select_reg = \ - (sq_perfcounter9_select_reg & ~SQ_PERFCOUNTER9_SELECT_SPM_MODE_MASK) | \ - (spm_mode << SQ_PERFCOUNTER9_SELECT_SPM_MODE_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_SET_SQC_BANK_MASK__VI(sq_perfcounter9_select_reg, sqc_bank_mask) \ - sq_perfcounter9_select_reg = \ - (sq_perfcounter9_select_reg & ~SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_MASK) | \ - (sqc_bank_mask << SQ_PERFCOUNTER9_SELECT_SQC_BANK_MASK_SHIFT) - -#define SQ_PERFCOUNTER9_SELECT_SET_SQC_CLIENT_MASK__VI(sq_perfcounter9_select_reg, \ - sqc_client_mask) \ - sq_perfcounter9_select_reg = \ - (sq_perfcounter9_select_reg & ~SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_MASK) | \ - (sqc_client_mask << SQ_PERFCOUNTER9_SELECT_SQC_CLIENT_MASK_SHIFT) - -#define SQ_PERFCOUNTER_CTRL2_GET_FORCE_EN__VI(sq_perfcounter_ctrl2) \ - ((sq_perfcounter_ctrl2 & SQ_PERFCOUNTER_CTRL2_FORCE_EN_MASK) >> \ - SQ_PERFCOUNTER_CTRL2_FORCE_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL2_MASK__VI (SQ_PERFCOUNTER_CTRL2_FORCE_EN_MASK) - -#define SQ_PERFCOUNTER_CTRL2_SET_FORCE_EN__VI(sq_perfcounter_ctrl2_reg, force_en) \ - sq_perfcounter_ctrl2_reg = (sq_perfcounter_ctrl2_reg & ~SQ_PERFCOUNTER_CTRL2_FORCE_EN_MASK) | \ - (force_en << SQ_PERFCOUNTER_CTRL2_FORCE_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_CNTR_RATE__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_CNTR_RATE_MASK) >> \ - SQ_PERFCOUNTER_CTRL_CNTR_RATE_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_CS_EN__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_CS_EN_MASK) >> SQ_PERFCOUNTER_CTRL_CS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_DISABLE_FLUSH__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_MASK) >> \ - SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_ES_EN__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_ES_EN_MASK) >> SQ_PERFCOUNTER_CTRL_ES_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_GS_EN__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_GS_EN_MASK) >> SQ_PERFCOUNTER_CTRL_GS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_HS_EN__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_HS_EN_MASK) >> SQ_PERFCOUNTER_CTRL_HS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_LS_EN__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_LS_EN_MASK) >> SQ_PERFCOUNTER_CTRL_LS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_PS_EN__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_PS_EN_MASK) >> SQ_PERFCOUNTER_CTRL_PS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_GET_VS_EN__VI(sq_perfcounter_ctrl) \ - ((sq_perfcounter_ctrl & SQ_PERFCOUNTER_CTRL_VS_EN_MASK) >> SQ_PERFCOUNTER_CTRL_VS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_MASK__VI \ - (SQ_PERFCOUNTER_CTRL_PS_EN_MASK | SQ_PERFCOUNTER_CTRL_VS_EN_MASK | \ - SQ_PERFCOUNTER_CTRL_GS_EN_MASK | SQ_PERFCOUNTER_CTRL_ES_EN_MASK | \ - SQ_PERFCOUNTER_CTRL_HS_EN_MASK | SQ_PERFCOUNTER_CTRL_LS_EN_MASK | \ - SQ_PERFCOUNTER_CTRL_CS_EN_MASK | SQ_PERFCOUNTER_CTRL_CNTR_RATE_MASK | \ - SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_MASK) - -#define SQ_PERFCOUNTER_CTRL_SET_CNTR_RATE__VI(sq_perfcounter_ctrl_reg, cntr_rate) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_CNTR_RATE_MASK) | \ - (cntr_rate << SQ_PERFCOUNTER_CTRL_CNTR_RATE_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_CS_EN__VI(sq_perfcounter_ctrl_reg, cs_en) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_CS_EN_MASK) | \ - (cs_en << SQ_PERFCOUNTER_CTRL_CS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_DISABLE_FLUSH__VI(sq_perfcounter_ctrl_reg, disable_flush) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_MASK) | \ - (disable_flush << SQ_PERFCOUNTER_CTRL_DISABLE_FLUSH_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_ES_EN__VI(sq_perfcounter_ctrl_reg, es_en) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_ES_EN_MASK) | \ - (es_en << SQ_PERFCOUNTER_CTRL_ES_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_GS_EN__VI(sq_perfcounter_ctrl_reg, gs_en) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_GS_EN_MASK) | \ - (gs_en << SQ_PERFCOUNTER_CTRL_GS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_HS_EN__VI(sq_perfcounter_ctrl_reg, hs_en) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_HS_EN_MASK) | \ - (hs_en << SQ_PERFCOUNTER_CTRL_HS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_LS_EN__VI(sq_perfcounter_ctrl_reg, ls_en) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_LS_EN_MASK) | \ - (ls_en << SQ_PERFCOUNTER_CTRL_LS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_PS_EN__VI(sq_perfcounter_ctrl_reg, ps_en) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_PS_EN_MASK) | \ - (ps_en << SQ_PERFCOUNTER_CTRL_PS_EN_SHIFT) - -#define SQ_PERFCOUNTER_CTRL_SET_VS_EN__VI(sq_perfcounter_ctrl_reg, vs_en) \ - sq_perfcounter_ctrl_reg = (sq_perfcounter_ctrl_reg & ~SQ_PERFCOUNTER_CTRL_VS_EN_MASK) | \ - (vs_en << SQ_PERFCOUNTER_CTRL_VS_EN_SHIFT) - -#define SQ_PERFCOUNTER_MASK_GET_SH0_MASK__VI(sq_perfcounter_mask) \ - ((sq_perfcounter_mask & SQ_PERFCOUNTER_MASK_SH0_MASK_MASK) >> SQ_PERFCOUNTER_MASK_SH0_MASK_SHIFT) - -#define SQ_PERFCOUNTER_MASK_GET_SH1_MASK__VI(sq_perfcounter_mask) \ - ((sq_perfcounter_mask & SQ_PERFCOUNTER_MASK_SH1_MASK_MASK) >> SQ_PERFCOUNTER_MASK_SH1_MASK_SHIFT) - -#define SQ_PERFCOUNTER_MASK_MASK__VI \ - (SQ_PERFCOUNTER_MASK_SH0_MASK_MASK | SQ_PERFCOUNTER_MASK_SH1_MASK_MASK) - -#define SQ_PERFCOUNTER_MASK_SET_SH0_MASK__VI(sq_perfcounter_mask_reg, sh0_mask) \ - sq_perfcounter_mask_reg = (sq_perfcounter_mask_reg & ~SQ_PERFCOUNTER_MASK_SH0_MASK_MASK) | \ - (sh0_mask << SQ_PERFCOUNTER_MASK_SH0_MASK_SHIFT) - -#define SQ_PERFCOUNTER_MASK_SET_SH1_MASK__VI(sq_perfcounter_mask_reg, sh1_mask) \ - sq_perfcounter_mask_reg = (sq_perfcounter_mask_reg & ~SQ_PERFCOUNTER_MASK_SH1_MASK_MASK) | \ - (sh1_mask << SQ_PERFCOUNTER_MASK_SH1_MASK_SHIFT) - -#define SQ_POWER_THROTTLE2_GET_LONG_TERM_INTERVAL_RATIO__VI(sq_power_throttle2) \ - ((sq_power_throttle2 & SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_MASK) >> \ - SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_SHIFT) - -#define SQ_POWER_THROTTLE2_GET_MAX_POWER_DELTA__VI(sq_power_throttle2) \ - ((sq_power_throttle2 & SQ_POWER_THROTTLE2_MAX_POWER_DELTA_MASK) >> \ - SQ_POWER_THROTTLE2_MAX_POWER_DELTA_SHIFT) - -#define SQ_POWER_THROTTLE2_GET_SHORT_TERM_INTERVAL_SIZE__VI(sq_power_throttle2) \ - ((sq_power_throttle2 & SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_MASK) >> \ - SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_SHIFT) - -#define SQ_POWER_THROTTLE2_GET_USE_REF_CLOCK__VI(sq_power_throttle2) \ - ((sq_power_throttle2 & SQ_POWER_THROTTLE2_USE_REF_CLOCK_MASK) >> \ - SQ_POWER_THROTTLE2_USE_REF_CLOCK_SHIFT) - -#define SQ_POWER_THROTTLE2_MASK__VI \ - (SQ_POWER_THROTTLE2_MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_MASK | \ - SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_MASK | SQ_POWER_THROTTLE2_USE_REF_CLOCK_MASK) - -#define SQ_POWER_THROTTLE2_SET_LONG_TERM_INTERVAL_RATIO__VI(sq_power_throttle2_reg, \ - long_term_interval_ratio) \ - sq_power_throttle2_reg = \ - (sq_power_throttle2_reg & ~SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_MASK) | \ - (long_term_interval_ratio << SQ_POWER_THROTTLE2_LONG_TERM_INTERVAL_RATIO_SHIFT) - -#define SQ_POWER_THROTTLE2_SET_MAX_POWER_DELTA__VI(sq_power_throttle2_reg, max_power_delta) \ - sq_power_throttle2_reg = (sq_power_throttle2_reg & ~SQ_POWER_THROTTLE2_MAX_POWER_DELTA_MASK) | \ - (max_power_delta << SQ_POWER_THROTTLE2_MAX_POWER_DELTA_SHIFT) - -#define SQ_POWER_THROTTLE2_SET_SHORT_TERM_INTERVAL_SIZE__VI(sq_power_throttle2_reg, \ - short_term_interval_size) \ - sq_power_throttle2_reg = \ - (sq_power_throttle2_reg & ~SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_MASK) | \ - (short_term_interval_size << SQ_POWER_THROTTLE2_SHORT_TERM_INTERVAL_SIZE_SHIFT) - -#define SQ_POWER_THROTTLE2_SET_USE_REF_CLOCK__VI(sq_power_throttle2_reg, use_ref_clock) \ - sq_power_throttle2_reg = (sq_power_throttle2_reg & ~SQ_POWER_THROTTLE2_USE_REF_CLOCK_MASK) | \ - (use_ref_clock << SQ_POWER_THROTTLE2_USE_REF_CLOCK_SHIFT) - -#define SQ_POWER_THROTTLE_GET_MAX_POWER__VI(sq_power_throttle) \ - ((sq_power_throttle & SQ_POWER_THROTTLE_MAX_POWER_MASK) >> SQ_POWER_THROTTLE_MAX_POWER_SHIFT) - -#define SQ_POWER_THROTTLE_GET_MIN_POWER__VI(sq_power_throttle) \ - ((sq_power_throttle & SQ_POWER_THROTTLE_MIN_POWER_MASK) >> SQ_POWER_THROTTLE_MIN_POWER_SHIFT) - -#define SQ_POWER_THROTTLE_GET_PHASE_OFFSET__VI(sq_power_throttle) \ - ((sq_power_throttle & SQ_POWER_THROTTLE_PHASE_OFFSET_MASK) >> \ - SQ_POWER_THROTTLE_PHASE_OFFSET_SHIFT) - -#define SQ_POWER_THROTTLE_MASK__VI \ - (SQ_POWER_THROTTLE_MIN_POWER_MASK | SQ_POWER_THROTTLE_MAX_POWER_MASK | \ - SQ_POWER_THROTTLE_PHASE_OFFSET_MASK) - -#define SQ_POWER_THROTTLE_SET_MAX_POWER__VI(sq_power_throttle_reg, max_power) \ - sq_power_throttle_reg = (sq_power_throttle_reg & ~SQ_POWER_THROTTLE_MAX_POWER_MASK) | \ - (max_power << SQ_POWER_THROTTLE_MAX_POWER_SHIFT) - -#define SQ_POWER_THROTTLE_SET_MIN_POWER__VI(sq_power_throttle_reg, min_power) \ - sq_power_throttle_reg = (sq_power_throttle_reg & ~SQ_POWER_THROTTLE_MIN_POWER_MASK) | \ - (min_power << SQ_POWER_THROTTLE_MIN_POWER_SHIFT) - -#define SQ_POWER_THROTTLE_SET_PHASE_OFFSET__VI(sq_power_throttle_reg, phase_offset) \ - sq_power_throttle_reg = (sq_power_throttle_reg & ~SQ_POWER_THROTTLE_PHASE_OFFSET_MASK) | \ - (phase_offset << SQ_POWER_THROTTLE_PHASE_OFFSET_SHIFT) - -#define SQ_RANDOM_WAVE_PRI_GET_RET__VI(sq_random_wave_pri) \ - ((sq_random_wave_pri & SQ_RANDOM_WAVE_PRI_RET_MASK) >> SQ_RANDOM_WAVE_PRI_RET_SHIFT) - -#define SQ_RANDOM_WAVE_PRI_GET_RNG__VI(sq_random_wave_pri) \ - ((sq_random_wave_pri & SQ_RANDOM_WAVE_PRI_RNG_MASK) >> SQ_RANDOM_WAVE_PRI_RNG_SHIFT) - -#define SQ_RANDOM_WAVE_PRI_GET_RUI__VI(sq_random_wave_pri) \ - ((sq_random_wave_pri & SQ_RANDOM_WAVE_PRI_RUI_MASK) >> SQ_RANDOM_WAVE_PRI_RUI_SHIFT) - -#define SQ_RANDOM_WAVE_PRI_MASK__VI \ - (SQ_RANDOM_WAVE_PRI_RET_MASK | SQ_RANDOM_WAVE_PRI_RUI_MASK | SQ_RANDOM_WAVE_PRI_RNG_MASK) - -#define SQ_RANDOM_WAVE_PRI_SET_RET__VI(sq_random_wave_pri_reg, ret) \ - sq_random_wave_pri_reg = (sq_random_wave_pri_reg & ~SQ_RANDOM_WAVE_PRI_RET_MASK) | \ - (ret << SQ_RANDOM_WAVE_PRI_RET_SHIFT) - -#define SQ_RANDOM_WAVE_PRI_SET_RNG__VI(sq_random_wave_pri_reg, rng) \ - sq_random_wave_pri_reg = (sq_random_wave_pri_reg & ~SQ_RANDOM_WAVE_PRI_RNG_MASK) | \ - (rng << SQ_RANDOM_WAVE_PRI_RNG_SHIFT) - -#define SQ_RANDOM_WAVE_PRI_SET_RUI__VI(sq_random_wave_pri_reg, rui) \ - sq_random_wave_pri_reg = (sq_random_wave_pri_reg & ~SQ_RANDOM_WAVE_PRI_RUI_MASK) | \ - (rui << SQ_RANDOM_WAVE_PRI_RUI_SHIFT) - -#define SQ_REG_CREDITS_GET_CMD_CREDITS__VI(sq_reg_credits) \ - ((sq_reg_credits & SQ_REG_CREDITS_CMD_CREDITS_MASK) >> SQ_REG_CREDITS_CMD_CREDITS_SHIFT) - -#define SQ_REG_CREDITS_GET_CMD_OVERFLOW__VI(sq_reg_credits) \ - ((sq_reg_credits & SQ_REG_CREDITS_CMD_OVERFLOW_MASK) >> SQ_REG_CREDITS_CMD_OVERFLOW_SHIFT) - -#define SQ_REG_CREDITS_GET_IMMED_OVERFLOW__VI(sq_reg_credits) \ - ((sq_reg_credits & SQ_REG_CREDITS_IMMED_OVERFLOW_MASK) >> SQ_REG_CREDITS_IMMED_OVERFLOW_SHIFT) - -#define SQ_REG_CREDITS_GET_REG_BUSY__VI(sq_reg_credits) \ - ((sq_reg_credits & SQ_REG_CREDITS_REG_BUSY_MASK) >> SQ_REG_CREDITS_REG_BUSY_SHIFT) - -#define SQ_REG_CREDITS_GET_SRBM_CREDITS__VI(sq_reg_credits) \ - ((sq_reg_credits & SQ_REG_CREDITS_SRBM_CREDITS_MASK) >> SQ_REG_CREDITS_SRBM_CREDITS_SHIFT) - -#define SQ_REG_CREDITS_GET_SRBM_OVERFLOW__VI(sq_reg_credits) \ - ((sq_reg_credits & SQ_REG_CREDITS_SRBM_OVERFLOW_MASK) >> SQ_REG_CREDITS_SRBM_OVERFLOW_SHIFT) - -#define SQ_REG_CREDITS_MASK__VI \ - (SQ_REG_CREDITS_SRBM_CREDITS_MASK | SQ_REG_CREDITS_CMD_CREDITS_MASK | \ - SQ_REG_CREDITS_REG_BUSY_MASK | SQ_REG_CREDITS_SRBM_OVERFLOW_MASK | \ - SQ_REG_CREDITS_IMMED_OVERFLOW_MASK | SQ_REG_CREDITS_CMD_OVERFLOW_MASK) - -#define SQ_REG_CREDITS_SET_CMD_CREDITS__VI(sq_reg_credits_reg, cmd_credits) \ - sq_reg_credits_reg = (sq_reg_credits_reg & ~SQ_REG_CREDITS_CMD_CREDITS_MASK) | \ - (cmd_credits << SQ_REG_CREDITS_CMD_CREDITS_SHIFT) - -#define SQ_REG_CREDITS_SET_CMD_OVERFLOW__VI(sq_reg_credits_reg, cmd_overflow) \ - sq_reg_credits_reg = (sq_reg_credits_reg & ~SQ_REG_CREDITS_CMD_OVERFLOW_MASK) | \ - (cmd_overflow << SQ_REG_CREDITS_CMD_OVERFLOW_SHIFT) - -#define SQ_REG_CREDITS_SET_IMMED_OVERFLOW__VI(sq_reg_credits_reg, immed_overflow) \ - sq_reg_credits_reg = (sq_reg_credits_reg & ~SQ_REG_CREDITS_IMMED_OVERFLOW_MASK) | \ - (immed_overflow << SQ_REG_CREDITS_IMMED_OVERFLOW_SHIFT) - -#define SQ_REG_CREDITS_SET_REG_BUSY__VI(sq_reg_credits_reg, reg_busy) \ - sq_reg_credits_reg = (sq_reg_credits_reg & ~SQ_REG_CREDITS_REG_BUSY_MASK) | \ - (reg_busy << SQ_REG_CREDITS_REG_BUSY_SHIFT) - -#define SQ_REG_CREDITS_SET_SRBM_CREDITS__VI(sq_reg_credits_reg, srbm_credits) \ - sq_reg_credits_reg = (sq_reg_credits_reg & ~SQ_REG_CREDITS_SRBM_CREDITS_MASK) | \ - (srbm_credits << SQ_REG_CREDITS_SRBM_CREDITS_SHIFT) - -#define SQ_REG_CREDITS_SET_SRBM_OVERFLOW__VI(sq_reg_credits_reg, srbm_overflow) \ - sq_reg_credits_reg = (sq_reg_credits_reg & ~SQ_REG_CREDITS_SRBM_OVERFLOW_MASK) | \ - (srbm_overflow << SQ_REG_CREDITS_SRBM_OVERFLOW_SHIFT) - -#define SQ_REG_TIMESTAMP_GET_TIMESTAMP__VI(sq_reg_timestamp) \ - ((sq_reg_timestamp & SQ_REG_TIMESTAMP_TIMESTAMP_MASK) >> SQ_REG_TIMESTAMP_TIMESTAMP_SHIFT) - -#define SQ_REG_TIMESTAMP_MASK__VI (SQ_REG_TIMESTAMP_TIMESTAMP_MASK) - -#define SQ_REG_TIMESTAMP_SET_TIMESTAMP__VI(sq_reg_timestamp_reg, timestamp) \ - sq_reg_timestamp_reg = (sq_reg_timestamp_reg & ~SQ_REG_TIMESTAMP_TIMESTAMP_MASK) | \ - (timestamp << SQ_REG_TIMESTAMP_TIMESTAMP_SHIFT) - -#define SQ_TEX_CLK_CTRL_GET_FORCE_CU_ON_SH0__VI(sq_tex_clk_ctrl) \ - ((sq_tex_clk_ctrl & SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_MASK) >> \ - SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT) - -#define SQ_TEX_CLK_CTRL_GET_FORCE_CU_ON_SH1__VI(sq_tex_clk_ctrl) \ - ((sq_tex_clk_ctrl & SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_MASK) >> \ - SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT) - -#define SQ_TEX_CLK_CTRL_MASK__VI \ - (SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_MASK | SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_MASK) - -#define SQ_TEX_CLK_CTRL_SET_FORCE_CU_ON_SH0__VI(sq_tex_clk_ctrl_reg, force_cu_on_sh0) \ - sq_tex_clk_ctrl_reg = (sq_tex_clk_ctrl_reg & ~SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_MASK) | \ - (force_cu_on_sh0 << SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH0_SHIFT) - -#define SQ_TEX_CLK_CTRL_SET_FORCE_CU_ON_SH1__VI(sq_tex_clk_ctrl_reg, force_cu_on_sh1) \ - sq_tex_clk_ctrl_reg = (sq_tex_clk_ctrl_reg & ~SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_MASK) | \ - (force_cu_on_sh1 << SQ_TEX_CLK_CTRL_FORCE_CU_ON_SH1_SHIFT) - -#define SQ_THREAD_TRACE_BASE2_GET_ADDR_HI__VI(sq_thread_trace_base2) \ - ((sq_thread_trace_base2 & SQ_THREAD_TRACE_BASE2_ADDR_HI_MASK) >> \ - SQ_THREAD_TRACE_BASE2_ADDR_HI_SHIFT) - -#define SQ_THREAD_TRACE_BASE2_MASK__VI (SQ_THREAD_TRACE_BASE2_ADDR_HI_MASK) - -#define SQ_THREAD_TRACE_BASE2_SET_ADDR_HI__VI(sq_thread_trace_base2_reg, addr_hi) \ - sq_thread_trace_base2_reg = (sq_thread_trace_base2_reg & ~SQ_THREAD_TRACE_BASE2_ADDR_HI_MASK) | \ - (addr_hi << SQ_THREAD_TRACE_BASE2_ADDR_HI_SHIFT) - -#define SQ_THREAD_TRACE_BASE_GET_ADDR__VI(sq_thread_trace_base) \ - ((sq_thread_trace_base & SQ_THREAD_TRACE_BASE_ADDR_MASK) >> SQ_THREAD_TRACE_BASE_ADDR_SHIFT) - -#define SQ_THREAD_TRACE_BASE_MASK__VI (SQ_THREAD_TRACE_BASE_ADDR_MASK) - -#define SQ_THREAD_TRACE_BASE_SET_ADDR__VI(sq_thread_trace_base_reg, addr) \ - sq_thread_trace_base_reg = (sq_thread_trace_base_reg & ~SQ_THREAD_TRACE_BASE_ADDR_MASK) | \ - (addr << SQ_THREAD_TRACE_BASE_ADDR_SHIFT) - -#define SQ_THREAD_TRACE_CNTR_GET_CNTR__VI(sq_thread_trace_cntr) \ - ((sq_thread_trace_cntr & SQ_THREAD_TRACE_CNTR_CNTR_MASK) >> SQ_THREAD_TRACE_CNTR_CNTR_SHIFT) - -#define SQ_THREAD_TRACE_CNTR_MASK__VI (SQ_THREAD_TRACE_CNTR_CNTR_MASK) - -#define SQ_THREAD_TRACE_CNTR_SET_CNTR__VI(sq_thread_trace_cntr_reg, cntr) \ - sq_thread_trace_cntr_reg = (sq_thread_trace_cntr_reg & ~SQ_THREAD_TRACE_CNTR_CNTR_MASK) | \ - (cntr << SQ_THREAD_TRACE_CNTR_CNTR_SHIFT) - -#define SQ_THREAD_TRACE_CTRL_GET_RESET_BUFFER__VI(sq_thread_trace_ctrl) \ - ((sq_thread_trace_ctrl & SQ_THREAD_TRACE_CTRL_RESET_BUFFER_MASK) >> \ - SQ_THREAD_TRACE_CTRL_RESET_BUFFER_SHIFT) - -#define SQ_THREAD_TRACE_CTRL_MASK__VI (SQ_THREAD_TRACE_CTRL_RESET_BUFFER_MASK) - -#define SQ_THREAD_TRACE_CTRL_SET_RESET_BUFFER__VI(sq_thread_trace_ctrl_reg, reset_buffer) \ - sq_thread_trace_ctrl_reg = \ - (sq_thread_trace_ctrl_reg & ~SQ_THREAD_TRACE_CTRL_RESET_BUFFER_MASK) | \ - (reset_buffer << SQ_THREAD_TRACE_CTRL_RESET_BUFFER_SHIFT) - -#define SQ_THREAD_TRACE_HIWATER_GET_HIWATER__VI(sq_thread_trace_hiwater) \ - ((sq_thread_trace_hiwater & SQ_THREAD_TRACE_HIWATER_HIWATER_MASK) >> \ - SQ_THREAD_TRACE_HIWATER_HIWATER_SHIFT) - -#define SQ_THREAD_TRACE_HIWATER_MASK__VI (SQ_THREAD_TRACE_HIWATER_HIWATER_MASK) - -#define SQ_THREAD_TRACE_HIWATER_SET_HIWATER__VI(sq_thread_trace_hiwater_reg, hiwater) \ - sq_thread_trace_hiwater_reg = \ - (sq_thread_trace_hiwater_reg & ~SQ_THREAD_TRACE_HIWATER_HIWATER_MASK) | \ - (hiwater << SQ_THREAD_TRACE_HIWATER_HIWATER_SHIFT) - -#define SQ_THREAD_TRACE_MASK_DEFAULT__VI 0x0000cf80 -#define SQ_THREAD_TRACE_MASK_GET_CU_SEL__VI(sq_thread_trace_mask) \ - ((sq_thread_trace_mask & SQ_THREAD_TRACE_MASK_CU_SEL_MASK) >> SQ_THREAD_TRACE_MASK_CU_SEL_SHIFT) - -#define SQ_THREAD_TRACE_MASK_GET_REG_STALL_EN__VI(sq_thread_trace_mask) \ - ((sq_thread_trace_mask & SQ_THREAD_TRACE_MASK_REG_STALL_EN_MASK) >> \ - SQ_THREAD_TRACE_MASK_REG_STALL_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_GET_SH_SEL__VI(sq_thread_trace_mask) \ - ((sq_thread_trace_mask & SQ_THREAD_TRACE_MASK_SH_SEL_MASK) >> SQ_THREAD_TRACE_MASK_SH_SEL_SHIFT) - -#define SQ_THREAD_TRACE_MASK_GET_SIMD_EN__VI(sq_thread_trace_mask) \ - ((sq_thread_trace_mask & SQ_THREAD_TRACE_MASK_SIMD_EN_MASK) >> SQ_THREAD_TRACE_MASK_SIMD_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_GET_SPI_STALL_EN__VI(sq_thread_trace_mask) \ - ((sq_thread_trace_mask & SQ_THREAD_TRACE_MASK_SPI_STALL_EN_MASK) >> \ - SQ_THREAD_TRACE_MASK_SPI_STALL_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_GET_SQ_STALL_EN__VI(sq_thread_trace_mask) \ - ((sq_thread_trace_mask & SQ_THREAD_TRACE_MASK_SQ_STALL_EN_MASK) >> \ - SQ_THREAD_TRACE_MASK_SQ_STALL_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_GET_VM_ID_MASK__VI(sq_thread_trace_mask) \ - ((sq_thread_trace_mask & SQ_THREAD_TRACE_MASK_VM_ID_MASK_MASK) >> \ - SQ_THREAD_TRACE_MASK_VM_ID_MASK_SHIFT) - -#define SQ_THREAD_TRACE_MASK_MASK__VI \ - (SQ_THREAD_TRACE_MASK_CU_SEL_MASK | SQ_THREAD_TRACE_MASK_SH_SEL_MASK | \ - SQ_THREAD_TRACE_MASK_REG_STALL_EN_MASK | SQ_THREAD_TRACE_MASK_SIMD_EN_MASK | \ - SQ_THREAD_TRACE_MASK_VM_ID_MASK_MASK | SQ_THREAD_TRACE_MASK_SPI_STALL_EN_MASK | \ - SQ_THREAD_TRACE_MASK_SQ_STALL_EN_MASK) - -#define SQ_THREAD_TRACE_MASK_SET_CU_SEL__VI(sq_thread_trace_mask_reg, cu_sel) \ - sq_thread_trace_mask_reg = (sq_thread_trace_mask_reg & ~SQ_THREAD_TRACE_MASK_CU_SEL_MASK) | \ - (cu_sel << SQ_THREAD_TRACE_MASK_CU_SEL_SHIFT) - -#define SQ_THREAD_TRACE_MASK_SET_REG_STALL_EN__VI(sq_thread_trace_mask_reg, reg_stall_en) \ - sq_thread_trace_mask_reg = \ - (sq_thread_trace_mask_reg & ~SQ_THREAD_TRACE_MASK_REG_STALL_EN_MASK) | \ - (reg_stall_en << SQ_THREAD_TRACE_MASK_REG_STALL_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_SET_SH_SEL__VI(sq_thread_trace_mask_reg, sh_sel) \ - sq_thread_trace_mask_reg = (sq_thread_trace_mask_reg & ~SQ_THREAD_TRACE_MASK_SH_SEL_MASK) | \ - (sh_sel << SQ_THREAD_TRACE_MASK_SH_SEL_SHIFT) - -#define SQ_THREAD_TRACE_MASK_SET_SIMD_EN__VI(sq_thread_trace_mask_reg, simd_en) \ - sq_thread_trace_mask_reg = (sq_thread_trace_mask_reg & ~SQ_THREAD_TRACE_MASK_SIMD_EN_MASK) | \ - (simd_en << SQ_THREAD_TRACE_MASK_SIMD_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_SET_SPI_STALL_EN__VI(sq_thread_trace_mask_reg, spi_stall_en) \ - sq_thread_trace_mask_reg = \ - (sq_thread_trace_mask_reg & ~SQ_THREAD_TRACE_MASK_SPI_STALL_EN_MASK) | \ - (spi_stall_en << SQ_THREAD_TRACE_MASK_SPI_STALL_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_SET_SQ_STALL_EN__VI(sq_thread_trace_mask_reg, sq_stall_en) \ - sq_thread_trace_mask_reg = (sq_thread_trace_mask_reg & ~SQ_THREAD_TRACE_MASK_SQ_STALL_EN_MASK) | \ - (sq_stall_en << SQ_THREAD_TRACE_MASK_SQ_STALL_EN_SHIFT) - -#define SQ_THREAD_TRACE_MASK_SET_VM_ID_MASK__VI(sq_thread_trace_mask_reg, vm_id_mask) \ - sq_thread_trace_mask_reg = (sq_thread_trace_mask_reg & ~SQ_THREAD_TRACE_MASK_VM_ID_MASK_MASK) | \ - (vm_id_mask << SQ_THREAD_TRACE_MASK_VM_ID_MASK_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_AUTOFLUSH_EN__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_MASK) >> \ - SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_CAPTURE_MODE__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_CAPTURE_MODE_MASK) >> \ - SQ_THREAD_TRACE_MODE_CAPTURE_MODE_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_INTERRUPT_EN__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_INTERRUPT_EN_MASK) >> \ - SQ_THREAD_TRACE_MODE_INTERRUPT_EN_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_ISSUE_MASK__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_ISSUE_MASK_MASK) >> \ - SQ_THREAD_TRACE_MODE_ISSUE_MASK_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MASK_CS__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MASK_CS_MASK) >> SQ_THREAD_TRACE_MODE_MASK_CS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MASK_ES__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MASK_ES_MASK) >> SQ_THREAD_TRACE_MODE_MASK_ES_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MASK_GS__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MASK_GS_MASK) >> SQ_THREAD_TRACE_MODE_MASK_GS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MASK_HS__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MASK_HS_MASK) >> SQ_THREAD_TRACE_MODE_MASK_HS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MASK_LS__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MASK_LS_MASK) >> SQ_THREAD_TRACE_MODE_MASK_LS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MASK_PS__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MASK_PS_MASK) >> SQ_THREAD_TRACE_MODE_MASK_PS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MASK_VS__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MASK_VS_MASK) >> SQ_THREAD_TRACE_MODE_MASK_VS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_MODE__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_MODE_MASK) >> SQ_THREAD_TRACE_MODE_MODE_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_PRIV__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_PRIV_MASK) >> SQ_THREAD_TRACE_MODE_PRIV_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_TEST_MODE__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_TEST_MODE_MASK) >> \ - SQ_THREAD_TRACE_MODE_TEST_MODE_SHIFT) - -#define SQ_THREAD_TRACE_MODE_GET_WRAP__VI(sq_thread_trace_mode) \ - ((sq_thread_trace_mode & SQ_THREAD_TRACE_MODE_WRAP_MASK) >> SQ_THREAD_TRACE_MODE_WRAP_SHIFT) - -#define SQ_THREAD_TRACE_MODE_MASK__VI \ - (SQ_THREAD_TRACE_MODE_MASK_PS_MASK | SQ_THREAD_TRACE_MODE_MASK_VS_MASK | \ - SQ_THREAD_TRACE_MODE_MASK_GS_MASK | SQ_THREAD_TRACE_MODE_MASK_ES_MASK | \ - SQ_THREAD_TRACE_MODE_MASK_HS_MASK | SQ_THREAD_TRACE_MODE_MASK_LS_MASK | \ - SQ_THREAD_TRACE_MODE_MASK_CS_MASK | SQ_THREAD_TRACE_MODE_MODE_MASK | \ - SQ_THREAD_TRACE_MODE_CAPTURE_MODE_MASK | SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_MASK | \ - SQ_THREAD_TRACE_MODE_PRIV_MASK | SQ_THREAD_TRACE_MODE_ISSUE_MASK_MASK | \ - SQ_THREAD_TRACE_MODE_TEST_MODE_MASK | SQ_THREAD_TRACE_MODE_INTERRUPT_EN_MASK | \ - SQ_THREAD_TRACE_MODE_WRAP_MASK) - -#define SQ_THREAD_TRACE_MODE_SET_AUTOFLUSH_EN__VI(sq_thread_trace_mode_reg, autoflush_en) \ - sq_thread_trace_mode_reg = \ - (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_MASK) | \ - (autoflush_en << SQ_THREAD_TRACE_MODE_AUTOFLUSH_EN_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_CAPTURE_MODE__VI(sq_thread_trace_mode_reg, capture_mode) \ - sq_thread_trace_mode_reg = \ - (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_CAPTURE_MODE_MASK) | \ - (capture_mode << SQ_THREAD_TRACE_MODE_CAPTURE_MODE_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_INTERRUPT_EN__VI(sq_thread_trace_mode_reg, interrupt_en) \ - sq_thread_trace_mode_reg = \ - (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_INTERRUPT_EN_MASK) | \ - (interrupt_en << SQ_THREAD_TRACE_MODE_INTERRUPT_EN_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_ISSUE_MASK__VI(sq_thread_trace_mode_reg, issue_mask) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_ISSUE_MASK_MASK) | \ - (issue_mask << SQ_THREAD_TRACE_MODE_ISSUE_MASK_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MASK_CS__VI(sq_thread_trace_mode_reg, mask_cs) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MASK_CS_MASK) | \ - (mask_cs << SQ_THREAD_TRACE_MODE_MASK_CS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MASK_ES__VI(sq_thread_trace_mode_reg, mask_es) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MASK_ES_MASK) | \ - (mask_es << SQ_THREAD_TRACE_MODE_MASK_ES_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MASK_GS__VI(sq_thread_trace_mode_reg, mask_gs) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MASK_GS_MASK) | \ - (mask_gs << SQ_THREAD_TRACE_MODE_MASK_GS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MASK_HS__VI(sq_thread_trace_mode_reg, mask_hs) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MASK_HS_MASK) | \ - (mask_hs << SQ_THREAD_TRACE_MODE_MASK_HS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MASK_LS__VI(sq_thread_trace_mode_reg, mask_ls) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MASK_LS_MASK) | \ - (mask_ls << SQ_THREAD_TRACE_MODE_MASK_LS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MASK_PS__VI(sq_thread_trace_mode_reg, mask_ps) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MASK_PS_MASK) | \ - (mask_ps << SQ_THREAD_TRACE_MODE_MASK_PS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MASK_VS__VI(sq_thread_trace_mode_reg, mask_vs) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MASK_VS_MASK) | \ - (mask_vs << SQ_THREAD_TRACE_MODE_MASK_VS_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_MODE__VI(sq_thread_trace_mode_reg, mode) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_MODE_MASK) | \ - (mode << SQ_THREAD_TRACE_MODE_MODE_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_PRIV__VI(sq_thread_trace_mode_reg, priv) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_PRIV_MASK) | \ - (priv << SQ_THREAD_TRACE_MODE_PRIV_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_TEST_MODE__VI(sq_thread_trace_mode_reg, test_mode) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_TEST_MODE_MASK) | \ - (test_mode << SQ_THREAD_TRACE_MODE_TEST_MODE_SHIFT) - -#define SQ_THREAD_TRACE_MODE_SET_WRAP__VI(sq_thread_trace_mode_reg, wrap) \ - sq_thread_trace_mode_reg = (sq_thread_trace_mode_reg & ~SQ_THREAD_TRACE_MODE_WRAP_MASK) | \ - (wrap << SQ_THREAD_TRACE_MODE_WRAP_SHIFT) - -#define SQ_THREAD_TRACE_PERF_MASK_GET_SH0_MASK__VI(sq_thread_trace_perf_mask) \ - ((sq_thread_trace_perf_mask & SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_MASK) >> \ - SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_SHIFT) - -#define SQ_THREAD_TRACE_PERF_MASK_GET_SH1_MASK__VI(sq_thread_trace_perf_mask) \ - ((sq_thread_trace_perf_mask & SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_MASK) >> \ - SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_SHIFT) - -#define SQ_THREAD_TRACE_PERF_MASK_MASK__VI \ - (SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_MASK | SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_MASK) - -#define SQ_THREAD_TRACE_PERF_MASK_SET_SH0_MASK__VI(sq_thread_trace_perf_mask_reg, sh0_mask) \ - sq_thread_trace_perf_mask_reg = \ - (sq_thread_trace_perf_mask_reg & ~SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_MASK) | \ - (sh0_mask << SQ_THREAD_TRACE_PERF_MASK_SH0_MASK_SHIFT) - -#define SQ_THREAD_TRACE_PERF_MASK_SET_SH1_MASK__VI(sq_thread_trace_perf_mask_reg, sh1_mask) \ - sq_thread_trace_perf_mask_reg = \ - (sq_thread_trace_perf_mask_reg & ~SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_MASK) | \ - (sh1_mask << SQ_THREAD_TRACE_PERF_MASK_SH1_MASK_SHIFT) - -#define SQ_THREAD_TRACE_SIZE_GET_SIZE__VI(sq_thread_trace_size) \ - ((sq_thread_trace_size & SQ_THREAD_TRACE_SIZE_SIZE_MASK) >> SQ_THREAD_TRACE_SIZE_SIZE_SHIFT) - -#define SQ_THREAD_TRACE_SIZE_MASK__VI (SQ_THREAD_TRACE_SIZE_SIZE_MASK) - -#define SQ_THREAD_TRACE_SIZE_SET_SIZE__VI(sq_thread_trace_size_reg, size) \ - sq_thread_trace_size_reg = (sq_thread_trace_size_reg & ~SQ_THREAD_TRACE_SIZE_SIZE_MASK) | \ - (size << SQ_THREAD_TRACE_SIZE_SIZE_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_GET_BUSY__VI(sq_thread_trace_status) \ - ((sq_thread_trace_status & SQ_THREAD_TRACE_STATUS_BUSY_MASK) >> SQ_THREAD_TRACE_STATUS_BUSY_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_GET_FINISH_DONE__VI(sq_thread_trace_status) \ - ((sq_thread_trace_status & SQ_THREAD_TRACE_STATUS_FINISH_DONE_MASK) >> \ - SQ_THREAD_TRACE_STATUS_FINISH_DONE_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_GET_FINISH_PENDING__VI(sq_thread_trace_status) \ - ((sq_thread_trace_status & SQ_THREAD_TRACE_STATUS_FINISH_PENDING_MASK) >> \ - SQ_THREAD_TRACE_STATUS_FINISH_PENDING_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_GET_FULL__VI(sq_thread_trace_status) \ - ((sq_thread_trace_status & SQ_THREAD_TRACE_STATUS_FULL_MASK) >> SQ_THREAD_TRACE_STATUS_FULL_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_GET_NEW_BUF__VI(sq_thread_trace_status) \ - ((sq_thread_trace_status & SQ_THREAD_TRACE_STATUS_NEW_BUF_MASK) >> \ - SQ_THREAD_TRACE_STATUS_NEW_BUF_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_MASK__VI \ - (SQ_THREAD_TRACE_STATUS_FINISH_PENDING_MASK | SQ_THREAD_TRACE_STATUS_FINISH_DONE_MASK | \ - SQ_THREAD_TRACE_STATUS_NEW_BUF_MASK | SQ_THREAD_TRACE_STATUS_BUSY_MASK | \ - SQ_THREAD_TRACE_STATUS_FULL_MASK) - -#define SQ_THREAD_TRACE_STATUS_SET_BUSY__VI(sq_thread_trace_status_reg, busy) \ - sq_thread_trace_status_reg = (sq_thread_trace_status_reg & ~SQ_THREAD_TRACE_STATUS_BUSY_MASK) | \ - (busy << SQ_THREAD_TRACE_STATUS_BUSY_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_SET_FINISH_DONE__VI(sq_thread_trace_status_reg, finish_done) \ - sq_thread_trace_status_reg = \ - (sq_thread_trace_status_reg & ~SQ_THREAD_TRACE_STATUS_FINISH_DONE_MASK) | \ - (finish_done << SQ_THREAD_TRACE_STATUS_FINISH_DONE_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_SET_FINISH_PENDING__VI(sq_thread_trace_status_reg, finish_pending) \ - sq_thread_trace_status_reg = \ - (sq_thread_trace_status_reg & ~SQ_THREAD_TRACE_STATUS_FINISH_PENDING_MASK) | \ - (finish_pending << SQ_THREAD_TRACE_STATUS_FINISH_PENDING_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_SET_FULL__VI(sq_thread_trace_status_reg, full) \ - sq_thread_trace_status_reg = (sq_thread_trace_status_reg & ~SQ_THREAD_TRACE_STATUS_FULL_MASK) | \ - (full << SQ_THREAD_TRACE_STATUS_FULL_SHIFT) - -#define SQ_THREAD_TRACE_STATUS_SET_NEW_BUF__VI(sq_thread_trace_status_reg, new_buf) \ - sq_thread_trace_status_reg = \ - (sq_thread_trace_status_reg & ~SQ_THREAD_TRACE_STATUS_NEW_BUF_MASK) | \ - (new_buf << SQ_THREAD_TRACE_STATUS_NEW_BUF_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT__VI 0xffffffff -#define SQ_THREAD_TRACE_TOKEN_MASK2_GET_INST_MASK__VI(sq_thread_trace_token_mask2) \ - ((sq_thread_trace_token_mask2 & SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_MASK) >> \ - SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_MASK__VI 0xffffffff -#define SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_SIZE__VI 32 -#define SQ_THREAD_TRACE_TOKEN_MASK2_MASK__VI (SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_MASK) - -#define SQ_THREAD_TRACE_TOKEN_MASK2_SET_INST_MASK__VI(sq_thread_trace_token_mask2_reg, inst_mask) \ - sq_thread_trace_token_mask2_reg = \ - (sq_thread_trace_token_mask2_reg & ~SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_MASK) | \ - (inst_mask << SQ_THREAD_TRACE_TOKEN_MASK2_INST_MASK_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK_GET_REG_DROP_ON_STALL__VI(sq_thread_trace_token_mask) \ - ((sq_thread_trace_token_mask & SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_MASK) >> \ - SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK_GET_REG_MASK__VI(sq_thread_trace_token_mask) \ - ((sq_thread_trace_token_mask & SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_MASK) >> \ - SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK_GET_TOKEN_MASK__VI(sq_thread_trace_token_mask) \ - ((sq_thread_trace_token_mask & SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_MASK) >> \ - SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK_MASK__VI \ - (SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_MASK | SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_MASK | \ - SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_MASK) - -#define SQ_THREAD_TRACE_TOKEN_MASK_SET_REG_DROP_ON_STALL__VI(sq_thread_trace_token_mask_reg, \ - reg_drop_on_stall) \ - sq_thread_trace_token_mask_reg = \ - (sq_thread_trace_token_mask_reg & ~SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_MASK) | \ - (reg_drop_on_stall << SQ_THREAD_TRACE_TOKEN_MASK_REG_DROP_ON_STALL_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK_SET_REG_MASK__VI(sq_thread_trace_token_mask_reg, reg_mask) \ - sq_thread_trace_token_mask_reg = \ - (sq_thread_trace_token_mask_reg & ~SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_MASK) | \ - (reg_mask << SQ_THREAD_TRACE_TOKEN_MASK_REG_MASK_SHIFT) - -#define SQ_THREAD_TRACE_TOKEN_MASK_SET_TOKEN_MASK__VI(sq_thread_trace_token_mask_reg, token_mask) \ - sq_thread_trace_token_mask_reg = \ - (sq_thread_trace_token_mask_reg & ~SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_MASK) | \ - (token_mask << SQ_THREAD_TRACE_TOKEN_MASK_TOKEN_MASK_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_0_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_0_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_USERDATA_0_GET_DATA__VI(sq_thread_trace_userdata_0) \ - ((sq_thread_trace_userdata_0 & SQ_THREAD_TRACE_USERDATA_0_DATA_MASK) >> \ - SQ_THREAD_TRACE_USERDATA_0_DATA_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_0_MASK__VI (SQ_THREAD_TRACE_USERDATA_0_DATA_MASK) - -#define SQ_THREAD_TRACE_USERDATA_0_SET_DATA__VI(sq_thread_trace_userdata_0_reg, data) \ - sq_thread_trace_userdata_0_reg = \ - (sq_thread_trace_userdata_0_reg & ~SQ_THREAD_TRACE_USERDATA_0_DATA_MASK) | \ - (data << SQ_THREAD_TRACE_USERDATA_0_DATA_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_1_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_1_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_USERDATA_1_GET_DATA__VI(sq_thread_trace_userdata_1) \ - ((sq_thread_trace_userdata_1 & SQ_THREAD_TRACE_USERDATA_1_DATA_MASK) >> \ - SQ_THREAD_TRACE_USERDATA_1_DATA_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_1_MASK__VI (SQ_THREAD_TRACE_USERDATA_1_DATA_MASK) - -#define SQ_THREAD_TRACE_USERDATA_1_SET_DATA__VI(sq_thread_trace_userdata_1_reg, data) \ - sq_thread_trace_userdata_1_reg = \ - (sq_thread_trace_userdata_1_reg & ~SQ_THREAD_TRACE_USERDATA_1_DATA_MASK) | \ - (data << SQ_THREAD_TRACE_USERDATA_1_DATA_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_USERDATA_2_GET_DATA__VI(sq_thread_trace_userdata_2) \ - ((sq_thread_trace_userdata_2 & SQ_THREAD_TRACE_USERDATA_2_DATA_MASK) >> \ - SQ_THREAD_TRACE_USERDATA_2_DATA_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_2_MASK__VI (SQ_THREAD_TRACE_USERDATA_2_DATA_MASK) - -#define SQ_THREAD_TRACE_USERDATA_2_SET_DATA__VI(sq_thread_trace_userdata_2_reg, data) \ - sq_thread_trace_userdata_2_reg = \ - (sq_thread_trace_userdata_2_reg & ~SQ_THREAD_TRACE_USERDATA_2_DATA_MASK) | \ - (data << SQ_THREAD_TRACE_USERDATA_2_DATA_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_3_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_USERDATA_3_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_USERDATA_3_GET_DATA__VI(sq_thread_trace_userdata_3) \ - ((sq_thread_trace_userdata_3 & SQ_THREAD_TRACE_USERDATA_3_DATA_MASK) >> \ - SQ_THREAD_TRACE_USERDATA_3_DATA_SHIFT) - -#define SQ_THREAD_TRACE_USERDATA_3_MASK__VI (SQ_THREAD_TRACE_USERDATA_3_DATA_MASK) - -#define SQ_THREAD_TRACE_USERDATA_3_SET_DATA__VI(sq_thread_trace_userdata_3_reg, data) \ - sq_thread_trace_userdata_3_reg = \ - (sq_thread_trace_userdata_3_reg & ~SQ_THREAD_TRACE_USERDATA_3_DATA_MASK) | \ - (data << SQ_THREAD_TRACE_USERDATA_3_DATA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_CMN_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_CMN_DEFAULT__VI 0x0000000d -#define SQ_THREAD_TRACE_WORD_CMN_GET_TIME_DELTA__VI(sq_thread_trace_word_cmn) \ - ((sq_thread_trace_word_cmn & SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_CMN_GET_TOKEN_TYPE__VI(sq_thread_trace_word_cmn) \ - ((sq_thread_trace_word_cmn & SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_CMN_MASK__VI \ - (SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_MASK | SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_MASK) - -#define SQ_THREAD_TRACE_WORD_CMN_SET_TIME_DELTA__VI(sq_thread_trace_word_cmn_reg, time_delta) \ - sq_thread_trace_word_cmn_reg = \ - (sq_thread_trace_word_cmn_reg & ~SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_CMN_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_CMN_SET_TOKEN_TYPE__VI(sq_thread_trace_word_cmn_reg, token_type) \ - sq_thread_trace_word_cmn_reg = \ - (sq_thread_trace_word_cmn_reg & ~SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_CMN_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_EVENT_DEFAULT__VI 0x0000cdcd -#define SQ_THREAD_TRACE_WORD_EVENT_GET_EVENT_TYPE__VI(sq_thread_trace_word_event) \ - ((sq_thread_trace_word_event & SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_GET_SH_ID__VI(sq_thread_trace_word_event) \ - ((sq_thread_trace_word_event & SQ_THREAD_TRACE_WORD_EVENT_SH_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_EVENT_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_GET_STAGE__VI(sq_thread_trace_word_event) \ - ((sq_thread_trace_word_event & SQ_THREAD_TRACE_WORD_EVENT_STAGE_MASK) >> \ - SQ_THREAD_TRACE_WORD_EVENT_STAGE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_GET_TIME_DELTA__VI(sq_thread_trace_word_event) \ - ((sq_thread_trace_word_event & SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_GET_TOKEN_TYPE__VI(sq_thread_trace_word_event) \ - ((sq_thread_trace_word_event & SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_MASK__VI \ - (SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_MASK | SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_EVENT_SH_ID_MASK | SQ_THREAD_TRACE_WORD_EVENT_STAGE_MASK | \ - SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_MASK) - -#define SQ_THREAD_TRACE_WORD_EVENT_SET_EVENT_TYPE__VI(sq_thread_trace_word_event_reg, event_type) \ - sq_thread_trace_word_event_reg = \ - (sq_thread_trace_word_event_reg & ~SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_MASK) | \ - (event_type << SQ_THREAD_TRACE_WORD_EVENT_EVENT_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_SET_SH_ID__VI(sq_thread_trace_word_event_reg, sh_id) \ - sq_thread_trace_word_event_reg = \ - (sq_thread_trace_word_event_reg & ~SQ_THREAD_TRACE_WORD_EVENT_SH_ID_MASK) | \ - (sh_id << SQ_THREAD_TRACE_WORD_EVENT_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_SET_STAGE__VI(sq_thread_trace_word_event_reg, stage) \ - sq_thread_trace_word_event_reg = \ - (sq_thread_trace_word_event_reg & ~SQ_THREAD_TRACE_WORD_EVENT_STAGE_MASK) | \ - (stage << SQ_THREAD_TRACE_WORD_EVENT_STAGE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_SET_TIME_DELTA__VI(sq_thread_trace_word_event_reg, time_delta) \ - sq_thread_trace_word_event_reg = \ - (sq_thread_trace_word_event_reg & ~SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_EVENT_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_EVENT_SET_TOKEN_TYPE__VI(sq_thread_trace_word_event_reg, token_type) \ - sq_thread_trace_word_event_reg = \ - (sq_thread_trace_word_event_reg & ~SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_EVENT_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_DEFAULT__VI 0x0000cdcd -#define SQ_THREAD_TRACE_WORD_INST_GET_INST_TYPE__VI(sq_thread_trace_word_inst) \ - ((sq_thread_trace_word_inst & SQ_THREAD_TRACE_WORD_INST_INST_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_INST_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_GET_SIMD_ID__VI(sq_thread_trace_word_inst) \ - ((sq_thread_trace_word_inst & SQ_THREAD_TRACE_WORD_INST_SIMD_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_GET_TIME_DELTA__VI(sq_thread_trace_word_inst) \ - ((sq_thread_trace_word_inst & SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_GET_TOKEN_TYPE__VI(sq_thread_trace_word_inst) \ - ((sq_thread_trace_word_inst & SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_GET_WAVE_ID__VI(sq_thread_trace_word_inst) \ - ((sq_thread_trace_word_inst & SQ_THREAD_TRACE_WORD_INST_WAVE_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_INST_TYPE_MASK__SI__CI 0x0000f000 -#define SQ_THREAD_TRACE_WORD_INST_INST_TYPE_MASK__VI 0x0000f800 -#define SQ_THREAD_TRACE_WORD_INST_INST_TYPE_SHIFT__SI__CI 12 -#define SQ_THREAD_TRACE_WORD_INST_INST_TYPE_SHIFT__VI 11 -#define SQ_THREAD_TRACE_WORD_INST_INST_TYPE_SIZE__SI__CI 4 -#define SQ_THREAD_TRACE_WORD_INST_INST_TYPE_SIZE__VI 5 -#define SQ_THREAD_TRACE_WORD_INST_MASK__VI \ - (SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_MASK | SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_INST_WAVE_ID_MASK | SQ_THREAD_TRACE_WORD_INST_SIMD_ID_MASK | \ - SQ_THREAD_TRACE_WORD_INST_INST_TYPE_MASK) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT__VI 0xcdcd05cd -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_GET_PC_LO__VI(sq_thread_trace_word_inst_pc_1_of_2) \ - ((sq_thread_trace_word_inst_pc_1_of_2 & SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_GET_SIMD_ID__VI(sq_thread_trace_word_inst_pc_1_of_2) \ - ((sq_thread_trace_word_inst_pc_1_of_2 & SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_GET_TIME_DELTA__VI( \ - sq_thread_trace_word_inst_pc_1_of_2) \ - ((sq_thread_trace_word_inst_pc_1_of_2 & SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_GET_TOKEN_TYPE__VI( \ - sq_thread_trace_word_inst_pc_1_of_2) \ - ((sq_thread_trace_word_inst_pc_1_of_2 & SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_GET_WAVE_ID__VI(sq_thread_trace_word_inst_pc_1_of_2) \ - ((sq_thread_trace_word_inst_pc_1_of_2 & SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_MASK | \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_MASK | \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_MASK | \ - SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_MASK) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SET_PC_LO__VI(sq_thread_trace_word_inst_pc_1_of_2_reg, \ - pc_lo) \ - sq_thread_trace_word_inst_pc_1_of_2_reg = (sq_thread_trace_word_inst_pc_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_MASK) | \ - (pc_lo << SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_PC_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SET_SIMD_ID__VI( \ - sq_thread_trace_word_inst_pc_1_of_2_reg, simd_id) \ - sq_thread_trace_word_inst_pc_1_of_2_reg = (sq_thread_trace_word_inst_pc_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_MASK) | \ - (simd_id << SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SET_TIME_DELTA__VI( \ - sq_thread_trace_word_inst_pc_1_of_2_reg, time_delta) \ - sq_thread_trace_word_inst_pc_1_of_2_reg = \ - (sq_thread_trace_word_inst_pc_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SET_TOKEN_TYPE__VI( \ - sq_thread_trace_word_inst_pc_1_of_2_reg, token_type) \ - sq_thread_trace_word_inst_pc_1_of_2_reg = \ - (sq_thread_trace_word_inst_pc_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_SET_WAVE_ID__VI( \ - sq_thread_trace_word_inst_pc_1_of_2_reg, wave_id) \ - sq_thread_trace_word_inst_pc_1_of_2_reg = (sq_thread_trace_word_inst_pc_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_MASK) | \ - (wave_id << SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT__VI 0x00cdcdcd -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_GET_PC_HI__VI(sq_thread_trace_word_inst_pc_2_of_2) \ - ((sq_thread_trace_word_inst_pc_2_of_2 & SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_MASK) - -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_SET_PC_HI__VI(sq_thread_trace_word_inst_pc_2_of_2_reg, \ - pc_hi) \ - sq_thread_trace_word_inst_pc_2_of_2_reg = (sq_thread_trace_word_inst_pc_2_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_MASK) | \ - (pc_hi << SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_PC_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_SET_INST_TYPE__VI(sq_thread_trace_word_inst_reg, inst_type) \ - sq_thread_trace_word_inst_reg = \ - (sq_thread_trace_word_inst_reg & ~SQ_THREAD_TRACE_WORD_INST_INST_TYPE_MASK) | \ - (inst_type << SQ_THREAD_TRACE_WORD_INST_INST_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_SET_SIMD_ID__VI(sq_thread_trace_word_inst_reg, simd_id) \ - sq_thread_trace_word_inst_reg = \ - (sq_thread_trace_word_inst_reg & ~SQ_THREAD_TRACE_WORD_INST_SIMD_ID_MASK) | \ - (simd_id << SQ_THREAD_TRACE_WORD_INST_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_SET_TIME_DELTA__VI(sq_thread_trace_word_inst_reg, time_delta) \ - sq_thread_trace_word_inst_reg = \ - (sq_thread_trace_word_inst_reg & ~SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_INST_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_SET_TOKEN_TYPE__VI(sq_thread_trace_word_inst_reg, token_type) \ - sq_thread_trace_word_inst_reg = \ - (sq_thread_trace_word_inst_reg & ~SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_INST_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_SET_WAVE_ID__VI(sq_thread_trace_word_inst_reg, wave_id) \ - sq_thread_trace_word_inst_reg = \ - (sq_thread_trace_word_inst_reg & ~SQ_THREAD_TRACE_WORD_INST_WAVE_ID_MASK) | \ - (wave_id << SQ_THREAD_TRACE_WORD_INST_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_GET_CU_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2) \ - ((sq_thread_trace_word_inst_userdata_1_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_GET_DATA_LO__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2) \ - ((sq_thread_trace_word_inst_userdata_1_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_GET_SH_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2) \ - ((sq_thread_trace_word_inst_userdata_1_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_GET_SIMD_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2) \ - ((sq_thread_trace_word_inst_userdata_1_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_GET_TIME_DELTA__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2) \ - ((sq_thread_trace_word_inst_userdata_1_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_GET_TOKEN_TYPE__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2) \ - ((sq_thread_trace_word_inst_userdata_1_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_GET_WAVE_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2) \ - ((sq_thread_trace_word_inst_userdata_1_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_MASK | \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_MASK | \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_MASK | \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_MASK | \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_MASK | \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_MASK) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SET_CU_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2_reg, cu_id) \ - sq_thread_trace_word_inst_userdata_1_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_MASK) | \ - (cu_id << SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SET_DATA_LO__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2_reg, data_lo) \ - sq_thread_trace_word_inst_userdata_1_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_MASK) | \ - (data_lo << SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DATA_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SET_SH_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2_reg, sh_id) \ - sq_thread_trace_word_inst_userdata_1_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_MASK) | \ - (sh_id << SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SET_SIMD_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2_reg, simd_id) \ - sq_thread_trace_word_inst_userdata_1_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_MASK) | \ - (simd_id << SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SET_TIME_DELTA__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2_reg, time_delta) \ - sq_thread_trace_word_inst_userdata_1_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SET_TOKEN_TYPE__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2_reg, token_type) \ - sq_thread_trace_word_inst_userdata_1_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_SET_WAVE_ID__VI( \ - sq_thread_trace_word_inst_userdata_1_of_2_reg, wave_id) \ - sq_thread_trace_word_inst_userdata_1_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_MASK) | \ - (wave_id << SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT__VI 0x0000cdcd -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_GET_DATA_HI__VI( \ - sq_thread_trace_word_inst_userdata_2_of_2) \ - ((sq_thread_trace_word_inst_userdata_2_of_2 & \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_MASK) >> \ - SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_MASK) - -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_SET_DATA_HI__VI( \ - sq_thread_trace_word_inst_userdata_2_of_2_reg, data_hi) \ - sq_thread_trace_word_inst_userdata_2_of_2_reg = \ - (sq_thread_trace_word_inst_userdata_2_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_MASK) | \ - (data_hi << SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DATA_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_ISSUE_DEFAULT__VI 0x0dcdcd4d -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST0__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST0_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST0_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST1__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST1_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST1_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST2__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST2_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST2_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST3__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST3_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST3_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST4__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST4_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST4_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST5__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST5_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST5_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST6__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST6_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST6_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST7__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST7_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST7_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST8__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST8_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST8_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_INST9__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_INST9_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_INST9_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_SIMD_ID__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_TIME_DELTA__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_GET_TOKEN_TYPE__VI(sq_thread_trace_word_issue) \ - ((sq_thread_trace_word_issue & SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_MASK__VI \ - (SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_MASK | SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_MASK | SQ_THREAD_TRACE_WORD_ISSUE_INST0_MASK | \ - SQ_THREAD_TRACE_WORD_ISSUE_INST1_MASK | SQ_THREAD_TRACE_WORD_ISSUE_INST2_MASK | \ - SQ_THREAD_TRACE_WORD_ISSUE_INST3_MASK | SQ_THREAD_TRACE_WORD_ISSUE_INST4_MASK | \ - SQ_THREAD_TRACE_WORD_ISSUE_INST5_MASK | SQ_THREAD_TRACE_WORD_ISSUE_INST6_MASK | \ - SQ_THREAD_TRACE_WORD_ISSUE_INST7_MASK | SQ_THREAD_TRACE_WORD_ISSUE_INST8_MASK | \ - SQ_THREAD_TRACE_WORD_ISSUE_INST9_MASK) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST0__VI(sq_thread_trace_word_issue_reg, inst0) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST0_MASK) | \ - (inst0 << SQ_THREAD_TRACE_WORD_ISSUE_INST0_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST1__VI(sq_thread_trace_word_issue_reg, inst1) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST1_MASK) | \ - (inst1 << SQ_THREAD_TRACE_WORD_ISSUE_INST1_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST2__VI(sq_thread_trace_word_issue_reg, inst2) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST2_MASK) | \ - (inst2 << SQ_THREAD_TRACE_WORD_ISSUE_INST2_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST3__VI(sq_thread_trace_word_issue_reg, inst3) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST3_MASK) | \ - (inst3 << SQ_THREAD_TRACE_WORD_ISSUE_INST3_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST4__VI(sq_thread_trace_word_issue_reg, inst4) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST4_MASK) | \ - (inst4 << SQ_THREAD_TRACE_WORD_ISSUE_INST4_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST5__VI(sq_thread_trace_word_issue_reg, inst5) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST5_MASK) | \ - (inst5 << SQ_THREAD_TRACE_WORD_ISSUE_INST5_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST6__VI(sq_thread_trace_word_issue_reg, inst6) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST6_MASK) | \ - (inst6 << SQ_THREAD_TRACE_WORD_ISSUE_INST6_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST7__VI(sq_thread_trace_word_issue_reg, inst7) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST7_MASK) | \ - (inst7 << SQ_THREAD_TRACE_WORD_ISSUE_INST7_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST8__VI(sq_thread_trace_word_issue_reg, inst8) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST8_MASK) | \ - (inst8 << SQ_THREAD_TRACE_WORD_ISSUE_INST8_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_INST9__VI(sq_thread_trace_word_issue_reg, inst9) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_INST9_MASK) | \ - (inst9 << SQ_THREAD_TRACE_WORD_ISSUE_INST9_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_SIMD_ID__VI(sq_thread_trace_word_issue_reg, simd_id) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_MASK) | \ - (simd_id << SQ_THREAD_TRACE_WORD_ISSUE_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_TIME_DELTA__VI(sq_thread_trace_word_issue_reg, time_delta) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_ISSUE_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_ISSUE_SET_TOKEN_TYPE__VI(sq_thread_trace_word_issue_reg, token_type) \ - sq_thread_trace_word_issue_reg = \ - (sq_thread_trace_word_issue_reg & ~SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_ISSUE_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_MISC_DEFAULT__VI 0x0000cdcd -#define SQ_THREAD_TRACE_WORD_MISC_GET_MISC_TOKEN_TYPE__VI(sq_thread_trace_word_misc) \ - ((sq_thread_trace_word_misc & SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_GET_SH_ID__VI(sq_thread_trace_word_misc) \ - ((sq_thread_trace_word_misc & SQ_THREAD_TRACE_WORD_MISC_SH_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_MISC_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_GET_TIME_DELTA__VI(sq_thread_trace_word_misc) \ - ((sq_thread_trace_word_misc & SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_GET_TOKEN_TYPE__VI(sq_thread_trace_word_misc) \ - ((sq_thread_trace_word_misc & SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_MASK__VI \ - (SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_MASK | SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_MISC_SH_ID_MASK | SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_MASK) - -#define SQ_THREAD_TRACE_WORD_MISC_SET_MISC_TOKEN_TYPE__VI(sq_thread_trace_word_misc_reg, \ - misc_token_type) \ - sq_thread_trace_word_misc_reg = \ - (sq_thread_trace_word_misc_reg & ~SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_MASK) | \ - (misc_token_type << SQ_THREAD_TRACE_WORD_MISC_MISC_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_SET_SH_ID__VI(sq_thread_trace_word_misc_reg, sh_id) \ - sq_thread_trace_word_misc_reg = \ - (sq_thread_trace_word_misc_reg & ~SQ_THREAD_TRACE_WORD_MISC_SH_ID_MASK) | \ - (sh_id << SQ_THREAD_TRACE_WORD_MISC_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_SET_TIME_DELTA__VI(sq_thread_trace_word_misc_reg, time_delta) \ - sq_thread_trace_word_misc_reg = \ - (sq_thread_trace_word_misc_reg & ~SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_MISC_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_MISC_SET_TOKEN_TYPE__VI(sq_thread_trace_word_misc_reg, token_type) \ - sq_thread_trace_word_misc_reg = \ - (sq_thread_trace_word_misc_reg & ~SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_MISC_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_GET_CNTR0__VI(sq_thread_trace_word_perf_1_of_2) \ - ((sq_thread_trace_word_perf_1_of_2 & SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_GET_CNTR1_LO__VI(sq_thread_trace_word_perf_1_of_2) \ - ((sq_thread_trace_word_perf_1_of_2 & SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_GET_CNTR_BANK__VI(sq_thread_trace_word_perf_1_of_2) \ - ((sq_thread_trace_word_perf_1_of_2 & SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_GET_CU_ID__VI(sq_thread_trace_word_perf_1_of_2) \ - ((sq_thread_trace_word_perf_1_of_2 & SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_GET_SH_ID__VI(sq_thread_trace_word_perf_1_of_2) \ - ((sq_thread_trace_word_perf_1_of_2 & SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_GET_TIME_DELTA__VI(sq_thread_trace_word_perf_1_of_2) \ - ((sq_thread_trace_word_perf_1_of_2 & SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_GET_TOKEN_TYPE__VI(sq_thread_trace_word_perf_1_of_2) \ - ((sq_thread_trace_word_perf_1_of_2 & SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_MASK | \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_MASK | SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_MASK | \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_MASK | SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_MASK | \ - SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_MASK) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SET_CNTR0__VI(sq_thread_trace_word_perf_1_of_2_reg, \ - cntr0) \ - sq_thread_trace_word_perf_1_of_2_reg = \ - (sq_thread_trace_word_perf_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_MASK) | \ - (cntr0 << SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR0_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SET_CNTR1_LO__VI(sq_thread_trace_word_perf_1_of_2_reg, \ - cntr1_lo) \ - sq_thread_trace_word_perf_1_of_2_reg = \ - (sq_thread_trace_word_perf_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_MASK) | \ - (cntr1_lo << SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR1_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SET_CNTR_BANK__VI(sq_thread_trace_word_perf_1_of_2_reg, \ - cntr_bank) \ - sq_thread_trace_word_perf_1_of_2_reg = \ - (sq_thread_trace_word_perf_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_MASK) | \ - (cntr_bank << SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CNTR_BANK_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SET_CU_ID__VI(sq_thread_trace_word_perf_1_of_2_reg, \ - cu_id) \ - sq_thread_trace_word_perf_1_of_2_reg = \ - (sq_thread_trace_word_perf_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_MASK) | \ - (cu_id << SQ_THREAD_TRACE_WORD_PERF_1_OF_2_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SET_SH_ID__VI(sq_thread_trace_word_perf_1_of_2_reg, \ - sh_id) \ - sq_thread_trace_word_perf_1_of_2_reg = \ - (sq_thread_trace_word_perf_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_MASK) | \ - (sh_id << SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SET_TIME_DELTA__VI(sq_thread_trace_word_perf_1_of_2_reg, \ - time_delta) \ - sq_thread_trace_word_perf_1_of_2_reg = \ - (sq_thread_trace_word_perf_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2_SET_TOKEN_TYPE__VI(sq_thread_trace_word_perf_1_of_2_reg, \ - token_type) \ - sq_thread_trace_word_perf_1_of_2_reg = \ - (sq_thread_trace_word_perf_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_PERF_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_GET_CNTR1_HI__VI(sq_thread_trace_word_perf_2_of_2) \ - ((sq_thread_trace_word_perf_2_of_2 & SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_GET_CNTR2__VI(sq_thread_trace_word_perf_2_of_2) \ - ((sq_thread_trace_word_perf_2_of_2 & SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_GET_CNTR3__VI(sq_thread_trace_word_perf_2_of_2) \ - ((sq_thread_trace_word_perf_2_of_2 & SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_MASK) >> \ - SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_MASK | SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_MASK | \ - SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_MASK) - -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_SET_CNTR1_HI__VI(sq_thread_trace_word_perf_2_of_2_reg, \ - cntr1_hi) \ - sq_thread_trace_word_perf_2_of_2_reg = \ - (sq_thread_trace_word_perf_2_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_MASK) | \ - (cntr1_hi << SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR1_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_SET_CNTR2__VI(sq_thread_trace_word_perf_2_of_2_reg, \ - cntr2) \ - sq_thread_trace_word_perf_2_of_2_reg = \ - (sq_thread_trace_word_perf_2_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_MASK) | \ - (cntr2 << SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR2_SHIFT) - -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2_SET_CNTR3__VI(sq_thread_trace_word_perf_2_of_2_reg, \ - cntr3) \ - sq_thread_trace_word_perf_2_of_2_reg = \ - (sq_thread_trace_word_perf_2_of_2_reg & ~SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_MASK) | \ - (cntr3 << SQ_THREAD_TRACE_WORD_PERF_2_OF_2_CNTR3_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_ME_ID__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_PIPE_ID__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_REG_ADDR__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_REG_DROPPED_PREV__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_REG_OP__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_REG_PRIV__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_REG_TYPE__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_TIME_DELTA__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_GET_TOKEN_TYPE__VI(sq_thread_trace_word_reg_1_of_2) \ - ((sq_thread_trace_word_reg_1_of_2 & SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_MASK | \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_MASK | SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_MASK | \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_MASK | \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_MASK | SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_MASK | \ - SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_MASK | SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_MASK) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_ME_ID__VI(sq_thread_trace_word_reg_1_of_2_reg, me_id) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_MASK) | \ - (me_id << SQ_THREAD_TRACE_WORD_REG_1_OF_2_ME_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_PIPE_ID__VI(sq_thread_trace_word_reg_1_of_2_reg, \ - pipe_id) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_MASK) | \ - (pipe_id << SQ_THREAD_TRACE_WORD_REG_1_OF_2_PIPE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_REG_ADDR__VI(sq_thread_trace_word_reg_1_of_2_reg, \ - reg_addr) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_MASK) | \ - (reg_addr << SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_ADDR_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_REG_DROPPED_PREV__VI( \ - sq_thread_trace_word_reg_1_of_2_reg, reg_dropped_prev) \ - sq_thread_trace_word_reg_1_of_2_reg = (sq_thread_trace_word_reg_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_MASK) | \ - (reg_dropped_prev << SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_DROPPED_PREV_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_REG_OP__VI(sq_thread_trace_word_reg_1_of_2_reg, \ - reg_op) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_MASK) | \ - (reg_op << SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_OP_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_REG_PRIV__VI(sq_thread_trace_word_reg_1_of_2_reg, \ - reg_priv) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_MASK) | \ - (reg_priv << SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_PRIV_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_REG_TYPE__VI(sq_thread_trace_word_reg_1_of_2_reg, \ - reg_type) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_MASK) | \ - (reg_type << SQ_THREAD_TRACE_WORD_REG_1_OF_2_REG_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_TIME_DELTA__VI(sq_thread_trace_word_reg_1_of_2_reg, \ - time_delta) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_REG_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2_SET_TOKEN_TYPE__VI(sq_thread_trace_word_reg_1_of_2_reg, \ - token_type) \ - sq_thread_trace_word_reg_1_of_2_reg = \ - (sq_thread_trace_word_reg_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_REG_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_GET_DATA__VI(sq_thread_trace_word_reg_2_of_2) \ - ((sq_thread_trace_word_reg_2_of_2 & SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_MASK__VI (SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_MASK) - -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2_SET_DATA__VI(sq_thread_trace_word_reg_2_of_2_reg, data) \ - sq_thread_trace_word_reg_2_of_2_reg = \ - (sq_thread_trace_word_reg_2_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_MASK) | \ - (data << SQ_THREAD_TRACE_WORD_REG_2_OF_2_DATA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_GET_DATA_LO__VI(sq_thread_trace_word_reg_cs_1_of_2) \ - ((sq_thread_trace_word_reg_cs_1_of_2 & SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_GET_ME_ID__VI(sq_thread_trace_word_reg_cs_1_of_2) \ - ((sq_thread_trace_word_reg_cs_1_of_2 & SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_GET_PIPE_ID__VI(sq_thread_trace_word_reg_cs_1_of_2) \ - ((sq_thread_trace_word_reg_cs_1_of_2 & SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_GET_REG_ADDR__VI(sq_thread_trace_word_reg_cs_1_of_2) \ - ((sq_thread_trace_word_reg_cs_1_of_2 & SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_GET_TIME_DELTA__VI(sq_thread_trace_word_reg_cs_1_of_2) \ - ((sq_thread_trace_word_reg_cs_1_of_2 & SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_GET_TOKEN_TYPE__VI(sq_thread_trace_word_reg_cs_1_of_2) \ - ((sq_thread_trace_word_reg_cs_1_of_2 & SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_MASK | \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_MASK | \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_MASK | \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_MASK | \ - SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_MASK) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_SET_DATA_LO__VI(sq_thread_trace_word_reg_cs_1_of_2_reg, \ - data_lo) \ - sq_thread_trace_word_reg_cs_1_of_2_reg = (sq_thread_trace_word_reg_cs_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_MASK) | \ - (data_lo << SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DATA_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_SET_ME_ID__VI(sq_thread_trace_word_reg_cs_1_of_2_reg, \ - me_id) \ - sq_thread_trace_word_reg_cs_1_of_2_reg = \ - (sq_thread_trace_word_reg_cs_1_of_2_reg & ~SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_MASK) | \ - (me_id << SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_ME_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_SET_PIPE_ID__VI(sq_thread_trace_word_reg_cs_1_of_2_reg, \ - pipe_id) \ - sq_thread_trace_word_reg_cs_1_of_2_reg = (sq_thread_trace_word_reg_cs_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_MASK) | \ - (pipe_id << SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_PIPE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_SET_REG_ADDR__VI( \ - sq_thread_trace_word_reg_cs_1_of_2_reg, reg_addr) \ - sq_thread_trace_word_reg_cs_1_of_2_reg = (sq_thread_trace_word_reg_cs_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_MASK) | \ - (reg_addr << SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_REG_ADDR_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_SET_TIME_DELTA__VI( \ - sq_thread_trace_word_reg_cs_1_of_2_reg, time_delta) \ - sq_thread_trace_word_reg_cs_1_of_2_reg = (sq_thread_trace_word_reg_cs_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_SET_TOKEN_TYPE__VI( \ - sq_thread_trace_word_reg_cs_1_of_2_reg, token_type) \ - sq_thread_trace_word_reg_cs_1_of_2_reg = (sq_thread_trace_word_reg_cs_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT__VI 0x0000cdcd -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_GET_DATA_HI__VI(sq_thread_trace_word_reg_cs_2_of_2) \ - ((sq_thread_trace_word_reg_cs_2_of_2 & SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_MASK) >> \ - SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_MASK) - -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_SET_DATA_HI__VI(sq_thread_trace_word_reg_cs_2_of_2_reg, \ - data_hi) \ - sq_thread_trace_word_reg_cs_2_of_2_reg = (sq_thread_trace_word_reg_cs_2_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_MASK) | \ - (data_hi << SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DATA_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT__VI 0xcdcd000d -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_GET_TIME_LO__VI( \ - sq_thread_trace_word_timestamp_1_of_2) \ - ((sq_thread_trace_word_timestamp_1_of_2 & SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_MASK) >> \ - SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_GET_TOKEN_TYPE__VI( \ - sq_thread_trace_word_timestamp_1_of_2) \ - ((sq_thread_trace_word_timestamp_1_of_2 & \ - SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_MASK | \ - SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_MASK) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_SET_TIME_LO__VI( \ - sq_thread_trace_word_timestamp_1_of_2_reg, time_lo) \ - sq_thread_trace_word_timestamp_1_of_2_reg = \ - (sq_thread_trace_word_timestamp_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_MASK) | \ - (time_lo << SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TIME_LO_SHIFT) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_SET_TOKEN_TYPE__VI( \ - sq_thread_trace_word_timestamp_1_of_2_reg, token_type) \ - sq_thread_trace_word_timestamp_1_of_2_reg = \ - (sq_thread_trace_word_timestamp_1_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_GET_TIME_HI__VI( \ - sq_thread_trace_word_timestamp_2_of_2) \ - ((sq_thread_trace_word_timestamp_2_of_2 & SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_MASK) >> \ - SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_MASK__VI \ - (SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_MASK) - -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_SET_TIME_HI__VI( \ - sq_thread_trace_word_timestamp_2_of_2_reg, time_hi) \ - sq_thread_trace_word_timestamp_2_of_2_reg = \ - (sq_thread_trace_word_timestamp_2_of_2_reg & \ - ~SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_MASK) | \ - (time_hi << SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_TIME_HI_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE_DEFAULT__VI 0x0000cdcd -#define SQ_THREAD_TRACE_WORD_WAVE_GET_CU_ID__VI(sq_thread_trace_word_wave) \ - ((sq_thread_trace_word_wave & SQ_THREAD_TRACE_WORD_WAVE_CU_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_GET_SH_ID__VI(sq_thread_trace_word_wave) \ - ((sq_thread_trace_word_wave & SQ_THREAD_TRACE_WORD_WAVE_SH_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_GET_SIMD_ID__VI(sq_thread_trace_word_wave) \ - ((sq_thread_trace_word_wave & SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_GET_TIME_DELTA__VI(sq_thread_trace_word_wave) \ - ((sq_thread_trace_word_wave & SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_GET_TOKEN_TYPE__VI(sq_thread_trace_word_wave) \ - ((sq_thread_trace_word_wave & SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_GET_WAVE_ID__VI(sq_thread_trace_word_wave) \ - ((sq_thread_trace_word_wave & SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_MASK__VI \ - (SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_MASK | SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_SH_ID_MASK | SQ_THREAD_TRACE_WORD_WAVE_CU_ID_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_MASK | SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_MASK) - -#define SQ_THREAD_TRACE_WORD_WAVE_SET_CU_ID__VI(sq_thread_trace_word_wave_reg, cu_id) \ - sq_thread_trace_word_wave_reg = \ - (sq_thread_trace_word_wave_reg & ~SQ_THREAD_TRACE_WORD_WAVE_CU_ID_MASK) | \ - (cu_id << SQ_THREAD_TRACE_WORD_WAVE_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_SET_SH_ID__VI(sq_thread_trace_word_wave_reg, sh_id) \ - sq_thread_trace_word_wave_reg = \ - (sq_thread_trace_word_wave_reg & ~SQ_THREAD_TRACE_WORD_WAVE_SH_ID_MASK) | \ - (sh_id << SQ_THREAD_TRACE_WORD_WAVE_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_SET_SIMD_ID__VI(sq_thread_trace_word_wave_reg, simd_id) \ - sq_thread_trace_word_wave_reg = \ - (sq_thread_trace_word_wave_reg & ~SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_MASK) | \ - (simd_id << SQ_THREAD_TRACE_WORD_WAVE_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_SET_TIME_DELTA__VI(sq_thread_trace_word_wave_reg, time_delta) \ - sq_thread_trace_word_wave_reg = \ - (sq_thread_trace_word_wave_reg & ~SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_WAVE_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_SET_TOKEN_TYPE__VI(sq_thread_trace_word_wave_reg, token_type) \ - sq_thread_trace_word_wave_reg = \ - (sq_thread_trace_word_wave_reg & ~SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_WAVE_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_SET_WAVE_ID__VI(sq_thread_trace_word_wave_reg, wave_id) \ - sq_thread_trace_word_wave_reg = \ - (sq_thread_trace_word_wave_reg & ~SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_MASK) | \ - (wave_id << SQ_THREAD_TRACE_WORD_WAVE_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT__VI 0xcdcdcdcd -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_COUNT__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_CU_ID__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_DISPATCHER__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_SH_ID__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_SIMD_ID__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_TG_ID__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_TIME_DELTA__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_TOKEN_TYPE__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_VS_NO_ALLOC_OR_GROUPED__VI( \ - sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & \ - SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_GET_WAVE_ID__VI(sq_thread_trace_word_wave_start) \ - ((sq_thread_trace_word_wave_start & SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_MASK) >> \ - SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_MASK__VI \ - (SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_MASK | SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_MASK | SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_MASK | \ - SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_MASK | SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_MASK) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_COUNT__VI(sq_thread_trace_word_wave_start_reg, count) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_MASK) | \ - (count << SQ_THREAD_TRACE_WORD_WAVE_START_COUNT_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_CU_ID__VI(sq_thread_trace_word_wave_start_reg, cu_id) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_MASK) | \ - (cu_id << SQ_THREAD_TRACE_WORD_WAVE_START_CU_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_DISPATCHER__VI(sq_thread_trace_word_wave_start_reg, \ - dispatcher) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_MASK) | \ - (dispatcher << SQ_THREAD_TRACE_WORD_WAVE_START_DISPATCHER_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_SH_ID__VI(sq_thread_trace_word_wave_start_reg, sh_id) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_MASK) | \ - (sh_id << SQ_THREAD_TRACE_WORD_WAVE_START_SH_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_SIMD_ID__VI(sq_thread_trace_word_wave_start_reg, \ - simd_id) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_MASK) | \ - (simd_id << SQ_THREAD_TRACE_WORD_WAVE_START_SIMD_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_TG_ID__VI(sq_thread_trace_word_wave_start_reg, tg_id) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_MASK) | \ - (tg_id << SQ_THREAD_TRACE_WORD_WAVE_START_TG_ID_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_TIME_DELTA__VI(sq_thread_trace_word_wave_start_reg, \ - time_delta) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_MASK) | \ - (time_delta << SQ_THREAD_TRACE_WORD_WAVE_START_TIME_DELTA_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_TOKEN_TYPE__VI(sq_thread_trace_word_wave_start_reg, \ - token_type) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_MASK) | \ - (token_type << SQ_THREAD_TRACE_WORD_WAVE_START_TOKEN_TYPE_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_VS_NO_ALLOC_OR_GROUPED__VI( \ - sq_thread_trace_word_wave_start_reg, vs_no_alloc_or_grouped) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & \ - ~SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_MASK) | \ - (vs_no_alloc_or_grouped << SQ_THREAD_TRACE_WORD_WAVE_START_VS_NO_ALLOC_OR_GROUPED_SHIFT) - -#define SQ_THREAD_TRACE_WORD_WAVE_START_SET_WAVE_ID__VI(sq_thread_trace_word_wave_start_reg, \ - wave_id) \ - sq_thread_trace_word_wave_start_reg = \ - (sq_thread_trace_word_wave_start_reg & ~SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_MASK) | \ - (wave_id << SQ_THREAD_TRACE_WORD_WAVE_START_WAVE_ID_SHIFT) - -#define SQ_THREAD_TRACE_WPTR_DEFAULT__SI__CI 0x00000000 -#define SQ_THREAD_TRACE_WPTR_DEFAULT__VI 0x0dcdcdcd -#define SQ_THREAD_TRACE_WPTR_GET_READ_OFFSET__VI(sq_thread_trace_wptr) \ - ((sq_thread_trace_wptr & SQ_THREAD_TRACE_WPTR_READ_OFFSET_MASK) >> \ - SQ_THREAD_TRACE_WPTR_READ_OFFSET_SHIFT) - -#define SQ_THREAD_TRACE_WPTR_GET_WPTR__VI(sq_thread_trace_wptr) \ - ((sq_thread_trace_wptr & SQ_THREAD_TRACE_WPTR_WPTR_MASK) >> SQ_THREAD_TRACE_WPTR_WPTR_SHIFT) - -#define SQ_THREAD_TRACE_WPTR_MASK__VI \ - (SQ_THREAD_TRACE_WPTR_WPTR_MASK | SQ_THREAD_TRACE_WPTR_READ_OFFSET_MASK) - -#define SQ_THREAD_TRACE_WPTR_SET_READ_OFFSET__VI(sq_thread_trace_wptr_reg, read_offset) \ - sq_thread_trace_wptr_reg = (sq_thread_trace_wptr_reg & ~SQ_THREAD_TRACE_WPTR_READ_OFFSET_MASK) | \ - (read_offset << SQ_THREAD_TRACE_WPTR_READ_OFFSET_SHIFT) - -#define SQ_THREAD_TRACE_WPTR_SET_WPTR__VI(sq_thread_trace_wptr_reg, wptr) \ - sq_thread_trace_wptr_reg = (sq_thread_trace_wptr_reg & ~SQ_THREAD_TRACE_WPTR_WPTR_MASK) | \ - (wptr << SQ_THREAD_TRACE_WPTR_WPTR_SHIFT) - -#define SQ_TIME_HI_GET_TIME__VI(sq_time_hi) \ - ((sq_time_hi & SQ_TIME_HI_TIME_MASK) >> SQ_TIME_HI_TIME_SHIFT) - -#define SQ_TIME_HI_MASK__VI (SQ_TIME_HI_TIME_MASK) - -#define SQ_TIME_HI_SET_TIME__VI(sq_time_hi_reg, time) \ - sq_time_hi_reg = (sq_time_hi_reg & ~SQ_TIME_HI_TIME_MASK) | (time << SQ_TIME_HI_TIME_SHIFT) - -#define SQ_TIME_LO_GET_TIME__VI(sq_time_lo) \ - ((sq_time_lo & SQ_TIME_LO_TIME_MASK) >> SQ_TIME_LO_TIME_SHIFT) - -#define SQ_TIME_LO_MASK__VI (SQ_TIME_LO_TIME_MASK) - -#define SQ_TIME_LO_SET_TIME__VI(sq_time_lo_reg, time) \ - sq_time_lo_reg = (sq_time_lo_reg & ~SQ_TIME_LO_TIME_MASK) | (time << SQ_TIME_LO_TIME_SHIFT) - -#define SQ_WAVE_EXEC_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_EXEC_HI_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_EXEC_HI_GET_EXEC_HI__VI(sq_wave_exec_hi) \ - ((sq_wave_exec_hi & SQ_WAVE_EXEC_HI_EXEC_HI_MASK) >> SQ_WAVE_EXEC_HI_EXEC_HI_SHIFT) - -#define SQ_WAVE_EXEC_HI_MASK__VI (SQ_WAVE_EXEC_HI_EXEC_HI_MASK) - -#define SQ_WAVE_EXEC_HI_SET_EXEC_HI__VI(sq_wave_exec_hi_reg, exec_hi) \ - sq_wave_exec_hi_reg = (sq_wave_exec_hi_reg & ~SQ_WAVE_EXEC_HI_EXEC_HI_MASK) | \ - (exec_hi << SQ_WAVE_EXEC_HI_EXEC_HI_SHIFT) - -#define SQ_WAVE_EXEC_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_EXEC_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_EXEC_LO_GET_EXEC_LO__VI(sq_wave_exec_lo) \ - ((sq_wave_exec_lo & SQ_WAVE_EXEC_LO_EXEC_LO_MASK) >> SQ_WAVE_EXEC_LO_EXEC_LO_SHIFT) - -#define SQ_WAVE_EXEC_LO_MASK__VI (SQ_WAVE_EXEC_LO_EXEC_LO_MASK) - -#define SQ_WAVE_EXEC_LO_SET_EXEC_LO__VI(sq_wave_exec_lo_reg, exec_lo) \ - sq_wave_exec_lo_reg = (sq_wave_exec_lo_reg & ~SQ_WAVE_EXEC_LO_EXEC_LO_MASK) | \ - (exec_lo << SQ_WAVE_EXEC_LO_EXEC_LO_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_GPR_ALLOC_DEFAULT__VI 0x0d0d0d0d -#define SQ_WAVE_GPR_ALLOC_GET_SGPR_BASE__VI(sq_wave_gpr_alloc) \ - ((sq_wave_gpr_alloc & SQ_WAVE_GPR_ALLOC_SGPR_BASE_MASK) >> SQ_WAVE_GPR_ALLOC_SGPR_BASE_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_GET_SGPR_SIZE__VI(sq_wave_gpr_alloc) \ - ((sq_wave_gpr_alloc & SQ_WAVE_GPR_ALLOC_SGPR_SIZE_MASK) >> SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_GET_VGPR_BASE__VI(sq_wave_gpr_alloc) \ - ((sq_wave_gpr_alloc & SQ_WAVE_GPR_ALLOC_VGPR_BASE_MASK) >> SQ_WAVE_GPR_ALLOC_VGPR_BASE_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_GET_VGPR_SIZE__VI(sq_wave_gpr_alloc) \ - ((sq_wave_gpr_alloc & SQ_WAVE_GPR_ALLOC_VGPR_SIZE_MASK) >> SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_MASK__VI \ - (SQ_WAVE_GPR_ALLOC_VGPR_BASE_MASK | SQ_WAVE_GPR_ALLOC_VGPR_SIZE_MASK | \ - SQ_WAVE_GPR_ALLOC_SGPR_BASE_MASK | SQ_WAVE_GPR_ALLOC_SGPR_SIZE_MASK) - -#define SQ_WAVE_GPR_ALLOC_SET_SGPR_BASE__VI(sq_wave_gpr_alloc_reg, sgpr_base) \ - sq_wave_gpr_alloc_reg = (sq_wave_gpr_alloc_reg & ~SQ_WAVE_GPR_ALLOC_SGPR_BASE_MASK) | \ - (sgpr_base << SQ_WAVE_GPR_ALLOC_SGPR_BASE_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_SET_SGPR_SIZE__VI(sq_wave_gpr_alloc_reg, sgpr_size) \ - sq_wave_gpr_alloc_reg = (sq_wave_gpr_alloc_reg & ~SQ_WAVE_GPR_ALLOC_SGPR_SIZE_MASK) | \ - (sgpr_size << SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_SET_VGPR_BASE__VI(sq_wave_gpr_alloc_reg, vgpr_base) \ - sq_wave_gpr_alloc_reg = (sq_wave_gpr_alloc_reg & ~SQ_WAVE_GPR_ALLOC_VGPR_BASE_MASK) | \ - (vgpr_base << SQ_WAVE_GPR_ALLOC_VGPR_BASE_SHIFT) - -#define SQ_WAVE_GPR_ALLOC_SET_VGPR_SIZE__VI(sq_wave_gpr_alloc_reg, vgpr_size) \ - sq_wave_gpr_alloc_reg = (sq_wave_gpr_alloc_reg & ~SQ_WAVE_GPR_ALLOC_VGPR_SIZE_MASK) | \ - (vgpr_size << SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT) - -#define SQ_WAVE_HW_ID_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_HW_ID_DEFAULT__VI 0xcdcd4dcd -#define SQ_WAVE_HW_ID_GET_CU_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_CU_ID_MASK) >> SQ_WAVE_HW_ID_CU_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_ME_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_ME_ID_MASK) >> SQ_WAVE_HW_ID_ME_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_PIPE_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_PIPE_ID_MASK) >> SQ_WAVE_HW_ID_PIPE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_QUEUE_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_QUEUE_ID_MASK) >> SQ_WAVE_HW_ID_QUEUE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_SE_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_SE_ID_MASK) >> SQ_WAVE_HW_ID_SE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_SH_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_SH_ID_MASK) >> SQ_WAVE_HW_ID_SH_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_SIMD_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_SIMD_ID_MASK) >> SQ_WAVE_HW_ID_SIMD_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_STATE_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_STATE_ID_MASK) >> SQ_WAVE_HW_ID_STATE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_TG_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_TG_ID_MASK) >> SQ_WAVE_HW_ID_TG_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_VM_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_VM_ID_MASK) >> SQ_WAVE_HW_ID_VM_ID_SHIFT) - -#define SQ_WAVE_HW_ID_GET_WAVE_ID__VI(sq_wave_hw_id) \ - ((sq_wave_hw_id & SQ_WAVE_HW_ID_WAVE_ID_MASK) >> SQ_WAVE_HW_ID_WAVE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_MASK__VI \ - (SQ_WAVE_HW_ID_WAVE_ID_MASK | SQ_WAVE_HW_ID_SIMD_ID_MASK | SQ_WAVE_HW_ID_PIPE_ID_MASK | \ - SQ_WAVE_HW_ID_CU_ID_MASK | SQ_WAVE_HW_ID_SH_ID_MASK | SQ_WAVE_HW_ID_SE_ID_MASK | \ - SQ_WAVE_HW_ID_TG_ID_MASK | SQ_WAVE_HW_ID_VM_ID_MASK | SQ_WAVE_HW_ID_QUEUE_ID_MASK | \ - SQ_WAVE_HW_ID_STATE_ID_MASK | SQ_WAVE_HW_ID_ME_ID_MASK) - -#define SQ_WAVE_HW_ID_SET_CU_ID__VI(sq_wave_hw_id_reg, cu_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_CU_ID_MASK) | (cu_id << SQ_WAVE_HW_ID_CU_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_ME_ID__VI(sq_wave_hw_id_reg, me_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_ME_ID_MASK) | (me_id << SQ_WAVE_HW_ID_ME_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_PIPE_ID__VI(sq_wave_hw_id_reg, pipe_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_PIPE_ID_MASK) | (pipe_id << SQ_WAVE_HW_ID_PIPE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_QUEUE_ID__VI(sq_wave_hw_id_reg, queue_id) \ - sq_wave_hw_id_reg = (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_QUEUE_ID_MASK) | \ - (queue_id << SQ_WAVE_HW_ID_QUEUE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_SE_ID__VI(sq_wave_hw_id_reg, se_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_SE_ID_MASK) | (se_id << SQ_WAVE_HW_ID_SE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_SH_ID__VI(sq_wave_hw_id_reg, sh_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_SH_ID_MASK) | (sh_id << SQ_WAVE_HW_ID_SH_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_SIMD_ID__VI(sq_wave_hw_id_reg, simd_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_SIMD_ID_MASK) | (simd_id << SQ_WAVE_HW_ID_SIMD_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_STATE_ID__VI(sq_wave_hw_id_reg, state_id) \ - sq_wave_hw_id_reg = (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_STATE_ID_MASK) | \ - (state_id << SQ_WAVE_HW_ID_STATE_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_TG_ID__VI(sq_wave_hw_id_reg, tg_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_TG_ID_MASK) | (tg_id << SQ_WAVE_HW_ID_TG_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_VM_ID__VI(sq_wave_hw_id_reg, vm_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_VM_ID_MASK) | (vm_id << SQ_WAVE_HW_ID_VM_ID_SHIFT) - -#define SQ_WAVE_HW_ID_SET_WAVE_ID__VI(sq_wave_hw_id_reg, wave_id) \ - sq_wave_hw_id_reg = \ - (sq_wave_hw_id_reg & ~SQ_WAVE_HW_ID_WAVE_ID_MASK) | (wave_id << SQ_WAVE_HW_ID_WAVE_ID_SHIFT) - -#define SQ_WAVE_IB_DBG0_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_IB_DBG0_DEFAULT__VI 0x4dcd0dcd -#define SQ_WAVE_IB_DBG0_ECC_ST_MASK__SI__CI 0x00c00000 -#define SQ_WAVE_IB_DBG0_ECC_ST_MASK__VI 0x03000000 -#define SQ_WAVE_IB_DBG0_ECC_ST_SHIFT__SI__CI 22 -#define SQ_WAVE_IB_DBG0_ECC_ST_SHIFT__VI 24 -#define SQ_WAVE_IB_DBG0_GET_ECC_ST__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_ECC_ST_MASK) >> SQ_WAVE_IB_DBG0_ECC_ST_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_HYB_CNT__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_HYB_CNT_MASK) >> SQ_WAVE_IB_DBG0_HYB_CNT_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_IBUF_RPTR__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_IBUF_RPTR_MASK) >> SQ_WAVE_IB_DBG0_IBUF_RPTR_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_IBUF_ST__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_IBUF_ST_MASK) >> SQ_WAVE_IB_DBG0_IBUF_ST_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_IBUF_WPTR__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_IBUF_WPTR_MASK) >> SQ_WAVE_IB_DBG0_IBUF_WPTR_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_INST_STR_ST__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_INST_STR_ST_MASK) >> SQ_WAVE_IB_DBG0_INST_STR_ST_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_IS_HYB__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_IS_HYB_MASK) >> SQ_WAVE_IB_DBG0_IS_HYB_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_KILL__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_KILL_MASK) >> SQ_WAVE_IB_DBG0_KILL_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_MISC_CNT__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_MISC_CNT_MASK) >> SQ_WAVE_IB_DBG0_MISC_CNT_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_NEED_KILL_IFETCH__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_MASK) >> \ - SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_NEED_NEXT_DW__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_NEED_NEXT_DW_MASK) >> SQ_WAVE_IB_DBG0_NEED_NEXT_DW_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_NO_PREFETCH_CNT__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_MASK) >> \ - SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_SHIFT) - -#define SQ_WAVE_IB_DBG0_GET_PC_INVALID__VI(sq_wave_ib_dbg0) \ - ((sq_wave_ib_dbg0 & SQ_WAVE_IB_DBG0_PC_INVALID_MASK) >> SQ_WAVE_IB_DBG0_PC_INVALID_SHIFT) - -#define SQ_WAVE_IB_DBG0_HYB_CNT_MASK__SI__CI 0x06000000 -#define SQ_WAVE_IB_DBG0_HYB_CNT_MASK__VI 0x18000000 -#define SQ_WAVE_IB_DBG0_HYB_CNT_SHIFT__SI__CI 25 -#define SQ_WAVE_IB_DBG0_HYB_CNT_SHIFT__VI 27 -#define SQ_WAVE_IB_DBG0_INST_STR_ST_MASK__SI__CI 0x00070000 -#define SQ_WAVE_IB_DBG0_INST_STR_ST_MASK__VI 0x000f0000 -#define SQ_WAVE_IB_DBG0_INST_STR_ST_SIZE__SI__CI 3 -#define SQ_WAVE_IB_DBG0_INST_STR_ST_SIZE__VI 4 -#define SQ_WAVE_IB_DBG0_IS_HYB_MASK__SI__CI 0x01000000 -#define SQ_WAVE_IB_DBG0_IS_HYB_MASK__VI 0x04000000 -#define SQ_WAVE_IB_DBG0_IS_HYB_SHIFT__SI__CI 24 -#define SQ_WAVE_IB_DBG0_IS_HYB_SHIFT__VI 26 -#define SQ_WAVE_IB_DBG0_KILL_MASK__VI 0x20000000 -#define SQ_WAVE_IB_DBG0_KILL_SHIFT__VI 29 -#define SQ_WAVE_IB_DBG0_MASK__VI \ - (SQ_WAVE_IB_DBG0_IBUF_ST_MASK | SQ_WAVE_IB_DBG0_PC_INVALID_MASK | \ - SQ_WAVE_IB_DBG0_NEED_NEXT_DW_MASK | SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_MASK | \ - SQ_WAVE_IB_DBG0_IBUF_RPTR_MASK | SQ_WAVE_IB_DBG0_IBUF_WPTR_MASK | \ - SQ_WAVE_IB_DBG0_INST_STR_ST_MASK | SQ_WAVE_IB_DBG0_MISC_CNT_MASK | \ - SQ_WAVE_IB_DBG0_ECC_ST_MASK | SQ_WAVE_IB_DBG0_IS_HYB_MASK | SQ_WAVE_IB_DBG0_HYB_CNT_MASK | \ - SQ_WAVE_IB_DBG0_KILL_MASK | SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_MASK) - -#define SQ_WAVE_IB_DBG0_MISC_CNT_MASK__SI__CI 0x00380000 -#define SQ_WAVE_IB_DBG0_MISC_CNT_MASK__VI 0x00f00000 -#define SQ_WAVE_IB_DBG0_MISC_CNT_SHIFT__SI__CI 19 -#define SQ_WAVE_IB_DBG0_MISC_CNT_SHIFT__VI 20 -#define SQ_WAVE_IB_DBG0_MISC_CNT_SIZE__SI__CI 3 -#define SQ_WAVE_IB_DBG0_MISC_CNT_SIZE__VI 4 -#define SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_MASK__VI 0x40000000 -#define SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_SHIFT__VI 30 -#define SQ_WAVE_IB_DBG0_SET_ECC_ST__VI(sq_wave_ib_dbg0_reg, ecc_st) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_ECC_ST_MASK) | \ - (ecc_st << SQ_WAVE_IB_DBG0_ECC_ST_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_HYB_CNT__VI(sq_wave_ib_dbg0_reg, hyb_cnt) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_HYB_CNT_MASK) | \ - (hyb_cnt << SQ_WAVE_IB_DBG0_HYB_CNT_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_IBUF_RPTR__VI(sq_wave_ib_dbg0_reg, ibuf_rptr) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_IBUF_RPTR_MASK) | \ - (ibuf_rptr << SQ_WAVE_IB_DBG0_IBUF_RPTR_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_IBUF_ST__VI(sq_wave_ib_dbg0_reg, ibuf_st) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_IBUF_ST_MASK) | \ - (ibuf_st << SQ_WAVE_IB_DBG0_IBUF_ST_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_IBUF_WPTR__VI(sq_wave_ib_dbg0_reg, ibuf_wptr) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_IBUF_WPTR_MASK) | \ - (ibuf_wptr << SQ_WAVE_IB_DBG0_IBUF_WPTR_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_INST_STR_ST__VI(sq_wave_ib_dbg0_reg, inst_str_st) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_INST_STR_ST_MASK) | \ - (inst_str_st << SQ_WAVE_IB_DBG0_INST_STR_ST_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_IS_HYB__VI(sq_wave_ib_dbg0_reg, is_hyb) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_IS_HYB_MASK) | \ - (is_hyb << SQ_WAVE_IB_DBG0_IS_HYB_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_KILL__VI(sq_wave_ib_dbg0_reg, kill) \ - sq_wave_ib_dbg0_reg = \ - (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_KILL_MASK) | (kill << SQ_WAVE_IB_DBG0_KILL_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_MISC_CNT__VI(sq_wave_ib_dbg0_reg, misc_cnt) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_MISC_CNT_MASK) | \ - (misc_cnt << SQ_WAVE_IB_DBG0_MISC_CNT_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_NEED_KILL_IFETCH__VI(sq_wave_ib_dbg0_reg, need_kill_ifetch) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_MASK) | \ - (need_kill_ifetch << SQ_WAVE_IB_DBG0_NEED_KILL_IFETCH_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_NEED_NEXT_DW__VI(sq_wave_ib_dbg0_reg, need_next_dw) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_NEED_NEXT_DW_MASK) | \ - (need_next_dw << SQ_WAVE_IB_DBG0_NEED_NEXT_DW_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_NO_PREFETCH_CNT__VI(sq_wave_ib_dbg0_reg, no_prefetch_cnt) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_MASK) | \ - (no_prefetch_cnt << SQ_WAVE_IB_DBG0_NO_PREFETCH_CNT_SHIFT) - -#define SQ_WAVE_IB_DBG0_SET_PC_INVALID__VI(sq_wave_ib_dbg0_reg, pc_invalid) \ - sq_wave_ib_dbg0_reg = (sq_wave_ib_dbg0_reg & ~SQ_WAVE_IB_DBG0_PC_INVALID_MASK) | \ - (pc_invalid << SQ_WAVE_IB_DBG0_PC_INVALID_SHIFT) - -#define SQ_WAVE_IB_DBG1_DEFAULT__VI 0x00000dc5 -#define SQ_WAVE_IB_DBG1_GET_IXNACK__VI(sq_wave_ib_dbg1) \ - ((sq_wave_ib_dbg1 & SQ_WAVE_IB_DBG1_IXNACK_MASK) >> SQ_WAVE_IB_DBG1_IXNACK_SHIFT) - -#define SQ_WAVE_IB_DBG1_GET_QCNT__VI(sq_wave_ib_dbg1) \ - ((sq_wave_ib_dbg1 & SQ_WAVE_IB_DBG1_QCNT_MASK) >> SQ_WAVE_IB_DBG1_QCNT_SHIFT) - -#define SQ_WAVE_IB_DBG1_GET_TA_NEED_RESET__VI(sq_wave_ib_dbg1) \ - ((sq_wave_ib_dbg1 & SQ_WAVE_IB_DBG1_TA_NEED_RESET_MASK) >> SQ_WAVE_IB_DBG1_TA_NEED_RESET_SHIFT) - -#define SQ_WAVE_IB_DBG1_GET_XCNT__VI(sq_wave_ib_dbg1) \ - ((sq_wave_ib_dbg1 & SQ_WAVE_IB_DBG1_XCNT_MASK) >> SQ_WAVE_IB_DBG1_XCNT_SHIFT) - -#define SQ_WAVE_IB_DBG1_GET_XNACK__VI(sq_wave_ib_dbg1) \ - ((sq_wave_ib_dbg1 & SQ_WAVE_IB_DBG1_XNACK_MASK) >> SQ_WAVE_IB_DBG1_XNACK_SHIFT) - -#define SQ_WAVE_IB_DBG1_IXNACK_MASK__VI 0x00000001 -#define SQ_WAVE_IB_DBG1_IXNACK_SHIFT__VI 0x00000000 -#define SQ_WAVE_IB_DBG1_IXNACK_SIZE__VI 1 -#define SQ_WAVE_IB_DBG1_MASK__VI \ - (SQ_WAVE_IB_DBG1_IXNACK_MASK | SQ_WAVE_IB_DBG1_XNACK_MASK | SQ_WAVE_IB_DBG1_TA_NEED_RESET_MASK | \ - SQ_WAVE_IB_DBG1_XCNT_MASK | SQ_WAVE_IB_DBG1_QCNT_MASK) - -#define SQ_WAVE_IB_DBG1_QCNT_MASK__VI 0x00000f00 -#define SQ_WAVE_IB_DBG1_QCNT_SHIFT__VI 8 -#define SQ_WAVE_IB_DBG1_QCNT_SIZE__VI 4 -#define SQ_WAVE_IB_DBG1_REG_SIZE__VI 32 -#define SQ_WAVE_IB_DBG1_SET_IXNACK__VI(sq_wave_ib_dbg1_reg, ixnack) \ - sq_wave_ib_dbg1_reg = (sq_wave_ib_dbg1_reg & ~SQ_WAVE_IB_DBG1_IXNACK_MASK) | \ - (ixnack << SQ_WAVE_IB_DBG1_IXNACK_SHIFT) - -#define SQ_WAVE_IB_DBG1_SET_QCNT__VI(sq_wave_ib_dbg1_reg, qcnt) \ - sq_wave_ib_dbg1_reg = \ - (sq_wave_ib_dbg1_reg & ~SQ_WAVE_IB_DBG1_QCNT_MASK) | (qcnt << SQ_WAVE_IB_DBG1_QCNT_SHIFT) - -#define SQ_WAVE_IB_DBG1_SET_TA_NEED_RESET__VI(sq_wave_ib_dbg1_reg, ta_need_reset) \ - sq_wave_ib_dbg1_reg = (sq_wave_ib_dbg1_reg & ~SQ_WAVE_IB_DBG1_TA_NEED_RESET_MASK) | \ - (ta_need_reset << SQ_WAVE_IB_DBG1_TA_NEED_RESET_SHIFT) - -#define SQ_WAVE_IB_DBG1_SET_XCNT__VI(sq_wave_ib_dbg1_reg, xcnt) \ - sq_wave_ib_dbg1_reg = \ - (sq_wave_ib_dbg1_reg & ~SQ_WAVE_IB_DBG1_XCNT_MASK) | (xcnt << SQ_WAVE_IB_DBG1_XCNT_SHIFT) - -#define SQ_WAVE_IB_DBG1_SET_XNACK__VI(sq_wave_ib_dbg1_reg, xnack) \ - sq_wave_ib_dbg1_reg = \ - (sq_wave_ib_dbg1_reg & ~SQ_WAVE_IB_DBG1_XNACK_MASK) | (xnack << SQ_WAVE_IB_DBG1_XNACK_SHIFT) - -#define SQ_WAVE_IB_DBG1_TA_NEED_RESET_MASK__VI 0x00000004 -#define SQ_WAVE_IB_DBG1_TA_NEED_RESET_SHIFT__VI 2 -#define SQ_WAVE_IB_DBG1_TA_NEED_RESET_SIZE__VI 1 -#define SQ_WAVE_IB_DBG1_XCNT_MASK__VI 0x000000f0 -#define SQ_WAVE_IB_DBG1_XCNT_SHIFT__VI 4 -#define SQ_WAVE_IB_DBG1_XCNT_SIZE__VI 4 -#define SQ_WAVE_IB_DBG1_XNACK_MASK__VI 0x00000002 -#define SQ_WAVE_IB_DBG1_XNACK_SHIFT__VI 1 -#define SQ_WAVE_IB_DBG1_XNACK_SIZE__VI 1 -#define SQ_WAVE_IB_STS_FIRST_REPLAY_MASK__VI 0x00008000 -#define SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT__VI 15 -#define SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE__VI 1 -#define SQ_WAVE_IB_STS_GET_EXP_CNT__VI(sq_wave_ib_sts) \ - ((sq_wave_ib_sts & SQ_WAVE_IB_STS_EXP_CNT_MASK) >> SQ_WAVE_IB_STS_EXP_CNT_SHIFT) - -#define SQ_WAVE_IB_STS_GET_FIRST_REPLAY__VI(sq_wave_ib_sts) \ - ((sq_wave_ib_sts & SQ_WAVE_IB_STS_FIRST_REPLAY_MASK) >> SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) - -#define SQ_WAVE_IB_STS_GET_LGKM_CNT__VI(sq_wave_ib_sts) \ - ((sq_wave_ib_sts & SQ_WAVE_IB_STS_LGKM_CNT_MASK) >> SQ_WAVE_IB_STS_LGKM_CNT_SHIFT) - -#define SQ_WAVE_IB_STS_GET_RCNT__VI(sq_wave_ib_sts) \ - ((sq_wave_ib_sts & SQ_WAVE_IB_STS_RCNT_MASK) >> SQ_WAVE_IB_STS_RCNT_SHIFT) - -#define SQ_WAVE_IB_STS_GET_VALU_CNT__VI(sq_wave_ib_sts) \ - ((sq_wave_ib_sts & SQ_WAVE_IB_STS_VALU_CNT_MASK) >> SQ_WAVE_IB_STS_VALU_CNT_SHIFT) - -#define SQ_WAVE_IB_STS_GET_VM_CNT__VI(sq_wave_ib_sts) \ - ((sq_wave_ib_sts & SQ_WAVE_IB_STS_VM_CNT_MASK) >> SQ_WAVE_IB_STS_VM_CNT_SHIFT) - -#define SQ_WAVE_IB_STS_MASK__VI \ - (SQ_WAVE_IB_STS_VM_CNT_MASK | SQ_WAVE_IB_STS_EXP_CNT_MASK | SQ_WAVE_IB_STS_LGKM_CNT_MASK | \ - SQ_WAVE_IB_STS_VALU_CNT_MASK | SQ_WAVE_IB_STS_FIRST_REPLAY_MASK | SQ_WAVE_IB_STS_RCNT_MASK) - -#define SQ_WAVE_IB_STS_RCNT_MASK__VI 0x000f0000 -#define SQ_WAVE_IB_STS_RCNT_SHIFT__VI 16 -#define SQ_WAVE_IB_STS_RCNT_SIZE__VI 4 -#define SQ_WAVE_IB_STS_SET_EXP_CNT__VI(sq_wave_ib_sts_reg, exp_cnt) \ - sq_wave_ib_sts_reg = (sq_wave_ib_sts_reg & ~SQ_WAVE_IB_STS_EXP_CNT_MASK) | \ - (exp_cnt << SQ_WAVE_IB_STS_EXP_CNT_SHIFT) - -#define SQ_WAVE_IB_STS_SET_FIRST_REPLAY__VI(sq_wave_ib_sts_reg, first_replay) \ - sq_wave_ib_sts_reg = (sq_wave_ib_sts_reg & ~SQ_WAVE_IB_STS_FIRST_REPLAY_MASK) | \ - (first_replay << SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) - -#define SQ_WAVE_IB_STS_SET_LGKM_CNT__VI(sq_wave_ib_sts_reg, lgkm_cnt) \ - sq_wave_ib_sts_reg = (sq_wave_ib_sts_reg & ~SQ_WAVE_IB_STS_LGKM_CNT_MASK) | \ - (lgkm_cnt << SQ_WAVE_IB_STS_LGKM_CNT_SHIFT) - -#define SQ_WAVE_IB_STS_SET_RCNT__VI(sq_wave_ib_sts_reg, rcnt) \ - sq_wave_ib_sts_reg = \ - (sq_wave_ib_sts_reg & ~SQ_WAVE_IB_STS_RCNT_MASK) | (rcnt << SQ_WAVE_IB_STS_RCNT_SHIFT) - -#define SQ_WAVE_IB_STS_SET_VALU_CNT__VI(sq_wave_ib_sts_reg, valu_cnt) \ - sq_wave_ib_sts_reg = (sq_wave_ib_sts_reg & ~SQ_WAVE_IB_STS_VALU_CNT_MASK) | \ - (valu_cnt << SQ_WAVE_IB_STS_VALU_CNT_SHIFT) - -#define SQ_WAVE_IB_STS_SET_VM_CNT__VI(sq_wave_ib_sts_reg, vm_cnt) \ - sq_wave_ib_sts_reg = \ - (sq_wave_ib_sts_reg & ~SQ_WAVE_IB_STS_VM_CNT_MASK) | (vm_cnt << SQ_WAVE_IB_STS_VM_CNT_SHIFT) - -#define SQ_WAVE_INST_DW0_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_INST_DW0_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_INST_DW0_GET_INST_DW0__VI(sq_wave_inst_dw0) \ - ((sq_wave_inst_dw0 & SQ_WAVE_INST_DW0_INST_DW0_MASK) >> SQ_WAVE_INST_DW0_INST_DW0_SHIFT) - -#define SQ_WAVE_INST_DW0_MASK__VI (SQ_WAVE_INST_DW0_INST_DW0_MASK) - -#define SQ_WAVE_INST_DW0_SET_INST_DW0__VI(sq_wave_inst_dw0_reg, inst_dw0) \ - sq_wave_inst_dw0_reg = (sq_wave_inst_dw0_reg & ~SQ_WAVE_INST_DW0_INST_DW0_MASK) | \ - (inst_dw0 << SQ_WAVE_INST_DW0_INST_DW0_SHIFT) - -#define SQ_WAVE_INST_DW1_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_INST_DW1_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_INST_DW1_GET_INST_DW1__VI(sq_wave_inst_dw1) \ - ((sq_wave_inst_dw1 & SQ_WAVE_INST_DW1_INST_DW1_MASK) >> SQ_WAVE_INST_DW1_INST_DW1_SHIFT) - -#define SQ_WAVE_INST_DW1_MASK__VI (SQ_WAVE_INST_DW1_INST_DW1_MASK) - -#define SQ_WAVE_INST_DW1_SET_INST_DW1__VI(sq_wave_inst_dw1_reg, inst_dw1) \ - sq_wave_inst_dw1_reg = (sq_wave_inst_dw1_reg & ~SQ_WAVE_INST_DW1_INST_DW1_MASK) | \ - (inst_dw1 << SQ_WAVE_INST_DW1_INST_DW1_SHIFT) - -#define SQ_WAVE_LDS_ALLOC_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_LDS_ALLOC_DEFAULT__VI 0x000dc0cd -#define SQ_WAVE_LDS_ALLOC_GET_LDS_BASE__VI(sq_wave_lds_alloc) \ - ((sq_wave_lds_alloc & SQ_WAVE_LDS_ALLOC_LDS_BASE_MASK) >> SQ_WAVE_LDS_ALLOC_LDS_BASE_SHIFT) - -#define SQ_WAVE_LDS_ALLOC_GET_LDS_SIZE__VI(sq_wave_lds_alloc) \ - ((sq_wave_lds_alloc & SQ_WAVE_LDS_ALLOC_LDS_SIZE_MASK) >> SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT) - -#define SQ_WAVE_LDS_ALLOC_MASK__VI \ - (SQ_WAVE_LDS_ALLOC_LDS_BASE_MASK | SQ_WAVE_LDS_ALLOC_LDS_SIZE_MASK) - -#define SQ_WAVE_LDS_ALLOC_SET_LDS_BASE__VI(sq_wave_lds_alloc_reg, lds_base) \ - sq_wave_lds_alloc_reg = (sq_wave_lds_alloc_reg & ~SQ_WAVE_LDS_ALLOC_LDS_BASE_MASK) | \ - (lds_base << SQ_WAVE_LDS_ALLOC_LDS_BASE_SHIFT) - -#define SQ_WAVE_LDS_ALLOC_SET_LDS_SIZE__VI(sq_wave_lds_alloc_reg, lds_size) \ - sq_wave_lds_alloc_reg = (sq_wave_lds_alloc_reg & ~SQ_WAVE_LDS_ALLOC_LDS_SIZE_MASK) | \ - (lds_size << SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT) - -#define SQ_WAVE_M0_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_M0_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_M0_GET_M0__VI(sq_wave_m0) ((sq_wave_m0 & SQ_WAVE_M0_M0_MASK) >> SQ_WAVE_M0_M0_SHIFT) - -#define SQ_WAVE_M0_MASK__VI (SQ_WAVE_M0_M0_MASK) - -#define SQ_WAVE_M0_SET_M0__VI(sq_wave_m0_reg, m0) \ - sq_wave_m0_reg = (sq_wave_m0_reg & ~SQ_WAVE_M0_M0_MASK) | (m0 << SQ_WAVE_M0_M0_SHIFT) - -#define SQ_WAVE_MODE_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_MODE_DEFAULT__VI 0xc80dcdcd -#define SQ_WAVE_MODE_GET_CSP__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_CSP_MASK) >> SQ_WAVE_MODE_CSP_SHIFT) - -#define SQ_WAVE_MODE_GET_DEBUG_EN__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_DEBUG_EN_MASK) >> SQ_WAVE_MODE_DEBUG_EN_SHIFT) - -#define SQ_WAVE_MODE_GET_DX10_CLAMP__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_DX10_CLAMP_MASK) >> SQ_WAVE_MODE_DX10_CLAMP_SHIFT) - -#define SQ_WAVE_MODE_GET_EXCP_EN__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_EXCP_EN_MASK) >> SQ_WAVE_MODE_EXCP_EN_SHIFT) - -#define SQ_WAVE_MODE_GET_FP_DENORM__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_FP_DENORM_MASK) >> SQ_WAVE_MODE_FP_DENORM_SHIFT) - -#define SQ_WAVE_MODE_GET_FP_ROUND__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_FP_ROUND_MASK) >> SQ_WAVE_MODE_FP_ROUND_SHIFT) - -#define SQ_WAVE_MODE_GET_GPR_IDX_EN__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_GPR_IDX_EN_MASK) >> SQ_WAVE_MODE_GPR_IDX_EN_SHIFT) - -#define SQ_WAVE_MODE_GET_IEEE__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_IEEE_MASK) >> SQ_WAVE_MODE_IEEE_SHIFT) - -#define SQ_WAVE_MODE_GET_LOD_CLAMPED__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_LOD_CLAMPED_MASK) >> SQ_WAVE_MODE_LOD_CLAMPED_SHIFT) - -#define SQ_WAVE_MODE_GET_VSKIP__VI(sq_wave_mode) \ - ((sq_wave_mode & SQ_WAVE_MODE_VSKIP_MASK) >> SQ_WAVE_MODE_VSKIP_SHIFT) - -#define SQ_WAVE_MODE_GPR_IDX_EN_MASK__VI 0x08000000 -#define SQ_WAVE_MODE_GPR_IDX_EN_SHIFT__VI 27 -#define SQ_WAVE_MODE_GPR_IDX_EN_SIZE__VI 1 -#define SQ_WAVE_MODE_MASK__VI \ - (SQ_WAVE_MODE_FP_ROUND_MASK | SQ_WAVE_MODE_FP_DENORM_MASK | SQ_WAVE_MODE_DX10_CLAMP_MASK | \ - SQ_WAVE_MODE_IEEE_MASK | SQ_WAVE_MODE_LOD_CLAMPED_MASK | SQ_WAVE_MODE_DEBUG_EN_MASK | \ - SQ_WAVE_MODE_EXCP_EN_MASK | SQ_WAVE_MODE_GPR_IDX_EN_MASK | SQ_WAVE_MODE_VSKIP_MASK | \ - SQ_WAVE_MODE_CSP_MASK) - -#define SQ_WAVE_MODE_SET_CSP__VI(sq_wave_mode_reg, csp) \ - sq_wave_mode_reg = (sq_wave_mode_reg & ~SQ_WAVE_MODE_CSP_MASK) | (csp << SQ_WAVE_MODE_CSP_SHIFT) - -#define SQ_WAVE_MODE_SET_DEBUG_EN__VI(sq_wave_mode_reg, debug_en) \ - sq_wave_mode_reg = \ - (sq_wave_mode_reg & ~SQ_WAVE_MODE_DEBUG_EN_MASK) | (debug_en << SQ_WAVE_MODE_DEBUG_EN_SHIFT) - -#define SQ_WAVE_MODE_SET_DX10_CLAMP__VI(sq_wave_mode_reg, dx10_clamp) \ - sq_wave_mode_reg = (sq_wave_mode_reg & ~SQ_WAVE_MODE_DX10_CLAMP_MASK) | \ - (dx10_clamp << SQ_WAVE_MODE_DX10_CLAMP_SHIFT) - -#define SQ_WAVE_MODE_SET_EXCP_EN__VI(sq_wave_mode_reg, excp_en) \ - sq_wave_mode_reg = \ - (sq_wave_mode_reg & ~SQ_WAVE_MODE_EXCP_EN_MASK) | (excp_en << SQ_WAVE_MODE_EXCP_EN_SHIFT) - -#define SQ_WAVE_MODE_SET_FP_DENORM__VI(sq_wave_mode_reg, fp_denorm) \ - sq_wave_mode_reg = (sq_wave_mode_reg & ~SQ_WAVE_MODE_FP_DENORM_MASK) | \ - (fp_denorm << SQ_WAVE_MODE_FP_DENORM_SHIFT) - -#define SQ_WAVE_MODE_SET_FP_ROUND__VI(sq_wave_mode_reg, fp_round) \ - sq_wave_mode_reg = \ - (sq_wave_mode_reg & ~SQ_WAVE_MODE_FP_ROUND_MASK) | (fp_round << SQ_WAVE_MODE_FP_ROUND_SHIFT) - -#define SQ_WAVE_MODE_SET_GPR_IDX_EN__VI(sq_wave_mode_reg, gpr_idx_en) \ - sq_wave_mode_reg = (sq_wave_mode_reg & ~SQ_WAVE_MODE_GPR_IDX_EN_MASK) | \ - (gpr_idx_en << SQ_WAVE_MODE_GPR_IDX_EN_SHIFT) - -#define SQ_WAVE_MODE_SET_IEEE__VI(sq_wave_mode_reg, ieee) \ - sq_wave_mode_reg = \ - (sq_wave_mode_reg & ~SQ_WAVE_MODE_IEEE_MASK) | (ieee << SQ_WAVE_MODE_IEEE_SHIFT) - -#define SQ_WAVE_MODE_SET_LOD_CLAMPED__VI(sq_wave_mode_reg, lod_clamped) \ - sq_wave_mode_reg = (sq_wave_mode_reg & ~SQ_WAVE_MODE_LOD_CLAMPED_MASK) | \ - (lod_clamped << SQ_WAVE_MODE_LOD_CLAMPED_SHIFT) - -#define SQ_WAVE_MODE_SET_VSKIP__VI(sq_wave_mode_reg, vskip) \ - sq_wave_mode_reg = \ - (sq_wave_mode_reg & ~SQ_WAVE_MODE_VSKIP_MASK) | (vskip << SQ_WAVE_MODE_VSKIP_SHIFT) - -#define SQ_WAVE_PC_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_PC_HI_DEFAULT__VI 0x0000cdcd -#define SQ_WAVE_PC_HI_GET_PC_HI__VI(sq_wave_pc_hi) \ - ((sq_wave_pc_hi & SQ_WAVE_PC_HI_PC_HI_MASK) >> SQ_WAVE_PC_HI_PC_HI_SHIFT) - -#define SQ_WAVE_PC_HI_MASK__VI (SQ_WAVE_PC_HI_PC_HI_MASK) - -#define SQ_WAVE_PC_HI_PC_HI_MASK__SI__CI 0x000000ff -#define SQ_WAVE_PC_HI_PC_HI_MASK__VI 0x0000ffff -#define SQ_WAVE_PC_HI_PC_HI_SIZE__SI__CI 8 -#define SQ_WAVE_PC_HI_PC_HI_SIZE__VI 16 -#define SQ_WAVE_PC_HI_SET_PC_HI__VI(sq_wave_pc_hi_reg, pc_hi) \ - sq_wave_pc_hi_reg = \ - (sq_wave_pc_hi_reg & ~SQ_WAVE_PC_HI_PC_HI_MASK) | (pc_hi << SQ_WAVE_PC_HI_PC_HI_SHIFT) - -#define SQ_WAVE_PC_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_PC_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_PC_LO_GET_PC_LO__VI(sq_wave_pc_lo) \ - ((sq_wave_pc_lo & SQ_WAVE_PC_LO_PC_LO_MASK) >> SQ_WAVE_PC_LO_PC_LO_SHIFT) - -#define SQ_WAVE_PC_LO_MASK__VI (SQ_WAVE_PC_LO_PC_LO_MASK) - -#define SQ_WAVE_PC_LO_SET_PC_LO__VI(sq_wave_pc_lo_reg, pc_lo) \ - sq_wave_pc_lo_reg = \ - (sq_wave_pc_lo_reg & ~SQ_WAVE_PC_LO_PC_LO_MASK) | (pc_lo << SQ_WAVE_PC_LO_PC_LO_SHIFT) - -#define SQ_WAVE_STATUS_ALLOW_REPLAY_MASK__VI 0x00400000 -#define SQ_WAVE_STATUS_ALLOW_REPLAY_SHIFT__VI 22 -#define SQ_WAVE_STATUS_ALLOW_REPLAY_SIZE__VI 1 -#define SQ_WAVE_STATUS_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_STATUS_DEFAULT__VI 0x08cdcdcd -#define SQ_WAVE_STATUS_GET_ALLOW_REPLAY__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_ALLOW_REPLAY_MASK) >> SQ_WAVE_STATUS_ALLOW_REPLAY_SHIFT) - -#define SQ_WAVE_STATUS_GET_COND_DBG_SYS__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_COND_DBG_SYS_MASK) >> SQ_WAVE_STATUS_COND_DBG_SYS_SHIFT) - -#define SQ_WAVE_STATUS_GET_COND_DBG_USER__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_COND_DBG_USER_MASK) >> SQ_WAVE_STATUS_COND_DBG_USER_SHIFT) - -#define SQ_WAVE_STATUS_GET_ECC_ERR__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_ECC_ERR_MASK) >> SQ_WAVE_STATUS_ECC_ERR_SHIFT) - -#define SQ_WAVE_STATUS_GET_EXECZ__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_EXECZ_MASK) >> SQ_WAVE_STATUS_EXECZ_SHIFT) - -#define SQ_WAVE_STATUS_GET_EXPORT_RDY__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_EXPORT_RDY_MASK) >> SQ_WAVE_STATUS_EXPORT_RDY_SHIFT) - -#define SQ_WAVE_STATUS_GET_HALT__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_HALT_MASK) >> SQ_WAVE_STATUS_HALT_SHIFT) - -#define SQ_WAVE_STATUS_GET_INST_ATC__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_INST_ATC_MASK) >> SQ_WAVE_STATUS_INST_ATC_SHIFT) - -#define SQ_WAVE_STATUS_GET_IN_BARRIER__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_IN_BARRIER_MASK) >> SQ_WAVE_STATUS_IN_BARRIER_SHIFT) - -#define SQ_WAVE_STATUS_GET_IN_TG__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_IN_TG_MASK) >> SQ_WAVE_STATUS_IN_TG_SHIFT) - -#define SQ_WAVE_STATUS_GET_MUST_EXPORT__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_MUST_EXPORT_MASK) >> SQ_WAVE_STATUS_MUST_EXPORT_SHIFT) - -#define SQ_WAVE_STATUS_GET_PERF_EN__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_PERF_EN_MASK) >> SQ_WAVE_STATUS_PERF_EN_SHIFT) - -#define SQ_WAVE_STATUS_GET_PRIV__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_PRIV_MASK) >> SQ_WAVE_STATUS_PRIV_SHIFT) - -#define SQ_WAVE_STATUS_GET_SCC__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_SCC_MASK) >> SQ_WAVE_STATUS_SCC_SHIFT) - -#define SQ_WAVE_STATUS_GET_SKIP_EXPORT__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_SKIP_EXPORT_MASK) >> SQ_WAVE_STATUS_SKIP_EXPORT_SHIFT) - -#define SQ_WAVE_STATUS_GET_SPI_PRIO__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_SPI_PRIO_MASK) >> SQ_WAVE_STATUS_SPI_PRIO_SHIFT) - -#define SQ_WAVE_STATUS_GET_TRAP__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_TRAP_MASK) >> SQ_WAVE_STATUS_TRAP_SHIFT) - -#define SQ_WAVE_STATUS_GET_TRAP_EN__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_TRAP_EN_MASK) >> SQ_WAVE_STATUS_TRAP_EN_SHIFT) - -#define SQ_WAVE_STATUS_GET_TTRACE_CU_EN__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_TTRACE_CU_EN_MASK) >> SQ_WAVE_STATUS_TTRACE_CU_EN_SHIFT) - -#define SQ_WAVE_STATUS_GET_TTRACE_EN__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_TTRACE_EN_MASK) >> SQ_WAVE_STATUS_TTRACE_EN_SHIFT) - -#define SQ_WAVE_STATUS_GET_USER_PRIO__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_USER_PRIO_MASK) >> SQ_WAVE_STATUS_USER_PRIO_SHIFT) - -#define SQ_WAVE_STATUS_GET_VALID__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_VALID_MASK) >> SQ_WAVE_STATUS_VALID_SHIFT) - -#define SQ_WAVE_STATUS_GET_VCCZ__VI(sq_wave_status) \ - ((sq_wave_status & SQ_WAVE_STATUS_VCCZ_MASK) >> SQ_WAVE_STATUS_VCCZ_SHIFT) - -#define SQ_WAVE_STATUS_MASK__VI \ - (SQ_WAVE_STATUS_SCC_MASK | SQ_WAVE_STATUS_SPI_PRIO_MASK | SQ_WAVE_STATUS_USER_PRIO_MASK | \ - SQ_WAVE_STATUS_PRIV_MASK | SQ_WAVE_STATUS_TRAP_EN_MASK | SQ_WAVE_STATUS_TTRACE_EN_MASK | \ - SQ_WAVE_STATUS_EXPORT_RDY_MASK | SQ_WAVE_STATUS_EXECZ_MASK | SQ_WAVE_STATUS_VCCZ_MASK | \ - SQ_WAVE_STATUS_IN_TG_MASK | SQ_WAVE_STATUS_IN_BARRIER_MASK | SQ_WAVE_STATUS_HALT_MASK | \ - SQ_WAVE_STATUS_TRAP_MASK | SQ_WAVE_STATUS_TTRACE_CU_EN_MASK | SQ_WAVE_STATUS_VALID_MASK | \ - SQ_WAVE_STATUS_ECC_ERR_MASK | SQ_WAVE_STATUS_SKIP_EXPORT_MASK | SQ_WAVE_STATUS_PERF_EN_MASK | \ - SQ_WAVE_STATUS_COND_DBG_USER_MASK | SQ_WAVE_STATUS_COND_DBG_SYS_MASK | \ - SQ_WAVE_STATUS_ALLOW_REPLAY_MASK | SQ_WAVE_STATUS_INST_ATC_MASK | \ - SQ_WAVE_STATUS_MUST_EXPORT_MASK) - -#define SQ_WAVE_STATUS_SET_ALLOW_REPLAY__VI(sq_wave_status_reg, allow_replay) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_ALLOW_REPLAY_MASK) | \ - (allow_replay << SQ_WAVE_STATUS_ALLOW_REPLAY_SHIFT) - -#define SQ_WAVE_STATUS_SET_COND_DBG_SYS__VI(sq_wave_status_reg, cond_dbg_sys) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_COND_DBG_SYS_MASK) | \ - (cond_dbg_sys << SQ_WAVE_STATUS_COND_DBG_SYS_SHIFT) - -#define SQ_WAVE_STATUS_SET_COND_DBG_USER__VI(sq_wave_status_reg, cond_dbg_user) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_COND_DBG_USER_MASK) | \ - (cond_dbg_user << SQ_WAVE_STATUS_COND_DBG_USER_SHIFT) - -#define SQ_WAVE_STATUS_SET_ECC_ERR__VI(sq_wave_status_reg, ecc_err) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_ECC_ERR_MASK) | \ - (ecc_err << SQ_WAVE_STATUS_ECC_ERR_SHIFT) - -#define SQ_WAVE_STATUS_SET_EXECZ__VI(sq_wave_status_reg, execz) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_EXECZ_MASK) | (execz << SQ_WAVE_STATUS_EXECZ_SHIFT) - -#define SQ_WAVE_STATUS_SET_EXPORT_RDY__VI(sq_wave_status_reg, export_rdy) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_EXPORT_RDY_MASK) | \ - (export_rdy << SQ_WAVE_STATUS_EXPORT_RDY_SHIFT) - -#define SQ_WAVE_STATUS_SET_HALT__VI(sq_wave_status_reg, halt) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_HALT_MASK) | (halt << SQ_WAVE_STATUS_HALT_SHIFT) - -#define SQ_WAVE_STATUS_SET_INST_ATC__VI(sq_wave_status_reg, inst_atc) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_INST_ATC_MASK) | \ - (inst_atc << SQ_WAVE_STATUS_INST_ATC_SHIFT) - -#define SQ_WAVE_STATUS_SET_IN_BARRIER__VI(sq_wave_status_reg, in_barrier) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_IN_BARRIER_MASK) | \ - (in_barrier << SQ_WAVE_STATUS_IN_BARRIER_SHIFT) - -#define SQ_WAVE_STATUS_SET_IN_TG__VI(sq_wave_status_reg, in_tg) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_IN_TG_MASK) | (in_tg << SQ_WAVE_STATUS_IN_TG_SHIFT) - -#define SQ_WAVE_STATUS_SET_MUST_EXPORT__VI(sq_wave_status_reg, must_export) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_MUST_EXPORT_MASK) | \ - (must_export << SQ_WAVE_STATUS_MUST_EXPORT_SHIFT) - -#define SQ_WAVE_STATUS_SET_PERF_EN__VI(sq_wave_status_reg, perf_en) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_PERF_EN_MASK) | \ - (perf_en << SQ_WAVE_STATUS_PERF_EN_SHIFT) - -#define SQ_WAVE_STATUS_SET_PRIV__VI(sq_wave_status_reg, priv) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_PRIV_MASK) | (priv << SQ_WAVE_STATUS_PRIV_SHIFT) - -#define SQ_WAVE_STATUS_SET_SCC__VI(sq_wave_status_reg, scc) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_SCC_MASK) | (scc << SQ_WAVE_STATUS_SCC_SHIFT) - -#define SQ_WAVE_STATUS_SET_SKIP_EXPORT__VI(sq_wave_status_reg, skip_export) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_SKIP_EXPORT_MASK) | \ - (skip_export << SQ_WAVE_STATUS_SKIP_EXPORT_SHIFT) - -#define SQ_WAVE_STATUS_SET_SPI_PRIO__VI(sq_wave_status_reg, spi_prio) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_SPI_PRIO_MASK) | \ - (spi_prio << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) - -#define SQ_WAVE_STATUS_SET_TRAP__VI(sq_wave_status_reg, trap) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_TRAP_MASK) | (trap << SQ_WAVE_STATUS_TRAP_SHIFT) - -#define SQ_WAVE_STATUS_SET_TRAP_EN__VI(sq_wave_status_reg, trap_en) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_TRAP_EN_MASK) | \ - (trap_en << SQ_WAVE_STATUS_TRAP_EN_SHIFT) - -#define SQ_WAVE_STATUS_SET_TTRACE_CU_EN__VI(sq_wave_status_reg, ttrace_cu_en) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_TTRACE_CU_EN_MASK) | \ - (ttrace_cu_en << SQ_WAVE_STATUS_TTRACE_CU_EN_SHIFT) - -#define SQ_WAVE_STATUS_SET_TTRACE_EN__VI(sq_wave_status_reg, ttrace_en) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_TTRACE_EN_MASK) | \ - (ttrace_en << SQ_WAVE_STATUS_TTRACE_EN_SHIFT) - -#define SQ_WAVE_STATUS_SET_USER_PRIO__VI(sq_wave_status_reg, user_prio) \ - sq_wave_status_reg = (sq_wave_status_reg & ~SQ_WAVE_STATUS_USER_PRIO_MASK) | \ - (user_prio << SQ_WAVE_STATUS_USER_PRIO_SHIFT) - -#define SQ_WAVE_STATUS_SET_VALID__VI(sq_wave_status_reg, valid) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_VALID_MASK) | (valid << SQ_WAVE_STATUS_VALID_SHIFT) - -#define SQ_WAVE_STATUS_SET_VCCZ__VI(sq_wave_status_reg, vccz) \ - sq_wave_status_reg = \ - (sq_wave_status_reg & ~SQ_WAVE_STATUS_VCCZ_MASK) | (vccz << SQ_WAVE_STATUS_VCCZ_SHIFT) - -#define SQ_WAVE_STATUS_USER_PRIO_MASK__VI 0x00000018 -#define SQ_WAVE_STATUS_USER_PRIO_SHIFT__VI 3 -#define SQ_WAVE_STATUS_USER_PRIO_SIZE__VI 2 -#define SQ_WAVE_TBA_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TBA_HI_DEFAULT__VI 0x000000cd -#define SQ_WAVE_TBA_HI_GET_ADDR_HI__VI(sq_wave_tba_hi) \ - ((sq_wave_tba_hi & SQ_WAVE_TBA_HI_ADDR_HI_MASK) >> SQ_WAVE_TBA_HI_ADDR_HI_SHIFT) - -#define SQ_WAVE_TBA_HI_MASK__VI (SQ_WAVE_TBA_HI_ADDR_HI_MASK) - -#define SQ_WAVE_TBA_HI_SET_ADDR_HI__VI(sq_wave_tba_hi_reg, addr_hi) \ - sq_wave_tba_hi_reg = (sq_wave_tba_hi_reg & ~SQ_WAVE_TBA_HI_ADDR_HI_MASK) | \ - (addr_hi << SQ_WAVE_TBA_HI_ADDR_HI_SHIFT) - -#define SQ_WAVE_TBA_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TBA_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TBA_LO_GET_ADDR_LO__VI(sq_wave_tba_lo) \ - ((sq_wave_tba_lo & SQ_WAVE_TBA_LO_ADDR_LO_MASK) >> SQ_WAVE_TBA_LO_ADDR_LO_SHIFT) - -#define SQ_WAVE_TBA_LO_MASK__VI (SQ_WAVE_TBA_LO_ADDR_LO_MASK) - -#define SQ_WAVE_TBA_LO_SET_ADDR_LO__VI(sq_wave_tba_lo_reg, addr_lo) \ - sq_wave_tba_lo_reg = (sq_wave_tba_lo_reg & ~SQ_WAVE_TBA_LO_ADDR_LO_MASK) | \ - (addr_lo << SQ_WAVE_TBA_LO_ADDR_LO_SHIFT) - -#define SQ_WAVE_TMA_HI_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TMA_HI_DEFAULT__VI 0x000000cd -#define SQ_WAVE_TMA_HI_GET_ADDR_HI__VI(sq_wave_tma_hi) \ - ((sq_wave_tma_hi & SQ_WAVE_TMA_HI_ADDR_HI_MASK) >> SQ_WAVE_TMA_HI_ADDR_HI_SHIFT) - -#define SQ_WAVE_TMA_HI_MASK__VI (SQ_WAVE_TMA_HI_ADDR_HI_MASK) - -#define SQ_WAVE_TMA_HI_SET_ADDR_HI__VI(sq_wave_tma_hi_reg, addr_hi) \ - sq_wave_tma_hi_reg = (sq_wave_tma_hi_reg & ~SQ_WAVE_TMA_HI_ADDR_HI_MASK) | \ - (addr_hi << SQ_WAVE_TMA_HI_ADDR_HI_SHIFT) - -#define SQ_WAVE_TMA_LO_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TMA_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TMA_LO_GET_ADDR_LO__VI(sq_wave_tma_lo) \ - ((sq_wave_tma_lo & SQ_WAVE_TMA_LO_ADDR_LO_MASK) >> SQ_WAVE_TMA_LO_ADDR_LO_SHIFT) - -#define SQ_WAVE_TMA_LO_MASK__VI (SQ_WAVE_TMA_LO_ADDR_LO_MASK) - -#define SQ_WAVE_TMA_LO_SET_ADDR_LO__VI(sq_wave_tma_lo_reg, addr_lo) \ - sq_wave_tma_lo_reg = (sq_wave_tma_lo_reg & ~SQ_WAVE_TMA_LO_ADDR_LO_MASK) | \ - (addr_lo << SQ_WAVE_TMA_LO_ADDR_LO_SHIFT) - -#define SQ_WAVE_TRAPSTS_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TRAPSTS_DEFAULT__VI 0xc00d05cd -#define SQ_WAVE_TRAPSTS_GET_DP_RATE__VI(sq_wave_trapsts) \ - ((sq_wave_trapsts & SQ_WAVE_TRAPSTS_DP_RATE_MASK) >> SQ_WAVE_TRAPSTS_DP_RATE_SHIFT) - -#define SQ_WAVE_TRAPSTS_GET_EXCP__VI(sq_wave_trapsts) \ - ((sq_wave_trapsts & SQ_WAVE_TRAPSTS_EXCP_MASK) >> SQ_WAVE_TRAPSTS_EXCP_SHIFT) - -#define SQ_WAVE_TRAPSTS_GET_EXCP_CYCLE__VI(sq_wave_trapsts) \ - ((sq_wave_trapsts & SQ_WAVE_TRAPSTS_EXCP_CYCLE_MASK) >> SQ_WAVE_TRAPSTS_EXCP_CYCLE_SHIFT) - -#define SQ_WAVE_TRAPSTS_GET_SAVECTX__VI(sq_wave_trapsts) \ - ((sq_wave_trapsts & SQ_WAVE_TRAPSTS_SAVECTX_MASK) >> SQ_WAVE_TRAPSTS_SAVECTX_SHIFT) - -#define SQ_WAVE_TRAPSTS_MASK__VI \ - (SQ_WAVE_TRAPSTS_EXCP_MASK | SQ_WAVE_TRAPSTS_SAVECTX_MASK | SQ_WAVE_TRAPSTS_EXCP_CYCLE_MASK | \ - SQ_WAVE_TRAPSTS_DP_RATE_MASK) - -#define SQ_WAVE_TRAPSTS_SAVECTX_MASK__VI 0x00000400 -#define SQ_WAVE_TRAPSTS_SAVECTX_SHIFT__VI 10 -#define SQ_WAVE_TRAPSTS_SAVECTX_SIZE__VI 1 -#define SQ_WAVE_TRAPSTS_SET_DP_RATE__VI(sq_wave_trapsts_reg, dp_rate) \ - sq_wave_trapsts_reg = (sq_wave_trapsts_reg & ~SQ_WAVE_TRAPSTS_DP_RATE_MASK) | \ - (dp_rate << SQ_WAVE_TRAPSTS_DP_RATE_SHIFT) - -#define SQ_WAVE_TRAPSTS_SET_EXCP__VI(sq_wave_trapsts_reg, excp) \ - sq_wave_trapsts_reg = \ - (sq_wave_trapsts_reg & ~SQ_WAVE_TRAPSTS_EXCP_MASK) | (excp << SQ_WAVE_TRAPSTS_EXCP_SHIFT) - -#define SQ_WAVE_TRAPSTS_SET_EXCP_CYCLE__VI(sq_wave_trapsts_reg, excp_cycle) \ - sq_wave_trapsts_reg = (sq_wave_trapsts_reg & ~SQ_WAVE_TRAPSTS_EXCP_CYCLE_MASK) | \ - (excp_cycle << SQ_WAVE_TRAPSTS_EXCP_CYCLE_SHIFT) - -#define SQ_WAVE_TRAPSTS_SET_SAVECTX__VI(sq_wave_trapsts_reg, savectx) \ - sq_wave_trapsts_reg = (sq_wave_trapsts_reg & ~SQ_WAVE_TRAPSTS_SAVECTX_MASK) | \ - (savectx << SQ_WAVE_TRAPSTS_SAVECTX_SHIFT) - -#define SQ_WAVE_TTMP0_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP0_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP0_GET_DATA__VI(sq_wave_ttmp0) \ - ((sq_wave_ttmp0 & SQ_WAVE_TTMP0_DATA_MASK) >> SQ_WAVE_TTMP0_DATA_SHIFT) - -#define SQ_WAVE_TTMP0_MASK__VI (SQ_WAVE_TTMP0_DATA_MASK) - -#define SQ_WAVE_TTMP0_SET_DATA__VI(sq_wave_ttmp0_reg, data) \ - sq_wave_ttmp0_reg = \ - (sq_wave_ttmp0_reg & ~SQ_WAVE_TTMP0_DATA_MASK) | (data << SQ_WAVE_TTMP0_DATA_SHIFT) - -#define SQ_WAVE_TTMP10_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP10_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP10_GET_DATA__VI(sq_wave_ttmp10) \ - ((sq_wave_ttmp10 & SQ_WAVE_TTMP10_DATA_MASK) >> SQ_WAVE_TTMP10_DATA_SHIFT) - -#define SQ_WAVE_TTMP10_MASK__VI (SQ_WAVE_TTMP10_DATA_MASK) - -#define SQ_WAVE_TTMP10_SET_DATA__VI(sq_wave_ttmp10_reg, data) \ - sq_wave_ttmp10_reg = \ - (sq_wave_ttmp10_reg & ~SQ_WAVE_TTMP10_DATA_MASK) | (data << SQ_WAVE_TTMP10_DATA_SHIFT) - -#define SQ_WAVE_TTMP11_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP11_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP11_GET_DATA__VI(sq_wave_ttmp11) \ - ((sq_wave_ttmp11 & SQ_WAVE_TTMP11_DATA_MASK) >> SQ_WAVE_TTMP11_DATA_SHIFT) - -#define SQ_WAVE_TTMP11_MASK__VI (SQ_WAVE_TTMP11_DATA_MASK) - -#define SQ_WAVE_TTMP11_SET_DATA__VI(sq_wave_ttmp11_reg, data) \ - sq_wave_ttmp11_reg = \ - (sq_wave_ttmp11_reg & ~SQ_WAVE_TTMP11_DATA_MASK) | (data << SQ_WAVE_TTMP11_DATA_SHIFT) - -#define SQ_WAVE_TTMP1_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP1_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP1_GET_DATA__VI(sq_wave_ttmp1) \ - ((sq_wave_ttmp1 & SQ_WAVE_TTMP1_DATA_MASK) >> SQ_WAVE_TTMP1_DATA_SHIFT) - -#define SQ_WAVE_TTMP1_MASK__VI (SQ_WAVE_TTMP1_DATA_MASK) - -#define SQ_WAVE_TTMP1_SET_DATA__VI(sq_wave_ttmp1_reg, data) \ - sq_wave_ttmp1_reg = \ - (sq_wave_ttmp1_reg & ~SQ_WAVE_TTMP1_DATA_MASK) | (data << SQ_WAVE_TTMP1_DATA_SHIFT) - -#define SQ_WAVE_TTMP2_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP2_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP2_GET_DATA__VI(sq_wave_ttmp2) \ - ((sq_wave_ttmp2 & SQ_WAVE_TTMP2_DATA_MASK) >> SQ_WAVE_TTMP2_DATA_SHIFT) - -#define SQ_WAVE_TTMP2_MASK__VI (SQ_WAVE_TTMP2_DATA_MASK) - -#define SQ_WAVE_TTMP2_SET_DATA__VI(sq_wave_ttmp2_reg, data) \ - sq_wave_ttmp2_reg = \ - (sq_wave_ttmp2_reg & ~SQ_WAVE_TTMP2_DATA_MASK) | (data << SQ_WAVE_TTMP2_DATA_SHIFT) - -#define SQ_WAVE_TTMP3_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP3_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP3_GET_DATA__VI(sq_wave_ttmp3) \ - ((sq_wave_ttmp3 & SQ_WAVE_TTMP3_DATA_MASK) >> SQ_WAVE_TTMP3_DATA_SHIFT) - -#define SQ_WAVE_TTMP3_MASK__VI (SQ_WAVE_TTMP3_DATA_MASK) - -#define SQ_WAVE_TTMP3_SET_DATA__VI(sq_wave_ttmp3_reg, data) \ - sq_wave_ttmp3_reg = \ - (sq_wave_ttmp3_reg & ~SQ_WAVE_TTMP3_DATA_MASK) | (data << SQ_WAVE_TTMP3_DATA_SHIFT) - -#define SQ_WAVE_TTMP4_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP4_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP4_GET_DATA__VI(sq_wave_ttmp4) \ - ((sq_wave_ttmp4 & SQ_WAVE_TTMP4_DATA_MASK) >> SQ_WAVE_TTMP4_DATA_SHIFT) - -#define SQ_WAVE_TTMP4_MASK__VI (SQ_WAVE_TTMP4_DATA_MASK) - -#define SQ_WAVE_TTMP4_SET_DATA__VI(sq_wave_ttmp4_reg, data) \ - sq_wave_ttmp4_reg = \ - (sq_wave_ttmp4_reg & ~SQ_WAVE_TTMP4_DATA_MASK) | (data << SQ_WAVE_TTMP4_DATA_SHIFT) - -#define SQ_WAVE_TTMP5_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP5_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP5_GET_DATA__VI(sq_wave_ttmp5) \ - ((sq_wave_ttmp5 & SQ_WAVE_TTMP5_DATA_MASK) >> SQ_WAVE_TTMP5_DATA_SHIFT) - -#define SQ_WAVE_TTMP5_MASK__VI (SQ_WAVE_TTMP5_DATA_MASK) - -#define SQ_WAVE_TTMP5_SET_DATA__VI(sq_wave_ttmp5_reg, data) \ - sq_wave_ttmp5_reg = \ - (sq_wave_ttmp5_reg & ~SQ_WAVE_TTMP5_DATA_MASK) | (data << SQ_WAVE_TTMP5_DATA_SHIFT) - -#define SQ_WAVE_TTMP6_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP6_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP6_GET_DATA__VI(sq_wave_ttmp6) \ - ((sq_wave_ttmp6 & SQ_WAVE_TTMP6_DATA_MASK) >> SQ_WAVE_TTMP6_DATA_SHIFT) - -#define SQ_WAVE_TTMP6_MASK__VI (SQ_WAVE_TTMP6_DATA_MASK) - -#define SQ_WAVE_TTMP6_SET_DATA__VI(sq_wave_ttmp6_reg, data) \ - sq_wave_ttmp6_reg = \ - (sq_wave_ttmp6_reg & ~SQ_WAVE_TTMP6_DATA_MASK) | (data << SQ_WAVE_TTMP6_DATA_SHIFT) - -#define SQ_WAVE_TTMP7_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP7_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP7_GET_DATA__VI(sq_wave_ttmp7) \ - ((sq_wave_ttmp7 & SQ_WAVE_TTMP7_DATA_MASK) >> SQ_WAVE_TTMP7_DATA_SHIFT) - -#define SQ_WAVE_TTMP7_MASK__VI (SQ_WAVE_TTMP7_DATA_MASK) - -#define SQ_WAVE_TTMP7_SET_DATA__VI(sq_wave_ttmp7_reg, data) \ - sq_wave_ttmp7_reg = \ - (sq_wave_ttmp7_reg & ~SQ_WAVE_TTMP7_DATA_MASK) | (data << SQ_WAVE_TTMP7_DATA_SHIFT) - -#define SQ_WAVE_TTMP8_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP8_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP8_GET_DATA__VI(sq_wave_ttmp8) \ - ((sq_wave_ttmp8 & SQ_WAVE_TTMP8_DATA_MASK) >> SQ_WAVE_TTMP8_DATA_SHIFT) - -#define SQ_WAVE_TTMP8_MASK__VI (SQ_WAVE_TTMP8_DATA_MASK) - -#define SQ_WAVE_TTMP8_SET_DATA__VI(sq_wave_ttmp8_reg, data) \ - sq_wave_ttmp8_reg = \ - (sq_wave_ttmp8_reg & ~SQ_WAVE_TTMP8_DATA_MASK) | (data << SQ_WAVE_TTMP8_DATA_SHIFT) - -#define SQ_WAVE_TTMP9_DEFAULT__SI__CI 0x00000000 -#define SQ_WAVE_TTMP9_DEFAULT__VI 0xcdcdcdcd -#define SQ_WAVE_TTMP9_GET_DATA__VI(sq_wave_ttmp9) \ - ((sq_wave_ttmp9 & SQ_WAVE_TTMP9_DATA_MASK) >> SQ_WAVE_TTMP9_DATA_SHIFT) - -#define SQ_WAVE_TTMP9_MASK__VI (SQ_WAVE_TTMP9_DATA_MASK) - -#define SQ_WAVE_TTMP9_SET_DATA__VI(sq_wave_ttmp9_reg, data) \ - sq_wave_ttmp9_reg = \ - (sq_wave_ttmp9_reg & ~SQ_WAVE_TTMP9_DATA_MASK) | (data << SQ_WAVE_TTMP9_DATA_SHIFT) - -#define SQ_WREXEC_EXEC_HI_ADDR_HI_MASK__VI 0x0000ffff -#define SQ_WREXEC_EXEC_HI_ADDR_HI_SHIFT__VI 0x00000000 -#define SQ_WREXEC_EXEC_HI_ADDR_HI_SIZE__VI 16 -#define SQ_WREXEC_EXEC_HI_ATC_MASK__VI 0x08000000 -#define SQ_WREXEC_EXEC_HI_ATC_SHIFT__VI 27 -#define SQ_WREXEC_EXEC_HI_ATC_SIZE__VI 1 -#define SQ_WREXEC_EXEC_HI_DEFAULT__VI 0xcc00cdcd -#define SQ_WREXEC_EXEC_HI_FIRST_WAVE_MASK__VI 0x04000000 -#define SQ_WREXEC_EXEC_HI_FIRST_WAVE_SHIFT__VI 26 -#define SQ_WREXEC_EXEC_HI_FIRST_WAVE_SIZE__VI 1 -#define SQ_WREXEC_EXEC_HI_GET_ADDR_HI__VI(sq_wrexec_exec_hi) \ - ((sq_wrexec_exec_hi & SQ_WREXEC_EXEC_HI_ADDR_HI_MASK) >> SQ_WREXEC_EXEC_HI_ADDR_HI_SHIFT) - -#define SQ_WREXEC_EXEC_HI_GET_ATC__VI(sq_wrexec_exec_hi) \ - ((sq_wrexec_exec_hi & SQ_WREXEC_EXEC_HI_ATC_MASK) >> SQ_WREXEC_EXEC_HI_ATC_SHIFT) - -#define SQ_WREXEC_EXEC_HI_GET_FIRST_WAVE__VI(sq_wrexec_exec_hi) \ - ((sq_wrexec_exec_hi & SQ_WREXEC_EXEC_HI_FIRST_WAVE_MASK) >> SQ_WREXEC_EXEC_HI_FIRST_WAVE_SHIFT) - -#define SQ_WREXEC_EXEC_HI_GET_MSB__VI(sq_wrexec_exec_hi) \ - ((sq_wrexec_exec_hi & SQ_WREXEC_EXEC_HI_MSB_MASK) >> SQ_WREXEC_EXEC_HI_MSB_SHIFT) - -#define SQ_WREXEC_EXEC_HI_GET_MTYPE__VI(sq_wrexec_exec_hi) \ - ((sq_wrexec_exec_hi & SQ_WREXEC_EXEC_HI_MTYPE_MASK) >> SQ_WREXEC_EXEC_HI_MTYPE_SHIFT) - -#define SQ_WREXEC_EXEC_HI_MASK__VI \ - (SQ_WREXEC_EXEC_HI_ADDR_HI_MASK | SQ_WREXEC_EXEC_HI_FIRST_WAVE_MASK | \ - SQ_WREXEC_EXEC_HI_ATC_MASK | SQ_WREXEC_EXEC_HI_MTYPE_MASK | SQ_WREXEC_EXEC_HI_MSB_MASK) - -#define SQ_WREXEC_EXEC_HI_MSB_MASK__VI 0x80000000 -#define SQ_WREXEC_EXEC_HI_MSB_SHIFT__VI 31 -#define SQ_WREXEC_EXEC_HI_MSB_SIZE__VI 1 -#define SQ_WREXEC_EXEC_HI_MTYPE_MASK__VI 0x70000000 -#define SQ_WREXEC_EXEC_HI_MTYPE_SHIFT__VI 28 -#define SQ_WREXEC_EXEC_HI_MTYPE_SIZE__VI 3 -#define SQ_WREXEC_EXEC_HI_REG_SIZE__VI 32 -#define SQ_WREXEC_EXEC_HI_SET_ADDR_HI__VI(sq_wrexec_exec_hi_reg, addr_hi) \ - sq_wrexec_exec_hi_reg = (sq_wrexec_exec_hi_reg & ~SQ_WREXEC_EXEC_HI_ADDR_HI_MASK) | \ - (addr_hi << SQ_WREXEC_EXEC_HI_ADDR_HI_SHIFT) - -#define SQ_WREXEC_EXEC_HI_SET_ATC__VI(sq_wrexec_exec_hi_reg, atc) \ - sq_wrexec_exec_hi_reg = \ - (sq_wrexec_exec_hi_reg & ~SQ_WREXEC_EXEC_HI_ATC_MASK) | (atc << SQ_WREXEC_EXEC_HI_ATC_SHIFT) - -#define SQ_WREXEC_EXEC_HI_SET_FIRST_WAVE__VI(sq_wrexec_exec_hi_reg, first_wave) \ - sq_wrexec_exec_hi_reg = (sq_wrexec_exec_hi_reg & ~SQ_WREXEC_EXEC_HI_FIRST_WAVE_MASK) | \ - (first_wave << SQ_WREXEC_EXEC_HI_FIRST_WAVE_SHIFT) - -#define SQ_WREXEC_EXEC_HI_SET_MSB__VI(sq_wrexec_exec_hi_reg, msb) \ - sq_wrexec_exec_hi_reg = \ - (sq_wrexec_exec_hi_reg & ~SQ_WREXEC_EXEC_HI_MSB_MASK) | (msb << SQ_WREXEC_EXEC_HI_MSB_SHIFT) - -#define SQ_WREXEC_EXEC_HI_SET_MTYPE__VI(sq_wrexec_exec_hi_reg, mtype) \ - sq_wrexec_exec_hi_reg = (sq_wrexec_exec_hi_reg & ~SQ_WREXEC_EXEC_HI_MTYPE_MASK) | \ - (mtype << SQ_WREXEC_EXEC_HI_MTYPE_SHIFT) - -#define SQ_WREXEC_EXEC_LO_ADDR_LO_MASK__VI 0xffffffff -#define SQ_WREXEC_EXEC_LO_ADDR_LO_SHIFT__VI 0x00000000 -#define SQ_WREXEC_EXEC_LO_ADDR_LO_SIZE__VI 32 -#define SQ_WREXEC_EXEC_LO_DEFAULT__VI 0xcdcdcdcd -#define SQ_WREXEC_EXEC_LO_GET_ADDR_LO__VI(sq_wrexec_exec_lo) \ - ((sq_wrexec_exec_lo & SQ_WREXEC_EXEC_LO_ADDR_LO_MASK) >> SQ_WREXEC_EXEC_LO_ADDR_LO_SHIFT) - -#define SQ_WREXEC_EXEC_LO_MASK__VI (SQ_WREXEC_EXEC_LO_ADDR_LO_MASK) - -#define SQ_WREXEC_EXEC_LO_REG_SIZE__VI 32 -#define SQ_WREXEC_EXEC_LO_SET_ADDR_LO__VI(sq_wrexec_exec_lo_reg, addr_lo) \ - sq_wrexec_exec_lo_reg = (sq_wrexec_exec_lo_reg & ~SQ_WREXEC_EXEC_LO_ADDR_LO_MASK) | \ - (addr_lo << SQ_WREXEC_EXEC_LO_ADDR_LO_SHIFT) - -#define USER_SQC_BANK_DISABLE_GET_SQC0_BANK_DISABLE__VI(user_sqc_bank_disable) \ - ((user_sqc_bank_disable & USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK) >> \ - USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SHIFT) - -#define USER_SQC_BANK_DISABLE_GET_SQC1_BANK_DISABLE__VI(user_sqc_bank_disable) \ - ((user_sqc_bank_disable & USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK) >> \ - USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SHIFT) - -#define USER_SQC_BANK_DISABLE_GET_SQC2_BANK_DISABLE__VI(user_sqc_bank_disable) \ - ((user_sqc_bank_disable & USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK) >> \ - USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SHIFT) - -#define USER_SQC_BANK_DISABLE_GET_SQC3_BANK_DISABLE__VI(user_sqc_bank_disable) \ - ((user_sqc_bank_disable & USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK) >> \ - USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SHIFT) - -#define USER_SQC_BANK_DISABLE_MASK__VI \ - (USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK | USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK | \ - USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK | USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK) - -#define USER_SQC_BANK_DISABLE_SET_SQC0_BANK_DISABLE__VI(user_sqc_bank_disable_reg, \ - sqc0_bank_disable) \ - user_sqc_bank_disable_reg = \ - (user_sqc_bank_disable_reg & ~USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_MASK) | \ - (sqc0_bank_disable << USER_SQC_BANK_DISABLE_SQC0_BANK_DISABLE_SHIFT) - -#define USER_SQC_BANK_DISABLE_SET_SQC1_BANK_DISABLE__VI(user_sqc_bank_disable_reg, \ - sqc1_bank_disable) \ - user_sqc_bank_disable_reg = \ - (user_sqc_bank_disable_reg & ~USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_MASK) | \ - (sqc1_bank_disable << USER_SQC_BANK_DISABLE_SQC1_BANK_DISABLE_SHIFT) - -#define USER_SQC_BANK_DISABLE_SET_SQC2_BANK_DISABLE__VI(user_sqc_bank_disable_reg, \ - sqc2_bank_disable) \ - user_sqc_bank_disable_reg = \ - (user_sqc_bank_disable_reg & ~USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_MASK) | \ - (sqc2_bank_disable << USER_SQC_BANK_DISABLE_SQC2_BANK_DISABLE_SHIFT) - -#define USER_SQC_BANK_DISABLE_SET_SQC3_BANK_DISABLE__VI(user_sqc_bank_disable_reg, \ - sqc3_bank_disable) \ - user_sqc_bank_disable_reg = \ - (user_sqc_bank_disable_reg & ~USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_MASK) | \ - (sqc3_bank_disable << USER_SQC_BANK_DISABLE_SQC3_BANK_DISABLE_SHIFT) - - -#endif // SI_CI_VI_merged_sq_reg_HEADER -#ifndef __VI___SI__CI_sq_reg_h -#define __VI___SI__CI_sq_reg_h - - -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -#if defined(LITTLEENDIAN_CPU) -typedef struct _cc_sqc_bank_disable_t { - unsigned int write_dis : 1; - unsigned int : 15; - unsigned int sqc0_bank_disable : 4; - unsigned int sqc1_bank_disable : 4; - unsigned int sqc2_bank_disable__CI__VI : 4; - unsigned int sqc3_bank_disable__CI__VI : 4; -} cc_sqc_bank_disable_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _cc_sqc_bank_disable_t { - unsigned int sqc3_bank_disable__CI__VI : 4; - unsigned int sqc2_bank_disable__CI__VI : 4; - unsigned int sqc1_bank_disable : 4; - unsigned int sqc0_bank_disable : 4; - unsigned int : 15; - unsigned int write_dis : 1; -} cc_sqc_bank_disable_t; - -#endif -typedef union { - unsigned int val : 32; - cc_sqc_bank_disable_t f; -} cc_sqc_bank_disable_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _cgtt_sq_clk_ctrl_t { - unsigned int on_delay : 4; - unsigned int off_hysteresis : 8; - unsigned int : 17; - unsigned int perfmon_override__VI : 1; - unsigned int core_override : 1; - unsigned int reg_override : 1; -} cgtt_sq_clk_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _cgtt_sq_clk_ctrl_t { - unsigned int reg_override : 1; - unsigned int core_override : 1; - unsigned int perfmon_override__VI : 1; - unsigned int : 17; - unsigned int off_hysteresis : 8; - unsigned int on_delay : 4; -} cgtt_sq_clk_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - cgtt_sq_clk_ctrl_t f; -} cgtt_sq_clk_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _cgtt_sqg_clk_ctrl_t { - unsigned int on_delay : 4; - unsigned int off_hysteresis : 8; - unsigned int : 16; - unsigned int ttrace_override__VI : 1; - unsigned int perfmon_override__VI : 1; - unsigned int core_override : 1; - unsigned int reg_override : 1; -} cgtt_sqg_clk_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _cgtt_sqg_clk_ctrl_t { - unsigned int reg_override : 1; - unsigned int core_override : 1; - unsigned int perfmon_override__VI : 1; - unsigned int ttrace_override__VI : 1; - unsigned int : 16; - unsigned int off_hysteresis : 8; - unsigned int on_delay : 4; -} cgtt_sqg_clk_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - cgtt_sqg_clk_ctrl_t f; -} cgtt_sqg_clk_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sh_mem_ape1_base_t { unsigned int base : 32; } sh_mem_ape1_base_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sh_mem_ape1_base_t { unsigned int base : 32; } sh_mem_ape1_base_t; - -#endif -typedef union { - unsigned int val : 32; - sh_mem_ape1_base_t f; -} sh_mem_ape1_base_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sh_mem_ape1_limit_t { unsigned int limit : 32; } sh_mem_ape1_limit_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sh_mem_ape1_limit_t { unsigned int limit : 32; } sh_mem_ape1_limit_t; - -#endif -typedef union { - unsigned int val : 32; - sh_mem_ape1_limit_t f; -} sh_mem_ape1_limit_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sh_mem_bases_t { - unsigned int private_base : 16; - unsigned int shared_base : 16; -} sh_mem_bases_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sh_mem_bases_t { - unsigned int shared_base : 16; - unsigned int private_base : 16; -} sh_mem_bases_t; - -#endif -typedef union { - unsigned int val : 32; - sh_mem_bases_t f; -} sh_mem_bases_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sh_mem_config_t__SI__CI { - unsigned int ptr32 : 1; - unsigned int private_atc : 1; - unsigned int alignment_mode : 2; - unsigned int default_mtype : 3; - unsigned int ape1_mtype : 3; - unsigned int : 22; -} sh_mem_config_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sh_mem_config_t__SI__CI { - unsigned int : 22; - unsigned int ape1_mtype : 3; - unsigned int default_mtype : 3; - unsigned int alignment_mode : 2; - unsigned int private_atc : 1; - unsigned int ptr32 : 1; -} sh_mem_config_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sh_mem_config_t__SI__CI f; -} sh_mem_config_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sh_mem_config_t__VI { - unsigned int address_mode : 2; - unsigned int private_atc : 1; - unsigned int alignment_mode : 2; - unsigned int default_mtype : 3; - unsigned int ape1_mtype : 3; - unsigned int ape1_atc : 1; - unsigned int : 20; -} sh_mem_config_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sh_mem_config_t__VI { - unsigned int : 20; - unsigned int ape1_atc : 1; - unsigned int ape1_mtype : 3; - unsigned int default_mtype : 3; - unsigned int alignment_mode : 2; - unsigned int private_atc : 1; - unsigned int address_mode : 2; -} sh_mem_config_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sh_mem_config_t__VI f; -} sh_mem_config_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_alu_clk_ctrl_t { - unsigned int force_cu_on_sh0 : 16; - unsigned int force_cu_on_sh1 : 16; -} sq_alu_clk_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_alu_clk_ctrl_t { - unsigned int force_cu_on_sh1 : 16; - unsigned int force_cu_on_sh0 : 16; -} sq_alu_clk_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_alu_clk_ctrl_t f; -} sq_alu_clk_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_buf_rsrc_word0_t { unsigned int base_address : 32; } sq_buf_rsrc_word0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_buf_rsrc_word0_t { unsigned int base_address : 32; } sq_buf_rsrc_word0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_buf_rsrc_word0_t f; -} sq_buf_rsrc_word0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_buf_rsrc_word1_t { - unsigned int base_address_hi : 16; - unsigned int stride : 14; - unsigned int cache_swizzle : 1; - unsigned int swizzle_enable : 1; -} sq_buf_rsrc_word1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_buf_rsrc_word1_t { - unsigned int swizzle_enable : 1; - unsigned int cache_swizzle : 1; - unsigned int stride : 14; - unsigned int base_address_hi : 16; -} sq_buf_rsrc_word1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_buf_rsrc_word1_t f; -} sq_buf_rsrc_word1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_buf_rsrc_word2_t { unsigned int num_records : 32; } sq_buf_rsrc_word2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_buf_rsrc_word2_t { unsigned int num_records : 32; } sq_buf_rsrc_word2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_buf_rsrc_word2_t f; -} sq_buf_rsrc_word2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_buf_rsrc_word3_t { - unsigned int dst_sel_x : 3; - unsigned int dst_sel_y : 3; - unsigned int dst_sel_z : 3; - unsigned int dst_sel_w : 3; - unsigned int num_format : 3; - unsigned int data_format : 4; - unsigned int element_size : 2; - unsigned int index_stride : 2; - unsigned int add_tid_enable : 1; - unsigned int atc__CI__VI : 1; - unsigned int hash_enable : 1; - unsigned int heap : 1; - unsigned int mtype__CI__VI : 3; - unsigned int type : 2; -} sq_buf_rsrc_word3_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_buf_rsrc_word3_t { - unsigned int type : 2; - unsigned int mtype__CI__VI : 3; - unsigned int heap : 1; - unsigned int hash_enable : 1; - unsigned int atc__CI__VI : 1; - unsigned int add_tid_enable : 1; - unsigned int index_stride : 2; - unsigned int element_size : 2; - unsigned int data_format : 4; - unsigned int num_format : 3; - unsigned int dst_sel_w : 3; - unsigned int dst_sel_z : 3; - unsigned int dst_sel_y : 3; - unsigned int dst_sel_x : 3; -} sq_buf_rsrc_word3_t; - -#endif -typedef union { - unsigned int val : 32; - sq_buf_rsrc_word3_t f; -} sq_buf_rsrc_word3_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_cac_mask_t__SI { - unsigned int valu : 1; - unsigned int valu_mul : 1; - unsigned int gpr : 1; - unsigned int : 29; -} sq_cac_mask_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_cac_mask_t__SI { - unsigned int : 29; - unsigned int gpr : 1; - unsigned int valu_mul : 1; - unsigned int valu : 1; -} sq_cac_mask_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_cac_mask_t__SI f; -} sq_cac_mask_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_cmd_t__SI__CI { - unsigned int cmd : 3; - unsigned int : 1; - unsigned int mode : 3; - unsigned int check_vmid : 1; - unsigned int trap_id : 3; - unsigned int : 5; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int : 2; - unsigned int queue_id : 3; - unsigned int : 1; - unsigned int vm_id : 4; -} sq_cmd_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_cmd_t__SI__CI { - unsigned int vm_id : 4; - unsigned int : 1; - unsigned int queue_id : 3; - unsigned int : 2; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int : 5; - unsigned int trap_id : 3; - unsigned int check_vmid : 1; - unsigned int mode : 3; - unsigned int : 1; - unsigned int cmd : 3; -} sq_cmd_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_cmd_t__SI__CI f; -} sq_cmd_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_cmd_t__VI { - unsigned int cmd : 3; - unsigned int : 1; - unsigned int mode : 3; - unsigned int check_vmid : 1; - unsigned int data : 3; - unsigned int : 5; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int : 2; - unsigned int queue_id : 3; - unsigned int : 1; - unsigned int vm_id : 4; -} sq_cmd_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_cmd_t__VI { - unsigned int vm_id : 4; - unsigned int : 1; - unsigned int queue_id : 3; - unsigned int : 2; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int : 5; - unsigned int data : 3; - unsigned int check_vmid : 1; - unsigned int mode : 3; - unsigned int : 1; - unsigned int cmd : 3; -} sq_cmd_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_cmd_t__VI f; -} sq_cmd_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_cmd_timestamp_t { - unsigned int timestamp : 8; - unsigned int : 24; -} sq_cmd_timestamp_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_cmd_timestamp_t { - unsigned int : 24; - unsigned int timestamp : 8; -} sq_cmd_timestamp_t; - -#endif -typedef union { - unsigned int val : 32; - sq_cmd_timestamp_t f; -} sq_cmd_timestamp_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_config_t__SI__CI { - unsigned int unused : 8; - unsigned int debug_en : 1; - unsigned int disable_sca_bypass : 1; - unsigned int disable_ib_dep_check : 1; - unsigned int enable_soft_clause__CI : 1; - unsigned int early_ta_done_disable__CI : 1; - unsigned int dua_flat_lock_enable__CI : 1; - unsigned int dua_lds_bypass_disable__CI : 1; - unsigned int dua_flat_lds_pingpong_disable__CI : 1; - unsigned int : 16; -} sq_config_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_config_t__SI__CI { - unsigned int : 16; - unsigned int dua_flat_lds_pingpong_disable__CI : 1; - unsigned int dua_lds_bypass_disable__CI : 1; - unsigned int dua_flat_lock_enable__CI : 1; - unsigned int early_ta_done_disable__CI : 1; - unsigned int enable_soft_clause__CI : 1; - unsigned int disable_ib_dep_check : 1; - unsigned int disable_sca_bypass : 1; - unsigned int debug_en : 1; - unsigned int unused : 8; -} sq_config_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_config_t__SI__CI f; -} sq_config_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_config_t__VI { - unsigned int unused : 8; - unsigned int debug_en : 1; - unsigned int debug_single_memop : 1; - unsigned int debug_one_inst_clause : 1; - unsigned int : 1; - unsigned int early_ta_done_disable : 1; - unsigned int dua_flat_lock_enable : 1; - unsigned int dua_lds_bypass_disable : 1; - unsigned int dua_flat_lds_pingpong_disable : 1; - unsigned int disable_vmem_soft_clause : 1; - unsigned int disable_smem_soft_clause : 1; - unsigned int enable_hiprio_on_exp_rdy_vs : 1; - unsigned int prio_val_on_exp_rdy_vs : 2; - unsigned int replay_sleep_cnt : 4; - unsigned int : 7; -} sq_config_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_config_t__VI { - unsigned int : 7; - unsigned int replay_sleep_cnt : 4; - unsigned int prio_val_on_exp_rdy_vs : 2; - unsigned int enable_hiprio_on_exp_rdy_vs : 1; - unsigned int disable_smem_soft_clause : 1; - unsigned int disable_vmem_soft_clause : 1; - unsigned int dua_flat_lds_pingpong_disable : 1; - unsigned int dua_lds_bypass_disable : 1; - unsigned int dua_flat_lock_enable : 1; - unsigned int early_ta_done_disable : 1; - unsigned int : 1; - unsigned int debug_one_inst_clause : 1; - unsigned int debug_single_memop : 1; - unsigned int debug_en : 1; - unsigned int unused : 8; -} sq_config_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_config_t__VI f; -} sq_config_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_debug_ctrl_local_t { - unsigned int unused : 8; - unsigned int : 24; -} sq_debug_ctrl_local_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_debug_ctrl_local_t { - unsigned int : 24; - unsigned int unused : 8; -} sq_debug_ctrl_local_t; - -#endif -typedef union { - unsigned int val : 32; - sq_debug_ctrl_local_t f; -} sq_debug_ctrl_local_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_debug_sts_global2_t { - unsigned int fifo_level_gfx0 : 8; - unsigned int fifo_level_gfx1 : 8; - unsigned int fifo_level_immed : 8; - unsigned int fifo_level_host : 8; -} sq_debug_sts_global2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_debug_sts_global2_t { - unsigned int fifo_level_host : 8; - unsigned int fifo_level_immed : 8; - unsigned int fifo_level_gfx1 : 8; - unsigned int fifo_level_gfx0 : 8; -} sq_debug_sts_global2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_debug_sts_global2_t f; -} sq_debug_sts_global2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_debug_sts_global3_t { - unsigned int fifo_level_host_cmd : 4; - unsigned int fifo_level_host_reg : 6; - unsigned int : 22; -} sq_debug_sts_global3_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_debug_sts_global3_t { - unsigned int : 22; - unsigned int fifo_level_host_reg : 6; - unsigned int fifo_level_host_cmd : 4; -} sq_debug_sts_global3_t; - -#endif -typedef union { - unsigned int val : 32; - sq_debug_sts_global3_t f; -} sq_debug_sts_global3_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_debug_sts_global_t { - unsigned int busy : 1; - unsigned int interrupt_msg_busy__CI__VI : 1; - unsigned int : 2; - unsigned int wave_level_sh0 : 12; - unsigned int wave_level_sh1 : 12; - unsigned int : 4; -} sq_debug_sts_global_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_debug_sts_global_t { - unsigned int : 4; - unsigned int wave_level_sh1 : 12; - unsigned int wave_level_sh0 : 12; - unsigned int : 2; - unsigned int interrupt_msg_busy__CI__VI : 1; - unsigned int busy : 1; -} sq_debug_sts_global_t; - -#endif -typedef union { - unsigned int val : 32; - sq_debug_sts_global_t f; -} sq_debug_sts_global_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_debug_sts_local_t { - unsigned int busy : 1; - unsigned int : 3; - unsigned int wave_level : 6; - unsigned int : 22; -} sq_debug_sts_local_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_debug_sts_local_t { - unsigned int : 22; - unsigned int wave_level : 6; - unsigned int : 3; - unsigned int busy : 1; -} sq_debug_sts_local_t; - -#endif -typedef union { - unsigned int val : 32; - sq_debug_sts_local_t f; -} sq_debug_sts_local_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ded_cnt_t__SI__CI { - unsigned int lds_ded : 6; - unsigned int : 2; - unsigned int sgpr_ded : 5; - unsigned int : 3; - unsigned int vgpr_ded : 9; - unsigned int : 7; -} sq_ded_cnt_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ded_cnt_t__SI__CI { - unsigned int : 7; - unsigned int vgpr_ded : 9; - unsigned int : 3; - unsigned int sgpr_ded : 5; - unsigned int : 2; - unsigned int lds_ded : 6; -} sq_ded_cnt_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_ded_cnt_t__SI__CI f; -} sq_ded_cnt_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ded_info_t__SI__CI { - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int source : 3; - unsigned int vm_id : 4; - unsigned int ring_id : 3; - unsigned int : 16; -} sq_ded_info_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ded_info_t__SI__CI { - unsigned int : 16; - unsigned int ring_id : 3; - unsigned int vm_id : 4; - unsigned int source : 3; - unsigned int simd_id : 2; - unsigned int wave_id : 4; -} sq_ded_info_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_ded_info_t__SI__CI f; -} sq_ded_info_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_fifo_sizes_t { - unsigned int interrupt_fifo_size : 4; - unsigned int : 4; - unsigned int ttrace_fifo_size : 4; - unsigned int : 4; - unsigned int export_buf_size : 2; - unsigned int vmem_data_fifo_size : 2; - unsigned int : 12; -} sq_fifo_sizes_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_fifo_sizes_t { - unsigned int : 12; - unsigned int vmem_data_fifo_size : 2; - unsigned int export_buf_size : 2; - unsigned int : 4; - unsigned int ttrace_fifo_size : 4; - unsigned int : 4; - unsigned int interrupt_fifo_size : 4; -} sq_fifo_sizes_t; - -#endif -typedef union { - unsigned int val : 32; - sq_fifo_sizes_t f; -} sq_fifo_sizes_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_flat_scratch_word0_t { - unsigned int size : 19; - unsigned int : 13; -} sq_flat_scratch_word0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_flat_scratch_word0_t { - unsigned int : 13; - unsigned int size : 19; -} sq_flat_scratch_word0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_flat_scratch_word0_t f; -} sq_flat_scratch_word0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_flat_scratch_word1_t { - unsigned int offset : 24; - unsigned int : 8; -} sq_flat_scratch_word1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_flat_scratch_word1_t { - unsigned int : 8; - unsigned int offset : 24; -} sq_flat_scratch_word1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_flat_scratch_word1_t f; -} sq_flat_scratch_word1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_hv_vmid_ctrl_t { - unsigned int default_vmid : 4; - unsigned int allowed_vmid_mask : 16; - unsigned int : 12; -} sq_hv_vmid_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_hv_vmid_ctrl_t { - unsigned int : 12; - unsigned int allowed_vmid_mask : 16; - unsigned int default_vmid : 4; -} sq_hv_vmid_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_hv_vmid_ctrl_t f; -} sq_hv_vmid_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word0_t { unsigned int base_address : 32; } sq_img_rsrc_word0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word0_t { unsigned int base_address : 32; } sq_img_rsrc_word0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word0_t f; -} sq_img_rsrc_word0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word1_t { - unsigned int base_address_hi : 8; - unsigned int min_lod : 12; - unsigned int data_format : 6; - unsigned int num_format : 4; - unsigned int mtype__CI__VI : 2; -} sq_img_rsrc_word1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word1_t { - unsigned int mtype__CI__VI : 2; - unsigned int num_format : 4; - unsigned int data_format : 6; - unsigned int min_lod : 12; - unsigned int base_address_hi : 8; -} sq_img_rsrc_word1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word1_t f; -} sq_img_rsrc_word1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word2_t { - unsigned int width : 14; - unsigned int height : 14; - unsigned int perf_mod : 3; - unsigned int interlaced : 1; -} sq_img_rsrc_word2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word2_t { - unsigned int interlaced : 1; - unsigned int perf_mod : 3; - unsigned int height : 14; - unsigned int width : 14; -} sq_img_rsrc_word2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word2_t f; -} sq_img_rsrc_word2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word3_t { - unsigned int dst_sel_x : 3; - unsigned int dst_sel_y : 3; - unsigned int dst_sel_z : 3; - unsigned int dst_sel_w : 3; - unsigned int base_level : 4; - unsigned int last_level : 4; - unsigned int tiling_index : 5; - unsigned int pow2_pad : 1; - unsigned int mtype__CI__VI : 1; - unsigned int atc__CI__VI : 1; - unsigned int type : 4; -} sq_img_rsrc_word3_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word3_t { - unsigned int type : 4; - unsigned int atc__CI__VI : 1; - unsigned int mtype__CI__VI : 1; - unsigned int pow2_pad : 1; - unsigned int tiling_index : 5; - unsigned int last_level : 4; - unsigned int base_level : 4; - unsigned int dst_sel_w : 3; - unsigned int dst_sel_z : 3; - unsigned int dst_sel_y : 3; - unsigned int dst_sel_x : 3; -} sq_img_rsrc_word3_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word3_t f; -} sq_img_rsrc_word3_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word4_t { - unsigned int depth : 13; - unsigned int pitch : 14; - unsigned int : 5; -} sq_img_rsrc_word4_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word4_t { - unsigned int : 5; - unsigned int pitch : 14; - unsigned int depth : 13; -} sq_img_rsrc_word4_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word4_t f; -} sq_img_rsrc_word4_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word5_t { - unsigned int base_array : 13; - unsigned int last_array : 13; - unsigned int : 6; -} sq_img_rsrc_word5_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word5_t { - unsigned int : 6; - unsigned int last_array : 13; - unsigned int base_array : 13; -} sq_img_rsrc_word5_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word5_t f; -} sq_img_rsrc_word5_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word6_t__SI__CI { - unsigned int min_lod_warn : 12; - unsigned int counter_bank_id__CI : 8; - unsigned int lod_hdw_cnt_en__CI : 1; - unsigned int ununsed__CI : 11; -} sq_img_rsrc_word6_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word6_t__SI__CI { - unsigned int ununsed__CI : 11; - unsigned int lod_hdw_cnt_en__CI : 1; - unsigned int counter_bank_id__CI : 8; - unsigned int min_lod_warn : 12; -} sq_img_rsrc_word6_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word6_t__SI__CI f; -} sq_img_rsrc_word6_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word6_t__VI { - unsigned int min_lod_warn : 12; - unsigned int counter_bank_id : 8; - unsigned int lod_hdw_cnt_en : 1; - unsigned int compression_en : 1; - unsigned int alpha_is_on_msb : 1; - unsigned int color_transform : 1; - unsigned int lost_alpha_bits : 4; - unsigned int lost_color_bits : 4; -} sq_img_rsrc_word6_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word6_t__VI { - unsigned int lost_color_bits : 4; - unsigned int lost_alpha_bits : 4; - unsigned int color_transform : 1; - unsigned int alpha_is_on_msb : 1; - unsigned int compression_en : 1; - unsigned int lod_hdw_cnt_en : 1; - unsigned int counter_bank_id : 8; - unsigned int min_lod_warn : 12; -} sq_img_rsrc_word6_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word6_t__VI f; -} sq_img_rsrc_word6_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word7_t__SI__CI { - unsigned int ununsed : 32; -} sq_img_rsrc_word7_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word7_t__SI__CI { - unsigned int ununsed : 32; -} sq_img_rsrc_word7_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word7_t__SI__CI f; -} sq_img_rsrc_word7_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_rsrc_word7_t__VI { - unsigned int meta_data_address : 32; -} sq_img_rsrc_word7_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_rsrc_word7_t__VI { - unsigned int meta_data_address : 32; -} sq_img_rsrc_word7_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_img_rsrc_word7_t__VI f; -} sq_img_rsrc_word7_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_samp_word0_t { - unsigned int clamp_x : 3; - unsigned int clamp_y : 3; - unsigned int clamp_z : 3; - unsigned int max_aniso_ratio : 3; - unsigned int depth_compare_func : 3; - unsigned int force_unnormalized : 1; - unsigned int aniso_threshold : 3; - unsigned int mc_coord_trunc : 1; - unsigned int force_degamma : 1; - unsigned int aniso_bias : 6; - unsigned int trunc_coord : 1; - unsigned int disable_cube_wrap : 1; - unsigned int filter_mode : 2; - unsigned int compat_mode__VI : 1; -} sq_img_samp_word0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_samp_word0_t { - unsigned int compat_mode__VI : 1; - unsigned int filter_mode : 2; - unsigned int disable_cube_wrap : 1; - unsigned int trunc_coord : 1; - unsigned int aniso_bias : 6; - unsigned int force_degamma : 1; - unsigned int mc_coord_trunc : 1; - unsigned int aniso_threshold : 3; - unsigned int force_unnormalized : 1; - unsigned int depth_compare_func : 3; - unsigned int max_aniso_ratio : 3; - unsigned int clamp_z : 3; - unsigned int clamp_y : 3; - unsigned int clamp_x : 3; -} sq_img_samp_word0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_samp_word0_t f; -} sq_img_samp_word0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_samp_word1_t { - unsigned int min_lod : 12; - unsigned int max_lod : 12; - unsigned int perf_mip : 4; - unsigned int perf_z : 4; -} sq_img_samp_word1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_samp_word1_t { - unsigned int perf_z : 4; - unsigned int perf_mip : 4; - unsigned int max_lod : 12; - unsigned int min_lod : 12; -} sq_img_samp_word1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_samp_word1_t f; -} sq_img_samp_word1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_samp_word2_t { - unsigned int lod_bias : 14; - unsigned int lod_bias_sec : 6; - unsigned int xy_mag_filter : 2; - unsigned int xy_min_filter : 2; - unsigned int z_filter : 2; - unsigned int mip_filter : 2; - unsigned int mip_point_preclamp : 1; - unsigned int disable_lsb_ceil : 1; - unsigned int filter_prec_fix : 1; - unsigned int aniso_override__VI : 1; -} sq_img_samp_word2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_samp_word2_t { - unsigned int aniso_override__VI : 1; - unsigned int filter_prec_fix : 1; - unsigned int disable_lsb_ceil : 1; - unsigned int mip_point_preclamp : 1; - unsigned int mip_filter : 2; - unsigned int z_filter : 2; - unsigned int xy_min_filter : 2; - unsigned int xy_mag_filter : 2; - unsigned int lod_bias_sec : 6; - unsigned int lod_bias : 14; -} sq_img_samp_word2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_samp_word2_t f; -} sq_img_samp_word2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_img_samp_word3_t { - unsigned int border_color_ptr : 12; - unsigned int : 18; - unsigned int border_color_type : 2; -} sq_img_samp_word3_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_img_samp_word3_t { - unsigned int border_color_type : 2; - unsigned int : 18; - unsigned int border_color_ptr : 12; -} sq_img_samp_word3_t; - -#endif -typedef union { - unsigned int val : 32; - sq_img_samp_word3_t f; -} sq_img_samp_word3_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ind_cmd_t__SI__CI { - unsigned int cmd__SI : 3; - unsigned int : 1; - unsigned int mode__SI : 2; - unsigned int : 2; - unsigned int trap_id__SI : 3; - unsigned int : 17; - unsigned int vm_id__SI : 4; -} sq_ind_cmd_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ind_cmd_t__SI__CI { - unsigned int vm_id__SI : 4; - unsigned int : 17; - unsigned int trap_id__SI : 3; - unsigned int : 2; - unsigned int mode__SI : 2; - unsigned int : 1; - unsigned int cmd__SI : 3; -} sq_ind_cmd_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_ind_cmd_t__SI__CI f; -} sq_ind_cmd_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ind_data_t { unsigned int data : 32; } sq_ind_data_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ind_data_t { unsigned int data : 32; } sq_ind_data_t; - -#endif -typedef union { - unsigned int val : 32; - sq_ind_data_t f; -} sq_ind_data_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ind_index_t { - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int thread_id : 6; - unsigned int auto_incr__CI__VI : 1; - unsigned int force_read__CI__VI : 1; - unsigned int read_timeout : 1; - unsigned int unindexed : 1; - unsigned int index : 16; -} sq_ind_index_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ind_index_t { - unsigned int index : 16; - unsigned int unindexed : 1; - unsigned int read_timeout : 1; - unsigned int force_read__CI__VI : 1; - unsigned int auto_incr__CI__VI : 1; - unsigned int thread_id : 6; - unsigned int simd_id : 2; - unsigned int wave_id : 4; -} sq_ind_index_t; - -#endif -typedef union { - unsigned int val : 32; - sq_ind_index_t f; -} sq_ind_index_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_auto_mask_t { - unsigned int mask : 24; - unsigned int : 8; -} sq_interrupt_auto_mask_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_auto_mask_t { - unsigned int : 8; - unsigned int mask : 24; -} sq_interrupt_auto_mask_t; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_auto_mask_t f; -} sq_interrupt_auto_mask_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_msg_ctrl_t { - unsigned int stall : 1; - unsigned int : 31; -} sq_interrupt_msg_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_msg_ctrl_t { - unsigned int : 31; - unsigned int stall : 1; -} sq_interrupt_msg_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_msg_ctrl_t f; -} sq_interrupt_msg_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_auto_t__CI { - unsigned int thread_trace : 1; - unsigned int wlt : 1; - unsigned int thread_trace_buf_full : 1; - unsigned int reg_timestamp : 1; - unsigned int cmd_timestamp : 1; - unsigned int host_cmd_overflow : 1; - unsigned int host_reg_overflow : 1; - unsigned int immed_overflow : 1; - unsigned int : 16; - unsigned int se_id : 2; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_auto_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_auto_t__CI { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 2; - unsigned int : 16; - unsigned int immed_overflow : 1; - unsigned int host_reg_overflow : 1; - unsigned int host_cmd_overflow : 1; - unsigned int cmd_timestamp : 1; - unsigned int reg_timestamp : 1; - unsigned int thread_trace_buf_full : 1; - unsigned int wlt : 1; - unsigned int thread_trace : 1; -} sq_interrupt_word_auto_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_auto_t__CI f; -} sq_interrupt_word_auto_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_auto_t__SI { - unsigned int thread_trace : 1; - unsigned int : 24; - unsigned int se_id : 1; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_auto_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_auto_t__SI { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 1; - unsigned int : 24; - unsigned int thread_trace : 1; -} sq_interrupt_word_auto_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_auto_t__SI f; -} sq_interrupt_word_auto_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_cmn_t__CI { - unsigned int : 24; - unsigned int se_id : 2; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_cmn_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_cmn_t__CI { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 2; - unsigned int : 24; -} sq_interrupt_word_cmn_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_cmn_t__CI f; -} sq_interrupt_word_cmn_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_cmn_t__SI { - unsigned int : 25; - unsigned int se_id : 1; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_cmn_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_cmn_t__SI { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 1; - unsigned int : 25; -} sq_interrupt_word_cmn_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_cmn_t__SI f; -} sq_interrupt_word_cmn_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_wave_t__CI { - unsigned int data : 8; - unsigned int sh_id : 1; - unsigned int priv : 1; - unsigned int vm_id : 4; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int cu_id : 4; - unsigned int se_id : 2; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_wave_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_wave_t__CI { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 2; - unsigned int cu_id : 4; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int vm_id : 4; - unsigned int priv : 1; - unsigned int sh_id : 1; - unsigned int data : 8; -} sq_interrupt_word_wave_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_wave_t__CI f; -} sq_interrupt_word_wave_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_wave_t__SI { - unsigned int data : 8; - unsigned int : 2; - unsigned int vm_id : 4; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int se_id : 1; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_wave_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_wave_t__SI { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 1; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int vm_id : 4; - unsigned int : 2; - unsigned int data : 8; -} sq_interrupt_word_wave_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_wave_t__SI f; -} sq_interrupt_word_wave_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_lb_ctr_ctrl_t { - unsigned int start : 1; - unsigned int load : 1; - unsigned int clear : 1; - unsigned int : 29; -} sq_lb_ctr_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_lb_ctr_ctrl_t { - unsigned int : 29; - unsigned int clear : 1; - unsigned int load : 1; - unsigned int start : 1; -} sq_lb_ctr_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_lb_ctr_ctrl_t f; -} sq_lb_ctr_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_lb_data_alu_cycles_t { unsigned int data : 32; } sq_lb_data_alu_cycles_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_lb_data_alu_cycles_t { unsigned int data : 32; } sq_lb_data_alu_cycles_t; - -#endif -typedef union { - unsigned int val : 32; - sq_lb_data_alu_cycles_t f; -} sq_lb_data_alu_cycles_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_lb_data_alu_stalls_t { unsigned int data : 32; } sq_lb_data_alu_stalls_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_lb_data_alu_stalls_t { unsigned int data : 32; } sq_lb_data_alu_stalls_t; - -#endif -typedef union { - unsigned int val : 32; - sq_lb_data_alu_stalls_t f; -} sq_lb_data_alu_stalls_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_lb_data_tex_cycles_t { unsigned int data : 32; } sq_lb_data_tex_cycles_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_lb_data_tex_cycles_t { unsigned int data : 32; } sq_lb_data_tex_cycles_t; - -#endif -typedef union { - unsigned int val : 32; - sq_lb_data_tex_cycles_t f; -} sq_lb_data_tex_cycles_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_lb_data_tex_stalls_t { unsigned int data : 32; } sq_lb_data_tex_stalls_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_lb_data_tex_stalls_t { unsigned int data : 32; } sq_lb_data_tex_stalls_t; - -#endif -typedef union { - unsigned int val : 32; - sq_lb_data_tex_stalls_t f; -} sq_lb_data_tex_stalls_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_lds_clk_ctrl_t { - unsigned int force_cu_on_sh0 : 16; - unsigned int force_cu_on_sh1 : 16; -} sq_lds_clk_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_lds_clk_ctrl_t { - unsigned int force_cu_on_sh1 : 16; - unsigned int force_cu_on_sh0 : 16; -} sq_lds_clk_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_lds_clk_ctrl_t f; -} sq_lds_clk_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter0_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter0_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter0_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter0_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter0_hi_t f; -} sq_perfcounter0_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter0_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter0_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter0_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter0_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter0_lo_t f; -} sq_perfcounter0_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter0_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter0_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter0_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter0_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter0_select_t__CI f; -} sq_perfcounter0_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter0_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter0_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter0_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter0_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter0_select_t__SI f; -} sq_perfcounter0_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter10_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter10_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter10_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter10_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter10_hi_t f; -} sq_perfcounter10_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter10_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter10_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter10_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter10_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter10_lo_t f; -} sq_perfcounter10_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter10_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter10_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter10_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter10_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter10_select_t__CI f; -} sq_perfcounter10_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter10_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter10_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter10_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter10_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter10_select_t__SI f; -} sq_perfcounter10_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter11_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter11_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter11_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter11_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter11_hi_t f; -} sq_perfcounter11_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter11_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter11_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter11_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter11_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter11_lo_t f; -} sq_perfcounter11_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter11_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter11_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter11_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter11_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter11_select_t__CI f; -} sq_perfcounter11_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter11_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter11_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter11_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter11_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter11_select_t__SI f; -} sq_perfcounter11_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter12_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter12_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter12_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter12_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter12_hi_t f; -} sq_perfcounter12_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter12_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter12_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter12_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter12_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter12_lo_t f; -} sq_perfcounter12_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter12_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter12_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter12_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter12_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter12_select_t__CI f; -} sq_perfcounter12_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter12_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter12_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter12_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter12_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter12_select_t__SI f; -} sq_perfcounter12_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter13_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter13_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter13_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter13_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter13_hi_t f; -} sq_perfcounter13_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter13_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter13_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter13_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter13_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter13_lo_t f; -} sq_perfcounter13_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter13_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter13_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter13_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter13_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter13_select_t__CI f; -} sq_perfcounter13_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter13_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter13_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter13_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter13_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter13_select_t__SI f; -} sq_perfcounter13_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter14_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter14_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter14_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter14_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter14_hi_t f; -} sq_perfcounter14_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter14_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter14_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter14_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter14_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter14_lo_t f; -} sq_perfcounter14_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter14_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter14_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter14_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter14_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter14_select_t__CI f; -} sq_perfcounter14_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter14_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter14_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter14_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter14_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter14_select_t__SI f; -} sq_perfcounter14_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter15_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter15_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter15_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter15_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter15_hi_t f; -} sq_perfcounter15_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter15_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter15_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter15_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter15_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter15_lo_t f; -} sq_perfcounter15_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter15_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter15_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter15_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter15_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter15_select_t__CI f; -} sq_perfcounter15_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter15_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter15_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter15_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter15_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter15_select_t__SI f; -} sq_perfcounter15_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter1_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter1_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter1_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter1_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter1_hi_t f; -} sq_perfcounter1_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter1_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter1_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter1_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter1_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter1_lo_t f; -} sq_perfcounter1_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter1_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter1_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter1_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter1_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter1_select_t__CI f; -} sq_perfcounter1_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter1_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter1_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter1_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter1_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter1_select_t__SI f; -} sq_perfcounter1_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter2_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter2_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter2_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter2_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter2_hi_t f; -} sq_perfcounter2_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter2_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter2_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter2_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter2_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter2_lo_t f; -} sq_perfcounter2_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter2_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter2_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter2_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter2_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter2_select_t__CI f; -} sq_perfcounter2_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter2_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter2_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter2_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter2_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter2_select_t__SI f; -} sq_perfcounter2_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter3_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter3_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter3_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter3_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter3_hi_t f; -} sq_perfcounter3_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter3_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter3_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter3_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter3_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter3_lo_t f; -} sq_perfcounter3_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter3_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter3_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter3_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter3_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter3_select_t__CI f; -} sq_perfcounter3_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter3_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter3_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter3_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter3_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter3_select_t__SI f; -} sq_perfcounter3_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter4_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter4_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter4_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter4_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter4_hi_t f; -} sq_perfcounter4_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter4_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter4_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter4_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter4_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter4_lo_t f; -} sq_perfcounter4_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter4_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter4_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter4_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter4_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter4_select_t__CI f; -} sq_perfcounter4_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter4_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter4_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter4_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter4_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter4_select_t__SI f; -} sq_perfcounter4_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter5_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter5_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter5_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter5_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter5_hi_t f; -} sq_perfcounter5_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter5_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter5_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter5_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter5_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter5_lo_t f; -} sq_perfcounter5_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter5_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter5_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter5_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter5_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter5_select_t__CI f; -} sq_perfcounter5_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter5_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter5_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter5_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter5_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter5_select_t__SI f; -} sq_perfcounter5_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter6_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter6_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter6_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter6_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter6_hi_t f; -} sq_perfcounter6_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter6_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter6_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter6_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter6_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter6_lo_t f; -} sq_perfcounter6_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter6_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter6_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter6_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter6_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter6_select_t__CI f; -} sq_perfcounter6_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter6_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter6_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter6_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter6_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter6_select_t__SI f; -} sq_perfcounter6_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter7_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter7_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter7_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter7_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter7_hi_t f; -} sq_perfcounter7_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter7_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter7_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter7_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter7_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter7_lo_t f; -} sq_perfcounter7_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter7_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter7_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter7_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter7_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter7_select_t__CI f; -} sq_perfcounter7_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter7_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter7_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter7_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter7_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter7_select_t__SI f; -} sq_perfcounter7_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter8_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter8_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter8_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter8_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter8_hi_t f; -} sq_perfcounter8_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter8_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter8_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter8_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter8_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter8_lo_t f; -} sq_perfcounter8_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter8_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter8_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter8_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter8_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter8_select_t__CI f; -} sq_perfcounter8_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter8_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter8_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter8_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter8_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter8_select_t__SI f; -} sq_perfcounter8_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter9_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter9_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter9_hi_t { unsigned int perfcounter_hi : 32; } sq_perfcounter9_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter9_hi_t f; -} sq_perfcounter9_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter9_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter9_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter9_lo_t { unsigned int perfcounter_lo : 32; } sq_perfcounter9_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter9_lo_t f; -} sq_perfcounter9_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter9_select_t__CI { - unsigned int perf_sel : 8; - unsigned int : 4; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter9_select_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter9_select_t__CI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 4; - unsigned int perf_sel : 8; -} sq_perfcounter9_select_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter9_select_t__CI f; -} sq_perfcounter9_select_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter9_select_t__SI { - unsigned int perf_sel : 9; - unsigned int : 15; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter9_select_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter9_select_t__SI { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int : 15; - unsigned int perf_sel : 9; -} sq_perfcounter9_select_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter9_select_t__SI f; -} sq_perfcounter9_select_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter_ctrl2_t { - unsigned int force_en : 1; - unsigned int : 31; -} sq_perfcounter_ctrl2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter_ctrl2_t { - unsigned int : 31; - unsigned int force_en : 1; -} sq_perfcounter_ctrl2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter_ctrl2_t f; -} sq_perfcounter_ctrl2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter_ctrl_t { - unsigned int ps_en : 1; - unsigned int vs_en : 1; - unsigned int gs_en : 1; - unsigned int es_en : 1; - unsigned int hs_en : 1; - unsigned int ls_en : 1; - unsigned int cs_en : 1; - unsigned int : 1; - unsigned int cntr_rate : 5; - unsigned int disable_flush : 1; - unsigned int : 18; -} sq_perfcounter_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter_ctrl_t { - unsigned int : 18; - unsigned int disable_flush : 1; - unsigned int cntr_rate : 5; - unsigned int : 1; - unsigned int cs_en : 1; - unsigned int ls_en : 1; - unsigned int hs_en : 1; - unsigned int es_en : 1; - unsigned int gs_en : 1; - unsigned int vs_en : 1; - unsigned int ps_en : 1; -} sq_perfcounter_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter_ctrl_t f; -} sq_perfcounter_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter_mask_t { - unsigned int sh0_mask : 16; - unsigned int sh1_mask : 16; -} sq_perfcounter_mask_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter_mask_t { - unsigned int sh1_mask : 16; - unsigned int sh0_mask : 16; -} sq_perfcounter_mask_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter_mask_t f; -} sq_perfcounter_mask_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_power_throttle2_t { - unsigned int max_power_delta : 14; - unsigned int : 2; - unsigned int short_term_interval_size : 10; - unsigned int : 1; - unsigned int long_term_interval_ratio : 4; - unsigned int use_ref_clock : 1; -} sq_power_throttle2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_power_throttle2_t { - unsigned int use_ref_clock : 1; - unsigned int long_term_interval_ratio : 4; - unsigned int : 1; - unsigned int short_term_interval_size : 10; - unsigned int : 2; - unsigned int max_power_delta : 14; -} sq_power_throttle2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_power_throttle2_t f; -} sq_power_throttle2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_power_throttle_t { - unsigned int min_power : 14; - unsigned int : 2; - unsigned int max_power : 14; - unsigned int phase_offset : 2; -} sq_power_throttle_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_power_throttle_t { - unsigned int phase_offset : 2; - unsigned int max_power : 14; - unsigned int : 2; - unsigned int min_power : 14; -} sq_power_throttle_t; - -#endif -typedef union { - unsigned int val : 32; - sq_power_throttle_t f; -} sq_power_throttle_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_random_wave_pri_t { - unsigned int ret : 7; - unsigned int rui : 3; - unsigned int rng : 11; - unsigned int : 11; -} sq_random_wave_pri_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_random_wave_pri_t { - unsigned int : 11; - unsigned int rng : 11; - unsigned int rui : 3; - unsigned int ret : 7; -} sq_random_wave_pri_t; - -#endif -typedef union { - unsigned int val : 32; - sq_random_wave_pri_t f; -} sq_random_wave_pri_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_reg_credits_t { - unsigned int srbm_credits : 6; - unsigned int : 2; - unsigned int cmd_credits : 4; - unsigned int : 16; - unsigned int reg_busy__CI__VI : 1; - unsigned int srbm_overflow__CI__VI : 1; - unsigned int immed_overflow__CI__VI : 1; - unsigned int cmd_overflow__CI__VI : 1; -} sq_reg_credits_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_reg_credits_t { - unsigned int cmd_overflow__CI__VI : 1; - unsigned int immed_overflow__CI__VI : 1; - unsigned int srbm_overflow__CI__VI : 1; - unsigned int reg_busy__CI__VI : 1; - unsigned int : 16; - unsigned int cmd_credits : 4; - unsigned int : 2; - unsigned int srbm_credits : 6; -} sq_reg_credits_t; - -#endif -typedef union { - unsigned int val : 32; - sq_reg_credits_t f; -} sq_reg_credits_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_reg_timestamp_t { - unsigned int timestamp : 8; - unsigned int : 24; -} sq_reg_timestamp_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_reg_timestamp_t { - unsigned int : 24; - unsigned int timestamp : 8; -} sq_reg_timestamp_t; - -#endif -typedef union { - unsigned int val : 32; - sq_reg_timestamp_t f; -} sq_reg_timestamp_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_sec_cnt_t__SI__CI { - unsigned int lds_sec : 6; - unsigned int : 2; - unsigned int sgpr_sec : 5; - unsigned int : 3; - unsigned int vgpr_sec : 9; - unsigned int : 7; -} sq_sec_cnt_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_sec_cnt_t__SI__CI { - unsigned int : 7; - unsigned int vgpr_sec : 9; - unsigned int : 3; - unsigned int sgpr_sec : 5; - unsigned int : 2; - unsigned int lds_sec : 6; -} sq_sec_cnt_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_sec_cnt_t__SI__CI f; -} sq_sec_cnt_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_tex_clk_ctrl_t { - unsigned int force_cu_on_sh0 : 16; - unsigned int force_cu_on_sh1 : 16; -} sq_tex_clk_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_tex_clk_ctrl_t { - unsigned int force_cu_on_sh1 : 16; - unsigned int force_cu_on_sh0 : 16; -} sq_tex_clk_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_tex_clk_ctrl_t f; -} sq_tex_clk_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_base2_t { - unsigned int addr_hi : 4; - unsigned int atc : 1; - unsigned int : 27; -} sq_thread_trace_base2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_base2_t { - unsigned int : 27; - unsigned int atc : 1; - unsigned int addr_hi : 4; -} sq_thread_trace_base2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_base2_t f; -} sq_thread_trace_base2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_base_t { unsigned int addr : 32; } sq_thread_trace_base_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_base_t { unsigned int addr : 32; } sq_thread_trace_base_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_base_t f; -} sq_thread_trace_base_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_cntr_t { unsigned int cntr : 32; } sq_thread_trace_cntr_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_cntr_t { unsigned int cntr : 32; } sq_thread_trace_cntr_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_cntr_t f; -} sq_thread_trace_cntr_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_ctrl_t { - unsigned int : 31; - unsigned int reset_buffer : 1; -} sq_thread_trace_ctrl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_ctrl_t { - unsigned int reset_buffer : 1; - unsigned int : 31; -} sq_thread_trace_ctrl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_ctrl_t f; -} sq_thread_trace_ctrl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_hiwater_t { - unsigned int hiwater : 3; - unsigned int : 29; -} sq_thread_trace_hiwater_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_hiwater_t { - unsigned int : 29; - unsigned int hiwater : 3; -} sq_thread_trace_hiwater_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_hiwater_t f; -} sq_thread_trace_hiwater_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_mask_t { - unsigned int cu_sel : 5; - unsigned int sh_sel : 1; - unsigned int : 1; - unsigned int reg_stall_en__CI__VI : 1; - unsigned int simd_en : 4; - unsigned int vm_id_mask : 2; - unsigned int spi_stall_en__CI__VI : 1; - unsigned int sq_stall_en__CI__VI : 1; - unsigned int random_seed : 16; -} sq_thread_trace_mask_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_mask_t { - unsigned int random_seed : 16; - unsigned int sq_stall_en__CI__VI : 1; - unsigned int spi_stall_en__CI__VI : 1; - unsigned int vm_id_mask : 2; - unsigned int simd_en : 4; - unsigned int reg_stall_en__CI__VI : 1; - unsigned int : 1; - unsigned int sh_sel : 1; - unsigned int cu_sel : 5; -} sq_thread_trace_mask_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_mask_t f; -} sq_thread_trace_mask_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_mode_t { - unsigned int mask_ps : 3; - unsigned int mask_vs : 3; - unsigned int mask_gs : 3; - unsigned int mask_es : 3; - unsigned int mask_hs : 3; - unsigned int mask_ls : 3; - unsigned int mask_cs : 3; - unsigned int mode : 2; - unsigned int capture_mode : 2; - unsigned int autoflush_en : 1; - unsigned int priv : 1; - unsigned int issue_mask : 2; - unsigned int test_mode : 1; - unsigned int interrupt_en : 1; - unsigned int wrap : 1; -} sq_thread_trace_mode_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_mode_t { - unsigned int wrap : 1; - unsigned int interrupt_en : 1; - unsigned int test_mode : 1; - unsigned int issue_mask : 2; - unsigned int priv : 1; - unsigned int autoflush_en : 1; - unsigned int capture_mode : 2; - unsigned int mode : 2; - unsigned int mask_cs : 3; - unsigned int mask_ls : 3; - unsigned int mask_hs : 3; - unsigned int mask_es : 3; - unsigned int mask_gs : 3; - unsigned int mask_vs : 3; - unsigned int mask_ps : 3; -} sq_thread_trace_mode_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_mode_t f; -} sq_thread_trace_mode_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_perf_mask_t { - unsigned int sh0_mask : 16; - unsigned int sh1_mask : 16; -} sq_thread_trace_perf_mask_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_perf_mask_t { - unsigned int sh1_mask : 16; - unsigned int sh0_mask : 16; -} sq_thread_trace_perf_mask_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_perf_mask_t f; -} sq_thread_trace_perf_mask_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_size_t { - unsigned int size : 22; - unsigned int : 10; -} sq_thread_trace_size_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_size_t { - unsigned int : 10; - unsigned int size : 22; -} sq_thread_trace_size_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_size_t f; -} sq_thread_trace_size_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_status_t { - unsigned int finish_pending : 10; - unsigned int : 6; - unsigned int finish_done : 10; - unsigned int : 3; - unsigned int new_buf : 1; - unsigned int busy : 1; - unsigned int full : 1; -} sq_thread_trace_status_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_status_t { - unsigned int full : 1; - unsigned int busy : 1; - unsigned int new_buf : 1; - unsigned int : 3; - unsigned int finish_done : 10; - unsigned int : 6; - unsigned int finish_pending : 10; -} sq_thread_trace_status_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_status_t f; -} sq_thread_trace_status_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_token_mask2_t__SI__CI { - unsigned int inst_mask : 16; - unsigned int : 16; -} sq_thread_trace_token_mask2_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_token_mask2_t__SI__CI { - unsigned int : 16; - unsigned int inst_mask : 16; -} sq_thread_trace_token_mask2_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_token_mask2_t__SI__CI f; -} sq_thread_trace_token_mask2_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_token_mask2_t__VI { - unsigned int inst_mask : 32; -} sq_thread_trace_token_mask2_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_token_mask2_t__VI { - unsigned int inst_mask : 32; -} sq_thread_trace_token_mask2_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_token_mask2_t__VI f; -} sq_thread_trace_token_mask2_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_token_mask_t { - unsigned int token_mask : 16; - unsigned int reg_mask : 8; - unsigned int reg_drop_on_stall__CI__VI : 1; - unsigned int : 7; -} sq_thread_trace_token_mask_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_token_mask_t { - unsigned int : 7; - unsigned int reg_drop_on_stall__CI__VI : 1; - unsigned int reg_mask : 8; - unsigned int token_mask : 16; -} sq_thread_trace_token_mask_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_token_mask_t f; -} sq_thread_trace_token_mask_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_0_t { - unsigned int data : 32; -} sq_thread_trace_userdata_0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_0_t { - unsigned int data : 32; -} sq_thread_trace_userdata_0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_userdata_0_t f; -} sq_thread_trace_userdata_0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_1_t { - unsigned int data : 32; -} sq_thread_trace_userdata_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_1_t { - unsigned int data : 32; -} sq_thread_trace_userdata_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_userdata_1_t f; -} sq_thread_trace_userdata_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_2_t { - unsigned int data : 32; -} sq_thread_trace_userdata_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_2_t { - unsigned int data : 32; -} sq_thread_trace_userdata_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_userdata_2_t f; -} sq_thread_trace_userdata_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_3_t { - unsigned int data : 32; -} sq_thread_trace_userdata_3_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_userdata_3_t { - unsigned int data : 32; -} sq_thread_trace_userdata_3_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_userdata_3_t f; -} sq_thread_trace_userdata_3_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_cmn_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int : 27; -} sq_thread_trace_word_cmn_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_cmn_t { - unsigned int : 27; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_cmn_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_cmn_t f; -} sq_thread_trace_word_cmn_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_event_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int sh_id : 1; - unsigned int stage : 3; - unsigned int : 1; - unsigned int event_type : 6; - unsigned int : 16; -} sq_thread_trace_word_event_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_event_t { - unsigned int : 16; - unsigned int event_type : 6; - unsigned int : 1; - unsigned int stage : 3; - unsigned int sh_id : 1; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_event_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_event_t f; -} sq_thread_trace_word_event_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_pc_1_of_2_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int : 5; - unsigned int pc_lo : 16; -} sq_thread_trace_word_inst_pc_1_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_pc_1_of_2_t { - unsigned int pc_lo : 16; - unsigned int : 5; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_inst_pc_1_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_inst_pc_1_of_2_t f; -} sq_thread_trace_word_inst_pc_1_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_pc_2_of_2_t { - unsigned int pc_hi : 24; - unsigned int : 8; -} sq_thread_trace_word_inst_pc_2_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_pc_2_of_2_t { - unsigned int : 8; - unsigned int pc_hi : 24; -} sq_thread_trace_word_inst_pc_2_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_inst_pc_2_of_2_t f; -} sq_thread_trace_word_inst_pc_2_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_t__SI__CI { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int size : 1; - unsigned int inst_type : 4; - unsigned int : 16; -} sq_thread_trace_word_inst_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_t__SI__CI { - unsigned int : 16; - unsigned int inst_type : 4; - unsigned int size : 1; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_inst_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_inst_t__SI__CI f; -} sq_thread_trace_word_inst_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_t__VI { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int inst_type : 5; - unsigned int : 16; -} sq_thread_trace_word_inst_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_t__VI { - unsigned int : 16; - unsigned int inst_type : 5; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_inst_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_inst_t__VI f; -} sq_thread_trace_word_inst_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_userdata_1_of_2_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int data_lo : 16; -} sq_thread_trace_word_inst_userdata_1_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_userdata_1_of_2_t { - unsigned int data_lo : 16; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_inst_userdata_1_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_inst_userdata_1_of_2_t f; -} sq_thread_trace_word_inst_userdata_1_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_userdata_2_of_2_t { - unsigned int data_hi : 16; - unsigned int : 16; -} sq_thread_trace_word_inst_userdata_2_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_inst_userdata_2_of_2_t { - unsigned int : 16; - unsigned int data_hi : 16; -} sq_thread_trace_word_inst_userdata_2_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_inst_userdata_2_of_2_t f; -} sq_thread_trace_word_inst_userdata_2_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_issue_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int simd_id : 2; - unsigned int : 1; - unsigned int inst0 : 2; - unsigned int inst1 : 2; - unsigned int inst2 : 2; - unsigned int inst3 : 2; - unsigned int inst4 : 2; - unsigned int inst5 : 2; - unsigned int inst6 : 2; - unsigned int inst7 : 2; - unsigned int inst8 : 2; - unsigned int inst9 : 2; - unsigned int : 4; -} sq_thread_trace_word_issue_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_issue_t { - unsigned int : 4; - unsigned int inst9 : 2; - unsigned int inst8 : 2; - unsigned int inst7 : 2; - unsigned int inst6 : 2; - unsigned int inst5 : 2; - unsigned int inst4 : 2; - unsigned int inst3 : 2; - unsigned int inst2 : 2; - unsigned int inst1 : 2; - unsigned int inst0 : 2; - unsigned int : 1; - unsigned int simd_id : 2; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_issue_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_issue_t f; -} sq_thread_trace_word_issue_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_misc_t__CI { - unsigned int token_type : 4; - unsigned int time_delta : 8; - unsigned int sh_id : 1; - unsigned int misc_token_type : 3; - unsigned int : 16; -} sq_thread_trace_word_misc_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_misc_t__CI { - unsigned int : 16; - unsigned int misc_token_type : 3; - unsigned int sh_id : 1; - unsigned int time_delta : 8; - unsigned int token_type : 4; -} sq_thread_trace_word_misc_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_misc_t__CI f; -} sq_thread_trace_word_misc_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_misc_t__SI { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int sh_id : 1; - unsigned int misc_token_type : 2; - unsigned int : 24; -} sq_thread_trace_word_misc_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_misc_t__SI { - unsigned int : 24; - unsigned int misc_token_type : 2; - unsigned int sh_id : 1; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_misc_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_misc_t__SI f; -} sq_thread_trace_word_misc_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_perf_1_of_2_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int cntr_bank : 2; - unsigned int cntr0 : 13; - unsigned int cntr1_lo : 7; -} sq_thread_trace_word_perf_1_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_perf_1_of_2_t { - unsigned int cntr1_lo : 7; - unsigned int cntr0 : 13; - unsigned int cntr_bank : 2; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_perf_1_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_perf_1_of_2_t f; -} sq_thread_trace_word_perf_1_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_perf_2_of_2_t { - unsigned int cntr1_hi : 6; - unsigned int cntr2 : 13; - unsigned int cntr3 : 13; -} sq_thread_trace_word_perf_2_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_perf_2_of_2_t { - unsigned int cntr3 : 13; - unsigned int cntr2 : 13; - unsigned int cntr1_hi : 6; -} sq_thread_trace_word_perf_2_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_perf_2_of_2_t f; -} sq_thread_trace_word_perf_2_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_1_of_2_t__CI { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int pipe_id : 2; - unsigned int me_id : 2; - unsigned int reg_dropped_prev : 1; - unsigned int reg_type : 3; - unsigned int : 1; - unsigned int reg_priv : 1; - unsigned int reg_op : 1; - unsigned int reg_addr : 16; -} sq_thread_trace_word_reg_1_of_2_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_1_of_2_t__CI { - unsigned int reg_addr : 16; - unsigned int reg_op : 1; - unsigned int reg_priv : 1; - unsigned int : 1; - unsigned int reg_type : 3; - unsigned int reg_dropped_prev : 1; - unsigned int me_id : 2; - unsigned int pipe_id : 2; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_reg_1_of_2_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_reg_1_of_2_t__CI f; -} sq_thread_trace_word_reg_1_of_2_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_1_of_2_t__SI { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int dispatcher : 5; - unsigned int reg_type : 3; - unsigned int : 1; - unsigned int reg_priv : 1; - unsigned int reg_op : 1; - unsigned int reg_addr : 16; -} sq_thread_trace_word_reg_1_of_2_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_1_of_2_t__SI { - unsigned int reg_addr : 16; - unsigned int reg_op : 1; - unsigned int reg_priv : 1; - unsigned int : 1; - unsigned int reg_type : 3; - unsigned int dispatcher : 5; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_reg_1_of_2_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_reg_1_of_2_t__SI f; -} sq_thread_trace_word_reg_1_of_2_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_2_of_2_t { - unsigned int data : 32; -} sq_thread_trace_word_reg_2_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_2_of_2_t { - unsigned int data : 32; -} sq_thread_trace_word_reg_2_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_reg_2_of_2_t f; -} sq_thread_trace_word_reg_2_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_cs_1_of_2_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int pipe_id : 2; - unsigned int me_id : 2; - unsigned int reg_addr : 7; - unsigned int data_lo : 16; -} sq_thread_trace_word_reg_cs_1_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_cs_1_of_2_t { - unsigned int data_lo : 16; - unsigned int reg_addr : 7; - unsigned int me_id : 2; - unsigned int pipe_id : 2; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_reg_cs_1_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_reg_cs_1_of_2_t f; -} sq_thread_trace_word_reg_cs_1_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_cs_2_of_2_t { - unsigned int data_hi : 16; - unsigned int : 16; -} sq_thread_trace_word_reg_cs_2_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_cs_2_of_2_t { - unsigned int : 16; - unsigned int data_hi : 16; -} sq_thread_trace_word_reg_cs_2_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_reg_cs_2_of_2_t f; -} sq_thread_trace_word_reg_cs_2_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_time_t__SI { - unsigned int token_type : 4; - unsigned int time_delta : 10; - unsigned int time_reset : 1; - unsigned int packet_lost : 1; - unsigned int : 16; -} sq_thread_trace_word_time_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_time_t__SI { - unsigned int : 16; - unsigned int packet_lost : 1; - unsigned int time_reset : 1; - unsigned int time_delta : 10; - unsigned int token_type : 4; -} sq_thread_trace_word_time_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_time_t__SI f; -} sq_thread_trace_word_time_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_timestamp_1_of_2_t { - unsigned int token_type : 4; - unsigned int : 12; - unsigned int time_lo : 16; -} sq_thread_trace_word_timestamp_1_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_timestamp_1_of_2_t { - unsigned int time_lo : 16; - unsigned int : 12; - unsigned int token_type : 4; -} sq_thread_trace_word_timestamp_1_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_timestamp_1_of_2_t f; -} sq_thread_trace_word_timestamp_1_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_timestamp_2_of_2_t { - unsigned int time_hi : 32; -} sq_thread_trace_word_timestamp_2_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_timestamp_2_of_2_t { - unsigned int time_hi : 32; -} sq_thread_trace_word_timestamp_2_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_timestamp_2_of_2_t f; -} sq_thread_trace_word_timestamp_2_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_wave_start_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int dispatcher : 5; - unsigned int vs_no_alloc_or_grouped : 1; - unsigned int count : 7; - unsigned int tg_id : 3; -} sq_thread_trace_word_wave_start_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_wave_start_t { - unsigned int tg_id : 3; - unsigned int count : 7; - unsigned int vs_no_alloc_or_grouped : 1; - unsigned int dispatcher : 5; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_wave_start_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_wave_start_t f; -} sq_thread_trace_word_wave_start_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_wave_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int : 16; -} sq_thread_trace_word_wave_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_wave_t { - unsigned int : 16; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_wave_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_wave_t f; -} sq_thread_trace_word_wave_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_wptr_t { - unsigned int wptr : 30; - unsigned int read_offset : 2; -} sq_thread_trace_wptr_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_wptr_t { - unsigned int read_offset : 2; - unsigned int wptr : 30; -} sq_thread_trace_wptr_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_wptr_t f; -} sq_thread_trace_wptr_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_time_hi_t { unsigned int time : 32; } sq_time_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_time_hi_t { unsigned int time : 32; } sq_time_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_time_hi_t f; -} sq_time_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_time_lo_t { unsigned int time : 32; } sq_time_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_time_lo_t { unsigned int time : 32; } sq_time_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_time_lo_t f; -} sq_time_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_exec_hi_t { unsigned int exec_hi : 32; } sq_wave_exec_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_exec_hi_t { unsigned int exec_hi : 32; } sq_wave_exec_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_exec_hi_t f; -} sq_wave_exec_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_exec_lo_t { unsigned int exec_lo : 32; } sq_wave_exec_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_exec_lo_t { unsigned int exec_lo : 32; } sq_wave_exec_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_exec_lo_t f; -} sq_wave_exec_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_gpr_alloc_t { - unsigned int vgpr_base : 6; - unsigned int : 2; - unsigned int vgpr_size : 6; - unsigned int : 2; - unsigned int sgpr_base : 6; - unsigned int : 2; - unsigned int sgpr_size : 4; - unsigned int : 4; -} sq_wave_gpr_alloc_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_gpr_alloc_t { - unsigned int : 4; - unsigned int sgpr_size : 4; - unsigned int : 2; - unsigned int sgpr_base : 6; - unsigned int : 2; - unsigned int vgpr_size : 6; - unsigned int : 2; - unsigned int vgpr_base : 6; -} sq_wave_gpr_alloc_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_gpr_alloc_t f; -} sq_wave_gpr_alloc_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_hw_id_t__CI { - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int pipe_id : 2; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int se_id : 2; - unsigned int : 1; - unsigned int tg_id : 4; - unsigned int vm_id : 4; - unsigned int queue_id : 3; - unsigned int state_id : 3; - unsigned int me_id : 2; -} sq_wave_hw_id_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_hw_id_t__CI { - unsigned int me_id : 2; - unsigned int state_id : 3; - unsigned int queue_id : 3; - unsigned int vm_id : 4; - unsigned int tg_id : 4; - unsigned int : 1; - unsigned int se_id : 2; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int pipe_id : 2; - unsigned int simd_id : 2; - unsigned int wave_id : 4; -} sq_wave_hw_id_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_hw_id_t__CI f; -} sq_wave_hw_id_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_hw_id_t__SI { - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int : 2; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int se_id : 1; - unsigned int : 2; - unsigned int tg_id : 4; - unsigned int vm_id : 4; - unsigned int ring_id : 3; - unsigned int state_id : 3; - unsigned int : 2; -} sq_wave_hw_id_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_hw_id_t__SI { - unsigned int : 2; - unsigned int state_id : 3; - unsigned int ring_id : 3; - unsigned int vm_id : 4; - unsigned int tg_id : 4; - unsigned int : 2; - unsigned int se_id : 1; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int : 2; - unsigned int simd_id : 2; - unsigned int wave_id : 4; -} sq_wave_hw_id_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_hw_id_t__SI f; -} sq_wave_hw_id_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ib_dbg0_t__SI__CI { - unsigned int ibuf_st : 3; - unsigned int pc_invalid : 1; - unsigned int need_next_dw : 1; - unsigned int no_prefetch_cnt : 3; - unsigned int ibuf_rptr : 2; - unsigned int ibuf_wptr : 2; - unsigned int : 4; - unsigned int inst_str_st : 3; - unsigned int misc_cnt : 3; - unsigned int ecc_st : 2; - unsigned int is_hyb : 1; - unsigned int hyb_cnt : 2; - unsigned int kill__CI : 1; - unsigned int need_kill_ifetch__CI : 1; - unsigned int : 3; -} sq_wave_ib_dbg0_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ib_dbg0_t__SI__CI { - unsigned int : 3; - unsigned int need_kill_ifetch__CI : 1; - unsigned int kill__CI : 1; - unsigned int hyb_cnt : 2; - unsigned int is_hyb : 1; - unsigned int ecc_st : 2; - unsigned int misc_cnt : 3; - unsigned int inst_str_st : 3; - unsigned int : 4; - unsigned int ibuf_wptr : 2; - unsigned int ibuf_rptr : 2; - unsigned int no_prefetch_cnt : 3; - unsigned int need_next_dw : 1; - unsigned int pc_invalid : 1; - unsigned int ibuf_st : 3; -} sq_wave_ib_dbg0_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ib_dbg0_t__SI__CI f; -} sq_wave_ib_dbg0_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ib_dbg0_t__VI { - unsigned int ibuf_st : 3; - unsigned int pc_invalid : 1; - unsigned int need_next_dw : 1; - unsigned int no_prefetch_cnt : 3; - unsigned int ibuf_rptr : 2; - unsigned int ibuf_wptr : 2; - unsigned int : 4; - unsigned int inst_str_st : 4; - unsigned int misc_cnt : 4; - unsigned int ecc_st : 2; - unsigned int is_hyb : 1; - unsigned int hyb_cnt : 2; - unsigned int kill : 1; - unsigned int need_kill_ifetch : 1; - unsigned int : 1; -} sq_wave_ib_dbg0_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ib_dbg0_t__VI { - unsigned int : 1; - unsigned int need_kill_ifetch : 1; - unsigned int kill : 1; - unsigned int hyb_cnt : 2; - unsigned int is_hyb : 1; - unsigned int ecc_st : 2; - unsigned int misc_cnt : 4; - unsigned int inst_str_st : 4; - unsigned int : 4; - unsigned int ibuf_wptr : 2; - unsigned int ibuf_rptr : 2; - unsigned int no_prefetch_cnt : 3; - unsigned int need_next_dw : 1; - unsigned int pc_invalid : 1; - unsigned int ibuf_st : 3; -} sq_wave_ib_dbg0_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ib_dbg0_t__VI f; -} sq_wave_ib_dbg0_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ib_sts_t__CI { - unsigned int vm_cnt : 4; - unsigned int exp_cnt : 3; - unsigned int : 1; - unsigned int lgkm_cnt : 4; - unsigned int valu_cnt : 3; - unsigned int : 17; -} sq_wave_ib_sts_t__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ib_sts_t__CI { - unsigned int : 17; - unsigned int valu_cnt : 3; - unsigned int lgkm_cnt : 4; - unsigned int : 1; - unsigned int exp_cnt : 3; - unsigned int vm_cnt : 4; -} sq_wave_ib_sts_t__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ib_sts_t__CI f; -} sq_wave_ib_sts_u__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ib_sts_t__SI { - unsigned int vm_cnt : 4; - unsigned int exp_cnt : 3; - unsigned int : 1; - unsigned int lgkm_cnt : 5; - unsigned int valu_cnt : 3; - unsigned int : 16; -} sq_wave_ib_sts_t__SI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ib_sts_t__SI { - unsigned int : 16; - unsigned int valu_cnt : 3; - unsigned int lgkm_cnt : 5; - unsigned int : 1; - unsigned int exp_cnt : 3; - unsigned int vm_cnt : 4; -} sq_wave_ib_sts_t__SI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ib_sts_t__SI f; -} sq_wave_ib_sts_u__SI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_inst_dw0_t { unsigned int inst_dw0 : 32; } sq_wave_inst_dw0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_inst_dw0_t { unsigned int inst_dw0 : 32; } sq_wave_inst_dw0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_inst_dw0_t f; -} sq_wave_inst_dw0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_inst_dw1_t { unsigned int inst_dw1 : 32; } sq_wave_inst_dw1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_inst_dw1_t { unsigned int inst_dw1 : 32; } sq_wave_inst_dw1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_inst_dw1_t f; -} sq_wave_inst_dw1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_lds_alloc_t { - unsigned int lds_base : 8; - unsigned int : 4; - unsigned int lds_size : 9; - unsigned int : 11; -} sq_wave_lds_alloc_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_lds_alloc_t { - unsigned int : 11; - unsigned int lds_size : 9; - unsigned int : 4; - unsigned int lds_base : 8; -} sq_wave_lds_alloc_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_lds_alloc_t f; -} sq_wave_lds_alloc_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_m0_t { unsigned int m0 : 32; } sq_wave_m0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_m0_t { unsigned int m0 : 32; } sq_wave_m0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_m0_t f; -} sq_wave_m0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_mode_t { - unsigned int fp_round : 4; - unsigned int fp_denorm : 4; - unsigned int dx10_clamp : 1; - unsigned int ieee : 1; - unsigned int lod_clamped : 1; - unsigned int debug_en : 1; - unsigned int excp_en : 9; - unsigned int : 6; - unsigned int gpr_idx_en__VI : 1; - unsigned int vskip : 1; - unsigned int csp : 3; -} sq_wave_mode_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_mode_t { - unsigned int csp : 3; - unsigned int vskip : 1; - unsigned int gpr_idx_en__VI : 1; - unsigned int : 6; - unsigned int excp_en : 9; - unsigned int debug_en : 1; - unsigned int lod_clamped : 1; - unsigned int ieee : 1; - unsigned int dx10_clamp : 1; - unsigned int fp_denorm : 4; - unsigned int fp_round : 4; -} sq_wave_mode_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_mode_t f; -} sq_wave_mode_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_pc_hi_t { - unsigned int pc_hi : 16; - unsigned int : 16; -} sq_wave_pc_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_pc_hi_t { - unsigned int : 16; - unsigned int pc_hi : 16; -} sq_wave_pc_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_pc_hi_t f; -} sq_wave_pc_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_pc_lo_t { unsigned int pc_lo : 32; } sq_wave_pc_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_pc_lo_t { unsigned int pc_lo : 32; } sq_wave_pc_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_pc_lo_t f; -} sq_wave_pc_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_status_t__SI__CI { - unsigned int scc : 1; - unsigned int spi_prio : 2; - unsigned int wave_prio : 2; - unsigned int priv : 1; - unsigned int trap_en : 1; - unsigned int ttrace_en : 1; - unsigned int export_rdy : 1; - unsigned int execz : 1; - unsigned int vccz : 1; - unsigned int in_tg : 1; - unsigned int in_barrier : 1; - unsigned int halt : 1; - unsigned int trap : 1; - unsigned int ttrace_cu_en : 1; - unsigned int valid : 1; - unsigned int ecc_err : 1; - unsigned int skip_export : 1; - unsigned int perf_en : 1; - unsigned int cond_dbg_user__CI : 1; - unsigned int cond_dbg_sys__CI : 1; - unsigned int data_atc__CI : 1; - unsigned int inst_atc__CI : 1; - unsigned int dispatch_cache_ctrl__CI : 3; - unsigned int must_export__CI : 1; - unsigned int : 4; -} sq_wave_status_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_status_t__SI__CI { - unsigned int : 4; - unsigned int must_export__CI : 1; - unsigned int dispatch_cache_ctrl__CI : 3; - unsigned int inst_atc__CI : 1; - unsigned int data_atc__CI : 1; - unsigned int cond_dbg_sys__CI : 1; - unsigned int cond_dbg_user__CI : 1; - unsigned int perf_en : 1; - unsigned int skip_export : 1; - unsigned int ecc_err : 1; - unsigned int valid : 1; - unsigned int ttrace_cu_en : 1; - unsigned int trap : 1; - unsigned int halt : 1; - unsigned int in_barrier : 1; - unsigned int in_tg : 1; - unsigned int vccz : 1; - unsigned int execz : 1; - unsigned int export_rdy : 1; - unsigned int ttrace_en : 1; - unsigned int trap_en : 1; - unsigned int priv : 1; - unsigned int wave_prio : 2; - unsigned int spi_prio : 2; - unsigned int scc : 1; -} sq_wave_status_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_status_t__SI__CI f; -} sq_wave_status_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_status_t__VI { - unsigned int scc : 1; - unsigned int spi_prio : 2; - unsigned int user_prio : 2; - unsigned int priv : 1; - unsigned int trap_en : 1; - unsigned int ttrace_en : 1; - unsigned int export_rdy : 1; - unsigned int execz : 1; - unsigned int vccz : 1; - unsigned int in_tg : 1; - unsigned int in_barrier : 1; - unsigned int halt : 1; - unsigned int trap : 1; - unsigned int ttrace_cu_en : 1; - unsigned int valid : 1; - unsigned int ecc_err : 1; - unsigned int skip_export : 1; - unsigned int perf_en : 1; - unsigned int cond_dbg_user : 1; - unsigned int cond_dbg_sys : 1; - unsigned int allow_replay : 1; - unsigned int inst_atc : 1; - unsigned int : 3; - unsigned int must_export : 1; - unsigned int : 4; -} sq_wave_status_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_status_t__VI { - unsigned int : 4; - unsigned int must_export : 1; - unsigned int : 3; - unsigned int inst_atc : 1; - unsigned int allow_replay : 1; - unsigned int cond_dbg_sys : 1; - unsigned int cond_dbg_user : 1; - unsigned int perf_en : 1; - unsigned int skip_export : 1; - unsigned int ecc_err : 1; - unsigned int valid : 1; - unsigned int ttrace_cu_en : 1; - unsigned int trap : 1; - unsigned int halt : 1; - unsigned int in_barrier : 1; - unsigned int in_tg : 1; - unsigned int vccz : 1; - unsigned int execz : 1; - unsigned int export_rdy : 1; - unsigned int ttrace_en : 1; - unsigned int trap_en : 1; - unsigned int priv : 1; - unsigned int user_prio : 2; - unsigned int spi_prio : 2; - unsigned int scc : 1; -} sq_wave_status_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_status_t__VI f; -} sq_wave_status_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_tba_hi_t { - unsigned int addr_hi : 8; - unsigned int : 24; -} sq_wave_tba_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_tba_hi_t { - unsigned int : 24; - unsigned int addr_hi : 8; -} sq_wave_tba_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_tba_hi_t f; -} sq_wave_tba_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_tba_lo_t { unsigned int addr_lo : 32; } sq_wave_tba_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_tba_lo_t { unsigned int addr_lo : 32; } sq_wave_tba_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_tba_lo_t f; -} sq_wave_tba_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_tma_hi_t { - unsigned int addr_hi : 8; - unsigned int : 24; -} sq_wave_tma_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_tma_hi_t { - unsigned int : 24; - unsigned int addr_hi : 8; -} sq_wave_tma_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_tma_hi_t f; -} sq_wave_tma_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_tma_lo_t { unsigned int addr_lo : 32; } sq_wave_tma_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_tma_lo_t { unsigned int addr_lo : 32; } sq_wave_tma_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_tma_lo_t f; -} sq_wave_tma_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_trapsts_t { - unsigned int excp : 9; - unsigned int : 1; - unsigned int savectx__VI : 1; - unsigned int : 5; - unsigned int excp_cycle : 6; - unsigned int : 7; - unsigned int dp_rate : 3; -} sq_wave_trapsts_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_trapsts_t { - unsigned int dp_rate : 3; - unsigned int : 7; - unsigned int excp_cycle : 6; - unsigned int : 5; - unsigned int savectx__VI : 1; - unsigned int : 1; - unsigned int excp : 9; -} sq_wave_trapsts_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_trapsts_t f; -} sq_wave_trapsts_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp0_t { unsigned int data : 32; } sq_wave_ttmp0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp0_t { unsigned int data : 32; } sq_wave_ttmp0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp0_t f; -} sq_wave_ttmp0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp10_t { unsigned int data : 32; } sq_wave_ttmp10_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp10_t { unsigned int data : 32; } sq_wave_ttmp10_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp10_t f; -} sq_wave_ttmp10_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp11_t { unsigned int data : 32; } sq_wave_ttmp11_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp11_t { unsigned int data : 32; } sq_wave_ttmp11_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp11_t f; -} sq_wave_ttmp11_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp1_t { unsigned int data : 32; } sq_wave_ttmp1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp1_t { unsigned int data : 32; } sq_wave_ttmp1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp1_t f; -} sq_wave_ttmp1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp2_t { unsigned int data : 32; } sq_wave_ttmp2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp2_t { unsigned int data : 32; } sq_wave_ttmp2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp2_t f; -} sq_wave_ttmp2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp3_t { unsigned int data : 32; } sq_wave_ttmp3_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp3_t { unsigned int data : 32; } sq_wave_ttmp3_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp3_t f; -} sq_wave_ttmp3_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp4_t { unsigned int data : 32; } sq_wave_ttmp4_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp4_t { unsigned int data : 32; } sq_wave_ttmp4_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp4_t f; -} sq_wave_ttmp4_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp5_t { unsigned int data : 32; } sq_wave_ttmp5_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp5_t { unsigned int data : 32; } sq_wave_ttmp5_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp5_t f; -} sq_wave_ttmp5_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp6_t { unsigned int data : 32; } sq_wave_ttmp6_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp6_t { unsigned int data : 32; } sq_wave_ttmp6_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp6_t f; -} sq_wave_ttmp6_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp7_t { unsigned int data : 32; } sq_wave_ttmp7_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp7_t { unsigned int data : 32; } sq_wave_ttmp7_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp7_t f; -} sq_wave_ttmp7_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp8_t { unsigned int data : 32; } sq_wave_ttmp8_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp8_t { unsigned int data : 32; } sq_wave_ttmp8_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp8_t f; -} sq_wave_ttmp8_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ttmp9_t { unsigned int data : 32; } sq_wave_ttmp9_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ttmp9_t { unsigned int data : 32; } sq_wave_ttmp9_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ttmp9_t f; -} sq_wave_ttmp9_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_caches_t__SI__CI { - unsigned int inst_invalidate : 1; - unsigned int data_invalidate : 1; - unsigned int invalidate_volatile__CI : 1; - unsigned int : 29; -} sqc_caches_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_caches_t__SI__CI { - unsigned int : 29; - unsigned int invalidate_volatile__CI : 1; - unsigned int data_invalidate : 1; - unsigned int inst_invalidate : 1; -} sqc_caches_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sqc_caches_t__SI__CI f; -} sqc_caches_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_caches_t__VI { - unsigned int target_inst : 1; - unsigned int target_data : 1; - unsigned int invalidate : 1; - unsigned int writeback : 1; - unsigned int vol : 1; - unsigned int : 11; - unsigned int complete : 1; - unsigned int : 15; -} sqc_caches_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_caches_t__VI { - unsigned int : 15; - unsigned int complete : 1; - unsigned int : 11; - unsigned int vol : 1; - unsigned int writeback : 1; - unsigned int invalidate : 1; - unsigned int target_data : 1; - unsigned int target_inst : 1; -} sqc_caches_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sqc_caches_t__VI f; -} sqc_caches_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_config_t { - unsigned int inst_cache_size : 2; - unsigned int data_cache_size : 2; - unsigned int miss_fifo_depth : 2; - unsigned int hit_fifo_depth : 1; - unsigned int force_always_miss : 1; - unsigned int force_in_order : 1; - unsigned int identity_hash_bank : 1; - unsigned int identity_hash_set : 1; - unsigned int per_vmid_inv_disable__CI__VI : 1; - unsigned int evict_lru : 2; - unsigned int force_2_bank : 1; - unsigned int force_1_bank : 1; - unsigned int ls_disable_clocks : 8; - unsigned int : 8; -} sqc_config_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_config_t { - unsigned int : 8; - unsigned int ls_disable_clocks : 8; - unsigned int force_1_bank : 1; - unsigned int force_2_bank : 1; - unsigned int evict_lru : 2; - unsigned int per_vmid_inv_disable__CI__VI : 1; - unsigned int identity_hash_set : 1; - unsigned int identity_hash_bank : 1; - unsigned int force_in_order : 1; - unsigned int force_always_miss : 1; - unsigned int hit_fifo_depth : 1; - unsigned int miss_fifo_depth : 2; - unsigned int data_cache_size : 2; - unsigned int inst_cache_size : 2; -} sqc_config_t; - -#endif -typedef union { - unsigned int val : 32; - sqc_config_t f; -} sqc_config_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_policy_t__SI__CI { - unsigned int data_l1_policy_0 : 1; - unsigned int data_l1_policy_1 : 1; - unsigned int data_l1_policy_2 : 1; - unsigned int data_l1_policy_3 : 1; - unsigned int data_l1_policy_4 : 1; - unsigned int data_l1_policy_5 : 1; - unsigned int data_l1_policy_6 : 1; - unsigned int data_l1_policy_7 : 1; - unsigned int data_l2_policy_0 : 2; - unsigned int data_l2_policy_1 : 2; - unsigned int data_l2_policy_2 : 2; - unsigned int data_l2_policy_3 : 2; - unsigned int data_l2_policy_4 : 2; - unsigned int data_l2_policy_5 : 2; - unsigned int data_l2_policy_6 : 2; - unsigned int data_l2_policy_7 : 2; - unsigned int inst_l2_policy : 2; - unsigned int : 6; -} sqc_policy_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_policy_t__SI__CI { - unsigned int : 6; - unsigned int inst_l2_policy : 2; - unsigned int data_l2_policy_7 : 2; - unsigned int data_l2_policy_6 : 2; - unsigned int data_l2_policy_5 : 2; - unsigned int data_l2_policy_4 : 2; - unsigned int data_l2_policy_3 : 2; - unsigned int data_l2_policy_2 : 2; - unsigned int data_l2_policy_1 : 2; - unsigned int data_l2_policy_0 : 2; - unsigned int data_l1_policy_7 : 1; - unsigned int data_l1_policy_6 : 1; - unsigned int data_l1_policy_5 : 1; - unsigned int data_l1_policy_4 : 1; - unsigned int data_l1_policy_3 : 1; - unsigned int data_l1_policy_2 : 1; - unsigned int data_l1_policy_1 : 1; - unsigned int data_l1_policy_0 : 1; -} sqc_policy_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sqc_policy_t__SI__CI f; -} sqc_policy_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_secded_cnt_t__SI__CI { - unsigned int inst_sec : 8; - unsigned int inst_ded : 8; - unsigned int data_sec : 8; - unsigned int data_ded : 8; -} sqc_secded_cnt_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_secded_cnt_t__SI__CI { - unsigned int data_ded : 8; - unsigned int data_sec : 8; - unsigned int inst_ded : 8; - unsigned int inst_sec : 8; -} sqc_secded_cnt_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sqc_secded_cnt_t__SI__CI f; -} sqc_secded_cnt_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_volatile_t__SI__CI { - unsigned int data_l1 : 4; - unsigned int data_l2 : 4; - unsigned int inst_l2 : 1; - unsigned int : 23; -} sqc_volatile_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_volatile_t__SI__CI { - unsigned int : 23; - unsigned int inst_l2 : 1; - unsigned int data_l2 : 4; - unsigned int data_l1 : 4; -} sqc_volatile_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sqc_volatile_t__SI__CI f; -} sqc_volatile_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _user_sqc_bank_disable_t { - unsigned int : 16; - unsigned int sqc0_bank_disable : 4; - unsigned int sqc1_bank_disable : 4; - unsigned int sqc2_bank_disable__CI__VI : 4; - unsigned int sqc3_bank_disable__CI__VI : 4; -} user_sqc_bank_disable_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _user_sqc_bank_disable_t { - unsigned int sqc3_bank_disable__CI__VI : 4; - unsigned int sqc2_bank_disable__CI__VI : 4; - unsigned int sqc1_bank_disable : 4; - unsigned int sqc0_bank_disable : 4; - unsigned int : 16; -} user_sqc_bank_disable_t; - -#endif -typedef union { - unsigned int val : 32; - user_sqc_bank_disable_t f; -} user_sqc_bank_disable_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _cc_gc_shader_rate_config_t { - unsigned int write_dis : 1; - unsigned int dpfp_rate : 2; - unsigned int sqc_balance_disable : 1; - unsigned int half_lds : 1; - unsigned int : 27; -} cc_gc_shader_rate_config_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _cc_gc_shader_rate_config_t { - unsigned int : 27; - unsigned int half_lds : 1; - unsigned int sqc_balance_disable : 1; - unsigned int dpfp_rate : 2; - unsigned int write_dis : 1; -} cc_gc_shader_rate_config_t; - -#endif -typedef union { - unsigned int val : 32; - cc_gc_shader_rate_config_t f; -} cc_gc_shader_rate_config_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _gc_user_shader_rate_config_t { - unsigned int : 1; - unsigned int dpfp_rate : 2; - unsigned int sqc_balance_disable : 1; - unsigned int half_lds : 1; - unsigned int : 27; -} gc_user_shader_rate_config_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _gc_user_shader_rate_config_t { - unsigned int : 27; - unsigned int half_lds : 1; - unsigned int sqc_balance_disable : 1; - unsigned int dpfp_rate : 2; - unsigned int : 1; -} gc_user_shader_rate_config_t; - -#endif -typedef union { - unsigned int val : 32; - gc_user_shader_rate_config_t f; -} gc_user_shader_rate_config_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_dsm_cntl_t { - unsigned int wavefront_stall_0 : 1; - unsigned int wavefront_stall_1 : 1; - unsigned int spi_backpressure_0 : 1; - unsigned int spi_backpressure_1 : 1; - unsigned int : 4; - unsigned int sel_dsm_sgpr_irritator_data0 : 1; - unsigned int sel_dsm_sgpr_irritator_data1 : 1; - unsigned int sgpr_enable_single_write : 1; - unsigned int : 5; - unsigned int sel_dsm_lds_irritator_data0 : 1; - unsigned int sel_dsm_lds_irritator_data1 : 1; - unsigned int lds_enable_single_write01 : 1; - unsigned int sel_dsm_lds_irritator_data2 : 1; - unsigned int sel_dsm_lds_irritator_data3 : 1; - unsigned int lds_enable_single_write23 : 1; - unsigned int : 2; - unsigned int sel_dsm_sp_irritator_data0 : 1; - unsigned int sel_dsm_sp_irritator_data1 : 1; - unsigned int sp_enable_single_write : 1; - unsigned int : 5; -} sq_dsm_cntl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_dsm_cntl_t { - unsigned int : 5; - unsigned int sp_enable_single_write : 1; - unsigned int sel_dsm_sp_irritator_data1 : 1; - unsigned int sel_dsm_sp_irritator_data0 : 1; - unsigned int : 2; - unsigned int lds_enable_single_write23 : 1; - unsigned int sel_dsm_lds_irritator_data3 : 1; - unsigned int sel_dsm_lds_irritator_data2 : 1; - unsigned int lds_enable_single_write01 : 1; - unsigned int sel_dsm_lds_irritator_data1 : 1; - unsigned int sel_dsm_lds_irritator_data0 : 1; - unsigned int : 5; - unsigned int sgpr_enable_single_write : 1; - unsigned int sel_dsm_sgpr_irritator_data1 : 1; - unsigned int sel_dsm_sgpr_irritator_data0 : 1; - unsigned int : 4; - unsigned int spi_backpressure_1 : 1; - unsigned int spi_backpressure_0 : 1; - unsigned int wavefront_stall_1 : 1; - unsigned int wavefront_stall_0 : 1; -} sq_dsm_cntl_t; - -#endif -typedef union { - unsigned int val : 32; - sq_dsm_cntl_t f; -} sq_dsm_cntl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_edc_ded_cnt_t { - unsigned int lds_ded : 8; - unsigned int sgpr_ded : 8; - unsigned int vgpr_ded : 8; - unsigned int : 8; -} sq_edc_ded_cnt_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_edc_ded_cnt_t { - unsigned int : 8; - unsigned int vgpr_ded : 8; - unsigned int sgpr_ded : 8; - unsigned int lds_ded : 8; -} sq_edc_ded_cnt_t; - -#endif -typedef union { - unsigned int val : 32; - sq_edc_ded_cnt_t f; -} sq_edc_ded_cnt_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_edc_info_t { - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int source : 3; - unsigned int vm_id : 4; - unsigned int : 19; -} sq_edc_info_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_edc_info_t { - unsigned int : 19; - unsigned int vm_id : 4; - unsigned int source : 3; - unsigned int simd_id : 2; - unsigned int wave_id : 4; -} sq_edc_info_t; - -#endif -typedef union { - unsigned int val : 32; - sq_edc_info_t f; -} sq_edc_info_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_edc_sec_cnt_t { - unsigned int lds_sec : 8; - unsigned int sgpr_sec : 8; - unsigned int vgpr_sec : 8; - unsigned int : 8; -} sq_edc_sec_cnt_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_edc_sec_cnt_t { - unsigned int : 8; - unsigned int vgpr_sec : 8; - unsigned int sgpr_sec : 8; - unsigned int lds_sec : 8; -} sq_edc_sec_cnt_t; - -#endif -typedef union { - unsigned int val : 32; - sq_edc_sec_cnt_t f; -} sq_edc_sec_cnt_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_auto_t { - unsigned int thread_trace : 1; - unsigned int wlt : 1; - unsigned int thread_trace_buf_full : 1; - unsigned int reg_timestamp : 1; - unsigned int cmd_timestamp : 1; - unsigned int host_cmd_overflow : 1; - unsigned int host_reg_overflow : 1; - unsigned int immed_overflow : 1; - unsigned int : 16; - unsigned int se_id : 2; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_auto_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_auto_t { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 2; - unsigned int : 16; - unsigned int immed_overflow : 1; - unsigned int host_reg_overflow : 1; - unsigned int host_cmd_overflow : 1; - unsigned int cmd_timestamp : 1; - unsigned int reg_timestamp : 1; - unsigned int thread_trace_buf_full : 1; - unsigned int wlt : 1; - unsigned int thread_trace : 1; -} sq_interrupt_word_auto_t; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_auto_t f; -} sq_interrupt_word_auto_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_cmn_t { - unsigned int : 24; - unsigned int se_id : 2; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_cmn_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_cmn_t { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 2; - unsigned int : 24; -} sq_interrupt_word_cmn_t; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_cmn_t f; -} sq_interrupt_word_cmn_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_interrupt_word_wave_t { - unsigned int data : 8; - unsigned int sh_id : 1; - unsigned int priv : 1; - unsigned int vm_id : 4; - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int cu_id : 4; - unsigned int se_id : 2; - unsigned int encoding : 2; - unsigned int : 4; -} sq_interrupt_word_wave_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_interrupt_word_wave_t { - unsigned int : 4; - unsigned int encoding : 2; - unsigned int se_id : 2; - unsigned int cu_id : 4; - unsigned int simd_id : 2; - unsigned int wave_id : 4; - unsigned int vm_id : 4; - unsigned int priv : 1; - unsigned int sh_id : 1; - unsigned int data : 8; -} sq_interrupt_word_wave_t; - -#endif -typedef union { - unsigned int val : 32; - sq_interrupt_word_wave_t f; -} sq_interrupt_word_wave_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_m0_gpr_idx_word_t { - unsigned int index : 8; - unsigned int : 4; - unsigned int vsrc0_rel : 1; - unsigned int vsrc1_rel : 1; - unsigned int vsrc2_rel : 1; - unsigned int vdst_rel : 1; - unsigned int : 16; -} sq_m0_gpr_idx_word_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_m0_gpr_idx_word_t { - unsigned int : 16; - unsigned int vdst_rel : 1; - unsigned int vsrc2_rel : 1; - unsigned int vsrc1_rel : 1; - unsigned int vsrc0_rel : 1; - unsigned int : 4; - unsigned int index : 8; -} sq_m0_gpr_idx_word_t; - -#endif -typedef union { - unsigned int val : 32; - sq_m0_gpr_idx_word_t f; -} sq_m0_gpr_idx_word_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter0_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter0_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter0_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter0_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter0_select_t f; -} sq_perfcounter0_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter10_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter10_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter10_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter10_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter10_select_t f; -} sq_perfcounter10_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter11_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter11_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter11_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter11_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter11_select_t f; -} sq_perfcounter11_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter12_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter12_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter12_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter12_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter12_select_t f; -} sq_perfcounter12_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter13_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter13_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter13_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter13_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter13_select_t f; -} sq_perfcounter13_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter14_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter14_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter14_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter14_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter14_select_t f; -} sq_perfcounter14_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter15_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter15_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter15_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter15_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter15_select_t f; -} sq_perfcounter15_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter1_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter1_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter1_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter1_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter1_select_t f; -} sq_perfcounter1_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter2_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter2_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter2_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter2_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter2_select_t f; -} sq_perfcounter2_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter3_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter3_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter3_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter3_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter3_select_t f; -} sq_perfcounter3_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter4_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter4_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter4_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter4_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter4_select_t f; -} sq_perfcounter4_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter5_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter5_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter5_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter5_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter5_select_t f; -} sq_perfcounter5_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter6_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter6_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter6_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter6_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter6_select_t f; -} sq_perfcounter6_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter7_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter7_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter7_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter7_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter7_select_t f; -} sq_perfcounter7_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter8_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter8_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter8_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter8_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter8_select_t f; -} sq_perfcounter8_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_perfcounter9_select_t { - unsigned int perf_sel : 9; - unsigned int : 3; - unsigned int sqc_bank_mask : 4; - unsigned int sqc_client_mask : 4; - unsigned int spm_mode : 4; - unsigned int simd_mask : 4; - unsigned int perf_mode : 4; -} sq_perfcounter9_select_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_perfcounter9_select_t { - unsigned int perf_mode : 4; - unsigned int simd_mask : 4; - unsigned int spm_mode : 4; - unsigned int sqc_client_mask : 4; - unsigned int sqc_bank_mask : 4; - unsigned int : 3; - unsigned int perf_sel : 9; -} sq_perfcounter9_select_t; - -#endif -typedef union { - unsigned int val : 32; - sq_perfcounter9_select_t f; -} sq_perfcounter9_select_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_misc_t { - unsigned int token_type : 4; - unsigned int time_delta : 8; - unsigned int sh_id : 1; - unsigned int misc_token_type : 3; - unsigned int : 16; -} sq_thread_trace_word_misc_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_misc_t { - unsigned int : 16; - unsigned int misc_token_type : 3; - unsigned int sh_id : 1; - unsigned int time_delta : 8; - unsigned int token_type : 4; -} sq_thread_trace_word_misc_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_misc_t f; -} sq_thread_trace_word_misc_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_1_of_2_t { - unsigned int token_type : 4; - unsigned int time_delta : 1; - unsigned int pipe_id : 2; - unsigned int me_id : 2; - unsigned int reg_dropped_prev : 1; - unsigned int reg_type : 3; - unsigned int : 1; - unsigned int reg_priv : 1; - unsigned int reg_op : 1; - unsigned int reg_addr : 16; -} sq_thread_trace_word_reg_1_of_2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_thread_trace_word_reg_1_of_2_t { - unsigned int reg_addr : 16; - unsigned int reg_op : 1; - unsigned int reg_priv : 1; - unsigned int : 1; - unsigned int reg_type : 3; - unsigned int reg_dropped_prev : 1; - unsigned int me_id : 2; - unsigned int pipe_id : 2; - unsigned int time_delta : 1; - unsigned int token_type : 4; -} sq_thread_trace_word_reg_1_of_2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_thread_trace_word_reg_1_of_2_t f; -} sq_thread_trace_word_reg_1_of_2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_hw_id_t { - unsigned int wave_id : 4; - unsigned int simd_id : 2; - unsigned int pipe_id : 2; - unsigned int cu_id : 4; - unsigned int sh_id : 1; - unsigned int se_id : 2; - unsigned int : 1; - unsigned int tg_id : 4; - unsigned int vm_id : 4; - unsigned int queue_id : 3; - unsigned int state_id : 3; - unsigned int me_id : 2; -} sq_wave_hw_id_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_hw_id_t { - unsigned int me_id : 2; - unsigned int state_id : 3; - unsigned int queue_id : 3; - unsigned int vm_id : 4; - unsigned int tg_id : 4; - unsigned int : 1; - unsigned int se_id : 2; - unsigned int sh_id : 1; - unsigned int cu_id : 4; - unsigned int pipe_id : 2; - unsigned int simd_id : 2; - unsigned int wave_id : 4; -} sq_wave_hw_id_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_hw_id_t f; -} sq_wave_hw_id_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ib_dbg1_t { - unsigned int ixnack : 1; - unsigned int xnack : 1; - unsigned int ta_need_reset : 1; - unsigned int : 1; - unsigned int xcnt : 4; - unsigned int qcnt : 4; - unsigned int : 20; -} sq_wave_ib_dbg1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ib_dbg1_t { - unsigned int : 20; - unsigned int qcnt : 4; - unsigned int xcnt : 4; - unsigned int : 1; - unsigned int ta_need_reset : 1; - unsigned int xnack : 1; - unsigned int ixnack : 1; -} sq_wave_ib_dbg1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ib_dbg1_t f; -} sq_wave_ib_dbg1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wave_ib_sts_t { - unsigned int vm_cnt : 4; - unsigned int exp_cnt : 3; - unsigned int : 1; - unsigned int lgkm_cnt : 4; - unsigned int valu_cnt : 3; - unsigned int first_replay : 1; - unsigned int rcnt : 4; - unsigned int : 12; -} sq_wave_ib_sts_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wave_ib_sts_t { - unsigned int : 12; - unsigned int rcnt : 4; - unsigned int first_replay : 1; - unsigned int valu_cnt : 3; - unsigned int lgkm_cnt : 4; - unsigned int : 1; - unsigned int exp_cnt : 3; - unsigned int vm_cnt : 4; -} sq_wave_ib_sts_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wave_ib_sts_t f; -} sq_wave_ib_sts_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wrexec_exec_hi_t { - unsigned int addr_hi : 16; - unsigned int : 10; - unsigned int first_wave : 1; - unsigned int atc : 1; - unsigned int mtype : 3; - unsigned int msb : 1; -} sq_wrexec_exec_hi_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wrexec_exec_hi_t { - unsigned int msb : 1; - unsigned int mtype : 3; - unsigned int atc : 1; - unsigned int first_wave : 1; - unsigned int : 10; - unsigned int addr_hi : 16; -} sq_wrexec_exec_hi_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wrexec_exec_hi_t f; -} sq_wrexec_exec_hi_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_wrexec_exec_lo_t { unsigned int addr_lo : 32; } sq_wrexec_exec_lo_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_wrexec_exec_lo_t { unsigned int addr_lo : 32; } sq_wrexec_exec_lo_t; - -#endif -typedef union { - unsigned int val : 32; - sq_wrexec_exec_lo_t f; -} sq_wrexec_exec_lo_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_atc_edc_gatcl1_cnt_t { - unsigned int icache_data_sec : 8; - unsigned int : 8; - unsigned int dcache_data_sec : 8; - unsigned int : 8; -} sqc_atc_edc_gatcl1_cnt_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_atc_edc_gatcl1_cnt_t { - unsigned int : 8; - unsigned int dcache_data_sec : 8; - unsigned int : 8; - unsigned int icache_data_sec : 8; -} sqc_atc_edc_gatcl1_cnt_t; - -#endif -typedef union { - unsigned int val : 32; - sqc_atc_edc_gatcl1_cnt_t f; -} sqc_atc_edc_gatcl1_cnt_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_dsm_cntl_t { - unsigned int sel_data_icache_banka : 2; - unsigned int en_single_wr_icache_banka : 1; - unsigned int sel_data_icache_bankb : 2; - unsigned int en_single_wr_icache_bankb : 1; - unsigned int sel_data_icache_bankc : 2; - unsigned int en_single_wr_icache_bankc : 1; - unsigned int sel_data_icache_bankd : 2; - unsigned int en_single_wr_icache_bankd : 1; - unsigned int sel_data_icache_gatcl1 : 2; - unsigned int en_single_wr_icache_gatcl1 : 1; - unsigned int sel_data_dcache_banka : 2; - unsigned int en_single_wr_dcache_banka : 1; - unsigned int sel_data_dcache_bankb : 2; - unsigned int en_single_wr_dcache_bankb : 1; - unsigned int sel_data_dcache_bankc : 2; - unsigned int en_single_wr_dcache_bankc : 1; - unsigned int sel_data_dcache_bankd : 2; - unsigned int en_single_wr_dcache_bankd : 1; - unsigned int sel_data_dcache_gatcl1 : 2; - unsigned int en_single_wr_dcache_gatcl1 : 1; - unsigned int : 2; -} sqc_dsm_cntl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_dsm_cntl_t { - unsigned int : 2; - unsigned int en_single_wr_dcache_gatcl1 : 1; - unsigned int sel_data_dcache_gatcl1 : 2; - unsigned int en_single_wr_dcache_bankd : 1; - unsigned int sel_data_dcache_bankd : 2; - unsigned int en_single_wr_dcache_bankc : 1; - unsigned int sel_data_dcache_bankc : 2; - unsigned int en_single_wr_dcache_bankb : 1; - unsigned int sel_data_dcache_bankb : 2; - unsigned int en_single_wr_dcache_banka : 1; - unsigned int sel_data_dcache_banka : 2; - unsigned int en_single_wr_icache_gatcl1 : 1; - unsigned int sel_data_icache_gatcl1 : 2; - unsigned int en_single_wr_icache_bankd : 1; - unsigned int sel_data_icache_bankd : 2; - unsigned int en_single_wr_icache_bankc : 1; - unsigned int sel_data_icache_bankc : 2; - unsigned int en_single_wr_icache_bankb : 1; - unsigned int sel_data_icache_bankb : 2; - unsigned int en_single_wr_icache_banka : 1; - unsigned int sel_data_icache_banka : 2; -} sqc_dsm_cntl_t; - -#endif -typedef union { - unsigned int val : 32; - sqc_dsm_cntl_t f; -} sqc_dsm_cntl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_edc_cnt_t { - unsigned int inst_sec : 8; - unsigned int inst_ded : 8; - unsigned int data_sec : 8; - unsigned int data_ded : 8; -} sqc_edc_cnt_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_edc_cnt_t { - unsigned int data_ded : 8; - unsigned int data_sec : 8; - unsigned int inst_ded : 8; - unsigned int inst_sec : 8; -} sqc_edc_cnt_t; - -#endif -typedef union { - unsigned int val : 32; - sqc_edc_cnt_t f; -} sqc_edc_cnt_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_gatcl1_cntl_t { - unsigned int reserved : 18; - unsigned int dcache_invalidate_all_vmid : 1; - unsigned int dcache_force_miss : 1; - unsigned int dcache_force_in_order : 1; - unsigned int dcache_reduce_fifo_depth_by_2 : 2; - unsigned int dcache_reduce_cache_size_by_2 : 2; - unsigned int icache_invalidate_all_vmid : 1; - unsigned int icache_force_miss : 1; - unsigned int icache_force_in_order : 1; - unsigned int icache_reduce_fifo_depth_by_2 : 2; - unsigned int icache_reduce_cache_size_by_2 : 2; -} sqc_gatcl1_cntl_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_gatcl1_cntl_t { - unsigned int icache_reduce_cache_size_by_2 : 2; - unsigned int icache_reduce_fifo_depth_by_2 : 2; - unsigned int icache_force_in_order : 1; - unsigned int icache_force_miss : 1; - unsigned int icache_invalidate_all_vmid : 1; - unsigned int dcache_reduce_cache_size_by_2 : 2; - unsigned int dcache_reduce_fifo_depth_by_2 : 2; - unsigned int dcache_force_in_order : 1; - unsigned int dcache_force_miss : 1; - unsigned int dcache_invalidate_all_vmid : 1; - unsigned int reserved : 18; -} sqc_gatcl1_cntl_t; - -#endif -typedef union { - unsigned int val : 32; - sqc_gatcl1_cntl_t f; -} sqc_gatcl1_cntl_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sqc_writeback_t { - unsigned int dwb : 1; - unsigned int dirty : 1; - unsigned int : 30; -} sqc_writeback_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sqc_writeback_t { - unsigned int : 30; - unsigned int dirty : 1; - unsigned int dwb : 1; -} sqc_writeback_t; - -#endif -typedef union { - unsigned int val : 32; - sqc_writeback_t f; -} sqc_writeback_u; - - -#endif // __VI___SI__CI_sq_reg_h diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_sq_uc_reg.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_sq_uc_reg.h deleted file mode 100644 index 2b118945bb..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_sq_uc_reg.h +++ /dev/null @@ -1,4485 +0,0 @@ -#if !defined SI_CI_VI_merged_sq_uc_reg_HEADER -#define SI_CI_VI_merged_sq_uc_reg_HEADER - - -// -// Source merge files: -// E:\MergedHeaders\SI+CI+Amur\Original\SICI/si_ci_merged_sq_uc_reg.h -// E:\MergedHeaders\SI+CI+Amur\Original\Amur/vi_sq_uc_reg.h -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -#define SQ_ATTR0 0x00000000 -#define SQ_BUFFER_ATOMIC_FCMPSWAP__SI__CI 0x0000003e -#define SQ_BUFFER_ATOMIC_FCMPSWAP_X2__SI__CI 0x0000005e -#define SQ_BUFFER_ATOMIC_FMAX__SI__CI 0x00000040 -#define SQ_BUFFER_ATOMIC_FMAX_X2__SI__CI 0x00000060 -#define SQ_BUFFER_ATOMIC_FMIN__SI__CI 0x0000003f -#define SQ_BUFFER_ATOMIC_FMIN_X2__SI__CI 0x0000005f -#define SQ_BUFFER_ATOMIC_RSUB_X2__SI 0x00000054 -#define SQ_BUFFER_ATOMIC_RSUB__SI 0x00000034 -#define SQ_BUFFER_LOAD_DWORDX3__CI 0x0000000f -#define SQ_BUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_BUFFER_STORE_BYTE 0x00000018 -#define SQ_BUFFER_STORE_DWORD 0x0000001c -#define SQ_BUFFER_STORE_DWORDX2 0x0000001d -#define SQ_BUFFER_STORE_DWORDX3__CI 0x0000001f -#define SQ_BUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_BUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_BUFFER_STORE_SHORT 0x0000001a -#define SQ_BUFFER_WBINVL1_SC__SI 0x00000070 -#define SQ_BUFFER_WBINVL1_VOL__CI 0x00000070 -#define SQ_CHAN_W 0x00000003 -#define SQ_CHAN_X 0x00000000 -#define SQ_CHAN_Y 0x00000001 -#define SQ_CHAN_Z 0x00000002 -#define SQ_CNT1 0x00000000 -#define SQ_CNT2 0x00000001 -#define SQ_CNT3 0x00000002 -#define SQ_CNT4 0x00000003 -#define SQ_DFMT_10_10_10_2__SI__CI 0x00000008 -#define SQ_DFMT_10_11_11__SI__CI 0x00000006 -#define SQ_DFMT_11_11_10__SI__CI 0x00000007 -#define SQ_DFMT_16__SI__CI 0x00000002 -#define SQ_DFMT_16_16__SI__CI 0x00000005 -#define SQ_DFMT_16_16_16_16__SI__CI 0x0000000c -#define SQ_DFMT_2_10_10_10__SI__CI 0x00000009 -#define SQ_DFMT_32__SI__CI 0x00000004 -#define SQ_DFMT_32_32__SI__CI 0x0000000b -#define SQ_DFMT_32_32_32__SI__CI 0x0000000d -#define SQ_DFMT_32_32_32_32__SI__CI 0x0000000e -#define SQ_DFMT_8__SI__CI 0x00000001 -#define SQ_DFMT_8_8__SI__CI 0x00000003 -#define SQ_DFMT_8_8_8_8__SI__CI 0x0000000a -#define SQ_DFMT_INVALID__SI__CI 0x00000000 -#define SQ_DS_0_ENCODING_MASK 0xfc000000 -#define SQ_DS_0_ENCODING_SHIFT 26 -#define SQ_DS_0_ENCODING_SIZE 6 -#define SQ_DS_0_GDS_SIZE 1 -#define SQ_DS_0_OFFSET0_MASK 0x000000ff -#define SQ_DS_0_OFFSET0_SHIFT 0x00000000 -#define SQ_DS_0_OFFSET0_SIZE 8 -#define SQ_DS_0_OFFSET1_MASK 0x0000ff00 -#define SQ_DS_0_OFFSET1_SHIFT 8 -#define SQ_DS_0_OFFSET1_SIZE 8 -#define SQ_DS_0_OP_SIZE 8 -#define SQ_DS_0_REG_SIZE 32 -#define SQ_DS_1_ADDR_MASK 0x000000ff -#define SQ_DS_1_ADDR_SHIFT 0x00000000 -#define SQ_DS_1_ADDR_SIZE 8 -#define SQ_DS_1_DATA0_MASK 0x0000ff00 -#define SQ_DS_1_DATA0_SHIFT 8 -#define SQ_DS_1_DATA0_SIZE 8 -#define SQ_DS_1_DATA1_MASK 0x00ff0000 -#define SQ_DS_1_DATA1_SHIFT 16 -#define SQ_DS_1_DATA1_SIZE 8 -#define SQ_DS_1_DEFAULT 0xcdcdcdcd -#define SQ_DS_1_REG_SIZE 32 -#define SQ_DS_1_VDST_MASK 0xff000000 -#define SQ_DS_1_VDST_SHIFT 24 -#define SQ_DS_1_VDST_SIZE 8 -#define SQ_DS_ADD_RTN_U32 0x00000020 -#define SQ_DS_ADD_RTN_U64 0x00000060 -#define SQ_DS_ADD_SRC2_U32 0x00000080 -#define SQ_DS_ADD_SRC2_U64 0x000000c0 -#define SQ_DS_ADD_U32 0x00000000 -#define SQ_DS_ADD_U64 0x00000040 -#define SQ_DS_AND_B32 0x00000009 -#define SQ_DS_AND_B64 0x00000049 -#define SQ_DS_AND_RTN_B32 0x00000029 -#define SQ_DS_AND_RTN_B64 0x00000069 -#define SQ_DS_AND_SRC2_B32 0x00000089 -#define SQ_DS_AND_SRC2_B64 0x000000c9 -#define SQ_DS_CMPST_B32 0x00000010 -#define SQ_DS_CMPST_B64 0x00000050 -#define SQ_DS_CMPST_F32 0x00000011 -#define SQ_DS_CMPST_F64 0x00000051 -#define SQ_DS_CMPST_RTN_B32 0x00000030 -#define SQ_DS_CMPST_RTN_B64 0x00000070 -#define SQ_DS_CMPST_RTN_F32 0x00000031 -#define SQ_DS_CMPST_RTN_F64 0x00000071 -#define SQ_DS_CONDXCHG32_RTN_B128__CI__VI 0x000000fd -#define SQ_DS_CONDXCHG32_RTN_B64__CI__VI 0x0000007e -#define SQ_DS_DEC_RTN_U32 0x00000024 -#define SQ_DS_DEC_RTN_U64 0x00000064 -#define SQ_DS_DEC_SRC2_U32 0x00000084 -#define SQ_DS_DEC_SRC2_U64 0x000000c4 -#define SQ_DS_DEC_U32 0x00000004 -#define SQ_DS_DEC_U64 0x00000044 -#define SQ_DS_GWS_SEMA_RELEASE_ALL__CI 0x00000018 -#define SQ_DS_INC_RTN_U32 0x00000023 -#define SQ_DS_INC_RTN_U64 0x00000063 -#define SQ_DS_INC_SRC2_U32 0x00000083 -#define SQ_DS_INC_SRC2_U64 0x000000c3 -#define SQ_DS_INC_U32 0x00000003 -#define SQ_DS_INC_U64 0x00000043 -#define SQ_DS_MAX_F32 0x00000013 -#define SQ_DS_MAX_F64 0x00000053 -#define SQ_DS_MAX_I32 0x00000006 -#define SQ_DS_MAX_I64 0x00000046 -#define SQ_DS_MAX_RTN_F32 0x00000033 -#define SQ_DS_MAX_RTN_F64 0x00000073 -#define SQ_DS_MAX_RTN_I32 0x00000026 -#define SQ_DS_MAX_RTN_I64 0x00000066 -#define SQ_DS_MAX_RTN_U32 0x00000028 -#define SQ_DS_MAX_RTN_U64 0x00000068 -#define SQ_DS_MAX_SRC2_F32 0x00000093 -#define SQ_DS_MAX_SRC2_F64 0x000000d3 -#define SQ_DS_MAX_SRC2_I32 0x00000086 -#define SQ_DS_MAX_SRC2_I64 0x000000c6 -#define SQ_DS_MAX_SRC2_U32 0x00000088 -#define SQ_DS_MAX_SRC2_U64 0x000000c8 -#define SQ_DS_MAX_U32 0x00000008 -#define SQ_DS_MAX_U64 0x00000048 -#define SQ_DS_MIN_F32 0x00000012 -#define SQ_DS_MIN_F64 0x00000052 -#define SQ_DS_MIN_I32 0x00000005 -#define SQ_DS_MIN_I64 0x00000045 -#define SQ_DS_MIN_RTN_F32 0x00000032 -#define SQ_DS_MIN_RTN_F64 0x00000072 -#define SQ_DS_MIN_RTN_I32 0x00000025 -#define SQ_DS_MIN_RTN_I64 0x00000065 -#define SQ_DS_MIN_RTN_U32 0x00000027 -#define SQ_DS_MIN_RTN_U64 0x00000067 -#define SQ_DS_MIN_SRC2_F32 0x00000092 -#define SQ_DS_MIN_SRC2_F64 0x000000d2 -#define SQ_DS_MIN_SRC2_I32 0x00000085 -#define SQ_DS_MIN_SRC2_I64 0x000000c5 -#define SQ_DS_MIN_SRC2_U32 0x00000087 -#define SQ_DS_MIN_SRC2_U64 0x000000c7 -#define SQ_DS_MIN_U32 0x00000007 -#define SQ_DS_MIN_U64 0x00000047 -#define SQ_DS_MSKOR_B32 0x0000000c -#define SQ_DS_MSKOR_B64 0x0000004c -#define SQ_DS_MSKOR_RTN_B32 0x0000002c -#define SQ_DS_MSKOR_RTN_B64 0x0000006c -#define SQ_DS_NOP__CI__VI 0x00000014 -#define SQ_DS_OR_B32 0x0000000a -#define SQ_DS_OR_B64 0x0000004a -#define SQ_DS_OR_RTN_B32 0x0000002a -#define SQ_DS_OR_RTN_B64 0x0000006a -#define SQ_DS_OR_SRC2_B32 0x0000008a -#define SQ_DS_OR_SRC2_B64 0x000000ca -#define SQ_DS_READ2ST64_B32 0x00000038 -#define SQ_DS_READ2ST64_B64 0x00000078 -#define SQ_DS_READ2_B32 0x00000037 -#define SQ_DS_READ2_B64 0x00000077 -#define SQ_DS_READ_B128__CI__VI 0x000000ff -#define SQ_DS_READ_B32 0x00000036 -#define SQ_DS_READ_B64 0x00000076 -#define SQ_DS_READ_B96__CI__VI 0x000000fe -#define SQ_DS_READ_I16 0x0000003b -#define SQ_DS_READ_I8 0x00000039 -#define SQ_DS_READ_U16 0x0000003c -#define SQ_DS_READ_U8 0x0000003a -#define SQ_DS_RSUB_RTN_U32 0x00000022 -#define SQ_DS_RSUB_RTN_U64 0x00000062 -#define SQ_DS_RSUB_SRC2_U32 0x00000082 -#define SQ_DS_RSUB_SRC2_U64 0x000000c2 -#define SQ_DS_RSUB_U32 0x00000002 -#define SQ_DS_RSUB_U64 0x00000042 -#define SQ_DS_SUB_RTN_U32 0x00000021 -#define SQ_DS_SUB_RTN_U64 0x00000061 -#define SQ_DS_SUB_SRC2_U32 0x00000081 -#define SQ_DS_SUB_SRC2_U64 0x000000c1 -#define SQ_DS_SUB_U32 0x00000001 -#define SQ_DS_SUB_U64 0x00000041 -#define SQ_DS_WRAP_RTN_B32__CI__VI 0x00000034 -#define SQ_DS_WRITE2ST64_B32 0x0000000f -#define SQ_DS_WRITE2ST64_B64 0x0000004f -#define SQ_DS_WRITE2_B32 0x0000000e -#define SQ_DS_WRITE2_B64 0x0000004e -#define SQ_DS_WRITE_B128__CI__VI 0x000000df -#define SQ_DS_WRITE_B16 0x0000001f -#define SQ_DS_WRITE_B32 0x0000000d -#define SQ_DS_WRITE_B64 0x0000004d -#define SQ_DS_WRITE_B8 0x0000001e -#define SQ_DS_WRITE_B96__CI__VI 0x000000de -#define SQ_DS_WRITE_SRC2_B32 0x0000008d -#define SQ_DS_WRITE_SRC2_B64 0x000000cd -#define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f -#define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f -#define SQ_DS_WRXCHG2_RTN_B32 0x0000002e -#define SQ_DS_WRXCHG2_RTN_B64 0x0000006e -#define SQ_DS_WRXCHG_RTN_B32 0x0000002d -#define SQ_DS_WRXCHG_RTN_B64 0x0000006d -#define SQ_DS_XOR_B32 0x0000000b -#define SQ_DS_XOR_B64 0x0000004b -#define SQ_DS_XOR_RTN_B32 0x0000002b -#define SQ_DS_XOR_RTN_B64 0x0000006b -#define SQ_DS_XOR_SRC2_B32 0x0000008b -#define SQ_DS_XOR_SRC2_B64 0x000000cb -#define SQ_ENC_DS_BITS 0xd8000000 -#define SQ_ENC_DS_FIELD 0x00000036 -#define SQ_ENC_DS_MASK 0xfc000000 -#define SQ_ENC_EXP_MASK 0xfc000000 -#define SQ_ENC_FLAT_BITS__CI__VI 0xdc000000 -#define SQ_ENC_FLAT_FIELD__CI__VI 0x00000037 -#define SQ_ENC_FLAT_MASK__CI__VI 0xfc000000 -#define SQ_ENC_MIMG_BITS 0xf0000000 -#define SQ_ENC_MIMG_FIELD 0x0000003c -#define SQ_ENC_MIMG_MASK 0xfc000000 -#define SQ_ENC_MTBUF_BITS 0xe8000000 -#define SQ_ENC_MTBUF_FIELD 0x0000003a -#define SQ_ENC_MTBUF_MASK 0xfc000000 -#define SQ_ENC_MUBUF_BITS 0xe0000000 -#define SQ_ENC_MUBUF_FIELD 0x00000038 -#define SQ_ENC_MUBUF_MASK 0xfc000000 -#define SQ_ENC_SMRD_BITS__SI__CI 0xc0000000 -#define SQ_ENC_SMRD_FIELD__SI__CI 0x00000018 -#define SQ_ENC_SMRD_MASK__SI__CI 0xf8000000 -#define SQ_ENC_SOP1_BITS 0xbe800000 -#define SQ_ENC_SOP1_FIELD 0x0000017d -#define SQ_ENC_SOP1_MASK 0xff800000 -#define SQ_ENC_SOP2_BITS 0x80000000 -#define SQ_ENC_SOP2_FIELD 0x00000002 -#define SQ_ENC_SOP2_MASK 0xc0000000 -#define SQ_ENC_SOPC_BITS 0xbf000000 -#define SQ_ENC_SOPC_FIELD 0x0000017e -#define SQ_ENC_SOPC_MASK 0xff800000 -#define SQ_ENC_SOPK_BITS 0xb0000000 -#define SQ_ENC_SOPK_FIELD 0x0000000b -#define SQ_ENC_SOPK_MASK 0xf0000000 -#define SQ_ENC_SOPP_BITS 0xbf800000 -#define SQ_ENC_SOPP_FIELD 0x0000017f -#define SQ_ENC_SOPP_MASK 0xff800000 -#define SQ_ENC_VINTRP_MASK 0xfc000000 -#define SQ_ENC_VOP1_BITS 0x7e000000 -#define SQ_ENC_VOP1_FIELD 0x0000003f -#define SQ_ENC_VOP1_MASK 0xfe000000 -#define SQ_ENC_VOP2_BITS 0x00000000 -#define SQ_ENC_VOP2_FIELD 0x00000000 -#define SQ_ENC_VOP2_MASK 0x80000000 -#define SQ_ENC_VOP3_BITS 0xd0000000 -#define SQ_ENC_VOP3_FIELD 0x00000034 -#define SQ_ENC_VOP3_MASK 0xfc000000 -#define SQ_ENC_VOPC_BITS 0x7c000000 -#define SQ_ENC_VOPC_FIELD 0x0000003e -#define SQ_ENC_VOPC_MASK 0xfe000000 -#define SQ_EQ 0x00000002 -#define SQ_EXEC_HI 0x0000007f -#define SQ_EXEC_LO 0x0000007e -#define SQ_EXP 0x00000000 -#define SQ_EXP_0_COMPR_MASK 0x00000400 -#define SQ_EXP_0_COMPR_SHIFT 10 -#define SQ_EXP_0_COMPR_SIZE 1 -#define SQ_EXP_0_DEFAULT 0xcc000dcd -#define SQ_EXP_0_DONE_MASK 0x00000800 -#define SQ_EXP_0_DONE_SHIFT 11 -#define SQ_EXP_0_DONE_SIZE 1 -#define SQ_EXP_0_ENCODING_MASK 0xfc000000 -#define SQ_EXP_0_ENCODING_SHIFT 26 -#define SQ_EXP_0_ENCODING_SIZE 6 -#define SQ_EXP_0_EN_MASK 0x0000000f -#define SQ_EXP_0_EN_SHIFT 0x00000000 -#define SQ_EXP_0_EN_SIZE 4 -#define SQ_EXP_0_REG_SIZE 32 -#define SQ_EXP_0_TGT_MASK 0x000003f0 -#define SQ_EXP_0_TGT_SHIFT 4 -#define SQ_EXP_0_TGT_SIZE 6 -#define SQ_EXP_0_VM_MASK 0x00001000 -#define SQ_EXP_0_VM_SHIFT 12 -#define SQ_EXP_0_VM_SIZE 1 -#define SQ_EXP_1_DEFAULT 0xcdcdcdcd -#define SQ_EXP_1_REG_SIZE 32 -#define SQ_EXP_1_VSRC0_MASK 0x000000ff -#define SQ_EXP_1_VSRC0_SHIFT 0x00000000 -#define SQ_EXP_1_VSRC0_SIZE 8 -#define SQ_EXP_1_VSRC1_MASK 0x0000ff00 -#define SQ_EXP_1_VSRC1_SHIFT 8 -#define SQ_EXP_1_VSRC1_SIZE 8 -#define SQ_EXP_1_VSRC2_MASK 0x00ff0000 -#define SQ_EXP_1_VSRC2_SHIFT 16 -#define SQ_EXP_1_VSRC2_SIZE 8 -#define SQ_EXP_1_VSRC3_MASK 0xff000000 -#define SQ_EXP_1_VSRC3_SHIFT 24 -#define SQ_EXP_1_VSRC3_SIZE 8 -#define SQ_EXP_GDS0 0x00000018 -#define SQ_EXP_MRT0 0x00000000 -#define SQ_EXP_MRTZ 0x00000008 -#define SQ_EXP_NULL 0x00000009 -#define SQ_EXP_NUM_GDS 0x00000005 -#define SQ_EXP_NUM_MRT 0x00000008 -#define SQ_EXP_NUM_PARAM 0x00000020 -#define SQ_EXP_NUM_POS 0x00000004 -#define SQ_EXP_PARAM0 0x00000020 -#define SQ_EXP_POS0 0x0000000c -#define SQ_F 0x00000000 -#define SQ_FLAT_0_DEFAULT__CI__VI 0xcdcd0000 -#define SQ_FLAT_0_ENCODING_MASK__CI__VI 0xfc000000 -#define SQ_FLAT_0_ENCODING_SHIFT__CI__VI 26 -#define SQ_FLAT_0_ENCODING_SIZE__CI__VI 6 -#define SQ_FLAT_0_GLC_MASK__CI__VI 0x00010000 -#define SQ_FLAT_0_GLC_SHIFT__CI__VI 16 -#define SQ_FLAT_0_GLC_SIZE__CI__VI 1 -#define SQ_FLAT_0_OP_MASK__CI__VI 0x01fc0000 -#define SQ_FLAT_0_OP_SHIFT__CI__VI 18 -#define SQ_FLAT_0_OP_SIZE__CI__VI 7 -#define SQ_FLAT_0_REG_SIZE__CI__VI 32 -#define SQ_FLAT_0_SLC_MASK__CI__VI 0x00020000 -#define SQ_FLAT_0_SLC_SHIFT__CI__VI 17 -#define SQ_FLAT_0_SLC_SIZE__CI__VI 1 -#define SQ_FLAT_1_ADDR_MASK__CI__VI 0x000000ff -#define SQ_FLAT_1_ADDR_SHIFT__CI__VI 0x00000000 -#define SQ_FLAT_1_ADDR_SIZE__CI__VI 8 -#define SQ_FLAT_1_DATA_MASK__CI__VI 0x0000ff00 -#define SQ_FLAT_1_DATA_SHIFT__CI__VI 8 -#define SQ_FLAT_1_DATA_SIZE__CI__VI 8 -#define SQ_FLAT_1_DEFAULT__CI__VI 0xcd80cdcd -#define SQ_FLAT_1_REG_SIZE__CI__VI 32 -#define SQ_FLAT_1_TFE_MASK__CI__VI 0x00800000 -#define SQ_FLAT_1_TFE_SHIFT__CI__VI 23 -#define SQ_FLAT_1_TFE_SIZE__CI__VI 1 -#define SQ_FLAT_1_VDST_MASK__CI__VI 0xff000000 -#define SQ_FLAT_1_VDST_SHIFT__CI__VI 24 -#define SQ_FLAT_1_VDST_SIZE__CI__VI 8 -#define SQ_FLAT_ATOMIC_ADD_X2__CI 0x00000052 -#define SQ_FLAT_ATOMIC_ADD__CI 0x00000032 -#define SQ_FLAT_ATOMIC_AND_X2__CI 0x00000059 -#define SQ_FLAT_ATOMIC_AND__CI 0x00000039 -#define SQ_FLAT_ATOMIC_CMPSWAP_X2__CI 0x00000051 -#define SQ_FLAT_ATOMIC_CMPSWAP__CI 0x00000031 -#define SQ_FLAT_ATOMIC_DEC_X2__CI 0x0000005d -#define SQ_FLAT_ATOMIC_DEC__CI 0x0000003d -#define SQ_FLAT_ATOMIC_FCMPSWAP_X2__CI 0x0000005e -#define SQ_FLAT_ATOMIC_FCMPSWAP__CI 0x0000003e -#define SQ_FLAT_ATOMIC_FMAX_X2__CI 0x00000060 -#define SQ_FLAT_ATOMIC_FMAX__CI 0x00000040 -#define SQ_FLAT_ATOMIC_FMIN_X2__CI 0x0000005f -#define SQ_FLAT_ATOMIC_FMIN__CI 0x0000003f -#define SQ_FLAT_ATOMIC_INC_X2__CI 0x0000005c -#define SQ_FLAT_ATOMIC_INC__CI 0x0000003c -#define SQ_FLAT_ATOMIC_OR_X2__CI 0x0000005a -#define SQ_FLAT_ATOMIC_OR__CI 0x0000003a -#define SQ_FLAT_ATOMIC_SMAX_X2__CI 0x00000057 -#define SQ_FLAT_ATOMIC_SMAX__CI 0x00000037 -#define SQ_FLAT_ATOMIC_SMIN_X2__CI 0x00000055 -#define SQ_FLAT_ATOMIC_SMIN__CI 0x00000035 -#define SQ_FLAT_ATOMIC_SUB_X2__CI 0x00000053 -#define SQ_FLAT_ATOMIC_SUB__CI 0x00000033 -#define SQ_FLAT_ATOMIC_SWAP_X2__CI 0x00000050 -#define SQ_FLAT_ATOMIC_SWAP__CI 0x00000030 -#define SQ_FLAT_ATOMIC_UMAX_X2__CI 0x00000058 -#define SQ_FLAT_ATOMIC_UMAX__CI 0x00000038 -#define SQ_FLAT_ATOMIC_UMIN_X2__CI 0x00000056 -#define SQ_FLAT_ATOMIC_UMIN__CI 0x00000036 -#define SQ_FLAT_ATOMIC_XOR_X2__CI 0x0000005b -#define SQ_FLAT_ATOMIC_XOR__CI 0x0000003b -#define SQ_FLAT_LOAD_DWORDX2__CI 0x0000000d -#define SQ_FLAT_LOAD_DWORDX3__CI 0x0000000f -#define SQ_FLAT_LOAD_DWORDX4__CI 0x0000000e -#define SQ_FLAT_LOAD_DWORD__CI 0x0000000c -#define SQ_FLAT_LOAD_SBYTE__CI 0x00000009 -#define SQ_FLAT_LOAD_SSHORT__CI 0x0000000b -#define SQ_FLAT_LOAD_UBYTE__CI 0x00000008 -#define SQ_FLAT_LOAD_USHORT__CI 0x0000000a -#define SQ_FLAT_SCRATCH_HI__CI 0x00000069 -#define SQ_FLAT_SCRATCH_LO__CI 0x00000068 -#define SQ_FLAT_STORE_BYTE__CI__VI 0x00000018 -#define SQ_FLAT_STORE_DWORDX2__CI__VI 0x0000001d -#define SQ_FLAT_STORE_DWORDX3__CI 0x0000001f -#define SQ_FLAT_STORE_DWORDX4__CI 0x0000001e -#define SQ_FLAT_STORE_DWORD__CI__VI 0x0000001c -#define SQ_FLAT_STORE_SHORT__CI__VI 0x0000001a -#define SQ_GE 0x00000006 -#define SQ_GS_OP_CUT 0x00000001 -#define SQ_GS_OP_EMIT 0x00000002 -#define SQ_GS_OP_EMIT_CUT 0x00000003 -#define SQ_GS_OP_NOP 0x00000000 -#define SQ_GT 0x00000004 -#define SQ_HWREG_ID_SHIFT 0x00000000 -#define SQ_HWREG_ID_SIZE 0x00000006 -#define SQ_HWREG_OFFSET_SHIFT 0x00000006 -#define SQ_HWREG_OFFSET_SIZE 0x00000005 -#define SQ_HWREG_SIZE_SHIFT 0x0000000b -#define SQ_HWREG_SIZE_SIZE 0x00000005 -#define SQ_HW_REG_GPR_ALLOC 0x00000005 -#define SQ_HW_REG_HW_ID 0x00000004 -#define SQ_HW_REG_IB_DBG0 0x0000000c -#define SQ_HW_REG_IB_STS 0x00000007 -#define SQ_HW_REG_INST_DW0 0x0000000a -#define SQ_HW_REG_INST_DW1 0x0000000b -#define SQ_HW_REG_LDS_ALLOC 0x00000006 -#define SQ_HW_REG_MODE 0x00000001 -#define SQ_HW_REG_PC_HI 0x00000009 -#define SQ_HW_REG_PC_LO 0x00000008 -#define SQ_HW_REG_STATUS 0x00000002 -#define SQ_HW_REG_TRAPSTS 0x00000003 -#define SQ_IMAGE_ATOMIC_AND 0x00000018 -#define SQ_IMAGE_ATOMIC_DEC 0x0000001c -#define SQ_IMAGE_ATOMIC_FCMPSWAP__SI__CI 0x0000001d -#define SQ_IMAGE_ATOMIC_FMAX__SI__CI 0x0000001f -#define SQ_IMAGE_ATOMIC_FMIN__SI__CI 0x0000001e -#define SQ_IMAGE_ATOMIC_INC 0x0000001b -#define SQ_IMAGE_ATOMIC_OR 0x00000019 -#define SQ_IMAGE_ATOMIC_RSUB__SI 0x00000013 -#define SQ_IMAGE_ATOMIC_SMAX 0x00000016 -#define SQ_IMAGE_ATOMIC_SMIN 0x00000014 -#define SQ_IMAGE_ATOMIC_UMAX 0x00000017 -#define SQ_IMAGE_ATOMIC_UMIN 0x00000015 -#define SQ_IMAGE_ATOMIC_XOR 0x0000001a -#define SQ_IMAGE_GATHER4 0x00000040 -#define SQ_IMAGE_GATHER4_B 0x00000045 -#define SQ_IMAGE_GATHER4_B_CL 0x00000046 -#define SQ_IMAGE_GATHER4_B_CL_O 0x00000056 -#define SQ_IMAGE_GATHER4_B_O 0x00000055 -#define SQ_IMAGE_GATHER4_C 0x00000048 -#define SQ_IMAGE_GATHER4_CL 0x00000041 -#define SQ_IMAGE_GATHER4_CL_O 0x00000051 -#define SQ_IMAGE_GATHER4_C_B 0x0000004d -#define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e -#define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e -#define SQ_IMAGE_GATHER4_C_B_O 0x0000005d -#define SQ_IMAGE_GATHER4_C_CL 0x00000049 -#define SQ_IMAGE_GATHER4_C_CL_O 0x00000059 -#define SQ_IMAGE_GATHER4_C_L 0x0000004c -#define SQ_IMAGE_GATHER4_C_LZ 0x0000004f -#define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f -#define SQ_IMAGE_GATHER4_C_L_O 0x0000005c -#define SQ_IMAGE_GATHER4_C_O 0x00000058 -#define SQ_IMAGE_GATHER4_L 0x00000044 -#define SQ_IMAGE_GATHER4_LZ 0x00000047 -#define SQ_IMAGE_GATHER4_LZ_O 0x00000057 -#define SQ_IMAGE_GATHER4_L_O 0x00000054 -#define SQ_IMAGE_GATHER4_O 0x00000050 -#define SQ_IMAGE_GET_LOD 0x00000060 -#define SQ_IMAGE_GET_RESINFO 0x0000000e -#define SQ_IMAGE_LOAD 0x00000000 -#define SQ_IMAGE_LOAD_MIP 0x00000001 -#define SQ_IMAGE_LOAD_MIP_PCK 0x00000004 -#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005 -#define SQ_IMAGE_LOAD_PCK 0x00000002 -#define SQ_IMAGE_LOAD_PCK_SGN 0x00000003 -#define SQ_IMAGE_RSRC256 0x0000007e -#define SQ_IMAGE_SAMPLE 0x00000020 -#define SQ_IMAGE_SAMPLER 0x0000007f -#define SQ_IMAGE_SAMPLE_B 0x00000025 -#define SQ_IMAGE_SAMPLE_B_CL 0x00000026 -#define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036 -#define SQ_IMAGE_SAMPLE_B_O 0x00000035 -#define SQ_IMAGE_SAMPLE_C 0x00000028 -#define SQ_IMAGE_SAMPLE_CD 0x00000068 -#define SQ_IMAGE_SAMPLE_CD_CL 0x00000069 -#define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d -#define SQ_IMAGE_SAMPLE_CD_O 0x0000006c -#define SQ_IMAGE_SAMPLE_CL 0x00000021 -#define SQ_IMAGE_SAMPLE_CL_O 0x00000031 -#define SQ_IMAGE_SAMPLE_C_B 0x0000002d -#define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e -#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e -#define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d -#define SQ_IMAGE_SAMPLE_C_CD 0x0000006a -#define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b -#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f -#define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e -#define SQ_IMAGE_SAMPLE_C_CL 0x00000029 -#define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039 -#define SQ_IMAGE_SAMPLE_C_D 0x0000002a -#define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b -#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b -#define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a -#define SQ_IMAGE_SAMPLE_C_L 0x0000002c -#define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f -#define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f -#define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c -#define SQ_IMAGE_SAMPLE_C_O 0x00000038 -#define SQ_IMAGE_SAMPLE_D 0x00000022 -#define SQ_IMAGE_SAMPLE_D_CL 0x00000023 -#define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033 -#define SQ_IMAGE_SAMPLE_D_O 0x00000032 -#define SQ_IMAGE_SAMPLE_L 0x00000024 -#define SQ_IMAGE_SAMPLE_LZ 0x00000027 -#define SQ_IMAGE_SAMPLE_LZ_O 0x00000037 -#define SQ_IMAGE_SAMPLE_L_O 0x00000034 -#define SQ_IMAGE_SAMPLE_O 0x00000030 -#define SQ_IMAGE_STORE 0x00000008 -#define SQ_IMAGE_STORE_MIP 0x00000009 -#define SQ_IMAGE_STORE_MIP_PCK 0x0000000b -#define SQ_IMAGE_STORE_PCK 0x0000000a -#define SQ_INST_DEFAULT 0xcdcdcdcd -#define SQ_INST_ENCODING_MASK 0xffffffff -#define SQ_INST_ENCODING_SHIFT 0x00000000 -#define SQ_INST_ENCODING_SIZE 32 -#define SQ_INST_REG_SIZE 32 -#define SQ_LE 0x00000003 -#define SQ_LG 0x00000005 -#define SQ_LT 0x00000001 -#define SQ_M0 0x0000007c -#define SQ_MIMG_0_DA_MASK 0x00004000 -#define SQ_MIMG_0_DA_SHIFT 14 -#define SQ_MIMG_0_DA_SIZE 1 -#define SQ_MIMG_0_DEFAULT 0xcdcdcd00 -#define SQ_MIMG_0_DMASK_MASK 0x00000f00 -#define SQ_MIMG_0_DMASK_SHIFT 8 -#define SQ_MIMG_0_DMASK_SIZE 4 -#define SQ_MIMG_0_ENCODING_MASK 0xfc000000 -#define SQ_MIMG_0_ENCODING_SHIFT 26 -#define SQ_MIMG_0_ENCODING_SIZE 6 -#define SQ_MIMG_0_GLC_MASK 0x00002000 -#define SQ_MIMG_0_GLC_SHIFT 13 -#define SQ_MIMG_0_GLC_SIZE 1 -#define SQ_MIMG_0_LWE_MASK 0x00020000 -#define SQ_MIMG_0_LWE_SHIFT 17 -#define SQ_MIMG_0_LWE_SIZE 1 -#define SQ_MIMG_0_OP_MASK 0x01fc0000 -#define SQ_MIMG_0_OP_SHIFT 18 -#define SQ_MIMG_0_OP_SIZE 7 -#define SQ_MIMG_0_R128_MASK 0x00008000 -#define SQ_MIMG_0_R128_SHIFT 15 -#define SQ_MIMG_0_R128_SIZE 1 -#define SQ_MIMG_0_REG_SIZE 32 -#define SQ_MIMG_0_SLC_MASK 0x02000000 -#define SQ_MIMG_0_SLC_SHIFT 25 -#define SQ_MIMG_0_SLC_SIZE 1 -#define SQ_MIMG_0_TFE_MASK 0x00010000 -#define SQ_MIMG_0_TFE_SHIFT 16 -#define SQ_MIMG_0_TFE_SIZE 1 -#define SQ_MIMG_0_UNORM_MASK 0x00001000 -#define SQ_MIMG_0_UNORM_SHIFT 12 -#define SQ_MIMG_0_UNORM_SIZE 1 -#define SQ_MIMG_1_REG_SIZE 32 -#define SQ_MIMG_1_SRSRC_MASK 0x001f0000 -#define SQ_MIMG_1_SRSRC_SHIFT 16 -#define SQ_MIMG_1_SRSRC_SIZE 5 -#define SQ_MIMG_1_SSAMP_MASK 0x03e00000 -#define SQ_MIMG_1_SSAMP_SHIFT 21 -#define SQ_MIMG_1_SSAMP_SIZE 5 -#define SQ_MIMG_1_VADDR_MASK 0x000000ff -#define SQ_MIMG_1_VADDR_SHIFT 0x00000000 -#define SQ_MIMG_1_VADDR_SIZE 8 -#define SQ_MIMG_1_VDATA_MASK 0x0000ff00 -#define SQ_MIMG_1_VDATA_SHIFT 8 -#define SQ_MIMG_1_VDATA_SIZE 8 -#define SQ_MSG_GS 0x00000002 -#define SQ_MSG_GS_DONE 0x00000003 -#define SQ_MSG_INTERRUPT 0x00000001 -#define SQ_MSG_SYSMSG 0x0000000f -#define SQ_MTBUF_0_ADDR64_MASK__SI__CI 0x00008000 -#define SQ_MTBUF_0_ADDR64_SHIFT__SI__CI 15 -#define SQ_MTBUF_0_ADDR64_SIZE__SI__CI 1 -#define SQ_MTBUF_0_DEFAULT 0xcdcdcdcd -#define SQ_MTBUF_0_DFMT_MASK 0x00780000 -#define SQ_MTBUF_0_DFMT_SHIFT 19 -#define SQ_MTBUF_0_DFMT_SIZE 4 -#define SQ_MTBUF_0_ENCODING_MASK 0xfc000000 -#define SQ_MTBUF_0_ENCODING_SHIFT 26 -#define SQ_MTBUF_0_ENCODING_SIZE 6 -#define SQ_MTBUF_0_GLC_MASK 0x00004000 -#define SQ_MTBUF_0_GLC_SHIFT 14 -#define SQ_MTBUF_0_GLC_SIZE 1 -#define SQ_MTBUF_0_IDXEN_MASK 0x00002000 -#define SQ_MTBUF_0_IDXEN_SHIFT 13 -#define SQ_MTBUF_0_IDXEN_SIZE 1 -#define SQ_MTBUF_0_NFMT_MASK 0x03800000 -#define SQ_MTBUF_0_NFMT_SHIFT 23 -#define SQ_MTBUF_0_NFMT_SIZE 3 -#define SQ_MTBUF_0_OFFEN_MASK 0x00001000 -#define SQ_MTBUF_0_OFFEN_SHIFT 12 -#define SQ_MTBUF_0_OFFEN_SIZE 1 -#define SQ_MTBUF_0_OFFSET_MASK 0x00000fff -#define SQ_MTBUF_0_OFFSET_SHIFT 0x00000000 -#define SQ_MTBUF_0_OFFSET_SIZE 12 -#define SQ_MTBUF_0_REG_SIZE 32 -#define SQ_MTBUF_1_DEFAULT 0xcdcdcdcd -#define SQ_MTBUF_1_REG_SIZE 32 -#define SQ_MTBUF_1_SLC_MASK 0x00400000 -#define SQ_MTBUF_1_SLC_SHIFT 22 -#define SQ_MTBUF_1_SLC_SIZE 1 -#define SQ_MTBUF_1_SOFFSET_MASK 0xff000000 -#define SQ_MTBUF_1_SOFFSET_SHIFT 24 -#define SQ_MTBUF_1_SOFFSET_SIZE 8 -#define SQ_MTBUF_1_SRSRC_MASK 0x001f0000 -#define SQ_MTBUF_1_SRSRC_SHIFT 16 -#define SQ_MTBUF_1_SRSRC_SIZE 5 -#define SQ_MTBUF_1_TFE_MASK 0x00800000 -#define SQ_MTBUF_1_TFE_SHIFT 23 -#define SQ_MTBUF_1_TFE_SIZE 1 -#define SQ_MTBUF_1_VADDR_MASK 0x000000ff -#define SQ_MTBUF_1_VADDR_SHIFT 0x00000000 -#define SQ_MTBUF_1_VADDR_SIZE 8 -#define SQ_MTBUF_1_VDATA_MASK 0x0000ff00 -#define SQ_MTBUF_1_VDATA_SHIFT 8 -#define SQ_MTBUF_1_VDATA_SIZE 8 -#define SQ_MUBUF_0_ADDR64_MASK__SI__CI 0x00008000 -#define SQ_MUBUF_0_ADDR64_SHIFT__SI__CI 15 -#define SQ_MUBUF_0_ADDR64_SIZE__SI__CI 1 -#define SQ_MUBUF_0_ENCODING_MASK 0xfc000000 -#define SQ_MUBUF_0_ENCODING_SHIFT 26 -#define SQ_MUBUF_0_ENCODING_SIZE 6 -#define SQ_MUBUF_0_GLC_MASK 0x00004000 -#define SQ_MUBUF_0_GLC_SHIFT 14 -#define SQ_MUBUF_0_GLC_SIZE 1 -#define SQ_MUBUF_0_IDXEN_MASK 0x00002000 -#define SQ_MUBUF_0_IDXEN_SHIFT 13 -#define SQ_MUBUF_0_IDXEN_SIZE 1 -#define SQ_MUBUF_0_LDS_MASK 0x00010000 -#define SQ_MUBUF_0_LDS_SHIFT 16 -#define SQ_MUBUF_0_LDS_SIZE 1 -#define SQ_MUBUF_0_OFFEN_MASK 0x00001000 -#define SQ_MUBUF_0_OFFEN_SHIFT 12 -#define SQ_MUBUF_0_OFFEN_SIZE 1 -#define SQ_MUBUF_0_OFFSET_MASK 0x00000fff -#define SQ_MUBUF_0_OFFSET_SHIFT 0x00000000 -#define SQ_MUBUF_0_OFFSET_SIZE 12 -#define SQ_MUBUF_0_OP_MASK 0x01fc0000 -#define SQ_MUBUF_0_OP_SHIFT 18 -#define SQ_MUBUF_0_OP_SIZE 7 -#define SQ_MUBUF_0_REG_SIZE 32 -#define SQ_MUBUF_1_REG_SIZE 32 -#define SQ_MUBUF_1_SLC_MASK__SI__CI 0x00400000 -#define SQ_MUBUF_1_SLC_SHIFT__SI__CI 22 -#define SQ_MUBUF_1_SLC_SIZE__SI__CI 1 -#define SQ_MUBUF_1_SOFFSET_MASK 0xff000000 -#define SQ_MUBUF_1_SOFFSET_SHIFT 24 -#define SQ_MUBUF_1_SOFFSET_SIZE 8 -#define SQ_MUBUF_1_SRSRC_MASK 0x001f0000 -#define SQ_MUBUF_1_SRSRC_SHIFT 16 -#define SQ_MUBUF_1_SRSRC_SIZE 5 -#define SQ_MUBUF_1_TFE_MASK 0x00800000 -#define SQ_MUBUF_1_TFE_SHIFT 23 -#define SQ_MUBUF_1_TFE_SIZE 1 -#define SQ_MUBUF_1_VADDR_MASK 0x000000ff -#define SQ_MUBUF_1_VADDR_SHIFT 0x00000000 -#define SQ_MUBUF_1_VADDR_SIZE 8 -#define SQ_MUBUF_1_VDATA_MASK 0x0000ff00 -#define SQ_MUBUF_1_VDATA_SHIFT 8 -#define SQ_MUBUF_1_VDATA_SIZE 8 -#define SQ_NE 0x00000005 -#define SQ_NEQ 0x0000000d -#define SQ_NFMT_FLOAT__SI__CI 0x00000007 -#define SQ_NFMT_SINT__SI__CI 0x00000005 -#define SQ_NFMT_SNORM__SI__CI 0x00000001 -#define SQ_NFMT_SNORM_OGL__SI__CI 0x00000006 -#define SQ_NFMT_SSCALED__SI__CI 0x00000003 -#define SQ_NFMT_UINT__SI__CI 0x00000004 -#define SQ_NFMT_UNORM__SI__CI 0x00000000 -#define SQ_NFMT_USCALED__SI__CI 0x00000002 -#define SQ_NGE 0x00000009 -#define SQ_NGT 0x0000000b -#define SQ_NLE 0x0000000c -#define SQ_NLG 0x0000000a -#define SQ_NLT 0x0000000e -#define SQ_NUM_ATTR 0x00000021 -#define SQ_NUM_TTMP 0x0000000c -#define SQ_NUM_VGPR 0x00000100 -#define SQ_O 0x00000007 -#define SQ_OMOD_D2 0x00000003 -#define SQ_OMOD_M2 0x00000001 -#define SQ_OMOD_M4 0x00000002 -#define SQ_OMOD_OFF 0x00000000 -#define SQ_PARAM_P0 0x00000002 -#define SQ_PARAM_P10 0x00000000 -#define SQ_PARAM_P20 0x00000001 -#define SQ_SENDMSG_GSOP_SHIFT 0x00000004 -#define SQ_SENDMSG_GSOP_SIZE 0x00000002 -#define SQ_SENDMSG_MSG_SHIFT 0x00000000 -#define SQ_SENDMSG_MSG_SIZE 0x00000004 -#define SQ_SENDMSG_STREAMID_SHIFT 0x00000008 -#define SQ_SENDMSG_STREAMID_SIZE 0x00000002 -#define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004 -#define SQ_SENDMSG_SYSTEM_SIZE 0x00000003 -#define SQ_SGPR0 0x00000000 -#define SQ_SMRD_DEFAULT__SI__CI 0xcdcdcdcd -#define SQ_SMRD_ENCODING_MASK__SI__CI 0xf8000000 -#define SQ_SMRD_ENCODING_SHIFT__SI__CI 27 -#define SQ_SMRD_ENCODING_SIZE__SI__CI 5 -#define SQ_SMRD_IMM_MASK__SI__CI 0x00000100 -#define SQ_SMRD_IMM_SHIFT__SI__CI 8 -#define SQ_SMRD_IMM_SIZE__SI__CI 1 -#define SQ_SMRD_OFFSET_MASK__SI__CI 0x000000ff -#define SQ_SMRD_OFFSET_SHIFT__SI__CI 0x00000000 -#define SQ_SMRD_OFFSET_SIZE__SI__CI 8 -#define SQ_SMRD_OP_MASK__SI__CI 0x07c00000 -#define SQ_SMRD_OP_SHIFT__SI__CI 22 -#define SQ_SMRD_OP_SIZE__SI__CI 5 -#define SQ_SMRD_REG_SIZE__SI__CI 32 -#define SQ_SMRD_SBASE_MASK__SI__CI 0x00007e00 -#define SQ_SMRD_SBASE_SHIFT__SI__CI 9 -#define SQ_SMRD_SBASE_SIZE__SI__CI 6 -#define SQ_SMRD_SDST_MASK__SI__CI 0x003f8000 -#define SQ_SMRD_SDST_SHIFT__SI__CI 15 -#define SQ_SMRD_SDST_SIZE__SI__CI 7 -#define SQ_SOP1_DEFAULT 0xcdcdcdcd -#define SQ_SOP1_ENCODING_MASK 0xff800000 -#define SQ_SOP1_ENCODING_SHIFT 23 -#define SQ_SOP1_ENCODING_SIZE 9 -#define SQ_SOP1_OP_MASK 0x0000ff00 -#define SQ_SOP1_OP_SHIFT 8 -#define SQ_SOP1_OP_SIZE 8 -#define SQ_SOP1_REG_SIZE 32 -#define SQ_SOP1_SDST_MASK 0x007f0000 -#define SQ_SOP1_SDST_SHIFT 16 -#define SQ_SOP1_SDST_SIZE 7 -#define SQ_SOP1_SSRC0_MASK 0x000000ff -#define SQ_SOP1_SSRC0_SHIFT 0x00000000 -#define SQ_SOP1_SSRC0_SIZE 8 -#define SQ_SOP2_DEFAULT 0xcdcdcdcd -#define SQ_SOP2_ENCODING_MASK 0xc0000000 -#define SQ_SOP2_ENCODING_SHIFT 30 -#define SQ_SOP2_ENCODING_SIZE 2 -#define SQ_SOP2_OP_MASK 0x3f800000 -#define SQ_SOP2_OP_SHIFT 23 -#define SQ_SOP2_OP_SIZE 7 -#define SQ_SOP2_REG_SIZE 32 -#define SQ_SOP2_SDST_MASK 0x007f0000 -#define SQ_SOP2_SDST_SHIFT 16 -#define SQ_SOP2_SDST_SIZE 7 -#define SQ_SOP2_SSRC0_MASK 0x000000ff -#define SQ_SOP2_SSRC0_SHIFT 0x00000000 -#define SQ_SOP2_SSRC0_SIZE 8 -#define SQ_SOP2_SSRC1_MASK 0x0000ff00 -#define SQ_SOP2_SSRC1_SHIFT 8 -#define SQ_SOP2_SSRC1_SIZE 8 -#define SQ_SOPC_DEFAULT 0xcdcdcdcd -#define SQ_SOPC_ENCODING_MASK 0xff800000 -#define SQ_SOPC_ENCODING_SHIFT 23 -#define SQ_SOPC_ENCODING_SIZE 9 -#define SQ_SOPC_OP_MASK 0x007f0000 -#define SQ_SOPC_OP_SHIFT 16 -#define SQ_SOPC_OP_SIZE 7 -#define SQ_SOPC_REG_SIZE 32 -#define SQ_SOPC_SSRC0_MASK 0x000000ff -#define SQ_SOPC_SSRC0_SHIFT 0x00000000 -#define SQ_SOPC_SSRC0_SIZE 8 -#define SQ_SOPC_SSRC1_MASK 0x0000ff00 -#define SQ_SOPC_SSRC1_SHIFT 8 -#define SQ_SOPC_SSRC1_SIZE 8 -#define SQ_SOPK_DEFAULT 0xcdcdcdcd -#define SQ_SOPK_ENCODING_MASK 0xf0000000 -#define SQ_SOPK_ENCODING_SHIFT 28 -#define SQ_SOPK_ENCODING_SIZE 4 -#define SQ_SOPK_OP_MASK 0x0f800000 -#define SQ_SOPK_OP_SHIFT 23 -#define SQ_SOPK_OP_SIZE 5 -#define SQ_SOPK_REG_SIZE 32 -#define SQ_SOPK_SDST_MASK 0x007f0000 -#define SQ_SOPK_SDST_SHIFT 16 -#define SQ_SOPK_SDST_SIZE 7 -#define SQ_SOPK_SIMM16_MASK 0x0000ffff -#define SQ_SOPK_SIMM16_SHIFT 0x00000000 -#define SQ_SOPK_SIMM16_SIZE 16 -#define SQ_SOPP_DEFAULT 0xcdcdcdcd -#define SQ_SOPP_ENCODING_MASK 0xff800000 -#define SQ_SOPP_ENCODING_SHIFT 23 -#define SQ_SOPP_ENCODING_SIZE 9 -#define SQ_SOPP_OP_MASK 0x007f0000 -#define SQ_SOPP_OP_SHIFT 16 -#define SQ_SOPP_OP_SIZE 7 -#define SQ_SOPP_REG_SIZE 32 -#define SQ_SOPP_SIMM16_MASK 0x0000ffff -#define SQ_SOPP_SIMM16_SHIFT 0x00000000 -#define SQ_SOPP_SIMM16_SIZE 16 -#define SQ_SRC_0 0x00000080 -#define SQ_SRC_0_5 0x000000f0 -#define SQ_SRC_1 0x000000f2 -#define SQ_SRC_10_INT 0x0000008a -#define SQ_SRC_11_INT 0x0000008b -#define SQ_SRC_12_INT 0x0000008c -#define SQ_SRC_13_INT 0x0000008d -#define SQ_SRC_14_INT 0x0000008e -#define SQ_SRC_15_INT 0x0000008f -#define SQ_SRC_16_INT 0x00000090 -#define SQ_SRC_17_INT 0x00000091 -#define SQ_SRC_18_INT 0x00000092 -#define SQ_SRC_19_INT 0x00000093 -#define SQ_SRC_1_INT 0x00000081 -#define SQ_SRC_2 0x000000f4 -#define SQ_SRC_20_INT 0x00000094 -#define SQ_SRC_21_INT 0x00000095 -#define SQ_SRC_22_INT 0x00000096 -#define SQ_SRC_23_INT 0x00000097 -#define SQ_SRC_24_INT 0x00000098 -#define SQ_SRC_25_INT 0x00000099 -#define SQ_SRC_26_INT 0x0000009a -#define SQ_SRC_27_INT 0x0000009b -#define SQ_SRC_28_INT 0x0000009c -#define SQ_SRC_29_INT 0x0000009d -#define SQ_SRC_2_INT 0x00000082 -#define SQ_SRC_30_INT 0x0000009e -#define SQ_SRC_31_INT 0x0000009f -#define SQ_SRC_32_INT 0x000000a0 -#define SQ_SRC_33_INT 0x000000a1 -#define SQ_SRC_34_INT 0x000000a2 -#define SQ_SRC_35_INT 0x000000a3 -#define SQ_SRC_36_INT 0x000000a4 -#define SQ_SRC_37_INT 0x000000a5 -#define SQ_SRC_38_INT 0x000000a6 -#define SQ_SRC_39_INT 0x000000a7 -#define SQ_SRC_3_INT 0x00000083 -#define SQ_SRC_4 0x000000f6 -#define SQ_SRC_40_INT 0x000000a8 -#define SQ_SRC_41_INT 0x000000a9 -#define SQ_SRC_42_INT 0x000000aa -#define SQ_SRC_43_INT 0x000000ab -#define SQ_SRC_44_INT 0x000000ac -#define SQ_SRC_45_INT 0x000000ad -#define SQ_SRC_46_INT 0x000000ae -#define SQ_SRC_47_INT 0x000000af -#define SQ_SRC_48_INT 0x000000b0 -#define SQ_SRC_49_INT 0x000000b1 -#define SQ_SRC_4_INT 0x00000084 -#define SQ_SRC_50_INT 0x000000b2 -#define SQ_SRC_51_INT 0x000000b3 -#define SQ_SRC_52_INT 0x000000b4 -#define SQ_SRC_53_INT 0x000000b5 -#define SQ_SRC_54_INT 0x000000b6 -#define SQ_SRC_55_INT 0x000000b7 -#define SQ_SRC_56_INT 0x000000b8 -#define SQ_SRC_57_INT 0x000000b9 -#define SQ_SRC_58_INT 0x000000ba -#define SQ_SRC_59_INT 0x000000bb -#define SQ_SRC_5_INT 0x00000085 -#define SQ_SRC_60_INT 0x000000bc -#define SQ_SRC_61_INT 0x000000bd -#define SQ_SRC_62_INT 0x000000be -#define SQ_SRC_63_INT 0x000000bf -#define SQ_SRC_64_INT 0x000000c0 -#define SQ_SRC_6_INT 0x00000086 -#define SQ_SRC_7_INT 0x00000087 -#define SQ_SRC_8_INT 0x00000088 -#define SQ_SRC_9_INT 0x00000089 -#define SQ_SRC_EXECZ 0x000000fc -#define SQ_SRC_LDS_DIRECT 0x000000fe -#define SQ_SRC_LITERAL 0x000000ff -#define SQ_SRC_M_0_5 0x000000f1 -#define SQ_SRC_M_1 0x000000f3 -#define SQ_SRC_M_10_INT 0x000000ca -#define SQ_SRC_M_11_INT 0x000000cb -#define SQ_SRC_M_12_INT 0x000000cc -#define SQ_SRC_M_13_INT 0x000000cd -#define SQ_SRC_M_14_INT 0x000000ce -#define SQ_SRC_M_15_INT 0x000000cf -#define SQ_SRC_M_16_INT 0x000000d0 -#define SQ_SRC_M_1_INT 0x000000c1 -#define SQ_SRC_M_2 0x000000f5 -#define SQ_SRC_M_2_INT 0x000000c2 -#define SQ_SRC_M_3_INT 0x000000c3 -#define SQ_SRC_M_4 0x000000f7 -#define SQ_SRC_M_4_INT 0x000000c4 -#define SQ_SRC_M_5_INT 0x000000c5 -#define SQ_SRC_M_6_INT 0x000000c6 -#define SQ_SRC_M_7_INT 0x000000c7 -#define SQ_SRC_M_8_INT 0x000000c8 -#define SQ_SRC_M_9_INT 0x000000c9 -#define SQ_SRC_SCC 0x000000fd -#define SQ_SRC_VCCZ 0x000000fb -#define SQ_SRC_VGPR0 0x00000100 -#define SQ_SRC_VGPR_BIT 0x00000100 -#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001 -#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003 -#define SQ_SYSMSG_OP_REG_RD 0x00000002 -#define SQ_SYSMSG_OP_TTRACE_PC 0x00000004 -#define SQ_S_ADDC_U32 0x00000004 -#define SQ_S_ADD_I32 0x00000002 -#define SQ_S_ADD_U32 0x00000000 -#define SQ_S_BARRIER 0x0000000a -#define SQ_S_BITCMP0_B32 0x0000000c -#define SQ_S_BITCMP0_B64 0x0000000e -#define SQ_S_BITCMP1_B32 0x0000000d -#define SQ_S_BITCMP1_B64 0x0000000f -#define SQ_S_BRANCH 0x00000002 -#define SQ_S_BUFFER_LOAD_DWORD 0x00000008 -#define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c -#define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009 -#define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a -#define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b -#define SQ_S_CBRANCH_CDBGSYS_AND_USER__CI__VI 0x0000001a -#define SQ_S_CBRANCH_CDBGSYS_OR_USER__CI__VI 0x00000019 -#define SQ_S_CBRANCH_CDBGSYS__CI__VI 0x00000017 -#define SQ_S_CBRANCH_CDBGUSER__CI__VI 0x00000018 -#define SQ_S_CBRANCH_EXECNZ 0x00000009 -#define SQ_S_CBRANCH_EXECZ 0x00000008 -#define SQ_S_CBRANCH_SCC0 0x00000004 -#define SQ_S_CBRANCH_SCC1 0x00000005 -#define SQ_S_CBRANCH_VCCNZ 0x00000007 -#define SQ_S_CBRANCH_VCCZ 0x00000006 -#define SQ_S_CMP_EQ_I32 0x00000000 -#define SQ_S_CMP_EQ_U32 0x00000006 -#define SQ_S_CMP_GE_I32 0x00000003 -#define SQ_S_CMP_GE_U32 0x00000009 -#define SQ_S_CMP_GT_I32 0x00000002 -#define SQ_S_CMP_GT_U32 0x00000008 -#define SQ_S_CMP_LE_I32 0x00000005 -#define SQ_S_CMP_LE_U32 0x0000000b -#define SQ_S_CMP_LG_I32 0x00000001 -#define SQ_S_CMP_LG_U32 0x00000007 -#define SQ_S_CMP_LT_I32 0x00000004 -#define SQ_S_CMP_LT_U32 0x0000000a -#define SQ_S_CSELECT_B32 0x0000000a -#define SQ_S_CSELECT_B64 0x0000000b -#define SQ_S_DCACHE_INV_VOL__CI 0x0000001d -#define SQ_S_DECPERFLEVEL 0x00000015 -#define SQ_S_ENDPGM 0x00000001 -#define SQ_S_ICACHE_INV 0x00000013 -#define SQ_S_INCPERFLEVEL 0x00000014 -#define SQ_S_LOAD_DWORD 0x00000000 -#define SQ_S_LOAD_DWORDX16 0x00000004 -#define SQ_S_LOAD_DWORDX2 0x00000001 -#define SQ_S_LOAD_DWORDX4 0x00000002 -#define SQ_S_LOAD_DWORDX8 0x00000003 -#define SQ_S_MAX_I32 0x00000008 -#define SQ_S_MAX_U32 0x00000009 -#define SQ_S_MIN_I32 0x00000006 -#define SQ_S_MIN_U32 0x00000007 -#define SQ_S_MOVK_I32 0x00000000 -#define SQ_S_NOP 0x00000000 -#define SQ_S_SENDMSG 0x00000010 -#define SQ_S_SENDMSGHALT 0x00000011 -#define SQ_S_SETHALT 0x0000000d -#define SQ_S_SETKILL__CI__VI 0x0000000b -#define SQ_S_SETPRIO 0x0000000f -#define SQ_S_SETVSKIP 0x00000010 -#define SQ_S_SLEEP 0x0000000e -#define SQ_S_SUBB_U32 0x00000005 -#define SQ_S_SUB_I32 0x00000003 -#define SQ_S_SUB_U32 0x00000001 -#define SQ_S_TRAP 0x00000012 -#define SQ_S_TTRACEDATA 0x00000016 -#define SQ_S_WAITCNT 0x0000000c -#define SQ_T 0x00000007 -#define SQ_TBA_HI 0x0000006d -#define SQ_TBA_LO 0x0000006c -#define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_TBUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_TMA_HI 0x0000006f -#define SQ_TMA_LO 0x0000006e -#define SQ_TRU 0x0000000f -#define SQ_TTMP0 0x00000070 -#define SQ_TTMP1 0x00000071 -#define SQ_TTMP10 0x0000007a -#define SQ_TTMP11 0x0000007b -#define SQ_TTMP2 0x00000072 -#define SQ_TTMP3 0x00000073 -#define SQ_TTMP4 0x00000074 -#define SQ_TTMP5 0x00000075 -#define SQ_TTMP6 0x00000076 -#define SQ_TTMP7 0x00000077 -#define SQ_TTMP8 0x00000078 -#define SQ_TTMP9 0x00000079 -#define SQ_U 0x00000008 -#define SQ_VCC_ALL 0x00000000 -#define SQ_VCC_HI 0x0000006b -#define SQ_VCC_LO 0x0000006a -#define SQ_VGPR0 0x00000000 -#define SQ_VINTRP_ATTRCHAN_MASK 0x00000300 -#define SQ_VINTRP_ATTRCHAN_SHIFT 8 -#define SQ_VINTRP_ATTRCHAN_SIZE 2 -#define SQ_VINTRP_ATTR_MASK 0x0000fc00 -#define SQ_VINTRP_ATTR_SHIFT 10 -#define SQ_VINTRP_ATTR_SIZE 6 -#define SQ_VINTRP_DEFAULT 0xcdcdcdcd -#define SQ_VINTRP_ENCODING_MASK 0xfc000000 -#define SQ_VINTRP_ENCODING_SHIFT 26 -#define SQ_VINTRP_ENCODING_SIZE 6 -#define SQ_VINTRP_OP_MASK 0x00030000 -#define SQ_VINTRP_OP_SHIFT 16 -#define SQ_VINTRP_OP_SIZE 2 -#define SQ_VINTRP_REG_SIZE 32 -#define SQ_VINTRP_VDST_MASK 0x03fc0000 -#define SQ_VINTRP_VDST_SHIFT 18 -#define SQ_VINTRP_VDST_SIZE 8 -#define SQ_VINTRP_VSRC_MASK 0x000000ff -#define SQ_VINTRP_VSRC_SHIFT 0x00000000 -#define SQ_VINTRP_VSRC_SIZE 8 -#define SQ_VOP1_DEFAULT 0xcdcdcdcd -#define SQ_VOP1_ENCODING_MASK 0xfe000000 -#define SQ_VOP1_ENCODING_SHIFT 25 -#define SQ_VOP1_ENCODING_SIZE 7 -#define SQ_VOP1_OP_MASK 0x0001fe00 -#define SQ_VOP1_OP_SHIFT 9 -#define SQ_VOP1_OP_SIZE 8 -#define SQ_VOP1_REG_SIZE 32 -#define SQ_VOP1_SRC0_MASK 0x000001ff -#define SQ_VOP1_SRC0_SHIFT 0x00000000 -#define SQ_VOP1_SRC0_SIZE 9 -#define SQ_VOP1_VDST_MASK 0x01fe0000 -#define SQ_VOP1_VDST_SHIFT 17 -#define SQ_VOP1_VDST_SIZE 8 -#define SQ_VOP2_DEFAULT 0xcdcdcdcd -#define SQ_VOP2_ENCODING_MASK 0x80000000 -#define SQ_VOP2_ENCODING_SHIFT 31 -#define SQ_VOP2_ENCODING_SIZE 1 -#define SQ_VOP2_OP_MASK 0x7e000000 -#define SQ_VOP2_OP_SHIFT 25 -#define SQ_VOP2_OP_SIZE 6 -#define SQ_VOP2_REG_SIZE 32 -#define SQ_VOP2_SRC0_MASK 0x000001ff -#define SQ_VOP2_SRC0_SHIFT 0x00000000 -#define SQ_VOP2_SRC0_SIZE 9 -#define SQ_VOP2_VDST_MASK 0x01fe0000 -#define SQ_VOP2_VDST_SHIFT 17 -#define SQ_VOP2_VDST_SIZE 8 -#define SQ_VOP2_VSRC1_MASK 0x0001fe00 -#define SQ_VOP2_VSRC1_SHIFT 9 -#define SQ_VOP2_VSRC1_SIZE 8 -#define SQ_VOP3_0_ABS_MASK 0x00000700 -#define SQ_VOP3_0_ABS_SHIFT 8 -#define SQ_VOP3_0_ABS_SIZE 3 -#define SQ_VOP3_0_CLAMP_SIZE 1 -#define SQ_VOP3_0_ENCODING_MASK 0xfc000000 -#define SQ_VOP3_0_ENCODING_SHIFT 26 -#define SQ_VOP3_0_ENCODING_SIZE 6 -#define SQ_VOP3_0_REG_SIZE 32 -#define SQ_VOP3_0_SDST_ENC_ENCODING_MASK 0xfc000000 -#define SQ_VOP3_0_SDST_ENC_ENCODING_SHIFT 26 -#define SQ_VOP3_0_SDST_ENC_ENCODING_SIZE 6 -#define SQ_VOP3_0_SDST_ENC_REG_SIZE 32 -#define SQ_VOP3_0_SDST_ENC_SDST_MASK 0x00007f00 -#define SQ_VOP3_0_SDST_ENC_SDST_SHIFT 8 -#define SQ_VOP3_0_SDST_ENC_SDST_SIZE 7 -#define SQ_VOP3_0_SDST_ENC_VDST_MASK 0x000000ff -#define SQ_VOP3_0_SDST_ENC_VDST_SHIFT 0x00000000 -#define SQ_VOP3_0_SDST_ENC_VDST_SIZE 8 -#define SQ_VOP3_0_VDST_MASK 0x000000ff -#define SQ_VOP3_0_VDST_SHIFT 0x00000000 -#define SQ_VOP3_0_VDST_SIZE 8 -#define SQ_VOP3_1_DEFAULT 0xcdcdcdcd -#define SQ_VOP3_1_NEG_MASK 0xe0000000 -#define SQ_VOP3_1_NEG_SHIFT 29 -#define SQ_VOP3_1_NEG_SIZE 3 -#define SQ_VOP3_1_OMOD_MASK 0x18000000 -#define SQ_VOP3_1_OMOD_SHIFT 27 -#define SQ_VOP3_1_OMOD_SIZE 2 -#define SQ_VOP3_1_REG_SIZE 32 -#define SQ_VOP3_1_SRC0_MASK 0x000001ff -#define SQ_VOP3_1_SRC0_SHIFT 0x00000000 -#define SQ_VOP3_1_SRC0_SIZE 9 -#define SQ_VOP3_1_SRC1_MASK 0x0003fe00 -#define SQ_VOP3_1_SRC1_SHIFT 9 -#define SQ_VOP3_1_SRC1_SIZE 9 -#define SQ_VOP3_1_SRC2_MASK 0x07fc0000 -#define SQ_VOP3_1_SRC2_SHIFT 18 -#define SQ_VOP3_1_SRC2_SIZE 9 -#define SQ_VOPC_DEFAULT 0xcdcdcdcd -#define SQ_VOPC_ENCODING_MASK 0xfe000000 -#define SQ_VOPC_ENCODING_SHIFT 25 -#define SQ_VOPC_ENCODING_SIZE 7 -#define SQ_VOPC_OP_MASK 0x01fe0000 -#define SQ_VOPC_OP_SHIFT 17 -#define SQ_VOPC_OP_SIZE 8 -#define SQ_VOPC_REG_SIZE 32 -#define SQ_VOPC_SRC0_MASK 0x000001ff -#define SQ_VOPC_SRC0_SHIFT 0x00000000 -#define SQ_VOPC_SRC0_SIZE 9 -#define SQ_VOPC_VSRC1_MASK 0x0001fe00 -#define SQ_VOPC_VSRC1_SHIFT 9 -#define SQ_VOPC_VSRC1_SIZE 8 -#define SQ_V_ADD_I32__SI__CI 0x00000025 -#define SQ_V_ASHR_I32__SI__CI 0x00000017 -#define SQ_V_ASHR_I64__SI__CI 0x00000163 -#define SQ_V_CEIL_F64__CI__VI 0x00000018 -#define SQ_V_CMPSX_EQ_F32__SI__CI 0x00000052 -#define SQ_V_CMPSX_EQ_F64__SI__CI 0x00000072 -#define SQ_V_CMPSX_F_F32__SI__CI 0x00000050 -#define SQ_V_CMPSX_F_F64__SI__CI 0x00000070 -#define SQ_V_CMPSX_GE_F32__SI__CI 0x00000056 -#define SQ_V_CMPSX_GE_F64__SI__CI 0x00000076 -#define SQ_V_CMPSX_GT_F32__SI__CI 0x00000054 -#define SQ_V_CMPSX_GT_F64__SI__CI 0x00000074 -#define SQ_V_CMPSX_LE_F32__SI__CI 0x00000053 -#define SQ_V_CMPSX_LE_F64__SI__CI 0x00000073 -#define SQ_V_CMPSX_LG_F32__SI__CI 0x00000055 -#define SQ_V_CMPSX_LG_F64__SI__CI 0x00000075 -#define SQ_V_CMPSX_LT_F32__SI__CI 0x00000051 -#define SQ_V_CMPSX_LT_F64__SI__CI 0x00000071 -#define SQ_V_CMPSX_NEQ_F32__SI__CI 0x0000005d -#define SQ_V_CMPSX_NEQ_F64__SI__CI 0x0000007d -#define SQ_V_CMPSX_NGE_F32__SI__CI 0x00000059 -#define SQ_V_CMPSX_NGE_F64__SI__CI 0x00000079 -#define SQ_V_CMPSX_NGT_F32__SI__CI 0x0000005b -#define SQ_V_CMPSX_NGT_F64__SI__CI 0x0000007b -#define SQ_V_CMPSX_NLE_F32__SI__CI 0x0000005c -#define SQ_V_CMPSX_NLE_F64__SI__CI 0x0000007c -#define SQ_V_CMPSX_NLG_F32__SI__CI 0x0000005a -#define SQ_V_CMPSX_NLG_F64__SI__CI 0x0000007a -#define SQ_V_CMPSX_NLT_F32__SI__CI 0x0000005e -#define SQ_V_CMPSX_NLT_F64__SI__CI 0x0000007e -#define SQ_V_CMPSX_O_F32__SI__CI 0x00000057 -#define SQ_V_CMPSX_O_F64__SI__CI 0x00000077 -#define SQ_V_CMPSX_TRU_F32__SI__CI 0x0000005f -#define SQ_V_CMPSX_TRU_F64__SI__CI 0x0000007f -#define SQ_V_CMPSX_U_F32__SI__CI 0x00000058 -#define SQ_V_CMPSX_U_F64__SI__CI 0x00000078 -#define SQ_V_CMPS_EQ_F32__SI__CI 0x00000042 -#define SQ_V_CMPS_EQ_F64__SI__CI 0x00000062 -#define SQ_V_CMPS_F_F32__SI__CI 0x00000040 -#define SQ_V_CMPS_F_F64__SI__CI 0x00000060 -#define SQ_V_CMPS_GE_F32__SI__CI 0x00000046 -#define SQ_V_CMPS_GE_F64__SI__CI 0x00000066 -#define SQ_V_CMPS_GT_F32__SI__CI 0x00000044 -#define SQ_V_CMPS_GT_F64__SI__CI 0x00000064 -#define SQ_V_CMPS_LE_F32__SI__CI 0x00000043 -#define SQ_V_CMPS_LE_F64__SI__CI 0x00000063 -#define SQ_V_CMPS_LG_F32__SI__CI 0x00000045 -#define SQ_V_CMPS_LG_F64__SI__CI 0x00000065 -#define SQ_V_CMPS_LT_F32__SI__CI 0x00000041 -#define SQ_V_CMPS_LT_F64__SI__CI 0x00000061 -#define SQ_V_CMPS_NEQ_F32__SI__CI 0x0000004d -#define SQ_V_CMPS_NEQ_F64__SI__CI 0x0000006d -#define SQ_V_CMPS_NGE_F32__SI__CI 0x00000049 -#define SQ_V_CMPS_NGE_F64__SI__CI 0x00000069 -#define SQ_V_CMPS_NGT_F32__SI__CI 0x0000004b -#define SQ_V_CMPS_NGT_F64__SI__CI 0x0000006b -#define SQ_V_CMPS_NLE_F32__SI__CI 0x0000004c -#define SQ_V_CMPS_NLE_F64__SI__CI 0x0000006c -#define SQ_V_CMPS_NLG_F32__SI__CI 0x0000004a -#define SQ_V_CMPS_NLG_F64__SI__CI 0x0000006a -#define SQ_V_CMPS_NLT_F32__SI__CI 0x0000004e -#define SQ_V_CMPS_NLT_F64__SI__CI 0x0000006e -#define SQ_V_CMPS_O_F32__SI__CI 0x00000047 -#define SQ_V_CMPS_O_F64__SI__CI 0x00000067 -#define SQ_V_CMPS_TRU_F32__SI__CI 0x0000004f -#define SQ_V_CMPS_TRU_F64__SI__CI 0x0000006f -#define SQ_V_CMPS_U_F32__SI__CI 0x00000048 -#define SQ_V_CMPS_U_F64__SI__CI 0x00000068 -#define SQ_V_CNDMASK_B32 0x00000000 -#define SQ_V_CVT_F16_F32 0x0000000a -#define SQ_V_CVT_F32_F16 0x0000000b -#define SQ_V_CVT_F32_F64 0x0000000f -#define SQ_V_CVT_F32_I32 0x00000005 -#define SQ_V_CVT_F32_U32 0x00000006 -#define SQ_V_CVT_F32_UBYTE0 0x00000011 -#define SQ_V_CVT_F32_UBYTE1 0x00000012 -#define SQ_V_CVT_F32_UBYTE2 0x00000013 -#define SQ_V_CVT_F32_UBYTE3 0x00000014 -#define SQ_V_CVT_F64_F32 0x00000010 -#define SQ_V_CVT_F64_I32 0x00000004 -#define SQ_V_CVT_F64_U32 0x00000016 -#define SQ_V_CVT_FLR_I32_F32 0x0000000d -#define SQ_V_CVT_I32_F32 0x00000008 -#define SQ_V_CVT_I32_F64 0x00000003 -#define SQ_V_CVT_OFF_F32_I4 0x0000000e -#define SQ_V_CVT_RPI_I32_F32 0x0000000c -#define SQ_V_CVT_U32_F32 0x00000007 -#define SQ_V_CVT_U32_F64 0x00000015 -#define SQ_V_EXP_LEGACY_F32__CI 0x00000046 -#define SQ_V_FLOOR_F64__CI__VI 0x0000001a -#define SQ_V_INTERP_MOV_F32 0x00000002 -#define SQ_V_INTERP_P1_F32 0x00000000 -#define SQ_V_INTERP_P2_F32 0x00000001 -#define SQ_V_LOG_CLAMP_F32__SI__CI 0x00000026 -#define SQ_V_LOG_LEGACY_F32__CI 0x00000045 -#define SQ_V_LSHL_B32__SI__CI 0x00000019 -#define SQ_V_LSHL_B64__SI__CI 0x00000161 -#define SQ_V_LSHR_B32__SI__CI 0x00000015 -#define SQ_V_LSHR_B64__SI__CI 0x00000162 -#define SQ_V_MAD_I64_I32__CI 0x00000177 -#define SQ_V_MAD_U64_U32__CI 0x00000176 -#define SQ_V_MAX_LEGACY_F32__SI__CI 0x0000000e -#define SQ_V_MIN_LEGACY_F32__SI__CI 0x0000000d -#define SQ_V_MOV_B32 0x00000001 -#define SQ_V_MOV_FED_B32 0x00000009 -#define SQ_V_MQSAD_PK_U16_U8__CI 0x00000173 -#define SQ_V_MQSAD_U32_U8__CI 0x00000175 -#define SQ_V_MQSAD_U8__SI 0x00000173 -#define SQ_V_MULLIT_F32__SI__CI 0x00000150 -#define SQ_V_MUL_LO_I32__SI__CI 0x0000016b -#define SQ_V_NOP 0x00000000 -#define SQ_V_OP1_COUNT 0x00000080 -#define SQ_V_OP2_COUNT 0x00000040 -#define SQ_V_OP2_OFFSET 0x00000100 -#define SQ_V_OPC_COUNT 0x00000100 -#define SQ_V_OPC_OFFSET 0x00000000 -#define SQ_V_QSAD_PK_U16_U8__CI 0x00000172 -#define SQ_V_QSAD_U8__SI 0x00000172 -#define SQ_V_RCP_CLAMP_F32__SI__CI 0x00000028 -#define SQ_V_RCP_CLAMP_F64__SI__CI 0x00000030 -#define SQ_V_RCP_LEGACY_F32__SI__CI 0x00000029 -#define SQ_V_READFIRSTLANE_B32 0x00000002 -#define SQ_V_RNDNE_F64__CI__VI 0x00000019 -#define SQ_V_RSQ_CLAMP_F32__SI__CI 0x0000002c -#define SQ_V_RSQ_CLAMP_F64__SI__CI 0x00000032 -#define SQ_V_RSQ_LEGACY_F32__SI__CI 0x0000002d -#define SQ_V_SUBREV_I32__SI__CI 0x00000027 -#define SQ_V_SUB_I32__SI__CI 0x00000026 -#define SQ_V_TRUNC_F64__CI__VI 0x00000017 -#define SQ_WAITCNT_EXP_SHIFT 0x00000004 -#define SQ_WAITCNT_EXP_SIZE 0x00000003 -#define SQ_WAITCNT_LGKM_SHIFT 0x00000008 -#define SQ_WAITCNT_LGKM_SIZE 0x00000004 -#define SQ_WAITCNT_VM_SHIFT 0x00000000 -#define SQ_WAITCNT_VM_SIZE 0x00000004 - -// Merged Defines - -#define SQ_BUFFER_ATOMIC_ADD__SI__CI 0x00000032 -#define SQ_BUFFER_ATOMIC_ADD__VI 0x00000042 -#define SQ_BUFFER_ATOMIC_ADD_X2__SI__CI 0x00000052 -#define SQ_BUFFER_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_BUFFER_ATOMIC_AND__SI__CI 0x00000039 -#define SQ_BUFFER_ATOMIC_AND__VI 0x00000048 -#define SQ_BUFFER_ATOMIC_AND_X2__SI__CI 0x00000059 -#define SQ_BUFFER_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_BUFFER_ATOMIC_CMPSWAP__SI__CI 0x00000031 -#define SQ_BUFFER_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__SI__CI 0x00000051 -#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_BUFFER_ATOMIC_DEC__SI__CI 0x0000003d -#define SQ_BUFFER_ATOMIC_DEC__VI 0x0000004c -#define SQ_BUFFER_ATOMIC_DEC_X2__SI__CI 0x0000005d -#define SQ_BUFFER_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_BUFFER_ATOMIC_INC__SI__CI 0x0000003c -#define SQ_BUFFER_ATOMIC_INC__VI 0x0000004b -#define SQ_BUFFER_ATOMIC_INC_X2__SI__CI 0x0000005c -#define SQ_BUFFER_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_BUFFER_ATOMIC_OR__SI__CI 0x0000003a -#define SQ_BUFFER_ATOMIC_OR__VI 0x00000049 -#define SQ_BUFFER_ATOMIC_OR_X2__SI__CI 0x0000005a -#define SQ_BUFFER_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_BUFFER_ATOMIC_SMAX__SI__CI 0x00000037 -#define SQ_BUFFER_ATOMIC_SMAX__VI 0x00000046 -#define SQ_BUFFER_ATOMIC_SMAX_X2__SI__CI 0x00000057 -#define SQ_BUFFER_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_BUFFER_ATOMIC_SMIN__SI__CI 0x00000035 -#define SQ_BUFFER_ATOMIC_SMIN__VI 0x00000044 -#define SQ_BUFFER_ATOMIC_SMIN_X2__SI__CI 0x00000055 -#define SQ_BUFFER_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_BUFFER_ATOMIC_SUB__SI__CI 0x00000033 -#define SQ_BUFFER_ATOMIC_SUB__VI 0x00000043 -#define SQ_BUFFER_ATOMIC_SUB_X2__SI__CI 0x00000053 -#define SQ_BUFFER_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_BUFFER_ATOMIC_SWAP__SI__CI 0x00000030 -#define SQ_BUFFER_ATOMIC_SWAP__VI 0x00000040 -#define SQ_BUFFER_ATOMIC_SWAP_X2__SI__CI 0x00000050 -#define SQ_BUFFER_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_BUFFER_ATOMIC_UMAX__SI__CI 0x00000038 -#define SQ_BUFFER_ATOMIC_UMAX__VI 0x00000047 -#define SQ_BUFFER_ATOMIC_UMAX_X2__SI__CI 0x00000058 -#define SQ_BUFFER_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_BUFFER_ATOMIC_UMIN__SI__CI 0x00000036 -#define SQ_BUFFER_ATOMIC_UMIN__VI 0x00000045 -#define SQ_BUFFER_ATOMIC_UMIN_X2__SI__CI 0x00000056 -#define SQ_BUFFER_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_BUFFER_ATOMIC_XOR__SI__CI 0x0000003b -#define SQ_BUFFER_ATOMIC_XOR__VI 0x0000004a -#define SQ_BUFFER_ATOMIC_XOR_X2__SI__CI 0x0000005b -#define SQ_BUFFER_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_BUFFER_LOAD_DWORD__SI__CI 0x0000000c -#define SQ_BUFFER_LOAD_DWORD__VI 0x00000014 -#define SQ_BUFFER_LOAD_DWORDX2__SI__CI 0x0000000d -#define SQ_BUFFER_LOAD_DWORDX2__VI 0x00000015 -#define SQ_BUFFER_LOAD_DWORDX3__VI 0x00000016 -#define SQ_BUFFER_LOAD_DWORDX4__SI__CI 0x0000000e -#define SQ_BUFFER_LOAD_DWORDX4__VI 0x00000017 -#define SQ_BUFFER_LOAD_FORMAT_D16_X__VI 0x00000008 -#define SQ_BUFFER_LOAD_FORMAT_D16_XY__VI 0x00000009 -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ__VI 0x0000000a -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW__VI 0x0000000b -#define SQ_BUFFER_LOAD_SBYTE__SI__CI 0x00000009 -#define SQ_BUFFER_LOAD_SBYTE__VI 0x00000011 -#define SQ_BUFFER_LOAD_SSHORT__SI__CI 0x0000000b -#define SQ_BUFFER_LOAD_SSHORT__VI 0x00000013 -#define SQ_BUFFER_LOAD_UBYTE__SI__CI 0x00000008 -#define SQ_BUFFER_LOAD_UBYTE__VI 0x00000010 -#define SQ_BUFFER_LOAD_USHORT__SI__CI 0x0000000a -#define SQ_BUFFER_LOAD_USHORT__VI 0x00000012 -#define SQ_BUFFER_STORE_DWORDX3__VI 0x0000001e -#define SQ_BUFFER_STORE_DWORDX4__SI__CI 0x0000001e -#define SQ_BUFFER_STORE_DWORDX4__VI 0x0000001f -#define SQ_BUFFER_STORE_FORMAT_D16_X__VI 0x0000000c -#define SQ_BUFFER_STORE_FORMAT_D16_XY__VI 0x0000000d -#define SQ_BUFFER_STORE_FORMAT_D16_XYZ__VI 0x0000000e -#define SQ_BUFFER_STORE_FORMAT_D16_XYZW__VI 0x0000000f -#define SQ_BUFFER_STORE_LDS_DWORD__VI 0x0000003d -#define SQ_BUFFER_WBINVL1__SI__CI 0x00000071 -#define SQ_BUFFER_WBINVL1__VI 0x0000003e -#define SQ_BUFFER_WBINVL1_VOL__VI 0x0000003f -#define SQ_DPP_BOUND_OFF__VI 0x00000000 -#define SQ_DPP_BOUND_ZERO__VI 0x00000001 -#define SQ_DPP_QUAD_PERM__VI 0x00000000 -#define SQ_DPP_ROW_BCAST15__VI 0x00000142 -#define SQ_DPP_ROW_BCAST31__VI 0x00000143 -#define SQ_DPP_ROW_HALF_MIRROR__VI 0x00000141 -#define SQ_DPP_ROW_MIRROR__VI 0x00000140 -#define SQ_DPP_ROW_RR1__VI 0x00000121 -#define SQ_DPP_ROW_RR10__VI 0x0000012a -#define SQ_DPP_ROW_RR11__VI 0x0000012b -#define SQ_DPP_ROW_RR12__VI 0x0000012c -#define SQ_DPP_ROW_RR13__VI 0x0000012d -#define SQ_DPP_ROW_RR14__VI 0x0000012e -#define SQ_DPP_ROW_RR15__VI 0x0000012f -#define SQ_DPP_ROW_RR2__VI 0x00000122 -#define SQ_DPP_ROW_RR3__VI 0x00000123 -#define SQ_DPP_ROW_RR4__VI 0x00000124 -#define SQ_DPP_ROW_RR5__VI 0x00000125 -#define SQ_DPP_ROW_RR6__VI 0x00000126 -#define SQ_DPP_ROW_RR7__VI 0x00000127 -#define SQ_DPP_ROW_RR8__VI 0x00000128 -#define SQ_DPP_ROW_RR9__VI 0x00000129 -#define SQ_DPP_ROW_SL1__VI 0x00000101 -#define SQ_DPP_ROW_SL10__VI 0x0000010a -#define SQ_DPP_ROW_SL11__VI 0x0000010b -#define SQ_DPP_ROW_SL12__VI 0x0000010c -#define SQ_DPP_ROW_SL13__VI 0x0000010d -#define SQ_DPP_ROW_SL14__VI 0x0000010e -#define SQ_DPP_ROW_SL15__VI 0x0000010f -#define SQ_DPP_ROW_SL2__VI 0x00000102 -#define SQ_DPP_ROW_SL3__VI 0x00000103 -#define SQ_DPP_ROW_SL4__VI 0x00000104 -#define SQ_DPP_ROW_SL5__VI 0x00000105 -#define SQ_DPP_ROW_SL6__VI 0x00000106 -#define SQ_DPP_ROW_SL7__VI 0x00000107 -#define SQ_DPP_ROW_SL8__VI 0x00000108 -#define SQ_DPP_ROW_SL9__VI 0x00000109 -#define SQ_DPP_ROW_SR1__VI 0x00000111 -#define SQ_DPP_ROW_SR10__VI 0x0000011a -#define SQ_DPP_ROW_SR11__VI 0x0000011b -#define SQ_DPP_ROW_SR12__VI 0x0000011c -#define SQ_DPP_ROW_SR13__VI 0x0000011d -#define SQ_DPP_ROW_SR14__VI 0x0000011e -#define SQ_DPP_ROW_SR15__VI 0x0000011f -#define SQ_DPP_ROW_SR2__VI 0x00000112 -#define SQ_DPP_ROW_SR3__VI 0x00000113 -#define SQ_DPP_ROW_SR4__VI 0x00000114 -#define SQ_DPP_ROW_SR5__VI 0x00000115 -#define SQ_DPP_ROW_SR6__VI 0x00000116 -#define SQ_DPP_ROW_SR7__VI 0x00000117 -#define SQ_DPP_ROW_SR8__VI 0x00000118 -#define SQ_DPP_ROW_SR9__VI 0x00000119 -#define SQ_DPP_WF_RL1__VI 0x00000134 -#define SQ_DPP_WF_RR1__VI 0x0000013c -#define SQ_DPP_WF_SL1__VI 0x00000130 -#define SQ_DPP_WF_SR1__VI 0x00000138 -#define SQ_DS_0_DEFAULT__SI__CI 0xcdcccdcd -#define SQ_DS_0_DEFAULT__VI 0xcdcdcdcd -#define SQ_DS_0_GDS_MASK__SI__CI 0x00020000 -#define SQ_DS_0_GDS_MASK__VI 0x00010000 -#define SQ_DS_0_GDS_SHIFT__SI__CI 17 -#define SQ_DS_0_GDS_SHIFT__VI 16 -#define SQ_DS_0_GET_ENCODING__VI(sq_ds_0) \ - ((sq_ds_0 & SQ_DS_0_ENCODING_MASK) >> SQ_DS_0_ENCODING_SHIFT) - -#define SQ_DS_0_GET_GDS__VI(sq_ds_0) ((sq_ds_0 & SQ_DS_0_GDS_MASK) >> SQ_DS_0_GDS_SHIFT) - -#define SQ_DS_0_GET_OFFSET0__VI(sq_ds_0) ((sq_ds_0 & SQ_DS_0_OFFSET0_MASK) >> SQ_DS_0_OFFSET0_SHIFT) - -#define SQ_DS_0_GET_OFFSET1__VI(sq_ds_0) ((sq_ds_0 & SQ_DS_0_OFFSET1_MASK) >> SQ_DS_0_OFFSET1_SHIFT) - -#define SQ_DS_0_GET_OP__VI(sq_ds_0) ((sq_ds_0 & SQ_DS_0_OP_MASK) >> SQ_DS_0_OP_SHIFT) - -#define SQ_DS_0_MASK__VI \ - (SQ_DS_0_OFFSET0_MASK | SQ_DS_0_OFFSET1_MASK | SQ_DS_0_GDS_MASK | SQ_DS_0_OP_MASK | \ - SQ_DS_0_ENCODING_MASK) - -#define SQ_DS_0_OP_MASK__SI__CI 0x03fc0000 -#define SQ_DS_0_OP_MASK__VI 0x01fe0000 -#define SQ_DS_0_OP_SHIFT__SI__CI 18 -#define SQ_DS_0_OP_SHIFT__VI 17 -#define SQ_DS_0_SET_ENCODING__VI(sq_ds_0_reg, encoding) \ - sq_ds_0_reg = (sq_ds_0_reg & ~SQ_DS_0_ENCODING_MASK) | (encoding << SQ_DS_0_ENCODING_SHIFT) - -#define SQ_DS_0_SET_GDS__VI(sq_ds_0_reg, gds) \ - sq_ds_0_reg = (sq_ds_0_reg & ~SQ_DS_0_GDS_MASK) | (gds << SQ_DS_0_GDS_SHIFT) - -#define SQ_DS_0_SET_OFFSET0__VI(sq_ds_0_reg, offset0) \ - sq_ds_0_reg = (sq_ds_0_reg & ~SQ_DS_0_OFFSET0_MASK) | (offset0 << SQ_DS_0_OFFSET0_SHIFT) - -#define SQ_DS_0_SET_OFFSET1__VI(sq_ds_0_reg, offset1) \ - sq_ds_0_reg = (sq_ds_0_reg & ~SQ_DS_0_OFFSET1_MASK) | (offset1 << SQ_DS_0_OFFSET1_SHIFT) - -#define SQ_DS_0_SET_OP__VI(sq_ds_0_reg, op) \ - sq_ds_0_reg = (sq_ds_0_reg & ~SQ_DS_0_OP_MASK) | (op << SQ_DS_0_OP_SHIFT) - -#define SQ_DS_1_GET_ADDR__VI(sq_ds_1) ((sq_ds_1 & SQ_DS_1_ADDR_MASK) >> SQ_DS_1_ADDR_SHIFT) - -#define SQ_DS_1_GET_DATA0__VI(sq_ds_1) ((sq_ds_1 & SQ_DS_1_DATA0_MASK) >> SQ_DS_1_DATA0_SHIFT) - -#define SQ_DS_1_GET_DATA1__VI(sq_ds_1) ((sq_ds_1 & SQ_DS_1_DATA1_MASK) >> SQ_DS_1_DATA1_SHIFT) - -#define SQ_DS_1_GET_VDST__VI(sq_ds_1) ((sq_ds_1 & SQ_DS_1_VDST_MASK) >> SQ_DS_1_VDST_SHIFT) - -#define SQ_DS_1_MASK__VI \ - (SQ_DS_1_ADDR_MASK | SQ_DS_1_DATA0_MASK | SQ_DS_1_DATA1_MASK | SQ_DS_1_VDST_MASK) - -#define SQ_DS_1_SET_ADDR__VI(sq_ds_1_reg, addr) \ - sq_ds_1_reg = (sq_ds_1_reg & ~SQ_DS_1_ADDR_MASK) | (addr << SQ_DS_1_ADDR_SHIFT) - -#define SQ_DS_1_SET_DATA0__VI(sq_ds_1_reg, data0) \ - sq_ds_1_reg = (sq_ds_1_reg & ~SQ_DS_1_DATA0_MASK) | (data0 << SQ_DS_1_DATA0_SHIFT) - -#define SQ_DS_1_SET_DATA1__VI(sq_ds_1_reg, data1) \ - sq_ds_1_reg = (sq_ds_1_reg & ~SQ_DS_1_DATA1_MASK) | (data1 << SQ_DS_1_DATA1_SHIFT) - -#define SQ_DS_1_SET_VDST__VI(sq_ds_1_reg, vdst) \ - sq_ds_1_reg = (sq_ds_1_reg & ~SQ_DS_1_VDST_MASK) | (vdst << SQ_DS_1_VDST_SHIFT) - -#define SQ_DS_ADD_F32__VI 0x00000015 -#define SQ_DS_ADD_RTN_F32__VI 0x00000035 -#define SQ_DS_ADD_SRC2_F32__VI 0x00000095 -#define SQ_DS_APPEND__SI__CI 0x0000003e -#define SQ_DS_APPEND__VI 0x000000be -#define SQ_DS_BPERMUTE_B32__VI 0x0000003f -#define SQ_DS_CONSUME__SI__CI 0x0000003d -#define SQ_DS_CONSUME__VI 0x000000bd -#define SQ_DS_GWS_BARRIER__SI__CI 0x0000001d -#define SQ_DS_GWS_BARRIER__VI 0x0000009d -#define SQ_DS_GWS_INIT__SI__CI 0x00000019 -#define SQ_DS_GWS_INIT__VI 0x00000099 -#define SQ_DS_GWS_SEMA_BR__SI__CI 0x0000001b -#define SQ_DS_GWS_SEMA_BR__VI 0x0000009b -#define SQ_DS_GWS_SEMA_P__SI__CI 0x0000001c -#define SQ_DS_GWS_SEMA_P__VI 0x0000009c -#define SQ_DS_GWS_SEMA_RELEASE_ALL__VI 0x00000098 -#define SQ_DS_GWS_SEMA_V__SI__CI 0x0000001a -#define SQ_DS_GWS_SEMA_V__VI 0x0000009a -#define SQ_DS_ORDERED_COUNT__SI__CI 0x0000003f -#define SQ_DS_ORDERED_COUNT__VI 0x000000bf -#define SQ_DS_PERMUTE_B32__VI 0x0000003e -#define SQ_DS_SWIZZLE_B32__SI__CI 0x00000035 -#define SQ_DS_SWIZZLE_B32__VI 0x0000003d -#define SQ_ENC_EXP_BITS__SI__CI 0xf8000000 -#define SQ_ENC_EXP_BITS__VI 0xc4000000 -#define SQ_ENC_EXP_FIELD__SI__CI 0x0000003e -#define SQ_ENC_EXP_FIELD__VI 0x00000031 -#define SQ_ENC_SMEM_BITS__VI 0xc0000000 -#define SQ_ENC_SMEM_FIELD__VI 0x00000030 -#define SQ_ENC_SMEM_MASK__VI 0xfc000000 -#define SQ_ENC_VINTRP_BITS__SI__CI 0xc8000000 -#define SQ_ENC_VINTRP_BITS__VI 0xd4000000 -#define SQ_ENC_VINTRP_FIELD__SI__CI 0x00000032 -#define SQ_ENC_VINTRP_FIELD__VI 0x00000035 -#define SQ_EXP_0_GET_COMPR__VI(sq_exp_0) ((sq_exp_0 & SQ_EXP_0_COMPR_MASK) >> SQ_EXP_0_COMPR_SHIFT) - -#define SQ_EXP_0_GET_DONE__VI(sq_exp_0) ((sq_exp_0 & SQ_EXP_0_DONE_MASK) >> SQ_EXP_0_DONE_SHIFT) - -#define SQ_EXP_0_GET_EN__VI(sq_exp_0) ((sq_exp_0 & SQ_EXP_0_EN_MASK) >> SQ_EXP_0_EN_SHIFT) - -#define SQ_EXP_0_GET_ENCODING__VI(sq_exp_0) \ - ((sq_exp_0 & SQ_EXP_0_ENCODING_MASK) >> SQ_EXP_0_ENCODING_SHIFT) - -#define SQ_EXP_0_GET_TGT__VI(sq_exp_0) ((sq_exp_0 & SQ_EXP_0_TGT_MASK) >> SQ_EXP_0_TGT_SHIFT) - -#define SQ_EXP_0_GET_VM__VI(sq_exp_0) ((sq_exp_0 & SQ_EXP_0_VM_MASK) >> SQ_EXP_0_VM_SHIFT) - -#define SQ_EXP_0_MASK__VI \ - (SQ_EXP_0_EN_MASK | SQ_EXP_0_TGT_MASK | SQ_EXP_0_COMPR_MASK | SQ_EXP_0_DONE_MASK | \ - SQ_EXP_0_VM_MASK | SQ_EXP_0_ENCODING_MASK) - -#define SQ_EXP_0_SET_COMPR__VI(sq_exp_0_reg, compr) \ - sq_exp_0_reg = (sq_exp_0_reg & ~SQ_EXP_0_COMPR_MASK) | (compr << SQ_EXP_0_COMPR_SHIFT) - -#define SQ_EXP_0_SET_DONE__VI(sq_exp_0_reg, done) \ - sq_exp_0_reg = (sq_exp_0_reg & ~SQ_EXP_0_DONE_MASK) | (done << SQ_EXP_0_DONE_SHIFT) - -#define SQ_EXP_0_SET_EN__VI(sq_exp_0_reg, en) \ - sq_exp_0_reg = (sq_exp_0_reg & ~SQ_EXP_0_EN_MASK) | (en << SQ_EXP_0_EN_SHIFT) - -#define SQ_EXP_0_SET_ENCODING__VI(sq_exp_0_reg, encoding) \ - sq_exp_0_reg = (sq_exp_0_reg & ~SQ_EXP_0_ENCODING_MASK) | (encoding << SQ_EXP_0_ENCODING_SHIFT) - -#define SQ_EXP_0_SET_TGT__VI(sq_exp_0_reg, tgt) \ - sq_exp_0_reg = (sq_exp_0_reg & ~SQ_EXP_0_TGT_MASK) | (tgt << SQ_EXP_0_TGT_SHIFT) - -#define SQ_EXP_0_SET_VM__VI(sq_exp_0_reg, vm) \ - sq_exp_0_reg = (sq_exp_0_reg & ~SQ_EXP_0_VM_MASK) | (vm << SQ_EXP_0_VM_SHIFT) - -#define SQ_EXP_1_GET_VSRC0__VI(sq_exp_1) ((sq_exp_1 & SQ_EXP_1_VSRC0_MASK) >> SQ_EXP_1_VSRC0_SHIFT) - -#define SQ_EXP_1_GET_VSRC1__VI(sq_exp_1) ((sq_exp_1 & SQ_EXP_1_VSRC1_MASK) >> SQ_EXP_1_VSRC1_SHIFT) - -#define SQ_EXP_1_GET_VSRC2__VI(sq_exp_1) ((sq_exp_1 & SQ_EXP_1_VSRC2_MASK) >> SQ_EXP_1_VSRC2_SHIFT) - -#define SQ_EXP_1_GET_VSRC3__VI(sq_exp_1) ((sq_exp_1 & SQ_EXP_1_VSRC3_MASK) >> SQ_EXP_1_VSRC3_SHIFT) - -#define SQ_EXP_1_MASK__VI \ - (SQ_EXP_1_VSRC0_MASK | SQ_EXP_1_VSRC1_MASK | SQ_EXP_1_VSRC2_MASK | SQ_EXP_1_VSRC3_MASK) - -#define SQ_EXP_1_SET_VSRC0__VI(sq_exp_1_reg, vsrc0) \ - sq_exp_1_reg = (sq_exp_1_reg & ~SQ_EXP_1_VSRC0_MASK) | (vsrc0 << SQ_EXP_1_VSRC0_SHIFT) - -#define SQ_EXP_1_SET_VSRC1__VI(sq_exp_1_reg, vsrc1) \ - sq_exp_1_reg = (sq_exp_1_reg & ~SQ_EXP_1_VSRC1_MASK) | (vsrc1 << SQ_EXP_1_VSRC1_SHIFT) - -#define SQ_EXP_1_SET_VSRC2__VI(sq_exp_1_reg, vsrc2) \ - sq_exp_1_reg = (sq_exp_1_reg & ~SQ_EXP_1_VSRC2_MASK) | (vsrc2 << SQ_EXP_1_VSRC2_SHIFT) - -#define SQ_EXP_1_SET_VSRC3__VI(sq_exp_1_reg, vsrc3) \ - sq_exp_1_reg = (sq_exp_1_reg & ~SQ_EXP_1_VSRC3_MASK) | (vsrc3 << SQ_EXP_1_VSRC3_SHIFT) - -#define SQ_FLAT_0_GET_ENCODING__VI(sq_flat_0) \ - ((sq_flat_0 & SQ_FLAT_0_ENCODING_MASK) >> SQ_FLAT_0_ENCODING_SHIFT) - -#define SQ_FLAT_0_GET_GLC__VI(sq_flat_0) ((sq_flat_0 & SQ_FLAT_0_GLC_MASK) >> SQ_FLAT_0_GLC_SHIFT) - -#define SQ_FLAT_0_GET_OP__VI(sq_flat_0) ((sq_flat_0 & SQ_FLAT_0_OP_MASK) >> SQ_FLAT_0_OP_SHIFT) - -#define SQ_FLAT_0_GET_SLC__VI(sq_flat_0) ((sq_flat_0 & SQ_FLAT_0_SLC_MASK) >> SQ_FLAT_0_SLC_SHIFT) - -#define SQ_FLAT_0_MASK__VI \ - (SQ_FLAT_0_GLC_MASK | SQ_FLAT_0_SLC_MASK | SQ_FLAT_0_OP_MASK | SQ_FLAT_0_ENCODING_MASK) - -#define SQ_FLAT_0_SET_ENCODING__VI(sq_flat_0_reg, encoding) \ - sq_flat_0_reg = \ - (sq_flat_0_reg & ~SQ_FLAT_0_ENCODING_MASK) | (encoding << SQ_FLAT_0_ENCODING_SHIFT) - -#define SQ_FLAT_0_SET_GLC__VI(sq_flat_0_reg, glc) \ - sq_flat_0_reg = (sq_flat_0_reg & ~SQ_FLAT_0_GLC_MASK) | (glc << SQ_FLAT_0_GLC_SHIFT) - -#define SQ_FLAT_0_SET_OP__VI(sq_flat_0_reg, op) \ - sq_flat_0_reg = (sq_flat_0_reg & ~SQ_FLAT_0_OP_MASK) | (op << SQ_FLAT_0_OP_SHIFT) - -#define SQ_FLAT_0_SET_SLC__VI(sq_flat_0_reg, slc) \ - sq_flat_0_reg = (sq_flat_0_reg & ~SQ_FLAT_0_SLC_MASK) | (slc << SQ_FLAT_0_SLC_SHIFT) - -#define SQ_FLAT_1_GET_ADDR__VI(sq_flat_1) \ - ((sq_flat_1 & SQ_FLAT_1_ADDR_MASK) >> SQ_FLAT_1_ADDR_SHIFT) - -#define SQ_FLAT_1_GET_DATA__VI(sq_flat_1) \ - ((sq_flat_1 & SQ_FLAT_1_DATA_MASK) >> SQ_FLAT_1_DATA_SHIFT) - -#define SQ_FLAT_1_GET_TFE__VI(sq_flat_1) ((sq_flat_1 & SQ_FLAT_1_TFE_MASK) >> SQ_FLAT_1_TFE_SHIFT) - -#define SQ_FLAT_1_GET_VDST__VI(sq_flat_1) \ - ((sq_flat_1 & SQ_FLAT_1_VDST_MASK) >> SQ_FLAT_1_VDST_SHIFT) - -#define SQ_FLAT_1_MASK__VI \ - (SQ_FLAT_1_ADDR_MASK | SQ_FLAT_1_DATA_MASK | SQ_FLAT_1_TFE_MASK | SQ_FLAT_1_VDST_MASK) - -#define SQ_FLAT_1_SET_ADDR__VI(sq_flat_1_reg, addr) \ - sq_flat_1_reg = (sq_flat_1_reg & ~SQ_FLAT_1_ADDR_MASK) | (addr << SQ_FLAT_1_ADDR_SHIFT) - -#define SQ_FLAT_1_SET_DATA__VI(sq_flat_1_reg, data) \ - sq_flat_1_reg = (sq_flat_1_reg & ~SQ_FLAT_1_DATA_MASK) | (data << SQ_FLAT_1_DATA_SHIFT) - -#define SQ_FLAT_1_SET_TFE__VI(sq_flat_1_reg, tfe) \ - sq_flat_1_reg = (sq_flat_1_reg & ~SQ_FLAT_1_TFE_MASK) | (tfe << SQ_FLAT_1_TFE_SHIFT) - -#define SQ_FLAT_1_SET_VDST__VI(sq_flat_1_reg, vdst) \ - sq_flat_1_reg = (sq_flat_1_reg & ~SQ_FLAT_1_VDST_MASK) | (vdst << SQ_FLAT_1_VDST_SHIFT) - -#define SQ_FLAT_ATOMIC_ADD__VI 0x00000042 -#define SQ_FLAT_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_FLAT_ATOMIC_AND__VI 0x00000048 -#define SQ_FLAT_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_FLAT_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_FLAT_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_FLAT_ATOMIC_DEC__VI 0x0000004c -#define SQ_FLAT_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_FLAT_ATOMIC_INC__VI 0x0000004b -#define SQ_FLAT_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_FLAT_ATOMIC_OR__VI 0x00000049 -#define SQ_FLAT_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_FLAT_ATOMIC_SMAX__VI 0x00000046 -#define SQ_FLAT_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_FLAT_ATOMIC_SMIN__VI 0x00000044 -#define SQ_FLAT_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_FLAT_ATOMIC_SUB__VI 0x00000043 -#define SQ_FLAT_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_FLAT_ATOMIC_SWAP__VI 0x00000040 -#define SQ_FLAT_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_FLAT_ATOMIC_UMAX__VI 0x00000047 -#define SQ_FLAT_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_FLAT_ATOMIC_UMIN__VI 0x00000045 -#define SQ_FLAT_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_FLAT_ATOMIC_XOR__VI 0x0000004a -#define SQ_FLAT_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_FLAT_LOAD_DWORD__VI 0x00000014 -#define SQ_FLAT_LOAD_DWORDX2__VI 0x00000015 -#define SQ_FLAT_LOAD_DWORDX3__VI 0x00000016 -#define SQ_FLAT_LOAD_DWORDX4__VI 0x00000017 -#define SQ_FLAT_LOAD_SBYTE__VI 0x00000011 -#define SQ_FLAT_LOAD_SSHORT__VI 0x00000013 -#define SQ_FLAT_LOAD_UBYTE__VI 0x00000010 -#define SQ_FLAT_LOAD_USHORT__VI 0x00000012 -#define SQ_FLAT_SCRATCH_HI__VI 0x00000067 -#define SQ_FLAT_SCRATCH_LO__VI 0x00000066 -#define SQ_FLAT_STORE_DWORDX3__VI 0x0000001e -#define SQ_FLAT_STORE_DWORDX4__VI 0x0000001f -#define SQ_HW_REG_IB_DBG1__VI 0x0000000d -#define SQ_IMAGE_ATOMIC_ADD__SI__CI 0x00000011 -#define SQ_IMAGE_ATOMIC_ADD__VI 0x00000012 -#define SQ_IMAGE_ATOMIC_CMPSWAP__SI__CI 0x00000010 -#define SQ_IMAGE_ATOMIC_CMPSWAP__VI 0x00000011 -#define SQ_IMAGE_ATOMIC_SUB__SI__CI 0x00000012 -#define SQ_IMAGE_ATOMIC_SUB__VI 0x00000013 -#define SQ_IMAGE_ATOMIC_SWAP__SI__CI 0x0000000f -#define SQ_IMAGE_ATOMIC_SWAP__VI 0x00000010 -#define SQ_INST_GET_ENCODING__VI(sq_inst) \ - ((sq_inst & SQ_INST_ENCODING_MASK) >> SQ_INST_ENCODING_SHIFT) - -#define SQ_INST_MASK__VI (SQ_INST_ENCODING_MASK) - -#define SQ_INST_SET_ENCODING__VI(sq_inst_reg, encoding) \ - sq_inst_reg = (sq_inst_reg & ~SQ_INST_ENCODING_MASK) | (encoding << SQ_INST_ENCODING_SHIFT) - -#define SQ_L1__VI 0x00000001 -#define SQ_L10__VI 0x0000000a -#define SQ_L11__VI 0x0000000b -#define SQ_L12__VI 0x0000000c -#define SQ_L13__VI 0x0000000d -#define SQ_L14__VI 0x0000000e -#define SQ_L15__VI 0x0000000f -#define SQ_L2__VI 0x00000002 -#define SQ_L3__VI 0x00000003 -#define SQ_L4__VI 0x00000004 -#define SQ_L5__VI 0x00000005 -#define SQ_L6__VI 0x00000006 -#define SQ_L7__VI 0x00000007 -#define SQ_L8__VI 0x00000008 -#define SQ_L9__VI 0x00000009 -#define SQ_MIMG_0_GET_DA__VI(sq_mimg_0) ((sq_mimg_0 & SQ_MIMG_0_DA_MASK) >> SQ_MIMG_0_DA_SHIFT) - -#define SQ_MIMG_0_GET_DMASK__VI(sq_mimg_0) \ - ((sq_mimg_0 & SQ_MIMG_0_DMASK_MASK) >> SQ_MIMG_0_DMASK_SHIFT) - -#define SQ_MIMG_0_GET_ENCODING__VI(sq_mimg_0) \ - ((sq_mimg_0 & SQ_MIMG_0_ENCODING_MASK) >> SQ_MIMG_0_ENCODING_SHIFT) - -#define SQ_MIMG_0_GET_GLC__VI(sq_mimg_0) ((sq_mimg_0 & SQ_MIMG_0_GLC_MASK) >> SQ_MIMG_0_GLC_SHIFT) - -#define SQ_MIMG_0_GET_LWE__VI(sq_mimg_0) ((sq_mimg_0 & SQ_MIMG_0_LWE_MASK) >> SQ_MIMG_0_LWE_SHIFT) - -#define SQ_MIMG_0_GET_OP__VI(sq_mimg_0) ((sq_mimg_0 & SQ_MIMG_0_OP_MASK) >> SQ_MIMG_0_OP_SHIFT) - -#define SQ_MIMG_0_GET_R128__VI(sq_mimg_0) \ - ((sq_mimg_0 & SQ_MIMG_0_R128_MASK) >> SQ_MIMG_0_R128_SHIFT) - -#define SQ_MIMG_0_GET_SLC__VI(sq_mimg_0) ((sq_mimg_0 & SQ_MIMG_0_SLC_MASK) >> SQ_MIMG_0_SLC_SHIFT) - -#define SQ_MIMG_0_GET_TFE__VI(sq_mimg_0) ((sq_mimg_0 & SQ_MIMG_0_TFE_MASK) >> SQ_MIMG_0_TFE_SHIFT) - -#define SQ_MIMG_0_GET_UNORM__VI(sq_mimg_0) \ - ((sq_mimg_0 & SQ_MIMG_0_UNORM_MASK) >> SQ_MIMG_0_UNORM_SHIFT) - -#define SQ_MIMG_0_MASK__VI \ - (SQ_MIMG_0_DMASK_MASK | SQ_MIMG_0_UNORM_MASK | SQ_MIMG_0_GLC_MASK | SQ_MIMG_0_DA_MASK | \ - SQ_MIMG_0_R128_MASK | SQ_MIMG_0_TFE_MASK | SQ_MIMG_0_LWE_MASK | SQ_MIMG_0_OP_MASK | \ - SQ_MIMG_0_SLC_MASK | SQ_MIMG_0_ENCODING_MASK) - -#define SQ_MIMG_0_SET_DA__VI(sq_mimg_0_reg, da) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_DA_MASK) | (da << SQ_MIMG_0_DA_SHIFT) - -#define SQ_MIMG_0_SET_DMASK__VI(sq_mimg_0_reg, dmask) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_DMASK_MASK) | (dmask << SQ_MIMG_0_DMASK_SHIFT) - -#define SQ_MIMG_0_SET_ENCODING__VI(sq_mimg_0_reg, encoding) \ - sq_mimg_0_reg = \ - (sq_mimg_0_reg & ~SQ_MIMG_0_ENCODING_MASK) | (encoding << SQ_MIMG_0_ENCODING_SHIFT) - -#define SQ_MIMG_0_SET_GLC__VI(sq_mimg_0_reg, glc) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_GLC_MASK) | (glc << SQ_MIMG_0_GLC_SHIFT) - -#define SQ_MIMG_0_SET_LWE__VI(sq_mimg_0_reg, lwe) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_LWE_MASK) | (lwe << SQ_MIMG_0_LWE_SHIFT) - -#define SQ_MIMG_0_SET_OP__VI(sq_mimg_0_reg, op) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_OP_MASK) | (op << SQ_MIMG_0_OP_SHIFT) - -#define SQ_MIMG_0_SET_R128__VI(sq_mimg_0_reg, r128) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_R128_MASK) | (r128 << SQ_MIMG_0_R128_SHIFT) - -#define SQ_MIMG_0_SET_SLC__VI(sq_mimg_0_reg, slc) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_SLC_MASK) | (slc << SQ_MIMG_0_SLC_SHIFT) - -#define SQ_MIMG_0_SET_TFE__VI(sq_mimg_0_reg, tfe) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_TFE_MASK) | (tfe << SQ_MIMG_0_TFE_SHIFT) - -#define SQ_MIMG_0_SET_UNORM__VI(sq_mimg_0_reg, unorm) \ - sq_mimg_0_reg = (sq_mimg_0_reg & ~SQ_MIMG_0_UNORM_MASK) | (unorm << SQ_MIMG_0_UNORM_SHIFT) - -#define SQ_MIMG_1_D16_MASK__VI 0x80000000 -#define SQ_MIMG_1_D16_SHIFT__VI 31 -#define SQ_MIMG_1_D16_SIZE__VI 1 -#define SQ_MIMG_1_DEFAULT__SI__CI 0x01cdcdcd -#define SQ_MIMG_1_DEFAULT__VI 0x81cdcdcd -#define SQ_MIMG_1_GET_D16__VI(sq_mimg_1) ((sq_mimg_1 & SQ_MIMG_1_D16_MASK) >> SQ_MIMG_1_D16_SHIFT) - -#define SQ_MIMG_1_GET_SRSRC__VI(sq_mimg_1) \ - ((sq_mimg_1 & SQ_MIMG_1_SRSRC_MASK) >> SQ_MIMG_1_SRSRC_SHIFT) - -#define SQ_MIMG_1_GET_SSAMP__VI(sq_mimg_1) \ - ((sq_mimg_1 & SQ_MIMG_1_SSAMP_MASK) >> SQ_MIMG_1_SSAMP_SHIFT) - -#define SQ_MIMG_1_GET_VADDR__VI(sq_mimg_1) \ - ((sq_mimg_1 & SQ_MIMG_1_VADDR_MASK) >> SQ_MIMG_1_VADDR_SHIFT) - -#define SQ_MIMG_1_GET_VDATA__VI(sq_mimg_1) \ - ((sq_mimg_1 & SQ_MIMG_1_VDATA_MASK) >> SQ_MIMG_1_VDATA_SHIFT) - -#define SQ_MIMG_1_MASK__VI \ - (SQ_MIMG_1_VADDR_MASK | SQ_MIMG_1_VDATA_MASK | SQ_MIMG_1_SRSRC_MASK | SQ_MIMG_1_SSAMP_MASK | \ - SQ_MIMG_1_D16_MASK) - -#define SQ_MIMG_1_SET_D16__VI(sq_mimg_1_reg, d16) \ - sq_mimg_1_reg = (sq_mimg_1_reg & ~SQ_MIMG_1_D16_MASK) | (d16 << SQ_MIMG_1_D16_SHIFT) - -#define SQ_MIMG_1_SET_SRSRC__VI(sq_mimg_1_reg, srsrc) \ - sq_mimg_1_reg = (sq_mimg_1_reg & ~SQ_MIMG_1_SRSRC_MASK) | (srsrc << SQ_MIMG_1_SRSRC_SHIFT) - -#define SQ_MIMG_1_SET_SSAMP__VI(sq_mimg_1_reg, ssamp) \ - sq_mimg_1_reg = (sq_mimg_1_reg & ~SQ_MIMG_1_SSAMP_MASK) | (ssamp << SQ_MIMG_1_SSAMP_SHIFT) - -#define SQ_MIMG_1_SET_VADDR__VI(sq_mimg_1_reg, vaddr) \ - sq_mimg_1_reg = (sq_mimg_1_reg & ~SQ_MIMG_1_VADDR_MASK) | (vaddr << SQ_MIMG_1_VADDR_SHIFT) - -#define SQ_MIMG_1_SET_VDATA__VI(sq_mimg_1_reg, vdata) \ - sq_mimg_1_reg = (sq_mimg_1_reg & ~SQ_MIMG_1_VDATA_MASK) | (vdata << SQ_MIMG_1_VDATA_SHIFT) - -#define SQ_MSG_SAVEWAVE__VI 0x00000004 -#define SQ_MTBUF_0_GET_DFMT__VI(sq_mtbuf_0) \ - ((sq_mtbuf_0 & SQ_MTBUF_0_DFMT_MASK) >> SQ_MTBUF_0_DFMT_SHIFT) - -#define SQ_MTBUF_0_GET_ENCODING__VI(sq_mtbuf_0) \ - ((sq_mtbuf_0 & SQ_MTBUF_0_ENCODING_MASK) >> SQ_MTBUF_0_ENCODING_SHIFT) - -#define SQ_MTBUF_0_GET_GLC__VI(sq_mtbuf_0) \ - ((sq_mtbuf_0 & SQ_MTBUF_0_GLC_MASK) >> SQ_MTBUF_0_GLC_SHIFT) - -#define SQ_MTBUF_0_GET_IDXEN__VI(sq_mtbuf_0) \ - ((sq_mtbuf_0 & SQ_MTBUF_0_IDXEN_MASK) >> SQ_MTBUF_0_IDXEN_SHIFT) - -#define SQ_MTBUF_0_GET_NFMT__VI(sq_mtbuf_0) \ - ((sq_mtbuf_0 & SQ_MTBUF_0_NFMT_MASK) >> SQ_MTBUF_0_NFMT_SHIFT) - -#define SQ_MTBUF_0_GET_OFFEN__VI(sq_mtbuf_0) \ - ((sq_mtbuf_0 & SQ_MTBUF_0_OFFEN_MASK) >> SQ_MTBUF_0_OFFEN_SHIFT) - -#define SQ_MTBUF_0_GET_OFFSET__VI(sq_mtbuf_0) \ - ((sq_mtbuf_0 & SQ_MTBUF_0_OFFSET_MASK) >> SQ_MTBUF_0_OFFSET_SHIFT) - -#define SQ_MTBUF_0_GET_OP__VI(sq_mtbuf_0) ((sq_mtbuf_0 & SQ_MTBUF_0_OP_MASK) >> SQ_MTBUF_0_OP_SHIFT) - -#define SQ_MTBUF_0_MASK__VI \ - (SQ_MTBUF_0_OFFSET_MASK | SQ_MTBUF_0_OFFEN_MASK | SQ_MTBUF_0_IDXEN_MASK | SQ_MTBUF_0_GLC_MASK | \ - SQ_MTBUF_0_OP_MASK | SQ_MTBUF_0_DFMT_MASK | SQ_MTBUF_0_NFMT_MASK | SQ_MTBUF_0_ENCODING_MASK) - -#define SQ_MTBUF_0_OP_MASK__SI__CI 0x00070000 -#define SQ_MTBUF_0_OP_MASK__VI 0x00078000 -#define SQ_MTBUF_0_OP_SHIFT__SI__CI 16 -#define SQ_MTBUF_0_OP_SHIFT__VI 15 -#define SQ_MTBUF_0_OP_SIZE__SI__CI 3 -#define SQ_MTBUF_0_OP_SIZE__VI 4 -#define SQ_MTBUF_0_SET_DFMT__VI(sq_mtbuf_0_reg, dfmt) \ - sq_mtbuf_0_reg = (sq_mtbuf_0_reg & ~SQ_MTBUF_0_DFMT_MASK) | (dfmt << SQ_MTBUF_0_DFMT_SHIFT) - -#define SQ_MTBUF_0_SET_ENCODING__VI(sq_mtbuf_0_reg, encoding) \ - sq_mtbuf_0_reg = \ - (sq_mtbuf_0_reg & ~SQ_MTBUF_0_ENCODING_MASK) | (encoding << SQ_MTBUF_0_ENCODING_SHIFT) - -#define SQ_MTBUF_0_SET_GLC__VI(sq_mtbuf_0_reg, glc) \ - sq_mtbuf_0_reg = (sq_mtbuf_0_reg & ~SQ_MTBUF_0_GLC_MASK) | (glc << SQ_MTBUF_0_GLC_SHIFT) - -#define SQ_MTBUF_0_SET_IDXEN__VI(sq_mtbuf_0_reg, idxen) \ - sq_mtbuf_0_reg = (sq_mtbuf_0_reg & ~SQ_MTBUF_0_IDXEN_MASK) | (idxen << SQ_MTBUF_0_IDXEN_SHIFT) - -#define SQ_MTBUF_0_SET_NFMT__VI(sq_mtbuf_0_reg, nfmt) \ - sq_mtbuf_0_reg = (sq_mtbuf_0_reg & ~SQ_MTBUF_0_NFMT_MASK) | (nfmt << SQ_MTBUF_0_NFMT_SHIFT) - -#define SQ_MTBUF_0_SET_OFFEN__VI(sq_mtbuf_0_reg, offen) \ - sq_mtbuf_0_reg = (sq_mtbuf_0_reg & ~SQ_MTBUF_0_OFFEN_MASK) | (offen << SQ_MTBUF_0_OFFEN_SHIFT) - -#define SQ_MTBUF_0_SET_OFFSET__VI(sq_mtbuf_0_reg, offset) \ - sq_mtbuf_0_reg = (sq_mtbuf_0_reg & ~SQ_MTBUF_0_OFFSET_MASK) | (offset << SQ_MTBUF_0_OFFSET_SHIFT) - -#define SQ_MTBUF_0_SET_OP__VI(sq_mtbuf_0_reg, op) \ - sq_mtbuf_0_reg = (sq_mtbuf_0_reg & ~SQ_MTBUF_0_OP_MASK) | (op << SQ_MTBUF_0_OP_SHIFT) - -#define SQ_MTBUF_1_GET_SLC__VI(sq_mtbuf_1) \ - ((sq_mtbuf_1 & SQ_MTBUF_1_SLC_MASK) >> SQ_MTBUF_1_SLC_SHIFT) - -#define SQ_MTBUF_1_GET_SOFFSET__VI(sq_mtbuf_1) \ - ((sq_mtbuf_1 & SQ_MTBUF_1_SOFFSET_MASK) >> SQ_MTBUF_1_SOFFSET_SHIFT) - -#define SQ_MTBUF_1_GET_SRSRC__VI(sq_mtbuf_1) \ - ((sq_mtbuf_1 & SQ_MTBUF_1_SRSRC_MASK) >> SQ_MTBUF_1_SRSRC_SHIFT) - -#define SQ_MTBUF_1_GET_TFE__VI(sq_mtbuf_1) \ - ((sq_mtbuf_1 & SQ_MTBUF_1_TFE_MASK) >> SQ_MTBUF_1_TFE_SHIFT) - -#define SQ_MTBUF_1_GET_VADDR__VI(sq_mtbuf_1) \ - ((sq_mtbuf_1 & SQ_MTBUF_1_VADDR_MASK) >> SQ_MTBUF_1_VADDR_SHIFT) - -#define SQ_MTBUF_1_GET_VDATA__VI(sq_mtbuf_1) \ - ((sq_mtbuf_1 & SQ_MTBUF_1_VDATA_MASK) >> SQ_MTBUF_1_VDATA_SHIFT) - -#define SQ_MTBUF_1_MASK__VI \ - (SQ_MTBUF_1_VADDR_MASK | SQ_MTBUF_1_VDATA_MASK | SQ_MTBUF_1_SRSRC_MASK | SQ_MTBUF_1_SLC_MASK | \ - SQ_MTBUF_1_TFE_MASK | SQ_MTBUF_1_SOFFSET_MASK) - -#define SQ_MTBUF_1_SET_SLC__VI(sq_mtbuf_1_reg, slc) \ - sq_mtbuf_1_reg = (sq_mtbuf_1_reg & ~SQ_MTBUF_1_SLC_MASK) | (slc << SQ_MTBUF_1_SLC_SHIFT) - -#define SQ_MTBUF_1_SET_SOFFSET__VI(sq_mtbuf_1_reg, soffset) \ - sq_mtbuf_1_reg = \ - (sq_mtbuf_1_reg & ~SQ_MTBUF_1_SOFFSET_MASK) | (soffset << SQ_MTBUF_1_SOFFSET_SHIFT) - -#define SQ_MTBUF_1_SET_SRSRC__VI(sq_mtbuf_1_reg, srsrc) \ - sq_mtbuf_1_reg = (sq_mtbuf_1_reg & ~SQ_MTBUF_1_SRSRC_MASK) | (srsrc << SQ_MTBUF_1_SRSRC_SHIFT) - -#define SQ_MTBUF_1_SET_TFE__VI(sq_mtbuf_1_reg, tfe) \ - sq_mtbuf_1_reg = (sq_mtbuf_1_reg & ~SQ_MTBUF_1_TFE_MASK) | (tfe << SQ_MTBUF_1_TFE_SHIFT) - -#define SQ_MTBUF_1_SET_VADDR__VI(sq_mtbuf_1_reg, vaddr) \ - sq_mtbuf_1_reg = (sq_mtbuf_1_reg & ~SQ_MTBUF_1_VADDR_MASK) | (vaddr << SQ_MTBUF_1_VADDR_SHIFT) - -#define SQ_MTBUF_1_SET_VDATA__VI(sq_mtbuf_1_reg, vdata) \ - sq_mtbuf_1_reg = (sq_mtbuf_1_reg & ~SQ_MTBUF_1_VDATA_MASK) | (vdata << SQ_MTBUF_1_VDATA_SHIFT) - -#define SQ_MUBUF_0_DEFAULT__SI__CI 0xcdcdcdcd -#define SQ_MUBUF_0_DEFAULT__VI 0xcdcd4dcd -#define SQ_MUBUF_0_GET_ENCODING__VI(sq_mubuf_0) \ - ((sq_mubuf_0 & SQ_MUBUF_0_ENCODING_MASK) >> SQ_MUBUF_0_ENCODING_SHIFT) - -#define SQ_MUBUF_0_GET_GLC__VI(sq_mubuf_0) \ - ((sq_mubuf_0 & SQ_MUBUF_0_GLC_MASK) >> SQ_MUBUF_0_GLC_SHIFT) - -#define SQ_MUBUF_0_GET_IDXEN__VI(sq_mubuf_0) \ - ((sq_mubuf_0 & SQ_MUBUF_0_IDXEN_MASK) >> SQ_MUBUF_0_IDXEN_SHIFT) - -#define SQ_MUBUF_0_GET_LDS__VI(sq_mubuf_0) \ - ((sq_mubuf_0 & SQ_MUBUF_0_LDS_MASK) >> SQ_MUBUF_0_LDS_SHIFT) - -#define SQ_MUBUF_0_GET_OFFEN__VI(sq_mubuf_0) \ - ((sq_mubuf_0 & SQ_MUBUF_0_OFFEN_MASK) >> SQ_MUBUF_0_OFFEN_SHIFT) - -#define SQ_MUBUF_0_GET_OFFSET__VI(sq_mubuf_0) \ - ((sq_mubuf_0 & SQ_MUBUF_0_OFFSET_MASK) >> SQ_MUBUF_0_OFFSET_SHIFT) - -#define SQ_MUBUF_0_GET_OP__VI(sq_mubuf_0) ((sq_mubuf_0 & SQ_MUBUF_0_OP_MASK) >> SQ_MUBUF_0_OP_SHIFT) - -#define SQ_MUBUF_0_GET_SLC__VI(sq_mubuf_0) \ - ((sq_mubuf_0 & SQ_MUBUF_0_SLC_MASK) >> SQ_MUBUF_0_SLC_SHIFT) - -#define SQ_MUBUF_0_MASK__VI \ - (SQ_MUBUF_0_OFFSET_MASK | SQ_MUBUF_0_OFFEN_MASK | SQ_MUBUF_0_IDXEN_MASK | SQ_MUBUF_0_GLC_MASK | \ - SQ_MUBUF_0_LDS_MASK | SQ_MUBUF_0_SLC_MASK | SQ_MUBUF_0_OP_MASK | SQ_MUBUF_0_ENCODING_MASK) - -#define SQ_MUBUF_0_SET_ENCODING__VI(sq_mubuf_0_reg, encoding) \ - sq_mubuf_0_reg = \ - (sq_mubuf_0_reg & ~SQ_MUBUF_0_ENCODING_MASK) | (encoding << SQ_MUBUF_0_ENCODING_SHIFT) - -#define SQ_MUBUF_0_SET_GLC__VI(sq_mubuf_0_reg, glc) \ - sq_mubuf_0_reg = (sq_mubuf_0_reg & ~SQ_MUBUF_0_GLC_MASK) | (glc << SQ_MUBUF_0_GLC_SHIFT) - -#define SQ_MUBUF_0_SET_IDXEN__VI(sq_mubuf_0_reg, idxen) \ - sq_mubuf_0_reg = (sq_mubuf_0_reg & ~SQ_MUBUF_0_IDXEN_MASK) | (idxen << SQ_MUBUF_0_IDXEN_SHIFT) - -#define SQ_MUBUF_0_SET_LDS__VI(sq_mubuf_0_reg, lds) \ - sq_mubuf_0_reg = (sq_mubuf_0_reg & ~SQ_MUBUF_0_LDS_MASK) | (lds << SQ_MUBUF_0_LDS_SHIFT) - -#define SQ_MUBUF_0_SET_OFFEN__VI(sq_mubuf_0_reg, offen) \ - sq_mubuf_0_reg = (sq_mubuf_0_reg & ~SQ_MUBUF_0_OFFEN_MASK) | (offen << SQ_MUBUF_0_OFFEN_SHIFT) - -#define SQ_MUBUF_0_SET_OFFSET__VI(sq_mubuf_0_reg, offset) \ - sq_mubuf_0_reg = (sq_mubuf_0_reg & ~SQ_MUBUF_0_OFFSET_MASK) | (offset << SQ_MUBUF_0_OFFSET_SHIFT) - -#define SQ_MUBUF_0_SET_OP__VI(sq_mubuf_0_reg, op) \ - sq_mubuf_0_reg = (sq_mubuf_0_reg & ~SQ_MUBUF_0_OP_MASK) | (op << SQ_MUBUF_0_OP_SHIFT) - -#define SQ_MUBUF_0_SET_SLC__VI(sq_mubuf_0_reg, slc) \ - sq_mubuf_0_reg = (sq_mubuf_0_reg & ~SQ_MUBUF_0_SLC_MASK) | (slc << SQ_MUBUF_0_SLC_SHIFT) - -#define SQ_MUBUF_0_SLC_MASK__VI 0x00020000 -#define SQ_MUBUF_0_SLC_SHIFT__VI 17 -#define SQ_MUBUF_0_SLC_SIZE__VI 1 -#define SQ_MUBUF_1_DEFAULT__SI__CI 0xcdcdcdcd -#define SQ_MUBUF_1_DEFAULT__VI 0xcd8dcdcd -#define SQ_MUBUF_1_GET_SOFFSET__VI(sq_mubuf_1) \ - ((sq_mubuf_1 & SQ_MUBUF_1_SOFFSET_MASK) >> SQ_MUBUF_1_SOFFSET_SHIFT) - -#define SQ_MUBUF_1_GET_SRSRC__VI(sq_mubuf_1) \ - ((sq_mubuf_1 & SQ_MUBUF_1_SRSRC_MASK) >> SQ_MUBUF_1_SRSRC_SHIFT) - -#define SQ_MUBUF_1_GET_TFE__VI(sq_mubuf_1) \ - ((sq_mubuf_1 & SQ_MUBUF_1_TFE_MASK) >> SQ_MUBUF_1_TFE_SHIFT) - -#define SQ_MUBUF_1_GET_VADDR__VI(sq_mubuf_1) \ - ((sq_mubuf_1 & SQ_MUBUF_1_VADDR_MASK) >> SQ_MUBUF_1_VADDR_SHIFT) - -#define SQ_MUBUF_1_GET_VDATA__VI(sq_mubuf_1) \ - ((sq_mubuf_1 & SQ_MUBUF_1_VDATA_MASK) >> SQ_MUBUF_1_VDATA_SHIFT) - -#define SQ_MUBUF_1_MASK__VI \ - (SQ_MUBUF_1_VADDR_MASK | SQ_MUBUF_1_VDATA_MASK | SQ_MUBUF_1_SRSRC_MASK | SQ_MUBUF_1_TFE_MASK | \ - SQ_MUBUF_1_SOFFSET_MASK) - -#define SQ_MUBUF_1_SET_SOFFSET__VI(sq_mubuf_1_reg, soffset) \ - sq_mubuf_1_reg = \ - (sq_mubuf_1_reg & ~SQ_MUBUF_1_SOFFSET_MASK) | (soffset << SQ_MUBUF_1_SOFFSET_SHIFT) - -#define SQ_MUBUF_1_SET_SRSRC__VI(sq_mubuf_1_reg, srsrc) \ - sq_mubuf_1_reg = (sq_mubuf_1_reg & ~SQ_MUBUF_1_SRSRC_MASK) | (srsrc << SQ_MUBUF_1_SRSRC_SHIFT) - -#define SQ_MUBUF_1_SET_TFE__VI(sq_mubuf_1_reg, tfe) \ - sq_mubuf_1_reg = (sq_mubuf_1_reg & ~SQ_MUBUF_1_TFE_MASK) | (tfe << SQ_MUBUF_1_TFE_SHIFT) - -#define SQ_MUBUF_1_SET_VADDR__VI(sq_mubuf_1_reg, vaddr) \ - sq_mubuf_1_reg = (sq_mubuf_1_reg & ~SQ_MUBUF_1_VADDR_MASK) | (vaddr << SQ_MUBUF_1_VADDR_SHIFT) - -#define SQ_MUBUF_1_SET_VDATA__VI(sq_mubuf_1_reg, vdata) \ - sq_mubuf_1_reg = (sq_mubuf_1_reg & ~SQ_MUBUF_1_VDATA_MASK) | (vdata << SQ_MUBUF_1_VDATA_SHIFT) - -#define SQ_NUM_SGPR__SI__CI 0x00000068 -#define SQ_NUM_SGPR__VI 0x00000066 -#define SQ_R1__VI 0x00000001 -#define SQ_R10__VI 0x0000000a -#define SQ_R11__VI 0x0000000b -#define SQ_R12__VI 0x0000000c -#define SQ_R13__VI 0x0000000d -#define SQ_R14__VI 0x0000000e -#define SQ_R15__VI 0x0000000f -#define SQ_R2__VI 0x00000002 -#define SQ_R3__VI 0x00000003 -#define SQ_R4__VI 0x00000004 -#define SQ_R5__VI 0x00000005 -#define SQ_R6__VI 0x00000006 -#define SQ_R7__VI 0x00000007 -#define SQ_R8__VI 0x00000008 -#define SQ_R9__VI 0x00000009 -#define SQ_SDWA_BYTE_0__VI 0x00000000 -#define SQ_SDWA_BYTE_1__VI 0x00000001 -#define SQ_SDWA_BYTE_2__VI 0x00000002 -#define SQ_SDWA_BYTE_3__VI 0x00000003 -#define SQ_SDWA_DWORD__VI 0x00000006 -#define SQ_SDWA_UNUSED_PAD__VI 0x00000000 -#define SQ_SDWA_UNUSED_PRESERVE__VI 0x00000002 -#define SQ_SDWA_UNUSED_SEXT__VI 0x00000001 -#define SQ_SDWA_WORD_0__VI 0x00000004 -#define SQ_SDWA_WORD_1__VI 0x00000005 -#define SQ_SMEM_0_DEFAULT__VI 0xcdcd0dcd -#define SQ_SMEM_0_ENCODING_MASK__VI 0xfc000000 -#define SQ_SMEM_0_ENCODING_SHIFT__VI 26 -#define SQ_SMEM_0_ENCODING_SIZE__VI 6 -#define SQ_SMEM_0_GET_ENCODING__VI(sq_smem_0) \ - ((sq_smem_0 & SQ_SMEM_0_ENCODING_MASK) >> SQ_SMEM_0_ENCODING_SHIFT) - -#define SQ_SMEM_0_GET_GLC__VI(sq_smem_0) ((sq_smem_0 & SQ_SMEM_0_GLC_MASK) >> SQ_SMEM_0_GLC_SHIFT) - -#define SQ_SMEM_0_GET_IMM__VI(sq_smem_0) ((sq_smem_0 & SQ_SMEM_0_IMM_MASK) >> SQ_SMEM_0_IMM_SHIFT) - -#define SQ_SMEM_0_GET_OP__VI(sq_smem_0) ((sq_smem_0 & SQ_SMEM_0_OP_MASK) >> SQ_SMEM_0_OP_SHIFT) - -#define SQ_SMEM_0_GET_SBASE__VI(sq_smem_0) \ - ((sq_smem_0 & SQ_SMEM_0_SBASE_MASK) >> SQ_SMEM_0_SBASE_SHIFT) - -#define SQ_SMEM_0_GET_SDATA__VI(sq_smem_0) \ - ((sq_smem_0 & SQ_SMEM_0_SDATA_MASK) >> SQ_SMEM_0_SDATA_SHIFT) - -#define SQ_SMEM_0_GLC_MASK__VI 0x00010000 -#define SQ_SMEM_0_GLC_SHIFT__VI 16 -#define SQ_SMEM_0_GLC_SIZE__VI 1 -#define SQ_SMEM_0_IMM_MASK__VI 0x00020000 -#define SQ_SMEM_0_IMM_SHIFT__VI 17 -#define SQ_SMEM_0_IMM_SIZE__VI 1 -#define SQ_SMEM_0_MASK__VI \ - (SQ_SMEM_0_SBASE_MASK | SQ_SMEM_0_SDATA_MASK | SQ_SMEM_0_GLC_MASK | SQ_SMEM_0_IMM_MASK | \ - SQ_SMEM_0_OP_MASK | SQ_SMEM_0_ENCODING_MASK) - -#define SQ_SMEM_0_OP_MASK__VI 0x03fc0000 -#define SQ_SMEM_0_OP_SHIFT__VI 18 -#define SQ_SMEM_0_OP_SIZE__VI 8 -#define SQ_SMEM_0_REG_SIZE__VI 32 -#define SQ_SMEM_0_SBASE_MASK__VI 0x0000003f -#define SQ_SMEM_0_SBASE_SHIFT__VI 0x00000000 -#define SQ_SMEM_0_SBASE_SIZE__VI 6 -#define SQ_SMEM_0_SDATA_MASK__VI 0x00001fc0 -#define SQ_SMEM_0_SDATA_SHIFT__VI 6 -#define SQ_SMEM_0_SDATA_SIZE__VI 7 -#define SQ_SMEM_0_SET_ENCODING__VI(sq_smem_0_reg, encoding) \ - sq_smem_0_reg = \ - (sq_smem_0_reg & ~SQ_SMEM_0_ENCODING_MASK) | (encoding << SQ_SMEM_0_ENCODING_SHIFT) - -#define SQ_SMEM_0_SET_GLC__VI(sq_smem_0_reg, glc) \ - sq_smem_0_reg = (sq_smem_0_reg & ~SQ_SMEM_0_GLC_MASK) | (glc << SQ_SMEM_0_GLC_SHIFT) - -#define SQ_SMEM_0_SET_IMM__VI(sq_smem_0_reg, imm) \ - sq_smem_0_reg = (sq_smem_0_reg & ~SQ_SMEM_0_IMM_MASK) | (imm << SQ_SMEM_0_IMM_SHIFT) - -#define SQ_SMEM_0_SET_OP__VI(sq_smem_0_reg, op) \ - sq_smem_0_reg = (sq_smem_0_reg & ~SQ_SMEM_0_OP_MASK) | (op << SQ_SMEM_0_OP_SHIFT) - -#define SQ_SMEM_0_SET_SBASE__VI(sq_smem_0_reg, sbase) \ - sq_smem_0_reg = (sq_smem_0_reg & ~SQ_SMEM_0_SBASE_MASK) | (sbase << SQ_SMEM_0_SBASE_SHIFT) - -#define SQ_SMEM_0_SET_SDATA__VI(sq_smem_0_reg, sdata) \ - sq_smem_0_reg = (sq_smem_0_reg & ~SQ_SMEM_0_SDATA_MASK) | (sdata << SQ_SMEM_0_SDATA_SHIFT) - -#define SQ_SMEM_1_DEFAULT__VI 0x000dcdcd -#define SQ_SMEM_1_GET_OFFSET__VI(sq_smem_1) \ - ((sq_smem_1 & SQ_SMEM_1_OFFSET_MASK) >> SQ_SMEM_1_OFFSET_SHIFT) - -#define SQ_SMEM_1_MASK__VI (SQ_SMEM_1_OFFSET_MASK) - -#define SQ_SMEM_1_OFFSET_MASK__VI 0x000fffff -#define SQ_SMEM_1_OFFSET_SHIFT__VI 0x00000000 -#define SQ_SMEM_1_OFFSET_SIZE__VI 20 -#define SQ_SMEM_1_REG_SIZE__VI 32 -#define SQ_SMEM_1_SET_OFFSET__VI(sq_smem_1_reg, offset) \ - sq_smem_1_reg = (sq_smem_1_reg & ~SQ_SMEM_1_OFFSET_MASK) | (offset << SQ_SMEM_1_OFFSET_SHIFT) - -#define SQ_SOP1_GET_ENCODING__VI(sq_sop1) \ - ((sq_sop1 & SQ_SOP1_ENCODING_MASK) >> SQ_SOP1_ENCODING_SHIFT) - -#define SQ_SOP1_GET_OP__VI(sq_sop1) ((sq_sop1 & SQ_SOP1_OP_MASK) >> SQ_SOP1_OP_SHIFT) - -#define SQ_SOP1_GET_SDST__VI(sq_sop1) ((sq_sop1 & SQ_SOP1_SDST_MASK) >> SQ_SOP1_SDST_SHIFT) - -#define SQ_SOP1_GET_SSRC0__VI(sq_sop1) ((sq_sop1 & SQ_SOP1_SSRC0_MASK) >> SQ_SOP1_SSRC0_SHIFT) - -#define SQ_SOP1_MASK__VI \ - (SQ_SOP1_SSRC0_MASK | SQ_SOP1_OP_MASK | SQ_SOP1_SDST_MASK | SQ_SOP1_ENCODING_MASK) - -#define SQ_SOP1_SET_ENCODING__VI(sq_sop1_reg, encoding) \ - sq_sop1_reg = (sq_sop1_reg & ~SQ_SOP1_ENCODING_MASK) | (encoding << SQ_SOP1_ENCODING_SHIFT) - -#define SQ_SOP1_SET_OP__VI(sq_sop1_reg, op) \ - sq_sop1_reg = (sq_sop1_reg & ~SQ_SOP1_OP_MASK) | (op << SQ_SOP1_OP_SHIFT) - -#define SQ_SOP1_SET_SDST__VI(sq_sop1_reg, sdst) \ - sq_sop1_reg = (sq_sop1_reg & ~SQ_SOP1_SDST_MASK) | (sdst << SQ_SOP1_SDST_SHIFT) - -#define SQ_SOP1_SET_SSRC0__VI(sq_sop1_reg, ssrc0) \ - sq_sop1_reg = (sq_sop1_reg & ~SQ_SOP1_SSRC0_MASK) | (ssrc0 << SQ_SOP1_SSRC0_SHIFT) - -#define SQ_SOP2_GET_ENCODING__VI(sq_sop2) \ - ((sq_sop2 & SQ_SOP2_ENCODING_MASK) >> SQ_SOP2_ENCODING_SHIFT) - -#define SQ_SOP2_GET_OP__VI(sq_sop2) ((sq_sop2 & SQ_SOP2_OP_MASK) >> SQ_SOP2_OP_SHIFT) - -#define SQ_SOP2_GET_SDST__VI(sq_sop2) ((sq_sop2 & SQ_SOP2_SDST_MASK) >> SQ_SOP2_SDST_SHIFT) - -#define SQ_SOP2_GET_SSRC0__VI(sq_sop2) ((sq_sop2 & SQ_SOP2_SSRC0_MASK) >> SQ_SOP2_SSRC0_SHIFT) - -#define SQ_SOP2_GET_SSRC1__VI(sq_sop2) ((sq_sop2 & SQ_SOP2_SSRC1_MASK) >> SQ_SOP2_SSRC1_SHIFT) - -#define SQ_SOP2_MASK__VI \ - (SQ_SOP2_SSRC0_MASK | SQ_SOP2_SSRC1_MASK | SQ_SOP2_SDST_MASK | SQ_SOP2_OP_MASK | \ - SQ_SOP2_ENCODING_MASK) - -#define SQ_SOP2_SET_ENCODING__VI(sq_sop2_reg, encoding) \ - sq_sop2_reg = (sq_sop2_reg & ~SQ_SOP2_ENCODING_MASK) | (encoding << SQ_SOP2_ENCODING_SHIFT) - -#define SQ_SOP2_SET_OP__VI(sq_sop2_reg, op) \ - sq_sop2_reg = (sq_sop2_reg & ~SQ_SOP2_OP_MASK) | (op << SQ_SOP2_OP_SHIFT) - -#define SQ_SOP2_SET_SDST__VI(sq_sop2_reg, sdst) \ - sq_sop2_reg = (sq_sop2_reg & ~SQ_SOP2_SDST_MASK) | (sdst << SQ_SOP2_SDST_SHIFT) - -#define SQ_SOP2_SET_SSRC0__VI(sq_sop2_reg, ssrc0) \ - sq_sop2_reg = (sq_sop2_reg & ~SQ_SOP2_SSRC0_MASK) | (ssrc0 << SQ_SOP2_SSRC0_SHIFT) - -#define SQ_SOP2_SET_SSRC1__VI(sq_sop2_reg, ssrc1) \ - sq_sop2_reg = (sq_sop2_reg & ~SQ_SOP2_SSRC1_MASK) | (ssrc1 << SQ_SOP2_SSRC1_SHIFT) - -#define SQ_SOPC_GET_ENCODING__VI(sq_sopc) \ - ((sq_sopc & SQ_SOPC_ENCODING_MASK) >> SQ_SOPC_ENCODING_SHIFT) - -#define SQ_SOPC_GET_OP__VI(sq_sopc) ((sq_sopc & SQ_SOPC_OP_MASK) >> SQ_SOPC_OP_SHIFT) - -#define SQ_SOPC_GET_SSRC0__VI(sq_sopc) ((sq_sopc & SQ_SOPC_SSRC0_MASK) >> SQ_SOPC_SSRC0_SHIFT) - -#define SQ_SOPC_GET_SSRC1__VI(sq_sopc) ((sq_sopc & SQ_SOPC_SSRC1_MASK) >> SQ_SOPC_SSRC1_SHIFT) - -#define SQ_SOPC_MASK__VI \ - (SQ_SOPC_SSRC0_MASK | SQ_SOPC_SSRC1_MASK | SQ_SOPC_OP_MASK | SQ_SOPC_ENCODING_MASK) - -#define SQ_SOPC_SET_ENCODING__VI(sq_sopc_reg, encoding) \ - sq_sopc_reg = (sq_sopc_reg & ~SQ_SOPC_ENCODING_MASK) | (encoding << SQ_SOPC_ENCODING_SHIFT) - -#define SQ_SOPC_SET_OP__VI(sq_sopc_reg, op) \ - sq_sopc_reg = (sq_sopc_reg & ~SQ_SOPC_OP_MASK) | (op << SQ_SOPC_OP_SHIFT) - -#define SQ_SOPC_SET_SSRC0__VI(sq_sopc_reg, ssrc0) \ - sq_sopc_reg = (sq_sopc_reg & ~SQ_SOPC_SSRC0_MASK) | (ssrc0 << SQ_SOPC_SSRC0_SHIFT) - -#define SQ_SOPC_SET_SSRC1__VI(sq_sopc_reg, ssrc1) \ - sq_sopc_reg = (sq_sopc_reg & ~SQ_SOPC_SSRC1_MASK) | (ssrc1 << SQ_SOPC_SSRC1_SHIFT) - -#define SQ_SOPK_GET_ENCODING__VI(sq_sopk) \ - ((sq_sopk & SQ_SOPK_ENCODING_MASK) >> SQ_SOPK_ENCODING_SHIFT) - -#define SQ_SOPK_GET_OP__VI(sq_sopk) ((sq_sopk & SQ_SOPK_OP_MASK) >> SQ_SOPK_OP_SHIFT) - -#define SQ_SOPK_GET_SDST__VI(sq_sopk) ((sq_sopk & SQ_SOPK_SDST_MASK) >> SQ_SOPK_SDST_SHIFT) - -#define SQ_SOPK_GET_SIMM16__VI(sq_sopk) ((sq_sopk & SQ_SOPK_SIMM16_MASK) >> SQ_SOPK_SIMM16_SHIFT) - -#define SQ_SOPK_MASK__VI \ - (SQ_SOPK_SIMM16_MASK | SQ_SOPK_SDST_MASK | SQ_SOPK_OP_MASK | SQ_SOPK_ENCODING_MASK) - -#define SQ_SOPK_SET_ENCODING__VI(sq_sopk_reg, encoding) \ - sq_sopk_reg = (sq_sopk_reg & ~SQ_SOPK_ENCODING_MASK) | (encoding << SQ_SOPK_ENCODING_SHIFT) - -#define SQ_SOPK_SET_OP__VI(sq_sopk_reg, op) \ - sq_sopk_reg = (sq_sopk_reg & ~SQ_SOPK_OP_MASK) | (op << SQ_SOPK_OP_SHIFT) - -#define SQ_SOPK_SET_SDST__VI(sq_sopk_reg, sdst) \ - sq_sopk_reg = (sq_sopk_reg & ~SQ_SOPK_SDST_MASK) | (sdst << SQ_SOPK_SDST_SHIFT) - -#define SQ_SOPK_SET_SIMM16__VI(sq_sopk_reg, simm16) \ - sq_sopk_reg = (sq_sopk_reg & ~SQ_SOPK_SIMM16_MASK) | (simm16 << SQ_SOPK_SIMM16_SHIFT) - -#define SQ_SOPP_GET_ENCODING__VI(sq_sopp) \ - ((sq_sopp & SQ_SOPP_ENCODING_MASK) >> SQ_SOPP_ENCODING_SHIFT) - -#define SQ_SOPP_GET_OP__VI(sq_sopp) ((sq_sopp & SQ_SOPP_OP_MASK) >> SQ_SOPP_OP_SHIFT) - -#define SQ_SOPP_GET_SIMM16__VI(sq_sopp) ((sq_sopp & SQ_SOPP_SIMM16_MASK) >> SQ_SOPP_SIMM16_SHIFT) - -#define SQ_SOPP_MASK__VI (SQ_SOPP_SIMM16_MASK | SQ_SOPP_OP_MASK | SQ_SOPP_ENCODING_MASK) - -#define SQ_SOPP_SET_ENCODING__VI(sq_sopp_reg, encoding) \ - sq_sopp_reg = (sq_sopp_reg & ~SQ_SOPP_ENCODING_MASK) | (encoding << SQ_SOPP_ENCODING_SHIFT) - -#define SQ_SOPP_SET_OP__VI(sq_sopp_reg, op) \ - sq_sopp_reg = (sq_sopp_reg & ~SQ_SOPP_OP_MASK) | (op << SQ_SOPP_OP_SHIFT) - -#define SQ_SOPP_SET_SIMM16__VI(sq_sopp_reg, simm16) \ - sq_sopp_reg = (sq_sopp_reg & ~SQ_SOPP_SIMM16_MASK) | (simm16 << SQ_SOPP_SIMM16_SHIFT) - -#define SQ_SRC_DPP__VI 0x000000fa -#define SQ_SRC_INV_2PI__VI 0x000000f8 -#define SQ_SRC_SDWA__VI 0x000000f9 -#define SQ_S_ABSDIFF_I32__SI__CI 0x0000002c -#define SQ_S_ABSDIFF_I32__VI 0x0000002a -#define SQ_S_ABS_I32__SI__CI 0x00000034 -#define SQ_S_ABS_I32__VI 0x00000030 -#define SQ_S_ADDK_I32__SI__CI 0x0000000f -#define SQ_S_ADDK_I32__VI 0x0000000e -#define SQ_S_ANDN2_B32__SI__CI 0x00000014 -#define SQ_S_ANDN2_B32__VI 0x00000012 -#define SQ_S_ANDN2_B64__SI__CI 0x00000015 -#define SQ_S_ANDN2_B64__VI 0x00000013 -#define SQ_S_ANDN2_SAVEEXEC_B64__SI__CI 0x00000027 -#define SQ_S_ANDN2_SAVEEXEC_B64__VI 0x00000023 -#define SQ_S_AND_B32__SI__CI 0x0000000e -#define SQ_S_AND_B32__VI 0x0000000c -#define SQ_S_AND_B64__SI__CI 0x0000000f -#define SQ_S_AND_B64__VI 0x0000000d -#define SQ_S_AND_SAVEEXEC_B64__SI__CI 0x00000024 -#define SQ_S_AND_SAVEEXEC_B64__VI 0x00000020 -#define SQ_S_ASHR_I32__SI__CI 0x00000022 -#define SQ_S_ASHR_I32__VI 0x00000020 -#define SQ_S_ASHR_I64__SI__CI 0x00000023 -#define SQ_S_ASHR_I64__VI 0x00000021 -#define SQ_S_ATC_PROBE__VI 0x00000026 -#define SQ_S_ATC_PROBE_BUFFER__VI 0x00000027 -#define SQ_S_BCNT0_I32_B32__SI__CI 0x0000000d -#define SQ_S_BCNT0_I32_B32__VI 0x0000000a -#define SQ_S_BCNT0_I32_B64__SI__CI 0x0000000e -#define SQ_S_BCNT0_I32_B64__VI 0x0000000b -#define SQ_S_BCNT1_I32_B32__SI__CI 0x0000000f -#define SQ_S_BCNT1_I32_B32__VI 0x0000000c -#define SQ_S_BCNT1_I32_B64__SI__CI 0x00000010 -#define SQ_S_BCNT1_I32_B64__VI 0x0000000d -#define SQ_S_BFE_I32__SI__CI 0x00000028 -#define SQ_S_BFE_I32__VI 0x00000026 -#define SQ_S_BFE_I64__SI__CI 0x0000002a -#define SQ_S_BFE_I64__VI 0x00000028 -#define SQ_S_BFE_U32__SI__CI 0x00000027 -#define SQ_S_BFE_U32__VI 0x00000025 -#define SQ_S_BFE_U64__SI__CI 0x00000029 -#define SQ_S_BFE_U64__VI 0x00000027 -#define SQ_S_BFM_B32__SI__CI 0x00000024 -#define SQ_S_BFM_B32__VI 0x00000022 -#define SQ_S_BFM_B64__SI__CI 0x00000025 -#define SQ_S_BFM_B64__VI 0x00000023 -#define SQ_S_BITSET0_B32__SI__CI 0x0000001b -#define SQ_S_BITSET0_B32__VI 0x00000018 -#define SQ_S_BITSET0_B64__SI__CI 0x0000001c -#define SQ_S_BITSET0_B64__VI 0x00000019 -#define SQ_S_BITSET1_B32__SI__CI 0x0000001d -#define SQ_S_BITSET1_B32__VI 0x0000001a -#define SQ_S_BITSET1_B64__SI__CI 0x0000001e -#define SQ_S_BITSET1_B64__VI 0x0000001b -#define SQ_S_BREV_B32__SI__CI 0x0000000b -#define SQ_S_BREV_B32__VI 0x00000008 -#define SQ_S_BREV_B64__SI__CI 0x0000000c -#define SQ_S_BREV_B64__VI 0x00000009 -#define SQ_S_BUFFER_ATOMIC_ADD__VI 0x00000042 -#define SQ_S_BUFFER_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_S_BUFFER_ATOMIC_AND__VI 0x00000048 -#define SQ_S_BUFFER_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_S_BUFFER_ATOMIC_DEC__VI 0x0000004c -#define SQ_S_BUFFER_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_S_BUFFER_ATOMIC_INC__VI 0x0000004b -#define SQ_S_BUFFER_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_S_BUFFER_ATOMIC_OR__VI 0x00000049 -#define SQ_S_BUFFER_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_S_BUFFER_ATOMIC_SMAX__VI 0x00000046 -#define SQ_S_BUFFER_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_S_BUFFER_ATOMIC_SMIN__VI 0x00000044 -#define SQ_S_BUFFER_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_S_BUFFER_ATOMIC_SUB__VI 0x00000043 -#define SQ_S_BUFFER_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_S_BUFFER_ATOMIC_SWAP__VI 0x00000040 -#define SQ_S_BUFFER_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_S_BUFFER_ATOMIC_UMAX__VI 0x00000047 -#define SQ_S_BUFFER_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_S_BUFFER_ATOMIC_UMIN__VI 0x00000045 -#define SQ_S_BUFFER_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_S_BUFFER_ATOMIC_XOR__VI 0x0000004a -#define SQ_S_BUFFER_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_S_BUFFER_STORE_DWORD__VI 0x00000018 -#define SQ_S_BUFFER_STORE_DWORDX2__VI 0x00000019 -#define SQ_S_BUFFER_STORE_DWORDX4__VI 0x0000001a -#define SQ_S_CBRANCH_G_FORK__SI__CI 0x0000002b -#define SQ_S_CBRANCH_G_FORK__VI 0x00000029 -#define SQ_S_CBRANCH_I_FORK__SI__CI 0x00000011 -#define SQ_S_CBRANCH_I_FORK__VI 0x00000010 -#define SQ_S_CBRANCH_JOIN__SI__CI 0x00000032 -#define SQ_S_CBRANCH_JOIN__VI 0x0000002e -#define SQ_S_CMOVK_I32__SI__CI 0x00000002 -#define SQ_S_CMOVK_I32__VI 0x00000001 -#define SQ_S_CMOV_B32__SI__CI 0x00000005 -#define SQ_S_CMOV_B32__VI 0x00000002 -#define SQ_S_CMOV_B64__SI__CI 0x00000006 -#define SQ_S_CMOV_B64__VI 0x00000003 -#define SQ_S_CMPK_EQ_I32__SI__CI 0x00000003 -#define SQ_S_CMPK_EQ_I32__VI 0x00000002 -#define SQ_S_CMPK_EQ_U32__SI__CI 0x00000009 -#define SQ_S_CMPK_EQ_U32__VI 0x00000008 -#define SQ_S_CMPK_GE_I32__SI__CI 0x00000006 -#define SQ_S_CMPK_GE_I32__VI 0x00000005 -#define SQ_S_CMPK_GE_U32__SI__CI 0x0000000c -#define SQ_S_CMPK_GE_U32__VI 0x0000000b -#define SQ_S_CMPK_GT_I32__SI__CI 0x00000005 -#define SQ_S_CMPK_GT_I32__VI 0x00000004 -#define SQ_S_CMPK_GT_U32__SI__CI 0x0000000b -#define SQ_S_CMPK_GT_U32__VI 0x0000000a -#define SQ_S_CMPK_LE_I32__SI__CI 0x00000008 -#define SQ_S_CMPK_LE_I32__VI 0x00000007 -#define SQ_S_CMPK_LE_U32__SI__CI 0x0000000e -#define SQ_S_CMPK_LE_U32__VI 0x0000000d -#define SQ_S_CMPK_LG_I32__SI__CI 0x00000004 -#define SQ_S_CMPK_LG_I32__VI 0x00000003 -#define SQ_S_CMPK_LG_U32__SI__CI 0x0000000a -#define SQ_S_CMPK_LG_U32__VI 0x00000009 -#define SQ_S_CMPK_LT_I32__SI__CI 0x00000007 -#define SQ_S_CMPK_LT_I32__VI 0x00000006 -#define SQ_S_CMPK_LT_U32__SI__CI 0x0000000d -#define SQ_S_CMPK_LT_U32__VI 0x0000000c -#define SQ_S_CMP_EQ_U64__VI 0x00000012 -#define SQ_S_CMP_LG_U64__VI 0x00000013 -#define SQ_S_DCACHE_INV__SI__CI 0x0000001f -#define SQ_S_DCACHE_INV__VI 0x00000020 -#define SQ_S_DCACHE_INV_VOL__VI 0x00000022 -#define SQ_S_DCACHE_WB__VI 0x00000021 -#define SQ_S_DCACHE_WB_VOL__VI 0x00000023 -#define SQ_S_ENDPGM_SAVED__VI 0x0000001b -#define SQ_S_FF0_I32_B32__SI__CI 0x00000011 -#define SQ_S_FF0_I32_B32__VI 0x0000000e -#define SQ_S_FF0_I32_B64__SI__CI 0x00000012 -#define SQ_S_FF0_I32_B64__VI 0x0000000f -#define SQ_S_FF1_I32_B32__SI__CI 0x00000013 -#define SQ_S_FF1_I32_B32__VI 0x00000010 -#define SQ_S_FF1_I32_B64__SI__CI 0x00000014 -#define SQ_S_FF1_I32_B64__VI 0x00000011 -#define SQ_S_FLBIT_I32__SI__CI 0x00000017 -#define SQ_S_FLBIT_I32__VI 0x00000014 -#define SQ_S_FLBIT_I32_B32__SI__CI 0x00000015 -#define SQ_S_FLBIT_I32_B32__VI 0x00000012 -#define SQ_S_FLBIT_I32_B64__SI__CI 0x00000016 -#define SQ_S_FLBIT_I32_B64__VI 0x00000013 -#define SQ_S_FLBIT_I32_I64__SI__CI 0x00000018 -#define SQ_S_FLBIT_I32_I64__VI 0x00000015 -#define SQ_S_GETPC_B64__SI__CI 0x0000001f -#define SQ_S_GETPC_B64__VI 0x0000001c -#define SQ_S_GETREG_B32__SI__CI 0x00000012 -#define SQ_S_GETREG_B32__VI 0x00000011 -#define SQ_S_GETREG_REGRD_B32__SI__CI 0x00000014 -#define SQ_S_GETREG_REGRD_B32__VI 0x00000013 -#define SQ_S_LSHL_B32__SI__CI 0x0000001e -#define SQ_S_LSHL_B32__VI 0x0000001c -#define SQ_S_LSHL_B64__SI__CI 0x0000001f -#define SQ_S_LSHL_B64__VI 0x0000001d -#define SQ_S_LSHR_B32__SI__CI 0x00000020 -#define SQ_S_LSHR_B32__VI 0x0000001e -#define SQ_S_LSHR_B64__SI__CI 0x00000021 -#define SQ_S_LSHR_B64__VI 0x0000001f -#define SQ_S_MEMREALTIME__VI 0x00000025 -#define SQ_S_MEMTIME__SI__CI 0x0000001e -#define SQ_S_MEMTIME__VI 0x00000024 -#define SQ_S_MOVRELD_B32__SI__CI 0x00000030 -#define SQ_S_MOVRELD_B32__VI 0x0000002c -#define SQ_S_MOVRELD_B64__SI__CI 0x00000031 -#define SQ_S_MOVRELD_B64__VI 0x0000002d -#define SQ_S_MOVRELS_B32__SI__CI 0x0000002e -#define SQ_S_MOVRELS_B32__VI 0x0000002a -#define SQ_S_MOVRELS_B64__SI__CI 0x0000002f -#define SQ_S_MOVRELS_B64__VI 0x0000002b -#define SQ_S_MOV_B32__SI__CI 0x00000003 -#define SQ_S_MOV_B32__VI 0x00000000 -#define SQ_S_MOV_B64__SI__CI 0x00000004 -#define SQ_S_MOV_B64__VI 0x00000001 -#define SQ_S_MOV_FED_B32__SI__CI 0x00000035 -#define SQ_S_MOV_FED_B32__VI 0x00000031 -#define SQ_S_MOV_REGRD_B32__SI__CI 0x00000033 -#define SQ_S_MOV_REGRD_B32__VI 0x0000002f -#define SQ_S_MULK_I32__SI__CI 0x00000010 -#define SQ_S_MULK_I32__VI 0x0000000f -#define SQ_S_MUL_I32__SI__CI 0x00000026 -#define SQ_S_MUL_I32__VI 0x00000024 -#define SQ_S_NAND_B32__SI__CI 0x00000018 -#define SQ_S_NAND_B32__VI 0x00000016 -#define SQ_S_NAND_B64__SI__CI 0x00000019 -#define SQ_S_NAND_B64__VI 0x00000017 -#define SQ_S_NAND_SAVEEXEC_B64__SI__CI 0x00000029 -#define SQ_S_NAND_SAVEEXEC_B64__VI 0x00000025 -#define SQ_S_NOR_B32__SI__CI 0x0000001a -#define SQ_S_NOR_B32__VI 0x00000018 -#define SQ_S_NOR_B64__SI__CI 0x0000001b -#define SQ_S_NOR_B64__VI 0x00000019 -#define SQ_S_NOR_SAVEEXEC_B64__SI__CI 0x0000002a -#define SQ_S_NOR_SAVEEXEC_B64__VI 0x00000026 -#define SQ_S_NOT_B32__SI__CI 0x00000007 -#define SQ_S_NOT_B32__VI 0x00000004 -#define SQ_S_NOT_B64__SI__CI 0x00000008 -#define SQ_S_NOT_B64__VI 0x00000005 -#define SQ_S_ORN2_B32__SI__CI 0x00000016 -#define SQ_S_ORN2_B32__VI 0x00000014 -#define SQ_S_ORN2_B64__SI__CI 0x00000017 -#define SQ_S_ORN2_B64__VI 0x00000015 -#define SQ_S_ORN2_SAVEEXEC_B64__SI__CI 0x00000028 -#define SQ_S_ORN2_SAVEEXEC_B64__VI 0x00000024 -#define SQ_S_OR_B32__SI__CI 0x00000010 -#define SQ_S_OR_B32__VI 0x0000000e -#define SQ_S_OR_B64__SI__CI 0x00000011 -#define SQ_S_OR_B64__VI 0x0000000f -#define SQ_S_OR_SAVEEXEC_B64__SI__CI 0x00000025 -#define SQ_S_OR_SAVEEXEC_B64__VI 0x00000021 -#define SQ_S_QUADMASK_B32__SI__CI 0x0000002c -#define SQ_S_QUADMASK_B32__VI 0x00000028 -#define SQ_S_QUADMASK_B64__SI__CI 0x0000002d -#define SQ_S_QUADMASK_B64__VI 0x00000029 -#define SQ_S_RFE_B64__SI__CI 0x00000022 -#define SQ_S_RFE_B64__VI 0x0000001f -#define SQ_S_RFE_RESTORE_B64__VI 0x0000002b -#define SQ_S_SETPC_B64__SI__CI 0x00000020 -#define SQ_S_SETPC_B64__VI 0x0000001d -#define SQ_S_SETREG_B32__SI__CI 0x00000013 -#define SQ_S_SETREG_B32__VI 0x00000012 -#define SQ_S_SETREG_IMM32_B32__SI__CI 0x00000015 -#define SQ_S_SETREG_IMM32_B32__VI 0x00000014 -#define SQ_S_SET_GPR_IDX_IDX__VI 0x00000032 -#define SQ_S_SET_GPR_IDX_MODE__VI 0x0000001d -#define SQ_S_SET_GPR_IDX_OFF__VI 0x0000001c -#define SQ_S_SET_GPR_IDX_ON__VI 0x00000011 -#define SQ_S_SEXT_I32_I16__SI__CI 0x0000001a -#define SQ_S_SEXT_I32_I16__VI 0x00000017 -#define SQ_S_SEXT_I32_I8__SI__CI 0x00000019 -#define SQ_S_SEXT_I32_I8__VI 0x00000016 -#define SQ_S_STORE_DWORD__VI 0x00000010 -#define SQ_S_STORE_DWORDX2__VI 0x00000011 -#define SQ_S_STORE_DWORDX4__VI 0x00000012 -#define SQ_S_SWAPPC_B64__SI__CI 0x00000021 -#define SQ_S_SWAPPC_B64__VI 0x0000001e -#define SQ_S_WAKEUP__VI 0x00000003 -#define SQ_S_WQM_B32__SI__CI 0x00000009 -#define SQ_S_WQM_B32__VI 0x00000006 -#define SQ_S_WQM_B64__SI__CI 0x0000000a -#define SQ_S_WQM_B64__VI 0x00000007 -#define SQ_S_XNOR_B32__SI__CI 0x0000001c -#define SQ_S_XNOR_B32__VI 0x0000001a -#define SQ_S_XNOR_B64__SI__CI 0x0000001d -#define SQ_S_XNOR_B64__VI 0x0000001b -#define SQ_S_XNOR_SAVEEXEC_B64__SI__CI 0x0000002b -#define SQ_S_XNOR_SAVEEXEC_B64__VI 0x00000027 -#define SQ_S_XOR_B32__SI__CI 0x00000012 -#define SQ_S_XOR_B32__VI 0x00000010 -#define SQ_S_XOR_B64__SI__CI 0x00000013 -#define SQ_S_XOR_B64__VI 0x00000011 -#define SQ_S_XOR_SAVEEXEC_B64__SI__CI 0x00000026 -#define SQ_S_XOR_SAVEEXEC_B64__VI 0x00000022 -#define SQ_TBUFFER_LOAD_FORMAT_D16_X__VI 0x00000008 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XY__VI 0x00000009 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ__VI 0x0000000a -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW__VI 0x0000000b -#define SQ_TBUFFER_STORE_FORMAT_D16_X__VI 0x0000000c -#define SQ_TBUFFER_STORE_FORMAT_D16_XY__VI 0x0000000d -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ__VI 0x0000000e -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW__VI 0x0000000f -#define SQ_VINTRP_GET_ATTR__VI(sq_vintrp) \ - ((sq_vintrp & SQ_VINTRP_ATTR_MASK) >> SQ_VINTRP_ATTR_SHIFT) - -#define SQ_VINTRP_GET_ATTRCHAN__VI(sq_vintrp) \ - ((sq_vintrp & SQ_VINTRP_ATTRCHAN_MASK) >> SQ_VINTRP_ATTRCHAN_SHIFT) - -#define SQ_VINTRP_GET_ENCODING__VI(sq_vintrp) \ - ((sq_vintrp & SQ_VINTRP_ENCODING_MASK) >> SQ_VINTRP_ENCODING_SHIFT) - -#define SQ_VINTRP_GET_OP__VI(sq_vintrp) ((sq_vintrp & SQ_VINTRP_OP_MASK) >> SQ_VINTRP_OP_SHIFT) - -#define SQ_VINTRP_GET_VDST__VI(sq_vintrp) \ - ((sq_vintrp & SQ_VINTRP_VDST_MASK) >> SQ_VINTRP_VDST_SHIFT) - -#define SQ_VINTRP_GET_VSRC__VI(sq_vintrp) \ - ((sq_vintrp & SQ_VINTRP_VSRC_MASK) >> SQ_VINTRP_VSRC_SHIFT) - -#define SQ_VINTRP_MASK__VI \ - (SQ_VINTRP_VSRC_MASK | SQ_VINTRP_ATTRCHAN_MASK | SQ_VINTRP_ATTR_MASK | SQ_VINTRP_OP_MASK | \ - SQ_VINTRP_VDST_MASK | SQ_VINTRP_ENCODING_MASK) - -#define SQ_VINTRP_SET_ATTR__VI(sq_vintrp_reg, attr) \ - sq_vintrp_reg = (sq_vintrp_reg & ~SQ_VINTRP_ATTR_MASK) | (attr << SQ_VINTRP_ATTR_SHIFT) - -#define SQ_VINTRP_SET_ATTRCHAN__VI(sq_vintrp_reg, attrchan) \ - sq_vintrp_reg = \ - (sq_vintrp_reg & ~SQ_VINTRP_ATTRCHAN_MASK) | (attrchan << SQ_VINTRP_ATTRCHAN_SHIFT) - -#define SQ_VINTRP_SET_ENCODING__VI(sq_vintrp_reg, encoding) \ - sq_vintrp_reg = \ - (sq_vintrp_reg & ~SQ_VINTRP_ENCODING_MASK) | (encoding << SQ_VINTRP_ENCODING_SHIFT) - -#define SQ_VINTRP_SET_OP__VI(sq_vintrp_reg, op) \ - sq_vintrp_reg = (sq_vintrp_reg & ~SQ_VINTRP_OP_MASK) | (op << SQ_VINTRP_OP_SHIFT) - -#define SQ_VINTRP_SET_VDST__VI(sq_vintrp_reg, vdst) \ - sq_vintrp_reg = (sq_vintrp_reg & ~SQ_VINTRP_VDST_MASK) | (vdst << SQ_VINTRP_VDST_SHIFT) - -#define SQ_VINTRP_SET_VSRC__VI(sq_vintrp_reg, vsrc) \ - sq_vintrp_reg = (sq_vintrp_reg & ~SQ_VINTRP_VSRC_MASK) | (vsrc << SQ_VINTRP_VSRC_SHIFT) - -#define SQ_VOP1_GET_ENCODING__VI(sq_vop1) \ - ((sq_vop1 & SQ_VOP1_ENCODING_MASK) >> SQ_VOP1_ENCODING_SHIFT) - -#define SQ_VOP1_GET_OP__VI(sq_vop1) ((sq_vop1 & SQ_VOP1_OP_MASK) >> SQ_VOP1_OP_SHIFT) - -#define SQ_VOP1_GET_SRC0__VI(sq_vop1) ((sq_vop1 & SQ_VOP1_SRC0_MASK) >> SQ_VOP1_SRC0_SHIFT) - -#define SQ_VOP1_GET_VDST__VI(sq_vop1) ((sq_vop1 & SQ_VOP1_VDST_MASK) >> SQ_VOP1_VDST_SHIFT) - -#define SQ_VOP1_MASK__VI \ - (SQ_VOP1_SRC0_MASK | SQ_VOP1_OP_MASK | SQ_VOP1_VDST_MASK | SQ_VOP1_ENCODING_MASK) - -#define SQ_VOP1_SET_ENCODING__VI(sq_vop1_reg, encoding) \ - sq_vop1_reg = (sq_vop1_reg & ~SQ_VOP1_ENCODING_MASK) | (encoding << SQ_VOP1_ENCODING_SHIFT) - -#define SQ_VOP1_SET_OP__VI(sq_vop1_reg, op) \ - sq_vop1_reg = (sq_vop1_reg & ~SQ_VOP1_OP_MASK) | (op << SQ_VOP1_OP_SHIFT) - -#define SQ_VOP1_SET_SRC0__VI(sq_vop1_reg, src0) \ - sq_vop1_reg = (sq_vop1_reg & ~SQ_VOP1_SRC0_MASK) | (src0 << SQ_VOP1_SRC0_SHIFT) - -#define SQ_VOP1_SET_VDST__VI(sq_vop1_reg, vdst) \ - sq_vop1_reg = (sq_vop1_reg & ~SQ_VOP1_VDST_MASK) | (vdst << SQ_VOP1_VDST_SHIFT) - -#define SQ_VOP2_GET_ENCODING__VI(sq_vop2) \ - ((sq_vop2 & SQ_VOP2_ENCODING_MASK) >> SQ_VOP2_ENCODING_SHIFT) - -#define SQ_VOP2_GET_OP__VI(sq_vop2) ((sq_vop2 & SQ_VOP2_OP_MASK) >> SQ_VOP2_OP_SHIFT) - -#define SQ_VOP2_GET_SRC0__VI(sq_vop2) ((sq_vop2 & SQ_VOP2_SRC0_MASK) >> SQ_VOP2_SRC0_SHIFT) - -#define SQ_VOP2_GET_VDST__VI(sq_vop2) ((sq_vop2 & SQ_VOP2_VDST_MASK) >> SQ_VOP2_VDST_SHIFT) - -#define SQ_VOP2_GET_VSRC1__VI(sq_vop2) ((sq_vop2 & SQ_VOP2_VSRC1_MASK) >> SQ_VOP2_VSRC1_SHIFT) - -#define SQ_VOP2_MASK__VI \ - (SQ_VOP2_SRC0_MASK | SQ_VOP2_VSRC1_MASK | SQ_VOP2_VDST_MASK | SQ_VOP2_OP_MASK | \ - SQ_VOP2_ENCODING_MASK) - -#define SQ_VOP2_SET_ENCODING__VI(sq_vop2_reg, encoding) \ - sq_vop2_reg = (sq_vop2_reg & ~SQ_VOP2_ENCODING_MASK) | (encoding << SQ_VOP2_ENCODING_SHIFT) - -#define SQ_VOP2_SET_OP__VI(sq_vop2_reg, op) \ - sq_vop2_reg = (sq_vop2_reg & ~SQ_VOP2_OP_MASK) | (op << SQ_VOP2_OP_SHIFT) - -#define SQ_VOP2_SET_SRC0__VI(sq_vop2_reg, src0) \ - sq_vop2_reg = (sq_vop2_reg & ~SQ_VOP2_SRC0_MASK) | (src0 << SQ_VOP2_SRC0_SHIFT) - -#define SQ_VOP2_SET_VDST__VI(sq_vop2_reg, vdst) \ - sq_vop2_reg = (sq_vop2_reg & ~SQ_VOP2_VDST_MASK) | (vdst << SQ_VOP2_VDST_SHIFT) - -#define SQ_VOP2_SET_VSRC1__VI(sq_vop2_reg, vsrc1) \ - sq_vop2_reg = (sq_vop2_reg & ~SQ_VOP2_VSRC1_MASK) | (vsrc1 << SQ_VOP2_VSRC1_SHIFT) - -#define SQ_VOP3_0_CLAMP_MASK__SI__CI 0x00000800 -#define SQ_VOP3_0_CLAMP_MASK__VI 0x00008000 -#define SQ_VOP3_0_CLAMP_SHIFT__SI__CI 11 -#define SQ_VOP3_0_CLAMP_SHIFT__VI 15 -#define SQ_VOP3_0_DEFAULT__SI__CI 0xcdcc0dcd -#define SQ_VOP3_0_DEFAULT__VI 0xcdcd85cd -#define SQ_VOP3_0_GET_ABS__VI(sq_vop3_0) ((sq_vop3_0 & SQ_VOP3_0_ABS_MASK) >> SQ_VOP3_0_ABS_SHIFT) - -#define SQ_VOP3_0_GET_CLAMP__VI(sq_vop3_0) \ - ((sq_vop3_0 & SQ_VOP3_0_CLAMP_MASK) >> SQ_VOP3_0_CLAMP_SHIFT) - -#define SQ_VOP3_0_GET_ENCODING__VI(sq_vop3_0) \ - ((sq_vop3_0 & SQ_VOP3_0_ENCODING_MASK) >> SQ_VOP3_0_ENCODING_SHIFT) - -#define SQ_VOP3_0_GET_OP__VI(sq_vop3_0) ((sq_vop3_0 & SQ_VOP3_0_OP_MASK) >> SQ_VOP3_0_OP_SHIFT) - -#define SQ_VOP3_0_GET_VDST__VI(sq_vop3_0) \ - ((sq_vop3_0 & SQ_VOP3_0_VDST_MASK) >> SQ_VOP3_0_VDST_SHIFT) - -#define SQ_VOP3_0_MASK__VI \ - (SQ_VOP3_0_VDST_MASK | SQ_VOP3_0_ABS_MASK | SQ_VOP3_0_CLAMP_MASK | SQ_VOP3_0_OP_MASK | \ - SQ_VOP3_0_ENCODING_MASK) - -#define SQ_VOP3_0_OP_MASK__SI__CI 0x03fe0000 -#define SQ_VOP3_0_OP_MASK__VI 0x03ff0000 -#define SQ_VOP3_0_OP_SHIFT__SI__CI 17 -#define SQ_VOP3_0_OP_SHIFT__VI 16 -#define SQ_VOP3_0_OP_SIZE__SI__CI 9 -#define SQ_VOP3_0_OP_SIZE__VI 10 -#define SQ_VOP3_0_SDST_ENC_CLAMP_MASK__VI 0x00008000 -#define SQ_VOP3_0_SDST_ENC_CLAMP_SHIFT__VI 15 -#define SQ_VOP3_0_SDST_ENC_CLAMP_SIZE__VI 1 -#define SQ_VOP3_0_SDST_ENC_DEFAULT__SI__CI 0xcdcc4dcd -#define SQ_VOP3_0_SDST_ENC_DEFAULT__VI 0xcdcdcdcd -#define SQ_VOP3_0_SDST_ENC_GET_CLAMP__VI(sq_vop3_0_sdst_enc) \ - ((sq_vop3_0_sdst_enc & SQ_VOP3_0_SDST_ENC_CLAMP_MASK) >> SQ_VOP3_0_SDST_ENC_CLAMP_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_GET_ENCODING__VI(sq_vop3_0_sdst_enc) \ - ((sq_vop3_0_sdst_enc & SQ_VOP3_0_SDST_ENC_ENCODING_MASK) >> SQ_VOP3_0_SDST_ENC_ENCODING_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_GET_OP__VI(sq_vop3_0_sdst_enc) \ - ((sq_vop3_0_sdst_enc & SQ_VOP3_0_SDST_ENC_OP_MASK) >> SQ_VOP3_0_SDST_ENC_OP_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_GET_SDST__VI(sq_vop3_0_sdst_enc) \ - ((sq_vop3_0_sdst_enc & SQ_VOP3_0_SDST_ENC_SDST_MASK) >> SQ_VOP3_0_SDST_ENC_SDST_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_GET_VDST__VI(sq_vop3_0_sdst_enc) \ - ((sq_vop3_0_sdst_enc & SQ_VOP3_0_SDST_ENC_VDST_MASK) >> SQ_VOP3_0_SDST_ENC_VDST_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_MASK__VI \ - (SQ_VOP3_0_SDST_ENC_VDST_MASK | SQ_VOP3_0_SDST_ENC_SDST_MASK | SQ_VOP3_0_SDST_ENC_CLAMP_MASK | \ - SQ_VOP3_0_SDST_ENC_OP_MASK | SQ_VOP3_0_SDST_ENC_ENCODING_MASK) - -#define SQ_VOP3_0_SDST_ENC_OP_MASK__SI__CI 0x03fe0000 -#define SQ_VOP3_0_SDST_ENC_OP_MASK__VI 0x03ff0000 -#define SQ_VOP3_0_SDST_ENC_OP_SHIFT__SI__CI 17 -#define SQ_VOP3_0_SDST_ENC_OP_SHIFT__VI 16 -#define SQ_VOP3_0_SDST_ENC_OP_SIZE__SI__CI 9 -#define SQ_VOP3_0_SDST_ENC_OP_SIZE__VI 10 -#define SQ_VOP3_0_SDST_ENC_SET_CLAMP__VI(sq_vop3_0_sdst_enc_reg, clamp) \ - sq_vop3_0_sdst_enc_reg = (sq_vop3_0_sdst_enc_reg & ~SQ_VOP3_0_SDST_ENC_CLAMP_MASK) | \ - (clamp << SQ_VOP3_0_SDST_ENC_CLAMP_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_SET_ENCODING__VI(sq_vop3_0_sdst_enc_reg, encoding) \ - sq_vop3_0_sdst_enc_reg = (sq_vop3_0_sdst_enc_reg & ~SQ_VOP3_0_SDST_ENC_ENCODING_MASK) | \ - (encoding << SQ_VOP3_0_SDST_ENC_ENCODING_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_SET_OP__VI(sq_vop3_0_sdst_enc_reg, op) \ - sq_vop3_0_sdst_enc_reg = \ - (sq_vop3_0_sdst_enc_reg & ~SQ_VOP3_0_SDST_ENC_OP_MASK) | (op << SQ_VOP3_0_SDST_ENC_OP_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_SET_SDST__VI(sq_vop3_0_sdst_enc_reg, sdst) \ - sq_vop3_0_sdst_enc_reg = (sq_vop3_0_sdst_enc_reg & ~SQ_VOP3_0_SDST_ENC_SDST_MASK) | \ - (sdst << SQ_VOP3_0_SDST_ENC_SDST_SHIFT) - -#define SQ_VOP3_0_SDST_ENC_SET_VDST__VI(sq_vop3_0_sdst_enc_reg, vdst) \ - sq_vop3_0_sdst_enc_reg = (sq_vop3_0_sdst_enc_reg & ~SQ_VOP3_0_SDST_ENC_VDST_MASK) | \ - (vdst << SQ_VOP3_0_SDST_ENC_VDST_SHIFT) - -#define SQ_VOP3_0_SET_ABS__VI(sq_vop3_0_reg, abs) \ - sq_vop3_0_reg = (sq_vop3_0_reg & ~SQ_VOP3_0_ABS_MASK) | (abs << SQ_VOP3_0_ABS_SHIFT) - -#define SQ_VOP3_0_SET_CLAMP__VI(sq_vop3_0_reg, clamp) \ - sq_vop3_0_reg = (sq_vop3_0_reg & ~SQ_VOP3_0_CLAMP_MASK) | (clamp << SQ_VOP3_0_CLAMP_SHIFT) - -#define SQ_VOP3_0_SET_ENCODING__VI(sq_vop3_0_reg, encoding) \ - sq_vop3_0_reg = \ - (sq_vop3_0_reg & ~SQ_VOP3_0_ENCODING_MASK) | (encoding << SQ_VOP3_0_ENCODING_SHIFT) - -#define SQ_VOP3_0_SET_OP__VI(sq_vop3_0_reg, op) \ - sq_vop3_0_reg = (sq_vop3_0_reg & ~SQ_VOP3_0_OP_MASK) | (op << SQ_VOP3_0_OP_SHIFT) - -#define SQ_VOP3_0_SET_VDST__VI(sq_vop3_0_reg, vdst) \ - sq_vop3_0_reg = (sq_vop3_0_reg & ~SQ_VOP3_0_VDST_MASK) | (vdst << SQ_VOP3_0_VDST_SHIFT) - -#define SQ_VOP3_1_GET_NEG__VI(sq_vop3_1) ((sq_vop3_1 & SQ_VOP3_1_NEG_MASK) >> SQ_VOP3_1_NEG_SHIFT) - -#define SQ_VOP3_1_GET_OMOD__VI(sq_vop3_1) \ - ((sq_vop3_1 & SQ_VOP3_1_OMOD_MASK) >> SQ_VOP3_1_OMOD_SHIFT) - -#define SQ_VOP3_1_GET_SRC0__VI(sq_vop3_1) \ - ((sq_vop3_1 & SQ_VOP3_1_SRC0_MASK) >> SQ_VOP3_1_SRC0_SHIFT) - -#define SQ_VOP3_1_GET_SRC1__VI(sq_vop3_1) \ - ((sq_vop3_1 & SQ_VOP3_1_SRC1_MASK) >> SQ_VOP3_1_SRC1_SHIFT) - -#define SQ_VOP3_1_GET_SRC2__VI(sq_vop3_1) \ - ((sq_vop3_1 & SQ_VOP3_1_SRC2_MASK) >> SQ_VOP3_1_SRC2_SHIFT) - -#define SQ_VOP3_1_MASK__VI \ - (SQ_VOP3_1_SRC0_MASK | SQ_VOP3_1_SRC1_MASK | SQ_VOP3_1_SRC2_MASK | SQ_VOP3_1_OMOD_MASK | \ - SQ_VOP3_1_NEG_MASK) - -#define SQ_VOP3_1_SET_NEG__VI(sq_vop3_1_reg, neg) \ - sq_vop3_1_reg = (sq_vop3_1_reg & ~SQ_VOP3_1_NEG_MASK) | (neg << SQ_VOP3_1_NEG_SHIFT) - -#define SQ_VOP3_1_SET_OMOD__VI(sq_vop3_1_reg, omod) \ - sq_vop3_1_reg = (sq_vop3_1_reg & ~SQ_VOP3_1_OMOD_MASK) | (omod << SQ_VOP3_1_OMOD_SHIFT) - -#define SQ_VOP3_1_SET_SRC0__VI(sq_vop3_1_reg, src0) \ - sq_vop3_1_reg = (sq_vop3_1_reg & ~SQ_VOP3_1_SRC0_MASK) | (src0 << SQ_VOP3_1_SRC0_SHIFT) - -#define SQ_VOP3_1_SET_SRC1__VI(sq_vop3_1_reg, src1) \ - sq_vop3_1_reg = (sq_vop3_1_reg & ~SQ_VOP3_1_SRC1_MASK) | (src1 << SQ_VOP3_1_SRC1_SHIFT) - -#define SQ_VOP3_1_SET_SRC2__VI(sq_vop3_1_reg, src2) \ - sq_vop3_1_reg = (sq_vop3_1_reg & ~SQ_VOP3_1_SRC2_MASK) | (src2 << SQ_VOP3_1_SRC2_SHIFT) - -#define SQ_VOPC_GET_ENCODING__VI(sq_vopc) \ - ((sq_vopc & SQ_VOPC_ENCODING_MASK) >> SQ_VOPC_ENCODING_SHIFT) - -#define SQ_VOPC_GET_OP__VI(sq_vopc) ((sq_vopc & SQ_VOPC_OP_MASK) >> SQ_VOPC_OP_SHIFT) - -#define SQ_VOPC_GET_SRC0__VI(sq_vopc) ((sq_vopc & SQ_VOPC_SRC0_MASK) >> SQ_VOPC_SRC0_SHIFT) - -#define SQ_VOPC_GET_VSRC1__VI(sq_vopc) ((sq_vopc & SQ_VOPC_VSRC1_MASK) >> SQ_VOPC_VSRC1_SHIFT) - -#define SQ_VOPC_MASK__VI \ - (SQ_VOPC_SRC0_MASK | SQ_VOPC_VSRC1_MASK | SQ_VOPC_OP_MASK | SQ_VOPC_ENCODING_MASK) - -#define SQ_VOPC_SET_ENCODING__VI(sq_vopc_reg, encoding) \ - sq_vopc_reg = (sq_vopc_reg & ~SQ_VOPC_ENCODING_MASK) | (encoding << SQ_VOPC_ENCODING_SHIFT) - -#define SQ_VOPC_SET_OP__VI(sq_vopc_reg, op) \ - sq_vopc_reg = (sq_vopc_reg & ~SQ_VOPC_OP_MASK) | (op << SQ_VOPC_OP_SHIFT) - -#define SQ_VOPC_SET_SRC0__VI(sq_vopc_reg, src0) \ - sq_vopc_reg = (sq_vopc_reg & ~SQ_VOPC_SRC0_MASK) | (src0 << SQ_VOPC_SRC0_SHIFT) - -#define SQ_VOPC_SET_VSRC1__VI(sq_vopc_reg, vsrc1) \ - sq_vopc_reg = (sq_vopc_reg & ~SQ_VOPC_VSRC1_MASK) | (vsrc1 << SQ_VOPC_VSRC1_SHIFT) - -#define SQ_VOP_DPP_BANK_MASK_MASK__VI 0x0f000000 -#define SQ_VOP_DPP_BANK_MASK_SHIFT__VI 24 -#define SQ_VOP_DPP_BANK_MASK_SIZE__VI 4 -#define SQ_VOP_DPP_BOUND_CTRL_MASK__VI 0x00080000 -#define SQ_VOP_DPP_BOUND_CTRL_SHIFT__VI 19 -#define SQ_VOP_DPP_BOUND_CTRL_SIZE__VI 1 -#define SQ_VOP_DPP_DEFAULT__VI 0xcdc9cdcd -#define SQ_VOP_DPP_DPP_CTRL_MASK__VI 0x0001ff00 -#define SQ_VOP_DPP_DPP_CTRL_SHIFT__VI 8 -#define SQ_VOP_DPP_DPP_CTRL_SIZE__VI 9 -#define SQ_VOP_DPP_GET_BANK_MASK__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_BANK_MASK_MASK) >> SQ_VOP_DPP_BANK_MASK_SHIFT) - -#define SQ_VOP_DPP_GET_BOUND_CTRL__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_BOUND_CTRL_MASK) >> SQ_VOP_DPP_BOUND_CTRL_SHIFT) - -#define SQ_VOP_DPP_GET_DPP_CTRL__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_DPP_CTRL_MASK) >> SQ_VOP_DPP_DPP_CTRL_SHIFT) - -#define SQ_VOP_DPP_GET_ROW_MASK__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_ROW_MASK_MASK) >> SQ_VOP_DPP_ROW_MASK_SHIFT) - -#define SQ_VOP_DPP_GET_SRC0__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_SRC0_MASK) >> SQ_VOP_DPP_SRC0_SHIFT) - -#define SQ_VOP_DPP_GET_SRC0_ABS__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_SRC0_ABS_MASK) >> SQ_VOP_DPP_SRC0_ABS_SHIFT) - -#define SQ_VOP_DPP_GET_SRC0_NEG__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_SRC0_NEG_MASK) >> SQ_VOP_DPP_SRC0_NEG_SHIFT) - -#define SQ_VOP_DPP_GET_SRC1_ABS__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_SRC1_ABS_MASK) >> SQ_VOP_DPP_SRC1_ABS_SHIFT) - -#define SQ_VOP_DPP_GET_SRC1_NEG__VI(sq_vop_dpp) \ - ((sq_vop_dpp & SQ_VOP_DPP_SRC1_NEG_MASK) >> SQ_VOP_DPP_SRC1_NEG_SHIFT) - -#define SQ_VOP_DPP_MASK__VI \ - (SQ_VOP_DPP_SRC0_MASK | SQ_VOP_DPP_DPP_CTRL_MASK | SQ_VOP_DPP_BOUND_CTRL_MASK | \ - SQ_VOP_DPP_SRC0_NEG_MASK | SQ_VOP_DPP_SRC0_ABS_MASK | SQ_VOP_DPP_SRC1_NEG_MASK | \ - SQ_VOP_DPP_SRC1_ABS_MASK | SQ_VOP_DPP_BANK_MASK_MASK | SQ_VOP_DPP_ROW_MASK_MASK) - -#define SQ_VOP_DPP_REG_SIZE__VI 32 -#define SQ_VOP_DPP_ROW_MASK_MASK__VI 0xf0000000 -#define SQ_VOP_DPP_ROW_MASK_SHIFT__VI 28 -#define SQ_VOP_DPP_ROW_MASK_SIZE__VI 4 -#define SQ_VOP_DPP_SET_BANK_MASK__VI(sq_vop_dpp_reg, bank_mask) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_BANK_MASK_MASK) | (bank_mask << SQ_VOP_DPP_BANK_MASK_SHIFT) - -#define SQ_VOP_DPP_SET_BOUND_CTRL__VI(sq_vop_dpp_reg, bound_ctrl) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_BOUND_CTRL_MASK) | (bound_ctrl << SQ_VOP_DPP_BOUND_CTRL_SHIFT) - -#define SQ_VOP_DPP_SET_DPP_CTRL__VI(sq_vop_dpp_reg, dpp_ctrl) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_DPP_CTRL_MASK) | (dpp_ctrl << SQ_VOP_DPP_DPP_CTRL_SHIFT) - -#define SQ_VOP_DPP_SET_ROW_MASK__VI(sq_vop_dpp_reg, row_mask) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_ROW_MASK_MASK) | (row_mask << SQ_VOP_DPP_ROW_MASK_SHIFT) - -#define SQ_VOP_DPP_SET_SRC0__VI(sq_vop_dpp_reg, src0) \ - sq_vop_dpp_reg = (sq_vop_dpp_reg & ~SQ_VOP_DPP_SRC0_MASK) | (src0 << SQ_VOP_DPP_SRC0_SHIFT) - -#define SQ_VOP_DPP_SET_SRC0_ABS__VI(sq_vop_dpp_reg, src0_abs) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_SRC0_ABS_MASK) | (src0_abs << SQ_VOP_DPP_SRC0_ABS_SHIFT) - -#define SQ_VOP_DPP_SET_SRC0_NEG__VI(sq_vop_dpp_reg, src0_neg) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_SRC0_NEG_MASK) | (src0_neg << SQ_VOP_DPP_SRC0_NEG_SHIFT) - -#define SQ_VOP_DPP_SET_SRC1_ABS__VI(sq_vop_dpp_reg, src1_abs) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_SRC1_ABS_MASK) | (src1_abs << SQ_VOP_DPP_SRC1_ABS_SHIFT) - -#define SQ_VOP_DPP_SET_SRC1_NEG__VI(sq_vop_dpp_reg, src1_neg) \ - sq_vop_dpp_reg = \ - (sq_vop_dpp_reg & ~SQ_VOP_DPP_SRC1_NEG_MASK) | (src1_neg << SQ_VOP_DPP_SRC1_NEG_SHIFT) - -#define SQ_VOP_DPP_SRC0_ABS_MASK__VI 0x00200000 -#define SQ_VOP_DPP_SRC0_ABS_SHIFT__VI 21 -#define SQ_VOP_DPP_SRC0_ABS_SIZE__VI 1 -#define SQ_VOP_DPP_SRC0_MASK__VI 0x000000ff -#define SQ_VOP_DPP_SRC0_NEG_MASK__VI 0x00100000 -#define SQ_VOP_DPP_SRC0_NEG_SHIFT__VI 20 -#define SQ_VOP_DPP_SRC0_NEG_SIZE__VI 1 -#define SQ_VOP_DPP_SRC0_SHIFT__VI 0x00000000 -#define SQ_VOP_DPP_SRC0_SIZE__VI 8 -#define SQ_VOP_DPP_SRC1_ABS_MASK__VI 0x00800000 -#define SQ_VOP_DPP_SRC1_ABS_SHIFT__VI 23 -#define SQ_VOP_DPP_SRC1_ABS_SIZE__VI 1 -#define SQ_VOP_DPP_SRC1_NEG_MASK__VI 0x00400000 -#define SQ_VOP_DPP_SRC1_NEG_SHIFT__VI 22 -#define SQ_VOP_DPP_SRC1_NEG_SIZE__VI 1 -#define SQ_VOP_SDWA_CLAMP_MASK__VI 0x00002000 -#define SQ_VOP_SDWA_CLAMP_SHIFT__VI 13 -#define SQ_VOP_SDWA_CLAMP_SIZE__VI 1 -#define SQ_VOP_SDWA_DEFAULT__VI 0x0d0d0dcd -#define SQ_VOP_SDWA_DST_SEL_MASK__VI 0x00000700 -#define SQ_VOP_SDWA_DST_SEL_SHIFT__VI 8 -#define SQ_VOP_SDWA_DST_SEL_SIZE__VI 3 -#define SQ_VOP_SDWA_DST_UNUSED_MASK__VI 0x00001800 -#define SQ_VOP_SDWA_DST_UNUSED_SHIFT__VI 11 -#define SQ_VOP_SDWA_DST_UNUSED_SIZE__VI 2 -#define SQ_VOP_SDWA_GET_CLAMP__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_CLAMP_MASK) >> SQ_VOP_SDWA_CLAMP_SHIFT) - -#define SQ_VOP_SDWA_GET_DST_SEL__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_DST_SEL_MASK) >> SQ_VOP_SDWA_DST_SEL_SHIFT) - -#define SQ_VOP_SDWA_GET_DST_UNUSED__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_DST_UNUSED_MASK) >> SQ_VOP_SDWA_DST_UNUSED_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC0__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC0_MASK) >> SQ_VOP_SDWA_SRC0_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC0_ABS__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC0_ABS_MASK) >> SQ_VOP_SDWA_SRC0_ABS_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC0_NEG__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC0_NEG_MASK) >> SQ_VOP_SDWA_SRC0_NEG_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC0_SEL__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC0_SEL_MASK) >> SQ_VOP_SDWA_SRC0_SEL_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC0_SEXT__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC0_SEXT_MASK) >> SQ_VOP_SDWA_SRC0_SEXT_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC1_ABS__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC1_ABS_MASK) >> SQ_VOP_SDWA_SRC1_ABS_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC1_NEG__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC1_NEG_MASK) >> SQ_VOP_SDWA_SRC1_NEG_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC1_SEL__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC1_SEL_MASK) >> SQ_VOP_SDWA_SRC1_SEL_SHIFT) - -#define SQ_VOP_SDWA_GET_SRC1_SEXT__VI(sq_vop_sdwa) \ - ((sq_vop_sdwa & SQ_VOP_SDWA_SRC1_SEXT_MASK) >> SQ_VOP_SDWA_SRC1_SEXT_SHIFT) - -#define SQ_VOP_SDWA_MASK__VI \ - (SQ_VOP_SDWA_SRC0_MASK | SQ_VOP_SDWA_DST_SEL_MASK | SQ_VOP_SDWA_DST_UNUSED_MASK | \ - SQ_VOP_SDWA_CLAMP_MASK | SQ_VOP_SDWA_SRC0_SEL_MASK | SQ_VOP_SDWA_SRC0_SEXT_MASK | \ - SQ_VOP_SDWA_SRC0_NEG_MASK | SQ_VOP_SDWA_SRC0_ABS_MASK | SQ_VOP_SDWA_SRC1_SEL_MASK | \ - SQ_VOP_SDWA_SRC1_SEXT_MASK | SQ_VOP_SDWA_SRC1_NEG_MASK | SQ_VOP_SDWA_SRC1_ABS_MASK) - -#define SQ_VOP_SDWA_REG_SIZE__VI 32 -#define SQ_VOP_SDWA_SET_CLAMP__VI(sq_vop_sdwa_reg, clamp) \ - sq_vop_sdwa_reg = (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_CLAMP_MASK) | (clamp << SQ_VOP_SDWA_CLAMP_SHIFT) - -#define SQ_VOP_SDWA_SET_DST_SEL__VI(sq_vop_sdwa_reg, dst_sel) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_DST_SEL_MASK) | (dst_sel << SQ_VOP_SDWA_DST_SEL_SHIFT) - -#define SQ_VOP_SDWA_SET_DST_UNUSED__VI(sq_vop_sdwa_reg, dst_unused) \ - sq_vop_sdwa_reg = (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_DST_UNUSED_MASK) | \ - (dst_unused << SQ_VOP_SDWA_DST_UNUSED_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC0__VI(sq_vop_sdwa_reg, src0) \ - sq_vop_sdwa_reg = (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC0_MASK) | (src0 << SQ_VOP_SDWA_SRC0_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC0_ABS__VI(sq_vop_sdwa_reg, src0_abs) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC0_ABS_MASK) | (src0_abs << SQ_VOP_SDWA_SRC0_ABS_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC0_NEG__VI(sq_vop_sdwa_reg, src0_neg) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC0_NEG_MASK) | (src0_neg << SQ_VOP_SDWA_SRC0_NEG_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC0_SEL__VI(sq_vop_sdwa_reg, src0_sel) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC0_SEL_MASK) | (src0_sel << SQ_VOP_SDWA_SRC0_SEL_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC0_SEXT__VI(sq_vop_sdwa_reg, src0_sext) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC0_SEXT_MASK) | (src0_sext << SQ_VOP_SDWA_SRC0_SEXT_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC1_ABS__VI(sq_vop_sdwa_reg, src1_abs) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC1_ABS_MASK) | (src1_abs << SQ_VOP_SDWA_SRC1_ABS_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC1_NEG__VI(sq_vop_sdwa_reg, src1_neg) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC1_NEG_MASK) | (src1_neg << SQ_VOP_SDWA_SRC1_NEG_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC1_SEL__VI(sq_vop_sdwa_reg, src1_sel) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC1_SEL_MASK) | (src1_sel << SQ_VOP_SDWA_SRC1_SEL_SHIFT) - -#define SQ_VOP_SDWA_SET_SRC1_SEXT__VI(sq_vop_sdwa_reg, src1_sext) \ - sq_vop_sdwa_reg = \ - (sq_vop_sdwa_reg & ~SQ_VOP_SDWA_SRC1_SEXT_MASK) | (src1_sext << SQ_VOP_SDWA_SRC1_SEXT_SHIFT) - -#define SQ_VOP_SDWA_SRC0_ABS_MASK__VI 0x00200000 -#define SQ_VOP_SDWA_SRC0_ABS_SHIFT__VI 21 -#define SQ_VOP_SDWA_SRC0_ABS_SIZE__VI 1 -#define SQ_VOP_SDWA_SRC0_MASK__VI 0x000000ff -#define SQ_VOP_SDWA_SRC0_NEG_MASK__VI 0x00100000 -#define SQ_VOP_SDWA_SRC0_NEG_SHIFT__VI 20 -#define SQ_VOP_SDWA_SRC0_NEG_SIZE__VI 1 -#define SQ_VOP_SDWA_SRC0_SEL_MASK__VI 0x00070000 -#define SQ_VOP_SDWA_SRC0_SEL_SHIFT__VI 16 -#define SQ_VOP_SDWA_SRC0_SEL_SIZE__VI 3 -#define SQ_VOP_SDWA_SRC0_SEXT_MASK__VI 0x00080000 -#define SQ_VOP_SDWA_SRC0_SEXT_SHIFT__VI 19 -#define SQ_VOP_SDWA_SRC0_SEXT_SIZE__VI 1 -#define SQ_VOP_SDWA_SRC0_SHIFT__VI 0x00000000 -#define SQ_VOP_SDWA_SRC0_SIZE__VI 8 -#define SQ_VOP_SDWA_SRC1_ABS_MASK__VI 0x20000000 -#define SQ_VOP_SDWA_SRC1_ABS_SHIFT__VI 29 -#define SQ_VOP_SDWA_SRC1_ABS_SIZE__VI 1 -#define SQ_VOP_SDWA_SRC1_NEG_MASK__VI 0x10000000 -#define SQ_VOP_SDWA_SRC1_NEG_SHIFT__VI 28 -#define SQ_VOP_SDWA_SRC1_NEG_SIZE__VI 1 -#define SQ_VOP_SDWA_SRC1_SEL_MASK__VI 0x07000000 -#define SQ_VOP_SDWA_SRC1_SEL_SHIFT__VI 24 -#define SQ_VOP_SDWA_SRC1_SEL_SIZE__VI 3 -#define SQ_VOP_SDWA_SRC1_SEXT_MASK__VI 0x08000000 -#define SQ_VOP_SDWA_SRC1_SEXT_SHIFT__VI 27 -#define SQ_VOP_SDWA_SRC1_SEXT_SIZE__VI 1 -#define SQ_V_ADDC_U32__SI__CI 0x00000028 -#define SQ_V_ADDC_U32__VI 0x0000001c -#define SQ_V_ADD_F16__VI 0x0000001f -#define SQ_V_ADD_F32__SI__CI 0x00000003 -#define SQ_V_ADD_F32__VI 0x00000001 -#define SQ_V_ADD_F64__SI__CI 0x00000164 -#define SQ_V_ADD_F64__VI 0x00000280 -#define SQ_V_ADD_U16__VI 0x00000026 -#define SQ_V_ADD_U32__VI 0x00000019 -#define SQ_V_ALIGNBIT_B32__SI__CI 0x0000014e -#define SQ_V_ALIGNBIT_B32__VI 0x000001ce -#define SQ_V_ALIGNBYTE_B32__SI__CI 0x0000014f -#define SQ_V_ALIGNBYTE_B32__VI 0x000001cf -#define SQ_V_AND_B32__SI__CI 0x0000001b -#define SQ_V_AND_B32__VI 0x00000013 -#define SQ_V_ASHRREV_I16__VI 0x0000002c -#define SQ_V_ASHRREV_I32__SI__CI 0x00000018 -#define SQ_V_ASHRREV_I32__VI 0x00000011 -#define SQ_V_ASHRREV_I64__VI 0x00000291 -#define SQ_V_BCNT_U32_B32__SI__CI 0x00000022 -#define SQ_V_BCNT_U32_B32__VI 0x0000028b -#define SQ_V_BFE_I32__SI__CI 0x00000149 -#define SQ_V_BFE_I32__VI 0x000001c9 -#define SQ_V_BFE_U32__SI__CI 0x00000148 -#define SQ_V_BFE_U32__VI 0x000001c8 -#define SQ_V_BFI_B32__SI__CI 0x0000014a -#define SQ_V_BFI_B32__VI 0x000001ca -#define SQ_V_BFM_B32__SI__CI 0x0000001e -#define SQ_V_BFM_B32__VI 0x00000293 -#define SQ_V_BFREV_B32__SI__CI 0x00000038 -#define SQ_V_BFREV_B32__VI 0x0000002c -#define SQ_V_CEIL_F16__VI 0x00000045 -#define SQ_V_CEIL_F32__SI__CI 0x00000022 -#define SQ_V_CEIL_F32__VI 0x0000001d -#define SQ_V_CLREXCP__SI__CI 0x00000041 -#define SQ_V_CLREXCP__VI 0x00000035 -#define SQ_V_CMPX_CLASS_F16__VI 0x00000015 -#define SQ_V_CMPX_CLASS_F32__SI__CI 0x00000098 -#define SQ_V_CMPX_CLASS_F32__VI 0x00000011 -#define SQ_V_CMPX_CLASS_F64__SI__CI 0x000000b8 -#define SQ_V_CMPX_CLASS_F64__VI 0x00000013 -#define SQ_V_CMPX_EQ_F16__VI 0x00000032 -#define SQ_V_CMPX_EQ_F32__SI__CI 0x00000012 -#define SQ_V_CMPX_EQ_F32__VI 0x00000052 -#define SQ_V_CMPX_EQ_F64__SI__CI 0x00000032 -#define SQ_V_CMPX_EQ_F64__VI 0x00000072 -#define SQ_V_CMPX_EQ_I16__VI 0x000000b2 -#define SQ_V_CMPX_EQ_I32__SI__CI 0x00000092 -#define SQ_V_CMPX_EQ_I32__VI 0x000000d2 -#define SQ_V_CMPX_EQ_I64__SI__CI 0x000000b2 -#define SQ_V_CMPX_EQ_I64__VI 0x000000f2 -#define SQ_V_CMPX_EQ_U16__VI 0x000000ba -#define SQ_V_CMPX_EQ_U32__SI__CI 0x000000d2 -#define SQ_V_CMPX_EQ_U32__VI 0x000000da -#define SQ_V_CMPX_EQ_U64__SI__CI 0x000000f2 -#define SQ_V_CMPX_EQ_U64__VI 0x000000fa -#define SQ_V_CMPX_F_F16__VI 0x00000030 -#define SQ_V_CMPX_F_F32__SI__CI 0x00000010 -#define SQ_V_CMPX_F_F32__VI 0x00000050 -#define SQ_V_CMPX_F_F64__SI__CI 0x00000030 -#define SQ_V_CMPX_F_F64__VI 0x00000070 -#define SQ_V_CMPX_F_I16__VI 0x000000b0 -#define SQ_V_CMPX_F_I32__SI__CI 0x00000090 -#define SQ_V_CMPX_F_I32__VI 0x000000d0 -#define SQ_V_CMPX_F_I64__SI__CI 0x000000b0 -#define SQ_V_CMPX_F_I64__VI 0x000000f0 -#define SQ_V_CMPX_F_U16__VI 0x000000b8 -#define SQ_V_CMPX_F_U32__SI__CI 0x000000d0 -#define SQ_V_CMPX_F_U32__VI 0x000000d8 -#define SQ_V_CMPX_F_U64__SI__CI 0x000000f0 -#define SQ_V_CMPX_F_U64__VI 0x000000f8 -#define SQ_V_CMPX_GE_F16__VI 0x00000036 -#define SQ_V_CMPX_GE_F32__SI__CI 0x00000016 -#define SQ_V_CMPX_GE_F32__VI 0x00000056 -#define SQ_V_CMPX_GE_F64__SI__CI 0x00000036 -#define SQ_V_CMPX_GE_F64__VI 0x00000076 -#define SQ_V_CMPX_GE_I16__VI 0x000000b6 -#define SQ_V_CMPX_GE_I32__SI__CI 0x00000096 -#define SQ_V_CMPX_GE_I32__VI 0x000000d6 -#define SQ_V_CMPX_GE_I64__SI__CI 0x000000b6 -#define SQ_V_CMPX_GE_I64__VI 0x000000f6 -#define SQ_V_CMPX_GE_U16__VI 0x000000be -#define SQ_V_CMPX_GE_U32__SI__CI 0x000000d6 -#define SQ_V_CMPX_GE_U32__VI 0x000000de -#define SQ_V_CMPX_GE_U64__SI__CI 0x000000f6 -#define SQ_V_CMPX_GE_U64__VI 0x000000fe -#define SQ_V_CMPX_GT_F16__VI 0x00000034 -#define SQ_V_CMPX_GT_F32__SI__CI 0x00000014 -#define SQ_V_CMPX_GT_F32__VI 0x00000054 -#define SQ_V_CMPX_GT_F64__SI__CI 0x00000034 -#define SQ_V_CMPX_GT_F64__VI 0x00000074 -#define SQ_V_CMPX_GT_I16__VI 0x000000b4 -#define SQ_V_CMPX_GT_I32__SI__CI 0x00000094 -#define SQ_V_CMPX_GT_I32__VI 0x000000d4 -#define SQ_V_CMPX_GT_I64__SI__CI 0x000000b4 -#define SQ_V_CMPX_GT_I64__VI 0x000000f4 -#define SQ_V_CMPX_GT_U16__VI 0x000000bc -#define SQ_V_CMPX_GT_U32__SI__CI 0x000000d4 -#define SQ_V_CMPX_GT_U32__VI 0x000000dc -#define SQ_V_CMPX_GT_U64__SI__CI 0x000000f4 -#define SQ_V_CMPX_GT_U64__VI 0x000000fc -#define SQ_V_CMPX_LE_F16__VI 0x00000033 -#define SQ_V_CMPX_LE_F32__SI__CI 0x00000013 -#define SQ_V_CMPX_LE_F32__VI 0x00000053 -#define SQ_V_CMPX_LE_F64__SI__CI 0x00000033 -#define SQ_V_CMPX_LE_F64__VI 0x00000073 -#define SQ_V_CMPX_LE_I16__VI 0x000000b3 -#define SQ_V_CMPX_LE_I32__SI__CI 0x00000093 -#define SQ_V_CMPX_LE_I32__VI 0x000000d3 -#define SQ_V_CMPX_LE_I64__SI__CI 0x000000b3 -#define SQ_V_CMPX_LE_I64__VI 0x000000f3 -#define SQ_V_CMPX_LE_U16__VI 0x000000bb -#define SQ_V_CMPX_LE_U32__SI__CI 0x000000d3 -#define SQ_V_CMPX_LE_U32__VI 0x000000db -#define SQ_V_CMPX_LE_U64__SI__CI 0x000000f3 -#define SQ_V_CMPX_LE_U64__VI 0x000000fb -#define SQ_V_CMPX_LG_F16__VI 0x00000035 -#define SQ_V_CMPX_LG_F32__SI__CI 0x00000015 -#define SQ_V_CMPX_LG_F32__VI 0x00000055 -#define SQ_V_CMPX_LG_F64__SI__CI 0x00000035 -#define SQ_V_CMPX_LG_F64__VI 0x00000075 -#define SQ_V_CMPX_LT_F16__VI 0x00000031 -#define SQ_V_CMPX_LT_F32__SI__CI 0x00000011 -#define SQ_V_CMPX_LT_F32__VI 0x00000051 -#define SQ_V_CMPX_LT_F64__SI__CI 0x00000031 -#define SQ_V_CMPX_LT_F64__VI 0x00000071 -#define SQ_V_CMPX_LT_I16__VI 0x000000b1 -#define SQ_V_CMPX_LT_I32__SI__CI 0x00000091 -#define SQ_V_CMPX_LT_I32__VI 0x000000d1 -#define SQ_V_CMPX_LT_I64__SI__CI 0x000000b1 -#define SQ_V_CMPX_LT_I64__VI 0x000000f1 -#define SQ_V_CMPX_LT_U16__VI 0x000000b9 -#define SQ_V_CMPX_LT_U32__SI__CI 0x000000d1 -#define SQ_V_CMPX_LT_U32__VI 0x000000d9 -#define SQ_V_CMPX_LT_U64__SI__CI 0x000000f1 -#define SQ_V_CMPX_LT_U64__VI 0x000000f9 -#define SQ_V_CMPX_NEQ_F16__VI 0x0000003d -#define SQ_V_CMPX_NEQ_F32__SI__CI 0x0000001d -#define SQ_V_CMPX_NEQ_F32__VI 0x0000005d -#define SQ_V_CMPX_NEQ_F64__SI__CI 0x0000003d -#define SQ_V_CMPX_NEQ_F64__VI 0x0000007d -#define SQ_V_CMPX_NE_I16__VI 0x000000b5 -#define SQ_V_CMPX_NE_I32__SI__CI 0x00000095 -#define SQ_V_CMPX_NE_I32__VI 0x000000d5 -#define SQ_V_CMPX_NE_I64__SI__CI 0x000000b5 -#define SQ_V_CMPX_NE_I64__VI 0x000000f5 -#define SQ_V_CMPX_NE_U16__VI 0x000000bd -#define SQ_V_CMPX_NE_U32__SI__CI 0x000000d5 -#define SQ_V_CMPX_NE_U32__VI 0x000000dd -#define SQ_V_CMPX_NE_U64__SI__CI 0x000000f5 -#define SQ_V_CMPX_NE_U64__VI 0x000000fd -#define SQ_V_CMPX_NGE_F16__VI 0x00000039 -#define SQ_V_CMPX_NGE_F32__SI__CI 0x00000019 -#define SQ_V_CMPX_NGE_F32__VI 0x00000059 -#define SQ_V_CMPX_NGE_F64__SI__CI 0x00000039 -#define SQ_V_CMPX_NGE_F64__VI 0x00000079 -#define SQ_V_CMPX_NGT_F16__VI 0x0000003b -#define SQ_V_CMPX_NGT_F32__SI__CI 0x0000001b -#define SQ_V_CMPX_NGT_F32__VI 0x0000005b -#define SQ_V_CMPX_NGT_F64__SI__CI 0x0000003b -#define SQ_V_CMPX_NGT_F64__VI 0x0000007b -#define SQ_V_CMPX_NLE_F16__VI 0x0000003c -#define SQ_V_CMPX_NLE_F32__SI__CI 0x0000001c -#define SQ_V_CMPX_NLE_F32__VI 0x0000005c -#define SQ_V_CMPX_NLE_F64__SI__CI 0x0000003c -#define SQ_V_CMPX_NLE_F64__VI 0x0000007c -#define SQ_V_CMPX_NLG_F16__VI 0x0000003a -#define SQ_V_CMPX_NLG_F32__SI__CI 0x0000001a -#define SQ_V_CMPX_NLG_F32__VI 0x0000005a -#define SQ_V_CMPX_NLG_F64__SI__CI 0x0000003a -#define SQ_V_CMPX_NLG_F64__VI 0x0000007a -#define SQ_V_CMPX_NLT_F16__VI 0x0000003e -#define SQ_V_CMPX_NLT_F32__SI__CI 0x0000001e -#define SQ_V_CMPX_NLT_F32__VI 0x0000005e -#define SQ_V_CMPX_NLT_F64__SI__CI 0x0000003e -#define SQ_V_CMPX_NLT_F64__VI 0x0000007e -#define SQ_V_CMPX_O_F16__VI 0x00000037 -#define SQ_V_CMPX_O_F32__SI__CI 0x00000017 -#define SQ_V_CMPX_O_F32__VI 0x00000057 -#define SQ_V_CMPX_O_F64__SI__CI 0x00000037 -#define SQ_V_CMPX_O_F64__VI 0x00000077 -#define SQ_V_CMPX_TRU_F16__VI 0x0000003f -#define SQ_V_CMPX_TRU_F32__SI__CI 0x0000001f -#define SQ_V_CMPX_TRU_F32__VI 0x0000005f -#define SQ_V_CMPX_TRU_F64__SI__CI 0x0000003f -#define SQ_V_CMPX_TRU_F64__VI 0x0000007f -#define SQ_V_CMPX_T_I16__VI 0x000000b7 -#define SQ_V_CMPX_T_I32__SI__CI 0x00000097 -#define SQ_V_CMPX_T_I32__VI 0x000000d7 -#define SQ_V_CMPX_T_I64__SI__CI 0x000000b7 -#define SQ_V_CMPX_T_I64__VI 0x000000f7 -#define SQ_V_CMPX_T_U16__VI 0x000000bf -#define SQ_V_CMPX_T_U32__SI__CI 0x000000d7 -#define SQ_V_CMPX_T_U32__VI 0x000000df -#define SQ_V_CMPX_T_U64__SI__CI 0x000000f7 -#define SQ_V_CMPX_T_U64__VI 0x000000ff -#define SQ_V_CMPX_U_F16__VI 0x00000038 -#define SQ_V_CMPX_U_F32__SI__CI 0x00000018 -#define SQ_V_CMPX_U_F32__VI 0x00000058 -#define SQ_V_CMPX_U_F64__SI__CI 0x00000038 -#define SQ_V_CMPX_U_F64__VI 0x00000078 -#define SQ_V_CMP_CLASS_F16__VI 0x00000014 -#define SQ_V_CMP_CLASS_F32__SI__CI 0x00000088 -#define SQ_V_CMP_CLASS_F32__VI 0x00000010 -#define SQ_V_CMP_CLASS_F64__SI__CI 0x000000a8 -#define SQ_V_CMP_CLASS_F64__VI 0x00000012 -#define SQ_V_CMP_EQ_F16__VI 0x00000022 -#define SQ_V_CMP_EQ_F32__SI__CI 0x00000002 -#define SQ_V_CMP_EQ_F32__VI 0x00000042 -#define SQ_V_CMP_EQ_F64__SI__CI 0x00000022 -#define SQ_V_CMP_EQ_F64__VI 0x00000062 -#define SQ_V_CMP_EQ_I16__VI 0x000000a2 -#define SQ_V_CMP_EQ_I32__SI__CI 0x00000082 -#define SQ_V_CMP_EQ_I32__VI 0x000000c2 -#define SQ_V_CMP_EQ_I64__SI__CI 0x000000a2 -#define SQ_V_CMP_EQ_I64__VI 0x000000e2 -#define SQ_V_CMP_EQ_U16__VI 0x000000aa -#define SQ_V_CMP_EQ_U32__SI__CI 0x000000c2 -#define SQ_V_CMP_EQ_U32__VI 0x000000ca -#define SQ_V_CMP_EQ_U64__SI__CI 0x000000e2 -#define SQ_V_CMP_EQ_U64__VI 0x000000ea -#define SQ_V_CMP_F_F16__VI 0x00000020 -#define SQ_V_CMP_F_F32__SI__CI 0x00000000 -#define SQ_V_CMP_F_F32__VI 0x00000040 -#define SQ_V_CMP_F_F64__SI__CI 0x00000020 -#define SQ_V_CMP_F_F64__VI 0x00000060 -#define SQ_V_CMP_F_I16__VI 0x000000a0 -#define SQ_V_CMP_F_I32__SI__CI 0x00000080 -#define SQ_V_CMP_F_I32__VI 0x000000c0 -#define SQ_V_CMP_F_I64__SI__CI 0x000000a0 -#define SQ_V_CMP_F_I64__VI 0x000000e0 -#define SQ_V_CMP_F_U16__VI 0x000000a8 -#define SQ_V_CMP_F_U32__SI__CI 0x000000c0 -#define SQ_V_CMP_F_U32__VI 0x000000c8 -#define SQ_V_CMP_F_U64__SI__CI 0x000000e0 -#define SQ_V_CMP_F_U64__VI 0x000000e8 -#define SQ_V_CMP_GE_F16__VI 0x00000026 -#define SQ_V_CMP_GE_F32__SI__CI 0x00000006 -#define SQ_V_CMP_GE_F32__VI 0x00000046 -#define SQ_V_CMP_GE_F64__SI__CI 0x00000026 -#define SQ_V_CMP_GE_F64__VI 0x00000066 -#define SQ_V_CMP_GE_I16__VI 0x000000a6 -#define SQ_V_CMP_GE_I32__SI__CI 0x00000086 -#define SQ_V_CMP_GE_I32__VI 0x000000c6 -#define SQ_V_CMP_GE_I64__SI__CI 0x000000a6 -#define SQ_V_CMP_GE_I64__VI 0x000000e6 -#define SQ_V_CMP_GE_U16__VI 0x000000ae -#define SQ_V_CMP_GE_U32__SI__CI 0x000000c6 -#define SQ_V_CMP_GE_U32__VI 0x000000ce -#define SQ_V_CMP_GE_U64__SI__CI 0x000000e6 -#define SQ_V_CMP_GE_U64__VI 0x000000ee -#define SQ_V_CMP_GT_F16__VI 0x00000024 -#define SQ_V_CMP_GT_F32__SI__CI 0x00000004 -#define SQ_V_CMP_GT_F32__VI 0x00000044 -#define SQ_V_CMP_GT_F64__SI__CI 0x00000024 -#define SQ_V_CMP_GT_F64__VI 0x00000064 -#define SQ_V_CMP_GT_I16__VI 0x000000a4 -#define SQ_V_CMP_GT_I32__SI__CI 0x00000084 -#define SQ_V_CMP_GT_I32__VI 0x000000c4 -#define SQ_V_CMP_GT_I64__SI__CI 0x000000a4 -#define SQ_V_CMP_GT_I64__VI 0x000000e4 -#define SQ_V_CMP_GT_U16__VI 0x000000ac -#define SQ_V_CMP_GT_U32__SI__CI 0x000000c4 -#define SQ_V_CMP_GT_U32__VI 0x000000cc -#define SQ_V_CMP_GT_U64__SI__CI 0x000000e4 -#define SQ_V_CMP_GT_U64__VI 0x000000ec -#define SQ_V_CMP_LE_F16__VI 0x00000023 -#define SQ_V_CMP_LE_F32__SI__CI 0x00000003 -#define SQ_V_CMP_LE_F32__VI 0x00000043 -#define SQ_V_CMP_LE_F64__SI__CI 0x00000023 -#define SQ_V_CMP_LE_F64__VI 0x00000063 -#define SQ_V_CMP_LE_I16__VI 0x000000a3 -#define SQ_V_CMP_LE_I32__SI__CI 0x00000083 -#define SQ_V_CMP_LE_I32__VI 0x000000c3 -#define SQ_V_CMP_LE_I64__SI__CI 0x000000a3 -#define SQ_V_CMP_LE_I64__VI 0x000000e3 -#define SQ_V_CMP_LE_U16__VI 0x000000ab -#define SQ_V_CMP_LE_U32__SI__CI 0x000000c3 -#define SQ_V_CMP_LE_U32__VI 0x000000cb -#define SQ_V_CMP_LE_U64__SI__CI 0x000000e3 -#define SQ_V_CMP_LE_U64__VI 0x000000eb -#define SQ_V_CMP_LG_F16__VI 0x00000025 -#define SQ_V_CMP_LG_F32__SI__CI 0x00000005 -#define SQ_V_CMP_LG_F32__VI 0x00000045 -#define SQ_V_CMP_LG_F64__SI__CI 0x00000025 -#define SQ_V_CMP_LG_F64__VI 0x00000065 -#define SQ_V_CMP_LT_F16__VI 0x00000021 -#define SQ_V_CMP_LT_F32__SI__CI 0x00000001 -#define SQ_V_CMP_LT_F32__VI 0x00000041 -#define SQ_V_CMP_LT_F64__SI__CI 0x00000021 -#define SQ_V_CMP_LT_F64__VI 0x00000061 -#define SQ_V_CMP_LT_I16__VI 0x000000a1 -#define SQ_V_CMP_LT_I32__SI__CI 0x00000081 -#define SQ_V_CMP_LT_I32__VI 0x000000c1 -#define SQ_V_CMP_LT_I64__SI__CI 0x000000a1 -#define SQ_V_CMP_LT_I64__VI 0x000000e1 -#define SQ_V_CMP_LT_U16__VI 0x000000a9 -#define SQ_V_CMP_LT_U32__SI__CI 0x000000c1 -#define SQ_V_CMP_LT_U32__VI 0x000000c9 -#define SQ_V_CMP_LT_U64__SI__CI 0x000000e1 -#define SQ_V_CMP_LT_U64__VI 0x000000e9 -#define SQ_V_CMP_NEQ_F16__VI 0x0000002d -#define SQ_V_CMP_NEQ_F32__SI__CI 0x0000000d -#define SQ_V_CMP_NEQ_F32__VI 0x0000004d -#define SQ_V_CMP_NEQ_F64__SI__CI 0x0000002d -#define SQ_V_CMP_NEQ_F64__VI 0x0000006d -#define SQ_V_CMP_NE_I16__VI 0x000000a5 -#define SQ_V_CMP_NE_I32__SI__CI 0x00000085 -#define SQ_V_CMP_NE_I32__VI 0x000000c5 -#define SQ_V_CMP_NE_I64__SI__CI 0x000000a5 -#define SQ_V_CMP_NE_I64__VI 0x000000e5 -#define SQ_V_CMP_NE_U16__VI 0x000000ad -#define SQ_V_CMP_NE_U32__SI__CI 0x000000c5 -#define SQ_V_CMP_NE_U32__VI 0x000000cd -#define SQ_V_CMP_NE_U64__SI__CI 0x000000e5 -#define SQ_V_CMP_NE_U64__VI 0x000000ed -#define SQ_V_CMP_NGE_F16__VI 0x00000029 -#define SQ_V_CMP_NGE_F32__SI__CI 0x00000009 -#define SQ_V_CMP_NGE_F32__VI 0x00000049 -#define SQ_V_CMP_NGE_F64__SI__CI 0x00000029 -#define SQ_V_CMP_NGE_F64__VI 0x00000069 -#define SQ_V_CMP_NGT_F16__VI 0x0000002b -#define SQ_V_CMP_NGT_F32__SI__CI 0x0000000b -#define SQ_V_CMP_NGT_F32__VI 0x0000004b -#define SQ_V_CMP_NGT_F64__SI__CI 0x0000002b -#define SQ_V_CMP_NGT_F64__VI 0x0000006b -#define SQ_V_CMP_NLE_F16__VI 0x0000002c -#define SQ_V_CMP_NLE_F32__SI__CI 0x0000000c -#define SQ_V_CMP_NLE_F32__VI 0x0000004c -#define SQ_V_CMP_NLE_F64__SI__CI 0x0000002c -#define SQ_V_CMP_NLE_F64__VI 0x0000006c -#define SQ_V_CMP_NLG_F16__VI 0x0000002a -#define SQ_V_CMP_NLG_F32__SI__CI 0x0000000a -#define SQ_V_CMP_NLG_F32__VI 0x0000004a -#define SQ_V_CMP_NLG_F64__SI__CI 0x0000002a -#define SQ_V_CMP_NLG_F64__VI 0x0000006a -#define SQ_V_CMP_NLT_F16__VI 0x0000002e -#define SQ_V_CMP_NLT_F32__SI__CI 0x0000000e -#define SQ_V_CMP_NLT_F32__VI 0x0000004e -#define SQ_V_CMP_NLT_F64__SI__CI 0x0000002e -#define SQ_V_CMP_NLT_F64__VI 0x0000006e -#define SQ_V_CMP_O_F16__VI 0x00000027 -#define SQ_V_CMP_O_F32__SI__CI 0x00000007 -#define SQ_V_CMP_O_F32__VI 0x00000047 -#define SQ_V_CMP_O_F64__SI__CI 0x00000027 -#define SQ_V_CMP_O_F64__VI 0x00000067 -#define SQ_V_CMP_TRU_F16__VI 0x0000002f -#define SQ_V_CMP_TRU_F32__SI__CI 0x0000000f -#define SQ_V_CMP_TRU_F32__VI 0x0000004f -#define SQ_V_CMP_TRU_F64__SI__CI 0x0000002f -#define SQ_V_CMP_TRU_F64__VI 0x0000006f -#define SQ_V_CMP_T_I16__VI 0x000000a7 -#define SQ_V_CMP_T_I32__SI__CI 0x00000087 -#define SQ_V_CMP_T_I32__VI 0x000000c7 -#define SQ_V_CMP_T_I64__SI__CI 0x000000a7 -#define SQ_V_CMP_T_I64__VI 0x000000e7 -#define SQ_V_CMP_T_U16__VI 0x000000af -#define SQ_V_CMP_T_U32__SI__CI 0x000000c7 -#define SQ_V_CMP_T_U32__VI 0x000000cf -#define SQ_V_CMP_T_U64__SI__CI 0x000000e7 -#define SQ_V_CMP_T_U64__VI 0x000000ef -#define SQ_V_CMP_U_F16__VI 0x00000028 -#define SQ_V_CMP_U_F32__SI__CI 0x00000008 -#define SQ_V_CMP_U_F32__VI 0x00000048 -#define SQ_V_CMP_U_F64__SI__CI 0x00000028 -#define SQ_V_CMP_U_F64__VI 0x00000068 -#define SQ_V_COS_F16__VI 0x0000004a -#define SQ_V_COS_F32__SI__CI 0x00000036 -#define SQ_V_COS_F32__VI 0x0000002a -#define SQ_V_CUBEID_F32__SI__CI 0x00000144 -#define SQ_V_CUBEID_F32__VI 0x000001c4 -#define SQ_V_CUBEMA_F32__SI__CI 0x00000147 -#define SQ_V_CUBEMA_F32__VI 0x000001c7 -#define SQ_V_CUBESC_F32__SI__CI 0x00000145 -#define SQ_V_CUBESC_F32__VI 0x000001c5 -#define SQ_V_CUBETC_F32__SI__CI 0x00000146 -#define SQ_V_CUBETC_F32__VI 0x000001c6 -#define SQ_V_CVT_F16_I16__VI 0x0000003a -#define SQ_V_CVT_F16_U16__VI 0x00000039 -#define SQ_V_CVT_I16_F16__VI 0x0000003c -#define SQ_V_CVT_NORM_I16_F16__VI 0x0000004d -#define SQ_V_CVT_NORM_U16_F16__VI 0x0000004e -#define SQ_V_CVT_PKACCUM_U8_F32__SI__CI 0x0000002c -#define SQ_V_CVT_PKACCUM_U8_F32__VI 0x000001f0 -#define SQ_V_CVT_PKNORM_I16_F16__VI 0x00000299 -#define SQ_V_CVT_PKNORM_I16_F32__SI__CI 0x0000002d -#define SQ_V_CVT_PKNORM_I16_F32__VI 0x00000294 -#define SQ_V_CVT_PKNORM_U16_F16__VI 0x0000029a -#define SQ_V_CVT_PKNORM_U16_F32__SI__CI 0x0000002e -#define SQ_V_CVT_PKNORM_U16_F32__VI 0x00000295 -#define SQ_V_CVT_PKRTZ_F16_F32__SI__CI 0x0000002f -#define SQ_V_CVT_PKRTZ_F16_F32__VI 0x00000296 -#define SQ_V_CVT_PK_I16_I32__SI__CI 0x00000031 -#define SQ_V_CVT_PK_I16_I32__VI 0x00000298 -#define SQ_V_CVT_PK_U16_U32__SI__CI 0x00000030 -#define SQ_V_CVT_PK_U16_U32__VI 0x00000297 -#define SQ_V_CVT_PK_U8_F32__SI__CI 0x0000015e -#define SQ_V_CVT_PK_U8_F32__VI 0x000001dd -#define SQ_V_CVT_U16_F16__VI 0x0000003b -#define SQ_V_DIV_FIXUP_F16__VI 0x000001ef -#define SQ_V_DIV_FIXUP_F32__SI__CI 0x0000015f -#define SQ_V_DIV_FIXUP_F32__VI 0x000001de -#define SQ_V_DIV_FIXUP_F64__SI__CI 0x00000160 -#define SQ_V_DIV_FIXUP_F64__VI 0x000001df -#define SQ_V_DIV_FMAS_F32__SI__CI 0x0000016f -#define SQ_V_DIV_FMAS_F32__VI 0x000001e2 -#define SQ_V_DIV_FMAS_F64__SI__CI 0x00000170 -#define SQ_V_DIV_FMAS_F64__VI 0x000001e3 -#define SQ_V_DIV_SCALE_F32__SI__CI 0x0000016d -#define SQ_V_DIV_SCALE_F32__VI 0x000001e0 -#define SQ_V_DIV_SCALE_F64__SI__CI 0x0000016e -#define SQ_V_DIV_SCALE_F64__VI 0x000001e1 -#define SQ_V_EXP_F16__VI 0x00000041 -#define SQ_V_EXP_F32__SI__CI 0x00000025 -#define SQ_V_EXP_F32__VI 0x00000020 -#define SQ_V_EXP_LEGACY_F32__VI 0x0000004b -#define SQ_V_FFBH_I32__SI__CI 0x0000003b -#define SQ_V_FFBH_I32__VI 0x0000002f -#define SQ_V_FFBH_U32__SI__CI 0x00000039 -#define SQ_V_FFBH_U32__VI 0x0000002d -#define SQ_V_FFBL_B32__SI__CI 0x0000003a -#define SQ_V_FFBL_B32__VI 0x0000002e -#define SQ_V_FLOOR_F16__VI 0x00000044 -#define SQ_V_FLOOR_F32__SI__CI 0x00000024 -#define SQ_V_FLOOR_F32__VI 0x0000001f -#define SQ_V_FMA_F16__VI 0x000001ee -#define SQ_V_FMA_F32__SI__CI 0x0000014b -#define SQ_V_FMA_F32__VI 0x000001cb -#define SQ_V_FMA_F64__SI__CI 0x0000014c -#define SQ_V_FMA_F64__VI 0x000001cc -#define SQ_V_FRACT_F16__VI 0x00000048 -#define SQ_V_FRACT_F32__SI__CI 0x00000020 -#define SQ_V_FRACT_F32__VI 0x0000001b -#define SQ_V_FRACT_F64__SI__CI 0x0000003e -#define SQ_V_FRACT_F64__VI 0x00000032 -#define SQ_V_FREXP_EXP_I16_F16__VI 0x00000043 -#define SQ_V_FREXP_EXP_I32_F32__SI__CI 0x0000003f -#define SQ_V_FREXP_EXP_I32_F32__VI 0x00000033 -#define SQ_V_FREXP_EXP_I32_F64__SI__CI 0x0000003c -#define SQ_V_FREXP_EXP_I32_F64__VI 0x00000030 -#define SQ_V_FREXP_MANT_F16__VI 0x00000042 -#define SQ_V_FREXP_MANT_F32__SI__CI 0x00000040 -#define SQ_V_FREXP_MANT_F32__VI 0x00000034 -#define SQ_V_FREXP_MANT_F64__SI__CI 0x0000003d -#define SQ_V_FREXP_MANT_F64__VI 0x00000031 -#define SQ_V_INTERP_P1LL_F16__VI 0x00000274 -#define SQ_V_INTERP_P1LV_F16__VI 0x00000275 -#define SQ_V_INTERP_P2_F16__VI 0x00000276 -#define SQ_V_INTRP_COUNT__VI 0x00000004 -#define SQ_V_INTRP_OFFSET__VI 0x00000270 -#define SQ_V_LDEXP_F16__VI 0x00000033 -#define SQ_V_LDEXP_F32__SI__CI 0x0000002b -#define SQ_V_LDEXP_F32__VI 0x00000288 -#define SQ_V_LDEXP_F64__SI__CI 0x00000168 -#define SQ_V_LDEXP_F64__VI 0x00000284 -#define SQ_V_LERP_U8__SI__CI 0x0000014d -#define SQ_V_LERP_U8__VI 0x000001cd -#define SQ_V_LOG_F16__VI 0x00000040 -#define SQ_V_LOG_F32__SI__CI 0x00000027 -#define SQ_V_LOG_F32__VI 0x00000021 -#define SQ_V_LOG_LEGACY_F32__VI 0x0000004c -#define SQ_V_LSHLREV_B16__VI 0x0000002a -#define SQ_V_LSHLREV_B32__SI__CI 0x0000001a -#define SQ_V_LSHLREV_B32__VI 0x00000012 -#define SQ_V_LSHLREV_B64__VI 0x0000028f -#define SQ_V_LSHRREV_B16__VI 0x0000002b -#define SQ_V_LSHRREV_B32__SI__CI 0x00000016 -#define SQ_V_LSHRREV_B32__VI 0x00000010 -#define SQ_V_LSHRREV_B64__VI 0x00000290 -#define SQ_V_MAC_F16__VI 0x00000023 -#define SQ_V_MAC_F32__SI__CI 0x0000001f -#define SQ_V_MAC_F32__VI 0x00000016 -#define SQ_V_MAC_LEGACY_F32__SI__CI 0x00000006 -#define SQ_V_MAC_LEGACY_F32__VI 0x0000028e -#define SQ_V_MADAK_F16__VI 0x00000025 -#define SQ_V_MADAK_F32__SI__CI 0x00000021 -#define SQ_V_MADAK_F32__VI 0x00000018 -#define SQ_V_MADMK_F16__VI 0x00000024 -#define SQ_V_MADMK_F32__SI__CI 0x00000020 -#define SQ_V_MADMK_F32__VI 0x00000017 -#define SQ_V_MAD_F16__VI 0x000001ea -#define SQ_V_MAD_F32__SI__CI 0x00000141 -#define SQ_V_MAD_F32__VI 0x000001c1 -#define SQ_V_MAD_I16__VI 0x000001ec -#define SQ_V_MAD_I32_I24__SI__CI 0x00000142 -#define SQ_V_MAD_I32_I24__VI 0x000001c2 -#define SQ_V_MAD_I64_I32__VI 0x000001e9 -#define SQ_V_MAD_LEGACY_F32__SI__CI 0x00000140 -#define SQ_V_MAD_LEGACY_F32__VI 0x000001c0 -#define SQ_V_MAD_U16__VI 0x000001eb -#define SQ_V_MAD_U32_U24__SI__CI 0x00000143 -#define SQ_V_MAD_U32_U24__VI 0x000001c3 -#define SQ_V_MAD_U64_U32__VI 0x000001e8 -#define SQ_V_MAX3_F32__SI__CI 0x00000154 -#define SQ_V_MAX3_F32__VI 0x000001d3 -#define SQ_V_MAX3_I32__SI__CI 0x00000155 -#define SQ_V_MAX3_I32__VI 0x000001d4 -#define SQ_V_MAX3_U32__SI__CI 0x00000156 -#define SQ_V_MAX3_U32__VI 0x000001d5 -#define SQ_V_MAX_F16__VI 0x0000002d -#define SQ_V_MAX_F32__SI__CI 0x00000010 -#define SQ_V_MAX_F32__VI 0x0000000b -#define SQ_V_MAX_F64__SI__CI 0x00000167 -#define SQ_V_MAX_F64__VI 0x00000283 -#define SQ_V_MAX_I16__VI 0x00000030 -#define SQ_V_MAX_I32__SI__CI 0x00000012 -#define SQ_V_MAX_I32__VI 0x0000000d -#define SQ_V_MAX_U16__VI 0x0000002f -#define SQ_V_MAX_U32__SI__CI 0x00000014 -#define SQ_V_MAX_U32__VI 0x0000000f -#define SQ_V_MBCNT_HI_U32_B32__SI__CI 0x00000024 -#define SQ_V_MBCNT_HI_U32_B32__VI 0x0000028d -#define SQ_V_MBCNT_LO_U32_B32__SI__CI 0x00000023 -#define SQ_V_MBCNT_LO_U32_B32__VI 0x0000028c -#define SQ_V_MED3_F32__SI__CI 0x00000157 -#define SQ_V_MED3_F32__VI 0x000001d6 -#define SQ_V_MED3_I32__SI__CI 0x00000158 -#define SQ_V_MED3_I32__VI 0x000001d7 -#define SQ_V_MED3_U32__SI__CI 0x00000159 -#define SQ_V_MED3_U32__VI 0x000001d8 -#define SQ_V_MIN3_F32__SI__CI 0x00000151 -#define SQ_V_MIN3_F32__VI 0x000001d0 -#define SQ_V_MIN3_I32__SI__CI 0x00000152 -#define SQ_V_MIN3_I32__VI 0x000001d1 -#define SQ_V_MIN3_U32__SI__CI 0x00000153 -#define SQ_V_MIN3_U32__VI 0x000001d2 -#define SQ_V_MIN_F16__VI 0x0000002e -#define SQ_V_MIN_F32__SI__CI 0x0000000f -#define SQ_V_MIN_F32__VI 0x0000000a -#define SQ_V_MIN_F64__SI__CI 0x00000166 -#define SQ_V_MIN_F64__VI 0x00000282 -#define SQ_V_MIN_I16__VI 0x00000032 -#define SQ_V_MIN_I32__SI__CI 0x00000011 -#define SQ_V_MIN_I32__VI 0x0000000c -#define SQ_V_MIN_U16__VI 0x00000031 -#define SQ_V_MIN_U32__SI__CI 0x00000013 -#define SQ_V_MIN_U32__VI 0x0000000e -#define SQ_V_MOVRELD_B32__SI__CI 0x00000042 -#define SQ_V_MOVRELD_B32__VI 0x00000036 -#define SQ_V_MOVRELSD_B32__SI__CI 0x00000044 -#define SQ_V_MOVRELSD_B32__VI 0x00000038 -#define SQ_V_MOVRELS_B32__SI__CI 0x00000043 -#define SQ_V_MOVRELS_B32__VI 0x00000037 -#define SQ_V_MQSAD_PK_U16_U8__VI 0x000001e6 -#define SQ_V_MQSAD_U32_U8__VI 0x000001e7 -#define SQ_V_MSAD_U8__SI__CI 0x00000171 -#define SQ_V_MSAD_U8__VI 0x000001e4 -#define SQ_V_MUL_F16__VI 0x00000022 -#define SQ_V_MUL_F32__SI__CI 0x00000008 -#define SQ_V_MUL_F32__VI 0x00000005 -#define SQ_V_MUL_F64__SI__CI 0x00000165 -#define SQ_V_MUL_F64__VI 0x00000281 -#define SQ_V_MUL_HI_I32__SI__CI 0x0000016c -#define SQ_V_MUL_HI_I32__VI 0x00000287 -#define SQ_V_MUL_HI_I32_I24__SI__CI 0x0000000a -#define SQ_V_MUL_HI_I32_I24__VI 0x00000007 -#define SQ_V_MUL_HI_U32__SI__CI 0x0000016a -#define SQ_V_MUL_HI_U32__VI 0x00000286 -#define SQ_V_MUL_HI_U32_U24__SI__CI 0x0000000c -#define SQ_V_MUL_HI_U32_U24__VI 0x00000009 -#define SQ_V_MUL_I32_I24__SI__CI 0x00000009 -#define SQ_V_MUL_I32_I24__VI 0x00000006 -#define SQ_V_MUL_LEGACY_F32__SI__CI 0x00000007 -#define SQ_V_MUL_LEGACY_F32__VI 0x00000004 -#define SQ_V_MUL_LO_U16__VI 0x00000029 -#define SQ_V_MUL_LO_U32__SI__CI 0x00000169 -#define SQ_V_MUL_LO_U32__VI 0x00000285 -#define SQ_V_MUL_U32_U24__SI__CI 0x0000000b -#define SQ_V_MUL_U32_U24__VI 0x00000008 -#define SQ_V_NOT_B32__SI__CI 0x00000037 -#define SQ_V_NOT_B32__VI 0x0000002b -#define SQ_V_OP1_OFFSET__SI__CI 0x00000180 -#define SQ_V_OP1_OFFSET__VI 0x00000140 -#define SQ_V_OP3_2IN_COUNT__VI 0x00000080 -#define SQ_V_OP3_2IN_OFFSET__VI 0x00000280 -#define SQ_V_OP3_3IN_COUNT__VI 0x000000b0 -#define SQ_V_OP3_3IN_OFFSET__VI 0x000001c0 -#define SQ_V_OP3_INTRP_COUNT__VI 0x0000000c -#define SQ_V_OP3_INTRP_OFFSET__VI 0x00000274 -#define SQ_V_OR_B32__SI__CI 0x0000001c -#define SQ_V_OR_B32__VI 0x00000014 -#define SQ_V_PERM_B32__VI 0x000001ed -#define SQ_V_QSAD_PK_U16_U8__VI 0x000001e5 -#define SQ_V_RCP_F16__VI 0x0000003d -#define SQ_V_RCP_F32__SI__CI 0x0000002a -#define SQ_V_RCP_F32__VI 0x00000022 -#define SQ_V_RCP_F64__SI__CI 0x0000002f -#define SQ_V_RCP_F64__VI 0x00000025 -#define SQ_V_RCP_IFLAG_F32__SI__CI 0x0000002b -#define SQ_V_RCP_IFLAG_F32__VI 0x00000023 -#define SQ_V_READLANE_B32__SI__CI 0x00000001 -#define SQ_V_READLANE_B32__VI 0x00000289 -#define SQ_V_RNDNE_F16__VI 0x00000047 -#define SQ_V_RNDNE_F32__SI__CI 0x00000023 -#define SQ_V_RNDNE_F32__VI 0x0000001e -#define SQ_V_RSQ_F16__VI 0x0000003f -#define SQ_V_RSQ_F32__SI__CI 0x0000002e -#define SQ_V_RSQ_F32__VI 0x00000024 -#define SQ_V_RSQ_F64__SI__CI 0x00000031 -#define SQ_V_RSQ_F64__VI 0x00000026 -#define SQ_V_SAD_HI_U8__SI__CI 0x0000015b -#define SQ_V_SAD_HI_U8__VI 0x000001da -#define SQ_V_SAD_U16__SI__CI 0x0000015c -#define SQ_V_SAD_U16__VI 0x000001db -#define SQ_V_SAD_U32__SI__CI 0x0000015d -#define SQ_V_SAD_U32__VI 0x000001dc -#define SQ_V_SAD_U8__SI__CI 0x0000015a -#define SQ_V_SAD_U8__VI 0x000001d9 -#define SQ_V_SIN_F16__VI 0x00000049 -#define SQ_V_SIN_F32__SI__CI 0x00000035 -#define SQ_V_SIN_F32__VI 0x00000029 -#define SQ_V_SQRT_F16__VI 0x0000003e -#define SQ_V_SQRT_F32__SI__CI 0x00000033 -#define SQ_V_SQRT_F32__VI 0x00000027 -#define SQ_V_SQRT_F64__SI__CI 0x00000034 -#define SQ_V_SQRT_F64__VI 0x00000028 -#define SQ_V_SUBBREV_U32__SI__CI 0x0000002a -#define SQ_V_SUBBREV_U32__VI 0x0000001e -#define SQ_V_SUBB_U32__SI__CI 0x00000029 -#define SQ_V_SUBB_U32__VI 0x0000001d -#define SQ_V_SUBREV_F16__VI 0x00000021 -#define SQ_V_SUBREV_F32__SI__CI 0x00000005 -#define SQ_V_SUBREV_F32__VI 0x00000003 -#define SQ_V_SUBREV_U16__VI 0x00000028 -#define SQ_V_SUBREV_U32__VI 0x0000001b -#define SQ_V_SUB_F16__VI 0x00000020 -#define SQ_V_SUB_F32__SI__CI 0x00000004 -#define SQ_V_SUB_F32__VI 0x00000002 -#define SQ_V_SUB_U16__VI 0x00000027 -#define SQ_V_SUB_U32__VI 0x0000001a -#define SQ_V_TRIG_PREOP_F64__SI__CI 0x00000174 -#define SQ_V_TRIG_PREOP_F64__VI 0x00000292 -#define SQ_V_TRUNC_F16__VI 0x00000046 -#define SQ_V_TRUNC_F32__SI__CI 0x00000021 -#define SQ_V_TRUNC_F32__VI 0x0000001c -#define SQ_V_WRITELANE_B32__SI__CI 0x00000002 -#define SQ_V_WRITELANE_B32__VI 0x0000028a -#define SQ_V_XOR_B32__SI__CI 0x0000001d -#define SQ_V_XOR_B32__VI 0x00000015 -#define SQ_XLATE_VOP3_TO_VINTRP_COUNT__VI 0x00000004 -#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET__VI 0x00000270 -#define SQ_XLATE_VOP3_TO_VOP1_COUNT__VI 0x00000080 -#define SQ_XLATE_VOP3_TO_VOP1_OFFSET__VI 0x00000140 -#define SQ_XLATE_VOP3_TO_VOP2_COUNT__VI 0x00000040 -#define SQ_XLATE_VOP3_TO_VOP2_OFFSET__VI 0x00000100 -#define SQ_XLATE_VOP3_TO_VOPC_COUNT__VI 0x00000100 -#define SQ_XLATE_VOP3_TO_VOPC_OFFSET__VI 0x00000000 -#define SQ_XNACK_MASK_HI__VI 0x00000069 -#define SQ_XNACK_MASK_LO__VI 0x00000068 - -#endif // SI_CI_VI_merged_sq_uc_reg_HEADER -#ifndef __VI___SI__CI_sq_uc_reg_h -#define __VI___SI__CI_sq_uc_reg_h - - -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ds_0_t__SI__CI { - unsigned int offset0 : 8; - unsigned int offset1 : 8; - unsigned int : 1; - unsigned int gds : 1; - unsigned int op : 8; - unsigned int encoding : 6; -} sq_ds_0_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ds_0_t__SI__CI { - unsigned int encoding : 6; - unsigned int op : 8; - unsigned int gds : 1; - unsigned int : 1; - unsigned int offset1 : 8; - unsigned int offset0 : 8; -} sq_ds_0_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_ds_0_t__SI__CI f; -} sq_ds_0_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ds_0_t__VI { - unsigned int offset0 : 8; - unsigned int offset1 : 8; - unsigned int gds : 1; - unsigned int op : 8; - unsigned int : 1; - unsigned int encoding : 6; -} sq_ds_0_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ds_0_t__VI { - unsigned int encoding : 6; - unsigned int : 1; - unsigned int op : 8; - unsigned int gds : 1; - unsigned int offset1 : 8; - unsigned int offset0 : 8; -} sq_ds_0_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_ds_0_t__VI f; -} sq_ds_0_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_ds_1_t { - unsigned int addr : 8; - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int vdst : 8; -} sq_ds_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_ds_1_t { - unsigned int vdst : 8; - unsigned int data1 : 8; - unsigned int data0 : 8; - unsigned int addr : 8; -} sq_ds_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_ds_1_t f; -} sq_ds_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_exp_0_t { - unsigned int en : 4; - unsigned int tgt : 6; - unsigned int compr : 1; - unsigned int done : 1; - unsigned int vm : 1; - unsigned int : 13; - unsigned int encoding : 6; -} sq_exp_0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_exp_0_t { - unsigned int encoding : 6; - unsigned int : 13; - unsigned int vm : 1; - unsigned int done : 1; - unsigned int compr : 1; - unsigned int tgt : 6; - unsigned int en : 4; -} sq_exp_0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_exp_0_t f; -} sq_exp_0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_exp_1_t { - unsigned int vsrc0 : 8; - unsigned int vsrc1 : 8; - unsigned int vsrc2 : 8; - unsigned int vsrc3 : 8; -} sq_exp_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_exp_1_t { - unsigned int vsrc3 : 8; - unsigned int vsrc2 : 8; - unsigned int vsrc1 : 8; - unsigned int vsrc0 : 8; -} sq_exp_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_exp_1_t f; -} sq_exp_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_flat_0_t { - unsigned int : 16; - unsigned int glc : 1; - unsigned int slc : 1; - unsigned int op : 7; - unsigned int : 1; - unsigned int encoding : 6; -} sq_flat_0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_flat_0_t { - unsigned int encoding : 6; - unsigned int : 1; - unsigned int op : 7; - unsigned int slc : 1; - unsigned int glc : 1; - unsigned int : 16; -} sq_flat_0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_flat_0_t f; -} sq_flat_0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_flat_1_t { - unsigned int addr : 8; - unsigned int data : 8; - unsigned int : 7; - unsigned int tfe : 1; - unsigned int vdst : 8; -} sq_flat_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_flat_1_t { - unsigned int vdst : 8; - unsigned int tfe : 1; - unsigned int : 7; - unsigned int data : 8; - unsigned int addr : 8; -} sq_flat_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_flat_1_t f; -} sq_flat_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_inst_t { unsigned int encoding : 32; } sq_inst_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_inst_t { unsigned int encoding : 32; } sq_inst_t; - -#endif -typedef union { - unsigned int val : 32; - sq_inst_t f; -} sq_inst_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mimg_0_t { - unsigned int : 8; - unsigned int dmask : 4; - unsigned int unorm : 1; - unsigned int glc : 1; - unsigned int da : 1; - unsigned int r128 : 1; - unsigned int tfe : 1; - unsigned int lwe : 1; - unsigned int op : 7; - unsigned int slc : 1; - unsigned int encoding : 6; -} sq_mimg_0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mimg_0_t { - unsigned int encoding : 6; - unsigned int slc : 1; - unsigned int op : 7; - unsigned int lwe : 1; - unsigned int tfe : 1; - unsigned int r128 : 1; - unsigned int da : 1; - unsigned int glc : 1; - unsigned int unorm : 1; - unsigned int dmask : 4; - unsigned int : 8; -} sq_mimg_0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_mimg_0_t f; -} sq_mimg_0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mimg_1_t { - unsigned int vaddr : 8; - unsigned int vdata : 8; - unsigned int srsrc : 5; - unsigned int ssamp : 5; - unsigned int : 5; - unsigned int d16__VI : 1; -} sq_mimg_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mimg_1_t { - unsigned int d16__VI : 1; - unsigned int : 5; - unsigned int ssamp : 5; - unsigned int srsrc : 5; - unsigned int vdata : 8; - unsigned int vaddr : 8; -} sq_mimg_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_mimg_1_t f; -} sq_mimg_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mtbuf_0_t__SI__CI { - unsigned int offset : 12; - unsigned int offen : 1; - unsigned int idxen : 1; - unsigned int glc : 1; - unsigned int addr64 : 1; - unsigned int op : 3; - unsigned int dfmt : 4; - unsigned int nfmt : 3; - unsigned int encoding : 6; -} sq_mtbuf_0_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mtbuf_0_t__SI__CI { - unsigned int encoding : 6; - unsigned int nfmt : 3; - unsigned int dfmt : 4; - unsigned int op : 3; - unsigned int addr64 : 1; - unsigned int glc : 1; - unsigned int idxen : 1; - unsigned int offen : 1; - unsigned int offset : 12; -} sq_mtbuf_0_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_mtbuf_0_t__SI__CI f; -} sq_mtbuf_0_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mtbuf_0_t__VI { - unsigned int offset : 12; - unsigned int offen : 1; - unsigned int idxen : 1; - unsigned int glc : 1; - unsigned int op : 4; - unsigned int dfmt : 4; - unsigned int nfmt : 3; - unsigned int encoding : 6; -} sq_mtbuf_0_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mtbuf_0_t__VI { - unsigned int encoding : 6; - unsigned int nfmt : 3; - unsigned int dfmt : 4; - unsigned int op : 4; - unsigned int glc : 1; - unsigned int idxen : 1; - unsigned int offen : 1; - unsigned int offset : 12; -} sq_mtbuf_0_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_mtbuf_0_t__VI f; -} sq_mtbuf_0_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mtbuf_1_t { - unsigned int vaddr : 8; - unsigned int vdata : 8; - unsigned int srsrc : 5; - unsigned int : 1; - unsigned int slc : 1; - unsigned int tfe : 1; - unsigned int soffset : 8; -} sq_mtbuf_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mtbuf_1_t { - unsigned int soffset : 8; - unsigned int tfe : 1; - unsigned int slc : 1; - unsigned int : 1; - unsigned int srsrc : 5; - unsigned int vdata : 8; - unsigned int vaddr : 8; -} sq_mtbuf_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_mtbuf_1_t f; -} sq_mtbuf_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mubuf_0_t { - unsigned int offset : 12; - unsigned int offen : 1; - unsigned int idxen : 1; - unsigned int glc : 1; - unsigned int addr64__SI__CI : 1; - unsigned int lds : 1; - unsigned int slc__VI : 1; - unsigned int op : 7; - unsigned int : 1; - unsigned int encoding : 6; -} sq_mubuf_0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mubuf_0_t { - unsigned int encoding : 6; - unsigned int : 1; - unsigned int op : 7; - unsigned int slc__VI : 1; - unsigned int lds : 1; - unsigned int addr64__SI__CI : 1; - unsigned int glc : 1; - unsigned int idxen : 1; - unsigned int offen : 1; - unsigned int offset : 12; -} sq_mubuf_0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_mubuf_0_t f; -} sq_mubuf_0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mubuf_1_t__SI__CI { - unsigned int vaddr : 8; - unsigned int vdata : 8; - unsigned int srsrc : 5; - unsigned int : 1; - unsigned int slc : 1; - unsigned int tfe : 1; - unsigned int soffset : 8; -} sq_mubuf_1_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mubuf_1_t__SI__CI { - unsigned int soffset : 8; - unsigned int tfe : 1; - unsigned int slc : 1; - unsigned int : 1; - unsigned int srsrc : 5; - unsigned int vdata : 8; - unsigned int vaddr : 8; -} sq_mubuf_1_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_mubuf_1_t__SI__CI f; -} sq_mubuf_1_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_mubuf_1_t__VI { - unsigned int vaddr : 8; - unsigned int vdata : 8; - unsigned int srsrc : 5; - unsigned int : 2; - unsigned int tfe : 1; - unsigned int soffset : 8; -} sq_mubuf_1_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_mubuf_1_t__VI { - unsigned int soffset : 8; - unsigned int tfe : 1; - unsigned int : 2; - unsigned int srsrc : 5; - unsigned int vdata : 8; - unsigned int vaddr : 8; -} sq_mubuf_1_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_mubuf_1_t__VI f; -} sq_mubuf_1_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_smrd_t__SI__CI { - unsigned int offset : 8; - unsigned int imm : 1; - unsigned int sbase : 6; - unsigned int sdst : 7; - unsigned int op : 5; - unsigned int encoding : 5; -} sq_smrd_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_smrd_t__SI__CI { - unsigned int encoding : 5; - unsigned int op : 5; - unsigned int sdst : 7; - unsigned int sbase : 6; - unsigned int imm : 1; - unsigned int offset : 8; -} sq_smrd_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_smrd_t__SI__CI f; -} sq_smrd_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_sop1_t { - unsigned int ssrc0 : 8; - unsigned int op : 8; - unsigned int sdst : 7; - unsigned int encoding : 9; -} sq_sop1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_sop1_t { - unsigned int encoding : 9; - unsigned int sdst : 7; - unsigned int op : 8; - unsigned int ssrc0 : 8; -} sq_sop1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_sop1_t f; -} sq_sop1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_sop2_t { - unsigned int ssrc0 : 8; - unsigned int ssrc1 : 8; - unsigned int sdst : 7; - unsigned int op : 7; - unsigned int encoding : 2; -} sq_sop2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_sop2_t { - unsigned int encoding : 2; - unsigned int op : 7; - unsigned int sdst : 7; - unsigned int ssrc1 : 8; - unsigned int ssrc0 : 8; -} sq_sop2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_sop2_t f; -} sq_sop2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_sopc_t { - unsigned int ssrc0 : 8; - unsigned int ssrc1 : 8; - unsigned int op : 7; - unsigned int encoding : 9; -} sq_sopc_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_sopc_t { - unsigned int encoding : 9; - unsigned int op : 7; - unsigned int ssrc1 : 8; - unsigned int ssrc0 : 8; -} sq_sopc_t; - -#endif -typedef union { - unsigned int val : 32; - sq_sopc_t f; -} sq_sopc_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_sopk_t { - unsigned int simm16 : 16; - unsigned int sdst : 7; - unsigned int op : 5; - unsigned int encoding : 4; -} sq_sopk_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_sopk_t { - unsigned int encoding : 4; - unsigned int op : 5; - unsigned int sdst : 7; - unsigned int simm16 : 16; -} sq_sopk_t; - -#endif -typedef union { - unsigned int val : 32; - sq_sopk_t f; -} sq_sopk_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_sopp_t { - unsigned int simm16 : 16; - unsigned int op : 7; - unsigned int encoding : 9; -} sq_sopp_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_sopp_t { - unsigned int encoding : 9; - unsigned int op : 7; - unsigned int simm16 : 16; -} sq_sopp_t; - -#endif -typedef union { - unsigned int val : 32; - sq_sopp_t f; -} sq_sopp_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vintrp_t { - unsigned int vsrc : 8; - unsigned int attrchan : 2; - unsigned int attr : 6; - unsigned int op : 2; - unsigned int vdst : 8; - unsigned int encoding : 6; -} sq_vintrp_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vintrp_t { - unsigned int encoding : 6; - unsigned int vdst : 8; - unsigned int op : 2; - unsigned int attr : 6; - unsigned int attrchan : 2; - unsigned int vsrc : 8; -} sq_vintrp_t; - -#endif -typedef union { - unsigned int val : 32; - sq_vintrp_t f; -} sq_vintrp_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop1_t { - unsigned int src0 : 9; - unsigned int op : 8; - unsigned int vdst : 8; - unsigned int encoding : 7; -} sq_vop1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop1_t { - unsigned int encoding : 7; - unsigned int vdst : 8; - unsigned int op : 8; - unsigned int src0 : 9; -} sq_vop1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_vop1_t f; -} sq_vop1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop2_t { - unsigned int src0 : 9; - unsigned int vsrc1 : 8; - unsigned int vdst : 8; - unsigned int op : 6; - unsigned int encoding : 1; -} sq_vop2_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop2_t { - unsigned int encoding : 1; - unsigned int op : 6; - unsigned int vdst : 8; - unsigned int vsrc1 : 8; - unsigned int src0 : 9; -} sq_vop2_t; - -#endif -typedef union { - unsigned int val : 32; - sq_vop2_t f; -} sq_vop2_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop3_0_sdst_enc_t__SI__CI { - unsigned int vdst : 8; - unsigned int sdst : 7; - unsigned int : 2; - unsigned int op : 9; - unsigned int encoding : 6; -} sq_vop3_0_sdst_enc_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop3_0_sdst_enc_t__SI__CI { - unsigned int encoding : 6; - unsigned int op : 9; - unsigned int : 2; - unsigned int sdst : 7; - unsigned int vdst : 8; -} sq_vop3_0_sdst_enc_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_vop3_0_sdst_enc_t__SI__CI f; -} sq_vop3_0_sdst_enc_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop3_0_sdst_enc_t__VI { - unsigned int vdst : 8; - unsigned int sdst : 7; - unsigned int clamp : 1; - unsigned int op : 10; - unsigned int encoding : 6; -} sq_vop3_0_sdst_enc_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop3_0_sdst_enc_t__VI { - unsigned int encoding : 6; - unsigned int op : 10; - unsigned int clamp : 1; - unsigned int sdst : 7; - unsigned int vdst : 8; -} sq_vop3_0_sdst_enc_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_vop3_0_sdst_enc_t__VI f; -} sq_vop3_0_sdst_enc_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop3_0_t__SI__CI { - unsigned int vdst : 8; - unsigned int abs : 3; - unsigned int clamp : 1; - unsigned int : 5; - unsigned int op : 9; - unsigned int encoding : 6; -} sq_vop3_0_t__SI__CI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop3_0_t__SI__CI { - unsigned int encoding : 6; - unsigned int op : 9; - unsigned int : 5; - unsigned int clamp : 1; - unsigned int abs : 3; - unsigned int vdst : 8; -} sq_vop3_0_t__SI__CI; - -#endif -typedef union { - unsigned int val : 32; - sq_vop3_0_t__SI__CI f; -} sq_vop3_0_u__SI__CI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop3_0_t__VI { - unsigned int vdst : 8; - unsigned int abs : 3; - unsigned int : 4; - unsigned int clamp : 1; - unsigned int op : 10; - unsigned int encoding : 6; -} sq_vop3_0_t__VI; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop3_0_t__VI { - unsigned int encoding : 6; - unsigned int op : 10; - unsigned int clamp : 1; - unsigned int : 4; - unsigned int abs : 3; - unsigned int vdst : 8; -} sq_vop3_0_t__VI; - -#endif -typedef union { - unsigned int val : 32; - sq_vop3_0_t__VI f; -} sq_vop3_0_u__VI; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop3_1_t { - unsigned int src0 : 9; - unsigned int src1 : 9; - unsigned int src2 : 9; - unsigned int omod : 2; - unsigned int neg : 3; -} sq_vop3_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop3_1_t { - unsigned int neg : 3; - unsigned int omod : 2; - unsigned int src2 : 9; - unsigned int src1 : 9; - unsigned int src0 : 9; -} sq_vop3_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_vop3_1_t f; -} sq_vop3_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vopc_t { - unsigned int src0 : 9; - unsigned int vsrc1 : 8; - unsigned int op : 8; - unsigned int encoding : 7; -} sq_vopc_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vopc_t { - unsigned int encoding : 7; - unsigned int op : 8; - unsigned int vsrc1 : 8; - unsigned int src0 : 9; -} sq_vopc_t; - -#endif -typedef union { - unsigned int val : 32; - sq_vopc_t f; -} sq_vopc_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_smem_0_t { - unsigned int sbase : 6; - unsigned int sdata : 7; - unsigned int : 3; - unsigned int glc : 1; - unsigned int imm : 1; - unsigned int op : 8; - unsigned int encoding : 6; -} sq_smem_0_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_smem_0_t { - unsigned int encoding : 6; - unsigned int op : 8; - unsigned int imm : 1; - unsigned int glc : 1; - unsigned int : 3; - unsigned int sdata : 7; - unsigned int sbase : 6; -} sq_smem_0_t; - -#endif -typedef union { - unsigned int val : 32; - sq_smem_0_t f; -} sq_smem_0_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_smem_1_t { - unsigned int offset : 20; - unsigned int : 12; -} sq_smem_1_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_smem_1_t { - unsigned int : 12; - unsigned int offset : 20; -} sq_smem_1_t; - -#endif -typedef union { - unsigned int val : 32; - sq_smem_1_t f; -} sq_smem_1_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop_dpp_t { - unsigned int src0 : 8; - unsigned int dpp_ctrl : 9; - unsigned int : 2; - unsigned int bound_ctrl : 1; - unsigned int src0_neg : 1; - unsigned int src0_abs : 1; - unsigned int src1_neg : 1; - unsigned int src1_abs : 1; - unsigned int bank_mask : 4; - unsigned int row_mask : 4; -} sq_vop_dpp_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop_dpp_t { - unsigned int row_mask : 4; - unsigned int bank_mask : 4; - unsigned int src1_abs : 1; - unsigned int src1_neg : 1; - unsigned int src0_abs : 1; - unsigned int src0_neg : 1; - unsigned int bound_ctrl : 1; - unsigned int : 2; - unsigned int dpp_ctrl : 9; - unsigned int src0 : 8; -} sq_vop_dpp_t; - -#endif -typedef union { - unsigned int val : 32; - sq_vop_dpp_t f; -} sq_vop_dpp_u; - - -#if defined(LITTLEENDIAN_CPU) -typedef struct _sq_vop_sdwa_t { - unsigned int src0 : 8; - unsigned int dst_sel : 3; - unsigned int dst_unused : 2; - unsigned int clamp : 1; - unsigned int : 2; - unsigned int src0_sel : 3; - unsigned int src0_sext : 1; - unsigned int src0_neg : 1; - unsigned int src0_abs : 1; - unsigned int : 2; - unsigned int src1_sel : 3; - unsigned int src1_sext : 1; - unsigned int src1_neg : 1; - unsigned int src1_abs : 1; - unsigned int : 2; -} sq_vop_sdwa_t; - -#elif defined(BIGENDIAN_CPU) -typedef struct _sq_vop_sdwa_t { - unsigned int : 2; - unsigned int src1_abs : 1; - unsigned int src1_neg : 1; - unsigned int src1_sext : 1; - unsigned int src1_sel : 3; - unsigned int : 2; - unsigned int src0_abs : 1; - unsigned int src0_neg : 1; - unsigned int src0_sext : 1; - unsigned int src0_sel : 3; - unsigned int : 2; - unsigned int clamp : 1; - unsigned int dst_unused : 2; - unsigned int dst_sel : 3; - unsigned int src0 : 8; -} sq_vop_sdwa_t; - -#endif -typedef union { - unsigned int val : 32; - sq_vop_sdwa_t f; -} sq_vop_sdwa_u; - - -#endif // __VI___SI__CI_sq_uc_reg_h diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_typedef.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_typedef.h deleted file mode 100644 index 2adbbcc5e2..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_ci_vi_merged_typedef.h +++ /dev/null @@ -1,12452 +0,0 @@ -#if !defined(SI_CI_VI_MERGED_TYPEDEF_HEADER) -#define SI_CI_VI_MERGED_TYPEDEF_HEADER - - -// * -// * -// * (c) 2014 AMD Inc. (unpublished) -// * -// * All rights reserved. This notice is intended as a precaution against -// * inadvertent publication and does not imply publication or any waiver -// * of confidentiality. The year included in the foregoing notice is the -// * year of creation of the work. -// -// - -#include "si_ci_vi_merged_registers.h" - -typedef union ABM_DEBUG_01__SI regABM_DEBUG_01__SI; -typedef union ABM_DEBUG_02__SI regABM_DEBUG_02__SI; -typedef union ABM_DEBUG_03__SI regABM_DEBUG_03__SI; -typedef union ABM_DEBUG_04__SI regABM_DEBUG_04__SI; -typedef union ABM_DEBUG_05__SI regABM_DEBUG_05__SI; -typedef union ABM_DEBUG_06__SI regABM_DEBUG_06__SI; -typedef union ABM_DEBUG_07__SI regABM_DEBUG_07__SI; -typedef union ABM_DEBUG_08__SI regABM_DEBUG_08__SI; -typedef union ABM_DEBUG_09__SI regABM_DEBUG_09__SI; -typedef union ABM_DEBUG_10__SI regABM_DEBUG_10__SI; -typedef union ABM_DEBUG_11__SI regABM_DEBUG_11__SI; -typedef union ABM_DEBUG_12__SI regABM_DEBUG_12__SI; -typedef union ABM_DEBUG_ID__SI regABM_DEBUG_ID__SI; -typedef union ABM_RBBMIF_RDWR_TIMEOUT__SI regABM_RBBMIF_RDWR_TIMEOUT__SI; -typedef union ABM_TEST_DEBUG_DATA__SI regABM_TEST_DEBUG_DATA__SI; -typedef union ABM_TEST_DEBUG_INDEX__SI regABM_TEST_DEBUG_INDEX__SI; -typedef union ACP_CONFIG__CI regACP_CONFIG__CI; -typedef union ACTIVITY_MONITOR__SI regACTIVITY_MONITOR__SI; -typedef union ACTIVITY_THRESHOLDS__SI regACTIVITY_THRESHOLDS__SI; -typedef union ADAPTER_ID regADAPTER_ID; -typedef union ADAPTER_ID_W regADAPTER_ID_W; -typedef union ADC_INT_CTRL__CI__VI regADC_INT_CTRL__CI__VI; -typedef union ADC_RANGE__CI__VI regADC_RANGE__CI__VI; -typedef union AFMT_60958_0__SI regAFMT_60958_0__SI; -typedef union AFMT_60958_1__SI regAFMT_60958_1__SI; -typedef union AFMT_60958_2__SI regAFMT_60958_2__SI; -typedef union AFMT_ACP__SI regAFMT_ACP__SI; -typedef union AFMT_AUDIO_CRC_CONTROL__SI regAFMT_AUDIO_CRC_CONTROL__SI; -typedef union AFMT_AUDIO_CRC_RESULT__SI regAFMT_AUDIO_CRC_RESULT__SI; -typedef union AFMT_AUDIO_INFO0__SI regAFMT_AUDIO_INFO0__SI; -typedef union AFMT_AUDIO_INFO1__SI regAFMT_AUDIO_INFO1__SI; -typedef union AFMT_AUDIO_PACKET_CONTROL2__SI regAFMT_AUDIO_PACKET_CONTROL2__SI; -typedef union AFMT_AUDIO_PACKET_CONTROL__SI regAFMT_AUDIO_PACKET_CONTROL__SI; -typedef union AFMT_AVI_INFO0__SI regAFMT_AVI_INFO0__SI; -typedef union AFMT_AVI_INFO1__SI regAFMT_AVI_INFO1__SI; -typedef union AFMT_AVI_INFO2__SI regAFMT_AVI_INFO2__SI; -typedef union AFMT_AVI_INFO3__SI regAFMT_AVI_INFO3__SI; -typedef union AFMT_GENERIC0_0__SI regAFMT_GENERIC0_0__SI; -typedef union AFMT_GENERIC0_1__SI regAFMT_GENERIC0_1__SI; -typedef union AFMT_GENERIC0_2__SI regAFMT_GENERIC0_2__SI; -typedef union AFMT_GENERIC0_3__SI regAFMT_GENERIC0_3__SI; -typedef union AFMT_GENERIC0_4__SI regAFMT_GENERIC0_4__SI; -typedef union AFMT_GENERIC0_5__SI regAFMT_GENERIC0_5__SI; -typedef union AFMT_GENERIC0_6__SI regAFMT_GENERIC0_6__SI; -typedef union AFMT_GENERIC0_7__SI regAFMT_GENERIC0_7__SI; -typedef union AFMT_GENERIC0_HDR__SI regAFMT_GENERIC0_HDR__SI; -typedef union AFMT_GENERIC1_0__SI regAFMT_GENERIC1_0__SI; -typedef union AFMT_GENERIC1_1__SI regAFMT_GENERIC1_1__SI; -typedef union AFMT_GENERIC1_2__SI regAFMT_GENERIC1_2__SI; -typedef union AFMT_GENERIC1_3__SI regAFMT_GENERIC1_3__SI; -typedef union AFMT_GENERIC1_4__SI regAFMT_GENERIC1_4__SI; -typedef union AFMT_GENERIC1_5__SI regAFMT_GENERIC1_5__SI; -typedef union AFMT_GENERIC1_6__SI regAFMT_GENERIC1_6__SI; -typedef union AFMT_GENERIC1_HDR__SI regAFMT_GENERIC1_HDR__SI; -typedef union AFMT_INFOFRAME_CONTROL0__SI regAFMT_INFOFRAME_CONTROL0__SI; -typedef union AFMT_INTERRUPT_STATUS__SI regAFMT_INTERRUPT_STATUS__SI; -typedef union AFMT_ISRC1_0__SI regAFMT_ISRC1_0__SI; -typedef union AFMT_ISRC1_1__SI regAFMT_ISRC1_1__SI; -typedef union AFMT_ISRC1_2__SI regAFMT_ISRC1_2__SI; -typedef union AFMT_ISRC1_3__SI regAFMT_ISRC1_3__SI; -typedef union AFMT_ISRC1_4__SI regAFMT_ISRC1_4__SI; -typedef union AFMT_ISRC2_0__SI regAFMT_ISRC2_0__SI; -typedef union AFMT_ISRC2_1__SI regAFMT_ISRC2_1__SI; -typedef union AFMT_ISRC2_2__SI regAFMT_ISRC2_2__SI; -typedef union AFMT_ISRC2_3__SI regAFMT_ISRC2_3__SI; -typedef union AFMT_MPEG_INFO0__SI regAFMT_MPEG_INFO0__SI; -typedef union AFMT_MPEG_INFO1__SI regAFMT_MPEG_INFO1__SI; -typedef union AFMT_RAMP_CONTROL0__SI regAFMT_RAMP_CONTROL0__SI; -typedef union AFMT_RAMP_CONTROL1__SI regAFMT_RAMP_CONTROL1__SI; -typedef union AFMT_RAMP_CONTROL2__SI regAFMT_RAMP_CONTROL2__SI; -typedef union AFMT_RAMP_CONTROL3__SI regAFMT_RAMP_CONTROL3__SI; -typedef union AFMT_STATUS__SI regAFMT_STATUS__SI; -typedef union AFMT_VBI_PACKET_CONTROL__SI regAFMT_VBI_PACKET_CONTROL__SI; -typedef union ALU_ADDER_INPUTS__SI regALU_ADDER_INPUTS__SI; -typedef union ALU_DISP_PARAM1__SI regALU_DISP_PARAM1__SI; -typedef union ALU_DISP_PARAM2__SI regALU_DISP_PARAM2__SI; -typedef union ALU_DISP_PARAM3__SI regALU_DISP_PARAM3__SI; -typedef union ALU_DISP_PARAM4_AND_STATE__SI regALU_DISP_PARAM4_AND_STATE__SI; -typedef union ALU_DISP_PARAM5__SI regALU_DISP_PARAM5__SI; -typedef union ATC_ATS_CNTL__CI__VI regATC_ATS_CNTL__CI__VI; -typedef union ATC_ATS_DEBUG__CI__VI regATC_ATS_DEBUG__CI__VI; -typedef union ATC_ATS_DEFAULT_PAGE_CNTL__CI__VI regATC_ATS_DEFAULT_PAGE_CNTL__CI__VI; -typedef union ATC_ATS_DEFAULT_PAGE_LOW__CI regATC_ATS_DEFAULT_PAGE_LOW__CI; -typedef union ATC_ATS_DEFAULT_PAGE_LOW__VI regATC_ATS_DEFAULT_PAGE_LOW__VI; -typedef union ATC_ATS_FAULT_CNTL__CI__VI regATC_ATS_FAULT_CNTL__CI__VI; -typedef union ATC_ATS_FAULT_DEBUG__CI__VI regATC_ATS_FAULT_DEBUG__CI__VI; -typedef union ATC_ATS_FAULT_STATUS_ADDR__CI__VI regATC_ATS_FAULT_STATUS_ADDR__CI__VI; -typedef union ATC_ATS_FAULT_STATUS_INFO__CI__VI regATC_ATS_FAULT_STATUS_INFO__CI__VI; -typedef union ATC_ATS_STATUS__CI__VI regATC_ATS_STATUS__CI__VI; -typedef union ATC_L1RD_DEBUG_TLB__CI__VI regATC_L1RD_DEBUG_TLB__CI__VI; -typedef union ATC_L1RD_STATUS__CI__VI regATC_L1RD_STATUS__CI__VI; -typedef union ATC_L1WR_DEBUG_TLB__CI__VI regATC_L1WR_DEBUG_TLB__CI__VI; -typedef union ATC_L1WR_STATUS__CI__VI regATC_L1WR_STATUS__CI__VI; -typedef union ATC_L1_ADDRESS_OFFSET__CI__VI regATC_L1_ADDRESS_OFFSET__CI__VI; -typedef union ATC_L1_CNTL__CI__VI regATC_L1_CNTL__CI__VI; -typedef union ATC_L2_CNTL2__CI__VI regATC_L2_CNTL2__CI__VI; -typedef union ATC_L2_CNTL__CI__VI regATC_L2_CNTL__CI__VI; -typedef union ATC_L2_DEBUG2__CI regATC_L2_DEBUG2__CI; -typedef union ATC_L2_DEBUG2__VI regATC_L2_DEBUG2__VI; -typedef union ATC_L2_DEBUG__CI__VI regATC_L2_DEBUG__CI__VI; -typedef union ATC_MISC_CG__CI__VI regATC_MISC_CG__CI__VI; -typedef union ATC_PERFCOUNTER0_CFG__CI__VI regATC_PERFCOUNTER0_CFG__CI__VI; -typedef union ATC_PERFCOUNTER1_CFG__CI__VI regATC_PERFCOUNTER1_CFG__CI__VI; -typedef union ATC_PERFCOUNTER2_CFG__CI__VI regATC_PERFCOUNTER2_CFG__CI__VI; -typedef union ATC_PERFCOUNTER3_CFG__CI__VI regATC_PERFCOUNTER3_CFG__CI__VI; -typedef union ATC_PERFCOUNTER_HI__CI__VI regATC_PERFCOUNTER_HI__CI__VI; -typedef union ATC_PERFCOUNTER_LO__CI__VI regATC_PERFCOUNTER_LO__CI__VI; -typedef union ATC_PERFCOUNTER_RSLT_CNTL__CI__VI regATC_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union ATC_VMID0_PASID_MAPPING__CI__VI regATC_VMID0_PASID_MAPPING__CI__VI; -typedef union ATC_VMID10_PASID_MAPPING__CI__VI regATC_VMID10_PASID_MAPPING__CI__VI; -typedef union ATC_VMID11_PASID_MAPPING__CI__VI regATC_VMID11_PASID_MAPPING__CI__VI; -typedef union ATC_VMID12_PASID_MAPPING__CI__VI regATC_VMID12_PASID_MAPPING__CI__VI; -typedef union ATC_VMID13_PASID_MAPPING__CI__VI regATC_VMID13_PASID_MAPPING__CI__VI; -typedef union ATC_VMID14_PASID_MAPPING__CI__VI regATC_VMID14_PASID_MAPPING__CI__VI; -typedef union ATC_VMID15_PASID_MAPPING__CI__VI regATC_VMID15_PASID_MAPPING__CI__VI; -typedef union ATC_VMID1_PASID_MAPPING__CI__VI regATC_VMID1_PASID_MAPPING__CI__VI; -typedef union ATC_VMID2_PASID_MAPPING__CI__VI regATC_VMID2_PASID_MAPPING__CI__VI; -typedef union ATC_VMID3_PASID_MAPPING__CI__VI regATC_VMID3_PASID_MAPPING__CI__VI; -typedef union ATC_VMID4_PASID_MAPPING__CI__VI regATC_VMID4_PASID_MAPPING__CI__VI; -typedef union ATC_VMID5_PASID_MAPPING__CI__VI regATC_VMID5_PASID_MAPPING__CI__VI; -typedef union ATC_VMID6_PASID_MAPPING__CI__VI regATC_VMID6_PASID_MAPPING__CI__VI; -typedef union ATC_VMID7_PASID_MAPPING__CI__VI regATC_VMID7_PASID_MAPPING__CI__VI; -typedef union ATC_VMID8_PASID_MAPPING__CI__VI regATC_VMID8_PASID_MAPPING__CI__VI; -typedef union ATC_VMID9_PASID_MAPPING__CI__VI regATC_VMID9_PASID_MAPPING__CI__VI; -typedef union ATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI - regATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI; -typedef union ATC_VM_APERTURE0_CNTL2__CI__VI regATC_VM_APERTURE0_CNTL2__CI__VI; -typedef union ATC_VM_APERTURE0_CNTL__CI__VI regATC_VM_APERTURE0_CNTL__CI__VI; -typedef union ATC_VM_APERTURE0_HIGH_ADDR__CI__VI regATC_VM_APERTURE0_HIGH_ADDR__CI__VI; -typedef union ATC_VM_APERTURE0_LOW_ADDR__CI__VI regATC_VM_APERTURE0_LOW_ADDR__CI__VI; -typedef union ATC_VM_APERTURE1_CNTL2__CI__VI regATC_VM_APERTURE1_CNTL2__CI__VI; -typedef union ATC_VM_APERTURE1_CNTL__CI__VI regATC_VM_APERTURE1_CNTL__CI__VI; -typedef union ATC_VM_APERTURE1_HIGH_ADDR__CI__VI regATC_VM_APERTURE1_HIGH_ADDR__CI__VI; -typedef union ATC_VM_APERTURE1_LOW_ADDR__CI__VI regATC_VM_APERTURE1_LOW_ADDR__CI__VI; -typedef union ATTR00__SI regATTR00__SI; -typedef union ATTR01__SI regATTR01__SI; -typedef union ATTR02__SI regATTR02__SI; -typedef union ATTR03__SI regATTR03__SI; -typedef union ATTR04__SI regATTR04__SI; -typedef union ATTR05__SI regATTR05__SI; -typedef union ATTR06__SI regATTR06__SI; -typedef union ATTR07__SI regATTR07__SI; -typedef union ATTR08__SI regATTR08__SI; -typedef union ATTR09__SI regATTR09__SI; -typedef union ATTR0A__SI regATTR0A__SI; -typedef union ATTR0B__SI regATTR0B__SI; -typedef union ATTR0C__SI regATTR0C__SI; -typedef union ATTR0D__SI regATTR0D__SI; -typedef union ATTR0E__SI regATTR0E__SI; -typedef union ATTR0F__SI regATTR0F__SI; -typedef union ATTR10__SI regATTR10__SI; -typedef union ATTR11__SI regATTR11__SI; -typedef union ATTR12__SI regATTR12__SI; -typedef union ATTR13__SI regATTR13__SI; -typedef union ATTR14__SI regATTR14__SI; -typedef union ATTRDR__SI regATTRDR__SI; -typedef union ATTRDW__SI regATTRDW__SI; -typedef union ATTRX__SI regATTRX__SI; -typedef union AUDIO_DESCRIPTOR0__SI regAUDIO_DESCRIPTOR0__SI; -typedef union AUDIO_DESCRIPTOR10__SI regAUDIO_DESCRIPTOR10__SI; -typedef union AUDIO_DESCRIPTOR11__SI regAUDIO_DESCRIPTOR11__SI; -typedef union AUDIO_DESCRIPTOR12__SI regAUDIO_DESCRIPTOR12__SI; -typedef union AUDIO_DESCRIPTOR13__SI regAUDIO_DESCRIPTOR13__SI; -typedef union AUDIO_DESCRIPTOR1__SI regAUDIO_DESCRIPTOR1__SI; -typedef union AUDIO_DESCRIPTOR2__SI regAUDIO_DESCRIPTOR2__SI; -typedef union AUDIO_DESCRIPTOR3__SI regAUDIO_DESCRIPTOR3__SI; -typedef union AUDIO_DESCRIPTOR4__SI regAUDIO_DESCRIPTOR4__SI; -typedef union AUDIO_DESCRIPTOR5__SI regAUDIO_DESCRIPTOR5__SI; -typedef union AUDIO_DESCRIPTOR6__SI regAUDIO_DESCRIPTOR6__SI; -typedef union AUDIO_DESCRIPTOR7__SI regAUDIO_DESCRIPTOR7__SI; -typedef union AUDIO_DESCRIPTOR8__SI regAUDIO_DESCRIPTOR8__SI; -typedef union AUDIO_DESCRIPTOR9__SI regAUDIO_DESCRIPTOR9__SI; -typedef union AUTH_STATE regAUTH_STATE; -typedef union AUXN_IMPCAL__SI regAUXN_IMPCAL__SI; -typedef union AUXP_IMPCAL__SI regAUXP_IMPCAL__SI; -typedef union AUX_ARB_CONTROL__SI regAUX_ARB_CONTROL__SI; -typedef union AUX_CONTROL__SI regAUX_CONTROL__SI; -typedef union AUX_DPHY_RX_CONTROL0__SI regAUX_DPHY_RX_CONTROL0__SI; -typedef union AUX_DPHY_RX_CONTROL1__SI regAUX_DPHY_RX_CONTROL1__SI; -typedef union AUX_DPHY_RX_STATUS__SI regAUX_DPHY_RX_STATUS__SI; -typedef union AUX_DPHY_TX_CONTROL__SI regAUX_DPHY_TX_CONTROL__SI; -typedef union AUX_DPHY_TX_REF_CONTROL__SI regAUX_DPHY_TX_REF_CONTROL__SI; -typedef union AUX_DPHY_TX_STATUS__SI regAUX_DPHY_TX_STATUS__SI; -typedef union AUX_INTERRUPT_CONTROL__SI regAUX_INTERRUPT_CONTROL__SI; -typedef union AUX_LS_DATA__SI regAUX_LS_DATA__SI; -typedef union AUX_LS_STATUS__SI regAUX_LS_STATUS__SI; -typedef union AUX_SW_CONTROL__SI regAUX_SW_CONTROL__SI; -typedef union AUX_SW_DATA__SI regAUX_SW_DATA__SI; -typedef union AUX_SW_STATUS__SI regAUX_SW_STATUS__SI; -typedef union AVP_BCKN_OVL__SI regAVP_BCKN_OVL__SI; -typedef union AVP_CONFIG__SI regAVP_CONFIG__SI; -typedef union AVP_RLC_CONTROL__SI regAVP_RLC_CONTROL__SI; -typedef union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI - regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI; -typedef union AZALIA_AUDIO_DTO_CONTROL__SI regAZALIA_AUDIO_DTO_CONTROL__SI; -typedef union AZALIA_AUDIO_DTO__SI regAZALIA_AUDIO_DTO__SI; -typedef union AZALIA_BDL_DMA_CONTROL__SI regAZALIA_BDL_DMA_CONTROL__SI; -typedef union AZALIA_CHANNEL_COUNT_CONTROL__SI regAZALIA_CHANNEL_COUNT_CONTROL__SI; -typedef union AZALIA_CODEC_CONTROL__SI regAZALIA_CODEC_CONTROL__SI; -typedef union AZALIA_CORB_DMA_CONTROL__SI regAZALIA_CORB_DMA_CONTROL__SI; -typedef union AZALIA_CUMULATIVE_LATENCY_COUNT__SI regAZALIA_CUMULATIVE_LATENCY_COUNT__SI; -typedef union AZALIA_CUMULATIVE_REQUEST_COUNT__SI regAZALIA_CUMULATIVE_REQUEST_COUNT__SI; -typedef union AZALIA_CYCLIC_BUFFER_SYNC__SI regAZALIA_CYCLIC_BUFFER_SYNC__SI; -typedef union AZALIA_DATA_DMA_CONTROL__SI regAZALIA_DATA_DMA_CONTROL__SI; -typedef union AZALIA_DEBUG_A__SI regAZALIA_DEBUG_A__SI; -typedef union AZALIA_DEBUG_B__SI regAZALIA_DEBUG_B__SI; -typedef union AZALIA_DEBUG_C__SI regAZALIA_DEBUG_C__SI; -typedef union AZALIA_DEBUG_D__SI regAZALIA_DEBUG_D__SI; -typedef union AZALIA_DEBUG_E__SI regAZALIA_DEBUG_E__SI; -typedef union AZALIA_DEBUG_F__SI regAZALIA_DEBUG_F__SI; -typedef union AZALIA_DEBUG_G__SI regAZALIA_DEBUG_G__SI; -typedef union AZALIA_DEBUG_H__SI regAZALIA_DEBUG_H__SI; -typedef union AZALIA_DEBUG_ID__SI regAZALIA_DEBUG_ID__SI; -typedef union AZALIA_DEBUG_I__SI regAZALIA_DEBUG_I__SI; -typedef union AZALIA_DEBUG_J__SI regAZALIA_DEBUG_J__SI; -typedef union AZALIA_DEBUG_K__SI regAZALIA_DEBUG_K__SI; -typedef union AZALIA_DEBUG_L__SI regAZALIA_DEBUG_L__SI; -typedef union AZALIA_DEBUG_M__SI regAZALIA_DEBUG_M__SI; -typedef union AZALIA_DEBUG_N__SI regAZALIA_DEBUG_N__SI; -typedef union AZALIA_DEBUG_O__SI regAZALIA_DEBUG_O__SI; -typedef union AZALIA_DEBUG_P__SI regAZALIA_DEBUG_P__SI; -typedef union AZALIA_DEBUG_Q__SI regAZALIA_DEBUG_Q__SI; -typedef union AZALIA_DEBUG_R__SI regAZALIA_DEBUG_R__SI; -typedef union AZALIA_DEBUG_S__SI regAZALIA_DEBUG_S__SI; -typedef union AZALIA_DEBUG__SI regAZALIA_DEBUG__SI; -typedef union AZALIA_DRM_COMMAND__SI regAZALIA_DRM_COMMAND__SI; -typedef union AZALIA_DRM_MASK_FIFO_STATUS__SI regAZALIA_DRM_MASK_FIFO_STATUS__SI; -typedef union AZALIA_DRM_PAYLOAD0__SI regAZALIA_DRM_PAYLOAD0__SI; -typedef union AZALIA_DRM_PAYLOAD1__SI regAZALIA_DRM_PAYLOAD1__SI; -typedef union AZALIA_DRM_PAYLOAD2__SI regAZALIA_DRM_PAYLOAD2__SI; -typedef union AZALIA_DRM_PAYLOAD3__SI regAZALIA_DRM_PAYLOAD3__SI; -typedef union AZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F0_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F0_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F0_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F0_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F0_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F0_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F0_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F0_CODEC_CONVERTER123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F0_CODEC_CONVERTER123_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F0_CODEC_CONVERTER123_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F0_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F0_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F0_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F0_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F0_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F0_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F0_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F0_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F0_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F0_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F0_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F0_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI - regAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI - regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI - regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI - regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI - regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI - regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI - regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI; -typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_ACP_DATA__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_DRM__SI regAZALIA_F0_CODEC_PIN0_CONTROL_DRM__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_HDCP_CONTROL__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_MULTICHANNEL_ENABLE__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC__SI; -typedef union AZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F0_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F0_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__SI - regAZALIA_F0_CODEC_PIN0_PARAMETER_CAPABILITIES__SI; -typedef union AZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F0_CODEC_PIN123_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__SI - regAZALIA_F0_CODEC_PIN123_PARAMETER_CAPABILITIES__SI; -typedef union AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F0_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F0_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F0_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI - regAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI; -typedef union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI - regAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI; -typedef union AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI - regAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI; -typedef union AZALIA_F0_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__SI - regAZALIA_F0_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__SI; -typedef union AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI - regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI; -typedef union AZALIA_F0_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI - regAZALIA_F0_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI; -typedef union AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI - regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI; -typedef union AZALIA_F2_CODEC_CONVERTER0_CONTROL_CHANNEL_STREAM_ID__SI - regAZALIA_F2_CODEC_CONVERTER0_CONTROL_CHANNEL_STREAM_ID__SI; -typedef union AZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F2_CODEC_CONVERTER0_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER_2__SI - regAZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER_2__SI; -typedef union AZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F2_CODEC_CONVERTER0_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_CONVERTER0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F2_CODEC_CONVERTER0_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F2_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F2_CODEC_CONVERTER0_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F2_CODEC_CONVERTER1_CONTROL_CHANNEL_STREAM_ID__SI - regAZALIA_F2_CODEC_CONVERTER1_CONTROL_CHANNEL_STREAM_ID__SI; -typedef union AZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F2_CODEC_CONVERTER1_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER_2__SI - regAZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER_2__SI; -typedef union AZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F2_CODEC_CONVERTER1_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_CONVERTER1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_CONVERTER1_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F2_CODEC_CONVERTER1_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F2_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F2_CODEC_CONVERTER1_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F2_CODEC_CONVERTER2_CONTROL_CHANNEL_STREAM_ID__SI - regAZALIA_F2_CODEC_CONVERTER2_CONTROL_CHANNEL_STREAM_ID__SI; -typedef union AZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F2_CODEC_CONVERTER2_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER_2__SI - regAZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER_2__SI; -typedef union AZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F2_CODEC_CONVERTER2_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_CONVERTER2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_CONVERTER2_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F2_CODEC_CONVERTER2_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F2_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F2_CODEC_CONVERTER2_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F2_CODEC_CONVERTER3_CONTROL_CHANNEL_STREAM_ID__SI - regAZALIA_F2_CODEC_CONVERTER3_CONTROL_CHANNEL_STREAM_ID__SI; -typedef union AZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SI - regAZALIA_F2_CODEC_CONVERTER3_CONTROL_CONVERTER_FORMAT__SI; -typedef union AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER_2__SI - regAZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER_2__SI; -typedef union AZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__SI - regAZALIA_F2_CODEC_CONVERTER3_CONTROL_DIGITAL_CONVERTER__SI; -typedef union AZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_CONVERTER3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_CONVERTER3_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F2_CODEC_CONVERTER3_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F2_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F2_CODEC_CONVERTER3_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__SI - regAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__SI - regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SI - regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SI - regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SI - regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI - regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI - regAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI - regAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI - regAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI - regAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI; -typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI - regAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_ACP_DATA__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_ACP_DATA__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_ACP_INDEX__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR_DATA__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR_DATA__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_CHANNEL_ALLOCATION__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_CHANNEL_ALLOCATION__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_DOWN_MIX_INFO__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_DOWN_MIX_INFO__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_DRM__SI regAZALIA_F2_CODEC_PIN0_CONTROL_DRM__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_HBR__SI regAZALIA_F2_CODEC_PIN0_CONTROL_HBR__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_HDCP_CONTROL__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_LIPSYNC__SI regAZALIA_F2_CODEC_PIN0_CONTROL_LIPSYNC__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL01_ENABLE__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL01_ENABLE__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL23_ENABLE__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL23_ENABLE__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL45_ENABLE__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL45_ENABLE__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL67_ENABLE__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_MULTICHANNEL67_ENABLE__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_UNSOLICITED_RESPONSE__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_UNSOLICITED_RESPONSE__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_DATA__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_DATA__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_INDEX__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_VIDEO_ID_INDEX__SI; -typedef union AZALIA_F2_CODEC_PIN0_CONTROL_WIDGET_CONTROL__SI - regAZALIA_F2_CODEC_PIN0_CONTROL_WIDGET_CONTROL__SI; -typedef union AZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN0_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN0_PARAMETER_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN0_PARAMETER_CONNECTION_LIST_LENGTH__SI - regAZALIA_F2_CODEC_PIN0_PARAMETER_CONNECTION_LIST_LENGTH__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_UNSOLICITED_RESPONSE__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_UNSOLICITED_RESPONSE__SI; -typedef union AZALIA_F2_CODEC_PIN1_CONTROL_WIDGET_CONTROL__SI - regAZALIA_F2_CODEC_PIN1_CONTROL_WIDGET_CONTROL__SI; -typedef union AZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN1_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN1_PARAMETER_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN1_PARAMETER_CONNECTION_LIST_LENGTH__SI - regAZALIA_F2_CODEC_PIN1_PARAMETER_CONNECTION_LIST_LENGTH__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_UNSOLICITED_RESPONSE__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_UNSOLICITED_RESPONSE__SI; -typedef union AZALIA_F2_CODEC_PIN2_CONTROL_WIDGET_CONTROL__SI - regAZALIA_F2_CODEC_PIN2_CONTROL_WIDGET_CONTROL__SI; -typedef union AZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN2_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN2_PARAMETER_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN2_PARAMETER_CONNECTION_LIST_LENGTH__SI - regAZALIA_F2_CODEC_PIN2_PARAMETER_CONNECTION_LIST_LENGTH__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_RESPONSE_PIN_SENSE__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_UNSOLICITED_RESPONSE__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_UNSOLICITED_RESPONSE__SI; -typedef union AZALIA_F2_CODEC_PIN3_CONTROL_WIDGET_CONTROL__SI - regAZALIA_F2_CODEC_PIN3_CONTROL_WIDGET_CONTROL__SI; -typedef union AZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN3_PARAMETER_AUDIO_WIDGET_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__SI - regAZALIA_F2_CODEC_PIN3_PARAMETER_CAPABILITIES__SI; -typedef union AZALIA_F2_CODEC_PIN3_PARAMETER_CONNECTION_LIST_LENGTH__SI - regAZALIA_F2_CODEC_PIN3_PARAMETER_CONNECTION_LIST_LENGTH__SI; -typedef union AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__SI - regAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__SI; -typedef union AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI - regAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI; -typedef union AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI - regAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI; -typedef union AZALIA_HDCP_REQUIRED__SI regAZALIA_HDCP_REQUIRED__SI; -typedef union AZALIA_HOT_PLUG_CONTROL__SI regAZALIA_HOT_PLUG_CONTROL__SI; -typedef union AZALIA_LATENCY_COUNTER_CONTROL__SI regAZALIA_LATENCY_COUNTER_CONTROL__SI; -typedef union AZALIA_POWER_MANAGEMENT_CONTROL__SI regAZALIA_POWER_MANAGEMENT_CONTROL__SI; -typedef union AZALIA_RIRB_AND_DP_CONTROL__SI regAZALIA_RIRB_AND_DP_CONTROL__SI; -typedef union AZALIA_RIRB_INTERRUPT_CONTROL__SI regAZALIA_RIRB_INTERRUPT_CONTROL__SI; -typedef union AZALIA_UNDERFLOW_FILLER_SAMPLE__SI regAZALIA_UNDERFLOW_FILLER_SAMPLE__SI; -typedef union AZALIA_UNSOLICITED_RESPONSE__SI regAZALIA_UNSOLICITED_RESPONSE__SI; -typedef union AZALIA_WALL_CLOCK_LOAD__SI regAZALIA_WALL_CLOCK_LOAD__SI; -typedef union AZALIA_WORSTCASE_LATENCY_COUNT__SI regAZALIA_WORSTCASE_LATENCY_COUNT__SI; -typedef union AZ_TEST_DEBUG_DATA__SI regAZ_TEST_DEBUG_DATA__SI; -typedef union AZ_TEST_DEBUG_INDEX__SI regAZ_TEST_DEBUG_INDEX__SI; -typedef union BACO_CNTL_MISC__CI__VI regBACO_CNTL_MISC__CI__VI; -typedef union BACO_CNTL__CI__VI regBACO_CNTL__CI__VI; -typedef union BASE_ADDR_1 regBASE_ADDR_1; -typedef union BASE_ADDR_2 regBASE_ADDR_2; -typedef union BASE_ADDR_3 regBASE_ADDR_3; -typedef union BASE_ADDR_4 regBASE_ADDR_4; -typedef union BASE_ADDR_5 regBASE_ADDR_5; -typedef union BASE_ADDR_6 regBASE_ADDR_6; -typedef union BASE_CLASS regBASE_CLASS; -typedef union BCI_DEBUG_READ regBCI_DEBUG_READ; -typedef union BIF_AVP_FB_FLUSH__SI regBIF_AVP_FB_FLUSH__SI; -typedef union BIF_BACO_DEBUG_LATCH__CI__VI regBIF_BACO_DEBUG_LATCH__CI__VI; -typedef union BIF_BACO_DEBUG__CI__VI regBIF_BACO_DEBUG__CI__VI; -typedef union BIF_BACO_MSIC__CI regBIF_BACO_MSIC__CI; -typedef union BIF_BUSNUM_CNTL1 regBIF_BUSNUM_CNTL1; -typedef union BIF_BUSNUM_CNTL2 regBIF_BUSNUM_CNTL2; -typedef union BIF_BUSNUM_LIST0 regBIF_BUSNUM_LIST0; -typedef union BIF_BUSNUM_LIST1 regBIF_BUSNUM_LIST1; -typedef union BIF_BUSY_DELAY_CNTR regBIF_BUSY_DELAY_CNTR; -typedef union BIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI regBIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI; -typedef union BIF_CLK_PDWN_DELAY_TIMER__SI__CI regBIF_CLK_PDWN_DELAY_TIMER__SI__CI; -typedef union BIF_CLOCK_CNTL__SI regBIF_CLOCK_CNTL__SI; -typedef union BIF_CP_FB_FLUSH__SI regBIF_CP_FB_FLUSH__SI; -typedef union BIF_DCT_FB_FLUSH__SI regBIF_DCT_FB_FLUSH__SI; -typedef union BIF_DEBUG_CNTL regBIF_DEBUG_CNTL; -typedef union BIF_DEBUG_MUX regBIF_DEBUG_MUX; -typedef union BIF_DEBUG_OUT regBIF_DEBUG_OUT; -typedef union BIF_DEVFUNCNUM_LIST0__CI__VI regBIF_DEVFUNCNUM_LIST0__CI__VI; -typedef union BIF_DEVFUNCNUM_LIST1__CI__VI regBIF_DEVFUNCNUM_LIST1__CI__VI; -typedef union BIF_DOORBELL_CNTL__CI__VI regBIF_DOORBELL_CNTL__CI__VI; -typedef union BIF_FB_EN regBIF_FB_EN; -typedef union BIF_FEATURES_CONTROL_MISC__CI__VI regBIF_FEATURES_CONTROL_MISC__CI__VI; -typedef union BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI - regBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI; -typedef union BIF_IMPCTL_RXCNTL__CI__VI regBIF_IMPCTL_RXCNTL__CI__VI; -typedef union BIF_IMPCTL_SMPLCNTL__CI__VI regBIF_IMPCTL_SMPLCNTL__CI__VI; -typedef union BIF_IMPCTL_TXCNTL_pd__CI__VI regBIF_IMPCTL_TXCNTL_pd__CI__VI; -typedef union BIF_IMPCTL_TXCNTL_pu__CI__VI regBIF_IMPCTL_TXCNTL_pu__CI__VI; -typedef union BIF_LNCNT_RESET__CI regBIF_LNCNT_RESET__CI; -typedef union BIF_PERFCOUNTER0_RESULT__CI__VI regBIF_PERFCOUNTER0_RESULT__CI__VI; -typedef union BIF_PERFCOUNTER1_RESULT__CI__VI regBIF_PERFCOUNTER1_RESULT__CI__VI; -typedef union BIF_PERFMON_CNTL__CI__VI regBIF_PERFMON_CNTL__CI__VI; -typedef union BIF_PIF_TXCLK_SWITCH_TIMER__CI regBIF_PIF_TXCLK_SWITCH_TIMER__CI; -typedef union BIF_PINSTRAP0__SI regBIF_PINSTRAP0__SI; -typedef union BIF_PWDN_COMMAND__CI regBIF_PWDN_COMMAND__CI; -typedef union BIF_PWDN_COMMAND__VI regBIF_PWDN_COMMAND__VI; -typedef union BIF_PWDN_STATUS__CI regBIF_PWDN_STATUS__CI; -typedef union BIF_PWDN_STATUS__VI regBIF_PWDN_STATUS__VI; -typedef union BIF_RESET_CNTL__CI regBIF_RESET_CNTL__CI; -typedef union BIF_RESET_EN__SI__CI regBIF_RESET_EN__SI__CI; -typedef union BIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI regBIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI; -typedef union BIF_RFE_IMPRST_CNTL__CI__VI regBIF_RFE_IMPRST_CNTL__CI__VI; -typedef union BIF_RFE_MASTER_SOFTRST_TRIGGER__CI regBIF_RFE_MASTER_SOFTRST_TRIGGER__CI; -typedef union BIF_RFE_MASTER_SOFTRST_TRIGGER__VI regBIF_RFE_MASTER_SOFTRST_TRIGGER__VI; -typedef union BIF_RFE_MMCFG_CNTL__CI__VI regBIF_RFE_MMCFG_CNTL__CI__VI; -typedef union BIF_RFE_MST_BU_CMDSTATUS__CI__VI regBIF_RFE_MST_BU_CMDSTATUS__CI__VI; -typedef union BIF_RFE_MST_BX_CMDSTATUS__CI__VI regBIF_RFE_MST_BX_CMDSTATUS__CI__VI; -typedef union BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI - regBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI; -typedef union BIF_RFE_MST_TMOUT_STATUS__CI__VI regBIF_RFE_MST_TMOUT_STATUS__CI__VI; -typedef union BIF_RFE_SNOOP_REG__CI__VI regBIF_RFE_SNOOP_REG__CI__VI; -typedef union BIF_RFE_SOFTRST_CNTL__CI regBIF_RFE_SOFTRST_CNTL__CI; -typedef union BIF_RFE_SOFTRST_CNTL__VI regBIF_RFE_SOFTRST_CNTL__VI; -typedef union BIF_SCRATCH0 regBIF_SCRATCH0; -typedef union BIF_SCRATCH1 regBIF_SCRATCH1; -typedef union BIF_SLAVE_PERF_COUNTER0__SI regBIF_SLAVE_PERF_COUNTER0__SI; -typedef union BIF_SLAVE_PERF_COUNTER1__SI regBIF_SLAVE_PERF_COUNTER1__SI; -typedef union BIF_SLAVE_PERF_COUNTER_CNTL__SI regBIF_SLAVE_PERF_COUNTER_CNTL__SI; -typedef union BIF_SLVARB_MODE__CI__VI regBIF_SLVARB_MODE__CI__VI; -typedef union BIF_SSA_DISP_LOWER__CI regBIF_SSA_DISP_LOWER__CI; -typedef union BIF_SSA_DISP_UPPER__CI regBIF_SSA_DISP_UPPER__CI; -typedef union BIF_SSA_GFX0_LOWER__CI regBIF_SSA_GFX0_LOWER__CI; -typedef union BIF_SSA_GFX0_UPPER__CI regBIF_SSA_GFX0_UPPER__CI; -typedef union BIF_SSA_GFX1_LOWER__CI regBIF_SSA_GFX1_LOWER__CI; -typedef union BIF_SSA_GFX1_UPPER__CI regBIF_SSA_GFX1_UPPER__CI; -typedef union BIF_SSA_GFX2_LOWER__CI regBIF_SSA_GFX2_LOWER__CI; -typedef union BIF_SSA_GFX2_UPPER__CI regBIF_SSA_GFX2_UPPER__CI; -typedef union BIF_SSA_GFX3_LOWER__CI regBIF_SSA_GFX3_LOWER__CI; -typedef union BIF_SSA_GFX3_UPPER__CI regBIF_SSA_GFX3_UPPER__CI; -typedef union BIF_SSA_MC_LOWER__CI regBIF_SSA_MC_LOWER__CI; -typedef union BIF_SSA_MC_UPPER__CI regBIF_SSA_MC_UPPER__CI; -typedef union BIF_SSA_PWR_STATUS__CI regBIF_SSA_PWR_STATUS__CI; -typedef union BIF_XDMA_HI__CI__VI regBIF_XDMA_HI__CI__VI; -typedef union BIF_XDMA_LO__CI__VI regBIF_XDMA_LO__CI__VI; -typedef union BIOS_SCRATCH_0 regBIOS_SCRATCH_0; -typedef union BIOS_SCRATCH_1 regBIOS_SCRATCH_1; -typedef union BIOS_SCRATCH_10 regBIOS_SCRATCH_10; -typedef union BIOS_SCRATCH_11 regBIOS_SCRATCH_11; -typedef union BIOS_SCRATCH_12 regBIOS_SCRATCH_12; -typedef union BIOS_SCRATCH_13 regBIOS_SCRATCH_13; -typedef union BIOS_SCRATCH_14 regBIOS_SCRATCH_14; -typedef union BIOS_SCRATCH_15 regBIOS_SCRATCH_15; -typedef union BIOS_SCRATCH_2 regBIOS_SCRATCH_2; -typedef union BIOS_SCRATCH_3 regBIOS_SCRATCH_3; -typedef union BIOS_SCRATCH_4 regBIOS_SCRATCH_4; -typedef union BIOS_SCRATCH_5 regBIOS_SCRATCH_5; -typedef union BIOS_SCRATCH_6 regBIOS_SCRATCH_6; -typedef union BIOS_SCRATCH_7 regBIOS_SCRATCH_7; -typedef union BIOS_SCRATCH_8 regBIOS_SCRATCH_8; -typedef union BIOS_SCRATCH_9 regBIOS_SCRATCH_9; -typedef union BIST regBIST; -typedef union BL1_PWM_ABM_CNTL__SI regBL1_PWM_ABM_CNTL__SI; -typedef union BL1_PWM_AMBIENT_LIGHT_LEVEL__SI regBL1_PWM_AMBIENT_LIGHT_LEVEL__SI; -typedef union BL1_PWM_BL_UPDATE_SAMPLE_RATE__SI regBL1_PWM_BL_UPDATE_SAMPLE_RATE__SI; -typedef union BL1_PWM_CURRENT_ABM_LEVEL__SI regBL1_PWM_CURRENT_ABM_LEVEL__SI; -typedef union BL1_PWM_FINAL_DUTY_CYCLE__SI regBL1_PWM_FINAL_DUTY_CYCLE__SI; -typedef union BL1_PWM_GRP2_REG_LOCK__SI regBL1_PWM_GRP2_REG_LOCK__SI; -typedef union BL1_PWM_MINIMUM_DUTY_CYCLE__SI regBL1_PWM_MINIMUM_DUTY_CYCLE__SI; -typedef union BL1_PWM_TARGET_ABM_LEVEL__SI regBL1_PWM_TARGET_ABM_LEVEL__SI; -typedef union BL1_PWM_USER_LEVEL__SI regBL1_PWM_USER_LEVEL__SI; -typedef union BL_PWM_CNTL2__SI regBL_PWM_CNTL2__SI; -typedef union BL_PWM_CNTL__SI regBL_PWM_CNTL__SI; -typedef union BL_PWM_GRP1_REG_LOCK__SI regBL_PWM_GRP1_REG_LOCK__SI; -typedef union BL_PWM_PERIOD_CNTL__SI regBL_PWM_PERIOD_CNTL__SI; -typedef union BUS_CNTL regBUS_CNTL; -typedef union BWD_CHROMA_BOT_ADDR__SI regBWD_CHROMA_BOT_ADDR__SI; -typedef union BWD_CHROMA_TOP_ADDR__SI regBWD_CHROMA_TOP_ADDR__SI; -typedef union BWD_LUMA_BOT_ADDR__SI regBWD_LUMA_BOT_ADDR__SI; -typedef union BWD_LUMA_TOP_ADDR__SI regBWD_LUMA_TOP_ADDR__SI; -typedef union BX_RESET_EN__CI__VI regBX_RESET_EN__CI__VI; -typedef union CACHE_LINE regCACHE_LINE; -typedef union CAC_ACC_ACP0__CI regCAC_ACC_ACP0__CI; -typedef union CAC_ACC_BCI0__CI regCAC_ACC_BCI0__CI; -typedef union CAC_ACC_BCI1__CI regCAC_ACC_BCI1__CI; -typedef union CAC_ACC_BIF0__CI regCAC_ACC_BIF0__CI; -typedef union CAC_ACC_CB0__CI regCAC_ACC_CB0__CI; -typedef union CAC_ACC_CB1__CI regCAC_ACC_CB1__CI; -typedef union CAC_ACC_CB2__CI regCAC_ACC_CB2__CI; -typedef union CAC_ACC_CB3__CI regCAC_ACC_CB3__CI; -typedef union CAC_ACC_CP0__CI regCAC_ACC_CP0__CI; -typedef union CAC_ACC_CP1__CI regCAC_ACC_CP1__CI; -typedef union CAC_ACC_CP2__CI regCAC_ACC_CP2__CI; -typedef union CAC_ACC_DB0__CI regCAC_ACC_DB0__CI; -typedef union CAC_ACC_DB1__CI regCAC_ACC_DB1__CI; -typedef union CAC_ACC_DB2__CI regCAC_ACC_DB2__CI; -typedef union CAC_ACC_DB3__CI regCAC_ACC_DB3__CI; -typedef union CAC_ACC_DC0__CI regCAC_ACC_DC0__CI; -typedef union CAC_ACC_DC1__CI regCAC_ACC_DC1__CI; -typedef union CAC_ACC_DC2__CI regCAC_ACC_DC2__CI; -typedef union CAC_ACC_DC3__CI regCAC_ACC_DC3__CI; -typedef union CAC_ACC_GDS0__CI regCAC_ACC_GDS0__CI; -typedef union CAC_ACC_GDS1__CI regCAC_ACC_GDS1__CI; -typedef union CAC_ACC_GDS2__CI regCAC_ACC_GDS2__CI; -typedef union CAC_ACC_GDS3__CI regCAC_ACC_GDS3__CI; -typedef union CAC_ACC_IA0__CI regCAC_ACC_IA0__CI; -typedef union CAC_ACC_IDLE_PWR0__CI regCAC_ACC_IDLE_PWR0__CI; -typedef union CAC_ACC_LDS0__CI regCAC_ACC_LDS0__CI; -typedef union CAC_ACC_LDS1__CI regCAC_ACC_LDS1__CI; -typedef union CAC_ACC_LDS2__CI regCAC_ACC_LDS2__CI; -typedef union CAC_ACC_LDS3__CI regCAC_ACC_LDS3__CI; -typedef union CAC_ACC_LOWER_CMON__SI regCAC_ACC_LOWER_CMON__SI; -typedef union CAC_ACC_LOWER_REGION_0__SI regCAC_ACC_LOWER_REGION_0__SI; -typedef union CAC_ACC_LOWER_REGION_10__SI regCAC_ACC_LOWER_REGION_10__SI; -typedef union CAC_ACC_LOWER_REGION_11__SI regCAC_ACC_LOWER_REGION_11__SI; -typedef union CAC_ACC_LOWER_REGION_12__SI regCAC_ACC_LOWER_REGION_12__SI; -typedef union CAC_ACC_LOWER_REGION_13__SI regCAC_ACC_LOWER_REGION_13__SI; -typedef union CAC_ACC_LOWER_REGION_14__SI regCAC_ACC_LOWER_REGION_14__SI; -typedef union CAC_ACC_LOWER_REGION_15__SI regCAC_ACC_LOWER_REGION_15__SI; -typedef union CAC_ACC_LOWER_REGION_1__SI regCAC_ACC_LOWER_REGION_1__SI; -typedef union CAC_ACC_LOWER_REGION_2__SI regCAC_ACC_LOWER_REGION_2__SI; -typedef union CAC_ACC_LOWER_REGION_3__SI regCAC_ACC_LOWER_REGION_3__SI; -typedef union CAC_ACC_LOWER_REGION_4__SI regCAC_ACC_LOWER_REGION_4__SI; -typedef union CAC_ACC_LOWER_REGION_5__SI regCAC_ACC_LOWER_REGION_5__SI; -typedef union CAC_ACC_LOWER_REGION_6__SI regCAC_ACC_LOWER_REGION_6__SI; -typedef union CAC_ACC_LOWER_REGION_7__SI regCAC_ACC_LOWER_REGION_7__SI; -typedef union CAC_ACC_LOWER_REGION_8__SI regCAC_ACC_LOWER_REGION_8__SI; -typedef union CAC_ACC_LOWER_REGION_9__SI regCAC_ACC_LOWER_REGION_9__SI; -typedef union CAC_ACC_MCD0__CI regCAC_ACC_MCD0__CI; -typedef union CAC_ACC_MCD1__CI regCAC_ACC_MCD1__CI; -typedef union CAC_ACC_MCD2__CI regCAC_ACC_MCD2__CI; -typedef union CAC_ACC_MCD3__CI regCAC_ACC_MCD3__CI; -typedef union CAC_ACC_NW_ACP0__CI regCAC_ACC_NW_ACP0__CI; -typedef union CAC_ACC_NW_BCI0__CI regCAC_ACC_NW_BCI0__CI; -typedef union CAC_ACC_NW_BCI1__CI regCAC_ACC_NW_BCI1__CI; -typedef union CAC_ACC_NW_BIF0__CI regCAC_ACC_NW_BIF0__CI; -typedef union CAC_ACC_NW_CB0__CI regCAC_ACC_NW_CB0__CI; -typedef union CAC_ACC_NW_CB1__CI regCAC_ACC_NW_CB1__CI; -typedef union CAC_ACC_NW_CB2__CI regCAC_ACC_NW_CB2__CI; -typedef union CAC_ACC_NW_CB3__CI regCAC_ACC_NW_CB3__CI; -typedef union CAC_ACC_NW_CP0__CI regCAC_ACC_NW_CP0__CI; -typedef union CAC_ACC_NW_CP1__CI regCAC_ACC_NW_CP1__CI; -typedef union CAC_ACC_NW_CP2__CI regCAC_ACC_NW_CP2__CI; -typedef union CAC_ACC_NW_DB0__CI regCAC_ACC_NW_DB0__CI; -typedef union CAC_ACC_NW_DB1__CI regCAC_ACC_NW_DB1__CI; -typedef union CAC_ACC_NW_DB2__CI regCAC_ACC_NW_DB2__CI; -typedef union CAC_ACC_NW_DB3__CI regCAC_ACC_NW_DB3__CI; -typedef union CAC_ACC_NW_DC0__CI regCAC_ACC_NW_DC0__CI; -typedef union CAC_ACC_NW_DC1__CI regCAC_ACC_NW_DC1__CI; -typedef union CAC_ACC_NW_DC2__CI regCAC_ACC_NW_DC2__CI; -typedef union CAC_ACC_NW_DC3__CI regCAC_ACC_NW_DC3__CI; -typedef union CAC_ACC_NW_GDS0__CI regCAC_ACC_NW_GDS0__CI; -typedef union CAC_ACC_NW_GDS1__CI regCAC_ACC_NW_GDS1__CI; -typedef union CAC_ACC_NW_GDS2__CI regCAC_ACC_NW_GDS2__CI; -typedef union CAC_ACC_NW_GDS3__CI regCAC_ACC_NW_GDS3__CI; -typedef union CAC_ACC_NW_IA0__CI regCAC_ACC_NW_IA0__CI; -typedef union CAC_ACC_NW_IDLE_PWR0__CI regCAC_ACC_NW_IDLE_PWR0__CI; -typedef union CAC_ACC_NW_LDS0__CI regCAC_ACC_NW_LDS0__CI; -typedef union CAC_ACC_NW_LDS1__CI regCAC_ACC_NW_LDS1__CI; -typedef union CAC_ACC_NW_LDS2__CI regCAC_ACC_NW_LDS2__CI; -typedef union CAC_ACC_NW_LDS3__CI regCAC_ACC_NW_LDS3__CI; -typedef union CAC_ACC_NW_MCD0__CI regCAC_ACC_NW_MCD0__CI; -typedef union CAC_ACC_NW_MCD1__CI regCAC_ACC_NW_MCD1__CI; -typedef union CAC_ACC_NW_MCD2__CI regCAC_ACC_NW_MCD2__CI; -typedef union CAC_ACC_NW_MCD3__CI regCAC_ACC_NW_MCD3__CI; -typedef union CAC_ACC_NW_PA0__CI regCAC_ACC_NW_PA0__CI; -typedef union CAC_ACC_NW_PA1__CI regCAC_ACC_NW_PA1__CI; -typedef union CAC_ACC_NW_SC0__CI regCAC_ACC_NW_SC0__CI; -typedef union CAC_ACC_NW_SPI0__CI regCAC_ACC_NW_SPI0__CI; -typedef union CAC_ACC_NW_SPI1__CI regCAC_ACC_NW_SPI1__CI; -typedef union CAC_ACC_NW_SPI2__CI regCAC_ACC_NW_SPI2__CI; -typedef union CAC_ACC_NW_SPI3__CI regCAC_ACC_NW_SPI3__CI; -typedef union CAC_ACC_NW_SPI4__CI regCAC_ACC_NW_SPI4__CI; -typedef union CAC_ACC_NW_SPI5__CI regCAC_ACC_NW_SPI5__CI; -typedef union CAC_ACC_NW_SPIM0__CI regCAC_ACC_NW_SPIM0__CI; -typedef union CAC_ACC_NW_SPIM1__CI regCAC_ACC_NW_SPIM1__CI; -typedef union CAC_ACC_NW_SPIM2__CI regCAC_ACC_NW_SPIM2__CI; -typedef union CAC_ACC_NW_SPIM3__CI regCAC_ACC_NW_SPIM3__CI; -typedef union CAC_ACC_NW_SPIM4__CI regCAC_ACC_NW_SPIM4__CI; -typedef union CAC_ACC_NW_SPIM5__CI regCAC_ACC_NW_SPIM5__CI; -typedef union CAC_ACC_NW_SPIM6__CI regCAC_ACC_NW_SPIM6__CI; -typedef union CAC_ACC_NW_SPIM7__CI regCAC_ACC_NW_SPIM7__CI; -typedef union CAC_ACC_NW_SQ0__CI regCAC_ACC_NW_SQ0__CI; -typedef union CAC_ACC_NW_SQ1__CI regCAC_ACC_NW_SQ1__CI; -typedef union CAC_ACC_NW_SQ2__CI regCAC_ACC_NW_SQ2__CI; -typedef union CAC_ACC_NW_SQ3__CI regCAC_ACC_NW_SQ3__CI; -typedef union CAC_ACC_NW_SQ4__CI regCAC_ACC_NW_SQ4__CI; -typedef union CAC_ACC_NW_SQ5__CI regCAC_ACC_NW_SQ5__CI; -typedef union CAC_ACC_NW_SQ6__CI regCAC_ACC_NW_SQ6__CI; -typedef union CAC_ACC_NW_SQ7__CI regCAC_ACC_NW_SQ7__CI; -typedef union CAC_ACC_NW_SQ8__CI regCAC_ACC_NW_SQ8__CI; -typedef union CAC_ACC_NW_SX0__CI regCAC_ACC_NW_SX0__CI; -typedef union CAC_ACC_NW_SX1__CI regCAC_ACC_NW_SX1__CI; -typedef union CAC_ACC_NW_SX2__CI regCAC_ACC_NW_SX2__CI; -typedef union CAC_ACC_NW_TA0__CI regCAC_ACC_NW_TA0__CI; -typedef union CAC_ACC_NW_TCC0__CI regCAC_ACC_NW_TCC0__CI; -typedef union CAC_ACC_NW_TCC1__CI regCAC_ACC_NW_TCC1__CI; -typedef union CAC_ACC_NW_TCC2__CI regCAC_ACC_NW_TCC2__CI; -typedef union CAC_ACC_NW_TCC3__CI regCAC_ACC_NW_TCC3__CI; -typedef union CAC_ACC_NW_TCC4__CI regCAC_ACC_NW_TCC4__CI; -typedef union CAC_ACC_NW_TCP0__CI regCAC_ACC_NW_TCP0__CI; -typedef union CAC_ACC_NW_TCP1__CI regCAC_ACC_NW_TCP1__CI; -typedef union CAC_ACC_NW_TCP2__CI regCAC_ACC_NW_TCP2__CI; -typedef union CAC_ACC_NW_TCP3__CI regCAC_ACC_NW_TCP3__CI; -typedef union CAC_ACC_NW_TCP4__CI regCAC_ACC_NW_TCP4__CI; -typedef union CAC_ACC_NW_TD0__CI regCAC_ACC_NW_TD0__CI; -typedef union CAC_ACC_NW_TD1__CI regCAC_ACC_NW_TD1__CI; -typedef union CAC_ACC_NW_TD2__CI regCAC_ACC_NW_TD2__CI; -typedef union CAC_ACC_NW_TD3__CI regCAC_ACC_NW_TD3__CI; -typedef union CAC_ACC_NW_TD4__CI regCAC_ACC_NW_TD4__CI; -typedef union CAC_ACC_NW_TD5__CI regCAC_ACC_NW_TD5__CI; -typedef union CAC_ACC_NW_UVD0__CI regCAC_ACC_NW_UVD0__CI; -typedef union CAC_ACC_NW_UVD1__CI regCAC_ACC_NW_UVD1__CI; -typedef union CAC_ACC_NW_UVD2__CI regCAC_ACC_NW_UVD2__CI; -typedef union CAC_ACC_NW_UVD3__CI regCAC_ACC_NW_UVD3__CI; -typedef union CAC_ACC_NW_UVD4__CI regCAC_ACC_NW_UVD4__CI; -typedef union CAC_ACC_NW_UVD5__CI regCAC_ACC_NW_UVD5__CI; -typedef union CAC_ACC_NW_UVD6__CI regCAC_ACC_NW_UVD6__CI; -typedef union CAC_ACC_NW_UVD7__CI regCAC_ACC_NW_UVD7__CI; -typedef union CAC_ACC_NW_VCE0__CI regCAC_ACC_NW_VCE0__CI; -typedef union CAC_ACC_NW_VCE1__CI regCAC_ACC_NW_VCE1__CI; -typedef union CAC_ACC_NW_VCE2__CI regCAC_ACC_NW_VCE2__CI; -typedef union CAC_ACC_NW_VCE3__CI regCAC_ACC_NW_VCE3__CI; -typedef union CAC_ACC_NW_VCE4__CI regCAC_ACC_NW_VCE4__CI; -typedef union CAC_ACC_NW_VGT0__CI regCAC_ACC_NW_VGT0__CI; -typedef union CAC_ACC_NW_VGT1__CI regCAC_ACC_NW_VGT1__CI; -typedef union CAC_ACC_NW_VGT2__CI regCAC_ACC_NW_VGT2__CI; -typedef union CAC_ACC_NW_WD0__CI regCAC_ACC_NW_WD0__CI; -typedef union CAC_ACC_NW_XDMA0__CI regCAC_ACC_NW_XDMA0__CI; -typedef union CAC_ACC_NW_XDMA1__CI regCAC_ACC_NW_XDMA1__CI; -typedef union CAC_ACC_NW_XDMA2__CI regCAC_ACC_NW_XDMA2__CI; -typedef union CAC_ACC_NW_XDMA3__CI regCAC_ACC_NW_XDMA3__CI; -typedef union CAC_ACC_NW_XDMA4__CI regCAC_ACC_NW_XDMA4__CI; -typedef union CAC_ACC_NW_XDMA5__CI regCAC_ACC_NW_XDMA5__CI; -typedef union CAC_ACC_PA0__CI regCAC_ACC_PA0__CI; -typedef union CAC_ACC_PA1__CI regCAC_ACC_PA1__CI; -typedef union CAC_ACC_SC0__CI regCAC_ACC_SC0__CI; -typedef union CAC_ACC_SPI0__CI regCAC_ACC_SPI0__CI; -typedef union CAC_ACC_SPI1__CI regCAC_ACC_SPI1__CI; -typedef union CAC_ACC_SPI2__CI regCAC_ACC_SPI2__CI; -typedef union CAC_ACC_SPI3__CI regCAC_ACC_SPI3__CI; -typedef union CAC_ACC_SPI4__CI regCAC_ACC_SPI4__CI; -typedef union CAC_ACC_SPI5__CI regCAC_ACC_SPI5__CI; -typedef union CAC_ACC_SPIM0__CI regCAC_ACC_SPIM0__CI; -typedef union CAC_ACC_SPIM1__CI regCAC_ACC_SPIM1__CI; -typedef union CAC_ACC_SPIM2__CI regCAC_ACC_SPIM2__CI; -typedef union CAC_ACC_SPIM3__CI regCAC_ACC_SPIM3__CI; -typedef union CAC_ACC_SPIM4__CI regCAC_ACC_SPIM4__CI; -typedef union CAC_ACC_SPIM5__CI regCAC_ACC_SPIM5__CI; -typedef union CAC_ACC_SPIM6__CI regCAC_ACC_SPIM6__CI; -typedef union CAC_ACC_SPIM7__CI regCAC_ACC_SPIM7__CI; -typedef union CAC_ACC_SQ0_LOWER__CI regCAC_ACC_SQ0_LOWER__CI; -typedef union CAC_ACC_SQ0_UPPER__CI regCAC_ACC_SQ0_UPPER__CI; -typedef union CAC_ACC_SQ1_LOWER__CI regCAC_ACC_SQ1_LOWER__CI; -typedef union CAC_ACC_SQ1_UPPER__CI regCAC_ACC_SQ1_UPPER__CI; -typedef union CAC_ACC_SQ2_LOWER__CI regCAC_ACC_SQ2_LOWER__CI; -typedef union CAC_ACC_SQ2_UPPER__CI regCAC_ACC_SQ2_UPPER__CI; -typedef union CAC_ACC_SQ3_LOWER__CI regCAC_ACC_SQ3_LOWER__CI; -typedef union CAC_ACC_SQ3_UPPER__CI regCAC_ACC_SQ3_UPPER__CI; -typedef union CAC_ACC_SQ4_LOWER__CI regCAC_ACC_SQ4_LOWER__CI; -typedef union CAC_ACC_SQ4_UPPER__CI regCAC_ACC_SQ4_UPPER__CI; -typedef union CAC_ACC_SQ5_LOWER__CI regCAC_ACC_SQ5_LOWER__CI; -typedef union CAC_ACC_SQ5_UPPER__CI regCAC_ACC_SQ5_UPPER__CI; -typedef union CAC_ACC_SQ6_LOWER__CI regCAC_ACC_SQ6_LOWER__CI; -typedef union CAC_ACC_SQ6_UPPER__CI regCAC_ACC_SQ6_UPPER__CI; -typedef union CAC_ACC_SQ7_LOWER__CI regCAC_ACC_SQ7_LOWER__CI; -typedef union CAC_ACC_SQ7_UPPER__CI regCAC_ACC_SQ7_UPPER__CI; -typedef union CAC_ACC_SQ8_LOWER__CI regCAC_ACC_SQ8_LOWER__CI; -typedef union CAC_ACC_SQ8_UPPER__CI regCAC_ACC_SQ8_UPPER__CI; -typedef union CAC_ACC_SX0__CI regCAC_ACC_SX0__CI; -typedef union CAC_ACC_SX1__CI regCAC_ACC_SX1__CI; -typedef union CAC_ACC_SX2__CI regCAC_ACC_SX2__CI; -typedef union CAC_ACC_TA0__CI regCAC_ACC_TA0__CI; -typedef union CAC_ACC_TCC0__CI regCAC_ACC_TCC0__CI; -typedef union CAC_ACC_TCC1__CI regCAC_ACC_TCC1__CI; -typedef union CAC_ACC_TCC2__CI regCAC_ACC_TCC2__CI; -typedef union CAC_ACC_TCC3__CI regCAC_ACC_TCC3__CI; -typedef union CAC_ACC_TCC4__CI regCAC_ACC_TCC4__CI; -typedef union CAC_ACC_TCP0__CI regCAC_ACC_TCP0__CI; -typedef union CAC_ACC_TCP1__CI regCAC_ACC_TCP1__CI; -typedef union CAC_ACC_TCP2__CI regCAC_ACC_TCP2__CI; -typedef union CAC_ACC_TCP3__CI regCAC_ACC_TCP3__CI; -typedef union CAC_ACC_TCP4__CI regCAC_ACC_TCP4__CI; -typedef union CAC_ACC_TD0__CI regCAC_ACC_TD0__CI; -typedef union CAC_ACC_TD1__CI regCAC_ACC_TD1__CI; -typedef union CAC_ACC_TD2__CI regCAC_ACC_TD2__CI; -typedef union CAC_ACC_TD3__CI regCAC_ACC_TD3__CI; -typedef union CAC_ACC_TD4__CI regCAC_ACC_TD4__CI; -typedef union CAC_ACC_TD5__CI regCAC_ACC_TD5__CI; -typedef union CAC_ACC_UPPER_CMON__SI regCAC_ACC_UPPER_CMON__SI; -typedef union CAC_ACC_UPPER_REGION_0__SI regCAC_ACC_UPPER_REGION_0__SI; -typedef union CAC_ACC_UPPER_REGION_10__SI regCAC_ACC_UPPER_REGION_10__SI; -typedef union CAC_ACC_UPPER_REGION_11__SI regCAC_ACC_UPPER_REGION_11__SI; -typedef union CAC_ACC_UPPER_REGION_12__SI regCAC_ACC_UPPER_REGION_12__SI; -typedef union CAC_ACC_UPPER_REGION_13__SI regCAC_ACC_UPPER_REGION_13__SI; -typedef union CAC_ACC_UPPER_REGION_14__SI regCAC_ACC_UPPER_REGION_14__SI; -typedef union CAC_ACC_UPPER_REGION_15__SI regCAC_ACC_UPPER_REGION_15__SI; -typedef union CAC_ACC_UPPER_REGION_1__SI regCAC_ACC_UPPER_REGION_1__SI; -typedef union CAC_ACC_UPPER_REGION_2__SI regCAC_ACC_UPPER_REGION_2__SI; -typedef union CAC_ACC_UPPER_REGION_3__SI regCAC_ACC_UPPER_REGION_3__SI; -typedef union CAC_ACC_UPPER_REGION_4__SI regCAC_ACC_UPPER_REGION_4__SI; -typedef union CAC_ACC_UPPER_REGION_5__SI regCAC_ACC_UPPER_REGION_5__SI; -typedef union CAC_ACC_UPPER_REGION_6__SI regCAC_ACC_UPPER_REGION_6__SI; -typedef union CAC_ACC_UPPER_REGION_7__SI regCAC_ACC_UPPER_REGION_7__SI; -typedef union CAC_ACC_UPPER_REGION_8__SI regCAC_ACC_UPPER_REGION_8__SI; -typedef union CAC_ACC_UPPER_REGION_9__SI regCAC_ACC_UPPER_REGION_9__SI; -typedef union CAC_ACC_UVD0__CI regCAC_ACC_UVD0__CI; -typedef union CAC_ACC_UVD1__CI regCAC_ACC_UVD1__CI; -typedef union CAC_ACC_UVD2__CI regCAC_ACC_UVD2__CI; -typedef union CAC_ACC_UVD3__CI regCAC_ACC_UVD3__CI; -typedef union CAC_ACC_UVD4__CI regCAC_ACC_UVD4__CI; -typedef union CAC_ACC_UVD5__CI regCAC_ACC_UVD5__CI; -typedef union CAC_ACC_UVD6__CI regCAC_ACC_UVD6__CI; -typedef union CAC_ACC_UVD7__CI regCAC_ACC_UVD7__CI; -typedef union CAC_ACC_VCE0__CI regCAC_ACC_VCE0__CI; -typedef union CAC_ACC_VCE1__CI regCAC_ACC_VCE1__CI; -typedef union CAC_ACC_VCE2__CI regCAC_ACC_VCE2__CI; -typedef union CAC_ACC_VCE3__CI regCAC_ACC_VCE3__CI; -typedef union CAC_ACC_VCE4__CI regCAC_ACC_VCE4__CI; -typedef union CAC_ACC_VGT0__CI regCAC_ACC_VGT0__CI; -typedef union CAC_ACC_VGT1__CI regCAC_ACC_VGT1__CI; -typedef union CAC_ACC_VGT2__CI regCAC_ACC_VGT2__CI; -typedef union CAC_ACC_WD0__CI regCAC_ACC_WD0__CI; -typedef union CAC_ACC_XDMA0__CI regCAC_ACC_XDMA0__CI; -typedef union CAC_ACC_XDMA1__CI regCAC_ACC_XDMA1__CI; -typedef union CAC_ACC_XDMA2__CI regCAC_ACC_XDMA2__CI; -typedef union CAC_ACC_XDMA3__CI regCAC_ACC_XDMA3__CI; -typedef union CAC_ACC_XDMA4__CI regCAC_ACC_XDMA4__CI; -typedef union CAC_ACC_XDMA5__CI regCAC_ACC_XDMA5__CI; -typedef union CAC_AGGR_LOWER__SI__CI regCAC_AGGR_LOWER__SI__CI; -typedef union CAC_AGGR_UPPER__SI__CI regCAC_AGGR_UPPER__SI__CI; -typedef union CAC_OVRRD_ACP__CI regCAC_OVRRD_ACP__CI; -typedef union CAC_OVRRD_BCI__CI regCAC_OVRRD_BCI__CI; -typedef union CAC_OVRRD_BIF__CI regCAC_OVRRD_BIF__CI; -typedef union CAC_OVRRD_BIF__SI regCAC_OVRRD_BIF__SI; -typedef union CAC_OVRRD_CB__CI regCAC_OVRRD_CB__CI; -typedef union CAC_OVRRD_CB__SI regCAC_OVRRD_CB__SI; -typedef union CAC_OVRRD_CP__CI regCAC_OVRRD_CP__CI; -typedef union CAC_OVRRD_CP__SI regCAC_OVRRD_CP__SI; -typedef union CAC_OVRRD_DB__CI regCAC_OVRRD_DB__CI; -typedef union CAC_OVRRD_DB__SI regCAC_OVRRD_DB__SI; -typedef union CAC_OVRRD_DC__CI regCAC_OVRRD_DC__CI; -typedef union CAC_OVRRD_DC__SI regCAC_OVRRD_DC__SI; -typedef union CAC_OVRRD_GDS__CI regCAC_OVRRD_GDS__CI; -typedef union CAC_OVRRD_IA__CI regCAC_OVRRD_IA__CI; -typedef union CAC_OVRRD_IA__SI regCAC_OVRRD_IA__SI; -typedef union CAC_OVRRD_IDLE_PWR__CI regCAC_OVRRD_IDLE_PWR__CI; -typedef union CAC_OVRRD_LDS__CI regCAC_OVRRD_LDS__CI; -typedef union CAC_OVRRD_LDS__SI regCAC_OVRRD_LDS__SI; -typedef union CAC_OVRRD_MCD__CI regCAC_OVRRD_MCD__CI; -typedef union CAC_OVRRD_MC__SI regCAC_OVRRD_MC__SI; -typedef union CAC_OVRRD_PA__CI regCAC_OVRRD_PA__CI; -typedef union CAC_OVRRD_PA__SI regCAC_OVRRD_PA__SI; -typedef union CAC_OVRRD_SC__CI regCAC_OVRRD_SC__CI; -typedef union CAC_OVRRD_SC__SI regCAC_OVRRD_SC__SI; -typedef union CAC_OVRRD_SPIM__CI regCAC_OVRRD_SPIM__CI; -typedef union CAC_OVRRD_SPI__CI regCAC_OVRRD_SPI__CI; -typedef union CAC_OVRRD_SPI__SI regCAC_OVRRD_SPI__SI; -typedef union CAC_OVRRD_SQ__CI regCAC_OVRRD_SQ__CI; -typedef union CAC_OVRRD_SQ__SI regCAC_OVRRD_SQ__SI; -typedef union CAC_OVRRD_SX__CI regCAC_OVRRD_SX__CI; -typedef union CAC_OVRRD_SX__SI regCAC_OVRRD_SX__SI; -typedef union CAC_OVRRD_TA__CI regCAC_OVRRD_TA__CI; -typedef union CAC_OVRRD_TA__SI regCAC_OVRRD_TA__SI; -typedef union CAC_OVRRD_TCC__CI regCAC_OVRRD_TCC__CI; -typedef union CAC_OVRRD_TCC__SI regCAC_OVRRD_TCC__SI; -typedef union CAC_OVRRD_TCP__CI regCAC_OVRRD_TCP__CI; -typedef union CAC_OVRRD_TCP__SI regCAC_OVRRD_TCP__SI; -typedef union CAC_OVRRD_TD__CI regCAC_OVRRD_TD__CI; -typedef union CAC_OVRRD_UVD__CI regCAC_OVRRD_UVD__CI; -typedef union CAC_OVRRD_UVD__SI regCAC_OVRRD_UVD__SI; -typedef union CAC_OVRRD_VCE__CI regCAC_OVRRD_VCE__CI; -typedef union CAC_OVRRD_VCE__SI regCAC_OVRRD_VCE__SI; -typedef union CAC_OVRRD_VGT__CI regCAC_OVRRD_VGT__CI; -typedef union CAC_OVRRD_VGT__SI regCAC_OVRRD_VGT__SI; -typedef union CAC_OVRRD_WD__CI regCAC_OVRRD_WD__CI; -typedef union CAC_OVRRD_XDMA__CI regCAC_OVRRD_XDMA__CI; -typedef union CAC_PCIE_LNCNT_0_ACC_SUM__CI regCAC_PCIE_LNCNT_0_ACC_SUM__CI; -typedef union CAC_PCIE_LNCNT_0_TIME_STAMP__CI regCAC_PCIE_LNCNT_0_TIME_STAMP__CI; -typedef union CAC_PCIE_LNCNT_1_ACC_SUM__CI regCAC_PCIE_LNCNT_1_ACC_SUM__CI; -typedef union CAC_PCIE_LNCNT_1_TIME_STAMP__CI regCAC_PCIE_LNCNT_1_TIME_STAMP__CI; -typedef union CAC_PCIE_LNCNT_2_ACC_SUM__CI regCAC_PCIE_LNCNT_2_ACC_SUM__CI; -typedef union CAC_PCIE_LNCNT_2_TIME_STAMP__CI regCAC_PCIE_LNCNT_2_TIME_STAMP__CI; -typedef union CAC_PCIE_LNCNT_3_ACC_SUM__CI regCAC_PCIE_LNCNT_3_ACC_SUM__CI; -typedef union CAC_PCIE_LNCNT_3_TIME_STAMP__CI regCAC_PCIE_LNCNT_3_TIME_STAMP__CI; -typedef union CAC_PCIE_LNCNT_CNTL__CI regCAC_PCIE_LNCNT_CNTL__CI; -typedef union CAC_SMC_IND_DATA__CI regCAC_SMC_IND_DATA__CI; -typedef union CAC_SMC_IND_INDEX__CI regCAC_SMC_IND_INDEX__CI; -typedef union CAC_THERMAL_STATUS__SI__CI regCAC_THERMAL_STATUS__SI__CI; -typedef union CAC_THRESHOLD_LOWER__SI__CI regCAC_THRESHOLD_LOWER__SI__CI; -typedef union CAC_THRESHOLD_UPPER__SI__CI regCAC_THRESHOLD_UPPER__SI__CI; -typedef union CAC_WEIGHT_ACP_0__CI regCAC_WEIGHT_ACP_0__CI; -typedef union CAC_WEIGHT_BCI_0__CI regCAC_WEIGHT_BCI_0__CI; -typedef union CAC_WEIGHT_BIF_0__SI__CI regCAC_WEIGHT_BIF_0__SI__CI; -typedef union CAC_WEIGHT_CB_0__SI__CI regCAC_WEIGHT_CB_0__SI__CI; -typedef union CAC_WEIGHT_CB_1__SI__CI regCAC_WEIGHT_CB_1__SI__CI; -typedef union CAC_WEIGHT_CP_0__SI__CI regCAC_WEIGHT_CP_0__SI__CI; -typedef union CAC_WEIGHT_CP_1__CI regCAC_WEIGHT_CP_1__CI; -typedef union CAC_WEIGHT_DB_0__SI__CI regCAC_WEIGHT_DB_0__SI__CI; -typedef union CAC_WEIGHT_DB_1__SI__CI regCAC_WEIGHT_DB_1__SI__CI; -typedef union CAC_WEIGHT_DC_0__SI__CI regCAC_WEIGHT_DC_0__SI__CI; -typedef union CAC_WEIGHT_DC_1__SI__CI regCAC_WEIGHT_DC_1__SI__CI; -typedef union CAC_WEIGHT_GDS_0__CI regCAC_WEIGHT_GDS_0__CI; -typedef union CAC_WEIGHT_GDS_1__CI regCAC_WEIGHT_GDS_1__CI; -typedef union CAC_WEIGHT_IA_0__SI__CI regCAC_WEIGHT_IA_0__SI__CI; -typedef union CAC_WEIGHT_IDLE_PWR_0__CI regCAC_WEIGHT_IDLE_PWR_0__CI; -typedef union CAC_WEIGHT_LDS_0__SI__CI regCAC_WEIGHT_LDS_0__SI__CI; -typedef union CAC_WEIGHT_LDS_1__CI regCAC_WEIGHT_LDS_1__CI; -typedef union CAC_WEIGHT_MCD_0__CI regCAC_WEIGHT_MCD_0__CI; -typedef union CAC_WEIGHT_MCD_1__CI regCAC_WEIGHT_MCD_1__CI; -typedef union CAC_WEIGHT_MC_0__SI regCAC_WEIGHT_MC_0__SI; -typedef union CAC_WEIGHT_PA_0__SI__CI regCAC_WEIGHT_PA_0__SI__CI; -typedef union CAC_WEIGHT_SC_0__SI__CI regCAC_WEIGHT_SC_0__SI__CI; -typedef union CAC_WEIGHT_SPIM_0__CI regCAC_WEIGHT_SPIM_0__CI; -typedef union CAC_WEIGHT_SPIM_1__CI regCAC_WEIGHT_SPIM_1__CI; -typedef union CAC_WEIGHT_SPIM_2__CI regCAC_WEIGHT_SPIM_2__CI; -typedef union CAC_WEIGHT_SPIM_3__CI regCAC_WEIGHT_SPIM_3__CI; -typedef union CAC_WEIGHT_SPI_0__SI__CI regCAC_WEIGHT_SPI_0__SI__CI; -typedef union CAC_WEIGHT_SPI_1__SI__CI regCAC_WEIGHT_SPI_1__SI__CI; -typedef union CAC_WEIGHT_SPI_2__SI__CI regCAC_WEIGHT_SPI_2__SI__CI; -typedef union CAC_WEIGHT_SQ_0__SI__CI regCAC_WEIGHT_SQ_0__SI__CI; -typedef union CAC_WEIGHT_SQ_1__SI__CI regCAC_WEIGHT_SQ_1__SI__CI; -typedef union CAC_WEIGHT_SQ_2__CI regCAC_WEIGHT_SQ_2__CI; -typedef union CAC_WEIGHT_SQ_3__CI regCAC_WEIGHT_SQ_3__CI; -typedef union CAC_WEIGHT_SQ_4__CI regCAC_WEIGHT_SQ_4__CI; -typedef union CAC_WEIGHT_SX_0__SI__CI regCAC_WEIGHT_SX_0__SI__CI; -typedef union CAC_WEIGHT_SX_1__SI__CI regCAC_WEIGHT_SX_1__SI__CI; -typedef union CAC_WEIGHT_TA_0__SI__CI regCAC_WEIGHT_TA_0__SI__CI; -typedef union CAC_WEIGHT_TCC_0__SI__CI regCAC_WEIGHT_TCC_0__SI__CI; -typedef union CAC_WEIGHT_TCC_1__SI__CI regCAC_WEIGHT_TCC_1__SI__CI; -typedef union CAC_WEIGHT_TCC_2__SI__CI regCAC_WEIGHT_TCC_2__SI__CI; -typedef union CAC_WEIGHT_TCP_0__SI__CI regCAC_WEIGHT_TCP_0__SI__CI; -typedef union CAC_WEIGHT_TCP_1__CI regCAC_WEIGHT_TCP_1__CI; -typedef union CAC_WEIGHT_TCP_2__CI regCAC_WEIGHT_TCP_2__CI; -typedef union CAC_WEIGHT_TD_0__CI regCAC_WEIGHT_TD_0__CI; -typedef union CAC_WEIGHT_TD_1__CI regCAC_WEIGHT_TD_1__CI; -typedef union CAC_WEIGHT_TD_2__CI regCAC_WEIGHT_TD_2__CI; -typedef union CAC_WEIGHT_UVD_0__SI__CI regCAC_WEIGHT_UVD_0__SI__CI; -typedef union CAC_WEIGHT_UVD_1__SI__CI regCAC_WEIGHT_UVD_1__SI__CI; -typedef union CAC_WEIGHT_UVD_2__SI__CI regCAC_WEIGHT_UVD_2__SI__CI; -typedef union CAC_WEIGHT_UVD_3__SI__CI regCAC_WEIGHT_UVD_3__SI__CI; -typedef union CAC_WEIGHT_VCE_0__SI__CI regCAC_WEIGHT_VCE_0__SI__CI; -typedef union CAC_WEIGHT_VCE_1__SI__CI regCAC_WEIGHT_VCE_1__SI__CI; -typedef union CAC_WEIGHT_VCE_2__SI__CI regCAC_WEIGHT_VCE_2__SI__CI; -typedef union CAC_WEIGHT_VGT_0__SI__CI regCAC_WEIGHT_VGT_0__SI__CI; -typedef union CAC_WEIGHT_VGT_1__SI__CI regCAC_WEIGHT_VGT_1__SI__CI; -typedef union CAC_WEIGHT_WD_0__CI regCAC_WEIGHT_WD_0__CI; -typedef union CAC_WEIGHT_XDMA_0__CI regCAC_WEIGHT_XDMA_0__CI; -typedef union CAC_WEIGHT_XDMA_1__CI regCAC_WEIGHT_XDMA_1__CI; -typedef union CAC_WEIGHT_XDMA_2__CI regCAC_WEIGHT_XDMA_2__CI; -typedef union CAP0_ANC0_OFFSET_HIGH__SI regCAP0_ANC0_OFFSET_HIGH__SI; -typedef union CAP0_ANC0_OFFSET__SI regCAP0_ANC0_OFFSET__SI; -typedef union CAP0_ANC1_OFFSET_HIGH__SI regCAP0_ANC1_OFFSET_HIGH__SI; -typedef union CAP0_ANC1_OFFSET__SI regCAP0_ANC1_OFFSET__SI; -typedef union CAP0_ANC2_OFFSET_HIGH__SI regCAP0_ANC2_OFFSET_HIGH__SI; -typedef union CAP0_ANC2_OFFSET__SI regCAP0_ANC2_OFFSET__SI; -typedef union CAP0_ANC3_OFFSET_HIGH__SI regCAP0_ANC3_OFFSET_HIGH__SI; -typedef union CAP0_ANC3_OFFSET__SI regCAP0_ANC3_OFFSET__SI; -typedef union CAP0_ANC_BUF01_BLOCK_CNT__SI regCAP0_ANC_BUF01_BLOCK_CNT__SI; -typedef union CAP0_ANC_BUF23_BLOCK_CNT__SI regCAP0_ANC_BUF23_BLOCK_CNT__SI; -typedef union CAP0_ANC_H_WINDOW__SI regCAP0_ANC_H_WINDOW__SI; -typedef union CAP0_BUF0_EVEN_OFFSET_HIGH__SI regCAP0_BUF0_EVEN_OFFSET_HIGH__SI; -typedef union CAP0_BUF0_EVEN_OFFSET__SI regCAP0_BUF0_EVEN_OFFSET__SI; -typedef union CAP0_BUF0_OFFSET_HIGH__SI regCAP0_BUF0_OFFSET_HIGH__SI; -typedef union CAP0_BUF0_OFFSET__SI regCAP0_BUF0_OFFSET__SI; -typedef union CAP0_BUF1_EVEN_OFFSET_HIGH__SI regCAP0_BUF1_EVEN_OFFSET_HIGH__SI; -typedef union CAP0_BUF1_EVEN_OFFSET__SI regCAP0_BUF1_EVEN_OFFSET__SI; -typedef union CAP0_BUF1_OFFSET_HIGH__SI regCAP0_BUF1_OFFSET_HIGH__SI; -typedef union CAP0_BUF1_OFFSET__SI regCAP0_BUF1_OFFSET__SI; -typedef union CAP0_BUF_PITCH__SI regCAP0_BUF_PITCH__SI; -typedef union CAP0_BUF_STATUS__SI regCAP0_BUF_STATUS__SI; -typedef union CAP0_CONFIG__SI regCAP0_CONFIG__SI; -typedef union CAP0_DEBUG__SI regCAP0_DEBUG__SI; -typedef union CAP0_H_WINDOW__SI regCAP0_H_WINDOW__SI; -typedef union CAP0_ONESHOT_BUF_OFFSET_HIGH__SI regCAP0_ONESHOT_BUF_OFFSET_HIGH__SI; -typedef union CAP0_ONESHOT_BUF_OFFSET__SI regCAP0_ONESHOT_BUF_OFFSET__SI; -typedef union CAP0_PORT_MODE_CNTL__SI regCAP0_PORT_MODE_CNTL__SI; -typedef union CAP0_TRIG_CNTL__SI regCAP0_TRIG_CNTL__SI; -typedef union CAP0_VBI0_OFFSET_HIGH__SI regCAP0_VBI0_OFFSET_HIGH__SI; -typedef union CAP0_VBI0_OFFSET__SI regCAP0_VBI0_OFFSET__SI; -typedef union CAP0_VBI1_OFFSET_HIGH__SI regCAP0_VBI1_OFFSET_HIGH__SI; -typedef union CAP0_VBI1_OFFSET__SI regCAP0_VBI1_OFFSET__SI; -typedef union CAP0_VBI2_OFFSET_HIGH__SI regCAP0_VBI2_OFFSET_HIGH__SI; -typedef union CAP0_VBI2_OFFSET__SI regCAP0_VBI2_OFFSET__SI; -typedef union CAP0_VBI3_OFFSET_HIGH__SI regCAP0_VBI3_OFFSET_HIGH__SI; -typedef union CAP0_VBI3_OFFSET__SI regCAP0_VBI3_OFFSET__SI; -typedef union CAP0_VBI_H_WINDOW__SI regCAP0_VBI_H_WINDOW__SI; -typedef union CAP0_VBI_V_WINDOW__SI regCAP0_VBI_V_WINDOW__SI; -typedef union CAP0_VIDEO_SYNC_TEST__SI regCAP0_VIDEO_SYNC_TEST__SI; -typedef union CAP0_V_WINDOW__SI regCAP0_V_WINDOW__SI; -typedef union CAP0_WR_BUFFER_STAT__SI regCAP0_WR_BUFFER_STAT__SI; -typedef union CAPTURE_HOST_BUSNUM regCAPTURE_HOST_BUSNUM; -typedef union CAPTURE_START_STATUS__SI regCAPTURE_START_STATUS__SI; -typedef union CAP_DEBUG__SI regCAP_DEBUG__SI; -typedef union CAP_INT_CNTL__SI regCAP_INT_CNTL__SI; -typedef union CAP_INT_STATUS__SI regCAP_INT_STATUS__SI; -typedef union CAP_PTR regCAP_PTR; -typedef union CB_BLEND0_CONTROL regCB_BLEND0_CONTROL; -typedef union CB_BLEND1_CONTROL regCB_BLEND1_CONTROL; -typedef union CB_BLEND2_CONTROL regCB_BLEND2_CONTROL; -typedef union CB_BLEND3_CONTROL regCB_BLEND3_CONTROL; -typedef union CB_BLEND4_CONTROL regCB_BLEND4_CONTROL; -typedef union CB_BLEND5_CONTROL regCB_BLEND5_CONTROL; -typedef union CB_BLEND6_CONTROL regCB_BLEND6_CONTROL; -typedef union CB_BLEND7_CONTROL regCB_BLEND7_CONTROL; -typedef union CB_BLEND_ALPHA regCB_BLEND_ALPHA; -typedef union CB_BLEND_BLUE regCB_BLEND_BLUE; -typedef union CB_BLEND_GREEN regCB_BLEND_GREEN; -typedef union CB_BLEND_RED regCB_BLEND_RED; -typedef union CB_CGTT_SCLK_CTRL regCB_CGTT_SCLK_CTRL; -typedef union CB_COLOR0_ATTRIB regCB_COLOR0_ATTRIB; -typedef union CB_COLOR0_BASE regCB_COLOR0_BASE; -typedef union CB_COLOR0_CLEAR_WORD0 regCB_COLOR0_CLEAR_WORD0; -typedef union CB_COLOR0_CLEAR_WORD1 regCB_COLOR0_CLEAR_WORD1; -typedef union CB_COLOR0_CMASK regCB_COLOR0_CMASK; -typedef union CB_COLOR0_CMASK_SLICE regCB_COLOR0_CMASK_SLICE; -typedef union CB_COLOR0_FMASK regCB_COLOR0_FMASK; -typedef union CB_COLOR0_FMASK_SLICE regCB_COLOR0_FMASK_SLICE; -typedef union CB_COLOR0_INFO regCB_COLOR0_INFO; -typedef union CB_COLOR0_PITCH regCB_COLOR0_PITCH; -typedef union CB_COLOR0_SLICE regCB_COLOR0_SLICE; -typedef union CB_COLOR0_VIEW regCB_COLOR0_VIEW; -typedef union CB_COLOR1_ATTRIB regCB_COLOR1_ATTRIB; -typedef union CB_COLOR1_BASE regCB_COLOR1_BASE; -typedef union CB_COLOR1_CLEAR_WORD0 regCB_COLOR1_CLEAR_WORD0; -typedef union CB_COLOR1_CLEAR_WORD1 regCB_COLOR1_CLEAR_WORD1; -typedef union CB_COLOR1_CMASK regCB_COLOR1_CMASK; -typedef union CB_COLOR1_CMASK_SLICE regCB_COLOR1_CMASK_SLICE; -typedef union CB_COLOR1_FMASK regCB_COLOR1_FMASK; -typedef union CB_COLOR1_FMASK_SLICE regCB_COLOR1_FMASK_SLICE; -typedef union CB_COLOR1_INFO regCB_COLOR1_INFO; -typedef union CB_COLOR1_PITCH regCB_COLOR1_PITCH; -typedef union CB_COLOR1_SLICE regCB_COLOR1_SLICE; -typedef union CB_COLOR1_VIEW regCB_COLOR1_VIEW; -typedef union CB_COLOR2_ATTRIB regCB_COLOR2_ATTRIB; -typedef union CB_COLOR2_BASE regCB_COLOR2_BASE; -typedef union CB_COLOR2_CLEAR_WORD0 regCB_COLOR2_CLEAR_WORD0; -typedef union CB_COLOR2_CLEAR_WORD1 regCB_COLOR2_CLEAR_WORD1; -typedef union CB_COLOR2_CMASK regCB_COLOR2_CMASK; -typedef union CB_COLOR2_CMASK_SLICE regCB_COLOR2_CMASK_SLICE; -typedef union CB_COLOR2_FMASK regCB_COLOR2_FMASK; -typedef union CB_COLOR2_FMASK_SLICE regCB_COLOR2_FMASK_SLICE; -typedef union CB_COLOR2_INFO regCB_COLOR2_INFO; -typedef union CB_COLOR2_PITCH regCB_COLOR2_PITCH; -typedef union CB_COLOR2_SLICE regCB_COLOR2_SLICE; -typedef union CB_COLOR2_VIEW regCB_COLOR2_VIEW; -typedef union CB_COLOR3_ATTRIB regCB_COLOR3_ATTRIB; -typedef union CB_COLOR3_BASE regCB_COLOR3_BASE; -typedef union CB_COLOR3_CLEAR_WORD0 regCB_COLOR3_CLEAR_WORD0; -typedef union CB_COLOR3_CLEAR_WORD1 regCB_COLOR3_CLEAR_WORD1; -typedef union CB_COLOR3_CMASK regCB_COLOR3_CMASK; -typedef union CB_COLOR3_CMASK_SLICE regCB_COLOR3_CMASK_SLICE; -typedef union CB_COLOR3_FMASK regCB_COLOR3_FMASK; -typedef union CB_COLOR3_FMASK_SLICE regCB_COLOR3_FMASK_SLICE; -typedef union CB_COLOR3_INFO regCB_COLOR3_INFO; -typedef union CB_COLOR3_PITCH regCB_COLOR3_PITCH; -typedef union CB_COLOR3_SLICE regCB_COLOR3_SLICE; -typedef union CB_COLOR3_VIEW regCB_COLOR3_VIEW; -typedef union CB_COLOR4_ATTRIB regCB_COLOR4_ATTRIB; -typedef union CB_COLOR4_BASE regCB_COLOR4_BASE; -typedef union CB_COLOR4_CLEAR_WORD0 regCB_COLOR4_CLEAR_WORD0; -typedef union CB_COLOR4_CLEAR_WORD1 regCB_COLOR4_CLEAR_WORD1; -typedef union CB_COLOR4_CMASK regCB_COLOR4_CMASK; -typedef union CB_COLOR4_CMASK_SLICE regCB_COLOR4_CMASK_SLICE; -typedef union CB_COLOR4_FMASK regCB_COLOR4_FMASK; -typedef union CB_COLOR4_FMASK_SLICE regCB_COLOR4_FMASK_SLICE; -typedef union CB_COLOR4_INFO regCB_COLOR4_INFO; -typedef union CB_COLOR4_PITCH regCB_COLOR4_PITCH; -typedef union CB_COLOR4_SLICE regCB_COLOR4_SLICE; -typedef union CB_COLOR4_VIEW regCB_COLOR4_VIEW; -typedef union CB_COLOR5_ATTRIB regCB_COLOR5_ATTRIB; -typedef union CB_COLOR5_BASE regCB_COLOR5_BASE; -typedef union CB_COLOR5_CLEAR_WORD0 regCB_COLOR5_CLEAR_WORD0; -typedef union CB_COLOR5_CLEAR_WORD1 regCB_COLOR5_CLEAR_WORD1; -typedef union CB_COLOR5_CMASK regCB_COLOR5_CMASK; -typedef union CB_COLOR5_CMASK_SLICE regCB_COLOR5_CMASK_SLICE; -typedef union CB_COLOR5_FMASK regCB_COLOR5_FMASK; -typedef union CB_COLOR5_FMASK_SLICE regCB_COLOR5_FMASK_SLICE; -typedef union CB_COLOR5_INFO regCB_COLOR5_INFO; -typedef union CB_COLOR5_PITCH regCB_COLOR5_PITCH; -typedef union CB_COLOR5_SLICE regCB_COLOR5_SLICE; -typedef union CB_COLOR5_VIEW regCB_COLOR5_VIEW; -typedef union CB_COLOR6_ATTRIB regCB_COLOR6_ATTRIB; -typedef union CB_COLOR6_BASE regCB_COLOR6_BASE; -typedef union CB_COLOR6_CLEAR_WORD0 regCB_COLOR6_CLEAR_WORD0; -typedef union CB_COLOR6_CLEAR_WORD1 regCB_COLOR6_CLEAR_WORD1; -typedef union CB_COLOR6_CMASK regCB_COLOR6_CMASK; -typedef union CB_COLOR6_CMASK_SLICE regCB_COLOR6_CMASK_SLICE; -typedef union CB_COLOR6_FMASK regCB_COLOR6_FMASK; -typedef union CB_COLOR6_FMASK_SLICE regCB_COLOR6_FMASK_SLICE; -typedef union CB_COLOR6_INFO regCB_COLOR6_INFO; -typedef union CB_COLOR6_PITCH regCB_COLOR6_PITCH; -typedef union CB_COLOR6_SLICE regCB_COLOR6_SLICE; -typedef union CB_COLOR6_VIEW regCB_COLOR6_VIEW; -typedef union CB_COLOR7_ATTRIB regCB_COLOR7_ATTRIB; -typedef union CB_COLOR7_BASE regCB_COLOR7_BASE; -typedef union CB_COLOR7_CLEAR_WORD0 regCB_COLOR7_CLEAR_WORD0; -typedef union CB_COLOR7_CLEAR_WORD1 regCB_COLOR7_CLEAR_WORD1; -typedef union CB_COLOR7_CMASK regCB_COLOR7_CMASK; -typedef union CB_COLOR7_CMASK_SLICE regCB_COLOR7_CMASK_SLICE; -typedef union CB_COLOR7_FMASK regCB_COLOR7_FMASK; -typedef union CB_COLOR7_FMASK_SLICE regCB_COLOR7_FMASK_SLICE; -typedef union CB_COLOR7_INFO regCB_COLOR7_INFO; -typedef union CB_COLOR7_PITCH regCB_COLOR7_PITCH; -typedef union CB_COLOR7_SLICE regCB_COLOR7_SLICE; -typedef union CB_COLOR7_VIEW regCB_COLOR7_VIEW; -typedef union CB_COLOR_CONTROL regCB_COLOR_CONTROL; -typedef union CB_DEBUG_BUS_1 regCB_DEBUG_BUS_1; -typedef union CB_DEBUG_BUS_10 regCB_DEBUG_BUS_10; -typedef union CB_DEBUG_BUS_11 regCB_DEBUG_BUS_11; -typedef union CB_DEBUG_BUS_12 regCB_DEBUG_BUS_12; -typedef union CB_DEBUG_BUS_13__SI__CI regCB_DEBUG_BUS_13__SI__CI; -typedef union CB_DEBUG_BUS_13__VI regCB_DEBUG_BUS_13__VI; -typedef union CB_DEBUG_BUS_14__SI__CI regCB_DEBUG_BUS_14__SI__CI; -typedef union CB_DEBUG_BUS_14__VI regCB_DEBUG_BUS_14__VI; -typedef union CB_DEBUG_BUS_15__SI__CI regCB_DEBUG_BUS_15__SI__CI; -typedef union CB_DEBUG_BUS_15__VI regCB_DEBUG_BUS_15__VI; -typedef union CB_DEBUG_BUS_16__SI__CI regCB_DEBUG_BUS_16__SI__CI; -typedef union CB_DEBUG_BUS_16__VI regCB_DEBUG_BUS_16__VI; -typedef union CB_DEBUG_BUS_17__SI__CI regCB_DEBUG_BUS_17__SI__CI; -typedef union CB_DEBUG_BUS_17__VI regCB_DEBUG_BUS_17__VI; -typedef union CB_DEBUG_BUS_18__SI__CI regCB_DEBUG_BUS_18__SI__CI; -typedef union CB_DEBUG_BUS_18__VI regCB_DEBUG_BUS_18__VI; -typedef union CB_DEBUG_BUS_2 regCB_DEBUG_BUS_2; -typedef union CB_DEBUG_BUS_3 regCB_DEBUG_BUS_3; -typedef union CB_DEBUG_BUS_4 regCB_DEBUG_BUS_4; -typedef union CB_DEBUG_BUS_5 regCB_DEBUG_BUS_5; -typedef union CB_DEBUG_BUS_6 regCB_DEBUG_BUS_6; -typedef union CB_DEBUG_BUS_7 regCB_DEBUG_BUS_7; -typedef union CB_DEBUG_BUS_8 regCB_DEBUG_BUS_8; -typedef union CB_DEBUG_BUS_9 regCB_DEBUG_BUS_9; -typedef union CB_HW_CONTROL regCB_HW_CONTROL; -typedef union CB_HW_CONTROL_1 regCB_HW_CONTROL_1; -typedef union CB_HW_CONTROL_2__CI regCB_HW_CONTROL_2__CI; -typedef union CB_HW_CONTROL_2__VI regCB_HW_CONTROL_2__VI; -typedef union CB_HW_CONTROL_2__SI regCB_HW_CONTROL_2__SI; -typedef union CB_HW_CONTROL_3__CI__VI regCB_HW_CONTROL_3__CI__VI; -typedef union CB_PERFCOUNTER0_HI regCB_PERFCOUNTER0_HI; -typedef union CB_PERFCOUNTER0_LO regCB_PERFCOUNTER0_LO; -typedef union CB_PERFCOUNTER0_SELECT0__SI regCB_PERFCOUNTER0_SELECT0__SI; -typedef union CB_PERFCOUNTER0_SELECT1__CI__VI regCB_PERFCOUNTER0_SELECT1__CI__VI; -typedef union CB_PERFCOUNTER0_SELECT1__SI regCB_PERFCOUNTER0_SELECT1__SI; -typedef union CB_PERFCOUNTER0_SELECT__CI__VI regCB_PERFCOUNTER0_SELECT__CI__VI; -typedef union CB_PERFCOUNTER1_HI regCB_PERFCOUNTER1_HI; -typedef union CB_PERFCOUNTER1_LO regCB_PERFCOUNTER1_LO; -typedef union CB_PERFCOUNTER1_SELECT0__SI regCB_PERFCOUNTER1_SELECT0__SI; -typedef union CB_PERFCOUNTER1_SELECT1__SI regCB_PERFCOUNTER1_SELECT1__SI; -typedef union CB_PERFCOUNTER1_SELECT__CI__VI regCB_PERFCOUNTER1_SELECT__CI__VI; -typedef union CB_PERFCOUNTER2_HI regCB_PERFCOUNTER2_HI; -typedef union CB_PERFCOUNTER2_LO regCB_PERFCOUNTER2_LO; -typedef union CB_PERFCOUNTER2_SELECT0__SI regCB_PERFCOUNTER2_SELECT0__SI; -typedef union CB_PERFCOUNTER2_SELECT1__SI regCB_PERFCOUNTER2_SELECT1__SI; -typedef union CB_PERFCOUNTER2_SELECT__CI__VI regCB_PERFCOUNTER2_SELECT__CI__VI; -typedef union CB_PERFCOUNTER3_HI regCB_PERFCOUNTER3_HI; -typedef union CB_PERFCOUNTER3_LO regCB_PERFCOUNTER3_LO; -typedef union CB_PERFCOUNTER3_SELECT0__SI regCB_PERFCOUNTER3_SELECT0__SI; -typedef union CB_PERFCOUNTER3_SELECT1__SI regCB_PERFCOUNTER3_SELECT1__SI; -typedef union CB_PERFCOUNTER3_SELECT__CI__VI regCB_PERFCOUNTER3_SELECT__CI__VI; -typedef union CB_PERFCOUNTER_FILTER__CI__VI regCB_PERFCOUNTER_FILTER__CI__VI; -typedef union CB_SHADER_MASK regCB_SHADER_MASK; -typedef union CB_TARGET_MASK regCB_TARGET_MASK; -typedef union CCIPHER_A_IK0 regCCIPHER_A_IK0; -typedef union CCIPHER_A_IK1 regCCIPHER_A_IK1; -typedef union CCIPHER_A_IK2 regCCIPHER_A_IK2; -typedef union CCIPHER_A_IK3 regCCIPHER_A_IK3; -typedef union CCIPHER_A_S0 regCCIPHER_A_S0; -typedef union CCIPHER_A_S1 regCCIPHER_A_S1; -typedef union CCIPHER_A_S10 regCCIPHER_A_S10; -typedef union CCIPHER_A_S11 regCCIPHER_A_S11; -typedef union CCIPHER_A_S12 regCCIPHER_A_S12; -typedef union CCIPHER_A_S13 regCCIPHER_A_S13; -typedef union CCIPHER_A_S14 regCCIPHER_A_S14; -typedef union CCIPHER_A_S15 regCCIPHER_A_S15; -typedef union CCIPHER_A_S16 regCCIPHER_A_S16; -typedef union CCIPHER_A_S17 regCCIPHER_A_S17; -typedef union CCIPHER_A_S18 regCCIPHER_A_S18; -typedef union CCIPHER_A_S19 regCCIPHER_A_S19; -typedef union CCIPHER_A_S2 regCCIPHER_A_S2; -typedef union CCIPHER_A_S20 regCCIPHER_A_S20; -typedef union CCIPHER_A_S21 regCCIPHER_A_S21; -typedef union CCIPHER_A_S22 regCCIPHER_A_S22; -typedef union CCIPHER_A_S23 regCCIPHER_A_S23; -typedef union CCIPHER_A_S24 regCCIPHER_A_S24; -typedef union CCIPHER_A_S25 regCCIPHER_A_S25; -typedef union CCIPHER_A_S26 regCCIPHER_A_S26; -typedef union CCIPHER_A_S27 regCCIPHER_A_S27; -typedef union CCIPHER_A_S28 regCCIPHER_A_S28; -typedef union CCIPHER_A_S29 regCCIPHER_A_S29; -typedef union CCIPHER_A_S3 regCCIPHER_A_S3; -typedef union CCIPHER_A_S30 regCCIPHER_A_S30; -typedef union CCIPHER_A_S31 regCCIPHER_A_S31; -typedef union CCIPHER_A_S4 regCCIPHER_A_S4; -typedef union CCIPHER_A_S5 regCCIPHER_A_S5; -typedef union CCIPHER_A_S6 regCCIPHER_A_S6; -typedef union CCIPHER_A_S7 regCCIPHER_A_S7; -typedef union CCIPHER_A_S8 regCCIPHER_A_S8; -typedef union CCIPHER_A_S9 regCCIPHER_A_S9; -typedef union CCIPHER_B_IK0 regCCIPHER_B_IK0; -typedef union CCIPHER_B_IK1 regCCIPHER_B_IK1; -typedef union CCIPHER_B_IK2 regCCIPHER_B_IK2; -typedef union CCIPHER_B_IK3 regCCIPHER_B_IK3; -typedef union CCIPHER_B_S0 regCCIPHER_B_S0; -typedef union CCIPHER_B_S1 regCCIPHER_B_S1; -typedef union CCIPHER_B_S10 regCCIPHER_B_S10; -typedef union CCIPHER_B_S11 regCCIPHER_B_S11; -typedef union CCIPHER_B_S12 regCCIPHER_B_S12; -typedef union CCIPHER_B_S13 regCCIPHER_B_S13; -typedef union CCIPHER_B_S14 regCCIPHER_B_S14; -typedef union CCIPHER_B_S15 regCCIPHER_B_S15; -typedef union CCIPHER_B_S16 regCCIPHER_B_S16; -typedef union CCIPHER_B_S17 regCCIPHER_B_S17; -typedef union CCIPHER_B_S18 regCCIPHER_B_S18; -typedef union CCIPHER_B_S19 regCCIPHER_B_S19; -typedef union CCIPHER_B_S2 regCCIPHER_B_S2; -typedef union CCIPHER_B_S20 regCCIPHER_B_S20; -typedef union CCIPHER_B_S21 regCCIPHER_B_S21; -typedef union CCIPHER_B_S22 regCCIPHER_B_S22; -typedef union CCIPHER_B_S23 regCCIPHER_B_S23; -typedef union CCIPHER_B_S24 regCCIPHER_B_S24; -typedef union CCIPHER_B_S25 regCCIPHER_B_S25; -typedef union CCIPHER_B_S26 regCCIPHER_B_S26; -typedef union CCIPHER_B_S27 regCCIPHER_B_S27; -typedef union CCIPHER_B_S28 regCCIPHER_B_S28; -typedef union CCIPHER_B_S29 regCCIPHER_B_S29; -typedef union CCIPHER_B_S3 regCCIPHER_B_S3; -typedef union CCIPHER_B_S30 regCCIPHER_B_S30; -typedef union CCIPHER_B_S31 regCCIPHER_B_S31; -typedef union CCIPHER_B_S4 regCCIPHER_B_S4; -typedef union CCIPHER_B_S5 regCCIPHER_B_S5; -typedef union CCIPHER_B_S6 regCCIPHER_B_S6; -typedef union CCIPHER_B_S7 regCCIPHER_B_S7; -typedef union CCIPHER_B_S8 regCCIPHER_B_S8; -typedef union CCIPHER_B_S9 regCCIPHER_B_S9; -typedef union CC_BIF_AZALIA_ID__CI regCC_BIF_AZALIA_ID__CI; -typedef union CC_BIF_AZALIA_ID__SI regCC_BIF_AZALIA_ID__SI; -typedef union CC_BIF_BU_PINSTRAP0__CI regCC_BIF_BU_PINSTRAP0__CI; -typedef union CC_BIF_BU_PINSTRAP0__VI regCC_BIF_BU_PINSTRAP0__VI; -typedef union CC_BIF_BX_FUSESTRAP0__CI__VI regCC_BIF_BX_FUSESTRAP0__CI__VI; -typedef union CC_BIF_BX_PINSTRAP0__CI regCC_BIF_BX_PINSTRAP0__CI; -typedef union CC_BIF_BX_PINSTRAP0__VI regCC_BIF_BX_PINSTRAP0__VI; -typedef union CC_BIF_BX_STRAP0__CI regCC_BIF_BX_STRAP0__CI; -typedef union CC_BIF_BX_STRAP0__VI regCC_BIF_BX_STRAP0__VI; -typedef union CC_BIF_BX_STRAP1__CI regCC_BIF_BX_STRAP1__CI; -typedef union CC_BIF_BX_STRAP1__VI regCC_BIF_BX_STRAP1__VI; -typedef union CC_BIF_EFUSE0__SI regCC_BIF_EFUSE0__SI; -typedef union CC_BIF_EFUSE1__SI regCC_BIF_EFUSE1__SI; -typedef union CC_BIF_EFUSE2__SI regCC_BIF_EFUSE2__SI; -typedef union CC_BIF_ID_STRAPS__CI regCC_BIF_ID_STRAPS__CI; -typedef union CC_BIF_ID_STRAPS__SI regCC_BIF_ID_STRAPS__SI; -typedef union CC_BIF_ROMSTRAP0__SI regCC_BIF_ROMSTRAP0__SI; -typedef union CC_BIF_ROMSTRAP1__SI regCC_BIF_ROMSTRAP1__SI; -typedef union CC_BIF_ROMSTRAP2__SI regCC_BIF_ROMSTRAP2__SI; -typedef union CC_BIF_ROMSTRAP3__SI regCC_BIF_ROMSTRAP3__SI; -typedef union CC_BIF_ROMSTRAP4__SI regCC_BIF_ROMSTRAP4__SI; -typedef union CC_BIF_ROMSTRAP5__SI regCC_BIF_ROMSTRAP5__SI; -typedef union CC_BIF_SECURE_CNTL__CI__VI regCC_BIF_SECURE_CNTL__CI__VI; -typedef union CC_BIF_STRAP0__CI regCC_BIF_STRAP0__CI; -typedef union CC_BIF_STRAP0__VI regCC_BIF_STRAP0__VI; -typedef union CC_BIF_STRAP1__CI regCC_BIF_STRAP1__CI; -typedef union CC_BIF_STRAP1__VI regCC_BIF_STRAP1__VI; -typedef union CC_BIF_STRAP2__CI regCC_BIF_STRAP2__CI; -typedef union CC_BIF_STRAP2__VI regCC_BIF_STRAP2__VI; -typedef union CC_BIF_STRAP3__CI regCC_BIF_STRAP3__CI; -typedef union CC_BIF_STRAP3__VI regCC_BIF_STRAP3__VI; -typedef union CC_BIF_STRAP4__CI regCC_BIF_STRAP4__CI; -typedef union CC_BIF_STRAP4__VI regCC_BIF_STRAP4__VI; -typedef union CC_BIF_STRAP5__CI regCC_BIF_STRAP5__CI; -typedef union CC_BIF_STRAP5__VI regCC_BIF_STRAP5__VI; -typedef union CC_BIF_STRAP6__CI regCC_BIF_STRAP6__CI; -typedef union CC_BIF_STRAP6__VI regCC_BIF_STRAP6__VI; -typedef union CC_BIF_STRAP7__CI regCC_BIF_STRAP7__CI; -typedef union CC_BIF_STRAP7__VI regCC_BIF_STRAP7__VI; -typedef union CC_BIF_STRAP8__CI regCC_BIF_STRAP8__CI; -typedef union CC_BIF_STRAP8__VI regCC_BIF_STRAP8__VI; -typedef union CC_BIF_STRAP9__CI regCC_BIF_STRAP9__CI; -typedef union CC_BIF_STRAP_FUSE0__CI regCC_BIF_STRAP_FUSE0__CI; -typedef union CC_CAC_CMON__CI regCC_CAC_CMON__CI; -typedef union CC_DC_MISC_STRAPS__SI regCC_DC_MISC_STRAPS__SI; -typedef union CC_DRM_ID_STRAPS regCC_DRM_ID_STRAPS; -typedef union CC_GC_EDC_CONFIG__CI__VI regCC_GC_EDC_CONFIG__CI__VI; -typedef union CC_GC_PRIM_CONFIG__CI__VI regCC_GC_PRIM_CONFIG__CI__VI; -typedef union CC_GC_SHADER_ARRAY_CONFIG__CI__VI regCC_GC_SHADER_ARRAY_CONFIG__CI__VI; -typedef union CC_GC_SHADER_ARRAY_CONFIG__SI regCC_GC_SHADER_ARRAY_CONFIG__SI; -typedef union CC_GIO_IOCCFG_FUSES__CI__VI regCC_GIO_IOCCFG_FUSES__CI__VI; -typedef union CC_GIO_IOC_FUSES__CI__VI regCC_GIO_IOC_FUSES__CI__VI; -typedef union CC_GNB_SECURE_SPARE__CI__VI regCC_GNB_SECURE_SPARE__CI__VI; -typedef union CC_MC_MAX_CHANNEL regCC_MC_MAX_CHANNEL; -typedef union CC_PWR_DYN_GF_RM__CI__VI regCC_PWR_DYN_GF_RM__CI__VI; -typedef union CC_PWR_DYN_RM1__CI__VI regCC_PWR_DYN_RM1__CI__VI; -typedef union CC_PWR_DYN_RM__CI__VI regCC_PWR_DYN_RM__CI__VI; -typedef union CC_PWR_GF_RM__CI__VI regCC_PWR_GF_RM__CI__VI; -typedef union CC_PWR_RM0__CI__VI regCC_PWR_RM0__CI__VI; -typedef union CC_PWR_RM1__CI__VI regCC_PWR_RM1__CI__VI; -typedef union CC_RB_BACKEND_DISABLE regCC_RB_BACKEND_DISABLE; -typedef union CC_RB_DAISY_CHAIN regCC_RB_DAISY_CHAIN; -typedef union CC_RB_REDUNDANCY__CI__VI regCC_RB_REDUNDANCY__CI__VI; -typedef union CC_RB_REDUNDANCY__SI regCC_RB_REDUNDANCY__SI; -typedef union CC_RCU_CG_STRAPS__SI regCC_RCU_CG_STRAPS__SI; -typedef union CC_RCU_CMON_STRAPS__SI regCC_RCU_CMON_STRAPS__SI; -typedef union CC_RCU_DC_MISC_STRAPS__SI regCC_RCU_DC_MISC_STRAPS__SI; -typedef union CC_RCU_DC_PIPE_DIS__SI regCC_RCU_DC_PIPE_DIS__SI; -typedef union CC_RCU_DYN_RM2__SI regCC_RCU_DYN_RM2__SI; -typedef union CC_RCU_DYN_RM__SI regCC_RCU_DYN_RM__SI; -typedef union CC_RCU_FUSES__CI regCC_RCU_FUSES__CI; -typedef union CC_RCU_FUSES__VI regCC_RCU_FUSES__VI; -typedef union CC_RCU_ID_STRAPS__SI regCC_RCU_ID_STRAPS__SI; -typedef union CC_RCU_MISC_STRAPS__SI regCC_RCU_MISC_STRAPS__SI; -typedef union CC_RCU_TMON_STRAPS__SI regCC_RCU_TMON_STRAPS__SI; -typedef union CC_SCLK_VID_FUSES__CI__VI regCC_SCLK_VID_FUSES__CI__VI; -typedef union CC_SMU_MISC_FUSES__CI__VI regCC_SMU_MISC_FUSES__CI__VI; -typedef union CC_SMU_TST_EFUSE1_MISC__CI__VI regCC_SMU_TST_EFUSE1_MISC__CI__VI; -typedef union CC_SQC_BANK_DISABLE regCC_SQC_BANK_DISABLE; -typedef union CC_SYS_RB_BACKEND_DISABLE regCC_SYS_RB_BACKEND_DISABLE; -typedef union CC_SYS_RB_REDUNDANCY__SI__CI regCC_SYS_RB_REDUNDANCY__SI__CI; -typedef union CC_SYS_RB_REDUNDANCY__VI regCC_SYS_RB_REDUNDANCY__VI; -typedef union CC_THM_FDO__CI regCC_THM_FDO__CI; -typedef union CC_THM_STRAPS0__CI regCC_THM_STRAPS0__CI; -typedef union CC_THM_STRAPS1__CI regCC_THM_STRAPS1__CI; -typedef union CC_TST_EFUSE0_RM regCC_TST_EFUSE0_RM; -typedef union CC_TST_EFUSE1_MISC regCC_TST_EFUSE1_MISC; -typedef union CC_TST_ID_STRAPS__CI__VI regCC_TST_ID_STRAPS__CI__VI; -typedef union CEC_ADDR__CI__VI regCEC_ADDR__CI__VI; -typedef union CEC_CONTROL__CI__VI regCEC_CONTROL__CI__VI; -typedef union CEC_DATA_LENGTH__CI__VI regCEC_DATA_LENGTH__CI__VI; -typedef union CEC_HPD_CONTROL__CI__VI regCEC_HPD_CONTROL__CI__VI; -typedef union CEC_HPD_TOGGLE_FILT_CONTROL__CI__VI regCEC_HPD_TOGGLE_FILT_CONTROL__CI__VI; -typedef union CEC_INT_EN__CI__VI regCEC_INT_EN__CI__VI; -typedef union CEC_MISC__CI__VI regCEC_MISC__CI__VI; -typedef union CEC_PAD_CNTL__CI__VI regCEC_PAD_CNTL__CI__VI; -typedef union CEC_RX_DATA_0__CI__VI regCEC_RX_DATA_0__CI__VI; -typedef union CEC_RX_DATA_1__CI__VI regCEC_RX_DATA_1__CI__VI; -typedef union CEC_RX_DATA_2__CI__VI regCEC_RX_DATA_2__CI__VI; -typedef union CEC_RX_DATA_3__CI__VI regCEC_RX_DATA_3__CI__VI; -typedef union CEC_SCRATCH_REG_0__CI__VI regCEC_SCRATCH_REG_0__CI__VI; -typedef union CEC_SCRATCH_REG_1__CI__VI regCEC_SCRATCH_REG_1__CI__VI; -typedef union CEC_SCRATCH_REG_2__CI__VI regCEC_SCRATCH_REG_2__CI__VI; -typedef union CEC_SCRATCH_REG_3__CI__VI regCEC_SCRATCH_REG_3__CI__VI; -typedef union CEC_SCRATCH_REG_4__CI__VI regCEC_SCRATCH_REG_4__CI__VI; -typedef union CEC_SCRATCH_REG_5__CI__VI regCEC_SCRATCH_REG_5__CI__VI; -typedef union CEC_STATUS__CI__VI regCEC_STATUS__CI__VI; -typedef union CEC_SW_OPCODE_0__CI__VI regCEC_SW_OPCODE_0__CI__VI; -typedef union CEC_SW_OPCODE_1__CI__VI regCEC_SW_OPCODE_1__CI__VI; -typedef union CEC_TX_DATA_0__CI__VI regCEC_TX_DATA_0__CI__VI; -typedef union CEC_TX_DATA_1__CI__VI regCEC_TX_DATA_1__CI__VI; -typedef union CEC_TX_DATA_2__CI__VI regCEC_TX_DATA_2__CI__VI; -typedef union CEC_TX_DATA_3__CI__VI regCEC_TX_DATA_3__CI__VI; -typedef union CGTS_CU0_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU0_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU0_SP0_CTRL_REG__CI__VI regCGTS_CU0_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU0_SP1_CTRL_REG__CI__VI regCGTS_CU0_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU0_TA_SQC_CTRL_REG__CI__VI regCGTS_CU0_TA_SQC_CTRL_REG__CI__VI; -typedef union CGTS_CU0_TD_TCP_CTRL_REG__CI__VI regCGTS_CU0_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU10_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU10_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU10_SP0_CTRL_REG__CI__VI regCGTS_CU10_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU10_SP1_CTRL_REG__CI__VI regCGTS_CU10_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU10_TA_CTRL_REG__CI__VI regCGTS_CU10_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU10_TD_TCP_CTRL_REG__CI__VI regCGTS_CU10_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU11_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU11_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU11_SP0_CTRL_REG__CI__VI regCGTS_CU11_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU11_SP1_CTRL_REG__CI__VI regCGTS_CU11_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU11_TA_CTRL_REG__CI__VI regCGTS_CU11_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU11_TD_TCP_CTRL_REG__CI__VI regCGTS_CU11_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU12_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU12_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU12_SP0_CTRL_REG__CI__VI regCGTS_CU12_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU12_SP1_CTRL_REG__CI__VI regCGTS_CU12_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU12_TA_SQC_CTRL_REG__CI__VI regCGTS_CU12_TA_SQC_CTRL_REG__CI__VI; -typedef union CGTS_CU12_TD_TCP_CTRL_REG__CI__VI regCGTS_CU12_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU13_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU13_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU13_SP0_CTRL_REG__CI__VI regCGTS_CU13_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU13_SP1_CTRL_REG__CI__VI regCGTS_CU13_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU13_TA_CTRL_REG__CI__VI regCGTS_CU13_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU13_TD_TCP_CTRL_REG__CI__VI regCGTS_CU13_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU14_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU14_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU14_SP0_CTRL_REG__CI__VI regCGTS_CU14_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU14_SP1_CTRL_REG__CI__VI regCGTS_CU14_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU14_TA_CTRL_REG__CI__VI regCGTS_CU14_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU14_TD_TCP_CTRL_REG__CI__VI regCGTS_CU14_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU15_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU15_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU15_SP0_CTRL_REG__CI__VI regCGTS_CU15_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU15_SP1_CTRL_REG__CI__VI regCGTS_CU15_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU15_TA_CTRL_REG__CI__VI regCGTS_CU15_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU15_TD_TCP_CTRL_REG__CI__VI regCGTS_CU15_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU1_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU1_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU1_SP0_CTRL_REG__CI__VI regCGTS_CU1_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU1_SP1_CTRL_REG__CI__VI regCGTS_CU1_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU1_TA_CTRL_REG__CI__VI regCGTS_CU1_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU1_TD_TCP_CTRL_REG__CI__VI regCGTS_CU1_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU2_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU2_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU2_SP0_CTRL_REG__CI__VI regCGTS_CU2_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU2_SP1_CTRL_REG__CI__VI regCGTS_CU2_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU2_TA_CTRL_REG__CI__VI regCGTS_CU2_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU2_TD_TCP_CTRL_REG__CI__VI regCGTS_CU2_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU3_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU3_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU3_SP0_CTRL_REG__CI__VI regCGTS_CU3_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU3_SP1_CTRL_REG__CI__VI regCGTS_CU3_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU3_TA_CTRL_REG__CI__VI regCGTS_CU3_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU3_TD_TCP_CTRL_REG__CI__VI regCGTS_CU3_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU4_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU4_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU4_SP0_CTRL_REG__CI__VI regCGTS_CU4_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU4_SP1_CTRL_REG__CI__VI regCGTS_CU4_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU4_TA_SQC_CTRL_REG__CI__VI regCGTS_CU4_TA_SQC_CTRL_REG__CI__VI; -typedef union CGTS_CU4_TD_TCP_CTRL_REG__CI__VI regCGTS_CU4_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU5_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU5_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU5_SP0_CTRL_REG__CI__VI regCGTS_CU5_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU5_SP1_CTRL_REG__CI__VI regCGTS_CU5_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU5_TA_CTRL_REG__CI__VI regCGTS_CU5_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU5_TD_TCP_CTRL_REG__CI__VI regCGTS_CU5_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU6_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU6_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU6_SP0_CTRL_REG__CI__VI regCGTS_CU6_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU6_SP1_CTRL_REG__CI__VI regCGTS_CU6_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU6_TA_CTRL_REG__CI__VI regCGTS_CU6_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU6_TD_TCP_CTRL_REG__CI__VI regCGTS_CU6_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU7_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU7_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU7_SP0_CTRL_REG__CI__VI regCGTS_CU7_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU7_SP1_CTRL_REG__CI__VI regCGTS_CU7_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU7_TA_CTRL_REG__CI__VI regCGTS_CU7_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU7_TD_TCP_CTRL_REG__CI__VI regCGTS_CU7_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU8_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU8_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU8_SP0_CTRL_REG__CI__VI regCGTS_CU8_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU8_SP1_CTRL_REG__CI__VI regCGTS_CU8_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU8_TA_SQC_CTRL_REG__CI__VI regCGTS_CU8_TA_SQC_CTRL_REG__CI__VI; -typedef union CGTS_CU8_TD_TCP_CTRL_REG__CI__VI regCGTS_CU8_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_CU9_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU9_LDS_SQ_CTRL_REG__CI__VI; -typedef union CGTS_CU9_SP0_CTRL_REG__CI__VI regCGTS_CU9_SP0_CTRL_REG__CI__VI; -typedef union CGTS_CU9_SP1_CTRL_REG__CI__VI regCGTS_CU9_SP1_CTRL_REG__CI__VI; -typedef union CGTS_CU9_TA_CTRL_REG__CI__VI regCGTS_CU9_TA_CTRL_REG__CI__VI; -typedef union CGTS_CU9_TD_TCP_CTRL_REG__CI__VI regCGTS_CU9_TD_TCP_CTRL_REG__CI__VI; -typedef union CGTS_RD_CTRL_REG regCGTS_RD_CTRL_REG; -typedef union CGTS_RD_REG regCGTS_RD_REG; -typedef union CGTS_S0C0_LDS_SQ_CTRL_REG__SI regCGTS_S0C0_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C0_SP0_CTRL_REG__SI regCGTS_S0C0_SP0_CTRL_REG__SI; -typedef union CGTS_S0C0_SP1_CTRL_REG__SI regCGTS_S0C0_SP1_CTRL_REG__SI; -typedef union CGTS_S0C0_TA_SQC_CTRL_REG__SI regCGTS_S0C0_TA_SQC_CTRL_REG__SI; -typedef union CGTS_S0C0_TD_TCP_CTRL_REG__SI regCGTS_S0C0_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S0C1_LDS_SQ_CTRL_REG__SI regCGTS_S0C1_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C1_SP0_CTRL_REG__SI regCGTS_S0C1_SP0_CTRL_REG__SI; -typedef union CGTS_S0C1_SP1_CTRL_REG__SI regCGTS_S0C1_SP1_CTRL_REG__SI; -typedef union CGTS_S0C1_TA_CTRL_REG__SI regCGTS_S0C1_TA_CTRL_REG__SI; -typedef union CGTS_S0C1_TD_TCP_CTRL_REG__SI regCGTS_S0C1_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S0C2_LDS_SQ_CTRL_REG__SI regCGTS_S0C2_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C2_SP0_CTRL_REG__SI regCGTS_S0C2_SP0_CTRL_REG__SI; -typedef union CGTS_S0C2_SP1_CTRL_REG__SI regCGTS_S0C2_SP1_CTRL_REG__SI; -typedef union CGTS_S0C2_TA_CTRL_REG__SI regCGTS_S0C2_TA_CTRL_REG__SI; -typedef union CGTS_S0C2_TD_TCP_CTRL_REG__SI regCGTS_S0C2_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S0C3_LDS_SQ_CTRL_REG__SI regCGTS_S0C3_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C3_SP0_CTRL_REG__SI regCGTS_S0C3_SP0_CTRL_REG__SI; -typedef union CGTS_S0C3_SP1_CTRL_REG__SI regCGTS_S0C3_SP1_CTRL_REG__SI; -typedef union CGTS_S0C3_TA_CTRL_REG__SI regCGTS_S0C3_TA_CTRL_REG__SI; -typedef union CGTS_S0C3_TD_TCP_CTRL_REG__SI regCGTS_S0C3_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S0C4_LDS_SQ_CTRL_REG__SI regCGTS_S0C4_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C4_SP0_CTRL_REG__SI regCGTS_S0C4_SP0_CTRL_REG__SI; -typedef union CGTS_S0C4_SP1_CTRL_REG__SI regCGTS_S0C4_SP1_CTRL_REG__SI; -typedef union CGTS_S0C4_TA_SQC_CTRL_REG__SI regCGTS_S0C4_TA_SQC_CTRL_REG__SI; -typedef union CGTS_S0C4_TD_TCP_CTRL_REG__SI regCGTS_S0C4_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S0C5_LDS_SQ_CTRL_REG__SI regCGTS_S0C5_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C5_SP0_CTRL_REG__SI regCGTS_S0C5_SP0_CTRL_REG__SI; -typedef union CGTS_S0C5_SP1_CTRL_REG__SI regCGTS_S0C5_SP1_CTRL_REG__SI; -typedef union CGTS_S0C5_TA_CTRL_REG__SI regCGTS_S0C5_TA_CTRL_REG__SI; -typedef union CGTS_S0C5_TD_TCP_CTRL_REG__SI regCGTS_S0C5_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S0C6_LDS_SQ_CTRL_REG__SI regCGTS_S0C6_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C6_SP0_CTRL_REG__SI regCGTS_S0C6_SP0_CTRL_REG__SI; -typedef union CGTS_S0C6_SP1_CTRL_REG__SI regCGTS_S0C6_SP1_CTRL_REG__SI; -typedef union CGTS_S0C6_TA_CTRL_REG__SI regCGTS_S0C6_TA_CTRL_REG__SI; -typedef union CGTS_S0C6_TD_TCP_CTRL_REG__SI regCGTS_S0C6_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S0C7_LDS_SQ_CTRL_REG__SI regCGTS_S0C7_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S0C7_SP0_CTRL_REG__SI regCGTS_S0C7_SP0_CTRL_REG__SI; -typedef union CGTS_S0C7_SP1_CTRL_REG__SI regCGTS_S0C7_SP1_CTRL_REG__SI; -typedef union CGTS_S0C7_TA_CTRL_REG__SI regCGTS_S0C7_TA_CTRL_REG__SI; -typedef union CGTS_S0C7_TD_TCP_CTRL_REG__SI regCGTS_S0C7_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C0_LDS_SQ_CTRL_REG__SI regCGTS_S1C0_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C0_SP0_CTRL_REG__SI regCGTS_S1C0_SP0_CTRL_REG__SI; -typedef union CGTS_S1C0_SP1_CTRL_REG__SI regCGTS_S1C0_SP1_CTRL_REG__SI; -typedef union CGTS_S1C0_TA_SQC_CTRL_REG__SI regCGTS_S1C0_TA_SQC_CTRL_REG__SI; -typedef union CGTS_S1C0_TD_TCP_CTRL_REG__SI regCGTS_S1C0_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C1_LDS_SQ_CTRL_REG__SI regCGTS_S1C1_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C1_SP0_CTRL_REG__SI regCGTS_S1C1_SP0_CTRL_REG__SI; -typedef union CGTS_S1C1_SP1_CTRL_REG__SI regCGTS_S1C1_SP1_CTRL_REG__SI; -typedef union CGTS_S1C1_TA_CTRL_REG__SI regCGTS_S1C1_TA_CTRL_REG__SI; -typedef union CGTS_S1C1_TD_TCP_CTRL_REG__SI regCGTS_S1C1_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C2_LDS_SQ_CTRL_REG__SI regCGTS_S1C2_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C2_SP0_CTRL_REG__SI regCGTS_S1C2_SP0_CTRL_REG__SI; -typedef union CGTS_S1C2_SP1_CTRL_REG__SI regCGTS_S1C2_SP1_CTRL_REG__SI; -typedef union CGTS_S1C2_TA_CTRL_REG__SI regCGTS_S1C2_TA_CTRL_REG__SI; -typedef union CGTS_S1C2_TD_TCP_CTRL_REG__SI regCGTS_S1C2_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C3_LDS_SQ_CTRL_REG__SI regCGTS_S1C3_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C3_SP0_CTRL_REG__SI regCGTS_S1C3_SP0_CTRL_REG__SI; -typedef union CGTS_S1C3_SP1_CTRL_REG__SI regCGTS_S1C3_SP1_CTRL_REG__SI; -typedef union CGTS_S1C3_TA_CTRL_REG__SI regCGTS_S1C3_TA_CTRL_REG__SI; -typedef union CGTS_S1C3_TD_TCP_CTRL_REG__SI regCGTS_S1C3_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C4_LDS_SQ_CTRL_REG__SI regCGTS_S1C4_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C4_SP0_CTRL_REG__SI regCGTS_S1C4_SP0_CTRL_REG__SI; -typedef union CGTS_S1C4_SP1_CTRL_REG__SI regCGTS_S1C4_SP1_CTRL_REG__SI; -typedef union CGTS_S1C4_TA_SQC_CTRL_REG__SI regCGTS_S1C4_TA_SQC_CTRL_REG__SI; -typedef union CGTS_S1C4_TD_TCP_CTRL_REG__SI regCGTS_S1C4_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C5_LDS_SQ_CTRL_REG__SI regCGTS_S1C5_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C5_SP0_CTRL_REG__SI regCGTS_S1C5_SP0_CTRL_REG__SI; -typedef union CGTS_S1C5_SP1_CTRL_REG__SI regCGTS_S1C5_SP1_CTRL_REG__SI; -typedef union CGTS_S1C5_TA_CTRL_REG__SI regCGTS_S1C5_TA_CTRL_REG__SI; -typedef union CGTS_S1C5_TD_TCP_CTRL_REG__SI regCGTS_S1C5_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C6_LDS_SQ_CTRL_REG__SI regCGTS_S1C6_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C6_SP0_CTRL_REG__SI regCGTS_S1C6_SP0_CTRL_REG__SI; -typedef union CGTS_S1C6_SP1_CTRL_REG__SI regCGTS_S1C6_SP1_CTRL_REG__SI; -typedef union CGTS_S1C6_TA_CTRL_REG__SI regCGTS_S1C6_TA_CTRL_REG__SI; -typedef union CGTS_S1C6_TD_TCP_CTRL_REG__SI regCGTS_S1C6_TD_TCP_CTRL_REG__SI; -typedef union CGTS_S1C7_LDS_SQ_CTRL_REG__SI regCGTS_S1C7_LDS_SQ_CTRL_REG__SI; -typedef union CGTS_S1C7_SP0_CTRL_REG__SI regCGTS_S1C7_SP0_CTRL_REG__SI; -typedef union CGTS_S1C7_SP1_CTRL_REG__SI regCGTS_S1C7_SP1_CTRL_REG__SI; -typedef union CGTS_S1C7_TA_CTRL_REG__SI regCGTS_S1C7_TA_CTRL_REG__SI; -typedef union CGTS_S1C7_TD_TCP_CTRL_REG__SI regCGTS_S1C7_TD_TCP_CTRL_REG__SI; -typedef union CGTS_SM_CTRL_REG regCGTS_SM_CTRL_REG; -typedef union CGTS_TCC_DISABLE regCGTS_TCC_DISABLE; -typedef union CGTS_USER_TCC_DISABLE regCGTS_USER_TCC_DISABLE; -typedef union CGTT_BCI_CLK_CTRL regCGTT_BCI_CLK_CTRL; -typedef union CGTT_BIF_CLK_CTRL0__SI regCGTT_BIF_CLK_CTRL0__SI; -typedef union CGTT_CPC_CLK_CTRL__CI__VI regCGTT_CPC_CLK_CTRL__CI__VI; -typedef union CGTT_CPF_CLK_CTRL__CI__VI regCGTT_CPF_CLK_CTRL__CI__VI; -typedef union CGTT_CP_CLK_CTRL regCGTT_CP_CLK_CTRL; -typedef union CGTT_DRM_CLK_CTRL0 regCGTT_DRM_CLK_CTRL0; -typedef union CGTT_GDS_CLK_CTRL regCGTT_GDS_CLK_CTRL; -typedef union CGTT_IA_CLK_CTRL__CI__VI regCGTT_IA_CLK_CTRL__CI__VI; -typedef union CGTT_IA_CLK_CTRL__SI regCGTT_IA_CLK_CTRL__SI; -typedef union CGTT_PA_CLK_CTRL regCGTT_PA_CLK_CTRL; -typedef union CGTT_PC_CLK_CTRL regCGTT_PC_CLK_CTRL; -typedef union CGTT_RLC_CLK_CTRL regCGTT_RLC_CLK_CTRL; -typedef union CGTT_ROM_CLK_CTRL0 regCGTT_ROM_CLK_CTRL0; -typedef union CGTT_SC_CLK_CTRL regCGTT_SC_CLK_CTRL; -typedef union CGTT_SPI_CLK_CTRL regCGTT_SPI_CLK_CTRL; -typedef union CGTT_SQG_CLK_CTRL regCGTT_SQG_CLK_CTRL; -typedef union CGTT_SQ_CLK_CTRL regCGTT_SQ_CLK_CTRL; -typedef union CGTT_SX_CLK_CTRL0 regCGTT_SX_CLK_CTRL0; -typedef union CGTT_SX_CLK_CTRL1__SI__CI regCGTT_SX_CLK_CTRL1__SI__CI; -typedef union CGTT_SX_CLK_CTRL1__VI regCGTT_SX_CLK_CTRL1__VI; -typedef union CGTT_SX_CLK_CTRL2__SI__CI regCGTT_SX_CLK_CTRL2__SI__CI; -typedef union CGTT_SX_CLK_CTRL2__VI regCGTT_SX_CLK_CTRL2__VI; -typedef union CGTT_SX_CLK_CTRL3__SI__CI regCGTT_SX_CLK_CTRL3__SI__CI; -typedef union CGTT_SX_CLK_CTRL3__VI regCGTT_SX_CLK_CTRL3__VI; -typedef union CGTT_SX_CLK_CTRL4__SI__CI regCGTT_SX_CLK_CTRL4__SI__CI; -typedef union CGTT_SX_CLK_CTRL4__VI regCGTT_SX_CLK_CTRL4__VI; -typedef union CGTT_TCI_CLK_CTRL regCGTT_TCI_CLK_CTRL; -typedef union CGTT_TCP_CLK_CTRL regCGTT_TCP_CLK_CTRL; -typedef union CGTT_VGT_CLK_CTRL__SI__CI regCGTT_VGT_CLK_CTRL__SI__CI; -typedef union CGTT_VGT_CLK_CTRL__VI regCGTT_VGT_CLK_CTRL__VI; -typedef union CGTT_WD_CLK_CTRL__CI regCGTT_WD_CLK_CTRL__CI; -typedef union CGTT_WD_CLK_CTRL__VI regCGTT_WD_CLK_CTRL__VI; -typedef union CG_ACLK_CNTL__CI__VI regCG_ACLK_CNTL__CI__VI; -typedef union CG_ACLK_STATUS__CI__VI regCG_ACLK_STATUS__CI__VI; -typedef union CG_ACPI_CNTL__CI__VI regCG_ACPI_CNTL__CI__VI; -typedef union CG_AM_0_BUSY_CNT__CI__VI regCG_AM_0_BUSY_CNT__CI__VI; -typedef union CG_AM_1_BUSY_CNT__CI__VI regCG_AM_1_BUSY_CNT__CI__VI; -typedef union CG_AM_2_BUSY_CNT__CI__VI regCG_AM_2_BUSY_CNT__CI__VI; -typedef union CG_AM_3_BUSY_CNT__CI__VI regCG_AM_3_BUSY_CNT__CI__VI; -typedef union CG_AM_4_BUSY_CNT__CI__VI regCG_AM_4_BUSY_CNT__CI__VI; -typedef union CG_AM_5_BUSY_CNT__CI__VI regCG_AM_5_BUSY_CNT__CI__VI; -typedef union CG_AM_6_BUSY_CNT__CI__VI regCG_AM_6_BUSY_CNT__CI__VI; -typedef union CG_AM_7_BUSY_CNT__CI__VI regCG_AM_7_BUSY_CNT__CI__VI; -typedef union CG_AM_CNTL__CI__VI regCG_AM_CNTL__CI__VI; -typedef union CG_AM_SATURATION_LIMIT__CI__VI regCG_AM_SATURATION_LIMIT__CI__VI; -typedef union CG_AM_SCLK_CNT__CI__VI regCG_AM_SCLK_CNT__CI__VI; -typedef union CG_AZ_REQ_AND_RSP regCG_AZ_REQ_AND_RSP; -typedef union CG_AZ_STATUS__CI__VI regCG_AZ_STATUS__CI__VI; -typedef union CG_BIF_REQ_AND_RSP regCG_BIF_REQ_AND_RSP; -typedef union CG_BUSY_SAMPLING_PARAMETERS__SI regCG_BUSY_SAMPLING_PARAMETERS__SI; -typedef union CG_CAC_CTRL_2__CI regCG_CAC_CTRL_2__CI; -typedef union CG_CAC_CTRL__CI regCG_CAC_CTRL__CI; -typedef union CG_CAC_CTRL__SI regCG_CAC_CTRL__SI; -typedef union CG_CGLS_TILE_0__SI regCG_CGLS_TILE_0__SI; -typedef union CG_CGTT_LOCAL_0__SI regCG_CGTT_LOCAL_0__SI; -typedef union CG_CGTT_LOCAL_1__SI regCG_CGTT_LOCAL_1__SI; -typedef union CG_CGTT_OVERRIDE_0__CI__VI regCG_CGTT_OVERRIDE_0__CI__VI; -typedef union CG_CGTT_OVERRIDE_1__CI__VI regCG_CGTT_OVERRIDE_1__CI__VI; -typedef union CG_CHRONO_31_0 regCG_CHRONO_31_0; -typedef union CG_CHRONO_63_32 regCG_CHRONO_63_32; -typedef union CG_CLIENT_HS_CNTL__CI__VI regCG_CLIENT_HS_CNTL__CI__VI; -typedef union CG_CLKPIN_CNTL_2__CI__VI regCG_CLKPIN_CNTL_2__CI__VI; -typedef union CG_CLKPIN_CNTL__CI__VI regCG_CLKPIN_CNTL__CI__VI; -typedef union CG_CLKPIN_CNTL__SI regCG_CLKPIN_CNTL__SI; -typedef union CG_CLK_DIVIDER_STATUS_0__CI__VI regCG_CLK_DIVIDER_STATUS_0__CI__VI; -typedef union CG_CLK_DIVIDER_STATUS_1__CI__VI regCG_CLK_DIVIDER_STATUS_1__CI__VI; -typedef union CG_DCLK_CNTL__CI__VI regCG_DCLK_CNTL__CI__VI; -typedef union CG_DCLK_STATUS__CI__VI regCG_DCLK_STATUS__CI__VI; -typedef union CG_DC_REQ_AND_RSP__SI regCG_DC_REQ_AND_RSP__SI; -typedef union CG_DISPLAY_GAP_CNTL2__CI__VI regCG_DISPLAY_GAP_CNTL2__CI__VI; -typedef union CG_DISPLAY_GAP_CNTL__CI__VI regCG_DISPLAY_GAP_CNTL__CI__VI; -typedef union CG_DISPLAY_GAP_CNTL__SI regCG_DISPLAY_GAP_CNTL__SI; -typedef union CG_DISPLAY_GAP_COUNTER__CI regCG_DISPLAY_GAP_COUNTER__CI; -typedef union CG_ECLK_CNTL__CI__VI regCG_ECLK_CNTL__CI__VI; -typedef union CG_ECLK_OVERCLOCKING_ATTEMPTS__CI__VI regCG_ECLK_OVERCLOCKING_ATTEMPTS__CI__VI; -typedef union CG_ECLK_STATUS__CI__VI regCG_ECLK_STATUS__CI__VI; -typedef union CG_EVCLK_CNTL__CI__VI regCG_EVCLK_CNTL__CI__VI; -typedef union CG_EVCLK_STATUS__CI__VI regCG_EVCLK_STATUS__CI__VI; -typedef union CG_FDO_CTRL0__SI__CI regCG_FDO_CTRL0__SI__CI; -typedef union CG_FDO_CTRL1__SI__CI regCG_FDO_CTRL1__SI__CI; -typedef union CG_FDO_CTRL2__SI__CI regCG_FDO_CTRL2__SI__CI; -typedef union CG_FIR_FILTER_COEFF_TAP_0__SI regCG_FIR_FILTER_COEFF_TAP_0__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_10__SI regCG_FIR_FILTER_COEFF_TAP_10__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_11__SI regCG_FIR_FILTER_COEFF_TAP_11__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_12__SI regCG_FIR_FILTER_COEFF_TAP_12__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_13__SI regCG_FIR_FILTER_COEFF_TAP_13__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_14__SI regCG_FIR_FILTER_COEFF_TAP_14__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_1__SI regCG_FIR_FILTER_COEFF_TAP_1__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_2__SI regCG_FIR_FILTER_COEFF_TAP_2__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_3__SI regCG_FIR_FILTER_COEFF_TAP_3__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_4__SI regCG_FIR_FILTER_COEFF_TAP_4__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_5__SI regCG_FIR_FILTER_COEFF_TAP_5__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_6__SI regCG_FIR_FILTER_COEFF_TAP_6__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_7__SI regCG_FIR_FILTER_COEFF_TAP_7__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_8__SI regCG_FIR_FILTER_COEFF_TAP_8__SI; -typedef union CG_FIR_FILTER_COEFF_TAP_9__SI regCG_FIR_FILTER_COEFF_TAP_9__SI; -typedef union CG_FPS_CNT__CI regCG_FPS_CNT__CI; -typedef union CG_FPS_CNT__VI regCG_FPS_CNT__VI; -typedef union CG_FREQ_TRAN_VOTING_0__CI__VI regCG_FREQ_TRAN_VOTING_0__CI__VI; -typedef union CG_FREQ_TRAN_VOTING_1__CI__VI regCG_FREQ_TRAN_VOTING_1__CI__VI; -typedef union CG_FREQ_TRAN_VOTING_2__CI__VI regCG_FREQ_TRAN_VOTING_2__CI__VI; -typedef union CG_FREQ_TRAN_VOTING_3__CI__VI regCG_FREQ_TRAN_VOTING_3__CI__VI; -typedef union CG_FREQ_TRAN_VOTING_4__CI__VI regCG_FREQ_TRAN_VOTING_4__CI__VI; -typedef union CG_FREQ_TRAN_VOTING_5__CI__VI regCG_FREQ_TRAN_VOTING_5__CI__VI; -typedef union CG_FREQ_TRAN_VOTING_6__CI__VI regCG_FREQ_TRAN_VOTING_6__CI__VI; -typedef union CG_FREQ_TRAN_VOTING_7__CI__VI regCG_FREQ_TRAN_VOTING_7__CI__VI; -typedef union CG_FREQ_TRAN_VOTING__SI regCG_FREQ_TRAN_VOTING__SI; -typedef union CG_GFXCLK_ON_OFF_RAMP__SI regCG_GFXCLK_ON_OFF_RAMP__SI; -typedef union CG_GFX_IDLE_THRESHOLDS__SI regCG_GFX_IDLE_THRESHOLDS__SI; -typedef union CG_IND_ADDR__SI regCG_IND_ADDR__SI; -typedef union CG_IND_DATA__SI regCG_IND_DATA__SI; -typedef union CG_INTERRUPT_STATUS regCG_INTERRUPT_STATUS; -typedef union CG_LCLK_CNTL__CI__VI regCG_LCLK_CNTL__CI__VI; -typedef union CG_LCLK_STATUS__CI__VI regCG_LCLK_STATUS__CI__VI; -typedef union CG_MISC_REG regCG_MISC_REG; -typedef union CG_MISC_REG_2 regCG_MISC_REG_2; -typedef union CG_MULT_THERMAL_CTRL__SI__CI regCG_MULT_THERMAL_CTRL__SI__CI; -typedef union CG_MULT_THERMAL_STATUS__SI__CI regCG_MULT_THERMAL_STATUS__SI__CI; -typedef union CG_PROG_CNTR_STATUS_REG__SI regCG_PROG_CNTR_STATUS_REG__SI; -typedef union CG_PROG_CNTR__SI regCG_PROG_CNTR__SI; -typedef union CG_SAMCLK_CNTL__CI__VI regCG_SAMCLK_CNTL__CI__VI; -typedef union CG_SAMCLK_OVERCLOCKING_ATTEMPTS__CI__VI regCG_SAMCLK_OVERCLOCKING_ATTEMPTS__CI__VI; -typedef union CG_SAMCLK_STATUS__CI__VI regCG_SAMCLK_STATUS__CI__VI; -typedef union CG_SCLK_CNTL__CI__VI regCG_SCLK_CNTL__CI__VI; -typedef union CG_SCLK_LCLK_OVERCLOCKING_ATTEMPTS__CI__VI - regCG_SCLK_LCLK_OVERCLOCKING_ATTEMPTS__CI__VI; -typedef union CG_SCLK_STATUS__CI__VI regCG_SCLK_STATUS__CI__VI; -typedef union CG_SPLL_AUTOSCALE_CNTL__SI regCG_SPLL_AUTOSCALE_CNTL__SI; -typedef union CG_SPLL_AUTOSCALE_STATUS__SI regCG_SPLL_AUTOSCALE_STATUS__SI; -typedef union CG_SPLL_FUNC_CNTL__SI__CI regCG_SPLL_FUNC_CNTL__SI__CI; -typedef union CG_SPLL_FUNC_CNTL__VI regCG_SPLL_FUNC_CNTL__VI; -typedef union CG_SPLL_FUNC_CNTL_2 regCG_SPLL_FUNC_CNTL_2; -typedef union CG_SPLL_FUNC_CNTL_3 regCG_SPLL_FUNC_CNTL_3; -typedef union CG_SPLL_FUNC_CNTL_4__SI__CI regCG_SPLL_FUNC_CNTL_4__SI__CI; -typedef union CG_SPLL_FUNC_CNTL_4__VI regCG_SPLL_FUNC_CNTL_4__VI; -typedef union CG_SPLL_FUNC_CNTL_5__SI__CI regCG_SPLL_FUNC_CNTL_5__SI__CI; -typedef union CG_SPLL_FUNC_CNTL_5__VI regCG_SPLL_FUNC_CNTL_5__VI; -typedef union CG_SPLL_FUNC_CNTL_6__CI__VI regCG_SPLL_FUNC_CNTL_6__CI__VI; -typedef union CG_SPLL_SPREAD_SPECTRUM regCG_SPLL_SPREAD_SPECTRUM; -typedef union CG_SPLL_SPREAD_SPECTRUM_2 regCG_SPLL_SPREAD_SPECTRUM_2; -typedef union CG_SPLL_STATUS regCG_SPLL_STATUS; -typedef union CG_SPMICLK_CNTL__CI__VI regCG_SPMICLK_CNTL__CI__VI; -typedef union CG_STATIC_SCREEN_CTRL__CI__VI regCG_STATIC_SCREEN_CTRL__CI__VI; -typedef union CG_STATIC_SCREEN_PARAMETER regCG_STATIC_SCREEN_PARAMETER; -typedef union CG_SW_INT_CTXID__SI regCG_SW_INT_CTXID__SI; -typedef union CG_SW_INT__SI regCG_SW_INT__SI; -typedef union CG_TACH_CTRL__SI__CI regCG_TACH_CTRL__SI__CI; -typedef union CG_TACH_STATUS__SI__CI regCG_TACH_STATUS__SI__CI; -typedef union CG_TARG_REF_CLK_CNTL__CI__VI regCG_TARG_REF_CLK_CNTL__CI__VI; -typedef union CG_THERMAL_CTRL__SI__CI regCG_THERMAL_CTRL__SI__CI; -typedef union CG_THERMAL_INT__SI__CI regCG_THERMAL_INT__SI__CI; -typedef union CG_THERMAL_INT_CTRL__CI__VI regCG_THERMAL_INT_CTRL__CI__VI; -typedef union CG_THERMAL_INT_ENA__CI__VI regCG_THERMAL_INT_ENA__CI__VI; -typedef union CG_THERMAL_INT_STATUS__CI__VI regCG_THERMAL_INT_STATUS__CI__VI; -typedef union CG_THERMAL_RANGE__SI__CI regCG_THERMAL_RANGE__SI__CI; -typedef union CG_THERMAL_STATUS__SI__CI regCG_THERMAL_STATUS__SI__CI; -typedef union CG_TIMESTAMP_HIGH__SI regCG_TIMESTAMP_HIGH__SI; -typedef union CG_TIMESTAMP_LOW__SI regCG_TIMESTAMP_LOW__SI; -typedef union CG_ULV_CONTROL__CI__VI regCG_ULV_CONTROL__CI__VI; -typedef union CG_ULV_CONTROL__SI regCG_ULV_CONTROL__SI; -typedef union CG_ULV_PARAMETER regCG_ULV_PARAMETER; -typedef union CG_ULV_VOTING__CI regCG_ULV_VOTING__CI; -typedef union CG_ULV_VOTING__VI regCG_ULV_VOTING__VI; -typedef union CG_UPLL_FUNC_CNTL_2__SI regCG_UPLL_FUNC_CNTL_2__SI; -typedef union CG_UPLL_FUNC_CNTL_3__SI regCG_UPLL_FUNC_CNTL_3__SI; -typedef union CG_UPLL_FUNC_CNTL_4__SI regCG_UPLL_FUNC_CNTL_4__SI; -typedef union CG_UPLL_FUNC_CNTL_5__SI regCG_UPLL_FUNC_CNTL_5__SI; -typedef union CG_UPLL_FUNC_CNTL__SI regCG_UPLL_FUNC_CNTL__SI; -typedef union CG_UPLL_SPREAD_SPECTRUM_2__SI regCG_UPLL_SPREAD_SPECTRUM_2__SI; -typedef union CG_UPLL_SPREAD_SPECTRUM__SI regCG_UPLL_SPREAD_SPECTRUM__SI; -typedef union CG_UPLL_STATUS__SI regCG_UPLL_STATUS__SI; -typedef union CG_VCEPLL_FUNC_CNTL_2__SI regCG_VCEPLL_FUNC_CNTL_2__SI; -typedef union CG_VCEPLL_FUNC_CNTL_3__SI regCG_VCEPLL_FUNC_CNTL_3__SI; -typedef union CG_VCEPLL_FUNC_CNTL_4__SI regCG_VCEPLL_FUNC_CNTL_4__SI; -typedef union CG_VCEPLL_FUNC_CNTL_5__SI regCG_VCEPLL_FUNC_CNTL_5__SI; -typedef union CG_VCEPLL_FUNC_CNTL__SI regCG_VCEPLL_FUNC_CNTL__SI; -typedef union CG_VCEPLL_SPREAD_SPECTRUM_2__SI regCG_VCEPLL_SPREAD_SPECTRUM_2__SI; -typedef union CG_VCEPLL_SPREAD_SPECTRUM__SI regCG_VCEPLL_SPREAD_SPECTRUM__SI; -typedef union CG_VCEPLL_STATUS__SI regCG_VCEPLL_STATUS__SI; -typedef union CG_VCLK_CNTL__CI__VI regCG_VCLK_CNTL__CI__VI; -typedef union CG_VCLK_DCLK_OVERCLOCKING_ATTEMPTS__CI__VI - regCG_VCLK_DCLK_OVERCLOCKING_ATTEMPTS__CI__VI; -typedef union CG_VCLK_STATUS__CI__VI regCG_VCLK_STATUS__CI__VI; -typedef union CG_WRM_RST_CNTL__CI__VI regCG_WRM_RST_CNTL__CI__VI; -typedef union CHROMA_BOT_ADDR__SI regCHROMA_BOT_ADDR__SI; -typedef union CHROMA_TOP_ADDR__SI regCHROMA_TOP_ADDR__SI; -typedef union CHUB_ATC_PERFCOUNTER0_CFG__CI__VI regCHUB_ATC_PERFCOUNTER0_CFG__CI__VI; -typedef union CHUB_ATC_PERFCOUNTER1_CFG__CI__VI regCHUB_ATC_PERFCOUNTER1_CFG__CI__VI; -typedef union CHUB_ATC_PERFCOUNTER_HI__CI__VI regCHUB_ATC_PERFCOUNTER_HI__CI__VI; -typedef union CHUB_ATC_PERFCOUNTER_LO__CI__VI regCHUB_ATC_PERFCOUNTER_LO__CI__VI; -typedef union CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI regCHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union CLIENT0_BM regCLIENT0_BM; -typedef union CLIENT0_CD0 regCLIENT0_CD0; -typedef union CLIENT0_CD1 regCLIENT0_CD1; -typedef union CLIENT0_CD2 regCLIENT0_CD2; -typedef union CLIENT0_CD3 regCLIENT0_CD3; -typedef union CLIENT0_CK0 regCLIENT0_CK0; -typedef union CLIENT0_CK1 regCLIENT0_CK1; -typedef union CLIENT0_CK2 regCLIENT0_CK2; -typedef union CLIENT0_CK3 regCLIENT0_CK3; -typedef union CLIENT0_K0 regCLIENT0_K0; -typedef union CLIENT0_K1 regCLIENT0_K1; -typedef union CLIENT0_K2 regCLIENT0_K2; -typedef union CLIENT0_K3 regCLIENT0_K3; -typedef union CLIENT0_OFFSET regCLIENT0_OFFSET; -typedef union CLIENT0_STATUS regCLIENT0_STATUS; -typedef union CLIENT1_BM regCLIENT1_BM; -typedef union CLIENT1_CD0 regCLIENT1_CD0; -typedef union CLIENT1_CD1 regCLIENT1_CD1; -typedef union CLIENT1_CD2 regCLIENT1_CD2; -typedef union CLIENT1_CD3 regCLIENT1_CD3; -typedef union CLIENT1_CK0 regCLIENT1_CK0; -typedef union CLIENT1_CK1 regCLIENT1_CK1; -typedef union CLIENT1_CK2 regCLIENT1_CK2; -typedef union CLIENT1_CK3 regCLIENT1_CK3; -typedef union CLIENT1_K0 regCLIENT1_K0; -typedef union CLIENT1_K1 regCLIENT1_K1; -typedef union CLIENT1_K2 regCLIENT1_K2; -typedef union CLIENT1_K3 regCLIENT1_K3; -typedef union CLIENT1_OFFSET regCLIENT1_OFFSET; -typedef union CLIENT1_PORT_STATUS regCLIENT1_PORT_STATUS; -typedef union CLIENT2_BM regCLIENT2_BM; -typedef union CLIENT2_CD0 regCLIENT2_CD0; -typedef union CLIENT2_CD1 regCLIENT2_CD1; -typedef union CLIENT2_CD2 regCLIENT2_CD2; -typedef union CLIENT2_CD3 regCLIENT2_CD3; -typedef union CLIENT2_CK0 regCLIENT2_CK0; -typedef union CLIENT2_CK1 regCLIENT2_CK1; -typedef union CLIENT2_CK2 regCLIENT2_CK2; -typedef union CLIENT2_CK3 regCLIENT2_CK3; -typedef union CLIENT2_K0 regCLIENT2_K0; -typedef union CLIENT2_K1 regCLIENT2_K1; -typedef union CLIENT2_K2 regCLIENT2_K2; -typedef union CLIENT2_K3 regCLIENT2_K3; -typedef union CLIENT2_OFFSET regCLIENT2_OFFSET; -typedef union CLIENT2_STATUS regCLIENT2_STATUS; -typedef union CLIPPER_DEBUG_REG00 regCLIPPER_DEBUG_REG00; -typedef union CLIPPER_DEBUG_REG01 regCLIPPER_DEBUG_REG01; -typedef union CLIPPER_DEBUG_REG02 regCLIPPER_DEBUG_REG02; -typedef union CLIPPER_DEBUG_REG03 regCLIPPER_DEBUG_REG03; -typedef union CLIPPER_DEBUG_REG04 regCLIPPER_DEBUG_REG04; -typedef union CLIPPER_DEBUG_REG05 regCLIPPER_DEBUG_REG05; -typedef union CLIPPER_DEBUG_REG06 regCLIPPER_DEBUG_REG06; -typedef union CLIPPER_DEBUG_REG07 regCLIPPER_DEBUG_REG07; -typedef union CLIPPER_DEBUG_REG08 regCLIPPER_DEBUG_REG08; -typedef union CLIPPER_DEBUG_REG09 regCLIPPER_DEBUG_REG09; -typedef union CLIPPER_DEBUG_REG10 regCLIPPER_DEBUG_REG10; -typedef union CLIPPER_DEBUG_REG11 regCLIPPER_DEBUG_REG11; -typedef union CLIPPER_DEBUG_REG12 regCLIPPER_DEBUG_REG12; -typedef union CLIPPER_DEBUG_REG13 regCLIPPER_DEBUG_REG13; -typedef union CLIPPER_DEBUG_REG14 regCLIPPER_DEBUG_REG14; -typedef union CLIPPER_DEBUG_REG15 regCLIPPER_DEBUG_REG15; -typedef union CLIPPER_DEBUG_REG16 regCLIPPER_DEBUG_REG16; -typedef union CLIPPER_DEBUG_REG17 regCLIPPER_DEBUG_REG17; -typedef union CLIPPER_DEBUG_REG18 regCLIPPER_DEBUG_REG18; -typedef union CLIPPER_DEBUG_REG19 regCLIPPER_DEBUG_REG19; -typedef union CLKREQB_PAD_CNTL__CI__VI regCLKREQB_PAD_CNTL__CI__VI; -typedef union CLOCK_POWER_CONTROL_5__CI__VI regCLOCK_POWER_CONTROL_5__CI__VI; -typedef union CMON_REGION_LOWER__SI__CI regCMON_REGION_LOWER__SI__CI; -typedef union CMON_REGION_UPPER__SI__CI regCMON_REGION_UPPER__SI__CI; -typedef union CMON_REG__SI regCMON_REG__SI; -typedef union CM_ARB_READ_CTL__SI regCM_ARB_READ_CTL__SI; -typedef union CM_ARB_WRITE_CTL__SI regCM_ARB_WRITE_CTL__SI; -typedef union CM_BITPLANE_MODE__SI regCM_BITPLANE_MODE__SI; -typedef union CM_BLK_STAT__SI regCM_BLK_STAT__SI; -typedef union CM_BUF_EMPTY__SI regCM_BUF_EMPTY__SI; -typedef union CM_COLOC_ADR__SI regCM_COLOC_ADR__SI; -typedef union CM_COLOC_LOC__SI regCM_COLOC_LOC__SI; -typedef union CM_COLOC_SCAN_INFO__SI regCM_COLOC_SCAN_INFO__SI; -typedef union CM_COLOC_STAT__SI regCM_COLOC_STAT__SI; -typedef union CM_CTL__SI regCM_CTL__SI; -typedef union CM_CTXT_ADR__SI regCM_CTXT_ADR__SI; -typedef union CM_CTXT_FMO_MBNR__SI regCM_CTXT_FMO_MBNR__SI; -typedef union CM_CTXT_TOP_FMO__SI regCM_CTXT_TOP_FMO__SI; -typedef union CM_CTXT_TOP_PREFETCH__SI regCM_CTXT_TOP_PREFETCH__SI; -typedef union CM_CURRENT_STAT__SI regCM_CURRENT_STAT__SI; -typedef union CM_DEBUG_INT_STAT__SI regCM_DEBUG_INT_STAT__SI; -typedef union CM_FW_ADR__SI regCM_FW_ADR__SI; -typedef union CM_FW_CTL__SI regCM_FW_CTL__SI; -typedef union CM_FW_LOWER_DAT__SI regCM_FW_LOWER_DAT__SI; -typedef union CM_FW_UPPER_DAT__SI regCM_FW_UPPER_DAT__SI; -typedef union CM_HW_DEBUG__SI regCM_HW_DEBUG__SI; -typedef union CM_INIT_TOP_BUF_NUM__SI regCM_INIT_TOP_BUF_NUM__SI; -typedef union CM_INT_EN__SI regCM_INT_EN__SI; -typedef union CM_INT_STAT__SI regCM_INT_STAT__SI; -typedef union CM_LMA_ADR__SI regCM_LMA_ADR__SI; -typedef union CM_LMA_CTL__SI regCM_LMA_CTL__SI; -typedef union CM_LMA_DAT__SI regCM_LMA_DAT__SI; -typedef union CM_QWORD8_BOTTOM__SI regCM_QWORD8_BOTTOM__SI; -typedef union CM_QWORD8_TOP__SI regCM_QWORD8_TOP__SI; -typedef union CM_RELEASE__SI regCM_RELEASE__SI; -typedef union CM_SLICE_INFO__SI regCM_SLICE_INFO__SI; -typedef union CM_SPS_INFO__SI regCM_SPS_INFO__SI; -typedef union CM_SRAM_RM_CTL__SI regCM_SRAM_RM_CTL__SI; -typedef union CM_STAT__SI regCM_STAT__SI; -typedef union CM_TOP_STAT__SI regCM_TOP_STAT__SI; -typedef union CNB_PWRMGT_CNTL__CI__VI regCNB_PWRMGT_CNTL__CI__VI; -typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; -typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; -typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; -typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; -typedef union COHER_DEST_BASE_HI_0__CI__VI regCOHER_DEST_BASE_HI_0__CI__VI; -typedef union COHER_DEST_BASE_HI_1__CI__VI regCOHER_DEST_BASE_HI_1__CI__VI; -typedef union COHER_DEST_BASE_HI_2__CI__VI regCOHER_DEST_BASE_HI_2__CI__VI; -typedef union COHER_DEST_BASE_HI_3__CI__VI regCOHER_DEST_BASE_HI_3__CI__VI; -typedef union COLOR_MATRIX_COEF_1_1__SI regCOLOR_MATRIX_COEF_1_1__SI; -typedef union COLOR_MATRIX_COEF_1_2__SI regCOLOR_MATRIX_COEF_1_2__SI; -typedef union COLOR_MATRIX_COEF_1_3__SI regCOLOR_MATRIX_COEF_1_3__SI; -typedef union COLOR_MATRIX_COEF_1_4__SI regCOLOR_MATRIX_COEF_1_4__SI; -typedef union COLOR_MATRIX_COEF_2_1__SI regCOLOR_MATRIX_COEF_2_1__SI; -typedef union COLOR_MATRIX_COEF_2_2__SI regCOLOR_MATRIX_COEF_2_2__SI; -typedef union COLOR_MATRIX_COEF_2_3__SI regCOLOR_MATRIX_COEF_2_3__SI; -typedef union COLOR_MATRIX_COEF_2_4__SI regCOLOR_MATRIX_COEF_2_4__SI; -typedef union COLOR_MATRIX_COEF_3_1__SI regCOLOR_MATRIX_COEF_3_1__SI; -typedef union COLOR_MATRIX_COEF_3_2__SI regCOLOR_MATRIX_COEF_3_2__SI; -typedef union COLOR_MATRIX_COEF_3_3__SI regCOLOR_MATRIX_COEF_3_3__SI; -typedef union COLOR_MATRIX_COEF_3_4__SI regCOLOR_MATRIX_COEF_3_4__SI; -typedef union COLOR_SPACE_CONVERT__SI regCOLOR_SPACE_CONVERT__SI; -typedef union COMMAND regCOMMAND; -typedef union COMPUTE_DIM_X regCOMPUTE_DIM_X; -typedef union COMPUTE_DIM_Y regCOMPUTE_DIM_Y; -typedef union COMPUTE_DIM_Z regCOMPUTE_DIM_Z; -typedef union COMPUTE_DISPATCH_INITIATOR regCOMPUTE_DISPATCH_INITIATOR; -typedef union COMPUTE_MAX_WAVE_ID__SI regCOMPUTE_MAX_WAVE_ID__SI; -typedef union COMPUTE_MISC_RESERVED__CI__VI regCOMPUTE_MISC_RESERVED__CI__VI; -typedef union COMPUTE_NUM_THREAD_X regCOMPUTE_NUM_THREAD_X; -typedef union COMPUTE_NUM_THREAD_Y regCOMPUTE_NUM_THREAD_Y; -typedef union COMPUTE_NUM_THREAD_Z regCOMPUTE_NUM_THREAD_Z; -typedef union COMPUTE_PERFCOUNT_ENABLE__CI__VI regCOMPUTE_PERFCOUNT_ENABLE__CI__VI; -typedef union COMPUTE_PGM_HI regCOMPUTE_PGM_HI; -typedef union COMPUTE_PGM_LO regCOMPUTE_PGM_LO; -typedef union COMPUTE_PGM_RSRC1 regCOMPUTE_PGM_RSRC1; -typedef union COMPUTE_PGM_RSRC2 regCOMPUTE_PGM_RSRC2; -typedef union COMPUTE_PIPELINESTAT_ENABLE__CI__VI regCOMPUTE_PIPELINESTAT_ENABLE__CI__VI; -typedef union COMPUTE_RESOURCE_LIMITS regCOMPUTE_RESOURCE_LIMITS; -typedef union COMPUTE_RESTART_X__CI__VI regCOMPUTE_RESTART_X__CI__VI; -typedef union COMPUTE_RESTART_Y__CI__VI regCOMPUTE_RESTART_Y__CI__VI; -typedef union COMPUTE_RESTART_Z__CI__VI regCOMPUTE_RESTART_Z__CI__VI; -typedef union COMPUTE_START_X regCOMPUTE_START_X; -typedef union COMPUTE_START_Y regCOMPUTE_START_Y; -typedef union COMPUTE_START_Z regCOMPUTE_START_Z; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE0 regCOMPUTE_STATIC_THREAD_MGMT_SE0; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE1 regCOMPUTE_STATIC_THREAD_MGMT_SE1; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI regCOMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI regCOMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI; -typedef union COMPUTE_TBA_HI regCOMPUTE_TBA_HI; -typedef union COMPUTE_TBA_LO regCOMPUTE_TBA_LO; -typedef union COMPUTE_THREAD_TRACE_ENABLE__CI__VI regCOMPUTE_THREAD_TRACE_ENABLE__CI__VI; -typedef union COMPUTE_TMA_HI regCOMPUTE_TMA_HI; -typedef union COMPUTE_TMA_LO regCOMPUTE_TMA_LO; -typedef union COMPUTE_TMPRING_SIZE regCOMPUTE_TMPRING_SIZE; -typedef union COMPUTE_USER_DATA_0 regCOMPUTE_USER_DATA_0; -typedef union COMPUTE_USER_DATA_1 regCOMPUTE_USER_DATA_1; -typedef union COMPUTE_USER_DATA_10 regCOMPUTE_USER_DATA_10; -typedef union COMPUTE_USER_DATA_11 regCOMPUTE_USER_DATA_11; -typedef union COMPUTE_USER_DATA_12 regCOMPUTE_USER_DATA_12; -typedef union COMPUTE_USER_DATA_13 regCOMPUTE_USER_DATA_13; -typedef union COMPUTE_USER_DATA_14 regCOMPUTE_USER_DATA_14; -typedef union COMPUTE_USER_DATA_15 regCOMPUTE_USER_DATA_15; -typedef union COMPUTE_USER_DATA_2 regCOMPUTE_USER_DATA_2; -typedef union COMPUTE_USER_DATA_3 regCOMPUTE_USER_DATA_3; -typedef union COMPUTE_USER_DATA_4 regCOMPUTE_USER_DATA_4; -typedef union COMPUTE_USER_DATA_5 regCOMPUTE_USER_DATA_5; -typedef union COMPUTE_USER_DATA_6 regCOMPUTE_USER_DATA_6; -typedef union COMPUTE_USER_DATA_7 regCOMPUTE_USER_DATA_7; -typedef union COMPUTE_USER_DATA_8 regCOMPUTE_USER_DATA_8; -typedef union COMPUTE_USER_DATA_9 regCOMPUTE_USER_DATA_9; -typedef union COMPUTE_VMID regCOMPUTE_VMID; -typedef union CONFIG_APER_SIZE regCONFIG_APER_SIZE; -typedef union CONFIG_CNTL regCONFIG_CNTL; -typedef union CONFIG_F0_BASE regCONFIG_F0_BASE; -typedef union CONFIG_MEMSIZE regCONFIG_MEMSIZE; -typedef union CONFIG_REG_APER_SIZE regCONFIG_REG_APER_SIZE; -typedef union CORB_CONTROL__SI regCORB_CONTROL__SI; -typedef union CORB_LOWER_BASE_ADDRESS__SI regCORB_LOWER_BASE_ADDRESS__SI; -typedef union CORB_READ_POINTER__SI regCORB_READ_POINTER__SI; -typedef union CORB_SIZE__SI regCORB_SIZE__SI; -typedef union CORB_STATUS__SI regCORB_STATUS__SI; -typedef union CORB_UPPER_BASE_ADDRESS__SI regCORB_UPPER_BASE_ADDRESS__SI; -typedef union CORB_WRITE_POINTER__SI regCORB_WRITE_POINTER__SI; -typedef union CORE_PERF_BOOST_CONTROL__CI__VI regCORE_PERF_BOOST_CONTROL__CI__VI; -typedef union CPC1_CONFIG__CI regCPC1_CONFIG__CI; -typedef union CPC2_CONFIG__CI regCPC2_CONFIG__CI; -typedef union CPC_INT_CNTL__CI__VI regCPC_INT_CNTL__CI__VI; -typedef union CPC_INT_CNTX_ID__CI__VI regCPC_INT_CNTX_ID__CI__VI; -typedef union CPC_INT_STATUS__CI__VI regCPC_INT_STATUS__CI__VI; -typedef union CPC_PERFCOUNTER0_HI__CI__VI regCPC_PERFCOUNTER0_HI__CI__VI; -typedef union CPC_PERFCOUNTER0_LO__CI__VI regCPC_PERFCOUNTER0_LO__CI__VI; -typedef union CPC_PERFCOUNTER0_SELECT1__CI__VI regCPC_PERFCOUNTER0_SELECT1__CI__VI; -typedef union CPC_PERFCOUNTER0_SELECT__CI__VI regCPC_PERFCOUNTER0_SELECT__CI__VI; -typedef union CPC_PERFCOUNTER1_HI__CI__VI regCPC_PERFCOUNTER1_HI__CI__VI; -typedef union CPC_PERFCOUNTER1_LO__CI__VI regCPC_PERFCOUNTER1_LO__CI__VI; -typedef union CPC_PERFCOUNTER1_SELECT__CI__VI regCPC_PERFCOUNTER1_SELECT__CI__VI; -typedef union CPF_PERFCOUNTER0_HI__CI__VI regCPF_PERFCOUNTER0_HI__CI__VI; -typedef union CPF_PERFCOUNTER0_LO__CI__VI regCPF_PERFCOUNTER0_LO__CI__VI; -typedef union CPF_PERFCOUNTER0_SELECT1__CI__VI regCPF_PERFCOUNTER0_SELECT1__CI__VI; -typedef union CPF_PERFCOUNTER0_SELECT__CI__VI regCPF_PERFCOUNTER0_SELECT__CI__VI; -typedef union CPF_PERFCOUNTER1_HI__CI__VI regCPF_PERFCOUNTER1_HI__CI__VI; -typedef union CPF_PERFCOUNTER1_LO__CI__VI regCPF_PERFCOUNTER1_LO__CI__VI; -typedef union CPF_PERFCOUNTER1_SELECT__CI__VI regCPF_PERFCOUNTER1_SELECT__CI__VI; -typedef union CPG_CONFIG__CI regCPG_CONFIG__CI; -typedef union CPG_PERFCOUNTER0_HI__CI__VI regCPG_PERFCOUNTER0_HI__CI__VI; -typedef union CPG_PERFCOUNTER0_LO__CI__VI regCPG_PERFCOUNTER0_LO__CI__VI; -typedef union CPG_PERFCOUNTER0_SELECT1__CI__VI regCPG_PERFCOUNTER0_SELECT1__CI__VI; -typedef union CPG_PERFCOUNTER0_SELECT__CI__VI regCPG_PERFCOUNTER0_SELECT__CI__VI; -typedef union CPG_PERFCOUNTER1_HI__CI__VI regCPG_PERFCOUNTER1_HI__CI__VI; -typedef union CPG_PERFCOUNTER1_LO__CI__VI regCPG_PERFCOUNTER1_LO__CI__VI; -typedef union CPG_PERFCOUNTER1_SELECT__CI__VI regCPG_PERFCOUNTER1_SELECT__CI__VI; -typedef union CPU_INT_ARGUMENT__CI__VI regCPU_INT_ARGUMENT__CI__VI; -typedef union CPU_INT_REQ__CI__VI regCPU_INT_REQ__CI__VI; -typedef union CPU_INT_RESPONSE__CI__VI regCPU_INT_RESPONSE__CI__VI; -typedef union CPU_INT_STATUS__CI__VI regCPU_INT_STATUS__CI__VI; -typedef union CPU_TDP_LIMIT_0__CI__VI regCPU_TDP_LIMIT_0__CI__VI; -typedef union CPU_TDP_LIMIT_1__CI__VI regCPU_TDP_LIMIT_1__CI__VI; -typedef union CPU_TDP_RUN_AVG__CI__VI regCPU_TDP_RUN_AVG__CI__VI; -typedef union CP_APPEND_ADDR_HI__SI__CI regCP_APPEND_ADDR_HI__SI__CI; -typedef union CP_APPEND_ADDR_HI__VI regCP_APPEND_ADDR_HI__VI; -typedef union CP_APPEND_ADDR_LO regCP_APPEND_ADDR_LO; -typedef union CP_APPEND_DATA regCP_APPEND_DATA; -typedef union CP_APPEND_LAST_CS_FENCE regCP_APPEND_LAST_CS_FENCE; -typedef union CP_APPEND_LAST_PS_FENCE regCP_APPEND_LAST_PS_FENCE; -typedef union CP_ATOMIC_PREOP_HI regCP_ATOMIC_PREOP_HI; -typedef union CP_ATOMIC_PREOP_LO regCP_ATOMIC_PREOP_LO; -typedef union CP_BUSY_STAT regCP_BUSY_STAT; -typedef union CP_CEQ1_AVAIL regCP_CEQ1_AVAIL; -typedef union CP_CEQ2_AVAIL regCP_CEQ2_AVAIL; -typedef union CP_CE_COMPARE_COUNT__CI__VI regCP_CE_COMPARE_COUNT__CI__VI; -typedef union CP_CE_COUNTER__CI__VI regCP_CE_COUNTER__CI__VI; -typedef union CP_CE_DE_COUNT__CI__VI regCP_CE_DE_COUNT__CI__VI; -typedef union CP_CE_F32_INTERRUPT__CI__VI regCP_CE_F32_INTERRUPT__CI__VI; -typedef union CP_CE_HEADER_DUMP regCP_CE_HEADER_DUMP; -typedef union CP_CE_IB1_BASE_HI regCP_CE_IB1_BASE_HI; -typedef union CP_CE_IB1_BASE_LO regCP_CE_IB1_BASE_LO; -typedef union CP_CE_IB1_BUFSZ regCP_CE_IB1_BUFSZ; -typedef union CP_CE_IB1_OFFSET__CI__VI regCP_CE_IB1_OFFSET__CI__VI; -typedef union CP_CE_IB2_BASE_HI regCP_CE_IB2_BASE_HI; -typedef union CP_CE_IB2_BASE_LO regCP_CE_IB2_BASE_LO; -typedef union CP_CE_IB2_BUFSZ regCP_CE_IB2_BUFSZ; -typedef union CP_CE_IB2_OFFSET__CI__VI regCP_CE_IB2_OFFSET__CI__VI; -typedef union CP_CE_INIT_BASE_HI regCP_CE_INIT_BASE_HI; -typedef union CP_CE_INIT_BASE_LO regCP_CE_INIT_BASE_LO; -typedef union CP_CE_INIT_BUFSZ regCP_CE_INIT_BUFSZ; -typedef union CP_CE_INTR_ROUTINE_START__CI__VI regCP_CE_INTR_ROUTINE_START__CI__VI; -typedef union CP_CE_PRGRM_CNTR_START__CI__VI regCP_CE_PRGRM_CNTR_START__CI__VI; -typedef union CP_CE_ROQ_IB1_STAT regCP_CE_ROQ_IB1_STAT; -typedef union CP_CE_ROQ_IB2_STAT regCP_CE_ROQ_IB2_STAT; -typedef union CP_CE_ROQ_RB_STAT regCP_CE_ROQ_RB_STAT; -typedef union CP_CE_UCODE_ADDR regCP_CE_UCODE_ADDR; -typedef union CP_CE_UCODE_DATA regCP_CE_UCODE_DATA; -typedef union CP_CMD_DATA regCP_CMD_DATA; -typedef union CP_CMD_INDEX regCP_CMD_INDEX; -typedef union CP_CNTL__SI regCP_CNTL__SI; -typedef union CP_CNTX_STAT__CI__VI regCP_CNTX_STAT__CI__VI; -typedef union CP_CNTX_STAT__SI regCP_CNTX_STAT__SI; -typedef union CP_COHER_BASE regCP_COHER_BASE; -typedef union CP_COHER_BASE_HI__CI__VI regCP_COHER_BASE_HI__CI__VI; -typedef union CP_COHER_CNTL regCP_COHER_CNTL; -typedef union CP_COHER_CNTL2__SI regCP_COHER_CNTL2__SI; -typedef union CP_COHER_SIZE regCP_COHER_SIZE; -typedef union CP_COHER_SIZE_HI__CI__VI regCP_COHER_SIZE_HI__CI__VI; -typedef union CP_COHER_START_DELAY regCP_COHER_START_DELAY; -typedef union CP_COHER_STATUS regCP_COHER_STATUS; -typedef union CP_CONFIG__SI regCP_CONFIG__SI; -typedef union CP_CONTEXT_CNTL__CI__VI regCP_CONTEXT_CNTL__CI__VI; -typedef union CP_CPC_BUSY_STAT__CI__VI regCP_CPC_BUSY_STAT__CI__VI; -typedef union CP_CPC_DEBUG_CNTL__CI__VI regCP_CPC_DEBUG_CNTL__CI__VI; -typedef union CP_CPC_DEBUG_DATA__CI__VI regCP_CPC_DEBUG_DATA__CI__VI; -typedef union CP_CPC_DEBUG__CI__VI regCP_CPC_DEBUG__CI__VI; -typedef union CP_CPC_GRBM_FREE_COUNT__CI__VI regCP_CPC_GRBM_FREE_COUNT__CI__VI; -typedef union CP_CPC_HALT_HYST_COUNT__CI__VI regCP_CPC_HALT_HYST_COUNT__CI__VI; -typedef union CP_CPC_MC_CNTL__CI regCP_CPC_MC_CNTL__CI; -typedef union CP_CPC_PRIV_VIOLATION_ADDR__CI__VI regCP_CPC_PRIV_VIOLATION_ADDR__CI__VI; -typedef union CP_CPC_SCRATCH_DATA__CI__VI regCP_CPC_SCRATCH_DATA__CI__VI; -typedef union CP_CPC_SCRATCH_INDEX__CI__VI regCP_CPC_SCRATCH_INDEX__CI__VI; -typedef union CP_CPC_STALLED_STAT1__CI__VI regCP_CPC_STALLED_STAT1__CI__VI; -typedef union CP_CPC_STATUS__CI__VI regCP_CPC_STATUS__CI__VI; -typedef union CP_CPF_BUSY_STAT__CI__VI regCP_CPF_BUSY_STAT__CI__VI; -typedef union CP_CPF_DEBUG_CNTL__CI__VI regCP_CPF_DEBUG_CNTL__CI__VI; -typedef union CP_CPF_DEBUG_DATA__CI__VI regCP_CPF_DEBUG_DATA__CI__VI; -typedef union CP_CPF_DEBUG__CI__VI regCP_CPF_DEBUG__CI__VI; -typedef union CP_CPF_STALLED_STAT1__CI__VI regCP_CPF_STALLED_STAT1__CI__VI; -typedef union CP_CPF_STATUS__CI__VI regCP_CPF_STATUS__CI__VI; -typedef union CP_CSF_CNTL regCP_CSF_CNTL; -typedef union CP_CSF_STAT regCP_CSF_STAT; -typedef union CP_DEBUG_CNTL__CI__VI regCP_DEBUG_CNTL__CI__VI; -typedef union CP_DEBUG_CNTL__SI regCP_DEBUG_CNTL__SI; -typedef union CP_DEBUG_DATA__CI__VI regCP_DEBUG_DATA__CI__VI; -typedef union CP_DEBUG_DATA__SI regCP_DEBUG_DATA__SI; -typedef union CP_DEBUG__CI__VI regCP_DEBUG__CI__VI; -typedef union CP_DEBUG__SI regCP_DEBUG__SI; -typedef union CP_DEVICE_ID__CI__VI regCP_DEVICE_ID__CI__VI; -typedef union CP_DE_CE_COUNT__CI__VI regCP_DE_CE_COUNT__CI__VI; -typedef union CP_DE_DE_COUNT__CI__VI regCP_DE_DE_COUNT__CI__VI; -typedef union CP_DE_LAST_INVAL_COUNT__CI__VI regCP_DE_LAST_INVAL_COUNT__CI__VI; -typedef union CP_DFY_ADDR_HI__CI__VI regCP_DFY_ADDR_HI__CI__VI; -typedef union CP_DFY_ADDR_LO__CI__VI regCP_DFY_ADDR_LO__CI__VI; -typedef union CP_DFY_CNTL__CI regCP_DFY_CNTL__CI; -typedef union CP_DFY_CNTL__VI regCP_DFY_CNTL__VI; -typedef union CP_DFY_DATA_0__CI__VI regCP_DFY_DATA_0__CI__VI; -typedef union CP_DFY_DATA_10__CI__VI regCP_DFY_DATA_10__CI__VI; -typedef union CP_DFY_DATA_11__CI__VI regCP_DFY_DATA_11__CI__VI; -typedef union CP_DFY_DATA_12__CI__VI regCP_DFY_DATA_12__CI__VI; -typedef union CP_DFY_DATA_13__CI__VI regCP_DFY_DATA_13__CI__VI; -typedef union CP_DFY_DATA_14__CI__VI regCP_DFY_DATA_14__CI__VI; -typedef union CP_DFY_DATA_15__CI__VI regCP_DFY_DATA_15__CI__VI; -typedef union CP_DFY_DATA_1__CI__VI regCP_DFY_DATA_1__CI__VI; -typedef union CP_DFY_DATA_2__CI__VI regCP_DFY_DATA_2__CI__VI; -typedef union CP_DFY_DATA_3__CI__VI regCP_DFY_DATA_3__CI__VI; -typedef union CP_DFY_DATA_4__CI__VI regCP_DFY_DATA_4__CI__VI; -typedef union CP_DFY_DATA_5__CI__VI regCP_DFY_DATA_5__CI__VI; -typedef union CP_DFY_DATA_6__CI__VI regCP_DFY_DATA_6__CI__VI; -typedef union CP_DFY_DATA_7__CI__VI regCP_DFY_DATA_7__CI__VI; -typedef union CP_DFY_DATA_8__CI__VI regCP_DFY_DATA_8__CI__VI; -typedef union CP_DFY_DATA_9__CI__VI regCP_DFY_DATA_9__CI__VI; -typedef union CP_DFY_STAT__CI__VI regCP_DFY_STAT__CI__VI; -typedef union CP_DMA_CNTL regCP_DMA_CNTL; -typedef union CP_DMA_ME_COMMAND regCP_DMA_ME_COMMAND; -typedef union CP_DMA_ME_CONTROL__CI regCP_DMA_ME_CONTROL__CI; -typedef union CP_DMA_ME_CONTROL__VI regCP_DMA_ME_CONTROL__VI; -typedef union CP_DMA_ME_DST_ADDR regCP_DMA_ME_DST_ADDR; -typedef union CP_DMA_ME_DST_ADDR_HI regCP_DMA_ME_DST_ADDR_HI; -typedef union CP_DMA_ME_SRC_ADDR regCP_DMA_ME_SRC_ADDR; -typedef union CP_DMA_ME_SRC_ADDR_HI regCP_DMA_ME_SRC_ADDR_HI; -typedef union CP_DMA_PFP_COMMAND regCP_DMA_PFP_COMMAND; -typedef union CP_DMA_PFP_CONTROL__CI regCP_DMA_PFP_CONTROL__CI; -typedef union CP_DMA_PFP_CONTROL__VI regCP_DMA_PFP_CONTROL__VI; -typedef union CP_DMA_PFP_DST_ADDR regCP_DMA_PFP_DST_ADDR; -typedef union CP_DMA_PFP_DST_ADDR_HI regCP_DMA_PFP_DST_ADDR_HI; -typedef union CP_DMA_PFP_SRC_ADDR regCP_DMA_PFP_SRC_ADDR; -typedef union CP_DMA_PFP_SRC_ADDR_HI regCP_DMA_PFP_SRC_ADDR_HI; -typedef union CP_DMA_PIO_COMMAND regCP_DMA_PIO_COMMAND; -typedef union CP_DMA_PIO_CONTROL__CI regCP_DMA_PIO_CONTROL__CI; -typedef union CP_DMA_PIO_CONTROL__VI regCP_DMA_PIO_CONTROL__VI; -typedef union CP_DMA_PIO_DST_ADDR regCP_DMA_PIO_DST_ADDR; -typedef union CP_DMA_PIO_DST_ADDR_HI regCP_DMA_PIO_DST_ADDR_HI; -typedef union CP_DMA_PIO_SRC_ADDR regCP_DMA_PIO_SRC_ADDR; -typedef union CP_DMA_PIO_SRC_ADDR_HI regCP_DMA_PIO_SRC_ADDR_HI; -typedef union CP_DMA_READ_TAGS regCP_DMA_READ_TAGS; -typedef union CP_ECC_FIRSTOCCURRENCE__SI__CI regCP_ECC_FIRSTOCCURRENCE__SI__CI; -typedef union CP_ECC_FIRSTOCCURRENCE__VI regCP_ECC_FIRSTOCCURRENCE__VI; -typedef union CP_ECC_FIRSTOCCURRENCE_RING0__SI__CI regCP_ECC_FIRSTOCCURRENCE_RING0__SI__CI; -typedef union CP_ECC_FIRSTOCCURRENCE_RING0__VI regCP_ECC_FIRSTOCCURRENCE_RING0__VI; -typedef union CP_ECC_FIRSTOCCURRENCE_RING1__SI__CI regCP_ECC_FIRSTOCCURRENCE_RING1__SI__CI; -typedef union CP_ECC_FIRSTOCCURRENCE_RING1__VI regCP_ECC_FIRSTOCCURRENCE_RING1__VI; -typedef union CP_ECC_FIRSTOCCURRENCE_RING2__SI__CI regCP_ECC_FIRSTOCCURRENCE_RING2__SI__CI; -typedef union CP_ECC_FIRSTOCCURRENCE_RING2__VI regCP_ECC_FIRSTOCCURRENCE_RING2__VI; -typedef union CP_ENDIAN_SWAP__CI__VI regCP_ENDIAN_SWAP__CI__VI; -typedef union CP_EOP_DONE_ADDR_HI__CI__VI regCP_EOP_DONE_ADDR_HI__CI__VI; -typedef union CP_EOP_DONE_ADDR_HI__SI regCP_EOP_DONE_ADDR_HI__SI; -typedef union CP_EOP_DONE_ADDR_LO__CI__VI regCP_EOP_DONE_ADDR_LO__CI__VI; -typedef union CP_EOP_DONE_ADDR_LO__SI regCP_EOP_DONE_ADDR_LO__SI; -typedef union CP_EOP_DONE_DATA_CNTL__CI__VI regCP_EOP_DONE_DATA_CNTL__CI__VI; -typedef union CP_EOP_DONE_DATA_HI__CI__VI regCP_EOP_DONE_DATA_HI__CI__VI; -typedef union CP_EOP_DONE_DATA_HI__SI regCP_EOP_DONE_DATA_HI__SI; -typedef union CP_EOP_DONE_DATA_LO__CI__VI regCP_EOP_DONE_DATA_LO__CI__VI; -typedef union CP_EOP_DONE_DATA_LO__SI regCP_EOP_DONE_DATA_LO__SI; -typedef union CP_EOP_DONE_EVENT_CNTL__CI regCP_EOP_DONE_EVENT_CNTL__CI; -typedef union CP_EOP_DONE_EVENT_CNTL__VI regCP_EOP_DONE_EVENT_CNTL__VI; -typedef union CP_EOP_LAST_FENCE_HI regCP_EOP_LAST_FENCE_HI; -typedef union CP_EOP_LAST_FENCE_LO regCP_EOP_LAST_FENCE_LO; -typedef union CP_FETCHER_SOURCE__CI regCP_FETCHER_SOURCE__CI; -typedef union CP_GDS_ATOMIC0_PREOP_HI regCP_GDS_ATOMIC0_PREOP_HI; -typedef union CP_GDS_ATOMIC0_PREOP_LO regCP_GDS_ATOMIC0_PREOP_LO; -typedef union CP_GDS_ATOMIC1_PREOP_HI regCP_GDS_ATOMIC1_PREOP_HI; -typedef union CP_GDS_ATOMIC1_PREOP_LO regCP_GDS_ATOMIC1_PREOP_LO; -typedef union CP_GRBM_FREE_COUNT regCP_GRBM_FREE_COUNT; -typedef union CP_HPD_EOP_BASE_ADDR_HI__CI regCP_HPD_EOP_BASE_ADDR_HI__CI; -typedef union CP_HPD_EOP_BASE_ADDR__CI regCP_HPD_EOP_BASE_ADDR__CI; -typedef union CP_HPD_EOP_CONTROL__CI regCP_HPD_EOP_CONTROL__CI; -typedef union CP_HPD_EOP_VMID__CI regCP_HPD_EOP_VMID__CI; -typedef union CP_HPD_ROQ_OFFSETS__CI__VI regCP_HPD_ROQ_OFFSETS__CI__VI; -typedef union CP_HQD_ACTIVE__CI__VI regCP_HQD_ACTIVE__CI__VI; -typedef union CP_HQD_ATOMIC0_PREOP_HI__CI__VI regCP_HQD_ATOMIC0_PREOP_HI__CI__VI; -typedef union CP_HQD_ATOMIC0_PREOP_LO__CI__VI regCP_HQD_ATOMIC0_PREOP_LO__CI__VI; -typedef union CP_HQD_ATOMIC1_PREOP_HI__CI__VI regCP_HQD_ATOMIC1_PREOP_HI__CI__VI; -typedef union CP_HQD_ATOMIC1_PREOP_LO__CI__VI regCP_HQD_ATOMIC1_PREOP_LO__CI__VI; -typedef union CP_HQD_DEQUEUE_REQUEST__CI__VI regCP_HQD_DEQUEUE_REQUEST__CI__VI; -typedef union CP_HQD_DMA_OFFLOAD__CI__VI regCP_HQD_DMA_OFFLOAD__CI__VI; -typedef union CP_HQD_HQ_SCHEDULER0__CI regCP_HQD_HQ_SCHEDULER0__CI; -typedef union CP_HQD_HQ_SCHEDULER0__VI regCP_HQD_HQ_SCHEDULER0__VI; -typedef union CP_HQD_HQ_SCHEDULER1__CI__VI regCP_HQD_HQ_SCHEDULER1__CI__VI; -typedef union CP_HQD_IB_BASE_ADDR_HI__CI__VI regCP_HQD_IB_BASE_ADDR_HI__CI__VI; -typedef union CP_HQD_IB_BASE_ADDR__CI__VI regCP_HQD_IB_BASE_ADDR__CI__VI; -typedef union CP_HQD_IB_CONTROL__CI regCP_HQD_IB_CONTROL__CI; -typedef union CP_HQD_IB_CONTROL__VI regCP_HQD_IB_CONTROL__VI; -typedef union CP_HQD_IB_RPTR__CI__VI regCP_HQD_IB_RPTR__CI__VI; -typedef union CP_HQD_IQ_RPTR__CI__VI regCP_HQD_IQ_RPTR__CI__VI; -typedef union CP_HQD_IQ_TIMER__CI regCP_HQD_IQ_TIMER__CI; -typedef union CP_HQD_IQ_TIMER__VI regCP_HQD_IQ_TIMER__VI; -typedef union CP_HQD_MSG_TYPE__CI__VI regCP_HQD_MSG_TYPE__CI__VI; -typedef union CP_HQD_PERSISTENT_STATE__CI__VI regCP_HQD_PERSISTENT_STATE__CI__VI; -typedef union CP_HQD_PIPE_PRIORITY__CI__VI regCP_HQD_PIPE_PRIORITY__CI__VI; -typedef union CP_HQD_PQ_BASE_HI__CI__VI regCP_HQD_PQ_BASE_HI__CI__VI; -typedef union CP_HQD_PQ_BASE__CI__VI regCP_HQD_PQ_BASE__CI__VI; -typedef union CP_HQD_PQ_CONTROL__CI regCP_HQD_PQ_CONTROL__CI; -typedef union CP_HQD_PQ_CONTROL__VI regCP_HQD_PQ_CONTROL__VI; -typedef union CP_HQD_PQ_DOORBELL_CONTROL__CI__VI regCP_HQD_PQ_DOORBELL_CONTROL__CI__VI; -typedef union CP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI regCP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI; -typedef union CP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI regCP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI; -typedef union CP_HQD_PQ_RPTR__CI__VI regCP_HQD_PQ_RPTR__CI__VI; -typedef union CP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI regCP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI; -typedef union CP_HQD_PQ_WPTR_POLL_ADDR__CI__VI regCP_HQD_PQ_WPTR_POLL_ADDR__CI__VI; -typedef union CP_HQD_PQ_WPTR__CI__VI regCP_HQD_PQ_WPTR__CI__VI; -typedef union CP_HQD_QUANTUM__CI__VI regCP_HQD_QUANTUM__CI__VI; -typedef union CP_HQD_QUEUE_PRIORITY__CI__VI regCP_HQD_QUEUE_PRIORITY__CI__VI; -typedef union CP_HQD_SEMA_CMD__CI__VI regCP_HQD_SEMA_CMD__CI__VI; -typedef union CP_HQD_VMID__CI__VI regCP_HQD_VMID__CI__VI; -typedef union CP_HYP_REG_PRIV_LEVEL_A__CI__VI regCP_HYP_REG_PRIV_LEVEL_A__CI__VI; -typedef union CP_HYP_REG_PRIV_LEVEL_B__CI__VI regCP_HYP_REG_PRIV_LEVEL_B__CI__VI; -typedef union CP_HYP_REG_PRIV_LEVEL_C__CI__VI regCP_HYP_REG_PRIV_LEVEL_C__CI__VI; -typedef union CP_HYP_REG_PRIV_LEVEL_D__CI__VI regCP_HYP_REG_PRIV_LEVEL_D__CI__VI; -typedef union CP_IB1_BASE_HI regCP_IB1_BASE_HI; -typedef union CP_IB1_BASE_LO regCP_IB1_BASE_LO; -typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; -typedef union CP_IB1_OFFSET regCP_IB1_OFFSET; -typedef union CP_IB1_PREAMBLE_BEGIN regCP_IB1_PREAMBLE_BEGIN; -typedef union CP_IB1_PREAMBLE_END regCP_IB1_PREAMBLE_END; -typedef union CP_IB1_PRIV_BASE_HI regCP_IB1_PRIV_BASE_HI; -typedef union CP_IB1_PRIV_BASE_LO regCP_IB1_PRIV_BASE_LO; -typedef union CP_IB1_PRIV_BUFSZ regCP_IB1_PRIV_BUFSZ; -typedef union CP_IB2_BASE_HI regCP_IB2_BASE_HI; -typedef union CP_IB2_BASE_LO regCP_IB2_BASE_LO; -typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; -typedef union CP_IB2_OFFSET regCP_IB2_OFFSET; -typedef union CP_IB2_PREAMBLE_BEGIN regCP_IB2_PREAMBLE_BEGIN; -typedef union CP_IB2_PREAMBLE_END regCP_IB2_PREAMBLE_END; -typedef union CP_INT_CNTL_RING0__CI__VI regCP_INT_CNTL_RING0__CI__VI; -typedef union CP_INT_CNTL_RING0__SI regCP_INT_CNTL_RING0__SI; -typedef union CP_INT_CNTL_RING1__CI__VI regCP_INT_CNTL_RING1__CI__VI; -typedef union CP_INT_CNTL_RING1__SI regCP_INT_CNTL_RING1__SI; -typedef union CP_INT_CNTL_RING2__CI__VI regCP_INT_CNTL_RING2__CI__VI; -typedef union CP_INT_CNTL_RING2__SI regCP_INT_CNTL_RING2__SI; -typedef union CP_INT_CNTL__CI__VI regCP_INT_CNTL__CI__VI; -typedef union CP_INT_CNTL__SI regCP_INT_CNTL__SI; -typedef union CP_INT_STATUS_RING0__CI regCP_INT_STATUS_RING0__CI; -typedef union CP_INT_STATUS_RING0__VI regCP_INT_STATUS_RING0__VI; -typedef union CP_INT_STATUS_RING0__SI regCP_INT_STATUS_RING0__SI; -typedef union CP_INT_STATUS_RING1__CI__VI regCP_INT_STATUS_RING1__CI__VI; -typedef union CP_INT_STATUS_RING1__SI regCP_INT_STATUS_RING1__SI; -typedef union CP_INT_STATUS_RING2__CI__VI regCP_INT_STATUS_RING2__CI__VI; -typedef union CP_INT_STATUS_RING2__SI regCP_INT_STATUS_RING2__SI; -typedef union CP_INT_STATUS__CI__VI regCP_INT_STATUS__CI__VI; -typedef union CP_INT_STATUS__SI regCP_INT_STATUS__SI; -typedef union CP_INT_STAT_DEBUG__CI__VI regCP_INT_STAT_DEBUG__CI__VI; -typedef union CP_INT_STAT_DEBUG__SI regCP_INT_STAT_DEBUG__SI; -typedef union CP_IQ_WAIT_TIME1__CI__VI regCP_IQ_WAIT_TIME1__CI__VI; -typedef union CP_IQ_WAIT_TIME2__CI__VI regCP_IQ_WAIT_TIME2__CI__VI; -typedef union CP_MAX_CONTEXT__CI__VI regCP_MAX_CONTEXT__CI__VI; -typedef union CP_MC_PACK_DELAY_CNT__SI__CI regCP_MC_PACK_DELAY_CNT__SI__CI; -typedef union CP_MC_RD_RETURN_TAGS__SI regCP_MC_RD_RETURN_TAGS__SI; -typedef union CP_MC_TAG_CNTL__CI regCP_MC_TAG_CNTL__CI; -typedef union CP_MC_TAG_DATA__CI regCP_MC_TAG_DATA__CI; -typedef union CP_ME0_PIPE0_PRIORITY__CI__VI regCP_ME0_PIPE0_PRIORITY__CI__VI; -typedef union CP_ME0_PIPE0_VMID__CI__VI regCP_ME0_PIPE0_VMID__CI__VI; -typedef union CP_ME0_PIPE1_PRIORITY__CI__VI regCP_ME0_PIPE1_PRIORITY__CI__VI; -typedef union CP_ME0_PIPE1_VMID__CI__VI regCP_ME0_PIPE1_VMID__CI__VI; -typedef union CP_ME0_PIPE2_PRIORITY__CI__VI regCP_ME0_PIPE2_PRIORITY__CI__VI; -typedef union CP_ME0_PIPE_PRIORITY_CNTS__CI__VI regCP_ME0_PIPE_PRIORITY_CNTS__CI__VI; -typedef union CP_ME1_INT_STAT_DEBUG__CI__VI regCP_ME1_INT_STAT_DEBUG__CI__VI; -typedef union CP_ME1_PIPE0_INT_CNTL__CI__VI regCP_ME1_PIPE0_INT_CNTL__CI__VI; -typedef union CP_ME1_PIPE0_INT_STATUS__CI__VI regCP_ME1_PIPE0_INT_STATUS__CI__VI; -typedef union CP_ME1_PIPE0_PRIORITY__CI__VI regCP_ME1_PIPE0_PRIORITY__CI__VI; -typedef union CP_ME1_PIPE1_INT_CNTL__CI__VI regCP_ME1_PIPE1_INT_CNTL__CI__VI; -typedef union CP_ME1_PIPE1_INT_STATUS__CI__VI regCP_ME1_PIPE1_INT_STATUS__CI__VI; -typedef union CP_ME1_PIPE1_PRIORITY__CI__VI regCP_ME1_PIPE1_PRIORITY__CI__VI; -typedef union CP_ME1_PIPE2_INT_CNTL__CI__VI regCP_ME1_PIPE2_INT_CNTL__CI__VI; -typedef union CP_ME1_PIPE2_INT_STATUS__CI__VI regCP_ME1_PIPE2_INT_STATUS__CI__VI; -typedef union CP_ME1_PIPE2_PRIORITY__CI__VI regCP_ME1_PIPE2_PRIORITY__CI__VI; -typedef union CP_ME1_PIPE3_INT_CNTL__CI__VI regCP_ME1_PIPE3_INT_CNTL__CI__VI; -typedef union CP_ME1_PIPE3_INT_STATUS__CI__VI regCP_ME1_PIPE3_INT_STATUS__CI__VI; -typedef union CP_ME1_PIPE3_PRIORITY__CI__VI regCP_ME1_PIPE3_PRIORITY__CI__VI; -typedef union CP_ME1_PIPE_PRIORITY_CNTS__CI__VI regCP_ME1_PIPE_PRIORITY_CNTS__CI__VI; -typedef union CP_ME2_INT_STAT_DEBUG__CI__VI regCP_ME2_INT_STAT_DEBUG__CI__VI; -typedef union CP_ME2_PIPE0_INT_CNTL__CI__VI regCP_ME2_PIPE0_INT_CNTL__CI__VI; -typedef union CP_ME2_PIPE0_INT_STATUS__CI__VI regCP_ME2_PIPE0_INT_STATUS__CI__VI; -typedef union CP_ME2_PIPE0_PRIORITY__CI__VI regCP_ME2_PIPE0_PRIORITY__CI__VI; -typedef union CP_ME2_PIPE1_INT_CNTL__CI__VI regCP_ME2_PIPE1_INT_CNTL__CI__VI; -typedef union CP_ME2_PIPE1_INT_STATUS__CI__VI regCP_ME2_PIPE1_INT_STATUS__CI__VI; -typedef union CP_ME2_PIPE1_PRIORITY__CI__VI regCP_ME2_PIPE1_PRIORITY__CI__VI; -typedef union CP_ME2_PIPE2_INT_CNTL__CI__VI regCP_ME2_PIPE2_INT_CNTL__CI__VI; -typedef union CP_ME2_PIPE2_INT_STATUS__CI__VI regCP_ME2_PIPE2_INT_STATUS__CI__VI; -typedef union CP_ME2_PIPE2_PRIORITY__CI__VI regCP_ME2_PIPE2_PRIORITY__CI__VI; -typedef union CP_ME2_PIPE3_INT_CNTL__CI__VI regCP_ME2_PIPE3_INT_CNTL__CI__VI; -typedef union CP_ME2_PIPE3_INT_STATUS__CI__VI regCP_ME2_PIPE3_INT_STATUS__CI__VI; -typedef union CP_ME2_PIPE3_PRIORITY__CI__VI regCP_ME2_PIPE3_PRIORITY__CI__VI; -typedef union CP_ME2_PIPE_PRIORITY_CNTS__CI__VI regCP_ME2_PIPE_PRIORITY_CNTS__CI__VI; -typedef union CP_MEC1_F32_INTERRUPT__CI regCP_MEC1_F32_INTERRUPT__CI; -typedef union CP_MEC1_F32_INTERRUPT__VI regCP_MEC1_F32_INTERRUPT__VI; -typedef union CP_MEC1_INTR_ROUTINE_START__CI__VI regCP_MEC1_INTR_ROUTINE_START__CI__VI; -typedef union CP_MEC1_PRGRM_CNTR_START__CI__VI regCP_MEC1_PRGRM_CNTR_START__CI__VI; -typedef union CP_MEC2_F32_INTERRUPT__CI regCP_MEC2_F32_INTERRUPT__CI; -typedef union CP_MEC2_F32_INTERRUPT__VI regCP_MEC2_F32_INTERRUPT__VI; -typedef union CP_MEC2_INTR_ROUTINE_START__CI__VI regCP_MEC2_INTR_ROUTINE_START__CI__VI; -typedef union CP_MEC2_PRGRM_CNTR_START__CI__VI regCP_MEC2_PRGRM_CNTR_START__CI__VI; -typedef union CP_MEC_CNTL__CI__VI regCP_MEC_CNTL__CI__VI; -typedef union CP_MEC_ME1_HEADER_DUMP__CI__VI regCP_MEC_ME1_HEADER_DUMP__CI__VI; -typedef union CP_MEC_ME1_UCODE_ADDR__CI__VI regCP_MEC_ME1_UCODE_ADDR__CI__VI; -typedef union CP_MEC_ME1_UCODE_DATA__CI__VI regCP_MEC_ME1_UCODE_DATA__CI__VI; -typedef union CP_MEC_ME2_HEADER_DUMP__CI__VI regCP_MEC_ME2_HEADER_DUMP__CI__VI; -typedef union CP_MEC_ME2_UCODE_ADDR__CI__VI regCP_MEC_ME2_UCODE_ADDR__CI__VI; -typedef union CP_MEC_ME2_UCODE_DATA__CI__VI regCP_MEC_ME2_UCODE_DATA__CI__VI; -typedef union CP_MEM_SLP_CNTL regCP_MEM_SLP_CNTL; -typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; -typedef union CP_MEQ_STAT regCP_MEQ_STAT; -typedef union CP_MEQ_STQ_THRESHOLD__CI__VI regCP_MEQ_STQ_THRESHOLD__CI__VI; -typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; -typedef union CP_ME_ATOMIC_PREOP_HI__CI__VI regCP_ME_ATOMIC_PREOP_HI__CI__VI; -typedef union CP_ME_ATOMIC_PREOP_LO__CI__VI regCP_ME_ATOMIC_PREOP_LO__CI__VI; -typedef union CP_ME_CNTL regCP_ME_CNTL; -typedef union CP_ME_F32_INTERRUPT__CI__VI regCP_ME_F32_INTERRUPT__CI__VI; -typedef union CP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI regCP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI; -typedef union CP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI regCP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI; -typedef union CP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI regCP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI; -typedef union CP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI regCP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI; -typedef union CP_ME_HEADER_DUMP regCP_ME_HEADER_DUMP; -typedef union CP_ME_INTR_ROUTINE_START__CI__VI regCP_ME_INTR_ROUTINE_START__CI__VI; -typedef union CP_ME_MC_RADDR_HI regCP_ME_MC_RADDR_HI; -typedef union CP_ME_MC_RADDR_LO regCP_ME_MC_RADDR_LO; -typedef union CP_ME_MC_WADDR_HI regCP_ME_MC_WADDR_HI; -typedef union CP_ME_MC_WADDR_LO regCP_ME_MC_WADDR_LO; -typedef union CP_ME_MC_WDATA_HI regCP_ME_MC_WDATA_HI; -typedef union CP_ME_MC_WDATA_LO regCP_ME_MC_WDATA_LO; -typedef union CP_ME_PREEMPTION__SI__CI regCP_ME_PREEMPTION__SI__CI; -typedef union CP_ME_PREEMPTION__VI regCP_ME_PREEMPTION__VI; -typedef union CP_ME_PRGRM_CNTR_START__CI__VI regCP_ME_PRGRM_CNTR_START__CI__VI; -typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; -typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; -typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; -typedef union CP_MQD_BASE_ADDR_HI__CI__VI regCP_MQD_BASE_ADDR_HI__CI__VI; -typedef union CP_MQD_BASE_ADDR__CI__VI regCP_MQD_BASE_ADDR__CI__VI; -typedef union CP_MQD_CONTROL__CI regCP_MQD_CONTROL__CI; -typedef union CP_MQD_CONTROL__VI regCP_MQD_CONTROL__VI; -typedef union CP_NUM_PRIM_NEEDED_COUNT0_HI regCP_NUM_PRIM_NEEDED_COUNT0_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT0_LO regCP_NUM_PRIM_NEEDED_COUNT0_LO; -typedef union CP_NUM_PRIM_NEEDED_COUNT1_HI regCP_NUM_PRIM_NEEDED_COUNT1_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT1_LO regCP_NUM_PRIM_NEEDED_COUNT1_LO; -typedef union CP_NUM_PRIM_NEEDED_COUNT2_HI regCP_NUM_PRIM_NEEDED_COUNT2_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT2_LO regCP_NUM_PRIM_NEEDED_COUNT2_LO; -typedef union CP_NUM_PRIM_NEEDED_COUNT3_HI regCP_NUM_PRIM_NEEDED_COUNT3_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT3_LO regCP_NUM_PRIM_NEEDED_COUNT3_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT0_HI regCP_NUM_PRIM_WRITTEN_COUNT0_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT0_LO regCP_NUM_PRIM_WRITTEN_COUNT0_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT1_HI regCP_NUM_PRIM_WRITTEN_COUNT1_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT1_LO regCP_NUM_PRIM_WRITTEN_COUNT1_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT2_HI regCP_NUM_PRIM_WRITTEN_COUNT2_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT2_LO regCP_NUM_PRIM_WRITTEN_COUNT2_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT3_HI regCP_NUM_PRIM_WRITTEN_COUNT3_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT3_LO regCP_NUM_PRIM_WRITTEN_COUNT3_LO; -typedef union CP_PA_CINVOC_COUNT_HI regCP_PA_CINVOC_COUNT_HI; -typedef union CP_PA_CINVOC_COUNT_LO regCP_PA_CINVOC_COUNT_LO; -typedef union CP_PA_CPRIM_COUNT_HI regCP_PA_CPRIM_COUNT_HI; -typedef union CP_PA_CPRIM_COUNT_LO regCP_PA_CPRIM_COUNT_LO; -typedef union CP_PERFCOUNTER_HI__SI regCP_PERFCOUNTER_HI__SI; -typedef union CP_PERFCOUNTER_LO__SI regCP_PERFCOUNTER_LO__SI; -typedef union CP_PERFCOUNTER_SELECT__SI regCP_PERFCOUNTER_SELECT__SI; -typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; -typedef union CP_PERFMON_CNTX_CNTL regCP_PERFMON_CNTX_CNTL; -typedef union CP_PFP_ATOMIC_PREOP_HI__CI__VI regCP_PFP_ATOMIC_PREOP_HI__CI__VI; -typedef union CP_PFP_ATOMIC_PREOP_LO__CI__VI regCP_PFP_ATOMIC_PREOP_LO__CI__VI; -typedef union CP_PFP_F32_INTERRUPT__CI__VI regCP_PFP_F32_INTERRUPT__CI__VI; -typedef union CP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI regCP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI; -typedef union CP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI regCP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI; -typedef union CP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI regCP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI; -typedef union CP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI regCP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI; -typedef union CP_PFP_HEADER_DUMP regCP_PFP_HEADER_DUMP; -typedef union CP_PFP_IB_CONTROL regCP_PFP_IB_CONTROL; -typedef union CP_PFP_INTR_ROUTINE_START__CI__VI regCP_PFP_INTR_ROUTINE_START__CI__VI; -typedef union CP_PFP_LOAD_CONTROL__SI__CI regCP_PFP_LOAD_CONTROL__SI__CI; -typedef union CP_PFP_LOAD_CONTROL__VI regCP_PFP_LOAD_CONTROL__VI; -typedef union CP_PFP_PRGRM_CNTR_START__CI__VI regCP_PFP_PRGRM_CNTR_START__CI__VI; -typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; -typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; -typedef union CP_PIPEID__CI__VI regCP_PIPEID__CI__VI; -typedef union CP_PIPE_STATS_ADDR_HI__CI__VI regCP_PIPE_STATS_ADDR_HI__CI__VI; -typedef union CP_PIPE_STATS_ADDR_HI__SI regCP_PIPE_STATS_ADDR_HI__SI; -typedef union CP_PIPE_STATS_ADDR_LO regCP_PIPE_STATS_ADDR_LO; -typedef union CP_PQ_WPTR_POLL_CNTL1__CI__VI regCP_PQ_WPTR_POLL_CNTL1__CI__VI; -typedef union CP_PQ_WPTR_POLL_CNTL__CI__VI regCP_PQ_WPTR_POLL_CNTL__CI__VI; -typedef union CP_PRIV_VIOLATION_ADDR regCP_PRIV_VIOLATION_ADDR; -typedef union CP_PRT_LOD_STATS_CNTL0__CI__VI regCP_PRT_LOD_STATS_CNTL0__CI__VI; -typedef union CP_PRT_LOD_STATS_CNTL1__CI__VI regCP_PRT_LOD_STATS_CNTL1__CI__VI; -typedef union CP_PRT_LOD_STATS_CNTL2__CI__VI regCP_PRT_LOD_STATS_CNTL2__CI__VI; -typedef union CP_PWR_CNTL__CI regCP_PWR_CNTL__CI; -typedef union CP_PWR_CNTL__VI regCP_PWR_CNTL__VI; -typedef union CP_PWR_CNTL__SI regCP_PWR_CNTL__SI; -typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; -typedef union CP_RB0_BASE regCP_RB0_BASE; -typedef union CP_RB0_BASE_HI__CI__VI regCP_RB0_BASE_HI__CI__VI; -typedef union CP_RB0_CNTL__CI regCP_RB0_CNTL__CI; -typedef union CP_RB0_CNTL__VI regCP_RB0_CNTL__VI; -typedef union CP_RB0_CNTL__SI regCP_RB0_CNTL__SI; -typedef union CP_RB0_RPTR regCP_RB0_RPTR; -typedef union CP_RB0_RPTR_ADDR regCP_RB0_RPTR_ADDR; -typedef union CP_RB0_RPTR_ADDR_HI regCP_RB0_RPTR_ADDR_HI; -typedef union CP_RB0_WPTR regCP_RB0_WPTR; -typedef union CP_RB1_BASE regCP_RB1_BASE; -typedef union CP_RB1_BASE_HI__CI__VI regCP_RB1_BASE_HI__CI__VI; -typedef union CP_RB1_CNTL__SI__CI regCP_RB1_CNTL__SI__CI; -typedef union CP_RB1_CNTL__VI regCP_RB1_CNTL__VI; -typedef union CP_RB1_RPTR regCP_RB1_RPTR; -typedef union CP_RB1_RPTR_ADDR regCP_RB1_RPTR_ADDR; -typedef union CP_RB1_RPTR_ADDR_HI regCP_RB1_RPTR_ADDR_HI; -typedef union CP_RB1_WPTR regCP_RB1_WPTR; -typedef union CP_RB2_BASE regCP_RB2_BASE; -typedef union CP_RB2_CNTL__SI__CI regCP_RB2_CNTL__SI__CI; -typedef union CP_RB2_CNTL__VI regCP_RB2_CNTL__VI; -typedef union CP_RB2_RPTR regCP_RB2_RPTR; -typedef union CP_RB2_RPTR_ADDR regCP_RB2_RPTR_ADDR; -typedef union CP_RB2_RPTR_ADDR_HI regCP_RB2_RPTR_ADDR_HI; -typedef union CP_RB2_WPTR regCP_RB2_WPTR; -typedef union CP_RB_BASE regCP_RB_BASE; -typedef union CP_RB_CNTL__CI regCP_RB_CNTL__CI; -typedef union CP_RB_CNTL__VI regCP_RB_CNTL__VI; -typedef union CP_RB_CNTL__SI regCP_RB_CNTL__SI; -typedef union CP_RB_OFFSET regCP_RB_OFFSET; -typedef union CP_RB_RPTR regCP_RB_RPTR; -typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; -typedef union CP_RB_RPTR_ADDR_HI regCP_RB_RPTR_ADDR_HI; -typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; -typedef union CP_RB_VMID regCP_RB_VMID; -typedef union CP_RB_WPTR regCP_RB_WPTR; -typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; -typedef union CP_RB_WPTR_POLL_ADDR_HI__CI regCP_RB_WPTR_POLL_ADDR_HI__CI; -typedef union CP_RB_WPTR_POLL_ADDR_HI__VI regCP_RB_WPTR_POLL_ADDR_HI__VI; -typedef union CP_RB_WPTR_POLL_ADDR_HI__SI regCP_RB_WPTR_POLL_ADDR_HI__SI; -typedef union CP_RB_WPTR_POLL_ADDR_LO__CI regCP_RB_WPTR_POLL_ADDR_LO__CI; -typedef union CP_RB_WPTR_POLL_ADDR_LO__VI regCP_RB_WPTR_POLL_ADDR_LO__VI; -typedef union CP_RB_WPTR_POLL_ADDR_LO__SI regCP_RB_WPTR_POLL_ADDR_LO__SI; -typedef union CP_RB_WPTR_POLL_CNTL regCP_RB_WPTR_POLL_CNTL; -typedef union CP_RING0_PRIORITY regCP_RING0_PRIORITY; -typedef union CP_RING1_PRIORITY regCP_RING1_PRIORITY; -typedef union CP_RING2_PRIORITY regCP_RING2_PRIORITY; -typedef union CP_RINGID regCP_RINGID; -typedef union CP_RING_PRIORITY_CNTS regCP_RING_PRIORITY_CNTS; -typedef union CP_ROQ1_THRESHOLDS regCP_ROQ1_THRESHOLDS; -typedef union CP_ROQ2_AVAIL regCP_ROQ2_AVAIL; -typedef union CP_ROQ2_THRESHOLDS regCP_ROQ2_THRESHOLDS; -typedef union CP_ROQ_AVAIL regCP_ROQ_AVAIL; -typedef union CP_ROQ_IB1_STAT regCP_ROQ_IB1_STAT; -typedef union CP_ROQ_IB2_STAT regCP_ROQ_IB2_STAT; -typedef union CP_ROQ_RB_STAT regCP_ROQ_RB_STAT; -typedef union CP_ROQ_THRESHOLDS__CI__VI regCP_ROQ_THRESHOLDS__CI__VI; -typedef union CP_SCRATCH_DATA regCP_SCRATCH_DATA; -typedef union CP_SCRATCH_INDEX regCP_SCRATCH_INDEX; -typedef union CP_SC_PSINVOC_COUNT0_HI regCP_SC_PSINVOC_COUNT0_HI; -typedef union CP_SC_PSINVOC_COUNT0_LO regCP_SC_PSINVOC_COUNT0_LO; -typedef union CP_SC_PSINVOC_COUNT1_HI__CI__VI regCP_SC_PSINVOC_COUNT1_HI__CI__VI; -typedef union CP_SC_PSINVOC_COUNT1_HI__SI regCP_SC_PSINVOC_COUNT1_HI__SI; -typedef union CP_SC_PSINVOC_COUNT1_LO__CI__VI regCP_SC_PSINVOC_COUNT1_LO__CI__VI; -typedef union CP_SC_PSINVOC_COUNT1_LO__SI regCP_SC_PSINVOC_COUNT1_LO__SI; -typedef union CP_SEM_INCOMPLETE_TIMER_CNTL__SI regCP_SEM_INCOMPLETE_TIMER_CNTL__SI; -typedef union CP_SEM_WAIT_TIMER regCP_SEM_WAIT_TIMER; -typedef union CP_SIG_SEM_ADDR_HI regCP_SIG_SEM_ADDR_HI; -typedef union CP_SIG_SEM_ADDR_LO regCP_SIG_SEM_ADDR_LO; -typedef union CP_STALLED_STAT1__CI regCP_STALLED_STAT1__CI; -typedef union CP_STALLED_STAT1__VI regCP_STALLED_STAT1__VI; -typedef union CP_STALLED_STAT1__SI regCP_STALLED_STAT1__SI; -typedef union CP_STALLED_STAT2 regCP_STALLED_STAT2; -typedef union CP_STALLED_STAT3 regCP_STALLED_STAT3; -typedef union CP_STAT__CI regCP_STAT__CI; -typedef union CP_STAT__VI regCP_STAT__VI; -typedef union CP_STAT__SI regCP_STAT__SI; -typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; -typedef union CP_STQ_STAT regCP_STQ_STAT; -typedef union CP_STQ_THRESHOLDS regCP_STQ_THRESHOLDS; -typedef union CP_STQ_WR_STAT__CI__VI regCP_STQ_WR_STAT__CI__VI; -typedef union CP_STREAM_OUT_ADDR_HI__CI__VI regCP_STREAM_OUT_ADDR_HI__CI__VI; -typedef union CP_STREAM_OUT_ADDR_HI__SI regCP_STREAM_OUT_ADDR_HI__SI; -typedef union CP_STREAM_OUT_ADDR_LO regCP_STREAM_OUT_ADDR_LO; -typedef union CP_STRMOUT_CNTL regCP_STRMOUT_CNTL; -typedef union CP_ST_BASE_HI regCP_ST_BASE_HI; -typedef union CP_ST_BASE_LO regCP_ST_BASE_LO; -typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; -typedef union CP_VGT_CSINVOC_COUNT_HI regCP_VGT_CSINVOC_COUNT_HI; -typedef union CP_VGT_CSINVOC_COUNT_LO regCP_VGT_CSINVOC_COUNT_LO; -typedef union CP_VGT_DSINVOC_COUNT_HI regCP_VGT_DSINVOC_COUNT_HI; -typedef union CP_VGT_DSINVOC_COUNT_LO regCP_VGT_DSINVOC_COUNT_LO; -typedef union CP_VGT_GSINVOC_COUNT_HI regCP_VGT_GSINVOC_COUNT_HI; -typedef union CP_VGT_GSINVOC_COUNT_LO regCP_VGT_GSINVOC_COUNT_LO; -typedef union CP_VGT_GSPRIM_COUNT_HI regCP_VGT_GSPRIM_COUNT_HI; -typedef union CP_VGT_GSPRIM_COUNT_LO regCP_VGT_GSPRIM_COUNT_LO; -typedef union CP_VGT_HSINVOC_COUNT_HI regCP_VGT_HSINVOC_COUNT_HI; -typedef union CP_VGT_HSINVOC_COUNT_LO regCP_VGT_HSINVOC_COUNT_LO; -typedef union CP_VGT_IAPRIM_COUNT_HI regCP_VGT_IAPRIM_COUNT_HI; -typedef union CP_VGT_IAPRIM_COUNT_LO regCP_VGT_IAPRIM_COUNT_LO; -typedef union CP_VGT_IAVERT_COUNT_HI regCP_VGT_IAVERT_COUNT_HI; -typedef union CP_VGT_IAVERT_COUNT_LO regCP_VGT_IAVERT_COUNT_LO; -typedef union CP_VGT_VSINVOC_COUNT_HI regCP_VGT_VSINVOC_COUNT_HI; -typedef union CP_VGT_VSINVOC_COUNT_LO regCP_VGT_VSINVOC_COUNT_LO; -typedef union CP_VMID regCP_VMID; -typedef union CP_VMID_PREEMPT__CI regCP_VMID_PREEMPT__CI; -typedef union CP_VMID_PREEMPT__VI regCP_VMID_PREEMPT__VI; -typedef union CP_VMID_RESET__CI__VI regCP_VMID_RESET__CI__VI; -typedef union CP_WAIT_REG_MEM_TIMEOUT regCP_WAIT_REG_MEM_TIMEOUT; -typedef union CP_WAIT_SEM_ADDR_HI regCP_WAIT_SEM_ADDR_HI; -typedef union CP_WAIT_SEM_ADDR_LO regCP_WAIT_SEM_ADDR_LO; -typedef union CP_WAIT_SEM_STATUS__CI regCP_WAIT_SEM_STATUS__CI; -typedef union CRT00__SI regCRT00__SI; -typedef union CRT01__SI regCRT01__SI; -typedef union CRT02__SI regCRT02__SI; -typedef union CRT03__SI regCRT03__SI; -typedef union CRT04__SI regCRT04__SI; -typedef union CRT05__SI regCRT05__SI; -typedef union CRT06__SI regCRT06__SI; -typedef union CRT07__SI regCRT07__SI; -typedef union CRT08__SI regCRT08__SI; -typedef union CRT09__SI regCRT09__SI; -typedef union CRT0A__SI regCRT0A__SI; -typedef union CRT0B__SI regCRT0B__SI; -typedef union CRT0C__SI regCRT0C__SI; -typedef union CRT0D__SI regCRT0D__SI; -typedef union CRT0E__SI regCRT0E__SI; -typedef union CRT0F__SI regCRT0F__SI; -typedef union CRT10__SI regCRT10__SI; -typedef union CRT11__SI regCRT11__SI; -typedef union CRT12__SI regCRT12__SI; -typedef union CRT13__SI regCRT13__SI; -typedef union CRT14__SI regCRT14__SI; -typedef union CRT15__SI regCRT15__SI; -typedef union CRT16__SI regCRT16__SI; -typedef union CRT17__SI regCRT17__SI; -typedef union CRT18__SI regCRT18__SI; -typedef union CRT1E__SI regCRT1E__SI; -typedef union CRT1F__SI regCRT1F__SI; -typedef union CRT22__SI regCRT22__SI; -typedef union CRTC0_PIXEL_RATE_CNTL__SI regCRTC0_PIXEL_RATE_CNTL__SI; -typedef union CRTC1_PIXEL_RATE_CNTL__SI regCRTC1_PIXEL_RATE_CNTL__SI; -typedef union CRTC2_PIXEL_RATE_CNTL__SI regCRTC2_PIXEL_RATE_CNTL__SI; -typedef union CRTC3_PIXEL_RATE_CNTL__SI regCRTC3_PIXEL_RATE_CNTL__SI; -typedef union CRTC4_PIXEL_RATE_CNTL__SI regCRTC4_PIXEL_RATE_CNTL__SI; -typedef union CRTC5_PIXEL_RATE_CNTL__SI regCRTC5_PIXEL_RATE_CNTL__SI; -typedef union CRTC8_DATA__SI regCRTC8_DATA__SI; -typedef union CRTC8_IDX__SI regCRTC8_IDX__SI; -typedef union CRTC_ALLOW_STOP_OFF_V_CNT__SI regCRTC_ALLOW_STOP_OFF_V_CNT__SI; -typedef union CRTC_BLACK_COLOR__SI regCRTC_BLACK_COLOR__SI; -typedef union CRTC_BLANK_CONTROL__SI regCRTC_BLANK_CONTROL__SI; -typedef union CRTC_BLANK_DATA_COLOR__SI regCRTC_BLANK_DATA_COLOR__SI; -typedef union CRTC_CONTROL__SI regCRTC_CONTROL__SI; -typedef union CRTC_COUNT_CONTROL__SI regCRTC_COUNT_CONTROL__SI; -typedef union CRTC_COUNT_RESET__SI regCRTC_COUNT_RESET__SI; -typedef union CRTC_DEBUG_01__SI regCRTC_DEBUG_01__SI; -typedef union CRTC_DEBUG_02__SI regCRTC_DEBUG_02__SI; -typedef union CRTC_DEBUG_03__SI regCRTC_DEBUG_03__SI; -typedef union CRTC_DEBUG_04__SI regCRTC_DEBUG_04__SI; -typedef union CRTC_DEBUG_05__SI regCRTC_DEBUG_05__SI; -typedef union CRTC_DEBUG_06__SI regCRTC_DEBUG_06__SI; -typedef union CRTC_DEBUG_07__SI regCRTC_DEBUG_07__SI; -typedef union CRTC_DEBUG_08__SI regCRTC_DEBUG_08__SI; -typedef union CRTC_DEBUG_BITS__SI regCRTC_DEBUG_BITS__SI; -typedef union CRTC_DEBUG__SI regCRTC_DEBUG__SI; -typedef union CRTC_DOUBLE_BUFFER_CONTROL__SI regCRTC_DOUBLE_BUFFER_CONTROL__SI; -typedef union CRTC_DOUT_INTERFACE_01__SI regCRTC_DOUT_INTERFACE_01__SI; -typedef union CRTC_DOUT_INTERFACE_02__SI regCRTC_DOUT_INTERFACE_02__SI; -typedef union CRTC_DTMTEST_CNTL__SI regCRTC_DTMTEST_CNTL__SI; -typedef union CRTC_DTMTEST_STATUS_POSITION__SI regCRTC_DTMTEST_STATUS_POSITION__SI; -typedef union CRTC_FLOW_CONTROL__SI regCRTC_FLOW_CONTROL__SI; -typedef union CRTC_FORCE_COUNT_NOW_CNTL__SI regCRTC_FORCE_COUNT_NOW_CNTL__SI; -typedef union CRTC_H_BLANK_START_END__SI regCRTC_H_BLANK_START_END__SI; -typedef union CRTC_H_SYNC_A_CNTL__SI regCRTC_H_SYNC_A_CNTL__SI; -typedef union CRTC_H_SYNC_A__SI regCRTC_H_SYNC_A__SI; -typedef union CRTC_H_SYNC_B_CNTL__SI regCRTC_H_SYNC_B_CNTL__SI; -typedef union CRTC_H_SYNC_B__SI regCRTC_H_SYNC_B__SI; -typedef union CRTC_H_TOTAL__SI regCRTC_H_TOTAL__SI; -typedef union CRTC_INTERLACE_CONTROL__SI regCRTC_INTERLACE_CONTROL__SI; -typedef union CRTC_INTERLACE_STATUS__SI regCRTC_INTERLACE_STATUS__SI; -typedef union CRTC_INTERRUPT_CONTROL__SI regCRTC_INTERRUPT_CONTROL__SI; -typedef union CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI regCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI; -typedef union CRTC_MASTER_EN__SI regCRTC_MASTER_EN__SI; -typedef union CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI regCRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI; -typedef union CRTC_MVP_INBAND_CNTL_INSERT__SI regCRTC_MVP_INBAND_CNTL_INSERT__SI; -typedef union CRTC_MVP_STATUS__SI regCRTC_MVP_STATUS__SI; -typedef union CRTC_NOM_VERT_POSITION__SI regCRTC_NOM_VERT_POSITION__SI; -typedef union CRTC_OVERSCAN_COLOR__SI regCRTC_OVERSCAN_COLOR__SI; -typedef union CRTC_PIXCLK_DTO_MODULO__SI regCRTC_PIXCLK_DTO_MODULO__SI; -typedef union CRTC_PIXCLK_DTO_PHASE__SI regCRTC_PIXCLK_DTO_PHASE__SI; -typedef union CRTC_PIXEL_DATA_READBACK__SI regCRTC_PIXEL_DATA_READBACK__SI; -typedef union CRTC_SCL_INTERFACE__SI regCRTC_SCL_INTERFACE__SI; -typedef union CRTC_SNAPSHOT_CONTROL__SI regCRTC_SNAPSHOT_CONTROL__SI; -typedef union CRTC_SNAPSHOT_FRAME__SI regCRTC_SNAPSHOT_FRAME__SI; -typedef union CRTC_SNAPSHOT_POSITION__SI regCRTC_SNAPSHOT_POSITION__SI; -typedef union CRTC_SNAPSHOT_STATUS__SI regCRTC_SNAPSHOT_STATUS__SI; -typedef union CRTC_START_LINE_CONTROL__SI regCRTC_START_LINE_CONTROL__SI; -typedef union CRTC_STATUS_FRAME_COUNT__SI regCRTC_STATUS_FRAME_COUNT__SI; -typedef union CRTC_STATUS_HV_COUNT__SI regCRTC_STATUS_HV_COUNT__SI; -typedef union CRTC_STATUS_POSITION__SI regCRTC_STATUS_POSITION__SI; -typedef union CRTC_STATUS_VF_COUNT__SI regCRTC_STATUS_VF_COUNT__SI; -typedef union CRTC_STATUS__SI regCRTC_STATUS__SI; -typedef union CRTC_STEREO_CONTROL__SI regCRTC_STEREO_CONTROL__SI; -typedef union CRTC_STEREO_FORCE_NEXT_EYE__SI regCRTC_STEREO_FORCE_NEXT_EYE__SI; -typedef union CRTC_STEREO_STATUS__SI regCRTC_STEREO_STATUS__SI; -typedef union CRTC_TEST_DEBUG_DATA__SI regCRTC_TEST_DEBUG_DATA__SI; -typedef union CRTC_TEST_DEBUG_INDEX__SI regCRTC_TEST_DEBUG_INDEX__SI; -typedef union CRTC_TEST_PATTERN_COLOR__SI regCRTC_TEST_PATTERN_COLOR__SI; -typedef union CRTC_TEST_PATTERN_CONTROL__SI regCRTC_TEST_PATTERN_CONTROL__SI; -typedef union CRTC_TEST_PATTERN_PARAMETERS__SI regCRTC_TEST_PATTERN_PARAMETERS__SI; -typedef union CRTC_TRIGA_CNTL__SI regCRTC_TRIGA_CNTL__SI; -typedef union CRTC_TRIGA_MANUAL_TRIG__SI regCRTC_TRIGA_MANUAL_TRIG__SI; -typedef union CRTC_TRIGB_CNTL__SI regCRTC_TRIGB_CNTL__SI; -typedef union CRTC_TRIGB_MANUAL_TRIG__SI regCRTC_TRIGB_MANUAL_TRIG__SI; -typedef union CRTC_UPDATE_LOCK__SI regCRTC_UPDATE_LOCK__SI; -typedef union CRTC_VBI_END__SI regCRTC_VBI_END__SI; -typedef union CRTC_VERT_SYNC_CONTROL__SI regCRTC_VERT_SYNC_CONTROL__SI; -typedef union CRTC_VGA_INTERFACE__SI regCRTC_VGA_INTERFACE__SI; -typedef union CRTC_VGA_PARAMETER_CAPTURE_MODE__SI regCRTC_VGA_PARAMETER_CAPTURE_MODE__SI; -typedef union CRTC_VSYNC_NOM_INT_STATUS__SI regCRTC_VSYNC_NOM_INT_STATUS__SI; -typedef union CRTC_V_BLANK_START_END__SI regCRTC_V_BLANK_START_END__SI; -typedef union CRTC_V_SYNC_A_CNTL__SI regCRTC_V_SYNC_A_CNTL__SI; -typedef union CRTC_V_SYNC_A__SI regCRTC_V_SYNC_A__SI; -typedef union CRTC_V_SYNC_B_CNTL__SI regCRTC_V_SYNC_B_CNTL__SI; -typedef union CRTC_V_SYNC_B__SI regCRTC_V_SYNC_B__SI; -typedef union CRTC_V_TOTAL_CONTROL__SI regCRTC_V_TOTAL_CONTROL__SI; -typedef union CRTC_V_TOTAL_INT_STATUS__SI regCRTC_V_TOTAL_INT_STATUS__SI; -typedef union CRTC_V_TOTAL_MAX__SI regCRTC_V_TOTAL_MAX__SI; -typedef union CRTC_V_TOTAL_MIN__SI regCRTC_V_TOTAL_MIN__SI; -typedef union CRTC_V_TOTAL__SI regCRTC_V_TOTAL__SI; -typedef union CRTC_V_UPDATE_INT_STATUS__SI regCRTC_V_UPDATE_INT_STATUS__SI; -typedef union CSPRIV_CONNECT__CI__VI regCSPRIV_CONNECT__CI__VI; -typedef union CSPRIV_THREAD_TRACE_EVENT__CI__VI regCSPRIV_THREAD_TRACE_EVENT__CI__VI; -typedef union CSPRIV_THREAD_TRACE_TG0__CI__VI regCSPRIV_THREAD_TRACE_TG0__CI__VI; -typedef union CSPRIV_THREAD_TRACE_TG1__CI__VI regCSPRIV_THREAD_TRACE_TG1__CI__VI; -typedef union CSPRIV_THREAD_TRACE_TG2__CI__VI regCSPRIV_THREAD_TRACE_TG2__CI__VI; -typedef union CSPRIV_THREAD_TRACE_TG3__CI__VI regCSPRIV_THREAD_TRACE_TG3__CI__VI; -typedef union CS_COPY_STATE regCS_COPY_STATE; -typedef union CURRENT_PG_STATUS__CI__VI regCURRENT_PG_STATUS__CI__VI; -typedef union CUR_COLOR1__SI regCUR_COLOR1__SI; -typedef union CUR_COLOR2__SI regCUR_COLOR2__SI; -typedef union CUR_CONTROL__SI regCUR_CONTROL__SI; -typedef union CUR_HOT_SPOT__SI regCUR_HOT_SPOT__SI; -typedef union CUR_POSITION__SI regCUR_POSITION__SI; -typedef union CUR_SIZE__SI regCUR_SIZE__SI; -typedef union CUR_SURFACE_ADDRESS_HIGH__SI regCUR_SURFACE_ADDRESS_HIGH__SI; -typedef union CUR_SURFACE_ADDRESS__SI regCUR_SURFACE_ADDRESS__SI; -typedef union CUR_UPDATE__SI regCUR_UPDATE__SI; -typedef union D1VGA_CONTROL__SI regD1VGA_CONTROL__SI; -typedef union D1_PROTECTION__SI regD1_PROTECTION__SI; -typedef union D2VGA_CONTROL__SI regD2VGA_CONTROL__SI; -typedef union D2_PROTECTION__SI regD2_PROTECTION__SI; -typedef union D3VGA_CONTROL__SI regD3VGA_CONTROL__SI; -typedef union D3_PROTECTION__SI regD3_PROTECTION__SI; -typedef union D4VGA_CONTROL__SI regD4VGA_CONTROL__SI; -typedef union D4_PROTECTION__SI regD4_PROTECTION__SI; -typedef union D5VGA_CONTROL__SI regD5VGA_CONTROL__SI; -typedef union D5_PROTECTION__SI regD5_PROTECTION__SI; -typedef union D6VGA_CONTROL__SI regD6VGA_CONTROL__SI; -typedef union D6_PROTECTION__SI regD6_PROTECTION__SI; -typedef union DAC_AUTODETECT_CONTROL2__SI regDAC_AUTODETECT_CONTROL2__SI; -typedef union DAC_AUTODETECT_CONTROL3__SI regDAC_AUTODETECT_CONTROL3__SI; -typedef union DAC_AUTODETECT_CONTROL__SI regDAC_AUTODETECT_CONTROL__SI; -typedef union DAC_AUTODETECT_INT_CONTROL__SI regDAC_AUTODETECT_INT_CONTROL__SI; -typedef union DAC_AUTODETECT_STATUS__SI regDAC_AUTODETECT_STATUS__SI; -typedef union DAC_AUTO_CALIB_CONTROL__SI regDAC_AUTO_CALIB_CONTROL__SI; -typedef union DAC_BGADJ_CONTROL__SI regDAC_BGADJ_CONTROL__SI; -typedef union DAC_COMPARATOR_ENABLE__SI regDAC_COMPARATOR_ENABLE__SI; -typedef union DAC_COMPARATOR_OUTPUT__SI regDAC_COMPARATOR_OUTPUT__SI; -typedef union DAC_CONTROL__SI regDAC_CONTROL__SI; -typedef union DAC_CRC_CONTROL__SI regDAC_CRC_CONTROL__SI; -typedef union DAC_CRC_EN__SI regDAC_CRC_EN__SI; -typedef union DAC_CRC_SIG_CONTROL_MASK__SI regDAC_CRC_SIG_CONTROL_MASK__SI; -typedef union DAC_CRC_SIG_CONTROL__SI regDAC_CRC_SIG_CONTROL__SI; -typedef union DAC_CRC_SIG_RGB_MASK__SI regDAC_CRC_SIG_RGB_MASK__SI; -typedef union DAC_CRC_SIG_RGB__SI regDAC_CRC_SIG_RGB__SI; -typedef union DAC_DATA__SI regDAC_DATA__SI; -typedef union DAC_DEBUG1__SI regDAC_DEBUG1__SI; -typedef union DAC_DEBUG2__SI regDAC_DEBUG2__SI; -typedef union DAC_DEBUG3__SI regDAC_DEBUG3__SI; -typedef union DAC_DFT_CONFIG__SI regDAC_DFT_CONFIG__SI; -typedef union DAC_ENABLE__SI regDAC_ENABLE__SI; -typedef union DAC_FORCE_DATA__SI regDAC_FORCE_DATA__SI; -typedef union DAC_FORCE_OUTPUT_CNTL__SI regDAC_FORCE_OUTPUT_CNTL__SI; -typedef union DAC_MACRO_CNTL__SI regDAC_MACRO_CNTL__SI; -typedef union DAC_MASK__SI regDAC_MASK__SI; -typedef union DAC_POWERDOWN__SI regDAC_POWERDOWN__SI; -typedef union DAC_PWR_CNTL__SI regDAC_PWR_CNTL__SI; -typedef union DAC_R_INDEX__SI regDAC_R_INDEX__SI; -typedef union DAC_SOURCE_SELECT__SI regDAC_SOURCE_SELECT__SI; -typedef union DAC_STEREOSYNC_SELECT__SI regDAC_STEREOSYNC_SELECT__SI; -typedef union DAC_SYNC_TRISTATE_CONTROL__SI regDAC_SYNC_TRISTATE_CONTROL__SI; -typedef union DAC_TEST_ENABLE__SI regDAC_TEST_ENABLE__SI; -typedef union DAC_W_INDEX__SI regDAC_W_INDEX__SI; -typedef union DATA_FORMAT__SI regDATA_FORMAT__SI; -typedef union DBG_BUS_OUT1 regDBG_BUS_OUT1; -typedef union DBG_BYPASS_SRBM_ACCESS__CI regDBG_BYPASS_SRBM_ACCESS__CI; -typedef union DBG_CHAIN_CONTROL regDBG_CHAIN_CONTROL; -typedef union DBG_FBC_COMP_DEBUG__SI regDBG_FBC_COMP_DEBUG__SI; -typedef union DBG_FBC_CTL23__SI regDBG_FBC_CTL23__SI; -typedef union DBG_FBC_DECOMP_CTL_DEBUG__SI regDBG_FBC_DECOMP_CTL_DEBUG__SI; -typedef union DBW_CHROMA_BOT_ADDR__SI regDBW_CHROMA_BOT_ADDR__SI; -typedef union DBW_CHROMA_TOP_ADDR__SI regDBW_CHROMA_TOP_ADDR__SI; -typedef union DBW_LUMA_BOT_ADDR__SI regDBW_LUMA_BOT_ADDR__SI; -typedef union DBW_LUMA_TOP_ADDR__SI regDBW_LUMA_TOP_ADDR__SI; -typedef union DB_ALPHA_TO_MASK regDB_ALPHA_TO_MASK; -typedef union DB_BUF_SIZE__SI regDB_BUF_SIZE__SI; -typedef union DB_CF_DAT__SI regDB_CF_DAT__SI; -typedef union DB_CGTT_CLK_CTRL_0 regDB_CGTT_CLK_CTRL_0; -typedef union DB_COUNT_CONTROL regDB_COUNT_CONTROL; -typedef union DB_CREDIT_LIMIT regDB_CREDIT_LIMIT; -typedef union DB_CTL__SI regDB_CTL__SI; -typedef union DB_DBG_CTL__SI regDB_DBG_CTL__SI; -typedef union DB_DBG_STAT__SI regDB_DBG_STAT__SI; -typedef union DB_DEBUG regDB_DEBUG; -typedef union DB_DEBUG2__CI__VI regDB_DEBUG2__CI__VI; -typedef union DB_DEBUG2__SI regDB_DEBUG2__SI; -typedef union DB_DEBUG3__CI regDB_DEBUG3__CI; -typedef union DB_DEBUG3__VI regDB_DEBUG3__VI; -typedef union DB_DEBUG3__SI regDB_DEBUG3__SI; -typedef union DB_DEBUG4__CI regDB_DEBUG4__CI; -typedef union DB_DEBUG4__VI regDB_DEBUG4__VI; -typedef union DB_DEBUG4__SI regDB_DEBUG4__SI; -typedef union DB_DEBUG_INT_STAT__SI regDB_DEBUG_INT_STAT__SI; -typedef union DB_DEPTH_BOUNDS_MAX regDB_DEPTH_BOUNDS_MAX; -typedef union DB_DEPTH_BOUNDS_MIN regDB_DEPTH_BOUNDS_MIN; -typedef union DB_DEPTH_CLEAR regDB_DEPTH_CLEAR; -typedef union DB_DEPTH_CONTROL regDB_DEPTH_CONTROL; -typedef union DB_DEPTH_INFO regDB_DEPTH_INFO; -typedef union DB_DEPTH_SIZE regDB_DEPTH_SIZE; -typedef union DB_DEPTH_SLICE regDB_DEPTH_SLICE; -typedef union DB_DEPTH_VIEW regDB_DEPTH_VIEW; -typedef union DB_EQAA regDB_EQAA; -typedef union DB_ERRCONCEAL_CONTROL__SI regDB_ERRCONCEAL_CONTROL__SI; -typedef union DB_ERRDET_CONTROL__SI regDB_ERRDET_CONTROL__SI; -typedef union DB_ERRDET__SI regDB_ERRDET__SI; -typedef union DB_FIFO_DEPTH1 regDB_FIFO_DEPTH1; -typedef union DB_FIFO_DEPTH2 regDB_FIFO_DEPTH2; -typedef union DB_FREE_CACHELINES regDB_FREE_CACHELINES; -typedef union DB_GREY_LEVELS__SI regDB_GREY_LEVELS__SI; -typedef union DB_HTILE_DATA_BASE regDB_HTILE_DATA_BASE; -typedef union DB_HTILE_SURFACE regDB_HTILE_SURFACE; -typedef union DB_HW_DEBUG__SI regDB_HW_DEBUG__SI; -typedef union DB_INTRA_HOR_ADR__SI regDB_INTRA_HOR_ADR__SI; -typedef union DB_INT_EN__SI regDB_INT_EN__SI; -typedef union DB_INT_STAT__SI regDB_INT_STAT__SI; -typedef union DB_LMA_ADR__SI regDB_LMA_ADR__SI; -typedef union DB_LMA_CTL__SI regDB_LMA_CTL__SI; -typedef union DB_LMA_DAT__SI regDB_LMA_DAT__SI; -typedef union DB_LUMA_ADR__SI regDB_LUMA_ADR__SI; -typedef union DB_OCCLUSION_COUNT0_HI__CI__VI regDB_OCCLUSION_COUNT0_HI__CI__VI; -typedef union DB_OCCLUSION_COUNT0_LOW__CI__VI regDB_OCCLUSION_COUNT0_LOW__CI__VI; -typedef union DB_OCCLUSION_COUNT1_HI__CI__VI regDB_OCCLUSION_COUNT1_HI__CI__VI; -typedef union DB_OCCLUSION_COUNT1_LOW__CI__VI regDB_OCCLUSION_COUNT1_LOW__CI__VI; -typedef union DB_OCCLUSION_COUNT2_HI__CI__VI regDB_OCCLUSION_COUNT2_HI__CI__VI; -typedef union DB_OCCLUSION_COUNT2_LOW__CI__VI regDB_OCCLUSION_COUNT2_LOW__CI__VI; -typedef union DB_OCCLUSION_COUNT3_HI__CI__VI regDB_OCCLUSION_COUNT3_HI__CI__VI; -typedef union DB_OCCLUSION_COUNT3_LOW__CI__VI regDB_OCCLUSION_COUNT3_LOW__CI__VI; -typedef union DB_PERFCOUNTER0_HI regDB_PERFCOUNTER0_HI; -typedef union DB_PERFCOUNTER0_LO regDB_PERFCOUNTER0_LO; -typedef union DB_PERFCOUNTER0_SELECT regDB_PERFCOUNTER0_SELECT; -typedef union DB_PERFCOUNTER0_SELECT1__CI__VI regDB_PERFCOUNTER0_SELECT1__CI__VI; -typedef union DB_PERFCOUNTER1_HI regDB_PERFCOUNTER1_HI; -typedef union DB_PERFCOUNTER1_LO regDB_PERFCOUNTER1_LO; -typedef union DB_PERFCOUNTER1_SELECT regDB_PERFCOUNTER1_SELECT; -typedef union DB_PERFCOUNTER1_SELECT1__CI__VI regDB_PERFCOUNTER1_SELECT1__CI__VI; -typedef union DB_PERFCOUNTER2_HI regDB_PERFCOUNTER2_HI; -typedef union DB_PERFCOUNTER2_LO regDB_PERFCOUNTER2_LO; -typedef union DB_PERFCOUNTER2_SELECT regDB_PERFCOUNTER2_SELECT; -typedef union DB_PERFCOUNTER3_HI regDB_PERFCOUNTER3_HI; -typedef union DB_PERFCOUNTER3_LO regDB_PERFCOUNTER3_LO; -typedef union DB_PERFCOUNTER3_SELECT regDB_PERFCOUNTER3_SELECT; -typedef union DB_PRELOAD_CONTROL regDB_PRELOAD_CONTROL; -typedef union DB_READ_DEBUG_0 regDB_READ_DEBUG_0; -typedef union DB_READ_DEBUG_1 regDB_READ_DEBUG_1; -typedef union DB_READ_DEBUG_2 regDB_READ_DEBUG_2; -typedef union DB_READ_DEBUG_3 regDB_READ_DEBUG_3; -typedef union DB_READ_DEBUG_4 regDB_READ_DEBUG_4; -typedef union DB_READ_DEBUG_5 regDB_READ_DEBUG_5; -typedef union DB_READ_DEBUG_6 regDB_READ_DEBUG_6; -typedef union DB_READ_DEBUG_7 regDB_READ_DEBUG_7; -typedef union DB_READ_DEBUG_8 regDB_READ_DEBUG_8; -typedef union DB_READ_DEBUG_9 regDB_READ_DEBUG_9; -typedef union DB_READ_DEBUG_A regDB_READ_DEBUG_A; -typedef union DB_READ_DEBUG_B regDB_READ_DEBUG_B; -typedef union DB_READ_DEBUG_C regDB_READ_DEBUG_C; -typedef union DB_READ_DEBUG_D regDB_READ_DEBUG_D; -typedef union DB_READ_DEBUG_E regDB_READ_DEBUG_E; -typedef union DB_READ_DEBUG_F regDB_READ_DEBUG_F; -typedef union DB_RENDER_CONTROL regDB_RENDER_CONTROL; -typedef union DB_RENDER_OVERRIDE regDB_RENDER_OVERRIDE; -typedef union DB_RENDER_OVERRIDE2 regDB_RENDER_OVERRIDE2; -typedef union DB_RING_CONTROL__CI__VI regDB_RING_CONTROL__CI__VI; -typedef union DB_SHADER_CONTROL regDB_SHADER_CONTROL; -typedef union DB_SLICE_INFO__SI regDB_SLICE_INFO__SI; -typedef union DB_SPS_INFO__SI regDB_SPS_INFO__SI; -typedef union DB_SRAM_RM_CTL__SI regDB_SRAM_RM_CTL__SI; -typedef union DB_SRESULTS_COMPARE_STATE0 regDB_SRESULTS_COMPARE_STATE0; -typedef union DB_SRESULTS_COMPARE_STATE1 regDB_SRESULTS_COMPARE_STATE1; -typedef union DB_STAT__SI regDB_STAT__SI; -typedef union DB_STENCILREFMASK regDB_STENCILREFMASK; -typedef union DB_STENCILREFMASK_BF regDB_STENCILREFMASK_BF; -typedef union DB_STENCIL_CLEAR regDB_STENCIL_CLEAR; -typedef union DB_STENCIL_CONTROL regDB_STENCIL_CONTROL; -typedef union DB_STENCIL_INFO regDB_STENCIL_INFO; -typedef union DB_STENCIL_READ_BASE regDB_STENCIL_READ_BASE; -typedef union DB_STENCIL_WRITE_BASE regDB_STENCIL_WRITE_BASE; -typedef union DB_SUBTILE_CONTROL regDB_SUBTILE_CONTROL; -typedef union DB_TOP_Y_PIC__SI regDB_TOP_Y_PIC__SI; -typedef union DB_UPROC_STAT__SI regDB_UPROC_STAT__SI; -typedef union DB_VC1_SP_CONTEXT__SI regDB_VC1_SP_CONTEXT__SI; -typedef union DB_WATERMARKS regDB_WATERMARKS; -typedef union DB_ZPASS_COUNT_HI regDB_ZPASS_COUNT_HI; -typedef union DB_ZPASS_COUNT_LOW regDB_ZPASS_COUNT_LOW; -typedef union DB_Z_INFO regDB_Z_INFO; -typedef union DB_Z_READ_BASE regDB_Z_READ_BASE; -typedef union DB_Z_WRITE_BASE regDB_Z_WRITE_BASE; -typedef union DCCG_AUDIO_DTO0_CNTL__SI regDCCG_AUDIO_DTO0_CNTL__SI; -typedef union DCCG_AUDIO_DTO0_LOAD__SI regDCCG_AUDIO_DTO0_LOAD__SI; -typedef union DCCG_AUDIO_DTO0_MODULE__SI regDCCG_AUDIO_DTO0_MODULE__SI; -typedef union DCCG_AUDIO_DTO0_PHASE__SI regDCCG_AUDIO_DTO0_PHASE__SI; -typedef union DCCG_AUDIO_DTO_SELECT__SI regDCCG_AUDIO_DTO_SELECT__SI; -typedef union DCCG_CG_PLL_PIXCLK_SEL__SI regDCCG_CG_PLL_PIXCLK_SEL__SI; -typedef union DCCG_DEBUG_01__SI regDCCG_DEBUG_01__SI; -typedef union DCCG_DEBUG_02__SI regDCCG_DEBUG_02__SI; -typedef union DCCG_DEBUG_03__SI regDCCG_DEBUG_03__SI; -typedef union DCCG_DEBUG_04__SI regDCCG_DEBUG_04__SI; -typedef union DCCG_DEBUG_05__SI regDCCG_DEBUG_05__SI; -typedef union DCCG_DEBUG_06__SI regDCCG_DEBUG_06__SI; -typedef union DCCG_DEBUG_07__SI regDCCG_DEBUG_07__SI; -typedef union DCCG_DEBUG_08__SI regDCCG_DEBUG_08__SI; -typedef union DCCG_DEBUG_09__SI regDCCG_DEBUG_09__SI; -typedef union DCCG_DEBUG_10__SI regDCCG_DEBUG_10__SI; -typedef union DCCG_DEBUG_11__SI regDCCG_DEBUG_11__SI; -typedef union DCCG_DEBUG_12__SI regDCCG_DEBUG_12__SI; -typedef union DCCG_DEBUG_13__SI regDCCG_DEBUG_13__SI; -typedef union DCCG_DEBUG_BLOCK_ID__SI regDCCG_DEBUG_BLOCK_ID__SI; -typedef union DCCG_DEBUG__SI regDCCG_DEBUG__SI; -typedef union DCCG_GATE_DISABLE_CNTL__SI regDCCG_GATE_DISABLE_CNTL__SI; -typedef union DCCG_TEST_CLK_SEL__SI regDCCG_TEST_CLK_SEL__SI; -typedef union DCCG_TEST_DEBUG_DATA__SI regDCCG_TEST_DEBUG_DATA__SI; -typedef union DCCG_TEST_DEBUG_INDEX__SI regDCCG_TEST_DEBUG_INDEX__SI; -typedef union DCCG_VPCLK_CNTL__SI regDCCG_VPCLK_CNTL__SI; -typedef union DCDEBUG_BUS_CLK1_SEL__SI regDCDEBUG_BUS_CLK1_SEL__SI; -typedef union DCDEBUG_BUS_CLK2_SEL__SI regDCDEBUG_BUS_CLK2_SEL__SI; -typedef union DCDEBUG_BUS_CLK3_SEL__SI regDCDEBUG_BUS_CLK3_SEL__SI; -typedef union DCDEBUG_BUS_CLK4_SEL__SI regDCDEBUG_BUS_CLK4_SEL__SI; -typedef union DCDEBUG_DATA_TRIGGER_MASK__SI regDCDEBUG_DATA_TRIGGER_MASK__SI; -typedef union DCDEBUG_DATA_TRIGGER_PATTERN__SI regDCDEBUG_DATA_TRIGGER_PATTERN__SI; -typedef union DCDEBUG_EDGE_TRIGGER_MASK__SI regDCDEBUG_EDGE_TRIGGER_MASK__SI; -typedef union DCDEBUG_EDGE_TRIGGER_PATTERN__SI regDCDEBUG_EDGE_TRIGGER_PATTERN__SI; -typedef union DCDEBUG_OUT_CNTL__SI regDCDEBUG_OUT_CNTL__SI; -typedef union DCDEBUG_OUT_PIN_OVERRIDE__SI regDCDEBUG_OUT_PIN_OVERRIDE__SI; -typedef union DCDEBUG_TRIGGER_CNTL__SI regDCDEBUG_TRIGGER_CNTL__SI; -typedef union DCDEBUG_TRIGGER_STAT__SI regDCDEBUG_TRIGGER_STAT__SI; -typedef union DCFE0_CLOCK_ENABLE__SI regDCFE0_CLOCK_ENABLE__SI; -typedef union DCFE1_CLOCK_ENABLE__SI regDCFE1_CLOCK_ENABLE__SI; -typedef union DCFE2_CLOCK_ENABLE__SI regDCFE2_CLOCK_ENABLE__SI; -typedef union DCFE3_CLOCK_ENABLE__SI regDCFE3_CLOCK_ENABLE__SI; -typedef union DCFE4_CLOCK_ENABLE__SI regDCFE4_CLOCK_ENABLE__SI; -typedef union DCFE5_CLOCK_ENABLE__SI regDCFE5_CLOCK_ENABLE__SI; -typedef union DCIO_DEBUG1__SI regDCIO_DEBUG1__SI; -typedef union DCIO_DEBUG2__SI regDCIO_DEBUG2__SI; -typedef union DCIO_DEBUG3__SI regDCIO_DEBUG3__SI; -typedef union DCIO_DEBUG4__SI regDCIO_DEBUG4__SI; -typedef union DCIO_DEBUG5__SI regDCIO_DEBUG5__SI; -typedef union DCIO_DEBUG6__SI regDCIO_DEBUG6__SI; -typedef union DCIO_DEBUG7__SI regDCIO_DEBUG7__SI; -typedef union DCIO_DEBUG__SI regDCIO_DEBUG__SI; -typedef union DCIO_IMPCAL_CNTL_AB__SI regDCIO_IMPCAL_CNTL_AB__SI; -typedef union DCIO_IMPCAL_CNTL_CD__SI regDCIO_IMPCAL_CNTL_CD__SI; -typedef union DCIO_IMPCAL_CNTL_EF__SI regDCIO_IMPCAL_CNTL_EF__SI; -typedef union DCI_TEST_DEBUG_DATA__SI regDCI_TEST_DEBUG_DATA__SI; -typedef union DCI_TEST_DEBUG_INDEX__SI regDCI_TEST_DEBUG_INDEX__SI; -typedef union DCPLL_CNTL__SI regDCPLL_CNTL__SI; -typedef union DCPLL_DEBUG_CLK_SEL__SI regDCPLL_DEBUG_CLK_SEL__SI; -typedef union DCPLL_DISPCLK_DTO_CNTL__SI regDCPLL_DISPCLK_DTO_CNTL__SI; -typedef union DCPLL_FB_DIV__SI regDCPLL_FB_DIV__SI; -typedef union DCPLL_PLL_CNTL__SI regDCPLL_PLL_CNTL__SI; -typedef union DCPLL_POST_DIV_SRC__SI regDCPLL_POST_DIV_SRC__SI; -typedef union DCPLL_POST_DIV__SI regDCPLL_POST_DIV__SI; -typedef union DCPLL_REF_DIV_SRC__SI regDCPLL_REF_DIV_SRC__SI; -typedef union DCPLL_REF_DIV__SI regDCPLL_REF_DIV__SI; -typedef union DCPLL_UNLOCK_DETECT_CNTL__SI regDCPLL_UNLOCK_DETECT_CNTL__SI; -typedef union DCPLL_UPDATE_CNTL__SI regDCPLL_UPDATE_CNTL__SI; -typedef union DCPLL_UPDATE_LOCK__SI regDCPLL_UPDATE_LOCK__SI; -typedef union DCPLL_VREG_CNTL__SI regDCPLL_VREG_CNTL__SI; -typedef union DCP_CONTROL__SI regDCP_CONTROL__SI; -typedef union DCP_CRC_CONTROL__SI regDCP_CRC_CONTROL__SI; -typedef union DCP_CRC_CURRENT__SI regDCP_CRC_CURRENT__SI; -typedef union DCP_CRC_LAST__SI regDCP_CRC_LAST__SI; -typedef union DCP_CRC_MASK__SI regDCP_CRC_MASK__SI; -typedef union DCP_DEBUG_ID__SI regDCP_DEBUG_ID__SI; -typedef union DCP_DEBUG__SI regDCP_DEBUG__SI; -typedef union DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI regDCP_LB_DATA_GAP_BETWEEN_CHUNK__SI; -typedef union DCP_MULTI_CHIP_CNTL__SI regDCP_MULTI_CHIP_CNTL__SI; -typedef union DCP_RBBMIF_RDWR_TIMEOUT__SI regDCP_RBBMIF_RDWR_TIMEOUT__SI; -typedef union DCP_TEST_DEBUG_DATA__SI regDCP_TEST_DEBUG_DATA__SI; -typedef union DCP_TEST_DEBUG_INDEX__SI regDCP_TEST_DEBUG_INDEX__SI; -typedef union DCP_TILING_CONFIG__SI regDCP_TILING_CONFIG__SI; -typedef union DC_ABM1_ACE_CNTL_MISC__SI regDC_ABM1_ACE_CNTL_MISC__SI; -typedef union DC_ABM1_ACE_OFFSET_SLOPE_0__SI regDC_ABM1_ACE_OFFSET_SLOPE_0__SI; -typedef union DC_ABM1_ACE_OFFSET_SLOPE_1__SI regDC_ABM1_ACE_OFFSET_SLOPE_1__SI; -typedef union DC_ABM1_ACE_OFFSET_SLOPE_2__SI regDC_ABM1_ACE_OFFSET_SLOPE_2__SI; -typedef union DC_ABM1_ACE_OFFSET_SLOPE_3__SI regDC_ABM1_ACE_OFFSET_SLOPE_3__SI; -typedef union DC_ABM1_ACE_OFFSET_SLOPE_4__SI regDC_ABM1_ACE_OFFSET_SLOPE_4__SI; -typedef union DC_ABM1_ACE_THRES_12__SI regDC_ABM1_ACE_THRES_12__SI; -typedef union DC_ABM1_ACE_THRES_34__SI regDC_ABM1_ACE_THRES_34__SI; -typedef union DC_ABM1_BL_MASTER_LOCK__SI regDC_ABM1_BL_MASTER_LOCK__SI; -typedef union DC_ABM1_CNTL__SI regDC_ABM1_CNTL__SI; -typedef union DC_ABM1_DEBUG_MISC__SI regDC_ABM1_DEBUG_MISC__SI; -typedef union DC_ABM1_HGLS_REG_READ_PROGRESS__SI regDC_ABM1_HGLS_REG_READ_PROGRESS__SI; -typedef union DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI regDC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI; -typedef union DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI regDC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI; -typedef union DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI regDC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI; -typedef union DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI regDC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI; -typedef union DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI regDC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI; -typedef union DC_ABM1_HG_MISC_CTRL__SI regDC_ABM1_HG_MISC_CTRL__SI; -typedef union DC_ABM1_HG_RESULT_10__SI regDC_ABM1_HG_RESULT_10__SI; -typedef union DC_ABM1_HG_RESULT_11__SI regDC_ABM1_HG_RESULT_11__SI; -typedef union DC_ABM1_HG_RESULT_12__SI regDC_ABM1_HG_RESULT_12__SI; -typedef union DC_ABM1_HG_RESULT_13__SI regDC_ABM1_HG_RESULT_13__SI; -typedef union DC_ABM1_HG_RESULT_14__SI regDC_ABM1_HG_RESULT_14__SI; -typedef union DC_ABM1_HG_RESULT_15__SI regDC_ABM1_HG_RESULT_15__SI; -typedef union DC_ABM1_HG_RESULT_16__SI regDC_ABM1_HG_RESULT_16__SI; -typedef union DC_ABM1_HG_RESULT_17__SI regDC_ABM1_HG_RESULT_17__SI; -typedef union DC_ABM1_HG_RESULT_18__SI regDC_ABM1_HG_RESULT_18__SI; -typedef union DC_ABM1_HG_RESULT_19__SI regDC_ABM1_HG_RESULT_19__SI; -typedef union DC_ABM1_HG_RESULT_1__SI regDC_ABM1_HG_RESULT_1__SI; -typedef union DC_ABM1_HG_RESULT_20__SI regDC_ABM1_HG_RESULT_20__SI; -typedef union DC_ABM1_HG_RESULT_21__SI regDC_ABM1_HG_RESULT_21__SI; -typedef union DC_ABM1_HG_RESULT_22__SI regDC_ABM1_HG_RESULT_22__SI; -typedef union DC_ABM1_HG_RESULT_23__SI regDC_ABM1_HG_RESULT_23__SI; -typedef union DC_ABM1_HG_RESULT_24__SI regDC_ABM1_HG_RESULT_24__SI; -typedef union DC_ABM1_HG_RESULT_2__SI regDC_ABM1_HG_RESULT_2__SI; -typedef union DC_ABM1_HG_RESULT_3__SI regDC_ABM1_HG_RESULT_3__SI; -typedef union DC_ABM1_HG_RESULT_4__SI regDC_ABM1_HG_RESULT_4__SI; -typedef union DC_ABM1_HG_RESULT_5__SI regDC_ABM1_HG_RESULT_5__SI; -typedef union DC_ABM1_HG_RESULT_6__SI regDC_ABM1_HG_RESULT_6__SI; -typedef union DC_ABM1_HG_RESULT_7__SI regDC_ABM1_HG_RESULT_7__SI; -typedef union DC_ABM1_HG_RESULT_8__SI regDC_ABM1_HG_RESULT_8__SI; -typedef union DC_ABM1_HG_RESULT_9__SI regDC_ABM1_HG_RESULT_9__SI; -typedef union DC_ABM1_HG_SAMPLE_RATE__SI regDC_ABM1_HG_SAMPLE_RATE__SI; -typedef union DC_ABM1_IPCSC_COEFF_SEL__SI regDC_ABM1_IPCSC_COEFF_SEL__SI; -typedef union DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI regDC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI; -typedef union DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI regDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI; -typedef union DC_ABM1_LS_MIN_MAX_LUMA__SI regDC_ABM1_LS_MIN_MAX_LUMA__SI; -typedef union DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI regDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI; -typedef union DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI regDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI; -typedef union DC_ABM1_LS_OVR_SCAN_BIN__SI regDC_ABM1_LS_OVR_SCAN_BIN__SI; -typedef union DC_ABM1_LS_PIXEL_COUNT__SI regDC_ABM1_LS_PIXEL_COUNT__SI; -typedef union DC_ABM1_LS_SAMPLE_RATE__SI regDC_ABM1_LS_SAMPLE_RATE__SI; -typedef union DC_ABM1_LS_SUM_OF_LUMA__SI regDC_ABM1_LS_SUM_OF_LUMA__SI; -typedef union DC_DISPCLK_PERFCOUNTER0_HI__SI regDC_DISPCLK_PERFCOUNTER0_HI__SI; -typedef union DC_DISPCLK_PERFCOUNTER0_LOW__SI regDC_DISPCLK_PERFCOUNTER0_LOW__SI; -typedef union DC_DISPCLK_PERFCOUNTER0_SELECT__SI regDC_DISPCLK_PERFCOUNTER0_SELECT__SI; -typedef union DC_DISPCLK_PERFCOUNTER1_HI__SI regDC_DISPCLK_PERFCOUNTER1_HI__SI; -typedef union DC_DISPCLK_PERFCOUNTER1_LOW__SI regDC_DISPCLK_PERFCOUNTER1_LOW__SI; -typedef union DC_DISPCLK_PERFCOUNTER1_SELECT__SI regDC_DISPCLK_PERFCOUNTER1_SELECT__SI; -typedef union DC_DMCU_SCRATCH__SI regDC_DMCU_SCRATCH__SI; -typedef union DC_DOUT_DEBUG_MUX_CNTL__SI regDC_DOUT_DEBUG_MUX_CNTL__SI; -typedef union DC_FID_CNT__SI regDC_FID_CNT__SI; -typedef union DC_GENERICA__SI regDC_GENERICA__SI; -typedef union DC_GENERICB__SI regDC_GENERICB__SI; -typedef union DC_GPIO_DDC1_A__SI regDC_GPIO_DDC1_A__SI; -typedef union DC_GPIO_DDC1_EN__SI regDC_GPIO_DDC1_EN__SI; -typedef union DC_GPIO_DDC1_MASK__SI regDC_GPIO_DDC1_MASK__SI; -typedef union DC_GPIO_DDC1_Y__SI regDC_GPIO_DDC1_Y__SI; -typedef union DC_GPIO_DDC2_A__SI regDC_GPIO_DDC2_A__SI; -typedef union DC_GPIO_DDC2_EN__SI regDC_GPIO_DDC2_EN__SI; -typedef union DC_GPIO_DDC2_MASK__SI regDC_GPIO_DDC2_MASK__SI; -typedef union DC_GPIO_DDC2_Y__SI regDC_GPIO_DDC2_Y__SI; -typedef union DC_GPIO_DDC3_A__SI regDC_GPIO_DDC3_A__SI; -typedef union DC_GPIO_DDC3_EN__SI regDC_GPIO_DDC3_EN__SI; -typedef union DC_GPIO_DDC3_MASK__SI regDC_GPIO_DDC3_MASK__SI; -typedef union DC_GPIO_DDC3_Y__SI regDC_GPIO_DDC3_Y__SI; -typedef union DC_GPIO_DDC4_A__SI regDC_GPIO_DDC4_A__SI; -typedef union DC_GPIO_DDC4_EN__SI regDC_GPIO_DDC4_EN__SI; -typedef union DC_GPIO_DDC4_MASK__SI regDC_GPIO_DDC4_MASK__SI; -typedef union DC_GPIO_DDC4_Y__SI regDC_GPIO_DDC4_Y__SI; -typedef union DC_GPIO_DDC5_A__SI regDC_GPIO_DDC5_A__SI; -typedef union DC_GPIO_DDC5_EN__SI regDC_GPIO_DDC5_EN__SI; -typedef union DC_GPIO_DDC5_MASK__SI regDC_GPIO_DDC5_MASK__SI; -typedef union DC_GPIO_DDC5_Y__SI regDC_GPIO_DDC5_Y__SI; -typedef union DC_GPIO_DDC6_A__SI regDC_GPIO_DDC6_A__SI; -typedef union DC_GPIO_DDC6_EN__SI regDC_GPIO_DDC6_EN__SI; -typedef union DC_GPIO_DDC6_MASK__SI regDC_GPIO_DDC6_MASK__SI; -typedef union DC_GPIO_DDC6_Y__SI regDC_GPIO_DDC6_Y__SI; -typedef union DC_GPIO_DEBUG__SI regDC_GPIO_DEBUG__SI; -typedef union DC_GPIO_DVODATA_A__SI regDC_GPIO_DVODATA_A__SI; -typedef union DC_GPIO_DVODATA_EN__SI regDC_GPIO_DVODATA_EN__SI; -typedef union DC_GPIO_DVODATA_MASK__SI regDC_GPIO_DVODATA_MASK__SI; -typedef union DC_GPIO_DVODATA_Y__SI regDC_GPIO_DVODATA_Y__SI; -typedef union DC_GPIO_GENERIC_A__SI regDC_GPIO_GENERIC_A__SI; -typedef union DC_GPIO_GENERIC_EN__SI regDC_GPIO_GENERIC_EN__SI; -typedef union DC_GPIO_GENERIC_MASK__SI regDC_GPIO_GENERIC_MASK__SI; -typedef union DC_GPIO_GENERIC_Y__SI regDC_GPIO_GENERIC_Y__SI; -typedef union DC_GPIO_HPD_A__SI regDC_GPIO_HPD_A__SI; -typedef union DC_GPIO_HPD_EN__SI regDC_GPIO_HPD_EN__SI; -typedef union DC_GPIO_HPD_MASK__SI regDC_GPIO_HPD_MASK__SI; -typedef union DC_GPIO_HPD_Y__SI regDC_GPIO_HPD_Y__SI; -typedef union DC_GPIO_PAD_STRENGTH_1__SI regDC_GPIO_PAD_STRENGTH_1__SI; -typedef union DC_GPIO_PAD_STRENGTH_2__SI regDC_GPIO_PAD_STRENGTH_2__SI; -typedef union DC_GPIO_PWRSEQ_A__SI regDC_GPIO_PWRSEQ_A__SI; -typedef union DC_GPIO_PWRSEQ_EN__SI regDC_GPIO_PWRSEQ_EN__SI; -typedef union DC_GPIO_PWRSEQ_MASK__SI regDC_GPIO_PWRSEQ_MASK__SI; -typedef union DC_GPIO_PWRSEQ_Y__SI regDC_GPIO_PWRSEQ_Y__SI; -typedef union DC_GPIO_SYNCA_A__SI regDC_GPIO_SYNCA_A__SI; -typedef union DC_GPIO_SYNCA_EN__SI regDC_GPIO_SYNCA_EN__SI; -typedef union DC_GPIO_SYNCA_MASK__SI regDC_GPIO_SYNCA_MASK__SI; -typedef union DC_GPIO_SYNCA_Y__SI regDC_GPIO_SYNCA_Y__SI; -typedef union DC_GPIO_SYNCB_A__SI regDC_GPIO_SYNCB_A__SI; -typedef union DC_GPIO_SYNCB_EN__SI regDC_GPIO_SYNCB_EN__SI; -typedef union DC_GPIO_SYNCB_MASK__SI regDC_GPIO_SYNCB_MASK__SI; -typedef union DC_GPIO_SYNCB_Y__SI regDC_GPIO_SYNCB_Y__SI; -typedef union DC_GPU_TIMER_READ_CNTL__SI regDC_GPU_TIMER_READ_CNTL__SI; -typedef union DC_GPU_TIMER_READ__SI regDC_GPU_TIMER_READ__SI; -typedef union DC_GPU_TIMER_START_POSITION__SI regDC_GPU_TIMER_START_POSITION__SI; -typedef union DC_HPD1_CONTROL__SI regDC_HPD1_CONTROL__SI; -typedef union DC_HPD1_INT_CONTROL__SI regDC_HPD1_INT_CONTROL__SI; -typedef union DC_HPD1_INT_STATUS__SI regDC_HPD1_INT_STATUS__SI; -typedef union DC_HPD2_CONTROL__SI regDC_HPD2_CONTROL__SI; -typedef union DC_HPD2_INT_CONTROL__SI regDC_HPD2_INT_CONTROL__SI; -typedef union DC_HPD2_INT_STATUS__SI regDC_HPD2_INT_STATUS__SI; -typedef union DC_HPD3_CONTROL__SI regDC_HPD3_CONTROL__SI; -typedef union DC_HPD3_INT_CONTROL__SI regDC_HPD3_INT_CONTROL__SI; -typedef union DC_HPD3_INT_STATUS__SI regDC_HPD3_INT_STATUS__SI; -typedef union DC_HPD4_CONTROL__SI regDC_HPD4_CONTROL__SI; -typedef union DC_HPD4_INT_CONTROL__SI regDC_HPD4_INT_CONTROL__SI; -typedef union DC_HPD4_INT_STATUS__SI regDC_HPD4_INT_STATUS__SI; -typedef union DC_HPD5_CONTROL__SI regDC_HPD5_CONTROL__SI; -typedef union DC_HPD5_INT_CONTROL__SI regDC_HPD5_INT_CONTROL__SI; -typedef union DC_HPD5_INT_STATUS__SI regDC_HPD5_INT_STATUS__SI; -typedef union DC_HPD6_CONTROL__SI regDC_HPD6_CONTROL__SI; -typedef union DC_HPD6_INT_CONTROL__SI regDC_HPD6_INT_CONTROL__SI; -typedef union DC_HPD6_INT_STATUS__SI regDC_HPD6_INT_STATUS__SI; -typedef union DC_I2C_ARBITRATION__SI regDC_I2C_ARBITRATION__SI; -typedef union DC_I2C_CONTROL__SI regDC_I2C_CONTROL__SI; -typedef union DC_I2C_DATA__SI regDC_I2C_DATA__SI; -typedef union DC_I2C_DDC1_HW_STATUS__SI regDC_I2C_DDC1_HW_STATUS__SI; -typedef union DC_I2C_DDC1_SETUP__SI regDC_I2C_DDC1_SETUP__SI; -typedef union DC_I2C_DDC1_SPEED__SI regDC_I2C_DDC1_SPEED__SI; -typedef union DC_I2C_DDC2_HW_STATUS__SI regDC_I2C_DDC2_HW_STATUS__SI; -typedef union DC_I2C_DDC2_SETUP__SI regDC_I2C_DDC2_SETUP__SI; -typedef union DC_I2C_DDC2_SPEED__SI regDC_I2C_DDC2_SPEED__SI; -typedef union DC_I2C_DDC3_HW_STATUS__SI regDC_I2C_DDC3_HW_STATUS__SI; -typedef union DC_I2C_DDC3_SETUP__SI regDC_I2C_DDC3_SETUP__SI; -typedef union DC_I2C_DDC3_SPEED__SI regDC_I2C_DDC3_SPEED__SI; -typedef union DC_I2C_DDC4_HW_STATUS__SI regDC_I2C_DDC4_HW_STATUS__SI; -typedef union DC_I2C_DDC4_SETUP__SI regDC_I2C_DDC4_SETUP__SI; -typedef union DC_I2C_DDC4_SPEED__SI regDC_I2C_DDC4_SPEED__SI; -typedef union DC_I2C_DDC5_HW_STATUS__SI regDC_I2C_DDC5_HW_STATUS__SI; -typedef union DC_I2C_DDC5_SETUP__SI regDC_I2C_DDC5_SETUP__SI; -typedef union DC_I2C_DDC5_SPEED__SI regDC_I2C_DDC5_SPEED__SI; -typedef union DC_I2C_DDC6_HW_STATUS__SI regDC_I2C_DDC6_HW_STATUS__SI; -typedef union DC_I2C_DDC6_SETUP__SI regDC_I2C_DDC6_SETUP__SI; -typedef union DC_I2C_DDC6_SPEED__SI regDC_I2C_DDC6_SPEED__SI; -typedef union DC_I2C_INTERRUPT_CONTROL__SI regDC_I2C_INTERRUPT_CONTROL__SI; -typedef union DC_I2C_SW_STATUS__SI regDC_I2C_SW_STATUS__SI; -typedef union DC_I2C_TRANSACTION0__SI regDC_I2C_TRANSACTION0__SI; -typedef union DC_I2C_TRANSACTION1__SI regDC_I2C_TRANSACTION1__SI; -typedef union DC_I2C_TRANSACTION2__SI regDC_I2C_TRANSACTION2__SI; -typedef union DC_I2C_TRANSACTION3__SI regDC_I2C_TRANSACTION3__SI; -typedef union DC_LB_BLACK_KEYER_B__SI regDC_LB_BLACK_KEYER_B__SI; -typedef union DC_LB_BLACK_KEYER_G__SI regDC_LB_BLACK_KEYER_G__SI; -typedef union DC_LB_BLACK_KEYER_R__SI regDC_LB_BLACK_KEYER_R__SI; -typedef union DC_LB_MEMORY_SPLIT__SI regDC_LB_MEMORY_SPLIT__SI; -typedef union DC_LB_MEM_SIZE__SI regDC_LB_MEM_SIZE__SI; -typedef union DC_LUT_30_COLOR__SI regDC_LUT_30_COLOR__SI; -typedef union DC_LUT_AUTOFILL__SI regDC_LUT_AUTOFILL__SI; -typedef union DC_LUT_BLACK_OFFSET_BLUE__SI regDC_LUT_BLACK_OFFSET_BLUE__SI; -typedef union DC_LUT_BLACK_OFFSET_GREEN__SI regDC_LUT_BLACK_OFFSET_GREEN__SI; -typedef union DC_LUT_BLACK_OFFSET_RED__SI regDC_LUT_BLACK_OFFSET_RED__SI; -typedef union DC_LUT_CONTROL__SI regDC_LUT_CONTROL__SI; -typedef union DC_LUT_PWL_DATA__SI regDC_LUT_PWL_DATA__SI; -typedef union DC_LUT_RW_INDEX__SI regDC_LUT_RW_INDEX__SI; -typedef union DC_LUT_RW_MODE__SI regDC_LUT_RW_MODE__SI; -typedef union DC_LUT_SEQ_COLOR__SI regDC_LUT_SEQ_COLOR__SI; -typedef union DC_LUT_WHITE_OFFSET_BLUE__SI regDC_LUT_WHITE_OFFSET_BLUE__SI; -typedef union DC_LUT_WHITE_OFFSET_GREEN__SI regDC_LUT_WHITE_OFFSET_GREEN__SI; -typedef union DC_LUT_WHITE_OFFSET_RED__SI regDC_LUT_WHITE_OFFSET_RED__SI; -typedef union DC_LUT_WRITE_EN_MASK__SI regDC_LUT_WRITE_EN_MASK__SI; -typedef union DC_MVP_LB_CONTROL__SI regDC_MVP_LB_CONTROL__SI; -typedef union DC_PAD_EXTERN_SIG__SI regDC_PAD_EXTERN_SIG__SI; -typedef union DC_PERFMON_CNTL__SI regDC_PERFMON_CNTL__SI; -typedef union DC_PINSTRAPS__SI regDC_PINSTRAPS__SI; -typedef union DC_REF_CLK_CNTL__SI regDC_REF_CLK_CNTL__SI; -typedef union DC_SCLK_PERFCOUNTER0_HI__SI regDC_SCLK_PERFCOUNTER0_HI__SI; -typedef union DC_SCLK_PERFCOUNTER0_LOW__SI regDC_SCLK_PERFCOUNTER0_LOW__SI; -typedef union DC_SCLK_PERFCOUNTER0_SELECT__SI regDC_SCLK_PERFCOUNTER0_SELECT__SI; -typedef union DC_SCLK_PERFCOUNTER1_HI__SI regDC_SCLK_PERFCOUNTER1_HI__SI; -typedef union DC_SCLK_PERFCOUNTER1_LOW__SI regDC_SCLK_PERFCOUNTER1_LOW__SI; -typedef union DC_SCLK_PERFCOUNTER1_SELECT__SI regDC_SCLK_PERFCOUNTER1_SELECT__SI; -typedef union DC_STUTTER_CNTL__SI regDC_STUTTER_CNTL__SI; -typedef union DC_STUTTER_STATUS__SI regDC_STUTTER_STATUS__SI; -typedef union DC_TEST_DEBUG_DATA__SI regDC_TEST_DEBUG_DATA__SI; -typedef union DC_TEST_DEBUG_INDEX__SI regDC_TEST_DEBUG_INDEX__SI; -typedef union DC_TEST_DEBUG_VIP_CNTL__SI regDC_TEST_DEBUG_VIP_CNTL__SI; -typedef union DDIA_DEBUG1__SI regDDIA_DEBUG1__SI; -typedef union DDIA_DEBUG2__SI regDDIA_DEBUG2__SI; -typedef union DDIA_DEBUG3__SI regDDIA_DEBUG3__SI; -typedef union DDIA_DEBUG4__SI regDDIA_DEBUG4__SI; -typedef union DDIA_DEBUG5__SI regDDIA_DEBUG5__SI; -typedef union DDIA_DEBUG6__SI regDDIA_DEBUG6__SI; -typedef union DEBUG_DATA regDEBUG_DATA; -typedef union DEBUG_DRM_MASK_0__SI regDEBUG_DRM_MASK_0__SI; -typedef union DEBUG_DRM_MASK_1__SI regDEBUG_DRM_MASK_1__SI; -typedef union DEBUG_DRM_MASK_2__SI regDEBUG_DRM_MASK_2__SI; -typedef union DEBUG_DRM_MASK_3__SI regDEBUG_DRM_MASK_3__SI; -typedef union DEBUG_ENCRYP_COEF_0__SI regDEBUG_ENCRYP_COEF_0__SI; -typedef union DEBUG_ENCRYP_COEF_1__SI regDEBUG_ENCRYP_COEF_1__SI; -typedef union DEBUG_ENCRYP_COEF_2__SI regDEBUG_ENCRYP_COEF_2__SI; -typedef union DEBUG_ENCRYP_COEF_3__SI regDEBUG_ENCRYP_COEF_3__SI; -typedef union DEBUG_INDEX regDEBUG_INDEX; -typedef union DENTIST_DISPCLK_CNTL__SI regDENTIST_DISPCLK_CNTL__SI; -typedef union DESKTOP_HEIGHT__SI regDESKTOP_HEIGHT__SI; -typedef union DEVICE_CAP regDEVICE_CAP; -typedef union DEVICE_CAP2__CI__VI regDEVICE_CAP2__CI__VI; -typedef union DEVICE_CAP2__SI regDEVICE_CAP2__SI; -typedef union DEVICE_CNTL2 regDEVICE_CNTL2; -typedef union DEVICE_CNTL__CI__VI regDEVICE_CNTL__CI__VI; -typedef union DEVICE_CNTL__SI regDEVICE_CNTL__SI; -typedef union DEVICE_ID regDEVICE_ID; -typedef union DEVICE_STATUS regDEVICE_STATUS; -typedef union DEVICE_STATUS2 regDEVICE_STATUS2; -typedef union DFT_CLK_STOP_COUNTER_LSB__CI__VI regDFT_CLK_STOP_COUNTER_LSB__CI__VI; -typedef union DFT_CLK_STOP_COUNTER_MSB__CI__VI regDFT_CLK_STOP_COUNTER_MSB__CI__VI; -typedef union DFT_CLK_STOP__CI__VI regDFT_CLK_STOP__CI__VI; -typedef union DH_TEST regDH_TEST; -typedef union DIDT_DB_CTRL0__CI__VI regDIDT_DB_CTRL0__CI__VI; -typedef union DIDT_DB_CTRL1__CI__VI regDIDT_DB_CTRL1__CI__VI; -typedef union DIDT_DB_CTRL2__CI__VI regDIDT_DB_CTRL2__CI__VI; -typedef union DIDT_DB_WEIGHT0_3__CI__VI regDIDT_DB_WEIGHT0_3__CI__VI; -typedef union DIDT_DB_WEIGHT4_7__CI__VI regDIDT_DB_WEIGHT4_7__CI__VI; -typedef union DIDT_DB_WEIGHT8_11__CI__VI regDIDT_DB_WEIGHT8_11__CI__VI; -typedef union DIDT_IND_DATA__CI__VI regDIDT_IND_DATA__CI__VI; -typedef union DIDT_IND_INDEX__CI__VI regDIDT_IND_INDEX__CI__VI; -typedef union DIDT_SQ_CTRL0__CI__VI regDIDT_SQ_CTRL0__CI__VI; -typedef union DIDT_SQ_CTRL1__CI__VI regDIDT_SQ_CTRL1__CI__VI; -typedef union DIDT_SQ_CTRL2__CI__VI regDIDT_SQ_CTRL2__CI__VI; -typedef union DIDT_SQ_WEIGHT0_3__CI__VI regDIDT_SQ_WEIGHT0_3__CI__VI; -typedef union DIDT_SQ_WEIGHT4_7__CI__VI regDIDT_SQ_WEIGHT4_7__CI__VI; -typedef union DIDT_SQ_WEIGHT8_11__CI__VI regDIDT_SQ_WEIGHT8_11__CI__VI; -typedef union DIDT_TCP_CTRL0__CI__VI regDIDT_TCP_CTRL0__CI__VI; -typedef union DIDT_TCP_CTRL1__CI__VI regDIDT_TCP_CTRL1__CI__VI; -typedef union DIDT_TCP_CTRL2__CI__VI regDIDT_TCP_CTRL2__CI__VI; -typedef union DIDT_TCP_WEIGHT0_3__CI__VI regDIDT_TCP_WEIGHT0_3__CI__VI; -typedef union DIDT_TCP_WEIGHT4_7__CI__VI regDIDT_TCP_WEIGHT4_7__CI__VI; -typedef union DIDT_TCP_WEIGHT8_11__CI__VI regDIDT_TCP_WEIGHT8_11__CI__VI; -typedef union DIDT_TD_CTRL0__CI__VI regDIDT_TD_CTRL0__CI__VI; -typedef union DIDT_TD_CTRL1__CI__VI regDIDT_TD_CTRL1__CI__VI; -typedef union DIDT_TD_CTRL2__CI__VI regDIDT_TD_CTRL2__CI__VI; -typedef union DIDT_TD_WEIGHT0_3__CI__VI regDIDT_TD_WEIGHT0_3__CI__VI; -typedef union DIDT_TD_WEIGHT4_7__CI__VI regDIDT_TD_WEIGHT4_7__CI__VI; -typedef union DIDT_TD_WEIGHT8_11__CI__VI regDIDT_TD_WEIGHT8_11__CI__VI; -typedef union DIGA_CLOCK_ENABLE__SI regDIGA_CLOCK_ENABLE__SI; -typedef union DIGA_DEBUG3__SI regDIGA_DEBUG3__SI; -typedef union DIGA_DEBUG4__SI regDIGA_DEBUG4__SI; -typedef union DIGA_DEBUG5__SI regDIGA_DEBUG5__SI; -typedef union DIGA_DEBUG6__SI regDIGA_DEBUG6__SI; -typedef union DIGA_DEBUG7__SI regDIGA_DEBUG7__SI; -typedef union DIGA_DEBUG8__SI regDIGA_DEBUG8__SI; -typedef union DIGA_HDCP_DEBUG_INFO__SI regDIGA_HDCP_DEBUG_INFO__SI; -typedef union DIGA_LINK_CNTL__SI regDIGA_LINK_CNTL__SI; -typedef union DIGA_TRANSMITTER_ENABLE__SI regDIGA_TRANSMITTER_ENABLE__SI; -typedef union DIGB_CLOCK_ENABLE__SI regDIGB_CLOCK_ENABLE__SI; -typedef union DIGB_DEBUG3__SI regDIGB_DEBUG3__SI; -typedef union DIGB_DEBUG4__SI regDIGB_DEBUG4__SI; -typedef union DIGB_DEBUG5__SI regDIGB_DEBUG5__SI; -typedef union DIGB_DEBUG6__SI regDIGB_DEBUG6__SI; -typedef union DIGB_DEBUG7__SI regDIGB_DEBUG7__SI; -typedef union DIGB_DEBUG8__SI regDIGB_DEBUG8__SI; -typedef union DIGB_HDCP_DEBUG_INFO__SI regDIGB_HDCP_DEBUG_INFO__SI; -typedef union DIGB_LINK_CNTL__SI regDIGB_LINK_CNTL__SI; -typedef union DIGB_TRANSMITTER_ENABLE__SI regDIGB_TRANSMITTER_ENABLE__SI; -typedef union DIGC_CLOCK_ENABLE__SI regDIGC_CLOCK_ENABLE__SI; -typedef union DIGD_CLOCK_ENABLE__SI regDIGD_CLOCK_ENABLE__SI; -typedef union DIGE_CLOCK_ENABLE__SI regDIGE_CLOCK_ENABLE__SI; -typedef union DIGF_CLOCK_ENABLE__SI regDIGF_CLOCK_ENABLE__SI; -typedef union DIG_CLOCK_PATTERN__SI regDIG_CLOCK_PATTERN__SI; -typedef union DIG_CNTL__SI regDIG_CNTL__SI; -typedef union DIG_DEBUG__SI regDIG_DEBUG__SI; -typedef union DIG_OUTPUT_CRC_CNTL__SI regDIG_OUTPUT_CRC_CNTL__SI; -typedef union DIG_OUTPUT_CRC_RESULT__SI regDIG_OUTPUT_CRC_RESULT__SI; -typedef union DIG_RANDOM_PATTERN_SEED__SI regDIG_RANDOM_PATTERN_SEED__SI; -typedef union DIG_TEST_PATTERN__SI regDIG_TEST_PATTERN__SI; -typedef union DISPCLK_CGTT_BLK_CTRL_REG__SI regDISPCLK_CGTT_BLK_CTRL_REG__SI; -typedef union DISPCLK_DCFE0_SOFT_RESET__SI regDISPCLK_DCFE0_SOFT_RESET__SI; -typedef union DISPCLK_DCFE1_SOFT_RESET__SI regDISPCLK_DCFE1_SOFT_RESET__SI; -typedef union DISPCLK_DCFE2_SOFT_RESET__SI regDISPCLK_DCFE2_SOFT_RESET__SI; -typedef union DISPCLK_DCFE3_SOFT_RESET__SI regDISPCLK_DCFE3_SOFT_RESET__SI; -typedef union DISPCLK_DCFE4_SOFT_RESET__SI regDISPCLK_DCFE4_SOFT_RESET__SI; -typedef union DISPCLK_DCFE5_SOFT_RESET__SI regDISPCLK_DCFE5_SOFT_RESET__SI; -typedef union DISPCLK_DCI_SOFT_RESET__SI regDISPCLK_DCI_SOFT_RESET__SI; -typedef union DISPCLK_DCO_SOFT_RESET__SI regDISPCLK_DCO_SOFT_RESET__SI; -typedef union DISPOUT_DEBUG_ID__SI regDISPOUT_DEBUG_ID__SI; -typedef union DISPOUT_SOFT_RESET__SI regDISPOUT_SOFT_RESET__SI; -typedef union DISP_INTERRUPT_STATUS_CONTINUE2__SI regDISP_INTERRUPT_STATUS_CONTINUE2__SI; -typedef union DISP_INTERRUPT_STATUS_CONTINUE__SI regDISP_INTERRUPT_STATUS_CONTINUE__SI; -typedef union DISP_INTERRUPT_STATUS__SI regDISP_INTERRUPT_STATUS__SI; -typedef union DISP_TIMER_CONTROL__SI regDISP_TIMER_CONTROL__SI; -typedef union DLL_CNTL__SI__CI regDLL_CNTL__SI__CI; -typedef union DMA_POSITION_LOWER_BASE_ADDRESS__SI regDMA_POSITION_LOWER_BASE_ADDRESS__SI; -typedef union DMA_POSITION_UPPER_BASE_ADDRESS__SI regDMA_POSITION_UPPER_BASE_ADDRESS__SI; -typedef union DMA_VIP0_TABLE_ADDR__SI regDMA_VIP0_TABLE_ADDR__SI; -typedef union DMA_VIP1_TABLE_ADDR__SI regDMA_VIP1_TABLE_ADDR__SI; -typedef union DMA_VIP2_TABLE_ADDR__SI regDMA_VIP2_TABLE_ADDR__SI; -typedef union DMA_VIP3_TABLE_ADDR__SI regDMA_VIP3_TABLE_ADDR__SI; -typedef union DMA_VIPH0_ACTIVE__SI regDMA_VIPH0_ACTIVE__SI; -typedef union DMA_VIPH0_COMMAND__SI regDMA_VIPH0_COMMAND__SI; -typedef union DMA_VIPH0_DESTINATION_ADDR_HIGH__SI regDMA_VIPH0_DESTINATION_ADDR_HIGH__SI; -typedef union DMA_VIPH0_SOURCE_ADDR_HIGH__SI regDMA_VIPH0_SOURCE_ADDR_HIGH__SI; -typedef union DMA_VIPH0_TABLE_ADDR_HIGH__SI regDMA_VIPH0_TABLE_ADDR_HIGH__SI; -typedef union DMA_VIPH1_ACTIVE__SI regDMA_VIPH1_ACTIVE__SI; -typedef union DMA_VIPH1_COMMAND__SI regDMA_VIPH1_COMMAND__SI; -typedef union DMA_VIPH1_DESTINATION_ADDR_HIGH__SI regDMA_VIPH1_DESTINATION_ADDR_HIGH__SI; -typedef union DMA_VIPH1_SOURCE_ADDR_HIGH__SI regDMA_VIPH1_SOURCE_ADDR_HIGH__SI; -typedef union DMA_VIPH1_TABLE_ADDR_HIGH__SI regDMA_VIPH1_TABLE_ADDR_HIGH__SI; -typedef union DMA_VIPH2_ACTIVE__SI regDMA_VIPH2_ACTIVE__SI; -typedef union DMA_VIPH2_COMMAND__SI regDMA_VIPH2_COMMAND__SI; -typedef union DMA_VIPH2_DESTINATION_ADDR_HIGH__SI regDMA_VIPH2_DESTINATION_ADDR_HIGH__SI; -typedef union DMA_VIPH2_SOURCE_ADDR_HIGH__SI regDMA_VIPH2_SOURCE_ADDR_HIGH__SI; -typedef union DMA_VIPH2_TABLE_ADDR_HIGH__SI regDMA_VIPH2_TABLE_ADDR_HIGH__SI; -typedef union DMA_VIPH3_ACTIVE__SI regDMA_VIPH3_ACTIVE__SI; -typedef union DMA_VIPH3_COMMAND__SI regDMA_VIPH3_COMMAND__SI; -typedef union DMA_VIPH3_DESTINATION_ADDR_HIGH__SI regDMA_VIPH3_DESTINATION_ADDR_HIGH__SI; -typedef union DMA_VIPH3_SOURCE_ADDR_HIGH__SI regDMA_VIPH3_SOURCE_ADDR_HIGH__SI; -typedef union DMA_VIPH3_TABLE_ADDR_HIGH__SI regDMA_VIPH3_TABLE_ADDR_HIGH__SI; -typedef union DMA_VIPH_ABORT__SI regDMA_VIPH_ABORT__SI; -typedef union DMA_VIPH_CHUNK_0__SI regDMA_VIPH_CHUNK_0__SI; -typedef union DMA_VIPH_CHUNK_1_VAL__SI regDMA_VIPH_CHUNK_1_VAL__SI; -typedef union DMA_VIPH_MISC_CNTL__SI regDMA_VIPH_MISC_CNTL__SI; -typedef union DMA_VIPH_STATUS__SI regDMA_VIPH_STATUS__SI; -typedef union DMA_VIPH_WRCOMB__SI regDMA_VIPH_WRCOMB__SI; -typedef union DMCU_CTRL__SI regDMCU_CTRL__SI; -typedef union DMCU_DEBUG_00__SI regDMCU_DEBUG_00__SI; -typedef union DMCU_DEBUG_01__SI regDMCU_DEBUG_01__SI; -typedef union DMCU_DEBUG_02__SI regDMCU_DEBUG_02__SI; -typedef union DMCU_DEBUG_03__SI regDMCU_DEBUG_03__SI; -typedef union DMCU_DEBUG_04__SI regDMCU_DEBUG_04__SI; -typedef union DMCU_DEBUG_05__SI regDMCU_DEBUG_05__SI; -typedef union DMCU_DEBUG_06__SI regDMCU_DEBUG_06__SI; -typedef union DMCU_DEBUG_07__SI regDMCU_DEBUG_07__SI; -typedef union DMCU_DEBUG_08__SI regDMCU_DEBUG_08__SI; -typedef union DMCU_DEBUG_09__SI regDMCU_DEBUG_09__SI; -typedef union DMCU_DEBUG_0A__SI regDMCU_DEBUG_0A__SI; -typedef union DMCU_DEBUG_0B__SI regDMCU_DEBUG_0B__SI; -typedef union DMCU_DEBUG_0C__SI regDMCU_DEBUG_0C__SI; -typedef union DMCU_DEBUG_0D__SI regDMCU_DEBUG_0D__SI; -typedef union DMCU_DEBUG_0E__SI regDMCU_DEBUG_0E__SI; -typedef union DMCU_DEBUG_0F__SI regDMCU_DEBUG_0F__SI; -typedef union DMCU_DEBUG_10__SI regDMCU_DEBUG_10__SI; -typedef union DMCU_DEBUG_11__SI regDMCU_DEBUG_11__SI; -typedef union DMCU_DEBUG_12__SI regDMCU_DEBUG_12__SI; -typedef union DMCU_DEBUG_13__SI regDMCU_DEBUG_13__SI; -typedef union DMCU_DEBUG_14__SI regDMCU_DEBUG_14__SI; -typedef union DMCU_DEBUG_15__SI regDMCU_DEBUG_15__SI; -typedef union DMCU_DEBUG_16__SI regDMCU_DEBUG_16__SI; -typedef union DMCU_DEBUG_17__SI regDMCU_DEBUG_17__SI; -typedef union DMCU_DEBUG_18__SI regDMCU_DEBUG_18__SI; -typedef union DMCU_DEBUG_19__SI regDMCU_DEBUG_19__SI; -typedef union DMCU_DEBUG_20__SI regDMCU_DEBUG_20__SI; -typedef union DMCU_DEBUG_21__SI regDMCU_DEBUG_21__SI; -typedef union DMCU_DEBUG_22__SI regDMCU_DEBUG_22__SI; -typedef union DMCU_DEBUG_23__SI regDMCU_DEBUG_23__SI; -typedef union DMCU_DEBUG_24__SI regDMCU_DEBUG_24__SI; -typedef union DMCU_DEBUG_25__SI regDMCU_DEBUG_25__SI; -typedef union DMCU_DEBUG_26__SI regDMCU_DEBUG_26__SI; -typedef union DMCU_DEBUG_27__SI regDMCU_DEBUG_27__SI; -typedef union DMCU_DEBUG_28__SI regDMCU_DEBUG_28__SI; -typedef union DMCU_DEBUG_29__SI regDMCU_DEBUG_29__SI; -typedef union DMCU_DEBUG_2A__SI regDMCU_DEBUG_2A__SI; -typedef union DMCU_DEBUG_2B__SI regDMCU_DEBUG_2B__SI; -typedef union DMCU_DEBUG_2C__SI regDMCU_DEBUG_2C__SI; -typedef union DMCU_DEBUG_32__SI regDMCU_DEBUG_32__SI; -typedef union DMCU_DEBUG_33__SI regDMCU_DEBUG_33__SI; -typedef union DMCU_DEBUG_34__SI regDMCU_DEBUG_34__SI; -typedef union DMCU_DEBUG_35__SI regDMCU_DEBUG_35__SI; -typedef union DMCU_DEBUG_36__SI regDMCU_DEBUG_36__SI; -typedef union DMCU_DEBUG_37__SI regDMCU_DEBUG_37__SI; -typedef union DMCU_DEBUG_38__SI regDMCU_DEBUG_38__SI; -typedef union DMCU_DEBUG_39__SI regDMCU_DEBUG_39__SI; -typedef union DMCU_DEBUG_3A__SI regDMCU_DEBUG_3A__SI; -typedef union DMCU_DEBUG_CONSTANT__SI regDMCU_DEBUG_CONSTANT__SI; -typedef union DMCU_DEBUG_ID__SI regDMCU_DEBUG_ID__SI; -typedef union DMCU_ERAM_RD_CTRL__SI regDMCU_ERAM_RD_CTRL__SI; -typedef union DMCU_ERAM_RD_DATA__SI regDMCU_ERAM_RD_DATA__SI; -typedef union DMCU_ERAM_WR_CTRL__SI regDMCU_ERAM_WR_CTRL__SI; -typedef union DMCU_ERAM_WR_DATA__SI regDMCU_ERAM_WR_DATA__SI; -typedef union DMCU_EVENT_TRIGGER__SI regDMCU_EVENT_TRIGGER__SI; -typedef union DMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI regDMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI; -typedef union DMCU_FW_CS_HI__SI regDMCU_FW_CS_HI__SI; -typedef union DMCU_FW_CS_LO__SI regDMCU_FW_CS_LO__SI; -typedef union DMCU_FW_END_ADDR__SI regDMCU_FW_END_ADDR__SI; -typedef union DMCU_FW_ISR_START_ADDR__SI regDMCU_FW_ISR_START_ADDR__SI; -typedef union DMCU_FW_START_ADDR__SI regDMCU_FW_START_ADDR__SI; -typedef union DMCU_INTERRUPT_STATUS__SI regDMCU_INTERRUPT_STATUS__SI; -typedef union DMCU_INTERRUPT_TO_HOST_EN_MASK__SI regDMCU_INTERRUPT_TO_HOST_EN_MASK__SI; -typedef union DMCU_INTERRUPT_TO_UC_EN_MASK__SI regDMCU_INTERRUPT_TO_UC_EN_MASK__SI; -typedef union DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI; -typedef union DMCU_INT_CNT__SI regDMCU_INT_CNT__SI; -typedef union DMCU_IRAM_RD_CTRL__SI regDMCU_IRAM_RD_CTRL__SI; -typedef union DMCU_IRAM_RD_DATA__SI regDMCU_IRAM_RD_DATA__SI; -typedef union DMCU_IRAM_WR_CTRL__SI regDMCU_IRAM_WR_CTRL__SI; -typedef union DMCU_IRAM_WR_DATA__SI regDMCU_IRAM_WR_DATA__SI; -typedef union DMCU_PC_START_ADDR__SI regDMCU_PC_START_ADDR__SI; -typedef union DMCU_RAM_ACCESS_CTRL__SI regDMCU_RAM_ACCESS_CTRL__SI; -typedef union DMCU_STATUS__SI regDMCU_STATUS__SI; -typedef union DMCU_TEST_DEBUG_DATA__SI regDMCU_TEST_DEBUG_DATA__SI; -typedef union DMCU_TEST_DEBUG_INDEX__SI regDMCU_TEST_DEBUG_INDEX__SI; -typedef union DMCU_UC_CCR__SI regDMCU_UC_CCR__SI; -typedef union DMCU_UC_INTERNAL_INT_STATUS__SI regDMCU_UC_INTERNAL_INT_STATUS__SI; -typedef union DMIF_ARBITRATION_CONTROL__SI regDMIF_ARBITRATION_CONTROL__SI; -typedef union DMIF_CONTROL__SI regDMIF_CONTROL__SI; -typedef union DMIF_DEBUG00__SI regDMIF_DEBUG00__SI; -typedef union DMIF_DEBUG01__SI regDMIF_DEBUG01__SI; -typedef union DMIF_DEBUG02__SI regDMIF_DEBUG02__SI; -typedef union DMIF_DEBUG03__SI regDMIF_DEBUG03__SI; -typedef union DMIF_DEBUG04__SI regDMIF_DEBUG04__SI; -typedef union DMIF_DEBUG05__SI regDMIF_DEBUG05__SI; -typedef union DMIF_HW_DEBUG__SI regDMIF_HW_DEBUG__SI; -typedef union DMIF_MULTI_CHIP_CNTL__SI regDMIF_MULTI_CHIP_CNTL__SI; -typedef union DMIF_STATUS__SI regDMIF_STATUS__SI; -typedef union DMIF_TEST_DEBUG_DATA__SI regDMIF_TEST_DEBUG_DATA__SI; -typedef union DMIF_TEST_DEBUG_INDEX__SI regDMIF_TEST_DEBUG_INDEX__SI; -typedef union DOUT_DEBUG__SI regDOUT_DEBUG__SI; -typedef union DOUT_POWER_MANAGEMENT_CNTL__SI regDOUT_POWER_MANAGEMENT_CNTL__SI; -typedef union DOUT_SCRATCH0__SI regDOUT_SCRATCH0__SI; -typedef union DOUT_SCRATCH1__SI regDOUT_SCRATCH1__SI; -typedef union DOUT_SCRATCH2__SI regDOUT_SCRATCH2__SI; -typedef union DOUT_SCRATCH3__SI regDOUT_SCRATCH3__SI; -typedef union DOUT_SCRATCH4__SI regDOUT_SCRATCH4__SI; -typedef union DOUT_SCRATCH5__SI regDOUT_SCRATCH5__SI; -typedef union DOUT_SCRATCH6__SI regDOUT_SCRATCH6__SI; -typedef union DOUT_SCRATCH7__SI regDOUT_SCRATCH7__SI; -typedef union DOUT_TEST_DEBUG_DATA__SI regDOUT_TEST_DEBUG_DATA__SI; -typedef union DOUT_TEST_DEBUG_INDEX__SI regDOUT_TEST_DEBUG_INDEX__SI; -typedef union DP_AUX1_DEBUG_A__SI regDP_AUX1_DEBUG_A__SI; -typedef union DP_AUX1_DEBUG_B__SI regDP_AUX1_DEBUG_B__SI; -typedef union DP_AUX1_DEBUG_C__SI regDP_AUX1_DEBUG_C__SI; -typedef union DP_AUX1_DEBUG_D__SI regDP_AUX1_DEBUG_D__SI; -typedef union DP_AUX1_DEBUG_E__SI regDP_AUX1_DEBUG_E__SI; -typedef union DP_AUX1_DEBUG_F__SI regDP_AUX1_DEBUG_F__SI; -typedef union DP_AUX1_DEBUG_G__SI regDP_AUX1_DEBUG_G__SI; -typedef union DP_AUX1_DEBUG_H__SI regDP_AUX1_DEBUG_H__SI; -typedef union DP_AUX1_DEBUG_I__SI regDP_AUX1_DEBUG_I__SI; -typedef union DP_AUX2_DEBUG_A__SI regDP_AUX2_DEBUG_A__SI; -typedef union DP_AUX2_DEBUG_B__SI regDP_AUX2_DEBUG_B__SI; -typedef union DP_AUX2_DEBUG_C__SI regDP_AUX2_DEBUG_C__SI; -typedef union DP_AUX2_DEBUG_D__SI regDP_AUX2_DEBUG_D__SI; -typedef union DP_AUX2_DEBUG_E__SI regDP_AUX2_DEBUG_E__SI; -typedef union DP_AUX2_DEBUG_F__SI regDP_AUX2_DEBUG_F__SI; -typedef union DP_AUX2_DEBUG_G__SI regDP_AUX2_DEBUG_G__SI; -typedef union DP_AUX2_DEBUG_H__SI regDP_AUX2_DEBUG_H__SI; -typedef union DP_AUX2_DEBUG_I__SI regDP_AUX2_DEBUG_I__SI; -typedef union DP_AUX3_DEBUG_A__SI regDP_AUX3_DEBUG_A__SI; -typedef union DP_AUX3_DEBUG_B__SI regDP_AUX3_DEBUG_B__SI; -typedef union DP_AUX3_DEBUG_C__SI regDP_AUX3_DEBUG_C__SI; -typedef union DP_AUX3_DEBUG_D__SI regDP_AUX3_DEBUG_D__SI; -typedef union DP_AUX3_DEBUG_E__SI regDP_AUX3_DEBUG_E__SI; -typedef union DP_AUX3_DEBUG_F__SI regDP_AUX3_DEBUG_F__SI; -typedef union DP_AUX3_DEBUG_G__SI regDP_AUX3_DEBUG_G__SI; -typedef union DP_AUX3_DEBUG_H__SI regDP_AUX3_DEBUG_H__SI; -typedef union DP_AUX3_DEBUG_I__SI regDP_AUX3_DEBUG_I__SI; -typedef union DP_AUX4_DEBUG_A__SI regDP_AUX4_DEBUG_A__SI; -typedef union DP_AUX4_DEBUG_B__SI regDP_AUX4_DEBUG_B__SI; -typedef union DP_AUX4_DEBUG_C__SI regDP_AUX4_DEBUG_C__SI; -typedef union DP_AUX4_DEBUG_D__SI regDP_AUX4_DEBUG_D__SI; -typedef union DP_AUX4_DEBUG_E__SI regDP_AUX4_DEBUG_E__SI; -typedef union DP_AUX4_DEBUG_F__SI regDP_AUX4_DEBUG_F__SI; -typedef union DP_AUX4_DEBUG_G__SI regDP_AUX4_DEBUG_G__SI; -typedef union DP_AUX4_DEBUG_H__SI regDP_AUX4_DEBUG_H__SI; -typedef union DP_AUX4_DEBUG_I__SI regDP_AUX4_DEBUG_I__SI; -typedef union DP_AUX5_DEBUG_A__SI regDP_AUX5_DEBUG_A__SI; -typedef union DP_AUX5_DEBUG_B__SI regDP_AUX5_DEBUG_B__SI; -typedef union DP_AUX5_DEBUG_C__SI regDP_AUX5_DEBUG_C__SI; -typedef union DP_AUX5_DEBUG_D__SI regDP_AUX5_DEBUG_D__SI; -typedef union DP_AUX5_DEBUG_E__SI regDP_AUX5_DEBUG_E__SI; -typedef union DP_AUX5_DEBUG_F__SI regDP_AUX5_DEBUG_F__SI; -typedef union DP_AUX5_DEBUG_G__SI regDP_AUX5_DEBUG_G__SI; -typedef union DP_AUX5_DEBUG_H__SI regDP_AUX5_DEBUG_H__SI; -typedef union DP_AUX5_DEBUG_I__SI regDP_AUX5_DEBUG_I__SI; -typedef union DP_AUX6_DEBUG_A__SI regDP_AUX6_DEBUG_A__SI; -typedef union DP_AUX6_DEBUG_B__SI regDP_AUX6_DEBUG_B__SI; -typedef union DP_AUX6_DEBUG_C__SI regDP_AUX6_DEBUG_C__SI; -typedef union DP_AUX6_DEBUG_D__SI regDP_AUX6_DEBUG_D__SI; -typedef union DP_AUX6_DEBUG_E__SI regDP_AUX6_DEBUG_E__SI; -typedef union DP_AUX6_DEBUG_F__SI regDP_AUX6_DEBUG_F__SI; -typedef union DP_AUX6_DEBUG_G__SI regDP_AUX6_DEBUG_G__SI; -typedef union DP_AUX6_DEBUG_H__SI regDP_AUX6_DEBUG_H__SI; -typedef union DP_AUX6_DEBUG_I__SI regDP_AUX6_DEBUG_I__SI; -typedef union DP_CONFIG__SI regDP_CONFIG__SI; -typedef union DP_CP_DEBUG1__SI regDP_CP_DEBUG1__SI; -typedef union DP_CP_DEBUG2__SI regDP_CP_DEBUG2__SI; -typedef union DP_CP_LINK_VERIFICATION_PATTERN__SI regDP_CP_LINK_VERIFICATION_PATTERN__SI; -typedef union DP_DEBUG_A__SI regDP_DEBUG_A__SI; -typedef union DP_DEBUG_B__SI regDP_DEBUG_B__SI; -typedef union DP_DEBUG_C__SI regDP_DEBUG_C__SI; -typedef union DP_DEBUG_D__SI regDP_DEBUG_D__SI; -typedef union DP_DEBUG_E__SI regDP_DEBUG_E__SI; -typedef union DP_DEBUG_F__SI regDP_DEBUG_F__SI; -typedef union DP_DEBUG_G__SI regDP_DEBUG_G__SI; -typedef union DP_DEBUG_H__SI regDP_DEBUG_H__SI; -typedef union DP_DEBUG_ID__SI regDP_DEBUG_ID__SI; -typedef union DP_DEBUG_Q__SI regDP_DEBUG_Q__SI; -typedef union DP_DEBUG_R__SI regDP_DEBUG_R__SI; -typedef union DP_DPHY_8B10B_CNTL__SI regDP_DPHY_8B10B_CNTL__SI; -typedef union DP_DPHY_CNTL__SI regDP_DPHY_CNTL__SI; -typedef union DP_DPHY_CRC_CNTL__SI regDP_DPHY_CRC_CNTL__SI; -typedef union DP_DPHY_CRC_EN__SI regDP_DPHY_CRC_EN__SI; -typedef union DP_DPHY_CRC_RESULT__SI regDP_DPHY_CRC_RESULT__SI; -typedef union DP_DPHY_FAST_TRAINING__SI regDP_DPHY_FAST_TRAINING__SI; -typedef union DP_DPHY_INTERNAL_CTRL__SI regDP_DPHY_INTERNAL_CTRL__SI; -typedef union DP_DPHY_PRBS_CNTL__SI regDP_DPHY_PRBS_CNTL__SI; -typedef union DP_DPHY_SCRAM_CNTL__SI regDP_DPHY_SCRAM_CNTL__SI; -typedef union DP_DPHY_SYM__SI regDP_DPHY_SYM__SI; -typedef union DP_DPHY_TRAINING_PATTERN_SEL__SI regDP_DPHY_TRAINING_PATTERN_SEL__SI; -typedef union DP_DTO0_MODULO__SI regDP_DTO0_MODULO__SI; -typedef union DP_DTO0_PHASE__SI regDP_DTO0_PHASE__SI; -typedef union DP_DTO1_MODULO__SI regDP_DTO1_MODULO__SI; -typedef union DP_DTO1_PHASE__SI regDP_DTO1_PHASE__SI; -typedef union DP_DTO2_MODULO__SI regDP_DTO2_MODULO__SI; -typedef union DP_DTO2_PHASE__SI regDP_DTO2_PHASE__SI; -typedef union DP_DTO3_MODULO__SI regDP_DTO3_MODULO__SI; -typedef union DP_DTO3_PHASE__SI regDP_DTO3_PHASE__SI; -typedef union DP_DTO4_MODULO__SI regDP_DTO4_MODULO__SI; -typedef union DP_DTO4_PHASE__SI regDP_DTO4_PHASE__SI; -typedef union DP_DTO5_MODULO__SI regDP_DTO5_MODULO__SI; -typedef union DP_DTO5_PHASE__SI regDP_DTO5_PHASE__SI; -typedef union DP_IDLE_PATTERN_CNTL__SI regDP_IDLE_PATTERN_CNTL__SI; -typedef union DP_LINK_CNTL__SI regDP_LINK_CNTL__SI; -typedef union DP_PIXEL_FORMAT__SI regDP_PIXEL_FORMAT__SI; -typedef union DP_SEC_ACP_HEADER__SI regDP_SEC_ACP_HEADER__SI; -typedef union DP_SEC_AUD_M_READBACK__SI regDP_SEC_AUD_M_READBACK__SI; -typedef union DP_SEC_AUD_M__SI regDP_SEC_AUD_M__SI; -typedef union DP_SEC_AUD_N_READBACK__SI regDP_SEC_AUD_N_READBACK__SI; -typedef union DP_SEC_AUD_N__SI regDP_SEC_AUD_N__SI; -typedef union DP_SEC_CNTL__SI regDP_SEC_CNTL__SI; -typedef union DP_SEC_FRAMING1__SI regDP_SEC_FRAMING1__SI; -typedef union DP_SEC_FRAMING2__SI regDP_SEC_FRAMING2__SI; -typedef union DP_SEC_FRAMING3__SI regDP_SEC_FRAMING3__SI; -typedef union DP_SEC_FRAMING4__SI regDP_SEC_FRAMING4__SI; -typedef union DP_SEC_PACKET_CNTL__SI regDP_SEC_PACKET_CNTL__SI; -typedef union DP_SEC_TIMESTAMP__SI regDP_SEC_TIMESTAMP__SI; -typedef union DP_STEER_FIFO__SI regDP_STEER_FIFO__SI; -typedef union DP_TEST_DEBUG_DATA__SI regDP_TEST_DEBUG_DATA__SI; -typedef union DP_TEST_DEBUG_INDEX__SI regDP_TEST_DEBUG_INDEX__SI; -typedef union DP_VID_INTERRUPT_CNTL__SI regDP_VID_INTERRUPT_CNTL__SI; -typedef union DP_VID_MSA_VBID__SI regDP_VID_MSA_VBID__SI; -typedef union DP_VID_M__SI regDP_VID_M__SI; -typedef union DP_VID_N__SI regDP_VID_N__SI; -typedef union DP_VID_STREAM_CNTL__SI regDP_VID_STREAM_CNTL__SI; -typedef union DP_VID_TIMING__SI regDP_VID_TIMING__SI; -typedef union DRMDMA0_CONFIG__SI regDRMDMA0_CONFIG__SI; -typedef union DRMDMA1_CLK_CTRL__SI regDRMDMA1_CLK_CTRL__SI; -typedef union DRMDMA1_CNTL__SI regDRMDMA1_CNTL__SI; -typedef union DRMDMA1_CONFIG__SI regDRMDMA1_CONFIG__SI; -typedef union DRMDMA1_CONTEXT_CNTL__SI regDRMDMA1_CONTEXT_CNTL__SI; -typedef union DRMDMA1_CRC_VALUE__SI regDRMDMA1_CRC_VALUE__SI; -typedef union DRMDMA1_DRM1_CTRL__SI regDRMDMA1_DRM1_CTRL__SI; -typedef union DRMDMA1_DRM_COUNTERDATA0__SI regDRMDMA1_DRM_COUNTERDATA0__SI; -typedef union DRMDMA1_DRM_COUNTERDATA1__SI regDRMDMA1_DRM_COUNTERDATA1__SI; -typedef union DRMDMA1_DRM_COUNTERDATA2__SI regDRMDMA1_DRM_COUNTERDATA2__SI; -typedef union DRMDMA1_DRM_COUNTERDATA3__SI regDRMDMA1_DRM_COUNTERDATA3__SI; -typedef union DRMDMA1_DRM_COUNTERKEY0__SI regDRMDMA1_DRM_COUNTERKEY0__SI; -typedef union DRMDMA1_DRM_COUNTERKEY1__SI regDRMDMA1_DRM_COUNTERKEY1__SI; -typedef union DRMDMA1_DRM_COUNTERKEY2__SI regDRMDMA1_DRM_COUNTERKEY2__SI; -typedef union DRMDMA1_DRM_COUNTERKEY3__SI regDRMDMA1_DRM_COUNTERKEY3__SI; -typedef union DRMDMA1_DRM_IVLOAD0__SI regDRMDMA1_DRM_IVLOAD0__SI; -typedef union DRMDMA1_DRM_IVLOAD1__SI regDRMDMA1_DRM_IVLOAD1__SI; -typedef union DRMDMA1_DRM_IVLOAD2__SI regDRMDMA1_DRM_IVLOAD2__SI; -typedef union DRMDMA1_DRM_IVLOAD3__SI regDRMDMA1_DRM_IVLOAD3__SI; -typedef union DRMDMA1_DRM_IVLOAD4__SI regDRMDMA1_DRM_IVLOAD4__SI; -typedef union DRMDMA1_DRM_OFFSET__SI regDRMDMA1_DRM_OFFSET__SI; -typedef union DRMDMA1_DRM_UNROLLKEY__SI regDRMDMA1_DRM_UNROLLKEY__SI; -typedef union DRMDMA1_DRM_WRAPPEDKEY0__SI regDRMDMA1_DRM_WRAPPEDKEY0__SI; -typedef union DRMDMA1_DRM_WRAPPEDKEY1__SI regDRMDMA1_DRM_WRAPPEDKEY1__SI; -typedef union DRMDMA1_DRM_WRAPPEDKEY2__SI regDRMDMA1_DRM_WRAPPEDKEY2__SI; -typedef union DRMDMA1_DRM_WRAPPEDKEY3__SI regDRMDMA1_DRM_WRAPPEDKEY3__SI; -typedef union DRMDMA1_FAULT_ADDR_HI__SI regDRMDMA1_FAULT_ADDR_HI__SI; -typedef union DRMDMA1_FAULT_ADDR_LO__SI regDRMDMA1_FAULT_ADDR_LO__SI; -typedef union DRMDMA1_FIFO_CNTL__SI regDRMDMA1_FIFO_CNTL__SI; -typedef union DRMDMA1_IB_BASE_HI__SI regDRMDMA1_IB_BASE_HI__SI; -typedef union DRMDMA1_IB_BASE_LO__SI regDRMDMA1_IB_BASE_LO__SI; -typedef union DRMDMA1_IB_CNTL__SI regDRMDMA1_IB_CNTL__SI; -typedef union DRMDMA1_IB_OFFSET__SI regDRMDMA1_IB_OFFSET__SI; -typedef union DRMDMA1_IB_RPTR__SI regDRMDMA1_IB_RPTR__SI; -typedef union DRMDMA1_IB_SIZE__SI regDRMDMA1_IB_SIZE__SI; -typedef union DRMDMA1_PERF_CNTL__SI regDRMDMA1_PERF_CNTL__SI; -typedef union DRMDMA1_PERF_COUNT0__SI regDRMDMA1_PERF_COUNT0__SI; -typedef union DRMDMA1_PERF_COUNT1__SI regDRMDMA1_PERF_COUNT1__SI; -typedef union DRMDMA1_PREEMPT__SI regDRMDMA1_PREEMPT__SI; -typedef union DRMDMA1_PRIV_MODE__SI regDRMDMA1_PRIV_MODE__SI; -typedef union DRMDMA1_RB_BASE__SI regDRMDMA1_RB_BASE__SI; -typedef union DRMDMA1_RB_CNTL__SI regDRMDMA1_RB_CNTL__SI; -typedef union DRMDMA1_RB_RPTR_ADDR_HI__SI regDRMDMA1_RB_RPTR_ADDR_HI__SI; -typedef union DRMDMA1_RB_RPTR_ADDR_LO__SI regDRMDMA1_RB_RPTR_ADDR_LO__SI; -typedef union DRMDMA1_RB_RPTR__SI regDRMDMA1_RB_RPTR__SI; -typedef union DRMDMA1_RB_WPTR_POLL_ADDR_HI__SI regDRMDMA1_RB_WPTR_POLL_ADDR_HI__SI; -typedef union DRMDMA1_RB_WPTR_POLL_ADDR_LO__SI regDRMDMA1_RB_WPTR_POLL_ADDR_LO__SI; -typedef union DRMDMA1_RB_WPTR_POLL_CNTL__SI regDRMDMA1_RB_WPTR_POLL_CNTL__SI; -typedef union DRMDMA1_RB_WPTR__SI regDRMDMA1_RB_WPTR__SI; -typedef union DRMDMA1_SEM_INCOMPLETE_TIMER_CNTL__SI regDRMDMA1_SEM_INCOMPLETE_TIMER_CNTL__SI; -typedef union DRMDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SI regDRMDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SI; -typedef union DRMDMA1_STATUS_REG__SI regDRMDMA1_STATUS_REG__SI; -typedef union DRMDMA1_TILING_CONFIG__SI regDRMDMA1_TILING_CONFIG__SI; -typedef union DRMDMA_CLK_CTRL__SI regDRMDMA_CLK_CTRL__SI; -typedef union DRMDMA_CNTL__SI regDRMDMA_CNTL__SI; -typedef union DRMDMA_CONTEXT_CNTL__SI regDRMDMA_CONTEXT_CNTL__SI; -typedef union DRMDMA_CRC_VALUE__SI regDRMDMA_CRC_VALUE__SI; -typedef union DRMDMA_DRM1_CTRL__SI regDRMDMA_DRM1_CTRL__SI; -typedef union DRMDMA_DRM_COUNTERDATA0__SI regDRMDMA_DRM_COUNTERDATA0__SI; -typedef union DRMDMA_DRM_COUNTERDATA1__SI regDRMDMA_DRM_COUNTERDATA1__SI; -typedef union DRMDMA_DRM_COUNTERDATA2__SI regDRMDMA_DRM_COUNTERDATA2__SI; -typedef union DRMDMA_DRM_COUNTERDATA3__SI regDRMDMA_DRM_COUNTERDATA3__SI; -typedef union DRMDMA_DRM_COUNTERKEY0__SI regDRMDMA_DRM_COUNTERKEY0__SI; -typedef union DRMDMA_DRM_COUNTERKEY1__SI regDRMDMA_DRM_COUNTERKEY1__SI; -typedef union DRMDMA_DRM_COUNTERKEY2__SI regDRMDMA_DRM_COUNTERKEY2__SI; -typedef union DRMDMA_DRM_COUNTERKEY3__SI regDRMDMA_DRM_COUNTERKEY3__SI; -typedef union DRMDMA_DRM_IVLOAD0__SI regDRMDMA_DRM_IVLOAD0__SI; -typedef union DRMDMA_DRM_IVLOAD1__SI regDRMDMA_DRM_IVLOAD1__SI; -typedef union DRMDMA_DRM_IVLOAD2__SI regDRMDMA_DRM_IVLOAD2__SI; -typedef union DRMDMA_DRM_IVLOAD3__SI regDRMDMA_DRM_IVLOAD3__SI; -typedef union DRMDMA_DRM_IVLOAD4__SI regDRMDMA_DRM_IVLOAD4__SI; -typedef union DRMDMA_DRM_OFFSET__SI regDRMDMA_DRM_OFFSET__SI; -typedef union DRMDMA_DRM_UNROLLKEY__SI regDRMDMA_DRM_UNROLLKEY__SI; -typedef union DRMDMA_DRM_WRAPPEDKEY0__SI regDRMDMA_DRM_WRAPPEDKEY0__SI; -typedef union DRMDMA_DRM_WRAPPEDKEY1__SI regDRMDMA_DRM_WRAPPEDKEY1__SI; -typedef union DRMDMA_DRM_WRAPPEDKEY2__SI regDRMDMA_DRM_WRAPPEDKEY2__SI; -typedef union DRMDMA_DRM_WRAPPEDKEY3__SI regDRMDMA_DRM_WRAPPEDKEY3__SI; -typedef union DRMDMA_FAULT_ADDR_HI__SI regDRMDMA_FAULT_ADDR_HI__SI; -typedef union DRMDMA_FAULT_ADDR_LO__SI regDRMDMA_FAULT_ADDR_LO__SI; -typedef union DRMDMA_FIFO_CNTL__SI regDRMDMA_FIFO_CNTL__SI; -typedef union DRMDMA_IB_BASE_HI__SI regDRMDMA_IB_BASE_HI__SI; -typedef union DRMDMA_IB_BASE_LO__SI regDRMDMA_IB_BASE_LO__SI; -typedef union DRMDMA_IB_CNTL__SI regDRMDMA_IB_CNTL__SI; -typedef union DRMDMA_IB_OFFSET__SI regDRMDMA_IB_OFFSET__SI; -typedef union DRMDMA_IB_RPTR__SI regDRMDMA_IB_RPTR__SI; -typedef union DRMDMA_IB_SIZE__SI regDRMDMA_IB_SIZE__SI; -typedef union DRMDMA_PERF_CNTL__SI regDRMDMA_PERF_CNTL__SI; -typedef union DRMDMA_PERF_COUNT0__SI regDRMDMA_PERF_COUNT0__SI; -typedef union DRMDMA_PERF_COUNT1__SI regDRMDMA_PERF_COUNT1__SI; -typedef union DRMDMA_PREEMPT__SI regDRMDMA_PREEMPT__SI; -typedef union DRMDMA_PRIV_MODE__SI regDRMDMA_PRIV_MODE__SI; -typedef union DRMDMA_RB_BASE__SI regDRMDMA_RB_BASE__SI; -typedef union DRMDMA_RB_CNTL__SI regDRMDMA_RB_CNTL__SI; -typedef union DRMDMA_RB_RPTR_ADDR_HI__SI regDRMDMA_RB_RPTR_ADDR_HI__SI; -typedef union DRMDMA_RB_RPTR_ADDR_LO__SI regDRMDMA_RB_RPTR_ADDR_LO__SI; -typedef union DRMDMA_RB_RPTR__SI regDRMDMA_RB_RPTR__SI; -typedef union DRMDMA_RB_WPTR_POLL_ADDR_HI__SI regDRMDMA_RB_WPTR_POLL_ADDR_HI__SI; -typedef union DRMDMA_RB_WPTR_POLL_ADDR_LO__SI regDRMDMA_RB_WPTR_POLL_ADDR_LO__SI; -typedef union DRMDMA_RB_WPTR_POLL_CNTL__SI regDRMDMA_RB_WPTR_POLL_CNTL__SI; -typedef union DRMDMA_RB_WPTR__SI regDRMDMA_RB_WPTR__SI; -typedef union DRMDMA_SEM_INCOMPLETE_TIMER_CNTL__SI regDRMDMA_SEM_INCOMPLETE_TIMER_CNTL__SI; -typedef union DRMDMA_SEM_WAIT_FAIL_TIMER_CNTL__SI regDRMDMA_SEM_WAIT_FAIL_TIMER_CNTL__SI; -typedef union DRMDMA_STATUS_REG__SI regDRMDMA_STATUS_REG__SI; -typedef union DRMDMA_TILING_CONFIG__SI regDRMDMA_TILING_CONFIG__SI; -typedef union DRM_ARB_PRIORITY regDRM_ARB_PRIORITY; -typedef union DRM_BYTESWAP regDRM_BYTESWAP; -typedef union DRM_DEBUG regDRM_DEBUG; -typedef union DRM_DEBUG_ID__SI regDRM_DEBUG_ID__SI; -typedef union DRM_DEBUG_INDEX0__SI regDRM_DEBUG_INDEX0__SI; -typedef union DRM_DEBUG_INDEX1__SI regDRM_DEBUG_INDEX1__SI; -typedef union DRM_DEBUG_INDEX2__SI regDRM_DEBUG_INDEX2__SI; -typedef union DRM_DEBUG_INDEX3__SI regDRM_DEBUG_INDEX3__SI; -typedef union DRM_DEBUG_INDEX4__SI regDRM_DEBUG_INDEX4__SI; -typedef union DRM_DEBUG_INDEX5__SI regDRM_DEBUG_INDEX5__SI; -typedef union DRM_DEBUG_INDEX6__SI regDRM_DEBUG_INDEX6__SI; -typedef union DRM_DEBUG_INDEX7__SI regDRM_DEBUG_INDEX7__SI; -typedef union DRM_HFS_CONT regDRM_HFS_CONT; -typedef union DRM_HFS_HW_NONCE0 regDRM_HFS_HW_NONCE0; -typedef union DRM_HFS_HW_NONCE1 regDRM_HFS_HW_NONCE1; -typedef union DRM_HFS_HW_NONCE2 regDRM_HFS_HW_NONCE2; -typedef union DRM_HFS_HW_NONCE3 regDRM_HFS_HW_NONCE3; -typedef union DRM_HFS_HW_RESULT0 regDRM_HFS_HW_RESULT0; -typedef union DRM_HFS_HW_RESULT1 regDRM_HFS_HW_RESULT1; -typedef union DRM_HFS_HW_RESULT2 regDRM_HFS_HW_RESULT2; -typedef union DRM_HFS_HW_RESULT3 regDRM_HFS_HW_RESULT3; -typedef union DRM_HFS_SECRET_SEL regDRM_HFS_SECRET_SEL; -typedef union DRM_HFS_START regDRM_HFS_START; -typedef union DRM_HFS_SW_NONCE0 regDRM_HFS_SW_NONCE0; -typedef union DRM_HFS_SW_NONCE1 regDRM_HFS_SW_NONCE1; -typedef union DRM_HFS_SW_NONCE2 regDRM_HFS_SW_NONCE2; -typedef union DRM_HFS_SW_NONCE3 regDRM_HFS_SW_NONCE3; -typedef union DRM_HFS_SW_RESULT0 regDRM_HFS_SW_RESULT0; -typedef union DRM_HFS_SW_RESULT1 regDRM_HFS_SW_RESULT1; -typedef union DRM_HFS_SW_RESULT2 regDRM_HFS_SW_RESULT2; -typedef union DRM_HFS_SW_RESULT3 regDRM_HFS_SW_RESULT3; -typedef union DRM_ID_EFUSE regDRM_ID_EFUSE; -typedef union DRM_IH_CREDITS regDRM_IH_CREDITS; -typedef union DRM_INT_ACK regDRM_INT_ACK; -typedef union DRM_INT_MASK regDRM_INT_MASK; -typedef union DRM_INT_STATUS regDRM_INT_STATUS; -typedef union DRM_KEYGEN_CONT regDRM_KEYGEN_CONT; -typedef union DRM_KEYGEN_RADDR regDRM_KEYGEN_RADDR; -typedef union DRM_KEYGEN_RDATA regDRM_KEYGEN_RDATA; -typedef union DRM_KEYGEN_START regDRM_KEYGEN_START; -typedef union DRM_KEYGEN_WADDR regDRM_KEYGEN_WADDR; -typedef union DRM_KEYGEN_WDATA regDRM_KEYGEN_WDATA; -typedef union DRM_PERFCOUNTER1_HI regDRM_PERFCOUNTER1_HI; -typedef union DRM_PERFCOUNTER1_LO regDRM_PERFCOUNTER1_LO; -typedef union DRM_PERFCOUNTER1_SELECT regDRM_PERFCOUNTER1_SELECT; -typedef union DRM_PERFCOUNTER2_HI regDRM_PERFCOUNTER2_HI; -typedef union DRM_PERFCOUNTER2_LO regDRM_PERFCOUNTER2_LO; -typedef union DRM_PERFCOUNTER2_SELECT regDRM_PERFCOUNTER2_SELECT; -typedef union DRM_PERFMON_CNTL regDRM_PERFMON_CNTL; -typedef union DRM_PROTO_ADDR regDRM_PROTO_ADDR; -typedef union DRM_PROTO_DATA regDRM_PROTO_DATA; -typedef union DRM_RESET regDRM_RESET; -typedef union DRM_SIG_FINISH regDRM_SIG_FINISH; -typedef union DRM_SIG_INVALID regDRM_SIG_INVALID; -typedef union DRM_SIG_RADDR regDRM_SIG_RADDR; -typedef union DRM_SIG_RDATA regDRM_SIG_RDATA; -typedef union DRM_SIG_RESULT0 regDRM_SIG_RESULT0; -typedef union DRM_SIG_RESULT1 regDRM_SIG_RESULT1; -typedef union DRM_SIG_RESULT2 regDRM_SIG_RESULT2; -typedef union DRM_SIG_RESULT3 regDRM_SIG_RESULT3; -typedef union DRM_SIG_START regDRM_SIG_START; -typedef union DRM_STATUS regDRM_STATUS; -typedef union DRM_TIMEOUT regDRM_TIMEOUT; -typedef union DRM_TRNG_CNTL regDRM_TRNG_CNTL; -typedef union DRM_TRNG_DATA regDRM_TRNG_DATA; -typedef union DTO_VCLK_DENOMIN__SI regDTO_VCLK_DENOMIN__SI; -typedef union DTO_VCLK_INC_CORR__SI regDTO_VCLK_INC_CORR__SI; -typedef union DTO_VCLK_INC__SI regDTO_VCLK_INC__SI; -typedef union DVOACLKC_CNTL__SI regDVOACLKC_CNTL__SI; -typedef union DVOACLKC_MVP_CNTL__SI regDVOACLKC_MVP_CNTL__SI; -typedef union DVOACLKD_CNTL__SI regDVOACLKD_CNTL__SI; -typedef union DVOA_DEBUG3__SI regDVOA_DEBUG3__SI; -typedef union DVOA_DEBUG4__SI regDVOA_DEBUG4__SI; -typedef union DVOA_DEBUG5__SI regDVOA_DEBUG5__SI; -typedef union DVOA_DEBUG6__SI regDVOA_DEBUG6__SI; -typedef union DVOA_DEBUG7__SI regDVOA_DEBUG7__SI; -typedef union DVO_CONTROL__SI regDVO_CONTROL__SI; -typedef union DVO_CRC2_SIG_MASK__SI regDVO_CRC2_SIG_MASK__SI; -typedef union DVO_CRC2_SIG_RESULT__SI regDVO_CRC2_SIG_RESULT__SI; -typedef union DVO_CRC_EN__SI regDVO_CRC_EN__SI; -typedef union DVO_ENABLE__SI regDVO_ENABLE__SI; -typedef union DVO_OUTPUT__SI regDVO_OUTPUT__SI; -typedef union DVO_SOURCE_SELECT__SI regDVO_SOURCE_SELECT__SI; -typedef union DVO_STRENGTH_CONTROL__SI regDVO_STRENGTH_CONTROL__SI; -typedef union EFUSE_STATUS__CI regEFUSE_STATUS__CI; -typedef union EXP0 regEXP0; -typedef union EXP1 regEXP1; -typedef union EXP2 regEXP2; -typedef union EXP3 regEXP3; -typedef union EXP4 regEXP4; -typedef union EXP5 regEXP5; -typedef union EXP6 regEXP6; -typedef union EXP7 regEXP7; -typedef union EXT1_DIFF_POST_DIV_CNTL__SI regEXT1_DIFF_POST_DIV_CNTL__SI; -typedef union EXT1_PPLL_CNTL__SI regEXT1_PPLL_CNTL__SI; -typedef union EXT1_PPLL_FB_DIV__SI regEXT1_PPLL_FB_DIV__SI; -typedef union EXT1_PPLL_POST_DIV_SRC__SI regEXT1_PPLL_POST_DIV_SRC__SI; -typedef union EXT1_PPLL_POST_DIV__SI regEXT1_PPLL_POST_DIV__SI; -typedef union EXT1_PPLL_REF_DIV_SRC__SI regEXT1_PPLL_REF_DIV_SRC__SI; -typedef union EXT1_PPLL_REF_DIV__SI regEXT1_PPLL_REF_DIV__SI; -typedef union EXT1_PPLL_UPDATE_CNTL__SI regEXT1_PPLL_UPDATE_CNTL__SI; -typedef union EXT1_PPLL_UPDATE_LOCK__SI regEXT1_PPLL_UPDATE_LOCK__SI; -typedef union EXT2_DIFF_POST_DIV_CNTL__SI regEXT2_DIFF_POST_DIV_CNTL__SI; -typedef union EXT2_PPLL_CNTL__SI regEXT2_PPLL_CNTL__SI; -typedef union EXT2_PPLL_FB_DIV__SI regEXT2_PPLL_FB_DIV__SI; -typedef union EXT2_PPLL_POST_DIV_SRC__SI regEXT2_PPLL_POST_DIV_SRC__SI; -typedef union EXT2_PPLL_POST_DIV__SI regEXT2_PPLL_POST_DIV__SI; -typedef union EXT2_PPLL_REF_DIV_SRC__SI regEXT2_PPLL_REF_DIV_SRC__SI; -typedef union EXT2_PPLL_REF_DIV__SI regEXT2_PPLL_REF_DIV__SI; -typedef union EXT2_PPLL_UPDATE_CNTL__SI regEXT2_PPLL_UPDATE_CNTL__SI; -typedef union EXT2_PPLL_UPDATE_LOCK__SI regEXT2_PPLL_UPDATE_LOCK__SI; -typedef union EXTERN_TRIG_CNTL__SI regEXTERN_TRIG_CNTL__SI; -typedef union EXT_OVERSCAN_LEFT_RIGHT__SI regEXT_OVERSCAN_LEFT_RIGHT__SI; -typedef union EXT_OVERSCAN_TOP_BOTTOM__SI regEXT_OVERSCAN_TOP_BOTTOM__SI; -typedef union FAST_AES0 regFAST_AES0; -typedef union FAST_AES1 regFAST_AES1; -typedef union FAST_AES2 regFAST_AES2; -typedef union FAST_AES3 regFAST_AES3; -typedef union FAST_AES4 regFAST_AES4; -typedef union FAST_AES5 regFAST_AES5; -typedef union FAST_AES6 regFAST_AES6; -typedef union FAST_AES7 regFAST_AES7; -typedef union FBC_CLIENT_REGION_MASK__SI regFBC_CLIENT_REGION_MASK__SI; -typedef union FBC_CNTL__SI regFBC_CNTL__SI; -typedef union FBC_COMP_CNTL__SI regFBC_COMP_CNTL__SI; -typedef union FBC_COMP_MODE__SI regFBC_COMP_MODE__SI; -typedef union FBC_CSM_REGION_OFFSET_01__SI regFBC_CSM_REGION_OFFSET_01__SI; -typedef union FBC_CSM_REGION_OFFSET_23__SI regFBC_CSM_REGION_OFFSET_23__SI; -typedef union FBC_DEBUG0__SI regFBC_DEBUG0__SI; -typedef union FBC_DEBUG1__SI regFBC_DEBUG1__SI; -typedef union FBC_DEBUG2__SI regFBC_DEBUG2__SI; -typedef union FBC_DEBUG_COMP__SI regFBC_DEBUG_COMP__SI; -typedef union FBC_DEBUG_CSR_RDATA__SI regFBC_DEBUG_CSR_RDATA__SI; -typedef union FBC_DEBUG_CSR_WDATA__SI regFBC_DEBUG_CSR_WDATA__SI; -typedef union FBC_DEBUG_CSR__SI regFBC_DEBUG_CSR__SI; -typedef union FBC_IDLE_FORCE_CLEAR_MASK__SI regFBC_IDLE_FORCE_CLEAR_MASK__SI; -typedef union FBC_IDLE_MASK__SI regFBC_IDLE_MASK__SI; -typedef union FBC_IND_LUT0__SI regFBC_IND_LUT0__SI; -typedef union FBC_IND_LUT10__SI regFBC_IND_LUT10__SI; -typedef union FBC_IND_LUT11__SI regFBC_IND_LUT11__SI; -typedef union FBC_IND_LUT12__SI regFBC_IND_LUT12__SI; -typedef union FBC_IND_LUT13__SI regFBC_IND_LUT13__SI; -typedef union FBC_IND_LUT14__SI regFBC_IND_LUT14__SI; -typedef union FBC_IND_LUT15__SI regFBC_IND_LUT15__SI; -typedef union FBC_IND_LUT1__SI regFBC_IND_LUT1__SI; -typedef union FBC_IND_LUT2__SI regFBC_IND_LUT2__SI; -typedef union FBC_IND_LUT3__SI regFBC_IND_LUT3__SI; -typedef union FBC_IND_LUT4__SI regFBC_IND_LUT4__SI; -typedef union FBC_IND_LUT5__SI regFBC_IND_LUT5__SI; -typedef union FBC_IND_LUT6__SI regFBC_IND_LUT6__SI; -typedef union FBC_IND_LUT7__SI regFBC_IND_LUT7__SI; -typedef union FBC_IND_LUT8__SI regFBC_IND_LUT8__SI; -typedef union FBC_IND_LUT9__SI regFBC_IND_LUT9__SI; -typedef union FBC_MISC__SI regFBC_MISC__SI; -typedef union FBC_START_STOP_DELAY__SI regFBC_START_STOP_DELAY__SI; -typedef union FBC_TEST_DEBUG_DATA__SI regFBC_TEST_DEBUG_DATA__SI; -typedef union FBC_TEST_DEBUG_INDEX__SI regFBC_TEST_DEBUG_INDEX__SI; -typedef union FIRMWARE_FLAGS__CI regFIRMWARE_FLAGS__CI; -typedef union FMT_BIT_DEPTH_CONTROL__SI regFMT_BIT_DEPTH_CONTROL__SI; -typedef union FMT_CLAMP_CNTL__SI regFMT_CLAMP_CNTL__SI; -typedef union FMT_CONTROL__SI regFMT_CONTROL__SI; -typedef union FMT_CRC_CNTL__SI regFMT_CRC_CNTL__SI; -typedef union FMT_CRC_SIG_BLUE_CONTROL_MASK__SI regFMT_CRC_SIG_BLUE_CONTROL_MASK__SI; -typedef union FMT_CRC_SIG_BLUE_CONTROL__SI regFMT_CRC_SIG_BLUE_CONTROL__SI; -typedef union FMT_CRC_SIG_RED_GREEN_MASK__SI regFMT_CRC_SIG_RED_GREEN_MASK__SI; -typedef union FMT_CRC_SIG_RED_GREEN__SI regFMT_CRC_SIG_RED_GREEN__SI; -typedef union FMT_DEBUG_CNTL__SI regFMT_DEBUG_CNTL__SI; -typedef union FMT_DITHER_RAND_B_SEED__SI regFMT_DITHER_RAND_B_SEED__SI; -typedef union FMT_DITHER_RAND_G_SEED__SI regFMT_DITHER_RAND_G_SEED__SI; -typedef union FMT_DITHER_RAND_R_SEED__SI regFMT_DITHER_RAND_R_SEED__SI; -typedef union FMT_DYNAMIC_EXP_CNTL__SI regFMT_DYNAMIC_EXP_CNTL__SI; -typedef union FMT_FORCE_DATA_0_1__SI regFMT_FORCE_DATA_0_1__SI; -typedef union FMT_FORCE_DATA_2_3__SI regFMT_FORCE_DATA_2_3__SI; -typedef union FMT_FORCE_OUTPUT_CNTL__SI regFMT_FORCE_OUTPUT_CNTL__SI; -typedef union FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI regFMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI; -typedef union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI - regFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI; -typedef union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI - regFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI; -typedef union FREQ_CHANGE_TIMEOUT__SI regFREQ_CHANGE_TIMEOUT__SI; -typedef union FWD_CHROMA_BOT_ADDR__SI regFWD_CHROMA_BOT_ADDR__SI; -typedef union FWD_CHROMA_TOP_ADDR__SI regFWD_CHROMA_TOP_ADDR__SI; -typedef union FWD_LUMA_BOT_ADDR__SI regFWD_LUMA_BOT_ADDR__SI; -typedef union FWD_LUMA_TOP_ADDR__SI regFWD_LUMA_TOP_ADDR__SI; -typedef union FW_CHRONO_31_0__CI__VI regFW_CHRONO_31_0__CI__VI; -typedef union FW_CHRONO_63_32__CI__VI regFW_CHRONO_63_32__CI__VI; -typedef union FW_DBG_COUNTER_1__CI__VI regFW_DBG_COUNTER_1__CI__VI; -typedef union FW_DBG_COUNTER_2__CI__VI regFW_DBG_COUNTER_2__CI__VI; -typedef union FW_DBG_SIGNAL_1__CI__VI regFW_DBG_SIGNAL_1__CI__VI; -typedef union FW_DBG_SIGNAL_2__CI__VI regFW_DBG_SIGNAL_2__CI__VI; -typedef union FW_PC_WATCH_1__CI__VI regFW_PC_WATCH_1__CI__VI; -typedef union FW_PC_WATCH_2__CI__VI regFW_PC_WATCH_2__CI__VI; -typedef union FW_PC_WATCH_3__CI__VI regFW_PC_WATCH_3__CI__VI; -typedef union FW_PC_WATCH_4__CI__VI regFW_PC_WATCH_4__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_0__CI__VI regGARLIC_FLUSH_ADDR_END_0__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_1__CI__VI regGARLIC_FLUSH_ADDR_END_1__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_2__CI__VI regGARLIC_FLUSH_ADDR_END_2__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_3__CI__VI regGARLIC_FLUSH_ADDR_END_3__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_4__CI__VI regGARLIC_FLUSH_ADDR_END_4__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_5__CI__VI regGARLIC_FLUSH_ADDR_END_5__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_6__CI__VI regGARLIC_FLUSH_ADDR_END_6__CI__VI; -typedef union GARLIC_FLUSH_ADDR_END_7__CI__VI regGARLIC_FLUSH_ADDR_END_7__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_0__CI__VI regGARLIC_FLUSH_ADDR_START_0__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_1__CI__VI regGARLIC_FLUSH_ADDR_START_1__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_2__CI__VI regGARLIC_FLUSH_ADDR_START_2__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_3__CI__VI regGARLIC_FLUSH_ADDR_START_3__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_4__CI__VI regGARLIC_FLUSH_ADDR_START_4__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_5__CI__VI regGARLIC_FLUSH_ADDR_START_5__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_6__CI__VI regGARLIC_FLUSH_ADDR_START_6__CI__VI; -typedef union GARLIC_FLUSH_ADDR_START_7__CI__VI regGARLIC_FLUSH_ADDR_START_7__CI__VI; -typedef union GARLIC_FLUSH_CNTL__CI regGARLIC_FLUSH_CNTL__CI; -typedef union GARLIC_FLUSH_CNTL__VI regGARLIC_FLUSH_CNTL__VI; -typedef union GARLIC_FLUSH_REQ__CI__VI regGARLIC_FLUSH_REQ__CI__VI; -typedef union GB_ADDR_CONFIG regGB_ADDR_CONFIG; -typedef union GB_BACKEND_MAP regGB_BACKEND_MAP; -typedef union GB_EDC_MODE regGB_EDC_MODE; -typedef union GB_GPU_ID regGB_GPU_ID; -typedef union GB_MACROTILE_MODE0__CI__VI regGB_MACROTILE_MODE0__CI__VI; -typedef union GB_MACROTILE_MODE10__CI__VI regGB_MACROTILE_MODE10__CI__VI; -typedef union GB_MACROTILE_MODE11__CI__VI regGB_MACROTILE_MODE11__CI__VI; -typedef union GB_MACROTILE_MODE12__CI__VI regGB_MACROTILE_MODE12__CI__VI; -typedef union GB_MACROTILE_MODE13__CI__VI regGB_MACROTILE_MODE13__CI__VI; -typedef union GB_MACROTILE_MODE14__CI__VI regGB_MACROTILE_MODE14__CI__VI; -typedef union GB_MACROTILE_MODE15__CI__VI regGB_MACROTILE_MODE15__CI__VI; -typedef union GB_MACROTILE_MODE1__CI__VI regGB_MACROTILE_MODE1__CI__VI; -typedef union GB_MACROTILE_MODE2__CI__VI regGB_MACROTILE_MODE2__CI__VI; -typedef union GB_MACROTILE_MODE3__CI__VI regGB_MACROTILE_MODE3__CI__VI; -typedef union GB_MACROTILE_MODE4__CI__VI regGB_MACROTILE_MODE4__CI__VI; -typedef union GB_MACROTILE_MODE5__CI__VI regGB_MACROTILE_MODE5__CI__VI; -typedef union GB_MACROTILE_MODE6__CI__VI regGB_MACROTILE_MODE6__CI__VI; -typedef union GB_MACROTILE_MODE7__CI__VI regGB_MACROTILE_MODE7__CI__VI; -typedef union GB_MACROTILE_MODE8__CI__VI regGB_MACROTILE_MODE8__CI__VI; -typedef union GB_MACROTILE_MODE9__CI__VI regGB_MACROTILE_MODE9__CI__VI; -typedef union GB_TILE_MODE0 regGB_TILE_MODE0; -typedef union GB_TILE_MODE1 regGB_TILE_MODE1; -typedef union GB_TILE_MODE10 regGB_TILE_MODE10; -typedef union GB_TILE_MODE11 regGB_TILE_MODE11; -typedef union GB_TILE_MODE12 regGB_TILE_MODE12; -typedef union GB_TILE_MODE13 regGB_TILE_MODE13; -typedef union GB_TILE_MODE14 regGB_TILE_MODE14; -typedef union GB_TILE_MODE15 regGB_TILE_MODE15; -typedef union GB_TILE_MODE16 regGB_TILE_MODE16; -typedef union GB_TILE_MODE17 regGB_TILE_MODE17; -typedef union GB_TILE_MODE18 regGB_TILE_MODE18; -typedef union GB_TILE_MODE19 regGB_TILE_MODE19; -typedef union GB_TILE_MODE2 regGB_TILE_MODE2; -typedef union GB_TILE_MODE20 regGB_TILE_MODE20; -typedef union GB_TILE_MODE21 regGB_TILE_MODE21; -typedef union GB_TILE_MODE22 regGB_TILE_MODE22; -typedef union GB_TILE_MODE23 regGB_TILE_MODE23; -typedef union GB_TILE_MODE24 regGB_TILE_MODE24; -typedef union GB_TILE_MODE25 regGB_TILE_MODE25; -typedef union GB_TILE_MODE26 regGB_TILE_MODE26; -typedef union GB_TILE_MODE27 regGB_TILE_MODE27; -typedef union GB_TILE_MODE28 regGB_TILE_MODE28; -typedef union GB_TILE_MODE29 regGB_TILE_MODE29; -typedef union GB_TILE_MODE3 regGB_TILE_MODE3; -typedef union GB_TILE_MODE30 regGB_TILE_MODE30; -typedef union GB_TILE_MODE31 regGB_TILE_MODE31; -typedef union GB_TILE_MODE4 regGB_TILE_MODE4; -typedef union GB_TILE_MODE5 regGB_TILE_MODE5; -typedef union GB_TILE_MODE6 regGB_TILE_MODE6; -typedef union GB_TILE_MODE7 regGB_TILE_MODE7; -typedef union GB_TILE_MODE8 regGB_TILE_MODE8; -typedef union GB_TILE_MODE9 regGB_TILE_MODE9; -typedef union GCK_ACLK_FUSES__CI__VI regGCK_ACLK_FUSES__CI__VI; -typedef union GCK_DCLK_FUSES__CI__VI regGCK_DCLK_FUSES__CI__VI; -typedef union GCK_DISPCLK_FUSES__CI__VI regGCK_DISPCLK_FUSES__CI__VI; -typedef union GCK_DPREFCLK_FUSES__CI__VI regGCK_DPREFCLK_FUSES__CI__VI; -typedef union GCK_ECLK_FUSES__CI__VI regGCK_ECLK_FUSES__CI__VI; -typedef union GCK_GPUPLL_DGCK_CNTL_2__CI__VI regGCK_GPUPLL_DGCK_CNTL_2__CI__VI; -typedef union GCK_GPUPLL_DGCK_CNTL_4__CI regGCK_GPUPLL_DGCK_CNTL_4__CI; -typedef union GCK_GPUPLL_DGCK_CNTL_4__VI regGCK_GPUPLL_DGCK_CNTL_4__VI; -typedef union GCK_GPUPLL_DGCK_CNTL_5__CI__VI regGCK_GPUPLL_DGCK_CNTL_5__CI__VI; -typedef union GCK_GPUPLL_DGCK_CNTL__CI regGCK_GPUPLL_DGCK_CNTL__CI; -typedef union GCK_GPUPLL_DGCK_CNTL__VI regGCK_GPUPLL_DGCK_CNTL__VI; -typedef union GCK_GPUPLL_SPREAD_SPECTRUM_2__CI__VI regGCK_GPUPLL_SPREAD_SPECTRUM_2__CI__VI; -typedef union GCK_GPUPLL_SPREAD_SPECTRUM__CI regGCK_GPUPLL_SPREAD_SPECTRUM__CI; -typedef union GCK_GPUPLL_SPREAD_SPECTRUM__VI regGCK_GPUPLL_SPREAD_SPECTRUM__VI; -typedef union GCK_GPUPLL_STATUS__CI regGCK_GPUPLL_STATUS__CI; -typedef union GCK_GPUPLL_STATUS__VI regGCK_GPUPLL_STATUS__VI; -typedef union GCK_MISC_2__CI__VI regGCK_MISC_2__CI__VI; -typedef union GCK_MISC_FUSES__CI__VI regGCK_MISC_FUSES__CI__VI; -typedef union GCK_MISC__CI regGCK_MISC__CI; -typedef union GCK_MISC__VI regGCK_MISC__VI; -typedef union GCK_PLL_CONTROL__CI__VI regGCK_PLL_CONTROL__CI__VI; -typedef union GCK_PLL_DGCK_CNTL__CI__VI regGCK_PLL_DGCK_CNTL__CI__VI; -typedef union GCK_PLL_FUSES__CI__VI regGCK_PLL_FUSES__CI__VI; -typedef union GCK_PLL_TEST_CNTL__CI regGCK_PLL_TEST_CNTL__CI; -typedef union GCK_PLL_TEST_CNTL__VI regGCK_PLL_TEST_CNTL__VI; -typedef union GCK_SAMCLK_FUSES__CI__VI regGCK_SAMCLK_FUSES__CI__VI; -typedef union GCK_SCLK_FUSES__CI__VI regGCK_SCLK_FUSES__CI__VI; -typedef union GCK_SMC_IND_DATA__CI__VI regGCK_SMC_IND_DATA__CI__VI; -typedef union GCK_SMC_IND_INDEX__CI__VI regGCK_SMC_IND_INDEX__CI__VI; -typedef union GCK_SPLL_FUSES__CI__VI regGCK_SPLL_FUSES__CI__VI; -typedef union GCK_VCLK_FUSES__CI__VI regGCK_VCLK_FUSES__CI__VI; -typedef union GC_PRIV_MODE regGC_PRIV_MODE; -typedef union GC_USER_PRIM_CONFIG__CI__VI regGC_USER_PRIM_CONFIG__CI__VI; -typedef union GC_USER_RB_BACKEND_DISABLE regGC_USER_RB_BACKEND_DISABLE; -typedef union GC_USER_RB_REDUNDANCY__CI__VI regGC_USER_RB_REDUNDANCY__CI__VI; -typedef union GC_USER_SHADER_ARRAY_CONFIG__SI__CI regGC_USER_SHADER_ARRAY_CONFIG__SI__CI; -typedef union GC_USER_SHADER_ARRAY_CONFIG__VI regGC_USER_SHADER_ARRAY_CONFIG__VI; -typedef union GC_USER_SYS_RB_BACKEND_DISABLE regGC_USER_SYS_RB_BACKEND_DISABLE; -typedef union GDS_ATOM_BASE regGDS_ATOM_BASE; -typedef union GDS_ATOM_CNTL regGDS_ATOM_CNTL; -typedef union GDS_ATOM_COMPLETE regGDS_ATOM_COMPLETE; -typedef union GDS_ATOM_DST regGDS_ATOM_DST; -typedef union GDS_ATOM_OFFSET0 regGDS_ATOM_OFFSET0; -typedef union GDS_ATOM_OFFSET1 regGDS_ATOM_OFFSET1; -typedef union GDS_ATOM_OP regGDS_ATOM_OP; -typedef union GDS_ATOM_READ0 regGDS_ATOM_READ0; -typedef union GDS_ATOM_READ0_U regGDS_ATOM_READ0_U; -typedef union GDS_ATOM_READ1 regGDS_ATOM_READ1; -typedef union GDS_ATOM_READ1_U regGDS_ATOM_READ1_U; -typedef union GDS_ATOM_SIZE regGDS_ATOM_SIZE; -typedef union GDS_ATOM_SRC0 regGDS_ATOM_SRC0; -typedef union GDS_ATOM_SRC0_U regGDS_ATOM_SRC0_U; -typedef union GDS_ATOM_SRC1 regGDS_ATOM_SRC1; -typedef union GDS_ATOM_SRC1_U regGDS_ATOM_SRC1_U; -typedef union GDS_CNTL_STATUS regGDS_CNTL_STATUS; -typedef union GDS_COMPUTE_MAX_WAVE_ID__CI__VI regGDS_COMPUTE_MAX_WAVE_ID__CI__VI; -typedef union GDS_CONFIG regGDS_CONFIG; -typedef union GDS_DEBUG_CNTL regGDS_DEBUG_CNTL; -typedef union GDS_DEBUG_DATA regGDS_DEBUG_DATA; -typedef union GDS_DEBUG_REG0__CI__VI regGDS_DEBUG_REG0__CI__VI; -typedef union GDS_DEBUG_REG0__SI regGDS_DEBUG_REG0__SI; -typedef union GDS_DEBUG_REG10__SI regGDS_DEBUG_REG10__SI; -typedef union GDS_DEBUG_REG1__CI__VI regGDS_DEBUG_REG1__CI__VI; -typedef union GDS_DEBUG_REG1__SI regGDS_DEBUG_REG1__SI; -typedef union GDS_DEBUG_REG2__CI__VI regGDS_DEBUG_REG2__CI__VI; -typedef union GDS_DEBUG_REG2__SI regGDS_DEBUG_REG2__SI; -typedef union GDS_DEBUG_REG3__CI__VI regGDS_DEBUG_REG3__CI__VI; -typedef union GDS_DEBUG_REG3__SI regGDS_DEBUG_REG3__SI; -typedef union GDS_DEBUG_REG4__CI__VI regGDS_DEBUG_REG4__CI__VI; -typedef union GDS_DEBUG_REG4__SI regGDS_DEBUG_REG4__SI; -typedef union GDS_DEBUG_REG5__CI__VI regGDS_DEBUG_REG5__CI__VI; -typedef union GDS_DEBUG_REG5__SI regGDS_DEBUG_REG5__SI; -typedef union GDS_DEBUG_REG6__CI__VI regGDS_DEBUG_REG6__CI__VI; -typedef union GDS_DEBUG_REG6__SI regGDS_DEBUG_REG6__SI; -typedef union GDS_DEBUG_REG7__SI regGDS_DEBUG_REG7__SI; -typedef union GDS_DEBUG_REG8__SI regGDS_DEBUG_REG8__SI; -typedef union GDS_DEBUG_REG9__SI regGDS_DEBUG_REG9__SI; -typedef union GDS_ENHANCE2__CI__VI regGDS_ENHANCE2__CI__VI; -typedef union GDS_ENHANCE__CI__VI regGDS_ENHANCE__CI__VI; -typedef union GDS_ENHANCE__SI regGDS_ENHANCE__SI; -typedef union GDS_GRBM_SECDED_CNT__CI regGDS_GRBM_SECDED_CNT__CI; -typedef union GDS_GRBM_SECDED_CNT__SI regGDS_GRBM_SECDED_CNT__SI; -typedef union GDS_GWS_RESET0__CI__VI regGDS_GWS_RESET0__CI__VI; -typedef union GDS_GWS_RESET1__CI__VI regGDS_GWS_RESET1__CI__VI; -typedef union GDS_GWS_RESOURCE_CNTL regGDS_GWS_RESOURCE_CNTL; -typedef union GDS_GWS_RESOURCE_CNT__CI__VI regGDS_GWS_RESOURCE_CNT__CI__VI; -typedef union GDS_GWS_RESOURCE_RESET__CI__VI regGDS_GWS_RESOURCE_RESET__CI__VI; -typedef union GDS_GWS_RESOURCE__CI regGDS_GWS_RESOURCE__CI; -typedef union GDS_GWS_RESOURCE__VI regGDS_GWS_RESOURCE__VI; -typedef union GDS_GWS_RESOURCE__SI regGDS_GWS_RESOURCE__SI; -typedef union GDS_GWS_VMID0__CI__VI regGDS_GWS_VMID0__CI__VI; -typedef union GDS_GWS_VMID10__CI__VI regGDS_GWS_VMID10__CI__VI; -typedef union GDS_GWS_VMID11__CI__VI regGDS_GWS_VMID11__CI__VI; -typedef union GDS_GWS_VMID12__CI__VI regGDS_GWS_VMID12__CI__VI; -typedef union GDS_GWS_VMID13__CI__VI regGDS_GWS_VMID13__CI__VI; -typedef union GDS_GWS_VMID14__CI__VI regGDS_GWS_VMID14__CI__VI; -typedef union GDS_GWS_VMID15__CI__VI regGDS_GWS_VMID15__CI__VI; -typedef union GDS_GWS_VMID1__CI__VI regGDS_GWS_VMID1__CI__VI; -typedef union GDS_GWS_VMID2__CI__VI regGDS_GWS_VMID2__CI__VI; -typedef union GDS_GWS_VMID3__CI__VI regGDS_GWS_VMID3__CI__VI; -typedef union GDS_GWS_VMID4__CI__VI regGDS_GWS_VMID4__CI__VI; -typedef union GDS_GWS_VMID5__CI__VI regGDS_GWS_VMID5__CI__VI; -typedef union GDS_GWS_VMID6__CI__VI regGDS_GWS_VMID6__CI__VI; -typedef union GDS_GWS_VMID7__CI__VI regGDS_GWS_VMID7__CI__VI; -typedef union GDS_GWS_VMID8__CI__VI regGDS_GWS_VMID8__CI__VI; -typedef union GDS_GWS_VMID9__CI__VI regGDS_GWS_VMID9__CI__VI; -typedef union GDS_OA_ADDRESS__CI regGDS_OA_ADDRESS__CI; -typedef union GDS_OA_ADDRESS__VI regGDS_OA_ADDRESS__VI; -typedef union GDS_OA_CGPG_RESTORE__CI__VI regGDS_OA_CGPG_RESTORE__CI__VI; -typedef union GDS_OA_CNTL__CI__VI regGDS_OA_CNTL__CI__VI; -typedef union GDS_OA_COUNTER__CI__VI regGDS_OA_COUNTER__CI__VI; -typedef union GDS_OA_DED__CI regGDS_OA_DED__CI; -typedef union GDS_OA_DED__SI regGDS_OA_DED__SI; -typedef union GDS_OA_INCDEC__CI__VI regGDS_OA_INCDEC__CI__VI; -typedef union GDS_OA_RESET_MASK__CI__VI regGDS_OA_RESET_MASK__CI__VI; -typedef union GDS_OA_RESET__CI__VI regGDS_OA_RESET__CI__VI; -typedef union GDS_OA_RING_SIZE__CI__VI regGDS_OA_RING_SIZE__CI__VI; -typedef union GDS_OA_VMID0__CI__VI regGDS_OA_VMID0__CI__VI; -typedef union GDS_OA_VMID10__CI__VI regGDS_OA_VMID10__CI__VI; -typedef union GDS_OA_VMID11__CI__VI regGDS_OA_VMID11__CI__VI; -typedef union GDS_OA_VMID12__CI__VI regGDS_OA_VMID12__CI__VI; -typedef union GDS_OA_VMID13__CI__VI regGDS_OA_VMID13__CI__VI; -typedef union GDS_OA_VMID14__CI__VI regGDS_OA_VMID14__CI__VI; -typedef union GDS_OA_VMID15__CI__VI regGDS_OA_VMID15__CI__VI; -typedef union GDS_OA_VMID1__CI__VI regGDS_OA_VMID1__CI__VI; -typedef union GDS_OA_VMID2__CI__VI regGDS_OA_VMID2__CI__VI; -typedef union GDS_OA_VMID3__CI__VI regGDS_OA_VMID3__CI__VI; -typedef union GDS_OA_VMID4__CI__VI regGDS_OA_VMID4__CI__VI; -typedef union GDS_OA_VMID5__CI__VI regGDS_OA_VMID5__CI__VI; -typedef union GDS_OA_VMID6__CI__VI regGDS_OA_VMID6__CI__VI; -typedef union GDS_OA_VMID7__CI__VI regGDS_OA_VMID7__CI__VI; -typedef union GDS_OA_VMID8__CI__VI regGDS_OA_VMID8__CI__VI; -typedef union GDS_OA_VMID9__CI__VI regGDS_OA_VMID9__CI__VI; -typedef union GDS_PERFCOUNTER0_HI regGDS_PERFCOUNTER0_HI; -typedef union GDS_PERFCOUNTER0_LO regGDS_PERFCOUNTER0_LO; -typedef union GDS_PERFCOUNTER0_SELECT regGDS_PERFCOUNTER0_SELECT; -typedef union GDS_PERFCOUNTER0_SELECT1__CI__VI regGDS_PERFCOUNTER0_SELECT1__CI__VI; -typedef union GDS_PERFCOUNTER1_HI regGDS_PERFCOUNTER1_HI; -typedef union GDS_PERFCOUNTER1_LO regGDS_PERFCOUNTER1_LO; -typedef union GDS_PERFCOUNTER1_SELECT regGDS_PERFCOUNTER1_SELECT; -typedef union GDS_PERFCOUNTER2_HI regGDS_PERFCOUNTER2_HI; -typedef union GDS_PERFCOUNTER2_LO regGDS_PERFCOUNTER2_LO; -typedef union GDS_PERFCOUNTER2_SELECT regGDS_PERFCOUNTER2_SELECT; -typedef union GDS_PERFCOUNTER3_HI regGDS_PERFCOUNTER3_HI; -typedef union GDS_PERFCOUNTER3_LO regGDS_PERFCOUNTER3_LO; -typedef union GDS_PERFCOUNTER3_SELECT regGDS_PERFCOUNTER3_SELECT; -typedef union GDS_PROTECTION_FAULT__CI__VI regGDS_PROTECTION_FAULT__CI__VI; -typedef union GDS_RD_ADDR regGDS_RD_ADDR; -typedef union GDS_RD_BURST_ADDR regGDS_RD_BURST_ADDR; -typedef union GDS_RD_BURST_COUNT regGDS_RD_BURST_COUNT; -typedef union GDS_RD_BURST_DATA regGDS_RD_BURST_DATA; -typedef union GDS_RD_DATA regGDS_RD_DATA; -typedef union GDS_SECDED_CNT__CI regGDS_SECDED_CNT__CI; -typedef union GDS_SECDED_CNT__SI regGDS_SECDED_CNT__SI; -typedef union GDS_VMID0_BASE__CI__VI regGDS_VMID0_BASE__CI__VI; -typedef union GDS_VMID0_SIZE__CI__VI regGDS_VMID0_SIZE__CI__VI; -typedef union GDS_VMID10_BASE__CI__VI regGDS_VMID10_BASE__CI__VI; -typedef union GDS_VMID10_SIZE__CI__VI regGDS_VMID10_SIZE__CI__VI; -typedef union GDS_VMID11_BASE__CI__VI regGDS_VMID11_BASE__CI__VI; -typedef union GDS_VMID11_SIZE__CI__VI regGDS_VMID11_SIZE__CI__VI; -typedef union GDS_VMID12_BASE__CI__VI regGDS_VMID12_BASE__CI__VI; -typedef union GDS_VMID12_SIZE__CI__VI regGDS_VMID12_SIZE__CI__VI; -typedef union GDS_VMID13_BASE__CI__VI regGDS_VMID13_BASE__CI__VI; -typedef union GDS_VMID13_SIZE__CI__VI regGDS_VMID13_SIZE__CI__VI; -typedef union GDS_VMID14_BASE__CI__VI regGDS_VMID14_BASE__CI__VI; -typedef union GDS_VMID14_SIZE__CI__VI regGDS_VMID14_SIZE__CI__VI; -typedef union GDS_VMID15_BASE__CI__VI regGDS_VMID15_BASE__CI__VI; -typedef union GDS_VMID15_SIZE__CI__VI regGDS_VMID15_SIZE__CI__VI; -typedef union GDS_VMID1_BASE__CI__VI regGDS_VMID1_BASE__CI__VI; -typedef union GDS_VMID1_SIZE__CI__VI regGDS_VMID1_SIZE__CI__VI; -typedef union GDS_VMID2_BASE__CI__VI regGDS_VMID2_BASE__CI__VI; -typedef union GDS_VMID2_SIZE__CI__VI regGDS_VMID2_SIZE__CI__VI; -typedef union GDS_VMID3_BASE__CI__VI regGDS_VMID3_BASE__CI__VI; -typedef union GDS_VMID3_SIZE__CI__VI regGDS_VMID3_SIZE__CI__VI; -typedef union GDS_VMID4_BASE__CI__VI regGDS_VMID4_BASE__CI__VI; -typedef union GDS_VMID4_SIZE__CI__VI regGDS_VMID4_SIZE__CI__VI; -typedef union GDS_VMID5_BASE__CI__VI regGDS_VMID5_BASE__CI__VI; -typedef union GDS_VMID5_SIZE__CI__VI regGDS_VMID5_SIZE__CI__VI; -typedef union GDS_VMID6_BASE__CI__VI regGDS_VMID6_BASE__CI__VI; -typedef union GDS_VMID6_SIZE__CI__VI regGDS_VMID6_SIZE__CI__VI; -typedef union GDS_VMID7_BASE__CI__VI regGDS_VMID7_BASE__CI__VI; -typedef union GDS_VMID7_SIZE__CI__VI regGDS_VMID7_SIZE__CI__VI; -typedef union GDS_VMID8_BASE__CI__VI regGDS_VMID8_BASE__CI__VI; -typedef union GDS_VMID8_SIZE__CI__VI regGDS_VMID8_SIZE__CI__VI; -typedef union GDS_VMID9_BASE__CI__VI regGDS_VMID9_BASE__CI__VI; -typedef union GDS_VMID9_SIZE__CI__VI regGDS_VMID9_SIZE__CI__VI; -typedef union GDS_VM_PROTECTION_FAULT__CI__VI regGDS_VM_PROTECTION_FAULT__CI__VI; -typedef union GDS_WRITE_COMPLETE regGDS_WRITE_COMPLETE; -typedef union GDS_WR_ADDR regGDS_WR_ADDR; -typedef union GDS_WR_BURST_ADDR regGDS_WR_BURST_ADDR; -typedef union GDS_WR_BURST_DATA regGDS_WR_BURST_DATA; -typedef union GDS_WR_DATA regGDS_WR_DATA; -typedef union GENENB__SI regGENENB__SI; -typedef union GENERAL_PWRMGT__CI__VI regGENERAL_PWRMGT__CI__VI; -typedef union GENERAL_PWRMGT__SI regGENERAL_PWRMGT__SI; -typedef union GENERIC_I2C_CONTROL__SI regGENERIC_I2C_CONTROL__SI; -typedef union GENERIC_I2C_DATA__SI regGENERIC_I2C_DATA__SI; -typedef union GENERIC_I2C_INTERRUPT_CONTROL__SI regGENERIC_I2C_INTERRUPT_CONTROL__SI; -typedef union GENERIC_I2C_PIN_DEBUG__SI regGENERIC_I2C_PIN_DEBUG__SI; -typedef union GENERIC_I2C_PIN_SELECTION__SI regGENERIC_I2C_PIN_SELECTION__SI; -typedef union GENERIC_I2C_SETUP__SI regGENERIC_I2C_SETUP__SI; -typedef union GENERIC_I2C_SPEED__SI regGENERIC_I2C_SPEED__SI; -typedef union GENERIC_I2C_STATUS__SI regGENERIC_I2C_STATUS__SI; -typedef union GENERIC_I2C_TRANSACTION__SI regGENERIC_I2C_TRANSACTION__SI; -typedef union GENFC_RD__SI regGENFC_RD__SI; -typedef union GENFC_WT__SI regGENFC_WT__SI; -typedef union GENMO_RD__SI regGENMO_RD__SI; -typedef union GENMO_WT__SI regGENMO_WT__SI; -typedef union GENS0__SI regGENS0__SI; -typedef union GENS1__SI regGENS1__SI; -typedef union GFX_COPY_STATE regGFX_COPY_STATE; -typedef union GFX_PIPE_CONTROL__CI__VI regGFX_PIPE_CONTROL__CI__VI; -typedef union GFX_PIPE_PRIORITY__CI regGFX_PIPE_PRIORITY__CI; -typedef union GFX_RLC_CONTROL__SI regGFX_RLC_CONTROL__SI; -typedef union GLOBAL_CAPABILITIES__SI regGLOBAL_CAPABILITIES__SI; -typedef union GLOBAL_CONTROL__SI regGLOBAL_CONTROL__SI; -typedef union GLOBAL_STATUS__SI regGLOBAL_STATUS__SI; -typedef union GMCON_DEBUG__CI regGMCON_DEBUG__CI; -typedef union GMCON_DEBUG__VI regGMCON_DEBUG__VI; -typedef union GMCON_MASK__CI__VI regGMCON_MASK__CI__VI; -typedef union GMCON_MISC2__CI regGMCON_MISC2__CI; -typedef union GMCON_MISC2__VI regGMCON_MISC2__VI; -typedef union GMCON_MISC3__CI regGMCON_MISC3__CI; -typedef union GMCON_MISC3__VI regGMCON_MISC3__VI; -typedef union GMCON_MISC__CI__VI regGMCON_MISC__CI__VI; -typedef union GMCON_PERF_MON_CNTL0__CI__VI regGMCON_PERF_MON_CNTL0__CI__VI; -typedef union GMCON_PERF_MON_CNTL1__CI regGMCON_PERF_MON_CNTL1__CI; -typedef union GMCON_PERF_MON_CNTL1__VI regGMCON_PERF_MON_CNTL1__VI; -typedef union GMCON_PERF_MON_RSLT0__CI__VI regGMCON_PERF_MON_RSLT0__CI__VI; -typedef union GMCON_PERF_MON_RSLT1__CI__VI regGMCON_PERF_MON_RSLT1__CI__VI; -typedef union GMCON_PGFSM_CONFIG__CI__VI regGMCON_PGFSM_CONFIG__CI__VI; -typedef union GMCON_PGFSM_READ__CI__VI regGMCON_PGFSM_READ__CI__VI; -typedef union GMCON_PGFSM_WRITE__CI__VI regGMCON_PGFSM_WRITE__CI__VI; -typedef union GMCON_RENG_EXECUTE__CI__VI regGMCON_RENG_EXECUTE__CI__VI; -typedef union GMCON_RENG_RAM_DATA__CI__VI regGMCON_RENG_RAM_DATA__CI__VI; -typedef union GMCON_RENG_RAM_INDEX__CI__VI regGMCON_RENG_RAM_INDEX__CI__VI; -typedef union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI - regGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI; -typedef union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI - regGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI; -typedef union GMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI - regGMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI; -typedef union GMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI - regGMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI; -typedef union GMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI - regGMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI; -typedef union GPIOPAD_A regGPIOPAD_A; -typedef union GPIOPAD_EN regGPIOPAD_EN; -typedef union GPIOPAD_EXTERN_TRIG_CNTL regGPIOPAD_EXTERN_TRIG_CNTL; -typedef union GPIOPAD_INT_EN regGPIOPAD_INT_EN; -typedef union GPIOPAD_INT_POLARITY regGPIOPAD_INT_POLARITY; -typedef union GPIOPAD_INT_STAT regGPIOPAD_INT_STAT; -typedef union GPIOPAD_INT_STAT_AK regGPIOPAD_INT_STAT_AK; -typedef union GPIOPAD_INT_STAT_EN regGPIOPAD_INT_STAT_EN; -typedef union GPIOPAD_INT_TYPE regGPIOPAD_INT_TYPE; -typedef union GPIOPAD_MASK regGPIOPAD_MASK; -typedef union GPIOPAD_PD_EN regGPIOPAD_PD_EN; -typedef union GPIOPAD_PINSTRAPS regGPIOPAD_PINSTRAPS; -typedef union GPIOPAD_PU_EN regGPIOPAD_PU_EN; -typedef union GPIOPAD_RCVR_SEL regGPIOPAD_RCVR_SEL; -typedef union GPIOPAD_STRENGTH regGPIOPAD_STRENGTH; -typedef union GPIOPAD_SW_INT_STAT regGPIOPAD_SW_INT_STAT; -typedef union GPIOPAD_Y regGPIOPAD_Y; -typedef union GPIO_MLPS_PINSTRAPS__CI__VI regGPIO_MLPS_PINSTRAPS__CI__VI; -typedef union GPU_GARLIC_FLUSH_DONE__CI__VI regGPU_GARLIC_FLUSH_DONE__CI__VI; -typedef union GPU_GARLIC_FLUSH_REQ__CI__VI regGPU_GARLIC_FLUSH_REQ__CI__VI; -typedef union GPU_HDP_FLUSH_DONE__CI__VI regGPU_HDP_FLUSH_DONE__CI__VI; -typedef union GPU_HDP_FLUSH_REQ__CI__VI regGPU_HDP_FLUSH_REQ__CI__VI; -typedef union GRA00__SI regGRA00__SI; -typedef union GRA01__SI regGRA01__SI; -typedef union GRA02__SI regGRA02__SI; -typedef union GRA03__SI regGRA03__SI; -typedef union GRA04__SI regGRA04__SI; -typedef union GRA05__SI regGRA05__SI; -typedef union GRA06__SI regGRA06__SI; -typedef union GRA07__SI regGRA07__SI; -typedef union GRA08__SI regGRA08__SI; -typedef union GRBM_CAM_DATA regGRBM_CAM_DATA; -typedef union GRBM_CAM_INDEX regGRBM_CAM_INDEX; -typedef union GRBM_CNTL regGRBM_CNTL; -typedef union GRBM_DEBUG regGRBM_DEBUG; -typedef union GRBM_DEBUG_CNTL regGRBM_DEBUG_CNTL; -typedef union GRBM_DEBUG_DATA regGRBM_DEBUG_DATA; -typedef union GRBM_DEBUG_SNAPSHOT__CI__VI regGRBM_DEBUG_SNAPSHOT__CI__VI; -typedef union GRBM_DEBUG_SNAPSHOT__SI regGRBM_DEBUG_SNAPSHOT__SI; -typedef union GRBM_GFX_CLKEN_CNTL regGRBM_GFX_CLKEN_CNTL; -typedef union GRBM_GFX_INDEX regGRBM_GFX_INDEX; -typedef union GRBM_INT_CNTL regGRBM_INT_CNTL; -typedef union GRBM_NOWHERE regGRBM_NOWHERE; -typedef union GRBM_PERFCOUNTER0_HI regGRBM_PERFCOUNTER0_HI; -typedef union GRBM_PERFCOUNTER0_LO regGRBM_PERFCOUNTER0_LO; -typedef union GRBM_PERFCOUNTER0_SELECT regGRBM_PERFCOUNTER0_SELECT; -typedef union GRBM_PERFCOUNTER1_HI regGRBM_PERFCOUNTER1_HI; -typedef union GRBM_PERFCOUNTER1_LO regGRBM_PERFCOUNTER1_LO; -typedef union GRBM_PERFCOUNTER1_SELECT regGRBM_PERFCOUNTER1_SELECT; -typedef union GRBM_PWR_CNTL__SI__CI regGRBM_PWR_CNTL__SI__CI; -typedef union GRBM_PWR_CNTL__VI regGRBM_PWR_CNTL__VI; -typedef union GRBM_READ_ERROR2__CI__VI regGRBM_READ_ERROR2__CI__VI; -typedef union GRBM_READ_ERROR__CI__VI regGRBM_READ_ERROR__CI__VI; -typedef union GRBM_READ_ERROR__SI regGRBM_READ_ERROR__SI; -typedef union GRBM_SCRATCH_REG0 regGRBM_SCRATCH_REG0; -typedef union GRBM_SCRATCH_REG1 regGRBM_SCRATCH_REG1; -typedef union GRBM_SCRATCH_REG2 regGRBM_SCRATCH_REG2; -typedef union GRBM_SCRATCH_REG3 regGRBM_SCRATCH_REG3; -typedef union GRBM_SCRATCH_REG4 regGRBM_SCRATCH_REG4; -typedef union GRBM_SCRATCH_REG5 regGRBM_SCRATCH_REG5; -typedef union GRBM_SCRATCH_REG6 regGRBM_SCRATCH_REG6; -typedef union GRBM_SCRATCH_REG7 regGRBM_SCRATCH_REG7; -typedef union GRBM_SE0_PERFCOUNTER_HI regGRBM_SE0_PERFCOUNTER_HI; -typedef union GRBM_SE0_PERFCOUNTER_LO regGRBM_SE0_PERFCOUNTER_LO; -typedef union GRBM_SE0_PERFCOUNTER_SELECT regGRBM_SE0_PERFCOUNTER_SELECT; -typedef union GRBM_SE1_PERFCOUNTER_HI regGRBM_SE1_PERFCOUNTER_HI; -typedef union GRBM_SE1_PERFCOUNTER_LO regGRBM_SE1_PERFCOUNTER_LO; -typedef union GRBM_SE1_PERFCOUNTER_SELECT regGRBM_SE1_PERFCOUNTER_SELECT; -typedef union GRBM_SE2_PERFCOUNTER_HI__CI__VI regGRBM_SE2_PERFCOUNTER_HI__CI__VI; -typedef union GRBM_SE2_PERFCOUNTER_LO__CI__VI regGRBM_SE2_PERFCOUNTER_LO__CI__VI; -typedef union GRBM_SE2_PERFCOUNTER_SELECT__CI__VI regGRBM_SE2_PERFCOUNTER_SELECT__CI__VI; -typedef union GRBM_SE3_PERFCOUNTER_HI__CI__VI regGRBM_SE3_PERFCOUNTER_HI__CI__VI; -typedef union GRBM_SE3_PERFCOUNTER_LO__CI__VI regGRBM_SE3_PERFCOUNTER_LO__CI__VI; -typedef union GRBM_SE3_PERFCOUNTER_SELECT__CI__VI regGRBM_SE3_PERFCOUNTER_SELECT__CI__VI; -typedef union GRBM_SKEW_CNTL regGRBM_SKEW_CNTL; -typedef union GRBM_SOFT_RESET regGRBM_SOFT_RESET; -typedef union GRBM_STATUS2__CI__VI regGRBM_STATUS2__CI__VI; -typedef union GRBM_STATUS2__SI regGRBM_STATUS2__SI; -typedef union GRBM_STATUS_SE0 regGRBM_STATUS_SE0; -typedef union GRBM_STATUS_SE1 regGRBM_STATUS_SE1; -typedef union GRBM_STATUS_SE2__CI__VI regGRBM_STATUS_SE2__CI__VI; -typedef union GRBM_STATUS_SE3__CI__VI regGRBM_STATUS_SE3__CI__VI; -typedef union GRBM_STATUS__CI__VI regGRBM_STATUS__CI__VI; -typedef union GRBM_STATUS__SI regGRBM_STATUS__SI; -typedef union GRBM_WAIT_IDLE_CLOCKS regGRBM_WAIT_IDLE_CLOCKS; -typedef union GRPH8_DATA__SI regGRPH8_DATA__SI; -typedef union GRPH8_IDX__SI regGRPH8_IDX__SI; -typedef union GRPH_ALPHA__SI regGRPH_ALPHA__SI; -typedef union GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI - regGRPH_COLOR_MATRIX_TRANSFORMATION_CNTL__SI; -typedef union GRPH_COMPRESS_PITCH__SI regGRPH_COMPRESS_PITCH__SI; -typedef union GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI regGRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI; -typedef union GRPH_COMPRESS_SURFACE_ADDRESS__SI regGRPH_COMPRESS_SURFACE_ADDRESS__SI; -typedef union GRPH_CONTROL__SI regGRPH_CONTROL__SI; -typedef union GRPH_DFQ_CONTROL__SI regGRPH_DFQ_CONTROL__SI; -typedef union GRPH_DFQ_STATUS__SI regGRPH_DFQ_STATUS__SI; -typedef union GRPH_ENABLE__SI regGRPH_ENABLE__SI; -typedef union GRPH_FLIP_CONTROL__SI regGRPH_FLIP_CONTROL__SI; -typedef union GRPH_INTERRUPT_CONTROL__SI regGRPH_INTERRUPT_CONTROL__SI; -typedef union GRPH_INTERRUPT_STATUS__SI regGRPH_INTERRUPT_STATUS__SI; -typedef union GRPH_KEY_RANGE_ALPHA__SI regGRPH_KEY_RANGE_ALPHA__SI; -typedef union GRPH_KEY_RANGE_BLUE__SI regGRPH_KEY_RANGE_BLUE__SI; -typedef union GRPH_KEY_RANGE_GREEN__SI regGRPH_KEY_RANGE_GREEN__SI; -typedef union GRPH_KEY_RANGE_RED__SI regGRPH_KEY_RANGE_RED__SI; -typedef union GRPH_LUT_10BIT_BYPASS__SI regGRPH_LUT_10BIT_BYPASS__SI; -typedef union GRPH_PITCH__SI regGRPH_PITCH__SI; -typedef union GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI regGRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI; -typedef union GRPH_PRIMARY_SURFACE_ADDRESS__SI regGRPH_PRIMARY_SURFACE_ADDRESS__SI; -typedef union GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI regGRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI; -typedef union GRPH_SECONDARY_SURFACE_ADDRESS__SI regGRPH_SECONDARY_SURFACE_ADDRESS__SI; -typedef union GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI regGRPH_SURFACE_ADDRESS_HIGH_INUSE__SI; -typedef union GRPH_SURFACE_ADDRESS_INUSE__SI regGRPH_SURFACE_ADDRESS_INUSE__SI; -typedef union GRPH_SURFACE_OFFSET_X__SI regGRPH_SURFACE_OFFSET_X__SI; -typedef union GRPH_SURFACE_OFFSET_Y__SI regGRPH_SURFACE_OFFSET_Y__SI; -typedef union GRPH_SWAP_CNTL__SI regGRPH_SWAP_CNTL__SI; -typedef union GRPH_UPDATE__SI regGRPH_UPDATE__SI; -typedef union GRPH_X_END__SI regGRPH_X_END__SI; -typedef union GRPH_X_START__SI regGRPH_X_START__SI; -typedef union GRPH_Y_END__SI regGRPH_Y_END__SI; -typedef union GRPH_Y_START__SI regGRPH_Y_START__SI; -typedef union HDCP_CONTROL__SI regHDCP_CONTROL__SI; -typedef union HDCP_DEBUG_CONTROL__SI regHDCP_DEBUG_CONTROL__SI; -typedef union HDCP_DEBUG__SI regHDCP_DEBUG__SI; -typedef union HDCP_DP_STATUS__SI regHDCP_DP_STATUS__SI; -typedef union HDCP_I2C_CONTROL_0__SI regHDCP_I2C_CONTROL_0__SI; -typedef union HDCP_I2C_CONTROL_1__SI regHDCP_I2C_CONTROL_1__SI; -typedef union HDCP_I2C_STATUS__SI regHDCP_I2C_STATUS__SI; -typedef union HDCP_INT_CONTROL__SI regHDCP_INT_CONTROL__SI; -typedef union HDCP_LINK0_STATUS__SI regHDCP_LINK0_STATUS__SI; -typedef union HDCP_LINK1_STATUS__SI regHDCP_LINK1_STATUS__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA0__SI regHDCP_RECV_PORT_LOCAL_DATA0__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA10__SI regHDCP_RECV_PORT_LOCAL_DATA10__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA11__SI regHDCP_RECV_PORT_LOCAL_DATA11__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA12__SI regHDCP_RECV_PORT_LOCAL_DATA12__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA13__SI regHDCP_RECV_PORT_LOCAL_DATA13__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA14__SI regHDCP_RECV_PORT_LOCAL_DATA14__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA15_0__SI regHDCP_RECV_PORT_LOCAL_DATA15_0__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA15_1__SI regHDCP_RECV_PORT_LOCAL_DATA15_1__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA16__SI regHDCP_RECV_PORT_LOCAL_DATA16__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA17__SI regHDCP_RECV_PORT_LOCAL_DATA17__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA18__SI regHDCP_RECV_PORT_LOCAL_DATA18__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA19__SI regHDCP_RECV_PORT_LOCAL_DATA19__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA1__SI regHDCP_RECV_PORT_LOCAL_DATA1__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA20__SI regHDCP_RECV_PORT_LOCAL_DATA20__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA2_0__SI regHDCP_RECV_PORT_LOCAL_DATA2_0__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA2_1__SI regHDCP_RECV_PORT_LOCAL_DATA2_1__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA3__SI regHDCP_RECV_PORT_LOCAL_DATA3__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA4__SI regHDCP_RECV_PORT_LOCAL_DATA4__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA5__SI regHDCP_RECV_PORT_LOCAL_DATA5__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA6__SI regHDCP_RECV_PORT_LOCAL_DATA6__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA7__SI regHDCP_RECV_PORT_LOCAL_DATA7__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA8__SI regHDCP_RECV_PORT_LOCAL_DATA8__SI; -typedef union HDCP_RECV_PORT_LOCAL_DATA9__SI regHDCP_RECV_PORT_LOCAL_DATA9__SI; -typedef union HDCP_RESET__SI regHDCP_RESET__SI; -typedef union HDCP_SHA_CONTROL__SI regHDCP_SHA_CONTROL__SI; -typedef union HDCP_SHA_DATA__SI regHDCP_SHA_DATA__SI; -typedef union HDCP_SHA_DBG_M0_0__SI regHDCP_SHA_DBG_M0_0__SI; -typedef union HDCP_SHA_DBG_M0_1__SI regHDCP_SHA_DBG_M0_1__SI; -typedef union HDCP_SHA_STATUS__SI regHDCP_SHA_STATUS__SI; -typedef union HDMI_ACR_32_0__SI regHDMI_ACR_32_0__SI; -typedef union HDMI_ACR_32_1__SI regHDMI_ACR_32_1__SI; -typedef union HDMI_ACR_44_0__SI regHDMI_ACR_44_0__SI; -typedef union HDMI_ACR_44_1__SI regHDMI_ACR_44_1__SI; -typedef union HDMI_ACR_48_0__SI regHDMI_ACR_48_0__SI; -typedef union HDMI_ACR_48_1__SI regHDMI_ACR_48_1__SI; -typedef union HDMI_ACR_PACKET_CONTROL__SI regHDMI_ACR_PACKET_CONTROL__SI; -typedef union HDMI_ACR_STATUS_0__SI regHDMI_ACR_STATUS_0__SI; -typedef union HDMI_ACR_STATUS_1__SI regHDMI_ACR_STATUS_1__SI; -typedef union HDMI_AUDIO_PACKET_CONTROL__SI regHDMI_AUDIO_PACKET_CONTROL__SI; -typedef union HDMI_CONTROL__SI regHDMI_CONTROL__SI; -typedef union HDMI_GC__SI regHDMI_GC__SI; -typedef union HDMI_GENERIC_PACKET_CONTROL__SI regHDMI_GENERIC_PACKET_CONTROL__SI; -typedef union HDMI_INFOFRAME_CONTROL0__SI regHDMI_INFOFRAME_CONTROL0__SI; -typedef union HDMI_INFOFRAME_CONTROL1__SI regHDMI_INFOFRAME_CONTROL1__SI; -typedef union HDMI_STATUS__SI regHDMI_STATUS__SI; -typedef union HDMI_VBI_PACKET_CONTROL__SI regHDMI_VBI_PACKET_CONTROL__SI; -typedef union HDP_DEBUG0 regHDP_DEBUG0; -typedef union HDP_DEBUG1 regHDP_DEBUG1; -typedef union HDP_HOST_PATH_CNTL regHDP_HOST_PATH_CNTL; -typedef union HDP_LAST_SURFACE_HIT regHDP_LAST_SURFACE_HIT; -typedef union HDP_MEM_COHERENCY_FLUSH_CNTL regHDP_MEM_COHERENCY_FLUSH_CNTL; -typedef union HDP_NONSURFACE_BASE regHDP_NONSURFACE_BASE; -typedef union HDP_NONSURFACE_INFO regHDP_NONSURFACE_INFO; -typedef union HDP_NONSURFACE_SIZE regHDP_NONSURFACE_SIZE; -typedef union HDP_NONSURF_FLAGS regHDP_NONSURF_FLAGS; -typedef union HDP_NONSURF_FLAGS_CLR regHDP_NONSURF_FLAGS_CLR; -typedef union HDP_OUTSTANDING_REQ regHDP_OUTSTANDING_REQ; -typedef union HDP_REG_COHERENCY_FLUSH_CNTL regHDP_REG_COHERENCY_FLUSH_CNTL; -typedef union HDP_SC_MULTI_CHIP_CNTL regHDP_SC_MULTI_CHIP_CNTL; -typedef union HDP_SURFACE0_BASE regHDP_SURFACE0_BASE; -typedef union HDP_SURFACE0_INFO regHDP_SURFACE0_INFO; -typedef union HDP_SURFACE0_LOWER_BOUND regHDP_SURFACE0_LOWER_BOUND; -typedef union HDP_SURFACE0_SIZE regHDP_SURFACE0_SIZE; -typedef union HDP_SURFACE0_UPPER_BOUND regHDP_SURFACE0_UPPER_BOUND; -typedef union HDP_SURFACE10_BASE regHDP_SURFACE10_BASE; -typedef union HDP_SURFACE10_INFO regHDP_SURFACE10_INFO; -typedef union HDP_SURFACE10_LOWER_BOUND regHDP_SURFACE10_LOWER_BOUND; -typedef union HDP_SURFACE10_SIZE regHDP_SURFACE10_SIZE; -typedef union HDP_SURFACE10_UPPER_BOUND regHDP_SURFACE10_UPPER_BOUND; -typedef union HDP_SURFACE11_BASE regHDP_SURFACE11_BASE; -typedef union HDP_SURFACE11_INFO regHDP_SURFACE11_INFO; -typedef union HDP_SURFACE11_LOWER_BOUND regHDP_SURFACE11_LOWER_BOUND; -typedef union HDP_SURFACE11_SIZE regHDP_SURFACE11_SIZE; -typedef union HDP_SURFACE11_UPPER_BOUND regHDP_SURFACE11_UPPER_BOUND; -typedef union HDP_SURFACE12_BASE regHDP_SURFACE12_BASE; -typedef union HDP_SURFACE12_INFO regHDP_SURFACE12_INFO; -typedef union HDP_SURFACE12_LOWER_BOUND regHDP_SURFACE12_LOWER_BOUND; -typedef union HDP_SURFACE12_SIZE regHDP_SURFACE12_SIZE; -typedef union HDP_SURFACE12_UPPER_BOUND regHDP_SURFACE12_UPPER_BOUND; -typedef union HDP_SURFACE13_BASE regHDP_SURFACE13_BASE; -typedef union HDP_SURFACE13_INFO regHDP_SURFACE13_INFO; -typedef union HDP_SURFACE13_LOWER_BOUND regHDP_SURFACE13_LOWER_BOUND; -typedef union HDP_SURFACE13_SIZE regHDP_SURFACE13_SIZE; -typedef union HDP_SURFACE13_UPPER_BOUND regHDP_SURFACE13_UPPER_BOUND; -typedef union HDP_SURFACE14_BASE regHDP_SURFACE14_BASE; -typedef union HDP_SURFACE14_INFO regHDP_SURFACE14_INFO; -typedef union HDP_SURFACE14_LOWER_BOUND regHDP_SURFACE14_LOWER_BOUND; -typedef union HDP_SURFACE14_SIZE regHDP_SURFACE14_SIZE; -typedef union HDP_SURFACE14_UPPER_BOUND regHDP_SURFACE14_UPPER_BOUND; -typedef union HDP_SURFACE15_BASE regHDP_SURFACE15_BASE; -typedef union HDP_SURFACE15_INFO regHDP_SURFACE15_INFO; -typedef union HDP_SURFACE15_LOWER_BOUND regHDP_SURFACE15_LOWER_BOUND; -typedef union HDP_SURFACE15_SIZE regHDP_SURFACE15_SIZE; -typedef union HDP_SURFACE15_UPPER_BOUND regHDP_SURFACE15_UPPER_BOUND; -typedef union HDP_SURFACE16_BASE regHDP_SURFACE16_BASE; -typedef union HDP_SURFACE16_INFO regHDP_SURFACE16_INFO; -typedef union HDP_SURFACE16_LOWER_BOUND regHDP_SURFACE16_LOWER_BOUND; -typedef union HDP_SURFACE16_SIZE regHDP_SURFACE16_SIZE; -typedef union HDP_SURFACE16_UPPER_BOUND regHDP_SURFACE16_UPPER_BOUND; -typedef union HDP_SURFACE17_BASE regHDP_SURFACE17_BASE; -typedef union HDP_SURFACE17_INFO regHDP_SURFACE17_INFO; -typedef union HDP_SURFACE17_LOWER_BOUND regHDP_SURFACE17_LOWER_BOUND; -typedef union HDP_SURFACE17_SIZE regHDP_SURFACE17_SIZE; -typedef union HDP_SURFACE17_UPPER_BOUND regHDP_SURFACE17_UPPER_BOUND; -typedef union HDP_SURFACE18_BASE regHDP_SURFACE18_BASE; -typedef union HDP_SURFACE18_INFO regHDP_SURFACE18_INFO; -typedef union HDP_SURFACE18_LOWER_BOUND regHDP_SURFACE18_LOWER_BOUND; -typedef union HDP_SURFACE18_SIZE regHDP_SURFACE18_SIZE; -typedef union HDP_SURFACE18_UPPER_BOUND regHDP_SURFACE18_UPPER_BOUND; -typedef union HDP_SURFACE19_BASE regHDP_SURFACE19_BASE; -typedef union HDP_SURFACE19_INFO regHDP_SURFACE19_INFO; -typedef union HDP_SURFACE19_LOWER_BOUND regHDP_SURFACE19_LOWER_BOUND; -typedef union HDP_SURFACE19_SIZE regHDP_SURFACE19_SIZE; -typedef union HDP_SURFACE19_UPPER_BOUND regHDP_SURFACE19_UPPER_BOUND; -typedef union HDP_SURFACE1_BASE regHDP_SURFACE1_BASE; -typedef union HDP_SURFACE1_INFO regHDP_SURFACE1_INFO; -typedef union HDP_SURFACE1_LOWER_BOUND regHDP_SURFACE1_LOWER_BOUND; -typedef union HDP_SURFACE1_SIZE regHDP_SURFACE1_SIZE; -typedef union HDP_SURFACE1_UPPER_BOUND regHDP_SURFACE1_UPPER_BOUND; -typedef union HDP_SURFACE20_BASE regHDP_SURFACE20_BASE; -typedef union HDP_SURFACE20_INFO regHDP_SURFACE20_INFO; -typedef union HDP_SURFACE20_LOWER_BOUND regHDP_SURFACE20_LOWER_BOUND; -typedef union HDP_SURFACE20_SIZE regHDP_SURFACE20_SIZE; -typedef union HDP_SURFACE20_UPPER_BOUND regHDP_SURFACE20_UPPER_BOUND; -typedef union HDP_SURFACE21_BASE regHDP_SURFACE21_BASE; -typedef union HDP_SURFACE21_INFO regHDP_SURFACE21_INFO; -typedef union HDP_SURFACE21_LOWER_BOUND regHDP_SURFACE21_LOWER_BOUND; -typedef union HDP_SURFACE21_SIZE regHDP_SURFACE21_SIZE; -typedef union HDP_SURFACE21_UPPER_BOUND regHDP_SURFACE21_UPPER_BOUND; -typedef union HDP_SURFACE22_BASE regHDP_SURFACE22_BASE; -typedef union HDP_SURFACE22_INFO regHDP_SURFACE22_INFO; -typedef union HDP_SURFACE22_LOWER_BOUND regHDP_SURFACE22_LOWER_BOUND; -typedef union HDP_SURFACE22_SIZE regHDP_SURFACE22_SIZE; -typedef union HDP_SURFACE22_UPPER_BOUND regHDP_SURFACE22_UPPER_BOUND; -typedef union HDP_SURFACE23_BASE regHDP_SURFACE23_BASE; -typedef union HDP_SURFACE23_INFO regHDP_SURFACE23_INFO; -typedef union HDP_SURFACE23_LOWER_BOUND regHDP_SURFACE23_LOWER_BOUND; -typedef union HDP_SURFACE23_SIZE regHDP_SURFACE23_SIZE; -typedef union HDP_SURFACE23_UPPER_BOUND regHDP_SURFACE23_UPPER_BOUND; -typedef union HDP_SURFACE24_BASE regHDP_SURFACE24_BASE; -typedef union HDP_SURFACE24_INFO regHDP_SURFACE24_INFO; -typedef union HDP_SURFACE24_LOWER_BOUND regHDP_SURFACE24_LOWER_BOUND; -typedef union HDP_SURFACE24_SIZE regHDP_SURFACE24_SIZE; -typedef union HDP_SURFACE24_UPPER_BOUND regHDP_SURFACE24_UPPER_BOUND; -typedef union HDP_SURFACE25_BASE regHDP_SURFACE25_BASE; -typedef union HDP_SURFACE25_INFO regHDP_SURFACE25_INFO; -typedef union HDP_SURFACE25_LOWER_BOUND regHDP_SURFACE25_LOWER_BOUND; -typedef union HDP_SURFACE25_SIZE regHDP_SURFACE25_SIZE; -typedef union HDP_SURFACE25_UPPER_BOUND regHDP_SURFACE25_UPPER_BOUND; -typedef union HDP_SURFACE26_BASE regHDP_SURFACE26_BASE; -typedef union HDP_SURFACE26_INFO regHDP_SURFACE26_INFO; -typedef union HDP_SURFACE26_LOWER_BOUND regHDP_SURFACE26_LOWER_BOUND; -typedef union HDP_SURFACE26_SIZE regHDP_SURFACE26_SIZE; -typedef union HDP_SURFACE26_UPPER_BOUND regHDP_SURFACE26_UPPER_BOUND; -typedef union HDP_SURFACE27_BASE regHDP_SURFACE27_BASE; -typedef union HDP_SURFACE27_INFO regHDP_SURFACE27_INFO; -typedef union HDP_SURFACE27_LOWER_BOUND regHDP_SURFACE27_LOWER_BOUND; -typedef union HDP_SURFACE27_SIZE regHDP_SURFACE27_SIZE; -typedef union HDP_SURFACE27_UPPER_BOUND regHDP_SURFACE27_UPPER_BOUND; -typedef union HDP_SURFACE28_BASE regHDP_SURFACE28_BASE; -typedef union HDP_SURFACE28_INFO regHDP_SURFACE28_INFO; -typedef union HDP_SURFACE28_LOWER_BOUND regHDP_SURFACE28_LOWER_BOUND; -typedef union HDP_SURFACE28_SIZE regHDP_SURFACE28_SIZE; -typedef union HDP_SURFACE28_UPPER_BOUND regHDP_SURFACE28_UPPER_BOUND; -typedef union HDP_SURFACE29_BASE regHDP_SURFACE29_BASE; -typedef union HDP_SURFACE29_INFO regHDP_SURFACE29_INFO; -typedef union HDP_SURFACE29_LOWER_BOUND regHDP_SURFACE29_LOWER_BOUND; -typedef union HDP_SURFACE29_SIZE regHDP_SURFACE29_SIZE; -typedef union HDP_SURFACE29_UPPER_BOUND regHDP_SURFACE29_UPPER_BOUND; -typedef union HDP_SURFACE2_BASE regHDP_SURFACE2_BASE; -typedef union HDP_SURFACE2_INFO regHDP_SURFACE2_INFO; -typedef union HDP_SURFACE2_LOWER_BOUND regHDP_SURFACE2_LOWER_BOUND; -typedef union HDP_SURFACE2_SIZE regHDP_SURFACE2_SIZE; -typedef union HDP_SURFACE2_UPPER_BOUND regHDP_SURFACE2_UPPER_BOUND; -typedef union HDP_SURFACE30_BASE regHDP_SURFACE30_BASE; -typedef union HDP_SURFACE30_INFO regHDP_SURFACE30_INFO; -typedef union HDP_SURFACE30_LOWER_BOUND regHDP_SURFACE30_LOWER_BOUND; -typedef union HDP_SURFACE30_SIZE regHDP_SURFACE30_SIZE; -typedef union HDP_SURFACE30_UPPER_BOUND regHDP_SURFACE30_UPPER_BOUND; -typedef union HDP_SURFACE31_BASE regHDP_SURFACE31_BASE; -typedef union HDP_SURFACE31_INFO regHDP_SURFACE31_INFO; -typedef union HDP_SURFACE31_LOWER_BOUND regHDP_SURFACE31_LOWER_BOUND; -typedef union HDP_SURFACE31_SIZE regHDP_SURFACE31_SIZE; -typedef union HDP_SURFACE31_UPPER_BOUND regHDP_SURFACE31_UPPER_BOUND; -typedef union HDP_SURFACE3_BASE regHDP_SURFACE3_BASE; -typedef union HDP_SURFACE3_INFO regHDP_SURFACE3_INFO; -typedef union HDP_SURFACE3_LOWER_BOUND regHDP_SURFACE3_LOWER_BOUND; -typedef union HDP_SURFACE3_SIZE regHDP_SURFACE3_SIZE; -typedef union HDP_SURFACE3_UPPER_BOUND regHDP_SURFACE3_UPPER_BOUND; -typedef union HDP_SURFACE4_BASE regHDP_SURFACE4_BASE; -typedef union HDP_SURFACE4_INFO regHDP_SURFACE4_INFO; -typedef union HDP_SURFACE4_LOWER_BOUND regHDP_SURFACE4_LOWER_BOUND; -typedef union HDP_SURFACE4_SIZE regHDP_SURFACE4_SIZE; -typedef union HDP_SURFACE4_UPPER_BOUND regHDP_SURFACE4_UPPER_BOUND; -typedef union HDP_SURFACE5_BASE regHDP_SURFACE5_BASE; -typedef union HDP_SURFACE5_INFO regHDP_SURFACE5_INFO; -typedef union HDP_SURFACE5_LOWER_BOUND regHDP_SURFACE5_LOWER_BOUND; -typedef union HDP_SURFACE5_SIZE regHDP_SURFACE5_SIZE; -typedef union HDP_SURFACE5_UPPER_BOUND regHDP_SURFACE5_UPPER_BOUND; -typedef union HDP_SURFACE6_BASE regHDP_SURFACE6_BASE; -typedef union HDP_SURFACE6_INFO regHDP_SURFACE6_INFO; -typedef union HDP_SURFACE6_LOWER_BOUND regHDP_SURFACE6_LOWER_BOUND; -typedef union HDP_SURFACE6_SIZE regHDP_SURFACE6_SIZE; -typedef union HDP_SURFACE6_UPPER_BOUND regHDP_SURFACE6_UPPER_BOUND; -typedef union HDP_SURFACE7_BASE regHDP_SURFACE7_BASE; -typedef union HDP_SURFACE7_INFO regHDP_SURFACE7_INFO; -typedef union HDP_SURFACE7_LOWER_BOUND regHDP_SURFACE7_LOWER_BOUND; -typedef union HDP_SURFACE7_SIZE regHDP_SURFACE7_SIZE; -typedef union HDP_SURFACE7_UPPER_BOUND regHDP_SURFACE7_UPPER_BOUND; -typedef union HDP_SURFACE8_BASE regHDP_SURFACE8_BASE; -typedef union HDP_SURFACE8_INFO regHDP_SURFACE8_INFO; -typedef union HDP_SURFACE8_LOWER_BOUND regHDP_SURFACE8_LOWER_BOUND; -typedef union HDP_SURFACE8_SIZE regHDP_SURFACE8_SIZE; -typedef union HDP_SURFACE8_UPPER_BOUND regHDP_SURFACE8_UPPER_BOUND; -typedef union HDP_SURFACE9_BASE regHDP_SURFACE9_BASE; -typedef union HDP_SURFACE9_INFO regHDP_SURFACE9_INFO; -typedef union HDP_SURFACE9_LOWER_BOUND regHDP_SURFACE9_LOWER_BOUND; -typedef union HDP_SURFACE9_SIZE regHDP_SURFACE9_SIZE; -typedef union HDP_SURFACE9_UPPER_BOUND regHDP_SURFACE9_UPPER_BOUND; -typedef union HDP_SURFACE_READ_FLAGS regHDP_SURFACE_READ_FLAGS; -typedef union HDP_SURFACE_READ_FLAGS_CLR regHDP_SURFACE_READ_FLAGS_CLR; -typedef union HDP_SURFACE_WRITE_FLAGS regHDP_SURFACE_WRITE_FLAGS; -typedef union HDP_SURFACE_WRITE_FLAGS_CLR regHDP_SURFACE_WRITE_FLAGS_CLR; -typedef union HDP_SW_SEMAPHORE regHDP_SW_SEMAPHORE; -typedef union HDP_TILING_CONFIG regHDP_TILING_CONFIG; -typedef union HDP_XDP_BUSY_STS regHDP_XDP_BUSY_STS; -typedef union HDP_XDP_CGTT_BLK_CTRL regHDP_XDP_CGTT_BLK_CTRL; -typedef union HDP_XDP_CHKN regHDP_XDP_CHKN; -typedef union HDP_XDP_D2H_BAR_UPDATE regHDP_XDP_D2H_BAR_UPDATE; -typedef union HDP_XDP_D2H_FLUSH regHDP_XDP_D2H_FLUSH; -typedef union HDP_XDP_D2H_RSVD_10 regHDP_XDP_D2H_RSVD_10; -typedef union HDP_XDP_D2H_RSVD_11 regHDP_XDP_D2H_RSVD_11; -typedef union HDP_XDP_D2H_RSVD_12 regHDP_XDP_D2H_RSVD_12; -typedef union HDP_XDP_D2H_RSVD_13 regHDP_XDP_D2H_RSVD_13; -typedef union HDP_XDP_D2H_RSVD_14 regHDP_XDP_D2H_RSVD_14; -typedef union HDP_XDP_D2H_RSVD_15 regHDP_XDP_D2H_RSVD_15; -typedef union HDP_XDP_D2H_RSVD_16 regHDP_XDP_D2H_RSVD_16; -typedef union HDP_XDP_D2H_RSVD_17 regHDP_XDP_D2H_RSVD_17; -typedef union HDP_XDP_D2H_RSVD_18 regHDP_XDP_D2H_RSVD_18; -typedef union HDP_XDP_D2H_RSVD_19 regHDP_XDP_D2H_RSVD_19; -typedef union HDP_XDP_D2H_RSVD_20 regHDP_XDP_D2H_RSVD_20; -typedef union HDP_XDP_D2H_RSVD_21 regHDP_XDP_D2H_RSVD_21; -typedef union HDP_XDP_D2H_RSVD_22 regHDP_XDP_D2H_RSVD_22; -typedef union HDP_XDP_D2H_RSVD_23 regHDP_XDP_D2H_RSVD_23; -typedef union HDP_XDP_D2H_RSVD_24 regHDP_XDP_D2H_RSVD_24; -typedef union HDP_XDP_D2H_RSVD_25 regHDP_XDP_D2H_RSVD_25; -typedef union HDP_XDP_D2H_RSVD_26 regHDP_XDP_D2H_RSVD_26; -typedef union HDP_XDP_D2H_RSVD_27 regHDP_XDP_D2H_RSVD_27; -typedef union HDP_XDP_D2H_RSVD_28 regHDP_XDP_D2H_RSVD_28; -typedef union HDP_XDP_D2H_RSVD_29 regHDP_XDP_D2H_RSVD_29; -typedef union HDP_XDP_D2H_RSVD_3 regHDP_XDP_D2H_RSVD_3; -typedef union HDP_XDP_D2H_RSVD_30 regHDP_XDP_D2H_RSVD_30; -typedef union HDP_XDP_D2H_RSVD_31 regHDP_XDP_D2H_RSVD_31; -typedef union HDP_XDP_D2H_RSVD_32 regHDP_XDP_D2H_RSVD_32; -typedef union HDP_XDP_D2H_RSVD_33 regHDP_XDP_D2H_RSVD_33; -typedef union HDP_XDP_D2H_RSVD_34 regHDP_XDP_D2H_RSVD_34; -typedef union HDP_XDP_D2H_RSVD_4 regHDP_XDP_D2H_RSVD_4; -typedef union HDP_XDP_D2H_RSVD_5 regHDP_XDP_D2H_RSVD_5; -typedef union HDP_XDP_D2H_RSVD_6 regHDP_XDP_D2H_RSVD_6; -typedef union HDP_XDP_D2H_RSVD_7 regHDP_XDP_D2H_RSVD_7; -typedef union HDP_XDP_D2H_RSVD_8 regHDP_XDP_D2H_RSVD_8; -typedef union HDP_XDP_D2H_RSVD_9 regHDP_XDP_D2H_RSVD_9; -typedef union HDP_XDP_DBG_ADDR regHDP_XDP_DBG_ADDR; -typedef union HDP_XDP_DBG_DATA regHDP_XDP_DBG_DATA; -typedef union HDP_XDP_DBG_MASK regHDP_XDP_DBG_MASK; -typedef union HDP_XDP_DIRECT2HDP_FIRST regHDP_XDP_DIRECT2HDP_FIRST; -typedef union HDP_XDP_DIRECT2HDP_LAST regHDP_XDP_DIRECT2HDP_LAST; -typedef union HDP_XDP_FLUSH_ARMED_STS regHDP_XDP_FLUSH_ARMED_STS; -typedef union HDP_XDP_FLUSH_CNTR0_STS regHDP_XDP_FLUSH_CNTR0_STS; -typedef union HDP_XDP_HDP_IPH_CFG regHDP_XDP_HDP_IPH_CFG; -typedef union HDP_XDP_HDP_MBX_MC_CFG regHDP_XDP_HDP_MBX_MC_CFG; -typedef union HDP_XDP_HDP_MC_CFG regHDP_XDP_HDP_MC_CFG; -typedef union HDP_XDP_HST_CFG regHDP_XDP_HST_CFG; -typedef union HDP_XDP_P2P_BAR0 regHDP_XDP_P2P_BAR0; -typedef union HDP_XDP_P2P_BAR1 regHDP_XDP_P2P_BAR1; -typedef union HDP_XDP_P2P_BAR2 regHDP_XDP_P2P_BAR2; -typedef union HDP_XDP_P2P_BAR3 regHDP_XDP_P2P_BAR3; -typedef union HDP_XDP_P2P_BAR4 regHDP_XDP_P2P_BAR4; -typedef union HDP_XDP_P2P_BAR5 regHDP_XDP_P2P_BAR5; -typedef union HDP_XDP_P2P_BAR6 regHDP_XDP_P2P_BAR6; -typedef union HDP_XDP_P2P_BAR7 regHDP_XDP_P2P_BAR7; -typedef union HDP_XDP_P2P_BAR_CFG regHDP_XDP_P2P_BAR_CFG; -typedef union HDP_XDP_P2P_MBX_ADDR0 regHDP_XDP_P2P_MBX_ADDR0; -typedef union HDP_XDP_P2P_MBX_ADDR1 regHDP_XDP_P2P_MBX_ADDR1; -typedef union HDP_XDP_P2P_MBX_ADDR2 regHDP_XDP_P2P_MBX_ADDR2; -typedef union HDP_XDP_P2P_MBX_ADDR3 regHDP_XDP_P2P_MBX_ADDR3; -typedef union HDP_XDP_P2P_MBX_ADDR4 regHDP_XDP_P2P_MBX_ADDR4; -typedef union HDP_XDP_P2P_MBX_ADDR5 regHDP_XDP_P2P_MBX_ADDR5; -typedef union HDP_XDP_P2P_MBX_ADDR6 regHDP_XDP_P2P_MBX_ADDR6; -typedef union HDP_XDP_P2P_MBX_OFFSET regHDP_XDP_P2P_MBX_OFFSET; -typedef union HDP_XDP_SID_CFG regHDP_XDP_SID_CFG; -typedef union HDP_XDP_SRBM_CFG regHDP_XDP_SRBM_CFG; -typedef union HDP_XDP_STICKY regHDP_XDP_STICKY; -typedef union HD_BACKPORCH_DUR__SI regHD_BACKPORCH_DUR__SI; -typedef union HD_CGMS_TIMING__SI regHD_CGMS_TIMING__SI; -typedef union HD_EMBEDDED_SYNC_CNTL__SI regHD_EMBEDDED_SYNC_CNTL__SI; -typedef union HD_INCR__SI regHD_INCR__SI; -typedef union HD_POS_SYNC_LEVEL__SI regHD_POS_SYNC_LEVEL__SI; -typedef union HD_SERATION_DUR__SI regHD_SERATION_DUR__SI; -typedef union HD_TRILEVEL_DUR__SI regHD_TRILEVEL_DUR__SI; -typedef union HEADER regHEADER; -typedef union HFS_SEED0 regHFS_SEED0; -typedef union HFS_SEED1 regHFS_SEED1; -typedef union HFS_SEED2 regHFS_SEED2; -typedef union HFS_SEED3 regHFS_SEED3; -typedef union HOST_BUSNUM regHOST_BUSNUM; -typedef union HPD_DEBUG__SI regHPD_DEBUG__SI; -typedef union HW_DEBUG regHW_DEBUG; -typedef union I2C_CNTL_0__SI regI2C_CNTL_0__SI; -typedef union I2C_CNTL_1__SI regI2C_CNTL_1__SI; -typedef union I2C_DATA__SI regI2C_DATA__SI; -typedef union I2C_DEBUG_BUS__SI regI2C_DEBUG_BUS__SI; -typedef union IA_CNTL_STATUS regIA_CNTL_STATUS; -typedef union IA_DEBUG_CNTL regIA_DEBUG_CNTL; -typedef union IA_DEBUG_DATA regIA_DEBUG_DATA; -typedef union IA_DEBUG_REG0__CI__VI regIA_DEBUG_REG0__CI__VI; -typedef union IA_DEBUG_REG0__SI regIA_DEBUG_REG0__SI; -typedef union IA_DEBUG_REG1__CI__VI regIA_DEBUG_REG1__CI__VI; -typedef union IA_DEBUG_REG1__SI regIA_DEBUG_REG1__SI; -typedef union IA_DEBUG_REG2__CI__VI regIA_DEBUG_REG2__CI__VI; -typedef union IA_DEBUG_REG2__SI regIA_DEBUG_REG2__SI; -typedef union IA_DEBUG_REG3__CI__VI regIA_DEBUG_REG3__CI__VI; -typedef union IA_DEBUG_REG3__SI regIA_DEBUG_REG3__SI; -typedef union IA_DEBUG_REG4__CI__VI regIA_DEBUG_REG4__CI__VI; -typedef union IA_DEBUG_REG4__SI regIA_DEBUG_REG4__SI; -typedef union IA_DEBUG_REG5__CI__VI regIA_DEBUG_REG5__CI__VI; -typedef union IA_DEBUG_REG5__SI regIA_DEBUG_REG5__SI; -typedef union IA_DEBUG_REG6__CI__VI regIA_DEBUG_REG6__CI__VI; -typedef union IA_DEBUG_REG6__SI regIA_DEBUG_REG6__SI; -typedef union IA_DEBUG_REG7__CI__VI regIA_DEBUG_REG7__CI__VI; -typedef union IA_DEBUG_REG7__SI regIA_DEBUG_REG7__SI; -typedef union IA_DEBUG_REG8 regIA_DEBUG_REG8; -typedef union IA_DEBUG_REG9__CI__VI regIA_DEBUG_REG9__CI__VI; -typedef union IA_DEBUG_REG9__SI regIA_DEBUG_REG9__SI; -typedef union IA_ENHANCE regIA_ENHANCE; -typedef union IA_MULTI_VGT_PARAM regIA_MULTI_VGT_PARAM; -typedef union IA_PERFCOUNTER0_HI regIA_PERFCOUNTER0_HI; -typedef union IA_PERFCOUNTER0_LO regIA_PERFCOUNTER0_LO; -typedef union IA_PERFCOUNTER0_SELECT1__CI__VI regIA_PERFCOUNTER0_SELECT1__CI__VI; -typedef union IA_PERFCOUNTER0_SELECT__CI__VI regIA_PERFCOUNTER0_SELECT__CI__VI; -typedef union IA_PERFCOUNTER0_SELECT__SI regIA_PERFCOUNTER0_SELECT__SI; -typedef union IA_PERFCOUNTER1_HI regIA_PERFCOUNTER1_HI; -typedef union IA_PERFCOUNTER1_LO regIA_PERFCOUNTER1_LO; -typedef union IA_PERFCOUNTER1_SELECT regIA_PERFCOUNTER1_SELECT; -typedef union IA_PERFCOUNTER2_HI regIA_PERFCOUNTER2_HI; -typedef union IA_PERFCOUNTER2_LO regIA_PERFCOUNTER2_LO; -typedef union IA_PERFCOUNTER2_SELECT regIA_PERFCOUNTER2_SELECT; -typedef union IA_PERFCOUNTER3_HI regIA_PERFCOUNTER3_HI; -typedef union IA_PERFCOUNTER3_LO regIA_PERFCOUNTER3_LO; -typedef union IA_PERFCOUNTER3_SELECT regIA_PERFCOUNTER3_SELECT; -typedef union IA_VMID_OVERRIDE__SI__CI regIA_VMID_OVERRIDE__SI__CI; -typedef union ICON_COLOR1__SI regICON_COLOR1__SI; -typedef union ICON_COLOR2__SI regICON_COLOR2__SI; -typedef union ICON_CONTROL__SI regICON_CONTROL__SI; -typedef union ICON_SIZE__SI regICON_SIZE__SI; -typedef union ICON_START_POSITION__SI regICON_START_POSITION__SI; -typedef union ICON_SURFACE_ADDRESS_HIGH__SI regICON_SURFACE_ADDRESS_HIGH__SI; -typedef union ICON_SURFACE_ADDRESS__SI regICON_SURFACE_ADDRESS__SI; -typedef union ICON_UPDATE__SI regICON_UPDATE__SI; -typedef union ID00_DCP_LB_DATA_P0__SI regID00_DCP_LB_DATA_P0__SI; -typedef union ID01_DCP_LB_DATA_P1__SI regID01_DCP_LB_DATA_P1__SI; -typedef union ID02_DCP_DMIF_GRPH_DATA_LOW_p0__SI regID02_DCP_DMIF_GRPH_DATA_LOW_p0__SI; -typedef union ID03_DCP_DMIF_GRPH_DATA_HIGH_p0__SI regID03_DCP_DMIF_GRPH_DATA_HIGH_p0__SI; -typedef union ID04_DCP_DMIF_GRPH_DATA_LOW_p1__SI regID04_DCP_DMIF_GRPH_DATA_LOW_p1__SI; -typedef union ID05_DCP_DMIF_GRPH_DATA_HIGH_p1__SI regID05_DCP_DMIF_GRPH_DATA_HIGH_p1__SI; -typedef union ID06_DCP_DMIF_OVLDATA_p0__SI regID06_DCP_DMIF_OVLDATA_p0__SI; -typedef union ID07_DCP_DMIF_OVLDATA_p1__SI regID07_DCP_DMIF_OVLDATA_p1__SI; -typedef union ID08_DCP_LB_CHUNK_REQUEST__SI regID08_DCP_LB_CHUNK_REQUEST__SI; -typedef union ID09_DCP_DMIF_CHUNK_REQUEST__SI regID09_DCP_DMIF_CHUNK_REQUEST__SI; -typedef union ID10_DCP_DCCIF_DATA__SI regID10_DCP_DCCIF_DATA__SI; -typedef union ID11_DCP_DCCIF_REQUEST__SI regID11_DCP_DCCIF_REQUEST__SI; -typedef union ID12_DCP_DCCIF_REQUEST__SI regID12_DCP_DCCIF_REQUEST__SI; -typedef union ID13_DCP_DCCIF_REQUEST__SI regID13_DCP_DCCIF_REQUEST__SI; -typedef union ID14_DCP_DMIF_STATUS__SI regID14_DCP_DMIF_STATUS__SI; -typedef union ID14_DMIF_STATUS__SI regID14_DMIF_STATUS__SI; -typedef union ID15_DMIF_MC_LATENCY__SI regID15_DMIF_MC_LATENCY__SI; -typedef union ID16_MCIF_MC_LATENCY__SI regID16_MCIF_MC_LATENCY__SI; -typedef union ID17_MCIF_MC_LATENCY__SI regID17_MCIF_MC_LATENCY__SI; -typedef union ID18_D1GRPH_PRIMARY_SURFACE_ADDRESS__SI regID18_D1GRPH_PRIMARY_SURFACE_ADDRESS__SI; -typedef union ID19_D1GRPH_SECONDARY_SURFACE_ADDRESS__SI - regID19_D1GRPH_SECONDARY_SURFACE_ADDRESS__SI; -typedef union ID20_D1OVL_SURFACE_ADDRESS__SI regID20_D1OVL_SURFACE_ADDRESS__SI; -typedef union ID21_D1GRPH_COMPRESS_SURFACE_ADDRESS__SI regID21_D1GRPH_COMPRESS_SURFACE_ADDRESS__SI; -typedef union ID22_D1CURSOR_SURFACE_ADDRESS__SI regID22_D1CURSOR_SURFACE_ADDRESS__SI; -typedef union ID23_D1ICON_SURFACE_ADDRESS__SI regID23_D1ICON_SURFACE_ADDRESS__SI; -typedef union ID30_DCCARB_VIP_R_ADDR__SI regID30_DCCARB_VIP_R_ADDR__SI; -typedef union ID31_DCCARB_DCT_R_ADDR__SI regID31_DCCARB_DCT_R_ADDR__SI; -typedef union ID34_DCCARB_FBC_R_ADDR__SI regID34_DCCARB_FBC_R_ADDR__SI; -typedef union ID35_DCCARB_VGA_W_ADDR__SI regID35_DCCARB_VGA_W_ADDR__SI; -typedef union ID36_DCCARB_FBC_W_ADDR__SI regID36_DCCARB_FBC_W_ADDR__SI; -typedef union ID37_MC_IF_DEBUG_01__SI regID37_MC_IF_DEBUG_01__SI; -typedef union ID38_MC_IF_DEBUG_02__SI regID38_MC_IF_DEBUG_02__SI; -typedef union ID39_MC_IF_DEBUG_03__SI regID39_MC_IF_DEBUG_03__SI; -typedef union ID40_MC_IF_DEBUG_04__SI regID40_MC_IF_DEBUG_04__SI; -typedef union ID41_MC_IF_DEBUG_05__SI regID41_MC_IF_DEBUG_05__SI; -typedef union ID42_MC_IF_DEBUG_06__SI regID42_MC_IF_DEBUG_06__SI; -typedef union ID43_MC_IF_DEBUG_07__SI regID43_MC_IF_DEBUG_07__SI; -typedef union ID44_MC_IF_DEBUG_08__SI regID44_MC_IF_DEBUG_08__SI; -typedef union ID45_MC_IF_DEBUG_09__SI regID45_MC_IF_DEBUG_09__SI; -typedef union ID46_MC_IF_DEBUG_10__SI regID46_MC_IF_DEBUG_10__SI; -typedef union IDCT_AUTH0__SI regIDCT_AUTH0__SI; -typedef union IDCT_AUTH1__SI regIDCT_AUTH1__SI; -typedef union IDCT_AUTH2__SI regIDCT_AUTH2__SI; -typedef union IDCT_AUTH3__SI regIDCT_AUTH3__SI; -typedef union IDCT_AUTH_CONTROL0__SI regIDCT_AUTH_CONTROL0__SI; -typedef union IDCT_AUTH_CONTROL1__SI regIDCT_AUTH_CONTROL1__SI; -typedef union IDCT_AUTH_CONTROL2__SI regIDCT_AUTH_CONTROL2__SI; -typedef union IDCT_AUTH_CONTROL3__SI regIDCT_AUTH_CONTROL3__SI; -typedef union IDCT_COEF_BASE__SI regIDCT_COEF_BASE__SI; -typedef union IDCT_COEF_DATA__SI regIDCT_COEF_DATA__SI; -typedef union IDCT_CONFIG__SI regIDCT_CONFIG__SI; -typedef union IDCT_CONTROL__SI regIDCT_CONTROL__SI; -typedef union IDCT_CURRENT_MB_STATUS_DEBUG__SI regIDCT_CURRENT_MB_STATUS_DEBUG__SI; -typedef union IDCT_DEBUG_00__SI regIDCT_DEBUG_00__SI; -typedef union IDCT_DEBUG_01__SI regIDCT_DEBUG_01__SI; -typedef union IDCT_DEBUG_02__SI regIDCT_DEBUG_02__SI; -typedef union IDCT_DEBUG_03__SI regIDCT_DEBUG_03__SI; -typedef union IDCT_DEBUG_04__SI regIDCT_DEBUG_04__SI; -typedef union IDCT_DEBUG_05__SI regIDCT_DEBUG_05__SI; -typedef union IDCT_DEBUG_06__SI regIDCT_DEBUG_06__SI; -typedef union IDCT_DEBUG_0A__SI regIDCT_DEBUG_0A__SI; -typedef union IDCT_DEBUG_0B__SI regIDCT_DEBUG_0B__SI; -typedef union IDCT_DEBUG_0C__SI regIDCT_DEBUG_0C__SI; -typedef union IDCT_DEBUG_18__SI regIDCT_DEBUG_18__SI; -typedef union IDCT_DEBUG_19__SI regIDCT_DEBUG_19__SI; -typedef union IDCT_DEBUG_20__SI regIDCT_DEBUG_20__SI; -typedef union IDCT_DEBUG_21__SI regIDCT_DEBUG_21__SI; -typedef union IDCT_DEBUG_22__SI regIDCT_DEBUG_22__SI; -typedef union IDCT_DEBUG_23__SI regIDCT_DEBUG_23__SI; -typedef union IDCT_DEBUG_24__SI regIDCT_DEBUG_24__SI; -typedef union IDCT_DRM_CONTROL_STATUS__SI regIDCT_DRM_CONTROL_STATUS__SI; -typedef union IDCT_DRM_WR_CREDIT__SI regIDCT_DRM_WR_CREDIT__SI; -typedef union IDCT_EOB_ERROR_STATUS__SI regIDCT_EOB_ERROR_STATUS__SI; -typedef union IDCT_IDLE_DEBUG__SI regIDCT_IDLE_DEBUG__SI; -typedef union IDCT_PIO_MODE_XY__SI regIDCT_PIO_MODE_XY__SI; -typedef union IDCT_SCRAMBLE_SELECT__SI regIDCT_SCRAMBLE_SELECT__SI; -typedef union IDCT_SCRATCH__SI regIDCT_SCRATCH__SI; -typedef union IDCT_SPAN__SI regIDCT_SPAN__SI; -typedef union IDCT_STATUS__SI regIDCT_STATUS__SI; -typedef union IDCT_STREAM_ID__SI regIDCT_STREAM_ID__SI; -typedef union IDCT_TEST_DEBUG_DATA__SI regIDCT_TEST_DEBUG_DATA__SI; -typedef union IDCT_TEST_DEBUG_INDEX__SI regIDCT_TEST_DEBUG_INDEX__SI; -typedef union IDDCCIF00_DBG_DCCIF_A__SI regIDDCCIF00_DBG_DCCIF_A__SI; -typedef union IDDCCIF01_DBG_DCCIF_B__SI regIDDCCIF01_DBG_DCCIF_B__SI; -typedef union IDDCCIF02_DBG_DCCIF_C__SI regIDDCCIF02_DBG_DCCIF_C__SI; -typedef union IDDCCIF03_DBG_DCCIF_D__SI regIDDCCIF03_DBG_DCCIF_D__SI; -typedef union IDDCCIF04_DBG_DCCIF_E__SI regIDDCCIF04_DBG_DCCIF_E__SI; -typedef union IDDCCIF05_DBG_DCCIF_F__SI regIDDCCIF05_DBG_DCCIF_F__SI; -typedef union IDDCCIF06_DBG_DCCIF_G__SI regIDDCCIF06_DBG_DCCIF_G__SI; -typedef union IDDCCIF07_DBG_DCCIF_H__SI regIDDCCIF07_DBG_DCCIF_H__SI; -typedef union IDDCCIF08_DBG_DCCIF_I__SI regIDDCCIF08_DBG_DCCIF_I__SI; -typedef union IDDCCIF09_DBG_DCCIF_J__SI regIDDCCIF09_DBG_DCCIF_J__SI; -typedef union IDDCCIF10_DBG_DCCIF_K__SI regIDDCCIF10_DBG_DCCIF_K__SI; -typedef union IDDCCIF11_DBG_DCCIF_L__SI regIDDCCIF11_DBG_DCCIF_L__SI; -typedef union IDSC_REG__CI regIDSC_REG__CI; -typedef union IH_ADVFAULT_CNTL__SI__CI regIH_ADVFAULT_CNTL__SI__CI; -typedef union IH_CNTL regIH_CNTL; -typedef union IH_LEVEL_STATUS regIH_LEVEL_STATUS; -typedef union IH_PERFCOUNTER0_RESULT__CI__VI regIH_PERFCOUNTER0_RESULT__CI__VI; -typedef union IH_PERFCOUNTER1_RESULT__CI__VI regIH_PERFCOUNTER1_RESULT__CI__VI; -typedef union IH_PERFMON_CNTL__CI__VI regIH_PERFMON_CNTL__CI__VI; -typedef union IH_PERF_CNTL__SI regIH_PERF_CNTL__SI; -typedef union IH_PERF_COUNT0__SI regIH_PERF_COUNT0__SI; -typedef union IH_PERF_COUNT1__SI regIH_PERF_COUNT1__SI; -typedef union IH_RB_BASE regIH_RB_BASE; -typedef union IH_RB_CNTL regIH_RB_CNTL; -typedef union IH_RB_RPTR regIH_RB_RPTR; -typedef union IH_RB_WPTR regIH_RB_WPTR; -typedef union IH_RB_WPTR_ADDR_HI regIH_RB_WPTR_ADDR_HI; -typedef union IH_RB_WPTR_ADDR_LO regIH_RB_WPTR_ADDR_LO; -typedef union IH_STATUS regIH_STATUS; -typedef union IH_VMID_0_LUT__CI__VI regIH_VMID_0_LUT__CI__VI; -typedef union IH_VMID_10_LUT__CI__VI regIH_VMID_10_LUT__CI__VI; -typedef union IH_VMID_11_LUT__CI__VI regIH_VMID_11_LUT__CI__VI; -typedef union IH_VMID_12_LUT__CI__VI regIH_VMID_12_LUT__CI__VI; -typedef union IH_VMID_13_LUT__CI__VI regIH_VMID_13_LUT__CI__VI; -typedef union IH_VMID_14_LUT__CI__VI regIH_VMID_14_LUT__CI__VI; -typedef union IH_VMID_15_LUT__CI__VI regIH_VMID_15_LUT__CI__VI; -typedef union IH_VMID_1_LUT__CI__VI regIH_VMID_1_LUT__CI__VI; -typedef union IH_VMID_2_LUT__CI__VI regIH_VMID_2_LUT__CI__VI; -typedef union IH_VMID_3_LUT__CI__VI regIH_VMID_3_LUT__CI__VI; -typedef union IH_VMID_4_LUT__CI__VI regIH_VMID_4_LUT__CI__VI; -typedef union IH_VMID_5_LUT__CI__VI regIH_VMID_5_LUT__CI__VI; -typedef union IH_VMID_6_LUT__CI__VI regIH_VMID_6_LUT__CI__VI; -typedef union IH_VMID_7_LUT__CI__VI regIH_VMID_7_LUT__CI__VI; -typedef union IH_VMID_8_LUT__CI__VI regIH_VMID_8_LUT__CI__VI; -typedef union IH_VMID_9_LUT__CI__VI regIH_VMID_9_LUT__CI__VI; -typedef union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__SI - regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__SI; -typedef union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__SI - regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__SI; -typedef union IMMEDIATE_COMMAND_OUTPUT_INTERFACE__SI regIMMEDIATE_COMMAND_OUTPUT_INTERFACE__SI; -typedef union IMMEDIATE_COMMAND_STATUS__SI regIMMEDIATE_COMMAND_STATUS__SI; -typedef union IMMEDIATE_RESPONSE_INPUT_INTERFACE__SI regIMMEDIATE_RESPONSE_INPUT_INTERFACE__SI; -typedef union IMPCTL_RESET__CI__VI regIMPCTL_RESET__CI__VI; -typedef union IM_INT_EN__SI regIM_INT_EN__SI; -typedef union IM_INT_STAT__SI regIM_INT_STAT__SI; -typedef union INPUT_PAYLOAD_CAPABILITY__SI regINPUT_PAYLOAD_CAPABILITY__SI; -typedef union INTERRUPT_CNTL regINTERRUPT_CNTL; -typedef union INTERRUPT_CNTL2 regINTERRUPT_CNTL2; -typedef union INTERRUPT_CONTROL__SI regINTERRUPT_CONTROL__SI; -typedef union INTERRUPT_LINE regINTERRUPT_LINE; -typedef union INTERRUPT_PIN regINTERRUPT_PIN; -typedef union INTERRUPT_STATUS__SI regINTERRUPT_STATUS__SI; -typedef union INT_MASK__SI regINT_MASK__SI; -typedef union IOU_MISC_STATUS__CI__VI regIOU_MISC_STATUS__CI__VI; -typedef union IOU_SMC_IND_DATA__CI__VI regIOU_SMC_IND_DATA__CI__VI; -typedef union IOU_SMC_IND_INDEX__CI__VI regIOU_SMC_IND_INDEX__CI__VI; -typedef union IT_BUF_SIZE__SI regIT_BUF_SIZE__SI; -typedef union IT_CF_DAT__SI regIT_CF_DAT__SI; -typedef union IT_CTL__SI regIT_CTL__SI; -typedef union IT_DEBUG_BUS__SI regIT_DEBUG_BUS__SI; -typedef union IT_DEBUG_INT_STAT__SI regIT_DEBUG_INT_STAT__SI; -typedef union IT_HW_DEBUG__SI regIT_HW_DEBUG__SI; -typedef union IT_INTRA_HOR_ADR__SI regIT_INTRA_HOR_ADR__SI; -typedef union IT_INT_EN__SI regIT_INT_EN__SI; -typedef union IT_INT_STAT__SI regIT_INT_STAT__SI; -typedef union IT_LMA_ADR__SI regIT_LMA_ADR__SI; -typedef union IT_LMA_CTL__SI regIT_LMA_CTL__SI; -typedef union IT_LMA_DAT__SI regIT_LMA_DAT__SI; -typedef union IT_PPS_INFO__SI regIT_PPS_INFO__SI; -typedef union IT_SLICE_INFO__SI regIT_SLICE_INFO__SI; -typedef union IT_SPS_INFO__SI regIT_SPS_INFO__SI; -typedef union IT_SRAM_RM_CTL__SI regIT_SRAM_RM_CTL__SI; -typedef union IT_STAT__SI regIT_STAT__SI; -typedef union KEFUSE0 regKEFUSE0; -typedef union KEFUSE1 regKEFUSE1; -typedef union KEFUSE2 regKEFUSE2; -typedef union KEFUSE3 regKEFUSE3; -typedef union KHFS0 regKHFS0; -typedef union KHFS1 regKHFS1; -typedef union KHFS2 regKHFS2; -typedef union KHFS3 regKHFS3; -typedef union KSESSION0 regKSESSION0; -typedef union KSESSION1 regKSESSION1; -typedef union KSESSION2 regKSESSION2; -typedef union KSESSION3 regKSESSION3; -typedef union KSIG0 regKSIG0; -typedef union KSIG1 regKSIG1; -typedef union KSIG2 regKSIG2; -typedef union KSIG3 regKSIG3; -typedef union LATENCY regLATENCY; -typedef union LB_DCP_WRITE__SI regLB_DCP_WRITE__SI; -typedef union LB_DEBUG_ID__SI regLB_DEBUG_ID__SI; -typedef union LB_DEBUG_PRE_ECO__SI regLB_DEBUG_PRE_ECO__SI; -typedef union LB_DEBUG__SI regLB_DEBUG__SI; -typedef union LB_DISP1_ALU__SI regLB_DISP1_ALU__SI; -typedef union LB_DISP1_PARAM__SI regLB_DISP1_PARAM__SI; -typedef union LB_DISP1_REQ__SI regLB_DISP1_REQ__SI; -typedef union LB_DISP2_ALU__SI regLB_DISP2_ALU__SI; -typedef union LB_DISP2_PARAM__SI regLB_DISP2_PARAM__SI; -typedef union LB_DISP2_REQ__SI regLB_DISP2_REQ__SI; -typedef union LB_MAX_REQ_OUTSTANDING__SI regLB_MAX_REQ_OUTSTANDING__SI; -typedef union LB_MCLK_CHG_DBG1__SI regLB_MCLK_CHG_DBG1__SI; -typedef union LB_MCLK_CHG_DBG2__SI regLB_MCLK_CHG_DBG2__SI; -typedef union LB_MVP_DEBUG1__SI regLB_MVP_DEBUG1__SI; -typedef union LB_MVP_DEBUG2__SI regLB_MVP_DEBUG2__SI; -typedef union LB_MVP_DEBUG3__SI regLB_MVP_DEBUG3__SI; -typedef union LB_MVP_DEBUG4__SI regLB_MVP_DEBUG4__SI; -typedef union LB_MVP_DEBUG5__SI regLB_MVP_DEBUG5__SI; -typedef union LB_NEW_LEVEL1__SI regLB_NEW_LEVEL1__SI; -typedef union LB_NEW_LEVEL2__SI regLB_NEW_LEVEL2__SI; -typedef union LB_NEW_STATUS1__SI regLB_NEW_STATUS1__SI; -typedef union LB_SCL1_READ__SI regLB_SCL1_READ__SI; -typedef union LB_SCL2_READ__SI regLB_SCL2_READ__SI; -typedef union LB_SLOW_REQ_VAL__SI regLB_SLOW_REQ_VAL__SI; -typedef union LB_STUTTER_DBG1__SI regLB_STUTTER_DBG1__SI; -typedef union LB_STUTTER_DBG2__SI regLB_STUTTER_DBG2__SI; -typedef union LB_STUTTER_DBG3__SI regLB_STUTTER_DBG3__SI; -typedef union LB_SYNC_RESET_SEL__SI regLB_SYNC_RESET_SEL__SI; -typedef union LB_TEST_DEBUG_DATA__SI regLB_TEST_DEBUG_DATA__SI; -typedef union LB_TEST_DEBUG_INDEX__SI regLB_TEST_DEBUG_INDEX__SI; -typedef union LB_URGENCY__SI regLB_URGENCY__SI; -typedef union LB_URGENT_LEVEL_CNTL__SI regLB_URGENT_LEVEL_CNTL__SI; -typedef union LCAC_CPL_CB_CNTL__SI regLCAC_CPL_CB_CNTL__SI; -typedef union LCAC_CPL_CB_OVR_SEL__SI regLCAC_CPL_CB_OVR_SEL__SI; -typedef union LCAC_CPL_CB_OVR_VAL__SI regLCAC_CPL_CB_OVR_VAL__SI; -typedef union LCAC_CPL_CNTL__CI regLCAC_CPL_CNTL__CI; -typedef union LCAC_CPL_DB_CNTL__SI regLCAC_CPL_DB_CNTL__SI; -typedef union LCAC_CPL_DB_OVR_SEL__SI regLCAC_CPL_DB_OVR_SEL__SI; -typedef union LCAC_CPL_DB_OVR_VAL__SI regLCAC_CPL_DB_OVR_VAL__SI; -typedef union LCAC_CPL_LDS_CNTL__SI regLCAC_CPL_LDS_CNTL__SI; -typedef union LCAC_CPL_LDS_OVR_SEL__SI regLCAC_CPL_LDS_OVR_SEL__SI; -typedef union LCAC_CPL_LDS_OVR_VAL__SI regLCAC_CPL_LDS_OVR_VAL__SI; -typedef union LCAC_CPL_MC_CNTL__SI regLCAC_CPL_MC_CNTL__SI; -typedef union LCAC_CPL_MC_OVR_SEL__SI regLCAC_CPL_MC_OVR_SEL__SI; -typedef union LCAC_CPL_MC_OVR_VAL__SI regLCAC_CPL_MC_OVR_VAL__SI; -typedef union LCAC_CPL_OVR_SEL__CI regLCAC_CPL_OVR_SEL__CI; -typedef union LCAC_CPL_OVR_VAL__CI regLCAC_CPL_OVR_VAL__CI; -typedef union LCAC_CPL_PA_CNTL__SI regLCAC_CPL_PA_CNTL__SI; -typedef union LCAC_CPL_PA_OVR_SEL__SI regLCAC_CPL_PA_OVR_SEL__SI; -typedef union LCAC_CPL_PA_OVR_VAL__SI regLCAC_CPL_PA_OVR_VAL__SI; -typedef union LCAC_CPL_SC_CNTL__SI regLCAC_CPL_SC_CNTL__SI; -typedef union LCAC_CPL_SC_OVR_SEL__SI regLCAC_CPL_SC_OVR_SEL__SI; -typedef union LCAC_CPL_SC_OVR_VAL__SI regLCAC_CPL_SC_OVR_VAL__SI; -typedef union LCAC_CPL_SPI_CNTL__SI regLCAC_CPL_SPI_CNTL__SI; -typedef union LCAC_CPL_SPI_OVR_SEL__SI regLCAC_CPL_SPI_OVR_SEL__SI; -typedef union LCAC_CPL_SPI_OVR_VAL__SI regLCAC_CPL_SPI_OVR_VAL__SI; -typedef union LCAC_CPL_SQ_CNTL__SI regLCAC_CPL_SQ_CNTL__SI; -typedef union LCAC_CPL_SQ_OVR_SEL__SI regLCAC_CPL_SQ_OVR_SEL__SI; -typedef union LCAC_CPL_SQ_OVR_VAL__SI regLCAC_CPL_SQ_OVR_VAL__SI; -typedef union LCAC_CPL_SX_CNTL__SI regLCAC_CPL_SX_CNTL__SI; -typedef union LCAC_CPL_SX_OVR_SEL__SI regLCAC_CPL_SX_OVR_SEL__SI; -typedef union LCAC_CPL_SX_OVR_VAL__SI regLCAC_CPL_SX_OVR_VAL__SI; -typedef union LCAC_CPL_TA_CNTL__SI regLCAC_CPL_TA_CNTL__SI; -typedef union LCAC_CPL_TA_OVR_SEL__SI regLCAC_CPL_TA_OVR_SEL__SI; -typedef union LCAC_CPL_TA_OVR_VAL__SI regLCAC_CPL_TA_OVR_VAL__SI; -typedef union LCAC_CPL_TCC_CNTL__SI regLCAC_CPL_TCC_CNTL__SI; -typedef union LCAC_CPL_TCC_OVR_SEL__SI regLCAC_CPL_TCC_OVR_SEL__SI; -typedef union LCAC_CPL_TCC_OVR_VAL__SI regLCAC_CPL_TCC_OVR_VAL__SI; -typedef union LCAC_CPL_TCP_CNTL__SI regLCAC_CPL_TCP_CNTL__SI; -typedef union LCAC_CPL_TCP_OVR_SEL__SI regLCAC_CPL_TCP_OVR_SEL__SI; -typedef union LCAC_CPL_TCP_OVR_VAL__SI regLCAC_CPL_TCP_OVR_VAL__SI; -typedef union LCAC_CPL_VGT_CNTL__SI regLCAC_CPL_VGT_CNTL__SI; -typedef union LCAC_CPL_VGT_OVR_SEL__SI regLCAC_CPL_VGT_OVR_SEL__SI; -typedef union LCAC_CPL_VGT_OVR_VAL__SI regLCAC_CPL_VGT_OVR_VAL__SI; -typedef union LCAC_MC0_CNTL__SI__CI regLCAC_MC0_CNTL__SI__CI; -typedef union LCAC_MC0_OVR_SEL__SI__CI regLCAC_MC0_OVR_SEL__SI__CI; -typedef union LCAC_MC0_OVR_VAL__SI__CI regLCAC_MC0_OVR_VAL__SI__CI; -typedef union LCAC_MC1_CNTL__SI__CI regLCAC_MC1_CNTL__SI__CI; -typedef union LCAC_MC1_OVR_SEL__SI__CI regLCAC_MC1_OVR_SEL__SI__CI; -typedef union LCAC_MC1_OVR_VAL__SI__CI regLCAC_MC1_OVR_VAL__SI__CI; -typedef union LCAC_MC2_CNTL__SI__CI regLCAC_MC2_CNTL__SI__CI; -typedef union LCAC_MC2_OVR_SEL__SI__CI regLCAC_MC2_OVR_SEL__SI__CI; -typedef union LCAC_MC2_OVR_VAL__SI__CI regLCAC_MC2_OVR_VAL__SI__CI; -typedef union LCAC_MC3_CNTL__SI__CI regLCAC_MC3_CNTL__SI__CI; -typedef union LCAC_MC3_OVR_SEL__SI__CI regLCAC_MC3_OVR_SEL__SI__CI; -typedef union LCAC_MC3_OVR_VAL__SI__CI regLCAC_MC3_OVR_VAL__SI__CI; -typedef union LCAC_MC4_CNTL__SI regLCAC_MC4_CNTL__SI; -typedef union LCAC_MC4_OVR_SEL__SI regLCAC_MC4_OVR_SEL__SI; -typedef union LCAC_MC4_OVR_VAL__SI regLCAC_MC4_OVR_VAL__SI; -typedef union LCAC_MC5_CNTL__SI regLCAC_MC5_CNTL__SI; -typedef union LCAC_MC5_OVR_SEL__SI regLCAC_MC5_OVR_SEL__SI; -typedef union LCAC_MC5_OVR_VAL__SI regLCAC_MC5_OVR_VAL__SI; -typedef union LCAC_SX0_CB_CNTL__SI regLCAC_SX0_CB_CNTL__SI; -typedef union LCAC_SX0_CB_OVR_SEL__SI regLCAC_SX0_CB_OVR_SEL__SI; -typedef union LCAC_SX0_CB_OVR_VAL__SI regLCAC_SX0_CB_OVR_VAL__SI; -typedef union LCAC_SX0_CNTL__CI regLCAC_SX0_CNTL__CI; -typedef union LCAC_SX0_DB_CNTL__SI regLCAC_SX0_DB_CNTL__SI; -typedef union LCAC_SX0_DB_OVR_SEL__SI regLCAC_SX0_DB_OVR_SEL__SI; -typedef union LCAC_SX0_DB_OVR_VAL__SI regLCAC_SX0_DB_OVR_VAL__SI; -typedef union LCAC_SX0_LDS_CNTL__SI regLCAC_SX0_LDS_CNTL__SI; -typedef union LCAC_SX0_LDS_OVR_SEL__SI regLCAC_SX0_LDS_OVR_SEL__SI; -typedef union LCAC_SX0_LDS_OVR_VAL__SI regLCAC_SX0_LDS_OVR_VAL__SI; -typedef union LCAC_SX0_OVR_SEL__CI regLCAC_SX0_OVR_SEL__CI; -typedef union LCAC_SX0_OVR_VAL__CI regLCAC_SX0_OVR_VAL__CI; -typedef union LCAC_SX0_TA_CNTL__SI regLCAC_SX0_TA_CNTL__SI; -typedef union LCAC_SX0_TA_OVR_SEL__SI regLCAC_SX0_TA_OVR_SEL__SI; -typedef union LCAC_SX0_TA_OVR_VAL__SI regLCAC_SX0_TA_OVR_VAL__SI; -typedef union LCAC_SX0_TCC_CNTL__SI regLCAC_SX0_TCC_CNTL__SI; -typedef union LCAC_SX0_TCC_OVR_SEL__SI regLCAC_SX0_TCC_OVR_SEL__SI; -typedef union LCAC_SX0_TCC_OVR_VAL__SI regLCAC_SX0_TCC_OVR_VAL__SI; -typedef union LCAC_SX0_TCP_CNTL__SI regLCAC_SX0_TCP_CNTL__SI; -typedef union LCAC_SX0_TCP_OVR_SEL__SI regLCAC_SX0_TCP_OVR_SEL__SI; -typedef union LCAC_SX0_TCP_OVR_VAL__SI regLCAC_SX0_TCP_OVR_VAL__SI; -typedef union LCAC_SX1_CB_CNTL__SI regLCAC_SX1_CB_CNTL__SI; -typedef union LCAC_SX1_CB_OVR_SEL__SI regLCAC_SX1_CB_OVR_SEL__SI; -typedef union LCAC_SX1_CB_OVR_VAL__SI regLCAC_SX1_CB_OVR_VAL__SI; -typedef union LCAC_SX1_CNTL__CI regLCAC_SX1_CNTL__CI; -typedef union LCAC_SX1_DB_CNTL__SI regLCAC_SX1_DB_CNTL__SI; -typedef union LCAC_SX1_DB_OVR_SEL__SI regLCAC_SX1_DB_OVR_SEL__SI; -typedef union LCAC_SX1_DB_OVR_VAL__SI regLCAC_SX1_DB_OVR_VAL__SI; -typedef union LCAC_SX1_LDS_CNTL__SI regLCAC_SX1_LDS_CNTL__SI; -typedef union LCAC_SX1_LDS_OVR_SEL__SI regLCAC_SX1_LDS_OVR_SEL__SI; -typedef union LCAC_SX1_LDS_OVR_VAL__SI regLCAC_SX1_LDS_OVR_VAL__SI; -typedef union LCAC_SX1_OVR_SEL__CI regLCAC_SX1_OVR_SEL__CI; -typedef union LCAC_SX1_OVR_VAL__CI regLCAC_SX1_OVR_VAL__CI; -typedef union LCAC_SX1_TA_CNTL__SI regLCAC_SX1_TA_CNTL__SI; -typedef union LCAC_SX1_TA_OVR_SEL__SI regLCAC_SX1_TA_OVR_SEL__SI; -typedef union LCAC_SX1_TA_OVR_VAL__SI regLCAC_SX1_TA_OVR_VAL__SI; -typedef union LCAC_SX1_TCC_CNTL__SI regLCAC_SX1_TCC_CNTL__SI; -typedef union LCAC_SX1_TCC_OVR_SEL__SI regLCAC_SX1_TCC_OVR_SEL__SI; -typedef union LCAC_SX1_TCC_OVR_VAL__SI regLCAC_SX1_TCC_OVR_VAL__SI; -typedef union LCAC_SX1_TCP_CNTL__SI regLCAC_SX1_TCP_CNTL__SI; -typedef union LCAC_SX1_TCP_OVR_SEL__SI regLCAC_SX1_TCP_OVR_SEL__SI; -typedef union LCAC_SX1_TCP_OVR_VAL__SI regLCAC_SX1_TCP_OVR_VAL__SI; -typedef union LCAC_SX2_CB_CNTL__SI regLCAC_SX2_CB_CNTL__SI; -typedef union LCAC_SX2_CB_OVR_SEL__SI regLCAC_SX2_CB_OVR_SEL__SI; -typedef union LCAC_SX2_CB_OVR_VAL__SI regLCAC_SX2_CB_OVR_VAL__SI; -typedef union LCAC_SX2_CNTL__CI regLCAC_SX2_CNTL__CI; -typedef union LCAC_SX2_DB_CNTL__SI regLCAC_SX2_DB_CNTL__SI; -typedef union LCAC_SX2_DB_OVR_SEL__SI regLCAC_SX2_DB_OVR_SEL__SI; -typedef union LCAC_SX2_DB_OVR_VAL__SI regLCAC_SX2_DB_OVR_VAL__SI; -typedef union LCAC_SX2_LDS_CNTL__SI regLCAC_SX2_LDS_CNTL__SI; -typedef union LCAC_SX2_LDS_OVR_SEL__SI regLCAC_SX2_LDS_OVR_SEL__SI; -typedef union LCAC_SX2_LDS_OVR_VAL__SI regLCAC_SX2_LDS_OVR_VAL__SI; -typedef union LCAC_SX2_OVR_SEL__CI regLCAC_SX2_OVR_SEL__CI; -typedef union LCAC_SX2_OVR_VAL__CI regLCAC_SX2_OVR_VAL__CI; -typedef union LCAC_SX2_TA_CNTL__SI regLCAC_SX2_TA_CNTL__SI; -typedef union LCAC_SX2_TA_OVR_SEL__SI regLCAC_SX2_TA_OVR_SEL__SI; -typedef union LCAC_SX2_TA_OVR_VAL__SI regLCAC_SX2_TA_OVR_VAL__SI; -typedef union LCAC_SX2_TCC_CNTL__SI regLCAC_SX2_TCC_CNTL__SI; -typedef union LCAC_SX2_TCC_OVR_SEL__SI regLCAC_SX2_TCC_OVR_SEL__SI; -typedef union LCAC_SX2_TCC_OVR_VAL__SI regLCAC_SX2_TCC_OVR_VAL__SI; -typedef union LCAC_SX2_TCP_CNTL__SI regLCAC_SX2_TCP_CNTL__SI; -typedef union LCAC_SX2_TCP_OVR_SEL__SI regLCAC_SX2_TCP_OVR_SEL__SI; -typedef union LCAC_SX2_TCP_OVR_VAL__SI regLCAC_SX2_TCP_OVR_VAL__SI; -typedef union LCAC_SX3_CB_CNTL__SI regLCAC_SX3_CB_CNTL__SI; -typedef union LCAC_SX3_CB_OVR_SEL__SI regLCAC_SX3_CB_OVR_SEL__SI; -typedef union LCAC_SX3_CB_OVR_VAL__SI regLCAC_SX3_CB_OVR_VAL__SI; -typedef union LCAC_SX3_CNTL__CI regLCAC_SX3_CNTL__CI; -typedef union LCAC_SX3_DB_CNTL__SI regLCAC_SX3_DB_CNTL__SI; -typedef union LCAC_SX3_DB_OVR_SEL__SI regLCAC_SX3_DB_OVR_SEL__SI; -typedef union LCAC_SX3_DB_OVR_VAL__SI regLCAC_SX3_DB_OVR_VAL__SI; -typedef union LCAC_SX3_LDS_CNTL__SI regLCAC_SX3_LDS_CNTL__SI; -typedef union LCAC_SX3_LDS_OVR_SEL__SI regLCAC_SX3_LDS_OVR_SEL__SI; -typedef union LCAC_SX3_LDS_OVR_VAL__SI regLCAC_SX3_LDS_OVR_VAL__SI; -typedef union LCAC_SX3_OVR_SEL__CI regLCAC_SX3_OVR_SEL__CI; -typedef union LCAC_SX3_OVR_VAL__CI regLCAC_SX3_OVR_VAL__CI; -typedef union LCAC_SX3_TA_CNTL__SI regLCAC_SX3_TA_CNTL__SI; -typedef union LCAC_SX3_TA_OVR_SEL__SI regLCAC_SX3_TA_OVR_SEL__SI; -typedef union LCAC_SX3_TA_OVR_VAL__SI regLCAC_SX3_TA_OVR_VAL__SI; -typedef union LCAC_SX3_TCC_CNTL__SI regLCAC_SX3_TCC_CNTL__SI; -typedef union LCAC_SX3_TCC_OVR_SEL__SI regLCAC_SX3_TCC_OVR_SEL__SI; -typedef union LCAC_SX3_TCC_OVR_VAL__SI regLCAC_SX3_TCC_OVR_VAL__SI; -typedef union LCAC_SX3_TCP_CNTL__SI regLCAC_SX3_TCP_CNTL__SI; -typedef union LCAC_SX3_TCP_OVR_SEL__SI regLCAC_SX3_TCP_OVR_SEL__SI; -typedef union LCAC_SX3_TCP_OVR_VAL__SI regLCAC_SX3_TCP_OVR_VAL__SI; -typedef union LCLK_ACTIVITY_CNT_CNTL__CI__VI regLCLK_ACTIVITY_CNT_CNTL__CI__VI; -typedef union LCLK_ACTIVITY_CNT_STATUS__CI__VI regLCLK_ACTIVITY_CNT_STATUS__CI__VI; -typedef union LCLK_AM_CNTL__CI__VI regLCLK_AM_CNTL__CI__VI; -typedef union LCLK_DEEP_SLEEP_CNTL2__CI__VI regLCLK_DEEP_SLEEP_CNTL2__CI__VI; -typedef union LCLK_DEEP_SLEEP_CNTL__CI__VI regLCLK_DEEP_SLEEP_CNTL__CI__VI; -typedef union LCLK_PERIOD_CNT_STATUS__CI__VI regLCLK_PERIOD_CNT_STATUS__CI__VI; -typedef union LINK_CAP regLINK_CAP; -typedef union LINK_CAP2__CI__VI regLINK_CAP2__CI__VI; -typedef union LINK_CAP2__SI regLINK_CAP2__SI; -typedef union LINK_CNTL regLINK_CNTL; -typedef union LINK_CNTL2 regLINK_CNTL2; -typedef union LINK_STATUS regLINK_STATUS; -typedef union LINK_STATUS2 regLINK_STATUS2; -typedef union LNCNT_CONTROL__CI regLNCNT_CONTROL__CI; -typedef union LNCNT_CONTROL__VI regLNCNT_CONTROL__VI; -typedef union LPML_SCALAR_1__CI regLPML_SCALAR_1__CI; -typedef union LPML_SCALAR_1__VI regLPML_SCALAR_1__VI; -typedef union LPML_SCALAR_2__CI regLPML_SCALAR_2__CI; -typedef union LPML_SCALAR_2__VI regLPML_SCALAR_2__VI; -typedef union LPMV_SCALAR_1__CI regLPMV_SCALAR_1__CI; -typedef union LPMV_SCALAR_1__VI regLPMV_SCALAR_1__VI; -typedef union LPMV_SCALAR_2__CI regLPMV_SCALAR_2__CI; -typedef union LPMV_SCALAR_2__VI regLPMV_SCALAR_2__VI; -typedef union LUMA_BOT_ADDR__SI regLUMA_BOT_ADDR__SI; -typedef union LUMA_TOP_ADDR__SI regLUMA_TOP_ADDR__SI; -typedef union LVDSA_PREEMPHASIS_CONTROL__SI regLVDSA_PREEMPHASIS_CONTROL__SI; -typedef union LVDSA_TRANSMITTER_ADJUST__SI regLVDSA_TRANSMITTER_ADJUST__SI; -typedef union LVDSB_PREEMPHASIS_CONTROL__SI regLVDSB_PREEMPHASIS_CONTROL__SI; -typedef union LVDSB_TRANSMITTER_ADJUST__SI regLVDSB_TRANSMITTER_ADJUST__SI; -typedef union LVDS_DATA_CNTL__SI regLVDS_DATA_CNTL__SI; -typedef union LVTMA_PWRSEQ_CNTL__SI regLVTMA_PWRSEQ_CNTL__SI; -typedef union LVTMA_PWRSEQ_DELAY1__SI regLVTMA_PWRSEQ_DELAY1__SI; -typedef union LVTMA_PWRSEQ_DELAY2__SI regLVTMA_PWRSEQ_DELAY2__SI; -typedef union LVTMA_PWRSEQ_REF_DIV__SI regLVTMA_PWRSEQ_REF_DIV__SI; -typedef union LVTMA_PWRSEQ_STATE__SI regLVTMA_PWRSEQ_STATE__SI; -typedef union LX0 regLX0; -typedef union LX1 regLX1; -typedef union LX2 regLX2; -typedef union LX3 regLX3; -typedef union MAJOR_VERSION__SI regMAJOR_VERSION__SI; -typedef union MASTER_COMM_CMD_REG__SI regMASTER_COMM_CMD_REG__SI; -typedef union MASTER_COMM_CNTL_REG__SI regMASTER_COMM_CNTL_REG__SI; -typedef union MASTER_COMM_DATA_REG1__SI regMASTER_COMM_DATA_REG1__SI; -typedef union MASTER_COMM_DATA_REG2__SI regMASTER_COMM_DATA_REG2__SI; -typedef union MASTER_COMM_DATA_REG3__SI regMASTER_COMM_DATA_REG3__SI; -typedef union MASTER_CREDIT_CNTL regMASTER_CREDIT_CNTL; -typedef union MASTER_UPDATE_LOCK__SI regMASTER_UPDATE_LOCK__SI; -typedef union MASTER_UPDATE_MODE__SI regMASTER_UPDATE_MODE__SI; -typedef union MAX_LATENCY regMAX_LATENCY; -typedef union MB_DONE__SI regMB_DONE__SI; -typedef union MCIF_CONTROL__SI regMCIF_CONTROL__SI; -typedef union MCIF_TEST_DEBUG_DATA__SI regMCIF_TEST_DEBUG_DATA__SI; -typedef union MCIF_TEST_DEBUG_INDEX__SI regMCIF_TEST_DEBUG_INDEX__SI; -typedef union MCIF_WRITE_COMBINE_CONTROL__SI regMCIF_WRITE_COMBINE_CONTROL__SI; -typedef union MCLK_AM_CNTL__CI__VI regMCLK_AM_CNTL__CI__VI; -typedef union MCLK_AM_PERIOD_CNT__CI__VI regMCLK_AM_PERIOD_CNT__CI__VI; -typedef union MCLK_AM_READ_CNT__CI__VI regMCLK_AM_READ_CNT__CI__VI; -typedef union MCLK_AM_WRITE_CNT__CI__VI regMCLK_AM_WRITE_CNT__CI__VI; -typedef union MCLK_CHG_CNT__SI regMCLK_CHG_CNT__SI; -typedef union MCLK_PWRMGT_CNTL__SI__CI regMCLK_PWRMGT_CNTL__SI__CI; -typedef union MC_ARB_ADDR_HASH regMC_ARB_ADDR_HASH; -typedef union MC_ARB_ADDR_SWIZ0__CI__VI regMC_ARB_ADDR_SWIZ0__CI__VI; -typedef union MC_ARB_ADDR_SWIZ1__CI__VI regMC_ARB_ADDR_SWIZ1__CI__VI; -typedef union MC_ARB_AGE_CNTL__CI__VI regMC_ARB_AGE_CNTL__CI__VI; -typedef union MC_ARB_AGE_RD regMC_ARB_AGE_RD; -typedef union MC_ARB_AGE_WR regMC_ARB_AGE_WR; -typedef union MC_ARB_BANKMAP regMC_ARB_BANKMAP; -typedef union MC_ARB_BURST_TIME regMC_ARB_BURST_TIME; -typedef union MC_ARB_BUSY_STATUS__CI regMC_ARB_BUSY_STATUS__CI; -typedef union MC_ARB_BUSY_STATUS__VI regMC_ARB_BUSY_STATUS__VI; -typedef union MC_ARB_CAC_CNTL regMC_ARB_CAC_CNTL; -typedef union MC_ARB_CG__CI__VI regMC_ARB_CG__CI__VI; -typedef union MC_ARB_CG__SI regMC_ARB_CG__SI; -typedef union MC_ARB_DRAM_TIMING regMC_ARB_DRAM_TIMING; -typedef union MC_ARB_DRAM_TIMING2 regMC_ARB_DRAM_TIMING2; -typedef union MC_ARB_DRAM_TIMING2_1 regMC_ARB_DRAM_TIMING2_1; -typedef union MC_ARB_DRAM_TIMING2_2__SI regMC_ARB_DRAM_TIMING2_2__SI; -typedef union MC_ARB_DRAM_TIMING2_3__SI regMC_ARB_DRAM_TIMING2_3__SI; -typedef union MC_ARB_DRAM_TIMING_1 regMC_ARB_DRAM_TIMING_1; -typedef union MC_ARB_DRAM_TIMING_2__SI regMC_ARB_DRAM_TIMING_2__SI; -typedef union MC_ARB_DRAM_TIMING_3__SI regMC_ARB_DRAM_TIMING_3__SI; -typedef union MC_ARB_FED_CNTL regMC_ARB_FED_CNTL; -typedef union MC_ARB_GDEC_RD_CNTL regMC_ARB_GDEC_RD_CNTL; -typedef union MC_ARB_GDEC_WR_CNTL regMC_ARB_GDEC_WR_CNTL; -typedef union MC_ARB_GECC2 regMC_ARB_GECC2; -typedef union MC_ARB_GECC2_CLI regMC_ARB_GECC2_CLI; -typedef union MC_ARB_GECC2_DEBUG regMC_ARB_GECC2_DEBUG; -typedef union MC_ARB_GECC2_DEBUG2 regMC_ARB_GECC2_DEBUG2; -typedef union MC_ARB_GECC2_MISC__SI__CI regMC_ARB_GECC2_MISC__SI__CI; -typedef union MC_ARB_GECC2_MISC__VI regMC_ARB_GECC2_MISC__VI; -typedef union MC_ARB_GECC2_STATUS regMC_ARB_GECC2_STATUS; -typedef union MC_ARB_HARSH_BWCNT0_RD__CI__VI regMC_ARB_HARSH_BWCNT0_RD__CI__VI; -typedef union MC_ARB_HARSH_BWCNT0_WR__CI__VI regMC_ARB_HARSH_BWCNT0_WR__CI__VI; -typedef union MC_ARB_HARSH_BWCNT1_RD__CI__VI regMC_ARB_HARSH_BWCNT1_RD__CI__VI; -typedef union MC_ARB_HARSH_BWCNT1_WR__CI__VI regMC_ARB_HARSH_BWCNT1_WR__CI__VI; -typedef union MC_ARB_HARSH_BWPERIOD0_RD__CI__VI regMC_ARB_HARSH_BWPERIOD0_RD__CI__VI; -typedef union MC_ARB_HARSH_BWPERIOD0_WR__CI__VI regMC_ARB_HARSH_BWPERIOD0_WR__CI__VI; -typedef union MC_ARB_HARSH_BWPERIOD1_RD__CI__VI regMC_ARB_HARSH_BWPERIOD1_RD__CI__VI; -typedef union MC_ARB_HARSH_BWPERIOD1_WR__CI__VI regMC_ARB_HARSH_BWPERIOD1_WR__CI__VI; -typedef union MC_ARB_HARSH_CTL_RD__CI__VI regMC_ARB_HARSH_CTL_RD__CI__VI; -typedef union MC_ARB_HARSH_CTL_WR__CI__VI regMC_ARB_HARSH_CTL_WR__CI__VI; -typedef union MC_ARB_HARSH_EN_RD__CI__VI regMC_ARB_HARSH_EN_RD__CI__VI; -typedef union MC_ARB_HARSH_EN_WR__CI__VI regMC_ARB_HARSH_EN_WR__CI__VI; -typedef union MC_ARB_HARSH_SAT0_RD__CI__VI regMC_ARB_HARSH_SAT0_RD__CI__VI; -typedef union MC_ARB_HARSH_SAT0_WR__CI__VI regMC_ARB_HARSH_SAT0_WR__CI__VI; -typedef union MC_ARB_HARSH_SAT1_RD__CI__VI regMC_ARB_HARSH_SAT1_RD__CI__VI; -typedef union MC_ARB_HARSH_SAT1_WR__CI__VI regMC_ARB_HARSH_SAT1_WR__CI__VI; -typedef union MC_ARB_HARSH_TX_HI0_RD__CI__VI regMC_ARB_HARSH_TX_HI0_RD__CI__VI; -typedef union MC_ARB_HARSH_TX_HI0_WR__CI__VI regMC_ARB_HARSH_TX_HI0_WR__CI__VI; -typedef union MC_ARB_HARSH_TX_HI1_RD__CI__VI regMC_ARB_HARSH_TX_HI1_RD__CI__VI; -typedef union MC_ARB_HARSH_TX_HI1_WR__CI__VI regMC_ARB_HARSH_TX_HI1_WR__CI__VI; -typedef union MC_ARB_HARSH_TX_LO0_RD__CI__VI regMC_ARB_HARSH_TX_LO0_RD__CI__VI; -typedef union MC_ARB_HARSH_TX_LO0_WR__CI__VI regMC_ARB_HARSH_TX_LO0_WR__CI__VI; -typedef union MC_ARB_HARSH_TX_LO1_RD__CI__VI regMC_ARB_HARSH_TX_LO1_RD__CI__VI; -typedef union MC_ARB_HARSH_TX_LO1_WR__CI__VI regMC_ARB_HARSH_TX_LO1_WR__CI__VI; -typedef union MC_ARB_LAZY0_RD regMC_ARB_LAZY0_RD; -typedef union MC_ARB_LAZY0_WR regMC_ARB_LAZY0_WR; -typedef union MC_ARB_LAZY1_RD regMC_ARB_LAZY1_RD; -typedef union MC_ARB_LAZY1_WR regMC_ARB_LAZY1_WR; -typedef union MC_ARB_LM_RD regMC_ARB_LM_RD; -typedef union MC_ARB_LM_WR regMC_ARB_LM_WR; -typedef union MC_ARB_MAX_LAT_CID__CI__VI regMC_ARB_MAX_LAT_CID__CI__VI; -typedef union MC_ARB_MAX_LAT_RSLT0__CI__VI regMC_ARB_MAX_LAT_RSLT0__CI__VI; -typedef union MC_ARB_MAX_LAT_RSLT1__CI__VI regMC_ARB_MAX_LAT_RSLT1__CI__VI; -typedef union MC_ARB_MINCLKS regMC_ARB_MINCLKS; -typedef union MC_ARB_MISC regMC_ARB_MISC; -typedef union MC_ARB_MISC2 regMC_ARB_MISC2; -typedef union MC_ARB_MISC3__CI regMC_ARB_MISC3__CI; -typedef union MC_ARB_MISC3__VI regMC_ARB_MISC3__VI; -typedef union MC_ARB_PERFCOUNTER0_CFG__CI__VI regMC_ARB_PERFCOUNTER0_CFG__CI__VI; -typedef union MC_ARB_PERFCOUNTER1_CFG__CI__VI regMC_ARB_PERFCOUNTER1_CFG__CI__VI; -typedef union MC_ARB_PERFCOUNTER2_CFG__CI__VI regMC_ARB_PERFCOUNTER2_CFG__CI__VI; -typedef union MC_ARB_PERFCOUNTER3_CFG__CI__VI regMC_ARB_PERFCOUNTER3_CFG__CI__VI; -typedef union MC_ARB_PERFCOUNTER_HI__CI__VI regMC_ARB_PERFCOUNTER_HI__CI__VI; -typedef union MC_ARB_PERFCOUNTER_LO__CI__VI regMC_ARB_PERFCOUNTER_LO__CI__VI; -typedef union MC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union MC_ARB_PERF_MON_CNTL0_ECC__CI regMC_ARB_PERF_MON_CNTL0_ECC__CI; -typedef union MC_ARB_PERF_MON_CNTL0__SI regMC_ARB_PERF_MON_CNTL0__SI; -typedef union MC_ARB_PERF_MON_CNTL1__SI regMC_ARB_PERF_MON_CNTL1__SI; -typedef union MC_ARB_PERF_MON_CNTL2__SI regMC_ARB_PERF_MON_CNTL2__SI; -typedef union MC_ARB_PERF_MON_RSLT0__SI regMC_ARB_PERF_MON_RSLT0__SI; -typedef union MC_ARB_PERF_MON_RSLT1__SI regMC_ARB_PERF_MON_RSLT1__SI; -typedef union MC_ARB_PERF_MON_RSLT2__SI regMC_ARB_PERF_MON_RSLT2__SI; -typedef union MC_ARB_PERF_MON_RSLT3__SI regMC_ARB_PERF_MON_RSLT3__SI; -typedef union MC_ARB_PM_CNTL__CI regMC_ARB_PM_CNTL__CI; -typedef union MC_ARB_PM_CNTL__VI regMC_ARB_PM_CNTL__VI; -typedef union MC_ARB_PM_CNTL__SI regMC_ARB_PM_CNTL__SI; -typedef union MC_ARB_POP regMC_ARB_POP; -typedef union MC_ARB_RAMCFG__CI__VI regMC_ARB_RAMCFG__CI__VI; -typedef union MC_ARB_RAMCFG__SI regMC_ARB_RAMCFG__SI; -typedef union MC_ARB_REFRESH_SCALE_CNTL__SI regMC_ARB_REFRESH_SCALE_CNTL__SI; -typedef union MC_ARB_REMREQ regMC_ARB_REMREQ; -typedef union MC_ARB_REPLAY regMC_ARB_REPLAY; -typedef union MC_ARB_RET_CREDITS2__CI__VI regMC_ARB_RET_CREDITS2__CI__VI; -typedef union MC_ARB_RET_CREDITS_RD regMC_ARB_RET_CREDITS_RD; -typedef union MC_ARB_RET_CREDITS_WR regMC_ARB_RET_CREDITS_WR; -typedef union MC_ARB_RFSH_CNTL regMC_ARB_RFSH_CNTL; -typedef union MC_ARB_RFSH_RATE regMC_ARB_RFSH_RATE; -typedef union MC_ARB_RSV0__SI regMC_ARB_RSV0__SI; -typedef union MC_ARB_RTT_CNTL0 regMC_ARB_RTT_CNTL0; -typedef union MC_ARB_RTT_CNTL1 regMC_ARB_RTT_CNTL1; -typedef union MC_ARB_RTT_CNTL2 regMC_ARB_RTT_CNTL2; -typedef union MC_ARB_RTT_DATA regMC_ARB_RTT_DATA; -typedef union MC_ARB_RTT_DEBUG regMC_ARB_RTT_DEBUG; -typedef union MC_ARB_SCRAMBLE_KEY0 regMC_ARB_SCRAMBLE_KEY0; -typedef union MC_ARB_SCRAMBLE_KEY1 regMC_ARB_SCRAMBLE_KEY1; -typedef union MC_ARB_SPARE0__SI regMC_ARB_SPARE0__SI; -typedef union MC_ARB_SPARE1__SI regMC_ARB_SPARE1__SI; -typedef union MC_ARB_SQM_CNTL__CI__VI regMC_ARB_SQM_CNTL__CI__VI; -typedef union MC_ARB_SQM_CNTL__SI regMC_ARB_SQM_CNTL__SI; -typedef union MC_ARB_SSM__CI regMC_ARB_SSM__CI; -typedef union MC_ARB_TM_CNTL_RD regMC_ARB_TM_CNTL_RD; -typedef union MC_ARB_TM_CNTL_WR regMC_ARB_TM_CNTL_WR; -typedef union MC_ARB_WCDR__SI__CI regMC_ARB_WCDR__SI__CI; -typedef union MC_ARB_WCDR_2__SI__CI regMC_ARB_WCDR_2__SI__CI; -typedef union MC_ARB_WTM_CNTL_RD regMC_ARB_WTM_CNTL_RD; -typedef union MC_ARB_WTM_CNTL_WR regMC_ARB_WTM_CNTL_WR; -typedef union MC_ARB_WTM_GRPWT_RD regMC_ARB_WTM_GRPWT_RD; -typedef union MC_ARB_WTM_GRPWT_WR regMC_ARB_WTM_GRPWT_WR; -typedef union MC_BIST_AUTO_CNTL__SI__CI regMC_BIST_AUTO_CNTL__SI__CI; -typedef union MC_BIST_CMD_CNTL__SI__CI regMC_BIST_CMD_CNTL__SI__CI; -typedef union MC_BIST_CMP_CNTL__SI__CI regMC_BIST_CMP_CNTL__SI__CI; -typedef union MC_BIST_CMP_CNTL_2__SI__CI regMC_BIST_CMP_CNTL_2__SI__CI; -typedef union MC_BIST_CNTL__SI__CI regMC_BIST_CNTL__SI__CI; -typedef union MC_BIST_DATA_MASK__SI__CI regMC_BIST_DATA_MASK__SI__CI; -typedef union MC_BIST_DATA_WORD0__SI__CI regMC_BIST_DATA_WORD0__SI__CI; -typedef union MC_BIST_DATA_WORD1__SI__CI regMC_BIST_DATA_WORD1__SI__CI; -typedef union MC_BIST_DATA_WORD2__SI__CI regMC_BIST_DATA_WORD2__SI__CI; -typedef union MC_BIST_DATA_WORD3__SI__CI regMC_BIST_DATA_WORD3__SI__CI; -typedef union MC_BIST_DATA_WORD4__SI__CI regMC_BIST_DATA_WORD4__SI__CI; -typedef union MC_BIST_DATA_WORD5__SI__CI regMC_BIST_DATA_WORD5__SI__CI; -typedef union MC_BIST_DATA_WORD6__SI__CI regMC_BIST_DATA_WORD6__SI__CI; -typedef union MC_BIST_DATA_WORD7__SI__CI regMC_BIST_DATA_WORD7__SI__CI; -typedef union MC_BIST_DIR_CNTL__SI__CI regMC_BIST_DIR_CNTL__SI__CI; -typedef union MC_BIST_EADDR__SI__CI regMC_BIST_EADDR__SI__CI; -typedef union MC_BIST_MISMATCH_ADDR__SI__CI regMC_BIST_MISMATCH_ADDR__SI__CI; -typedef union MC_BIST_RDATA_EDC__SI__CI regMC_BIST_RDATA_EDC__SI__CI; -typedef union MC_BIST_RDATA_MASK__SI__CI regMC_BIST_RDATA_MASK__SI__CI; -typedef union MC_BIST_RDATA_WORD0__SI__CI regMC_BIST_RDATA_WORD0__SI__CI; -typedef union MC_BIST_RDATA_WORD1__SI__CI regMC_BIST_RDATA_WORD1__SI__CI; -typedef union MC_BIST_RDATA_WORD2__SI__CI regMC_BIST_RDATA_WORD2__SI__CI; -typedef union MC_BIST_RDATA_WORD3__SI__CI regMC_BIST_RDATA_WORD3__SI__CI; -typedef union MC_BIST_RDATA_WORD4__SI__CI regMC_BIST_RDATA_WORD4__SI__CI; -typedef union MC_BIST_RDATA_WORD5__SI__CI regMC_BIST_RDATA_WORD5__SI__CI; -typedef union MC_BIST_RDATA_WORD6__SI__CI regMC_BIST_RDATA_WORD6__SI__CI; -typedef union MC_BIST_RDATA_WORD7__SI__CI regMC_BIST_RDATA_WORD7__SI__CI; -typedef union MC_BIST_SADDR__SI__CI regMC_BIST_SADDR__SI__CI; -typedef union MC_CG_CONFIG regMC_CG_CONFIG; -typedef union MC_CG_CONFIG_MCD regMC_CG_CONFIG_MCD; -typedef union MC_CG_DATAPORT regMC_CG_DATAPORT; -typedef union MC_CITF_CNTL__CI regMC_CITF_CNTL__CI; -typedef union MC_CITF_CNTL__VI regMC_CITF_CNTL__VI; -typedef union MC_CITF_CNTL__SI regMC_CITF_CNTL__SI; -typedef union MC_CITF_CREDITS_ARB_RD regMC_CITF_CREDITS_ARB_RD; -typedef union MC_CITF_CREDITS_ARB_WR__SI__CI regMC_CITF_CREDITS_ARB_WR__SI__CI; -typedef union MC_CITF_CREDITS_ARB_WR__VI regMC_CITF_CREDITS_ARB_WR__VI; -typedef union MC_CITF_CREDITS_VM regMC_CITF_CREDITS_VM; -typedef union MC_CITF_CREDITS_XBAR regMC_CITF_CREDITS_XBAR; -typedef union MC_CITF_DAGB_CNTL regMC_CITF_DAGB_CNTL; -typedef union MC_CITF_DAGB_DLY regMC_CITF_DAGB_DLY; -typedef union MC_CITF_INT_CREDITS regMC_CITF_INT_CREDITS; -typedef union MC_CITF_INT_CREDITS_WR__CI__VI regMC_CITF_INT_CREDITS_WR__CI__VI; -typedef union MC_CITF_MISC_RD_CG regMC_CITF_MISC_RD_CG; -typedef union MC_CITF_MISC_VM_CG regMC_CITF_MISC_VM_CG; -typedef union MC_CITF_MISC_WR_CG regMC_CITF_MISC_WR_CG; -typedef union MC_CITF_PERFCOUNTER0_CFG__CI__VI regMC_CITF_PERFCOUNTER0_CFG__CI__VI; -typedef union MC_CITF_PERFCOUNTER1_CFG__CI__VI regMC_CITF_PERFCOUNTER1_CFG__CI__VI; -typedef union MC_CITF_PERFCOUNTER2_CFG__CI__VI regMC_CITF_PERFCOUNTER2_CFG__CI__VI; -typedef union MC_CITF_PERFCOUNTER3_CFG__CI__VI regMC_CITF_PERFCOUNTER3_CFG__CI__VI; -typedef union MC_CITF_PERFCOUNTER_HI__CI__VI regMC_CITF_PERFCOUNTER_HI__CI__VI; -typedef union MC_CITF_PERFCOUNTER_LO__CI__VI regMC_CITF_PERFCOUNTER_LO__CI__VI; -typedef union MC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union MC_CITF_PERF_MON_CNTL0__SI regMC_CITF_PERF_MON_CNTL0__SI; -typedef union MC_CITF_PERF_MON_CNTL1__SI regMC_CITF_PERF_MON_CNTL1__SI; -typedef union MC_CITF_PERF_MON_CNTL2 regMC_CITF_PERF_MON_CNTL2; -typedef union MC_CITF_PERF_MON_RSLT0__SI regMC_CITF_PERF_MON_RSLT0__SI; -typedef union MC_CITF_PERF_MON_RSLT1__SI regMC_CITF_PERF_MON_RSLT1__SI; -typedef union MC_CITF_PERF_MON_RSLT2__SI__CI regMC_CITF_PERF_MON_RSLT2__SI__CI; -typedef union MC_CITF_PERF_MON_RSLT2__VI regMC_CITF_PERF_MON_RSLT2__VI; -typedef union MC_CITF_REMREQ regMC_CITF_REMREQ; -typedef union MC_CITF_RET_MODE regMC_CITF_RET_MODE; -typedef union MC_CITF_WTM_RD_CNTL__CI__VI regMC_CITF_WTM_RD_CNTL__CI__VI; -typedef union MC_CITF_WTM_RD_CNTL__SI regMC_CITF_WTM_RD_CNTL__SI; -typedef union MC_CITF_WTM_WR_CNTL__CI__VI regMC_CITF_WTM_WR_CNTL__CI__VI; -typedef union MC_CITF_WTM_WR_CNTL__SI regMC_CITF_WTM_WR_CNTL__SI; -typedef union MC_CITF_XTRA_ENABLE regMC_CITF_XTRA_ENABLE; -typedef union MC_CONFIG__SI__CI regMC_CONFIG__SI__CI; -typedef union MC_CONFIG__VI regMC_CONFIG__VI; -typedef union MC_CONFIG_MCD regMC_CONFIG_MCD; -typedef union MC_DC_INTERFACE_NACK_STATUS__SI regMC_DC_INTERFACE_NACK_STATUS__SI; -typedef union MC_DLB_CONFIG0__CI regMC_DLB_CONFIG0__CI; -typedef union MC_DLB_CONFIG1__CI regMC_DLB_CONFIG1__CI; -typedef union MC_DLB_MISCCTRL0__CI regMC_DLB_MISCCTRL0__CI; -typedef union MC_DLB_MISCCTRL1__CI regMC_DLB_MISCCTRL1__CI; -typedef union MC_DLB_MISCCTRL2__CI regMC_DLB_MISCCTRL2__CI; -typedef union MC_DLB_SETUPFIFO__CI regMC_DLB_SETUPFIFO__CI; -typedef union MC_DLB_SETUPSWEEP__CI regMC_DLB_SETUPSWEEP__CI; -typedef union MC_DLB_SETUP__CI regMC_DLB_SETUP__CI; -typedef union MC_DLB_STATUS_MISC0__CI regMC_DLB_STATUS_MISC0__CI; -typedef union MC_DLB_STATUS_MISC1__CI regMC_DLB_STATUS_MISC1__CI; -typedef union MC_DLB_STATUS_MISC2__CI regMC_DLB_STATUS_MISC2__CI; -typedef union MC_DLB_STATUS_MISC3__CI regMC_DLB_STATUS_MISC3__CI; -typedef union MC_DLB_STATUS_MISC4__CI regMC_DLB_STATUS_MISC4__CI; -typedef union MC_DLB_STATUS_MISC5__CI regMC_DLB_STATUS_MISC5__CI; -typedef union MC_DLB_STATUS_MISC6__CI regMC_DLB_STATUS_MISC6__CI; -typedef union MC_DLB_STATUS_MISC7__CI regMC_DLB_STATUS_MISC7__CI; -typedef union MC_DLB_STATUS__CI regMC_DLB_STATUS__CI; -typedef union MC_DLB_WRITE_MASK__CI regMC_DLB_WRITE_MASK__CI; -typedef union MC_HUB_MISC_DBG__SI__CI regMC_HUB_MISC_DBG__SI__CI; -typedef union MC_HUB_MISC_FRAMING regMC_HUB_MISC_FRAMING; -typedef union MC_HUB_MISC_HUB_CG regMC_HUB_MISC_HUB_CG; -typedef union MC_HUB_MISC_IDLE_STATUS__CI regMC_HUB_MISC_IDLE_STATUS__CI; -typedef union MC_HUB_MISC_IDLE_STATUS__VI regMC_HUB_MISC_IDLE_STATUS__VI; -typedef union MC_HUB_MISC_IDLE_STATUS__SI regMC_HUB_MISC_IDLE_STATUS__SI; -typedef union MC_HUB_MISC_OVERRIDE regMC_HUB_MISC_OVERRIDE; -typedef union MC_HUB_MISC_POWER regMC_HUB_MISC_POWER; -typedef union MC_HUB_MISC_SIP_CG regMC_HUB_MISC_SIP_CG; -typedef union MC_HUB_MISC_STATUS__SI__CI regMC_HUB_MISC_STATUS__SI__CI; -typedef union MC_HUB_MISC_STATUS__VI regMC_HUB_MISC_STATUS__VI; -typedef union MC_HUB_MISC_VM_CG regMC_HUB_MISC_VM_CG; -typedef union MC_HUB_PERFCOUNTER0_CFG__CI__VI regMC_HUB_PERFCOUNTER0_CFG__CI__VI; -typedef union MC_HUB_PERFCOUNTER1_CFG__CI__VI regMC_HUB_PERFCOUNTER1_CFG__CI__VI; -typedef union MC_HUB_PERFCOUNTER2_CFG__CI__VI regMC_HUB_PERFCOUNTER2_CFG__CI__VI; -typedef union MC_HUB_PERFCOUNTER3_CFG__CI__VI regMC_HUB_PERFCOUNTER3_CFG__CI__VI; -typedef union MC_HUB_PERFCOUNTER_HI__CI__VI regMC_HUB_PERFCOUNTER_HI__CI__VI; -typedef union MC_HUB_PERFCOUNTER_LO__CI__VI regMC_HUB_PERFCOUNTER_LO__CI__VI; -typedef union MC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union MC_HUB_RDREQ_ACPG_LIMIT__CI__VI regMC_HUB_RDREQ_ACPG_LIMIT__CI__VI; -typedef union MC_HUB_RDREQ_ACPG__CI__VI regMC_HUB_RDREQ_ACPG__CI__VI; -typedef union MC_HUB_RDREQ_ACPO__CI__VI regMC_HUB_RDREQ_ACPO__CI__VI; -typedef union MC_HUB_RDREQ_CNTL__SI__CI regMC_HUB_RDREQ_CNTL__SI__CI; -typedef union MC_HUB_RDREQ_CNTL__VI regMC_HUB_RDREQ_CNTL__VI; -typedef union MC_HUB_RDREQ_CPC__CI regMC_HUB_RDREQ_CPC__CI; -typedef union MC_HUB_RDREQ_CPF__CI regMC_HUB_RDREQ_CPF__CI; -typedef union MC_HUB_RDREQ_CPG__CI regMC_HUB_RDREQ_CPG__CI; -typedef union MC_HUB_RDREQ_CP__SI regMC_HUB_RDREQ_CP__SI; -typedef union MC_HUB_RDREQ_CREDITS regMC_HUB_RDREQ_CREDITS; -typedef union MC_HUB_RDREQ_CREDITS2__SI__CI regMC_HUB_RDREQ_CREDITS2__SI__CI; -typedef union MC_HUB_RDREQ_CREDITS2__VI regMC_HUB_RDREQ_CREDITS2__VI; -typedef union MC_HUB_RDREQ_DMIF regMC_HUB_RDREQ_DMIF; -typedef union MC_HUB_RDREQ_DMIF_LIMIT regMC_HUB_RDREQ_DMIF_LIMIT; -typedef union MC_HUB_RDREQ_DRMDMA0__SI regMC_HUB_RDREQ_DRMDMA0__SI; -typedef union MC_HUB_RDREQ_DRMDMA1__SI regMC_HUB_RDREQ_DRMDMA1__SI; -typedef union MC_HUB_RDREQ_GBL0 regMC_HUB_RDREQ_GBL0; -typedef union MC_HUB_RDREQ_GBL1 regMC_HUB_RDREQ_GBL1; -typedef union MC_HUB_RDREQ_HDP regMC_HUB_RDREQ_HDP; -typedef union MC_HUB_RDREQ_IA0__CI regMC_HUB_RDREQ_IA0__CI; -typedef union MC_HUB_RDREQ_IA1__CI regMC_HUB_RDREQ_IA1__CI; -typedef union MC_HUB_RDREQ_IA__CI regMC_HUB_RDREQ_IA__CI; -typedef union MC_HUB_RDREQ_MCDW__SI__CI regMC_HUB_RDREQ_MCDW__SI__CI; -typedef union MC_HUB_RDREQ_MCDW__VI regMC_HUB_RDREQ_MCDW__VI; -typedef union MC_HUB_RDREQ_MCDX__SI__CI regMC_HUB_RDREQ_MCDX__SI__CI; -typedef union MC_HUB_RDREQ_MCDX__VI regMC_HUB_RDREQ_MCDX__VI; -typedef union MC_HUB_RDREQ_MCDY__SI__CI regMC_HUB_RDREQ_MCDY__SI__CI; -typedef union MC_HUB_RDREQ_MCDY__VI regMC_HUB_RDREQ_MCDY__VI; -typedef union MC_HUB_RDREQ_MCDZ__SI__CI regMC_HUB_RDREQ_MCDZ__SI__CI; -typedef union MC_HUB_RDREQ_MCDZ__VI regMC_HUB_RDREQ_MCDZ__VI; -typedef union MC_HUB_RDREQ_MCIF regMC_HUB_RDREQ_MCIF; -typedef union MC_HUB_RDREQ_RLC regMC_HUB_RDREQ_RLC; -typedef union MC_HUB_RDREQ_SAM__CI regMC_HUB_RDREQ_SAM__CI; -typedef union MC_HUB_RDREQ_SDMA0__CI__VI regMC_HUB_RDREQ_SDMA0__CI__VI; -typedef union MC_HUB_RDREQ_SDMA1__CI__VI regMC_HUB_RDREQ_SDMA1__CI__VI; -typedef union MC_HUB_RDREQ_SEM regMC_HUB_RDREQ_SEM; -typedef union MC_HUB_RDREQ_SIP__SI__CI regMC_HUB_RDREQ_SIP__SI__CI; -typedef union MC_HUB_RDREQ_SIP__VI regMC_HUB_RDREQ_SIP__VI; -typedef union MC_HUB_RDREQ_SMU regMC_HUB_RDREQ_SMU; -typedef union MC_HUB_RDREQ_STATUS__SI__CI regMC_HUB_RDREQ_STATUS__SI__CI; -typedef union MC_HUB_RDREQ_STATUS__VI regMC_HUB_RDREQ_STATUS__VI; -typedef union MC_HUB_RDREQ_UMC regMC_HUB_RDREQ_UMC; -typedef union MC_HUB_RDREQ_UVD regMC_HUB_RDREQ_UVD; -typedef union MC_HUB_RDREQ_VCE__SI__CI regMC_HUB_RDREQ_VCE__SI__CI; -typedef union MC_HUB_RDREQ_VCEU__SI__CI regMC_HUB_RDREQ_VCEU__SI__CI; -typedef union MC_HUB_RDREQ_VGT__SI regMC_HUB_RDREQ_VGT__SI; -typedef union MC_HUB_RDREQ_VMC regMC_HUB_RDREQ_VMC; -typedef union MC_HUB_RDREQ_WTM_CNTL regMC_HUB_RDREQ_WTM_CNTL; -typedef union MC_HUB_RDREQ_XDMAM regMC_HUB_RDREQ_XDMAM; -typedef union MC_HUB_SHARED_DAGB_DLY regMC_HUB_SHARED_DAGB_DLY; -typedef union MC_HUB_WDP_ACPG__CI__VI regMC_HUB_WDP_ACPG__CI__VI; -typedef union MC_HUB_WDP_ACPO__CI__VI regMC_HUB_WDP_ACPO__CI__VI; -typedef union MC_HUB_WDP_BP regMC_HUB_WDP_BP; -typedef union MC_HUB_WDP_CNTL regMC_HUB_WDP_CNTL; -typedef union MC_HUB_WDP_CPC__CI regMC_HUB_WDP_CPC__CI; -typedef union MC_HUB_WDP_CPF__CI regMC_HUB_WDP_CPF__CI; -typedef union MC_HUB_WDP_CPG__CI regMC_HUB_WDP_CPG__CI; -typedef union MC_HUB_WDP_CP__SI regMC_HUB_WDP_CP__SI; -typedef union MC_HUB_WDP_CREDITS regMC_HUB_WDP_CREDITS; -typedef union MC_HUB_WDP_DRMDMA0__SI regMC_HUB_WDP_DRMDMA0__SI; -typedef union MC_HUB_WDP_DRMDMA1__SI regMC_HUB_WDP_DRMDMA1__SI; -typedef union MC_HUB_WDP_ERR regMC_HUB_WDP_ERR; -typedef union MC_HUB_WDP_GBL0 regMC_HUB_WDP_GBL0; -typedef union MC_HUB_WDP_GBL1 regMC_HUB_WDP_GBL1; -typedef union MC_HUB_WDP_HDP regMC_HUB_WDP_HDP; -typedef union MC_HUB_WDP_IH regMC_HUB_WDP_IH; -typedef union MC_HUB_WDP_MCDW regMC_HUB_WDP_MCDW; -typedef union MC_HUB_WDP_MCDX regMC_HUB_WDP_MCDX; -typedef union MC_HUB_WDP_MCDY regMC_HUB_WDP_MCDY; -typedef union MC_HUB_WDP_MCDZ regMC_HUB_WDP_MCDZ; -typedef union MC_HUB_WDP_MCIF regMC_HUB_WDP_MCIF; -typedef union MC_HUB_WDP_MGPU__SI__CI regMC_HUB_WDP_MGPU__SI__CI; -typedef union MC_HUB_WDP_MGPU2__SI__CI regMC_HUB_WDP_MGPU2__SI__CI; -typedef union MC_HUB_WDP_RLC regMC_HUB_WDP_RLC; -typedef union MC_HUB_WDP_SAM__CI regMC_HUB_WDP_SAM__CI; -typedef union MC_HUB_WDP_SDMA0__CI__VI regMC_HUB_WDP_SDMA0__CI__VI; -typedef union MC_HUB_WDP_SDMA1__CI__VI regMC_HUB_WDP_SDMA1__CI__VI; -typedef union MC_HUB_WDP_SEM regMC_HUB_WDP_SEM; -typedef union MC_HUB_WDP_SH0 regMC_HUB_WDP_SH0; -typedef union MC_HUB_WDP_SH1 regMC_HUB_WDP_SH1; -typedef union MC_HUB_WDP_SH2__CI__VI regMC_HUB_WDP_SH2__CI__VI; -typedef union MC_HUB_WDP_SH3__CI__VI regMC_HUB_WDP_SH3__CI__VI; -typedef union MC_HUB_WDP_SIP regMC_HUB_WDP_SIP; -typedef union MC_HUB_WDP_SMU regMC_HUB_WDP_SMU; -typedef union MC_HUB_WDP_STATUS__SI__CI regMC_HUB_WDP_STATUS__SI__CI; -typedef union MC_HUB_WDP_STATUS__VI regMC_HUB_WDP_STATUS__VI; -typedef union MC_HUB_WDP_UMC regMC_HUB_WDP_UMC; -typedef union MC_HUB_WDP_UVD regMC_HUB_WDP_UVD; -typedef union MC_HUB_WDP_VCE__SI__CI regMC_HUB_WDP_VCE__SI__CI; -typedef union MC_HUB_WDP_VCEU__SI__CI regMC_HUB_WDP_VCEU__SI__CI; -typedef union MC_HUB_WDP_WTM_CNTL regMC_HUB_WDP_WTM_CNTL; -typedef union MC_HUB_WDP_XDMA regMC_HUB_WDP_XDMA; -typedef union MC_HUB_WDP_XDMAM regMC_HUB_WDP_XDMAM; -typedef union MC_HUB_WDP_XDP regMC_HUB_WDP_XDP; -typedef union MC_HUB_WRRET_CNTL regMC_HUB_WRRET_CNTL; -typedef union MC_HUB_WRRET_MCDW regMC_HUB_WRRET_MCDW; -typedef union MC_HUB_WRRET_MCDX regMC_HUB_WRRET_MCDX; -typedef union MC_HUB_WRRET_MCDY regMC_HUB_WRRET_MCDY; -typedef union MC_HUB_WRRET_MCDZ regMC_HUB_WRRET_MCDZ; -typedef union MC_HUB_WRRET_STATUS regMC_HUB_WRRET_STATUS; -typedef union MC_IMP_CNTL__SI__CI regMC_IMP_CNTL__SI__CI; -typedef union MC_IMP_DEBUG__SI__CI regMC_IMP_DEBUG__SI__CI; -typedef union MC_IMP_DQ_STATUS__SI__CI regMC_IMP_DQ_STATUS__SI__CI; -typedef union MC_IMP_STATUS__SI__CI regMC_IMP_STATUS__SI__CI; -typedef union MC_IO_APHY_STR_CNTL_D0__SI__CI regMC_IO_APHY_STR_CNTL_D0__SI__CI; -typedef union MC_IO_APHY_STR_CNTL_D1__SI__CI regMC_IO_APHY_STR_CNTL_D1__SI__CI; -typedef union MC_IO_CDRCNTL1_D0__SI__CI regMC_IO_CDRCNTL1_D0__SI__CI; -typedef union MC_IO_CDRCNTL1_D1__SI__CI regMC_IO_CDRCNTL1_D1__SI__CI; -typedef union MC_IO_CDRCNTL2_D0__SI__CI regMC_IO_CDRCNTL2_D0__SI__CI; -typedef union MC_IO_CDRCNTL2_D1__SI__CI regMC_IO_CDRCNTL2_D1__SI__CI; -typedef union MC_IO_CDRCNTL_D0__SI__CI regMC_IO_CDRCNTL_D0__SI__CI; -typedef union MC_IO_CDRCNTL_D1__SI__CI regMC_IO_CDRCNTL_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_CLKSEL_D0__SI__CI regMC_IO_DEBUG_ACMD_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_CLKSEL_D1__SI__CI regMC_IO_DEBUG_ACMD_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_MISC_D0__SI__CI regMC_IO_DEBUG_ACMD_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_MISC_D1__SI__CI regMC_IO_DEBUG_ACMD_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_OFSCAL_D0__SI__CI regMC_IO_DEBUG_ACMD_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_OFSCAL_D1__SI__CI regMC_IO_DEBUG_ACMD_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_RXPHASE_D0__SI__CI regMC_IO_DEBUG_ACMD_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_RXPHASE_D1__SI__CI regMC_IO_DEBUG_ACMD_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXPHASE_D0__SI__CI regMC_IO_DEBUG_ACMD_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXPHASE_D1__SI__CI regMC_IO_DEBUG_ACMD_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXSLF_D0__SI__CI regMC_IO_DEBUG_ACMD_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_ACMD_TXSLF_D1__SI__CI regMC_IO_DEBUG_ACMD_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_CLKSEL_D0__SI__CI regMC_IO_DEBUG_ADDRH_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_CLKSEL_D1__SI__CI regMC_IO_DEBUG_ADDRH_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_MISC_D0__SI__CI regMC_IO_DEBUG_ADDRH_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_MISC_D1__SI__CI regMC_IO_DEBUG_ADDRH_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_RXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRH_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_RXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRH_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXSLF_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRH_TXSLF_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_CLKSEL_D0__SI__CI regMC_IO_DEBUG_ADDRL_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_CLKSEL_D1__SI__CI regMC_IO_DEBUG_ADDRL_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_MISC_D0__SI__CI regMC_IO_DEBUG_ADDRL_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_MISC_D1__SI__CI regMC_IO_DEBUG_ADDRL_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_RXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRL_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_RXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRL_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXSLF_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_ADDRL_TXSLF_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_CK_CLKSEL_D0__SI__CI regMC_IO_DEBUG_CK_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_CK_CLKSEL_D1__SI__CI regMC_IO_DEBUG_CK_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_CK_MISC_D0__SI__CI regMC_IO_DEBUG_CK_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_CK_MISC_D1__SI__CI regMC_IO_DEBUG_CK_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_CK_RXPHASE_D0__SI__CI regMC_IO_DEBUG_CK_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_CK_RXPHASE_D1__SI__CI regMC_IO_DEBUG_CK_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_CK_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_CK_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_CK_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_CK_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_CK_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_CK_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_CK_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_CK_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_CK_TXPHASE_D0__SI__CI regMC_IO_DEBUG_CK_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_CK_TXPHASE_D1__SI__CI regMC_IO_DEBUG_CK_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_CK_TXSLF_D0__SI__CI regMC_IO_DEBUG_CK_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_CK_TXSLF_D1__SI__CI regMC_IO_DEBUG_CK_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_CLKSEL_D0__SI__CI regMC_IO_DEBUG_CMD_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_CLKSEL_D1__SI__CI regMC_IO_DEBUG_CMD_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_MISC_D0__SI__CI regMC_IO_DEBUG_CMD_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_MISC_D1__SI__CI regMC_IO_DEBUG_CMD_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_OFSCAL_D0__SI__CI regMC_IO_DEBUG_CMD_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_OFSCAL_D1__SI__CI regMC_IO_DEBUG_CMD_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_RXPHASE_D0__SI__CI regMC_IO_DEBUG_CMD_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_RXPHASE_D1__SI__CI regMC_IO_DEBUG_CMD_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_RX_EQ_D0__SI__CI regMC_IO_DEBUG_CMD_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_RX_EQ_D1__SI__CI regMC_IO_DEBUG_CMD_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_CMD_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_CMD_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_CMD_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_CMD_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXPHASE_D0__SI__CI regMC_IO_DEBUG_CMD_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXPHASE_D1__SI__CI regMC_IO_DEBUG_CMD_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXSLF_D0__SI__CI regMC_IO_DEBUG_CMD_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_CMD_TXSLF_D1__SI__CI regMC_IO_DEBUG_CMD_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DBI_CDR_PHSIZE_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DBI_CDR_PHSIZE_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DBI_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DBI_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_MISC_D0__SI__CI regMC_IO_DEBUG_DBI_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_MISC_D1__SI__CI regMC_IO_DEBUG_DBI_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DBI_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DBI_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DBI_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DBI_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DBI_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DBI_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DBI_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DBI_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DBI_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DBI_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DBI_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DBI_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DBI_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DBI_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXSLF_D0__SI__CI regMC_IO_DEBUG_DBI_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DBI_TXSLF_D1__SI__CI regMC_IO_DEBUG_DBI_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_DQ0_RX_DYN_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_DQ0_RX_DYN_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_DQ0_RX_EQ_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_DQ0_RX_EQ_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_DQ1_RX_DYN_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_DQ1_RX_DYN_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_DQ1_RX_EQ_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_DQ1_RX_EQ_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB0H_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB0H_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB0H_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB0H_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB0H_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB0H_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0H_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0H_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB0H_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB0H_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB0L_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB0L_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB0L_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB0L_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB0L_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB0L_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0L_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0L_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB0L_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB0L_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB1H_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB1H_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB1H_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB1H_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB1H_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB1H_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1H_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1H_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB1H_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB1H_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB1L_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB1L_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB1L_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB1L_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB1L_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB1L_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1L_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1L_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB1L_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB1L_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB2H_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB2H_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB2H_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB2H_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB2H_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB2H_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2H_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2H_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB2H_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB2H_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB2L_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB2L_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB2L_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB2L_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB2L_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB2L_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2L_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2L_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB2L_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB2L_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB3H_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB3H_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB3H_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB3H_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB3H_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB3H_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3H_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3H_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB3H_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB3H_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB3L_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB3L_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB3L_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB3L_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB3L_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB3L_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3L_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3L_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB3L_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB3L_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__SI__CI; -typedef union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_EDC_CDR_PHSIZE_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_EDC_CDR_PHSIZE_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_CLKSEL_D0__SI__CI regMC_IO_DEBUG_EDC_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_CLKSEL_D1__SI__CI regMC_IO_DEBUG_EDC_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_MISC_D0__SI__CI regMC_IO_DEBUG_EDC_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_MISC_D1__SI__CI regMC_IO_DEBUG_EDC_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_OFSCAL_D0__SI__CI regMC_IO_DEBUG_EDC_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_OFSCAL_D1__SI__CI regMC_IO_DEBUG_EDC_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_RXPHASE_D0__SI__CI regMC_IO_DEBUG_EDC_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_RXPHASE_D1__SI__CI regMC_IO_DEBUG_EDC_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_EDC_RX_DYN_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_EDC_RX_DYN_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_EQ_D0__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_EQ_D1__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_EDC_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_EDC_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_EDC_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_EDC_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_EDC_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_EDC_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXPHASE_D0__SI__CI regMC_IO_DEBUG_EDC_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXPHASE_D1__SI__CI regMC_IO_DEBUG_EDC_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXSLF_D0__SI__CI regMC_IO_DEBUG_EDC_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_EDC_TXSLF_D1__SI__CI regMC_IO_DEBUG_EDC_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_UP_0__SI__CI regMC_IO_DEBUG_UP_0__SI__CI; -typedef union MC_IO_DEBUG_UP_1__SI__CI regMC_IO_DEBUG_UP_1__SI__CI; -typedef union MC_IO_DEBUG_UP_10__SI__CI regMC_IO_DEBUG_UP_10__SI__CI; -typedef union MC_IO_DEBUG_UP_100__SI__CI regMC_IO_DEBUG_UP_100__SI__CI; -typedef union MC_IO_DEBUG_UP_101__SI__CI regMC_IO_DEBUG_UP_101__SI__CI; -typedef union MC_IO_DEBUG_UP_102__SI__CI regMC_IO_DEBUG_UP_102__SI__CI; -typedef union MC_IO_DEBUG_UP_103__SI__CI regMC_IO_DEBUG_UP_103__SI__CI; -typedef union MC_IO_DEBUG_UP_104__SI__CI regMC_IO_DEBUG_UP_104__SI__CI; -typedef union MC_IO_DEBUG_UP_105__SI__CI regMC_IO_DEBUG_UP_105__SI__CI; -typedef union MC_IO_DEBUG_UP_106__SI__CI regMC_IO_DEBUG_UP_106__SI__CI; -typedef union MC_IO_DEBUG_UP_107__SI__CI regMC_IO_DEBUG_UP_107__SI__CI; -typedef union MC_IO_DEBUG_UP_108__SI__CI regMC_IO_DEBUG_UP_108__SI__CI; -typedef union MC_IO_DEBUG_UP_109__SI__CI regMC_IO_DEBUG_UP_109__SI__CI; -typedef union MC_IO_DEBUG_UP_11__SI__CI regMC_IO_DEBUG_UP_11__SI__CI; -typedef union MC_IO_DEBUG_UP_110__SI__CI regMC_IO_DEBUG_UP_110__SI__CI; -typedef union MC_IO_DEBUG_UP_111__SI__CI regMC_IO_DEBUG_UP_111__SI__CI; -typedef union MC_IO_DEBUG_UP_112__SI__CI regMC_IO_DEBUG_UP_112__SI__CI; -typedef union MC_IO_DEBUG_UP_113__SI__CI regMC_IO_DEBUG_UP_113__SI__CI; -typedef union MC_IO_DEBUG_UP_114__SI__CI regMC_IO_DEBUG_UP_114__SI__CI; -typedef union MC_IO_DEBUG_UP_115__SI__CI regMC_IO_DEBUG_UP_115__SI__CI; -typedef union MC_IO_DEBUG_UP_116__SI__CI regMC_IO_DEBUG_UP_116__SI__CI; -typedef union MC_IO_DEBUG_UP_117__SI__CI regMC_IO_DEBUG_UP_117__SI__CI; -typedef union MC_IO_DEBUG_UP_118__SI__CI regMC_IO_DEBUG_UP_118__SI__CI; -typedef union MC_IO_DEBUG_UP_119__SI__CI regMC_IO_DEBUG_UP_119__SI__CI; -typedef union MC_IO_DEBUG_UP_12__SI__CI regMC_IO_DEBUG_UP_12__SI__CI; -typedef union MC_IO_DEBUG_UP_120__SI__CI regMC_IO_DEBUG_UP_120__SI__CI; -typedef union MC_IO_DEBUG_UP_121__SI__CI regMC_IO_DEBUG_UP_121__SI__CI; -typedef union MC_IO_DEBUG_UP_122__SI__CI regMC_IO_DEBUG_UP_122__SI__CI; -typedef union MC_IO_DEBUG_UP_123__SI__CI regMC_IO_DEBUG_UP_123__SI__CI; -typedef union MC_IO_DEBUG_UP_124__SI__CI regMC_IO_DEBUG_UP_124__SI__CI; -typedef union MC_IO_DEBUG_UP_125__SI__CI regMC_IO_DEBUG_UP_125__SI__CI; -typedef union MC_IO_DEBUG_UP_126__SI__CI regMC_IO_DEBUG_UP_126__SI__CI; -typedef union MC_IO_DEBUG_UP_127__SI__CI regMC_IO_DEBUG_UP_127__SI__CI; -typedef union MC_IO_DEBUG_UP_128__SI__CI regMC_IO_DEBUG_UP_128__SI__CI; -typedef union MC_IO_DEBUG_UP_129__SI__CI regMC_IO_DEBUG_UP_129__SI__CI; -typedef union MC_IO_DEBUG_UP_13__SI__CI regMC_IO_DEBUG_UP_13__SI__CI; -typedef union MC_IO_DEBUG_UP_130__SI__CI regMC_IO_DEBUG_UP_130__SI__CI; -typedef union MC_IO_DEBUG_UP_131__SI__CI regMC_IO_DEBUG_UP_131__SI__CI; -typedef union MC_IO_DEBUG_UP_132__SI__CI regMC_IO_DEBUG_UP_132__SI__CI; -typedef union MC_IO_DEBUG_UP_133__SI__CI regMC_IO_DEBUG_UP_133__SI__CI; -typedef union MC_IO_DEBUG_UP_134__SI__CI regMC_IO_DEBUG_UP_134__SI__CI; -typedef union MC_IO_DEBUG_UP_135__SI__CI regMC_IO_DEBUG_UP_135__SI__CI; -typedef union MC_IO_DEBUG_UP_136__SI__CI regMC_IO_DEBUG_UP_136__SI__CI; -typedef union MC_IO_DEBUG_UP_137__SI__CI regMC_IO_DEBUG_UP_137__SI__CI; -typedef union MC_IO_DEBUG_UP_138__SI__CI regMC_IO_DEBUG_UP_138__SI__CI; -typedef union MC_IO_DEBUG_UP_139__SI__CI regMC_IO_DEBUG_UP_139__SI__CI; -typedef union MC_IO_DEBUG_UP_14__SI__CI regMC_IO_DEBUG_UP_14__SI__CI; -typedef union MC_IO_DEBUG_UP_140__SI__CI regMC_IO_DEBUG_UP_140__SI__CI; -typedef union MC_IO_DEBUG_UP_141__SI__CI regMC_IO_DEBUG_UP_141__SI__CI; -typedef union MC_IO_DEBUG_UP_142__SI__CI regMC_IO_DEBUG_UP_142__SI__CI; -typedef union MC_IO_DEBUG_UP_143__SI__CI regMC_IO_DEBUG_UP_143__SI__CI; -typedef union MC_IO_DEBUG_UP_144__SI__CI regMC_IO_DEBUG_UP_144__SI__CI; -typedef union MC_IO_DEBUG_UP_145__SI__CI regMC_IO_DEBUG_UP_145__SI__CI; -typedef union MC_IO_DEBUG_UP_146__SI__CI regMC_IO_DEBUG_UP_146__SI__CI; -typedef union MC_IO_DEBUG_UP_147__SI__CI regMC_IO_DEBUG_UP_147__SI__CI; -typedef union MC_IO_DEBUG_UP_148__SI__CI regMC_IO_DEBUG_UP_148__SI__CI; -typedef union MC_IO_DEBUG_UP_149__SI__CI regMC_IO_DEBUG_UP_149__SI__CI; -typedef union MC_IO_DEBUG_UP_15__SI__CI regMC_IO_DEBUG_UP_15__SI__CI; -typedef union MC_IO_DEBUG_UP_150__SI__CI regMC_IO_DEBUG_UP_150__SI__CI; -typedef union MC_IO_DEBUG_UP_151__SI__CI regMC_IO_DEBUG_UP_151__SI__CI; -typedef union MC_IO_DEBUG_UP_152__SI__CI regMC_IO_DEBUG_UP_152__SI__CI; -typedef union MC_IO_DEBUG_UP_153__SI__CI regMC_IO_DEBUG_UP_153__SI__CI; -typedef union MC_IO_DEBUG_UP_154__SI__CI regMC_IO_DEBUG_UP_154__SI__CI; -typedef union MC_IO_DEBUG_UP_155__SI__CI regMC_IO_DEBUG_UP_155__SI__CI; -typedef union MC_IO_DEBUG_UP_156__SI__CI regMC_IO_DEBUG_UP_156__SI__CI; -typedef union MC_IO_DEBUG_UP_157__SI__CI regMC_IO_DEBUG_UP_157__SI__CI; -typedef union MC_IO_DEBUG_UP_158__SI__CI regMC_IO_DEBUG_UP_158__SI__CI; -typedef union MC_IO_DEBUG_UP_159__SI__CI regMC_IO_DEBUG_UP_159__SI__CI; -typedef union MC_IO_DEBUG_UP_16__SI__CI regMC_IO_DEBUG_UP_16__SI__CI; -typedef union MC_IO_DEBUG_UP_17__SI__CI regMC_IO_DEBUG_UP_17__SI__CI; -typedef union MC_IO_DEBUG_UP_18__SI__CI regMC_IO_DEBUG_UP_18__SI__CI; -typedef union MC_IO_DEBUG_UP_19__SI__CI regMC_IO_DEBUG_UP_19__SI__CI; -typedef union MC_IO_DEBUG_UP_2__SI__CI regMC_IO_DEBUG_UP_2__SI__CI; -typedef union MC_IO_DEBUG_UP_20__SI__CI regMC_IO_DEBUG_UP_20__SI__CI; -typedef union MC_IO_DEBUG_UP_21__SI__CI regMC_IO_DEBUG_UP_21__SI__CI; -typedef union MC_IO_DEBUG_UP_22__SI__CI regMC_IO_DEBUG_UP_22__SI__CI; -typedef union MC_IO_DEBUG_UP_23__SI__CI regMC_IO_DEBUG_UP_23__SI__CI; -typedef union MC_IO_DEBUG_UP_24__SI__CI regMC_IO_DEBUG_UP_24__SI__CI; -typedef union MC_IO_DEBUG_UP_25__SI__CI regMC_IO_DEBUG_UP_25__SI__CI; -typedef union MC_IO_DEBUG_UP_26__SI__CI regMC_IO_DEBUG_UP_26__SI__CI; -typedef union MC_IO_DEBUG_UP_27__SI__CI regMC_IO_DEBUG_UP_27__SI__CI; -typedef union MC_IO_DEBUG_UP_28__SI__CI regMC_IO_DEBUG_UP_28__SI__CI; -typedef union MC_IO_DEBUG_UP_29__SI__CI regMC_IO_DEBUG_UP_29__SI__CI; -typedef union MC_IO_DEBUG_UP_3__SI__CI regMC_IO_DEBUG_UP_3__SI__CI; -typedef union MC_IO_DEBUG_UP_30__SI__CI regMC_IO_DEBUG_UP_30__SI__CI; -typedef union MC_IO_DEBUG_UP_31__SI__CI regMC_IO_DEBUG_UP_31__SI__CI; -typedef union MC_IO_DEBUG_UP_32__SI__CI regMC_IO_DEBUG_UP_32__SI__CI; -typedef union MC_IO_DEBUG_UP_33__SI__CI regMC_IO_DEBUG_UP_33__SI__CI; -typedef union MC_IO_DEBUG_UP_34__SI__CI regMC_IO_DEBUG_UP_34__SI__CI; -typedef union MC_IO_DEBUG_UP_35__SI__CI regMC_IO_DEBUG_UP_35__SI__CI; -typedef union MC_IO_DEBUG_UP_36__SI__CI regMC_IO_DEBUG_UP_36__SI__CI; -typedef union MC_IO_DEBUG_UP_37__SI__CI regMC_IO_DEBUG_UP_37__SI__CI; -typedef union MC_IO_DEBUG_UP_38__SI__CI regMC_IO_DEBUG_UP_38__SI__CI; -typedef union MC_IO_DEBUG_UP_39__SI__CI regMC_IO_DEBUG_UP_39__SI__CI; -typedef union MC_IO_DEBUG_UP_4__SI__CI regMC_IO_DEBUG_UP_4__SI__CI; -typedef union MC_IO_DEBUG_UP_40__SI__CI regMC_IO_DEBUG_UP_40__SI__CI; -typedef union MC_IO_DEBUG_UP_41__SI__CI regMC_IO_DEBUG_UP_41__SI__CI; -typedef union MC_IO_DEBUG_UP_42__SI__CI regMC_IO_DEBUG_UP_42__SI__CI; -typedef union MC_IO_DEBUG_UP_43__SI__CI regMC_IO_DEBUG_UP_43__SI__CI; -typedef union MC_IO_DEBUG_UP_44__SI__CI regMC_IO_DEBUG_UP_44__SI__CI; -typedef union MC_IO_DEBUG_UP_45__SI__CI regMC_IO_DEBUG_UP_45__SI__CI; -typedef union MC_IO_DEBUG_UP_46__SI__CI regMC_IO_DEBUG_UP_46__SI__CI; -typedef union MC_IO_DEBUG_UP_47__SI__CI regMC_IO_DEBUG_UP_47__SI__CI; -typedef union MC_IO_DEBUG_UP_48__SI__CI regMC_IO_DEBUG_UP_48__SI__CI; -typedef union MC_IO_DEBUG_UP_49__SI__CI regMC_IO_DEBUG_UP_49__SI__CI; -typedef union MC_IO_DEBUG_UP_5__SI__CI regMC_IO_DEBUG_UP_5__SI__CI; -typedef union MC_IO_DEBUG_UP_50__SI__CI regMC_IO_DEBUG_UP_50__SI__CI; -typedef union MC_IO_DEBUG_UP_51__SI__CI regMC_IO_DEBUG_UP_51__SI__CI; -typedef union MC_IO_DEBUG_UP_52__SI__CI regMC_IO_DEBUG_UP_52__SI__CI; -typedef union MC_IO_DEBUG_UP_53__SI__CI regMC_IO_DEBUG_UP_53__SI__CI; -typedef union MC_IO_DEBUG_UP_54__SI__CI regMC_IO_DEBUG_UP_54__SI__CI; -typedef union MC_IO_DEBUG_UP_55__SI__CI regMC_IO_DEBUG_UP_55__SI__CI; -typedef union MC_IO_DEBUG_UP_56__SI__CI regMC_IO_DEBUG_UP_56__SI__CI; -typedef union MC_IO_DEBUG_UP_57__SI__CI regMC_IO_DEBUG_UP_57__SI__CI; -typedef union MC_IO_DEBUG_UP_58__SI__CI regMC_IO_DEBUG_UP_58__SI__CI; -typedef union MC_IO_DEBUG_UP_59__SI__CI regMC_IO_DEBUG_UP_59__SI__CI; -typedef union MC_IO_DEBUG_UP_6__SI__CI regMC_IO_DEBUG_UP_6__SI__CI; -typedef union MC_IO_DEBUG_UP_60__SI__CI regMC_IO_DEBUG_UP_60__SI__CI; -typedef union MC_IO_DEBUG_UP_61__SI__CI regMC_IO_DEBUG_UP_61__SI__CI; -typedef union MC_IO_DEBUG_UP_62__SI__CI regMC_IO_DEBUG_UP_62__SI__CI; -typedef union MC_IO_DEBUG_UP_63__SI__CI regMC_IO_DEBUG_UP_63__SI__CI; -typedef union MC_IO_DEBUG_UP_64__SI__CI regMC_IO_DEBUG_UP_64__SI__CI; -typedef union MC_IO_DEBUG_UP_65__SI__CI regMC_IO_DEBUG_UP_65__SI__CI; -typedef union MC_IO_DEBUG_UP_66__SI__CI regMC_IO_DEBUG_UP_66__SI__CI; -typedef union MC_IO_DEBUG_UP_67__SI__CI regMC_IO_DEBUG_UP_67__SI__CI; -typedef union MC_IO_DEBUG_UP_68__SI__CI regMC_IO_DEBUG_UP_68__SI__CI; -typedef union MC_IO_DEBUG_UP_69__SI__CI regMC_IO_DEBUG_UP_69__SI__CI; -typedef union MC_IO_DEBUG_UP_7__SI__CI regMC_IO_DEBUG_UP_7__SI__CI; -typedef union MC_IO_DEBUG_UP_70__SI__CI regMC_IO_DEBUG_UP_70__SI__CI; -typedef union MC_IO_DEBUG_UP_71__SI__CI regMC_IO_DEBUG_UP_71__SI__CI; -typedef union MC_IO_DEBUG_UP_72__SI__CI regMC_IO_DEBUG_UP_72__SI__CI; -typedef union MC_IO_DEBUG_UP_73__SI__CI regMC_IO_DEBUG_UP_73__SI__CI; -typedef union MC_IO_DEBUG_UP_74__SI__CI regMC_IO_DEBUG_UP_74__SI__CI; -typedef union MC_IO_DEBUG_UP_75__SI__CI regMC_IO_DEBUG_UP_75__SI__CI; -typedef union MC_IO_DEBUG_UP_76__SI__CI regMC_IO_DEBUG_UP_76__SI__CI; -typedef union MC_IO_DEBUG_UP_77__SI__CI regMC_IO_DEBUG_UP_77__SI__CI; -typedef union MC_IO_DEBUG_UP_78__SI__CI regMC_IO_DEBUG_UP_78__SI__CI; -typedef union MC_IO_DEBUG_UP_79__SI__CI regMC_IO_DEBUG_UP_79__SI__CI; -typedef union MC_IO_DEBUG_UP_8__SI__CI regMC_IO_DEBUG_UP_8__SI__CI; -typedef union MC_IO_DEBUG_UP_80__SI__CI regMC_IO_DEBUG_UP_80__SI__CI; -typedef union MC_IO_DEBUG_UP_81__SI__CI regMC_IO_DEBUG_UP_81__SI__CI; -typedef union MC_IO_DEBUG_UP_82__SI__CI regMC_IO_DEBUG_UP_82__SI__CI; -typedef union MC_IO_DEBUG_UP_83__SI__CI regMC_IO_DEBUG_UP_83__SI__CI; -typedef union MC_IO_DEBUG_UP_84__SI__CI regMC_IO_DEBUG_UP_84__SI__CI; -typedef union MC_IO_DEBUG_UP_85__SI__CI regMC_IO_DEBUG_UP_85__SI__CI; -typedef union MC_IO_DEBUG_UP_86__SI__CI regMC_IO_DEBUG_UP_86__SI__CI; -typedef union MC_IO_DEBUG_UP_87__SI__CI regMC_IO_DEBUG_UP_87__SI__CI; -typedef union MC_IO_DEBUG_UP_88__SI__CI regMC_IO_DEBUG_UP_88__SI__CI; -typedef union MC_IO_DEBUG_UP_89__SI__CI regMC_IO_DEBUG_UP_89__SI__CI; -typedef union MC_IO_DEBUG_UP_9__SI__CI regMC_IO_DEBUG_UP_9__SI__CI; -typedef union MC_IO_DEBUG_UP_90__SI__CI regMC_IO_DEBUG_UP_90__SI__CI; -typedef union MC_IO_DEBUG_UP_91__SI__CI regMC_IO_DEBUG_UP_91__SI__CI; -typedef union MC_IO_DEBUG_UP_92__SI__CI regMC_IO_DEBUG_UP_92__SI__CI; -typedef union MC_IO_DEBUG_UP_93__SI__CI regMC_IO_DEBUG_UP_93__SI__CI; -typedef union MC_IO_DEBUG_UP_94__SI__CI regMC_IO_DEBUG_UP_94__SI__CI; -typedef union MC_IO_DEBUG_UP_95__SI__CI regMC_IO_DEBUG_UP_95__SI__CI; -typedef union MC_IO_DEBUG_UP_96__SI__CI regMC_IO_DEBUG_UP_96__SI__CI; -typedef union MC_IO_DEBUG_UP_97__SI__CI regMC_IO_DEBUG_UP_97__SI__CI; -typedef union MC_IO_DEBUG_UP_98__SI__CI regMC_IO_DEBUG_UP_98__SI__CI; -typedef union MC_IO_DEBUG_UP_99__SI__CI regMC_IO_DEBUG_UP_99__SI__CI; -typedef union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_CLKSEL_D0__SI__CI regMC_IO_DEBUG_WCDR_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_CLKSEL_D1__SI__CI regMC_IO_DEBUG_WCDR_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_MISC_D0__SI__CI regMC_IO_DEBUG_WCDR_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_MISC_D1__SI__CI regMC_IO_DEBUG_WCDR_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_OFSCAL_D0__SI__CI regMC_IO_DEBUG_WCDR_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_OFSCAL_D1__SI__CI regMC_IO_DEBUG_WCDR_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RXPHASE_D0__SI__CI regMC_IO_DEBUG_WCDR_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RXPHASE_D1__SI__CI regMC_IO_DEBUG_WCDR_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_DYN_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_DYN_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_EQ_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_EQ_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_PM_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_PM_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXPHASE_D0__SI__CI regMC_IO_DEBUG_WCDR_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXPHASE_D1__SI__CI regMC_IO_DEBUG_WCDR_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXSLF_D0__SI__CI regMC_IO_DEBUG_WCDR_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_WCDR_TXSLF_D1__SI__CI regMC_IO_DEBUG_WCDR_TXSLF_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_CLKSEL_D0__SI__CI regMC_IO_DEBUG_WCK_CLKSEL_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_CLKSEL_D1__SI__CI regMC_IO_DEBUG_WCK_CLKSEL_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_MISC_D0__SI__CI regMC_IO_DEBUG_WCK_MISC_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_MISC_D1__SI__CI regMC_IO_DEBUG_WCK_MISC_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_OFSCAL_D0__SI__CI regMC_IO_DEBUG_WCK_OFSCAL_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_OFSCAL_D1__SI__CI regMC_IO_DEBUG_WCK_OFSCAL_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_RXPHASE_D0__SI__CI regMC_IO_DEBUG_WCK_RXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_RXPHASE_D1__SI__CI regMC_IO_DEBUG_WCK_RXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_RX_EQ_D0__SI__CI regMC_IO_DEBUG_WCK_RX_EQ_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_RX_EQ_D1__SI__CI regMC_IO_DEBUG_WCK_RX_EQ_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_WCK_RX_VREF_CAL_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_WCK_RX_VREF_CAL_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_WCK_TXBST_PD_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_WCK_TXBST_PD_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_WCK_TXBST_PU_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_WCK_TXBST_PU_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXPHASE_D0__SI__CI regMC_IO_DEBUG_WCK_TXPHASE_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXPHASE_D1__SI__CI regMC_IO_DEBUG_WCK_TXPHASE_D1__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXSLF_D0__SI__CI regMC_IO_DEBUG_WCK_TXSLF_D0__SI__CI; -typedef union MC_IO_DEBUG_WCK_TXSLF_D1__SI__CI regMC_IO_DEBUG_WCK_TXSLF_D1__SI__CI; -typedef union MC_IO_DPHY_STR_CNTL_D0__SI__CI regMC_IO_DPHY_STR_CNTL_D0__SI__CI; -typedef union MC_IO_DPHY_STR_CNTL_D1__SI__CI regMC_IO_DPHY_STR_CNTL_D1__SI__CI; -typedef union MC_IO_PAD_CNTL__SI__CI regMC_IO_PAD_CNTL__SI__CI; -typedef union MC_IO_PAD_CNTL_D0__SI__CI regMC_IO_PAD_CNTL_D0__SI__CI; -typedef union MC_IO_PAD_CNTL_D1__SI__CI regMC_IO_PAD_CNTL_D1__SI__CI; -typedef union MC_IO_RXCNTL1_DPHY0_D0__CI regMC_IO_RXCNTL1_DPHY0_D0__CI; -typedef union MC_IO_RXCNTL1_DPHY0_D0__SI regMC_IO_RXCNTL1_DPHY0_D0__SI; -typedef union MC_IO_RXCNTL1_DPHY0_D1__CI regMC_IO_RXCNTL1_DPHY0_D1__CI; -typedef union MC_IO_RXCNTL1_DPHY0_D1__SI regMC_IO_RXCNTL1_DPHY0_D1__SI; -typedef union MC_IO_RXCNTL1_DPHY1_D0__CI regMC_IO_RXCNTL1_DPHY1_D0__CI; -typedef union MC_IO_RXCNTL1_DPHY1_D0__SI regMC_IO_RXCNTL1_DPHY1_D0__SI; -typedef union MC_IO_RXCNTL1_DPHY1_D1__CI regMC_IO_RXCNTL1_DPHY1_D1__CI; -typedef union MC_IO_RXCNTL1_DPHY1_D1__SI regMC_IO_RXCNTL1_DPHY1_D1__SI; -typedef union MC_IO_RXCNTL_DPHY0_D0__SI__CI regMC_IO_RXCNTL_DPHY0_D0__SI__CI; -typedef union MC_IO_RXCNTL_DPHY0_D1__SI__CI regMC_IO_RXCNTL_DPHY0_D1__SI__CI; -typedef union MC_IO_RXCNTL_DPHY1_D0__SI__CI regMC_IO_RXCNTL_DPHY1_D0__SI__CI; -typedef union MC_IO_RXCNTL_DPHY1_D1__SI__CI regMC_IO_RXCNTL_DPHY1_D1__SI__CI; -typedef union MC_IO_TXCNTL_APHY_D0__SI__CI regMC_IO_TXCNTL_APHY_D0__SI__CI; -typedef union MC_IO_TXCNTL_APHY_D1__SI__CI regMC_IO_TXCNTL_APHY_D1__SI__CI; -typedef union MC_IO_TXCNTL_DPHY0_D0__SI__CI regMC_IO_TXCNTL_DPHY0_D0__SI__CI; -typedef union MC_IO_TXCNTL_DPHY0_D1__SI__CI regMC_IO_TXCNTL_DPHY0_D1__SI__CI; -typedef union MC_IO_TXCNTL_DPHY1_D0__SI__CI regMC_IO_TXCNTL_DPHY1_D0__SI__CI; -typedef union MC_IO_TXCNTL_DPHY1_D1__SI__CI regMC_IO_TXCNTL_DPHY1_D1__SI__CI; -typedef union MC_MCBVM_PERFCOUNTER0_CFG__CI__VI regMC_MCBVM_PERFCOUNTER0_CFG__CI__VI; -typedef union MC_MCBVM_PERFCOUNTER1_CFG__CI__VI regMC_MCBVM_PERFCOUNTER1_CFG__CI__VI; -typedef union MC_MCBVM_PERFCOUNTER2_CFG__CI__VI regMC_MCBVM_PERFCOUNTER2_CFG__CI__VI; -typedef union MC_MCBVM_PERFCOUNTER3_CFG__CI__VI regMC_MCBVM_PERFCOUNTER3_CFG__CI__VI; -typedef union MC_MCBVM_PERFCOUNTER_HI__CI__VI regMC_MCBVM_PERFCOUNTER_HI__CI__VI; -typedef union MC_MCBVM_PERFCOUNTER_LO__CI__VI regMC_MCBVM_PERFCOUNTER_LO__CI__VI; -typedef union MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union MC_MCDVM_PERFCOUNTER0_CFG__CI__VI regMC_MCDVM_PERFCOUNTER0_CFG__CI__VI; -typedef union MC_MCDVM_PERFCOUNTER1_CFG__CI__VI regMC_MCDVM_PERFCOUNTER1_CFG__CI__VI; -typedef union MC_MCDVM_PERFCOUNTER2_CFG__CI__VI regMC_MCDVM_PERFCOUNTER2_CFG__CI__VI; -typedef union MC_MCDVM_PERFCOUNTER3_CFG__CI__VI regMC_MCDVM_PERFCOUNTER3_CFG__CI__VI; -typedef union MC_MCDVM_PERFCOUNTER_HI__CI__VI regMC_MCDVM_PERFCOUNTER_HI__CI__VI; -typedef union MC_MCDVM_PERFCOUNTER_LO__CI__VI regMC_MCDVM_PERFCOUNTER_LO__CI__VI; -typedef union MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union MC_MEM_POWER_LS regMC_MEM_POWER_LS; -typedef union MC_NPL_STATUS__SI__CI regMC_NPL_STATUS__SI__CI; -typedef union MC_PHY_TIMING_2__SI__CI regMC_PHY_TIMING_2__SI__CI; -typedef union MC_PHY_TIMING_D0__SI__CI regMC_PHY_TIMING_D0__SI__CI; -typedef union MC_PHY_TIMING_D1__SI__CI regMC_PHY_TIMING_D1__SI__CI; -typedef union MC_PMG_AUTO_CFG__SI__CI regMC_PMG_AUTO_CFG__SI__CI; -typedef union MC_PMG_AUTO_CMD__SI__CI regMC_PMG_AUTO_CMD__SI__CI; -typedef union MC_PMG_CFG__SI__CI regMC_PMG_CFG__SI__CI; -typedef union MC_PMG_CMD_EMRS__SI__CI regMC_PMG_CMD_EMRS__SI__CI; -typedef union MC_PMG_CMD_MRS__SI__CI regMC_PMG_CMD_MRS__SI__CI; -typedef union MC_PMG_CMD_MRS1__SI__CI regMC_PMG_CMD_MRS1__SI__CI; -typedef union MC_PMG_CMD_MRS2__SI__CI regMC_PMG_CMD_MRS2__SI__CI; -typedef union MC_PWRMGT__CI__VI regMC_PWRMGT__CI__VI; -typedef union MC_RD_CB regMC_RD_CB; -typedef union MC_RD_DB regMC_RD_DB; -typedef union MC_RD_GRP_EXT regMC_RD_GRP_EXT; -typedef union MC_RD_GRP_GFX__CI regMC_RD_GRP_GFX__CI; -typedef union MC_RD_GRP_GFX__VI regMC_RD_GRP_GFX__VI; -typedef union MC_RD_GRP_GFX__SI regMC_RD_GRP_GFX__SI; -typedef union MC_RD_GRP_LCL regMC_RD_GRP_LCL; -typedef union MC_RD_GRP_OTH__CI regMC_RD_GRP_OTH__CI; -typedef union MC_RD_GRP_OTH__VI regMC_RD_GRP_OTH__VI; -typedef union MC_RD_GRP_OTH__SI regMC_RD_GRP_OTH__SI; -typedef union MC_RD_GRP_SYS__CI__VI regMC_RD_GRP_SYS__CI__VI; -typedef union MC_RD_GRP_SYS__SI regMC_RD_GRP_SYS__SI; -typedef union MC_RD_HUB regMC_RD_HUB; -typedef union MC_RD_TC0 regMC_RD_TC0; -typedef union MC_RD_TC1 regMC_RD_TC1; -typedef union MC_RPB_ARB_CNTL regMC_RPB_ARB_CNTL; -typedef union MC_RPB_BIF_CNTL regMC_RPB_BIF_CNTL; -typedef union MC_RPB_CID_QUEUE_EX regMC_RPB_CID_QUEUE_EX; -typedef union MC_RPB_CID_QUEUE_EX_DATA regMC_RPB_CID_QUEUE_EX_DATA; -typedef union MC_RPB_CID_QUEUE_RD regMC_RPB_CID_QUEUE_RD; -typedef union MC_RPB_CID_QUEUE_WR regMC_RPB_CID_QUEUE_WR; -typedef union MC_RPB_CONF regMC_RPB_CONF; -typedef union MC_RPB_DBG1 regMC_RPB_DBG1; -typedef union MC_RPB_EFF_CNTL regMC_RPB_EFF_CNTL; -typedef union MC_RPB_IF_CONF regMC_RPB_IF_CONF; -typedef union MC_RPB_PERFCOUNTER0_CFG__CI__VI regMC_RPB_PERFCOUNTER0_CFG__CI__VI; -typedef union MC_RPB_PERFCOUNTER1_CFG__CI__VI regMC_RPB_PERFCOUNTER1_CFG__CI__VI; -typedef union MC_RPB_PERFCOUNTER2_CFG__CI__VI regMC_RPB_PERFCOUNTER2_CFG__CI__VI; -typedef union MC_RPB_PERFCOUNTER3_CFG__CI__VI regMC_RPB_PERFCOUNTER3_CFG__CI__VI; -typedef union MC_RPB_PERFCOUNTER_HI__CI__VI regMC_RPB_PERFCOUNTER_HI__CI__VI; -typedef union MC_RPB_PERFCOUNTER_LO__CI__VI regMC_RPB_PERFCOUNTER_LO__CI__VI; -typedef union MC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union MC_RPB_PERF_COUNTER_CNTL regMC_RPB_PERF_COUNTER_CNTL; -typedef union MC_RPB_PERF_COUNTER_STATUS regMC_RPB_PERF_COUNTER_STATUS; -typedef union MC_RPB_RD_SWITCH_CNTL regMC_RPB_RD_SWITCH_CNTL; -typedef union MC_RPB_WR_COMBINE_CNTL regMC_RPB_WR_COMBINE_CNTL; -typedef union MC_RPB_WR_SWITCH_CNTL regMC_RPB_WR_SWITCH_CNTL; -typedef union MC_SEQ_BIT_REMAP_B0_D0__SI__CI regMC_SEQ_BIT_REMAP_B0_D0__SI__CI; -typedef union MC_SEQ_BIT_REMAP_B0_D1__SI__CI regMC_SEQ_BIT_REMAP_B0_D1__SI__CI; -typedef union MC_SEQ_BIT_REMAP_B1_D0__SI__CI regMC_SEQ_BIT_REMAP_B1_D0__SI__CI; -typedef union MC_SEQ_BIT_REMAP_B1_D1__SI__CI regMC_SEQ_BIT_REMAP_B1_D1__SI__CI; -typedef union MC_SEQ_BIT_REMAP_B2_D0__SI__CI regMC_SEQ_BIT_REMAP_B2_D0__SI__CI; -typedef union MC_SEQ_BIT_REMAP_B2_D1__SI__CI regMC_SEQ_BIT_REMAP_B2_D1__SI__CI; -typedef union MC_SEQ_BIT_REMAP_B3_D0__SI__CI regMC_SEQ_BIT_REMAP_B3_D0__SI__CI; -typedef union MC_SEQ_BIT_REMAP_B3_D1__SI__CI regMC_SEQ_BIT_REMAP_B3_D1__SI__CI; -typedef union MC_SEQ_BYTE_REMAP_D0__SI__CI regMC_SEQ_BYTE_REMAP_D0__SI__CI; -typedef union MC_SEQ_BYTE_REMAP_D1__SI__CI regMC_SEQ_BYTE_REMAP_D1__SI__CI; -typedef union MC_SEQ_CAS_TIMING__SI__CI regMC_SEQ_CAS_TIMING__SI__CI; -typedef union MC_SEQ_CAS_TIMING_LP__SI__CI regMC_SEQ_CAS_TIMING_LP__SI__CI; -typedef union MC_SEQ_CG__SI__CI regMC_SEQ_CG__SI__CI; -typedef union MC_SEQ_CMD__SI__CI regMC_SEQ_CMD__SI__CI; -typedef union MC_SEQ_CNTL__SI__CI regMC_SEQ_CNTL__SI__CI; -typedef union MC_SEQ_CNTL_2__CI regMC_SEQ_CNTL_2__CI; -typedef union MC_SEQ_CNTL_2__SI regMC_SEQ_CNTL_2__SI; -typedef union MC_SEQ_CNTL_3__CI regMC_SEQ_CNTL_3__CI; -typedef union MC_SEQ_DLL_STBY_LP__CI regMC_SEQ_DLL_STBY_LP__CI; -typedef union MC_SEQ_DLL_STBY__CI regMC_SEQ_DLL_STBY__CI; -typedef union MC_SEQ_DRAM__SI__CI regMC_SEQ_DRAM__SI__CI; -typedef union MC_SEQ_DRAM_2__SI__CI regMC_SEQ_DRAM_2__SI__CI; -typedef union MC_SEQ_DRAM_ERROR_INSERTION__SI__CI regMC_SEQ_DRAM_ERROR_INSERTION__SI__CI; -typedef union MC_SEQ_FIFO_CTL__SI__CI regMC_SEQ_FIFO_CTL__SI__CI; -typedef union MC_SEQ_G5PDX_CMD0_LP__CI regMC_SEQ_G5PDX_CMD0_LP__CI; -typedef union MC_SEQ_G5PDX_CMD0__CI regMC_SEQ_G5PDX_CMD0__CI; -typedef union MC_SEQ_G5PDX_CMD1_LP__CI regMC_SEQ_G5PDX_CMD1_LP__CI; -typedef union MC_SEQ_G5PDX_CMD1__CI regMC_SEQ_G5PDX_CMD1__CI; -typedef union MC_SEQ_G5PDX_CTRL_LP__CI regMC_SEQ_G5PDX_CTRL_LP__CI; -typedef union MC_SEQ_G5PDX_CTRL__CI regMC_SEQ_G5PDX_CTRL__CI; -typedef union MC_SEQ_IO_DEBUG_DATA__SI__CI regMC_SEQ_IO_DEBUG_DATA__SI__CI; -typedef union MC_SEQ_IO_DEBUG_INDEX__SI__CI regMC_SEQ_IO_DEBUG_INDEX__SI__CI; -typedef union MC_SEQ_IO_RDBI__SI__CI regMC_SEQ_IO_RDBI__SI__CI; -typedef union MC_SEQ_IO_REDC__SI__CI regMC_SEQ_IO_REDC__SI__CI; -typedef union MC_SEQ_IO_RESERVE_D0__SI__CI regMC_SEQ_IO_RESERVE_D0__SI__CI; -typedef union MC_SEQ_IO_RESERVE_D1__SI__CI regMC_SEQ_IO_RESERVE_D1__SI__CI; -typedef union MC_SEQ_IO_RWORD0__SI__CI regMC_SEQ_IO_RWORD0__SI__CI; -typedef union MC_SEQ_IO_RWORD1__SI__CI regMC_SEQ_IO_RWORD1__SI__CI; -typedef union MC_SEQ_IO_RWORD2__SI__CI regMC_SEQ_IO_RWORD2__SI__CI; -typedef union MC_SEQ_IO_RWORD3__SI__CI regMC_SEQ_IO_RWORD3__SI__CI; -typedef union MC_SEQ_IO_RWORD4__SI__CI regMC_SEQ_IO_RWORD4__SI__CI; -typedef union MC_SEQ_IO_RWORD5__SI__CI regMC_SEQ_IO_RWORD5__SI__CI; -typedef union MC_SEQ_IO_RWORD6__SI__CI regMC_SEQ_IO_RWORD6__SI__CI; -typedef union MC_SEQ_IO_RWORD7__SI__CI regMC_SEQ_IO_RWORD7__SI__CI; -typedef union MC_SEQ_MISC0__SI__CI regMC_SEQ_MISC0__SI__CI; -typedef union MC_SEQ_MISC1__SI__CI regMC_SEQ_MISC1__SI__CI; -typedef union MC_SEQ_MISC3__SI__CI regMC_SEQ_MISC3__SI__CI; -typedef union MC_SEQ_MISC4__SI__CI regMC_SEQ_MISC4__SI__CI; -typedef union MC_SEQ_MISC5__SI__CI regMC_SEQ_MISC5__SI__CI; -typedef union MC_SEQ_MISC6__SI__CI regMC_SEQ_MISC6__SI__CI; -typedef union MC_SEQ_MISC7__SI__CI regMC_SEQ_MISC7__SI__CI; -typedef union MC_SEQ_MISC8__SI__CI regMC_SEQ_MISC8__SI__CI; -typedef union MC_SEQ_MISC9__SI__CI regMC_SEQ_MISC9__SI__CI; -typedef union MC_SEQ_MISC_TIMING__SI__CI regMC_SEQ_MISC_TIMING__SI__CI; -typedef union MC_SEQ_MISC_TIMING2__SI__CI regMC_SEQ_MISC_TIMING2__SI__CI; -typedef union MC_SEQ_MISC_TIMING2_LP__SI__CI regMC_SEQ_MISC_TIMING2_LP__SI__CI; -typedef union MC_SEQ_MISC_TIMING_LP__SI__CI regMC_SEQ_MISC_TIMING_LP__SI__CI; -typedef union MC_SEQ_MPLL_OVERRIDE__SI__CI regMC_SEQ_MPLL_OVERRIDE__SI__CI; -typedef union MC_SEQ_PERF_CNTL__SI__CI regMC_SEQ_PERF_CNTL__SI__CI; -typedef union MC_SEQ_PERF_CNTL_1__SI__CI regMC_SEQ_PERF_CNTL_1__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI; -typedef union MC_SEQ_PERF_SEQ_CTL__SI__CI regMC_SEQ_PERF_SEQ_CTL__SI__CI; -typedef union MC_SEQ_PHYREG_BCAST__CI regMC_SEQ_PHYREG_BCAST__CI; -typedef union MC_SEQ_PMG_CMD_EMRS_LP__SI__CI regMC_SEQ_PMG_CMD_EMRS_LP__SI__CI; -typedef union MC_SEQ_PMG_CMD_MRS1_LP__SI__CI regMC_SEQ_PMG_CMD_MRS1_LP__SI__CI; -typedef union MC_SEQ_PMG_CMD_MRS2_LP__SI__CI regMC_SEQ_PMG_CMD_MRS2_LP__SI__CI; -typedef union MC_SEQ_PMG_CMD_MRS_LP__SI__CI regMC_SEQ_PMG_CMD_MRS_LP__SI__CI; -typedef union MC_SEQ_PMG_DVS_CMD_LP__CI regMC_SEQ_PMG_DVS_CMD_LP__CI; -typedef union MC_SEQ_PMG_DVS_CMD__CI regMC_SEQ_PMG_DVS_CMD__CI; -typedef union MC_SEQ_PMG_DVS_CTL_LP__CI regMC_SEQ_PMG_DVS_CTL_LP__CI; -typedef union MC_SEQ_PMG_DVS_CTL__CI regMC_SEQ_PMG_DVS_CTL__CI; -typedef union MC_SEQ_PMG_PG_HWCNTL__SI__CI regMC_SEQ_PMG_PG_HWCNTL__SI__CI; -typedef union MC_SEQ_PMG_PG_SWCNTL_0__SI__CI regMC_SEQ_PMG_PG_SWCNTL_0__SI__CI; -typedef union MC_SEQ_PMG_PG_SWCNTL_1__SI__CI regMC_SEQ_PMG_PG_SWCNTL_1__SI__CI; -typedef union MC_SEQ_PMG_TIMING__SI__CI regMC_SEQ_PMG_TIMING__SI__CI; -typedef union MC_SEQ_PMG_TIMING_LP__SI__CI regMC_SEQ_PMG_TIMING_LP__SI__CI; -typedef union MC_SEQ_RAS_TIMING__SI__CI regMC_SEQ_RAS_TIMING__SI__CI; -typedef union MC_SEQ_RAS_TIMING_LP__SI__CI regMC_SEQ_RAS_TIMING_LP__SI__CI; -typedef union MC_SEQ_RD_CTL_D0__SI__CI regMC_SEQ_RD_CTL_D0__SI__CI; -typedef union MC_SEQ_RD_CTL_D0_LP__SI__CI regMC_SEQ_RD_CTL_D0_LP__SI__CI; -typedef union MC_SEQ_RD_CTL_D1__SI__CI regMC_SEQ_RD_CTL_D1__SI__CI; -typedef union MC_SEQ_RD_CTL_D1_LP__SI__CI regMC_SEQ_RD_CTL_D1_LP__SI__CI; -typedef union MC_SEQ_RESERVE_0_S__SI__CI regMC_SEQ_RESERVE_0_S__SI__CI; -typedef union MC_SEQ_RESERVE_1_S__SI__CI regMC_SEQ_RESERVE_1_S__SI__CI; -typedef union MC_SEQ_RESERVE_M__SI__CI regMC_SEQ_RESERVE_M__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE0_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE0_D0__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE0_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE0_D1__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE1_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE1_D0__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE1_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE1_D1__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE2_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE2_D0__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE2_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE2_D1__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE3_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE3_D0__SI__CI; -typedef union MC_SEQ_RXFRAMING_BYTE3_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE3_D1__SI__CI; -typedef union MC_SEQ_RXFRAMING_DBI_D0__SI__CI regMC_SEQ_RXFRAMING_DBI_D0__SI__CI; -typedef union MC_SEQ_RXFRAMING_DBI_D1__SI__CI regMC_SEQ_RXFRAMING_DBI_D1__SI__CI; -typedef union MC_SEQ_RXFRAMING_EDC_D0__SI__CI regMC_SEQ_RXFRAMING_EDC_D0__SI__CI; -typedef union MC_SEQ_RXFRAMING_EDC_D1__SI__CI regMC_SEQ_RXFRAMING_EDC_D1__SI__CI; -typedef union MC_SEQ_SREG_READ__CI regMC_SEQ_SREG_READ__CI; -typedef union MC_SEQ_SREG_STATUS__CI regMC_SEQ_SREG_STATUS__CI; -typedef union MC_SEQ_STATUS_M__SI__CI regMC_SEQ_STATUS_M__SI__CI; -typedef union MC_SEQ_STATUS_S__SI__CI regMC_SEQ_STATUS_S__SI__CI; -typedef union MC_SEQ_SUP_CNTL__SI__CI regMC_SEQ_SUP_CNTL__SI__CI; -typedef union MC_SEQ_SUP_DEC_STAT__SI__CI regMC_SEQ_SUP_DEC_STAT__SI__CI; -typedef union MC_SEQ_SUP_GP0_STAT__SI__CI regMC_SEQ_SUP_GP0_STAT__SI__CI; -typedef union MC_SEQ_SUP_GP1_STAT__SI__CI regMC_SEQ_SUP_GP1_STAT__SI__CI; -typedef union MC_SEQ_SUP_GP2_STAT__SI__CI regMC_SEQ_SUP_GP2_STAT__SI__CI; -typedef union MC_SEQ_SUP_GP3_STAT__SI__CI regMC_SEQ_SUP_GP3_STAT__SI__CI; -typedef union MC_SEQ_SUP_IR_STAT__SI__CI regMC_SEQ_SUP_IR_STAT__SI__CI; -typedef union MC_SEQ_SUP_PGM__SI__CI regMC_SEQ_SUP_PGM__SI__CI; -typedef union MC_SEQ_SUP_PGM_STAT__SI__CI regMC_SEQ_SUP_PGM_STAT__SI__CI; -typedef union MC_SEQ_SUP_R_PGM__SI__CI regMC_SEQ_SUP_R_PGM__SI__CI; -typedef union MC_SEQ_TCG_CNTL__SI__CI regMC_SEQ_TCG_CNTL__SI__CI; -typedef union MC_SEQ_TIMER_RD__SI__CI regMC_SEQ_TIMER_RD__SI__CI; -typedef union MC_SEQ_TIMER_WR__SI__CI regMC_SEQ_TIMER_WR__SI__CI; -typedef union MC_SEQ_TRAIN_CAPTURE__SI__CI regMC_SEQ_TRAIN_CAPTURE__SI__CI; -typedef union MC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI regMC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI; -typedef union MC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI regMC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI; -typedef union MC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI regMC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI; -typedef union MC_SEQ_TRAIN_TIMING__SI__CI regMC_SEQ_TRAIN_TIMING__SI__CI; -typedef union MC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI regMC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI; -typedef union MC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI regMC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI; -typedef union MC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI regMC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI; -typedef union MC_SEQ_TRAIN_WAKEUP_MASK__SI__CI regMC_SEQ_TRAIN_WAKEUP_MASK__SI__CI; -typedef union MC_SEQ_TSM_BCNT__SI__CI regMC_SEQ_TSM_BCNT__SI__CI; -typedef union MC_SEQ_TSM_CTRL__SI__CI regMC_SEQ_TSM_CTRL__SI__CI; -typedef union MC_SEQ_TSM_DBI__SI__CI regMC_SEQ_TSM_DBI__SI__CI; -typedef union MC_SEQ_TSM_DEBUG_DATA__SI__CI regMC_SEQ_TSM_DEBUG_DATA__SI__CI; -typedef union MC_SEQ_TSM_DEBUG_INDEX__SI__CI regMC_SEQ_TSM_DEBUG_INDEX__SI__CI; -typedef union MC_SEQ_TSM_EDC__SI__CI regMC_SEQ_TSM_EDC__SI__CI; -typedef union MC_SEQ_TSM_FLAG__SI__CI regMC_SEQ_TSM_FLAG__SI__CI; -typedef union MC_SEQ_TSM_GCNT__SI__CI regMC_SEQ_TSM_GCNT__SI__CI; -typedef union MC_SEQ_TSM_MISC__SI__CI regMC_SEQ_TSM_MISC__SI__CI; -typedef union MC_SEQ_TSM_NCNT__SI__CI regMC_SEQ_TSM_NCNT__SI__CI; -typedef union MC_SEQ_TSM_OCNT__SI__CI regMC_SEQ_TSM_OCNT__SI__CI; -typedef union MC_SEQ_TSM_UPDATE__SI__CI regMC_SEQ_TSM_UPDATE__SI__CI; -typedef union MC_SEQ_TSM_WCDR__SI__CI regMC_SEQ_TSM_WCDR__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE0_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE0_D0__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE0_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE0_D1__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE1_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE1_D0__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE1_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE1_D1__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE2_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE2_D0__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE2_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE2_D1__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE3_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE3_D0__SI__CI; -typedef union MC_SEQ_TXFRAMING_BYTE3_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE3_D1__SI__CI; -typedef union MC_SEQ_TXFRAMING_DBI_D0__SI__CI regMC_SEQ_TXFRAMING_DBI_D0__SI__CI; -typedef union MC_SEQ_TXFRAMING_DBI_D1__SI__CI regMC_SEQ_TXFRAMING_DBI_D1__SI__CI; -typedef union MC_SEQ_TXFRAMING_EDC_D0__SI__CI regMC_SEQ_TXFRAMING_EDC_D0__SI__CI; -typedef union MC_SEQ_TXFRAMING_EDC_D1__SI__CI regMC_SEQ_TXFRAMING_EDC_D1__SI__CI; -typedef union MC_SEQ_TXFRAMING_FCK_D0__SI__CI regMC_SEQ_TXFRAMING_FCK_D0__SI__CI; -typedef union MC_SEQ_TXFRAMING_FCK_D1__SI__CI regMC_SEQ_TXFRAMING_FCK_D1__SI__CI; -typedef union MC_SEQ_VENDOR_ID_I0__SI__CI regMC_SEQ_VENDOR_ID_I0__SI__CI; -typedef union MC_SEQ_VENDOR_ID_I1__SI__CI regMC_SEQ_VENDOR_ID_I1__SI__CI; -typedef union MC_SEQ_WCDR_CTRL__SI__CI regMC_SEQ_WCDR_CTRL__SI__CI; -typedef union MC_SEQ_WR_CTL_2__SI__CI regMC_SEQ_WR_CTL_2__SI__CI; -typedef union MC_SEQ_WR_CTL_2_LP__SI__CI regMC_SEQ_WR_CTL_2_LP__SI__CI; -typedef union MC_SEQ_WR_CTL_D0__SI__CI regMC_SEQ_WR_CTL_D0__SI__CI; -typedef union MC_SEQ_WR_CTL_D0_LP__SI__CI regMC_SEQ_WR_CTL_D0_LP__SI__CI; -typedef union MC_SEQ_WR_CTL_D1__SI__CI regMC_SEQ_WR_CTL_D1__SI__CI; -typedef union MC_SEQ_WR_CTL_D1_LP__SI__CI regMC_SEQ_WR_CTL_D1_LP__SI__CI; -typedef union MC_SHARED_BLACKOUT_CNTL__SI__CI regMC_SHARED_BLACKOUT_CNTL__SI__CI; -typedef union MC_SHARED_BLACKOUT_CNTL__VI regMC_SHARED_BLACKOUT_CNTL__VI; -typedef union MC_SHARED_CHMAP regMC_SHARED_CHMAP; -typedef union MC_SHARED_CHREMAP__SI__CI regMC_SHARED_CHREMAP__SI__CI; -typedef union MC_SHARED_CHREMAP__VI regMC_SHARED_CHREMAP__VI; -typedef union MC_TRAIN_EDCCDR_R_D0__SI__CI regMC_TRAIN_EDCCDR_R_D0__SI__CI; -typedef union MC_TRAIN_EDCCDR_R_D1__SI__CI regMC_TRAIN_EDCCDR_R_D1__SI__CI; -typedef union MC_TRAIN_EDC_STATUS_D0__SI__CI regMC_TRAIN_EDC_STATUS_D0__SI__CI; -typedef union MC_TRAIN_EDC_STATUS_D1__SI__CI regMC_TRAIN_EDC_STATUS_D1__SI__CI; -typedef union MC_TRAIN_PRBSERR_0_D0__SI__CI regMC_TRAIN_PRBSERR_0_D0__SI__CI; -typedef union MC_TRAIN_PRBSERR_0_D1__SI__CI regMC_TRAIN_PRBSERR_0_D1__SI__CI; -typedef union MC_TRAIN_PRBSERR_1_D0__SI__CI regMC_TRAIN_PRBSERR_1_D0__SI__CI; -typedef union MC_TRAIN_PRBSERR_1_D1__SI__CI regMC_TRAIN_PRBSERR_1_D1__SI__CI; -typedef union MC_TRAIN_PRBSERR_2_D0__SI__CI regMC_TRAIN_PRBSERR_2_D0__SI__CI; -typedef union MC_TRAIN_PRBSERR_2_D1__SI__CI regMC_TRAIN_PRBSERR_2_D1__SI__CI; -typedef union MC_TSM_DEBUG_BCNT0__SI__CI regMC_TSM_DEBUG_BCNT0__SI__CI; -typedef union MC_TSM_DEBUG_BCNT1__SI__CI regMC_TSM_DEBUG_BCNT1__SI__CI; -typedef union MC_TSM_DEBUG_BCNT10__SI__CI regMC_TSM_DEBUG_BCNT10__SI__CI; -typedef union MC_TSM_DEBUG_BCNT2__SI__CI regMC_TSM_DEBUG_BCNT2__SI__CI; -typedef union MC_TSM_DEBUG_BCNT3__SI__CI regMC_TSM_DEBUG_BCNT3__SI__CI; -typedef union MC_TSM_DEBUG_BCNT4__SI__CI regMC_TSM_DEBUG_BCNT4__SI__CI; -typedef union MC_TSM_DEBUG_BCNT5__SI__CI regMC_TSM_DEBUG_BCNT5__SI__CI; -typedef union MC_TSM_DEBUG_BCNT6__SI__CI regMC_TSM_DEBUG_BCNT6__SI__CI; -typedef union MC_TSM_DEBUG_BCNT7__SI__CI regMC_TSM_DEBUG_BCNT7__SI__CI; -typedef union MC_TSM_DEBUG_BCNT8__SI__CI regMC_TSM_DEBUG_BCNT8__SI__CI; -typedef union MC_TSM_DEBUG_BCNT9__SI__CI regMC_TSM_DEBUG_BCNT9__SI__CI; -typedef union MC_TSM_DEBUG_BKPT__SI__CI regMC_TSM_DEBUG_BKPT__SI__CI; -typedef union MC_TSM_DEBUG_FLAG__SI__CI regMC_TSM_DEBUG_FLAG__SI__CI; -typedef union MC_TSM_DEBUG_GCNT__SI__CI regMC_TSM_DEBUG_GCNT__SI__CI; -typedef union MC_TSM_DEBUG_MISC__SI__CI regMC_TSM_DEBUG_MISC__SI__CI; -typedef union MC_TSM_DEBUG_ST01__SI__CI regMC_TSM_DEBUG_ST01__SI__CI; -typedef union MC_TSM_DEBUG_ST23__SI__CI regMC_TSM_DEBUG_ST23__SI__CI; -typedef union MC_TSM_DEBUG_ST45__SI__CI regMC_TSM_DEBUG_ST45__SI__CI; -typedef union MC_VM_AGP_BASE regMC_VM_AGP_BASE; -typedef union MC_VM_AGP_BOT regMC_VM_AGP_BOT; -typedef union MC_VM_AGP_TOP regMC_VM_AGP_TOP; -typedef union MC_VM_DC_WRITE_CNTL regMC_VM_DC_WRITE_CNTL; -typedef union MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR; -typedef union MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR; -typedef union MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR; -typedef union MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR; -typedef union MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR; -typedef union MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR; -typedef union MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR; -typedef union MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR; -typedef union MC_VM_FB_LOCATION regMC_VM_FB_LOCATION; -typedef union MC_VM_FB_OFFSET regMC_VM_FB_OFFSET; -typedef union MC_VM_L2_PERFCOUNTER0_CFG__CI__VI regMC_VM_L2_PERFCOUNTER0_CFG__CI__VI; -typedef union MC_VM_L2_PERFCOUNTER1_CFG__CI__VI regMC_VM_L2_PERFCOUNTER1_CFG__CI__VI; -typedef union MC_VM_L2_PERFCOUNTER_HI__CI__VI regMC_VM_L2_PERFCOUNTER_HI__CI__VI; -typedef union MC_VM_L2_PERFCOUNTER_LO__CI__VI regMC_VM_L2_PERFCOUNTER_LO__CI__VI; -typedef union MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI; -typedef union MC_VM_MB_L1_TLB0_DEBUG regMC_VM_MB_L1_TLB0_DEBUG; -typedef union MC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__SI regMC_VM_MB_L1_TLB0_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MB_L1_TLB0_PERF_COUNTER_STATUS__SI regMC_VM_MB_L1_TLB0_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MB_L1_TLB0_STATUS regMC_VM_MB_L1_TLB0_STATUS; -typedef union MC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__SI regMC_VM_MB_L1_TLB1_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MB_L1_TLB1_PERF_COUNTER_STATUS__SI regMC_VM_MB_L1_TLB1_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MB_L1_TLB1_STATUS regMC_VM_MB_L1_TLB1_STATUS; -typedef union MC_VM_MB_L1_TLB2_DEBUG regMC_VM_MB_L1_TLB2_DEBUG; -typedef union MC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__SI regMC_VM_MB_L1_TLB2_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MB_L1_TLB2_PERF_COUNTER_STATUS__SI regMC_VM_MB_L1_TLB2_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MB_L1_TLB2_STATUS regMC_VM_MB_L1_TLB2_STATUS; -typedef union MC_VM_MB_L1_TLB3_DEBUG regMC_VM_MB_L1_TLB3_DEBUG; -typedef union MC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__SI regMC_VM_MB_L1_TLB3_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MB_L1_TLB3_PERF_COUNTER_STATUS__SI regMC_VM_MB_L1_TLB3_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MB_L1_TLB3_STATUS regMC_VM_MB_L1_TLB3_STATUS; -typedef union MC_VM_MB_L2ARBITER_L2_CREDITS regMC_VM_MB_L2ARBITER_L2_CREDITS; -typedef union MC_VM_MB_SECURE__SI regMC_VM_MB_SECURE__SI; -typedef union MC_VM_MD_L1_TLB0_DEBUG regMC_VM_MD_L1_TLB0_DEBUG; -typedef union MC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__SI regMC_VM_MD_L1_TLB0_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MD_L1_TLB0_PERF_COUNTER_STATUS__SI regMC_VM_MD_L1_TLB0_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MD_L1_TLB0_STATUS regMC_VM_MD_L1_TLB0_STATUS; -typedef union MC_VM_MD_L1_TLB1_DEBUG regMC_VM_MD_L1_TLB1_DEBUG; -typedef union MC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__SI regMC_VM_MD_L1_TLB1_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MD_L1_TLB1_PERF_COUNTER_STATUS__SI regMC_VM_MD_L1_TLB1_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MD_L1_TLB1_STATUS regMC_VM_MD_L1_TLB1_STATUS; -typedef union MC_VM_MD_L1_TLB2_DEBUG regMC_VM_MD_L1_TLB2_DEBUG; -typedef union MC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__SI regMC_VM_MD_L1_TLB2_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MD_L1_TLB2_PERF_COUNTER_STATUS__SI regMC_VM_MD_L1_TLB2_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MD_L1_TLB2_STATUS regMC_VM_MD_L1_TLB2_STATUS; -typedef union MC_VM_MD_L1_TLB3_DEBUG regMC_VM_MD_L1_TLB3_DEBUG; -typedef union MC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__SI regMC_VM_MD_L1_TLB3_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MD_L1_TLB3_PERF_COUNTER_STATUS__SI regMC_VM_MD_L1_TLB3_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MD_L1_TLB3_STATUS regMC_VM_MD_L1_TLB3_STATUS; -typedef union MC_VM_MD_L1_TLB4_DEBUG__SI regMC_VM_MD_L1_TLB4_DEBUG__SI; -typedef union MC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__SI regMC_VM_MD_L1_TLB4_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MD_L1_TLB4_PERF_COUNTER_STATUS__SI regMC_VM_MD_L1_TLB4_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MD_L1_TLB4_STATUS__SI regMC_VM_MD_L1_TLB4_STATUS__SI; -typedef union MC_VM_MD_L1_TLB5_DEBUG__SI regMC_VM_MD_L1_TLB5_DEBUG__SI; -typedef union MC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__SI regMC_VM_MD_L1_TLB5_PERF_COUNTER_CNTL__SI; -typedef union MC_VM_MD_L1_TLB5_PERF_COUNTER_STATUS__SI regMC_VM_MD_L1_TLB5_PERF_COUNTER_STATUS__SI; -typedef union MC_VM_MD_L1_TLB5_STATUS__SI regMC_VM_MD_L1_TLB5_STATUS__SI; -typedef union MC_VM_MD_L2ARBITER_L2_CREDITS regMC_VM_MD_L2ARBITER_L2_CREDITS; -typedef union MC_VM_MD_SECURE__SI regMC_VM_MD_SECURE__SI; -typedef union MC_VM_MX_L1_TLB_CNTL regMC_VM_MX_L1_TLB_CNTL; -typedef union MC_VM_STEERING__CI__VI regMC_VM_STEERING__CI__VI; -typedef union MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR; -typedef union MC_VM_SYSTEM_APERTURE_HIGH_ADDR regMC_VM_SYSTEM_APERTURE_HIGH_ADDR; -typedef union MC_VM_SYSTEM_APERTURE_LOW_ADDR regMC_VM_SYSTEM_APERTURE_LOW_ADDR; -typedef union MC_WR_CB regMC_WR_CB; -typedef union MC_WR_DB regMC_WR_DB; -typedef union MC_WR_GRP_EXT regMC_WR_GRP_EXT; -typedef union MC_WR_GRP_GFX__CI regMC_WR_GRP_GFX__CI; -typedef union MC_WR_GRP_GFX__VI regMC_WR_GRP_GFX__VI; -typedef union MC_WR_GRP_GFX__SI regMC_WR_GRP_GFX__SI; -typedef union MC_WR_GRP_LCL regMC_WR_GRP_LCL; -typedef union MC_WR_GRP_OTH__CI__VI regMC_WR_GRP_OTH__CI__VI; -typedef union MC_WR_GRP_OTH__SI regMC_WR_GRP_OTH__SI; -typedef union MC_WR_GRP_SYS__CI regMC_WR_GRP_SYS__CI; -typedef union MC_WR_GRP_SYS__VI regMC_WR_GRP_SYS__VI; -typedef union MC_WR_GRP_SYS__SI regMC_WR_GRP_SYS__SI; -typedef union MC_WR_HUB regMC_WR_HUB; -typedef union MC_WR_TC0 regMC_WR_TC0; -typedef union MC_WR_TC1 regMC_WR_TC1; -typedef union MC_XBAR_ADDR_DEC regMC_XBAR_ADDR_DEC; -typedef union MC_XBAR_ARB regMC_XBAR_ARB; -typedef union MC_XBAR_ARB_MAX_BURST regMC_XBAR_ARB_MAX_BURST; -typedef union MC_XBAR_CHTRIREMAP regMC_XBAR_CHTRIREMAP; -typedef union MC_XBAR_PERF_MON_CNTL0__SI__CI regMC_XBAR_PERF_MON_CNTL0__SI__CI; -typedef union MC_XBAR_PERF_MON_CNTL1__SI__CI regMC_XBAR_PERF_MON_CNTL1__SI__CI; -typedef union MC_XBAR_PERF_MON_CNTL2__SI__CI regMC_XBAR_PERF_MON_CNTL2__SI__CI; -typedef union MC_XBAR_PERF_MON_MAX_THSH__SI__CI regMC_XBAR_PERF_MON_MAX_THSH__SI__CI; -typedef union MC_XBAR_PERF_MON_RSLT0__SI__CI regMC_XBAR_PERF_MON_RSLT0__SI__CI; -typedef union MC_XBAR_PERF_MON_RSLT1__SI__CI regMC_XBAR_PERF_MON_RSLT1__SI__CI; -typedef union MC_XBAR_PERF_MON_RSLT2__SI__CI regMC_XBAR_PERF_MON_RSLT2__SI__CI; -typedef union MC_XBAR_PERF_MON_RSLT3__SI__CI regMC_XBAR_PERF_MON_RSLT3__SI__CI; -typedef union MC_XBAR_RDREQ_CREDIT regMC_XBAR_RDREQ_CREDIT; -typedef union MC_XBAR_RDREQ_PRI_CREDIT regMC_XBAR_RDREQ_PRI_CREDIT; -typedef union MC_XBAR_RDRET_CREDIT1 regMC_XBAR_RDRET_CREDIT1; -typedef union MC_XBAR_RDRET_CREDIT2 regMC_XBAR_RDRET_CREDIT2; -typedef union MC_XBAR_RDRET_PRI_CREDIT1 regMC_XBAR_RDRET_PRI_CREDIT1; -typedef union MC_XBAR_RDRET_PRI_CREDIT2 regMC_XBAR_RDRET_PRI_CREDIT2; -typedef union MC_XBAR_REMOTE regMC_XBAR_REMOTE; -typedef union MC_XBAR_SPARE0 regMC_XBAR_SPARE0; -typedef union MC_XBAR_SPARE1 regMC_XBAR_SPARE1; -typedef union MC_XBAR_TWOCHAN regMC_XBAR_TWOCHAN; -typedef union MC_XBAR_WRREQ_CREDIT regMC_XBAR_WRREQ_CREDIT; -typedef union MC_XBAR_WRRET_CREDIT1 regMC_XBAR_WRRET_CREDIT1; -typedef union MC_XBAR_WRRET_CREDIT2 regMC_XBAR_WRRET_CREDIT2; -typedef union MC_XPB_CLG_CFG0 regMC_XPB_CLG_CFG0; -typedef union MC_XPB_CLG_CFG1 regMC_XPB_CLG_CFG1; -typedef union MC_XPB_CLG_CFG10 regMC_XPB_CLG_CFG10; -typedef union MC_XPB_CLG_CFG11 regMC_XPB_CLG_CFG11; -typedef union MC_XPB_CLG_CFG12 regMC_XPB_CLG_CFG12; -typedef union MC_XPB_CLG_CFG13 regMC_XPB_CLG_CFG13; -typedef union MC_XPB_CLG_CFG14 regMC_XPB_CLG_CFG14; -typedef union MC_XPB_CLG_CFG15 regMC_XPB_CLG_CFG15; -typedef union MC_XPB_CLG_CFG16 regMC_XPB_CLG_CFG16; -typedef union MC_XPB_CLG_CFG17 regMC_XPB_CLG_CFG17; -typedef union MC_XPB_CLG_CFG18 regMC_XPB_CLG_CFG18; -typedef union MC_XPB_CLG_CFG19 regMC_XPB_CLG_CFG19; -typedef union MC_XPB_CLG_CFG2 regMC_XPB_CLG_CFG2; -typedef union MC_XPB_CLG_CFG20 regMC_XPB_CLG_CFG20; -typedef union MC_XPB_CLG_CFG21 regMC_XPB_CLG_CFG21; -typedef union MC_XPB_CLG_CFG22 regMC_XPB_CLG_CFG22; -typedef union MC_XPB_CLG_CFG23 regMC_XPB_CLG_CFG23; -typedef union MC_XPB_CLG_CFG24 regMC_XPB_CLG_CFG24; -typedef union MC_XPB_CLG_CFG25 regMC_XPB_CLG_CFG25; -typedef union MC_XPB_CLG_CFG26 regMC_XPB_CLG_CFG26; -typedef union MC_XPB_CLG_CFG27 regMC_XPB_CLG_CFG27; -typedef union MC_XPB_CLG_CFG28 regMC_XPB_CLG_CFG28; -typedef union MC_XPB_CLG_CFG29 regMC_XPB_CLG_CFG29; -typedef union MC_XPB_CLG_CFG3 regMC_XPB_CLG_CFG3; -typedef union MC_XPB_CLG_CFG30 regMC_XPB_CLG_CFG30; -typedef union MC_XPB_CLG_CFG31 regMC_XPB_CLG_CFG31; -typedef union MC_XPB_CLG_CFG32 regMC_XPB_CLG_CFG32; -typedef union MC_XPB_CLG_CFG33 regMC_XPB_CLG_CFG33; -typedef union MC_XPB_CLG_CFG34 regMC_XPB_CLG_CFG34; -typedef union MC_XPB_CLG_CFG35 regMC_XPB_CLG_CFG35; -typedef union MC_XPB_CLG_CFG36 regMC_XPB_CLG_CFG36; -typedef union MC_XPB_CLG_CFG4 regMC_XPB_CLG_CFG4; -typedef union MC_XPB_CLG_CFG5 regMC_XPB_CLG_CFG5; -typedef union MC_XPB_CLG_CFG6 regMC_XPB_CLG_CFG6; -typedef union MC_XPB_CLG_CFG7 regMC_XPB_CLG_CFG7; -typedef union MC_XPB_CLG_CFG8 regMC_XPB_CLG_CFG8; -typedef union MC_XPB_CLG_CFG9 regMC_XPB_CLG_CFG9; -typedef union MC_XPB_CLG_EXTRA regMC_XPB_CLG_EXTRA; -typedef union MC_XPB_CLG_EXTRA_RD regMC_XPB_CLG_EXTRA_RD; -typedef union MC_XPB_CLK_GAT regMC_XPB_CLK_GAT; -typedef union MC_XPB_INTF_CFG regMC_XPB_INTF_CFG; -typedef union MC_XPB_INTF_CFG2 regMC_XPB_INTF_CFG2; -typedef union MC_XPB_INTF_STS regMC_XPB_INTF_STS; -typedef union MC_XPB_LB_ADDR regMC_XPB_LB_ADDR; -typedef union MC_XPB_MAP_INVERT_FLUSH_NUM_LSB regMC_XPB_MAP_INVERT_FLUSH_NUM_LSB; -typedef union MC_XPB_MISC_CFG regMC_XPB_MISC_CFG; -typedef union MC_XPB_P2P_BAR0 regMC_XPB_P2P_BAR0; -typedef union MC_XPB_P2P_BAR1 regMC_XPB_P2P_BAR1; -typedef union MC_XPB_P2P_BAR2 regMC_XPB_P2P_BAR2; -typedef union MC_XPB_P2P_BAR3 regMC_XPB_P2P_BAR3; -typedef union MC_XPB_P2P_BAR4 regMC_XPB_P2P_BAR4; -typedef union MC_XPB_P2P_BAR5 regMC_XPB_P2P_BAR5; -typedef union MC_XPB_P2P_BAR6 regMC_XPB_P2P_BAR6; -typedef union MC_XPB_P2P_BAR7 regMC_XPB_P2P_BAR7; -typedef union MC_XPB_P2P_BAR_CFG regMC_XPB_P2P_BAR_CFG; -typedef union MC_XPB_P2P_BAR_DEBUG regMC_XPB_P2P_BAR_DEBUG; -typedef union MC_XPB_P2P_BAR_DELTA_ABOVE regMC_XPB_P2P_BAR_DELTA_ABOVE; -typedef union MC_XPB_P2P_BAR_DELTA_BELOW regMC_XPB_P2P_BAR_DELTA_BELOW; -typedef union MC_XPB_P2P_BAR_SETUP regMC_XPB_P2P_BAR_SETUP; -typedef union MC_XPB_PEER_SYS_BAR0 regMC_XPB_PEER_SYS_BAR0; -typedef union MC_XPB_PEER_SYS_BAR1 regMC_XPB_PEER_SYS_BAR1; -typedef union MC_XPB_PEER_SYS_BAR2 regMC_XPB_PEER_SYS_BAR2; -typedef union MC_XPB_PEER_SYS_BAR3 regMC_XPB_PEER_SYS_BAR3; -typedef union MC_XPB_PEER_SYS_BAR4 regMC_XPB_PEER_SYS_BAR4; -typedef union MC_XPB_PEER_SYS_BAR5 regMC_XPB_PEER_SYS_BAR5; -typedef union MC_XPB_PEER_SYS_BAR6 regMC_XPB_PEER_SYS_BAR6; -typedef union MC_XPB_PEER_SYS_BAR7 regMC_XPB_PEER_SYS_BAR7; -typedef union MC_XPB_PEER_SYS_BAR8 regMC_XPB_PEER_SYS_BAR8; -typedef union MC_XPB_PEER_SYS_BAR9 regMC_XPB_PEER_SYS_BAR9; -typedef union MC_XPB_PERF_KNOBS regMC_XPB_PERF_KNOBS; -typedef union MC_XPB_PIPE_STS regMC_XPB_PIPE_STS; -typedef union MC_XPB_RTR_DEST_MAP0 regMC_XPB_RTR_DEST_MAP0; -typedef union MC_XPB_RTR_DEST_MAP1 regMC_XPB_RTR_DEST_MAP1; -typedef union MC_XPB_RTR_DEST_MAP2 regMC_XPB_RTR_DEST_MAP2; -typedef union MC_XPB_RTR_DEST_MAP3 regMC_XPB_RTR_DEST_MAP3; -typedef union MC_XPB_RTR_DEST_MAP4 regMC_XPB_RTR_DEST_MAP4; -typedef union MC_XPB_RTR_DEST_MAP5 regMC_XPB_RTR_DEST_MAP5; -typedef union MC_XPB_RTR_DEST_MAP6 regMC_XPB_RTR_DEST_MAP6; -typedef union MC_XPB_RTR_DEST_MAP7 regMC_XPB_RTR_DEST_MAP7; -typedef union MC_XPB_RTR_DEST_MAP8 regMC_XPB_RTR_DEST_MAP8; -typedef union MC_XPB_RTR_DEST_MAP9 regMC_XPB_RTR_DEST_MAP9; -typedef union MC_XPB_RTR_SRC_APRTR0 regMC_XPB_RTR_SRC_APRTR0; -typedef union MC_XPB_RTR_SRC_APRTR1 regMC_XPB_RTR_SRC_APRTR1; -typedef union MC_XPB_RTR_SRC_APRTR2 regMC_XPB_RTR_SRC_APRTR2; -typedef union MC_XPB_RTR_SRC_APRTR3 regMC_XPB_RTR_SRC_APRTR3; -typedef union MC_XPB_RTR_SRC_APRTR4 regMC_XPB_RTR_SRC_APRTR4; -typedef union MC_XPB_RTR_SRC_APRTR5 regMC_XPB_RTR_SRC_APRTR5; -typedef union MC_XPB_RTR_SRC_APRTR6 regMC_XPB_RTR_SRC_APRTR6; -typedef union MC_XPB_RTR_SRC_APRTR7 regMC_XPB_RTR_SRC_APRTR7; -typedef union MC_XPB_RTR_SRC_APRTR8 regMC_XPB_RTR_SRC_APRTR8; -typedef union MC_XPB_RTR_SRC_APRTR9 regMC_XPB_RTR_SRC_APRTR9; -typedef union MC_XPB_STICKY regMC_XPB_STICKY; -typedef union MC_XPB_STICKY_W1C regMC_XPB_STICKY_W1C; -typedef union MC_XPB_SUB_CTRL regMC_XPB_SUB_CTRL; -typedef union MC_XPB_UNC_THRESH_HST regMC_XPB_UNC_THRESH_HST; -typedef union MC_XPB_UNC_THRESH_SID regMC_XPB_UNC_THRESH_SID; -typedef union MC_XPB_WCB_CFG regMC_XPB_WCB_CFG; -typedef union MC_XPB_WCB_STS regMC_XPB_WCB_STS; -typedef union MC_XPB_XDMA_PEER_SYS_BAR0 regMC_XPB_XDMA_PEER_SYS_BAR0; -typedef union MC_XPB_XDMA_PEER_SYS_BAR1 regMC_XPB_XDMA_PEER_SYS_BAR1; -typedef union MC_XPB_XDMA_PEER_SYS_BAR2 regMC_XPB_XDMA_PEER_SYS_BAR2; -typedef union MC_XPB_XDMA_PEER_SYS_BAR3 regMC_XPB_XDMA_PEER_SYS_BAR3; -typedef union MC_XPB_XDMA_RTR_DEST_MAP0 regMC_XPB_XDMA_RTR_DEST_MAP0; -typedef union MC_XPB_XDMA_RTR_DEST_MAP1 regMC_XPB_XDMA_RTR_DEST_MAP1; -typedef union MC_XPB_XDMA_RTR_DEST_MAP2 regMC_XPB_XDMA_RTR_DEST_MAP2; -typedef union MC_XPB_XDMA_RTR_DEST_MAP3 regMC_XPB_XDMA_RTR_DEST_MAP3; -typedef union MC_XPB_XDMA_RTR_SRC_APRTR0 regMC_XPB_XDMA_RTR_SRC_APRTR0; -typedef union MC_XPB_XDMA_RTR_SRC_APRTR1 regMC_XPB_XDMA_RTR_SRC_APRTR1; -typedef union MC_XPB_XDMA_RTR_SRC_APRTR2 regMC_XPB_XDMA_RTR_SRC_APRTR2; -typedef union MC_XPB_XDMA_RTR_SRC_APRTR3 regMC_XPB_XDMA_RTR_SRC_APRTR3; -typedef union MEM_TYPE_CNTL__CI__VI regMEM_TYPE_CNTL__CI__VI; -typedef union MICROSECOND_TIME_BASE_DIV__SI regMICROSECOND_TIME_BASE_DIV__SI; -typedef union MINOR_VERSION__SI regMINOR_VERSION__SI; -typedef union MIN_GRANT regMIN_GRANT; -typedef union MISC_CLK_CTRL__CI__VI regMISC_CLK_CTRL__CI__VI; -typedef union MLPS0_DEBUG_BUS_SIGNALS__CI__VI regMLPS0_DEBUG_BUS_SIGNALS__CI__VI; -typedef union MLPS1_DEBUG_BUS_SIGNALS__CI__VI regMLPS1_DEBUG_BUS_SIGNALS__CI__VI; -typedef union MLPS2_DEBUG_BUS_SIGNALS__CI__VI regMLPS2_DEBUG_BUS_SIGNALS__CI__VI; -typedef union MLPS3_DEBUG_BUS_SIGNALS__CI__VI regMLPS3_DEBUG_BUS_SIGNALS__CI__VI; -typedef union MLPSPAD_PINSTRAPS__CI regMLPSPAD_PINSTRAPS__CI; -typedef union MLPSPAD_PINSTRAPS__VI regMLPSPAD_PINSTRAPS__VI; -typedef union MLPS_CNTL__CI__VI regMLPS_CNTL__CI__VI; -typedef union MM_CFGREGS_CNTL regMM_CFGREGS_CNTL; -typedef union MM_DATA regMM_DATA; -typedef union MM_INDEX regMM_INDEX; -typedef union MM_INDEX_HI__CI__VI regMM_INDEX_HI__CI__VI; -typedef union MPLL_AD_FUNC_CNTL__SI__CI regMPLL_AD_FUNC_CNTL__SI__CI; -typedef union MPLL_AD_STATUS__SI__CI regMPLL_AD_STATUS__SI__CI; -typedef union MPLL_BYPASSCLK_SEL regMPLL_BYPASSCLK_SEL; -typedef union MPLL_CNTL_MODE__SI__CI regMPLL_CNTL_MODE__SI__CI; -typedef union MPLL_CONTROL__SI__CI regMPLL_CONTROL__SI__CI; -typedef union MPLL_DQ_0_0_STATUS__SI__CI regMPLL_DQ_0_0_STATUS__SI__CI; -typedef union MPLL_DQ_0_1_STATUS__SI__CI regMPLL_DQ_0_1_STATUS__SI__CI; -typedef union MPLL_DQ_1_0_STATUS__SI__CI regMPLL_DQ_1_0_STATUS__SI__CI; -typedef union MPLL_DQ_1_1_STATUS__SI__CI regMPLL_DQ_1_1_STATUS__SI__CI; -typedef union MPLL_DQ_FUNC_CNTL__SI__CI regMPLL_DQ_FUNC_CNTL__SI__CI; -typedef union MPLL_FUNC_CNTL__SI__CI regMPLL_FUNC_CNTL__SI__CI; -typedef union MPLL_FUNC_CNTL_1__SI__CI regMPLL_FUNC_CNTL_1__SI__CI; -typedef union MPLL_FUNC_CNTL_2__CI regMPLL_FUNC_CNTL_2__CI; -typedef union MPLL_FUNC_CNTL_2__SI regMPLL_FUNC_CNTL_2__SI; -typedef union MPLL_SEQ_UCODE_1__SI__CI regMPLL_SEQ_UCODE_1__SI__CI; -typedef union MPLL_SEQ_UCODE_2__SI__CI regMPLL_SEQ_UCODE_2__SI__CI; -typedef union MPLL_SS1__SI__CI regMPLL_SS1__SI__CI; -typedef union MPLL_SS2__SI__CI regMPLL_SS2__SI__CI; -typedef union MPLL_TIME__SI__CI regMPLL_TIME__SI__CI; -typedef union MPRD_BUF_SIZE__SI regMPRD_BUF_SIZE__SI; -typedef union MPRD_BUF_WIDTH__SI regMPRD_BUF_WIDTH__SI; -typedef union MPRD_BYPASS_PITCH__SI regMPRD_BYPASS_PITCH__SI; -typedef union MPRD_CNTRL__SI regMPRD_CNTRL__SI; -typedef union MPRD_DBW_BUF_SIZE__SI regMPRD_DBW_BUF_SIZE__SI; -typedef union MPRD_HW_DEBUG__SI regMPRD_HW_DEBUG__SI; -typedef union MPRD_OUTOFRANGE_PIXELS__SI regMPRD_OUTOFRANGE_PIXELS__SI; -typedef union MPRD_STATUS__SI regMPRD_STATUS__SI; -typedef union MP_BUF_MAP__SI regMP_BUF_MAP__SI; -typedef union MP_BUF_NUM__SI regMP_BUF_NUM__SI; -typedef union MP_BUF_SIZE__SI regMP_BUF_SIZE__SI; -typedef union MP_CACHE_CTRL__SI regMP_CACHE_CTRL__SI; -typedef union MP_CACHE_PERF_COUNTER__SI regMP_CACHE_PERF_COUNTER__SI; -typedef union MP_CACHE_SRAM_RM_CTL__SI regMP_CACHE_SRAM_RM_CTL__SI; -typedef union MP_CF_DAT__SI regMP_CF_DAT__SI; -typedef union MP_COL_INFO__SI regMP_COL_INFO__SI; -typedef union MP_COL_PIC_BOTTOM__SI regMP_COL_PIC_BOTTOM__SI; -typedef union MP_COL_PIC_TOP__SI regMP_COL_PIC_TOP__SI; -typedef union MP_CTL__SI regMP_CTL__SI; -typedef union MP_CURR_PIC_BOTTOM__SI regMP_CURR_PIC_BOTTOM__SI; -typedef union MP_CURR_PIC_TOP__SI regMP_CURR_PIC_TOP__SI; -typedef union MP_DEBUG_INT_STAT__SI regMP_DEBUG_INT_STAT__SI; -typedef union MP_HW_DEBUG__SI regMP_HW_DEBUG__SI; -typedef union MP_INT_EN__SI regMP_INT_EN__SI; -typedef union MP_INT_STAT__SI regMP_INT_STAT__SI; -typedef union MP_LISTX0_0__SI regMP_LISTX0_0__SI; -typedef union MP_LISTX0_10__SI regMP_LISTX0_10__SI; -typedef union MP_LISTX0_11__SI regMP_LISTX0_11__SI; -typedef union MP_LISTX0_12__SI regMP_LISTX0_12__SI; -typedef union MP_LISTX0_13__SI regMP_LISTX0_13__SI; -typedef union MP_LISTX0_14__SI regMP_LISTX0_14__SI; -typedef union MP_LISTX0_15__SI regMP_LISTX0_15__SI; -typedef union MP_LISTX0_1__SI regMP_LISTX0_1__SI; -typedef union MP_LISTX0_2__SI regMP_LISTX0_2__SI; -typedef union MP_LISTX0_3__SI regMP_LISTX0_3__SI; -typedef union MP_LISTX0_4__SI regMP_LISTX0_4__SI; -typedef union MP_LISTX0_5__SI regMP_LISTX0_5__SI; -typedef union MP_LISTX0_6__SI regMP_LISTX0_6__SI; -typedef union MP_LISTX0_7__SI regMP_LISTX0_7__SI; -typedef union MP_LISTX0_8__SI regMP_LISTX0_8__SI; -typedef union MP_LISTX0_9__SI regMP_LISTX0_9__SI; -typedef union MP_LISTX1_0__SI regMP_LISTX1_0__SI; -typedef union MP_LISTX1_10__SI regMP_LISTX1_10__SI; -typedef union MP_LISTX1_11__SI regMP_LISTX1_11__SI; -typedef union MP_LISTX1_12__SI regMP_LISTX1_12__SI; -typedef union MP_LISTX1_13__SI regMP_LISTX1_13__SI; -typedef union MP_LISTX1_14__SI regMP_LISTX1_14__SI; -typedef union MP_LISTX1_15__SI regMP_LISTX1_15__SI; -typedef union MP_LISTX1_1__SI regMP_LISTX1_1__SI; -typedef union MP_LISTX1_2__SI regMP_LISTX1_2__SI; -typedef union MP_LISTX1_3__SI regMP_LISTX1_3__SI; -typedef union MP_LISTX1_4__SI regMP_LISTX1_4__SI; -typedef union MP_LISTX1_5__SI regMP_LISTX1_5__SI; -typedef union MP_LISTX1_6__SI regMP_LISTX1_6__SI; -typedef union MP_LISTX1_7__SI regMP_LISTX1_7__SI; -typedef union MP_LISTX1_8__SI regMP_LISTX1_8__SI; -typedef union MP_LISTX1_9__SI regMP_LISTX1_9__SI; -typedef union MP_LMA_ADR__SI regMP_LMA_ADR__SI; -typedef union MP_LMA_CTL__SI regMP_LMA_CTL__SI; -typedef union MP_LMA_DAT__SI regMP_LMA_DAT__SI; -typedef union MP_PPS_INFO__SI regMP_PPS_INFO__SI; -typedef union MP_SLICE_INFO__SI regMP_SLICE_INFO__SI; -typedef union MP_SPS_INFO__SI regMP_SPS_INFO__SI; -typedef union MP_SRAM_RM_CTL__SI regMP_SRAM_RM_CTL__SI; -typedef union MP_STAT__SI regMP_STAT__SI; -typedef union MP_VC1_DONE_CTXT__SI regMP_VC1_DONE_CTXT__SI; -typedef union MP_VC1_PPS_INFO__SI regMP_VC1_PPS_INFO__SI; -typedef union MP_VC1_REF_INFO__SI regMP_VC1_REF_INFO__SI; -typedef union MP_VC1_USE_HYBRIDPRED__SI regMP_VC1_USE_HYBRIDPRED__SI; -typedef union MSI_CAP_LIST regMSI_CAP_LIST; -typedef union MSI_MSG_ADDR_HI regMSI_MSG_ADDR_HI; -typedef union MSI_MSG_ADDR_LO regMSI_MSG_ADDR_LO; -typedef union MSI_MSG_CNTL regMSI_MSG_CNTL; -typedef union MSI_MSG_DATA regMSI_MSG_DATA; -typedef union MSI_MSG_DATA_64 regMSI_MSG_DATA_64; -typedef union MVP_AFR_FLIP_FIFO_CNTL__SI regMVP_AFR_FLIP_FIFO_CNTL__SI; -typedef union MVP_AFR_FLIP_MODE__SI regMVP_AFR_FLIP_MODE__SI; -typedef union MVP_BLACK_KEYER__SI regMVP_BLACK_KEYER__SI; -typedef union MVP_CONTROL1__SI regMVP_CONTROL1__SI; -typedef union MVP_CONTROL2__SI regMVP_CONTROL2__SI; -typedef union MVP_CONTROL3__SI regMVP_CONTROL3__SI; -typedef union MVP_CRC_CNTL__SI regMVP_CRC_CNTL__SI; -typedef union MVP_CRC_RESULT_BLUE_GREEN__SI regMVP_CRC_RESULT_BLUE_GREEN__SI; -typedef union MVP_CRC_RESULT_RED__SI regMVP_CRC_RESULT_RED__SI; -typedef union MVP_DEBUG_01__SI regMVP_DEBUG_01__SI; -typedef union MVP_DEBUG_02__SI regMVP_DEBUG_02__SI; -typedef union MVP_DEBUG_03__SI regMVP_DEBUG_03__SI; -typedef union MVP_DEBUG_04__SI regMVP_DEBUG_04__SI; -typedef union MVP_DEBUG_05__SI regMVP_DEBUG_05__SI; -typedef union MVP_DEBUG_06__SI regMVP_DEBUG_06__SI; -typedef union MVP_DEBUG_07__SI regMVP_DEBUG_07__SI; -typedef union MVP_DEBUG_08__SI regMVP_DEBUG_08__SI; -typedef union MVP_DEBUG_09__SI regMVP_DEBUG_09__SI; -typedef union MVP_DEBUG_10__SI regMVP_DEBUG_10__SI; -typedef union MVP_DEBUG_11__SI regMVP_DEBUG_11__SI; -typedef union MVP_DEBUG_12__SI regMVP_DEBUG_12__SI; -typedef union MVP_DEBUG_13__SI regMVP_DEBUG_13__SI; -typedef union MVP_DEBUG_14__SI regMVP_DEBUG_14__SI; -typedef union MVP_DEBUG_15__SI regMVP_DEBUG_15__SI; -typedef union MVP_DEBUG_16__SI regMVP_DEBUG_16__SI; -typedef union MVP_DEBUG_17__SI regMVP_DEBUG_17__SI; -typedef union MVP_FIFO_CONTROL__SI regMVP_FIFO_CONTROL__SI; -typedef union MVP_FIFO_STATUS__SI regMVP_FIFO_STATUS__SI; -typedef union MVP_FLIP_LINE_NUM_INSERT__SI regMVP_FLIP_LINE_NUM_INSERT__SI; -typedef union MVP_INBAND_CNTL_CAP__SI regMVP_INBAND_CNTL_CAP__SI; -typedef union MVP_RECEIVE_CNT_CNTL1__SI regMVP_RECEIVE_CNT_CNTL1__SI; -typedef union MVP_RECEIVE_CNT_CNTL2__SI regMVP_RECEIVE_CNT_CNTL2__SI; -typedef union MVP_SLAVE_STATUS__SI regMVP_SLAVE_STATUS__SI; -typedef union MVP_TEST_DEBUG_DATA__SI regMVP_TEST_DEBUG_DATA__SI; -typedef union MVP_TEST_DEBUG_INDEX__SI regMVP_TEST_DEBUG_INDEX__SI; -typedef union NB_PSTATE_CONTROL__CI__VI regNB_PSTATE_CONTROL__CI__VI; -typedef union NB_PSTATE_STATUS__CI__VI regNB_PSTATE_STATUS__CI__VI; -typedef union NEW_REFCLKB_TIMER_1__CI regNEW_REFCLKB_TIMER_1__CI; -typedef union NEW_REFCLKB_TIMER__CI regNEW_REFCLKB_TIMER__CI; -typedef union OPEN_DRAIN_SELECT regOPEN_DRAIN_SELECT; -typedef union OUTPUT_PAYLOAD_CAPABILITY__SI regOUTPUT_PAYLOAD_CAPABILITY__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_LOWER_BASE_ADDRESS__SI - regOUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_LOWER_BASE_ADDRESS__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_UPPER_BASE_ADDRESS__SI - regOUTPUT_STREAM_DESCRIPTOR_0_BDL_POINTER_UPPER_BASE_ADDRESS__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__SI - regOUTPUT_STREAM_DESCRIPTOR_0_CONTROL_AND_STATUS__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_CYCLIC_BUFFER_LENGTH__SI - regOUTPUT_STREAM_DESCRIPTOR_0_CYCLIC_BUFFER_LENGTH__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_FIFO_SIZE__SI regOUTPUT_STREAM_DESCRIPTOR_0_FIFO_SIZE__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SI regOUTPUT_STREAM_DESCRIPTOR_0_FORMAT__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_LAST_VALID_INDEX__SI - regOUTPUT_STREAM_DESCRIPTOR_0_LAST_VALID_INDEX__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__SI - regOUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__SI; -typedef union OUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER__SI - regOUTPUT_STREAM_DESCRIPTOR_0_LINK_POSITION_IN_CURRENT_BUFFER__SI; -typedef union OVLSCL_DEBUG0__SI regOVLSCL_DEBUG0__SI; -typedef union OVLSCL_DEBUG1__SI regOVLSCL_DEBUG1__SI; -typedef union OVLSCL_DEBUG2__SI regOVLSCL_DEBUG2__SI; -typedef union OVLSCL_EDGE_PIXEL_CNTL__SI regOVLSCL_EDGE_PIXEL_CNTL__SI; -typedef union OVL_ALPHA_CONTROL__SI regOVL_ALPHA_CONTROL__SI; -typedef union OVL_ALPHA__SI regOVL_ALPHA__SI; -typedef union OVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI regOVL_COLOR_MATRIX_TRANSFORMATION_CNTL__SI; -typedef union OVL_CONTROL1__SI regOVL_CONTROL1__SI; -typedef union OVL_CONTROL2__SI regOVL_CONTROL2__SI; -typedef union OVL_DFQ_CONTROL__SI regOVL_DFQ_CONTROL__SI; -typedef union OVL_DFQ_STATUS__SI regOVL_DFQ_STATUS__SI; -typedef union OVL_ENABLE__SI regOVL_ENABLE__SI; -typedef union OVL_END__SI regOVL_END__SI; -typedef union OVL_KEY_ALPHA__SI regOVL_KEY_ALPHA__SI; -typedef union OVL_KEY_CONTROL__SI regOVL_KEY_CONTROL__SI; -typedef union OVL_KEY_RANGE_BLUE_CB__SI regOVL_KEY_RANGE_BLUE_CB__SI; -typedef union OVL_KEY_RANGE_GREEN_Y__SI regOVL_KEY_RANGE_GREEN_Y__SI; -typedef union OVL_KEY_RANGE_RED_CR__SI regOVL_KEY_RANGE_RED_CR__SI; -typedef union OVL_MATRIX_COEF_1_1__SI regOVL_MATRIX_COEF_1_1__SI; -typedef union OVL_MATRIX_COEF_1_2__SI regOVL_MATRIX_COEF_1_2__SI; -typedef union OVL_MATRIX_COEF_1_3__SI regOVL_MATRIX_COEF_1_3__SI; -typedef union OVL_MATRIX_COEF_1_4__SI regOVL_MATRIX_COEF_1_4__SI; -typedef union OVL_MATRIX_COEF_2_1__SI regOVL_MATRIX_COEF_2_1__SI; -typedef union OVL_MATRIX_COEF_2_2__SI regOVL_MATRIX_COEF_2_2__SI; -typedef union OVL_MATRIX_COEF_2_3__SI regOVL_MATRIX_COEF_2_3__SI; -typedef union OVL_MATRIX_COEF_2_4__SI regOVL_MATRIX_COEF_2_4__SI; -typedef union OVL_MATRIX_COEF_3_1__SI regOVL_MATRIX_COEF_3_1__SI; -typedef union OVL_MATRIX_COEF_3_2__SI regOVL_MATRIX_COEF_3_2__SI; -typedef union OVL_MATRIX_COEF_3_3__SI regOVL_MATRIX_COEF_3_3__SI; -typedef union OVL_MATRIX_COEF_3_4__SI regOVL_MATRIX_COEF_3_4__SI; -typedef union OVL_MATRIX_TRANSFORM_EN__SI regOVL_MATRIX_TRANSFORM_EN__SI; -typedef union OVL_PITCH__SI regOVL_PITCH__SI; -typedef union OVL_PWL_0TOF__SI regOVL_PWL_0TOF__SI; -typedef union OVL_PWL_100TO13F__SI regOVL_PWL_100TO13F__SI; -typedef union OVL_PWL_10TO1F__SI regOVL_PWL_10TO1F__SI; -typedef union OVL_PWL_140TO17F__SI regOVL_PWL_140TO17F__SI; -typedef union OVL_PWL_180TO1BF__SI regOVL_PWL_180TO1BF__SI; -typedef union OVL_PWL_1C0TO1FF__SI regOVL_PWL_1C0TO1FF__SI; -typedef union OVL_PWL_200TO23F__SI regOVL_PWL_200TO23F__SI; -typedef union OVL_PWL_20TO3F__SI regOVL_PWL_20TO3F__SI; -typedef union OVL_PWL_240TO27F__SI regOVL_PWL_240TO27F__SI; -typedef union OVL_PWL_280TO2BF__SI regOVL_PWL_280TO2BF__SI; -typedef union OVL_PWL_2C0TO2FF__SI regOVL_PWL_2C0TO2FF__SI; -typedef union OVL_PWL_300TO33F__SI regOVL_PWL_300TO33F__SI; -typedef union OVL_PWL_340TO37F__SI regOVL_PWL_340TO37F__SI; -typedef union OVL_PWL_380TO3BF__SI regOVL_PWL_380TO3BF__SI; -typedef union OVL_PWL_3C0TO3FF__SI regOVL_PWL_3C0TO3FF__SI; -typedef union OVL_PWL_40TO7F__SI regOVL_PWL_40TO7F__SI; -typedef union OVL_PWL_80TOBF__SI regOVL_PWL_80TOBF__SI; -typedef union OVL_PWL_C0TOFF__SI regOVL_PWL_C0TOFF__SI; -typedef union OVL_PWL_TRANSFORM_EN__SI regOVL_PWL_TRANSFORM_EN__SI; -typedef union OVL_RT_BAND_POSITION__SI regOVL_RT_BAND_POSITION__SI; -typedef union OVL_RT_PROCEED_COND__SI regOVL_RT_PROCEED_COND__SI; -typedef union OVL_RT_SKEWCOMMAND__SI regOVL_RT_SKEWCOMMAND__SI; -typedef union OVL_RT_SKEWCONTROL__SI regOVL_RT_SKEWCONTROL__SI; -typedef union OVL_RT_STAT__SI regOVL_RT_STAT__SI; -typedef union OVL_START__SI regOVL_START__SI; -typedef union OVL_SURFACE_ADDRESS_HIGH_INUSE__SI regOVL_SURFACE_ADDRESS_HIGH_INUSE__SI; -typedef union OVL_SURFACE_ADDRESS_HIGH__SI regOVL_SURFACE_ADDRESS_HIGH__SI; -typedef union OVL_SURFACE_ADDRESS_INUSE__SI regOVL_SURFACE_ADDRESS_INUSE__SI; -typedef union OVL_SURFACE_ADDRESS__SI regOVL_SURFACE_ADDRESS__SI; -typedef union OVL_SURFACE_OFFSET_X__SI regOVL_SURFACE_OFFSET_X__SI; -typedef union OVL_SURFACE_OFFSET_Y__SI regOVL_SURFACE_OFFSET_Y__SI; -typedef union OVL_SWAP_CNTL__SI regOVL_SWAP_CNTL__SI; -typedef union OVL_UPDATE__SI regOVL_UPDATE__SI; -typedef union P1PLL_CNTL__SI regP1PLL_CNTL__SI; -typedef union P1PLL_DEBUG_CLK_SEL__SI regP1PLL_DEBUG_CLK_SEL__SI; -typedef union P1PLL_DS_CNTL__SI regP1PLL_DS_CNTL__SI; -typedef union P1PLL_IDCLKA_CNTL__SI regP1PLL_IDCLKA_CNTL__SI; -typedef union P1PLL_INT_SS_CNTL__SI regP1PLL_INT_SS_CNTL__SI; -typedef union P1PLL_UNLOCK_DETECT_CNTL__SI regP1PLL_UNLOCK_DETECT_CNTL__SI; -typedef union P1PLL_VREG_CNTL__SI regP1PLL_VREG_CNTL__SI; -typedef union P2PLL_CNTL__SI regP2PLL_CNTL__SI; -typedef union P2PLL_DEBUG_CLK_SEL__SI regP2PLL_DEBUG_CLK_SEL__SI; -typedef union P2PLL_DS_CNTL__SI regP2PLL_DS_CNTL__SI; -typedef union P2PLL_IDCLKB_CNTL__SI regP2PLL_IDCLKB_CNTL__SI; -typedef union P2PLL_INT_SS_CNTL__SI regP2PLL_INT_SS_CNTL__SI; -typedef union P2PLL_UNLOCK_DETECT_CNTL__SI regP2PLL_UNLOCK_DETECT_CNTL__SI; -typedef union P2PLL_VREG_CNTL__SI regP2PLL_VREG_CNTL__SI; -typedef union PAGE_MIRROR_CNTL regPAGE_MIRROR_CNTL; -typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; -typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; -typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; -typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; -typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; -typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; -typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; -typedef union PA_CL_NANINF_CNTL regPA_CL_NANINF_CNTL; -typedef union PA_CL_POINT_CULL_RAD regPA_CL_POINT_CULL_RAD; -typedef union PA_CL_POINT_SIZE regPA_CL_POINT_SIZE; -typedef union PA_CL_POINT_X_RAD regPA_CL_POINT_X_RAD; -typedef union PA_CL_POINT_Y_RAD regPA_CL_POINT_Y_RAD; -typedef union PA_CL_RESET_DEBUG__CI__VI regPA_CL_RESET_DEBUG__CI__VI; -typedef union PA_CL_UCP_0_W regPA_CL_UCP_0_W; -typedef union PA_CL_UCP_0_X regPA_CL_UCP_0_X; -typedef union PA_CL_UCP_0_Y regPA_CL_UCP_0_Y; -typedef union PA_CL_UCP_0_Z regPA_CL_UCP_0_Z; -typedef union PA_CL_UCP_1_W regPA_CL_UCP_1_W; -typedef union PA_CL_UCP_1_X regPA_CL_UCP_1_X; -typedef union PA_CL_UCP_1_Y regPA_CL_UCP_1_Y; -typedef union PA_CL_UCP_1_Z regPA_CL_UCP_1_Z; -typedef union PA_CL_UCP_2_W regPA_CL_UCP_2_W; -typedef union PA_CL_UCP_2_X regPA_CL_UCP_2_X; -typedef union PA_CL_UCP_2_Y regPA_CL_UCP_2_Y; -typedef union PA_CL_UCP_2_Z regPA_CL_UCP_2_Z; -typedef union PA_CL_UCP_3_W regPA_CL_UCP_3_W; -typedef union PA_CL_UCP_3_X regPA_CL_UCP_3_X; -typedef union PA_CL_UCP_3_Y regPA_CL_UCP_3_Y; -typedef union PA_CL_UCP_3_Z regPA_CL_UCP_3_Z; -typedef union PA_CL_UCP_4_W regPA_CL_UCP_4_W; -typedef union PA_CL_UCP_4_X regPA_CL_UCP_4_X; -typedef union PA_CL_UCP_4_Y regPA_CL_UCP_4_Y; -typedef union PA_CL_UCP_4_Z regPA_CL_UCP_4_Z; -typedef union PA_CL_UCP_5_W regPA_CL_UCP_5_W; -typedef union PA_CL_UCP_5_X regPA_CL_UCP_5_X; -typedef union PA_CL_UCP_5_Y regPA_CL_UCP_5_Y; -typedef union PA_CL_UCP_5_Z regPA_CL_UCP_5_Z; -typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; -typedef union PA_CL_VPORT_XOFFSET_1 regPA_CL_VPORT_XOFFSET_1; -typedef union PA_CL_VPORT_XOFFSET_10 regPA_CL_VPORT_XOFFSET_10; -typedef union PA_CL_VPORT_XOFFSET_11 regPA_CL_VPORT_XOFFSET_11; -typedef union PA_CL_VPORT_XOFFSET_12 regPA_CL_VPORT_XOFFSET_12; -typedef union PA_CL_VPORT_XOFFSET_13 regPA_CL_VPORT_XOFFSET_13; -typedef union PA_CL_VPORT_XOFFSET_14 regPA_CL_VPORT_XOFFSET_14; -typedef union PA_CL_VPORT_XOFFSET_15 regPA_CL_VPORT_XOFFSET_15; -typedef union PA_CL_VPORT_XOFFSET_2 regPA_CL_VPORT_XOFFSET_2; -typedef union PA_CL_VPORT_XOFFSET_3 regPA_CL_VPORT_XOFFSET_3; -typedef union PA_CL_VPORT_XOFFSET_4 regPA_CL_VPORT_XOFFSET_4; -typedef union PA_CL_VPORT_XOFFSET_5 regPA_CL_VPORT_XOFFSET_5; -typedef union PA_CL_VPORT_XOFFSET_6 regPA_CL_VPORT_XOFFSET_6; -typedef union PA_CL_VPORT_XOFFSET_7 regPA_CL_VPORT_XOFFSET_7; -typedef union PA_CL_VPORT_XOFFSET_8 regPA_CL_VPORT_XOFFSET_8; -typedef union PA_CL_VPORT_XOFFSET_9 regPA_CL_VPORT_XOFFSET_9; -typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; -typedef union PA_CL_VPORT_XSCALE_1 regPA_CL_VPORT_XSCALE_1; -typedef union PA_CL_VPORT_XSCALE_10 regPA_CL_VPORT_XSCALE_10; -typedef union PA_CL_VPORT_XSCALE_11 regPA_CL_VPORT_XSCALE_11; -typedef union PA_CL_VPORT_XSCALE_12 regPA_CL_VPORT_XSCALE_12; -typedef union PA_CL_VPORT_XSCALE_13 regPA_CL_VPORT_XSCALE_13; -typedef union PA_CL_VPORT_XSCALE_14 regPA_CL_VPORT_XSCALE_14; -typedef union PA_CL_VPORT_XSCALE_15 regPA_CL_VPORT_XSCALE_15; -typedef union PA_CL_VPORT_XSCALE_2 regPA_CL_VPORT_XSCALE_2; -typedef union PA_CL_VPORT_XSCALE_3 regPA_CL_VPORT_XSCALE_3; -typedef union PA_CL_VPORT_XSCALE_4 regPA_CL_VPORT_XSCALE_4; -typedef union PA_CL_VPORT_XSCALE_5 regPA_CL_VPORT_XSCALE_5; -typedef union PA_CL_VPORT_XSCALE_6 regPA_CL_VPORT_XSCALE_6; -typedef union PA_CL_VPORT_XSCALE_7 regPA_CL_VPORT_XSCALE_7; -typedef union PA_CL_VPORT_XSCALE_8 regPA_CL_VPORT_XSCALE_8; -typedef union PA_CL_VPORT_XSCALE_9 regPA_CL_VPORT_XSCALE_9; -typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; -typedef union PA_CL_VPORT_YOFFSET_1 regPA_CL_VPORT_YOFFSET_1; -typedef union PA_CL_VPORT_YOFFSET_10 regPA_CL_VPORT_YOFFSET_10; -typedef union PA_CL_VPORT_YOFFSET_11 regPA_CL_VPORT_YOFFSET_11; -typedef union PA_CL_VPORT_YOFFSET_12 regPA_CL_VPORT_YOFFSET_12; -typedef union PA_CL_VPORT_YOFFSET_13 regPA_CL_VPORT_YOFFSET_13; -typedef union PA_CL_VPORT_YOFFSET_14 regPA_CL_VPORT_YOFFSET_14; -typedef union PA_CL_VPORT_YOFFSET_15 regPA_CL_VPORT_YOFFSET_15; -typedef union PA_CL_VPORT_YOFFSET_2 regPA_CL_VPORT_YOFFSET_2; -typedef union PA_CL_VPORT_YOFFSET_3 regPA_CL_VPORT_YOFFSET_3; -typedef union PA_CL_VPORT_YOFFSET_4 regPA_CL_VPORT_YOFFSET_4; -typedef union PA_CL_VPORT_YOFFSET_5 regPA_CL_VPORT_YOFFSET_5; -typedef union PA_CL_VPORT_YOFFSET_6 regPA_CL_VPORT_YOFFSET_6; -typedef union PA_CL_VPORT_YOFFSET_7 regPA_CL_VPORT_YOFFSET_7; -typedef union PA_CL_VPORT_YOFFSET_8 regPA_CL_VPORT_YOFFSET_8; -typedef union PA_CL_VPORT_YOFFSET_9 regPA_CL_VPORT_YOFFSET_9; -typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; -typedef union PA_CL_VPORT_YSCALE_1 regPA_CL_VPORT_YSCALE_1; -typedef union PA_CL_VPORT_YSCALE_10 regPA_CL_VPORT_YSCALE_10; -typedef union PA_CL_VPORT_YSCALE_11 regPA_CL_VPORT_YSCALE_11; -typedef union PA_CL_VPORT_YSCALE_12 regPA_CL_VPORT_YSCALE_12; -typedef union PA_CL_VPORT_YSCALE_13 regPA_CL_VPORT_YSCALE_13; -typedef union PA_CL_VPORT_YSCALE_14 regPA_CL_VPORT_YSCALE_14; -typedef union PA_CL_VPORT_YSCALE_15 regPA_CL_VPORT_YSCALE_15; -typedef union PA_CL_VPORT_YSCALE_2 regPA_CL_VPORT_YSCALE_2; -typedef union PA_CL_VPORT_YSCALE_3 regPA_CL_VPORT_YSCALE_3; -typedef union PA_CL_VPORT_YSCALE_4 regPA_CL_VPORT_YSCALE_4; -typedef union PA_CL_VPORT_YSCALE_5 regPA_CL_VPORT_YSCALE_5; -typedef union PA_CL_VPORT_YSCALE_6 regPA_CL_VPORT_YSCALE_6; -typedef union PA_CL_VPORT_YSCALE_7 regPA_CL_VPORT_YSCALE_7; -typedef union PA_CL_VPORT_YSCALE_8 regPA_CL_VPORT_YSCALE_8; -typedef union PA_CL_VPORT_YSCALE_9 regPA_CL_VPORT_YSCALE_9; -typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; -typedef union PA_CL_VPORT_ZOFFSET_1 regPA_CL_VPORT_ZOFFSET_1; -typedef union PA_CL_VPORT_ZOFFSET_10 regPA_CL_VPORT_ZOFFSET_10; -typedef union PA_CL_VPORT_ZOFFSET_11 regPA_CL_VPORT_ZOFFSET_11; -typedef union PA_CL_VPORT_ZOFFSET_12 regPA_CL_VPORT_ZOFFSET_12; -typedef union PA_CL_VPORT_ZOFFSET_13 regPA_CL_VPORT_ZOFFSET_13; -typedef union PA_CL_VPORT_ZOFFSET_14 regPA_CL_VPORT_ZOFFSET_14; -typedef union PA_CL_VPORT_ZOFFSET_15 regPA_CL_VPORT_ZOFFSET_15; -typedef union PA_CL_VPORT_ZOFFSET_2 regPA_CL_VPORT_ZOFFSET_2; -typedef union PA_CL_VPORT_ZOFFSET_3 regPA_CL_VPORT_ZOFFSET_3; -typedef union PA_CL_VPORT_ZOFFSET_4 regPA_CL_VPORT_ZOFFSET_4; -typedef union PA_CL_VPORT_ZOFFSET_5 regPA_CL_VPORT_ZOFFSET_5; -typedef union PA_CL_VPORT_ZOFFSET_6 regPA_CL_VPORT_ZOFFSET_6; -typedef union PA_CL_VPORT_ZOFFSET_7 regPA_CL_VPORT_ZOFFSET_7; -typedef union PA_CL_VPORT_ZOFFSET_8 regPA_CL_VPORT_ZOFFSET_8; -typedef union PA_CL_VPORT_ZOFFSET_9 regPA_CL_VPORT_ZOFFSET_9; -typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; -typedef union PA_CL_VPORT_ZSCALE_1 regPA_CL_VPORT_ZSCALE_1; -typedef union PA_CL_VPORT_ZSCALE_10 regPA_CL_VPORT_ZSCALE_10; -typedef union PA_CL_VPORT_ZSCALE_11 regPA_CL_VPORT_ZSCALE_11; -typedef union PA_CL_VPORT_ZSCALE_12 regPA_CL_VPORT_ZSCALE_12; -typedef union PA_CL_VPORT_ZSCALE_13 regPA_CL_VPORT_ZSCALE_13; -typedef union PA_CL_VPORT_ZSCALE_14 regPA_CL_VPORT_ZSCALE_14; -typedef union PA_CL_VPORT_ZSCALE_15 regPA_CL_VPORT_ZSCALE_15; -typedef union PA_CL_VPORT_ZSCALE_2 regPA_CL_VPORT_ZSCALE_2; -typedef union PA_CL_VPORT_ZSCALE_3 regPA_CL_VPORT_ZSCALE_3; -typedef union PA_CL_VPORT_ZSCALE_4 regPA_CL_VPORT_ZSCALE_4; -typedef union PA_CL_VPORT_ZSCALE_5 regPA_CL_VPORT_ZSCALE_5; -typedef union PA_CL_VPORT_ZSCALE_6 regPA_CL_VPORT_ZSCALE_6; -typedef union PA_CL_VPORT_ZSCALE_7 regPA_CL_VPORT_ZSCALE_7; -typedef union PA_CL_VPORT_ZSCALE_8 regPA_CL_VPORT_ZSCALE_8; -typedef union PA_CL_VPORT_ZSCALE_9 regPA_CL_VPORT_ZSCALE_9; -typedef union PA_CL_VS_OUT_CNTL regPA_CL_VS_OUT_CNTL; -typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; -typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; -typedef union PA_SC_AA_MASK_X0Y0_X1Y0 regPA_SC_AA_MASK_X0Y0_X1Y0; -typedef union PA_SC_AA_MASK_X0Y1_X1Y1 regPA_SC_AA_MASK_X0Y1_X1Y1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3; -typedef union PA_SC_CENTROID_PRIORITY_0 regPA_SC_CENTROID_PRIORITY_0; -typedef union PA_SC_CENTROID_PRIORITY_1 regPA_SC_CENTROID_PRIORITY_1; -typedef union PA_SC_CLIPRECT_0_BR regPA_SC_CLIPRECT_0_BR; -typedef union PA_SC_CLIPRECT_0_TL regPA_SC_CLIPRECT_0_TL; -typedef union PA_SC_CLIPRECT_1_BR regPA_SC_CLIPRECT_1_BR; -typedef union PA_SC_CLIPRECT_1_TL regPA_SC_CLIPRECT_1_TL; -typedef union PA_SC_CLIPRECT_2_BR regPA_SC_CLIPRECT_2_BR; -typedef union PA_SC_CLIPRECT_2_TL regPA_SC_CLIPRECT_2_TL; -typedef union PA_SC_CLIPRECT_3_BR regPA_SC_CLIPRECT_3_BR; -typedef union PA_SC_CLIPRECT_3_TL regPA_SC_CLIPRECT_3_TL; -typedef union PA_SC_CLIPRECT_RULE regPA_SC_CLIPRECT_RULE; -typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; -typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; -typedef union PA_SC_DEBUG_REG0 regPA_SC_DEBUG_REG0; -typedef union PA_SC_DEBUG_REG1 regPA_SC_DEBUG_REG1; -typedef union PA_SC_EDGERULE regPA_SC_EDGERULE; -typedef union PA_SC_ENHANCE__CI__VI regPA_SC_ENHANCE__CI__VI; -typedef union PA_SC_ENHANCE__SI regPA_SC_ENHANCE__SI; -typedef union PA_SC_FIFO_DEPTH_CNTL regPA_SC_FIFO_DEPTH_CNTL; -typedef union PA_SC_FIFO_SIZE regPA_SC_FIFO_SIZE; -typedef union PA_SC_FORCE_EOV_MAX_CNTS regPA_SC_FORCE_EOV_MAX_CNTS; -typedef union PA_SC_GENERIC_SCISSOR_BR regPA_SC_GENERIC_SCISSOR_BR; -typedef union PA_SC_GENERIC_SCISSOR_TL regPA_SC_GENERIC_SCISSOR_TL; -typedef union PA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI regPA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI; -typedef union PA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI regPA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI; -typedef union PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI; -typedef union PA_SC_HP3D_TRAP_SCREEN_H__CI__VI regPA_SC_HP3D_TRAP_SCREEN_H__CI__VI; -typedef union PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI - regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI; -typedef union PA_SC_HP3D_TRAP_SCREEN_V__CI__VI regPA_SC_HP3D_TRAP_SCREEN_V__CI__VI; -typedef union PA_SC_IF_FIFO_SIZE regPA_SC_IF_FIFO_SIZE; -typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; -typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; -typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; -typedef union PA_SC_MODE_CNTL_0 regPA_SC_MODE_CNTL_0; -typedef union PA_SC_MODE_CNTL_1 regPA_SC_MODE_CNTL_1; -typedef union PA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI regPA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI; -typedef union PA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI regPA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI; -typedef union PA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI regPA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI; -typedef union PA_SC_P3D_TRAP_SCREEN_H__CI__VI regPA_SC_P3D_TRAP_SCREEN_H__CI__VI; -typedef union PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI; -typedef union PA_SC_P3D_TRAP_SCREEN_V__CI__VI regPA_SC_P3D_TRAP_SCREEN_V__CI__VI; -typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; -typedef union PA_SC_PERFCOUNTER0_LO regPA_SC_PERFCOUNTER0_LO; -typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; -typedef union PA_SC_PERFCOUNTER0_SELECT1__CI__VI regPA_SC_PERFCOUNTER0_SELECT1__CI__VI; -typedef union PA_SC_PERFCOUNTER1_HI regPA_SC_PERFCOUNTER1_HI; -typedef union PA_SC_PERFCOUNTER1_LO regPA_SC_PERFCOUNTER1_LO; -typedef union PA_SC_PERFCOUNTER1_SELECT regPA_SC_PERFCOUNTER1_SELECT; -typedef union PA_SC_PERFCOUNTER2_HI regPA_SC_PERFCOUNTER2_HI; -typedef union PA_SC_PERFCOUNTER2_LO regPA_SC_PERFCOUNTER2_LO; -typedef union PA_SC_PERFCOUNTER2_SELECT regPA_SC_PERFCOUNTER2_SELECT; -typedef union PA_SC_PERFCOUNTER3_HI regPA_SC_PERFCOUNTER3_HI; -typedef union PA_SC_PERFCOUNTER3_LO regPA_SC_PERFCOUNTER3_LO; -typedef union PA_SC_PERFCOUNTER3_SELECT regPA_SC_PERFCOUNTER3_SELECT; -typedef union PA_SC_PERFCOUNTER4_HI regPA_SC_PERFCOUNTER4_HI; -typedef union PA_SC_PERFCOUNTER4_LO regPA_SC_PERFCOUNTER4_LO; -typedef union PA_SC_PERFCOUNTER4_SELECT regPA_SC_PERFCOUNTER4_SELECT; -typedef union PA_SC_PERFCOUNTER5_HI regPA_SC_PERFCOUNTER5_HI; -typedef union PA_SC_PERFCOUNTER5_LO regPA_SC_PERFCOUNTER5_LO; -typedef union PA_SC_PERFCOUNTER5_SELECT regPA_SC_PERFCOUNTER5_SELECT; -typedef union PA_SC_PERFCOUNTER6_HI regPA_SC_PERFCOUNTER6_HI; -typedef union PA_SC_PERFCOUNTER6_LO regPA_SC_PERFCOUNTER6_LO; -typedef union PA_SC_PERFCOUNTER6_SELECT regPA_SC_PERFCOUNTER6_SELECT; -typedef union PA_SC_PERFCOUNTER7_HI regPA_SC_PERFCOUNTER7_HI; -typedef union PA_SC_PERFCOUNTER7_LO regPA_SC_PERFCOUNTER7_LO; -typedef union PA_SC_PERFCOUNTER7_SELECT regPA_SC_PERFCOUNTER7_SELECT; -typedef union PA_SC_RASTER_CONFIG regPA_SC_RASTER_CONFIG; -typedef union PA_SC_RASTER_CONFIG_1__CI__VI regPA_SC_RASTER_CONFIG_1__CI__VI; -typedef union PA_SC_SCREEN_EXTENT_CONTROL__CI__VI regPA_SC_SCREEN_EXTENT_CONTROL__CI__VI; -typedef union PA_SC_SCREEN_EXTENT_MAX_0__CI__VI regPA_SC_SCREEN_EXTENT_MAX_0__CI__VI; -typedef union PA_SC_SCREEN_EXTENT_MAX_1__CI__VI regPA_SC_SCREEN_EXTENT_MAX_1__CI__VI; -typedef union PA_SC_SCREEN_EXTENT_MIN_0__CI__VI regPA_SC_SCREEN_EXTENT_MIN_0__CI__VI; -typedef union PA_SC_SCREEN_EXTENT_MIN_1__CI__VI regPA_SC_SCREEN_EXTENT_MIN_1__CI__VI; -typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; -typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; -typedef union PA_SC_TRAP_SCREEN_COUNT__CI__VI regPA_SC_TRAP_SCREEN_COUNT__CI__VI; -typedef union PA_SC_TRAP_SCREEN_HV_EN__CI__VI regPA_SC_TRAP_SCREEN_HV_EN__CI__VI; -typedef union PA_SC_TRAP_SCREEN_HV_LOCK__CI__VI regPA_SC_TRAP_SCREEN_HV_LOCK__CI__VI; -typedef union PA_SC_TRAP_SCREEN_H__CI__VI regPA_SC_TRAP_SCREEN_H__CI__VI; -typedef union PA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI regPA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI; -typedef union PA_SC_TRAP_SCREEN_V__CI__VI regPA_SC_TRAP_SCREEN_V__CI__VI; -typedef union PA_SC_VPORT_SCISSOR_0_BR regPA_SC_VPORT_SCISSOR_0_BR; -typedef union PA_SC_VPORT_SCISSOR_0_TL regPA_SC_VPORT_SCISSOR_0_TL; -typedef union PA_SC_VPORT_SCISSOR_10_BR regPA_SC_VPORT_SCISSOR_10_BR; -typedef union PA_SC_VPORT_SCISSOR_10_TL regPA_SC_VPORT_SCISSOR_10_TL; -typedef union PA_SC_VPORT_SCISSOR_11_BR regPA_SC_VPORT_SCISSOR_11_BR; -typedef union PA_SC_VPORT_SCISSOR_11_TL regPA_SC_VPORT_SCISSOR_11_TL; -typedef union PA_SC_VPORT_SCISSOR_12_BR regPA_SC_VPORT_SCISSOR_12_BR; -typedef union PA_SC_VPORT_SCISSOR_12_TL regPA_SC_VPORT_SCISSOR_12_TL; -typedef union PA_SC_VPORT_SCISSOR_13_BR regPA_SC_VPORT_SCISSOR_13_BR; -typedef union PA_SC_VPORT_SCISSOR_13_TL regPA_SC_VPORT_SCISSOR_13_TL; -typedef union PA_SC_VPORT_SCISSOR_14_BR regPA_SC_VPORT_SCISSOR_14_BR; -typedef union PA_SC_VPORT_SCISSOR_14_TL regPA_SC_VPORT_SCISSOR_14_TL; -typedef union PA_SC_VPORT_SCISSOR_15_BR regPA_SC_VPORT_SCISSOR_15_BR; -typedef union PA_SC_VPORT_SCISSOR_15_TL regPA_SC_VPORT_SCISSOR_15_TL; -typedef union PA_SC_VPORT_SCISSOR_1_BR regPA_SC_VPORT_SCISSOR_1_BR; -typedef union PA_SC_VPORT_SCISSOR_1_TL regPA_SC_VPORT_SCISSOR_1_TL; -typedef union PA_SC_VPORT_SCISSOR_2_BR regPA_SC_VPORT_SCISSOR_2_BR; -typedef union PA_SC_VPORT_SCISSOR_2_TL regPA_SC_VPORT_SCISSOR_2_TL; -typedef union PA_SC_VPORT_SCISSOR_3_BR regPA_SC_VPORT_SCISSOR_3_BR; -typedef union PA_SC_VPORT_SCISSOR_3_TL regPA_SC_VPORT_SCISSOR_3_TL; -typedef union PA_SC_VPORT_SCISSOR_4_BR regPA_SC_VPORT_SCISSOR_4_BR; -typedef union PA_SC_VPORT_SCISSOR_4_TL regPA_SC_VPORT_SCISSOR_4_TL; -typedef union PA_SC_VPORT_SCISSOR_5_BR regPA_SC_VPORT_SCISSOR_5_BR; -typedef union PA_SC_VPORT_SCISSOR_5_TL regPA_SC_VPORT_SCISSOR_5_TL; -typedef union PA_SC_VPORT_SCISSOR_6_BR regPA_SC_VPORT_SCISSOR_6_BR; -typedef union PA_SC_VPORT_SCISSOR_6_TL regPA_SC_VPORT_SCISSOR_6_TL; -typedef union PA_SC_VPORT_SCISSOR_7_BR regPA_SC_VPORT_SCISSOR_7_BR; -typedef union PA_SC_VPORT_SCISSOR_7_TL regPA_SC_VPORT_SCISSOR_7_TL; -typedef union PA_SC_VPORT_SCISSOR_8_BR regPA_SC_VPORT_SCISSOR_8_BR; -typedef union PA_SC_VPORT_SCISSOR_8_TL regPA_SC_VPORT_SCISSOR_8_TL; -typedef union PA_SC_VPORT_SCISSOR_9_BR regPA_SC_VPORT_SCISSOR_9_BR; -typedef union PA_SC_VPORT_SCISSOR_9_TL regPA_SC_VPORT_SCISSOR_9_TL; -typedef union PA_SC_VPORT_ZMAX_0 regPA_SC_VPORT_ZMAX_0; -typedef union PA_SC_VPORT_ZMAX_1 regPA_SC_VPORT_ZMAX_1; -typedef union PA_SC_VPORT_ZMAX_10 regPA_SC_VPORT_ZMAX_10; -typedef union PA_SC_VPORT_ZMAX_11 regPA_SC_VPORT_ZMAX_11; -typedef union PA_SC_VPORT_ZMAX_12 regPA_SC_VPORT_ZMAX_12; -typedef union PA_SC_VPORT_ZMAX_13 regPA_SC_VPORT_ZMAX_13; -typedef union PA_SC_VPORT_ZMAX_14 regPA_SC_VPORT_ZMAX_14; -typedef union PA_SC_VPORT_ZMAX_15 regPA_SC_VPORT_ZMAX_15; -typedef union PA_SC_VPORT_ZMAX_2 regPA_SC_VPORT_ZMAX_2; -typedef union PA_SC_VPORT_ZMAX_3 regPA_SC_VPORT_ZMAX_3; -typedef union PA_SC_VPORT_ZMAX_4 regPA_SC_VPORT_ZMAX_4; -typedef union PA_SC_VPORT_ZMAX_5 regPA_SC_VPORT_ZMAX_5; -typedef union PA_SC_VPORT_ZMAX_6 regPA_SC_VPORT_ZMAX_6; -typedef union PA_SC_VPORT_ZMAX_7 regPA_SC_VPORT_ZMAX_7; -typedef union PA_SC_VPORT_ZMAX_8 regPA_SC_VPORT_ZMAX_8; -typedef union PA_SC_VPORT_ZMAX_9 regPA_SC_VPORT_ZMAX_9; -typedef union PA_SC_VPORT_ZMIN_0 regPA_SC_VPORT_ZMIN_0; -typedef union PA_SC_VPORT_ZMIN_1 regPA_SC_VPORT_ZMIN_1; -typedef union PA_SC_VPORT_ZMIN_10 regPA_SC_VPORT_ZMIN_10; -typedef union PA_SC_VPORT_ZMIN_11 regPA_SC_VPORT_ZMIN_11; -typedef union PA_SC_VPORT_ZMIN_12 regPA_SC_VPORT_ZMIN_12; -typedef union PA_SC_VPORT_ZMIN_13 regPA_SC_VPORT_ZMIN_13; -typedef union PA_SC_VPORT_ZMIN_14 regPA_SC_VPORT_ZMIN_14; -typedef union PA_SC_VPORT_ZMIN_15 regPA_SC_VPORT_ZMIN_15; -typedef union PA_SC_VPORT_ZMIN_2 regPA_SC_VPORT_ZMIN_2; -typedef union PA_SC_VPORT_ZMIN_3 regPA_SC_VPORT_ZMIN_3; -typedef union PA_SC_VPORT_ZMIN_4 regPA_SC_VPORT_ZMIN_4; -typedef union PA_SC_VPORT_ZMIN_5 regPA_SC_VPORT_ZMIN_5; -typedef union PA_SC_VPORT_ZMIN_6 regPA_SC_VPORT_ZMIN_6; -typedef union PA_SC_VPORT_ZMIN_7 regPA_SC_VPORT_ZMIN_7; -typedef union PA_SC_VPORT_ZMIN_8 regPA_SC_VPORT_ZMIN_8; -typedef union PA_SC_VPORT_ZMIN_9 regPA_SC_VPORT_ZMIN_9; -typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; -typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; -typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; -typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; -typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; -typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; -typedef union PA_SU_HARDWARE_SCREEN_OFFSET regPA_SU_HARDWARE_SCREEN_OFFSET; -typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; -typedef union PA_SU_LINE_STIPPLE_CNTL regPA_SU_LINE_STIPPLE_CNTL; -typedef union PA_SU_LINE_STIPPLE_SCALE regPA_SU_LINE_STIPPLE_SCALE; -typedef union PA_SU_LINE_STIPPLE_VALUE regPA_SU_LINE_STIPPLE_VALUE; -typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; -typedef union PA_SU_PERFCOUNTER0_LO regPA_SU_PERFCOUNTER0_LO; -typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; -typedef union PA_SU_PERFCOUNTER0_SELECT1__CI__VI regPA_SU_PERFCOUNTER0_SELECT1__CI__VI; -typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; -typedef union PA_SU_PERFCOUNTER1_LO regPA_SU_PERFCOUNTER1_LO; -typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; -typedef union PA_SU_PERFCOUNTER1_SELECT1__CI__VI regPA_SU_PERFCOUNTER1_SELECT1__CI__VI; -typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; -typedef union PA_SU_PERFCOUNTER2_LO regPA_SU_PERFCOUNTER2_LO; -typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; -typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; -typedef union PA_SU_PERFCOUNTER3_LO regPA_SU_PERFCOUNTER3_LO; -typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; -typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; -typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; -typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; -typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; -typedef union PA_SU_POLY_OFFSET_CLAMP regPA_SU_POLY_OFFSET_CLAMP; -typedef union PA_SU_POLY_OFFSET_DB_FMT_CNTL regPA_SU_POLY_OFFSET_DB_FMT_CNTL; -typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; -typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; -typedef union PA_SU_PRIM_FILTER_CNTL regPA_SU_PRIM_FILTER_CNTL; -typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; -typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; -typedef union PB0_DFT_DEBUG_CTRL_REG0__CI__VI regPB0_DFT_DEBUG_CTRL_REG0__CI__VI; -typedef union PB0_DFT_JIT_INJ_REG0__CI__VI regPB0_DFT_JIT_INJ_REG0__CI__VI; -typedef union PB0_DFT_JIT_INJ_REG1__CI__VI regPB0_DFT_JIT_INJ_REG1__CI__VI; -typedef union PB0_DFT_JIT_INJ_REG2__CI__VI regPB0_DFT_JIT_INJ_REG2__CI__VI; -typedef union PB0_DFT_JIT_INJ_STAT_REG0__CI__VI regPB0_DFT_JIT_INJ_STAT_REG0__CI__VI; -typedef union PB0_GLB_CTRL_REG0__CI__VI regPB0_GLB_CTRL_REG0__CI__VI; -typedef union PB0_GLB_CTRL_REG1__CI__VI regPB0_GLB_CTRL_REG1__CI__VI; -typedef union PB0_GLB_CTRL_REG2__CI__VI regPB0_GLB_CTRL_REG2__CI__VI; -typedef union PB0_GLB_CTRL_REG3__CI__VI regPB0_GLB_CTRL_REG3__CI__VI; -typedef union PB0_GLB_CTRL_REG4__CI__VI regPB0_GLB_CTRL_REG4__CI__VI; -typedef union PB0_GLB_CTRL_REG5__CI__VI regPB0_GLB_CTRL_REG5__CI__VI; -typedef union PB0_GLB_OVRD_REG0__CI__VI regPB0_GLB_OVRD_REG0__CI__VI; -typedef union PB0_GLB_OVRD_REG1__CI__VI regPB0_GLB_OVRD_REG1__CI__VI; -typedef union PB0_GLB_OVRD_REG2__CI__VI regPB0_GLB_OVRD_REG2__CI__VI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG0__CI regPB0_GLB_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG0__VI regPB0_GLB_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG1__CI regPB0_GLB_SCI_STAT_OVRD_REG1__CI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG1__VI regPB0_GLB_SCI_STAT_OVRD_REG1__VI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG2__CI regPB0_GLB_SCI_STAT_OVRD_REG2__CI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG2__VI regPB0_GLB_SCI_STAT_OVRD_REG2__VI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG3__CI regPB0_GLB_SCI_STAT_OVRD_REG3__CI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG3__VI regPB0_GLB_SCI_STAT_OVRD_REG3__VI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG4__CI regPB0_GLB_SCI_STAT_OVRD_REG4__CI; -typedef union PB0_GLB_SCI_STAT_OVRD_REG4__VI regPB0_GLB_SCI_STAT_OVRD_REG4__VI; -typedef union PB0_HW_DEBUG__CI regPB0_HW_DEBUG__CI; -typedef union PB0_HW_DEBUG__VI regPB0_HW_DEBUG__VI; -typedef union PB0_PIF_CNTL2__CI regPB0_PIF_CNTL2__CI; -typedef union PB0_PIF_CNTL__CI regPB0_PIF_CNTL__CI; -typedef union PB0_PIF_HW_DEBUG__CI regPB0_PIF_HW_DEBUG__CI; -typedef union PB0_PIF_HW_DEBUG__VI regPB0_PIF_HW_DEBUG__VI; -typedef union PB0_PIF_PAIRING__CI regPB0_PIF_PAIRING__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_0__CI regPB0_PIF_PDNB_OVERRIDE_0__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_10__CI regPB0_PIF_PDNB_OVERRIDE_10__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_11__CI regPB0_PIF_PDNB_OVERRIDE_11__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_12__CI regPB0_PIF_PDNB_OVERRIDE_12__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_13__CI regPB0_PIF_PDNB_OVERRIDE_13__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_14__CI regPB0_PIF_PDNB_OVERRIDE_14__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_15__CI regPB0_PIF_PDNB_OVERRIDE_15__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_1__CI regPB0_PIF_PDNB_OVERRIDE_1__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_2__CI regPB0_PIF_PDNB_OVERRIDE_2__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_3__CI regPB0_PIF_PDNB_OVERRIDE_3__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_4__CI regPB0_PIF_PDNB_OVERRIDE_4__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_5__CI regPB0_PIF_PDNB_OVERRIDE_5__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_6__CI regPB0_PIF_PDNB_OVERRIDE_6__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_7__CI regPB0_PIF_PDNB_OVERRIDE_7__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_8__CI regPB0_PIF_PDNB_OVERRIDE_8__CI; -typedef union PB0_PIF_PDNB_OVERRIDE_9__CI regPB0_PIF_PDNB_OVERRIDE_9__CI; -typedef union PB0_PIF_PWRDOWN_0__CI regPB0_PIF_PWRDOWN_0__CI; -typedef union PB0_PIF_PWRDOWN_1__CI regPB0_PIF_PWRDOWN_1__CI; -typedef union PB0_PIF_PWRDOWN_2__CI regPB0_PIF_PWRDOWN_2__CI; -typedef union PB0_PIF_PWRDOWN_3__CI regPB0_PIF_PWRDOWN_3__CI; -typedef union PB0_PIF_SCRATCH__CI__VI regPB0_PIF_SCRATCH__CI__VI; -typedef union PB0_PIF_SC_CTL__CI regPB0_PIF_SC_CTL__CI; -typedef union PB0_PIF_SEQ_STATUS_0__CI regPB0_PIF_SEQ_STATUS_0__CI; -typedef union PB0_PIF_SEQ_STATUS_10__CI regPB0_PIF_SEQ_STATUS_10__CI; -typedef union PB0_PIF_SEQ_STATUS_11__CI regPB0_PIF_SEQ_STATUS_11__CI; -typedef union PB0_PIF_SEQ_STATUS_12__CI regPB0_PIF_SEQ_STATUS_12__CI; -typedef union PB0_PIF_SEQ_STATUS_13__CI regPB0_PIF_SEQ_STATUS_13__CI; -typedef union PB0_PIF_SEQ_STATUS_14__CI regPB0_PIF_SEQ_STATUS_14__CI; -typedef union PB0_PIF_SEQ_STATUS_15__CI regPB0_PIF_SEQ_STATUS_15__CI; -typedef union PB0_PIF_SEQ_STATUS_1__CI regPB0_PIF_SEQ_STATUS_1__CI; -typedef union PB0_PIF_SEQ_STATUS_2__CI regPB0_PIF_SEQ_STATUS_2__CI; -typedef union PB0_PIF_SEQ_STATUS_3__CI regPB0_PIF_SEQ_STATUS_3__CI; -typedef union PB0_PIF_SEQ_STATUS_4__CI regPB0_PIF_SEQ_STATUS_4__CI; -typedef union PB0_PIF_SEQ_STATUS_5__CI regPB0_PIF_SEQ_STATUS_5__CI; -typedef union PB0_PIF_SEQ_STATUS_6__CI regPB0_PIF_SEQ_STATUS_6__CI; -typedef union PB0_PIF_SEQ_STATUS_7__CI regPB0_PIF_SEQ_STATUS_7__CI; -typedef union PB0_PIF_SEQ_STATUS_8__CI regPB0_PIF_SEQ_STATUS_8__CI; -typedef union PB0_PIF_SEQ_STATUS_9__CI regPB0_PIF_SEQ_STATUS_9__CI; -typedef union PB0_PIF_TXPHYSTATUS__CI regPB0_PIF_TXPHYSTATUS__CI; -typedef union PB0_PLL_LC0_CTRL_REG0__CI__VI regPB0_PLL_LC0_CTRL_REG0__CI__VI; -typedef union PB0_PLL_LC0_OVRD_REG0__CI__VI regPB0_PLL_LC0_OVRD_REG0__CI__VI; -typedef union PB0_PLL_LC0_OVRD_REG1__CI__VI regPB0_PLL_LC0_OVRD_REG1__CI__VI; -typedef union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC0_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC0_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC1_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC1_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC2_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC2_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC3_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC3_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_RO0_CTRL_REG0__CI__VI regPB0_PLL_RO0_CTRL_REG0__CI__VI; -typedef union PB0_PLL_RO0_OVRD_REG0__CI__VI regPB0_PLL_RO0_OVRD_REG0__CI__VI; -typedef union PB0_PLL_RO0_OVRD_REG1__CI__VI regPB0_PLL_RO0_OVRD_REG1__CI__VI; -typedef union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO0_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO0_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO1_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO1_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO2_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO2_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO3_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO3_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_PLL_RO_GLB_CTRL_REG0__CI regPB0_PLL_RO_GLB_CTRL_REG0__CI; -typedef union PB0_PLL_RO_GLB_CTRL_REG0__VI regPB0_PLL_RO_GLB_CTRL_REG0__VI; -typedef union PB0_PLL_RO_GLB_OVRD_REG0__CI__VI regPB0_PLL_RO_GLB_OVRD_REG0__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG0__CI__VI regPB0_RX_GLB_CTRL_REG0__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG1__CI__VI regPB0_RX_GLB_CTRL_REG1__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG2__CI__VI regPB0_RX_GLB_CTRL_REG2__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG3__CI__VI regPB0_RX_GLB_CTRL_REG3__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG4__CI__VI regPB0_RX_GLB_CTRL_REG4__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG5__CI__VI regPB0_RX_GLB_CTRL_REG5__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG6__CI__VI regPB0_RX_GLB_CTRL_REG6__CI__VI; -typedef union PB0_RX_GLB_CTRL_REG7__CI regPB0_RX_GLB_CTRL_REG7__CI; -typedef union PB0_RX_GLB_CTRL_REG7__VI regPB0_RX_GLB_CTRL_REG7__VI; -typedef union PB0_RX_GLB_CTRL_REG8__CI__VI regPB0_RX_GLB_CTRL_REG8__CI__VI; -typedef union PB0_RX_GLB_OVRD_REG0__CI__VI regPB0_RX_GLB_OVRD_REG0__CI__VI; -typedef union PB0_RX_GLB_OVRD_REG1__CI__VI regPB0_RX_GLB_OVRD_REG1__CI__VI; -typedef union PB0_RX_GLB_SCI_STAT_OVRD_REG0__CI regPB0_RX_GLB_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_GLB_SCI_STAT_OVRD_REG0__VI regPB0_RX_GLB_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE0_CTRL_REG0__CI__VI regPB0_RX_LANE0_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE0_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE0_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE10_CTRL_REG0__CI__VI regPB0_RX_LANE10_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE10_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE10_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE11_CTRL_REG0__CI__VI regPB0_RX_LANE11_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE11_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE11_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE12_CTRL_REG0__CI__VI regPB0_RX_LANE12_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE12_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE12_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE13_CTRL_REG0__CI__VI regPB0_RX_LANE13_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE13_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE13_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE14_CTRL_REG0__CI__VI regPB0_RX_LANE14_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE14_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE14_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE15_CTRL_REG0__CI__VI regPB0_RX_LANE15_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE15_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE15_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE1_CTRL_REG0__CI__VI regPB0_RX_LANE1_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE1_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE1_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE2_CTRL_REG0__CI__VI regPB0_RX_LANE2_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE2_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE2_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE3_CTRL_REG0__CI__VI regPB0_RX_LANE3_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE3_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE3_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE4_CTRL_REG0__CI__VI regPB0_RX_LANE4_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE4_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE4_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE5_CTRL_REG0__CI__VI regPB0_RX_LANE5_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE5_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE5_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE6_CTRL_REG0__CI__VI regPB0_RX_LANE6_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE6_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE6_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE7_CTRL_REG0__CI__VI regPB0_RX_LANE7_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE7_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE7_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE8_CTRL_REG0__CI__VI regPB0_RX_LANE8_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE8_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE8_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_RX_LANE9_CTRL_REG0__CI__VI regPB0_RX_LANE9_CTRL_REG0__CI__VI; -typedef union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE9_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE9_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_STRAP_GLB_REG0__CI__VI regPB0_STRAP_GLB_REG0__CI__VI; -typedef union PB0_STRAP_PIN_REG0__CI__VI regPB0_STRAP_PIN_REG0__CI__VI; -typedef union PB0_STRAP_PLL_REG0__CI__VI regPB0_STRAP_PLL_REG0__CI__VI; -typedef union PB0_STRAP_RX_REG0__CI__VI regPB0_STRAP_RX_REG0__CI__VI; -typedef union PB0_STRAP_RX_REG1__CI__VI regPB0_STRAP_RX_REG1__CI__VI; -typedef union PB0_STRAP_TX_REG0__CI__VI regPB0_STRAP_TX_REG0__CI__VI; -typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI - regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI; -typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI - regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI; -typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI - regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI; -typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI - regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI; -typedef union PB0_TX_GLB_CTRL_REG0__CI regPB0_TX_GLB_CTRL_REG0__CI; -typedef union PB0_TX_GLB_CTRL_REG0__VI regPB0_TX_GLB_CTRL_REG0__VI; -typedef union PB0_TX_GLB_LANE_SKEW_CTRL__CI__VI regPB0_TX_GLB_LANE_SKEW_CTRL__CI__VI; -typedef union PB0_TX_GLB_OVRD_REG0__CI__VI regPB0_TX_GLB_OVRD_REG0__CI__VI; -typedef union PB0_TX_GLB_OVRD_REG1__CI__VI regPB0_TX_GLB_OVRD_REG1__CI__VI; -typedef union PB0_TX_GLB_OVRD_REG2__CI__VI regPB0_TX_GLB_OVRD_REG2__CI__VI; -typedef union PB0_TX_GLB_OVRD_REG3__CI__VI regPB0_TX_GLB_OVRD_REG3__CI__VI; -typedef union PB0_TX_GLB_OVRD_REG4__CI__VI regPB0_TX_GLB_OVRD_REG4__CI__VI; -typedef union PB0_TX_GLB_SCI_STAT_OVRD_REG0__CI regPB0_TX_GLB_SCI_STAT_OVRD_REG0__CI; -typedef union PB0_TX_GLB_SCI_STAT_OVRD_REG0__VI regPB0_TX_GLB_SCI_STAT_OVRD_REG0__VI; -typedef union PB0_TX_LANE0_CTRL_REG0__CI__VI regPB0_TX_LANE0_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE0_OVRD_REG0__CI__VI regPB0_TX_LANE0_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE10_CTRL_REG0__CI__VI regPB0_TX_LANE10_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE10_OVRD_REG0__CI__VI regPB0_TX_LANE10_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE11_CTRL_REG0__CI__VI regPB0_TX_LANE11_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE11_OVRD_REG0__CI__VI regPB0_TX_LANE11_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE12_CTRL_REG0__CI__VI regPB0_TX_LANE12_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE12_OVRD_REG0__CI__VI regPB0_TX_LANE12_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE13_CTRL_REG0__CI__VI regPB0_TX_LANE13_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE13_OVRD_REG0__CI__VI regPB0_TX_LANE13_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE14_CTRL_REG0__CI__VI regPB0_TX_LANE14_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE14_OVRD_REG0__CI__VI regPB0_TX_LANE14_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE15_CTRL_REG0__CI__VI regPB0_TX_LANE15_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE15_OVRD_REG0__CI__VI regPB0_TX_LANE15_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE1_CTRL_REG0__CI__VI regPB0_TX_LANE1_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE1_OVRD_REG0__CI__VI regPB0_TX_LANE1_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE2_CTRL_REG0__CI__VI regPB0_TX_LANE2_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE2_OVRD_REG0__CI__VI regPB0_TX_LANE2_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE3_CTRL_REG0__CI__VI regPB0_TX_LANE3_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE3_OVRD_REG0__CI__VI regPB0_TX_LANE3_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE4_CTRL_REG0__CI__VI regPB0_TX_LANE4_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE4_OVRD_REG0__CI__VI regPB0_TX_LANE4_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE5_CTRL_REG0__CI__VI regPB0_TX_LANE5_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE5_OVRD_REG0__CI__VI regPB0_TX_LANE5_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE6_CTRL_REG0__CI__VI regPB0_TX_LANE6_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE6_OVRD_REG0__CI__VI regPB0_TX_LANE6_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE7_CTRL_REG0__CI__VI regPB0_TX_LANE7_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE7_OVRD_REG0__CI__VI regPB0_TX_LANE7_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE8_CTRL_REG0__CI__VI regPB0_TX_LANE8_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE8_OVRD_REG0__CI__VI regPB0_TX_LANE8_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE9_CTRL_REG0__CI__VI regPB0_TX_LANE9_CTRL_REG0__CI__VI; -typedef union PB0_TX_LANE9_OVRD_REG0__CI__VI regPB0_TX_LANE9_OVRD_REG0__CI__VI; -typedef union PB0_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_DFT_DEBUG_CTRL_REG0__CI__VI regPB1_DFT_DEBUG_CTRL_REG0__CI__VI; -typedef union PB1_DFT_JIT_INJ_REG0__CI__VI regPB1_DFT_JIT_INJ_REG0__CI__VI; -typedef union PB1_DFT_JIT_INJ_REG1__CI__VI regPB1_DFT_JIT_INJ_REG1__CI__VI; -typedef union PB1_DFT_JIT_INJ_REG2__CI__VI regPB1_DFT_JIT_INJ_REG2__CI__VI; -typedef union PB1_DFT_JIT_INJ_STAT_REG0__CI__VI regPB1_DFT_JIT_INJ_STAT_REG0__CI__VI; -typedef union PB1_GLB_CTRL_REG0__CI__VI regPB1_GLB_CTRL_REG0__CI__VI; -typedef union PB1_GLB_CTRL_REG1__CI__VI regPB1_GLB_CTRL_REG1__CI__VI; -typedef union PB1_GLB_CTRL_REG2__CI__VI regPB1_GLB_CTRL_REG2__CI__VI; -typedef union PB1_GLB_CTRL_REG3__CI__VI regPB1_GLB_CTRL_REG3__CI__VI; -typedef union PB1_GLB_CTRL_REG4__CI__VI regPB1_GLB_CTRL_REG4__CI__VI; -typedef union PB1_GLB_CTRL_REG5__CI__VI regPB1_GLB_CTRL_REG5__CI__VI; -typedef union PB1_GLB_OVRD_REG0__CI__VI regPB1_GLB_OVRD_REG0__CI__VI; -typedef union PB1_GLB_OVRD_REG1__CI__VI regPB1_GLB_OVRD_REG1__CI__VI; -typedef union PB1_GLB_OVRD_REG2__CI__VI regPB1_GLB_OVRD_REG2__CI__VI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG0__CI regPB1_GLB_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG0__VI regPB1_GLB_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG1__CI regPB1_GLB_SCI_STAT_OVRD_REG1__CI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG1__VI regPB1_GLB_SCI_STAT_OVRD_REG1__VI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG2__CI regPB1_GLB_SCI_STAT_OVRD_REG2__CI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG2__VI regPB1_GLB_SCI_STAT_OVRD_REG2__VI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG3__CI regPB1_GLB_SCI_STAT_OVRD_REG3__CI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG3__VI regPB1_GLB_SCI_STAT_OVRD_REG3__VI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG4__CI regPB1_GLB_SCI_STAT_OVRD_REG4__CI; -typedef union PB1_GLB_SCI_STAT_OVRD_REG4__VI regPB1_GLB_SCI_STAT_OVRD_REG4__VI; -typedef union PB1_HW_DEBUG__CI regPB1_HW_DEBUG__CI; -typedef union PB1_HW_DEBUG__VI regPB1_HW_DEBUG__VI; -typedef union PB1_PIF_CNTL2__CI regPB1_PIF_CNTL2__CI; -typedef union PB1_PIF_CNTL__CI regPB1_PIF_CNTL__CI; -typedef union PB1_PIF_HW_DEBUG__CI regPB1_PIF_HW_DEBUG__CI; -typedef union PB1_PIF_HW_DEBUG__VI regPB1_PIF_HW_DEBUG__VI; -typedef union PB1_PIF_PAIRING__CI regPB1_PIF_PAIRING__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_0__CI regPB1_PIF_PDNB_OVERRIDE_0__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_10__CI regPB1_PIF_PDNB_OVERRIDE_10__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_11__CI regPB1_PIF_PDNB_OVERRIDE_11__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_12__CI regPB1_PIF_PDNB_OVERRIDE_12__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_13__CI regPB1_PIF_PDNB_OVERRIDE_13__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_14__CI regPB1_PIF_PDNB_OVERRIDE_14__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_15__CI regPB1_PIF_PDNB_OVERRIDE_15__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_1__CI regPB1_PIF_PDNB_OVERRIDE_1__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_2__CI regPB1_PIF_PDNB_OVERRIDE_2__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_3__CI regPB1_PIF_PDNB_OVERRIDE_3__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_4__CI regPB1_PIF_PDNB_OVERRIDE_4__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_5__CI regPB1_PIF_PDNB_OVERRIDE_5__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_6__CI regPB1_PIF_PDNB_OVERRIDE_6__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_7__CI regPB1_PIF_PDNB_OVERRIDE_7__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_8__CI regPB1_PIF_PDNB_OVERRIDE_8__CI; -typedef union PB1_PIF_PDNB_OVERRIDE_9__CI regPB1_PIF_PDNB_OVERRIDE_9__CI; -typedef union PB1_PIF_PWRDOWN_0__CI regPB1_PIF_PWRDOWN_0__CI; -typedef union PB1_PIF_PWRDOWN_1__CI regPB1_PIF_PWRDOWN_1__CI; -typedef union PB1_PIF_PWRDOWN_2__CI regPB1_PIF_PWRDOWN_2__CI; -typedef union PB1_PIF_PWRDOWN_3__CI regPB1_PIF_PWRDOWN_3__CI; -typedef union PB1_PIF_SCRATCH__CI__VI regPB1_PIF_SCRATCH__CI__VI; -typedef union PB1_PIF_SC_CTL__CI regPB1_PIF_SC_CTL__CI; -typedef union PB1_PIF_SEQ_STATUS_0__CI regPB1_PIF_SEQ_STATUS_0__CI; -typedef union PB1_PIF_SEQ_STATUS_10__CI regPB1_PIF_SEQ_STATUS_10__CI; -typedef union PB1_PIF_SEQ_STATUS_11__CI regPB1_PIF_SEQ_STATUS_11__CI; -typedef union PB1_PIF_SEQ_STATUS_12__CI regPB1_PIF_SEQ_STATUS_12__CI; -typedef union PB1_PIF_SEQ_STATUS_13__CI regPB1_PIF_SEQ_STATUS_13__CI; -typedef union PB1_PIF_SEQ_STATUS_14__CI regPB1_PIF_SEQ_STATUS_14__CI; -typedef union PB1_PIF_SEQ_STATUS_15__CI regPB1_PIF_SEQ_STATUS_15__CI; -typedef union PB1_PIF_SEQ_STATUS_1__CI regPB1_PIF_SEQ_STATUS_1__CI; -typedef union PB1_PIF_SEQ_STATUS_2__CI regPB1_PIF_SEQ_STATUS_2__CI; -typedef union PB1_PIF_SEQ_STATUS_3__CI regPB1_PIF_SEQ_STATUS_3__CI; -typedef union PB1_PIF_SEQ_STATUS_4__CI regPB1_PIF_SEQ_STATUS_4__CI; -typedef union PB1_PIF_SEQ_STATUS_5__CI regPB1_PIF_SEQ_STATUS_5__CI; -typedef union PB1_PIF_SEQ_STATUS_6__CI regPB1_PIF_SEQ_STATUS_6__CI; -typedef union PB1_PIF_SEQ_STATUS_7__CI regPB1_PIF_SEQ_STATUS_7__CI; -typedef union PB1_PIF_SEQ_STATUS_8__CI regPB1_PIF_SEQ_STATUS_8__CI; -typedef union PB1_PIF_SEQ_STATUS_9__CI regPB1_PIF_SEQ_STATUS_9__CI; -typedef union PB1_PIF_TXPHYSTATUS__CI regPB1_PIF_TXPHYSTATUS__CI; -typedef union PB1_PLL_LC0_CTRL_REG0__CI__VI regPB1_PLL_LC0_CTRL_REG0__CI__VI; -typedef union PB1_PLL_LC0_OVRD_REG0__CI__VI regPB1_PLL_LC0_OVRD_REG0__CI__VI; -typedef union PB1_PLL_LC0_OVRD_REG1__CI__VI regPB1_PLL_LC0_OVRD_REG1__CI__VI; -typedef union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC0_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC0_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC1_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC1_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC2_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC2_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC3_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC3_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_RO0_CTRL_REG0__CI__VI regPB1_PLL_RO0_CTRL_REG0__CI__VI; -typedef union PB1_PLL_RO0_OVRD_REG0__CI__VI regPB1_PLL_RO0_OVRD_REG0__CI__VI; -typedef union PB1_PLL_RO0_OVRD_REG1__CI__VI regPB1_PLL_RO0_OVRD_REG1__CI__VI; -typedef union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO0_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO0_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO1_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO1_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO2_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO2_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO3_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO3_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_PLL_RO_GLB_CTRL_REG0__CI regPB1_PLL_RO_GLB_CTRL_REG0__CI; -typedef union PB1_PLL_RO_GLB_CTRL_REG0__VI regPB1_PLL_RO_GLB_CTRL_REG0__VI; -typedef union PB1_PLL_RO_GLB_OVRD_REG0__CI__VI regPB1_PLL_RO_GLB_OVRD_REG0__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG0__CI__VI regPB1_RX_GLB_CTRL_REG0__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG1__CI__VI regPB1_RX_GLB_CTRL_REG1__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG2__CI__VI regPB1_RX_GLB_CTRL_REG2__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG3__CI__VI regPB1_RX_GLB_CTRL_REG3__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG4__CI__VI regPB1_RX_GLB_CTRL_REG4__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG5__CI__VI regPB1_RX_GLB_CTRL_REG5__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG6__CI__VI regPB1_RX_GLB_CTRL_REG6__CI__VI; -typedef union PB1_RX_GLB_CTRL_REG7__CI regPB1_RX_GLB_CTRL_REG7__CI; -typedef union PB1_RX_GLB_CTRL_REG7__VI regPB1_RX_GLB_CTRL_REG7__VI; -typedef union PB1_RX_GLB_CTRL_REG8__CI__VI regPB1_RX_GLB_CTRL_REG8__CI__VI; -typedef union PB1_RX_GLB_OVRD_REG0__CI__VI regPB1_RX_GLB_OVRD_REG0__CI__VI; -typedef union PB1_RX_GLB_OVRD_REG1__CI__VI regPB1_RX_GLB_OVRD_REG1__CI__VI; -typedef union PB1_RX_GLB_SCI_STAT_OVRD_REG0__CI regPB1_RX_GLB_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_GLB_SCI_STAT_OVRD_REG0__VI regPB1_RX_GLB_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE0_CTRL_REG0__CI__VI regPB1_RX_LANE0_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE0_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE0_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE10_CTRL_REG0__CI__VI regPB1_RX_LANE10_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE10_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE10_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE11_CTRL_REG0__CI__VI regPB1_RX_LANE11_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE11_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE11_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE12_CTRL_REG0__CI__VI regPB1_RX_LANE12_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE12_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE12_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE13_CTRL_REG0__CI__VI regPB1_RX_LANE13_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE13_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE13_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE14_CTRL_REG0__CI__VI regPB1_RX_LANE14_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE14_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE14_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE15_CTRL_REG0__CI__VI regPB1_RX_LANE15_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE15_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE15_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE1_CTRL_REG0__CI__VI regPB1_RX_LANE1_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE1_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE1_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE2_CTRL_REG0__CI__VI regPB1_RX_LANE2_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE2_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE2_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE3_CTRL_REG0__CI__VI regPB1_RX_LANE3_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE3_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE3_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE4_CTRL_REG0__CI__VI regPB1_RX_LANE4_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE4_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE4_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE5_CTRL_REG0__CI__VI regPB1_RX_LANE5_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE5_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE5_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE6_CTRL_REG0__CI__VI regPB1_RX_LANE6_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE6_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE6_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE7_CTRL_REG0__CI__VI regPB1_RX_LANE7_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE7_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE7_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE8_CTRL_REG0__CI__VI regPB1_RX_LANE8_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE8_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE8_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_RX_LANE9_CTRL_REG0__CI__VI regPB1_RX_LANE9_CTRL_REG0__CI__VI; -typedef union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE9_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE9_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_STRAP_GLB_REG0__CI__VI regPB1_STRAP_GLB_REG0__CI__VI; -typedef union PB1_STRAP_PIN_REG0__CI__VI regPB1_STRAP_PIN_REG0__CI__VI; -typedef union PB1_STRAP_PLL_REG0__CI__VI regPB1_STRAP_PLL_REG0__CI__VI; -typedef union PB1_STRAP_RX_REG0__CI__VI regPB1_STRAP_RX_REG0__CI__VI; -typedef union PB1_STRAP_RX_REG1__CI__VI regPB1_STRAP_RX_REG1__CI__VI; -typedef union PB1_STRAP_TX_REG0__CI__VI regPB1_STRAP_TX_REG0__CI__VI; -typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI - regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI; -typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI - regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI; -typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI - regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI; -typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI - regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI; -typedef union PB1_TX_GLB_CTRL_REG0__CI regPB1_TX_GLB_CTRL_REG0__CI; -typedef union PB1_TX_GLB_CTRL_REG0__VI regPB1_TX_GLB_CTRL_REG0__VI; -typedef union PB1_TX_GLB_LANE_SKEW_CTRL__CI__VI regPB1_TX_GLB_LANE_SKEW_CTRL__CI__VI; -typedef union PB1_TX_GLB_OVRD_REG0__CI__VI regPB1_TX_GLB_OVRD_REG0__CI__VI; -typedef union PB1_TX_GLB_OVRD_REG1__CI__VI regPB1_TX_GLB_OVRD_REG1__CI__VI; -typedef union PB1_TX_GLB_OVRD_REG2__CI__VI regPB1_TX_GLB_OVRD_REG2__CI__VI; -typedef union PB1_TX_GLB_OVRD_REG3__CI__VI regPB1_TX_GLB_OVRD_REG3__CI__VI; -typedef union PB1_TX_GLB_OVRD_REG4__CI__VI regPB1_TX_GLB_OVRD_REG4__CI__VI; -typedef union PB1_TX_GLB_SCI_STAT_OVRD_REG0__CI regPB1_TX_GLB_SCI_STAT_OVRD_REG0__CI; -typedef union PB1_TX_GLB_SCI_STAT_OVRD_REG0__VI regPB1_TX_GLB_SCI_STAT_OVRD_REG0__VI; -typedef union PB1_TX_LANE0_CTRL_REG0__CI__VI regPB1_TX_LANE0_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE0_OVRD_REG0__CI__VI regPB1_TX_LANE0_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE10_CTRL_REG0__CI__VI regPB1_TX_LANE10_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE10_OVRD_REG0__CI__VI regPB1_TX_LANE10_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE11_CTRL_REG0__CI__VI regPB1_TX_LANE11_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE11_OVRD_REG0__CI__VI regPB1_TX_LANE11_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE12_CTRL_REG0__CI__VI regPB1_TX_LANE12_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE12_OVRD_REG0__CI__VI regPB1_TX_LANE12_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE13_CTRL_REG0__CI__VI regPB1_TX_LANE13_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE13_OVRD_REG0__CI__VI regPB1_TX_LANE13_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE14_CTRL_REG0__CI__VI regPB1_TX_LANE14_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE14_OVRD_REG0__CI__VI regPB1_TX_LANE14_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE15_CTRL_REG0__CI__VI regPB1_TX_LANE15_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE15_OVRD_REG0__CI__VI regPB1_TX_LANE15_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE1_CTRL_REG0__CI__VI regPB1_TX_LANE1_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE1_OVRD_REG0__CI__VI regPB1_TX_LANE1_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE2_CTRL_REG0__CI__VI regPB1_TX_LANE2_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE2_OVRD_REG0__CI__VI regPB1_TX_LANE2_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE3_CTRL_REG0__CI__VI regPB1_TX_LANE3_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE3_OVRD_REG0__CI__VI regPB1_TX_LANE3_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE4_CTRL_REG0__CI__VI regPB1_TX_LANE4_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE4_OVRD_REG0__CI__VI regPB1_TX_LANE4_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE5_CTRL_REG0__CI__VI regPB1_TX_LANE5_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE5_OVRD_REG0__CI__VI regPB1_TX_LANE5_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE6_CTRL_REG0__CI__VI regPB1_TX_LANE6_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE6_OVRD_REG0__CI__VI regPB1_TX_LANE6_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE7_CTRL_REG0__CI__VI regPB1_TX_LANE7_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE7_OVRD_REG0__CI__VI regPB1_TX_LANE7_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE8_CTRL_REG0__CI__VI regPB1_TX_LANE8_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE8_OVRD_REG0__CI__VI regPB1_TX_LANE8_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE9_CTRL_REG0__CI__VI regPB1_TX_LANE9_CTRL_REG0__CI__VI; -typedef union PB1_TX_LANE9_OVRD_REG0__CI__VI regPB1_TX_LANE9_OVRD_REG0__CI__VI; -typedef union PB1_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI; -typedef union PCIEP_BCH_ECC_CNTL__CI__VI regPCIEP_BCH_ECC_CNTL__CI__VI; -typedef union PCIEP_HW_DEBUG regPCIEP_HW_DEBUG; -typedef union PCIEP_PORT_CNTL__CI__VI regPCIEP_PORT_CNTL__CI__VI; -typedef union PCIEP_PORT_CNTL__SI regPCIEP_PORT_CNTL__SI; -typedef union PCIEP_RESERVED regPCIEP_RESERVED; -typedef union PCIEP_SCRATCH regPCIEP_SCRATCH; -typedef union PCIEP_STRAP_LC regPCIEP_STRAP_LC; -typedef union PCIEP_STRAP_MISC__CI__VI regPCIEP_STRAP_MISC__CI__VI; -typedef union PCIEP_STRAP_MISC__SI regPCIEP_STRAP_MISC__SI; -typedef union PCIE_ACS_CAP__CI__VI regPCIE_ACS_CAP__CI__VI; -typedef union PCIE_ACS_CNTL__CI__VI regPCIE_ACS_CNTL__CI__VI; -typedef union PCIE_ACS_ENH_CAP_LIST__CI__VI regPCIE_ACS_ENH_CAP_LIST__CI__VI; -typedef union PCIE_ADV_ERR_CAP_CNTL__SI__CI regPCIE_ADV_ERR_CAP_CNTL__SI__CI; -typedef union PCIE_ADV_ERR_CAP_CNTL__VI regPCIE_ADV_ERR_CAP_CNTL__VI; -typedef union PCIE_ADV_ERR_RPT_ENH_CAP_LIST regPCIE_ADV_ERR_RPT_ENH_CAP_LIST; -typedef union PCIE_ATS_CAP__CI regPCIE_ATS_CAP__CI; -typedef union PCIE_ATS_CAP__VI regPCIE_ATS_CAP__VI; -typedef union PCIE_ATS_CNTL__CI__VI regPCIE_ATS_CNTL__CI__VI; -typedef union PCIE_ATS_ENH_CAP_LIST__CI__VI regPCIE_ATS_ENH_CAP_LIST__CI__VI; -typedef union PCIE_BAR1_CAP__CI__VI regPCIE_BAR1_CAP__CI__VI; -typedef union PCIE_BAR1_CNTL__CI__VI regPCIE_BAR1_CNTL__CI__VI; -typedef union PCIE_BAR2_CAP__CI__VI regPCIE_BAR2_CAP__CI__VI; -typedef union PCIE_BAR2_CNTL__CI__VI regPCIE_BAR2_CNTL__CI__VI; -typedef union PCIE_BAR3_CAP__CI__VI regPCIE_BAR3_CAP__CI__VI; -typedef union PCIE_BAR3_CNTL__CI__VI regPCIE_BAR3_CNTL__CI__VI; -typedef union PCIE_BAR4_CAP__CI__VI regPCIE_BAR4_CAP__CI__VI; -typedef union PCIE_BAR4_CNTL__CI__VI regPCIE_BAR4_CNTL__CI__VI; -typedef union PCIE_BAR5_CAP__CI__VI regPCIE_BAR5_CAP__CI__VI; -typedef union PCIE_BAR5_CNTL__CI__VI regPCIE_BAR5_CNTL__CI__VI; -typedef union PCIE_BAR6_CAP__CI__VI regPCIE_BAR6_CAP__CI__VI; -typedef union PCIE_BAR6_CNTL__CI__VI regPCIE_BAR6_CNTL__CI__VI; -typedef union PCIE_BAR_ENH_CAP_LIST__CI__VI regPCIE_BAR_ENH_CAP_LIST__CI__VI; -typedef union PCIE_BUS_CNTL regPCIE_BUS_CNTL; -typedef union PCIE_B_P90_CNTL__SI regPCIE_B_P90_CNTL__SI; -typedef union PCIE_CAC_DEVICE_CORRELATION__SI regPCIE_CAC_DEVICE_CORRELATION__SI; -typedef union PCIE_CAC_ENH_CAP_LIST__SI regPCIE_CAC_ENH_CAP_LIST__SI; -typedef union PCIE_CAP regPCIE_CAP; -typedef union PCIE_CAP_LIST regPCIE_CAP_LIST; -typedef union PCIE_CFG_CNTL__CI__VI regPCIE_CFG_CNTL__CI__VI; -typedef union PCIE_CFG_CNTL__SI regPCIE_CFG_CNTL__SI; -typedef union PCIE_CI_CNTL__CI__VI regPCIE_CI_CNTL__CI__VI; -typedef union PCIE_CI_CNTL__SI regPCIE_CI_CNTL__SI; -typedef union PCIE_CI_MST_C_RTR_TIMEOUT_CNTL__SI regPCIE_CI_MST_C_RTR_TIMEOUT_CNTL__SI; -typedef union PCIE_CI_MST_R_RTR_TIMEOUT_CNTL__SI regPCIE_CI_MST_R_RTR_TIMEOUT_CNTL__SI; -typedef union PCIE_CI_SLV_R_RTR_TIMEOUT_CNTL__SI regPCIE_CI_SLV_R_RTR_TIMEOUT_CNTL__SI; -typedef union PCIE_CNTL2 regPCIE_CNTL2; -typedef union PCIE_CNTL__CI regPCIE_CNTL__CI; -typedef union PCIE_CNTL__VI regPCIE_CNTL__VI; -typedef union PCIE_CNTL__SI regPCIE_CNTL__SI; -typedef union PCIE_CONFIG_CNTL regPCIE_CONFIG_CNTL; -typedef union PCIE_CORR_ERR_MASK regPCIE_CORR_ERR_MASK; -typedef union PCIE_CORR_ERR_STATUS regPCIE_CORR_ERR_STATUS; -typedef union PCIE_DATA regPCIE_DATA; -typedef union PCIE_DATA_2__CI__VI regPCIE_DATA_2__CI__VI; -typedef union PCIE_DEBUG_CNTL regPCIE_DEBUG_CNTL; -typedef union PCIE_DEV_SERIAL_NUM_DW1 regPCIE_DEV_SERIAL_NUM_DW1; -typedef union PCIE_DEV_SERIAL_NUM_DW2 regPCIE_DEV_SERIAL_NUM_DW2; -typedef union PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST regPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST; -typedef union PCIE_DPA_CAP__CI__VI regPCIE_DPA_CAP__CI__VI; -typedef union PCIE_DPA_CNTL__CI__VI regPCIE_DPA_CNTL__CI__VI; -typedef union PCIE_DPA_ENH_CAP_LIST__CI__VI regPCIE_DPA_ENH_CAP_LIST__CI__VI; -typedef union PCIE_DPA_LATENCY_INDICATOR__CI__VI regPCIE_DPA_LATENCY_INDICATOR__CI__VI; -typedef union PCIE_DPA_STATUS__CI__VI regPCIE_DPA_STATUS__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI; -typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI; -typedef union PCIE_ERR_CNTL__CI__VI regPCIE_ERR_CNTL__CI__VI; -typedef union PCIE_ERR_CNTL__SI regPCIE_ERR_CNTL__SI; -typedef union PCIE_F0_DPA_CAP__CI__VI regPCIE_F0_DPA_CAP__CI__VI; -typedef union PCIE_F0_DPA_CNTL__CI__VI regPCIE_F0_DPA_CNTL__CI__VI; -typedef union PCIE_F0_DPA_LATENCY_INDICATOR__CI__VI regPCIE_F0_DPA_LATENCY_INDICATOR__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI; -typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI; -typedef union PCIE_FC_CPL regPCIE_FC_CPL; -typedef union PCIE_FC_NP regPCIE_FC_NP; -typedef union PCIE_FC_P regPCIE_FC_P; -typedef union PCIE_HDR_LOG0 regPCIE_HDR_LOG0; -typedef union PCIE_HDR_LOG1 regPCIE_HDR_LOG1; -typedef union PCIE_HDR_LOG2 regPCIE_HDR_LOG2; -typedef union PCIE_HDR_LOG3 regPCIE_HDR_LOG3; -typedef union PCIE_HW_DEBUG regPCIE_HW_DEBUG; -typedef union PCIE_I2C_DEBUG_BUS regPCIE_I2C_DEBUG_BUS; -typedef union PCIE_I2C_REG_ADDR_EXPAND regPCIE_I2C_REG_ADDR_EXPAND; -typedef union PCIE_I2C_REG_DATA regPCIE_I2C_REG_DATA; -typedef union PCIE_INDEX_2__CI__VI regPCIE_INDEX_2__CI__VI; -typedef union PCIE_INDEX__CI__VI regPCIE_INDEX__CI__VI; -typedef union PCIE_INDEX__SI regPCIE_INDEX__SI; -typedef union PCIE_INT_CNTL regPCIE_INT_CNTL; -typedef union PCIE_INT_STATUS regPCIE_INT_STATUS; -typedef union PCIE_LANE_0_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_10_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_11_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_12_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_13_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_14_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_15_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_1_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_2_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_3_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_4_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_5_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_6_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_7_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_8_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_9_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI; -typedef union PCIE_LANE_ERROR_STATUS__CI__VI regPCIE_LANE_ERROR_STATUS__CI__VI; -typedef union PCIE_LC_BW_CHANGE_CNTL regPCIE_LC_BW_CHANGE_CNTL; -typedef union PCIE_LC_CDR_CNTL regPCIE_LC_CDR_CNTL; -typedef union PCIE_LC_CNTL regPCIE_LC_CNTL; -typedef union PCIE_LC_CNTL2__CI__VI regPCIE_LC_CNTL2__CI__VI; -typedef union PCIE_LC_CNTL2__SI regPCIE_LC_CNTL2__SI; -typedef union PCIE_LC_CNTL3 regPCIE_LC_CNTL3; -typedef union PCIE_LC_CNTL4__CI regPCIE_LC_CNTL4__CI; -typedef union PCIE_LC_CNTL4__VI regPCIE_LC_CNTL4__VI; -typedef union PCIE_LC_CNTL5__CI__VI regPCIE_LC_CNTL5__CI__VI; -typedef union PCIE_LC_FORCE_COEFF__CI__VI regPCIE_LC_FORCE_COEFF__CI__VI; -typedef union PCIE_LC_LANE_CNTL regPCIE_LC_LANE_CNTL; -typedef union PCIE_LC_LINK_WIDTH_CNTL regPCIE_LC_LINK_WIDTH_CNTL; -typedef union PCIE_LC_N_FTS_CNTL regPCIE_LC_N_FTS_CNTL; -typedef union PCIE_LC_SPEED_CNTL__CI__VI regPCIE_LC_SPEED_CNTL__CI__VI; -typedef union PCIE_LC_SPEED_CNTL__SI regPCIE_LC_SPEED_CNTL__SI; -typedef union PCIE_LC_STATE0 regPCIE_LC_STATE0; -typedef union PCIE_LC_STATE1 regPCIE_LC_STATE1; -typedef union PCIE_LC_STATE10 regPCIE_LC_STATE10; -typedef union PCIE_LC_STATE11 regPCIE_LC_STATE11; -typedef union PCIE_LC_STATE2 regPCIE_LC_STATE2; -typedef union PCIE_LC_STATE3 regPCIE_LC_STATE3; -typedef union PCIE_LC_STATE4 regPCIE_LC_STATE4; -typedef union PCIE_LC_STATE5 regPCIE_LC_STATE5; -typedef union PCIE_LC_STATE6 regPCIE_LC_STATE6; -typedef union PCIE_LC_STATE7 regPCIE_LC_STATE7; -typedef union PCIE_LC_STATE8 regPCIE_LC_STATE8; -typedef union PCIE_LC_STATE9 regPCIE_LC_STATE9; -typedef union PCIE_LC_STATUS1 regPCIE_LC_STATUS1; -typedef union PCIE_LC_STATUS2 regPCIE_LC_STATUS2; -typedef union PCIE_LC_TRAINING_CNTL__CI regPCIE_LC_TRAINING_CNTL__CI; -typedef union PCIE_LC_TRAINING_CNTL__VI regPCIE_LC_TRAINING_CNTL__VI; -typedef union PCIE_LC_TRAINING_CNTL__SI regPCIE_LC_TRAINING_CNTL__SI; -typedef union PCIE_LINK_CNTL3__CI__VI regPCIE_LINK_CNTL3__CI__VI; -typedef union PCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI regPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI; -typedef union PCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI regPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI; -typedef union PCIE_P90RX_PRBS10_CNTL__SI regPCIE_P90RX_PRBS10_CNTL__SI; -typedef union PCIE_P90_BRX_PRBS10_ER__SI regPCIE_P90_BRX_PRBS10_ER__SI; -typedef union PCIE_PAGE_REQ_CNTL__CI__VI regPCIE_PAGE_REQ_CNTL__CI__VI; -typedef union PCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI regPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI; -typedef union PCIE_PAGE_REQ_STATUS__CI__VI regPCIE_PAGE_REQ_STATUS__CI__VI; -typedef union PCIE_PASID_CAP__CI__VI regPCIE_PASID_CAP__CI__VI; -typedef union PCIE_PASID_CNTL__CI__VI regPCIE_PASID_CNTL__CI__VI; -typedef union PCIE_PASID_ENH_CAP_LIST__CI__VI regPCIE_PASID_ENH_CAP_LIST__CI__VI; -typedef union PCIE_PERF_CNTL_EVENT0_PORT_SEL regPCIE_PERF_CNTL_EVENT0_PORT_SEL; -typedef union PCIE_PERF_CNTL_EVENT1_PORT_SEL regPCIE_PERF_CNTL_EVENT1_PORT_SEL; -typedef union PCIE_PERF_CNTL_MST_C_CLK regPCIE_PERF_CNTL_MST_C_CLK; -typedef union PCIE_PERF_CNTL_MST_R_CLK regPCIE_PERF_CNTL_MST_R_CLK; -typedef union PCIE_PERF_CNTL_SLV_NS_C_CLK regPCIE_PERF_CNTL_SLV_NS_C_CLK; -typedef union PCIE_PERF_CNTL_SLV_R_CLK regPCIE_PERF_CNTL_SLV_R_CLK; -typedef union PCIE_PERF_CNTL_SLV_S_C_CLK regPCIE_PERF_CNTL_SLV_S_C_CLK; -typedef union PCIE_PERF_CNTL_TXCLK regPCIE_PERF_CNTL_TXCLK; -typedef union PCIE_PERF_CNTL_TXCLK2 regPCIE_PERF_CNTL_TXCLK2; -typedef union PCIE_PERF_COUNT0_MST_C_CLK regPCIE_PERF_COUNT0_MST_C_CLK; -typedef union PCIE_PERF_COUNT0_MST_R_CLK regPCIE_PERF_COUNT0_MST_R_CLK; -typedef union PCIE_PERF_COUNT0_SLV_NS_C_CLK regPCIE_PERF_COUNT0_SLV_NS_C_CLK; -typedef union PCIE_PERF_COUNT0_SLV_R_CLK regPCIE_PERF_COUNT0_SLV_R_CLK; -typedef union PCIE_PERF_COUNT0_SLV_S_C_CLK regPCIE_PERF_COUNT0_SLV_S_C_CLK; -typedef union PCIE_PERF_COUNT0_TXCLK regPCIE_PERF_COUNT0_TXCLK; -typedef union PCIE_PERF_COUNT0_TXCLK2 regPCIE_PERF_COUNT0_TXCLK2; -typedef union PCIE_PERF_COUNT1_MST_C_CLK regPCIE_PERF_COUNT1_MST_C_CLK; -typedef union PCIE_PERF_COUNT1_MST_R_CLK regPCIE_PERF_COUNT1_MST_R_CLK; -typedef union PCIE_PERF_COUNT1_SLV_NS_C_CLK regPCIE_PERF_COUNT1_SLV_NS_C_CLK; -typedef union PCIE_PERF_COUNT1_SLV_R_CLK regPCIE_PERF_COUNT1_SLV_R_CLK; -typedef union PCIE_PERF_COUNT1_SLV_S_C_CLK regPCIE_PERF_COUNT1_SLV_S_C_CLK; -typedef union PCIE_PERF_COUNT1_TXCLK regPCIE_PERF_COUNT1_TXCLK; -typedef union PCIE_PERF_COUNT1_TXCLK2 regPCIE_PERF_COUNT1_TXCLK2; -typedef union PCIE_PERF_COUNT_CNTL regPCIE_PERF_COUNT_CNTL; -typedef union PCIE_PERF_LATENCY_CNTL__SI regPCIE_PERF_LATENCY_CNTL__SI; -typedef union PCIE_PERF_LATENCY_COUNTER0__SI regPCIE_PERF_LATENCY_COUNTER0__SI; -typedef union PCIE_PERF_LATENCY_COUNTER1__SI regPCIE_PERF_LATENCY_COUNTER1__SI; -typedef union PCIE_PERF_LATENCY_MAX__SI regPCIE_PERF_LATENCY_MAX__SI; -typedef union PCIE_PERF_LATENCY_REQ_ID__SI regPCIE_PERF_LATENCY_REQ_ID__SI; -typedef union PCIE_PERF_LATENCY_TAG__SI regPCIE_PERF_LATENCY_TAG__SI; -typedef union PCIE_PERF_LATENCY_THRESHOLD__SI regPCIE_PERF_LATENCY_THRESHOLD__SI; -typedef union PCIE_PERF_LATENCY_TIMER_HI__SI regPCIE_PERF_LATENCY_TIMER_HI__SI; -typedef union PCIE_PERF_LATENCY_TIMER_LO__SI regPCIE_PERF_LATENCY_TIMER_LO__SI; -typedef union PCIE_PERF_MAS_ACC_END_LO__SI regPCIE_PERF_MAS_ACC_END_LO__SI; -typedef union PCIE_PERF_MAS_ACC_START_END_HI__SI regPCIE_PERF_MAS_ACC_START_END_HI__SI; -typedef union PCIE_PERF_MAS_ACC_START_LO__SI regPCIE_PERF_MAS_ACC_START_LO__SI; -typedef union PCIE_PERF_SLV_ACC_HI__SI regPCIE_PERF_SLV_ACC_HI__SI; -typedef union PCIE_PERF_SLV_ACC_LO__SI regPCIE_PERF_SLV_ACC_LO__SI; -typedef union PCIE_PI_RCVL0S_FTS_DET__SI regPCIE_PI_RCVL0S_FTS_DET__SI; -typedef union PCIE_PORT_DATA__SI regPCIE_PORT_DATA__SI; -typedef union PCIE_PORT_INDEX__SI regPCIE_PORT_INDEX__SI; -typedef union PCIE_PORT_VC_CAP_REG1 regPCIE_PORT_VC_CAP_REG1; -typedef union PCIE_PORT_VC_CAP_REG2 regPCIE_PORT_VC_CAP_REG2; -typedef union PCIE_PORT_VC_CNTL regPCIE_PORT_VC_CNTL; -typedef union PCIE_PORT_VC_STATUS regPCIE_PORT_VC_STATUS; -typedef union PCIE_PRBS_CLR regPCIE_PRBS_CLR; -typedef union PCIE_PRBS_ERRCNT_0 regPCIE_PRBS_ERRCNT_0; -typedef union PCIE_PRBS_ERRCNT_1 regPCIE_PRBS_ERRCNT_1; -typedef union PCIE_PRBS_ERRCNT_10 regPCIE_PRBS_ERRCNT_10; -typedef union PCIE_PRBS_ERRCNT_11 regPCIE_PRBS_ERRCNT_11; -typedef union PCIE_PRBS_ERRCNT_12 regPCIE_PRBS_ERRCNT_12; -typedef union PCIE_PRBS_ERRCNT_13 regPCIE_PRBS_ERRCNT_13; -typedef union PCIE_PRBS_ERRCNT_14 regPCIE_PRBS_ERRCNT_14; -typedef union PCIE_PRBS_ERRCNT_15 regPCIE_PRBS_ERRCNT_15; -typedef union PCIE_PRBS_ERRCNT_2 regPCIE_PRBS_ERRCNT_2; -typedef union PCIE_PRBS_ERRCNT_3 regPCIE_PRBS_ERRCNT_3; -typedef union PCIE_PRBS_ERRCNT_4 regPCIE_PRBS_ERRCNT_4; -typedef union PCIE_PRBS_ERRCNT_5 regPCIE_PRBS_ERRCNT_5; -typedef union PCIE_PRBS_ERRCNT_6 regPCIE_PRBS_ERRCNT_6; -typedef union PCIE_PRBS_ERRCNT_7 regPCIE_PRBS_ERRCNT_7; -typedef union PCIE_PRBS_ERRCNT_8 regPCIE_PRBS_ERRCNT_8; -typedef union PCIE_PRBS_ERRCNT_9 regPCIE_PRBS_ERRCNT_9; -typedef union PCIE_PRBS_FREERUN regPCIE_PRBS_FREERUN; -typedef union PCIE_PRBS_HI_BITCNT regPCIE_PRBS_HI_BITCNT; -typedef union PCIE_PRBS_LO_BITCNT regPCIE_PRBS_LO_BITCNT; -typedef union PCIE_PRBS_MISC__CI regPCIE_PRBS_MISC__CI; -typedef union PCIE_PRBS_MISC__VI regPCIE_PRBS_MISC__VI; -typedef union PCIE_PRBS_MISC__SI regPCIE_PRBS_MISC__SI; -typedef union PCIE_PRBS_STATUS1 regPCIE_PRBS_STATUS1; -typedef union PCIE_PRBS_STATUS2 regPCIE_PRBS_STATUS2; -typedef union PCIE_PRBS_USER_PATTERN__CI__VI regPCIE_PRBS_USER_PATTERN__CI__VI; -typedef union PCIE_PRBS_USER_PATTERN__SI regPCIE_PRBS_USER_PATTERN__SI; -typedef union PCIE_PWR_BUDGET_CAP__CI__VI regPCIE_PWR_BUDGET_CAP__CI__VI; -typedef union PCIE_PWR_BUDGET_DATA_SELECT__CI__VI regPCIE_PWR_BUDGET_DATA_SELECT__CI__VI; -typedef union PCIE_PWR_BUDGET_DATA__CI__VI regPCIE_PWR_BUDGET_DATA__CI__VI; -typedef union PCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI regPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI; -typedef union PCIE_P_BUF_STATUS__CI__VI regPCIE_P_BUF_STATUS__CI__VI; -typedef union PCIE_P_BUF_STATUS__SI regPCIE_P_BUF_STATUS__SI; -typedef union PCIE_P_CNTL__CI__VI regPCIE_P_CNTL__CI__VI; -typedef union PCIE_P_CNTL__SI regPCIE_P_CNTL__SI; -typedef union PCIE_P_DECODER_STATUS__CI__VI regPCIE_P_DECODER_STATUS__CI__VI; -typedef union PCIE_P_DECODER_STATUS__SI regPCIE_P_DECODER_STATUS__SI; -typedef union PCIE_P_DECODE_ERR_CNTL__SI regPCIE_P_DECODE_ERR_CNTL__SI; -typedef union PCIE_P_DECODE_ERR_CNT_0__SI regPCIE_P_DECODE_ERR_CNT_0__SI; -typedef union PCIE_P_DECODE_ERR_CNT_10__SI regPCIE_P_DECODE_ERR_CNT_10__SI; -typedef union PCIE_P_DECODE_ERR_CNT_11__SI regPCIE_P_DECODE_ERR_CNT_11__SI; -typedef union PCIE_P_DECODE_ERR_CNT_12__SI regPCIE_P_DECODE_ERR_CNT_12__SI; -typedef union PCIE_P_DECODE_ERR_CNT_13__SI regPCIE_P_DECODE_ERR_CNT_13__SI; -typedef union PCIE_P_DECODE_ERR_CNT_14__SI regPCIE_P_DECODE_ERR_CNT_14__SI; -typedef union PCIE_P_DECODE_ERR_CNT_15__SI regPCIE_P_DECODE_ERR_CNT_15__SI; -typedef union PCIE_P_DECODE_ERR_CNT_1__SI regPCIE_P_DECODE_ERR_CNT_1__SI; -typedef union PCIE_P_DECODE_ERR_CNT_2__SI regPCIE_P_DECODE_ERR_CNT_2__SI; -typedef union PCIE_P_DECODE_ERR_CNT_3__SI regPCIE_P_DECODE_ERR_CNT_3__SI; -typedef union PCIE_P_DECODE_ERR_CNT_4__SI regPCIE_P_DECODE_ERR_CNT_4__SI; -typedef union PCIE_P_DECODE_ERR_CNT_5__SI regPCIE_P_DECODE_ERR_CNT_5__SI; -typedef union PCIE_P_DECODE_ERR_CNT_6__SI regPCIE_P_DECODE_ERR_CNT_6__SI; -typedef union PCIE_P_DECODE_ERR_CNT_7__SI regPCIE_P_DECODE_ERR_CNT_7__SI; -typedef union PCIE_P_DECODE_ERR_CNT_8__SI regPCIE_P_DECODE_ERR_CNT_8__SI; -typedef union PCIE_P_DECODE_ERR_CNT_9__SI regPCIE_P_DECODE_ERR_CNT_9__SI; -typedef union PCIE_P_IMP_CNTL_STRENGTH__SI regPCIE_P_IMP_CNTL_STRENGTH__SI; -typedef union PCIE_P_IMP_CNTL_UPDATE__SI regPCIE_P_IMP_CNTL_UPDATE__SI; -typedef union PCIE_P_MISC_DEBUG_STATUS__SI regPCIE_P_MISC_DEBUG_STATUS__SI; -typedef union PCIE_P_MISC_STATUS__CI__VI regPCIE_P_MISC_STATUS__CI__VI; -typedef union PCIE_P_PAD_FORCE_DIS__SI regPCIE_P_PAD_FORCE_DIS__SI; -typedef union PCIE_P_PAD_FORCE_EN__SI regPCIE_P_PAD_FORCE_EN__SI; -typedef union PCIE_P_PAD_MISC_CNTL__SI regPCIE_P_PAD_MISC_CNTL__SI; -typedef union PCIE_P_PLL_CNTL__SI regPCIE_P_PLL_CNTL__SI; -typedef union PCIE_P_PORT_LANE_STATUS regPCIE_P_PORT_LANE_STATUS; -typedef union PCIE_P_RCVR_DEBUG_CNTL__SI regPCIE_P_RCVR_DEBUG_CNTL__SI; -typedef union PCIE_P_RCV_L0S_FTS_DET__CI__VI regPCIE_P_RCV_L0S_FTS_DET__CI__VI; -typedef union PCIE_P_RXP_ERR_RETRAIN_CTL__SI regPCIE_P_RXP_ERR_RETRAIN_CTL__SI; -typedef union PCIE_P_STR_CNTL_UPDATE__SI regPCIE_P_STR_CNTL_UPDATE__SI; -typedef union PCIE_P_SYMSYNC_CTL__SI regPCIE_P_SYMSYNC_CTL__SI; -typedef union PCIE_REG_R_RTR_TIMEOUT_CNTL__SI regPCIE_REG_R_RTR_TIMEOUT_CNTL__SI; -typedef union PCIE_RESERVED regPCIE_RESERVED; -typedef union PCIE_RTR_CPL_TIMEOUT_STATUS__SI regPCIE_RTR_CPL_TIMEOUT_STATUS__SI; -typedef union PCIE_RX_CNTL2__CI__VI regPCIE_RX_CNTL2__CI__VI; -typedef union PCIE_RX_CNTL3__CI__VI regPCIE_RX_CNTL3__CI__VI; -typedef union PCIE_RX_CNTL__CI__VI regPCIE_RX_CNTL__CI__VI; -typedef union PCIE_RX_CNTL__SI regPCIE_RX_CNTL__SI; -typedef union PCIE_RX_CREDITS_ALLOCATED_CPL regPCIE_RX_CREDITS_ALLOCATED_CPL; -typedef union PCIE_RX_CREDITS_ALLOCATED_NP regPCIE_RX_CREDITS_ALLOCATED_NP; -typedef union PCIE_RX_CREDITS_ALLOCATED_P regPCIE_RX_CREDITS_ALLOCATED_P; -typedef union PCIE_RX_CREDITS_RECEIVED_CPL__SI regPCIE_RX_CREDITS_RECEIVED_CPL__SI; -typedef union PCIE_RX_CREDITS_RECEIVED_NP__SI regPCIE_RX_CREDITS_RECEIVED_NP__SI; -typedef union PCIE_RX_CREDITS_RECEIVED_P__SI regPCIE_RX_CREDITS_RECEIVED_P__SI; -typedef union PCIE_RX_EXPECTED_SEQNUM__CI__VI regPCIE_RX_EXPECTED_SEQNUM__CI__VI; -typedef union PCIE_RX_LASTACK_SEQNUM__SI regPCIE_RX_LASTACK_SEQNUM__SI; -typedef union PCIE_RX_LAST_TLP0 regPCIE_RX_LAST_TLP0; -typedef union PCIE_RX_LAST_TLP1 regPCIE_RX_LAST_TLP1; -typedef union PCIE_RX_LAST_TLP2 regPCIE_RX_LAST_TLP2; -typedef union PCIE_RX_LAST_TLP3 regPCIE_RX_LAST_TLP3; -typedef union PCIE_RX_NUM_NACK_GENERATED__SI regPCIE_RX_NUM_NACK_GENERATED__SI; -typedef union PCIE_RX_NUM_NACK__SI regPCIE_RX_NUM_NACK__SI; -typedef union PCIE_RX_NUM_NAK_GENERATED__CI__VI regPCIE_RX_NUM_NAK_GENERATED__CI__VI; -typedef union PCIE_RX_NUM_NAK__CI__VI regPCIE_RX_NUM_NAK__CI__VI; -typedef union PCIE_RX_VENDOR_SPECIFIC regPCIE_RX_VENDOR_SPECIFIC; -typedef union PCIE_SCRATCH regPCIE_SCRATCH; -typedef union PCIE_SECONDARY_ENH_CAP_LIST__CI__VI regPCIE_SECONDARY_ENH_CAP_LIST__CI__VI; -typedef union PCIE_STRAP_F0__CI regPCIE_STRAP_F0__CI; -typedef union PCIE_STRAP_F0__VI regPCIE_STRAP_F0__VI; -typedef union PCIE_STRAP_F1__CI__VI regPCIE_STRAP_F1__CI__VI; -typedef union PCIE_STRAP_F2__CI__VI regPCIE_STRAP_F2__CI__VI; -typedef union PCIE_STRAP_F3__CI__VI regPCIE_STRAP_F3__CI__VI; -typedef union PCIE_STRAP_F4__CI__VI regPCIE_STRAP_F4__CI__VI; -typedef union PCIE_STRAP_F5__CI__VI regPCIE_STRAP_F5__CI__VI; -typedef union PCIE_STRAP_F6__CI__VI regPCIE_STRAP_F6__CI__VI; -typedef union PCIE_STRAP_F7__CI__VI regPCIE_STRAP_F7__CI__VI; -typedef union PCIE_STRAP_I2C_BD regPCIE_STRAP_I2C_BD; -typedef union PCIE_STRAP_MISC2 regPCIE_STRAP_MISC2; -typedef union PCIE_STRAP_MISC__CI__VI regPCIE_STRAP_MISC__CI__VI; -typedef union PCIE_STRAP_MISC__SI regPCIE_STRAP_MISC__SI; -typedef union PCIE_STRAP_PI regPCIE_STRAP_PI; -typedef union PCIE_TLP_PREFIX_LOG0__CI__VI regPCIE_TLP_PREFIX_LOG0__CI__VI; -typedef union PCIE_TLP_PREFIX_LOG1__CI__VI regPCIE_TLP_PREFIX_LOG1__CI__VI; -typedef union PCIE_TLP_PREFIX_LOG2__CI__VI regPCIE_TLP_PREFIX_LOG2__CI__VI; -typedef union PCIE_TLP_PREFIX_LOG3__CI__VI regPCIE_TLP_PREFIX_LOG3__CI__VI; -typedef union PCIE_TRUSTED_BASE_CLASS__SI regPCIE_TRUSTED_BASE_CLASS__SI; -typedef union PCIE_TRUSTED_CAC_CAP_LIST__SI regPCIE_TRUSTED_CAC_CAP_LIST__SI; -typedef union PCIE_TRUSTED_CAC_DEVICE_CORRELATION__SI regPCIE_TRUSTED_CAC_DEVICE_CORRELATION__SI; -typedef union PCIE_TRUSTED_FIRST_CAP_OFFSET__SI regPCIE_TRUSTED_FIRST_CAP_OFFSET__SI; -typedef union PCIE_TRUSTED_PROG_INTERFACE__SI regPCIE_TRUSTED_PROG_INTERFACE__SI; -typedef union PCIE_TRUSTED_SUB_CLASS__SI regPCIE_TRUSTED_SUB_CLASS__SI; -typedef union PCIE_TX_ACK_LATENCY_LIMIT__CI__VI regPCIE_TX_ACK_LATENCY_LIMIT__CI__VI; -typedef union PCIE_TX_ACK_LATENCY_LIMIT__SI regPCIE_TX_ACK_LATENCY_LIMIT__SI; -typedef union PCIE_TX_CNTL__CI__VI regPCIE_TX_CNTL__CI__VI; -typedef union PCIE_TX_CNTL__SI regPCIE_TX_CNTL__SI; -typedef union PCIE_TX_CREDITS_ADVT_CPL regPCIE_TX_CREDITS_ADVT_CPL; -typedef union PCIE_TX_CREDITS_ADVT_NP regPCIE_TX_CREDITS_ADVT_NP; -typedef union PCIE_TX_CREDITS_ADVT_P regPCIE_TX_CREDITS_ADVT_P; -typedef union PCIE_TX_CREDITS_FCU_THRESHOLD__CI__VI regPCIE_TX_CREDITS_FCU_THRESHOLD__CI__VI; -typedef union PCIE_TX_CREDITS_INIT_CPL regPCIE_TX_CREDITS_INIT_CPL; -typedef union PCIE_TX_CREDITS_INIT_NP regPCIE_TX_CREDITS_INIT_NP; -typedef union PCIE_TX_CREDITS_INIT_P regPCIE_TX_CREDITS_INIT_P; -typedef union PCIE_TX_CREDITS_STATUS regPCIE_TX_CREDITS_STATUS; -typedef union PCIE_TX_F0_ATTR_CNTL__CI__VI regPCIE_TX_F0_ATTR_CNTL__CI__VI; -typedef union PCIE_TX_F1_F2_ATTR_CNTL__CI__VI regPCIE_TX_F1_F2_ATTR_CNTL__CI__VI; -typedef union PCIE_TX_LAST_TLP0 regPCIE_TX_LAST_TLP0; -typedef union PCIE_TX_LAST_TLP1 regPCIE_TX_LAST_TLP1; -typedef union PCIE_TX_LAST_TLP2 regPCIE_TX_LAST_TLP2; -typedef union PCIE_TX_LAST_TLP3 regPCIE_TX_LAST_TLP3; -typedef union PCIE_TX_REPLAY regPCIE_TX_REPLAY; -typedef union PCIE_TX_REQUESTER_ID regPCIE_TX_REQUESTER_ID; -typedef union PCIE_TX_REQUEST_NUM_CNTL regPCIE_TX_REQUEST_NUM_CNTL; -typedef union PCIE_TX_SEQ regPCIE_TX_SEQ; -typedef union PCIE_TX_SLVCPL_TIMEOUT_CNTL__SI regPCIE_TX_SLVCPL_TIMEOUT_CNTL__SI; -typedef union PCIE_TX_VENDOR_SPECIFIC regPCIE_TX_VENDOR_SPECIFIC; -typedef union PCIE_UNCORR_ERR_MASK regPCIE_UNCORR_ERR_MASK; -typedef union PCIE_UNCORR_ERR_SEVERITY regPCIE_UNCORR_ERR_SEVERITY; -typedef union PCIE_UNCORR_ERR_STATUS regPCIE_UNCORR_ERR_STATUS; -typedef union PCIE_VC0_RESOURCE_CAP regPCIE_VC0_RESOURCE_CAP; -typedef union PCIE_VC0_RESOURCE_CNTL regPCIE_VC0_RESOURCE_CNTL; -typedef union PCIE_VC0_RESOURCE_STATUS regPCIE_VC0_RESOURCE_STATUS; -typedef union PCIE_VC1_RESOURCE_CAP regPCIE_VC1_RESOURCE_CAP; -typedef union PCIE_VC1_RESOURCE_CNTL regPCIE_VC1_RESOURCE_CNTL; -typedef union PCIE_VC1_RESOURCE_STATUS regPCIE_VC1_RESOURCE_STATUS; -typedef union PCIE_VC_ENH_CAP_LIST regPCIE_VC_ENH_CAP_LIST; -typedef union PCIE_VENDOR_SPECIFIC1 regPCIE_VENDOR_SPECIFIC1; -typedef union PCIE_VENDOR_SPECIFIC2 regPCIE_VENDOR_SPECIFIC2; -typedef union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST regPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST; -typedef union PCIE_VENDOR_SPECIFIC_HDR regPCIE_VENDOR_SPECIFIC_HDR; -typedef union PCIE_WPR_CNTL regPCIE_WPR_CNTL; -typedef union PEER0_FB_OFFSET_HI__CI__VI regPEER0_FB_OFFSET_HI__CI__VI; -typedef union PEER0_FB_OFFSET_LO__CI__VI regPEER0_FB_OFFSET_LO__CI__VI; -typedef union PEER1_FB_OFFSET_HI__CI__VI regPEER1_FB_OFFSET_HI__CI__VI; -typedef union PEER1_FB_OFFSET_LO__CI__VI regPEER1_FB_OFFSET_LO__CI__VI; -typedef union PEER2_FB_OFFSET_HI__CI__VI regPEER2_FB_OFFSET_HI__CI__VI; -typedef union PEER2_FB_OFFSET_LO__CI__VI regPEER2_FB_OFFSET_LO__CI__VI; -typedef union PEER3_FB_OFFSET_HI__CI__VI regPEER3_FB_OFFSET_HI__CI__VI; -typedef union PEER3_FB_OFFSET_LO__CI__VI regPEER3_FB_OFFSET_LO__CI__VI; -typedef union PEER_REG_RANGE0 regPEER_REG_RANGE0; -typedef union PEER_REG_RANGE1 regPEER_REG_RANGE1; -typedef union PERF_MON_CTRL_1__CI__VI regPERF_MON_CTRL_1__CI__VI; -typedef union PERF_MON_CTRL_2__CI__VI regPERF_MON_CTRL_2__CI__VI; -typedef union PHY_AUX_CNTL__SI regPHY_AUX_CNTL__SI; -typedef union PHY_PAD_FORCE_DIS1__SI regPHY_PAD_FORCE_DIS1__SI; -typedef union PHY_PAD_FORCE_DIS2__SI regPHY_PAD_FORCE_DIS2__SI; -typedef union PHY_PAD_FORCE_EN1__SI regPHY_PAD_FORCE_EN1__SI; -typedef union PHY_PAD_FORCE_EN2__SI regPHY_PAD_FORCE_EN2__SI; -typedef union PHY_TESTMODES__SI regPHY_TESTMODES__SI; -typedef union PIPE0_ARBITRATION_CONTROL1__SI regPIPE0_ARBITRATION_CONTROL1__SI; -typedef union PIPE0_ARBITRATION_CONTROL2__SI regPIPE0_ARBITRATION_CONTROL2__SI; -typedef union PIPE0_ARBITRATION_CONTROL3__SI regPIPE0_ARBITRATION_CONTROL3__SI; -typedef union PIPE0_URGENCY_CONTROL__SI regPIPE0_URGENCY_CONTROL__SI; -typedef union PIPE1_ARBITRATION_CONTROL1__SI regPIPE1_ARBITRATION_CONTROL1__SI; -typedef union PIPE1_ARBITRATION_CONTROL2__SI regPIPE1_ARBITRATION_CONTROL2__SI; -typedef union PIPE1_ARBITRATION_CONTROL3__SI regPIPE1_ARBITRATION_CONTROL3__SI; -typedef union PIPE1_URGENCY_CONTROL__SI regPIPE1_URGENCY_CONTROL__SI; -typedef union PIPE2_ARBITRATION_CONTROL1__SI regPIPE2_ARBITRATION_CONTROL1__SI; -typedef union PIPE2_ARBITRATION_CONTROL2__SI regPIPE2_ARBITRATION_CONTROL2__SI; -typedef union PIPE2_ARBITRATION_CONTROL3__SI regPIPE2_ARBITRATION_CONTROL3__SI; -typedef union PIPE2_URGENCY_CONTROL__SI regPIPE2_URGENCY_CONTROL__SI; -typedef union PIPE3_ARBITRATION_CONTROL1__SI regPIPE3_ARBITRATION_CONTROL1__SI; -typedef union PIPE3_ARBITRATION_CONTROL2__SI regPIPE3_ARBITRATION_CONTROL2__SI; -typedef union PIPE3_ARBITRATION_CONTROL3__SI regPIPE3_ARBITRATION_CONTROL3__SI; -typedef union PIPE3_URGENCY_CONTROL__SI regPIPE3_URGENCY_CONTROL__SI; -typedef union PIPE4_ARBITRATION_CONTROL1__SI regPIPE4_ARBITRATION_CONTROL1__SI; -typedef union PIPE4_ARBITRATION_CONTROL2__SI regPIPE4_ARBITRATION_CONTROL2__SI; -typedef union PIPE4_ARBITRATION_CONTROL3__SI regPIPE4_ARBITRATION_CONTROL3__SI; -typedef union PIPE4_URGENCY_CONTROL__SI regPIPE4_URGENCY_CONTROL__SI; -typedef union PIPE5_ARBITRATION_CONTROL1__SI regPIPE5_ARBITRATION_CONTROL1__SI; -typedef union PIPE5_ARBITRATION_CONTROL2__SI regPIPE5_ARBITRATION_CONTROL2__SI; -typedef union PIPE5_ARBITRATION_CONTROL3__SI regPIPE5_ARBITRATION_CONTROL3__SI; -typedef union PIPE5_URGENCY_CONTROL__SI regPIPE5_URGENCY_CONTROL__SI; -typedef union PIXCLK1_RESYNC_CNTL__SI regPIXCLK1_RESYNC_CNTL__SI; -typedef union PIXCLK2_RESYNC_CNTL__SI regPIXCLK2_RESYNC_CNTL__SI; -typedef union PLL_TEST_CNTL regPLL_TEST_CNTL; -typedef union PMI_CAP regPMI_CAP; -typedef union PMI_CAP_LIST regPMI_CAP_LIST; -typedef union PMI_STATUS_CNTL regPMI_STATUS_CNTL; -typedef union PRIORITY_A_CNT__SI regPRIORITY_A_CNT__SI; -typedef union PRIORITY_B_CNT__SI regPRIORITY_B_CNT__SI; -typedef union PROCESSOR_TDP__CI__VI regPROCESSOR_TDP__CI__VI; -typedef union PROG_INTERFACE regPROG_INTERFACE; -typedef union PSTATE_STATUS__CI__VI regPSTATE_STATUS__CI__VI; -typedef union PWR_BIF_SSA__CI__VI regPWR_BIF_SSA__CI__VI; -typedef union PWR_EVENT_CLEAR__CI__VI regPWR_EVENT_CLEAR__CI__VI; -typedef union PWR_EVENT_PENDING__CI__VI regPWR_EVENT_PENDING__CI__VI; -typedef union PWR_EVENT_POLARITY__CI__VI regPWR_EVENT_POLARITY__CI__VI; -typedef union PWR_EVENT_SENSE__CI__VI regPWR_EVENT_SENSE__CI__VI; -typedef union PWR_IDSC_CTRL2__CI regPWR_IDSC_CTRL2__CI; -typedef union PWR_IDSC_CTRL__CI regPWR_IDSC_CTRL__CI; -typedef union PWR_INT_GPIO_CLEAR__CI regPWR_INT_GPIO_CLEAR__CI; -typedef union PWR_INT_GPIO_CLEAR__VI regPWR_INT_GPIO_CLEAR__VI; -typedef union PWR_INT_GPIO_PENDING__CI regPWR_INT_GPIO_PENDING__CI; -typedef union PWR_INT_GPIO_PENDING__VI regPWR_INT_GPIO_PENDING__VI; -typedef union PWR_INT_GPIO_POLARITY__CI regPWR_INT_GPIO_POLARITY__CI; -typedef union PWR_INT_GPIO_POLARITY__VI regPWR_INT_GPIO_POLARITY__VI; -typedef union PWR_INT_GPIO_SENSE__CI regPWR_INT_GPIO_SENSE__CI; -typedef union PWR_INT_GPIO_SENSE__VI regPWR_INT_GPIO_SENSE__VI; -typedef union PWR_MM_CNTL__CI__VI regPWR_MM_CNTL__CI__VI; -typedef union PWR_RLC_CNTL__CI__VI regPWR_RLC_CNTL__CI__VI; -typedef union PWR_SMC_IND_DATA__CI__VI regPWR_SMC_IND_DATA__CI__VI; -typedef union PWR_SMC_IND_INDEX__CI__VI regPWR_SMC_IND_INDEX__CI__VI; -typedef union PWR_STAT_CNTR_CNTL__CI__VI regPWR_STAT_CNTR_CNTL__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_0__CI__VI regPWR_STAT_CNTR_EVENT_0__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_1__CI__VI regPWR_STAT_CNTR_EVENT_1__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_2__CI__VI regPWR_STAT_CNTR_EVENT_2__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_3__CI__VI regPWR_STAT_CNTR_EVENT_3__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_4__CI__VI regPWR_STAT_CNTR_EVENT_4__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_5__CI__VI regPWR_STAT_CNTR_EVENT_5__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_6__CI__VI regPWR_STAT_CNTR_EVENT_6__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_7__CI__VI regPWR_STAT_CNTR_EVENT_7__CI__VI; -typedef union PWR_STAT_CNTR_EVENT_8__CI__VI regPWR_STAT_CNTR_EVENT_8__CI__VI; -typedef union PWR_STAT_CNTR_TIME__CI__VI regPWR_STAT_CNTR_TIME__CI__VI; -typedef union PWR_STAT_EVENT_SEL_CNTL__CI__VI regPWR_STAT_EVENT_SEL_CNTL__CI__VI; -typedef union PWR_STAT_GFX_CU_EVENT_CNTL__CI__VI regPWR_STAT_GFX_CU_EVENT_CNTL__CI__VI; -typedef union PWR_STAT_GFX_NONCU_EVENT_CNTL__CI__VI regPWR_STAT_GFX_NONCU_EVENT_CNTL__CI__VI; -typedef union PWR_SVI2_PLANE1_LOAD__CI regPWR_SVI2_PLANE1_LOAD__CI; -typedef union PWR_SVI2_PLANE2_LOAD__CI regPWR_SVI2_PLANE2_LOAD__CI; -typedef union PWR_SVI2_STATUS__CI regPWR_SVI2_STATUS__CI; -typedef union PWR_SVI2_TELEMETRY_1__CI regPWR_SVI2_TELEMETRY_1__CI; -typedef union PWR_SVI2_TELEMETRY_2__CI regPWR_SVI2_TELEMETRY_2__CI; -typedef union PWR_SVI2_TFN__CI regPWR_SVI2_TFN__CI; -typedef union PWR_SVI2_THERM_CNTL__CI regPWR_SVI2_THERM_CNTL__CI; -typedef union PWR_SVI2_VID__CI regPWR_SVI2_VID__CI; -typedef union RAS_BCI_SIGNATURE0 regRAS_BCI_SIGNATURE0; -typedef union RAS_BCI_SIGNATURE1 regRAS_BCI_SIGNATURE1; -typedef union RAS_CB_SIGNATURE0 regRAS_CB_SIGNATURE0; -typedef union RAS_DB_SIGNATURE0 regRAS_DB_SIGNATURE0; -typedef union RAS_IA_SIGNATURE0 regRAS_IA_SIGNATURE0; -typedef union RAS_IA_SIGNATURE1 regRAS_IA_SIGNATURE1; -typedef union RAS_PA_SIGNATURE0 regRAS_PA_SIGNATURE0; -typedef union RAS_SC_SIGNATURE0 regRAS_SC_SIGNATURE0; -typedef union RAS_SC_SIGNATURE1 regRAS_SC_SIGNATURE1; -typedef union RAS_SC_SIGNATURE2 regRAS_SC_SIGNATURE2; -typedef union RAS_SC_SIGNATURE3 regRAS_SC_SIGNATURE3; -typedef union RAS_SC_SIGNATURE4 regRAS_SC_SIGNATURE4; -typedef union RAS_SC_SIGNATURE5 regRAS_SC_SIGNATURE5; -typedef union RAS_SC_SIGNATURE6 regRAS_SC_SIGNATURE6; -typedef union RAS_SC_SIGNATURE7 regRAS_SC_SIGNATURE7; -typedef union RAS_SIGNATURE_CONTROL regRAS_SIGNATURE_CONTROL; -typedef union RAS_SIGNATURE_MASK regRAS_SIGNATURE_MASK; -typedef union RAS_SPI_SIGNATURE0 regRAS_SPI_SIGNATURE0; -typedef union RAS_SPI_SIGNATURE1 regRAS_SPI_SIGNATURE1; -typedef union RAS_SQ_SIGNATURE0__SI__CI regRAS_SQ_SIGNATURE0__SI__CI; -typedef union RAS_SX_SIGNATURE0 regRAS_SX_SIGNATURE0; -typedef union RAS_SX_SIGNATURE1 regRAS_SX_SIGNATURE1; -typedef union RAS_SX_SIGNATURE2 regRAS_SX_SIGNATURE2; -typedef union RAS_SX_SIGNATURE3 regRAS_SX_SIGNATURE3; -typedef union RAS_TA_SIGNATURE0 regRAS_TA_SIGNATURE0; -typedef union RAS_TD_SIGNATURE0 regRAS_TD_SIGNATURE0; -typedef union RAS_VGT_SIGNATURE0 regRAS_VGT_SIGNATURE0; -typedef union RCU_ASIC_SERIAL_NUM0__SI regRCU_ASIC_SERIAL_NUM0__SI; -typedef union RCU_ASIC_SERIAL_NUM1__SI regRCU_ASIC_SERIAL_NUM1__SI; -typedef union RCU_BACKUP_STRAP0__SI regRCU_BACKUP_STRAP0__SI; -typedef union RCU_BACKUP_STRAP1__SI regRCU_BACKUP_STRAP1__SI; -typedef union RCU_BACKUP_STRAP2__SI regRCU_BACKUP_STRAP2__SI; -typedef union RCU_BACKUP_STRAP3__SI regRCU_BACKUP_STRAP3__SI; -typedef union RCU_CC_ATC_FUSE__SI regRCU_CC_ATC_FUSE__SI; -typedef union RCU_CC_BIF_AZALIA_ID__SI regRCU_CC_BIF_AZALIA_ID__SI; -typedef union RCU_CC_BIF_ID_STRAPS__SI regRCU_CC_BIF_ID_STRAPS__SI; -typedef union RCU_CC_BIF_SECURE_CNTL__SI regRCU_CC_BIF_SECURE_CNTL__SI; -typedef union RCU_CC_BIF_STRAP0__SI regRCU_CC_BIF_STRAP0__SI; -typedef union RCU_CC_BIF_STRAP10__SI regRCU_CC_BIF_STRAP10__SI; -typedef union RCU_CC_BIF_STRAP11__SI regRCU_CC_BIF_STRAP11__SI; -typedef union RCU_CC_BIF_STRAP12__SI regRCU_CC_BIF_STRAP12__SI; -typedef union RCU_CC_BIF_STRAP13__SI regRCU_CC_BIF_STRAP13__SI; -typedef union RCU_CC_BIF_STRAP14__SI regRCU_CC_BIF_STRAP14__SI; -typedef union RCU_CC_BIF_STRAP1__SI regRCU_CC_BIF_STRAP1__SI; -typedef union RCU_CC_BIF_STRAP2__SI regRCU_CC_BIF_STRAP2__SI; -typedef union RCU_CC_BIF_STRAP3__SI regRCU_CC_BIF_STRAP3__SI; -typedef union RCU_CC_BIF_STRAP4__SI regRCU_CC_BIF_STRAP4__SI; -typedef union RCU_CC_BIF_STRAP5__SI regRCU_CC_BIF_STRAP5__SI; -typedef union RCU_CC_BIF_STRAP6__SI regRCU_CC_BIF_STRAP6__SI; -typedef union RCU_CC_BIF_STRAP7__SI regRCU_CC_BIF_STRAP7__SI; -typedef union RCU_CC_BIF_STRAP8__SI regRCU_CC_BIF_STRAP8__SI; -typedef union RCU_CC_BIF_STRAP9__SI regRCU_CC_BIF_STRAP9__SI; -typedef union RCU_CC_BIF_STRAP_FUSE0__SI regRCU_CC_BIF_STRAP_FUSE0__SI; -typedef union RCU_CC_DC_AUDIO__SI regRCU_CC_DC_AUDIO__SI; -typedef union RCU_CC_DC_PIPE_DIS__SI regRCU_CC_DC_PIPE_DIS__SI; -typedef union RCU_CC_GC_RB_REDUNDANCY0__SI regRCU_CC_GC_RB_REDUNDANCY0__SI; -typedef union RCU_CC_GC_RB_REDUNDANCY1__SI regRCU_CC_GC_RB_REDUNDANCY1__SI; -typedef union RCU_CC_GC_SHADER_ARRAY_CONFIG0__SI regRCU_CC_GC_SHADER_ARRAY_CONFIG0__SI; -typedef union RCU_CC_GC_SHADER_ARRAY_CONFIG1__SI regRCU_CC_GC_SHADER_ARRAY_CONFIG1__SI; -typedef union RCU_CC_GC_SHADER_ARRAY_CONFIG2__SI regRCU_CC_GC_SHADER_ARRAY_CONFIG2__SI; -typedef union RCU_CC_GC_SHADER_ARRAY_CONFIG3__SI regRCU_CC_GC_SHADER_ARRAY_CONFIG3__SI; -typedef union RCU_CC_MC_MAX_CHANNEL__SI regRCU_CC_MC_MAX_CHANNEL__SI; -typedef union RCU_CC_RB_BACKEND_DISABLE0__SI regRCU_CC_RB_BACKEND_DISABLE0__SI; -typedef union RCU_CC_RB_BACKEND_DISABLE1__SI regRCU_CC_RB_BACKEND_DISABLE1__SI; -typedef union RCU_CC_RB_BACKEND_DISABLE2__SI regRCU_CC_RB_BACKEND_DISABLE2__SI; -typedef union RCU_CC_RB_BACKEND_DISABLE3__SI regRCU_CC_RB_BACKEND_DISABLE3__SI; -typedef union RCU_CC_TCC_DISABLE__SI regRCU_CC_TCC_DISABLE__SI; -typedef union RCU_CC_UVD_DISABLE__SI regRCU_CC_UVD_DISABLE__SI; -typedef union RCU_DYN_RM2__SI regRCU_DYN_RM2__SI; -typedef union RCU_DYN_RM__SI regRCU_DYN_RM__SI; -typedef union RCU_EFUSE_SCRATCH__SI regRCU_EFUSE_SCRATCH__SI; -typedef union RCU_EFUSE_STRAPS0__SI regRCU_EFUSE_STRAPS0__SI; -typedef union RCU_EFUSE_STRAPS10__SI regRCU_EFUSE_STRAPS10__SI; -typedef union RCU_EFUSE_STRAPS11__SI regRCU_EFUSE_STRAPS11__SI; -typedef union RCU_EFUSE_STRAPS12__SI regRCU_EFUSE_STRAPS12__SI; -typedef union RCU_EFUSE_STRAPS13__SI regRCU_EFUSE_STRAPS13__SI; -typedef union RCU_EFUSE_STRAPS14__SI regRCU_EFUSE_STRAPS14__SI; -typedef union RCU_EFUSE_STRAPS15__SI regRCU_EFUSE_STRAPS15__SI; -typedef union RCU_EFUSE_STRAPS16__SI regRCU_EFUSE_STRAPS16__SI; -typedef union RCU_EFUSE_STRAPS17__SI regRCU_EFUSE_STRAPS17__SI; -typedef union RCU_EFUSE_STRAPS18__SI regRCU_EFUSE_STRAPS18__SI; -typedef union RCU_EFUSE_STRAPS19__SI regRCU_EFUSE_STRAPS19__SI; -typedef union RCU_EFUSE_STRAPS1__SI regRCU_EFUSE_STRAPS1__SI; -typedef union RCU_EFUSE_STRAPS20__SI regRCU_EFUSE_STRAPS20__SI; -typedef union RCU_EFUSE_STRAPS21__SI regRCU_EFUSE_STRAPS21__SI; -typedef union RCU_EFUSE_STRAPS22__SI regRCU_EFUSE_STRAPS22__SI; -typedef union RCU_EFUSE_STRAPS23__SI regRCU_EFUSE_STRAPS23__SI; -typedef union RCU_EFUSE_STRAPS24__SI regRCU_EFUSE_STRAPS24__SI; -typedef union RCU_EFUSE_STRAPS25__SI regRCU_EFUSE_STRAPS25__SI; -typedef union RCU_EFUSE_STRAPS26__SI regRCU_EFUSE_STRAPS26__SI; -typedef union RCU_EFUSE_STRAPS27__SI regRCU_EFUSE_STRAPS27__SI; -typedef union RCU_EFUSE_STRAPS28__SI regRCU_EFUSE_STRAPS28__SI; -typedef union RCU_EFUSE_STRAPS29__SI regRCU_EFUSE_STRAPS29__SI; -typedef union RCU_EFUSE_STRAPS2__SI regRCU_EFUSE_STRAPS2__SI; -typedef union RCU_EFUSE_STRAPS30__SI regRCU_EFUSE_STRAPS30__SI; -typedef union RCU_EFUSE_STRAPS31__SI regRCU_EFUSE_STRAPS31__SI; -typedef union RCU_EFUSE_STRAPS32__SI regRCU_EFUSE_STRAPS32__SI; -typedef union RCU_EFUSE_STRAPS33__SI regRCU_EFUSE_STRAPS33__SI; -typedef union RCU_EFUSE_STRAPS34__SI regRCU_EFUSE_STRAPS34__SI; -typedef union RCU_EFUSE_STRAPS35__SI regRCU_EFUSE_STRAPS35__SI; -typedef union RCU_EFUSE_STRAPS36__SI regRCU_EFUSE_STRAPS36__SI; -typedef union RCU_EFUSE_STRAPS37__SI regRCU_EFUSE_STRAPS37__SI; -typedef union RCU_EFUSE_STRAPS38__SI regRCU_EFUSE_STRAPS38__SI; -typedef union RCU_EFUSE_STRAPS39__SI regRCU_EFUSE_STRAPS39__SI; -typedef union RCU_EFUSE_STRAPS3__SI regRCU_EFUSE_STRAPS3__SI; -typedef union RCU_EFUSE_STRAPS40__SI regRCU_EFUSE_STRAPS40__SI; -typedef union RCU_EFUSE_STRAPS4__SI regRCU_EFUSE_STRAPS4__SI; -typedef union RCU_EFUSE_STRAPS5__SI regRCU_EFUSE_STRAPS5__SI; -typedef union RCU_EFUSE_STRAPS6__SI regRCU_EFUSE_STRAPS6__SI; -typedef union RCU_EFUSE_STRAPS7__SI regRCU_EFUSE_STRAPS7__SI; -typedef union RCU_EFUSE_STRAPS8__SI regRCU_EFUSE_STRAPS8__SI; -typedef union RCU_EFUSE_STRAPS9__SI regRCU_EFUSE_STRAPS9__SI; -typedef union RCU_FCTRL__SI regRCU_FCTRL__SI; -typedef union RCU_IND_DATA__SI regRCU_IND_DATA__SI; -typedef union RCU_IND_INDEX__SI regRCU_IND_INDEX__SI; -typedef union RCU_MISC_CTRL__CI__VI regRCU_MISC_CTRL__CI__VI; -typedef union RCU_MISC_CTRL__SI regRCU_MISC_CTRL__SI; -typedef union RCU_PCIECONFIG__CI__VI regRCU_PCIECONFIG__CI__VI; -typedef union RCU_ROM_BIF_STRAP0__SI regRCU_ROM_BIF_STRAP0__SI; -typedef union RCU_ROM_BIF_STRAP10__SI regRCU_ROM_BIF_STRAP10__SI; -typedef union RCU_ROM_BIF_STRAP11__SI regRCU_ROM_BIF_STRAP11__SI; -typedef union RCU_ROM_BIF_STRAP12__SI regRCU_ROM_BIF_STRAP12__SI; -typedef union RCU_ROM_BIF_STRAP13__SI regRCU_ROM_BIF_STRAP13__SI; -typedef union RCU_ROM_BIF_STRAP14__SI regRCU_ROM_BIF_STRAP14__SI; -typedef union RCU_ROM_BIF_STRAP1__SI regRCU_ROM_BIF_STRAP1__SI; -typedef union RCU_ROM_BIF_STRAP2__SI regRCU_ROM_BIF_STRAP2__SI; -typedef union RCU_ROM_BIF_STRAP3__SI regRCU_ROM_BIF_STRAP3__SI; -typedef union RCU_ROM_BIF_STRAP4__SI regRCU_ROM_BIF_STRAP4__SI; -typedef union RCU_ROM_BIF_STRAP5__SI regRCU_ROM_BIF_STRAP5__SI; -typedef union RCU_ROM_BIF_STRAP6__SI regRCU_ROM_BIF_STRAP6__SI; -typedef union RCU_ROM_BIF_STRAP7__SI regRCU_ROM_BIF_STRAP7__SI; -typedef union RCU_ROM_BIF_STRAP8__SI regRCU_ROM_BIF_STRAP8__SI; -typedef union RCU_ROM_BIF_STRAP9__SI regRCU_ROM_BIF_STRAP9__SI; -typedef union RCU_ROM_MSC_STRAPS0__SI regRCU_ROM_MSC_STRAPS0__SI; -typedef union RCU_ROM_MSC_STRAPS1__SI regRCU_ROM_MSC_STRAPS1__SI; -typedef union RCU_ROM_MSC_STRAPS2__SI regRCU_ROM_MSC_STRAPS2__SI; -typedef union RCU_ROM_MSC_STRAPS3__SI regRCU_ROM_MSC_STRAPS3__SI; -typedef union RCU_ROM_MSC_STRAPS4__SI regRCU_ROM_MSC_STRAPS4__SI; -typedef union RCU_ROM_MSC_STRAPS5__SI regRCU_ROM_MSC_STRAPS5__SI; -typedef union RCU_ROM_SPARE_STRAP0__SI regRCU_ROM_SPARE_STRAP0__SI; -typedef union RCU_ROM_SPARE_STRAP1__SI regRCU_ROM_SPARE_STRAP1__SI; -typedef union RCU_ROM_SPARE_STRAP2__SI regRCU_ROM_SPARE_STRAP2__SI; -typedef union RCU_ROM_SPARE_STRAP3__SI regRCU_ROM_SPARE_STRAP3__SI; -typedef union RCU_SCRATCH_0__SI regRCU_SCRATCH_0__SI; -typedef union RCU_SCRATCH_1__SI regRCU_SCRATCH_1__SI; -typedef union RCU_SCRATCH_2__SI regRCU_SCRATCH_2__SI; -typedef union RCU_SPARE_EFUSE__SI regRCU_SPARE_EFUSE__SI; -typedef union RCU_STATUS__SI regRCU_STATUS__SI; -typedef union RCU_SYSRESET__CI regRCU_SYSRESET__CI; -typedef union RCU_SYSRESET__VI regRCU_SYSRESET__VI; -typedef union RCU_UC_EVENTS_DATA__SI regRCU_UC_EVENTS_DATA__SI; -typedef union RCU_UC_EVENTS__CI__VI regRCU_UC_EVENTS__CI__VI; -typedef union RCU_UC_EVENTS__SI regRCU_UC_EVENTS__SI; -typedef union RCU_UC_INT__SI regRCU_UC_INT__SI; -typedef union RCU_UC_ROMRD_INSTR__SI regRCU_UC_ROMRD_INSTR__SI; -typedef union REQ_FIFO_STAT__SI regREQ_FIFO_STAT__SI; -typedef union RESPONSE_INTERRUPT_COUNT__SI regRESPONSE_INTERRUPT_COUNT__SI; -typedef union REVISION_ID regREVISION_ID; -typedef union RE_CTL2_B__SI regRE_CTL2_B__SI; -typedef union RE_CTL2__SI regRE_CTL2__SI; -typedef union RE_CTL__SI regRE_CTL__SI; -typedef union RE_DEBUG_INT_STAT__SI regRE_DEBUG_INT_STAT__SI; -typedef union RE_DEBUG_SI_B__SI regRE_DEBUG_SI_B__SI; -typedef union RE_DEBUG_SI__SI regRE_DEBUG_SI__SI; -typedef union RE_DECODE_CMD__SI regRE_DECODE_CMD__SI; -typedef union RE_HW_DEBUG__SI regRE_HW_DEBUG__SI; -typedef union RE_INT_EN__SI regRE_INT_EN__SI; -typedef union RE_INT_STAT__SI regRE_INT_STAT__SI; -typedef union RE_LMA_ADR__SI regRE_LMA_ADR__SI; -typedef union RE_LMA_CTL__SI regRE_LMA_CTL__SI; -typedef union RE_LMA_DAT__SI regRE_LMA_DAT__SI; -typedef union RE_PES_CTL__SI regRE_PES_CTL__SI; -typedef union RE_PES_DECODE_CMD__SI regRE_PES_DECODE_CMD__SI; -typedef union RE_PES_RESULT__SI regRE_PES_RESULT__SI; -typedef union RE_PES_SHIFTER_STAT__SI regRE_PES_SHIFTER_STAT__SI; -typedef union RE_PPS_INFO__SI regRE_PPS_INFO__SI; -typedef union RE_RESULT__SI regRE_RESULT__SI; -typedef union RE_SHIFTER_B_STAT2__SI regRE_SHIFTER_B_STAT2__SI; -typedef union RE_SHIFTER_CTXT__SI regRE_SHIFTER_CTXT__SI; -typedef union RE_SHIFTER_STAT2__SI regRE_SHIFTER_STAT2__SI; -typedef union RE_SHIFTER_STAT__SI regRE_SHIFTER_STAT__SI; -typedef union RE_SI_B_CTL__SI regRE_SI_B_CTL__SI; -typedef union RE_SI_B_STAT__SI regRE_SI_B_STAT__SI; -typedef union RE_SI_CTL__SI regRE_SI_CTL__SI; -typedef union RE_SI_INT_CTL__SI regRE_SI_INT_CTL__SI; -typedef union RE_SI_STAT__SI regRE_SI_STAT__SI; -typedef union RE_SLICE_INFO__SI regRE_SLICE_INFO__SI; -typedef union RE_SPS_INFO__SI regRE_SPS_INFO__SI; -typedef union RE_SRAM_RM_CTL__SI regRE_SRAM_RM_CTL__SI; -typedef union RE_STAT__SI regRE_STAT__SI; -typedef union RINGOSC_MASK regRINGOSC_MASK; -typedef union RIRB_CONTROL__SI regRIRB_CONTROL__SI; -typedef union RIRB_LOWER_BASE_ADDRESS__SI regRIRB_LOWER_BASE_ADDRESS__SI; -typedef union RIRB_SIZE__SI regRIRB_SIZE__SI; -typedef union RIRB_STATUS__SI regRIRB_STATUS__SI; -typedef union RIRB_UPPER_BASE_ADDRESS__SI regRIRB_UPPER_BASE_ADDRESS__SI; -typedef union RIRB_WRITE_POINTER__SI regRIRB_WRITE_POINTER__SI; -typedef union RI_CRC__SI regRI_CRC__SI; -typedef union RI_CTL__SI regRI_CTL__SI; -typedef union RI_DEBUG_INT_STAT__SI regRI_DEBUG_INT_STAT__SI; -typedef union RI_INT_EN__SI regRI_INT_EN__SI; -typedef union RI_INT_STAT__SI regRI_INT_STAT__SI; -typedef union RLC_AUTO_PG_CTRL regRLC_AUTO_PG_CTRL; -typedef union RLC_CAPTURE_GPU_CLOCK_COUNT regRLC_CAPTURE_GPU_CLOCK_COUNT; -typedef union RLC_CGCG_CGLS_CTRL__CI regRLC_CGCG_CGLS_CTRL__CI; -typedef union RLC_CGCG_CGLS_CTRL__VI regRLC_CGCG_CGLS_CTRL__VI; -typedef union RLC_CGCG_CGLS_CTRL__SI regRLC_CGCG_CGLS_CTRL__SI; -typedef union RLC_CGCG_RAMP_CTRL regRLC_CGCG_RAMP_CTRL; -typedef union RLC_CGTT_MGCG_OVERRIDE regRLC_CGTT_MGCG_OVERRIDE; -typedef union RLC_CLEARSTATE_RESTORE_BASE__SI regRLC_CLEARSTATE_RESTORE_BASE__SI; -typedef union RLC_CNTL regRLC_CNTL; -typedef union RLC_CURRENT_CONTEXT__SI regRLC_CURRENT_CONTEXT__SI; -typedef union RLC_CU_STATUS__CI__VI regRLC_CU_STATUS__CI__VI; -typedef union RLC_CU_STATUS__SI regRLC_CU_STATUS__SI; -typedef union RLC_DEBUG regRLC_DEBUG; -typedef union RLC_DEBUG_SELECT regRLC_DEBUG_SELECT; -typedef union RLC_DRIVER_CPDMA_STATUS__SI__CI regRLC_DRIVER_CPDMA_STATUS__SI__CI; -typedef union RLC_DRMDMA_CURRENT_CONTEXT__SI regRLC_DRMDMA_CURRENT_CONTEXT__SI; -typedef union RLC_DRMDMA_HB_RPTR__SI regRLC_DRMDMA_HB_RPTR__SI; -typedef union RLC_DRMDMA_HB_WPTR_MSB_ADDR__SI regRLC_DRMDMA_HB_WPTR_MSB_ADDR__SI; -typedef union RLC_DRMDMA_HB_WPTR__SI regRLC_DRMDMA_HB_WPTR__SI; -typedef union RLC_DRMDMA_RL_BASE__SI regRLC_DRMDMA_RL_BASE__SI; -typedef union RLC_DRMDMA_RL_SIZE__SI regRLC_DRMDMA_RL_SIZE__SI; -typedef union RLC_DYN_PG_REQUEST__CI__VI regRLC_DYN_PG_REQUEST__CI__VI; -typedef union RLC_DYN_PG_REQUEST__SI regRLC_DYN_PG_REQUEST__SI; -typedef union RLC_DYN_PG_STATUS__CI__VI regRLC_DYN_PG_STATUS__CI__VI; -typedef union RLC_DYN_PG_STATUS__SI regRLC_DYN_PG_STATUS__SI; -typedef union RLC_GCPM_GENERAL_0__SI regRLC_GCPM_GENERAL_0__SI; -typedef union RLC_GCPM_GENERAL_1__SI regRLC_GCPM_GENERAL_1__SI; -typedef union RLC_GCPM_GENERAL_2__SI regRLC_GCPM_GENERAL_2__SI; -typedef union RLC_GCPM_GENERAL_3__SI regRLC_GCPM_GENERAL_3__SI; -typedef union RLC_GCPM_GENERAL_4__SI regRLC_GCPM_GENERAL_4__SI; -typedef union RLC_GCPM_GENERAL_5__SI regRLC_GCPM_GENERAL_5__SI; -typedef union RLC_GCPM_GENERAL_6__SI regRLC_GCPM_GENERAL_6__SI; -typedef union RLC_GCPM_GENERAL_7__SI regRLC_GCPM_GENERAL_7__SI; -typedef union RLC_GPM_CU_PD_TIMEOUT__CI regRLC_GPM_CU_PD_TIMEOUT__CI; -typedef union RLC_GPM_DEBUG_SELECT__CI__VI regRLC_GPM_DEBUG_SELECT__CI__VI; -typedef union RLC_GPM_DEBUG__CI__VI regRLC_GPM_DEBUG__CI__VI; -typedef union RLC_GPM_GENERAL_0__CI__VI regRLC_GPM_GENERAL_0__CI__VI; -typedef union RLC_GPM_GENERAL_1__CI__VI regRLC_GPM_GENERAL_1__CI__VI; -typedef union RLC_GPM_GENERAL_2__CI__VI regRLC_GPM_GENERAL_2__CI__VI; -typedef union RLC_GPM_GENERAL_3__CI__VI regRLC_GPM_GENERAL_3__CI__VI; -typedef union RLC_GPM_GENERAL_4__CI__VI regRLC_GPM_GENERAL_4__CI__VI; -typedef union RLC_GPM_GENERAL_5__CI__VI regRLC_GPM_GENERAL_5__CI__VI; -typedef union RLC_GPM_GENERAL_6__CI__VI regRLC_GPM_GENERAL_6__CI__VI; -typedef union RLC_GPM_GENERAL_7__CI__VI regRLC_GPM_GENERAL_7__CI__VI; -typedef union RLC_GPM_LOG_ADDR__CI regRLC_GPM_LOG_ADDR__CI; -typedef union RLC_GPM_LOG_CONT__CI__VI regRLC_GPM_LOG_CONT__CI__VI; -typedef union RLC_GPM_LOG_SIZE__CI__VI regRLC_GPM_LOG_SIZE__CI__VI; -typedef union RLC_GPM_PERF_COUNT_0__CI__VI regRLC_GPM_PERF_COUNT_0__CI__VI; -typedef union RLC_GPM_PERF_COUNT_1__CI__VI regRLC_GPM_PERF_COUNT_1__CI__VI; -typedef union RLC_GPM_SCRATCH_ADDR__CI__VI regRLC_GPM_SCRATCH_ADDR__CI__VI; -typedef union RLC_GPM_SCRATCH_DATA__CI__VI regRLC_GPM_SCRATCH_DATA__CI__VI; -typedef union RLC_GPM_STAT__CI__VI regRLC_GPM_STAT__CI__VI; -typedef union RLC_GPM_THREAD_ENABLE__CI__VI regRLC_GPM_THREAD_ENABLE__CI__VI; -typedef union RLC_GPM_THREAD_PRIORITY__CI__VI regRLC_GPM_THREAD_PRIORITY__CI__VI; -typedef union RLC_GPM_UCODE_ADDR__CI__VI regRLC_GPM_UCODE_ADDR__CI__VI; -typedef union RLC_GPM_UCODE_DATA__CI__VI regRLC_GPM_UCODE_DATA__CI__VI; -typedef union RLC_GPM_VMID_THREAD0__CI__VI regRLC_GPM_VMID_THREAD0__CI__VI; -typedef union RLC_GPM_VMID_THREAD1__CI__VI regRLC_GPM_VMID_THREAD1__CI__VI; -typedef union RLC_GPR_REG1__CI__VI regRLC_GPR_REG1__CI__VI; -typedef union RLC_GPR_REG2__CI__VI regRLC_GPR_REG2__CI__VI; -typedef union RLC_GPU_CLOCK_32 regRLC_GPU_CLOCK_32; -typedef union RLC_GPU_CLOCK_32_RES_SEL regRLC_GPU_CLOCK_32_RES_SEL; -typedef union RLC_GPU_CLOCK_COUNT_LSB regRLC_GPU_CLOCK_COUNT_LSB; -typedef union RLC_GPU_CLOCK_COUNT_MSB regRLC_GPU_CLOCK_COUNT_MSB; -typedef union RLC_JUMP_TABLE_RESTORE__CI__VI regRLC_JUMP_TABLE_RESTORE__CI__VI; -typedef union RLC_LB_ALWAYS_ACTIVE_CU_MASK__CI__VI regRLC_LB_ALWAYS_ACTIVE_CU_MASK__CI__VI; -typedef union RLC_LB_ALWAYS_ACTIVE_CU_MASK__SI regRLC_LB_ALWAYS_ACTIVE_CU_MASK__SI; -typedef union RLC_LB_CNTL regRLC_LB_CNTL; -typedef union RLC_LB_CNTR_INIT regRLC_LB_CNTR_INIT; -typedef union RLC_LB_CNTR_MAX regRLC_LB_CNTR_MAX; -typedef union RLC_LB_INIT_CU_MASK__CI__VI regRLC_LB_INIT_CU_MASK__CI__VI; -typedef union RLC_LB_INIT_CU_MASK__SI regRLC_LB_INIT_CU_MASK__SI; -typedef union RLC_LB_PARAMS regRLC_LB_PARAMS; -typedef union RLC_LOAD_BALANCE_CNTR regRLC_LOAD_BALANCE_CNTR; -typedef union RLC_MAX_PG_CU regRLC_MAX_PG_CU; -typedef union RLC_MC_CNTL regRLC_MC_CNTL; -typedef union RLC_MEM_SLP_CNTL regRLC_MEM_SLP_CNTL; -typedef union RLC_PERFCOUNTER0_HI regRLC_PERFCOUNTER0_HI; -typedef union RLC_PERFCOUNTER0_LO regRLC_PERFCOUNTER0_LO; -typedef union RLC_PERFCOUNTER0_SELECT regRLC_PERFCOUNTER0_SELECT; -typedef union RLC_PERFCOUNTER1_HI regRLC_PERFCOUNTER1_HI; -typedef union RLC_PERFCOUNTER1_LO regRLC_PERFCOUNTER1_LO; -typedef union RLC_PERFCOUNTER1_SELECT regRLC_PERFCOUNTER1_SELECT; -typedef union RLC_PERFMON_CNTL regRLC_PERFMON_CNTL; -typedef union RLC_PG_ALWAYS_ON_CU_MASK__CI__VI regRLC_PG_ALWAYS_ON_CU_MASK__CI__VI; -typedef union RLC_PG_ALWAYS_ON_CU_MASK__SI regRLC_PG_ALWAYS_ON_CU_MASK__SI; -typedef union RLC_PG_CNTL regRLC_PG_CNTL; -typedef union RLC_PG_DELAY_2__CI__VI regRLC_PG_DELAY_2__CI__VI; -typedef union RLC_PG_DELAY__CI__VI regRLC_PG_DELAY__CI__VI; -typedef union RLC_RL_BASE__SI regRLC_RL_BASE__SI; -typedef union RLC_RL_SIZE__SI regRLC_RL_SIZE__SI; -typedef union RLC_SAFE_MODE__CI regRLC_SAFE_MODE__CI; -typedef union RLC_SAFE_MODE__VI regRLC_SAFE_MODE__VI; -typedef union RLC_SAVE_AND_RESTORE_BASE__SI__CI regRLC_SAVE_AND_RESTORE_BASE__SI__CI; -typedef union RLC_SERDES_CU_MASTER_BUSY__CI__VI regRLC_SERDES_CU_MASTER_BUSY__CI__VI; -typedef union RLC_SERDES_MASTER_BUSY_0__SI regRLC_SERDES_MASTER_BUSY_0__SI; -typedef union RLC_SERDES_MASTER_BUSY_1__SI regRLC_SERDES_MASTER_BUSY_1__SI; -typedef union RLC_SERDES_NONCU_MASTER_BUSY__CI regRLC_SERDES_NONCU_MASTER_BUSY__CI; -typedef union RLC_SERDES_NONCU_MASTER_BUSY__VI regRLC_SERDES_NONCU_MASTER_BUSY__VI; -typedef union RLC_SERDES_RD_DATA_0 regRLC_SERDES_RD_DATA_0; -typedef union RLC_SERDES_RD_DATA_1 regRLC_SERDES_RD_DATA_1; -typedef union RLC_SERDES_RD_DATA_2 regRLC_SERDES_RD_DATA_2; -typedef union RLC_SERDES_RD_MASTER_INDEX__CI regRLC_SERDES_RD_MASTER_INDEX__CI; -typedef union RLC_SERDES_RD_MASTER_INDEX__VI regRLC_SERDES_RD_MASTER_INDEX__VI; -typedef union RLC_SERDES_RD_MASTER_INDEX__SI regRLC_SERDES_RD_MASTER_INDEX__SI; -typedef union RLC_SERDES_WR_CTRL__CI regRLC_SERDES_WR_CTRL__CI; -typedef union RLC_SERDES_WR_CTRL__VI regRLC_SERDES_WR_CTRL__VI; -typedef union RLC_SERDES_WR_CTRL__SI regRLC_SERDES_WR_CTRL__SI; -typedef union RLC_SERDES_WR_CU_MASTER_MASK__CI__VI regRLC_SERDES_WR_CU_MASTER_MASK__CI__VI; -typedef union RLC_SERDES_WR_DATA regRLC_SERDES_WR_DATA; -typedef union RLC_SERDES_WR_MASTER_MASK_0__SI regRLC_SERDES_WR_MASTER_MASK_0__SI; -typedef union RLC_SERDES_WR_MASTER_MASK_1__SI regRLC_SERDES_WR_MASTER_MASK_1__SI; -typedef union RLC_SERDES_WR_NONCU_MASTER_MASK__CI regRLC_SERDES_WR_NONCU_MASTER_MASK__CI; -typedef union RLC_SERDES_WR_NONCU_MASTER_MASK__VI regRLC_SERDES_WR_NONCU_MASTER_MASK__VI; -typedef union RLC_SMU_GRBM_REG_SAVE_CTRL regRLC_SMU_GRBM_REG_SAVE_CTRL; -typedef union RLC_SMU_PG_CTRL__SI__CI regRLC_SMU_PG_CTRL__SI__CI; -typedef union RLC_SMU_PG_WAKE_UP_CTRL__SI__CI regRLC_SMU_PG_WAKE_UP_CTRL__SI__CI; -typedef union RLC_SOFT_RESET_GPU__SI__CI regRLC_SOFT_RESET_GPU__SI__CI; -typedef union RLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_DEBUG_SELECT__CI__VI regRLC_SPM_DEBUG_SELECT__CI__VI; -typedef union RLC_SPM_DEBUG__CI__VI regRLC_SPM_DEBUG__CI__VI; -typedef union RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI regRLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI; -typedef union RLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI regRLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI; -typedef union RLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_INT_CNTL__CI__VI regRLC_SPM_INT_CNTL__CI__VI; -typedef union RLC_SPM_INT_STATUS__CI__VI regRLC_SPM_INT_STATUS__CI__VI; -typedef union RLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_PERFMON_CNTL__CI__VI regRLC_SPM_PERFMON_CNTL__CI__VI; -typedef union RLC_SPM_PERFMON_RING_BASE_HI__CI__VI regRLC_SPM_PERFMON_RING_BASE_HI__CI__VI; -typedef union RLC_SPM_PERFMON_RING_BASE_LO__CI__VI regRLC_SPM_PERFMON_RING_BASE_LO__CI__VI; -typedef union RLC_SPM_PERFMON_RING_SIZE__CI__VI regRLC_SPM_PERFMON_RING_SIZE__CI__VI; -typedef union RLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI regRLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI; -typedef union RLC_SPM_RING_RDPTR__CI__VI regRLC_SPM_RING_RDPTR__CI__VI; -typedef union RLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_SEGMENT_THRESHOLD__CI__VI regRLC_SPM_SEGMENT_THRESHOLD__CI__VI; -typedef union RLC_SPM_SE_MUXSEL_ADDR__CI__VI regRLC_SPM_SE_MUXSEL_ADDR__CI__VI; -typedef union RLC_SPM_SE_MUXSEL_DATA__CI__VI regRLC_SPM_SE_MUXSEL_DATA__CI__VI; -typedef union RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI regRLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI; -typedef union RLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI; -typedef union RLC_SPM_VMID__CI__VI regRLC_SPM_VMID__CI__VI; -typedef union RLC_STATIC_PG_STATUS__CI__VI regRLC_STATIC_PG_STATUS__CI__VI; -typedef union RLC_STAT__CI__VI regRLC_STAT__CI__VI; -typedef union RLC_STAT__SI regRLC_STAT__SI; -typedef union RLC_THREAD1_DELAY regRLC_THREAD1_DELAY; -typedef union RLC_THREAD_ENABLE__SI regRLC_THREAD_ENABLE__SI; -typedef union RLC_THREAD_PRIORITY__SI regRLC_THREAD_PRIORITY__SI; -typedef union RLC_TTOP_DELAY__SI regRLC_TTOP_DELAY__SI; -typedef union RLC_UCODE_ADDR__SI regRLC_UCODE_ADDR__SI; -typedef union RLC_UCODE_CNTL regRLC_UCODE_CNTL; -typedef union RLC_UCODE_DATA__SI regRLC_UCODE_DATA__SI; -typedef union RLC_VMID_THREAD1__SI regRLC_VMID_THREAD1__SI; -typedef union RLC_VMID_THREAD2__SI regRLC_VMID_THREAD2__SI; -typedef union RLC_VMID_THREAD3__SI regRLC_VMID_THREAD3__SI; -typedef union RLC_VMID__SI regRLC_VMID__SI; -typedef union ROLLING_WINDOW_CAC_AGGR_LOWER__SI__CI regROLLING_WINDOW_CAC_AGGR_LOWER__SI__CI; -typedef union ROLLING_WINDOW_CAC_AGGR_UPPER__CI regROLLING_WINDOW_CAC_AGGR_UPPER__CI; -typedef union ROLLING_WINDOW_CAC_AGGR_UPPER__SI regROLLING_WINDOW_CAC_AGGR_UPPER__SI; -typedef union ROM_BASE_ADDR regROM_BASE_ADDR; -typedef union ROM_CC_BIF_PINSTRAP__CI__VI regROM_CC_BIF_PINSTRAP__CI__VI; -typedef union ROM_CC_STRAP_PIN_REG0__CI__VI regROM_CC_STRAP_PIN_REG0__CI__VI; -typedef union ROM_CNTL regROM_CNTL; -typedef union ROM_DATA regROM_DATA; -typedef union ROM_INDEX regROM_INDEX; -typedef union ROM_SMC_IND_DATA__CI__VI regROM_SMC_IND_DATA__CI__VI; -typedef union ROM_SMC_IND_INDEX__CI__VI regROM_SMC_IND_INDEX__CI__VI; -typedef union ROM_START regROM_START; -typedef union ROM_STATUS regROM_STATUS; -typedef union ROM_SW_CNTL regROM_SW_CNTL; -typedef union ROM_SW_COMMAND regROM_SW_COMMAND; -typedef union ROM_SW_DATA_1 regROM_SW_DATA_1; -typedef union ROM_SW_DATA_10 regROM_SW_DATA_10; -typedef union ROM_SW_DATA_11 regROM_SW_DATA_11; -typedef union ROM_SW_DATA_12 regROM_SW_DATA_12; -typedef union ROM_SW_DATA_13 regROM_SW_DATA_13; -typedef union ROM_SW_DATA_14 regROM_SW_DATA_14; -typedef union ROM_SW_DATA_15 regROM_SW_DATA_15; -typedef union ROM_SW_DATA_16 regROM_SW_DATA_16; -typedef union ROM_SW_DATA_17 regROM_SW_DATA_17; -typedef union ROM_SW_DATA_18 regROM_SW_DATA_18; -typedef union ROM_SW_DATA_19 regROM_SW_DATA_19; -typedef union ROM_SW_DATA_2 regROM_SW_DATA_2; -typedef union ROM_SW_DATA_20 regROM_SW_DATA_20; -typedef union ROM_SW_DATA_21 regROM_SW_DATA_21; -typedef union ROM_SW_DATA_22 regROM_SW_DATA_22; -typedef union ROM_SW_DATA_23 regROM_SW_DATA_23; -typedef union ROM_SW_DATA_24 regROM_SW_DATA_24; -typedef union ROM_SW_DATA_25 regROM_SW_DATA_25; -typedef union ROM_SW_DATA_26 regROM_SW_DATA_26; -typedef union ROM_SW_DATA_27 regROM_SW_DATA_27; -typedef union ROM_SW_DATA_28 regROM_SW_DATA_28; -typedef union ROM_SW_DATA_29 regROM_SW_DATA_29; -typedef union ROM_SW_DATA_3 regROM_SW_DATA_3; -typedef union ROM_SW_DATA_30 regROM_SW_DATA_30; -typedef union ROM_SW_DATA_31 regROM_SW_DATA_31; -typedef union ROM_SW_DATA_32 regROM_SW_DATA_32; -typedef union ROM_SW_DATA_33 regROM_SW_DATA_33; -typedef union ROM_SW_DATA_34 regROM_SW_DATA_34; -typedef union ROM_SW_DATA_35 regROM_SW_DATA_35; -typedef union ROM_SW_DATA_36 regROM_SW_DATA_36; -typedef union ROM_SW_DATA_37 regROM_SW_DATA_37; -typedef union ROM_SW_DATA_38 regROM_SW_DATA_38; -typedef union ROM_SW_DATA_39 regROM_SW_DATA_39; -typedef union ROM_SW_DATA_4 regROM_SW_DATA_4; -typedef union ROM_SW_DATA_40 regROM_SW_DATA_40; -typedef union ROM_SW_DATA_41 regROM_SW_DATA_41; -typedef union ROM_SW_DATA_42 regROM_SW_DATA_42; -typedef union ROM_SW_DATA_43 regROM_SW_DATA_43; -typedef union ROM_SW_DATA_44 regROM_SW_DATA_44; -typedef union ROM_SW_DATA_45 regROM_SW_DATA_45; -typedef union ROM_SW_DATA_46 regROM_SW_DATA_46; -typedef union ROM_SW_DATA_47 regROM_SW_DATA_47; -typedef union ROM_SW_DATA_48 regROM_SW_DATA_48; -typedef union ROM_SW_DATA_49 regROM_SW_DATA_49; -typedef union ROM_SW_DATA_5 regROM_SW_DATA_5; -typedef union ROM_SW_DATA_50 regROM_SW_DATA_50; -typedef union ROM_SW_DATA_51 regROM_SW_DATA_51; -typedef union ROM_SW_DATA_52 regROM_SW_DATA_52; -typedef union ROM_SW_DATA_53 regROM_SW_DATA_53; -typedef union ROM_SW_DATA_54 regROM_SW_DATA_54; -typedef union ROM_SW_DATA_55 regROM_SW_DATA_55; -typedef union ROM_SW_DATA_56 regROM_SW_DATA_56; -typedef union ROM_SW_DATA_57 regROM_SW_DATA_57; -typedef union ROM_SW_DATA_58 regROM_SW_DATA_58; -typedef union ROM_SW_DATA_59 regROM_SW_DATA_59; -typedef union ROM_SW_DATA_6 regROM_SW_DATA_6; -typedef union ROM_SW_DATA_60 regROM_SW_DATA_60; -typedef union ROM_SW_DATA_61 regROM_SW_DATA_61; -typedef union ROM_SW_DATA_62 regROM_SW_DATA_62; -typedef union ROM_SW_DATA_63 regROM_SW_DATA_63; -typedef union ROM_SW_DATA_64 regROM_SW_DATA_64; -typedef union ROM_SW_DATA_7 regROM_SW_DATA_7; -typedef union ROM_SW_DATA_8 regROM_SW_DATA_8; -typedef union ROM_SW_DATA_9 regROM_SW_DATA_9; -typedef union ROM_SW_STATUS regROM_SW_STATUS; -typedef union S0_S1_VID_DC_SMIO_CNTL regS0_S1_VID_DC_SMIO_CNTL; -typedef union S0_VID_SMIO_CNTL regS0_VID_SMIO_CNTL; -typedef union S1_VID_SMIO_CNTL regS1_VID_SMIO_CNTL; -typedef union SCG_DEBUG_01__SI regSCG_DEBUG_01__SI; -typedef union SCG_DEBUG_02__SI regSCG_DEBUG_02__SI; -typedef union SCG_DEBUG_03__SI regSCG_DEBUG_03__SI; -typedef union SCG_DEBUG_04__SI regSCG_DEBUG_04__SI; -typedef union SCLK_CGTT_BLK_CTRL_REG__SI regSCLK_CGTT_BLK_CTRL_REG__SI; -typedef union SCLK_DCI_SOFT_RESET__SI regSCLK_DCI_SOFT_RESET__SI; -typedef union SCLK_DCO_SOFT_RESET__SI regSCLK_DCO_SOFT_RESET__SI; -typedef union SCLK_DEEP_SLEEP_CNTL2__CI regSCLK_DEEP_SLEEP_CNTL2__CI; -typedef union SCLK_DEEP_SLEEP_CNTL2__VI regSCLK_DEEP_SLEEP_CNTL2__VI; -typedef union SCLK_DEEP_SLEEP_CNTL3__CI__VI regSCLK_DEEP_SLEEP_CNTL3__CI__VI; -typedef union SCLK_DEEP_SLEEP_CNTL__CI__VI regSCLK_DEEP_SLEEP_CNTL__CI__VI; -typedef union SCLK_DEEP_SLEEP_MISC_CNTL__CI__VI regSCLK_DEEP_SLEEP_MISC_CNTL__CI__VI; -typedef union SCLK_MIN_DIV__CI__VI regSCLK_MIN_DIV__CI__VI; -typedef union SCLK_PWRMGT_CNTL__CI__VI regSCLK_PWRMGT_CNTL__CI__VI; -typedef union SCLK_PWRMGT_CNTL__SI regSCLK_PWRMGT_CNTL__SI; -typedef union SCLK_STARTUP_DID__CI__VI regSCLK_STARTUP_DID__CI__VI; -typedef union SCL_ALU_CONTROL__SI regSCL_ALU_CONTROL__SI; -typedef union SCL_AUTOMATIC_MODE_CONTROL__SI regSCL_AUTOMATIC_MODE_CONTROL__SI; -typedef union SCL_BYPASS_CONTROL__SI regSCL_BYPASS_CONTROL__SI; -typedef union SCL_COEFRAM__SI regSCL_COEFRAM__SI; -typedef union SCL_COEF_RAM_CONFLICT_STATUS__SI regSCL_COEF_RAM_CONFLICT_STATUS__SI; -typedef union SCL_COEF_RAM_SELECT__SI regSCL_COEF_RAM_SELECT__SI; -typedef union SCL_COEF_RAM_TAP_DATA__SI regSCL_COEF_RAM_TAP_DATA__SI; -typedef union SCL_CONTROL1__SI regSCL_CONTROL1__SI; -typedef union SCL_CONTROL2__SI regSCL_CONTROL2__SI; -typedef union SCL_CONTROL__SI regSCL_CONTROL__SI; -typedef union SCL_CRC_CURRENT__SI regSCL_CRC_CURRENT__SI; -typedef union SCL_CRC_ENABLE__SI regSCL_CRC_ENABLE__SI; -typedef union SCL_CRC_LAST__SI regSCL_CRC_LAST__SI; -typedef union SCL_CRC_MASK__SI regSCL_CRC_MASK__SI; -typedef union SCL_CRC_SOURCE_SEL__SI regSCL_CRC_SOURCE_SEL__SI; -typedef union SCL_CRTC_INTERFACE__SI regSCL_CRTC_INTERFACE__SI; -typedef union SCL_DEBUG_ID__SI regSCL_DEBUG_ID__SI; -typedef union SCL_DEBUG__SI regSCL_DEBUG__SI; -typedef union SCL_DTMTEST_CNTL__SI regSCL_DTMTEST_CNTL__SI; -typedef union SCL_DTMTEST_CRC_BLUE__SI regSCL_DTMTEST_CRC_BLUE__SI; -typedef union SCL_DTMTEST_CRC_GREEN__SI regSCL_DTMTEST_CRC_GREEN__SI; -typedef union SCL_DTMTEST_CRC_RED__SI regSCL_DTMTEST_CRC_RED__SI; -typedef union SCL_F_SHARP_CONTROL__SI regSCL_F_SHARP_CONTROL__SI; -typedef union SCL_HFILT_COEF__SI regSCL_HFILT_COEF__SI; -typedef union SCL_HFILT_IO__SI regSCL_HFILT_IO__SI; -typedef union SCL_HIGH_PASS_FILTER_CONTROL__SI regSCL_HIGH_PASS_FILTER_CONTROL__SI; -typedef union SCL_HORZ_FILTER_CONTROL__SI regSCL_HORZ_FILTER_CONTROL__SI; -typedef union SCL_HORZ_FILTER_INIT_CHROMA__SI regSCL_HORZ_FILTER_INIT_CHROMA__SI; -typedef union SCL_HORZ_FILTER_INIT_RGB_LUMA__SI regSCL_HORZ_FILTER_INIT_RGB_LUMA__SI; -typedef union SCL_HORZ_FILTER_SCALE_RATIO__SI regSCL_HORZ_FILTER_SCALE_RATIO__SI; -typedef union SCL_H_COUNTERS__SI regSCL_H_COUNTERS__SI; -typedef union SCL_LB_INTERFACE__SI regSCL_LB_INTERFACE__SI; -typedef union SCL_LOW_PASS_FILTER_CONTROL__SI regSCL_LOW_PASS_FILTER_CONTROL__SI; -typedef union SCL_MANUAL_REPLICATE_CONTROL__SI regSCL_MANUAL_REPLICATE_CONTROL__SI; -typedef union SCL_MODE_CHANGE_DET1__SI regSCL_MODE_CHANGE_DET1__SI; -typedef union SCL_MODE_CHANGE_DET2__SI regSCL_MODE_CHANGE_DET2__SI; -typedef union SCL_MODE_CHANGE_DET3__SI regSCL_MODE_CHANGE_DET3__SI; -typedef union SCL_MODE_CHANGE_MASK__SI regSCL_MODE_CHANGE_MASK__SI; -typedef union SCL_ONE_SHOT_WATERMARK__SI regSCL_ONE_SHOT_WATERMARK__SI; -typedef union SCL_RBBMIF_RDWR_TIMEOUT__SI regSCL_RBBMIF_RDWR_TIMEOUT__SI; -typedef union SCL_READBBUF_IO__SI regSCL_READBBUF_IO__SI; -typedef union SCL_SCALER_ENABLE__SI regSCL_SCALER_ENABLE__SI; -typedef union SCL_TAP_CONTROL__SI regSCL_TAP_CONTROL__SI; -typedef union SCL_TEST_DEBUG_DATA__SI regSCL_TEST_DEBUG_DATA__SI; -typedef union SCL_TEST_DEBUG_INDEX__SI regSCL_TEST_DEBUG_INDEX__SI; -typedef union SCL_UNDERFLOW_STATUS__SI regSCL_UNDERFLOW_STATUS__SI; -typedef union SCL_UPDATE__SI regSCL_UPDATE__SI; -typedef union SCL_VERT_FILTER_CONTROL__SI regSCL_VERT_FILTER_CONTROL__SI; -typedef union SCL_VERT_FILTER_INIT_BOT__SI regSCL_VERT_FILTER_INIT_BOT__SI; -typedef union SCL_VERT_FILTER_INIT__SI regSCL_VERT_FILTER_INIT__SI; -typedef union SCL_VERT_FILTER_SCALE_RATIO__SI regSCL_VERT_FILTER_SCALE_RATIO__SI; -typedef union SCL_VFILT_COEF__SI regSCL_VFILT_COEF__SI; -typedef union SCL_VFILT_IO__SI regSCL_VFILT_IO__SI; -typedef union SCL_V_COUNTERS__SI regSCL_V_COUNTERS__SI; -typedef union SCRATCH_ADDR__CI__VI regSCRATCH_ADDR__CI__VI; -typedef union SCRATCH_ADDR__SI regSCRATCH_ADDR__SI; -typedef union SCRATCH_REG0 regSCRATCH_REG0; -typedef union SCRATCH_REG1 regSCRATCH_REG1; -typedef union SCRATCH_REG2 regSCRATCH_REG2; -typedef union SCRATCH_REG3 regSCRATCH_REG3; -typedef union SCRATCH_REG4 regSCRATCH_REG4; -typedef union SCRATCH_REG5 regSCRATCH_REG5; -typedef union SCRATCH_REG6 regSCRATCH_REG6; -typedef union SCRATCH_REG7 regSCRATCH_REG7; -typedef union SCRATCH_UMSK__CI__VI regSCRATCH_UMSK__CI__VI; -typedef union SCRATCH_UMSK__SI regSCRATCH_UMSK__SI; -typedef union SD1_CC_EDS_LEVEL_CNTL__SI regSD1_CC_EDS_LEVEL_CNTL__SI; -typedef union SD1_CHROMA_MOD_CNTL__SI regSD1_CHROMA_MOD_CNTL__SI; -typedef union SD1_CHROMA_OFFSET__SI regSD1_CHROMA_OFFSET__SI; -typedef union SD1_COL_SC_DENOMIN__SI regSD1_COL_SC_DENOMIN__SI; -typedef union SD1_COL_SC_INC_CORR__SI regSD1_COL_SC_INC_CORR__SI; -typedef union SD1_COL_SC_INC__SI regSD1_COL_SC_INC__SI; -typedef union SD1_COL_SC_PHASE_CNTL__SI regSD1_COL_SC_PHASE_CNTL__SI; -typedef union SD1_CRC_CNTL__SI regSD1_CRC_CNTL__SI; -typedef union SD1_CRTC_HV_START__SI regSD1_CRTC_HV_START__SI; -typedef union SD1_CRTC_TV_FRAMESTART_CNTL__SI regSD1_CRTC_TV_FRAMESTART_CNTL__SI; -typedef union SD1_FORCE_DAC_DATA__SI regSD1_FORCE_DAC_DATA__SI; -typedef union SD1_LUMA_BLANK_SETUP_LEVELS__SI regSD1_LUMA_BLANK_SETUP_LEVELS__SI; -typedef union SD1_LUMA_COMB_FILT_CNTL1__SI regSD1_LUMA_COMB_FILT_CNTL1__SI; -typedef union SD1_LUMA_COMB_FILT_CNTL2__SI regSD1_LUMA_COMB_FILT_CNTL2__SI; -typedef union SD1_LUMA_COMB_FILT_CNTL3__SI regSD1_LUMA_COMB_FILT_CNTL3__SI; -typedef union SD1_LUMA_COMB_FILT_CNTL4__SI regSD1_LUMA_COMB_FILT_CNTL4__SI; -typedef union SD1_LUMA_FILT_CNTL__SI regSD1_LUMA_FILT_CNTL__SI; -typedef union SD1_LUMA_OFFSET_LIMIT__SI regSD1_LUMA_OFFSET_LIMIT__SI; -typedef union SD1_LUMA_SYNC_TIP_LEVELS__SI regSD1_LUMA_SYNC_TIP_LEVELS__SI; -typedef union SD1_MAIN_CNTL2__SI regSD1_MAIN_CNTL2__SI; -typedef union SD1_MAIN_CNTL__SI regSD1_MAIN_CNTL__SI; -typedef union SD1_MV_AGC_CNTL__SI regSD1_MV_AGC_CNTL__SI; -typedef union SD1_MV_AGC_MAX_LEVELS__SI regSD1_MV_AGC_MAX_LEVELS__SI; -typedef union SD1_MV_AGC_PAL_A_B_LEVELS__SI regSD1_MV_AGC_PAL_A_B_LEVELS__SI; -typedef union SD1_MV_BLANK_SETUP_LEVELS__SI regSD1_MV_BLANK_SETUP_LEVELS__SI; -typedef union SD1_MV_BP_LEVEL__SI regSD1_MV_BP_LEVEL__SI; -typedef union SD1_MV_N0_CONTROL__SI regSD1_MV_N0_CONTROL__SI; -typedef union SD1_MV_N10_PS_AGC__SI regSD1_MV_N10_PS_AGC__SI; -typedef union SD1_MV_N11_N12_PS_AGC__SI regSD1_MV_N11_N12_PS_AGC__SI; -typedef union SD1_MV_N13_N14_PS_AGC_H_EN__SI regSD1_MV_N13_N14_PS_AGC_H_EN__SI; -typedef union SD1_MV_N15_BP_TIMING__SI regSD1_MV_N15_BP_TIMING__SI; -typedef union SD1_MV_N16_CS_H_TIMING__SI regSD1_MV_N16_CS_H_TIMING__SI; -typedef union SD1_MV_N17_TO_N19_CS__SI regSD1_MV_N17_TO_N19_CS__SI; -typedef union SD1_MV_N1_TO_N3_CS__SI regSD1_MV_N1_TO_N3_CS__SI; -typedef union SD1_MV_N20_TO_N22_CS_RGB__SI regSD1_MV_N20_TO_N22_CS_RGB__SI; -typedef union SD1_MV_N4_TO_N7_CS__SI regSD1_MV_N4_TO_N7_CS__SI; -typedef union SD1_MV_N8_PS_AGC__SI regSD1_MV_N8_PS_AGC__SI; -typedef union SD1_MV_N9_PS_AGC__SI regSD1_MV_N9_PS_AGC__SI; -typedef union SD1_MV_TIMING_INTERNAL_INIT__SI regSD1_MV_TIMING_INTERNAL_INIT__SI; -typedef union SD1_MV_V_PS_AGC_TIMING__SI regSD1_MV_V_PS_AGC_TIMING__SI; -typedef union SD1_MV_V_REDUCE_SYNC_ENDS__SI regSD1_MV_V_REDUCE_SYNC_ENDS__SI; -typedef union SD1_RGB_OR_PBPR_BLANK_LEVEL__SI regSD1_RGB_OR_PBPR_BLANK_LEVEL__SI; -typedef union SD1_SCM_COL_SC_DENOMIN__SI regSD1_SCM_COL_SC_DENOMIN__SI; -typedef union SD1_SCM_COL_SC_INC_CORR__SI regSD1_SCM_COL_SC_INC_CORR__SI; -typedef union SD1_SCM_COL_SC_INC__SI regSD1_SCM_COL_SC_INC__SI; -typedef union SD1_SCM_DB_DR_SCALE_FACTORS__SI regSD1_SCM_DB_DR_SCALE_FACTORS__SI; -typedef union SD1_SCM_MAX_DTO_SWING__SI regSD1_SCM_MAX_DTO_SWING__SI; -typedef union SD1_SCM_MIN_DTO_SWING__SI regSD1_SCM_MIN_DTO_SWING__SI; -typedef union SD1_SCM_MOD_CNTL__SI regSD1_SCM_MOD_CNTL__SI; -typedef union SD1_SDTV0_DEBUG__SI regSD1_SDTV0_DEBUG__SI; -typedef union SD1_TIMING_H_134BIT__SI regSD1_TIMING_H_134BIT__SI; -typedef union SD1_TIMING_H_20BIT__SI regSD1_TIMING_H_20BIT__SI; -typedef union SD1_TIMING_H_ACTIVE_FILT_WINDOW1__SI regSD1_TIMING_H_ACTIVE_FILT_WINDOW1__SI; -typedef union SD1_TIMING_H_ACTIVE_FILT_WINDOW2__SI regSD1_TIMING_H_ACTIVE_FILT_WINDOW2__SI; -typedef union SD1_TIMING_H_ADV_ACTIVE__SI regSD1_TIMING_H_ADV_ACTIVE__SI; -typedef union SD1_TIMING_H_ADV_VBI_PASSTHRU__SI regSD1_TIMING_H_ADV_VBI_PASSTHRU__SI; -typedef union SD1_TIMING_H_BURST__SI regSD1_TIMING_H_BURST__SI; -typedef union SD1_TIMING_H_CC_EDS__SI regSD1_TIMING_H_CC_EDS__SI; -typedef union SD1_TIMING_H_COUNT_INIT__SI regSD1_TIMING_H_COUNT_INIT__SI; -typedef union SD1_TIMING_H_COUNT__SI regSD1_TIMING_H_COUNT__SI; -typedef union SD1_TIMING_H_EQUALIZATION1__SI regSD1_TIMING_H_EQUALIZATION1__SI; -typedef union SD1_TIMING_H_EQUALIZATION2__SI regSD1_TIMING_H_EQUALIZATION2__SI; -typedef union SD1_TIMING_H_HSYNC__SI regSD1_TIMING_H_HSYNC__SI; -typedef union SD1_TIMING_H_RUNIN_FILT_WINDOW__SI regSD1_TIMING_H_RUNIN_FILT_WINDOW__SI; -typedef union SD1_TIMING_H_SERATION1__SI regSD1_TIMING_H_SERATION1__SI; -typedef union SD1_TIMING_H_SERATION2__SI regSD1_TIMING_H_SERATION2__SI; -typedef union SD1_TIMING_H_SETUP1__SI regSD1_TIMING_H_SETUP1__SI; -typedef union SD1_TIMING_H_SETUP2__SI regSD1_TIMING_H_SETUP2__SI; -typedef union SD1_TIMING_H_TOTAL__SI regSD1_TIMING_H_TOTAL__SI; -typedef union SD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW__SI - regSD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW__SI; -typedef union SD1_TIMING_H_VBI_PASSTHRU__SI regSD1_TIMING_H_VBI_PASSTHRU__SI; -typedef union SD1_TIMING_H_WSS__SI regSD1_TIMING_H_WSS__SI; -typedef union SD1_TIMING_INTERNAL_INIT__SI regSD1_TIMING_INTERNAL_INIT__SI; -typedef union SD1_TIMING_V_134BIT__SI regSD1_TIMING_V_134BIT__SI; -typedef union SD1_TIMING_V_20BIT__SI regSD1_TIMING_V_20BIT__SI; -typedef union SD1_TIMING_V_ACTIVE1__SI regSD1_TIMING_V_ACTIVE1__SI; -typedef union SD1_TIMING_V_ACTIVE2__SI regSD1_TIMING_V_ACTIVE2__SI; -typedef union SD1_TIMING_V_BURST1__SI regSD1_TIMING_V_BURST1__SI; -typedef union SD1_TIMING_V_BURST2__SI regSD1_TIMING_V_BURST2__SI; -typedef union SD1_TIMING_V_CC_EDS__SI regSD1_TIMING_V_CC_EDS__SI; -typedef union SD1_TIMING_V_EQUALIZATION1__SI regSD1_TIMING_V_EQUALIZATION1__SI; -typedef union SD1_TIMING_V_EQUALIZATION2__SI regSD1_TIMING_V_EQUALIZATION2__SI; -typedef union SD1_TIMING_V_F_COUNT_INIT__SI regSD1_TIMING_V_F_COUNT_INIT__SI; -typedef union SD1_TIMING_V_F_COUNT__SI regSD1_TIMING_V_F_COUNT__SI; -typedef union SD1_TIMING_V_F_TOTAL__SI regSD1_TIMING_V_F_TOTAL__SI; -typedef union SD1_TIMING_V_SERATION1__SI regSD1_TIMING_V_SERATION1__SI; -typedef union SD1_TIMING_V_SERATION2__SI regSD1_TIMING_V_SERATION2__SI; -typedef union SD1_TIMING_V_SETUP1__SI regSD1_TIMING_V_SETUP1__SI; -typedef union SD1_TIMING_V_SETUP2__SI regSD1_TIMING_V_SETUP2__SI; -typedef union SD1_TIMING_V_VBI_PASSTHRU1__SI regSD1_TIMING_V_VBI_PASSTHRU1__SI; -typedef union SD1_TIMING_V_VBI_PASSTHRU2__SI regSD1_TIMING_V_VBI_PASSTHRU2__SI; -typedef union SD1_TIMING_V_WSS__SI regSD1_TIMING_V_WSS__SI; -typedef union SD1_TV_SOURCE_CONTROL__SI regSD1_TV_SOURCE_CONTROL__SI; -typedef union SD1_UPSAMPLE_MODE__SI regSD1_UPSAMPLE_MODE__SI; -typedef union SD1_U_AND_V_GAIN_SETTINGS__SI regSD1_U_AND_V_GAIN_SETTINGS__SI; -typedef union SD1_U_V_BREAK_POINT_SETTINGS__SI regSD1_U_V_BREAK_POINT_SETTINGS__SI; -typedef union SD1_VBI_134BIT_CNTL__SI regSD1_VBI_134BIT_CNTL__SI; -typedef union SD1_VBI_134BIT_DTO_CNTL__SI regSD1_VBI_134BIT_DTO_CNTL__SI; -typedef union SD1_VBI_134BIT_H_DATA__SI regSD1_VBI_134BIT_H_DATA__SI; -typedef union SD1_VBI_134BIT_NULL_PACKET_CNTL__SI regSD1_VBI_134BIT_NULL_PACKET_CNTL__SI; -typedef union SD1_VBI_134BIT_P_DATA0__SI regSD1_VBI_134BIT_P_DATA0__SI; -typedef union SD1_VBI_134BIT_P_DATA1__SI regSD1_VBI_134BIT_P_DATA1__SI; -typedef union SD1_VBI_134BIT_P_DATA2__SI regSD1_VBI_134BIT_P_DATA2__SI; -typedef union SD1_VBI_134BIT_P_DATA3__SI regSD1_VBI_134BIT_P_DATA3__SI; -typedef union SD1_VBI_20BIT_CNTL__SI regSD1_VBI_20BIT_CNTL__SI; -typedef union SD1_VBI_20BIT_DTO_CNTL__SI regSD1_VBI_20BIT_DTO_CNTL__SI; -typedef union SD1_VBI_20BIT_NULL_PACKET_CNTL__SI regSD1_VBI_20BIT_NULL_PACKET_CNTL__SI; -typedef union SD1_VBI_CC_CNTL__SI regSD1_VBI_CC_CNTL__SI; -typedef union SD1_VBI_CC_EDS_DTO_CNTL__SI regSD1_VBI_CC_EDS_DTO_CNTL__SI; -typedef union SD1_VBI_EDS_CNTL__SI regSD1_VBI_EDS_CNTL__SI; -typedef union SD1_VBI_LEVEL_CNTL__SI regSD1_VBI_LEVEL_CNTL__SI; -typedef union SD1_VBI_RUNIN_GAIN_CNTL__SI regSD1_VBI_RUNIN_GAIN_CNTL__SI; -typedef union SD1_VBI_WSS_CNTL__SI regSD1_VBI_WSS_CNTL__SI; -typedef union SD1_VBI_WSS_DTO_CNTL__SI regSD1_VBI_WSS_DTO_CNTL__SI; -typedef union SD1_VIDEO_PORT_SIG__SI regSD1_VIDEO_PORT_SIG__SI; -typedef union SD1_VIDOUT_MUX_CNTL__SI regSD1_VIDOUT_MUX_CNTL__SI; -typedef union SD1_Y_AND_PASSTHRU_GAIN_SETTINGS__SI regSD1_Y_AND_PASSTHRU_GAIN_SETTINGS__SI; -typedef union SD1_Y_BREAK_POINT_SETTING__SI regSD1_Y_BREAK_POINT_SETTING__SI; -typedef union SDMA0_CHICKEN_BITS__CI__VI regSDMA0_CHICKEN_BITS__CI__VI; -typedef union SDMA0_CLK_CTRL__CI__VI regSDMA0_CLK_CTRL__CI__VI; -typedef union SDMA0_CNTL__CI regSDMA0_CNTL__CI; -typedef union SDMA0_CNTL__VI regSDMA0_CNTL__VI; -typedef union SDMA0_F32_CNTL__CI__VI regSDMA0_F32_CNTL__CI__VI; -typedef union SDMA0_FREEZE__CI__VI regSDMA0_FREEZE__CI__VI; -typedef union SDMA0_GFX_APE1_CNTL__CI__VI regSDMA0_GFX_APE1_CNTL__CI__VI; -typedef union SDMA0_GFX_CONTEXT_CNTL__CI__VI regSDMA0_GFX_CONTEXT_CNTL__CI__VI; -typedef union SDMA0_GFX_CONTEXT_STATUS__CI__VI regSDMA0_GFX_CONTEXT_STATUS__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERDATA0__CI__VI regSDMA0_GFX_DRM_COUNTERDATA0__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERDATA1__CI__VI regSDMA0_GFX_DRM_COUNTERDATA1__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERDATA2__CI__VI regSDMA0_GFX_DRM_COUNTERDATA2__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERDATA3__CI__VI regSDMA0_GFX_DRM_COUNTERDATA3__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERKEY0__CI__VI regSDMA0_GFX_DRM_COUNTERKEY0__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERKEY1__CI__VI regSDMA0_GFX_DRM_COUNTERKEY1__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERKEY2__CI__VI regSDMA0_GFX_DRM_COUNTERKEY2__CI__VI; -typedef union SDMA0_GFX_DRM_COUNTERKEY3__CI__VI regSDMA0_GFX_DRM_COUNTERKEY3__CI__VI; -typedef union SDMA0_GFX_DRM_IVLOAD0__CI__VI regSDMA0_GFX_DRM_IVLOAD0__CI__VI; -typedef union SDMA0_GFX_DRM_IVLOAD1__CI__VI regSDMA0_GFX_DRM_IVLOAD1__CI__VI; -typedef union SDMA0_GFX_DRM_IVLOAD2__CI__VI regSDMA0_GFX_DRM_IVLOAD2__CI__VI; -typedef union SDMA0_GFX_DRM_IVLOAD3__CI__VI regSDMA0_GFX_DRM_IVLOAD3__CI__VI; -typedef union SDMA0_GFX_DRM_IVLOAD4__CI__VI regSDMA0_GFX_DRM_IVLOAD4__CI__VI; -typedef union SDMA0_GFX_DRM_OFFSET__CI__VI regSDMA0_GFX_DRM_OFFSET__CI__VI; -typedef union SDMA0_GFX_DRM_UNROLLKEY__CI__VI regSDMA0_GFX_DRM_UNROLLKEY__CI__VI; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY0__CI__VI regSDMA0_GFX_DRM_WRAPPEDKEY0__CI__VI; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY1__CI__VI regSDMA0_GFX_DRM_WRAPPEDKEY1__CI__VI; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY2__CI__VI regSDMA0_GFX_DRM_WRAPPEDKEY2__CI__VI; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY3__CI__VI regSDMA0_GFX_DRM_WRAPPEDKEY3__CI__VI; -typedef union SDMA0_GFX_IB_BASE_HI__CI__VI regSDMA0_GFX_IB_BASE_HI__CI__VI; -typedef union SDMA0_GFX_IB_BASE_LO__CI__VI regSDMA0_GFX_IB_BASE_LO__CI__VI; -typedef union SDMA0_GFX_IB_CNTL__CI__VI regSDMA0_GFX_IB_CNTL__CI__VI; -typedef union SDMA0_GFX_IB_OFFSET__CI__VI regSDMA0_GFX_IB_OFFSET__CI__VI; -typedef union SDMA0_GFX_IB_RPTR__CI__VI regSDMA0_GFX_IB_RPTR__CI__VI; -typedef union SDMA0_GFX_IB_SIZE__CI__VI regSDMA0_GFX_IB_SIZE__CI__VI; -typedef union SDMA0_GFX_RB_BASE_HI__CI__VI regSDMA0_GFX_RB_BASE_HI__CI__VI; -typedef union SDMA0_GFX_RB_BASE__CI__VI regSDMA0_GFX_RB_BASE__CI__VI; -typedef union SDMA0_GFX_RB_CNTL__CI__VI regSDMA0_GFX_RB_CNTL__CI__VI; -typedef union SDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI regSDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI; -typedef union SDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI regSDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI; -typedef union SDMA0_GFX_RB_RPTR__CI__VI regSDMA0_GFX_RB_RPTR__CI__VI; -typedef union SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI; -typedef union SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI; -typedef union SDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI regSDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI; -typedef union SDMA0_GFX_RB_WPTR__CI__VI regSDMA0_GFX_RB_WPTR__CI__VI; -typedef union SDMA0_GFX_SKIP_CNTL__CI__VI regSDMA0_GFX_SKIP_CNTL__CI__VI; -typedef union SDMA0_GFX_VIRTUAL_ADDR__CI__VI regSDMA0_GFX_VIRTUAL_ADDR__CI__VI; -typedef union SDMA0_HASH__CI__VI regSDMA0_HASH__CI__VI; -typedef union SDMA0_IB_OFFSET_FETCH__CI__VI regSDMA0_IB_OFFSET_FETCH__CI__VI; -typedef union SDMA0_PERFCOUNTER0_RESULT__CI__VI regSDMA0_PERFCOUNTER0_RESULT__CI__VI; -typedef union SDMA0_PERFCOUNTER1_RESULT__CI__VI regSDMA0_PERFCOUNTER1_RESULT__CI__VI; -typedef union SDMA0_PERFMON_CNTL__CI__VI regSDMA0_PERFMON_CNTL__CI__VI; -typedef union SDMA0_PHASE0_QUANTUM__CI__VI regSDMA0_PHASE0_QUANTUM__CI__VI; -typedef union SDMA0_PHASE1_QUANTUM__CI__VI regSDMA0_PHASE1_QUANTUM__CI__VI; -typedef union SDMA0_POWER_CNTL__CI__VI regSDMA0_POWER_CNTL__CI__VI; -typedef union SDMA0_PROGRAM__CI__VI regSDMA0_PROGRAM__CI__VI; -typedef union SDMA0_RB_RPTR_FETCH__CI__VI regSDMA0_RB_RPTR_FETCH__CI__VI; -typedef union SDMA0_RLC0_APE1_CNTL__CI__VI regSDMA0_RLC0_APE1_CNTL__CI__VI; -typedef union SDMA0_RLC0_CONTEXT_STATUS__CI__VI regSDMA0_RLC0_CONTEXT_STATUS__CI__VI; -typedef union SDMA0_RLC0_DOORBELL_LOG__CI__VI regSDMA0_RLC0_DOORBELL_LOG__CI__VI; -typedef union SDMA0_RLC0_DOORBELL__CI__VI regSDMA0_RLC0_DOORBELL__CI__VI; -typedef union SDMA0_RLC0_IB_BASE_HI__CI__VI regSDMA0_RLC0_IB_BASE_HI__CI__VI; -typedef union SDMA0_RLC0_IB_BASE_LO__CI__VI regSDMA0_RLC0_IB_BASE_LO__CI__VI; -typedef union SDMA0_RLC0_IB_CNTL__CI__VI regSDMA0_RLC0_IB_CNTL__CI__VI; -typedef union SDMA0_RLC0_IB_OFFSET__CI__VI regSDMA0_RLC0_IB_OFFSET__CI__VI; -typedef union SDMA0_RLC0_IB_RPTR__CI__VI regSDMA0_RLC0_IB_RPTR__CI__VI; -typedef union SDMA0_RLC0_IB_SIZE__CI__VI regSDMA0_RLC0_IB_SIZE__CI__VI; -typedef union SDMA0_RLC0_RB_BASE_HI__CI__VI regSDMA0_RLC0_RB_BASE_HI__CI__VI; -typedef union SDMA0_RLC0_RB_BASE__CI__VI regSDMA0_RLC0_RB_BASE__CI__VI; -typedef union SDMA0_RLC0_RB_CNTL__CI__VI regSDMA0_RLC0_RB_CNTL__CI__VI; -typedef union SDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI regSDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI; -typedef union SDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI regSDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI; -typedef union SDMA0_RLC0_RB_RPTR__CI__VI regSDMA0_RLC0_RB_RPTR__CI__VI; -typedef union SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI; -typedef union SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI; -typedef union SDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI regSDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI; -typedef union SDMA0_RLC0_RB_WPTR__CI__VI regSDMA0_RLC0_RB_WPTR__CI__VI; -typedef union SDMA0_RLC0_SKIP_CNTL__CI__VI regSDMA0_RLC0_SKIP_CNTL__CI__VI; -typedef union SDMA0_RLC0_VIRTUAL_ADDR__CI__VI regSDMA0_RLC0_VIRTUAL_ADDR__CI__VI; -typedef union SDMA0_RLC1_APE1_CNTL__CI__VI regSDMA0_RLC1_APE1_CNTL__CI__VI; -typedef union SDMA0_RLC1_CONTEXT_STATUS__CI__VI regSDMA0_RLC1_CONTEXT_STATUS__CI__VI; -typedef union SDMA0_RLC1_DOORBELL_LOG__CI__VI regSDMA0_RLC1_DOORBELL_LOG__CI__VI; -typedef union SDMA0_RLC1_DOORBELL__CI__VI regSDMA0_RLC1_DOORBELL__CI__VI; -typedef union SDMA0_RLC1_IB_BASE_HI__CI__VI regSDMA0_RLC1_IB_BASE_HI__CI__VI; -typedef union SDMA0_RLC1_IB_BASE_LO__CI__VI regSDMA0_RLC1_IB_BASE_LO__CI__VI; -typedef union SDMA0_RLC1_IB_CNTL__CI__VI regSDMA0_RLC1_IB_CNTL__CI__VI; -typedef union SDMA0_RLC1_IB_OFFSET__CI__VI regSDMA0_RLC1_IB_OFFSET__CI__VI; -typedef union SDMA0_RLC1_IB_RPTR__CI__VI regSDMA0_RLC1_IB_RPTR__CI__VI; -typedef union SDMA0_RLC1_IB_SIZE__CI__VI regSDMA0_RLC1_IB_SIZE__CI__VI; -typedef union SDMA0_RLC1_RB_BASE_HI__CI__VI regSDMA0_RLC1_RB_BASE_HI__CI__VI; -typedef union SDMA0_RLC1_RB_BASE__CI__VI regSDMA0_RLC1_RB_BASE__CI__VI; -typedef union SDMA0_RLC1_RB_CNTL__CI__VI regSDMA0_RLC1_RB_CNTL__CI__VI; -typedef union SDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI regSDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI; -typedef union SDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI regSDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI; -typedef union SDMA0_RLC1_RB_RPTR__CI__VI regSDMA0_RLC1_RB_RPTR__CI__VI; -typedef union SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI; -typedef union SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI; -typedef union SDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI regSDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI; -typedef union SDMA0_RLC1_RB_WPTR__CI__VI regSDMA0_RLC1_RB_WPTR__CI__VI; -typedef union SDMA0_RLC1_SKIP_CNTL__CI__VI regSDMA0_RLC1_SKIP_CNTL__CI__VI; -typedef union SDMA0_RLC1_VIRTUAL_ADDR__CI__VI regSDMA0_RLC1_VIRTUAL_ADDR__CI__VI; -typedef union SDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI regSDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI; -typedef union SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI; -typedef union SDMA0_STATUS1_REG__CI__VI regSDMA0_STATUS1_REG__CI__VI; -typedef union SDMA0_STATUS_REG__CI regSDMA0_STATUS_REG__CI; -typedef union SDMA0_STATUS_REG__VI regSDMA0_STATUS_REG__VI; -typedef union SDMA0_TILING_CONFIG__CI__VI regSDMA0_TILING_CONFIG__CI__VI; -typedef union SDMA0_UCODE_ADDR__CI__VI regSDMA0_UCODE_ADDR__CI__VI; -typedef union SDMA0_UCODE_DATA__CI__VI regSDMA0_UCODE_DATA__CI__VI; -typedef union SDMA1_CHICKEN_BITS__CI__VI regSDMA1_CHICKEN_BITS__CI__VI; -typedef union SDMA1_CLK_CTRL__CI__VI regSDMA1_CLK_CTRL__CI__VI; -typedef union SDMA1_CNTL__CI regSDMA1_CNTL__CI; -typedef union SDMA1_CNTL__VI regSDMA1_CNTL__VI; -typedef union SDMA1_CONFIG__CI regSDMA1_CONFIG__CI; -typedef union SDMA1_F32_CNTL__CI__VI regSDMA1_F32_CNTL__CI__VI; -typedef union SDMA1_FREEZE__CI__VI regSDMA1_FREEZE__CI__VI; -typedef union SDMA1_GFX_APE1_CNTL__CI__VI regSDMA1_GFX_APE1_CNTL__CI__VI; -typedef union SDMA1_GFX_CONTEXT_CNTL__CI__VI regSDMA1_GFX_CONTEXT_CNTL__CI__VI; -typedef union SDMA1_GFX_CONTEXT_STATUS__CI__VI regSDMA1_GFX_CONTEXT_STATUS__CI__VI; -typedef union SDMA1_GFX_IB_BASE_HI__CI__VI regSDMA1_GFX_IB_BASE_HI__CI__VI; -typedef union SDMA1_GFX_IB_BASE_LO__CI__VI regSDMA1_GFX_IB_BASE_LO__CI__VI; -typedef union SDMA1_GFX_IB_CNTL__CI__VI regSDMA1_GFX_IB_CNTL__CI__VI; -typedef union SDMA1_GFX_IB_OFFSET__CI__VI regSDMA1_GFX_IB_OFFSET__CI__VI; -typedef union SDMA1_GFX_IB_RPTR__CI__VI regSDMA1_GFX_IB_RPTR__CI__VI; -typedef union SDMA1_GFX_IB_SIZE__CI__VI regSDMA1_GFX_IB_SIZE__CI__VI; -typedef union SDMA1_GFX_RB_BASE_HI__CI__VI regSDMA1_GFX_RB_BASE_HI__CI__VI; -typedef union SDMA1_GFX_RB_BASE__CI__VI regSDMA1_GFX_RB_BASE__CI__VI; -typedef union SDMA1_GFX_RB_CNTL__CI__VI regSDMA1_GFX_RB_CNTL__CI__VI; -typedef union SDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI regSDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI; -typedef union SDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI regSDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI; -typedef union SDMA1_GFX_RB_RPTR__CI__VI regSDMA1_GFX_RB_RPTR__CI__VI; -typedef union SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI; -typedef union SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI; -typedef union SDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI regSDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI; -typedef union SDMA1_GFX_RB_WPTR__CI__VI regSDMA1_GFX_RB_WPTR__CI__VI; -typedef union SDMA1_GFX_SKIP_CNTL__CI__VI regSDMA1_GFX_SKIP_CNTL__CI__VI; -typedef union SDMA1_GFX_VIRTUAL_ADDR__CI__VI regSDMA1_GFX_VIRTUAL_ADDR__CI__VI; -typedef union SDMA1_HASH__CI__VI regSDMA1_HASH__CI__VI; -typedef union SDMA1_IB_OFFSET_FETCH__CI__VI regSDMA1_IB_OFFSET_FETCH__CI__VI; -typedef union SDMA1_PERFCOUNTER0_RESULT__CI__VI regSDMA1_PERFCOUNTER0_RESULT__CI__VI; -typedef union SDMA1_PERFCOUNTER1_RESULT__CI__VI regSDMA1_PERFCOUNTER1_RESULT__CI__VI; -typedef union SDMA1_PERFMON_CNTL__CI__VI regSDMA1_PERFMON_CNTL__CI__VI; -typedef union SDMA1_PHASE0_QUANTUM__CI__VI regSDMA1_PHASE0_QUANTUM__CI__VI; -typedef union SDMA1_PHASE1_QUANTUM__CI__VI regSDMA1_PHASE1_QUANTUM__CI__VI; -typedef union SDMA1_POWER_CNTL__CI__VI regSDMA1_POWER_CNTL__CI__VI; -typedef union SDMA1_PROGRAM__CI__VI regSDMA1_PROGRAM__CI__VI; -typedef union SDMA1_RB_RPTR_FETCH__CI__VI regSDMA1_RB_RPTR_FETCH__CI__VI; -typedef union SDMA1_RLC0_APE1_CNTL__CI__VI regSDMA1_RLC0_APE1_CNTL__CI__VI; -typedef union SDMA1_RLC0_CONTEXT_STATUS__CI__VI regSDMA1_RLC0_CONTEXT_STATUS__CI__VI; -typedef union SDMA1_RLC0_DOORBELL_LOG__CI__VI regSDMA1_RLC0_DOORBELL_LOG__CI__VI; -typedef union SDMA1_RLC0_DOORBELL__CI__VI regSDMA1_RLC0_DOORBELL__CI__VI; -typedef union SDMA1_RLC0_IB_BASE_HI__CI__VI regSDMA1_RLC0_IB_BASE_HI__CI__VI; -typedef union SDMA1_RLC0_IB_BASE_LO__CI__VI regSDMA1_RLC0_IB_BASE_LO__CI__VI; -typedef union SDMA1_RLC0_IB_CNTL__CI__VI regSDMA1_RLC0_IB_CNTL__CI__VI; -typedef union SDMA1_RLC0_IB_OFFSET__CI__VI regSDMA1_RLC0_IB_OFFSET__CI__VI; -typedef union SDMA1_RLC0_IB_RPTR__CI__VI regSDMA1_RLC0_IB_RPTR__CI__VI; -typedef union SDMA1_RLC0_IB_SIZE__CI__VI regSDMA1_RLC0_IB_SIZE__CI__VI; -typedef union SDMA1_RLC0_RB_BASE_HI__CI__VI regSDMA1_RLC0_RB_BASE_HI__CI__VI; -typedef union SDMA1_RLC0_RB_BASE__CI__VI regSDMA1_RLC0_RB_BASE__CI__VI; -typedef union SDMA1_RLC0_RB_CNTL__CI__VI regSDMA1_RLC0_RB_CNTL__CI__VI; -typedef union SDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI regSDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI; -typedef union SDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI regSDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI; -typedef union SDMA1_RLC0_RB_RPTR__CI__VI regSDMA1_RLC0_RB_RPTR__CI__VI; -typedef union SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI; -typedef union SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI; -typedef union SDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI regSDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI; -typedef union SDMA1_RLC0_RB_WPTR__CI__VI regSDMA1_RLC0_RB_WPTR__CI__VI; -typedef union SDMA1_RLC0_SKIP_CNTL__CI__VI regSDMA1_RLC0_SKIP_CNTL__CI__VI; -typedef union SDMA1_RLC0_VIRTUAL_ADDR__CI__VI regSDMA1_RLC0_VIRTUAL_ADDR__CI__VI; -typedef union SDMA1_RLC1_APE1_CNTL__CI__VI regSDMA1_RLC1_APE1_CNTL__CI__VI; -typedef union SDMA1_RLC1_CONTEXT_STATUS__CI__VI regSDMA1_RLC1_CONTEXT_STATUS__CI__VI; -typedef union SDMA1_RLC1_DOORBELL_LOG__CI__VI regSDMA1_RLC1_DOORBELL_LOG__CI__VI; -typedef union SDMA1_RLC1_DOORBELL__CI__VI regSDMA1_RLC1_DOORBELL__CI__VI; -typedef union SDMA1_RLC1_IB_BASE_HI__CI__VI regSDMA1_RLC1_IB_BASE_HI__CI__VI; -typedef union SDMA1_RLC1_IB_BASE_LO__CI__VI regSDMA1_RLC1_IB_BASE_LO__CI__VI; -typedef union SDMA1_RLC1_IB_CNTL__CI__VI regSDMA1_RLC1_IB_CNTL__CI__VI; -typedef union SDMA1_RLC1_IB_OFFSET__CI__VI regSDMA1_RLC1_IB_OFFSET__CI__VI; -typedef union SDMA1_RLC1_IB_RPTR__CI__VI regSDMA1_RLC1_IB_RPTR__CI__VI; -typedef union SDMA1_RLC1_IB_SIZE__CI__VI regSDMA1_RLC1_IB_SIZE__CI__VI; -typedef union SDMA1_RLC1_RB_BASE_HI__CI__VI regSDMA1_RLC1_RB_BASE_HI__CI__VI; -typedef union SDMA1_RLC1_RB_BASE__CI__VI regSDMA1_RLC1_RB_BASE__CI__VI; -typedef union SDMA1_RLC1_RB_CNTL__CI__VI regSDMA1_RLC1_RB_CNTL__CI__VI; -typedef union SDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI regSDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI; -typedef union SDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI regSDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI; -typedef union SDMA1_RLC1_RB_RPTR__CI__VI regSDMA1_RLC1_RB_RPTR__CI__VI; -typedef union SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI; -typedef union SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI; -typedef union SDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI regSDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI; -typedef union SDMA1_RLC1_RB_WPTR__CI__VI regSDMA1_RLC1_RB_WPTR__CI__VI; -typedef union SDMA1_RLC1_SKIP_CNTL__CI__VI regSDMA1_RLC1_SKIP_CNTL__CI__VI; -typedef union SDMA1_RLC1_VIRTUAL_ADDR__CI__VI regSDMA1_RLC1_VIRTUAL_ADDR__CI__VI; -typedef union SDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI regSDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI; -typedef union SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI; -typedef union SDMA1_STATUS1_REG__CI__VI regSDMA1_STATUS1_REG__CI__VI; -typedef union SDMA1_STATUS_REG__CI regSDMA1_STATUS_REG__CI; -typedef union SDMA1_STATUS_REG__VI regSDMA1_STATUS_REG__VI; -typedef union SDMA1_TILING_CONFIG__CI__VI regSDMA1_TILING_CONFIG__CI__VI; -typedef union SDMA1_UCODE_ADDR__CI__VI regSDMA1_UCODE_ADDR__CI__VI; -typedef union SDMA1_UCODE_DATA__CI__VI regSDMA1_UCODE_DATA__CI__VI; -typedef union SDMA_CONFIG__CI regSDMA_CONFIG__CI; -typedef union SDMA_PGFSM_CONFIG__CI__VI regSDMA_PGFSM_CONFIG__CI__VI; -typedef union SDMA_PGFSM_READ__CI__VI regSDMA_PGFSM_READ__CI__VI; -typedef union SDMA_PGFSM_WRITE__CI__VI regSDMA_PGFSM_WRITE__CI__VI; -typedef union SDMA_POWER_GATING__CI__VI regSDMA_POWER_GATING__CI__VI; -typedef union SDVO_CNTL__SI regSDVO_CNTL__SI; -typedef union SEM_CHICKEN_BITS__CI__VI regSEM_CHICKEN_BITS__CI__VI; -typedef union SEM_EDC_CONFIG__CI__VI regSEM_EDC_CONFIG__CI__VI; -typedef union SEM_MAILBOX regSEM_MAILBOX; -typedef union SEM_MAILBOX_CLIENTCONFIG__CI__VI regSEM_MAILBOX_CLIENTCONFIG__CI__VI; -typedef union SEM_MAILBOX_CLIENTCONFIG__SI regSEM_MAILBOX_CLIENTCONFIG__SI; -typedef union SEM_MAILBOX_CONTROL regSEM_MAILBOX_CONTROL; -typedef union SEM_MCIF_CONFIG regSEM_MCIF_CONFIG; -typedef union SEM_STATUS__CI__VI regSEM_STATUS__CI__VI; -typedef union SEQ00__SI regSEQ00__SI; -typedef union SEQ01__SI regSEQ01__SI; -typedef union SEQ02__SI regSEQ02__SI; -typedef union SEQ03__SI regSEQ03__SI; -typedef union SEQ04__SI regSEQ04__SI; -typedef union SEQ8_DATA__SI regSEQ8_DATA__SI; -typedef union SEQ8_IDX__SI regSEQ8_IDX__SI; -typedef union SETUP_DEBUG_REG0 regSETUP_DEBUG_REG0; -typedef union SETUP_DEBUG_REG1 regSETUP_DEBUG_REG1; -typedef union SETUP_DEBUG_REG2 regSETUP_DEBUG_REG2; -typedef union SETUP_DEBUG_REG3 regSETUP_DEBUG_REG3; -typedef union SETUP_DEBUG_REG4 regSETUP_DEBUG_REG4; -typedef union SETUP_DEBUG_REG5 regSETUP_DEBUG_REG5; -typedef union SH_HIDDEN_PRIVATE_BASE_VMID__CI__VI regSH_HIDDEN_PRIVATE_BASE_VMID__CI__VI; -typedef union SH_MEM_APE1_BASE__CI__VI regSH_MEM_APE1_BASE__CI__VI; -typedef union SH_MEM_APE1_LIMIT__CI__VI regSH_MEM_APE1_LIMIT__CI__VI; -typedef union SH_MEM_BASES__CI__VI regSH_MEM_BASES__CI__VI; -typedef union SH_MEM_CONFIG__CI regSH_MEM_CONFIG__CI; -typedef union SH_MEM_CONFIG__VI regSH_MEM_CONFIG__VI; -typedef union SH_STATIC_MEM_CONFIG__CI__VI regSH_STATIC_MEM_CONFIG__CI__VI; -typedef union SLAVE_COMM_CMD_REG__SI regSLAVE_COMM_CMD_REG__SI; -typedef union SLAVE_COMM_CNTL_REG__SI regSLAVE_COMM_CNTL_REG__SI; -typedef union SLAVE_COMM_DATA_REG1__SI regSLAVE_COMM_DATA_REG1__SI; -typedef union SLAVE_COMM_DATA_REG2__SI regSLAVE_COMM_DATA_REG2__SI; -typedef union SLAVE_COMM_DATA_REG3__SI regSLAVE_COMM_DATA_REG3__SI; -typedef union SLAVE_HANG_ERROR regSLAVE_HANG_ERROR; -typedef union SLAVE_HANG_PROTECTION_CNTL regSLAVE_HANG_PROTECTION_CNTL; -typedef union SLAVE_REQ_CREDIT_CNTL regSLAVE_REQ_CREDIT_CNTL; -typedef union SLOW_AES0 regSLOW_AES0; -typedef union SLOW_AES1 regSLOW_AES1; -typedef union SLOW_AES2 regSLOW_AES2; -typedef union SLOW_AES3 regSLOW_AES3; -typedef union SMBCLK_PAD_CNTL__CI regSMBCLK_PAD_CNTL__CI; -typedef union SMBCLK_PAD_CNTL__VI regSMBCLK_PAD_CNTL__VI; -typedef union SMBDAT_PAD_CNTL__CI regSMBDAT_PAD_CNTL__CI; -typedef union SMBDAT_PAD_CNTL__VI regSMBDAT_PAD_CNTL__VI; -typedef union SMBUS_SLV_CNTL__CI regSMBUS_SLV_CNTL__CI; -typedef union SMC_ACP_RESP__CI__VI regSMC_ACP_RESP__CI__VI; -typedef union SMC_DBG_CNTL__CI__VI regSMC_DBG_CNTL__CI__VI; -typedef union SMC_DEBUG_BUS__SI regSMC_DEBUG_BUS__SI; -typedef union SMC_DMA_CAPTURE_EN regSMC_DMA_CAPTURE_EN; -typedef union SMC_DMA_CORE_CAPT_0 regSMC_DMA_CORE_CAPT_0; -typedef union SMC_DMA_CORE_CAPT_1 regSMC_DMA_CORE_CAPT_1; -typedef union SMC_DMA_CORE_CAPT_2 regSMC_DMA_CORE_CAPT_2; -typedef union SMC_DMA_CORE_CAPT_3 regSMC_DMA_CORE_CAPT_3; -typedef union SMC_DMA_CORE_CAPT_4 regSMC_DMA_CORE_CAPT_4; -typedef union SMC_DMA_CORE_CAPT_5 regSMC_DMA_CORE_CAPT_5; -typedef union SMC_DMA_CORE_CAPT_6 regSMC_DMA_CORE_CAPT_6; -typedef union SMC_DMA_CORE_CAPT_7 regSMC_DMA_CORE_CAPT_7; -typedef union SMC_DMA_CORE_STATUS_0 regSMC_DMA_CORE_STATUS_0; -typedef union SMC_DMA_CORE_STATUS_1 regSMC_DMA_CORE_STATUS_1; -typedef union SMC_DMA_CORE_STATUS_2 regSMC_DMA_CORE_STATUS_2; -typedef union SMC_DMA_CORE_STATUS_3 regSMC_DMA_CORE_STATUS_3; -typedef union SMC_DMA_CORE_STATUS_4 regSMC_DMA_CORE_STATUS_4; -typedef union SMC_DMA_CORE_STATUS_5 regSMC_DMA_CORE_STATUS_5; -typedef union SMC_DMA_CORE_STATUS_6 regSMC_DMA_CORE_STATUS_6; -typedef union SMC_DMA_CORE_STATUS_7 regSMC_DMA_CORE_STATUS_7; -typedef union SMC_DMA_DEVQ_CAPT_0 regSMC_DMA_DEVQ_CAPT_0; -typedef union SMC_DMA_DEVQ_CAPT_1 regSMC_DMA_DEVQ_CAPT_1; -typedef union SMC_DMA_DEVQ_CAPT_2 regSMC_DMA_DEVQ_CAPT_2; -typedef union SMC_DMA_DEVQ_CAPT_3 regSMC_DMA_DEVQ_CAPT_3; -typedef union SMC_DMA_DEVQ_CAPT_4 regSMC_DMA_DEVQ_CAPT_4; -typedef union SMC_DMA_DEVQ_CAPT_5 regSMC_DMA_DEVQ_CAPT_5; -typedef union SMC_DMA_DEVQ_CAPT_6 regSMC_DMA_DEVQ_CAPT_6; -typedef union SMC_DMA_DEVQ_CAPT_7 regSMC_DMA_DEVQ_CAPT_7; -typedef union SMC_DMA_DEVQ_STATUS_0 regSMC_DMA_DEVQ_STATUS_0; -typedef union SMC_DMA_DEVQ_STATUS_1 regSMC_DMA_DEVQ_STATUS_1; -typedef union SMC_DMA_DEVQ_STATUS_2 regSMC_DMA_DEVQ_STATUS_2; -typedef union SMC_DMA_DEVQ_STATUS_3 regSMC_DMA_DEVQ_STATUS_3; -typedef union SMC_DMA_DEVQ_STATUS_4 regSMC_DMA_DEVQ_STATUS_4; -typedef union SMC_DMA_DEVQ_STATUS_5 regSMC_DMA_DEVQ_STATUS_5; -typedef union SMC_DMA_DEVQ_STATUS_6 regSMC_DMA_DEVQ_STATUS_6; -typedef union SMC_DMA_DEVQ_STATUS_7 regSMC_DMA_DEVQ_STATUS_7; -typedef union SMC_DMA_DMEM_CAPT_0 regSMC_DMA_DMEM_CAPT_0; -typedef union SMC_DMA_DMEM_CAPT_1 regSMC_DMA_DMEM_CAPT_1; -typedef union SMC_DMA_DMEM_CAPT_2 regSMC_DMA_DMEM_CAPT_2; -typedef union SMC_DMA_DMEM_CAPT_3 regSMC_DMA_DMEM_CAPT_3; -typedef union SMC_DMA_DMEM_CAPT_4 regSMC_DMA_DMEM_CAPT_4; -typedef union SMC_DMA_DMEM_CAPT_5 regSMC_DMA_DMEM_CAPT_5; -typedef union SMC_DMA_DMEM_CAPT_6 regSMC_DMA_DMEM_CAPT_6; -typedef union SMC_DMA_DMEM_CAPT_7 regSMC_DMA_DMEM_CAPT_7; -typedef union SMC_DMA_DMEM_STATUS_0 regSMC_DMA_DMEM_STATUS_0; -typedef union SMC_DMA_DMEM_STATUS_1 regSMC_DMA_DMEM_STATUS_1; -typedef union SMC_DMA_DMEM_STATUS_2 regSMC_DMA_DMEM_STATUS_2; -typedef union SMC_DMA_DMEM_STATUS_3 regSMC_DMA_DMEM_STATUS_3; -typedef union SMC_DMA_DMEM_STATUS_4 regSMC_DMA_DMEM_STATUS_4; -typedef union SMC_DMA_DMEM_STATUS_5 regSMC_DMA_DMEM_STATUS_5; -typedef union SMC_DMA_DMEM_STATUS_6 regSMC_DMA_DMEM_STATUS_6; -typedef union SMC_DMA_DMEM_STATUS_7 regSMC_DMA_DMEM_STATUS_7; -typedef union SMC_DMA_IMEMQ_CAPT_1 regSMC_DMA_IMEMQ_CAPT_1; -typedef union SMC_DMA_IMEMQ_CAPT_2 regSMC_DMA_IMEMQ_CAPT_2; -typedef union SMC_DMA_IMEMQ_CAPT_3 regSMC_DMA_IMEMQ_CAPT_3; -typedef union SMC_DMA_IMEMQ_CAPT_4 regSMC_DMA_IMEMQ_CAPT_4; -typedef union SMC_DMA_IMEMQ_CAPT_5 regSMC_DMA_IMEMQ_CAPT_5; -typedef union SMC_DMA_IMEMQ_CAPT_6 regSMC_DMA_IMEMQ_CAPT_6; -typedef union SMC_DMA_IMEMQ_CAPT_7 regSMC_DMA_IMEMQ_CAPT_7; -typedef union SMC_DMA_IMEMQ_STATUS_0 regSMC_DMA_IMEMQ_STATUS_0; -typedef union SMC_DMA_IMEMQ_STATUS_1 regSMC_DMA_IMEMQ_STATUS_1; -typedef union SMC_DMA_IMEMQ_STATUS_2 regSMC_DMA_IMEMQ_STATUS_2; -typedef union SMC_DMA_IMEMQ_STATUS_3 regSMC_DMA_IMEMQ_STATUS_3; -typedef union SMC_DMA_IMEMQ_STATUS_4 regSMC_DMA_IMEMQ_STATUS_4; -typedef union SMC_DMA_IMEMQ_STATUS_5 regSMC_DMA_IMEMQ_STATUS_5; -typedef union SMC_DMA_IMEMQ_STATUS_6 regSMC_DMA_IMEMQ_STATUS_6; -typedef union SMC_DMA_IMEMQ_STATUS_7 regSMC_DMA_IMEMQ_STATUS_7; -typedef union SMC_DRAM_ACCESS_CNTL__CI__VI regSMC_DRAM_ACCESS_CNTL__CI__VI; -typedef union SMC_DRAM_CNTL_RDREQ_ADDR regSMC_DRAM_CNTL_RDREQ_ADDR; -typedef union SMC_DRAM_CNTL_RDREQ_CNTL_0__CI__VI regSMC_DRAM_CNTL_RDREQ_CNTL_0__CI__VI; -typedef union SMC_DRAM_CNTL_RDREQ_CNTL_0__SI regSMC_DRAM_CNTL_RDREQ_CNTL_0__SI; -typedef union SMC_DRAM_CNTL_RDREQ_CNTL_1__CI__VI regSMC_DRAM_CNTL_RDREQ_CNTL_1__CI__VI; -typedef union SMC_DRAM_CNTL_RDREQ_CNTL_1__SI regSMC_DRAM_CNTL_RDREQ_CNTL_1__SI; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_0 regSMC_DRAM_CNTL_RDRET_DATA_0_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_1 regSMC_DRAM_CNTL_RDRET_DATA_0_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_2 regSMC_DRAM_CNTL_RDRET_DATA_0_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_3 regSMC_DRAM_CNTL_RDRET_DATA_0_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_4 regSMC_DRAM_CNTL_RDRET_DATA_0_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_5 regSMC_DRAM_CNTL_RDRET_DATA_0_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_6 regSMC_DRAM_CNTL_RDRET_DATA_0_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_0_7 regSMC_DRAM_CNTL_RDRET_DATA_0_7; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_0 regSMC_DRAM_CNTL_RDRET_DATA_1_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_1 regSMC_DRAM_CNTL_RDRET_DATA_1_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_2 regSMC_DRAM_CNTL_RDRET_DATA_1_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_3 regSMC_DRAM_CNTL_RDRET_DATA_1_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_4 regSMC_DRAM_CNTL_RDRET_DATA_1_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_5 regSMC_DRAM_CNTL_RDRET_DATA_1_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_6 regSMC_DRAM_CNTL_RDRET_DATA_1_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_1_7 regSMC_DRAM_CNTL_RDRET_DATA_1_7; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_0 regSMC_DRAM_CNTL_RDRET_DATA_2_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_1 regSMC_DRAM_CNTL_RDRET_DATA_2_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_2 regSMC_DRAM_CNTL_RDRET_DATA_2_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_3 regSMC_DRAM_CNTL_RDRET_DATA_2_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_4 regSMC_DRAM_CNTL_RDRET_DATA_2_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_5 regSMC_DRAM_CNTL_RDRET_DATA_2_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_6 regSMC_DRAM_CNTL_RDRET_DATA_2_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_2_7 regSMC_DRAM_CNTL_RDRET_DATA_2_7; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_0 regSMC_DRAM_CNTL_RDRET_DATA_3_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_1 regSMC_DRAM_CNTL_RDRET_DATA_3_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_2 regSMC_DRAM_CNTL_RDRET_DATA_3_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_3 regSMC_DRAM_CNTL_RDRET_DATA_3_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_4 regSMC_DRAM_CNTL_RDRET_DATA_3_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_5 regSMC_DRAM_CNTL_RDRET_DATA_3_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_6 regSMC_DRAM_CNTL_RDRET_DATA_3_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_3_7 regSMC_DRAM_CNTL_RDRET_DATA_3_7; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_0 regSMC_DRAM_CNTL_RDRET_DATA_4_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_1 regSMC_DRAM_CNTL_RDRET_DATA_4_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_2 regSMC_DRAM_CNTL_RDRET_DATA_4_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_3 regSMC_DRAM_CNTL_RDRET_DATA_4_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_4 regSMC_DRAM_CNTL_RDRET_DATA_4_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_5 regSMC_DRAM_CNTL_RDRET_DATA_4_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_6 regSMC_DRAM_CNTL_RDRET_DATA_4_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_4_7 regSMC_DRAM_CNTL_RDRET_DATA_4_7; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_0 regSMC_DRAM_CNTL_RDRET_DATA_5_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_1 regSMC_DRAM_CNTL_RDRET_DATA_5_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_2 regSMC_DRAM_CNTL_RDRET_DATA_5_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_3 regSMC_DRAM_CNTL_RDRET_DATA_5_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_4 regSMC_DRAM_CNTL_RDRET_DATA_5_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_5 regSMC_DRAM_CNTL_RDRET_DATA_5_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_6 regSMC_DRAM_CNTL_RDRET_DATA_5_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_5_7 regSMC_DRAM_CNTL_RDRET_DATA_5_7; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_0 regSMC_DRAM_CNTL_RDRET_DATA_6_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_1 regSMC_DRAM_CNTL_RDRET_DATA_6_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_2 regSMC_DRAM_CNTL_RDRET_DATA_6_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_3 regSMC_DRAM_CNTL_RDRET_DATA_6_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_4 regSMC_DRAM_CNTL_RDRET_DATA_6_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_5 regSMC_DRAM_CNTL_RDRET_DATA_6_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_6 regSMC_DRAM_CNTL_RDRET_DATA_6_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_6_7 regSMC_DRAM_CNTL_RDRET_DATA_6_7; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_0 regSMC_DRAM_CNTL_RDRET_DATA_7_0; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_1 regSMC_DRAM_CNTL_RDRET_DATA_7_1; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_2 regSMC_DRAM_CNTL_RDRET_DATA_7_2; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_3 regSMC_DRAM_CNTL_RDRET_DATA_7_3; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_4 regSMC_DRAM_CNTL_RDRET_DATA_7_4; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_5 regSMC_DRAM_CNTL_RDRET_DATA_7_5; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_6 regSMC_DRAM_CNTL_RDRET_DATA_7_6; -typedef union SMC_DRAM_CNTL_RDRET_DATA_7_7 regSMC_DRAM_CNTL_RDRET_DATA_7_7; -typedef union SMC_DRAM_CNTL_RDRET_NACK regSMC_DRAM_CNTL_RDRET_NACK; -typedef union SMC_DRAM_CNTL_RDRET_VALID regSMC_DRAM_CNTL_RDRET_VALID; -typedef union SMC_DRAM_CNTL_WRREQ_CNTL regSMC_DRAM_CNTL_WRREQ_CNTL; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_0 regSMC_DRAM_CNTL_WRREQ_DATA_0; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_1 regSMC_DRAM_CNTL_WRREQ_DATA_1; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_2 regSMC_DRAM_CNTL_WRREQ_DATA_2; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_3 regSMC_DRAM_CNTL_WRREQ_DATA_3; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_4 regSMC_DRAM_CNTL_WRREQ_DATA_4; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_5 regSMC_DRAM_CNTL_WRREQ_DATA_5; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_6 regSMC_DRAM_CNTL_WRREQ_DATA_6; -typedef union SMC_DRAM_CNTL_WRREQ_DATA_7 regSMC_DRAM_CNTL_WRREQ_DATA_7; -typedef union SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__CI__VI regSMC_DRAM_CNTL_WRREQ_HIGH_ADDR__CI__VI; -typedef union SMC_DRAM_CNTL_WRREQ_HIGH_ADDR__SI regSMC_DRAM_CNTL_WRREQ_HIGH_ADDR__SI; -typedef union SMC_DRAM_CNTL_WRREQ_LOW_ADDR regSMC_DRAM_CNTL_WRREQ_LOW_ADDR; -typedef union SMC_DRAM_CNTL_WRREQ_MASK regSMC_DRAM_CNTL_WRREQ_MASK; -typedef union SMC_DRAM_CNTL_WRREQ_STATUS regSMC_DRAM_CNTL_WRREQ_STATUS; -typedef union SMC_DRAM_CNTL_WRRET_STATUS_0 regSMC_DRAM_CNTL_WRRET_STATUS_0; -typedef union SMC_DRAM_CNTL_WRRET_STATUS_1__SI regSMC_DRAM_CNTL_WRRET_STATUS_1__SI; -typedef union SMC_DRAM_CNTL_WRRET_STATUS_2__SI regSMC_DRAM_CNTL_WRRET_STATUS_2__SI; -typedef union SMC_DRAM_CNTL_WRRET_STATUS_3__SI regSMC_DRAM_CNTL_WRRET_STATUS_3__SI; -typedef union SMC_EVENT_CLEAR__SI regSMC_EVENT_CLEAR__SI; -typedef union SMC_EVENT_PENDING__SI regSMC_EVENT_PENDING__SI; -typedef union SMC_EVENT_POLARITY__SI regSMC_EVENT_POLARITY__SI; -typedef union SMC_EVENT_SENSE__SI regSMC_EVENT_SENSE__SI; -typedef union SMC_HOST_MSG regSMC_HOST_MSG; -typedef union SMC_HOST_RESP regSMC_HOST_RESP; -typedef union SMC_IND_ACCESS_CNTL regSMC_IND_ACCESS_CNTL; -typedef union SMC_IND_DATA regSMC_IND_DATA; -typedef union SMC_IND_DATA_0__CI__VI regSMC_IND_DATA_0__CI__VI; -typedef union SMC_IND_DATA_1__CI__VI regSMC_IND_DATA_1__CI__VI; -typedef union SMC_IND_DATA_2__CI__VI regSMC_IND_DATA_2__CI__VI; -typedef union SMC_IND_DATA_3__CI__VI regSMC_IND_DATA_3__CI__VI; -typedef union SMC_IND_DATA_4__CI__VI regSMC_IND_DATA_4__CI__VI; -typedef union SMC_IND_DATA_5__CI__VI regSMC_IND_DATA_5__CI__VI; -typedef union SMC_IND_DATA_6__CI__VI regSMC_IND_DATA_6__CI__VI; -typedef union SMC_IND_DATA_7__CI__VI regSMC_IND_DATA_7__CI__VI; -typedef union SMC_IND_INDEX regSMC_IND_INDEX; -typedef union SMC_IND_INDEX_0__CI__VI regSMC_IND_INDEX_0__CI__VI; -typedef union SMC_IND_INDEX_1__CI__VI regSMC_IND_INDEX_1__CI__VI; -typedef union SMC_IND_INDEX_2__CI__VI regSMC_IND_INDEX_2__CI__VI; -typedef union SMC_IND_INDEX_3__CI__VI regSMC_IND_INDEX_3__CI__VI; -typedef union SMC_IND_INDEX_4__CI__VI regSMC_IND_INDEX_4__CI__VI; -typedef union SMC_IND_INDEX_5__CI__VI regSMC_IND_INDEX_5__CI__VI; -typedef union SMC_IND_INDEX_6__CI__VI regSMC_IND_INDEX_6__CI__VI; -typedef union SMC_IND_INDEX_7__CI__VI regSMC_IND_INDEX_7__CI__VI; -typedef union SMC_INTR_CNTL_INTR_ID regSMC_INTR_CNTL_INTR_ID; -typedef union SMC_INTR_CNTL_LEVEL_0 regSMC_INTR_CNTL_LEVEL_0; -typedef union SMC_INTR_CNTL_LEVEL_1 regSMC_INTR_CNTL_LEVEL_1; -typedef union SMC_INTR_CNTL_LINE regSMC_INTR_CNTL_LINE; -typedef union SMC_INTR_CNTL_MASK_0 regSMC_INTR_CNTL_MASK_0; -typedef union SMC_INTR_CNTL_MASK_1 regSMC_INTR_CNTL_MASK_1; -typedef union SMC_INTR_CNTL_PRIORITY_0 regSMC_INTR_CNTL_PRIORITY_0; -typedef union SMC_INTR_CNTL_PRIORITY_1 regSMC_INTR_CNTL_PRIORITY_1; -typedef union SMC_INTR_CNTL_PRIORITY_10 regSMC_INTR_CNTL_PRIORITY_10; -typedef union SMC_INTR_CNTL_PRIORITY_11 regSMC_INTR_CNTL_PRIORITY_11; -typedef union SMC_INTR_CNTL_PRIORITY_12 regSMC_INTR_CNTL_PRIORITY_12; -typedef union SMC_INTR_CNTL_PRIORITY_13 regSMC_INTR_CNTL_PRIORITY_13; -typedef union SMC_INTR_CNTL_PRIORITY_14 regSMC_INTR_CNTL_PRIORITY_14; -typedef union SMC_INTR_CNTL_PRIORITY_15 regSMC_INTR_CNTL_PRIORITY_15; -typedef union SMC_INTR_CNTL_PRIORITY_2 regSMC_INTR_CNTL_PRIORITY_2; -typedef union SMC_INTR_CNTL_PRIORITY_3 regSMC_INTR_CNTL_PRIORITY_3; -typedef union SMC_INTR_CNTL_PRIORITY_4 regSMC_INTR_CNTL_PRIORITY_4; -typedef union SMC_INTR_CNTL_PRIORITY_5 regSMC_INTR_CNTL_PRIORITY_5; -typedef union SMC_INTR_CNTL_PRIORITY_6 regSMC_INTR_CNTL_PRIORITY_6; -typedef union SMC_INTR_CNTL_PRIORITY_7 regSMC_INTR_CNTL_PRIORITY_7; -typedef union SMC_INTR_CNTL_PRIORITY_8 regSMC_INTR_CNTL_PRIORITY_8; -typedef union SMC_INTR_CNTL_PRIORITY_9 regSMC_INTR_CNTL_PRIORITY_9; -typedef union SMC_INTR_CNTL_STATUS_0 regSMC_INTR_CNTL_STATUS_0; -typedef union SMC_INTR_CNTL_STATUS_1 regSMC_INTR_CNTL_STATUS_1; -typedef union SMC_INT_GPIO_CLEAR__SI regSMC_INT_GPIO_CLEAR__SI; -typedef union SMC_INT_GPIO_PENDING__SI regSMC_INT_GPIO_PENDING__SI; -typedef union SMC_INT_GPIO_POLARITY__SI regSMC_INT_GPIO_POLARITY__SI; -typedef union SMC_INT_GPIO_SENSE__SI regSMC_INT_GPIO_SENSE__SI; -typedef union SMC_INT_REQ__SI regSMC_INT_REQ__SI; -typedef union SMC_INT_STATUS__SI regSMC_INT_STATUS__SI; -typedef union SMC_LM32_ADDER0 regSMC_LM32_ADDER0; -typedef union SMC_LM32_ADDER1 regSMC_LM32_ADDER1; -typedef union SMC_LM32_ADDER2 regSMC_LM32_ADDER2; -typedef union SMC_LM32_ARITH_MISC regSMC_LM32_ARITH_MISC; -typedef union SMC_LM32_BP0 regSMC_LM32_BP0; -typedef union SMC_LM32_BP1 regSMC_LM32_BP1; -typedef union SMC_LM32_BP2 regSMC_LM32_BP2; -typedef union SMC_LM32_BP3 regSMC_LM32_BP3; -typedef union SMC_LM32_DC regSMC_LM32_DC; -typedef union SMC_LM32_DEBA regSMC_LM32_DEBA; -typedef union SMC_LM32_GPR_0 regSMC_LM32_GPR_0; -typedef union SMC_LM32_GPR_1 regSMC_LM32_GPR_1; -typedef union SMC_LM32_GPR_10 regSMC_LM32_GPR_10; -typedef union SMC_LM32_GPR_11 regSMC_LM32_GPR_11; -typedef union SMC_LM32_GPR_12 regSMC_LM32_GPR_12; -typedef union SMC_LM32_GPR_13 regSMC_LM32_GPR_13; -typedef union SMC_LM32_GPR_14 regSMC_LM32_GPR_14; -typedef union SMC_LM32_GPR_15 regSMC_LM32_GPR_15; -typedef union SMC_LM32_GPR_16 regSMC_LM32_GPR_16; -typedef union SMC_LM32_GPR_17 regSMC_LM32_GPR_17; -typedef union SMC_LM32_GPR_18 regSMC_LM32_GPR_18; -typedef union SMC_LM32_GPR_19 regSMC_LM32_GPR_19; -typedef union SMC_LM32_GPR_2 regSMC_LM32_GPR_2; -typedef union SMC_LM32_GPR_20 regSMC_LM32_GPR_20; -typedef union SMC_LM32_GPR_21 regSMC_LM32_GPR_21; -typedef union SMC_LM32_GPR_22 regSMC_LM32_GPR_22; -typedef union SMC_LM32_GPR_23 regSMC_LM32_GPR_23; -typedef union SMC_LM32_GPR_24 regSMC_LM32_GPR_24; -typedef union SMC_LM32_GPR_25 regSMC_LM32_GPR_25; -typedef union SMC_LM32_GPR_26 regSMC_LM32_GPR_26; -typedef union SMC_LM32_GPR_27 regSMC_LM32_GPR_27; -typedef union SMC_LM32_GPR_28 regSMC_LM32_GPR_28; -typedef union SMC_LM32_GPR_29 regSMC_LM32_GPR_29; -typedef union SMC_LM32_GPR_3 regSMC_LM32_GPR_3; -typedef union SMC_LM32_GPR_30 regSMC_LM32_GPR_30; -typedef union SMC_LM32_GPR_31 regSMC_LM32_GPR_31; -typedef union SMC_LM32_GPR_4 regSMC_LM32_GPR_4; -typedef union SMC_LM32_GPR_5 regSMC_LM32_GPR_5; -typedef union SMC_LM32_GPR_6 regSMC_LM32_GPR_6; -typedef union SMC_LM32_GPR_7 regSMC_LM32_GPR_7; -typedef union SMC_LM32_GPR_8 regSMC_LM32_GPR_8; -typedef union SMC_LM32_GPR_9 regSMC_LM32_GPR_9; -typedef union SMC_LM32_MC_ARITH regSMC_LM32_MC_ARITH; -typedef union SMC_LM32_MULTIPLIER regSMC_LM32_MULTIPLIER; -typedef union SMC_LM32_MULT_MC0 regSMC_LM32_MULT_MC0; -typedef union SMC_LM32_MULT_MC1 regSMC_LM32_MULT_MC1; -typedef union SMC_LM32_WP0 regSMC_LM32_WP0; -typedef union SMC_LM32_WP1 regSMC_LM32_WP1; -typedef union SMC_LM32_WP2 regSMC_LM32_WP2; -typedef union SMC_LM32_WP3 regSMC_LM32_WP3; -typedef union SMC_MESSAGE_0__CI__VI regSMC_MESSAGE_0__CI__VI; -typedef union SMC_MESSAGE_0__SI regSMC_MESSAGE_0__SI; -typedef union SMC_MESSAGE_10__CI__VI regSMC_MESSAGE_10__CI__VI; -typedef union SMC_MESSAGE_11__CI__VI regSMC_MESSAGE_11__CI__VI; -typedef union SMC_MESSAGE_1__CI__VI regSMC_MESSAGE_1__CI__VI; -typedef union SMC_MESSAGE_1__SI regSMC_MESSAGE_1__SI; -typedef union SMC_MESSAGE_2__CI__VI regSMC_MESSAGE_2__CI__VI; -typedef union SMC_MESSAGE_3__CI__VI regSMC_MESSAGE_3__CI__VI; -typedef union SMC_MESSAGE_4__CI__VI regSMC_MESSAGE_4__CI__VI; -typedef union SMC_MESSAGE_5__CI__VI regSMC_MESSAGE_5__CI__VI; -typedef union SMC_MESSAGE_6__CI__VI regSMC_MESSAGE_6__CI__VI; -typedef union SMC_MESSAGE_7__CI__VI regSMC_MESSAGE_7__CI__VI; -typedef union SMC_MESSAGE_8__CI__VI regSMC_MESSAGE_8__CI__VI; -typedef union SMC_MESSAGE_9__CI__VI regSMC_MESSAGE_9__CI__VI; -typedef union SMC_MISC_HANDSHAKE__CI__VI regSMC_MISC_HANDSHAKE__CI__VI; -typedef union SMC_MSG_ARG_0__CI__VI regSMC_MSG_ARG_0__CI__VI; -typedef union SMC_MSG_ARG_10__CI__VI regSMC_MSG_ARG_10__CI__VI; -typedef union SMC_MSG_ARG_11__CI__VI regSMC_MSG_ARG_11__CI__VI; -typedef union SMC_MSG_ARG_1__CI__VI regSMC_MSG_ARG_1__CI__VI; -typedef union SMC_MSG_ARG_2__CI__VI regSMC_MSG_ARG_2__CI__VI; -typedef union SMC_MSG_ARG_3__CI__VI regSMC_MSG_ARG_3__CI__VI; -typedef union SMC_MSG_ARG_4__CI__VI regSMC_MSG_ARG_4__CI__VI; -typedef union SMC_MSG_ARG_5__CI__VI regSMC_MSG_ARG_5__CI__VI; -typedef union SMC_MSG_ARG_6__CI__VI regSMC_MSG_ARG_6__CI__VI; -typedef union SMC_MSG_ARG_7__CI__VI regSMC_MSG_ARG_7__CI__VI; -typedef union SMC_MSG_ARG_8__CI__VI regSMC_MSG_ARG_8__CI__VI; -typedef union SMC_MSG_ARG_9__CI__VI regSMC_MSG_ARG_9__CI__VI; -typedef union SMC_MUTEX_0__CI__VI regSMC_MUTEX_0__CI__VI; -typedef union SMC_MUTEX_1__CI__VI regSMC_MUTEX_1__CI__VI; -typedef union SMC_MUTEX_2__CI__VI regSMC_MUTEX_2__CI__VI; -typedef union SMC_MUTEX_3__CI__VI regSMC_MUTEX_3__CI__VI; -typedef union SMC_PC_A__CI__VI regSMC_PC_A__CI__VI; -typedef union SMC_PC_C__CI__VI regSMC_PC_C__CI__VI; -typedef union SMC_PC_D__CI__VI regSMC_PC_D__CI__VI; -typedef union SMC_PC_F__CI__VI regSMC_PC_F__CI__VI; -typedef union SMC_PC_M__CI__VI regSMC_PC_M__CI__VI; -typedef union SMC_PC_TRACE_0_BR_INST__CI__VI regSMC_PC_TRACE_0_BR_INST__CI__VI; -typedef union SMC_PC_TRACE_0_BR_INST__SI regSMC_PC_TRACE_0_BR_INST__SI; -typedef union SMC_PC_TRACE_0_BR_TAR__CI__VI regSMC_PC_TRACE_0_BR_TAR__CI__VI; -typedef union SMC_PC_TRACE_0_BR_TAR__SI regSMC_PC_TRACE_0_BR_TAR__SI; -typedef union SMC_PC_TRACE_1_BR_INST__CI__VI regSMC_PC_TRACE_1_BR_INST__CI__VI; -typedef union SMC_PC_TRACE_1_BR_INST__SI regSMC_PC_TRACE_1_BR_INST__SI; -typedef union SMC_PC_TRACE_1_BR_TAR__CI__VI regSMC_PC_TRACE_1_BR_TAR__CI__VI; -typedef union SMC_PC_TRACE_1_BR_TAR__SI regSMC_PC_TRACE_1_BR_TAR__SI; -typedef union SMC_PC_TRACE_2_BR_INST__CI__VI regSMC_PC_TRACE_2_BR_INST__CI__VI; -typedef union SMC_PC_TRACE_2_BR_INST__SI regSMC_PC_TRACE_2_BR_INST__SI; -typedef union SMC_PC_TRACE_2_BR_TAR__CI__VI regSMC_PC_TRACE_2_BR_TAR__CI__VI; -typedef union SMC_PC_TRACE_2_BR_TAR__SI regSMC_PC_TRACE_2_BR_TAR__SI; -typedef union SMC_PC_TRACE_3_BR_INST__CI__VI regSMC_PC_TRACE_3_BR_INST__CI__VI; -typedef union SMC_PC_TRACE_3_BR_INST__SI regSMC_PC_TRACE_3_BR_INST__SI; -typedef union SMC_PC_TRACE_3_BR_TAR__CI__VI regSMC_PC_TRACE_3_BR_TAR__CI__VI; -typedef union SMC_PC_TRACE_3_BR_TAR__SI regSMC_PC_TRACE_3_BR_TAR__SI; -typedef union SMC_PC_W__CI__VI regSMC_PC_W__CI__VI; -typedef union SMC_PC_X__CI__VI regSMC_PC_X__CI__VI; -typedef union SMC_PC__SI regSMC_PC__SI; -typedef union SMC_RAMFLOP_0__CI__VI regSMC_RAMFLOP_0__CI__VI; -typedef union SMC_RAMFLOP_10__CI__VI regSMC_RAMFLOP_10__CI__VI; -typedef union SMC_RAMFLOP_11__CI__VI regSMC_RAMFLOP_11__CI__VI; -typedef union SMC_RAMFLOP_12__CI__VI regSMC_RAMFLOP_12__CI__VI; -typedef union SMC_RAMFLOP_13__CI__VI regSMC_RAMFLOP_13__CI__VI; -typedef union SMC_RAMFLOP_14__CI__VI regSMC_RAMFLOP_14__CI__VI; -typedef union SMC_RAMFLOP_15__CI__VI regSMC_RAMFLOP_15__CI__VI; -typedef union SMC_RAMFLOP_16__CI__VI regSMC_RAMFLOP_16__CI__VI; -typedef union SMC_RAMFLOP_17__CI__VI regSMC_RAMFLOP_17__CI__VI; -typedef union SMC_RAMFLOP_18__CI__VI regSMC_RAMFLOP_18__CI__VI; -typedef union SMC_RAMFLOP_19__CI__VI regSMC_RAMFLOP_19__CI__VI; -typedef union SMC_RAMFLOP_1__CI__VI regSMC_RAMFLOP_1__CI__VI; -typedef union SMC_RAMFLOP_20__CI__VI regSMC_RAMFLOP_20__CI__VI; -typedef union SMC_RAMFLOP_21__CI__VI regSMC_RAMFLOP_21__CI__VI; -typedef union SMC_RAMFLOP_22__CI__VI regSMC_RAMFLOP_22__CI__VI; -typedef union SMC_RAMFLOP_23__CI__VI regSMC_RAMFLOP_23__CI__VI; -typedef union SMC_RAMFLOP_24__CI__VI regSMC_RAMFLOP_24__CI__VI; -typedef union SMC_RAMFLOP_25__CI__VI regSMC_RAMFLOP_25__CI__VI; -typedef union SMC_RAMFLOP_26__CI__VI regSMC_RAMFLOP_26__CI__VI; -typedef union SMC_RAMFLOP_27__CI__VI regSMC_RAMFLOP_27__CI__VI; -typedef union SMC_RAMFLOP_28__CI__VI regSMC_RAMFLOP_28__CI__VI; -typedef union SMC_RAMFLOP_29__CI__VI regSMC_RAMFLOP_29__CI__VI; -typedef union SMC_RAMFLOP_2__CI__VI regSMC_RAMFLOP_2__CI__VI; -typedef union SMC_RAMFLOP_30__CI__VI regSMC_RAMFLOP_30__CI__VI; -typedef union SMC_RAMFLOP_31__CI__VI regSMC_RAMFLOP_31__CI__VI; -typedef union SMC_RAMFLOP_3__CI__VI regSMC_RAMFLOP_3__CI__VI; -typedef union SMC_RAMFLOP_4__CI__VI regSMC_RAMFLOP_4__CI__VI; -typedef union SMC_RAMFLOP_5__CI__VI regSMC_RAMFLOP_5__CI__VI; -typedef union SMC_RAMFLOP_6__CI__VI regSMC_RAMFLOP_6__CI__VI; -typedef union SMC_RAMFLOP_7__CI__VI regSMC_RAMFLOP_7__CI__VI; -typedef union SMC_RAMFLOP_8__CI__VI regSMC_RAMFLOP_8__CI__VI; -typedef union SMC_RAMFLOP_9__CI__VI regSMC_RAMFLOP_9__CI__VI; -typedef union SMC_RESP_0__CI__VI regSMC_RESP_0__CI__VI; -typedef union SMC_RESP_0__SI regSMC_RESP_0__SI; -typedef union SMC_RESP_10__CI__VI regSMC_RESP_10__CI__VI; -typedef union SMC_RESP_11__CI__VI regSMC_RESP_11__CI__VI; -typedef union SMC_RESP_1__CI__VI regSMC_RESP_1__CI__VI; -typedef union SMC_RESP_1__SI regSMC_RESP_1__SI; -typedef union SMC_RESP_2__CI__VI regSMC_RESP_2__CI__VI; -typedef union SMC_RESP_3__CI__VI regSMC_RESP_3__CI__VI; -typedef union SMC_RESP_4__CI__VI regSMC_RESP_4__CI__VI; -typedef union SMC_RESP_5__CI__VI regSMC_RESP_5__CI__VI; -typedef union SMC_RESP_6__CI__VI regSMC_RESP_6__CI__VI; -typedef union SMC_RESP_7__CI__VI regSMC_RESP_7__CI__VI; -typedef union SMC_RESP_8__CI__VI regSMC_RESP_8__CI__VI; -typedef union SMC_RESP_9__CI__VI regSMC_RESP_9__CI__VI; -typedef union SMC_SCRATCH0 regSMC_SCRATCH0; -typedef union SMC_SCRATCH1 regSMC_SCRATCH1; -typedef union SMC_SCRATCH10 regSMC_SCRATCH10; -typedef union SMC_SCRATCH11 regSMC_SCRATCH11; -typedef union SMC_SCRATCH12 regSMC_SCRATCH12; -typedef union SMC_SCRATCH2 regSMC_SCRATCH2; -typedef union SMC_SCRATCH3 regSMC_SCRATCH3; -typedef union SMC_SCRATCH4 regSMC_SCRATCH4; -typedef union SMC_SCRATCH5 regSMC_SCRATCH5; -typedef union SMC_SCRATCH6 regSMC_SCRATCH6; -typedef union SMC_SCRATCH7 regSMC_SCRATCH7; -typedef union SMC_SCRATCH8 regSMC_SCRATCH8; -typedef union SMC_SCRATCH9 regSMC_SCRATCH9; -typedef union SMC_SP__CI__VI regSMC_SP__CI__VI; -typedef union SMC_SRBM_CREDITS regSMC_SRBM_CREDITS; -typedef union SMC_SW_INT_CTXID__CI__VI regSMC_SW_INT_CTXID__CI__VI; -typedef union SMC_SW_INT__CI__VI regSMC_SW_INT__CI__VI; -typedef union SMC_SYSCON_ACP_RESP__CI__VI regSMC_SYSCON_ACP_RESP__CI__VI; -typedef union SMC_SYSCON_DBG_CNTL__CI__VI regSMC_SYSCON_DBG_CNTL__CI__VI; -typedef union SMC_SYSCON_GPIO_IN_0 regSMC_SYSCON_GPIO_IN_0; -typedef union SMC_SYSCON_GPIO_IN_1 regSMC_SYSCON_GPIO_IN_1; -typedef union SMC_SYSCON_GPIO_IN_2 regSMC_SYSCON_GPIO_IN_2; -typedef union SMC_SYSCON_GPIO_IN_3 regSMC_SYSCON_GPIO_IN_3; -typedef union SMC_SYSCON_GPIO_OUT_0 regSMC_SYSCON_GPIO_OUT_0; -typedef union SMC_SYSCON_GPIO_OUT_1 regSMC_SYSCON_GPIO_OUT_1; -typedef union SMC_SYSCON_GPIO_OUT_2 regSMC_SYSCON_GPIO_OUT_2; -typedef union SMC_SYSCON_GPIO_OUT_3 regSMC_SYSCON_GPIO_OUT_3; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_0_1__SI regSMC_SYSCON_HOST_RAM_PWRDN_0_1__SI; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_0__CI__VI regSMC_SYSCON_HOST_RAM_PWRDN_0__CI__VI; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_1__CI__VI regSMC_SYSCON_HOST_RAM_PWRDN_1__CI__VI; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_2_3__SI regSMC_SYSCON_HOST_RAM_PWRDN_2_3__SI; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_2__CI__VI regSMC_SYSCON_HOST_RAM_PWRDN_2__CI__VI; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_3__CI__VI regSMC_SYSCON_HOST_RAM_PWRDN_3__CI__VI; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_4__CI__VI regSMC_SYSCON_HOST_RAM_PWRDN_4__CI__VI; -typedef union SMC_SYSCON_HOST_RAM_PWRDN_4__SI regSMC_SYSCON_HOST_RAM_PWRDN_4__SI; -typedef union SMC_SYSCON_INTR_SERVICE_INDEX__SI regSMC_SYSCON_INTR_SERVICE_INDEX__SI; -typedef union SMC_SYSCON_INTR_STATUS__SI regSMC_SYSCON_INTR_STATUS__SI; -typedef union SMC_SYSCON_LM32_CLOCK_CNTL_0 regSMC_SYSCON_LM32_CLOCK_CNTL_0; -typedef union SMC_SYSCON_LM32_CLOCK_CNTL_1 regSMC_SYSCON_LM32_CLOCK_CNTL_1; -typedef union SMC_SYSCON_LM32_CLOCK_CNTL_2 regSMC_SYSCON_LM32_CLOCK_CNTL_2; -typedef union SMC_SYSCON_LM32_RESET_CNTL regSMC_SYSCON_LM32_RESET_CNTL; -typedef union SMC_SYSCON_MISC_CNTL__CI__VI regSMC_SYSCON_MISC_CNTL__CI__VI; -typedef union SMC_SYSCON_MSG_0__CI__VI regSMC_SYSCON_MSG_0__CI__VI; -typedef union SMC_SYSCON_MSG_0__SI regSMC_SYSCON_MSG_0__SI; -typedef union SMC_SYSCON_MSG_10__CI__VI regSMC_SYSCON_MSG_10__CI__VI; -typedef union SMC_SYSCON_MSG_11__CI__VI regSMC_SYSCON_MSG_11__CI__VI; -typedef union SMC_SYSCON_MSG_1__CI__VI regSMC_SYSCON_MSG_1__CI__VI; -typedef union SMC_SYSCON_MSG_1__SI regSMC_SYSCON_MSG_1__SI; -typedef union SMC_SYSCON_MSG_2__CI__VI regSMC_SYSCON_MSG_2__CI__VI; -typedef union SMC_SYSCON_MSG_3__CI__VI regSMC_SYSCON_MSG_3__CI__VI; -typedef union SMC_SYSCON_MSG_4__CI__VI regSMC_SYSCON_MSG_4__CI__VI; -typedef union SMC_SYSCON_MSG_5__CI__VI regSMC_SYSCON_MSG_5__CI__VI; -typedef union SMC_SYSCON_MSG_6__CI__VI regSMC_SYSCON_MSG_6__CI__VI; -typedef union SMC_SYSCON_MSG_7__CI__VI regSMC_SYSCON_MSG_7__CI__VI; -typedef union SMC_SYSCON_MSG_8__CI__VI regSMC_SYSCON_MSG_8__CI__VI; -typedef union SMC_SYSCON_MSG_9__CI__VI regSMC_SYSCON_MSG_9__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_0__CI__VI regSMC_SYSCON_MSG_ARG_0__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_10__CI__VI regSMC_SYSCON_MSG_ARG_10__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_11__CI__VI regSMC_SYSCON_MSG_ARG_11__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_1__CI__VI regSMC_SYSCON_MSG_ARG_1__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_2__CI__VI regSMC_SYSCON_MSG_ARG_2__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_3__CI__VI regSMC_SYSCON_MSG_ARG_3__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_4__CI__VI regSMC_SYSCON_MSG_ARG_4__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_5__CI__VI regSMC_SYSCON_MSG_ARG_5__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_6__CI__VI regSMC_SYSCON_MSG_ARG_6__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_7__CI__VI regSMC_SYSCON_MSG_ARG_7__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_8__CI__VI regSMC_SYSCON_MSG_ARG_8__CI__VI; -typedef union SMC_SYSCON_MSG_ARG_9__CI__VI regSMC_SYSCON_MSG_ARG_9__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_0__CI__VI regSMC_SYSCON_MSG_RESP_0__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_0__SI regSMC_SYSCON_MSG_RESP_0__SI; -typedef union SMC_SYSCON_MSG_RESP_10__CI__VI regSMC_SYSCON_MSG_RESP_10__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_11__CI__VI regSMC_SYSCON_MSG_RESP_11__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_1__CI__VI regSMC_SYSCON_MSG_RESP_1__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_1__SI regSMC_SYSCON_MSG_RESP_1__SI; -typedef union SMC_SYSCON_MSG_RESP_2__CI__VI regSMC_SYSCON_MSG_RESP_2__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_3__CI__VI regSMC_SYSCON_MSG_RESP_3__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_4__CI__VI regSMC_SYSCON_MSG_RESP_4__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_5__CI__VI regSMC_SYSCON_MSG_RESP_5__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_6__CI__VI regSMC_SYSCON_MSG_RESP_6__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_7__CI__VI regSMC_SYSCON_MSG_RESP_7__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_8__CI__VI regSMC_SYSCON_MSG_RESP_8__CI__VI; -typedef union SMC_SYSCON_MSG_RESP_9__CI__VI regSMC_SYSCON_MSG_RESP_9__CI__VI; -typedef union SMC_SYSCON_MSTRCFG_0 regSMC_SYSCON_MSTRCFG_0; -typedef union SMC_SYSCON_MSTRCFG_1 regSMC_SYSCON_MSTRCFG_1; -typedef union SMC_SYSCON_MSTRCFG_2 regSMC_SYSCON_MSTRCFG_2; -typedef union SMC_SYSCON_MSTRCFG_3 regSMC_SYSCON_MSTRCFG_3; -typedef union SMC_SYSCON_MSTRCFG_4 regSMC_SYSCON_MSTRCFG_4; -typedef union SMC_SYSCON_MSTRCFG_5__CI__VI regSMC_SYSCON_MSTRCFG_5__CI__VI; -typedef union SMC_SYSCON_MUTEX_0__CI__VI regSMC_SYSCON_MUTEX_0__CI__VI; -typedef union SMC_SYSCON_MUTEX_1__CI__VI regSMC_SYSCON_MUTEX_1__CI__VI; -typedef union SMC_SYSCON_MUTEX_2__CI__VI regSMC_SYSCON_MUTEX_2__CI__VI; -typedef union SMC_SYSCON_MUTEX_3__CI__VI regSMC_SYSCON_MUTEX_3__CI__VI; -typedef union SMC_SYSCON_RAM_CFG regSMC_SYSCON_RAM_CFG; -typedef union SMC_SYSCON_SLVCFG regSMC_SYSCON_SLVCFG; -typedef union SMC_SYSCON_SP__CI__VI regSMC_SYSCON_SP__CI__VI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_0_1__SI regSMC_SYSCON_UC_RAM_PWRDN_0_1__SI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_0__CI__VI regSMC_SYSCON_UC_RAM_PWRDN_0__CI__VI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_1__CI__VI regSMC_SYSCON_UC_RAM_PWRDN_1__CI__VI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_2_3__SI regSMC_SYSCON_UC_RAM_PWRDN_2_3__SI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_2__CI__VI regSMC_SYSCON_UC_RAM_PWRDN_2__CI__VI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_3__CI__VI regSMC_SYSCON_UC_RAM_PWRDN_3__CI__VI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_4__CI__VI regSMC_SYSCON_UC_RAM_PWRDN_4__CI__VI; -typedef union SMC_SYSCON_UC_RAM_PWRDN_4__SI regSMC_SYSCON_UC_RAM_PWRDN_4__SI; -typedef union SMC_TIMER_0_0_OCMP regSMC_TIMER_0_0_OCMP; -typedef union SMC_TIMER_0_1_OCMP regSMC_TIMER_0_1_OCMP; -typedef union SMC_TIMER_0_2_OCMP regSMC_TIMER_0_2_OCMP; -typedef union SMC_TIMER_0_3_OCMP regSMC_TIMER_0_3_OCMP; -typedef union SMC_TIMER_0_CMP_AUTOINC regSMC_TIMER_0_CMP_AUTOINC; -typedef union SMC_TIMER_0_CNT regSMC_TIMER_0_CNT; -typedef union SMC_TIMER_0_CTRL_0__CI__VI regSMC_TIMER_0_CTRL_0__CI__VI; -typedef union SMC_TIMER_0_CTRL_0__SI regSMC_TIMER_0_CTRL_0__SI; -typedef union SMC_TIMER_0_CTRL_1__CI__VI regSMC_TIMER_0_CTRL_1__CI__VI; -typedef union SMC_TIMER_0_CTRL_1__SI regSMC_TIMER_0_CTRL_1__SI; -typedef union SMC_TIMER_0_INTERRUPT regSMC_TIMER_0_INTERRUPT; -typedef union SMC_TIMER_1_0_OCMP regSMC_TIMER_1_0_OCMP; -typedef union SMC_TIMER_1_1_OCMP regSMC_TIMER_1_1_OCMP; -typedef union SMC_TIMER_1_2_OCMP regSMC_TIMER_1_2_OCMP; -typedef union SMC_TIMER_1_3_OCMP regSMC_TIMER_1_3_OCMP; -typedef union SMC_TIMER_1_CMP_AUTOINC regSMC_TIMER_1_CMP_AUTOINC; -typedef union SMC_TIMER_1_CNT regSMC_TIMER_1_CNT; -typedef union SMC_TIMER_1_CTRL_0__CI__VI regSMC_TIMER_1_CTRL_0__CI__VI; -typedef union SMC_TIMER_1_CTRL_0__SI regSMC_TIMER_1_CTRL_0__SI; -typedef union SMC_TIMER_1_CTRL_1__CI__VI regSMC_TIMER_1_CTRL_1__CI__VI; -typedef union SMC_TIMER_1_CTRL_1__SI regSMC_TIMER_1_CTRL_1__SI; -typedef union SMC_TIMER_1_INTERRUPT regSMC_TIMER_1_INTERRUPT; -typedef union SMC_TIMER_2_0_OCMP regSMC_TIMER_2_0_OCMP; -typedef union SMC_TIMER_2_1_OCMP regSMC_TIMER_2_1_OCMP; -typedef union SMC_TIMER_2_2_OCMP regSMC_TIMER_2_2_OCMP; -typedef union SMC_TIMER_2_3_OCMP regSMC_TIMER_2_3_OCMP; -typedef union SMC_TIMER_2_CMP_AUTOINC regSMC_TIMER_2_CMP_AUTOINC; -typedef union SMC_TIMER_2_CNT regSMC_TIMER_2_CNT; -typedef union SMC_TIMER_2_CTRL_0__CI__VI regSMC_TIMER_2_CTRL_0__CI__VI; -typedef union SMC_TIMER_2_CTRL_0__SI regSMC_TIMER_2_CTRL_0__SI; -typedef union SMC_TIMER_2_CTRL_1__CI__VI regSMC_TIMER_2_CTRL_1__CI__VI; -typedef union SMC_TIMER_2_CTRL_1__SI regSMC_TIMER_2_CTRL_1__SI; -typedef union SMC_TIMER_2_INTERRUPT regSMC_TIMER_2_INTERRUPT; -typedef union SMC_TIMER_3_0_OCMP regSMC_TIMER_3_0_OCMP; -typedef union SMC_TIMER_3_1_OCMP regSMC_TIMER_3_1_OCMP; -typedef union SMC_TIMER_3_2_OCMP regSMC_TIMER_3_2_OCMP; -typedef union SMC_TIMER_3_3_OCMP regSMC_TIMER_3_3_OCMP; -typedef union SMC_TIMER_3_CMP_AUTOINC regSMC_TIMER_3_CMP_AUTOINC; -typedef union SMC_TIMER_3_CNT regSMC_TIMER_3_CNT; -typedef union SMC_TIMER_3_CTRL_0__CI__VI regSMC_TIMER_3_CTRL_0__CI__VI; -typedef union SMC_TIMER_3_CTRL_0__SI regSMC_TIMER_3_CTRL_0__SI; -typedef union SMC_TIMER_3_CTRL_1__CI__VI regSMC_TIMER_3_CTRL_1__CI__VI; -typedef union SMC_TIMER_3_CTRL_1__SI regSMC_TIMER_3_CTRL_1__SI; -typedef union SMC_TIMER_3_INTERRUPT regSMC_TIMER_3_INTERRUPT; -typedef union SMC_TIMER_4_0_OCMP regSMC_TIMER_4_0_OCMP; -typedef union SMC_TIMER_4_1_OCMP regSMC_TIMER_4_1_OCMP; -typedef union SMC_TIMER_4_2_OCMP regSMC_TIMER_4_2_OCMP; -typedef union SMC_TIMER_4_3_OCMP regSMC_TIMER_4_3_OCMP; -typedef union SMC_TIMER_4_CMP_AUTOINC regSMC_TIMER_4_CMP_AUTOINC; -typedef union SMC_TIMER_4_CNT regSMC_TIMER_4_CNT; -typedef union SMC_TIMER_4_CTRL_0__CI__VI regSMC_TIMER_4_CTRL_0__CI__VI; -typedef union SMC_TIMER_4_CTRL_0__SI regSMC_TIMER_4_CTRL_0__SI; -typedef union SMC_TIMER_4_CTRL_1__CI__VI regSMC_TIMER_4_CTRL_1__CI__VI; -typedef union SMC_TIMER_4_CTRL_1__SI regSMC_TIMER_4_CTRL_1__SI; -typedef union SMC_TIMER_4_INTERRUPT regSMC_TIMER_4_INTERRUPT; -typedef union SMC_TIMER_5_0_OCMP regSMC_TIMER_5_0_OCMP; -typedef union SMC_TIMER_5_1_OCMP regSMC_TIMER_5_1_OCMP; -typedef union SMC_TIMER_5_2_OCMP regSMC_TIMER_5_2_OCMP; -typedef union SMC_TIMER_5_3_OCMP regSMC_TIMER_5_3_OCMP; -typedef union SMC_TIMER_5_CMP_AUTOINC regSMC_TIMER_5_CMP_AUTOINC; -typedef union SMC_TIMER_5_CNT regSMC_TIMER_5_CNT; -typedef union SMC_TIMER_5_CTRL_0__CI__VI regSMC_TIMER_5_CTRL_0__CI__VI; -typedef union SMC_TIMER_5_CTRL_0__SI regSMC_TIMER_5_CTRL_0__SI; -typedef union SMC_TIMER_5_CTRL_1__CI__VI regSMC_TIMER_5_CTRL_1__CI__VI; -typedef union SMC_TIMER_5_CTRL_1__SI regSMC_TIMER_5_CTRL_1__SI; -typedef union SMC_TIMER_5_INTERRUPT regSMC_TIMER_5_INTERRUPT; -typedef union SMC_TIMER_6_0_OCMP regSMC_TIMER_6_0_OCMP; -typedef union SMC_TIMER_6_1_OCMP regSMC_TIMER_6_1_OCMP; -typedef union SMC_TIMER_6_2_OCMP regSMC_TIMER_6_2_OCMP; -typedef union SMC_TIMER_6_3_OCMP regSMC_TIMER_6_3_OCMP; -typedef union SMC_TIMER_6_CMP_AUTOINC regSMC_TIMER_6_CMP_AUTOINC; -typedef union SMC_TIMER_6_CNT regSMC_TIMER_6_CNT; -typedef union SMC_TIMER_6_CTRL_0__CI__VI regSMC_TIMER_6_CTRL_0__CI__VI; -typedef union SMC_TIMER_6_CTRL_0__SI regSMC_TIMER_6_CTRL_0__SI; -typedef union SMC_TIMER_6_CTRL_1__CI__VI regSMC_TIMER_6_CTRL_1__CI__VI; -typedef union SMC_TIMER_6_CTRL_1__SI regSMC_TIMER_6_CTRL_1__SI; -typedef union SMC_TIMER_6_INTERRUPT regSMC_TIMER_6_INTERRUPT; -typedef union SMC_TIMER_7_0_OCMP regSMC_TIMER_7_0_OCMP; -typedef union SMC_TIMER_7_1_OCMP regSMC_TIMER_7_1_OCMP; -typedef union SMC_TIMER_7_2_OCMP regSMC_TIMER_7_2_OCMP; -typedef union SMC_TIMER_7_3_OCMP regSMC_TIMER_7_3_OCMP; -typedef union SMC_TIMER_7_CMP_AUTOINC regSMC_TIMER_7_CMP_AUTOINC; -typedef union SMC_TIMER_7_CNT regSMC_TIMER_7_CNT; -typedef union SMC_TIMER_7_CTRL_0__CI__VI regSMC_TIMER_7_CTRL_0__CI__VI; -typedef union SMC_TIMER_7_CTRL_0__SI regSMC_TIMER_7_CTRL_0__SI; -typedef union SMC_TIMER_7_CTRL_1__CI__VI regSMC_TIMER_7_CTRL_1__CI__VI; -typedef union SMC_TIMER_7_CTRL_1__SI regSMC_TIMER_7_CTRL_1__SI; -typedef union SMC_TIMER_7_INTERRUPT regSMC_TIMER_7_INTERRUPT; -typedef union SMC_UART_CFG__SI__CI regSMC_UART_CFG__SI__CI; -typedef union SMC_UART_CG_CNTL__CI regSMC_UART_CG_CNTL__CI; -typedef union SMC_UART_RXQ_STATUS__SI__CI regSMC_UART_RXQ_STATUS__SI__CI; -typedef union SMC_UART_RX_CFG__SI__CI regSMC_UART_RX_CFG__SI__CI; -typedef union SMC_UART_TX_Q__SI__CI regSMC_UART_TX_Q__SI__CI; -typedef union SMC_UART_TX_STATUS__SI__CI regSMC_UART_TX_STATUS__SI__CI; -typedef union SMIO_ENABLE regSMIO_ENABLE; -typedef union SMU_AUTH_STATUS__CI__VI regSMU_AUTH_STATUS__CI__VI; -typedef union SMU_BLOCKED_DATA__CI__VI regSMU_BLOCKED_DATA__CI__VI; -typedef union SMU_BRIDGE_MSTRCFG__CI__VI regSMU_BRIDGE_MSTRCFG__CI__VI; -typedef union SMU_CABLESAFE__CI__VI regSMU_CABLESAFE__CI__VI; -typedef union SMU_DFT_MISC__CI__VI regSMU_DFT_MISC__CI__VI; -typedef union SMU_DMA_ACTIVE_SAMPLE__CI__VI regSMU_DMA_ACTIVE_SAMPLE__CI__VI; -typedef union SMU_EFUSE_0__CI__VI regSMU_EFUSE_0__CI__VI; -typedef union SMU_FIRMWARE_AUTH__CI__VI regSMU_FIRMWARE_AUTH__CI__VI; -typedef union SMU_GPIOPAD_A__CI__VI regSMU_GPIOPAD_A__CI__VI; -typedef union SMU_GPIOPAD_EN__CI__VI regSMU_GPIOPAD_EN__CI__VI; -typedef union SMU_GPIOPAD_EXTERN_TRIG_CNTL__CI__VI regSMU_GPIOPAD_EXTERN_TRIG_CNTL__CI__VI; -typedef union SMU_GPIOPAD_INT_EN__CI__VI regSMU_GPIOPAD_INT_EN__CI__VI; -typedef union SMU_GPIOPAD_INT_POLARITY__CI__VI regSMU_GPIOPAD_INT_POLARITY__CI__VI; -typedef union SMU_GPIOPAD_INT_STAT_AK__CI__VI regSMU_GPIOPAD_INT_STAT_AK__CI__VI; -typedef union SMU_GPIOPAD_INT_STAT_EN__CI__VI regSMU_GPIOPAD_INT_STAT_EN__CI__VI; -typedef union SMU_GPIOPAD_INT_STAT__CI__VI regSMU_GPIOPAD_INT_STAT__CI__VI; -typedef union SMU_GPIOPAD_INT_TYPE__CI__VI regSMU_GPIOPAD_INT_TYPE__CI__VI; -typedef union SMU_GPIOPAD_MASK__CI__VI regSMU_GPIOPAD_MASK__CI__VI; -typedef union SMU_GPIOPAD_PD_EN__CI__VI regSMU_GPIOPAD_PD_EN__CI__VI; -typedef union SMU_GPIOPAD_PINSTRAPS__CI__VI regSMU_GPIOPAD_PINSTRAPS__CI__VI; -typedef union SMU_GPIOPAD_PU_EN__CI__VI regSMU_GPIOPAD_PU_EN__CI__VI; -typedef union SMU_GPIOPAD_RCVR_SEL__CI__VI regSMU_GPIOPAD_RCVR_SEL__CI__VI; -typedef union SMU_GPIOPAD_STRENGTH__CI__VI regSMU_GPIOPAD_STRENGTH__CI__VI; -typedef union SMU_GPIOPAD_SW_INT_STAT__CI__VI regSMU_GPIOPAD_SW_INT_STAT__CI__VI; -typedef union SMU_GPIOPAD_Y__CI__VI regSMU_GPIOPAD_Y__CI__VI; -typedef union SMU_IOC_CTRL__CI__VI regSMU_IOC_CTRL__CI__VI; -typedef union SMU_IOC_MSTRCFG__CI__VI regSMU_IOC_MSTRCFG__CI__VI; -typedef union SMU_IOC_PHASE1__CI__VI regSMU_IOC_PHASE1__CI__VI; -typedef union SMU_IOC_PHASE2__CI__VI regSMU_IOC_PHASE2__CI__VI; -typedef union SMU_IOC_PHASE3__CI__VI regSMU_IOC_PHASE3__CI__VI; -typedef union SMU_IOC_RDDATA__CI__VI regSMU_IOC_RDDATA__CI__VI; -typedef union SMU_KEY_READ_STATUS__CI__VI regSMU_KEY_READ_STATUS__CI__VI; -typedef union SMU_LCLK_CNTL__CI__VI regSMU_LCLK_CNTL__CI__VI; -typedef union SMU_LCLK_STATUS__CI__VI regSMU_LCLK_STATUS__CI__VI; -typedef union SMU_MAIN_PLL_OP_FREQ__CI__VI regSMU_MAIN_PLL_OP_FREQ__CI__VI; -typedef union SMU_MISC_STATUS__CI__VI regSMU_MISC_STATUS__CI__VI; -typedef union SMU_PM_MISC__CI__VI regSMU_PM_MISC__CI__VI; -typedef union SMU_PM_SIGNALS_OVERRIDE__CI__VI regSMU_PM_SIGNALS_OVERRIDE__CI__VI; -typedef union SMU_PSTATE_CONTROL__CI__VI regSMU_PSTATE_CONTROL__CI__VI; -typedef union SMU_RST_CTRL__CI__VI regSMU_RST_CTRL__CI__VI; -typedef union SMU_RST_OVERRIDE__CI__VI regSMU_RST_OVERRIDE__CI__VI; -typedef union SMU_SCLK_CNTL__CI__VI regSMU_SCLK_CNTL__CI__VI; -typedef union SMU_SCLK_STATUS__CI__VI regSMU_SCLK_STATUS__CI__VI; -typedef union SMU_SCRATCH0__CI__VI regSMU_SCRATCH0__CI__VI; -typedef union SMU_SCRATCH_A__CI__VI regSMU_SCRATCH_A__CI__VI; -typedef union SMU_SCRATCH_B__CI__VI regSMU_SCRATCH_B__CI__VI; -typedef union SMU_SCRATCH_C__CI__VI regSMU_SCRATCH_C__CI__VI; -typedef union SMU_SECURE_KEY_0__CI__VI regSMU_SECURE_KEY_0__CI__VI; -typedef union SMU_SECURE_KEY_1__CI__VI regSMU_SECURE_KEY_1__CI__VI; -typedef union SMU_SECURE_KEY_2__CI__VI regSMU_SECURE_KEY_2__CI__VI; -typedef union SMU_SECURE_KEY_3__CI__VI regSMU_SECURE_KEY_3__CI__VI; -typedef union SMU_SMC_IND_DATA__CI__VI regSMU_SMC_IND_DATA__CI__VI; -typedef union SMU_SMC_IND_INDEX__CI__VI regSMU_SMC_IND_INDEX__CI__VI; -typedef union SMU_SRAM_BLOCK_READ_HIGH_ADDR__CI__VI regSMU_SRAM_BLOCK_READ_HIGH_ADDR__CI__VI; -typedef union SMU_SRAM_BLOCK_READ_LOW_ADDR__CI__VI regSMU_SRAM_BLOCK_READ_LOW_ADDR__CI__VI; -typedef union SMU_SRAM_BLOCK_WRITE_HIGH_ADDR__CI__VI regSMU_SRAM_BLOCK_WRITE_HIGH_ADDR__CI__VI; -typedef union SMU_SRAM_BLOCK_WRITE_LOW_ADDR__CI__VI regSMU_SRAM_BLOCK_WRITE_LOW_ADDR__CI__VI; -typedef union SNAPSHOT_V_COUNTER__SI regSNAPSHOT_V_COUNTER__SI; -typedef union SPI_ARB_CYCLES_0 regSPI_ARB_CYCLES_0; -typedef union SPI_ARB_CYCLES_1 regSPI_ARB_CYCLES_1; -typedef union SPI_ARB_PRIORITY__CI__VI regSPI_ARB_PRIORITY__CI__VI; -typedef union SPI_ARB_PRIORITY__SI regSPI_ARB_PRIORITY__SI; -typedef union SPI_BARYC_CNTL regSPI_BARYC_CNTL; -typedef union SPI_CDBG_SYS_CS0__CI__VI regSPI_CDBG_SYS_CS0__CI__VI; -typedef union SPI_CDBG_SYS_CS1__CI__VI regSPI_CDBG_SYS_CS1__CI__VI; -typedef union SPI_CDBG_SYS_GFX__CI__VI regSPI_CDBG_SYS_GFX__CI__VI; -typedef union SPI_CDBG_SYS_HP3D__CI__VI regSPI_CDBG_SYS_HP3D__CI__VI; -typedef union SPI_COMPUTE_QUEUE_RESET__CI__VI regSPI_COMPUTE_QUEUE_RESET__CI__VI; -typedef union SPI_CONFIG_CNTL regSPI_CONFIG_CNTL; -typedef union SPI_CONFIG_CNTL_1 regSPI_CONFIG_CNTL_1; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI; -typedef union SPI_CSQ_WF_ACTIVE_STATUS__CI__VI regSPI_CSQ_WF_ACTIVE_STATUS__CI__VI; -typedef union SPI_DEBUG_BUSY__CI__VI regSPI_DEBUG_BUSY__CI__VI; -typedef union SPI_DEBUG_BUSY__SI regSPI_DEBUG_BUSY__SI; -typedef union SPI_DEBUG_CNTL__CI__VI regSPI_DEBUG_CNTL__CI__VI; -typedef union SPI_DEBUG_CNTL__SI regSPI_DEBUG_CNTL__SI; -typedef union SPI_DEBUG_READ regSPI_DEBUG_READ; -typedef union SPI_DYN_GPR_LOCK_EN__SI regSPI_DYN_GPR_LOCK_EN__SI; -typedef union SPI_GDBG_TBA_HI__CI__VI regSPI_GDBG_TBA_HI__CI__VI; -typedef union SPI_GDBG_TBA_LO__CI__VI regSPI_GDBG_TBA_LO__CI__VI; -typedef union SPI_GDBG_TMA_HI__CI__VI regSPI_GDBG_TMA_HI__CI__VI; -typedef union SPI_GDBG_TMA_LO__CI__VI regSPI_GDBG_TMA_LO__CI__VI; -typedef union SPI_GDBG_TRAP_CONFIG__CI__VI regSPI_GDBG_TRAP_CONFIG__CI__VI; -typedef union SPI_GDBG_TRAP_DATA0__CI__VI regSPI_GDBG_TRAP_DATA0__CI__VI; -typedef union SPI_GDBG_TRAP_DATA1__CI__VI regSPI_GDBG_TRAP_DATA1__CI__VI; -typedef union SPI_GDBG_TRAP_MASK__CI__VI regSPI_GDBG_TRAP_MASK__CI__VI; -typedef union SPI_GDBG_WAVE_CNTL__CI__VI regSPI_GDBG_WAVE_CNTL__CI__VI; -typedef union SPI_GDS_CREDITS regSPI_GDS_CREDITS; -typedef union SPI_INTERP_CONTROL_0 regSPI_INTERP_CONTROL_0; -typedef union SPI_LB_CTR_CTRL regSPI_LB_CTR_CTRL; -typedef union SPI_LB_CU_MASK regSPI_LB_CU_MASK; -typedef union SPI_LB_DATA_REG regSPI_LB_DATA_REG; -typedef union SPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI regSPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI; -typedef union SPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI regSPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI; -typedef union SPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI regSPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI; -typedef union SPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI regSPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI; -typedef union SPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI regSPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI; -typedef union SPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI regSPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI; -typedef union SPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI regSPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI; -typedef union SPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI regSPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI; -typedef union SPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI regSPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI; -typedef union SPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI regSPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI; -typedef union SPI_PERFCOUNTER0_HI regSPI_PERFCOUNTER0_HI; -typedef union SPI_PERFCOUNTER0_LO regSPI_PERFCOUNTER0_LO; -typedef union SPI_PERFCOUNTER0_SELECT regSPI_PERFCOUNTER0_SELECT; -typedef union SPI_PERFCOUNTER0_SELECT1__CI__VI regSPI_PERFCOUNTER0_SELECT1__CI__VI; -typedef union SPI_PERFCOUNTER1_HI regSPI_PERFCOUNTER1_HI; -typedef union SPI_PERFCOUNTER1_LO regSPI_PERFCOUNTER1_LO; -typedef union SPI_PERFCOUNTER1_SELECT regSPI_PERFCOUNTER1_SELECT; -typedef union SPI_PERFCOUNTER1_SELECT1__CI__VI regSPI_PERFCOUNTER1_SELECT1__CI__VI; -typedef union SPI_PERFCOUNTER2_HI regSPI_PERFCOUNTER2_HI; -typedef union SPI_PERFCOUNTER2_LO regSPI_PERFCOUNTER2_LO; -typedef union SPI_PERFCOUNTER2_SELECT regSPI_PERFCOUNTER2_SELECT; -typedef union SPI_PERFCOUNTER2_SELECT1__CI__VI regSPI_PERFCOUNTER2_SELECT1__CI__VI; -typedef union SPI_PERFCOUNTER3_HI regSPI_PERFCOUNTER3_HI; -typedef union SPI_PERFCOUNTER3_LO regSPI_PERFCOUNTER3_LO; -typedef union SPI_PERFCOUNTER3_SELECT regSPI_PERFCOUNTER3_SELECT; -typedef union SPI_PERFCOUNTER3_SELECT1__CI__VI regSPI_PERFCOUNTER3_SELECT1__CI__VI; -typedef union SPI_PERFCOUNTER4_HI__CI__VI regSPI_PERFCOUNTER4_HI__CI__VI; -typedef union SPI_PERFCOUNTER4_LO__CI__VI regSPI_PERFCOUNTER4_LO__CI__VI; -typedef union SPI_PERFCOUNTER4_SELECT__CI__VI regSPI_PERFCOUNTER4_SELECT__CI__VI; -typedef union SPI_PERFCOUNTER5_HI__CI__VI regSPI_PERFCOUNTER5_HI__CI__VI; -typedef union SPI_PERFCOUNTER5_LO__CI__VI regSPI_PERFCOUNTER5_LO__CI__VI; -typedef union SPI_PERFCOUNTER5_SELECT__CI__VI regSPI_PERFCOUNTER5_SELECT__CI__VI; -typedef union SPI_PERFCOUNTER_BINS regSPI_PERFCOUNTER_BINS; -typedef union SPI_PG_ENABLE_STATIC_CU_MASK regSPI_PG_ENABLE_STATIC_CU_MASK; -typedef union SPI_PS_INPUT_ADDR regSPI_PS_INPUT_ADDR; -typedef union SPI_PS_INPUT_CNTL_0 regSPI_PS_INPUT_CNTL_0; -typedef union SPI_PS_INPUT_CNTL_1 regSPI_PS_INPUT_CNTL_1; -typedef union SPI_PS_INPUT_CNTL_10 regSPI_PS_INPUT_CNTL_10; -typedef union SPI_PS_INPUT_CNTL_11 regSPI_PS_INPUT_CNTL_11; -typedef union SPI_PS_INPUT_CNTL_12 regSPI_PS_INPUT_CNTL_12; -typedef union SPI_PS_INPUT_CNTL_13 regSPI_PS_INPUT_CNTL_13; -typedef union SPI_PS_INPUT_CNTL_14 regSPI_PS_INPUT_CNTL_14; -typedef union SPI_PS_INPUT_CNTL_15 regSPI_PS_INPUT_CNTL_15; -typedef union SPI_PS_INPUT_CNTL_16 regSPI_PS_INPUT_CNTL_16; -typedef union SPI_PS_INPUT_CNTL_17 regSPI_PS_INPUT_CNTL_17; -typedef union SPI_PS_INPUT_CNTL_18 regSPI_PS_INPUT_CNTL_18; -typedef union SPI_PS_INPUT_CNTL_19 regSPI_PS_INPUT_CNTL_19; -typedef union SPI_PS_INPUT_CNTL_2 regSPI_PS_INPUT_CNTL_2; -typedef union SPI_PS_INPUT_CNTL_20 regSPI_PS_INPUT_CNTL_20; -typedef union SPI_PS_INPUT_CNTL_21 regSPI_PS_INPUT_CNTL_21; -typedef union SPI_PS_INPUT_CNTL_22 regSPI_PS_INPUT_CNTL_22; -typedef union SPI_PS_INPUT_CNTL_23 regSPI_PS_INPUT_CNTL_23; -typedef union SPI_PS_INPUT_CNTL_24 regSPI_PS_INPUT_CNTL_24; -typedef union SPI_PS_INPUT_CNTL_25 regSPI_PS_INPUT_CNTL_25; -typedef union SPI_PS_INPUT_CNTL_26 regSPI_PS_INPUT_CNTL_26; -typedef union SPI_PS_INPUT_CNTL_27 regSPI_PS_INPUT_CNTL_27; -typedef union SPI_PS_INPUT_CNTL_28 regSPI_PS_INPUT_CNTL_28; -typedef union SPI_PS_INPUT_CNTL_29 regSPI_PS_INPUT_CNTL_29; -typedef union SPI_PS_INPUT_CNTL_3 regSPI_PS_INPUT_CNTL_3; -typedef union SPI_PS_INPUT_CNTL_30 regSPI_PS_INPUT_CNTL_30; -typedef union SPI_PS_INPUT_CNTL_31 regSPI_PS_INPUT_CNTL_31; -typedef union SPI_PS_INPUT_CNTL_4 regSPI_PS_INPUT_CNTL_4; -typedef union SPI_PS_INPUT_CNTL_5 regSPI_PS_INPUT_CNTL_5; -typedef union SPI_PS_INPUT_CNTL_6 regSPI_PS_INPUT_CNTL_6; -typedef union SPI_PS_INPUT_CNTL_7 regSPI_PS_INPUT_CNTL_7; -typedef union SPI_PS_INPUT_CNTL_8 regSPI_PS_INPUT_CNTL_8; -typedef union SPI_PS_INPUT_CNTL_9 regSPI_PS_INPUT_CNTL_9; -typedef union SPI_PS_INPUT_ENA regSPI_PS_INPUT_ENA; -typedef union SPI_PS_IN_CONTROL regSPI_PS_IN_CONTROL; -typedef union SPI_PS_MAX_WAVE_ID regSPI_PS_MAX_WAVE_ID; -typedef union SPI_RESET_DEBUG__CI__VI regSPI_RESET_DEBUG__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_0__CI__VI regSPI_RESOURCE_RESERVE_CU_0__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_10__CI__VI regSPI_RESOURCE_RESERVE_CU_10__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_11__CI__VI regSPI_RESOURCE_RESERVE_CU_11__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_1__CI__VI regSPI_RESOURCE_RESERVE_CU_1__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_2__CI__VI regSPI_RESOURCE_RESERVE_CU_2__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_3__CI__VI regSPI_RESOURCE_RESERVE_CU_3__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_4__CI__VI regSPI_RESOURCE_RESERVE_CU_4__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_5__CI__VI regSPI_RESOURCE_RESERVE_CU_5__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_6__CI__VI regSPI_RESOURCE_RESERVE_CU_6__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_7__CI__VI regSPI_RESOURCE_RESERVE_CU_7__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_8__CI__VI regSPI_RESOURCE_RESERVE_CU_8__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_9__CI__VI regSPI_RESOURCE_RESERVE_CU_9__CI__VI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_0__SI regSPI_RESOURCE_RESERVE_CU_AB_0__SI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_1__SI regSPI_RESOURCE_RESERVE_CU_AB_1__SI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_2__SI regSPI_RESOURCE_RESERVE_CU_AB_2__SI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_3__SI regSPI_RESOURCE_RESERVE_CU_AB_3__SI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_4__SI regSPI_RESOURCE_RESERVE_CU_AB_4__SI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_5__SI regSPI_RESOURCE_RESERVE_CU_AB_5__SI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_6__SI regSPI_RESOURCE_RESERVE_CU_AB_6__SI; -typedef union SPI_RESOURCE_RESERVE_CU_AB_7__SI regSPI_RESOURCE_RESERVE_CU_AB_7__SI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_0__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_0__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_10__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_10__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_11__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_11__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_1__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_1__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_2__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_2__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_3__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_3__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_4__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_4__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_5__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_5__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_6__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_6__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_7__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_7__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_8__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_8__CI__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_9__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_9__CI__VI; -typedef union SPI_SHADER_COL_FORMAT regSPI_SHADER_COL_FORMAT; -typedef union SPI_SHADER_LATE_ALLOC_VS__CI__VI regSPI_SHADER_LATE_ALLOC_VS__CI__VI; -typedef union SPI_SHADER_PGM_HI_ES regSPI_SHADER_PGM_HI_ES; -typedef union SPI_SHADER_PGM_HI_GS regSPI_SHADER_PGM_HI_GS; -typedef union SPI_SHADER_PGM_HI_HS regSPI_SHADER_PGM_HI_HS; -typedef union SPI_SHADER_PGM_HI_LS regSPI_SHADER_PGM_HI_LS; -typedef union SPI_SHADER_PGM_HI_PS regSPI_SHADER_PGM_HI_PS; -typedef union SPI_SHADER_PGM_HI_VS regSPI_SHADER_PGM_HI_VS; -typedef union SPI_SHADER_PGM_LO_ES regSPI_SHADER_PGM_LO_ES; -typedef union SPI_SHADER_PGM_LO_GS regSPI_SHADER_PGM_LO_GS; -typedef union SPI_SHADER_PGM_LO_HS regSPI_SHADER_PGM_LO_HS; -typedef union SPI_SHADER_PGM_LO_LS regSPI_SHADER_PGM_LO_LS; -typedef union SPI_SHADER_PGM_LO_PS regSPI_SHADER_PGM_LO_PS; -typedef union SPI_SHADER_PGM_LO_VS regSPI_SHADER_PGM_LO_VS; -typedef union SPI_SHADER_PGM_RSRC1_ES regSPI_SHADER_PGM_RSRC1_ES; -typedef union SPI_SHADER_PGM_RSRC1_GS regSPI_SHADER_PGM_RSRC1_GS; -typedef union SPI_SHADER_PGM_RSRC1_HS regSPI_SHADER_PGM_RSRC1_HS; -typedef union SPI_SHADER_PGM_RSRC1_LS regSPI_SHADER_PGM_RSRC1_LS; -typedef union SPI_SHADER_PGM_RSRC1_PS regSPI_SHADER_PGM_RSRC1_PS; -typedef union SPI_SHADER_PGM_RSRC1_VS regSPI_SHADER_PGM_RSRC1_VS; -typedef union SPI_SHADER_PGM_RSRC2_ES regSPI_SHADER_PGM_RSRC2_ES; -typedef union SPI_SHADER_PGM_RSRC2_ES_GS__CI__VI regSPI_SHADER_PGM_RSRC2_ES_GS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC2_ES_VS__CI__VI regSPI_SHADER_PGM_RSRC2_ES_VS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC2_GS regSPI_SHADER_PGM_RSRC2_GS; -typedef union SPI_SHADER_PGM_RSRC2_HS regSPI_SHADER_PGM_RSRC2_HS; -typedef union SPI_SHADER_PGM_RSRC2_LS regSPI_SHADER_PGM_RSRC2_LS; -typedef union SPI_SHADER_PGM_RSRC2_LS_ES__CI__VI regSPI_SHADER_PGM_RSRC2_LS_ES__CI__VI; -typedef union SPI_SHADER_PGM_RSRC2_LS_HS__CI__VI regSPI_SHADER_PGM_RSRC2_LS_HS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC2_LS_VS__CI__VI regSPI_SHADER_PGM_RSRC2_LS_VS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC2_PS regSPI_SHADER_PGM_RSRC2_PS; -typedef union SPI_SHADER_PGM_RSRC2_VS regSPI_SHADER_PGM_RSRC2_VS; -typedef union SPI_SHADER_PGM_RSRC3_ES__CI__VI regSPI_SHADER_PGM_RSRC3_ES__CI__VI; -typedef union SPI_SHADER_PGM_RSRC3_GS__CI__VI regSPI_SHADER_PGM_RSRC3_GS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC3_HS__CI__VI regSPI_SHADER_PGM_RSRC3_HS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC3_LS__CI__VI regSPI_SHADER_PGM_RSRC3_LS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC3_PS__CI__VI regSPI_SHADER_PGM_RSRC3_PS__CI__VI; -typedef union SPI_SHADER_PGM_RSRC3_VS__CI__VI regSPI_SHADER_PGM_RSRC3_VS__CI__VI; -typedef union SPI_SHADER_POS_FORMAT regSPI_SHADER_POS_FORMAT; -typedef union SPI_SHADER_TBA_HI_ES regSPI_SHADER_TBA_HI_ES; -typedef union SPI_SHADER_TBA_HI_GS regSPI_SHADER_TBA_HI_GS; -typedef union SPI_SHADER_TBA_HI_HS regSPI_SHADER_TBA_HI_HS; -typedef union SPI_SHADER_TBA_HI_LS regSPI_SHADER_TBA_HI_LS; -typedef union SPI_SHADER_TBA_HI_PS regSPI_SHADER_TBA_HI_PS; -typedef union SPI_SHADER_TBA_HI_VS regSPI_SHADER_TBA_HI_VS; -typedef union SPI_SHADER_TBA_LO_ES regSPI_SHADER_TBA_LO_ES; -typedef union SPI_SHADER_TBA_LO_GS regSPI_SHADER_TBA_LO_GS; -typedef union SPI_SHADER_TBA_LO_HS regSPI_SHADER_TBA_LO_HS; -typedef union SPI_SHADER_TBA_LO_LS regSPI_SHADER_TBA_LO_LS; -typedef union SPI_SHADER_TBA_LO_PS regSPI_SHADER_TBA_LO_PS; -typedef union SPI_SHADER_TBA_LO_VS regSPI_SHADER_TBA_LO_VS; -typedef union SPI_SHADER_TMA_HI_ES regSPI_SHADER_TMA_HI_ES; -typedef union SPI_SHADER_TMA_HI_GS regSPI_SHADER_TMA_HI_GS; -typedef union SPI_SHADER_TMA_HI_HS regSPI_SHADER_TMA_HI_HS; -typedef union SPI_SHADER_TMA_HI_LS regSPI_SHADER_TMA_HI_LS; -typedef union SPI_SHADER_TMA_HI_PS regSPI_SHADER_TMA_HI_PS; -typedef union SPI_SHADER_TMA_HI_VS regSPI_SHADER_TMA_HI_VS; -typedef union SPI_SHADER_TMA_LO_ES regSPI_SHADER_TMA_LO_ES; -typedef union SPI_SHADER_TMA_LO_GS regSPI_SHADER_TMA_LO_GS; -typedef union SPI_SHADER_TMA_LO_HS regSPI_SHADER_TMA_LO_HS; -typedef union SPI_SHADER_TMA_LO_LS regSPI_SHADER_TMA_LO_LS; -typedef union SPI_SHADER_TMA_LO_PS regSPI_SHADER_TMA_LO_PS; -typedef union SPI_SHADER_TMA_LO_VS regSPI_SHADER_TMA_LO_VS; -typedef union SPI_SHADER_USER_DATA_ES_0 regSPI_SHADER_USER_DATA_ES_0; -typedef union SPI_SHADER_USER_DATA_ES_1 regSPI_SHADER_USER_DATA_ES_1; -typedef union SPI_SHADER_USER_DATA_ES_10 regSPI_SHADER_USER_DATA_ES_10; -typedef union SPI_SHADER_USER_DATA_ES_11 regSPI_SHADER_USER_DATA_ES_11; -typedef union SPI_SHADER_USER_DATA_ES_12 regSPI_SHADER_USER_DATA_ES_12; -typedef union SPI_SHADER_USER_DATA_ES_13 regSPI_SHADER_USER_DATA_ES_13; -typedef union SPI_SHADER_USER_DATA_ES_14 regSPI_SHADER_USER_DATA_ES_14; -typedef union SPI_SHADER_USER_DATA_ES_15 regSPI_SHADER_USER_DATA_ES_15; -typedef union SPI_SHADER_USER_DATA_ES_2 regSPI_SHADER_USER_DATA_ES_2; -typedef union SPI_SHADER_USER_DATA_ES_3 regSPI_SHADER_USER_DATA_ES_3; -typedef union SPI_SHADER_USER_DATA_ES_4 regSPI_SHADER_USER_DATA_ES_4; -typedef union SPI_SHADER_USER_DATA_ES_5 regSPI_SHADER_USER_DATA_ES_5; -typedef union SPI_SHADER_USER_DATA_ES_6 regSPI_SHADER_USER_DATA_ES_6; -typedef union SPI_SHADER_USER_DATA_ES_7 regSPI_SHADER_USER_DATA_ES_7; -typedef union SPI_SHADER_USER_DATA_ES_8 regSPI_SHADER_USER_DATA_ES_8; -typedef union SPI_SHADER_USER_DATA_ES_9 regSPI_SHADER_USER_DATA_ES_9; -typedef union SPI_SHADER_USER_DATA_GS_0 regSPI_SHADER_USER_DATA_GS_0; -typedef union SPI_SHADER_USER_DATA_GS_1 regSPI_SHADER_USER_DATA_GS_1; -typedef union SPI_SHADER_USER_DATA_GS_10 regSPI_SHADER_USER_DATA_GS_10; -typedef union SPI_SHADER_USER_DATA_GS_11 regSPI_SHADER_USER_DATA_GS_11; -typedef union SPI_SHADER_USER_DATA_GS_12 regSPI_SHADER_USER_DATA_GS_12; -typedef union SPI_SHADER_USER_DATA_GS_13 regSPI_SHADER_USER_DATA_GS_13; -typedef union SPI_SHADER_USER_DATA_GS_14 regSPI_SHADER_USER_DATA_GS_14; -typedef union SPI_SHADER_USER_DATA_GS_15 regSPI_SHADER_USER_DATA_GS_15; -typedef union SPI_SHADER_USER_DATA_GS_2 regSPI_SHADER_USER_DATA_GS_2; -typedef union SPI_SHADER_USER_DATA_GS_3 regSPI_SHADER_USER_DATA_GS_3; -typedef union SPI_SHADER_USER_DATA_GS_4 regSPI_SHADER_USER_DATA_GS_4; -typedef union SPI_SHADER_USER_DATA_GS_5 regSPI_SHADER_USER_DATA_GS_5; -typedef union SPI_SHADER_USER_DATA_GS_6 regSPI_SHADER_USER_DATA_GS_6; -typedef union SPI_SHADER_USER_DATA_GS_7 regSPI_SHADER_USER_DATA_GS_7; -typedef union SPI_SHADER_USER_DATA_GS_8 regSPI_SHADER_USER_DATA_GS_8; -typedef union SPI_SHADER_USER_DATA_GS_9 regSPI_SHADER_USER_DATA_GS_9; -typedef union SPI_SHADER_USER_DATA_HS_0 regSPI_SHADER_USER_DATA_HS_0; -typedef union SPI_SHADER_USER_DATA_HS_1 regSPI_SHADER_USER_DATA_HS_1; -typedef union SPI_SHADER_USER_DATA_HS_10 regSPI_SHADER_USER_DATA_HS_10; -typedef union SPI_SHADER_USER_DATA_HS_11 regSPI_SHADER_USER_DATA_HS_11; -typedef union SPI_SHADER_USER_DATA_HS_12 regSPI_SHADER_USER_DATA_HS_12; -typedef union SPI_SHADER_USER_DATA_HS_13 regSPI_SHADER_USER_DATA_HS_13; -typedef union SPI_SHADER_USER_DATA_HS_14 regSPI_SHADER_USER_DATA_HS_14; -typedef union SPI_SHADER_USER_DATA_HS_15 regSPI_SHADER_USER_DATA_HS_15; -typedef union SPI_SHADER_USER_DATA_HS_2 regSPI_SHADER_USER_DATA_HS_2; -typedef union SPI_SHADER_USER_DATA_HS_3 regSPI_SHADER_USER_DATA_HS_3; -typedef union SPI_SHADER_USER_DATA_HS_4 regSPI_SHADER_USER_DATA_HS_4; -typedef union SPI_SHADER_USER_DATA_HS_5 regSPI_SHADER_USER_DATA_HS_5; -typedef union SPI_SHADER_USER_DATA_HS_6 regSPI_SHADER_USER_DATA_HS_6; -typedef union SPI_SHADER_USER_DATA_HS_7 regSPI_SHADER_USER_DATA_HS_7; -typedef union SPI_SHADER_USER_DATA_HS_8 regSPI_SHADER_USER_DATA_HS_8; -typedef union SPI_SHADER_USER_DATA_HS_9 regSPI_SHADER_USER_DATA_HS_9; -typedef union SPI_SHADER_USER_DATA_LS_0 regSPI_SHADER_USER_DATA_LS_0; -typedef union SPI_SHADER_USER_DATA_LS_1 regSPI_SHADER_USER_DATA_LS_1; -typedef union SPI_SHADER_USER_DATA_LS_10 regSPI_SHADER_USER_DATA_LS_10; -typedef union SPI_SHADER_USER_DATA_LS_11 regSPI_SHADER_USER_DATA_LS_11; -typedef union SPI_SHADER_USER_DATA_LS_12 regSPI_SHADER_USER_DATA_LS_12; -typedef union SPI_SHADER_USER_DATA_LS_13 regSPI_SHADER_USER_DATA_LS_13; -typedef union SPI_SHADER_USER_DATA_LS_14 regSPI_SHADER_USER_DATA_LS_14; -typedef union SPI_SHADER_USER_DATA_LS_15 regSPI_SHADER_USER_DATA_LS_15; -typedef union SPI_SHADER_USER_DATA_LS_2 regSPI_SHADER_USER_DATA_LS_2; -typedef union SPI_SHADER_USER_DATA_LS_3 regSPI_SHADER_USER_DATA_LS_3; -typedef union SPI_SHADER_USER_DATA_LS_4 regSPI_SHADER_USER_DATA_LS_4; -typedef union SPI_SHADER_USER_DATA_LS_5 regSPI_SHADER_USER_DATA_LS_5; -typedef union SPI_SHADER_USER_DATA_LS_6 regSPI_SHADER_USER_DATA_LS_6; -typedef union SPI_SHADER_USER_DATA_LS_7 regSPI_SHADER_USER_DATA_LS_7; -typedef union SPI_SHADER_USER_DATA_LS_8 regSPI_SHADER_USER_DATA_LS_8; -typedef union SPI_SHADER_USER_DATA_LS_9 regSPI_SHADER_USER_DATA_LS_9; -typedef union SPI_SHADER_USER_DATA_PS_0 regSPI_SHADER_USER_DATA_PS_0; -typedef union SPI_SHADER_USER_DATA_PS_1 regSPI_SHADER_USER_DATA_PS_1; -typedef union SPI_SHADER_USER_DATA_PS_10 regSPI_SHADER_USER_DATA_PS_10; -typedef union SPI_SHADER_USER_DATA_PS_11 regSPI_SHADER_USER_DATA_PS_11; -typedef union SPI_SHADER_USER_DATA_PS_12 regSPI_SHADER_USER_DATA_PS_12; -typedef union SPI_SHADER_USER_DATA_PS_13 regSPI_SHADER_USER_DATA_PS_13; -typedef union SPI_SHADER_USER_DATA_PS_14 regSPI_SHADER_USER_DATA_PS_14; -typedef union SPI_SHADER_USER_DATA_PS_15 regSPI_SHADER_USER_DATA_PS_15; -typedef union SPI_SHADER_USER_DATA_PS_2 regSPI_SHADER_USER_DATA_PS_2; -typedef union SPI_SHADER_USER_DATA_PS_3 regSPI_SHADER_USER_DATA_PS_3; -typedef union SPI_SHADER_USER_DATA_PS_4 regSPI_SHADER_USER_DATA_PS_4; -typedef union SPI_SHADER_USER_DATA_PS_5 regSPI_SHADER_USER_DATA_PS_5; -typedef union SPI_SHADER_USER_DATA_PS_6 regSPI_SHADER_USER_DATA_PS_6; -typedef union SPI_SHADER_USER_DATA_PS_7 regSPI_SHADER_USER_DATA_PS_7; -typedef union SPI_SHADER_USER_DATA_PS_8 regSPI_SHADER_USER_DATA_PS_8; -typedef union SPI_SHADER_USER_DATA_PS_9 regSPI_SHADER_USER_DATA_PS_9; -typedef union SPI_SHADER_USER_DATA_VS_0 regSPI_SHADER_USER_DATA_VS_0; -typedef union SPI_SHADER_USER_DATA_VS_1 regSPI_SHADER_USER_DATA_VS_1; -typedef union SPI_SHADER_USER_DATA_VS_10 regSPI_SHADER_USER_DATA_VS_10; -typedef union SPI_SHADER_USER_DATA_VS_11 regSPI_SHADER_USER_DATA_VS_11; -typedef union SPI_SHADER_USER_DATA_VS_12 regSPI_SHADER_USER_DATA_VS_12; -typedef union SPI_SHADER_USER_DATA_VS_13 regSPI_SHADER_USER_DATA_VS_13; -typedef union SPI_SHADER_USER_DATA_VS_14 regSPI_SHADER_USER_DATA_VS_14; -typedef union SPI_SHADER_USER_DATA_VS_15 regSPI_SHADER_USER_DATA_VS_15; -typedef union SPI_SHADER_USER_DATA_VS_2 regSPI_SHADER_USER_DATA_VS_2; -typedef union SPI_SHADER_USER_DATA_VS_3 regSPI_SHADER_USER_DATA_VS_3; -typedef union SPI_SHADER_USER_DATA_VS_4 regSPI_SHADER_USER_DATA_VS_4; -typedef union SPI_SHADER_USER_DATA_VS_5 regSPI_SHADER_USER_DATA_VS_5; -typedef union SPI_SHADER_USER_DATA_VS_6 regSPI_SHADER_USER_DATA_VS_6; -typedef union SPI_SHADER_USER_DATA_VS_7 regSPI_SHADER_USER_DATA_VS_7; -typedef union SPI_SHADER_USER_DATA_VS_8 regSPI_SHADER_USER_DATA_VS_8; -typedef union SPI_SHADER_USER_DATA_VS_9 regSPI_SHADER_USER_DATA_VS_9; -typedef union SPI_SHADER_Z_FORMAT regSPI_SHADER_Z_FORMAT; -typedef union SPI_SLAVE_DEBUG_BUSY regSPI_SLAVE_DEBUG_BUSY; -typedef union SPI_STATIC_THREAD_MGMT_1__SI regSPI_STATIC_THREAD_MGMT_1__SI; -typedef union SPI_STATIC_THREAD_MGMT_2__SI regSPI_STATIC_THREAD_MGMT_2__SI; -typedef union SPI_STATIC_THREAD_MGMT_3__SI regSPI_STATIC_THREAD_MGMT_3__SI; -typedef union SPI_SX_EXPORT_BUFFER_SIZES regSPI_SX_EXPORT_BUFFER_SIZES; -typedef union SPI_SX_SCOREBOARD_BUFFER_SIZES regSPI_SX_SCOREBOARD_BUFFER_SIZES; -typedef union SPI_TMPRING_SIZE regSPI_TMPRING_SIZE; -typedef union SPI_VS_OUT_CONFIG regSPI_VS_OUT_CONFIG; -typedef union SPI_WAVE_MGMT_1__SI regSPI_WAVE_MGMT_1__SI; -typedef union SPI_WAVE_MGMT_2__SI regSPI_WAVE_MGMT_2__SI; -typedef union SPI_WCL_PIPE_PERCENT_CS0__CI__VI regSPI_WCL_PIPE_PERCENT_CS0__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_CS1__CI__VI regSPI_WCL_PIPE_PERCENT_CS1__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_CS2__CI__VI regSPI_WCL_PIPE_PERCENT_CS2__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_CS3__CI__VI regSPI_WCL_PIPE_PERCENT_CS3__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_CS4__CI__VI regSPI_WCL_PIPE_PERCENT_CS4__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_CS5__CI__VI regSPI_WCL_PIPE_PERCENT_CS5__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_CS6__CI__VI regSPI_WCL_PIPE_PERCENT_CS6__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_CS7__CI__VI regSPI_WCL_PIPE_PERCENT_CS7__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_GFX__CI__VI regSPI_WCL_PIPE_PERCENT_GFX__CI__VI; -typedef union SPI_WCL_PIPE_PERCENT_HP3D__CI__VI regSPI_WCL_PIPE_PERCENT_HP3D__CI__VI; -typedef union SPI_WF_LIFETIME_CNTL__CI__VI regSPI_WF_LIFETIME_CNTL__CI__VI; -typedef union SPI_WF_LIFETIME_DEBUG__CI__VI regSPI_WF_LIFETIME_DEBUG__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_0__CI__VI regSPI_WF_LIFETIME_LIMIT_0__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_1__CI__VI regSPI_WF_LIFETIME_LIMIT_1__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_2__CI__VI regSPI_WF_LIFETIME_LIMIT_2__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_3__CI__VI regSPI_WF_LIFETIME_LIMIT_3__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_4__CI__VI regSPI_WF_LIFETIME_LIMIT_4__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_5__CI__VI regSPI_WF_LIFETIME_LIMIT_5__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_6__CI__VI regSPI_WF_LIFETIME_LIMIT_6__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_7__CI__VI regSPI_WF_LIFETIME_LIMIT_7__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_8__CI__VI regSPI_WF_LIFETIME_LIMIT_8__CI__VI; -typedef union SPI_WF_LIFETIME_LIMIT_9__CI__VI regSPI_WF_LIFETIME_LIMIT_9__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_0__CI__VI regSPI_WF_LIFETIME_STATUS_0__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_10__CI__VI regSPI_WF_LIFETIME_STATUS_10__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_11__CI__VI regSPI_WF_LIFETIME_STATUS_11__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_12__CI__VI regSPI_WF_LIFETIME_STATUS_12__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_13__CI__VI regSPI_WF_LIFETIME_STATUS_13__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_14__CI__VI regSPI_WF_LIFETIME_STATUS_14__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_15__CI__VI regSPI_WF_LIFETIME_STATUS_15__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_16__CI__VI regSPI_WF_LIFETIME_STATUS_16__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_17__CI__VI regSPI_WF_LIFETIME_STATUS_17__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_18__CI__VI regSPI_WF_LIFETIME_STATUS_18__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_19__CI__VI regSPI_WF_LIFETIME_STATUS_19__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_1__CI__VI regSPI_WF_LIFETIME_STATUS_1__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_20__CI__VI regSPI_WF_LIFETIME_STATUS_20__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_2__CI__VI regSPI_WF_LIFETIME_STATUS_2__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_3__CI__VI regSPI_WF_LIFETIME_STATUS_3__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_4__CI__VI regSPI_WF_LIFETIME_STATUS_4__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_5__CI__VI regSPI_WF_LIFETIME_STATUS_5__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_6__CI__VI regSPI_WF_LIFETIME_STATUS_6__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_7__CI__VI regSPI_WF_LIFETIME_STATUS_7__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_8__CI__VI regSPI_WF_LIFETIME_STATUS_8__CI__VI; -typedef union SPI_WF_LIFETIME_STATUS_9__CI__VI regSPI_WF_LIFETIME_STATUS_9__CI__VI; -typedef union SPLL_CNTL_MODE__CI__VI regSPLL_CNTL_MODE__CI__VI; -typedef union SPLL_CNTL_MODE__SI regSPLL_CNTL_MODE__SI; -typedef union SPLL_TIME regSPLL_TIME; -typedef union SPMI_C6_STATE_0__CI__VI regSPMI_C6_STATE_0__CI__VI; -typedef union SPMI_C6_STATE_1__CI regSPMI_C6_STATE_1__CI; -typedef union SPMI_CONFIG_0_0__CI regSPMI_CONFIG_0_0__CI; -typedef union SPMI_CONFIG_0_1__CI regSPMI_CONFIG_0_1__CI; -typedef union SPMI_CONFIG_1_0__CI regSPMI_CONFIG_1_0__CI; -typedef union SPMI_CONFIG_1_1__CI regSPMI_CONFIG_1_1__CI; -typedef union SPMI_FSM_BUSY_0__CI__VI regSPMI_FSM_BUSY_0__CI__VI; -typedef union SPMI_FSM_BUSY_1__CI regSPMI_FSM_BUSY_1__CI; -typedef union SPMI_FSM_READ_TRIGGER_0__CI__VI regSPMI_FSM_READ_TRIGGER_0__CI__VI; -typedef union SPMI_FSM_READ_TRIGGER_1__CI regSPMI_FSM_READ_TRIGGER_1__CI; -typedef union SPMI_FSM_RESET_TRIGGER_0__CI__VI regSPMI_FSM_RESET_TRIGGER_0__CI__VI; -typedef union SPMI_FSM_RESET_TRIGGER_1__CI regSPMI_FSM_RESET_TRIGGER_1__CI; -typedef union SPMI_FSM_WRITE_TRIGGER_0__CI__VI regSPMI_FSM_WRITE_TRIGGER_0__CI__VI; -typedef union SPMI_FSM_WRITE_TRIGGER_1__CI regSPMI_FSM_WRITE_TRIGGER_1__CI; -typedef union SPMI_IND_ADDR__CI__VI regSPMI_IND_ADDR__CI__VI; -typedef union SPMI_IND_DATA__CI__VI regSPMI_IND_DATA__CI__VI; -typedef union SPMI_JTAG_OVER_0__CI__VI regSPMI_JTAG_OVER_0__CI__VI; -typedef union SPMI_JTAG_OVER_1__CI regSPMI_JTAG_OVER_1__CI; -typedef union SPMI_PATH_0__CI__VI regSPMI_PATH_0__CI__VI; -typedef union SPMI_PATH_1__CI regSPMI_PATH_1__CI; -typedef union SPMI_RESET__CI regSPMI_RESET__CI; -typedef union SPMI_RESET__VI regSPMI_RESET__VI; -typedef union SPMI_SMC_IND_DATA__CI__VI regSPMI_SMC_IND_DATA__CI__VI; -typedef union SPMI_SMC_IND_INDEX__CI__VI regSPMI_SMC_IND_INDEX__CI__VI; -typedef union SPMI_SRAM_ADDRESS__CI__VI regSPMI_SRAM_ADDRESS__CI__VI; -typedef union SPMI_SRAM_DATA__CI__VI regSPMI_SRAM_DATA__CI__VI; -typedef union SPMI_TIMER__CI regSPMI_TIMER__CI; -typedef union SQC_CACHES__SI__CI regSQC_CACHES__SI__CI; -typedef union SQC_CACHES__VI regSQC_CACHES__VI; -typedef union SQC_CONFIG regSQC_CONFIG; -typedef union SQC_POLICY__CI regSQC_POLICY__CI; -typedef union SQC_SECDED_CNT__SI__CI regSQC_SECDED_CNT__SI__CI; -typedef union SQC_VOLATILE__CI regSQC_VOLATILE__CI; -typedef union SQ_ALU_CLK_CTRL regSQ_ALU_CLK_CTRL; -typedef union SQ_BUF_RSRC_WORD0 regSQ_BUF_RSRC_WORD0; -typedef union SQ_BUF_RSRC_WORD1 regSQ_BUF_RSRC_WORD1; -typedef union SQ_BUF_RSRC_WORD2 regSQ_BUF_RSRC_WORD2; -typedef union SQ_BUF_RSRC_WORD3 regSQ_BUF_RSRC_WORD3; -typedef union SQ_CAC_MASK__SI regSQ_CAC_MASK__SI; -typedef union SQ_CMD_TIMESTAMP__CI__VI regSQ_CMD_TIMESTAMP__CI__VI; -typedef union SQ_CMD__CI regSQ_CMD__CI; -typedef union SQ_CMD__VI regSQ_CMD__VI; -typedef union SQ_CONFIG__SI__CI regSQ_CONFIG__SI__CI; -typedef union SQ_CONFIG__VI regSQ_CONFIG__VI; -typedef union SQ_DEBUG_CTRL_LOCAL regSQ_DEBUG_CTRL_LOCAL; -typedef union SQ_DEBUG_STS_GLOBAL regSQ_DEBUG_STS_GLOBAL; -typedef union SQ_DEBUG_STS_GLOBAL2__CI__VI regSQ_DEBUG_STS_GLOBAL2__CI__VI; -typedef union SQ_DEBUG_STS_GLOBAL3__CI__VI regSQ_DEBUG_STS_GLOBAL3__CI__VI; -typedef union SQ_DEBUG_STS_LOCAL regSQ_DEBUG_STS_LOCAL; -typedef union SQ_DED_CNT__SI__CI regSQ_DED_CNT__SI__CI; -typedef union SQ_DED_INFO__SI__CI regSQ_DED_INFO__SI__CI; -typedef union SQ_DS_0__SI__CI regSQ_DS_0__SI__CI; -typedef union SQ_DS_0__VI regSQ_DS_0__VI; -typedef union SQ_DS_1 regSQ_DS_1; -typedef union SQ_EXP_0 regSQ_EXP_0; -typedef union SQ_EXP_1 regSQ_EXP_1; -typedef union SQ_FIFO_SIZES regSQ_FIFO_SIZES; -typedef union SQ_FLAT_0__CI__VI regSQ_FLAT_0__CI__VI; -typedef union SQ_FLAT_1__CI__VI regSQ_FLAT_1__CI__VI; -typedef union SQ_FLAT_SCRATCH_WORD0__CI__VI regSQ_FLAT_SCRATCH_WORD0__CI__VI; -typedef union SQ_FLAT_SCRATCH_WORD1__CI__VI regSQ_FLAT_SCRATCH_WORD1__CI__VI; -typedef union SQ_HV_VMID_CTRL__CI__VI regSQ_HV_VMID_CTRL__CI__VI; -typedef union SQ_IMG_RSRC_WORD0 regSQ_IMG_RSRC_WORD0; -typedef union SQ_IMG_RSRC_WORD1 regSQ_IMG_RSRC_WORD1; -typedef union SQ_IMG_RSRC_WORD2 regSQ_IMG_RSRC_WORD2; -typedef union SQ_IMG_RSRC_WORD3 regSQ_IMG_RSRC_WORD3; -typedef union SQ_IMG_RSRC_WORD4 regSQ_IMG_RSRC_WORD4; -typedef union SQ_IMG_RSRC_WORD5 regSQ_IMG_RSRC_WORD5; -typedef union SQ_IMG_RSRC_WORD6 regSQ_IMG_RSRC_WORD6; -typedef union SQ_IMG_RSRC_WORD7 regSQ_IMG_RSRC_WORD7; -typedef union SQ_IMG_SAMP_WORD0 regSQ_IMG_SAMP_WORD0; -typedef union SQ_IMG_SAMP_WORD1 regSQ_IMG_SAMP_WORD1; -typedef union SQ_IMG_SAMP_WORD2 regSQ_IMG_SAMP_WORD2; -typedef union SQ_IMG_SAMP_WORD3 regSQ_IMG_SAMP_WORD3; -typedef union SQ_IND_CMD__SI__CI regSQ_IND_CMD__SI__CI; -typedef union SQ_IND_DATA regSQ_IND_DATA; -typedef union SQ_IND_INDEX regSQ_IND_INDEX; -typedef union SQ_INST regSQ_INST; -typedef union SQ_INTERRUPT_AUTO_MASK__CI__VI regSQ_INTERRUPT_AUTO_MASK__CI__VI; -typedef union SQ_INTERRUPT_MSG_CTRL__CI__VI regSQ_INTERRUPT_MSG_CTRL__CI__VI; -typedef union SQ_INTERRUPT_WORD_AUTO__CI__VI regSQ_INTERRUPT_WORD_AUTO__CI__VI; -typedef union SQ_INTERRUPT_WORD_AUTO__SI regSQ_INTERRUPT_WORD_AUTO__SI; -typedef union SQ_INTERRUPT_WORD_CMN__CI__VI regSQ_INTERRUPT_WORD_CMN__CI__VI; -typedef union SQ_INTERRUPT_WORD_CMN__SI regSQ_INTERRUPT_WORD_CMN__SI; -typedef union SQ_INTERRUPT_WORD_WAVE__CI__VI regSQ_INTERRUPT_WORD_WAVE__CI__VI; -typedef union SQ_INTERRUPT_WORD_WAVE__SI regSQ_INTERRUPT_WORD_WAVE__SI; -typedef union SQ_LB_CTR_CTRL regSQ_LB_CTR_CTRL; -typedef union SQ_LB_DATA_ALU_CYCLES regSQ_LB_DATA_ALU_CYCLES; -typedef union SQ_LB_DATA_ALU_STALLS regSQ_LB_DATA_ALU_STALLS; -typedef union SQ_LB_DATA_TEX_CYCLES regSQ_LB_DATA_TEX_CYCLES; -typedef union SQ_LB_DATA_TEX_STALLS regSQ_LB_DATA_TEX_STALLS; -typedef union SQ_LDS_CLK_CTRL__CI__VI regSQ_LDS_CLK_CTRL__CI__VI; -typedef union SQ_MIMG_0 regSQ_MIMG_0; -typedef union SQ_MIMG_1 regSQ_MIMG_1; -typedef union SQ_MTBUF_0__SI__CI regSQ_MTBUF_0__SI__CI; -typedef union SQ_MTBUF_0__VI regSQ_MTBUF_0__VI; -typedef union SQ_MTBUF_1 regSQ_MTBUF_1; -typedef union SQ_MUBUF_0 regSQ_MUBUF_0; -typedef union SQ_MUBUF_1__SI__CI regSQ_MUBUF_1__SI__CI; -typedef union SQ_MUBUF_1__VI regSQ_MUBUF_1__VI; -typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; -typedef union SQ_PERFCOUNTER0_LO regSQ_PERFCOUNTER0_LO; -typedef union SQ_PERFCOUNTER0_SELECT__CI__VI regSQ_PERFCOUNTER0_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER0_SELECT__SI regSQ_PERFCOUNTER0_SELECT__SI; -typedef union SQ_PERFCOUNTER10_HI regSQ_PERFCOUNTER10_HI; -typedef union SQ_PERFCOUNTER10_LO regSQ_PERFCOUNTER10_LO; -typedef union SQ_PERFCOUNTER10_SELECT__CI__VI regSQ_PERFCOUNTER10_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER10_SELECT__SI regSQ_PERFCOUNTER10_SELECT__SI; -typedef union SQ_PERFCOUNTER11_HI regSQ_PERFCOUNTER11_HI; -typedef union SQ_PERFCOUNTER11_LO regSQ_PERFCOUNTER11_LO; -typedef union SQ_PERFCOUNTER11_SELECT__CI__VI regSQ_PERFCOUNTER11_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER11_SELECT__SI regSQ_PERFCOUNTER11_SELECT__SI; -typedef union SQ_PERFCOUNTER12_HI regSQ_PERFCOUNTER12_HI; -typedef union SQ_PERFCOUNTER12_LO regSQ_PERFCOUNTER12_LO; -typedef union SQ_PERFCOUNTER12_SELECT__CI__VI regSQ_PERFCOUNTER12_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER12_SELECT__SI regSQ_PERFCOUNTER12_SELECT__SI; -typedef union SQ_PERFCOUNTER13_HI regSQ_PERFCOUNTER13_HI; -typedef union SQ_PERFCOUNTER13_LO regSQ_PERFCOUNTER13_LO; -typedef union SQ_PERFCOUNTER13_SELECT__CI__VI regSQ_PERFCOUNTER13_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER13_SELECT__SI regSQ_PERFCOUNTER13_SELECT__SI; -typedef union SQ_PERFCOUNTER14_HI regSQ_PERFCOUNTER14_HI; -typedef union SQ_PERFCOUNTER14_LO regSQ_PERFCOUNTER14_LO; -typedef union SQ_PERFCOUNTER14_SELECT__CI__VI regSQ_PERFCOUNTER14_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER14_SELECT__SI regSQ_PERFCOUNTER14_SELECT__SI; -typedef union SQ_PERFCOUNTER15_HI regSQ_PERFCOUNTER15_HI; -typedef union SQ_PERFCOUNTER15_LO regSQ_PERFCOUNTER15_LO; -typedef union SQ_PERFCOUNTER15_SELECT__CI__VI regSQ_PERFCOUNTER15_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER15_SELECT__SI regSQ_PERFCOUNTER15_SELECT__SI; -typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; -typedef union SQ_PERFCOUNTER1_LO regSQ_PERFCOUNTER1_LO; -typedef union SQ_PERFCOUNTER1_SELECT__CI__VI regSQ_PERFCOUNTER1_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER1_SELECT__SI regSQ_PERFCOUNTER1_SELECT__SI; -typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; -typedef union SQ_PERFCOUNTER2_LO regSQ_PERFCOUNTER2_LO; -typedef union SQ_PERFCOUNTER2_SELECT__CI__VI regSQ_PERFCOUNTER2_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER2_SELECT__SI regSQ_PERFCOUNTER2_SELECT__SI; -typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; -typedef union SQ_PERFCOUNTER3_LO regSQ_PERFCOUNTER3_LO; -typedef union SQ_PERFCOUNTER3_SELECT__CI__VI regSQ_PERFCOUNTER3_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER3_SELECT__SI regSQ_PERFCOUNTER3_SELECT__SI; -typedef union SQ_PERFCOUNTER4_HI regSQ_PERFCOUNTER4_HI; -typedef union SQ_PERFCOUNTER4_LO regSQ_PERFCOUNTER4_LO; -typedef union SQ_PERFCOUNTER4_SELECT__CI__VI regSQ_PERFCOUNTER4_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER4_SELECT__SI regSQ_PERFCOUNTER4_SELECT__SI; -typedef union SQ_PERFCOUNTER5_HI regSQ_PERFCOUNTER5_HI; -typedef union SQ_PERFCOUNTER5_LO regSQ_PERFCOUNTER5_LO; -typedef union SQ_PERFCOUNTER5_SELECT__CI__VI regSQ_PERFCOUNTER5_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER5_SELECT__SI regSQ_PERFCOUNTER5_SELECT__SI; -typedef union SQ_PERFCOUNTER6_HI regSQ_PERFCOUNTER6_HI; -typedef union SQ_PERFCOUNTER6_LO regSQ_PERFCOUNTER6_LO; -typedef union SQ_PERFCOUNTER6_SELECT__CI__VI regSQ_PERFCOUNTER6_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER6_SELECT__SI regSQ_PERFCOUNTER6_SELECT__SI; -typedef union SQ_PERFCOUNTER7_HI regSQ_PERFCOUNTER7_HI; -typedef union SQ_PERFCOUNTER7_LO regSQ_PERFCOUNTER7_LO; -typedef union SQ_PERFCOUNTER7_SELECT__CI__VI regSQ_PERFCOUNTER7_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER7_SELECT__SI regSQ_PERFCOUNTER7_SELECT__SI; -typedef union SQ_PERFCOUNTER8_HI regSQ_PERFCOUNTER8_HI; -typedef union SQ_PERFCOUNTER8_LO regSQ_PERFCOUNTER8_LO; -typedef union SQ_PERFCOUNTER8_SELECT__CI__VI regSQ_PERFCOUNTER8_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER8_SELECT__SI regSQ_PERFCOUNTER8_SELECT__SI; -typedef union SQ_PERFCOUNTER9_HI regSQ_PERFCOUNTER9_HI; -typedef union SQ_PERFCOUNTER9_LO regSQ_PERFCOUNTER9_LO; -typedef union SQ_PERFCOUNTER9_SELECT__CI__VI regSQ_PERFCOUNTER9_SELECT__CI__VI; -typedef union SQ_PERFCOUNTER9_SELECT__SI regSQ_PERFCOUNTER9_SELECT__SI; -typedef union SQ_PERFCOUNTER_CTRL regSQ_PERFCOUNTER_CTRL; -typedef union SQ_PERFCOUNTER_CTRL2__CI__VI regSQ_PERFCOUNTER_CTRL2__CI__VI; -typedef union SQ_PERFCOUNTER_MASK__CI__VI regSQ_PERFCOUNTER_MASK__CI__VI; -typedef union SQ_POWER_THROTTLE regSQ_POWER_THROTTLE; -typedef union SQ_POWER_THROTTLE2 regSQ_POWER_THROTTLE2; -typedef union SQ_RANDOM_WAVE_PRI regSQ_RANDOM_WAVE_PRI; -typedef union SQ_REG_CREDITS regSQ_REG_CREDITS; -typedef union SQ_REG_TIMESTAMP__CI__VI regSQ_REG_TIMESTAMP__CI__VI; -typedef union SQ_SEC_CNT__SI__CI regSQ_SEC_CNT__SI__CI; -typedef union SQ_SMRD__SI__CI regSQ_SMRD__SI__CI; -typedef union SQ_SOP1 regSQ_SOP1; -typedef union SQ_SOP2 regSQ_SOP2; -typedef union SQ_SOPC regSQ_SOPC; -typedef union SQ_SOPK regSQ_SOPK; -typedef union SQ_SOPP regSQ_SOPP; -typedef union SQ_TEX_CLK_CTRL regSQ_TEX_CLK_CTRL; -typedef union SQ_THREAD_TRACE_BASE regSQ_THREAD_TRACE_BASE; -typedef union SQ_THREAD_TRACE_BASE2__CI__VI regSQ_THREAD_TRACE_BASE2__CI__VI; -typedef union SQ_THREAD_TRACE_CNTR regSQ_THREAD_TRACE_CNTR; -typedef union SQ_THREAD_TRACE_CTRL regSQ_THREAD_TRACE_CTRL; -typedef union SQ_THREAD_TRACE_HIWATER regSQ_THREAD_TRACE_HIWATER; -typedef union SQ_THREAD_TRACE_MASK regSQ_THREAD_TRACE_MASK; -typedef union SQ_THREAD_TRACE_MODE regSQ_THREAD_TRACE_MODE; -typedef union SQ_THREAD_TRACE_PERF_MASK regSQ_THREAD_TRACE_PERF_MASK; -typedef union SQ_THREAD_TRACE_SIZE regSQ_THREAD_TRACE_SIZE; -typedef union SQ_THREAD_TRACE_STATUS regSQ_THREAD_TRACE_STATUS; -typedef union SQ_THREAD_TRACE_TOKEN_MASK regSQ_THREAD_TRACE_TOKEN_MASK; -typedef union SQ_THREAD_TRACE_TOKEN_MASK2__CI regSQ_THREAD_TRACE_TOKEN_MASK2__CI; -typedef union SQ_THREAD_TRACE_TOKEN_MASK2__VI regSQ_THREAD_TRACE_TOKEN_MASK2__VI; -typedef union SQ_THREAD_TRACE_USERDATA_0 regSQ_THREAD_TRACE_USERDATA_0; -typedef union SQ_THREAD_TRACE_USERDATA_1 regSQ_THREAD_TRACE_USERDATA_1; -typedef union SQ_THREAD_TRACE_USERDATA_2 regSQ_THREAD_TRACE_USERDATA_2; -typedef union SQ_THREAD_TRACE_USERDATA_3 regSQ_THREAD_TRACE_USERDATA_3; -typedef union SQ_THREAD_TRACE_WORD_CMN regSQ_THREAD_TRACE_WORD_CMN; -typedef union SQ_THREAD_TRACE_WORD_EVENT regSQ_THREAD_TRACE_WORD_EVENT; -typedef union SQ_THREAD_TRACE_WORD_INST__SI__CI regSQ_THREAD_TRACE_WORD_INST__SI__CI; -typedef union SQ_THREAD_TRACE_WORD_INST__VI regSQ_THREAD_TRACE_WORD_INST__VI; -typedef union SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 - regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 - regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_ISSUE regSQ_THREAD_TRACE_WORD_ISSUE; -typedef union SQ_THREAD_TRACE_WORD_MISC__CI__VI regSQ_THREAD_TRACE_WORD_MISC__CI__VI; -typedef union SQ_THREAD_TRACE_WORD_MISC__SI regSQ_THREAD_TRACE_WORD_MISC__SI; -typedef union SQ_THREAD_TRACE_WORD_PERF_1_OF_2 regSQ_THREAD_TRACE_WORD_PERF_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_PERF_2_OF_2 regSQ_THREAD_TRACE_WORD_PERF_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_REG_1_OF_2__CI__VI regSQ_THREAD_TRACE_WORD_REG_1_OF_2__CI__VI; -typedef union SQ_THREAD_TRACE_WORD_REG_1_OF_2__SI regSQ_THREAD_TRACE_WORD_REG_1_OF_2__SI; -typedef union SQ_THREAD_TRACE_WORD_REG_2_OF_2 regSQ_THREAD_TRACE_WORD_REG_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI - regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI; -typedef union SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI - regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI; -typedef union SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_TIME__SI regSQ_THREAD_TRACE_WORD_TIME__SI; -typedef union SQ_THREAD_TRACE_WORD_WAVE regSQ_THREAD_TRACE_WORD_WAVE; -typedef union SQ_THREAD_TRACE_WORD_WAVE_START regSQ_THREAD_TRACE_WORD_WAVE_START; -typedef union SQ_THREAD_TRACE_WPTR regSQ_THREAD_TRACE_WPTR; -typedef union SQ_TIME_HI regSQ_TIME_HI; -typedef union SQ_TIME_LO regSQ_TIME_LO; -typedef union SQ_VINTRP regSQ_VINTRP; -typedef union SQ_VOP1 regSQ_VOP1; -typedef union SQ_VOP2 regSQ_VOP2; -typedef union SQ_VOP3_0__SI__CI regSQ_VOP3_0__SI__CI; -typedef union SQ_VOP3_0__VI regSQ_VOP3_0__VI; -typedef union SQ_VOP3_0_SDST_ENC__SI__CI regSQ_VOP3_0_SDST_ENC__SI__CI; -typedef union SQ_VOP3_0_SDST_ENC__VI regSQ_VOP3_0_SDST_ENC__VI; -typedef union SQ_VOP3_1 regSQ_VOP3_1; -typedef union SQ_VOPC regSQ_VOPC; -typedef union SQ_WAVE_EXEC_HI regSQ_WAVE_EXEC_HI; -typedef union SQ_WAVE_EXEC_LO regSQ_WAVE_EXEC_LO; -typedef union SQ_WAVE_GPR_ALLOC regSQ_WAVE_GPR_ALLOC; -typedef union SQ_WAVE_HW_ID__CI__VI regSQ_WAVE_HW_ID__CI__VI; -typedef union SQ_WAVE_HW_ID__SI regSQ_WAVE_HW_ID__SI; -typedef union SQ_WAVE_IB_DBG0__SI__CI regSQ_WAVE_IB_DBG0__SI__CI; -typedef union SQ_WAVE_IB_DBG0__VI regSQ_WAVE_IB_DBG0__VI; -typedef union SQ_WAVE_IB_STS__CI__VI regSQ_WAVE_IB_STS__CI__VI; -typedef union SQ_WAVE_IB_STS__SI regSQ_WAVE_IB_STS__SI; -typedef union SQ_WAVE_INST_DW0 regSQ_WAVE_INST_DW0; -typedef union SQ_WAVE_INST_DW1 regSQ_WAVE_INST_DW1; -typedef union SQ_WAVE_LDS_ALLOC regSQ_WAVE_LDS_ALLOC; -typedef union SQ_WAVE_M0 regSQ_WAVE_M0; -typedef union SQ_WAVE_MODE regSQ_WAVE_MODE; -typedef union SQ_WAVE_PC_HI regSQ_WAVE_PC_HI; -typedef union SQ_WAVE_PC_LO regSQ_WAVE_PC_LO; -typedef union SQ_WAVE_STATUS__SI__CI regSQ_WAVE_STATUS__SI__CI; -typedef union SQ_WAVE_STATUS__VI regSQ_WAVE_STATUS__VI; -typedef union SQ_WAVE_TBA_HI regSQ_WAVE_TBA_HI; -typedef union SQ_WAVE_TBA_LO regSQ_WAVE_TBA_LO; -typedef union SQ_WAVE_TMA_HI regSQ_WAVE_TMA_HI; -typedef union SQ_WAVE_TMA_LO regSQ_WAVE_TMA_LO; -typedef union SQ_WAVE_TRAPSTS regSQ_WAVE_TRAPSTS; -typedef union SQ_WAVE_TTMP0 regSQ_WAVE_TTMP0; -typedef union SQ_WAVE_TTMP1 regSQ_WAVE_TTMP1; -typedef union SQ_WAVE_TTMP10 regSQ_WAVE_TTMP10; -typedef union SQ_WAVE_TTMP11 regSQ_WAVE_TTMP11; -typedef union SQ_WAVE_TTMP2 regSQ_WAVE_TTMP2; -typedef union SQ_WAVE_TTMP3 regSQ_WAVE_TTMP3; -typedef union SQ_WAVE_TTMP4 regSQ_WAVE_TTMP4; -typedef union SQ_WAVE_TTMP5 regSQ_WAVE_TTMP5; -typedef union SQ_WAVE_TTMP6 regSQ_WAVE_TTMP6; -typedef union SQ_WAVE_TTMP7 regSQ_WAVE_TTMP7; -typedef union SQ_WAVE_TTMP8 regSQ_WAVE_TTMP8; -typedef union SQ_WAVE_TTMP9 regSQ_WAVE_TTMP9; -typedef union SRBM_CAM_DATA regSRBM_CAM_DATA; -typedef union SRBM_CAM_INDEX regSRBM_CAM_INDEX; -typedef union SRBM_CHIP_REVISION regSRBM_CHIP_REVISION; -typedef union SRBM_CNTL regSRBM_CNTL; -typedef union SRBM_DEBUG_CNTL regSRBM_DEBUG_CNTL; -typedef union SRBM_DEBUG_DATA regSRBM_DEBUG_DATA; -typedef union SRBM_DEBUG_SNAPSHOT__SI__CI regSRBM_DEBUG_SNAPSHOT__SI__CI; -typedef union SRBM_DEBUG_SNAPSHOT__VI regSRBM_DEBUG_SNAPSHOT__VI; -typedef union SRBM_DEBUG__CI__VI regSRBM_DEBUG__CI__VI; -typedef union SRBM_DEBUG__SI regSRBM_DEBUG__SI; -typedef union SRBM_DRMDMA_CLKEN_CNTL__SI regSRBM_DRMDMA_CLKEN_CNTL__SI; -typedef union SRBM_GFX_CNTL__CI__VI regSRBM_GFX_CNTL__CI__VI; -typedef union SRBM_GFX_CNTL__SI regSRBM_GFX_CNTL__SI; -typedef union SRBM_INT_ACK regSRBM_INT_ACK; -typedef union SRBM_INT_CNTL regSRBM_INT_CNTL; -typedef union SRBM_INT_STATUS regSRBM_INT_STATUS; -typedef union SRBM_MC_CLKEN_CNTL__CI__VI regSRBM_MC_CLKEN_CNTL__CI__VI; -typedef union SRBM_PERFCOUNTER0_HI regSRBM_PERFCOUNTER0_HI; -typedef union SRBM_PERFCOUNTER0_LO regSRBM_PERFCOUNTER0_LO; -typedef union SRBM_PERFCOUNTER0_SELECT regSRBM_PERFCOUNTER0_SELECT; -typedef union SRBM_PERFCOUNTER1_HI regSRBM_PERFCOUNTER1_HI; -typedef union SRBM_PERFCOUNTER1_LO regSRBM_PERFCOUNTER1_LO; -typedef union SRBM_PERFCOUNTER1_SELECT regSRBM_PERFCOUNTER1_SELECT; -typedef union SRBM_PERFMON_CNTL regSRBM_PERFMON_CNTL; -typedef union SRBM_READ_ERROR__CI regSRBM_READ_ERROR__CI; -typedef union SRBM_READ_ERROR__VI regSRBM_READ_ERROR__VI; -typedef union SRBM_READ_ERROR__SI regSRBM_READ_ERROR__SI; -typedef union SRBM_SAM_CLKEN_CNTL__CI__VI regSRBM_SAM_CLKEN_CNTL__CI__VI; -typedef union SRBM_SDMA_CLKEN_CNTL__CI__VI regSRBM_SDMA_CLKEN_CNTL__CI__VI; -typedef union SRBM_SOFT_RESET__CI regSRBM_SOFT_RESET__CI; -typedef union SRBM_SOFT_RESET__VI regSRBM_SOFT_RESET__VI; -typedef union SRBM_SOFT_RESET__SI regSRBM_SOFT_RESET__SI; -typedef union SRBM_STATUS__SI__CI regSRBM_STATUS__SI__CI; -typedef union SRBM_STATUS__VI regSRBM_STATUS__VI; -typedef union SRBM_STATUS2__CI regSRBM_STATUS2__CI; -typedef union SRBM_STATUS2__VI regSRBM_STATUS2__VI; -typedef union SRBM_STATUS2__SI regSRBM_STATUS2__SI; -typedef union SRBM_SYS_CLKEN_CNTL regSRBM_SYS_CLKEN_CNTL; -typedef union SRBM_UVD_CLKEN_CNTL regSRBM_UVD_CLKEN_CNTL; -typedef union SRBM_VCE_CLKEN_CNTL regSRBM_VCE_CLKEN_CNTL; -typedef union STATE_CHANGE_STATUS__SI regSTATE_CHANGE_STATUS__SI; -typedef union STATUS regSTATUS; -typedef union STREAM_SYNCHRONIZATION__SI regSTREAM_SYNCHRONIZATION__SI; -typedef union STUTTER_A_CNT__SI regSTUTTER_A_CNT__SI; -typedef union STUTTER_B_CNT__SI regSTUTTER_B_CNT__SI; -typedef union SUB_CLASS regSUB_CLASS; -typedef union SVI2_NB_STATUS__CI__VI regSVI2_NB_STATUS__CI__VI; -typedef union SXIFCCG_DEBUG_REG0 regSXIFCCG_DEBUG_REG0; -typedef union SXIFCCG_DEBUG_REG1 regSXIFCCG_DEBUG_REG1; -typedef union SXIFCCG_DEBUG_REG2 regSXIFCCG_DEBUG_REG2; -typedef union SXIFCCG_DEBUG_REG3 regSXIFCCG_DEBUG_REG3; -typedef union SX_DEBUG_1__SI__CI regSX_DEBUG_1__SI__CI; -typedef union SX_DEBUG_1__VI regSX_DEBUG_1__VI; -typedef union SX_DEBUG_BUSY regSX_DEBUG_BUSY; -typedef union SX_DEBUG_BUSY_2__CI__VI regSX_DEBUG_BUSY_2__CI__VI; -typedef union SX_DEBUG_BUSY_2__SI regSX_DEBUG_BUSY_2__SI; -typedef union SX_DEBUG_BUSY_3 regSX_DEBUG_BUSY_3; -typedef union SX_DEBUG_BUSY_4 regSX_DEBUG_BUSY_4; -typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; -typedef union SX_PERFCOUNTER0_LO regSX_PERFCOUNTER0_LO; -typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; -typedef union SX_PERFCOUNTER0_SELECT1__CI__VI regSX_PERFCOUNTER0_SELECT1__CI__VI; -typedef union SX_PERFCOUNTER1_HI regSX_PERFCOUNTER1_HI; -typedef union SX_PERFCOUNTER1_LO regSX_PERFCOUNTER1_LO; -typedef union SX_PERFCOUNTER1_SELECT regSX_PERFCOUNTER1_SELECT; -typedef union SX_PERFCOUNTER1_SELECT1__CI__VI regSX_PERFCOUNTER1_SELECT1__CI__VI; -typedef union SX_PERFCOUNTER2_HI regSX_PERFCOUNTER2_HI; -typedef union SX_PERFCOUNTER2_LO regSX_PERFCOUNTER2_LO; -typedef union SX_PERFCOUNTER2_SELECT regSX_PERFCOUNTER2_SELECT; -typedef union SX_PERFCOUNTER3_HI regSX_PERFCOUNTER3_HI; -typedef union SX_PERFCOUNTER3_LO regSX_PERFCOUNTER3_LO; -typedef union SX_PERFCOUNTER3_SELECT regSX_PERFCOUNTER3_SELECT; -typedef union TARGET_AND_CURRENT_PROFILE_INDEX_1 regTARGET_AND_CURRENT_PROFILE_INDEX_1; -typedef union TARGET_AND_CURRENT_PROFILE_INDEX__CI__VI regTARGET_AND_CURRENT_PROFILE_INDEX__CI__VI; -typedef union TARGET_AND_CURRENT_PROFILE_INDEX__SI regTARGET_AND_CURRENT_PROFILE_INDEX__SI; -typedef union TA_BC_BASE_ADDR regTA_BC_BASE_ADDR; -typedef union TA_BC_BASE_ADDR_HI__CI__VI regTA_BC_BASE_ADDR_HI__CI__VI; -typedef union TA_CGTT_CTRL regTA_CGTT_CTRL; -typedef union TA_CNTL regTA_CNTL; -typedef union TA_CNTL_AUX regTA_CNTL_AUX; -typedef union TA_CS_BC_BASE_ADDR regTA_CS_BC_BASE_ADDR; -typedef union TA_CS_BC_BASE_ADDR_HI__CI__VI regTA_CS_BC_BASE_ADDR_HI__CI__VI; -typedef union TA_DEBUG_DATA regTA_DEBUG_DATA; -typedef union TA_DEBUG_INDEX regTA_DEBUG_INDEX; -typedef union TA_PERFCOUNTER0_HI regTA_PERFCOUNTER0_HI; -typedef union TA_PERFCOUNTER0_LO regTA_PERFCOUNTER0_LO; -typedef union TA_PERFCOUNTER0_SELECT regTA_PERFCOUNTER0_SELECT; -typedef union TA_PERFCOUNTER0_SELECT1__CI__VI regTA_PERFCOUNTER0_SELECT1__CI__VI; -typedef union TA_PERFCOUNTER1_HI regTA_PERFCOUNTER1_HI; -typedef union TA_PERFCOUNTER1_LO regTA_PERFCOUNTER1_LO; -typedef union TA_PERFCOUNTER1_SELECT regTA_PERFCOUNTER1_SELECT; -typedef union TA_RESERVED_010C__CI__VI regTA_RESERVED_010C__CI__VI; -typedef union TA_SCRATCH regTA_SCRATCH; -typedef union TA_STATUS regTA_STATUS; -typedef union TCA_CGTT_SCLK_CTRL regTCA_CGTT_SCLK_CTRL; -typedef union TCA_CTRL regTCA_CTRL; -typedef union TCA_PERFCOUNTER0_HI regTCA_PERFCOUNTER0_HI; -typedef union TCA_PERFCOUNTER0_LO regTCA_PERFCOUNTER0_LO; -typedef union TCA_PERFCOUNTER0_SELECT1__CI__VI regTCA_PERFCOUNTER0_SELECT1__CI__VI; -typedef union TCA_PERFCOUNTER0_SELECT__CI__VI regTCA_PERFCOUNTER0_SELECT__CI__VI; -typedef union TCA_PERFCOUNTER0_SELECT__SI regTCA_PERFCOUNTER0_SELECT__SI; -typedef union TCA_PERFCOUNTER1_HI regTCA_PERFCOUNTER1_HI; -typedef union TCA_PERFCOUNTER1_LO regTCA_PERFCOUNTER1_LO; -typedef union TCA_PERFCOUNTER1_SELECT1__CI__VI regTCA_PERFCOUNTER1_SELECT1__CI__VI; -typedef union TCA_PERFCOUNTER1_SELECT__CI__VI regTCA_PERFCOUNTER1_SELECT__CI__VI; -typedef union TCA_PERFCOUNTER1_SELECT__SI regTCA_PERFCOUNTER1_SELECT__SI; -typedef union TCA_PERFCOUNTER2_HI regTCA_PERFCOUNTER2_HI; -typedef union TCA_PERFCOUNTER2_LO regTCA_PERFCOUNTER2_LO; -typedef union TCA_PERFCOUNTER2_SELECT__CI__VI regTCA_PERFCOUNTER2_SELECT__CI__VI; -typedef union TCA_PERFCOUNTER2_SELECT__SI regTCA_PERFCOUNTER2_SELECT__SI; -typedef union TCA_PERFCOUNTER3_HI regTCA_PERFCOUNTER3_HI; -typedef union TCA_PERFCOUNTER3_LO regTCA_PERFCOUNTER3_LO; -typedef union TCA_PERFCOUNTER3_SELECT__CI__VI regTCA_PERFCOUNTER3_SELECT__CI__VI; -typedef union TCA_PERFCOUNTER3_SELECT__SI regTCA_PERFCOUNTER3_SELECT__SI; -typedef union TCC_CGTT_SCLK_CTRL regTCC_CGTT_SCLK_CTRL; -typedef union TCC_CTRL regTCC_CTRL; -typedef union TCC_EDC_COUNTER__SI__CI regTCC_EDC_COUNTER__SI__CI; -typedef union TCC_PERFCOUNTER0_HI regTCC_PERFCOUNTER0_HI; -typedef union TCC_PERFCOUNTER0_LO regTCC_PERFCOUNTER0_LO; -typedef union TCC_PERFCOUNTER0_SELECT1__CI__VI regTCC_PERFCOUNTER0_SELECT1__CI__VI; -typedef union TCC_PERFCOUNTER0_SELECT__CI__VI regTCC_PERFCOUNTER0_SELECT__CI__VI; -typedef union TCC_PERFCOUNTER0_SELECT__SI regTCC_PERFCOUNTER0_SELECT__SI; -typedef union TCC_PERFCOUNTER1_HI regTCC_PERFCOUNTER1_HI; -typedef union TCC_PERFCOUNTER1_LO regTCC_PERFCOUNTER1_LO; -typedef union TCC_PERFCOUNTER1_SELECT1__CI__VI regTCC_PERFCOUNTER1_SELECT1__CI__VI; -typedef union TCC_PERFCOUNTER1_SELECT__CI__VI regTCC_PERFCOUNTER1_SELECT__CI__VI; -typedef union TCC_PERFCOUNTER1_SELECT__SI regTCC_PERFCOUNTER1_SELECT__SI; -typedef union TCC_PERFCOUNTER2_HI regTCC_PERFCOUNTER2_HI; -typedef union TCC_PERFCOUNTER2_LO regTCC_PERFCOUNTER2_LO; -typedef union TCC_PERFCOUNTER2_SELECT__CI__VI regTCC_PERFCOUNTER2_SELECT__CI__VI; -typedef union TCC_PERFCOUNTER2_SELECT__SI regTCC_PERFCOUNTER2_SELECT__SI; -typedef union TCC_PERFCOUNTER3_HI regTCC_PERFCOUNTER3_HI; -typedef union TCC_PERFCOUNTER3_LO regTCC_PERFCOUNTER3_LO; -typedef union TCC_PERFCOUNTER3_SELECT__CI__VI regTCC_PERFCOUNTER3_SELECT__CI__VI; -typedef union TCC_PERFCOUNTER3_SELECT__SI regTCC_PERFCOUNTER3_SELECT__SI; -typedef union TCC_REDUNDANCY__CI__VI regTCC_REDUNDANCY__CI__VI; -typedef union TCI_CNTL_1 regTCI_CNTL_1; -typedef union TCI_CNTL_2 regTCI_CNTL_2; -typedef union TCI_STATUS regTCI_STATUS; -typedef union TCP_ADDR_CONFIG regTCP_ADDR_CONFIG; -typedef union TCP_BUFFER_ADDR_HASH_CNTL regTCP_BUFFER_ADDR_HASH_CNTL; -typedef union TCP_CHAN_STEER_HI regTCP_CHAN_STEER_HI; -typedef union TCP_CHAN_STEER_LO regTCP_CHAN_STEER_LO; -typedef union TCP_CNTL regTCP_CNTL; -typedef union TCP_CREDIT regTCP_CREDIT; -typedef union TCP_DEBUG_DATA regTCP_DEBUG_DATA; -typedef union TCP_DEBUG_INDEX regTCP_DEBUG_INDEX; -typedef union TCP_EDC_COUNTER__SI__CI regTCP_EDC_COUNTER__SI__CI; -typedef union TCP_INVALIDATE regTCP_INVALIDATE; -typedef union TCP_PERFCOUNTER0_HI regTCP_PERFCOUNTER0_HI; -typedef union TCP_PERFCOUNTER0_LO regTCP_PERFCOUNTER0_LO; -typedef union TCP_PERFCOUNTER0_SELECT1__CI__VI regTCP_PERFCOUNTER0_SELECT1__CI__VI; -typedef union TCP_PERFCOUNTER0_SELECT__CI__VI regTCP_PERFCOUNTER0_SELECT__CI__VI; -typedef union TCP_PERFCOUNTER0_SELECT__SI regTCP_PERFCOUNTER0_SELECT__SI; -typedef union TCP_PERFCOUNTER1_HI regTCP_PERFCOUNTER1_HI; -typedef union TCP_PERFCOUNTER1_LO regTCP_PERFCOUNTER1_LO; -typedef union TCP_PERFCOUNTER1_SELECT1__CI__VI regTCP_PERFCOUNTER1_SELECT1__CI__VI; -typedef union TCP_PERFCOUNTER1_SELECT__CI__VI regTCP_PERFCOUNTER1_SELECT__CI__VI; -typedef union TCP_PERFCOUNTER1_SELECT__SI regTCP_PERFCOUNTER1_SELECT__SI; -typedef union TCP_PERFCOUNTER2_HI regTCP_PERFCOUNTER2_HI; -typedef union TCP_PERFCOUNTER2_LO regTCP_PERFCOUNTER2_LO; -typedef union TCP_PERFCOUNTER2_SELECT__CI__VI regTCP_PERFCOUNTER2_SELECT__CI__VI; -typedef union TCP_PERFCOUNTER2_SELECT__SI regTCP_PERFCOUNTER2_SELECT__SI; -typedef union TCP_PERFCOUNTER3_HI regTCP_PERFCOUNTER3_HI; -typedef union TCP_PERFCOUNTER3_LO regTCP_PERFCOUNTER3_LO; -typedef union TCP_PERFCOUNTER3_SELECT__CI__VI regTCP_PERFCOUNTER3_SELECT__CI__VI; -typedef union TCP_PERFCOUNTER3_SELECT__SI regTCP_PERFCOUNTER3_SELECT__SI; -typedef union TCP_STATUS regTCP_STATUS; -typedef union TCP_WATCH0_ADDR_H__CI__VI regTCP_WATCH0_ADDR_H__CI__VI; -typedef union TCP_WATCH0_ADDR_L__CI__VI regTCP_WATCH0_ADDR_L__CI__VI; -typedef union TCP_WATCH0_CNTL__CI__VI regTCP_WATCH0_CNTL__CI__VI; -typedef union TCP_WATCH1_ADDR_H__CI__VI regTCP_WATCH1_ADDR_H__CI__VI; -typedef union TCP_WATCH1_ADDR_L__CI__VI regTCP_WATCH1_ADDR_L__CI__VI; -typedef union TCP_WATCH1_CNTL__CI__VI regTCP_WATCH1_CNTL__CI__VI; -typedef union TCP_WATCH2_ADDR_H__CI__VI regTCP_WATCH2_ADDR_H__CI__VI; -typedef union TCP_WATCH2_ADDR_L__CI__VI regTCP_WATCH2_ADDR_L__CI__VI; -typedef union TCP_WATCH2_CNTL__CI__VI regTCP_WATCH2_CNTL__CI__VI; -typedef union TCP_WATCH3_ADDR_H__CI__VI regTCP_WATCH3_ADDR_H__CI__VI; -typedef union TCP_WATCH3_ADDR_L__CI__VI regTCP_WATCH3_ADDR_L__CI__VI; -typedef union TCP_WATCH3_CNTL__CI__VI regTCP_WATCH3_CNTL__CI__VI; -typedef union TCS_CGTT_SCLK_CTRL__CI regTCS_CGTT_SCLK_CTRL__CI; -typedef union TCS_CTRL__CI regTCS_CTRL__CI; -typedef union TCS_PERFCOUNTER0_HI__CI regTCS_PERFCOUNTER0_HI__CI; -typedef union TCS_PERFCOUNTER0_LO__CI regTCS_PERFCOUNTER0_LO__CI; -typedef union TCS_PERFCOUNTER0_SELECT1__CI regTCS_PERFCOUNTER0_SELECT1__CI; -typedef union TCS_PERFCOUNTER0_SELECT__CI regTCS_PERFCOUNTER0_SELECT__CI; -typedef union TCS_PERFCOUNTER1_HI__CI regTCS_PERFCOUNTER1_HI__CI; -typedef union TCS_PERFCOUNTER1_LO__CI regTCS_PERFCOUNTER1_LO__CI; -typedef union TCS_PERFCOUNTER1_SELECT__CI regTCS_PERFCOUNTER1_SELECT__CI; -typedef union TCS_PERFCOUNTER2_HI__CI regTCS_PERFCOUNTER2_HI__CI; -typedef union TCS_PERFCOUNTER2_LO__CI regTCS_PERFCOUNTER2_LO__CI; -typedef union TCS_PERFCOUNTER2_SELECT__CI regTCS_PERFCOUNTER2_SELECT__CI; -typedef union TCS_PERFCOUNTER3_HI__CI regTCS_PERFCOUNTER3_HI__CI; -typedef union TCS_PERFCOUNTER3_LO__CI regTCS_PERFCOUNTER3_LO__CI; -typedef union TCS_PERFCOUNTER3_SELECT__CI regTCS_PERFCOUNTER3_SELECT__CI; -typedef union TC_CFG_L1_LOAD_POLICY0__CI__VI regTC_CFG_L1_LOAD_POLICY0__CI__VI; -typedef union TC_CFG_L1_LOAD_POLICY1__CI__VI regTC_CFG_L1_LOAD_POLICY1__CI__VI; -typedef union TC_CFG_L1_STORE_POLICY__CI__VI regTC_CFG_L1_STORE_POLICY__CI__VI; -typedef union TC_CFG_L1_VOLATILE__CI__VI regTC_CFG_L1_VOLATILE__CI__VI; -typedef union TC_CFG_L2_ATOMIC_POLICY__CI__VI regTC_CFG_L2_ATOMIC_POLICY__CI__VI; -typedef union TC_CFG_L2_LOAD_POLICY0__CI__VI regTC_CFG_L2_LOAD_POLICY0__CI__VI; -typedef union TC_CFG_L2_LOAD_POLICY1__CI__VI regTC_CFG_L2_LOAD_POLICY1__CI__VI; -typedef union TC_CFG_L2_STORE_POLICY0__CI__VI regTC_CFG_L2_STORE_POLICY0__CI__VI; -typedef union TC_CFG_L2_STORE_POLICY1__CI__VI regTC_CFG_L2_STORE_POLICY1__CI__VI; -typedef union TC_CFG_L2_VOLATILE__CI__VI regTC_CFG_L2_VOLATILE__CI__VI; -typedef union TDP_ACC_CORE_0__CI__VI regTDP_ACC_CORE_0__CI__VI; -typedef union TDP_ACC_CORE_1__CI__VI regTDP_ACC_CORE_1__CI__VI; -typedef union TD_CGTT_CTRL regTD_CGTT_CTRL; -typedef union TD_CNTL regTD_CNTL; -typedef union TD_DEBUG_DATA__CI__VI regTD_DEBUG_DATA__CI__VI; -typedef union TD_DEBUG_DATA__SI regTD_DEBUG_DATA__SI; -typedef union TD_DEBUG_INDEX regTD_DEBUG_INDEX; -typedef union TD_PERFCOUNTER0_HI regTD_PERFCOUNTER0_HI; -typedef union TD_PERFCOUNTER0_LO regTD_PERFCOUNTER0_LO; -typedef union TD_PERFCOUNTER0_SELECT regTD_PERFCOUNTER0_SELECT; -typedef union TD_PERFCOUNTER0_SELECT1__CI__VI regTD_PERFCOUNTER0_SELECT1__CI__VI; -typedef union TD_PERFCOUNTER1_HI__CI__VI regTD_PERFCOUNTER1_HI__CI__VI; -typedef union TD_PERFCOUNTER1_LO__CI__VI regTD_PERFCOUNTER1_LO__CI__VI; -typedef union TD_PERFCOUNTER1_SELECT__CI__VI regTD_PERFCOUNTER1_SELECT__CI__VI; -typedef union TD_SCRATCH regTD_SCRATCH; -typedef union TD_STATUS regTD_STATUS; -typedef union THERMAL_PROTECT_COUNTER__SI regTHERMAL_PROTECT_COUNTER__SI; -typedef union THM_CLK_CNTL regTHM_CLK_CNTL; -typedef union THM_CMON_CTRL2__SI regTHM_CMON_CTRL2__SI; -typedef union THM_CMON_CTRL__SI regTHM_CMON_CTRL__SI; -typedef union THM_CTF_DELAY__CI regTHM_CTF_DELAY__CI; -typedef union THM_CTF_STATUS__CI regTHM_CTF_STATUS__CI; -typedef union THM_SMC_IND_DATA__CI regTHM_SMC_IND_DATA__CI; -typedef union THM_SMC_IND_INDEX__CI regTHM_SMC_IND_INDEX__CI; -typedef union THM_SW_TEMP__CI regTHM_SW_TEMP__CI; -typedef union THM_TMON0_CSR_RD__SI__CI regTHM_TMON0_CSR_RD__SI__CI; -typedef union THM_TMON0_CSR_WR__SI__CI regTHM_TMON0_CSR_WR__SI__CI; -typedef union THM_TMON0_CTRL__SI__CI regTHM_TMON0_CTRL__SI__CI; -typedef union THM_TMON0_CTRL2__SI__CI regTHM_TMON0_CTRL2__SI__CI; -typedef union THM_TMON0_DEBUG__SI__CI regTHM_TMON0_DEBUG__SI__CI; -typedef union THM_TMON0_INT_DATA__SI__CI regTHM_TMON0_INT_DATA__SI__CI; -typedef union THM_TMON0_RDIL0_DATA__SI__CI regTHM_TMON0_RDIL0_DATA__SI__CI; -typedef union THM_TMON0_RDIL10_DATA__SI__CI regTHM_TMON0_RDIL10_DATA__SI__CI; -typedef union THM_TMON0_RDIL11_DATA__SI__CI regTHM_TMON0_RDIL11_DATA__SI__CI; -typedef union THM_TMON0_RDIL12_DATA__SI__CI regTHM_TMON0_RDIL12_DATA__SI__CI; -typedef union THM_TMON0_RDIL13_DATA__SI__CI regTHM_TMON0_RDIL13_DATA__SI__CI; -typedef union THM_TMON0_RDIL14_DATA__SI__CI regTHM_TMON0_RDIL14_DATA__SI__CI; -typedef union THM_TMON0_RDIL15_DATA__SI__CI regTHM_TMON0_RDIL15_DATA__SI__CI; -typedef union THM_TMON0_RDIL1_DATA__SI__CI regTHM_TMON0_RDIL1_DATA__SI__CI; -typedef union THM_TMON0_RDIL2_DATA__SI__CI regTHM_TMON0_RDIL2_DATA__SI__CI; -typedef union THM_TMON0_RDIL3_DATA__SI__CI regTHM_TMON0_RDIL3_DATA__SI__CI; -typedef union THM_TMON0_RDIL4_DATA__SI__CI regTHM_TMON0_RDIL4_DATA__SI__CI; -typedef union THM_TMON0_RDIL5_DATA__SI__CI regTHM_TMON0_RDIL5_DATA__SI__CI; -typedef union THM_TMON0_RDIL6_DATA__SI__CI regTHM_TMON0_RDIL6_DATA__SI__CI; -typedef union THM_TMON0_RDIL7_DATA__SI__CI regTHM_TMON0_RDIL7_DATA__SI__CI; -typedef union THM_TMON0_RDIL8_DATA__SI__CI regTHM_TMON0_RDIL8_DATA__SI__CI; -typedef union THM_TMON0_RDIL9_DATA__SI__CI regTHM_TMON0_RDIL9_DATA__SI__CI; -typedef union THM_TMON0_RDIR0_DATA__SI__CI regTHM_TMON0_RDIR0_DATA__SI__CI; -typedef union THM_TMON0_RDIR10_DATA__SI__CI regTHM_TMON0_RDIR10_DATA__SI__CI; -typedef union THM_TMON0_RDIR11_DATA__SI__CI regTHM_TMON0_RDIR11_DATA__SI__CI; -typedef union THM_TMON0_RDIR12_DATA__SI__CI regTHM_TMON0_RDIR12_DATA__SI__CI; -typedef union THM_TMON0_RDIR13_DATA__SI__CI regTHM_TMON0_RDIR13_DATA__SI__CI; -typedef union THM_TMON0_RDIR14_DATA__SI__CI regTHM_TMON0_RDIR14_DATA__SI__CI; -typedef union THM_TMON0_RDIR15_DATA__SI__CI regTHM_TMON0_RDIR15_DATA__SI__CI; -typedef union THM_TMON0_RDIR1_DATA__SI__CI regTHM_TMON0_RDIR1_DATA__SI__CI; -typedef union THM_TMON0_RDIR2_DATA__SI__CI regTHM_TMON0_RDIR2_DATA__SI__CI; -typedef union THM_TMON0_RDIR3_DATA__SI__CI regTHM_TMON0_RDIR3_DATA__SI__CI; -typedef union THM_TMON0_RDIR4_DATA__SI__CI regTHM_TMON0_RDIR4_DATA__SI__CI; -typedef union THM_TMON0_RDIR5_DATA__SI__CI regTHM_TMON0_RDIR5_DATA__SI__CI; -typedef union THM_TMON0_RDIR6_DATA__SI__CI regTHM_TMON0_RDIR6_DATA__SI__CI; -typedef union THM_TMON0_RDIR7_DATA__SI__CI regTHM_TMON0_RDIR7_DATA__SI__CI; -typedef union THM_TMON0_RDIR8_DATA__SI__CI regTHM_TMON0_RDIR8_DATA__SI__CI; -typedef union THM_TMON0_RDIR9_DATA__SI__CI regTHM_TMON0_RDIR9_DATA__SI__CI; -typedef union THM_TMON1_CSR_RD__SI__CI regTHM_TMON1_CSR_RD__SI__CI; -typedef union THM_TMON1_CSR_WR__SI__CI regTHM_TMON1_CSR_WR__SI__CI; -typedef union THM_TMON1_CTRL__SI__CI regTHM_TMON1_CTRL__SI__CI; -typedef union THM_TMON1_CTRL2__SI__CI regTHM_TMON1_CTRL2__SI__CI; -typedef union THM_TMON1_DEBUG__SI__CI regTHM_TMON1_DEBUG__SI__CI; -typedef union THM_TMON1_INT_DATA__SI__CI regTHM_TMON1_INT_DATA__SI__CI; -typedef union THM_TMON1_RDIL0_DATA__SI__CI regTHM_TMON1_RDIL0_DATA__SI__CI; -typedef union THM_TMON1_RDIL10_DATA__SI__CI regTHM_TMON1_RDIL10_DATA__SI__CI; -typedef union THM_TMON1_RDIL11_DATA__SI__CI regTHM_TMON1_RDIL11_DATA__SI__CI; -typedef union THM_TMON1_RDIL12_DATA__SI__CI regTHM_TMON1_RDIL12_DATA__SI__CI; -typedef union THM_TMON1_RDIL13_DATA__SI__CI regTHM_TMON1_RDIL13_DATA__SI__CI; -typedef union THM_TMON1_RDIL14_DATA__SI__CI regTHM_TMON1_RDIL14_DATA__SI__CI; -typedef union THM_TMON1_RDIL15_DATA__SI__CI regTHM_TMON1_RDIL15_DATA__SI__CI; -typedef union THM_TMON1_RDIL1_DATA__SI__CI regTHM_TMON1_RDIL1_DATA__SI__CI; -typedef union THM_TMON1_RDIL2_DATA__SI__CI regTHM_TMON1_RDIL2_DATA__SI__CI; -typedef union THM_TMON1_RDIL3_DATA__SI__CI regTHM_TMON1_RDIL3_DATA__SI__CI; -typedef union THM_TMON1_RDIL4_DATA__SI__CI regTHM_TMON1_RDIL4_DATA__SI__CI; -typedef union THM_TMON1_RDIL5_DATA__SI__CI regTHM_TMON1_RDIL5_DATA__SI__CI; -typedef union THM_TMON1_RDIL6_DATA__SI__CI regTHM_TMON1_RDIL6_DATA__SI__CI; -typedef union THM_TMON1_RDIL7_DATA__SI__CI regTHM_TMON1_RDIL7_DATA__SI__CI; -typedef union THM_TMON1_RDIL8_DATA__SI__CI regTHM_TMON1_RDIL8_DATA__SI__CI; -typedef union THM_TMON1_RDIL9_DATA__SI__CI regTHM_TMON1_RDIL9_DATA__SI__CI; -typedef union THM_TMON1_RDIR0_DATA__SI__CI regTHM_TMON1_RDIR0_DATA__SI__CI; -typedef union THM_TMON1_RDIR10_DATA__SI__CI regTHM_TMON1_RDIR10_DATA__SI__CI; -typedef union THM_TMON1_RDIR11_DATA__SI__CI regTHM_TMON1_RDIR11_DATA__SI__CI; -typedef union THM_TMON1_RDIR12_DATA__SI__CI regTHM_TMON1_RDIR12_DATA__SI__CI; -typedef union THM_TMON1_RDIR13_DATA__SI__CI regTHM_TMON1_RDIR13_DATA__SI__CI; -typedef union THM_TMON1_RDIR14_DATA__SI__CI regTHM_TMON1_RDIR14_DATA__SI__CI; -typedef union THM_TMON1_RDIR15_DATA__SI__CI regTHM_TMON1_RDIR15_DATA__SI__CI; -typedef union THM_TMON1_RDIR1_DATA__SI__CI regTHM_TMON1_RDIR1_DATA__SI__CI; -typedef union THM_TMON1_RDIR2_DATA__SI__CI regTHM_TMON1_RDIR2_DATA__SI__CI; -typedef union THM_TMON1_RDIR3_DATA__SI__CI regTHM_TMON1_RDIR3_DATA__SI__CI; -typedef union THM_TMON1_RDIR4_DATA__SI__CI regTHM_TMON1_RDIR4_DATA__SI__CI; -typedef union THM_TMON1_RDIR5_DATA__SI__CI regTHM_TMON1_RDIR5_DATA__SI__CI; -typedef union THM_TMON1_RDIR6_DATA__SI__CI regTHM_TMON1_RDIR6_DATA__SI__CI; -typedef union THM_TMON1_RDIR7_DATA__SI__CI regTHM_TMON1_RDIR7_DATA__SI__CI; -typedef union THM_TMON1_RDIR8_DATA__SI__CI regTHM_TMON1_RDIR8_DATA__SI__CI; -typedef union THM_TMON1_RDIR9_DATA__SI__CI regTHM_TMON1_RDIR9_DATA__SI__CI; -typedef union THM_TMON_CONFIG2__SI__CI regTHM_TMON_CONFIG2__SI__CI; -typedef union THM_TMON_CONFIG__CI regTHM_TMON_CONFIG__CI; -typedef union THM_TMON_CONFIG__SI regTHM_TMON_CONFIG__SI; -typedef union TMDS_CNTL__SI regTMDS_CNTL__SI; -typedef union TMDS_CONTROL0_FEEDBACK__SI regTMDS_CONTROL0_FEEDBACK__SI; -typedef union TMDS_CONTROL_CHAR__SI regTMDS_CONTROL_CHAR__SI; -typedef union TMDS_CTL0_1_GEN_CNTL__SI regTMDS_CTL0_1_GEN_CNTL__SI; -typedef union TMDS_CTL2_3_GEN_CNTL__SI regTMDS_CTL2_3_GEN_CNTL__SI; -typedef union TMDS_CTL_BITS__SI regTMDS_CTL_BITS__SI; -typedef union TMDS_DCBALANCER_CONTROL__SI regTMDS_DCBALANCER_CONTROL__SI; -typedef union TMDS_DEBUG__SI regTMDS_DEBUG__SI; -typedef union TMDS_STEREOSYNC_CTL_SEL__SI regTMDS_STEREOSYNC_CTL_SEL__SI; -typedef union TMDS_SYNC_CHAR_PATTERN_0_1__SI regTMDS_SYNC_CHAR_PATTERN_0_1__SI; -typedef union TMDS_SYNC_CHAR_PATTERN_2_3__SI regTMDS_SYNC_CHAR_PATTERN_2_3__SI; -typedef union TMDS_SYNC_DCBALANCE_CHAR__SI regTMDS_SYNC_DCBALANCE_CHAR__SI; -typedef union TST_MISC_CTRL regTST_MISC_CTRL; -typedef union TST_TC_JTAG_0 regTST_TC_JTAG_0; -typedef union TST_TC_JTAG_1 regTST_TC_JTAG_1; -typedef union UART_CLK_GPIO_SEL regUART_CLK_GPIO_SEL; -typedef union UNDERFLOW_STATUS__SI regUNDERFLOW_STATUS__SI; -typedef union UNIPHY_DATA_SYNCHRONIZATION__SI regUNIPHY_DATA_SYNCHRONIZATION__SI; -typedef union UNIPHY_IMPCAL_LINKA__SI regUNIPHY_IMPCAL_LINKA__SI; -typedef union UNIPHY_IMPCAL_LINKB__SI regUNIPHY_IMPCAL_LINKB__SI; -typedef union UNIPHY_IMPCAL_LINKC__SI regUNIPHY_IMPCAL_LINKC__SI; -typedef union UNIPHY_IMPCAL_LINKD__SI regUNIPHY_IMPCAL_LINKD__SI; -typedef union UNIPHY_IMPCAL_LINKE__SI regUNIPHY_IMPCAL_LINKE__SI; -typedef union UNIPHY_IMPCAL_LINKF__SI regUNIPHY_IMPCAL_LINKF__SI; -typedef union UNIPHY_IMPCAL_PERIOD__SI regUNIPHY_IMPCAL_PERIOD__SI; -typedef union UNIPHY_MACRO_CONTROL1__SI regUNIPHY_MACRO_CONTROL1__SI; -typedef union UNIPHY_MACRO_CONTROL2__SI regUNIPHY_MACRO_CONTROL2__SI; -typedef union UNIPHY_MACRO_CONTROL3__SI regUNIPHY_MACRO_CONTROL3__SI; -typedef union UNIPHY_MACRO_CONTROL4__SI regUNIPHY_MACRO_CONTROL4__SI; -typedef union UNIPHY_REG_TEST_OUTPUT__SI regUNIPHY_REG_TEST_OUTPUT__SI; -typedef union UNIPHY_TRANSMITTER_CONTROL__SI regUNIPHY_TRANSMITTER_CONTROL__SI; -typedef union URGENCY_STAT__SI regURGENCY_STAT__SI; -typedef union USER_SQC_BANK_DISABLE regUSER_SQC_BANK_DISABLE; -typedef union UVD_ADDR_MODE__SI regUVD_ADDR_MODE__SI; -typedef union UVD_AVP_COOKIE_ID__SI regUVD_AVP_COOKIE_ID__SI; -typedef union UVD_AVP_CSA_ADDR__SI regUVD_AVP_CSA_ADDR__SI; -typedef union UVD_AVP_CSA_SIZE__SI regUVD_AVP_CSA_SIZE__SI; -typedef union UVD_AVP_EXT_INT_CTX_ID__SI regUVD_AVP_EXT_INT_CTX_ID__SI; -typedef union UVD_AVP_EXT_INT_ID__SI regUVD_AVP_EXT_INT_ID__SI; -typedef union UVD_AVP_FCS_STATUS__SI regUVD_AVP_FCS_STATUS__SI; -typedef union UVD_AVP_IDLE_COOKIE_ID__SI regUVD_AVP_IDLE_COOKIE_ID__SI; -typedef union UVD_AVP_RLC_HB_BASE__SI regUVD_AVP_RLC_HB_BASE__SI; -typedef union UVD_AVP_RLC_HB_CNTL__SI regUVD_AVP_RLC_HB_CNTL__SI; -typedef union UVD_AVP_RLC_HB_RPTR__SI regUVD_AVP_RLC_HB_RPTR__SI; -typedef union UVD_AVP_RLC_HB_WPTR_LSB_ADDR__SI regUVD_AVP_RLC_HB_WPTR_LSB_ADDR__SI; -typedef union UVD_AVP_RLC_HB_WPTR_MSB_ADDR__SI regUVD_AVP_RLC_HB_WPTR_MSB_ADDR__SI; -typedef union UVD_AVP_RLC_HB_WPTR__SI regUVD_AVP_RLC_HB_WPTR__SI; -typedef union UVD_AVP_RLC_RL_BASE__SI regUVD_AVP_RLC_RL_BASE__SI; -typedef union UVD_AVP_RLC_RL_SIZE__SI regUVD_AVP_RLC_RL_SIZE__SI; -typedef union UVD_AVP_RLC_SCRATCH__SI regUVD_AVP_RLC_SCRATCH__SI; -typedef union UVD_CBUF_ID__SI regUVD_CBUF_ID__SI; -typedef union UVD_CGC_CTRL__SI regUVD_CGC_CTRL__SI; -typedef union UVD_CGC_GATE__SI regUVD_CGC_GATE__SI; -typedef union UVD_CGC_STATUS__SI regUVD_CGC_STATUS__SI; -typedef union UVD_CONFIG__SI__CI regUVD_CONFIG__SI__CI; -typedef union UVD_CONTEXT_ID__SI regUVD_CONTEXT_ID__SI; -typedef union UVD_COOKIE_ID__SI regUVD_COOKIE_ID__SI; -typedef union UVD_CSA_ADDR__SI regUVD_CSA_ADDR__SI; -typedef union UVD_CSA_SIZE__SI regUVD_CSA_SIZE__SI; -typedef union UVD_CTX_DATA__SI regUVD_CTX_DATA__SI; -typedef union UVD_CTX_INDEX__SI regUVD_CTX_INDEX__SI; -typedef union UVD_CXW_BLOCK_STATUS__SI regUVD_CXW_BLOCK_STATUS__SI; -typedef union UVD_CXW_CNTL__SI regUVD_CXW_CNTL__SI; -typedef union UVD_CXW_EN__SI regUVD_CXW_EN__SI; -typedef union UVD_CXW_EVENT__SI regUVD_CXW_EVENT__SI; -typedef union UVD_CXW_FINISHED__SI regUVD_CXW_FINISHED__SI; -typedef union UVD_CXW_INT_ID__SI regUVD_CXW_INT_ID__SI; -typedef union UVD_CXW_SAVE_AREA_ADDR__SI regUVD_CXW_SAVE_AREA_ADDR__SI; -typedef union UVD_CXW_SAVE_AREA_SIZE__SI regUVD_CXW_SAVE_AREA_SIZE__SI; -typedef union UVD_CXW_SCAN_AREA_OFFSET__SI regUVD_CXW_SCAN_AREA_OFFSET__SI; -typedef union UVD_CXW_SE__SI regUVD_CXW_SE__SI; -typedef union UVD_CXW_SHIFT_CNTL__SI regUVD_CXW_SHIFT_CNTL__SI; -typedef union UVD_CXW_SHIFT_FINISHED__SI regUVD_CXW_SHIFT_FINISHED__SI; -typedef union UVD_CXW_START__SI regUVD_CXW_START__SI; -typedef union UVD_CXW_WR_INT_CTX_ID__SI regUVD_CXW_WR_INT_CTX_ID__SI; -typedef union UVD_CXW_WR_INT_ID__SI regUVD_CXW_WR_INT_ID__SI; -typedef union UVD_CXW_WR__SI regUVD_CXW_WR__SI; -typedef union UVD_DBW_BUF_SIZE__SI regUVD_DBW_BUF_SIZE__SI; -typedef union UVD_DBW_CHROMA_ADR__SI regUVD_DBW_CHROMA_ADR__SI; -typedef union UVD_DBW_CHROMA_BOT_ADR__SI regUVD_DBW_CHROMA_BOT_ADR__SI; -typedef union UVD_DBW_LUMA_ADR__SI regUVD_DBW_LUMA_ADR__SI; -typedef union UVD_DBW_LUMA_BOT_ADR__SI regUVD_DBW_LUMA_BOT_ADR__SI; -typedef union UVD_DBW_MACRO_TILE_CONFIG__SI regUVD_DBW_MACRO_TILE_CONFIG__SI; -typedef union UVD_DBW_MEM_ADDR_SEL_0__SI regUVD_DBW_MEM_ADDR_SEL_0__SI; -typedef union UVD_DBW_MEM_ADDR_SEL_1__SI regUVD_DBW_MEM_ADDR_SEL_1__SI; -typedef union UVD_DB_MACRO_TILE_CONFIG__SI regUVD_DB_MACRO_TILE_CONFIG__SI; -typedef union UVD_DB_MEM_ADDR_SEL_0__SI regUVD_DB_MEM_ADDR_SEL_0__SI; -typedef union UVD_DB_MEM_ADDR_SEL_1__SI regUVD_DB_MEM_ADDR_SEL_1__SI; -typedef union UVD_DEBUG_CTRL__SI regUVD_DEBUG_CTRL__SI; -typedef union UVD_DEBUG_SCRATCH__SI regUVD_DEBUG_SCRATCH__SI; -typedef union UVD_DRM_CMD__SI regUVD_DRM_CMD__SI; -typedef union UVD_DRM_CNTDAT0__SI regUVD_DRM_CNTDAT0__SI; -typedef union UVD_DRM_CNTDAT1__SI regUVD_DRM_CNTDAT1__SI; -typedef union UVD_DRM_CNTDAT2__SI regUVD_DRM_CNTDAT2__SI; -typedef union UVD_DRM_CNTDAT3__SI regUVD_DRM_CNTDAT3__SI; -typedef union UVD_DRM_CNTKEY0__SI regUVD_DRM_CNTKEY0__SI; -typedef union UVD_DRM_CNTKEY1__SI regUVD_DRM_CNTKEY1__SI; -typedef union UVD_DRM_CNTKEY2__SI regUVD_DRM_CNTKEY2__SI; -typedef union UVD_DRM_CNTKEY3__SI regUVD_DRM_CNTKEY3__SI; -typedef union UVD_DRM_KEY0__SI regUVD_DRM_KEY0__SI; -typedef union UVD_DRM_KEY1__SI regUVD_DRM_KEY1__SI; -typedef union UVD_DRM_KEY2__SI regUVD_DRM_KEY2__SI; -typedef union UVD_DRM_KEY3__SI regUVD_DRM_KEY3__SI; -typedef union UVD_DRM_OFFSET__SI regUVD_DRM_OFFSET__SI; -typedef union UVD_DRV_FW_MSG__SI regUVD_DRV_FW_MSG__SI; -typedef union UVD_DXVA_BUF_SIZE__SI regUVD_DXVA_BUF_SIZE__SI; -typedef union UVD_ENGINE_CNTL__SI regUVD_ENGINE_CNTL__SI; -typedef union UVD_FCS_AVP_SYS_INT_ACK__SI regUVD_FCS_AVP_SYS_INT_ACK__SI; -typedef union UVD_FCS_AVP_SYS_INT_EN__SI regUVD_FCS_AVP_SYS_INT_EN__SI; -typedef union UVD_FCS_AVP_SYS_INT_STAT__SI regUVD_FCS_AVP_SYS_INT_STAT__SI; -typedef union UVD_FCS_AVP_VCPU_INT_ACK__SI regUVD_FCS_AVP_VCPU_INT_ACK__SI; -typedef union UVD_FCS_AVP_VCPU_INT_EN__SI regUVD_FCS_AVP_VCPU_INT_EN__SI; -typedef union UVD_FCS_AVP_VCPU_INT_STAT__SI regUVD_FCS_AVP_VCPU_INT_STAT__SI; -typedef union UVD_FCS_CTRL__SI regUVD_FCS_CTRL__SI; -typedef union UVD_FCS_STATUS__SI regUVD_FCS_STATUS__SI; -typedef union UVD_FCS_SYS_INT_ACK__SI regUVD_FCS_SYS_INT_ACK__SI; -typedef union UVD_FCS_SYS_INT_EN__SI regUVD_FCS_SYS_INT_EN__SI; -typedef union UVD_FCS_SYS_INT_STAT__SI regUVD_FCS_SYS_INT_STAT__SI; -typedef union UVD_FCS_VCPU_INT_ACK__SI regUVD_FCS_VCPU_INT_ACK__SI; -typedef union UVD_FCS_VCPU_INT_EN__SI regUVD_FCS_VCPU_INT_EN__SI; -typedef union UVD_FCS_VCPU_INT_STAT__SI regUVD_FCS_VCPU_INT_STAT__SI; -typedef union UVD_FW_BYTECNT__SI regUVD_FW_BYTECNT__SI; -typedef union UVD_FW_DEBUG_ADDR__SI regUVD_FW_DEBUG_ADDR__SI; -typedef union UVD_FW_DEBUG_DATA__SI regUVD_FW_DEBUG_DATA__SI; -typedef union UVD_FW_DRV_MSG_ACK__SI regUVD_FW_DRV_MSG_ACK__SI; -typedef union UVD_FW_EXP_RESULT0__SI regUVD_FW_EXP_RESULT0__SI; -typedef union UVD_FW_EXP_RESULT1__SI regUVD_FW_EXP_RESULT1__SI; -typedef union UVD_FW_EXP_RESULT2__SI regUVD_FW_EXP_RESULT2__SI; -typedef union UVD_FW_EXP_RESULT3__SI regUVD_FW_EXP_RESULT3__SI; -typedef union UVD_FW_LENGTH__SI regUVD_FW_LENGTH__SI; -typedef union UVD_FW_NONCE0__SI regUVD_FW_NONCE0__SI; -typedef union UVD_FW_NONCE1__SI regUVD_FW_NONCE1__SI; -typedef union UVD_FW_NONCE2__SI regUVD_FW_NONCE2__SI; -typedef union UVD_FW_NONCE3__SI regUVD_FW_NONCE3__SI; -typedef union UVD_FW_PERIODIC_CNTL__SI regUVD_FW_PERIODIC_CNTL__SI; -typedef union UVD_FW_SELF_RECOVERY_CNTL__SI regUVD_FW_SELF_RECOVERY_CNTL__SI; -typedef union UVD_FW_START__SI regUVD_FW_START__SI; -typedef union UVD_FW_STATS__SI regUVD_FW_STATS__SI; -typedef union UVD_FW_STATUS__SI regUVD_FW_STATUS__SI; -typedef union UVD_GPCOM_SYS_CMD__SI regUVD_GPCOM_SYS_CMD__SI; -typedef union UVD_GPCOM_SYS_DATA0__SI regUVD_GPCOM_SYS_DATA0__SI; -typedef union UVD_GPCOM_SYS_DATA1__SI regUVD_GPCOM_SYS_DATA1__SI; -typedef union UVD_GPCOM_VCPU_CMD__SI regUVD_GPCOM_VCPU_CMD__SI; -typedef union UVD_GPCOM_VCPU_DATA0__SI regUVD_GPCOM_VCPU_DATA0__SI; -typedef union UVD_GPCOM_VCPU_DATA1__SI regUVD_GPCOM_VCPU_DATA1__SI; -typedef union UVD_GPF_STATUS__SI regUVD_GPF_STATUS__SI; -typedef union UVD_GP_SCRATCH0__SI regUVD_GP_SCRATCH0__SI; -typedef union UVD_GP_SCRATCH1__SI regUVD_GP_SCRATCH1__SI; -typedef union UVD_GP_SCRATCH2__SI regUVD_GP_SCRATCH2__SI; -typedef union UVD_GP_SCRATCH3__SI regUVD_GP_SCRATCH3__SI; -typedef union UVD_GP_SCRATCH4__SI regUVD_GP_SCRATCH4__SI; -typedef union UVD_GP_SCRATCH5__SI regUVD_GP_SCRATCH5__SI; -typedef union UVD_GP_SCRATCH6__SI regUVD_GP_SCRATCH6__SI; -typedef union UVD_GP_SCRATCH7__SI regUVD_GP_SCRATCH7__SI; -typedef union UVD_HEIGHT__SI regUVD_HEIGHT__SI; -typedef union UVD_IDLE_COOKIE_ID__SI regUVD_IDLE_COOKIE_ID__SI; -typedef union UVD_JOB_DONE__SI regUVD_JOB_DONE__SI; -typedef union UVD_JOB_START__SI regUVD_JOB_START__SI; -typedef union UVD_LBSI_ADDR_0__SI regUVD_LBSI_ADDR_0__SI; -typedef union UVD_LBSI_ADDR_1__SI regUVD_LBSI_ADDR_1__SI; -typedef union UVD_LBSI_BURST_LEN__SI regUVD_LBSI_BURST_LEN__SI; -typedef union UVD_LBSI_CONFIG__SI regUVD_LBSI_CONFIG__SI; -typedef union UVD_LBSI_CURR_ADDR__SI regUVD_LBSI_CURR_ADDR__SI; -typedef union UVD_LBSI_DRM_FLUSH_CTL_STATUS__SI regUVD_LBSI_DRM_FLUSH_CTL_STATUS__SI; -typedef union UVD_LBSI_LEN_0__SI regUVD_LBSI_LEN_0__SI; -typedef union UVD_LBSI_LEN_1__SI regUVD_LBSI_LEN_1__SI; -typedef union UVD_LBSI_PF_BUFF_COUNT__SI regUVD_LBSI_PF_BUFF_COUNT__SI; -typedef union UVD_LBSI_RE_WAIT_COUNT__SI regUVD_LBSI_RE_WAIT_COUNT__SI; -typedef union UVD_LMI_ADDR_EXT__SI regUVD_LMI_ADDR_EXT__SI; -typedef union UVD_LMI_ARB_CTRL__SI regUVD_LMI_ARB_CTRL__SI; -typedef union UVD_LMI_AVG_LAT_CNTR__SI regUVD_LMI_AVG_LAT_CNTR__SI; -typedef union UVD_LMI_AXI_ERR_STATUS__SI regUVD_LMI_AXI_ERR_STATUS__SI; -typedef union UVD_LMI_CACHE_CTRL__SI regUVD_LMI_CACHE_CTRL__SI; -typedef union UVD_LMI_CLEAN_STATUS__SI regUVD_LMI_CLEAN_STATUS__SI; -typedef union UVD_LMI_CRC0__SI regUVD_LMI_CRC0__SI; -typedef union UVD_LMI_CRC1__SI regUVD_LMI_CRC1__SI; -typedef union UVD_LMI_CRC2__SI regUVD_LMI_CRC2__SI; -typedef union UVD_LMI_CRC3__SI regUVD_LMI_CRC3__SI; -typedef union UVD_LMI_CRC4__SI regUVD_LMI_CRC4__SI; -typedef union UVD_LMI_CRC5__SI regUVD_LMI_CRC5__SI; -typedef union UVD_LMI_CRC6__SI regUVD_LMI_CRC6__SI; -typedef union UVD_LMI_CRC7__SI regUVD_LMI_CRC7__SI; -typedef union UVD_LMI_CTRL2__SI regUVD_LMI_CTRL2__SI; -typedef union UVD_LMI_CTRL__SI regUVD_LMI_CTRL__SI; -typedef union UVD_LMI_EXT40_ADDR__SI regUVD_LMI_EXT40_ADDR__SI; -typedef union UVD_LMI_ISOC_CTRL__SI regUVD_LMI_ISOC_CTRL__SI; -typedef union UVD_LMI_ISOC_PREF_BASE1__SI regUVD_LMI_ISOC_PREF_BASE1__SI; -typedef union UVD_LMI_ISOC_PREF_BASE2__SI regUVD_LMI_ISOC_PREF_BASE2__SI; -typedef union UVD_LMI_ISOC_PREF_LIMIT1__SI regUVD_LMI_ISOC_PREF_LIMIT1__SI; -typedef union UVD_LMI_ISOC_PREF_LIMIT2__SI regUVD_LMI_ISOC_PREF_LIMIT2__SI; -typedef union UVD_LMI_LAT_CNTR__SI regUVD_LMI_LAT_CNTR__SI; -typedef union UVD_LMI_LAT_CTRL__SI regUVD_LMI_LAT_CTRL__SI; -typedef union UVD_LMI_MC_CREDITS__SI regUVD_LMI_MC_CREDITS__SI; -typedef union UVD_LMI_PERFMON_COUNT_HI__SI regUVD_LMI_PERFMON_COUNT_HI__SI; -typedef union UVD_LMI_PERFMON_COUNT_LO__SI regUVD_LMI_PERFMON_COUNT_LO__SI; -typedef union UVD_LMI_PERFMON_CTRL__SI regUVD_LMI_PERFMON_CTRL__SI; -typedef union UVD_LMI_RD_BURST_CTRL__SI regUVD_LMI_RD_BURST_CTRL__SI; -typedef union UVD_LMI_SPH__SI regUVD_LMI_SPH__SI; -typedef union UVD_LMI_STATUS__SI regUVD_LMI_STATUS__SI; -typedef union UVD_LMI_SWAP_CNTL__SI regUVD_LMI_SWAP_CNTL__SI; -typedef union UVD_LMI_URGENT_CTRL__SI regUVD_LMI_URGENT_CTRL__SI; -typedef union UVD_LMI_UVD_SWAP__SI regUVD_LMI_UVD_SWAP__SI; -typedef union UVD_LMI_VCPU_VM1__SI regUVD_LMI_VCPU_VM1__SI; -typedef union UVD_LMI_VCPU_VM__SI regUVD_LMI_VCPU_VM__SI; -typedef union UVD_LMI_VM_CTRL__SI regUVD_LMI_VM_CTRL__SI; -typedef union UVD_LMI_WR_BURST_CTRL__SI regUVD_LMI_WR_BURST_CTRL__SI; -typedef union UVD_LMI_WR_COMB_CTRL__SI regUVD_LMI_WR_COMB_CTRL__SI; -typedef union UVD_MACRO_TILE_CONFIG__SI regUVD_MACRO_TILE_CONFIG__SI; -typedef union UVD_MASTINT_EN__SI regUVD_MASTINT_EN__SI; -typedef union UVD_MB_CTL_BUF_BASE__SI regUVD_MB_CTL_BUF_BASE__SI; -typedef union UVD_MEM_ADDR_SEL_0__SI regUVD_MEM_ADDR_SEL_0__SI; -typedef union UVD_MEM_ADDR_SEL_1__SI regUVD_MEM_ADDR_SEL_1__SI; -typedef union UVD_MPC_CHROMA_HITPEND__SI regUVD_MPC_CHROMA_HITPEND__SI; -typedef union UVD_MPC_CHROMA_HIT__SI regUVD_MPC_CHROMA_HIT__SI; -typedef union UVD_MPC_CHROMA_SRCH__SI regUVD_MPC_CHROMA_SRCH__SI; -typedef union UVD_MPC_CNTL__SI regUVD_MPC_CNTL__SI; -typedef union UVD_MPC_LUMA_HITPEND__SI regUVD_MPC_LUMA_HITPEND__SI; -typedef union UVD_MPC_LUMA_HIT__SI regUVD_MPC_LUMA_HIT__SI; -typedef union UVD_MPC_LUMA_SRCH__SI regUVD_MPC_LUMA_SRCH__SI; -typedef union UVD_MPC_PERF0__SI regUVD_MPC_PERF0__SI; -typedef union UVD_MPC_PERF1__SI regUVD_MPC_PERF1__SI; -typedef union UVD_MPC_PITCH__SI regUVD_MPC_PITCH__SI; -typedef union UVD_MPC_REF_BAR0__SI regUVD_MPC_REF_BAR0__SI; -typedef union UVD_MPC_REF_BAR10__SI regUVD_MPC_REF_BAR10__SI; -typedef union UVD_MPC_REF_BAR11__SI regUVD_MPC_REF_BAR11__SI; -typedef union UVD_MPC_REF_BAR12__SI regUVD_MPC_REF_BAR12__SI; -typedef union UVD_MPC_REF_BAR13__SI regUVD_MPC_REF_BAR13__SI; -typedef union UVD_MPC_REF_BAR14__SI regUVD_MPC_REF_BAR14__SI; -typedef union UVD_MPC_REF_BAR15__SI regUVD_MPC_REF_BAR15__SI; -typedef union UVD_MPC_REF_BAR16__SI regUVD_MPC_REF_BAR16__SI; -typedef union UVD_MPC_REF_BAR1__SI regUVD_MPC_REF_BAR1__SI; -typedef union UVD_MPC_REF_BAR2__SI regUVD_MPC_REF_BAR2__SI; -typedef union UVD_MPC_REF_BAR3__SI regUVD_MPC_REF_BAR3__SI; -typedef union UVD_MPC_REF_BAR4__SI regUVD_MPC_REF_BAR4__SI; -typedef union UVD_MPC_REF_BAR5__SI regUVD_MPC_REF_BAR5__SI; -typedef union UVD_MPC_REF_BAR6__SI regUVD_MPC_REF_BAR6__SI; -typedef union UVD_MPC_REF_BAR7__SI regUVD_MPC_REF_BAR7__SI; -typedef union UVD_MPC_REF_BAR8__SI regUVD_MPC_REF_BAR8__SI; -typedef union UVD_MPC_REF_BAR9__SI regUVD_MPC_REF_BAR9__SI; -typedef union UVD_MPC_REF_PIC_ADDR_CONF__SI regUVD_MPC_REF_PIC_ADDR_CONF__SI; -typedef union UVD_MPC_SET_ALU__SI regUVD_MPC_SET_ALU__SI; -typedef union UVD_MPC_SET_MUXA0__SI regUVD_MPC_SET_MUXA0__SI; -typedef union UVD_MPC_SET_MUXA1__SI regUVD_MPC_SET_MUXA1__SI; -typedef union UVD_MPC_SET_MUXB0__SI regUVD_MPC_SET_MUXB0__SI; -typedef union UVD_MPC_SET_MUXB1__SI regUVD_MPC_SET_MUXB1__SI; -typedef union UVD_MPC_SET_MUX__SI regUVD_MPC_SET_MUX__SI; -typedef union UVD_MPEG2_CTRL__SI regUVD_MPEG2_CTRL__SI; -typedef union UVD_MPEG2_ERROR__SI regUVD_MPEG2_ERROR__SI; -typedef union UVD_MPRD_INITIAL_XY__SI regUVD_MPRD_INITIAL_XY__SI; -typedef union UVD_MP_SWAP_CNTL__SI regUVD_MP_SWAP_CNTL__SI; -typedef union UVD_NO_OP__SI regUVD_NO_OP__SI; -typedef union UVD_PERF_BANK_CONF__SI regUVD_PERF_BANK_CONF__SI; -typedef union UVD_PERF_BANK_COUNT0__SI regUVD_PERF_BANK_COUNT0__SI; -typedef union UVD_PERF_BANK_COUNT1__SI regUVD_PERF_BANK_COUNT1__SI; -typedef union UVD_PERF_BANK_COUNT2__SI regUVD_PERF_BANK_COUNT2__SI; -typedef union UVD_PERF_BANK_COUNT3__SI regUVD_PERF_BANK_COUNT3__SI; -typedef union UVD_PERF_BANK_COUNT4__SI regUVD_PERF_BANK_COUNT4__SI; -typedef union UVD_PERF_BANK_COUNT5__SI regUVD_PERF_BANK_COUNT5__SI; -typedef union UVD_PERF_BANK_COUNT6__SI regUVD_PERF_BANK_COUNT6__SI; -typedef union UVD_PERF_BANK_COUNT7__SI regUVD_PERF_BANK_COUNT7__SI; -typedef union UVD_PERF_BANK_EVENT_SEL0__SI regUVD_PERF_BANK_EVENT_SEL0__SI; -typedef union UVD_PERF_BANK_EVENT_SEL1__SI regUVD_PERF_BANK_EVENT_SEL1__SI; -typedef union UVD_PICCOUNT__SI regUVD_PICCOUNT__SI; -typedef union UVD_PIC_CTL_BUF_BASE__SI regUVD_PIC_CTL_BUF_BASE__SI; -typedef union UVD_PITCH__SI regUVD_PITCH__SI; -typedef union UVD_PRIVILEGE_REG_MASK_1__SI regUVD_PRIVILEGE_REG_MASK_1__SI; -typedef union UVD_PRIVILEGE_REG_MASK_IDCT__SI regUVD_PRIVILEGE_REG_MASK_IDCT__SI; -typedef union UVD_PWR_STATUS__SI regUVD_PWR_STATUS__SI; -typedef union UVD_RBC_BDM_PRE__SI regUVD_RBC_BDM_PRE__SI; -typedef union UVD_RBC_BUF_STATUS__SI regUVD_RBC_BUF_STATUS__SI; -typedef union UVD_RBC_CAM_DATA__SI regUVD_RBC_CAM_DATA__SI; -typedef union UVD_RBC_CAM_EN__SI regUVD_RBC_CAM_EN__SI; -typedef union UVD_RBC_CAM_INDEX__SI regUVD_RBC_CAM_INDEX__SI; -typedef union UVD_RBC_CXW_RELEASE__SI regUVD_RBC_CXW_RELEASE__SI; -typedef union UVD_RBC_IB_BASE__SI regUVD_RBC_IB_BASE__SI; -typedef union UVD_RBC_IB_PRIVILEGE_REG_CHECK__SI regUVD_RBC_IB_PRIVILEGE_REG_CHECK__SI; -typedef union UVD_RBC_IB_SIZE_UPDATE__SI regUVD_RBC_IB_SIZE_UPDATE__SI; -typedef union UVD_RBC_IB_SIZE__SI regUVD_RBC_IB_SIZE__SI; -typedef union UVD_RBC_PRIV_FAULT_REG__SI regUVD_RBC_PRIV_FAULT_REG__SI; -typedef union UVD_RBC_RB_BASE__SI regUVD_RBC_RB_BASE__SI; -typedef union UVD_RBC_RB_CNTL__SI regUVD_RBC_RB_CNTL__SI; -typedef union UVD_RBC_RB_RPTR_ADDR__SI regUVD_RBC_RB_RPTR_ADDR__SI; -typedef union UVD_RBC_RB_RPTR__SI regUVD_RBC_RB_RPTR__SI; -typedef union UVD_RBC_RB_WPTR_CNTL__SI regUVD_RBC_RB_WPTR_CNTL__SI; -typedef union UVD_RBC_RB_WPTR__SI regUVD_RBC_RB_WPTR__SI; -typedef union UVD_RBC_READ_REQ_URGENT_CNTL__SI regUVD_RBC_READ_REQ_URGENT_CNTL__SI; -typedef union UVD_RBC_VCPU_ACCESS__SI regUVD_RBC_VCPU_ACCESS__SI; -typedef union UVD_RBC_WPTR_POLL_ADDR__SI regUVD_RBC_WPTR_POLL_ADDR__SI; -typedef union UVD_RBC_WPTR_POLL_CNTL__SI regUVD_RBC_WPTR_POLL_CNTL__SI; -typedef union UVD_RBC_WPTR_STATUS__SI regUVD_RBC_WPTR_STATUS__SI; -typedef union UVD_RB_ARB_CTRL__SI regUVD_RB_ARB_CTRL__SI; -typedef union UVD_REPLAY_OFFSET__SI regUVD_REPLAY_OFFSET__SI; -typedef union UVD_RESERVED_0__SI regUVD_RESERVED_0__SI; -typedef union UVD_RESERVED_1__SI regUVD_RESERVED_1__SI; -typedef union UVD_RESERVED_2__SI regUVD_RESERVED_2__SI; -typedef union UVD_RLC_CONTROL__SI regUVD_RLC_CONTROL__SI; -typedef union UVD_RLC_HB_BASE__SI regUVD_RLC_HB_BASE__SI; -typedef union UVD_RLC_HB_CNTL__SI regUVD_RLC_HB_CNTL__SI; -typedef union UVD_RLC_HB_RPTR__SI regUVD_RLC_HB_RPTR__SI; -typedef union UVD_RLC_HB_WPTR_LSB_ADDR__SI regUVD_RLC_HB_WPTR_LSB_ADDR__SI; -typedef union UVD_RLC_HB_WPTR_MSB_ADDR__SI regUVD_RLC_HB_WPTR_MSB_ADDR__SI; -typedef union UVD_RLC_HB_WPTR__SI regUVD_RLC_HB_WPTR__SI; -typedef union UVD_RLC_RL_BASE__SI regUVD_RLC_RL_BASE__SI; -typedef union UVD_RLC_RL_SIZE__SI regUVD_RLC_RL_SIZE__SI; -typedef union UVD_RLC_SCRATCH__SI regUVD_RLC_SCRATCH__SI; -typedef union UVD_RMAP_CONF__SI regUVD_RMAP_CONF__SI; -typedef union UVD_SCRATCH_NP__SI regUVD_SCRATCH_NP__SI; -typedef union UVD_SEMA_ADDR_HIGH__SI regUVD_SEMA_ADDR_HIGH__SI; -typedef union UVD_SEMA_ADDR_LOW__SI regUVD_SEMA_ADDR_LOW__SI; -typedef union UVD_SEMA_CMD__SI regUVD_SEMA_CMD__SI; -typedef union UVD_SEMA_CNTL__SI regUVD_SEMA_CNTL__SI; -typedef union UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI - regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI; -typedef union UVD_SEMA_TIMEOUT_STATUS__SI regUVD_SEMA_TIMEOUT_STATUS__SI; -typedef union UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI; -typedef union UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI - regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI; -typedef union UVD_SOFT_RESET__SI regUVD_SOFT_RESET__SI; -typedef union UVD_STATUS__SI regUVD_STATUS__SI; -typedef union UVD_STOP_CONTEXT__SI regUVD_STOP_CONTEXT__SI; -typedef union UVD_SW_SCRATCH_00__SI regUVD_SW_SCRATCH_00__SI; -typedef union UVD_SW_SCRATCH_01__SI regUVD_SW_SCRATCH_01__SI; -typedef union UVD_SW_SCRATCH_02__SI regUVD_SW_SCRATCH_02__SI; -typedef union UVD_SW_SCRATCH_03__SI regUVD_SW_SCRATCH_03__SI; -typedef union UVD_SW_SCRATCH_04__SI regUVD_SW_SCRATCH_04__SI; -typedef union UVD_SW_SCRATCH_05__SI regUVD_SW_SCRATCH_05__SI; -typedef union UVD_SW_SCRATCH_06__SI regUVD_SW_SCRATCH_06__SI; -typedef union UVD_SW_SCRATCH_07__SI regUVD_SW_SCRATCH_07__SI; -typedef union UVD_SW_SCRATCH_08__SI regUVD_SW_SCRATCH_08__SI; -typedef union UVD_SW_SCRATCH_09__SI regUVD_SW_SCRATCH_09__SI; -typedef union UVD_SW_SCRATCH_10__SI regUVD_SW_SCRATCH_10__SI; -typedef union UVD_SW_SCRATCH_11__SI regUVD_SW_SCRATCH_11__SI; -typedef union UVD_SW_SCRATCH_12__SI regUVD_SW_SCRATCH_12__SI; -typedef union UVD_SW_SCRATCH_13__SI regUVD_SW_SCRATCH_13__SI; -typedef union UVD_SW_SCRATCH_14__SI regUVD_SW_SCRATCH_14__SI; -typedef union UVD_SW_SCRATCH_15__SI regUVD_SW_SCRATCH_15__SI; -typedef union UVD_SYS_INT_ACK__SI regUVD_SYS_INT_ACK__SI; -typedef union UVD_SYS_INT_EN__SI regUVD_SYS_INT_EN__SI; -typedef union UVD_SYS_INT_STATUS__SI regUVD_SYS_INT_STATUS__SI; -typedef union UVD_UDEC_ADR__SI regUVD_UDEC_ADR__SI; -typedef union UVD_UDEC_DBW_TILING_CONFIG__SI regUVD_UDEC_DBW_TILING_CONFIG__SI; -typedef union UVD_UDEC_DB_TILING_CONFIG__SI regUVD_UDEC_DB_TILING_CONFIG__SI; -typedef union UVD_UDEC_DEBUG_MUX__SI regUVD_UDEC_DEBUG_MUX__SI; -typedef union UVD_UDEC_TILING_CONFIG__SI regUVD_UDEC_TILING_CONFIG__SI; -typedef union UVD_UMC_AVP_BLOCK_REQ__SI regUVD_UMC_AVP_BLOCK_REQ__SI; -typedef union UVD_UMC_AVP_CTL_CMD__SI regUVD_UMC_AVP_CTL_CMD__SI; -typedef union UVD_UMC_IDCT_BLOCK_REQ__SI regUVD_UMC_IDCT_BLOCK_REQ__SI; -typedef union UVD_UMC_IDCT_CTL_CMD__SI regUVD_UMC_IDCT_CTL_CMD__SI; -typedef union UVD_UMC_UVD_BLOCK_REQ__SI regUVD_UMC_UVD_BLOCK_REQ__SI; -typedef union UVD_UMC_UVD_CTL_CMD__SI regUVD_UMC_UVD_CTL_CMD__SI; -typedef union UVD_UVBASE__SI regUVD_UVBASE__SI; -typedef union UVD_VCPU_CACHE_OFFSET0__SI regUVD_VCPU_CACHE_OFFSET0__SI; -typedef union UVD_VCPU_CACHE_OFFSET1__SI regUVD_VCPU_CACHE_OFFSET1__SI; -typedef union UVD_VCPU_CACHE_OFFSET2__SI regUVD_VCPU_CACHE_OFFSET2__SI; -typedef union UVD_VCPU_CACHE_OFFSET3__SI regUVD_VCPU_CACHE_OFFSET3__SI; -typedef union UVD_VCPU_CACHE_OFFSET4__SI regUVD_VCPU_CACHE_OFFSET4__SI; -typedef union UVD_VCPU_CACHE_OFFSET5__SI regUVD_VCPU_CACHE_OFFSET5__SI; -typedef union UVD_VCPU_CACHE_OFFSET6__SI regUVD_VCPU_CACHE_OFFSET6__SI; -typedef union UVD_VCPU_CACHE_OFFSET7__SI regUVD_VCPU_CACHE_OFFSET7__SI; -typedef union UVD_VCPU_CACHE_OFFSET8__SI regUVD_VCPU_CACHE_OFFSET8__SI; -typedef union UVD_VCPU_CACHE_SIZE0__SI regUVD_VCPU_CACHE_SIZE0__SI; -typedef union UVD_VCPU_CACHE_SIZE1__SI regUVD_VCPU_CACHE_SIZE1__SI; -typedef union UVD_VCPU_CACHE_SIZE2__SI regUVD_VCPU_CACHE_SIZE2__SI; -typedef union UVD_VCPU_CACHE_SIZE3__SI regUVD_VCPU_CACHE_SIZE3__SI; -typedef union UVD_VCPU_CACHE_SIZE4__SI regUVD_VCPU_CACHE_SIZE4__SI; -typedef union UVD_VCPU_CACHE_SIZE5__SI regUVD_VCPU_CACHE_SIZE5__SI; -typedef union UVD_VCPU_CACHE_SIZE6__SI regUVD_VCPU_CACHE_SIZE6__SI; -typedef union UVD_VCPU_CACHE_SIZE7__SI regUVD_VCPU_CACHE_SIZE7__SI; -typedef union UVD_VCPU_CACHE_SIZE8__SI regUVD_VCPU_CACHE_SIZE8__SI; -typedef union UVD_VCPU_CNTL__SI regUVD_VCPU_CNTL__SI; -typedef union UVD_VCPU_DBG__SI regUVD_VCPU_DBG__SI; -typedef union UVD_VCPU_INT_ACK__SI regUVD_VCPU_INT_ACK__SI; -typedef union UVD_VCPU_INT_EN__SI regUVD_VCPU_INT_EN__SI; -typedef union UVD_VCPU_INT_ROUTE__SI regUVD_VCPU_INT_ROUTE__SI; -typedef union UVD_VCPU_INT_STATUS__SI regUVD_VCPU_INT_STATUS__SI; -typedef union UVD_VCPU_NONCACHE_OFFSET0__SI regUVD_VCPU_NONCACHE_OFFSET0__SI; -typedef union UVD_VCPU_NONCACHE_OFFSET1__SI regUVD_VCPU_NONCACHE_OFFSET1__SI; -typedef union UVD_VCPU_NONCACHE_SIZE0__SI regUVD_VCPU_NONCACHE_SIZE0__SI; -typedef union UVD_VCPU_NONCACHE_SIZE1__SI regUVD_VCPU_NONCACHE_SIZE1__SI; -typedef union UVD_VCPU_PDEBUG_CCOUNT__SI regUVD_VCPU_PDEBUG_CCOUNT__SI; -typedef union UVD_VCPU_PDEBUG_DATA_H__SI regUVD_VCPU_PDEBUG_DATA_H__SI; -typedef union UVD_VCPU_PDEBUG_DATA_L__SI regUVD_VCPU_PDEBUG_DATA_L__SI; -typedef union UVD_VCPU_PDEBUG_EPC__SI regUVD_VCPU_PDEBUG_EPC__SI; -typedef union UVD_VCPU_PDEBUG_EXCCAUSE__SI regUVD_VCPU_PDEBUG_EXCCAUSE__SI; -typedef union UVD_VCPU_PDEBUG_ICOUNT__SI regUVD_VCPU_PDEBUG_ICOUNT__SI; -typedef union UVD_VCPU_PDEBUG_PSTATUS__SI regUVD_VCPU_PDEBUG_PSTATUS__SI; -typedef union UVD_VCPU_PDEBUG_PS__SI regUVD_VCPU_PDEBUG_PS__SI; -typedef union UVD_VCPU_PRID__SI regUVD_VCPU_PRID__SI; -typedef union UVD_VCPU_TRCE_RD__SI regUVD_VCPU_TRCE_RD__SI; -typedef union UVD_VCPU_TRCE__SI regUVD_VCPU_TRCE__SI; -typedef union UVD_WIDTH__SI regUVD_WIDTH__SI; -typedef union UVD_YBASE__SI regUVD_YBASE__SI; -typedef union VBLANK_STATUS__SI regVBLANK_STATUS__SI; -typedef union VCE_CONFIG__CI regVCE_CONFIG__CI; -typedef union VENDOR_CAP_LIST__CI__VI regVENDOR_CAP_LIST__CI__VI; -typedef union VENDOR_ID regVENDOR_ID; -typedef union VGA25_PPLL_CNTL__SI regVGA25_PPLL_CNTL__SI; -typedef union VGA25_PPLL_FB_DIV__SI regVGA25_PPLL_FB_DIV__SI; -typedef union VGA25_PPLL_POST_DIV_SRC__SI regVGA25_PPLL_POST_DIV_SRC__SI; -typedef union VGA25_PPLL_POST_DIV__SI regVGA25_PPLL_POST_DIV__SI; -typedef union VGA25_PPLL_REF_DIV_SRC__SI regVGA25_PPLL_REF_DIV_SRC__SI; -typedef union VGA25_PPLL_REF_DIV__SI regVGA25_PPLL_REF_DIV__SI; -typedef union VGA28_PPLL_CNTL__SI regVGA28_PPLL_CNTL__SI; -typedef union VGA28_PPLL_FB_DIV__SI regVGA28_PPLL_FB_DIV__SI; -typedef union VGA28_PPLL_POST_DIV_SRC__SI regVGA28_PPLL_POST_DIV_SRC__SI; -typedef union VGA28_PPLL_POST_DIV__SI regVGA28_PPLL_POST_DIV__SI; -typedef union VGA28_PPLL_REF_DIV_SRC__SI regVGA28_PPLL_REF_DIV_SRC__SI; -typedef union VGA28_PPLL_REF_DIV__SI regVGA28_PPLL_REF_DIV__SI; -typedef union VGA41_PPLL_CNTL__SI regVGA41_PPLL_CNTL__SI; -typedef union VGA41_PPLL_FB_DIV__SI regVGA41_PPLL_FB_DIV__SI; -typedef union VGA41_PPLL_POST_DIV_SRC__SI regVGA41_PPLL_POST_DIV_SRC__SI; -typedef union VGA41_PPLL_POST_DIV__SI regVGA41_PPLL_POST_DIV__SI; -typedef union VGA41_PPLL_REF_DIV_SRC__SI regVGA41_PPLL_REF_DIV_SRC__SI; -typedef union VGA41_PPLL_REF_DIV__SI regVGA41_PPLL_REF_DIV__SI; -typedef union VGADCCIF_HOSTIF_R_ADDR__SI regVGADCCIF_HOSTIF_R_ADDR__SI; -typedef union VGADCCIF_HOSTIF_W_ADDR__SI regVGADCCIF_HOSTIF_W_ADDR__SI; -typedef union VGADCCIF_RENDERIF_R_ADDR__SI regVGADCCIF_RENDERIF_R_ADDR__SI; -typedef union VGADCCIF_RENDERIF_W_ADDR__SI regVGADCCIF_RENDERIF_W_ADDR__SI; -typedef union VGADCC_DBG_DCCIF_A__SI regVGADCC_DBG_DCCIF_A__SI; -typedef union VGADCC_DBG_DCCIF_B__SI regVGADCC_DBG_DCCIF_B__SI; -typedef union VGADCC_DBG_DCCIF_C__SI regVGADCC_DBG_DCCIF_C__SI; -typedef union VGADCC_DBG_DCCIF_D__SI regVGADCC_DBG_DCCIF_D__SI; -typedef union VGADCC_DBG_DCCIF_E__SI regVGADCC_DBG_DCCIF_E__SI; -typedef union VGADCC_DBG_DCCIF_F__SI regVGADCC_DBG_DCCIF_F__SI; -typedef union VGADCC_DBG_DCCIF_G__SI regVGADCC_DBG_DCCIF_G__SI; -typedef union VGADCC_DBG_DCCIF_H__SI regVGADCC_DBG_DCCIF_H__SI; -typedef union VGADCC_DBG_DCCIF_I__SI regVGADCC_DBG_DCCIF_I__SI; -typedef union VGADCC_DBG_DCCIF_J__SI regVGADCC_DBG_DCCIF_J__SI; -typedef union VGADCC_DBG_DCCIF_K__SI regVGADCC_DBG_DCCIF_K__SI; -typedef union VGADCC_DBG_DCCIF_L__SI regVGADCC_DBG_DCCIF_L__SI; -typedef union VGADCC_DBG_DCCIF_M__SI regVGADCC_DBG_DCCIF_M__SI; -typedef union VGADCC_DBG_DCCIF_N__SI regVGADCC_DBG_DCCIF_N__SI; -typedef union VGADCC_DBG_DCCIF_O__SI regVGADCC_DBG_DCCIF_O__SI; -typedef union VGADCC_DBG_DCCIF_P__SI regVGADCC_DBG_DCCIF_P__SI; -typedef union VGA_ADDR__SI regVGA_ADDR__SI; -typedef union VGA_CACHE_CONTROL__SI regVGA_CACHE_CONTROL__SI; -typedef union VGA_COHERENCY_TIMER_CNTL__SI regVGA_COHERENCY_TIMER_CNTL__SI; -typedef union VGA_CRTC__SI regVGA_CRTC__SI; -typedef union VGA_DEBUG_ID__SI regVGA_DEBUG_ID__SI; -typedef union VGA_DEBUG_READBACK_DATA__SI regVGA_DEBUG_READBACK_DATA__SI; -typedef union VGA_DEBUG_READBACK_INDEX__SI regVGA_DEBUG_READBACK_INDEX__SI; -typedef union VGA_DISPBUF1_SURFACE_ADDR__SI regVGA_DISPBUF1_SURFACE_ADDR__SI; -typedef union VGA_DISPBUF2_SURFACE_ADDR__SI regVGA_DISPBUF2_SURFACE_ADDR__SI; -typedef union VGA_GRAPH__SI regVGA_GRAPH__SI; -typedef union VGA_HDP_CONTROL__SI regVGA_HDP_CONTROL__SI; -typedef union VGA_HDP__SI regVGA_HDP__SI; -typedef union VGA_HW_DEBUG__SI regVGA_HW_DEBUG__SI; -typedef union VGA_INTERRUPT_CONTROL__SI regVGA_INTERRUPT_CONTROL__SI; -typedef union VGA_INTERRUPT_STATUS__SI regVGA_INTERRUPT_STATUS__SI; -typedef union VGA_MAIN_CONTROL__SI regVGA_MAIN_CONTROL__SI; -typedef union VGA_MAIN__SI regVGA_MAIN__SI; -typedef union VGA_MEMORY_BASE_ADDRESS_HIGH__SI regVGA_MEMORY_BASE_ADDRESS_HIGH__SI; -typedef union VGA_MEMORY_BASE_ADDRESS__SI regVGA_MEMORY_BASE_ADDRESS__SI; -typedef union VGA_MEM_READ_PAGE_ADDR__SI regVGA_MEM_READ_PAGE_ADDR__SI; -typedef union VGA_MEM_WRITE_PAGE_ADDR__SI regVGA_MEM_WRITE_PAGE_ADDR__SI; -typedef union VGA_MODE_CONTROL__SI regVGA_MODE_CONTROL__SI; -typedef union VGA_REG__SI regVGA_REG__SI; -typedef union VGA_RENDER_CONTROL__SI regVGA_RENDER_CONTROL__SI; -typedef union VGA_SEQUENCER_RESET_CONTROL__SI regVGA_SEQUENCER_RESET_CONTROL__SI; -typedef union VGA_SOURCE_SELECT__SI regVGA_SOURCE_SELECT__SI; -typedef union VGA_STATUS_CLEAR__SI regVGA_STATUS_CLEAR__SI; -typedef union VGA_STATUS__SI regVGA_STATUS__SI; -typedef union VGA_SURFACE_PITCH_SELECT__SI regVGA_SURFACE_PITCH_SELECT__SI; -typedef union VGA_TEST_CONTROL__SI regVGA_TEST_CONTROL__SI; -typedef union VGA_TEST_DEBUG_DATA__SI regVGA_TEST_DEBUG_DATA__SI; -typedef union VGA_TEST_DEBUG_INDEX__SI regVGA_TEST_DEBUG_INDEX__SI; -typedef union VGA_TEXT__SI regVGA_TEXT__SI; -typedef union VGA_VGADCCIF__SI regVGA_VGADCCIF__SI; -typedef union VGT_CACHE_INVALIDATION regVGT_CACHE_INVALIDATION; -typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; -typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; -typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; -typedef union VGT_DEBUG_REG0 regVGT_DEBUG_REG0; -typedef union VGT_DEBUG_REG1 regVGT_DEBUG_REG1; -typedef union VGT_DEBUG_REG10__CI__VI regVGT_DEBUG_REG10__CI__VI; -typedef union VGT_DEBUG_REG10__SI regVGT_DEBUG_REG10__SI; -typedef union VGT_DEBUG_REG11__CI__VI regVGT_DEBUG_REG11__CI__VI; -typedef union VGT_DEBUG_REG11__SI regVGT_DEBUG_REG11__SI; -typedef union VGT_DEBUG_REG12 regVGT_DEBUG_REG12; -typedef union VGT_DEBUG_REG13 regVGT_DEBUG_REG13; -typedef union VGT_DEBUG_REG14 regVGT_DEBUG_REG14; -typedef union VGT_DEBUG_REG15__CI__VI regVGT_DEBUG_REG15__CI__VI; -typedef union VGT_DEBUG_REG15__SI regVGT_DEBUG_REG15__SI; -typedef union VGT_DEBUG_REG16__CI__VI regVGT_DEBUG_REG16__CI__VI; -typedef union VGT_DEBUG_REG16__SI regVGT_DEBUG_REG16__SI; -typedef union VGT_DEBUG_REG17 regVGT_DEBUG_REG17; -typedef union VGT_DEBUG_REG18__CI__VI regVGT_DEBUG_REG18__CI__VI; -typedef union VGT_DEBUG_REG18__SI regVGT_DEBUG_REG18__SI; -typedef union VGT_DEBUG_REG19__CI__VI regVGT_DEBUG_REG19__CI__VI; -typedef union VGT_DEBUG_REG19__SI regVGT_DEBUG_REG19__SI; -typedef union VGT_DEBUG_REG20 regVGT_DEBUG_REG20; -typedef union VGT_DEBUG_REG21 regVGT_DEBUG_REG21; -typedef union VGT_DEBUG_REG22 regVGT_DEBUG_REG22; -typedef union VGT_DEBUG_REG23 regVGT_DEBUG_REG23; -typedef union VGT_DEBUG_REG24 regVGT_DEBUG_REG24; -typedef union VGT_DEBUG_REG25 regVGT_DEBUG_REG25; -typedef union VGT_DEBUG_REG26__CI__VI regVGT_DEBUG_REG26__CI__VI; -typedef union VGT_DEBUG_REG26__SI regVGT_DEBUG_REG26__SI; -typedef union VGT_DEBUG_REG27 regVGT_DEBUG_REG27; -typedef union VGT_DEBUG_REG28 regVGT_DEBUG_REG28; -typedef union VGT_DEBUG_REG29 regVGT_DEBUG_REG29; -typedef union VGT_DEBUG_REG2__CI__VI regVGT_DEBUG_REG2__CI__VI; -typedef union VGT_DEBUG_REG2__SI regVGT_DEBUG_REG2__SI; -typedef union VGT_DEBUG_REG30__CI regVGT_DEBUG_REG30__CI; -typedef union VGT_DEBUG_REG30__SI regVGT_DEBUG_REG30__SI; -typedef union VGT_DEBUG_REG31__CI__VI regVGT_DEBUG_REG31__CI__VI; -typedef union VGT_DEBUG_REG31__SI regVGT_DEBUG_REG31__SI; -typedef union VGT_DEBUG_REG32__CI__VI regVGT_DEBUG_REG32__CI__VI; -typedef union VGT_DEBUG_REG32__SI regVGT_DEBUG_REG32__SI; -typedef union VGT_DEBUG_REG33__CI__VI regVGT_DEBUG_REG33__CI__VI; -typedef union VGT_DEBUG_REG33__SI regVGT_DEBUG_REG33__SI; -typedef union VGT_DEBUG_REG34__CI__VI regVGT_DEBUG_REG34__CI__VI; -typedef union VGT_DEBUG_REG34__SI regVGT_DEBUG_REG34__SI; -typedef union VGT_DEBUG_REG35__CI regVGT_DEBUG_REG35__CI; -typedef union VGT_DEBUG_REG35__SI regVGT_DEBUG_REG35__SI; -typedef union VGT_DEBUG_REG36__SI regVGT_DEBUG_REG36__SI; -typedef union VGT_DEBUG_REG36__VI regVGT_DEBUG_REG36__VI; -typedef union VGT_DEBUG_REG37__SI regVGT_DEBUG_REG37__SI; -typedef union VGT_DEBUG_REG38__SI regVGT_DEBUG_REG38__SI; -typedef union VGT_DEBUG_REG39__SI regVGT_DEBUG_REG39__SI; -typedef union VGT_DEBUG_REG3__CI__VI regVGT_DEBUG_REG3__CI__VI; -typedef union VGT_DEBUG_REG3__SI regVGT_DEBUG_REG3__SI; -typedef union VGT_DEBUG_REG40__SI regVGT_DEBUG_REG40__SI; -typedef union VGT_DEBUG_REG41__SI regVGT_DEBUG_REG41__SI; -typedef union VGT_DEBUG_REG42__SI regVGT_DEBUG_REG42__SI; -typedef union VGT_DEBUG_REG4__CI__VI regVGT_DEBUG_REG4__CI__VI; -typedef union VGT_DEBUG_REG4__SI regVGT_DEBUG_REG4__SI; -typedef union VGT_DEBUG_REG5__CI__VI regVGT_DEBUG_REG5__CI__VI; -typedef union VGT_DEBUG_REG5__SI regVGT_DEBUG_REG5__SI; -typedef union VGT_DEBUG_REG6__CI__VI regVGT_DEBUG_REG6__CI__VI; -typedef union VGT_DEBUG_REG6__SI regVGT_DEBUG_REG6__SI; -typedef union VGT_DEBUG_REG7__CI__VI regVGT_DEBUG_REG7__CI__VI; -typedef union VGT_DEBUG_REG7__SI regVGT_DEBUG_REG7__SI; -typedef union VGT_DEBUG_REG8__CI__VI regVGT_DEBUG_REG8__CI__VI; -typedef union VGT_DEBUG_REG8__SI regVGT_DEBUG_REG8__SI; -typedef union VGT_DEBUG_REG9 regVGT_DEBUG_REG9; -typedef union VGT_DMA_BASE regVGT_DMA_BASE; -typedef union VGT_DMA_BASE_HI regVGT_DMA_BASE_HI; -typedef union VGT_DMA_CONTROL__CI__VI regVGT_DMA_CONTROL__CI__VI; -typedef union VGT_DMA_DATA_FIFO_DEPTH regVGT_DMA_DATA_FIFO_DEPTH; -typedef union VGT_DMA_INDEX_TYPE__SI__CI regVGT_DMA_INDEX_TYPE__SI__CI; -typedef union VGT_DMA_INDEX_TYPE__VI regVGT_DMA_INDEX_TYPE__VI; -typedef union VGT_DMA_LS_HS_CONFIG__CI__VI regVGT_DMA_LS_HS_CONFIG__CI__VI; -typedef union VGT_DMA_MAX_SIZE regVGT_DMA_MAX_SIZE; -typedef union VGT_DMA_NUM_INSTANCES regVGT_DMA_NUM_INSTANCES; -typedef union VGT_DMA_PRIMITIVE_TYPE__CI__VI regVGT_DMA_PRIMITIVE_TYPE__CI__VI; -typedef union VGT_DMA_REQ_FIFO_DEPTH regVGT_DMA_REQ_FIFO_DEPTH; -typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; -typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; -typedef union VGT_DRAW_INIT_FIFO_DEPTH regVGT_DRAW_INIT_FIFO_DEPTH; -typedef union VGT_ENHANCE regVGT_ENHANCE; -typedef union VGT_ESGS_RING_ITEMSIZE regVGT_ESGS_RING_ITEMSIZE; -typedef union VGT_ESGS_RING_SIZE regVGT_ESGS_RING_SIZE; -typedef union VGT_ES_PER_GS regVGT_ES_PER_GS; -typedef union VGT_EVENT_ADDRESS_REG regVGT_EVENT_ADDRESS_REG; -typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; -typedef union VGT_FIFO_DEPTHS regVGT_FIFO_DEPTHS; -typedef union VGT_GROUP_DECR regVGT_GROUP_DECR; -typedef union VGT_GROUP_FIRST_DECR regVGT_GROUP_FIRST_DECR; -typedef union VGT_GROUP_PRIM_TYPE regVGT_GROUP_PRIM_TYPE; -typedef union VGT_GROUP_VECT_0_CNTL regVGT_GROUP_VECT_0_CNTL; -typedef union VGT_GROUP_VECT_0_FMT_CNTL regVGT_GROUP_VECT_0_FMT_CNTL; -typedef union VGT_GROUP_VECT_1_CNTL regVGT_GROUP_VECT_1_CNTL; -typedef union VGT_GROUP_VECT_1_FMT_CNTL regVGT_GROUP_VECT_1_FMT_CNTL; -typedef union VGT_GSVS_RING_ITEMSIZE regVGT_GSVS_RING_ITEMSIZE; -typedef union VGT_GSVS_RING_OFFSET_1 regVGT_GSVS_RING_OFFSET_1; -typedef union VGT_GSVS_RING_OFFSET_2 regVGT_GSVS_RING_OFFSET_2; -typedef union VGT_GSVS_RING_OFFSET_3 regVGT_GSVS_RING_OFFSET_3; -typedef union VGT_GSVS_RING_SIZE regVGT_GSVS_RING_SIZE; -typedef union VGT_GS_INSTANCE_CNT regVGT_GS_INSTANCE_CNT; -typedef union VGT_GS_MAX_VERT_OUT regVGT_GS_MAX_VERT_OUT; -typedef union VGT_GS_MODE regVGT_GS_MODE; -typedef union VGT_GS_ONCHIP_CNTL__CI__VI regVGT_GS_ONCHIP_CNTL__CI__VI; -typedef union VGT_GS_OUT_PRIM_TYPE regVGT_GS_OUT_PRIM_TYPE; -typedef union VGT_GS_PER_ES regVGT_GS_PER_ES; -typedef union VGT_GS_PER_VS regVGT_GS_PER_VS; -typedef union VGT_GS_VERTEX_REUSE regVGT_GS_VERTEX_REUSE; -typedef union VGT_GS_VERT_ITEMSIZE regVGT_GS_VERT_ITEMSIZE; -typedef union VGT_GS_VERT_ITEMSIZE_1 regVGT_GS_VERT_ITEMSIZE_1; -typedef union VGT_GS_VERT_ITEMSIZE_2 regVGT_GS_VERT_ITEMSIZE_2; -typedef union VGT_GS_VERT_ITEMSIZE_3 regVGT_GS_VERT_ITEMSIZE_3; -typedef union VGT_HOS_CNTL regVGT_HOS_CNTL; -typedef union VGT_HOS_MAX_TESS_LEVEL regVGT_HOS_MAX_TESS_LEVEL; -typedef union VGT_HOS_MIN_TESS_LEVEL regVGT_HOS_MIN_TESS_LEVEL; -typedef union VGT_HOS_REUSE_DEPTH regVGT_HOS_REUSE_DEPTH; -typedef union VGT_HS_OFFCHIP_PARAM regVGT_HS_OFFCHIP_PARAM; -typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; -typedef union VGT_INDEX_TYPE regVGT_INDEX_TYPE; -typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; -typedef union VGT_INSTANCE_STEP_RATE_0 regVGT_INSTANCE_STEP_RATE_0; -typedef union VGT_INSTANCE_STEP_RATE_1 regVGT_INSTANCE_STEP_RATE_1; -typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; -typedef union VGT_LS_HS_CONFIG regVGT_LS_HS_CONFIG; -typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; -typedef union VGT_MC_LAT_CNTL regVGT_MC_LAT_CNTL; -typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; -typedef union VGT_MULTI_PRIM_IB_RESET_EN regVGT_MULTI_PRIM_IB_RESET_EN; -typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; -typedef union VGT_NUM_INDICES regVGT_NUM_INDICES; -typedef union VGT_NUM_INSTANCES regVGT_NUM_INSTANCES; -typedef union VGT_OUTPUT_PATH_CNTL regVGT_OUTPUT_PATH_CNTL; -typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; -typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; -typedef union VGT_PERFCOUNTER0_LO regVGT_PERFCOUNTER0_LO; -typedef union VGT_PERFCOUNTER0_SELECT1__CI__VI regVGT_PERFCOUNTER0_SELECT1__CI__VI; -typedef union VGT_PERFCOUNTER0_SELECT__CI__VI regVGT_PERFCOUNTER0_SELECT__CI__VI; -typedef union VGT_PERFCOUNTER0_SELECT__SI regVGT_PERFCOUNTER0_SELECT__SI; -typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; -typedef union VGT_PERFCOUNTER1_LO regVGT_PERFCOUNTER1_LO; -typedef union VGT_PERFCOUNTER1_SELECT1__CI__VI regVGT_PERFCOUNTER1_SELECT1__CI__VI; -typedef union VGT_PERFCOUNTER1_SELECT__CI__VI regVGT_PERFCOUNTER1_SELECT__CI__VI; -typedef union VGT_PERFCOUNTER1_SELECT__SI regVGT_PERFCOUNTER1_SELECT__SI; -typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; -typedef union VGT_PERFCOUNTER2_LO regVGT_PERFCOUNTER2_LO; -typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; -typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; -typedef union VGT_PERFCOUNTER3_LO regVGT_PERFCOUNTER3_LO; -typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; -typedef union VGT_PERFCOUNTER_SEID_MASK regVGT_PERFCOUNTER_SEID_MASK; -typedef union VGT_PRIMITIVEID_EN regVGT_PRIMITIVEID_EN; -typedef union VGT_PRIMITIVEID_RESET regVGT_PRIMITIVEID_RESET; -typedef union VGT_PRIMITIVE_TYPE regVGT_PRIMITIVE_TYPE; -typedef union VGT_RESET_DEBUG__CI__VI regVGT_RESET_DEBUG__CI__VI; -typedef union VGT_REUSE_OFF regVGT_REUSE_OFF; -typedef union VGT_SHADER_STAGES_EN regVGT_SHADER_STAGES_EN; -typedef union VGT_STRMOUT_BUFFER_CONFIG regVGT_STRMOUT_BUFFER_CONFIG; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_0 regVGT_STRMOUT_BUFFER_FILLED_SIZE_0; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_1 regVGT_STRMOUT_BUFFER_FILLED_SIZE_1; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_2 regVGT_STRMOUT_BUFFER_FILLED_SIZE_2; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_3 regVGT_STRMOUT_BUFFER_FILLED_SIZE_3; -typedef union VGT_STRMOUT_BUFFER_OFFSET_0 regVGT_STRMOUT_BUFFER_OFFSET_0; -typedef union VGT_STRMOUT_BUFFER_OFFSET_1 regVGT_STRMOUT_BUFFER_OFFSET_1; -typedef union VGT_STRMOUT_BUFFER_OFFSET_2 regVGT_STRMOUT_BUFFER_OFFSET_2; -typedef union VGT_STRMOUT_BUFFER_OFFSET_3 regVGT_STRMOUT_BUFFER_OFFSET_3; -typedef union VGT_STRMOUT_BUFFER_SIZE_0 regVGT_STRMOUT_BUFFER_SIZE_0; -typedef union VGT_STRMOUT_BUFFER_SIZE_1 regVGT_STRMOUT_BUFFER_SIZE_1; -typedef union VGT_STRMOUT_BUFFER_SIZE_2 regVGT_STRMOUT_BUFFER_SIZE_2; -typedef union VGT_STRMOUT_BUFFER_SIZE_3 regVGT_STRMOUT_BUFFER_SIZE_3; -typedef union VGT_STRMOUT_CONFIG regVGT_STRMOUT_CONFIG; -typedef union VGT_STRMOUT_DELAY__CI__VI regVGT_STRMOUT_DELAY__CI__VI; -typedef union VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE - regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE; -typedef union VGT_STRMOUT_DRAW_OPAQUE_OFFSET regVGT_STRMOUT_DRAW_OPAQUE_OFFSET; -typedef union VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE; -typedef union VGT_STRMOUT_VTX_STRIDE_0 regVGT_STRMOUT_VTX_STRIDE_0; -typedef union VGT_STRMOUT_VTX_STRIDE_1 regVGT_STRMOUT_VTX_STRIDE_1; -typedef union VGT_STRMOUT_VTX_STRIDE_2 regVGT_STRMOUT_VTX_STRIDE_2; -typedef union VGT_STRMOUT_VTX_STRIDE_3 regVGT_STRMOUT_VTX_STRIDE_3; -typedef union VGT_SYS_CONFIG regVGT_SYS_CONFIG; -typedef union VGT_TF_MEMORY_BASE regVGT_TF_MEMORY_BASE; -typedef union VGT_TF_PARAM regVGT_TF_PARAM; -typedef union VGT_TF_RING_SIZE regVGT_TF_RING_SIZE; -typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; -typedef union VGT_VS_MAX_WAVE_ID__CI__VI regVGT_VS_MAX_WAVE_ID__CI__VI; -typedef union VGT_VTX_CNT_EN regVGT_VTX_CNT_EN; -typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; -typedef union VID_BUFFER_CONTROL__SI regVID_BUFFER_CONTROL__SI; -typedef union VIEWPORT_SIZE__SI regVIEWPORT_SIZE__SI; -typedef union VIEWPORT_START__SI regVIEWPORT_START__SI; -typedef union VIPH_CH0_ABCNT__SI regVIPH_CH0_ABCNT__SI; -typedef union VIPH_CH0_ADDR__SI regVIPH_CH0_ADDR__SI; -typedef union VIPH_CH0_DATA__SI regVIPH_CH0_DATA__SI; -typedef union VIPH_CH0_SBCNT__SI regVIPH_CH0_SBCNT__SI; -typedef union VIPH_CH1_ABCNT__SI regVIPH_CH1_ABCNT__SI; -typedef union VIPH_CH1_ADDR__SI regVIPH_CH1_ADDR__SI; -typedef union VIPH_CH1_DATA__SI regVIPH_CH1_DATA__SI; -typedef union VIPH_CH1_SBCNT__SI regVIPH_CH1_SBCNT__SI; -typedef union VIPH_CH2_ABCNT__SI regVIPH_CH2_ABCNT__SI; -typedef union VIPH_CH2_ADDR__SI regVIPH_CH2_ADDR__SI; -typedef union VIPH_CH2_DATA__SI regVIPH_CH2_DATA__SI; -typedef union VIPH_CH2_SBCNT__SI regVIPH_CH2_SBCNT__SI; -typedef union VIPH_CH3_ABCNT__SI regVIPH_CH3_ABCNT__SI; -typedef union VIPH_CH3_ADDR__SI regVIPH_CH3_ADDR__SI; -typedef union VIPH_CH3_DATA__SI regVIPH_CH3_DATA__SI; -typedef union VIPH_CH3_SBCNT__SI regVIPH_CH3_SBCNT__SI; -typedef union VIPH_CONTROL__SI regVIPH_CONTROL__SI; -typedef union VIPH_DMA_CHUNK__SI regVIPH_DMA_CHUNK__SI; -typedef union VIPH_DV_INT__SI regVIPH_DV_INT__SI; -typedef union VIPH_DV_LAT__SI regVIPH_DV_LAT__SI; -typedef union VIPH_READ_URG__SI regVIPH_READ_URG__SI; -typedef union VIPH_REG_ADDR__SI regVIPH_REG_ADDR__SI; -typedef union VIPH_REG_DATA__SI regVIPH_REG_DATA__SI; -typedef union VIPH_TIMEOUT_STAT__SI regVIPH_TIMEOUT_STAT__SI; -typedef union VIPH_WRCOMB_STALL__SI regVIPH_WRCOMB_STALL__SI; -typedef union VIPH_WRCOMB_STAT0__SI regVIPH_WRCOMB_STAT0__SI; -typedef union VIPH_WRCOMB_STAT1__SI regVIPH_WRCOMB_STAT1__SI; -typedef union VIPPAD_A__SI regVIPPAD_A__SI; -typedef union VIPPAD_EN__SI regVIPPAD_EN__SI; -typedef union VIPPAD_MASK__SI regVIPPAD_MASK__SI; -typedef union VIPPAD_PD_DIS__SI regVIPPAD_PD_DIS__SI; -typedef union VIPPAD_RECV__SI regVIPPAD_RECV__SI; -typedef union VIPPAD_STRENGTH__SI regVIPPAD_STRENGTH__SI; -typedef union VIPPAD_Y__SI regVIPPAD_Y__SI; -typedef union VIP_DCCIF_CNTL__SI regVIP_DCCIF_CNTL__SI; -typedef union VIP_HW_DEBUG__SI regVIP_HW_DEBUG__SI; -typedef union VIP_INT__SI regVIP_INT__SI; -typedef union VIP_MCIF_CNTL__SI regVIP_MCIF_CNTL__SI; -typedef union VLINE_START_END__SI regVLINE_START_END__SI; -typedef union VLINE_STATUS__SI regVLINE_STATUS__SI; -typedef union VM_CONTEXT0_CNTL__SI__CI regVM_CONTEXT0_CNTL__SI__CI; -typedef union VM_CONTEXT0_CNTL__VI regVM_CONTEXT0_CNTL__VI; -typedef union VM_CONTEXT0_CNTL2 regVM_CONTEXT0_CNTL2; -typedef union VM_CONTEXT0_PAGE_TABLE_BASE_ADDR regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT0_PAGE_TABLE_END_ADDR regVM_CONTEXT0_PAGE_TABLE_END_ADDR; -typedef union VM_CONTEXT0_PAGE_TABLE_START_ADDR regVM_CONTEXT0_PAGE_TABLE_START_ADDR; -typedef union VM_CONTEXT0_PROTECTION_FAULT_ADDR regVM_CONTEXT0_PROTECTION_FAULT_ADDR; -typedef union VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR - regVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR; -typedef union VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI - regVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI; -typedef union VM_CONTEXT0_PROTECTION_FAULT_STATUS regVM_CONTEXT0_PROTECTION_FAULT_STATUS; -typedef union VM_CONTEXT10_PAGE_TABLE_BASE_ADDR regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT11_PAGE_TABLE_BASE_ADDR regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT12_PAGE_TABLE_BASE_ADDR regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT13_PAGE_TABLE_BASE_ADDR regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT14_PAGE_TABLE_BASE_ADDR regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT15_PAGE_TABLE_BASE_ADDR regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT1_CNTL__SI__CI regVM_CONTEXT1_CNTL__SI__CI; -typedef union VM_CONTEXT1_CNTL__VI regVM_CONTEXT1_CNTL__VI; -typedef union VM_CONTEXT1_CNTL2 regVM_CONTEXT1_CNTL2; -typedef union VM_CONTEXT1_PAGE_TABLE_BASE_ADDR regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT1_PAGE_TABLE_END_ADDR regVM_CONTEXT1_PAGE_TABLE_END_ADDR; -typedef union VM_CONTEXT1_PAGE_TABLE_START_ADDR regVM_CONTEXT1_PAGE_TABLE_START_ADDR; -typedef union VM_CONTEXT1_PROTECTION_FAULT_ADDR regVM_CONTEXT1_PROTECTION_FAULT_ADDR; -typedef union VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR - regVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR; -typedef union VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI - regVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI; -typedef union VM_CONTEXT1_PROTECTION_FAULT_STATUS regVM_CONTEXT1_PROTECTION_FAULT_STATUS; -typedef union VM_CONTEXT2_PAGE_TABLE_BASE_ADDR regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT3_PAGE_TABLE_BASE_ADDR regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT4_PAGE_TABLE_BASE_ADDR regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT5_PAGE_TABLE_BASE_ADDR regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT6_PAGE_TABLE_BASE_ADDR regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT7_PAGE_TABLE_BASE_ADDR regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT8_PAGE_TABLE_BASE_ADDR regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXT9_PAGE_TABLE_BASE_ADDR regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR; -typedef union VM_CONTEXTS_DISABLE regVM_CONTEXTS_DISABLE; -typedef union VM_DEBUG regVM_DEBUG; -typedef union VM_DUMMY_PAGE_FAULT_ADDR regVM_DUMMY_PAGE_FAULT_ADDR; -typedef union VM_DUMMY_PAGE_FAULT_CNTL regVM_DUMMY_PAGE_FAULT_CNTL; -typedef union VM_FAULT_CLIENT_ID regVM_FAULT_CLIENT_ID; -typedef union VM_INVALIDATE_REQUEST regVM_INVALIDATE_REQUEST; -typedef union VM_INVALIDATE_RESPONSE regVM_INVALIDATE_RESPONSE; -typedef union VM_L2_BANK_SELECT_MASKA regVM_L2_BANK_SELECT_MASKA; -typedef union VM_L2_BANK_SELECT_MASKB regVM_L2_BANK_SELECT_MASKB; -typedef union VM_L2_CG regVM_L2_CG; -typedef union VM_L2_CNTL2 regVM_L2_CNTL2; -typedef union VM_L2_CNTL3 regVM_L2_CNTL3; -typedef union VM_L2_CNTL__CI__VI regVM_L2_CNTL__CI__VI; -typedef union VM_L2_CNTL__SI regVM_L2_CNTL__SI; -typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR - regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR; -typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR - regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR; -typedef union VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET; -typedef union VM_L2_PERF_COUNTER_CNTL__SI regVM_L2_PERF_COUNTER_CNTL__SI; -typedef union VM_L2_PERF_COUNTER_STATUS__SI regVM_L2_PERF_COUNTER_STATUS__SI; -typedef union VM_L2_STATUS regVM_L2_STATUS; -typedef union VM_PRT_APERTURE0_HIGH_ADDR regVM_PRT_APERTURE0_HIGH_ADDR; -typedef union VM_PRT_APERTURE0_LOW_ADDR regVM_PRT_APERTURE0_LOW_ADDR; -typedef union VM_PRT_APERTURE1_HIGH_ADDR regVM_PRT_APERTURE1_HIGH_ADDR; -typedef union VM_PRT_APERTURE1_LOW_ADDR regVM_PRT_APERTURE1_LOW_ADDR; -typedef union VM_PRT_APERTURE2_HIGH_ADDR regVM_PRT_APERTURE2_HIGH_ADDR; -typedef union VM_PRT_APERTURE2_LOW_ADDR regVM_PRT_APERTURE2_LOW_ADDR; -typedef union VM_PRT_APERTURE3_HIGH_ADDR regVM_PRT_APERTURE3_HIGH_ADDR; -typedef union VM_PRT_APERTURE3_LOW_ADDR regVM_PRT_APERTURE3_LOW_ADDR; -typedef union VM_PRT_CNTL__CI__VI regVM_PRT_CNTL__CI__VI; -typedef union VM_PRT_CNTL__SI regVM_PRT_CNTL__SI; -typedef union VM_SECURE_FAULT_CNTL regVM_SECURE_FAULT_CNTL; -typedef union V_COUNTER__SI regV_COUNTER__SI; -typedef union WAIT_UNTIL_POLL_CNTL__SI regWAIT_UNTIL_POLL_CNTL__SI; -typedef union WAIT_UNTIL_POLL_MASK__SI regWAIT_UNTIL_POLL_MASK__SI; -typedef union WAIT_UNTIL_POLL_REFDATA__SI regWAIT_UNTIL_POLL_REFDATA__SI; -typedef union WAIT_UNTIL__SI regWAIT_UNTIL__SI; -typedef union WAKE_ENABLE__SI regWAKE_ENABLE__SI; -typedef union WALL_CLOCK_COUNTER_ALIAS__SI regWALL_CLOCK_COUNTER_ALIAS__SI; -typedef union WALL_CLOCK_COUNTER__SI regWALL_CLOCK_COUNTER__SI; -typedef union WD_CNTL_STATUS__CI__VI regWD_CNTL_STATUS__CI__VI; -typedef union WD_DEBUG_CNTL__CI__VI regWD_DEBUG_CNTL__CI__VI; -typedef union WD_DEBUG_DATA__CI__VI regWD_DEBUG_DATA__CI__VI; -typedef union WD_DEBUG_REG0__CI__VI regWD_DEBUG_REG0__CI__VI; -typedef union WD_DEBUG_REG1__CI__VI regWD_DEBUG_REG1__CI__VI; -typedef union WD_DEBUG_REG2__CI__VI regWD_DEBUG_REG2__CI__VI; -typedef union WD_DEBUG_REG3__CI__VI regWD_DEBUG_REG3__CI__VI; -typedef union WD_DEBUG_REG4__CI__VI regWD_DEBUG_REG4__CI__VI; -typedef union WD_DEBUG_REG5__CI__VI regWD_DEBUG_REG5__CI__VI; -typedef union WD_ENHANCE__CI__VI regWD_ENHANCE__CI__VI; -typedef union WD_PERFCOUNTER0_HI__CI__VI regWD_PERFCOUNTER0_HI__CI__VI; -typedef union WD_PERFCOUNTER0_LO__CI__VI regWD_PERFCOUNTER0_LO__CI__VI; -typedef union WD_PERFCOUNTER0_SELECT__CI__VI regWD_PERFCOUNTER0_SELECT__CI__VI; -typedef union WD_PERFCOUNTER1_HI__CI__VI regWD_PERFCOUNTER1_HI__CI__VI; -typedef union WD_PERFCOUNTER1_LO__CI__VI regWD_PERFCOUNTER1_LO__CI__VI; -typedef union WD_PERFCOUNTER1_SELECT__CI__VI regWD_PERFCOUNTER1_SELECT__CI__VI; -typedef union WD_PERFCOUNTER2_HI__CI__VI regWD_PERFCOUNTER2_HI__CI__VI; -typedef union WD_PERFCOUNTER2_LO__CI__VI regWD_PERFCOUNTER2_LO__CI__VI; -typedef union WD_PERFCOUNTER2_SELECT__CI__VI regWD_PERFCOUNTER2_SELECT__CI__VI; -typedef union WD_PERFCOUNTER3_HI__CI__VI regWD_PERFCOUNTER3_HI__CI__VI; -typedef union WD_PERFCOUNTER3_LO__CI__VI regWD_PERFCOUNTER3_LO__CI__VI; -typedef union WD_PERFCOUNTER3_SELECT__CI__VI regWD_PERFCOUNTER3_SELECT__CI__VI; -typedef union ATC_ATS_FAULT_STATUS_INFO2__VI regATC_ATS_FAULT_STATUS_INFO2__VI; -typedef union ATC_ATS_VMID_STATUS__VI regATC_ATS_VMID_STATUS__VI; -typedef union ATC_L1RD_DEBUG2_TLB__VI regATC_L1RD_DEBUG2_TLB__VI; -typedef union ATC_L1WR_DEBUG2_TLB__VI regATC_L1WR_DEBUG2_TLB__VI; -typedef union ATC_L2_CACHE_DATA0__VI regATC_L2_CACHE_DATA0__VI; -typedef union ATC_L2_CACHE_DATA1__VI regATC_L2_CACHE_DATA1__VI; -typedef union ATC_L2_CACHE_DATA2__VI regATC_L2_CACHE_DATA2__VI; -typedef union ATC_L2_CNTL3__VI regATC_L2_CNTL3__VI; -typedef union ATC_L2_STATUS__VI regATC_L2_STATUS__VI; -typedef union ATC_L2_STATUS2__VI regATC_L2_STATUS2__VI; -typedef union BF_ANA_ISO_CNTL__VI regBF_ANA_ISO_CNTL__VI; -typedef union BIF_ATOMIC_ERR_LOG__VI regBIF_ATOMIC_ERR_LOG__VI; -typedef union BIF_BME_STATUS__VI regBIF_BME_STATUS__VI; -typedef union BIF_CLK_CTRL__VI regBIF_CLK_CTRL__VI; -typedef union BIF_DOORBELL_APER_EN__VI regBIF_DOORBELL_APER_EN__VI; -typedef union BIF_DOORBELL_GBLAPER1_LOWER__VI regBIF_DOORBELL_GBLAPER1_LOWER__VI; -typedef union BIF_DOORBELL_GBLAPER1_UPPER__VI regBIF_DOORBELL_GBLAPER1_UPPER__VI; -typedef union BIF_DOORBELL_GBLAPER2_LOWER__VI regBIF_DOORBELL_GBLAPER2_LOWER__VI; -typedef union BIF_DOORBELL_GBLAPER2_UPPER__VI regBIF_DOORBELL_GBLAPER2_UPPER__VI; -typedef union BIF_GPUIOV_RESET_NOTIFICATION__VI regBIF_GPUIOV_RESET_NOTIFICATION__VI; -typedef union BIF_GPUIOV_VM_INIT_STATUS__VI regBIF_GPUIOV_VM_INIT_STATUS__VI; -typedef union BIF_MM_INDACCESS_CNTL__VI regBIF_MM_INDACCESS_CNTL__VI; -typedef union BIF_RB_BASE__VI regBIF_RB_BASE__VI; -typedef union BIF_RB_CNTL__VI regBIF_RB_CNTL__VI; -typedef union BIF_RB_RPTR__VI regBIF_RB_RPTR__VI; -typedef union BIF_RB_WPTR__VI regBIF_RB_WPTR__VI; -typedef union BIF_RB_WPTR_ADDR_HI__VI regBIF_RB_WPTR_ADDR_HI__VI; -typedef union BIF_RB_WPTR_ADDR_LO__VI regBIF_RB_WPTR_ADDR_LO__VI; -typedef union BIF_RFE_MST_SMBUS_CMDSTATUS__VI regBIF_RFE_MST_SMBUS_CMDSTATUS__VI; -typedef union BIF_RFE_WARMRST_CNTL__VI regBIF_RFE_WARMRST_CNTL__VI; -typedef union BIF_RLC_INTR_CNTL__VI regBIF_RLC_INTR_CNTL__VI; -typedef union BIF_SMU_DATA__VI regBIF_SMU_DATA__VI; -typedef union BIF_SMU_INDEX__VI regBIF_SMU_INDEX__VI; -typedef union BIF_VDDGFX_FB_CMP__VI regBIF_VDDGFX_FB_CMP__VI; -typedef union BIF_VDDGFX_GFX0_LOWER__VI regBIF_VDDGFX_GFX0_LOWER__VI; -typedef union BIF_VDDGFX_GFX0_UPPER__VI regBIF_VDDGFX_GFX0_UPPER__VI; -typedef union BIF_VDDGFX_GFX1_LOWER__VI regBIF_VDDGFX_GFX1_LOWER__VI; -typedef union BIF_VDDGFX_GFX1_UPPER__VI regBIF_VDDGFX_GFX1_UPPER__VI; -typedef union BIF_VDDGFX_GFX2_LOWER__VI regBIF_VDDGFX_GFX2_LOWER__VI; -typedef union BIF_VDDGFX_GFX2_UPPER__VI regBIF_VDDGFX_GFX2_UPPER__VI; -typedef union BIF_VDDGFX_GFX3_LOWER__VI regBIF_VDDGFX_GFX3_LOWER__VI; -typedef union BIF_VDDGFX_GFX3_UPPER__VI regBIF_VDDGFX_GFX3_UPPER__VI; -typedef union BIF_VDDGFX_GFX4_LOWER__VI regBIF_VDDGFX_GFX4_LOWER__VI; -typedef union BIF_VDDGFX_GFX4_UPPER__VI regBIF_VDDGFX_GFX4_UPPER__VI; -typedef union BIF_VDDGFX_GFX5_LOWER__VI regBIF_VDDGFX_GFX5_LOWER__VI; -typedef union BIF_VDDGFX_GFX5_UPPER__VI regBIF_VDDGFX_GFX5_UPPER__VI; -typedef union BIF_VDDGFX_RSV1_LOWER__VI regBIF_VDDGFX_RSV1_LOWER__VI; -typedef union BIF_VDDGFX_RSV1_UPPER__VI regBIF_VDDGFX_RSV1_UPPER__VI; -typedef union BIF_VDDGFX_RSV2_LOWER__VI regBIF_VDDGFX_RSV2_LOWER__VI; -typedef union BIF_VDDGFX_RSV2_UPPER__VI regBIF_VDDGFX_RSV2_UPPER__VI; -typedef union BIF_VDDGFX_RSV3_LOWER__VI regBIF_VDDGFX_RSV3_LOWER__VI; -typedef union BIF_VDDGFX_RSV3_UPPER__VI regBIF_VDDGFX_RSV3_UPPER__VI; -typedef union BIF_VDDGFX_RSV4_LOWER__VI regBIF_VDDGFX_RSV4_LOWER__VI; -typedef union BIF_VDDGFX_RSV4_UPPER__VI regBIF_VDDGFX_RSV4_UPPER__VI; -typedef union BIF_VIRT_RESET_REQ__VI regBIF_VIRT_RESET_REQ__VI; -typedef union BX_RESET_CNTL__VI regBX_RESET_CNTL__VI; -typedef union CB_COLOR0_DCC_BASE__VI regCB_COLOR0_DCC_BASE__VI; -typedef union CB_COLOR0_DCC_CONTROL__VI regCB_COLOR0_DCC_CONTROL__VI; -typedef union CB_COLOR1_DCC_BASE__VI regCB_COLOR1_DCC_BASE__VI; -typedef union CB_COLOR1_DCC_CONTROL__VI regCB_COLOR1_DCC_CONTROL__VI; -typedef union CB_COLOR2_DCC_BASE__VI regCB_COLOR2_DCC_BASE__VI; -typedef union CB_COLOR2_DCC_CONTROL__VI regCB_COLOR2_DCC_CONTROL__VI; -typedef union CB_COLOR3_DCC_BASE__VI regCB_COLOR3_DCC_BASE__VI; -typedef union CB_COLOR3_DCC_CONTROL__VI regCB_COLOR3_DCC_CONTROL__VI; -typedef union CB_COLOR4_DCC_BASE__VI regCB_COLOR4_DCC_BASE__VI; -typedef union CB_COLOR4_DCC_CONTROL__VI regCB_COLOR4_DCC_CONTROL__VI; -typedef union CB_COLOR5_DCC_BASE__VI regCB_COLOR5_DCC_BASE__VI; -typedef union CB_COLOR5_DCC_CONTROL__VI regCB_COLOR5_DCC_CONTROL__VI; -typedef union CB_COLOR6_DCC_BASE__VI regCB_COLOR6_DCC_BASE__VI; -typedef union CB_COLOR6_DCC_CONTROL__VI regCB_COLOR6_DCC_CONTROL__VI; -typedef union CB_COLOR7_DCC_BASE__VI regCB_COLOR7_DCC_BASE__VI; -typedef union CB_COLOR7_DCC_CONTROL__VI regCB_COLOR7_DCC_CONTROL__VI; -typedef union CB_DCC_CONFIG__VI regCB_DCC_CONFIG__VI; -typedef union CB_DCC_CONTROL__VI regCB_DCC_CONTROL__VI; -typedef union CB_DEBUG_BUS_19__VI regCB_DEBUG_BUS_19__VI; -typedef union CB_DEBUG_BUS_20__VI regCB_DEBUG_BUS_20__VI; -typedef union CB_DEBUG_BUS_21__VI regCB_DEBUG_BUS_21__VI; -typedef union CB_DEBUG_BUS_22__VI regCB_DEBUG_BUS_22__VI; -typedef union CC_BIF_BX_PINSTRAP1__VI regCC_BIF_BX_PINSTRAP1__VI; -typedef union CC_BIF_BX_PINSTRAP2__VI regCC_BIF_BX_PINSTRAP2__VI; -typedef union CC_BIF_BX_STRAP2__VI regCC_BIF_BX_STRAP2__VI; -typedef union CC_BIF_HARDCODE_STRAPS0__VI regCC_BIF_HARDCODE_STRAPS0__VI; -typedef union CC_BIF_HARDCODE_STRAPS1__VI regCC_BIF_HARDCODE_STRAPS1__VI; -typedef union CC_BIF_HARDCODE_STRAPS2__VI regCC_BIF_HARDCODE_STRAPS2__VI; -typedef union CC_BIF_HARDCODE_STRAPS3__VI regCC_BIF_HARDCODE_STRAPS3__VI; -typedef union CC_BIF_HARDCODE_STRAPS4__VI regCC_BIF_HARDCODE_STRAPS4__VI; -typedef union CC_BIF_HARDCODE_STRAPS5_PORT_A__VI regCC_BIF_HARDCODE_STRAPS5_PORT_A__VI; -typedef union CC_BIF_SMB_PINSTRAP0__VI regCC_BIF_SMB_PINSTRAP0__VI; -typedef union CC_BIF_SMB_STRAP0__VI regCC_BIF_SMB_STRAP0__VI; -typedef union CC_BIF_SMB_STRAP1__VI regCC_BIF_SMB_STRAP1__VI; -typedef union CC_BIF_SMB_STRAP2__VI regCC_BIF_SMB_STRAP2__VI; -typedef union CC_BIF_SMB_STRAP3__VI regCC_BIF_SMB_STRAP3__VI; -typedef union CC_BIF_SMB_STRAP4__VI regCC_BIF_SMB_STRAP4__VI; -typedef union CC_BIF_STRAP10_A__VI regCC_BIF_STRAP10_A__VI; -typedef union CC_BIF_STRAP11_A__VI regCC_BIF_STRAP11_A__VI; -typedef union CC_BIF_STRAP9_A__VI regCC_BIF_STRAP9_A__VI; -typedef union CC_FCTRL_FUSES__VI regCC_FCTRL_FUSES__VI; -typedef union CC_GC_SHADER_RATE_CONFIG__VI regCC_GC_SHADER_RATE_CONFIG__VI; -typedef union CC_HARVEST_FUSES__VI regCC_HARVEST_FUSES__VI; -typedef union CFG_LNC_WINDOW__VI regCFG_LNC_WINDOW__VI; -typedef union CG_ACLK_DIV_CNTL__VI regCG_ACLK_DIV_CNTL__VI; -typedef union CG_ACLK_DIV_PSPCLK_OVERCLOCKING_ATTEMPTS__VI - regCG_ACLK_DIV_PSPCLK_OVERCLOCKING_ATTEMPTS__VI; -typedef union CG_ACLK_DIV_STATUS__VI regCG_ACLK_DIV_STATUS__VI; -typedef union CG_CLK_DIVIDER_STATUS_2__VI regCG_CLK_DIVIDER_STATUS_2__VI; -typedef union CG_PSPCLK_CNTL__VI regCG_PSPCLK_CNTL__VI; -typedef union CG_PSPCLK_STATUS__VI regCG_PSPCLK_STATUS__VI; -typedef union CG_SPLL_FUNC_CNTL_7__VI regCG_SPLL_FUNC_CNTL_7__VI; -typedef union CLKREQB_PERF_COUNTER__VI regCLKREQB_PERF_COUNTER__VI; -typedef union COMPUTE_DISPATCH_ID__VI regCOMPUTE_DISPATCH_ID__VI; -typedef union COMPUTE_NOWHERE__VI regCOMPUTE_NOWHERE__VI; -typedef union COMPUTE_RELAUNCH__VI regCOMPUTE_RELAUNCH__VI; -typedef union COMPUTE_THREADGROUP_ID__VI regCOMPUTE_THREADGROUP_ID__VI; -typedef union COMPUTE_WAVE_RESTORE_ADDR_HI__VI regCOMPUTE_WAVE_RESTORE_ADDR_HI__VI; -typedef union COMPUTE_WAVE_RESTORE_ADDR_LO__VI regCOMPUTE_WAVE_RESTORE_ADDR_LO__VI; -typedef union COMPUTE_WAVE_RESTORE_CONTROL__VI regCOMPUTE_WAVE_RESTORE_CONTROL__VI; -typedef union CPM_CONTROL__VI regCPM_CONTROL__VI; -typedef union CP_ATCL1_CNTL__VI regCP_ATCL1_CNTL__VI; -typedef union CP_CE_COMPLETION_STATUS__VI regCP_CE_COMPLETION_STATUS__VI; -typedef union CP_CE_METADATA_BASE_ADDR__VI regCP_CE_METADATA_BASE_ADDR__VI; -typedef union CP_CE_METADATA_BASE_ADDR_HI__VI regCP_CE_METADATA_BASE_ADDR_HI__VI; -typedef union CP_CE_RB_OFFSET__VI regCP_CE_RB_OFFSET__VI; -typedef union CP_CPC_IC_BASE_CNTL__VI regCP_CPC_IC_BASE_CNTL__VI; -typedef union CP_CPC_IC_BASE_HI__VI regCP_CPC_IC_BASE_HI__VI; -typedef union CP_CPC_IC_BASE_LO__VI regCP_CPC_IC_BASE_LO__VI; -typedef union CP_CPC_IC_OP_CNTL__VI regCP_CPC_IC_OP_CNTL__VI; -typedef union CP_CPC_MGCG_SYNC_CNTL__VI regCP_CPC_MGCG_SYNC_CNTL__VI; -typedef union CP_DFY_CMD__VI regCP_DFY_CMD__VI; -typedef union CP_DISPATCH_INDR_ADDR__VI regCP_DISPATCH_INDR_ADDR__VI; -typedef union CP_DISPATCH_INDR_ADDR_HI__VI regCP_DISPATCH_INDR_ADDR_HI__VI; -typedef union CP_DRAW_INDX_INDR_ADDR__VI regCP_DRAW_INDX_INDR_ADDR__VI; -typedef union CP_DRAW_INDX_INDR_ADDR_HI__VI regCP_DRAW_INDX_INDR_ADDR_HI__VI; -typedef union CP_DRAW_OBJECT__VI regCP_DRAW_OBJECT__VI; -typedef union CP_DRAW_OBJECT_COUNTER__VI regCP_DRAW_OBJECT_COUNTER__VI; -typedef union CP_DRAW_WINDOW_CNTL__VI regCP_DRAW_WINDOW_CNTL__VI; -typedef union CP_DRAW_WINDOW_HI__VI regCP_DRAW_WINDOW_HI__VI; -typedef union CP_DRAW_WINDOW_LO__VI regCP_DRAW_WINDOW_LO__VI; -typedef union CP_DRAW_WINDOW_MASK_HI__VI regCP_DRAW_WINDOW_MASK_HI__VI; -typedef union CP_EOP_DONE_CNTX_ID__VI regCP_EOP_DONE_CNTX_ID__VI; -typedef union CP_GDS_BKUP_ADDR__VI regCP_GDS_BKUP_ADDR__VI; -typedef union CP_GDS_BKUP_ADDR_HI__VI regCP_GDS_BKUP_ADDR_HI__VI; -typedef union CP_HPD_STATUS0__VI regCP_HPD_STATUS0__VI; -typedef union CP_HQD_CNTL_STACK_OFFSET__VI regCP_HQD_CNTL_STACK_OFFSET__VI; -typedef union CP_HQD_CNTL_STACK_SIZE__VI regCP_HQD_CNTL_STACK_SIZE__VI; -typedef union CP_HQD_CTX_SAVE_BASE_ADDR_HI__VI regCP_HQD_CTX_SAVE_BASE_ADDR_HI__VI; -typedef union CP_HQD_CTX_SAVE_BASE_ADDR_LO__VI regCP_HQD_CTX_SAVE_BASE_ADDR_LO__VI; -typedef union CP_HQD_CTX_SAVE_CONTROL__VI regCP_HQD_CTX_SAVE_CONTROL__VI; -typedef union CP_HQD_CTX_SAVE_SIZE__VI regCP_HQD_CTX_SAVE_SIZE__VI; -typedef union CP_HQD_EOP_BASE_ADDR__VI regCP_HQD_EOP_BASE_ADDR__VI; -typedef union CP_HQD_EOP_BASE_ADDR_HI__VI regCP_HQD_EOP_BASE_ADDR_HI__VI; -typedef union CP_HQD_EOP_CONTROL__VI regCP_HQD_EOP_CONTROL__VI; -typedef union CP_HQD_EOP_DONES__VI regCP_HQD_EOP_DONES__VI; -typedef union CP_HQD_EOP_EVENTS__VI regCP_HQD_EOP_EVENTS__VI; -typedef union CP_HQD_EOP_RPTR__VI regCP_HQD_EOP_RPTR__VI; -typedef union CP_HQD_EOP_WPTR__VI regCP_HQD_EOP_WPTR__VI; -typedef union CP_HQD_EOP_WPTR_MEM__VI regCP_HQD_EOP_WPTR_MEM__VI; -typedef union CP_HQD_ERROR__VI regCP_HQD_ERROR__VI; -typedef union CP_HQD_GDS_RESOURCE_STATE__VI regCP_HQD_GDS_RESOURCE_STATE__VI; -typedef union CP_HQD_HQ_CONTROL0__VI regCP_HQD_HQ_CONTROL0__VI; -typedef union CP_HQD_HQ_CONTROL1__VI regCP_HQD_HQ_CONTROL1__VI; -typedef union CP_HQD_HQ_STATUS0__VI regCP_HQD_HQ_STATUS0__VI; -typedef union CP_HQD_HQ_STATUS1__VI regCP_HQD_HQ_STATUS1__VI; -typedef union CP_HQD_OFFLOAD__VI regCP_HQD_OFFLOAD__VI; -typedef union CP_HQD_WG_STATE_OFFSET__VI regCP_HQD_WG_STATE_OFFSET__VI; -typedef union CP_HYP_CE_UCODE_ADDR__VI regCP_HYP_CE_UCODE_ADDR__VI; -typedef union CP_HYP_CE_UCODE_DATA__VI regCP_HYP_CE_UCODE_DATA__VI; -typedef union CP_HYP_CONFIG_RANGE_BASE_1__VI regCP_HYP_CONFIG_RANGE_BASE_1__VI; -typedef union CP_HYP_CONFIG_RANGE_BASE_2__VI regCP_HYP_CONFIG_RANGE_BASE_2__VI; -typedef union CP_HYP_CONFIG_RANGE_END_1__VI regCP_HYP_CONFIG_RANGE_END_1__VI; -typedef union CP_HYP_CONFIG_RANGE_END_2__VI regCP_HYP_CONFIG_RANGE_END_2__VI; -typedef union CP_HYP_CONTEXT_RANGE_BASE__VI regCP_HYP_CONTEXT_RANGE_BASE__VI; -typedef union CP_HYP_CONTEXT_RANGE_END__VI regCP_HYP_CONTEXT_RANGE_END__VI; -typedef union CP_HYP_MEC1_UCODE_ADDR__VI regCP_HYP_MEC1_UCODE_ADDR__VI; -typedef union CP_HYP_MEC1_UCODE_DATA__VI regCP_HYP_MEC1_UCODE_DATA__VI; -typedef union CP_HYP_MEC2_UCODE_ADDR__VI regCP_HYP_MEC2_UCODE_ADDR__VI; -typedef union CP_HYP_MEC2_UCODE_DATA__VI regCP_HYP_MEC2_UCODE_DATA__VI; -typedef union CP_HYP_ME_UCODE_ADDR__VI regCP_HYP_ME_UCODE_ADDR__VI; -typedef union CP_HYP_ME_UCODE_DATA__VI regCP_HYP_ME_UCODE_DATA__VI; -typedef union CP_HYP_PFP_UCODE_ADDR__VI regCP_HYP_PFP_UCODE_ADDR__VI; -typedef union CP_HYP_PFP_UCODE_DATA__VI regCP_HYP_PFP_UCODE_DATA__VI; -typedef union CP_HYP_SHADER_RANGE_BASE__VI regCP_HYP_SHADER_RANGE_BASE__VI; -typedef union CP_HYP_SHADER_RANGE_END__VI regCP_HYP_SHADER_RANGE_END__VI; -typedef union CP_HYP_UCONFIG_RANGE_BASE__VI regCP_HYP_UCONFIG_RANGE_BASE__VI; -typedef union CP_HYP_UCONFIG_RANGE_END__VI regCP_HYP_UCONFIG_RANGE_END__VI; -typedef union CP_INDEX_BASE_ADDR__VI regCP_INDEX_BASE_ADDR__VI; -typedef union CP_INDEX_BASE_ADDR_HI__VI regCP_INDEX_BASE_ADDR_HI__VI; -typedef union CP_INDEX_TYPE__VI regCP_INDEX_TYPE__VI; -typedef union CP_MEC1_F32_INT_DIS__VI regCP_MEC1_F32_INT_DIS__VI; -typedef union CP_MEC2_F32_INT_DIS__VI regCP_MEC2_F32_INT_DIS__VI; -typedef union CP_MEC_DOORBELL_RANGE_LOWER__VI regCP_MEC_DOORBELL_RANGE_LOWER__VI; -typedef union CP_MEC_DOORBELL_RANGE_UPPER__VI regCP_MEC_DOORBELL_RANGE_UPPER__VI; -typedef union CP_PFP_COMPLETION_STATUS__VI regCP_PFP_COMPLETION_STATUS__VI; -typedef union CP_PFP_METADATA_BASE_ADDR__VI regCP_PFP_METADATA_BASE_ADDR__VI; -typedef union CP_PFP_METADATA_BASE_ADDR_HI__VI regCP_PFP_METADATA_BASE_ADDR_HI__VI; -typedef union CP_PIPE_STATS_CONTROL__VI regCP_PIPE_STATS_CONTROL__VI; -typedef union CP_PQ_STATUS__VI regCP_PQ_STATUS__VI; -typedef union CP_PRED_NOT_VISIBLE__VI regCP_PRED_NOT_VISIBLE__VI; -typedef union CP_RB_DOORBELL_CONTROL__VI regCP_RB_DOORBELL_CONTROL__VI; -typedef union CP_RB_DOORBELL_RANGE_LOWER__VI regCP_RB_DOORBELL_RANGE_LOWER__VI; -typedef union CP_RB_DOORBELL_RANGE_UPPER__VI regCP_RB_DOORBELL_RANGE_UPPER__VI; -typedef union CP_SAMPLE_STATUS__VI regCP_SAMPLE_STATUS__VI; -typedef union CP_STREAM_OUT_CONTROL__VI regCP_STREAM_OUT_CONTROL__VI; -typedef union CP_VMID_STATUS__VI regCP_VMID_STATUS__VI; -typedef union DBG_SMB_BYPASS_SRBM_ACCESS__VI regDBG_SMB_BYPASS_SRBM_ACCESS__VI; -typedef union DIDT_DBR_CTRL0__VI regDIDT_DBR_CTRL0__VI; -typedef union DIDT_DBR_CTRL1__VI regDIDT_DBR_CTRL1__VI; -typedef union DIDT_DBR_CTRL2__VI regDIDT_DBR_CTRL2__VI; -typedef union DIDT_DBR_CTRL_OCP__VI regDIDT_DBR_CTRL_OCP__VI; -typedef union DIDT_DBR_WEIGHT0_3__VI regDIDT_DBR_WEIGHT0_3__VI; -typedef union DIDT_DBR_WEIGHT4_7__VI regDIDT_DBR_WEIGHT4_7__VI; -typedef union DIDT_DBR_WEIGHT8_11__VI regDIDT_DBR_WEIGHT8_11__VI; -typedef union DIDT_DB_CTRL_OCP__VI regDIDT_DB_CTRL_OCP__VI; -typedef union DIDT_SQ_CTRL_OCP__VI regDIDT_SQ_CTRL_OCP__VI; -typedef union DIDT_TCP_CTRL_OCP__VI regDIDT_TCP_CTRL_OCP__VI; -typedef union DIDT_TD_CTRL_OCP__VI regDIDT_TD_CTRL_OCP__VI; -typedef union GARLIC_COHE_CP_DMA_ME_COMMAND__VI regGARLIC_COHE_CP_DMA_ME_COMMAND__VI; -typedef union GARLIC_COHE_CP_DMA_PFP_COMMAND__VI regGARLIC_COHE_CP_DMA_PFP_COMMAND__VI; -typedef union GARLIC_COHE_CP_DMA_PIO_COMMAND__VI regGARLIC_COHE_CP_DMA_PIO_COMMAND__VI; -typedef union GARLIC_COHE_CP_RB0_WPTR__VI regGARLIC_COHE_CP_RB0_WPTR__VI; -typedef union GARLIC_COHE_CP_RB1_WPTR__VI regGARLIC_COHE_CP_RB1_WPTR__VI; -typedef union GARLIC_COHE_CP_RB2_WPTR__VI regGARLIC_COHE_CP_RB2_WPTR__VI; -typedef union GARLIC_COHE_GARLIC_FLUSH_REQ__VI regGARLIC_COHE_GARLIC_FLUSH_REQ__VI; -typedef union GARLIC_COHE_SAM_SAB_RBI_WPTR__VI regGARLIC_COHE_SAM_SAB_RBI_WPTR__VI; -typedef union GARLIC_COHE_SAM_SAB_RBO_WPTR__VI regGARLIC_COHE_SAM_SAB_RBO_WPTR__VI; -typedef union GARLIC_COHE_SDMA0_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA0_GFX_RB_WPTR__VI; -typedef union GARLIC_COHE_SDMA1_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA1_GFX_RB_WPTR__VI; -typedef union GARLIC_COHE_SDMA2_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA2_GFX_RB_WPTR__VI; -typedef union GARLIC_COHE_SDMA3_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA3_GFX_RB_WPTR__VI; -typedef union GARLIC_COHE_UVD_RBC_RB_WPTR__VI regGARLIC_COHE_UVD_RBC_RB_WPTR__VI; -typedef union GARLIC_COHE_VCE_OUT_RB_WPTR__VI regGARLIC_COHE_VCE_OUT_RB_WPTR__VI; -typedef union GARLIC_COHE_VCE_RB_WPTR__VI regGARLIC_COHE_VCE_RB_WPTR__VI; -typedef union GARLIC_COHE_VCE_RB_WPTR2__VI regGARLIC_COHE_VCE_RB_WPTR2__VI; -typedef union GCK_ACLK_DIV_FUSES__VI regGCK_ACLK_DIV_FUSES__VI; -typedef union GCK_ADFS_CLK_BYPASS_CNTL1__VI regGCK_ADFS_CLK_BYPASS_CNTL1__VI; -typedef union GCK_ADFS_CLK_BYPASS_CNTL2__VI regGCK_ADFS_CLK_BYPASS_CNTL2__VI; -typedef union GCK_DFS_BYPASS_CNTL__VI regGCK_DFS_BYPASS_CNTL__VI; -typedef union GCK_GPUPLL_DGCK_CNTL_1__VI regGCK_GPUPLL_DGCK_CNTL_1__VI; -typedef union GCK_GPUPLL_DGCK_CNTL_3__VI regGCK_GPUPLL_DGCK_CNTL_3__VI; -typedef union GCK_GPUPLL_DGCK_CNTL_6__VI regGCK_GPUPLL_DGCK_CNTL_6__VI; -typedef union GCK_GPUPLL_DGCK_CNTL_7__VI regGCK_GPUPLL_DGCK_CNTL_7__VI; -typedef union GCK_LCLK_FUSES__VI regGCK_LCLK_FUSES__VI; -typedef union GCK_PLL_TEST_CNTL_2__VI regGCK_PLL_TEST_CNTL_2__VI; -typedef union GCK_PSPCLK_FUSES__VI regGCK_PSPCLK_FUSES__VI; -typedef union GCK_RESET_TMR_FUSES__VI regGCK_RESET_TMR_FUSES__VI; -typedef union GCK_SPARE_1__VI regGCK_SPARE_1__VI; -typedef union GCK_TPLL_FUSES__VI regGCK_TPLL_FUSES__VI; -typedef union GC_CAC_ACC_BCI0__VI regGC_CAC_ACC_BCI0__VI; -typedef union GC_CAC_ACC_CB0__VI regGC_CAC_ACC_CB0__VI; -typedef union GC_CAC_ACC_CB1__VI regGC_CAC_ACC_CB1__VI; -typedef union GC_CAC_ACC_CB2__VI regGC_CAC_ACC_CB2__VI; -typedef union GC_CAC_ACC_CB3__VI regGC_CAC_ACC_CB3__VI; -typedef union GC_CAC_ACC_CP0__VI regGC_CAC_ACC_CP0__VI; -typedef union GC_CAC_ACC_CP1__VI regGC_CAC_ACC_CP1__VI; -typedef union GC_CAC_ACC_CP2__VI regGC_CAC_ACC_CP2__VI; -typedef union GC_CAC_ACC_CU0__VI regGC_CAC_ACC_CU0__VI; -typedef union GC_CAC_ACC_CU1__VI regGC_CAC_ACC_CU1__VI; -typedef union GC_CAC_ACC_CU2__VI regGC_CAC_ACC_CU2__VI; -typedef union GC_CAC_ACC_CU3__VI regGC_CAC_ACC_CU3__VI; -typedef union GC_CAC_ACC_CU_LKG0__VI regGC_CAC_ACC_CU_LKG0__VI; -typedef union GC_CAC_ACC_CU_LKG1__VI regGC_CAC_ACC_CU_LKG1__VI; -typedef union GC_CAC_ACC_CU_LKG2__VI regGC_CAC_ACC_CU_LKG2__VI; -typedef union GC_CAC_ACC_CU_LKG3__VI regGC_CAC_ACC_CU_LKG3__VI; -typedef union GC_CAC_ACC_CU_LKG4__VI regGC_CAC_ACC_CU_LKG4__VI; -typedef union GC_CAC_ACC_CU_LKG5__VI regGC_CAC_ACC_CU_LKG5__VI; -typedef union GC_CAC_ACC_CU_LKG6__VI regGC_CAC_ACC_CU_LKG6__VI; -typedef union GC_CAC_ACC_CU_LKG7__VI regGC_CAC_ACC_CU_LKG7__VI; -typedef union GC_CAC_ACC_DB0__VI regGC_CAC_ACC_DB0__VI; -typedef union GC_CAC_ACC_DB1__VI regGC_CAC_ACC_DB1__VI; -typedef union GC_CAC_ACC_DB2__VI regGC_CAC_ACC_DB2__VI; -typedef union GC_CAC_ACC_DB3__VI regGC_CAC_ACC_DB3__VI; -typedef union GC_CAC_ACC_GCATCL20__VI regGC_CAC_ACC_GCATCL20__VI; -typedef union GC_CAC_ACC_GDS0__VI regGC_CAC_ACC_GDS0__VI; -typedef union GC_CAC_ACC_GDS1__VI regGC_CAC_ACC_GDS1__VI; -typedef union GC_CAC_ACC_GDS2__VI regGC_CAC_ACC_GDS2__VI; -typedef union GC_CAC_ACC_GDS3__VI regGC_CAC_ACC_GDS3__VI; -typedef union GC_CAC_ACC_IA0__VI regGC_CAC_ACC_IA0__VI; -typedef union GC_CAC_ACC_LDS0__VI regGC_CAC_ACC_LDS0__VI; -typedef union GC_CAC_ACC_LDS1__VI regGC_CAC_ACC_LDS1__VI; -typedef union GC_CAC_ACC_LDS2__VI regGC_CAC_ACC_LDS2__VI; -typedef union GC_CAC_ACC_LDS3__VI regGC_CAC_ACC_LDS3__VI; -typedef union GC_CAC_ACC_NONCU_LKG0__VI regGC_CAC_ACC_NONCU_LKG0__VI; -typedef union GC_CAC_ACC_NONCU_LKG1__VI regGC_CAC_ACC_NONCU_LKG1__VI; -typedef union GC_CAC_ACC_NONCU_LKG2__VI regGC_CAC_ACC_NONCU_LKG2__VI; -typedef union GC_CAC_ACC_NONCU_LKG3__VI regGC_CAC_ACC_NONCU_LKG3__VI; -typedef union GC_CAC_ACC_NONCU_LKG4__VI regGC_CAC_ACC_NONCU_LKG4__VI; -typedef union GC_CAC_ACC_NONCU_LKG5__VI regGC_CAC_ACC_NONCU_LKG5__VI; -typedef union GC_CAC_ACC_NONCU_LKG6__VI regGC_CAC_ACC_NONCU_LKG6__VI; -typedef union GC_CAC_ACC_PA0__VI regGC_CAC_ACC_PA0__VI; -typedef union GC_CAC_ACC_PA1__VI regGC_CAC_ACC_PA1__VI; -typedef union GC_CAC_ACC_PC0__VI regGC_CAC_ACC_PC0__VI; -typedef union GC_CAC_ACC_SC0__VI regGC_CAC_ACC_SC0__VI; -typedef union GC_CAC_ACC_SPI0__VI regGC_CAC_ACC_SPI0__VI; -typedef union GC_CAC_ACC_SPI1__VI regGC_CAC_ACC_SPI1__VI; -typedef union GC_CAC_ACC_SPI2__VI regGC_CAC_ACC_SPI2__VI; -typedef union GC_CAC_ACC_SPI3__VI regGC_CAC_ACC_SPI3__VI; -typedef union GC_CAC_ACC_SPI4__VI regGC_CAC_ACC_SPI4__VI; -typedef union GC_CAC_ACC_SPI5__VI regGC_CAC_ACC_SPI5__VI; -typedef union GC_CAC_ACC_SQ0_LOWER__VI regGC_CAC_ACC_SQ0_LOWER__VI; -typedef union GC_CAC_ACC_SQ0_UPPER__VI regGC_CAC_ACC_SQ0_UPPER__VI; -typedef union GC_CAC_ACC_SQ1_LOWER__VI regGC_CAC_ACC_SQ1_LOWER__VI; -typedef union GC_CAC_ACC_SQ1_UPPER__VI regGC_CAC_ACC_SQ1_UPPER__VI; -typedef union GC_CAC_ACC_SQ2_LOWER__VI regGC_CAC_ACC_SQ2_LOWER__VI; -typedef union GC_CAC_ACC_SQ2_UPPER__VI regGC_CAC_ACC_SQ2_UPPER__VI; -typedef union GC_CAC_ACC_SQ3_LOWER__VI regGC_CAC_ACC_SQ3_LOWER__VI; -typedef union GC_CAC_ACC_SQ3_UPPER__VI regGC_CAC_ACC_SQ3_UPPER__VI; -typedef union GC_CAC_ACC_SQ4_LOWER__VI regGC_CAC_ACC_SQ4_LOWER__VI; -typedef union GC_CAC_ACC_SQ4_UPPER__VI regGC_CAC_ACC_SQ4_UPPER__VI; -typedef union GC_CAC_ACC_SQ5_LOWER__VI regGC_CAC_ACC_SQ5_LOWER__VI; -typedef union GC_CAC_ACC_SQ5_UPPER__VI regGC_CAC_ACC_SQ5_UPPER__VI; -typedef union GC_CAC_ACC_SQ6_LOWER__VI regGC_CAC_ACC_SQ6_LOWER__VI; -typedef union GC_CAC_ACC_SQ6_UPPER__VI regGC_CAC_ACC_SQ6_UPPER__VI; -typedef union GC_CAC_ACC_SQ7_LOWER__VI regGC_CAC_ACC_SQ7_LOWER__VI; -typedef union GC_CAC_ACC_SQ7_UPPER__VI regGC_CAC_ACC_SQ7_UPPER__VI; -typedef union GC_CAC_ACC_SQ8_LOWER__VI regGC_CAC_ACC_SQ8_LOWER__VI; -typedef union GC_CAC_ACC_SQ8_UPPER__VI regGC_CAC_ACC_SQ8_UPPER__VI; -typedef union GC_CAC_ACC_SX0__VI regGC_CAC_ACC_SX0__VI; -typedef union GC_CAC_ACC_SXRB0__VI regGC_CAC_ACC_SXRB0__VI; -typedef union GC_CAC_ACC_SXRB1__VI regGC_CAC_ACC_SXRB1__VI; -typedef union GC_CAC_ACC_TA0__VI regGC_CAC_ACC_TA0__VI; -typedef union GC_CAC_ACC_TCC0__VI regGC_CAC_ACC_TCC0__VI; -typedef union GC_CAC_ACC_TCC1__VI regGC_CAC_ACC_TCC1__VI; -typedef union GC_CAC_ACC_TCC2__VI regGC_CAC_ACC_TCC2__VI; -typedef union GC_CAC_ACC_TCC3__VI regGC_CAC_ACC_TCC3__VI; -typedef union GC_CAC_ACC_TCC4__VI regGC_CAC_ACC_TCC4__VI; -typedef union GC_CAC_ACC_TCP0__VI regGC_CAC_ACC_TCP0__VI; -typedef union GC_CAC_ACC_TCP1__VI regGC_CAC_ACC_TCP1__VI; -typedef union GC_CAC_ACC_TCP2__VI regGC_CAC_ACC_TCP2__VI; -typedef union GC_CAC_ACC_TCP3__VI regGC_CAC_ACC_TCP3__VI; -typedef union GC_CAC_ACC_TCP4__VI regGC_CAC_ACC_TCP4__VI; -typedef union GC_CAC_ACC_TD0__VI regGC_CAC_ACC_TD0__VI; -typedef union GC_CAC_ACC_TD1__VI regGC_CAC_ACC_TD1__VI; -typedef union GC_CAC_ACC_TD2__VI regGC_CAC_ACC_TD2__VI; -typedef union GC_CAC_ACC_TD3__VI regGC_CAC_ACC_TD3__VI; -typedef union GC_CAC_ACC_TD4__VI regGC_CAC_ACC_TD4__VI; -typedef union GC_CAC_ACC_TD5__VI regGC_CAC_ACC_TD5__VI; -typedef union GC_CAC_ACC_VGT0__VI regGC_CAC_ACC_VGT0__VI; -typedef union GC_CAC_ACC_VGT1__VI regGC_CAC_ACC_VGT1__VI; -typedef union GC_CAC_ACC_VGT2__VI regGC_CAC_ACC_VGT2__VI; -typedef union GC_CAC_ACC_WD0__VI regGC_CAC_ACC_WD0__VI; -typedef union GC_CAC_AGGR_LOWER__VI regGC_CAC_AGGR_LOWER__VI; -typedef union GC_CAC_AGGR_UPPER__VI regGC_CAC_AGGR_UPPER__VI; -typedef union GC_CAC_CGTT_CLK_CTRL__VI regGC_CAC_CGTT_CLK_CTRL__VI; -typedef union GC_CAC_CNTL__VI regGC_CAC_CNTL__VI; -typedef union GC_CAC_CTRL_1__VI regGC_CAC_CTRL_1__VI; -typedef union GC_CAC_CTRL_2__VI regGC_CAC_CTRL_2__VI; -typedef union GC_CAC_IND_DATA__VI regGC_CAC_IND_DATA__VI; -typedef union GC_CAC_IND_INDEX__VI regGC_CAC_IND_INDEX__VI; -typedef union GC_CAC_LKG_AGGR_LOWER__VI regGC_CAC_LKG_AGGR_LOWER__VI; -typedef union GC_CAC_LKG_AGGR_UPPER__VI regGC_CAC_LKG_AGGR_UPPER__VI; -typedef union GC_CAC_OVRD_BCI__VI regGC_CAC_OVRD_BCI__VI; -typedef union GC_CAC_OVRD_CB__VI regGC_CAC_OVRD_CB__VI; -typedef union GC_CAC_OVRD_CP__VI regGC_CAC_OVRD_CP__VI; -typedef union GC_CAC_OVRD_CU__VI regGC_CAC_OVRD_CU__VI; -typedef union GC_CAC_OVRD_CU_LKG__VI regGC_CAC_OVRD_CU_LKG__VI; -typedef union GC_CAC_OVRD_DB__VI regGC_CAC_OVRD_DB__VI; -typedef union GC_CAC_OVRD_GCATCL2__VI regGC_CAC_OVRD_GCATCL2__VI; -typedef union GC_CAC_OVRD_GDS__VI regGC_CAC_OVRD_GDS__VI; -typedef union GC_CAC_OVRD_IA__VI regGC_CAC_OVRD_IA__VI; -typedef union GC_CAC_OVRD_LDS__VI regGC_CAC_OVRD_LDS__VI; -typedef union GC_CAC_OVRD_NONCU_LKG__VI regGC_CAC_OVRD_NONCU_LKG__VI; -typedef union GC_CAC_OVRD_PA__VI regGC_CAC_OVRD_PA__VI; -typedef union GC_CAC_OVRD_PC__VI regGC_CAC_OVRD_PC__VI; -typedef union GC_CAC_OVRD_SC__VI regGC_CAC_OVRD_SC__VI; -typedef union GC_CAC_OVRD_SPI__VI regGC_CAC_OVRD_SPI__VI; -typedef union GC_CAC_OVRD_SQ__VI regGC_CAC_OVRD_SQ__VI; -typedef union GC_CAC_OVRD_SX__VI regGC_CAC_OVRD_SX__VI; -typedef union GC_CAC_OVRD_SXRB__VI regGC_CAC_OVRD_SXRB__VI; -typedef union GC_CAC_OVRD_TA__VI regGC_CAC_OVRD_TA__VI; -typedef union GC_CAC_OVRD_TCC__VI regGC_CAC_OVRD_TCC__VI; -typedef union GC_CAC_OVRD_TCP__VI regGC_CAC_OVRD_TCP__VI; -typedef union GC_CAC_OVRD_TD__VI regGC_CAC_OVRD_TD__VI; -typedef union GC_CAC_OVRD_VGT__VI regGC_CAC_OVRD_VGT__VI; -typedef union GC_CAC_OVRD_WD__VI regGC_CAC_OVRD_WD__VI; -typedef union GC_CAC_OVR_SEL__VI regGC_CAC_OVR_SEL__VI; -typedef union GC_CAC_OVR_VAL__VI regGC_CAC_OVR_VAL__VI; -typedef union GC_CAC_WEIGHT_BCI_0__VI regGC_CAC_WEIGHT_BCI_0__VI; -typedef union GC_CAC_WEIGHT_CB_0__VI regGC_CAC_WEIGHT_CB_0__VI; -typedef union GC_CAC_WEIGHT_CB_1__VI regGC_CAC_WEIGHT_CB_1__VI; -typedef union GC_CAC_WEIGHT_CP_0__VI regGC_CAC_WEIGHT_CP_0__VI; -typedef union GC_CAC_WEIGHT_CP_1__VI regGC_CAC_WEIGHT_CP_1__VI; -typedef union GC_CAC_WEIGHT_CU_0__VI regGC_CAC_WEIGHT_CU_0__VI; -typedef union GC_CAC_WEIGHT_CU_1__VI regGC_CAC_WEIGHT_CU_1__VI; -typedef union GC_CAC_WEIGHT_CU_LKG_0__VI regGC_CAC_WEIGHT_CU_LKG_0__VI; -typedef union GC_CAC_WEIGHT_CU_LKG_1__VI regGC_CAC_WEIGHT_CU_LKG_1__VI; -typedef union GC_CAC_WEIGHT_CU_LKG_2__VI regGC_CAC_WEIGHT_CU_LKG_2__VI; -typedef union GC_CAC_WEIGHT_CU_LKG_3__VI regGC_CAC_WEIGHT_CU_LKG_3__VI; -typedef union GC_CAC_WEIGHT_DB_0__VI regGC_CAC_WEIGHT_DB_0__VI; -typedef union GC_CAC_WEIGHT_DB_1__VI regGC_CAC_WEIGHT_DB_1__VI; -typedef union GC_CAC_WEIGHT_GCATCL2_0__VI regGC_CAC_WEIGHT_GCATCL2_0__VI; -typedef union GC_CAC_WEIGHT_GDS_0__VI regGC_CAC_WEIGHT_GDS_0__VI; -typedef union GC_CAC_WEIGHT_GDS_1__VI regGC_CAC_WEIGHT_GDS_1__VI; -typedef union GC_CAC_WEIGHT_IA_0__VI regGC_CAC_WEIGHT_IA_0__VI; -typedef union GC_CAC_WEIGHT_LDS_0__VI regGC_CAC_WEIGHT_LDS_0__VI; -typedef union GC_CAC_WEIGHT_LDS_1__VI regGC_CAC_WEIGHT_LDS_1__VI; -typedef union GC_CAC_WEIGHT_NONCU_LKG_0__VI regGC_CAC_WEIGHT_NONCU_LKG_0__VI; -typedef union GC_CAC_WEIGHT_NONCU_LKG_1__VI regGC_CAC_WEIGHT_NONCU_LKG_1__VI; -typedef union GC_CAC_WEIGHT_NONCU_LKG_2__VI regGC_CAC_WEIGHT_NONCU_LKG_2__VI; -typedef union GC_CAC_WEIGHT_NONCU_LKG_3__VI regGC_CAC_WEIGHT_NONCU_LKG_3__VI; -typedef union GC_CAC_WEIGHT_PA_0__VI regGC_CAC_WEIGHT_PA_0__VI; -typedef union GC_CAC_WEIGHT_PC_0__VI regGC_CAC_WEIGHT_PC_0__VI; -typedef union GC_CAC_WEIGHT_SC_0__VI regGC_CAC_WEIGHT_SC_0__VI; -typedef union GC_CAC_WEIGHT_SPI_0__VI regGC_CAC_WEIGHT_SPI_0__VI; -typedef union GC_CAC_WEIGHT_SPI_1__VI regGC_CAC_WEIGHT_SPI_1__VI; -typedef union GC_CAC_WEIGHT_SPI_2__VI regGC_CAC_WEIGHT_SPI_2__VI; -typedef union GC_CAC_WEIGHT_SQ_0__VI regGC_CAC_WEIGHT_SQ_0__VI; -typedef union GC_CAC_WEIGHT_SQ_1__VI regGC_CAC_WEIGHT_SQ_1__VI; -typedef union GC_CAC_WEIGHT_SQ_2__VI regGC_CAC_WEIGHT_SQ_2__VI; -typedef union GC_CAC_WEIGHT_SQ_3__VI regGC_CAC_WEIGHT_SQ_3__VI; -typedef union GC_CAC_WEIGHT_SQ_4__VI regGC_CAC_WEIGHT_SQ_4__VI; -typedef union GC_CAC_WEIGHT_SXRB_0__VI regGC_CAC_WEIGHT_SXRB_0__VI; -typedef union GC_CAC_WEIGHT_SX_0__VI regGC_CAC_WEIGHT_SX_0__VI; -typedef union GC_CAC_WEIGHT_TA_0__VI regGC_CAC_WEIGHT_TA_0__VI; -typedef union GC_CAC_WEIGHT_TCC_0__VI regGC_CAC_WEIGHT_TCC_0__VI; -typedef union GC_CAC_WEIGHT_TCC_1__VI regGC_CAC_WEIGHT_TCC_1__VI; -typedef union GC_CAC_WEIGHT_TCC_2__VI regGC_CAC_WEIGHT_TCC_2__VI; -typedef union GC_CAC_WEIGHT_TCP_0__VI regGC_CAC_WEIGHT_TCP_0__VI; -typedef union GC_CAC_WEIGHT_TCP_1__VI regGC_CAC_WEIGHT_TCP_1__VI; -typedef union GC_CAC_WEIGHT_TCP_2__VI regGC_CAC_WEIGHT_TCP_2__VI; -typedef union GC_CAC_WEIGHT_TD_0__VI regGC_CAC_WEIGHT_TD_0__VI; -typedef union GC_CAC_WEIGHT_TD_1__VI regGC_CAC_WEIGHT_TD_1__VI; -typedef union GC_CAC_WEIGHT_TD_2__VI regGC_CAC_WEIGHT_TD_2__VI; -typedef union GC_CAC_WEIGHT_VGT_0__VI regGC_CAC_WEIGHT_VGT_0__VI; -typedef union GC_CAC_WEIGHT_VGT_1__VI regGC_CAC_WEIGHT_VGT_1__VI; -typedef union GC_CAC_WEIGHT_WD_0__VI regGC_CAC_WEIGHT_WD_0__VI; -typedef union GC_USER_SHADER_RATE_CONFIG__VI regGC_USER_SHADER_RATE_CONFIG__VI; -typedef union GDS_CS_CTXSW_CNT0__VI regGDS_CS_CTXSW_CNT0__VI; -typedef union GDS_CS_CTXSW_CNT1__VI regGDS_CS_CTXSW_CNT1__VI; -typedef union GDS_CS_CTXSW_CNT2__VI regGDS_CS_CTXSW_CNT2__VI; -typedef union GDS_CS_CTXSW_CNT3__VI regGDS_CS_CTXSW_CNT3__VI; -typedef union GDS_CS_CTXSW_STATUS__VI regGDS_CS_CTXSW_STATUS__VI; -typedef union GDS_DSM_CNTL__VI regGDS_DSM_CNTL__VI; -typedef union GDS_EDC_CNT__VI regGDS_EDC_CNT__VI; -typedef union GDS_EDC_GRBM_CNT__VI regGDS_EDC_GRBM_CNT__VI; -typedef union GDS_EDC_OA_DED__VI regGDS_EDC_OA_DED__VI; -typedef union GDS_GFX_CTXSW_STATUS__VI regGDS_GFX_CTXSW_STATUS__VI; -typedef union GDS_PS0_CTXSW_CNT0__VI regGDS_PS0_CTXSW_CNT0__VI; -typedef union GDS_PS0_CTXSW_CNT1__VI regGDS_PS0_CTXSW_CNT1__VI; -typedef union GDS_PS0_CTXSW_CNT2__VI regGDS_PS0_CTXSW_CNT2__VI; -typedef union GDS_PS0_CTXSW_CNT3__VI regGDS_PS0_CTXSW_CNT3__VI; -typedef union GDS_PS1_CTXSW_CNT0__VI regGDS_PS1_CTXSW_CNT0__VI; -typedef union GDS_PS1_CTXSW_CNT1__VI regGDS_PS1_CTXSW_CNT1__VI; -typedef union GDS_PS1_CTXSW_CNT2__VI regGDS_PS1_CTXSW_CNT2__VI; -typedef union GDS_PS1_CTXSW_CNT3__VI regGDS_PS1_CTXSW_CNT3__VI; -typedef union GDS_PS2_CTXSW_CNT0__VI regGDS_PS2_CTXSW_CNT0__VI; -typedef union GDS_PS2_CTXSW_CNT1__VI regGDS_PS2_CTXSW_CNT1__VI; -typedef union GDS_PS2_CTXSW_CNT2__VI regGDS_PS2_CTXSW_CNT2__VI; -typedef union GDS_PS2_CTXSW_CNT3__VI regGDS_PS2_CTXSW_CNT3__VI; -typedef union GDS_PS3_CTXSW_CNT0__VI regGDS_PS3_CTXSW_CNT0__VI; -typedef union GDS_PS3_CTXSW_CNT1__VI regGDS_PS3_CTXSW_CNT1__VI; -typedef union GDS_PS3_CTXSW_CNT2__VI regGDS_PS3_CTXSW_CNT2__VI; -typedef union GDS_PS3_CTXSW_CNT3__VI regGDS_PS3_CTXSW_CNT3__VI; -typedef union GDS_PS4_CTXSW_CNT0__VI regGDS_PS4_CTXSW_CNT0__VI; -typedef union GDS_PS4_CTXSW_CNT1__VI regGDS_PS4_CTXSW_CNT1__VI; -typedef union GDS_PS4_CTXSW_CNT2__VI regGDS_PS4_CTXSW_CNT2__VI; -typedef union GDS_PS4_CTXSW_CNT3__VI regGDS_PS4_CTXSW_CNT3__VI; -typedef union GDS_PS5_CTXSW_CNT0__VI regGDS_PS5_CTXSW_CNT0__VI; -typedef union GDS_PS5_CTXSW_CNT1__VI regGDS_PS5_CTXSW_CNT1__VI; -typedef union GDS_PS5_CTXSW_CNT2__VI regGDS_PS5_CTXSW_CNT2__VI; -typedef union GDS_PS5_CTXSW_CNT3__VI regGDS_PS5_CTXSW_CNT3__VI; -typedef union GDS_PS6_CTXSW_CNT0__VI regGDS_PS6_CTXSW_CNT0__VI; -typedef union GDS_PS6_CTXSW_CNT1__VI regGDS_PS6_CTXSW_CNT1__VI; -typedef union GDS_PS6_CTXSW_CNT2__VI regGDS_PS6_CTXSW_CNT2__VI; -typedef union GDS_PS6_CTXSW_CNT3__VI regGDS_PS6_CTXSW_CNT3__VI; -typedef union GDS_PS7_CTXSW_CNT0__VI regGDS_PS7_CTXSW_CNT0__VI; -typedef union GDS_PS7_CTXSW_CNT1__VI regGDS_PS7_CTXSW_CNT1__VI; -typedef union GDS_PS7_CTXSW_CNT2__VI regGDS_PS7_CTXSW_CNT2__VI; -typedef union GDS_PS7_CTXSW_CNT3__VI regGDS_PS7_CTXSW_CNT3__VI; -typedef union GDS_VS_CTXSW_CNT0__VI regGDS_VS_CTXSW_CNT0__VI; -typedef union GDS_VS_CTXSW_CNT1__VI regGDS_VS_CTXSW_CNT1__VI; -typedef union GDS_VS_CTXSW_CNT2__VI regGDS_VS_CTXSW_CNT2__VI; -typedef union GDS_VS_CTXSW_CNT3__VI regGDS_VS_CTXSW_CNT3__VI; -typedef union GMCON_LPT_TARGET__VI regGMCON_LPT_TARGET__VI; -typedef union GPU_BIST_CONTROL__VI regGPU_BIST_CONTROL__VI; -typedef union GRBM_CGTT_CLK_CNTL__VI regGRBM_CGTT_CLK_CNTL__VI; -typedef union GRBM_DSM_BYPASS__VI regGRBM_DSM_BYPASS__VI; -typedef union GRBM_HYP_CAM_DATA__VI regGRBM_HYP_CAM_DATA__VI; -typedef union GRBM_HYP_CAM_INDEX__VI regGRBM_HYP_CAM_INDEX__VI; -typedef union GRBM_TRAP_ADDR__VI regGRBM_TRAP_ADDR__VI; -typedef union GRBM_TRAP_ADDR_MSK__VI regGRBM_TRAP_ADDR_MSK__VI; -typedef union GRBM_TRAP_OP__VI regGRBM_TRAP_OP__VI; -typedef union GRBM_TRAP_WD__VI regGRBM_TRAP_WD__VI; -typedef union GRBM_TRAP_WD_MSK__VI regGRBM_TRAP_WD_MSK__VI; -typedef union GRBM_WRITE_ERROR__VI regGRBM_WRITE_ERROR__VI; -typedef union GSKT_CONTROL__VI regGSKT_CONTROL__VI; -typedef union IH_DSM_MATCH_DATA_CONTROL__VI regIH_DSM_MATCH_DATA_CONTROL__VI; -typedef union IH_DSM_MATCH_FIELD_CONTROL__VI regIH_DSM_MATCH_FIELD_CONTROL__VI; -typedef union IH_DSM_MATCH_VALUE_BIT_31_0__VI regIH_DSM_MATCH_VALUE_BIT_31_0__VI; -typedef union IH_DSM_MATCH_VALUE_BIT_63_32__VI regIH_DSM_MATCH_VALUE_BIT_63_32__VI; -typedef union IH_DSM_MATCH_VALUE_BIT_95_64__VI regIH_DSM_MATCH_VALUE_BIT_95_64__VI; -typedef union IH_VERSION__VI regIH_VERSION__VI; -typedef union LM_CONTROL__VI regLM_CONTROL__VI; -typedef union LM_LANEENABLE__VI regLM_LANEENABLE__VI; -typedef union LM_PCIERXMUX0__VI regLM_PCIERXMUX0__VI; -typedef union LM_PCIERXMUX1__VI regLM_PCIERXMUX1__VI; -typedef union LM_PCIERXMUX2__VI regLM_PCIERXMUX2__VI; -typedef union LM_PCIERXMUX3__VI regLM_PCIERXMUX3__VI; -typedef union LM_PCIETXMUX0__VI regLM_PCIETXMUX0__VI; -typedef union LM_PCIETXMUX1__VI regLM_PCIETXMUX1__VI; -typedef union LM_PCIETXMUX2__VI regLM_PCIETXMUX2__VI; -typedef union LM_PCIETXMUX3__VI regLM_PCIETXMUX3__VI; -typedef union LM_POWERCONTROL__VI regLM_POWERCONTROL__VI; -typedef union LM_POWERCONTROL1__VI regLM_POWERCONTROL1__VI; -typedef union LM_POWERCONTROL2__VI regLM_POWERCONTROL2__VI; -typedef union LM_POWERCONTROL3__VI regLM_POWERCONTROL3__VI; -typedef union LM_POWERCONTROL4__VI regLM_POWERCONTROL4__VI; -typedef union LM_PRBSCONTROL__VI regLM_PRBSCONTROL__VI; -typedef union LNCNT_QUAN_THRD__VI regLNCNT_QUAN_THRD__VI; -typedef union LNCNT_WEIGHT__VI regLNCNT_WEIGHT__VI; -typedef union LNC_BW_WACC__VI regLNC_BW_WACC__VI; -typedef union LNC_CMN_WACC__VI regLNC_CMN_WACC__VI; -typedef union LNC_TOTAL_WACC__VI regLNC_TOTAL_WACC__VI; -typedef union MAILBOX_CONTROL__VI regMAILBOX_CONTROL__VI; -typedef union MAILBOX_INDEX__VI regMAILBOX_INDEX__VI; -typedef union MAILBOX_INT_CNTL__VI regMAILBOX_INT_CNTL__VI; -typedef union MAILBOX_MSGBUF_RCV_DW0__VI regMAILBOX_MSGBUF_RCV_DW0__VI; -typedef union MAILBOX_MSGBUF_RCV_DW1__VI regMAILBOX_MSGBUF_RCV_DW1__VI; -typedef union MAILBOX_MSGBUF_RCV_DW2__VI regMAILBOX_MSGBUF_RCV_DW2__VI; -typedef union MAILBOX_MSGBUF_RCV_DW3__VI regMAILBOX_MSGBUF_RCV_DW3__VI; -typedef union MAILBOX_MSGBUF_TRN_DW0__VI regMAILBOX_MSGBUF_TRN_DW0__VI; -typedef union MAILBOX_MSGBUF_TRN_DW1__VI regMAILBOX_MSGBUF_TRN_DW1__VI; -typedef union MAILBOX_MSGBUF_TRN_DW2__VI regMAILBOX_MSGBUF_TRN_DW2__VI; -typedef union MAILBOX_MSGBUF_TRN_DW3__VI regMAILBOX_MSGBUF_TRN_DW3__VI; -typedef union MC_ARB_ATOMIC__VI regMC_ARB_ATOMIC__VI; -typedef union MC_ARB_GRUB__VI regMC_ARB_GRUB__VI; -typedef union MC_ARB_GRUB2__VI regMC_ARB_GRUB2__VI; -typedef union MC_ARB_GRUB_PRIORITY1_RD__VI regMC_ARB_GRUB_PRIORITY1_RD__VI; -typedef union MC_ARB_GRUB_PRIORITY1_WR__VI regMC_ARB_GRUB_PRIORITY1_WR__VI; -typedef union MC_ARB_GRUB_PRIORITY2_RD__VI regMC_ARB_GRUB_PRIORITY2_RD__VI; -typedef union MC_ARB_GRUB_PRIORITY2_WR__VI regMC_ARB_GRUB_PRIORITY2_WR__VI; -typedef union MC_ARB_GRUB_PROMOTE__VI regMC_ARB_GRUB_PROMOTE__VI; -typedef union MC_ARB_GRUB_REALTIME_RD__VI regMC_ARB_GRUB_REALTIME_RD__VI; -typedef union MC_ARB_GRUB_REALTIME_WR__VI regMC_ARB_GRUB_REALTIME_WR__VI; -typedef union MC_ARB_PERF_CID__VI regMC_ARB_PERF_CID__VI; -typedef union MC_ARB_SNOOP__VI regMC_ARB_SNOOP__VI; -typedef union MC_CITF_CREDITS_ARB_RD2__VI regMC_CITF_CREDITS_ARB_RD2__VI; -typedef union MC_FUS_ARB_GARLIC_CNTL__VI regMC_FUS_ARB_GARLIC_CNTL__VI; -typedef union MC_FUS_ARB_GARLIC_ISOC_PRI__VI regMC_FUS_ARB_GARLIC_ISOC_PRI__VI; -typedef union MC_FUS_ARB_GARLIC_WR_PRI__VI regMC_FUS_ARB_GARLIC_WR_PRI__VI; -typedef union MC_FUS_ARB_GARLIC_WR_PRI2__VI regMC_FUS_ARB_GARLIC_WR_PRI2__VI; -typedef union MC_FUS_DRAM0_BANK_ADDR_MAPPING__VI regMC_FUS_DRAM0_BANK_ADDR_MAPPING__VI; -typedef union MC_FUS_DRAM0_CS01_MASK__VI regMC_FUS_DRAM0_CS01_MASK__VI; -typedef union MC_FUS_DRAM0_CS0_BASE__VI regMC_FUS_DRAM0_CS0_BASE__VI; -typedef union MC_FUS_DRAM0_CS1_BASE__VI regMC_FUS_DRAM0_CS1_BASE__VI; -typedef union MC_FUS_DRAM0_CS23_MASK__VI regMC_FUS_DRAM0_CS23_MASK__VI; -typedef union MC_FUS_DRAM0_CS2_BASE__VI regMC_FUS_DRAM0_CS2_BASE__VI; -typedef union MC_FUS_DRAM0_CS3_BASE__VI regMC_FUS_DRAM0_CS3_BASE__VI; -typedef union MC_FUS_DRAM0_CTL_BASE__VI regMC_FUS_DRAM0_CTL_BASE__VI; -typedef union MC_FUS_DRAM0_CTL_LIMIT__VI regMC_FUS_DRAM0_CTL_LIMIT__VI; -typedef union MC_FUS_DRAM1_BANK_ADDR_MAPPING__VI regMC_FUS_DRAM1_BANK_ADDR_MAPPING__VI; -typedef union MC_FUS_DRAM1_CS01_MASK__VI regMC_FUS_DRAM1_CS01_MASK__VI; -typedef union MC_FUS_DRAM1_CS0_BASE__VI regMC_FUS_DRAM1_CS0_BASE__VI; -typedef union MC_FUS_DRAM1_CS1_BASE__VI regMC_FUS_DRAM1_CS1_BASE__VI; -typedef union MC_FUS_DRAM1_CS23_MASK__VI regMC_FUS_DRAM1_CS23_MASK__VI; -typedef union MC_FUS_DRAM1_CS2_BASE__VI regMC_FUS_DRAM1_CS2_BASE__VI; -typedef union MC_FUS_DRAM1_CS3_BASE__VI regMC_FUS_DRAM1_CS3_BASE__VI; -typedef union MC_FUS_DRAM1_CTL_BASE__VI regMC_FUS_DRAM1_CTL_BASE__VI; -typedef union MC_FUS_DRAM1_CTL_LIMIT__VI regMC_FUS_DRAM1_CTL_LIMIT__VI; -typedef union MC_FUS_DRAM_APER_BASE__VI regMC_FUS_DRAM_APER_BASE__VI; -typedef union MC_FUS_DRAM_APER_DEF__VI regMC_FUS_DRAM_APER_DEF__VI; -typedef union MC_FUS_DRAM_APER_TOP__VI regMC_FUS_DRAM_APER_TOP__VI; -typedef union MC_FUS_DRAM_CTL_HIGH_01__VI regMC_FUS_DRAM_CTL_HIGH_01__VI; -typedef union MC_FUS_DRAM_CTL_HIGH_23__VI regMC_FUS_DRAM_CTL_HIGH_23__VI; -typedef union MC_FUS_DRAM_MODE__VI regMC_FUS_DRAM_MODE__VI; -typedef union MC_GRUB_FEATURES__VI regMC_GRUB_FEATURES__VI; -typedef union MC_GRUB_PERFCOUNTER0_CFG__VI regMC_GRUB_PERFCOUNTER0_CFG__VI; -typedef union MC_GRUB_PERFCOUNTER1_CFG__VI regMC_GRUB_PERFCOUNTER1_CFG__VI; -typedef union MC_GRUB_PERFCOUNTER_HI__VI regMC_GRUB_PERFCOUNTER_HI__VI; -typedef union MC_GRUB_PERFCOUNTER_LO__VI regMC_GRUB_PERFCOUNTER_LO__VI; -typedef union MC_GRUB_PERFCOUNTER_RSLT_CNTL__VI regMC_GRUB_PERFCOUNTER_RSLT_CNTL__VI; -typedef union MC_GRUB_POST_PROBE_DELAY__VI regMC_GRUB_POST_PROBE_DELAY__VI; -typedef union MC_GRUB_PROBE_CREDITS__VI regMC_GRUB_PROBE_CREDITS__VI; -typedef union MC_GRUB_PROBE_MAP__VI regMC_GRUB_PROBE_MAP__VI; -typedef union MC_GRUB_TCB_DATA_HI__VI regMC_GRUB_TCB_DATA_HI__VI; -typedef union MC_GRUB_TCB_DATA_LO__VI regMC_GRUB_TCB_DATA_LO__VI; -typedef union MC_GRUB_TCB_INDEX__VI regMC_GRUB_TCB_INDEX__VI; -typedef union MC_GRUB_TX_CREDITS__VI regMC_GRUB_TX_CREDITS__VI; -typedef union MC_HUB_MISC_ATOMIC_IDLE_STATUS__VI regMC_HUB_MISC_ATOMIC_IDLE_STATUS__VI; -typedef union MC_HUB_RDREQ_BYPASS_GBL0__VI regMC_HUB_RDREQ_BYPASS_GBL0__VI; -typedef union MC_HUB_RDREQ_ISP_CCPU__VI regMC_HUB_RDREQ_ISP_CCPU__VI; -typedef union MC_HUB_RDREQ_ISP_MPM__VI regMC_HUB_RDREQ_ISP_MPM__VI; -typedef union MC_HUB_RDREQ_ISP_SPM__VI regMC_HUB_RDREQ_ISP_SPM__VI; -typedef union MC_HUB_RDREQ_MCDS__VI regMC_HUB_RDREQ_MCDS__VI; -typedef union MC_HUB_RDREQ_MCDT__VI regMC_HUB_RDREQ_MCDT__VI; -typedef union MC_HUB_RDREQ_MCDU__VI regMC_HUB_RDREQ_MCDU__VI; -typedef union MC_HUB_RDREQ_MCDV__VI regMC_HUB_RDREQ_MCDV__VI; -typedef union MC_HUB_RDREQ_SAMMSP__VI regMC_HUB_RDREQ_SAMMSP__VI; -typedef union MC_HUB_RDREQ_VCE0__VI regMC_HUB_RDREQ_VCE0__VI; -typedef union MC_HUB_RDREQ_VCE1__VI regMC_HUB_RDREQ_VCE1__VI; -typedef union MC_HUB_RDREQ_VCEU0__VI regMC_HUB_RDREQ_VCEU0__VI; -typedef union MC_HUB_RDREQ_VCEU1__VI regMC_HUB_RDREQ_VCEU1__VI; -typedef union MC_HUB_RDREQ_VP8__VI regMC_HUB_RDREQ_VP8__VI; -typedef union MC_HUB_WDP_BP2__VI regMC_HUB_WDP_BP2__VI; -typedef union MC_HUB_WDP_BYPASS_GBL0__VI regMC_HUB_WDP_BYPASS_GBL0__VI; -typedef union MC_HUB_WDP_BYPASS_GBL1__VI regMC_HUB_WDP_BYPASS_GBL1__VI; -typedef union MC_HUB_WDP_CREDITS2__VI regMC_HUB_WDP_CREDITS2__VI; -typedef union MC_HUB_WDP_CREDITS_MCDS__VI regMC_HUB_WDP_CREDITS_MCDS__VI; -typedef union MC_HUB_WDP_CREDITS_MCDT__VI regMC_HUB_WDP_CREDITS_MCDT__VI; -typedef union MC_HUB_WDP_CREDITS_MCDU__VI regMC_HUB_WDP_CREDITS_MCDU__VI; -typedef union MC_HUB_WDP_CREDITS_MCDV__VI regMC_HUB_WDP_CREDITS_MCDV__VI; -typedef union MC_HUB_WDP_CREDITS_MCDW__VI regMC_HUB_WDP_CREDITS_MCDW__VI; -typedef union MC_HUB_WDP_CREDITS_MCDX__VI regMC_HUB_WDP_CREDITS_MCDX__VI; -typedef union MC_HUB_WDP_CREDITS_MCDY__VI regMC_HUB_WDP_CREDITS_MCDY__VI; -typedef union MC_HUB_WDP_CREDITS_MCDZ__VI regMC_HUB_WDP_CREDITS_MCDZ__VI; -typedef union MC_HUB_WDP_ISP_CCPU__VI regMC_HUB_WDP_ISP_CCPU__VI; -typedef union MC_HUB_WDP_ISP_MPM__VI regMC_HUB_WDP_ISP_MPM__VI; -typedef union MC_HUB_WDP_ISP_MPS__VI regMC_HUB_WDP_ISP_MPS__VI; -typedef union MC_HUB_WDP_ISP_SPM__VI regMC_HUB_WDP_ISP_SPM__VI; -typedef union MC_HUB_WDP_MCDS__VI regMC_HUB_WDP_MCDS__VI; -typedef union MC_HUB_WDP_MCDT__VI regMC_HUB_WDP_MCDT__VI; -typedef union MC_HUB_WDP_MCDU__VI regMC_HUB_WDP_MCDU__VI; -typedef union MC_HUB_WDP_MCDV__VI regMC_HUB_WDP_MCDV__VI; -typedef union MC_HUB_WDP_SAMMSP__VI regMC_HUB_WDP_SAMMSP__VI; -typedef union MC_HUB_WDP_VCE0__VI regMC_HUB_WDP_VCE0__VI; -typedef union MC_HUB_WDP_VCE1__VI regMC_HUB_WDP_VCE1__VI; -typedef union MC_HUB_WDP_VCEU0__VI regMC_HUB_WDP_VCEU0__VI; -typedef union MC_HUB_WDP_VCEU1__VI regMC_HUB_WDP_VCEU1__VI; -typedef union MC_HUB_WDP_VP8__VI regMC_HUB_WDP_VP8__VI; -typedef union MC_HUB_WRRET_MCDS__VI regMC_HUB_WRRET_MCDS__VI; -typedef union MC_HUB_WRRET_MCDT__VI regMC_HUB_WRRET_MCDT__VI; -typedef union MC_HUB_WRRET_MCDU__VI regMC_HUB_WRRET_MCDU__VI; -typedef union MC_HUB_WRRET_MCDV__VI regMC_HUB_WRRET_MCDV__VI; -typedef union MC_RPB_TCI_CNTL__VI regMC_RPB_TCI_CNTL__VI; -typedef union MC_RPB_TCI_CNTL2__VI regMC_RPB_TCI_CNTL2__VI; -typedef union MC_SHARED_ACTIVE_FCN_ID__VI regMC_SHARED_ACTIVE_FCN_ID__VI; -typedef union MC_SHARED_CHREMAP2__VI regMC_SHARED_CHREMAP2__VI; -typedef union MC_SHARED_VF_ENABLE__VI regMC_SHARED_VF_ENABLE__VI; -typedef union MC_SHARED_VIRT_RESET_REQ__VI regMC_SHARED_VIRT_RESET_REQ__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF0__VI regMC_VM_FB_SIZE_OFFSET_VF0__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF1__VI regMC_VM_FB_SIZE_OFFSET_VF1__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF10__VI regMC_VM_FB_SIZE_OFFSET_VF10__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF11__VI regMC_VM_FB_SIZE_OFFSET_VF11__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF12__VI regMC_VM_FB_SIZE_OFFSET_VF12__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF13__VI regMC_VM_FB_SIZE_OFFSET_VF13__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF14__VI regMC_VM_FB_SIZE_OFFSET_VF14__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF15__VI regMC_VM_FB_SIZE_OFFSET_VF15__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF2__VI regMC_VM_FB_SIZE_OFFSET_VF2__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF3__VI regMC_VM_FB_SIZE_OFFSET_VF3__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF4__VI regMC_VM_FB_SIZE_OFFSET_VF4__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF5__VI regMC_VM_FB_SIZE_OFFSET_VF5__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF6__VI regMC_VM_FB_SIZE_OFFSET_VF6__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF7__VI regMC_VM_FB_SIZE_OFFSET_VF7__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF8__VI regMC_VM_FB_SIZE_OFFSET_VF8__VI; -typedef union MC_VM_FB_SIZE_OFFSET_VF9__VI regMC_VM_FB_SIZE_OFFSET_VF9__VI; -typedef union MC_VM_MB_L1_TLB1_DEBUG__VI regMC_VM_MB_L1_TLB1_DEBUG__VI; -typedef union MC_VM_NB_LOWER_TOP_OF_DRAM2__VI regMC_VM_NB_LOWER_TOP_OF_DRAM2__VI; -typedef union MC_VM_NB_MMIOBASE__VI regMC_VM_NB_MMIOBASE__VI; -typedef union MC_VM_NB_MMIOLIMIT__VI regMC_VM_NB_MMIOLIMIT__VI; -typedef union MC_VM_NB_PCI_ARB__VI regMC_VM_NB_PCI_ARB__VI; -typedef union MC_VM_NB_PCI_CTRL__VI regMC_VM_NB_PCI_CTRL__VI; -typedef union MC_VM_NB_TOP_OF_DRAM3__VI regMC_VM_NB_TOP_OF_DRAM3__VI; -typedef union MC_VM_NB_TOP_OF_DRAM_SLOT1__VI regMC_VM_NB_TOP_OF_DRAM_SLOT1__VI; -typedef union MC_VM_NB_UPPER_TOP_OF_DRAM2__VI regMC_VM_NB_UPPER_TOP_OF_DRAM2__VI; -typedef union MC_XBAR_FIFO_MON_CNTL0__VI regMC_XBAR_FIFO_MON_CNTL0__VI; -typedef union MC_XBAR_FIFO_MON_CNTL1__VI regMC_XBAR_FIFO_MON_CNTL1__VI; -typedef union MC_XBAR_FIFO_MON_CNTL2__VI regMC_XBAR_FIFO_MON_CNTL2__VI; -typedef union MC_XBAR_FIFO_MON_MAX_THSH__VI regMC_XBAR_FIFO_MON_MAX_THSH__VI; -typedef union MC_XBAR_FIFO_MON_RSLT0__VI regMC_XBAR_FIFO_MON_RSLT0__VI; -typedef union MC_XBAR_FIFO_MON_RSLT1__VI regMC_XBAR_FIFO_MON_RSLT1__VI; -typedef union MC_XBAR_FIFO_MON_RSLT2__VI regMC_XBAR_FIFO_MON_RSLT2__VI; -typedef union MC_XBAR_FIFO_MON_RSLT3__VI regMC_XBAR_FIFO_MON_RSLT3__VI; -typedef union MP_FPS_CNT__VI regMP_FPS_CNT__VI; -typedef union MSI_MASK__VI regMSI_MASK__VI; -typedef union MSI_MASK_64__VI regMSI_MASK_64__VI; -typedef union MSI_PENDING__VI regMSI_PENDING__VI; -typedef union MSI_PENDING_64__VI regMSI_PENDING_64__VI; -typedef union ORB_IF_config__VI regORB_IF_config__VI; -typedef union PA_SC_DSM_CNTL__VI regPA_SC_DSM_CNTL__VI; -typedef union PA_SC_ENHANCE_1__VI regPA_SC_ENHANCE_1__VI; -typedef union PA_SC_SHADER_CONTROL__VI regPA_SC_SHADER_CONTROL__VI; -typedef union PB0_PIF_BIF_CMD_STATUS__VI regPB0_PIF_BIF_CMD_STATUS__VI; -typedef union PB0_PIF_CMD_BUS_CTRL__VI regPB0_PIF_CMD_BUS_CTRL__VI; -typedef union PB0_PIF_CMD_BUS_GLB_OVRD__VI regPB0_PIF_CMD_BUS_GLB_OVRD__VI; -typedef union PB0_PIF_CTRL__VI regPB0_PIF_CTRL__VI; -typedef union PB0_PIF_GLB_OVRD__VI regPB0_PIF_GLB_OVRD__VI; -typedef union PB0_PIF_GLB_OVRD2__VI regPB0_PIF_GLB_OVRD2__VI; -typedef union PB0_PIF_LANE0_OVRD__VI regPB0_PIF_LANE0_OVRD__VI; -typedef union PB0_PIF_LANE0_OVRD2__VI regPB0_PIF_LANE0_OVRD2__VI; -typedef union PB0_PIF_LANE1_OVRD__VI regPB0_PIF_LANE1_OVRD__VI; -typedef union PB0_PIF_LANE1_OVRD2__VI regPB0_PIF_LANE1_OVRD2__VI; -typedef union PB0_PIF_LANE2_OVRD__VI regPB0_PIF_LANE2_OVRD__VI; -typedef union PB0_PIF_LANE2_OVRD2__VI regPB0_PIF_LANE2_OVRD2__VI; -typedef union PB0_PIF_LANE3_OVRD__VI regPB0_PIF_LANE3_OVRD__VI; -typedef union PB0_PIF_LANE3_OVRD2__VI regPB0_PIF_LANE3_OVRD2__VI; -typedef union PB0_PIF_LANE4_OVRD__VI regPB0_PIF_LANE4_OVRD__VI; -typedef union PB0_PIF_LANE4_OVRD2__VI regPB0_PIF_LANE4_OVRD2__VI; -typedef union PB0_PIF_LANE5_OVRD__VI regPB0_PIF_LANE5_OVRD__VI; -typedef union PB0_PIF_LANE5_OVRD2__VI regPB0_PIF_LANE5_OVRD2__VI; -typedef union PB0_PIF_LANE6_OVRD__VI regPB0_PIF_LANE6_OVRD__VI; -typedef union PB0_PIF_LANE6_OVRD2__VI regPB0_PIF_LANE6_OVRD2__VI; -typedef union PB0_PIF_LANE7_OVRD__VI regPB0_PIF_LANE7_OVRD__VI; -typedef union PB0_PIF_LANE7_OVRD2__VI regPB0_PIF_LANE7_OVRD2__VI; -typedef union PB0_PIF_RX_CTRL__VI regPB0_PIF_RX_CTRL__VI; -typedef union PB0_PIF_RX_CTRL2__VI regPB0_PIF_RX_CTRL2__VI; -typedef union PB0_PIF_STRAP_0__VI regPB0_PIF_STRAP_0__VI; -typedef union PB0_PIF_TX_CTRL__VI regPB0_PIF_TX_CTRL__VI; -typedef union PB0_PIF_TX_CTRL2__VI regPB0_PIF_TX_CTRL2__VI; -typedef union PB0_STRAP_GLB_REG1__VI regPB0_STRAP_GLB_REG1__VI; -typedef union PB0_STRAP_GLB_REG2__VI regPB0_STRAP_GLB_REG2__VI; -typedef union PB1_PIF_BIF_CMD_STATUS__VI regPB1_PIF_BIF_CMD_STATUS__VI; -typedef union PB1_PIF_CMD_BUS_CTRL__VI regPB1_PIF_CMD_BUS_CTRL__VI; -typedef union PB1_PIF_CMD_BUS_GLB_OVRD__VI regPB1_PIF_CMD_BUS_GLB_OVRD__VI; -typedef union PB1_PIF_CTRL__VI regPB1_PIF_CTRL__VI; -typedef union PB1_PIF_GLB_OVRD__VI regPB1_PIF_GLB_OVRD__VI; -typedef union PB1_PIF_GLB_OVRD2__VI regPB1_PIF_GLB_OVRD2__VI; -typedef union PB1_PIF_LANE0_OVRD__VI regPB1_PIF_LANE0_OVRD__VI; -typedef union PB1_PIF_LANE0_OVRD2__VI regPB1_PIF_LANE0_OVRD2__VI; -typedef union PB1_PIF_LANE1_OVRD__VI regPB1_PIF_LANE1_OVRD__VI; -typedef union PB1_PIF_LANE1_OVRD2__VI regPB1_PIF_LANE1_OVRD2__VI; -typedef union PB1_PIF_LANE2_OVRD__VI regPB1_PIF_LANE2_OVRD__VI; -typedef union PB1_PIF_LANE2_OVRD2__VI regPB1_PIF_LANE2_OVRD2__VI; -typedef union PB1_PIF_LANE3_OVRD__VI regPB1_PIF_LANE3_OVRD__VI; -typedef union PB1_PIF_LANE3_OVRD2__VI regPB1_PIF_LANE3_OVRD2__VI; -typedef union PB1_PIF_LANE4_OVRD__VI regPB1_PIF_LANE4_OVRD__VI; -typedef union PB1_PIF_LANE4_OVRD2__VI regPB1_PIF_LANE4_OVRD2__VI; -typedef union PB1_PIF_LANE5_OVRD__VI regPB1_PIF_LANE5_OVRD__VI; -typedef union PB1_PIF_LANE5_OVRD2__VI regPB1_PIF_LANE5_OVRD2__VI; -typedef union PB1_PIF_LANE6_OVRD__VI regPB1_PIF_LANE6_OVRD__VI; -typedef union PB1_PIF_LANE6_OVRD2__VI regPB1_PIF_LANE6_OVRD2__VI; -typedef union PB1_PIF_LANE7_OVRD__VI regPB1_PIF_LANE7_OVRD__VI; -typedef union PB1_PIF_LANE7_OVRD2__VI regPB1_PIF_LANE7_OVRD2__VI; -typedef union PB1_PIF_RX_CTRL__VI regPB1_PIF_RX_CTRL__VI; -typedef union PB1_PIF_RX_CTRL2__VI regPB1_PIF_RX_CTRL2__VI; -typedef union PB1_PIF_STRAP_0__VI regPB1_PIF_STRAP_0__VI; -typedef union PB1_PIF_TX_CTRL__VI regPB1_PIF_TX_CTRL__VI; -typedef union PB1_PIF_TX_CTRL2__VI regPB1_PIF_TX_CTRL2__VI; -typedef union PB1_STRAP_GLB_REG1__VI regPB1_STRAP_GLB_REG1__VI; -typedef union PB1_STRAP_GLB_REG2__VI regPB1_STRAP_GLB_REG2__VI; -typedef union PCIEP_ERROR_INJECT_PHYSICAL__VI regPCIEP_ERROR_INJECT_PHYSICAL__VI; -typedef union PCIEP_ERROR_INJECT_TRANSACTION__VI regPCIEP_ERROR_INJECT_TRANSACTION__VI; -typedef union PCIEP_SRIOV_PRIV_CTRL__VI regPCIEP_SRIOV_PRIV_CTRL__VI; -typedef union PCIE_ARI_CAP__VI regPCIE_ARI_CAP__VI; -typedef union PCIE_ARI_CNTL__VI regPCIE_ARI_CNTL__VI; -typedef union PCIE_ARI_ENH_CAP_LIST__VI regPCIE_ARI_ENH_CAP_LIST__VI; -typedef union PCIE_EFUSE__VI regPCIE_EFUSE__VI; -typedef union PCIE_EFUSE2__VI regPCIE_EFUSE2__VI; -typedef union PCIE_EFUSE3__VI regPCIE_EFUSE3__VI; -typedef union PCIE_EFUSE4__VI regPCIE_EFUSE4__VI; -typedef union PCIE_EFUSE5__VI regPCIE_EFUSE5__VI; -typedef union PCIE_HOLD_TRAINING_A__VI regPCIE_HOLD_TRAINING_A__VI; -typedef union PCIE_LC_BEST_EQ_SETTINGS__VI regPCIE_LC_BEST_EQ_SETTINGS__VI; -typedef union PCIE_LC_CNTL6__VI regPCIE_LC_CNTL6__VI; -typedef union PCIE_LC_FORCE_EQ_REQ_COEFF__VI regPCIE_LC_FORCE_EQ_REQ_COEFF__VI; -typedef union PCIE_LTR_CAP__VI regPCIE_LTR_CAP__VI; -typedef union PCIE_LTR_ENH_CAP_LIST__VI regPCIE_LTR_ENH_CAP_LIST__VI; -typedef union PCIE_MC_ADDR0__VI regPCIE_MC_ADDR0__VI; -typedef union PCIE_MC_ADDR1__VI regPCIE_MC_ADDR1__VI; -typedef union PCIE_MC_BLOCK_ALL0__VI regPCIE_MC_BLOCK_ALL0__VI; -typedef union PCIE_MC_BLOCK_ALL1__VI regPCIE_MC_BLOCK_ALL1__VI; -typedef union PCIE_MC_BLOCK_UNTRANSLATED_0__VI regPCIE_MC_BLOCK_UNTRANSLATED_0__VI; -typedef union PCIE_MC_BLOCK_UNTRANSLATED_1__VI regPCIE_MC_BLOCK_UNTRANSLATED_1__VI; -typedef union PCIE_MC_CAP__VI regPCIE_MC_CAP__VI; -typedef union PCIE_MC_CNTL__VI regPCIE_MC_CNTL__VI; -typedef union PCIE_MC_ENH_CAP_LIST__VI regPCIE_MC_ENH_CAP_LIST__VI; -typedef union PCIE_MC_RCV0__VI regPCIE_MC_RCV0__VI; -typedef union PCIE_MC_RCV1__VI regPCIE_MC_RCV1__VI; -typedef union PCIE_OBFF_CNTL__VI regPCIE_OBFF_CNTL__VI; -typedef union PCIE_RXDET_OVERRIDE__VI regPCIE_RXDET_OVERRIDE__VI; -typedef union PCIE_SRIOV_CAP__VI regPCIE_SRIOV_CAP__VI; -typedef union PCIE_SRIOV_CONTROL__VI regPCIE_SRIOV_CONTROL__VI; -typedef union PCIE_SRIOV_ENH_CAP_LIST__VI regPCIE_SRIOV_ENH_CAP_LIST__VI; -typedef union PCIE_SRIOV_FIRST_VF_OFFSET__VI regPCIE_SRIOV_FIRST_VF_OFFSET__VI; -typedef union PCIE_SRIOV_FUNC_DEP_LINK__VI regPCIE_SRIOV_FUNC_DEP_LINK__VI; -typedef union PCIE_SRIOV_INITIAL_VFS__VI regPCIE_SRIOV_INITIAL_VFS__VI; -typedef union PCIE_SRIOV_NUM_VFS__VI regPCIE_SRIOV_NUM_VFS__VI; -typedef union PCIE_SRIOV_STATUS__VI regPCIE_SRIOV_STATUS__VI; -typedef union PCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI regPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI; -typedef union PCIE_SRIOV_SYSTEM_PAGE_SIZE__VI regPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI; -typedef union PCIE_SRIOV_TOTAL_VFS__VI regPCIE_SRIOV_TOTAL_VFS__VI; -typedef union PCIE_SRIOV_VF_BASE_ADDR_0__VI regPCIE_SRIOV_VF_BASE_ADDR_0__VI; -typedef union PCIE_SRIOV_VF_BASE_ADDR_1__VI regPCIE_SRIOV_VF_BASE_ADDR_1__VI; -typedef union PCIE_SRIOV_VF_BASE_ADDR_2__VI regPCIE_SRIOV_VF_BASE_ADDR_2__VI; -typedef union PCIE_SRIOV_VF_BASE_ADDR_3__VI regPCIE_SRIOV_VF_BASE_ADDR_3__VI; -typedef union PCIE_SRIOV_VF_BASE_ADDR_4__VI regPCIE_SRIOV_VF_BASE_ADDR_4__VI; -typedef union PCIE_SRIOV_VF_BASE_ADDR_5__VI regPCIE_SRIOV_VF_BASE_ADDR_5__VI; -typedef union PCIE_SRIOV_VF_DEVICE_ID__VI regPCIE_SRIOV_VF_DEVICE_ID__VI; -typedef union PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI - regPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI; -typedef union PCIE_SRIOV_VF_STRIDE__VI regPCIE_SRIOV_VF_STRIDE__VI; -typedef union PCIE_TPH_REQR_CAP__VI regPCIE_TPH_REQR_CAP__VI; -typedef union PCIE_TPH_REQR_CNTL__VI regPCIE_TPH_REQR_CNTL__VI; -typedef union PCIE_TPH_REQR_ENH_CAP_LIST__VI regPCIE_TPH_REQR_ENH_CAP_LIST__VI; -typedef union PCIE_TX_LTR_CNTL__VI regPCIE_TX_LTR_CNTL__VI; -typedef union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI - regPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI; -typedef union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI regPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI; -typedef union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI - regPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI; -typedef union PCIE_WRAP_DTM_MISC__VI regPCIE_WRAP_DTM_MISC__VI; -typedef union PCIE_WRAP_MISC__VI regPCIE_WRAP_MISC__VI; -typedef union PCIE_WRAP_PIF_MISC__VI regPCIE_WRAP_PIF_MISC__VI; -typedef union PCIE_WRAP_REG_TARG_MISC__VI regPCIE_WRAP_REG_TARG_MISC__VI; -typedef union PCIE_WRAP_SCRATCH1__VI regPCIE_WRAP_SCRATCH1__VI; -typedef union PCIE_WRAP_SCRATCH2__VI regPCIE_WRAP_SCRATCH2__VI; -typedef union PCIE_WRAP_TURNAROUND_DAISYCHAIN__VI regPCIE_WRAP_TURNAROUND_DAISYCHAIN__VI; -typedef union PWR_OBSRV_CNTL__VI regPWR_OBSRV_CNTL__VI; -typedef union RAS_TA_SIGNATURE1__VI regRAS_TA_SIGNATURE1__VI; -typedef union REG_ADAPT_pciecore0_CONTROL__VI regREG_ADAPT_pciecore0_CONTROL__VI; -typedef union REG_ADAPT_pif0_CONTROL__VI regREG_ADAPT_pif0_CONTROL__VI; -typedef union REG_ADAPT_pwregr_CONTROL__VI regREG_ADAPT_pwregr_CONTROL__VI; -typedef union REG_ADAPT_pwregt_CONTROL__VI regREG_ADAPT_pwregt_CONTROL__VI; -typedef union REMAP_HDP_MEM_FLUSH_CNTL__VI regREMAP_HDP_MEM_FLUSH_CNTL__VI; -typedef union REMAP_HDP_REG_FLUSH_CNTL__VI regREMAP_HDP_REG_FLUSH_CNTL__VI; -typedef union RLC_CLK_CNTL__VI regRLC_CLK_CNTL__VI; -typedef union RLC_CP_RESPONSE0__VI regRLC_CP_RESPONSE0__VI; -typedef union RLC_CP_RESPONSE1__VI regRLC_CP_RESPONSE1__VI; -typedef union RLC_CP_RESPONSE2__VI regRLC_CP_RESPONSE2__VI; -typedef union RLC_CP_RESPONSE3__VI regRLC_CP_RESPONSE3__VI; -typedef union RLC_CP_SCHEDULERS__VI regRLC_CP_SCHEDULERS__VI; -typedef union RLC_CSIB_ADDR_HI__VI regRLC_CSIB_ADDR_HI__VI; -typedef union RLC_CSIB_ADDR_LO__VI regRLC_CSIB_ADDR_LO__VI; -typedef union RLC_CSIB_LENGTH__VI regRLC_CSIB_LENGTH__VI; -typedef union RLC_DEBE_0__VI regRLC_DEBE_0__VI; -typedef union RLC_DEBE_1__VI regRLC_DEBE_1__VI; -typedef union RLC_DEBE_2__VI regRLC_DEBE_2__VI; -typedef union RLC_DEBE_3__VI regRLC_DEBE_3__VI; -typedef union RLC_DEBE_WRITE_DIS__VI regRLC_DEBE_WRITE_DIS__VI; -typedef union RLC_GPM_GENERAL_10__VI regRLC_GPM_GENERAL_10__VI; -typedef union RLC_GPM_GENERAL_11__VI regRLC_GPM_GENERAL_11__VI; -typedef union RLC_GPM_GENERAL_12__VI regRLC_GPM_GENERAL_12__VI; -typedef union RLC_GPM_GENERAL_8__VI regRLC_GPM_GENERAL_8__VI; -typedef union RLC_GPM_GENERAL_9__VI regRLC_GPM_GENERAL_9__VI; -typedef union RLC_GPM_INT_DISABLE_TH0__VI regRLC_GPM_INT_DISABLE_TH0__VI; -typedef union RLC_GPM_INT_DISABLE_TH1__VI regRLC_GPM_INT_DISABLE_TH1__VI; -typedef union RLC_GPM_INT_FORCE_TH0__VI regRLC_GPM_INT_FORCE_TH0__VI; -typedef union RLC_GPM_INT_FORCE_TH1__VI regRLC_GPM_INT_FORCE_TH1__VI; -typedef union RLC_GPM_THREAD_RESET__VI regRLC_GPM_THREAD_RESET__VI; -typedef union RLC_GPU_IOV_ACTIVE_FCN_ID__VI regRLC_GPU_IOV_ACTIVE_FCN_ID__VI; -typedef union RLC_GPU_IOV_RLC_RESPONSE__VI regRLC_GPU_IOV_RLC_RESPONSE__VI; -typedef union RLC_GPU_IOV_VF_ENABLE__VI regRLC_GPU_IOV_VF_ENABLE__VI; -typedef union RLC_MGCG_CTRL__VI regRLC_MGCG_CTRL__VI; -typedef union RLC_PERFMON_CLK_CNTL__VI regRLC_PERFMON_CLK_CNTL__VI; -typedef union RLC_PG_DELAY_3__VI regRLC_PG_DELAY_3__VI; -typedef union RLC_RLCV_COMMAND__VI regRLC_RLCV_COMMAND__VI; -typedef union RLC_RLCV_SAFE_MODE__VI regRLC_RLCV_SAFE_MODE__VI; -typedef union RLC_ROM_CNTL__VI regRLC_ROM_CNTL__VI; -typedef union RLC_SMU_ARGUMENT_1__VI regRLC_SMU_ARGUMENT_1__VI; -typedef union RLC_SMU_ARGUMENT_2__VI regRLC_SMU_ARGUMENT_2__VI; -typedef union RLC_SMU_COMMAND__VI regRLC_SMU_COMMAND__VI; -typedef union RLC_SMU_MESSAGE__VI regRLC_SMU_MESSAGE__VI; -typedef union RLC_SMU_RESP__VI regRLC_SMU_RESP__VI; -typedef union RLC_SMU_SAFE_MODE__VI regRLC_SMU_SAFE_MODE__VI; -typedef union RLC_SRM_ARAM_ADDR__VI regRLC_SRM_ARAM_ADDR__VI; -typedef union RLC_SRM_ARAM_DATA__VI regRLC_SRM_ARAM_DATA__VI; -typedef union RLC_SRM_CNTL__VI regRLC_SRM_CNTL__VI; -typedef union RLC_SRM_DEBUG__VI regRLC_SRM_DEBUG__VI; -typedef union RLC_SRM_DEBUG_SELECT__VI regRLC_SRM_DEBUG_SELECT__VI; -typedef union RLC_SRM_DRAM_ADDR__VI regRLC_SRM_DRAM_ADDR__VI; -typedef union RLC_SRM_DRAM_DATA__VI regRLC_SRM_DRAM_DATA__VI; -typedef union RLC_SRM_GPM_ABORT__VI regRLC_SRM_GPM_ABORT__VI; -typedef union RLC_SRM_GPM_COMMAND__VI regRLC_SRM_GPM_COMMAND__VI; -typedef union RLC_SRM_GPM_COMMAND_STATUS__VI regRLC_SRM_GPM_COMMAND_STATUS__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_0__VI regRLC_SRM_INDEX_CNTL_ADDR_0__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_1__VI regRLC_SRM_INDEX_CNTL_ADDR_1__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_2__VI regRLC_SRM_INDEX_CNTL_ADDR_2__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_3__VI regRLC_SRM_INDEX_CNTL_ADDR_3__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_4__VI regRLC_SRM_INDEX_CNTL_ADDR_4__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_5__VI regRLC_SRM_INDEX_CNTL_ADDR_5__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_6__VI regRLC_SRM_INDEX_CNTL_ADDR_6__VI; -typedef union RLC_SRM_INDEX_CNTL_ADDR_7__VI regRLC_SRM_INDEX_CNTL_ADDR_7__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_0__VI regRLC_SRM_INDEX_CNTL_DATA_0__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_1__VI regRLC_SRM_INDEX_CNTL_DATA_1__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_2__VI regRLC_SRM_INDEX_CNTL_DATA_2__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_3__VI regRLC_SRM_INDEX_CNTL_DATA_3__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_4__VI regRLC_SRM_INDEX_CNTL_DATA_4__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_5__VI regRLC_SRM_INDEX_CNTL_DATA_5__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_6__VI regRLC_SRM_INDEX_CNTL_DATA_6__VI; -typedef union RLC_SRM_INDEX_CNTL_DATA_7__VI regRLC_SRM_INDEX_CNTL_DATA_7__VI; -typedef union RLC_SRM_RLCV_COMMAND__VI regRLC_SRM_RLCV_COMMAND__VI; -typedef union RLC_SRM_RLCV_COMMAND_STATUS__VI regRLC_SRM_RLCV_COMMAND_STATUS__VI; -typedef union RLC_SRM_STAT__VI regRLC_SRM_STAT__VI; -typedef union SDMA0_ACTIVE_FCN_ID__VI regSDMA0_ACTIVE_FCN_ID__VI; -typedef union SDMA0_ATOMIC_CNTL__VI regSDMA0_ATOMIC_CNTL__VI; -typedef union SDMA0_ATOMIC_PREOP_HI__VI regSDMA0_ATOMIC_PREOP_HI__VI; -typedef union SDMA0_ATOMIC_PREOP_LO__VI regSDMA0_ATOMIC_PREOP_LO__VI; -typedef union SDMA0_BA_THRESHOLD__VI regSDMA0_BA_THRESHOLD__VI; -typedef union SDMA0_CONTEXT_REG_TYPE0__VI regSDMA0_CONTEXT_REG_TYPE0__VI; -typedef union SDMA0_CONTEXT_REG_TYPE1__VI regSDMA0_CONTEXT_REG_TYPE1__VI; -typedef union SDMA0_CONTEXT_REG_TYPE2__VI regSDMA0_CONTEXT_REG_TYPE2__VI; -typedef union SDMA0_EDC_CONFIG__VI regSDMA0_EDC_CONFIG__VI; -typedef union SDMA0_GFX_CSA_ADDR_HI__VI regSDMA0_GFX_CSA_ADDR_HI__VI; -typedef union SDMA0_GFX_CSA_ADDR_LO__VI regSDMA0_GFX_CSA_ADDR_LO__VI; -typedef union SDMA0_GFX_DOORBELL__VI regSDMA0_GFX_DOORBELL__VI; -typedef union SDMA0_GFX_DOORBELL_LOG__VI regSDMA0_GFX_DOORBELL_LOG__VI; -typedef union SDMA0_GFX_DUMMY_REG__VI regSDMA0_GFX_DUMMY_REG__VI; -typedef union SDMA0_GFX_IB_SUB_REMAIN__VI regSDMA0_GFX_IB_SUB_REMAIN__VI; -typedef union SDMA0_GFX_MIDCMD_CNTL__VI regSDMA0_GFX_MIDCMD_CNTL__VI; -typedef union SDMA0_GFX_MIDCMD_DATA0__VI regSDMA0_GFX_MIDCMD_DATA0__VI; -typedef union SDMA0_GFX_MIDCMD_DATA1__VI regSDMA0_GFX_MIDCMD_DATA1__VI; -typedef union SDMA0_GFX_MIDCMD_DATA2__VI regSDMA0_GFX_MIDCMD_DATA2__VI; -typedef union SDMA0_GFX_MIDCMD_DATA3__VI regSDMA0_GFX_MIDCMD_DATA3__VI; -typedef union SDMA0_GFX_MIDCMD_DATA4__VI regSDMA0_GFX_MIDCMD_DATA4__VI; -typedef union SDMA0_GFX_MIDCMD_DATA5__VI regSDMA0_GFX_MIDCMD_DATA5__VI; -typedef union SDMA0_GFX_PREEMPT__VI regSDMA0_GFX_PREEMPT__VI; -typedef union SDMA0_GFX_WATERMARK__VI regSDMA0_GFX_WATERMARK__VI; -typedef union SDMA0_ID__VI regSDMA0_ID__VI; -typedef union SDMA0_PERF_REG_TYPE0__VI regSDMA0_PERF_REG_TYPE0__VI; -typedef union SDMA0_PUB_REG_TYPE0__VI regSDMA0_PUB_REG_TYPE0__VI; -typedef union SDMA0_PUB_REG_TYPE1__VI regSDMA0_PUB_REG_TYPE1__VI; -typedef union SDMA0_RD_BURST_CNTL__VI regSDMA0_RD_BURST_CNTL__VI; -typedef union SDMA0_RLC0_CSA_ADDR_HI__VI regSDMA0_RLC0_CSA_ADDR_HI__VI; -typedef union SDMA0_RLC0_CSA_ADDR_LO__VI regSDMA0_RLC0_CSA_ADDR_LO__VI; -typedef union SDMA0_RLC0_DUMMY_REG__VI regSDMA0_RLC0_DUMMY_REG__VI; -typedef union SDMA0_RLC0_IB_SUB_REMAIN__VI regSDMA0_RLC0_IB_SUB_REMAIN__VI; -typedef union SDMA0_RLC0_MIDCMD_CNTL__VI regSDMA0_RLC0_MIDCMD_CNTL__VI; -typedef union SDMA0_RLC0_MIDCMD_DATA0__VI regSDMA0_RLC0_MIDCMD_DATA0__VI; -typedef union SDMA0_RLC0_MIDCMD_DATA1__VI regSDMA0_RLC0_MIDCMD_DATA1__VI; -typedef union SDMA0_RLC0_MIDCMD_DATA2__VI regSDMA0_RLC0_MIDCMD_DATA2__VI; -typedef union SDMA0_RLC0_MIDCMD_DATA3__VI regSDMA0_RLC0_MIDCMD_DATA3__VI; -typedef union SDMA0_RLC0_MIDCMD_DATA4__VI regSDMA0_RLC0_MIDCMD_DATA4__VI; -typedef union SDMA0_RLC0_MIDCMD_DATA5__VI regSDMA0_RLC0_MIDCMD_DATA5__VI; -typedef union SDMA0_RLC0_PREEMPT__VI regSDMA0_RLC0_PREEMPT__VI; -typedef union SDMA0_RLC0_WATERMARK__VI regSDMA0_RLC0_WATERMARK__VI; -typedef union SDMA0_RLC1_CSA_ADDR_HI__VI regSDMA0_RLC1_CSA_ADDR_HI__VI; -typedef union SDMA0_RLC1_CSA_ADDR_LO__VI regSDMA0_RLC1_CSA_ADDR_LO__VI; -typedef union SDMA0_RLC1_DUMMY_REG__VI regSDMA0_RLC1_DUMMY_REG__VI; -typedef union SDMA0_RLC1_IB_SUB_REMAIN__VI regSDMA0_RLC1_IB_SUB_REMAIN__VI; -typedef union SDMA0_RLC1_MIDCMD_CNTL__VI regSDMA0_RLC1_MIDCMD_CNTL__VI; -typedef union SDMA0_RLC1_MIDCMD_DATA0__VI regSDMA0_RLC1_MIDCMD_DATA0__VI; -typedef union SDMA0_RLC1_MIDCMD_DATA1__VI regSDMA0_RLC1_MIDCMD_DATA1__VI; -typedef union SDMA0_RLC1_MIDCMD_DATA2__VI regSDMA0_RLC1_MIDCMD_DATA2__VI; -typedef union SDMA0_RLC1_MIDCMD_DATA3__VI regSDMA0_RLC1_MIDCMD_DATA3__VI; -typedef union SDMA0_RLC1_MIDCMD_DATA4__VI regSDMA0_RLC1_MIDCMD_DATA4__VI; -typedef union SDMA0_RLC1_MIDCMD_DATA5__VI regSDMA0_RLC1_MIDCMD_DATA5__VI; -typedef union SDMA0_RLC1_PREEMPT__VI regSDMA0_RLC1_PREEMPT__VI; -typedef union SDMA0_RLC1_WATERMARK__VI regSDMA0_RLC1_WATERMARK__VI; -typedef union SDMA0_STATUS2_REG__VI regSDMA0_STATUS2_REG__VI; -typedef union SDMA0_VERSION__VI regSDMA0_VERSION__VI; -typedef union SDMA0_VF_ENABLE__VI regSDMA0_VF_ENABLE__VI; -typedef union SDMA0_VIRT_RESET_REQ__VI regSDMA0_VIRT_RESET_REQ__VI; -typedef union SDMA0_VM_CNTL__VI regSDMA0_VM_CNTL__VI; -typedef union SDMA0_VM_CTX_CNTL__VI regSDMA0_VM_CTX_CNTL__VI; -typedef union SDMA0_VM_CTX_HI__VI regSDMA0_VM_CTX_HI__VI; -typedef union SDMA0_VM_CTX_LO__VI regSDMA0_VM_CTX_LO__VI; -typedef union SDMA1_ACTIVE_FCN_ID__VI regSDMA1_ACTIVE_FCN_ID__VI; -typedef union SDMA1_ATOMIC_CNTL__VI regSDMA1_ATOMIC_CNTL__VI; -typedef union SDMA1_ATOMIC_PREOP_HI__VI regSDMA1_ATOMIC_PREOP_HI__VI; -typedef union SDMA1_ATOMIC_PREOP_LO__VI regSDMA1_ATOMIC_PREOP_LO__VI; -typedef union SDMA1_BA_THRESHOLD__VI regSDMA1_BA_THRESHOLD__VI; -typedef union SDMA1_CONTEXT_REG_TYPE0__VI regSDMA1_CONTEXT_REG_TYPE0__VI; -typedef union SDMA1_CONTEXT_REG_TYPE1__VI regSDMA1_CONTEXT_REG_TYPE1__VI; -typedef union SDMA1_CONTEXT_REG_TYPE2__VI regSDMA1_CONTEXT_REG_TYPE2__VI; -typedef union SDMA1_EDC_CONFIG__VI regSDMA1_EDC_CONFIG__VI; -typedef union SDMA1_GFX_CSA_ADDR_HI__VI regSDMA1_GFX_CSA_ADDR_HI__VI; -typedef union SDMA1_GFX_CSA_ADDR_LO__VI regSDMA1_GFX_CSA_ADDR_LO__VI; -typedef union SDMA1_GFX_DOORBELL__VI regSDMA1_GFX_DOORBELL__VI; -typedef union SDMA1_GFX_DOORBELL_LOG__VI regSDMA1_GFX_DOORBELL_LOG__VI; -typedef union SDMA1_GFX_DUMMY_REG__VI regSDMA1_GFX_DUMMY_REG__VI; -typedef union SDMA1_GFX_IB_SUB_REMAIN__VI regSDMA1_GFX_IB_SUB_REMAIN__VI; -typedef union SDMA1_GFX_MIDCMD_CNTL__VI regSDMA1_GFX_MIDCMD_CNTL__VI; -typedef union SDMA1_GFX_MIDCMD_DATA0__VI regSDMA1_GFX_MIDCMD_DATA0__VI; -typedef union SDMA1_GFX_MIDCMD_DATA1__VI regSDMA1_GFX_MIDCMD_DATA1__VI; -typedef union SDMA1_GFX_MIDCMD_DATA2__VI regSDMA1_GFX_MIDCMD_DATA2__VI; -typedef union SDMA1_GFX_MIDCMD_DATA3__VI regSDMA1_GFX_MIDCMD_DATA3__VI; -typedef union SDMA1_GFX_MIDCMD_DATA4__VI regSDMA1_GFX_MIDCMD_DATA4__VI; -typedef union SDMA1_GFX_MIDCMD_DATA5__VI regSDMA1_GFX_MIDCMD_DATA5__VI; -typedef union SDMA1_GFX_PREEMPT__VI regSDMA1_GFX_PREEMPT__VI; -typedef union SDMA1_GFX_WATERMARK__VI regSDMA1_GFX_WATERMARK__VI; -typedef union SDMA1_ID__VI regSDMA1_ID__VI; -typedef union SDMA1_PERF_REG_TYPE0__VI regSDMA1_PERF_REG_TYPE0__VI; -typedef union SDMA1_PUB_REG_TYPE0__VI regSDMA1_PUB_REG_TYPE0__VI; -typedef union SDMA1_PUB_REG_TYPE1__VI regSDMA1_PUB_REG_TYPE1__VI; -typedef union SDMA1_RD_BURST_CNTL__VI regSDMA1_RD_BURST_CNTL__VI; -typedef union SDMA1_RLC0_CSA_ADDR_HI__VI regSDMA1_RLC0_CSA_ADDR_HI__VI; -typedef union SDMA1_RLC0_CSA_ADDR_LO__VI regSDMA1_RLC0_CSA_ADDR_LO__VI; -typedef union SDMA1_RLC0_DUMMY_REG__VI regSDMA1_RLC0_DUMMY_REG__VI; -typedef union SDMA1_RLC0_IB_SUB_REMAIN__VI regSDMA1_RLC0_IB_SUB_REMAIN__VI; -typedef union SDMA1_RLC0_MIDCMD_CNTL__VI regSDMA1_RLC0_MIDCMD_CNTL__VI; -typedef union SDMA1_RLC0_MIDCMD_DATA0__VI regSDMA1_RLC0_MIDCMD_DATA0__VI; -typedef union SDMA1_RLC0_MIDCMD_DATA1__VI regSDMA1_RLC0_MIDCMD_DATA1__VI; -typedef union SDMA1_RLC0_MIDCMD_DATA2__VI regSDMA1_RLC0_MIDCMD_DATA2__VI; -typedef union SDMA1_RLC0_MIDCMD_DATA3__VI regSDMA1_RLC0_MIDCMD_DATA3__VI; -typedef union SDMA1_RLC0_MIDCMD_DATA4__VI regSDMA1_RLC0_MIDCMD_DATA4__VI; -typedef union SDMA1_RLC0_MIDCMD_DATA5__VI regSDMA1_RLC0_MIDCMD_DATA5__VI; -typedef union SDMA1_RLC0_PREEMPT__VI regSDMA1_RLC0_PREEMPT__VI; -typedef union SDMA1_RLC0_WATERMARK__VI regSDMA1_RLC0_WATERMARK__VI; -typedef union SDMA1_RLC1_CSA_ADDR_HI__VI regSDMA1_RLC1_CSA_ADDR_HI__VI; -typedef union SDMA1_RLC1_CSA_ADDR_LO__VI regSDMA1_RLC1_CSA_ADDR_LO__VI; -typedef union SDMA1_RLC1_DUMMY_REG__VI regSDMA1_RLC1_DUMMY_REG__VI; -typedef union SDMA1_RLC1_IB_SUB_REMAIN__VI regSDMA1_RLC1_IB_SUB_REMAIN__VI; -typedef union SDMA1_RLC1_MIDCMD_CNTL__VI regSDMA1_RLC1_MIDCMD_CNTL__VI; -typedef union SDMA1_RLC1_MIDCMD_DATA0__VI regSDMA1_RLC1_MIDCMD_DATA0__VI; -typedef union SDMA1_RLC1_MIDCMD_DATA1__VI regSDMA1_RLC1_MIDCMD_DATA1__VI; -typedef union SDMA1_RLC1_MIDCMD_DATA2__VI regSDMA1_RLC1_MIDCMD_DATA2__VI; -typedef union SDMA1_RLC1_MIDCMD_DATA3__VI regSDMA1_RLC1_MIDCMD_DATA3__VI; -typedef union SDMA1_RLC1_MIDCMD_DATA4__VI regSDMA1_RLC1_MIDCMD_DATA4__VI; -typedef union SDMA1_RLC1_MIDCMD_DATA5__VI regSDMA1_RLC1_MIDCMD_DATA5__VI; -typedef union SDMA1_RLC1_PREEMPT__VI regSDMA1_RLC1_PREEMPT__VI; -typedef union SDMA1_RLC1_WATERMARK__VI regSDMA1_RLC1_WATERMARK__VI; -typedef union SDMA1_STATUS2_REG__VI regSDMA1_STATUS2_REG__VI; -typedef union SDMA1_VERSION__VI regSDMA1_VERSION__VI; -typedef union SDMA1_VF_ENABLE__VI regSDMA1_VF_ENABLE__VI; -typedef union SDMA1_VIRT_RESET_REQ__VI regSDMA1_VIRT_RESET_REQ__VI; -typedef union SDMA1_VM_CNTL__VI regSDMA1_VM_CNTL__VI; -typedef union SDMA1_VM_CTX_CNTL__VI regSDMA1_VM_CTX_CNTL__VI; -typedef union SDMA1_VM_CTX_HI__VI regSDMA1_VM_CTX_HI__VI; -typedef union SDMA1_VM_CTX_LO__VI regSDMA1_VM_CTX_LO__VI; -typedef union SEM_ACTIVE_FCN_ID__VI regSEM_ACTIVE_FCN_ID__VI; -typedef union SEM_MAILBOX_CLIENTCONFIG_EXTRA__VI regSEM_MAILBOX_CLIENTCONFIG_EXTRA__VI; -typedef union SEM_PERFCOUNTER0_RESULT__VI regSEM_PERFCOUNTER0_RESULT__VI; -typedef union SEM_PERFCOUNTER1_RESULT__VI regSEM_PERFCOUNTER1_RESULT__VI; -typedef union SEM_PERFMON_CNTL__VI regSEM_PERFMON_CNTL__VI; -typedef union SEM_VF_ENABLE__VI regSEM_VF_ENABLE__VI; -typedef union SEM_VIRT_RESET_REQ__VI regSEM_VIRT_RESET_REQ__VI; -typedef union SE_CAC_CGTT_CLK_CTRL__VI regSE_CAC_CGTT_CLK_CTRL__VI; -typedef union SMBUS_BACO_DUMMY__VI regSMBUS_BACO_DUMMY__VI; -typedef union SMBUS_BLKRD_CMD_CTRL0__VI regSMBUS_BLKRD_CMD_CTRL0__VI; -typedef union SMBUS_BLKRD_CMD_CTRL1__VI regSMBUS_BLKRD_CMD_CTRL1__VI; -typedef union SMBUS_BLKWR_CMD_CTRL0__VI regSMBUS_BLKWR_CMD_CTRL0__VI; -typedef union SMBUS_BLKWR_CMD_CTRL1__VI regSMBUS_BLKWR_CMD_CTRL1__VI; -typedef union SMBUS_CNTL0__VI regSMBUS_CNTL0__VI; -typedef union SMBUS_CNTL1__VI regSMBUS_CNTL1__VI; -typedef union SMBUS_TIMING_CNTL0__VI regSMBUS_TIMING_CNTL0__VI; -typedef union SMBUS_TIMING_CNTL1__VI regSMBUS_TIMING_CNTL1__VI; -typedef union SMBUS_TIMING_CNTL2__VI regSMBUS_TIMING_CNTL2__VI; -typedef union SMBUS_TRIGGER_CNTL__VI regSMBUS_TRIGGER_CNTL__VI; -typedef union SMBUS_UDID_CNTL0__VI regSMBUS_UDID_CNTL0__VI; -typedef union SMBUS_UDID_CNTL1__VI regSMBUS_UDID_CNTL1__VI; -typedef union SMBUS_UDID_CNTL2__VI regSMBUS_UDID_CNTL2__VI; -typedef union SMU_ACTIVE_FCN_ID__VI regSMU_ACTIVE_FCN_ID__VI; -typedef union SMU_AUTH_INPUT_DATA__VI regSMU_AUTH_INPUT_DATA__VI; -typedef union SMU_BIF_VDDGFX_PWR_STATUS__VI regSMU_BIF_VDDGFX_PWR_STATUS__VI; -typedef union SMU_CG_FPS_CNT__VI regSMU_CG_FPS_CNT__VI; -typedef union SMU_COMPUTE_UNIT_POWER_STATUS_HIGH__VI regSMU_COMPUTE_UNIT_POWER_STATUS_HIGH__VI; -typedef union SMU_DC_CNTL__VI regSMU_DC_CNTL__VI; -typedef union SMU_IND_DATA_0__VI regSMU_IND_DATA_0__VI; -typedef union SMU_IND_DATA_1__VI regSMU_IND_DATA_1__VI; -typedef union SMU_IND_DATA_2__VI regSMU_IND_DATA_2__VI; -typedef union SMU_IND_DATA_3__VI regSMU_IND_DATA_3__VI; -typedef union SMU_IND_DATA_4__VI regSMU_IND_DATA_4__VI; -typedef union SMU_IND_DATA_5__VI regSMU_IND_DATA_5__VI; -typedef union SMU_IND_DATA_6__VI regSMU_IND_DATA_6__VI; -typedef union SMU_IND_DATA_7__VI regSMU_IND_DATA_7__VI; -typedef union SMU_IND_INDEX_0__VI regSMU_IND_INDEX_0__VI; -typedef union SMU_IND_INDEX_1__VI regSMU_IND_INDEX_1__VI; -typedef union SMU_IND_INDEX_2__VI regSMU_IND_INDEX_2__VI; -typedef union SMU_IND_INDEX_3__VI regSMU_IND_INDEX_3__VI; -typedef union SMU_IND_INDEX_4__VI regSMU_IND_INDEX_4__VI; -typedef union SMU_IND_INDEX_5__VI regSMU_IND_INDEX_5__VI; -typedef union SMU_IND_INDEX_6__VI regSMU_IND_INDEX_6__VI; -typedef union SMU_IND_INDEX_7__VI regSMU_IND_INDEX_7__VI; -typedef union SMU_MP1_RLC2MP_RESP__VI regSMU_MP1_RLC2MP_RESP__VI; -typedef union SMU_MP1_SRBM2P_MSG_5__VI regSMU_MP1_SRBM2P_MSG_5__VI; -typedef union SMU_PM_STATUS_0__VI regSMU_PM_STATUS_0__VI; -typedef union SMU_PM_STATUS_1__VI regSMU_PM_STATUS_1__VI; -typedef union SMU_PM_STATUS_10__VI regSMU_PM_STATUS_10__VI; -typedef union SMU_PM_STATUS_100__VI regSMU_PM_STATUS_100__VI; -typedef union SMU_PM_STATUS_101__VI regSMU_PM_STATUS_101__VI; -typedef union SMU_PM_STATUS_102__VI regSMU_PM_STATUS_102__VI; -typedef union SMU_PM_STATUS_103__VI regSMU_PM_STATUS_103__VI; -typedef union SMU_PM_STATUS_104__VI regSMU_PM_STATUS_104__VI; -typedef union SMU_PM_STATUS_105__VI regSMU_PM_STATUS_105__VI; -typedef union SMU_PM_STATUS_106__VI regSMU_PM_STATUS_106__VI; -typedef union SMU_PM_STATUS_107__VI regSMU_PM_STATUS_107__VI; -typedef union SMU_PM_STATUS_108__VI regSMU_PM_STATUS_108__VI; -typedef union SMU_PM_STATUS_109__VI regSMU_PM_STATUS_109__VI; -typedef union SMU_PM_STATUS_11__VI regSMU_PM_STATUS_11__VI; -typedef union SMU_PM_STATUS_110__VI regSMU_PM_STATUS_110__VI; -typedef union SMU_PM_STATUS_111__VI regSMU_PM_STATUS_111__VI; -typedef union SMU_PM_STATUS_112__VI regSMU_PM_STATUS_112__VI; -typedef union SMU_PM_STATUS_113__VI regSMU_PM_STATUS_113__VI; -typedef union SMU_PM_STATUS_114__VI regSMU_PM_STATUS_114__VI; -typedef union SMU_PM_STATUS_115__VI regSMU_PM_STATUS_115__VI; -typedef union SMU_PM_STATUS_116__VI regSMU_PM_STATUS_116__VI; -typedef union SMU_PM_STATUS_117__VI regSMU_PM_STATUS_117__VI; -typedef union SMU_PM_STATUS_118__VI regSMU_PM_STATUS_118__VI; -typedef union SMU_PM_STATUS_119__VI regSMU_PM_STATUS_119__VI; -typedef union SMU_PM_STATUS_12__VI regSMU_PM_STATUS_12__VI; -typedef union SMU_PM_STATUS_120__VI regSMU_PM_STATUS_120__VI; -typedef union SMU_PM_STATUS_121__VI regSMU_PM_STATUS_121__VI; -typedef union SMU_PM_STATUS_122__VI regSMU_PM_STATUS_122__VI; -typedef union SMU_PM_STATUS_123__VI regSMU_PM_STATUS_123__VI; -typedef union SMU_PM_STATUS_124__VI regSMU_PM_STATUS_124__VI; -typedef union SMU_PM_STATUS_125__VI regSMU_PM_STATUS_125__VI; -typedef union SMU_PM_STATUS_126__VI regSMU_PM_STATUS_126__VI; -typedef union SMU_PM_STATUS_127__VI regSMU_PM_STATUS_127__VI; -typedef union SMU_PM_STATUS_13__VI regSMU_PM_STATUS_13__VI; -typedef union SMU_PM_STATUS_14__VI regSMU_PM_STATUS_14__VI; -typedef union SMU_PM_STATUS_15__VI regSMU_PM_STATUS_15__VI; -typedef union SMU_PM_STATUS_16__VI regSMU_PM_STATUS_16__VI; -typedef union SMU_PM_STATUS_17__VI regSMU_PM_STATUS_17__VI; -typedef union SMU_PM_STATUS_18__VI regSMU_PM_STATUS_18__VI; -typedef union SMU_PM_STATUS_19__VI regSMU_PM_STATUS_19__VI; -typedef union SMU_PM_STATUS_2__VI regSMU_PM_STATUS_2__VI; -typedef union SMU_PM_STATUS_20__VI regSMU_PM_STATUS_20__VI; -typedef union SMU_PM_STATUS_21__VI regSMU_PM_STATUS_21__VI; -typedef union SMU_PM_STATUS_22__VI regSMU_PM_STATUS_22__VI; -typedef union SMU_PM_STATUS_23__VI regSMU_PM_STATUS_23__VI; -typedef union SMU_PM_STATUS_24__VI regSMU_PM_STATUS_24__VI; -typedef union SMU_PM_STATUS_25__VI regSMU_PM_STATUS_25__VI; -typedef union SMU_PM_STATUS_26__VI regSMU_PM_STATUS_26__VI; -typedef union SMU_PM_STATUS_27__VI regSMU_PM_STATUS_27__VI; -typedef union SMU_PM_STATUS_28__VI regSMU_PM_STATUS_28__VI; -typedef union SMU_PM_STATUS_29__VI regSMU_PM_STATUS_29__VI; -typedef union SMU_PM_STATUS_3__VI regSMU_PM_STATUS_3__VI; -typedef union SMU_PM_STATUS_30__VI regSMU_PM_STATUS_30__VI; -typedef union SMU_PM_STATUS_31__VI regSMU_PM_STATUS_31__VI; -typedef union SMU_PM_STATUS_32__VI regSMU_PM_STATUS_32__VI; -typedef union SMU_PM_STATUS_33__VI regSMU_PM_STATUS_33__VI; -typedef union SMU_PM_STATUS_34__VI regSMU_PM_STATUS_34__VI; -typedef union SMU_PM_STATUS_35__VI regSMU_PM_STATUS_35__VI; -typedef union SMU_PM_STATUS_36__VI regSMU_PM_STATUS_36__VI; -typedef union SMU_PM_STATUS_37__VI regSMU_PM_STATUS_37__VI; -typedef union SMU_PM_STATUS_38__VI regSMU_PM_STATUS_38__VI; -typedef union SMU_PM_STATUS_39__VI regSMU_PM_STATUS_39__VI; -typedef union SMU_PM_STATUS_4__VI regSMU_PM_STATUS_4__VI; -typedef union SMU_PM_STATUS_40__VI regSMU_PM_STATUS_40__VI; -typedef union SMU_PM_STATUS_41__VI regSMU_PM_STATUS_41__VI; -typedef union SMU_PM_STATUS_42__VI regSMU_PM_STATUS_42__VI; -typedef union SMU_PM_STATUS_43__VI regSMU_PM_STATUS_43__VI; -typedef union SMU_PM_STATUS_44__VI regSMU_PM_STATUS_44__VI; -typedef union SMU_PM_STATUS_45__VI regSMU_PM_STATUS_45__VI; -typedef union SMU_PM_STATUS_46__VI regSMU_PM_STATUS_46__VI; -typedef union SMU_PM_STATUS_47__VI regSMU_PM_STATUS_47__VI; -typedef union SMU_PM_STATUS_48__VI regSMU_PM_STATUS_48__VI; -typedef union SMU_PM_STATUS_49__VI regSMU_PM_STATUS_49__VI; -typedef union SMU_PM_STATUS_5__VI regSMU_PM_STATUS_5__VI; -typedef union SMU_PM_STATUS_50__VI regSMU_PM_STATUS_50__VI; -typedef union SMU_PM_STATUS_51__VI regSMU_PM_STATUS_51__VI; -typedef union SMU_PM_STATUS_52__VI regSMU_PM_STATUS_52__VI; -typedef union SMU_PM_STATUS_53__VI regSMU_PM_STATUS_53__VI; -typedef union SMU_PM_STATUS_54__VI regSMU_PM_STATUS_54__VI; -typedef union SMU_PM_STATUS_55__VI regSMU_PM_STATUS_55__VI; -typedef union SMU_PM_STATUS_56__VI regSMU_PM_STATUS_56__VI; -typedef union SMU_PM_STATUS_57__VI regSMU_PM_STATUS_57__VI; -typedef union SMU_PM_STATUS_58__VI regSMU_PM_STATUS_58__VI; -typedef union SMU_PM_STATUS_59__VI regSMU_PM_STATUS_59__VI; -typedef union SMU_PM_STATUS_6__VI regSMU_PM_STATUS_6__VI; -typedef union SMU_PM_STATUS_60__VI regSMU_PM_STATUS_60__VI; -typedef union SMU_PM_STATUS_61__VI regSMU_PM_STATUS_61__VI; -typedef union SMU_PM_STATUS_62__VI regSMU_PM_STATUS_62__VI; -typedef union SMU_PM_STATUS_63__VI regSMU_PM_STATUS_63__VI; -typedef union SMU_PM_STATUS_64__VI regSMU_PM_STATUS_64__VI; -typedef union SMU_PM_STATUS_65__VI regSMU_PM_STATUS_65__VI; -typedef union SMU_PM_STATUS_66__VI regSMU_PM_STATUS_66__VI; -typedef union SMU_PM_STATUS_67__VI regSMU_PM_STATUS_67__VI; -typedef union SMU_PM_STATUS_68__VI regSMU_PM_STATUS_68__VI; -typedef union SMU_PM_STATUS_69__VI regSMU_PM_STATUS_69__VI; -typedef union SMU_PM_STATUS_7__VI regSMU_PM_STATUS_7__VI; -typedef union SMU_PM_STATUS_70__VI regSMU_PM_STATUS_70__VI; -typedef union SMU_PM_STATUS_71__VI regSMU_PM_STATUS_71__VI; -typedef union SMU_PM_STATUS_72__VI regSMU_PM_STATUS_72__VI; -typedef union SMU_PM_STATUS_73__VI regSMU_PM_STATUS_73__VI; -typedef union SMU_PM_STATUS_74__VI regSMU_PM_STATUS_74__VI; -typedef union SMU_PM_STATUS_75__VI regSMU_PM_STATUS_75__VI; -typedef union SMU_PM_STATUS_76__VI regSMU_PM_STATUS_76__VI; -typedef union SMU_PM_STATUS_77__VI regSMU_PM_STATUS_77__VI; -typedef union SMU_PM_STATUS_78__VI regSMU_PM_STATUS_78__VI; -typedef union SMU_PM_STATUS_79__VI regSMU_PM_STATUS_79__VI; -typedef union SMU_PM_STATUS_8__VI regSMU_PM_STATUS_8__VI; -typedef union SMU_PM_STATUS_80__VI regSMU_PM_STATUS_80__VI; -typedef union SMU_PM_STATUS_81__VI regSMU_PM_STATUS_81__VI; -typedef union SMU_PM_STATUS_82__VI regSMU_PM_STATUS_82__VI; -typedef union SMU_PM_STATUS_83__VI regSMU_PM_STATUS_83__VI; -typedef union SMU_PM_STATUS_84__VI regSMU_PM_STATUS_84__VI; -typedef union SMU_PM_STATUS_85__VI regSMU_PM_STATUS_85__VI; -typedef union SMU_PM_STATUS_86__VI regSMU_PM_STATUS_86__VI; -typedef union SMU_PM_STATUS_87__VI regSMU_PM_STATUS_87__VI; -typedef union SMU_PM_STATUS_88__VI regSMU_PM_STATUS_88__VI; -typedef union SMU_PM_STATUS_89__VI regSMU_PM_STATUS_89__VI; -typedef union SMU_PM_STATUS_9__VI regSMU_PM_STATUS_9__VI; -typedef union SMU_PM_STATUS_90__VI regSMU_PM_STATUS_90__VI; -typedef union SMU_PM_STATUS_91__VI regSMU_PM_STATUS_91__VI; -typedef union SMU_PM_STATUS_92__VI regSMU_PM_STATUS_92__VI; -typedef union SMU_PM_STATUS_93__VI regSMU_PM_STATUS_93__VI; -typedef union SMU_PM_STATUS_94__VI regSMU_PM_STATUS_94__VI; -typedef union SMU_PM_STATUS_95__VI regSMU_PM_STATUS_95__VI; -typedef union SMU_PM_STATUS_96__VI regSMU_PM_STATUS_96__VI; -typedef union SMU_PM_STATUS_97__VI regSMU_PM_STATUS_97__VI; -typedef union SMU_PM_STATUS_98__VI regSMU_PM_STATUS_98__VI; -typedef union SMU_PM_STATUS_99__VI regSMU_PM_STATUS_99__VI; -typedef union SMU_PSTATE_COMPUTE_UNIT_0__VI regSMU_PSTATE_COMPUTE_UNIT_0__VI; -typedef union SMU_PSTATE_COMPUTE_UNIT_1__VI regSMU_PSTATE_COMPUTE_UNIT_1__VI; -typedef union SMU_PSTATE_CONFIGURATION__VI regSMU_PSTATE_CONFIGURATION__VI; -typedef union SMU_PSTATE_CONFIGURATION_0__VI regSMU_PSTATE_CONFIGURATION_0__VI; -typedef union SMU_PSTATE_CONFIGURATION_1__VI regSMU_PSTATE_CONFIGURATION_1__VI; -typedef union SMU_PSTATE_CONFIGURATION_2__VI regSMU_PSTATE_CONFIGURATION_2__VI; -typedef union SMU_PSTATE_CONFIGURATION_3__VI regSMU_PSTATE_CONFIGURATION_3__VI; -typedef union SMU_PSTATE_CONFIGURATION_4__VI regSMU_PSTATE_CONFIGURATION_4__VI; -typedef union SMU_PSTATE_CONFIGURATION_5__VI regSMU_PSTATE_CONFIGURATION_5__VI; -typedef union SMU_PSTATE_CONFIGURATION_6__VI regSMU_PSTATE_CONFIGURATION_6__VI; -typedef union SMU_PSTATE_CONFIGURATION_7__VI regSMU_PSTATE_CONFIGURATION_7__VI; -typedef union SMU_PSTATE_CONTROL_AND_STATUS__VI regSMU_PSTATE_CONTROL_AND_STATUS__VI; -typedef union SMU_RLC_RESPONSE__VI regSMU_RLC_RESPONSE__VI; -typedef union SMU_TCON_0__VI regSMU_TCON_0__VI; -typedef union SMU_TP_SHORT_INIT__VI regSMU_TP_SHORT_INIT__VI; -typedef union SMU_UVD_CNTL__VI regSMU_UVD_CNTL__VI; -typedef union SMU_VCE_CNTL__VI regSMU_VCE_CNTL__VI; -typedef union SMU_VF_ENABLE__VI regSMU_VF_ENABLE__VI; -typedef union SMU_VIRT_RESET_REQ__VI regSMU_VIRT_RESET_REQ__VI; -typedef union SPI_COMPUTE_WF_CTX_SAVE__VI regSPI_COMPUTE_WF_CTX_SAVE__VI; -typedef union SPI_CONFIG_CNTL_2__VI regSPI_CONFIG_CNTL_2__VI; -typedef union SPI_DSM_CNTL__VI regSPI_DSM_CNTL__VI; -typedef union SPI_EDC_CNT__VI regSPI_EDC_CNT__VI; -typedef union SPI_GFX_CNTL__VI regSPI_GFX_CNTL__VI; -typedef union SPI_RESOURCE_RESERVE_CU_12__VI regSPI_RESOURCE_RESERVE_CU_12__VI; -typedef union SPI_RESOURCE_RESERVE_CU_13__VI regSPI_RESOURCE_RESERVE_CU_13__VI; -typedef union SPI_RESOURCE_RESERVE_CU_14__VI regSPI_RESOURCE_RESERVE_CU_14__VI; -typedef union SPI_RESOURCE_RESERVE_CU_15__VI regSPI_RESOURCE_RESERVE_CU_15__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_12__VI regSPI_RESOURCE_RESERVE_EN_CU_12__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_13__VI regSPI_RESOURCE_RESERVE_EN_CU_13__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_14__VI regSPI_RESOURCE_RESERVE_EN_CU_14__VI; -typedef union SPI_RESOURCE_RESERVE_EN_CU_15__VI regSPI_RESOURCE_RESERVE_EN_CU_15__VI; -typedef union SPI_START_PHASE__VI regSPI_START_PHASE__VI; -typedef union SPMI_CONFIG0_0__VI regSPMI_CONFIG0_0__VI; -typedef union SPMI_CONFIG1_0__VI regSPMI_CONFIG1_0__VI; -typedef union SPMI_FORCE_CLOCK_GATERS__VI regSPMI_FORCE_CLOCK_GATERS__VI; -typedef union SPMI_SPARE__VI regSPMI_SPARE__VI; -typedef union SPMI_SPARE_EX__VI regSPMI_SPARE_EX__VI; -typedef union SPMI_SRAM_CLK_GATER__VI regSPMI_SRAM_CLK_GATER__VI; -typedef union SQC_ATC_EDC_GATCL1_CNT__VI regSQC_ATC_EDC_GATCL1_CNT__VI; -typedef union SQC_DSM_CNTL__VI regSQC_DSM_CNTL__VI; -typedef union SQC_EDC_CNT__VI regSQC_EDC_CNT__VI; -typedef union SQC_GATCL1_CNTL__VI regSQC_GATCL1_CNTL__VI; -typedef union SQC_WRITEBACK__VI regSQC_WRITEBACK__VI; -typedef union SQ_DSM_CNTL__VI regSQ_DSM_CNTL__VI; -typedef union SQ_EDC_DED_CNT__VI regSQ_EDC_DED_CNT__VI; -typedef union SQ_EDC_INFO__VI regSQ_EDC_INFO__VI; -typedef union SQ_EDC_SEC_CNT__VI regSQ_EDC_SEC_CNT__VI; -typedef union SQ_M0_GPR_IDX_WORD__VI regSQ_M0_GPR_IDX_WORD__VI; -typedef union SQ_SMEM_0__VI regSQ_SMEM_0__VI; -typedef union SQ_SMEM_1__VI regSQ_SMEM_1__VI; -typedef union SQ_VOP_DPP__VI regSQ_VOP_DPP__VI; -typedef union SQ_VOP_SDWA__VI regSQ_VOP_SDWA__VI; -typedef union SQ_WAVE_IB_DBG1__VI regSQ_WAVE_IB_DBG1__VI; -typedef union SQ_WREXEC_EXEC_HI__VI regSQ_WREXEC_EXEC_HI__VI; -typedef union SQ_WREXEC_EXEC_LO__VI regSQ_WREXEC_EXEC_LO__VI; -typedef union SRBM_BIF_PLT0__VI regSRBM_BIF_PLT0__VI; -typedef union SRBM_BIF_PLT1__VI regSRBM_BIF_PLT1__VI; -typedef union SRBM_CPU_PLT0__VI regSRBM_CPU_PLT0__VI; -typedef union SRBM_CPU_PLT1__VI regSRBM_CPU_PLT1__VI; -typedef union SRBM_DEBUG_SNAPSHOT2__VI regSRBM_DEBUG_SNAPSHOT2__VI; -typedef union SRBM_DSM_TRIG_CNTL0__VI regSRBM_DSM_TRIG_CNTL0__VI; -typedef union SRBM_DSM_TRIG_CNTL1__VI regSRBM_DSM_TRIG_CNTL1__VI; -typedef union SRBM_DSM_TRIG_MASK0__VI regSRBM_DSM_TRIG_MASK0__VI; -typedef union SRBM_DSM_TRIG_MASK1__VI regSRBM_DSM_TRIG_MASK1__VI; -typedef union SRBM_FIREWALL_ERROR_ADDR__VI regSRBM_FIREWALL_ERROR_ADDR__VI; -typedef union SRBM_FIREWALL_ERROR_SRC__VI regSRBM_FIREWALL_ERROR_SRC__VI; -typedef union SRBM_GFX_CNTL_DATA__VI regSRBM_GFX_CNTL_DATA__VI; -typedef union SRBM_GFX_CNTL_SELECT__VI regSRBM_GFX_CNTL_SELECT__VI; -typedef union SRBM_GRBM_PLT0__VI regSRBM_GRBM_PLT0__VI; -typedef union SRBM_GRBM_PLT1__VI regSRBM_GRBM_PLT1__VI; -typedef union SRBM_ISP_CLKEN_CNTL__VI regSRBM_ISP_CLKEN_CNTL__VI; -typedef union SRBM_ISP_DOMAIN_ADDR0__VI regSRBM_ISP_DOMAIN_ADDR0__VI; -typedef union SRBM_ISP_DOMAIN_ADDR1__VI regSRBM_ISP_DOMAIN_ADDR1__VI; -typedef union SRBM_ISP_DOMAIN_ADDR2__VI regSRBM_ISP_DOMAIN_ADDR2__VI; -typedef union SRBM_MC_DOMAIN_ADDR0__VI regSRBM_MC_DOMAIN_ADDR0__VI; -typedef union SRBM_MC_DOMAIN_ADDR1__VI regSRBM_MC_DOMAIN_ADDR1__VI; -typedef union SRBM_MC_DOMAIN_ADDR2__VI regSRBM_MC_DOMAIN_ADDR2__VI; -typedef union SRBM_MC_DOMAIN_ADDR3__VI regSRBM_MC_DOMAIN_ADDR3__VI; -typedef union SRBM_MC_DOMAIN_ADDR4__VI regSRBM_MC_DOMAIN_ADDR4__VI; -typedef union SRBM_MC_DOMAIN_ADDR5__VI regSRBM_MC_DOMAIN_ADDR5__VI; -typedef union SRBM_MC_DOMAIN_ADDR6__VI regSRBM_MC_DOMAIN_ADDR6__VI; -typedef union SRBM_PEER_PLT0__VI regSRBM_PEER_PLT0__VI; -typedef union SRBM_PEER_PLT1__VI regSRBM_PEER_PLT1__VI; -typedef union SRBM_PF_PLT0__VI regSRBM_PF_PLT0__VI; -typedef union SRBM_PF_PLT1__VI regSRBM_PF_PLT1__VI; -typedef union SRBM_READ_CNTL__VI regSRBM_READ_CNTL__VI; -typedef union SRBM_READ_ERROR2__VI regSRBM_READ_ERROR2__VI; -typedef union SRBM_SDMA0_PLT0__VI regSRBM_SDMA0_PLT0__VI; -typedef union SRBM_SDMA0_PLT1__VI regSRBM_SDMA0_PLT1__VI; -typedef union SRBM_SDMA_DOMAIN_ADDR0__VI regSRBM_SDMA_DOMAIN_ADDR0__VI; -typedef union SRBM_SDMA_DOMAIN_ADDR1__VI regSRBM_SDMA_DOMAIN_ADDR1__VI; -typedef union SRBM_SDMA_DOMAIN_ADDR2__VI regSRBM_SDMA_DOMAIN_ADDR2__VI; -typedef union SRBM_SDMA_DOMAIN_ADDR3__VI regSRBM_SDMA_DOMAIN_ADDR3__VI; -typedef union SRBM_SMU_PLT0__VI regSRBM_SMU_PLT0__VI; -typedef union SRBM_SMU_PLT1__VI regSRBM_SMU_PLT1__VI; -typedef union SRBM_STATUS3__VI regSRBM_STATUS3__VI; -typedef union SRBM_SYS_DOMAIN_ADDR0__VI regSRBM_SYS_DOMAIN_ADDR0__VI; -typedef union SRBM_SYS_DOMAIN_ADDR1__VI regSRBM_SYS_DOMAIN_ADDR1__VI; -typedef union SRBM_SYS_DOMAIN_ADDR2__VI regSRBM_SYS_DOMAIN_ADDR2__VI; -typedef union SRBM_SYS_DOMAIN_ADDR3__VI regSRBM_SYS_DOMAIN_ADDR3__VI; -typedef union SRBM_SYS_DOMAIN_ADDR4__VI regSRBM_SYS_DOMAIN_ADDR4__VI; -typedef union SRBM_SYS_DOMAIN_ADDR5__VI regSRBM_SYS_DOMAIN_ADDR5__VI; -typedef union SRBM_SYS_DOMAIN_ADDR6__VI regSRBM_SYS_DOMAIN_ADDR6__VI; -typedef union SRBM_TST_PLT0__VI regSRBM_TST_PLT0__VI; -typedef union SRBM_TST_PLT1__VI regSRBM_TST_PLT1__VI; -typedef union SRBM_UVD_DOMAIN_ADDR0__VI regSRBM_UVD_DOMAIN_ADDR0__VI; -typedef union SRBM_UVD_DOMAIN_ADDR1__VI regSRBM_UVD_DOMAIN_ADDR1__VI; -typedef union SRBM_UVD_DOMAIN_ADDR2__VI regSRBM_UVD_DOMAIN_ADDR2__VI; -typedef union SRBM_VCE_DOMAIN_ADDR0__VI regSRBM_VCE_DOMAIN_ADDR0__VI; -typedef union SRBM_VCE_DOMAIN_ADDR1__VI regSRBM_VCE_DOMAIN_ADDR1__VI; -typedef union SRBM_VCE_DOMAIN_ADDR2__VI regSRBM_VCE_DOMAIN_ADDR2__VI; -typedef union SRBM_VF_ENABLE__VI regSRBM_VF_ENABLE__VI; -typedef union SRBM_VF_PLT0__VI regSRBM_VF_PLT0__VI; -typedef union SRBM_VF_PLT1__VI regSRBM_VF_PLT1__VI; -typedef union SRBM_VIRHYP_PLT0__VI regSRBM_VIRHYP_PLT0__VI; -typedef union SRBM_VIRHYP_PLT1__VI regSRBM_VIRHYP_PLT1__VI; -typedef union SRBM_VIRT_CNTL__VI regSRBM_VIRT_CNTL__VI; -typedef union SRBM_VIRT_RESET_REQ__VI regSRBM_VIRT_RESET_REQ__VI; -typedef union SRBM_VP8_CLKEN_CNTL__VI regSRBM_VP8_CLKEN_CNTL__VI; -typedef union SRBM_VP8_DOMAIN_ADDR0__VI regSRBM_VP8_DOMAIN_ADDR0__VI; -typedef union SWRST_COMMAND_0__VI regSWRST_COMMAND_0__VI; -typedef union SWRST_COMMAND_1__VI regSWRST_COMMAND_1__VI; -typedef union SWRST_COMMAND_STATUS__VI regSWRST_COMMAND_STATUS__VI; -typedef union SWRST_CONTROL_0__VI regSWRST_CONTROL_0__VI; -typedef union SWRST_CONTROL_1__VI regSWRST_CONTROL_1__VI; -typedef union SWRST_CONTROL_2__VI regSWRST_CONTROL_2__VI; -typedef union SWRST_CONTROL_3__VI regSWRST_CONTROL_3__VI; -typedef union SWRST_CONTROL_4__VI regSWRST_CONTROL_4__VI; -typedef union SWRST_CONTROL_5__VI regSWRST_CONTROL_5__VI; -typedef union SWRST_CONTROL_6__VI regSWRST_CONTROL_6__VI; -typedef union SWRST_EP_COMMAND_0__VI regSWRST_EP_COMMAND_0__VI; -typedef union SWRST_EP_CONTROL_0__VI regSWRST_EP_CONTROL_0__VI; -typedef union SWRST_GENERAL_CONTROL__VI regSWRST_GENERAL_CONTROL__VI; -typedef union SX_BLEND_OPT_CONTROL__VI regSX_BLEND_OPT_CONTROL__VI; -typedef union SX_BLEND_OPT_EPSILON__VI regSX_BLEND_OPT_EPSILON__VI; -typedef union SX_MRT0_BLEND_OPT__VI regSX_MRT0_BLEND_OPT__VI; -typedef union SX_MRT1_BLEND_OPT__VI regSX_MRT1_BLEND_OPT__VI; -typedef union SX_MRT2_BLEND_OPT__VI regSX_MRT2_BLEND_OPT__VI; -typedef union SX_MRT3_BLEND_OPT__VI regSX_MRT3_BLEND_OPT__VI; -typedef union SX_MRT4_BLEND_OPT__VI regSX_MRT4_BLEND_OPT__VI; -typedef union SX_MRT5_BLEND_OPT__VI regSX_MRT5_BLEND_OPT__VI; -typedef union SX_MRT6_BLEND_OPT__VI regSX_MRT6_BLEND_OPT__VI; -typedef union SX_MRT7_BLEND_OPT__VI regSX_MRT7_BLEND_OPT__VI; -typedef union SX_PS_DOWNCONVERT__VI regSX_PS_DOWNCONVERT__VI; -typedef union SYS_GRBM_GFX_INDEX_DATA__VI regSYS_GRBM_GFX_INDEX_DATA__VI; -typedef union SYS_GRBM_GFX_INDEX_SELECT__VI regSYS_GRBM_GFX_INDEX_SELECT__VI; -typedef union TCC_DSM_CNTL__VI regTCC_DSM_CNTL__VI; -typedef union TCC_EDC_CNT__VI regTCC_EDC_CNT__VI; -typedef union TCC_EXE_DISABLE__VI regTCC_EXE_DISABLE__VI; -typedef union TCP_ATC_EDC_GATCL1_CNT__VI regTCP_ATC_EDC_GATCL1_CNT__VI; -typedef union TCP_CNTL2__VI regTCP_CNTL2__VI; -typedef union TCP_DSM_CNTL__VI regTCP_DSM_CNTL__VI; -typedef union TCP_EDC_CNT__VI regTCP_EDC_CNT__VI; -typedef union TCP_GATCL1_CNTL__VI regTCP_GATCL1_CNTL__VI; -typedef union TCP_GATCL1_DSM_CNTL__VI regTCP_GATCL1_DSM_CNTL__VI; -typedef union TD_DSM_CNTL__VI regTD_DSM_CNTL__VI; -typedef union VGT_DISPATCH_DRAW_INDEX__VI regVGT_DISPATCH_DRAW_INDEX__VI; -typedef union VGT_TESS_DISTRIBUTION__VI regVGT_TESS_DISTRIBUTION__VI; -typedef union VM_INIT_STATUS__VI regVM_INIT_STATUS__VI; -typedef union VM_L2_CNTL4__VI regVM_L2_CNTL4__VI; -typedef union WD_DEBUG_REG10__VI regWD_DEBUG_REG10__VI; -typedef union WD_DEBUG_REG6__VI regWD_DEBUG_REG6__VI; -typedef union WD_DEBUG_REG7__VI regWD_DEBUG_REG7__VI; -typedef union WD_DEBUG_REG8__VI regWD_DEBUG_REG8__VI; -typedef union WD_DEBUG_REG9__VI regWD_DEBUG_REG9__VI; -typedef union WD_QOS__VI regWD_QOS__VI; -#endif // SI_CI_VI_MERGED_TYPEDEF_HEADER diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_pm4defs.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_pm4defs.h deleted file mode 100644 index f883c43aa5..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx8/si_pm4defs.h +++ /dev/null @@ -1,2408 +0,0 @@ -/* -*************************************************************************************************** -* -* Trade secret of Advanced Micro Devices, Inc. -* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against inadvertent publication and -* does not imply publication or any waiver of confidentiality. The year included in the foregoing -* notice is the year of creation of the work. -* -*************************************************************************************************** -*/ - -#ifndef _SI_PM4DEFS_H_ -#define _SI_PM4DEFS_H_ - -#include "si_ci_vi_merged_typedef.h" - -/****************************************************************************** -* -* si_pm4defs.h -* -* SI PM4 definitions, typedefs, and enumerations. -* -******************************************************************************/ - -// File version information -#define SI_PM4DEFS_VERSION_MAJOR 1 -#define SI_PM4DEFS_VERSION_MINOR 1 - -// PM4 command shifts -#define PM4_PREDICATE_SHIFT 0 -#define PM4_SHADERTYPE_SHIFT 1 -#define PM4_OP_SHIFT 8 -#define PM4_COUNT_SHIFT 16 -#define PM4_TYPE_SHIFT 30 -#define PM4_T0_ONE_REG_WR_SHIFT 15 -#define PM4_T0_INDX_SHIFT 0 - -// PM4 command control settings -#define PM4_T0_NO_INCR (1 << PM4_T0_ONE_REG_WR_SHIFT) - -// ROLL_CONTEXT defines -#define PM4_SEL_8_CP_STATE 0 -#define PM4_SEL_BLOCK_STATE 1 - -/** -*************************************************************************************************** -* @brief This enum defines the Shader types supported in PM4 type 3 header -*************************************************************************************************** -*/ -enum PM4ShaderType { - ShaderGraphics = 0, ///< Graphics shader - ShaderCompute = 1 ///< Compute shader -}; - -/** -*************************************************************************************************** -* @brief This enum defines the predicate value supported in PM4 type 3 header -*************************************************************************************************** -*/ -enum PM4Predicate { - PredDisable = 0, ///< Predicate disabled - PredEnable = 1 ///< Predicate enabled -}; - -// PM4 type 3 header macro for creating a PM4 type 3 header -#define PM4_TYPE_3_HDR(opCode, count, shaderType, predicate) \ - ((unsigned int)(predicate << PM4_PREDICATE_SHIFT) | (shaderType << PM4_SHADERTYPE_SHIFT) | \ - (PM4_TYPE_3 << PM4_TYPE_SHIFT) | ((count - 2) << PM4_COUNT_SHIFT) | (opCode << PM4_OP_SHIFT)) - - -// PM4 type 0 header macros -#define PM4_TYPE_0_HDR(Reg0, nWrites) \ - ((((unsigned int)(nWrites)-1) << PM4_COUNT_SHIFT) | ((Reg0) << PM4_T0_INDX_SHIFT)) - -// RJVR: This macro needs to be modified to use Type 3 ONE_REG_WRITE. -#define PM4_TYPE_0_HDR_NO_INCR(Reg0, nWrites) \ - ((((unsigned int)(nWrites)-1) << PM4_COUNT_SHIFT) | ((Reg0) << PM4_T0_INDX_SHIFT) | \ - PM4_T0_NO_INCR) - -// PM4 type 2 NOP -#define PM4_TYPE_2_NOP (PM4_TYPE_2 << PM4_TYPE_SHIFT) - - -// PM4 1-DWORD size type 3 NOP for VI. -// Type 2 NOP support has been dropped from the CP, a new type 3 NOP should be used in it's place. -// The CP added a 1-DWORD type 3 NOP designated by a special count set to 0x3FFF. -///@note 0x3FFF + 2 to account for the PM4_TYPE_3_HDR macro's -2 of the count -#define PM4_TYPE_3_NOP_VI PM4_TYPE_3_HDR(IT_NOP, 0x3FFF + 2, ShaderGraphics, PredDisable) - -//------------------------------------------------------------------------------------------------- - -typedef union _PM4_TYPE_0_HEADER { - struct { - unsigned int base : 16; ///< the DWORD Memory-mapped address - unsigned int count : 14; ///< count of DWORDs in the *information* body (N - 1 for N dwords) - unsigned int type : 2; ///< packet identifier. It should be 0 for type 0 packets. - }; - unsigned int u32All; - -} PM4_TYPE_0_HEADER; - -//------------------------------------------------------------------------------------------------- - -typedef union PM4_TYPE_3_HEADER { - struct { - unsigned int predicate : 1; ///< predicated version of packet when set - unsigned int shaderType : 1; ///< 0: Graphics, 1: Compute Shader - unsigned int reserved1 : 6; ///< reserved - unsigned int opcode : 8; ///< IT opcode - unsigned int count : 14; ///< number of DWORDs - 1 in the information body. - unsigned int type : 2; ///< packet identifier. It should be 3 for type 3 packets - }; - unsigned int u32All; -} PM4_TYPE_3_HEADER; - -//------------------------------------------------------------------------------------------------- - -///@note Naming this union CONTEXT_CONTROL results in the following compiler error which MSDN says -/// will not be fixed. -/// fatal error C1001: An internal error has occurred in the compiler. -/// (compiler file 'msc1.cpp', line 1393) -// To work around this problem, try simplifying or changing the program near the -// locations listed above. -typedef union _CONTEXT_CONTROL_ENABLE { - struct { - unsigned int enableSingleCntxConfigReg : 1; ///< single context config reg - unsigned int enableMultiCntxRenderReg : 1; ///< multi context render state reg - unsigned int reserved1 : 13; ///< reserved - unsigned int enableUserConfigReg__CI : 1; ///< User Config Reg on CI(reserved for SI) - unsigned int enableGfxSHReg : 1; ///< Gfx SH Registers - unsigned int reserved2 : 7; ///< reserved - unsigned int enableCSSHReg : 1; ///< CS SH Registers - unsigned int reserved3 : 6; ///< reserved - unsigned int enableDw : 1; ///< DW enable - }; - unsigned int u32All; -} CONTEXT_CONTROL_ENABLE; - -//------------------------------------------------------------------------------------------------- - -typedef struct _PM4CMDCONTEXTCONTROL { - union { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union { - CONTEXT_CONTROL_ENABLE loadControl; ///< enable bits for loading - unsigned int ordinal2; - }; - union { - CONTEXT_CONTROL_ENABLE shadowEnable; ///< enable bits for shadowing - unsigned int ordinal3; - }; - -} PM4CMDCONTEXTCONTROL, *PPM4CMDCONTEXTCONTROL; - -//------------------------------------------------------------------------------------------------- -typedef union _LOAD_ADDRESS_HIGH { - struct { - unsigned int ADDR_HI : 16; ///< bits (47:32) for the block in Memory from where - ///< the CP will fetch the state - unsigned int reserved1 : 15; ///< reserved - unsigned int WAIT_IDLE : 1; ///< if set the CP will wait for the graphics pipe to - ///< be idle by writing to the GRBM Wait Until register - ///< with “Wait for 3D idle" - }; - unsigned int u32All; -} LOAD_ADDRESS_HIGH; - -//------------------------------------------------------------------------------------------------- - -// PM4CMDLOADDATA can be used with the following opcodes -// - IT_LOAD_CONFIG_REG -// - IT_LOAD_CONTEXT_REG -// - IT_LOAD_SH_REG -typedef struct _PM4CMDLOADDATA { - union { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union { - unsigned int addrLo; ///< low 32 address bits for the block in memory from where - ///< the CP will fetch the state - unsigned int ordinal2; - }; - union { - LOAD_ADDRESS_HIGH addrHi; - unsigned int ordinal3; - }; - union { - unsigned int regOffset; ///< offset in DWords from the register base address - unsigned int ordinal4; - }; - union { - unsigned int numDwords; ///< number of DWords that the CP will fetch and write - ///< into the chip. A value of zero will fetch nothing - unsigned int ordinal5; - }; - // This is a variable length packet. So, based on size in header, the layout following this - // looks as follows (offser/numDwords pairs). - // unsigned int offset1; - // unsigned int numDwords1; - // ... - // unsigned int offsetN; - // unsigned int numDwordsN; - -} PM4CMDLOADDATA, *PPM4CMDLOADDATA; - -//------------------------------------------------------------------------------------------------- - -// PM4CMDSETDATA can be used with the following opcodes: -// -// - IT_SET_CONFIG_REG -// - IT_SET_CONTEXT_REG -// - IT_SET_CONTEXT_REG_INDIRECT -// - IT_SET_SH_REG -typedef struct _PM4CMDSETDATA { - union { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union { - unsigned int regOffset; ///< offset in DWords from the register base address - unsigned int ordinal2; - }; - // This is a variable length packet. So, based on size in header, the layout following this - // looks as follows: - // Data for SET_CONTEXT_REG - // DW Offset into Patch table for SET_CONTEXT_REG_INDIRECT - // unsigned int data0; - // ... - // unsigned int dataN; - -} PM4CMDSETDATA, *PPM4CMDSETDATA; - -//------------------------------------------------------------------------------------------------- - -typedef struct _PM4CMDNOP { - union { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; -} PM4CMDNOP, *PPM4CMDNOP; - -//------------------------------------------------------------------------------------------------- - -typedef struct _PM4CMDDRAWINDEXOFFSET2 { - union { - PM4_TYPE_3_HEADER header; ///
    -* -* -* (c) 2000 ATI Technologies Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against -* inadvertent publication and does not imply publication or any waiver -* of confidentiality. The year included in the foregoing notice is the -* year of creation of the work. -* -*/ - -namespace pm4_profile { -namespace gfx9 { - -#ifndef _DRIVER_BUILD -#ifndef GL_ZERO -#define GL__ZERO BLEND_ZERO -#define GL__ONE BLEND_ONE -#define GL__SRC_COLOR BLEND_SRC_COLOR -#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR -#define GL__DST_COLOR BLEND_DST_COLOR -#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR -#define GL__SRC_ALPHA BLEND_SRC_ALPHA -#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA -#define GL__DST_ALPHA BLEND_DST_ALPHA -#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA -#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE -#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR -#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR -#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA -#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA -#endif -#endif - -/******************************************************* - * ATS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * XPB DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RPB DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RSMU_GENERIC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RSMU_GC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_RST DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_MISC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_RAS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_BX DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_EPF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_EPVF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RCC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RCC_DWN DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RCC_DWNP DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_SWDS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_RC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RCC_SHADOW_REG DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RCC_EP DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GDC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GDC_RAS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * NBIF_SION DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RCC_STRAP DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GDC_RST DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * PCIEMSIX DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RCC_PFC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * IH DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SEM DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SDMA DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SDMA1 DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP0_CRU DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP0_CRU_SMN DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP0_CRU_RSMU DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP0_MMU DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP0_HUBIF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP1_CRU DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP1_CRU_SMN DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP1_CRU_RSMU DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP1_MMU DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP1_HUBIF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP_HUBIF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP_HUBIF_NB DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP_SMNIF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP_ROM DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * MP_DMAC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SMUIO DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GDS DATA_TYPE Enums - *******************************************************/ - -#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H -#define ENUMS_GDS_PERFCOUNT_SELECT_H -typedef enum GDS_PERFCOUNT_SELECT { - GDS_PERF_SEL_DS_ADDR_CONFL = 0, - GDS_PERF_SEL_DS_BANK_CONFL = 1, - GDS_PERF_SEL_WBUF_FLUSH = 2, - GDS_PERF_SEL_WR_COMP = 3, - GDS_PERF_SEL_WBUF_WR = 4, - GDS_PERF_SEL_RBUF_HIT = 5, - GDS_PERF_SEL_RBUF_MISS = 6, - GDS_PERF_SEL_SE0_SH0_NORET = 7, - GDS_PERF_SEL_SE0_SH0_RET = 8, - GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, - GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, - GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, - GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, - GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, - GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, - GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, - GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, - GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, - GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, - GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, - GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, - GDS_PERF_SEL_SE0_SH1_NORET = 21, - GDS_PERF_SEL_SE0_SH1_RET = 22, - GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, - GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, - GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, - GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, - GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, - GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, - GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, - GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, - GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, - GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, - GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, - GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, - GDS_PERF_SEL_SE1_SH0_NORET = 35, - GDS_PERF_SEL_SE1_SH0_RET = 36, - GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, - GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, - GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, - GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, - GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, - GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, - GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, - GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, - GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, - GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, - GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, - GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, - GDS_PERF_SEL_SE1_SH1_NORET = 49, - GDS_PERF_SEL_SE1_SH1_RET = 50, - GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, - GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, - GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, - GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, - GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, - GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, - GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, - GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, - GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, - GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, - GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, - GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, - GDS_PERF_SEL_SE2_SH0_NORET = 63, - GDS_PERF_SEL_SE2_SH0_RET = 64, - GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, - GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, - GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, - GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, - GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, - GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, - GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, - GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, - GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, - GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, - GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, - GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, - GDS_PERF_SEL_SE2_SH1_NORET = 77, - GDS_PERF_SEL_SE2_SH1_RET = 78, - GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, - GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, - GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, - GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, - GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, - GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, - GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, - GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, - GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, - GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, - GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, - GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, - GDS_PERF_SEL_SE3_SH0_NORET = 91, - GDS_PERF_SEL_SE3_SH0_RET = 92, - GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, - GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, - GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, - GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, - GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, - GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, - GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, - GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, - GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, - GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, - GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, - GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, - GDS_PERF_SEL_SE3_SH1_NORET = 105, - GDS_PERF_SEL_SE3_SH1_RET = 106, - GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, - GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, - GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, - GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, - GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, - GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, - GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, - GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, - GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, - GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, - GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, - GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, - GDS_PERF_SEL_GWS_RELEASED = 119, - GDS_PERF_SEL_GWS_BYPASS = 120, -} GDS_PERFCOUNT_SELECT; -#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ - -/******************************************************* - * CB DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * TC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GC_CAC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RLC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SPI DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SQ DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * COMP DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VGT DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GB DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * TP DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * TCC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GRBM DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * CP DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SQ_UC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * DIDT DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SX DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * DB DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * TA DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * PA DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RMI DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * DBGU_GFX DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GRBM_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GDS_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RLC_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * CB_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * PA_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * PC_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SX_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SC_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * WD_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * IA_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VGT_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * SPI_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * CPC_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * CPG_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * CPF_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * BCI_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * RMI_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * DB_DEBUGBUS DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * ATCL2 DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * ATCL2PFCNTR DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * ATCL2PFCNTL DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VML2PF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VML2VC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VML2PL DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VML2PR DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VMSHAREDHV DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VMSHAREDPF DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * VMSHAREDVC DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * GC_EA DATA_TYPE Enums - *******************************************************/ - -/******************************************************* - * Chip Enums - *******************************************************/ - -/* - * SurfaceEndian enum - */ - -typedef enum SurfaceEndian { - ENDIAN_NONE = 0x00000000, - ENDIAN_8IN16 = 0x00000001, - ENDIAN_8IN32 = 0x00000002, - ENDIAN_8IN64 = 0x00000003, -} SurfaceEndian; - -/* - * ArrayMode enum - */ - -typedef enum ArrayMode { - ARRAY_LINEAR_GENERAL = 0x00000000, - ARRAY_LINEAR_ALIGNED = 0x00000001, - ARRAY_1D_TILED_THIN1 = 0x00000002, - ARRAY_1D_TILED_THICK = 0x00000003, - ARRAY_2D_TILED_THIN1 = 0x00000004, - ARRAY_PRT_TILED_THIN1 = 0x00000005, - ARRAY_PRT_2D_TILED_THIN1 = 0x00000006, - ARRAY_2D_TILED_THICK = 0x00000007, - ARRAY_2D_TILED_XTHICK = 0x00000008, - ARRAY_PRT_TILED_THICK = 0x00000009, - ARRAY_PRT_2D_TILED_THICK = 0x0000000a, - ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b, - ARRAY_3D_TILED_THIN1 = 0x0000000c, - ARRAY_3D_TILED_THICK = 0x0000000d, - ARRAY_3D_TILED_XTHICK = 0x0000000e, - ARRAY_PRT_3D_TILED_THICK = 0x0000000f, -} ArrayMode; - -/* - * NumPipes enum - */ - -typedef enum NumPipes { - ADDR_CONFIG_1_PIPE = 0x00000000, - ADDR_CONFIG_2_PIPE = 0x00000001, - ADDR_CONFIG_4_PIPE = 0x00000002, - ADDR_CONFIG_8_PIPE = 0x00000003, - ADDR_CONFIG_16_PIPE = 0x00000004, - ADDR_CONFIG_32_PIPE = 0x00000005, -} NumPipes; - -/* - * NumBanksConfig enum - */ - -typedef enum NumBanksConfig { - ADDR_CONFIG_1_BANK = 0x00000000, - ADDR_CONFIG_2_BANK = 0x00000001, - ADDR_CONFIG_4_BANK = 0x00000002, - ADDR_CONFIG_8_BANK = 0x00000003, - ADDR_CONFIG_16_BANK = 0x00000004, -} NumBanksConfig; - -/* - * PipeInterleaveSize enum - */ - -typedef enum PipeInterleaveSize { - ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, - ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, - ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, - ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, -} PipeInterleaveSize; - -/* - * BankInterleaveSize enum - */ - -typedef enum BankInterleaveSize { - ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, - ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, - ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, - ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, -} BankInterleaveSize; - -/* - * NumShaderEngines enum - */ - -typedef enum NumShaderEngines { - ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, - ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, - ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, - ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, -} NumShaderEngines; - -/* - * NumRbPerShaderEngine enum - */ - -typedef enum NumRbPerShaderEngine { - ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, - ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, - ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, -} NumRbPerShaderEngine; - -/* - * NumGPUs enum - */ - -typedef enum NumGPUs { - ADDR_CONFIG_1_GPU = 0x00000000, - ADDR_CONFIG_2_GPU = 0x00000001, - ADDR_CONFIG_4_GPU = 0x00000002, - ADDR_CONFIG_8_GPU = 0x00000003, -} NumGPUs; - -/* - * NumMaxCompressedFragments enum - */ - -typedef enum NumMaxCompressedFragments { - ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, - ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, - ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, - ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, -} NumMaxCompressedFragments; - -/* - * ShaderEngineTileSize enum - */ - -typedef enum ShaderEngineTileSize { - ADDR_CONFIG_SE_TILE_16 = 0x00000000, - ADDR_CONFIG_SE_TILE_32 = 0x00000001, -} ShaderEngineTileSize; - -/* - * MultiGPUTileSize enum - */ - -typedef enum MultiGPUTileSize { - ADDR_CONFIG_GPU_TILE_16 = 0x00000000, - ADDR_CONFIG_GPU_TILE_32 = 0x00000001, - ADDR_CONFIG_GPU_TILE_64 = 0x00000002, - ADDR_CONFIG_GPU_TILE_128 = 0x00000003, -} MultiGPUTileSize; - -/* - * RowSize enum - */ - -typedef enum RowSize { - ADDR_CONFIG_1KB_ROW = 0x00000000, - ADDR_CONFIG_2KB_ROW = 0x00000001, - ADDR_CONFIG_4KB_ROW = 0x00000002, -} RowSize; - -/* - * NumLowerPipes enum - */ - -typedef enum NumLowerPipes { - ADDR_CONFIG_1_LOWER_PIPES = 0x00000000, - ADDR_CONFIG_2_LOWER_PIPES = 0x00000001, -} NumLowerPipes; - -/* - * ColorTransform enum - */ - -typedef enum ColorTransform { - DCC_CT_AUTO = 0x00000000, - DCC_CT_NONE = 0x00000001, - ABGR_TO_A_BG_G_RB = 0x00000002, - BGRA_TO_BG_G_RB_A = 0x00000003, -} ColorTransform; - -/* - * CompareRef enum - */ - -typedef enum CompareRef { - REF_NEVER = 0x00000000, - REF_LESS = 0x00000001, - REF_EQUAL = 0x00000002, - REF_LEQUAL = 0x00000003, - REF_GREATER = 0x00000004, - REF_NOTEQUAL = 0x00000005, - REF_GEQUAL = 0x00000006, - REF_ALWAYS = 0x00000007, -} CompareRef; - -/* - * ReadSize enum - */ - -typedef enum ReadSize { - READ_256_BITS = 0x00000000, - READ_512_BITS = 0x00000001, -} ReadSize; - -/* - * DepthFormat enum - */ - -typedef enum DepthFormat { - DEPTH_INVALID = 0x00000000, - DEPTH_16 = 0x00000001, - DEPTH_X8_24 = 0x00000002, - DEPTH_8_24 = 0x00000003, - DEPTH_X8_24_FLOAT = 0x00000004, - DEPTH_8_24_FLOAT = 0x00000005, - DEPTH_32_FLOAT = 0x00000006, - DEPTH_X24_8_32_FLOAT = 0x00000007, -} DepthFormat; - -/* - * ZFormat enum - */ - -typedef enum ZFormat { - Z_INVALID = 0x00000000, - Z_16 = 0x00000001, - Z_24 = 0x00000002, - Z_32_FLOAT = 0x00000003, -} ZFormat; - -/* - * StencilFormat enum - */ - -typedef enum StencilFormat { - STENCIL_INVALID = 0x00000000, - STENCIL_8 = 0x00000001, -} StencilFormat; - -/* - * CmaskMode enum - */ - -typedef enum CmaskMode { - CMASK_CLEAR_NONE = 0x00000000, - CMASK_CLEAR_ONE = 0x00000001, - CMASK_CLEAR_ALL = 0x00000002, - CMASK_ANY_EXPANDED = 0x00000003, - CMASK_ALPHA0_FRAG1 = 0x00000004, - CMASK_ALPHA0_FRAG2 = 0x00000005, - CMASK_ALPHA0_FRAG4 = 0x00000006, - CMASK_ALPHA0_FRAGS = 0x00000007, - CMASK_ALPHA1_FRAG1 = 0x00000008, - CMASK_ALPHA1_FRAG2 = 0x00000009, - CMASK_ALPHA1_FRAG4 = 0x0000000a, - CMASK_ALPHA1_FRAGS = 0x0000000b, - CMASK_ALPHAX_FRAG1 = 0x0000000c, - CMASK_ALPHAX_FRAG2 = 0x0000000d, - CMASK_ALPHAX_FRAG4 = 0x0000000e, - CMASK_ALPHAX_FRAGS = 0x0000000f, -} CmaskMode; - -/* - * QuadExportFormat enum - */ - -typedef enum QuadExportFormat { - EXPORT_UNUSED = 0x00000000, - EXPORT_32_R = 0x00000001, - EXPORT_32_GR = 0x00000002, - EXPORT_32_AR = 0x00000003, - EXPORT_FP16_ABGR = 0x00000004, - EXPORT_UNSIGNED16_ABGR = 0x00000005, - EXPORT_SIGNED16_ABGR = 0x00000006, - EXPORT_32_ABGR = 0x00000007, - EXPORT_32BPP_8PIX = 0x00000008, - EXPORT_16_16_UNSIGNED_8PIX = 0x00000009, - EXPORT_16_16_SIGNED_8PIX = 0x0000000a, - EXPORT_16_16_FLOAT_8PIX = 0x0000000b, -} QuadExportFormat; - -/* - * QuadExportFormatOld enum - */ - -typedef enum QuadExportFormatOld { - EXPORT_4P_32BPC_ABGR = 0x00000000, - EXPORT_4P_16BPC_ABGR = 0x00000001, - EXPORT_4P_32BPC_GR = 0x00000002, - EXPORT_4P_32BPC_AR = 0x00000003, - EXPORT_2P_32BPC_ABGR = 0x00000004, - EXPORT_8P_32BPC_R = 0x00000005, -} QuadExportFormatOld; - -/* - * ColorFormat enum - */ - -typedef enum ColorFormat { - COLOR_INVALID = 0x00000000, - COLOR_8 = 0x00000001, - COLOR_16 = 0x00000002, - COLOR_8_8 = 0x00000003, - COLOR_32 = 0x00000004, - COLOR_16_16 = 0x00000005, - COLOR_10_11_11 = 0x00000006, - COLOR_11_11_10 = 0x00000007, - COLOR_10_10_10_2 = 0x00000008, - COLOR_2_10_10_10 = 0x00000009, - COLOR_8_8_8_8 = 0x0000000a, - COLOR_32_32 = 0x0000000b, - COLOR_16_16_16_16 = 0x0000000c, - COLOR_RESERVED_13 = 0x0000000d, - COLOR_32_32_32_32 = 0x0000000e, - COLOR_RESERVED_15 = 0x0000000f, - COLOR_5_6_5 = 0x00000010, - COLOR_1_5_5_5 = 0x00000011, - COLOR_5_5_5_1 = 0x00000012, - COLOR_4_4_4_4 = 0x00000013, - COLOR_8_24 = 0x00000014, - COLOR_24_8 = 0x00000015, - COLOR_X24_8_32_FLOAT = 0x00000016, - COLOR_RESERVED_23 = 0x00000017, - COLOR_RESERVED_24 = 0x00000018, - COLOR_RESERVED_25 = 0x00000019, - COLOR_RESERVED_26 = 0x0000001a, - COLOR_RESERVED_27 = 0x0000001b, - COLOR_RESERVED_28 = 0x0000001c, - COLOR_RESERVED_29 = 0x0000001d, - COLOR_RESERVED_30 = 0x0000001e, - COLOR_2_10_10_10_6E4 = 0x0000001f, -} ColorFormat; - -/* - * SurfaceFormat enum - */ - -typedef enum SurfaceFormat { - FMT_INVALID = 0x00000000, - FMT_8 = 0x00000001, - FMT_16 = 0x00000002, - FMT_8_8 = 0x00000003, - FMT_32 = 0x00000004, - FMT_16_16 = 0x00000005, - FMT_10_11_11 = 0x00000006, - FMT_11_11_10 = 0x00000007, - FMT_10_10_10_2 = 0x00000008, - FMT_2_10_10_10 = 0x00000009, - FMT_8_8_8_8 = 0x0000000a, - FMT_32_32 = 0x0000000b, - FMT_16_16_16_16 = 0x0000000c, - FMT_32_32_32 = 0x0000000d, - FMT_32_32_32_32 = 0x0000000e, - FMT_RESERVED_4 = 0x0000000f, - FMT_5_6_5 = 0x00000010, - FMT_1_5_5_5 = 0x00000011, - FMT_5_5_5_1 = 0x00000012, - FMT_4_4_4_4 = 0x00000013, - FMT_8_24 = 0x00000014, - FMT_24_8 = 0x00000015, - FMT_X24_8_32_FLOAT = 0x00000016, - FMT_RESERVED_33 = 0x00000017, - FMT_11_11_10_FLOAT = 0x00000018, - FMT_16_FLOAT = 0x00000019, - FMT_32_FLOAT = 0x0000001a, - FMT_16_16_FLOAT = 0x0000001b, - FMT_8_24_FLOAT = 0x0000001c, - FMT_24_8_FLOAT = 0x0000001d, - FMT_32_32_FLOAT = 0x0000001e, - FMT_10_11_11_FLOAT = 0x0000001f, - FMT_16_16_16_16_FLOAT = 0x00000020, - FMT_3_3_2 = 0x00000021, - FMT_6_5_5 = 0x00000022, - FMT_32_32_32_32_FLOAT = 0x00000023, - FMT_RESERVED_36 = 0x00000024, - FMT_1 = 0x00000025, - FMT_1_REVERSED = 0x00000026, - FMT_GB_GR = 0x00000027, - FMT_BG_RG = 0x00000028, - FMT_32_AS_8 = 0x00000029, - FMT_32_AS_8_8 = 0x0000002a, - FMT_5_9_9_9_SHAREDEXP = 0x0000002b, - FMT_8_8_8 = 0x0000002c, - FMT_16_16_16 = 0x0000002d, - FMT_16_16_16_FLOAT = 0x0000002e, - FMT_4_4 = 0x0000002f, - FMT_32_32_32_FLOAT = 0x00000030, - FMT_BC1 = 0x00000031, - FMT_BC2 = 0x00000032, - FMT_BC3 = 0x00000033, - FMT_BC4 = 0x00000034, - FMT_BC5 = 0x00000035, - FMT_BC6 = 0x00000036, - FMT_BC7 = 0x00000037, - FMT_32_AS_32_32_32_32 = 0x00000038, - FMT_APC3 = 0x00000039, - FMT_APC4 = 0x0000003a, - FMT_APC5 = 0x0000003b, - FMT_APC6 = 0x0000003c, - FMT_APC7 = 0x0000003d, - FMT_CTX1 = 0x0000003e, - FMT_RESERVED_63 = 0x0000003f, -} SurfaceFormat; - -/* - * BUF_DATA_FORMAT enum - */ - -typedef enum BUF_DATA_FORMAT { - BUF_DATA_FORMAT_INVALID = 0x00000000, - BUF_DATA_FORMAT_8 = 0x00000001, - BUF_DATA_FORMAT_16 = 0x00000002, - BUF_DATA_FORMAT_8_8 = 0x00000003, - BUF_DATA_FORMAT_32 = 0x00000004, - BUF_DATA_FORMAT_16_16 = 0x00000005, - BUF_DATA_FORMAT_10_11_11 = 0x00000006, - BUF_DATA_FORMAT_11_11_10 = 0x00000007, - BUF_DATA_FORMAT_10_10_10_2 = 0x00000008, - BUF_DATA_FORMAT_2_10_10_10 = 0x00000009, - BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a, - BUF_DATA_FORMAT_32_32 = 0x0000000b, - BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c, - BUF_DATA_FORMAT_32_32_32 = 0x0000000d, - BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e, - BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f, -} BUF_DATA_FORMAT; - -/* - * IMG_DATA_FORMAT enum - */ - -typedef enum IMG_DATA_FORMAT { - IMG_DATA_FORMAT_INVALID = 0x00000000, - IMG_DATA_FORMAT_8 = 0x00000001, - IMG_DATA_FORMAT_16 = 0x00000002, - IMG_DATA_FORMAT_8_8 = 0x00000003, - IMG_DATA_FORMAT_32 = 0x00000004, - IMG_DATA_FORMAT_16_16 = 0x00000005, - IMG_DATA_FORMAT_10_11_11 = 0x00000006, - IMG_DATA_FORMAT_11_11_10 = 0x00000007, - IMG_DATA_FORMAT_10_10_10_2 = 0x00000008, - IMG_DATA_FORMAT_2_10_10_10 = 0x00000009, - IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a, - IMG_DATA_FORMAT_32_32 = 0x0000000b, - IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c, - IMG_DATA_FORMAT_32_32_32 = 0x0000000d, - IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e, - IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f, - IMG_DATA_FORMAT_5_6_5 = 0x00000010, - IMG_DATA_FORMAT_1_5_5_5 = 0x00000011, - IMG_DATA_FORMAT_5_5_5_1 = 0x00000012, - IMG_DATA_FORMAT_4_4_4_4 = 0x00000013, - IMG_DATA_FORMAT_8_24 = 0x00000014, - IMG_DATA_FORMAT_24_8 = 0x00000015, - IMG_DATA_FORMAT_X24_8_32 = 0x00000016, - IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017, - IMG_DATA_FORMAT_ETC2_RGB = 0x00000018, - IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019, - IMG_DATA_FORMAT_ETC2_R = 0x0000001a, - IMG_DATA_FORMAT_ETC2_RG = 0x0000001b, - IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c, - IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d, - IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e, - IMG_DATA_FORMAT_6E4 = 0x0000001f, - IMG_DATA_FORMAT_GB_GR = 0x00000020, - IMG_DATA_FORMAT_BG_RG = 0x00000021, - IMG_DATA_FORMAT_5_9_9_9 = 0x00000022, - IMG_DATA_FORMAT_BC1 = 0x00000023, - IMG_DATA_FORMAT_BC2 = 0x00000024, - IMG_DATA_FORMAT_BC3 = 0x00000025, - IMG_DATA_FORMAT_BC4 = 0x00000026, - IMG_DATA_FORMAT_BC5 = 0x00000027, - IMG_DATA_FORMAT_BC6 = 0x00000028, - IMG_DATA_FORMAT_BC7 = 0x00000029, - IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a, - IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b, - IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c, - IMG_DATA_FORMAT_FMASK = 0x0000002d, - IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e, - IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f, - IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030, - IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031, - IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032, - IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033, - IMG_DATA_FORMAT_N_IN_16 = 0x00000034, - IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035, - IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036, - IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037, - IMG_DATA_FORMAT_RESERVED_56 = 0x00000038, - IMG_DATA_FORMAT_4_4 = 0x00000039, - IMG_DATA_FORMAT_6_5_5 = 0x0000003a, - IMG_DATA_FORMAT_S8_16 = 0x0000003b, - IMG_DATA_FORMAT_S8_32 = 0x0000003c, - IMG_DATA_FORMAT_8_AS_32 = 0x0000003d, - IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e, - IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f, -} IMG_DATA_FORMAT; - -/* - * BUF_NUM_FORMAT enum - */ - -typedef enum BUF_NUM_FORMAT { - BUF_NUM_FORMAT_UNORM = 0x00000000, - BUF_NUM_FORMAT_SNORM = 0x00000001, - BUF_NUM_FORMAT_USCALED = 0x00000002, - BUF_NUM_FORMAT_SSCALED = 0x00000003, - BUF_NUM_FORMAT_UINT = 0x00000004, - BUF_NUM_FORMAT_SINT = 0x00000005, - BUF_NUM_FORMAT_RESERVED_6 = 0x00000006, - BUF_NUM_FORMAT_FLOAT = 0x00000007, -} BUF_NUM_FORMAT; - -/* - * IMG_NUM_FORMAT enum - */ - -typedef enum IMG_NUM_FORMAT { - IMG_NUM_FORMAT_UNORM = 0x00000000, - IMG_NUM_FORMAT_SNORM = 0x00000001, - IMG_NUM_FORMAT_USCALED = 0x00000002, - IMG_NUM_FORMAT_SSCALED = 0x00000003, - IMG_NUM_FORMAT_UINT = 0x00000004, - IMG_NUM_FORMAT_SINT = 0x00000005, - IMG_NUM_FORMAT_RESERVED_6 = 0x00000006, - IMG_NUM_FORMAT_FLOAT = 0x00000007, - IMG_NUM_FORMAT_RESERVED_8 = 0x00000008, - IMG_NUM_FORMAT_SRGB = 0x00000009, - IMG_NUM_FORMAT_UNORM_UINT = 0x0000000a, - IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b, - IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c, - IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d, - IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e, - IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f, -} IMG_NUM_FORMAT; - -/* - * IMG_NUM_FORMAT_FMASK enum - */ - -typedef enum IMG_NUM_FORMAT_FMASK { - IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000, - IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001, - IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002, - IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003, - IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004, - IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005, - IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006, - IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007, - IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008, - IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009, - IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a, - IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b, - IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c, - IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d, - IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e, - IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f, -} IMG_NUM_FORMAT_FMASK; - -/* - * IMG_NUM_FORMAT_N_IN_16 enum - */ - -typedef enum IMG_NUM_FORMAT_N_IN_16 { - IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000, - IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001, - IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002, - IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003, - IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004, - IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005, - IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006, - IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007, - IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008, - IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009, - IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a, - IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b, - IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c, - IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d, - IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e, - IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f, -} IMG_NUM_FORMAT_N_IN_16; - -/* - * IMG_NUM_FORMAT_ASTC_2D enum - */ - -typedef enum IMG_NUM_FORMAT_ASTC_2D { - IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000, - IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001, - IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002, - IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003, - IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004, - IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005, - IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006, - IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007, - IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008, - IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009, - IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a, - IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b, - IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c, - IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d, - IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e, - IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f, -} IMG_NUM_FORMAT_ASTC_2D; - -/* - * IMG_NUM_FORMAT_ASTC_3D enum - */ - -typedef enum IMG_NUM_FORMAT_ASTC_3D { - IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000, - IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001, - IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002, - IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003, - IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004, - IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005, - IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006, - IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007, - IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008, - IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009, - IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a, - IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b, - IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c, - IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d, - IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e, - IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f, -} IMG_NUM_FORMAT_ASTC_3D; - -/* - * TileType enum - */ - -typedef enum TileType { - ARRAY_COLOR_TILE = 0x00000000, - ARRAY_DEPTH_TILE = 0x00000001, -} TileType; - -/* - * NonDispTilingOrder enum - */ - -typedef enum NonDispTilingOrder { - ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000, - ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001, -} NonDispTilingOrder; - -/* - * MicroTileMode enum - */ - -typedef enum MicroTileMode { - ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000, - ADDR_SURF_THIN_MICRO_TILING = 0x00000001, - ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002, - ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003, - ADDR_SURF_THICK_MICRO_TILING = 0x00000004, -} MicroTileMode; - -/* - * TileSplit enum - */ - -typedef enum TileSplit { - ADDR_SURF_TILE_SPLIT_64B = 0x00000000, - ADDR_SURF_TILE_SPLIT_128B = 0x00000001, - ADDR_SURF_TILE_SPLIT_256B = 0x00000002, - ADDR_SURF_TILE_SPLIT_512B = 0x00000003, - ADDR_SURF_TILE_SPLIT_1KB = 0x00000004, - ADDR_SURF_TILE_SPLIT_2KB = 0x00000005, - ADDR_SURF_TILE_SPLIT_4KB = 0x00000006, -} TileSplit; - -/* - * SampleSplit enum - */ - -typedef enum SampleSplit { - ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000, - ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001, - ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002, - ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003, -} SampleSplit; - -/* - * PipeConfig enum - */ - -typedef enum PipeConfig { - ADDR_SURF_P2 = 0x00000000, - ADDR_SURF_P2_RESERVED0 = 0x00000001, - ADDR_SURF_P2_RESERVED1 = 0x00000002, - ADDR_SURF_P2_RESERVED2 = 0x00000003, - ADDR_SURF_P4_8x16 = 0x00000004, - ADDR_SURF_P4_16x16 = 0x00000005, - ADDR_SURF_P4_16x32 = 0x00000006, - ADDR_SURF_P4_32x32 = 0x00000007, - ADDR_SURF_P8_16x16_8x16 = 0x00000008, - ADDR_SURF_P8_16x32_8x16 = 0x00000009, - ADDR_SURF_P8_32x32_8x16 = 0x0000000a, - ADDR_SURF_P8_16x32_16x16 = 0x0000000b, - ADDR_SURF_P8_32x32_16x16 = 0x0000000c, - ADDR_SURF_P8_32x32_16x32 = 0x0000000d, - ADDR_SURF_P8_32x64_32x32 = 0x0000000e, - ADDR_SURF_P8_RESERVED0 = 0x0000000f, - ADDR_SURF_P16_32x32_8x16 = 0x00000010, - ADDR_SURF_P16_32x32_16x16 = 0x00000011, -} PipeConfig; - -/* - * SeEnable enum - */ - -typedef enum SeEnable { - ADDR_CONFIG_DISABLE_SE = 0x00000000, - ADDR_CONFIG_ENABLE_SE = 0x00000001, -} SeEnable; - -/* - * NumBanks enum - */ - -typedef enum NumBanks { - ADDR_SURF_2_BANK = 0x00000000, - ADDR_SURF_4_BANK = 0x00000001, - ADDR_SURF_8_BANK = 0x00000002, - ADDR_SURF_16_BANK = 0x00000003, -} NumBanks; - -/* - * BankWidth enum - */ - -typedef enum BankWidth { - ADDR_SURF_BANK_WIDTH_1 = 0x00000000, - ADDR_SURF_BANK_WIDTH_2 = 0x00000001, - ADDR_SURF_BANK_WIDTH_4 = 0x00000002, - ADDR_SURF_BANK_WIDTH_8 = 0x00000003, -} BankWidth; - -/* - * BankHeight enum - */ - -typedef enum BankHeight { - ADDR_SURF_BANK_HEIGHT_1 = 0x00000000, - ADDR_SURF_BANK_HEIGHT_2 = 0x00000001, - ADDR_SURF_BANK_HEIGHT_4 = 0x00000002, - ADDR_SURF_BANK_HEIGHT_8 = 0x00000003, -} BankHeight; - -/* - * BankWidthHeight enum - */ - -typedef enum BankWidthHeight { - ADDR_SURF_BANK_WH_1 = 0x00000000, - ADDR_SURF_BANK_WH_2 = 0x00000001, - ADDR_SURF_BANK_WH_4 = 0x00000002, - ADDR_SURF_BANK_WH_8 = 0x00000003, -} BankWidthHeight; - -/* - * MacroTileAspect enum - */ - -typedef enum MacroTileAspect { - ADDR_SURF_MACRO_ASPECT_1 = 0x00000000, - ADDR_SURF_MACRO_ASPECT_2 = 0x00000001, - ADDR_SURF_MACRO_ASPECT_4 = 0x00000002, - ADDR_SURF_MACRO_ASPECT_8 = 0x00000003, -} MacroTileAspect; - -/* - * GATCL1RequestType enum - */ - -typedef enum GATCL1RequestType { - GATCL1_TYPE_NORMAL = 0x00000000, - GATCL1_TYPE_SHOOTDOWN = 0x00000001, - GATCL1_TYPE_BYPASS = 0x00000002, -} GATCL1RequestType; - -/* - * UTCL1RequestType enum - */ - -typedef enum UTCL1RequestType { - UTCL1_TYPE_NORMAL = 0x00000000, - UTCL1_TYPE_SHOOTDOWN = 0x00000001, - UTCL1_TYPE_BYPASS = 0x00000002, -} UTCL1RequestType; - -/* - * UTCL1FaultType enum - */ - -typedef enum UTCL1FaultType { - UTCL1_XNACK_SUCCESS = 0x00000000, - UTCL1_XNACK_RETRY = 0x00000001, - UTCL1_XNACK_PRT = 0x00000002, - UTCL1_XNACK_NO_RETRY = 0x00000003, -} UTCL1FaultType; - -/* - * TCC_CACHE_POLICIES enum - */ - -typedef enum TCC_CACHE_POLICIES { - TCC_CACHE_POLICY_LRU = 0x00000000, - TCC_CACHE_POLICY_STREAM = 0x00000001, -} TCC_CACHE_POLICIES; - -/* - * MTYPE enum - */ - -typedef enum MTYPE { - MTYPE_NC = 0x00000000, - MTYPE_WC = 0x00000001, - MTYPE_CC = 0x00000002, - MTYPE_UC = 0x00000003, -} MTYPE; - -/* - * RMI_CID enum - */ - -typedef enum RMI_CID { - RMI_CID_CC = 0x00000000, - RMI_CID_FC = 0x00000001, - RMI_CID_CM = 0x00000002, - RMI_CID_DC = 0x00000003, - RMI_CID_Z = 0x00000004, - RMI_CID_S = 0x00000005, - RMI_CID_TILE = 0x00000006, - RMI_CID_ZPCPSD = 0x00000007, -} RMI_CID; - -/* - * PERFMON_COUNTER_MODE enum - */ - -typedef enum PERFMON_COUNTER_MODE { - PERFMON_COUNTER_MODE_ACCUM = 0x00000000, - PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, - PERFMON_COUNTER_MODE_MAX = 0x00000002, - PERFMON_COUNTER_MODE_DIRTY = 0x00000003, - PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, - PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, - PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, - PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, - PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, - PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, - PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, -} PERFMON_COUNTER_MODE; - -/* - * PERFMON_SPM_MODE enum - */ - -typedef enum PERFMON_SPM_MODE { - PERFMON_SPM_MODE_OFF = 0x00000000, - PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, - PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, - PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, - PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, - PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, - PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, - PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, - PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, - PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, - PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, -} PERFMON_SPM_MODE; - -/* - * SurfaceTiling enum - */ - -typedef enum SurfaceTiling { - ARRAY_LINEAR = 0x00000000, - ARRAY_TILED = 0x00000001, -} SurfaceTiling; - -/* - * SurfaceArray enum - */ - -typedef enum SurfaceArray { - ARRAY_1D = 0x00000000, - ARRAY_2D = 0x00000001, - ARRAY_3D = 0x00000002, - ARRAY_3D_SLICE = 0x00000003, -} SurfaceArray; - -/* - * ColorArray enum - */ - -typedef enum ColorArray { - ARRAY_2D_ALT_COLOR = 0x00000000, - ARRAY_2D_COLOR = 0x00000001, - ARRAY_3D_SLICE_COLOR = 0x00000003, -} ColorArray; - -/* - * DepthArray enum - */ - -typedef enum DepthArray { - ARRAY_2D_ALT_DEPTH = 0x00000000, - ARRAY_2D_DEPTH = 0x00000001, -} DepthArray; - -/* - * ENUM_NUM_SIMD_PER_CU enum - */ - -typedef enum ENUM_NUM_SIMD_PER_CU { - NUM_SIMD_PER_CU = 0x00000004, -} ENUM_NUM_SIMD_PER_CU; - -/* - * DSM_ENABLE_ERROR_INJECT enum - */ - -typedef enum DSM_ENABLE_ERROR_INJECT { - DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, - DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, - DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, - DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, -} DSM_ENABLE_ERROR_INJECT; - -/* - * DSM_SELECT_INJECT_DELAY enum - */ - -typedef enum DSM_SELECT_INJECT_DELAY { - DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, - DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, -} DSM_SELECT_INJECT_DELAY; - -/* - * DSM_DATA_SEL enum - */ - -typedef enum DSM_DATA_SEL { - DSM_DATA_SEL_DISABLE = 0x00000000, - DSM_DATA_SEL_0 = 0x00000001, - DSM_DATA_SEL_1 = 0x00000002, - DSM_DATA_SEL_BOTH = 0x00000003, -} DSM_DATA_SEL; - -/* - * DSM_SINGLE_WRITE enum - */ - -typedef enum DSM_SINGLE_WRITE { - DSM_SINGLE_WRITE_DIS = 0x00000000, - DSM_SINGLE_WRITE_EN = 0x00000001, -} DSM_SINGLE_WRITE; - -/* - * PipeTiling enum - */ - -typedef enum PipeTiling { - CONFIG_1_PIPE = 0x00000000, - CONFIG_2_PIPE = 0x00000001, - CONFIG_4_PIPE = 0x00000002, - CONFIG_8_PIPE = 0x00000003, -} PipeTiling; - -/* - * BankTiling enum - */ - -typedef enum BankTiling { - CONFIG_4_BANK = 0x00000000, - CONFIG_8_BANK = 0x00000001, -} BankTiling; - -/* - * GroupInterleave enum - */ - -typedef enum GroupInterleave { - CONFIG_256B_GROUP = 0x00000000, - CONFIG_512B_GROUP = 0x00000001, -} GroupInterleave; - -/* - * RowTiling enum - */ - -typedef enum RowTiling { - CONFIG_1KB_ROW = 0x00000000, - CONFIG_2KB_ROW = 0x00000001, - CONFIG_4KB_ROW = 0x00000002, - CONFIG_8KB_ROW = 0x00000003, - CONFIG_1KB_ROW_OPT = 0x00000004, - CONFIG_2KB_ROW_OPT = 0x00000005, - CONFIG_4KB_ROW_OPT = 0x00000006, - CONFIG_8KB_ROW_OPT = 0x00000007, -} RowTiling; - -/* - * BankSwapBytes enum - */ - -typedef enum BankSwapBytes { - CONFIG_128B_SWAPS = 0x00000000, - CONFIG_256B_SWAPS = 0x00000001, - CONFIG_512B_SWAPS = 0x00000002, - CONFIG_1KB_SWAPS = 0x00000003, -} BankSwapBytes; - -/* - * SampleSplitBytes enum - */ - -typedef enum SampleSplitBytes { - CONFIG_1KB_SPLIT = 0x00000000, - CONFIG_2KB_SPLIT = 0x00000001, - CONFIG_4KB_SPLIT = 0x00000002, - CONFIG_8KB_SPLIT = 0x00000003, -} SampleSplitBytes; - -/* - * SWIZZLE_TYPE_ENUM enum - */ - -typedef enum SWIZZLE_TYPE_ENUM { - SW_Z = 0x00000000, - SW_S = 0x00000001, - SW_D = 0x00000002, - SW_R = 0x00000003, - SW_L = 0x00000004, -} SWIZZLE_TYPE_ENUM; - -/* - * TC_MICRO_TILE_MODE enum - */ - -typedef enum TC_MICRO_TILE_MODE { - MICRO_TILE_MODE_LINEAR = 0x00000000, - MICRO_TILE_MODE_ROTATED = 0x00000001, - MICRO_TILE_MODE_STD_2D = 0x00000002, - MICRO_TILE_MODE_STD_3D = 0x00000003, - MICRO_TILE_MODE_DISPLAY_2D = 0x00000004, - MICRO_TILE_MODE_DISPLAY_3D = 0x00000005, - MICRO_TILE_MODE_Z_2D = 0x00000006, - MICRO_TILE_MODE_Z_3D = 0x00000007, -} TC_MICRO_TILE_MODE; - -/* - * SWIZZLE_MODE_ENUM enum - */ - -typedef enum SWIZZLE_MODE_ENUM { - SW_LINEAR = 0x00000000, - SW_256B_S = 0x00000001, - SW_256B_D = 0x00000002, - SW_256B_R = 0x00000003, - SW_4KB_Z = 0x00000004, - SW_4KB_S = 0x00000005, - SW_4KB_D = 0x00000006, - SW_4KB_R = 0x00000007, - SW_64KB_Z = 0x00000008, - SW_64KB_S = 0x00000009, - SW_64KB_D = 0x0000000a, - SW_64KB_R = 0x0000000b, - SW_VAR_Z = 0x0000000c, - SW_VAR_S = 0x0000000d, - SW_VAR_D = 0x0000000e, - SW_VAR_R = 0x0000000f, - SW_64KB_Z_T = 0x00000010, - SW_64KB_S_T = 0x00000011, - SW_64KB_D_T = 0x00000012, - SW_64KB_R_T = 0x00000013, - SW_4KB_Z_X = 0x00000014, - SW_4KB_S_X = 0x00000015, - SW_4KB_D_X = 0x00000016, - SW_4KB_R_X = 0x00000017, - SW_64KB_Z_X = 0x00000018, - SW_64KB_S_X = 0x00000019, - SW_64KB_D_X = 0x0000001a, - SW_64KB_R_X = 0x0000001b, - SW_VAR_Z_X = 0x0000001c, - SW_VAR_S_X = 0x0000001d, - SW_VAR_D_X = 0x0000001e, - SW_VAR_R_X = 0x0000001f, -} SWIZZLE_MODE_ENUM; - -/******************************************************* - * ATS Enums - *******************************************************/ - -/******************************************************* - * XPB Enums - *******************************************************/ - -/******************************************************* - * RPB Enums - *******************************************************/ - -/******************************************************* - * RSMU_GENERIC Enums - *******************************************************/ - -/******************************************************* - * RSMU_GC Enums - *******************************************************/ - -/******************************************************* - * BIF_RST Enums - *******************************************************/ - -/******************************************************* - * BIF_MISC Enums - *******************************************************/ - -/******************************************************* - * BIF_RAS Enums - *******************************************************/ - -/******************************************************* - * BIF_BX Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_EPF Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_EPVF Enums - *******************************************************/ - -/******************************************************* - * RCC Enums - *******************************************************/ - -/******************************************************* - * RCC_DWN Enums - *******************************************************/ - -/******************************************************* - * RCC_DWNP Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_SWDS Enums - *******************************************************/ - -/******************************************************* - * BIF_CFG_RC Enums - *******************************************************/ - -/******************************************************* - * RCC_SHADOW_REG Enums - *******************************************************/ - -/******************************************************* - * RCC_EP Enums - *******************************************************/ - -/******************************************************* - * GDC Enums - *******************************************************/ - -/******************************************************* - * GDC_RAS Enums - *******************************************************/ - -/******************************************************* - * NBIF_SION Enums - *******************************************************/ - -/******************************************************* - * RCC_STRAP Enums - *******************************************************/ - -/******************************************************* - * GDC_RST Enums - *******************************************************/ - -/******************************************************* - * PCIEMSIX Enums - *******************************************************/ - -/******************************************************* - * RCC_PFC Enums - *******************************************************/ - -/******************************************************* - * IH Enums - *******************************************************/ - -/* - * IH_PERF_SEL enum - */ - -typedef enum IH_PERF_SEL { - IH_PERF_SEL_CYCLE = 0x00000000, - IH_PERF_SEL_IDLE = 0x00000001, - IH_PERF_SEL_INPUT_IDLE = 0x00000002, - IH_PERF_SEL_BUFFER_IDLE = 0x00000003, - IH_PERF_SEL_RB0_FULL = 0x00000004, - IH_PERF_SEL_RB0_OVERFLOW = 0x00000005, - IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006, - IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007, - IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008, - IH_PERF_SEL_MC_WR_IDLE = 0x00000009, - IH_PERF_SEL_MC_WR_COUNT = 0x0000000a, - IH_PERF_SEL_MC_WR_STALL = 0x0000000b, - IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c, - IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d, - IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e, - IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f, - IH_PERF_SEL_RB1_FULL = 0x00000010, - IH_PERF_SEL_RB1_OVERFLOW = 0x00000011, - IH_PERF_SEL_COOKIE_REC_ERROR = 0x00000012, - IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013, - IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014, - IH_PERF_SEL_RB2_FULL = 0x00000015, - IH_PERF_SEL_RB2_OVERFLOW = 0x00000016, - IH_PERF_SEL_CLIENT_CREDIT_ERROR = 0x00000017, - IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018, - IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019, - IH_PERF_SEL_STORM_CLIENT_INT_DROP = 0x0000001a, - IH_PERF_SEL_SELF_IV_VALID = 0x0000001b, - IH_PERF_SEL_BUFFER_FIFO_FULL = 0x0000001c, - Reserved29 = 0x0000001d, - IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001e, - IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001f, - IH_PERF_SEL_RB0_FULL_VF2 = 0x00000020, - IH_PERF_SEL_RB0_FULL_VF3 = 0x00000021, - IH_PERF_SEL_RB0_FULL_VF4 = 0x00000022, - IH_PERF_SEL_RB0_FULL_VF5 = 0x00000023, - IH_PERF_SEL_RB0_FULL_VF6 = 0x00000024, - IH_PERF_SEL_RB0_FULL_VF7 = 0x00000025, - IH_PERF_SEL_RB0_FULL_VF8 = 0x00000026, - IH_PERF_SEL_RB0_FULL_VF9 = 0x00000027, - IH_PERF_SEL_RB0_FULL_VF10 = 0x00000028, - IH_PERF_SEL_RB0_FULL_VF11 = 0x00000029, - IH_PERF_SEL_RB0_FULL_VF12 = 0x0000002a, - IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002b, - IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002c, - IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002d, - IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002e, - IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002f, - IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x00000030, - IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000031, - IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000032, - IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000033, - IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000034, - IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000035, - IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000036, - IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000037, - IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000038, - IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000039, - IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x0000003a, - IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003b, - IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003c, - IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003d, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003e, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003f, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x00000040, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000041, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000042, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000043, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000044, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000045, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000046, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000047, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000048, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000049, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x0000004a, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004b, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004c, - IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004d, - IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004e, - IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004f, - IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x00000050, - IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000051, - IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000052, - IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000053, - IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000054, - IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000055, - IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000056, - IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000057, - IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000058, - IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000059, - IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x0000005a, - IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005b, - IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005c, - IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005d, - IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005e, - IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005f, - IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x00000060, - IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000061, - IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000062, - IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000063, - IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000064, - IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000065, - IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000066, - IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000067, - IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000068, - IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000069, - IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x0000006a, - IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006b, - IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006c, - IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006d, - IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006e, - IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006f, - IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x00000070, - IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000071, - IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000072, - IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000073, - IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000074, - IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000075, - IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000076, - IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000077, - IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000078, - IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000079, - IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x0000007a, - IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007b, - IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007c, - IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007d, - IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007e, - IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007f, - IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x00000080, - IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000081, - IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000082, - IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000083, - IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000084, - IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000085, - IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000086, - IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000087, - IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000088, - IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000089, - IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x0000008a, - IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008b, - IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008c, - IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008d, - Reserved142 = 0x0000008e, - Reserved143 = 0x0000008f, - Reserved144 = 0x00000090, - Reserved145 = 0x00000091, - Reserved146 = 0x00000092, - Reserved147 = 0x00000093, - Reserved148 = 0x00000094, - Reserved149 = 0x00000095, - IH_PERF_SEL_CLIENT0_INT = 0x00000096, - IH_PERF_SEL_CLIENT1_INT = 0x00000097, - IH_PERF_SEL_CLIENT2_INT = 0x00000098, - IH_PERF_SEL_CLIENT3_INT = 0x00000099, - IH_PERF_SEL_CLIENT4_INT = 0x0000009a, - IH_PERF_SEL_CLIENT5_INT = 0x0000009b, - IH_PERF_SEL_CLIENT6_INT = 0x0000009c, - IH_PERF_SEL_CLIENT7_INT = 0x0000009d, - IH_PERF_SEL_CLIENT8_INT = 0x0000009e, - IH_PERF_SEL_CLIENT9_INT = 0x0000009f, - IH_PERF_SEL_CLIENT10_INT = 0x000000a0, - IH_PERF_SEL_CLIENT11_INT = 0x000000a1, - IH_PERF_SEL_CLIENT12_INT = 0x000000a2, - IH_PERF_SEL_CLIENT13_INT = 0x000000a3, - IH_PERF_SEL_CLIENT14_INT = 0x000000a4, - IH_PERF_SEL_CLIENT15_INT = 0x000000a5, - IH_PERF_SEL_CLIENT16_INT = 0x000000a6, - IH_PERF_SEL_CLIENT17_INT = 0x000000a7, - IH_PERF_SEL_CLIENT18_INT = 0x000000a8, - IH_PERF_SEL_CLIENT19_INT = 0x000000a9, - IH_PERF_SEL_CLIENT20_INT = 0x000000aa, - IH_PERF_SEL_CLIENT21_INT = 0x000000ab, - IH_PERF_SEL_CLIENT22_INT = 0x000000ac, - IH_PERF_SEL_CLIENT23_INT = 0x000000ad, - IH_PERF_SEL_CLIENT24_INT = 0x000000ae, - IH_PERF_SEL_CLIENT25_INT = 0x000000af, - IH_PERF_SEL_CLIENT26_INT = 0x000000b0, - IH_PERF_SEL_CLIENT27_INT = 0x000000b1, - IH_PERF_SEL_CLIENT28_INT = 0x000000b2, - IH_PERF_SEL_CLIENT29_INT = 0x000000b3, - IH_PERF_SEL_CLIENT30_INT = 0x000000b4, - IH_PERF_SEL_CLIENT31_INT = 0x000000b5, - IH_PERF_SEL_RB1_FULL_VF0 = 0x000000b6, - IH_PERF_SEL_RB1_FULL_VF1 = 0x000000b7, - IH_PERF_SEL_RB1_FULL_VF2 = 0x000000b8, - IH_PERF_SEL_RB1_FULL_VF3 = 0x000000b9, - IH_PERF_SEL_RB1_FULL_VF4 = 0x000000ba, - IH_PERF_SEL_RB1_FULL_VF5 = 0x000000bb, - IH_PERF_SEL_RB1_FULL_VF6 = 0x000000bc, - IH_PERF_SEL_RB1_FULL_VF7 = 0x000000bd, - IH_PERF_SEL_RB1_FULL_VF8 = 0x000000be, - IH_PERF_SEL_RB1_FULL_VF9 = 0x000000bf, - IH_PERF_SEL_RB1_FULL_VF10 = 0x000000c0, - IH_PERF_SEL_RB1_FULL_VF11 = 0x000000c1, - IH_PERF_SEL_RB1_FULL_VF12 = 0x000000c2, - IH_PERF_SEL_RB1_FULL_VF13 = 0x000000c3, - IH_PERF_SEL_RB1_FULL_VF14 = 0x000000c4, - IH_PERF_SEL_RB1_FULL_VF15 = 0x000000c5, - IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000c6, - IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000c7, - IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000c8, - IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000c9, - IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000ca, - IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000cb, - IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000cc, - IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000cd, - IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000ce, - IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000cf, - IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000d0, - IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000d1, - IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000d2, - IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000d3, - IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000d4, - IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000d5, - IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x000000d6, - IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x000000d7, - IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x000000d8, - IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x000000d9, - IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x000000da, - IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x000000db, - IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x000000dc, - IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x000000dd, - IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x000000de, - IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x000000df, - IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x000000e0, - IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x000000e1, - IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x000000e2, - IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x000000e3, - IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x000000e4, - IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x000000e5, - IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x000000e6, - IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x000000e7, - IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x000000e8, - IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x000000e9, - IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x000000ea, - IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x000000eb, - IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x000000ec, - IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x000000ed, - IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x000000ee, - IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x000000ef, - IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x000000f0, - IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x000000f1, - IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x000000f2, - IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x000000f3, - IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x000000f4, - IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x000000f5, - IH_PERF_SEL_RB2_FULL_VF0 = 0x000000f6, - IH_PERF_SEL_RB2_FULL_VF1 = 0x000000f7, - IH_PERF_SEL_RB2_FULL_VF2 = 0x000000f8, - IH_PERF_SEL_RB2_FULL_VF3 = 0x000000f9, - IH_PERF_SEL_RB2_FULL_VF4 = 0x000000fa, - IH_PERF_SEL_RB2_FULL_VF5 = 0x000000fb, - IH_PERF_SEL_RB2_FULL_VF6 = 0x000000fc, - IH_PERF_SEL_RB2_FULL_VF7 = 0x000000fd, - IH_PERF_SEL_RB2_FULL_VF8 = 0x000000fe, - IH_PERF_SEL_RB2_FULL_VF9 = 0x000000ff, - IH_PERF_SEL_RB2_FULL_VF10 = 0x00000100, - IH_PERF_SEL_RB2_FULL_VF11 = 0x00000101, - IH_PERF_SEL_RB2_FULL_VF12 = 0x00000102, - IH_PERF_SEL_RB2_FULL_VF13 = 0x00000103, - IH_PERF_SEL_RB2_FULL_VF14 = 0x00000104, - IH_PERF_SEL_RB2_FULL_VF15 = 0x00000105, - IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x00000106, - IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x00000107, - IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x00000108, - IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x00000109, - IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x0000010a, - IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x0000010b, - IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x0000010c, - IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x0000010d, - IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x0000010e, - IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x0000010f, - IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000110, - IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000111, - IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000112, - IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x00000113, - IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x00000114, - IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x00000115, - IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x00000116, - IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x00000117, - IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x00000118, - IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x00000119, - IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x0000011a, - IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x0000011b, - IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x0000011c, - IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x0000011d, - IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x0000011e, - IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x0000011f, - IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000120, - IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000121, - IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000122, - IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x00000123, - IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x00000124, - IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x00000125, - IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x00000126, - IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x00000127, - IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x00000128, - IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x00000129, - IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x0000012a, - IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x0000012b, - IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x0000012c, - IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x0000012d, - IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x0000012e, - IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x0000012f, - IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000130, - IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000131, - IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000132, - IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x00000133, - IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x00000134, - IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x00000135, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 0x00000136, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 0x00000137, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 0x00000138, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 0x00000139, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 0x0000013a, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 0x0000013b, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 0x0000013c, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 0x0000013d, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 0x0000013e, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 0x0000013f, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 0x00000140, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 0x00000141, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 0x00000142, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 0x00000143, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 0x00000144, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 0x00000145, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 0x00000146, - IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16 = 0x00000147, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 0x00000148, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 0x00000149, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 0x0000014a, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 0x0000014b, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 0x0000014c, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 0x0000014d, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 0x0000014e, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 0x0000014f, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 0x00000150, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 0x00000151, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 0x00000152, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 0x00000153, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 0x00000154, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 0x00000155, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 0x00000156, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 0x00000157, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 0x00000158, - IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16 = 0x00000159, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 0x0000015a, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 0x0000015b, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 0x0000015c, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 0x0000015d, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 0x0000015e, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 0x0000015f, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 0x00000160, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 0x00000161, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 0x00000162, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 0x00000163, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 0x00000164, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 0x00000165, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 0x00000166, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 0x00000167, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 0x00000168, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 0x00000169, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 0x0000016a, - IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16 = 0x0000016b, - Reserved364 = 0x0000016c, - Reserved365 = 0x0000016d, - Reserved366 = 0x0000016e, - Reserved367 = 0x0000016f, - Reserved368 = 0x00000170, - Reserved369 = 0x00000171, - Reserved370 = 0x00000172, - Reserved371 = 0x00000173, - Reserved372 = 0x00000174, - Reserved373 = 0x00000175, - Reserved374 = 0x00000176, - Reserved375 = 0x00000177, - Reserved376 = 0x00000178, - Reserved377 = 0x00000179, - Reserved378 = 0x0000017a, - Reserved379 = 0x0000017b, - Reserved380 = 0x0000017c, - Reserved381 = 0x0000017d, - Reserved382 = 0x0000017e, - Reserved383 = 0x0000017f, - Reserved384 = 0x00000180, - Reserved385 = 0x00000181, - Reserved386 = 0x00000182, - Reserved387 = 0x00000183, - Reserved388 = 0x00000184, - Reserved389 = 0x00000185, - Reserved390 = 0x00000186, - Reserved391 = 0x00000187, - Reserved392 = 0x00000188, - Reserved393 = 0x00000189, - Reserved394 = 0x0000018a, - Reserved395 = 0x0000018b, - Reserved396 = 0x0000018c, - Reserved397 = 0x0000018d, - Reserved398 = 0x0000018e, - Reserved399 = 0x0000018f, - Reserved400 = 0x00000190, - Reserved401 = 0x00000191, - Reserved402 = 0x00000192, - Reserved403 = 0x00000193, - Reserved404 = 0x00000194, - Reserved405 = 0x00000195, - Reserved406 = 0x00000196, - Reserved407 = 0x00000197, - Reserved408 = 0x00000198, - Reserved409 = 0x00000199, - Reserved410 = 0x0000019a, - Reserved411 = 0x0000019b, - Reserved412 = 0x0000019c, - Reserved413 = 0x0000019d, - Reserved414 = 0x0000019e, - Reserved415 = 0x0000019f, - Reserved416 = 0x000001a0, - Reserved417 = 0x000001a1, - Reserved418 = 0x000001a2, - Reserved419 = 0x000001a3, - Reserved420 = 0x000001a4, - Reserved421 = 0x000001a5, - Reserved422 = 0x000001a6, - Reserved423 = 0x000001a7, - Reserved424 = 0x000001a8, - Reserved425 = 0x000001a9, - Reserved426 = 0x000001aa, - Reserved427 = 0x000001ab, - Reserved428 = 0x000001ac, - Reserved429 = 0x000001ad, - Reserved430 = 0x000001ae, - Reserved431 = 0x000001af, - Reserved432 = 0x000001b0, - Reserved433 = 0x000001b1, - Reserved434 = 0x000001b2, - Reserved435 = 0x000001b3, - Reserved436 = 0x000001b4, - Reserved437 = 0x000001b5, - Reserved438 = 0x000001b6, - Reserved439 = 0x000001b7, - Reserved440 = 0x000001b8, - Reserved441 = 0x000001b9, - Reserved442 = 0x000001ba, - Reserved443 = 0x000001bb, - Reserved444 = 0x000001bc, - Reserved445 = 0x000001bd, - Reserved446 = 0x000001be, - Reserved447 = 0x000001bf, - Reserved448 = 0x000001c0, - Reserved449 = 0x000001c1, - Reserved450 = 0x000001c2, - Reserved451 = 0x000001c3, - Reserved452 = 0x000001c4, - Reserved453 = 0x000001c5, - Reserved454 = 0x000001c6, - Reserved455 = 0x000001c7, - Reserved456 = 0x000001c8, - Reserved457 = 0x000001c9, - Reserved458 = 0x000001ca, - Reserved459 = 0x000001cb, - Reserved460 = 0x000001cc, - Reserved461 = 0x000001cd, - Reserved462 = 0x000001ce, - Reserved463 = 0x000001cf, - Reserved464 = 0x000001d0, - Reserved465 = 0x000001d1, - Reserved466 = 0x000001d2, - Reserved467 = 0x000001d3, - Reserved468 = 0x000001d4, - Reserved469 = 0x000001d5, - Reserved470 = 0x000001d6, - Reserved471 = 0x000001d7, - Reserved472 = 0x000001d8, - Reserved473 = 0x000001d9, - Reserved474 = 0x000001da, - Reserved475 = 0x000001db, - Reserved476 = 0x000001dc, - Reserved477 = 0x000001dd, - Reserved478 = 0x000001de, - Reserved479 = 0x000001df, - Reserved480 = 0x000001e0, - Reserved481 = 0x000001e1, - Reserved482 = 0x000001e2, - Reserved483 = 0x000001e3, - Reserved484 = 0x000001e4, - Reserved485 = 0x000001e5, - Reserved486 = 0x000001e6, - Reserved487 = 0x000001e7, - Reserved488 = 0x000001e8, - Reserved489 = 0x000001e9, - Reserved490 = 0x000001ea, - Reserved491 = 0x000001eb, - Reserved492 = 0x000001ec, - Reserved493 = 0x000001ed, - Reserved494 = 0x000001ee, - Reserved495 = 0x000001ef, - Reserved496 = 0x000001f0, - Reserved497 = 0x000001f1, - Reserved498 = 0x000001f2, - Reserved499 = 0x000001f3, - Reserved500 = 0x000001f4, - Reserved501 = 0x000001f5, - Reserved502 = 0x000001f6, - Reserved503 = 0x000001f7, - Reserved504 = 0x000001f8, - Reserved505 = 0x000001f9, - Reserved506 = 0x000001fa, - Reserved507 = 0x000001fb, - Reserved508 = 0x000001fc, - Reserved509 = 0x000001fd, - Reserved510 = 0x000001fe, - Reserved511 = 0x000001ff, -} IH_PERF_SEL; - -/* - * IH_CLIENT_TYPE enum - */ - -typedef enum IH_CLIENT_TYPE { - IH_GFX_VMID_CLIENT = 0x00000000, - IH_MM_VMID_CLIENT = 0x00000001, - IH_MULTI_VMID_CLIENT = 0x00000002, - IH_CLIENT_TYPE_RESERVED = 0x00000003, -} IH_CLIENT_TYPE; - -/* - * IH_RING_ID enum - */ - -typedef enum IH_RING_ID { - IH_RING_ID_INTERRUPT = 0x00000000, - IH_RING_ID_REQUEST = 0x00000001, - IH_RING_ID_TRANSLATION = 0x00000002, - IH_RING_ID_RESERVED = 0x00000003, -} IH_RING_ID; - -/* - * IH_VF_RB_SELECT enum - */ - -typedef enum IH_VF_RB_SELECT { - IH_VF_RB_SELECT_CLIENT_FCN_ID = 0x00000000, - IH_VF_RB_SELECT_IH_FCN_ID = 0x00000001, - IH_VF_RB_SELECT_PF = 0x00000002, - IH_VF_RB_SELECT_RESERVED = 0x00000003, -} IH_VF_RB_SELECT; - -/******************************************************* - * SEM Enums - *******************************************************/ - -/* - * SEM_PERF_SEL enum - */ - -typedef enum SEM_PERF_SEL { - SEM_PERF_SEL_CYCLE = 0x00000000, - SEM_PERF_SEL_IDLE = 0x00000001, - SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, - SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, - SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004, - SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005, - SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006, - SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007, - SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008, - SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009, - SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a, - SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b, - SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c, - SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d, - SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e, - SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f, - SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010, - SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011, - SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012, - SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013, - SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014, - SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015, - SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016, - SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017, - SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018, - SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019, - SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a, - SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b, - SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c, - SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d, - SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e, - SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f, - SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020, - SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021, - SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022, - SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023, - SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024, - SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025, - SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026, - SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027, - SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028, - SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029, - SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a, - SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b, - SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c, - SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d, - SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e, - SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f, - SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030, - SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031, - SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032, - SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033, - SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034, - SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035, - SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036, - SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037, - SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038, - SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039, - SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a, - SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b, - SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c, - SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d, - SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e, - SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f, - SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040, - SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041, - SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042, - SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043, - SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044, - SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045, - SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046, - SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047, - SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048, - SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049, - SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a, - SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b, - SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c, - SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d, - SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e, - SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f, - SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050, - SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051, - SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052, - SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053, - SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054, - SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055, - SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056, - SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057, - SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058, - SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059, - SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a, - SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b, - SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c, - SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d, - SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e, - SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f, - SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060, - SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061, - SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062, - SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063, - SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064, - SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065, - SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066, - SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067, - SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068, - SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069, - SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a, - SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b, - SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c, - SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d, - SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e, - SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f, - SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070, - SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071, - SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072, - SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073, - SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074, - SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075, - SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076, - SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077, - SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078, - SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079, - SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a, - SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b, - SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c, - SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d, - SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e, - SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f, - SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080, - SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081, - SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082, - SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083, - SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084, - SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085, - SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086, - SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087, - SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088, - SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089, - SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a, - SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b, - SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c, - SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d, - SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e, - SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f, - SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090, - SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091, - SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092, - SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093, - SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094, - SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095, - SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096, - SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097, - SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098, - SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099, - SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a, - SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b, - SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c, - SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d, - SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e, - SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f, - SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0, - SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1, - SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2, - SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3, - SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4, - SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5, - SEM_PERF_SEL_MC_RD_REQ = 0x000000a6, - SEM_PERF_SEL_MC_RD_RET = 0x000000a7, - SEM_PERF_SEL_MC_WR_REQ = 0x000000a8, - SEM_PERF_SEL_MC_WR_RET = 0x000000a9, - SEM_PERF_SEL_ATC_REQ = 0x000000aa, - SEM_PERF_SEL_ATC_RET = 0x000000ab, - SEM_PERF_SEL_ATC_XNACK = 0x000000ac, - SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad, - SEM_PERF_SEL_ATC_VM_INVALIDATION = 0x000000ae, -} SEM_PERF_SEL; - -/******************************************************* - * SDMA Enums - *******************************************************/ - -/* - * SDMA_PERF_SEL enum - */ - -typedef enum SDMA_PERF_SEL { - SDMA_PERF_SEL_CYCLE = 0x00000000, - SDMA_PERF_SEL_IDLE = 0x00000001, - SDMA_PERF_SEL_REG_IDLE = 0x00000002, - SDMA_PERF_SEL_RB_EMPTY = 0x00000003, - SDMA_PERF_SEL_RB_FULL = 0x00000004, - SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, - SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, - SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, - SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, - SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, - SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, - SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, - SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, - SDMA_PERF_SEL_EX_IDLE = 0x0000000d, - SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, - SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, - SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, - SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, - SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, - SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, - SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, - SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, - SDMA_PERF_SEL_DRM_IDLE = 0x00000016, - SDMA_PERF_SEL_DRM_REQ_STALL = 0x00000017, - SDMA_PERF_SEL_SEM_IDLE = 0x00000018, - SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, - SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, - SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, - SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, - SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, - SDMA_PERF_SEL_INT_IDLE = 0x0000001e, - SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, - SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, - SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, - SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, - SDMA_PERF_SEL_NUM_PACKET = 0x00000023, - SDMA_PERF_SEL_DRM1_REQ_STALL = 0x00000024, - SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, - SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, - SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, - SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, - SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, - SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, - SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, - SDMA_PERF_SEL_CE_DRM_IDLE = 0x0000002c, - SDMA_PERF_SEL_CE_DRM1_IDLE = 0x0000002d, - SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, - SDMA_PERF_SEL_CE_DRM_FULL = 0x0000002f, - SDMA_PERF_SEL_CE_DRM1_FULL = 0x00000030, - SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, - SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, - SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, - SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, - SDMA_PERF_SEL_GFX_SELECT = 0x00000035, - SDMA_PERF_SEL_RLC0_SELECT = 0x00000036, - SDMA_PERF_SEL_RLC1_SELECT = 0x00000037, - SDMA_PERF_SEL_PAGE_SELECT = 0x00000038, - SDMA_PERF_SEL_CTX_CHANGE = 0x00000039, - SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, - SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, - SDMA_PERF_SEL_DOORBELL = 0x0000003c, - SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, - SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, - SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, - SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, - SDMA_PERF_SEL_CE_L1_STALL = 0x00000041, - SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042, - SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043, - SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044, - SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045, - SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046, - SDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047, - SDMA_PERF_SEL_ATCL2_FREE = 0x00000048, - SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049, - SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a, - SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b, - SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c, - SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d, - SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e, - SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f, - SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050, - SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051, - SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052, - SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053, - SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054, - SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055, - SDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056, - SDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057, - SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058, - SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059, - SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a, - SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b, - SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c, - SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d, - SDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e, - SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x000000fe, - SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x000000ff, -} SDMA_PERF_SEL; - -/******************************************************* - * SDMA1 Enums - *******************************************************/ - -/******************************************************* - * MP0_CRU Enums - *******************************************************/ - -/******************************************************* - * MP0_CRU_SMN Enums - *******************************************************/ - -/******************************************************* - * MP0_CRU_RSMU Enums - *******************************************************/ - -/******************************************************* - * MP0_MMU Enums - *******************************************************/ - -/******************************************************* - * MP0_HUBIF Enums - *******************************************************/ - -/******************************************************* - * MP1_CRU Enums - *******************************************************/ - -/******************************************************* - * MP1_CRU_SMN Enums - *******************************************************/ - -/******************************************************* - * MP1_CRU_RSMU Enums - *******************************************************/ - -/******************************************************* - * MP1_MMU Enums - *******************************************************/ - -/******************************************************* - * MP1_HUBIF Enums - *******************************************************/ - -/******************************************************* - * MP_HUBIF Enums - *******************************************************/ - -/******************************************************* - * MP_HUBIF_NB Enums - *******************************************************/ - -/******************************************************* - * MP_SMNIF Enums - *******************************************************/ - -/******************************************************* - * MP_ROM Enums - *******************************************************/ - -/******************************************************* - * MP_DMAC Enums - *******************************************************/ - -/******************************************************* - * SMUIO Enums - *******************************************************/ - -/* - * ROM_SIGNATURE value - */ - -#define ROM_SIGNATURE 0x0000aa55 - -/******************************************************* - * GDS Enums - *******************************************************/ - -/******************************************************* - * CB Enums - *******************************************************/ - -/* - * SurfaceNumber enum - */ - -typedef enum SurfaceNumber { - NUMBER_UNORM = 0x00000000, - NUMBER_SNORM = 0x00000001, - NUMBER_USCALED = 0x00000002, - NUMBER_SSCALED = 0x00000003, - NUMBER_UINT = 0x00000004, - NUMBER_SINT = 0x00000005, - NUMBER_SRGB = 0x00000006, - NUMBER_FLOAT = 0x00000007, -} SurfaceNumber; - -/* - * SurfaceSwap enum - */ - -typedef enum SurfaceSwap { - SWAP_STD = 0x00000000, - SWAP_ALT = 0x00000001, - SWAP_STD_REV = 0x00000002, - SWAP_ALT_REV = 0x00000003, -} SurfaceSwap; - -/* - * CBMode enum - */ - -typedef enum CBMode { - CB_DISABLE = 0x00000000, - CB_NORMAL = 0x00000001, - CB_ELIMINATE_FAST_CLEAR = 0x00000002, - CB_RESOLVE = 0x00000003, - CB_DECOMPRESS = 0x00000004, - CB_FMASK_DECOMPRESS = 0x00000005, - CB_DCC_DECOMPRESS = 0x00000006, -} CBMode; - -/* - * RoundMode enum - */ - -typedef enum RoundMode { - ROUND_BY_HALF = 0x00000000, - ROUND_TRUNCATE = 0x00000001, -} RoundMode; - -/* - * BlendOp enum - */ - -typedef enum BlendOp { - BLEND_ZERO = 0x00000000, - BLEND_ONE = 0x00000001, - BLEND_SRC_COLOR = 0x00000002, - BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, - BLEND_SRC_ALPHA = 0x00000004, - BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, - BLEND_DST_ALPHA = 0x00000006, - BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, - BLEND_DST_COLOR = 0x00000008, - BLEND_ONE_MINUS_DST_COLOR = 0x00000009, - BLEND_SRC_ALPHA_SATURATE = 0x0000000a, - BLEND_BOTH_SRC_ALPHA = 0x0000000b, - BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c, - BLEND_CONSTANT_COLOR = 0x0000000d, - BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e, - BLEND_SRC1_COLOR = 0x0000000f, - BLEND_INV_SRC1_COLOR = 0x00000010, - BLEND_SRC1_ALPHA = 0x00000011, - BLEND_INV_SRC1_ALPHA = 0x00000012, - BLEND_CONSTANT_ALPHA = 0x00000013, - BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014, -} BlendOp; - -/* - * CombFunc enum - */ - -typedef enum CombFunc { - COMB_DST_PLUS_SRC = 0x00000000, - COMB_SRC_MINUS_DST = 0x00000001, - COMB_MIN_DST_SRC = 0x00000002, - COMB_MAX_DST_SRC = 0x00000003, - COMB_DST_MINUS_SRC = 0x00000004, -} CombFunc; - -/* - * BlendOpt enum - */ - -typedef enum BlendOpt { - FORCE_OPT_AUTO = 0x00000000, - FORCE_OPT_DISABLE = 0x00000001, - FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, - FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, - FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, - FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, - FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, - FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, -} BlendOpt; - -/* - * CmaskCode enum - */ - -typedef enum CmaskCode { - CMASK_CLR00_F0 = 0x00000000, - CMASK_CLR00_F1 = 0x00000001, - CMASK_CLR00_F2 = 0x00000002, - CMASK_CLR00_FX = 0x00000003, - CMASK_CLR01_F0 = 0x00000004, - CMASK_CLR01_F1 = 0x00000005, - CMASK_CLR01_F2 = 0x00000006, - CMASK_CLR01_FX = 0x00000007, - CMASK_CLR10_F0 = 0x00000008, - CMASK_CLR10_F1 = 0x00000009, - CMASK_CLR10_F2 = 0x0000000a, - CMASK_CLR10_FX = 0x0000000b, - CMASK_CLR11_F0 = 0x0000000c, - CMASK_CLR11_F1 = 0x0000000d, - CMASK_CLR11_F2 = 0x0000000e, - CMASK_CLR11_FX = 0x0000000f, -} CmaskCode; - -/* - * MemArbMode enum - */ - -typedef enum MemArbMode { - MEM_ARB_MODE_FIXED = 0x00000000, - MEM_ARB_MODE_AGE = 0x00000001, - MEM_ARB_MODE_WEIGHT = 0x00000002, - MEM_ARB_MODE_BOTH = 0x00000003, -} MemArbMode; - -/* - * CBPerfOpFilterSel enum - */ - -typedef enum CBPerfOpFilterSel { - CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, - CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, - CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, - CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, - CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, - CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, -} CBPerfOpFilterSel; - -/* - * CBPerfClearFilterSel enum - */ - -typedef enum CBPerfClearFilterSel { - CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, - CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, -} CBPerfClearFilterSel; - -/* - * CBPerfSel enum - */ - -typedef enum CBPerfSel { - CB_PERF_SEL_NONE = 0x00000000, - CB_PERF_SEL_BUSY = 0x00000001, - CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002, - CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003, - CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004, - CB_PERF_SEL_DRAWN_QUAD = 0x00000005, - CB_PERF_SEL_DRAWN_PIXEL = 0x00000006, - CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007, - CB_PERF_SEL_DRAWN_TILE = 0x00000008, - CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009, - CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a, - CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b, - CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c, - CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d, - CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e, - CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f, - CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010, - CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011, - CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012, - CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013, - CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014, - CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015, - CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016, - CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e, - CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f, - CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020, - CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021, - CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022, - CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023, - CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024, - CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025, - CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026, - CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027, - CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028, - CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029, - CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a, - CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b, - CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c, - CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d, - CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e, - CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f, - CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030, - CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031, - CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032, - CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033, - CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034, - CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035, - CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036, - CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a, - CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e, - CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f, - CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040, - CB_PERF_SEL_CM_CACHE_HIT = 0x00000041, - CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042, - CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043, - CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044, - CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045, - CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046, - CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047, - CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048, - CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049, - CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a, - CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b, - CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c, - CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d, - CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e, - CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f, - CB_PERF_SEL_FC_CACHE_HIT = 0x00000050, - CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051, - CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052, - CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053, - CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054, - CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055, - CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056, - CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057, - CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058, - CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059, - CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a, - CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b, - CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c, - CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d, - CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e, - CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f, - CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060, - CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061, - CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062, - CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063, - CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064, - CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065, - CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066, - CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067, - CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068, - CB_PERF_SEL_CC_CACHE_STALL = 0x00000069, - CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a, - CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b, - CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c, - CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d, - CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e, - CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x0000006f, - CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x00000070, - CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000071, - CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000072, - CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000073, - CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000074, - CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000075, - CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000076, - CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077, - CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078, - CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000079, - CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x0000007a, - CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007b, - CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007c, - CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007d, - CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007e, - CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007f, - CB_PERF_SEL_CC_MC_READ_REQUEST = 0x00000080, - CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081, - CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082, - CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000083, - CB_PERF_SEL_CM_TQ_FULL = 0x00000084, - CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000085, - CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086, - CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087, - CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088, - CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x00000089, - CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008a, - CB_PERF_SEL_CC_SF_FULL = 0x0000008b, - CB_PERF_SEL_CC_RB_FULL = 0x0000008c, - CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x0000008d, - CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x0000008e, - CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x0000008f, - CB_PERF_SEL_EVENT = 0x00000090, - CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000091, - CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000092, - CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000093, - CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000094, - CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000095, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000096, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000097, - CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000098, - CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x00000099, - CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009a, - CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x0000009b, - CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x0000009c, - CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x0000009d, - CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x0000009e, - CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x0000009f, - CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a0, - CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a1, - CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a2, - CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a3, - CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a4, - CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000a5, - CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000a6, - CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000a7, - CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000a8, - CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000a9, - CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000aa, - CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000ab, - CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000ac, - CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000ad, - CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000ae, - CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000af, - CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b0, - CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b1, - CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b2, - CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b3, - CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b4, - CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000b5, - CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000b6, - CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000b7, - CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000b8, - CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000b9, - CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000ba, - CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000bb, - CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000bc, - CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000bd, - CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000be, - CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000bf, - CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c0, - CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c1, - CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c2, - CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c3, - CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c4, - CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000c5, - CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000c6, - CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000c7, - CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000c8, - CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000c9, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000ca, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000cb, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000cc, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000cd, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000ce, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000cf, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d0, - CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d1, - CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d2, - CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d3, - CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d4, - CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000d5, - CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000d6, - CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000d7, - CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000d8, - CB_PERF_SEL_DRAWN_BUSY = 0x000000d9, - CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000da, - CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000db, - CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000dc, - CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000dd, - CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000de, - CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000df, - CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e0, - CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e1, - CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e2, - CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e3, - CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000e4, - CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000e5, - CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000e6, - CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000e7, - CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000e8, - CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000e9, - CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000ea, - CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000eb, - CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000ec, - CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000ed, - CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000ee, - CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000ef, - CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f0, - CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f1, - CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f2, - CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f3, - CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000f4, - CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000f5, - CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000f6, - CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000f7, - CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000f8, - CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000f9, - CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x000000fa, - CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x000000fb, - CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x000000fc, - CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x000000fd, - CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x000000fe, - CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000ff, - CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000100, - CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000101, - CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000102, - CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000103, - CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x00000104, - CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x00000105, - CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x00000106, - CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x00000107, - CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x00000108, - CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x00000109, - CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x0000010a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x0000010b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000010c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000010d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x0000010e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x0000010f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000110, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000111, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000112, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x00000114, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000115, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x00000116, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x00000117, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118, - CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000119, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x0000011a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x0000011b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x0000011c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x0000011d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x0000011e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x0000011f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000120, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000121, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000122, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000123, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x00000124, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x00000125, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x00000126, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x00000127, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x00000128, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x00000129, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x0000012a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x0000012b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x0000012c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x0000012d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x0000012e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x0000012f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000130, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000131, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000132, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000133, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x00000134, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x00000135, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x00000136, - CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x00000137, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000138, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000139, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000140, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000141, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000142, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000143, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000144, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000145, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000146, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x00000147, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x00000148, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x00000149, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x0000014a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x0000014b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x0000014c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x0000014d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000150, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000151, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000152, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000153, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000154, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000155, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x00000156, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x00000157, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x00000158, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x00000159, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x0000015a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x0000015b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x0000015c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x0000015d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x0000015e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x0000015f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000160, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000161, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000162, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000163, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x00000164, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x00000165, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x00000166, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x00000167, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x00000168, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x00000169, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x0000016a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x0000016b, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x0000016c, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x0000016d, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x0000016e, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x0000016f, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000170, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000171, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000172, - CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000173, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x00000174, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x00000175, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x00000176, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x00000177, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x00000178, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x00000179, - CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x0000017a, - CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x0000017b, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x0000017c, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x0000017d, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x0000017e, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x0000017f, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000180, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000181, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000182, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000183, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x00000184, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x00000185, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x00000186, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x00000187, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x00000188, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x00000189, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x0000018a, - CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x0000018b, - CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x0000018c, - CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x0000018d, - CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x0000018e, - CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x0000018f, - CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000190, - CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000191, - CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000192, - CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000193, - CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x00000194, - CB_PERF_SEL_NACK_CM_READ = 0x00000195, - CB_PERF_SEL_NACK_CM_WRITE = 0x00000196, - CB_PERF_SEL_NACK_FC_READ = 0x00000197, - CB_PERF_SEL_NACK_FC_WRITE = 0x00000198, - CB_PERF_SEL_NACK_DC_READ = 0x00000199, - CB_PERF_SEL_NACK_DC_WRITE = 0x0000019a, - CB_PERF_SEL_NACK_CC_READ = 0x0000019b, - CB_PERF_SEL_NACK_CC_WRITE = 0x0000019c, - CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN = 0x0000019d, - CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN = 0x0000019e, - CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN = 0x0000019f, - CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN = 0x000001a0, - CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a1, - CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a2, - CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a3, - CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a4, - CB_PERF_SEL_CM_MC_WRITE_ACK64B = 0x000001a5, - CB_PERF_SEL_FC_MC_WRITE_ACK64B = 0x000001a6, - CB_PERF_SEL_DC_MC_WRITE_ACK64B = 0x000001a7, - CB_PERF_SEL_CC_MC_WRITE_ACK64B = 0x000001a8, - CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 0x000001a9, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS = 0x000001aa, - CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA = 0x000001ab, - CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT = 0x000001ac, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX = 0x000001ad, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX = 0x000001ae, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX = 0x000001af, - CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX = 0x000001b0, - CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED = 0x000001b1, - CB_PERF_SEL_DB_CB_CONTEXT_DONE = 0x000001b2, - CB_PERF_SEL_DB_CB_EOP_DONE = 0x000001b3, - CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL = 0x000001b4, - CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD = 0x000001b5, -} CBPerfSel; - -/* - * CmaskAddr enum - */ - -typedef enum CmaskAddr { - CMASK_ADDR_TILED = 0x00000000, - CMASK_ADDR_LINEAR = 0x00000001, - CMASK_ADDR_COMPATIBLE = 0x00000002, -} CmaskAddr; - -/* - * SourceFormat enum - */ - -typedef enum SourceFormat { - EXPORT_4C_32BPC = 0x00000000, - EXPORT_4C_16BPC = 0x00000001, - EXPORT_2C_32BPC_GR = 0x00000002, - EXPORT_2C_32BPC_AR = 0x00000003, -} SourceFormat; - -/******************************************************* - * SC Enums - *******************************************************/ - -/******************************************************* - * TC Enums - *******************************************************/ - -/* - * TC_OP_MASKS enum - */ - -typedef enum TC_OP_MASKS { - TC_OP_MASK_FLUSH_DENROM = 0x00000008, - TC_OP_MASK_64 = 0x00000020, - TC_OP_MASK_NO_RTN = 0x00000040, -} TC_OP_MASKS; - -/* - * TC_OP enum - */ - -typedef enum TC_OP { - TC_OP_READ = 0x00000000, - TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, - TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, - TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, - TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, - TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005, - TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, - TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, - TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, - TC_OP_PROBE_FILTER = 0x0000000c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, - TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, - TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, - TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, - TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, - TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, - TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, - TC_OP_ATOMIC_AND_RTN_32 = 0x00000015, - TC_OP_ATOMIC_OR_RTN_32 = 0x00000016, - TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017, - TC_OP_ATOMIC_INC_RTN_32 = 0x00000018, - TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019, - TC_OP_WBINVL1_VOL = 0x0000001a, - TC_OP_WBINVL1_SD = 0x0000001b, - TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c, - TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d, - TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e, - TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f, - TC_OP_WRITE = 0x00000020, - TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, - TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, - TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, - TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, - TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, - TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, - TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, - TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, - TC_OP_WBINVL2_SD = 0x0000002c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e, - TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, - TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, - TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, - TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, - TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, - TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, - TC_OP_ATOMIC_AND_RTN_64 = 0x00000035, - TC_OP_ATOMIC_OR_RTN_64 = 0x00000036, - TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037, - TC_OP_ATOMIC_INC_RTN_64 = 0x00000038, - TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039, - TC_OP_WBL2_NC = 0x0000003a, - TC_OP_WBL2_WC = 0x0000003b, - TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, - TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, - TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, - TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, - TC_OP_WBINVL1 = 0x00000040, - TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, - TC_OP_ATOMIC_FMIN_32 = 0x00000042, - TC_OP_ATOMIC_FMAX_32 = 0x00000043, - TC_OP_RESERVED_FOP_32_0 = 0x00000044, - TC_OP_RESERVED_FOP_32_1 = 0x00000045, - TC_OP_RESERVED_FOP_32_2 = 0x00000046, - TC_OP_ATOMIC_SWAP_32 = 0x00000047, - TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, - TC_OP_INV_METADATA = 0x0000004c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, - TC_OP_ATOMIC_ADD_32 = 0x0000004f, - TC_OP_ATOMIC_SUB_32 = 0x00000050, - TC_OP_ATOMIC_SMIN_32 = 0x00000051, - TC_OP_ATOMIC_UMIN_32 = 0x00000052, - TC_OP_ATOMIC_SMAX_32 = 0x00000053, - TC_OP_ATOMIC_UMAX_32 = 0x00000054, - TC_OP_ATOMIC_AND_32 = 0x00000055, - TC_OP_ATOMIC_OR_32 = 0x00000056, - TC_OP_ATOMIC_XOR_32 = 0x00000057, - TC_OP_ATOMIC_INC_32 = 0x00000058, - TC_OP_ATOMIC_DEC_32 = 0x00000059, - TC_OP_INVL2_NC = 0x0000005a, - TC_OP_NOP_RTN0 = 0x0000005b, - TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, - TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, - TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, - TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, - TC_OP_WBINVL2 = 0x00000060, - TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, - TC_OP_ATOMIC_FMIN_64 = 0x00000062, - TC_OP_ATOMIC_FMAX_64 = 0x00000063, - TC_OP_RESERVED_FOP_64_0 = 0x00000064, - TC_OP_RESERVED_FOP_64_1 = 0x00000065, - TC_OP_RESERVED_FOP_64_2 = 0x00000066, - TC_OP_ATOMIC_SWAP_64 = 0x00000067, - TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, - TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, - TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, - TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, - TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, - TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, - TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, - TC_OP_ATOMIC_ADD_64 = 0x0000006f, - TC_OP_ATOMIC_SUB_64 = 0x00000070, - TC_OP_ATOMIC_SMIN_64 = 0x00000071, - TC_OP_ATOMIC_UMIN_64 = 0x00000072, - TC_OP_ATOMIC_SMAX_64 = 0x00000073, - TC_OP_ATOMIC_UMAX_64 = 0x00000074, - TC_OP_ATOMIC_AND_64 = 0x00000075, - TC_OP_ATOMIC_OR_64 = 0x00000076, - TC_OP_ATOMIC_XOR_64 = 0x00000077, - TC_OP_ATOMIC_INC_64 = 0x00000078, - TC_OP_ATOMIC_DEC_64 = 0x00000079, - TC_OP_WBINVL2_NC = 0x0000007a, - TC_OP_NOP_ACK = 0x0000007b, - TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, - TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, - TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, - TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, -} TC_OP; - -/* - * TC_NACKS enum - */ - -typedef enum TC_NACKS { - TC_NACK_NO_FAULT = 0x00000000, - TC_NACK_PAGE_FAULT = 0x00000001, - TC_NACK_PROTECTION_FAULT = 0x00000002, - TC_NACK_DATA_ERROR = 0x00000003, -} TC_NACKS; - -/* - * TC_EA_CID enum - */ - -typedef enum TC_EA_CID { - TC_EA_CID_RT = 0x00000000, - TC_EA_CID_FMASK = 0x00000001, - TC_EA_CID_DCC = 0x00000002, - TC_EA_CID_TCPMETA = 0x00000003, - TC_EA_CID_Z = 0x00000004, - TC_EA_CID_STENCIL = 0x00000005, - TC_EA_CID_HTILE = 0x00000006, - TC_EA_CID_MISC = 0x00000007, - TC_EA_CID_TCP = 0x00000008, - TC_EA_CID_SQC = 0x00000009, - TC_EA_CID_CPF = 0x0000000a, - TC_EA_CID_CPG = 0x0000000b, - TC_EA_CID_IA = 0x0000000c, - TC_EA_CID_WD = 0x0000000d, - TC_EA_CID_PA = 0x0000000e, - TC_EA_CID_UTCL2_TPI = 0x0000000f, -} TC_EA_CID; - -/******************************************************* - * GC_CAC Enums - *******************************************************/ - -/******************************************************* - * RLC Enums - *******************************************************/ - -/******************************************************* - * SPI Enums - *******************************************************/ - -/* - * SPI_SAMPLE_CNTL enum - */ - -typedef enum SPI_SAMPLE_CNTL { - CENTROIDS_ONLY = 0x00000000, - CENTERS_ONLY = 0x00000001, - CENTROIDS_AND_CENTERS = 0x00000002, - UNDEF = 0x00000003, -} SPI_SAMPLE_CNTL; - -/* - * SPI_FOG_MODE enum - */ - -typedef enum SPI_FOG_MODE { - SPI_FOG_NONE = 0x00000000, - SPI_FOG_EXP = 0x00000001, - SPI_FOG_EXP2 = 0x00000002, - SPI_FOG_LINEAR = 0x00000003, -} SPI_FOG_MODE; - -/* - * SPI_PNT_SPRITE_OVERRIDE enum - */ - -typedef enum SPI_PNT_SPRITE_OVERRIDE { - SPI_PNT_SPRITE_SEL_0 = 0x00000000, - SPI_PNT_SPRITE_SEL_1 = 0x00000001, - SPI_PNT_SPRITE_SEL_S = 0x00000002, - SPI_PNT_SPRITE_SEL_T = 0x00000003, - SPI_PNT_SPRITE_SEL_NONE = 0x00000004, -} SPI_PNT_SPRITE_OVERRIDE; - -/* - * SPI_PERFCNT_SEL enum - */ - -typedef enum SPI_PERFCNT_SEL { - SPI_PERF_VS_WINDOW_VALID = 0x00000000, - SPI_PERF_VS_BUSY = 0x00000001, - SPI_PERF_VS_FIRST_WAVE = 0x00000002, - SPI_PERF_VS_LAST_WAVE = 0x00000003, - SPI_PERF_VS_LSHS_DEALLOC = 0x00000004, - SPI_PERF_VS_PC_STALL = 0x00000005, - SPI_PERF_VS_POS0_STALL = 0x00000006, - SPI_PERF_VS_POS1_STALL = 0x00000007, - SPI_PERF_VS_CRAWLER_STALL = 0x00000008, - SPI_PERF_VS_EVENT_WAVE = 0x00000009, - SPI_PERF_VS_WAVE = 0x0000000a, - SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b, - SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c, - SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d, - SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e, - SPI_PERF_VS_LAST_SUBGRP = 0x0000000f, - SPI_PERF_VS_ALLOC_CNT = 0x00000010, - SPI_PERF_VS_PC_ALLOC_CNT = 0x00000011, - SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x00000012, - SPI_PERF_GS_WINDOW_VALID = 0x00000013, - SPI_PERF_GS_BUSY = 0x00000014, - SPI_PERF_GS_CRAWLER_STALL = 0x00000015, - SPI_PERF_GS_EVENT_WAVE = 0x00000016, - SPI_PERF_GS_WAVE = 0x00000017, - SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000018, - SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000019, - SPI_PERF_GS_FIRST_SUBGRP = 0x0000001a, - SPI_PERF_GS_LAST_SUBGRP = 0x0000001b, - SPI_PERF_GS_HS_DEALLOC = 0x0000001c, - SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000001d, - SPI_PERF_GS_GRP_FIFO_FULL = 0x0000001e, - SPI_PERF_HS_WINDOW_VALID = 0x0000001f, - SPI_PERF_HS_BUSY = 0x00000020, - SPI_PERF_HS_CRAWLER_STALL = 0x00000021, - SPI_PERF_HS_FIRST_WAVE = 0x00000022, - SPI_PERF_HS_LAST_WAVE = 0x00000023, - SPI_PERF_HS_OFFCHIP_LDS_STALL = 0x00000024, - SPI_PERF_HS_EVENT_WAVE = 0x00000025, - SPI_PERF_HS_WAVE = 0x00000026, - SPI_PERF_HS_PERS_UPD_FULL0 = 0x00000027, - SPI_PERF_HS_PERS_UPD_FULL1 = 0x00000028, - SPI_PERF_CSG_WINDOW_VALID = 0x00000029, - SPI_PERF_CSG_BUSY = 0x0000002a, - SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000002b, - SPI_PERF_CSG_CRAWLER_STALL = 0x0000002c, - SPI_PERF_CSG_EVENT_WAVE = 0x0000002d, - SPI_PERF_CSG_WAVE = 0x0000002e, - SPI_PERF_CSN_WINDOW_VALID = 0x0000002f, - SPI_PERF_CSN_BUSY = 0x00000030, - SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000031, - SPI_PERF_CSN_CRAWLER_STALL = 0x00000032, - SPI_PERF_CSN_EVENT_WAVE = 0x00000033, - SPI_PERF_CSN_WAVE = 0x00000034, - SPI_PERF_PS_WINDOW_VALID = 0x00000035, - SPI_PERF_PS_BUSY = 0x00000036, - SPI_PERF_PS_ACTIVE = 0x00000037, - SPI_PERF_PS_DEALLOC_BIN0 = 0x00000038, - SPI_PERF_PS_FPOS_BIN1_STALL = 0x00000039, - SPI_PERF_PS_EVENT_WAVE = 0x0000003a, - SPI_PERF_PS_WAVE = 0x0000003b, - SPI_PERF_PS_OPT_WAVE = 0x0000003c, - SPI_PERF_PS_PASS_BIN0 = 0x0000003d, - SPI_PERF_PS_PASS_BIN1 = 0x0000003e, - SPI_PERF_PS_FPOS_BIN2 = 0x0000003f, - SPI_PERF_PS_PRIM_BIN0 = 0x00000040, - SPI_PERF_PS_PRIM_BIN1 = 0x00000041, - SPI_PERF_PS_CNF_BIN2 = 0x00000042, - SPI_PERF_PS_CNF_BIN3 = 0x00000043, - SPI_PERF_PS_CRAWLER_STALL = 0x00000044, - SPI_PERF_PS_LDS_RES_FULL = 0x00000045, - SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000046, - SPI_PERF_PS_PERS_UPD_FULL1 = 0x00000047, - SPI_PERF_PS_POPS_WAVE_SENT = 0x00000048, - SPI_PERF_PS_POPS_WAVE_EXIT = 0x00000049, - SPI_PERF_LDS0_PC_VALID = 0x0000004a, - SPI_PERF_LDS1_PC_VALID = 0x0000004b, - SPI_PERF_RA_PIPE_REQ_BIN2 = 0x0000004c, - SPI_PERF_RA_TASK_REQ_BIN3 = 0x0000004d, - SPI_PERF_RA_WR_CTL_FULL = 0x0000004e, - SPI_PERF_RA_REQ_NO_ALLOC = 0x0000004f, - SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000050, - SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x00000051, - SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000052, - SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000053, - SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x00000054, - SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x00000055, - SPI_PERF_RA_RES_STALL_PS = 0x00000056, - SPI_PERF_RA_RES_STALL_VS = 0x00000057, - SPI_PERF_RA_RES_STALL_GS = 0x00000058, - SPI_PERF_RA_RES_STALL_HS = 0x00000059, - SPI_PERF_RA_RES_STALL_CSG = 0x0000005a, - SPI_PERF_RA_RES_STALL_CSN = 0x0000005b, - SPI_PERF_RA_TMP_STALL_PS = 0x0000005c, - SPI_PERF_RA_TMP_STALL_VS = 0x0000005d, - SPI_PERF_RA_TMP_STALL_GS = 0x0000005e, - SPI_PERF_RA_TMP_STALL_HS = 0x0000005f, - SPI_PERF_RA_TMP_STALL_CSG = 0x00000060, - SPI_PERF_RA_TMP_STALL_CSN = 0x00000061, - SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x00000062, - SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x00000063, - SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x00000064, - SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000065, - SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x00000066, - SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x00000067, - SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x00000068, - SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x00000069, - SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x0000006a, - SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x0000006b, - SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x0000006c, - SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x0000006d, - SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x0000006e, - SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x0000006f, - SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x00000070, - SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x00000071, - SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x00000072, - SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x00000073, - SPI_PERF_RA_LDS_CU_FULL_PS = 0x00000074, - SPI_PERF_RA_LDS_CU_FULL_LS = 0x00000075, - SPI_PERF_RA_LDS_CU_FULL_ES = 0x00000076, - SPI_PERF_RA_LDS_CU_FULL_CSG = 0x00000077, - SPI_PERF_RA_LDS_CU_FULL_CSN = 0x00000078, - SPI_PERF_RA_BAR_CU_FULL_HS = 0x00000079, - SPI_PERF_RA_BAR_CU_FULL_CSG = 0x0000007a, - SPI_PERF_RA_BAR_CU_FULL_CSN = 0x0000007b, - SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x0000007c, - SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x0000007d, - SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x0000007e, - SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x0000007f, - SPI_PERF_RA_WVLIM_STALL_PS = 0x00000080, - SPI_PERF_RA_WVLIM_STALL_VS = 0x00000081, - SPI_PERF_RA_WVLIM_STALL_GS = 0x00000082, - SPI_PERF_RA_WVLIM_STALL_HS = 0x00000083, - SPI_PERF_RA_WVLIM_STALL_CSG = 0x00000084, - SPI_PERF_RA_WVLIM_STALL_CSN = 0x00000085, - SPI_PERF_RA_VS_LOCK = 0x00000086, - SPI_PERF_RA_GS_LOCK = 0x00000087, - SPI_PERF_RA_HS_LOCK = 0x00000088, - SPI_PERF_RA_CSG_LOCK = 0x00000089, - SPI_PERF_RA_CSN_LOCK = 0x0000008a, - SPI_PERF_RA_RSV_UPD = 0x0000008b, - SPI_PERF_EXP_ARB_COL_CNT = 0x0000008c, - SPI_PERF_EXP_ARB_PAR_CNT = 0x0000008d, - SPI_PERF_EXP_ARB_POS_CNT = 0x0000008e, - SPI_PERF_EXP_ARB_GDS_CNT = 0x0000008f, - SPI_PERF_NUM_PS_COL_R0_EXPORTS = 0x00000090, - SPI_PERF_NUM_PS_COL_R1_EXPORTS = 0x00000091, - SPI_PERF_NUM_VS_POS_R0_EXPORTS = 0x00000092, - SPI_PERF_NUM_VS_POS_R1_EXPORTS = 0x00000093, - SPI_PERF_NUM_VS_PARAM_R0_EXPORTS = 0x00000094, - SPI_PERF_NUM_VS_PARAM_R1_EXPORTS = 0x00000095, - SPI_PERF_NUM_VS_GDS_R0_EXPORTS = 0x00000096, - SPI_PERF_NUM_VS_GDS_R1_EXPORTS = 0x00000097, - SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x00000098, - SPI_PERF_CLKGATE_BUSY_STALL = 0x00000099, - SPI_PERF_CLKGATE_ACTIVE_STALL = 0x0000009a, - SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x0000009b, - SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x0000009c, - SPI_PERF_CLKGATE_CGTT_REG_ON = 0x0000009d, - SPI_PERF_PIX_ALLOC_PEND_CNT = 0x0000009e, - SPI_PERF_PIX_ALLOC_SCB_STALL = 0x0000009f, - SPI_PERF_PIX_ALLOC_DB0_STALL = 0x000000a0, - SPI_PERF_PIX_ALLOC_DB1_STALL = 0x000000a1, - SPI_PERF_PIX_ALLOC_DB2_STALL = 0x000000a2, - SPI_PERF_PIX_ALLOC_DB3_STALL = 0x000000a3, - SPI_PERF_PC_ALLOC_ACCUM = 0x000000a4, - SPI_PERF_GS_NGG_SE_HAS_BATON = 0x000000a5, - SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON = 0x000000a6, - SPI_PERF_GS_NGG_SE_FORWARDED_BATON = 0x000000a7, - SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT = 0x000000a8, - SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT = 0x000000a9, - SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT = 0x000000aa, - SPI_PERF_GS_NGG_PC_FULL = 0x000000ab, - SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x000000ac, - SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY = 0x000000ad, - SPI_PERF_GSC_VTX_BUSY = 0x000000ae, - SPI_PERF_GSC_VTX_INPUT_STARVED = 0x000000af, - SPI_PERF_GSC_VTX_VSR_STALL = 0x000000b0, - SPI_PERF_GSC_VTX_VSR_FULL = 0x000000b1, - SPI_PERF_GSC_VTX_CAC_BUSY = 0x000000b2, - SPI_PERF_ESC_VTX_BUSY = 0x000000b3, - SPI_PERF_ESC_VTX_INPUT_STARVED = 0x000000b4, - SPI_PERF_ESC_VTX_VSR_STALL = 0x000000b5, - SPI_PERF_ESC_VTX_VSR_FULL = 0x000000b6, - SPI_PERF_ESC_VTX_CAC_BUSY = 0x000000b7, - SPI_PERF_SWC_PS_WR = 0x000000b8, - SPI_PERF_SWC_VS_WR = 0x000000b9, - SPI_PERF_SWC_GS_WR = 0x000000ba, - SPI_PERF_SWC_HS_WR = 0x000000bb, - SPI_PERF_SWC_CSG_WR = 0x000000bc, - SPI_PERF_SWC_CSC_WR = 0x000000bd, - SPI_PERF_VWC_PS_WR = 0x000000be, - SPI_PERF_VWC_VS_WR = 0x000000bf, - SPI_PERF_VWC_GS_WR = 0x000000c0, - SPI_PERF_VWC_HS_WR = 0x000000c1, - SPI_PERF_VWC_CSG_WR = 0x000000c2, - SPI_PERF_VWC_CSC_WR = 0x000000c3, -} SPI_PERFCNT_SEL; - -/* - * SPI_SHADER_FORMAT enum - */ - -typedef enum SPI_SHADER_FORMAT { - SPI_SHADER_NONE = 0x00000000, - SPI_SHADER_1COMP = 0x00000001, - SPI_SHADER_2COMP = 0x00000002, - SPI_SHADER_4COMPRESS = 0x00000003, - SPI_SHADER_4COMP = 0x00000004, -} SPI_SHADER_FORMAT; - -/* - * SPI_SHADER_EX_FORMAT enum - */ - -typedef enum SPI_SHADER_EX_FORMAT { - SPI_SHADER_ZERO = 0x00000000, - SPI_SHADER_32_R = 0x00000001, - SPI_SHADER_32_GR = 0x00000002, - SPI_SHADER_32_AR = 0x00000003, - SPI_SHADER_FP16_ABGR = 0x00000004, - SPI_SHADER_UNORM16_ABGR = 0x00000005, - SPI_SHADER_SNORM16_ABGR = 0x00000006, - SPI_SHADER_UINT16_ABGR = 0x00000007, - SPI_SHADER_SINT16_ABGR = 0x00000008, - SPI_SHADER_32_ABGR = 0x00000009, -} SPI_SHADER_EX_FORMAT; - -/* - * CLKGATE_SM_MODE enum - */ - -typedef enum CLKGATE_SM_MODE { - ON_SEQ = 0x00000000, - OFF_SEQ = 0x00000001, - PROG_SEQ = 0x00000002, - READ_SEQ = 0x00000003, - SM_MODE_RESERVED = 0x00000004, -} CLKGATE_SM_MODE; - -/* - * CLKGATE_BASE_MODE enum - */ - -typedef enum CLKGATE_BASE_MODE { - MULT_8 = 0x00000000, - MULT_16 = 0x00000001, -} CLKGATE_BASE_MODE; - -/******************************************************* - * SQ Enums - *******************************************************/ - -/* - * SQ_TEX_CLAMP enum - */ - -typedef enum SQ_TEX_CLAMP { - SQ_TEX_WRAP = 0x00000000, - SQ_TEX_MIRROR = 0x00000001, - SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, - SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, - SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, - SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, - SQ_TEX_CLAMP_BORDER = 0x00000006, - SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, -} SQ_TEX_CLAMP; - -/* - * SQ_TEX_XY_FILTER enum - */ - -typedef enum SQ_TEX_XY_FILTER { - SQ_TEX_XY_FILTER_POINT = 0x00000000, - SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, - SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, - SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, -} SQ_TEX_XY_FILTER; - -/* - * SQ_TEX_Z_FILTER enum - */ - -typedef enum SQ_TEX_Z_FILTER { - SQ_TEX_Z_FILTER_NONE = 0x00000000, - SQ_TEX_Z_FILTER_POINT = 0x00000001, - SQ_TEX_Z_FILTER_LINEAR = 0x00000002, -} SQ_TEX_Z_FILTER; - -/* - * SQ_TEX_MIP_FILTER enum - */ - -typedef enum SQ_TEX_MIP_FILTER { - SQ_TEX_MIP_FILTER_NONE = 0x00000000, - SQ_TEX_MIP_FILTER_POINT = 0x00000001, - SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, - SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003, -} SQ_TEX_MIP_FILTER; - -/* - * SQ_TEX_ANISO_RATIO enum - */ - -typedef enum SQ_TEX_ANISO_RATIO { - SQ_TEX_ANISO_RATIO_1 = 0x00000000, - SQ_TEX_ANISO_RATIO_2 = 0x00000001, - SQ_TEX_ANISO_RATIO_4 = 0x00000002, - SQ_TEX_ANISO_RATIO_8 = 0x00000003, - SQ_TEX_ANISO_RATIO_16 = 0x00000004, -} SQ_TEX_ANISO_RATIO; - -/* - * SQ_TEX_DEPTH_COMPARE enum - */ - -typedef enum SQ_TEX_DEPTH_COMPARE { - SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, - SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, - SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, - SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, - SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, - SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, - SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, - SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, -} SQ_TEX_DEPTH_COMPARE; - -/* - * SQ_TEX_BORDER_COLOR enum - */ - -typedef enum SQ_TEX_BORDER_COLOR { - SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, - SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, - SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, - SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, -} SQ_TEX_BORDER_COLOR; - -/* - * SQ_RSRC_BUF_TYPE enum - */ - -typedef enum SQ_RSRC_BUF_TYPE { - SQ_RSRC_BUF = 0x00000000, - SQ_RSRC_BUF_RSVD_1 = 0x00000001, - SQ_RSRC_BUF_RSVD_2 = 0x00000002, - SQ_RSRC_BUF_RSVD_3 = 0x00000003, -} SQ_RSRC_BUF_TYPE; - -/* - * SQ_RSRC_IMG_TYPE enum - */ - -typedef enum SQ_RSRC_IMG_TYPE { - SQ_RSRC_IMG_RSVD_0 = 0x00000000, - SQ_RSRC_IMG_RSVD_1 = 0x00000001, - SQ_RSRC_IMG_RSVD_2 = 0x00000002, - SQ_RSRC_IMG_RSVD_3 = 0x00000003, - SQ_RSRC_IMG_RSVD_4 = 0x00000004, - SQ_RSRC_IMG_RSVD_5 = 0x00000005, - SQ_RSRC_IMG_RSVD_6 = 0x00000006, - SQ_RSRC_IMG_RSVD_7 = 0x00000007, - SQ_RSRC_IMG_1D = 0x00000008, - SQ_RSRC_IMG_2D = 0x00000009, - SQ_RSRC_IMG_3D = 0x0000000a, - SQ_RSRC_IMG_CUBE = 0x0000000b, - SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, - SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, - SQ_RSRC_IMG_2D_MSAA = 0x0000000e, - SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, -} SQ_RSRC_IMG_TYPE; - -/* - * SQ_RSRC_FLAT_TYPE enum - */ - -typedef enum SQ_RSRC_FLAT_TYPE { - SQ_RSRC_FLAT_RSVD_0 = 0x00000000, - SQ_RSRC_FLAT = 0x00000001, - SQ_RSRC_FLAT_RSVD_2 = 0x00000002, - SQ_RSRC_FLAT_RSVD_3 = 0x00000003, -} SQ_RSRC_FLAT_TYPE; - -/* - * SQ_IMG_FILTER_TYPE enum - */ - -typedef enum SQ_IMG_FILTER_TYPE { - SQ_IMG_FILTER_MODE_BLEND = 0x00000000, - SQ_IMG_FILTER_MODE_MIN = 0x00000001, - SQ_IMG_FILTER_MODE_MAX = 0x00000002, -} SQ_IMG_FILTER_TYPE; - -/* - * SQ_SEL_XYZW01 enum - */ - -typedef enum SQ_SEL_XYZW01 { - SQ_SEL_0 = 0x00000000, - SQ_SEL_1 = 0x00000001, - SQ_SEL_N_BC_1 = 0x00000002, - SQ_SEL_RESERVED_1 = 0x00000003, - SQ_SEL_X = 0x00000004, - SQ_SEL_Y = 0x00000005, - SQ_SEL_Z = 0x00000006, - SQ_SEL_W = 0x00000007, -} SQ_SEL_XYZW01; - -/* - * SQ_WAVE_TYPE enum - */ - -typedef enum SQ_WAVE_TYPE { - SQ_WAVE_TYPE_PS = 0x00000000, - SQ_WAVE_TYPE_VS = 0x00000001, - SQ_WAVE_TYPE_GS = 0x00000002, - SQ_WAVE_TYPE_ES = 0x00000003, - SQ_WAVE_TYPE_HS = 0x00000004, - SQ_WAVE_TYPE_LS = 0x00000005, - SQ_WAVE_TYPE_CS = 0x00000006, - SQ_WAVE_TYPE_PS1 = 0x00000007, -} SQ_WAVE_TYPE; - -/* - * SQ_THREAD_TRACE_TOKEN_TYPE enum - */ - -typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { - SQ_THREAD_TRACE_TOKEN_MISC = 0x00000000, - SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001, - SQ_THREAD_TRACE_TOKEN_REG = 0x00000002, - SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003, - SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x00000004, - SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x00000005, - SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006, - SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007, - SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008, - SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009, - SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a, - SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b, - SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c, - SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d, - SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e, - SQ_THREAD_TRACE_TOKEN_REG_CS = 0x0000000f, -} SQ_THREAD_TRACE_TOKEN_TYPE; - -/* - * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum - */ - -typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { - SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x00000000, - SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x00000001, - SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x00000002, - SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x00000003, - SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x00000004, - SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x00000005, - SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x00000006, - SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x00000007, -} SQ_THREAD_TRACE_MISC_TOKEN_TYPE; - -/* - * SQ_THREAD_TRACE_INST_TYPE enum - */ - -typedef enum SQ_THREAD_TRACE_INST_TYPE { - SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x00000000, - SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x00000001, - SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x00000002, - SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x00000003, - SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x00000004, - SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x00000005, - SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006, - SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007, - SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008, - SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009, - SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a, - SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b, - SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c, - SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d, - SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0x0000000e, - SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f, - SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x00000010, - SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x00000011, - SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x00000012, - SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x00000013, - SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x00000014, - SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x00000015, - SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x00000016, - SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x00000017, - SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x00000018, - SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 0x00000019, - SQ_THREAD_TRACE_INST_TYPE_DIDT_STALL_START = 0x0000001a, - SQ_THREAD_TRACE_INST_TYPE_DIDT_STALL_END = 0x0000001b, -} SQ_THREAD_TRACE_INST_TYPE; - -/* - * SQ_THREAD_TRACE_REG_TYPE enum - */ - -typedef enum SQ_THREAD_TRACE_REG_TYPE { - SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000, - SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001, - SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002, - SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003, - SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004, - SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005, - SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006, - SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007, -} SQ_THREAD_TRACE_REG_TYPE; - -/* - * SQ_THREAD_TRACE_REG_OP enum - */ - -typedef enum SQ_THREAD_TRACE_REG_OP { - SQ_THREAD_TRACE_REG_OP_READ = 0x00000000, - SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001, -} SQ_THREAD_TRACE_REG_OP; - -/* - * SQ_THREAD_TRACE_MODE_SEL enum - */ - -typedef enum SQ_THREAD_TRACE_MODE_SEL { - SQ_THREAD_TRACE_MODE_OFF = 0x00000000, - SQ_THREAD_TRACE_MODE_ON = 0x00000001, -} SQ_THREAD_TRACE_MODE_SEL; - -/* - * SQ_THREAD_TRACE_CAPTURE_MODE enum - */ - -typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { - SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000, - SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001, - SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002, -} SQ_THREAD_TRACE_CAPTURE_MODE; - -/* - * SQ_THREAD_TRACE_VM_ID_MASK enum - */ - -typedef enum SQ_THREAD_TRACE_VM_ID_MASK { - SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000, - SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001, - SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002, -} SQ_THREAD_TRACE_VM_ID_MASK; - -/* - * SQ_THREAD_TRACE_WAVE_MASK enum - */ - -typedef enum SQ_THREAD_TRACE_WAVE_MASK { - SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000, - SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001, -} SQ_THREAD_TRACE_WAVE_MASK; - -/* - * SQ_THREAD_TRACE_ISSUE enum - */ - -typedef enum SQ_THREAD_TRACE_ISSUE { - SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000, - SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001, - SQ_THREAD_TRACE_ISSUE_INST = 0x00000002, - SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003, -} SQ_THREAD_TRACE_ISSUE; - -/* - * SQ_THREAD_TRACE_ISSUE_MASK enum - */ - -typedef enum SQ_THREAD_TRACE_ISSUE_MASK { - SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000, - SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001, - SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002, - SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x00000003, -} SQ_THREAD_TRACE_ISSUE_MASK; - -/* - * SQ_PERF_SEL enum - */ - -typedef enum SQ_PERF_SEL { - SQ_PERF_SEL_NONE = 0x00000000, - SQ_PERF_SEL_ACCUM_PREV = 0x00000001, - SQ_PERF_SEL_CYCLES = 0x00000002, - SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, - SQ_PERF_SEL_WAVES = 0x00000004, - SQ_PERF_SEL_LEVEL_WAVES = 0x00000005, - SQ_PERF_SEL_WAVES_EQ_64 = 0x00000006, - SQ_PERF_SEL_WAVES_LT_64 = 0x00000007, - SQ_PERF_SEL_WAVES_LT_48 = 0x00000008, - SQ_PERF_SEL_WAVES_LT_32 = 0x00000009, - SQ_PERF_SEL_WAVES_LT_16 = 0x0000000a, - SQ_PERF_SEL_WAVES_CU = 0x0000000b, - SQ_PERF_SEL_LEVEL_WAVES_CU = 0x0000000c, - SQ_PERF_SEL_BUSY_CU_CYCLES = 0x0000000d, - SQ_PERF_SEL_ITEMS = 0x0000000e, - SQ_PERF_SEL_QUADS = 0x0000000f, - SQ_PERF_SEL_EVENTS = 0x00000010, - SQ_PERF_SEL_SURF_SYNCS = 0x00000011, - SQ_PERF_SEL_TTRACE_REQS = 0x00000012, - SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000013, - SQ_PERF_SEL_TTRACE_STALL = 0x00000014, - SQ_PERF_SEL_MSG_CNTR = 0x00000015, - SQ_PERF_SEL_MSG_PERF = 0x00000016, - SQ_PERF_SEL_MSG_GSCNT = 0x00000017, - SQ_PERF_SEL_MSG_INTERRUPT = 0x00000018, - SQ_PERF_SEL_INSTS = 0x00000019, - SQ_PERF_SEL_INSTS_VALU = 0x0000001a, - SQ_PERF_SEL_INSTS_VMEM_WR = 0x0000001b, - SQ_PERF_SEL_INSTS_VMEM_RD = 0x0000001c, - SQ_PERF_SEL_INSTS_VMEM = 0x0000001d, - SQ_PERF_SEL_INSTS_SALU = 0x0000001e, - SQ_PERF_SEL_INSTS_SMEM = 0x0000001f, - SQ_PERF_SEL_INSTS_FLAT = 0x00000020, - SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x00000021, - SQ_PERF_SEL_INSTS_LDS = 0x00000022, - SQ_PERF_SEL_INSTS_GDS = 0x00000023, - SQ_PERF_SEL_INSTS_EXP = 0x00000024, - SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000025, - SQ_PERF_SEL_INSTS_BRANCH = 0x00000026, - SQ_PERF_SEL_INSTS_SENDMSG = 0x00000027, - SQ_PERF_SEL_INSTS_VSKIPPED = 0x00000028, - SQ_PERF_SEL_INST_LEVEL_VMEM = 0x00000029, - SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000002a, - SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000002b, - SQ_PERF_SEL_INST_LEVEL_GDS = 0x0000002c, - SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000002d, - SQ_PERF_SEL_WAVE_CYCLES = 0x0000002e, - SQ_PERF_SEL_WAVE_READY = 0x0000002f, - SQ_PERF_SEL_WAIT_CNT_VM = 0x00000030, - SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000031, - SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000032, - SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000033, - SQ_PERF_SEL_WAIT_BARRIER = 0x00000034, - SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000035, - SQ_PERF_SEL_WAIT_SLEEP = 0x00000036, - SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x00000037, - SQ_PERF_SEL_WAIT_OTHER = 0x00000038, - SQ_PERF_SEL_WAIT_ANY = 0x00000039, - SQ_PERF_SEL_WAIT_TTRACE = 0x0000003a, - SQ_PERF_SEL_WAIT_IFETCH = 0x0000003b, - SQ_PERF_SEL_WAIT_INST_ANY = 0x0000003c, - SQ_PERF_SEL_WAIT_INST_VMEM = 0x0000003d, - SQ_PERF_SEL_WAIT_INST_SCA = 0x0000003e, - SQ_PERF_SEL_WAIT_INST_LDS = 0x0000003f, - SQ_PERF_SEL_WAIT_INST_VALU = 0x00000040, - SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000041, - SQ_PERF_SEL_WAIT_INST_MISC = 0x00000042, - SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000043, - SQ_PERF_SEL_ACTIVE_INST_ANY = 0x00000044, - SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x00000045, - SQ_PERF_SEL_ACTIVE_INST_LDS = 0x00000046, - SQ_PERF_SEL_ACTIVE_INST_VALU = 0x00000047, - SQ_PERF_SEL_ACTIVE_INST_SCA = 0x00000048, - SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x00000049, - SQ_PERF_SEL_ACTIVE_INST_MISC = 0x0000004a, - SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x0000004b, - SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x0000004c, - SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x0000004d, - SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x0000004e, - SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x0000004f, - SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x00000050, - SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000051, - SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000052, - SQ_PERF_SEL_INST_CYCLES_SMEM = 0x00000053, - SQ_PERF_SEL_INST_CYCLES_SALU = 0x00000054, - SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x00000055, - SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x00000056, - SQ_PERF_SEL_IFETCH = 0x00000057, - SQ_PERF_SEL_IFETCH_LEVEL = 0x00000058, - SQ_PERF_SEL_CBRANCH_FORK = 0x00000059, - SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x0000005a, - SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x0000005b, - SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x0000005c, - SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x0000005d, - SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000005e, - SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000005f, - SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000060, - SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000061, - SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x00000062, - SQ_PERF_SEL_VALU_DEP_STALL = 0x00000063, - SQ_PERF_SEL_VALU_STARVE = 0x00000064, - SQ_PERF_SEL_TA_STARVE = 0x00000065, - SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000066, - SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000067, - SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000068, - SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x00000069, - SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x0000006a, - SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x0000006b, - SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x0000006c, - SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x0000006d, - SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x0000006e, - SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x0000006f, - SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x00000070, - SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x00000071, - SQ_PERF_SEL_SRC_CD_BUSY = 0x00000072, - SQ_PERF_SEL_PT_POWER_STALL = 0x00000073, - SQ_PERF_SEL_USER0 = 0x00000074, - SQ_PERF_SEL_USER1 = 0x00000075, - SQ_PERF_SEL_USER2 = 0x00000076, - SQ_PERF_SEL_USER3 = 0x00000077, - SQ_PERF_SEL_USER4 = 0x00000078, - SQ_PERF_SEL_USER5 = 0x00000079, - SQ_PERF_SEL_USER6 = 0x0000007a, - SQ_PERF_SEL_USER7 = 0x0000007b, - SQ_PERF_SEL_USER8 = 0x0000007c, - SQ_PERF_SEL_USER9 = 0x0000007d, - SQ_PERF_SEL_USER10 = 0x0000007e, - SQ_PERF_SEL_USER11 = 0x0000007f, - SQ_PERF_SEL_USER12 = 0x00000080, - SQ_PERF_SEL_USER13 = 0x00000081, - SQ_PERF_SEL_USER14 = 0x00000082, - SQ_PERF_SEL_USER15 = 0x00000083, - SQ_PERF_SEL_USER_LEVEL0 = 0x00000084, - SQ_PERF_SEL_USER_LEVEL1 = 0x00000085, - SQ_PERF_SEL_USER_LEVEL2 = 0x00000086, - SQ_PERF_SEL_USER_LEVEL3 = 0x00000087, - SQ_PERF_SEL_USER_LEVEL4 = 0x00000088, - SQ_PERF_SEL_USER_LEVEL5 = 0x00000089, - SQ_PERF_SEL_USER_LEVEL6 = 0x0000008a, - SQ_PERF_SEL_USER_LEVEL7 = 0x0000008b, - SQ_PERF_SEL_USER_LEVEL8 = 0x0000008c, - SQ_PERF_SEL_USER_LEVEL9 = 0x0000008d, - SQ_PERF_SEL_USER_LEVEL10 = 0x0000008e, - SQ_PERF_SEL_USER_LEVEL11 = 0x0000008f, - SQ_PERF_SEL_USER_LEVEL12 = 0x00000090, - SQ_PERF_SEL_USER_LEVEL13 = 0x00000091, - SQ_PERF_SEL_USER_LEVEL14 = 0x00000092, - SQ_PERF_SEL_USER_LEVEL15 = 0x00000093, - SQ_PERF_SEL_POWER_VALU = 0x00000094, - SQ_PERF_SEL_POWER_VALU0 = 0x00000095, - SQ_PERF_SEL_POWER_VALU1 = 0x00000096, - SQ_PERF_SEL_POWER_VALU2 = 0x00000097, - SQ_PERF_SEL_POWER_GPR_RD = 0x00000098, - SQ_PERF_SEL_POWER_GPR_WR = 0x00000099, - SQ_PERF_SEL_POWER_LDS_BUSY = 0x0000009a, - SQ_PERF_SEL_POWER_ALU_BUSY = 0x0000009b, - SQ_PERF_SEL_POWER_TEX_BUSY = 0x0000009c, - SQ_PERF_SEL_ACCUM_PREV_HIRES = 0x0000009d, - SQ_PERF_SEL_WAVES_RESTORED = 0x0000009e, - SQ_PERF_SEL_WAVES_SAVED = 0x0000009f, - SQ_PERF_SEL_INSTS_SMEM_NORM = 0x000000a0, - SQ_PERF_SEL_XNACK_FIRST = 0x000000a1, - SQ_PERF_SEL_XNACK_ALL = 0x000000a2, - SQ_PERF_SEL_XNACK_FIFO_FULL = 0x000000a3, - SQ_PERF_SEL_IFETCH_XNACK = 0x000000a4, - SQ_PERF_SEL_TLB_SHOOTDOWN = 0x000000a5, - SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x000000a6, - SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x000000a7, - SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x000000a8, - SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x000000a9, - SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x000000aa, - SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x000000ab, - SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x000000ac, - SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000ad, - SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000ae, - SQ_PERF_SEL_UTCL1_TRANSLATION_HIT_EVENT = 0x000000af, - SQ_PERF_SEL_UTCL1_REQUEST = 0x000000b0, - SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b1, - SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b2, - SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b3, - SQ_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b4, - SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b5, - SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000b6, - SQ_PERF_SEL_DUMMY_END = 0x000000b7, - SQ_PERF_SEL_DUMMY_LAST = 0x000000ff, - SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000100, - SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000101, - SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x00000102, - SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x00000103, - SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000104, - SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x00000105, - SQC_PERF_SEL_TC_REQ = 0x00000106, - SQC_PERF_SEL_TC_INST_REQ = 0x00000107, - SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000108, - SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000109, - SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x0000010a, - SQC_PERF_SEL_TC_STALL = 0x0000010b, - SQC_PERF_SEL_TC_STARVE = 0x0000010c, - SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010d, - SQC_PERF_SEL_ICACHE_REQ = 0x0000010e, - SQC_PERF_SEL_ICACHE_HITS = 0x0000010f, - SQC_PERF_SEL_ICACHE_MISSES = 0x00000110, - SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000111, - SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000112, - SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000113, - SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000114, - SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000115, - SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000116, - SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000117, - SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000118, - SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x00000119, - SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000011a, - SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000011b, - SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000011c, - SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000011d, - SQC_PERF_SEL_ICACHE_PREFETCH_1 = 0x0000011e, - SQC_PERF_SEL_ICACHE_PREFETCH_2 = 0x0000011f, - SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 0x00000120, - SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000121, - SQC_PERF_SEL_DCACHE_REQ = 0x00000122, - SQC_PERF_SEL_DCACHE_HITS = 0x00000123, - SQC_PERF_SEL_DCACHE_MISSES = 0x00000124, - SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000125, - SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000126, - SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0x00000127, - SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000128, - SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000129, - SQC_PERF_SEL_DCACHE_ATOMIC = 0x0000012a, - SQC_PERF_SEL_DCACHE_VOLATILE = 0x0000012b, - SQC_PERF_SEL_DCACHE_INVAL_INST = 0x0000012c, - SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012d, - SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0x0000012e, - SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0x0000012f, - SQC_PERF_SEL_DCACHE_WB_INST = 0x00000130, - SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x00000131, - SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0x00000132, - SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0x00000133, - SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000134, - SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x00000135, - SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x00000136, - SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000137, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000138, - SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000139, - SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x0000013a, - SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x0000013b, - SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x0000013c, - SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x0000013d, - SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x0000013e, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000013f, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000140, - SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x00000141, - SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000142, - SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000143, - SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000144, - SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000145, - SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000146, - SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000147, - SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000148, - SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000149, - SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x0000014a, - SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x0000014b, - SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x0000014c, - SQC_PERF_SEL_SQ_DCACHE_REQS = 0x0000014d, - SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x0000014e, - SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x0000014f, - SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000150, - SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000151, - SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000152, - SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000153, - SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000154, - SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0x00000155, - SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0x00000156, - SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_HIT = 0x00000157, - SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0x00000158, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000159, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0x0000015a, - SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0x0000015b, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x0000015c, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x0000015d, - SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x0000015e, - SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x0000015f, - SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x00000160, - SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x00000161, - SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_HIT = 0x00000162, - SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x00000163, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000164, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000165, - SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x00000166, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x00000167, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x00000168, - SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x00000169, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x0000016a, - SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x0000016b, - SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x0000016c, - SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL = 0x0000016d, - SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ = 0x0000016e, - SQC_PERF_SEL_ICACHE_UTCL2_INFLIGHT_LEVEL = 0x0000016f, - SQC_PERF_SEL_ICACHE_UTCL2_ALL_REQ = 0x00000170, - SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL = 0x00000171, - SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ = 0x00000172, - SQC_PERF_SEL_DCACHE_UTCL2_INFLIGHT_LEVEL = 0x00000173, - SQC_PERF_SEL_DCACHE_UTCL2_ALL_REQ = 0x00000174, - SQC_PERF_SEL_DUMMY_LAST = 0x00000175, -} SQ_PERF_SEL; - -/* - * SQ_CAC_POWER_SEL enum - */ - -typedef enum SQ_CAC_POWER_SEL { - SQ_CAC_POWER_VALU = 0x00000000, - SQ_CAC_POWER_VALU0 = 0x00000001, - SQ_CAC_POWER_VALU1 = 0x00000002, - SQ_CAC_POWER_VALU2 = 0x00000003, - SQ_CAC_POWER_GPR_RD = 0x00000004, - SQ_CAC_POWER_GPR_WR = 0x00000005, - SQ_CAC_POWER_LDS_BUSY = 0x00000006, - SQ_CAC_POWER_ALU_BUSY = 0x00000007, - SQ_CAC_POWER_TEX_BUSY = 0x00000008, -} SQ_CAC_POWER_SEL; - -/* - * SQ_IND_CMD_CMD enum - */ - -typedef enum SQ_IND_CMD_CMD { - SQ_IND_CMD_CMD_NULL = 0x00000000, - SQ_IND_CMD_CMD_SETHALT = 0x00000001, - SQ_IND_CMD_CMD_SAVECTX = 0x00000002, - SQ_IND_CMD_CMD_KILL = 0x00000003, - SQ_IND_CMD_CMD_DEBUG = 0x00000004, - SQ_IND_CMD_CMD_TRAP = 0x00000005, - SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006, - SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007, -} SQ_IND_CMD_CMD; - -/* - * SQ_IND_CMD_MODE enum - */ - -typedef enum SQ_IND_CMD_MODE { - SQ_IND_CMD_MODE_SINGLE = 0x00000000, - SQ_IND_CMD_MODE_BROADCAST = 0x00000001, - SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, - SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, - SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, -} SQ_IND_CMD_MODE; - -/* - * SQ_EDC_INFO_SOURCE enum - */ - -typedef enum SQ_EDC_INFO_SOURCE { - SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, - SQ_EDC_INFO_SOURCE_INST = 0x00000001, - SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, - SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, - SQ_EDC_INFO_SOURCE_LDS = 0x00000004, - SQ_EDC_INFO_SOURCE_GDS = 0x00000005, - SQ_EDC_INFO_SOURCE_TA = 0x00000006, -} SQ_EDC_INFO_SOURCE; - -/* - * SQ_ROUND_MODE enum - */ - -typedef enum SQ_ROUND_MODE { - SQ_ROUND_NEAREST_EVEN = 0x00000000, - SQ_ROUND_PLUS_INFINITY = 0x00000001, - SQ_ROUND_MINUS_INFINITY = 0x00000002, - SQ_ROUND_TO_ZERO = 0x00000003, -} SQ_ROUND_MODE; - -/* - * SQ_INTERRUPT_WORD_ENCODING enum - */ - -typedef enum SQ_INTERRUPT_WORD_ENCODING { - SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000, - SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001, - SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002, -} SQ_INTERRUPT_WORD_ENCODING; - -/* - * SQ_IBUF_ST enum - */ - -typedef enum SQ_IBUF_ST { - SQ_IBUF_IB_IDLE = 0x00000000, - SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, - SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, - SQ_IBUF_IB_LE_4DW = 0x00000003, - SQ_IBUF_IB_WAIT_DRET = 0x00000004, - SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, - SQ_IBUF_IB_DRET = 0x00000006, - SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, -} SQ_IBUF_ST; - -/* - * SQ_INST_STR_ST enum - */ - -typedef enum SQ_INST_STR_ST { - SQ_INST_STR_IB_WAVE_NORML = 0x00000000, - SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, - SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, - SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, - SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004, - SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005, - SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006, - SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007, -} SQ_INST_STR_ST; - -/* - * SQ_WAVE_IB_ECC_ST enum - */ - -typedef enum SQ_WAVE_IB_ECC_ST { - SQ_WAVE_IB_ECC_CLEAN = 0x00000000, - SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, - SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, - SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, -} SQ_WAVE_IB_ECC_ST; - -/* - * SH_MEM_ADDRESS_MODE enum - */ - -typedef enum SH_MEM_ADDRESS_MODE { - SH_MEM_ADDRESS_MODE_64 = 0x00000000, - SH_MEM_ADDRESS_MODE_32 = 0x00000001, -} SH_MEM_ADDRESS_MODE; - -/* - * SH_MEM_ALIGNMENT_MODE enum - */ - -typedef enum SH_MEM_ALIGNMENT_MODE { - SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, - SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, - SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, - SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, -} SH_MEM_ALIGNMENT_MODE; - -/* - * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum - */ - -typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { - SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018, - SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019, -} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; - -/* - * SQ_LB_CTR_SEL_VALUES enum - */ - -typedef enum SQ_LB_CTR_SEL_VALUES { - SQ_LB_CTR_SEL_ALU_CYCLES = 0x00000000, - SQ_LB_CTR_SEL_ALU_STALLS = 0x00000001, - SQ_LB_CTR_SEL_TEX_CYCLES = 0x00000002, - SQ_LB_CTR_SEL_TEX_STALLS = 0x00000003, - SQ_LB_CTR_SEL_SALU_CYCLES = 0x00000004, - SQ_LB_CTR_SEL_SCALAR_STALLS = 0x00000005, - SQ_LB_CTR_SEL_SMEM_CYCLES = 0x00000006, - SQ_LB_CTR_SEL_ICACHE_STALLS = 0x00000007, - SQ_LB_CTR_SEL_DCACHE_STALLS = 0x00000008, - SQ_LB_CTR_SEL_RESERVED0 = 0x00000009, - SQ_LB_CTR_SEL_RESERVED1 = 0x0000000a, - SQ_LB_CTR_SEL_RESERVED2 = 0x0000000b, - SQ_LB_CTR_SEL_RESERVED3 = 0x0000000c, - SQ_LB_CTR_SEL_RESERVED4 = 0x0000000d, - SQ_LB_CTR_SEL_RESERVED5 = 0x0000000e, - SQ_LB_CTR_SEL_RESERVED6 = 0x0000000f, -} SQ_LB_CTR_SEL_VALUES; - -/* - * SQ_WAVE_TYPE value - */ - -#define SQ_WAVE_TYPE_PS0 0x00000000 - -/* - * SQIND_PARTITIONS value - */ - -#define SQIND_GLOBAL_REGS_OFFSET 0x00000000 -#define SQIND_GLOBAL_REGS_SIZE 0x00000008 -#define SQIND_LOCAL_REGS_OFFSET 0x00000008 -#define SQIND_LOCAL_REGS_SIZE 0x00000008 -#define SQIND_WAVE_HWREGS_OFFSET 0x00000010 -#define SQIND_WAVE_HWREGS_SIZE 0x000001f0 -#define SQIND_WAVE_SGPRS_OFFSET 0x00000200 -#define SQIND_WAVE_SGPRS_SIZE 0x00000200 -#define SQIND_WAVE_VGPRS_OFFSET 0x00000400 -#define SQIND_WAVE_VGPRS_SIZE 0x00000100 - -/* - * SQ_GFXDEC value - */ - -#define SQ_GFXDEC_BEGIN 0x0000a000 -#define SQ_GFXDEC_END 0x0000c000 -#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a - -/* - * SQDEC value - */ - -#define SQDEC_BEGIN 0x00002300 -#define SQDEC_END 0x000023ff - -/* - * SQPERFSDEC value - */ - -#define SQPERFSDEC_BEGIN 0x0000d9c0 -#define SQPERFSDEC_END 0x0000da40 - -/* - * SQPERFDDEC value - */ - -#define SQPERFDDEC_BEGIN 0x0000d1c0 -#define SQPERFDDEC_END 0x0000d240 - -/* - * SQGFXUDEC value - */ - -#define SQGFXUDEC_BEGIN 0x0000c330 -#define SQGFXUDEC_END 0x0000c380 - -/* - * SQPWRDEC value - */ - -#define SQPWRDEC_BEGIN 0x0000f08c -#define SQPWRDEC_END 0x0000f094 - -/* - * SQ_DISPATCHER value - */ - -#define SQ_DISPATCHER_GFX_MIN 0x00000010 -#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 - -/* - * SQ_MAX value - */ - -#define SQ_MAX_PGM_SGPRS 0x00000068 -#define SQ_MAX_PGM_VGPRS 0x00000100 - -/* - * SQ_THREAD_TRACE_TIME_UNIT value - */ - -#define SQ_THREAD_TRACE_TIME_UNIT 0x00000004 - -/* - * SQ_EXCP_BITS value - */ - -#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000 -#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007 -#define SQ_EX_MODE_EXCP_INVALID 0x00000000 -#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001 -#define SQ_EX_MODE_EXCP_DIV0 0x00000002 -#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003 -#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004 -#define SQ_EX_MODE_EXCP_INEXACT 0x00000005 -#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006 -#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007 -#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008 - -/* - * SQ_EXCP_HI_BITS value - */ - -#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000 -#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001 -#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002 - -/* - * HW_INSERTED_INST_ID value - */ - -#define INST_ID_PRIV_START 0x80000000 -#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 -#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 -#define INST_ID_HW_TRAP 0xfffffff2 -#define INST_ID_KILL_SEQ 0xfffffff3 -#define INST_ID_SPI_WREXEC 0xfffffff4 -#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe - -/* - * SIMM16_WAITCNT_PARTITIONS value - */ - -#define SIMM16_WAITCNT_VM_CNT_START 0x00000000 -#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004 -#define SIMM16_WAITCNT_EXP_CNT_START 0x00000004 -#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003 -#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008 -#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004 -#define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e -#define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002 - -/* - * SQ_EDC_FUE_CNTL_BITS value - */ - -#define SQ_EDC_FUE_CNTL_SIMD0 0x00000000 -#define SQ_EDC_FUE_CNTL_SIMD1 0x00000001 -#define SQ_EDC_FUE_CNTL_SIMD2 0x00000002 -#define SQ_EDC_FUE_CNTL_SIMD3 0x00000003 -#define SQ_EDC_FUE_CNTL_SQ 0x00000004 -#define SQ_EDC_FUE_CNTL_LDS 0x00000005 -#define SQ_EDC_FUE_CNTL_TD 0x00000006 -#define SQ_EDC_FUE_CNTL_TA 0x00000007 -#define SQ_EDC_FUE_CNTL_TCP 0x00000008 - -/******************************************************* - * COMP Enums - *******************************************************/ - -/* - * CSDATA_TYPE enum - */ - -typedef enum CSDATA_TYPE { - CSDATA_TYPE_TG = 0x00000000, - CSDATA_TYPE_STATE = 0x00000001, - CSDATA_TYPE_EVENT = 0x00000002, - CSDATA_TYPE_PRIVATE = 0x00000003, -} CSDATA_TYPE; - -/* - * CSDATA_TYPE_WIDTH value - */ - -#define CSDATA_TYPE_WIDTH 0x00000002 - -/* - * CSDATA_ADDR_WIDTH value - */ - -#define CSDATA_ADDR_WIDTH 0x00000007 - -/* - * CSDATA_DATA_WIDTH value - */ - -#define CSDATA_DATA_WIDTH 0x00000020 - -/******************************************************* - * VGT Enums - *******************************************************/ - -/* - * VGT_OUT_PRIM_TYPE enum - */ - -typedef enum VGT_OUT_PRIM_TYPE { - VGT_OUT_POINT = 0x00000000, - VGT_OUT_LINE = 0x00000001, - VGT_OUT_TRI = 0x00000002, - VGT_OUT_RECT_V0 = 0x00000003, - VGT_OUT_RECT_V1 = 0x00000004, - VGT_OUT_RECT_V2 = 0x00000005, - VGT_OUT_RECT_V3 = 0x00000006, - VGT_OUT_2D_RECT = 0x00000007, - VGT_TE_QUAD = 0x00000008, - VGT_TE_PRIM_INDEX_LINE = 0x00000009, - VGT_TE_PRIM_INDEX_TRI = 0x0000000a, - VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, - VGT_OUT_LINE_ADJ = 0x0000000c, - VGT_OUT_TRI_ADJ = 0x0000000d, - VGT_OUT_PATCH = 0x0000000e, -} VGT_OUT_PRIM_TYPE; - -/* - * VGT_DI_PRIM_TYPE enum - */ - -typedef enum VGT_DI_PRIM_TYPE { - DI_PT_NONE = 0x00000000, - DI_PT_POINTLIST = 0x00000001, - DI_PT_LINELIST = 0x00000002, - DI_PT_LINESTRIP = 0x00000003, - DI_PT_TRILIST = 0x00000004, - DI_PT_TRIFAN = 0x00000005, - DI_PT_TRISTRIP = 0x00000006, - DI_PT_2D_RECTANGLE = 0x00000007, - DI_PT_UNUSED_1 = 0x00000008, - DI_PT_PATCH = 0x00000009, - DI_PT_LINELIST_ADJ = 0x0000000a, - DI_PT_LINESTRIP_ADJ = 0x0000000b, - DI_PT_TRILIST_ADJ = 0x0000000c, - DI_PT_TRISTRIP_ADJ = 0x0000000d, - DI_PT_UNUSED_3 = 0x0000000e, - DI_PT_UNUSED_4 = 0x0000000f, - DI_PT_TRI_WITH_WFLAGS = 0x00000010, - DI_PT_RECTLIST = 0x00000011, - DI_PT_LINELOOP = 0x00000012, - DI_PT_QUADLIST = 0x00000013, - DI_PT_QUADSTRIP = 0x00000014, - DI_PT_POLYGON = 0x00000015, -} VGT_DI_PRIM_TYPE; - -/* - * VGT_DI_SOURCE_SELECT enum - */ - -typedef enum VGT_DI_SOURCE_SELECT { - DI_SRC_SEL_DMA = 0x00000000, - DI_SRC_SEL_IMMEDIATE = 0x00000001, - DI_SRC_SEL_AUTO_INDEX = 0x00000002, - DI_SRC_SEL_RESERVED = 0x00000003, -} VGT_DI_SOURCE_SELECT; - -/* - * VGT_DI_MAJOR_MODE_SELECT enum - */ - -typedef enum VGT_DI_MAJOR_MODE_SELECT { - DI_MAJOR_MODE_0 = 0x00000000, - DI_MAJOR_MODE_1 = 0x00000001, -} VGT_DI_MAJOR_MODE_SELECT; - -/* - * VGT_DI_INDEX_SIZE enum - */ - -typedef enum VGT_DI_INDEX_SIZE { - DI_INDEX_SIZE_16_BIT = 0x00000000, - DI_INDEX_SIZE_32_BIT = 0x00000001, - DI_INDEX_SIZE_8_BIT = 0x00000002, -} VGT_DI_INDEX_SIZE; - -/* - * VGT_EVENT_TYPE enum - */ - -typedef enum VGT_EVENT_TYPE { - Reserved_0x00 = 0x00000000, - SAMPLE_STREAMOUTSTATS1 = 0x00000001, - SAMPLE_STREAMOUTSTATS2 = 0x00000002, - SAMPLE_STREAMOUTSTATS3 = 0x00000003, - CACHE_FLUSH_TS = 0x00000004, - CONTEXT_DONE = 0x00000005, - CACHE_FLUSH = 0x00000006, - CS_PARTIAL_FLUSH = 0x00000007, - VGT_STREAMOUT_SYNC = 0x00000008, - SET_FE_ID = 0x00000009, - VGT_STREAMOUT_RESET = 0x0000000a, - END_OF_PIPE_INCR_DE = 0x0000000b, - END_OF_PIPE_IB_END = 0x0000000c, - RST_PIX_CNT = 0x0000000d, - BREAK_BATCH = 0x0000000e, - VS_PARTIAL_FLUSH = 0x0000000f, - PS_PARTIAL_FLUSH = 0x00000010, - FLUSH_HS_OUTPUT = 0x00000011, - FLUSH_DFSM = 0x00000012, - RESET_TO_LOWEST_VGT = 0x00000013, - CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, - ZPASS_DONE = 0x00000015, - CACHE_FLUSH_AND_INV_EVENT = 0x00000016, - PERFCOUNTER_START = 0x00000017, - PERFCOUNTER_STOP = 0x00000018, - PIPELINESTAT_START = 0x00000019, - PIPELINESTAT_STOP = 0x0000001a, - PERFCOUNTER_SAMPLE = 0x0000001b, - Available_0x1c = 0x0000001c, - Available_0x1d = 0x0000001d, - SAMPLE_PIPELINESTAT = 0x0000001e, - SO_VGTSTREAMOUT_FLUSH = 0x0000001f, - SAMPLE_STREAMOUTSTATS = 0x00000020, - RESET_VTX_CNT = 0x00000021, - BLOCK_CONTEXT_DONE = 0x00000022, - CS_CONTEXT_DONE = 0x00000023, - VGT_FLUSH = 0x00000024, - TGID_ROLLOVER = 0x00000025, - SQ_NON_EVENT = 0x00000026, - SC_SEND_DB_VPZ = 0x00000027, - BOTTOM_OF_PIPE_TS = 0x00000028, - FLUSH_SX_TS = 0x00000029, - DB_CACHE_FLUSH_AND_INV = 0x0000002a, - FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, - FLUSH_AND_INV_DB_META = 0x0000002c, - FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, - FLUSH_AND_INV_CB_META = 0x0000002e, - CS_DONE = 0x0000002f, - PS_DONE = 0x00000030, - FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, - SX_CB_RAT_ACK_REQUEST = 0x00000032, - THREAD_TRACE_START = 0x00000033, - THREAD_TRACE_STOP = 0x00000034, - THREAD_TRACE_MARKER = 0x00000035, - THREAD_TRACE_FLUSH = 0x00000036, - THREAD_TRACE_FINISH = 0x00000037, - PIXEL_PIPE_STAT_CONTROL = 0x00000038, - PIXEL_PIPE_STAT_DUMP = 0x00000039, - PIXEL_PIPE_STAT_RESET = 0x0000003a, - CONTEXT_SUSPEND = 0x0000003b, - OFFCHIP_HS_DEALLOC = 0x0000003c, - ENABLE_NGG_PIPELINE = 0x0000003d, - ENABLE_LEGACY_PIPELINE = 0x0000003e, - Reserved_0x3f = 0x0000003f, -} VGT_EVENT_TYPE; - -/* - * VGT_DMA_SWAP_MODE enum - */ - -typedef enum VGT_DMA_SWAP_MODE { - VGT_DMA_SWAP_NONE = 0x00000000, - VGT_DMA_SWAP_16_BIT = 0x00000001, - VGT_DMA_SWAP_32_BIT = 0x00000002, - VGT_DMA_SWAP_WORD = 0x00000003, -} VGT_DMA_SWAP_MODE; - -/* - * VGT_INDEX_TYPE_MODE enum - */ - -typedef enum VGT_INDEX_TYPE_MODE { - VGT_INDEX_16 = 0x00000000, - VGT_INDEX_32 = 0x00000001, - VGT_INDEX_8 = 0x00000002, -} VGT_INDEX_TYPE_MODE; - -/* - * VGT_DMA_BUF_TYPE enum - */ - -typedef enum VGT_DMA_BUF_TYPE { - VGT_DMA_BUF_MEM = 0x00000000, - VGT_DMA_BUF_RING = 0x00000001, - VGT_DMA_BUF_SETUP = 0x00000002, - VGT_DMA_PTR_UPDATE = 0x00000003, -} VGT_DMA_BUF_TYPE; - -/* - * VGT_OUTPATH_SELECT enum - */ - -typedef enum VGT_OUTPATH_SELECT { - VGT_OUTPATH_VTX_REUSE = 0x00000000, - VGT_OUTPATH_TESS_EN = 0x00000001, - VGT_OUTPATH_PASSTHRU = 0x00000002, - VGT_OUTPATH_GS_BLOCK = 0x00000003, - VGT_OUTPATH_HS_BLOCK = 0x00000004, - VGT_OUTPATH_PRIM_GEN = 0x00000005, -} VGT_OUTPATH_SELECT; - -/* - * VGT_GRP_PRIM_TYPE enum - */ - -typedef enum VGT_GRP_PRIM_TYPE { - VGT_GRP_3D_POINT = 0x00000000, - VGT_GRP_3D_LINE = 0x00000001, - VGT_GRP_3D_TRI = 0x00000002, - VGT_GRP_3D_RECT = 0x00000003, - VGT_GRP_3D_QUAD = 0x00000004, - VGT_GRP_2D_COPY_RECT_V0 = 0x00000005, - VGT_GRP_2D_COPY_RECT_V1 = 0x00000006, - VGT_GRP_2D_COPY_RECT_V2 = 0x00000007, - VGT_GRP_2D_COPY_RECT_V3 = 0x00000008, - VGT_GRP_2D_FILL_RECT = 0x00000009, - VGT_GRP_2D_LINE = 0x0000000a, - VGT_GRP_2D_TRI = 0x0000000b, - VGT_GRP_PRIM_INDEX_LINE = 0x0000000c, - VGT_GRP_PRIM_INDEX_TRI = 0x0000000d, - VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e, - VGT_GRP_3D_LINE_ADJ = 0x0000000f, - VGT_GRP_3D_TRI_ADJ = 0x00000010, - VGT_GRP_3D_PATCH = 0x00000011, - VGT_GRP_2D_RECT = 0x00000012, -} VGT_GRP_PRIM_TYPE; - -/* - * VGT_GRP_PRIM_ORDER enum - */ - -typedef enum VGT_GRP_PRIM_ORDER { - VGT_GRP_LIST = 0x00000000, - VGT_GRP_STRIP = 0x00000001, - VGT_GRP_FAN = 0x00000002, - VGT_GRP_LOOP = 0x00000003, - VGT_GRP_POLYGON = 0x00000004, -} VGT_GRP_PRIM_ORDER; - -/* - * VGT_GROUP_CONV_SEL enum - */ - -typedef enum VGT_GROUP_CONV_SEL { - VGT_GRP_INDEX_16 = 0x00000000, - VGT_GRP_INDEX_32 = 0x00000001, - VGT_GRP_UINT_16 = 0x00000002, - VGT_GRP_UINT_32 = 0x00000003, - VGT_GRP_SINT_16 = 0x00000004, - VGT_GRP_SINT_32 = 0x00000005, - VGT_GRP_FLOAT_32 = 0x00000006, - VGT_GRP_AUTO_PRIM = 0x00000007, - VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, -} VGT_GROUP_CONV_SEL; - -/* - * VGT_GS_MODE_TYPE enum - */ - -typedef enum VGT_GS_MODE_TYPE { - GS_OFF = 0x00000000, - GS_SCENARIO_A = 0x00000001, - GS_SCENARIO_B = 0x00000002, - GS_SCENARIO_G = 0x00000003, - GS_SCENARIO_C = 0x00000004, - SPRITE_EN = 0x00000005, -} VGT_GS_MODE_TYPE; - -/* - * VGT_GS_CUT_MODE enum - */ - -typedef enum VGT_GS_CUT_MODE { - GS_CUT_1024 = 0x00000000, - GS_CUT_512 = 0x00000001, - GS_CUT_256 = 0x00000002, - GS_CUT_128 = 0x00000003, -} VGT_GS_CUT_MODE; - -/* - * VGT_GS_OUTPRIM_TYPE enum - */ - -typedef enum VGT_GS_OUTPRIM_TYPE { - POINTLIST = 0x00000000, - LINESTRIP = 0x00000001, - TRISTRIP = 0x00000002, - RECTLIST = 0x00000003, -} VGT_GS_OUTPRIM_TYPE; - -/* - * VGT_CACHE_INVALID_MODE enum - */ - -typedef enum VGT_CACHE_INVALID_MODE { - VC_ONLY = 0x00000000, - TC_ONLY = 0x00000001, - VC_AND_TC = 0x00000002, -} VGT_CACHE_INVALID_MODE; - -/* - * VGT_TESS_TYPE enum - */ - -typedef enum VGT_TESS_TYPE { - TESS_ISOLINE = 0x00000000, - TESS_TRIANGLE = 0x00000001, - TESS_QUAD = 0x00000002, -} VGT_TESS_TYPE; - -/* - * VGT_TESS_PARTITION enum - */ - -typedef enum VGT_TESS_PARTITION { - PART_INTEGER = 0x00000000, - PART_POW2 = 0x00000001, - PART_FRAC_ODD = 0x00000002, - PART_FRAC_EVEN = 0x00000003, -} VGT_TESS_PARTITION; - -/* - * VGT_TESS_TOPOLOGY enum - */ - -typedef enum VGT_TESS_TOPOLOGY { - OUTPUT_POINT = 0x00000000, - OUTPUT_LINE = 0x00000001, - OUTPUT_TRIANGLE_CW = 0x00000002, - OUTPUT_TRIANGLE_CCW = 0x00000003, -} VGT_TESS_TOPOLOGY; - -/* - * VGT_RDREQ_POLICY enum - */ - -typedef enum VGT_RDREQ_POLICY { - VGT_POLICY_LRU = 0x00000000, - VGT_POLICY_STREAM = 0x00000001, -} VGT_RDREQ_POLICY; - -/* - * VGT_DIST_MODE enum - */ - -typedef enum VGT_DIST_MODE { - NO_DIST = 0x00000000, - PATCHES = 0x00000001, - DONUTS = 0x00000002, - TRAPEZOIDS = 0x00000003, -} VGT_DIST_MODE; - -/* - * VGT_STAGES_LS_EN enum - */ - -typedef enum VGT_STAGES_LS_EN { - LS_STAGE_OFF = 0x00000000, - LS_STAGE_ON = 0x00000001, - CS_STAGE_ON = 0x00000002, - RESERVED_LS = 0x00000003, -} VGT_STAGES_LS_EN; - -/* - * VGT_STAGES_HS_EN enum - */ - -typedef enum VGT_STAGES_HS_EN { - HS_STAGE_OFF = 0x00000000, - HS_STAGE_ON = 0x00000001, -} VGT_STAGES_HS_EN; - -/* - * VGT_STAGES_ES_EN enum - */ - -typedef enum VGT_STAGES_ES_EN { - ES_STAGE_OFF = 0x00000000, - ES_STAGE_DS = 0x00000001, - ES_STAGE_REAL = 0x00000002, - RESERVED_ES = 0x00000003, -} VGT_STAGES_ES_EN; - -/* - * VGT_STAGES_GS_EN enum - */ - -typedef enum VGT_STAGES_GS_EN { - GS_STAGE_OFF = 0x00000000, - GS_STAGE_ON = 0x00000001, -} VGT_STAGES_GS_EN; - -/* - * VGT_STAGES_VS_EN enum - */ - -typedef enum VGT_STAGES_VS_EN { - VS_STAGE_REAL = 0x00000000, - VS_STAGE_DS = 0x00000001, - VS_STAGE_COPY_SHADER = 0x00000002, - RESERVED_VS = 0x00000003, -} VGT_STAGES_VS_EN; - -/* - * VGT_PERFCOUNT_SELECT enum - */ - -typedef enum VGT_PERFCOUNT_SELECT { - vgt_perf_UNUSED0 = 0x00000000, - vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001, - vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002, - vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003, - vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004, - vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005, - vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006, - vgt_perf_VGT_SPI_PRIMGEN_GS_PRIM_FIFO_STALL = 0x00000007, - vgt_perf_VGT_SPI_PRIMGEN_ES_VERT_FIFO_STALL = 0x00000008, - vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009, - vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a, - vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b, - vgt_perf_VGT_SPI_PRIMGEN_SUBGRP_FIFO_STALL = 0x0000000c, - vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d, - vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e, - vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f, - vgt_perf_VGT_SPI_GSSUBGRP_EVENT_WINDOW_ACTIVE = 0x00000010, - vgt_perf_VGT_SPI_GSSUBGRP_IS_EVENT = 0x00000011, - vgt_perf_VGT_SPI_GSSUBGRP_SEND = 0x00000012, - vgt_perf_VGT_SPI_VSWAVE_EVENT_WINDOW_ACTIVE = 0x00000013, - vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014, - vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015, - vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016, - vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017, - vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018, - vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019, - vgt_perf_VGT_SPI_VSWAVE_IS_EVENT = 0x0000001a, - vgt_perf_VGT_SPI_VSWAVE_SEND = 0x0000001b, - vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c, - vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d, - vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e, - vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f, - vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020, - vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021, - vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022, - vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023, - vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024, - vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025, - vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026, - vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027, - vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028, - vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029, - vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a, - vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b, - vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c, - vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d, - vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e, - vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f, - vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030, - vgt_perf_VSVERT_DS_SEND = 0x00000031, - vgt_perf_VSVERT_API_SEND = 0x00000032, - vgt_perf_hs_tif_stall = 0x00000033, - vgt_perf_hs_input_stall = 0x00000034, - vgt_perf_hs_interface_stall = 0x00000035, - vgt_perf_hs_tfm_stall = 0x00000036, - vgt_perf_te11_starved_after_work = 0x00000037, - vgt_perf_gs_event_stall = 0x00000038, - vgt_perf_vgt_pa_clipp_send_not_event = 0x00000039, - vgt_perf_vgt_pa_clipp_valid_prim = 0x0000003a, - vgt_perf_REUSED_ES_INDICES = 0x0000003b, - vgt_perf_VS_CACHE_HITS = 0x0000003c, - vgt_perf_GS_CACHE_HITS = 0x0000003d, - vgt_perf_DS_CACHE_HITS = 0x0000003e, - vgt_perf_TOTAL_CACHE_HITS = 0x0000003f, - vgt_perf_vgt_busy = 0x00000040, - vgt_perf_vgt_gs_busy = 0x00000041, - vgt_perf_gsprim_stalled = 0x00000042, - vgt_perf_esvert_stalled_gs_tbl = 0x00000043, - vgt_perf_esvert_stalled_gs_event = 0x00000044, - vgt_perf_vgt_spi_primgen_wd_interface_stall = 0x00000045, - vgt_perf_UNUSED70 = 0x00000046, - vgt_perf_gsprim_stalled_gs_tbl = 0x00000047, - vgt_perf_gsprim_stalled_gs_event = 0x00000048, - vgt_perf_gsprim_stalled_esvert = 0x00000049, - vgt_perf_UNUSED74 = 0x0000004a, - vgt_perf_UNUSED75 = 0x0000004b, - vgt_perf_counters_avail_stalled = 0x0000004c, - vgt_perf_gs_rb_space_avail_stalled = 0x0000004d, - vgt_perf_gs_issue_rtr_stalled = 0x0000004e, - vgt_perf_gssubgrp_stalled = 0x0000004f, - vgt_perf_strmout_stalled = 0x00000050, - vgt_perf_UNUSED81 = 0x00000051, - vgt_perf_cm_stalled_by_gog = 0x00000052, - vgt_perf_cm_reading_stalled = 0x00000053, - vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054, - vgt_perf_gog_vs_tbl_stalled = 0x00000055, - vgt_perf_gog_out_indx_stalled = 0x00000056, - vgt_perf_gog_out_prim_stalled = 0x00000057, - vgt_perf_waveid_stalled = 0x00000058, - vgt_perf_gog_busy = 0x00000059, - vgt_perf_REUSED_VS_INDICES = 0x0000005a, - vgt_perf_sclk_reg_vld_event = 0x0000005b, - vgt_perf_vs_conflicting_indices = 0x0000005c, - vgt_perf_sclk_core_vld_event = 0x0000005d, - vgt_perf_hsthdgrp_stalled = 0x0000005e, - vgt_perf_sclk_gs_vld_event = 0x0000005f, - vgt_perf_vgt_spi_lsvert_valid = 0x00000060, - vgt_perf_vgt_spi_lsvert_eov = 0x00000061, - vgt_perf_vgt_spi_lsvert_stalled = 0x00000062, - vgt_perf_vgt_spi_lsvert_starved_busy = 0x00000063, - vgt_perf_vgt_spi_lsvert_starved_idle = 0x00000064, - vgt_perf_vgt_spi_lsvert_static = 0x00000065, - vgt_perf_UNUSED102 = 0x00000066, - vgt_perf_UNUSED103 = 0x00000067, - vgt_perf_UNUSED104 = 0x00000068, - vgt_perf_vgt_spi_hsvert_valid = 0x00000069, - vgt_perf_vgt_spi_hsvert_eov = 0x0000006a, - vgt_perf_vgt_spi_hsvert_stalled = 0x0000006b, - vgt_perf_vgt_spi_hsvert_starved_busy = 0x0000006c, - vgt_perf_vgt_spi_hsvert_starved_idle = 0x0000006d, - vgt_perf_vgt_spi_hsvert_static = 0x0000006e, - vgt_perf_vgt_spi_hsthdgrp_event_window_active = 0x0000006f, - vgt_perf_vgt_spi_hsthdgrp_is_event = 0x00000070, - vgt_perf_vgt_spi_hsthdgrp_send = 0x00000071, - vgt_perf_ds_prims = 0x00000072, - vgt_perf_UNUSED115 = 0x00000073, - vgt_perf_UNUSED116 = 0x00000074, - vgt_perf_hs_thread_groups = 0x00000075, - vgt_perf_UNUSED118 = 0x00000076, - vgt_perf_vs_thread_groups = 0x00000077, - vgt_perf_UNUSED120 = 0x00000078, - vgt_perf_UNUSED121 = 0x00000079, - vgt_perf_UNUSED122 = 0x0000007a, - vgt_perf_gs_done_latency = 0x0000007b, - vgt_perf_vgt_hs_busy = 0x0000007c, - vgt_perf_vgt_te11_busy = 0x0000007d, - vgt_perf_UNUSED126 = 0x0000007e, - vgt_perf_hs_flush = 0x0000007f, - vgt_perf_UNUSED128 = 0x00000080, - vgt_perf_vgt_pa_clipp_eopg = 0x00000081, - vgt_perf_UNUSED130 = 0x00000082, - vgt_perf_UNUSED131 = 0x00000083, - vgt_perf_UNUSED132 = 0x00000084, - vgt_perf_gs_done = 0x00000085, - vgt_perf_vs_done = 0x00000086, - vgt_perf_gs_done_received = 0x00000087, - vgt_perf_UNUSED136 = 0x00000088, - vgt_perf_gs_ring_high_water_mark = 0x00000089, - vgt_perf_vs_table_high_water_mark = 0x0000008a, - vgt_perf_hs_tgs_active_high_water_mark = 0x0000008b, - vgt_perf_pa_clipp_dealloc = 0x0000008c, - vgt_perf_cut_mem_flush_stalled = 0x0000008d, - vgt_perf_vsvert_work_received = 0x0000008e, - vgt_perf_vgt_pa_clipp_starved_after_work = 0x0000008f, - vgt_perf_te11_con_starved_after_work = 0x00000090, - vgt_perf_te11_con_stalled = 0x00000091, - vgt_perf_vgt_spi_vsvert_valid = 0x00000092, - vgt_perf_sclk_te11_vld = 0x00000093, -} VGT_PERFCOUNT_SELECT; - -/* - * IA_PERFCOUNT_SELECT enum - */ - -typedef enum IA_PERFCOUNT_SELECT { - ia_perf_grp_input_event_window_active = 0x00000000, - ia_perf_dma_data_fifo_full = 0x00000001, - ia_perf_UNUSED2 = 0x00000002, - ia_perf_UNUSED3 = 0x00000003, - ia_perf_UNUSED4 = 0x00000004, - ia_perf_UNUSED5 = 0x00000005, - ia_perf_UNUSED6 = 0x00000006, - ia_perf_MC_LAT_BIN_0 = 0x00000007, - ia_perf_MC_LAT_BIN_1 = 0x00000008, - ia_perf_MC_LAT_BIN_2 = 0x00000009, - ia_perf_MC_LAT_BIN_3 = 0x0000000a, - ia_perf_MC_LAT_BIN_4 = 0x0000000b, - ia_perf_MC_LAT_BIN_5 = 0x0000000c, - ia_perf_MC_LAT_BIN_6 = 0x0000000d, - ia_perf_MC_LAT_BIN_7 = 0x0000000e, - ia_perf_ia_busy = 0x0000000f, - ia_perf_sclk_reg_vld_event = 0x00000010, - ia_perf_sclk_input_vld = 0x00000011, - ia_perf_sclk_core_vld = 0x00000012, - ia_perf_sclk_inval_vld = 0x00000013, - ia_perf_ia_dma_return = 0x00000014, - ia_perf_IA_STALLED = 0x00000015, - ia_perf_shift_starved_pipe0_event = 0x00000016, - ia_perf_shift_starved_pipe1_event = 0x00000017, - ia_perf_utcl1_translation_miss_event = 0x00000018, - ia_perf_utcl1_translation_hit_event = 0x00000019, - ia_perf_utcl1_stall_event = 0x0000001a, - ia_perf_utcl1_retry_event = 0x0000001b, - ia_perf_utcl1_consecutive_retry_event = 0x0000001c, - ia_perf_utcl1_request_event_1 = 0x0000001d, - ia_perf_utcl1_request_event_0 = 0x0000001e, - ia_perf_utcl1_stall_utcl2_event = 0x0000001f, -} IA_PERFCOUNT_SELECT; - -/* - * WD_PERFCOUNT_SELECT enum - */ - -typedef enum WD_PERFCOUNT_SELECT { - wd_perf_rbiu_fifos_event_window_active = 0x00000000, - wd_perf_rbiu_dr_fifo_starved = 0x00000001, - wd_perf_rbiu_dr_fifo_stalled = 0x00000002, - wd_perf_rbiu_di_fifo_starved = 0x00000003, - wd_perf_rbiu_di_fifo_stalled = 0x00000004, - wd_perf_wd_busy = 0x00000005, - wd_perf_wd_sclk_reg_vld_event = 0x00000006, - wd_perf_wd_sclk_input_vld_event = 0x00000007, - wd_perf_wd_sclk_core_vld_event = 0x00000008, - wd_perf_WD_STALLED = 0x00000009, - wd_perf_inside_tf_bin_0 = 0x0000000a, - wd_perf_inside_tf_bin_1 = 0x0000000b, - wd_perf_inside_tf_bin_2 = 0x0000000c, - wd_perf_inside_tf_bin_3 = 0x0000000d, - wd_perf_inside_tf_bin_4 = 0x0000000e, - wd_perf_inside_tf_bin_5 = 0x0000000f, - wd_perf_inside_tf_bin_6 = 0x00000010, - wd_perf_inside_tf_bin_7 = 0x00000011, - wd_perf_inside_tf_bin_8 = 0x00000012, - wd_perf_tfreq_lat_bin_0 = 0x00000013, - wd_perf_tfreq_lat_bin_1 = 0x00000014, - wd_perf_tfreq_lat_bin_2 = 0x00000015, - wd_perf_tfreq_lat_bin_3 = 0x00000016, - wd_perf_tfreq_lat_bin_4 = 0x00000017, - wd_perf_tfreq_lat_bin_5 = 0x00000018, - wd_perf_tfreq_lat_bin_6 = 0x00000019, - wd_perf_tfreq_lat_bin_7 = 0x0000001a, - wd_starved_on_hs_done = 0x0000001b, - wd_perf_se0_hs_done_latency = 0x0000001c, - wd_perf_se1_hs_done_latency = 0x0000001d, - wd_perf_se2_hs_done_latency = 0x0000001e, - wd_perf_se3_hs_done_latency = 0x0000001f, - wd_perf_hs_done_se0 = 0x00000020, - wd_perf_hs_done_se1 = 0x00000021, - wd_perf_hs_done_se2 = 0x00000022, - wd_perf_hs_done_se3 = 0x00000023, - wd_perf_null_patches = 0x00000024, - wd_perf_sclk_te11_cld = 0x00000025, - wd_perf_csb_lat_bin_0 = 0x00000026, - wd_perf_csb_lat_bin_1 = 0x00000027, - wd_perf_csb_lat_bin_2 = 0x00000028, - wd_perf_csb_lat_bin_3 = 0x00000029, - wd_perf_csb_lat_bin_4 = 0x0000002a, - wd_perf_csb_lat_bin_5 = 0x0000002b, - wd_perf_csb_lat_bin_6 = 0x0000002c, - wd_perf_csb_lat_bin_7 = 0x0000002d, - wd_perf_rm_stalled_pos_buf = 0x0000002e, - wd_perf_rm_stalled_param_buf = 0x0000002f, - wd_perf_rm_stalled_index_buf = 0x00000030, - wd_perf_rm_stalled_csb_buf = 0x00000031, - wd_perf_utcl1_translation_miss_event = 0x00000032, - wd_perf_utcl1_translation_hit_event = 0x00000033, - wd_perf_utcl1_stall_event = 0x00000034, - wd_perf_utcl1_retry_event = 0x00000035, - wd_perf_utcl1_consecutive_retry_event = 0x00000036, - wd_perf_utcl1_request_event_1 = 0x00000037, - wd_perf_utcl1_request_event_0 = 0x00000038, - wd_perf_utcl1_stall_utcl2_event = 0x00000039, -} WD_PERFCOUNT_SELECT; - -/* - * WD_IA_DRAW_TYPE enum - */ - -typedef enum WD_IA_DRAW_TYPE { - WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, - WD_IA_DRAW_TYPE_REG_XFER = 0x00000001, - WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, - WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, - WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, - WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, - WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, - WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, -} WD_IA_DRAW_TYPE; - -/* - * WD_IA_DRAW_REG_XFER enum - */ - -typedef enum WD_IA_DRAW_REG_XFER { - WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000, - WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001, - WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002, -} WD_IA_DRAW_REG_XFER; - -/* - * WD_IA_DRAW_SOURCE enum - */ - -typedef enum WD_IA_DRAW_SOURCE { - WD_IA_DRAW_SOURCE_DMA = 0x00000000, - WD_IA_DRAW_SOURCE_IMMD = 0x00000001, - WD_IA_DRAW_SOURCE_AUTO = 0x00000002, - WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, -} WD_IA_DRAW_SOURCE; - -/* - * GS_THREADID_SIZE value - */ - -#define GSTHREADID_SIZE 0x00000002 - -/******************************************************* - * GB Enums - *******************************************************/ - -/* - * GB_EDC_DED_MODE enum - */ - -typedef enum GB_EDC_DED_MODE { - GB_EDC_DED_MODE_LOG = 0x00000000, - GB_EDC_DED_MODE_HALT = 0x00000001, - GB_EDC_DED_MODE_INT_HALT = 0x00000002, -} GB_EDC_DED_MODE; - -/* - * VALUE_GB_TILING_CONFIG_TABLE_SIZE value - */ - -#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020 - -/* - * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value - */ - -#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010 - -/******************************************************* - * TP Enums - *******************************************************/ - -/* - * TA_TC_ADDR_MODES enum - */ - -typedef enum TA_TC_ADDR_MODES { - TA_TC_ADDR_MODE_DEFAULT = 0x00000000, - TA_TC_ADDR_MODE_COMP0 = 0x00000001, - TA_TC_ADDR_MODE_COMP1 = 0x00000002, - TA_TC_ADDR_MODE_COMP2 = 0x00000003, - TA_TC_ADDR_MODE_COMP3 = 0x00000004, - TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, - TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, -} TA_TC_ADDR_MODES; - -/* - * TA_PERFCOUNT_SEL enum - */ - -typedef enum TA_PERFCOUNT_SEL { - TA_PERF_SEL_NULL = 0x00000000, - TA_PERF_SEL_sh_fifo_busy = 0x00000001, - TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002, - TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003, - TA_PERF_SEL_sh_fifo_data_busy = 0x00000004, - TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005, - TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006, - TA_PERF_SEL_gradient_busy = 0x00000007, - TA_PERF_SEL_gradient_fifo_busy = 0x00000008, - TA_PERF_SEL_lod_busy = 0x00000009, - TA_PERF_SEL_lod_fifo_busy = 0x0000000a, - TA_PERF_SEL_addresser_busy = 0x0000000b, - TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, - TA_PERF_SEL_aligner_busy = 0x0000000d, - TA_PERF_SEL_write_path_busy = 0x0000000e, - TA_PERF_SEL_ta_busy = 0x0000000f, - TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010, - TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011, - TA_PERF_SEL_sp_ta_data_cycles = 0x00000012, - TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013, - TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014, - TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015, - TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016, - TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017, - TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018, - TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019, - TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a, - TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b, - TA_PERF_SEL_ta_sh_fifo_starved = 0x0000001c, - TA_PERF_SEL_RESERVED_29 = 0x0000001d, - TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e, - TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f, - TA_PERF_SEL_total_wavefronts = 0x00000020, - TA_PERF_SEL_gradient_cycles = 0x00000021, - TA_PERF_SEL_walker_cycles = 0x00000022, - TA_PERF_SEL_aligner_cycles = 0x00000023, - TA_PERF_SEL_image_wavefronts = 0x00000024, - TA_PERF_SEL_image_read_wavefronts = 0x00000025, - TA_PERF_SEL_image_write_wavefronts = 0x00000026, - TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, - TA_PERF_SEL_image_total_cycles = 0x00000028, - TA_PERF_SEL_RESERVED_41 = 0x00000029, - TA_PERF_SEL_RESERVED_42 = 0x0000002a, - TA_PERF_SEL_RESERVED_43 = 0x0000002b, - TA_PERF_SEL_buffer_wavefronts = 0x0000002c, - TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d, - TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e, - TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, - TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030, - TA_PERF_SEL_buffer_total_cycles = 0x00000031, - TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032, - TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033, - TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034, - TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035, - TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, - TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, - TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038, - TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, - TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, - TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, - TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, - TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, - TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, - TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f, - TA_PERF_SEL_color_1_cycle_pixels = 0x00000040, - TA_PERF_SEL_color_2_cycle_pixels = 0x00000041, - TA_PERF_SEL_color_3_cycle_pixels = 0x00000042, - TA_PERF_SEL_color_4_cycle_pixels = 0x00000043, - TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044, - TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045, - TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046, - TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047, - TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048, - TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, - TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, - TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, - TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, - TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, - TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, - TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, - TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, - TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, - TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, - TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, - TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, - TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, - TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, - TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, - TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, - TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, - TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, - TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, - TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, - TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, - TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, - TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, - TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, - TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, - TA_PERF_SEL_write_path_input_cycles = 0x00000062, - TA_PERF_SEL_write_path_output_cycles = 0x00000063, - TA_PERF_SEL_flat_wavefronts = 0x00000064, - TA_PERF_SEL_flat_read_wavefronts = 0x00000065, - TA_PERF_SEL_flat_write_wavefronts = 0x00000066, - TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067, - TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068, - TA_PERF_SEL_reg_sclk_vld = 0x00000069, - TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a, - TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b, - TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c, - TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d, - TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e, - TA_PERF_SEL_xnack_on_phase0 = 0x0000006f, - TA_PERF_SEL_xnack_on_phase1 = 0x00000070, - TA_PERF_SEL_xnack_on_phase2 = 0x00000071, - TA_PERF_SEL_xnack_on_phase3 = 0x00000072, - TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073, - TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074, - TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075, - TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076, -} TA_PERFCOUNT_SEL; - -/* - * TD_PERFCOUNT_SEL enum - */ - -typedef enum TD_PERFCOUNT_SEL { - TD_PERF_SEL_none = 0x00000000, - TD_PERF_SEL_td_busy = 0x00000001, - TD_PERF_SEL_input_busy = 0x00000002, - TD_PERF_SEL_output_busy = 0x00000003, - TD_PERF_SEL_lerp_busy = 0x00000004, - TD_PERF_SEL_reg_sclk_vld = 0x00000005, - TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006, - TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007, - TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008, - TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009, - TD_PERF_SEL_tc_td_fifo_full = 0x0000000a, - TD_PERF_SEL_output_fifo_full = 0x0000000b, - TD_PERF_SEL_RESERVED_12 = 0x0000000c, - TD_PERF_SEL_RESERVED_13 = 0x0000000d, - TD_PERF_SEL_RESERVED_14 = 0x0000000e, - TD_PERF_SEL_tc_stall = 0x0000000f, - TD_PERF_SEL_pc_stall = 0x00000010, - TD_PERF_SEL_gds_stall = 0x00000011, - TD_PERF_SEL_RESERVED_18 = 0x00000012, - TD_PERF_SEL_RESERVED_19 = 0x00000013, - TD_PERF_SEL_gather4_wavefront = 0x00000014, - TD_PERF_SEL_gather4h_wavefront = 0x00000015, - TD_PERF_SEL_gather4h_packed_wavefront = 0x00000016, - TD_PERF_SEL_gather8h_packed_wavefront = 0x00000017, - TD_PERF_SEL_sample_c_wavefront = 0x00000018, - TD_PERF_SEL_load_wavefront = 0x00000019, - TD_PERF_SEL_atomic_wavefront = 0x0000001a, - TD_PERF_SEL_store_wavefront = 0x0000001b, - TD_PERF_SEL_ldfptr_wavefront = 0x0000001c, - TD_PERF_SEL_d16_en_wavefront = 0x0000001d, - TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e, - TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f, - TD_PERF_SEL_coalescable_wavefront = 0x00000020, - TD_PERF_SEL_coalesced_phase = 0x00000021, - TD_PERF_SEL_four_phase_wavefront = 0x00000022, - TD_PERF_SEL_eight_phase_wavefront = 0x00000023, - TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024, - TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025, - TD_PERF_SEL_write_ack_wavefront = 0x00000026, - TD_PERF_SEL_RESERVED_39 = 0x00000027, - TD_PERF_SEL_user_defined_border = 0x00000028, - TD_PERF_SEL_white_border = 0x00000029, - TD_PERF_SEL_opaque_black_border = 0x0000002a, - TD_PERF_SEL_RESERVED_43 = 0x0000002b, - TD_PERF_SEL_RESERVED_44 = 0x0000002c, - TD_PERF_SEL_nack = 0x0000002d, - TD_PERF_SEL_td_sp_traffic = 0x0000002e, - TD_PERF_SEL_consume_gds_traffic = 0x0000002f, - TD_PERF_SEL_addresscmd_poison = 0x00000030, - TD_PERF_SEL_data_poison = 0x00000031, - TD_PERF_SEL_start_cycle_0 = 0x00000032, - TD_PERF_SEL_start_cycle_1 = 0x00000033, - TD_PERF_SEL_start_cycle_2 = 0x00000034, - TD_PERF_SEL_start_cycle_3 = 0x00000035, - TD_PERF_SEL_null_cycle_output = 0x00000036, - TD_PERF_SEL_d16_data_packed = 0x00000037, - TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 0x00000038, -} TD_PERFCOUNT_SEL; - -/* - * TCP_PERFCOUNT_SELECT enum - */ - -typedef enum TCP_PERFCOUNT_SELECT { - TCP_PERF_SEL_GATE_EN1 = 0x00000000, - TCP_PERF_SEL_GATE_EN2 = 0x00000001, - TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002, - TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000003, - TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000004, - TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000005, - TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000006, - TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000007, - TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000008, - TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES = 0x00000009, - TCP_PERF_SEL_LOD_STALL_CYCLES = 0x0000000a, - TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x0000000b, - TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x0000000c, - TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x0000000d, - TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000e, - TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x0000000f, - TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x00000010, - TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x00000011, - TCP_PERF_SEL_TCR_RDRET_STALL = 0x00000012, - TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x00000013, - TCP_PERF_SEL_HOLE_READ_STALL = 0x00000014, - TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000015, - TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000016, - TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000017, - TCP_PERF_SEL_POWER_STALL = 0x00000018, - TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 0x00000019, - TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x0000001a, - TCP_PERF_SEL_TA_TCP_STATE_READ = 0x0000001b, - TCP_PERF_SEL_VOLATILE = 0x0000001c, - TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000001d, - TCP_PERF_SEL_TOTAL_READ = 0x0000001e, - TCP_PERF_SEL_TOTAL_NON_READ = 0x0000001f, - TCP_PERF_SEL_TOTAL_WRITE = 0x00000020, - TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000021, - TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000022, - TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000023, - TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000024, - TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000025, - TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x00000026, - TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000027, - TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000028, - TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x00000029, - TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x0000002a, - TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x0000002b, - TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x0000002c, - TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x0000002d, - TCP_PERF_SEL_SHOOTDOWN = 0x0000002e, - TCP_PERF_SEL_UTCL1_REQUEST = 0x0000002f, - TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x00000030, - TCP_PERF_SEL_UTCL1_TRANSLATION_HIT = 0x00000031, - TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 0x00000032, - TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x00000033, - TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x00000034, - TCP_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000035, - TCP_PERF_SEL_UTCL1_LFIFO_FULL = 0x00000036, - TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000037, - TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000038, - TCP_PERF_SEL_CLIENT_UTCL1_INFLIGHT = 0x00000039, - TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 0x0000003a, - TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x0000003b, - TCP_PERF_SEL_TOTAL_CACHE_ACCESSES = 0x0000003c, - TCP_PERF_SEL_TAGRAM0_REQ = 0x0000003d, - TCP_PERF_SEL_TAGRAM1_REQ = 0x0000003e, - TCP_PERF_SEL_TAGRAM2_REQ = 0x0000003f, - TCP_PERF_SEL_TAGRAM3_REQ = 0x00000040, - TCP_PERF_SEL_TCP_LATENCY = 0x00000041, - TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x00000042, - TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x00000043, - TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000044, - TCP_PERF_SEL_TCC_READ_REQ = 0x00000045, - TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000046, - TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000047, - TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x00000048, - TCP_PERF_SEL_TCC_LRU_REQ = 0x00000049, - TCP_PERF_SEL_TCC_STREAM_REQ = 0x0000004a, - TCP_PERF_SEL_TCC_NC_READ_REQ = 0x0000004b, - TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x0000004c, - TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x0000004d, - TCP_PERF_SEL_TCC_UC_READ_REQ = 0x0000004e, - TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x0000004f, - TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x00000050, - TCP_PERF_SEL_TCC_CC_READ_REQ = 0x00000051, - TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x00000052, - TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x00000053, - TCP_PERF_SEL_TCC_DCC_REQ = 0x00000054, -} TCP_PERFCOUNT_SELECT; - -/* - * TCP_CACHE_POLICIES enum - */ - -typedef enum TCP_CACHE_POLICIES { - TCP_CACHE_POLICY_MISS_LRU = 0x00000000, - TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, - TCP_CACHE_POLICY_HIT_LRU = 0x00000002, - TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, -} TCP_CACHE_POLICIES; - -/* - * TCP_CACHE_STORE_POLICIES enum - */ - -typedef enum TCP_CACHE_STORE_POLICIES { - TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000, - TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001, -} TCP_CACHE_STORE_POLICIES; - -/* - * TCP_WATCH_MODES enum - */ - -typedef enum TCP_WATCH_MODES { - TCP_WATCH_MODE_READ = 0x00000000, - TCP_WATCH_MODE_NONREAD = 0x00000001, - TCP_WATCH_MODE_ATOMIC = 0x00000002, - TCP_WATCH_MODE_ALL = 0x00000003, -} TCP_WATCH_MODES; - -/* - * TCP_DSM_DATA_SEL enum - */ - -typedef enum TCP_DSM_DATA_SEL { - TCP_DSM_DISABLE = 0x00000000, - TCP_DSM_SEL0 = 0x00000001, - TCP_DSM_SEL1 = 0x00000002, - TCP_DSM_SEL_BOTH = 0x00000003, -} TCP_DSM_DATA_SEL; - -/* - * TCP_DSM_SINGLE_WRITE enum - */ - -typedef enum TCP_DSM_SINGLE_WRITE { - TCP_DSM_SINGLE_WRITE_DIS = 0x00000000, - TCP_DSM_SINGLE_WRITE_EN = 0x00000001, -} TCP_DSM_SINGLE_WRITE; - -/* - * TCP_DSM_INJECT_SEL enum - */ - -typedef enum TCP_DSM_INJECT_SEL { - TCP_DSM_INJECT_SEL0 = 0x00000000, - TCP_DSM_INJECT_SEL1 = 0x00000001, - TCP_DSM_INJECT_SEL2 = 0x00000002, - TCP_DSM_INJECT_SEL3 = 0x00000003, -} TCP_DSM_INJECT_SEL; - -/* - * TCP_OPCODE_TYPE enum - */ - -typedef enum TCP_OPCODE_TYPE { - TCP_OPCODE_READ = 0x00000000, - TCP_OPCODE_WRITE = 0x00000001, - TCP_OPCODE_ATOMIC = 0x00000002, - TCP_OPCODE_WBINVL1 = 0x00000003, - TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004, - TCP_OPCODE_GATHERH = 0x00000005, -} TCP_OPCODE_TYPE; - -/******************************************************* - * TCC Enums - *******************************************************/ - -/* - * TCC_PERF_SEL enum - */ - -typedef enum TCC_PERF_SEL { - TCC_PERF_SEL_NONE = 0x00000000, - TCC_PERF_SEL_CYCLE = 0x00000001, - TCC_PERF_SEL_BUSY = 0x00000002, - TCC_PERF_SEL_REQ = 0x00000003, - TCC_PERF_SEL_STREAMING_REQ = 0x00000004, - TCC_PERF_SEL_COMPRESSED_REQ = 0x00000005, - TCC_PERF_SEL_COMPRESSED_0_REQ = 0x00000006, - TCC_PERF_SEL_COMPRESSED_32_REQ = 0x00000007, - TCC_PERF_SEL_METADATA_REQ = 0x00000008, - TCC_PERF_SEL_NC_REQ = 0x00000009, - TCC_PERF_SEL_UC_REQ = 0x0000000a, - TCC_PERF_SEL_CC_REQ = 0x0000000b, - TCC_PERF_SEL_PROBE = 0x0000000c, - TCC_PERF_SEL_PROBE_ALL = 0x0000000d, - TCC_PERF_SEL_INTERNAL_PROBE = 0x0000000e, - TCC_PERF_SEL_READ = 0x0000000f, - TCC_PERF_SEL_WRITE = 0x00000010, - TCC_PERF_SEL_ATOMIC = 0x00000011, - TCC_PERF_SEL_NOP_ACK = 0x00000012, - TCC_PERF_SEL_NOP_RTN0 = 0x00000013, - TCC_PERF_SEL_HIT = 0x00000014, - TCC_PERF_SEL_SECTOR_HIT = 0x00000015, - TCC_PERF_SEL_MISS = 0x00000016, - TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000017, - TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000018, - TCC_PERF_SEL_WRITEBACK = 0x00000019, - TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x0000001a, - TCC_PERF_SEL_SRC_FIFO_FULL = 0x0000001b, - TCC_PERF_SEL_HOLE_FIFO_FULL = 0x0000001c, - TCC_PERF_SEL_EA_WRREQ = 0x0000001d, - TCC_PERF_SEL_EA_WRREQ_64B = 0x0000001e, - TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x0000001f, - TCC_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000020, - TCC_PERF_SEL_EA_WRREQ_STALL = 0x00000021, - TCC_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x00000022, - TCC_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x00000023, - TCC_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x00000024, - TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000025, - TCC_PERF_SEL_EA_WRREQ_LEVEL = 0x00000026, - TCC_PERF_SEL_EA_ATOMIC = 0x00000027, - TCC_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000028, - TCC_PERF_SEL_EA_RDREQ = 0x00000029, - TCC_PERF_SEL_EA_RDREQ_32B = 0x0000002a, - TCC_PERF_SEL_EA_RD_UNCACHED_32B = 0x0000002b, - TCC_PERF_SEL_EA_RD_MDC_32B = 0x0000002c, - TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 0x0000002d, - TCC_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x0000002e, - TCC_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x0000002f, - TCC_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x00000030, - TCC_PERF_SEL_EA_RDREQ_LEVEL = 0x00000031, - TCC_PERF_SEL_TAG_STALL = 0x00000032, - TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x00000033, - TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x00000034, - TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x00000035, - TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x00000036, - TCC_PERF_SEL_TAG_PROBE_STALL = 0x00000037, - TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000038, - TCC_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 0x00000039, - TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x0000003a, - TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x0000003b, - TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x0000003c, - TCC_PERF_SEL_BUBBLE = 0x0000003d, - TCC_PERF_SEL_RETURN_ACK = 0x0000003e, - TCC_PERF_SEL_RETURN_DATA = 0x0000003f, - TCC_PERF_SEL_RETURN_HOLE = 0x00000040, - TCC_PERF_SEL_RETURN_ACK_HOLE = 0x00000041, - TCC_PERF_SEL_IB_REQ = 0x00000042, - TCC_PERF_SEL_IB_STALL = 0x00000043, - TCC_PERF_SEL_IB_TAG_STALL = 0x00000044, - TCC_PERF_SEL_IB_MDC_STALL = 0x00000045, - TCC_PERF_SEL_TCA_LEVEL = 0x00000046, - TCC_PERF_SEL_HOLE_LEVEL = 0x00000047, - TCC_PERF_SEL_EA_RDRET_NACK = 0x00000048, - TCC_PERF_SEL_EA_WRRET_NACK = 0x00000049, - TCC_PERF_SEL_NORMAL_WRITEBACK = 0x0000004a, - TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x0000004b, - TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x0000004c, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x0000004d, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x0000004e, - TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x0000004f, - TCC_PERF_SEL_NORMAL_EVICT = 0x00000050, - TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x00000051, - TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x00000052, - TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x00000053, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x00000054, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x00000055, - TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x00000056, - TCC_PERF_SEL_PROBE_EVICT = 0x00000057, - TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x00000058, - TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x00000059, - TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x0000005a, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x0000005b, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x0000005c, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x0000005d, - TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x0000005e, - TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x0000005f, - TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x00000060, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x00000061, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x00000062, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000063, - TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x00000064, - TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x00000065, - TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x00000066, - TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x00000067, - TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x00000068, - TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x00000069, - TCC_PERF_SEL_TC_OP_INV_METADATA = 0x0000006a, - TCC_PERF_SEL_MDC_REQ = 0x0000006b, - TCC_PERF_SEL_MDC_LEVEL = 0x0000006c, - TCC_PERF_SEL_MDC_TAG_HIT = 0x0000006d, - TCC_PERF_SEL_MDC_SECTOR_HIT = 0x0000006e, - TCC_PERF_SEL_MDC_SECTOR_MISS = 0x0000006f, - TCC_PERF_SEL_MDC_TAG_STALL = 0x00000070, - TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x00000071, - TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x00000072, - TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x00000073, - TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000074, - TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x00000075, - TCC_PERF_SEL_CLIENT0_REQ = 0x00000080, - TCC_PERF_SEL_CLIENT1_REQ = 0x00000081, - TCC_PERF_SEL_CLIENT2_REQ = 0x00000082, - TCC_PERF_SEL_CLIENT3_REQ = 0x00000083, - TCC_PERF_SEL_CLIENT4_REQ = 0x00000084, - TCC_PERF_SEL_CLIENT5_REQ = 0x00000085, - TCC_PERF_SEL_CLIENT6_REQ = 0x00000086, - TCC_PERF_SEL_CLIENT7_REQ = 0x00000087, - TCC_PERF_SEL_CLIENT8_REQ = 0x00000088, - TCC_PERF_SEL_CLIENT9_REQ = 0x00000089, - TCC_PERF_SEL_CLIENT10_REQ = 0x0000008a, - TCC_PERF_SEL_CLIENT11_REQ = 0x0000008b, - TCC_PERF_SEL_CLIENT12_REQ = 0x0000008c, - TCC_PERF_SEL_CLIENT13_REQ = 0x0000008d, - TCC_PERF_SEL_CLIENT14_REQ = 0x0000008e, - TCC_PERF_SEL_CLIENT15_REQ = 0x0000008f, - TCC_PERF_SEL_CLIENT16_REQ = 0x00000090, - TCC_PERF_SEL_CLIENT17_REQ = 0x00000091, - TCC_PERF_SEL_CLIENT18_REQ = 0x00000092, - TCC_PERF_SEL_CLIENT19_REQ = 0x00000093, - TCC_PERF_SEL_CLIENT20_REQ = 0x00000094, - TCC_PERF_SEL_CLIENT21_REQ = 0x00000095, - TCC_PERF_SEL_CLIENT22_REQ = 0x00000096, - TCC_PERF_SEL_CLIENT23_REQ = 0x00000097, - TCC_PERF_SEL_CLIENT24_REQ = 0x00000098, - TCC_PERF_SEL_CLIENT25_REQ = 0x00000099, - TCC_PERF_SEL_CLIENT26_REQ = 0x0000009a, - TCC_PERF_SEL_CLIENT27_REQ = 0x0000009b, - TCC_PERF_SEL_CLIENT28_REQ = 0x0000009c, - TCC_PERF_SEL_CLIENT29_REQ = 0x0000009d, - TCC_PERF_SEL_CLIENT30_REQ = 0x0000009e, - TCC_PERF_SEL_CLIENT31_REQ = 0x0000009f, - TCC_PERF_SEL_CLIENT32_REQ = 0x000000a0, - TCC_PERF_SEL_CLIENT33_REQ = 0x000000a1, - TCC_PERF_SEL_CLIENT34_REQ = 0x000000a2, - TCC_PERF_SEL_CLIENT35_REQ = 0x000000a3, - TCC_PERF_SEL_CLIENT36_REQ = 0x000000a4, - TCC_PERF_SEL_CLIENT37_REQ = 0x000000a5, - TCC_PERF_SEL_CLIENT38_REQ = 0x000000a6, - TCC_PERF_SEL_CLIENT39_REQ = 0x000000a7, - TCC_PERF_SEL_CLIENT40_REQ = 0x000000a8, - TCC_PERF_SEL_CLIENT41_REQ = 0x000000a9, - TCC_PERF_SEL_CLIENT42_REQ = 0x000000aa, - TCC_PERF_SEL_CLIENT43_REQ = 0x000000ab, - TCC_PERF_SEL_CLIENT44_REQ = 0x000000ac, - TCC_PERF_SEL_CLIENT45_REQ = 0x000000ad, - TCC_PERF_SEL_CLIENT46_REQ = 0x000000ae, - TCC_PERF_SEL_CLIENT47_REQ = 0x000000af, - TCC_PERF_SEL_CLIENT48_REQ = 0x000000b0, - TCC_PERF_SEL_CLIENT49_REQ = 0x000000b1, - TCC_PERF_SEL_CLIENT50_REQ = 0x000000b2, - TCC_PERF_SEL_CLIENT51_REQ = 0x000000b3, - TCC_PERF_SEL_CLIENT52_REQ = 0x000000b4, - TCC_PERF_SEL_CLIENT53_REQ = 0x000000b5, - TCC_PERF_SEL_CLIENT54_REQ = 0x000000b6, - TCC_PERF_SEL_CLIENT55_REQ = 0x000000b7, - TCC_PERF_SEL_CLIENT56_REQ = 0x000000b8, - TCC_PERF_SEL_CLIENT57_REQ = 0x000000b9, - TCC_PERF_SEL_CLIENT58_REQ = 0x000000ba, - TCC_PERF_SEL_CLIENT59_REQ = 0x000000bb, - TCC_PERF_SEL_CLIENT60_REQ = 0x000000bc, - TCC_PERF_SEL_CLIENT61_REQ = 0x000000bd, - TCC_PERF_SEL_CLIENT62_REQ = 0x000000be, - TCC_PERF_SEL_CLIENT63_REQ = 0x000000bf, - TCC_PERF_SEL_CLIENT64_REQ = 0x000000c0, - TCC_PERF_SEL_CLIENT65_REQ = 0x000000c1, - TCC_PERF_SEL_CLIENT66_REQ = 0x000000c2, - TCC_PERF_SEL_CLIENT67_REQ = 0x000000c3, - TCC_PERF_SEL_CLIENT68_REQ = 0x000000c4, - TCC_PERF_SEL_CLIENT69_REQ = 0x000000c5, - TCC_PERF_SEL_CLIENT70_REQ = 0x000000c6, - TCC_PERF_SEL_CLIENT71_REQ = 0x000000c7, - TCC_PERF_SEL_CLIENT72_REQ = 0x000000c8, - TCC_PERF_SEL_CLIENT73_REQ = 0x000000c9, - TCC_PERF_SEL_CLIENT74_REQ = 0x000000ca, - TCC_PERF_SEL_CLIENT75_REQ = 0x000000cb, - TCC_PERF_SEL_CLIENT76_REQ = 0x000000cc, - TCC_PERF_SEL_CLIENT77_REQ = 0x000000cd, - TCC_PERF_SEL_CLIENT78_REQ = 0x000000ce, - TCC_PERF_SEL_CLIENT79_REQ = 0x000000cf, - TCC_PERF_SEL_CLIENT80_REQ = 0x000000d0, - TCC_PERF_SEL_CLIENT81_REQ = 0x000000d1, - TCC_PERF_SEL_CLIENT82_REQ = 0x000000d2, - TCC_PERF_SEL_CLIENT83_REQ = 0x000000d3, - TCC_PERF_SEL_CLIENT84_REQ = 0x000000d4, - TCC_PERF_SEL_CLIENT85_REQ = 0x000000d5, - TCC_PERF_SEL_CLIENT86_REQ = 0x000000d6, - TCC_PERF_SEL_CLIENT87_REQ = 0x000000d7, - TCC_PERF_SEL_CLIENT88_REQ = 0x000000d8, - TCC_PERF_SEL_CLIENT89_REQ = 0x000000d9, - TCC_PERF_SEL_CLIENT90_REQ = 0x000000da, - TCC_PERF_SEL_CLIENT91_REQ = 0x000000db, - TCC_PERF_SEL_CLIENT92_REQ = 0x000000dc, - TCC_PERF_SEL_CLIENT93_REQ = 0x000000dd, - TCC_PERF_SEL_CLIENT94_REQ = 0x000000de, - TCC_PERF_SEL_CLIENT95_REQ = 0x000000df, - TCC_PERF_SEL_CLIENT96_REQ = 0x000000e0, - TCC_PERF_SEL_CLIENT97_REQ = 0x000000e1, - TCC_PERF_SEL_CLIENT98_REQ = 0x000000e2, - TCC_PERF_SEL_CLIENT99_REQ = 0x000000e3, - TCC_PERF_SEL_CLIENT100_REQ = 0x000000e4, - TCC_PERF_SEL_CLIENT101_REQ = 0x000000e5, - TCC_PERF_SEL_CLIENT102_REQ = 0x000000e6, - TCC_PERF_SEL_CLIENT103_REQ = 0x000000e7, - TCC_PERF_SEL_CLIENT104_REQ = 0x000000e8, - TCC_PERF_SEL_CLIENT105_REQ = 0x000000e9, - TCC_PERF_SEL_CLIENT106_REQ = 0x000000ea, - TCC_PERF_SEL_CLIENT107_REQ = 0x000000eb, - TCC_PERF_SEL_CLIENT108_REQ = 0x000000ec, - TCC_PERF_SEL_CLIENT109_REQ = 0x000000ed, - TCC_PERF_SEL_CLIENT110_REQ = 0x000000ee, - TCC_PERF_SEL_CLIENT111_REQ = 0x000000ef, - TCC_PERF_SEL_CLIENT112_REQ = 0x000000f0, - TCC_PERF_SEL_CLIENT113_REQ = 0x000000f1, - TCC_PERF_SEL_CLIENT114_REQ = 0x000000f2, - TCC_PERF_SEL_CLIENT115_REQ = 0x000000f3, - TCC_PERF_SEL_CLIENT116_REQ = 0x000000f4, - TCC_PERF_SEL_CLIENT117_REQ = 0x000000f5, - TCC_PERF_SEL_CLIENT118_REQ = 0x000000f6, - TCC_PERF_SEL_CLIENT119_REQ = 0x000000f7, - TCC_PERF_SEL_CLIENT120_REQ = 0x000000f8, - TCC_PERF_SEL_CLIENT121_REQ = 0x000000f9, - TCC_PERF_SEL_CLIENT122_REQ = 0x000000fa, - TCC_PERF_SEL_CLIENT123_REQ = 0x000000fb, - TCC_PERF_SEL_CLIENT124_REQ = 0x000000fc, - TCC_PERF_SEL_CLIENT125_REQ = 0x000000fd, - TCC_PERF_SEL_CLIENT126_REQ = 0x000000fe, - TCC_PERF_SEL_CLIENT127_REQ = 0x000000ff, -} TCC_PERF_SEL; - -/* - * TCA_PERF_SEL enum - */ - -typedef enum TCA_PERF_SEL { - TCA_PERF_SEL_NONE = 0x00000000, - TCA_PERF_SEL_CYCLE = 0x00000001, - TCA_PERF_SEL_BUSY = 0x00000002, - TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003, - TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004, - TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005, - TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006, - TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007, - TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008, - TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009, - TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a, - TCA_PERF_SEL_REQ_TCC0 = 0x0000000b, - TCA_PERF_SEL_REQ_TCC1 = 0x0000000c, - TCA_PERF_SEL_REQ_TCC2 = 0x0000000d, - TCA_PERF_SEL_REQ_TCC3 = 0x0000000e, - TCA_PERF_SEL_REQ_TCC4 = 0x0000000f, - TCA_PERF_SEL_REQ_TCC5 = 0x00000010, - TCA_PERF_SEL_REQ_TCC6 = 0x00000011, - TCA_PERF_SEL_REQ_TCC7 = 0x00000012, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019, - TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a, - TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b, - TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c, - TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d, - TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e, - TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f, - TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020, - TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021, - TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022, -} TCA_PERF_SEL; - -/******************************************************* - * GRBM Enums - *******************************************************/ - -/* - * GRBM_PERF_SEL enum - */ - -typedef enum GRBM_PERF_SEL { - GRBM_PERF_SEL_COUNT = 0x00000000, - GRBM_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, - GRBM_PERF_SEL_CP_BUSY = 0x00000003, - GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, - GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, - GRBM_PERF_SEL_CB_BUSY = 0x00000006, - GRBM_PERF_SEL_DB_BUSY = 0x00000007, - GRBM_PERF_SEL_PA_BUSY = 0x00000008, - GRBM_PERF_SEL_SC_BUSY = 0x00000009, - GRBM_PERF_SEL_RESERVED_6 = 0x0000000a, - GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, - GRBM_PERF_SEL_SX_BUSY = 0x0000000c, - GRBM_PERF_SEL_TA_BUSY = 0x0000000d, - GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, - GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, - GRBM_PERF_SEL_RESERVED_5 = 0x00000010, - GRBM_PERF_SEL_VGT_BUSY = 0x00000011, - GRBM_PERF_SEL_RESERVED_4 = 0x00000012, - GRBM_PERF_SEL_RESERVED_3 = 0x00000013, - GRBM_PERF_SEL_RESERVED_2 = 0x00000014, - GRBM_PERF_SEL_RESERVED_1 = 0x00000015, - GRBM_PERF_SEL_RESERVED_0 = 0x00000016, - GRBM_PERF_SEL_IA_BUSY = 0x00000017, - GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018, - GRBM_PERF_SEL_GDS_BUSY = 0x00000019, - GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, - GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, - GRBM_PERF_SEL_TC_BUSY = 0x0000001c, - GRBM_PERF_SEL_CPG_BUSY = 0x0000001d, - GRBM_PERF_SEL_CPC_BUSY = 0x0000001e, - GRBM_PERF_SEL_CPF_BUSY = 0x0000001f, - GRBM_PERF_SEL_WD_BUSY = 0x00000020, - GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x00000021, - GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022, - GRBM_PERF_SEL_EA_BUSY = 0x00000023, - GRBM_PERF_SEL_RMI_BUSY = 0x00000024, - GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025, -} GRBM_PERF_SEL; - -/* - * GRBM_SE0_PERF_SEL enum - */ - -typedef enum GRBM_SE0_PERF_SEL { - GRBM_SE0_PERF_SEL_COUNT = 0x00000000, - GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, - GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f, -} GRBM_SE0_PERF_SEL; - -/* - * GRBM_SE1_PERF_SEL enum - */ - -typedef enum GRBM_SE1_PERF_SEL { - GRBM_SE1_PERF_SEL_COUNT = 0x00000000, - GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, - GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f, -} GRBM_SE1_PERF_SEL; - -/* - * GRBM_SE2_PERF_SEL enum - */ - -typedef enum GRBM_SE2_PERF_SEL { - GRBM_SE2_PERF_SEL_COUNT = 0x00000000, - GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, - GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f, -} GRBM_SE2_PERF_SEL; - -/* - * GRBM_SE3_PERF_SEL enum - */ - -typedef enum GRBM_SE3_PERF_SEL { - GRBM_SE3_PERF_SEL_COUNT = 0x00000000, - GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, - GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, - GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, - GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, - GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005, - GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, - GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, - GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, - GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, - GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, - GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b, - GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, - GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d, - GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, - GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f, -} GRBM_SE3_PERF_SEL; - -/******************************************************* - * CP Enums - *******************************************************/ - -/* - * CP_RING_ID enum - */ - -typedef enum CP_RING_ID { - RINGID0 = 0x00000000, - RINGID1 = 0x00000001, - RINGID2 = 0x00000002, - RINGID3 = 0x00000003, -} CP_RING_ID; - -/* - * CP_PIPE_ID enum - */ - -typedef enum CP_PIPE_ID { - PIPE_ID0 = 0x00000000, - PIPE_ID1 = 0x00000001, - PIPE_ID2 = 0x00000002, - PIPE_ID3 = 0x00000003, -} CP_PIPE_ID; - -/* - * CP_ME_ID enum - */ - -typedef enum CP_ME_ID { - ME_ID0 = 0x00000000, - ME_ID1 = 0x00000001, - ME_ID2 = 0x00000002, - ME_ID3 = 0x00000003, -} CP_ME_ID; - -/* - * SPM_PERFMON_STATE enum - */ - -typedef enum SPM_PERFMON_STATE { - STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, - STRM_PERFMON_STATE_START_COUNTING = 0x00000001, - STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, - STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, - STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, - STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} SPM_PERFMON_STATE; - -/* - * CP_PERFMON_STATE enum - */ - -typedef enum CP_PERFMON_STATE { - CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, - CP_PERFMON_STATE_START_COUNTING = 0x00000001, - CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, - CP_PERFMON_STATE_RESERVED_3 = 0x00000003, - CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, - CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} CP_PERFMON_STATE; - -/* - * CP_PERFMON_ENABLE_MODE enum - */ - -typedef enum CP_PERFMON_ENABLE_MODE { - CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, - CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, - CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, - CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, -} CP_PERFMON_ENABLE_MODE; - -/* - * CPG_PERFCOUNT_SEL enum - */ - -typedef enum CPG_PERFCOUNT_SEL { - CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, - CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, - CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, - CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003, - CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, - CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, - CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, - CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, - CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008, - CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, - CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, - CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, - CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, - CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, - CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, - CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, - CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, - CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, - CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, - CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, - CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, - CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, - CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, - CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, - CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, - CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, - CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, - CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, - CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, - CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, - CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e, - CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, - CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, - CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, - CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022, - CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023, - CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, - CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, - CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, - CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, - CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028, - CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, - CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, - CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, - CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, - CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, - CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e, - CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f, - CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030, - CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031, - CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000032, - CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000033, - CPG_PERF_SEL_CPG_STAT_STALL = 0x00000034, - CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000035, - CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000036, - CPF_PERF_SEL_CPG_TCIU_STALL = 0x00000037, - CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000038, - CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x00000039, - CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003a, -} CPG_PERFCOUNT_SEL; - -/* - * CPF_PERFCOUNT_SEL enum - */ - -typedef enum CPF_PERFCOUNT_SEL { - CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, - CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001, - CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, - CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, - CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, - CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, - CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, - CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007, - CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008, - CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009, - CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, - CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, - CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, - CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, - CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, - CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f, - CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010, - CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011, - CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012, - CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013, - CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014, - CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015, - CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000016, - CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000017, - CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000018, - CPF_PERF_SEL_CPF_STAT_STALL = 0x00000019, - CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001a, - CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001b, - CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001c, - CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001d, - CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001e, - CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x0000001f, -} CPF_PERFCOUNT_SEL; - -/* - * CPC_PERFCOUNT_SEL enum - */ - -typedef enum CPC_PERFCOUNT_SEL { - CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, - CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, - CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, - CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003, - CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004, - CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009, - CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a, - CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, - CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, - CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011, - CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012, - CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, - CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, - CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, - CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016, - CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017, - CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018, - CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019, - CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a, - CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b, - CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c, - CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d, - CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e, - CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f, - CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020, - CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021, - CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022, -} CPC_PERFCOUNT_SEL; - -/* - * CP_ALPHA_TAG_RAM_SEL enum - */ - -typedef enum CP_ALPHA_TAG_RAM_SEL { - CPG_TAG_RAM = 0x00000000, - CPC_TAG_RAM = 0x00000001, - CPF_TAG_RAM = 0x00000002, - RSV_TAG_RAM = 0x00000003, -} CP_ALPHA_TAG_RAM_SEL; - -/* - * CPF_PERFCOUNTWINDOW_SEL enum - */ - -typedef enum CPF_PERFCOUNTWINDOW_SEL { - CPF_PERFWINDOW_SEL_CSF = 0x00000000, - CPF_PERFWINDOW_SEL_HQD1 = 0x00000001, - CPF_PERFWINDOW_SEL_HQD2 = 0x00000002, - CPF_PERFWINDOW_SEL_RDMA = 0x00000003, - CPF_PERFWINDOW_SEL_RWPP = 0x00000004, -} CPF_PERFCOUNTWINDOW_SEL; - -/* - * CPG_PERFCOUNTWINDOW_SEL enum - */ - -typedef enum CPG_PERFCOUNTWINDOW_SEL { - CPG_PERFWINDOW_SEL_PFP = 0x00000000, - CPG_PERFWINDOW_SEL_ME = 0x00000001, - CPG_PERFWINDOW_SEL_CE = 0x00000002, - CPG_PERFWINDOW_SEL_RESERVED1 = 0x00000003, - CPG_PERFWINDOW_SEL_MEC1 = 0x00000004, - CPG_PERFWINDOW_SEL_MEC2 = 0x00000005, - CPG_PERFWINDOW_SEL_DFY = 0x00000006, - CPG_PERFWINDOW_SEL_DMA = 0x00000007, - CPG_PERFWINDOW_SEL_SHADOW = 0x00000008, - CPG_PERFWINDOW_SEL_RB = 0x00000009, - CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a, - CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b, - CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c, - CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d, - CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e, - CPG_PERFWINDOW_SEL_MEMWR = 0x0000000f, - CPG_PERFWINDOW_SEL_MEMRD = 0x00000010, - CPG_PERFWINDOW_SEL_VGT0 = 0x00000011, - CPG_PERFWINDOW_SEL_VGT1 = 0x00000012, - CPG_PERFWINDOW_SEL_APPEND = 0x00000013, - CPG_PERFWINDOW_SEL_QURD = 0x00000014, - CPG_PERFWINDOW_SEL_CPCQU = 0x00000015, - CPG_PERFWINDOW_SEL_SR = 0x00000016, - CPG_PERFWINDOW_SEL_QU_EOP = 0x00000017, - CPG_PERFWINDOW_SEL_QU_STRM = 0x00000018, - CPG_PERFWINDOW_SEL_QU_PIPE = 0x00000019, - CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001a, - CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001b, - CPG_PERFWINDOW_SEL_SD = 0x0000001c, -} CPG_PERFCOUNTWINDOW_SEL; - -/* - * CPF_LATENCY_STATS_SEL enum - */ - -typedef enum CPF_LATENCY_STATS_SEL { - CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, - CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, - CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, - CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, - CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, - CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, - CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006, - CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007, - CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008, -} CPF_LATENCY_STATS_SEL; - -/* - * CPG_LATENCY_STATS_SEL enum - */ - -typedef enum CPG_LATENCY_STATS_SEL { - CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, - CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, - CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, - CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, - CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, - CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, - CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006, - CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007, - CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008, - CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009, - CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a, - CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b, - CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000c, - CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000d, - CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000e, - CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000f, - CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x00000010, - CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x00000011, -} CPG_LATENCY_STATS_SEL; - -/* - * CPC_LATENCY_STATS_SEL enum - */ - -typedef enum CPC_LATENCY_STATS_SEL { - CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, - CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, - CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, - CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, - CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, - CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, -} CPC_LATENCY_STATS_SEL; - -/* - * SEM_RESPONSE value - */ - -#define SEM_ECC_ERROR 0x00000000 -#define SEM_TRANS_ERROR 0x00000001 -#define SEM_FAILED 0x00000002 -#define SEM_PASSED 0x00000003 - -/* - * IQ_RETRY_TYPE value - */ - -#define IQ_QUEUE_SLEEP 0x00000000 -#define IQ_OFFLOAD_RETRY 0x00000001 -#define IQ_SCH_WAVE_MSG 0x00000002 -#define IQ_SEM_REARM 0x00000003 -#define IQ_DEQUEUE_RETRY 0x00000004 - -/* - * IQ_INTR_TYPE value - */ - -#define IQ_INTR_TYPE_PQ 0x00000000 -#define IQ_INTR_TYPE_IB 0x00000001 -#define IQ_INTR_TYPE_MQD 0x00000002 - -/* - * VMID_SIZE value - */ - -#define VMID_SZ 0x00000004 - -/* - * SRCID_SECURE value - */ - -#define SRCID_SECURE_E 0x0000000e -#define SRCID_RLC 0x00000000 -#define SRCID_RLCV 0x00000006 -#define SRCID_SECURE_CP 0x00000007 -#define SRCID_NONSECURE_CP 0x00000001 -#define SRCID_SECURE_CP_RCIU 0x00000007 -#define SRCID_NONSECURE_CP_RCIU 0x00000001 - -/* - * CONFIG_SPACE value - */ - -#define CONFIG_SPACE_START 0x00002000 -#define CONFIG_SPACE_END 0x00009fff - -/* - * CONFIG_SPACE1 value - */ - -#define CONFIG_SPACE1_START 0x00002000 -#define CONFIG_SPACE1_END 0x00002bff - -/* - * CONFIG_SPACE2 value - */ - -#define CONFIG_SPACE2_START 0x00003000 -#define CONFIG_SPACE2_END 0x00009fff - -/* - * UCONFIG_SPACE value - */ - -#define UCONFIG_SPACE_START 0x0000c000 -#define UCONFIG_SPACE_END 0x0000ffff - -/* - * PERSISTENT_SPACE value - */ - -#define PERSISTENT_SPACE_START 0x00002c00 -#define PERSISTENT_SPACE_END 0x00002fff - -/* - * CONTEXT_SPACE value - */ - -#define CONTEXT_SPACE_START 0x0000a000 -#define CONTEXT_SPACE_END 0x0000bfff - -/******************************************************* - * SQ_UC Enums - *******************************************************/ - -/* - * VALUE_SQ_ENC_SOP1 value - */ - -#define SQ_ENC_SOP1_BITS 0xbe800000 -#define SQ_ENC_SOP1_MASK 0xff800000 -#define SQ_ENC_SOP1_FIELD 0x0000017d - -/* - * VALUE_SQ_ENC_SOPC value - */ - -#define SQ_ENC_SOPC_BITS 0xbf000000 -#define SQ_ENC_SOPC_MASK 0xff800000 -#define SQ_ENC_SOPC_FIELD 0x0000017e - -/* - * VALUE_SQ_ENC_SOPP value - */ - -#define SQ_ENC_SOPP_BITS 0xbf800000 -#define SQ_ENC_SOPP_MASK 0xff800000 -#define SQ_ENC_SOPP_FIELD 0x0000017f - -/* - * VALUE_SQ_ENC_SOPK value - */ - -#define SQ_ENC_SOPK_BITS 0xb0000000 -#define SQ_ENC_SOPK_MASK 0xf0000000 -#define SQ_ENC_SOPK_FIELD 0x0000000b - -/* - * VALUE_SQ_ENC_SOP2 value - */ - -#define SQ_ENC_SOP2_BITS 0x80000000 -#define SQ_ENC_SOP2_MASK 0xc0000000 -#define SQ_ENC_SOP2_FIELD 0x00000002 - -/* - * VALUE_SQ_ENC_SMEM value - */ - -#define SQ_ENC_SMEM_BITS 0xc0000000 -#define SQ_ENC_SMEM_MASK 0xfc000000 -#define SQ_ENC_SMEM_FIELD 0x00000030 - -/* - * VALUE_SQ_ENC_VOP1 value - */ - -#define SQ_ENC_VOP1_BITS 0x7e000000 -#define SQ_ENC_VOP1_MASK 0xfe000000 -#define SQ_ENC_VOP1_FIELD 0x0000003f - -/* - * VALUE_SQ_ENC_VOPC value - */ - -#define SQ_ENC_VOPC_BITS 0x7c000000 -#define SQ_ENC_VOPC_MASK 0xfe000000 -#define SQ_ENC_VOPC_FIELD 0x0000003e - -/* - * VALUE_SQ_ENC_VOP2 value - */ - -#define SQ_ENC_VOP2_BITS 0x00000000 -#define SQ_ENC_VOP2_MASK 0x80000000 -#define SQ_ENC_VOP2_FIELD 0x00000000 - -/* - * VALUE_SQ_ENC_VINTRP value - */ - -#define SQ_ENC_VINTRP_BITS 0xd4000000 -#define SQ_ENC_VINTRP_MASK 0xfc000000 -#define SQ_ENC_VINTRP_FIELD 0x00000035 - -/* - * VALUE_SQ_ENC_VOP3P value - */ - -#define SQ_ENC_VOP3P_BITS 0xd3800000 -#define SQ_ENC_VOP3P_MASK 0xff800000 -#define SQ_ENC_VOP3P_FIELD 0x000001a7 - -/* - * VALUE_SQ_ENC_VOP3 value - */ - -#define SQ_ENC_VOP3_BITS 0xd0000000 -#define SQ_ENC_VOP3_MASK 0xfc000000 -#define SQ_ENC_VOP3_FIELD 0x00000034 - -/* - * VALUE_SQ_ENC_DS value - */ - -#define SQ_ENC_DS_BITS 0xd8000000 -#define SQ_ENC_DS_MASK 0xfc000000 -#define SQ_ENC_DS_FIELD 0x00000036 - -/* - * VALUE_SQ_ENC_MUBUF value - */ - -#define SQ_ENC_MUBUF_BITS 0xe0000000 -#define SQ_ENC_MUBUF_MASK 0xfc000000 -#define SQ_ENC_MUBUF_FIELD 0x00000038 - -/* - * VALUE_SQ_ENC_MTBUF value - */ - -#define SQ_ENC_MTBUF_BITS 0xe8000000 -#define SQ_ENC_MTBUF_MASK 0xfc000000 -#define SQ_ENC_MTBUF_FIELD 0x0000003a - -/* - * VALUE_SQ_ENC_MIMG value - */ - -#define SQ_ENC_MIMG_BITS 0xf0000000 -#define SQ_ENC_MIMG_MASK 0xfc000000 -#define SQ_ENC_MIMG_FIELD 0x0000003c - -/* - * VALUE_SQ_ENC_EXP value - */ - -#define SQ_ENC_EXP_BITS 0xc4000000 -#define SQ_ENC_EXP_MASK 0xfc000000 -#define SQ_ENC_EXP_FIELD 0x00000031 - -/* - * VALUE_SQ_ENC_FLAT value - */ - -#define SQ_ENC_FLAT_BITS 0xdc000000 -#define SQ_ENC_FLAT_MASK 0xfc000000 -#define SQ_ENC_FLAT_FIELD 0x00000037 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value - */ - -#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x00000100 - -/* - * VALUE_SQ_SENDMSG_STREAMID_SHIFT value - */ - -#define SQ_SENDMSG_STREAMID_SHIFT 0x00000008 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value - */ - -#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x00000100 - -/* - * VALUE_SQ_WAITCNT_LGKM_SHIFT value - */ - -#define SQ_WAITCNT_LGKM_SHIFT 0x00000008 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value - */ - -#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x00000140 - -/* - * VALUE_SQ_HWREG_ID_SIZE value - */ - -#define SQ_HWREG_ID_SIZE 0x00000006 - -/* - * VALUE_SQ_NUM_ATTR value - */ - -#define SQ_NUM_ATTR 0x00000021 - -/* - * VALUE_SQ_WAITCNT_VM_SIZE value - */ - -#define SQ_WAITCNT_VM_SIZE 0x00000004 - -/* - * VALUE_SQ_SENDMSG_STREAMID_SIZE value - */ - -#define SQ_SENDMSG_STREAMID_SIZE 0x00000002 - -/* - * VALUE_SQ_SENDMSG_GSOP_SIZE value - */ - -#define SQ_SENDMSG_GSOP_SIZE 0x00000002 - -/* - * VALUE_SQ_EXP_NUM_GDS value - */ - -#define SQ_EXP_NUM_GDS 0x00000005 - -/* - * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value - */ - -#define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004 - -/* - * VALUE_SQ_WAITCNT_EXP_SIZE value - */ - -#define SQ_WAITCNT_EXP_SIZE 0x00000003 - -/* - * VALUE_SQ_V_OP3P_COUNT value - */ - -#define SQ_V_OP3P_COUNT 0x00000080 - -/* - * VALUE_SQ_SRC_VGPR_BIT value - */ - -#define SQ_SRC_VGPR_BIT 0x00000100 - -/* - * VALUE_SQ_WAITCNT_VM_HI_SIZE value - */ - -#define SQ_WAITCNT_VM_HI_SIZE 0x00000002 - -/* - * VALUE_SQ_HWREG_SIZE_SHIFT value - */ - -#define SQ_HWREG_SIZE_SHIFT 0x0000000b - -/* - * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value - */ - -#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x00000004 - -/* - * VALUE_SQ_HWREG_OFFSET_SIZE value - */ - -#define SQ_HWREG_OFFSET_SIZE 0x00000005 - -/* - * VALUE_SQ_V_OP3_2IN_OFFSET value - */ - -#define SQ_V_OP3_2IN_OFFSET 0x00000280 - -/* - * VALUE_SQ_HWREG_OFFSET_SHIFT value - */ - -#define SQ_HWREG_OFFSET_SHIFT 0x00000006 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value - */ - -#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270 - -/* - * VALUE_SQ_HWREG_ID_SHIFT value - */ - -#define SQ_HWREG_ID_SHIFT 0x00000000 - -/* - * VALUE_SQ_NUM_VGPR value - */ - -#define SQ_NUM_VGPR 0x00000100 - -/* - * VALUE_SQ_EXP_NUM_POS value - */ - -#define SQ_EXP_NUM_POS 0x00000004 - -/* - * VALUE_SQ_V_OP2_COUNT value - */ - -#define SQ_V_OP2_COUNT 0x00000040 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value - */ - -#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x00000000 - -/* - * VALUE_SQ_V_OP3_INTRP_COUNT value - */ - -#define SQ_V_OP3_INTRP_COUNT 0x0000000c - -/* - * VALUE_SQ_V_OP3_3IN_OFFSET value - */ - -#define SQ_V_OP3_3IN_OFFSET 0x000001c0 - -/* - * VALUE_SQ_WAITCNT_VM_SHIFT value - */ - -#define SQ_WAITCNT_VM_SHIFT 0x00000000 - -/* - * VALUE_SQ_NUM_TTMP value - */ - -#define SQ_NUM_TTMP 0x00000010 - -/* - * VALUE_SQ_V_INTRP_COUNT value - */ - -#define SQ_V_INTRP_COUNT 0x00000004 - -/* - * VALUE_SQ_SENDMSG_GSOP_SHIFT value - */ - -#define SQ_SENDMSG_GSOP_SHIFT 0x00000004 - -/* - * VALUE_SQ_SENDMSG_MSG_SIZE value - */ - -#define SQ_SENDMSG_MSG_SIZE 0x00000004 - -/* - * VALUE_SQ_NUM_SGPR value - */ - -#define SQ_NUM_SGPR 0x00000066 - -/* - * VALUE_SQ_V_OP1_COUNT value - */ - -#define SQ_V_OP1_COUNT 0x00000080 - -/* - * VALUE_SQ_EXP_NUM_PARAM value - */ - -#define SQ_EXP_NUM_PARAM 0x00000020 - -/* - * VALUE_SQ_EXP_NUM_MRT value - */ - -#define SQ_EXP_NUM_MRT 0x00000008 - -/* - * VALUE_SQ_V_OP3_INTRP_OFFSET value - */ - -#define SQ_V_OP3_INTRP_OFFSET 0x00000274 - -/* - * VALUE_SQ_WAITCNT_EXP_SHIFT value - */ - -#define SQ_WAITCNT_EXP_SHIFT 0x00000004 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value - */ - -#define SQ_XLATE_VOP3_TO_VOP3P_COUNT 0x00000080 - -/* - * VALUE_SQ_SENDMSG_MSG_SHIFT value - */ - -#define SQ_SENDMSG_MSG_SHIFT 0x00000000 - -/* - * VALUE_SQ_WAITCNT_VM_HI_SHIFT value - */ - -#define SQ_WAITCNT_VM_HI_SHIFT 0x0000000e - -/* - * VALUE_SQ_V_OP3_2IN_COUNT value - */ - -#define SQ_V_OP3_2IN_COUNT 0x00000080 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value - */ - -#define SQ_XLATE_VOP3_TO_VOP3P_OFFSET 0x00000380 - -/* - * VALUE_SQ_V_OP3_3IN_COUNT value - */ - -#define SQ_V_OP3_3IN_COUNT 0x000000b0 - -/* - * VALUE_SQ_V_OPC_COUNT value - */ - -#define SQ_V_OPC_COUNT 0x00000100 - -/* - * VALUE_SQ_HWREG_SIZE_SIZE value - */ - -#define SQ_HWREG_SIZE_SIZE 0x00000005 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value - */ - -#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x00000040 - -/* - * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value - */ - -#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x00000080 - -/* - * VALUE_SQ_SENDMSG_SYSTEM_SIZE value - */ - -#define SQ_SENDMSG_SYSTEM_SIZE 0x00000003 - -/* - * VALUE_SQ_WAITCNT_LGKM_SIZE value - */ - -#define SQ_WAITCNT_LGKM_SIZE 0x00000004 - -/* - * VALUE_SQ_SEG value - */ - -#define SQ_FLAT 0x00000000 -#define SQ_SCRATCH 0x00000001 -#define SQ_GLOBAL 0x00000002 - -/* - * VALUE_SQ_PARAM value - */ - -#define SQ_PARAM_P10 0x00000000 -#define SQ_PARAM_P20 0x00000001 -#define SQ_PARAM_P0 0x00000002 - -/* - * VALUE_SQ_OP_MTBUF value - */ - -#define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_TBUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x00000008 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x00000009 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b -#define SQ_TBUFFER_STORE_FORMAT_D16_X 0x0000000c -#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f - -/* - * VALUE_SQ_SDST_EXEC value - */ - -#define SQ_EXEC_LO 0x0000007e -#define SQ_EXEC_HI 0x0000007f - -/* - * VALUE_SQ_GS_OP value - */ - -#define SQ_GS_OP_NOP 0x00000000 -#define SQ_GS_OP_CUT 0x00000001 -#define SQ_GS_OP_EMIT 0x00000002 -#define SQ_GS_OP_EMIT_CUT 0x00000003 - -/* - * VALUE_SQ_TGT_INTERNAL value - */ - -#define SQ_EXP_GDS0 0x00000018 - -/* - * VALUE_SQ_TRAP value - */ - -#define SQ_TTMP0 0x0000006c -#define SQ_TTMP1 0x0000006d -#define SQ_TTMP2 0x0000006e -#define SQ_TTMP3 0x0000006f -#define SQ_TTMP4 0x00000070 -#define SQ_TTMP5 0x00000071 -#define SQ_TTMP6 0x00000072 -#define SQ_TTMP7 0x00000073 -#define SQ_TTMP8 0x00000074 -#define SQ_TTMP9 0x00000075 -#define SQ_TTMP10 0x00000076 -#define SQ_TTMP11 0x00000077 -#define SQ_TTMP12 0x00000078 -#define SQ_TTMP13 0x00000079 -#define SQ_TTMP14 0x0000007a -#define SQ_TTMP15 0x0000007b - -/* - * VALUE_SQ_OP_VOPC value - */ - -#define SQ_V_CMP_CLASS_F32 0x00000010 -#define SQ_V_CMPX_CLASS_F32 0x00000011 -#define SQ_V_CMP_CLASS_F64 0x00000012 -#define SQ_V_CMPX_CLASS_F64 0x00000013 -#define SQ_V_CMP_CLASS_F16 0x00000014 -#define SQ_V_CMPX_CLASS_F16 0x00000015 -#define SQ_V_CMP_F_F16 0x00000020 -#define SQ_V_CMP_LT_F16 0x00000021 -#define SQ_V_CMP_EQ_F16 0x00000022 -#define SQ_V_CMP_LE_F16 0x00000023 -#define SQ_V_CMP_GT_F16 0x00000024 -#define SQ_V_CMP_LG_F16 0x00000025 -#define SQ_V_CMP_GE_F16 0x00000026 -#define SQ_V_CMP_O_F16 0x00000027 -#define SQ_V_CMP_U_F16 0x00000028 -#define SQ_V_CMP_NGE_F16 0x00000029 -#define SQ_V_CMP_NLG_F16 0x0000002a -#define SQ_V_CMP_NGT_F16 0x0000002b -#define SQ_V_CMP_NLE_F16 0x0000002c -#define SQ_V_CMP_NEQ_F16 0x0000002d -#define SQ_V_CMP_NLT_F16 0x0000002e -#define SQ_V_CMP_TRU_F16 0x0000002f -#define SQ_V_CMPX_F_F16 0x00000030 -#define SQ_V_CMPX_LT_F16 0x00000031 -#define SQ_V_CMPX_EQ_F16 0x00000032 -#define SQ_V_CMPX_LE_F16 0x00000033 -#define SQ_V_CMPX_GT_F16 0x00000034 -#define SQ_V_CMPX_LG_F16 0x00000035 -#define SQ_V_CMPX_GE_F16 0x00000036 -#define SQ_V_CMPX_O_F16 0x00000037 -#define SQ_V_CMPX_U_F16 0x00000038 -#define SQ_V_CMPX_NGE_F16 0x00000039 -#define SQ_V_CMPX_NLG_F16 0x0000003a -#define SQ_V_CMPX_NGT_F16 0x0000003b -#define SQ_V_CMPX_NLE_F16 0x0000003c -#define SQ_V_CMPX_NEQ_F16 0x0000003d -#define SQ_V_CMPX_NLT_F16 0x0000003e -#define SQ_V_CMPX_TRU_F16 0x0000003f -#define SQ_V_CMP_F_F32 0x00000040 -#define SQ_V_CMP_LT_F32 0x00000041 -#define SQ_V_CMP_EQ_F32 0x00000042 -#define SQ_V_CMP_LE_F32 0x00000043 -#define SQ_V_CMP_GT_F32 0x00000044 -#define SQ_V_CMP_LG_F32 0x00000045 -#define SQ_V_CMP_GE_F32 0x00000046 -#define SQ_V_CMP_O_F32 0x00000047 -#define SQ_V_CMP_U_F32 0x00000048 -#define SQ_V_CMP_NGE_F32 0x00000049 -#define SQ_V_CMP_NLG_F32 0x0000004a -#define SQ_V_CMP_NGT_F32 0x0000004b -#define SQ_V_CMP_NLE_F32 0x0000004c -#define SQ_V_CMP_NEQ_F32 0x0000004d -#define SQ_V_CMP_NLT_F32 0x0000004e -#define SQ_V_CMP_TRU_F32 0x0000004f -#define SQ_V_CMPX_F_F32 0x00000050 -#define SQ_V_CMPX_LT_F32 0x00000051 -#define SQ_V_CMPX_EQ_F32 0x00000052 -#define SQ_V_CMPX_LE_F32 0x00000053 -#define SQ_V_CMPX_GT_F32 0x00000054 -#define SQ_V_CMPX_LG_F32 0x00000055 -#define SQ_V_CMPX_GE_F32 0x00000056 -#define SQ_V_CMPX_O_F32 0x00000057 -#define SQ_V_CMPX_U_F32 0x00000058 -#define SQ_V_CMPX_NGE_F32 0x00000059 -#define SQ_V_CMPX_NLG_F32 0x0000005a -#define SQ_V_CMPX_NGT_F32 0x0000005b -#define SQ_V_CMPX_NLE_F32 0x0000005c -#define SQ_V_CMPX_NEQ_F32 0x0000005d -#define SQ_V_CMPX_NLT_F32 0x0000005e -#define SQ_V_CMPX_TRU_F32 0x0000005f -#define SQ_V_CMP_F_F64 0x00000060 -#define SQ_V_CMP_LT_F64 0x00000061 -#define SQ_V_CMP_EQ_F64 0x00000062 -#define SQ_V_CMP_LE_F64 0x00000063 -#define SQ_V_CMP_GT_F64 0x00000064 -#define SQ_V_CMP_LG_F64 0x00000065 -#define SQ_V_CMP_GE_F64 0x00000066 -#define SQ_V_CMP_O_F64 0x00000067 -#define SQ_V_CMP_U_F64 0x00000068 -#define SQ_V_CMP_NGE_F64 0x00000069 -#define SQ_V_CMP_NLG_F64 0x0000006a -#define SQ_V_CMP_NGT_F64 0x0000006b -#define SQ_V_CMP_NLE_F64 0x0000006c -#define SQ_V_CMP_NEQ_F64 0x0000006d -#define SQ_V_CMP_NLT_F64 0x0000006e -#define SQ_V_CMP_TRU_F64 0x0000006f -#define SQ_V_CMPX_F_F64 0x00000070 -#define SQ_V_CMPX_LT_F64 0x00000071 -#define SQ_V_CMPX_EQ_F64 0x00000072 -#define SQ_V_CMPX_LE_F64 0x00000073 -#define SQ_V_CMPX_GT_F64 0x00000074 -#define SQ_V_CMPX_LG_F64 0x00000075 -#define SQ_V_CMPX_GE_F64 0x00000076 -#define SQ_V_CMPX_O_F64 0x00000077 -#define SQ_V_CMPX_U_F64 0x00000078 -#define SQ_V_CMPX_NGE_F64 0x00000079 -#define SQ_V_CMPX_NLG_F64 0x0000007a -#define SQ_V_CMPX_NGT_F64 0x0000007b -#define SQ_V_CMPX_NLE_F64 0x0000007c -#define SQ_V_CMPX_NEQ_F64 0x0000007d -#define SQ_V_CMPX_NLT_F64 0x0000007e -#define SQ_V_CMPX_TRU_F64 0x0000007f -#define SQ_V_CMP_F_I16 0x000000a0 -#define SQ_V_CMP_LT_I16 0x000000a1 -#define SQ_V_CMP_EQ_I16 0x000000a2 -#define SQ_V_CMP_LE_I16 0x000000a3 -#define SQ_V_CMP_GT_I16 0x000000a4 -#define SQ_V_CMP_NE_I16 0x000000a5 -#define SQ_V_CMP_GE_I16 0x000000a6 -#define SQ_V_CMP_T_I16 0x000000a7 -#define SQ_V_CMP_F_U16 0x000000a8 -#define SQ_V_CMP_LT_U16 0x000000a9 -#define SQ_V_CMP_EQ_U16 0x000000aa -#define SQ_V_CMP_LE_U16 0x000000ab -#define SQ_V_CMP_GT_U16 0x000000ac -#define SQ_V_CMP_NE_U16 0x000000ad -#define SQ_V_CMP_GE_U16 0x000000ae -#define SQ_V_CMP_T_U16 0x000000af -#define SQ_V_CMPX_F_I16 0x000000b0 -#define SQ_V_CMPX_LT_I16 0x000000b1 -#define SQ_V_CMPX_EQ_I16 0x000000b2 -#define SQ_V_CMPX_LE_I16 0x000000b3 -#define SQ_V_CMPX_GT_I16 0x000000b4 -#define SQ_V_CMPX_NE_I16 0x000000b5 -#define SQ_V_CMPX_GE_I16 0x000000b6 -#define SQ_V_CMPX_T_I16 0x000000b7 -#define SQ_V_CMPX_F_U16 0x000000b8 -#define SQ_V_CMPX_LT_U16 0x000000b9 -#define SQ_V_CMPX_EQ_U16 0x000000ba -#define SQ_V_CMPX_LE_U16 0x000000bb -#define SQ_V_CMPX_GT_U16 0x000000bc -#define SQ_V_CMPX_NE_U16 0x000000bd -#define SQ_V_CMPX_GE_U16 0x000000be -#define SQ_V_CMPX_T_U16 0x000000bf -#define SQ_V_CMP_F_I32 0x000000c0 -#define SQ_V_CMP_LT_I32 0x000000c1 -#define SQ_V_CMP_EQ_I32 0x000000c2 -#define SQ_V_CMP_LE_I32 0x000000c3 -#define SQ_V_CMP_GT_I32 0x000000c4 -#define SQ_V_CMP_NE_I32 0x000000c5 -#define SQ_V_CMP_GE_I32 0x000000c6 -#define SQ_V_CMP_T_I32 0x000000c7 -#define SQ_V_CMP_F_U32 0x000000c8 -#define SQ_V_CMP_LT_U32 0x000000c9 -#define SQ_V_CMP_EQ_U32 0x000000ca -#define SQ_V_CMP_LE_U32 0x000000cb -#define SQ_V_CMP_GT_U32 0x000000cc -#define SQ_V_CMP_NE_U32 0x000000cd -#define SQ_V_CMP_GE_U32 0x000000ce -#define SQ_V_CMP_T_U32 0x000000cf -#define SQ_V_CMPX_F_I32 0x000000d0 -#define SQ_V_CMPX_LT_I32 0x000000d1 -#define SQ_V_CMPX_EQ_I32 0x000000d2 -#define SQ_V_CMPX_LE_I32 0x000000d3 -#define SQ_V_CMPX_GT_I32 0x000000d4 -#define SQ_V_CMPX_NE_I32 0x000000d5 -#define SQ_V_CMPX_GE_I32 0x000000d6 -#define SQ_V_CMPX_T_I32 0x000000d7 -#define SQ_V_CMPX_F_U32 0x000000d8 -#define SQ_V_CMPX_LT_U32 0x000000d9 -#define SQ_V_CMPX_EQ_U32 0x000000da -#define SQ_V_CMPX_LE_U32 0x000000db -#define SQ_V_CMPX_GT_U32 0x000000dc -#define SQ_V_CMPX_NE_U32 0x000000dd -#define SQ_V_CMPX_GE_U32 0x000000de -#define SQ_V_CMPX_T_U32 0x000000df -#define SQ_V_CMP_F_I64 0x000000e0 -#define SQ_V_CMP_LT_I64 0x000000e1 -#define SQ_V_CMP_EQ_I64 0x000000e2 -#define SQ_V_CMP_LE_I64 0x000000e3 -#define SQ_V_CMP_GT_I64 0x000000e4 -#define SQ_V_CMP_NE_I64 0x000000e5 -#define SQ_V_CMP_GE_I64 0x000000e6 -#define SQ_V_CMP_T_I64 0x000000e7 -#define SQ_V_CMP_F_U64 0x000000e8 -#define SQ_V_CMP_LT_U64 0x000000e9 -#define SQ_V_CMP_EQ_U64 0x000000ea -#define SQ_V_CMP_LE_U64 0x000000eb -#define SQ_V_CMP_GT_U64 0x000000ec -#define SQ_V_CMP_NE_U64 0x000000ed -#define SQ_V_CMP_GE_U64 0x000000ee -#define SQ_V_CMP_T_U64 0x000000ef -#define SQ_V_CMPX_F_I64 0x000000f0 -#define SQ_V_CMPX_LT_I64 0x000000f1 -#define SQ_V_CMPX_EQ_I64 0x000000f2 -#define SQ_V_CMPX_LE_I64 0x000000f3 -#define SQ_V_CMPX_GT_I64 0x000000f4 -#define SQ_V_CMPX_NE_I64 0x000000f5 -#define SQ_V_CMPX_GE_I64 0x000000f6 -#define SQ_V_CMPX_T_I64 0x000000f7 -#define SQ_V_CMPX_F_U64 0x000000f8 -#define SQ_V_CMPX_LT_U64 0x000000f9 -#define SQ_V_CMPX_EQ_U64 0x000000fa -#define SQ_V_CMPX_LE_U64 0x000000fb -#define SQ_V_CMPX_GT_U64 0x000000fc -#define SQ_V_CMPX_NE_U64 0x000000fd -#define SQ_V_CMPX_GE_U64 0x000000fe -#define SQ_V_CMPX_T_U64 0x000000ff - -/* - * VALUE_SQ_COMPI value - */ - -#define SQ_F 0x00000000 -#define SQ_LT 0x00000001 -#define SQ_EQ 0x00000002 -#define SQ_LE 0x00000003 -#define SQ_GT 0x00000004 -#define SQ_NE 0x00000005 -#define SQ_GE 0x00000006 -#define SQ_T 0x00000007 - -/* - * VALUE_SQ_OP_MUBUF value - */ - -#define SQ_BUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_BUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_BUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x00000008 -#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x00000009 -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b -#define SQ_BUFFER_STORE_FORMAT_D16_X 0x0000000c -#define SQ_BUFFER_STORE_FORMAT_D16_XY 0x0000000d -#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e -#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f -#define SQ_BUFFER_LOAD_UBYTE 0x00000010 -#define SQ_BUFFER_LOAD_SBYTE 0x00000011 -#define SQ_BUFFER_LOAD_USHORT 0x00000012 -#define SQ_BUFFER_LOAD_SSHORT 0x00000013 -#define SQ_BUFFER_LOAD_DWORD 0x00000014 -#define SQ_BUFFER_LOAD_DWORDX2 0x00000015 -#define SQ_BUFFER_LOAD_DWORDX3 0x00000016 -#define SQ_BUFFER_LOAD_DWORDX4 0x00000017 -#define SQ_BUFFER_STORE_BYTE 0x00000018 -#define SQ_BUFFER_STORE_BYTE_D16_HI 0x00000019 -#define SQ_BUFFER_STORE_SHORT 0x0000001a -#define SQ_BUFFER_STORE_SHORT_D16_HI 0x0000001b -#define SQ_BUFFER_STORE_DWORD 0x0000001c -#define SQ_BUFFER_STORE_DWORDX2 0x0000001d -#define SQ_BUFFER_STORE_DWORDX3 0x0000001e -#define SQ_BUFFER_STORE_DWORDX4 0x0000001f -#define SQ_BUFFER_LOAD_UBYTE_D16 0x00000020 -#define SQ_BUFFER_LOAD_UBYTE_D16_HI 0x00000021 -#define SQ_BUFFER_LOAD_SBYTE_D16 0x00000022 -#define SQ_BUFFER_LOAD_SBYTE_D16_HI 0x00000023 -#define SQ_BUFFER_LOAD_SHORT_D16 0x00000024 -#define SQ_BUFFER_LOAD_SHORT_D16_HI 0x00000025 -#define SQ_BUFFER_LOAD_FORMAT_D16_HI_X 0x00000026 -#define SQ_BUFFER_STORE_FORMAT_D16_HI_X 0x00000027 -#define SQ_BUFFER_STORE_LDS_DWORD 0x0000003d -#define SQ_BUFFER_WBINVL1 0x0000003e -#define SQ_BUFFER_WBINVL1_VOL 0x0000003f -#define SQ_BUFFER_ATOMIC_SWAP 0x00000040 -#define SQ_BUFFER_ATOMIC_CMPSWAP 0x00000041 -#define SQ_BUFFER_ATOMIC_ADD 0x00000042 -#define SQ_BUFFER_ATOMIC_SUB 0x00000043 -#define SQ_BUFFER_ATOMIC_SMIN 0x00000044 -#define SQ_BUFFER_ATOMIC_UMIN 0x00000045 -#define SQ_BUFFER_ATOMIC_SMAX 0x00000046 -#define SQ_BUFFER_ATOMIC_UMAX 0x00000047 -#define SQ_BUFFER_ATOMIC_AND 0x00000048 -#define SQ_BUFFER_ATOMIC_OR 0x00000049 -#define SQ_BUFFER_ATOMIC_XOR 0x0000004a -#define SQ_BUFFER_ATOMIC_INC 0x0000004b -#define SQ_BUFFER_ATOMIC_DEC 0x0000004c -#define SQ_BUFFER_ATOMIC_SWAP_X2 0x00000060 -#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061 -#define SQ_BUFFER_ATOMIC_ADD_X2 0x00000062 -#define SQ_BUFFER_ATOMIC_SUB_X2 0x00000063 -#define SQ_BUFFER_ATOMIC_SMIN_X2 0x00000064 -#define SQ_BUFFER_ATOMIC_UMIN_X2 0x00000065 -#define SQ_BUFFER_ATOMIC_SMAX_X2 0x00000066 -#define SQ_BUFFER_ATOMIC_UMAX_X2 0x00000067 -#define SQ_BUFFER_ATOMIC_AND_X2 0x00000068 -#define SQ_BUFFER_ATOMIC_OR_X2 0x00000069 -#define SQ_BUFFER_ATOMIC_XOR_X2 0x0000006a -#define SQ_BUFFER_ATOMIC_INC_X2 0x0000006b -#define SQ_BUFFER_ATOMIC_DEC_X2 0x0000006c - -/* - * VALUE_SQ_DPP_CTRL_L_1_15 value - */ - -#define SQ_L1 0x00000001 -#define SQ_L2 0x00000002 -#define SQ_L3 0x00000003 -#define SQ_L4 0x00000004 -#define SQ_L5 0x00000005 -#define SQ_L6 0x00000006 -#define SQ_L7 0x00000007 -#define SQ_L8 0x00000008 -#define SQ_L9 0x00000009 -#define SQ_L10 0x0000000a -#define SQ_L11 0x0000000b -#define SQ_L12 0x0000000c -#define SQ_L13 0x0000000d -#define SQ_L14 0x0000000e -#define SQ_L15 0x0000000f - -/* - * VALUE_SQ_SDWA_SEL value - */ - -#define SQ_SDWA_BYTE_0 0x00000000 -#define SQ_SDWA_BYTE_1 0x00000001 -#define SQ_SDWA_BYTE_2 0x00000002 -#define SQ_SDWA_BYTE_3 0x00000003 -#define SQ_SDWA_WORD_0 0x00000004 -#define SQ_SDWA_WORD_1 0x00000005 -#define SQ_SDWA_DWORD 0x00000006 - -/* - * VALUE_SQ_OP_SOP1 value - */ - -#define SQ_S_MOV_B32 0x00000000 -#define SQ_S_MOV_B64 0x00000001 -#define SQ_S_CMOV_B32 0x00000002 -#define SQ_S_CMOV_B64 0x00000003 -#define SQ_S_NOT_B32 0x00000004 -#define SQ_S_NOT_B64 0x00000005 -#define SQ_S_WQM_B32 0x00000006 -#define SQ_S_WQM_B64 0x00000007 -#define SQ_S_BREV_B32 0x00000008 -#define SQ_S_BREV_B64 0x00000009 -#define SQ_S_BCNT0_I32_B32 0x0000000a -#define SQ_S_BCNT0_I32_B64 0x0000000b -#define SQ_S_BCNT1_I32_B32 0x0000000c -#define SQ_S_BCNT1_I32_B64 0x0000000d -#define SQ_S_FF0_I32_B32 0x0000000e -#define SQ_S_FF0_I32_B64 0x0000000f -#define SQ_S_FF1_I32_B32 0x00000010 -#define SQ_S_FF1_I32_B64 0x00000011 -#define SQ_S_FLBIT_I32_B32 0x00000012 -#define SQ_S_FLBIT_I32_B64 0x00000013 -#define SQ_S_FLBIT_I32 0x00000014 -#define SQ_S_FLBIT_I32_I64 0x00000015 -#define SQ_S_SEXT_I32_I8 0x00000016 -#define SQ_S_SEXT_I32_I16 0x00000017 -#define SQ_S_BITSET0_B32 0x00000018 -#define SQ_S_BITSET0_B64 0x00000019 -#define SQ_S_BITSET1_B32 0x0000001a -#define SQ_S_BITSET1_B64 0x0000001b -#define SQ_S_GETPC_B64 0x0000001c -#define SQ_S_SETPC_B64 0x0000001d -#define SQ_S_SWAPPC_B64 0x0000001e -#define SQ_S_RFE_B64 0x0000001f -#define SQ_S_AND_SAVEEXEC_B64 0x00000020 -#define SQ_S_OR_SAVEEXEC_B64 0x00000021 -#define SQ_S_XOR_SAVEEXEC_B64 0x00000022 -#define SQ_S_ANDN2_SAVEEXEC_B64 0x00000023 -#define SQ_S_ORN2_SAVEEXEC_B64 0x00000024 -#define SQ_S_NAND_SAVEEXEC_B64 0x00000025 -#define SQ_S_NOR_SAVEEXEC_B64 0x00000026 -#define SQ_S_XNOR_SAVEEXEC_B64 0x00000027 -#define SQ_S_QUADMASK_B32 0x00000028 -#define SQ_S_QUADMASK_B64 0x00000029 -#define SQ_S_MOVRELS_B32 0x0000002a -#define SQ_S_MOVRELS_B64 0x0000002b -#define SQ_S_MOVRELD_B32 0x0000002c -#define SQ_S_MOVRELD_B64 0x0000002d -#define SQ_S_CBRANCH_JOIN 0x0000002e -#define SQ_S_MOV_REGRD_B32 0x0000002f -#define SQ_S_ABS_I32 0x00000030 -#define SQ_S_MOV_FED_B32 0x00000031 -#define SQ_S_SET_GPR_IDX_IDX 0x00000032 -#define SQ_S_ANDN1_SAVEEXEC_B64 0x00000033 -#define SQ_S_ORN1_SAVEEXEC_B64 0x00000034 -#define SQ_S_ANDN1_WREXEC_B64 0x00000035 -#define SQ_S_ANDN2_WREXEC_B64 0x00000036 -#define SQ_S_BITREPLICATE_B64_B32 0x00000037 - -/* - * VALUE_SQ_SSRC_SPECIAL_SCC value - */ - -#define SQ_SRC_SCC 0x000000fd - -/* - * VALUE_SQ_VCC_LOHI value - */ - -#define SQ_VCC_LO 0x0000006a -#define SQ_VCC_HI 0x0000006b - -/* - * VALUE_SQ_OP_VOP3 value - */ - -#define SQ_V_MAD_LEGACY_F32 0x000001c0 -#define SQ_V_MAD_F32 0x000001c1 -#define SQ_V_MAD_I32_I24 0x000001c2 -#define SQ_V_MAD_U32_U24 0x000001c3 -#define SQ_V_CUBEID_F32 0x000001c4 -#define SQ_V_CUBESC_F32 0x000001c5 -#define SQ_V_CUBETC_F32 0x000001c6 -#define SQ_V_CUBEMA_F32 0x000001c7 -#define SQ_V_BFE_U32 0x000001c8 -#define SQ_V_BFE_I32 0x000001c9 -#define SQ_V_BFI_B32 0x000001ca -#define SQ_V_FMA_F32 0x000001cb -#define SQ_V_FMA_F64 0x000001cc -#define SQ_V_LERP_U8 0x000001cd -#define SQ_V_ALIGNBIT_B32 0x000001ce -#define SQ_V_ALIGNBYTE_B32 0x000001cf -#define SQ_V_MIN3_F32 0x000001d0 -#define SQ_V_MIN3_I32 0x000001d1 -#define SQ_V_MIN3_U32 0x000001d2 -#define SQ_V_MAX3_F32 0x000001d3 -#define SQ_V_MAX3_I32 0x000001d4 -#define SQ_V_MAX3_U32 0x000001d5 -#define SQ_V_MED3_F32 0x000001d6 -#define SQ_V_MED3_I32 0x000001d7 -#define SQ_V_MED3_U32 0x000001d8 -#define SQ_V_SAD_U8 0x000001d9 -#define SQ_V_SAD_HI_U8 0x000001da -#define SQ_V_SAD_U16 0x000001db -#define SQ_V_SAD_U32 0x000001dc -#define SQ_V_CVT_PK_U8_F32 0x000001dd -#define SQ_V_DIV_FIXUP_F32 0x000001de -#define SQ_V_DIV_FIXUP_F64 0x000001df -#define SQ_V_DIV_SCALE_F32 0x000001e0 -#define SQ_V_DIV_SCALE_F64 0x000001e1 -#define SQ_V_DIV_FMAS_F32 0x000001e2 -#define SQ_V_DIV_FMAS_F64 0x000001e3 -#define SQ_V_MSAD_U8 0x000001e4 -#define SQ_V_QSAD_PK_U16_U8 0x000001e5 -#define SQ_V_MQSAD_PK_U16_U8 0x000001e6 -#define SQ_V_MQSAD_U32_U8 0x000001e7 -#define SQ_V_MAD_U64_U32 0x000001e8 -#define SQ_V_MAD_I64_I32 0x000001e9 -#define SQ_V_MAD_LEGACY_F16 0x000001ea -#define SQ_V_MAD_LEGACY_U16 0x000001eb -#define SQ_V_MAD_LEGACY_I16 0x000001ec -#define SQ_V_PERM_B32 0x000001ed -#define SQ_V_FMA_LEGACY_F16 0x000001ee -#define SQ_V_DIV_FIXUP_LEGACY_F16 0x000001ef -#define SQ_V_CVT_PKACCUM_U8_F32 0x000001f0 -#define SQ_V_MAD_U32_U16 0x000001f1 -#define SQ_V_MAD_I32_I16 0x000001f2 -#define SQ_V_XAD_U32 0x000001f3 -#define SQ_V_MIN3_F16 0x000001f4 -#define SQ_V_MIN3_I16 0x000001f5 -#define SQ_V_MIN3_U16 0x000001f6 -#define SQ_V_MAX3_F16 0x000001f7 -#define SQ_V_MAX3_I16 0x000001f8 -#define SQ_V_MAX3_U16 0x000001f9 -#define SQ_V_MED3_F16 0x000001fa -#define SQ_V_MED3_I16 0x000001fb -#define SQ_V_MED3_U16 0x000001fc -#define SQ_V_LSHL_ADD_U32 0x000001fd -#define SQ_V_ADD_LSHL_U32 0x000001fe -#define SQ_V_ADD3_U32 0x000001ff -#define SQ_V_LSHL_OR_B32 0x00000200 -#define SQ_V_AND_OR_B32 0x00000201 -#define SQ_V_OR3_B32 0x00000202 -#define SQ_V_MAD_F16 0x00000203 -#define SQ_V_MAD_U16 0x00000204 -#define SQ_V_MAD_I16 0x00000205 -#define SQ_V_FMA_F16 0x00000206 -#define SQ_V_DIV_FIXUP_F16 0x00000207 -#define SQ_V_INTERP_P1LL_F16 0x00000274 -#define SQ_V_INTERP_P1LV_F16 0x00000275 -#define SQ_V_INTERP_P2_LEGACY_F16 0x00000276 -#define SQ_V_INTERP_P2_F16 0x00000277 -#define SQ_V_ADD_F64 0x00000280 -#define SQ_V_MUL_F64 0x00000281 -#define SQ_V_MIN_F64 0x00000282 -#define SQ_V_MAX_F64 0x00000283 -#define SQ_V_LDEXP_F64 0x00000284 -#define SQ_V_MUL_LO_U32 0x00000285 -#define SQ_V_MUL_HI_U32 0x00000286 -#define SQ_V_MUL_HI_I32 0x00000287 -#define SQ_V_LDEXP_F32 0x00000288 -#define SQ_V_READLANE_B32 0x00000289 -#define SQ_V_WRITELANE_B32 0x0000028a -#define SQ_V_BCNT_U32_B32 0x0000028b -#define SQ_V_MBCNT_LO_U32_B32 0x0000028c -#define SQ_V_MBCNT_HI_U32_B32 0x0000028d -#define SQ_V_MAC_LEGACY_F32 0x0000028e -#define SQ_V_LSHLREV_B64 0x0000028f -#define SQ_V_LSHRREV_B64 0x00000290 -#define SQ_V_ASHRREV_I64 0x00000291 -#define SQ_V_TRIG_PREOP_F64 0x00000292 -#define SQ_V_BFM_B32 0x00000293 -#define SQ_V_CVT_PKNORM_I16_F32 0x00000294 -#define SQ_V_CVT_PKNORM_U16_F32 0x00000295 -#define SQ_V_CVT_PKRTZ_F16_F32 0x00000296 -#define SQ_V_CVT_PK_U16_U32 0x00000297 -#define SQ_V_CVT_PK_I16_I32 0x00000298 -#define SQ_V_CVT_PKNORM_I16_F16 0x00000299 -#define SQ_V_CVT_PKNORM_U16_F16 0x0000029a -#define SQ_V_READLANE_REGRD_B32 0x0000029b -#define SQ_V_ADD_I32 0x0000029c -#define SQ_V_SUB_I32 0x0000029d -#define SQ_V_ADD_I16 0x0000029e -#define SQ_V_SUB_I16 0x0000029f -#define SQ_V_PACK_B32_F16 0x000002a0 - -/* - * VALUE_SQ_CHAN value - */ - -#define SQ_CHAN_X 0x00000000 -#define SQ_CHAN_Y 0x00000001 -#define SQ_CHAN_Z 0x00000002 -#define SQ_CHAN_W 0x00000003 - -/* - * VALUE_SQ_COMPF value - */ - -#define SQ_F 0x00000000 -#define SQ_LT 0x00000001 -#define SQ_EQ 0x00000002 -#define SQ_LE 0x00000003 -#define SQ_GT 0x00000004 -#define SQ_LG 0x00000005 -#define SQ_GE 0x00000006 -#define SQ_O 0x00000007 -#define SQ_U 0x00000008 -#define SQ_NGE 0x00000009 -#define SQ_NLG 0x0000000a -#define SQ_NGT 0x0000000b -#define SQ_NLE 0x0000000c -#define SQ_NEQ 0x0000000d -#define SQ_NLT 0x0000000e -#define SQ_TRU 0x0000000f - -/* - * VALUE_SQ_TGT value - */ - -#define SQ_EXP_MRT0 0x00000000 -#define SQ_EXP_MRTZ 0x00000008 -#define SQ_EXP_NULL 0x00000009 -#define SQ_EXP_POS0 0x0000000c -#define SQ_EXP_PARAM0 0x00000020 - -/* - * VALUE_SQ_SSRC_SPECIAL_LDS value - */ - -#define SQ_SRC_LDS_DIRECT 0x000000fe - -/* - * VALUE_SQ_HW_REG value - */ - -#define SQ_HW_REG_MODE 0x00000001 -#define SQ_HW_REG_STATUS 0x00000002 -#define SQ_HW_REG_TRAPSTS 0x00000003 -#define SQ_HW_REG_HW_ID 0x00000004 -#define SQ_HW_REG_GPR_ALLOC 0x00000005 -#define SQ_HW_REG_LDS_ALLOC 0x00000006 -#define SQ_HW_REG_IB_STS 0x00000007 -#define SQ_HW_REG_PC_LO 0x00000008 -#define SQ_HW_REG_PC_HI 0x00000009 -#define SQ_HW_REG_INST_DW0 0x0000000a -#define SQ_HW_REG_INST_DW1 0x0000000b -#define SQ_HW_REG_IB_DBG0 0x0000000c -#define SQ_HW_REG_IB_DBG1 0x0000000d -#define SQ_HW_REG_FLUSH_IB 0x0000000e -#define SQ_HW_REG_SH_MEM_BASES 0x0000000f -#define SQ_HW_REG_SQ_SHADER_TBA_LO 0x00000010 -#define SQ_HW_REG_SQ_SHADER_TBA_HI 0x00000011 -#define SQ_HW_REG_SQ_SHADER_TMA_LO 0x00000012 -#define SQ_HW_REG_SQ_SHADER_TMA_HI 0x00000013 - -/* - * VALUE_SQ_OP_FLAT_GLBL value - */ - -#define SQ_GLOBAL_LOAD_UBYTE 0x00000010 -#define SQ_GLOBAL_LOAD_SBYTE 0x00000011 -#define SQ_GLOBAL_LOAD_USHORT 0x00000012 -#define SQ_GLOBAL_LOAD_SSHORT 0x00000013 -#define SQ_GLOBAL_LOAD_DWORD 0x00000014 -#define SQ_GLOBAL_LOAD_DWORDX2 0x00000015 -#define SQ_GLOBAL_LOAD_DWORDX3 0x00000016 -#define SQ_GLOBAL_LOAD_DWORDX4 0x00000017 -#define SQ_GLOBAL_STORE_BYTE 0x00000018 -#define SQ_GLOBAL_STORE_BYTE_D16_HI 0x00000019 -#define SQ_GLOBAL_STORE_SHORT 0x0000001a -#define SQ_GLOBAL_STORE_SHORT_D16_HI 0x0000001b -#define SQ_GLOBAL_STORE_DWORD 0x0000001c -#define SQ_GLOBAL_STORE_DWORDX2 0x0000001d -#define SQ_GLOBAL_STORE_DWORDX3 0x0000001e -#define SQ_GLOBAL_STORE_DWORDX4 0x0000001f -#define SQ_GLOBAL_LOAD_UBYTE_D16 0x00000020 -#define SQ_GLOBAL_LOAD_UBYTE_D16_HI 0x00000021 -#define SQ_GLOBAL_LOAD_SBYTE_D16 0x00000022 -#define SQ_GLOBAL_LOAD_SBYTE_D16_HI 0x00000023 -#define SQ_GLOBAL_LOAD_SHORT_D16 0x00000024 -#define SQ_GLOBAL_LOAD_SHORT_D16_HI 0x00000025 -#define SQ_GLOBAL_ATOMIC_SWAP 0x00000040 -#define SQ_GLOBAL_ATOMIC_CMPSWAP 0x00000041 -#define SQ_GLOBAL_ATOMIC_ADD 0x00000042 -#define SQ_GLOBAL_ATOMIC_SUB 0x00000043 -#define SQ_GLOBAL_ATOMIC_SMIN 0x00000044 -#define SQ_GLOBAL_ATOMIC_UMIN 0x00000045 -#define SQ_GLOBAL_ATOMIC_SMAX 0x00000046 -#define SQ_GLOBAL_ATOMIC_UMAX 0x00000047 -#define SQ_GLOBAL_ATOMIC_AND 0x00000048 -#define SQ_GLOBAL_ATOMIC_OR 0x00000049 -#define SQ_GLOBAL_ATOMIC_XOR 0x0000004a -#define SQ_GLOBAL_ATOMIC_INC 0x0000004b -#define SQ_GLOBAL_ATOMIC_DEC 0x0000004c -#define SQ_GLOBAL_ATOMIC_SWAP_X2 0x00000060 -#define SQ_GLOBAL_ATOMIC_CMPSWAP_X2 0x00000061 -#define SQ_GLOBAL_ATOMIC_ADD_X2 0x00000062 -#define SQ_GLOBAL_ATOMIC_SUB_X2 0x00000063 -#define SQ_GLOBAL_ATOMIC_SMIN_X2 0x00000064 -#define SQ_GLOBAL_ATOMIC_UMIN_X2 0x00000065 -#define SQ_GLOBAL_ATOMIC_SMAX_X2 0x00000066 -#define SQ_GLOBAL_ATOMIC_UMAX_X2 0x00000067 -#define SQ_GLOBAL_ATOMIC_AND_X2 0x00000068 -#define SQ_GLOBAL_ATOMIC_OR_X2 0x00000069 -#define SQ_GLOBAL_ATOMIC_XOR_X2 0x0000006a -#define SQ_GLOBAL_ATOMIC_INC_X2 0x0000006b -#define SQ_GLOBAL_ATOMIC_DEC_X2 0x0000006c - -/* - * VALUE_SQ_OP_FLAT_SCRATCH value - */ - -#define SQ_SCRATCH_LOAD_UBYTE 0x00000010 -#define SQ_SCRATCH_LOAD_SBYTE 0x00000011 -#define SQ_SCRATCH_LOAD_USHORT 0x00000012 -#define SQ_SCRATCH_LOAD_SSHORT 0x00000013 -#define SQ_SCRATCH_LOAD_DWORD 0x00000014 -#define SQ_SCRATCH_LOAD_DWORDX2 0x00000015 -#define SQ_SCRATCH_LOAD_DWORDX3 0x00000016 -#define SQ_SCRATCH_LOAD_DWORDX4 0x00000017 -#define SQ_SCRATCH_STORE_BYTE 0x00000018 -#define SQ_SCRATCH_STORE_BYTE_D16_HI 0x00000019 -#define SQ_SCRATCH_STORE_SHORT 0x0000001a -#define SQ_SCRATCH_STORE_SHORT_D16_HI 0x0000001b -#define SQ_SCRATCH_STORE_DWORD 0x0000001c -#define SQ_SCRATCH_STORE_DWORDX2 0x0000001d -#define SQ_SCRATCH_STORE_DWORDX3 0x0000001e -#define SQ_SCRATCH_STORE_DWORDX4 0x0000001f -#define SQ_SCRATCH_LOAD_UBYTE_D16 0x00000020 -#define SQ_SCRATCH_LOAD_UBYTE_D16_HI 0x00000021 -#define SQ_SCRATCH_LOAD_SBYTE_D16 0x00000022 -#define SQ_SCRATCH_LOAD_SBYTE_D16_HI 0x00000023 -#define SQ_SCRATCH_LOAD_SHORT_D16 0x00000024 -#define SQ_SCRATCH_LOAD_SHORT_D16_HI 0x00000025 - -/* - * VALUE_SQ_OP_SMEM value - */ - -#define SQ_S_LOAD_DWORD 0x00000000 -#define SQ_S_LOAD_DWORDX2 0x00000001 -#define SQ_S_LOAD_DWORDX4 0x00000002 -#define SQ_S_LOAD_DWORDX8 0x00000003 -#define SQ_S_LOAD_DWORDX16 0x00000004 -#define SQ_S_SCRATCH_LOAD_DWORD 0x00000005 -#define SQ_S_SCRATCH_LOAD_DWORDX2 0x00000006 -#define SQ_S_SCRATCH_LOAD_DWORDX4 0x00000007 -#define SQ_S_BUFFER_LOAD_DWORD 0x00000008 -#define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009 -#define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a -#define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b -#define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c -#define SQ_S_STORE_DWORD 0x00000010 -#define SQ_S_STORE_DWORDX2 0x00000011 -#define SQ_S_STORE_DWORDX4 0x00000012 -#define SQ_S_SCRATCH_STORE_DWORD 0x00000015 -#define SQ_S_SCRATCH_STORE_DWORDX2 0x00000016 -#define SQ_S_SCRATCH_STORE_DWORDX4 0x00000017 -#define SQ_S_BUFFER_STORE_DWORD 0x00000018 -#define SQ_S_BUFFER_STORE_DWORDX2 0x00000019 -#define SQ_S_BUFFER_STORE_DWORDX4 0x0000001a -#define SQ_S_DCACHE_INV 0x00000020 -#define SQ_S_DCACHE_WB 0x00000021 -#define SQ_S_DCACHE_INV_VOL 0x00000022 -#define SQ_S_DCACHE_WB_VOL 0x00000023 -#define SQ_S_MEMTIME 0x00000024 -#define SQ_S_MEMREALTIME 0x00000025 -#define SQ_S_ATC_PROBE 0x00000026 -#define SQ_S_ATC_PROBE_BUFFER 0x00000027 -#define SQ_S_DCACHE_DISCARD 0x00000028 -#define SQ_S_DCACHE_DISCARD_X2 0x00000029 -#define SQ_S_BUFFER_ATOMIC_SWAP 0x00000040 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x00000041 -#define SQ_S_BUFFER_ATOMIC_ADD 0x00000042 -#define SQ_S_BUFFER_ATOMIC_SUB 0x00000043 -#define SQ_S_BUFFER_ATOMIC_SMIN 0x00000044 -#define SQ_S_BUFFER_ATOMIC_UMIN 0x00000045 -#define SQ_S_BUFFER_ATOMIC_SMAX 0x00000046 -#define SQ_S_BUFFER_ATOMIC_UMAX 0x00000047 -#define SQ_S_BUFFER_ATOMIC_AND 0x00000048 -#define SQ_S_BUFFER_ATOMIC_OR 0x00000049 -#define SQ_S_BUFFER_ATOMIC_XOR 0x0000004a -#define SQ_S_BUFFER_ATOMIC_INC 0x0000004b -#define SQ_S_BUFFER_ATOMIC_DEC 0x0000004c -#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x00000060 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061 -#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x00000062 -#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x00000063 -#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x00000064 -#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x00000065 -#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x00000066 -#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x00000067 -#define SQ_S_BUFFER_ATOMIC_AND_X2 0x00000068 -#define SQ_S_BUFFER_ATOMIC_OR_X2 0x00000069 -#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x0000006a -#define SQ_S_BUFFER_ATOMIC_INC_X2 0x0000006b -#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x0000006c -#define SQ_S_ATOMIC_SWAP 0x00000080 -#define SQ_S_ATOMIC_CMPSWAP 0x00000081 -#define SQ_S_ATOMIC_ADD 0x00000082 -#define SQ_S_ATOMIC_SUB 0x00000083 -#define SQ_S_ATOMIC_SMIN 0x00000084 -#define SQ_S_ATOMIC_UMIN 0x00000085 -#define SQ_S_ATOMIC_SMAX 0x00000086 -#define SQ_S_ATOMIC_UMAX 0x00000087 -#define SQ_S_ATOMIC_AND 0x00000088 -#define SQ_S_ATOMIC_OR 0x00000089 -#define SQ_S_ATOMIC_XOR 0x0000008a -#define SQ_S_ATOMIC_INC 0x0000008b -#define SQ_S_ATOMIC_DEC 0x0000008c -#define SQ_S_ATOMIC_SWAP_X2 0x000000a0 -#define SQ_S_ATOMIC_CMPSWAP_X2 0x000000a1 -#define SQ_S_ATOMIC_ADD_X2 0x000000a2 -#define SQ_S_ATOMIC_SUB_X2 0x000000a3 -#define SQ_S_ATOMIC_SMIN_X2 0x000000a4 -#define SQ_S_ATOMIC_UMIN_X2 0x000000a5 -#define SQ_S_ATOMIC_SMAX_X2 0x000000a6 -#define SQ_S_ATOMIC_UMAX_X2 0x000000a7 -#define SQ_S_ATOMIC_AND_X2 0x000000a8 -#define SQ_S_ATOMIC_OR_X2 0x000000a9 -#define SQ_S_ATOMIC_XOR_X2 0x000000aa -#define SQ_S_ATOMIC_INC_X2 0x000000ab -#define SQ_S_ATOMIC_DEC_X2 0x000000ac - -/* - * VALUE_SQ_OP_MIMG value - */ - -#define SQ_IMAGE_LOAD 0x00000000 -#define SQ_IMAGE_LOAD_MIP 0x00000001 -#define SQ_IMAGE_LOAD_PCK 0x00000002 -#define SQ_IMAGE_LOAD_PCK_SGN 0x00000003 -#define SQ_IMAGE_LOAD_MIP_PCK 0x00000004 -#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005 -#define SQ_IMAGE_STORE 0x00000008 -#define SQ_IMAGE_STORE_MIP 0x00000009 -#define SQ_IMAGE_STORE_PCK 0x0000000a -#define SQ_IMAGE_STORE_MIP_PCK 0x0000000b -#define SQ_IMAGE_GET_RESINFO 0x0000000e -#define SQ_IMAGE_ATOMIC_SWAP 0x00000010 -#define SQ_IMAGE_ATOMIC_CMPSWAP 0x00000011 -#define SQ_IMAGE_ATOMIC_ADD 0x00000012 -#define SQ_IMAGE_ATOMIC_SUB 0x00000013 -#define SQ_IMAGE_ATOMIC_SMIN 0x00000014 -#define SQ_IMAGE_ATOMIC_UMIN 0x00000015 -#define SQ_IMAGE_ATOMIC_SMAX 0x00000016 -#define SQ_IMAGE_ATOMIC_UMAX 0x00000017 -#define SQ_IMAGE_ATOMIC_AND 0x00000018 -#define SQ_IMAGE_ATOMIC_OR 0x00000019 -#define SQ_IMAGE_ATOMIC_XOR 0x0000001a -#define SQ_IMAGE_ATOMIC_INC 0x0000001b -#define SQ_IMAGE_ATOMIC_DEC 0x0000001c -#define SQ_IMAGE_SAMPLE 0x00000020 -#define SQ_IMAGE_SAMPLE_CL 0x00000021 -#define SQ_IMAGE_SAMPLE_D 0x00000022 -#define SQ_IMAGE_SAMPLE_D_CL 0x00000023 -#define SQ_IMAGE_SAMPLE_L 0x00000024 -#define SQ_IMAGE_SAMPLE_B 0x00000025 -#define SQ_IMAGE_SAMPLE_B_CL 0x00000026 -#define SQ_IMAGE_SAMPLE_LZ 0x00000027 -#define SQ_IMAGE_SAMPLE_C 0x00000028 -#define SQ_IMAGE_SAMPLE_C_CL 0x00000029 -#define SQ_IMAGE_SAMPLE_C_D 0x0000002a -#define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b -#define SQ_IMAGE_SAMPLE_C_L 0x0000002c -#define SQ_IMAGE_SAMPLE_C_B 0x0000002d -#define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e -#define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f -#define SQ_IMAGE_SAMPLE_O 0x00000030 -#define SQ_IMAGE_SAMPLE_CL_O 0x00000031 -#define SQ_IMAGE_SAMPLE_D_O 0x00000032 -#define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033 -#define SQ_IMAGE_SAMPLE_L_O 0x00000034 -#define SQ_IMAGE_SAMPLE_B_O 0x00000035 -#define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036 -#define SQ_IMAGE_SAMPLE_LZ_O 0x00000037 -#define SQ_IMAGE_SAMPLE_C_O 0x00000038 -#define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039 -#define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a -#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b -#define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c -#define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d -#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e -#define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f -#define SQ_IMAGE_GATHER4 0x00000040 -#define SQ_IMAGE_GATHER4_CL 0x00000041 -#define SQ_IMAGE_GATHER4H 0x00000042 -#define SQ_IMAGE_GATHER4_L 0x00000044 -#define SQ_IMAGE_GATHER4_B 0x00000045 -#define SQ_IMAGE_GATHER4_B_CL 0x00000046 -#define SQ_IMAGE_GATHER4_LZ 0x00000047 -#define SQ_IMAGE_GATHER4_C 0x00000048 -#define SQ_IMAGE_GATHER4_C_CL 0x00000049 -#define SQ_IMAGE_GATHER4H_PCK 0x0000004a -#define SQ_IMAGE_GATHER8H_PCK 0x0000004b -#define SQ_IMAGE_GATHER4_C_L 0x0000004c -#define SQ_IMAGE_GATHER4_C_B 0x0000004d -#define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e -#define SQ_IMAGE_GATHER4_C_LZ 0x0000004f -#define SQ_IMAGE_GATHER4_O 0x00000050 -#define SQ_IMAGE_GATHER4_CL_O 0x00000051 -#define SQ_IMAGE_GATHER4_L_O 0x00000054 -#define SQ_IMAGE_GATHER4_B_O 0x00000055 -#define SQ_IMAGE_GATHER4_B_CL_O 0x00000056 -#define SQ_IMAGE_GATHER4_LZ_O 0x00000057 -#define SQ_IMAGE_GATHER4_C_O 0x00000058 -#define SQ_IMAGE_GATHER4_C_CL_O 0x00000059 -#define SQ_IMAGE_GATHER4_C_L_O 0x0000005c -#define SQ_IMAGE_GATHER4_C_B_O 0x0000005d -#define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e -#define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f -#define SQ_IMAGE_GET_LOD 0x00000060 -#define SQ_IMAGE_SAMPLE_CD 0x00000068 -#define SQ_IMAGE_SAMPLE_CD_CL 0x00000069 -#define SQ_IMAGE_SAMPLE_C_CD 0x0000006a -#define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b -#define SQ_IMAGE_SAMPLE_CD_O 0x0000006c -#define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d -#define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e -#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f -#define SQ_IMAGE_RSRC256 0x0000007e -#define SQ_IMAGE_SAMPLER 0x0000007f -#define SQ_IMAGE_SAMPLE_A 0x000000a0 -#define SQ_IMAGE_SAMPLE_CL_A 0x000000a1 -#define SQ_IMAGE_SAMPLE_B_A 0x000000a5 -#define SQ_IMAGE_SAMPLE_B_CL_A 0x000000a6 -#define SQ_IMAGE_SAMPLE_C_A 0x000000a8 -#define SQ_IMAGE_SAMPLE_C_CL_A 0x000000a9 -#define SQ_IMAGE_SAMPLE_C_B_A 0x000000ad -#define SQ_IMAGE_SAMPLE_C_B_CL_A 0x000000ae -#define SQ_IMAGE_SAMPLE_O_A 0x000000b0 -#define SQ_IMAGE_SAMPLE_CL_O_A 0x000000b1 -#define SQ_IMAGE_SAMPLE_B_O_A 0x000000b5 -#define SQ_IMAGE_SAMPLE_B_CL_O_A 0x000000b6 -#define SQ_IMAGE_SAMPLE_C_O_A 0x000000b8 -#define SQ_IMAGE_SAMPLE_C_CL_O_A 0x000000b9 -#define SQ_IMAGE_SAMPLE_C_B_O_A 0x000000bd -#define SQ_IMAGE_SAMPLE_C_B_CL_O_A 0x000000be -#define SQ_IMAGE_GATHER4_A 0x000000c0 -#define SQ_IMAGE_GATHER4_CL_A 0x000000c1 -#define SQ_IMAGE_GATHER4_B_A 0x000000c5 -#define SQ_IMAGE_GATHER4_B_CL_A 0x000000c6 -#define SQ_IMAGE_GATHER4_C_A 0x000000c8 -#define SQ_IMAGE_GATHER4_C_CL_A 0x000000c9 -#define SQ_IMAGE_GATHER4_C_B_A 0x000000cd -#define SQ_IMAGE_GATHER4_C_B_CL_A 0x000000ce -#define SQ_IMAGE_GATHER4_O_A 0x000000d0 -#define SQ_IMAGE_GATHER4_CL_O_A 0x000000d1 -#define SQ_IMAGE_GATHER4_B_O_A 0x000000d5 -#define SQ_IMAGE_GATHER4_B_CL_O_A 0x000000d6 -#define SQ_IMAGE_GATHER4_C_O_A 0x000000d8 -#define SQ_IMAGE_GATHER4_C_CL_O_A 0x000000d9 -#define SQ_IMAGE_GATHER4_C_B_O_A 0x000000dd -#define SQ_IMAGE_GATHER4_C_B_CL_O_A 0x000000de - -/* - * VALUE_SQ_SSRC_0_63_INLINES value - */ - -#define SQ_SRC_0 0x00000080 -#define SQ_SRC_1_INT 0x00000081 -#define SQ_SRC_2_INT 0x00000082 -#define SQ_SRC_3_INT 0x00000083 -#define SQ_SRC_4_INT 0x00000084 -#define SQ_SRC_5_INT 0x00000085 -#define SQ_SRC_6_INT 0x00000086 -#define SQ_SRC_7_INT 0x00000087 -#define SQ_SRC_8_INT 0x00000088 -#define SQ_SRC_9_INT 0x00000089 -#define SQ_SRC_10_INT 0x0000008a -#define SQ_SRC_11_INT 0x0000008b -#define SQ_SRC_12_INT 0x0000008c -#define SQ_SRC_13_INT 0x0000008d -#define SQ_SRC_14_INT 0x0000008e -#define SQ_SRC_15_INT 0x0000008f -#define SQ_SRC_16_INT 0x00000090 -#define SQ_SRC_17_INT 0x00000091 -#define SQ_SRC_18_INT 0x00000092 -#define SQ_SRC_19_INT 0x00000093 -#define SQ_SRC_20_INT 0x00000094 -#define SQ_SRC_21_INT 0x00000095 -#define SQ_SRC_22_INT 0x00000096 -#define SQ_SRC_23_INT 0x00000097 -#define SQ_SRC_24_INT 0x00000098 -#define SQ_SRC_25_INT 0x00000099 -#define SQ_SRC_26_INT 0x0000009a -#define SQ_SRC_27_INT 0x0000009b -#define SQ_SRC_28_INT 0x0000009c -#define SQ_SRC_29_INT 0x0000009d -#define SQ_SRC_30_INT 0x0000009e -#define SQ_SRC_31_INT 0x0000009f -#define SQ_SRC_32_INT 0x000000a0 -#define SQ_SRC_33_INT 0x000000a1 -#define SQ_SRC_34_INT 0x000000a2 -#define SQ_SRC_35_INT 0x000000a3 -#define SQ_SRC_36_INT 0x000000a4 -#define SQ_SRC_37_INT 0x000000a5 -#define SQ_SRC_38_INT 0x000000a6 -#define SQ_SRC_39_INT 0x000000a7 -#define SQ_SRC_40_INT 0x000000a8 -#define SQ_SRC_41_INT 0x000000a9 -#define SQ_SRC_42_INT 0x000000aa -#define SQ_SRC_43_INT 0x000000ab -#define SQ_SRC_44_INT 0x000000ac -#define SQ_SRC_45_INT 0x000000ad -#define SQ_SRC_46_INT 0x000000ae -#define SQ_SRC_47_INT 0x000000af -#define SQ_SRC_48_INT 0x000000b0 -#define SQ_SRC_49_INT 0x000000b1 -#define SQ_SRC_50_INT 0x000000b2 -#define SQ_SRC_51_INT 0x000000b3 -#define SQ_SRC_52_INT 0x000000b4 -#define SQ_SRC_53_INT 0x000000b5 -#define SQ_SRC_54_INT 0x000000b6 -#define SQ_SRC_55_INT 0x000000b7 -#define SQ_SRC_56_INT 0x000000b8 -#define SQ_SRC_57_INT 0x000000b9 -#define SQ_SRC_58_INT 0x000000ba -#define SQ_SRC_59_INT 0x000000bb -#define SQ_SRC_60_INT 0x000000bc -#define SQ_SRC_61_INT 0x000000bd -#define SQ_SRC_62_INT 0x000000be -#define SQ_SRC_63_INT 0x000000bf - -/* - * VALUE_SQ_OP_SOPC value - */ - -#define SQ_S_CMP_EQ_I32 0x00000000 -#define SQ_S_CMP_LG_I32 0x00000001 -#define SQ_S_CMP_GT_I32 0x00000002 -#define SQ_S_CMP_GE_I32 0x00000003 -#define SQ_S_CMP_LT_I32 0x00000004 -#define SQ_S_CMP_LE_I32 0x00000005 -#define SQ_S_CMP_EQ_U32 0x00000006 -#define SQ_S_CMP_LG_U32 0x00000007 -#define SQ_S_CMP_GT_U32 0x00000008 -#define SQ_S_CMP_GE_U32 0x00000009 -#define SQ_S_CMP_LT_U32 0x0000000a -#define SQ_S_CMP_LE_U32 0x0000000b -#define SQ_S_BITCMP0_B32 0x0000000c -#define SQ_S_BITCMP1_B32 0x0000000d -#define SQ_S_BITCMP0_B64 0x0000000e -#define SQ_S_BITCMP1_B64 0x0000000f -#define SQ_S_SETVSKIP 0x00000010 -#define SQ_S_SET_GPR_IDX_ON 0x00000011 -#define SQ_S_CMP_EQ_U64 0x00000012 -#define SQ_S_CMP_LG_U64 0x00000013 - -/* - * VALUE_SQ_OP_SOPK value - */ - -#define SQ_S_MOVK_I32 0x00000000 -#define SQ_S_CMOVK_I32 0x00000001 -#define SQ_S_CMPK_EQ_I32 0x00000002 -#define SQ_S_CMPK_LG_I32 0x00000003 -#define SQ_S_CMPK_GT_I32 0x00000004 -#define SQ_S_CMPK_GE_I32 0x00000005 -#define SQ_S_CMPK_LT_I32 0x00000006 -#define SQ_S_CMPK_LE_I32 0x00000007 -#define SQ_S_CMPK_EQ_U32 0x00000008 -#define SQ_S_CMPK_LG_U32 0x00000009 -#define SQ_S_CMPK_GT_U32 0x0000000a -#define SQ_S_CMPK_GE_U32 0x0000000b -#define SQ_S_CMPK_LT_U32 0x0000000c -#define SQ_S_CMPK_LE_U32 0x0000000d -#define SQ_S_ADDK_I32 0x0000000e -#define SQ_S_MULK_I32 0x0000000f -#define SQ_S_CBRANCH_I_FORK 0x00000010 -#define SQ_S_GETREG_B32 0x00000011 -#define SQ_S_SETREG_B32 0x00000012 -#define SQ_S_GETREG_REGRD_B32 0x00000013 -#define SQ_S_SETREG_IMM32_B32 0x00000014 -#define SQ_S_CALL_B64 0x00000015 - -/* - * VALUE_SQ_CNT value - */ - -#define SQ_CNT1 0x00000000 -#define SQ_CNT2 0x00000001 -#define SQ_CNT3 0x00000002 -#define SQ_CNT4 0x00000003 - -/* - * VALUE_SQ_OPU_VOP3 value - */ - -#define SQ_V_OPC_OFFSET 0x00000000 -#define SQ_V_OP2_OFFSET 0x00000100 -#define SQ_V_OP1_OFFSET 0x00000140 -#define SQ_V_INTRP_OFFSET 0x00000270 -#define SQ_V_OP3P_OFFSET 0x00000380 - -/* - * VALUE_SQ_SDWA_UNUSED value - */ - -#define SQ_SDWA_UNUSED_PAD 0x00000000 -#define SQ_SDWA_UNUSED_SEXT 0x00000001 -#define SQ_SDWA_UNUSED_PRESERVE 0x00000002 - -/* - * VALUE_SQ_DPP_CTRL value - */ - -#define SQ_DPP_QUAD_PERM 0x00000000 -#define SQ_DPP_ROW_SL1 0x00000101 -#define SQ_DPP_ROW_SL2 0x00000102 -#define SQ_DPP_ROW_SL3 0x00000103 -#define SQ_DPP_ROW_SL4 0x00000104 -#define SQ_DPP_ROW_SL5 0x00000105 -#define SQ_DPP_ROW_SL6 0x00000106 -#define SQ_DPP_ROW_SL7 0x00000107 -#define SQ_DPP_ROW_SL8 0x00000108 -#define SQ_DPP_ROW_SL9 0x00000109 -#define SQ_DPP_ROW_SL10 0x0000010a -#define SQ_DPP_ROW_SL11 0x0000010b -#define SQ_DPP_ROW_SL12 0x0000010c -#define SQ_DPP_ROW_SL13 0x0000010d -#define SQ_DPP_ROW_SL14 0x0000010e -#define SQ_DPP_ROW_SL15 0x0000010f -#define SQ_DPP_ROW_SR1 0x00000111 -#define SQ_DPP_ROW_SR2 0x00000112 -#define SQ_DPP_ROW_SR3 0x00000113 -#define SQ_DPP_ROW_SR4 0x00000114 -#define SQ_DPP_ROW_SR5 0x00000115 -#define SQ_DPP_ROW_SR6 0x00000116 -#define SQ_DPP_ROW_SR7 0x00000117 -#define SQ_DPP_ROW_SR8 0x00000118 -#define SQ_DPP_ROW_SR9 0x00000119 -#define SQ_DPP_ROW_SR10 0x0000011a -#define SQ_DPP_ROW_SR11 0x0000011b -#define SQ_DPP_ROW_SR12 0x0000011c -#define SQ_DPP_ROW_SR13 0x0000011d -#define SQ_DPP_ROW_SR14 0x0000011e -#define SQ_DPP_ROW_SR15 0x0000011f -#define SQ_DPP_ROW_RR1 0x00000121 -#define SQ_DPP_ROW_RR2 0x00000122 -#define SQ_DPP_ROW_RR3 0x00000123 -#define SQ_DPP_ROW_RR4 0x00000124 -#define SQ_DPP_ROW_RR5 0x00000125 -#define SQ_DPP_ROW_RR6 0x00000126 -#define SQ_DPP_ROW_RR7 0x00000127 -#define SQ_DPP_ROW_RR8 0x00000128 -#define SQ_DPP_ROW_RR9 0x00000129 -#define SQ_DPP_ROW_RR10 0x0000012a -#define SQ_DPP_ROW_RR11 0x0000012b -#define SQ_DPP_ROW_RR12 0x0000012c -#define SQ_DPP_ROW_RR13 0x0000012d -#define SQ_DPP_ROW_RR14 0x0000012e -#define SQ_DPP_ROW_RR15 0x0000012f -#define SQ_DPP_WF_SL1 0x00000130 -#define SQ_DPP_WF_RL1 0x00000134 -#define SQ_DPP_WF_SR1 0x00000138 -#define SQ_DPP_WF_RR1 0x0000013c -#define SQ_DPP_ROW_MIRROR 0x00000140 -#define SQ_DPP_ROW_HALF_MIRROR 0x00000141 -#define SQ_DPP_ROW_BCAST15 0x00000142 -#define SQ_DPP_ROW_BCAST31 0x00000143 - -/* - * VALUE_SQ_ATTR value - */ - -#define SQ_ATTR0 0x00000000 - -/* - * VALUE_SQ_OP_EXP value - */ - -#define SQ_EXP 0x00000000 - -/* - * VALUE_SQ_SSRC_SPECIAL_SDWA value - */ - -#define SQ_SRC_SDWA 0x000000f9 - -/* - * VALUE_SQ_SSRC_SPECIAL_NOLIT value - */ - -#define SQ_SRC_64_INT 0x000000c0 -#define SQ_SRC_M_1_INT 0x000000c1 -#define SQ_SRC_M_2_INT 0x000000c2 -#define SQ_SRC_M_3_INT 0x000000c3 -#define SQ_SRC_M_4_INT 0x000000c4 -#define SQ_SRC_M_5_INT 0x000000c5 -#define SQ_SRC_M_6_INT 0x000000c6 -#define SQ_SRC_M_7_INT 0x000000c7 -#define SQ_SRC_M_8_INT 0x000000c8 -#define SQ_SRC_M_9_INT 0x000000c9 -#define SQ_SRC_M_10_INT 0x000000ca -#define SQ_SRC_M_11_INT 0x000000cb -#define SQ_SRC_M_12_INT 0x000000cc -#define SQ_SRC_M_13_INT 0x000000cd -#define SQ_SRC_M_14_INT 0x000000ce -#define SQ_SRC_M_15_INT 0x000000cf -#define SQ_SRC_M_16_INT 0x000000d0 -#define SQ_SRC_0_5 0x000000f0 -#define SQ_SRC_M_0_5 0x000000f1 -#define SQ_SRC_1 0x000000f2 -#define SQ_SRC_M_1 0x000000f3 -#define SQ_SRC_2 0x000000f4 -#define SQ_SRC_M_2 0x000000f5 -#define SQ_SRC_4 0x000000f6 -#define SQ_SRC_M_4 0x000000f7 -#define SQ_SRC_INV_2PI 0x000000f8 - -/* - * VALUE_SQ_OP_SOPP value - */ - -#define SQ_S_NOP 0x00000000 -#define SQ_S_ENDPGM 0x00000001 -#define SQ_S_BRANCH 0x00000002 -#define SQ_S_WAKEUP 0x00000003 -#define SQ_S_CBRANCH_SCC0 0x00000004 -#define SQ_S_CBRANCH_SCC1 0x00000005 -#define SQ_S_CBRANCH_VCCZ 0x00000006 -#define SQ_S_CBRANCH_VCCNZ 0x00000007 -#define SQ_S_CBRANCH_EXECZ 0x00000008 -#define SQ_S_CBRANCH_EXECNZ 0x00000009 -#define SQ_S_BARRIER 0x0000000a -#define SQ_S_SETKILL 0x0000000b -#define SQ_S_WAITCNT 0x0000000c -#define SQ_S_SETHALT 0x0000000d -#define SQ_S_SLEEP 0x0000000e -#define SQ_S_SETPRIO 0x0000000f -#define SQ_S_SENDMSG 0x00000010 -#define SQ_S_SENDMSGHALT 0x00000011 -#define SQ_S_TRAP 0x00000012 -#define SQ_S_ICACHE_INV 0x00000013 -#define SQ_S_INCPERFLEVEL 0x00000014 -#define SQ_S_DECPERFLEVEL 0x00000015 -#define SQ_S_TTRACEDATA 0x00000016 -#define SQ_S_CBRANCH_CDBGSYS 0x00000017 -#define SQ_S_CBRANCH_CDBGUSER 0x00000018 -#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x00000019 -#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x0000001a -#define SQ_S_ENDPGM_SAVED 0x0000001b -#define SQ_S_SET_GPR_IDX_OFF 0x0000001c -#define SQ_S_SET_GPR_IDX_MODE 0x0000001d -#define SQ_S_ENDPGM_ORDERED_PS_DONE 0x0000001e - -/* - * VALUE_SQ_OP_DS value - */ - -#define SQ_DS_ADD_U32 0x00000000 -#define SQ_DS_SUB_U32 0x00000001 -#define SQ_DS_RSUB_U32 0x00000002 -#define SQ_DS_INC_U32 0x00000003 -#define SQ_DS_DEC_U32 0x00000004 -#define SQ_DS_MIN_I32 0x00000005 -#define SQ_DS_MAX_I32 0x00000006 -#define SQ_DS_MIN_U32 0x00000007 -#define SQ_DS_MAX_U32 0x00000008 -#define SQ_DS_AND_B32 0x00000009 -#define SQ_DS_OR_B32 0x0000000a -#define SQ_DS_XOR_B32 0x0000000b -#define SQ_DS_MSKOR_B32 0x0000000c -#define SQ_DS_WRITE_B32 0x0000000d -#define SQ_DS_WRITE2_B32 0x0000000e -#define SQ_DS_WRITE2ST64_B32 0x0000000f -#define SQ_DS_CMPST_B32 0x00000010 -#define SQ_DS_CMPST_F32 0x00000011 -#define SQ_DS_MIN_F32 0x00000012 -#define SQ_DS_MAX_F32 0x00000013 -#define SQ_DS_NOP 0x00000014 -#define SQ_DS_ADD_F32 0x00000015 -#define SQ_DS_WRITE_ADDTID_B32 0x0000001d -#define SQ_DS_WRITE_B8 0x0000001e -#define SQ_DS_WRITE_B16 0x0000001f -#define SQ_DS_ADD_RTN_U32 0x00000020 -#define SQ_DS_SUB_RTN_U32 0x00000021 -#define SQ_DS_RSUB_RTN_U32 0x00000022 -#define SQ_DS_INC_RTN_U32 0x00000023 -#define SQ_DS_DEC_RTN_U32 0x00000024 -#define SQ_DS_MIN_RTN_I32 0x00000025 -#define SQ_DS_MAX_RTN_I32 0x00000026 -#define SQ_DS_MIN_RTN_U32 0x00000027 -#define SQ_DS_MAX_RTN_U32 0x00000028 -#define SQ_DS_AND_RTN_B32 0x00000029 -#define SQ_DS_OR_RTN_B32 0x0000002a -#define SQ_DS_XOR_RTN_B32 0x0000002b -#define SQ_DS_MSKOR_RTN_B32 0x0000002c -#define SQ_DS_WRXCHG_RTN_B32 0x0000002d -#define SQ_DS_WRXCHG2_RTN_B32 0x0000002e -#define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f -#define SQ_DS_CMPST_RTN_B32 0x00000030 -#define SQ_DS_CMPST_RTN_F32 0x00000031 -#define SQ_DS_MIN_RTN_F32 0x00000032 -#define SQ_DS_MAX_RTN_F32 0x00000033 -#define SQ_DS_WRAP_RTN_B32 0x00000034 -#define SQ_DS_ADD_RTN_F32 0x00000035 -#define SQ_DS_READ_B32 0x00000036 -#define SQ_DS_READ2_B32 0x00000037 -#define SQ_DS_READ2ST64_B32 0x00000038 -#define SQ_DS_READ_I8 0x00000039 -#define SQ_DS_READ_U8 0x0000003a -#define SQ_DS_READ_I16 0x0000003b -#define SQ_DS_READ_U16 0x0000003c -#define SQ_DS_SWIZZLE_B32 0x0000003d -#define SQ_DS_PERMUTE_B32 0x0000003e -#define SQ_DS_BPERMUTE_B32 0x0000003f -#define SQ_DS_ADD_U64 0x00000040 -#define SQ_DS_SUB_U64 0x00000041 -#define SQ_DS_RSUB_U64 0x00000042 -#define SQ_DS_INC_U64 0x00000043 -#define SQ_DS_DEC_U64 0x00000044 -#define SQ_DS_MIN_I64 0x00000045 -#define SQ_DS_MAX_I64 0x00000046 -#define SQ_DS_MIN_U64 0x00000047 -#define SQ_DS_MAX_U64 0x00000048 -#define SQ_DS_AND_B64 0x00000049 -#define SQ_DS_OR_B64 0x0000004a -#define SQ_DS_XOR_B64 0x0000004b -#define SQ_DS_MSKOR_B64 0x0000004c -#define SQ_DS_WRITE_B64 0x0000004d -#define SQ_DS_WRITE2_B64 0x0000004e -#define SQ_DS_WRITE2ST64_B64 0x0000004f -#define SQ_DS_CMPST_B64 0x00000050 -#define SQ_DS_CMPST_F64 0x00000051 -#define SQ_DS_MIN_F64 0x00000052 -#define SQ_DS_MAX_F64 0x00000053 -#define SQ_DS_WRITE_B8_D16_HI 0x00000054 -#define SQ_DS_WRITE_B16_D16_HI 0x00000055 -#define SQ_DS_READ_U8_D16 0x00000056 -#define SQ_DS_READ_U8_D16_HI 0x00000057 -#define SQ_DS_READ_I8_D16 0x00000058 -#define SQ_DS_READ_I8_D16_HI 0x00000059 -#define SQ_DS_READ_U16_D16 0x0000005a -#define SQ_DS_READ_U16_D16_HI 0x0000005b -#define SQ_DS_ADD_RTN_U64 0x00000060 -#define SQ_DS_SUB_RTN_U64 0x00000061 -#define SQ_DS_RSUB_RTN_U64 0x00000062 -#define SQ_DS_INC_RTN_U64 0x00000063 -#define SQ_DS_DEC_RTN_U64 0x00000064 -#define SQ_DS_MIN_RTN_I64 0x00000065 -#define SQ_DS_MAX_RTN_I64 0x00000066 -#define SQ_DS_MIN_RTN_U64 0x00000067 -#define SQ_DS_MAX_RTN_U64 0x00000068 -#define SQ_DS_AND_RTN_B64 0x00000069 -#define SQ_DS_OR_RTN_B64 0x0000006a -#define SQ_DS_XOR_RTN_B64 0x0000006b -#define SQ_DS_MSKOR_RTN_B64 0x0000006c -#define SQ_DS_WRXCHG_RTN_B64 0x0000006d -#define SQ_DS_WRXCHG2_RTN_B64 0x0000006e -#define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f -#define SQ_DS_CMPST_RTN_B64 0x00000070 -#define SQ_DS_CMPST_RTN_F64 0x00000071 -#define SQ_DS_MIN_RTN_F64 0x00000072 -#define SQ_DS_MAX_RTN_F64 0x00000073 -#define SQ_DS_READ_B64 0x00000076 -#define SQ_DS_READ2_B64 0x00000077 -#define SQ_DS_READ2ST64_B64 0x00000078 -#define SQ_DS_CONDXCHG32_RTN_B64 0x0000007e -#define SQ_DS_ADD_SRC2_U32 0x00000080 -#define SQ_DS_SUB_SRC2_U32 0x00000081 -#define SQ_DS_RSUB_SRC2_U32 0x00000082 -#define SQ_DS_INC_SRC2_U32 0x00000083 -#define SQ_DS_DEC_SRC2_U32 0x00000084 -#define SQ_DS_MIN_SRC2_I32 0x00000085 -#define SQ_DS_MAX_SRC2_I32 0x00000086 -#define SQ_DS_MIN_SRC2_U32 0x00000087 -#define SQ_DS_MAX_SRC2_U32 0x00000088 -#define SQ_DS_AND_SRC2_B32 0x00000089 -#define SQ_DS_OR_SRC2_B32 0x0000008a -#define SQ_DS_XOR_SRC2_B32 0x0000008b -#define SQ_DS_WRITE_SRC2_B32 0x0000008d -#define SQ_DS_MIN_SRC2_F32 0x00000092 -#define SQ_DS_MAX_SRC2_F32 0x00000093 -#define SQ_DS_ADD_SRC2_F32 0x00000095 -#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x00000098 -#define SQ_DS_GWS_INIT 0x00000099 -#define SQ_DS_GWS_SEMA_V 0x0000009a -#define SQ_DS_GWS_SEMA_BR 0x0000009b -#define SQ_DS_GWS_SEMA_P 0x0000009c -#define SQ_DS_GWS_BARRIER 0x0000009d -#define SQ_DS_READ_ADDTID_B32 0x000000b6 -#define SQ_DS_CONSUME 0x000000bd -#define SQ_DS_APPEND 0x000000be -#define SQ_DS_ORDERED_COUNT 0x000000bf -#define SQ_DS_ADD_SRC2_U64 0x000000c0 -#define SQ_DS_SUB_SRC2_U64 0x000000c1 -#define SQ_DS_RSUB_SRC2_U64 0x000000c2 -#define SQ_DS_INC_SRC2_U64 0x000000c3 -#define SQ_DS_DEC_SRC2_U64 0x000000c4 -#define SQ_DS_MIN_SRC2_I64 0x000000c5 -#define SQ_DS_MAX_SRC2_I64 0x000000c6 -#define SQ_DS_MIN_SRC2_U64 0x000000c7 -#define SQ_DS_MAX_SRC2_U64 0x000000c8 -#define SQ_DS_AND_SRC2_B64 0x000000c9 -#define SQ_DS_OR_SRC2_B64 0x000000ca -#define SQ_DS_XOR_SRC2_B64 0x000000cb -#define SQ_DS_WRITE_SRC2_B64 0x000000cd -#define SQ_DS_MIN_SRC2_F64 0x000000d2 -#define SQ_DS_MAX_SRC2_F64 0x000000d3 -#define SQ_DS_WRITE_B96 0x000000de -#define SQ_DS_WRITE_B128 0x000000df -#define SQ_DS_CONDXCHG32_RTN_B128 0x000000fd -#define SQ_DS_READ_B96 0x000000fe -#define SQ_DS_READ_B128 0x000000ff - -/* - * VALUE_SQ_DPP_CTRL_R_1_15 value - */ - -#define SQ_R1 0x00000001 -#define SQ_R2 0x00000002 -#define SQ_R3 0x00000003 -#define SQ_R4 0x00000004 -#define SQ_R5 0x00000005 -#define SQ_R6 0x00000006 -#define SQ_R7 0x00000007 -#define SQ_R8 0x00000008 -#define SQ_R9 0x00000009 -#define SQ_R10 0x0000000a -#define SQ_R11 0x0000000b -#define SQ_R12 0x0000000c -#define SQ_R13 0x0000000d -#define SQ_R14 0x0000000e -#define SQ_R15 0x0000000f - -/* - * VALUE_SQ_SSRC_SPECIAL_EXECZ value - */ - -#define SQ_SRC_EXECZ 0x000000fc - -/* - * VALUE_SQ_OMOD value - */ - -#define SQ_OMOD_OFF 0x00000000 -#define SQ_OMOD_M2 0x00000001 -#define SQ_OMOD_M4 0x00000002 -#define SQ_OMOD_D2 0x00000003 - -/* - * VALUE_SQ_OP_VINTRP value - */ - -#define SQ_V_INTERP_P1_F32 0x00000000 -#define SQ_V_INTERP_P2_F32 0x00000001 -#define SQ_V_INTERP_MOV_F32 0x00000002 - -/* - * VALUE_SQ_SSRC_SPECIAL_APERTURE value - */ - -#define SQ_SRC_SHARED_BASE 0x000000eb -#define SQ_SRC_SHARED_LIMIT 0x000000ec -#define SQ_SRC_PRIVATE_BASE 0x000000ed -#define SQ_SRC_PRIVATE_LIMIT 0x000000ee - -/* - * VALUE_SQ_OP_FLAT value - */ - -#define SQ_FLAT_LOAD_UBYTE 0x00000010 -#define SQ_FLAT_LOAD_SBYTE 0x00000011 -#define SQ_FLAT_LOAD_USHORT 0x00000012 -#define SQ_FLAT_LOAD_SSHORT 0x00000013 -#define SQ_FLAT_LOAD_DWORD 0x00000014 -#define SQ_FLAT_LOAD_DWORDX2 0x00000015 -#define SQ_FLAT_LOAD_DWORDX3 0x00000016 -#define SQ_FLAT_LOAD_DWORDX4 0x00000017 -#define SQ_FLAT_STORE_BYTE 0x00000018 -#define SQ_FLAT_STORE_BYTE_D16_HI 0x00000019 -#define SQ_FLAT_STORE_SHORT 0x0000001a -#define SQ_FLAT_STORE_SHORT_D16_HI 0x0000001b -#define SQ_FLAT_STORE_DWORD 0x0000001c -#define SQ_FLAT_STORE_DWORDX2 0x0000001d -#define SQ_FLAT_STORE_DWORDX3 0x0000001e -#define SQ_FLAT_STORE_DWORDX4 0x0000001f -#define SQ_FLAT_LOAD_UBYTE_D16 0x00000020 -#define SQ_FLAT_LOAD_UBYTE_D16_HI 0x00000021 -#define SQ_FLAT_LOAD_SBYTE_D16 0x00000022 -#define SQ_FLAT_LOAD_SBYTE_D16_HI 0x00000023 -#define SQ_FLAT_LOAD_SHORT_D16 0x00000024 -#define SQ_FLAT_LOAD_SHORT_D16_HI 0x00000025 -#define SQ_FLAT_ATOMIC_SWAP 0x00000040 -#define SQ_FLAT_ATOMIC_CMPSWAP 0x00000041 -#define SQ_FLAT_ATOMIC_ADD 0x00000042 -#define SQ_FLAT_ATOMIC_SUB 0x00000043 -#define SQ_FLAT_ATOMIC_SMIN 0x00000044 -#define SQ_FLAT_ATOMIC_UMIN 0x00000045 -#define SQ_FLAT_ATOMIC_SMAX 0x00000046 -#define SQ_FLAT_ATOMIC_UMAX 0x00000047 -#define SQ_FLAT_ATOMIC_AND 0x00000048 -#define SQ_FLAT_ATOMIC_OR 0x00000049 -#define SQ_FLAT_ATOMIC_XOR 0x0000004a -#define SQ_FLAT_ATOMIC_INC 0x0000004b -#define SQ_FLAT_ATOMIC_DEC 0x0000004c -#define SQ_FLAT_ATOMIC_SWAP_X2 0x00000060 -#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x00000061 -#define SQ_FLAT_ATOMIC_ADD_X2 0x00000062 -#define SQ_FLAT_ATOMIC_SUB_X2 0x00000063 -#define SQ_FLAT_ATOMIC_SMIN_X2 0x00000064 -#define SQ_FLAT_ATOMIC_UMIN_X2 0x00000065 -#define SQ_FLAT_ATOMIC_SMAX_X2 0x00000066 -#define SQ_FLAT_ATOMIC_UMAX_X2 0x00000067 -#define SQ_FLAT_ATOMIC_AND_X2 0x00000068 -#define SQ_FLAT_ATOMIC_OR_X2 0x00000069 -#define SQ_FLAT_ATOMIC_XOR_X2 0x0000006a -#define SQ_FLAT_ATOMIC_INC_X2 0x0000006b -#define SQ_FLAT_ATOMIC_DEC_X2 0x0000006c - -/* - * VALUE_SQ_DPP_BOUND_CTRL value - */ - -#define SQ_DPP_BOUND_OFF 0x00000000 -#define SQ_DPP_BOUND_ZERO 0x00000001 - -/* - * VALUE_SQ_SSRC_SPECIAL_DPP value - */ - -#define SQ_SRC_DPP 0x000000fa - -/* - * VALUE_SQ_SGPR value - */ - -#define SQ_SGPR0 0x00000000 - -/* - * VALUE_SQ_OP_VOP2 value - */ - -#define SQ_V_CNDMASK_B32 0x00000000 -#define SQ_V_ADD_F32 0x00000001 -#define SQ_V_SUB_F32 0x00000002 -#define SQ_V_SUBREV_F32 0x00000003 -#define SQ_V_MUL_LEGACY_F32 0x00000004 -#define SQ_V_MUL_F32 0x00000005 -#define SQ_V_MUL_I32_I24 0x00000006 -#define SQ_V_MUL_HI_I32_I24 0x00000007 -#define SQ_V_MUL_U32_U24 0x00000008 -#define SQ_V_MUL_HI_U32_U24 0x00000009 -#define SQ_V_MIN_F32 0x0000000a -#define SQ_V_MAX_F32 0x0000000b -#define SQ_V_MIN_I32 0x0000000c -#define SQ_V_MAX_I32 0x0000000d -#define SQ_V_MIN_U32 0x0000000e -#define SQ_V_MAX_U32 0x0000000f -#define SQ_V_LSHRREV_B32 0x00000010 -#define SQ_V_ASHRREV_I32 0x00000011 -#define SQ_V_LSHLREV_B32 0x00000012 -#define SQ_V_AND_B32 0x00000013 -#define SQ_V_OR_B32 0x00000014 -#define SQ_V_XOR_B32 0x00000015 -#define SQ_V_MAC_F32 0x00000016 -#define SQ_V_MADMK_F32 0x00000017 -#define SQ_V_MADAK_F32 0x00000018 -#define SQ_V_ADD_CO_U32 0x00000019 -#define SQ_V_SUB_CO_U32 0x0000001a -#define SQ_V_SUBREV_CO_U32 0x0000001b -#define SQ_V_ADDC_CO_U32 0x0000001c -#define SQ_V_SUBB_CO_U32 0x0000001d -#define SQ_V_SUBBREV_CO_U32 0x0000001e -#define SQ_V_ADD_F16 0x0000001f -#define SQ_V_SUB_F16 0x00000020 -#define SQ_V_SUBREV_F16 0x00000021 -#define SQ_V_MUL_F16 0x00000022 -#define SQ_V_MAC_F16 0x00000023 -#define SQ_V_MADMK_F16 0x00000024 -#define SQ_V_MADAK_F16 0x00000025 -#define SQ_V_ADD_U16 0x00000026 -#define SQ_V_SUB_U16 0x00000027 -#define SQ_V_SUBREV_U16 0x00000028 -#define SQ_V_MUL_LO_U16 0x00000029 -#define SQ_V_LSHLREV_B16 0x0000002a -#define SQ_V_LSHRREV_B16 0x0000002b -#define SQ_V_ASHRREV_I16 0x0000002c -#define SQ_V_MAX_F16 0x0000002d -#define SQ_V_MIN_F16 0x0000002e -#define SQ_V_MAX_U16 0x0000002f -#define SQ_V_MAX_I16 0x00000030 -#define SQ_V_MIN_U16 0x00000031 -#define SQ_V_MIN_I16 0x00000032 -#define SQ_V_LDEXP_F16 0x00000033 -#define SQ_V_ADD_U32 0x00000034 -#define SQ_V_SUB_U32 0x00000035 -#define SQ_V_SUBREV_U32 0x00000036 - -/* - * VALUE_SQ_SYSMSG_OP value - */ - -#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001 -#define SQ_SYSMSG_OP_REG_RD 0x00000002 -#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003 -#define SQ_SYSMSG_OP_TTRACE_PC 0x00000004 -#define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005 -#define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006 - -/* - * VALUE_SQ_FLAT_SCRATCH_LOHI value - */ - -#define SQ_FLAT_SCRATCH_LO 0x00000066 -#define SQ_FLAT_SCRATCH_HI 0x00000067 - -/* - * VALUE_SQ_MSG value - */ - -#define SQ_MSG_INTERRUPT 0x00000001 -#define SQ_MSG_GS 0x00000002 -#define SQ_MSG_GS_DONE 0x00000003 -#define SQ_MSG_SAVEWAVE 0x00000004 -#define SQ_MSG_STALL_WAVE_GEN 0x00000005 -#define SQ_MSG_HALT_WAVES 0x00000006 -#define SQ_MSG_ORDERED_PS_DONE 0x00000007 -#define SQ_MSG_EARLY_PRIM_DEALLOC 0x00000008 -#define SQ_MSG_GS_ALLOC_REQ 0x00000009 -#define SQ_MSG_GET_DOORBELL 0x0000000a -#define SQ_MSG_SYSMSG 0x0000000f - -/* - * VALUE_SQ_OP_SOP2 value - */ - -#define SQ_S_ADD_U32 0x00000000 -#define SQ_S_SUB_U32 0x00000001 -#define SQ_S_ADD_I32 0x00000002 -#define SQ_S_SUB_I32 0x00000003 -#define SQ_S_ADDC_U32 0x00000004 -#define SQ_S_SUBB_U32 0x00000005 -#define SQ_S_MIN_I32 0x00000006 -#define SQ_S_MIN_U32 0x00000007 -#define SQ_S_MAX_I32 0x00000008 -#define SQ_S_MAX_U32 0x00000009 -#define SQ_S_CSELECT_B32 0x0000000a -#define SQ_S_CSELECT_B64 0x0000000b -#define SQ_S_AND_B32 0x0000000c -#define SQ_S_AND_B64 0x0000000d -#define SQ_S_OR_B32 0x0000000e -#define SQ_S_OR_B64 0x0000000f -#define SQ_S_XOR_B32 0x00000010 -#define SQ_S_XOR_B64 0x00000011 -#define SQ_S_ANDN2_B32 0x00000012 -#define SQ_S_ANDN2_B64 0x00000013 -#define SQ_S_ORN2_B32 0x00000014 -#define SQ_S_ORN2_B64 0x00000015 -#define SQ_S_NAND_B32 0x00000016 -#define SQ_S_NAND_B64 0x00000017 -#define SQ_S_NOR_B32 0x00000018 -#define SQ_S_NOR_B64 0x00000019 -#define SQ_S_XNOR_B32 0x0000001a -#define SQ_S_XNOR_B64 0x0000001b -#define SQ_S_LSHL_B32 0x0000001c -#define SQ_S_LSHL_B64 0x0000001d -#define SQ_S_LSHR_B32 0x0000001e -#define SQ_S_LSHR_B64 0x0000001f -#define SQ_S_ASHR_I32 0x00000020 -#define SQ_S_ASHR_I64 0x00000021 -#define SQ_S_BFM_B32 0x00000022 -#define SQ_S_BFM_B64 0x00000023 -#define SQ_S_MUL_I32 0x00000024 -#define SQ_S_BFE_U32 0x00000025 -#define SQ_S_BFE_I32 0x00000026 -#define SQ_S_BFE_U64 0x00000027 -#define SQ_S_BFE_I64 0x00000028 -#define SQ_S_CBRANCH_G_FORK 0x00000029 -#define SQ_S_ABSDIFF_I32 0x0000002a -#define SQ_S_RFE_RESTORE_B64 0x0000002b -#define SQ_S_MUL_HI_U32 0x0000002c -#define SQ_S_MUL_HI_I32 0x0000002d -#define SQ_S_LSHL1_ADD_U32 0x0000002e -#define SQ_S_LSHL2_ADD_U32 0x0000002f -#define SQ_S_LSHL3_ADD_U32 0x00000030 -#define SQ_S_LSHL4_ADD_U32 0x00000031 -#define SQ_S_PACK_LL_B32_B16 0x00000032 -#define SQ_S_PACK_LH_B32_B16 0x00000033 -#define SQ_S_PACK_HH_B32_B16 0x00000034 - -/* - * VALUE_SQ_SDST_M0 value - */ - -#define SQ_M0 0x0000007c - -/* - * VALUE_SQ_OP_VOP1 value - */ - -#define SQ_V_NOP 0x00000000 -#define SQ_V_MOV_B32 0x00000001 -#define SQ_V_READFIRSTLANE_B32 0x00000002 -#define SQ_V_CVT_I32_F64 0x00000003 -#define SQ_V_CVT_F64_I32 0x00000004 -#define SQ_V_CVT_F32_I32 0x00000005 -#define SQ_V_CVT_F32_U32 0x00000006 -#define SQ_V_CVT_U32_F32 0x00000007 -#define SQ_V_CVT_I32_F32 0x00000008 -#define SQ_V_MOV_FED_B32 0x00000009 -#define SQ_V_CVT_F16_F32 0x0000000a -#define SQ_V_CVT_F32_F16 0x0000000b -#define SQ_V_CVT_RPI_I32_F32 0x0000000c -#define SQ_V_CVT_FLR_I32_F32 0x0000000d -#define SQ_V_CVT_OFF_F32_I4 0x0000000e -#define SQ_V_CVT_F32_F64 0x0000000f -#define SQ_V_CVT_F64_F32 0x00000010 -#define SQ_V_CVT_F32_UBYTE0 0x00000011 -#define SQ_V_CVT_F32_UBYTE1 0x00000012 -#define SQ_V_CVT_F32_UBYTE2 0x00000013 -#define SQ_V_CVT_F32_UBYTE3 0x00000014 -#define SQ_V_CVT_U32_F64 0x00000015 -#define SQ_V_CVT_F64_U32 0x00000016 -#define SQ_V_TRUNC_F64 0x00000017 -#define SQ_V_CEIL_F64 0x00000018 -#define SQ_V_RNDNE_F64 0x00000019 -#define SQ_V_FLOOR_F64 0x0000001a -#define SQ_V_FRACT_F32 0x0000001b -#define SQ_V_TRUNC_F32 0x0000001c -#define SQ_V_CEIL_F32 0x0000001d -#define SQ_V_RNDNE_F32 0x0000001e -#define SQ_V_FLOOR_F32 0x0000001f -#define SQ_V_EXP_F32 0x00000020 -#define SQ_V_LOG_F32 0x00000021 -#define SQ_V_RCP_F32 0x00000022 -#define SQ_V_RCP_IFLAG_F32 0x00000023 -#define SQ_V_RSQ_F32 0x00000024 -#define SQ_V_RCP_F64 0x00000025 -#define SQ_V_RSQ_F64 0x00000026 -#define SQ_V_SQRT_F32 0x00000027 -#define SQ_V_SQRT_F64 0x00000028 -#define SQ_V_SIN_F32 0x00000029 -#define SQ_V_COS_F32 0x0000002a -#define SQ_V_NOT_B32 0x0000002b -#define SQ_V_BFREV_B32 0x0000002c -#define SQ_V_FFBH_U32 0x0000002d -#define SQ_V_FFBL_B32 0x0000002e -#define SQ_V_FFBH_I32 0x0000002f -#define SQ_V_FREXP_EXP_I32_F64 0x00000030 -#define SQ_V_FREXP_MANT_F64 0x00000031 -#define SQ_V_FRACT_F64 0x00000032 -#define SQ_V_FREXP_EXP_I32_F32 0x00000033 -#define SQ_V_FREXP_MANT_F32 0x00000034 -#define SQ_V_CLREXCP 0x00000035 -#define SQ_V_MOV_PRSV_B32 0x00000036 -#define SQ_V_SCREEN_PARTITION_4SE_B32 0x00000037 -#define SQ_V_CVT_F16_U16 0x00000039 -#define SQ_V_CVT_F16_I16 0x0000003a -#define SQ_V_CVT_U16_F16 0x0000003b -#define SQ_V_CVT_I16_F16 0x0000003c -#define SQ_V_RCP_F16 0x0000003d -#define SQ_V_SQRT_F16 0x0000003e -#define SQ_V_RSQ_F16 0x0000003f -#define SQ_V_LOG_F16 0x00000040 -#define SQ_V_EXP_F16 0x00000041 -#define SQ_V_FREXP_MANT_F16 0x00000042 -#define SQ_V_FREXP_EXP_I16_F16 0x00000043 -#define SQ_V_FLOOR_F16 0x00000044 -#define SQ_V_CEIL_F16 0x00000045 -#define SQ_V_TRUNC_F16 0x00000046 -#define SQ_V_RNDNE_F16 0x00000047 -#define SQ_V_FRACT_F16 0x00000048 -#define SQ_V_SIN_F16 0x00000049 -#define SQ_V_COS_F16 0x0000004a -#define SQ_V_EXP_LEGACY_F32 0x0000004b -#define SQ_V_LOG_LEGACY_F32 0x0000004c -#define SQ_V_CVT_NORM_I16_F16 0x0000004d -#define SQ_V_CVT_NORM_U16_F16 0x0000004e -#define SQ_V_SAT_PK_U8_I16 0x0000004f -#define SQ_V_WRITELANE_REGWR_B32 0x00000050 -#define SQ_V_SWAP_B32 0x00000051 - -/* - * VALUE_SQ_SSRC_SPECIAL_LIT value - */ - -#define SQ_SRC_LITERAL 0x000000ff - -/* - * VALUE_SQ_VGPR value - */ - -#define SQ_VGPR0 0x00000000 - -/* - * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value - */ - -#define SQ_SRC_POPS_EXITING_WAVE_ID 0x000000ef - -/* - * VALUE_SQ_SSRC_SPECIAL_VCCZ value - */ - -#define SQ_SRC_VCCZ 0x000000fb - -/* - * VALUE_SQ_OP_VOP3P value - */ - -#define SQ_V_PK_MAD_I16 0x00000000 -#define SQ_V_PK_MUL_LO_U16 0x00000001 -#define SQ_V_PK_ADD_I16 0x00000002 -#define SQ_V_PK_SUB_I16 0x00000003 -#define SQ_V_PK_LSHLREV_B16 0x00000004 -#define SQ_V_PK_LSHRREV_B16 0x00000005 -#define SQ_V_PK_ASHRREV_I16 0x00000006 -#define SQ_V_PK_MAX_I16 0x00000007 -#define SQ_V_PK_MIN_I16 0x00000008 -#define SQ_V_PK_MAD_U16 0x00000009 -#define SQ_V_PK_ADD_U16 0x0000000a -#define SQ_V_PK_SUB_U16 0x0000000b -#define SQ_V_PK_MAX_U16 0x0000000c -#define SQ_V_PK_MIN_U16 0x0000000d -#define SQ_V_PK_FMA_F16 0x0000000e -#define SQ_V_PK_ADD_F16 0x0000000f -#define SQ_V_PK_MUL_F16 0x00000010 -#define SQ_V_PK_MIN_F16 0x00000011 -#define SQ_V_PK_MAX_F16 0x00000012 -#define SQ_V_MAD_MIX_F32 0x00000020 -#define SQ_V_MAD_MIXLO_F16 0x00000021 -#define SQ_V_MAD_MIXHI_F16 0x00000022 - -/* - * VALUE_SQ_VCC value - */ - -#define SQ_VCC_ALL 0x00000000 - -/* - * VALUE_SQ_SRC_VGPR value - */ - -#define SQ_SRC_VGPR0 0x00000100 - -/* - * VALUE_SQ_XNACK_MASK_LOHI value - */ - -#define SQ_XNACK_MASK_LO 0x00000068 -#define SQ_XNACK_MASK_HI 0x00000069 - -/******************************************************* - * DIDT Enums - *******************************************************/ - -/******************************************************* - * SX Enums - *******************************************************/ - -/* - * SX_BLEND_OPT enum - */ - -typedef enum SX_BLEND_OPT { - BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, - BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, - BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, - BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, - BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, - BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, - BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, - BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, -} SX_BLEND_OPT; - -/* - * SX_OPT_COMB_FCN enum - */ - -typedef enum SX_OPT_COMB_FCN { - OPT_COMB_NONE = 0x00000000, - OPT_COMB_ADD = 0x00000001, - OPT_COMB_SUBTRACT = 0x00000002, - OPT_COMB_MIN = 0x00000003, - OPT_COMB_MAX = 0x00000004, - OPT_COMB_REVSUBTRACT = 0x00000005, - OPT_COMB_BLEND_DISABLED = 0x00000006, - OPT_COMB_SAFE_ADD = 0x00000007, -} SX_OPT_COMB_FCN; - -/* - * SX_DOWNCONVERT_FORMAT enum - */ - -typedef enum SX_DOWNCONVERT_FORMAT { - SX_RT_EXPORT_NO_CONVERSION = 0x00000000, - SX_RT_EXPORT_32_R = 0x00000001, - SX_RT_EXPORT_32_A = 0x00000002, - SX_RT_EXPORT_10_11_11 = 0x00000003, - SX_RT_EXPORT_2_10_10_10 = 0x00000004, - SX_RT_EXPORT_8_8_8_8 = 0x00000005, - SX_RT_EXPORT_5_6_5 = 0x00000006, - SX_RT_EXPORT_1_5_5_5 = 0x00000007, - SX_RT_EXPORT_4_4_4_4 = 0x00000008, - SX_RT_EXPORT_16_16_GR = 0x00000009, - SX_RT_EXPORT_16_16_AR = 0x0000000a, -} SX_DOWNCONVERT_FORMAT; - -/* - * SX_PERFCOUNTER_VALS enum - */ - -typedef enum SX_PERFCOUNTER_VALS { - SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000, - SX_PERF_SEL_PA_REQ = 0x00000001, - SX_PERF_SEL_PA_POS = 0x00000002, - SX_PERF_SEL_CLOCK = 0x00000003, - SX_PERF_SEL_GATE_EN1 = 0x00000004, - SX_PERF_SEL_GATE_EN2 = 0x00000005, - SX_PERF_SEL_GATE_EN3 = 0x00000006, - SX_PERF_SEL_GATE_EN4 = 0x00000007, - SX_PERF_SEL_SH_POS_STARVE = 0x00000008, - SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009, - SX_PERF_SEL_SH_POS_STALL = 0x0000000a, - SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b, - SX_PERF_SEL_DB0_PIXELS = 0x0000000c, - SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d, - SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e, - SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f, - SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010, - SX_PERF_SEL_DB1_PIXELS = 0x00000011, - SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012, - SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013, - SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014, - SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015, - SX_PERF_SEL_DB2_PIXELS = 0x00000016, - SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017, - SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018, - SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019, - SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a, - SX_PERF_SEL_DB3_PIXELS = 0x0000001b, - SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c, - SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d, - SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e, - SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f, - SX_PERF_SEL_COL_BUSY = 0x00000020, - SX_PERF_SEL_POS_BUSY = 0x00000021, - SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022, - SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023, - SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024, - SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025, - SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026, - SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027, - SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028, - SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029, - SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a, - SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b, - SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c, - SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d, - SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e, - SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f, - SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030, - SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031, - SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032, - SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033, - SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034, - SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035, - SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036, - SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037, - SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038, - SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039, - SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a, - SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b, - SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c, - SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d, - SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e, - SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f, - SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040, - SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041, - SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042, - SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043, - SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044, - SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045, - SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046, - SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047, - SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048, - SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049, - SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a, - SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b, - SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c, - SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d, - SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e, - SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f, - SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050, - SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051, - SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052, - SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053, - SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054, - SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055, - SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056, - SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057, - SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058, - SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059, - SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a, - SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b, - SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c, - SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d, - SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e, - SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f, - SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060, - SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061, - SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062, - SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063, - SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064, - SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065, - SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066, - SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067, - SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068, - SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069, - SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a, - SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b, - SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c, - SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d, - SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e, - SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f, - SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070, - SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071, - SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072, - SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073, - SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074, - SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075, - SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076, - SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077, - SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078, - SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079, - SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a, - SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b, - SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c, - SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d, - SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e, - SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f, - SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080, - SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081, - SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082, - SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083, - SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084, - SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085, - SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086, - SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087, - SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088, - SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089, - SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a, - SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b, - SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c, - SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d, - SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e, - SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f, - SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090, - SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091, - SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092, - SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093, - SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094, - SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095, - SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096, - SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097, - SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098, - SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099, - SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a, - SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b, - SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c, - SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d, - SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e, - SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f, - SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0, - SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1, - SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2, - SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3, - SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4, - SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5, - SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6, - SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7, - SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8, - SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9, - SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa, - SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab, - SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac, - SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad, - SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae, - SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af, - SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0, - SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1, - SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2, - SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3, - SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4, - SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5, - SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6, - SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7, - SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8, - SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9, - SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba, - SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb, - SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc, - SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd, - SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be, - SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf, - SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0, - SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1, - SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2, - SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3, - SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4, - SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5, - SX_PERF_SEL_PA_REQ_LATENCY = 0x000000c6, - SX_PERF_SEL_POS_SCBD_STALL = 0x000000c7, - SX_PERF_SEL_COL_SCBD_STALL = 0x000000c8, - SX_PERF_SEL_CLOCK_DROP_STALL = 0x000000c9, - SX_PERF_SEL_GATE_EN5 = 0x000000ca, - SX_PERF_SEL_GATE_EN6 = 0x000000cb, - SX_PERF_SEL_DB0_SIZE = 0x000000cc, - SX_PERF_SEL_DB1_SIZE = 0x000000cd, - SX_PERF_SEL_DB2_SIZE = 0x000000ce, - SX_PERF_SEL_DB3_SIZE = 0x000000cf, -} SX_PERFCOUNTER_VALS; - -/******************************************************* - * DB Enums - *******************************************************/ - -/* - * ForceControl enum - */ - -typedef enum ForceControl { - FORCE_OFF = 0x00000000, - FORCE_ENABLE = 0x00000001, - FORCE_DISABLE = 0x00000002, - FORCE_RESERVED = 0x00000003, -} ForceControl; - -/* - * ZSamplePosition enum - */ - -typedef enum ZSamplePosition { - Z_SAMPLE_CENTER = 0x00000000, - Z_SAMPLE_CENTROID = 0x00000001, -} ZSamplePosition; - -/* - * ZOrder enum - */ - -typedef enum ZOrder { - LATE_Z = 0x00000000, - EARLY_Z_THEN_LATE_Z = 0x00000001, - RE_Z = 0x00000002, - EARLY_Z_THEN_RE_Z = 0x00000003, -} ZOrder; - -/* - * ZpassControl enum - */ - -typedef enum ZpassControl { - ZPASS_DISABLE = 0x00000000, - ZPASS_SAMPLES = 0x00000001, - ZPASS_PIXELS = 0x00000002, -} ZpassControl; - -/* - * ZModeForce enum - */ - -typedef enum ZModeForce { - NO_FORCE = 0x00000000, - FORCE_EARLY_Z = 0x00000001, - FORCE_LATE_Z = 0x00000002, - FORCE_RE_Z = 0x00000003, -} ZModeForce; - -/* - * ZLimitSumm enum - */ - -typedef enum ZLimitSumm { - FORCE_SUMM_OFF = 0x00000000, - FORCE_SUMM_MINZ = 0x00000001, - FORCE_SUMM_MAXZ = 0x00000002, - FORCE_SUMM_BOTH = 0x00000003, -} ZLimitSumm; - -/* - * CompareFrag enum - */ - -typedef enum CompareFrag { - FRAG_NEVER = 0x00000000, - FRAG_LESS = 0x00000001, - FRAG_EQUAL = 0x00000002, - FRAG_LEQUAL = 0x00000003, - FRAG_GREATER = 0x00000004, - FRAG_NOTEQUAL = 0x00000005, - FRAG_GEQUAL = 0x00000006, - FRAG_ALWAYS = 0x00000007, -} CompareFrag; - -/* - * StencilOp enum - */ - -typedef enum StencilOp { - STENCIL_KEEP = 0x00000000, - STENCIL_ZERO = 0x00000001, - STENCIL_ONES = 0x00000002, - STENCIL_REPLACE_TEST = 0x00000003, - STENCIL_REPLACE_OP = 0x00000004, - STENCIL_ADD_CLAMP = 0x00000005, - STENCIL_SUB_CLAMP = 0x00000006, - STENCIL_INVERT = 0x00000007, - STENCIL_ADD_WRAP = 0x00000008, - STENCIL_SUB_WRAP = 0x00000009, - STENCIL_AND = 0x0000000a, - STENCIL_OR = 0x0000000b, - STENCIL_XOR = 0x0000000c, - STENCIL_NAND = 0x0000000d, - STENCIL_NOR = 0x0000000e, - STENCIL_XNOR = 0x0000000f, -} StencilOp; - -/* - * ConservativeZExport enum - */ - -typedef enum ConservativeZExport { - EXPORT_ANY_Z = 0x00000000, - EXPORT_LESS_THAN_Z = 0x00000001, - EXPORT_GREATER_THAN_Z = 0x00000002, - EXPORT_RESERVED = 0x00000003, -} ConservativeZExport; - -/* - * DbPSLControl enum - */ - -typedef enum DbPSLControl { - PSLC_AUTO = 0x00000000, - PSLC_ON_HANG_ONLY = 0x00000001, - PSLC_ASAP = 0x00000002, - PSLC_COUNTDOWN = 0x00000003, -} DbPSLControl; - -/* - * DbPRTFaultBehavior enum - */ - -typedef enum DbPRTFaultBehavior { - FAULT_ZERO = 0x00000000, - FAULT_ONE = 0x00000001, - FAULT_FAIL = 0x00000002, - FAULT_PASS = 0x00000003, -} DbPRTFaultBehavior; - -/* - * PerfCounter_Vals enum - */ - -typedef enum PerfCounter_Vals { - DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, - DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, - DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, - DB_PERF_SEL_SC_DB_tile_events = 0x00000003, - DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, - DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, - DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, - DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, - DB_PERF_SEL_hiz_qtiles_culled = 0x00000008, - DB_PERF_SEL_his_qtiles_culled = 0x00000009, - DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, - DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, - DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, - DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, - DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, - DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, - DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, - DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, - DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, - DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, - DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, - DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, - DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, - DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, - DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, - DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, - DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, - DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, - DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, - DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, - DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, - DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, - DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020, - DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021, - DB_PERF_SEL_DB_CB_tile_sends = 0x00000022, - DB_PERF_SEL_DB_CB_tile_busy = 0x00000023, - DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024, - DB_PERF_SEL_SX_DB_quad_sends = 0x00000025, - DB_PERF_SEL_SX_DB_quad_busy = 0x00000026, - DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027, - DB_PERF_SEL_SX_DB_quad_quads = 0x00000028, - DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029, - DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a, - DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b, - DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c, - DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d, - DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e, - DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f, - DB_PERF_SEL_tile_rd_sends = 0x00000030, - DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031, - DB_PERF_SEL_quad_rd_sends = 0x00000032, - DB_PERF_SEL_quad_rd_busy = 0x00000033, - DB_PERF_SEL_quad_rd_mi_stall = 0x00000034, - DB_PERF_SEL_quad_rd_rw_collision = 0x00000035, - DB_PERF_SEL_quad_rd_tag_stall = 0x00000036, - DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037, - DB_PERF_SEL_quad_rd_panic = 0x00000038, - DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039, - DB_PERF_SEL_quad_rdret_sends = 0x0000003a, - DB_PERF_SEL_quad_rdret_busy = 0x0000003b, - DB_PERF_SEL_tile_wr_sends = 0x0000003c, - DB_PERF_SEL_tile_wr_acks = 0x0000003d, - DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e, - DB_PERF_SEL_quad_wr_sends = 0x0000003f, - DB_PERF_SEL_quad_wr_busy = 0x00000040, - DB_PERF_SEL_quad_wr_mi_stall = 0x00000041, - DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042, - DB_PERF_SEL_quad_wr_acks = 0x00000043, - DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044, - DB_PERF_SEL_Tile_Cache_misses = 0x00000045, - DB_PERF_SEL_Tile_Cache_hits = 0x00000046, - DB_PERF_SEL_Tile_Cache_flushes = 0x00000047, - DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048, - DB_PERF_SEL_Tile_Cache_starves = 0x00000049, - DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a, - DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b, - DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c, - DB_PERF_SEL_tcp_preloader_reads = 0x0000004d, - DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e, - DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f, - DB_PERF_SEL_tcp_preloader_flushes = 0x00000050, - DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051, - DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052, - DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053, - DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054, - DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055, - DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056, - DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057, - DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058, - DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059, - DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a, - DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b, - DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c, - DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d, - DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e, - DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f, - DB_PERF_SEL_Stencil_Cache_hits = 0x00000060, - DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061, - DB_PERF_SEL_Stencil_Cache_starves = 0x00000062, - DB_PERF_SEL_Stencil_Cache_frees = 0x00000063, - DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064, - DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065, - DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066, - DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067, - DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068, - DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069, - DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a, - DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b, - DB_PERF_SEL_Z_Cache_frees = 0x0000006c, - DB_PERF_SEL_Plane_Cache_misses = 0x0000006d, - DB_PERF_SEL_Plane_Cache_hits = 0x0000006e, - DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f, - DB_PERF_SEL_Plane_Cache_starves = 0x00000070, - DB_PERF_SEL_Plane_Cache_frees = 0x00000071, - DB_PERF_SEL_flush_expanded_stencil = 0x00000072, - DB_PERF_SEL_flush_compressed_stencil = 0x00000073, - DB_PERF_SEL_flush_single_stencil = 0x00000074, - DB_PERF_SEL_planes_flushed = 0x00000075, - DB_PERF_SEL_flush_1plane = 0x00000076, - DB_PERF_SEL_flush_2plane = 0x00000077, - DB_PERF_SEL_flush_3plane = 0x00000078, - DB_PERF_SEL_flush_4plane = 0x00000079, - DB_PERF_SEL_flush_5plane = 0x0000007a, - DB_PERF_SEL_flush_6plane = 0x0000007b, - DB_PERF_SEL_flush_7plane = 0x0000007c, - DB_PERF_SEL_flush_8plane = 0x0000007d, - DB_PERF_SEL_flush_9plane = 0x0000007e, - DB_PERF_SEL_flush_10plane = 0x0000007f, - DB_PERF_SEL_flush_11plane = 0x00000080, - DB_PERF_SEL_flush_12plane = 0x00000081, - DB_PERF_SEL_flush_13plane = 0x00000082, - DB_PERF_SEL_flush_14plane = 0x00000083, - DB_PERF_SEL_flush_15plane = 0x00000084, - DB_PERF_SEL_flush_16plane = 0x00000085, - DB_PERF_SEL_flush_expanded_z = 0x00000086, - DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087, - DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088, - DB_PERF_SEL_dk_tile_sends = 0x00000089, - DB_PERF_SEL_dk_tile_busy = 0x0000008a, - DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b, - DB_PERF_SEL_dk_tile_stalls = 0x0000008c, - DB_PERF_SEL_dk_squad_sends = 0x0000008d, - DB_PERF_SEL_dk_squad_busy = 0x0000008e, - DB_PERF_SEL_dk_squad_stalls = 0x0000008f, - DB_PERF_SEL_Op_Pipe_Busy = 0x00000090, - DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091, - DB_PERF_SEL_qc_busy = 0x00000092, - DB_PERF_SEL_qc_xfc = 0x00000093, - DB_PERF_SEL_qc_conflicts = 0x00000094, - DB_PERF_SEL_qc_full_stall = 0x00000095, - DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096, - DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097, - DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098, - DB_PERF_SEL_tl_busy = 0x00000099, - DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a, - DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b, - DB_PERF_SEL_tl_stencil_stall = 0x0000009c, - DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d, - DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e, - DB_PERF_SEL_tl_events = 0x0000009f, - DB_PERF_SEL_tl_summarize_squads = 0x000000a0, - DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1, - DB_PERF_SEL_tl_expand_squads = 0x000000a2, - DB_PERF_SEL_tl_preZ_squads = 0x000000a3, - DB_PERF_SEL_tl_postZ_squads = 0x000000a4, - DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5, - DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6, - DB_PERF_SEL_tl_tile_ops = 0x000000a7, - DB_PERF_SEL_tl_in_xfc = 0x000000a8, - DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9, - DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa, - DB_PERF_SEL_tl_out_xfc = 0x000000ab, - DB_PERF_SEL_tl_out_squads = 0x000000ac, - DB_PERF_SEL_zf_plane_multicycle = 0x000000ad, - DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae, - DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af, - DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0, - DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1, - DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2, - DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3, - DB_PERF_SEL_ts_tc_update_stall = 0x000000b4, - DB_PERF_SEL_sc_kick_start = 0x000000b5, - DB_PERF_SEL_sc_kick_end = 0x000000b6, - DB_PERF_SEL_clock_reg_active = 0x000000b7, - DB_PERF_SEL_clock_main_active = 0x000000b8, - DB_PERF_SEL_clock_mem_export_active = 0x000000b9, - DB_PERF_SEL_esr_ps_out_busy = 0x000000ba, - DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb, - DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc, - DB_PERF_SEL_etr_out_send = 0x000000bd, - DB_PERF_SEL_etr_out_busy = 0x000000be, - DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf, - DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0, - DB_PERF_SEL_etr_out_esr_stall = 0x000000c1, - DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2, - DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3, - DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4, - DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5, - DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6, - DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7, - DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8, - DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9, - DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca, - DB_PERF_SEL_postzl_se_busy = 0x000000cb, - DB_PERF_SEL_postzl_se_stall = 0x000000cc, - DB_PERF_SEL_postzl_partial_launch = 0x000000cd, - DB_PERF_SEL_postzl_full_launch = 0x000000ce, - DB_PERF_SEL_postzl_partial_waiting = 0x000000cf, - DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0, - DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1, - DB_PEFF_SEL_prezl_tile_mem_stall = 0x000000d2, - DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3, - DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4, - DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5, - DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6, - DB_PERF_SEL_mi_rdreq_busy = 0x000000d7, - DB_PERF_SEL_mi_rdreq_stall = 0x000000d8, - DB_PERF_SEL_mi_wrreq_busy = 0x000000d9, - DB_PERF_SEL_mi_wrreq_stall = 0x000000da, - DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db, - DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc, - DB_PERF_SEL_prezl_src_in_sends = 0x000000dd, - DB_PERF_SEL_prezl_src_in_stall = 0x000000de, - DB_PERF_SEL_prezl_src_in_squads = 0x000000df, - DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0, - DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1, - DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2, - DB_PERF_SEL_prezl_src_out_stall = 0x000000e3, - DB_PERF_SEL_postzl_src_in_sends = 0x000000e4, - DB_PERF_SEL_postzl_src_in_stall = 0x000000e5, - DB_PERF_SEL_postzl_src_in_squads = 0x000000e6, - DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7, - DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8, - DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9, - DB_PERF_SEL_postzl_src_out_stall = 0x000000ea, - DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb, - DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec, - DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed, - DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee, - DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef, - DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0, - DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1, - DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2, - DB_PERF_SEL_depth_bounds_qtiles_culled = 0x000000f3, - DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4, - DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5, - DB_PERF_SEL_flush_compressed = 0x000000f6, - DB_PERF_SEL_flush_plane_le4 = 0x000000f7, - DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8, - DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9, - DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa, - DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb, - DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc, - DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd, - DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe, - DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff, - DB_PERF_SEL_di_dt_stall = 0x00000100, - DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000101, - DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000102, - DB_PERF_SEL_SX_DB_quad_double_format = 0x00000103, - DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000104, - DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000105, - DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106, - DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107, - DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108, - DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109, - DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a, - DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b, - DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c, - DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d, - DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e, - DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f, - DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110, - DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111, - Spare_274 = 0x00000112, - Spare_275 = 0x00000113, - Spare_276 = 0x00000114, - Spare_277 = 0x00000115, - Spare_278 = 0x00000116, - Spare_279 = 0x00000117, - Spare_280 = 0x00000118, - Spare_281 = 0x00000119, - Spare_282 = 0x0000011a, - Spare_283 = 0x0000011b, - Spare_284 = 0x0000011c, - Spare_285 = 0x0000011d, - Spare_286 = 0x0000011e, - DB_PERF_SEL_DFSM_prez_killed_squad = 0x0000011f, - DB_PERF_SEL_DFSM_squads_in = 0x00000120, - DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000121, - DB_PERF_SEL_DFSM_quads_in = 0x00000122, - DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000123, - DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000124, - DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000125, - DB_PERF_SEL_DFSM_lit_samples_in = 0x00000126, - DB_PERF_SEL_DFSM_lit_samples_out = 0x00000127, - DB_PERF_SEL_DFSM_cycles_above_watermark = 0x00000128, - DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x00000129, - DB_PERF_SEL_DFSM_stalled_by_downstream = 0x0000012a, - DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000012b, - DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000012c, - DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000012d, - DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x0000012e, - DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x0000012f, - DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x00000130, - DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000131, - DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000132, - DB_PERF_SEL_unmapped_z_tile_culled = 0x00000133, - DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000134, - DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000135, - DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 0x00000136, - DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 0x00000137, - DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 0x00000138, - DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 0x00000139, - DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 0x0000013a, - DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 0x0000013b, - DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 0x0000013c, - DB_PERF_SEL_DB_CB_context_dones = 0x0000013d, - DB_PERF_SEL_DB_CB_eop_dones = 0x0000013e, - DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x0000013f, - DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x00000140, - DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000141, - DB_PERF_SEL_SC_DB_tile_backface = 0x00000142, - DB_PERF_SEL_SC_DB_quad_quads = 0x00000143, - DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000144, - DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000145, - DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000146, - DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000147, -} PerfCounter_Vals; - -/* - * RingCounterControl enum - */ - -typedef enum RingCounterControl { - COUNTER_RING_SPLIT = 0x00000000, - COUNTER_RING_0 = 0x00000001, - COUNTER_RING_1 = 0x00000002, -} RingCounterControl; - -/* - * DbMemArbWatermarks enum - */ - -typedef enum DbMemArbWatermarks { - TRANSFERRED_64_BYTES = 0x00000000, - TRANSFERRED_128_BYTES = 0x00000001, - TRANSFERRED_256_BYTES = 0x00000002, - TRANSFERRED_512_BYTES = 0x00000003, - TRANSFERRED_1024_BYTES = 0x00000004, - TRANSFERRED_2048_BYTES = 0x00000005, - TRANSFERRED_4096_BYTES = 0x00000006, - TRANSFERRED_8192_BYTES = 0x00000007, -} DbMemArbWatermarks; - -/* - * DFSMFlushEvents enum - */ - -typedef enum DFSMFlushEvents { - DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000, - DB_FLUSH_AND_INV_DB_META = 0x00000001, - DB_CACHE_FLUSH = 0x00000002, - DB_CACHE_FLUSH_TS = 0x00000003, - DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004, - DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005, - DB_VPORT_CHANGED_EVENT = 0x00000006, - DB_CONTEXT_DONE_EVENT = 0x00000007, - DB_BREAK_BATCH_EVENT = 0x00000008, - DB_PSINVOKE_CHANGE_EVENT = 0x00000009, -} DFSMFlushEvents; - -/* - * PixelPipeCounterId enum - */ - -typedef enum PixelPipeCounterId { - PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, - PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, - PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, - PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, - PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004, - PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005, - PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006, - PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007, -} PixelPipeCounterId; - -/* - * PixelPipeStride enum - */ - -typedef enum PixelPipeStride { - PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, - PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, - PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, - PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, -} PixelPipeStride; - -/******************************************************* - * TA Enums - *******************************************************/ - -/* - * TEX_BORDER_COLOR_TYPE enum - */ - -typedef enum TEX_BORDER_COLOR_TYPE { - TEX_BorderColor_TransparentBlack = 0x00000000, - TEX_BorderColor_OpaqueBlack = 0x00000001, - TEX_BorderColor_OpaqueWhite = 0x00000002, - TEX_BorderColor_Register = 0x00000003, -} TEX_BORDER_COLOR_TYPE; - -/* - * TEX_BC_SWIZZLE enum - */ - -typedef enum TEX_BC_SWIZZLE { - TEX_BC_Swizzle_XYZW = 0x00000000, - TEX_BC_Swizzle_XWYZ = 0x00000001, - TEX_BC_Swizzle_WZYX = 0x00000002, - TEX_BC_Swizzle_WXYZ = 0x00000003, - TEX_BC_Swizzle_ZYXW = 0x00000004, - TEX_BC_Swizzle_YXWZ = 0x00000005, -} TEX_BC_SWIZZLE; - -/* - * TEX_CHROMA_KEY enum - */ - -typedef enum TEX_CHROMA_KEY { - TEX_ChromaKey_Disabled = 0x00000000, - TEX_ChromaKey_Kill = 0x00000001, - TEX_ChromaKey_Blend = 0x00000002, - TEX_ChromaKey_RESERVED_3 = 0x00000003, -} TEX_CHROMA_KEY; - -/* - * TEX_CLAMP enum - */ - -typedef enum TEX_CLAMP { - TEX_Clamp_Repeat = 0x00000000, - TEX_Clamp_Mirror = 0x00000001, - TEX_Clamp_ClampToLast = 0x00000002, - TEX_Clamp_MirrorOnceToLast = 0x00000003, - TEX_Clamp_ClampHalfToBorder = 0x00000004, - TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, - TEX_Clamp_ClampToBorder = 0x00000006, - TEX_Clamp_MirrorOnceToBorder = 0x00000007, -} TEX_CLAMP; - -/* - * TEX_COORD_TYPE enum - */ - -typedef enum TEX_COORD_TYPE { - TEX_CoordType_Unnormalized = 0x00000000, - TEX_CoordType_Normalized = 0x00000001, -} TEX_COORD_TYPE; - -/* - * TEX_DEPTH_COMPARE_FUNCTION enum - */ - -typedef enum TEX_DEPTH_COMPARE_FUNCTION { - TEX_DepthCompareFunction_Never = 0x00000000, - TEX_DepthCompareFunction_Less = 0x00000001, - TEX_DepthCompareFunction_Equal = 0x00000002, - TEX_DepthCompareFunction_LessEqual = 0x00000003, - TEX_DepthCompareFunction_Greater = 0x00000004, - TEX_DepthCompareFunction_NotEqual = 0x00000005, - TEX_DepthCompareFunction_GreaterEqual = 0x00000006, - TEX_DepthCompareFunction_Always = 0x00000007, -} TEX_DEPTH_COMPARE_FUNCTION; - -/* - * TEX_DIM enum - */ - -typedef enum TEX_DIM { - TEX_Dim_1D = 0x00000000, - TEX_Dim_2D = 0x00000001, - TEX_Dim_3D = 0x00000002, - TEX_Dim_CubeMap = 0x00000003, - TEX_Dim_1DArray = 0x00000004, - TEX_Dim_2DArray = 0x00000005, - TEX_Dim_2D_MSAA = 0x00000006, - TEX_Dim_2DArray_MSAA = 0x00000007, -} TEX_DIM; - -/* - * TEX_FORMAT_COMP enum - */ - -typedef enum TEX_FORMAT_COMP { - TEX_FormatComp_Unsigned = 0x00000000, - TEX_FormatComp_Signed = 0x00000001, - TEX_FormatComp_UnsignedBiased = 0x00000002, - TEX_FormatComp_RESERVED_3 = 0x00000003, -} TEX_FORMAT_COMP; - -/* - * TEX_MAX_ANISO_RATIO enum - */ - -typedef enum TEX_MAX_ANISO_RATIO { - TEX_MaxAnisoRatio_1to1 = 0x00000000, - TEX_MaxAnisoRatio_2to1 = 0x00000001, - TEX_MaxAnisoRatio_4to1 = 0x00000002, - TEX_MaxAnisoRatio_8to1 = 0x00000003, - TEX_MaxAnisoRatio_16to1 = 0x00000004, - TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, - TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, - TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, -} TEX_MAX_ANISO_RATIO; - -/* - * TEX_MIP_FILTER enum - */ - -typedef enum TEX_MIP_FILTER { - TEX_MipFilter_None = 0x00000000, - TEX_MipFilter_Point = 0x00000001, - TEX_MipFilter_Linear = 0x00000002, - TEX_MipFilter_Point_Aniso_Adj = 0x00000003, -} TEX_MIP_FILTER; - -/* - * TEX_REQUEST_SIZE enum - */ - -typedef enum TEX_REQUEST_SIZE { - TEX_RequestSize_32B = 0x00000000, - TEX_RequestSize_64B = 0x00000001, - TEX_RequestSize_128B = 0x00000002, - TEX_RequestSize_2X64B = 0x00000003, -} TEX_REQUEST_SIZE; - -/* - * TEX_SAMPLER_TYPE enum - */ - -typedef enum TEX_SAMPLER_TYPE { - TEX_SamplerType_Invalid = 0x00000000, - TEX_SamplerType_Valid = 0x00000001, -} TEX_SAMPLER_TYPE; - -/* - * TEX_XY_FILTER enum - */ - -typedef enum TEX_XY_FILTER { - TEX_XYFilter_Point = 0x00000000, - TEX_XYFilter_Linear = 0x00000001, - TEX_XYFilter_AnisoPoint = 0x00000002, - TEX_XYFilter_AnisoLinear = 0x00000003, -} TEX_XY_FILTER; - -/* - * TEX_Z_FILTER enum - */ - -typedef enum TEX_Z_FILTER { - TEX_ZFilter_None = 0x00000000, - TEX_ZFilter_Point = 0x00000001, - TEX_ZFilter_Linear = 0x00000002, - TEX_ZFilter_RESERVED_3 = 0x00000003, -} TEX_Z_FILTER; - -/* - * VTX_CLAMP enum - */ - -typedef enum VTX_CLAMP { - VTX_Clamp_ClampToZero = 0x00000000, - VTX_Clamp_ClampToNAN = 0x00000001, -} VTX_CLAMP; - -/* - * VTX_FETCH_TYPE enum - */ - -typedef enum VTX_FETCH_TYPE { - VTX_FetchType_VertexData = 0x00000000, - VTX_FetchType_InstanceData = 0x00000001, - VTX_FetchType_NoIndexOffset = 0x00000002, - VTX_FetchType_RESERVED_3 = 0x00000003, -} VTX_FETCH_TYPE; - -/* - * VTX_FORMAT_COMP_ALL enum - */ - -typedef enum VTX_FORMAT_COMP_ALL { - VTX_FormatCompAll_Unsigned = 0x00000000, - VTX_FormatCompAll_Signed = 0x00000001, -} VTX_FORMAT_COMP_ALL; - -/* - * VTX_MEM_REQUEST_SIZE enum - */ - -typedef enum VTX_MEM_REQUEST_SIZE { - VTX_MemRequestSize_32B = 0x00000000, - VTX_MemRequestSize_64B = 0x00000001, -} VTX_MEM_REQUEST_SIZE; - -/* - * TVX_DATA_FORMAT enum - */ - -typedef enum TVX_DATA_FORMAT { - TVX_FMT_INVALID = 0x00000000, - TVX_FMT_8 = 0x00000001, - TVX_FMT_4_4 = 0x00000002, - TVX_FMT_3_3_2 = 0x00000003, - TVX_FMT_RESERVED_4 = 0x00000004, - TVX_FMT_16 = 0x00000005, - TVX_FMT_16_FLOAT = 0x00000006, - TVX_FMT_8_8 = 0x00000007, - TVX_FMT_5_6_5 = 0x00000008, - TVX_FMT_6_5_5 = 0x00000009, - TVX_FMT_1_5_5_5 = 0x0000000a, - TVX_FMT_4_4_4_4 = 0x0000000b, - TVX_FMT_5_5_5_1 = 0x0000000c, - TVX_FMT_32 = 0x0000000d, - TVX_FMT_32_FLOAT = 0x0000000e, - TVX_FMT_16_16 = 0x0000000f, - TVX_FMT_16_16_FLOAT = 0x00000010, - TVX_FMT_8_24 = 0x00000011, - TVX_FMT_8_24_FLOAT = 0x00000012, - TVX_FMT_24_8 = 0x00000013, - TVX_FMT_24_8_FLOAT = 0x00000014, - TVX_FMT_10_11_11 = 0x00000015, - TVX_FMT_10_11_11_FLOAT = 0x00000016, - TVX_FMT_11_11_10 = 0x00000017, - TVX_FMT_11_11_10_FLOAT = 0x00000018, - TVX_FMT_2_10_10_10 = 0x00000019, - TVX_FMT_8_8_8_8 = 0x0000001a, - TVX_FMT_10_10_10_2 = 0x0000001b, - TVX_FMT_X24_8_32_FLOAT = 0x0000001c, - TVX_FMT_32_32 = 0x0000001d, - TVX_FMT_32_32_FLOAT = 0x0000001e, - TVX_FMT_16_16_16_16 = 0x0000001f, - TVX_FMT_16_16_16_16_FLOAT = 0x00000020, - TVX_FMT_RESERVED_33 = 0x00000021, - TVX_FMT_32_32_32_32 = 0x00000022, - TVX_FMT_32_32_32_32_FLOAT = 0x00000023, - TVX_FMT_RESERVED_36 = 0x00000024, - TVX_FMT_1 = 0x00000025, - TVX_FMT_1_REVERSED = 0x00000026, - TVX_FMT_GB_GR = 0x00000027, - TVX_FMT_BG_RG = 0x00000028, - TVX_FMT_32_AS_8 = 0x00000029, - TVX_FMT_32_AS_8_8 = 0x0000002a, - TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b, - TVX_FMT_8_8_8 = 0x0000002c, - TVX_FMT_16_16_16 = 0x0000002d, - TVX_FMT_16_16_16_FLOAT = 0x0000002e, - TVX_FMT_32_32_32 = 0x0000002f, - TVX_FMT_32_32_32_FLOAT = 0x00000030, - TVX_FMT_BC1 = 0x00000031, - TVX_FMT_BC2 = 0x00000032, - TVX_FMT_BC3 = 0x00000033, - TVX_FMT_BC4 = 0x00000034, - TVX_FMT_BC5 = 0x00000035, - TVX_FMT_APC0 = 0x00000036, - TVX_FMT_APC1 = 0x00000037, - TVX_FMT_APC2 = 0x00000038, - TVX_FMT_APC3 = 0x00000039, - TVX_FMT_APC4 = 0x0000003a, - TVX_FMT_APC5 = 0x0000003b, - TVX_FMT_APC6 = 0x0000003c, - TVX_FMT_APC7 = 0x0000003d, - TVX_FMT_CTX1 = 0x0000003e, - TVX_FMT_RESERVED_63 = 0x0000003f, -} TVX_DATA_FORMAT; - -/* - * TVX_DST_SEL enum - */ - -typedef enum TVX_DST_SEL { - TVX_DstSel_X = 0x00000000, - TVX_DstSel_Y = 0x00000001, - TVX_DstSel_Z = 0x00000002, - TVX_DstSel_W = 0x00000003, - TVX_DstSel_0f = 0x00000004, - TVX_DstSel_1f = 0x00000005, - TVX_DstSel_RESERVED_6 = 0x00000006, - TVX_DstSel_Mask = 0x00000007, -} TVX_DST_SEL; - -/* - * TVX_ENDIAN_SWAP enum - */ - -typedef enum TVX_ENDIAN_SWAP { - TVX_EndianSwap_None = 0x00000000, - TVX_EndianSwap_8in16 = 0x00000001, - TVX_EndianSwap_8in32 = 0x00000002, - TVX_EndianSwap_8in64 = 0x00000003, -} TVX_ENDIAN_SWAP; - -/* - * TVX_INST enum - */ - -typedef enum TVX_INST { - TVX_Inst_NormalVertexFetch = 0x00000000, - TVX_Inst_SemanticVertexFetch = 0x00000001, - TVX_Inst_RESERVED_2 = 0x00000002, - TVX_Inst_LD = 0x00000003, - TVX_Inst_GetTextureResInfo = 0x00000004, - TVX_Inst_GetNumberOfSamples = 0x00000005, - TVX_Inst_GetLOD = 0x00000006, - TVX_Inst_GetGradientsH = 0x00000007, - TVX_Inst_GetGradientsV = 0x00000008, - TVX_Inst_SetTextureOffsets = 0x00000009, - TVX_Inst_KeepGradients = 0x0000000a, - TVX_Inst_SetGradientsH = 0x0000000b, - TVX_Inst_SetGradientsV = 0x0000000c, - TVX_Inst_Pass = 0x0000000d, - TVX_Inst_GetBufferResInfo = 0x0000000e, - TVX_Inst_RESERVED_15 = 0x0000000f, - TVX_Inst_Sample = 0x00000010, - TVX_Inst_Sample_L = 0x00000011, - TVX_Inst_Sample_LB = 0x00000012, - TVX_Inst_Sample_LZ = 0x00000013, - TVX_Inst_Sample_G = 0x00000014, - TVX_Inst_Gather4 = 0x00000015, - TVX_Inst_Sample_G_LB = 0x00000016, - TVX_Inst_Gather4_O = 0x00000017, - TVX_Inst_Sample_C = 0x00000018, - TVX_Inst_Sample_C_L = 0x00000019, - TVX_Inst_Sample_C_LB = 0x0000001a, - TVX_Inst_Sample_C_LZ = 0x0000001b, - TVX_Inst_Sample_C_G = 0x0000001c, - TVX_Inst_Gather4_C = 0x0000001d, - TVX_Inst_Sample_C_G_LB = 0x0000001e, - TVX_Inst_Gather4_C_O = 0x0000001f, -} TVX_INST; - -/* - * TVX_NUM_FORMAT_ALL enum - */ - -typedef enum TVX_NUM_FORMAT_ALL { - TVX_NumFormatAll_Norm = 0x00000000, - TVX_NumFormatAll_Int = 0x00000001, - TVX_NumFormatAll_Scaled = 0x00000002, - TVX_NumFormatAll_RESERVED_3 = 0x00000003, -} TVX_NUM_FORMAT_ALL; - -/* - * TVX_SRC_SEL enum - */ - -typedef enum TVX_SRC_SEL { - TVX_SrcSel_X = 0x00000000, - TVX_SrcSel_Y = 0x00000001, - TVX_SrcSel_Z = 0x00000002, - TVX_SrcSel_W = 0x00000003, - TVX_SrcSel_0f = 0x00000004, - TVX_SrcSel_1f = 0x00000005, -} TVX_SRC_SEL; - -/* - * TVX_SRF_MODE_ALL enum - */ - -typedef enum TVX_SRF_MODE_ALL { - TVX_SRFModeAll_ZCMO = 0x00000000, - TVX_SRFModeAll_NZ = 0x00000001, -} TVX_SRF_MODE_ALL; - -/* - * TVX_TYPE enum - */ - -typedef enum TVX_TYPE { - TVX_Type_InvalidTextureResource = 0x00000000, - TVX_Type_InvalidVertexBuffer = 0x00000001, - TVX_Type_ValidTextureResource = 0x00000002, - TVX_Type_ValidVertexBuffer = 0x00000003, -} TVX_TYPE; - -/******************************************************* - * PA Enums - *******************************************************/ - -/* - * SU_PERFCNT_SEL enum - */ - -typedef enum SU_PERFCNT_SEL { - PERF_PAPC_PASX_REQ = 0x00000000, - PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, - PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, - PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, - PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, - PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, - PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, - PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, - PERF_PAPC_PA_INPUT_PRIM = 0x00000008, - PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, - PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, - PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, - PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, - PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, - PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, - PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, - PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, - PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, - PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, - PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, - PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, - PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, - PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, - PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, - PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, - PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, - PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, - PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, - PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, - PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, - PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, - PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, - PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, - PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, - PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, - PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, - PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, - PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, - PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, - PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, - PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, - PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, - PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, - PERF_PAPC_SU_INPUT_PRIM = 0x00000031, - PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, - PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, - PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, - PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, - PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, - PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, - PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, - PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, - PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, - PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, - PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, - PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, - PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, - PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, - PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, - PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, - PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, - PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, - PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, - PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, - PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, - PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, - PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, - PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, - PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, - PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, - PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, - PERF_PAPC_PASX_REC_IDLE = 0x00000050, - PERF_PAPC_PASX_REC_BUSY = 0x00000051, - PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, - PERF_PAPC_PASX_REC_STALLED = 0x00000053, - PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, - PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, - PERF_PAPC_CCGSM_IDLE = 0x00000056, - PERF_PAPC_CCGSM_BUSY = 0x00000057, - PERF_PAPC_CCGSM_STALLED = 0x00000058, - PERF_PAPC_CLPRIM_IDLE = 0x00000059, - PERF_PAPC_CLPRIM_BUSY = 0x0000005a, - PERF_PAPC_CLPRIM_STALLED = 0x0000005b, - PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, - PERF_PAPC_CLIPSM_IDLE = 0x0000005d, - PERF_PAPC_CLIPSM_BUSY = 0x0000005e, - PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, - PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, - PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, - PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, - PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, - PERF_PAPC_CLIPGA_IDLE = 0x00000064, - PERF_PAPC_CLIPGA_BUSY = 0x00000065, - PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, - PERF_PAPC_CLIPGA_STALLED = 0x00000067, - PERF_PAPC_CLIP_IDLE = 0x00000068, - PERF_PAPC_CLIP_BUSY = 0x00000069, - PERF_PAPC_SU_IDLE = 0x0000006a, - PERF_PAPC_SU_BUSY = 0x0000006b, - PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, - PERF_PAPC_SU_STALLED_SC = 0x0000006d, - PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, - PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, - PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, - PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, - PERF_PAPC_PASX_SE0_REQ = 0x00000072, - PERF_PAPC_PASX_SE1_REQ = 0x00000073, - PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, - PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, - PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, - PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, - PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, - PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, - PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, - PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, - PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, - PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, - PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, - PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, - PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, - PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, - PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, - PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, - PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, - PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, - PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, - PERF_PAPC_SU_CULLED_PRIM = 0x00000087, - PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088, - PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089, - PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a, - PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b, - PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c, - PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d, - PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e, - PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f, - PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090, - PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091, - PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092, - PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093, - PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094, - PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095, - PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096, - PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097, - PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098, - PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099, - PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a, - PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b, - PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c, - PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d, - PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e, - PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f, - PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0, - PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1, - PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2, - PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3, - PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4, - PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5, - PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 0x000000a6, - PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 0x000000a7, - PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 0x000000a8, - PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000a9, - PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000aa, - PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ab, - PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ac, - PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ad, - PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ae, - PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000af, - PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b0, - PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1 = 0x000000b1, - PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT = 0x000000b2, - PERF_UTC_SIDEBAND_DRIVER_BUSY = 0x000000b3, - PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1 = 0x000000b4, - PERF_UTC_INDEX_DRIVER_STALLING_CLIENT = 0x000000b5, - PERF_UTC_INDEX_DRIVER_BUSY = 0x000000b6, - PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1 = 0x000000b7, - PERF_UTC_POSITION_DRIVER_STALLING_CLIENT = 0x000000b8, - PERF_UTC_POSITION_DRIVER_BUSY = 0x000000b9, - PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1 = 0x000000ba, - PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER = 0x000000bb, - PERF_UTC_SIDEBAND_RECEIVER_BUSY = 0x000000bc, - PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1 = 0x000000bd, - PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER = 0x000000be, - PERF_UTC_INDEX_RECEIVER_BUSY = 0x000000bf, - PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1 = 0x000000c0, - PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER = 0x000000c1, - PERF_UTC_POSITION_RECEIVER_BUSY = 0x000000c2, - PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE = 0x000000c3, - PERF_TCIF_STALLING_CLIENT_NO_CREDITS = 0x000000c4, - PERF_TCIF_BUSY = 0x000000c5, - PERF_TCIF_SIDEBAND_RDREQ = 0x000000c6, - PERF_TCIF_INDEX_RDREQ = 0x000000c7, - PERF_TCIF_POSITION_RDREQ = 0x000000c8, - PERF_SIDEBAND_WAITING_ON_UTCL1 = 0x000000c9, - PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY = 0x000000ca, - PERF_WRITING_TO_SIDEBAND_MEMORY = 0x000000cb, - PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD = 0x000000cc, - PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD = 0x000000cd, - PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD = 0x000000ce, - PERF_SIDEBAND_WAITING_ON_RETURNED_DATA = 0x000000cf, - PERF_SIDEBAND_POP_BIT_FIFO_FULL = 0x000000d0, - PERF_SIDEBAND_FIFO_VMID_FIFO_FULL = 0x000000d1, - PERF_SIDEBAND_INVALID_REFETCH = 0x000000d2, - PERF_SIDEBAND_QUALIFIED_BUSY = 0x000000d3, - PERF_SIDEBAND_QUALIFIED_STARVED = 0x000000d4, - PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_ = 0x000000d5, - PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_ = 0x000000d6, - PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_ = 0x000000d7, - PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_ = 0x000000d8, - PERF_INDEX_REQUEST_WAITING_ON_TOKENS = 0x000000d9, - PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO = 0x000000da, - PERF_INDEX_REQUEST_QUALIFIED_BUSY = 0x000000db, - PERF_INDEX_REQUEST_QUALIFIED_STARVED = 0x000000dc, - PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE = 0x000000dd, - PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO = 0x000000de, - PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE = 0x000000df, - PERF_INDEX_RECEIVE_QUALIFIED_BUSY = 0x000000e0, - PERF_INDEX_RECEIVE_QUALIFIED_STARVED = 0x000000e1, - PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE = 0x000000e2, - PERF_INDEX_RECEIVE_1_TO_7_VALID_DWORDS_THIS_CACHELINE = 0x000000e3, - PERF_INDEX_RECEIVE_8_TO_15_VALID_DWORDS_THIS_CACHELINE = 0x000000e4, - PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE = 0x000000e5, - PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x000000e6, - PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x000000e7, - PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO = 0x000000e8, - PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO = 0x000000e9, - PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO = 0x000000ea, - PERF_POS_REQ_STALLED_BY_NO_TOKENS = 0x000000eb, - PERF_POS_REQ_STALLED_BY_NO_PRIM = 0x000000ec, - PERF_POS_REQ_STALLED_BY_UTCL1 = 0x000000ed, - PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x000000ee, - PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x000000ef, - PERF_POS_REQ_QUALIFIED_BUSY = 0x000000f0, - PERF_POS_REQ_QUALIFIED_STARVED = 0x000000f1, - PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO = 0x000000f2, - PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO = 0x000000f3, - PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE = 0x000000f4, - PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE = 0x000000f5, - PERF_POS_RET_QUALIFIED_BUSY = 0x000000f6, - PERF_POS_RET_QUALIFIED_STARVED = 0x000000f7, - PERF_TC_LATENCY_BIN0 = 0x000000f8, - PERF_TC_LATENCY_BIN1 = 0x000000f9, - PERF_TC_LATENCY_BIN2 = 0x000000fa, - PERF_TC_LATENCY_BIN3 = 0x000000fb, - PERF_TC_LATENCY_BIN4 = 0x000000fc, - PERF_TC_LATENCY_BIN5 = 0x000000fd, - PERF_TC_LATENCY_BIN6 = 0x000000fe, - PERF_TC_LATENCY_BIN7 = 0x000000ff, - PERF_TC_STREAM0_DATA_AVAILABLE = 0x00000100, - PERF_TC_STREAM1_DATA_AVAILABLE = 0x00000101, - PERF_TC_STREAM2_DATA_AVAILABLE = 0x00000102, - PERF_PAWD_DEALLOC_FIFO_IS_FULL = 0x00000103, - PERF_PAWD_DEALLOC_WAITING_TO_BE_READ = 0x00000104, - PERF_SHOOTDOWN_WAIT_ON_UTCL1 = 0x00000105, - PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND = 0x00000106, - PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX = 0x00000107, - PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION = 0x00000108, - PERF_SHOOTDOWN_WAIT_ALL_CLEAN = 0x00000109, - PERF_SHOOTDOWN_WAIT_DEASSERT = 0x0000010a, - PERF_UTCL1_TRANSLATION_MISS_CLIENT0 = 0x0000010b, - PERF_UTCL1_TRANSLATION_MISS_CLIENT1 = 0x0000010c, - PERF_UTCL1_TRANSLATION_MISS_CLIENT2 = 0x0000010d, - PERF_UTCL1_PERMISSION_MISS_CLIENT0 = 0x0000010e, - PERF_UTCL1_PERMISSION_MISS_CLIENT1 = 0x0000010f, - PERF_UTCL1_PERMISSION_MISS_CLIENT2 = 0x00000110, - PERF_UTCL1_TRANSLATION_HIT_CLIENT0 = 0x00000111, - PERF_UTCL1_TRANSLATION_HIT_CLIENT1 = 0x00000112, - PERF_UTCL1_TRANSLATION_HIT_CLIENT2 = 0x00000113, - PERF_UTCL1_REQUEST_CLIENT0 = 0x00000114, - PERF_UTCL1_REQUEST_CLIENT1 = 0x00000115, - PERF_UTCL1_REQUEST_CLIENT2 = 0x00000116, - PERF_UTCL1_STALL_MISSFIFO_FULL = 0x00000117, - PERF_UTCL1_STALL_INFLIGHT_MAX = 0x00000118, - PERF_UTCL1_STALL_LRU_INFLIGHT = 0x00000119, - PERF_UTCL1_STALL_MULTI_MISS = 0x0000011a, - PERF_UTCL1_LFIFO_FULL = 0x0000011b, - PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0 = 0x0000011c, - PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1 = 0x0000011d, - PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2 = 0x0000011e, - PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x0000011f, - PERF_UTCL1_UTCL2_REQ = 0x00000120, - PERF_UTCL1_UTCL2_RET = 0x00000121, - PERF_UTCL1_UTCL2_INFLIGHT = 0x00000122, - PERF_CLIENT_UTCL1_INFLIGHT = 0x00000123, -} SU_PERFCNT_SEL; - -/* - * SC_PERFCNT_SEL enum - */ - -typedef enum SC_PERFCNT_SEL { - SC_SRPS_WINDOW_VALID = 0x00000000, - SC_PSSW_WINDOW_VALID = 0x00000001, - SC_TPQZ_WINDOW_VALID = 0x00000002, - SC_QZQP_WINDOW_VALID = 0x00000003, - SC_TRPK_WINDOW_VALID = 0x00000004, - SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, - SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, - SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, - SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, - SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, - SC_STARVED_BY_PA = 0x0000000a, - SC_STALLED_BY_PRIMFIFO = 0x0000000b, - SC_STALLED_BY_DB_TILE = 0x0000000c, - SC_STARVED_BY_DB_TILE = 0x0000000d, - SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, - SC_STALLED_BY_TILEFIFO = 0x0000000f, - SC_STALLED_BY_DB_QUAD = 0x00000010, - SC_STARVED_BY_DB_QUAD = 0x00000011, - SC_STALLED_BY_QUADFIFO = 0x00000012, - SC_STALLED_BY_BCI = 0x00000013, - SC_STALLED_BY_SPI = 0x00000014, - SC_SCISSOR_DISCARD = 0x00000015, - SC_BB_DISCARD = 0x00000016, - SC_SUPERTILE_COUNT = 0x00000017, - SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, - SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, - SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, - SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, - SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, - SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, - SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, - SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, - SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, - SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, - SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, - SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, - SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, - SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, - SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, - SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, - SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, - SC_TILE_PER_PRIM_H0 = 0x00000029, - SC_TILE_PER_PRIM_H1 = 0x0000002a, - SC_TILE_PER_PRIM_H2 = 0x0000002b, - SC_TILE_PER_PRIM_H3 = 0x0000002c, - SC_TILE_PER_PRIM_H4 = 0x0000002d, - SC_TILE_PER_PRIM_H5 = 0x0000002e, - SC_TILE_PER_PRIM_H6 = 0x0000002f, - SC_TILE_PER_PRIM_H7 = 0x00000030, - SC_TILE_PER_PRIM_H8 = 0x00000031, - SC_TILE_PER_PRIM_H9 = 0x00000032, - SC_TILE_PER_PRIM_H10 = 0x00000033, - SC_TILE_PER_PRIM_H11 = 0x00000034, - SC_TILE_PER_PRIM_H12 = 0x00000035, - SC_TILE_PER_PRIM_H13 = 0x00000036, - SC_TILE_PER_PRIM_H14 = 0x00000037, - SC_TILE_PER_PRIM_H15 = 0x00000038, - SC_TILE_PER_PRIM_H16 = 0x00000039, - SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, - SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, - SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, - SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, - SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, - SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, - SC_TILE_PER_SUPERTILE_H6 = 0x00000040, - SC_TILE_PER_SUPERTILE_H7 = 0x00000041, - SC_TILE_PER_SUPERTILE_H8 = 0x00000042, - SC_TILE_PER_SUPERTILE_H9 = 0x00000043, - SC_TILE_PER_SUPERTILE_H10 = 0x00000044, - SC_TILE_PER_SUPERTILE_H11 = 0x00000045, - SC_TILE_PER_SUPERTILE_H12 = 0x00000046, - SC_TILE_PER_SUPERTILE_H13 = 0x00000047, - SC_TILE_PER_SUPERTILE_H14 = 0x00000048, - SC_TILE_PER_SUPERTILE_H15 = 0x00000049, - SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, - SC_TILE_PICKED_H1 = 0x0000004b, - SC_TILE_PICKED_H2 = 0x0000004c, - SC_TILE_PICKED_H3 = 0x0000004d, - SC_TILE_PICKED_H4 = 0x0000004e, - SC_QZ0_TILE_COUNT = 0x0000004f, - SC_QZ1_TILE_COUNT = 0x00000050, - SC_QZ2_TILE_COUNT = 0x00000051, - SC_QZ3_TILE_COUNT = 0x00000052, - SC_QZ0_TILE_COVERED_COUNT = 0x00000053, - SC_QZ1_TILE_COVERED_COUNT = 0x00000054, - SC_QZ2_TILE_COVERED_COUNT = 0x00000055, - SC_QZ3_TILE_COVERED_COUNT = 0x00000056, - SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057, - SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00000058, - SC_QZ2_TILE_NOT_COVERED_COUNT = 0x00000059, - SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005a, - SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b, - SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c, - SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d, - SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e, - SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f, - SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060, - SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061, - SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062, - SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063, - SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064, - SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065, - SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066, - SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067, - SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068, - SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069, - SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a, - SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b, - SC_QZ1_QUAD_PER_TILE_H0 = 0x0000006c, - SC_QZ1_QUAD_PER_TILE_H1 = 0x0000006d, - SC_QZ1_QUAD_PER_TILE_H2 = 0x0000006e, - SC_QZ1_QUAD_PER_TILE_H3 = 0x0000006f, - SC_QZ1_QUAD_PER_TILE_H4 = 0x00000070, - SC_QZ1_QUAD_PER_TILE_H5 = 0x00000071, - SC_QZ1_QUAD_PER_TILE_H6 = 0x00000072, - SC_QZ1_QUAD_PER_TILE_H7 = 0x00000073, - SC_QZ1_QUAD_PER_TILE_H8 = 0x00000074, - SC_QZ1_QUAD_PER_TILE_H9 = 0x00000075, - SC_QZ1_QUAD_PER_TILE_H10 = 0x00000076, - SC_QZ1_QUAD_PER_TILE_H11 = 0x00000077, - SC_QZ1_QUAD_PER_TILE_H12 = 0x00000078, - SC_QZ1_QUAD_PER_TILE_H13 = 0x00000079, - SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007a, - SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007b, - SC_QZ1_QUAD_PER_TILE_H16 = 0x0000007c, - SC_QZ2_QUAD_PER_TILE_H0 = 0x0000007d, - SC_QZ2_QUAD_PER_TILE_H1 = 0x0000007e, - SC_QZ2_QUAD_PER_TILE_H2 = 0x0000007f, - SC_QZ2_QUAD_PER_TILE_H3 = 0x00000080, - SC_QZ2_QUAD_PER_TILE_H4 = 0x00000081, - SC_QZ2_QUAD_PER_TILE_H5 = 0x00000082, - SC_QZ2_QUAD_PER_TILE_H6 = 0x00000083, - SC_QZ2_QUAD_PER_TILE_H7 = 0x00000084, - SC_QZ2_QUAD_PER_TILE_H8 = 0x00000085, - SC_QZ2_QUAD_PER_TILE_H9 = 0x00000086, - SC_QZ2_QUAD_PER_TILE_H10 = 0x00000087, - SC_QZ2_QUAD_PER_TILE_H11 = 0x00000088, - SC_QZ2_QUAD_PER_TILE_H12 = 0x00000089, - SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008a, - SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008b, - SC_QZ2_QUAD_PER_TILE_H15 = 0x0000008c, - SC_QZ2_QUAD_PER_TILE_H16 = 0x0000008d, - SC_QZ3_QUAD_PER_TILE_H0 = 0x0000008e, - SC_QZ3_QUAD_PER_TILE_H1 = 0x0000008f, - SC_QZ3_QUAD_PER_TILE_H2 = 0x00000090, - SC_QZ3_QUAD_PER_TILE_H3 = 0x00000091, - SC_QZ3_QUAD_PER_TILE_H4 = 0x00000092, - SC_QZ3_QUAD_PER_TILE_H5 = 0x00000093, - SC_QZ3_QUAD_PER_TILE_H6 = 0x00000094, - SC_QZ3_QUAD_PER_TILE_H7 = 0x00000095, - SC_QZ3_QUAD_PER_TILE_H8 = 0x00000096, - SC_QZ3_QUAD_PER_TILE_H9 = 0x00000097, - SC_QZ3_QUAD_PER_TILE_H10 = 0x00000098, - SC_QZ3_QUAD_PER_TILE_H11 = 0x00000099, - SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009a, - SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009b, - SC_QZ3_QUAD_PER_TILE_H14 = 0x0000009c, - SC_QZ3_QUAD_PER_TILE_H15 = 0x0000009d, - SC_QZ3_QUAD_PER_TILE_H16 = 0x0000009e, - SC_QZ0_QUAD_COUNT = 0x0000009f, - SC_QZ1_QUAD_COUNT = 0x000000a0, - SC_QZ2_QUAD_COUNT = 0x000000a1, - SC_QZ3_QUAD_COUNT = 0x000000a2, - SC_P0_HIZ_TILE_COUNT = 0x000000a3, - SC_P1_HIZ_TILE_COUNT = 0x000000a4, - SC_P2_HIZ_TILE_COUNT = 0x000000a5, - SC_P3_HIZ_TILE_COUNT = 0x000000a6, - SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7, - SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8, - SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9, - SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa, - SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab, - SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac, - SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad, - SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae, - SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af, - SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0, - SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1, - SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2, - SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3, - SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4, - SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5, - SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6, - SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7, - SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000b8, - SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000b9, - SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000ba, - SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bb, - SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000bc, - SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000bd, - SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000be, - SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000bf, - SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c0, - SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c1, - SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c2, - SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c3, - SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c4, - SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c5, - SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000c6, - SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000c7, - SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000c8, - SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000c9, - SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ca, - SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cb, - SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000cc, - SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000cd, - SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000ce, - SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000cf, - SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d0, - SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d1, - SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d2, - SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d3, - SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d4, - SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d5, - SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000d6, - SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000d7, - SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000d8, - SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000d9, - SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000da, - SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000db, - SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000dc, - SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000dd, - SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000de, - SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000df, - SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e0, - SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e1, - SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e2, - SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e3, - SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e4, - SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e5, - SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000e6, - SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000e7, - SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000e8, - SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000e9, - SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ea, - SC_P0_HIZ_QUAD_COUNT = 0x000000eb, - SC_P1_HIZ_QUAD_COUNT = 0x000000ec, - SC_P2_HIZ_QUAD_COUNT = 0x000000ed, - SC_P3_HIZ_QUAD_COUNT = 0x000000ee, - SC_P0_DETAIL_QUAD_COUNT = 0x000000ef, - SC_P1_DETAIL_QUAD_COUNT = 0x000000f0, - SC_P2_DETAIL_QUAD_COUNT = 0x000000f1, - SC_P3_DETAIL_QUAD_COUNT = 0x000000f2, - SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3, - SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4, - SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5, - SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6, - SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, - SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, - SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, - SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, - SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, - SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, - SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, - SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, - SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, - SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000100, - SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000101, - SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000102, - SC_EARLYZ_QUAD_COUNT = 0x00000103, - SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104, - SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105, - SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106, - SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107, - SC_PKR_QUAD_PER_ROW_H1 = 0x00000108, - SC_PKR_QUAD_PER_ROW_H2 = 0x00000109, - SC_PKR_4X2_QUAD_SPLIT = 0x0000010a, - SC_PKR_4X2_FILL_QUAD = 0x0000010b, - SC_PKR_END_OF_VECTOR = 0x0000010c, - SC_PKR_CONTROL_XFER = 0x0000010d, - SC_PKR_DBHANG_FORCE_EOV = 0x0000010e, - SC_REG_SCLK_BUSY = 0x0000010f, - SC_GRP0_DYN_SCLK_BUSY = 0x00000110, - SC_GRP1_DYN_SCLK_BUSY = 0x00000111, - SC_GRP2_DYN_SCLK_BUSY = 0x00000112, - SC_GRP3_DYN_SCLK_BUSY = 0x00000113, - SC_GRP4_DYN_SCLK_BUSY = 0x00000114, - SC_PA0_SC_DATA_FIFO_RD = 0x00000115, - SC_PA0_SC_DATA_FIFO_WE = 0x00000116, - SC_PA1_SC_DATA_FIFO_RD = 0x00000117, - SC_PA1_SC_DATA_FIFO_WE = 0x00000118, - SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119, - SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a, - SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b, - SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c, - SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d, - SC_PS_ARB_SC_BUSY = 0x0000011e, - SC_PS_ARB_PA_SC_BUSY = 0x0000011f, - SC_PA2_SC_DATA_FIFO_RD = 0x00000120, - SC_PA2_SC_DATA_FIFO_WE = 0x00000121, - SC_PA3_SC_DATA_FIFO_RD = 0x00000122, - SC_PA3_SC_DATA_FIFO_WE = 0x00000123, - SC_PA_SC_DEALLOC_0_0_WE = 0x00000124, - SC_PA_SC_DEALLOC_0_1_WE = 0x00000125, - SC_PA_SC_DEALLOC_1_0_WE = 0x00000126, - SC_PA_SC_DEALLOC_1_1_WE = 0x00000127, - SC_PA_SC_DEALLOC_2_0_WE = 0x00000128, - SC_PA_SC_DEALLOC_2_1_WE = 0x00000129, - SC_PA_SC_DEALLOC_3_0_WE = 0x0000012a, - SC_PA_SC_DEALLOC_3_1_WE = 0x0000012b, - SC_PA0_SC_EOP_WE = 0x0000012c, - SC_PA0_SC_EOPG_WE = 0x0000012d, - SC_PA0_SC_EVENT_WE = 0x0000012e, - SC_PA1_SC_EOP_WE = 0x0000012f, - SC_PA1_SC_EOPG_WE = 0x00000130, - SC_PA1_SC_EVENT_WE = 0x00000131, - SC_PA2_SC_EOP_WE = 0x00000132, - SC_PA2_SC_EOPG_WE = 0x00000133, - SC_PA2_SC_EVENT_WE = 0x00000134, - SC_PA3_SC_EOP_WE = 0x00000135, - SC_PA3_SC_EOPG_WE = 0x00000136, - SC_PA3_SC_EVENT_WE = 0x00000137, - SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138, - SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x00000139, - SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013a, - SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013b, - SC_PS_ARB_EVENT_SYNC_POP = 0x0000013c, - SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x0000013d, - SC_PA0_SC_FPOV_WE = 0x0000013e, - SC_PA1_SC_FPOV_WE = 0x0000013f, - SC_PA2_SC_FPOV_WE = 0x00000140, - SC_PA3_SC_FPOV_WE = 0x00000141, - SC_PA0_SC_LPOV_WE = 0x00000142, - SC_PA1_SC_LPOV_WE = 0x00000143, - SC_PA2_SC_LPOV_WE = 0x00000144, - SC_PA3_SC_LPOV_WE = 0x00000145, - SC_SC_SPI_DEALLOC_0_0 = 0x00000146, - SC_SC_SPI_DEALLOC_0_1 = 0x00000147, - SC_SC_SPI_DEALLOC_0_2 = 0x00000148, - SC_SC_SPI_DEALLOC_1_0 = 0x00000149, - SC_SC_SPI_DEALLOC_1_1 = 0x0000014a, - SC_SC_SPI_DEALLOC_1_2 = 0x0000014b, - SC_SC_SPI_DEALLOC_2_0 = 0x0000014c, - SC_SC_SPI_DEALLOC_2_1 = 0x0000014d, - SC_SC_SPI_DEALLOC_2_2 = 0x0000014e, - SC_SC_SPI_DEALLOC_3_0 = 0x0000014f, - SC_SC_SPI_DEALLOC_3_1 = 0x00000150, - SC_SC_SPI_DEALLOC_3_2 = 0x00000151, - SC_SC_SPI_FPOV_0 = 0x00000152, - SC_SC_SPI_FPOV_1 = 0x00000153, - SC_SC_SPI_FPOV_2 = 0x00000154, - SC_SC_SPI_FPOV_3 = 0x00000155, - SC_SC_SPI_EVENT = 0x00000156, - SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157, - SC_PS_TS_EVENT_FIFO_POP = 0x00000158, - SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159, - SC_PS_CTX_DONE_FIFO_POP = 0x0000015a, - SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015b, - SC_EOP_SYNC_WINDOW = 0x0000015c, - SC_PA0_SC_NULL_WE = 0x0000015d, - SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e, - SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x0000015f, - SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160, - SC_PA0_SC_DEALLOC_0_RD = 0x00000161, - SC_PA0_SC_DEALLOC_1_RD = 0x00000162, - SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000163, - SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000164, - SC_PA1_SC_DEALLOC_0_RD = 0x00000165, - SC_PA1_SC_DEALLOC_1_RD = 0x00000166, - SC_PA1_SC_NULL_WE = 0x00000167, - SC_PA1_SC_NULL_DEALLOC_WE = 0x00000168, - SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x00000169, - SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016a, - SC_PA2_SC_DEALLOC_0_RD = 0x0000016b, - SC_PA2_SC_DEALLOC_1_RD = 0x0000016c, - SC_PA2_SC_NULL_WE = 0x0000016d, - SC_PA2_SC_NULL_DEALLOC_WE = 0x0000016e, - SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x0000016f, - SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000170, - SC_PA3_SC_DEALLOC_0_RD = 0x00000171, - SC_PA3_SC_DEALLOC_1_RD = 0x00000172, - SC_PA3_SC_NULL_WE = 0x00000173, - SC_PA3_SC_NULL_DEALLOC_WE = 0x00000174, - SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175, - SC_PS_PA0_SC_FIFO_FULL = 0x00000176, - SC_PA0_PS_DATA_FULL_MINUS3 = 0x00000177, - SC_PS_PA1_SC_FIFO_EMPTY = 0x00000178, - SC_PS_PA1_SC_FIFO_FULL = 0x00000179, - SC_PA1_PS_DATA_FULL_MINUS3 = 0x0000017a, - SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017b, - SC_PS_PA2_SC_FIFO_FULL = 0x0000017c, - SC_PA2_PS_DATA_FULL_MINUS3 = 0x0000017d, - SC_PS_PA3_SC_FIFO_EMPTY = 0x0000017e, - SC_PS_PA3_SC_FIFO_FULL = 0x0000017f, - SC_PA3_PS_DATA_FULL_MINUS3 = 0x00000180, - SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000181, - SC_BUSY_CNT_NOT_ZERO = 0x00000182, - SC_BM_BUSY = 0x00000183, - SC_BACKEND_BUSY = 0x00000184, - SC_SCF_SCB_INTERFACE_BUSY = 0x00000185, - SC_SCB_BUSY = 0x00000186, - SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187, - SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188, - SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189, - SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a, - SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b, - SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c, - SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d, - SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e, - SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f, - SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190, - SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191, - SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192, - SC_PBB_BUSY = 0x00000193, - SC_PBB_BUSY_AND_NO_SENDS = 0x00000194, - SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195, - SC_PBB_NUM_BINS = 0x00000196, - SC_PBB_END_OF_BIN = 0x00000197, - SC_PBB_END_OF_BATCH = 0x00000198, - SC_PBB_PRIMBIN_PROCESSED = 0x00000199, - SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a, - SC_PBB_NONBINNED_PRIM = 0x0000019b, - SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c, - SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d, - SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e, - SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f, - SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0, - SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1, - SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2, - SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3, - SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4, - SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5, - SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6, - SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001a7, - SC_POPS_FORCE_EOV = 0x000001a8, - SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 0x000001a9, - SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 0x000001aa, - SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 0x000001ab, - SC_FULL_FULL_QUAD = 0x000001ac, - SC_FULL_HALF_QUAD = 0x000001ad, - SC_FULL_QTR_QUAD = 0x000001ae, - SC_HALF_FULL_QUAD = 0x000001af, - SC_HALF_HALF_QUAD = 0x000001b0, - SC_HALF_QTR_QUAD = 0x000001b1, - SC_QTR_FULL_QUAD = 0x000001b2, - SC_QTR_HALF_QUAD = 0x000001b3, - SC_QTR_QTR_QUAD = 0x000001b4, - SC_GRP5_DYN_SCLK_BUSY = 0x000001b5, - SC_GRP6_DYN_SCLK_BUSY = 0x000001b6, - SC_GRP7_DYN_SCLK_BUSY = 0x000001b7, - SC_GRP8_DYN_SCLK_BUSY = 0x000001b8, - SC_GRP9_DYN_SCLK_BUSY = 0x000001b9, - SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba, - SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb, - SC_PK_BUSY = 0x000001bc, - SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd, - SC_PK_DEALLOC_WAVE_BREAK = 0x000001be, - SC_SPI_SEND = 0x000001bf, - SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0, - SC_SPI_CREDIT_AT_MAX = 0x000001c1, - SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2, - SC_BCI_SEND = 0x000001c3, - SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4, - SC_BCI_CREDIT_AT_MAX = 0x000001c5, - SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6, - SC_SPIBC_FULL_FREEZE = 0x000001c7, - SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8, - SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9, - SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da, - SC_DB0_TILE_INTERFACE_BUSY = 0x000001db, - SC_DB0_TILE_INTERFACE_SEND = 0x000001dc, - SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd, - SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001de, - SC_DB0_TILE_INTERFACE_SEND_SOP = 0x000001df, - SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0, - SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1, - SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2, - SC_DB1_TILE_INTERFACE_BUSY = 0x000001e3, - SC_DB1_TILE_INTERFACE_SEND = 0x000001e4, - SC_DB1_TILE_INTERFACE_SEND_EVENT = 0x000001e5, - SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001e6, - SC_DB1_TILE_INTERFACE_SEND_SOP = 0x000001e7, - SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e8, - SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e9, - SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea, -} SC_PERFCNT_SEL; - -/* - * SePairXsel enum - */ - -typedef enum SePairXsel { - RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, - RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 0x00000004, -} SePairXsel; - -/* - * SePairYsel enum - */ - -typedef enum SePairYsel { - RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, - RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 0x00000004, -} SePairYsel; - -/* - * SePairMap enum - */ - -typedef enum SePairMap { - RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, - RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, - RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, - RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, -} SePairMap; - -/* - * SeXsel enum - */ - -typedef enum SeXsel { - RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, - RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 0x00000004, -} SeXsel; - -/* - * SeYsel enum - */ - -typedef enum SeYsel { - RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, - RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 0x00000004, -} SeYsel; - -/* - * SeMap enum - */ - -typedef enum SeMap { - RASTER_CONFIG_SE_MAP_0 = 0x00000000, - RASTER_CONFIG_SE_MAP_1 = 0x00000001, - RASTER_CONFIG_SE_MAP_2 = 0x00000002, - RASTER_CONFIG_SE_MAP_3 = 0x00000003, -} SeMap; - -/* - * ScXsel enum - */ - -typedef enum ScXsel { - RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, -} ScXsel; - -/* - * ScYsel enum - */ - -typedef enum ScYsel { - RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, - RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, - RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, - RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, -} ScYsel; - -/* - * ScMap enum - */ - -typedef enum ScMap { - RASTER_CONFIG_SC_MAP_0 = 0x00000000, - RASTER_CONFIG_SC_MAP_1 = 0x00000001, - RASTER_CONFIG_SC_MAP_2 = 0x00000002, - RASTER_CONFIG_SC_MAP_3 = 0x00000003, -} ScMap; - -/* - * PkrXsel2 enum - */ - -typedef enum PkrXsel2 { - RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, - RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, - RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, - RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, -} PkrXsel2; - -/* - * PkrXsel enum - */ - -typedef enum PkrXsel { - RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, - RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, - RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, - RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, -} PkrXsel; - -/* - * PkrYsel enum - */ - -typedef enum PkrYsel { - RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, - RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, - RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, - RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, -} PkrYsel; - -/* - * PkrMap enum - */ - -typedef enum PkrMap { - RASTER_CONFIG_PKR_MAP_0 = 0x00000000, - RASTER_CONFIG_PKR_MAP_1 = 0x00000001, - RASTER_CONFIG_PKR_MAP_2 = 0x00000002, - RASTER_CONFIG_PKR_MAP_3 = 0x00000003, -} PkrMap; - -/* - * RbXsel enum - */ - -typedef enum RbXsel { - RASTER_CONFIG_RB_XSEL_0 = 0x00000000, - RASTER_CONFIG_RB_XSEL_1 = 0x00000001, -} RbXsel; - -/* - * RbYsel enum - */ - -typedef enum RbYsel { - RASTER_CONFIG_RB_YSEL_0 = 0x00000000, - RASTER_CONFIG_RB_YSEL_1 = 0x00000001, -} RbYsel; - -/* - * RbXsel2 enum - */ - -typedef enum RbXsel2 { - RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, - RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, - RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, - RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, -} RbXsel2; - -/* - * RbMap enum - */ - -typedef enum RbMap { - RASTER_CONFIG_RB_MAP_0 = 0x00000000, - RASTER_CONFIG_RB_MAP_1 = 0x00000001, - RASTER_CONFIG_RB_MAP_2 = 0x00000002, - RASTER_CONFIG_RB_MAP_3 = 0x00000003, -} RbMap; - -/* - * BinningMode enum - */ - -typedef enum BinningMode { - BINNING_ALLOWED = 0x00000000, - FORCE_BINNING_ON = 0x00000001, - DISABLE_BINNING_USE_NEW_SC = 0x00000002, - DISABLE_BINNING_USE_LEGACY_SC = 0x00000003, -} BinningMode; - -/* - * BinSizeExtend enum - */ - -typedef enum BinSizeExtend { - BIN_SIZE_32_PIXELS = 0x00000000, - BIN_SIZE_64_PIXELS = 0x00000001, - BIN_SIZE_128_PIXELS = 0x00000002, - BIN_SIZE_256_PIXELS = 0x00000003, - BIN_SIZE_512_PIXELS = 0x00000004, -} BinSizeExtend; - -/* - * BinEventCntl enum - */ - -typedef enum BinEventCntl { - BINNER_BREAK_BATCH = 0x00000000, - BINNER_PIPELINE = 0x00000001, - BINNER_DROP = 0x00000002, - BINNER_DROP_ASSERT = 0x00000003, -} BinEventCntl; - -/* - * CovToShaderSel enum - */ - -typedef enum CovToShaderSel { - INPUT_COVERAGE = 0x00000000, - INPUT_INNER_COVERAGE = 0x00000001, - INPUT_DEPTH_COVERAGE = 0x00000002, - RAW = 0x00000003, -} CovToShaderSel; - -/* - * ScUncertaintyRegionMode enum - */ - -typedef enum ScUncertaintyRegionMode { - SC_HALF_LSB = 0x00000000, - SC_LSB_ONE_SIDED = 0x00000001, - SC_LSB_TWO_SIDED = 0x00000002, -} ScUncertaintyRegionMode; - -/******************************************************* - * RMI Enums - *******************************************************/ - -/* - * RMIPerfSel enum - */ - -typedef enum RMIPerfSel { - RMI_PERF_SEL_NONE = 0x00000000, - RMI_PERF_SEL_BUSY = 0x00000001, - RMI_PERF_SEL_REG_CLK_VLD = 0x00000002, - RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003, - RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004, - RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005, - RMI_PERF_SEL_PERF_WINDOW = 0x00000006, - RMI_PERF_SEL_EVENT_SEND = 0x00000007, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017, - RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028, - RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029, - RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a, - RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b, - RMI_PERF_SEL_UTCL1_TRANSLATION_HIT = 0x0000002c, - RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002d, - RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002e, - RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002f, - RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x00000030, - RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000031, - RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000032, - RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000033, - RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000034, - RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000035, - RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000036, - RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 0x00000037, - RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000038, - RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000039, - RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x0000003a, - RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003b, - RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003c, - RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003d, - RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003e, - RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003f, - RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 0x00000040, - RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000041, - RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000042, - RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000043, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000044, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000045, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000046, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000047, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000048, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000049, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x0000004a, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004b, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004c, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004d, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004e, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004f, - RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x00000050, - RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000051, - RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000052, - RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 0x00000053, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000054, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000055, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000056, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000057, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000058, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000059, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x0000005a, - RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005b, - RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005c, - RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005d, - RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005e, - RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005f, - RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x00000060, - RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000061, - RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000062, - RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000063, - RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000064, - RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000065, - RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000066, - RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000067, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000068, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000069, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x0000006a, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006b, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006c, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006d, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006e, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006f, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x00000070, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000071, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000072, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000073, - RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000074, - RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 0x00000075, - RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 0x00000076, - RMI_PERF_SEL_RB_RMI_WR_IDLE = 0x00000077, - RMI_PERF_SEL_RB_RMI_WR_STARVE = 0x00000078, - RMI_PERF_SEL_RB_RMI_WR_STALL = 0x00000079, - RMI_PERF_SEL_RB_RMI_WR_BUSY = 0x0000007a, - RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 0x0000007b, - RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 0x0000007c, - RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 0x0000007d, - RMI_PERF_SEL_RB_RMI_RD_IDLE = 0x0000007e, - RMI_PERF_SEL_RB_RMI_RD_STARVE = 0x0000007f, - RMI_PERF_SEL_RB_RMI_RD_STALL = 0x00000080, - RMI_PERF_SEL_RB_RMI_RD_BUSY = 0x00000081, - RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 0x00000082, - RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 0x00000083, - RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 0x00000084, - RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000085, - RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000086, - RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000087, - RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000088, - RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000089, - RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x0000008a, - RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000008b, - RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000008c, - RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000008d, - RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000008e, - RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000008f, - RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x00000090, - RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000091, - RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000092, - RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000093, - RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000094, - RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000095, - RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000096, - RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000097, - RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000098, - RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000099, - RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 0x0000009a, - RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 0x0000009b, - RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 0x0000009c, - RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 0x0000009d, - RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 0x0000009e, - RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x0000009f, - RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x000000a0, - RMI_PERF_SEL_UTCL1_BUSY = 0x000000a1, - RMI_PERF_SEL_RMI_UTC_REQ = 0x000000a2, - RMI_PERF_SEL_RMI_UTC_BUSY = 0x000000a3, - RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x000000a4, - RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2 = 0x000000a5, - RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x000000a6, - RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x000000a7, - RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x000000a8, - RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS = 0x000000a9, - RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x000000aa, - RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x000000ab, - RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x000000ac, - RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x000000ad, - RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x000000ae, - RMI_PERF_SEL_XNACK_FIFO_FULL = 0x000000af, - RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x000000b0, - RMI_PERF_SEL_LAT_FIFO_FULL = 0x000000b1, - RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x000000b2, - RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x000000b3, - RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x000000b4, - RMI_PERF_SEL_PRT_FIFO_REQ = 0x000000b5, - RMI_PERF_SEL_PRT_FIFO_BUSY = 0x000000b6, - RMI_PERF_SEL_TCIW_REQ = 0x000000b7, - RMI_PERF_SEL_TCIW_BUSY = 0x000000b8, - RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000b9, - RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000ba, - RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000bb, - RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000bc, - RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000bd, - RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000be, - RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000bf, - RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000c0, - RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000c1, - RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000c2, - RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000c3, - RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000c4, - RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000c5, - RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000c6, - RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000c7, - RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000c8, - RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000c9, - RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000ca, - RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000cb, - RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000cc, - RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000cd, - RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000ce, - RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000cf, - RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000d0, - RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000d1, - RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000d2, - RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000d3, - RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC = 0x000000d4, - RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000d5, - RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000d6, - RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000d7, - RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000d8, - RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000d9, - RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000da, - RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000db, - RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000dc, - RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000dd, - RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000de, - RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000df, - RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000e0, - RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000e1, - RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000e2, - RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000e3, - RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000e4, - RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000e5, - RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000e6, - RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000e7, - RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000e8, - RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000e9, - RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000ea, - RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000eb, - RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000ec, - RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000ed, - RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000ee, - RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000ef, - RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000f0, - RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000f1, - RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000f2, - RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000f3, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000f4, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000f5, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000f6, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000f7, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000f8, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000f9, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000fa, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000fb, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000fc, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000fd, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000fe, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000ff, - RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x00000100, -} RMIPerfSel; - -/******************************************************* - * DBGU_GFX Enums - *******************************************************/ - -/******************************************************* - * GRBM_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * GDS_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * RLC_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * CB_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * PA_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * PC_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * SX_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * SC_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * WD_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * IA_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * VGT_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * SPI_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * CPC_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * CPG_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * CPF_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * BCI_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * RMI_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * DB_DEBUGBUS Enums - *******************************************************/ - -/******************************************************* - * ATCL2 Enums - *******************************************************/ - -/******************************************************* - * ATCL2PFCNTR Enums - *******************************************************/ - -/******************************************************* - * ATCL2PFCNTL Enums - *******************************************************/ - -/******************************************************* - * VML2PF Enums - *******************************************************/ - -/******************************************************* - * VML2VC Enums - *******************************************************/ - -/******************************************************* - * VML2PL Enums - *******************************************************/ - -/******************************************************* - * VML2PR Enums - *******************************************************/ - -/******************************************************* - * VMSHAREDHV Enums - *******************************************************/ - -/******************************************************* - * VMSHAREDPF Enums - *******************************************************/ - -/******************************************************* - * VMSHAREDVC Enums - *******************************************************/ - -/******************************************************* - * GC_EA Enums - *******************************************************/ - -} // gfx9 -} // pm4_profile - -#endif /*_greenland_ENUM_HEADER*/ diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_mask.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_mask.h deleted file mode 100644 index 66bd9deeb6..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_mask.h +++ /dev/null @@ -1,63332 +0,0 @@ -#if !defined(_greenland_MASK_HEADER) -#define _greenland_MASK_HEADER -/* -* greenland_mask.h -* -* Register Spec Release: -* -* -* (c) 2000 ATI Technologies Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against -* inadvertent publication and does not imply publication or any waiver -* of confidentiality. The year included in the foregoing notice is the -* year of creation of the work. -* -*/ - -namespace pm4_profile { -namespace gfx9 { - -// ATC_ATS_CNTL -#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L -#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L -#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L -#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L -#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L -#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L -#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L -#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00c00000L - -// ATC_ATS_DEBUG -#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x00000001L -#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x00000002L -#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x00000004L -#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x00000020L -#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x00000040L -#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x00000080L -#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x00000100L -#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x00000200L -#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x00003c00L -#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x00004000L -#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x00008000L -#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x00010000L -#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x00020000L -#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00040000L -#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x00080000L -#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x00100000L -#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x00200000L -#define ATC_ATS_DEBUG__DISABLE_MULTIPLE_INVALIDATIONS_MASK 0x00400000L -#define ATC_ATS_DEBUG__DROP_PAGE_REQUEST_WHEN_FULL_MASK 0x00800000L -#define ATC_ATS_DEBUG__EFFECTIVE_TRANS_WORK_QUEUE_SIZE_MASK 0x07000000L -#define ATC_ATS_DEBUG__EFFECTIVE_PR_WORK_QUEUE_SIZE_MASK 0x78000000L -#define ATC_ATS_DEBUG__DISABLE_VMID16_PASID_MAPPING_MASK 0x80000000L - -// ATC_ATS_FAULT_DEBUG -#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000001L -#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x00000002L - -// ATC_ATS_STATUS -#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L -#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L -#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L -#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L -#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001c0L - -// ATC_ATS_FAULT_CNTL -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001ffL -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007fc00L -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000L - -// ATC_ATS_FAULT_STATUS_INFO -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001ffL -#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007c00L -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L -#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00f80000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0f000000L - -// ATC_ATS_FAULT_STATUS_ADDR -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffffL - -// ATC_ATS_DEFAULT_PAGE_LOW -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffffL - -// ATC_TRANS_FAULT_RSPCNTRL -#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L - -// ATC_ATS_FAULT_STATUS_INFO2 -#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L -#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001eL -#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003e00L - -// ATHUB_MISC_CNTL -#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000fc0L -#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L -#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L -#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L -#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07e00000L -#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L -#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L - -// ATC_VMID_PASID_MAPPING_UPDATE_STATUS -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L - -// ATC_VMID0_PASID_MAPPING -#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID1_PASID_MAPPING -#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID2_PASID_MAPPING -#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID3_PASID_MAPPING -#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID4_PASID_MAPPING -#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID5_PASID_MAPPING -#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID6_PASID_MAPPING -#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID7_PASID_MAPPING -#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID8_PASID_MAPPING -#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID9_PASID_MAPPING -#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID10_PASID_MAPPING -#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID11_PASID_MAPPING -#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID12_PASID_MAPPING -#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID13_PASID_MAPPING -#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID14_PASID_MAPPING -#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID15_PASID_MAPPING -#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_ATS_VMID_STATUS -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L -#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L -#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L -#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L -#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L -#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L -#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L -#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L -#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L -#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L -#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L -#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L -#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L -#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L -#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L -#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L -#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L - -// ATC_ATS_GFX_ATCL2_STATUS -#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L - -// ATC_PERFCOUNTER0_CFG -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000ffL -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0f000000L -#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L - -// ATC_PERFCOUNTER1_CFG -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000ffL -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0f000000L -#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L - -// ATC_PERFCOUNTER2_CFG -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000ffL -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0f000000L -#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L - -// ATC_PERFCOUNTER3_CFG -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000ffL -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0f000000L -#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L - -// ATC_PERFCOUNTER_RSLT_CNTL -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000fL -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000ff00L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00ff0000L -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - -// ATC_PERFCOUNTER_LO -#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffffL - -// ATC_PERFCOUNTER_HI -#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000ffffL -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000L - -// ATHUB_PCIE_ATS_CNTL -#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001f0000L -#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_PASID_CNTL -#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L -#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L -#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L - -// ATHUB_PCIE_PAGE_REQ_CNTL -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L - -// ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC -#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffffL - -// ATHUB_COMMAND -#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L - -// ATHUB_PCIE_ATS_CNTL_VF_0 -#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_1 -#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_2 -#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_3 -#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_4 -#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_5 -#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_6 -#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_7 -#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_8 -#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_9 -#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_10 -#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_11 -#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_12 -#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_13 -#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_14 -#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_PCIE_ATS_CNTL_VF_15 -#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L - -// ATHUB_MEM_POWER_LS -#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL -#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L - -// ATS_IH_CREDIT -#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00ff0000L - -// ATHUB_IH_CREDIT -#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00ff0000L - -// ATC_VMID16_PASID_MAPPING -#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID17_PASID_MAPPING -#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID18_PASID_MAPPING -#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID19_PASID_MAPPING -#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID20_PASID_MAPPING -#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID21_PASID_MAPPING -#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID22_PASID_MAPPING -#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID23_PASID_MAPPING -#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID24_PASID_MAPPING -#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID25_PASID_MAPPING -#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID26_PASID_MAPPING -#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID27_PASID_MAPPING -#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID28_PASID_MAPPING -#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID29_PASID_MAPPING -#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID30_PASID_MAPPING -#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_VMID31_PASID_MAPPING -#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000ffffL -#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L - -// ATC_ATS_MMHUB_ATCL2_STATUS -#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L - -// ATHUB_SHARED_VIRT_RESET_REQ -#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000ffffL -#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L - -// ATHUB_SHARED_ACTIVE_FCN_ID -#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000fL -#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L - -// ATC_ATS_SDPPORT_CNTL -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001e00L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L - -// ATC_ATS_DEBUG2 -#define ATC_ATS_DEBUG2__PRI_STOP_TIME_MASK 0x0000000fL -#define ATC_ATS_DEBUG2__MAPPING_MULTIPLE_INVALIDATE_ALL_UTCL2_MASK 0x00000010L -#define ATC_ATS_DEBUG2__MAPPING_DIFF_SINGLE_INVALIDATE_ALL_UTCL2_MASK 0x00000020L -#define ATC_ATS_DEBUG2__SNAPSHOT_FOR_WQ_MASK 0x00000040L -#define ATC_ATS_DEBUG2__MAPPING_SAVE_MODE_MASK 0x00000080L -#define ATC_ATS_DEBUG2__HOST_TRANS_MISS_MODE_MASK 0x00000100L -#define ATC_ATS_DEBUG2__LOG_NONFLUSH_TYPE_INVALIDATION_MASK 0x00000200L -#define ATC_ATS_DEBUG2__ALWAYS_BUSY_MASK 0x00000400L -#define ATC_ATS_DEBUG2__DISABLE_LOG_FUNCTION_MASK 0x00000800L -#define ATC_ATS_DEBUG2__DISABLE_PRI_RESET_WHEN_FAILURE_MASK 0x00001000L -#define ATC_ATS_DEBUG2__TRANS_RET_SNOOP_CNTL_MASK 0x00006000L -#define ATC_ATS_DEBUG2__EFFECTIVE_LOG_FIFO_DEPTH_MASK 0x0f000000L -#define ATC_ATS_DEBUG2__FAULT_ON_NOENOUGH_PERMISSIONS_MASK 0x10000000L - -// ATC_ATS_VMID_SNAPSHOT_GFX_STAT -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L - -// ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L - -// XPB_RTR_SRC_APRTR0 -#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR1 -#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR2 -#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR3 -#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR4 -#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR5 -#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR6 -#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR7 -#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR8 -#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_SRC_APRTR9 -#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7fffffffL - -// XPB_XDMA_RTR_SRC_APRTR0 -#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7fffffffL - -// XPB_XDMA_RTR_SRC_APRTR1 -#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7fffffffL - -// XPB_XDMA_RTR_SRC_APRTR2 -#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7fffffffL - -// XPB_XDMA_RTR_SRC_APRTR3 -#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7fffffffL - -// XPB_RTR_DEST_MAP0 -#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP1 -#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP2 -#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP3 -#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP4 -#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP5 -#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP6 -#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP7 -#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP8 -#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000L - -// XPB_RTR_DEST_MAP9 -#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00f00000L -#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L -#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000L - -// XPB_XDMA_RTR_DEST_MAP0 -#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L -#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L - -// XPB_XDMA_RTR_DEST_MAP1 -#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L -#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L - -// XPB_XDMA_RTR_DEST_MAP2 -#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L -#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L - -// XPB_XDMA_RTR_DEST_MAP3 -#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L -#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L - -// XPB_CLG_CFG0 -#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_CFG1 -#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_CFG2 -#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_CFG3 -#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_CFG4 -#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_CFG5 -#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_CFG6 -#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_CFG7 -#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000fL -#define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L -#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003c00L -#define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003c000L - -// XPB_CLG_EXTRA -#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003fL -#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007c0L -#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L -#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L -#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001f8000L -#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03e00000L -#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L -#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L - -// XPB_CLG_EXTRA_MSK -#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003fL -#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007c0L -#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001f800L -#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003e0000L - -// XPB_LB_ADDR -#define XPB_LB_ADDR__CMP0_MASK 0x000003ffL -#define XPB_LB_ADDR__MASK0_MASK 0x000ffc00L -#define XPB_LB_ADDR__CMP1_MASK 0x03f00000L -#define XPB_LB_ADDR__MASK1_MASK 0xfc000000L - -// XPB_WCB_STS -#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000ffffL -#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007f0000L -#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000L - -// XPB_HST_CFG -#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L - -// XPB_P2P_BAR_CFG -#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000fL -#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L -#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L -#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L -#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L -#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L -#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L -#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L -#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L - -// XPB_P2P_BAR0 -#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR0__VALID_MASK 0x00001000L -#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR1 -#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR1__VALID_MASK 0x00001000L -#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR2 -#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR2__VALID_MASK 0x00001000L -#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR3 -#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR3__VALID_MASK 0x00001000L -#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR4 -#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR4__VALID_MASK 0x00001000L -#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR5 -#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR5__VALID_MASK 0x00001000L -#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR6 -#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR6__VALID_MASK 0x00001000L -#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR7 -#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000fL -#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000f0L -#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR7__VALID_MASK 0x00001000L -#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR_SETUP -#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000ffL -#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000f00L -#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L -#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000L - -// XPB_P2P_BAR_DEBUG -#define XPB_P2P_BAR_DEBUG__SEL_MASK 0x000000ffL -#define XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0x00000f00L -#define XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0x0000f000L - -// XPB_P2P_BAR_DELTA_ABOVE -#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000ffL -#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0fffff00L - -// XPB_P2P_BAR_DELTA_BELOW -#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000ffL -#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0fffff00L - -// XPB_PEER_SYS_BAR0 -#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR1 -#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR2 -#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR3 -#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR4 -#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR5 -#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR6 -#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR7 -#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR8 -#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xfffffffeL - -// XPB_PEER_SYS_BAR9 -#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xfffffffeL - -// XPB_XDMA_PEER_SYS_BAR0 -#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xfffffffeL - -// XPB_XDMA_PEER_SYS_BAR1 -#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xfffffffeL - -// XPB_XDMA_PEER_SYS_BAR2 -#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xfffffffeL - -// XPB_XDMA_PEER_SYS_BAR3 -#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xfffffffeL - -// XPB_CLK_GAT -#define XPB_CLK_GAT__ONDLY_MASK 0x0000003fL -#define XPB_CLK_GAT__OFFDLY_MASK 0x00000fc0L -#define XPB_CLK_GAT__RDYDLY_MASK 0x0003f000L -#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L -#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L - -// XPB_INTF_CFG -#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000ffL -#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000ff00L -#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007f0000L -#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L -#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L -#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L -#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L -#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L -#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L -#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L -#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L - -// XPB_INTF_STS -#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000ffL -#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007f00L -#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L -#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L -#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L -#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L -#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07f80000L - -// XPB_PIPE_STS -#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L -#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000feL -#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007f00L -#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L -#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L -#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L -#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L -#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L -#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L -#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L -#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L -#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L -#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000L - -// XPB_SUB_CTRL -#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L -#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L -#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L -#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L -#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L -#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L -#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L -#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L -#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L -#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L -#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L -#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L -#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L -#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L -#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L -#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L -#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L -#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L -#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L -#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L - -// XPB_MAP_INVERT_FLUSH_NUM_LSB -#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000ffffL - -// XPB_PERF_KNOBS -#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003fL -#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000fc0L -#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003f000L - -// XPB_STICKY -#define XPB_STICKY__BITS_MASK 0xffffffffL - -// XPB_STICKY_W1C -#define XPB_STICKY_W1C__BITS_MASK 0xffffffffL - -// XPB_MISC_CFG -#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000ffL -#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000ff00L -#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00ff0000L -#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000L -#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L - -// XPB_INTF_CFG2 -#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000ffL - -// XPB_CLG_EXTRA_RD -#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003fL -#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007c0L -#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L -#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L -#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001f8000L -#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03e00000L -#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L -#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L - -// XPB_CLG_EXTRA_MSK_RD -#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003fL -#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007c0L -#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001f800L -#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003e0000L - -// XPB_CLG_GFX_MATCH -#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003fL -#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000fc0L -#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003f000L -#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00fc0000L -#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L -#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L -#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L -#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L - -// XPB_CLG_GFX_MATCH_MSK -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003fL -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000fc0L -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003f000L -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00fc0000L - -// XPB_CLG_MM_MATCH -#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003fL -#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000fc0L -#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003f000L -#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00fc0000L -#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L -#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L -#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L -#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L - -// XPB_CLG_MM_MATCH_MSK -#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003fL -#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000fc0L -#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003f000L -#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00fc0000L - -// XPB_CLG_GFX_UNITID_MAPPING0 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_GFX_UNITID_MAPPING1 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_GFX_UNITID_MAPPING2 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_GFX_UNITID_MAPPING3 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_GFX_UNITID_MAPPING4 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_GFX_UNITID_MAPPING5 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_GFX_UNITID_MAPPING6 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_GFX_UNITID_MAPPING7 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_MM_UNITID_MAPPING0 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_MM_UNITID_MAPPING1 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_MM_UNITID_MAPPING2 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001c0L - -// XPB_CLG_MM_UNITID_MAPPING3 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001fL -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001c0L - -// RPB_PASSPW_CONF -#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L -#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L -#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L -#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L -#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L -#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L -#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L -#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L - -// RPB_BLOCKLEVEL_CONF -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L -#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000cL -#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L -#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000c0L -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000c00L -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L - -// RPB_SECLEVEL_CONF -#define RPB_SECLEVEL_CONF__ATC_SECLEVEL_MASK 0x00000007L - -// RPB_TAG_CONF -#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000ffL -#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000ff00L -#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00ff0000L - -// RPB_DBG1 -#define RPB_DBG1__RPB_IO_RD_MASK 0x000000ffL -#define RPB_DBG1__RPB_OUTSTANDING_RD_32B_MASK 0x000fff00L -#define RPB_DBG1__DEBUG_BITS_MASK 0xfff00000L - -// RPB_EFF_CNTL -#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000ffL -#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000ff00L - -// RPB_ARB_CNTL -#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000ffL -#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000ff00L -#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00ff0000L -#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L -#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L - -// RPB_ARB_CNTL2 -#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000ffL -#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000ff00L -#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00ff0000L - -// RPB_BIF_CNTL -#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000ffL -#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000ff00L -#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L -#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L -#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L -#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07f80000L -#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L -#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L -#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L -#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L - -// RPB_WR_SWITCH_CNTL -#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007fL -#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003f80L -#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001fc000L -#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0fe00000L -#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L - -// RPB_WR_COMBINE_CNTL -#define RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000003L -#define RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x0000003cL -#define RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000040L - -// RPB_RD_SWITCH_CNTL -#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007fL -#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003f80L -#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001fc000L -#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0fe00000L -#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L - -// RPB_CID_QUEUE_WR -#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001fL -#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007e0L -#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L -#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L -#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L -#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L - -// RPB_CID_QUEUE_RD -#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001fL -#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007e0L -#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L -#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001c000L - -// RPB_PERF_COUNTER_CNTL -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L -#define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L -#define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L -#define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L -#define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001e0L -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003e00L -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007c000L -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00f80000L -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000L - -// RPB_PERF_COUNTER_STATUS -#define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffffL - -// RPB_CID_QUEUE_EX -#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L -#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001feL - -// RPB_CID_QUEUE_EX_DATA -#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000ffffL -#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000L - -// RPB_SWITCH_CNTL2 -#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007fL -#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003f80L -#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001fc000L -#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0fe00000L - -// RPB_DEINTRLV_COMBINE_CNTL -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000fL -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L -#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L - -// RPB_VC_SWITCH_RDWR -#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L -#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003fcL -#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003fc00L - -// RPB_PERFCOUNTER_LO -#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffffL - -// RPB_PERFCOUNTER_HI -#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000ffffL -#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000L - -// RPB_PERFCOUNTER0_CFG -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000ffL -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0f000000L -#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L - -// RPB_PERFCOUNTER1_CFG -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000ffL -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0f000000L -#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L - -// RPB_PERFCOUNTER2_CFG -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000ffL -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0f000000L -#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L - -// RPB_PERFCOUNTER3_CFG -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000ffL -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0f000000L -#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L - -// RPB_PERFCOUNTER_RSLT_CNTL -#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000fL -#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000ff00L -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00ff0000L -#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - -// RPB_MISC_CG -#define RPB_MISC_CG__ONDLY_MASK 0x0000003fL -#define RPB_MISC_CG__OFFDLY_MASK 0x00000fc0L -#define RPB_MISC_CG__RDYDLY_MASK 0x0003f000L -#define RPB_MISC_CG__ENABLE_MASK 0x00040000L -#define RPB_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L -#define RPB_MISC_CG__PG_EN_MASK 0x00100000L -#define RPB_MISC_CG__PG_IDLE_CYCLE_MASK 0x3fe00000L - -// RPB_RD_QUEUE_CNTL -#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L -#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L -#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L -#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L -#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003e0L -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000fc00L -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001f0000L -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07e00000L - -// RPB_RD_QUEUE_CNTL2 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001fL -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007e0L -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000f800L -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003f0000L - -// RPB_WR_QUEUE_CNTL -#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L -#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L -#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L -#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L -#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003e0L -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000fc00L -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001f0000L -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07e00000L - -// RPB_WR_QUEUE_CNTL2 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001fL -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007e0L -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000f800L -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003f0000L - -// RPB_EA_QUEUE_WR -#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001fL -#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000e0L -#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L -#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L - -// RPB_ATS_CNTL -#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L -#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L -#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007cL -#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007f80L -#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L -#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L -#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L -#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7e000000L - -// RPB_ATS_CNTL2 -#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003fL -#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000fc0L -#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L -#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L -#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000c0000L - -// RPB_SDPPORT_CNTL -#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L -#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L -#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003c0L -#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L -#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L -#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000f0000L -#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L -#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L - -// RSMU_HCID_GENERIC -#define RSMU_HCID_GENERIC__RSMU_HCID_HwRev_MASK 0x0000003fL -#define RSMU_HCID_GENERIC__RSMU_HCID_HwMinVer_MASK 0x00001fc0L -#define RSMU_HCID_GENERIC__RSMU_HCID_HwMajVer_MASK 0x000fe000L -#define RSMU_HCID_GENERIC__RSMU_HCID_HwID_MASK 0xfff00000L - -// RSMU_SIID_GENERIC -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfRev_MASK 0x0000003fL -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfMinVer_MASK 0x00001fc0L -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfMajVer_MASK 0x000fe000L -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfID_MASK 0xfff00000L - -// RSMU_DBG_MUX_CONTROL_GENERIC -#define RSMU_DBG_MUX_CONTROL_GENERIC__RSMU_DBG_MUX_SELECT_MASK 0x000000ffL - -// RSMU_SW_MMIO_PUB_IND_ADDR_0_GENERIC -#define RSMU_SW_MMIO_PUB_IND_ADDR_0_GENERIC__RSMU_SW_MMIO_PUB_IND_ADDR_0_MASK 0xffffffffL - -// RSMU_SW_MMIO_PUB_IND_DATA_0_GENERIC -#define RSMU_SW_MMIO_PUB_IND_DATA_0_GENERIC__RSMU_SW_MMIO_PUB_IND_DATA_0_MASK 0xffffffffL - -// RSMU_SW_MMIO_PUB_IND_ADDR_1_GENERIC -#define RSMU_SW_MMIO_PUB_IND_ADDR_1_GENERIC__RSMU_SW_MMIO_PUB_IND_ADDR_1_MASK 0xffffffffL - -// RSMU_SW_MMIO_PUB_IND_DATA_1_GENERIC -#define RSMU_SW_MMIO_PUB_IND_DATA_1_GENERIC__RSMU_SW_MMIO_PUB_IND_DATA_1_MASK 0xffffffffL - -// RSMU_SOFT_RESETB_GENERIC -#define RSMU_SOFT_RESETB_GENERIC__RSMU_SOFT_RESETB_MASK 0x00000003L -#define RSMU_SOFT_RESETB_GENERIC__RSMU_MASTER_SOFT_RESET_FENCE_ENABLE_MASK 0x0000000cL -#define RSMU_SOFT_RESETB_GENERIC__RSMU_SLAVE_SOFT_RESET_TIMEOUT_ENABLE_MASK 0x00000030L - -// RSMU_PGFSM_CONTROL_GENERIC -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_SW_CONTROL_MASK 0x00000001L -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_CMD_MASK 0x0000000eL -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_ADDR_MASK 0x000000f0L -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_SELECT_MASK 0x0000ff00L - -// RSMU_PGFSM_WR_DATA_GENERIC -#define RSMU_PGFSM_WR_DATA_GENERIC__RSMU_PGFSM_WR_DATA_MASK 0xffffffffL - -// RSMU_PGFSM_RD_DATA_GENERIC -#define RSMU_PGFSM_RD_DATA_GENERIC__RSMU_PGFSM_RD_DATA_MASK 0xffffffffL - -// RSMU_IH_CREDIT_GENERIC -#define RSMU_IH_CREDIT_GENERIC__RSMU_IH_CREDIT_MASK 0xffffffffL - -// RSMU_IH_RESET_CNTL_GENERIC -#define RSMU_IH_RESET_CNTL_GENERIC__RSMU_IH_RESET_MASK 0x00000001L -#define RSMU_IH_RESET_CNTL_GENERIC__RSMU_IH_HARD_RESET_ENABLE_MASK 0x00000002L -#define RSMU_IH_RESET_CNTL_GENERIC__RSMU_IH_SOFT_RESET_ENABLE_MASK 0x00000004L - -// RSMU_SEM_RESP_GENERIC -#define RSMU_SEM_RESP_GENERIC__RSMU_SEM_RESP_MASK 0xffffffffL - -// RSMU_SEM_RESET_CNTL_GENERIC -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_RESET_MASK 0x00000001L -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_HARD_RESET_ENABLE_MASK 0x00000002L -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_SOFT_RESET_ENABLE_MASK 0x00000004L -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_RESET_PROTECT_ENABLE_MASK 0x00000008L - -// RSMU_VIRTUAL_WIRE_SRC_ID_GENERIC -#define RSMU_VIRTUAL_WIRE_SRC_ID_GENERIC__RSMU_VIRTUAL_WIRE_SRC_ID_MASK 0x0000001fL - -// RSMU_VIRTUAL_WIRE_INDEX_GENERIC -#define RSMU_VIRTUAL_WIRE_INDEX_GENERIC__RSMU_VIRTUAL_WIRE_INDEX_MASK 0x000003ffL - -// RSMU_SW_STRAPRX_ADDR_GENERIC -#define RSMU_SW_STRAPRX_ADDR_GENERIC__RSMU_SW_STRAPRX_ADDR_MASK 0xffffffffL - -// RSMU_SW_STRAPRX_DATA_GENERIC -#define RSMU_SW_STRAPRX_DATA_GENERIC__RSMU_SW_STRAPRX_DATA_MASK 0xffffffffL - -// RSMU_SW_STRAP_CONTROL_GENERIC -#define RSMU_SW_STRAP_CONTROL_GENERIC__RSMU_SW_PUB_FUSE_RELOAD_MASK 0x00000001L -#define RSMU_SW_STRAP_CONTROL_GENERIC__RSMU_SW_ROM_RELOAD_MASK 0x00000002L - -// RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_ADDR_MASK 0x000fffffL -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_APERTUREID_MASK 0x00300000L -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_INITIATORID_MASK 0x3fc00000L -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_OP_MASK 0x40000000L -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_OUTSTANDING_MASK 0x80000000L - -// RSMU_IP_MASTER_STATUS_GENERIC -#define RSMU_IP_MASTER_STATUS_GENERIC__RSMU_IP_MASTER_REQ_PENDING_MASK 0x00000001L -#define RSMU_IP_MASTER_STATUS_GENERIC__RSMU_IP_MASTER_RESP_PENDING_MASK 0x00000002L - -// RSMU_GPUREG_SCRATCH_REG_0_GENERIC -#define RSMU_GPUREG_SCRATCH_REG_0_GENERIC__RSMU_GPUREG_SCRATCH_REG_0_MASK 0xffffffffL - -// RSMU_GPUREG_SCRATCH_REG_1_GENERIC -#define RSMU_GPUREG_SCRATCH_REG_1_GENERIC__RSMU_GPUREG_SCRATCH_REG_1_MASK 0xffffffffL - -// RSMU_COLD_RESETB_GENERIC -#define RSMU_COLD_RESETB_GENERIC__RSMU_COLD_RESETB_MASK 0x00000001L - -// RSMU_HARD_RESETB_GENERIC -#define RSMU_HARD_RESETB_GENERIC__RSMU_HARD_RESETB_MASK 0x00000003L -#define RSMU_HARD_RESETB_GENERIC__RSMU_MASTER_HARD_RESET_FENCE_ENABLE_MASK 0x0000000cL -#define RSMU_HARD_RESETB_GENERIC__RSMU_SLAVE_HARD_RESET_TIMEOUT_ENABLE_MASK 0x00000060L - -// RSMU_PUB_FUSE_ADDR_GENERIC -#define RSMU_PUB_FUSE_ADDR_GENERIC__RSMU_PUB_FUSE_START_ADDR_MASK 0x0000ffffL -#define RSMU_PUB_FUSE_ADDR_GENERIC__RSMU_PUB_FUSE_END_ADDR_MASK 0xffff0000L - -// RSMU_SEC_FUSE_ADDR_GENERIC -#define RSMU_SEC_FUSE_ADDR_GENERIC__RSMU_SEC_FUSE_START_ADDR_MASK 0x0000ffffL -#define RSMU_SEC_FUSE_ADDR_GENERIC__RSMU_SEC_FUSE_END_ADDR_MASK 0xffff0000L - -// RSMU_ROM_ADDR_GENERIC -#define RSMU_ROM_ADDR_GENERIC__RSMU_ROM_START_ADDR_MASK 0x0000ffffL -#define RSMU_ROM_ADDR_GENERIC__RSMU_ROM_END_ADDR_MASK 0xffff0000L - -// RSMU_MEM_POWER_CTRL_GENERIC -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_FUSE_RM_FUSES_MASK 0x000001ffL -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_RF_BC1_MASK 0x00000200L -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_RF_BC2_MASK 0x00000400L -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_PDP_BC1_MASK 0x00000800L -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_PDP_BC2_MASK 0x00001000L -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_HD_BC1_MASK 0x00002000L -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_HD_BC2_MASK 0x00004000L - -// RSMU_MP0_STRAPRX_ADDR_GENERIC -#define RSMU_MP0_STRAPRX_ADDR_GENERIC__RSMU_MP0_STRAPRX_ADDR_MASK 0xffffffffL - -// RSMU_MP0_STRAPRX_DATA_GENERIC -#define RSMU_MP0_STRAPRX_DATA_GENERIC__RSMU_MP0_STRAPRX_DATA_MASK 0xffffffffL - -// RSMU_SMS_FUSE_CFG_GENERIC -#define RSMU_SMS_FUSE_CFG_GENERIC__RSMU_SMS_FUSE_RESETB_MASK 0x00000001L -#define RSMU_SMS_FUSE_CFG_GENERIC__RSMU_SMS_FUSE_RUN_BIHR_MASK 0x00000002L -#define RSMU_SMS_FUSE_CFG_GENERIC__RSMU_SMS_FUSE_RUN_MBIST_MASK 0x00000004L - -// RSMU_SMS_FUSE_ADDR_BASE_GENERIC -#define RSMU_SMS_FUSE_ADDR_BASE_GENERIC__RSMU_SMS_FUSE_ADDR_BASE_MASK 0x000fffffL - -// RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP0_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP1_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP2_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP3_MASK 0xff000000L - -// RSMU_STRAP_CONTROL_GENERIC -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PUB_FUSE_READY_MASK 0x00000001L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PUB_FUSE_VALID_MASK 0x00000002L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PUB_FUSE_RELOAD_MASK 0x00000004L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_ROM_READY_MASK 0x00000008L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_ROM_VALID_MASK 0x00000010L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_ROM_RELOAD_MASK 0x00000020L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PIN_RELOAD_MASK 0x00000040L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SEC_FUSE_READY_MASK 0x00000080L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SEC_FUSE_VALID_MASK 0x00000100L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP0_MASK 0x00000200L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP1_MASK 0x00000400L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP2_MASK 0x00000800L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP3_MASK 0x00001000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP0_MASK 0x00002000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP1_MASK 0x00004000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP2_MASK 0x00008000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP3_MASK 0x00010000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP0_MASK 0x00020000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP1_MASK 0x00040000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP2_MASK 0x00080000L -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP3_MASK 0x00100000L - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP4_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP5_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP6_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP7_MASK 0xff000000L - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP8_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP9_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP10_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP11_MASK 0xff000000L - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP12_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP13_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP14_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP15_MASK 0xff000000L - -// RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP4_MASK 0x00000001L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP5_MASK 0x00000002L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP6_MASK 0x00000004L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP7_MASK 0x00000008L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP8_MASK 0x00000010L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP9_MASK 0x00000020L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP10_MASK 0x00000040L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP11_MASK 0x00000080L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP12_MASK 0x00000100L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP13_MASK 0x00000200L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP14_MASK 0x00000400L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP15_MASK 0x00000800L - -// RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP4_MASK 0x00000001L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP5_MASK 0x00000002L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP6_MASK 0x00000004L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP7_MASK 0x00000008L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP8_MASK 0x00000010L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP9_MASK 0x00000020L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP10_MASK 0x00000040L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP11_MASK 0x00000080L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP12_MASK 0x00000100L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP13_MASK 0x00000200L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP14_MASK 0x00000400L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP15_MASK 0x00000800L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP4_MASK 0x00001000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP5_MASK 0x00002000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP6_MASK 0x00004000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP7_MASK 0x00008000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP8_MASK 0x00010000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP9_MASK 0x00020000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP10_MASK \ - 0x00040000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP11_MASK \ - 0x00080000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP12_MASK \ - 0x00100000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP13_MASK \ - 0x00200000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP14_MASK \ - 0x00400000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP15_MASK \ - 0x00800000L - -// RSMU_CAC_LKG_WEIGHT_0_GENERIC -#define RSMU_CAC_LKG_WEIGHT_0_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_0_MASK 0x0000ffffL -#define RSMU_CAC_LKG_WEIGHT_0_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_0_MASK 0xffff0000L - -// RSMU_CAC_LKG_WEIGHT_1_GENERIC -#define RSMU_CAC_LKG_WEIGHT_1_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_1_MASK 0x0000ffffL -#define RSMU_CAC_LKG_WEIGHT_1_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_1_MASK 0xffff0000L - -// RSMU_CAC_LKG_WEIGHT_2_GENERIC -#define RSMU_CAC_LKG_WEIGHT_2_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_2_MASK 0x0000ffffL -#define RSMU_CAC_LKG_WEIGHT_2_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_2_MASK 0xffff0000L - -// RSMU_CAC_LKG_WEIGHT_3_GENERIC -#define RSMU_CAC_LKG_WEIGHT_3_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_3_MASK 0x0000ffffL -#define RSMU_CAC_LKG_WEIGHT_3_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_3_MASK 0xffff0000L - -// RSMU_CAC_LKG_ACC_0_GENERIC -#define RSMU_CAC_LKG_ACC_0_GENERIC__RSMU_CAC_LKG_ACC_0_MASK 0xffffffffL - -// RSMU_CAC_LKG_ACC_1_GENERIC -#define RSMU_CAC_LKG_ACC_1_GENERIC__RSMU_CAC_LKG_ACC_1_MASK 0xffffffffL - -// RSMU_CAC_LKG_ACC_2_GENERIC -#define RSMU_CAC_LKG_ACC_2_GENERIC__RSMU_CAC_LKG_ACC_2_MASK 0xffffffffL - -// RSMU_CAC_LKG_ACC_3_GENERIC -#define RSMU_CAC_LKG_ACC_3_GENERIC__RSMU_CAC_LKG_ACC_3_MASK 0xffffffffL - -// RSMU_CAC_LKG_ACC_4_GENERIC -#define RSMU_CAC_LKG_ACC_4_GENERIC__RSMU_CAC_LKG_ACC_4_MASK 0xffffffffL - -// RSMU_CAC_LKG_ACC_5_GENERIC -#define RSMU_CAC_LKG_ACC_5_GENERIC__RSMU_CAC_LKG_ACC_5_MASK 0xffffffffL - -// RSMU_CAC_LKG_ACC_6_GENERIC -#define RSMU_CAC_LKG_ACC_6_GENERIC__RSMU_CAC_LKG_ACC_6_MASK 0xffffffffL - -// RSMU_CAC_LKG_ACC_7_GENERIC -#define RSMU_CAC_LKG_ACC_7_GENERIC__RSMU_CAC_LKG_ACC_7_MASK 0xffffffffL - -// RSMU_CAC_CONTROL_GENERIC -#define RSMU_CAC_CONTROL_GENERIC__RSMU_CAC_WINDOW_MASK 0x00ffffffL -#define RSMU_CAC_CONTROL_GENERIC__RSMU_CAC_ENABLE_MASK 0x80000000L - -// RSMU_CAC_WEIGHT_0_GENERIC -#define RSMU_CAC_WEIGHT_0_GENERIC__CAC_WEIGHT_LO_0_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_0_GENERIC__CAC_WEIGHT_HI_0_MASK 0xffff0000L - -// RSMU_CAC_WEIGHT_1_GENERIC -#define RSMU_CAC_WEIGHT_1_GENERIC__CAC_WEIGHT_LO_1_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_1_GENERIC__CAC_WEIGHT_HI_1_MASK 0xffff0000L - -// RSMU_CAC_WEIGHT_2_GENERIC -#define RSMU_CAC_WEIGHT_2_GENERIC__CAC_WEIGHT_LO_2_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_2_GENERIC__CAC_WEIGHT_HI_2_MASK 0xffff0000L - -// RSMU_CAC_WEIGHT_3_GENERIC -#define RSMU_CAC_WEIGHT_3_GENERIC__CAC_WEIGHT_LO_3_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_3_GENERIC__CAC_WEIGHT_HI_3_MASK 0xffff0000L - -// RSMU_CAC_WEIGHT_4_GENERIC -#define RSMU_CAC_WEIGHT_4_GENERIC__CAC_WEIGHT_LO_4_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_4_GENERIC__CAC_WEIGHT_HI_4_MASK 0xffff0000L - -// RSMU_CAC_WEIGHT_5_GENERIC -#define RSMU_CAC_WEIGHT_5_GENERIC__CAC_WEIGHT_LO_5_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_5_GENERIC__CAC_WEIGHT_HI_5_MASK 0xffff0000L - -// RSMU_CAC_WEIGHT_6_GENERIC -#define RSMU_CAC_WEIGHT_6_GENERIC__CAC_WEIGHT_LO_6_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_6_GENERIC__CAC_WEIGHT_HI_6_MASK 0xffff0000L - -// RSMU_CAC_WEIGHT_7_GENERIC -#define RSMU_CAC_WEIGHT_7_GENERIC__CAC_WEIGHT_LO_7_MASK 0x0000ffffL -#define RSMU_CAC_WEIGHT_7_GENERIC__CAC_WEIGHT_HI_7_MASK 0xffff0000L - -// RSMU_CAC_ACC_0_GENERIC -#define RSMU_CAC_ACC_0_GENERIC__RSMU_CAC_ACC_0_MASK 0xffffffffL - -// RSMU_CAC_ACC_1_GENERIC -#define RSMU_CAC_ACC_1_GENERIC__RSMU_CAC_ACC_1_MASK 0xffffffffL - -// RSMU_CAC_ACC_2_GENERIC -#define RSMU_CAC_ACC_2_GENERIC__RSMU_CAC_ACC_2_MASK 0xffffffffL - -// RSMU_CAC_ACC_3_GENERIC -#define RSMU_CAC_ACC_3_GENERIC__RSMU_CAC_ACC_3_MASK 0xffffffffL - -// RSMU_CAC_ACC_4_GENERIC -#define RSMU_CAC_ACC_4_GENERIC__RSMU_CAC_ACC_4_MASK 0xffffffffL - -// RSMU_CAC_ACC_5_GENERIC -#define RSMU_CAC_ACC_5_GENERIC__RSMU_CAC_ACC_5_MASK 0xffffffffL - -// RSMU_CAC_ACC_6_GENERIC -#define RSMU_CAC_ACC_6_GENERIC__RSMU_CAC_ACC_6_MASK 0xffffffffL - -// RSMU_CAC_ACC_7_GENERIC -#define RSMU_CAC_ACC_7_GENERIC__RSMU_CAC_ACC_7_MASK 0xffffffffL - -// RSMU_CAC_ACC_8_GENERIC -#define RSMU_CAC_ACC_8_GENERIC__RSMU_CAC_ACC_8_MASK 0xffffffffL - -// RSMU_CAC_ACC_9_GENERIC -#define RSMU_CAC_ACC_9_GENERIC__RSMU_CAC_ACC_9_MASK 0xffffffffL - -// RSMU_CAC_ACC_10_GENERIC -#define RSMU_CAC_ACC_10_GENERIC__RSMU_CAC_ACC_10_MASK 0xffffffffL - -// RSMU_CAC_ACC_11_GENERIC -#define RSMU_CAC_ACC_11_GENERIC__RSMU_CAC_ACC_11_MASK 0xffffffffL - -// RSMU_CAC_ACC_12_GENERIC -#define RSMU_CAC_ACC_12_GENERIC__RSMU_CAC_ACC_12_MASK 0xffffffffL - -// RSMU_CAC_ACC_13_GENERIC -#define RSMU_CAC_ACC_13_GENERIC__RSMU_CAC_ACC_13_MASK 0xffffffffL - -// RSMU_CAC_ACC_14_GENERIC -#define RSMU_CAC_ACC_14_GENERIC__RSMU_CAC_ACC_14_MASK 0xffffffffL - -// RSMU_CAC_ACC_15_GENERIC -#define RSMU_CAC_ACC_15_GENERIC__RSMU_CAC_ACC_15_MASK 0xffffffffL - -// RSMU_CAC_AGGR_LO_GENERIC -#define RSMU_CAC_AGGR_LO_GENERIC__RSMU_CAC_AGGR_LO_MASK 0xffffffffL - -// RSMU_CAC_AGGR_HI_GENERIC -#define RSMU_CAC_AGGR_HI_GENERIC__RSMU_CAC_AGGR_HI_MASK 0xffffffffL - -// RSMU_DPM_CONTROL_GENERIC -#define RSMU_DPM_CONTROL_GENERIC__RSMU_DPM_ACC_RESET_MASK 0x00000001L -#define RSMU_DPM_CONTROL_GENERIC__RSMU_DPM_ACC_START_MASK 0x00000002L -#define RSMU_DPM_CONTROL_GENERIC__RSMU_DPM_BUSY_MASK_MASK 0x000003fcL - -// RSMU_DPM_ACC_GENERIC -#define RSMU_DPM_ACC_GENERIC__RSMU_DPM_ACC_MASK 0x00ffffffL - -// RSMU_DPM_IPCLK_REF_COUNTER_GENERIC -#define RSMU_DPM_IPCLK_REF_COUNTER_GENERIC__RSMU_DPM_IPCLK_REF_COUNTER_MASK 0x00ffffffL - -// RSMU_COUNTER_0_GENERIC -#define RSMU_COUNTER_0_GENERIC__RSMU_COUNTER_0_MASK 0xffffffffL - -// RSMU_COUNTER_1_GENERIC -#define RSMU_COUNTER_1_GENERIC__RSMU_COUNTER_1_MASK 0x00ffffffL - -// RSMU_PWRMGT_INTR_ENABLE_P0_GENERIC -#define RSMU_PWRMGT_INTR_ENABLE_P0_GENERIC__RSMU_PWRMGT_INTR_ENABLE_P0_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_ENABLE_P1_GENERIC -#define RSMU_PWRMGT_INTR_ENABLE_P1_GENERIC__RSMU_PWRMGT_INTR_ENABLE_P1_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_ENABLE_P2_GENERIC -#define RSMU_PWRMGT_INTR_ENABLE_P2_GENERIC__RSMU_PWRMGT_INTR_ENABLE_P2_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_TARGET_ADDR_P0_GENERIC -#define RSMU_PWRMGT_INTR_TARGET_ADDR_P0_GENERIC__RSMU_PWRMGT_INTR_TARGET_ADDR_P0_MASK 0xffffffffL - -// RSMU_PWRMGT_INTR_TARGET_ADDR_P1_GENERIC -#define RSMU_PWRMGT_INTR_TARGET_ADDR_P1_GENERIC__RSMU_PWRMGT_INTR_TARGET_ADDR_P1_MASK 0xffffffffL - -// RSMU_PWRMGT_INTR_TARGET_ADDR_P2_GENERIC -#define RSMU_PWRMGT_INTR_TARGET_ADDR_P2_GENERIC__RSMU_PWRMGT_INTR_TARGET_ADDR_P2_MASK 0xffffffffL - -// RSMU_PWRMGT_INTR_CONFIG_P0_GENERIC -#define RSMU_PWRMGT_INTR_CONFIG_P0_GENERIC__RSMU_PWRMGT_INTR_CONFIG_VC_P0_MASK 0x00000003L - -// RSMU_PWRMGT_INTR_CONFIG_P1_GENERIC -#define RSMU_PWRMGT_INTR_CONFIG_P1_GENERIC__RSMU_PWRMGT_INTR_CONFIG_VC_P1_MASK 0x00000003L - -// RSMU_PWRMGT_INTR_CONFIG_P2_GENERIC -#define RSMU_PWRMGT_INTR_CONFIG_P2_GENERIC__RSMU_PWRMGT_INTR_CONFIG_VC_P2_MASK 0x00000003L - -// RSMU_PWRMGT_INTR_STATUS_GENERIC -#define RSMU_PWRMGT_INTR_STATUS_GENERIC__RSMU_PWRMGT_INTR_STATUS_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_PENDING_P0_GENERIC -#define RSMU_PWRMGT_INTR_PENDING_P0_GENERIC__RSMU_PWRMGT_INTR_PENDING_P0_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_PENDING_P1_GENERIC -#define RSMU_PWRMGT_INTR_PENDING_P1_GENERIC__RSMU_PWRMGT_INTR_PENDING_P1_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_PENDING_P2_GENERIC -#define RSMU_PWRMGT_INTR_PENDING_P2_GENERIC__RSMU_PWRMGT_INTR_PENDING_P2_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_TYPE_GENERIC -#define RSMU_PWRMGT_INTR_TYPE_GENERIC__RSMU_PWRMGT_INTR_TYPE_MASK 0x0000ffffL - -// RSMU_PWRMGT_INTR_INTERCEPT_GENERIC -#define RSMU_PWRMGT_INTR_INTERCEPT_GENERIC__RSMU_PWRMGT_INTR_OVERRIDE_MASK 0x0000ffffL -#define RSMU_PWRMGT_INTR_INTERCEPT_GENERIC__RSMU_PWRMGT_INTR_VALUE_MASK 0xffff0000L - -// RSMU_PWRMGT_INTR_CLEAR_GENERIC -#define RSMU_PWRMGT_INTR_CLEAR_GENERIC__RSMU_PWRMGT_INTR_CLEAR_MASK 0x0000ffffL - -// RSMU_HARD_RESETB_DELAY_GENERIC -#define RSMU_HARD_RESETB_DELAY_GENERIC__RSMU_HARD_RESETB_DELAY_MASK 0x0000003fL - -// RSMU_MMIOPUB_SCRATCH_REG_0_GENERIC -#define RSMU_MMIOPUB_SCRATCH_REG_0_GENERIC__RSMU_MMIOPUB_SCRATCH_REG_0_MASK 0xffffffffL - -// RSMU_VF_ENABLE_GENERIC -#define RSMU_VF_ENABLE_GENERIC__RSMU_VF_ENABLE_MASK 0x00000001L - -// RSMU_MGCG_CONTROL_GENERIC -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_AXI_SLAVE_MGCG_OVERRIDE_MASK 0x00000001L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_AXI_MASTER_MGCG_OVERRIDE_MASK 0x00000002L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_SEC_INTR_MGCG_OVERRIDE_MASK 0x00000004L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_PWRMGT_INTR_MGCG_OVERRIDE_MASK 0x00000008L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_REG_WRAPPER_MGCG_OVERRIDE_MASK 0x00000010L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_STRAP_MASTER_MGCG_OVERRIDE_MASK 0x00000020L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_VWIRE_SRC_MGCG_OVERRIDE_MASK 0x00000040L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_REGIF_MASTER_MGCG_OVERRIDE_MASK 0x00000080L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_PGFSM_MGCG_OVERRIDE_MASK 0x00000100L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_IH_MGCG_OVERRIDE_MASK 0x00000200L -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_SEM_MGCG_OVERRIDE_MASK 0x00000400L - -// RSMU_CUSTOM_HARD_RESETB_GENERIC -#define RSMU_CUSTOM_HARD_RESETB_GENERIC__RSMU_CUSTOM_HARD_RESETB_MASK 0x0000000fL - -// RSMU_SEC_AXI_MASTER_ENABLE_GENERIC -#define RSMU_SEC_AXI_MASTER_ENABLE_GENERIC__RSMU_SEC_AXI_MASTER_ENABLE_MASK 0x00000001L - -// RSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC__RSMU_SEC_SLAVE_ERROR_COUNTER_MASK 0x0000ffffL -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC__RSMU_SEC_SLAVE_ERROR_COUNTER_RSMU_MASK 0xffff0000L - -// RSMU_AXI_MASTER_QOS_CNTL_GENERIC -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_MASTER_QOS_OVRD_MODE_MASK 0x00000001L -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_MASTER_QOS_OVRD_VALUE_MASK 0x0000001eL -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_AWQOS_OVRD_MODE_MASK 0x00000020L -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_AWQOS_OVRD_VALUE_MASK 0x000003c0L -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_ARQOS_OVRD_MODE_MASK 0x00000400L -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_ARQOS_OVRD_VALUE_MASK 0x00007800L - -// RSMU_MASTER_ERROR_COUNTER_GENERIC -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_SMN_SLVERR_COUNTER_MASK 0x000000ffL -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_SMN_DECERR_COUNTER_MASK 0x0000ff00L -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_MASTER_SLVERR_COUNTER_MASK 0x00ff0000L -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_MASTER_DECERR_COUNTER_MASK 0xff000000L - -// RSMU_SLAVE_TIMEOUT_VALUE_GENERIC -#define RSMU_SLAVE_TIMEOUT_VALUE_GENERIC__RSMU_SLAVE_TIMEOUT_VALUE_MASK 0xffffffffL - -// RSMU_RESET_TIMEOUT_CONTROL_GENERIC -#define RSMU_RESET_TIMEOUT_CONTROL_GENERIC__RSMU_SLAVE_TIMEOUT_ENABLE_MASK 0x00000001L -#define RSMU_RESET_TIMEOUT_CONTROL_GENERIC__RSMU_SLAVE_RESET_TIMEOUT_VALUE_MASK 0x000001feL - -// RSMU_SLAVE_ERROR_COUNTER_GENERIC -#define RSMU_SLAVE_ERROR_COUNTER_GENERIC__RSMU_SLAVE_ERROR_COUNTER_MASK 0x000000ffL - -// RSMU_AEB_LOCK_0_GENERIC -#define RSMU_AEB_LOCK_0_GENERIC__RSMU_AEB_LOCK_0_MASK 0xfffffff8L - -// RSMU_AEB_LOCK_1_GENERIC -#define RSMU_AEB_LOCK_1_GENERIC__RSMU_AEB_LOCK_1_MASK 0xffffffffL - -// RSMU_AEB_OVERRIDE_0_GENERIC -#define RSMU_AEB_OVERRIDE_0_GENERIC__RSMU_AEB_OVERRIDE_0_MASK 0xfffffff8L - -// RSMU_AEB_OVERRIDE_1_GENERIC -#define RSMU_AEB_OVERRIDE_1_GENERIC__RSMU_AEB_OVERRIDE_1_MASK 0xffffffffL - -// RSMU_SEC_INTR_ENABLE_GENERIC -#define RSMU_SEC_INTR_ENABLE_GENERIC__RSMU_SEC_INTR_ENABLE_MASK 0x0000ffffL - -// RSMU_SEC_INTR_TARGET_ADDR_GENERIC -#define RSMU_SEC_INTR_TARGET_ADDR_GENERIC__RSMU_SEC_INTR_TARGET_ADDR_MASK 0xffffffffL - -// RSMU_SEC_INTR_CONFIG_GENERIC -#define RSMU_SEC_INTR_CONFIG_GENERIC__RSMU_SEC_INTR_CONFIG_VC_MASK 0x00000003L - -// RSMU_SEC_INTR_STATUS_GENERIC -#define RSMU_SEC_INTR_STATUS_GENERIC__RSMU_SEC_INTR_STATUS_MASK 0x0000ffffL - -// RSMU_SEC_INTR_PENDING_GENERIC -#define RSMU_SEC_INTR_PENDING_GENERIC__RSMU_SEC_INTR_PENDING_MASK 0x0000ffffL - -// RSMU_SEC_INTR_TYPE_GENERIC -#define RSMU_SEC_INTR_TYPE_GENERIC__RSMU_SEC_INTR_TYPE_MASK 0x0000ffffL - -// RSMU_SEC_INTR_INTERCEPT_GENERIC -#define RSMU_SEC_INTR_INTERCEPT_GENERIC__RSMU_SEC_INTR_OVERRIDE_MASK 0x0000ffffL -#define RSMU_SEC_INTR_INTERCEPT_GENERIC__RSMU_SEC_INTR_VALUE_MASK 0xffff0000L - -// RSMU_SEC_INTR_CLEAR_GENERIC -#define RSMU_SEC_INTR_CLEAR_GENERIC__RSMU_SEC_INTR_CLEAR_MASK 0x0000ffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_0_GENERIC -#define RSMU_SEC_MASTER_TRUST_LEVEL_0_GENERIC__RSMU_SEC_MASTER_TRUST_LEVEL_0_MASK 0x00ffffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GENERIC -#define RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GENERIC__RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_MASK 0x00ffffffL - -// RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE1_MASK 0x00000001L -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE2_MASK 0x00000002L -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC__RSMU_SEC_TLVL_MASK_RSMU_RANGE2_MASK 0x000003fcL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_DEFAULT_MASK \ - 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_DEFAULT_MASK \ - 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_DEFAULT_MASK \ - 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_DEFAULT_MASK \ - 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_DEFAULT_MASK \ - 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_DEFAULT_MASK \ - 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_DEFAULT_MASK \ - 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_DEFAULT_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_DEFAULT_MASK \ - 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_DEFAULT_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_DEFAULT_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_DEFAULT_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_DEFAULT_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_DEFAULT_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_0_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_0_GENERIC__RSMU_SEC_START_ADDR_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_0_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_0_GENERIC__RSMU_SEC_END_ADDR_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_0_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_0_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_0_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_0_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_0_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_0_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_0_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_0_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_0_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_0_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_0_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_0_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_0_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_0_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_0_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_0_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_0_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_0_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_0_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_0_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_1_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_1_GENERIC__RSMU_SEC_START_ADDR_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_1_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_1_GENERIC__RSMU_SEC_END_ADDR_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_1_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_1_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_1_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_1_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_1_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_1_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_1_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_1_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_1_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_1_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_1_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_1_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_1_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_1_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_1_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_1_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_1_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_1_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_1_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_1_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_2_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_2_GENERIC__RSMU_SEC_START_ADDR_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_2_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_2_GENERIC__RSMU_SEC_END_ADDR_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_2_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_2_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_2_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_2_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_2_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_2_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_2_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_2_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_2_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_2_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_2_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_2_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_2_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_2_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_2_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_2_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_2_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_2_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_2_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_2_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_3_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_3_GENERIC__RSMU_SEC_START_ADDR_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_3_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_3_GENERIC__RSMU_SEC_END_ADDR_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_3_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_3_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_3_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_3_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_3_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_3_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_3_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_3_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_3_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_3_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_3_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_3_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_3_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_3_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_3_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_3_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_3_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_3_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_3_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_3_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_4_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_4_GENERIC__RSMU_SEC_START_ADDR_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_4_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_4_GENERIC__RSMU_SEC_END_ADDR_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_4_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_4_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_4_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_4_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_4_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_4_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_4_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_4_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_4_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_4_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_4_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_4_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_4_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_4_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_4_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_4_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_4_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_4_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_4_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_4_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_5_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_5_GENERIC__RSMU_SEC_START_ADDR_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_5_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_5_GENERIC__RSMU_SEC_END_ADDR_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_5_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_5_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_5_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_5_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_5_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_5_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_5_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_5_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_5_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_5_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_5_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_5_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_5_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_5_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_5_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_5_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_5_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_5_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_5_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_5_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_6_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_6_GENERIC__RSMU_SEC_START_ADDR_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_6_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_6_GENERIC__RSMU_SEC_END_ADDR_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_6_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_6_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_6_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_6_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_6_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_6_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_6_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_6_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_6_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_6_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_6_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_6_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_6_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_6_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_6_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_6_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_6_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_6_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_6_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_6_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_7_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_7_GENERIC__RSMU_SEC_START_ADDR_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_7_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_7_GENERIC__RSMU_SEC_END_ADDR_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_7_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_7_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_7_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_7_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_7_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_7_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_7_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_7_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_7_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_7_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_7_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_7_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_7_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_7_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_7_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_7_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_7_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_7_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_7_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_7_MASK \ - 0x00008000L - -// RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_ADDR_MASK 0x000fffffL -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_APERTUREID_MASK 0x00300000L -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_INITIATORID_MASK 0x3fc00000L -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_OP_MASK 0x40000000L -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_OUTSTANDING_MASK 0x80000000L - -// RSMU_MMIOSEC_SCRATCH_REG_0_GENERIC -#define RSMU_MMIOSEC_SCRATCH_REG_0_GENERIC__RSMU_MMIOSEC_SCRATCH_REG_0_MASK 0xffffffffL - -// RSMU_HCID_GC -#define RSMU_HCID_GC__RSMU_HCID_HwRev_MASK 0x0000003fL -#define RSMU_HCID_GC__RSMU_HCID_HwMinVer_MASK 0x00001fc0L -#define RSMU_HCID_GC__RSMU_HCID_HwMajVer_MASK 0x000fe000L -#define RSMU_HCID_GC__RSMU_HCID_HwID_MASK 0xfff00000L - -// RSMU_SIID_GC -#define RSMU_SIID_GC__RSMU_SIID_SwIfRev_MASK 0x0000003fL -#define RSMU_SIID_GC__RSMU_SIID_SwIfMinVer_MASK 0x00001fc0L -#define RSMU_SIID_GC__RSMU_SIID_SwIfMajVer_MASK 0x000fe000L -#define RSMU_SIID_GC__RSMU_SIID_SwIfID_MASK 0xfff00000L - -// RSMU_DBG_MUX_CONTROL_GC -#define RSMU_DBG_MUX_CONTROL_GC__RSMU_DBG_MUX_SELECT_MASK 0x000000ffL - -// RSMU_SW_MMIO_PUB_IND_ADDR_0_GC -#define RSMU_SW_MMIO_PUB_IND_ADDR_0_GC__RSMU_SW_MMIO_PUB_IND_ADDR_0_MASK 0xffffffffL - -// RSMU_SW_MMIO_PUB_IND_DATA_0_GC -#define RSMU_SW_MMIO_PUB_IND_DATA_0_GC__RSMU_SW_MMIO_PUB_IND_DATA_0_MASK 0xffffffffL - -// RSMU_SW_MMIO_PUB_IND_ADDR_1_GC -#define RSMU_SW_MMIO_PUB_IND_ADDR_1_GC__RSMU_SW_MMIO_PUB_IND_ADDR_1_MASK 0xffffffffL - -// RSMU_SW_MMIO_PUB_IND_DATA_1_GC -#define RSMU_SW_MMIO_PUB_IND_DATA_1_GC__RSMU_SW_MMIO_PUB_IND_DATA_1_MASK 0xffffffffL - -// RSMU_SOFT_RESETB_GC -#define RSMU_SOFT_RESETB_GC__RSMU_SOFT_RESETB_MASK 0x00000003L -#define RSMU_SOFT_RESETB_GC__RSMU_MASTER_SOFT_RESET_FENCE_ENABLE_MASK 0x0000000cL -#define RSMU_SOFT_RESETB_GC__RSMU_SLAVE_SOFT_RESET_TIMEOUT_ENABLE_MASK 0x00000030L - -// RSMU_IH_CREDIT_GC -#define RSMU_IH_CREDIT_GC__RSMU_IH_CREDIT_MASK 0xffffffffL - -// RSMU_IH_RESET_CNTL_GC -#define RSMU_IH_RESET_CNTL_GC__RSMU_IH_RESET_MASK 0x00000001L -#define RSMU_IH_RESET_CNTL_GC__RSMU_IH_HARD_RESET_ENABLE_MASK 0x00000002L -#define RSMU_IH_RESET_CNTL_GC__RSMU_IH_SOFT_RESET_ENABLE_MASK 0x00000004L - -// RSMU_SEM_RESP_GC -#define RSMU_SEM_RESP_GC__RSMU_SEM_RESP_MASK 0xffffffffL - -// RSMU_SEM_RESET_CNTL_GC -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_RESET_MASK 0x00000001L -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_HARD_RESET_ENABLE_MASK 0x00000002L -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_SOFT_RESET_ENABLE_MASK 0x00000004L -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_RESET_PROTECT_ENABLE_MASK 0x00000008L - -// RSMU_SW_STRAPRX_ADDR_GC -#define RSMU_SW_STRAPRX_ADDR_GC__RSMU_SW_STRAPRX_ADDR_MASK 0xffffffffL - -// RSMU_SW_STRAPRX_DATA_GC -#define RSMU_SW_STRAPRX_DATA_GC__RSMU_SW_STRAPRX_DATA_MASK 0xffffffffL - -// RSMU_SW_STRAP_CONTROL_GC -#define RSMU_SW_STRAP_CONTROL_GC__RSMU_SW_PUB_FUSE_RELOAD_MASK 0x00000001L -#define RSMU_SW_STRAP_CONTROL_GC__RSMU_SW_ROM_RELOAD_MASK 0x00000002L - -// RSMU_TIMEOUT_ERROR_LOG_REG_GC -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_ADDR_MASK 0x000fffffL -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_APERTUREID_MASK 0x00300000L -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_INITIATORID_MASK 0x3fc00000L -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_OP_MASK 0x40000000L -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_OUTSTANDING_MASK 0x80000000L - -// RSMU_IP_MASTER_STATUS_GC -#define RSMU_IP_MASTER_STATUS_GC__RSMU_IP_MASTER_REQ_PENDING_MASK 0x00000001L -#define RSMU_IP_MASTER_STATUS_GC__RSMU_IP_MASTER_RESP_PENDING_MASK 0x00000002L - -// RSMU_GPUREG_SCRATCH_REG_0_GC -#define RSMU_GPUREG_SCRATCH_REG_0_GC__RSMU_GPUREG_SCRATCH_REG_0_MASK 0xffffffffL - -// RSMU_GPUREG_SCRATCH_REG_1_GC -#define RSMU_GPUREG_SCRATCH_REG_1_GC__RSMU_GPUREG_SCRATCH_REG_1_MASK 0xffffffffL - -// RSMU_COLD_RESETB_GC -#define RSMU_COLD_RESETB_GC__RSMU_COLD_RESETB_MASK 0x00000001L - -// RSMU_HARD_RESETB_GC -#define RSMU_HARD_RESETB_GC__RSMU_HARD_RESETB_MASK 0x00000003L -#define RSMU_HARD_RESETB_GC__RSMU_MASTER_HARD_RESET_FENCE_ENABLE_MASK 0x0000000cL -#define RSMU_HARD_RESETB_GC__RSMU_SLAVE_HARD_RESET_TIMEOUT_ENABLE_MASK 0x00000060L - -// RSMU_PUB_FUSE_ADDR_GC -#define RSMU_PUB_FUSE_ADDR_GC__RSMU_PUB_FUSE_START_ADDR_MASK 0x0000ffffL -#define RSMU_PUB_FUSE_ADDR_GC__RSMU_PUB_FUSE_END_ADDR_MASK 0xffff0000L - -// RSMU_SEC_FUSE_ADDR_GC -#define RSMU_SEC_FUSE_ADDR_GC__RSMU_SEC_FUSE_START_ADDR_MASK 0x0000ffffL -#define RSMU_SEC_FUSE_ADDR_GC__RSMU_SEC_FUSE_END_ADDR_MASK 0xffff0000L - -// RSMU_MEM_POWER_CTRL_GC -#define RSMU_MEM_POWER_CTRL_GC__RSMU_FUSE_RM_FUSES_MASK 0x000001ffL -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_RF_BC1_MASK 0x00000200L -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_RF_BC2_MASK 0x00000400L -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_PDP_BC1_MASK 0x00000800L -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_PDP_BC2_MASK 0x00001000L -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_HD_BC1_MASK 0x00002000L -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_HD_BC2_MASK 0x00004000L - -// RSMU_MP0_STRAPRX_ADDR_GC -#define RSMU_MP0_STRAPRX_ADDR_GC__RSMU_MP0_STRAPRX_ADDR_MASK 0xffffffffL - -// RSMU_MP0_STRAPRX_DATA_GC -#define RSMU_MP0_STRAPRX_DATA_GC__RSMU_MP0_STRAPRX_DATA_MASK 0xffffffffL - -// RSMU_SMS_FUSE_CFG_GC -#define RSMU_SMS_FUSE_CFG_GC__RSMU_SMS_FUSE_RESETB_MASK 0x00000001L -#define RSMU_SMS_FUSE_CFG_GC__RSMU_SMS_FUSE_RUN_BIHR_MASK 0x00000002L -#define RSMU_SMS_FUSE_CFG_GC__RSMU_SMS_FUSE_RUN_MBIST_MASK 0x00000004L - -// RSMU_SMS_FUSE_ADDR_BASE_GC -#define RSMU_SMS_FUSE_ADDR_BASE_GC__RSMU_SMS_FUSE_ADDR_BASE_MASK 0x000fffffL - -// RSMU_SMS_FUSE_ADDR_OFFSET_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP0_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP1_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP2_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP3_MASK 0xff000000L - -// RSMU_STRAP_CONTROL_GC -#define RSMU_STRAP_CONTROL_GC__RSMU_PUB_FUSE_READY_MASK 0x00000001L -#define RSMU_STRAP_CONTROL_GC__RSMU_PUB_FUSE_VALID_MASK 0x00000002L -#define RSMU_STRAP_CONTROL_GC__RSMU_PUB_FUSE_RELOAD_MASK 0x00000004L -#define RSMU_STRAP_CONTROL_GC__RSMU_ROM_READY_MASK 0x00000008L -#define RSMU_STRAP_CONTROL_GC__RSMU_ROM_VALID_MASK 0x00000010L -#define RSMU_STRAP_CONTROL_GC__RSMU_ROM_RELOAD_MASK 0x00000020L -#define RSMU_STRAP_CONTROL_GC__RSMU_PIN_RELOAD_MASK 0x00000040L -#define RSMU_STRAP_CONTROL_GC__RSMU_SEC_FUSE_READY_MASK 0x00000080L -#define RSMU_STRAP_CONTROL_GC__RSMU_SEC_FUSE_VALID_MASK 0x00000100L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP0_MASK 0x00000200L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP1_MASK 0x00000400L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP2_MASK 0x00000800L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP3_MASK 0x00001000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP0_MASK 0x00002000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP1_MASK 0x00004000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP2_MASK 0x00008000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP3_MASK 0x00010000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP0_MASK 0x00020000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP1_MASK 0x00040000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP2_MASK 0x00080000L -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP3_MASK 0x00100000L - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP4_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP5_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP6_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP7_MASK 0xff000000L - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP8_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP9_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP10_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP11_MASK 0xff000000L - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP12_MASK 0x000000ffL -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP13_MASK 0x0000ff00L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP14_MASK 0x00ff0000L -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP15_MASK 0xff000000L - -// RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP4_MASK 0x00000001L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP5_MASK 0x00000002L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP6_MASK 0x00000004L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP7_MASK 0x00000008L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP8_MASK 0x00000010L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP9_MASK 0x00000020L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP10_MASK 0x00000040L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP11_MASK 0x00000080L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP12_MASK 0x00000100L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP13_MASK 0x00000200L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP14_MASK 0x00000400L -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP15_MASK 0x00000800L - -// RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP4_MASK 0x00000001L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP5_MASK 0x00000002L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP6_MASK 0x00000004L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP7_MASK 0x00000008L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP8_MASK 0x00000010L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP9_MASK 0x00000020L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP10_MASK 0x00000040L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP11_MASK 0x00000080L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP12_MASK 0x00000100L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP13_MASK 0x00000200L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP14_MASK 0x00000400L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP15_MASK 0x00000800L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP4_MASK 0x00001000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP5_MASK 0x00002000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP6_MASK 0x00004000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP7_MASK 0x00008000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP8_MASK 0x00010000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP9_MASK 0x00020000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP10_MASK 0x00040000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP11_MASK 0x00080000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP12_MASK 0x00100000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP13_MASK 0x00200000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP14_MASK 0x00400000L -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP15_MASK 0x00800000L - -// RSMU_DPM_CONTROL_GC -#define RSMU_DPM_CONTROL_GC__RSMU_DPM_ACC_RESET_MASK 0x00000001L -#define RSMU_DPM_CONTROL_GC__RSMU_DPM_ACC_START_MASK 0x00000002L -#define RSMU_DPM_CONTROL_GC__RSMU_DPM_BUSY_MASK_MASK 0x000003fcL - -// RSMU_DPM_ACC_GC -#define RSMU_DPM_ACC_GC__RSMU_DPM_ACC_MASK 0x00ffffffL - -// RSMU_DPM_IPCLK_REF_COUNTER_GC -#define RSMU_DPM_IPCLK_REF_COUNTER_GC__RSMU_DPM_IPCLK_REF_COUNTER_MASK 0x00ffffffL - -// RSMU_COUNTER_0_GC -#define RSMU_COUNTER_0_GC__RSMU_COUNTER_0_MASK 0xffffffffL - -// RSMU_COUNTER_1_GC -#define RSMU_COUNTER_1_GC__RSMU_COUNTER_1_MASK 0x00ffffffL - -// RSMU_HARD_RESETB_DELAY_GC -#define RSMU_HARD_RESETB_DELAY_GC__RSMU_HARD_RESETB_DELAY_MASK 0x0000003fL - -// RSMU_MMIOPUB_SCRATCH_REG_0_GC -#define RSMU_MMIOPUB_SCRATCH_REG_0_GC__RSMU_MMIOPUB_SCRATCH_REG_0_MASK 0xffffffffL - -// RSMU_VF_ENABLE_GC -#define RSMU_VF_ENABLE_GC__RSMU_VF_ENABLE_MASK 0x00000001L - -// RSMU_MGCG_CONTROL_GC -#define RSMU_MGCG_CONTROL_GC__RSMU_AXI_SLAVE_MGCG_OVERRIDE_MASK 0x00000001L -#define RSMU_MGCG_CONTROL_GC__RSMU_AXI_MASTER_MGCG_OVERRIDE_MASK 0x00000002L -#define RSMU_MGCG_CONTROL_GC__RSMU_SEC_INTR_MGCG_OVERRIDE_MASK 0x00000004L -#define RSMU_MGCG_CONTROL_GC__RSMU_PWRMGT_INTR_MGCG_OVERRIDE_MASK 0x00000008L -#define RSMU_MGCG_CONTROL_GC__RSMU_REG_WRAPPER_MGCG_OVERRIDE_MASK 0x00000010L -#define RSMU_MGCG_CONTROL_GC__RSMU_STRAP_MASTER_MGCG_OVERRIDE_MASK 0x00000020L -#define RSMU_MGCG_CONTROL_GC__RSMU_VWIRE_SRC_MGCG_OVERRIDE_MASK 0x00000040L -#define RSMU_MGCG_CONTROL_GC__RSMU_REGIF_MASTER_MGCG_OVERRIDE_MASK 0x00000080L -#define RSMU_MGCG_CONTROL_GC__RSMU_PGFSM_MGCG_OVERRIDE_MASK 0x00000100L -#define RSMU_MGCG_CONTROL_GC__RSMU_IH_MGCG_OVERRIDE_MASK 0x00000200L -#define RSMU_MGCG_CONTROL_GC__RSMU_SEM_MGCG_OVERRIDE_MASK 0x00000400L - -// RSMU_RESIDENCY_COUNTER_CNTL_GC -#define RSMU_RESIDENCY_COUNTER_CNTL_GC__RSMU_RESIDENCY_COUNTER_RESET_MASK 0x00000001L -#define RSMU_RESIDENCY_COUNTER_CNTL_GC__RSMU_RESIDENCY_COUNTER_START_MASK 0x00000002L -#define RSMU_RESIDENCY_COUNTER_CNTL_GC__RSMU_RESIDENCY_COUNTER_SELECT_MASK 0x0000003cL - -// RSMU_RESIDENCY_COUNTER_GC -#define RSMU_RESIDENCY_COUNTER_GC__RSMU_RESIDENCY_COUNTER_MASK 0xffffffffL - -// RSMU_RESIDENCY_REF_COUNTER_GC -#define RSMU_RESIDENCY_REF_COUNTER_GC__RSMU_RESIDENCY_REF_COUNTER_MASK 0xffffffffL - -// RSMU_CUSTOM_HARD_RESETB_GC -#define RSMU_CUSTOM_HARD_RESETB_GC__RSMU_CUSTOM_HARD_RESETB_MASK 0x0000000fL - -// RSMU_SEC_AXI_MASTER_ENABLE_GC -#define RSMU_SEC_AXI_MASTER_ENABLE_GC__RSMU_SEC_AXI_MASTER_ENABLE_MASK 0x00000001L - -// RSMU_SEC_SLAVE_ERROR_COUNTER_GC -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GC__RSMU_SEC_SLAVE_ERROR_COUNTER_MASK 0x0000ffffL -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GC__RSMU_SEC_SLAVE_ERROR_COUNTER_RSMU_MASK 0xffff0000L - -// RSMU_AXI_MASTER_QOS_CNTL_GC -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_MASTER_QOS_OVRD_MODE_MASK 0x00000001L -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_MASTER_QOS_OVRD_VALUE_MASK 0x0000001eL -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_AWQOS_OVRD_MODE_MASK 0x00000020L -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_AWQOS_OVRD_VALUE_MASK 0x000003c0L -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_ARQOS_OVRD_MODE_MASK 0x00000400L -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_ARQOS_OVRD_VALUE_MASK 0x00007800L - -// RSMU_MASTER_ERROR_COUNTER_GC -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_SMN_SLVERR_COUNTER_MASK 0x000000ffL -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_SMN_DECERR_COUNTER_MASK 0x0000ff00L -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_MASTER_SLVERR_COUNTER_MASK 0x00ff0000L -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_MASTER_DECERR_COUNTER_MASK 0xff000000L - -// RSMU_SLAVE_TIMEOUT_VALUE_GC -#define RSMU_SLAVE_TIMEOUT_VALUE_GC__RSMU_SLAVE_TIMEOUT_VALUE_MASK 0xffffffffL - -// RSMU_RESET_TIMEOUT_CONTROL_GC -#define RSMU_RESET_TIMEOUT_CONTROL_GC__RSMU_SLAVE_TIMEOUT_ENABLE_MASK 0x00000001L -#define RSMU_RESET_TIMEOUT_CONTROL_GC__RSMU_SLAVE_RESET_TIMEOUT_VALUE_MASK 0x000001feL - -// RSMU_SLAVE_ERROR_COUNTER_GC -#define RSMU_SLAVE_ERROR_COUNTER_GC__RSMU_SLAVE_ERROR_COUNTER_MASK 0x000000ffL - -// RSMU_AEB_LOCK_0_GC -#define RSMU_AEB_LOCK_0_GC__RSMU_AEB_LOCK_0_MASK 0xfffffff8L - -// RSMU_AEB_LOCK_1_GC -#define RSMU_AEB_LOCK_1_GC__RSMU_AEB_LOCK_1_MASK 0xffffffffL - -// RSMU_AEB_OVERRIDE_0_GC -#define RSMU_AEB_OVERRIDE_0_GC__RSMU_AEB_OVERRIDE_0_MASK 0xfffffff8L - -// RSMU_AEB_OVERRIDE_1_GC -#define RSMU_AEB_OVERRIDE_1_GC__RSMU_AEB_OVERRIDE_1_MASK 0xffffffffL - -// RSMU_SEC_INTR_ENABLE_GC -#define RSMU_SEC_INTR_ENABLE_GC__RSMU_SEC_INTR_ENABLE_MASK 0x0000ffffL - -// RSMU_SEC_INTR_TARGET_ADDR_GC -#define RSMU_SEC_INTR_TARGET_ADDR_GC__RSMU_SEC_INTR_TARGET_ADDR_MASK 0xffffffffL - -// RSMU_SEC_INTR_CONFIG_GC -#define RSMU_SEC_INTR_CONFIG_GC__RSMU_SEC_INTR_CONFIG_VC_MASK 0x00000003L - -// RSMU_SEC_INTR_STATUS_GC -#define RSMU_SEC_INTR_STATUS_GC__RSMU_SEC_INTR_STATUS_MASK 0x0000ffffL - -// RSMU_SEC_INTR_PENDING_GC -#define RSMU_SEC_INTR_PENDING_GC__RSMU_SEC_INTR_PENDING_MASK 0x0000ffffL - -// RSMU_SEC_INTR_TYPE_GC -#define RSMU_SEC_INTR_TYPE_GC__RSMU_SEC_INTR_TYPE_MASK 0x0000ffffL - -// RSMU_SEC_INTR_INTERCEPT_GC -#define RSMU_SEC_INTR_INTERCEPT_GC__RSMU_SEC_INTR_OVERRIDE_MASK 0x0000ffffL -#define RSMU_SEC_INTR_INTERCEPT_GC__RSMU_SEC_INTR_VALUE_MASK 0xffff0000L - -// RSMU_SEC_INTR_CLEAR_GC -#define RSMU_SEC_INTR_CLEAR_GC__RSMU_SEC_INTR_CLEAR_MASK 0x0000ffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_0_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_0_GC__RSMU_SEC_MASTER_TRUST_LEVEL_0_MASK 0x00ffffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_1_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_1_GC__RSMU_SEC_MASTER_TRUST_LEVEL_1_MASK 0x00ffffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_2_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_2_GC__RSMU_SEC_MASTER_TRUST_LEVEL_2_MASK 0x00ffffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_3_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_3_GC__RSMU_SEC_MASTER_TRUST_LEVEL_3_MASK 0x00ffffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_5_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_5_GC__RSMU_SEC_MASTER_TRUST_LEVEL_5_MASK 0x00ffffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_6_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_6_GC__RSMU_SEC_MASTER_TRUST_LEVEL_6_MASK 0x00ffffffL - -// RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC__RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_MASK 0x00ffffffL - -// RSMU_SEC_ACCESS_CONTROL_RSMU_GC -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE1_MASK 0x00000001L -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE2_MASK 0x00000002L -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GC__RSMU_SEC_TLVL_MASK_RSMU_RANGE2_MASK 0x000003fcL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_DEFAULT_MASK \ - 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_RW_MASK_SET0_GROUP_DEFAULT_MASK \ - 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_VF_MASK_SET0_GROUP_DEFAULT_MASK \ - 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_MASK \ - 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_DEFAULT_MASK \ - 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_RW_MASK_SET1_GROUP_DEFAULT_MASK \ - 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_VF_MASK_SET1_GROUP_DEFAULT_MASK \ - 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_DEFAULT_MASK \ - 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_DEFAULT_MASK \ - 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_DEFAULT_MASK \ - 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_DEFAULT_MASK \ - 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_DEFAULT_MASK \ - 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_DEFAULT_MASK \ - 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_DEFAULT_MASK \ - 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_DEFAULT_MASK \ - 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_0_GC -#define RSMU_SEC_START_ADDR_GROUP_0_GC__RSMU_SEC_START_ADDR_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_0_GC -#define RSMU_SEC_END_ADDR_GROUP_0_GC__RSMU_SEC_END_ADDR_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_0_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_0_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_0_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC__RSMU_SEC_RW_MASK_SET0_GROUP_0_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC__RSMU_SEC_VF_MASK_SET0_GROUP_0_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_0_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_0_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_0_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_0_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC__RSMU_SEC_RW_MASK_SET1_GROUP_0_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC__RSMU_SEC_VF_MASK_SET1_GROUP_0_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_0_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_0_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_0_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_0_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_0_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_0_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_0_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_0_MASK 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_1_GC -#define RSMU_SEC_START_ADDR_GROUP_1_GC__RSMU_SEC_START_ADDR_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_1_GC -#define RSMU_SEC_END_ADDR_GROUP_1_GC__RSMU_SEC_END_ADDR_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_1_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_1_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_1_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC__RSMU_SEC_RW_MASK_SET0_GROUP_1_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC__RSMU_SEC_VF_MASK_SET0_GROUP_1_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_1_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_1_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_1_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_1_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC__RSMU_SEC_RW_MASK_SET1_GROUP_1_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC__RSMU_SEC_VF_MASK_SET1_GROUP_1_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_1_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_1_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_1_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_1_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_1_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_1_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_1_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_1_MASK 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_2_GC -#define RSMU_SEC_START_ADDR_GROUP_2_GC__RSMU_SEC_START_ADDR_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_2_GC -#define RSMU_SEC_END_ADDR_GROUP_2_GC__RSMU_SEC_END_ADDR_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_2_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_2_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_2_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC__RSMU_SEC_RW_MASK_SET0_GROUP_2_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC__RSMU_SEC_VF_MASK_SET0_GROUP_2_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_2_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_2_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_2_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_2_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC__RSMU_SEC_RW_MASK_SET1_GROUP_2_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC__RSMU_SEC_VF_MASK_SET1_GROUP_2_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_2_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_2_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_2_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_2_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_2_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_2_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_2_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_2_MASK 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_3_GC -#define RSMU_SEC_START_ADDR_GROUP_3_GC__RSMU_SEC_START_ADDR_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_3_GC -#define RSMU_SEC_END_ADDR_GROUP_3_GC__RSMU_SEC_END_ADDR_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_3_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_3_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_3_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC__RSMU_SEC_RW_MASK_SET0_GROUP_3_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC__RSMU_SEC_VF_MASK_SET0_GROUP_3_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_3_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_3_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_3_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_3_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC__RSMU_SEC_RW_MASK_SET1_GROUP_3_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC__RSMU_SEC_VF_MASK_SET1_GROUP_3_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_3_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_3_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_3_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_3_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_3_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_3_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_3_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_3_MASK 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_4_GC -#define RSMU_SEC_START_ADDR_GROUP_4_GC__RSMU_SEC_START_ADDR_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_4_GC -#define RSMU_SEC_END_ADDR_GROUP_4_GC__RSMU_SEC_END_ADDR_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_4_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_4_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_4_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC__RSMU_SEC_RW_MASK_SET0_GROUP_4_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC__RSMU_SEC_VF_MASK_SET0_GROUP_4_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_4_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_4_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_4_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_4_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC__RSMU_SEC_RW_MASK_SET1_GROUP_4_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC__RSMU_SEC_VF_MASK_SET1_GROUP_4_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_4_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_4_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_4_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_4_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_4_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_4_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_4_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_4_MASK 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_5_GC -#define RSMU_SEC_START_ADDR_GROUP_5_GC__RSMU_SEC_START_ADDR_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_5_GC -#define RSMU_SEC_END_ADDR_GROUP_5_GC__RSMU_SEC_END_ADDR_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_5_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_5_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_5_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC__RSMU_SEC_RW_MASK_SET0_GROUP_5_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC__RSMU_SEC_VF_MASK_SET0_GROUP_5_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_5_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_5_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_5_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_5_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC__RSMU_SEC_RW_MASK_SET1_GROUP_5_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC__RSMU_SEC_VF_MASK_SET1_GROUP_5_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_5_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_5_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_5_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_5_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_5_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_5_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_5_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_5_MASK 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_6_GC -#define RSMU_SEC_START_ADDR_GROUP_6_GC__RSMU_SEC_START_ADDR_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_6_GC -#define RSMU_SEC_END_ADDR_GROUP_6_GC__RSMU_SEC_END_ADDR_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_6_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_6_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_6_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC__RSMU_SEC_RW_MASK_SET0_GROUP_6_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC__RSMU_SEC_VF_MASK_SET0_GROUP_6_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_6_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_6_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_6_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_6_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC__RSMU_SEC_RW_MASK_SET1_GROUP_6_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC__RSMU_SEC_VF_MASK_SET1_GROUP_6_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_6_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_6_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_6_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_6_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_6_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_6_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_6_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_6_MASK 0x00008000L - -// RSMU_SEC_START_ADDR_GROUP_7_GC -#define RSMU_SEC_START_ADDR_GROUP_7_GC__RSMU_SEC_START_ADDR_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_END_ADDR_GROUP_7_GC -#define RSMU_SEC_END_ADDR_GROUP_7_GC__RSMU_SEC_END_ADDR_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_INITID_MASK_SET0_GROUP_7_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_7_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_7_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC__RSMU_SEC_RW_MASK_SET0_GROUP_7_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC__RSMU_SEC_VF_MASK_SET0_GROUP_7_MASK 0x00000400L - -// RSMU_SEC_INITID_MASK_SET1_GROUP_7_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_7_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_7_MASK 0xffffffffL - -// RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_7_MASK 0x000000ffL -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC__RSMU_SEC_RW_MASK_SET1_GROUP_7_MASK 0x00000300L -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC__RSMU_SEC_VF_MASK_SET1_GROUP_7_MASK 0x00000400L - -// RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_7_MASK 0x00000007L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_7_MASK 0x00000038L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_7_MASK 0x000001c0L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_7_MASK 0x00000e00L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_7_MASK 0x00001000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_7_MASK 0x00002000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_7_MASK 0x00004000L -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_7_MASK 0x00008000L - -// RSMU_SEC_SLAVE_ERROR_LOG_REG_GC -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_ADDR_MASK 0x000fffffL -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_APERTUREID_MASK 0x00300000L -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_INITIATORID_MASK 0x3fc00000L -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_OP_MASK 0x40000000L -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_OUTSTANDING_MASK 0x80000000L - -// RSMU_MMIOSEC_SCRATCH_REG_0_GC -#define RSMU_MMIOSEC_SCRATCH_REG_0_GC__RSMU_MMIOSEC_SCRATCH_REG_0_MASK 0xffffffffL - -// nbif_gpu_HARD_RST_CTRL -#define nbif_gpu_HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L -#define nbif_gpu_HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L -#define nbif_gpu_HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L -#define nbif_gpu_HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L -#define nbif_gpu_HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L -#define nbif_gpu_HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L -#define nbif_gpu_HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L -#define nbif_gpu_HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L -#define nbif_gpu_HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L -#define nbif_gpu_HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L -#define nbif_gpu_HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L -#define nbif_gpu_HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L - -// nbif_gpu_RSMU_SOFT_RST_CTRL -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L -#define nbif_gpu_RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK 0x80000000L - -// nbif_gpu_SELF_SOFT_RST -#define nbif_gpu_SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L -#define nbif_gpu_SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L -#define nbif_gpu_SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L -#define nbif_gpu_SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L -#define nbif_gpu_SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L -#define nbif_gpu_SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L -#define nbif_gpu_SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L -#define nbif_gpu_SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L -#define nbif_gpu_SELF_SOFT_RST__SDP_PORT_RST_MASK 0x08000000L -#define nbif_gpu_SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L -#define nbif_gpu_SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L -#define nbif_gpu_SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L -#define nbif_gpu_SELF_SOFT_RST__CORE_RST_MASK 0x80000000L - -// nbif_gpu_GFX_DRV_MODE1_RST_CTRL -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L - -// nbif_gpu_BIF_RST_MISC_CTRL -#define nbif_gpu_BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L -#define nbif_gpu_BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000cL -#define nbif_gpu_BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L -#define nbif_gpu_BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L -#define nbif_gpu_BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L -#define nbif_gpu_BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001c00L -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L -#define nbif_gpu_BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x00060000L -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L - -// nbif_gpu_BIF_RST_MISC_CTRL2 -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK 0x00000001L -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK 0x00000002L -#define nbif_gpu_BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK 0x00000004L -#define nbif_gpu_BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK 0x00008000L -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L -#define nbif_gpu_BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L -#define nbif_gpu_BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L - -// nbif_gpu_BIF_RST_MISC_CTRL3 -#define nbif_gpu_BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000fL -#define nbif_gpu_BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L -#define nbif_gpu_BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L -#define nbif_gpu_BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L -#define nbif_gpu_BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001c00L -#define nbif_gpu_BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000e000L - -// nbif_gpu_BIF_RST_GFXVF_FLR_IDLE -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE_MASK 0x00000001L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE_MASK 0x00000002L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE_MASK 0x00000004L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE_MASK 0x00000008L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE_MASK 0x00000010L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE_MASK 0x00000020L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE_MASK 0x00000040L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE_MASK 0x00000080L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE_MASK 0x00000100L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE_MASK 0x00000200L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE_MASK 0x00000400L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE_MASK 0x00000800L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE_MASK 0x00001000L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE_MASK 0x00002000L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE_MASK 0x00004000L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE_MASK 0x00008000L -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK 0x80000000L - -// nbif_gpu_DEV0_PF0_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_DEV0_PF1_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_DEV0_PF2_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_DEV0_PF3_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_DEV0_PF4_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_DEV0_PF5_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_DEV0_PF6_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_DEV0_PF7_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001c0000L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L - -// nbif_gpu_BIF_INST_RESET_INTR_STS -#define nbif_gpu_BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L -#define nbif_gpu_BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L -#define nbif_gpu_BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L -#define nbif_gpu_BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L -#define nbif_gpu_BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L - -// nbif_gpu_BIF_PF_FLR_INTR_STS -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L - -// nbif_gpu_BIF_D3HOTD0_INTR_STS -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L - -// nbif_gpu_BIF_POWER_INTR_STS -#define nbif_gpu_BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L -#define nbif_gpu_BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L - -// nbif_gpu_BIF_PF_DSTATE_INTR_STS -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L - -// nbif_gpu_BIF_PF0_VF_FLR_INTR_STS -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS_MASK 0x00000001L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS_MASK 0x00000002L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS_MASK 0x00000004L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS_MASK 0x00000008L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS_MASK 0x00000010L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS_MASK 0x00000020L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS_MASK 0x00000040L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS_MASK 0x00000080L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS_MASK 0x00000100L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS_MASK 0x00000200L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS_MASK 0x00000400L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS_MASK 0x00000800L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS_MASK 0x00001000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS_MASK 0x00002000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS_MASK 0x00004000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS_MASK 0x00008000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS_MASK 0x80000000L - -// nbif_gpu_BIF_INST_RESET_INTR_MASK -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L - -// nbif_gpu_BIF_PF_FLR_INTR_MASK -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L - -// nbif_gpu_BIF_D3HOTD0_INTR_MASK -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L - -// nbif_gpu_BIF_POWER_INTR_MASK -#define nbif_gpu_BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L -#define nbif_gpu_BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L - -// nbif_gpu_BIF_PF_DSTATE_INTR_MASK -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L - -// nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK_MASK 0x00000001L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK_MASK 0x00000002L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK_MASK 0x00000004L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK_MASK 0x00000008L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK_MASK 0x00000010L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK_MASK 0x00000020L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK_MASK 0x00000040L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK_MASK 0x00000080L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK_MASK 0x00000100L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK_MASK 0x00000200L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK_MASK 0x00000400L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK_MASK 0x00000800L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK_MASK 0x00001000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK_MASK 0x00002000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK_MASK 0x00004000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK_MASK 0x00008000L -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK_MASK 0x80000000L - -// nbif_gpu_BIF_PF_FLR_RST -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L - -// nbif_gpu_BIF_PF_FLR_PROTECT -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT_MASK 0x00000001L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT_MASK 0x00000002L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT_MASK 0x00000004L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT_MASK 0x00000008L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT_MASK 0x00000010L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT_MASK 0x00000020L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT_MASK 0x00000040L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT_MASK 0x00000080L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE_MASK 0x00010000L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE_MASK 0x00020000L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE_MASK 0x00040000L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE_MASK 0x00080000L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE_MASK 0x00100000L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE_MASK 0x00200000L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE_MASK 0x00400000L -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE_MASK 0x00800000L - -// nbif_gpu_BIF_PF0_VF_FLR_RST -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L - -// nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L -#define nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L - -// nbif_gpu_BIF_GFX_VF_FLR_PROTECT -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF0_FLR_PROTECT_MASK 0x00000001L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF1_FLR_PROTECT_MASK 0x00000002L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF2_FLR_PROTECT_MASK 0x00000004L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF3_FLR_PROTECT_MASK 0x00000008L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF4_FLR_PROTECT_MASK 0x00000010L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF5_FLR_PROTECT_MASK 0x00000020L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF6_FLR_PROTECT_MASK 0x00000040L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF7_FLR_PROTECT_MASK 0x00000080L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF8_FLR_PROTECT_MASK 0x00000100L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF9_FLR_PROTECT_MASK 0x00000200L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF10_FLR_PROTECT_MASK 0x00000400L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF11_FLR_PROTECT_MASK 0x00000800L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF12_FLR_PROTECT_MASK 0x00001000L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF13_FLR_PROTECT_MASK 0x00002000L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF14_FLR_PROTECT_MASK 0x00004000L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF15_FLR_PROTECT_MASK 0x00008000L -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__PF0_SOFTPF_FLR_PROTECT_MASK 0x80000000L - -// nbif_gpu_BIF_PORT0_DSTATE_VALUE -#define nbif_gpu_BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L -#define nbif_gpu_BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L - -// nbif_gpu_MISC_SECURITY_SET -#define nbif_gpu_MISC_SECURITY_SET__SMN_VWR_SECURITY_SEL_MASK 0x00000007L -#define nbif_gpu_MISC_SECURITY_SET__SDP_VWR_SECURITY_SEL_MASK 0x00000038L -#define nbif_gpu_MISC_SECURITY_SET__BIFSELF_DMA_SECLEVEL_MASK 0x000001c0L -#define nbif_gpu_MISC_SECURITY_SET__CFG_RSP_DBGMSK_MASK 0x00000200L -#define nbif_gpu_MISC_SECURITY_SET__MMIO_RSP_DBGMSK_MASK 0x00000400L - -// nbif_gpu_MISC_SCRATCH -#define nbif_gpu_MISC_SCRATCH__MISC_SCRATCH0_MASK 0xffffffffL - -// nbif_gpu_INTR_LINE_POLARITY -#define nbif_gpu_INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000ffL - -// nbif_gpu_INTR_LINE_ENABLE -#define nbif_gpu_INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000ffL - -// nbif_gpu_OUTSTANDING_VC_ALLOC -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000cL -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000c0L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000c00L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000c000L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000f0000L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0c000000L -#define nbif_gpu_OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xf0000000L - -// nbif_gpu_BIFC_MISC_CTRL0 -#define nbif_gpu_BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L -#define nbif_gpu_BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L -#define nbif_gpu_BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L -#define nbif_gpu_BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L -#define nbif_gpu_BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L -#define nbif_gpu_BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L -#define nbif_gpu_BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L -#define nbif_gpu_BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L - -// nbif_gpu_BIFC_MISC_CTRL1 -#define nbif_gpu_BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L -#define nbif_gpu_BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L -#define nbif_gpu_BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L -#define nbif_gpu_BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L -#define nbif_gpu_BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L -#define nbif_gpu_BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L -#define nbif_gpu_BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0x00000080L -#define nbif_gpu_BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L -#define nbif_gpu_BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000c00L -#define nbif_gpu_BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L -#define nbif_gpu_BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L -#define nbif_gpu_BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L -#define nbif_gpu_BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L - -// nbif_gpu_BIFC_BME_ERR_LOG -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F1_MASK 0x00000002L -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F2_MASK 0x00000004L -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F3_MASK 0x00000008L -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F4_MASK 0x00000010L -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F5_MASK 0x00000020L -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F6_MASK 0x00000040L -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F7_MASK 0x00000080L -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F1_MASK 0x00020000L -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F2_MASK 0x00040000L -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F3_MASK 0x00080000L -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F4_MASK 0x00100000L -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F5_MASK 0x00200000L -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F6_MASK 0x00400000L -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F7_MASK 0x00800000L - -// nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000cL -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000c0L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000c00L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000c0000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00c00000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0c000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000cL -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000c0L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000c00L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000c0000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00c00000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0c000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000cL -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000c0L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000c00L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000c0000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00c00000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0c000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000cL -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000c0L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000c00L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000c0000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00c00000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0c000000L -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L - -// nbif_gpu_NBIF_VWIRE_CTRL -#define nbif_gpu_NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L -#define nbif_gpu_NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000f0L -#define nbif_gpu_NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L -#define nbif_gpu_NBIF_VWIRE_CTRL__SMN_VWR_DBGMSK_MASK 0x00000200L -#define nbif_gpu_NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L -#define nbif_gpu_NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00f00000L -#define nbif_gpu_NBIF_VWIRE_CTRL__SDP_VWR_DBGMSK_MASK 0x02000000L -#define nbif_gpu_NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0c000000L - -// nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L - -// nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L - -// nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L - -// nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L - -// nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L - -// nbif_gpu_NBIF_MGCG_CTRL -#define nbif_gpu_NBIF_MGCG_CTRL__NBIF_MGCG_EN_MASK 0x00000001L -#define nbif_gpu_NBIF_MGCG_CTRL__NBIF_MGCG_MODE_MASK 0x00000002L -#define nbif_gpu_NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS_MASK 0x000003fcL - -// nbif_gpu_NBIF_DS_CTRL_LCLK -#define nbif_gpu_NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L -#define nbif_gpu_NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xffff0000L - -// nbif_gpu_SMN_MST_CNTL0 -#define nbif_gpu_SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L -#define nbif_gpu_SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L -#define nbif_gpu_SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L -#define nbif_gpu_SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L -#define nbif_gpu_SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L - -// nbif_gpu_SMN_MST_EP_CNTL1 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L - -// nbif_gpu_SMN_MST_EP_CNTL2 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L - -// nbif_gpu_SMN_MST_EP_CNTL3 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L - -// nbif_gpu_SMN_MST_EP_CNTL4 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L - -// nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L - -// nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L - -// nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L - -// nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L - -// nbif_gpu_BME_DUMMY_CNTL_0 -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000cL -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000c0L -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000c00L -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000c000L - -// nbif_gpu_BIFC_THT_CNTL -#define nbif_gpu_BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000fL -#define nbif_gpu_BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000f0L -#define nbif_gpu_BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000f00L - -// nbif_gpu_BIFC_HSTARB_CNTL -#define nbif_gpu_BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L - -// nbif_gpu_BIFC_GSI_CNTL -#define nbif_gpu_BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001cL -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L -#define nbif_gpu_BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000c00L -#define nbif_gpu_BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L - -// nbif_gpu_BIFC_PCIEFUNC_CNTL -#define nbif_gpu_BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000ffffL -#define nbif_gpu_BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L - -// nbif_gpu_BIFC_SDP_CNTL_0 -#define nbif_gpu_BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x0000003fL -#define nbif_gpu_BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x00000fc0L -#define nbif_gpu_BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x0003f000L -#define nbif_gpu_BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0x00fc0000L -#define nbif_gpu_BIFC_SDP_CNTL_0__RCC_GMI_DBGMSK_MASK 0x01000000L -#define nbif_gpu_BIFC_SDP_CNTL_0__BIH_GMI_DBGMSK_MASK 0x02000000L - -// nbif_gpu_BIFC_PERF_CNTL_0 -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x001f0000L -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x1f000000L - -// nbif_gpu_BIFC_PERF_CNTL_1 -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x003f0000L -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x7f000000L - -// nbif_gpu_BIFC_PERF_CNT_MMIO_RD -#define nbif_gpu_BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xffffffffL - -// nbif_gpu_BIFC_PERF_CNT_MMIO_WR -#define nbif_gpu_BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xffffffffL - -// nbif_gpu_BIFC_PERF_CNT_DMA_RD -#define nbif_gpu_BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xffffffffL - -// nbif_gpu_BIFC_PERF_CNT_DMA_WR -#define nbif_gpu_BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xffffffffL - -// nbif_gpu_NBIF_REGIF_ERRSET_CTRL -#define nbif_gpu_NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L - -// nbif_gpu_BIF_RAS_LEAF0_CTRL -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_BIF_RAS_LEAF1_CTRL -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_BIF_RAS_LEAF2_CTRL -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_BIF_RAS_MISC_CTRL -#define nbif_gpu_BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN_MASK 0x00000001L - -// nbif_gpu_SUM_INDEX -#define nbif_gpu_SUM_INDEX__SUM_INDEX_MASK 0xffffffffL - -// nbif_gpu_SUM_DATA -#define nbif_gpu_SUM_DATA__SUM_DATA_MASK 0xffffffffL - -// nbif_gpu_SBIOS_SCRATCH_0 -#define nbif_gpu_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xffffffffL - -// nbif_gpu_SBIOS_SCRATCH_1 -#define nbif_gpu_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xffffffffL - -// nbif_gpu_SBIOS_SCRATCH_2 -#define nbif_gpu_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xffffffffL - -// nbif_gpu_SBIOS_SCRATCH_3 -#define nbif_gpu_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xffffffffL - -// nbif_gpu_BIF_RLC_INTR_CNTL -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L - -// nbif_gpu_BIF_VCE_INTR_CNTL -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L - -// nbif_gpu_BIF_UVD_INTR_CNTL -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR0 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR1 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR2 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR3 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR4 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR5 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR6 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR7 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000fffffL - -// nbif_gpu_GFX_MMIOREG_CAM_CNTL -#define nbif_gpu_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000ffL - -// nbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL -#define nbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xffffffffL - -// nbif_gpu_GFX_MMIOREG_CAM_ONE_CPL -#define nbif_gpu_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xffffffffL - -// nbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL -#define nbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xffffffffL - -// nbif_gpu_MM_INDEX -#define nbif_gpu_MM_INDEX__MM_OFFSET_MASK 0x7fffffffL -#define nbif_gpu_MM_INDEX__MM_APER_MASK 0x80000000L - -// nbif_gpu_MM_INDEX_HI -#define nbif_gpu_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffffL - -// nbif_gpu_MM_DATA -#define nbif_gpu_MM_DATA__MM_DATA_MASK 0xffffffffL - -// nbif_gpu_SYSHUB_INDEX_OVLP -#define nbif_gpu_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003fffffL - -// nbif_gpu_SYSHUB_DATA_OVLP -#define nbif_gpu_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIE_INDEX -#define nbif_gpu_PCIE_INDEX__PCIE_INDEX_MASK 0xffffffffL - -// nbif_gpu_PCIE_DATA -#define nbif_gpu_PCIE_DATA__PCIE_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIE_INDEX2 -#define nbif_gpu_PCIE_INDEX2__PCIE_INDEX2_MASK 0xffffffffL - -// nbif_gpu_PCIE_DATA2 -#define nbif_gpu_PCIE_DATA2__PCIE_DATA2_MASK 0xffffffffL - -// nbif_gpu_CC_BIF_BX_STRAP0 -#define nbif_gpu_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xfe000000L - -// nbif_gpu_CC_BIF_BX_PINSTRAP0 - -// nbif_gpu_CC_BIF_BX_FUSESTRAP0 -#define nbif_gpu_CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x00000002L - -// nbif_gpu_BIF_MM_INDACCESS_CNTL -#define nbif_gpu_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L -#define nbif_gpu_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L - -// nbif_gpu_BUS_CNTL -#define nbif_gpu_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L -#define nbif_gpu_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L -#define nbif_gpu_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L -#define nbif_gpu_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L -#define nbif_gpu_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L -#define nbif_gpu_BUS_CNTL__SET_AZ_TC_MASK 0x00001c00L -#define nbif_gpu_BUS_CNTL__SET_MC_TC_MASK 0x0000e000L -#define nbif_gpu_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L -#define nbif_gpu_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L -#define nbif_gpu_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L -#define nbif_gpu_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L - -// nbif_gpu_BIF_SCRATCH0 -#define nbif_gpu_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffffL - -// nbif_gpu_BIF_SCRATCH1 -#define nbif_gpu_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffffL - -// nbif_gpu_BX_RESET_EN -#define nbif_gpu_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L -#define nbif_gpu_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L -#define nbif_gpu_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L -#define nbif_gpu_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L -#define nbif_gpu_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L - -// nbif_gpu_MM_CFGREGS_CNTL -#define nbif_gpu_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L -#define nbif_gpu_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000c0L -#define nbif_gpu_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L - -// nbif_gpu_HW_DEBUG -#define nbif_gpu_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define nbif_gpu_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define nbif_gpu_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define nbif_gpu_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define nbif_gpu_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define nbif_gpu_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define nbif_gpu_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define nbif_gpu_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define nbif_gpu_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define nbif_gpu_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define nbif_gpu_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define nbif_gpu_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define nbif_gpu_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define nbif_gpu_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define nbif_gpu_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define nbif_gpu_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L -#define nbif_gpu_HW_DEBUG__HW_16_DEBUG_MASK 0x00010000L -#define nbif_gpu_HW_DEBUG__HW_17_DEBUG_MASK 0x00020000L -#define nbif_gpu_HW_DEBUG__HW_18_DEBUG_MASK 0x00040000L -#define nbif_gpu_HW_DEBUG__HW_19_DEBUG_MASK 0x00080000L -#define nbif_gpu_HW_DEBUG__HW_20_DEBUG_MASK 0x00100000L -#define nbif_gpu_HW_DEBUG__HW_21_DEBUG_MASK 0x00200000L -#define nbif_gpu_HW_DEBUG__HW_22_DEBUG_MASK 0x00400000L -#define nbif_gpu_HW_DEBUG__HW_23_DEBUG_MASK 0x00800000L -#define nbif_gpu_HW_DEBUG__HW_24_DEBUG_MASK 0x01000000L -#define nbif_gpu_HW_DEBUG__HW_25_DEBUG_MASK 0x02000000L -#define nbif_gpu_HW_DEBUG__HW_26_DEBUG_MASK 0x04000000L -#define nbif_gpu_HW_DEBUG__HW_27_DEBUG_MASK 0x08000000L -#define nbif_gpu_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000L -#define nbif_gpu_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000L -#define nbif_gpu_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000L -#define nbif_gpu_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000L - -// nbif_gpu_BX_RESET_CNTL -#define nbif_gpu_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L - -// nbif_gpu_INTERRUPT_CNTL -#define nbif_gpu_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L -#define nbif_gpu_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L -#define nbif_gpu_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L -#define nbif_gpu_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000f0L -#define nbif_gpu_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L -#define nbif_gpu_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L - -// nbif_gpu_INTERRUPT_CNTL2 -#define nbif_gpu_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffffL - -// nbif_gpu_CLKREQB_PAD_CNTL -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK 0xff000000L - -// nbif_gpu_CLKREQB_PERF_COUNTER -#define nbif_gpu_CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK 0xffffffffL - -// nbif_gpu_BIF_CLK_CTRL -#define nbif_gpu_BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK 0x00000001L -#define nbif_gpu_BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x00000002L - -// nbif_gpu_BIF_FEATURES_CONTROL_MISC -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x00000200L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x00000400L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000800L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK \ - 0x01000000L - -// nbif_gpu_BIF_DOORBELL_CNTL -#define nbif_gpu_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L -#define nbif_gpu_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L -#define nbif_gpu_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L -#define nbif_gpu_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L -#define nbif_gpu_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L - -// nbif_gpu_BIF_DOORBELL_INT_CNTL -#define nbif_gpu_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L -#define nbif_gpu_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L - -// nbif_gpu_BIF_SLVARB_MODE -#define nbif_gpu_BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x00000003L - -// nbif_gpu_BIF_FB_EN -#define nbif_gpu_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L -#define nbif_gpu_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L - -// nbif_gpu_BIF_BUSY_DELAY_CNTR -#define nbif_gpu_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003fL - -// nbif_gpu_BIF_PERFMON_CNTL -#define nbif_gpu_BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x00000001L -#define nbif_gpu_BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x00000002L -#define nbif_gpu_BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x00000004L -#define nbif_gpu_BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x00001f00L -#define nbif_gpu_BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x0003e000L - -// nbif_gpu_BIF_PERFCOUNTER0_RESULT -#define nbif_gpu_BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL - -// nbif_gpu_BIF_PERFCOUNTER1_RESULT -#define nbif_gpu_BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL - -// nbif_gpu_BIF_MST_TRANS_PENDING_VF -#define nbif_gpu_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000ffffL - -// nbif_gpu_BIF_SLV_TRANS_PENDING_VF -#define nbif_gpu_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000ffffL - -// nbif_gpu_BACO_CNTL -#define nbif_gpu_BACO_CNTL__BACO_EN_MASK 0x00000001L -#define nbif_gpu_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L -#define nbif_gpu_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L -#define nbif_gpu_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L -#define nbif_gpu_BACO_CNTL__BACO_MODE_MASK 0x00000100L -#define nbif_gpu_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L -#define nbif_gpu_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L - -// nbif_gpu_BIF_BACO_EXIT_TIME0 -#define nbif_gpu_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000fffffL - -// nbif_gpu_BIF_BACO_EXIT_TIMER1 -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000fffffL -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L - -// nbif_gpu_BIF_BACO_EXIT_TIMER2 -#define nbif_gpu_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000fffffL - -// nbif_gpu_BIF_BACO_EXIT_TIMER3 -#define nbif_gpu_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000fffffL - -// nbif_gpu_BIF_BACO_EXIT_TIMER4 -#define nbif_gpu_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000fffffL - -// nbif_gpu_MEM_TYPE_CNTL -#define nbif_gpu_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L - -// nbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS -#define nbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L - -// nbif_gpu_BIF_VDDGFX_GFX0_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_GFX0_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_GFX1_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_GFX1_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_GFX2_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_GFX2_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_GFX3_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_GFX3_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_GFX4_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_GFX4_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_GFX5_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_GFX5_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_RSV1_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_RSV1_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_RSV2_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_RSV2_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_RSV3_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_RSV3_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_RSV4_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003fffcL -#define nbif_gpu_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L -#define nbif_gpu_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L - -// nbif_gpu_BIF_VDDGFX_RSV4_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003fffcL - -// nbif_gpu_BIF_VDDGFX_FB_CMP -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L - -// nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER -#define nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000ffcL -#define nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L - -// nbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER -#define nbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000ffcL - -// nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER -#define nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000ffcL -#define nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L - -// nbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER -#define nbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000ffcL - -// nbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL -#define nbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007fffcL - -// nbif_gpu_REMAP_HDP_REG_FLUSH_CNTL -#define nbif_gpu_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007fffcL - -// nbif_gpu_BIF_RB_CNTL -#define nbif_gpu_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define nbif_gpu_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003eL -#define nbif_gpu_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L -#define nbif_gpu_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L -#define nbif_gpu_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L -#define nbif_gpu_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L - -// nbif_gpu_BIF_RB_BASE -#define nbif_gpu_BIF_RB_BASE__ADDR_MASK 0xffffffffL - -// nbif_gpu_BIF_RB_RPTR -#define nbif_gpu_BIF_RB_RPTR__OFFSET_MASK 0x0003fffcL - -// nbif_gpu_BIF_RB_WPTR -#define nbif_gpu_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L -#define nbif_gpu_BIF_RB_WPTR__OFFSET_MASK 0x0003fffcL - -// nbif_gpu_BIF_RB_WPTR_ADDR_HI -#define nbif_gpu_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL - -// nbif_gpu_BIF_RB_WPTR_ADDR_LO -#define nbif_gpu_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// nbif_gpu_MAILBOX_INDEX -#define nbif_gpu_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001fL - -// nbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION -#define nbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffffL - -// nbif_gpu_BIF_GMI_WRR_WEIGHT -#define nbif_gpu_BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT_MASK 0x000000ffL -#define nbif_gpu_BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT_MASK 0x0000ff00L -#define nbif_gpu_BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT_MASK 0x00ff0000L - -// nbif_gpu_NBIF_STRAP_WRITE_CTRL -#define nbif_gpu_NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L - -// nbif_gpu_BIF_BME_STATUS -#define nbif_gpu_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L -#define nbif_gpu_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L - -// nbif_gpu_BIF_ATOMIC_ERR_LOG -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L - -// nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK \ - 0xffffffffL - -// nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK \ - 0xffffffffL - -// nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x0000ff00L - -// nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL -#define nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L - -// nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL -#define nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L - -// nbif_gpu_GPU_HDP_FLUSH_REQ -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L -#define nbif_gpu_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L - -// nbif_gpu_GPU_HDP_FLUSH_DONE -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L -#define nbif_gpu_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L - -// nbif_gpu_BIF_TRANS_PENDING -#define nbif_gpu_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L -#define nbif_gpu_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xffffffffL - -// nbif_gpu_MAILBOX_CONTROL -#define nbif_gpu_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L -#define nbif_gpu_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L -#define nbif_gpu_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L -#define nbif_gpu_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L - -// nbif_gpu_MAILBOX_INT_CNTL -#define nbif_gpu_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L -#define nbif_gpu_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L - -// nbif_gpu_BIF_VMHV_MAILBOX -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000f00L -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000f0000L -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L - -// nbif_gpu_VENDOR_ID_epf -#define nbif_gpu_VENDOR_ID_epf__VENDOR_ID_MASK 0x0000ffffL - -// nbif_gpu_DEVICE_ID_epf -#define nbif_gpu_DEVICE_ID_epf__DEVICE_ID_MASK 0x0000ffffL - -// nbif_gpu_COMMAND_epf -#define nbif_gpu_COMMAND_epf__IO_ACCESS_EN_MASK 0x00000001L -#define nbif_gpu_COMMAND_epf__MEM_ACCESS_EN_MASK 0x00000002L -#define nbif_gpu_COMMAND_epf__BUS_MASTER_EN_MASK 0x00000004L -#define nbif_gpu_COMMAND_epf__SPECIAL_CYCLE_EN_MASK 0x00000008L -#define nbif_gpu_COMMAND_epf__MEM_WRITE_INVALIDATE_EN_MASK 0x00000010L -#define nbif_gpu_COMMAND_epf__PAL_SNOOP_EN_MASK 0x00000020L -#define nbif_gpu_COMMAND_epf__PARITY_ERROR_RESPONSE_MASK 0x00000040L -#define nbif_gpu_COMMAND_epf__AD_STEPPING_MASK 0x00000080L -#define nbif_gpu_COMMAND_epf__SERR_EN_MASK 0x00000100L -#define nbif_gpu_COMMAND_epf__FAST_B2B_EN_MASK 0x00000200L -#define nbif_gpu_COMMAND_epf__INT_DIS_MASK 0x00000400L - -// nbif_gpu_STATUS_epf -#define nbif_gpu_STATUS_epf__INT_STATUS_MASK 0x00000008L -#define nbif_gpu_STATUS_epf__CAP_LIST_MASK 0x00000010L -#define nbif_gpu_STATUS_epf__PCI_66_EN_MASK 0x00000020L -#define nbif_gpu_STATUS_epf__FAST_BACK_CAPABLE_MASK 0x00000080L -#define nbif_gpu_STATUS_epf__MASTER_DATA_PARITY_ERROR_MASK 0x00000100L -#define nbif_gpu_STATUS_epf__DEVSEL_TIMING_MASK 0x00000600L -#define nbif_gpu_STATUS_epf__SIGNAL_TARGET_ABORT_MASK 0x00000800L -#define nbif_gpu_STATUS_epf__RECEIVED_TARGET_ABORT_MASK 0x00001000L -#define nbif_gpu_STATUS_epf__RECEIVED_MASTER_ABORT_MASK 0x00002000L -#define nbif_gpu_STATUS_epf__SIGNALED_SYSTEM_ERROR_MASK 0x00004000L -#define nbif_gpu_STATUS_epf__PARITY_ERROR_DETECTED_MASK 0x00008000L - -// nbif_gpu_REVISION_ID_epf -#define nbif_gpu_REVISION_ID_epf__MINOR_REV_ID_MASK 0x0000000fL -#define nbif_gpu_REVISION_ID_epf__MAJOR_REV_ID_MASK 0x000000f0L - -// nbif_gpu_PROG_INTERFACE_epf -#define nbif_gpu_PROG_INTERFACE_epf__PROG_INTERFACE_MASK 0x000000ffL - -// nbif_gpu_SUB_CLASS_epf -#define nbif_gpu_SUB_CLASS_epf__SUB_CLASS_MASK 0x000000ffL - -// nbif_gpu_BASE_CLASS_epf -#define nbif_gpu_BASE_CLASS_epf__BASE_CLASS_MASK 0x000000ffL - -// nbif_gpu_CACHE_LINE_epf -#define nbif_gpu_CACHE_LINE_epf__CACHE_LINE_SIZE_MASK 0x000000ffL - -// nbif_gpu_LATENCY_epf -#define nbif_gpu_LATENCY_epf__LATENCY_TIMER_MASK 0x000000ffL - -// nbif_gpu_HEADER_epf -#define nbif_gpu_HEADER_epf__HEADER_TYPE_MASK 0x0000007fL -#define nbif_gpu_HEADER_epf__DEVICE_TYPE_MASK 0x00000080L - -// nbif_gpu_BIST_epf -#define nbif_gpu_BIST_epf__BIST_COMP_MASK 0x0000000fL -#define nbif_gpu_BIST_epf__BIST_STRT_MASK 0x00000040L -#define nbif_gpu_BIST_epf__BIST_CAP_MASK 0x00000080L - -// nbif_gpu_BASE_ADDR_1_epf -#define nbif_gpu_BASE_ADDR_1_epf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_2_epf -#define nbif_gpu_BASE_ADDR_2_epf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_3_epf -#define nbif_gpu_BASE_ADDR_3_epf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_4_epf -#define nbif_gpu_BASE_ADDR_4_epf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_5_epf -#define nbif_gpu_BASE_ADDR_5_epf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_6_epf -#define nbif_gpu_BASE_ADDR_6_epf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_ROM_BASE_ADDR_epf -#define nbif_gpu_ROM_BASE_ADDR_epf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_CAP_PTR_epf -#define nbif_gpu_CAP_PTR_epf__CAP_PTR_MASK 0x000000ffL - -// nbif_gpu_INTERRUPT_LINE_epf -#define nbif_gpu_INTERRUPT_LINE_epf__INTERRUPT_LINE_MASK 0x000000ffL - -// nbif_gpu_INTERRUPT_PIN_epf -#define nbif_gpu_INTERRUPT_PIN_epf__INTERRUPT_PIN_MASK 0x000000ffL - -// nbif_gpu_ADAPTER_ID_epf -#define nbif_gpu_ADAPTER_ID_epf__SUBSYSTEM_VENDOR_ID_MASK 0x0000ffffL -#define nbif_gpu_ADAPTER_ID_epf__SUBSYSTEM_ID_MASK 0xffff0000L - -// nbif_gpu_MIN_GRANT_epf -#define nbif_gpu_MIN_GRANT_epf__MIN_GNT_MASK 0x000000ffL - -// nbif_gpu_MAX_LATENCY_epf -#define nbif_gpu_MAX_LATENCY_epf__MAX_LAT_MASK 0x000000ffL - -// nbif_gpu_VENDOR_CAP_LIST_epf -#define nbif_gpu_VENDOR_CAP_LIST_epf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_VENDOR_CAP_LIST_epf__NEXT_PTR_MASK 0x0000ff00L -#define nbif_gpu_VENDOR_CAP_LIST_epf__LENGTH_MASK 0x00ff0000L - -// nbif_gpu_ADAPTER_ID_W_epf -#define nbif_gpu_ADAPTER_ID_W_epf__SUBSYSTEM_VENDOR_ID_MASK 0x0000ffffL -#define nbif_gpu_ADAPTER_ID_W_epf__SUBSYSTEM_ID_MASK 0xffff0000L - -// nbif_gpu_PMI_CAP_LIST_epf -#define nbif_gpu_PMI_CAP_LIST_epf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_PMI_CAP_LIST_epf__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_PMI_CAP_epf -#define nbif_gpu_PMI_CAP_epf__VERSION_MASK 0x00000007L -#define nbif_gpu_PMI_CAP_epf__PME_CLOCK_MASK 0x00000008L -#define nbif_gpu_PMI_CAP_epf__DEV_SPECIFIC_INIT_MASK 0x00000020L -#define nbif_gpu_PMI_CAP_epf__AUX_CURRENT_MASK 0x000001c0L -#define nbif_gpu_PMI_CAP_epf__D1_SUPPORT_MASK 0x00000200L -#define nbif_gpu_PMI_CAP_epf__D2_SUPPORT_MASK 0x00000400L -#define nbif_gpu_PMI_CAP_epf__PME_SUPPORT_MASK 0x0000f800L - -// nbif_gpu_PMI_STATUS_CNTL_epf -#define nbif_gpu_PMI_STATUS_CNTL_epf__POWER_STATE_MASK 0x00000003L -#define nbif_gpu_PMI_STATUS_CNTL_epf__NO_SOFT_RESET_MASK 0x00000008L -#define nbif_gpu_PMI_STATUS_CNTL_epf__PME_EN_MASK 0x00000100L -#define nbif_gpu_PMI_STATUS_CNTL_epf__DATA_SELECT_MASK 0x00001e00L -#define nbif_gpu_PMI_STATUS_CNTL_epf__DATA_SCALE_MASK 0x00006000L -#define nbif_gpu_PMI_STATUS_CNTL_epf__PME_STATUS_MASK 0x00008000L -#define nbif_gpu_PMI_STATUS_CNTL_epf__B2_B3_SUPPORT_MASK 0x00400000L -#define nbif_gpu_PMI_STATUS_CNTL_epf__BUS_PWR_EN_MASK 0x00800000L -#define nbif_gpu_PMI_STATUS_CNTL_epf__PMI_DATA_MASK 0xff000000L - -// nbif_gpu_PCIE_CAP_LIST_epf -#define nbif_gpu_PCIE_CAP_LIST_epf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_PCIE_CAP_LIST_epf__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_PCIE_CAP_epf -#define nbif_gpu_PCIE_CAP_epf__VERSION_MASK 0x0000000fL -#define nbif_gpu_PCIE_CAP_epf__DEVICE_TYPE_MASK 0x000000f0L -#define nbif_gpu_PCIE_CAP_epf__SLOT_IMPLEMENTED_MASK 0x00000100L -#define nbif_gpu_PCIE_CAP_epf__INT_MESSAGE_NUM_MASK 0x00003e00L - -// nbif_gpu_DEVICE_CAP_epf -#define nbif_gpu_DEVICE_CAP_epf__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L -#define nbif_gpu_DEVICE_CAP_epf__PHANTOM_FUNC_MASK 0x00000018L -#define nbif_gpu_DEVICE_CAP_epf__EXTENDED_TAG_MASK 0x00000020L -#define nbif_gpu_DEVICE_CAP_epf__L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0L -#define nbif_gpu_DEVICE_CAP_epf__L1_ACCEPTABLE_LATENCY_MASK 0x00000e00L -#define nbif_gpu_DEVICE_CAP_epf__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L -#define nbif_gpu_DEVICE_CAP_epf__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03fc0000L -#define nbif_gpu_DEVICE_CAP_epf__CAPTURED_SLOT_POWER_SCALE_MASK 0x0c000000L -#define nbif_gpu_DEVICE_CAP_epf__FLR_CAPABLE_MASK 0x10000000L - -// nbif_gpu_DEVICE_CNTL_epf -#define nbif_gpu_DEVICE_CNTL_epf__CORR_ERR_EN_MASK 0x00000001L -#define nbif_gpu_DEVICE_CNTL_epf__NON_FATAL_ERR_EN_MASK 0x00000002L -#define nbif_gpu_DEVICE_CNTL_epf__FATAL_ERR_EN_MASK 0x00000004L -#define nbif_gpu_DEVICE_CNTL_epf__USR_REPORT_EN_MASK 0x00000008L -#define nbif_gpu_DEVICE_CNTL_epf__RELAXED_ORD_EN_MASK 0x00000010L -#define nbif_gpu_DEVICE_CNTL_epf__MAX_PAYLOAD_SIZE_MASK 0x000000e0L -#define nbif_gpu_DEVICE_CNTL_epf__EXTENDED_TAG_EN_MASK 0x00000100L -#define nbif_gpu_DEVICE_CNTL_epf__PHANTOM_FUNC_EN_MASK 0x00000200L -#define nbif_gpu_DEVICE_CNTL_epf__AUX_POWER_PM_EN_MASK 0x00000400L -#define nbif_gpu_DEVICE_CNTL_epf__NO_SNOOP_EN_MASK 0x00000800L -#define nbif_gpu_DEVICE_CNTL_epf__MAX_READ_REQUEST_SIZE_MASK 0x00007000L -#define nbif_gpu_DEVICE_CNTL_epf__INITIATE_FLR_MASK 0x00008000L - -// nbif_gpu_DEVICE_STATUS_epf -#define nbif_gpu_DEVICE_STATUS_epf__CORR_ERR_MASK 0x00000001L -#define nbif_gpu_DEVICE_STATUS_epf__NON_FATAL_ERR_MASK 0x00000002L -#define nbif_gpu_DEVICE_STATUS_epf__FATAL_ERR_MASK 0x00000004L -#define nbif_gpu_DEVICE_STATUS_epf__USR_DETECTED_MASK 0x00000008L -#define nbif_gpu_DEVICE_STATUS_epf__AUX_PWR_MASK 0x00000010L -#define nbif_gpu_DEVICE_STATUS_epf__TRANSACTIONS_PEND_MASK 0x00000020L - -// nbif_gpu_LINK_CAP_epf -#define nbif_gpu_LINK_CAP_epf__LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_CAP_epf__LINK_WIDTH_MASK 0x000003f0L -#define nbif_gpu_LINK_CAP_epf__PM_SUPPORT_MASK 0x00000c00L -#define nbif_gpu_LINK_CAP_epf__L0S_EXIT_LATENCY_MASK 0x00007000L -#define nbif_gpu_LINK_CAP_epf__L1_EXIT_LATENCY_MASK 0x00038000L -#define nbif_gpu_LINK_CAP_epf__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L -#define nbif_gpu_LINK_CAP_epf__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L -#define nbif_gpu_LINK_CAP_epf__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L -#define nbif_gpu_LINK_CAP_epf__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L -#define nbif_gpu_LINK_CAP_epf__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L -#define nbif_gpu_LINK_CAP_epf__PORT_NUMBER_MASK 0xff000000L - -// nbif_gpu_LINK_CNTL_epf -#define nbif_gpu_LINK_CNTL_epf__PM_CONTROL_MASK 0x00000003L -#define nbif_gpu_LINK_CNTL_epf__READ_CPL_BOUNDARY_MASK 0x00000008L -#define nbif_gpu_LINK_CNTL_epf__LINK_DIS_MASK 0x00000010L -#define nbif_gpu_LINK_CNTL_epf__RETRAIN_LINK_MASK 0x00000020L -#define nbif_gpu_LINK_CNTL_epf__COMMON_CLOCK_CFG_MASK 0x00000040L -#define nbif_gpu_LINK_CNTL_epf__EXTENDED_SYNC_MASK 0x00000080L -#define nbif_gpu_LINK_CNTL_epf__CLOCK_POWER_MANAGEMENT_EN_MASK 0x00000100L -#define nbif_gpu_LINK_CNTL_epf__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x00000200L -#define nbif_gpu_LINK_CNTL_epf__LINK_BW_MANAGEMENT_INT_EN_MASK 0x00000400L -#define nbif_gpu_LINK_CNTL_epf__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x00000800L - -// nbif_gpu_LINK_STATUS_epf -#define nbif_gpu_LINK_STATUS_epf__CURRENT_LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_STATUS_epf__NEGOTIATED_LINK_WIDTH_MASK 0x000003f0L -#define nbif_gpu_LINK_STATUS_epf__LINK_TRAINING_MASK 0x00000800L -#define nbif_gpu_LINK_STATUS_epf__SLOT_CLOCK_CFG_MASK 0x00001000L -#define nbif_gpu_LINK_STATUS_epf__DL_ACTIVE_MASK 0x00002000L -#define nbif_gpu_LINK_STATUS_epf__LINK_BW_MANAGEMENT_STATUS_MASK 0x00004000L -#define nbif_gpu_LINK_STATUS_epf__LINK_AUTONOMOUS_BW_STATUS_MASK 0x00008000L - -// nbif_gpu_DEVICE_CAP2_epf -#define nbif_gpu_DEVICE_CAP2_epf__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000fL -#define nbif_gpu_DEVICE_CAP2_epf__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L -#define nbif_gpu_DEVICE_CAP2_epf__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L -#define nbif_gpu_DEVICE_CAP2_epf__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L -#define nbif_gpu_DEVICE_CAP2_epf__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L -#define nbif_gpu_DEVICE_CAP2_epf__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L -#define nbif_gpu_DEVICE_CAP2_epf__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L -#define nbif_gpu_DEVICE_CAP2_epf__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L -#define nbif_gpu_DEVICE_CAP2_epf__LTR_SUPPORTED_MASK 0x00000800L -#define nbif_gpu_DEVICE_CAP2_epf__TPH_CPLR_SUPPORTED_MASK 0x00003000L -#define nbif_gpu_DEVICE_CAP2_epf__OBFF_SUPPORTED_MASK 0x000c0000L -#define nbif_gpu_DEVICE_CAP2_epf__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L -#define nbif_gpu_DEVICE_CAP2_epf__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L -#define nbif_gpu_DEVICE_CAP2_epf__MAX_END_END_TLP_PREFIXES_MASK 0x00c00000L - -// nbif_gpu_DEVICE_CNTL2_epf -#define nbif_gpu_DEVICE_CNTL2_epf__CPL_TIMEOUT_VALUE_MASK 0x0000000fL -#define nbif_gpu_DEVICE_CNTL2_epf__CPL_TIMEOUT_DIS_MASK 0x00000010L -#define nbif_gpu_DEVICE_CNTL2_epf__ARI_FORWARDING_EN_MASK 0x00000020L -#define nbif_gpu_DEVICE_CNTL2_epf__ATOMICOP_REQUEST_EN_MASK 0x00000040L -#define nbif_gpu_DEVICE_CNTL2_epf__ATOMICOP_EGRESS_BLOCKING_MASK 0x00000080L -#define nbif_gpu_DEVICE_CNTL2_epf__IDO_REQUEST_ENABLE_MASK 0x00000100L -#define nbif_gpu_DEVICE_CNTL2_epf__IDO_COMPLETION_ENABLE_MASK 0x00000200L -#define nbif_gpu_DEVICE_CNTL2_epf__LTR_EN_MASK 0x00000400L -#define nbif_gpu_DEVICE_CNTL2_epf__OBFF_EN_MASK 0x00006000L -#define nbif_gpu_DEVICE_CNTL2_epf__END_END_TLP_PREFIX_BLOCKING_MASK 0x00008000L - -// nbif_gpu_DEVICE_STATUS2_epf -#define nbif_gpu_DEVICE_STATUS2_epf__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_LINK_CAP2_epf -#define nbif_gpu_LINK_CAP2_epf__SUPPORTED_LINK_SPEED_MASK 0x000000feL -#define nbif_gpu_LINK_CAP2_epf__CROSSLINK_SUPPORTED_MASK 0x00000100L -#define nbif_gpu_LINK_CAP2_epf__RESERVED_MASK 0xfffffe00L - -// nbif_gpu_LINK_CNTL2_epf -#define nbif_gpu_LINK_CNTL2_epf__TARGET_LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_CNTL2_epf__ENTER_COMPLIANCE_MASK 0x00000010L -#define nbif_gpu_LINK_CNTL2_epf__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x00000020L -#define nbif_gpu_LINK_CNTL2_epf__SELECTABLE_DEEMPHASIS_MASK 0x00000040L -#define nbif_gpu_LINK_CNTL2_epf__XMIT_MARGIN_MASK 0x00000380L -#define nbif_gpu_LINK_CNTL2_epf__ENTER_MOD_COMPLIANCE_MASK 0x00000400L -#define nbif_gpu_LINK_CNTL2_epf__COMPLIANCE_SOS_MASK 0x00000800L -#define nbif_gpu_LINK_CNTL2_epf__COMPLIANCE_DEEMPHASIS_MASK 0x0000f000L - -// nbif_gpu_LINK_STATUS2_epf -#define nbif_gpu_LINK_STATUS2_epf__CUR_DEEMPHASIS_LEVEL_MASK 0x00000001L -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_COMPLETE_MASK 0x00000002L -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_PHASE1_SUCCESS_MASK 0x00000004L -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_PHASE2_SUCCESS_MASK 0x00000008L -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_PHASE3_SUCCESS_MASK 0x00000010L -#define nbif_gpu_LINK_STATUS2_epf__LINK_EQUALIZATION_REQUEST_MASK 0x00000020L - -// nbif_gpu_SLOT_CAP2_epf -#define nbif_gpu_SLOT_CAP2_epf__RESERVED_MASK 0xffffffffL - -// nbif_gpu_SLOT_CNTL2_epf -#define nbif_gpu_SLOT_CNTL2_epf__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_SLOT_STATUS2_epf -#define nbif_gpu_SLOT_STATUS2_epf__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_MSI_CAP_LIST_epf -#define nbif_gpu_MSI_CAP_LIST_epf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_MSI_CAP_LIST_epf__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_MSI_MSG_CNTL_epf -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_EN_MASK 0x00000001L -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_MULTI_CAP_MASK 0x0000000eL -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_MULTI_EN_MASK 0x00000070L -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_64BIT_MASK 0x00000080L -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_PERVECTOR_MASKING_CAP_MASK 0x00000100L - -// nbif_gpu_MSI_MSG_ADDR_LO_epf -#define nbif_gpu_MSI_MSG_ADDR_LO_epf__MSI_MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_MSI_MSG_ADDR_HI_epf -#define nbif_gpu_MSI_MSG_ADDR_HI_epf__MSI_MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_MSI_MSG_DATA_64_epf -#define nbif_gpu_MSI_MSG_DATA_64_epf__MSI_DATA_64_MASK 0x0000ffffL - -// nbif_gpu_MSI_MSG_DATA_epf -#define nbif_gpu_MSI_MSG_DATA_epf__MSI_DATA_MASK 0x0000ffffL - -// nbif_gpu_MSI_MASK_epf -#define nbif_gpu_MSI_MASK_epf__MSI_MASK_MASK 0xffffffffL - -// nbif_gpu_MSI_PENDING_epf -#define nbif_gpu_MSI_PENDING_epf__MSI_PENDING_MASK 0xffffffffL - -// nbif_gpu_MSI_MASK_64_epf -#define nbif_gpu_MSI_MASK_64_epf__MSI_MASK_64_MASK 0xffffffffL - -// nbif_gpu_MSI_PENDING_64_epf -#define nbif_gpu_MSI_PENDING_64_epf__MSI_PENDING_64_MASK 0xffffffffL - -// nbif_gpu_MSIX_CAP_LIST_epf -#define nbif_gpu_MSIX_CAP_LIST_epf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_MSIX_CAP_LIST_epf__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_MSIX_MSG_CNTL_epf -#define nbif_gpu_MSIX_MSG_CNTL_epf__MSIX_TABLE_SIZE_MASK 0x000007ffL -#define nbif_gpu_MSIX_MSG_CNTL_epf__MSIX_FUNC_MASK_MASK 0x00004000L -#define nbif_gpu_MSIX_MSG_CNTL_epf__MSIX_EN_MASK 0x00008000L - -// nbif_gpu_MSIX_TABLE_epf -#define nbif_gpu_MSIX_TABLE_epf__MSIX_TABLE_BIR_MASK 0x00000007L -#define nbif_gpu_MSIX_TABLE_epf__MSIX_TABLE_OFFSET_MASK 0xfffffff8L - -// nbif_gpu_MSIX_PBA_epf -#define nbif_gpu_MSIX_PBA_epf__MSIX_PBA_BIR_MASK 0x00000007L -#define nbif_gpu_MSIX_PBA_epf__MSIX_PBA_OFFSET_MASK 0xfffffff8L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf__VSEC_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf__VSEC_REV_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf__VSEC_LENGTH_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf__SCRATCH_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf__SCRATCH_MASK 0xffffffffL - -// nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__EXT_VC_COUNT_MASK 0x00000007L -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__REF_CLK_MASK 0x00000300L -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000c00L - -// nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf__VC_ARB_CAP_MASK 0x000000ffL -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf__VC_ARB_TABLE_OFFSET_MASK 0xff000000L - -// nbif_gpu_PCIE_PORT_VC_CNTL_epf -#define nbif_gpu_PCIE_PORT_VC_CNTL_epf__LOAD_VC_ARB_TABLE_MASK 0x00000001L -#define nbif_gpu_PCIE_PORT_VC_CNTL_epf__VC_ARB_SELECT_MASK 0x0000000eL - -// nbif_gpu_PCIE_PORT_VC_STATUS_epf -#define nbif_gpu_PCIE_PORT_VC_STATUS_epf__VC_ARB_TABLE_STATUS_MASK 0x00000001L - -// nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__PORT_ARB_CAP_MASK 0x000000ffL -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__REJECT_SNOOP_TRANS_MASK 0x00008000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__MAX_TIME_SLOTS_MASK 0x003f0000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__PORT_ARB_TABLE_OFFSET_MASK 0xff000000L - -// nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__TC_VC_MAP_TC0_MASK 0x00000001L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__TC_VC_MAP_TC1_7_MASK 0x000000feL -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__LOAD_PORT_ARB_TABLE_MASK 0x00010000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__PORT_ARB_SELECT_MASK 0x000e0000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__VC_ID_MASK 0x07000000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__VC_ENABLE_MASK 0x80000000L - -// nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf__PORT_ARB_TABLE_STATUS_MASK 0x00000001L -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf__VC_NEGOTIATION_PENDING_MASK 0x00000002L - -// nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__PORT_ARB_CAP_MASK 0x000000ffL -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__REJECT_SNOOP_TRANS_MASK 0x00008000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__MAX_TIME_SLOTS_MASK 0x003f0000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__PORT_ARB_TABLE_OFFSET_MASK 0xff000000L - -// nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__TC_VC_MAP_TC0_MASK 0x00000001L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__TC_VC_MAP_TC1_7_MASK 0x000000feL -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__LOAD_PORT_ARB_TABLE_MASK 0x00010000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__PORT_ARB_SELECT_MASK 0x000e0000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__VC_ID_MASK 0x07000000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__VC_ENABLE_MASK 0x80000000L - -// nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf__PORT_ARB_TABLE_STATUS_MASK 0x00000001L -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf__VC_NEGOTIATION_PENDING_MASK 0x00000002L - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf__SERIAL_NUMBER_LO_MASK 0xffffffffL - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf__SERIAL_NUMBER_HI_MASK 0xffffffffL - -// nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__DLP_ERR_STATUS_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__SURPDN_ERR_STATUS_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__PSN_ERR_STATUS_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__FC_ERR_STATUS_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__CPL_TIMEOUT_STATUS_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__CPL_ABORT_ERR_STATUS_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__UNEXP_CPL_STATUS_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__RCV_OVFL_STATUS_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__MAL_TLP_STATUS_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__ECRC_ERR_STATUS_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__ACS_VIOLATION_STATUS_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__UNCORR_INT_ERR_STATUS_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L - -// nbif_gpu_PCIE_UNCORR_ERR_MASK_epf -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__DLP_ERR_MASK_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__SURPDN_ERR_MASK_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__PSN_ERR_MASK_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__FC_ERR_MASK_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__CPL_TIMEOUT_MASK_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__CPL_ABORT_ERR_MASK_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__UNEXP_CPL_MASK_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__RCV_OVFL_MASK_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__MAL_TLP_MASK_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__ECRC_ERR_MASK_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__ACS_VIOLATION_MASK_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__UNCORR_INT_ERR_MASK_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__MC_BLOCKED_TLP_MASK_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L - -// nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__DLP_ERR_SEVERITY_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__SURPDN_ERR_SEVERITY_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__PSN_ERR_SEVERITY_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__FC_ERR_SEVERITY_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__UNEXP_CPL_SEVERITY_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__RCV_OVFL_SEVERITY_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__MAL_TLP_SEVERITY_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__ECRC_ERR_SEVERITY_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__ACS_VIOLATION_SEVERITY_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L - -// nbif_gpu_PCIE_CORR_ERR_STATUS_epf -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__RCV_ERR_STATUS_MASK 0x00000001L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__BAD_TLP_STATUS_MASK 0x00000040L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__BAD_DLLP_STATUS_MASK 0x00000080L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__CORR_INT_ERR_STATUS_MASK 0x00004000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__HDR_LOG_OVFL_STATUS_MASK 0x00008000L - -// nbif_gpu_PCIE_CORR_ERR_MASK_epf -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__RCV_ERR_MASK_MASK 0x00000001L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__BAD_TLP_MASK_MASK 0x00000040L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__BAD_DLLP_MASK_MASK 0x00000080L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__CORR_INT_ERR_MASK_MASK 0x00004000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__HDR_LOG_OVFL_MASK_MASK 0x00008000L - -// nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__FIRST_ERR_PTR_MASK 0x0000001fL -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_GEN_CAP_MASK 0x00000020L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_GEN_EN_MASK 0x00000040L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_CHECK_CAP_MASK 0x00000080L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_CHECK_EN_MASK 0x00000100L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__MULTI_HDR_RECD_CAP_MASK 0x00000200L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__MULTI_HDR_RECD_EN_MASK 0x00000400L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L - -// nbif_gpu_PCIE_HDR_LOG0_epf -#define nbif_gpu_PCIE_HDR_LOG0_epf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG1_epf -#define nbif_gpu_PCIE_HDR_LOG1_epf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG2_epf -#define nbif_gpu_PCIE_HDR_LOG2_epf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG3_epf -#define nbif_gpu_PCIE_HDR_LOG3_epf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_ROOT_ERR_CMD_epf -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epf__CORR_ERR_REP_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epf__NONFATAL_ERR_REP_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epf__FATAL_ERR_REP_EN_MASK 0x00000004L - -// nbif_gpu_PCIE_ROOT_ERR_STATUS_epf -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__ERR_CORR_RCVD_MASK 0x00000001L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__MULT_ERR_CORR_RCVD_MASK 0x00000002L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000L - -// nbif_gpu_PCIE_ERR_SRC_ID_epf -#define nbif_gpu_PCIE_ERR_SRC_ID_epf__ERR_CORR_SRC_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ERR_SRC_ID_epf__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000L - -// nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_BAR1_CAP_epf -#define nbif_gpu_PCIE_BAR1_CAP_epf__BAR_SIZE_SUPPORTED_MASK 0x00fffff0L - -// nbif_gpu_PCIE_BAR1_CNTL_epf -#define nbif_gpu_PCIE_BAR1_CNTL_epf__BAR_INDEX_MASK 0x00000007L -#define nbif_gpu_PCIE_BAR1_CNTL_epf__BAR_TOTAL_NUM_MASK 0x000000e0L -#define nbif_gpu_PCIE_BAR1_CNTL_epf__BAR_SIZE_MASK 0x00001f00L - -// nbif_gpu_PCIE_BAR2_CAP_epf -#define nbif_gpu_PCIE_BAR2_CAP_epf__BAR_SIZE_SUPPORTED_MASK 0x00fffff0L - -// nbif_gpu_PCIE_BAR2_CNTL_epf -#define nbif_gpu_PCIE_BAR2_CNTL_epf__BAR_INDEX_MASK 0x00000007L -#define nbif_gpu_PCIE_BAR2_CNTL_epf__BAR_TOTAL_NUM_MASK 0x000000e0L -#define nbif_gpu_PCIE_BAR2_CNTL_epf__BAR_SIZE_MASK 0x00001f00L - -// nbif_gpu_PCIE_BAR3_CAP_epf -#define nbif_gpu_PCIE_BAR3_CAP_epf__BAR_SIZE_SUPPORTED_MASK 0x00fffff0L - -// nbif_gpu_PCIE_BAR3_CNTL_epf -#define nbif_gpu_PCIE_BAR3_CNTL_epf__BAR_INDEX_MASK 0x00000007L -#define nbif_gpu_PCIE_BAR3_CNTL_epf__BAR_TOTAL_NUM_MASK 0x000000e0L -#define nbif_gpu_PCIE_BAR3_CNTL_epf__BAR_SIZE_MASK 0x00001f00L - -// nbif_gpu_PCIE_BAR4_CAP_epf -#define nbif_gpu_PCIE_BAR4_CAP_epf__BAR_SIZE_SUPPORTED_MASK 0x00fffff0L - -// nbif_gpu_PCIE_BAR4_CNTL_epf -#define nbif_gpu_PCIE_BAR4_CNTL_epf__BAR_INDEX_MASK 0x00000007L -#define nbif_gpu_PCIE_BAR4_CNTL_epf__BAR_TOTAL_NUM_MASK 0x000000e0L -#define nbif_gpu_PCIE_BAR4_CNTL_epf__BAR_SIZE_MASK 0x00001f00L - -// nbif_gpu_PCIE_BAR5_CAP_epf -#define nbif_gpu_PCIE_BAR5_CAP_epf__BAR_SIZE_SUPPORTED_MASK 0x00fffff0L - -// nbif_gpu_PCIE_BAR5_CNTL_epf -#define nbif_gpu_PCIE_BAR5_CNTL_epf__BAR_INDEX_MASK 0x00000007L -#define nbif_gpu_PCIE_BAR5_CNTL_epf__BAR_TOTAL_NUM_MASK 0x000000e0L -#define nbif_gpu_PCIE_BAR5_CNTL_epf__BAR_SIZE_MASK 0x00001f00L - -// nbif_gpu_PCIE_BAR6_CAP_epf -#define nbif_gpu_PCIE_BAR6_CAP_epf__BAR_SIZE_SUPPORTED_MASK 0x00fffff0L - -// nbif_gpu_PCIE_BAR6_CNTL_epf -#define nbif_gpu_PCIE_BAR6_CNTL_epf__BAR_INDEX_MASK 0x00000007L -#define nbif_gpu_PCIE_BAR6_CNTL_epf__BAR_TOTAL_NUM_MASK 0x000000e0L -#define nbif_gpu_PCIE_BAR6_CNTL_epf__BAR_SIZE_MASK 0x00001f00L - -// nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf__DATA_SELECT_MASK 0x000000ffL - -// nbif_gpu_PCIE_PWR_BUDGET_DATA_epf -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__BASE_POWER_MASK 0x000000ffL -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__DATA_SCALE_MASK 0x00000300L -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__PM_SUB_STATE_MASK 0x00001c00L -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__PM_STATE_MASK 0x00006000L -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__TYPE_MASK 0x00038000L -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__POWER_RAIL_MASK 0x001c0000L - -// nbif_gpu_PCIE_PWR_BUDGET_CAP_epf -#define nbif_gpu_PCIE_PWR_BUDGET_CAP_epf__SYSTEM_ALLOCATED_MASK 0x00000001L - -// nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_DPA_CAP_epf -#define nbif_gpu_PCIE_DPA_CAP_epf__SUBSTATE_MAX_MASK 0x0000001fL -#define nbif_gpu_PCIE_DPA_CAP_epf__TRANS_LAT_UNIT_MASK 0x00000300L -#define nbif_gpu_PCIE_DPA_CAP_epf__PWR_ALLOC_SCALE_MASK 0x00003000L -#define nbif_gpu_PCIE_DPA_CAP_epf__TRANS_LAT_VAL_0_MASK 0x00ff0000L -#define nbif_gpu_PCIE_DPA_CAP_epf__TRANS_LAT_VAL_1_MASK 0xff000000L - -// nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf -#define nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf__TRANS_LAT_INDICATOR_BITS_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_STATUS_epf -#define nbif_gpu_PCIE_DPA_STATUS_epf__SUBSTATE_STATUS_MASK 0x0000001fL -#define nbif_gpu_PCIE_DPA_STATUS_epf__SUBSTATE_CNTL_ENABLED_MASK 0x00000100L - -// nbif_gpu_PCIE_DPA_CNTL_epf -#define nbif_gpu_PCIE_DPA_CNTL_epf__SUBSTATE_CNTL_MASK 0x0000001fL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_LINK_CNTL3_epf -#define nbif_gpu_PCIE_LINK_CNTL3_epf__PERFORM_EQUALIZATION_MASK 0x00000001L -#define nbif_gpu_PCIE_LINK_CNTL3_epf__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_LINK_CNTL3_epf__RESERVED_MASK 0xfffffffcL - -// nbif_gpu_PCIE_LANE_ERROR_STATUS_epf -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_epf__LANE_ERROR_STATUS_BITS_MASK 0x0000ffffL -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_epf__RESERVED_MASK 0xffff0000L - -// nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_ACS_CAP_epf -#define nbif_gpu_PCIE_ACS_CAP_epf__SOURCE_VALIDATION_MASK 0x00000001L -#define nbif_gpu_PCIE_ACS_CAP_epf__TRANSLATION_BLOCKING_MASK 0x00000002L -#define nbif_gpu_PCIE_ACS_CAP_epf__P2P_REQUEST_REDIRECT_MASK 0x00000004L -#define nbif_gpu_PCIE_ACS_CAP_epf__P2P_COMPLETION_REDIRECT_MASK 0x00000008L -#define nbif_gpu_PCIE_ACS_CAP_epf__UPSTREAM_FORWARDING_MASK 0x00000010L -#define nbif_gpu_PCIE_ACS_CAP_epf__P2P_EGRESS_CONTROL_MASK 0x00000020L -#define nbif_gpu_PCIE_ACS_CAP_epf__DIRECT_TRANSLATED_P2P_MASK 0x00000040L -#define nbif_gpu_PCIE_ACS_CAP_epf__EGRESS_CONTROL_VECTOR_SIZE_MASK 0x0000ff00L - -// nbif_gpu_PCIE_ACS_CNTL_epf -#define nbif_gpu_PCIE_ACS_CNTL_epf__SOURCE_VALIDATION_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_ACS_CNTL_epf__TRANSLATION_BLOCKING_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_ACS_CNTL_epf__P2P_REQUEST_REDIRECT_EN_MASK 0x00000004L -#define nbif_gpu_PCIE_ACS_CNTL_epf__P2P_COMPLETION_REDIRECT_EN_MASK 0x00000008L -#define nbif_gpu_PCIE_ACS_CNTL_epf__UPSTREAM_FORWARDING_EN_MASK 0x00000010L -#define nbif_gpu_PCIE_ACS_CNTL_epf__P2P_EGRESS_CONTROL_EN_MASK 0x00000020L -#define nbif_gpu_PCIE_ACS_CNTL_epf__DIRECT_TRANSLATED_P2P_EN_MASK 0x00000040L - -// nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_ATS_CAP_epf -#define nbif_gpu_PCIE_ATS_CAP_epf__INVALIDATE_Q_DEPTH_MASK 0x0000001fL -#define nbif_gpu_PCIE_ATS_CAP_epf__PAGE_ALIGNED_REQUEST_MASK 0x00000020L -#define nbif_gpu_PCIE_ATS_CAP_epf__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x00000040L - -// nbif_gpu_PCIE_ATS_CNTL_epf -#define nbif_gpu_PCIE_ATS_CNTL_epf__STU_MASK 0x0000001fL -#define nbif_gpu_PCIE_ATS_CNTL_epf__ATC_ENABLE_MASK 0x00008000L - -// nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_PAGE_REQ_CNTL_epf -#define nbif_gpu_PCIE_PAGE_REQ_CNTL_epf__PRI_ENABLE_MASK 0x00000001L -#define nbif_gpu_PCIE_PAGE_REQ_CNTL_epf__PRI_RESET_MASK 0x00000002L - -// nbif_gpu_PCIE_PAGE_REQ_STATUS_epf -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__RESPONSE_FAILURE_MASK 0x00000001L -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x00000002L -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__STOPPED_MASK 0x00000100L -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__PRG_RESPONSE_PASID_REQUIRED_MASK 0x00008000L - -// nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf -#define nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffffL - -// nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf -#define nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffffL - -// nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_PASID_CAP_epf -#define nbif_gpu_PCIE_PASID_CAP_epf__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x00000002L -#define nbif_gpu_PCIE_PASID_CAP_epf__PASID_PRIV_MODE_SUPPORTED_MASK 0x00000004L -#define nbif_gpu_PCIE_PASID_CAP_epf__MAX_PASID_WIDTH_MASK 0x00001f00L - -// nbif_gpu_PCIE_PASID_CNTL_epf -#define nbif_gpu_PCIE_PASID_CNTL_epf__PASID_ENABLE_MASK 0x00000001L -#define nbif_gpu_PCIE_PASID_CNTL_epf__PASID_EXE_PERMISSION_ENABLE_MASK 0x00000002L -#define nbif_gpu_PCIE_PASID_CNTL_epf__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00000004L - -// nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_TPH_REQR_CAP_epf -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_ST_TABLE_SIZE_MASK 0x07ff0000L - -// nbif_gpu_PCIE_TPH_REQR_CNTL_epf -#define nbif_gpu_PCIE_TPH_REQR_CNTL_epf__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L -#define nbif_gpu_PCIE_TPH_REQR_CNTL_epf__TPH_REQR_EN_MASK 0x00000300L - -// nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_MC_CAP_epf -#define nbif_gpu_PCIE_MC_CAP_epf__MC_MAX_GROUP_MASK 0x0000003fL -#define nbif_gpu_PCIE_MC_CAP_epf__MC_WIN_SIZE_REQ_MASK 0x00003f00L -#define nbif_gpu_PCIE_MC_CAP_epf__MC_ECRC_REGEN_SUPP_MASK 0x00008000L - -// nbif_gpu_PCIE_MC_CNTL_epf -#define nbif_gpu_PCIE_MC_CNTL_epf__MC_NUM_GROUP_MASK 0x0000003fL -#define nbif_gpu_PCIE_MC_CNTL_epf__MC_ENABLE_MASK 0x00008000L - -// nbif_gpu_PCIE_MC_ADDR0_epf -#define nbif_gpu_PCIE_MC_ADDR0_epf__MC_INDEX_POS_MASK 0x0000003fL -#define nbif_gpu_PCIE_MC_ADDR0_epf__MC_BASE_ADDR_0_MASK 0xfffff000L - -// nbif_gpu_PCIE_MC_ADDR1_epf -#define nbif_gpu_PCIE_MC_ADDR1_epf__MC_BASE_ADDR_1_MASK 0xffffffffL - -// nbif_gpu_PCIE_MC_RCV0_epf -#define nbif_gpu_PCIE_MC_RCV0_epf__MC_RECEIVE_0_MASK 0xffffffffL - -// nbif_gpu_PCIE_MC_RCV1_epf -#define nbif_gpu_PCIE_MC_RCV1_epf__MC_RECEIVE_1_MASK 0xffffffffL - -// nbif_gpu_PCIE_MC_BLOCK_ALL0_epf -#define nbif_gpu_PCIE_MC_BLOCK_ALL0_epf__MC_BLOCK_ALL_0_MASK 0xffffffffL - -// nbif_gpu_PCIE_MC_BLOCK_ALL1_epf -#define nbif_gpu_PCIE_MC_BLOCK_ALL1_epf__MC_BLOCK_ALL_1_MASK 0xffffffffL - -// nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf -#define nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffffL - -// nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf -#define nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffffL - -// nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_LTR_CAP_epf -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003ffL -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001c00L -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03ff0000L -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000L - -// nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_ARI_CAP_epf -#define nbif_gpu_PCIE_ARI_CAP_epf__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x00000001L -#define nbif_gpu_PCIE_ARI_CAP_epf__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x00000002L -#define nbif_gpu_PCIE_ARI_CAP_epf__ARI_NEXT_FUNC_NUM_MASK 0x0000ff00L - -// nbif_gpu_PCIE_ARI_CNTL_epf -#define nbif_gpu_PCIE_ARI_CNTL_epf__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_ARI_CNTL_epf__ARI_ACS_FUNC_GROUPS_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_ARI_CNTL_epf__ARI_FUNCTION_GROUP_MASK 0x00000070L - -// nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_SRIOV_CAP_epf -#define nbif_gpu_PCIE_SRIOV_CAP_epf__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L -#define nbif_gpu_PCIE_SRIOV_CAP_epf__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L -#define nbif_gpu_PCIE_SRIOV_CAP_epf__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xffe00000L - -// nbif_gpu_PCIE_SRIOV_CONTROL_epf -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_ENABLE_MASK 0x00000001L -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_MIGRATION_ENABLE_MASK 0x00000002L -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x00000004L -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_MSE_MASK 0x00000008L -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_ARI_CAP_HIERARCHY_MASK 0x00000010L - -// nbif_gpu_PCIE_SRIOV_STATUS_epf -#define nbif_gpu_PCIE_SRIOV_STATUS_epf__SRIOV_VF_MIGRATION_STATUS_MASK 0x00000001L - -// nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf -#define nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf__SRIOV_INITIAL_VFS_MASK 0x0000ffffL - -// nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf -#define nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf__SRIOV_TOTAL_VFS_MASK 0x0000ffffL - -// nbif_gpu_PCIE_SRIOV_NUM_VFS_epf -#define nbif_gpu_PCIE_SRIOV_NUM_VFS_epf__SRIOV_NUM_VFS_MASK 0x0000ffffL - -// nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf -#define nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf__SRIOV_FUNC_DEP_LINK_MASK 0x000000ffL - -// nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf -#define nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf__SRIOV_FIRST_VF_OFFSET_MASK 0x0000ffffL - -// nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf -#define nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf__SRIOV_VF_STRIDE_MASK 0x0000ffffL - -// nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf -#define nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf__SRIOV_VF_DEVICE_ID_MASK 0x0000ffffL - -// nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf -#define nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf -#define nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf__VF_BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf__VF_BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf__VF_BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf__VF_BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf__VF_BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf__VF_BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf -#define nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf__SRIOV_VF_MIGRATION_STATE_BIF_MASK \ - 0x00000007L -#define nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK \ - 0xfffffff8L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf__VSEC_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf__VSEC_REV_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf__VSEC_LENGTH_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf__VF_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf__VF_NUM_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_CMD_COMPLETE_INTR_EN_MASK \ - 0x00000001L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK \ - 0x00000002L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_HANG_NEED_FLR_INTR_EN_MASK \ - 0x00000004L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK \ - 0x00000008L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_CMD_COMPLETE_INTR_EN_MASK \ - 0x00000100L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK \ - 0x00000200L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_HANG_NEED_FLR_INTR_EN_MASK \ - 0x00000400L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK \ - 0x00000800L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_CMD_COMPLETE_INTR_EN_MASK \ - 0x00010000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK \ - 0x00020000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_HANG_NEED_FLR_INTR_EN_MASK \ - 0x00040000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK \ - 0x00080000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK \ - 0x01000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK \ - 0x02000000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_CMD_COMPLETE_INTR_STATUS_MASK \ - 0x00000001L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK \ - 0x00000002L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_HANG_NEED_FLR_INTR_STATUS_MASK \ - 0x00000004L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK \ - 0x00000008L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_CMD_COMPLETE_INTR_STATUS_MASK \ - 0x00000100L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK \ - 0x00000200L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_HANG_NEED_FLR_INTR_STATUS_MASK \ - 0x00000400L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK \ - 0x00000800L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_CMD_COMPLETE_INTR_STATUS_MASK \ - 0x00010000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK \ - 0x00020000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_HANG_NEED_FLR_INTR_STATUS_MASK \ - 0x00040000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK \ - 0x00080000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK \ - 0x01000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK \ - 0x02000000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf__SOFT_PF_FLR_MASK 0x00000001L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__VF_INDEX_MASK 0x000000ffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__TRN_MSG_DATA_MASK 0x00000f00L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__TRN_MSG_VALID_MASK 0x00008000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__RCV_MSG_DATA_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__RCV_MSG_ACK_MASK 0x01000000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF0_TRN_ACK_MASK 0x00000001L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF0_RCV_VALID_MASK 0x00000002L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF1_TRN_ACK_MASK 0x00000004L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF1_RCV_VALID_MASK 0x00000008L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF2_TRN_ACK_MASK 0x00000010L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF2_RCV_VALID_MASK 0x00000020L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF3_TRN_ACK_MASK 0x00000040L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF3_RCV_VALID_MASK 0x00000080L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF4_TRN_ACK_MASK 0x00000100L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF4_RCV_VALID_MASK 0x00000200L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF5_TRN_ACK_MASK 0x00000400L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF5_RCV_VALID_MASK 0x00000800L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF6_TRN_ACK_MASK 0x00001000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF6_RCV_VALID_MASK 0x00002000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF7_TRN_ACK_MASK 0x00004000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF7_RCV_VALID_MASK 0x00008000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF8_TRN_ACK_MASK 0x00010000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF8_RCV_VALID_MASK 0x00020000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF9_TRN_ACK_MASK 0x00040000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF9_RCV_VALID_MASK 0x00080000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF10_TRN_ACK_MASK 0x00100000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF10_RCV_VALID_MASK 0x00200000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF11_TRN_ACK_MASK 0x00400000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF11_RCV_VALID_MASK 0x00800000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF12_TRN_ACK_MASK 0x01000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF12_RCV_VALID_MASK 0x02000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF13_TRN_ACK_MASK 0x04000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF13_RCV_VALID_MASK 0x08000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF14_TRN_ACK_MASK 0x10000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF14_RCV_VALID_MASK 0x20000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF15_TRN_ACK_MASK 0x40000000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF15_RCV_VALID_MASK 0x80000000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf__PF_TRN_ACK_MASK 0x00000001L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf__PF_RCV_VALID_MASK 0x00000002L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf__CONTEXT_SIZE_MASK 0x0000007fL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf__LOC_MASK 0x00000080L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf__CONTEXT_OFFSET_MASK 0xfffffc00L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf__TOTAL_FB_AVAILABLE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf__TOTAL_FB_CONSUMED_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf__UVDSCH_OFFSET_MASK 0x000000ffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf__VCESCH_OFFSET_MASK 0x0000ff00L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf__GFXSCH_OFFSET_MASK 0x00ff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf__VF0_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf__VF0_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf__VF1_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf__VF1_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf__VF2_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf__VF2_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf__VF3_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf__VF3_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf__VF4_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf__VF4_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf__VF5_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf__VF5_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf__VF6_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf__VF6_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf__VF7_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf__VF7_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf__VF8_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf__VF8_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf__VF9_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf__VF9_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf__VF10_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf__VF10_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf__VF11_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf__VF11_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf__VF12_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf__VF12_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf__VF13_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf__VF13_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf__VF14_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf__VF14_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf__VF15_FB_SIZE_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf__VF15_FB_OFFSET_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf__DW0_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf__DW1_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf__DW2_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf__DW3_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf__DW4_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf__DW5_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf__DW6_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf__DW7_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf__DW0_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf__DW1_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf__DW2_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf__DW3_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf__DW4_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf__DW5_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf__DW6_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf__DW7_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf__DW0_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf__DW1_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf__DW2_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf__DW3_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf__DW4_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf__DW5_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf__DW6_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf__DW7_MASK 0xffffffffL - -// nbif_gpu_VENDOR_ID_epvf -#define nbif_gpu_VENDOR_ID_epvf__VENDOR_ID_MASK 0x0000ffffL - -// nbif_gpu_DEVICE_ID_epvf -#define nbif_gpu_DEVICE_ID_epvf__DEVICE_ID_MASK 0x0000ffffL - -// nbif_gpu_COMMAND_epvf -#define nbif_gpu_COMMAND_epvf__IO_ACCESS_EN_MASK 0x00000001L -#define nbif_gpu_COMMAND_epvf__MEM_ACCESS_EN_MASK 0x00000002L -#define nbif_gpu_COMMAND_epvf__BUS_MASTER_EN_MASK 0x00000004L -#define nbif_gpu_COMMAND_epvf__SPECIAL_CYCLE_EN_MASK 0x00000008L -#define nbif_gpu_COMMAND_epvf__MEM_WRITE_INVALIDATE_EN_MASK 0x00000010L -#define nbif_gpu_COMMAND_epvf__PAL_SNOOP_EN_MASK 0x00000020L -#define nbif_gpu_COMMAND_epvf__PARITY_ERROR_RESPONSE_MASK 0x00000040L -#define nbif_gpu_COMMAND_epvf__AD_STEPPING_MASK 0x00000080L -#define nbif_gpu_COMMAND_epvf__SERR_EN_MASK 0x00000100L -#define nbif_gpu_COMMAND_epvf__FAST_B2B_EN_MASK 0x00000200L -#define nbif_gpu_COMMAND_epvf__INT_DIS_MASK 0x00000400L - -// nbif_gpu_STATUS_epvf -#define nbif_gpu_STATUS_epvf__INT_STATUS_MASK 0x00000008L -#define nbif_gpu_STATUS_epvf__CAP_LIST_MASK 0x00000010L -#define nbif_gpu_STATUS_epvf__PCI_66_EN_MASK 0x00000020L -#define nbif_gpu_STATUS_epvf__FAST_BACK_CAPABLE_MASK 0x00000080L -#define nbif_gpu_STATUS_epvf__MASTER_DATA_PARITY_ERROR_MASK 0x00000100L -#define nbif_gpu_STATUS_epvf__DEVSEL_TIMING_MASK 0x00000600L -#define nbif_gpu_STATUS_epvf__SIGNAL_TARGET_ABORT_MASK 0x00000800L -#define nbif_gpu_STATUS_epvf__RECEIVED_TARGET_ABORT_MASK 0x00001000L -#define nbif_gpu_STATUS_epvf__RECEIVED_MASTER_ABORT_MASK 0x00002000L -#define nbif_gpu_STATUS_epvf__SIGNALED_SYSTEM_ERROR_MASK 0x00004000L -#define nbif_gpu_STATUS_epvf__PARITY_ERROR_DETECTED_MASK 0x00008000L - -// nbif_gpu_REVISION_ID_epvf -#define nbif_gpu_REVISION_ID_epvf__MINOR_REV_ID_MASK 0x0000000fL -#define nbif_gpu_REVISION_ID_epvf__MAJOR_REV_ID_MASK 0x000000f0L - -// nbif_gpu_PROG_INTERFACE_epvf -#define nbif_gpu_PROG_INTERFACE_epvf__PROG_INTERFACE_MASK 0x000000ffL - -// nbif_gpu_SUB_CLASS_epvf -#define nbif_gpu_SUB_CLASS_epvf__SUB_CLASS_MASK 0x000000ffL - -// nbif_gpu_BASE_CLASS_epvf -#define nbif_gpu_BASE_CLASS_epvf__BASE_CLASS_MASK 0x000000ffL - -// nbif_gpu_CACHE_LINE_epvf -#define nbif_gpu_CACHE_LINE_epvf__CACHE_LINE_SIZE_MASK 0x000000ffL - -// nbif_gpu_LATENCY_epvf -#define nbif_gpu_LATENCY_epvf__LATENCY_TIMER_MASK 0x000000ffL - -// nbif_gpu_HEADER_epvf -#define nbif_gpu_HEADER_epvf__HEADER_TYPE_MASK 0x0000007fL -#define nbif_gpu_HEADER_epvf__DEVICE_TYPE_MASK 0x00000080L - -// nbif_gpu_BIST_epvf -#define nbif_gpu_BIST_epvf__BIST_COMP_MASK 0x0000000fL -#define nbif_gpu_BIST_epvf__BIST_STRT_MASK 0x00000040L -#define nbif_gpu_BIST_epvf__BIST_CAP_MASK 0x00000080L - -// nbif_gpu_BASE_ADDR_1_epvf -#define nbif_gpu_BASE_ADDR_1_epvf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_2_epvf -#define nbif_gpu_BASE_ADDR_2_epvf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_3_epvf -#define nbif_gpu_BASE_ADDR_3_epvf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_4_epvf -#define nbif_gpu_BASE_ADDR_4_epvf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_5_epvf -#define nbif_gpu_BASE_ADDR_5_epvf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_BASE_ADDR_6_epvf -#define nbif_gpu_BASE_ADDR_6_epvf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_ROM_BASE_ADDR_epvf -#define nbif_gpu_ROM_BASE_ADDR_epvf__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_CAP_PTR_epvf -#define nbif_gpu_CAP_PTR_epvf__CAP_PTR_MASK 0x000000ffL - -// nbif_gpu_INTERRUPT_LINE_epvf -#define nbif_gpu_INTERRUPT_LINE_epvf__INTERRUPT_LINE_MASK 0x000000ffL - -// nbif_gpu_INTERRUPT_PIN_epvf -#define nbif_gpu_INTERRUPT_PIN_epvf__INTERRUPT_PIN_MASK 0x000000ffL - -// nbif_gpu_ADAPTER_ID_epvf -#define nbif_gpu_ADAPTER_ID_epvf__SUBSYSTEM_VENDOR_ID_MASK 0x0000ffffL -#define nbif_gpu_ADAPTER_ID_epvf__SUBSYSTEM_ID_MASK 0xffff0000L - -// nbif_gpu_PCIE_CAP_LIST_epvf -#define nbif_gpu_PCIE_CAP_LIST_epvf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_PCIE_CAP_LIST_epvf__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_PCIE_CAP_epvf -#define nbif_gpu_PCIE_CAP_epvf__VERSION_MASK 0x0000000fL -#define nbif_gpu_PCIE_CAP_epvf__DEVICE_TYPE_MASK 0x000000f0L -#define nbif_gpu_PCIE_CAP_epvf__SLOT_IMPLEMENTED_MASK 0x00000100L -#define nbif_gpu_PCIE_CAP_epvf__INT_MESSAGE_NUM_MASK 0x00003e00L - -// nbif_gpu_DEVICE_CAP_epvf -#define nbif_gpu_DEVICE_CAP_epvf__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L -#define nbif_gpu_DEVICE_CAP_epvf__PHANTOM_FUNC_MASK 0x00000018L -#define nbif_gpu_DEVICE_CAP_epvf__EXTENDED_TAG_MASK 0x00000020L -#define nbif_gpu_DEVICE_CAP_epvf__L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0L -#define nbif_gpu_DEVICE_CAP_epvf__L1_ACCEPTABLE_LATENCY_MASK 0x00000e00L -#define nbif_gpu_DEVICE_CAP_epvf__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L -#define nbif_gpu_DEVICE_CAP_epvf__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03fc0000L -#define nbif_gpu_DEVICE_CAP_epvf__CAPTURED_SLOT_POWER_SCALE_MASK 0x0c000000L -#define nbif_gpu_DEVICE_CAP_epvf__FLR_CAPABLE_MASK 0x10000000L - -// nbif_gpu_DEVICE_CNTL_epvf -#define nbif_gpu_DEVICE_CNTL_epvf__CORR_ERR_EN_MASK 0x00000001L -#define nbif_gpu_DEVICE_CNTL_epvf__NON_FATAL_ERR_EN_MASK 0x00000002L -#define nbif_gpu_DEVICE_CNTL_epvf__FATAL_ERR_EN_MASK 0x00000004L -#define nbif_gpu_DEVICE_CNTL_epvf__USR_REPORT_EN_MASK 0x00000008L -#define nbif_gpu_DEVICE_CNTL_epvf__RELAXED_ORD_EN_MASK 0x00000010L -#define nbif_gpu_DEVICE_CNTL_epvf__MAX_PAYLOAD_SIZE_MASK 0x000000e0L -#define nbif_gpu_DEVICE_CNTL_epvf__EXTENDED_TAG_EN_MASK 0x00000100L -#define nbif_gpu_DEVICE_CNTL_epvf__PHANTOM_FUNC_EN_MASK 0x00000200L -#define nbif_gpu_DEVICE_CNTL_epvf__AUX_POWER_PM_EN_MASK 0x00000400L -#define nbif_gpu_DEVICE_CNTL_epvf__NO_SNOOP_EN_MASK 0x00000800L -#define nbif_gpu_DEVICE_CNTL_epvf__MAX_READ_REQUEST_SIZE_MASK 0x00007000L -#define nbif_gpu_DEVICE_CNTL_epvf__INITIATE_FLR_MASK 0x00008000L - -// nbif_gpu_DEVICE_STATUS_epvf -#define nbif_gpu_DEVICE_STATUS_epvf__CORR_ERR_MASK 0x00000001L -#define nbif_gpu_DEVICE_STATUS_epvf__NON_FATAL_ERR_MASK 0x00000002L -#define nbif_gpu_DEVICE_STATUS_epvf__FATAL_ERR_MASK 0x00000004L -#define nbif_gpu_DEVICE_STATUS_epvf__USR_DETECTED_MASK 0x00000008L -#define nbif_gpu_DEVICE_STATUS_epvf__AUX_PWR_MASK 0x00000010L -#define nbif_gpu_DEVICE_STATUS_epvf__TRANSACTIONS_PEND_MASK 0x00000020L - -// nbif_gpu_LINK_CAP_epvf -#define nbif_gpu_LINK_CAP_epvf__LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_CAP_epvf__LINK_WIDTH_MASK 0x000003f0L -#define nbif_gpu_LINK_CAP_epvf__PM_SUPPORT_MASK 0x00000c00L -#define nbif_gpu_LINK_CAP_epvf__L0S_EXIT_LATENCY_MASK 0x00007000L -#define nbif_gpu_LINK_CAP_epvf__L1_EXIT_LATENCY_MASK 0x00038000L -#define nbif_gpu_LINK_CAP_epvf__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L -#define nbif_gpu_LINK_CAP_epvf__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L -#define nbif_gpu_LINK_CAP_epvf__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L -#define nbif_gpu_LINK_CAP_epvf__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L -#define nbif_gpu_LINK_CAP_epvf__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L -#define nbif_gpu_LINK_CAP_epvf__PORT_NUMBER_MASK 0xff000000L - -// nbif_gpu_LINK_CNTL_epvf -#define nbif_gpu_LINK_CNTL_epvf__PM_CONTROL_MASK 0x00000003L -#define nbif_gpu_LINK_CNTL_epvf__READ_CPL_BOUNDARY_MASK 0x00000008L -#define nbif_gpu_LINK_CNTL_epvf__LINK_DIS_MASK 0x00000010L -#define nbif_gpu_LINK_CNTL_epvf__RETRAIN_LINK_MASK 0x00000020L -#define nbif_gpu_LINK_CNTL_epvf__COMMON_CLOCK_CFG_MASK 0x00000040L -#define nbif_gpu_LINK_CNTL_epvf__EXTENDED_SYNC_MASK 0x00000080L -#define nbif_gpu_LINK_CNTL_epvf__CLOCK_POWER_MANAGEMENT_EN_MASK 0x00000100L -#define nbif_gpu_LINK_CNTL_epvf__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x00000200L -#define nbif_gpu_LINK_CNTL_epvf__LINK_BW_MANAGEMENT_INT_EN_MASK 0x00000400L -#define nbif_gpu_LINK_CNTL_epvf__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x00000800L - -// nbif_gpu_LINK_STATUS_epvf -#define nbif_gpu_LINK_STATUS_epvf__CURRENT_LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_STATUS_epvf__NEGOTIATED_LINK_WIDTH_MASK 0x000003f0L -#define nbif_gpu_LINK_STATUS_epvf__LINK_TRAINING_MASK 0x00000800L -#define nbif_gpu_LINK_STATUS_epvf__SLOT_CLOCK_CFG_MASK 0x00001000L -#define nbif_gpu_LINK_STATUS_epvf__DL_ACTIVE_MASK 0x00002000L -#define nbif_gpu_LINK_STATUS_epvf__LINK_BW_MANAGEMENT_STATUS_MASK 0x00004000L -#define nbif_gpu_LINK_STATUS_epvf__LINK_AUTONOMOUS_BW_STATUS_MASK 0x00008000L - -// nbif_gpu_DEVICE_CAP2_epvf -#define nbif_gpu_DEVICE_CAP2_epvf__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000fL -#define nbif_gpu_DEVICE_CAP2_epvf__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L -#define nbif_gpu_DEVICE_CAP2_epvf__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L -#define nbif_gpu_DEVICE_CAP2_epvf__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L -#define nbif_gpu_DEVICE_CAP2_epvf__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L -#define nbif_gpu_DEVICE_CAP2_epvf__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L -#define nbif_gpu_DEVICE_CAP2_epvf__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L -#define nbif_gpu_DEVICE_CAP2_epvf__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L -#define nbif_gpu_DEVICE_CAP2_epvf__LTR_SUPPORTED_MASK 0x00000800L -#define nbif_gpu_DEVICE_CAP2_epvf__TPH_CPLR_SUPPORTED_MASK 0x00003000L -#define nbif_gpu_DEVICE_CAP2_epvf__OBFF_SUPPORTED_MASK 0x000c0000L -#define nbif_gpu_DEVICE_CAP2_epvf__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L -#define nbif_gpu_DEVICE_CAP2_epvf__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L -#define nbif_gpu_DEVICE_CAP2_epvf__MAX_END_END_TLP_PREFIXES_MASK 0x00c00000L - -// nbif_gpu_DEVICE_CNTL2_epvf -#define nbif_gpu_DEVICE_CNTL2_epvf__CPL_TIMEOUT_VALUE_MASK 0x0000000fL -#define nbif_gpu_DEVICE_CNTL2_epvf__CPL_TIMEOUT_DIS_MASK 0x00000010L -#define nbif_gpu_DEVICE_CNTL2_epvf__ARI_FORWARDING_EN_MASK 0x00000020L -#define nbif_gpu_DEVICE_CNTL2_epvf__ATOMICOP_REQUEST_EN_MASK 0x00000040L -#define nbif_gpu_DEVICE_CNTL2_epvf__ATOMICOP_EGRESS_BLOCKING_MASK 0x00000080L -#define nbif_gpu_DEVICE_CNTL2_epvf__IDO_REQUEST_ENABLE_MASK 0x00000100L -#define nbif_gpu_DEVICE_CNTL2_epvf__IDO_COMPLETION_ENABLE_MASK 0x00000200L -#define nbif_gpu_DEVICE_CNTL2_epvf__LTR_EN_MASK 0x00000400L -#define nbif_gpu_DEVICE_CNTL2_epvf__OBFF_EN_MASK 0x00006000L -#define nbif_gpu_DEVICE_CNTL2_epvf__END_END_TLP_PREFIX_BLOCKING_MASK 0x00008000L - -// nbif_gpu_DEVICE_STATUS2_epvf -#define nbif_gpu_DEVICE_STATUS2_epvf__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_LINK_CAP2_epvf -#define nbif_gpu_LINK_CAP2_epvf__SUPPORTED_LINK_SPEED_MASK 0x000000feL -#define nbif_gpu_LINK_CAP2_epvf__CROSSLINK_SUPPORTED_MASK 0x00000100L -#define nbif_gpu_LINK_CAP2_epvf__RESERVED_MASK 0xfffffe00L - -// nbif_gpu_LINK_CNTL2_epvf -#define nbif_gpu_LINK_CNTL2_epvf__TARGET_LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_CNTL2_epvf__ENTER_COMPLIANCE_MASK 0x00000010L -#define nbif_gpu_LINK_CNTL2_epvf__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x00000020L -#define nbif_gpu_LINK_CNTL2_epvf__SELECTABLE_DEEMPHASIS_MASK 0x00000040L -#define nbif_gpu_LINK_CNTL2_epvf__XMIT_MARGIN_MASK 0x00000380L -#define nbif_gpu_LINK_CNTL2_epvf__ENTER_MOD_COMPLIANCE_MASK 0x00000400L -#define nbif_gpu_LINK_CNTL2_epvf__COMPLIANCE_SOS_MASK 0x00000800L -#define nbif_gpu_LINK_CNTL2_epvf__COMPLIANCE_DEEMPHASIS_MASK 0x0000f000L - -// nbif_gpu_LINK_STATUS2_epvf -#define nbif_gpu_LINK_STATUS2_epvf__CUR_DEEMPHASIS_LEVEL_MASK 0x00000001L -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_COMPLETE_MASK 0x00000002L -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_PHASE1_SUCCESS_MASK 0x00000004L -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_PHASE2_SUCCESS_MASK 0x00000008L -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_PHASE3_SUCCESS_MASK 0x00000010L -#define nbif_gpu_LINK_STATUS2_epvf__LINK_EQUALIZATION_REQUEST_MASK 0x00000020L - -// nbif_gpu_SLOT_CAP2_epvf -#define nbif_gpu_SLOT_CAP2_epvf__RESERVED_MASK 0xffffffffL - -// nbif_gpu_SLOT_CNTL2_epvf -#define nbif_gpu_SLOT_CNTL2_epvf__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_SLOT_STATUS2_epvf -#define nbif_gpu_SLOT_STATUS2_epvf__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_MSI_CAP_LIST_epvf -#define nbif_gpu_MSI_CAP_LIST_epvf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_MSI_CAP_LIST_epvf__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_MSI_MSG_CNTL_epvf -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_EN_MASK 0x00000001L -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_MULTI_CAP_MASK 0x0000000eL -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_MULTI_EN_MASK 0x00000070L -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_64BIT_MASK 0x00000080L -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_PERVECTOR_MASKING_CAP_MASK 0x00000100L - -// nbif_gpu_MSI_MSG_ADDR_LO_epvf -#define nbif_gpu_MSI_MSG_ADDR_LO_epvf__MSI_MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_MSI_MSG_ADDR_HI_epvf -#define nbif_gpu_MSI_MSG_ADDR_HI_epvf__MSI_MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_MSI_MSG_DATA_64_epvf -#define nbif_gpu_MSI_MSG_DATA_64_epvf__MSI_DATA_64_MASK 0x0000ffffL - -// nbif_gpu_MSI_MSG_DATA_epvf -#define nbif_gpu_MSI_MSG_DATA_epvf__MSI_DATA_MASK 0x0000ffffL - -// nbif_gpu_MSI_MASK_epvf -#define nbif_gpu_MSI_MASK_epvf__MSI_MASK_MASK 0xffffffffL - -// nbif_gpu_MSI_PENDING_epvf -#define nbif_gpu_MSI_PENDING_epvf__MSI_PENDING_MASK 0xffffffffL - -// nbif_gpu_MSI_MASK_64_epvf -#define nbif_gpu_MSI_MASK_64_epvf__MSI_MASK_64_MASK 0xffffffffL - -// nbif_gpu_MSI_PENDING_64_epvf -#define nbif_gpu_MSI_PENDING_64_epvf__MSI_PENDING_64_MASK 0xffffffffL - -// nbif_gpu_MSIX_CAP_LIST_epvf -#define nbif_gpu_MSIX_CAP_LIST_epvf__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_MSIX_CAP_LIST_epvf__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_MSIX_MSG_CNTL_epvf -#define nbif_gpu_MSIX_MSG_CNTL_epvf__MSIX_TABLE_SIZE_MASK 0x000007ffL -#define nbif_gpu_MSIX_MSG_CNTL_epvf__MSIX_FUNC_MASK_MASK 0x00004000L -#define nbif_gpu_MSIX_MSG_CNTL_epvf__MSIX_EN_MASK 0x00008000L - -// nbif_gpu_MSIX_TABLE_epvf -#define nbif_gpu_MSIX_TABLE_epvf__MSIX_TABLE_BIR_MASK 0x00000007L -#define nbif_gpu_MSIX_TABLE_epvf__MSIX_TABLE_OFFSET_MASK 0xfffffff8L - -// nbif_gpu_MSIX_PBA_epvf -#define nbif_gpu_MSIX_PBA_epvf__MSIX_PBA_BIR_MASK 0x00000007L -#define nbif_gpu_MSIX_PBA_epvf__MSIX_PBA_OFFSET_MASK 0xfffffff8L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf__VSEC_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf__VSEC_REV_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf__VSEC_LENGTH_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf__SCRATCH_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf__SCRATCH_MASK 0xffffffffL - -// nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__DLP_ERR_STATUS_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__SURPDN_ERR_STATUS_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__PSN_ERR_STATUS_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__FC_ERR_STATUS_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__CPL_TIMEOUT_STATUS_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__CPL_ABORT_ERR_STATUS_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__UNEXP_CPL_STATUS_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__RCV_OVFL_STATUS_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__MAL_TLP_STATUS_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__ECRC_ERR_STATUS_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__ACS_VIOLATION_STATUS_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__UNCORR_INT_ERR_STATUS_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L - -// nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__DLP_ERR_MASK_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__SURPDN_ERR_MASK_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__PSN_ERR_MASK_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__FC_ERR_MASK_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__CPL_TIMEOUT_MASK_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__CPL_ABORT_ERR_MASK_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__UNEXP_CPL_MASK_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__RCV_OVFL_MASK_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__MAL_TLP_MASK_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__ECRC_ERR_MASK_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__ACS_VIOLATION_MASK_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__UNCORR_INT_ERR_MASK_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__MC_BLOCKED_TLP_MASK_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L - -// nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__DLP_ERR_SEVERITY_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__SURPDN_ERR_SEVERITY_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__PSN_ERR_SEVERITY_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__FC_ERR_SEVERITY_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__UNEXP_CPL_SEVERITY_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__RCV_OVFL_SEVERITY_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__MAL_TLP_SEVERITY_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__ECRC_ERR_SEVERITY_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__ACS_VIOLATION_SEVERITY_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L - -// nbif_gpu_PCIE_CORR_ERR_STATUS_epvf -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__RCV_ERR_STATUS_MASK 0x00000001L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__BAD_TLP_STATUS_MASK 0x00000040L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__BAD_DLLP_STATUS_MASK 0x00000080L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__CORR_INT_ERR_STATUS_MASK 0x00004000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__HDR_LOG_OVFL_STATUS_MASK 0x00008000L - -// nbif_gpu_PCIE_CORR_ERR_MASK_epvf -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__RCV_ERR_MASK_MASK 0x00000001L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__BAD_TLP_MASK_MASK 0x00000040L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__BAD_DLLP_MASK_MASK 0x00000080L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__CORR_INT_ERR_MASK_MASK 0x00004000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__HDR_LOG_OVFL_MASK_MASK 0x00008000L - -// nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__FIRST_ERR_PTR_MASK 0x0000001fL -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_GEN_CAP_MASK 0x00000020L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_GEN_EN_MASK 0x00000040L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_CHECK_CAP_MASK 0x00000080L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_CHECK_EN_MASK 0x00000100L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__MULTI_HDR_RECD_CAP_MASK 0x00000200L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__MULTI_HDR_RECD_EN_MASK 0x00000400L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L - -// nbif_gpu_PCIE_HDR_LOG0_epvf -#define nbif_gpu_PCIE_HDR_LOG0_epvf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG1_epvf -#define nbif_gpu_PCIE_HDR_LOG1_epvf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG2_epvf -#define nbif_gpu_PCIE_HDR_LOG2_epvf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG3_epvf -#define nbif_gpu_PCIE_HDR_LOG3_epvf__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_ROOT_ERR_CMD_epvf -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epvf__CORR_ERR_REP_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epvf__NONFATAL_ERR_REP_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epvf__FATAL_ERR_REP_EN_MASK 0x00000004L - -// nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__ERR_CORR_RCVD_MASK 0x00000001L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__MULT_ERR_CORR_RCVD_MASK 0x00000002L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000L - -// nbif_gpu_PCIE_ERR_SRC_ID_epvf -#define nbif_gpu_PCIE_ERR_SRC_ID_epvf__ERR_CORR_SRC_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ERR_SRC_ID_epvf__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000L - -// nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_ATS_CAP_epvf -#define nbif_gpu_PCIE_ATS_CAP_epvf__INVALIDATE_Q_DEPTH_MASK 0x0000001fL -#define nbif_gpu_PCIE_ATS_CAP_epvf__PAGE_ALIGNED_REQUEST_MASK 0x00000020L -#define nbif_gpu_PCIE_ATS_CAP_epvf__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x00000040L - -// nbif_gpu_PCIE_ATS_CNTL_epvf -#define nbif_gpu_PCIE_ATS_CNTL_epvf__STU_MASK 0x0000001fL -#define nbif_gpu_PCIE_ATS_CNTL_epvf__ATC_ENABLE_MASK 0x00008000L - -// nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_ARI_CAP_epvf -#define nbif_gpu_PCIE_ARI_CAP_epvf__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x00000001L -#define nbif_gpu_PCIE_ARI_CAP_epvf__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x00000002L -#define nbif_gpu_PCIE_ARI_CAP_epvf__ARI_NEXT_FUNC_NUM_MASK 0x0000ff00L - -// nbif_gpu_PCIE_ARI_CNTL_epvf -#define nbif_gpu_PCIE_ARI_CNTL_epvf__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_ARI_CNTL_epvf__ARI_ACS_FUNC_GROUPS_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_ARI_CNTL_epvf__ARI_FUNCTION_GROUP_MASK 0x00000070L - -// nbif_gpu_RCC_BACO_CNTL_MISC -#define nbif_gpu_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L -#define nbif_gpu_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L - -// nbif_gpu_RCC_RESET_EN -#define nbif_gpu_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L - -// nbif_gpu_RCC_VDM_SUPPORT -#define nbif_gpu_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L -#define nbif_gpu_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L -#define nbif_gpu_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L -#define nbif_gpu_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L -#define nbif_gpu_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L - -// nbif_gpu_RCC_BUS_CNTL -#define nbif_gpu_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L -#define nbif_gpu_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L -#define nbif_gpu_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L -#define nbif_gpu_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L -#define nbif_gpu_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L -#define nbif_gpu_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L -#define nbif_gpu_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L -#define nbif_gpu_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L -#define nbif_gpu_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L -#define nbif_gpu_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L -#define nbif_gpu_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L -#define nbif_gpu_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L -#define nbif_gpu_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L -#define nbif_gpu_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L -#define nbif_gpu_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L -#define nbif_gpu_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L -#define nbif_gpu_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0e000000L -#define nbif_gpu_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L -#define nbif_gpu_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe0000000L - -// nbif_gpu_RCC_CONFIG_CNTL -#define nbif_gpu_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L -#define nbif_gpu_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L -#define nbif_gpu_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L - -// nbif_gpu_RCC_CONFIG_F0_BASE -#define nbif_gpu_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xffffffffL - -// nbif_gpu_RCC_CONFIG_APER_SIZE -#define nbif_gpu_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffffL - -// nbif_gpu_RCC_CONFIG_REG_APER_SIZE -#define nbif_gpu_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000fffffL - -// nbif_gpu_RCC_XDMA_LO -#define nbif_gpu_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffffL -#define nbif_gpu_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L - -// nbif_gpu_RCC_XDMA_HI -#define nbif_gpu_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffffL - -// nbif_gpu_RCC_FEATURES_CONTROL_MISC -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L - -// nbif_gpu_RCC_BUSNUM_CNTL1 -#define nbif_gpu_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000ffL - -// nbif_gpu_RCC_BUSNUM_LIST0 -#define nbif_gpu_RCC_BUSNUM_LIST0__ID0_MASK 0x000000ffL -#define nbif_gpu_RCC_BUSNUM_LIST0__ID1_MASK 0x0000ff00L -#define nbif_gpu_RCC_BUSNUM_LIST0__ID2_MASK 0x00ff0000L -#define nbif_gpu_RCC_BUSNUM_LIST0__ID3_MASK 0xff000000L - -// nbif_gpu_RCC_BUSNUM_LIST1 -#define nbif_gpu_RCC_BUSNUM_LIST1__ID4_MASK 0x000000ffL -#define nbif_gpu_RCC_BUSNUM_LIST1__ID5_MASK 0x0000ff00L -#define nbif_gpu_RCC_BUSNUM_LIST1__ID6_MASK 0x00ff0000L -#define nbif_gpu_RCC_BUSNUM_LIST1__ID7_MASK 0xff000000L - -// nbif_gpu_RCC_BUSNUM_CNTL2 -#define nbif_gpu_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000ffL -#define nbif_gpu_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L -#define nbif_gpu_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L -#define nbif_gpu_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L - -// nbif_gpu_RCC_CAPTURE_HOST_BUSNUM -#define nbif_gpu_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L - -// nbif_gpu_RCC_HOST_BUSNUM -#define nbif_gpu_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000ffffL - -// nbif_gpu_RCC_PEER0_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000fffffL - -// nbif_gpu_RCC_PEER0_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000fffffL -#define nbif_gpu_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L - -// nbif_gpu_RCC_PEER1_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000fffffL - -// nbif_gpu_RCC_PEER1_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000fffffL -#define nbif_gpu_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L - -// nbif_gpu_RCC_PEER2_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000fffffL - -// nbif_gpu_RCC_PEER2_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000fffffL -#define nbif_gpu_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L - -// nbif_gpu_RCC_PEER3_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000fffffL - -// nbif_gpu_RCC_PEER3_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000fffffL -#define nbif_gpu_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L - -// nbif_gpu_RCC_DEVFUNCNUM_LIST0 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000ffL -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00ff0000L -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000L - -// nbif_gpu_RCC_DEVFUNCNUM_LIST1 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000ffL -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00ff0000L -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000L - -// nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO -#define nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK 0x0000ffffL -#define nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK 0xffff0000L - -// nbif_gpu_RCC_DEV0_LINK_CNTL -#define nbif_gpu_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L - -// nbif_gpu_RCC_CMN_LINK_CNTL -#define nbif_gpu_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L -#define nbif_gpu_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L -#define nbif_gpu_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L -#define nbif_gpu_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L - -// nbif_gpu_RCC_EP_REQUESTERID_RESTORE -#define nbif_gpu_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000ffL -#define nbif_gpu_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001f00L - -// nbif_gpu_RCC_LTR_LSWITCH_CNTL -#define nbif_gpu_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003ffL - -// nbif_gpu_RCC_MH_ARB_CNTL -#define nbif_gpu_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L -#define nbif_gpu_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007ffeL - -// nbif_gpu_GFXMSIX_VECT0_ADDR_LO -#define nbif_gpu_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_GFXMSIX_VECT1_ADDR_LO -#define nbif_gpu_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_GFXMSIX_VECT2_ADDR_LO -#define nbif_gpu_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_GFXMSIX_VECT0_ADDR_HI -#define nbif_gpu_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_GFXMSIX_VECT1_ADDR_HI -#define nbif_gpu_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_GFXMSIX_VECT2_ADDR_HI -#define nbif_gpu_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_GFXMSIX_VECT0_MSG_DATA -#define nbif_gpu_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_GFXMSIX_VECT1_MSG_DATA -#define nbif_gpu_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_GFXMSIX_VECT2_MSG_DATA -#define nbif_gpu_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_GFXMSIX_VECT0_CONTROL -#define nbif_gpu_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_GFXMSIX_VECT1_CONTROL -#define nbif_gpu_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_GFXMSIX_VECT2_CONTROL -#define nbif_gpu_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_GFXMSIX_PBA -#define nbif_gpu_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L -#define nbif_gpu_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L -#define nbif_gpu_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L - -// nbif_gpu_RCC_DOORBELL_APER_EN -#define nbif_gpu_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L - -// nbif_gpu_RCC_CONFIG_MEMSIZE -#define nbif_gpu_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffffL - -// nbif_gpu_RCC_CONFIG_RESERVED -#define nbif_gpu_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffffL - -// nbif_gpu_RCC_IOV_FUNC_IDENTIFIER -#define nbif_gpu_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L -#define nbif_gpu_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L - -// nbif_gpu_DN_PCIE_RESERVED -#define nbif_gpu_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffffL - -// nbif_gpu_DN_PCIE_SCRATCH -#define nbif_gpu_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffffL - -// nbif_gpu_DN_PCIE_HW_DEBUG -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L - -// nbif_gpu_DN_PCIE_CNTL -#define nbif_gpu_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L -#define nbif_gpu_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L -#define nbif_gpu_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L - -// nbif_gpu_DN_PCIE_CONFIG_CNTL -#define nbif_gpu_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L - -// nbif_gpu_DN_PCIE_RX_CNTL2 -#define nbif_gpu_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L - -// nbif_gpu_DN_PCIE_BUS_CNTL -#define nbif_gpu_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L -#define nbif_gpu_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L - -// nbif_gpu_DN_PCIE_CFG_CNTL -#define nbif_gpu_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L -#define nbif_gpu_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L -#define nbif_gpu_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L - -// nbif_gpu_DN_PCIE_STRAP_F0 -#define nbif_gpu_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L -#define nbif_gpu_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L -#define nbif_gpu_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00e00000L - -// nbif_gpu_DN_PCIE_STRAP_MISC -#define nbif_gpu_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L -#define nbif_gpu_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L - -// nbif_gpu_DN_PCIE_STRAP_MISC2 -#define nbif_gpu_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L - -// nbif_gpu_PCIEP_RESERVED -#define nbif_gpu_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffffL - -// nbif_gpu_PCIEP_SCRATCH -#define nbif_gpu_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffffL - -// nbif_gpu_PCIEP_HW_DEBUG -#define nbif_gpu_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define nbif_gpu_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L - -// nbif_gpu_PCIE_ERR_CNTL -#define nbif_gpu_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L -#define nbif_gpu_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L -#define nbif_gpu_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L -#define nbif_gpu_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L - -// nbif_gpu_PCIE_RX_CNTL -#define nbif_gpu_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L -#define nbif_gpu_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L -#define nbif_gpu_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L -#define nbif_gpu_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L -#define nbif_gpu_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L - -// nbif_gpu_PCIE_LC_SPEED_CNTL -#define nbif_gpu_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L -#define nbif_gpu_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L - -// nbif_gpu_PCIE_LC_CNTL2 -#define nbif_gpu_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L - -// nbif_gpu_PCIEP_STRAP_MISC -#define nbif_gpu_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L - -// nbif_gpu_LTR_MSG_INFO_FROM_EP -#define nbif_gpu_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xffffffffL - -// nbif_gpu_VENDOR_ID_swds -#define nbif_gpu_VENDOR_ID_swds__VENDOR_ID_MASK 0x0000ffffL - -// nbif_gpu_DEVICE_ID_swds -#define nbif_gpu_DEVICE_ID_swds__DEVICE_ID_MASK 0x0000ffffL - -// nbif_gpu_COMMAND_swds -#define nbif_gpu_COMMAND_swds__IOEN_DN_MASK 0x00000001L -#define nbif_gpu_COMMAND_swds__MEMEN_DN_MASK 0x00000002L -#define nbif_gpu_COMMAND_swds__BUS_MASTER_EN_MASK 0x00000004L -#define nbif_gpu_COMMAND_swds__SPECIAL_CYCLE_EN_MASK 0x00000008L -#define nbif_gpu_COMMAND_swds__MEM_WRITE_INVALIDATE_EN_MASK 0x00000010L -#define nbif_gpu_COMMAND_swds__PAL_SNOOP_EN_MASK 0x00000020L -#define nbif_gpu_COMMAND_swds__PARITY_ERROR_RESPONSE_MASK 0x00000040L -#define nbif_gpu_COMMAND_swds__AD_STEPPING_MASK 0x00000080L -#define nbif_gpu_COMMAND_swds__SERR_EN_MASK 0x00000100L -#define nbif_gpu_COMMAND_swds__FAST_B2B_EN_MASK 0x00000200L -#define nbif_gpu_COMMAND_swds__INT_DIS_MASK 0x00000400L - -// nbif_gpu_STATUS_swds -#define nbif_gpu_STATUS_swds__INT_STATUS_MASK 0x00000008L -#define nbif_gpu_STATUS_swds__CAP_LIST_MASK 0x00000010L -#define nbif_gpu_STATUS_swds__PCI_66_EN_MASK 0x00000020L -#define nbif_gpu_STATUS_swds__FAST_BACK_CAPABLE_MASK 0x00000080L -#define nbif_gpu_STATUS_swds__MASTER_DATA_PARITY_ERROR_MASK 0x00000100L -#define nbif_gpu_STATUS_swds__DEVSEL_TIMING_MASK 0x00000600L -#define nbif_gpu_STATUS_swds__SIGNAL_TARGET_ABORT_MASK 0x00000800L -#define nbif_gpu_STATUS_swds__RECEIVED_TARGET_ABORT_MASK 0x00001000L -#define nbif_gpu_STATUS_swds__RECEIVED_MASTER_ABORT_MASK 0x00002000L -#define nbif_gpu_STATUS_swds__SIGNALED_SYSTEM_ERROR_MASK 0x00004000L -#define nbif_gpu_STATUS_swds__PARITY_ERROR_DETECTED_MASK 0x00008000L - -// nbif_gpu_REVISION_ID_swds -#define nbif_gpu_REVISION_ID_swds__MINOR_REV_ID_MASK 0x0000000fL -#define nbif_gpu_REVISION_ID_swds__MAJOR_REV_ID_MASK 0x000000f0L - -// nbif_gpu_PROG_INTERFACE_swds -#define nbif_gpu_PROG_INTERFACE_swds__PROG_INTERFACE_MASK 0x000000ffL - -// nbif_gpu_SUB_CLASS_swds -#define nbif_gpu_SUB_CLASS_swds__SUB_CLASS_MASK 0x000000ffL - -// nbif_gpu_BASE_CLASS_swds -#define nbif_gpu_BASE_CLASS_swds__BASE_CLASS_MASK 0x000000ffL - -// nbif_gpu_CACHE_LINE_swds -#define nbif_gpu_CACHE_LINE_swds__CACHE_LINE_SIZE_MASK 0x000000ffL - -// nbif_gpu_LATENCY_swds -#define nbif_gpu_LATENCY_swds__LATENCY_TIMER_MASK 0x000000ffL - -// nbif_gpu_HEADER_swds -#define nbif_gpu_HEADER_swds__HEADER_TYPE_MASK 0x0000007fL -#define nbif_gpu_HEADER_swds__DEVICE_TYPE_MASK 0x00000080L - -// nbif_gpu_BIST_swds -#define nbif_gpu_BIST_swds__BIST_COMP_MASK 0x0000000fL -#define nbif_gpu_BIST_swds__BIST_STRT_MASK 0x00000040L -#define nbif_gpu_BIST_swds__BIST_CAP_MASK 0x00000080L - -// nbif_gpu_BASE_ADDR_1_swds -#define nbif_gpu_BASE_ADDR_1_swds__BASE_ADDR_MASK 0xffffffffL - -// nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__PRIMARY_BUS_MASK 0x000000ffL -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__SECONDARY_BUS_MASK 0x0000ff00L -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__SUB_BUS_NUM_MASK 0x00ff0000L -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__SECONDARY_LATENCY_TIMER_MASK 0xff000000L - -// nbif_gpu_IO_BASE_LIMIT_swds -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_BASE_TYPE_MASK 0x0000000fL -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_BASE_MASK 0x000000f0L -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_LIMIT_TYPE_MASK 0x00000f00L -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_LIMIT_MASK 0x0000f000L - -// nbif_gpu_SECONDARY_STATUS_swds -#define nbif_gpu_SECONDARY_STATUS_swds__CAP_LIST_MASK 0x00000010L -#define nbif_gpu_SECONDARY_STATUS_swds__PCI_66_EN_MASK 0x00000020L -#define nbif_gpu_SECONDARY_STATUS_swds__FAST_BACK_CAPABLE_MASK 0x00000080L -#define nbif_gpu_SECONDARY_STATUS_swds__MASTER_DATA_PARITY_ERROR_MASK 0x00000100L -#define nbif_gpu_SECONDARY_STATUS_swds__DEVSEL_TIMING_MASK 0x00000600L -#define nbif_gpu_SECONDARY_STATUS_swds__SIGNAL_TARGET_ABORT_MASK 0x00000800L -#define nbif_gpu_SECONDARY_STATUS_swds__RECEIVED_TARGET_ABORT_MASK 0x00001000L -#define nbif_gpu_SECONDARY_STATUS_swds__RECEIVED_MASTER_ABORT_MASK 0x00002000L -#define nbif_gpu_SECONDARY_STATUS_swds__RECEIVED_SYSTEM_ERROR_MASK 0x00004000L -#define nbif_gpu_SECONDARY_STATUS_swds__PARITY_ERROR_DETECTED_MASK 0x00008000L - -// nbif_gpu_MEM_BASE_LIMIT_swds -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_BASE_TYPE_MASK 0x0000000fL -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_BASE_31_20_MASK 0x0000fff0L -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_LIMIT_TYPE_MASK 0x000f0000L -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_LIMIT_31_20_MASK 0xfff00000L - -// nbif_gpu_PREF_BASE_LIMIT_swds -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_BASE_TYPE_MASK 0x0000000fL -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_BASE_31_20_MASK 0x0000fff0L -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_LIMIT_TYPE_MASK 0x000f0000L -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_LIMIT_31_20_MASK 0xfff00000L - -// nbif_gpu_PREF_BASE_UPPER_swds -#define nbif_gpu_PREF_BASE_UPPER_swds__PREF_BASE_UPPER_MASK 0xffffffffL - -// nbif_gpu_PREF_LIMIT_UPPER_swds -#define nbif_gpu_PREF_LIMIT_UPPER_swds__PREF_LIMIT_UPPER_MASK 0xffffffffL - -// nbif_gpu_IO_BASE_LIMIT_HI_swds -#define nbif_gpu_IO_BASE_LIMIT_HI_swds__IO_BASE_31_16_MASK 0x0000ffffL -#define nbif_gpu_IO_BASE_LIMIT_HI_swds__IO_LIMIT_31_16_MASK 0xffff0000L - -// nbif_gpu_IRQ_BRIDGE_CNTL_swds -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__PARITY_RESPONSE_EN_MASK 0x00000001L -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__SERR_EN_MASK 0x00000002L -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__ISA_EN_MASK 0x00000004L -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__VGA_EN_MASK 0x00000008L -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__VGA_DEC_MASK 0x00000010L -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__MASTER_ABORT_MODE_MASK 0x00000020L -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__SECONDARY_BUS_RESET_MASK 0x00000040L -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__FAST_B2B_EN_MASK 0x00000080L - -// nbif_gpu_CAP_PTR_swds -#define nbif_gpu_CAP_PTR_swds__CAP_PTR_MASK 0x000000ffL - -// nbif_gpu_INTERRUPT_LINE_swds -#define nbif_gpu_INTERRUPT_LINE_swds__INTERRUPT_LINE_MASK 0x000000ffL - -// nbif_gpu_INTERRUPT_PIN_swds -#define nbif_gpu_INTERRUPT_PIN_swds__INTERRUPT_PIN_MASK 0x000000ffL - -// nbif_gpu_PMI_CAP_LIST_swds -#define nbif_gpu_PMI_CAP_LIST_swds__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_PMI_CAP_LIST_swds__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_PMI_CAP_swds -#define nbif_gpu_PMI_CAP_swds__VERSION_MASK 0x00000007L -#define nbif_gpu_PMI_CAP_swds__PME_CLOCK_MASK 0x00000008L -#define nbif_gpu_PMI_CAP_swds__DEV_SPECIFIC_INIT_MASK 0x00000020L -#define nbif_gpu_PMI_CAP_swds__AUX_CURRENT_MASK 0x000001c0L -#define nbif_gpu_PMI_CAP_swds__D1_SUPPORT_MASK 0x00000200L -#define nbif_gpu_PMI_CAP_swds__D2_SUPPORT_MASK 0x00000400L -#define nbif_gpu_PMI_CAP_swds__PME_SUPPORT_MASK 0x0000f800L - -// nbif_gpu_PMI_STATUS_CNTL_swds -#define nbif_gpu_PMI_STATUS_CNTL_swds__POWER_STATE_MASK 0x00000003L -#define nbif_gpu_PMI_STATUS_CNTL_swds__NO_SOFT_RESET_MASK 0x00000008L -#define nbif_gpu_PMI_STATUS_CNTL_swds__PME_EN_MASK 0x00000100L -#define nbif_gpu_PMI_STATUS_CNTL_swds__DATA_SELECT_MASK 0x00001e00L -#define nbif_gpu_PMI_STATUS_CNTL_swds__DATA_SCALE_MASK 0x00006000L -#define nbif_gpu_PMI_STATUS_CNTL_swds__PME_STATUS_MASK 0x00008000L -#define nbif_gpu_PMI_STATUS_CNTL_swds__B2_B3_SUPPORT_MASK 0x00400000L -#define nbif_gpu_PMI_STATUS_CNTL_swds__BUS_PWR_EN_MASK 0x00800000L -#define nbif_gpu_PMI_STATUS_CNTL_swds__PMI_DATA_MASK 0xff000000L - -// nbif_gpu_PCIE_CAP_LIST_swds -#define nbif_gpu_PCIE_CAP_LIST_swds__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_PCIE_CAP_LIST_swds__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_PCIE_CAP_swds -#define nbif_gpu_PCIE_CAP_swds__VERSION_MASK 0x0000000fL -#define nbif_gpu_PCIE_CAP_swds__DEVICE_TYPE_MASK 0x000000f0L -#define nbif_gpu_PCIE_CAP_swds__SLOT_IMPLEMENTED_MASK 0x00000100L -#define nbif_gpu_PCIE_CAP_swds__INT_MESSAGE_NUM_MASK 0x00003e00L - -// nbif_gpu_DEVICE_CAP_swds -#define nbif_gpu_DEVICE_CAP_swds__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L -#define nbif_gpu_DEVICE_CAP_swds__PHANTOM_FUNC_MASK 0x00000018L -#define nbif_gpu_DEVICE_CAP_swds__EXTENDED_TAG_MASK 0x00000020L -#define nbif_gpu_DEVICE_CAP_swds__L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0L -#define nbif_gpu_DEVICE_CAP_swds__L1_ACCEPTABLE_LATENCY_MASK 0x00000e00L -#define nbif_gpu_DEVICE_CAP_swds__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L -#define nbif_gpu_DEVICE_CAP_swds__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03fc0000L -#define nbif_gpu_DEVICE_CAP_swds__CAPTURED_SLOT_POWER_SCALE_MASK 0x0c000000L -#define nbif_gpu_DEVICE_CAP_swds__FLR_CAPABLE_MASK 0x10000000L - -// nbif_gpu_DEVICE_CNTL_swds -#define nbif_gpu_DEVICE_CNTL_swds__CORR_ERR_EN_MASK 0x00000001L -#define nbif_gpu_DEVICE_CNTL_swds__NON_FATAL_ERR_EN_MASK 0x00000002L -#define nbif_gpu_DEVICE_CNTL_swds__FATAL_ERR_EN_MASK 0x00000004L -#define nbif_gpu_DEVICE_CNTL_swds__USR_REPORT_EN_MASK 0x00000008L -#define nbif_gpu_DEVICE_CNTL_swds__RELAXED_ORD_EN_MASK 0x00000010L -#define nbif_gpu_DEVICE_CNTL_swds__MAX_PAYLOAD_SIZE_MASK 0x000000e0L -#define nbif_gpu_DEVICE_CNTL_swds__EXTENDED_TAG_EN_MASK 0x00000100L -#define nbif_gpu_DEVICE_CNTL_swds__PHANTOM_FUNC_EN_MASK 0x00000200L -#define nbif_gpu_DEVICE_CNTL_swds__AUX_POWER_PM_EN_MASK 0x00000400L -#define nbif_gpu_DEVICE_CNTL_swds__NO_SNOOP_EN_MASK 0x00000800L -#define nbif_gpu_DEVICE_CNTL_swds__MAX_READ_REQUEST_SIZE_MASK 0x00007000L -#define nbif_gpu_DEVICE_CNTL_swds__BRIDGE_CFG_RETRY_EN_MASK 0x00008000L - -// nbif_gpu_DEVICE_STATUS_swds -#define nbif_gpu_DEVICE_STATUS_swds__CORR_ERR_MASK 0x00000001L -#define nbif_gpu_DEVICE_STATUS_swds__NON_FATAL_ERR_MASK 0x00000002L -#define nbif_gpu_DEVICE_STATUS_swds__FATAL_ERR_MASK 0x00000004L -#define nbif_gpu_DEVICE_STATUS_swds__USR_DETECTED_MASK 0x00000008L -#define nbif_gpu_DEVICE_STATUS_swds__AUX_PWR_MASK 0x00000010L -#define nbif_gpu_DEVICE_STATUS_swds__TRANSACTIONS_PEND_MASK 0x00000020L - -// nbif_gpu_LINK_CAP_swds -#define nbif_gpu_LINK_CAP_swds__LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_CAP_swds__LINK_WIDTH_MASK 0x000003f0L -#define nbif_gpu_LINK_CAP_swds__PM_SUPPORT_MASK 0x00000c00L -#define nbif_gpu_LINK_CAP_swds__L0S_EXIT_LATENCY_MASK 0x00007000L -#define nbif_gpu_LINK_CAP_swds__L1_EXIT_LATENCY_MASK 0x00038000L -#define nbif_gpu_LINK_CAP_swds__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L -#define nbif_gpu_LINK_CAP_swds__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L -#define nbif_gpu_LINK_CAP_swds__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L -#define nbif_gpu_LINK_CAP_swds__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L -#define nbif_gpu_LINK_CAP_swds__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L -#define nbif_gpu_LINK_CAP_swds__PORT_NUMBER_MASK 0xff000000L - -// nbif_gpu_LINK_CNTL_swds -#define nbif_gpu_LINK_CNTL_swds__PM_CONTROL_MASK 0x00000003L -#define nbif_gpu_LINK_CNTL_swds__READ_CPL_BOUNDARY_MASK 0x00000008L -#define nbif_gpu_LINK_CNTL_swds__LINK_DIS_MASK 0x00000010L -#define nbif_gpu_LINK_CNTL_swds__RETRAIN_LINK_MASK 0x00000020L -#define nbif_gpu_LINK_CNTL_swds__COMMON_CLOCK_CFG_MASK 0x00000040L -#define nbif_gpu_LINK_CNTL_swds__EXTENDED_SYNC_MASK 0x00000080L -#define nbif_gpu_LINK_CNTL_swds__CLOCK_POWER_MANAGEMENT_EN_MASK 0x00000100L -#define nbif_gpu_LINK_CNTL_swds__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x00000200L -#define nbif_gpu_LINK_CNTL_swds__LINK_BW_MANAGEMENT_INT_EN_MASK 0x00000400L -#define nbif_gpu_LINK_CNTL_swds__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x00000800L - -// nbif_gpu_LINK_STATUS_swds -#define nbif_gpu_LINK_STATUS_swds__CURRENT_LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_STATUS_swds__NEGOTIATED_LINK_WIDTH_MASK 0x000003f0L -#define nbif_gpu_LINK_STATUS_swds__LINK_TRAINING_MASK 0x00000800L -#define nbif_gpu_LINK_STATUS_swds__SLOT_CLOCK_CFG_MASK 0x00001000L -#define nbif_gpu_LINK_STATUS_swds__DL_ACTIVE_MASK 0x00002000L -#define nbif_gpu_LINK_STATUS_swds__LINK_BW_MANAGEMENT_STATUS_MASK 0x00004000L -#define nbif_gpu_LINK_STATUS_swds__LINK_AUTONOMOUS_BW_STATUS_MASK 0x00008000L - -// nbif_gpu_SLOT_CAP_swds -#define nbif_gpu_SLOT_CAP_swds__ATTN_BUTTON_PRESENT_MASK 0x00000001L -#define nbif_gpu_SLOT_CAP_swds__PWR_CONTROLLER_PRESENT_MASK 0x00000002L -#define nbif_gpu_SLOT_CAP_swds__MRL_SENSOR_PRESENT_MASK 0x00000004L -#define nbif_gpu_SLOT_CAP_swds__ATTN_INDICATOR_PRESENT_MASK 0x00000008L -#define nbif_gpu_SLOT_CAP_swds__PWR_INDICATOR_PRESENT_MASK 0x00000010L -#define nbif_gpu_SLOT_CAP_swds__HOTPLUG_SURPRISE_MASK 0x00000020L -#define nbif_gpu_SLOT_CAP_swds__HOTPLUG_CAPABLE_MASK 0x00000040L -#define nbif_gpu_SLOT_CAP_swds__SLOT_PWR_LIMIT_VALUE_MASK 0x00007f80L -#define nbif_gpu_SLOT_CAP_swds__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L -#define nbif_gpu_SLOT_CAP_swds__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L -#define nbif_gpu_SLOT_CAP_swds__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L -#define nbif_gpu_SLOT_CAP_swds__PHYSICAL_SLOT_NUM_MASK 0xfff80000L - -// nbif_gpu_SLOT_CNTL_swds -#define nbif_gpu_SLOT_CNTL_swds__ATTN_BUTTON_PRESSED_EN_MASK 0x00000001L -#define nbif_gpu_SLOT_CNTL_swds__PWR_FAULT_DETECTED_EN_MASK 0x00000002L -#define nbif_gpu_SLOT_CNTL_swds__MRL_SENSOR_CHANGED_EN_MASK 0x00000004L -#define nbif_gpu_SLOT_CNTL_swds__PRESENCE_DETECT_CHANGED_EN_MASK 0x00000008L -#define nbif_gpu_SLOT_CNTL_swds__COMMAND_COMPLETED_INTR_EN_MASK 0x00000010L -#define nbif_gpu_SLOT_CNTL_swds__HOTPLUG_INTR_EN_MASK 0x00000020L -#define nbif_gpu_SLOT_CNTL_swds__ATTN_INDICATOR_CNTL_MASK 0x000000c0L -#define nbif_gpu_SLOT_CNTL_swds__PWR_INDICATOR_CNTL_MASK 0x00000300L -#define nbif_gpu_SLOT_CNTL_swds__PWR_CONTROLLER_CNTL_MASK 0x00000400L -#define nbif_gpu_SLOT_CNTL_swds__ELECTROMECH_INTERLOCK_CNTL_MASK 0x00000800L -#define nbif_gpu_SLOT_CNTL_swds__DL_STATE_CHANGED_EN_MASK 0x00001000L - -// nbif_gpu_SLOT_STATUS_swds -#define nbif_gpu_SLOT_STATUS_swds__ATTN_BUTTON_PRESSED_MASK 0x00000001L -#define nbif_gpu_SLOT_STATUS_swds__PWR_FAULT_DETECTED_MASK 0x00000002L -#define nbif_gpu_SLOT_STATUS_swds__MRL_SENSOR_CHANGED_MASK 0x00000004L -#define nbif_gpu_SLOT_STATUS_swds__PRESENCE_DETECT_CHANGED_MASK 0x00000008L -#define nbif_gpu_SLOT_STATUS_swds__COMMAND_COMPLETED_MASK 0x00000010L -#define nbif_gpu_SLOT_STATUS_swds__MRL_SENSOR_STATE_MASK 0x00000020L -#define nbif_gpu_SLOT_STATUS_swds__PRESENCE_DETECT_STATE_MASK 0x00000040L -#define nbif_gpu_SLOT_STATUS_swds__ELECTROMECH_INTERLOCK_STATUS_MASK 0x00000080L -#define nbif_gpu_SLOT_STATUS_swds__DL_STATE_CHANGED_MASK 0x00000100L - -// nbif_gpu_DEVICE_CAP2_swds -#define nbif_gpu_DEVICE_CAP2_swds__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000fL -#define nbif_gpu_DEVICE_CAP2_swds__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L -#define nbif_gpu_DEVICE_CAP2_swds__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L -#define nbif_gpu_DEVICE_CAP2_swds__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L -#define nbif_gpu_DEVICE_CAP2_swds__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L -#define nbif_gpu_DEVICE_CAP2_swds__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L -#define nbif_gpu_DEVICE_CAP2_swds__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L -#define nbif_gpu_DEVICE_CAP2_swds__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L -#define nbif_gpu_DEVICE_CAP2_swds__LTR_SUPPORTED_MASK 0x00000800L -#define nbif_gpu_DEVICE_CAP2_swds__TPH_CPLR_SUPPORTED_MASK 0x00003000L -#define nbif_gpu_DEVICE_CAP2_swds__OBFF_SUPPORTED_MASK 0x000c0000L -#define nbif_gpu_DEVICE_CAP2_swds__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L -#define nbif_gpu_DEVICE_CAP2_swds__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L -#define nbif_gpu_DEVICE_CAP2_swds__MAX_END_END_TLP_PREFIXES_MASK 0x00c00000L - -// nbif_gpu_DEVICE_CNTL2_swds -#define nbif_gpu_DEVICE_CNTL2_swds__CPL_TIMEOUT_VALUE_MASK 0x0000000fL -#define nbif_gpu_DEVICE_CNTL2_swds__CPL_TIMEOUT_DIS_MASK 0x00000010L -#define nbif_gpu_DEVICE_CNTL2_swds__ARI_FORWARDING_EN_MASK 0x00000020L -#define nbif_gpu_DEVICE_CNTL2_swds__ATOMICOP_REQUEST_EN_MASK 0x00000040L -#define nbif_gpu_DEVICE_CNTL2_swds__ATOMICOP_EGRESS_BLOCKING_MASK 0x00000080L -#define nbif_gpu_DEVICE_CNTL2_swds__IDO_REQUEST_ENABLE_MASK 0x00000100L -#define nbif_gpu_DEVICE_CNTL2_swds__IDO_COMPLETION_ENABLE_MASK 0x00000200L -#define nbif_gpu_DEVICE_CNTL2_swds__LTR_EN_MASK 0x00000400L -#define nbif_gpu_DEVICE_CNTL2_swds__OBFF_EN_MASK 0x00006000L -#define nbif_gpu_DEVICE_CNTL2_swds__END_END_TLP_PREFIX_BLOCKING_MASK 0x00008000L - -// nbif_gpu_DEVICE_STATUS2_swds -#define nbif_gpu_DEVICE_STATUS2_swds__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_LINK_CAP2_swds -#define nbif_gpu_LINK_CAP2_swds__SUPPORTED_LINK_SPEED_MASK 0x000000feL -#define nbif_gpu_LINK_CAP2_swds__CROSSLINK_SUPPORTED_MASK 0x00000100L -#define nbif_gpu_LINK_CAP2_swds__RESERVED_MASK 0xfffffe00L - -// nbif_gpu_LINK_CNTL2_swds -#define nbif_gpu_LINK_CNTL2_swds__TARGET_LINK_SPEED_MASK 0x0000000fL -#define nbif_gpu_LINK_CNTL2_swds__ENTER_COMPLIANCE_MASK 0x00000010L -#define nbif_gpu_LINK_CNTL2_swds__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x00000020L -#define nbif_gpu_LINK_CNTL2_swds__SELECTABLE_DEEMPHASIS_MASK 0x00000040L -#define nbif_gpu_LINK_CNTL2_swds__XMIT_MARGIN_MASK 0x00000380L -#define nbif_gpu_LINK_CNTL2_swds__ENTER_MOD_COMPLIANCE_MASK 0x00000400L -#define nbif_gpu_LINK_CNTL2_swds__COMPLIANCE_SOS_MASK 0x00000800L -#define nbif_gpu_LINK_CNTL2_swds__COMPLIANCE_DEEMPHASIS_MASK 0x0000f000L - -// nbif_gpu_LINK_STATUS2_swds -#define nbif_gpu_LINK_STATUS2_swds__CUR_DEEMPHASIS_LEVEL_MASK 0x00000001L -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_COMPLETE_MASK 0x00000002L -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_PHASE1_SUCCESS_MASK 0x00000004L -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_PHASE2_SUCCESS_MASK 0x00000008L -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_PHASE3_SUCCESS_MASK 0x00000010L -#define nbif_gpu_LINK_STATUS2_swds__LINK_EQUALIZATION_REQUEST_MASK 0x00000020L - -// nbif_gpu_SLOT_CAP2_swds -#define nbif_gpu_SLOT_CAP2_swds__RESERVED_MASK 0xffffffffL - -// nbif_gpu_SLOT_CNTL2_swds -#define nbif_gpu_SLOT_CNTL2_swds__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_SLOT_STATUS2_swds -#define nbif_gpu_SLOT_STATUS2_swds__RESERVED_MASK 0x0000ffffL - -// nbif_gpu_MSI_CAP_LIST_swds -#define nbif_gpu_MSI_CAP_LIST_swds__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_MSI_CAP_LIST_swds__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_MSI_MSG_CNTL_swds -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_EN_MASK 0x00000001L -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_MULTI_CAP_MASK 0x0000000eL -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_MULTI_EN_MASK 0x00000070L -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_64BIT_MASK 0x00000080L -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_PERVECTOR_MASKING_CAP_MASK 0x00000100L - -// nbif_gpu_MSI_MSG_ADDR_LO_swds -#define nbif_gpu_MSI_MSG_ADDR_LO_swds__MSI_MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_MSI_MSG_ADDR_HI_swds -#define nbif_gpu_MSI_MSG_ADDR_HI_swds__MSI_MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_MSI_MSG_DATA_64_swds -#define nbif_gpu_MSI_MSG_DATA_64_swds__MSI_DATA_64_MASK 0x0000ffffL - -// nbif_gpu_MSI_MSG_DATA_swds -#define nbif_gpu_MSI_MSG_DATA_swds__MSI_DATA_MASK 0x0000ffffL - -// nbif_gpu_SSID_CAP_LIST_swds -#define nbif_gpu_SSID_CAP_LIST_swds__CAP_ID_MASK 0x000000ffL -#define nbif_gpu_SSID_CAP_LIST_swds__NEXT_PTR_MASK 0x0000ff00L - -// nbif_gpu_SSID_CAP_swds -#define nbif_gpu_SSID_CAP_swds__SUBSYSTEM_VENDOR_ID_MASK 0x0000ffffL -#define nbif_gpu_SSID_CAP_swds__SUBSYSTEM_ID_MASK 0xffff0000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds__VSEC_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds__VSEC_REV_MASK 0x000f0000L -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds__VSEC_LENGTH_MASK 0xfff00000L - -// nbif_gpu_PCIE_VENDOR_SPECIFIC1_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC1_swds__SCRATCH_MASK 0xffffffffL - -// nbif_gpu_PCIE_VENDOR_SPECIFIC2_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC2_swds__SCRATCH_MASK 0xffffffffL - -// nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__EXT_VC_COUNT_MASK 0x00000007L -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__REF_CLK_MASK 0x00000300L -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000c00L - -// nbif_gpu_PCIE_PORT_VC_CAP_REG2_swds -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_swds__VC_ARB_CAP_MASK 0x000000ffL -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_swds__VC_ARB_TABLE_OFFSET_MASK 0xff000000L - -// nbif_gpu_PCIE_PORT_VC_CNTL_swds -#define nbif_gpu_PCIE_PORT_VC_CNTL_swds__LOAD_VC_ARB_TABLE_MASK 0x00000001L -#define nbif_gpu_PCIE_PORT_VC_CNTL_swds__VC_ARB_SELECT_MASK 0x0000000eL - -// nbif_gpu_PCIE_PORT_VC_STATUS_swds -#define nbif_gpu_PCIE_PORT_VC_STATUS_swds__VC_ARB_TABLE_STATUS_MASK 0x00000001L - -// nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__PORT_ARB_CAP_MASK 0x000000ffL -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__REJECT_SNOOP_TRANS_MASK 0x00008000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__MAX_TIME_SLOTS_MASK 0x003f0000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__PORT_ARB_TABLE_OFFSET_MASK 0xff000000L - -// nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__TC_VC_MAP_TC0_MASK 0x00000001L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__TC_VC_MAP_TC1_7_MASK 0x000000feL -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__LOAD_PORT_ARB_TABLE_MASK 0x00010000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__PORT_ARB_SELECT_MASK 0x000e0000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__VC_ID_MASK 0x07000000L -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__VC_ENABLE_MASK 0x80000000L - -// nbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds__PORT_ARB_TABLE_STATUS_MASK 0x00000001L -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds__VC_NEGOTIATION_PENDING_MASK 0x00000002L - -// nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__PORT_ARB_CAP_MASK 0x000000ffL -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__REJECT_SNOOP_TRANS_MASK 0x00008000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__MAX_TIME_SLOTS_MASK 0x003f0000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__PORT_ARB_TABLE_OFFSET_MASK 0xff000000L - -// nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__TC_VC_MAP_TC0_MASK 0x00000001L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__TC_VC_MAP_TC1_7_MASK 0x000000feL -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__LOAD_PORT_ARB_TABLE_MASK 0x00010000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__PORT_ARB_SELECT_MASK 0x000e0000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__VC_ID_MASK 0x07000000L -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__VC_ENABLE_MASK 0x80000000L - -// nbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds__PORT_ARB_TABLE_STATUS_MASK 0x00000001L -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds__VC_NEGOTIATION_PENDING_MASK 0x00000002L - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds__SERIAL_NUMBER_LO_MASK 0xffffffffL - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds__SERIAL_NUMBER_HI_MASK 0xffffffffL - -// nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__DLP_ERR_STATUS_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__SURPDN_ERR_STATUS_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__PSN_ERR_STATUS_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__FC_ERR_STATUS_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__CPL_TIMEOUT_STATUS_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__CPL_ABORT_ERR_STATUS_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__UNEXP_CPL_STATUS_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__RCV_OVFL_STATUS_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__MAL_TLP_STATUS_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__ECRC_ERR_STATUS_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__ACS_VIOLATION_STATUS_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__UNCORR_INT_ERR_STATUS_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L - -// nbif_gpu_PCIE_UNCORR_ERR_MASK_swds -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__DLP_ERR_MASK_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__SURPDN_ERR_MASK_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__PSN_ERR_MASK_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__FC_ERR_MASK_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__CPL_TIMEOUT_MASK_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__CPL_ABORT_ERR_MASK_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__UNEXP_CPL_MASK_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__RCV_OVFL_MASK_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__MAL_TLP_MASK_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__ECRC_ERR_MASK_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__ACS_VIOLATION_MASK_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__UNCORR_INT_ERR_MASK_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__MC_BLOCKED_TLP_MASK_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L - -// nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__DLP_ERR_SEVERITY_MASK 0x00000010L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__SURPDN_ERR_SEVERITY_MASK 0x00000020L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__PSN_ERR_SEVERITY_MASK 0x00001000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__FC_ERR_SEVERITY_MASK 0x00002000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__UNEXP_CPL_SEVERITY_MASK 0x00010000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__RCV_OVFL_SEVERITY_MASK 0x00020000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__MAL_TLP_SEVERITY_MASK 0x00040000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__ECRC_ERR_SEVERITY_MASK 0x00080000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__ACS_VIOLATION_SEVERITY_MASK 0x00200000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L - -// nbif_gpu_PCIE_CORR_ERR_STATUS_swds -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__RCV_ERR_STATUS_MASK 0x00000001L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__BAD_TLP_STATUS_MASK 0x00000040L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__BAD_DLLP_STATUS_MASK 0x00000080L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__CORR_INT_ERR_STATUS_MASK 0x00004000L -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__HDR_LOG_OVFL_STATUS_MASK 0x00008000L - -// nbif_gpu_PCIE_CORR_ERR_MASK_swds -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__RCV_ERR_MASK_MASK 0x00000001L -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__BAD_TLP_MASK_MASK 0x00000040L -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__BAD_DLLP_MASK_MASK 0x00000080L -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__CORR_INT_ERR_MASK_MASK 0x00004000L -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__HDR_LOG_OVFL_MASK_MASK 0x00008000L - -// nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__FIRST_ERR_PTR_MASK 0x0000001fL -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_GEN_CAP_MASK 0x00000020L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_GEN_EN_MASK 0x00000040L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_CHECK_CAP_MASK 0x00000080L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_CHECK_EN_MASK 0x00000100L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__MULTI_HDR_RECD_CAP_MASK 0x00000200L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__MULTI_HDR_RECD_EN_MASK 0x00000400L -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L - -// nbif_gpu_PCIE_HDR_LOG0_swds -#define nbif_gpu_PCIE_HDR_LOG0_swds__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG1_swds -#define nbif_gpu_PCIE_HDR_LOG1_swds__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG2_swds -#define nbif_gpu_PCIE_HDR_LOG2_swds__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_HDR_LOG3_swds -#define nbif_gpu_PCIE_HDR_LOG3_swds__TLP_HDR_MASK 0xffffffffL - -// nbif_gpu_PCIE_ROOT_ERR_CMD_swds -#define nbif_gpu_PCIE_ROOT_ERR_CMD_swds__CORR_ERR_REP_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_ROOT_ERR_CMD_swds__NONFATAL_ERR_REP_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_ROOT_ERR_CMD_swds__FATAL_ERR_REP_EN_MASK 0x00000004L - -// nbif_gpu_PCIE_ROOT_ERR_STATUS_swds -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__ERR_CORR_RCVD_MASK 0x00000001L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__MULT_ERR_CORR_RCVD_MASK 0x00000002L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000L - -// nbif_gpu_PCIE_ERR_SRC_ID_swds -#define nbif_gpu_PCIE_ERR_SRC_ID_swds__ERR_CORR_SRC_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ERR_SRC_ID_swds__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000L - -// nbif_gpu_PCIE_TLP_PREFIX_LOG0_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG0_swds__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG1_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG1_swds__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG2_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG2_swds__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_TLP_PREFIX_LOG3_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG3_swds__TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_LINK_CNTL3_swds -#define nbif_gpu_PCIE_LINK_CNTL3_swds__PERFORM_EQUALIZATION_MASK 0x00000001L -#define nbif_gpu_PCIE_LINK_CNTL3_swds__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_LINK_CNTL3_swds__RESERVED_MASK 0xfffffffcL - -// nbif_gpu_PCIE_LANE_ERROR_STATUS_swds -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_swds__LANE_ERROR_STATUS_BITS_MASK 0x0000ffffL -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_swds__RESERVED_MASK 0xffff0000L - -// nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x00000070L -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK \ - 0x00000070L -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK \ - 0x00000070L -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK \ - 0x00000070L -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK \ - 0x00000070L -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK \ - 0x00000070L -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET_MASK 0x0000000fL -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK \ - 0x00000070L -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET_MASK 0x00000f00L -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x00007000L -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__RESERVED_MASK 0x00008000L - -// nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds__CAP_ID_MASK 0x0000ffffL -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds__CAP_VER_MASK 0x000f0000L -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds__NEXT_PTR_MASK 0xfff00000L - -// nbif_gpu_PCIE_ACS_CAP_swds -#define nbif_gpu_PCIE_ACS_CAP_swds__SOURCE_VALIDATION_MASK 0x00000001L -#define nbif_gpu_PCIE_ACS_CAP_swds__TRANSLATION_BLOCKING_MASK 0x00000002L -#define nbif_gpu_PCIE_ACS_CAP_swds__P2P_REQUEST_REDIRECT_MASK 0x00000004L -#define nbif_gpu_PCIE_ACS_CAP_swds__P2P_COMPLETION_REDIRECT_MASK 0x00000008L -#define nbif_gpu_PCIE_ACS_CAP_swds__UPSTREAM_FORWARDING_MASK 0x00000010L -#define nbif_gpu_PCIE_ACS_CAP_swds__P2P_EGRESS_CONTROL_MASK 0x00000020L -#define nbif_gpu_PCIE_ACS_CAP_swds__DIRECT_TRANSLATED_P2P_MASK 0x00000040L -#define nbif_gpu_PCIE_ACS_CAP_swds__EGRESS_CONTROL_VECTOR_SIZE_MASK 0x0000ff00L - -// nbif_gpu_PCIE_ACS_CNTL_swds -#define nbif_gpu_PCIE_ACS_CNTL_swds__SOURCE_VALIDATION_EN_MASK 0x00000001L -#define nbif_gpu_PCIE_ACS_CNTL_swds__TRANSLATION_BLOCKING_EN_MASK 0x00000002L -#define nbif_gpu_PCIE_ACS_CNTL_swds__P2P_REQUEST_REDIRECT_EN_MASK 0x00000004L -#define nbif_gpu_PCIE_ACS_CNTL_swds__P2P_COMPLETION_REDIRECT_EN_MASK 0x00000008L -#define nbif_gpu_PCIE_ACS_CNTL_swds__UPSTREAM_FORWARDING_EN_MASK 0x00000010L -#define nbif_gpu_PCIE_ACS_CNTL_swds__P2P_EGRESS_CONTROL_EN_MASK 0x00000020L -#define nbif_gpu_PCIE_ACS_CNTL_swds__DIRECT_TRANSLATED_P2P_EN_MASK 0x00000040L - -// nbif_gpu_SHADOW_COMMAND -#define nbif_gpu_SHADOW_COMMAND__IOEN_UP_MASK 0x00000001L -#define nbif_gpu_SHADOW_COMMAND__MEMEN_UP_MASK 0x00000002L - -// nbif_gpu_SHADOW_BASE_ADDR_1 -#define nbif_gpu_SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xffffffffL - -// nbif_gpu_SHADOW_BASE_ADDR_2 -#define nbif_gpu_SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xffffffffL - -// nbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY -#define nbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000ff00L -#define nbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00ff0000L - -// nbif_gpu_SHADOW_IO_BASE_LIMIT -#define nbif_gpu_SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x000000f0L -#define nbif_gpu_SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0x0000f000L - -// nbif_gpu_SHADOW_MEM_BASE_LIMIT -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000fL -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000fff0L -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000f0000L -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xfff00000L - -// nbif_gpu_SHADOW_PREF_BASE_LIMIT -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000fL -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000fff0L -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000f0000L -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xfff00000L - -// nbif_gpu_SHADOW_PREF_BASE_UPPER -#define nbif_gpu_SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xffffffffL - -// nbif_gpu_SHADOW_PREF_LIMIT_UPPER -#define nbif_gpu_SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xffffffffL - -// nbif_gpu_SHADOW_IO_BASE_LIMIT_HI -#define nbif_gpu_SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000ffffL -#define nbif_gpu_SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xffff0000L - -// nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x00000004L -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x00000008L -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x00000010L -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x00000040L - -// nbif_gpu_SUC_INDEX -#define nbif_gpu_SUC_INDEX__SUC_INDEX_MASK 0xffffffffL - -// nbif_gpu_SUC_DATA -#define nbif_gpu_SUC_DATA__SUC_DATA_MASK 0xffffffffL - -// nbif_gpu_EP_PCIE_SCRATCH -#define nbif_gpu_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffffL - -// nbif_gpu_EP_PCIE_HW_DEBUG -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L - -// nbif_gpu_EP_PCIE_CNTL -#define nbif_gpu_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L -#define nbif_gpu_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L -#define nbif_gpu_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L - -// nbif_gpu_EP_PCIE_INT_CNTL -#define nbif_gpu_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L -#define nbif_gpu_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L -#define nbif_gpu_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L -#define nbif_gpu_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L -#define nbif_gpu_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L -#define nbif_gpu_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L - -// nbif_gpu_EP_PCIE_INT_STATUS -#define nbif_gpu_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L -#define nbif_gpu_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L -#define nbif_gpu_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L -#define nbif_gpu_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L -#define nbif_gpu_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L -#define nbif_gpu_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L - -// nbif_gpu_EP_PCIE_RX_CNTL2 -#define nbif_gpu_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L - -// nbif_gpu_EP_PCIE_BUS_CNTL -#define nbif_gpu_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L - -// nbif_gpu_EP_PCIE_CFG_CNTL -#define nbif_gpu_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L -#define nbif_gpu_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L -#define nbif_gpu_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L - -// nbif_gpu_EP_PCIE_OBFF_CNTL -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x00000001L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x00000002L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x00000004L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x00000008L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0x000000f0L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0x00000f00L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0x0000f000L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x00010000L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x00020000L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x00040000L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK 0x00080000L -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0x00f00000L - -// nbif_gpu_EP_PCIE_TX_LTR_CNTL -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001c00L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L - -// nbif_gpu_EP_PCIE_STRAP_MISC -#define nbif_gpu_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L - -// nbif_gpu_EP_PCIE_STRAP_MISC2 -#define nbif_gpu_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L - -// nbif_gpu_EP_PCIE_STRAP_PI - -// nbif_gpu_EP_PCIE_F0_DPA_CAP -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00ff0000L -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000L - -// nbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR -#define nbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000ffL - -// nbif_gpu_EP_PCIE_F0_DPA_CNTL -#define nbif_gpu_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x0000001fL -#define nbif_gpu_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x00000100L - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL - -// nbif_gpu_EP_PCIE_PME_CONTROL -#define nbif_gpu_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x0000001fL - -// nbif_gpu_EP_PCIEP_RESERVED -#define nbif_gpu_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffffL - -// nbif_gpu_EP_PCIEP_HW_DEBUG -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L - -// nbif_gpu_EP_PCIE_TX_CNTL -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000c00L -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L - -// nbif_gpu_EP_PCIE_TX_REQUESTER_ID -#define nbif_gpu_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L -#define nbif_gpu_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000f8L -#define nbif_gpu_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000ff00L - -// nbif_gpu_EP_PCIE_ERR_CNTL -#define nbif_gpu_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L -#define nbif_gpu_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L - -// nbif_gpu_EP_PCIE_RX_CNTL -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L - -// nbif_gpu_EP_PCIE_LC_SPEED_CNTL -#define nbif_gpu_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L -#define nbif_gpu_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L - -// nbif_gpu_A2S_CNTL_CL0 -#define nbif_gpu_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L -#define nbif_gpu_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000cL -#define nbif_gpu_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L -#define nbif_gpu_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000c0L -#define nbif_gpu_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L -#define nbif_gpu_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000c00L -#define nbif_gpu_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L -#define nbif_gpu_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000c000L -#define nbif_gpu_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L -#define nbif_gpu_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000c0000L -#define nbif_gpu_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L - -// nbif_gpu_A2S_CNTL_CL1 -#define nbif_gpu_A2S_CNTL_CL1__NSNOOP_MAP_MASK 0x00000003L -#define nbif_gpu_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK 0x0000000cL -#define nbif_gpu_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK 0x00000030L -#define nbif_gpu_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK 0x000000c0L -#define nbif_gpu_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L -#define nbif_gpu_A2S_CNTL_CL1__BLKLVL_MAP_MASK 0x00000c00L -#define nbif_gpu_A2S_CNTL_CL1__DATERR_MAP_MASK 0x00003000L -#define nbif_gpu_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK 0x0000c000L -#define nbif_gpu_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK 0x00030000L -#define nbif_gpu_A2S_CNTL_CL1__RESP_WR_MAP_MASK 0x000c0000L -#define nbif_gpu_A2S_CNTL_CL1__RESP_RD_MAP_MASK 0x00300000L - -// nbif_gpu_A2S_CNTL_CL2 -#define nbif_gpu_A2S_CNTL_CL2__NSNOOP_MAP_MASK 0x00000003L -#define nbif_gpu_A2S_CNTL_CL2__REQPASSPW_VC0_MAP_MASK 0x0000000cL -#define nbif_gpu_A2S_CNTL_CL2__REQPASSPW_NVC0_MAP_MASK 0x00000030L -#define nbif_gpu_A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP_MASK 0x000000c0L -#define nbif_gpu_A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L -#define nbif_gpu_A2S_CNTL_CL2__BLKLVL_MAP_MASK 0x00000c00L -#define nbif_gpu_A2S_CNTL_CL2__DATERR_MAP_MASK 0x00003000L -#define nbif_gpu_A2S_CNTL_CL2__EXOKAY_WR_MAP_MASK 0x0000c000L -#define nbif_gpu_A2S_CNTL_CL2__EXOKAY_RD_MAP_MASK 0x00030000L -#define nbif_gpu_A2S_CNTL_CL2__RESP_WR_MAP_MASK 0x000c0000L -#define nbif_gpu_A2S_CNTL_CL2__RESP_RD_MAP_MASK 0x00300000L - -// nbif_gpu_A2S_CNTL_CL3 -#define nbif_gpu_A2S_CNTL_CL3__NSNOOP_MAP_MASK 0x00000003L -#define nbif_gpu_A2S_CNTL_CL3__REQPASSPW_VC0_MAP_MASK 0x0000000cL -#define nbif_gpu_A2S_CNTL_CL3__REQPASSPW_NVC0_MAP_MASK 0x00000030L -#define nbif_gpu_A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP_MASK 0x000000c0L -#define nbif_gpu_A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L -#define nbif_gpu_A2S_CNTL_CL3__BLKLVL_MAP_MASK 0x00000c00L -#define nbif_gpu_A2S_CNTL_CL3__DATERR_MAP_MASK 0x00003000L -#define nbif_gpu_A2S_CNTL_CL3__EXOKAY_WR_MAP_MASK 0x0000c000L -#define nbif_gpu_A2S_CNTL_CL3__EXOKAY_RD_MAP_MASK 0x00030000L -#define nbif_gpu_A2S_CNTL_CL3__RESP_WR_MAP_MASK 0x000c0000L -#define nbif_gpu_A2S_CNTL_CL3__RESP_RD_MAP_MASK 0x00300000L - -// nbif_gpu_A2S_CNTL_CL4 -#define nbif_gpu_A2S_CNTL_CL4__NSNOOP_MAP_MASK 0x00000003L -#define nbif_gpu_A2S_CNTL_CL4__REQPASSPW_VC0_MAP_MASK 0x0000000cL -#define nbif_gpu_A2S_CNTL_CL4__REQPASSPW_NVC0_MAP_MASK 0x00000030L -#define nbif_gpu_A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP_MASK 0x000000c0L -#define nbif_gpu_A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L -#define nbif_gpu_A2S_CNTL_CL4__BLKLVL_MAP_MASK 0x00000c00L -#define nbif_gpu_A2S_CNTL_CL4__DATERR_MAP_MASK 0x00003000L -#define nbif_gpu_A2S_CNTL_CL4__EXOKAY_WR_MAP_MASK 0x0000c000L -#define nbif_gpu_A2S_CNTL_CL4__EXOKAY_RD_MAP_MASK 0x00030000L -#define nbif_gpu_A2S_CNTL_CL4__RESP_WR_MAP_MASK 0x000c0000L -#define nbif_gpu_A2S_CNTL_CL4__RESP_RD_MAP_MASK 0x00300000L - -// nbif_gpu_A2S_CNTL_SW0 -#define nbif_gpu_A2S_CNTL_SW0__WR_TAG_SET_MIN_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL_SW0__RD_TAG_SET_MIN_MASK 0x00000038L -#define nbif_gpu_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK 0x00000040L -#define nbif_gpu_A2S_CNTL_SW0__RSP_REORDER_DIS_MASK 0x00000080L -#define nbif_gpu_A2S_CNTL_SW0__WRRSP_ACCUM_SEL_MASK 0x00000100L -#define nbif_gpu_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L -#define nbif_gpu_A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000400L -#define nbif_gpu_A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000800L -#define nbif_gpu_A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00001000L -#define nbif_gpu_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00ff0000L -#define nbif_gpu_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xff000000L - -// nbif_gpu_A2S_CNTL_SW1 -#define nbif_gpu_A2S_CNTL_SW1__WR_TAG_SET_MIN_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL_SW1__RD_TAG_SET_MIN_MASK 0x00000038L -#define nbif_gpu_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK 0x00000040L -#define nbif_gpu_A2S_CNTL_SW1__RSP_REORDER_DIS_MASK 0x00000080L -#define nbif_gpu_A2S_CNTL_SW1__WRRSP_ACCUM_SEL_MASK 0x00000100L -#define nbif_gpu_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L -#define nbif_gpu_A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000400L -#define nbif_gpu_A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000800L -#define nbif_gpu_A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00001000L -#define nbif_gpu_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00ff0000L -#define nbif_gpu_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xff000000L - -// nbif_gpu_A2S_CNTL_SW2 -#define nbif_gpu_A2S_CNTL_SW2__WR_TAG_SET_MIN_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL_SW2__RD_TAG_SET_MIN_MASK 0x00000038L -#define nbif_gpu_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK 0x00000040L -#define nbif_gpu_A2S_CNTL_SW2__RSP_REORDER_DIS_MASK 0x00000080L -#define nbif_gpu_A2S_CNTL_SW2__WRRSP_ACCUM_SEL_MASK 0x00000100L -#define nbif_gpu_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L -#define nbif_gpu_A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000400L -#define nbif_gpu_A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000800L -#define nbif_gpu_A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00001000L -#define nbif_gpu_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00ff0000L -#define nbif_gpu_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xff000000L - -// nbif_gpu_A2S_CNTL2_SEC_CL0 -#define nbif_gpu_A2S_CNTL2_SEC_CL0__SECLVL_MAP_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL2_SEC_CL0__DBGMSK_MAP_MASK 0x00000008L - -// nbif_gpu_A2S_CNTL2_SEC_CL1 -#define nbif_gpu_A2S_CNTL2_SEC_CL1__SECLVL_MAP_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL2_SEC_CL1__DBGMSK_MAP_MASK 0x00000008L - -// nbif_gpu_A2S_CNTL2_SEC_CL2 -#define nbif_gpu_A2S_CNTL2_SEC_CL2__SECLVL_MAP_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL2_SEC_CL2__DBGMSK_MAP_MASK 0x00000008L - -// nbif_gpu_A2S_CNTL2_SEC_CL3 -#define nbif_gpu_A2S_CNTL2_SEC_CL3__SECLVL_MAP_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL2_SEC_CL3__DBGMSK_MAP_MASK 0x00000008L - -// nbif_gpu_A2S_CNTL2_SEC_CL4 -#define nbif_gpu_A2S_CNTL2_SEC_CL4__SECLVL_MAP_MASK 0x00000007L -#define nbif_gpu_A2S_CNTL2_SEC_CL4__DBGMSK_MAP_MASK 0x00000008L - -// nbif_gpu_NGDC_MGCG_CTRL -#define nbif_gpu_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L -#define nbif_gpu_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L -#define nbif_gpu_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003fcL - -// nbif_gpu_A2S_MISC_CNTL -#define nbif_gpu_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L -#define nbif_gpu_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L - -// nbif_gpu_NGDC_SDP_PORT_CTRL -#define nbif_gpu_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003fL - -// nbif_gpu_BIF_SDMA0_DOORBELL_RANGE -#define nbif_gpu_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000ffcL -#define nbif_gpu_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001f0000L - -// nbif_gpu_BIF_SDMA1_DOORBELL_RANGE -#define nbif_gpu_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000ffcL -#define nbif_gpu_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001f0000L - -// nbif_gpu_BIF_IH_DOORBELL_RANGE -#define nbif_gpu_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000ffcL -#define nbif_gpu_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001f0000L - -// nbif_gpu_BIF_MMSCH0_DOORBELL_RANGE -#define nbif_gpu_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000ffcL -#define nbif_gpu_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001f0000L - -// nbif_gpu_S2A_MISC_CNTL -#define nbif_gpu_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L -#define nbif_gpu_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L -#define nbif_gpu_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L - -// nbif_gpu_GDC_RAS_LEAF0_CTRL -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_GDC_RAS_LEAF1_CTRL -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_GDC_RAS_LEAF2_CTRL -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_GDC_RAS_LEAF3_CTRL -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_GDC_RAS_LEAF4_CTRL -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_GDC_RAS_LEAF5_CTRL -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_DET_EN_MASK 0x00000001L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK 0x00000004L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_DET_EN_MASK 0x00000010L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK 0x00000040L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV_MASK 0x00010000L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV_MASK 0x00020000L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_ERR_DET_MASK 0x00040000L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET_MASK 0x00080000L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT_MASK 0x00100000L -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__EGRESS_STALLED_MASK 0x00200000L - -// nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xffffffffL - -// nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xffffffffL - -// nbif_gpu_SION_CNTL_REG0 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L - -// nbif_gpu_SION_CNTL_REG1 -#define nbif_gpu_SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000ffL -#define nbif_gpu_SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000ff00L - -// nbif_gpu_RCC_BIF_STRAP0 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_GEN3_DIS_PIN_MASK 0x00000001L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK 0x00000002L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_GPUIOV_SEC_LVL_OVRD_EN_MASK 0x10000000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L - -// nbif_gpu_RCC_BIF_STRAP1 -#define nbif_gpu_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L -#define nbif_gpu_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L -#define nbif_gpu_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK 0x00000010L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000c00L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_GPUIOV_SEC_LVL_OVRD_VAL_MASK 0x00380000L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L - -// nbif_gpu_RCC_BIF_STRAP2 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SATA_DID_RAID_EN_0_MASK 0x00000002L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SATA_DID_RAID_EN_1_MASK 0x00000004L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_PCIE_SEC_LVL_OVRD_EN_MASK 0x00000080L -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_PCIE_SEC_LVL_OVRD_VAL_MASK 0x00000700L -#define nbif_gpu_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00003800L -#define nbif_gpu_RCC_BIF_STRAP2__RESERVED2_BIF_STRAP2_MASK 0x0001c000L - -// nbif_gpu_RCC_BIF_STRAP3 -#define nbif_gpu_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000ffffL -#define nbif_gpu_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xffff0000L - -// nbif_gpu_RCC_BIF_STRAP4 -#define nbif_gpu_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000ffffL -#define nbif_gpu_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xffff0000L - -// nbif_gpu_RCC_BIF_STRAP5 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000ffffL -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L - -// nbif_gpu_RCC_BIF_STRAP6 -#define nbif_gpu_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK 0xffffffffL - -// nbif_gpu_RCC_DEV0_PORT_STRAP0 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001fffe0L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00e00000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0e000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_PORT_STRAP1 -#define nbif_gpu_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xffff0000L - -// nbif_gpu_RCC_DEV0_PORT_STRAP2 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000e00L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00060000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1c000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xe0000000L - -// nbif_gpu_RCC_DEV0_PORT_STRAP3 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK \ - 0x00003800L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK \ - 0x0003c000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK \ - 0x001c0000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK \ - 0x01e00000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_PORT_STRAP4 -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00ff0000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xff000000L - -// nbif_gpu_RCC_DEV0_PORT_STRAP5 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_PORT_STRAP6 -#define nbif_gpu_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L - -// nbif_gpu_RCC_DEV0_PORT_STRAP7 -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000f00L -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000f000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00ff0000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1f000000L -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xe0000000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0f000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP1 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xffff0000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003eL -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003e00L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK \ - 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00e00000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0_MASK 0x000fffffL -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000ffffL - -// nbif_gpu_RCC_DEV0_EPF0_STRAP8 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000006L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00000010L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00000060L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00000e00L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x00003000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x0000c000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00380000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x00c00000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xc0000000L - -// nbif_gpu_RCC_DEV0_EPF0_STRAP9 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP9__STRAP_SECURE_ID_DEV0_F0_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF0_STRAP9__STRAP_SECURE_LVL_DEV0_F0_MASK 0x00030000L - -// nbif_gpu_RCC_DEV0_EPF1_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF1_STRAP10 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK 0x001ffffeL - -// nbif_gpu_RCC_DEV0_EPF1_STRAP11 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK 0x001ffffeL - -// nbif_gpu_RCC_DEV0_EPF1_STRAP12 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK 0x001ffffeL - -// nbif_gpu_RCC_DEV0_EPF1_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF1_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L - -// nbif_gpu_RCC_DEV0_EPF1_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF1_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF1_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000ffffL - -// nbif_gpu_RCC_DEV0_EPF1_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK 0x00000070L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L - -// nbif_gpu_RCC_DEV0_EPF1_STRAP7 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK 0x0000001eL - -// nbif_gpu_RCC_DEV1_PORT_STRAP0 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1_MASK 0x00000004L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1_MASK 0x00000008L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1_MASK 0x00000010L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1_MASK 0x001fffe0L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1_MASK 0x00e00000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_MASK 0x01000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_MASK 0x0e000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_MASK 0x70000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_PORT_STRAP1 -#define nbif_gpu_RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1_MASK 0xffff0000L - -// nbif_gpu_RCC_DEV1_PORT_STRAP2 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1_MASK 0x00000004L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1_MASK 0x00000008L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1_MASK 0x00000010L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1_MASK 0x00000020L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1_MASK 0x00000040L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1_MASK 0x00000080L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1_MASK 0x00000100L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1_MASK 0x00000e00L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_MASK 0x00001000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_MASK 0x00002000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1_MASK 0x00004000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1_MASK 0x00008000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1_MASK 0x00010000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1_MASK 0x00060000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1_MASK 0x00080000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_MASK 0x00700000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1_MASK 0x03800000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1_MASK 0x1c000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1_MASK 0xe0000000L - -// nbif_gpu_RCC_DEV1_PORT_STRAP3 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1_MASK 0x00000004L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1_MASK 0x00000038L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1_MASK 0x00000040L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1_MASK 0x00000080L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1_MASK 0x00000100L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1_MASK 0x00000600L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK \ - 0x00003800L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_MASK \ - 0x0003c000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK \ - 0x001c0000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_MASK \ - 0x01e00000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1_MASK 0x06000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1_MASK 0x18000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1_MASK 0x20000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1_MASK 0x40000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_PORT_STRAP4 -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_MASK 0x00ff0000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_MASK 0xff000000L - -// nbif_gpu_RCC_DEV1_PORT_STRAP5 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_MASK 0x00010000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1_MASK 0x00020000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1_MASK 0x00040000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1_MASK 0x00080000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1_MASK 0x00200000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_MASK 0x00800000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_MASK 0x01000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_MASK 0x02000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_MASK 0x04000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_MASK 0x08000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_MASK 0x10000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_MASK 0x20000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1_MASK 0x40000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_PORT_STRAP6 -#define nbif_gpu_RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_MASK 0x00000002L - -// nbif_gpu_RCC_DEV1_PORT_STRAP7 -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1_MASK 0x00000f00L -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1_MASK 0x0000f000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1_MASK 0x00ff0000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1_MASK 0x1f000000L -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1_MASK 0xe0000000L - -// nbif_gpu_RCC_DEV0_EPF2_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF2_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF2_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK 0x07000000L - -// nbif_gpu_RCC_DEV0_EPF2_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF2_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF2_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2_MASK 0x01000000L - -// nbif_gpu_RCC_DEV0_EPF2_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2_MASK 0x00000070L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2_MASK 0x00000200L - -// nbif_gpu_RCC_DEV0_EPF3_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF3_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF3_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK 0x07000000L - -// nbif_gpu_RCC_DEV0_EPF3_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF3_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF3_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3_MASK 0x00f00000L - -// nbif_gpu_RCC_DEV0_EPF3_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3_MASK 0x00000070L - -// nbif_gpu_RCC_DEV0_EPF4_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF4_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF4_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4_MASK 0x07000000L - -// nbif_gpu_RCC_DEV0_EPF4_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF4_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF4_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4_MASK 0x00f00000L - -// nbif_gpu_RCC_DEV0_EPF4_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4_MASK 0x00000070L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4_MASK 0x00000200L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4_MASK 0x00020000L - -// nbif_gpu_RCC_DEV0_EPF5_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF5_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF5_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5_MASK 0x07000000L - -// nbif_gpu_RCC_DEV0_EPF5_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF5_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF5_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5_MASK 0x0000ffffL - -// nbif_gpu_RCC_DEV0_EPF5_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5_MASK 0x00000070L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5_MASK 0x00000200L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5_MASK 0x00020000L - -// nbif_gpu_RCC_DEV0_EPF6_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF6_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF6_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6_MASK 0x07000000L - -// nbif_gpu_RCC_DEV0_EPF6_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF6_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF6_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6_MASK 0x0000ffffL - -// nbif_gpu_RCC_DEV0_EPF6_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6_MASK 0x00000070L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6_MASK 0x00000200L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6_MASK 0x00020000L - -// nbif_gpu_RCC_DEV0_EPF7_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7_MASK 0x10000000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7_MASK 0x20000000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7_MASK 0x40000000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF7_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV0_EPF7_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7_MASK 0x00000080L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7_MASK 0x00004000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7_MASK 0x00020000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7_MASK 0x00800000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7_MASK 0x07000000L - -// nbif_gpu_RCC_DEV0_EPF7_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7_MASK 0x00040000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7_MASK 0x00080000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7_MASK 0x01000000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7_MASK 0x02000000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7_MASK 0x04000000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7_MASK 0x08000000L - -// nbif_gpu_RCC_DEV0_EPF7_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7_MASK 0x00100000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7_MASK 0x00200000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7_MASK 0x00400000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7_MASK 0x70000000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7_MASK 0x80000000L - -// nbif_gpu_RCC_DEV0_EPF7_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7_MASK 0x0000ffffL - -// nbif_gpu_RCC_DEV0_EPF7_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7_MASK 0x00000001L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7_MASK 0x00000002L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7_MASK 0x00000070L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7_MASK 0x00000100L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7_MASK 0x00000200L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7_MASK 0x00010000L -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7_MASK 0x00020000L - -// nbif_gpu_RCC_DEV1_EPF0_STRAP0 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0_MASK 0x10000000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_MASK 0x20000000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0_MASK 0x40000000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_EPF0_STRAP13 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV1_EPF0_STRAP2 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0_MASK 0x00000080L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0_MASK 0x00000100L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_MASK 0x00004000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0_MASK 0x00008000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0_MASK 0x00010000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0_MASK 0x00020000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0_MASK 0x00200000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0_MASK 0x00800000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0_MASK 0x07000000L - -// nbif_gpu_RCC_DEV1_EPF0_STRAP3 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0_MASK 0x00040000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0_MASK 0x00080000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0_MASK 0x01000000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0_MASK 0x02000000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_MASK 0x04000000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_MASK 0x08000000L - -// nbif_gpu_RCC_DEV1_EPF0_STRAP4 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0_MASK 0x00200000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0_MASK 0x00400000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0_MASK 0x70000000L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_EPF0_STRAP5 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0_MASK 0x01000000L - -// nbif_gpu_RCC_DEV1_EPF0_STRAP6 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0_MASK 0x00000070L - -// nbif_gpu_RCC_DEV1_EPF1_STRAP0 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1_MASK 0x10000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1_MASK 0x20000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1_MASK 0x40000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_EPF1_STRAP13 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV1_EPF1_STRAP2 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1_MASK 0x00000080L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1_MASK 0x00000100L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1_MASK 0x00004000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1_MASK 0x00010000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1_MASK 0x00020000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1_MASK 0x00200000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1_MASK 0x00800000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1_MASK 0x07000000L - -// nbif_gpu_RCC_DEV1_EPF1_STRAP3 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1_MASK 0x00040000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1_MASK 0x00080000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1_MASK 0x01000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1_MASK 0x02000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1_MASK 0x04000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1_MASK 0x08000000L - -// nbif_gpu_RCC_DEV1_EPF1_STRAP4 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1_MASK 0x00200000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1_MASK 0x00400000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1_MASK 0x70000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_EPF1_STRAP5 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1_MASK 0x0000ffffL - -// nbif_gpu_RCC_DEV1_EPF1_STRAP6 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1_MASK 0x00000070L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1_MASK 0x00000100L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1_MASK 0x00000200L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1_MASK 0x00010000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1_MASK 0x00020000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1_MASK 0x01000000L -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1_MASK 0x02000000L - -// nbif_gpu_RCC_DEV1_EPF2_STRAP0 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2_MASK 0x0000ffffL -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2_MASK 0x000f0000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2_MASK 0x00f00000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2_MASK 0x10000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2_MASK 0x20000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2_MASK 0x40000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_EPF2_STRAP13 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2_MASK 0x000000ffL -#define nbif_gpu_RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2_MASK 0x0000ff00L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2_MASK 0x00ff0000L - -// nbif_gpu_RCC_DEV1_EPF2_STRAP2 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2_MASK 0x00000080L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2_MASK 0x00000100L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2_MASK 0x00004000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2_MASK 0x00010000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2_MASK 0x00020000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2_MASK 0x00200000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2_MASK 0x00800000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2_MASK 0x07000000L - -// nbif_gpu_RCC_DEV1_EPF2_STRAP3 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2_MASK 0x0003fffcL -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2_MASK 0x00040000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2_MASK 0x00080000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2_MASK 0x01000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2_MASK 0x02000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2_MASK 0x04000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2_MASK 0x08000000L - -// nbif_gpu_RCC_DEV1_EPF2_STRAP4 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2_MASK 0x00100000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2_MASK 0x00200000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2_MASK 0x00400000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2_MASK 0x0f800000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2_MASK 0x70000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2_MASK 0x80000000L - -// nbif_gpu_RCC_DEV1_EPF2_STRAP5 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2_MASK 0x0000ffffL - -// nbif_gpu_RCC_DEV1_EPF2_STRAP6 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2_MASK 0x00000001L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2_MASK 0x00000002L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2_MASK 0x00000070L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2_MASK 0x00000100L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2_MASK 0x00000200L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2_MASK 0x00010000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2_MASK 0x00020000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2_MASK 0x01000000L -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2_MASK 0x02000000L - -// nbif_gpu_SHUB_PF_FLR_RST -#define nbif_gpu_SHUB_PF_FLR_RST__PF0_FLR_RST_MASK 0x00000001L -#define nbif_gpu_SHUB_PF_FLR_RST__PF1_FLR_RST_MASK 0x00000002L -#define nbif_gpu_SHUB_PF_FLR_RST__PF2_FLR_RST_MASK 0x00000004L -#define nbif_gpu_SHUB_PF_FLR_RST__PF3_FLR_RST_MASK 0x00000008L -#define nbif_gpu_SHUB_PF_FLR_RST__PF4_FLR_RST_MASK 0x00000010L -#define nbif_gpu_SHUB_PF_FLR_RST__PF5_FLR_RST_MASK 0x00000020L -#define nbif_gpu_SHUB_PF_FLR_RST__PF6_FLR_RST_MASK 0x00000040L -#define nbif_gpu_SHUB_PF_FLR_RST__PF7_FLR_RST_MASK 0x00000080L - -// nbif_gpu_SHUB_GFX_DRV_MODE1_RST -#define nbif_gpu_SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L - -// nbif_gpu_SHUB_LINK_RESET -#define nbif_gpu_SHUB_LINK_RESET__LINK_RESET_MASK 0x00000001L - -// nbif_gpu_SHUB_PF0_VF_FLR_RST -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L - -// nbif_gpu_SHUB_HARD_RST_CTRL -#define nbif_gpu_SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L -#define nbif_gpu_SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L -#define nbif_gpu_SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L -#define nbif_gpu_SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L -#define nbif_gpu_SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L - -// nbif_gpu_SHUB_SOFT_RST_CTRL -#define nbif_gpu_SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L -#define nbif_gpu_SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L -#define nbif_gpu_SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L -#define nbif_gpu_SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L -#define nbif_gpu_SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L - -// nbif_gpu_SHUB_SDP_PORT_RST -#define nbif_gpu_SHUB_SDP_PORT_RST__SDP_PORT_RST_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT0_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT1_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT2_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT3_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT4_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT5_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT6_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT7_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT8_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT9_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT10_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT11_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT12_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT13_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT14_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT15_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT16_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT17_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT18_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT19_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT20_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT21_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT22_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT23_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT24_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT25_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT26_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT27_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT28_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT29_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT30_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT31_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffcL - -// nbif_gpu_PCIEMSIX_VECT0_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT1_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT2_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT3_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT4_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT5_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT6_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT7_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT8_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT9_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT10_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT11_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT12_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT13_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT14_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT15_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT16_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT17_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT18_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT19_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT20_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT21_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT22_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT23_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT24_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT25_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT26_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT27_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT28_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT29_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT30_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT31_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT0_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT1_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT2_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT3_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT4_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT5_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT6_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT7_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT8_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT9_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT10_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT11_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT12_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT13_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT14_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT15_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT16_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT17_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT18_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT19_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT20_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT21_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT22_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT23_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT24_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT25_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT26_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT27_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT28_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT29_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT30_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT31_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xffffffffL - -// nbif_gpu_PCIEMSIX_VECT0_CONTROL -#define nbif_gpu_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT1_CONTROL -#define nbif_gpu_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT2_CONTROL -#define nbif_gpu_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT3_CONTROL -#define nbif_gpu_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT4_CONTROL -#define nbif_gpu_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT5_CONTROL -#define nbif_gpu_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT6_CONTROL -#define nbif_gpu_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT7_CONTROL -#define nbif_gpu_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT8_CONTROL -#define nbif_gpu_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT9_CONTROL -#define nbif_gpu_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT10_CONTROL -#define nbif_gpu_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT11_CONTROL -#define nbif_gpu_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT12_CONTROL -#define nbif_gpu_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT13_CONTROL -#define nbif_gpu_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT14_CONTROL -#define nbif_gpu_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT15_CONTROL -#define nbif_gpu_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT16_CONTROL -#define nbif_gpu_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT17_CONTROL -#define nbif_gpu_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT18_CONTROL -#define nbif_gpu_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT19_CONTROL -#define nbif_gpu_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT20_CONTROL -#define nbif_gpu_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT21_CONTROL -#define nbif_gpu_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT22_CONTROL -#define nbif_gpu_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT23_CONTROL -#define nbif_gpu_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT24_CONTROL -#define nbif_gpu_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT25_CONTROL -#define nbif_gpu_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT26_CONTROL -#define nbif_gpu_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT27_CONTROL -#define nbif_gpu_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT28_CONTROL -#define nbif_gpu_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT29_CONTROL -#define nbif_gpu_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT30_CONTROL -#define nbif_gpu_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_VECT31_CONTROL -#define nbif_gpu_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L - -// nbif_gpu_PCIEMSIX_PBA -#define nbif_gpu_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xffffffffL - -// nbif_gpu_RCC_PFC_LTR_CNTL -#define nbif_gpu_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003ffL -#define nbif_gpu_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001c00L -#define nbif_gpu_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L -#define nbif_gpu_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03ff0000L -#define nbif_gpu_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1c000000L -#define nbif_gpu_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L - -// nbif_gpu_RCC_PFC_PME_RESTORE -#define nbif_gpu_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L -#define nbif_gpu_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_0 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_1 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xffffffffL - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_2 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xffffffffL - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_3 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xffffffffL - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_4 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xffffffffL - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_5 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xffffffffL - -// nbif_gpu_RCC_PFC_AUXPWR_CNTL -#define nbif_gpu_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L -#define nbif_gpu_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L - -// IH_VMID_0_LUT -#define IH_VMID_0_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_1_LUT -#define IH_VMID_1_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_2_LUT -#define IH_VMID_2_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_3_LUT -#define IH_VMID_3_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_4_LUT -#define IH_VMID_4_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_5_LUT -#define IH_VMID_5_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_6_LUT -#define IH_VMID_6_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_7_LUT -#define IH_VMID_7_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_8_LUT -#define IH_VMID_8_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_9_LUT -#define IH_VMID_9_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_10_LUT -#define IH_VMID_10_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_11_LUT -#define IH_VMID_11_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_12_LUT -#define IH_VMID_12_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_13_LUT -#define IH_VMID_13_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_14_LUT -#define IH_VMID_14_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_15_LUT -#define IH_VMID_15_LUT__PASID_MASK 0x0000ffffL - -// IH_VMID_0_LUT_MM -#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_1_LUT_MM -#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_2_LUT_MM -#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_3_LUT_MM -#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_4_LUT_MM -#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_5_LUT_MM -#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_6_LUT_MM -#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_7_LUT_MM -#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_8_LUT_MM -#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_9_LUT_MM -#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_10_LUT_MM -#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_11_LUT_MM -#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_12_LUT_MM -#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_13_LUT_MM -#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_14_LUT_MM -#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_VMID_15_LUT_MM -#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000ffffL - -// IH_COOKIE_0 -#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000ffL -#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000ff00L -#define IH_COOKIE_0__RING_ID_MASK 0x00ff0000L -#define IH_COOKIE_0__VM_ID_MASK 0x0f000000L -#define IH_COOKIE_0__RESERVED_MASK 0x70000000L -#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L - -// IH_COOKIE_1 -#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xffffffffL - -// IH_COOKIE_2 -#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000ffffL -#define IH_COOKIE_2__RESERVED_MASK 0x7fff0000L -#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L - -// IH_COOKIE_3 -#define IH_COOKIE_3__PAS_ID_MASK 0x0000ffffL -#define IH_COOKIE_3__RESERVED_MASK 0x7fff0000L -#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L - -// IH_COOKIE_4 -#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xffffffffL - -// IH_COOKIE_5 -#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xffffffffL - -// IH_COOKIE_6 -#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xffffffffL - -// IH_COOKIE_7 -#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xffffffffL - -// IH_REGISTER_LAST_PART0 -#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xffffffffL - -// IH_RB_CNTL -#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL -#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L -#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L -#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L -#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L -#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000f000L -#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L -#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L -#define IH_RB_CNTL__MC_SWAP_MASK 0x000c0000L -#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L -#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L -#define IH_RB_CNTL__MC_RO_MASK 0x00400000L -#define IH_RB_CNTL__MC_VMID_MASK 0x0f000000L -#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L - -// IH_RB_BASE -#define IH_RB_BASE__ADDR_MASK 0xffffffffL - -// IH_RB_BASE_HI -#define IH_RB_BASE_HI__ADDR_MASK 0x000000ffL - -// IH_RB_RPTR -#define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL - -// IH_RB_WPTR -#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L -#define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL -#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L -#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L - -// IH_RB_WPTR_ADDR_HI -#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000ffffL - -// IH_RB_WPTR_ADDR_LO -#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// IH_DOORBELL_RPTR -#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03ffffffL -#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L - -// IH_RB_CNTL_RING1 -#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L -#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003eL -#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L -#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L -#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L -#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000f000L -#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L -#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000c0000L -#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L -#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L -#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0f000000L -#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L -#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L - -// IH_RB_BASE_RING1 -#define IH_RB_BASE_RING1__ADDR_MASK 0xffffffffL - -// IH_RB_BASE_HI_RING1 -#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000ffL - -// IH_RB_RPTR_RING1 -#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003fffcL - -// IH_RB_WPTR_RING1 -#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L -#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003fffcL -#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L -#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L - -// IH_DOORBELL_RPTR_RING1 -#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03ffffffL -#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L - -// IH_RB_CNTL_RING2 -#define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L -#define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003eL -#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L -#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L -#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L -#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000f000L -#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L -#define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000c0000L -#define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L -#define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L -#define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0f000000L -#define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L -#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L - -// IH_RB_BASE_RING2 -#define IH_RB_BASE_RING2__ADDR_MASK 0xffffffffL - -// IH_RB_BASE_HI_RING2 -#define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000ffL - -// IH_RB_RPTR_RING2 -#define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003fffcL - -// IH_RB_WPTR_RING2 -#define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L -#define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003fffcL -#define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L -#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L - -// IH_DOORBELL_RPTR_RING2 -#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03ffffffL -#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L - -// IH_VERSION -#define IH_VERSION__MINVER_MASK 0x0000007fL -#define IH_VERSION__MAJVER_MASK 0x00007f00L -#define IH_VERSION__REV_MASK 0x003f0000L - -// IH_CNTL -#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001fL -#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000c0L -#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007f00L -#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L - -// IH_CNTL2 -#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x000000ffL -#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L - -// IH_STATUS -#define IH_STATUS__IDLE_MASK 0x00000001L -#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L -#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L -#define IH_STATUS__RB_FULL_MASK 0x00000008L -#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L -#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L -#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L -#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L -#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L -#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L -#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L -#define IH_STATUS__SWITCH_READY_MASK 0x00000800L -#define IH_STATUS__RB1_FULL_MASK 0x00001000L -#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L -#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L -#define IH_STATUS__RB2_FULL_MASK 0x00008000L -#define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L -#define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L -#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L - -// IH_PERFMON_CNTL -#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L -#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L -#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000007fcL -#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L -#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L -#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x07fc0000L - -// IH_PERFCOUNTER0_RESULT -#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL - -// IH_PERFCOUNTER1_RESULT -#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL - -// IH_DEBUG -#define IH_DEBUG__DBG_SEL_VF_MASK 0x00000008L -#define IH_DEBUG__DBG_SEL_VFID_MASK 0x000000f0L -#define IH_DEBUG__DBG_SEL_IH_RING_ID_MASK 0x00003000L - -// IH_DSM_MATCH_VALUE_BIT_31_0 -#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffffL - -// IH_DSM_MATCH_VALUE_BIT_63_32 -#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffffL - -// IH_DSM_MATCH_VALUE_BIT_95_64 -#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffffL - -// IH_DSM_MATCH_FIELD_CONTROL -#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L -#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L -#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L -#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L -#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L -#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L -#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L - -// IH_DSM_MATCH_DATA_CONTROL -#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0fffffffL - -// IH_DSM_MATCH_FCN_ID -#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L -#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001eL - -// IH_LIMIT_INT_RATE_CNTL -#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L -#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001eL -#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000ffe0L -#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001e0000L -#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xffe00000L - -// IH_VF_RB_STATUS -#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000ffffL -#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000L - -// IH_VF_RB_STATUS2 -#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000ffffL -#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0xffff0000L - -// IH_VF_RB1_STATUS -#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000ffffL -#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000L - -// IH_VF_RB1_STATUS2 -#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000ffffL - -// IH_VF_RB2_STATUS -#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000ffffL -#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000L - -// IH_VF_RB2_STATUS2 -#define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x0000ffffL - -// IH_INT_FLOOD_CNTL -#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L -#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L -#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L - -// IH_RB0_INT_FLOOD_STATUS -#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000ffffL -#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L - -// IH_RB1_INT_FLOOD_STATUS -#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000ffffL -#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L - -// IH_RB2_INT_FLOOD_STATUS -#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000ffffL -#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L - -// IH_INT_FLOOD_STATUS -#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000ffL -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000ff00L -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00ff0000L -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0f000000L -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L -#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L - -// IH_STORM_CLIENT_LIST_CNTL -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L - -// IH_CLK_CTRL -#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L -#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L -#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L -#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L -#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L - -// IH_INT_FLAGS -#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L -#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L -#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L -#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L -#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L -#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L -#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L -#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L -#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L -#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L -#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L -#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L -#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L -#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L -#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L -#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L -#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L -#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L -#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L -#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L -#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L -#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L -#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L -#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L -#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L -#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L -#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L -#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L -#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L -#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L -#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L -#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L - -// IH_LAST_INT_INFO0 -#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000ffL -#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000ff00L -#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00ff0000L -#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0f000000L - -// IH_LAST_INT_INFO1 -#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xffffffffL - -// IH_LAST_INT_INFO2 -#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000ffffL -#define IH_LAST_INT_INFO2__VF_ID_MASK 0x000f0000L -#define IH_LAST_INT_INFO2__VF_MASK 0x00100000L - -// IH_SCRATCH -#define IH_SCRATCH__DATA_MASK 0xffffffffL - -// IH_CLIENT_CREDIT_ERROR -#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L -#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L - -// IH_GPU_IOV_VIOLATION_LOG -#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003fffcL -#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L -#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00f00000L -#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xff000000L - -// IH_COOKIE_REC_VIOLATION_LOG -#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x00ff0000L -#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0xff000000L - -// IH_CREDIT_STATUS -#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L -#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L -#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L -#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L -#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L -#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L -#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L -#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L -#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L -#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L -#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L -#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L -#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L -#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L -#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L -#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L -#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L -#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L -#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L -#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L -#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L -#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L -#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L -#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L -#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L -#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L -#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L -#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L -#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L -#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L -#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L - -// IH_MMHUB_ERROR -#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L -#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L -#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L -#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L -#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L -#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L - -// IH_DEBUG_INDEX -#define IH_DEBUG_INDEX__INDEX_MASK 0x0000003fL - -// IH_DEBUG_DATA -#define IH_DEBUG_DATA__DATA_MASK 0x00ffffffL - -// IH_REGISTER_LAST_PART2 -#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xffffffffL - -// IH_ACTIVE_FCN_ID -#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000fL -#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0L -#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L - -// IH_VIRT_RESET_REQ -#define IH_VIRT_RESET_REQ__VF_MASK 0x0000ffffL -#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L - -// IH_CLIENT_CFG -#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001fL - -// IH_CLIENT_CFG_INDEX -#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001fL - -// IH_CLIENT_CFG_DATA -#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0001ffffL -#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000c0000L -#define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L -#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00c00000L -#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L - -// IH_CID_REMAP_INDEX -#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L - -// IH_CID_REMAP_DATA -#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000ffL -#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000ff00L -#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00ff0000L - -// IH_CHICKEN -#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L - -// IH_MMHUB_TLVL -#define IH_MMHUB_TLVL__IV_TLVL_MASK 0x00000007L -#define IH_MMHUB_TLVL__WPTR_WB_TLVL_MASK 0x00000070L - -// IH_REGISTER_LAST_PART1 -#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xffffffffL - -// SEM_REQ_INPUT_0 -#define SEM_REQ_INPUT_0__DATA_MASK 0xffffffffL - -// SEM_REQ_INPUT_1 -#define SEM_REQ_INPUT_1__DATA_MASK 0xffffffffL - -// SEM_REQ_INPUT_2 -#define SEM_REQ_INPUT_2__DATA_MASK 0xffffffffL - -// SEM_REQ_INPUT_3 -#define SEM_REQ_INPUT_3__DATA_MASK 0xffffffffL - -// SEM_REGISTER_LAST_PART0 -#define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xffffffffL - -// SEM_CLK_CTRL -#define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define SEM_CLK_CTRL__RESERVED_MASK 0x00fff000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SEM_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// SEM_UTC_CREDIT -#define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001fL -#define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000f00L - -// SEM_UTC_CONFIG -#define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L -#define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L -#define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L -#define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L - -// SEM_UTCL2_TRAN_EN_LUT -#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L -#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L -#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L -#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L -#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L -#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L -#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L -#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L -#define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7fffff00L -#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L - -// SEM_MCIF_CONFIG -#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L -#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000fcL -#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003f00L - -// SEM_PERFMON_CNTL -#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003fcL -#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000ff000L - -// SEM_PERFCOUNTER0_RESULT -#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL - -// SEM_PERFCOUNTER1_RESULT -#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL - -// SEM_STATUS -#define SEM_STATUS__SEM_IDLE_MASK 0x00000001L -#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L -#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L -#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L -#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L -#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L -#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L -#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L -#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L -#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L -#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L -#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L -#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L -#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L -#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L -#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L -#define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L -#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L -#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L -#define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L -#define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L -#define SEM_STATUS__MIF_IDLE_MASK 0x00200000L -#define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L -#define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L -#define SEM_STATUS__SWITCH_READY_MASK 0x80000000L - -// SEM_MAILBOX_CLIENTCONFIG -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L -#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L -#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L -#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001c0000L -#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00e00000L - -// SEM_MAILBOX -#define SEM_MAILBOX__HOSTPORT_MASK 0x0000ffffL -#define SEM_MAILBOX__RESERVED_MASK 0xffff0000L - -// SEM_MAILBOX_CONTROL -#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ffffL -#define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xffff0000L - -// SEM_CHICKEN_BITS -#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L -#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L -#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L -#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L -#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L -#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L -#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L -#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000c00L -#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L -#define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L -#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L -#define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L -#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L - -// SEM_MAILBOX_CLIENTCONFIG_EXTRA -#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000fL - -// SEM_GPU_IOV_VIOLATION_LOG -#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003fffcL -#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L -#define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00f00000L -#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xff000000L - -// SEM_OUTSTANDING_THRESHOLD -#define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000ffL - -// SEM_REGISTER_LAST_PART2 -#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xffffffffL - -// SEM_ACTIVE_FCN_ID -#define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000000fL -#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L - -// SEM_VIRT_RESET_REQ -#define SEM_VIRT_RESET_REQ__VF_MASK 0x0000ffffL -#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L - -// SEM_RESP_SDMA0 -#define SEM_RESP_SDMA0__ADDR_MASK 0x000ffffcL - -// SEM_RESP_SDMA1 -#define SEM_RESP_SDMA1__ADDR_MASK 0x000ffffcL - -// SEM_RESP_UVD -#define SEM_RESP_UVD__ADDR_MASK 0x000ffffcL - -// SEM_RESP_VCE_0 -#define SEM_RESP_VCE_0__ADDR_MASK 0x000ffffcL - -// SEM_RESP_ACP -#define SEM_RESP_ACP__ADDR_MASK 0x000ffffcL - -// SEM_RESP_ISP -#define SEM_RESP_ISP__ADDR_MASK 0x000ffffcL - -// SEM_RESP_VCE_1 -#define SEM_RESP_VCE_1__ADDR_MASK 0x000ffffcL - -// SEM_RESP_VP8 -#define SEM_RESP_VP8__ADDR_MASK 0x000ffffcL - -// SEM_RESP_GC -#define SEM_RESP_GC__ADDR_MASK 0x000ffffcL - -// SEM_CID_REMAP_INDEX -#define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L - -// SEM_CID_REMAP_DATA -#define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000ffL -#define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000ff00L -#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00ff0000L - -// SEM_ATOMIC_OP_LUT -#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007fL -#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003f80L -#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001fc000L -#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0fe00000L - -// SEM_EDC_CONFIG -#define SEM_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L -#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L - -// SEM_CHICKEN_BITS2 -#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L - -// SEM_MMHUB_TLVL -#define SEM_MMHUB_TLVL__VALUE_MASK 0x00000007L - -// SEM_REGISTER_LAST_PART1 -#define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xffffffffL - -// SDMA0_UCODE_ADDR -#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001fffL - -// SDMA0_UCODE_DATA -#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffffL - -// SDMA0_REGISTER_SECURITY_CNTL -#define SDMA0_REGISTER_SECURITY_CNTL__ENABLE_MASK 0x00000001L - -// SDMA0_VM_CNTL -#define SDMA0_VM_CNTL__CMD_MASK 0x0000000fL - -// SDMA0_VM_CTX_LO -#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_VM_CTX_HI -#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffffL - -// SDMA0_ACTIVE_FCN_ID -#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000fL -#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0L -#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L - -// SDMA0_VM_CTX_CNTL -#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000f0L - -// SDMA0_VIRT_RESET_REQ -#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000ffffL -#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L - -// SDMA0_CONTEXT_REG_TYPE0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY0_MASK 0x00100000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY1_MASK 0x00200000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY2_MASK 0x00400000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY3_MASK 0x00800000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY0_MASK 0x01000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY1_MASK 0x02000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY2_MASK 0x04000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY3_MASK 0x08000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA0_MASK 0x10000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA1_MASK 0x20000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA2_MASK 0x40000000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA3_MASK 0x80000000L - -// SDMA0_CONTEXT_REG_TYPE1 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_OFFSET_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD0_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD1_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD2_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD3_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD4_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_UNROLLKEY_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_AES_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xffc00000L - -// SDMA0_CONTEXT_REG_TYPE2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00L - -// SDMA0_CONTEXT_REG_TYPE3 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xffffffffL - -// SDMA0_PUB_REG_TYPE0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE0__SDMA0_REGISTER_SECURITY_CNTL_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01f80000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L - -// SDMA0_PUB_REG_TYPE1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L - -// SDMA0_PUB_REG_TYPE2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L - -// SDMA0_PUB_REG_TYPE3 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xfffffffcL - -// SDMA0_CONTEXT_GROUP_BOUNDARY -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xffffffffL - -// SDMA0_POWER_CNTL -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003ff000L - -// SDMA0_CLK_CTRL -#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00fff000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// SDMA0_CNTL -#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA0_CNTL__DRM_RESTORE_ENABLE_MASK 0x00080000L -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L - -// SDMA0_CHICKEN_BITS -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001c00L -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0c000000L -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000L - -// SDMA0_GB_ADDR_CONFIG -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L - -// SDMA0_GB_ADDR_CONFIG_READ -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L - -// SDMA0_RB_RPTR_FETCH_HI -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffffL - -// SDMA0_RB_RPTR_FETCH -#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffcL - -// SDMA0_IB_OFFSET_FETCH -#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003ffffcL - -// SDMA0_PROGRAM -#define SDMA0_PROGRAM__STREAM_MASK 0xffffffffL - -// SDMA0_STATUS_REG -#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA0_STATUS_REG__DRM_IDLE_MASK 0x00800000L -#define SDMA0_STATUS_REG__DRM_MASK_FULL_MASK 0x01000000L -#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L - -// SDMA0_STATUS1_REG -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA0_STATUS1_REG__CE_DRM_IDLE_MASK 0x00000080L -#define SDMA0_STATUS1_REG__CE_DRM1_IDLE_MASK 0x00000100L -#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA0_STATUS1_REG__CE_DRM_FULL_MASK 0x00000800L -#define SDMA0_STATUS1_REG__CE_DRM1_FULL_MASK 0x00001000L -#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA0_STATUS1_REG__DRM_CTX_RESTORE_MASK 0x00010000L -#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L - -// SDMA0_RD_BURST_CNTL -#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L - -// SDMA0_HBM_PAGE_CONFIG -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L - -// SDMA0_UCODE_CHECKSUM -#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xffffffffL - -// SDMA0_F32_CNTL -#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L -#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000fcL - -// SDMA0_FREEZE -#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L - -// SDMA0_PHASE0_QUANTUM -#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000fL -#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00ffff00L -#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L - -// SDMA0_PHASE1_QUANTUM -#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000fL -#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00ffff00L -#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L - -// SDMA_POWER_GATING -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L -#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L - -// SDMA_PGFSM_CONFIG -#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000ffL -#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L -#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L -#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L -#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L -#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L -#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L -#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000L - -// SDMA_PGFSM_WRITE -#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffffL - -// SDMA_PGFSM_READ -#define SDMA_PGFSM_READ__VALUE_MASK 0x00ffffffL - -// SDMA0_EDC_CONFIG -#define SDMA0_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L -#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L - -// SDMA0_BA_THRESHOLD -#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003ffL -#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03ff0000L - -// SDMA0_ID -#define SDMA0_ID__DEVICE_ID_MASK 0x000000ffL - -// SDMA0_VERSION -#define SDMA0_VERSION__MINVER_MASK 0x0000007fL -#define SDMA0_VERSION__MAJVER_MASK 0x00007f00L -#define SDMA0_VERSION__REV_MASK 0x003f0000L - -// SDMA0_EDC_COUNTER -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L - -// SDMA0_EDC_COUNTER_CLEAR -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L - -// SDMA0_STATUS2_REG -#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000ffcL -#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000L - -// SDMA0_ATOMIC_CNTL -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffffL -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L - -// SDMA0_ATOMIC_PREOP_LO -#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffffL - -// SDMA0_ATOMIC_PREOP_HI -#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffffL - -// SDMA0_UTCL1_CNTL -#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007feL -#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00ffc000L -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1f000000L -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xe0000000L - -// SDMA0_UTCL1_WATERMK -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003ffL -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003fc00L -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03fc0000L -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xfc000000L - -// SDMA0_UTCL1_RD_STATUS -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03c00000L -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000L -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L - -// SDMA0_UTCL1_WR_STATUS -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01c00000L -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0e000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L - -// SDMA0_UTCL1_INV0 -#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0ffff000L -#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xf0000000L - -// SDMA0_UTCL1_INV1 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xffffffffL - -// SDMA0_UTCL1_INV2 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffffffffL - -// SDMA0_UTCL1_RD_XNACK0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffffL - -// SDMA0_UTCL1_RD_XNACK1 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000fL -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000f0L -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03ffff00L -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0c000000L - -// SDMA0_UTCL1_WR_XNACK0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffffL - -// SDMA0_UTCL1_WR_XNACK1 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000fL -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000f0L -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03ffff00L -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0c000000L - -// SDMA0_UTCL1_TIMEOUT -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000ffffL -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000L - -// SDMA0_UTCL1_PAGE -#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001eL -#define SDMA0_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L -#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001c0L -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L - -// SDMA0_POWER_CNTL_IDLE -#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000ffffL -#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00ff0000L -#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000L - -// SDMA0_RELAX_ORDERING_LUT -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000c0L -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07ffc000L -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L - -// SDMA0_CHICKEN_BITS_2 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000fL - -// SDMA0_STATUS3_REG -#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000ffffL -#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000f0000L -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L - -// SDMA0_PHYSICAL_ADDR_LO -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xfffff000L - -// SDMA0_PHYSICAL_ADDR_HI -#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000ffffL - -// SDMA0_PHASE2_QUANTUM -#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000fL -#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00ffff00L -#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L - -// SDMA0_ERROR_LOG -#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000ffffL -#define SDMA0_ERROR_LOG__STATUS_MASK 0xffff0000L - -// SDMA0_PUB_DUMMY_REG0 -#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xffffffffL - -// SDMA0_PUB_DUMMY_REG1 -#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xffffffffL - -// SDMA0_PUB_DUMMY_REG2 -#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xffffffffL - -// SDMA0_PUB_DUMMY_REG3 -#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xffffffffL - -// SDMA0_F32_COUNTER -#define SDMA0_F32_COUNTER__VALUE_MASK 0xffffffffL - -// SDMA0_UNBREAKABLE -#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L - -// SDMA0_PERFMON_CNTL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003fcL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000ff000L - -// SDMA0_PERFCOUNTER0_RESULT -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL - -// SDMA0_PERFCOUNTER1_RESULT -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL - -// SDMA0_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003fffL -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0fffc000L -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L - -// SDMA0_CRD_CNTL -#define SDMA0_CRD_CNTL__DRM_CREDIT_MASK 0x0000007fL -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001f80L -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L - -// SDMA0_MMHUB_TRUSTLVL -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001c0L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000e00L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001c0000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00e00000L - -// SDMA0_GPU_IOV_VIOLATION_LOG -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003fffcL -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00f00000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xff000000L - -// SDMA0_ULV_CNTL -#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001fL -#define SDMA0_ULV_CNTL__ENTER_ULV_STATUS_MASK 0x80000000L - -// SDMA0_EA_DBIT_ADDR_DATA -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xffffffffL - -// SDMA0_EA_DBIT_ADDR_INDEX -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L - -// SDMA0_GFX_RB_CNTL -#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA0_GFX_RB_BASE -#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA0_GFX_RB_BASE_HI -#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA0_GFX_RB_RPTR -#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_GFX_RB_RPTR_HI -#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_GFX_RB_WPTR -#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_GFX_RB_WPTR_HI -#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_GFX_RB_WPTR_POLL_CNTL -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA0_GFX_RB_RPTR_ADDR_HI -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_GFX_RB_RPTR_ADDR_LO -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_GFX_IB_CNTL -#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA0_GFX_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA0_GFX_IB_RPTR -#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA0_GFX_IB_OFFSET -#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA0_GFX_IB_BASE_LO -#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA0_GFX_IB_BASE_HI -#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA0_GFX_IB_SIZE -#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA0_GFX_SKIP_CNTL -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA0_GFX_CONTEXT_STATUS -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA0_GFX_DOORBELL -#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA0_GFX_CONTEXT_CNTL -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0f000000L - -// SDMA0_GFX_DRM_WRAPPEDKEY0 -#define SDMA0_GFX_DRM_WRAPPEDKEY0__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_WRAPPEDKEY1 -#define SDMA0_GFX_DRM_WRAPPEDKEY1__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_WRAPPEDKEY2 -#define SDMA0_GFX_DRM_WRAPPEDKEY2__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_WRAPPEDKEY3 -#define SDMA0_GFX_DRM_WRAPPEDKEY3__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERKEY0 -#define SDMA0_GFX_DRM_COUNTERKEY0__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERKEY1 -#define SDMA0_GFX_DRM_COUNTERKEY1__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERKEY2 -#define SDMA0_GFX_DRM_COUNTERKEY2__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERKEY3 -#define SDMA0_GFX_DRM_COUNTERKEY3__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERDATA0 -#define SDMA0_GFX_DRM_COUNTERDATA0__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERDATA1 -#define SDMA0_GFX_DRM_COUNTERDATA1__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERDATA2 -#define SDMA0_GFX_DRM_COUNTERDATA2__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_COUNTERDATA3 -#define SDMA0_GFX_DRM_COUNTERDATA3__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_OFFSET -#define SDMA0_GFX_DRM_OFFSET__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_IVLOAD0 -#define SDMA0_GFX_DRM_IVLOAD0__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_IVLOAD1 -#define SDMA0_GFX_DRM_IVLOAD1__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_IVLOAD2 -#define SDMA0_GFX_DRM_IVLOAD2__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_IVLOAD3 -#define SDMA0_GFX_DRM_IVLOAD3__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_IVLOAD4 -#define SDMA0_GFX_DRM_IVLOAD4__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_DRM_UNROLLKEY -#define SDMA0_GFX_DRM_UNROLLKEY__VALUE_MASK 0xffffffffL - -// SDMA0_GFX_AES -#define SDMA0_GFX_AES__AES_TRUSTED_MASK 0x00000001L - -// SDMA0_GFX_STATUS -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA0_GFX_DOORBELL_LOG -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA0_GFX_WATERMARK -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA0_GFX_DOORBELL_OFFSET -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA0_GFX_CSA_ADDR_LO -#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_GFX_CSA_ADDR_HI -#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_GFX_IB_SUB_REMAIN -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA0_GFX_PREEMPT -#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA0_GFX_DUMMY_REG -#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA0_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_GFX_RB_AQL_CNTL -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA0_GFX_MINOR_PTR_UPDATE -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA0_GFX_MIDCMD_DATA0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA1 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA2 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA3 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA4 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA5 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA6 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA7 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_DATA8 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA0_GFX_MIDCMD_CNTL -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// SDMA0_PAGE_RB_CNTL -#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA0_PAGE_RB_BASE -#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA0_PAGE_RB_BASE_HI -#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA0_PAGE_RB_RPTR -#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_PAGE_RB_RPTR_HI -#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_PAGE_RB_WPTR -#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_PAGE_RB_WPTR_HI -#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_PAGE_RB_WPTR_POLL_CNTL -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA0_PAGE_RB_RPTR_ADDR_HI -#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_PAGE_RB_RPTR_ADDR_LO -#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_PAGE_IB_CNTL -#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA0_PAGE_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA0_PAGE_IB_RPTR -#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA0_PAGE_IB_OFFSET -#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA0_PAGE_IB_BASE_LO -#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA0_PAGE_IB_BASE_HI -#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA0_PAGE_IB_SIZE -#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA0_PAGE_SKIP_CNTL -#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA0_PAGE_CONTEXT_STATUS -#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA0_PAGE_DOORBELL -#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA0_PAGE_STATUS -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA0_PAGE_DOORBELL_LOG -#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA0_PAGE_WATERMARK -#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA0_PAGE_DOORBELL_OFFSET -#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA0_PAGE_CSA_ADDR_LO -#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_PAGE_CSA_ADDR_HI -#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_PAGE_IB_SUB_REMAIN -#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA0_PAGE_PREEMPT -#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA0_PAGE_DUMMY_REG -#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_PAGE_RB_AQL_CNTL -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA0_PAGE_MINOR_PTR_UPDATE -#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA0_PAGE_MIDCMD_DATA0 -#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA1 -#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA2 -#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA3 -#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA4 -#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA5 -#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA6 -#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA7 -#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_DATA8 -#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA0_PAGE_MIDCMD_CNTL -#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// SDMA0_RLC0_RB_CNTL -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA0_RLC0_RB_BASE -#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA0_RLC0_RB_BASE_HI -#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA0_RLC0_RB_RPTR -#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC0_RB_RPTR_HI -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC0_RB_WPTR -#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC0_RB_WPTR_HI -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC0_RB_WPTR_POLL_CNTL -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA0_RLC0_RB_RPTR_ADDR_HI -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC0_RB_RPTR_ADDR_LO -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_RLC0_IB_CNTL -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA0_RLC0_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA0_RLC0_IB_RPTR -#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA0_RLC0_IB_OFFSET -#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA0_RLC0_IB_BASE_LO -#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA0_RLC0_IB_BASE_HI -#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC0_IB_SIZE -#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA0_RLC0_SKIP_CNTL -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA0_RLC0_CONTEXT_STATUS -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA0_RLC0_DOORBELL -#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA0_RLC0_STATUS -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA0_RLC0_DOORBELL_LOG -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA0_RLC0_WATERMARK -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA0_RLC0_DOORBELL_OFFSET -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA0_RLC0_CSA_ADDR_LO -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_RLC0_CSA_ADDR_HI -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC0_IB_SUB_REMAIN -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA0_RLC0_PREEMPT -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA0_RLC0_DUMMY_REG -#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_RLC0_RB_AQL_CNTL -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA0_RLC0_MINOR_PTR_UPDATE -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA0_RLC0_MIDCMD_DATA0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA1 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA2 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA3 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA4 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA5 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA6 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA7 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_DATA8 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA0_RLC0_MIDCMD_CNTL -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// SDMA0_RLC1_RB_CNTL -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA0_RLC1_RB_BASE -#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA0_RLC1_RB_BASE_HI -#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA0_RLC1_RB_RPTR -#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC1_RB_RPTR_HI -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC1_RB_WPTR -#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC1_RB_WPTR_HI -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA0_RLC1_RB_WPTR_POLL_CNTL -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA0_RLC1_RB_RPTR_ADDR_HI -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC1_RB_RPTR_ADDR_LO -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_RLC1_IB_CNTL -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA0_RLC1_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA0_RLC1_IB_RPTR -#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA0_RLC1_IB_OFFSET -#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA0_RLC1_IB_BASE_LO -#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA0_RLC1_IB_BASE_HI -#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC1_IB_SIZE -#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA0_RLC1_SKIP_CNTL -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA0_RLC1_CONTEXT_STATUS -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA0_RLC1_DOORBELL -#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA0_RLC1_STATUS -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA0_RLC1_DOORBELL_LOG -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA0_RLC1_WATERMARK -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA0_RLC1_DOORBELL_OFFSET -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA0_RLC1_CSA_ADDR_LO -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_RLC1_CSA_ADDR_HI -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC1_IB_SUB_REMAIN -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA0_RLC1_PREEMPT -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA0_RLC1_DUMMY_REG -#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA0_RLC1_RB_AQL_CNTL -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA0_RLC1_MINOR_PTR_UPDATE -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA0_RLC1_MIDCMD_DATA0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA1 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA2 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA3 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA4 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA5 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA6 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA7 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_DATA8 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA0_RLC1_MIDCMD_CNTL -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// SDMA1_UCODE_ADDR -#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001fffL - -// SDMA1_UCODE_DATA -#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffffL - -// SDMA1_REGISTER_SECURITY_CNTL -#define SDMA1_REGISTER_SECURITY_CNTL__ENABLE_MASK 0x00000001L - -// SDMA1_VM_CNTL -#define SDMA1_VM_CNTL__CMD_MASK 0x0000000fL - -// SDMA1_VM_CTX_LO -#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_VM_CTX_HI -#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffffL - -// SDMA1_ACTIVE_FCN_ID -#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000fL -#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0L -#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L - -// SDMA1_VM_CTX_CNTL -#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000f0L - -// SDMA1_VIRT_RESET_REQ -#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000ffffL -#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L - -// SDMA1_CONTEXT_REG_TYPE0 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY0_MASK 0x00100000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY1_MASK 0x00200000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY2_MASK 0x00400000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY3_MASK 0x00800000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY0_MASK 0x01000000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY1_MASK 0x02000000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY2_MASK 0x04000000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY3_MASK 0x08000000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA0_MASK 0x10000000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA1_MASK 0x20000000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA2_MASK 0x40000000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA3_MASK 0x80000000L - -// SDMA1_CONTEXT_REG_TYPE1 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_OFFSET_MASK 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD0_MASK 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD1_MASK 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD2_MASK 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD3_MASK 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD4_MASK 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_UNROLLKEY_MASK 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_AES_MASK 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xffc00000L - -// SDMA1_CONTEXT_REG_TYPE2 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00L - -// SDMA1_CONTEXT_REG_TYPE3 -#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xffffffffL - -// SDMA1_PUB_REG_TYPE0 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL_MASK 0x00000004L -#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01f80000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L - -// SDMA1_PUB_REG_TYPE1 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L - -// SDMA1_PUB_REG_TYPE2 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L - -// SDMA1_PUB_REG_TYPE3 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xfffffffcL - -// SDMA1_CONTEXT_GROUP_BOUNDARY -#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xffffffffL - -// SDMA1_POWER_CNTL -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003ff000L - -// SDMA1_CLK_CTRL -#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00fff000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// SDMA1_CNTL -#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA1_CNTL__DRM_RESTORE_ENABLE_MASK 0x00080000L -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L - -// SDMA1_CHICKEN_BITS -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001c00L -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0c000000L -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000L - -// SDMA1_GB_ADDR_CONFIG -#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L - -// SDMA1_GB_ADDR_CONFIG_READ -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L - -// SDMA1_RB_RPTR_FETCH_HI -#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffffL - -// SDMA1_RB_RPTR_FETCH -#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffcL - -// SDMA1_IB_OFFSET_FETCH -#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003ffffcL - -// SDMA1_PROGRAM -#define SDMA1_PROGRAM__STREAM_MASK 0xffffffffL - -// SDMA1_STATUS_REG -#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA1_STATUS_REG__DRM_IDLE_MASK 0x00800000L -#define SDMA1_STATUS_REG__DRM_MASK_FULL_MASK 0x01000000L -#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L - -// SDMA1_STATUS1_REG -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA1_STATUS1_REG__CE_DRM_IDLE_MASK 0x00000080L -#define SDMA1_STATUS1_REG__CE_DRM1_IDLE_MASK 0x00000100L -#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA1_STATUS1_REG__CE_DRM_FULL_MASK 0x00000800L -#define SDMA1_STATUS1_REG__CE_DRM1_FULL_MASK 0x00001000L -#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA1_STATUS1_REG__DRM_CTX_RESTORE_MASK 0x00010000L -#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L - -// SDMA1_RD_BURST_CNTL -#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L - -// SDMA1_HBM_PAGE_CONFIG -#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L - -// SDMA1_UCODE_CHECKSUM -#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xffffffffL - -// SDMA1_F32_CNTL -#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L -#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000fcL - -// SDMA1_FREEZE -#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L - -// SDMA1_PHASE0_QUANTUM -#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000fL -#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00ffff00L -#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L - -// SDMA1_PHASE1_QUANTUM -#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000fL -#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00ffff00L -#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L - -// SDMA1_EDC_CONFIG -#define SDMA1_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L -#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L - -// SDMA1_BA_THRESHOLD -#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003ffL -#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03ff0000L - -// SDMA1_ID -#define SDMA1_ID__DEVICE_ID_MASK 0x000000ffL - -// SDMA1_VERSION -#define SDMA1_VERSION__MINVER_MASK 0x0000007fL -#define SDMA1_VERSION__MAJVER_MASK 0x00007f00L -#define SDMA1_VERSION__REV_MASK 0x003f0000L - -// SDMA1_EDC_COUNTER -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L - -// SDMA1_EDC_COUNTER_CLEAR -#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L - -// SDMA1_STATUS2_REG -#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000ffcL -#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000L - -// SDMA1_ATOMIC_CNTL -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffffL -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L - -// SDMA1_ATOMIC_PREOP_LO -#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffffL - -// SDMA1_ATOMIC_PREOP_HI -#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffffL - -// SDMA1_UTCL1_CNTL -#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007feL -#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00ffc000L -#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1f000000L -#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xe0000000L - -// SDMA1_UTCL1_WATERMK -#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003ffL -#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003fc00L -#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03fc0000L -#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xfc000000L - -// SDMA1_UTCL1_RD_STATUS -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03c00000L -#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000L -#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L - -// SDMA1_UTCL1_WR_STATUS -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01c00000L -#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0e000000L -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L - -// SDMA1_UTCL1_INV0 -#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0ffff000L -#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xf0000000L - -// SDMA1_UTCL1_INV1 -#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xffffffffL - -// SDMA1_UTCL1_INV2 -#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffffffffL - -// SDMA1_UTCL1_RD_XNACK0 -#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffffL - -// SDMA1_UTCL1_RD_XNACK1 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000fL -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000f0L -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03ffff00L -#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0c000000L - -// SDMA1_UTCL1_WR_XNACK0 -#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffffL - -// SDMA1_UTCL1_WR_XNACK1 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000fL -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000f0L -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03ffff00L -#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0c000000L - -// SDMA1_UTCL1_TIMEOUT -#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000ffffL -#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000L - -// SDMA1_UTCL1_PAGE -#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001eL -#define SDMA1_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L -#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001c0L -#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L - -// SDMA1_POWER_CNTL_IDLE -#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000ffffL -#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00ff0000L -#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000L - -// SDMA1_RELAX_ORDERING_LUT -#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000c0L -#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07ffc000L -#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L - -// SDMA1_CHICKEN_BITS_2 -#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000fL - -// SDMA1_STATUS3_REG -#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000ffffL -#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000f0000L -#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L - -// SDMA1_PHYSICAL_ADDR_LO -#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xfffff000L - -// SDMA1_PHYSICAL_ADDR_HI -#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000ffffL - -// SDMA1_PHASE2_QUANTUM -#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000fL -#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00ffff00L -#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L - -// SDMA1_ERROR_LOG -#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000ffffL -#define SDMA1_ERROR_LOG__STATUS_MASK 0xffff0000L - -// SDMA1_PUB_DUMMY_REG0 -#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xffffffffL - -// SDMA1_PUB_DUMMY_REG1 -#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xffffffffL - -// SDMA1_PUB_DUMMY_REG2 -#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xffffffffL - -// SDMA1_PUB_DUMMY_REG3 -#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xffffffffL - -// SDMA1_F32_COUNTER -#define SDMA1_F32_COUNTER__VALUE_MASK 0xffffffffL - -// SDMA1_UNBREAKABLE -#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L - -// SDMA1_PERFMON_CNTL -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003fcL -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000ff000L - -// SDMA1_PERFCOUNTER0_RESULT -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL - -// SDMA1_PERFCOUNTER1_RESULT -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL - -// SDMA1_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003fffL -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0fffc000L -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L - -// SDMA1_CRD_CNTL -#define SDMA1_CRD_CNTL__DRM_CREDIT_MASK 0x0000007fL -#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001f80L -#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L - -// SDMA1_MMHUB_TRUSTLVL -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001c0L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000e00L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001c0000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00e00000L - -// SDMA1_GPU_IOV_VIOLATION_LOG -#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003fffcL -#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00f00000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xff000000L - -// SDMA1_ULV_CNTL -#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001fL -#define SDMA1_ULV_CNTL__ENTER_ULV_STATUS_MASK 0x80000000L - -// SDMA1_EA_DBIT_ADDR_DATA -#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xffffffffL - -// SDMA1_EA_DBIT_ADDR_INDEX -#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L - -// SDMA1_GFX_RB_CNTL -#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA1_GFX_RB_BASE -#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA1_GFX_RB_BASE_HI -#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA1_GFX_RB_RPTR -#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_GFX_RB_RPTR_HI -#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_GFX_RB_WPTR -#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_GFX_RB_WPTR_HI -#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_GFX_RB_WPTR_POLL_CNTL -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA1_GFX_RB_RPTR_ADDR_HI -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_GFX_RB_RPTR_ADDR_LO -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_GFX_IB_CNTL -#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA1_GFX_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA1_GFX_IB_RPTR -#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA1_GFX_IB_OFFSET -#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA1_GFX_IB_BASE_LO -#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA1_GFX_IB_BASE_HI -#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA1_GFX_IB_SIZE -#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA1_GFX_SKIP_CNTL -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA1_GFX_CONTEXT_STATUS -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA1_GFX_DOORBELL -#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA1_GFX_CONTEXT_CNTL -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0f000000L - -// SDMA1_GFX_AES -#define SDMA1_GFX_AES__AES_TRUSTED_MASK 0x00000001L - -// SDMA1_GFX_STATUS -#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA1_GFX_DOORBELL_LOG -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA1_GFX_WATERMARK -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA1_GFX_DOORBELL_OFFSET -#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA1_GFX_CSA_ADDR_LO -#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_GFX_CSA_ADDR_HI -#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_GFX_IB_SUB_REMAIN -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA1_GFX_PREEMPT -#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA1_GFX_DUMMY_REG -#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA1_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_GFX_RB_AQL_CNTL -#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA1_GFX_MINOR_PTR_UPDATE -#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA1_GFX_MIDCMD_DATA0 -#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA1 -#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA2 -#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA3 -#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA4 -#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA5 -#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA6 -#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA7 -#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_DATA8 -#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA1_GFX_MIDCMD_CNTL -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// SDMA1_PAGE_RB_CNTL -#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA1_PAGE_RB_BASE -#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA1_PAGE_RB_BASE_HI -#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA1_PAGE_RB_RPTR -#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_PAGE_RB_RPTR_HI -#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_PAGE_RB_WPTR -#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_PAGE_RB_WPTR_HI -#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_PAGE_RB_WPTR_POLL_CNTL -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA1_PAGE_RB_RPTR_ADDR_HI -#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_PAGE_RB_RPTR_ADDR_LO -#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_PAGE_IB_CNTL -#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA1_PAGE_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA1_PAGE_IB_RPTR -#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA1_PAGE_IB_OFFSET -#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA1_PAGE_IB_BASE_LO -#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA1_PAGE_IB_BASE_HI -#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA1_PAGE_IB_SIZE -#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA1_PAGE_SKIP_CNTL -#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA1_PAGE_CONTEXT_STATUS -#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA1_PAGE_DOORBELL -#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA1_PAGE_STATUS -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA1_PAGE_DOORBELL_LOG -#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA1_PAGE_WATERMARK -#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA1_PAGE_DOORBELL_OFFSET -#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA1_PAGE_CSA_ADDR_LO -#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_PAGE_CSA_ADDR_HI -#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_PAGE_IB_SUB_REMAIN -#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA1_PAGE_PREEMPT -#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA1_PAGE_DUMMY_REG -#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_PAGE_RB_AQL_CNTL -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA1_PAGE_MINOR_PTR_UPDATE -#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA1_PAGE_MIDCMD_DATA0 -#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA1 -#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA2 -#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA3 -#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA4 -#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA5 -#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA6 -#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA7 -#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_DATA8 -#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA1_PAGE_MIDCMD_CNTL -#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// SDMA1_RLC0_RB_CNTL -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA1_RLC0_RB_BASE -#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA1_RLC0_RB_BASE_HI -#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA1_RLC0_RB_RPTR -#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC0_RB_RPTR_HI -#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC0_RB_WPTR -#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC0_RB_WPTR_HI -#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC0_RB_WPTR_POLL_CNTL -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA1_RLC0_RB_RPTR_ADDR_HI -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC0_RB_RPTR_ADDR_LO -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_RLC0_IB_CNTL -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA1_RLC0_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA1_RLC0_IB_RPTR -#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA1_RLC0_IB_OFFSET -#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA1_RLC0_IB_BASE_LO -#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA1_RLC0_IB_BASE_HI -#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC0_IB_SIZE -#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA1_RLC0_SKIP_CNTL -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA1_RLC0_CONTEXT_STATUS -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA1_RLC0_DOORBELL -#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA1_RLC0_STATUS -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA1_RLC0_DOORBELL_LOG -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA1_RLC0_WATERMARK -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA1_RLC0_DOORBELL_OFFSET -#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA1_RLC0_CSA_ADDR_LO -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_RLC0_CSA_ADDR_HI -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC0_IB_SUB_REMAIN -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA1_RLC0_PREEMPT -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA1_RLC0_DUMMY_REG -#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_RLC0_RB_AQL_CNTL -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA1_RLC0_MINOR_PTR_UPDATE -#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA1_RLC0_MIDCMD_DATA0 -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA1 -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA2 -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA3 -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA4 -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA5 -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA6 -#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA7 -#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_DATA8 -#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA1_RLC0_MIDCMD_CNTL -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// SDMA1_RLC1_RB_CNTL -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007eL -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000L -#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0f000000L - -// SDMA1_RLC1_RB_BASE -#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffffL - -// SDMA1_RLC1_RB_BASE_HI -#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00ffffffL - -// SDMA1_RLC1_RB_RPTR -#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC1_RB_RPTR_HI -#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC1_RB_WPTR -#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC1_RB_WPTR_HI -#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xffffffffL - -// SDMA1_RLC1_RB_WPTR_POLL_CNTL -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000fff0L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// SDMA1_RLC1_RB_RPTR_ADDR_HI -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC1_RB_RPTR_ADDR_LO -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_RLC1_IB_CNTL -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000f0000L -#define SDMA1_RLC1_IB_CNTL__IB_PRIV_MASK 0x80000000L - -// SDMA1_RLC1_IB_RPTR -#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003ffffcL - -// SDMA1_RLC1_IB_OFFSET -#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003ffffcL - -// SDMA1_RLC1_IB_BASE_LO -#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0L - -// SDMA1_RLC1_IB_BASE_HI -#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC1_IB_SIZE -#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000fffffL - -// SDMA1_RLC1_SKIP_CNTL -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003fffL - -// SDMA1_RLC1_CONTEXT_STATUS -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L - -// SDMA1_RLC1_DOORBELL -#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L - -// SDMA1_RLC1_STATUS -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000ffL -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L - -// SDMA1_RLC1_DOORBELL_LOG -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffcL - -// SDMA1_RLC1_WATERMARK -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000fffL -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03ff0000L - -// SDMA1_RLC1_DOORBELL_OFFSET -#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcL - -// SDMA1_RLC1_CSA_ADDR_LO -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_RLC1_CSA_ADDR_HI -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC1_IB_SUB_REMAIN -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003fffL - -// SDMA1_RLC1_PREEMPT -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L - -// SDMA1_RLC1_DUMMY_REG -#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffffL - -// SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffffL - -// SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffcL - -// SDMA1_RLC1_RB_AQL_CNTL -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feL -#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00L - -// SDMA1_RLC1_MINOR_PTR_UPDATE -#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L - -// SDMA1_RLC1_MIDCMD_DATA0 -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA1 -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA2 -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA3 -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA4 -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA5 -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA6 -#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA7 -#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_DATA8 -#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffffL - -// SDMA1_RLC1_MIDCMD_CNTL -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000f0L -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -// MP0_SMNIF_ERROR -#define MP0_SMNIF_ERROR__RESERVED_MASK 0xffffffffL - -// MP0_SFUSE_PUB -#define MP0_SFUSE_PUB__DATA_MASK 0xffffffffL - -// MP0_FW_DEBUG_CNT0 -#define MP0_FW_DEBUG_CNT0__DATA_MASK 0x0000ffffL - -// MP0_FW_DEBUG_CNT1 -#define MP0_FW_DEBUG_CNT1__DATA_MASK 0x0000ffffL - -// MP0_FW_DEBUG_CNT2 -#define MP0_FW_DEBUG_CNT2__DATA_MASK 0x0000ffffL - -// MP0_FW_DEBUG_CNT3 -#define MP0_FW_DEBUG_CNT3__DATA_MASK 0x0000ffffL - -// MP0_FW_DEBUG_SIGNAL0 -#define MP0_FW_DEBUG_SIGNAL0__DATA_MASK 0x00ffffffL - -// MP0_FW_DEBUG_SIGNAL1 -#define MP0_FW_DEBUG_SIGNAL1__DATA_MASK 0x00ffffffL - -// MP0_DSM_ENABLE -#define MP0_DSM_ENABLE__MP0_ENB_EDBGREQ_MASK 0x00000001L -#define MP0_DSM_ENABLE__MP0_ENB_DBGRESTART_MASK 0x00000002L -#define MP0_DSM_ENABLE__MP0_ENB_UNUSED_MASK 0x00000004L -#define MP0_DSM_ENABLE__MP0_ENB_DSMINT_MASK 0x00000008L - -// MP0_SOC_INFO -#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L -#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001cL - -// MP0_MUTEX_0 -#define MP0_MUTEX_0__MUTEX_MASK 0x000000ffL - -// MP0_MUTEX_1 -#define MP0_MUTEX_1__MUTEX_MASK 0x000000ffL - -// MP0_MUTEX_2 -#define MP0_MUTEX_2__MUTEX_MASK 0x000000ffL - -// MP0_MUTEX_3 -#define MP0_MUTEX_3__MUTEX_MASK 0x000000ffL - -// MP0_PUB_SCRATCH0 -#define MP0_PUB_SCRATCH0__DATA_MASK 0xffffffffL - -// MP0_PUB_SCRATCH1 -#define MP0_PUB_SCRATCH1__DATA_MASK 0xffffffffL - -// MP0_PUB_SCRATCH2 -#define MP0_PUB_SCRATCH2__DATA_MASK 0xffffffffL - -// MP0_PUB_SCRATCH3 -#define MP0_PUB_SCRATCH3__DATA_MASK 0xffffffffL - -// MP0_RSMU_SECINTR -#define MP0_RSMU_SECINTR__RESEREVED_MASK 0xffffffffL - -// MP0_FW_INTF -#define MP0_FW_INTF__FRA_BOOT_TDR_MASK 0x00000001L -#define MP0_FW_INTF__FUSE_VALID_MASK 0x00000002L -#define MP0_FW_INTF__FUSE_ERROR_MASK 0x00000004L -#define MP0_FW_INTF__FUSE_SSTATE_MASK 0x00000018L -#define MP0_FW_INTF__FRA_EN_TDR_MASK 0x00000080L -#define MP0_FW_INTF__AEB_VALID_MASK 0x00000100L -#define MP0_FW_INTF__AEB_DATA_MASK 0x00000e00L -#define MP0_FW_INTF__SS_UNK_MASK 0x00010000L -#define MP0_FW_INTF__SS_BLANK_MASK 0x00020000L -#define MP0_FW_INTF__SS_PROTO_MASK 0x00040000L -#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L -#define MP0_FW_INTF__SS_FRA_MASK 0x00100000L -#define MP0_FW_INTF__SS_NOTR_MASK 0x00200000L - -// MP0_FW_CHRONO_LO -#define MP0_FW_CHRONO_LO__COUNT_MASK 0xffffffffL - -// MP0_FW_CHRONO_HI -#define MP0_FW_CHRONO_HI__COUNT_MASK 0xffffffffL - -// MP0_PIC0_MASK_0 -#define MP0_PIC0_MASK_0__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC0_MASK_0__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC0_MASK_0__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC0_MASK_0__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC0_MASK_0__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC0_MASK_0__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC0_MASK_0__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC0_MASK_0__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC0_MASK_0__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC0_MASK_0__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC0_MASK_0__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC0_MASK_0__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC0_MASK_0__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC0_MASK_0__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC0_MASK_0__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC0_MASK_0__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC0_MASK_0__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC0_MASK_0__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC0_MASK_0__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC0_MASK_0__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC0_MASK_0__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC0_MASK_0__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC0_MASK_0__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC0_MASK_0__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC0_MASK_0__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC0_MASK_0__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC0_MASK_0__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC0_MASK_0__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC0_MASK_0__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC0_MASK_0__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC0_MASK_0__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC0_MASK_0__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC0_MASK_1 -#define MP0_PIC0_MASK_1__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC0_MASK_1__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC0_MASK_1__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC0_MASK_1__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC0_MASK_1__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC0_MASK_1__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC0_MASK_1__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC0_MASK_1__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC0_MASK_1__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC0_MASK_1__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC0_MASK_1__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC0_MASK_1__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC0_MASK_1__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC0_MASK_1__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC0_MASK_1__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC0_MASK_1__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC0_MASK_1__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC0_MASK_1__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC0_MASK_1__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC0_MASK_1__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC0_MASK_1__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC0_MASK_1__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC0_MASK_1__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC0_MASK_1__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC0_MASK_1__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC0_MASK_1__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC0_MASK_1__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC0_MASK_1__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC0_MASK_1__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC0_MASK_1__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC0_MASK_1__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC0_MASK_1__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC0_MASK_2 -#define MP0_PIC0_MASK_2__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC0_MASK_2__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC0_MASK_2__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC0_MASK_2__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC0_MASK_2__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC0_MASK_2__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC0_MASK_2__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC0_MASK_2__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC0_MASK_2__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC0_MASK_2__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC0_MASK_2__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC0_MASK_2__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC0_MASK_2__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC0_MASK_2__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC0_MASK_2__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC0_MASK_2__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC0_MASK_2__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC0_MASK_2__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC0_MASK_2__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC0_MASK_2__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC0_MASK_2__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC0_MASK_2__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC0_MASK_2__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC0_MASK_2__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC0_MASK_2__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC0_MASK_2__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC0_MASK_2__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC0_MASK_2__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC0_MASK_2__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC0_MASK_2__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC0_MASK_2__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC0_MASK_2__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC0_MASK_3 -#define MP0_PIC0_MASK_3__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC0_MASK_3__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC0_MASK_3__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC0_MASK_3__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC0_MASK_3__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC0_MASK_3__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC0_MASK_3__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC0_MASK_3__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC0_MASK_3__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC0_MASK_3__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC0_MASK_3__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC0_MASK_3__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC0_MASK_3__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC0_MASK_3__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC0_MASK_3__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC0_MASK_3__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC0_MASK_3__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC0_MASK_3__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC0_MASK_3__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC0_MASK_3__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC0_MASK_3__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC0_MASK_3__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC0_MASK_3__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC0_MASK_3__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC0_MASK_3__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC0_MASK_3__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC0_MASK_3__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC0_MASK_3__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC0_MASK_3__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC0_MASK_3__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC0_MASK_3__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC0_MASK_3__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC0_STATUS_0 -#define MP0_PIC0_STATUS_0__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC0_STATUS_0__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC0_STATUS_0__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC0_STATUS_0__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC0_STATUS_0__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC0_STATUS_0__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC0_STATUS_0__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC0_STATUS_0__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC0_STATUS_0__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC0_STATUS_0__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC0_STATUS_0__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC0_STATUS_0__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC0_STATUS_0__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC0_STATUS_0__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC0_STATUS_1 -#define MP0_PIC0_STATUS_1__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC0_STATUS_1__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC0_STATUS_1__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC0_STATUS_1__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC0_STATUS_1__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC0_STATUS_1__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC0_STATUS_1__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC0_STATUS_1__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC0_STATUS_1__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC0_STATUS_1__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC0_STATUS_1__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC0_STATUS_1__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC0_STATUS_1__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC0_STATUS_1__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC0_STATUS_2 -#define MP0_PIC0_STATUS_2__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC0_STATUS_2__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC0_STATUS_2__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC0_STATUS_2__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC0_STATUS_2__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC0_STATUS_2__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC0_STATUS_2__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC0_STATUS_2__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC0_STATUS_2__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC0_STATUS_2__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC0_STATUS_2__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC0_STATUS_2__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC0_STATUS_2__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC0_STATUS_2__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC0_STATUS_3 -#define MP0_PIC0_STATUS_3__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC0_STATUS_3__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC0_STATUS_3__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC0_STATUS_3__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC0_STATUS_3__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC0_STATUS_3__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC0_STATUS_3__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC0_STATUS_3__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC0_STATUS_3__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC0_STATUS_3__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC0_STATUS_3__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC0_STATUS_3__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC0_STATUS_3__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC0_STATUS_3__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC0_INTR -#define MP0_PIC0_INTR__INTR_LINE_MASK 0x00000001L -#define MP0_PIC0_INTR__RESERVED_MASK 0xfffffffeL - -// MP0_PIC0_ID -#define MP0_PIC0_ID__INTR_ID_MASK 0x000000ffL -#define MP0_PIC0_ID__RESERVED_MASK 0xffffff00L - -// MP0_PIC1_MASK_0 -#define MP0_PIC1_MASK_0__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC1_MASK_0__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC1_MASK_0__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC1_MASK_0__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC1_MASK_0__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC1_MASK_0__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC1_MASK_0__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC1_MASK_0__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC1_MASK_0__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC1_MASK_0__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC1_MASK_0__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC1_MASK_0__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC1_MASK_0__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC1_MASK_0__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC1_MASK_0__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC1_MASK_0__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC1_MASK_0__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC1_MASK_0__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC1_MASK_0__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC1_MASK_0__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC1_MASK_0__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC1_MASK_0__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC1_MASK_0__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC1_MASK_0__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC1_MASK_0__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC1_MASK_0__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC1_MASK_0__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC1_MASK_0__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC1_MASK_0__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC1_MASK_0__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC1_MASK_0__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC1_MASK_0__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC1_MASK_1 -#define MP0_PIC1_MASK_1__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC1_MASK_1__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC1_MASK_1__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC1_MASK_1__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC1_MASK_1__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC1_MASK_1__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC1_MASK_1__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC1_MASK_1__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC1_MASK_1__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC1_MASK_1__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC1_MASK_1__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC1_MASK_1__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC1_MASK_1__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC1_MASK_1__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC1_MASK_1__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC1_MASK_1__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC1_MASK_1__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC1_MASK_1__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC1_MASK_1__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC1_MASK_1__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC1_MASK_1__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC1_MASK_1__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC1_MASK_1__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC1_MASK_1__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC1_MASK_1__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC1_MASK_1__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC1_MASK_1__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC1_MASK_1__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC1_MASK_1__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC1_MASK_1__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC1_MASK_1__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC1_MASK_1__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC1_MASK_2 -#define MP0_PIC1_MASK_2__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC1_MASK_2__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC1_MASK_2__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC1_MASK_2__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC1_MASK_2__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC1_MASK_2__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC1_MASK_2__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC1_MASK_2__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC1_MASK_2__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC1_MASK_2__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC1_MASK_2__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC1_MASK_2__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC1_MASK_2__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC1_MASK_2__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC1_MASK_2__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC1_MASK_2__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC1_MASK_2__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC1_MASK_2__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC1_MASK_2__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC1_MASK_2__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC1_MASK_2__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC1_MASK_2__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC1_MASK_2__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC1_MASK_2__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC1_MASK_2__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC1_MASK_2__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC1_MASK_2__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC1_MASK_2__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC1_MASK_2__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC1_MASK_2__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC1_MASK_2__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC1_MASK_2__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC1_MASK_3 -#define MP0_PIC1_MASK_3__INTR_MASK_0_MASK 0x00000001L -#define MP0_PIC1_MASK_3__INTR_MASK_1_MASK 0x00000002L -#define MP0_PIC1_MASK_3__INTR_MASK_2_MASK 0x00000004L -#define MP0_PIC1_MASK_3__INTR_MASK_3_MASK 0x00000008L -#define MP0_PIC1_MASK_3__INTR_MASK_4_MASK 0x00000010L -#define MP0_PIC1_MASK_3__INTR_MASK_5_MASK 0x00000020L -#define MP0_PIC1_MASK_3__INTR_MASK_6_MASK 0x00000040L -#define MP0_PIC1_MASK_3__INTR_MASK_7_MASK 0x00000080L -#define MP0_PIC1_MASK_3__INTR_MASK_8_MASK 0x00000100L -#define MP0_PIC1_MASK_3__INTR_MASK_9_MASK 0x00000200L -#define MP0_PIC1_MASK_3__INTR_MASK_10_MASK 0x00000400L -#define MP0_PIC1_MASK_3__INTR_MASK_11_MASK 0x00000800L -#define MP0_PIC1_MASK_3__INTR_MASK_12_MASK 0x00001000L -#define MP0_PIC1_MASK_3__INTR_MASK_13_MASK 0x00002000L -#define MP0_PIC1_MASK_3__INTR_MASK_14_MASK 0x00004000L -#define MP0_PIC1_MASK_3__INTR_MASK_15_MASK 0x00008000L -#define MP0_PIC1_MASK_3__INTR_MASK_16_MASK 0x00010000L -#define MP0_PIC1_MASK_3__INTR_MASK_17_MASK 0x00020000L -#define MP0_PIC1_MASK_3__INTR_MASK_18_MASK 0x00040000L -#define MP0_PIC1_MASK_3__INTR_MASK_19_MASK 0x00080000L -#define MP0_PIC1_MASK_3__INTR_MASK_20_MASK 0x00100000L -#define MP0_PIC1_MASK_3__INTR_MASK_21_MASK 0x00200000L -#define MP0_PIC1_MASK_3__INTR_MASK_22_MASK 0x00400000L -#define MP0_PIC1_MASK_3__INTR_MASK_23_MASK 0x00800000L -#define MP0_PIC1_MASK_3__INTR_MASK_24_MASK 0x01000000L -#define MP0_PIC1_MASK_3__INTR_MASK_25_MASK 0x02000000L -#define MP0_PIC1_MASK_3__INTR_MASK_26_MASK 0x04000000L -#define MP0_PIC1_MASK_3__INTR_MASK_27_MASK 0x08000000L -#define MP0_PIC1_MASK_3__INTR_MASK_28_MASK 0x10000000L -#define MP0_PIC1_MASK_3__INTR_MASK_29_MASK 0x20000000L -#define MP0_PIC1_MASK_3__INTR_MASK_30_MASK 0x40000000L -#define MP0_PIC1_MASK_3__INTR_MASK_31_MASK 0x80000000L - -// MP0_PIC1_STATUS_0 -#define MP0_PIC1_STATUS_0__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC1_STATUS_0__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC1_STATUS_0__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC1_STATUS_0__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC1_STATUS_0__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC1_STATUS_0__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC1_STATUS_0__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC1_STATUS_0__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC1_STATUS_0__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC1_STATUS_0__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC1_STATUS_0__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC1_STATUS_0__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC1_STATUS_0__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC1_STATUS_0__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC1_STATUS_1 -#define MP0_PIC1_STATUS_1__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC1_STATUS_1__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC1_STATUS_1__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC1_STATUS_1__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC1_STATUS_1__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC1_STATUS_1__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC1_STATUS_1__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC1_STATUS_1__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC1_STATUS_1__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC1_STATUS_1__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC1_STATUS_1__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC1_STATUS_1__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC1_STATUS_1__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC1_STATUS_1__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC1_STATUS_2 -#define MP0_PIC1_STATUS_2__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC1_STATUS_2__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC1_STATUS_2__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC1_STATUS_2__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC1_STATUS_2__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC1_STATUS_2__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC1_STATUS_2__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC1_STATUS_2__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC1_STATUS_2__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC1_STATUS_2__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC1_STATUS_2__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC1_STATUS_2__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC1_STATUS_2__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC1_STATUS_2__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC1_STATUS_3 -#define MP0_PIC1_STATUS_3__INTR_FLAG_0_MASK 0x00000001L -#define MP0_PIC1_STATUS_3__INTR_FLAG_1_MASK 0x00000002L -#define MP0_PIC1_STATUS_3__INTR_FLAG_2_MASK 0x00000004L -#define MP0_PIC1_STATUS_3__INTR_FLAG_3_MASK 0x00000008L -#define MP0_PIC1_STATUS_3__INTR_FLAG_4_MASK 0x00000010L -#define MP0_PIC1_STATUS_3__INTR_FLAG_5_MASK 0x00000020L -#define MP0_PIC1_STATUS_3__INTR_FLAG_6_MASK 0x00000040L -#define MP0_PIC1_STATUS_3__INTR_FLAG_7_MASK 0x00000080L -#define MP0_PIC1_STATUS_3__INTR_FLAG_8_MASK 0x00000100L -#define MP0_PIC1_STATUS_3__INTR_FLAG_9_MASK 0x00000200L -#define MP0_PIC1_STATUS_3__INTR_FLAG_10_MASK 0x00000400L -#define MP0_PIC1_STATUS_3__INTR_FLAG_11_MASK 0x00000800L -#define MP0_PIC1_STATUS_3__INTR_FLAG_12_MASK 0x00001000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_13_MASK 0x00002000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_14_MASK 0x00004000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_15_MASK 0x00008000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_16_MASK 0x00010000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_17_MASK 0x00020000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_18_MASK 0x00040000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_19_MASK 0x00080000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_20_MASK 0x00100000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_21_MASK 0x00200000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_22_MASK 0x00400000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_23_MASK 0x00800000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_24_MASK 0x01000000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_25_MASK 0x02000000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_26_MASK 0x04000000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_27_MASK 0x08000000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_28_MASK 0x10000000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_29_MASK 0x20000000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_30_MASK 0x40000000L -#define MP0_PIC1_STATUS_3__INTR_FLAG_31_MASK 0x80000000L - -// MP0_PIC1_INTR -#define MP0_PIC1_INTR__INTR_LINE_MASK 0x00000001L -#define MP0_PIC1_INTR__RESERVED_MASK 0xfffffffeL - -// MP0_PIC1_ID -#define MP0_PIC1_ID__INTR_ID_MASK 0x000000ffL -#define MP0_PIC1_ID__RESERVED_MASK 0xffffff00L - -// MP0_TIMER_0_CTRL0 -#define MP0_TIMER_0_CTRL0__START_MASK 0x00000001L -#define MP0_TIMER_0_CTRL0__CLEAR_MASK 0x00000100L -#define MP0_TIMER_0_CTRL0__DEC_MASK 0x00010000L -#define MP0_TIMER_0_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP0_TIMER_1_CTRL0 -#define MP0_TIMER_1_CTRL0__START_MASK 0x00000001L -#define MP0_TIMER_1_CTRL0__CLEAR_MASK 0x00000100L -#define MP0_TIMER_1_CTRL0__DEC_MASK 0x00010000L -#define MP0_TIMER_1_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP0_TIMER_2_CTRL0 -#define MP0_TIMER_2_CTRL0__START_MASK 0x00000001L -#define MP0_TIMER_2_CTRL0__CLEAR_MASK 0x00000100L -#define MP0_TIMER_2_CTRL0__DEC_MASK 0x00010000L -#define MP0_TIMER_2_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP0_TIMER_3_CTRL0 -#define MP0_TIMER_3_CTRL0__START_MASK 0x00000001L -#define MP0_TIMER_3_CTRL0__CLEAR_MASK 0x00000100L -#define MP0_TIMER_3_CTRL0__DEC_MASK 0x00010000L -#define MP0_TIMER_3_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP0_TIMER_0_CTRL1 -#define MP0_TIMER_0_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP0_TIMER_0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP0_TIMER_0_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP0_TIMER_0_CTRL1__RESERVED_MASK 0xff000000L - -// MP0_TIMER_1_CTRL1 -#define MP0_TIMER_1_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP0_TIMER_1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP0_TIMER_1_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP0_TIMER_1_CTRL1__RESERVED_MASK 0xff000000L - -// MP0_TIMER_2_CTRL1 -#define MP0_TIMER_2_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP0_TIMER_2_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP0_TIMER_2_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP0_TIMER_2_CTRL1__RESERVED_MASK 0xff000000L - -// MP0_TIMER_3_CTRL1 -#define MP0_TIMER_3_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP0_TIMER_3_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP0_TIMER_3_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP0_TIMER_3_CTRL1__RESERVED_MASK 0xff000000L - -// MP0_TIMER_0_CMP0_AUTOINC -#define MP0_TIMER_0_CMP0_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP0_TIMER_0_CMP0_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_1_CMP0_AUTOINC -#define MP0_TIMER_1_CMP0_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP0_TIMER_1_CMP0_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_2_CMP0_AUTOINC -#define MP0_TIMER_2_CMP0_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP0_TIMER_2_CMP0_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_3_CMP0_AUTOINC -#define MP0_TIMER_3_CMP0_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP0_TIMER_3_CMP0_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_0_INTEN -#define MP0_TIMER_0_INTEN__INTEN_MASK 0x0000000fL -#define MP0_TIMER_0_INTEN__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_1_INTEN -#define MP0_TIMER_1_INTEN__INTEN_MASK 0x0000000fL -#define MP0_TIMER_1_INTEN__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_2_INTEN -#define MP0_TIMER_2_INTEN__INTEN_MASK 0x0000000fL -#define MP0_TIMER_2_INTEN__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_3_INTEN -#define MP0_TIMER_3_INTEN__INTEN_MASK 0x0000000fL -#define MP0_TIMER_3_INTEN__RESERVED_MASK 0xfffffff0L - -// MP0_TIMER_OCMP0_0_0 -#define MP0_TIMER_OCMP0_0_0__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_1_0 -#define MP0_TIMER_OCMP0_1_0__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_2_0 -#define MP0_TIMER_OCMP0_2_0__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_3_0 -#define MP0_TIMER_OCMP0_3_0__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_0_1 -#define MP0_TIMER_OCMP0_0_1__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_1_1 -#define MP0_TIMER_OCMP0_1_1__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_2_1 -#define MP0_TIMER_OCMP0_2_1__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_3_1 -#define MP0_TIMER_OCMP0_3_1__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_0_2 -#define MP0_TIMER_OCMP0_0_2__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_1_2 -#define MP0_TIMER_OCMP0_1_2__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_2_2 -#define MP0_TIMER_OCMP0_2_2__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_3_2 -#define MP0_TIMER_OCMP0_3_2__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_0_3 -#define MP0_TIMER_OCMP0_0_3__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_1_3 -#define MP0_TIMER_OCMP0_1_3__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_2_3 -#define MP0_TIMER_OCMP0_2_3__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_OCMP0_3_3 -#define MP0_TIMER_OCMP0_3_3__OCMP0_MASK 0xffffffffL - -// MP0_TIMER_0_CNT -#define MP0_TIMER_0_CNT__COUNT_MASK 0xffffffffL - -// MP0_TIMER_1_CNT -#define MP0_TIMER_1_CNT__COUNT_MASK 0xffffffffL - -// MP0_TIMER_2_CNT -#define MP0_TIMER_2_CNT__COUNT_MASK 0xffffffffL - -// MP0_TIMER_3_CNT -#define MP0_TIMER_3_CNT__COUNT_MASK 0xffffffffL - -// MP0_C2PMSG_0 -#define MP0_C2PMSG_0__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_1 -#define MP0_C2PMSG_1__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_2 -#define MP0_C2PMSG_2__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_3 -#define MP0_C2PMSG_3__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_4 -#define MP0_C2PMSG_4__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_5 -#define MP0_C2PMSG_5__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_6 -#define MP0_C2PMSG_6__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_7 -#define MP0_C2PMSG_7__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_8 -#define MP0_C2PMSG_8__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_9 -#define MP0_C2PMSG_9__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_10 -#define MP0_C2PMSG_10__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_11 -#define MP0_C2PMSG_11__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_12 -#define MP0_C2PMSG_12__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_13 -#define MP0_C2PMSG_13__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_14 -#define MP0_C2PMSG_14__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_15 -#define MP0_C2PMSG_15__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_16 -#define MP0_C2PMSG_16__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_17 -#define MP0_C2PMSG_17__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_18 -#define MP0_C2PMSG_18__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_19 -#define MP0_C2PMSG_19__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_20 -#define MP0_C2PMSG_20__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_21 -#define MP0_C2PMSG_21__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_22 -#define MP0_C2PMSG_22__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_23 -#define MP0_C2PMSG_23__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_24 -#define MP0_C2PMSG_24__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_25 -#define MP0_C2PMSG_25__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_26 -#define MP0_C2PMSG_26__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_27 -#define MP0_C2PMSG_27__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_28 -#define MP0_C2PMSG_28__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_29 -#define MP0_C2PMSG_29__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_30 -#define MP0_C2PMSG_30__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_31 -#define MP0_C2PMSG_31__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_32 -#define MP0_C2PMSG_32__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_33 -#define MP0_C2PMSG_33__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_34 -#define MP0_C2PMSG_34__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_35 -#define MP0_C2PMSG_35__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_36 -#define MP0_C2PMSG_36__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_37 -#define MP0_C2PMSG_37__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_38 -#define MP0_C2PMSG_38__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_39 -#define MP0_C2PMSG_39__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_40 -#define MP0_C2PMSG_40__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_41 -#define MP0_C2PMSG_41__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_42 -#define MP0_C2PMSG_42__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_43 -#define MP0_C2PMSG_43__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_44 -#define MP0_C2PMSG_44__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_45 -#define MP0_C2PMSG_45__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_46 -#define MP0_C2PMSG_46__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_47 -#define MP0_C2PMSG_47__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_48 -#define MP0_C2PMSG_48__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_49 -#define MP0_C2PMSG_49__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_50 -#define MP0_C2PMSG_50__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_51 -#define MP0_C2PMSG_51__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_52 -#define MP0_C2PMSG_52__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_53 -#define MP0_C2PMSG_53__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_54 -#define MP0_C2PMSG_54__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_55 -#define MP0_C2PMSG_55__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_56 -#define MP0_C2PMSG_56__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_57 -#define MP0_C2PMSG_57__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_58 -#define MP0_C2PMSG_58__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_59 -#define MP0_C2PMSG_59__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_60 -#define MP0_C2PMSG_60__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_61 -#define MP0_C2PMSG_61__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_62 -#define MP0_C2PMSG_62__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_63 -#define MP0_C2PMSG_63__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_64 -#define MP0_C2PMSG_64__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_65 -#define MP0_C2PMSG_65__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_66 -#define MP0_C2PMSG_66__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_67 -#define MP0_C2PMSG_67__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_68 -#define MP0_C2PMSG_68__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_69 -#define MP0_C2PMSG_69__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_70 -#define MP0_C2PMSG_70__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_71 -#define MP0_C2PMSG_71__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_72 -#define MP0_C2PMSG_72__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_73 -#define MP0_C2PMSG_73__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_74 -#define MP0_C2PMSG_74__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_75 -#define MP0_C2PMSG_75__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_76 -#define MP0_C2PMSG_76__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_77 -#define MP0_C2PMSG_77__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_78 -#define MP0_C2PMSG_78__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_79 -#define MP0_C2PMSG_79__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_80 -#define MP0_C2PMSG_80__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_81 -#define MP0_C2PMSG_81__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_82 -#define MP0_C2PMSG_82__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_83 -#define MP0_C2PMSG_83__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_84 -#define MP0_C2PMSG_84__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_85 -#define MP0_C2PMSG_85__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_86 -#define MP0_C2PMSG_86__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_87 -#define MP0_C2PMSG_87__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_88 -#define MP0_C2PMSG_88__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_89 -#define MP0_C2PMSG_89__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_90 -#define MP0_C2PMSG_90__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_91 -#define MP0_C2PMSG_91__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_92 -#define MP0_C2PMSG_92__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_93 -#define MP0_C2PMSG_93__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_94 -#define MP0_C2PMSG_94__CONTENT_MASK 0xffffffffL - -// MP0_C2PMSG_95 -#define MP0_C2PMSG_95__CONTENT_MASK 0xffffffffL - -// MP0_P2CMSG_0 -#define MP0_P2CMSG_0__CONTENT_MASK 0xffffffffL - -// MP0_P2CMSG_1 -#define MP0_P2CMSG_1__CONTENT_MASK 0xffffffffL - -// MP0_P2CMSG_2 -#define MP0_P2CMSG_2__CONTENT_MASK 0xffffffffL - -// MP0_P2CMSG_3 -#define MP0_P2CMSG_3__CONTENT_MASK 0xffffffffL - -// MP0_P2CMSG_INTEN -#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000fL - -// MP0_P2CMSG_INTSTS -#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L - -// MP0_C2PMSG_ATTR_0 -#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xffffffffL - -// MP0_C2PMSG_ATTR_1 -#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xffffffffL - -// MP0_C2PMSG_ATTR_2 -#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xffffffffL - -// MP0_C2PMSG_ATTR_3 -#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xffffffffL - -// MP0_C2PMSG_ATTR_4 -#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xffffffffL - -// MP0_C2PMSG_ATTR_5 -#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xffffffffL - -// MP0_P2CMSG_ATTR -#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000ffL - -// MP0_P2SMSG_0 -#define MP0_P2SMSG_0__CONTENT_MASK 0xffffffffL - -// MP0_P2SMSG_1 -#define MP0_P2SMSG_1__CONTENT_MASK 0xffffffffL - -// MP0_P2SMSG_2 -#define MP0_P2SMSG_2__CONTENT_MASK 0xffffffffL - -// MP0_P2SMSG_3 -#define MP0_P2SMSG_3__CONTENT_MASK 0xffffffffL - -// MP0_P2SMSG_ATTR -#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000ffL - -// MP0_S2PMSG_ATTR -#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L - -// MP0_P2SMSG_INTSTS -#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L - -// MP0_S2PMSG_0 -#define MP0_S2PMSG_0__CONTENT_MASK 0xffffffffL - -// MP0_PUB_RSMU_HCID -#define MP0_PUB_RSMU_HCID__HwRev_MASK 0x0000003fL -#define MP0_PUB_RSMU_HCID__HwMinVer_MASK 0x00001fc0L -#define MP0_PUB_RSMU_HCID__HwMajVer_MASK 0x000fe000L -#define MP0_PUB_RSMU_HCID__HwID_MASK 0xfff00000L - -// MP0_PUB_RSMU_SIID -#define MP0_PUB_RSMU_SIID__SwIfRev_MASK 0x0000003fL -#define MP0_PUB_RSMU_SIID__SwIfMinVer_MASK 0x00001fc0L -#define MP0_PUB_RSMU_SIID__SwIfMajVer_MASK 0x000fe000L -#define MP0_PUB_RSMU_SIID__SwIfID_MASK 0xfff00000L - -// MP0_SAM_IH_EXT_ERR_INTR -#define MP0_SAM_IH_EXT_ERR_INTR__UVD_MASK 0x00000001L -#define MP0_SAM_IH_EXT_ERR_INTR__VCE_MASK 0x00000002L -#define MP0_SAM_IH_EXT_ERR_INTR__ISP_MASK 0x00000004L -#define MP0_SAM_IH_EXT_ERR_INTR__VP8_MASK 0x00000008L - -// MP0_SAM_IH_EXT_ERR_INTR_STATUS -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK 0x00000001L -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x00000002L -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK 0x00000004L -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__VP8_MASK 0x00000008L - -// MP0_REVID -#define MP0_REVID__REVID_MASK 0xffffffffL - -// MP0_RSMU_HCID -#define MP0_RSMU_HCID__HwRev_MASK 0x0000003fL -#define MP0_RSMU_HCID__HwMinVer_MASK 0x00001fc0L -#define MP0_RSMU_HCID__HwMajVer_MASK 0x000fe000L -#define MP0_RSMU_HCID__HwID_MASK 0xfff00000L - -// MP0_RSMU_SIID -#define MP0_RSMU_SIID__SwIfRev_MASK 0x0000003fL -#define MP0_RSMU_SIID__SwIfMinVer_MASK 0x00001fc0L -#define MP0_RSMU_SIID__SwIfMajVer_MASK 0x000fe000L -#define MP0_RSMU_SIID__SwIfID_MASK 0xfff00000L - -// MP0_RAM_REPAIR_DONE -#define MP0_RAM_REPAIR_DONE__STATUS_MASK 0xffffffffL - -// MP0_RAM_REPAIR_RESULT -#define MP0_RAM_REPAIR_RESULT__PASS_MASK 0xffffffffL - -// MP0_FUSE_HARVESTING -#define MP0_FUSE_HARVESTING__DATA_MASK 0xffffffffL - -// MP0_FUSE_RMBITS -#define MP0_FUSE_RMBITS__RM_MASK 0x000001ffL -#define MP0_FUSE_RMBITS__RM_RESERVED_MASK 0x0000fe00L -#define MP0_FUSE_RMBITS__BC_MASK 0x003f0000L -#define MP0_FUSE_RMBITS__BC_RESERVED_MASK 0xffc00000L - -// MP0_SMS_CFG -#define MP0_SMS_CFG__SMS_RESETB_MASK 0x00000001L -#define MP0_SMS_CFG__RUN_BIHR_MASK 0x00000100L -#define MP0_SMS_CFG__RUN_MBIST_MASK 0x00000200L -#define MP0_SMS_CFG__SMS_FUSE_VALID_MASK 0x00010000L -#define MP0_SMS_CFG__SMS_NEXT_FETCH_MASK 0x01000000L -#define MP0_SMS_CFG__RAM_REPAIR_DONE_MASK 0x02000000L -#define MP0_SMS_CFG__RAM_BIST_FAIL_MASK 0x04000000L - -// MP0_FUSE_SMS_0 -#define MP0_FUSE_SMS_0__DATA_MASK 0xffffffffL - -// MP0_FUSE_SMS_1 -#define MP0_FUSE_SMS_1__DATA_MASK 0xffffffffL - -// MP0_FUSE_SMS_2 -#define MP0_FUSE_SMS_2__DATA_MASK 0xffffffffL - -// MP0_FUSE_SMS_3 -#define MP0_FUSE_SMS_3__DATA_MASK 0xffffffffL - -// MP0_FUSE_SMS_4 -#define MP0_FUSE_SMS_4__DATA_MASK 0xffffffffL - -// MP0_FUSE_SMS_5 -#define MP0_FUSE_SMS_5__DATA_MASK 0xffffffffL - -// MP0_FUSE_SMS_6 -#define MP0_FUSE_SMS_6__DATA_MASK 0xffffffffL - -// MP0_FUSE_SMS_7 -#define MP0_FUSE_SMS_7__DATA_MASK 0xffffffffL - -// MP0_ACC_VIO_INTSTS -#define MP0_ACC_VIO_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_ACC_VIO_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_ACC_VIO_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_ACC_VIO_INTSTS__INTSTS3_MASK 0x00000008L -#define MP0_ACC_VIO_INTSTS__INTSTS4_MASK 0x00000010L -#define MP0_ACC_VIO_INTSTS__INTSTS5_MASK 0x00000020L -#define MP0_ACC_VIO_INTSTS__INTSTS6_MASK 0x00000040L -#define MP0_ACC_VIO_INTSTS__INTSTS7_MASK 0x00000080L -#define MP0_ACC_VIO_INTSTS__INTSTS8_MASK 0x00000100L -#define MP0_ACC_VIO_INTSTS__INTSTS9_MASK 0x00000200L -#define MP0_ACC_VIO_INTSTS__INTSTS10_MASK 0x00000400L -#define MP0_ACC_VIO_INTSTS__INTSTS11_MASK 0x00000800L -#define MP0_ACC_VIO_INTSTS__INTSTS12_MASK 0x00001000L -#define MP0_ACC_VIO_INTSTS__INTSTS13_MASK 0x00002000L -#define MP0_ACC_VIO_INTSTS__INTSTS14_MASK 0x00004000L -#define MP0_ACC_VIO_INTSTS__INTSTS15_MASK 0x00008000L -#define MP0_ACC_VIO_INTSTS__INTSTS16_MASK 0x00010000L -#define MP0_ACC_VIO_INTSTS__INTSTS17_MASK 0x00020000L -#define MP0_ACC_VIO_INTSTS__INTSTS18_MASK 0x00040000L -#define MP0_ACC_VIO_INTSTS__INTSTS19_MASK 0x00080000L -#define MP0_ACC_VIO_INTSTS__INTSTS20_MASK 0x00100000L -#define MP0_ACC_VIO_INTSTS__INTSTS21_MASK 0x00200000L -#define MP0_ACC_VIO_INTSTS__INTSTS22_MASK 0x00400000L -#define MP0_ACC_VIO_INTSTS__INTSTS23_MASK 0x00800000L -#define MP0_ACC_VIO_INTSTS__INTSTS24_MASK 0x01000000L -#define MP0_ACC_VIO_INTSTS__INTSTS25_MASK 0x02000000L -#define MP0_ACC_VIO_INTSTS__INTSTS26_MASK 0x04000000L -#define MP0_ACC_VIO_INTSTS__INTSTS27_MASK 0x08000000L -#define MP0_ACC_VIO_INTSTS__INTSTS28_MASK 0x10000000L -#define MP0_ACC_VIO_INTSTS__INTSTS29_MASK 0x20000000L -#define MP0_ACC_VIO_INTSTS__INTSTS30_MASK 0x40000000L -#define MP0_ACC_VIO_INTSTS__INTSTS31_MASK 0x80000000L - -// MP0_TDR_MISC0_STATUS -#define MP0_TDR_MISC0_STATUS__DATA_MASK 0xffffffffL - -// MP0_FW_OVERRIDE -#define MP0_FW_OVERRIDE__FORCE_SS_NOTR_MASK 0x00000001L -#define MP0_FW_OVERRIDE__RESERVED_MASK 0xfffffffeL - -// MP0_BOOTROM_REVID -#define MP0_BOOTROM_REVID__REVID_MASK 0xffffffffL - -// MP0_CRU_CPU_CTRL_STS -#define MP0_CRU_CPU_CTRL_STS__EVENTI_MASK 0x00000001L -#define MP0_CRU_CPU_CTRL_STS__EVENTO_MASK 0x00000002L -#define MP0_CRU_CPU_CTRL_STS__TEINIT_MASK 0x00000004L -#define MP0_CRU_CPU_CTRL_STS__CP15SDISABLE_MASK 0x00000008L -#define MP0_CRU_CPU_CTRL_STS__L1RSTDISABLE_MASK 0x00000010L -#define MP0_CRU_CPU_CTRL_STS__PCLKENDBG_MASK 0x00000020L -#define MP0_CRU_CPU_CTRL_STS__CLUSTERID_MASK 0x000003c0L - -// MP0_SFUSE_SEC -#define MP0_SFUSE_SEC__CPU_DBG_SEL_MASK 0x00000001L -#define MP0_SFUSE_SEC__DATA_MASK 0xfffffffeL - -// MP0_COLD_BOOT_EVENTS -#define MP0_COLD_BOOT_EVENTS__COLD_BOOT_SEQ_DONE_MASK 0x00000001L -#define MP0_COLD_BOOT_EVENTS__RESERVED_MASK 0xfffffffeL - -// MP0_WARM_BOOT_EVENTS -#define MP0_WARM_BOOT_EVENTS__WARM_BOOT_SEQ_DONE_MASK 0x00000001L -#define MP0_WARM_BOOT_EVENTS__RESERVED_MASK 0xfffffffeL - -// MP0_NSWORLD_P2CMSG_INTR_CTRL -#define MP0_NSWORLD_P2CMSG_INTR_CTRL__P2CMSG_INTEN_NSENB_MASK 0x0000000fL - -// MP0_NSWORLD_P2CMSG_CTRL -#define MP0_NSWORLD_P2CMSG_CTRL__P2CMSG_NSENB_MASK 0x0000000fL - -// MP0_NSWORLD_C2PMSG_CTRL -#define MP0_NSWORLD_C2PMSG_CTRL__C2PMSG_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_C2PMSG_CTRL_1 -#define MP0_NSWORLD_C2PMSG_CTRL_1__C2PMSG_NSENB_1_MASK 0xffffffffL - -// MP0_NSWORLD_C2PMSG_CTRL_2 -#define MP0_NSWORLD_C2PMSG_CTRL_2__C2PMSG_NSENB_2_MASK 0xffffffffL - -// MP0_NSWORLD_P2SMSG_CTRL -#define MP0_NSWORLD_P2SMSG_CTRL__P2SMSG_NSENB_MASK 0x0000000fL - -// MP0_NSWORLD_S2PMSG_CTRL -#define MP0_NSWORLD_S2PMSG_CTRL__S2PMSG_NSENB_MASK 0x00000001L - -// MP0_NSWORLD_PIC0_CTRL_0 -#define MP0_NSWORLD_PIC0_CTRL_0__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_PIC0_CTRL_1 -#define MP0_NSWORLD_PIC0_CTRL_1__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_PIC0_CTRL_2 -#define MP0_NSWORLD_PIC0_CTRL_2__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_PIC0_CTRL_3 -#define MP0_NSWORLD_PIC0_CTRL_3__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_PIC1_CTRL_0 -#define MP0_NSWORLD_PIC1_CTRL_0__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_PIC1_CTRL_1 -#define MP0_NSWORLD_PIC1_CTRL_1__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_PIC1_CTRL_2 -#define MP0_NSWORLD_PIC1_CTRL_2__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_PIC1_CTRL_3 -#define MP0_NSWORLD_PIC1_CTRL_3__PIC_NSENB_MASK 0xffffffffL - -// MP0_NSWORLD_TIMER_CTRL -#define MP0_NSWORLD_TIMER_CTRL__TIMER_0_NSENB_MASK 0x00000001L -#define MP0_NSWORLD_TIMER_CTRL__TIMER_1_NSENB_MASK 0x00000002L -#define MP0_NSWORLD_TIMER_CTRL__TIMER_2_NSENB_MASK 0x00000004L -#define MP0_NSWORLD_TIMER_CTRL__TIMER_3_NSENB_MASK 0x00000008L - -// MP0_EVCNTCTL -#define MP0_EVCNTCTL__EVENTCNT_EN_MASK 0x00000001L -#define MP0_EVCNTCTL__EVENTCNT_RSTB_MASK 0x00000002L -#define MP0_EVCNTCTL__EVENTCNT_SHADOW_MASK 0x00000004L - -// MP0_EVCNTSEL -#define MP0_EVCNTSEL__EVENT0_BLK_MASK 0x0000003fL -#define MP0_EVCNTSEL__EVENT0_SEL_MASK 0x00003f00L -#define MP0_EVCNTSEL__EVENT1_BLK_MASK 0x003f0000L -#define MP0_EVCNTSEL__EVENT1_SEL_MASK 0x3f000000L - -// MP0_EVCNT0 -#define MP0_EVCNT0__EVENTCNT0_MASK 0xffffffffL - -// MP0_EVCNT1 -#define MP0_EVCNT1__EVENTCNT1_MASK 0xffffffffL - -// MP0_EVCNTHI -#define MP0_EVCNTHI__EVENTCNT0_HI_MASK 0x000000ffL -#define MP0_EVCNTHI__EVENTCNT1_HI_MASK 0x00ff0000L - -// MP0_J2P_MBOX0 -#define MP0_J2P_MBOX0__MBX_MASK 0xffffffffL - -// MP0_J2P_MBOX1 -#define MP0_J2P_MBOX1__MBX_MASK 0xffffffffL - -// MP0_J2P_ATTR -#define MP0_J2P_ATTR__J2P_ATTR_MASK 0x00000003L - -// MP0_CRU_ACC_VIO_INTSTS -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS3_MASK 0x00000008L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS4_MASK 0x00000010L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS5_MASK 0x00000020L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS6_MASK 0x00000040L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS7_MASK 0x00000080L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS8_MASK 0x00000100L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS9_MASK 0x00000200L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS10_MASK 0x00000400L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS11_MASK 0x00000800L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS12_MASK 0x00001000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS13_MASK 0x00002000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS14_MASK 0x00004000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS15_MASK 0x00008000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS16_MASK 0x00010000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS17_MASK 0x00020000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS18_MASK 0x00040000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS19_MASK 0x00080000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS20_MASK 0x00100000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS21_MASK 0x00200000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS22_MASK 0x00400000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS23_MASK 0x00800000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS24_MASK 0x01000000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS25_MASK 0x02000000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS26_MASK 0x04000000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS27_MASK 0x08000000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS28_MASK 0x10000000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS29_MASK 0x20000000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS30_MASK 0x40000000L -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS31_MASK 0x80000000L - -// MP0_ACC_VIOL_LOG0 -#define MP0_ACC_VIOL_LOG0__AXI_ACC_VIO_LOG_MASK 0x7fffffffL -#define MP0_ACC_VIOL_LOG0__AXI_LOG_CLEAR_MASK 0x80000000L - -// MP0_ACC_VIOL_LOG1 -#define MP0_ACC_VIOL_LOG1__AXI_ACC_VIO_ADDR_MASK 0xffffffffL - -// MP0_SEC_SCRATCH0 -#define MP0_SEC_SCRATCH0__DATA_MASK 0xffffffffL - -// MP0_SEC_SCRATCH1 -#define MP0_SEC_SCRATCH1__DATA_MASK 0xffffffffL - -// MP0_SEC_SCRATCH2 -#define MP0_SEC_SCRATCH2__DATA_MASK 0xffffffffL - -// MP0_SEC_SCRATCH3 -#define MP0_SEC_SCRATCH3__DATA_MASK 0xffffffffL - -// MP0_STICKY -#define MP0_STICKY__DATA_MASK 0xffffffffL - -// MP0_CRU_MISC_CTRL -#define MP0_CRU_MISC_CTRL__ERROR_RESPONSE_ON_ACCVIOL_MASK 0x00000001L - -// MP0_SOFT_RESET_CTRL -#define MP0_SOFT_RESET_CTRL__MP_MMU_RESET_MASK 0x00000001L -#define MP0_SOFT_RESET_CTRL__MP_CPU_RESET_MASK 0x00000002L -#define MP0_SOFT_RESET_CTRL__MP_SMNIF_RESET_MASK 0x00000004L -#define MP0_SOFT_RESET_CTRL__MP_ROM_RESET_MASK 0x00000008L -#define MP0_SOFT_RESET_CTRL__MP_DAP_RESET_MASK 0x00000010L -#define MP0_SOFT_RESET_CTRL__MP_DRM_RESET_MASK 0x00000020L -#define MP0_SOFT_RESET_CTRL__MP_SHUBIF_RESET_MASK 0x00000100L -#define MP0_SOFT_RESET_CTRL__MP_MHUBIF_RESET_MASK 0x00000200L - -// MP0_NS_PROT_FAULT_STATUS_0 -#define MP0_NS_PROT_FAULT_STATUS_0__MMU_CFG_NS0_VIOL_MASK 0x00000001L -#define MP0_NS_PROT_FAULT_STATUS_0__MMU_SRAM_NS0_VIOL_MASK 0x00000002L -#define MP0_NS_PROT_FAULT_STATUS_0__ROM_NS0_VIOL_MASK 0x00000004L -#define MP0_NS_PROT_FAULT_STATUS_0__ROM_CFG_NS0_VIOL_MASK 0x00000008L -#define MP0_NS_PROT_FAULT_STATUS_0__CRU_NS0_VIOL_MASK 0x00000010L - -// MP0_FW_STATUS -#define MP0_FW_STATUS__FW_STATUS_MASK 0xffffffffL - -// MP0_ROM_FW_CNTL -#define MP0_ROM_FW_CNTL__ROM_FW_FLOW_CNTL_MASK 0xffffffffL - -// MP0_FW_MISC_CTRL -#define MP0_FW_MISC_CTRL__MP_FW_VALUE_MASK 0xffffffffL - -// MP0_AEB_STATUS_0 -#define MP0_AEB_STATUS_0__MP0_AEB_DBG_BUS_en_MASK 0x00000001L -#define MP0_AEB_STATUS_0__MP0_AEB_CPU_DBG_TDRs_en_MASK 0x00000002L -#define MP0_AEB_STATUS_0__MP0_AEB_JTAG_AXI_master_en_MASK 0x00000004L -#define MP0_AEB_STATUS_0__MP0_AEB_ROM_content_visible_en_MASK 0x00000008L -#define MP0_AEB_STATUS_0__MP0_AEB_ROM_keys_visible_en_MASK 0x00000010L -#define MP0_AEB_STATUS_0__MP0_AEB_SCAN_DUMP_en_MASK 0x00000020L - -// MP0_AEB_STATUS_1 -#define MP0_AEB_STATUS_1__MP1_AEB_DBG_BUS_en_MASK 0x00000001L -#define MP0_AEB_STATUS_1__MP1_AEB_CPU_DBG_TDRs_en_MASK 0x00000002L -#define MP0_AEB_STATUS_1__MP1_AEB_JTAG_AXI_master_en_MASK 0x00000004L -#define MP0_AEB_STATUS_1__MP1_AEB_SCAN_DUMP_en_MASK 0x00000008L - -// MP0_AEB_JTAG_DBG_CTRL -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_DBG_BUS_en_MASK 0x00000001L -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_CPU_DBG_TDRs_en_MASK 0x00000002L -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_JTAG_AXI_master_en_MASK 0x00000004L -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_SCAN_DUMP_en_MASK 0x00000008L - -// MP0_AEB_JTAG_DBG_CTRL_LOCK -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_DBG_BUS_en_MASK 0x00000001L -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_CPU_DBG_TDRs_en_MASK 0x00000002L -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_JTAG_AXI_master_en_MASK 0x00000004L -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_SCAN_DUMP_en_MASK 0x00000008L - -// MP0_AEB_CNTL_0 -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_DBG_BUS_en_MASK 0x00000001L -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_CPU_DBG_TDRs_en_MASK 0x00000002L -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_JTAG_AXI_master_en_MASK 0x00000004L -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_ROM_content_visible_en_MASK 0x00000008L -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_ROM_keys_visible_en_MASK 0x00000010L -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_SCAN_DUMP_en_MASK 0x00000020L - -// MP0_AEB_CNTL_1 -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_DBG_BUS_en_MASK 0x00000001L -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_CPU_DBG_TDRs_en_MASK 0x00000002L -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_JTAG_AXI_master_en_MASK 0x00000004L -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_SCAN_DUMP_en_MASK 0x00000008L - -// MP0_PIC0_LEVEL_0 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_LEVEL_1 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_LEVEL_2 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_LEVEL_3 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_EDGE_0 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_EDGE_1 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_EDGE_2 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_EDGE_3 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC0_PRIORITY_0 -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_1 -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_2 -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_3 -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_4 -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_5 -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_6 -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_7 -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_8 -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_9 -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_10 -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_11 -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_12 -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_13 -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_14 -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_15 -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_16 -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_17 -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_18 -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_19 -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_20 -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_21 -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_22 -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_23 -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_24 -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_25 -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_26 -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_27 -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_28 -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_29 -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_30 -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC0_PRIORITY_31 -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_LEVEL_0 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_LEVEL_1 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_LEVEL_2 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_LEVEL_3 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_EDGE_0 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_EDGE_1 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_EDGE_2 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_EDGE_3 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_0_MASK 0x00000001L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_1_MASK 0x00000002L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_2_MASK 0x00000004L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_3_MASK 0x00000008L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_4_MASK 0x00000010L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_5_MASK 0x00000020L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_6_MASK 0x00000040L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_7_MASK 0x00000080L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_8_MASK 0x00000100L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_9_MASK 0x00000200L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_10_MASK 0x00000400L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_11_MASK 0x00000800L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_12_MASK 0x00001000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_13_MASK 0x00002000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_14_MASK 0x00004000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_15_MASK 0x00008000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_16_MASK 0x00010000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_17_MASK 0x00020000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_18_MASK 0x00040000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_19_MASK 0x00080000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_20_MASK 0x00100000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_21_MASK 0x00200000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_22_MASK 0x00400000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_23_MASK 0x00800000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_24_MASK 0x01000000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_25_MASK 0x02000000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_26_MASK 0x04000000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_27_MASK 0x08000000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_28_MASK 0x10000000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_29_MASK 0x20000000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_30_MASK 0x40000000L -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_31_MASK 0x80000000L - -// MP0_PIC1_PRIORITY_0 -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_1 -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_2 -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_3 -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_4 -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_5 -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_6 -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_7 -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_8 -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_9 -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_10 -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_11 -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_12 -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_13 -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_14 -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_15 -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_16 -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_17 -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_18 -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_19 -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_20 -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_21 -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_22 -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_23 -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_24 -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_25 -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_26 -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_27 -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_28 -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_29 -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_30 -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_PIC1_PRIORITY_31 -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_3_MASK 0xff000000L - -// MP0_SAM_IH_EXT_ERR_INTR_ACK -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__UVD_MASK 0x00000001L -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__VCE_MASK 0x00000002L -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__ISP_MASK 0x00000004L -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__VP8_MASK 0x00000008L - -// MP0_RSMU_SECINTR_FETCH0 -#define MP0_RSMU_SECINTR_FETCH0__UNIT_ID_MASK 0x0000003fL -#define MP0_RSMU_SECINTR_FETCH0__INIT_ID_MASK 0x00003fc0L - -// MP0_RSMU_SECINTR_FETCH1 -#define MP0_RSMU_SECINTR_FETCH1__WDATA_MASK 0xffffffffL - -// MP0_RSMU_SECINTR_STATUS -#define MP0_RSMU_SECINTR_STATUS__IFIFO_COUNT_MASK 0x0000003fL -#define MP0_RSMU_SECINTR_STATUS__DFIFO_COUNT_MASK 0x00003f00L -#define MP0_RSMU_SECINTR_STATUS__FIFO_NOTEMPTY_MASK 0x00010000L -#define MP0_RSMU_SECINTR_STATUS__FIFO_HALF_MASK 0x00020000L -#define MP0_RSMU_SECINTR_STATUS__FIFO_FULL_MASK 0x00040000L - -// MP0_RSMU_SECINTR_FLUSH0 -#define MP0_RSMU_SECINTR_FLUSH0__RESERVED_MASK 0xffffffffL - -// MP0_RSMU_SECINTR_FLUSH1 -#define MP0_RSMU_SECINTR_FLUSH1__RESERVED_MASK 0xffffffffL - -// MP0_RSMU_SECINTR_CTRL -#define MP0_RSMU_SECINTR_CTRL__FIFO_SELECT_MASK 0x00000003L -#define MP0_RSMU_SECINTR_CTRL__CLR_OFCNT_MASK 0x00000004L - -// MP0_RSMU_SECINTR_OFCNT -#define MP0_RSMU_SECINTR_OFCNT__OFCNT_MASK 0xffffffffL - -// MP0_SMN_SAM_IH_EXT_ERR_INTR -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__UVD_MASK 0x00000001L -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__VCE_MASK 0x00000002L -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__ISP_MASK 0x00000004L -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__VP8_MASK 0x00000008L - -// MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK 0x00000001L -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x00000002L -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK 0x00000004L -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__VP8_MASK 0x00000008L - -// MP0_SMN_C2PMSG_32 -#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_33 -#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_34 -#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_35 -#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_36 -#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_37 -#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_38 -#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_39 -#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_40 -#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_41 -#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_42 -#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_43 -#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_44 -#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_45 -#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_46 -#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_47 -#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_48 -#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_49 -#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_50 -#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_51 -#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_52 -#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_53 -#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_54 -#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_55 -#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_56 -#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_57 -#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_58 -#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_59 -#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_60 -#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_61 -#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_62 -#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_63 -#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_64 -#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_65 -#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_66 -#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_67 -#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_68 -#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_69 -#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_70 -#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_71 -#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_72 -#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_73 -#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_74 -#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_75 -#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_76 -#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_77 -#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_78 -#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_79 -#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_80 -#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_81 -#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_82 -#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_83 -#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_84 -#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_85 -#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_86 -#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_87 -#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_88 -#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_89 -#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_90 -#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_91 -#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_92 -#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_93 -#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_94 -#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xffffffffL - -// MP0_SMN_C2PMSG_95 -#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xffffffffL - -// MP0_RSMU_PUB_RSMU_HCID -#define MP0_RSMU_PUB_RSMU_HCID__HwRev_MASK 0x0000003fL -#define MP0_RSMU_PUB_RSMU_HCID__HwMinVer_MASK 0x00001fc0L -#define MP0_RSMU_PUB_RSMU_HCID__HwMajVer_MASK 0x000fe000L -#define MP0_RSMU_PUB_RSMU_HCID__HwID_MASK 0xfff00000L - -// MP0_RSMU_PUB_RSMU_SIID -#define MP0_RSMU_PUB_RSMU_SIID__SwIfRev_MASK 0x0000003fL -#define MP0_RSMU_PUB_RSMU_SIID__SwIfMinVer_MASK 0x00001fc0L -#define MP0_RSMU_PUB_RSMU_SIID__SwIfMajVer_MASK 0x000fe000L -#define MP0_RSMU_PUB_RSMU_SIID__SwIfID_MASK 0xfff00000L - -// MP0_MMU_SRAM_FLOP_START_ADDR -#define MP0_MMU_SRAM_FLOP_START_ADDR__VALUE_MASK 0xffffffffL - -// MP0_MMU_SRAM_ACC_VIOLATION_LOG_ADDR -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_ADDR__ADDRESS_MASK 0xffffffffL - -// MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_UNSECURE_BAR_MASK 0x00000002L -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_OP_MASK 0x00000008L -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE_MASK 0x00000030L -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_PERMISSION_MASK 0x000000c0L -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_UNIT_ID_MASK 0x00003f00L -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_INIT_ID_MASK 0x003fc000L -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR_MASK 0x00400000L - -// MP0_MMU_MISC_CNTL -#define MP0_MMU_MISC_CNTL__ALLOW_UNPRIVILIGED_REG_ACC_MASK 0x00000001L -#define MP0_MMU_MISC_CNTL__RETURN_ERR_ON_VIOLATED_READ_MASK 0x00000002L -#define MP0_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_PSRAM_MASK 0x00000004L -#define MP0_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_CPU_MASK 0x00000008L -#define MP0_MMU_MISC_CNTL__ENABLE_RAM_FLOPS_MASK 0x00000010L -#define MP0_MMU_MISC_CNTL__RESERVED2_MASK 0x000000e0L -#define MP0_MMU_MISC_CNTL__MEM_SLEEP_TIMEOUT_MASK 0x0000ff00L -#define MP0_MMU_MISC_CNTL__CLK_GATE_EN_MASK 0x00010000L -#define MP0_MMU_MISC_CNTL__CLK_GATE_OVERRIDE_MASK 0x00020000L -#define MP0_MMU_MISC_CNTL__CLK_GATE_TIMEOUT_MASK 0x003c0000L -#define MP0_MMU_MISC_CNTL__REGCLK_STATUS_MASK 0x00400000L -#define MP0_MMU_MISC_CNTL__SYSCLK_STATUS_MASK 0x00800000L -#define MP0_MMU_MISC_CNTL__MEM_DEEP_SLEEP_EN_MASK 0x01000000L -#define MP0_MMU_MISC_CNTL__MEM_DEEP_SLEEP_STATUS_MASK 0x02000000L -#define MP0_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_EN_MASK 0x04000000L -#define MP0_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_STATUS_MASK 0x08000000L -#define MP0_MMU_MISC_CNTL__MEM_PG_DLY_MASK 0xf0000000L - -// MP0_MMU_ACCESS_ERR_LOG -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_BLOCK_MASK 0x00000006L -#define MP0_MMU_ACCESS_ERR_LOG__ACC_VIOLATION_LOG_CLEAR_MASK 0x00000008L -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_UNIT_ID_MASK 0x00003f00L -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_INIT_ID_MASK 0x003fc000L -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_PROT_MASK 0x01c00000L - -// MP0_MMU_SRAM_UNSECURE_BAR -#define MP0_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR_MASK 0x0003ffffL -#define MP0_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR_LOCK_MASK 0x02000000L - -// MP0_MMU_SCRATCH_0 -#define MP0_MMU_SCRATCH_0__RESERVED_MASK 0xffffffffL - -// MP0_MMU_SCRATCH_1 -#define MP0_MMU_SCRATCH_1__RESERVED_MASK 0xffffffffL - -// MP0_MMU_SCRATCH_2 -#define MP0_MMU_SCRATCH_2__RESERVED_MASK 0xffffffffL - -// MP0_MMU_SCRATCH_3 -#define MP0_MMU_SCRATCH_3__RESERVED_MASK 0xffffffffL - -// MP0_MMU_SCRATCH_4 -#define MP0_MMU_SCRATCH_4__RESERVED_MASK 0xffffffffL - -// MP0_MMU_SCRATCH_5 -#define MP0_MMU_SCRATCH_5__RESERVED_MASK 0xffffffffL - -// MP0_MMU_SCRATCH_6 -#define MP0_MMU_SCRATCH_6__RESERVED_MASK 0xffffffffL - -// MP0_MMU_SCRATCH_7 -#define MP0_MMU_SCRATCH_7__RESERVED_MASK 0xffffffffL - -// MP0_MCA_ACCESS_CNTL -#define MP0_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_EN_MASK 0x00000001L -#define MP0_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_RD_WR_SEL_MASK 0x00000002L -#define MP0_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_REG_SEL_MASK 0x0000007cL - -// MP0_MCA_ACCESS_WR_DATA -#define MP0_MCA_ACCESS_WR_DATA__MCA_ACCESS_WR_DATA_MASK 0xffffffffL - -// MP0_MCA_ACCESS_RD_DATA -#define MP0_MCA_ACCESS_RD_DATA__MCA_ACCESS_RD_DATA_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB0_1 -#define MP0_MMHUB_SOC_TLB0_1__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_2 -#define MP0_MMHUB_SOC_TLB0_2__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_3 -#define MP0_MMHUB_SOC_TLB0_3__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_4 -#define MP0_MMHUB_SOC_TLB0_4__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_5 -#define MP0_MMHUB_SOC_TLB0_5__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_6 -#define MP0_MMHUB_SOC_TLB0_6__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_7 -#define MP0_MMHUB_SOC_TLB0_7__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_8 -#define MP0_MMHUB_SOC_TLB0_8__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_9 -#define MP0_MMHUB_SOC_TLB0_9__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_10 -#define MP0_MMHUB_SOC_TLB0_10__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_11 -#define MP0_MMHUB_SOC_TLB0_11__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_12 -#define MP0_MMHUB_SOC_TLB0_12__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_13 -#define MP0_MMHUB_SOC_TLB0_13__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_14 -#define MP0_MMHUB_SOC_TLB0_14__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_15 -#define MP0_MMHUB_SOC_TLB0_15__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_16 -#define MP0_MMHUB_SOC_TLB0_16__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_17 -#define MP0_MMHUB_SOC_TLB0_17__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_18 -#define MP0_MMHUB_SOC_TLB0_18__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_19 -#define MP0_MMHUB_SOC_TLB0_19__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_20 -#define MP0_MMHUB_SOC_TLB0_20__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_21 -#define MP0_MMHUB_SOC_TLB0_21__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_22 -#define MP0_MMHUB_SOC_TLB0_22__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_23 -#define MP0_MMHUB_SOC_TLB0_23__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_24 -#define MP0_MMHUB_SOC_TLB0_24__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_25 -#define MP0_MMHUB_SOC_TLB0_25__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_26 -#define MP0_MMHUB_SOC_TLB0_26__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_27 -#define MP0_MMHUB_SOC_TLB0_27__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_28 -#define MP0_MMHUB_SOC_TLB0_28__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_29 -#define MP0_MMHUB_SOC_TLB0_29__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_30 -#define MP0_MMHUB_SOC_TLB0_30__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_31 -#define MP0_MMHUB_SOC_TLB0_31__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_32 -#define MP0_MMHUB_SOC_TLB0_32__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_33 -#define MP0_MMHUB_SOC_TLB0_33__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_34 -#define MP0_MMHUB_SOC_TLB0_34__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_35 -#define MP0_MMHUB_SOC_TLB0_35__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_36 -#define MP0_MMHUB_SOC_TLB0_36__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_37 -#define MP0_MMHUB_SOC_TLB0_37__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_38 -#define MP0_MMHUB_SOC_TLB0_38__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_39 -#define MP0_MMHUB_SOC_TLB0_39__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_40 -#define MP0_MMHUB_SOC_TLB0_40__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_41 -#define MP0_MMHUB_SOC_TLB0_41__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_42 -#define MP0_MMHUB_SOC_TLB0_42__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_43 -#define MP0_MMHUB_SOC_TLB0_43__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_44 -#define MP0_MMHUB_SOC_TLB0_44__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_45 -#define MP0_MMHUB_SOC_TLB0_45__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_46 -#define MP0_MMHUB_SOC_TLB0_46__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_47 -#define MP0_MMHUB_SOC_TLB0_47__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_48 -#define MP0_MMHUB_SOC_TLB0_48__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_49 -#define MP0_MMHUB_SOC_TLB0_49__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_50 -#define MP0_MMHUB_SOC_TLB0_50__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_51 -#define MP0_MMHUB_SOC_TLB0_51__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_52 -#define MP0_MMHUB_SOC_TLB0_52__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_53 -#define MP0_MMHUB_SOC_TLB0_53__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_54 -#define MP0_MMHUB_SOC_TLB0_54__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_55 -#define MP0_MMHUB_SOC_TLB0_55__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_56 -#define MP0_MMHUB_SOC_TLB0_56__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_57 -#define MP0_MMHUB_SOC_TLB0_57__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_58 -#define MP0_MMHUB_SOC_TLB0_58__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_59 -#define MP0_MMHUB_SOC_TLB0_59__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_60 -#define MP0_MMHUB_SOC_TLB0_60__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_61 -#define MP0_MMHUB_SOC_TLB0_61__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB0_62 -#define MP0_MMHUB_SOC_TLB0_62__SOC_ADDR_MASK 0x003fffffL - -// MP0_MMHUB_SOC_TLB1_1 -#define MP0_MMHUB_SOC_TLB1_1__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_1__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_1__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_2 -#define MP0_MMHUB_SOC_TLB1_2__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_2__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_2__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_3 -#define MP0_MMHUB_SOC_TLB1_3__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_3__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_3__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_4 -#define MP0_MMHUB_SOC_TLB1_4__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_4__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_4__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_5 -#define MP0_MMHUB_SOC_TLB1_5__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_5__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_5__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_6 -#define MP0_MMHUB_SOC_TLB1_6__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_6__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_6__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_7 -#define MP0_MMHUB_SOC_TLB1_7__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_7__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_7__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_8 -#define MP0_MMHUB_SOC_TLB1_8__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_8__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_8__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_9 -#define MP0_MMHUB_SOC_TLB1_9__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_9__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_9__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_10 -#define MP0_MMHUB_SOC_TLB1_10__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_10__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_10__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_11 -#define MP0_MMHUB_SOC_TLB1_11__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_11__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_11__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_12 -#define MP0_MMHUB_SOC_TLB1_12__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_12__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_12__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_13 -#define MP0_MMHUB_SOC_TLB1_13__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_13__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_13__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_14 -#define MP0_MMHUB_SOC_TLB1_14__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_14__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_14__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_15 -#define MP0_MMHUB_SOC_TLB1_15__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_15__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_15__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_16 -#define MP0_MMHUB_SOC_TLB1_16__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_16__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_16__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_17 -#define MP0_MMHUB_SOC_TLB1_17__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_17__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_17__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_18 -#define MP0_MMHUB_SOC_TLB1_18__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_18__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_18__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_19 -#define MP0_MMHUB_SOC_TLB1_19__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_19__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_19__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_20 -#define MP0_MMHUB_SOC_TLB1_20__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_20__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_20__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_21 -#define MP0_MMHUB_SOC_TLB1_21__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_21__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_21__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_22 -#define MP0_MMHUB_SOC_TLB1_22__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_22__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_22__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_23 -#define MP0_MMHUB_SOC_TLB1_23__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_23__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_23__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_24 -#define MP0_MMHUB_SOC_TLB1_24__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_24__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_24__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_25 -#define MP0_MMHUB_SOC_TLB1_25__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_25__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_25__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_26 -#define MP0_MMHUB_SOC_TLB1_26__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_26__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_26__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_27 -#define MP0_MMHUB_SOC_TLB1_27__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_27__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_27__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_28 -#define MP0_MMHUB_SOC_TLB1_28__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_28__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_28__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_29 -#define MP0_MMHUB_SOC_TLB1_29__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_29__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_29__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_30 -#define MP0_MMHUB_SOC_TLB1_30__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_30__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_30__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_31 -#define MP0_MMHUB_SOC_TLB1_31__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_31__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_31__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_32 -#define MP0_MMHUB_SOC_TLB1_32__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_32__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_32__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_33 -#define MP0_MMHUB_SOC_TLB1_33__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_33__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_33__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_34 -#define MP0_MMHUB_SOC_TLB1_34__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_34__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_34__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_35 -#define MP0_MMHUB_SOC_TLB1_35__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_35__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_35__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_36 -#define MP0_MMHUB_SOC_TLB1_36__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_36__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_36__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_37 -#define MP0_MMHUB_SOC_TLB1_37__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_37__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_37__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_38 -#define MP0_MMHUB_SOC_TLB1_38__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_38__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_38__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_39 -#define MP0_MMHUB_SOC_TLB1_39__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_39__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_39__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_40 -#define MP0_MMHUB_SOC_TLB1_40__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_40__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_40__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_41 -#define MP0_MMHUB_SOC_TLB1_41__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_41__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_41__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_42 -#define MP0_MMHUB_SOC_TLB1_42__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_42__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_42__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_43 -#define MP0_MMHUB_SOC_TLB1_43__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_43__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_43__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_44 -#define MP0_MMHUB_SOC_TLB1_44__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_44__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_44__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_45 -#define MP0_MMHUB_SOC_TLB1_45__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_45__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_45__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_46 -#define MP0_MMHUB_SOC_TLB1_46__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_46__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_46__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_47 -#define MP0_MMHUB_SOC_TLB1_47__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_47__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_47__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_48 -#define MP0_MMHUB_SOC_TLB1_48__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_48__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_48__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_49 -#define MP0_MMHUB_SOC_TLB1_49__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_49__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_49__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_50 -#define MP0_MMHUB_SOC_TLB1_50__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_50__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_50__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_51 -#define MP0_MMHUB_SOC_TLB1_51__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_51__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_51__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_52 -#define MP0_MMHUB_SOC_TLB1_52__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_52__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_52__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_53 -#define MP0_MMHUB_SOC_TLB1_53__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_53__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_53__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_54 -#define MP0_MMHUB_SOC_TLB1_54__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_54__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_54__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_55 -#define MP0_MMHUB_SOC_TLB1_55__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_55__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_55__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_56 -#define MP0_MMHUB_SOC_TLB1_56__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_56__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_56__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_57 -#define MP0_MMHUB_SOC_TLB1_57__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_57__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_57__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_58 -#define MP0_MMHUB_SOC_TLB1_58__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_58__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_58__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_59 -#define MP0_MMHUB_SOC_TLB1_59__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_59__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_59__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_60 -#define MP0_MMHUB_SOC_TLB1_60__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_60__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_60__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_61 -#define MP0_MMHUB_SOC_TLB1_61__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_61__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_61__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB1_62 -#define MP0_MMHUB_SOC_TLB1_62__COHERENCE_MASK 0x00000001L -#define MP0_MMHUB_SOC_TLB1_62__SEG_SIZE_MASK 0x0000001eL -#define MP0_MMHUB_SOC_TLB1_62__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_MMHUB_SOC_TLB2_1 -#define MP0_MMHUB_SOC_TLB2_1__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_2 -#define MP0_MMHUB_SOC_TLB2_2__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_3 -#define MP0_MMHUB_SOC_TLB2_3__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_4 -#define MP0_MMHUB_SOC_TLB2_4__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_5 -#define MP0_MMHUB_SOC_TLB2_5__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_6 -#define MP0_MMHUB_SOC_TLB2_6__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_7 -#define MP0_MMHUB_SOC_TLB2_7__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_8 -#define MP0_MMHUB_SOC_TLB2_8__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_9 -#define MP0_MMHUB_SOC_TLB2_9__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_10 -#define MP0_MMHUB_SOC_TLB2_10__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_11 -#define MP0_MMHUB_SOC_TLB2_11__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_12 -#define MP0_MMHUB_SOC_TLB2_12__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_13 -#define MP0_MMHUB_SOC_TLB2_13__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_14 -#define MP0_MMHUB_SOC_TLB2_14__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_15 -#define MP0_MMHUB_SOC_TLB2_15__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_16 -#define MP0_MMHUB_SOC_TLB2_16__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_17 -#define MP0_MMHUB_SOC_TLB2_17__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_18 -#define MP0_MMHUB_SOC_TLB2_18__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_19 -#define MP0_MMHUB_SOC_TLB2_19__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_20 -#define MP0_MMHUB_SOC_TLB2_20__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_21 -#define MP0_MMHUB_SOC_TLB2_21__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_22 -#define MP0_MMHUB_SOC_TLB2_22__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_23 -#define MP0_MMHUB_SOC_TLB2_23__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_24 -#define MP0_MMHUB_SOC_TLB2_24__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_25 -#define MP0_MMHUB_SOC_TLB2_25__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_26 -#define MP0_MMHUB_SOC_TLB2_26__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_27 -#define MP0_MMHUB_SOC_TLB2_27__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_28 -#define MP0_MMHUB_SOC_TLB2_28__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_29 -#define MP0_MMHUB_SOC_TLB2_29__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_30 -#define MP0_MMHUB_SOC_TLB2_30__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_31 -#define MP0_MMHUB_SOC_TLB2_31__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_32 -#define MP0_MMHUB_SOC_TLB2_32__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_33 -#define MP0_MMHUB_SOC_TLB2_33__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_34 -#define MP0_MMHUB_SOC_TLB2_34__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_35 -#define MP0_MMHUB_SOC_TLB2_35__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_36 -#define MP0_MMHUB_SOC_TLB2_36__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_37 -#define MP0_MMHUB_SOC_TLB2_37__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_38 -#define MP0_MMHUB_SOC_TLB2_38__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_39 -#define MP0_MMHUB_SOC_TLB2_39__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_40 -#define MP0_MMHUB_SOC_TLB2_40__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_41 -#define MP0_MMHUB_SOC_TLB2_41__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_42 -#define MP0_MMHUB_SOC_TLB2_42__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_43 -#define MP0_MMHUB_SOC_TLB2_43__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_44 -#define MP0_MMHUB_SOC_TLB2_44__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_45 -#define MP0_MMHUB_SOC_TLB2_45__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_46 -#define MP0_MMHUB_SOC_TLB2_46__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_47 -#define MP0_MMHUB_SOC_TLB2_47__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_48 -#define MP0_MMHUB_SOC_TLB2_48__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_49 -#define MP0_MMHUB_SOC_TLB2_49__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_50 -#define MP0_MMHUB_SOC_TLB2_50__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_51 -#define MP0_MMHUB_SOC_TLB2_51__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_52 -#define MP0_MMHUB_SOC_TLB2_52__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_53 -#define MP0_MMHUB_SOC_TLB2_53__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_54 -#define MP0_MMHUB_SOC_TLB2_54__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_55 -#define MP0_MMHUB_SOC_TLB2_55__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_56 -#define MP0_MMHUB_SOC_TLB2_56__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_57 -#define MP0_MMHUB_SOC_TLB2_57__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_58 -#define MP0_MMHUB_SOC_TLB2_58__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_59 -#define MP0_MMHUB_SOC_TLB2_59__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_60 -#define MP0_MMHUB_SOC_TLB2_60__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_61 -#define MP0_MMHUB_SOC_TLB2_61__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB2_62 -#define MP0_MMHUB_SOC_TLB2_62__AWUSER_MASK 0xffffffffL - -// MP0_MMHUB_SOC_TLB3_1 -#define MP0_MMHUB_SOC_TLB3_1__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_1__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_2 -#define MP0_MMHUB_SOC_TLB3_2__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_2__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_3 -#define MP0_MMHUB_SOC_TLB3_3__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_3__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_4 -#define MP0_MMHUB_SOC_TLB3_4__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_4__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_5 -#define MP0_MMHUB_SOC_TLB3_5__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_5__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_6 -#define MP0_MMHUB_SOC_TLB3_6__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_6__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_7 -#define MP0_MMHUB_SOC_TLB3_7__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_7__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_8 -#define MP0_MMHUB_SOC_TLB3_8__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_8__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_9 -#define MP0_MMHUB_SOC_TLB3_9__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_9__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_10 -#define MP0_MMHUB_SOC_TLB3_10__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_10__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_11 -#define MP0_MMHUB_SOC_TLB3_11__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_11__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_12 -#define MP0_MMHUB_SOC_TLB3_12__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_12__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_13 -#define MP0_MMHUB_SOC_TLB3_13__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_13__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_14 -#define MP0_MMHUB_SOC_TLB3_14__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_14__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_15 -#define MP0_MMHUB_SOC_TLB3_15__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_15__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_16 -#define MP0_MMHUB_SOC_TLB3_16__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_16__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_17 -#define MP0_MMHUB_SOC_TLB3_17__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_17__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_18 -#define MP0_MMHUB_SOC_TLB3_18__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_18__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_19 -#define MP0_MMHUB_SOC_TLB3_19__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_19__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_20 -#define MP0_MMHUB_SOC_TLB3_20__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_20__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_21 -#define MP0_MMHUB_SOC_TLB3_21__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_21__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_22 -#define MP0_MMHUB_SOC_TLB3_22__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_22__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_23 -#define MP0_MMHUB_SOC_TLB3_23__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_23__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_24 -#define MP0_MMHUB_SOC_TLB3_24__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_24__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_25 -#define MP0_MMHUB_SOC_TLB3_25__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_25__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_26 -#define MP0_MMHUB_SOC_TLB3_26__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_26__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_27 -#define MP0_MMHUB_SOC_TLB3_27__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_27__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_28 -#define MP0_MMHUB_SOC_TLB3_28__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_28__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_29 -#define MP0_MMHUB_SOC_TLB3_29__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_29__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_30 -#define MP0_MMHUB_SOC_TLB3_30__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_30__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_31 -#define MP0_MMHUB_SOC_TLB3_31__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_31__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_32 -#define MP0_MMHUB_SOC_TLB3_32__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_32__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_33 -#define MP0_MMHUB_SOC_TLB3_33__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_33__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_34 -#define MP0_MMHUB_SOC_TLB3_34__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_34__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_35 -#define MP0_MMHUB_SOC_TLB3_35__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_35__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_36 -#define MP0_MMHUB_SOC_TLB3_36__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_36__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_37 -#define MP0_MMHUB_SOC_TLB3_37__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_37__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_38 -#define MP0_MMHUB_SOC_TLB3_38__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_38__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_39 -#define MP0_MMHUB_SOC_TLB3_39__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_39__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_40 -#define MP0_MMHUB_SOC_TLB3_40__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_40__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_41 -#define MP0_MMHUB_SOC_TLB3_41__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_41__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_42 -#define MP0_MMHUB_SOC_TLB3_42__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_42__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_43 -#define MP0_MMHUB_SOC_TLB3_43__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_43__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_44 -#define MP0_MMHUB_SOC_TLB3_44__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_44__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_45 -#define MP0_MMHUB_SOC_TLB3_45__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_45__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_46 -#define MP0_MMHUB_SOC_TLB3_46__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_46__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_47 -#define MP0_MMHUB_SOC_TLB3_47__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_47__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_48 -#define MP0_MMHUB_SOC_TLB3_48__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_48__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_49 -#define MP0_MMHUB_SOC_TLB3_49__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_49__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_50 -#define MP0_MMHUB_SOC_TLB3_50__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_50__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_51 -#define MP0_MMHUB_SOC_TLB3_51__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_51__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_52 -#define MP0_MMHUB_SOC_TLB3_52__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_52__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_53 -#define MP0_MMHUB_SOC_TLB3_53__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_53__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_54 -#define MP0_MMHUB_SOC_TLB3_54__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_54__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_55 -#define MP0_MMHUB_SOC_TLB3_55__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_55__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_56 -#define MP0_MMHUB_SOC_TLB3_56__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_56__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_57 -#define MP0_MMHUB_SOC_TLB3_57__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_57__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_58 -#define MP0_MMHUB_SOC_TLB3_58__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_58__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_59 -#define MP0_MMHUB_SOC_TLB3_59__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_59__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_60 -#define MP0_MMHUB_SOC_TLB3_60__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_60__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_61 -#define MP0_MMHUB_SOC_TLB3_61__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_61__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_SOC_TLB3_62 -#define MP0_MMHUB_SOC_TLB3_62__ARUSER_MASK 0x03ffffffL -#define MP0_MMHUB_SOC_TLB3_62__WUSER_MASK 0x3c000000L - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB_MASK 0xffffffffL - -// MP0_MMHUB_TLB_ATTRIBUTE_1 -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_2 -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_3 -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_4 -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_5 -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_6 -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_7 -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_8 -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_9 -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_10 -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_11 -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_12 -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_13 -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_14 -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_15 -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_16 -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_17 -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_18 -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_19 -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_20 -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_21 -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_22 -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_23 -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_24 -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_25 -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_26 -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_27 -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_28 -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_29 -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_30 -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_31 -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_32 -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_33 -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_34 -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_35 -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_36 -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_37 -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_38 -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_39 -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_40 -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_41 -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_42 -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_43 -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_44 -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_45 -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_46 -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_47 -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_48 -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_49 -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_50 -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_51 -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_52 -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_53 -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_54 -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_55 -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_56 -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_57 -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_58 -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_59 -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_60 -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_61 -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_TLB_ATTRIBUTE_62 -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_CCP_MASK 0x00800000L -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB_MASK 0x40000000L -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_MMHUB_INT_STATUS -#define MP0_MMHUB_INT_STATUS__RD_ERROR_MASK 0x00000001L -#define MP0_MMHUB_INT_STATUS__WR_ERROR_MASK 0x00000002L -#define MP0_MMHUB_INT_STATUS__REG_ERROR_MASK 0x00000004L - -// MP0_MMHUB_WR_INT_ADDR -#define MP0_MMHUB_WR_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP0_MMHUB_WR_INT_OTHER -#define MP0_MMHUB_WR_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP0_MMHUB_WR_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP0_MMHUB_WR_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP0_MMHUB_WR_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP0_MMHUB_WR_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP0_MMHUB_WR_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP0_MMHUB_WR_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP0_MMHUB_WR_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP0_MMHUB_RD_INT_ADDR -#define MP0_MMHUB_RD_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP0_MMHUB_RD_INT_OTHER -#define MP0_MMHUB_RD_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP0_MMHUB_RD_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP0_MMHUB_RD_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP0_MMHUB_RD_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP0_MMHUB_RD_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP0_MMHUB_RD_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP0_MMHUB_RD_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP0_MMHUB_RD_INT_OTHER__ERROR_LENGTH_MASK 0x04000000L -#define MP0_MMHUB_RD_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP0_MMHUB_REG_INT_ADDR -#define MP0_MMHUB_REG_INT_ADDR__ADDR_MASK 0x0000ffffL - -// MP0_MMHUB_REG_INT_OTHER -#define MP0_MMHUB_REG_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP0_MMHUB_REG_INT_OTHER__ERROR_AES_MASK 0x00100000L -#define MP0_MMHUB_REG_INT_OTHER__ERROR_MST_MASK 0x00200000L -#define MP0_MMHUB_REG_INT_OTHER__ERROR_ADDR_MASK 0x00400000L -#define MP0_MMHUB_REG_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP0_MMHUB_REG_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP0_MMHUB_AXCACHE_CFG -#define MP0_MMHUB_AXCACHE_CFG__ARCACHE_NONCOH_MASK 0x0000000fL -#define MP0_MMHUB_AXCACHE_CFG__ARCACHE_COH_MASK 0x000000f0L -#define MP0_MMHUB_AXCACHE_CFG__AWCACHE_NONCOH_MASK 0x00000f00L -#define MP0_MMHUB_AXCACHE_CFG__AWCACHE_COH_MASK 0x0000f000L -#define MP0_MMHUB_AXCACHE_CFG__QOSW_MASK 0x000f0000L -#define MP0_MMHUB_AXCACHE_CFG__QOSR_MASK 0x00f00000L - -// MP0_MMHUB_DS_OVERRIDE -#define MP0_MMHUB_DS_OVERRIDE__DS_CNT_MASK 0x000007ffL -#define MP0_MMHUB_DS_OVERRIDE__DS_DISABLE_MASK 0x00000800L - -// MP0_MMHUB_OUTSTANDING -#define MP0_MMHUB_OUTSTANDING__PENDING_WR_MASK 0x0000ffffL -#define MP0_MMHUB_OUTSTANDING__PENDING_RD_MASK 0x00ff0000L - -// MP0_SYSHUB_SOC_TLB0_1 -#define MP0_SYSHUB_SOC_TLB0_1__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_2 -#define MP0_SYSHUB_SOC_TLB0_2__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_3 -#define MP0_SYSHUB_SOC_TLB0_3__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_4 -#define MP0_SYSHUB_SOC_TLB0_4__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_5 -#define MP0_SYSHUB_SOC_TLB0_5__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_6 -#define MP0_SYSHUB_SOC_TLB0_6__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_7 -#define MP0_SYSHUB_SOC_TLB0_7__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_8 -#define MP0_SYSHUB_SOC_TLB0_8__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_9 -#define MP0_SYSHUB_SOC_TLB0_9__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_10 -#define MP0_SYSHUB_SOC_TLB0_10__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_11 -#define MP0_SYSHUB_SOC_TLB0_11__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_12 -#define MP0_SYSHUB_SOC_TLB0_12__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_13 -#define MP0_SYSHUB_SOC_TLB0_13__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_14 -#define MP0_SYSHUB_SOC_TLB0_14__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_15 -#define MP0_SYSHUB_SOC_TLB0_15__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_16 -#define MP0_SYSHUB_SOC_TLB0_16__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_17 -#define MP0_SYSHUB_SOC_TLB0_17__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_18 -#define MP0_SYSHUB_SOC_TLB0_18__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_19 -#define MP0_SYSHUB_SOC_TLB0_19__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_20 -#define MP0_SYSHUB_SOC_TLB0_20__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_21 -#define MP0_SYSHUB_SOC_TLB0_21__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_22 -#define MP0_SYSHUB_SOC_TLB0_22__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_23 -#define MP0_SYSHUB_SOC_TLB0_23__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_24 -#define MP0_SYSHUB_SOC_TLB0_24__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_25 -#define MP0_SYSHUB_SOC_TLB0_25__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_26 -#define MP0_SYSHUB_SOC_TLB0_26__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_27 -#define MP0_SYSHUB_SOC_TLB0_27__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_28 -#define MP0_SYSHUB_SOC_TLB0_28__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_29 -#define MP0_SYSHUB_SOC_TLB0_29__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_30 -#define MP0_SYSHUB_SOC_TLB0_30__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_31 -#define MP0_SYSHUB_SOC_TLB0_31__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_32 -#define MP0_SYSHUB_SOC_TLB0_32__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_33 -#define MP0_SYSHUB_SOC_TLB0_33__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_34 -#define MP0_SYSHUB_SOC_TLB0_34__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_35 -#define MP0_SYSHUB_SOC_TLB0_35__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_36 -#define MP0_SYSHUB_SOC_TLB0_36__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_37 -#define MP0_SYSHUB_SOC_TLB0_37__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_38 -#define MP0_SYSHUB_SOC_TLB0_38__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_39 -#define MP0_SYSHUB_SOC_TLB0_39__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_40 -#define MP0_SYSHUB_SOC_TLB0_40__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_41 -#define MP0_SYSHUB_SOC_TLB0_41__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_42 -#define MP0_SYSHUB_SOC_TLB0_42__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_43 -#define MP0_SYSHUB_SOC_TLB0_43__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_44 -#define MP0_SYSHUB_SOC_TLB0_44__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_45 -#define MP0_SYSHUB_SOC_TLB0_45__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_46 -#define MP0_SYSHUB_SOC_TLB0_46__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_47 -#define MP0_SYSHUB_SOC_TLB0_47__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_48 -#define MP0_SYSHUB_SOC_TLB0_48__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_49 -#define MP0_SYSHUB_SOC_TLB0_49__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_50 -#define MP0_SYSHUB_SOC_TLB0_50__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_51 -#define MP0_SYSHUB_SOC_TLB0_51__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_52 -#define MP0_SYSHUB_SOC_TLB0_52__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_53 -#define MP0_SYSHUB_SOC_TLB0_53__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_54 -#define MP0_SYSHUB_SOC_TLB0_54__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_55 -#define MP0_SYSHUB_SOC_TLB0_55__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_56 -#define MP0_SYSHUB_SOC_TLB0_56__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_57 -#define MP0_SYSHUB_SOC_TLB0_57__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_58 -#define MP0_SYSHUB_SOC_TLB0_58__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_59 -#define MP0_SYSHUB_SOC_TLB0_59__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_60 -#define MP0_SYSHUB_SOC_TLB0_60__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_61 -#define MP0_SYSHUB_SOC_TLB0_61__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB0_62 -#define MP0_SYSHUB_SOC_TLB0_62__SOC_ADDR_MASK 0x003fffffL - -// MP0_SYSHUB_SOC_TLB1_1 -#define MP0_SYSHUB_SOC_TLB1_1__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_1__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_1__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_2 -#define MP0_SYSHUB_SOC_TLB1_2__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_2__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_2__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_3 -#define MP0_SYSHUB_SOC_TLB1_3__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_3__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_3__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_4 -#define MP0_SYSHUB_SOC_TLB1_4__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_4__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_4__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_5 -#define MP0_SYSHUB_SOC_TLB1_5__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_5__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_5__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_6 -#define MP0_SYSHUB_SOC_TLB1_6__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_6__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_6__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_7 -#define MP0_SYSHUB_SOC_TLB1_7__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_7__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_7__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_8 -#define MP0_SYSHUB_SOC_TLB1_8__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_8__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_8__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_9 -#define MP0_SYSHUB_SOC_TLB1_9__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_9__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_9__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_10 -#define MP0_SYSHUB_SOC_TLB1_10__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_10__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_10__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_11 -#define MP0_SYSHUB_SOC_TLB1_11__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_11__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_11__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_12 -#define MP0_SYSHUB_SOC_TLB1_12__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_12__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_12__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_13 -#define MP0_SYSHUB_SOC_TLB1_13__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_13__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_13__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_14 -#define MP0_SYSHUB_SOC_TLB1_14__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_14__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_14__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_15 -#define MP0_SYSHUB_SOC_TLB1_15__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_15__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_15__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_16 -#define MP0_SYSHUB_SOC_TLB1_16__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_16__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_16__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_17 -#define MP0_SYSHUB_SOC_TLB1_17__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_17__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_17__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_18 -#define MP0_SYSHUB_SOC_TLB1_18__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_18__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_18__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_19 -#define MP0_SYSHUB_SOC_TLB1_19__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_19__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_19__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_20 -#define MP0_SYSHUB_SOC_TLB1_20__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_20__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_20__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_21 -#define MP0_SYSHUB_SOC_TLB1_21__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_21__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_21__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_22 -#define MP0_SYSHUB_SOC_TLB1_22__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_22__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_22__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_23 -#define MP0_SYSHUB_SOC_TLB1_23__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_23__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_23__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_24 -#define MP0_SYSHUB_SOC_TLB1_24__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_24__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_24__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_25 -#define MP0_SYSHUB_SOC_TLB1_25__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_25__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_25__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_26 -#define MP0_SYSHUB_SOC_TLB1_26__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_26__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_26__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_27 -#define MP0_SYSHUB_SOC_TLB1_27__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_27__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_27__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_28 -#define MP0_SYSHUB_SOC_TLB1_28__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_28__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_28__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_29 -#define MP0_SYSHUB_SOC_TLB1_29__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_29__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_29__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_30 -#define MP0_SYSHUB_SOC_TLB1_30__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_30__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_30__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_31 -#define MP0_SYSHUB_SOC_TLB1_31__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_31__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_31__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_32 -#define MP0_SYSHUB_SOC_TLB1_32__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_32__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_32__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_33 -#define MP0_SYSHUB_SOC_TLB1_33__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_33__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_33__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_34 -#define MP0_SYSHUB_SOC_TLB1_34__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_34__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_34__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_35 -#define MP0_SYSHUB_SOC_TLB1_35__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_35__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_35__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_36 -#define MP0_SYSHUB_SOC_TLB1_36__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_36__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_36__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_37 -#define MP0_SYSHUB_SOC_TLB1_37__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_37__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_37__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_38 -#define MP0_SYSHUB_SOC_TLB1_38__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_38__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_38__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_39 -#define MP0_SYSHUB_SOC_TLB1_39__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_39__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_39__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_40 -#define MP0_SYSHUB_SOC_TLB1_40__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_40__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_40__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_41 -#define MP0_SYSHUB_SOC_TLB1_41__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_41__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_41__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_42 -#define MP0_SYSHUB_SOC_TLB1_42__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_42__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_42__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_43 -#define MP0_SYSHUB_SOC_TLB1_43__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_43__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_43__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_44 -#define MP0_SYSHUB_SOC_TLB1_44__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_44__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_44__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_45 -#define MP0_SYSHUB_SOC_TLB1_45__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_45__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_45__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_46 -#define MP0_SYSHUB_SOC_TLB1_46__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_46__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_46__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_47 -#define MP0_SYSHUB_SOC_TLB1_47__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_47__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_47__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_48 -#define MP0_SYSHUB_SOC_TLB1_48__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_48__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_48__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_49 -#define MP0_SYSHUB_SOC_TLB1_49__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_49__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_49__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_50 -#define MP0_SYSHUB_SOC_TLB1_50__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_50__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_50__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_51 -#define MP0_SYSHUB_SOC_TLB1_51__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_51__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_51__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_52 -#define MP0_SYSHUB_SOC_TLB1_52__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_52__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_52__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_53 -#define MP0_SYSHUB_SOC_TLB1_53__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_53__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_53__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_54 -#define MP0_SYSHUB_SOC_TLB1_54__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_54__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_54__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_55 -#define MP0_SYSHUB_SOC_TLB1_55__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_55__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_55__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_56 -#define MP0_SYSHUB_SOC_TLB1_56__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_56__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_56__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_57 -#define MP0_SYSHUB_SOC_TLB1_57__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_57__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_57__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_58 -#define MP0_SYSHUB_SOC_TLB1_58__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_58__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_58__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_59 -#define MP0_SYSHUB_SOC_TLB1_59__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_59__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_59__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_60 -#define MP0_SYSHUB_SOC_TLB1_60__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_60__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_60__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_61 -#define MP0_SYSHUB_SOC_TLB1_61__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_61__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_61__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB1_62 -#define MP0_SYSHUB_SOC_TLB1_62__COHERENCE_MASK 0x00000001L -#define MP0_SYSHUB_SOC_TLB1_62__SEG_SIZE_MASK 0x0000001eL -#define MP0_SYSHUB_SOC_TLB1_62__SEG_OFFSET_MASK 0x00003fe0L - -// MP0_SYSHUB_SOC_TLB2_1 -#define MP0_SYSHUB_SOC_TLB2_1__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_2 -#define MP0_SYSHUB_SOC_TLB2_2__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_3 -#define MP0_SYSHUB_SOC_TLB2_3__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_4 -#define MP0_SYSHUB_SOC_TLB2_4__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_5 -#define MP0_SYSHUB_SOC_TLB2_5__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_6 -#define MP0_SYSHUB_SOC_TLB2_6__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_7 -#define MP0_SYSHUB_SOC_TLB2_7__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_8 -#define MP0_SYSHUB_SOC_TLB2_8__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_9 -#define MP0_SYSHUB_SOC_TLB2_9__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_10 -#define MP0_SYSHUB_SOC_TLB2_10__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_11 -#define MP0_SYSHUB_SOC_TLB2_11__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_12 -#define MP0_SYSHUB_SOC_TLB2_12__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_13 -#define MP0_SYSHUB_SOC_TLB2_13__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_14 -#define MP0_SYSHUB_SOC_TLB2_14__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_15 -#define MP0_SYSHUB_SOC_TLB2_15__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_16 -#define MP0_SYSHUB_SOC_TLB2_16__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_17 -#define MP0_SYSHUB_SOC_TLB2_17__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_18 -#define MP0_SYSHUB_SOC_TLB2_18__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_19 -#define MP0_SYSHUB_SOC_TLB2_19__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_20 -#define MP0_SYSHUB_SOC_TLB2_20__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_21 -#define MP0_SYSHUB_SOC_TLB2_21__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_22 -#define MP0_SYSHUB_SOC_TLB2_22__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_23 -#define MP0_SYSHUB_SOC_TLB2_23__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_24 -#define MP0_SYSHUB_SOC_TLB2_24__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_25 -#define MP0_SYSHUB_SOC_TLB2_25__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_26 -#define MP0_SYSHUB_SOC_TLB2_26__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_27 -#define MP0_SYSHUB_SOC_TLB2_27__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_28 -#define MP0_SYSHUB_SOC_TLB2_28__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_29 -#define MP0_SYSHUB_SOC_TLB2_29__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_30 -#define MP0_SYSHUB_SOC_TLB2_30__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_31 -#define MP0_SYSHUB_SOC_TLB2_31__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_32 -#define MP0_SYSHUB_SOC_TLB2_32__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_33 -#define MP0_SYSHUB_SOC_TLB2_33__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_34 -#define MP0_SYSHUB_SOC_TLB2_34__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_35 -#define MP0_SYSHUB_SOC_TLB2_35__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_36 -#define MP0_SYSHUB_SOC_TLB2_36__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_37 -#define MP0_SYSHUB_SOC_TLB2_37__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_38 -#define MP0_SYSHUB_SOC_TLB2_38__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_39 -#define MP0_SYSHUB_SOC_TLB2_39__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_40 -#define MP0_SYSHUB_SOC_TLB2_40__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_41 -#define MP0_SYSHUB_SOC_TLB2_41__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_42 -#define MP0_SYSHUB_SOC_TLB2_42__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_43 -#define MP0_SYSHUB_SOC_TLB2_43__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_44 -#define MP0_SYSHUB_SOC_TLB2_44__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_45 -#define MP0_SYSHUB_SOC_TLB2_45__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_46 -#define MP0_SYSHUB_SOC_TLB2_46__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_47 -#define MP0_SYSHUB_SOC_TLB2_47__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_48 -#define MP0_SYSHUB_SOC_TLB2_48__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_49 -#define MP0_SYSHUB_SOC_TLB2_49__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_50 -#define MP0_SYSHUB_SOC_TLB2_50__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_51 -#define MP0_SYSHUB_SOC_TLB2_51__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_52 -#define MP0_SYSHUB_SOC_TLB2_52__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_53 -#define MP0_SYSHUB_SOC_TLB2_53__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_54 -#define MP0_SYSHUB_SOC_TLB2_54__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_55 -#define MP0_SYSHUB_SOC_TLB2_55__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_56 -#define MP0_SYSHUB_SOC_TLB2_56__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_57 -#define MP0_SYSHUB_SOC_TLB2_57__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_58 -#define MP0_SYSHUB_SOC_TLB2_58__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_59 -#define MP0_SYSHUB_SOC_TLB2_59__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_60 -#define MP0_SYSHUB_SOC_TLB2_60__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_61 -#define MP0_SYSHUB_SOC_TLB2_61__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB2_62 -#define MP0_SYSHUB_SOC_TLB2_62__AWUSER_MASK 0xffffffffL - -// MP0_SYSHUB_SOC_TLB3_1 -#define MP0_SYSHUB_SOC_TLB3_1__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_1__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_2 -#define MP0_SYSHUB_SOC_TLB3_2__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_2__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_3 -#define MP0_SYSHUB_SOC_TLB3_3__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_3__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_4 -#define MP0_SYSHUB_SOC_TLB3_4__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_4__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_5 -#define MP0_SYSHUB_SOC_TLB3_5__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_5__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_6 -#define MP0_SYSHUB_SOC_TLB3_6__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_6__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_7 -#define MP0_SYSHUB_SOC_TLB3_7__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_7__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_8 -#define MP0_SYSHUB_SOC_TLB3_8__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_8__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_9 -#define MP0_SYSHUB_SOC_TLB3_9__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_9__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_10 -#define MP0_SYSHUB_SOC_TLB3_10__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_10__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_11 -#define MP0_SYSHUB_SOC_TLB3_11__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_11__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_12 -#define MP0_SYSHUB_SOC_TLB3_12__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_12__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_13 -#define MP0_SYSHUB_SOC_TLB3_13__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_13__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_14 -#define MP0_SYSHUB_SOC_TLB3_14__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_14__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_15 -#define MP0_SYSHUB_SOC_TLB3_15__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_15__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_16 -#define MP0_SYSHUB_SOC_TLB3_16__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_16__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_17 -#define MP0_SYSHUB_SOC_TLB3_17__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_17__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_18 -#define MP0_SYSHUB_SOC_TLB3_18__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_18__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_19 -#define MP0_SYSHUB_SOC_TLB3_19__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_19__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_20 -#define MP0_SYSHUB_SOC_TLB3_20__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_20__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_21 -#define MP0_SYSHUB_SOC_TLB3_21__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_21__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_22 -#define MP0_SYSHUB_SOC_TLB3_22__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_22__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_23 -#define MP0_SYSHUB_SOC_TLB3_23__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_23__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_24 -#define MP0_SYSHUB_SOC_TLB3_24__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_24__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_25 -#define MP0_SYSHUB_SOC_TLB3_25__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_25__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_26 -#define MP0_SYSHUB_SOC_TLB3_26__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_26__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_27 -#define MP0_SYSHUB_SOC_TLB3_27__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_27__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_28 -#define MP0_SYSHUB_SOC_TLB3_28__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_28__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_29 -#define MP0_SYSHUB_SOC_TLB3_29__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_29__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_30 -#define MP0_SYSHUB_SOC_TLB3_30__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_30__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_31 -#define MP0_SYSHUB_SOC_TLB3_31__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_31__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_32 -#define MP0_SYSHUB_SOC_TLB3_32__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_32__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_33 -#define MP0_SYSHUB_SOC_TLB3_33__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_33__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_34 -#define MP0_SYSHUB_SOC_TLB3_34__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_34__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_35 -#define MP0_SYSHUB_SOC_TLB3_35__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_35__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_36 -#define MP0_SYSHUB_SOC_TLB3_36__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_36__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_37 -#define MP0_SYSHUB_SOC_TLB3_37__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_37__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_38 -#define MP0_SYSHUB_SOC_TLB3_38__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_38__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_39 -#define MP0_SYSHUB_SOC_TLB3_39__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_39__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_40 -#define MP0_SYSHUB_SOC_TLB3_40__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_40__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_41 -#define MP0_SYSHUB_SOC_TLB3_41__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_41__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_42 -#define MP0_SYSHUB_SOC_TLB3_42__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_42__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_43 -#define MP0_SYSHUB_SOC_TLB3_43__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_43__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_44 -#define MP0_SYSHUB_SOC_TLB3_44__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_44__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_45 -#define MP0_SYSHUB_SOC_TLB3_45__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_45__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_46 -#define MP0_SYSHUB_SOC_TLB3_46__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_46__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_47 -#define MP0_SYSHUB_SOC_TLB3_47__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_47__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_48 -#define MP0_SYSHUB_SOC_TLB3_48__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_48__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_49 -#define MP0_SYSHUB_SOC_TLB3_49__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_49__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_50 -#define MP0_SYSHUB_SOC_TLB3_50__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_50__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_51 -#define MP0_SYSHUB_SOC_TLB3_51__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_51__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_52 -#define MP0_SYSHUB_SOC_TLB3_52__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_52__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_53 -#define MP0_SYSHUB_SOC_TLB3_53__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_53__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_54 -#define MP0_SYSHUB_SOC_TLB3_54__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_54__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_55 -#define MP0_SYSHUB_SOC_TLB3_55__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_55__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_56 -#define MP0_SYSHUB_SOC_TLB3_56__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_56__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_57 -#define MP0_SYSHUB_SOC_TLB3_57__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_57__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_58 -#define MP0_SYSHUB_SOC_TLB3_58__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_58__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_59 -#define MP0_SYSHUB_SOC_TLB3_59__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_59__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_60 -#define MP0_SYSHUB_SOC_TLB3_60__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_60__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_61 -#define MP0_SYSHUB_SOC_TLB3_61__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_61__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_SOC_TLB3_62 -#define MP0_SYSHUB_SOC_TLB3_62__ARUSER_MASK 0x03ffffffL -#define MP0_SYSHUB_SOC_TLB3_62__WUSER_MASK 0x3c000000L - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB_MASK 0xffffffffL - -// MP0_SYSHUB_TLB_ATTRIBUTE_1 -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_2 -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_3 -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_4 -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_5 -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_6 -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_7 -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_8 -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_9 -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_10 -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_11 -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_12 -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_13 -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_14 -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_15 -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_16 -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_17 -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_18 -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_19 -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_20 -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_21 -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_22 -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_23 -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_24 -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_25 -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_26 -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_27 -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_28 -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_29 -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_30 -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_31 -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_32 -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_33 -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_34 -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_35 -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_36 -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_37 -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_38 -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_39 -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_40 -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_41 -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_42 -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_43 -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_44 -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_45 -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_46 -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_47 -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_48 -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_49 -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_50 -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_51 -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_52 -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_53 -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_54 -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_55 -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_56 -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_57 -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_58 -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_59 -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_60 -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_61 -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_TLB_ATTRIBUTE_62 -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN_MASK 0x00008000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_CCP_MASK 0x00800000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB_MASK 0x40000000L -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV_MASK 0x80000000L - -// MP0_SYSHUB_INT_STATUS -#define MP0_SYSHUB_INT_STATUS__RD_ERROR_MASK 0x00000001L -#define MP0_SYSHUB_INT_STATUS__WR_ERROR_MASK 0x00000002L -#define MP0_SYSHUB_INT_STATUS__REG_ERROR_MASK 0x00000004L - -// MP0_SYSHUB_WR_INT_ADDR -#define MP0_SYSHUB_WR_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP0_SYSHUB_WR_INT_OTHER -#define MP0_SYSHUB_WR_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP0_SYSHUB_WR_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP0_SYSHUB_RD_INT_ADDR -#define MP0_SYSHUB_RD_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP0_SYSHUB_RD_INT_OTHER -#define MP0_SYSHUB_RD_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_LENGTH_MASK 0x04000000L -#define MP0_SYSHUB_RD_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP0_SYSHUB_REG_INT_ADDR -#define MP0_SYSHUB_REG_INT_ADDR__ADDR_MASK 0x0000ffffL - -// MP0_SYSHUB_REG_INT_OTHER -#define MP0_SYSHUB_REG_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_AES_MASK 0x00100000L -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_MST_MASK 0x00200000L -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_ADDR_MASK 0x00400000L -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP0_SYSHUB_REG_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP0_SYSHUB_AXCACHE_CFG -#define MP0_SYSHUB_AXCACHE_CFG__ARCACHE_NONCOH_MASK 0x0000000fL -#define MP0_SYSHUB_AXCACHE_CFG__ARCACHE_COH_MASK 0x000000f0L -#define MP0_SYSHUB_AXCACHE_CFG__AWCACHE_NONCOH_MASK 0x00000f00L -#define MP0_SYSHUB_AXCACHE_CFG__AWCACHE_COH_MASK 0x0000f000L -#define MP0_SYSHUB_AXCACHE_CFG__QOSW_MASK 0x000f0000L -#define MP0_SYSHUB_AXCACHE_CFG__QOSR_MASK 0x00f00000L - -// MP0_SYSHUB_DS_OVERRIDE -#define MP0_SYSHUB_DS_OVERRIDE__DS_CNT_MASK 0x000007ffL -#define MP0_SYSHUB_DS_OVERRIDE__DS_DISABLE_MASK 0x00000800L - -// MP0_SYSHUB_OUTSTANDING -#define MP0_SYSHUB_OUTSTANDING__PENDING_WR_MASK 0x0000ffffL -#define MP0_SYSHUB_OUTSTANDING__PENDING_RD_MASK 0x00ff0000L - -// MP1_SMNIF_ERROR -#define MP1_SMNIF_ERROR__RESERVED_MASK 0xffffffffL - -// MP1_LX3_PDEBUGPC -#define MP1_LX3_PDEBUGPC__PDEBUGPC_MASK 0xffffffffL - -// MP1_LX3_PWAITMODE -#define MP1_LX3_PWAITMODE__PWAITMODE_MASK 0x00000001L - -// MP1_IH_MP0SW_INT_CTXID -#define MP1_IH_MP0SW_INT_CTXID__CTXID_MASK 0x0fffffffL - -// MP1_IH_MP1SW_INT_CTXID -#define MP1_IH_MP1SW_INT_CTXID__CTXID_MASK 0x0fffffffL - -// MP1_IH_DISP_TIMER_ID -#define MP1_IH_DISP_TIMER_ID__DISP_T0_INT_ID_MASK 0x000000ffL -#define MP1_IH_DISP_TIMER_ID__DISP_T1_INT_ID_MASK 0x0000ff00L - -// MP1_FW_DEBUG_CNT0 -#define MP1_FW_DEBUG_CNT0__DATA_MASK 0x0000ffffL - -// MP1_FW_DEBUG_CNT1 -#define MP1_FW_DEBUG_CNT1__DATA_MASK 0x0000ffffL - -// MP1_FW_DEBUG_CNT2 -#define MP1_FW_DEBUG_CNT2__DATA_MASK 0x0000ffffL - -// MP1_FW_DEBUG_CNT3 -#define MP1_FW_DEBUG_CNT3__DATA_MASK 0x0000ffffL - -// MP1_FW_DEBUG_SIGNAL0 -#define MP1_FW_DEBUG_SIGNAL0__DATA_MASK 0x00ffffffL - -// MP1_FW_DEBUG_SIGNAL1 -#define MP1_FW_DEBUG_SIGNAL1__DATA_MASK 0x00ffffffL - -// MP1_DSM_ENABLE -#define MP1_DSM_ENABLE__MP1_ENB_BREAKINRELAY_MASK 0x00000001L -#define MP1_DSM_ENABLE__MP1_ENB_CROSSTRIGGERIN_MASK 0x00000002L -#define MP1_DSM_ENABLE__MP1_ENB_DSMINT_MASK 0x00000004L -#define MP1_DSM_ENABLE__MP1_ENB_UNUSED_MASK 0x00000008L - -// MP1_FIRMWARE_FLAGS -#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L -#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xfffffffeL - -// MP1_MUTEX_0 -#define MP1_MUTEX_0__MUTEX_MASK 0x000000ffL - -// MP1_MUTEX_1 -#define MP1_MUTEX_1__MUTEX_MASK 0x000000ffL - -// MP1_MUTEX_2 -#define MP1_MUTEX_2__MUTEX_MASK 0x000000ffL - -// MP1_MUTEX_3 -#define MP1_MUTEX_3__MUTEX_MASK 0x000000ffL - -// MP1_PUB_SCRATCH0 -#define MP1_PUB_SCRATCH0__DATA_MASK 0xffffffffL - -// MP1_PUB_SCRATCH1 -#define MP1_PUB_SCRATCH1__DATA_MASK 0xffffffffL - -// MP1_PUB_SCRATCH2 -#define MP1_PUB_SCRATCH2__DATA_MASK 0xffffffffL - -// MP1_PUB_SCRATCH3 -#define MP1_PUB_SCRATCH3__DATA_MASK 0xffffffffL - -// MP1_FW_CHRONO_LO -#define MP1_FW_CHRONO_LO__COUNT_MASK 0xffffffffL - -// MP1_FW_CHRONO_HI -#define MP1_FW_CHRONO_HI__COUNT_MASK 0xffffffffL - -// MP1_C2PMSG_0 -#define MP1_C2PMSG_0__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_1 -#define MP1_C2PMSG_1__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_2 -#define MP1_C2PMSG_2__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_3 -#define MP1_C2PMSG_3__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_4 -#define MP1_C2PMSG_4__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_5 -#define MP1_C2PMSG_5__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_6 -#define MP1_C2PMSG_6__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_7 -#define MP1_C2PMSG_7__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_8 -#define MP1_C2PMSG_8__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_9 -#define MP1_C2PMSG_9__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_10 -#define MP1_C2PMSG_10__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_11 -#define MP1_C2PMSG_11__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_12 -#define MP1_C2PMSG_12__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_13 -#define MP1_C2PMSG_13__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_14 -#define MP1_C2PMSG_14__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_15 -#define MP1_C2PMSG_15__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_16 -#define MP1_C2PMSG_16__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_17 -#define MP1_C2PMSG_17__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_18 -#define MP1_C2PMSG_18__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_19 -#define MP1_C2PMSG_19__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_20 -#define MP1_C2PMSG_20__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_21 -#define MP1_C2PMSG_21__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_22 -#define MP1_C2PMSG_22__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_23 -#define MP1_C2PMSG_23__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_24 -#define MP1_C2PMSG_24__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_25 -#define MP1_C2PMSG_25__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_26 -#define MP1_C2PMSG_26__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_27 -#define MP1_C2PMSG_27__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_28 -#define MP1_C2PMSG_28__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_29 -#define MP1_C2PMSG_29__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_30 -#define MP1_C2PMSG_30__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_31 -#define MP1_C2PMSG_31__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_32 -#define MP1_C2PMSG_32__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_33 -#define MP1_C2PMSG_33__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_34 -#define MP1_C2PMSG_34__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_35 -#define MP1_C2PMSG_35__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_36 -#define MP1_C2PMSG_36__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_37 -#define MP1_C2PMSG_37__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_38 -#define MP1_C2PMSG_38__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_39 -#define MP1_C2PMSG_39__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_40 -#define MP1_C2PMSG_40__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_41 -#define MP1_C2PMSG_41__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_42 -#define MP1_C2PMSG_42__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_43 -#define MP1_C2PMSG_43__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_44 -#define MP1_C2PMSG_44__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_45 -#define MP1_C2PMSG_45__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_46 -#define MP1_C2PMSG_46__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_47 -#define MP1_C2PMSG_47__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_48 -#define MP1_C2PMSG_48__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_49 -#define MP1_C2PMSG_49__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_50 -#define MP1_C2PMSG_50__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_51 -#define MP1_C2PMSG_51__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_52 -#define MP1_C2PMSG_52__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_53 -#define MP1_C2PMSG_53__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_54 -#define MP1_C2PMSG_54__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_55 -#define MP1_C2PMSG_55__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_56 -#define MP1_C2PMSG_56__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_57 -#define MP1_C2PMSG_57__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_58 -#define MP1_C2PMSG_58__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_59 -#define MP1_C2PMSG_59__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_60 -#define MP1_C2PMSG_60__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_61 -#define MP1_C2PMSG_61__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_62 -#define MP1_C2PMSG_62__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_63 -#define MP1_C2PMSG_63__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_64 -#define MP1_C2PMSG_64__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_65 -#define MP1_C2PMSG_65__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_66 -#define MP1_C2PMSG_66__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_67 -#define MP1_C2PMSG_67__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_68 -#define MP1_C2PMSG_68__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_69 -#define MP1_C2PMSG_69__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_70 -#define MP1_C2PMSG_70__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_71 -#define MP1_C2PMSG_71__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_72 -#define MP1_C2PMSG_72__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_73 -#define MP1_C2PMSG_73__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_74 -#define MP1_C2PMSG_74__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_75 -#define MP1_C2PMSG_75__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_76 -#define MP1_C2PMSG_76__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_77 -#define MP1_C2PMSG_77__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_78 -#define MP1_C2PMSG_78__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_79 -#define MP1_C2PMSG_79__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_80 -#define MP1_C2PMSG_80__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_81 -#define MP1_C2PMSG_81__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_82 -#define MP1_C2PMSG_82__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_83 -#define MP1_C2PMSG_83__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_84 -#define MP1_C2PMSG_84__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_85 -#define MP1_C2PMSG_85__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_86 -#define MP1_C2PMSG_86__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_87 -#define MP1_C2PMSG_87__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_88 -#define MP1_C2PMSG_88__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_89 -#define MP1_C2PMSG_89__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_90 -#define MP1_C2PMSG_90__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_91 -#define MP1_C2PMSG_91__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_92 -#define MP1_C2PMSG_92__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_93 -#define MP1_C2PMSG_93__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_94 -#define MP1_C2PMSG_94__CONTENT_MASK 0xffffffffL - -// MP1_C2PMSG_95 -#define MP1_C2PMSG_95__CONTENT_MASK 0xffffffffL - -// MP1_P2CMSG_0 -#define MP1_P2CMSG_0__CONTENT_MASK 0xffffffffL - -// MP1_P2CMSG_1 -#define MP1_P2CMSG_1__CONTENT_MASK 0xffffffffL - -// MP1_P2CMSG_2 -#define MP1_P2CMSG_2__CONTENT_MASK 0xffffffffL - -// MP1_P2CMSG_3 -#define MP1_P2CMSG_3__CONTENT_MASK 0xffffffffL - -// MP1_P2CMSG_INTEN -#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000fL - -// MP1_P2CMSG_INTSTS -#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L - -// MP1_P2SMSG_0 -#define MP1_P2SMSG_0__CONTENT_MASK 0xffffffffL - -// MP1_P2SMSG_1 -#define MP1_P2SMSG_1__CONTENT_MASK 0xffffffffL - -// MP1_P2SMSG_2 -#define MP1_P2SMSG_2__CONTENT_MASK 0xffffffffL - -// MP1_P2SMSG_3 -#define MP1_P2SMSG_3__CONTENT_MASK 0xffffffffL - -// MP1_P2SMSG_INTSTS -#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L - -// MP1_S2PMSG_0 -#define MP1_S2PMSG_0__CONTENT_MASK 0xffffffffL - -// MP1_PUB_RSMU_HCID -#define MP1_PUB_RSMU_HCID__HwRev_MASK 0x0000003fL -#define MP1_PUB_RSMU_HCID__HwMinVer_MASK 0x00001fc0L -#define MP1_PUB_RSMU_HCID__HwMajVer_MASK 0x000fe000L -#define MP1_PUB_RSMU_HCID__HwID_MASK 0xfff00000L - -// MP1_PUB_RSMU_SIID -#define MP1_PUB_RSMU_SIID__SwIfRev_MASK 0x0000003fL -#define MP1_PUB_RSMU_SIID__SwIfMinVer_MASK 0x00001fc0L -#define MP1_PUB_RSMU_SIID__SwIfMajVer_MASK 0x000fe000L -#define MP1_PUB_RSMU_SIID__SwIfID_MASK 0xfff00000L - -// MP1_SRBMTMR_0_CTRL0 -#define MP1_SRBMTMR_0_CTRL0__START_MASK 0x00000001L -#define MP1_SRBMTMR_0_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_SRBMTMR_0_CTRL0__DEC_MASK 0x00010000L -#define MP1_SRBMTMR_0_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_SRBMTMR_1_CTRL0 -#define MP1_SRBMTMR_1_CTRL0__START_MASK 0x00000001L -#define MP1_SRBMTMR_1_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_SRBMTMR_1_CTRL0__DEC_MASK 0x00010000L -#define MP1_SRBMTMR_1_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_SRBMTMR_0_CTRL1 -#define MP1_SRBMTMR_0_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_SRBMTMR_0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_SRBMTMR_0_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_SRBMTMR_0_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_SRBMTMR_1_CTRL1 -#define MP1_SRBMTMR_1_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_SRBMTMR_1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_SRBMTMR_1_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_SRBMTMR_1_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_SRBMTMR_0_CMP_AUTOINC -#define MP1_SRBMTMR_0_CMP_AUTOINC__AUTOINC_MASK 0x00000001L -#define MP1_SRBMTMR_0_CMP_AUTOINC__RESERVED_MASK 0xfffffffeL - -// MP1_SRBMTMR_1_CMP_AUTOINC -#define MP1_SRBMTMR_1_CMP_AUTOINC__AUTOINC_MASK 0x00000001L -#define MP1_SRBMTMR_1_CMP_AUTOINC__RESERVED_MASK 0xfffffffeL - -// MP1_SRBMTMR_0_INTEN -#define MP1_SRBMTMR_0_INTEN__INTEN_MASK 0x00000001L -#define MP1_SRBMTMR_0_INTEN__RESERVED_MASK 0xfffffffeL - -// MP1_SRBMTMR_1_INTEN -#define MP1_SRBMTMR_1_INTEN__INTEN_MASK 0x00000001L -#define MP1_SRBMTMR_1_INTEN__RESERVED_MASK 0xfffffffeL - -// MP1_SRBMTMR_OCMP_0_0 -#define MP1_SRBMTMR_OCMP_0_0__OCMP_MASK 0xffffffffL - -// MP1_SRBMTMR_OCMP_1_0 -#define MP1_SRBMTMR_OCMP_1_0__OCMP_MASK 0xffffffffL - -// MP1_SRBMTMR_0_CNT -#define MP1_SRBMTMR_0_CNT__COUNT_MASK 0xffffffffL - -// MP1_SRBMTMR_1_CNT -#define MP1_SRBMTMR_1_CNT__COUNT_MASK 0xffffffffL - -// MP1_ACP2MP_RESP -#define MP1_ACP2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_DC2MP_RESP -#define MP1_DC2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_UVD2MP_RESP -#define MP1_UVD2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_VCE2MP_RESP -#define MP1_VCE2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_RLC2MP_RESP -#define MP1_RLC2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_IH_MP0SW_INT -#define MP1_IH_MP0SW_INT__VALID_MASK 0x00000001L -#define MP1_IH_MP0SW_INT__ID_MASK 0x000001feL - -// MP1_IH_MP1SW_INT -#define MP1_IH_MP1SW_INT__VALID_MASK 0x00000001L -#define MP1_IH_MP1SW_INT__ID_MASK 0x000001feL - -// MP1_IH_SW_INT_CTRL -#define MP1_IH_SW_INT_CTRL__MAX_CREDIT_VALUE_MASK 0x0000001fL -#define MP1_IH_SW_INT_CTRL__MP0_SW_TRIG_MASK_MASK 0x00000020L -#define MP1_IH_SW_INT_CTRL__MP0_SW_INT_ACK_MASK 0x00000040L -#define MP1_IH_SW_INT_CTRL__MP1_SW_TRIG_MASK_MASK 0x00000080L -#define MP1_IH_SW_INT_CTRL__MP1_SW_INT_ACK_MASK 0x00000100L - -// MP1_IH_DISPTMR0_INT_CTRL -#define MP1_IH_DISPTMR0_INT_CTRL__STATUS_MASK 0x00000001L -#define MP1_IH_DISPTMR0_INT_CTRL__UNMASK_MASK 0x00000002L -#define MP1_IH_DISPTMR0_INT_CTRL__TYPE_MASK 0x00000004L -#define MP1_IH_DISPTMR0_INT_CTRL__ACK_MASK 0x00000008L -#define MP1_IH_DISPTMR0_INT_CTRL__MASK_MASK 0x00000010L - -// MP1_IH_DISPTMR1_INT_CTRL -#define MP1_IH_DISPTMR1_INT_CTRL__STATUS_MASK 0x00000001L -#define MP1_IH_DISPTMR1_INT_CTRL__UNMASK_MASK 0x00000002L -#define MP1_IH_DISPTMR1_INT_CTRL__TYPE_MASK 0x00000004L -#define MP1_IH_DISPTMR1_INT_CTRL__ACK_MASK 0x00000008L -#define MP1_IH_DISPTMR1_INT_CTRL__MASK_MASK 0x00000010L - -// MP1_FPS_CNT -#define MP1_FPS_CNT__COUNT_MASK 0xffffffffL - -// MP1_REVID -#define MP1_REVID__REVID_MASK 0xffffffffL - -// MP1_RSMU_HCID -#define MP1_RSMU_HCID__HwRev_MASK 0x0000003fL -#define MP1_RSMU_HCID__HwMinVer_MASK 0x00001fc0L -#define MP1_RSMU_HCID__HwMajVer_MASK 0x000fe000L -#define MP1_RSMU_HCID__HwID_MASK 0xfff00000L - -// MP1_RSMU_SIID -#define MP1_RSMU_SIID__SwIfRev_MASK 0x0000003fL -#define MP1_RSMU_SIID__SwIfMinVer_MASK 0x00001fc0L -#define MP1_RSMU_SIID__SwIfMajVer_MASK 0x000fe000L -#define MP1_RSMU_SIID__SwIfID_MASK 0xfff00000L - -// MP1_RAM_REPAIR_DONE -#define MP1_RAM_REPAIR_DONE__STATUS_MASK 0xffffffffL - -// MP1_RAM_REPAIR_RESULT -#define MP1_RAM_REPAIR_RESULT__PASS_MASK 0xffffffffL - -// MP1_FUSE_HARVESTING -#define MP1_FUSE_HARVESTING__DATA_MASK 0xffffffffL - -// MP1_FUSE_RMBITS -#define MP1_FUSE_RMBITS__RM_MASK 0x000001ffL -#define MP1_FUSE_RMBITS__RM_RESERVED_MASK 0x0000fe00L -#define MP1_FUSE_RMBITS__BC_MASK 0x003f0000L -#define MP1_FUSE_RMBITS__BC_RESERVED_MASK 0xffc00000L - -// MP1_SMS_CFG -#define MP1_SMS_CFG__SMS_RESETB_MASK 0x00000001L -#define MP1_SMS_CFG__RUN_BIHR_MASK 0x00000100L -#define MP1_SMS_CFG__RUN_MBIST_MASK 0x00000200L -#define MP1_SMS_CFG__SMS_FUSE_VALID_MASK 0x00010000L -#define MP1_SMS_CFG__SMS_NEXT_FETCH_MASK 0x01000000L -#define MP1_SMS_CFG__RAM_REPAIR_DONE_MASK 0x02000000L -#define MP1_SMS_CFG__RAM_BIST_FAIL_MASK 0x04000000L - -// MP1_FUSE_SMS_0 -#define MP1_FUSE_SMS_0__DATA_MASK 0xffffffffL - -// MP1_FUSE_SMS_1 -#define MP1_FUSE_SMS_1__DATA_MASK 0xffffffffL - -// MP1_FUSE_SMS_2 -#define MP1_FUSE_SMS_2__DATA_MASK 0xffffffffL - -// MP1_FUSE_SMS_3 -#define MP1_FUSE_SMS_3__DATA_MASK 0xffffffffL - -// MP1_FUSE_SMS_4 -#define MP1_FUSE_SMS_4__DATA_MASK 0xffffffffL - -// MP1_FUSE_SMS_5 -#define MP1_FUSE_SMS_5__DATA_MASK 0xffffffffL - -// MP1_FUSE_SMS_6 -#define MP1_FUSE_SMS_6__DATA_MASK 0xffffffffL - -// MP1_FUSE_SMS_7 -#define MP1_FUSE_SMS_7__DATA_MASK 0xffffffffL - -// MP1_ACC_VIO_INTSTS -#define MP1_ACC_VIO_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_ACC_VIO_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_ACC_VIO_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_ACC_VIO_INTSTS__INTSTS3_MASK 0x00000008L -#define MP1_ACC_VIO_INTSTS__INTSTS4_MASK 0x00000010L -#define MP1_ACC_VIO_INTSTS__INTSTS5_MASK 0x00000020L -#define MP1_ACC_VIO_INTSTS__INTSTS6_MASK 0x00000040L -#define MP1_ACC_VIO_INTSTS__INTSTS7_MASK 0x00000080L -#define MP1_ACC_VIO_INTSTS__INTSTS8_MASK 0x00000100L -#define MP1_ACC_VIO_INTSTS__INTSTS9_MASK 0x00000200L -#define MP1_ACC_VIO_INTSTS__INTSTS10_MASK 0x00000400L -#define MP1_ACC_VIO_INTSTS__INTSTS11_MASK 0x00000800L -#define MP1_ACC_VIO_INTSTS__INTSTS12_MASK 0x00001000L -#define MP1_ACC_VIO_INTSTS__INTSTS13_MASK 0x00002000L -#define MP1_ACC_VIO_INTSTS__INTSTS14_MASK 0x00004000L -#define MP1_ACC_VIO_INTSTS__INTSTS15_MASK 0x00008000L -#define MP1_ACC_VIO_INTSTS__INTSTS16_MASK 0x00010000L -#define MP1_ACC_VIO_INTSTS__INTSTS17_MASK 0x00020000L -#define MP1_ACC_VIO_INTSTS__INTSTS18_MASK 0x00040000L -#define MP1_ACC_VIO_INTSTS__INTSTS19_MASK 0x00080000L -#define MP1_ACC_VIO_INTSTS__INTSTS20_MASK 0x00100000L -#define MP1_ACC_VIO_INTSTS__INTSTS21_MASK 0x00200000L -#define MP1_ACC_VIO_INTSTS__INTSTS22_MASK 0x00400000L -#define MP1_ACC_VIO_INTSTS__INTSTS23_MASK 0x00800000L -#define MP1_ACC_VIO_INTSTS__INTSTS24_MASK 0x01000000L -#define MP1_ACC_VIO_INTSTS__INTSTS25_MASK 0x02000000L -#define MP1_ACC_VIO_INTSTS__INTSTS26_MASK 0x04000000L -#define MP1_ACC_VIO_INTSTS__INTSTS27_MASK 0x08000000L -#define MP1_ACC_VIO_INTSTS__INTSTS28_MASK 0x10000000L -#define MP1_ACC_VIO_INTSTS__INTSTS29_MASK 0x20000000L -#define MP1_ACC_VIO_INTSTS__INTSTS30_MASK 0x40000000L -#define MP1_ACC_VIO_INTSTS__INTSTS31_MASK 0x80000000L - -// MP1_TDR_MISC0_STATUS -#define MP1_TDR_MISC0_STATUS__DATA_MASK 0xffffffffL - -// MP1_EVCNTCTL -#define MP1_EVCNTCTL__EVENTCNT_EN_MASK 0x00000001L -#define MP1_EVCNTCTL__EVENTCNT_RSTB_MASK 0x00000002L -#define MP1_EVCNTCTL__EVENTCNT_SHADOW_MASK 0x00000004L - -// MP1_EVCNTSEL -#define MP1_EVCNTSEL__EVENT0_BLK_MASK 0x0000003fL -#define MP1_EVCNTSEL__EVENT0_SEL_MASK 0x00003f00L -#define MP1_EVCNTSEL__EVENT1_BLK_MASK 0x003f0000L -#define MP1_EVCNTSEL__EVENT1_SEL_MASK 0x3f000000L - -// MP1_EVCNT0 -#define MP1_EVCNT0__EVENTCNT0_MASK 0xffffffffL - -// MP1_EVCNT1 -#define MP1_EVCNT1__EVENTCNT1_MASK 0xffffffffL - -// MP1_EVCNTHI -#define MP1_EVCNTHI__EVENTCNT0_HI_MASK 0x000000ffL -#define MP1_EVCNTHI__EVENTCNT1_HI_MASK 0x00ff0000L - -// MP1_J2P_MBOX0 -#define MP1_J2P_MBOX0__MBX_MASK 0xffffffffL - -// MP1_J2P_MBOX1 -#define MP1_J2P_MBOX1__MBX_MASK 0xffffffffL - -// MP1_J2P_ATTR -#define MP1_J2P_ATTR__J2P_ATTR_MASK 0x00000003L - -// MP1_CRU_ACC_VIO_INTSTS -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS3_MASK 0x00000008L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS4_MASK 0x00000010L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS5_MASK 0x00000020L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS6_MASK 0x00000040L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS7_MASK 0x00000080L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS8_MASK 0x00000100L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS9_MASK 0x00000200L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS10_MASK 0x00000400L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS11_MASK 0x00000800L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS12_MASK 0x00001000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS13_MASK 0x00002000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS14_MASK 0x00004000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS15_MASK 0x00008000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS16_MASK 0x00010000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS17_MASK 0x00020000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS18_MASK 0x00040000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS19_MASK 0x00080000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS20_MASK 0x00100000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS21_MASK 0x00200000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS22_MASK 0x00400000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS23_MASK 0x00800000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS24_MASK 0x01000000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS25_MASK 0x02000000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS26_MASK 0x04000000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS27_MASK 0x08000000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS28_MASK 0x10000000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS29_MASK 0x20000000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS30_MASK 0x40000000L -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS31_MASK 0x80000000L - -// MP1_ACC_VIOL_LOG0 -#define MP1_ACC_VIOL_LOG0__AXI_ACC_VIO_LOG_MASK 0x7fffffffL -#define MP1_ACC_VIOL_LOG0__AXI_LOG_CLEAR_MASK 0x80000000L - -// MP1_ACC_VIOL_LOG1 -#define MP1_ACC_VIOL_LOG1__AXI_ACC_VIO_ADDR_MASK 0xffffffffL - -// MP1_SEC_SCRATCH0 -#define MP1_SEC_SCRATCH0__DATA_MASK 0xffffffffL - -// MP1_SEC_SCRATCH1 -#define MP1_SEC_SCRATCH1__DATA_MASK 0xffffffffL - -// MP1_SEC_SCRATCH2 -#define MP1_SEC_SCRATCH2__DATA_MASK 0xffffffffL - -// MP1_SEC_SCRATCH3 -#define MP1_SEC_SCRATCH3__DATA_MASK 0xffffffffL - -// MP1_STICKY -#define MP1_STICKY__DATA_MASK 0xffffffffL - -// MP1_CRU_MISC_CTRL -#define MP1_CRU_MISC_CTRL__ERROR_RESPONSE_ON_ACCVIOL_MASK 0x00000001L - -// MP1_SOFT_RESET_CTRL -#define MP1_SOFT_RESET_CTRL__MP_MMU_RESET_MASK 0x00000001L -#define MP1_SOFT_RESET_CTRL__MP_CPU_RESET_MASK 0x00000002L -#define MP1_SOFT_RESET_CTRL__MP_SMNIF_RESET_MASK 0x00000004L -#define MP1_SOFT_RESET_CTRL__MP_DMAC_RESET_MASK 0x00000008L -#define MP1_SOFT_RESET_CTRL__MP_HUBIFNB_RESET_MASK 0x00000010L -#define MP1_SOFT_RESET_CTRL__MP_SHUBIF_RESET_MASK 0x00000100L -#define MP1_SOFT_RESET_CTRL__MP_MHUBIF_RESET_MASK 0x00000200L - -// MP1_NS_PROT_FAULT_STATUS_0 -#define MP1_NS_PROT_FAULT_STATUS_0__MMU_CFG_NS0_VIOL_MASK 0x00000001L -#define MP1_NS_PROT_FAULT_STATUS_0__MMU_SRAM_NS0_VIOL_MASK 0x00000002L -#define MP1_NS_PROT_FAULT_STATUS_0__CRU_NS0_VIOL_MASK 0x00000010L - -// MP1_FW_MISC_CTRL -#define MP1_FW_MISC_CTRL__MP_FW_VALUE_MASK 0xffffffffL - -// MP1_AEB_STATUS_0 -#define MP1_AEB_STATUS_0__MP1_AEB_DBG_BUS_en_MASK 0x00000001L -#define MP1_AEB_STATUS_0__MP1_AEB_CPU_DBG_TDRs_en_MASK 0x00000002L -#define MP1_AEB_STATUS_0__MP1_AEB_JTAG_AXI_master_en_MASK 0x00000004L -#define MP1_AEB_STATUS_0__MP1_AEB_DIS_SCAN_DUMP_en_MASK 0x00000008L - -// MP1_PIC0_MASK_0 -#define MP1_PIC0_MASK_0__INTR_MASK_0_MASK 0x00000001L -#define MP1_PIC0_MASK_0__INTR_MASK_1_MASK 0x00000002L -#define MP1_PIC0_MASK_0__INTR_MASK_2_MASK 0x00000004L -#define MP1_PIC0_MASK_0__INTR_MASK_3_MASK 0x00000008L -#define MP1_PIC0_MASK_0__INTR_MASK_4_MASK 0x00000010L -#define MP1_PIC0_MASK_0__INTR_MASK_5_MASK 0x00000020L -#define MP1_PIC0_MASK_0__INTR_MASK_6_MASK 0x00000040L -#define MP1_PIC0_MASK_0__INTR_MASK_7_MASK 0x00000080L - -// MP1_PIC0_LEVEL_0 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_7_MASK 0x00000080L - -// MP1_PIC0_EDGE_0 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_7_MASK 0x00000080L - -// MP1_PIC0_PRIORITY_0 -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC0_PRIORITY_1 -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC0_STATUS_0 -#define MP1_PIC0_STATUS_0__INTR_FLAG_0_MASK 0x00000001L -#define MP1_PIC0_STATUS_0__INTR_FLAG_1_MASK 0x00000002L -#define MP1_PIC0_STATUS_0__INTR_FLAG_2_MASK 0x00000004L -#define MP1_PIC0_STATUS_0__INTR_FLAG_3_MASK 0x00000008L -#define MP1_PIC0_STATUS_0__INTR_FLAG_4_MASK 0x00000010L -#define MP1_PIC0_STATUS_0__INTR_FLAG_5_MASK 0x00000020L -#define MP1_PIC0_STATUS_0__INTR_FLAG_6_MASK 0x00000040L -#define MP1_PIC0_STATUS_0__INTR_FLAG_7_MASK 0x00000080L - -// MP1_PIC0_INTR -#define MP1_PIC0_INTR__INTR_LINE_MASK 0x00000001L -#define MP1_PIC0_INTR__RESERVED_MASK 0xfffffffeL - -// MP1_PIC0_ID -#define MP1_PIC0_ID__INTR_ID_MASK 0x000000ffL -#define MP1_PIC0_ID__RESERVED_MASK 0xffffff00L - -// MP1_PIC1_MASK_0 -#define MP1_PIC1_MASK_0__INTR_MASK_0_MASK 0x00000001L -#define MP1_PIC1_MASK_0__INTR_MASK_1_MASK 0x00000002L -#define MP1_PIC1_MASK_0__INTR_MASK_2_MASK 0x00000004L -#define MP1_PIC1_MASK_0__INTR_MASK_3_MASK 0x00000008L -#define MP1_PIC1_MASK_0__INTR_MASK_4_MASK 0x00000010L -#define MP1_PIC1_MASK_0__INTR_MASK_5_MASK 0x00000020L -#define MP1_PIC1_MASK_0__INTR_MASK_6_MASK 0x00000040L -#define MP1_PIC1_MASK_0__INTR_MASK_7_MASK 0x00000080L -#define MP1_PIC1_MASK_0__INTR_MASK_8_MASK 0x00000100L -#define MP1_PIC1_MASK_0__INTR_MASK_9_MASK 0x00000200L -#define MP1_PIC1_MASK_0__INTR_MASK_10_MASK 0x00000400L -#define MP1_PIC1_MASK_0__INTR_MASK_11_MASK 0x00000800L -#define MP1_PIC1_MASK_0__INTR_MASK_12_MASK 0x00001000L -#define MP1_PIC1_MASK_0__INTR_MASK_13_MASK 0x00002000L -#define MP1_PIC1_MASK_0__INTR_MASK_14_MASK 0x00004000L -#define MP1_PIC1_MASK_0__INTR_MASK_15_MASK 0x00008000L -#define MP1_PIC1_MASK_0__INTR_MASK_16_MASK 0x00010000L -#define MP1_PIC1_MASK_0__INTR_MASK_17_MASK 0x00020000L -#define MP1_PIC1_MASK_0__INTR_MASK_18_MASK 0x00040000L -#define MP1_PIC1_MASK_0__INTR_MASK_19_MASK 0x00080000L -#define MP1_PIC1_MASK_0__INTR_MASK_20_MASK 0x00100000L -#define MP1_PIC1_MASK_0__INTR_MASK_21_MASK 0x00200000L -#define MP1_PIC1_MASK_0__INTR_MASK_22_MASK 0x00400000L -#define MP1_PIC1_MASK_0__INTR_MASK_23_MASK 0x00800000L -#define MP1_PIC1_MASK_0__INTR_MASK_24_MASK 0x01000000L -#define MP1_PIC1_MASK_0__INTR_MASK_25_MASK 0x02000000L -#define MP1_PIC1_MASK_0__INTR_MASK_26_MASK 0x04000000L -#define MP1_PIC1_MASK_0__INTR_MASK_27_MASK 0x08000000L -#define MP1_PIC1_MASK_0__INTR_MASK_28_MASK 0x10000000L -#define MP1_PIC1_MASK_0__INTR_MASK_29_MASK 0x20000000L -#define MP1_PIC1_MASK_0__INTR_MASK_30_MASK 0x40000000L -#define MP1_PIC1_MASK_0__INTR_MASK_31_MASK 0x80000000L - -// MP1_PIC1_MASK_1 -#define MP1_PIC1_MASK_1__INTR_MASK_0_MASK 0x00000001L -#define MP1_PIC1_MASK_1__INTR_MASK_1_MASK 0x00000002L -#define MP1_PIC1_MASK_1__INTR_MASK_2_MASK 0x00000004L -#define MP1_PIC1_MASK_1__INTR_MASK_3_MASK 0x00000008L -#define MP1_PIC1_MASK_1__INTR_MASK_4_MASK 0x00000010L -#define MP1_PIC1_MASK_1__INTR_MASK_5_MASK 0x00000020L -#define MP1_PIC1_MASK_1__INTR_MASK_6_MASK 0x00000040L -#define MP1_PIC1_MASK_1__INTR_MASK_7_MASK 0x00000080L -#define MP1_PIC1_MASK_1__INTR_MASK_8_MASK 0x00000100L -#define MP1_PIC1_MASK_1__INTR_MASK_9_MASK 0x00000200L -#define MP1_PIC1_MASK_1__INTR_MASK_10_MASK 0x00000400L -#define MP1_PIC1_MASK_1__INTR_MASK_11_MASK 0x00000800L -#define MP1_PIC1_MASK_1__INTR_MASK_12_MASK 0x00001000L -#define MP1_PIC1_MASK_1__INTR_MASK_13_MASK 0x00002000L -#define MP1_PIC1_MASK_1__INTR_MASK_14_MASK 0x00004000L -#define MP1_PIC1_MASK_1__INTR_MASK_15_MASK 0x00008000L -#define MP1_PIC1_MASK_1__INTR_MASK_16_MASK 0x00010000L -#define MP1_PIC1_MASK_1__INTR_MASK_17_MASK 0x00020000L -#define MP1_PIC1_MASK_1__INTR_MASK_18_MASK 0x00040000L -#define MP1_PIC1_MASK_1__INTR_MASK_19_MASK 0x00080000L -#define MP1_PIC1_MASK_1__INTR_MASK_20_MASK 0x00100000L -#define MP1_PIC1_MASK_1__INTR_MASK_21_MASK 0x00200000L -#define MP1_PIC1_MASK_1__INTR_MASK_22_MASK 0x00400000L -#define MP1_PIC1_MASK_1__INTR_MASK_23_MASK 0x00800000L -#define MP1_PIC1_MASK_1__INTR_MASK_24_MASK 0x01000000L -#define MP1_PIC1_MASK_1__INTR_MASK_25_MASK 0x02000000L -#define MP1_PIC1_MASK_1__INTR_MASK_26_MASK 0x04000000L -#define MP1_PIC1_MASK_1__INTR_MASK_27_MASK 0x08000000L -#define MP1_PIC1_MASK_1__INTR_MASK_28_MASK 0x10000000L -#define MP1_PIC1_MASK_1__INTR_MASK_29_MASK 0x20000000L -#define MP1_PIC1_MASK_1__INTR_MASK_30_MASK 0x40000000L -#define MP1_PIC1_MASK_1__INTR_MASK_31_MASK 0x80000000L - -// MP1_PIC1_MASK_2 -#define MP1_PIC1_MASK_2__INTR_MASK_0_MASK 0x00000001L -#define MP1_PIC1_MASK_2__INTR_MASK_1_MASK 0x00000002L -#define MP1_PIC1_MASK_2__INTR_MASK_2_MASK 0x00000004L -#define MP1_PIC1_MASK_2__INTR_MASK_3_MASK 0x00000008L -#define MP1_PIC1_MASK_2__INTR_MASK_4_MASK 0x00000010L -#define MP1_PIC1_MASK_2__INTR_MASK_5_MASK 0x00000020L -#define MP1_PIC1_MASK_2__INTR_MASK_6_MASK 0x00000040L -#define MP1_PIC1_MASK_2__INTR_MASK_7_MASK 0x00000080L -#define MP1_PIC1_MASK_2__INTR_MASK_8_MASK 0x00000100L -#define MP1_PIC1_MASK_2__INTR_MASK_9_MASK 0x00000200L -#define MP1_PIC1_MASK_2__INTR_MASK_10_MASK 0x00000400L -#define MP1_PIC1_MASK_2__INTR_MASK_11_MASK 0x00000800L -#define MP1_PIC1_MASK_2__INTR_MASK_12_MASK 0x00001000L -#define MP1_PIC1_MASK_2__INTR_MASK_13_MASK 0x00002000L -#define MP1_PIC1_MASK_2__INTR_MASK_14_MASK 0x00004000L -#define MP1_PIC1_MASK_2__INTR_MASK_15_MASK 0x00008000L -#define MP1_PIC1_MASK_2__INTR_MASK_16_MASK 0x00010000L -#define MP1_PIC1_MASK_2__INTR_MASK_17_MASK 0x00020000L -#define MP1_PIC1_MASK_2__INTR_MASK_18_MASK 0x00040000L -#define MP1_PIC1_MASK_2__INTR_MASK_19_MASK 0x00080000L -#define MP1_PIC1_MASK_2__INTR_MASK_20_MASK 0x00100000L -#define MP1_PIC1_MASK_2__INTR_MASK_21_MASK 0x00200000L -#define MP1_PIC1_MASK_2__INTR_MASK_22_MASK 0x00400000L -#define MP1_PIC1_MASK_2__INTR_MASK_23_MASK 0x00800000L -#define MP1_PIC1_MASK_2__INTR_MASK_24_MASK 0x01000000L -#define MP1_PIC1_MASK_2__INTR_MASK_25_MASK 0x02000000L -#define MP1_PIC1_MASK_2__INTR_MASK_26_MASK 0x04000000L -#define MP1_PIC1_MASK_2__INTR_MASK_27_MASK 0x08000000L -#define MP1_PIC1_MASK_2__INTR_MASK_28_MASK 0x10000000L -#define MP1_PIC1_MASK_2__INTR_MASK_29_MASK 0x20000000L -#define MP1_PIC1_MASK_2__INTR_MASK_30_MASK 0x40000000L -#define MP1_PIC1_MASK_2__INTR_MASK_31_MASK 0x80000000L - -// MP1_PIC1_MASK_3 -#define MP1_PIC1_MASK_3__INTR_MASK_0_MASK 0x00000001L -#define MP1_PIC1_MASK_3__INTR_MASK_1_MASK 0x00000002L -#define MP1_PIC1_MASK_3__INTR_MASK_2_MASK 0x00000004L -#define MP1_PIC1_MASK_3__INTR_MASK_3_MASK 0x00000008L -#define MP1_PIC1_MASK_3__INTR_MASK_4_MASK 0x00000010L -#define MP1_PIC1_MASK_3__INTR_MASK_5_MASK 0x00000020L -#define MP1_PIC1_MASK_3__INTR_MASK_6_MASK 0x00000040L -#define MP1_PIC1_MASK_3__INTR_MASK_7_MASK 0x00000080L -#define MP1_PIC1_MASK_3__INTR_MASK_8_MASK 0x00000100L -#define MP1_PIC1_MASK_3__INTR_MASK_9_MASK 0x00000200L -#define MP1_PIC1_MASK_3__INTR_MASK_10_MASK 0x00000400L -#define MP1_PIC1_MASK_3__INTR_MASK_11_MASK 0x00000800L -#define MP1_PIC1_MASK_3__INTR_MASK_12_MASK 0x00001000L -#define MP1_PIC1_MASK_3__INTR_MASK_13_MASK 0x00002000L -#define MP1_PIC1_MASK_3__INTR_MASK_14_MASK 0x00004000L -#define MP1_PIC1_MASK_3__INTR_MASK_15_MASK 0x00008000L -#define MP1_PIC1_MASK_3__INTR_MASK_16_MASK 0x00010000L -#define MP1_PIC1_MASK_3__INTR_MASK_17_MASK 0x00020000L -#define MP1_PIC1_MASK_3__INTR_MASK_18_MASK 0x00040000L -#define MP1_PIC1_MASK_3__INTR_MASK_19_MASK 0x00080000L -#define MP1_PIC1_MASK_3__INTR_MASK_20_MASK 0x00100000L -#define MP1_PIC1_MASK_3__INTR_MASK_21_MASK 0x00200000L -#define MP1_PIC1_MASK_3__INTR_MASK_22_MASK 0x00400000L -#define MP1_PIC1_MASK_3__INTR_MASK_23_MASK 0x00800000L -#define MP1_PIC1_MASK_3__INTR_MASK_24_MASK 0x01000000L -#define MP1_PIC1_MASK_3__INTR_MASK_25_MASK 0x02000000L -#define MP1_PIC1_MASK_3__INTR_MASK_26_MASK 0x04000000L -#define MP1_PIC1_MASK_3__INTR_MASK_27_MASK 0x08000000L -#define MP1_PIC1_MASK_3__INTR_MASK_28_MASK 0x10000000L -#define MP1_PIC1_MASK_3__INTR_MASK_29_MASK 0x20000000L -#define MP1_PIC1_MASK_3__INTR_MASK_30_MASK 0x40000000L -#define MP1_PIC1_MASK_3__INTR_MASK_31_MASK 0x80000000L - -// MP1_PIC1_LEVEL_0 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_LEVEL_1 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_LEVEL_2 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_LEVEL_3 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_EDGE_0 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_EDGE_1 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_EDGE_2 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_EDGE_3 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_0_MASK 0x00000001L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_1_MASK 0x00000002L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_2_MASK 0x00000004L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_3_MASK 0x00000008L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_4_MASK 0x00000010L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_5_MASK 0x00000020L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_6_MASK 0x00000040L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_7_MASK 0x00000080L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_8_MASK 0x00000100L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_9_MASK 0x00000200L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_10_MASK 0x00000400L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_11_MASK 0x00000800L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_12_MASK 0x00001000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_13_MASK 0x00002000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_14_MASK 0x00004000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_15_MASK 0x00008000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_16_MASK 0x00010000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_17_MASK 0x00020000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_18_MASK 0x00040000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_19_MASK 0x00080000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_20_MASK 0x00100000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_21_MASK 0x00200000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_22_MASK 0x00400000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_23_MASK 0x00800000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_24_MASK 0x01000000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_25_MASK 0x02000000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_26_MASK 0x04000000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_27_MASK 0x08000000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_28_MASK 0x10000000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_29_MASK 0x20000000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_30_MASK 0x40000000L -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_31_MASK 0x80000000L - -// MP1_PIC1_PRIORITY_0 -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_1 -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_2 -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_3 -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_4 -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_5 -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_6 -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_7 -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_8 -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_9 -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_10 -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_11 -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_12 -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_13 -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_14 -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_15 -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_16 -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_17 -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_18 -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_19 -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_20 -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_21 -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_22 -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_23 -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_24 -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_25 -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_26 -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_27 -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_28 -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_29 -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_30 -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_PRIORITY_31 -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_0_MASK 0x000000ffL -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_1_MASK 0x0000ff00L -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_2_MASK 0x00ff0000L -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_3_MASK 0xff000000L - -// MP1_PIC1_STATUS_0 -#define MP1_PIC1_STATUS_0__INTR_FLAG_0_MASK 0x00000001L -#define MP1_PIC1_STATUS_0__INTR_FLAG_1_MASK 0x00000002L -#define MP1_PIC1_STATUS_0__INTR_FLAG_2_MASK 0x00000004L -#define MP1_PIC1_STATUS_0__INTR_FLAG_3_MASK 0x00000008L -#define MP1_PIC1_STATUS_0__INTR_FLAG_4_MASK 0x00000010L -#define MP1_PIC1_STATUS_0__INTR_FLAG_5_MASK 0x00000020L -#define MP1_PIC1_STATUS_0__INTR_FLAG_6_MASK 0x00000040L -#define MP1_PIC1_STATUS_0__INTR_FLAG_7_MASK 0x00000080L -#define MP1_PIC1_STATUS_0__INTR_FLAG_8_MASK 0x00000100L -#define MP1_PIC1_STATUS_0__INTR_FLAG_9_MASK 0x00000200L -#define MP1_PIC1_STATUS_0__INTR_FLAG_10_MASK 0x00000400L -#define MP1_PIC1_STATUS_0__INTR_FLAG_11_MASK 0x00000800L -#define MP1_PIC1_STATUS_0__INTR_FLAG_12_MASK 0x00001000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_13_MASK 0x00002000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_14_MASK 0x00004000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_15_MASK 0x00008000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_16_MASK 0x00010000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_17_MASK 0x00020000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_18_MASK 0x00040000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_19_MASK 0x00080000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_20_MASK 0x00100000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_21_MASK 0x00200000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_22_MASK 0x00400000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_23_MASK 0x00800000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_24_MASK 0x01000000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_25_MASK 0x02000000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_26_MASK 0x04000000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_27_MASK 0x08000000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_28_MASK 0x10000000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_29_MASK 0x20000000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_30_MASK 0x40000000L -#define MP1_PIC1_STATUS_0__INTR_FLAG_31_MASK 0x80000000L - -// MP1_PIC1_STATUS_1 -#define MP1_PIC1_STATUS_1__INTR_FLAG_0_MASK 0x00000001L -#define MP1_PIC1_STATUS_1__INTR_FLAG_1_MASK 0x00000002L -#define MP1_PIC1_STATUS_1__INTR_FLAG_2_MASK 0x00000004L -#define MP1_PIC1_STATUS_1__INTR_FLAG_3_MASK 0x00000008L -#define MP1_PIC1_STATUS_1__INTR_FLAG_4_MASK 0x00000010L -#define MP1_PIC1_STATUS_1__INTR_FLAG_5_MASK 0x00000020L -#define MP1_PIC1_STATUS_1__INTR_FLAG_6_MASK 0x00000040L -#define MP1_PIC1_STATUS_1__INTR_FLAG_7_MASK 0x00000080L -#define MP1_PIC1_STATUS_1__INTR_FLAG_8_MASK 0x00000100L -#define MP1_PIC1_STATUS_1__INTR_FLAG_9_MASK 0x00000200L -#define MP1_PIC1_STATUS_1__INTR_FLAG_10_MASK 0x00000400L -#define MP1_PIC1_STATUS_1__INTR_FLAG_11_MASK 0x00000800L -#define MP1_PIC1_STATUS_1__INTR_FLAG_12_MASK 0x00001000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_13_MASK 0x00002000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_14_MASK 0x00004000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_15_MASK 0x00008000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_16_MASK 0x00010000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_17_MASK 0x00020000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_18_MASK 0x00040000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_19_MASK 0x00080000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_20_MASK 0x00100000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_21_MASK 0x00200000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_22_MASK 0x00400000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_23_MASK 0x00800000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_24_MASK 0x01000000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_25_MASK 0x02000000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_26_MASK 0x04000000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_27_MASK 0x08000000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_28_MASK 0x10000000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_29_MASK 0x20000000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_30_MASK 0x40000000L -#define MP1_PIC1_STATUS_1__INTR_FLAG_31_MASK 0x80000000L - -// MP1_PIC1_STATUS_2 -#define MP1_PIC1_STATUS_2__INTR_FLAG_0_MASK 0x00000001L -#define MP1_PIC1_STATUS_2__INTR_FLAG_1_MASK 0x00000002L -#define MP1_PIC1_STATUS_2__INTR_FLAG_2_MASK 0x00000004L -#define MP1_PIC1_STATUS_2__INTR_FLAG_3_MASK 0x00000008L -#define MP1_PIC1_STATUS_2__INTR_FLAG_4_MASK 0x00000010L -#define MP1_PIC1_STATUS_2__INTR_FLAG_5_MASK 0x00000020L -#define MP1_PIC1_STATUS_2__INTR_FLAG_6_MASK 0x00000040L -#define MP1_PIC1_STATUS_2__INTR_FLAG_7_MASK 0x00000080L -#define MP1_PIC1_STATUS_2__INTR_FLAG_8_MASK 0x00000100L -#define MP1_PIC1_STATUS_2__INTR_FLAG_9_MASK 0x00000200L -#define MP1_PIC1_STATUS_2__INTR_FLAG_10_MASK 0x00000400L -#define MP1_PIC1_STATUS_2__INTR_FLAG_11_MASK 0x00000800L -#define MP1_PIC1_STATUS_2__INTR_FLAG_12_MASK 0x00001000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_13_MASK 0x00002000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_14_MASK 0x00004000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_15_MASK 0x00008000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_16_MASK 0x00010000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_17_MASK 0x00020000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_18_MASK 0x00040000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_19_MASK 0x00080000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_20_MASK 0x00100000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_21_MASK 0x00200000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_22_MASK 0x00400000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_23_MASK 0x00800000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_24_MASK 0x01000000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_25_MASK 0x02000000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_26_MASK 0x04000000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_27_MASK 0x08000000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_28_MASK 0x10000000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_29_MASK 0x20000000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_30_MASK 0x40000000L -#define MP1_PIC1_STATUS_2__INTR_FLAG_31_MASK 0x80000000L - -// MP1_PIC1_STATUS_3 -#define MP1_PIC1_STATUS_3__INTR_FLAG_0_MASK 0x00000001L -#define MP1_PIC1_STATUS_3__INTR_FLAG_1_MASK 0x00000002L -#define MP1_PIC1_STATUS_3__INTR_FLAG_2_MASK 0x00000004L -#define MP1_PIC1_STATUS_3__INTR_FLAG_3_MASK 0x00000008L -#define MP1_PIC1_STATUS_3__INTR_FLAG_4_MASK 0x00000010L -#define MP1_PIC1_STATUS_3__INTR_FLAG_5_MASK 0x00000020L -#define MP1_PIC1_STATUS_3__INTR_FLAG_6_MASK 0x00000040L -#define MP1_PIC1_STATUS_3__INTR_FLAG_7_MASK 0x00000080L -#define MP1_PIC1_STATUS_3__INTR_FLAG_8_MASK 0x00000100L -#define MP1_PIC1_STATUS_3__INTR_FLAG_9_MASK 0x00000200L -#define MP1_PIC1_STATUS_3__INTR_FLAG_10_MASK 0x00000400L -#define MP1_PIC1_STATUS_3__INTR_FLAG_11_MASK 0x00000800L -#define MP1_PIC1_STATUS_3__INTR_FLAG_12_MASK 0x00001000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_13_MASK 0x00002000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_14_MASK 0x00004000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_15_MASK 0x00008000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_16_MASK 0x00010000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_17_MASK 0x00020000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_18_MASK 0x00040000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_19_MASK 0x00080000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_20_MASK 0x00100000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_21_MASK 0x00200000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_22_MASK 0x00400000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_23_MASK 0x00800000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_24_MASK 0x01000000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_25_MASK 0x02000000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_26_MASK 0x04000000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_27_MASK 0x08000000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_28_MASK 0x10000000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_29_MASK 0x20000000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_30_MASK 0x40000000L -#define MP1_PIC1_STATUS_3__INTR_FLAG_31_MASK 0x80000000L - -// MP1_PIC1_INTR -#define MP1_PIC1_INTR__INTR_LINE_MASK 0x00000001L -#define MP1_PIC1_INTR__RESERVED_MASK 0xfffffffeL - -// MP1_PIC1_ID -#define MP1_PIC1_ID__INTR_ID_MASK 0x000000ffL -#define MP1_PIC1_ID__RESERVED_MASK 0xffffff00L - -// MP1_TIMER_0_CTRL0 -#define MP1_TIMER_0_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_0_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_0_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_0_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_1_CTRL0 -#define MP1_TIMER_1_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_1_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_1_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_1_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_2_CTRL0 -#define MP1_TIMER_2_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_2_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_2_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_2_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_3_CTRL0 -#define MP1_TIMER_3_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_3_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_3_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_3_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_4_CTRL0 -#define MP1_TIMER_4_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_4_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_4_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_4_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_5_CTRL0 -#define MP1_TIMER_5_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_5_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_5_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_5_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_6_CTRL0 -#define MP1_TIMER_6_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_6_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_6_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_6_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_7_CTRL0 -#define MP1_TIMER_7_CTRL0__START_MASK 0x00000001L -#define MP1_TIMER_7_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_TIMER_7_CTRL0__DEC_MASK 0x00010000L -#define MP1_TIMER_7_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_TIMER_0_CTRL1 -#define MP1_TIMER_0_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_0_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_0_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_1_CTRL1 -#define MP1_TIMER_1_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_1_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_1_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_2_CTRL1 -#define MP1_TIMER_2_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_2_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_2_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_2_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_3_CTRL1 -#define MP1_TIMER_3_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_3_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_3_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_3_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_4_CTRL1 -#define MP1_TIMER_4_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_4_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_4_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_4_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_5_CTRL1 -#define MP1_TIMER_5_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_5_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_5_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_5_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_6_CTRL1 -#define MP1_TIMER_6_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_6_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_6_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_6_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_7_CTRL1 -#define MP1_TIMER_7_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_TIMER_7_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_TIMER_7_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_TIMER_7_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_TIMER_0_CMP_AUTOINC -#define MP1_TIMER_0_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_0_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_1_CMP_AUTOINC -#define MP1_TIMER_1_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_1_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_2_CMP_AUTOINC -#define MP1_TIMER_2_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_2_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_3_CMP_AUTOINC -#define MP1_TIMER_3_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_3_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_4_CMP_AUTOINC -#define MP1_TIMER_4_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_4_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_5_CMP_AUTOINC -#define MP1_TIMER_5_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_5_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_6_CMP_AUTOINC -#define MP1_TIMER_6_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_6_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_7_CMP_AUTOINC -#define MP1_TIMER_7_CMP_AUTOINC__AUTOINC_MASK 0x0000000fL -#define MP1_TIMER_7_CMP_AUTOINC__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_0_INTEN -#define MP1_TIMER_0_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_0_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_1_INTEN -#define MP1_TIMER_1_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_1_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_2_INTEN -#define MP1_TIMER_2_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_2_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_3_INTEN -#define MP1_TIMER_3_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_3_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_4_INTEN -#define MP1_TIMER_4_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_4_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_5_INTEN -#define MP1_TIMER_5_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_5_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_6_INTEN -#define MP1_TIMER_6_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_6_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_7_INTEN -#define MP1_TIMER_7_INTEN__INTEN_MASK 0x0000000fL -#define MP1_TIMER_7_INTEN__RESERVED_MASK 0xfffffff0L - -// MP1_TIMER_OCMP_0_0 -#define MP1_TIMER_OCMP_0_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_1_0 -#define MP1_TIMER_OCMP_1_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_2_0 -#define MP1_TIMER_OCMP_2_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_3_0 -#define MP1_TIMER_OCMP_3_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_4_0 -#define MP1_TIMER_OCMP_4_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_5_0 -#define MP1_TIMER_OCMP_5_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_6_0 -#define MP1_TIMER_OCMP_6_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_7_0 -#define MP1_TIMER_OCMP_7_0__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_0_1 -#define MP1_TIMER_OCMP_0_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_1_1 -#define MP1_TIMER_OCMP_1_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_2_1 -#define MP1_TIMER_OCMP_2_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_3_1 -#define MP1_TIMER_OCMP_3_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_4_1 -#define MP1_TIMER_OCMP_4_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_5_1 -#define MP1_TIMER_OCMP_5_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_6_1 -#define MP1_TIMER_OCMP_6_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_7_1 -#define MP1_TIMER_OCMP_7_1__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_0_2 -#define MP1_TIMER_OCMP_0_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_1_2 -#define MP1_TIMER_OCMP_1_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_2_2 -#define MP1_TIMER_OCMP_2_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_3_2 -#define MP1_TIMER_OCMP_3_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_4_2 -#define MP1_TIMER_OCMP_4_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_5_2 -#define MP1_TIMER_OCMP_5_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_6_2 -#define MP1_TIMER_OCMP_6_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_7_2 -#define MP1_TIMER_OCMP_7_2__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_0_3 -#define MP1_TIMER_OCMP_0_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_1_3 -#define MP1_TIMER_OCMP_1_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_2_3 -#define MP1_TIMER_OCMP_2_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_3_3 -#define MP1_TIMER_OCMP_3_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_4_3 -#define MP1_TIMER_OCMP_4_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_5_3 -#define MP1_TIMER_OCMP_5_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_6_3 -#define MP1_TIMER_OCMP_6_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_OCMP_7_3 -#define MP1_TIMER_OCMP_7_3__OCMP_MASK 0xffffffffL - -// MP1_TIMER_0_CNT -#define MP1_TIMER_0_CNT__COUNT_MASK 0xffffffffL - -// MP1_TIMER_1_CNT -#define MP1_TIMER_1_CNT__COUNT_MASK 0xffffffffL - -// MP1_TIMER_2_CNT -#define MP1_TIMER_2_CNT__COUNT_MASK 0xffffffffL - -// MP1_TIMER_3_CNT -#define MP1_TIMER_3_CNT__COUNT_MASK 0xffffffffL - -// MP1_TIMER_4_CNT -#define MP1_TIMER_4_CNT__COUNT_MASK 0xffffffffL - -// MP1_TIMER_5_CNT -#define MP1_TIMER_5_CNT__COUNT_MASK 0xffffffffL - -// MP1_TIMER_6_CNT -#define MP1_TIMER_6_CNT__COUNT_MASK 0xffffffffL - -// MP1_TIMER_7_CNT -#define MP1_TIMER_7_CNT__COUNT_MASK 0xffffffffL - -// MP1_C2PMSG_ATTR_0 -#define MP1_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xffffffffL - -// MP1_C2PMSG_ATTR_1 -#define MP1_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xffffffffL - -// MP1_C2PMSG_ATTR_2 -#define MP1_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xffffffffL - -// MP1_C2PMSG_ATTR_3 -#define MP1_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xffffffffL - -// MP1_C2PMSG_ATTR_4 -#define MP1_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xffffffffL - -// MP1_C2PMSG_ATTR_5 -#define MP1_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xffffffffL - -// MP1_P2CMSG_ATTR -#define MP1_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000ffL - -// MP1_S2PMSG_ATTR -#define MP1_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L - -// MP1_P2SMSG_ATTR -#define MP1_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000ffL - -// MP1_SMN_SRBMTMR_0_CTRL0 -#define MP1_SMN_SRBMTMR_0_CTRL0__START_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_0_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_SMN_SRBMTMR_0_CTRL0__DEC_MASK 0x00010000L -#define MP1_SMN_SRBMTMR_0_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_SMN_SRBMTMR_1_CTRL0 -#define MP1_SMN_SRBMTMR_1_CTRL0__START_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_1_CTRL0__CLEAR_MASK 0x00000100L -#define MP1_SMN_SRBMTMR_1_CTRL0__DEC_MASK 0x00010000L -#define MP1_SMN_SRBMTMR_1_CTRL0__PULSE_COUNT_MODE_MASK 0x01000000L - -// MP1_SMN_SRBMTMR_0_CTRL1 -#define MP1_SMN_SRBMTMR_0_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_SMN_SRBMTMR_0_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_SMN_SRBMTMR_0_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_SMN_SRBMTMR_1_CTRL1 -#define MP1_SMN_SRBMTMR_1_CTRL1__PWM_OUTPUT_EN_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x00000100L -#define MP1_SMN_SRBMTMR_1_CTRL1__TIMER_SATURATION_EN_MASK 0x00010000L -#define MP1_SMN_SRBMTMR_1_CTRL1__RESERVED_MASK 0xff000000L - -// MP1_SMN_SRBMTMR_0_CMP_AUTOINC -#define MP1_SMN_SRBMTMR_0_CMP_AUTOINC__AUTOINC_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_0_CMP_AUTOINC__RESERVED_RW_MASK 0x00000002L -#define MP1_SMN_SRBMTMR_0_CMP_AUTOINC__RESERVED_MASK 0xfffffffcL - -// MP1_SMN_SRBMTMR_1_CMP_AUTOINC -#define MP1_SMN_SRBMTMR_1_CMP_AUTOINC__AUTOINC_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_1_CMP_AUTOINC__RESERVED_RW_MASK 0x00000002L -#define MP1_SMN_SRBMTMR_1_CMP_AUTOINC__RESERVED_MASK 0xfffffffcL - -// MP1_SMN_SRBMTMR_0_INTEN -#define MP1_SMN_SRBMTMR_0_INTEN__INTEN_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_0_INTEN__RESERVED_MASK 0xfffffffeL - -// MP1_SMN_SRBMTMR_1_INTEN -#define MP1_SMN_SRBMTMR_1_INTEN__INTEN_MASK 0x00000001L -#define MP1_SMN_SRBMTMR_1_INTEN__RESERVED_MASK 0xfffffffeL - -// MP1_SMN_SRBMTMR_OCMP_0_0 -#define MP1_SMN_SRBMTMR_OCMP_0_0__OCMP_MASK 0xffffffffL - -// MP1_SMN_SRBMTMR_OCMP_1_0 -#define MP1_SMN_SRBMTMR_OCMP_1_0__OCMP_MASK 0xffffffffL - -// MP1_SMN_SRBMTMR_0_CNT -#define MP1_SMN_SRBMTMR_0_CNT__COUNT_MASK 0xffffffffL - -// MP1_SMN_SRBMTMR_1_CNT -#define MP1_SMN_SRBMTMR_1_CNT__COUNT_MASK 0xffffffffL - -// MP1_SMN_ACP2MP_RESP -#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_SMN_DC2MP_RESP -#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_SMN_UVD2MP_RESP -#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_SMN_VCE2MP_RESP -#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_SMN_RLC2MP_RESP -#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_32 -#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_33 -#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_34 -#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_35 -#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_36 -#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_37 -#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_38 -#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_39 -#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_40 -#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_41 -#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_42 -#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_43 -#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_44 -#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_45 -#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_46 -#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_47 -#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_48 -#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_49 -#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_50 -#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_51 -#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_52 -#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_53 -#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_54 -#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_55 -#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_56 -#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_57 -#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_58 -#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_59 -#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_60 -#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_61 -#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_62 -#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_63 -#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_64 -#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_65 -#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_66 -#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_67 -#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_68 -#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_69 -#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_70 -#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_71 -#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_72 -#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_73 -#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_74 -#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_75 -#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_76 -#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_77 -#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_78 -#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_79 -#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_80 -#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_81 -#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_82 -#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_83 -#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_84 -#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_85 -#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_86 -#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_87 -#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_88 -#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_89 -#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_90 -#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_91 -#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_92 -#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_93 -#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_94 -#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xffffffffL - -// MP1_SMN_C2PMSG_95 -#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xffffffffL - -// MP1_SMN_IH_MP0SW_INT -#define MP1_SMN_IH_MP0SW_INT__VALID_MASK 0x00000001L -#define MP1_SMN_IH_MP0SW_INT__ID_MASK 0x000001feL - -// MP1_SMN_IH_MP1SW_INT -#define MP1_SMN_IH_MP1SW_INT__VALID_MASK 0x00000001L -#define MP1_SMN_IH_MP1SW_INT__ID_MASK 0x000001feL - -// MP1_SMN_IH_SW_INT_CTRL -#define MP1_SMN_IH_SW_INT_CTRL__MAX_CREDIT_VALUE_MASK 0x0000001fL -#define MP1_SMN_IH_SW_INT_CTRL__MP0_SW_TRIG_MASK_MASK 0x00000020L -#define MP1_SMN_IH_SW_INT_CTRL__MP0_SW_INT_ACK_MASK 0x00000040L -#define MP1_SMN_IH_SW_INT_CTRL__MP1_SW_TRIG_MASK_MASK 0x00000080L -#define MP1_SMN_IH_SW_INT_CTRL__MP1_SW_INT_ACK_MASK 0x00000100L - -// MP1_SMN_IH_DISPTMR0_INT_CTRL -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__STATUS_MASK 0x00000001L -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__UNMASK_MASK 0x00000002L -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__TYPE_MASK 0x00000004L -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__ACK_MASK 0x00000008L -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__MASK_MASK 0x00000010L - -// MP1_SMN_IH_DISPTMR1_INT_CTRL -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__STATUS_MASK 0x00000001L -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__UNMASK_MASK 0x00000002L -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__TYPE_MASK 0x00000004L -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__ACK_MASK 0x00000008L -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__MASK_MASK 0x00000010L - -// MP1_SMN_FPS_CNT -#define MP1_SMN_FPS_CNT__COUNT_MASK 0xffffffffL - -// MP1_RSMU_PUB_RSMU_HCID -#define MP1_RSMU_PUB_RSMU_HCID__HwRev_MASK 0x0000003fL -#define MP1_RSMU_PUB_RSMU_HCID__HwMinVer_MASK 0x00001fc0L -#define MP1_RSMU_PUB_RSMU_HCID__HwMajVer_MASK 0x000fe000L -#define MP1_RSMU_PUB_RSMU_HCID__HwID_MASK 0xfff00000L - -// MP1_RSMU_PUB_RSMU_SIID -#define MP1_RSMU_PUB_RSMU_SIID__SwIfRev_MASK 0x0000003fL -#define MP1_RSMU_PUB_RSMU_SIID__SwIfMinVer_MASK 0x00001fc0L -#define MP1_RSMU_PUB_RSMU_SIID__SwIfMajVer_MASK 0x000fe000L -#define MP1_RSMU_PUB_RSMU_SIID__SwIfID_MASK 0xfff00000L - -// MP1_PMI_0_START -#define MP1_PMI_0_START__ADDR_MASK 0x0003ffffL -#define MP1_PMI_0_START__ENABLE_MASK 0x80000000L - -// MP1_PMI_0_FIFO -#define MP1_PMI_0_FIFO__DEPTH_MASK 0x0000000fL - -// MP1_PMI_0_STATUS -#define MP1_PMI_0_STATUS__FULL_MASK 0x00000001L -#define MP1_PMI_0_STATUS__EMPTY_MASK 0x00000002L - -// MP1_PMI_0_READ_POINTER -#define MP1_PMI_0_READ_POINTER__CURRENT_MASK 0x0003ffffL - -// MP1_PMI_0_WRITE_POINTER -#define MP1_PMI_0_WRITE_POINTER__CURRENT_MASK 0x0003ffffL - -// MP1_PMI_1_START -#define MP1_PMI_1_START__ADDR_MASK 0x0003ffffL -#define MP1_PMI_1_START__ENABLE_MASK 0x80000000L - -// MP1_PMI_1_FIFO -#define MP1_PMI_1_FIFO__DEPTH_MASK 0x0000000fL - -// MP1_PMI_1_STATUS -#define MP1_PMI_1_STATUS__FULL_MASK 0x00000001L -#define MP1_PMI_1_STATUS__EMPTY_MASK 0x00000002L - -// MP1_PMI_1_READ_POINTER -#define MP1_PMI_1_READ_POINTER__CURRENT_MASK 0x0003ffffL - -// MP1_PMI_1_WRITE_POINTER -#define MP1_PMI_1_WRITE_POINTER__CURRENT_MASK 0x0003ffffL - -// MP1_PMI_2_START -#define MP1_PMI_2_START__ADDR_MASK 0x0003ffffL -#define MP1_PMI_2_START__ENABLE_MASK 0x80000000L - -// MP1_PMI_2_FIFO -#define MP1_PMI_2_FIFO__DEPTH_MASK 0x0000000fL - -// MP1_PMI_2_STATUS -#define MP1_PMI_2_STATUS__FULL_MASK 0x00000001L -#define MP1_PMI_2_STATUS__EMPTY_MASK 0x00000002L - -// MP1_PMI_2_READ_POINTER -#define MP1_PMI_2_READ_POINTER__CURRENT_MASK 0x0003ffffL - -// MP1_PMI_2_WRITE_POINTER -#define MP1_PMI_2_WRITE_POINTER__CURRENT_MASK 0x0003ffffL - -// MP1_PMI_OUT_CONFIG -#define MP1_PMI_OUT_CONFIG__PMI0_OUT_SEL_MASK 0x00000003L -#define MP1_PMI_OUT_CONFIG__PMI1_OUT_SEL_MASK 0x0000000cL -#define MP1_PMI_OUT_CONFIG__PMI2_OUT_SEL_MASK 0x00000030L - -// MP1_PMI_RELOAD -#define MP1_PMI_RELOAD__PMI_PARAMETERS_MASK 0x00000007L - -// MP1_PMI_INTERRUPT_CONTROL -#define MP1_PMI_INTERRUPT_CONTROL__PMI_PENDING_MASK 0x00000007L -#define MP1_PMI_INTERRUPT_CONTROL__PMI_INTERRUPT_MASK_MASK 0x00000038L - -// MP1_MMU_SRAM_ACC_VIOLATION_LOG_ADDR -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_ADDR__ADDRESS_MASK 0xffffffffL - -// MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_UNSECURE_BAR_MASK 0x00000002L -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_OP_MASK 0x00000008L -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE_MASK 0x00000030L -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_PERMISSION_MASK 0x000000c0L -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_UNIT_ID_MASK 0x00003f00L -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_INIT_ID_MASK 0x003fc000L -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR_MASK 0x00400000L - -// MP1_MMU_MISC_CNTL -#define MP1_MMU_MISC_CNTL__ALLOW_UNPRIVILIGED_REG_ACC_MASK 0x00000001L -#define MP1_MMU_MISC_CNTL__RETURN_ERR_ON_VIOLATED_READ_MASK 0x00000002L -#define MP1_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_PSRAM_MASK 0x00000004L -#define MP1_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_CPU_MASK 0x00000008L -#define MP1_MMU_MISC_CNTL__RESERVED2_MASK 0x000000f0L -#define MP1_MMU_MISC_CNTL__MEM_SLEEP_TIMEOUT_MASK 0x0000ff00L -#define MP1_MMU_MISC_CNTL__CLK_GATE_EN_MASK 0x00010000L -#define MP1_MMU_MISC_CNTL__CLK_GATE_OVERRIDE_MASK 0x00020000L -#define MP1_MMU_MISC_CNTL__CLK_GATE_TIMEOUT_MASK 0x003c0000L -#define MP1_MMU_MISC_CNTL__REGCLK_STATUS_MASK 0x00400000L -#define MP1_MMU_MISC_CNTL__SYSCLK_STATUS_MASK 0x00800000L -#define MP1_MMU_MISC_CNTL__MEM_DEEP_SLEEP_EN_MASK 0x01000000L -#define MP1_MMU_MISC_CNTL__MEM_DEEP_SLEEP_STATUS_MASK 0x02000000L -#define MP1_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_EN_MASK 0x04000000L -#define MP1_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_STATUS_MASK 0x08000000L -#define MP1_MMU_MISC_CNTL__MEM_PG_DLY_MASK 0xf0000000L - -// MP1_MMU_ACCESS_ERR_LOG -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_BLOCK_MASK 0x00000006L -#define MP1_MMU_ACCESS_ERR_LOG__ACC_VIOLATION_LOG_CLEAR_MASK 0x00000008L -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_UNIT_ID_MASK 0x00003f00L -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_INIT_ID_MASK 0x003fc000L -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_PROT_MASK 0x01c00000L - -// MP1_MMU_SRAM_UNSECURE_BAR -#define MP1_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR_MASK 0x0003ffffL -#define MP1_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR_LOCK_MASK 0x02000000L - -// MP1_MMU_SCRATCH_0 -#define MP1_MMU_SCRATCH_0__RESERVED_MASK 0xffffffffL - -// MP1_MMU_SCRATCH_1 -#define MP1_MMU_SCRATCH_1__RESERVED_MASK 0xffffffffL - -// MP1_MMU_SCRATCH_2 -#define MP1_MMU_SCRATCH_2__RESERVED_MASK 0xffffffffL - -// MP1_MMU_SCRATCH_3 -#define MP1_MMU_SCRATCH_3__RESERVED_MASK 0xffffffffL - -// MP1_MMU_SCRATCH_4 -#define MP1_MMU_SCRATCH_4__RESERVED_MASK 0xffffffffL - -// MP1_MMU_SCRATCH_5 -#define MP1_MMU_SCRATCH_5__RESERVED_MASK 0xffffffffL - -// MP1_MMU_SCRATCH_6 -#define MP1_MMU_SCRATCH_6__RESERVED_MASK 0xffffffffL - -// MP1_MMU_SCRATCH_7 -#define MP1_MMU_SCRATCH_7__RESERVED_MASK 0xffffffffL - -// MP1_MCA_ACCESS_CNTL -#define MP1_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_EN_MASK 0x00000001L -#define MP1_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_RD_WR_SEL_MASK 0x00000002L -#define MP1_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_REG_SEL_MASK 0x0000007cL - -// MP1_MCA_ACCESS_WR_DATA -#define MP1_MCA_ACCESS_WR_DATA__MCA_ACCESS_WR_DATA_MASK 0xffffffffL - -// MP1_MCA_ACCESS_RD_DATA -#define MP1_MCA_ACCESS_RD_DATA__MCA_ACCESS_RD_DATA_MASK 0xffffffffL - -// MP1_PMI_0 -#define MP1_PMI_0__DATA_MASK 0x0000ffffL -#define MP1_PMI_0__AxId_MASK 0xffff0000L - -// MP1_PMI_1 -#define MP1_PMI_1__DATA_MASK 0x0000ffffL -#define MP1_PMI_1__AxId_MASK 0xffff0000L - -// MP1_PMI_2 -#define MP1_PMI_2__DATA_MASK 0x0000ffffL -#define MP1_PMI_2__AxId_MASK 0xffff0000L - -// MP1_MMHUB_SOC_TLB0_1 -#define MP1_MMHUB_SOC_TLB0_1__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_2 -#define MP1_MMHUB_SOC_TLB0_2__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_3 -#define MP1_MMHUB_SOC_TLB0_3__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_4 -#define MP1_MMHUB_SOC_TLB0_4__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_5 -#define MP1_MMHUB_SOC_TLB0_5__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_6 -#define MP1_MMHUB_SOC_TLB0_6__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_7 -#define MP1_MMHUB_SOC_TLB0_7__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_8 -#define MP1_MMHUB_SOC_TLB0_8__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_9 -#define MP1_MMHUB_SOC_TLB0_9__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_10 -#define MP1_MMHUB_SOC_TLB0_10__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_11 -#define MP1_MMHUB_SOC_TLB0_11__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_12 -#define MP1_MMHUB_SOC_TLB0_12__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_13 -#define MP1_MMHUB_SOC_TLB0_13__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_14 -#define MP1_MMHUB_SOC_TLB0_14__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_15 -#define MP1_MMHUB_SOC_TLB0_15__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_16 -#define MP1_MMHUB_SOC_TLB0_16__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_17 -#define MP1_MMHUB_SOC_TLB0_17__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_18 -#define MP1_MMHUB_SOC_TLB0_18__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_19 -#define MP1_MMHUB_SOC_TLB0_19__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_20 -#define MP1_MMHUB_SOC_TLB0_20__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_21 -#define MP1_MMHUB_SOC_TLB0_21__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_22 -#define MP1_MMHUB_SOC_TLB0_22__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_23 -#define MP1_MMHUB_SOC_TLB0_23__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_24 -#define MP1_MMHUB_SOC_TLB0_24__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_25 -#define MP1_MMHUB_SOC_TLB0_25__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_26 -#define MP1_MMHUB_SOC_TLB0_26__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_27 -#define MP1_MMHUB_SOC_TLB0_27__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_28 -#define MP1_MMHUB_SOC_TLB0_28__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_29 -#define MP1_MMHUB_SOC_TLB0_29__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_30 -#define MP1_MMHUB_SOC_TLB0_30__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_31 -#define MP1_MMHUB_SOC_TLB0_31__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_32 -#define MP1_MMHUB_SOC_TLB0_32__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_33 -#define MP1_MMHUB_SOC_TLB0_33__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_34 -#define MP1_MMHUB_SOC_TLB0_34__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_35 -#define MP1_MMHUB_SOC_TLB0_35__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_36 -#define MP1_MMHUB_SOC_TLB0_36__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_37 -#define MP1_MMHUB_SOC_TLB0_37__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_38 -#define MP1_MMHUB_SOC_TLB0_38__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_39 -#define MP1_MMHUB_SOC_TLB0_39__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_40 -#define MP1_MMHUB_SOC_TLB0_40__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_41 -#define MP1_MMHUB_SOC_TLB0_41__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_42 -#define MP1_MMHUB_SOC_TLB0_42__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_43 -#define MP1_MMHUB_SOC_TLB0_43__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_44 -#define MP1_MMHUB_SOC_TLB0_44__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_45 -#define MP1_MMHUB_SOC_TLB0_45__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_46 -#define MP1_MMHUB_SOC_TLB0_46__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_47 -#define MP1_MMHUB_SOC_TLB0_47__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_48 -#define MP1_MMHUB_SOC_TLB0_48__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_49 -#define MP1_MMHUB_SOC_TLB0_49__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_50 -#define MP1_MMHUB_SOC_TLB0_50__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_51 -#define MP1_MMHUB_SOC_TLB0_51__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_52 -#define MP1_MMHUB_SOC_TLB0_52__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_53 -#define MP1_MMHUB_SOC_TLB0_53__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_54 -#define MP1_MMHUB_SOC_TLB0_54__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_55 -#define MP1_MMHUB_SOC_TLB0_55__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_56 -#define MP1_MMHUB_SOC_TLB0_56__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_57 -#define MP1_MMHUB_SOC_TLB0_57__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_58 -#define MP1_MMHUB_SOC_TLB0_58__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_59 -#define MP1_MMHUB_SOC_TLB0_59__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_60 -#define MP1_MMHUB_SOC_TLB0_60__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_61 -#define MP1_MMHUB_SOC_TLB0_61__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB0_62 -#define MP1_MMHUB_SOC_TLB0_62__SOC_ADDR_MASK 0x003fffffL - -// MP1_MMHUB_SOC_TLB1_1 -#define MP1_MMHUB_SOC_TLB1_1__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_1__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_1__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_2 -#define MP1_MMHUB_SOC_TLB1_2__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_2__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_2__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_3 -#define MP1_MMHUB_SOC_TLB1_3__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_3__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_3__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_4 -#define MP1_MMHUB_SOC_TLB1_4__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_4__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_4__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_5 -#define MP1_MMHUB_SOC_TLB1_5__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_5__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_5__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_6 -#define MP1_MMHUB_SOC_TLB1_6__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_6__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_6__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_7 -#define MP1_MMHUB_SOC_TLB1_7__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_7__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_7__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_8 -#define MP1_MMHUB_SOC_TLB1_8__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_8__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_8__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_9 -#define MP1_MMHUB_SOC_TLB1_9__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_9__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_9__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_10 -#define MP1_MMHUB_SOC_TLB1_10__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_10__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_10__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_11 -#define MP1_MMHUB_SOC_TLB1_11__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_11__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_11__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_12 -#define MP1_MMHUB_SOC_TLB1_12__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_12__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_12__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_13 -#define MP1_MMHUB_SOC_TLB1_13__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_13__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_13__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_14 -#define MP1_MMHUB_SOC_TLB1_14__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_14__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_14__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_15 -#define MP1_MMHUB_SOC_TLB1_15__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_15__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_15__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_16 -#define MP1_MMHUB_SOC_TLB1_16__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_16__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_16__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_17 -#define MP1_MMHUB_SOC_TLB1_17__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_17__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_17__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_18 -#define MP1_MMHUB_SOC_TLB1_18__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_18__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_18__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_19 -#define MP1_MMHUB_SOC_TLB1_19__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_19__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_19__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_20 -#define MP1_MMHUB_SOC_TLB1_20__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_20__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_20__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_21 -#define MP1_MMHUB_SOC_TLB1_21__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_21__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_21__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_22 -#define MP1_MMHUB_SOC_TLB1_22__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_22__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_22__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_23 -#define MP1_MMHUB_SOC_TLB1_23__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_23__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_23__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_24 -#define MP1_MMHUB_SOC_TLB1_24__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_24__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_24__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_25 -#define MP1_MMHUB_SOC_TLB1_25__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_25__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_25__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_26 -#define MP1_MMHUB_SOC_TLB1_26__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_26__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_26__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_27 -#define MP1_MMHUB_SOC_TLB1_27__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_27__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_27__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_28 -#define MP1_MMHUB_SOC_TLB1_28__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_28__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_28__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_29 -#define MP1_MMHUB_SOC_TLB1_29__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_29__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_29__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_30 -#define MP1_MMHUB_SOC_TLB1_30__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_30__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_30__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_31 -#define MP1_MMHUB_SOC_TLB1_31__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_31__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_31__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_32 -#define MP1_MMHUB_SOC_TLB1_32__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_32__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_32__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_33 -#define MP1_MMHUB_SOC_TLB1_33__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_33__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_33__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_34 -#define MP1_MMHUB_SOC_TLB1_34__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_34__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_34__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_35 -#define MP1_MMHUB_SOC_TLB1_35__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_35__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_35__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_36 -#define MP1_MMHUB_SOC_TLB1_36__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_36__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_36__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_37 -#define MP1_MMHUB_SOC_TLB1_37__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_37__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_37__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_38 -#define MP1_MMHUB_SOC_TLB1_38__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_38__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_38__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_39 -#define MP1_MMHUB_SOC_TLB1_39__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_39__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_39__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_40 -#define MP1_MMHUB_SOC_TLB1_40__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_40__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_40__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_41 -#define MP1_MMHUB_SOC_TLB1_41__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_41__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_41__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_42 -#define MP1_MMHUB_SOC_TLB1_42__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_42__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_42__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_43 -#define MP1_MMHUB_SOC_TLB1_43__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_43__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_43__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_44 -#define MP1_MMHUB_SOC_TLB1_44__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_44__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_44__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_45 -#define MP1_MMHUB_SOC_TLB1_45__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_45__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_45__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_46 -#define MP1_MMHUB_SOC_TLB1_46__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_46__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_46__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_47 -#define MP1_MMHUB_SOC_TLB1_47__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_47__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_47__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_48 -#define MP1_MMHUB_SOC_TLB1_48__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_48__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_48__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_49 -#define MP1_MMHUB_SOC_TLB1_49__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_49__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_49__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_50 -#define MP1_MMHUB_SOC_TLB1_50__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_50__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_50__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_51 -#define MP1_MMHUB_SOC_TLB1_51__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_51__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_51__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_52 -#define MP1_MMHUB_SOC_TLB1_52__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_52__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_52__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_53 -#define MP1_MMHUB_SOC_TLB1_53__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_53__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_53__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_54 -#define MP1_MMHUB_SOC_TLB1_54__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_54__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_54__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_55 -#define MP1_MMHUB_SOC_TLB1_55__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_55__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_55__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_56 -#define MP1_MMHUB_SOC_TLB1_56__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_56__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_56__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_57 -#define MP1_MMHUB_SOC_TLB1_57__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_57__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_57__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_58 -#define MP1_MMHUB_SOC_TLB1_58__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_58__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_58__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_59 -#define MP1_MMHUB_SOC_TLB1_59__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_59__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_59__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_60 -#define MP1_MMHUB_SOC_TLB1_60__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_60__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_60__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_61 -#define MP1_MMHUB_SOC_TLB1_61__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_61__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_61__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB1_62 -#define MP1_MMHUB_SOC_TLB1_62__COHERENCE_MASK 0x00000001L -#define MP1_MMHUB_SOC_TLB1_62__SEG_SIZE_MASK 0x0000001eL -#define MP1_MMHUB_SOC_TLB1_62__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_MMHUB_SOC_TLB2_1 -#define MP1_MMHUB_SOC_TLB2_1__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_2 -#define MP1_MMHUB_SOC_TLB2_2__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_3 -#define MP1_MMHUB_SOC_TLB2_3__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_4 -#define MP1_MMHUB_SOC_TLB2_4__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_5 -#define MP1_MMHUB_SOC_TLB2_5__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_6 -#define MP1_MMHUB_SOC_TLB2_6__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_7 -#define MP1_MMHUB_SOC_TLB2_7__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_8 -#define MP1_MMHUB_SOC_TLB2_8__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_9 -#define MP1_MMHUB_SOC_TLB2_9__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_10 -#define MP1_MMHUB_SOC_TLB2_10__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_11 -#define MP1_MMHUB_SOC_TLB2_11__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_12 -#define MP1_MMHUB_SOC_TLB2_12__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_13 -#define MP1_MMHUB_SOC_TLB2_13__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_14 -#define MP1_MMHUB_SOC_TLB2_14__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_15 -#define MP1_MMHUB_SOC_TLB2_15__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_16 -#define MP1_MMHUB_SOC_TLB2_16__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_17 -#define MP1_MMHUB_SOC_TLB2_17__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_18 -#define MP1_MMHUB_SOC_TLB2_18__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_19 -#define MP1_MMHUB_SOC_TLB2_19__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_20 -#define MP1_MMHUB_SOC_TLB2_20__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_21 -#define MP1_MMHUB_SOC_TLB2_21__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_22 -#define MP1_MMHUB_SOC_TLB2_22__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_23 -#define MP1_MMHUB_SOC_TLB2_23__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_24 -#define MP1_MMHUB_SOC_TLB2_24__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_25 -#define MP1_MMHUB_SOC_TLB2_25__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_26 -#define MP1_MMHUB_SOC_TLB2_26__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_27 -#define MP1_MMHUB_SOC_TLB2_27__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_28 -#define MP1_MMHUB_SOC_TLB2_28__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_29 -#define MP1_MMHUB_SOC_TLB2_29__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_30 -#define MP1_MMHUB_SOC_TLB2_30__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_31 -#define MP1_MMHUB_SOC_TLB2_31__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_32 -#define MP1_MMHUB_SOC_TLB2_32__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_33 -#define MP1_MMHUB_SOC_TLB2_33__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_34 -#define MP1_MMHUB_SOC_TLB2_34__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_35 -#define MP1_MMHUB_SOC_TLB2_35__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_36 -#define MP1_MMHUB_SOC_TLB2_36__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_37 -#define MP1_MMHUB_SOC_TLB2_37__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_38 -#define MP1_MMHUB_SOC_TLB2_38__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_39 -#define MP1_MMHUB_SOC_TLB2_39__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_40 -#define MP1_MMHUB_SOC_TLB2_40__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_41 -#define MP1_MMHUB_SOC_TLB2_41__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_42 -#define MP1_MMHUB_SOC_TLB2_42__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_43 -#define MP1_MMHUB_SOC_TLB2_43__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_44 -#define MP1_MMHUB_SOC_TLB2_44__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_45 -#define MP1_MMHUB_SOC_TLB2_45__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_46 -#define MP1_MMHUB_SOC_TLB2_46__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_47 -#define MP1_MMHUB_SOC_TLB2_47__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_48 -#define MP1_MMHUB_SOC_TLB2_48__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_49 -#define MP1_MMHUB_SOC_TLB2_49__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_50 -#define MP1_MMHUB_SOC_TLB2_50__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_51 -#define MP1_MMHUB_SOC_TLB2_51__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_52 -#define MP1_MMHUB_SOC_TLB2_52__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_53 -#define MP1_MMHUB_SOC_TLB2_53__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_54 -#define MP1_MMHUB_SOC_TLB2_54__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_55 -#define MP1_MMHUB_SOC_TLB2_55__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_56 -#define MP1_MMHUB_SOC_TLB2_56__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_57 -#define MP1_MMHUB_SOC_TLB2_57__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_58 -#define MP1_MMHUB_SOC_TLB2_58__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_59 -#define MP1_MMHUB_SOC_TLB2_59__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_60 -#define MP1_MMHUB_SOC_TLB2_60__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_61 -#define MP1_MMHUB_SOC_TLB2_61__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB2_62 -#define MP1_MMHUB_SOC_TLB2_62__AWUSER_MASK 0xffffffffL - -// MP1_MMHUB_SOC_TLB3_1 -#define MP1_MMHUB_SOC_TLB3_1__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_1__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_2 -#define MP1_MMHUB_SOC_TLB3_2__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_2__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_3 -#define MP1_MMHUB_SOC_TLB3_3__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_3__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_4 -#define MP1_MMHUB_SOC_TLB3_4__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_4__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_5 -#define MP1_MMHUB_SOC_TLB3_5__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_5__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_6 -#define MP1_MMHUB_SOC_TLB3_6__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_6__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_7 -#define MP1_MMHUB_SOC_TLB3_7__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_7__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_8 -#define MP1_MMHUB_SOC_TLB3_8__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_8__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_9 -#define MP1_MMHUB_SOC_TLB3_9__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_9__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_10 -#define MP1_MMHUB_SOC_TLB3_10__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_10__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_11 -#define MP1_MMHUB_SOC_TLB3_11__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_11__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_12 -#define MP1_MMHUB_SOC_TLB3_12__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_12__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_13 -#define MP1_MMHUB_SOC_TLB3_13__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_13__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_14 -#define MP1_MMHUB_SOC_TLB3_14__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_14__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_15 -#define MP1_MMHUB_SOC_TLB3_15__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_15__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_16 -#define MP1_MMHUB_SOC_TLB3_16__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_16__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_17 -#define MP1_MMHUB_SOC_TLB3_17__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_17__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_18 -#define MP1_MMHUB_SOC_TLB3_18__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_18__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_19 -#define MP1_MMHUB_SOC_TLB3_19__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_19__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_20 -#define MP1_MMHUB_SOC_TLB3_20__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_20__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_21 -#define MP1_MMHUB_SOC_TLB3_21__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_21__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_22 -#define MP1_MMHUB_SOC_TLB3_22__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_22__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_23 -#define MP1_MMHUB_SOC_TLB3_23__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_23__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_24 -#define MP1_MMHUB_SOC_TLB3_24__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_24__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_25 -#define MP1_MMHUB_SOC_TLB3_25__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_25__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_26 -#define MP1_MMHUB_SOC_TLB3_26__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_26__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_27 -#define MP1_MMHUB_SOC_TLB3_27__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_27__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_28 -#define MP1_MMHUB_SOC_TLB3_28__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_28__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_29 -#define MP1_MMHUB_SOC_TLB3_29__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_29__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_30 -#define MP1_MMHUB_SOC_TLB3_30__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_30__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_31 -#define MP1_MMHUB_SOC_TLB3_31__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_31__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_32 -#define MP1_MMHUB_SOC_TLB3_32__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_32__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_33 -#define MP1_MMHUB_SOC_TLB3_33__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_33__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_34 -#define MP1_MMHUB_SOC_TLB3_34__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_34__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_35 -#define MP1_MMHUB_SOC_TLB3_35__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_35__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_36 -#define MP1_MMHUB_SOC_TLB3_36__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_36__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_37 -#define MP1_MMHUB_SOC_TLB3_37__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_37__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_38 -#define MP1_MMHUB_SOC_TLB3_38__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_38__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_39 -#define MP1_MMHUB_SOC_TLB3_39__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_39__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_40 -#define MP1_MMHUB_SOC_TLB3_40__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_40__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_41 -#define MP1_MMHUB_SOC_TLB3_41__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_41__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_42 -#define MP1_MMHUB_SOC_TLB3_42__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_42__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_43 -#define MP1_MMHUB_SOC_TLB3_43__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_43__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_44 -#define MP1_MMHUB_SOC_TLB3_44__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_44__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_45 -#define MP1_MMHUB_SOC_TLB3_45__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_45__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_46 -#define MP1_MMHUB_SOC_TLB3_46__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_46__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_47 -#define MP1_MMHUB_SOC_TLB3_47__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_47__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_48 -#define MP1_MMHUB_SOC_TLB3_48__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_48__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_49 -#define MP1_MMHUB_SOC_TLB3_49__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_49__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_50 -#define MP1_MMHUB_SOC_TLB3_50__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_50__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_51 -#define MP1_MMHUB_SOC_TLB3_51__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_51__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_52 -#define MP1_MMHUB_SOC_TLB3_52__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_52__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_53 -#define MP1_MMHUB_SOC_TLB3_53__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_53__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_54 -#define MP1_MMHUB_SOC_TLB3_54__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_54__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_55 -#define MP1_MMHUB_SOC_TLB3_55__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_55__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_56 -#define MP1_MMHUB_SOC_TLB3_56__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_56__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_57 -#define MP1_MMHUB_SOC_TLB3_57__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_57__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_58 -#define MP1_MMHUB_SOC_TLB3_58__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_58__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_59 -#define MP1_MMHUB_SOC_TLB3_59__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_59__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_60 -#define MP1_MMHUB_SOC_TLB3_60__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_60__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_61 -#define MP1_MMHUB_SOC_TLB3_61__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_61__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_SOC_TLB3_62 -#define MP1_MMHUB_SOC_TLB3_62__ARUSER_MASK 0x03ffffffL -#define MP1_MMHUB_SOC_TLB3_62__WUSER_MASK 0x3c000000L - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB_MASK 0xffffffffL - -// MP1_MMHUB_TLB_ATTRIBUTE_1 -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_2 -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_3 -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_4 -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_5 -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_6 -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_7 -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_8 -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_9 -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_10 -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_11 -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_12 -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_13 -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_14 -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_15 -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_16 -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_17 -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_18 -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_19 -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_20 -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_21 -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_22 -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_23 -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_24 -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_25 -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_26 -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_27 -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_28 -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_29 -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_30 -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_31 -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_32 -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_33 -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_34 -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_35 -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_36 -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_37 -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_38 -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_39 -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_40 -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_41 -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_42 -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_43 -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_44 -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_45 -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_46 -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_47 -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_48 -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_49 -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_50 -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_51 -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_52 -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_53 -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_54 -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_55 -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_56 -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_57 -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_58 -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_59 -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_60 -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_61 -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_TLB_ATTRIBUTE_62 -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_DMA_MASK 0x00800000L -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB_MASK 0x40000000L -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_MMHUB_INT_STATUS -#define MP1_MMHUB_INT_STATUS__RD_ERROR_MASK 0x00000001L -#define MP1_MMHUB_INT_STATUS__WR_ERROR_MASK 0x00000002L -#define MP1_MMHUB_INT_STATUS__REG_ERROR_MASK 0x00000004L - -// MP1_MMHUB_WR_INT_ADDR -#define MP1_MMHUB_WR_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP1_MMHUB_WR_INT_OTHER -#define MP1_MMHUB_WR_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP1_MMHUB_WR_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP1_MMHUB_WR_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP1_MMHUB_WR_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP1_MMHUB_WR_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP1_MMHUB_WR_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP1_MMHUB_WR_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP1_MMHUB_WR_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP1_MMHUB_RD_INT_ADDR -#define MP1_MMHUB_RD_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP1_MMHUB_RD_INT_OTHER -#define MP1_MMHUB_RD_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP1_MMHUB_RD_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP1_MMHUB_RD_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP1_MMHUB_RD_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP1_MMHUB_RD_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP1_MMHUB_RD_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP1_MMHUB_RD_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP1_MMHUB_RD_INT_OTHER__ERROR_LENGTH_MASK 0x04000000L -#define MP1_MMHUB_RD_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP1_MMHUB_REG_INT_ADDR -#define MP1_MMHUB_REG_INT_ADDR__ADDR_MASK 0x0000ffffL - -// MP1_MMHUB_REG_INT_OTHER -#define MP1_MMHUB_REG_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP1_MMHUB_REG_INT_OTHER__ERROR_AES_MASK 0x00100000L -#define MP1_MMHUB_REG_INT_OTHER__ERROR_MST_MASK 0x00200000L -#define MP1_MMHUB_REG_INT_OTHER__ERROR_ADDR_MASK 0x00400000L -#define MP1_MMHUB_REG_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP1_MMHUB_REG_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP1_MMHUB_AXCACHE_CFG -#define MP1_MMHUB_AXCACHE_CFG__ARCACHE_NONCOH_MASK 0x0000000fL -#define MP1_MMHUB_AXCACHE_CFG__ARCACHE_COH_MASK 0x000000f0L -#define MP1_MMHUB_AXCACHE_CFG__AWCACHE_NONCOH_MASK 0x00000f00L -#define MP1_MMHUB_AXCACHE_CFG__AWCACHE_COH_MASK 0x0000f000L -#define MP1_MMHUB_AXCACHE_CFG__QOSW_MASK 0x000f0000L -#define MP1_MMHUB_AXCACHE_CFG__QOSR_MASK 0x00f00000L - -// MP1_MMHUB_DS_OVERRIDE -#define MP1_MMHUB_DS_OVERRIDE__DS_CNT_MASK 0x000007ffL -#define MP1_MMHUB_DS_OVERRIDE__DS_DISABLE_MASK 0x00000800L - -// MP1_MMHUB_OUTSTANDING -#define MP1_MMHUB_OUTSTANDING__PENDING_WR_MASK 0x0000ffffL -#define MP1_MMHUB_OUTSTANDING__PENDING_RD_MASK 0x00ff0000L - -// MP1_SYSHUB_SOC_TLB0_1 -#define MP1_SYSHUB_SOC_TLB0_1__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_2 -#define MP1_SYSHUB_SOC_TLB0_2__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_3 -#define MP1_SYSHUB_SOC_TLB0_3__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_4 -#define MP1_SYSHUB_SOC_TLB0_4__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_5 -#define MP1_SYSHUB_SOC_TLB0_5__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_6 -#define MP1_SYSHUB_SOC_TLB0_6__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_7 -#define MP1_SYSHUB_SOC_TLB0_7__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_8 -#define MP1_SYSHUB_SOC_TLB0_8__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_9 -#define MP1_SYSHUB_SOC_TLB0_9__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_10 -#define MP1_SYSHUB_SOC_TLB0_10__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_11 -#define MP1_SYSHUB_SOC_TLB0_11__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_12 -#define MP1_SYSHUB_SOC_TLB0_12__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_13 -#define MP1_SYSHUB_SOC_TLB0_13__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_14 -#define MP1_SYSHUB_SOC_TLB0_14__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_15 -#define MP1_SYSHUB_SOC_TLB0_15__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_16 -#define MP1_SYSHUB_SOC_TLB0_16__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_17 -#define MP1_SYSHUB_SOC_TLB0_17__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_18 -#define MP1_SYSHUB_SOC_TLB0_18__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_19 -#define MP1_SYSHUB_SOC_TLB0_19__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_20 -#define MP1_SYSHUB_SOC_TLB0_20__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_21 -#define MP1_SYSHUB_SOC_TLB0_21__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_22 -#define MP1_SYSHUB_SOC_TLB0_22__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_23 -#define MP1_SYSHUB_SOC_TLB0_23__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_24 -#define MP1_SYSHUB_SOC_TLB0_24__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_25 -#define MP1_SYSHUB_SOC_TLB0_25__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_26 -#define MP1_SYSHUB_SOC_TLB0_26__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_27 -#define MP1_SYSHUB_SOC_TLB0_27__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_28 -#define MP1_SYSHUB_SOC_TLB0_28__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_29 -#define MP1_SYSHUB_SOC_TLB0_29__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_30 -#define MP1_SYSHUB_SOC_TLB0_30__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_31 -#define MP1_SYSHUB_SOC_TLB0_31__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_32 -#define MP1_SYSHUB_SOC_TLB0_32__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_33 -#define MP1_SYSHUB_SOC_TLB0_33__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_34 -#define MP1_SYSHUB_SOC_TLB0_34__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_35 -#define MP1_SYSHUB_SOC_TLB0_35__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_36 -#define MP1_SYSHUB_SOC_TLB0_36__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_37 -#define MP1_SYSHUB_SOC_TLB0_37__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_38 -#define MP1_SYSHUB_SOC_TLB0_38__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_39 -#define MP1_SYSHUB_SOC_TLB0_39__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_40 -#define MP1_SYSHUB_SOC_TLB0_40__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_41 -#define MP1_SYSHUB_SOC_TLB0_41__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_42 -#define MP1_SYSHUB_SOC_TLB0_42__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_43 -#define MP1_SYSHUB_SOC_TLB0_43__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_44 -#define MP1_SYSHUB_SOC_TLB0_44__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_45 -#define MP1_SYSHUB_SOC_TLB0_45__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_46 -#define MP1_SYSHUB_SOC_TLB0_46__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_47 -#define MP1_SYSHUB_SOC_TLB0_47__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_48 -#define MP1_SYSHUB_SOC_TLB0_48__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_49 -#define MP1_SYSHUB_SOC_TLB0_49__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_50 -#define MP1_SYSHUB_SOC_TLB0_50__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_51 -#define MP1_SYSHUB_SOC_TLB0_51__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_52 -#define MP1_SYSHUB_SOC_TLB0_52__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_53 -#define MP1_SYSHUB_SOC_TLB0_53__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_54 -#define MP1_SYSHUB_SOC_TLB0_54__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_55 -#define MP1_SYSHUB_SOC_TLB0_55__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_56 -#define MP1_SYSHUB_SOC_TLB0_56__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_57 -#define MP1_SYSHUB_SOC_TLB0_57__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_58 -#define MP1_SYSHUB_SOC_TLB0_58__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_59 -#define MP1_SYSHUB_SOC_TLB0_59__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_60 -#define MP1_SYSHUB_SOC_TLB0_60__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_61 -#define MP1_SYSHUB_SOC_TLB0_61__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB0_62 -#define MP1_SYSHUB_SOC_TLB0_62__SOC_ADDR_MASK 0x003fffffL - -// MP1_SYSHUB_SOC_TLB1_1 -#define MP1_SYSHUB_SOC_TLB1_1__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_1__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_1__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_2 -#define MP1_SYSHUB_SOC_TLB1_2__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_2__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_2__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_3 -#define MP1_SYSHUB_SOC_TLB1_3__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_3__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_3__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_4 -#define MP1_SYSHUB_SOC_TLB1_4__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_4__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_4__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_5 -#define MP1_SYSHUB_SOC_TLB1_5__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_5__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_5__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_6 -#define MP1_SYSHUB_SOC_TLB1_6__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_6__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_6__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_7 -#define MP1_SYSHUB_SOC_TLB1_7__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_7__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_7__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_8 -#define MP1_SYSHUB_SOC_TLB1_8__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_8__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_8__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_9 -#define MP1_SYSHUB_SOC_TLB1_9__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_9__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_9__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_10 -#define MP1_SYSHUB_SOC_TLB1_10__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_10__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_10__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_11 -#define MP1_SYSHUB_SOC_TLB1_11__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_11__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_11__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_12 -#define MP1_SYSHUB_SOC_TLB1_12__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_12__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_12__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_13 -#define MP1_SYSHUB_SOC_TLB1_13__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_13__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_13__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_14 -#define MP1_SYSHUB_SOC_TLB1_14__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_14__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_14__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_15 -#define MP1_SYSHUB_SOC_TLB1_15__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_15__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_15__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_16 -#define MP1_SYSHUB_SOC_TLB1_16__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_16__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_16__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_17 -#define MP1_SYSHUB_SOC_TLB1_17__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_17__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_17__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_18 -#define MP1_SYSHUB_SOC_TLB1_18__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_18__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_18__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_19 -#define MP1_SYSHUB_SOC_TLB1_19__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_19__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_19__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_20 -#define MP1_SYSHUB_SOC_TLB1_20__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_20__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_20__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_21 -#define MP1_SYSHUB_SOC_TLB1_21__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_21__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_21__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_22 -#define MP1_SYSHUB_SOC_TLB1_22__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_22__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_22__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_23 -#define MP1_SYSHUB_SOC_TLB1_23__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_23__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_23__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_24 -#define MP1_SYSHUB_SOC_TLB1_24__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_24__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_24__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_25 -#define MP1_SYSHUB_SOC_TLB1_25__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_25__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_25__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_26 -#define MP1_SYSHUB_SOC_TLB1_26__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_26__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_26__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_27 -#define MP1_SYSHUB_SOC_TLB1_27__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_27__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_27__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_28 -#define MP1_SYSHUB_SOC_TLB1_28__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_28__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_28__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_29 -#define MP1_SYSHUB_SOC_TLB1_29__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_29__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_29__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_30 -#define MP1_SYSHUB_SOC_TLB1_30__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_30__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_30__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_31 -#define MP1_SYSHUB_SOC_TLB1_31__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_31__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_31__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_32 -#define MP1_SYSHUB_SOC_TLB1_32__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_32__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_32__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_33 -#define MP1_SYSHUB_SOC_TLB1_33__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_33__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_33__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_34 -#define MP1_SYSHUB_SOC_TLB1_34__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_34__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_34__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_35 -#define MP1_SYSHUB_SOC_TLB1_35__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_35__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_35__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_36 -#define MP1_SYSHUB_SOC_TLB1_36__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_36__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_36__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_37 -#define MP1_SYSHUB_SOC_TLB1_37__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_37__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_37__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_38 -#define MP1_SYSHUB_SOC_TLB1_38__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_38__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_38__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_39 -#define MP1_SYSHUB_SOC_TLB1_39__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_39__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_39__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_40 -#define MP1_SYSHUB_SOC_TLB1_40__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_40__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_40__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_41 -#define MP1_SYSHUB_SOC_TLB1_41__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_41__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_41__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_42 -#define MP1_SYSHUB_SOC_TLB1_42__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_42__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_42__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_43 -#define MP1_SYSHUB_SOC_TLB1_43__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_43__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_43__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_44 -#define MP1_SYSHUB_SOC_TLB1_44__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_44__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_44__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_45 -#define MP1_SYSHUB_SOC_TLB1_45__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_45__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_45__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_46 -#define MP1_SYSHUB_SOC_TLB1_46__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_46__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_46__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_47 -#define MP1_SYSHUB_SOC_TLB1_47__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_47__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_47__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_48 -#define MP1_SYSHUB_SOC_TLB1_48__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_48__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_48__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_49 -#define MP1_SYSHUB_SOC_TLB1_49__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_49__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_49__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_50 -#define MP1_SYSHUB_SOC_TLB1_50__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_50__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_50__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_51 -#define MP1_SYSHUB_SOC_TLB1_51__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_51__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_51__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_52 -#define MP1_SYSHUB_SOC_TLB1_52__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_52__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_52__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_53 -#define MP1_SYSHUB_SOC_TLB1_53__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_53__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_53__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_54 -#define MP1_SYSHUB_SOC_TLB1_54__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_54__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_54__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_55 -#define MP1_SYSHUB_SOC_TLB1_55__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_55__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_55__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_56 -#define MP1_SYSHUB_SOC_TLB1_56__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_56__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_56__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_57 -#define MP1_SYSHUB_SOC_TLB1_57__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_57__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_57__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_58 -#define MP1_SYSHUB_SOC_TLB1_58__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_58__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_58__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_59 -#define MP1_SYSHUB_SOC_TLB1_59__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_59__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_59__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_60 -#define MP1_SYSHUB_SOC_TLB1_60__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_60__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_60__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_61 -#define MP1_SYSHUB_SOC_TLB1_61__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_61__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_61__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB1_62 -#define MP1_SYSHUB_SOC_TLB1_62__COHERENCE_MASK 0x00000001L -#define MP1_SYSHUB_SOC_TLB1_62__SEG_SIZE_MASK 0x0000001eL -#define MP1_SYSHUB_SOC_TLB1_62__SEG_OFFSET_MASK 0x00003fe0L - -// MP1_SYSHUB_SOC_TLB2_1 -#define MP1_SYSHUB_SOC_TLB2_1__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_2 -#define MP1_SYSHUB_SOC_TLB2_2__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_3 -#define MP1_SYSHUB_SOC_TLB2_3__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_4 -#define MP1_SYSHUB_SOC_TLB2_4__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_5 -#define MP1_SYSHUB_SOC_TLB2_5__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_6 -#define MP1_SYSHUB_SOC_TLB2_6__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_7 -#define MP1_SYSHUB_SOC_TLB2_7__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_8 -#define MP1_SYSHUB_SOC_TLB2_8__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_9 -#define MP1_SYSHUB_SOC_TLB2_9__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_10 -#define MP1_SYSHUB_SOC_TLB2_10__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_11 -#define MP1_SYSHUB_SOC_TLB2_11__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_12 -#define MP1_SYSHUB_SOC_TLB2_12__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_13 -#define MP1_SYSHUB_SOC_TLB2_13__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_14 -#define MP1_SYSHUB_SOC_TLB2_14__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_15 -#define MP1_SYSHUB_SOC_TLB2_15__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_16 -#define MP1_SYSHUB_SOC_TLB2_16__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_17 -#define MP1_SYSHUB_SOC_TLB2_17__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_18 -#define MP1_SYSHUB_SOC_TLB2_18__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_19 -#define MP1_SYSHUB_SOC_TLB2_19__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_20 -#define MP1_SYSHUB_SOC_TLB2_20__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_21 -#define MP1_SYSHUB_SOC_TLB2_21__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_22 -#define MP1_SYSHUB_SOC_TLB2_22__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_23 -#define MP1_SYSHUB_SOC_TLB2_23__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_24 -#define MP1_SYSHUB_SOC_TLB2_24__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_25 -#define MP1_SYSHUB_SOC_TLB2_25__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_26 -#define MP1_SYSHUB_SOC_TLB2_26__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_27 -#define MP1_SYSHUB_SOC_TLB2_27__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_28 -#define MP1_SYSHUB_SOC_TLB2_28__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_29 -#define MP1_SYSHUB_SOC_TLB2_29__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_30 -#define MP1_SYSHUB_SOC_TLB2_30__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_31 -#define MP1_SYSHUB_SOC_TLB2_31__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_32 -#define MP1_SYSHUB_SOC_TLB2_32__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_33 -#define MP1_SYSHUB_SOC_TLB2_33__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_34 -#define MP1_SYSHUB_SOC_TLB2_34__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_35 -#define MP1_SYSHUB_SOC_TLB2_35__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_36 -#define MP1_SYSHUB_SOC_TLB2_36__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_37 -#define MP1_SYSHUB_SOC_TLB2_37__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_38 -#define MP1_SYSHUB_SOC_TLB2_38__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_39 -#define MP1_SYSHUB_SOC_TLB2_39__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_40 -#define MP1_SYSHUB_SOC_TLB2_40__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_41 -#define MP1_SYSHUB_SOC_TLB2_41__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_42 -#define MP1_SYSHUB_SOC_TLB2_42__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_43 -#define MP1_SYSHUB_SOC_TLB2_43__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_44 -#define MP1_SYSHUB_SOC_TLB2_44__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_45 -#define MP1_SYSHUB_SOC_TLB2_45__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_46 -#define MP1_SYSHUB_SOC_TLB2_46__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_47 -#define MP1_SYSHUB_SOC_TLB2_47__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_48 -#define MP1_SYSHUB_SOC_TLB2_48__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_49 -#define MP1_SYSHUB_SOC_TLB2_49__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_50 -#define MP1_SYSHUB_SOC_TLB2_50__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_51 -#define MP1_SYSHUB_SOC_TLB2_51__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_52 -#define MP1_SYSHUB_SOC_TLB2_52__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_53 -#define MP1_SYSHUB_SOC_TLB2_53__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_54 -#define MP1_SYSHUB_SOC_TLB2_54__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_55 -#define MP1_SYSHUB_SOC_TLB2_55__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_56 -#define MP1_SYSHUB_SOC_TLB2_56__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_57 -#define MP1_SYSHUB_SOC_TLB2_57__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_58 -#define MP1_SYSHUB_SOC_TLB2_58__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_59 -#define MP1_SYSHUB_SOC_TLB2_59__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_60 -#define MP1_SYSHUB_SOC_TLB2_60__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_61 -#define MP1_SYSHUB_SOC_TLB2_61__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB2_62 -#define MP1_SYSHUB_SOC_TLB2_62__AWUSER_MASK 0xffffffffL - -// MP1_SYSHUB_SOC_TLB3_1 -#define MP1_SYSHUB_SOC_TLB3_1__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_1__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_2 -#define MP1_SYSHUB_SOC_TLB3_2__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_2__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_3 -#define MP1_SYSHUB_SOC_TLB3_3__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_3__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_4 -#define MP1_SYSHUB_SOC_TLB3_4__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_4__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_5 -#define MP1_SYSHUB_SOC_TLB3_5__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_5__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_6 -#define MP1_SYSHUB_SOC_TLB3_6__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_6__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_7 -#define MP1_SYSHUB_SOC_TLB3_7__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_7__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_8 -#define MP1_SYSHUB_SOC_TLB3_8__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_8__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_9 -#define MP1_SYSHUB_SOC_TLB3_9__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_9__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_10 -#define MP1_SYSHUB_SOC_TLB3_10__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_10__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_11 -#define MP1_SYSHUB_SOC_TLB3_11__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_11__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_12 -#define MP1_SYSHUB_SOC_TLB3_12__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_12__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_13 -#define MP1_SYSHUB_SOC_TLB3_13__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_13__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_14 -#define MP1_SYSHUB_SOC_TLB3_14__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_14__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_15 -#define MP1_SYSHUB_SOC_TLB3_15__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_15__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_16 -#define MP1_SYSHUB_SOC_TLB3_16__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_16__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_17 -#define MP1_SYSHUB_SOC_TLB3_17__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_17__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_18 -#define MP1_SYSHUB_SOC_TLB3_18__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_18__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_19 -#define MP1_SYSHUB_SOC_TLB3_19__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_19__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_20 -#define MP1_SYSHUB_SOC_TLB3_20__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_20__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_21 -#define MP1_SYSHUB_SOC_TLB3_21__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_21__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_22 -#define MP1_SYSHUB_SOC_TLB3_22__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_22__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_23 -#define MP1_SYSHUB_SOC_TLB3_23__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_23__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_24 -#define MP1_SYSHUB_SOC_TLB3_24__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_24__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_25 -#define MP1_SYSHUB_SOC_TLB3_25__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_25__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_26 -#define MP1_SYSHUB_SOC_TLB3_26__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_26__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_27 -#define MP1_SYSHUB_SOC_TLB3_27__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_27__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_28 -#define MP1_SYSHUB_SOC_TLB3_28__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_28__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_29 -#define MP1_SYSHUB_SOC_TLB3_29__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_29__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_30 -#define MP1_SYSHUB_SOC_TLB3_30__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_30__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_31 -#define MP1_SYSHUB_SOC_TLB3_31__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_31__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_32 -#define MP1_SYSHUB_SOC_TLB3_32__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_32__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_33 -#define MP1_SYSHUB_SOC_TLB3_33__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_33__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_34 -#define MP1_SYSHUB_SOC_TLB3_34__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_34__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_35 -#define MP1_SYSHUB_SOC_TLB3_35__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_35__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_36 -#define MP1_SYSHUB_SOC_TLB3_36__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_36__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_37 -#define MP1_SYSHUB_SOC_TLB3_37__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_37__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_38 -#define MP1_SYSHUB_SOC_TLB3_38__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_38__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_39 -#define MP1_SYSHUB_SOC_TLB3_39__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_39__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_40 -#define MP1_SYSHUB_SOC_TLB3_40__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_40__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_41 -#define MP1_SYSHUB_SOC_TLB3_41__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_41__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_42 -#define MP1_SYSHUB_SOC_TLB3_42__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_42__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_43 -#define MP1_SYSHUB_SOC_TLB3_43__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_43__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_44 -#define MP1_SYSHUB_SOC_TLB3_44__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_44__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_45 -#define MP1_SYSHUB_SOC_TLB3_45__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_45__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_46 -#define MP1_SYSHUB_SOC_TLB3_46__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_46__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_47 -#define MP1_SYSHUB_SOC_TLB3_47__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_47__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_48 -#define MP1_SYSHUB_SOC_TLB3_48__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_48__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_49 -#define MP1_SYSHUB_SOC_TLB3_49__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_49__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_50 -#define MP1_SYSHUB_SOC_TLB3_50__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_50__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_51 -#define MP1_SYSHUB_SOC_TLB3_51__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_51__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_52 -#define MP1_SYSHUB_SOC_TLB3_52__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_52__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_53 -#define MP1_SYSHUB_SOC_TLB3_53__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_53__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_54 -#define MP1_SYSHUB_SOC_TLB3_54__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_54__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_55 -#define MP1_SYSHUB_SOC_TLB3_55__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_55__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_56 -#define MP1_SYSHUB_SOC_TLB3_56__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_56__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_57 -#define MP1_SYSHUB_SOC_TLB3_57__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_57__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_58 -#define MP1_SYSHUB_SOC_TLB3_58__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_58__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_59 -#define MP1_SYSHUB_SOC_TLB3_59__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_59__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_60 -#define MP1_SYSHUB_SOC_TLB3_60__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_60__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_61 -#define MP1_SYSHUB_SOC_TLB3_61__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_61__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_SOC_TLB3_62 -#define MP1_SYSHUB_SOC_TLB3_62__ARUSER_MASK 0x03ffffffL -#define MP1_SYSHUB_SOC_TLB3_62__WUSER_MASK 0x3c000000L - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB_MASK 0xffffffffL - -// MP1_SYSHUB_TLB_ATTRIBUTE_1 -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_2 -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_3 -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_4 -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_5 -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_6 -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_7 -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_8 -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_9 -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_10 -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_11 -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_12 -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_13 -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_14 -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_15 -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_16 -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_17 -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_18 -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_19 -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_20 -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_21 -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_22 -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_23 -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_24 -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_25 -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_26 -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_27 -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_28 -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_29 -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_30 -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_31 -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_32 -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_33 -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_34 -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_35 -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_36 -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_37 -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_38 -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_39 -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_40 -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_41 -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_42 -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_43 -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_44 -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_45 -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_46 -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_47 -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_48 -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_49 -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_50 -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_51 -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_52 -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_53 -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_54 -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_55 -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_56 -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_57 -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_58 -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_59 -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_60 -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_61 -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_TLB_ATTRIBUTE_62 -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN_MASK 0x00008000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_DMA_MASK 0x00800000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB_MASK 0x40000000L -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV_MASK 0x80000000L - -// MP1_SYSHUB_INT_STATUS -#define MP1_SYSHUB_INT_STATUS__RD_ERROR_MASK 0x00000001L -#define MP1_SYSHUB_INT_STATUS__WR_ERROR_MASK 0x00000002L -#define MP1_SYSHUB_INT_STATUS__REG_ERROR_MASK 0x00000004L - -// MP1_SYSHUB_WR_INT_ADDR -#define MP1_SYSHUB_WR_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP1_SYSHUB_WR_INT_OTHER -#define MP1_SYSHUB_WR_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP1_SYSHUB_WR_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP1_SYSHUB_RD_INT_ADDR -#define MP1_SYSHUB_RD_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP1_SYSHUB_RD_INT_OTHER -#define MP1_SYSHUB_RD_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_LENGTH_MASK 0x04000000L -#define MP1_SYSHUB_RD_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP1_SYSHUB_REG_INT_ADDR -#define MP1_SYSHUB_REG_INT_ADDR__ADDR_MASK 0x0000ffffL - -// MP1_SYSHUB_REG_INT_OTHER -#define MP1_SYSHUB_REG_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_AES_MASK 0x00100000L -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_MST_MASK 0x00200000L -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_ADDR_MASK 0x00400000L -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP1_SYSHUB_REG_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP1_SYSHUB_AXCACHE_CFG -#define MP1_SYSHUB_AXCACHE_CFG__ARCACHE_NONCOH_MASK 0x0000000fL -#define MP1_SYSHUB_AXCACHE_CFG__ARCACHE_COH_MASK 0x000000f0L -#define MP1_SYSHUB_AXCACHE_CFG__AWCACHE_NONCOH_MASK 0x00000f00L -#define MP1_SYSHUB_AXCACHE_CFG__AWCACHE_COH_MASK 0x0000f000L -#define MP1_SYSHUB_AXCACHE_CFG__QOSW_MASK 0x000f0000L -#define MP1_SYSHUB_AXCACHE_CFG__QOSR_MASK 0x00f00000L - -// MP1_SYSHUB_DS_OVERRIDE -#define MP1_SYSHUB_DS_OVERRIDE__DS_CNT_MASK 0x000007ffL -#define MP1_SYSHUB_DS_OVERRIDE__DS_DISABLE_MASK 0x00000800L - -// MP1_SYSHUB_OUTSTANDING -#define MP1_SYSHUB_OUTSTANDING__PENDING_WR_MASK 0x0000ffffL -#define MP1_SYSHUB_OUTSTANDING__PENDING_RD_MASK 0x00ff0000L - -// MP_HUBIF_SOC_TLB0_1 -#define MP_HUBIF_SOC_TLB0_1__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_2 -#define MP_HUBIF_SOC_TLB0_2__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_3 -#define MP_HUBIF_SOC_TLB0_3__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_4 -#define MP_HUBIF_SOC_TLB0_4__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_5 -#define MP_HUBIF_SOC_TLB0_5__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_6 -#define MP_HUBIF_SOC_TLB0_6__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_7 -#define MP_HUBIF_SOC_TLB0_7__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_8 -#define MP_HUBIF_SOC_TLB0_8__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_9 -#define MP_HUBIF_SOC_TLB0_9__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_10 -#define MP_HUBIF_SOC_TLB0_10__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_11 -#define MP_HUBIF_SOC_TLB0_11__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_12 -#define MP_HUBIF_SOC_TLB0_12__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_13 -#define MP_HUBIF_SOC_TLB0_13__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_14 -#define MP_HUBIF_SOC_TLB0_14__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_15 -#define MP_HUBIF_SOC_TLB0_15__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_16 -#define MP_HUBIF_SOC_TLB0_16__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_17 -#define MP_HUBIF_SOC_TLB0_17__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_18 -#define MP_HUBIF_SOC_TLB0_18__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_19 -#define MP_HUBIF_SOC_TLB0_19__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_20 -#define MP_HUBIF_SOC_TLB0_20__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_21 -#define MP_HUBIF_SOC_TLB0_21__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_22 -#define MP_HUBIF_SOC_TLB0_22__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_23 -#define MP_HUBIF_SOC_TLB0_23__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_24 -#define MP_HUBIF_SOC_TLB0_24__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_25 -#define MP_HUBIF_SOC_TLB0_25__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_26 -#define MP_HUBIF_SOC_TLB0_26__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_27 -#define MP_HUBIF_SOC_TLB0_27__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_28 -#define MP_HUBIF_SOC_TLB0_28__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_29 -#define MP_HUBIF_SOC_TLB0_29__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_30 -#define MP_HUBIF_SOC_TLB0_30__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_31 -#define MP_HUBIF_SOC_TLB0_31__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_32 -#define MP_HUBIF_SOC_TLB0_32__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_33 -#define MP_HUBIF_SOC_TLB0_33__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_34 -#define MP_HUBIF_SOC_TLB0_34__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_35 -#define MP_HUBIF_SOC_TLB0_35__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_36 -#define MP_HUBIF_SOC_TLB0_36__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_37 -#define MP_HUBIF_SOC_TLB0_37__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_38 -#define MP_HUBIF_SOC_TLB0_38__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_39 -#define MP_HUBIF_SOC_TLB0_39__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_40 -#define MP_HUBIF_SOC_TLB0_40__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_41 -#define MP_HUBIF_SOC_TLB0_41__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_42 -#define MP_HUBIF_SOC_TLB0_42__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_43 -#define MP_HUBIF_SOC_TLB0_43__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_44 -#define MP_HUBIF_SOC_TLB0_44__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_45 -#define MP_HUBIF_SOC_TLB0_45__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_46 -#define MP_HUBIF_SOC_TLB0_46__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_47 -#define MP_HUBIF_SOC_TLB0_47__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_48 -#define MP_HUBIF_SOC_TLB0_48__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_49 -#define MP_HUBIF_SOC_TLB0_49__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_50 -#define MP_HUBIF_SOC_TLB0_50__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_51 -#define MP_HUBIF_SOC_TLB0_51__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_52 -#define MP_HUBIF_SOC_TLB0_52__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_53 -#define MP_HUBIF_SOC_TLB0_53__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_54 -#define MP_HUBIF_SOC_TLB0_54__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_55 -#define MP_HUBIF_SOC_TLB0_55__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_56 -#define MP_HUBIF_SOC_TLB0_56__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_57 -#define MP_HUBIF_SOC_TLB0_57__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_58 -#define MP_HUBIF_SOC_TLB0_58__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_59 -#define MP_HUBIF_SOC_TLB0_59__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_60 -#define MP_HUBIF_SOC_TLB0_60__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_61 -#define MP_HUBIF_SOC_TLB0_61__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB0_62 -#define MP_HUBIF_SOC_TLB0_62__SOC_ADDR_MASK 0x003fffffL - -// MP_HUBIF_SOC_TLB1_1 -#define MP_HUBIF_SOC_TLB1_1__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_1__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_1__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_2 -#define MP_HUBIF_SOC_TLB1_2__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_2__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_2__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_3 -#define MP_HUBIF_SOC_TLB1_3__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_3__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_3__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_4 -#define MP_HUBIF_SOC_TLB1_4__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_4__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_4__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_5 -#define MP_HUBIF_SOC_TLB1_5__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_5__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_5__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_6 -#define MP_HUBIF_SOC_TLB1_6__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_6__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_6__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_7 -#define MP_HUBIF_SOC_TLB1_7__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_7__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_7__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_8 -#define MP_HUBIF_SOC_TLB1_8__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_8__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_8__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_9 -#define MP_HUBIF_SOC_TLB1_9__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_9__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_9__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_10 -#define MP_HUBIF_SOC_TLB1_10__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_10__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_10__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_11 -#define MP_HUBIF_SOC_TLB1_11__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_11__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_11__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_12 -#define MP_HUBIF_SOC_TLB1_12__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_12__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_12__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_13 -#define MP_HUBIF_SOC_TLB1_13__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_13__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_13__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_14 -#define MP_HUBIF_SOC_TLB1_14__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_14__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_14__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_15 -#define MP_HUBIF_SOC_TLB1_15__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_15__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_15__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_16 -#define MP_HUBIF_SOC_TLB1_16__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_16__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_16__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_17 -#define MP_HUBIF_SOC_TLB1_17__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_17__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_17__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_18 -#define MP_HUBIF_SOC_TLB1_18__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_18__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_18__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_19 -#define MP_HUBIF_SOC_TLB1_19__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_19__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_19__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_20 -#define MP_HUBIF_SOC_TLB1_20__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_20__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_20__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_21 -#define MP_HUBIF_SOC_TLB1_21__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_21__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_21__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_22 -#define MP_HUBIF_SOC_TLB1_22__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_22__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_22__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_23 -#define MP_HUBIF_SOC_TLB1_23__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_23__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_23__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_24 -#define MP_HUBIF_SOC_TLB1_24__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_24__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_24__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_25 -#define MP_HUBIF_SOC_TLB1_25__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_25__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_25__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_26 -#define MP_HUBIF_SOC_TLB1_26__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_26__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_26__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_27 -#define MP_HUBIF_SOC_TLB1_27__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_27__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_27__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_28 -#define MP_HUBIF_SOC_TLB1_28__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_28__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_28__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_29 -#define MP_HUBIF_SOC_TLB1_29__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_29__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_29__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_30 -#define MP_HUBIF_SOC_TLB1_30__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_30__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_30__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_31 -#define MP_HUBIF_SOC_TLB1_31__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_31__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_31__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_32 -#define MP_HUBIF_SOC_TLB1_32__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_32__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_32__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_33 -#define MP_HUBIF_SOC_TLB1_33__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_33__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_33__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_34 -#define MP_HUBIF_SOC_TLB1_34__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_34__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_34__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_35 -#define MP_HUBIF_SOC_TLB1_35__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_35__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_35__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_36 -#define MP_HUBIF_SOC_TLB1_36__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_36__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_36__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_37 -#define MP_HUBIF_SOC_TLB1_37__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_37__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_37__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_38 -#define MP_HUBIF_SOC_TLB1_38__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_38__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_38__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_39 -#define MP_HUBIF_SOC_TLB1_39__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_39__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_39__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_40 -#define MP_HUBIF_SOC_TLB1_40__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_40__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_40__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_41 -#define MP_HUBIF_SOC_TLB1_41__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_41__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_41__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_42 -#define MP_HUBIF_SOC_TLB1_42__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_42__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_42__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_43 -#define MP_HUBIF_SOC_TLB1_43__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_43__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_43__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_44 -#define MP_HUBIF_SOC_TLB1_44__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_44__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_44__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_45 -#define MP_HUBIF_SOC_TLB1_45__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_45__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_45__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_46 -#define MP_HUBIF_SOC_TLB1_46__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_46__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_46__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_47 -#define MP_HUBIF_SOC_TLB1_47__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_47__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_47__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_48 -#define MP_HUBIF_SOC_TLB1_48__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_48__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_48__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_49 -#define MP_HUBIF_SOC_TLB1_49__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_49__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_49__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_50 -#define MP_HUBIF_SOC_TLB1_50__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_50__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_50__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_51 -#define MP_HUBIF_SOC_TLB1_51__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_51__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_51__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_52 -#define MP_HUBIF_SOC_TLB1_52__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_52__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_52__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_53 -#define MP_HUBIF_SOC_TLB1_53__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_53__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_53__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_54 -#define MP_HUBIF_SOC_TLB1_54__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_54__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_54__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_55 -#define MP_HUBIF_SOC_TLB1_55__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_55__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_55__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_56 -#define MP_HUBIF_SOC_TLB1_56__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_56__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_56__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_57 -#define MP_HUBIF_SOC_TLB1_57__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_57__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_57__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_58 -#define MP_HUBIF_SOC_TLB1_58__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_58__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_58__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_59 -#define MP_HUBIF_SOC_TLB1_59__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_59__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_59__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_60 -#define MP_HUBIF_SOC_TLB1_60__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_60__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_60__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_61 -#define MP_HUBIF_SOC_TLB1_61__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_61__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_61__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB1_62 -#define MP_HUBIF_SOC_TLB1_62__COHERENCE_MASK 0x00000001L -#define MP_HUBIF_SOC_TLB1_62__SEG_SIZE_MASK 0x0000001eL -#define MP_HUBIF_SOC_TLB1_62__SEG_OFFSET_MASK 0x00003fe0L - -// MP_HUBIF_SOC_TLB2_1 -#define MP_HUBIF_SOC_TLB2_1__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_2 -#define MP_HUBIF_SOC_TLB2_2__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_3 -#define MP_HUBIF_SOC_TLB2_3__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_4 -#define MP_HUBIF_SOC_TLB2_4__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_5 -#define MP_HUBIF_SOC_TLB2_5__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_6 -#define MP_HUBIF_SOC_TLB2_6__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_7 -#define MP_HUBIF_SOC_TLB2_7__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_8 -#define MP_HUBIF_SOC_TLB2_8__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_9 -#define MP_HUBIF_SOC_TLB2_9__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_10 -#define MP_HUBIF_SOC_TLB2_10__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_11 -#define MP_HUBIF_SOC_TLB2_11__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_12 -#define MP_HUBIF_SOC_TLB2_12__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_13 -#define MP_HUBIF_SOC_TLB2_13__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_14 -#define MP_HUBIF_SOC_TLB2_14__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_15 -#define MP_HUBIF_SOC_TLB2_15__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_16 -#define MP_HUBIF_SOC_TLB2_16__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_17 -#define MP_HUBIF_SOC_TLB2_17__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_18 -#define MP_HUBIF_SOC_TLB2_18__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_19 -#define MP_HUBIF_SOC_TLB2_19__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_20 -#define MP_HUBIF_SOC_TLB2_20__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_21 -#define MP_HUBIF_SOC_TLB2_21__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_22 -#define MP_HUBIF_SOC_TLB2_22__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_23 -#define MP_HUBIF_SOC_TLB2_23__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_24 -#define MP_HUBIF_SOC_TLB2_24__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_25 -#define MP_HUBIF_SOC_TLB2_25__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_26 -#define MP_HUBIF_SOC_TLB2_26__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_27 -#define MP_HUBIF_SOC_TLB2_27__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_28 -#define MP_HUBIF_SOC_TLB2_28__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_29 -#define MP_HUBIF_SOC_TLB2_29__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_30 -#define MP_HUBIF_SOC_TLB2_30__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_31 -#define MP_HUBIF_SOC_TLB2_31__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_32 -#define MP_HUBIF_SOC_TLB2_32__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_33 -#define MP_HUBIF_SOC_TLB2_33__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_34 -#define MP_HUBIF_SOC_TLB2_34__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_35 -#define MP_HUBIF_SOC_TLB2_35__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_36 -#define MP_HUBIF_SOC_TLB2_36__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_37 -#define MP_HUBIF_SOC_TLB2_37__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_38 -#define MP_HUBIF_SOC_TLB2_38__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_39 -#define MP_HUBIF_SOC_TLB2_39__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_40 -#define MP_HUBIF_SOC_TLB2_40__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_41 -#define MP_HUBIF_SOC_TLB2_41__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_42 -#define MP_HUBIF_SOC_TLB2_42__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_43 -#define MP_HUBIF_SOC_TLB2_43__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_44 -#define MP_HUBIF_SOC_TLB2_44__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_45 -#define MP_HUBIF_SOC_TLB2_45__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_46 -#define MP_HUBIF_SOC_TLB2_46__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_47 -#define MP_HUBIF_SOC_TLB2_47__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_48 -#define MP_HUBIF_SOC_TLB2_48__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_49 -#define MP_HUBIF_SOC_TLB2_49__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_50 -#define MP_HUBIF_SOC_TLB2_50__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_51 -#define MP_HUBIF_SOC_TLB2_51__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_52 -#define MP_HUBIF_SOC_TLB2_52__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_53 -#define MP_HUBIF_SOC_TLB2_53__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_54 -#define MP_HUBIF_SOC_TLB2_54__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_55 -#define MP_HUBIF_SOC_TLB2_55__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_56 -#define MP_HUBIF_SOC_TLB2_56__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_57 -#define MP_HUBIF_SOC_TLB2_57__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_58 -#define MP_HUBIF_SOC_TLB2_58__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_59 -#define MP_HUBIF_SOC_TLB2_59__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_60 -#define MP_HUBIF_SOC_TLB2_60__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_61 -#define MP_HUBIF_SOC_TLB2_61__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB2_62 -#define MP_HUBIF_SOC_TLB2_62__AWUSER_MASK 0xffffffffL - -// MP_HUBIF_SOC_TLB3_1 -#define MP_HUBIF_SOC_TLB3_1__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_1__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_2 -#define MP_HUBIF_SOC_TLB3_2__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_2__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_3 -#define MP_HUBIF_SOC_TLB3_3__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_3__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_4 -#define MP_HUBIF_SOC_TLB3_4__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_4__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_5 -#define MP_HUBIF_SOC_TLB3_5__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_5__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_6 -#define MP_HUBIF_SOC_TLB3_6__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_6__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_7 -#define MP_HUBIF_SOC_TLB3_7__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_7__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_8 -#define MP_HUBIF_SOC_TLB3_8__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_8__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_9 -#define MP_HUBIF_SOC_TLB3_9__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_9__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_10 -#define MP_HUBIF_SOC_TLB3_10__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_10__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_11 -#define MP_HUBIF_SOC_TLB3_11__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_11__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_12 -#define MP_HUBIF_SOC_TLB3_12__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_12__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_13 -#define MP_HUBIF_SOC_TLB3_13__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_13__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_14 -#define MP_HUBIF_SOC_TLB3_14__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_14__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_15 -#define MP_HUBIF_SOC_TLB3_15__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_15__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_16 -#define MP_HUBIF_SOC_TLB3_16__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_16__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_17 -#define MP_HUBIF_SOC_TLB3_17__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_17__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_18 -#define MP_HUBIF_SOC_TLB3_18__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_18__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_19 -#define MP_HUBIF_SOC_TLB3_19__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_19__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_20 -#define MP_HUBIF_SOC_TLB3_20__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_20__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_21 -#define MP_HUBIF_SOC_TLB3_21__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_21__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_22 -#define MP_HUBIF_SOC_TLB3_22__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_22__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_23 -#define MP_HUBIF_SOC_TLB3_23__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_23__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_24 -#define MP_HUBIF_SOC_TLB3_24__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_24__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_25 -#define MP_HUBIF_SOC_TLB3_25__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_25__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_26 -#define MP_HUBIF_SOC_TLB3_26__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_26__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_27 -#define MP_HUBIF_SOC_TLB3_27__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_27__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_28 -#define MP_HUBIF_SOC_TLB3_28__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_28__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_29 -#define MP_HUBIF_SOC_TLB3_29__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_29__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_30 -#define MP_HUBIF_SOC_TLB3_30__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_30__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_31 -#define MP_HUBIF_SOC_TLB3_31__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_31__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_32 -#define MP_HUBIF_SOC_TLB3_32__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_32__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_33 -#define MP_HUBIF_SOC_TLB3_33__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_33__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_34 -#define MP_HUBIF_SOC_TLB3_34__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_34__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_35 -#define MP_HUBIF_SOC_TLB3_35__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_35__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_36 -#define MP_HUBIF_SOC_TLB3_36__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_36__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_37 -#define MP_HUBIF_SOC_TLB3_37__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_37__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_38 -#define MP_HUBIF_SOC_TLB3_38__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_38__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_39 -#define MP_HUBIF_SOC_TLB3_39__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_39__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_40 -#define MP_HUBIF_SOC_TLB3_40__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_40__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_41 -#define MP_HUBIF_SOC_TLB3_41__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_41__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_42 -#define MP_HUBIF_SOC_TLB3_42__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_42__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_43 -#define MP_HUBIF_SOC_TLB3_43__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_43__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_44 -#define MP_HUBIF_SOC_TLB3_44__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_44__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_45 -#define MP_HUBIF_SOC_TLB3_45__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_45__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_46 -#define MP_HUBIF_SOC_TLB3_46__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_46__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_47 -#define MP_HUBIF_SOC_TLB3_47__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_47__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_48 -#define MP_HUBIF_SOC_TLB3_48__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_48__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_49 -#define MP_HUBIF_SOC_TLB3_49__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_49__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_50 -#define MP_HUBIF_SOC_TLB3_50__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_50__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_51 -#define MP_HUBIF_SOC_TLB3_51__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_51__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_52 -#define MP_HUBIF_SOC_TLB3_52__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_52__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_53 -#define MP_HUBIF_SOC_TLB3_53__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_53__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_54 -#define MP_HUBIF_SOC_TLB3_54__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_54__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_55 -#define MP_HUBIF_SOC_TLB3_55__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_55__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_56 -#define MP_HUBIF_SOC_TLB3_56__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_56__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_57 -#define MP_HUBIF_SOC_TLB3_57__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_57__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_58 -#define MP_HUBIF_SOC_TLB3_58__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_58__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_59 -#define MP_HUBIF_SOC_TLB3_59__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_59__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_60 -#define MP_HUBIF_SOC_TLB3_60__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_60__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_61 -#define MP_HUBIF_SOC_TLB3_61__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_61__WUSER_MASK 0x3c000000L - -// MP_HUBIF_SOC_TLB3_62 -#define MP_HUBIF_SOC_TLB3_62__ARUSER_MASK 0x03ffffffL -#define MP_HUBIF_SOC_TLB3_62__WUSER_MASK 0x3c000000L - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB_MASK 0xffffffffL - -// MP_HUBIF_TLB_ATTRIBUTE_1 -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_2 -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_3 -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_4 -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_5 -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_6 -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_7 -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_8 -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_9 -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_10 -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_11 -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_12 -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_13 -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_14 -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_15 -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_16 -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_17 -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_18 -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_19 -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_20 -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_21 -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_22 -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_23 -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_24 -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_25 -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_26 -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_27 -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_28 -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_29 -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_30 -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_31 -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_32 -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_33 -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_34 -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_35 -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_36 -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_37 -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_38 -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_39 -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_40 -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_41 -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_42 -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_43 -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_44 -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_45 -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_46 -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_47 -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_48 -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_49 -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_50 -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_51 -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_52 -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_53 -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_54 -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_55 -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_56 -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_57 -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_58 -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_59 -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_60 -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_61 -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_TLB_ATTRIBUTE_62 -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1_MASK 0x00000001L -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1_MASK 0x00000002L -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL_MASK 0x00006000L -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_AES_EN_MASK 0x00008000L -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_CCP_MASK 0x00800000L -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_PUB_MASK 0x40000000L -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_PRIV_MASK 0x80000000L - -// MP_HUBIF_INT_STATUS -#define MP_HUBIF_INT_STATUS__RD_ERROR_MASK 0x00000001L -#define MP_HUBIF_INT_STATUS__WR_ERROR_MASK 0x00000002L -#define MP_HUBIF_INT_STATUS__REG_ERROR_MASK 0x00000004L - -// MP_HUBIF_WR_INT_ADDR -#define MP_HUBIF_WR_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP_HUBIF_WR_INT_OTHER -#define MP_HUBIF_WR_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP_HUBIF_WR_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP_HUBIF_WR_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP_HUBIF_WR_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP_HUBIF_WR_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP_HUBIF_WR_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP_HUBIF_WR_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP_HUBIF_WR_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP_HUBIF_RD_INT_ADDR -#define MP_HUBIF_RD_INT_ADDR__ADDR_MASK 0xffffffffL - -// MP_HUBIF_RD_INT_OTHER -#define MP_HUBIF_RD_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP_HUBIF_RD_INT_OTHER__ERROR_TLB_MASK 0x00100000L -#define MP_HUBIF_RD_INT_OTHER__ERROR_PAGE_MASK 0x00200000L -#define MP_HUBIF_RD_INT_OTHER__ERROR_ATTRIB_MASK 0x00400000L -#define MP_HUBIF_RD_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP_HUBIF_RD_INT_OTHER__ERROR_MST_MASK 0x01000000L -#define MP_HUBIF_RD_INT_OTHER__ERROR_AES_MASK 0x02000000L -#define MP_HUBIF_RD_INT_OTHER__ERROR_LENGTH_MASK 0x04000000L -#define MP_HUBIF_RD_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP_HUBIF_REG_INT_ADDR -#define MP_HUBIF_REG_INT_ADDR__ADDR_MASK 0x0000ffffL - -// MP_HUBIF_REG_INT_OTHER -#define MP_HUBIF_REG_INT_OTHER__AXI_ID_MASK 0x0003ffffL -#define MP_HUBIF_REG_INT_OTHER__ERROR_AES_MASK 0x00100000L -#define MP_HUBIF_REG_INT_OTHER__ERROR_MST_MASK 0x00200000L -#define MP_HUBIF_REG_INT_OTHER__ERROR_ADDR_MASK 0x00400000L -#define MP_HUBIF_REG_INT_OTHER__ERROR_PROT_MASK 0x00800000L -#define MP_HUBIF_REG_INT_OTHER__INT_CLEAR_MASK 0x80000000L - -// MP_HUBIF_AXCACHE_CFG -#define MP_HUBIF_AXCACHE_CFG__ARCACHE_NONCOH_MASK 0x0000000fL -#define MP_HUBIF_AXCACHE_CFG__ARCACHE_COH_MASK 0x000000f0L -#define MP_HUBIF_AXCACHE_CFG__AWCACHE_NONCOH_MASK 0x00000f00L -#define MP_HUBIF_AXCACHE_CFG__AWCACHE_COH_MASK 0x0000f000L -#define MP_HUBIF_AXCACHE_CFG__QOSW_MASK 0x000f0000L -#define MP_HUBIF_AXCACHE_CFG__QOSR_MASK 0x00f00000L - -// MP_HUBIF_DS_OVERRIDE -#define MP_HUBIF_DS_OVERRIDE__DS_CNT_MASK 0x000007ffL -#define MP_HUBIF_DS_OVERRIDE__DS_DISABLE_MASK 0x00000800L - -// MP_HUBIF_OUTSTANDING -#define MP_HUBIF_OUTSTANDING__PENDING_WR_MASK 0x0000ffffL -#define MP_HUBIF_OUTSTANDING__PENDING_RD_MASK 0x00ff0000L - -// HUBIF_NB_AX_ADDR_LO -#define HUBIF_NB_AX_ADDR_LO__AX_ADDR_LO_MASK 0xffffffffL - -// HUBIF_NB_AX_MISC -#define HUBIF_NB_AX_MISC__AX_ADDR_HI_MASK 0x0000ffffL -#define HUBIF_NB_AX_MISC__AX_ID_MASK 0x00ff0000L -#define HUBIF_NB_AX_MISC__AX_QOS_MASK 0x0f000000L - -// HUBIF_NB_AX_MISC_2 -#define HUBIF_NB_AX_MISC_2__AX_LEN_MASK 0x000000ffL -#define HUBIF_NB_AX_MISC_2__AX_SIZE_MASK 0x00000700L -#define HUBIF_NB_AX_MISC_2__AX_BURST_MASK 0x00001800L -#define HUBIF_NB_AX_MISC_2__AX_CACHE_MASK 0x0001e000L -#define HUBIF_NB_AX_MISC_2__AX_PROT_MASK 0x000e0000L -#define HUBIF_NB_AX_MISC_2__AX_USER_MASK 0x03f00000L -#define HUBIF_NB_AX_MISC_2__AX_LOCK_MASK 0x0c000000L -#define HUBIF_NB_AX_MISC_2__AX_OPCODE_MASK 0x10000000L -#define HUBIF_NB_AX_MISC_2__AX_TRAN_STRT_MASK 0x20000000L -#define HUBIF_NB_AX_MISC_2__AX_TRAN_END_MASK 0x40000000L - -// HUBIF_NB_WSTRB0 -#define HUBIF_NB_WSTRB0__AX_WSTRB_MASK 0xffffffffL - -// HUBIF_NB_WSTRB1 -#define HUBIF_NB_WSTRB1__AX_WSTRB_MASK 0xffffffffL - -// HUBIF_NB_WDATA0 -#define HUBIF_NB_WDATA0__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA1 -#define HUBIF_NB_WDATA1__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA2 -#define HUBIF_NB_WDATA2__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA3 -#define HUBIF_NB_WDATA3__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA4 -#define HUBIF_NB_WDATA4__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA5 -#define HUBIF_NB_WDATA5__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA6 -#define HUBIF_NB_WDATA6__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA7 -#define HUBIF_NB_WDATA7__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA8 -#define HUBIF_NB_WDATA8__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA9 -#define HUBIF_NB_WDATA9__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA10 -#define HUBIF_NB_WDATA10__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA11 -#define HUBIF_NB_WDATA11__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA12 -#define HUBIF_NB_WDATA12__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA13 -#define HUBIF_NB_WDATA13__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA14 -#define HUBIF_NB_WDATA14__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_WDATA15 -#define HUBIF_NB_WDATA15__AX_WDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA0 -#define HUBIF_NB_RDATA0__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA1 -#define HUBIF_NB_RDATA1__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA2 -#define HUBIF_NB_RDATA2__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA3 -#define HUBIF_NB_RDATA3__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA4 -#define HUBIF_NB_RDATA4__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA5 -#define HUBIF_NB_RDATA5__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA6 -#define HUBIF_NB_RDATA6__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA7 -#define HUBIF_NB_RDATA7__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA8 -#define HUBIF_NB_RDATA8__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA9 -#define HUBIF_NB_RDATA9__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA10 -#define HUBIF_NB_RDATA10__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA11 -#define HUBIF_NB_RDATA11__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA12 -#define HUBIF_NB_RDATA12__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA13 -#define HUBIF_NB_RDATA13__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA14 -#define HUBIF_NB_RDATA14__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_RDATA15 -#define HUBIF_NB_RDATA15__AX_RDATA_MASK 0xffffffffL - -// HUBIF_NB_AXI_RESP -#define HUBIF_NB_AXI_RESP__AXI_RESP_MASK 0x0000ffffL - -// HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ACC_VIOLATION_TYPE_MASK 0x00000006L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR_MASK 0x00000008L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__REG_CLK_STS_MASK 0x00000010L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ALLOW_NON_PRIV_REG_ACC_MASK 0x00000020L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__WRITE_REQ_CNT_EN_MASK 0x00000040L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__READ_REQ_CNT_EN_MASK 0x00000080L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__AXI_ID_MASK 0x03ffff00L -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__AXI_APROT_MASK 0x1c000000L - -// HUBIF_ACC_VIOLATION_LOG_ADDR -#define HUBIF_ACC_VIOLATION_LOG_ADDR__AXI_ADDR_MASK 0xffffffffL - -// SMNIF_TLB_0 -#define SMNIF_TLB_0__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_0__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_1 -#define SMNIF_TLB_1__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_1__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_2 -#define SMNIF_TLB_2__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_2__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_3 -#define SMNIF_TLB_3__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_3__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_4 -#define SMNIF_TLB_4__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_4__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_5 -#define SMNIF_TLB_5__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_5__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_6 -#define SMNIF_TLB_6__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_6__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_7 -#define SMNIF_TLB_7__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_7__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_8 -#define SMNIF_TLB_8__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_8__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_9 -#define SMNIF_TLB_9__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_9__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_10 -#define SMNIF_TLB_10__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_10__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_11 -#define SMNIF_TLB_11__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_11__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_12 -#define SMNIF_TLB_12__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_12__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_13 -#define SMNIF_TLB_13__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_13__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_14 -#define SMNIF_TLB_14__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_14__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLB_15 -#define SMNIF_TLB_15__SMN_ADDR_LOWER_MASK 0x0000ffffL -#define SMNIF_TLB_15__SMN_ADDR_UPPER_MASK 0xffff0000L - -// SMNIF_TLV0 -#define SMNIF_TLV0__TLB0_MASK 0x00000007L -#define SMNIF_TLV0__TLB1_MASK 0x00000070L -#define SMNIF_TLV0__TLB2_MASK 0x00000700L -#define SMNIF_TLV0__TLB3_MASK 0x00007000L -#define SMNIF_TLV0__TLB4_MASK 0x00070000L -#define SMNIF_TLV0__TLB5_MASK 0x00700000L -#define SMNIF_TLV0__TLB6_MASK 0x07000000L -#define SMNIF_TLV0__TLB7_MASK 0x70000000L - -// SMNIF_TLV1 -#define SMNIF_TLV1__TLB8_MASK 0x00000007L -#define SMNIF_TLV1__TLB9_MASK 0x00000070L -#define SMNIF_TLV1__TLB10_MASK 0x00000700L -#define SMNIF_TLV1__TLB11_MASK 0x00007000L -#define SMNIF_TLV1__TLB12_MASK 0x00070000L -#define SMNIF_TLV1__TLB13_MASK 0x00700000L -#define SMNIF_TLV1__TLB14_MASK 0x07000000L -#define SMNIF_TLV1__TLB15_MASK 0x70000000L - -// SMNIF_TLV2 -#define SMNIF_TLV2__TLB16_MASK 0x00000007L -#define SMNIF_TLV2__TLB17_MASK 0x00000070L -#define SMNIF_TLV2__TLB18_MASK 0x00000700L -#define SMNIF_TLV2__TLB19_MASK 0x00007000L -#define SMNIF_TLV2__TLB20_MASK 0x00070000L -#define SMNIF_TLV2__TLB21_MASK 0x00700000L -#define SMNIF_TLV2__TLB22_MASK 0x07000000L -#define SMNIF_TLV2__TLB23_MASK 0x70000000L - -// SMNIF_TLV3 -#define SMNIF_TLV3__TLB24_MASK 0x00000007L -#define SMNIF_TLV3__TLB25_MASK 0x00000070L -#define SMNIF_TLV3__TLB26_MASK 0x00000700L -#define SMNIF_TLV3__TLB27_MASK 0x00007000L -#define SMNIF_TLV3__TLB28_MASK 0x00070000L -#define SMNIF_TLV3__TLB29_MASK 0x00700000L -#define SMNIF_TLV3__TLB30_MASK 0x07000000L -#define SMNIF_TLV3__TLB31_MASK 0x70000000L - -// SMNIF_TLB_QOS -#define SMNIF_TLB_QOS__TLB_QOS_MASK 0xffffffffL - -// SMNIF_ACC_VIOLATION_LOG_ADDR -#define SMNIF_ACC_VIOLATION_LOG_ADDR__AXI_ADDR_MASK 0xffffffffL - -// SMNIF_ACC_VIOLATION_LOG_STATUS -#define SMNIF_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define SMNIF_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE_MASK 0x00000006L -#define SMNIF_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR_MASK 0x00000008L -#define SMNIF_ACC_VIOLATION_LOG_STATUS__AXI_ID_MASK 0x03ffff00L -#define SMNIF_ACC_VIOLATION_LOG_STATUS__AXI_PROT_MASK 0x1c000000L - -// SMNIF_LPBK_WR_VIOL_ADDR -#define SMNIF_LPBK_WR_VIOL_ADDR__AXI_ADDR_MASK 0xffffffffL - -// SMNIF_LPBK_WR_VIOL_STATUS -#define SMNIF_LPBK_WR_VIOL_STATUS__VIOL_DET_MASK 0x00000001L -#define SMNIF_LPBK_WR_VIOL_STATUS__VIOL_CLEAR_MASK 0x00000008L -#define SMNIF_LPBK_WR_VIOL_STATUS__AXI_ID_MASK 0x03ffff00L -#define SMNIF_LPBK_WR_VIOL_STATUS__AXI_PROT_MASK 0x1c000000L - -// SMNIF_LPBK_RD_VIOL_ADDR -#define SMNIF_LPBK_RD_VIOL_ADDR__AXI_ADDR_MASK 0xffffffffL - -// SMNIF_LPBK_RD_VIOL_STATUS -#define SMNIF_LPBK_RD_VIOL_STATUS__VIOL_DET_MASK 0x00000001L -#define SMNIF_LPBK_RD_VIOL_STATUS__VIOL_CLEAR_MASK 0x00000008L -#define SMNIF_LPBK_RD_VIOL_STATUS__AXI_ID_MASK 0x03ffff00L -#define SMNIF_LPBK_RD_VIOL_STATUS__AXI_PROT_MASK 0x1c000000L - -// SMNIF_MISC_CTRL -#define SMNIF_MISC_CTRL__CLK_GATE_EN_MASK 0x00000001L -#define SMNIF_MISC_CTRL__CLK_GATE_OVERRIDE_MASK 0x00000002L -#define SMNIF_MISC_CTRL__CLK_GATE_TIMEOUT_MASK 0x0000003cL -#define SMNIF_MISC_CTRL__REG_CLK_STS_MASK 0x00010000L -#define SMNIF_MISC_CTRL__ALLOW_NON_PRIV_REG_ACC_MASK 0x00020000L -#define SMNIF_MISC_CTRL__WRITE_REQ_CNT_EN_MASK 0x00040000L -#define SMNIF_MISC_CTRL__READ_REQ_CNT_EN_MASK 0x00080000L -#define SMNIF_MISC_CTRL__FORCE_INGRESS_PROT_MASK 0x01000000L - -// SMNIF_REQ_CNT -#define SMNIF_REQ_CNT__WRITE_REQ_CNT_MASK 0x000000ffL -#define SMNIF_REQ_CNT__READ_REQ_CNT_MASK 0x0000ff00L - -// SMNIF_SCRATCH0 -#define SMNIF_SCRATCH0__DATA_MASK 0xffffffffL - -// SMNIF_SCRATCH1 -#define SMNIF_SCRATCH1__DATA_MASK 0xffffffffL - -// SMNIF_SCRATCH2 -#define SMNIF_SCRATCH2__DATA_MASK 0xffffffffL - -// SMNIF_SCRATCH3 -#define SMNIF_SCRATCH3__DATA_MASK 0xffffffffL - -// SMNIF_SECURE_CTRL -#define SMNIF_SECURE_CTRL__ALLOW_NONMP_SRAM_ACCESS_MASK 0x00000001L - -// SMNIF_TLVMASK_SECURE -#define SMNIF_TLVMASK_SECURE__TLV0_MASK_MASK 0x00000007L -#define SMNIF_TLVMASK_SECURE__TLV1_MASK_MASK 0x00000070L -#define SMNIF_TLVMASK_SECURE__TLV2_MASK_MASK 0x00000700L -#define SMNIF_TLVMASK_SECURE__TLV3_MASK_MASK 0x00007000L -#define SMNIF_TLVMASK_SECURE__TLV4_MASK_MASK 0x00070000L -#define SMNIF_TLVMASK_SECURE__TLV5_MASK_MASK 0x00700000L -#define SMNIF_TLVMASK_SECURE__TLV6_MASK_MASK 0x07000000L -#define SMNIF_TLVMASK_SECURE__TLV7_MASK_MASK 0x70000000L - -// SMNIF_TLVMASK_NONSECURE -#define SMNIF_TLVMASK_NONSECURE__TLV0_NSMASK_MASK 0x00000007L -#define SMNIF_TLVMASK_NONSECURE__TLV1_NSMASK_MASK 0x00000070L -#define SMNIF_TLVMASK_NONSECURE__TLV2_NSMASK_MASK 0x00000700L -#define SMNIF_TLVMASK_NONSECURE__TLV3_NSMASK_MASK 0x00007000L -#define SMNIF_TLVMASK_NONSECURE__TLV4_NSMASK_MASK 0x00070000L -#define SMNIF_TLVMASK_NONSECURE__TLV5_NSMASK_MASK 0x00700000L -#define SMNIF_TLVMASK_NONSECURE__TLV6_NSMASK_MASK 0x07000000L -#define SMNIF_TLVMASK_NONSECURE__TLV7_NSMASK_MASK 0x70000000L - -// SMNIF_TLR_0 -#define SMNIF_TLR_0__MASK_MASK 0x000000ffL -#define SMNIF_TLR_0__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_0__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_0__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_0__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_0 -#define SMNIF_TLR_ADDR_0__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_0__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_1 -#define SMNIF_TLR_1__MASK_MASK 0x000000ffL -#define SMNIF_TLR_1__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_1__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_1__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_1__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_1 -#define SMNIF_TLR_ADDR_1__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_1__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_2 -#define SMNIF_TLR_2__MASK_MASK 0x000000ffL -#define SMNIF_TLR_2__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_2__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_2__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_2__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_2 -#define SMNIF_TLR_ADDR_2__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_2__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_3 -#define SMNIF_TLR_3__MASK_MASK 0x000000ffL -#define SMNIF_TLR_3__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_3__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_3__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_3__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_3 -#define SMNIF_TLR_ADDR_3__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_3__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_4 -#define SMNIF_TLR_4__MASK_MASK 0x000000ffL -#define SMNIF_TLR_4__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_4__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_4__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_4__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_4 -#define SMNIF_TLR_ADDR_4__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_4__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_5 -#define SMNIF_TLR_5__MASK_MASK 0x000000ffL -#define SMNIF_TLR_5__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_5__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_5__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_5__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_5 -#define SMNIF_TLR_ADDR_5__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_5__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_6 -#define SMNIF_TLR_6__MASK_MASK 0x000000ffL -#define SMNIF_TLR_6__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_6__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_6__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_6__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_6 -#define SMNIF_TLR_ADDR_6__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_6__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_7 -#define SMNIF_TLR_7__MASK_MASK 0x000000ffL -#define SMNIF_TLR_7__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_7__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_7__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_7__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_7 -#define SMNIF_TLR_ADDR_7__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_7__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_8 -#define SMNIF_TLR_8__MASK_MASK 0x000000ffL -#define SMNIF_TLR_8__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_8__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_8__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_8__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_8 -#define SMNIF_TLR_ADDR_8__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_8__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_9 -#define SMNIF_TLR_9__MASK_MASK 0x000000ffL -#define SMNIF_TLR_9__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_9__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_9__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_9__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_9 -#define SMNIF_TLR_ADDR_9__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_9__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_10 -#define SMNIF_TLR_10__MASK_MASK 0x000000ffL -#define SMNIF_TLR_10__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_10__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_10__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_10__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_10 -#define SMNIF_TLR_ADDR_10__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_10__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_11 -#define SMNIF_TLR_11__MASK_MASK 0x000000ffL -#define SMNIF_TLR_11__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_11__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_11__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_11__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_11 -#define SMNIF_TLR_ADDR_11__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_11__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_12 -#define SMNIF_TLR_12__MASK_MASK 0x000000ffL -#define SMNIF_TLR_12__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_12__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_12__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_12__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_12 -#define SMNIF_TLR_ADDR_12__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_12__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_13 -#define SMNIF_TLR_13__MASK_MASK 0x000000ffL -#define SMNIF_TLR_13__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_13__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_13__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_13__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_13 -#define SMNIF_TLR_ADDR_13__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_13__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_14 -#define SMNIF_TLR_14__MASK_MASK 0x000000ffL -#define SMNIF_TLR_14__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_14__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_14__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_14__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_14 -#define SMNIF_TLR_ADDR_14__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_14__END_ADDR_MASK 0xffff0000L - -// SMNIF_TLR_15 -#define SMNIF_TLR_15__MASK_MASK 0x000000ffL -#define SMNIF_TLR_15__RD_ACC_MASK 0x00000100L -#define SMNIF_TLR_15__WR_ACC_MASK 0x00000200L -#define SMNIF_TLR_15__SLV_ADDR_MASK 0x00003c00L -#define SMNIF_TLR_15__VALID_MASK 0x00008000L - -// SMNIF_TLR_ADDR_15 -#define SMNIF_TLR_ADDR_15__START_ADDR_MASK 0x0000ffffL -#define SMNIF_TLR_ADDR_15__END_ADDR_MASK 0xffff0000L - -// MP_ROM_ACC_VIOLATION_LOG_ADDR -#define MP_ROM_ACC_VIOLATION_LOG_ADDR__ADDRESS_MASK 0xffffffffL - -// MP_ROM_ACC_VIOLATION_LOG_STATUS -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_BLOCK_MASK 0x00000006L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE_MASK 0x00000018L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_PROT_MASK 0x000000e0L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_UNIT_ID_MASK 0x00003f00L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_INIT_ID_MASK 0x003fc000L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ROM_WRITE_DETECTED_MASK 0x01000000L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__UNSECURE_ROM_ACC_DETECTED_MASK 0x02000000L -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR_MASK 0x80000000L - -// MP_ROM_MISC_CNTL -#define MP_ROM_MISC_CNTL__DISABLE_ROM_MASK 0x00000001L -#define MP_ROM_MISC_CNTL__ALLOW_UNPRIVILIGED_REG_ACC_MASK 0x00000002L -#define MP_ROM_MISC_CNTL__ALLOW_UNPRIVILIGED_ROM_ACC_MASK 0x00000004L -#define MP_ROM_MISC_CNTL__RETURN_ERR_ON_VIOLATED_READ_MASK 0x00000008L -#define MP_ROM_MISC_CNTL__HIDE_ROM_KEY_MASK 0x00000010L -#define MP_ROM_MISC_CNTL__CLK_GATE_EN_MASK 0x00010000L -#define MP_ROM_MISC_CNTL__CLK_GATE_OVERRIDE_MASK 0x00020000L -#define MP_ROM_MISC_CNTL__CLK_GATE_TIMEOUT_MASK 0x003c0000L -#define MP_ROM_MISC_CNTL__REGCLK_STATUS_MASK 0x00400000L -#define MP_ROM_MISC_CNTL__SYSCLK_STATUS_MASK 0x00800000L - -// MP_ROM_SCRATCH_0 -#define MP_ROM_SCRATCH_0__RESERVED_MASK 0xffffffffL - -// MP_ROM_SCRATCH_1 -#define MP_ROM_SCRATCH_1__RESERVED_MASK 0xffffffffL - -// MP_ROM_SCRATCH_2 -#define MP_ROM_SCRATCH_2__RESERVED_MASK 0xffffffffL - -// MP_ROM_SCRATCH_3 -#define MP_ROM_SCRATCH_3__RESERVED_MASK 0xffffffffL - -// DMAC_ACC_VIOLATION_LOG_ADDR -#define DMAC_ACC_VIOLATION_LOG_ADDR__AXI_ADDR_MASK 0xffffffffL - -// DMAC_ACC_VIOLATION_LOG_STATUS -#define DMAC_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED_MASK 0x00000001L -#define DMAC_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE_MASK 0x00000006L -#define DMAC_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR_MASK 0x00000008L -#define DMAC_ACC_VIOLATION_LOG_STATUS__AXI_ID_MASK 0x03ffff00L -#define DMAC_ACC_VIOLATION_LOG_STATUS__AXI_APROT_MASK 0x1c000000L - -// DMAC_MISC_CTRL -#define DMAC_MISC_CTRL__ALLOW_NON_PRIV_REG_ACC_MASK 0x00000001L - -// SMUSVI0_PLANE1_LOAD -#define SMUSVI0_PLANE1_LOAD__SVI0_LOADLINE_PLANE1_MASK 0x0000001fL -#define SMUSVI0_PLANE1_LOAD__SVI0_PSI1_PLANE1_MASK 0x00000020L -#define SMUSVI0_PLANE1_LOAD__WAITVIDCOMPDIS_MASK 0x40000000L -#define SMUSVI0_PLANE1_LOAD__SVIBUSY_MASK 0x80000000L - -// SMUSVI0_PLANE0_LOAD -#define SMUSVI0_PLANE0_LOAD__SVI0_LOADLINE_PLANE0_MASK 0x0000001fL -#define SMUSVI0_PLANE0_LOAD__SVI0_PSI1_PLANE0_MASK 0x00000020L - -// SMUSVI0_TFN -#define SMUSVI0_TFN__SVI0_TFN_PLANE0_MASK 0x00000001L -#define SMUSVI0_TFN__SVI0_TFN_PLANE1_MASK 0x00000002L - -// SMUSVI0_TEL_PLANE1 -#define SMUSVI0_TEL_PLANE1__SVI0_PLANE1_IDDCOR_MASK 0x000000ffL -#define SMUSVI0_TEL_PLANE1__SVI0_PLANE1_VDDCOR_MASK 0x01ff0000L - -// SMUSVI0_TEL_PLANE0 -#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000ffL -#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01ff0000L - -// SMUSVI1_TEL_PLANE0 -#define SMUSVI1_TEL_PLANE0__SVI1_PLANE0_IDDCOR_MASK 0x000000ffL -#define SMUSVI1_TEL_PLANE0__SVI1_PLANE0_VDDCOR_MASK 0x01ff0000L - -// SMUSVI1_PLANE0_LOAD -#define SMUSVI1_PLANE0_LOAD__SVI1_LOADLINE_PLANE0_MASK 0x0000001fL -#define SMUSVI1_PLANE0_LOAD__SVI1_PSI1_PLANE0_MASK 0x00000020L -#define SMUSVI1_PLANE0_LOAD__SVIBUSY1_MASK 0x80000000L - -// SMUSVI1_TFN -#define SMUSVI1_TFN__SVI1_TFN_PLANE0_MASK 0x00000001L -#define SMUSVI1_TFN__SVI1_TFN_PLANE1_MASK 0x00000002L - -// SMUSVI1_PLANE0_PSI0 -#define SMUSVI1_PLANE0_PSI0__SVI1_PLANE0_PSI_VID_MASK 0x000000ffL -#define SMUSVI1_PLANE0_PSI0__SVI1_PLANE0_PSI_VID_EN_MASK 0x00000100L - -// SMUSVI0_MISC_VID_STATUS -#define SMUSVI0_MISC_VID_STATUS__MAX_VID_MASK 0x000000ffL -#define SMUSVI0_MISC_VID_STATUS__MIN_VID_MASK 0x0003fc00L -#define SMUSVI0_MISC_VID_STATUS__SVI0_PLANE0_PSI_VID_MASK 0x7f800000L -#define SMUSVI0_MISC_VID_STATUS__SVI0_PLANE0_PSI_VID_EN_MASK 0x80000000L - -// SMUSVI0_PWR_CTL_MISC -#define SMUSVI0_PWR_CTL_MISC__SVI0_PLANE1_PSIVID_MASK 0x0000007fL -#define SMUSVI0_PWR_CTL_MISC__SVI0_PLANE1_PSIVIDEN_MASK 0x00000080L -#define SMUSVI0_PWR_CTL_MISC__SVI0_PLANE1_PSIVID_HI_MASK 0x00000100L -#define SMUSVI0_PWR_CTL_MISC__SVI2HIGHFREQSEL_MASK 0x00004000L - -// SMUSVI0_PLANE_VIDCHG -#define SMUSVI0_PLANE_VIDCHG__SVI0_VIDPLANE_MASK 0x00000003L -#define SMUSVI0_PLANE_VIDCHG__SVI0_VIDCHGZEROVID_MASK 0x00000020L -#define SMUSVI0_PLANE_VIDCHG__SVI0_VIDCHGRAMP_MASK 0x00000040L -#define SMUSVI0_PLANE_VIDCHG__SVI0_VSTIME_MASK 0x00000380L -#define SMUSVI0_PLANE_VIDCHG__SVI0_VID_MASK 0x00ff0000L - -// SMUSVI1_PLANE_VIDCHG -#define SMUSVI1_PLANE_VIDCHG__SVI1_VIDPLANE_MASK 0x00000003L -#define SMUSVI1_PLANE_VIDCHG__SVI1_VIDCHGZEROVID_MASK 0x00000020L -#define SMUSVI1_PLANE_VIDCHG__SVI1_VIDCHGRAMP_MASK 0x00000040L -#define SMUSVI1_PLANE_VIDCHG__SVI1_VSTIME_MASK 0x00000380L -#define SMUSVI1_PLANE_VIDCHG__SVI1_VID_MASK 0x00ff0000L - -// SMUSVI_WARMRESET_TARGET_VID -#define SMUSVI_WARMRESET_TARGET_VID__SVI0_PLANE0_WARMRESET_TAGET_VID_MASK 0x000000ffL -#define SMUSVI_WARMRESET_TARGET_VID__SVI0_PLANE1_WARMRESET_TAGET_VID_MASK 0x0000ff00L -#define SMUSVI_WARMRESET_TARGET_VID__SVI1_PLANE0_WARMRESET_TAGET_VID_MASK 0x00ff0000L -#define SMUSVI_WARMRESET_TARGET_VID__SVI1_PLANE1_WARMRESET_TAGET_VID_MASK 0xff000000L - -// SMUSVI_WARMRESET_SEL -#define SMUSVI_WARMRESET_SEL__SVI0_PLANE0_WARMRESET_SEL_MASK 0x00000003L -#define SMUSVI_WARMRESET_SEL__SVI0_PLANE1_WARMRESET_SEL_MASK 0x0000000cL -#define SMUSVI_WARMRESET_SEL__SVI1_PLANE0_WARMRESET_SEL_MASK 0x00000030L -#define SMUSVI_WARMRESET_SEL__SVI1_PLANE1_WARMRESET_SEL_MASK 0x000000c0L - -// SMUSVI0_PLANE0_VIDCHGBUSY -#define SMUSVI0_PLANE0_VIDCHGBUSY__SVI0_PLANE0_VID_CHGBUSY_MASK 0x00000001L - -// SMUSVI0_PLANE1_VIDCHGBUSY -#define SMUSVI0_PLANE1_VIDCHGBUSY__SVI0_PLANE1_VID_CHGBUSY_MASK 0x00000001L - -// SMUSVI1_PLANE0_VIDCHGBUSY -#define SMUSVI1_PLANE0_VIDCHGBUSY__SVI1_PLANE0_VID_CHGBUSY_MASK 0x00000001L - -// SMUSVI1_PLANE1_VIDCHGBUSY -#define SMUSVI1_PLANE1_VIDCHGBUSY__SVI1_PLANE1_VID_CHGBUSY_MASK 0x00000001L - -// SMUSVI0_PLANE0_CURRENTVID -#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xff000000L - -// SMUSVI1_PLANE0_CURRENTVID -#define SMUSVI1_PLANE0_CURRENTVID__CURRENT_SVI1_PLANE0_VID_MASK 0xff000000L - -// SMUSVI0_PLANE1_CURRENTVID -#define SMUSVI0_PLANE1_CURRENTVID__CURRENT_SVI0_PLANE1_VID_MASK 0xff000000L - -// SMUSVI_ALL_CPU_IN_CC6 -#define SMUSVI_ALL_CPU_IN_CC6__ALL_CPU_IN_CC6_MASK 0x00000001L - -// SMUSVI_BOOTVID -#define SMUSVI_BOOTVID__BOOTSVD_VR0_MASK 0x00000001L -#define SMUSVI_BOOTVID__BOOTSVC_VR0_MASK 0x00000002L -#define SMUSVI_BOOTVID__BOOTSVD_VR1_MASK 0x00000004L -#define SMUSVI_BOOTVID__BOOTSVC_VR1_MASK 0x00000008L -#define SMUSVI_BOOTVID__SVI0_PLANE1_STARTUP_COMPL_EN_MASK 0x00000100L -#define SMUSVI_BOOTVID__SVI0_PLANE0_STARTUP_COMPL_EN_MASK 0x00000200L -#define SMUSVI_BOOTVID__SVI1_PLANE0_STARTUP_COMPL_EN_MASK 0x00000400L - -// SMUSVI_STARTUP_VID_COMPLETE -#define SMUSVI_STARTUP_VID_COMPLETE__STARTUP_SVI1_PLANE0_COMPLETE_MASK 0x00000001L -#define SMUSVI_STARTUP_VID_COMPLETE__STARTUP_SVI0_PLANE0_COMPLETE_MASK 0x00000002L -#define SMUSVI_STARTUP_VID_COMPLETE__STARTUP_SVI0_PLANE1_COMPLETE_MASK 0x00000004L - -// SMUSVI_WARM_RESET -#define SMUSVI_WARM_RESET__WARM_RESET_MASK 0x00000001L - -// SMUSVI_SVC0 -#define SMUSVI_SVC0__SCHMEN_MASK 0x00000002L -#define SMUSVI_SVC0__PU_MASK 0x00000004L -#define SMUSVI_SVC0__PD_MASK 0x00000008L -#define SMUSVI_SVC0__S0_MASK 0x00000040L -#define SMUSVI_SVC0__S1_MASK 0x00000080L -#define SMUSVI_SVC0__OE_OVERRIDE_MASK 0x00020000L -#define SMUSVI_SVC0__OE_MASK 0x00040000L -#define SMUSVI_SVC0__A_OVERRIDE_MASK 0x00080000L -#define SMUSVI_SVC0__A_MASK 0x00100000L -#define SMUSVI_SVC0__Y_MASK 0x80000000L - -// SMUSVI_SVD0 -#define SMUSVI_SVD0__SCHMEN_MASK 0x00000002L -#define SMUSVI_SVD0__PU_MASK 0x00000004L -#define SMUSVI_SVD0__PD_MASK 0x00000008L -#define SMUSVI_SVD0__S0_MASK 0x00000040L -#define SMUSVI_SVD0__S1_MASK 0x00000080L -#define SMUSVI_SVD0__OE_OVERRIDE_MASK 0x00020000L -#define SMUSVI_SVD0__OE_MASK 0x00040000L -#define SMUSVI_SVD0__A_OVERRIDE_MASK 0x00080000L -#define SMUSVI_SVD0__A_MASK 0x00100000L -#define SMUSVI_SVD0__Y_MASK 0x80000000L - -// SMUSVI_SVT0 -#define SMUSVI_SVT0__SCHMEN_MASK 0x00000001L -#define SMUSVI_SVT0__OE_MASK 0x00000002L -#define SMUSVI_SVT0__PU_MASK 0x00000004L -#define SMUSVI_SVT0__PD_MASK 0x00000008L -#define SMUSVI_SVT0__S0_MASK 0x00000040L -#define SMUSVI_SVT0__S1_MASK 0x00000080L -#define SMUSVI_SVT0__A_MASK 0x00100000L -#define SMUSVI_SVT0__Y_MASK 0x80000000L - -// SMUSVI_PLANE_USAGE -#define SMUSVI_PLANE_USAGE__SVI0_PLANE0_USAGE_MASK 0x00000001L -#define SMUSVI_PLANE_USAGE__SVI0_PLANE1_USAGE_MASK 0x00000002L -#define SMUSVI_PLANE_USAGE__SVI1_PLANE0_USAGE_MASK 0x00000004L -#define SMUSVI_PLANE_USAGE__SVI1_PLANE1_USAGE_MASK 0x00000008L - -// SMUIO_MCM_CONFIG -#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L -#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001cL -#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L - -// SMUSVI_STARTUP_VID_EN -#define SMUSVI_STARTUP_VID_EN__STARTUP_VID_EN_MASK 0x00000001L - -// SMUSVI_STARTUP_VID_TRIGGER -#define SMUSVI_STARTUP_VID_TRIGGER__STARTUP_VID_TRIGGER_MASK 0x00000001L - -// SMUIO_RESET_SEL -#define SMUIO_RESET_SEL__SMUIO_RESET_SEL_MASK 0x00000001L - -// SMUIO_MP_RESET_INTR -#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L - -// SMUIO_RESET_DELAY -#define SMUIO_RESET_DELAY__SMUIO_RESET_DELAY_MASK 0x0000ffffL - -// ROM_CNTL -#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L - -// PAGE_MIRROR_CNTL -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00ffffffL -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0c000000L - -// ROM_STATUS -#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L - -// CGTT_ROM_CLK_CTRL0 -#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL -#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L - -// ROM_INDEX -#define ROM_INDEX__ROM_INDEX_MASK 0x00ffffffL - -// ROM_DATA -#define ROM_DATA__ROM_DATA_MASK 0xffffffffL - -// ROM_START -#define ROM_START__ROM_START_MASK 0x00ffffffL - -// ROM_SW_CNTL -#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000ffffL -#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L -#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L - -// ROM_SW_STATUS -#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L - -// ROM_SW_COMMAND -#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000ffL -#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00L - -// ROM_SW_DATA_1 -#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_2 -#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_3 -#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_4 -#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_5 -#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_6 -#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_7 -#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_8 -#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_9 -#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_10 -#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_11 -#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_12 -#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_13 -#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_14 -#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_15 -#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_16 -#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_17 -#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_18 -#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_19 -#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_20 -#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_21 -#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_22 -#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_23 -#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_24 -#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_25 -#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_26 -#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_27 -#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_28 -#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_29 -#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_30 -#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_31 -#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_32 -#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_33 -#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_34 -#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_35 -#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_36 -#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_37 -#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_38 -#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_39 -#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_40 -#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_41 -#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_42 -#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_43 -#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_44 -#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_45 -#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_46 -#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_47 -#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_48 -#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_49 -#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_50 -#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_51 -#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_52 -#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_53 -#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_54 -#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_55 -#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_56 -#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_57 -#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_58 -#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_59 -#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_60 -#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_61 -#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_62 -#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_63 -#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffffL - -// ROM_SW_DATA_64 -#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffffL - -// SMU_GPIOPAD_SW_INT_STAT -#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L - -// SMU_GPIOPAD_MASK -#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL - -// SMU_GPIOPAD_A -#define SMU_GPIOPAD_A__GPIO_A_MASK 0x7fffffffL - -// SMU_GPIOPAD_TXIMPSEL -#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7fffffffL - -// SMU_GPIOPAD_EN -#define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL - -// SMU_GPIOPAD_Y -#define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL - -// SMU_GPIOPAD_RXEN -#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7fffffffL - -// SMU_GPIOPAD_RCVR_SEL0 -#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7fffffffL - -// SMU_GPIOPAD_RCVR_SEL1 -#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7fffffffL - -// SMU_GPIOPAD_PU_EN -#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL - -// SMU_GPIOPAD_PD_EN -#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL - -// SMU_GPIOPAD_PINSTRAPS -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L - -// SMU_GPIOPAD_INT_STAT_EN -#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL -#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L - -// SMU_GPIOPAD_INT_STAT -#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL -#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L - -// SMU_GPIOPAD_INT_STAT_AK -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L -#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L - -// SMU_GPIOPAD_INT_EN -#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL -#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L - -// SMU_GPIOPAD_INT_TYPE -#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL -#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L - -// SMU_GPIOPAD_INT_POLARITY -#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL -#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L - -// ROM_CC_BIF_PINSTRAP -#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L -#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_PIN_MASK 0x0000000eL -#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L -#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L -#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L -#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L -#define ROM_CC_BIF_PINSTRAP__BIF_TX_HALF_SWING_MASK 0x00000400L - -// IO_SMUIO_PINSTRAP -#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L -#define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L -#define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000e0L -#define IO_SMUIO_PINSTRAP__TX_DEEMPH_EN_MASK 0x00000100L - -// SMUIO_PCC_CONTROL -#define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L - -// SMUIO_PCC_GPIO_SELECT -#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xffffffffL - -// SMUIO_GPIO_INT_SELECT -#define SMUIO_GPIO_INT_SELECT__GPIO_INT_SELECT_MASK 0xffffffffL - -// SMIO_INDEX -#define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L - -// S0_VID_SMIO_CNTL -#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xffffffffL - -// S1_VID_SMIO_CNTL -#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xffffffffL - -// OPEN_DRAIN_SELECT -#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7fffffffL -#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L - -// SMIO_ENABLE -#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xffffffffL - -// CPL_VDDCR_SOC_IDLE -#define CPL_VDDCR_SOC_IDLE__CPL_VDDCR_SOC_IDLE_MASK 0x00000001L - -// ROM_SW_SECURE -#define ROM_SW_SECURE__ROM_WR_ACCESS_DISABLE_MASK 0x00000001L - -// GDS_CONFIG -#define GDS_CONFIG__WRITE_DIS_MASK 0x00000001L -#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L -#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L -#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L -#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L - -// GDS_CNTL_STATUS -#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L -#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L -#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L -#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L -#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L -#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L -#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L -#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L -#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L -#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L - -// GDS_ENHANCE2 -#define GDS_ENHANCE2__MISC_MASK 0x0000ffffL -#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000L - -// GDS_PROTECTION_FAULT -#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L -#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L -#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L -#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L -#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003c0L -#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000c00L -#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000f000L -#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000L - -// GDS_VM_PROTECTION_FAULT -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L -#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L -#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L -#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L -#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L -#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000f00L -#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000L - -// GDS_EDC_CNT -#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L -#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000cL -#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_CNT__UNUSED_MASK 0xffffffc0L - -// GDS_EDC_GRBM_CNT -#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L -#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000cL -#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xfffffff0L - -// GDS_EDC_OA_DED -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L -#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L -#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L -#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L -#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L -#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L -#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L -#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L -#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L -#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L -#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000L - -// GDS_DEBUG_CNTL -#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x0000001fL -#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0L - -// GDS_DEBUG_DATA -#define GDS_DEBUG_DATA__DATA_MASK 0xffffffffL - -// GDS_DSM_CNTL -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L -#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L -#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L -#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L -#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L -#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GDS_DSM_CNTL__UNUSED_MASK 0xffff8000L - -// GDS_EDC_OA_PHY_CNT -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000cL -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000c0L -#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L -#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xfffffc00L - -// GDS_EDC_OA_PIPE_CNT -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000cL -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000c0L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000c00L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000c000L -#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xffff0000L - -// GDS_DSM_CNTL2 -#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GDS_DSM_CNTL2__UNUSED_MASK 0x03ff8000L -#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xfc000000L - -// GDS_WD_GDS_CSB -#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001fffL -#define GDS_WD_GDS_CSB__UNUSED_MASK 0xffffe000L - -// GDS_VMID0_BASE -#define GDS_VMID0_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID1_BASE -#define GDS_VMID1_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID2_BASE -#define GDS_VMID2_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID3_BASE -#define GDS_VMID3_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID4_BASE -#define GDS_VMID4_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID5_BASE -#define GDS_VMID5_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID6_BASE -#define GDS_VMID6_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID7_BASE -#define GDS_VMID7_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID8_BASE -#define GDS_VMID8_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID9_BASE -#define GDS_VMID9_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID10_BASE -#define GDS_VMID10_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID11_BASE -#define GDS_VMID11_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID12_BASE -#define GDS_VMID12_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID13_BASE -#define GDS_VMID13_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID14_BASE -#define GDS_VMID14_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID15_BASE -#define GDS_VMID15_BASE__BASE_MASK 0x0000ffffL - -// GDS_VMID0_SIZE -#define GDS_VMID0_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID1_SIZE -#define GDS_VMID1_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID2_SIZE -#define GDS_VMID2_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID3_SIZE -#define GDS_VMID3_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID4_SIZE -#define GDS_VMID4_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID5_SIZE -#define GDS_VMID5_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID6_SIZE -#define GDS_VMID6_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID7_SIZE -#define GDS_VMID7_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID8_SIZE -#define GDS_VMID8_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID9_SIZE -#define GDS_VMID9_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID10_SIZE -#define GDS_VMID10_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID11_SIZE -#define GDS_VMID11_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID12_SIZE -#define GDS_VMID12_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID13_SIZE -#define GDS_VMID13_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID14_SIZE -#define GDS_VMID14_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_VMID15_SIZE -#define GDS_VMID15_SIZE__SIZE_MASK 0x0001ffffL - -// GDS_GWS_VMID0 -#define GDS_GWS_VMID0__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID0__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID1 -#define GDS_GWS_VMID1__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID1__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID2 -#define GDS_GWS_VMID2__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID2__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID3 -#define GDS_GWS_VMID3__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID3__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID4 -#define GDS_GWS_VMID4__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID4__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID5 -#define GDS_GWS_VMID5__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID5__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID6 -#define GDS_GWS_VMID6__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID6__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID7 -#define GDS_GWS_VMID7__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID7__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID8 -#define GDS_GWS_VMID8__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID8__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID9 -#define GDS_GWS_VMID9__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID9__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID10 -#define GDS_GWS_VMID10__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID10__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID11 -#define GDS_GWS_VMID11__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID11__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID12 -#define GDS_GWS_VMID12__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID12__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID13 -#define GDS_GWS_VMID13__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID13__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID14 -#define GDS_GWS_VMID14__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID14__SIZE_MASK 0x007f0000L - -// GDS_GWS_VMID15 -#define GDS_GWS_VMID15__BASE_MASK 0x0000003fL -#define GDS_GWS_VMID15__SIZE_MASK 0x007f0000L - -// GDS_OA_VMID0 -#define GDS_OA_VMID0__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID1 -#define GDS_OA_VMID1__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID2 -#define GDS_OA_VMID2__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID3 -#define GDS_OA_VMID3__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID4 -#define GDS_OA_VMID4__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID5 -#define GDS_OA_VMID5__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID6 -#define GDS_OA_VMID6__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID7 -#define GDS_OA_VMID7__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID8 -#define GDS_OA_VMID8__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID9 -#define GDS_OA_VMID9__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID10 -#define GDS_OA_VMID10__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID11 -#define GDS_OA_VMID11__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID12 -#define GDS_OA_VMID12__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID13 -#define GDS_OA_VMID13__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID14 -#define GDS_OA_VMID14__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000L - -// GDS_OA_VMID15 -#define GDS_OA_VMID15__MASK_MASK 0x0000ffffL -#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000L - -// GDS_GWS_RESET0 -#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L -#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L -#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L -#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L -#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L -#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L -#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L -#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L -#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L -#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L -#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L -#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L -#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L -#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L -#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L -#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L -#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L -#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L -#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L -#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L -#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L -#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L -#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L -#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L -#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L -#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L -#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L -#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L -#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L -#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L -#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L -#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L - -// GDS_GWS_RESET1 -#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L -#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L -#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L -#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L -#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L -#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L -#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L -#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L -#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L -#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L -#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L -#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L -#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L -#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L -#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L -#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L -#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L -#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L -#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L -#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L -#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L -#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L -#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L -#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L -#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L -#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L -#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L -#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L -#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L -#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L -#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L -#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L - -// GDS_GWS_RESOURCE_RESET -#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000ff00L - -// GDS_COMPUTE_MAX_WAVE_ID -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL - -// GDS_OA_RESET_MASK -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L -#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L -#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000L - -// GDS_OA_RESET -#define GDS_OA_RESET__RESET_MASK 0x00000001L -#define GDS_OA_RESET__PIPE_ID_MASK 0x0000ff00L - -// GDS_ENHANCE -#define GDS_ENHANCE__MISC_MASK 0x0000ffffL -#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L -#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L -#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L -#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L -#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L -#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L -#define GDS_ENHANCE__UNUSED_MASK 0xffc00000L - -// GDS_OA_CGPG_RESTORE -#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000ffL -#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000f00L -#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000f000L -#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000f0000L -#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000L - -// GDS_CS_CTXSW_STATUS -#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L -#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L -#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffcL - -// GDS_CS_CTXSW_CNT0 -#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_CS_CTXSW_CNT1 -#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_CS_CTXSW_CNT2 -#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_CS_CTXSW_CNT3 -#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_GFX_CTXSW_STATUS -#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L -#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L -#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffcL - -// GDS_VS_CTXSW_CNT0 -#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_VS_CTXSW_CNT1 -#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_VS_CTXSW_CNT2 -#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_VS_CTXSW_CNT3 -#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS0_CTXSW_CNT0 -#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS1_CTXSW_CNT0 -#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS2_CTXSW_CNT0 -#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS3_CTXSW_CNT0 -#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS4_CTXSW_CNT0 -#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS5_CTXSW_CNT0 -#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS6_CTXSW_CNT0 -#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS7_CTXSW_CNT0 -#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_PS0_CTXSW_CNT1 -#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS1_CTXSW_CNT1 -#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS2_CTXSW_CNT1 -#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS3_CTXSW_CNT1 -#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS4_CTXSW_CNT1 -#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS5_CTXSW_CNT1 -#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS6_CTXSW_CNT1 -#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS7_CTXSW_CNT1 -#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_PS0_CTXSW_CNT2 -#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS1_CTXSW_CNT2 -#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS2_CTXSW_CNT2 -#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS3_CTXSW_CNT2 -#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS4_CTXSW_CNT2 -#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS5_CTXSW_CNT2 -#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS6_CTXSW_CNT2 -#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS7_CTXSW_CNT2 -#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_PS0_CTXSW_CNT3 -#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS1_CTXSW_CNT3 -#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS2_CTXSW_CNT3 -#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS3_CTXSW_CNT3 -#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS4_CTXSW_CNT3 -#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS5_CTXSW_CNT3 -#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS6_CTXSW_CNT3 -#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_PS7_CTXSW_CNT3 -#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_GS_CTXSW_CNT0 -#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000ffffL -#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xffff0000L - -// GDS_GS_CTXSW_CNT1 -#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000ffffL -#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xffff0000L - -// GDS_GS_CTXSW_CNT2 -#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000ffffL -#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xffff0000L - -// GDS_GS_CTXSW_CNT3 -#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000ffffL -#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xffff0000L - -// GDS_RD_ADDR -#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffffL - -// GDS_RD_DATA -#define GDS_RD_DATA__READ_DATA_MASK 0xffffffffL - -// GDS_RD_BURST_ADDR -#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffffL - -// GDS_RD_BURST_COUNT -#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffffL - -// GDS_RD_BURST_DATA -#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffffL - -// GDS_WR_ADDR -#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffffL - -// GDS_WR_DATA -#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffffL - -// GDS_WR_BURST_ADDR -#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffffL - -// GDS_WR_BURST_DATA -#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffffL - -// GDS_WRITE_COMPLETE -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffffL - -// GDS_ATOM_CNTL -#define GDS_ATOM_CNTL__AINC_MASK 0x0000003fL -#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000c0L -#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L -#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00L - -// GDS_ATOM_COMPLETE -#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L -#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffeL - -// GDS_ATOM_BASE -#define GDS_ATOM_BASE__BASE_MASK 0x0000ffffL -#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000L - -// GDS_ATOM_SIZE -#define GDS_ATOM_SIZE__SIZE_MASK 0x0000ffffL -#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000L - -// GDS_ATOM_OFFSET0 -#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000ffL -#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00L - -// GDS_ATOM_OFFSET1 -#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000ffL -#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00L - -// GDS_ATOM_DST -#define GDS_ATOM_DST__DST_MASK 0xffffffffL - -// GDS_ATOM_OP -#define GDS_ATOM_OP__OP_MASK 0x000000ffL -#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00L - -// GDS_ATOM_SRC0 -#define GDS_ATOM_SRC0__DATA_MASK 0xffffffffL - -// GDS_ATOM_SRC0_U -#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffffL - -// GDS_ATOM_SRC1 -#define GDS_ATOM_SRC1__DATA_MASK 0xffffffffL - -// GDS_ATOM_SRC1_U -#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffffL - -// GDS_ATOM_READ0 -#define GDS_ATOM_READ0__DATA_MASK 0xffffffffL - -// GDS_ATOM_READ0_U -#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffffL - -// GDS_ATOM_READ1 -#define GDS_ATOM_READ1__DATA_MASK 0xffffffffL - -// GDS_ATOM_READ1_U -#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffffL - -// GDS_GWS_RESOURCE_CNTL -#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003fL -#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0L - -// GDS_GWS_RESOURCE -#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L -#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001ffeL -#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L -#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L -#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L -#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0fff0000L -#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L -#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L -#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L -#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L - -// GDS_GWS_RESOURCE_CNT -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000ffffL -#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000L - -// GDS_OA_CNTL -#define GDS_OA_CNTL__INDEX_MASK 0x0000000fL -#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0L - -// GDS_OA_COUNTER -#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffffL - -// GDS_OA_ADDRESS -#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000ffffL -#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000f0000L -#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L -#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000L -#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L -#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L - -// GDS_OA_INCDEC -#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffffL -#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L - -// GDS_OA_RING_SIZE -#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffffL - -// GDS_PERFCOUNTER0_LO -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GDS_PERFCOUNTER1_LO -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GDS_PERFCOUNTER2_LO -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GDS_PERFCOUNTER3_LO -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GDS_PERFCOUNTER0_HI -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GDS_PERFCOUNTER1_HI -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GDS_PERFCOUNTER2_HI -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GDS_PERFCOUNTER3_HI -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GDS_PERFCOUNTER0_SELECT -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L - -// GDS_PERFCOUNTER1_SELECT -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L - -// GDS_PERFCOUNTER2_SELECT -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L - -// GDS_PERFCOUNTER3_SELECT -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L - -// GDS_PERFCOUNTER0_SELECT1 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L - -// CGTT_GDS_CLK_CTRL -#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// GDS_DEBUG_REG0 -#define GDS_DEBUG_REG0__spare1_MASK 0x0000003fL -#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x00000040L -#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0x00000f80L -#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x00001000L -#define GDS_DEBUG_REG0__cstate_MASK 0x0001e000L -#define GDS_DEBUG_REG0__buff_write_MASK 0x00020000L -#define GDS_DEBUG_REG0__flush_request_MASK 0x00040000L -#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x00080000L -#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x00100000L -#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x00200000L -#define GDS_DEBUG_REG0__spare_MASK 0xffc00000L - -// GDS_DEBUG_REG1 -#define GDS_DEBUG_REG1__tag_hit_MASK 0x00000001L -#define GDS_DEBUG_REG1__tag_miss_MASK 0x00000002L -#define GDS_DEBUG_REG1__pixel_addr_MASK 0x0001fffcL -#define GDS_DEBUG_REG1__pixel_vld_MASK 0x00020000L -#define GDS_DEBUG_REG1__data_ready_MASK 0x00040000L -#define GDS_DEBUG_REG1__awaiting_data_MASK 0x00080000L -#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x00100000L -#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x00200000L -#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x00400000L -#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x00800000L -#define GDS_DEBUG_REG1__spare_MASK 0xff000000L - -// GDS_DEBUG_REG2 -#define GDS_DEBUG_REG2__ds_full_MASK 0x00000001L -#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x00000002L -#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x00000004L -#define GDS_DEBUG_REG2__cmd_write_MASK 0x00000008L -#define GDS_DEBUG_REG2__app_sel_MASK 0x000000f0L -#define GDS_DEBUG_REG2__req_MASK 0x007fff00L -#define GDS_DEBUG_REG2__spare_MASK 0xff800000L - -// GDS_DEBUG_REG3 -#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x000007ffL -#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x00007800L -#define GDS_DEBUG_REG3__spare_MASK 0xffff8000L - -// GDS_DEBUG_REG4 -#define GDS_DEBUG_REG4__gws_busy_MASK 0x00000001L -#define GDS_DEBUG_REG4__gws_req_MASK 0x00000002L -#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x00000004L -#define GDS_DEBUG_REG4__cur_reso_MASK 0x000001f8L -#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x00000200L -#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x00000400L -#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x00000800L -#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x00001000L -#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x00002000L -#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x00004000L -#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x00008000L -#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x00010000L -#define GDS_DEBUG_REG4__cmd_write_MASK 0x00020000L -#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x00040000L -#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x00080000L -#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x00100000L -#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x00200000L -#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x00400000L -#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x00800000L -#define GDS_DEBUG_REG4__spare_MASK 0xff000000L - -// GDS_DEBUG_REG5 -#define GDS_DEBUG_REG5__write_dis_MASK 0x00000001L -#define GDS_DEBUG_REG5__dec_error_MASK 0x00000002L -#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x00000004L -#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x00000008L -#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x00000010L -#define GDS_DEBUG_REG5__spare_MASK 0x000000e0L -#define GDS_DEBUG_REG5__error_ds_address_MASK 0x003fff00L -#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000L - -// GDS_DEBUG_REG6 -#define GDS_DEBUG_REG6__oa_busy_MASK 0x00000001L -#define GDS_DEBUG_REG6__counters_enabled_MASK 0x0000001eL -#define GDS_DEBUG_REG6__counters_busy_MASK 0x001fffe0L -#define GDS_DEBUG_REG6__spare_MASK 0xffe00000L - -// GDS_DEBUG_REG7 -#define GDS_DEBUG_REG7__csb_inc_total_MASK 0xffffffffL - -// GDS_DEBUG_REG8 -#define GDS_DEBUG_REG8__csb_dec_total_MASK 0xffffffffL - -// CB_HW_CONTROL -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L -#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L - -// CB_HW_CONTROL_1 -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L -#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xfc000000L - -// CB_HW_CONTROL_2 -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0f000000L -#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000L - -// CB_HW_CONTROL_3 -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L -#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L -#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L -#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L -#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L -#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L -#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L -#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L - -// CB_HW_MEM_ARBITER_RD -#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L -#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003cL -#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003c0L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000c00L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000c000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000c0000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L -#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L -#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1c000000L -#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L - -// CB_HW_MEM_ARBITER_WR -#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L -#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003cL -#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003c0L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000c00L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000c000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000c0000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L -#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L -#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1c000000L -#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L - -// CB_DCC_CONFIG -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001fL -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000ff00L -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007f0000L -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0f000000L -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000L - -// CB_DEBUG_BUS_1 - -// CB_DEBUG_BUS_2 - -// CB_DEBUG_BUS_3 - -// CB_DEBUG_BUS_4 - -// CB_DEBUG_BUS_5 - -// CB_DEBUG_BUS_6 - -// CB_DEBUG_BUS_7 - -// CB_DEBUG_BUS_8 - -// CB_DEBUG_BUS_9 - -// CB_DEBUG_BUS_10 - -// CB_DEBUG_BUS_11 - -// CB_DEBUG_BUS_12 - -// CB_DEBUG_BUS_13 - -// CB_DEBUG_BUS_14 - -// CB_DEBUG_BUS_15 - -// CB_DEBUG_BUS_16 - -// CB_DEBUG_BUS_17 -#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x00000001L -#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x00000002L -#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x00000004L -#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x00000008L -#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x00000010L -#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x00000020L -#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x00000040L -#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x00000080L -#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x00000100L -#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x00000200L -#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x00000400L -#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x0007f800L - -// CB_DEBUG_BUS_18 -#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x00000001L -#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x00000002L -#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x00000004L -#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x00000008L -#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x00000010L -#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x00000020L -#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x00000040L -#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x00000080L -#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x00000100L -#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x00000200L -#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x00000400L -#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x00000800L -#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x00001000L -#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x00002000L -#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x00004000L -#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x00008000L -#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x00010000L -#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x00020000L -#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x00040000L -#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x00080000L -#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x00100000L -#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x00200000L - -// CB_DEBUG_BUS_19 -#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x00000003L -#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x00000004L -#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x00000008L -#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x00000010L -#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x00000020L -#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x00000040L -#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x00000080L -#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x00000100L -#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x00000200L -#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x00000400L -#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x00000800L -#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x00001000L -#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x00002000L -#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x00004000L -#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x00008000L -#define CB_DEBUG_BUS_19__DD_READY_MASK 0x00010000L -#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x00020000L -#define CB_DEBUG_BUS_19__DC_READY_MASK 0x00040000L - -// CB_DEBUG_BUS_20 -#define CB_DEBUG_BUS_20__RDREQ_CM_FIFO_EMPTY_MASK 0x00000001L -#define CB_DEBUG_BUS_20__RDREQ_DC_FIFO_EMPTY_MASK 0x00000002L -#define CB_DEBUG_BUS_20__RDREQ_FC_FIFO_EMPTY_MASK 0x00000004L -#define CB_DEBUG_BUS_20__RDREQ_CC_FIFO_EMPTY_MASK 0x00000008L -#define CB_DEBUG_BUS_20__RDREQ_RMI_FIFO_EMPTY_MASK 0x00000010L -#define CB_DEBUG_BUS_20__RDREQ_CREDITS_USED_MASK 0x00000fe0L -#define CB_DEBUG_BUS_20__WRREQ_CM_FIFO_EMPTY_MASK 0x00001000L -#define CB_DEBUG_BUS_20__WRREQ_DC_FIFO_EMPTY_MASK 0x00002000L -#define CB_DEBUG_BUS_20__WRREQ_FC_FIFO_EMPTY_MASK 0x00004000L -#define CB_DEBUG_BUS_20__WRREQ_CC_FIFO_EMPTY_MASK 0x00008000L -#define CB_DEBUG_BUS_20__WRREQ_RMI_FIFO_EMPTY_MASK 0x00010000L -#define CB_DEBUG_BUS_20__WRREQ_CREDITS_USED_MASK 0x00fe0000L - -// CB_DEBUG_BUS_21 -#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x00000001L -#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x00000002L -#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x00000004L -#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x00000008L -#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x00000010L -#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x00000020L -#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x00000040L -#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x00000080L - -// CB_DEBUG_BUS_22 -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0x00000fffL -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0x00fff000L - -// CB_BLEND_RED -#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL - -// CB_BLEND_GREEN -#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL - -// CB_BLEND_BLUE -#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL - -// CB_BLEND_ALPHA -#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL - -// CB_DCC_CONTROL -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007cL - -// CB_COLOR_CONTROL -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L -#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L -#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L - -// CB_BLEND0_CONTROL -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_BLEND1_CONTROL -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_BLEND2_CONTROL -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_BLEND3_CONTROL -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_BLEND4_CONTROL -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_BLEND5_CONTROL -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_BLEND6_CONTROL -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_BLEND7_CONTROL -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L - -// CB_MRT0_EPITCH -#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_MRT1_EPITCH -#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_MRT2_EPITCH -#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_MRT3_EPITCH -#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_MRT4_EPITCH -#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_MRT5_EPITCH -#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_MRT6_EPITCH -#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_MRT7_EPITCH -#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000ffffL - -// CB_COLOR0_BASE -#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR1_BASE -#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR2_BASE -#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR3_BASE -#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR4_BASE -#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR5_BASE -#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR6_BASE -#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR7_BASE -#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR0_BASE_EXT -#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR1_BASE_EXT -#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR2_BASE_EXT -#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR3_BASE_EXT -#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR4_BASE_EXT -#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR5_BASE_EXT -#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR6_BASE_EXT -#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR7_BASE_EXT -#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR0_ATTRIB2 -#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR1_ATTRIB2 -#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR2_ATTRIB2 -#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR3_ATTRIB2 -#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR4_ATTRIB2 -#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR5_ATTRIB2 -#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR6_ATTRIB2 -#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR7_ATTRIB2 -#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003fffL -#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0fffc000L -#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xf0000000L - -// CB_COLOR0_VIEW -#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR1_VIEW -#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR2_VIEW -#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR3_VIEW -#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR4_VIEW -#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR5_VIEW -#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR6_VIEW -#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR7_VIEW -#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL -#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0f000000L - -// CB_COLOR0_INFO -#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR1_INFO -#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR2_INFO -#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR3_INFO -#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR4_INFO -#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR5_INFO -#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR6_INFO -#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR7_INFO -#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL -#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L - -// CB_COLOR0_ATTRIB -#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR1_ATTRIB -#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR2_ATTRIB -#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR3_ATTRIB -#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR4_ATTRIB -#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR5_ATTRIB -#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR6_ATTRIB -#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR7_ATTRIB -#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007ffL -#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007c0000L -#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0f800000L -#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L - -// CB_COLOR0_DCC_CONTROL -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR1_DCC_CONTROL -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR2_DCC_CONTROL -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR3_DCC_CONTROL -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR4_DCC_CONTROL -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR5_DCC_CONTROL -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR6_DCC_CONTROL -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR7_DCC_CONTROL -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000cL -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003c00L -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003c000L - -// CB_COLOR0_CMASK -#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR1_CMASK -#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR2_CMASK -#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR3_CMASK -#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR4_CMASK -#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR5_CMASK -#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR6_CMASK -#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR7_CMASK -#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR0_CMASK_BASE_EXT -#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR1_CMASK_BASE_EXT -#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR2_CMASK_BASE_EXT -#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR3_CMASK_BASE_EXT -#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR4_CMASK_BASE_EXT -#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR5_CMASK_BASE_EXT -#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR6_CMASK_BASE_EXT -#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR7_CMASK_BASE_EXT -#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR0_FMASK -#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR1_FMASK -#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR2_FMASK -#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR3_FMASK -#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR4_FMASK -#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR5_FMASK -#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR6_FMASK -#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR7_FMASK -#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL - -// CB_COLOR0_FMASK_BASE_EXT -#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR1_FMASK_BASE_EXT -#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR2_FMASK_BASE_EXT -#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR3_FMASK_BASE_EXT -#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR4_FMASK_BASE_EXT -#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR5_FMASK_BASE_EXT -#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR6_FMASK_BASE_EXT -#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR7_FMASK_BASE_EXT -#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR0_CLEAR_WORD0 -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR1_CLEAR_WORD0 -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR2_CLEAR_WORD0 -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR3_CLEAR_WORD0 -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR4_CLEAR_WORD0 -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR5_CLEAR_WORD0 -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR6_CLEAR_WORD0 -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR7_CLEAR_WORD0 -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL - -// CB_COLOR0_CLEAR_WORD1 -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR1_CLEAR_WORD1 -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR2_CLEAR_WORD1 -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR3_CLEAR_WORD1 -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR4_CLEAR_WORD1 -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR5_CLEAR_WORD1 -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR6_CLEAR_WORD1 -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR7_CLEAR_WORD1 -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL - -// CB_COLOR0_DCC_BASE -#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR1_DCC_BASE -#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR2_DCC_BASE -#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR3_DCC_BASE -#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR4_DCC_BASE -#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR5_DCC_BASE -#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR6_DCC_BASE -#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR7_DCC_BASE -#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffffL - -// CB_COLOR0_DCC_BASE_EXT -#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR1_DCC_BASE_EXT -#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR2_DCC_BASE_EXT -#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR3_DCC_BASE_EXT -#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR4_DCC_BASE_EXT -#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR5_DCC_BASE_EXT -#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR6_DCC_BASE_EXT -#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_COLOR7_DCC_BASE_EXT -#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000ffL - -// CB_TARGET_MASK -#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL -#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L -#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L -#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L -#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L -#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L -#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L -#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L - -// CB_SHADER_MASK -#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL -#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L -#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L -#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L -#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L -#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L -#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L -#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L - -// CB_PERFCOUNTER0_LO -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CB_PERFCOUNTER1_LO -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CB_PERFCOUNTER2_LO -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CB_PERFCOUNTER3_LO -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CB_PERFCOUNTER0_HI -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CB_PERFCOUNTER1_HI -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CB_PERFCOUNTER2_HI -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CB_PERFCOUNTER3_HI -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CB_PERFCOUNTER_FILTER -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000eL -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003e0L -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000e000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001c0000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00c00000L - -// CB_PERFCOUNTER0_SELECT -#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007fc00L -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// CB_PERFCOUNTER0_SELECT1 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// CB_PERFCOUNTER1_SELECT -#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL -#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// CB_PERFCOUNTER2_SELECT -#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL -#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// CB_PERFCOUNTER3_SELECT -#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL -#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// CB_CGTT_SCLK_CTRL -#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// GC_CAC_CTRL_1 -#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00ffffffL -#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xff000000L - -// GC_CAC_CTRL_2 -#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L -#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L -#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xfffffffcL - -// GC_CAC_CGTT_CLK_CTRL -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L - -// GC_CAC_AGGR_LOWER -#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xffffffffL - -// GC_CAC_AGGR_UPPER -#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xffffffffL - -// GC_CAC_SOFT_CTRL -#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L -#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xfffffffeL - -// GC_DIDT_CTRL0 -#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L -#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001e0L - -// GC_DIDT_CTRL1 -#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000ffffL -#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xffff0000L - -// GC_DIDT_CTRL2 -#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003fffL -#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000c000L -#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L -#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L - -// GC_DIDT_WEIGHT -#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000ffL -#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000ff00L -#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00ff0000L -#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xff000000L - -// GC_DIDT_WEIGHT_1 -#define GC_DIDT_WEIGHT_1__DBR_WEIGHT_MASK 0x000000ffL - -// GC_EDC_CTRL -#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L -#define GC_EDC_CTRL__UNUSED_0_MASK 0xfffffc00L - -// GC_EDC_THRESHOLD -#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xffffffffL - -// GC_EDC_STATUS -#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L -#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03fffff8L - -// GC_EDC_OVERFLOW -#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001fffeL -#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L -#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xfffc0000L - -// GC_EDC_ROLLING_POWER_DELTA -#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xffffffffL - -// GC_DIDT_DROOP_CTRL -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007ffeL -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L -#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L - -// GC_EDC_DROOP_CTRL -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L -#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007ffeL -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000f8000L -#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L -#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L - -// GC_CAC_IND_INDEX -#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xffffffffL - -// GC_CAC_IND_DATA -#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xffffffffL - -// SE_CAC_CGTT_CLK_CTRL -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L - -// SE_CAC_IND_INDEX -#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xffffffffL - -// SE_CAC_IND_DATA -#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xffffffffL - -// GC_CAC_CNTL -#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L -#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001fffeL -#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007e0000L -#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7f800000L -#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L - -// GC_CAC_OVR_SEL -#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xffffffffL - -// GC_CAC_OVR_VAL -#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xffffffffL - -// GC_CAC_WEIGHT_BCI_0 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CB_0 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CB_1 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CBR_0 -#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CBR_1 -#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CP_0 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CP_1 -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_DB_0 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_DB_1 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_DBR_0 -#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_DBR_1 -#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_GDS_0 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_GDS_1 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_IA_0 -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_LDS_0 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_LDS_1 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_PA_0 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_PC_0 -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SC_0 -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SPI_0 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SPI_1 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SPI_2 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SQ_0 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SQ_1 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SQ_2 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SQ_3 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SQ_4 -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SX_0 -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_SXRB_0 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TA_0 -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TCC_0 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TCC_1 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TCC_2 -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TCP_0 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TCP_1 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TCP_2 -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TD_0 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TD_1 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_TD_2 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_VGT_0 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_VGT_1 -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_RMI_0 -#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xffff0000L - -// GC_CAC_WEIGHT_WD_0 -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xffff0000L - -// GC_CAC_WEIGHT_EA_0 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_EA_1 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_EA_2 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ATCL2_0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ATCL2_1 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ATCL2_2 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ROUTER_0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ROUTER_1 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ROUTER_2 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ROUTER_3 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_ROUTER_4 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_VML2_0 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_VML2_1 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_VML2_2 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_0 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_1 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_2 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_3 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_4 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_5 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_6 -#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13_MASK 0xffff0000L - -// GC_CAC_WEIGHT_CU_7 -#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15_MASK 0xffff0000L - -// GC_CAC_ACC_BCI0 -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_BCI1 -#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CB0 -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CB1 -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CB2 -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CB3 -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CBR0 -#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CBR1 -#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CBR2 -#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CBR3 -#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CP0 -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CP1 -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CP2 -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DB0 -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DB1 -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DB2 -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DB3 -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DBR0 -#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DBR1 -#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DBR2 -#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_DBR3 -#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_GDS0 -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_GDS1 -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_GDS2 -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_GDS3 -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_IA0 -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_LDS0 -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_LDS1 -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_LDS2 -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_LDS3 -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_PA0 -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_PA1 -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_PC0 -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SC0 -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SPI0 -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SPI1 -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SPI2 -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SPI3 -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SPI4 -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SPI5 -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ0_LOWER -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ0_UPPER -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ1_LOWER -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ1_UPPER -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ2_LOWER -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ2_UPPER -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ3_LOWER -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ3_UPPER -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ4_LOWER -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ4_UPPER -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ5_LOWER -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ5_UPPER -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ6_LOWER -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ6_UPPER -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ7_LOWER -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ7_UPPER -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SQ8_LOWER -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SQ8_UPPER -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000ffL -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xffffff00L - -// GC_CAC_ACC_SX0 -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SXRB0 -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_SXRB1 -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TA0 -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCC0 -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCC1 -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCC2 -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCC3 -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCC4 -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCP0 -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCP1 -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCP2 -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCP3 -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TCP4 -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TD0 -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TD1 -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TD2 -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TD3 -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TD4 -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_TD5 -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_VGT0 -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_VGT1 -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_VGT2 -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_RMI0 -#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_WD0 -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_EA0 -#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_EA1 -#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_EA2 -#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_EA3 -#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_EA4 -#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_EA5 -#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ATCL20 -#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ATCL21 -#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ATCL22 -#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ATCL23 -#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ATCL24 -#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER0 -#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER1 -#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER2 -#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER3 -#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER4 -#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER5 -#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER6 -#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER7 -#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER8 -#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_ROUTER9 -#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_VML20 -#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_VML21 -#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_VML22 -#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_VML23 -#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_VML24 -#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU0 -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU1 -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU2 -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU3 -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU4 -#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU5 -#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU6 -#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU7 -#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU8 -#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU9 -#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU10 -#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU11 -#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU12 -#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU13 -#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU14 -#define GC_CAC_ACC_CU14__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_CU15 -#define GC_CAC_ACC_CU15__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_OVRD_BCI -#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L -#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000cL - -// GC_CAC_OVRD_CB -#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000fL -#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000f0L - -// GC_CAC_OVRD_CBR -#define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK 0x0000000fL -#define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK 0x000000f0L - -// GC_CAC_OVRD_CP -#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L -#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L - -// GC_CAC_OVRD_DB -#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000fL -#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000f0L - -// GC_CAC_OVRD_DBR -#define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK 0x0000000fL -#define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK 0x000000f0L - -// GC_CAC_OVRD_GDS -#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000fL -#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000f0L - -// GC_CAC_OVRD_IA -#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_LDS -#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000fL -#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000f0L - -// GC_CAC_OVRD_PA -#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L -#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000cL - -// GC_CAC_OVRD_PC -#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_SC -#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_SPI -#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003fL -#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000fc0L - -// GC_CAC_OVRD_CU -#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_SQ -#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001ffL -#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003fe00L - -// GC_CAC_OVRD_SX -#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_SXRB -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_TA -#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_TCC -#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001fL -#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003e0L - -// GC_CAC_OVRD_TCP -#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001fL -#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003e0L - -// GC_CAC_OVRD_TD -#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003fL -#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000fc0L - -// GC_CAC_OVRD_VGT -#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L -#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L - -// GC_CAC_OVRD_RMI -#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_WD -#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L - -// GC_CAC_OVRD_EA -#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003fL -#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000fc0L - -// GC_CAC_OVRD_UTCL2_ATCL2 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001fL -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003e0L - -// GC_CAC_OVRD_UTCL2_ROUTER -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003ffL -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000ffc00L - -// GC_CAC_OVRD_UTCL2_VML2 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001fL -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003e0L - -// GC_CAC_WEIGHT_UTCL2_WALKER_0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_WALKER_1 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xffff0000L - -// GC_CAC_WEIGHT_UTCL2_WALKER_2 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000ffffL -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xffff0000L - -// GC_CAC_ACC_UTCL2_WALKER0 -#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_WALKER1 -#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_WALKER2 -#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_WALKER3 -#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_ACC_UTCL2_WALKER4 -#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xffffffffL - -// GC_CAC_OVRD_UTCL2_WALKER -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001fL -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003e0L - -// SE_CAC_CNTL -#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L -#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001fffeL -#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007e0000L -#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7f800000L -#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L - -// SE_CAC_OVR_SEL -#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xffffffffL - -// SE_CAC_OVR_VAL -#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xffffffffL - -// RLC_GPM_PERF_COUNT_0 -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000fL -#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000f0L -#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000f00L -#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000f000L -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L -#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000c0000L -#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L -#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000L - -// RLC_GPM_PERF_COUNT_1 -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000fL -#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000f0L -#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000f00L -#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000f000L -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L -#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000c0000L -#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L -#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000L - -// RLC_PERFCOUNTER0_LO -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// RLC_PERFCOUNTER1_LO -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// RLC_PERFCOUNTER0_HI -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// RLC_PERFCOUNTER1_HI -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// RLC_PERFMON_CLK_CNTL -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L - -// RLC_PERFMON_CNTL -#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L - -// RLC_PERFCOUNTER0_SELECT -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL - -// RLC_PERFCOUNTER1_SELECT -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL - -// RLC_GPU_IOV_PERF_CNT_CNTL -#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xfffffff8L - -// RLC_GPU_IOV_PERF_CNT_WR_ADDR -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000fL -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xffffffc0L - -// RLC_GPU_IOV_PERF_CNT_WR_DATA -#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000fL - -// RLC_GPU_IOV_PERF_CNT_RD_ADDR -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000fL -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xffffffc0L - -// RLC_GPU_IOV_PERF_CNT_RD_DATA -#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000fL - -// RLC_SPM_PERFMON_CNTL -#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000fffL -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L -#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000c000L -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000L - -// RLC_SPM_PERFMON_RING_BASE_LO -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffffL - -// RLC_SPM_PERFMON_RING_BASE_HI -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000ffffL -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000L - -// RLC_SPM_PERFMON_RING_SIZE -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffffL - -// RLC_SPM_PERFMON_SEGMENT_SIZE -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000ffL -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000f800L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001f0000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03e00000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L - -// RLC_SPM_SE_MUXSEL_ADDR -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffffL - -// RLC_SPM_SE_MUXSEL_DATA -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffffL - -// RLC_SPM_CPG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_CPC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_CPF_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_CB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_DB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_PA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_GDS_PERFMON_SAMPLE_DELAY -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_IA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_SC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_TCC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_TCA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_TCP_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_TA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_TD_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_VGT_PERFMON_SAMPLE_DELAY -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_SPI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_SQG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_SX_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_GLOBAL_MUXSEL_ADDR -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffffL - -// RLC_SPM_GLOBAL_MUXSEL_DATA -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffffL - -// RLC_SPM_RING_RDPTR -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffffL - -// RLC_SPM_SEGMENT_THRESHOLD -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffffL - -// RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_SPM_RMI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000ffL -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00L - -// RLC_CNTL -#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L -#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L -#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L -#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L -#define RLC_CNTL__RESERVED_MASK 0xfffffff0L - -// RLC_DEBUG_SELECT -#define RLC_DEBUG_SELECT__SELECT_MASK 0x000000ffL -#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00L - -// RLC_DEBUG -#define RLC_DEBUG__DATA_MASK 0xffffffffL - -// RLC_STAT -#define RLC_STAT__RLC_BUSY_MASK 0x00000001L -#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L -#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L -#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L -#define RLC_STAT__MC_BUSY_MASK 0x00000010L -#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L -#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L -#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L -#define RLC_STAT__RESERVED_MASK 0xffffff00L - -// RLC_INT_STAT -#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000ffL -#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L -#define RLC_INT_STAT__RESERVED_MASK 0xfffffe00L - -// RLC_SAFE_MODE -#define RLC_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001eL -#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000e0L -#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000f00L -#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000L - -// RLC_MEM_SLP_CNTL -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L -#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007cL -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000ff00L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00ff0000L -#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L - -// SMU_RLC_RESPONSE -#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffffL - -// RLC_RLCV_SAFE_MODE -#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001eL -#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000e0L -#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000f00L -#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000L - -// RLC_SMU_SAFE_MODE -#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001eL -#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000e0L -#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000f00L -#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000L - -// RLC_RLCV_COMMAND -#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000fL -#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0L - -// RLC_REFCLOCK_TIMESTAMP_LSB -#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xffffffffL - -// RLC_REFCLOCK_TIMESTAMP_MSB -#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xffffffffL - -// RLC_GPM_TIMER_INT_0 -#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xffffffffL - -// RLC_GPM_TIMER_INT_1 -#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xffffffffL - -// RLC_GPM_TIMER_INT_2 -#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xffffffffL - -// RLC_GPM_TIMER_INT_3 -#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xffffffffL - -// RLC_GPM_TIMER_CTRL -#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L -#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L -#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L -#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L -#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xfffffff0L - -// RLC_GPM_TIMER_STAT -#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L -#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L -#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L -#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L -#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xfffffff0L - -// RLC_LB_CNTL -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L -#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L -#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000ff0L -#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000L - -// RLC_LB_CNTR_MAX -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffffL - -// RLC_LB_CNTR_INIT -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffffL - -// RLC_LOAD_BALANCE_CNTR -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffffL - -// RLC_JUMP_TABLE_RESTORE -#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffffL - -// RLC_PG_DELAY_2 -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000ffL -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000ff00L -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000L - -// RLC_GPM_DEBUG_INST_HIST -#define RLC_GPM_DEBUG_INST_HIST__DEBUG_ENABLE_MASK 0x00000001L -#define RLC_GPM_DEBUG_INST_HIST__INSTRUCTION_HISTORY_SAVE_INTERVAL_MASK 0x0000000eL -#define RLC_GPM_DEBUG_INST_HIST__RESERVED_MASK 0xfffffff0L - -// RLC_GPM_DEBUG_SELECT -#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0x000000ffL -#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x00000300L -#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00L - -// RLC_GPM_DEBUG -#define RLC_GPM_DEBUG__DATA_MASK 0xffffffffL - -// RLC_GPM_DEBUG_INST_A -#define RLC_GPM_DEBUG_INST_A__INST_A_MASK 0xffffffffL - -// RLC_GPM_DEBUG_INST_B -#define RLC_GPM_DEBUG_INST_B__INST_B_MASK 0xffffffffL - -// RLC_GPM_DEBUG_INST_ADDR -#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A_MASK 0x0000ffffL -#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B_MASK 0xffff0000L - -// RLC_SEMAPHORE_0 -#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001fL -#define RLC_SEMAPHORE_0__RESERVED_MASK 0xffffffe0L - -// RLC_SEMAPHORE_1 -#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001fL -#define RLC_SEMAPHORE_1__RESERVED_MASK 0xffffffe0L - -// RLC_RLCV_SPARE_INT -#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L -#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xfffffffeL - -// RLC_GPU_CLOCK_COUNT_LSB -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffffL - -// RLC_GPU_CLOCK_COUNT_MSB -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffffL - -// RLC_CAPTURE_GPU_CLOCK_COUNT -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffeL - -// RLC_UCODE_CNTL -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffffL - -// RLC_GPM_STAT -#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L -#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L -#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L -#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L -#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L -#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L -#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L -#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L -#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L -#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L -#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L -#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000L - -// RLC_GPU_CLOCK_32_RES_SEL -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003fL -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0L - -// RLC_GPU_CLOCK_32 -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffffL - -// RLC_PG_CNTL -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L -#define RLC_PG_CNTL__RESERVED_MASK 0x00003fe0L -#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L -#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L -#define RLC_PG_CNTL__RESERVED1_MASK 0x00f00000L - -// RLC_GPM_THREAD_PRIORITY -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000ffL -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000ff00L -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00ff0000L -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000L - -// RLC_GPM_THREAD_ENABLE -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L -#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0L - -// RLC_CGTT_MGCG_OVERRIDE -#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L -#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L -#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L -#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xffffff00L - -// RLC_CGCG_CGLS_CTRL -#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L -#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000fcL -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07ffff00L -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L - -// RLC_CGCG_RAMP_CTRL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000fL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000f0L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000f00L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000f000L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0fff0000L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000L - -// RLC_CGCG_CGLS_CTRL_3D -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000fcL -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07ffff00L -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L -#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L -#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L - -// RLC_CGCG_RAMP_CTRL_3D -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000fL -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000f0L -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000f00L -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000f000L -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0fff0000L -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xf0000000L - -// RLC_DYN_PG_STATUS -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL - -// RLC_DYN_PG_REQUEST -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffffL - -// RLC_PG_DELAY -#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000ffL -#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000ff00L -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00ff0000L -#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000L - -// RLC_CU_STATUS -#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffffL - -// RLC_LB_INIT_CU_MASK -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffffL - -// RLC_LB_ALWAYS_ACTIVE_CU_MASK -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffffL - -// RLC_LB_PARAMS -#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L -#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000feL -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000ff00L -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000L - -// RLC_THREAD1_DELAY -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000ffL -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000ff00L -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00ff0000L -#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000L - -// RLC_LB_THR_CONFIG_1 -#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xffffffffL - -// RLC_LB_THR_CONFIG_2 -#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xffffffffL - -// RLC_LB_THR_CONFIG_3 -#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xffffffffL - -// RLC_LB_THR_CONFIG_4 -#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xffffffffL - -// RLC_LB_DEBUG_1 -#define RLC_LB_DEBUG_1__DATA_MASK 0xffffffffL - -// RLC_PG_ALWAYS_ON_CU_MASK -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffffL - -// RLC_MAX_PG_CU -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000ffL -#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00L - -// RLC_AUTO_PG_CTRL -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007fff8L -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000L - -// RLC_SMU_GRBM_REG_SAVE_CTRL -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffeL - -// RLC_SERDES_RD_MASTER_INDEX -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000fL -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001c0L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000e00L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001e000L -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L -#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfff80000L - -// RLC_SERDES_RD_DATA_0 -#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffffL - -// RLC_SERDES_RD_DATA_1 -#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffffL - -// RLC_SERDES_RD_DATA_2 -#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffffL - -// RLC_SERDES_WR_CU_MASTER_MASK -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffffL - -// RLC_SERDES_WR_NONCU_MASTER_MASK -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000ffffL -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xfc000000L - -// RLC_SERDES_WR_NONCU_MASTER_MASK_1 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000ffffL -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xfe000000L - -// RLC_SERDES_NONCU_MASTER_BUSY_1 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000ffffL -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xfe000000L - -// RLC_SERDES_WR_CTRL -#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000ffL -#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L -#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L -#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L -#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L -#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L -#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L -#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03ff0000L -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L -#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000L - -// RLC_SERDES_WR_DATA -#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffffL - -// RLC_SERDES_CU_MASTER_BUSY -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffffL - -// RLC_SERDES_NONCU_MASTER_BUSY -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000ffffL -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L -#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xfc000000L - -// RLC_GPM_GENERAL_0 -#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_1 -#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_2 -#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_3 -#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_4 -#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_5 -#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_6 -#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_7 -#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffffL - -// RLC_GPM_SCRATCH_ADDR -#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001ffL -#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00L - -// RLC_GPM_SCRATCH_DATA -#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffffL - -// RLC_STATIC_PG_STATUS -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL - -// RLC_GPR_REG1 -#define RLC_GPR_REG1__DATA_MASK 0xffffffffL - -// RLC_GPR_REG2 -#define RLC_GPR_REG2__DATA_MASK 0xffffffffL - -// RLC_MGCG_CTRL -#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L -#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L -#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L -#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L -#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007f80L -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L -#define RLC_MGCG_CTRL__SPARE_MASK 0xfffe0000L - -// RLC_GPM_THREAD_RESET -#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L -#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L -#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L -#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L -#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0L - -// RLC_GPM_CP_DMA_COMPLETE_T0 -#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L -#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xfffffffeL - -// RLC_GPM_CP_DMA_COMPLETE_T1 -#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L -#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xfffffffeL - -// RLC_FIREWALL_VIOLATION -#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xffffffffL - -// RLC_SPM_MC_CNTL -#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000fL -#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L -#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L -#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L -#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xfffffc00L - -// RLC_SPM_INT_CNTL -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L -#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffeL - -// RLC_SPM_INT_STATUS -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L -#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffeL - -// RLC_SPM_DEBUG_SELECT -#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0x000000ffL -#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x00007f00L -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x00008000L -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000L - -// RLC_SPM_DEBUG -#define RLC_SPM_DEBUG__DATA_MASK 0xffffffffL - -// RLC_SMU_MESSAGE -#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffffL - -// RLC_GPM_LOG_SIZE -#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffffL - -// RLC_GPM_LOG_CONT -#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffffL - -// RLC_PG_DELAY_3 -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000ffL -#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00L - -// RLC_GPM_INT_DISABLE_TH0 -#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffffL - -// RLC_GPM_INT_DISABLE_TH1 -#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffffL - -// RLC_GPM_INT_FORCE_TH0 -#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffffL - -// RLC_GPM_INT_FORCE_TH1 -#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffffL - -// RLC_SRM_CNTL -#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L -#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L -#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffcL - -// RLC_SRM_DEBUG_SELECT -#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0x000000ffL -#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00L - -// RLC_SRM_DEBUG -#define RLC_SRM_DEBUG__DATA_MASK 0xffffffffL - -// RLC_SRM_ARAM_ADDR -#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000fffL -#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffff000L - -// RLC_SRM_ARAM_DATA -#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffffL - -// RLC_SRM_DRAM_ADDR -#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000fffL -#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffff000L - -// RLC_SRM_DRAM_DATA -#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffffL - -// RLC_SRM_GPM_COMMAND -#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001cL -#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001ffe0L -#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000L -#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L - -// RLC_SRM_GPM_COMMAND_STATUS -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffcL - -// RLC_SRM_RLCV_COMMAND -#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L -#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000eL -#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000fff0L -#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0fff0000L -#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L - -// RLC_SRM_RLCV_COMMAND_STATUS -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffcL - -// RLC_SRM_INDEX_CNTL_ADDR_0 -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_ADDR_1 -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_ADDR_2 -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_ADDR_3 -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_ADDR_4 -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_ADDR_5 -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_ADDR_6 -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_ADDR_7 -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000ffffL -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000L - -// RLC_SRM_INDEX_CNTL_DATA_0 -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffffL - -// RLC_SRM_INDEX_CNTL_DATA_1 -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffffL - -// RLC_SRM_INDEX_CNTL_DATA_2 -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffffL - -// RLC_SRM_INDEX_CNTL_DATA_3 -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffffL - -// RLC_SRM_INDEX_CNTL_DATA_4 -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffffL - -// RLC_SRM_INDEX_CNTL_DATA_5 -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffffL - -// RLC_SRM_INDEX_CNTL_DATA_6 -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffffL - -// RLC_SRM_INDEX_CNTL_DATA_7 -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffffL - -// RLC_SRM_STAT -#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L -#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L -#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffcL - -// RLC_SRM_GPM_ABORT -#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L -#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffeL - -// RLC_CSIB_ADDR_LO -#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffffL - -// RLC_CSIB_ADDR_HI -#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000ffffL - -// RLC_CSIB_LENGTH -#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffffL - -// RLC_SMU_COMMAND -#define RLC_SMU_COMMAND__CMD_MASK 0xffffffffL - -// RLC_CP_SCHEDULERS -#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000ffL -#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000ff00L -#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00ff0000L -#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000L - -// RLC_SMU_ARGUMENT_1 -#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xffffffffL - -// RLC_SMU_ARGUMENT_2 -#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xffffffffL - -// RLC_GPM_GENERAL_8 -#define RLC_GPM_GENERAL_8__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_9 -#define RLC_GPM_GENERAL_9__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_10 -#define RLC_GPM_GENERAL_10__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_11 -#define RLC_GPM_GENERAL_11__DATA_MASK 0xffffffffL - -// RLC_GPM_GENERAL_12 -#define RLC_GPM_GENERAL_12__DATA_MASK 0xffffffffL - -// RLC_UTCL2_CNTL -#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L -#define RLC_UTCL2_CNTL__RESERVED_MASK 0xfffffffeL - -// RLC_GPM_UTCL1_CNTL_0 -#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xc0000000L - -// RLC_GPM_UTCL1_CNTL_1 -#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xc0000000L - -// RLC_GPM_UTCL1_CNTL_2 -#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xc0000000L - -// RLC_SPM_UTCL1_CNTL -#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xc0000000L - -// RLC_PREWALKER_UTCL1_CNTL -#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xc0000000L - -// RLC_PREWALKER_UTCL1_TRIG -#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L -#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001eL -#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L -#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L -#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L -#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L -#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7ffffe00L -#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L - -// RLC_PREWALKER_UTCL1_ADDR_LSB -#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xffffffffL - -// RLC_PREWALKER_UTCL1_ADDR_MSB -#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000ffffL - -// RLC_PREWALKER_UTCL1_SIZE_LSB -#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xffffffffL - -// RLC_PREWALKER_UTCL1_SIZE_MSB -#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L - -// RLC_DSM_TRIG -#define RLC_DSM_TRIG__S_MASK 0x00000001L - -// RLC_UTCL1_STATUS_2 -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L -#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xfffffc00L - -// RLC_SPM_UTCL1_ERROR_1 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003cL -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003c0L - -// RLC_SPM_UTCL1_ERROR_2 -#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xffffffffL - -// RLC_GPM_UTCL1_TH0_ERROR_1 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003cL -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003c0L - -// RLC_GPM_UTCL1_TH0_ERROR_2 -#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xffffffffL - -// RLC_GPM_UTCL1_TH1_ERROR_1 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003cL -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003c0L - -// RLC_GPM_UTCL1_TH1_ERROR_2 -#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xffffffffL - -// RLC_GPM_UTCL1_TH2_ERROR_1 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003cL -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003c0L - -// RLC_GPM_UTCL1_TH2_ERROR_2 -#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xffffffffL - -// RLC_CP_EOF_INT -#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L -#define RLC_CP_EOF_INT__RESERVED_MASK 0xfffffffeL - -// RLC_CP_EOF_INT_CNT -#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xffffffffL - -// RLC_R2I_CNTL_0 -#define RLC_R2I_CNTL_0__Data_MASK 0xffffffffL - -// RLC_R2I_CNTL_1 -#define RLC_R2I_CNTL_1__Data_MASK 0xffffffffL - -// RLC_R2I_CNTL_2 -#define RLC_R2I_CNTL_2__Data_MASK 0xffffffffL - -// RLC_R2I_CNTL_3 -#define RLC_R2I_CNTL_3__Data_MASK 0xffffffffL - -// RLC_SPARE_INT -#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L -#define RLC_SPARE_INT__RESERVED_MASK 0xfffffffeL - -// RLC_UTCL1_STATUS -#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000f8L -#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003f00L -#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000c000L -#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003f0000L -#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00c00000L -#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3f000000L -#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xc0000000L - -// RLC_LBPW_CU_STAT -#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000ffffL -#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xffff0000L - -// RLC_DS_CNTL -#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L -#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L -#define RLC_DS_CNTL__RESRVED_MASK 0x0000fffcL -#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L -#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L -#define RLC_DS_CNTL__RESRVED_1_MASK 0xfffc0000L - -// CGTT_RLC_CLK_CTRL -#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L - -// RLC_GFX_RM_CNTL -#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L -#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xfffffffeL - -// RLC_CLK_CNTL -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L -#define RLC_CLK_CNTL__RESERVED_MASK 0xfffffffcL - -// RLC_GPM_UCODE_ADDR -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003fffL -#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xffffc000L - -// RLC_GPM_UCODE_DATA -#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// RLC_GC_FUSESTRAP_RELOAD -#define RLC_GC_FUSESTRAP_RELOAD__RELOAD_MASK 0x00000001L -#define RLC_GC_FUSESTRAP_RELOAD__RESERVED_MASK 0xfffffffeL - -// RLC_GC_FUSESTRAP_GC_WRITE_DISABLE -#define RLC_GC_FUSESTRAP_GC_WRITE_DISABLE__GLOBAL_WRITE_DIS_MASK 0x00000001L -#define RLC_GC_FUSESTRAP_GC_WRITE_DISABLE__RESERVED_MASK 0xfffffffeL - -// RLC_GC_FUSESTRAP_CC_WRITE_DISABLE -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__CU_WRITE_DIS_MASK 0x00000001L -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__TCC_WRITE_DIS_MASK 0x00000002L -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__RB_WRITE_DIS_MASK 0x00000004L -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__PRIM_WRITE_DIS_MASK 0x00000008L -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__RATE_WRITE_DIS_MASK 0x00000010L -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__EDC_WRITE_DIS_MASK 0x00000020L -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__RESERVED_MASK 0xffffffc0L - -// RLC_GC_FUSESTRAP_DEBE_0 -#define RLC_GC_FUSESTRAP_DEBE_0__DEBE_31_0_MASK 0xffffffffL - -// RLC_GC_FUSESTRAP_DEBE_1 -#define RLC_GC_FUSESTRAP_DEBE_1__DEBE_63_32_MASK 0xffffffffL - -// RLC_GC_FUSESTRAP_DEBE_2 -#define RLC_GC_FUSESTRAP_DEBE_2__DEBE_95_64_MASK 0xffffffffL - -// RLC_GC_FUSESTRAP_DEBE_3 -#define RLC_GC_FUSESTRAP_DEBE_3__DEBE_127_96_MASK 0xffffffffL - -// RLC_GC_FUSESTRAP_DPFP_RATE -#define RLC_GC_FUSESTRAP_DPFP_RATE__DPFP_RATE_MASK 0x00000003L -#define RLC_GC_FUSESTRAP_DPFP_RATE__RESERVED_MASK 0xfffffffcL - -// RLC_GC_FUSESTRAP_DISABLE_EDC -#define RLC_GC_FUSESTRAP_DISABLE_EDC__DISABLE_EDC_MASK 0x00000001L -#define RLC_GC_FUSESTRAP_DISABLE_EDC__RESERVED_MASK 0xfffffffeL - -// RLC_HYP_SEMAPHORE_2 -#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001fL -#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xffffffe0L - -// RLC_HYP_SEMAPHORE_3 -#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001fL -#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xffffffe0L - -// RLC_GPU_IOV_VF_ENABLE -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000fffeL -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000L - -// RLC_GPU_IOV_CFG_REG1 -#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000fL -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L -#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000c0L -#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000ff00L -#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00ff0000L -#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000L - -// RLC_GPU_IOV_CFG_REG2 -#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000fL -#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0L - -// RLC_GPU_IOV_SCH_BLOCK -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000fL -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000f0L -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007f00L -#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7fff0000L - -// RLC_GPU_IOV_CFG_REG6 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007fL -#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L -#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L -#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00L - -// RLC_GPU_IOV_CFG_REG8 -#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffffL - -// RLC_GPU_IOV_UCODE_ADDR -#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL -#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000L - -// RLC_GPU_IOV_UCODE_DATA -#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// RLC_GPU_IOV_SCRATCH_ADDR -#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001ffL -#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00L - -// RLC_GPU_IOV_SCRATCH_DATA -#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffffL - -// RLC_GPU_IOV_F32_CNTL -#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffeL - -// RLC_GPU_IOV_F32_RESET -#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L -#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffeL - -// RLC_GPU_IOV_SDMA0_STATUS -#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000feL -#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000e00L -#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000L - -// RLC_GPU_IOV_SDMA1_STATUS -#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000feL -#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000e00L -#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000L - -// RLC_GPU_IOV_SMU_RESPONSE -#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffffL - -// RLC_GPU_IOV_VIRT_RESET_REQ -#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000ffffL -#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000L -#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L - -// RLC_GPU_IOV_SDMA0_BUSY_STATUS -#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffffL - -// RLC_GPU_IOV_SDMA1_BUSY_STATUS -#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffffL - -// RLC_GPU_IOV_VM_BUSY_STATUS -#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffffL - -// RLC_GPU_IOV_SCH_0 -#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xffffffffL - -// RLC_GPU_IOV_SCH_1 -#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffffL - -// RLC_GPU_IOV_SCH_2 -#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffffL - -// RLC_GPU_IOV_SCH_3 -#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xffffffffL - -// RLC_GPU_IOV_RLC_RESPONSE -#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffffL - -// RLC_GPU_IOV_ACTIVE_FCN_ID -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000fL -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0L -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L - -// RLC_RLCV_TIMER_INT_0 -#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xffffffffL - -// RLC_RLCV_TIMER_CTRL -#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L -#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xfffffffeL - -// RLC_RLCV_TIMER_STAT -#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L -#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xfffffffeL - -// RLC_GPU_IOV_INT_DISABLE -#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffffL - -// RLC_GPU_IOV_INT_FORCE -#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffffL - -// RLC_GPU_IOV_VF_DOORBELL_STATUS -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000ffffL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7fff0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L - -// RLC_GPU_IOV_VF_DOORBELL_STATUS_SET -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000ffffL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7fff0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L - -// RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000ffffL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7fff0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L - -// RLC_GPU_IOV_VF_MASK -#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000ffffL -#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xffff0000L - -// RLC_REG_PRIV_LEVEL_A -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL0_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL1_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL2_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL3_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL4_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL5_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL6_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL7_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL8_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL9_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL10_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL11_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL12_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL13_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL14_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL15_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_B -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL16_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL17_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL18_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL19_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL20_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL21_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL22_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL23_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL24_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL25_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL26_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL27_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL28_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL29_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL30_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL31_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_C -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL32_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL33_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL34_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL35_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL36_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL37_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL38_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL39_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL40_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL41_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL42_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL43_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL44_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL45_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL46_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL47_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_D -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL48_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL49_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL50_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL51_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL52_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL53_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL54_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL55_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL56_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL57_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL58_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL59_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL60_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL61_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL62_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL63_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_E -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL64_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL65_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL66_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL67_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL68_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL69_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL70_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL71_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL72_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL73_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL74_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL75_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL76_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL77_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL78_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL79_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_F -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL80_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL81_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL82_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL83_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL84_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL85_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL86_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL87_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL88_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL89_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL90_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL91_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL92_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL93_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL94_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL95_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_G -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL96_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL97_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL98_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL99_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL100_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL101_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL102_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL103_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL104_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL105_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL106_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL107_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL108_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL109_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL110_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL111_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_H -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL112_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL113_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL114_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL115_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL116_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL117_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL118_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL119_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL120_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL121_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL122_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL123_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL124_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL125_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL126_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL127_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_I -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL128_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL129_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL130_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL131_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL132_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL133_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL134_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL135_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL136_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL137_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL138_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL139_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL140_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL141_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL142_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL143_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_J -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL144_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL145_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL146_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL147_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL148_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL149_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL150_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL151_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL152_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL153_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL154_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL155_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL156_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL157_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL158_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL159_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_K -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL160_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL161_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL162_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL163_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL164_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL165_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL166_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL167_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL168_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL169_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL170_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL171_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL172_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL173_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL174_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL175_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL176_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL177_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL178_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL179_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL180_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL181_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL182_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL183_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL184_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL185_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL186_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL187_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL188_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL189_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL190_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL191_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_M -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL192_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL193_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL194_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL195_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL196_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL197_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL198_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL199_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL200_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL201_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL202_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL203_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL204_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL205_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL206_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL207_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_N -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL208_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL209_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL210_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL211_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL212_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL213_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL214_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL215_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL216_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL217_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL218_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL219_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL220_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL221_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL222_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL223_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_O -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL224_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL225_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL226_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL227_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL228_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL229_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL230_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL231_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL232_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL233_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL234_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL235_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL236_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL237_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL238_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL239_MASK 0xc0000000L - -// RLC_REG_PRIV_LEVEL_P -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL240_MASK 0x00000003L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL241_MASK 0x0000000cL -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL242_MASK 0x00000030L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL243_MASK 0x000000c0L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL244_MASK 0x00000300L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL245_MASK 0x00000c00L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL246_MASK 0x00003000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL247_MASK 0x0000c000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL248_MASK 0x00030000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL249_MASK 0x000c0000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL250_MASK 0x00300000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL251_MASK 0x00c00000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL252_MASK 0x03000000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL253_MASK 0x0c000000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL254_MASK 0x30000000L -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL255_MASK 0xc0000000L - -// RLC_REG_SEC_INT_STATUS -#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_MASK 0x0000ffffL -#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_OVERFLOW_MASK 0x00010000L -#define RLC_REG_SEC_INT_STATUS__RESERVED_MASK 0xfffe0000L - -// RLC_FWL_FIRST_VIOL_ADDR -#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x0003ffffL -#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x00040000L -#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK 0xfff80000L - -// SPI_PS_MAX_WAVE_ID -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL -#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03ff0000L - -// SPI_START_PHASE -#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L -#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000cL -#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L - -// SPI_GFX_CNTL -#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L - -// SPI_DEBUG_CNTL -#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x00000001L -#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0x0000000eL -#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x000003f0L -#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000fc00L -#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x00080000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x00200000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x00400000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x00800000L -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x01000000L -#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0x0e000000L -#define SPI_DEBUG_CNTL__BCI_PIPE_PER_STAGE_CG_OVERRIDE_MASK 0x40000000L -#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L - -// SPI_DEBUG_READ -#define SPI_DEBUG_READ__DATA_MASK 0xffffffffL - -// SPI_DSM_CNTL -#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8L - -// SPI_DSM_CNTL2 -#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003f0L -#define SPI_DSM_CNTL2__UNUSED_MASK 0xfffffc00L - -// SPI_EDC_CNT -#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L - -// SPI_DEBUG_BUSY -#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L -#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L -#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L -#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L -#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L -#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L -#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L -#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L -#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L -#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L -#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L -#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L -#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L -#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L -#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L -#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L -#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00010000L -#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00020000L -#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00040000L -#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00080000L -#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L -#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00200000L -#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00400000L -#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00800000L - -// SPI_CONFIG_PS_CU_EN -#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L -#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000fffeL -#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xffff0000L - -// SPI_WF_LIFETIME_CNTL -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000fL -#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L - -// SPI_WF_LIFETIME_LIMIT_0 -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_1 -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_2 -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_3 -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_4 -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_5 -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_6 -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_7 -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_8 -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_LIMIT_9 -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_0 -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_1 -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_2 -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_3 -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_4 -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_5 -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_6 -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_7 -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_8 -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_9 -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_10 -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_11 -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_12 -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_13 -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_14 -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_15 -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_16 -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_17 -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_18 -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_19 -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_STATUS_20 -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L - -// SPI_WF_LIFETIME_DEBUG -#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffffL -#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L - -// SPI_SLAVE_DEBUG_BUSY -#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L -#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L -#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L -#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L -#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x00000010L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000020L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000040L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x00000080L -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x00000100L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000200L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000400L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x00000800L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x00001000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x00002000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x00004000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x00008000L -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x00010000L -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x00020000L -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x00040000L -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x00080000L -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x00100000L -#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00200000L -#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x00400000L - -// SPI_LB_CTR_CTRL -#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L -#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L -#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L -#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L - -// SPI_LB_CU_MASK -#define SPI_LB_CU_MASK__CU_MASK_MASK 0x0000ffffL - -// SPI_LB_DATA_REG -#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffffL - -// SPI_PG_ENABLE_STATIC_CU_MASK -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0x0000ffffL - -// SPI_GDS_CREDITS -#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000ffL -#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000ff00L -#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000L - -// SPI_SX_EXPORT_BUFFER_SIZES -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000ffffL -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000L - -// SPI_SX_SCOREBOARD_BUFFER_SIZES -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000ffffL -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000L - -// SPI_CSQ_WF_ACTIVE_STATUS -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffffL - -// SPI_CSQ_WF_ACTIVE_COUNT_0 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07ff0000L - -// SPI_CSQ_WF_ACTIVE_COUNT_1 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07ff0000L - -// SPI_CSQ_WF_ACTIVE_COUNT_2 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07ff0000L - -// SPI_CSQ_WF_ACTIVE_COUNT_3 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07ff0000L - -// SPI_CSQ_WF_ACTIVE_COUNT_4 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07ff0000L - -// SPI_CSQ_WF_ACTIVE_COUNT_5 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07ff0000L - -// SPI_CSQ_WF_ACTIVE_COUNT_6 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07ff0000L - -// SPI_CSQ_WF_ACTIVE_COUNT_7 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007ffL -#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07ff0000L - -// SPI_LB_DATA_WAVES -#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000ffffL -#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xffff0000L - -// SPI_LB_DATA_PERCU_WAVE_HSGS -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000ffffL -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xffff0000L - -// SPI_LB_DATA_PERCU_WAVE_VSPS -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000ffffL -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xffff0000L - -// SPI_LB_DATA_PERCU_WAVE_CS -#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0x0000ffffL - -// SPIS_DEBUG_READ -#define SPIS_DEBUG_READ__DATA_MASK 0xffffffffL - -// BCI_DEBUG_READ -#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL - -// SPI_P0_TRAP_SCREEN_PSBA_LO -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffffL - -// SPI_P0_TRAP_SCREEN_PSBA_HI -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0x000000ffL - -// SPI_P0_TRAP_SCREEN_PSMA_LO -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffffL - -// SPI_P0_TRAP_SCREEN_PSMA_HI -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0x000000ffL - -// SPI_P0_TRAP_SCREEN_GPR_MIN -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x0000003fL -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x000003c0L - -// SPI_P1_TRAP_SCREEN_PSBA_LO -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffffL - -// SPI_P1_TRAP_SCREEN_PSBA_HI -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0x000000ffL - -// SPI_P1_TRAP_SCREEN_PSMA_LO -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffffL - -// SPI_P1_TRAP_SCREEN_PSMA_HI -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0x000000ffL - -// SPI_P1_TRAP_SCREEN_GPR_MIN -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x0000003fL -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x000003c0L - -// SPI_SHADER_PGM_LO_PS -#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_HI_PS -#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000ffL - -// SPI_SHADER_PGM_RSRC1_PS -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L -#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L - -// SPI_SHADER_PGM_RSRC2_PS -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000ff00L -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01ff0000L -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L - -// SPI_SHADER_PGM_RSRC3_PS -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003f0000L -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3c000000L - -// SPI_SHADER_USER_DATA_PS_0 -#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_1 -#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_2 -#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_3 -#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_4 -#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_5 -#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_6 -#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_7 -#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_8 -#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_9 -#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_10 -#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_11 -#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_12 -#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_13 -#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_14 -#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_15 -#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_16 -#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_17 -#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_18 -#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_19 -#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_20 -#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_21 -#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_22 -#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_23 -#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_24 -#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_25 -#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_26 -#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_27 -#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_28 -#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_29 -#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_30 -#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_PS_31 -#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xffffffffL - -// SPI_SHADER_PGM_LO_VS -#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_HI_VS -#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0x000000ffL - -// SPI_SHADER_PGM_RSRC1_VS -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L -#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L - -// SPI_SHADER_PGM_RSRC2_VS -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003fe000L -#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L - -// SPI_SHADER_PGM_RSRC3_VS -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003f0000L -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3c000000L - -// SPI_SHADER_LATE_ALLOC_VS -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003fL - -// SPI_SHADER_USER_DATA_VS_0 -#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_1 -#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_2 -#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_3 -#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_4 -#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_5 -#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_6 -#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_7 -#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_8 -#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_9 -#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_10 -#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_11 -#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_12 -#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_13 -#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_14 -#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_15 -#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_16 -#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_17 -#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_18 -#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_19 -#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_20 -#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_21 -#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_22 -#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_23 -#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_24 -#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_25 -#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_26 -#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_27 -#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_28 -#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_29 -#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_30 -#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_VS_31 -#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xffffffffL - -// SPI_SHADER_PGM_RSRC2_GS_VS -#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07f80000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L - -// SPI_SHADER_USER_DATA_ADDR_LO_GS -#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ADDR_HI_GS -#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_LO_GS -#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_HI_GS -#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0x000000ffL - -// SPI_SHADER_PGM_LO_ES -#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_HI_ES -#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000ffL - -// SPI_SHADER_PGM_RSRC1_GS -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L -#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L -#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L - -// SPI_SHADER_PGM_RSRC2_GS -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L -#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L -#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07f80000L -#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L - -// SPI_SHADER_PGM_RSRC3_GS -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000ffffL -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003f0000L -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03c00000L -#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3c000000L - -// SPI_SHADER_PGM_RSRC4_GS -#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007fL -#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003f80L - -// SPI_SHADER_USER_DATA_ES_0 -#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_1 -#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_2 -#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_3 -#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_4 -#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_5 -#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_6 -#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_7 -#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_8 -#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_9 -#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_10 -#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_11 -#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_12 -#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_13 -#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_14 -#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_15 -#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_16 -#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_17 -#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_18 -#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_19 -#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_20 -#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_21 -#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_22 -#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_23 -#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_24 -#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_25 -#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_26 -#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_27 -#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_28 -#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_29 -#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_30 -#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ES_31 -#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ADDR_LO_HS -#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_ADDR_HI_HS -#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_LO_HS -#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_HI_HS -#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0x000000ffL - -// SPI_SHADER_PGM_LO_LS -#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffffL - -// SPI_SHADER_PGM_HI_LS -#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000ffL - -// SPI_SHADER_PGM_RSRC1_HS -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000c00L -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000ff000L -#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L -#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L - -// SPI_SHADER_PGM_RSRC2_HS -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003eL -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000ff80L -#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01ff0000L -#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L - -// SPI_SHADER_PGM_RSRC3_HS -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003fL -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003c0L -#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003c00L -#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xffff0000L - -// SPI_SHADER_PGM_RSRC4_HS -#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007fL - -// SPI_SHADER_USER_DATA_LS_0 -#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_1 -#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_2 -#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_3 -#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_4 -#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_5 -#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_6 -#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_7 -#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_8 -#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_9 -#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_10 -#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_11 -#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_12 -#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_13 -#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_14 -#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_15 -#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_16 -#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_17 -#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_18 -#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_19 -#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_20 -#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_21 -#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_22 -#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_23 -#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_24 -#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_25 -#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_26 -#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_27 -#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_28 -#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_29 -#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_30 -#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_LS_31 -#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_0 -#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_1 -#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_2 -#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_3 -#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_4 -#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_5 -#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_6 -#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_7 -#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_8 -#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_9 -#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_10 -#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_11 -#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_12 -#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_13 -#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_14 -#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_15 -#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_16 -#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_17 -#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_18 -#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_19 -#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_20 -#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_21 -#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_22 -#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_23 -#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_24 -#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_25 -#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_26 -#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_27 -#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_28 -#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_29 -#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_30 -#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xffffffffL - -// SPI_SHADER_USER_DATA_COMMON_31 -#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xffffffffL - -// SPI_ARB_PRIORITY -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001c0L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000e00L -#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L -#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000c000L -#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L -#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000c0000L - -// SPI_ARB_CYCLES_0 -#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000ffffL -#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000L - -// SPI_ARB_CYCLES_1 -#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000ffffL -#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000L - -// SPI_CDBG_SYS_GFX -#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x00000001L -#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x00000002L -#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x00000004L -#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x00000008L -#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x00000010L -#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x00000020L -#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x00000040L - -// SPI_CDBG_SYS_HP3D -#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x00000001L -#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x00000002L -#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x00000004L -#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x00000008L -#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x00000010L -#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x00000020L - -// SPI_CDBG_SYS_CS0 -#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000ffL -#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000ff00L -#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00ff0000L -#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000L - -// SPI_CDBG_SYS_CS1 -#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0x000000ffL -#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0x0000ff00L -#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0x00ff0000L -#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000L - -// SPI_WCL_PIPE_PERCENT_GFX -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000f80L -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001f000L -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003e0000L -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07c00000L - -// SPI_WCL_PIPE_PERCENT_HP3D -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007fL -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001f000L -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07c00000L - -// SPI_WCL_PIPE_PERCENT_CS0 -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x0000007fL - -// SPI_WCL_PIPE_PERCENT_CS1 -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x0000007fL - -// SPI_WCL_PIPE_PERCENT_CS2 -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x0000007fL - -// SPI_WCL_PIPE_PERCENT_CS3 -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x0000007fL - -// SPI_WCL_PIPE_PERCENT_CS4 -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x0000007fL - -// SPI_WCL_PIPE_PERCENT_CS5 -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x0000007fL - -// SPI_WCL_PIPE_PERCENT_CS6 -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x0000007fL - -// SPI_WCL_PIPE_PERCENT_CS7 -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x0000007fL - -// SPI_GDBG_WAVE_CNTL -#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L -#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001fffeL - -// SPI_GDBG_TRAP_CONFIG -#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L -#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000cL -#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L -#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L -#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L -#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L -#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L -#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000L - -// SPI_GDBG_TRAP_MASK -#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x000001ffL -#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x00000200L - -// SPI_GDBG_WAVE_CNTL2 -#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000ffffL -#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L - -// SPI_GDBG_WAVE_CNTL3 -#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L -#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L -#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L -#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L -#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L -#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L -#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0fffe000L -#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L - -// SPI_GDBG_TRAP_DATA0 -#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffffL - -// SPI_GDBG_TRAP_DATA1 -#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffffL - -// SPI_RESET_DEBUG -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x00000001L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x00000002L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x00000004L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x00000008L -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x00000010L - -// SPI_COMPUTE_QUEUE_RESET -#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x00000001L - -// SPI_RESOURCE_RESERVE_CU_0 -#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_1 -#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_2 -#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_3 -#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_4 -#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_5 -#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_6 -#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_7 -#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_8 -#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_9 -#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_10 -#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_11 -#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_12 -#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_13 -#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_14 -#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_CU_15 -#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000fL -#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000f0L -#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000f00L -#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L - -// SPI_RESOURCE_RESERVE_EN_CU_0 -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_1 -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_2 -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_3 -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_4 -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_5 -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_6 -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_7 -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_8 -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_9 -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_10 -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_11 -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_12 -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_13 -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_14 -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_RESOURCE_RESERVE_EN_CU_15 -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000fffeL -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00ff0000L -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L - -// SPI_COMPUTE_WF_CTX_SAVE -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L - -// SPI_ARB_CNTL_0 -#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000fL -#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000f0L -#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000f00L - -// SPI_PS_INPUT_CNTL_0 -#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_1 -#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_2 -#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_3 -#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_4 -#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_5 -#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_6 -#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_7 -#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_8 -#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_9 -#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_10 -#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_11 -#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_12 -#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_13 -#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_14 -#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_15 -#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_16 -#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_17 -#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_18 -#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_19 -#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001e000L -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_20 -#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_21 -#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_22 -#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_23 -#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_24 -#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_25 -#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_26 -#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_27 -#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_28 -#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_29 -#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_30 -#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L - -// SPI_PS_INPUT_CNTL_31 -#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003fL -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L - -// SPI_VS_OUT_CONFIG -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003eL -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L - -// SPI_PS_INPUT_ENA -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L - -// SPI_PS_INPUT_ADDR -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L - -// SPI_INTERP_CONTROL_0 -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001cL -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000e0L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L - -// SPI_PS_IN_CONTROL -#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL -#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L -#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L -#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L - -// SPI_BARYC_CNTL -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L -#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L - -// SPI_TMPRING_SIZE -#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000fffL -#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L - -// SPI_SHADER_POS_FORMAT -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000fL -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000f0L -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000f00L -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000f000L - -// SPI_SHADER_Z_FORMAT -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000fL - -// SPI_SHADER_COL_FORMAT -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000fL -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000f0L -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000f00L -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000f000L -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000f0000L -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00f00000L -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0f000000L -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000L - -// SPI_CONFIG_CNTL -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001fffffL -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00e00000L -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L -#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L -#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L -#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xc0000000L - -// SPI_CONFIG_CNTL_1 -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000fL -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L -#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003c00L -#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L -#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000L - -// SPI_CONFIG_CNTL_2 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000fL -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000f0L - -// SPI_PERFCOUNTER0_HI -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SPI_PERFCOUNTER0_LO -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SPI_PERFCOUNTER1_HI -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SPI_PERFCOUNTER1_LO -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SPI_PERFCOUNTER2_HI -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SPI_PERFCOUNTER2_LO -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SPI_PERFCOUNTER3_HI -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SPI_PERFCOUNTER3_LO -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SPI_PERFCOUNTER4_HI -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SPI_PERFCOUNTER4_LO -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SPI_PERFCOUNTER5_HI -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SPI_PERFCOUNTER5_LO -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SPI_PERFCOUNTER0_SELECT -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// SPI_PERFCOUNTER1_SELECT -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// SPI_PERFCOUNTER2_SELECT -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003ffL -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// SPI_PERFCOUNTER3_SELECT -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003ffL -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0f000000L -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// SPI_PERFCOUNTER0_SELECT1 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// SPI_PERFCOUNTER1_SELECT1 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// SPI_PERFCOUNTER2_SELECT1 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// SPI_PERFCOUNTER3_SELECT1 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// SPI_PERFCOUNTER4_SELECT -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000ffL - -// SPI_PERFCOUNTER5_SELECT -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000ffL - -// SPI_PERFCOUNTER_BINS -#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000fL -#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000f0L -#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000f00L -#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000f000L -#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000f0000L -#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00f00000L -#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0f000000L -#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000L - -// CGTS_SM_CTRL_REG -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L -#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L -#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L -#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L -#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L -#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L - -// CGTS_RD_CTRL_REG -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL -#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L - -// CGTS_RD_REG -#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL - -// CGTS_TCC_DISABLE -#define CGTS_TCC_DISABLE__WRITE_DIS_MASK 0x00000001L -#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L - -// CGTS_USER_TCC_DISABLE -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L - -// CGTS_CU0_SP0_CTRL_REG -#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU0_LDS_SQ_CTRL_REG -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU0_TA_SQC_CTRL_REG -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007f0000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU0_SP1_CTRL_REG -#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU0_TD_TCP_CTRL_REG -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU0_TCPI_CTRL_REG -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU1_SP0_CTRL_REG -#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU1_LDS_SQ_CTRL_REG -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU1_TA_SQC_CTRL_REG -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU1_SP1_CTRL_REG -#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU1_TD_TCP_CTRL_REG -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU1_TCPI_CTRL_REG -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU2_SP0_CTRL_REG -#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU2_LDS_SQ_CTRL_REG -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU2_TA_SQC_CTRL_REG -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU2_SP1_CTRL_REG -#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU2_TD_TCP_CTRL_REG -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU2_TCPI_CTRL_REG -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU3_SP0_CTRL_REG -#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU3_LDS_SQ_CTRL_REG -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU3_TA_SQC_CTRL_REG -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007f0000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU3_SP1_CTRL_REG -#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU3_TD_TCP_CTRL_REG -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU3_TCPI_CTRL_REG -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU4_SP0_CTRL_REG -#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU4_LDS_SQ_CTRL_REG -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU4_TA_SQC_CTRL_REG -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU4_SP1_CTRL_REG -#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU4_TD_TCP_CTRL_REG -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU4_TCPI_CTRL_REG -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU5_SP0_CTRL_REG -#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU5_LDS_SQ_CTRL_REG -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU5_TA_SQC_CTRL_REG -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU5_SP1_CTRL_REG -#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU5_TD_TCP_CTRL_REG -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU5_TCPI_CTRL_REG -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU6_SP0_CTRL_REG -#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU6_LDS_SQ_CTRL_REG -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU6_TA_SQC_CTRL_REG -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007f0000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU6_SP1_CTRL_REG -#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU6_TD_TCP_CTRL_REG -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU6_TCPI_CTRL_REG -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU7_SP0_CTRL_REG -#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU7_LDS_SQ_CTRL_REG -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU7_TA_SQC_CTRL_REG -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU7_SP1_CTRL_REG -#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU7_TD_TCP_CTRL_REG -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU7_TCPI_CTRL_REG -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU8_SP0_CTRL_REG -#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU8_LDS_SQ_CTRL_REG -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU8_TA_SQC_CTRL_REG -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU8_SP1_CTRL_REG -#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU8_TD_TCP_CTRL_REG -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU8_TCPI_CTRL_REG -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU9_SP0_CTRL_REG -#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU9_LDS_SQ_CTRL_REG -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU9_TA_SQC_CTRL_REG -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007f0000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU9_SP1_CTRL_REG -#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU9_TD_TCP_CTRL_REG -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU9_TCPI_CTRL_REG -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU10_SP0_CTRL_REG -#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU10_LDS_SQ_CTRL_REG -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU10_TA_SQC_CTRL_REG -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU10_SP1_CTRL_REG -#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU10_TD_TCP_CTRL_REG -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU10_TCPI_CTRL_REG -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU11_SP0_CTRL_REG -#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU11_LDS_SQ_CTRL_REG -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU11_TA_SQC_CTRL_REG -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU11_SP1_CTRL_REG -#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU11_TD_TCP_CTRL_REG -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU11_TCPI_CTRL_REG -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU12_SP0_CTRL_REG -#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU12_LDS_SQ_CTRL_REG -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU12_TA_SQC_CTRL_REG -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007f0000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU12_SP1_CTRL_REG -#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU12_TD_TCP_CTRL_REG -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU12_TCPI_CTRL_REG -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU13_SP0_CTRL_REG -#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU13_LDS_SQ_CTRL_REG -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU13_TA_SQC_CTRL_REG -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU13_SP1_CTRL_REG -#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU13_TD_TCP_CTRL_REG -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU13_TCPI_CTRL_REG -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU14_SP0_CTRL_REG -#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU14_LDS_SQ_CTRL_REG -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU14_TA_SQC_CTRL_REG -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L - -// CGTS_CU14_SP1_CTRL_REG -#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU14_TD_TCP_CTRL_REG -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU14_TCPI_CTRL_REG -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTS_CU15_SP0_CTRL_REG -#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007fL -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007f0000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU15_LDS_SQ_CTRL_REG -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007fL -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007f0000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU15_TA_SQC_CTRL_REG -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007fL -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007f0000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU15_SP1_CTRL_REG -#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007fL -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007f0000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU15_TD_TCP_CTRL_REG -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007fL -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007f0000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L - -// CGTS_CU15_TCPI_CTRL_REG -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007fL -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xfffff000L - -// CGTT_SPI_CLK_CTRL -#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// CGTT_PC_CLK_CTRL -#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L -#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// CGTT_BCI_CLK_CTRL -#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000f000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// SQ_CONFIG -#define SQ_CONFIG__UNUSED_MASK 0x0000007fL -#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L -#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L -#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L -#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L -#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L -#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0fe00000L -#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L -#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L -#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L -#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L - -// SQC_CONFIG -#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L -#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000cL -#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L -#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L -#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L -#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L -#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L -#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L -#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L -#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L -#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L -#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L -#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00ff0000L -#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L -#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L - -// LDS_CONFIG -#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L -#define LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK 0x00000002L - -// SQC_DSM_CNTL -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000c0L -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000c0000L -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L - -// SQC_DSM_CNTLA -#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000c0L -#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000c0000L -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L -#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L - -// SQC_DSM_CNTLB -#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000c0L -#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000c0000L -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L -#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L - -// SQC_DSM_CNTL2 -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000c0000L -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xfc000000L - -// SQC_DSM_CNTL2A -#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000c0000L -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L - -// SQC_DSM_CNTL2B -#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000c0000L -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L - -// SQC_EDC_FUE_CNTL -#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000ffffL -#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xffff0000L - -// SQC_EDC_CNT2 -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000cL -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000c0L -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000c00L -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000c000L -#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000c0000L -#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00c00000L -#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0c000000L -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L - -// SQC_EDC_CNT3 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000cL -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000c0L -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000c00L -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000c000L -#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000c0000L -#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00c00000L -#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L - -// SQ_RANDOM_WAVE_PRI -#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007fL -#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L -#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007ffc00L - -// SQ_REG_CREDITS -#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003fL -#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000f00L -#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L -#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L -#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L -#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L - -// SQ_FIFO_SIZES -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000fL -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000f00L -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000c0000L - -// SQ_DSM_CNTL -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L - -// SQ_DSM_CNTL2 -#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000fc000L -#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03f00000L -#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xfc000000L - -// SQ_RUNTIME_CONFIG -#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L - -// CC_GC_SHADER_RATE_CONFIG -#define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS_MASK 0x00000001L -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L - -// GC_USER_SHADER_RATE_CONFIG -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L - -// SQ_INTERRUPT_AUTO_MASK -#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00ffffffL - -// SQ_INTERRUPT_MSG_CTRL -#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L - -// SQ_DEBUG_PERFCOUNT_TRAP -#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK 0x00000001L -#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK 0x0000000eL -#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK 0x0ffffff0L - -// SQ_UTCL1_CNTL1 -#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000ff80L -#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L -#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L -#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000L - -// SQ_UTCL1_CNTL2 -#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000ffL -#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007f0000L -#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xf0000000L - -// SQ_UTCL1_STATUS -#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000fff8L -#define SQ_UTCL1_STATUS__UNUSED_MASK 0xffff0000L - -// SQ_TIME_HI -#define SQ_TIME_HI__TIME_MASK 0xffffffffL - -// SQ_TIME_LO -#define SQ_TIME_LO__TIME_MASK 0xffffffffL - -// SQ_LB_CTR_CTRL -#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L -#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L -#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L - -// SQ_LB_DATA0 -#define SQ_LB_DATA0__DATA_MASK 0xffffffffL - -// SQ_LB_DATA1 -#define SQ_LB_DATA1__DATA_MASK 0xffffffffL - -// SQ_LB_DATA2 -#define SQ_LB_DATA2__DATA_MASK 0xffffffffL - -// SQ_LB_DATA3 -#define SQ_LB_DATA3__DATA_MASK 0xffffffffL - -// SQ_LB_CTR_SEL -#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000fL -#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000f0L -#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000f00L -#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000f000L - -// SQ_LB_CTR0_CU -#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000ffffL -#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xffff0000L - -// SQ_LB_CTR1_CU -#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000ffffL -#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xffff0000L - -// SQ_LB_CTR2_CU -#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000ffffL -#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xffff0000L - -// SQ_LB_CTR3_CU -#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000ffffL -#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xffff0000L - -// SQC_EDC_CNT -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000cL -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000c0L -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000c00L -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000c000L -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000c0000L -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00c00000L -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0c000000L -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xc0000000L - -// SQ_EDC_SEC_CNT -#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000ffL -#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000ff00L -#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00ff0000L - -// SQ_EDC_DED_CNT -#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000ffL -#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000ff00L -#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00ff0000L - -// SQ_EDC_INFO -#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000fL -#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L -#define SQ_EDC_INFO__SOURCE_MASK 0x000001c0L -#define SQ_EDC_INFO__VM_ID_MASK 0x00001e00L - -// SQ_EDC_CNT -#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L -#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000cL -#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L -#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000c0L -#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L -#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000c00L -#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L -#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000c000L -#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L -#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000c0000L -#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L -#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00c00000L -#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L -#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0c000000L - -// SQ_EDC_FUE_CNTL -#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000ffffL -#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xffff0000L - -// SQ_BUF_RSRC_WORD0 -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL - -// SQ_BUF_RSRC_WORD1 -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000ffffL -#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000L -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L - -// SQ_BUF_RSRC_WORD2 -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffffL - -// SQ_BUF_RSRC_WORD3 -#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L -#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L -#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L -#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L -#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L -#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000L - -// SQ_IMG_RSRC_WORD0 -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL - -// SQ_IMG_RSRC_WORD1 -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000ffL -#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000fff00L -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03f00000L -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000L -#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L -#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L - -// SQ_IMG_RSRC_WORD2 -#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003fffL -#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0fffc000L -#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L - -// SQ_IMG_RSRC_WORD3 -#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L -#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000f000L -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000f0000L -#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01f00000L -#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000L - -// SQ_IMG_RSRC_WORD4 -#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001fffL -#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1fffe000L -#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xe0000000L - -// SQ_IMG_RSRC_WORD5 -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001fffL -#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001e000L -#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01fe0000L -#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L -#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L -#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L -#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xf0000000L - -// SQ_IMG_RSRC_WORD6 -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000fffL -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000ff000L -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0f000000L -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000L - -// SQ_IMG_RSRC_WORD7 -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffffL - -// SQ_IMG_SAMP_WORD0 -#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L -#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L -#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001c0L -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000e00L -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07e00000L -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L - -// SQ_IMG_SAMP_WORD1 -#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000fffL -#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00fff000L -#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0f000000L -#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000L - -// SQ_IMG_SAMP_WORD2 -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003fffL -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000fc000L -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00c00000L -#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L -#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0c000000L -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L - -// SQ_IMG_SAMP_WORD3 -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000fffL -#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000L - -// SQ_FLAT_SCRATCH_WORD0 -#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007ffffL - -// SQ_FLAT_SCRATCH_WORD1 -#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00ffffffL - -// SQ_M0_GPR_IDX_WORD -#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000ffL -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L -#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L - -// SQ_IND_INDEX -#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000fL -#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L -#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000fc0L -#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L -#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L -#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L -#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L -#define SQ_IND_INDEX__INDEX_MASK 0xffff0000L - -// SQ_CMD -#define SQ_CMD__CMD_MASK 0x00000007L -#define SQ_CMD__MODE_MASK 0x00000070L -#define SQ_CMD__CHECK_VMID_MASK 0x00000080L -#define SQ_CMD__DATA_MASK 0x00000f00L -#define SQ_CMD__WAVE_ID_MASK 0x000f0000L -#define SQ_CMD__SIMD_ID_MASK 0x00300000L -#define SQ_CMD__QUEUE_ID_MASK 0x07000000L -#define SQ_CMD__VM_ID_MASK 0xf0000000L - -// SQ_IND_DATA -#define SQ_IND_DATA__DATA_MASK 0xffffffffL - -// SQ_REG_TIMESTAMP -#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000ffL - -// SQ_CMD_TIMESTAMP -#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000ffL - -// SQ_DEBUG_STS_GLOBAL -#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L -#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L - -// SQ_DEBUG_STS_GLOBAL2 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L - -// SQ_DEBUG_STS_GLOBAL3 -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000003f0L - -// SH_MEM_BASES -#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000ffffL -#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000L - -// SH_MEM_CONFIG -#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L -#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L -#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L -#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L - -// SQ_SHADER_TBA_LO -#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xffffffffL - -// SQ_SHADER_TBA_HI -#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000ffL - -// SQ_SHADER_TMA_LO -#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xffffffffL - -// SQ_SHADER_TMA_HI -#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000ffL - -// SQ_THREAD_TRACE_WORD_CMN -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x00000010L - -// SQ_THREAD_TRACE_WORD_INST -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x000001e0L -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x00000600L -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0x0000f800L - -// SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001e0L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000L - -// SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00ffffffL - -// SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003c00L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000c000L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000L - -// SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0x0000ffffL - -// SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000L - -// SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffffL - -// SQ_THREAD_TRACE_WORD_WAVE -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x00003c00L -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0x0000c000L - -// SQ_THREAD_TRACE_WORD_MISC -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x00000ff0L -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x00001000L -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0x0000e000L - -// SQ_THREAD_TRACE_WORD_WAVE_START -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003c00L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000c000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001f0000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000L - -// SQ_THREAD_TRACE_WORD_REG_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001c00L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000L - -// SQ_THREAD_TRACE_WORD_REG_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffffL - -// SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000fe00L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000L - -// SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000ffffL - -// SQ_THREAD_TRACE_WORD_EVENT -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x000001c0L -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0x0000fc00L - -// SQ_THREAD_TRACE_WORD_ISSUE -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000c00L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000c000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000c0000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00c00000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0c000000L - -// SQ_THREAD_TRACE_WORD_PERF_1_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003c0L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000c00L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01fff000L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000L - -// SQ_THREAD_TRACE_WORD_PERF_2_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003fL -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007ffc0L -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000L - -// SQ_WREXEC_EXEC_LO -#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffffL - -// SQ_WREXEC_EXEC_HI -#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000ffffL -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L -#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L -#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L -#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L - -// SQC_ICACHE_UTCL1_CNTL1 -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000ff80L -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000L - -// SQC_ICACHE_UTCL1_CNTL2 -#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000ffL -#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01e00000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L - -// SQC_DCACHE_UTCL1_CNTL1 -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000ff80L -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000L - -// SQC_DCACHE_UTCL1_CNTL2 -#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000ffL -#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01e00000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L - -// SQC_ICACHE_UTCL1_STATUS -#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L - -// SQC_DCACHE_UTCL1_STATUS -#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L - -// SQC_CACHES -#define SQC_CACHES__TARGET_INST_MASK 0x00000001L -#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L -#define SQC_CACHES__INVALIDATE_MASK 0x00000004L -#define SQC_CACHES__WRITEBACK_MASK 0x00000008L -#define SQC_CACHES__VOL_MASK 0x00000010L -#define SQC_CACHES__COMPLETE_MASK 0x00010000L - -// SQC_WRITEBACK -#define SQC_WRITEBACK__DWB_MASK 0x00000001L -#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L - -// SQ_THREAD_TRACE_BASE -#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffffL - -// SQ_THREAD_TRACE_BASE2 -#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000fL - -// SQ_THREAD_TRACE_SIZE -#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003fffffL - -// SQ_THREAD_TRACE_MASK -#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001fL -#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L -#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000f00L -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L - -// SQ_THREAD_TRACE_USERDATA_0 -#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffffL - -// SQ_THREAD_TRACE_USERDATA_1 -#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffffL - -// SQ_THREAD_TRACE_USERDATA_2 -#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffffL - -// SQ_THREAD_TRACE_USERDATA_3 -#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffffL - -// SQ_THREAD_TRACE_MODE -#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L -#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L -#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001c0L -#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000e00L -#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L -#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L -#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001c0000L -#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L -#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L -#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L -#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L - -// SQ_THREAD_TRACE_CTRL -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L - -// SQ_THREAD_TRACE_TOKEN_MASK -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000ffffL -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00ff0000L -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L - -// SQ_THREAD_TRACE_TOKEN_MASK2 -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffffL - -// SQ_THREAD_TRACE_PERF_MASK -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000ffffL -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000L - -// SQ_THREAD_TRACE_WPTR -#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffffL -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000L - -// SQ_THREAD_TRACE_STATUS -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003ffL -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03ff0000L -#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L -#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L -#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L -#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L - -// SQ_THREAD_TRACE_CNTR -#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffffL - -// SQ_THREAD_TRACE_HIWATER -#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L - -// SQ_PERFCOUNTER0_LO -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER1_LO -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER2_LO -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER3_LO -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER4_LO -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER5_LO -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER6_LO -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER7_LO -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER8_LO -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER9_LO -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER10_LO -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER11_LO -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER12_LO -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER13_LO -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER14_LO -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER15_LO -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SQ_PERFCOUNTER0_HI -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER1_HI -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER2_HI -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER3_HI -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER4_HI -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER5_HI -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER6_HI -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER7_HI -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER8_HI -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER9_HI -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER10_HI -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER11_HI -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER12_HI -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER13_HI -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER14_HI -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER15_HI -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SQ_PERFCOUNTER_CTRL -#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L -#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L -#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L -#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L -#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L -#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L -#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001f00L -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L - -// SQ_PERFCOUNTER_MASK -#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000ffffL -#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000L - -// SQ_PERFCOUNTER_CTRL2 -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L - -// SQ_PERFCOUNTER0_SELECT -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER1_SELECT -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER2_SELECT -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER3_SELECT -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER4_SELECT -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER5_SELECT -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER6_SELECT -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER7_SELECT -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER8_SELECT -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER9_SELECT -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER10_SELECT -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER11_SELECT -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER12_SELECT -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER13_SELECT -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER14_SELECT -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000L - -// SQ_PERFCOUNTER15_SELECT -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001ffL -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000f000L -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00f00000L -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0f000000L -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000L - -// CGTT_SQ_CLK_CTRL -#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// CGTT_SQG_CLK_CTRL -#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// SQ_ALU_CLK_CTRL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L - -// SQ_TEX_CLK_CTRL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L - -// SQ_LDS_CLK_CTRL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L - -// SQ_POWER_THROTTLE -#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003fffL -#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000L -#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000L - -// SQ_POWER_THROTTLE2 -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003fffL -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L - -// SQ_WAVE_INST_DW0 -#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffffL - -// SQ_WAVE_INST_DW1 -#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffffL - -// SQ_WAVE_PC_LO -#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffffL - -// SQ_WAVE_PC_HI -#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000ffffL - -// SQ_WAVE_IB_DBG0 -#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L -#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000e0L -#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L -#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000c00L -#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000f0000L -#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L -#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L -#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L -#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L - -// SQ_WAVE_IB_DBG1 -#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L -#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L -#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001f0L -#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000f800L -#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007c0000L -#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xfe000000L - -// SQ_WAVE_FLUSH_IB -#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xffffffffL - -// SQ_WAVE_EXEC_LO -#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffffL - -// SQ_WAVE_EXEC_HI -#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffffL - -// SQ_WAVE_STATUS -#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L -#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L -#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L -#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L -#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L -#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L -#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L -#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L -#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L -#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L -#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L -#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L -#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L -#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L -#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L -#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L -#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L -#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L -#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L -#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L -#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L -#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L -#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L - -// SQ_WAVE_MODE -#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000fL -#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000f0L -#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L -#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L -#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L -#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L -#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001ff000L -#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L -#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L -#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L -#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L -#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L -#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L -#define SQ_WAVE_MODE__CSP_MASK 0xe0000000L - -// SQ_WAVE_TRAPSTS -#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001ffL -#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L -#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L -#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003f0000L -#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L -#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000L - -// SQ_WAVE_HW_ID -#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000fL -#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L -#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000c0L -#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000f00L -#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L -#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L -#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000f0000L -#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00f00000L -#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L -#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L -#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000L - -// SQ_WAVE_GPR_ALLOC -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003fL -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003f00L -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003f0000L -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0f000000L - -// SQ_WAVE_LDS_ALLOC -#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000ffL -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001ff000L - -// SQ_WAVE_IB_STS -#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000fL -#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L -#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000f00L -#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L -#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L -#define SQ_WAVE_IB_STS__RCNT_MASK 0x001f0000L -#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00c00000L - -// SQ_WAVE_M0 -#define SQ_WAVE_M0__M0_MASK 0xffffffffL - -// SQ_WAVE_TTMP0 -#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP1 -#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP2 -#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP3 -#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP4 -#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP5 -#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP6 -#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP7 -#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP8 -#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP9 -#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP10 -#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP11 -#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP12 -#define SQ_WAVE_TTMP12__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP13 -#define SQ_WAVE_TTMP13__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP14 -#define SQ_WAVE_TTMP14__DATA_MASK 0xffffffffL - -// SQ_WAVE_TTMP15 -#define SQ_WAVE_TTMP15__DATA_MASK 0xffffffffL - -// SQ_DEBUG_STS_LOCAL -#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L -#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L - -// SQ_DEBUG_CTRL_LOCAL -#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000ffL - -// SQ_INTERRUPT_WORD_CMN_HI -#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x00000300L -#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0x00000c00L - -// SQ_INTERRUPT_WORD_AUTO_LO -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x00000001L -#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x00000002L -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x00000004L -#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x00000008L -#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x00000010L -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x00000020L -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x00000040L -#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x00000080L -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x00000100L - -// SQ_INTERRUPT_WORD_AUTO_HI -#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x00000300L -#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0x00000c00L - -// SQ_INTERRUPT_WORD_WAVE_LO -#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00ffffffL -#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3c000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xc0000000L - -// SQ_INTERRUPT_WORD_WAVE_HI -#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x0000000fL -#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x000000f0L -#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x00000300L -#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0x00000c00L - -// SQ_INTERRUPT_WORD_CMN_CTXID -#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x03000000L -#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0x0c000000L - -// SQ_INTERRUPT_WORD_AUTO_CTXID -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000L - -// SQ_INTERRUPT_WORD_WAVE_CTXID -#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fffL -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000L - -// COMPUTE_DISPATCH_INITIATOR -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L -#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L -#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L - -// COMPUTE_DIM_X -#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL - -// COMPUTE_DIM_Y -#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL - -// COMPUTE_DIM_Z -#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL - -// COMPUTE_START_X -#define COMPUTE_START_X__START_MASK 0xffffffffL - -// COMPUTE_START_Y -#define COMPUTE_START_Y__START_MASK 0xffffffffL - -// COMPUTE_START_Z -#define COMPUTE_START_Z__START_MASK 0xffffffffL - -// COMPUTE_NUM_THREAD_X -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L - -// COMPUTE_NUM_THREAD_Y -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L - -// COMPUTE_NUM_THREAD_Z -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L - -// COMPUTE_PIPELINESTAT_ENABLE -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L - -// COMPUTE_PERFCOUNT_ENABLE -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L - -// COMPUTE_PGM_LO -#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL - -// COMPUTE_PGM_HI -#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL - -// COMPUTE_DISPATCH_PKT_ADDR_LO -#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xffffffffL - -// COMPUTE_DISPATCH_PKT_ADDR_HI -#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000ffL - -// COMPUTE_DISPATCH_SCRATCH_BASE_LO -#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xffffffffL - -// COMPUTE_DISPATCH_SCRATCH_BASE_HI -#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000ffL - -// COMPUTE_PGM_RSRC1 -#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL -#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L -#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L -#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L -#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L -#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L -#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L -#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L -#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L -#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L -#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L - -// COMPUTE_PGM_RSRC2 -#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L -#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L -#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L -#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L -#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L -#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L -#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L -#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L - -// COMPUTE_VMID -#define COMPUTE_VMID__DATA_MASK 0x0000000fL - -// COMPUTE_RESOURCE_LIMITS -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003ffL -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L -#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L - -// COMPUTE_STATIC_THREAD_MGMT_SE0 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L - -// COMPUTE_STATIC_THREAD_MGMT_SE1 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L - -// COMPUTE_TMPRING_SIZE -#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL -#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L - -// COMPUTE_STATIC_THREAD_MGMT_SE2 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000L - -// COMPUTE_STATIC_THREAD_MGMT_SE3 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000ffffL -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000L - -// COMPUTE_RESTART_X -#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffffL - -// COMPUTE_RESTART_Y -#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffffL - -// COMPUTE_RESTART_Z -#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffffL - -// COMPUTE_THREAD_TRACE_ENABLE -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L - -// COMPUTE_MISC_RESERVED -#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L -#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L -#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L -#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001ffe0L - -// COMPUTE_DISPATCH_ID -#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffffL - -// COMPUTE_THREADGROUP_ID -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffffL - -// COMPUTE_RELAUNCH -#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffffL -#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L -#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L - -// COMPUTE_WAVE_RESTORE_ADDR_LO -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffffL - -// COMPUTE_WAVE_RESTORE_ADDR_HI -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0x0000ffffL - -// COMPUTE_USER_DATA_0 -#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_1 -#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_2 -#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_3 -#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_4 -#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_5 -#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_6 -#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_7 -#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_8 -#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_9 -#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_10 -#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_11 -#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_12 -#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_13 -#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_14 -#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL - -// COMPUTE_USER_DATA_15 -#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL - -// COMPUTE_NOWHERE -#define COMPUTE_NOWHERE__DATA_MASK 0xffffffffL - -// CSPRIV_CONNECT -#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x0000ffffL -#define CSPRIV_CONNECT__QUEUE_ID_MASK 0x00e00000L -#define CSPRIV_CONNECT__RELAUNCH_WAVES_MASK 0x01000000L -#define CSPRIV_CONNECT__QSWITCH_MODE_MASK 0x02000000L -#define CSPRIV_CONNECT__VMID_MASK 0x3c000000L -#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000L - -// CSPRIV_CONNECT2 -#define CSPRIV_CONNECT2__DOORBELL_OFFSET_MASK 0x03ffffffL - -// CSPRIV_THREAD_TRACE_TG0 -#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffffL - -// CSPRIV_THREAD_TRACE_TG1 -#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffffL - -// CSPRIV_THREAD_TRACE_TG2 -#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffffL - -// CSPRIV_THREAD_TRACE_TG3 -#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0x00000fffL -#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0x00fff000L -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x01000000L -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x02000000L -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x04000000L -#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x08000000L -#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000L - -// CSPRIV_THREAD_TRACE_EVENT -#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x0000001fL - -// VGT_DMA_PRIMITIVE_TYPE -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003fL - -// VGT_DMA_CONTROL -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000ffffL -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L -#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L -#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L -#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L -#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L - -// VGT_VTX_VECT_EJECT_REG -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007fL - -// VGT_DMA_DATA_FIFO_DEPTH -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001ffL -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007fe00L - -// VGT_DMA_REQ_FIFO_DEPTH -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003fL - -// VGT_DRAW_INIT_FIFO_DEPTH -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003fL - -// VGT_LAST_COPY_STATE -#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L - -// CC_GC_SHADER_ARRAY_CONFIG -#define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS_MASK 0x00000001L -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L - -// GC_USER_SHADER_ARRAY_CONFIG -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L - -// VGT_CACHE_INVALIDATION -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000c0L -#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L -#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001f0000L -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01c00000L -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0e000000L -#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L - -// VGT_RESET_DEBUG -#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L -#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L -#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L - -// VGT_STRMOUT_DELAY -#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000ffL -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001c000L -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000e0000L - -// VGT_FIFO_DEPTHS -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007fL -#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003fff00L -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0fc00000L - -// VGT_GS_VERTEX_REUSE -#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001fL - -// VGT_MC_LAT_CNTL -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000fL - -// IA_CNTL_STATUS -#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L -#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L -#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L -#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L - -// VGT_DMA_LS_HS_CONFIG -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003f00L - -// VGT_SYS_CONFIG -#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007eL -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L - -// WD_BUF_RESOURCE_1 -#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000ffffL -#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xffff0000L - -// WD_BUF_RESOURCE_2 -#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001fffL -#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L -#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xffff0000L - -// VGT_VS_MAX_WAVE_ID -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL - -// VGT_GS_MAX_WAVE_ID -#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL - -// WD_CNTL_STATUS -#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L -#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L - -// GFX_PIPE_CONTROL -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001fffL -#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000e000L -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L - -// VGT_DEBUG_CNTL -#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000003fL -#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x00000040L - -// VGT_DEBUG_DATA -#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL - -// IA_DEBUG_CNTL -#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x0000003fL -#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x00000040L - -// IA_DEBUG_DATA -#define IA_DEBUG_DATA__DATA_MASK 0xffffffffL - -// VGT_CNTL_STATUS -#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L -#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L -#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L -#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L -#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L -#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L -#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L -#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L -#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L -#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L - -// WD_DEBUG_CNTL -#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x0000003fL -#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x00000040L - -// WD_DEBUG_DATA -#define WD_DEBUG_DATA__DATA_MASK 0xffffffffL - -// WD_QOS -#define WD_QOS__DRAW_STALL_MASK 0x00000001L - -// WD_UTCL1_CNTL -#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L - -// WD_UTCL1_STATUS -#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003f00L -#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003f0000L -#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3f000000L - -// IA_UTCL1_CNTL -#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L - -// IA_UTCL1_STATUS -#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003f00L -#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003f0000L -#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3f000000L - -// CC_GC_PRIM_CONFIG -#define CC_GC_PRIM_CONFIG__WRITE_DIS_MASK 0x00000001L -#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0f000000L - -// GC_USER_PRIM_CONFIG -#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0f000000L - -// CS_COPY_STATE -#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L - -// GFX_COPY_STATE -#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L - -// VGT_DRAW_INITIATOR -#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L -#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000cL -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L -#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L -#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L -#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L -#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L -#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xe0000000L - -// VGT_DRAW_PAYLOAD_CNTL -#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L -#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L -#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L -#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L - -// VGT_INDEX_PAYLOAD_CNTL -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L - -// VGT_EVENT_INITIATOR -#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL -#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07fffc00L -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L - -// VGT_DMA_EVENT_INITIATOR -#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL -#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07fffc00L -#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L - -// VGT_EVENT_ADDRESS_REG -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0fffffffL - -// VGT_GS_MAX_PRIMS_PER_SUBGROUP -#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000ffffL - -// VGT_DMA_BASE_HI -#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000ffffL - -// VGT_DMA_BASE -#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL - -// VGT_DMA_INDEX_TYPE -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000cL -#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L -#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L -#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L -#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L - -// VGT_DMA_NUM_INSTANCES -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL - -// IA_ENHANCE -#define IA_ENHANCE__MISC_MASK 0xffffffffL - -// VGT_DMA_SIZE -#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffffL - -// VGT_DMA_MAX_SIZE -#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffffL - -// VGT_IMMED_DATA -#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL - -// VGT_PRIMITIVEID_EN -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L -#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L - -// VGT_PRIMITIVEID_RESET -#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffffL - -// VGT_VTX_CNT_EN -#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L - -// VGT_REUSE_OFF -#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L - -// VGT_INSTANCE_STEP_RATE_0 -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffffL - -// VGT_INSTANCE_STEP_RATE_1 -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffffL - -// VGT_VERTEX_REUSE_BLOCK_CNTL -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000ffL - -// VGT_OUT_DEALLOC_CNTL -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007fL - -// VGT_MULTI_PRIM_IB_RESET_INDX -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffffL - -// VGT_ENHANCE -#define VGT_ENHANCE__MISC_MASK 0xffffffffL - -// VGT_OUTPUT_PATH_CNTL -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L - -// VGT_HOS_CNTL -#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L - -// VGT_HOS_MAX_TESS_LEVEL -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffffL - -// VGT_HOS_MIN_TESS_LEVEL -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffffL - -// VGT_HOS_REUSE_DEPTH -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000ffL - -// VGT_GROUP_PRIM_TYPE -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001fL -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L - -// VGT_GROUP_FIRST_DECR -#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000fL - -// VGT_GROUP_DECR -#define VGT_GROUP_DECR__DECR_MASK 0x0000000fL - -// VGT_GROUP_VECT_0_CNTL -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000ff00L -#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00ff0000L - -// VGT_GROUP_VECT_1_CNTL -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000ff00L -#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00ff0000L - -// VGT_GROUP_VECT_0_FMT_CNTL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000fL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000f0L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000f00L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000f0000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0f000000L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000L - -// VGT_GROUP_VECT_1_FMT_CNTL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000fL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000f0L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000f00L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000f0000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0f000000L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000L - -// VGT_GS_MODE -#define VGT_GS_MODE__MODE_MASK 0x00000007L -#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L -#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L -#define VGT_GS_MODE__RESERVED_1_MASK 0x000007c0L -#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L -#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L -#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L -#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L -#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L -#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L -#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L -#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L - -// VGT_GS_ONCHIP_CNTL -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007ffL -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003ff800L -#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xffc00000L - -// VGT_GS_OUT_PRIM_TYPE -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003fL -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003f00L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003f0000L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0fc00000L -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L - -// VGT_GS_PER_ES -#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007ffL - -// VGT_ES_PER_GS -#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007ffL - -// VGT_GS_PER_VS -#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000fL - -// VGT_STRMOUT_CONFIG -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L -#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000f00L -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L - -// VGT_STRMOUT_BUFFER_SIZE_0 -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_SIZE_1 -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_SIZE_2 -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_SIZE_3 -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_OFFSET_0 -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_OFFSET_1 -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_OFFSET_2 -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_OFFSET_3 -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffffL - -// VGT_STRMOUT_VTX_STRIDE_0 -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003ffL - -// VGT_STRMOUT_VTX_STRIDE_1 -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003ffL - -// VGT_STRMOUT_VTX_STRIDE_2 -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003ffL - -// VGT_STRMOUT_VTX_STRIDE_3 -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003ffL - -// VGT_STRMOUT_BUFFER_CONFIG -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000fL -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000f0L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000f00L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000f000L - -// VGT_STRMOUT_DRAW_OPAQUE_OFFSET -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffffL - -// VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001ffL - -// VGT_GS_MAX_VERT_OUT -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007ffL - -// VGT_SHADER_STAGES_EN -#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L -#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L -#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L -#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L -#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000c0L -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L -#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L -#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L -#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L -#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L - -// VGT_DISPATCH_DRAW_INDEX -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffffL - -// VGT_LS_HS_CONFIG -#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000ffL -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003f00L -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000fc000L - -// VGT_TF_PARAM -#define VGT_TF_PARAM__TYPE_MASK 0x00000003L -#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001cL -#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000e0L -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L -#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L -#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L -#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L -#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L - -// VGT_TESS_DISTRIBUTION -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000ffL -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000ff00L -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00ff0000L -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1f000000L -#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xe0000000L - -// VGT_GS_INSTANCE_CNT -#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L -#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001fcL - -// VGT_GSVS_RING_OFFSET_1 -#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007fffL - -// VGT_GSVS_RING_OFFSET_2 -#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007fffL - -// VGT_GSVS_RING_OFFSET_3 -#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007fffL - -// VGT_ESGS_RING_ITEMSIZE -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL - -// VGT_GSVS_RING_ITEMSIZE -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL - -// VGT_GS_VERT_ITEMSIZE -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL - -// VGT_GS_VERT_ITEMSIZE_1 -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007fffL - -// VGT_GS_VERT_ITEMSIZE_2 -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007fffL - -// VGT_GS_VERT_ITEMSIZE_3 -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007fffL - -// WD_ENHANCE -#define WD_ENHANCE__MISC_MASK 0xffffffffL - -// VGT_OBJECT_ID -#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xffffffffL - -// VGT_INDEX_TYPE -#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L - -// VGT_NUM_INDICES -#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffffL - -// VGT_NUM_INSTANCES -#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL - -// VGT_PRIMITIVE_TYPE -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003fL - -// VGT_MAX_VTX_INDX -#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffffL - -// VGT_MIN_VTX_INDX -#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffffL - -// VGT_INDX_OFFSET -#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffffL - -// VGT_MULTI_PRIM_IB_RESET_EN -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L -#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_1 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_2 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffffL - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_3 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffffL - -// VGT_TF_RING_SIZE -#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000ffffL - -// VGT_HS_OFFCHIP_PARAM -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001ffL -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L - -// VGT_TF_MEMORY_BASE -#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffffL - -// VGT_TF_MEMORY_BASE_HI -#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000ffL - -// WD_POS_BUF_BASE -#define WD_POS_BUF_BASE__BASE_MASK 0xffffffffL - -// WD_POS_BUF_BASE_HI -#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000ffL - -// WD_CNTL_SB_BUF_BASE -#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xffffffffL - -// WD_CNTL_SB_BUF_BASE_HI -#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000ffL - -// WD_INDEX_BUF_BASE -#define WD_INDEX_BUF_BASE__BASE_MASK 0xffffffffL - -// WD_INDEX_BUF_BASE_HI -#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000ffL - -// IA_MULTI_VGT_PARAM -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000ffffL -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L -#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L - -// VGT_GSVS_RING_SIZE -#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL - -// VGT_INSTANCE_BASE_ID -#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xffffffffL - -// VGT_PERFCOUNTER0_LO -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// VGT_PERFCOUNTER1_LO -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// VGT_PERFCOUNTER2_LO -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// VGT_PERFCOUNTER3_LO -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// VGT_PERFCOUNTER0_HI -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// VGT_PERFCOUNTER1_HI -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// VGT_PERFCOUNTER2_HI -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// VGT_PERFCOUNTER3_HI -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// IA_PERFCOUNTER0_LO -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// IA_PERFCOUNTER1_LO -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// IA_PERFCOUNTER2_LO -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// IA_PERFCOUNTER3_LO -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// IA_PERFCOUNTER0_HI -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// IA_PERFCOUNTER1_HI -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// IA_PERFCOUNTER2_HI -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// IA_PERFCOUNTER3_HI -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// WD_PERFCOUNTER0_LO -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// WD_PERFCOUNTER1_LO -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// WD_PERFCOUNTER2_LO -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// WD_PERFCOUNTER3_LO -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// WD_PERFCOUNTER0_HI -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// WD_PERFCOUNTER1_HI -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// WD_PERFCOUNTER2_HI -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// WD_PERFCOUNTER3_HI -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// VGT_PERFCOUNTER_SEID_MASK -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000ffL - -// VGT_PERFCOUNTER0_SELECT -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// VGT_PERFCOUNTER1_SELECT -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// VGT_PERFCOUNTER2_SELECT -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// VGT_PERFCOUNTER3_SELECT -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// VGT_PERFCOUNTER0_SELECT1 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// VGT_PERFCOUNTER1_SELECT1 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// IA_PERFCOUNTER0_SELECT -#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// IA_PERFCOUNTER1_SELECT -#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL -#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// IA_PERFCOUNTER2_SELECT -#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL -#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// IA_PERFCOUNTER3_SELECT -#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL -#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// IA_PERFCOUNTER0_SELECT1 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// WD_PERFCOUNTER0_SELECT -#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL -#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// WD_PERFCOUNTER1_SELECT -#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL -#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// WD_PERFCOUNTER2_SELECT -#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL -#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// WD_PERFCOUNTER3_SELECT -#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL -#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// CGTT_VGT_CLK_CTRL -#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L -#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L -#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// CGTT_IA_CLK_CTRL -#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L -#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// CGTT_WD_CLK_CTRL -#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L -#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L -#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L - -// VGT_DEBUG_REG0 -#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00000001L -#define VGT_DEBUG_REG0__SPARE9_MASK 0x00000002L -#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00000004L -#define VGT_DEBUG_REG0__SPARE8_MASK 0x00000008L -#define VGT_DEBUG_REG0__SPARE7_MASK 0x00000010L -#define VGT_DEBUG_REG0__SPARE6_MASK 0x00000020L -#define VGT_DEBUG_REG0__SPARE5_MASK 0x00000040L -#define VGT_DEBUG_REG0__SPARE4_MASK 0x00000080L -#define VGT_DEBUG_REG0__pi_busy_MASK 0x00000100L -#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x00000200L -#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x00000400L -#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x00000800L -#define VGT_DEBUG_REG0__gs_busy_MASK 0x00001000L -#define VGT_DEBUG_REG0__rcm_busy_MASK 0x00002000L -#define VGT_DEBUG_REG0__tm_busy_MASK 0x00004000L -#define VGT_DEBUG_REG0__cm_busy_MASK 0x00008000L -#define VGT_DEBUG_REG0__gog_busy_MASK 0x00010000L -#define VGT_DEBUG_REG0__frmt_busy_MASK 0x00020000L -#define VGT_DEBUG_REG0__SPARE10_MASK 0x00040000L -#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x00080000L -#define VGT_DEBUG_REG0__SPARE3_MASK 0x00100000L -#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x00200000L -#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x00400000L -#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x00800000L -#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L -#define VGT_DEBUG_REG0__SPARE2_MASK 0x02000000L -#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x04000000L -#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x08000000L -#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000L -#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L -#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000L -#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000L - -// VGT_DEBUG_REG1 -#define VGT_DEBUG_REG1__SPARE9_MASK 0x00000001L -#define VGT_DEBUG_REG1__SPARE8_MASK 0x00000002L -#define VGT_DEBUG_REG1__SPARE7_MASK 0x00000004L -#define VGT_DEBUG_REG1__SPARE6_MASK 0x00000008L -#define VGT_DEBUG_REG1__SPARE5_MASK 0x00000010L -#define VGT_DEBUG_REG1__SPARE4_MASK 0x00000020L -#define VGT_DEBUG_REG1__SPARE3_MASK 0x00000040L -#define VGT_DEBUG_REG1__SPARE2_MASK 0x00000080L -#define VGT_DEBUG_REG1__SPARE1_MASK 0x00000100L -#define VGT_DEBUG_REG1__SPARE0_MASK 0x00000200L -#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x00000400L -#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x00000800L -#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x00001000L -#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x00002000L -#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x00004000L -#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00008000L -#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00010000L -#define VGT_DEBUG_REG1__SPARE12_MASK 0x00020000L -#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00040000L -#define VGT_DEBUG_REG1__SPARE11_MASK 0x00080000L -#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00100000L -#define VGT_DEBUG_REG1__SPARE10_MASK 0x00200000L -#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00400000L -#define VGT_DEBUG_REG1__SPARE23_MASK 0x00800000L -#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x01000000L -#define VGT_DEBUG_REG1__SPARE25_MASK 0x02000000L -#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x04000000L -#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x08000000L -#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000L -#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000L -#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000L -#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000L - -// VGT_DEBUG_REG2 -#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x00000001L -#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x00000002L -#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x00000004L -#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x00000008L -#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x00000020L -#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x00000040L -#define VGT_DEBUG_REG2__grpModBusy_MASK 0x00000080L -#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x00000100L -#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x00000200L -#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x00000400L -#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x00000800L -#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x00001000L -#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x00002000L -#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x00004000L -#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x00008000L -#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x00010000L -#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x00020000L -#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x00040000L -#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x00080000L -#define VGT_DEBUG_REG2__p0_rtr_MASK 0x00100000L -#define VGT_DEBUG_REG2__p1_rtr_MASK 0x00200000L -#define VGT_DEBUG_REG2__p0_dr_MASK 0x00400000L -#define VGT_DEBUG_REG2__p1_dr_MASK 0x00800000L -#define VGT_DEBUG_REG2__p0_rts_MASK 0x01000000L -#define VGT_DEBUG_REG2__p1_rts_MASK 0x02000000L -#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x04000000L -#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x08000000L -#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000L -#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000L - -// VGT_DEBUG_REG3 -#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0x00000fffL -#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x0003f000L -#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x03fc0000L -#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000L - -// VGT_DEBUG_REG4 -#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0x000000ffL -#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0x00ffff00L -#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000L -#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000L -#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000L -#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000L - -// VGT_DEBUG_REG5 -#define VGT_DEBUG_REG5__SPARE4_MASK 0x00000007L -#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0x000000f8L -#define VGT_DEBUG_REG5__SPARE3_MASK 0x00000700L -#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0x0000f800L -#define VGT_DEBUG_REG5__SPARE2_MASK 0x00070000L -#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0x00f80000L -#define VGT_DEBUG_REG5__SPARE1_MASK 0x07000000L -#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000L - -// VGT_DEBUG_REG6 -#define VGT_DEBUG_REG6__debug_BASE_MASK 0x0000ffffL -#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000L - -// VGT_DEBUG_REG7 -#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x00000001L -#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x00000002L -#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x00000004L -#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x00000008L -#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG7__SPARE_MASK 0x0000ffe0L -#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000L - -// VGT_DEBUG_REG8 -#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x00000001L -#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x00000002L -#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x00000004L -#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x00000008L -#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x00000010L -#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x00000020L -#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x00000040L -#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x00000080L -#define VGT_DEBUG_REG8__valid_r2_MASK 0x00000100L -#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x00000200L -#define VGT_DEBUG_REG8__r0_rtr_MASK 0x00000400L -#define VGT_DEBUG_REG8__r1_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG8__r2_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x00004000L -#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x00008000L -#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x00010000L -#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x00020000L -#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x00040000L -#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x00080000L -#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x00100000L -#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x00200000L -#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x00400000L -#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x00800000L -#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x01000000L -#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x02000000L -#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x04000000L -#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x08000000L -#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000L -#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000L -#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000L -#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000L - -// VGT_DEBUG_REG9 -#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x00000003L -#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x00000004L -#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x00000008L -#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x00000010L -#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x00000020L -#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x00000040L -#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x00000080L -#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x00000100L -#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x00000200L -#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x00000400L -#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x0003f800L -#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x00040000L -#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x00380000L -#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x00400000L -#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x00800000L -#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x01000000L -#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x02000000L -#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x04000000L -#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000L -#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000L -#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000L -#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000L - -// VGT_DEBUG_REG10 -#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x0000001fL -#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x00000020L -#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x00000040L -#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x00000180L -#define VGT_DEBUG_REG10__SPARE2_MASK 0x00000600L -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x00000800L -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x00001000L -#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x007fe000L -#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000L - -// VGT_DEBUG_REG11 -#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x00000001L -#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x00000002L -#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x00000004L -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x00000008L -#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x00000010L -#define VGT_DEBUG_REG11__SPARE1_MASK 0x00000020L -#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x00000040L -#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x00000080L -#define VGT_DEBUG_REG11__hold_eswave_MASK 0x00000100L -#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x00000200L -#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x00000400L -#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x00000800L -#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x00001000L -#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x00004000L -#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x00008000L -#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x00010000L -#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x00020000L -#define VGT_DEBUG_REG11__SPARE0_MASK 0x00040000L -#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x00080000L -#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x00100000L -#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x00200000L -#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x00400000L -#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x00800000L -#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x01000000L -#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x02000000L -#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x04000000L -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x08000000L -#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000L -#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000L -#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000L -#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000L - -// VGT_DEBUG_REG12 -#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x00000007L -#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x00000038L -#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x000001c0L -#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0x00000e00L -#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x00007000L -#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x00038000L -#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x001c0000L -#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0x00e00000L -#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x07000000L -#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000L -#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000L -#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000L - -// VGT_DEBUG_REG13 -#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x00000007L -#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x00000038L -#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x000001c0L -#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0x00000e00L -#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x00007000L -#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x00038000L -#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x003c0000L -#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x00400000L -#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x00800000L -#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x01000000L -#define VGT_DEBUG_REG13__SPARE1_MASK 0x02000000L -#define VGT_DEBUG_REG13__SPARE0_MASK 0x04000000L -#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000L - -// VGT_DEBUG_REG14 -#define VGT_DEBUG_REG14__SPARE3_MASK 0x0000000fL -#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x00000010L -#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x00000020L -#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x00000040L -#define VGT_DEBUG_REG14__SPARE8_MASK 0x00000180L -#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x00000200L -#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x00000400L -#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x00000800L -#define VGT_DEBUG_REG14__SPARE2_MASK 0x001ff000L -#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x00200000L -#define VGT_DEBUG_REG14__SPARE_MASK 0x01c00000L -#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x02000000L -#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x04000000L -#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x08000000L -#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000L -#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000L -#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000L -#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000L - -// VGT_DEBUG_REG15 -#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x00000001L -#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x00000002L -#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x00000004L -#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x00000008L -#define VGT_DEBUG_REG15__counters_full_MASK 0x00000010L -#define VGT_DEBUG_REG15__active_sm_q_MASK 0x000003e0L -#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x00007c00L -#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0x000f8000L -#define VGT_DEBUG_REG15__SPARE25_MASK 0x03f00000L -#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0x0c000000L -#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000L -#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000L - -// VGT_DEBUG_REG16 -#define VGT_DEBUG_REG16__gog_busy_MASK 0x00000001L -#define VGT_DEBUG_REG16__gog_state_q_MASK 0x0000000eL -#define VGT_DEBUG_REG16__r0_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG16__r1_rtr_MASK 0x00000020L -#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x00000040L -#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x00000080L -#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x00000100L -#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x00000200L -#define VGT_DEBUG_REG16__r2_rtr_MASK 0x00000400L -#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x00002000L -#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x00004000L -#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x00008000L -#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x00010000L -#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x00020000L -#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x00040000L -#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x00080000L -#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x00100000L -#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x00200000L -#define VGT_DEBUG_REG16__send_event_q_MASK 0x00400000L -#define VGT_DEBUG_REG16__SPARE24_MASK 0x00800000L -#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x01000000L -#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0x0e000000L -#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000L -#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000L -#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000L -#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000L - -// VGT_DEBUG_REG17 -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x0000003fL -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0x00000fc0L -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x0003f000L -#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000L - -// VGT_DEBUG_REG18 -#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x00000001L -#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x00000002L -#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x00000004L -#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x00000008L -#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x00000020L -#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x00000040L -#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x00000080L -#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x00000700L -#define VGT_DEBUG_REG18__valid_indices_MASK 0x00000800L -#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x00001000L -#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x00002000L -#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x00004000L -#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x00008000L -#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x00010000L -#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x00020000L -#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x00040000L -#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x00080000L -#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x00100000L -#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x00200000L -#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x00400000L -#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x00800000L -#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x07000000L -#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x08000000L -#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000L -#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000L - -// VGT_DEBUG_REG19 -#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x00000001L -#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x00000002L -#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x00000004L -#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x00000008L -#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x00000010L -#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x00000020L -#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x00000040L -#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x00000080L -#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x00000100L -#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x00000200L -#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x00000400L -#define VGT_DEBUG_REG19__hold_prim_MASK 0x00000800L -#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x00001000L -#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x00002000L -#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x00004000L -#define VGT_DEBUG_REG19__new_packet_q_MASK 0x00008000L -#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x00010000L -#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x00020000L -#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x00040000L -#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x00080000L -#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x03f00000L -#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x04000000L -#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x08000000L -#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000L -#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000L -#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000L - -// VGT_DEBUG_REG20 -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0x0000ffffL -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x00010000L -#define VGT_DEBUG_REG20__SPARE17_MASK 0x00020000L -#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x003c0000L -#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000L -#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000L -#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000L -#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000L - -// VGT_DEBUG_REG21 -#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x00000001L -#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x00000002L -#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x00000004L -#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x00000008L -#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x00000010L -#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x00000020L -#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x00000040L -#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x00000080L -#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x00000100L -#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x00000200L -#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x00000400L -#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x00000800L -#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x00002000L -#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x00004000L -#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x00008000L -#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x00010000L -#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0x000e0000L -#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x00100000L -#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x00200000L -#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x00400000L -#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x00800000L -#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x01000000L -#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x02000000L -#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x04000000L -#define VGT_DEBUG_REG21__null_r2_q_MASK 0x08000000L -#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000L -#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000L -#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000L -#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000L - -// VGT_DEBUG_REG22 -#define VGT_DEBUG_REG22__cm_state16_MASK 0x00000003L -#define VGT_DEBUG_REG22__cm_state17_MASK 0x0000000cL -#define VGT_DEBUG_REG22__cm_state18_MASK 0x00000030L -#define VGT_DEBUG_REG22__cm_state19_MASK 0x000000c0L -#define VGT_DEBUG_REG22__cm_state20_MASK 0x00000300L -#define VGT_DEBUG_REG22__cm_state21_MASK 0x00000c00L -#define VGT_DEBUG_REG22__cm_state22_MASK 0x00003000L -#define VGT_DEBUG_REG22__cm_state23_MASK 0x0000c000L -#define VGT_DEBUG_REG22__cm_state24_MASK 0x00030000L -#define VGT_DEBUG_REG22__cm_state25_MASK 0x000c0000L -#define VGT_DEBUG_REG22__cm_state26_MASK 0x00300000L -#define VGT_DEBUG_REG22__cm_state27_MASK 0x00c00000L -#define VGT_DEBUG_REG22__cm_state28_MASK 0x03000000L -#define VGT_DEBUG_REG22__cm_state29_MASK 0x0c000000L -#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000L -#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000L - -// VGT_DEBUG_REG23 -#define VGT_DEBUG_REG23__frmt_busy_MASK 0x00000001L -#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x00000002L -#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x00000004L -#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x00000008L -#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x00000020L -#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x00000040L -#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x00000080L -#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x00000100L -#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x00000200L -#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x00000400L -#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x00000800L -#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x00001000L -#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x00002000L -#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x00004000L -#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x00018000L -#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x001e0000L -#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0x00e00000L -#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000L - -// VGT_DEBUG_REG24 -#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0x00ffffffL -#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x03000000L -#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000L - -// VGT_DEBUG_REG25 -#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x03ffffffL -#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000L -#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000L -#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000L - -// VGT_DEBUG_REG26 -#define VGT_DEBUG_REG26__cm_state0_MASK 0x00000003L -#define VGT_DEBUG_REG26__cm_state1_MASK 0x0000000cL -#define VGT_DEBUG_REG26__cm_state2_MASK 0x00000030L -#define VGT_DEBUG_REG26__cm_state3_MASK 0x000000c0L -#define VGT_DEBUG_REG26__cm_state4_MASK 0x00000300L -#define VGT_DEBUG_REG26__cm_state5_MASK 0x00000c00L -#define VGT_DEBUG_REG26__cm_state6_MASK 0x00003000L -#define VGT_DEBUG_REG26__cm_state7_MASK 0x0000c000L -#define VGT_DEBUG_REG26__cm_state8_MASK 0x00030000L -#define VGT_DEBUG_REG26__cm_state9_MASK 0x000c0000L -#define VGT_DEBUG_REG26__cm_state10_MASK 0x00300000L -#define VGT_DEBUG_REG26__cm_state11_MASK 0x00c00000L -#define VGT_DEBUG_REG26__cm_state12_MASK 0x03000000L -#define VGT_DEBUG_REG26__cm_state13_MASK 0x0c000000L -#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000L -#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000L - -// VGT_DEBUG_REG27 -#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x00000001L -#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x00000002L -#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x00000004L -#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x00000008L -#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x00000020L -#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x00000040L -#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x00000080L -#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x00000300L -#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x00000400L -#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x00000800L -#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x00003000L -#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x00004000L -#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x00008000L -#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x00010000L -#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x00020000L -#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x00040000L -#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x00080000L -#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000L -#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000L - -// VGT_DEBUG_REG28 -#define VGT_DEBUG_REG28__con_state_q_MASK 0x0000000fL -#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x00000010L -#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x00000020L -#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L -#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x00000080L -#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x00000100L -#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x00000200L -#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x00000400L -#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x00004000L -#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x00008000L -#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x00010000L -#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x00020000L -#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x00040000L -#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x00080000L -#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x00100000L -#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L -#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x00400000L -#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x00800000L -#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x01000000L -#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x02000000L -#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x04000000L -#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000L -#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000L -#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000L -#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000L - -// VGT_DEBUG_REG29 -#define VGT_DEBUG_REG29__con_state_q_MASK 0x0000000fL -#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x00000010L -#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x00000020L -#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L -#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x00000080L -#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x00000100L -#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x00000200L -#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x00000400L -#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x00004000L -#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x00008000L -#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x00010000L -#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x00020000L -#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x00040000L -#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x00080000L -#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x00100000L -#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L -#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x00400000L -#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x00800000L -#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x01000000L -#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x02000000L -#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x04000000L -#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000L -#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000L -#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000L -#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000L - -// VGT_DEBUG_REG30 -#define VGT_DEBUG_REG30__te_vert_fifo_full_MASK 0x00000001L -#define VGT_DEBUG_REG30__te_pg_prim_fifo_full_MASK 0x00000002L -#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x00000004L -#define VGT_DEBUG_REG30__pipe1_dr_MASK 0x00000008L -#define VGT_DEBUG_REG30__esvert_fifo_empty_MASK 0x00000010L -#define VGT_DEBUG_REG30__gsprim_fifo_empty_MASK 0x00000020L -#define VGT_DEBUG_REG30__gswave_fifo_empty_MASK 0x00000040L -#define VGT_DEBUG_REG30__eswave_fifo_empty_MASK 0x00000080L -#define VGT_DEBUG_REG30__vgt_subgrp_grant_fifo_empty_MASK 0x00000100L -#define VGT_DEBUG_REG30__subgrp_data_fifo_empty_MASK 0x00000200L -#define VGT_DEBUG_REG30__VGT_SPI_esvert_busy_MASK 0x00000400L -#define VGT_DEBUG_REG30__VGT_SPI_gsprim_busy_MASK 0x00000800L -#define VGT_DEBUG_REG30__VGT_WD_subgrp_req_busy_MASK 0x00001000L -#define VGT_DEBUG_REG30__VGT_SPI_subgrp_busy_MASK 0x00002000L -#define VGT_DEBUG_REG30__te_pg_prim_fifo_empty_MASK 0x00004000L -#define VGT_DEBUG_REG30__te_vert_fifo_empty_MASK 0x00008000L -#define VGT_DEBUG_REG30__new_indices_p2_MASK 0x00030000L -#define VGT_DEBUG_REG30__eosg_p2_MASK 0x00040000L -#define VGT_DEBUG_REG30__SPARE_MASK 0xfff80000L - -// VGT_DEBUG_REG31 -#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x00000001L -#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x00000002L -#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x00000004L -#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x00000008L -#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x00000010L -#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x00000020L -#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x00000040L -#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x00000080L -#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x00000100L -#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x00000200L -#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x00000400L -#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x00000800L -#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x00004000L -#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x00008000L -#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x00010000L -#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x00020000L -#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x00040000L -#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x00080000L -#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x00100000L -#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x00200000L -#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x00400000L -#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x00800000L -#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x01000000L -#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x02000000L -#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x04000000L -#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x08000000L -#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000L -#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000L -#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000L -#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000L - -// VGT_DEBUG_REG32 -#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x00000001L -#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x00000002L -#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x00000004L -#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x00000008L -#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x00000010L -#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x00000020L -#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x00000040L -#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x00000080L -#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x00000100L -#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x00000200L -#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x00000400L -#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x00000800L -#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x00003000L -#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x00004000L -#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x00008000L -#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x00010000L -#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x00020000L -#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x00040000L -#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x00080000L -#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x00100000L -#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x00200000L -#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x00400000L -#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x00800000L -#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x01000000L -#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x02000000L -#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x04000000L -#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000L - -// VGT_DEBUG_REG33 -#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x00000001L -#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x00000002L -#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x00000004L -#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x00000008L -#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x00000010L -#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x00000020L -#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x00000040L -#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x00000080L -#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x00000100L -#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x00000200L -#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x00000400L -#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x00000800L -#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x00002000L -#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x00004000L -#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x00008000L -#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x00010000L -#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x00020000L -#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x00040000L -#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x00080000L -#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x00100000L -#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x00200000L -#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x00400000L -#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x00800000L -#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x03000000L -#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0x0c000000L -#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000L -#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000L -#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000L -#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000L - -// VGT_DEBUG_REG34 -#define VGT_DEBUG_REG34__con_state_q_MASK 0x0000000fL -#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x00000010L -#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x00000020L -#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L -#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x00000080L -#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x00000100L -#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x00000200L -#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x00000400L -#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x00000800L -#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x00001000L -#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x00002000L -#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x00004000L -#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x00008000L -#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x00010000L -#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x00020000L -#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x00040000L -#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x00080000L -#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x00100000L -#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L -#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x00400000L -#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x00800000L -#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x01000000L -#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x02000000L -#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x04000000L -#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x08000000L -#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000L -#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000L -#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000L -#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000L - -// VGT_DEBUG_REG36 -#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffffL - -// IA_DEBUG_REG0 -#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x00000001L -#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x00000002L -#define IA_DEBUG_REG0__ia_busy_MASK 0x00000004L -#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x00000008L -#define IA_DEBUG_REG0__SPARE0_MASK 0x00000010L -#define IA_DEBUG_REG0__dma_req_busy_MASK 0x00000020L -#define IA_DEBUG_REG0__dma_busy_MASK 0x00000040L -#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x00000080L -#define IA_DEBUG_REG0__grp_busy_MASK 0x00000100L -#define IA_DEBUG_REG0__SPARE1_MASK 0x00000200L -#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x00000400L -#define IA_DEBUG_REG0__grp_dma_read_MASK 0x00000800L -#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x00001000L -#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x00002000L -#define IA_DEBUG_REG0__SPARE2_MASK 0x00ffc000L -#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L -#define IA_DEBUG_REG0__core_clk_busy_MASK 0x02000000L -#define IA_DEBUG_REG0__SPARE3_MASK 0x04000000L -#define IA_DEBUG_REG0__SPARE4_MASK 0x08000000L -#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000L -#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L -#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000L -#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000L - -// IA_DEBUG_REG1 -#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x00000001L -#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x00000002L -#define IA_DEBUG_REG1__start_new_packet_MASK 0x00000004L -#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x00000008L -#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x00000010L -#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x00000060L -#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x00000080L -#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x00000100L -#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x00000200L -#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x00000400L -#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x00000800L -#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x00001000L -#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x00002000L -#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x00004000L -#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x00008000L -#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x00010000L -#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x00020000L -#define IA_DEBUG_REG1__stage2_dr_MASK 0x00040000L -#define IA_DEBUG_REG1__stage2_rtr_MASK 0x00080000L -#define IA_DEBUG_REG1__stage3_dr_MASK 0x00100000L -#define IA_DEBUG_REG1__stage3_rtr_MASK 0x00200000L -#define IA_DEBUG_REG1__stage4_dr_MASK 0x00400000L -#define IA_DEBUG_REG1__stage4_rtr_MASK 0x00800000L -#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x01000000L -#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x02000000L -#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x04000000L -#define IA_DEBUG_REG1__grp_dma_read_MASK 0x08000000L -#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000L -#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000L -#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000L -#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000L - -// IA_DEBUG_REG2 -#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x00000001L -#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x00000002L -#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x00000004L -#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x00000008L -#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x00000010L -#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x00000060L -#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x00000080L -#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x00000100L -#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x00000200L -#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x00000400L -#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x00000800L -#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x00001000L -#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x00002000L -#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x00004000L -#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x00008000L -#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x00010000L -#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x00020000L -#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x00040000L -#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x00080000L -#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x00100000L -#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x00200000L -#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x00400000L -#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x00800000L -#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x01000000L -#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x02000000L -#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x04000000L -#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x08000000L -#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000L -#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000L -#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000L -#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000L - -// IA_DEBUG_REG3 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x00000001L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x00000002L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x00000004L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x00000008L -#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x00000010L -#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x00000020L -#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x00000040L -#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x00000080L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x00000100L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x00000200L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x00000400L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x00000800L -#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x00001000L -#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x00002000L -#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x00004000L -#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x00008000L -#define IA_DEBUG_REG3__pipe0_dr_MASK 0x00010000L -#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x00020000L -#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x00040000L -#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x00080000L -#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x00100000L -#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x00200000L -#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x00400000L -#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x00800000L -#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x03000000L -#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x04000000L -#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x08000000L -#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000L -#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000L -#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000L -#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000L - -// IA_DEBUG_REG4 -#define IA_DEBUG_REG4__pipe0_dr_MASK 0x00000001L -#define IA_DEBUG_REG4__pipe1_dr_MASK 0x00000002L -#define IA_DEBUG_REG4__pipe2_dr_MASK 0x00000004L -#define IA_DEBUG_REG4__pipe3_dr_MASK 0x00000008L -#define IA_DEBUG_REG4__pipe4_dr_MASK 0x00000010L -#define IA_DEBUG_REG4__pipe5_dr_MASK 0x00000020L -#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x00000040L -#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x00000080L -#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x00000100L -#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x00000200L -#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x00000400L -#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x00000800L -#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x00001000L -#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x00002000L -#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x00004000L -#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x00008000L -#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x00010000L -#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0x000e0000L -#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x00100000L -#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0x00e00000L -#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x01000000L -#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x02000000L -#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0x0c000000L -#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000L -#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000L -#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000L -#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000L - -// IA_DEBUG_REG5 -#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0x0000ffffL -#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000L -#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000L -#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000L - -// IA_DEBUG_REG6 -#define IA_DEBUG_REG6__current_shift_q_MASK 0x0000000fL -#define IA_DEBUG_REG6__current_stride_pre_MASK 0x000000f0L -#define IA_DEBUG_REG6__current_stride_q_MASK 0x00001f00L -#define IA_DEBUG_REG6__first_group_partial_MASK 0x00002000L -#define IA_DEBUG_REG6__second_group_partial_MASK 0x00004000L -#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x00008000L -#define IA_DEBUG_REG6__next_stride_q_MASK 0x001f0000L -#define IA_DEBUG_REG6__next_group_partial_MASK 0x00200000L -#define IA_DEBUG_REG6__after_group_partial_MASK 0x00400000L -#define IA_DEBUG_REG6__extract_group_MASK 0x00800000L -#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000L - -// IA_DEBUG_REG7 -#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0x0000000fL -#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0x000000f0L -#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0x00000f00L -#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0x0000f000L -#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0x000f0000L -#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x00700000L -#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x00800000L -#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x01000000L -#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x02000000L -#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x04000000L -#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x08000000L -#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000L -#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000L -#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000L -#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000L - -// IA_DEBUG_REG8 -#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x0000001fL -#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x00000020L -#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x00000040L -#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x00000080L -#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x00000100L -#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x00000200L -#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x00000400L -#define IA_DEBUG_REG8__grp_continued_MASK 0x00000800L -#define IA_DEBUG_REG8__grp_state_sel_MASK 0x00007000L -#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x001f8000L -#define IA_DEBUG_REG8__grp_output_path_MASK 0x00e00000L -#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x01000000L -#define IA_DEBUG_REG8__grp_eop_MASK 0x02000000L -#define IA_DEBUG_REG8__grp_eopg_MASK 0x04000000L -#define IA_DEBUG_REG8__grp_event_flag_MASK 0x08000000L -#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000L - -// IA_DEBUG_REG9 -#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x00000001L -#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x00000002L -#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x00000004L -#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x00000008L -#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x00000010L -#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x00000020L -#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x00000040L -#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x00000080L -#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x00000100L -#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x00000200L -#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x00000400L -#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x00000800L -#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x00001000L -#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x00002000L -#define IA_DEBUG_REG9__SPARE0_MASK 0x00004000L -#define IA_DEBUG_REG9__SPARE1_MASK 0x00008000L -#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x00010000L -#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x00020000L -#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x00040000L -#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x00080000L -#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000L - -// WD_DEBUG_REG0 -#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x00000001L -#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x00000002L -#define WD_DEBUG_REG0__wd_busy_MASK 0x00000004L -#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x00000008L -#define WD_DEBUG_REG0__rbiu_busy_MASK 0x00000010L -#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x00000020L -#define WD_DEBUG_REG0__spl_di_busy_MASK 0x00000040L -#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x00000080L -#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x00000100L -#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x00000200L -#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x00000400L -#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x00000800L -#define WD_DEBUG_REG0__SPARE2_MASK 0x00001000L -#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x00002000L -#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x00004000L -#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x00008000L -#define WD_DEBUG_REG0__SPARE3_MASK 0x00010000L -#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x00020000L -#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x00040000L -#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x00080000L -#define WD_DEBUG_REG0__se0_synced_q_MASK 0x00100000L -#define WD_DEBUG_REG0__se1_synced_q_MASK 0x00200000L -#define WD_DEBUG_REG0__se2_synced_q_MASK 0x00400000L -#define WD_DEBUG_REG0__se3_synced_q_MASK 0x00800000L -#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L -#define WD_DEBUG_REG0__input_clk_busy_MASK 0x02000000L -#define WD_DEBUG_REG0__core_clk_busy_MASK 0x04000000L -#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x08000000L -#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000L -#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000L -#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000L -#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000L - -// WD_DEBUG_REG1 -#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x00000001L -#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x00000002L -#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x00000004L -#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x00000008L -#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x00000010L -#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x00000020L -#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x00000040L -#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x00000080L -#define WD_DEBUG_REG1__SPARE0_MASK 0x00000100L -#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x00000200L -#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x00000400L -#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x00000800L -#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x0001f000L -#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0x000e0000L -#define WD_DEBUG_REG1__free_cnt_q_MASK 0x03f00000L -#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x04000000L -#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x08000000L -#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000L -#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000L -#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000L -#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000L - -// WD_DEBUG_REG2 -#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x00000001L -#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x00000002L -#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x00000004L -#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x00000008L -#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x00000010L -#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x00000020L -#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x00000040L -#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x00000080L -#define WD_DEBUG_REG2__SPARE0_MASK 0x00000100L -#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x00000200L -#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x00000400L -#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x00000800L -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x0001f000L -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0x000e0000L -#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x03f00000L -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x04000000L -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x08000000L -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000L -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000L -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000L -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000L - -// WD_DEBUG_REG3 -#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x00000001L -#define WD_DEBUG_REG3__SPARE0_MASK 0x00000002L -#define WD_DEBUG_REG3__pipe0_dr_MASK 0x00000004L -#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x00000008L -#define WD_DEBUG_REG3__pipe1_dr_MASK 0x00000010L -#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x00000020L -#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x00000040L -#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x00000080L -#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x00000300L -#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x00000400L -#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x00000800L -#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x00001000L -#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x00002000L -#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x00004000L -#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x00008000L -#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x00010000L -#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x00020000L -#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x00040000L -#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x00080000L -#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x00100000L -#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x00200000L -#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x00400000L -#define WD_DEBUG_REG3__SPARE1_MASK 0x00800000L -#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x01000000L -#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x02000000L -#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x04000000L -#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x08000000L -#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000L -#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000L -#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000L -#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000L - -// WD_DEBUG_REG4 -#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x00000001L -#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x00000002L -#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x00000004L -#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x00000008L -#define WD_DEBUG_REG4__pipe0_dr_MASK 0x00000010L -#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x00000020L -#define WD_DEBUG_REG4__pipe1_dr_MASK 0x00000040L -#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x00000080L -#define WD_DEBUG_REG4__pipe2_dr_MASK 0x00000100L -#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x00000200L -#define WD_DEBUG_REG4__pipe3_ld_MASK 0x00000400L -#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x00000800L -#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x00001000L -#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x00002000L -#define WD_DEBUG_REG4__di_type_p0_MASK 0x0000c000L -#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x00070000L -#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x00080000L -#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x00100000L -#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x00200000L -#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x00400000L -#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x00800000L -#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x01000000L -#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x02000000L -#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x04000000L -#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x08000000L -#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000L -#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000L -#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000L -#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000L - -// WD_DEBUG_REG5 -#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x00000001L -#define WD_DEBUG_REG5__SPARE0_MASK 0x00000002L -#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x00000004L -#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x00000008L -#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x00000010L -#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x00000020L -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x00000040L -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x00000080L -#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x00000300L -#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x00000400L -#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x00000800L -#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x00001000L -#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x00002000L -#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x00004000L -#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x00008000L -#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x00010000L -#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x00020000L -#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x00040000L -#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x00080000L -#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x00100000L -#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x00200000L -#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x00400000L -#define WD_DEBUG_REG5__SPARE1_MASK 0x00800000L -#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x01000000L -#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x02000000L -#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x04000000L -#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x08000000L -#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000L -#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000L -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000L -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000L - -// WD_DEBUG_REG6 -#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffffL - -// WD_DEBUG_REG7 -#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x00000001L -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x00000002L -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x00000004L -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x00000008L -#define WD_DEBUG_REG7__SPARE0_MASK 0x000000f0L -#define WD_DEBUG_REG7__SPARE1_MASK 0x00000f00L -#define WD_DEBUG_REG7__SPARE2_MASK 0x0000f000L -#define WD_DEBUG_REG7__SPARE3_MASK 0x000f0000L -#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x00100000L -#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x00200000L -#define WD_DEBUG_REG7__SPARE4_MASK 0x0fc00000L -#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000L -#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000L -#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000L -#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000L - -// WD_DEBUG_REG8 -#define WD_DEBUG_REG8__pipe0_dr_MASK 0x00000001L -#define WD_DEBUG_REG8__pipe1_dr_MASK 0x00000002L -#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x00000004L -#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x00000008L -#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x00000010L -#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x00000020L -#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x00000040L -#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x00000080L -#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x00000100L -#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x00000200L -#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x00000400L -#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x00000800L -#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x0003f000L -#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x00040000L -#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x00080000L -#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x07f00000L -#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x08000000L -#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000L -#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000L -#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000L -#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000L - -// WD_DEBUG_REG9 -#define WD_DEBUG_REG9__pipe0_dr_MASK 0x00000001L -#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x00000002L -#define WD_DEBUG_REG9__pipe2_dr_MASK 0x00000004L -#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x00000008L -#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x00000010L -#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x00000020L -#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x00000040L -#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x00000080L -#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x00000100L -#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x00000200L -#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x00000400L -#define WD_DEBUG_REG9__SPARE0_MASK 0x0000f800L -#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x00070000L -#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x00080000L -#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0x00f00000L -#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x01000000L -#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x02000000L -#define WD_DEBUG_REG9__mem_is_even_MASK 0x04000000L -#define WD_DEBUG_REG9__SPARE1_MASK 0x08000000L -#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000L -#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000L -#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000L - -// WD_DEBUG_REG10 -#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x00000001L -#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x00000002L -#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x00000004L -#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x00000008L -#define WD_DEBUG_REG10__pipe0_dr_MASK 0x00000010L -#define WD_DEBUG_REG10__pipe1_dr_MASK 0x00000020L -#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x00000040L -#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x00000080L -#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x00000100L -#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x00000200L -#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x00000400L -#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x00000800L -#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x00001000L -#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x00002000L -#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x00004000L -#define WD_DEBUG_REG10__eop_p1_q_MASK 0x00008000L -#define WD_DEBUG_REG10__patch_accum_q_MASK 0x00ff0000L -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x01000000L -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x02000000L -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x04000000L -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x08000000L -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000L -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000L -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000L -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000L - -// WD_DEBUG_REG11 -#define WD_DEBUG_REG11__WD_SE0VGT_subgrp_grant_busy_MASK 0x00000001L -#define WD_DEBUG_REG11__WD_SE1VGT_subgrp_grant_busy_MASK 0x00000002L -#define WD_DEBUG_REG11__WD_SE2VGT_subgrp_grant_busy_MASK 0x00000004L -#define WD_DEBUG_REG11__WD_SE3VGT_subgrp_grant_busy_MASK 0x00000008L -#define WD_DEBUG_REG11__WD_SE0PA_sideband_active_busy_MASK 0x00000010L -#define WD_DEBUG_REG11__WD_SE1PA_sideband_active_busy_MASK 0x00000020L -#define WD_DEBUG_REG11__WD_SE2PA_sideband_active_busy_MASK 0x00000040L -#define WD_DEBUG_REG11__WD_SE3PA_sideband_active_busy_MASK 0x00000080L -#define WD_DEBUG_REG11__wd_sm_rm_req_valid_MASK 0x00000100L -#define WD_DEBUG_REG11__wd_sm_rm_req_eopg_MASK 0x00000200L -#define WD_DEBUG_REG11__wd_sm_rm_req_null_MASK 0x00000400L -#define WD_DEBUG_REG11__wd_sm_rm_req_state_sel_MASK 0x00003800L -#define WD_DEBUG_REG11__wd_sm_rm_req_eop_MASK 0x00004000L -#define WD_DEBUG_REG11__wd_sm_rm_req_is_event_MASK 0x00008000L -#define WD_DEBUG_REG11__curr_fe_id_MASK 0x00030000L -#define WD_DEBUG_REG11__SE0_subgrp_fifo_empty_MASK 0x00040000L -#define WD_DEBUG_REG11__SE2_subgrp_fifo_empty_MASK 0x00080000L -#define WD_DEBUG_REG11__SE1_subgrp_fifo_empty_MASK 0x00100000L -#define WD_DEBUG_REG11__SE3_subgrp_fifo_empty_MASK 0x00200000L -#define WD_DEBUG_REG11__SE0_subgrp_fifo_full_MASK 0x00400000L -#define WD_DEBUG_REG11__SE1_subgrp_fifo_full_MASK 0x00800000L -#define WD_DEBUG_REG11__SE2_subgrp_fifo_full_MASK 0x01000000L -#define WD_DEBUG_REG11__SE3_subgrp_fifo_full_MASK 0x02000000L -#define WD_DEBUG_REG11__SPARE_MASK 0xfc000000L - -// WD_DEBUG_REG12 -#define WD_DEBUG_REG12__wd_csbm_sm_max_waves_MASK 0x00000007L -#define WD_DEBUG_REG12__SPARE1_MASK 0x00000038L -#define WD_DEBUG_REG12__wd_csbm_sm_ordered_id_mode_MASK 0x00000040L -#define WD_DEBUG_REG12__wd_csbm_sm_null_subgrp_MASK 0x00000080L -#define WD_DEBUG_REG12__wd_csbm_sm_curr_fe_id_MASK 0x00000300L -#define WD_DEBUG_REG12__wd_csbm_sm_fe_id_MASK 0x00000c00L -#define WD_DEBUG_REG12__SPARE0_MASK 0xfffff000L - -// WD_DEBUG_REG13 -#define WD_DEBUG_REG13__decr_p2_MASK 0x00000001L -#define WD_DEBUG_REG13__pe0_ld_MASK 0x00000002L -#define WD_DEBUG_REG13__ptpos0_ld_MASK 0x00000004L -#define WD_DEBUG_REG13__ptpar0_ld_MASK 0x00000008L -#define WD_DEBUG_REG13__pipe0_ld_MASK 0x00000010L -#define WD_DEBUG_REG13__pipe1_ld_MASK 0x00000020L -#define WD_DEBUG_REG13__pipe2_ld_MASK 0x00000040L -#define WD_DEBUG_REG13__SPARE0_MASK 0xffffff80L - -// CC_RB_REDUNDANCY -#define CC_RB_REDUNDANCY__WRITE_DIS_MASK 0x00000001L -#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L -#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L - -// CC_RB_BACKEND_DISABLE -#define CC_RB_BACKEND_DISABLE__WRITE_DIS_MASK 0x00000001L -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L - -// GC_USER_RB_REDUNDANCY -#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L -#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L - -// GC_USER_RB_BACKEND_DISABLE -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L - -// GB_ADDR_CONFIG -#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000c0L -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00e00000L -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L -#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0c000000L -#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L -#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L - -// GB_ADDR_CONFIG_READ -#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000c0L -#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L -#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00e00000L -#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L -#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0c000000L -#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L -#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L -#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L - -// GB_BACKEND_MAP -#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffffL - -// GB_GPU_ID -#define GB_GPU_ID__GPU_ID_MASK 0x0000000fL - -// CC_RB_DAISY_CHAIN -#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL -#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L -#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L -#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L -#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L -#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L -#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L -#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L - -// GB_TILE_MODE0 -#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE1 -#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE2 -#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE3 -#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE4 -#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE5 -#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE6 -#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE7 -#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE8 -#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE9 -#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE10 -#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE11 -#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE12 -#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE13 -#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE14 -#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE15 -#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE16 -#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE17 -#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE18 -#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE19 -#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE20 -#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE21 -#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE22 -#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE23 -#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE24 -#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE25 -#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE26 -#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE27 -#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE28 -#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE29 -#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE30 -#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_TILE_MODE31 -#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003cL -#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007c0L -#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01c00000L -#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L - -// GB_MACROTILE_MODE0 -#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE1 -#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE2 -#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE3 -#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE4 -#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE5 -#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE6 -#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE7 -#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE8 -#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE9 -#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE10 -#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE11 -#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE12 -#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE13 -#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE14 -#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000c0L - -// GB_MACROTILE_MODE15 -#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000cL -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000c0L - -// GB_EDC_MODE -#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L -#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L -#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L -#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L -#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L -#define GB_EDC_MODE__BYPASS_MASK 0x80000000L - -// CC_GC_EDC_CONFIG -#define CC_GC_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L -#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L - -// RAS_SIGNATURE_CONTROL -#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L - -// RAS_SIGNATURE_MASK -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffffL - -// RAS_SX_SIGNATURE0 -#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_SX_SIGNATURE1 -#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffffL - -// RAS_SX_SIGNATURE2 -#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffffL - -// RAS_SX_SIGNATURE3 -#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffffL - -// RAS_DB_SIGNATURE0 -#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_PA_SIGNATURE0 -#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_VGT_SIGNATURE0 -#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_SQ_SIGNATURE0 -#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE0 -#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE1 -#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE2 -#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE3 -#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE4 -#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE5 -#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE6 -#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffffL - -// RAS_SC_SIGNATURE7 -#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffffL - -// RAS_IA_SIGNATURE0 -#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_IA_SIGNATURE1 -#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffffL - -// RAS_SPI_SIGNATURE0 -#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_SPI_SIGNATURE1 -#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL - -// RAS_TA_SIGNATURE0 -#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_TD_SIGNATURE0 -#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_CB_SIGNATURE0 -#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_BCI_SIGNATURE0 -#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL - -// RAS_BCI_SIGNATURE1 -#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL - -// RAS_TA_SIGNATURE1 -#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffffL - -// TD_CNTL -#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L -#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L -#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L -#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L -#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L -#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L -#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L -#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L -#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L -#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L -#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L -#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L - -// TD_STATUS -#define TD_STATUS__BUSY_MASK 0x80000000L - -// TD_DEBUG_INDEX -#define TD_DEBUG_INDEX__INDEX_MASK 0x0000001fL - -// TD_DEBUG_DATA -#define TD_DEBUG_DATA__DATA_MASK 0xffffffffL - -// TD_DSM_CNTL -#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000c0L -#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L - -// TD_DSM_CNTL2 -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xfc000000L - -// TD_SCRATCH -#define TD_SCRATCH__SCRATCH_MASK 0xffffffffL - -// TA_CNTL -#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007fL -#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001e00L -#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000e000L -#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001f0000L -#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000L - -// TA_CNTL_AUX -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L -#define TA_CNTL_AUX__RESERVED_MASK 0x0000000eL -#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L -#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L -#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L -#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L -#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000c00L -#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L -#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L -#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L -#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L -#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L -#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L -#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L -#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L -#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L -#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L -#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L -#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L -#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L -#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L -#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L -#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L -#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xc0000000L - -// TA_RESERVED_010C -#define TA_RESERVED_010C__Unused_MASK 0xffffffffL - -// TA_GRAD_ADJ -#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000ffL -#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000ff00L -#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00ff0000L -#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xff000000L - -// TA_STATUS -#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L -#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L -#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L -#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L -#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L -#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L -#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L -#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L -#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L -#define TA_STATUS__IN_BUSY_MASK 0x01000000L -#define TA_STATUS__FG_BUSY_MASK 0x02000000L -#define TA_STATUS__LA_BUSY_MASK 0x04000000L -#define TA_STATUS__FL_BUSY_MASK 0x08000000L -#define TA_STATUS__TA_BUSY_MASK 0x10000000L -#define TA_STATUS__FA_BUSY_MASK 0x20000000L -#define TA_STATUS__AL_BUSY_MASK 0x40000000L -#define TA_STATUS__BUSY_MASK 0x80000000L - -// TA_DEBUG_INDEX -#define TA_DEBUG_INDEX__INDEX_MASK 0x0000001fL - -// TA_DEBUG_DATA -#define TA_DEBUG_DATA__DATA_MASK 0xffffffffL - -// TA_SCRATCH -#define TA_SCRATCH__SCRATCH_MASK 0xffffffffL - -// TCP_INVALIDATE -#define TCP_INVALIDATE__START_MASK 0x00000001L - -// TCP_STATUS -#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L -#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L -#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L -#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L -#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L -#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L -#define TCP_STATUS__READ_BUSY_MASK 0x00000040L -#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L -#define TCP_STATUS__VM_BUSY_MASK 0x00000100L - -// TCP_CNTL -#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L -#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L -#define TCP_CNTL__L1_SIZE_MASK 0x0000000cL -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001f8000L -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0fc00000L -#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L -#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L -#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L - -// TCP_CHAN_STEER_LO -#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000fL -#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000f0L -#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000f00L -#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000f000L -#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000f0000L -#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00f00000L -#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0f000000L -#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000L - -// TCP_CHAN_STEER_HI -#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000fL -#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000f0L -#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000f00L -#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000f000L -#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000f0000L -#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00f00000L -#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0f000000L -#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000L - -// TCP_ADDR_CONFIG -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000fL -#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L -#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001c0L -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L - -// TCP_CREDIT -#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003ffL -#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007f0000L -#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000L - -// TCP_DEBUG_INDEX -#define TCP_DEBUG_INDEX__INDEX_MASK 0x0000001fL - -// TCP_DEBUG_DATA -#define TCP_DEBUG_DATA__DATA_MASK 0x00ffffffL - -// TCP_BUFFER_ADDR_HASH_CNTL -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L - -// TCP_EDC_CNT -#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000ffL -#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000ff00L -#define TCP_EDC_CNT__DED_COUNT_MASK 0x00ff0000L - -// TC_CFG_L1_LOAD_POLICY0 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000cL -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000c0L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000c00L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000c000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000c0000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00c00000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0c000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000L - -// TC_CFG_L1_LOAD_POLICY1 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000cL -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000c0L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000c00L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000c000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000c0000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00c00000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0c000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000L - -// TC_CFG_L1_STORE_POLICY -#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L -#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L -#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L -#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L -#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L -#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L -#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L -#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L -#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L -#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L -#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L -#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L -#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L -#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L -#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L -#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L -#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L -#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L -#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L -#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L -#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L -#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L -#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L -#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L -#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L - -// TC_CFG_L2_LOAD_POLICY0 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000cL -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000c0L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000c00L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000c000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000c0000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00c00000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0c000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000L - -// TC_CFG_L2_LOAD_POLICY1 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000cL -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000c0L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000c00L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000c000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000c0000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00c00000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0c000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000L - -// TC_CFG_L2_STORE_POLICY0 -#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000cL -#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000c0L -#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000c00L -#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000c000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000c0000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00c00000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0c000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000L - -// TC_CFG_L2_STORE_POLICY1 -#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000cL -#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000c0L -#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000c00L -#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000c000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000c0000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00c00000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0c000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000L - -// TC_CFG_L2_ATOMIC_POLICY -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000cL -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000c0L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000c00L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000c000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000c0000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00c00000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0c000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000L - -// TC_CFG_L1_VOLATILE -#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000fL - -// TC_CFG_L2_VOLATILE -#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000fL - -// TCI_STATUS -#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L - -// TCI_CNTL_1 -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000ffffL -#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00ff0000L -#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000L - -// TCI_CNTL_2 -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L -#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001feL - -// TCP_WATCH0_ADDR_H -#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000ffffL - -// TCP_WATCH1_ADDR_H -#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000ffffL - -// TCP_WATCH2_ADDR_H -#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000ffffL - -// TCP_WATCH3_ADDR_H -#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000ffffL - -// TCP_WATCH0_ADDR_L -#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0L - -// TCP_WATCH1_ADDR_L -#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0L - -// TCP_WATCH2_ADDR_L -#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0L - -// TCP_WATCH3_ADDR_L -#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0L - -// TCP_WATCH0_CNTL -#define TCP_WATCH0_CNTL__MASK_MASK 0x00ffffffL -#define TCP_WATCH0_CNTL__VMID_MASK 0x0f000000L -#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L - -// TCP_WATCH1_CNTL -#define TCP_WATCH1_CNTL__MASK_MASK 0x00ffffffL -#define TCP_WATCH1_CNTL__VMID_MASK 0x0f000000L -#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L - -// TCP_WATCH2_CNTL -#define TCP_WATCH2_CNTL__MASK_MASK 0x00ffffffL -#define TCP_WATCH2_CNTL__VMID_MASK 0x0f000000L -#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L - -// TCP_WATCH3_CNTL -#define TCP_WATCH3_CNTL__MASK_MASK 0x00ffffffL -#define TCP_WATCH3_CNTL__VMID_MASK 0x0f000000L -#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L - -// TCP_GATCL1_CNTL -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L -#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000L - -// TCP_ATC_EDC_GATCL1_CNT -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000ffL - -// TCP_GATCL1_DSM_CNTL -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L - -// TCP_CNTL2 -#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000ffL - -// TCP_UTCL1_CNTL1 -#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L -#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000ff80L -#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000L - -// TCP_UTCL1_CNTL2 -#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000ffL -#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L -#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L - -// TCP_UTCL1_STATUS -#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L - -// TCP_PERFCOUNTER_FILTER -#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L -#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L -#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001cL -#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007e0L -#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L -#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000f8000L -#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L -#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01c00000L -#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L -#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L -#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L -#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L - -// TCP_PERFCOUNTER_FILTER_EN -#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L -#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L -#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L -#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L -#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L -#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L -#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L -#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L -#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L -#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L -#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L -#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L - -// TA_BC_BASE_ADDR -#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL - -// TA_BC_BASE_ADDR_HI -#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL - -// TA_CS_BC_BASE_ADDR -#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL - -// TA_CS_BC_BASE_ADDR_HI -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL - -// TA_GRAD_ADJ_UCONFIG -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000ffL -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000ff00L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00ff0000L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xff000000L - -// TD_PERFCOUNTER0_LO -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TD_PERFCOUNTER1_LO -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TD_PERFCOUNTER0_HI -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TD_PERFCOUNTER1_HI -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TA_PERFCOUNTER0_LO -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TA_PERFCOUNTER1_LO -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TA_PERFCOUNTER0_HI -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TA_PERFCOUNTER1_HI -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCP_PERFCOUNTER0_LO -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCP_PERFCOUNTER1_LO -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCP_PERFCOUNTER2_LO -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCP_PERFCOUNTER3_LO -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCP_PERFCOUNTER0_HI -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCP_PERFCOUNTER1_HI -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCP_PERFCOUNTER2_HI -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCP_PERFCOUNTER3_HI -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TD_PERFCOUNTER0_SELECT -#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// TD_PERFCOUNTER1_SELECT -#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003fc00L -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// TD_PERFCOUNTER0_SELECT1 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// TA_PERFCOUNTER0_SELECT -#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// TA_PERFCOUNTER1_SELECT -#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003fc00L -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// TA_PERFCOUNTER0_SELECT1 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// TCP_PERFCOUNTER0_SELECT -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCP_PERFCOUNTER1_SELECT -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCP_PERFCOUNTER0_SELECT1 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// TCP_PERFCOUNTER1_SELECT1 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// TCP_PERFCOUNTER2_SELECT -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCP_PERFCOUNTER3_SELECT -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// TD_CGTT_CTRL -#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL -#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// TA_CGTT_CTRL -#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL -#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// CGTT_TCPI_CLK_CTRL -#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000f000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// CGTT_TCPF_CLK_CTRL -#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000f000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// CGTT_TCI_CLK_CTRL -#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// TCC_CTRL -#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L -#define TCC_CTRL__RATE_MASK 0x0000000cL -#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000f0L -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000f00L -#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000f000L -#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000f0000L -#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L -#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L -#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0c000000L -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000L - -// TCC_CTRL2 -#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000fL - -// TCC_EDC_CNT -#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L -#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000cL -#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L -#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000c0L -#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L -#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000c00L -#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L -#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000c000L -#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L -#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000c0000L -#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L -#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00c00000L -#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L -#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0c000000L -#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L -#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xc0000000L - -// TCC_EDC_CNT2 -#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L -#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000cL -#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L -#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000c0L -#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L - -// TCC_REDUNDANCY -#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L -#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L - -// TCC_EXE_DISABLE -#define TCC_EXE_DISABLE__WRITE_DIS_MASK 0x00000001L -#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L - -// TCC_DSM_CNTL -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000c0L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000c0000L -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L - -// TCC_DSM_CNTLA -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000c0L -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000c0000L -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L - -// TCC_DSM_CNTL2 -#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000c0000L -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L -#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L -#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xfc000000L - -// TCC_DSM_CNTL2A -#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L -#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000c0000L -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L -#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L - -// TCC_DSM_CNTL2B -#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L - -// TCC_WBINVL2 -#define TCC_WBINVL2__DONE_MASK 0x00000010L - -// TCC_SOFT_RESET -#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L - -// TCA_CTRL -#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000fL -#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L -#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L -#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L -#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L - -// TCA_BURST_MASK -#define TCA_BURST_MASK__ADDR_MASK_MASK 0xffffffffL - -// TCA_BURST_CTRL -#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L -#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L -#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L -#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L -#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L -#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L -#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L -#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L -#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L -#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L -#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L -#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L -#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L - -// TCA_DSM_CNTL -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L - -// TCA_DSM_CNTL2 -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xfc000000L - -// TCA_EDC_CNT -#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L -#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000cL - -// TCC_PERFCOUNTER0_LO -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCC_PERFCOUNTER1_LO -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCC_PERFCOUNTER2_LO -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCC_PERFCOUNTER3_LO -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCC_PERFCOUNTER0_HI -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCC_PERFCOUNTER1_HI -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCC_PERFCOUNTER2_HI -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCC_PERFCOUNTER3_HI -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCA_PERFCOUNTER0_LO -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCA_PERFCOUNTER1_LO -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCA_PERFCOUNTER2_LO -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCA_PERFCOUNTER3_LO -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// TCA_PERFCOUNTER0_HI -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCA_PERFCOUNTER1_HI -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCA_PERFCOUNTER2_HI -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCA_PERFCOUNTER3_HI -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// TCC_PERFCOUNTER0_SELECT -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCC_PERFCOUNTER1_SELECT -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCC_PERFCOUNTER0_SELECT1 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L - -// TCC_PERFCOUNTER1_SELECT1 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L - -// TCC_PERFCOUNTER2_SELECT -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCC_PERFCOUNTER3_SELECT -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCA_PERFCOUNTER0_SELECT -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCA_PERFCOUNTER1_SELECT -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCA_PERFCOUNTER0_SELECT1 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L - -// TCA_PERFCOUNTER1_SELECT1 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L - -// TCA_PERFCOUNTER2_SELECT -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCA_PERFCOUNTER3_SELECT -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003ffL -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// TCC_CGTT_SCLK_CTRL -#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// TCA_CGTT_SCLK_CTRL -#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// GRBM_CNTL -#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL -#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L - -// GRBM_SKEW_CNTL -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003fL -#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000fc0L - -// GRBM_PWR_CNTL -#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L -#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000cL -#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L -#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000c0L -#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L -#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L - -// GRBM_STATUS -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000fL -#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L -#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L -#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L -#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L -#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L -#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L -#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L -#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L -#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L -#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L -#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L -#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L -#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L -#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L -#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L -#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L -#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L -#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L -#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L -#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L -#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L - -// GRBM_STATUS2 -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000fL -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L -#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L -#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L -#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L -#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L -#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L -#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L -#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L -#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L -#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L -#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L -#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L -#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L -#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L -#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L - -// GRBM_STATUS_SE0 -#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L - -// GRBM_STATUS_SE1 -#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L - -// GRBM_STATUS_SE2 -#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L - -// GRBM_STATUS_SE3 -#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L - -// GRBM_SOFT_RESET -#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L -#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L -#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L -#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L -#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L - -// GRBM_DEBUG_CNTL -#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x0000003fL - -// GRBM_DEBUG_DATA -#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffffL - -// GRBM_CGTT_CLK_CNTL -#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000fL -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L - -// GRBM_GFX_CLKEN_CNTL -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L - -// GRBM_WAIT_IDLE_CLOCKS -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000ffL - -// GRBM_DEBUG -#define GRBM_DEBUG__IGNORE_RDY_MASK 0x00000002L -#define GRBM_DEBUG__IGNORE_FAO_MASK 0x00000020L -#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000040L -#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000080L -#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0x00000f00L -#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x00001000L -#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x00002000L -#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000L - -// GRBM_DEBUG_SNAPSHOT -#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x00000001L -#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x00000002L -#define GRBM_DEBUG_SNAPSHOT__RSMU_RDY_MASK 0x00000004L -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x00000008L -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x00000010L -#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x00000020L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x00000040L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x00000080L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x00000100L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x00000200L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x00000400L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x00000800L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x00001000L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x00002000L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x00004000L -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x00008000L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x00010000L -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x00020000L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x00040000L -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x00080000L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x00100000L -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x00200000L - -// GRBM_RSMU_READ_ERROR -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000ffffcL -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07e00000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L - -// GRBM_CHICKEN_BITS -#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L - -// GRBM_READ_ERROR -#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL -#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L -#define GRBM_READ_ERROR__READ_MEID_MASK 0x00c00000L -#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L - -// GRBM_READ_ERROR2 -#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L -#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L - -// GRBM_INT_CNTL -#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L - -// GRBM_TRAP_OP -#define GRBM_TRAP_OP__RW_MASK 0x00000001L - -// GRBM_TRAP_ADDR -#define GRBM_TRAP_ADDR__DATA_MASK 0x0003ffffL - -// GRBM_TRAP_ADDR_MSK -#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003ffffL - -// GRBM_TRAP_WD -#define GRBM_TRAP_WD__DATA_MASK 0xffffffffL - -// GRBM_TRAP_WD_MSK -#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffffL - -// GRBM_DSM_BYPASS -#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L -#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L - -// GRBM_IOV_ERROR -#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000ffffcL -#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03f00000L -#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L -#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L -#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L - -// GRBM_WRITE_ERROR -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L -#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001cL -#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001e0L -#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L -#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001e000L -#define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L -#define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK 0x00040000L -#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L -#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00c00000L -#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L - -// GRBM_GFX_CNTL -#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L -#define GRBM_GFX_CNTL__MEID_MASK 0x0000000cL -#define GRBM_GFX_CNTL__VMID_MASK 0x000000f0L -#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L - -// GRBM_RSMU_CFG -#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000fffL -#define GRBM_RSMU_CFG__QOS_MASK 0x0000f000L -#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L -#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L - -// GRBM_IH_CREDIT -#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00ff0000L - -// GRBM_PWR_CNTL2 -#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L -#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L - -// GRBM_UTCL2_INVAL_RANGE_START -#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003ffffL - -// GRBM_UTCL2_INVAL_RANGE_END -#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003ffffL - -// GRBM_CHIP_REVISION -#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL - -// GRBM_SCRATCH_REG0 -#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL - -// GRBM_SCRATCH_REG1 -#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL - -// GRBM_SCRATCH_REG2 -#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL - -// GRBM_SCRATCH_REG3 -#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL - -// GRBM_SCRATCH_REG4 -#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL - -// GRBM_SCRATCH_REG5 -#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL - -// GRBM_SCRATCH_REG6 -#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL - -// GRBM_SCRATCH_REG7 -#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL - -// DEBUG_INDEX -#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x0003ffffL - -// DEBUG_DATA -#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL - -// GRBM_NOWHERE -#define GRBM_NOWHERE__DATA_MASK 0xffffffffL - -// GRBM_GFX_INDEX -#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000ffL -#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000ff00L -#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00ff0000L -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L - -// GRBM_PERFCOUNTER0_LO -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GRBM_PERFCOUNTER0_HI -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GRBM_PERFCOUNTER1_LO -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GRBM_PERFCOUNTER1_HI -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GRBM_SE0_PERFCOUNTER_LO -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GRBM_SE0_PERFCOUNTER_HI -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GRBM_SE1_PERFCOUNTER_LO -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GRBM_SE1_PERFCOUNTER_HI -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GRBM_SE2_PERFCOUNTER_LO -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GRBM_SE2_PERFCOUNTER_HI -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GRBM_SE3_PERFCOUNTER_LO -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// GRBM_SE3_PERFCOUNTER_HI -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// GRBM_PERFCOUNTER0_SELECT -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L -#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L -#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L -#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L - -// GRBM_PERFCOUNTER1_SELECT -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L -#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L -#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L -#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L - -// GRBM_SE0_PERFCOUNTER_SELECT -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L - -// GRBM_SE1_PERFCOUNTER_SELECT -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L - -// GRBM_SE2_PERFCOUNTER_SELECT -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L - -// GRBM_SE3_PERFCOUNTER_SELECT -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L - -// GRBM_HYP_CAM_INDEX -#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L - -// GRBM_CAM_INDEX -#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L - -// GRBM_HYP_CAM_DATA -#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L - -// GRBM_CAM_DATA -#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL -#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L - -// GRBM_GFX_CNTL_SR_SELECT -#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L - -// GRBM_GFX_CNTL_SR_DATA -#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L -#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000cL -#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000f0L -#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L - -// GRBM_GFX_INDEX_SR_SELECT -#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L - -// GRBM_GFX_INDEX_SR_DATA -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000ffL -#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000ff00L -#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00ff0000L -#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L -#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L - -// GRBM_SRCID_CAM_INDEX -#define GRBM_SRCID_CAM_INDEX__INDEX_MASK 0x00000007L - -// GRBM_SRCID_CAM_DATA -#define GRBM_SRCID_CAM_DATA__PROG_SRCID_MASK 0x00003fffL - -// GRBM_PF_ONLY_RANGE0 -#define GRBM_PF_ONLY_RANGE0__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE0__END_MASK 0xffff0000L - -// GRBM_PF_ONLY_RANGE1 -#define GRBM_PF_ONLY_RANGE1__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE1__END_MASK 0xffff0000L - -// GRBM_PF_ONLY_RANGE2 -#define GRBM_PF_ONLY_RANGE2__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE2__END_MASK 0xffff0000L - -// GRBM_PF_ONLY_RANGE3 -#define GRBM_PF_ONLY_RANGE3__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE3__END_MASK 0xffff0000L - -// GRBM_PF_ONLY_RANGE4 -#define GRBM_PF_ONLY_RANGE4__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE4__END_MASK 0xffff0000L - -// GRBM_PF_ONLY_RANGE5 -#define GRBM_PF_ONLY_RANGE5__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE5__END_MASK 0xffff0000L - -// GRBM_PF_ONLY_RANGE6 -#define GRBM_PF_ONLY_RANGE6__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE6__END_MASK 0xffff0000L - -// GRBM_PF_ONLY_RANGE7 -#define GRBM_PF_ONLY_RANGE7__START_MASK 0x0000ffffL -#define GRBM_PF_ONLY_RANGE7__END_MASK 0xffff0000L - -// GRBM_IOV_ENABLE -#define GRBM_IOV_ENABLE__PF_ONLY_RANGE_ENABLE_MASK 0x000000ffL -#define GRBM_IOV_ENABLE__IOV_ERROR_CHECK_ENABLE_MASK 0x80000000L - -// CP_CPC_DEBUG_CNTL -#define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007fL -#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK 0x003f0000L -#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK 0x80000000L - -// CP_CPC_DEBUG_DATA -#define CP_CPC_DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL - -// CP_CPF_DEBUG_CNTL -#define CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007fL -#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK 0x003f0000L -#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK 0x80000000L - -// CP_CPF_DEBUG_DATA -#define CP_CPF_DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL - -// CP_CPC_STATUS -#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L -#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L -#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L -#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L -#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L -#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L -#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L -#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L -#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L -#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L -#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L -#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L -#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L -#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L -#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L - -// CP_CPC_BUSY_STAT -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L - -// CP_CPC_STALLED_STAT1 -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L -#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L - -// CP_CPF_STATUS -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L -#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L -#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L -#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L -#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L -#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L -#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L -#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L -#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L -#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L -#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L -#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L -#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L -#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L - -// CP_CPF_BUSY_STAT -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L - -// CP_CPF_STALLED_STAT1 -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L -#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L -#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L -#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L - -// CP_CPC_GRBM_FREE_COUNT -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL - -// CP_CPC_PRIV_VIOLATION_ADDR -#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000ffffL - -// CP_MEC_CNTL -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L -#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L -#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L -#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L -#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L - -// CP_MEC_ME1_HEADER_DUMP -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffffL - -// CP_MEC_ME2_HEADER_DUMP -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffffL - -// CP_CPC_SCRATCH_INDEX -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001ffL - -// CP_CPC_SCRATCH_DATA -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL - -// CP_CPF_GRBM_FREE_COUNT -#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L - -// CP_CPC_HALT_HYST_COUNT -#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000fL - -// CP_PRT_LOD_STATS_CNTL0 -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffffL - -// CP_PRT_LOD_STATS_CNTL1 -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffffL - -// CP_PRT_LOD_STATS_CNTL2 -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003ffL - -// CP_PRT_LOD_STATS_CNTL3 -#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003fcL -#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003fc00L -#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L -#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L -#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L -#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L - -// CP_CE_COMPARE_COUNT -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffffL - -// CP_CE_DE_COUNT -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffffL - -// CP_DE_CE_COUNT -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffffL - -// CP_DE_LAST_INVAL_COUNT -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffffL - -// CP_DE_DE_COUNT -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffffL - -// CP_STALLED_STAT1 -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L - -// CP_STALLED_STAT2 -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L - -// CP_STALLED_STAT3 -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L -#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L - -// CP_BUSY_STAT -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L -#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L -#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L -#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L -#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L -#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L -#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L -#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L -#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L -#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L -#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L - -// CP_STAT -#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L -#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L -#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L -#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L -#define CP_STAT__DC_BUSY_MASK 0x00002000L -#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L -#define CP_STAT__PFP_BUSY_MASK 0x00008000L -#define CP_STAT__MEQ_BUSY_MASK 0x00010000L -#define CP_STAT__ME_BUSY_MASK 0x00020000L -#define CP_STAT__QUERY_BUSY_MASK 0x00040000L -#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L -#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L -#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L -#define CP_STAT__DMA_BUSY_MASK 0x00400000L -#define CP_STAT__RCIU_BUSY_MASK 0x00800000L -#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L -#define CP_STAT__CE_BUSY_MASK 0x04000000L -#define CP_STAT__TCIU_BUSY_MASK 0x08000000L -#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L -#define CP_STAT__CP_BUSY_MASK 0x80000000L - -// CP_ME_HEADER_DUMP -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL - -// CP_PFP_HEADER_DUMP -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL - -// CP_GRBM_FREE_COUNT -#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L - -// CP_CE_HEADER_DUMP -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL - -// CP_PFP_INSTR_PNTR -#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000ffffL - -// CP_ME_INSTR_PNTR -#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000ffffL - -// CP_CE_INSTR_PNTR -#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000ffffL - -// CP_MEC1_INSTR_PNTR -#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000ffffL - -// CP_MEC2_INSTR_PNTR -#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000ffffL - -// CP_CSF_STAT -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001ff00L - -// CP_ME_CNTL -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L -#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L -#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L -#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L -#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L -#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L -#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L -#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L -#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L -#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L -#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L -#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L -#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L - -// CP_CNTX_STAT -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000ffL -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L - -// CP_ME_PREEMPTION -#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L - -// CP_RB0_RPTR -#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL - -// CP_RB_RPTR -#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL - -// CP_RB1_RPTR -#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL - -// CP_RB2_RPTR -#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL - -// CP_RB_WPTR_DELAY -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L - -// CP_RB_WPTR_POLL_CNTL -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L - -// CP_ROQ_THRESHOLDS -#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000ffL -#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000ff00L - -// CP_MEQ_STQ_THRESHOLD -#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000ffL - -// CP_ROQ1_THRESHOLDS -#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL -#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L -#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L -#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L - -// CP_ROQ2_THRESHOLDS -#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL -#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L -#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L -#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L - -// CP_STQ_THRESHOLDS -#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000ffL -#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000ff00L -#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00ff0000L - -// CP_QUEUE_THRESHOLDS -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L - -// CP_MEQ_THRESHOLDS -#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL -#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L - -// CP_ROQ_AVAIL -#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL -#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L - -// CP_STQ_AVAIL -#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001ffL - -// CP_ROQ2_AVAIL -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL - -// CP_MEQ_AVAIL -#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL - -// CP_CMD_INDEX -#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL -#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L -#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L - -// CP_CMD_DATA -#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL - -// CP_ROQ_RB_STAT -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003ffL -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03ff0000L - -// CP_ROQ_IB1_STAT -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03ff0000L - -// CP_ROQ_IB2_STAT -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003ffL -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03ff0000L - -// CP_STQ_STAT -#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003ffL - -// CP_STQ_WR_STAT -#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003ffL - -// CP_MEQ_STAT -#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL -#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L - -// CP_CEQ1_AVAIL -#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L - -// CP_CEQ2_AVAIL -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL - -// CP_CE_ROQ_RB_STAT -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L - -// CP_CE_ROQ_IB1_STAT -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L - -// CP_CE_ROQ_IB2_STAT -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L - -// CP_INT_STAT_DEBUG -#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L -#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L -#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L -#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L -#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L -#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L -#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L -#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L -#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L -#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L -#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L -#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L -#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L - -// CP_DEBUG_CNTL -#define CP_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007fL -#define CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK 0x003f0000L -#define CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK 0x80000000L - -// CP_DEBUG_DATA -#define CP_DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL - -// CP_PRIV_VIOLATION_ADDR -#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000ffffL - -// CP_DFY_CNTL -#define CP_DFY_CNTL__POLICY_MASK 0x00000001L -#define CP_DFY_CNTL__MTYPE_MASK 0x0000000cL -#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L -#define CP_DFY_CNTL__WRITE_DIS_MASK 0x08000000L -#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L -#define CP_DFY_CNTL__MODE_MASK 0x60000000L -#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L - -// CP_DFY_STAT -#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000ffffL -#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07ff0000L -#define CP_DFY_STAT__BUSY_MASK 0x80000000L - -// CP_DFY_ADDR_HI -#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffffL - -// CP_DFY_ADDR_LO -#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0L - -// CP_DFY_DATA_0 -#define CP_DFY_DATA_0__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_1 -#define CP_DFY_DATA_1__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_2 -#define CP_DFY_DATA_2__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_3 -#define CP_DFY_DATA_3__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_4 -#define CP_DFY_DATA_4__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_5 -#define CP_DFY_DATA_5__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_6 -#define CP_DFY_DATA_6__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_7 -#define CP_DFY_DATA_7__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_8 -#define CP_DFY_DATA_8__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_9 -#define CP_DFY_DATA_9__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_10 -#define CP_DFY_DATA_10__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_11 -#define CP_DFY_DATA_11__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_12 -#define CP_DFY_DATA_12__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_13 -#define CP_DFY_DATA_13__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_14 -#define CP_DFY_DATA_14__DATA_MASK 0xffffffffL - -// CP_DFY_DATA_15 -#define CP_DFY_DATA_15__DATA_MASK 0xffffffffL - -// CP_DFY_CMD -#define CP_DFY_CMD__OFFSET_MASK 0x000001ffL -#define CP_DFY_CMD__SIZE_MASK 0xffff0000L - -// CP_EOPQ_WAIT_TIME -#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003ffL -#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003fc00L - -// CP_CPC_MGCG_SYNC_CNTL -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000ffL -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000ff00L - -// CPC_INT_INFO -#define CPC_INT_INFO__ADDR_HI_MASK 0x0000ffffL -#define CPC_INT_INFO__TYPE_MASK 0x00010000L -#define CPC_INT_INFO__VMID_MASK 0x00f00000L -#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L - -// CPC_INT_ADDR -#define CPC_INT_ADDR__ADDR_MASK 0xffffffffL - -// CPC_INT_PASID -#define CPC_INT_PASID__PASID_MASK 0x0000ffffL - -// CP_GFX_ERROR -#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000fL -#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L -#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L -#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L -#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L -#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L -#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L -#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L -#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L -#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L -#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L -#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L -#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L -#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L -#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L -#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L -#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L -#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L -#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L -#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L -#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L -#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L -#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L -#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L -#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L -#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L -#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L -#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L -#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L - -// CPG_UTCL1_CNTL -#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L - -// CPC_UTCL1_CNTL -#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L - -// CPF_UTCL1_CNTL -#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000fffffL -#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L -#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L - -// CP_AQL_SMM_STATUS -#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xffffffffL - -// CP_RB0_BASE -#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL - -// CP_RB0_BASE_HI -#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000ffL - -// CP_RB_BASE -#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL - -// CP_RB1_BASE -#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL - -// CP_RB1_BASE_HI -#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000ffL - -// CP_RB2_BASE -#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL - -// CP_RB0_CNTL -#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L -#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L - -// CP_RB_CNTL -#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L - -// CP_RB1_CNTL -#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L - -// CP_RB2_CNTL -#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL -#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L -#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L -#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L - -// CP_RB_RPTR_WR -#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL - -// CP_RB0_RPTR_ADDR -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL - -// CP_RB_RPTR_ADDR -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL - -// CP_RB1_RPTR_ADDR -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL - -// CP_RB2_RPTR_ADDR -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL - -// CP_RB0_RPTR_ADDR_HI -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000ffffL - -// CP_RB_RPTR_ADDR_HI -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000ffffL - -// CP_RB1_RPTR_ADDR_HI -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000ffffL - -// CP_RB2_RPTR_ADDR_HI -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000ffffL - -// CP_RB0_ACTIVE -#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L - -// CP_RB_ACTIVE -#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L - -// CP_RB0_BUFSZ_MASK -#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000fffffL - -// CP_RB_BUFSZ_MASK -#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000fffffL - -// CP_RB_WPTR_POLL_ADDR_LO -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffcL - -// CP_RB_WPTR_POLL_ADDR_HI -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000ffffL - -// GC_PRIV_MODE -#define GC_PRIV_MODE__MC_PRIV_MODE_MASK 0x00000001L - -// CP_INT_CNTL -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_INT_CNTL_RING0 -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_INT_CNTL_RING1 -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_INT_CNTL_RING2 -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_INT_STATUS -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L - -// CP_INT_STATUS_RING0 -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L - -// CP_INT_STATUS_RING1 -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L - -// CP_INT_STATUS_RING2 -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L - -// CP_DEVICE_ID -#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000ffL - -// CP_RING_PRIORITY_CNTS -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L - -// CP_ME0_PIPE_PRIORITY_CNTS -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L - -// CP_RING0_PRIORITY -#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME0_PIPE0_PRIORITY -#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_RING1_PRIORITY -#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME0_PIPE1_PRIORITY -#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_RING2_PRIORITY -#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME0_PIPE2_PRIORITY -#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_FATAL_ERROR -#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L -#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L -#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L -#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L -#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L - -// CP_RB_VMID -#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL -#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L -#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L - -// CP_ME0_PIPE0_VMID -#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000fL - -// CP_ME0_PIPE1_VMID -#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000fL - -// CP_RB0_WPTR -#define CP_RB0_WPTR__RB_WPTR_MASK 0xffffffffL - -// CP_RB_WPTR -#define CP_RB_WPTR__RB_WPTR_MASK 0xffffffffL - -// CP_RB0_WPTR_HI -#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xffffffffL - -// CP_RB_WPTR_HI -#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xffffffffL - -// CP_RB1_WPTR -#define CP_RB1_WPTR__RB_WPTR_MASK 0xffffffffL - -// CP_RB1_WPTR_HI -#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xffffffffL - -// CP_RB2_WPTR -#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL - -// CP_RB_DOORBELL_CONTROL -#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_RANGE_LOWER -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0ffffffcL - -// CP_RB_DOORBELL_RANGE_UPPER -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0ffffffcL - -// CP_MEC_DOORBELL_RANGE_LOWER -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0ffffffcL - -// CP_MEC_DOORBELL_RANGE_UPPER -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0ffffffcL - -// CPG_UTCL1_ERROR -#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L - -// CPC_UTCL1_ERROR -#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L - -// CP_IB1_PRIV_BASE_LO -#define CP_IB1_PRIV_BASE_LO__IB1_PRIV_BASE_LO_MASK 0xfffffffcL - -// CP_IB1_PRIV_BASE_HI -#define CP_IB1_PRIV_BASE_HI__IB1_PRIV_BASE_HI_MASK 0x0000ffffL - -// CP_IB1_PRIV_BUFSZ -#define CP_IB1_PRIV_BUFSZ__IB1_PRIV_BUFSZ_MASK 0x000fffffL - -// CP_ME_F32_INTERRUPT -#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L -#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L -#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L -#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L - -// CP_PFP_F32_INTERRUPT -#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L - -// CP_CE_F32_INTERRUPT -#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L -#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000002L -#define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK 0x00000004L -#define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK 0x00000008L - -// CP_MEC1_F32_INTERRUPT -#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L - -// CP_MEC2_F32_INTERRUPT -#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L - -// CP_MEC1_F32_INT_DIS -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L - -// CP_MEC2_F32_INT_DIS -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L - -// CP_VIRT_STATUS -#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffffL - -// CP_PWR_CNTL -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L - -// CP_MEM_SLP_CNTL -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L -#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007cL -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L -#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L - -// CP_ECC_FIRSTOCCURRENCE -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L -#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000f0L -#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L -#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000c00L -#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L -#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L - -// CP_ECC_FIRSTOCCURRENCE_RING0 -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffffL - -// CP_ECC_FIRSTOCCURRENCE_RING1 -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffffL - -// CP_ECC_FIRSTOCCURRENCE_RING2 -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffffL - -// CP_DEBUG -#define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK 0x00070000L -#define CP_DEBUG__BUSY_EXTENDER_MASK 0x00180000L -#define CP_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L -#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L -#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L -#define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L -#define CP_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L -#define CP_DEBUG__CPG_TC_MTYPE_OVERRIDE_MASK 0x08000000L -#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L -#define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L -#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK 0x40000000L -#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK 0x80000000L - -// CP_CPF_DEBUG -#define CP_CPF_DEBUG__BUSY_EXTENDER_MASK 0x00180000L -#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L -#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L -#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK 0x20000000L -#define CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE_MASK 0x40000000L -#define CP_CPF_DEBUG__DBGU_TRIGGER_MASK 0x80000000L - -// CP_CPC_DEBUG -#define CP_CPC_DEBUG__BUSY_EXTENDER_MASK 0x00180000L -#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK 0x00200000L -#define CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L -#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L -#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L -#define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L -#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L -#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L -#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK 0x80000000L - -// CP_PQ_WPTR_POLL_CNTL -#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000ffL -#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L -#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L - -// CP_PQ_WPTR_POLL_CNTL1 -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffffL - -// CPC_INT_CNTL -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME1_PIPE0_INT_CNTL -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME1_PIPE1_INT_CNTL -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME1_PIPE2_INT_CNTL -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME1_PIPE3_INT_CNTL -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME2_PIPE0_INT_CNTL -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME2_PIPE1_INT_CNTL -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME2_PIPE2_INT_CNTL -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CP_ME2_PIPE3_INT_CNTL -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L - -// CPC_INT_STATUS -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME1_PIPE0_INT_STATUS -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME1_PIPE1_INT_STATUS -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME1_PIPE2_INT_STATUS -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME1_PIPE3_INT_STATUS -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME2_PIPE0_INT_STATUS -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME2_PIPE1_INT_STATUS -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME2_PIPE2_INT_STATUS -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME2_PIPE3_INT_STATUS -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L - -// CP_ME1_INT_STAT_DEBUG -#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L -#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L -#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L -#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L -#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L -#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L -#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L -#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L -#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L -#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L - -// CP_ME2_INT_STAT_DEBUG -#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L -#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L -#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L -#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L -#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L -#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L -#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L -#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L -#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L -#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L - -// CP_ME1_PIPE_PRIORITY_CNTS -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L - -// CP_ME1_PIPE0_PRIORITY -#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME1_PIPE1_PRIORITY -#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME1_PIPE2_PRIORITY -#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME1_PIPE3_PRIORITY -#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME2_PIPE_PRIORITY_CNTS -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L - -// CP_ME2_PIPE0_PRIORITY -#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME2_PIPE1_PRIORITY -#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME2_PIPE2_PRIORITY -#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_ME2_PIPE3_PRIORITY -#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L - -// CP_CE_PRGRM_CNTR_START -#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007ffL - -// CP_PFP_PRGRM_CNTR_START -#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001fffL - -// CP_ME_PRGRM_CNTR_START -#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000fffL - -// CP_MEC1_PRGRM_CNTR_START -#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000ffffL - -// CP_MEC2_PRGRM_CNTR_START -#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000ffffL - -// CP_CE_INTR_ROUTINE_START -#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007ffL - -// CP_PFP_INTR_ROUTINE_START -#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001fffL - -// CP_ME_INTR_ROUTINE_START -#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000fffL - -// CP_MEC1_INTR_ROUTINE_START -#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000ffffL - -// CP_MEC2_INTR_ROUTINE_START -#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000ffffL - -// CP_CONTEXT_CNTL -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L - -// CP_MAX_CONTEXT -#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L - -// CP_IQ_WAIT_TIME1 -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000ffL -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000ff00L -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00ff0000L -#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000L - -// CP_IQ_WAIT_TIME2 -#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000ffL -#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000ff00L -#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00ff0000L -#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000L - -// CP_VMID_RESET -#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000ffffL - -// CP_VMID_PREEMPT -#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000ffffL -#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000f0000L - -// CP_VMID_STATUS -#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000ffffL -#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000L - -// CPC_INT_CNTX_ID -#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffffffffL - -// CP_PQ_STATUS -#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L -#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L - -// CP_CPC_IC_BASE_LO -#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000L - -// CP_CPC_IC_BASE_HI -#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000ffffL - -// CP_CPC_IC_BASE_CNTL -#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000fL -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L - -// CP_CPC_IC_OP_CNTL -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L - -// CP_RB_DOORBELL_CONTROL_SCH_0 -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CONTROL_SCH_1 -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CONTROL_SCH_2 -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CONTROL_SCH_3 -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CONTROL_SCH_4 -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CONTROL_SCH_5 -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CONTROL_SCH_6 -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CONTROL_SCH_7 -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L - -// CP_RB_DOORBELL_CLEAR -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L - -// CP_GFX_MQD_CONTROL -#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000fL -#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L -#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L - -// CP_GFX_MQD_BASE_ADDR -#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffcL - -// CP_GFX_MQD_BASE_ADDR_HI -#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000ffffL - -// CP_RB_STATUS -#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L -#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L - -// CPG_UTCL1_STATUS -#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003f00L -#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003f0000L -#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3f000000L - -// CPC_UTCL1_STATUS -#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003f00L -#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003f0000L -#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3f000000L - -// CPF_UTCL1_STATUS -#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003f00L -#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003f0000L -#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3f000000L - -// CP_SD_CNTL -#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L -#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L -#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L -#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L -#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L -#define CP_SD_CNTL__WD_EN_MASK 0x00000020L -#define CP_SD_CNTL__IA_EN_MASK 0x00000040L -#define CP_SD_CNTL__PA_EN_MASK 0x00000080L -#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L -#define CP_SD_CNTL__EA_EN_MASK 0x00000200L - -// CP_TMZ_CNTL -#define CP_TMZ_CNTL__PTE_DISABLE_MASK 0x00000001L - -// CP_SOFT_RESET_CNTL -#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L -#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L -#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L -#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L -#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L -#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L -#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L - -// CP_CPC_GFX_CNTL -#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L -#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L -#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L -#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L - -// CP_SECURE_TMZ -#define CP_SECURE_TMZ__TMZ_MASK 0x00000001L - -// CP_GFX_SECURE_REQ0 -#define CP_GFX_SECURE_REQ0__REQ_TYPE_MASK 0x000000ffL -#define CP_GFX_SECURE_REQ0__RSP_TYPE_MASK 0x0000ff00L -#define CP_GFX_SECURE_REQ0__RSP_EN_MASK 0x40000000L -#define CP_GFX_SECURE_REQ0__REQ_EN_MASK 0x80000000L - -// CP_HQD_SECURE_REQ0 -#define CP_HQD_SECURE_REQ0__REQ_TYPE_MASK 0x000000ffL -#define CP_HQD_SECURE_REQ0__RSP_TYPE_MASK 0x0000ff00L -#define CP_HQD_SECURE_REQ0__RSP_EN_MASK 0x40000000L -#define CP_HQD_SECURE_REQ0__REQ_EN_MASK 0x80000000L - -// CP_HQD_GFX_CONTROL -#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000fL -#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007ff0L -#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L - -// CP_HQD_GFX_STATUS -#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000ffffL - -// CP_HPD_ROQ_OFFSETS -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003f00L -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003f0000L - -// CP_HPD_STATUS0 -#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001fL -#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000e0L -#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000ff00L -#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L -#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01f00000L -#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L - -// CP_HPD_UTCL1_CNTL -#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000fL - -// CP_HPD_UTCL1_ERROR -#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000ffffL -#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L -#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00f00000L - -// CP_HPD_UTCL1_ERROR_ADDR -#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xfffff000L - -// CP_MQD_BASE_ADDR -#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffcL - -// CP_MQD_BASE_ADDR_HI -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000ffffL - -// CP_HQD_ACTIVE -#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L -#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L - -// CP_HQD_VMID -#define CP_HQD_VMID__VMID_MASK 0x0000000fL -#define CP_HQD_VMID__IB_VMID_MASK 0x00000f00L -#define CP_HQD_VMID__VQID_MASK 0x03ff0000L - -// CP_HQD_PERSISTENT_STATE -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003ff00L -#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L -#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L -#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L -#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L -#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L -#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L -#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L - -// CP_HQD_PIPE_PRIORITY -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L - -// CP_HQD_QUEUE_PRIORITY -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000fL - -// CP_HQD_QUANTUM -#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L -#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L -#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003f00L -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L - -// CP_HQD_PQ_BASE -#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffffL - -// CP_HQD_PQ_BASE_HI -#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000ffL - -// CP_HQD_PQ_RPTR -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffffL - -// CP_HQD_PQ_RPTR_REPORT_ADDR -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffcL - -// CP_HQD_PQ_RPTR_REPORT_ADDR_HI -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000ffffL - -// CP_HQD_PQ_WPTR_POLL_ADDR -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffff8L - -// CP_HQD_PQ_WPTR_POLL_ADDR_HI -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000ffffL - -// CP_HQD_PQ_DOORBELL_CONTROL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0ffffffcL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L - -// CP_HQD_PQ_CONTROL -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003fL -#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L -#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003f00L -#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L -#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L -#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L -#define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L -#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L -#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L -#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L - -// CP_HQD_IB_BASE_ADDR -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffcL - -// CP_HQD_IB_BASE_ADDR_HI -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000ffffL - -// CP_HQD_IB_RPTR -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000fffffL - -// CP_HQD_IB_CONTROL -#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000fffffL -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L -#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK 0x40000000L -#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L - -// CP_HQD_IQ_TIMER -#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000ffL -#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L -#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000c000L -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003f0000L -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L -#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L -#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L -#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L -#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L - -// CP_HQD_IQ_RPTR -#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003fL - -// CP_HQD_DEQUEUE_REQUEST -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L - -// CP_HQD_DMA_OFFLOAD -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L - -// CP_HQD_OFFLOAD -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L - -// CP_HQD_SEMA_CMD -#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L -#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L - -// CP_HQD_MSG_TYPE -#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L -#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L - -// CP_HQD_ATOMIC0_PREOP_LO -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffffL - -// CP_HQD_ATOMIC0_PREOP_HI -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffffL - -// CP_HQD_ATOMIC1_PREOP_LO -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffffL - -// CP_HQD_ATOMIC1_PREOP_HI -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffffL - -// CP_HQD_HQ_SCHEDULER0 -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffffL - -// CP_HQD_HQ_STATUS0 -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000cL -#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L -#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3ffffc00L -#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L -#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L - -// CP_HQD_HQ_SCHEDULER1 -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffffL - -// CP_HQD_HQ_CONTROL0 -#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffffL - -// CP_MQD_CONTROL -#define CP_MQD_CONTROL__VMID_MASK 0x0000000fL -#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L -#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L -#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L -#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L - -// CP_HQD_HQ_STATUS1 -#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffffL - -// CP_HQD_HQ_CONTROL1 -#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffffL - -// CP_HQD_EOP_BASE_ADDR -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffffL - -// CP_HQD_EOP_BASE_ADDR_HI -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000ffL - -// CP_HQD_EOP_CONTROL -#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003fL -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L -#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L - -// CP_HQD_EOP_RPTR -#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001fffL -#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L -#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L -#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L - -// CP_HQD_EOP_WPTR -#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001fffL -#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L -#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000L - -// CP_HQD_EOP_EVENTS -#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000fffL -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L - -// CP_HQD_CTX_SAVE_BASE_ADDR_LO -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000L - -// CP_HQD_CTX_SAVE_BASE_ADDR_HI -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_HQD_CTX_SAVE_CONTROL -#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L -#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L - -// CP_HQD_CNTL_STACK_OFFSET -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007ffcL - -// CP_HQD_CNTL_STACK_SIZE -#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L - -// CP_HQD_WG_STATE_OFFSET -#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01fffffcL - -// CP_HQD_CTX_SAVE_SIZE -#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01fff000L - -// CP_HQD_GDS_RESOURCE_STATE -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003f0L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003f000L - -// CP_HQD_ERROR -#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000fL -#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L -#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L -#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L -#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L -#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L -#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L -#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L -#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L -#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L -#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L -#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L -#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L -#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L -#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L - -// CP_HQD_EOP_WPTR_MEM -#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001fffL - -// CP_HQD_AQL_CONTROL -#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007fffL -#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L -#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7fff0000L -#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L - -// CP_HQD_PQ_WPTR_LO -#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xffffffffL - -// CP_HQD_PQ_WPTR_HI -#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xffffffffL - -// COHER_DEST_BASE_0 -#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL - -// COHER_DEST_BASE_1 -#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL - -// COHER_DEST_BASE_2 -#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL - -// COHER_DEST_BASE_3 -#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL - -// COHER_DEST_BASE_HI_0 -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000ffL - -// COHER_DEST_BASE_HI_1 -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000ffL - -// COHER_DEST_BASE_HI_2 -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000ffL - -// COHER_DEST_BASE_HI_3 -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000ffL - -// CP_PERFMON_CNTX_CNTL -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L - -// CP_RINGID -#define CP_RINGID__RINGID_MASK 0x00000003L - -// CP_PIPEID -#define CP_PIPEID__PIPE_ID_MASK 0x00000003L - -// CP_VMID -#define CP_VMID__VMID_MASK 0x0000000fL - -// CP_EOP_DONE_EVENT_CNTL -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007fL -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003f000L -#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L -#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L - -// CP_EOP_DONE_DATA_CNTL -#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L -#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000L - -// CP_EOP_DONE_CNTX_ID -#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xffffffffL - -// CP_EOP_DONE_ADDR_LO -#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffcL - -// CP_EOP_DONE_ADDR_HI -#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_EOP_DONE_DATA_LO -#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffffL - -// CP_EOP_DONE_DATA_HI -#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffffL - -// CP_EOP_LAST_FENCE_LO -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL - -// CP_EOP_LAST_FENCE_HI -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL - -// CP_STREAM_OUT_ADDR_LO -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffcL - -// CP_STREAM_OUT_ADDR_HI -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000ffffL - -// CP_NUM_PRIM_WRITTEN_COUNT0_LO -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_WRITTEN_COUNT0_HI -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT0_LO -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT0_HI -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL - -// CP_NUM_PRIM_WRITTEN_COUNT1_LO -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_WRITTEN_COUNT1_HI -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT1_LO -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT1_HI -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL - -// CP_NUM_PRIM_WRITTEN_COUNT2_LO -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_WRITTEN_COUNT2_HI -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT2_LO -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT2_HI -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL - -// CP_NUM_PRIM_WRITTEN_COUNT3_LO -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_WRITTEN_COUNT3_HI -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT3_LO -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL - -// CP_NUM_PRIM_NEEDED_COUNT3_HI -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL - -// CP_PIPE_STATS_ADDR_LO -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL - -// CP_PIPE_STATS_ADDR_HI -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000ffffL - -// CP_VGT_IAVERT_COUNT_LO -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_IAVERT_COUNT_HI -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffffL - -// CP_VGT_IAPRIM_COUNT_LO -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_IAPRIM_COUNT_HI -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffffL - -// CP_VGT_GSPRIM_COUNT_LO -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_GSPRIM_COUNT_HI -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffffL - -// CP_VGT_VSINVOC_COUNT_LO -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_VSINVOC_COUNT_HI -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffffL - -// CP_VGT_GSINVOC_COUNT_LO -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_GSINVOC_COUNT_HI -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffffL - -// CP_VGT_HSINVOC_COUNT_LO -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_HSINVOC_COUNT_HI -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffffL - -// CP_VGT_DSINVOC_COUNT_LO -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_DSINVOC_COUNT_HI -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffffL - -// CP_PA_CINVOC_COUNT_LO -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL - -// CP_PA_CINVOC_COUNT_HI -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL - -// CP_PA_CPRIM_COUNT_LO -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL - -// CP_PA_CPRIM_COUNT_HI -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL - -// CP_SC_PSINVOC_COUNT0_LO -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffffL - -// CP_SC_PSINVOC_COUNT0_HI -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffffL - -// CP_SC_PSINVOC_COUNT1_LO -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffffL - -// CP_SC_PSINVOC_COUNT1_HI -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffffL - -// CP_VGT_CSINVOC_COUNT_LO -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffffL - -// CP_VGT_CSINVOC_COUNT_HI -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffffL - -// CP_PIPE_STATS_CONTROL -#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L - -// CP_STREAM_OUT_CONTROL -#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L - -// CP_STRMOUT_CNTL -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L - -// SCRATCH_REG0 -#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL -#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL - -// SCRATCH_REG1 -#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL -#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL - -// SCRATCH_REG2 -#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL -#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL - -// SCRATCH_REG3 -#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL -#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL - -// SCRATCH_REG4 -#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL -#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL - -// SCRATCH_REG5 -#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL -#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL - -// SCRATCH_REG6 -#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL -#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL - -// SCRATCH_REG7 -#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL -#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL - -// CP_APPEND_DATA_HI -#define CP_APPEND_DATA_HI__DATA_MASK 0xffffffffL - -// CP_APPEND_LAST_CS_FENCE_HI -#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xffffffffL - -// CP_APPEND_LAST_PS_FENCE_HI -#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xffffffffL - -// SCRATCH_UMSK -#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000ffL -#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L - -// SCRATCH_ADDR -#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffffL - -// CP_PFP_ATOMIC_PREOP_LO -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL - -// CP_PFP_ATOMIC_PREOP_HI -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL - -// CP_PFP_GDS_ATOMIC0_PREOP_LO -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL - -// CP_PFP_GDS_ATOMIC0_PREOP_HI -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL - -// CP_PFP_GDS_ATOMIC1_PREOP_LO -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL - -// CP_PFP_GDS_ATOMIC1_PREOP_HI -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL - -// CP_APPEND_ADDR_LO -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL - -// CP_APPEND_ADDR_HI -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000ffffL -#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L -#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L -#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L - -// CP_APPEND_DATA_LO -#define CP_APPEND_DATA_LO__DATA_MASK 0xffffffffL - -// CP_APPEND_LAST_CS_FENCE_LO -#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xffffffffL - -// CP_APPEND_LAST_PS_FENCE_LO -#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xffffffffL - -// CP_ATOMIC_PREOP_LO -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL - -// CP_ME_ATOMIC_PREOP_LO -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL - -// CP_ATOMIC_PREOP_HI -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL - -// CP_ME_ATOMIC_PREOP_HI -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL - -// CP_GDS_ATOMIC0_PREOP_LO -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL - -// CP_ME_GDS_ATOMIC0_PREOP_LO -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL - -// CP_GDS_ATOMIC0_PREOP_HI -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL - -// CP_ME_GDS_ATOMIC0_PREOP_HI -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL - -// CP_GDS_ATOMIC1_PREOP_LO -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL - -// CP_ME_GDS_ATOMIC1_PREOP_LO -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL - -// CP_GDS_ATOMIC1_PREOP_HI -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL - -// CP_ME_GDS_ATOMIC1_PREOP_HI -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL - -// CP_ME_MC_WADDR_LO -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL - -// CP_ME_MC_WADDR_HI -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000ffffL -#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L - -// CP_ME_MC_WDATA_LO -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL - -// CP_ME_MC_WDATA_HI -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL - -// CP_ME_MC_RADDR_LO -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL - -// CP_ME_MC_RADDR_HI -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000ffffL -#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L - -// CP_SEM_WAIT_TIMER -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffffL - -// CP_SIG_SEM_ADDR_LO -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L - -// CP_SIG_SEM_ADDR_HI -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000ffffL -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L - -// CP_WAIT_SEM_ADDR_LO -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L - -// CP_WAIT_SEM_ADDR_HI -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000ffffL -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L - -// CP_WAIT_REG_MEM_TIMEOUT -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffffL - -// CP_COHER_START_DELAY -#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL - -// CP_COHER_CNTL -#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L -#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L -#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L -#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L -#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L -#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L -#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L -#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L - -// CP_COHER_SIZE -#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL - -// CP_COHER_SIZE_HI -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL - -// CP_COHER_BASE -#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL - -// CP_COHER_BASE_HI -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL - -// CP_COHER_STATUS -#define CP_COHER_STATUS__MEID_MASK 0x03000000L -#define CP_COHER_STATUS__STATUS_MASK 0x80000000L - -// CP_DMA_PIO_SRC_ADDR -#define CP_DMA_PIO_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL - -// CP_DMA_PIO_SRC_ADDR_HI -#define CP_DMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000ffffL - -// CP_DMA_PIO_DST_ADDR -#define CP_DMA_PIO_DST_ADDR__DST_ADDR_MASK 0xffffffffL - -// CP_DMA_PIO_DST_ADDR_HI -#define CP_DMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000ffffL - -// CP_DMA_PIO_CONTROL -#define CP_DMA_PIO_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L -#define CP_DMA_PIO_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L -#define CP_DMA_PIO_CONTROL__DST_SELECT_MASK 0x00300000L -#define CP_DMA_PIO_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L -#define CP_DMA_PIO_CONTROL__SRC_SELECT_MASK 0x60000000L - -// CP_DMA_PIO_COMMAND -#define CP_DMA_PIO_COMMAND__BYTE_COUNT_MASK 0x03ffffffL -#define CP_DMA_PIO_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_PIO_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_PIO_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_PIO_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_PIO_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_PIO_COMMAND__DIS_WC_MASK 0x80000000L - -// CP_DMA_ME_SRC_ADDR -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL - -// CP_DMA_ME_SRC_ADDR_HI -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000ffffL - -// CP_DMA_ME_DST_ADDR -#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL - -// CP_DMA_ME_DST_ADDR_HI -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000ffffL - -// CP_DMA_ME_CONTROL -#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L -#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L -#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L - -// CP_DMA_ME_COMMAND -#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03ffffffL -#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L - -// CP_DMA_PFP_SRC_ADDR -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL - -// CP_DMA_PFP_SRC_ADDR_HI -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000ffffL - -// CP_DMA_PFP_DST_ADDR -#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL - -// CP_DMA_PFP_DST_ADDR_HI -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000ffffL - -// CP_DMA_PFP_CONTROL -#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L -#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L -#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L - -// CP_DMA_PFP_COMMAND -#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03ffffffL -#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L - -// CP_DMA_CNTL -#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L -#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L -#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L -#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L -#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L -#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L - -// CP_DMA_READ_TAGS -#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L - -// CP_PFP_IB_CONTROL -#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000ffL - -// CP_PFP_LOAD_CONTROL -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L - -// CP_SCRATCH_INDEX -#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000ffL - -// CP_SCRATCH_DATA -#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL - -// CP_RB_OFFSET -#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL - -// CP_IB1_OFFSET -#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL - -// CP_IB2_OFFSET -#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL - -// CP_IB1_PREAMBLE_BEGIN -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL - -// CP_IB1_PREAMBLE_END -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL - -// CP_IB2_PREAMBLE_BEGIN -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL - -// CP_IB2_PREAMBLE_END -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL - -// CP_CE_IB1_OFFSET -#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL - -// CP_CE_IB2_OFFSET -#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL - -// CP_CE_COUNTER -#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffffL - -// CP_CE_RB_OFFSET -#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL - -// CP_PFP_COMPLETION_STATUS -#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L - -// CP_CE_COMPLETION_STATUS -#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L - -// CP_PRED_NOT_VISIBLE -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L - -// CP_PFP_METADATA_BASE_ADDR -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffffL - -// CP_PFP_METADATA_BASE_ADDR_HI -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_CE_METADATA_BASE_ADDR -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffffL - -// CP_CE_METADATA_BASE_ADDR_HI -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_DRAW_INDX_INDR_ADDR -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffffL - -// CP_DRAW_INDX_INDR_ADDR_HI -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_DISPATCH_INDR_ADDR -#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffffL - -// CP_DISPATCH_INDR_ADDR_HI -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_INDEX_BASE_ADDR -#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffffL - -// CP_INDEX_BASE_ADDR_HI -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_INDEX_TYPE -#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L - -// CP_GDS_BKUP_ADDR -#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffffL - -// CP_GDS_BKUP_ADDR_HI -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000ffffL - -// CP_SAMPLE_STATUS -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L - -// CP_ME_COHER_CNTL -#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L -#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L -#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L -#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L -#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L -#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L -#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L -#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L -#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L -#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L -#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L -#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L -#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L - -// CP_ME_COHER_SIZE -#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL - -// CP_ME_COHER_SIZE_HI -#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL - -// CP_ME_COHER_BASE -#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL - -// CP_ME_COHER_BASE_HI -#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL - -// CP_ME_COHER_STATUS -#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL -#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L - -// CP_CE_INIT_CMD_BUFSZ -#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000fffL - -// CP_CE_IB1_CMD_BUFSZ -#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000fffffL - -// CP_CE_IB2_CMD_BUFSZ -#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000fffffL - -// CP_IB1_CMD_BUFSZ -#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000fffffL - -// CP_IB2_CMD_BUFSZ -#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000fffffL - -// CP_ST_CMD_BUFSZ -#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000fffffL - -// CP_CE_INIT_BASE_LO -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L - -// CP_CE_INIT_BASE_HI -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000ffffL - -// CP_CE_INIT_BUFSZ -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL - -// CP_CE_IB1_BASE_LO -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL - -// CP_CE_IB1_BASE_HI -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000ffffL - -// CP_CE_IB1_BUFSZ -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL - -// CP_CE_IB2_BASE_LO -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL - -// CP_CE_IB2_BASE_HI -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000ffffL - -// CP_CE_IB2_BUFSZ -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL - -// CP_IB1_BASE_LO -#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL - -// CP_IB1_BASE_HI -#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000ffffL - -// CP_IB1_BUFSZ -#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL - -// CP_IB2_BASE_LO -#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL - -// CP_IB2_BASE_HI -#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000ffffL - -// CP_IB2_BUFSZ -#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL - -// CP_ST_BASE_LO -#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffcL - -// CP_ST_BASE_HI -#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000ffffL - -// CP_ST_BUFSZ -#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL - -// CPG_PERFCOUNTER1_LO -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CPG_PERFCOUNTER1_HI -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CPG_PERFCOUNTER0_LO -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CPG_PERFCOUNTER0_HI -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CPC_PERFCOUNTER1_LO -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CPC_PERFCOUNTER1_HI -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CPC_PERFCOUNTER0_LO -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CPC_PERFCOUNTER0_HI -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CPF_PERFCOUNTER1_LO -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CPF_PERFCOUNTER1_HI -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CPF_PERFCOUNTER0_LO -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// CPF_PERFCOUNTER0_HI -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// CPF_LATENCY_STATS_DATA -#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xffffffffL - -// CPG_LATENCY_STATS_DATA -#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xffffffffL - -// CPC_LATENCY_STATS_DATA -#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xffffffffL - -// CPG_PERFCOUNTER1_SELECT -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003ffL -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000ffc00L -#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0f000000L -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xf0000000L - -// CPG_PERFCOUNTER0_SELECT1 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003ffL -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000ffc00L -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0f000000L -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xf0000000L - -// CPG_PERFCOUNTER0_SELECT -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003ffL -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000ffc00L -#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0f000000L -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xf0000000L - -// CPC_PERFCOUNTER1_SELECT -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003ffL -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000ffc00L -#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0f000000L -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xf0000000L - -// CPC_PERFCOUNTER0_SELECT1 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003ffL -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000ffc00L -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0f000000L -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xf0000000L - -// CPC_PERFCOUNTER0_SELECT -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003ffL -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000ffc00L -#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0f000000L -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xf0000000L - -// CPF_PERFCOUNTER1_SELECT -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003ffL -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000ffc00L -#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0f000000L -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xf0000000L - -// CPF_PERFCOUNTER0_SELECT1 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003ffL -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000ffc00L -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0f000000L -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xf0000000L - -// CPF_PERFCOUNTER0_SELECT -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003ffL -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000ffc00L -#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0f000000L -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xf0000000L - -// CPF_TC_PERF_COUNTER_WINDOW_SELECT -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L - -// CPG_TC_PERF_COUNTER_WINDOW_SELECT -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001fL -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L - -// CPF_LATENCY_STATS_SELECT -#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000fL -#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L - -// CPG_LATENCY_STATS_SELECT -#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001fL -#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L - -// CPC_LATENCY_STATS_SELECT -#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L -#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L - -// CP_DRAW_OBJECT -#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffffL - -// CP_DRAW_OBJECT_COUNTER -#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000ffffL - -// CP_DRAW_WINDOW_MASK_HI -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffffL - -// CP_DRAW_WINDOW_HI -#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffffL - -// CP_DRAW_WINDOW_LO -#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000ffffL -#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000L - -// CP_DRAW_WINDOW_CNTL -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L -#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L - -// CP_PERFMON_CNTL -#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000f0L -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L - -// CGTT_CPC_CLK_CTRL -#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L - -// CGTT_CPF_CLK_CTRL -#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L - -// CGTT_CP_CLK_CTRL -#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L - -// CP_HYP_PFP_UCODE_ADDR -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003fffL - -// CP_PFP_UCODE_ADDR -#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003fffL - -// CP_HYP_PFP_UCODE_DATA -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_PFP_UCODE_DATA -#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_HYP_ME_UCODE_ADDR -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001fffL - -// CP_ME_RAM_RADDR -#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001fffL - -// CP_ME_RAM_WADDR -#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001fffL - -// CP_HYP_ME_UCODE_DATA -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_ME_RAM_DATA -#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL - -// CP_HYP_CE_UCODE_ADDR -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL - -// CP_CE_UCODE_ADDR -#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL - -// CP_HYP_CE_UCODE_DATA -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_CE_UCODE_DATA -#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_HYP_MEC1_UCODE_ADDR -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001ffffL - -// CP_MEC_ME1_UCODE_ADDR -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001ffffL - -// CP_HYP_MEC1_UCODE_DATA -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_MEC_ME1_UCODE_DATA -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_HYP_MEC2_UCODE_ADDR -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001ffffL - -// CP_MEC_ME2_UCODE_ADDR -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001ffffL - -// CP_HYP_MEC2_UCODE_DATA -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_MEC_ME2_UCODE_DATA -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL - -// CP_HYP_PFP_UCODE_CHKSUM -#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xffffffffL - -// CP_HYP_CE_UCODE_CHKSUM -#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xffffffffL - -// CP_HYP_ME_UCODE_CHKSUM -#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xffffffffL - -// CP_HYP_MEC_ME1_UCODE_CHKSUM -#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xffffffffL - -// CP_HYP_MEC_ME2_UCODE_CHKSUM -#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xffffffffL - -// CP_HYP_CONFIG_RANGE_BASE_1 -#define CP_HYP_CONFIG_RANGE_BASE_1__BASE_MASK 0x0003ffffL - -// CP_HYP_CONFIG_RANGE_END_1 -#define CP_HYP_CONFIG_RANGE_END_1__END_MASK 0x0003ffffL - -// CP_HYP_SHADER_RANGE_BASE -#define CP_HYP_SHADER_RANGE_BASE__BASE_MASK 0x0003ffffL - -// CP_HYP_SHADER_RANGE_END -#define CP_HYP_SHADER_RANGE_END__END_MASK 0x0003ffffL - -// CP_HYP_CONFIG_RANGE_BASE_2 -#define CP_HYP_CONFIG_RANGE_BASE_2__BASE_MASK 0x0003ffffL - -// CP_HYP_CONFIG_RANGE_END_2 -#define CP_HYP_CONFIG_RANGE_END_2__END_MASK 0x0003ffffL - -// CP_HYP_CONTEXT_RANGE_BASE -#define CP_HYP_CONTEXT_RANGE_BASE__BASE_MASK 0x0003ffffL - -// CP_HYP_CONTEXT_RANGE_END -#define CP_HYP_CONTEXT_RANGE_END__END_MASK 0x0003ffffL - -// CP_HYP_UCONFIG_RANGE_BASE -#define CP_HYP_UCONFIG_RANGE_BASE__BASE_MASK 0x0003ffffL - -// CP_HYP_UCONFIG_RANGE_END -#define CP_HYP_UCONFIG_RANGE_END__END_MASK 0x0003ffffL - -// CP_HYP_CPC_SECURE_REG0 -#define CP_HYP_CPC_SECURE_REG0__DATA_MASK 0xffffffffL - -// CP_HYP_CPC_SECURE_REG1 -#define CP_HYP_CPC_SECURE_REG1__DATA_MASK 0xffffffffL - -// CP_HYP_CPC_SECURE_REG2 -#define CP_HYP_CPC_SECURE_REG2__DATA_MASK 0xffffffffL - -// CP_HYP_CPC_SECURE_REG3 -#define CP_HYP_CPC_SECURE_REG3__DATA_MASK 0xffffffffL - -// CP_HYP_FIREWALL_MODIFIED_MASK -#define CP_HYP_FIREWALL_MODIFIED_MASK__ME0_PIPE_MASK_MASK 0x00000003L -#define CP_HYP_FIREWALL_MODIFIED_MASK__ME1_PIPE_MASK_MASK 0x00000f00L -#define CP_HYP_FIREWALL_MODIFIED_MASK__ME2_PIPE_MASK_MASK 0x000f0000L - -// CP_PSP_REG_PRIV_LEVEL_A -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL0_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL1_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL2_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL3_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL4_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL5_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL6_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL7_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL8_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL9_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL10_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL11_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL12_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL13_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL14_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL15_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_B -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL16_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL17_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL18_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL19_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL20_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL21_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL22_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL23_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL24_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL25_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL26_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL27_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL28_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL29_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL30_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL31_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_C -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL32_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL33_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL34_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL35_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL36_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL37_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL38_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL39_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL40_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL41_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL42_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL43_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL44_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL45_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL46_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL47_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_D -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL48_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL49_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL50_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL51_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL52_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL53_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL54_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL55_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL56_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL57_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL58_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL59_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL60_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL61_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL62_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL63_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_E -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL64_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL65_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL66_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL67_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL68_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL69_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL70_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL71_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL72_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL73_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL74_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL75_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL76_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL77_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL78_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL79_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_F -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL80_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL81_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL82_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL83_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL84_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL85_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL86_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL87_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL88_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL89_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL90_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL91_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL92_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL93_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL94_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL95_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_G -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL96_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL97_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL98_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL99_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL100_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL101_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL102_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL103_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL104_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL105_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL106_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL107_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL108_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL109_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL110_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL111_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_H -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL112_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL113_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL114_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL115_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL116_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL117_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL118_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL119_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL120_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL121_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL122_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL123_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL124_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL125_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL126_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL127_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_I -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL128_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL129_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL130_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL131_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL132_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL133_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL134_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL135_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL136_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL137_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL138_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL139_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL140_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL141_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL142_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL143_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_J -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL144_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL145_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL146_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL147_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL148_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL149_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL150_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL151_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL152_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL153_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL154_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL155_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL156_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL157_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL158_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL159_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_K -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL160_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL161_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL162_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL163_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL164_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL165_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL166_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL167_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL168_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL169_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL170_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL171_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL172_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL173_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL174_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL175_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL176_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL177_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL178_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL179_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL180_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL181_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL182_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL183_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL184_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL185_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL186_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL187_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL188_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL189_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL190_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL191_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_M -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL192_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL193_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL194_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL195_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL196_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL197_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL198_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL199_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL200_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL201_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL202_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL203_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL204_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL205_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL206_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL207_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_N -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL208_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL209_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL210_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL211_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL212_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL213_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL214_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL215_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL216_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL217_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL218_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL219_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL220_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL221_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL222_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL223_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_O -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL224_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL225_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL226_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL227_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL228_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL229_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL230_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL231_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL232_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL233_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL234_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL235_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL236_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL237_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL238_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL239_MASK 0xc0000000L - -// CP_PSP_REG_PRIV_LEVEL_P -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL240_MASK 0x00000003L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL241_MASK 0x0000000cL -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL242_MASK 0x00000030L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL243_MASK 0x000000c0L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL244_MASK 0x00000300L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL245_MASK 0x00000c00L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL246_MASK 0x00003000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL247_MASK 0x0000c000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL248_MASK 0x00030000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL249_MASK 0x000c0000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL250_MASK 0x00300000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL251_MASK 0x00c00000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL252_MASK 0x03000000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL253_MASK 0x0c000000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL254_MASK 0x30000000L -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL255_MASK 0xc0000000L - -// CPG_PSP_DEBUG -#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L -#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L - -// CPC_PSP_DEBUG -#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L -#define CPC_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L - -// CPF_PSP_DEBUG -#define CPF_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L -#define CPF_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L - -// CP_PSP_FIREWALL_MODIFIED_MASK -#define CP_PSP_FIREWALL_MODIFIED_MASK__ME0_PIPE_MASK_MASK 0x00000003L -#define CP_PSP_FIREWALL_MODIFIED_MASK__ME1_PIPE_MASK_MASK 0x00000f00L -#define CP_PSP_FIREWALL_MODIFIED_MASK__ME2_PIPE_MASK_MASK 0x000f0000L - -// SQ_SOPK -#define SQ_SOPK__SIMM16_MASK 0x0000ffffL -#define SQ_SOPK__SDST_MASK 0x007f0000L -#define SQ_SOPK__OP_MASK 0x0f800000L -#define SQ_SOPK__ENCODING_MASK 0xf0000000L - -// SQ_VINTRP -#define SQ_VINTRP__VSRC_MASK 0x000000ffL -#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L -#define SQ_VINTRP__ATTR_MASK 0x0000fc00L -#define SQ_VINTRP__OP_MASK 0x00030000L -#define SQ_VINTRP__VDST_MASK 0x03fc0000L -#define SQ_VINTRP__ENCODING_MASK 0xfc000000L - -// SQ_SCRATCH_0 -#define SQ_SCRATCH_0__OFFSET_MASK 0x00001fffL -#define SQ_SCRATCH_0__LDS_MASK 0x00002000L -#define SQ_SCRATCH_0__SEG_MASK 0x0000c000L -#define SQ_SCRATCH_0__GLC_MASK 0x00010000L -#define SQ_SCRATCH_0__SLC_MASK 0x00020000L -#define SQ_SCRATCH_0__OP_MASK 0x01fc0000L -#define SQ_SCRATCH_0__ENCODING_MASK 0xfc000000L - -// SQ_VOP3_0 -#define SQ_VOP3_0__VDST_MASK 0x000000ffL -#define SQ_VOP3_0__ABS_MASK 0x00000700L -#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L -#define SQ_VOP3_0__CLAMP_MASK 0x00008000L -#define SQ_VOP3_0__OP_MASK 0x03ff0000L -#define SQ_VOP3_0__ENCODING_MASK 0xfc000000L - -// SQ_FLAT_0 -#define SQ_FLAT_0__OFFSET_MASK 0x00000fffL -#define SQ_FLAT_0__LDS_MASK 0x00002000L -#define SQ_FLAT_0__SEG_MASK 0x0000c000L -#define SQ_FLAT_0__GLC_MASK 0x00010000L -#define SQ_FLAT_0__SLC_MASK 0x00020000L -#define SQ_FLAT_0__OP_MASK 0x01fc0000L -#define SQ_FLAT_0__ENCODING_MASK 0xfc000000L - -// SQ_SMEM_0 -#define SQ_SMEM_0__SBASE_MASK 0x0000003fL -#define SQ_SMEM_0__SDATA_MASK 0x00001fc0L -#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L -#define SQ_SMEM_0__NV_MASK 0x00008000L -#define SQ_SMEM_0__GLC_MASK 0x00010000L -#define SQ_SMEM_0__IMM_MASK 0x00020000L -#define SQ_SMEM_0__OP_MASK 0x03fc0000L -#define SQ_SMEM_0__ENCODING_MASK 0xfc000000L - -// SQ_VOP3P_0 -#define SQ_VOP3P_0__VDST_MASK 0x000000ffL -#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L -#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L -#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L -#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L -#define SQ_VOP3P_0__OP_MASK 0x007f0000L -#define SQ_VOP3P_0__ENCODING_MASK 0xff800000L - -// SQ_EXP_0 -#define SQ_EXP_0__EN_MASK 0x0000000fL -#define SQ_EXP_0__TGT_MASK 0x000003f0L -#define SQ_EXP_0__COMPR_MASK 0x00000400L -#define SQ_EXP_0__DONE_MASK 0x00000800L -#define SQ_EXP_0__VM_MASK 0x00001000L -#define SQ_EXP_0__ENCODING_MASK 0xfc000000L - -// SQ_VOP3P_1 -#define SQ_VOP3P_1__SRC0_MASK 0x000001ffL -#define SQ_VOP3P_1__SRC1_MASK 0x0003fe00L -#define SQ_VOP3P_1__SRC2_MASK 0x07fc0000L -#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L -#define SQ_VOP3P_1__NEG_MASK 0xe0000000L - -// SQ_SOP1 -#define SQ_SOP1__SSRC0_MASK 0x000000ffL -#define SQ_SOP1__OP_MASK 0x0000ff00L -#define SQ_SOP1__SDST_MASK 0x007f0000L -#define SQ_SOP1__ENCODING_MASK 0xff800000L - -// SQ_DS_0 -#define SQ_DS_0__OFFSET0_MASK 0x000000ffL -#define SQ_DS_0__OFFSET1_MASK 0x0000ff00L -#define SQ_DS_0__GDS_MASK 0x00010000L -#define SQ_DS_0__OP_MASK 0x01fe0000L -#define SQ_DS_0__ENCODING_MASK 0xfc000000L - -// SQ_VOP_DPP -#define SQ_VOP_DPP__SRC0_MASK 0x000000ffL -#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001ff00L -#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L -#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L -#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L -#define SQ_VOP_DPP__BANK_MASK_MASK 0x0f000000L -#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000L - -// SQ_MUBUF_0 -#define SQ_MUBUF_0__OFFSET_MASK 0x00000fffL -#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MUBUF_0__GLC_MASK 0x00004000L -#define SQ_MUBUF_0__LDS_MASK 0x00010000L -#define SQ_MUBUF_0__SLC_MASK 0x00020000L -#define SQ_MUBUF_0__OP_MASK 0x01fc0000L -#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000L - -// SQ_VOP1 -#define SQ_VOP1__SRC0_MASK 0x000001ffL -#define SQ_VOP1__OP_MASK 0x0001fe00L -#define SQ_VOP1__VDST_MASK 0x01fe0000L -#define SQ_VOP1__ENCODING_MASK 0xfe000000L - -// SQ_GLBL_0 -#define SQ_GLBL_0__OFFSET_MASK 0x00001fffL -#define SQ_GLBL_0__LDS_MASK 0x00002000L -#define SQ_GLBL_0__SEG_MASK 0x0000c000L -#define SQ_GLBL_0__GLC_MASK 0x00010000L -#define SQ_GLBL_0__SLC_MASK 0x00020000L -#define SQ_GLBL_0__OP_MASK 0x01fc0000L -#define SQ_GLBL_0__ENCODING_MASK 0xfc000000L - -// SQ_VOP2 -#define SQ_VOP2__SRC0_MASK 0x000001ffL -#define SQ_VOP2__VSRC1_MASK 0x0001fe00L -#define SQ_VOP2__VDST_MASK 0x01fe0000L -#define SQ_VOP2__OP_MASK 0x7e000000L -#define SQ_VOP2__ENCODING_MASK 0x80000000L - -// SQ_GLBL_1 -#define SQ_GLBL_1__ADDR_MASK 0x000000ffL -#define SQ_GLBL_1__DATA_MASK 0x0000ff00L -#define SQ_GLBL_1__SADDR_MASK 0x007f0000L -#define SQ_GLBL_1__NV_MASK 0x00800000L -#define SQ_GLBL_1__VDST_MASK 0xff000000L - -// SQ_MTBUF_0 -#define SQ_MTBUF_0__OFFSET_MASK 0x00000fffL -#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MTBUF_0__GLC_MASK 0x00004000L -#define SQ_MTBUF_0__OP_MASK 0x00078000L -#define SQ_MTBUF_0__DFMT_MASK 0x00780000L -#define SQ_MTBUF_0__NFMT_MASK 0x03800000L -#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000L - -// SQ_SOPP -#define SQ_SOPP__SIMM16_MASK 0x0000ffffL -#define SQ_SOPP__OP_MASK 0x007f0000L -#define SQ_SOPP__ENCODING_MASK 0xff800000L - -// SQ_VOP_SDWA -#define SQ_VOP_SDWA__SRC0_MASK 0x000000ffL -#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L -#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L -#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L -#define SQ_VOP_SDWA__OMOD_MASK 0x0000c000L -#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L -#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L -#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_SDWA__S0_MASK 0x00800000L -#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L -#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L -#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L -#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L -#define SQ_VOP_SDWA__S1_MASK 0x80000000L - -// SQ_VOP3_0_SDST_ENC -#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000ffL -#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007f00L -#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L -#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03ff0000L -#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000L - -// SQ_MIMG_0 -#define SQ_MIMG_0__OPM_MASK 0x00000001L -#define SQ_MIMG_0__DMASK_MASK 0x00000f00L -#define SQ_MIMG_0__UNORM_MASK 0x00001000L -#define SQ_MIMG_0__GLC_MASK 0x00002000L -#define SQ_MIMG_0__DA_MASK 0x00004000L -#define SQ_MIMG_0__A16_MASK 0x00008000L -#define SQ_MIMG_0__TFE_MASK 0x00010000L -#define SQ_MIMG_0__LWE_MASK 0x00020000L -#define SQ_MIMG_0__OP_MASK 0x01fc0000L -#define SQ_MIMG_0__SLC_MASK 0x02000000L -#define SQ_MIMG_0__ENCODING_MASK 0xfc000000L - -// SQ_VOPC -#define SQ_VOPC__SRC0_MASK 0x000001ffL -#define SQ_VOPC__VSRC1_MASK 0x0001fe00L -#define SQ_VOPC__OP_MASK 0x01fe0000L -#define SQ_VOPC__ENCODING_MASK 0xfe000000L - -// SQ_VOP_SDWA_SDST_ENC -#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000ffL -#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007f00L -#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L -#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L - -// SQ_EXP_1 -#define SQ_EXP_1__VSRC0_MASK 0x000000ffL -#define SQ_EXP_1__VSRC1_MASK 0x0000ff00L -#define SQ_EXP_1__VSRC2_MASK 0x00ff0000L -#define SQ_EXP_1__VSRC3_MASK 0xff000000L - -// SQ_SMEM_1 -#define SQ_SMEM_1__OFFSET_MASK 0x001fffffL -#define SQ_SMEM_1__SOFFSET_MASK 0xfe000000L - -// SQ_MTBUF_1 -#define SQ_MTBUF_1__VADDR_MASK 0x000000ffL -#define SQ_MTBUF_1__VDATA_MASK 0x0000ff00L -#define SQ_MTBUF_1__SRSRC_MASK 0x001f0000L -#define SQ_MTBUF_1__SLC_MASK 0x00400000L -#define SQ_MTBUF_1__TFE_MASK 0x00800000L -#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000L - -// SQ_FLAT_1 -#define SQ_FLAT_1__ADDR_MASK 0x000000ffL -#define SQ_FLAT_1__DATA_MASK 0x0000ff00L -#define SQ_FLAT_1__SADDR_MASK 0x007f0000L -#define SQ_FLAT_1__NV_MASK 0x00800000L -#define SQ_FLAT_1__VDST_MASK 0xff000000L - -// SQ_SOPC -#define SQ_SOPC__SSRC0_MASK 0x000000ffL -#define SQ_SOPC__SSRC1_MASK 0x0000ff00L -#define SQ_SOPC__OP_MASK 0x007f0000L -#define SQ_SOPC__ENCODING_MASK 0xff800000L - -// SQ_MIMG_1 -#define SQ_MIMG_1__VADDR_MASK 0x000000ffL -#define SQ_MIMG_1__VDATA_MASK 0x0000ff00L -#define SQ_MIMG_1__SRSRC_MASK 0x001f0000L -#define SQ_MIMG_1__SSAMP_MASK 0x03e00000L -#define SQ_MIMG_1__D16_MASK 0x80000000L - -// SQ_VOP3_1 -#define SQ_VOP3_1__SRC0_MASK 0x000001ffL -#define SQ_VOP3_1__SRC1_MASK 0x0003fe00L -#define SQ_VOP3_1__SRC2_MASK 0x07fc0000L -#define SQ_VOP3_1__OMOD_MASK 0x18000000L -#define SQ_VOP3_1__NEG_MASK 0xe0000000L - -// SQ_DS_1 -#define SQ_DS_1__ADDR_MASK 0x000000ffL -#define SQ_DS_1__DATA0_MASK 0x0000ff00L -#define SQ_DS_1__DATA1_MASK 0x00ff0000L -#define SQ_DS_1__VDST_MASK 0xff000000L - -// SQ_MUBUF_1 -#define SQ_MUBUF_1__VADDR_MASK 0x000000ffL -#define SQ_MUBUF_1__VDATA_MASK 0x0000ff00L -#define SQ_MUBUF_1__SRSRC_MASK 0x001f0000L -#define SQ_MUBUF_1__TFE_MASK 0x00800000L -#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000L - -// SQ_SOP2 -#define SQ_SOP2__SSRC0_MASK 0x000000ffL -#define SQ_SOP2__SSRC1_MASK 0x0000ff00L -#define SQ_SOP2__SDST_MASK 0x007f0000L -#define SQ_SOP2__OP_MASK 0x3f800000L -#define SQ_SOP2__ENCODING_MASK 0xc0000000L - -// SQ_INST -#define SQ_INST__ENCODING_MASK 0xffffffffL - -// SQ_SCRATCH_1 -#define SQ_SCRATCH_1__ADDR_MASK 0x000000ffL -#define SQ_SCRATCH_1__DATA_MASK 0x0000ff00L -#define SQ_SCRATCH_1__SADDR_MASK 0x007f0000L -#define SQ_SCRATCH_1__NV_MASK 0x00800000L -#define SQ_SCRATCH_1__VDST_MASK 0xff000000L - -// DIDT_IND_INDEX -#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffffL - -// DIDT_IND_DATA -#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffffL - -// DIDT_SQ_CTRL0 -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00ffff00L -#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xf8000000L - -// DIDT_SQ_CTRL1 -#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000ffffL -#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000L - -// DIDT_SQ_CTRL2 -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003fffL -#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000c000L -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L - -// DIDT_SQ_STALL_CTRL -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003fL -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000fc0L -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003f000L -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00fc0000L -#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xff000000L - -// DIDT_SQ_TUNING_CTRL -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003fffL -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0fffc000L - -// DIDT_SQ_STALL_AUTO_RELEASE_CTRL -#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00ffffffL - -// DIDT_SQ_CTRL3 -#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000cL -#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003e00L -#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003fc000L -#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L - -// DIDT_SQ_STALL_PATTERN_1_2 -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_SQ_STALL_PATTERN_3_4 -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_SQ_STALL_PATTERN_5_6 -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_SQ_STALL_PATTERN_7 -#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_SQ_WEIGHT0_3 -#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000ffL -#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000ff00L -#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00ff0000L -#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000L - -// DIDT_SQ_WEIGHT4_7 -#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000ffL -#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000ff00L -#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00ff0000L -#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000L - -// DIDT_SQ_WEIGHT8_11 -#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000ffL -#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000ff00L -#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00ff0000L -#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000L - -// DIDT_SQ_EDC_CTRL -#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001fe00L -#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xff800000L - -// DIDT_SQ_EDC_THRESHOLD -#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xffffffffL - -// DIDT_SQ_EDC_STALL_PATTERN_1_2 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_SQ_EDC_STALL_PATTERN_3_4 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_SQ_EDC_STALL_PATTERN_5_6 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_SQ_EDC_STALL_PATTERN_7 -#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_SQ_EDC_STATUS -#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000eL - -// DIDT_SQ_EDC_STALL_DELAY_1 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x000000ffL -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x0000ff00L -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x00ff0000L -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0xff000000L - -// DIDT_SQ_EDC_STALL_DELAY_2 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x000000ffL -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x0000ff00L -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x00ff0000L -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0xff000000L - -// DIDT_SQ_EDC_STALL_DELAY_3 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x000000ffL -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x0000ff00L -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x00ff0000L -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK 0xff000000L - -// DIDT_SQ_EDC_STALL_DELAY_4 -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK 0x000000ffL -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK 0x0000ff00L -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK 0x00ff0000L -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK 0xff000000L - -// DIDT_SQ_EDC_OVERFLOW -#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001fffeL - -// DIDT_SQ_EDC_ROLLING_POWER_DELTA -#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xffffffffL - -// DIDT_DB_CTRL0 -#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00ffff00L -#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xf8000000L - -// DIDT_DB_CTRL1 -#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000ffffL -#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000L - -// DIDT_DB_CTRL2 -#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003fffL -#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000c000L -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L - -// DIDT_DB_STALL_CTRL -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003fL -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000fc0L -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003f000L -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00fc0000L -#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xff000000L - -// DIDT_DB_TUNING_CTRL -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003fffL -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0fffc000L - -// DIDT_DB_STALL_AUTO_RELEASE_CTRL -#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00ffffffL - -// DIDT_DB_CTRL3 -#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000cL -#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003e00L -#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003fc000L -#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L - -// DIDT_DB_STALL_PATTERN_1_2 -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_DB_STALL_PATTERN_3_4 -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_DB_STALL_PATTERN_5_6 -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_DB_STALL_PATTERN_7 -#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_DB_WEIGHT0_3 -#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000ffL -#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000ff00L -#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00ff0000L -#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000L - -// DIDT_DB_WEIGHT4_7 -#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000ffL -#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000ff00L -#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00ff0000L -#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000L - -// DIDT_DB_WEIGHT8_11 -#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000ffL -#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000ff00L -#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00ff0000L -#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000L - -// DIDT_DB_EDC_CTRL -#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001fe00L -#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xff800000L - -// DIDT_DB_EDC_THRESHOLD -#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xffffffffL - -// DIDT_DB_EDC_STALL_PATTERN_1_2 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_DB_EDC_STALL_PATTERN_3_4 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_DB_EDC_STALL_PATTERN_5_6 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_DB_EDC_STALL_PATTERN_7 -#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_DB_EDC_STATUS -#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000eL - -// DIDT_DB_EDC_STALL_DELAY_1 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000003fL -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000fc0L -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x0003f000L -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x00fc0000L -#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xff000000L - -// DIDT_DB_EDC_OVERFLOW -#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001fffeL - -// DIDT_DB_EDC_ROLLING_POWER_DELTA -#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xffffffffL - -// DIDT_TD_CTRL0 -#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00ffff00L -#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xf8000000L - -// DIDT_TD_CTRL1 -#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000ffffL -#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000L - -// DIDT_TD_CTRL2 -#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003fffL -#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000c000L -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L - -// DIDT_TD_STALL_CTRL -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003fL -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000fc0L -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003f000L -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00fc0000L -#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xff000000L - -// DIDT_TD_TUNING_CTRL -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003fffL -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0fffc000L - -// DIDT_TD_STALL_AUTO_RELEASE_CTRL -#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00ffffffL - -// DIDT_TD_CTRL3 -#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000cL -#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003e00L -#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003fc000L -#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L - -// DIDT_TD_STALL_PATTERN_1_2 -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_TD_STALL_PATTERN_3_4 -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_TD_STALL_PATTERN_5_6 -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_TD_STALL_PATTERN_7 -#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_TD_WEIGHT0_3 -#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000ffL -#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000ff00L -#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00ff0000L -#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000L - -// DIDT_TD_WEIGHT4_7 -#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000ffL -#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000ff00L -#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00ff0000L -#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000L - -// DIDT_TD_WEIGHT8_11 -#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000ffL -#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000ff00L -#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00ff0000L -#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000L - -// DIDT_TD_EDC_CTRL -#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001fe00L -#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xff800000L - -// DIDT_TD_EDC_THRESHOLD -#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xffffffffL - -// DIDT_TD_EDC_STALL_PATTERN_1_2 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_TD_EDC_STALL_PATTERN_3_4 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_TD_EDC_STALL_PATTERN_5_6 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_TD_EDC_STALL_PATTERN_7 -#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_TD_EDC_STATUS -#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000eL - -// DIDT_TD_EDC_STALL_DELAY_1 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x000000ffL -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x0000ff00L -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x00ff0000L -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0xff000000L - -// DIDT_TD_EDC_STALL_DELAY_2 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x000000ffL -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x0000ff00L -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x00ff0000L -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0xff000000L - -// DIDT_TD_EDC_STALL_DELAY_3 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x000000ffL -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x0000ff00L -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x00ff0000L -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK 0xff000000L - -// DIDT_TD_EDC_STALL_DELAY_4 -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK 0x000000ffL -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK 0x0000ff00L -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14_MASK 0x00ff0000L -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15_MASK 0xff000000L - -// DIDT_TD_EDC_OVERFLOW -#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001fffeL - -// DIDT_TD_EDC_ROLLING_POWER_DELTA -#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xffffffffL - -// DIDT_TCP_CTRL0 -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00ffff00L -#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xf8000000L - -// DIDT_TCP_CTRL1 -#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000ffffL -#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000L - -// DIDT_TCP_CTRL2 -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003fffL -#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000c000L -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L - -// DIDT_TCP_STALL_CTRL -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003fL -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000fc0L -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003f000L -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00fc0000L -#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xff000000L - -// DIDT_TCP_TUNING_CTRL -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003fffL -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0fffc000L - -// DIDT_TCP_STALL_AUTO_RELEASE_CTRL -#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00ffffffL - -// DIDT_TCP_CTRL3 -#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000cL -#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003e00L -#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003fc000L -#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L - -// DIDT_TCP_STALL_PATTERN_1_2 -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_TCP_STALL_PATTERN_3_4 -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_TCP_STALL_PATTERN_5_6 -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_TCP_STALL_PATTERN_7 -#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_TCP_WEIGHT0_3 -#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000ffL -#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000ff00L -#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00ff0000L -#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000L - -// DIDT_TCP_WEIGHT4_7 -#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000ffL -#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000ff00L -#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00ff0000L -#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000L - -// DIDT_TCP_WEIGHT8_11 -#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000ffL -#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000ff00L -#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00ff0000L -#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000L - -// DIDT_TCP_EDC_CTRL -#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001fe00L -#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xff800000L - -// DIDT_TCP_EDC_THRESHOLD -#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xffffffffL - -// DIDT_TCP_EDC_STALL_PATTERN_1_2 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_TCP_EDC_STALL_PATTERN_3_4 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_TCP_EDC_STALL_PATTERN_5_6 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_TCP_EDC_STALL_PATTERN_7 -#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_TCP_EDC_STATUS -#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000eL - -// DIDT_TCP_EDC_STALL_DELAY_1 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x000000ffL -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x0000ff00L -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x00ff0000L -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0xff000000L - -// DIDT_TCP_EDC_STALL_DELAY_2 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x000000ffL -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x0000ff00L -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x00ff0000L -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0xff000000L - -// DIDT_TCP_EDC_STALL_DELAY_3 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x000000ffL -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x0000ff00L -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x00ff0000L -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK 0xff000000L - -// DIDT_TCP_EDC_STALL_DELAY_4 -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK 0x000000ffL -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK 0x0000ff00L -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14_MASK 0x00ff0000L -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15_MASK 0xff000000L - -// DIDT_TCP_EDC_OVERFLOW -#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001fffeL - -// DIDT_TCP_EDC_ROLLING_POWER_DELTA -#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xffffffffL - -// DIDT_DBR_CTRL0 -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00ffff00L -#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xf8000000L - -// DIDT_DBR_CTRL1 -#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000ffffL -#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000L - -// DIDT_DBR_CTRL2 -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003fffL -#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000c000L -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L -#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L - -// DIDT_DBR_STALL_CTRL -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003fL -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000fc0L -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003f000L -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00fc0000L -#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xff000000L - -// DIDT_DBR_TUNING_CTRL -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003fffL -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0fffc000L - -// DIDT_DBR_STALL_AUTO_RELEASE_CTRL -#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00ffffffL - -// DIDT_DBR_CTRL3 -#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000cL -#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003e00L -#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003fc000L -#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L - -// DIDT_DBR_STALL_PATTERN_1_2 -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_DBR_STALL_PATTERN_3_4 -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_DBR_STALL_PATTERN_5_6 -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_DBR_STALL_PATTERN_7 -#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_DBR_WEIGHT0_3 -#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000ffL -#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000ff00L -#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00ff0000L -#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000L - -// DIDT_DBR_WEIGHT4_7 -#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000ffL -#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000ff00L -#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00ff0000L -#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000L - -// DIDT_DBR_WEIGHT8_11 -#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000ffL -#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000ff00L -#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00ff0000L -#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000L - -// DIDT_DBR_EDC_CTRL -#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001f0L -#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001fe00L -#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xff800000L - -// DIDT_DBR_EDC_THRESHOLD -#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xffffffffL - -// DIDT_DBR_EDC_STALL_PATTERN_1_2 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007fffL -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7fff0000L -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L - -// DIDT_DBR_EDC_STALL_PATTERN_3_4 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007fffL -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7fff0000L -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L - -// DIDT_DBR_EDC_STALL_PATTERN_5_6 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007fffL -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7fff0000L -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L - -// DIDT_DBR_EDC_STALL_PATTERN_7 -#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007fffL -#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xffff8000L - -// DIDT_DBR_EDC_STATUS -#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000eL -#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xfffffff0L - -// DIDT_DBR_EDC_STALL_DELAY_1 -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000007L -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1_MASK 0x00000038L -#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xffffffc0L - -// DIDT_DBR_EDC_OVERFLOW -#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001fffeL - -// DIDT_DBR_EDC_ROLLING_POWER_DELTA -#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xffffffffL - -// DIDT_SQ_STALL_EVENT_COUNTER -#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xffffffffL - -// DIDT_DB_STALL_EVENT_COUNTER -#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xffffffffL - -// DIDT_TD_STALL_EVENT_COUNTER -#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xffffffffL - -// DIDT_TCP_STALL_EVENT_COUNTER -#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xffffffffL - -// DIDT_DBR_STALL_EVENT_COUNTER -#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xffffffffL - -// SX_DEBUG_BUSY -#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L -#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L -#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L -#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L -#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L -#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L -#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L -#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L -#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L -#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L -#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L -#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L -#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L -#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L -#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L -#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L -#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L -#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L -#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L -#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L -#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L -#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L -#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L -#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L -#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L - -// SX_DEBUG_BUSY_2 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x00000001L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x00000002L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x00000004L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x00000008L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x00000010L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x00000020L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x00000040L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000080L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000100L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000200L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000400L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000800L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00002000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00004000L -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00008000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00010000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00020000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00040000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00080000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00100000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00200000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00400000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00800000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x01000000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x02000000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x04000000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x08000000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x10000000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x20000000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x40000000L -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x80000000L - -// SX_DEBUG_BUSY_3 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x00000001L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x00000002L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x00000004L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x00000008L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x00000010L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x00000020L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x00000040L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000080L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000100L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000200L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000400L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000800L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00002000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00004000L -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00008000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00010000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00020000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00040000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00080000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00100000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00200000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00400000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00800000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x01000000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x02000000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x04000000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x08000000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x10000000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x20000000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x40000000L -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x80000000L - -// SX_DEBUG_BUSY_4 -#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY_MASK 0x00000001L -#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0_MASK 0x00000002L -#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE_MASK 0x00000004L -#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY_MASK 0x00000008L -#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY_MASK 0x00000010L -#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0_MASK 0x00000020L -#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE_MASK 0x00000040L -#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY_MASK 0x00000080L -#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY_MASK 0x00000100L -#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0_MASK 0x00000200L -#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE_MASK 0x00000400L -#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY_MASK 0x00000800L -#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY_MASK 0x00001000L -#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0_MASK 0x00002000L -#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE_MASK 0x00004000L -#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY_MASK 0x00008000L -#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY_MASK 0x00010000L -#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY_MASK 0x00020000L -#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY_MASK 0x00040000L -#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE_MASK 0x00080000L -#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY_MASK 0x00100000L -#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY_MASK 0x00200000L -#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE_MASK 0x00400000L -#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY_MASK 0x00800000L -#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY_MASK 0x01000000L -#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE_MASK 0x02000000L -#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY_MASK 0x04000000L -#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY_MASK 0x08000000L -#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE_MASK 0x10000000L -#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_MASK 0x20000000L -#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x40000000L -#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2_MASK 0x80000000L - -// SX_DEBUG_BUSY_5 -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000001L -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000002L -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000004L -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O_MASK 0x00000008L -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000010L -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000020L -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000040L -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3_MASK 0x00000080L -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4_MASK 0x00000100L -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5_MASK 0x00000200L -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O_MASK 0x00000400L -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_MASK 0x00000800L -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00001000L -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2_MASK 0x00002000L -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3_MASK 0x00004000L -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4_MASK 0x00008000L -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5_MASK 0x00010000L -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O_MASK 0x00020000L -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_MASK 0x00040000L -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x00080000L -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2_MASK 0x00100000L -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3_MASK 0x00200000L -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4_MASK 0x00400000L -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5_MASK 0x00800000L -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O_MASK 0x01000000L -#define SX_DEBUG_BUSY_5__RESERVED_MASK 0xfe000000L - -// SX_DEBUG_1 -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007fL -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L -#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L -#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffc000L - -// SX_PS_DOWNCONVERT -#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000fL -#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000f0L -#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000f00L -#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000f000L -#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000f0000L -#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00f00000L -#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0f000000L -#define SX_PS_DOWNCONVERT__MRT7_MASK 0xf0000000L - -// SX_BLEND_OPT_EPSILON -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000fL -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000f0L -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000f00L -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000f000L -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000f0000L -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00f00000L -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0f000000L -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xf0000000L - -// SX_BLEND_OPT_CONTROL -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L - -// SX_MRT0_BLEND_OPT -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_MRT1_BLEND_OPT -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_MRT2_BLEND_OPT -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_MRT3_BLEND_OPT -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_MRT4_BLEND_OPT -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_MRT5_BLEND_OPT -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_MRT6_BLEND_OPT -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_MRT7_BLEND_OPT -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L - -// SX_PERFCOUNTER0_LO -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SX_PERFCOUNTER0_HI -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SX_PERFCOUNTER1_LO -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SX_PERFCOUNTER1_HI -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SX_PERFCOUNTER2_LO -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SX_PERFCOUNTER2_HI -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SX_PERFCOUNTER3_LO -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// SX_PERFCOUNTER3_HI -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// SX_PERFCOUNTER0_SELECT -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L - -// SX_PERFCOUNTER1_SELECT -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L - -// SX_PERFCOUNTER2_SELECT -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L - -// SX_PERFCOUNTER3_SELECT -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003ffL -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L - -// SX_PERFCOUNTER0_SELECT1 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L - -// SX_PERFCOUNTER1_SELECT1 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L - -// CGTT_SX_CLK_CTRL0 -#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000f000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L - -// CGTT_SX_CLK_CTRL1 -#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000f000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL1__DBG_EN_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L - -// CGTT_SX_CLK_CTRL2 -#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000e000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL2__DBG_EN_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L - -// CGTT_SX_CLK_CTRL3 -#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000e000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL3__DBG_EN_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L - -// CGTT_SX_CLK_CTRL4 -#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000f000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL4__DBG_EN_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L - -// DB_DEBUG -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L -#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L -#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000c00L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L -#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L -#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0f000000L -#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L - -// DB_DEBUG2 -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L -#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L -#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L -#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003e00L -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L -#define DB_DEBUG2__RESERVED_MASK 0x00010000L -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L - -// DB_DEBUG3 -#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L -#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L -#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L -#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L - -// DB_DEBUG4 -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L -#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L -#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L -#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L -#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L -#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L -#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L -#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L -#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L -#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L -#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L -#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L -#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L -#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L -#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfff80000L - -// DB_RMI_CACHE_POLICY -#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L -#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L -#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L -#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L -#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L -#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L -#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L -#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L -#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L -#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L -#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L -#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L -#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L -#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L -#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L - -// DB_CREDIT_LIMIT -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001fL -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003e0L -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001c00L -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000L - -// DB_WATERMARKS -#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001fL -#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007e0L -#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L -#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000f8000L -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0ff00000L -#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L -#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L - -// DB_EXCEPTION_CONTROL -#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L -#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L -#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L - -// DB_SUBTILE_CONTROL -#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L -#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000cL -#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L -#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000c0L -#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L -#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000c00L -#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L -#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000c000L -#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L -#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000c0000L - -// DB_FREE_CACHELINES -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007fL -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003f80L -#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000fc000L -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00f00000L -#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xff000000L - -// DB_FIFO_DEPTH1 -#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001fL -#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003e0L -#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000fc00L -#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001f0000L -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000L - -// DB_FIFO_DEPTH2 -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000ffL -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007f00L -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01ff8000L -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000L - -// DB_RING_CONTROL -#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L - -// DB_MEM_ARB_WATERMARKS -#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L -#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L -#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L -#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L - -// DB_DFSM_CONFIG -#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L -#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L -#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L -#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L -#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007f00L - -// DB_DFSM_WATERMARK -#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000ffffL -#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xffff0000L - -// DB_DFSM_TILES_IN_FLIGHT -#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000ffffL -#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xffff0000L - -// DB_DFSM_PRIMS_IN_FLIGHT -#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000ffffL -#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xffff0000L - -// DB_DFSM_WATCHDOG -#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xffffffffL - -// DB_DFSM_FLUSH_ENABLE -#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003ffL -#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0f000000L -#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xf0000000L - -// DB_DFSM_FLUSH_AUX_EVENT -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000ffL -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000ff00L -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00ff0000L -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xff000000L - -// DB_READ_DEBUG_0 -#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffffL - -// DB_READ_DEBUG_1 -#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffffL - -// DB_READ_DEBUG_2 -#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffffL - -// DB_READ_DEBUG_3 -#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_4 -#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_5 -#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_6 -#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_7 -#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_8 -#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_9 -#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_A -#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_B -#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_C -#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_D -#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_E -#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffffL - -// DB_READ_DEBUG_F -#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffffL - -// DB_Z_READ_BASE -#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffffL - -// DB_Z_READ_BASE_HI -#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000ffL - -// DB_STENCIL_READ_BASE -#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffffL - -// DB_STENCIL_READ_BASE_HI -#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000ffL - -// DB_Z_WRITE_BASE -#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffffL - -// DB_Z_WRITE_BASE_HI -#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000ffL - -// DB_STENCIL_WRITE_BASE -#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffffL - -// DB_STENCIL_WRITE_BASE_HI -#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000ffL - -// DB_DFSM_CONTROL -#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L -#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L -#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L - -// DB_Z_INFO -#define DB_Z_INFO__FORMAT_MASK 0x00000003L -#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000cL -#define DB_Z_INFO__SW_MODE_MASK 0x000001f0L -#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L -#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L -#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L -#define DB_Z_INFO__MAXMIP_MASK 0x000f0000L -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L -#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L -#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L -#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L -#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L - -// DB_Z_INFO2 -#define DB_Z_INFO2__EPITCH_MASK 0x0000ffffL - -// DB_STENCIL_INFO -#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L -#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001f0L -#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L -#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L -#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L -#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L - -// DB_STENCIL_INFO2 -#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000ffffL - -// DB_DEPTH_SIZE -#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003fffL -#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3fff0000L - -// DB_DEPTH_VIEW -#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007ffL -#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00ffe000L -#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L -#define DB_DEPTH_VIEW__MIPID_MASK 0x3c000000L - -// DB_RENDER_FILTER -#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000ffffL - -// DB_RENDER_CONTROL -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L -#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L -#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L -#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L -#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000f00L -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L - -// DB_COUNT_CONTROL -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L -#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L -#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000f00L -#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000f000L -#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L -#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00f00000L -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0f000000L -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000L - -// DB_RENDER_OVERRIDE -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000cL -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L -#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03e00000L -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L - -// DB_RENDER_OVERRIDE2 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001cL -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001c0000L -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L -#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L - -// DB_EQAA -#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L -#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L -#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L -#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L -#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L -#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L - -// DB_SHADER_CONTROL -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L -#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L -#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L -#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L -#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L -#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L -#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L - -// DB_DEPTH_BOUNDS_MIN -#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffffL - -// DB_DEPTH_BOUNDS_MAX -#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffffL - -// DB_STENCIL_CLEAR -#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000ffL - -// DB_DEPTH_CLEAR -#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL - -// DB_HTILE_DATA_BASE -#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffffL - -// DB_HTILE_DATA_BASE_HI -#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000ffL - -// DB_HTILE_SURFACE -#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L -#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L -#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003f0L -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000fc00L -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L -#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L -#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L - -// DB_PRELOAD_CONTROL -#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000ffL -#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000ff00L -#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00ff0000L -#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000L - -// DB_STENCILREFMASK -#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000ffL -#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L -#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L -#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000L - -// DB_STENCILREFMASK_BF -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000ffL -#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000L - -// DB_SRESULTS_COMPARE_STATE0 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000ff0L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000ff000L -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L - -// DB_SRESULTS_COMPARE_STATE1 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000ff0L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000ff000L -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L - -// DB_DEPTH_CONTROL -#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L -#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L -#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L -#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L -#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L - -// DB_STENCIL_CONTROL -#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000fL -#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000f0L -#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000f00L -#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000f000L -#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000f0000L -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00f00000L - -// DB_ALPHA_TO_MASK -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000c00L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000c000L -#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L - -// DB_ZPASS_COUNT_LOW -#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffffL - -// DB_ZPASS_COUNT_HI -#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffffL - -// DB_OCCLUSION_COUNT0_LOW -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffffL - -// DB_OCCLUSION_COUNT0_HI -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffffL - -// DB_OCCLUSION_COUNT1_LOW -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffffL - -// DB_OCCLUSION_COUNT1_HI -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffffL - -// DB_OCCLUSION_COUNT2_LOW -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffffL - -// DB_OCCLUSION_COUNT2_HI -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffffL - -// DB_OCCLUSION_COUNT3_LOW -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffffL - -// DB_OCCLUSION_COUNT3_HI -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffffL - -// DB_PERFCOUNTER0_LO -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// DB_PERFCOUNTER1_LO -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// DB_PERFCOUNTER2_LO -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// DB_PERFCOUNTER3_LO -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// DB_PERFCOUNTER0_HI -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// DB_PERFCOUNTER1_HI -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// DB_PERFCOUNTER2_HI -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// DB_PERFCOUNTER3_HI -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// DB_PERFCOUNTER0_SELECT -#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// DB_PERFCOUNTER1_SELECT -#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// DB_PERFCOUNTER2_SELECT -#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003ffL -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// DB_PERFCOUNTER3_SELECT -#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003ffL -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0f000000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// DB_PERFCOUNTER0_SELECT1 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// DB_PERFCOUNTER1_SELECT1 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// DB_CGTT_CLK_CTRL_0 -#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000fL -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000f000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L - -// PA_CL_ENHANCE -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L -#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L -#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L -#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L -#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L -#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L -#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L -#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L -#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L -#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001c000L -#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L -#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L -#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L -#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L - -// PA_CL_RESET_DEBUG -#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L - -// PA_SIDEBAND_REQUEST_DELAYS -#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000ffffL -#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xffff0000L - -// PA_UTCL1_CNTL1 -#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L -#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000ff80L -#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L -#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L -#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000L - -// PA_UTCL1_CNTL2 -#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000ffL -#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L -#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L -#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L -#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01e00000L -#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L -#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -#define PA_UTCL1_CNTL2__RESERVED_MASK 0xf8000000L - -// PA_SC_ENHANCE -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L -#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L -#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L - -// PA_SC_ENHANCE_1 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L -#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L -#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L -#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L -#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L -#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L -#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L -#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L -#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L -#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L -#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L -#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L -#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L -#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L -#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L -#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L -#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L -#define PA_SC_ENHANCE_1__RSVD_MASK 0xff800000L - -// PA_SC_DSM_CNTL -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L - -// PA_SC_TILE_STEERING_CREST_OVERRIDE -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L - -// PA_SC_FIFO_SIZE -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003fL -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007fc0L -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001f8000L -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xffe00000L - -// PA_SC_IF_FIFO_SIZE -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003fL -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000fc0L -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003f000L -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00fc0000L - -// PA_SC_PKR_WAVE_TABLE_CNTL -#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003fL - -// PA_SC_FORCE_EOV_MAX_CNTS -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000ffffL -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000L - -// PA_SC_BINNER_EVENT_CNTL_0 -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000cL -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000c0L -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000c00L -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000c000L -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000c0000L -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00c00000L -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0c000000L -#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xc0000000L - -// PA_SC_BINNER_EVENT_CNTL_1 -#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000cL -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000c0L -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000c00L -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000c000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000c0000L -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00c00000L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0c000000L -#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xc0000000L - -// PA_SC_BINNER_EVENT_CNTL_2 -#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000cL -#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000c0L -#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000c00L -#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000c000L -#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000c0000L -#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00c00000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0c000000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xc0000000L - -// PA_SC_BINNER_EVENT_CNTL_3 -#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000cL -#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000c0L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000c00L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000c000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000c0000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00c00000L -#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0c000000L -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xc0000000L - -// PA_SC_BINNER_TIMEOUT_COUNTER -#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xffffffffL - -// PA_SC_BINNER_PERF_CNTL_0 -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003ffL -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000ffc00L -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L - -// PA_SC_BINNER_PERF_CNTL_1 -#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001fL -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003e0L -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03fffc00L - -// PA_SC_BINNER_PERF_CNTL_2 -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007ffL -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003ff800L - -// PA_SC_BINNER_PERF_CNTL_3 -#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xffffffffL - -// PA_SC_P3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L - -// PA_SC_HP3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L - -// PA_SC_TRAP_SCREEN_HV_LOCK -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L - -// PA_CL_CNTL_STATUS -#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L -#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L -#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L - -// PA_SU_CNTL_STATUS -#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L - -// PA_SC_FIFO_DEPTH_CNTL -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003ffL - -// PA_SU_DEBUG_CNTL -#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL - -// PA_SU_DEBUG_DATA -#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL - -// PA_SC_DEBUG_CNTL -#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x000000ffL -#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS_MASK 0x00000100L - -// PA_SC_DEBUG_DATA -#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_1 -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_2 -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_3 -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_4 -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_5 -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_6 -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_7 -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_8 -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_9 -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_10 -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_11 -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_12 -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_13 -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_14 -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XSCALE_15 -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_1 -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_2 -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_3 -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_4 -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_5 -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_6 -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_7 -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_8 -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_9 -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_10 -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_11 -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_12 -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_13 -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_14 -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_XOFFSET_15 -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_1 -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_2 -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_3 -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_4 -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_5 -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_6 -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_7 -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_8 -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_9 -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_10 -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_11 -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_12 -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_13 -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_14 -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YSCALE_15 -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_1 -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_2 -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_3 -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_4 -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_5 -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_6 -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_7 -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_8 -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_9 -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_10 -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_11 -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_12 -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_13 -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_14 -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_YOFFSET_15 -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_1 -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_2 -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_3 -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_4 -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_5 -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_6 -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_7 -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_8 -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_9 -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_10 -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_11 -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_12 -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_13 -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_14 -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZSCALE_15 -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_1 -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_2 -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_3 -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_4 -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_5 -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_6 -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_7 -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_8 -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_9 -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_10 -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_11 -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_12 -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_13 -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_14 -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VPORT_ZOFFSET_15 -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffffL - -// PA_CL_VTE_CNTL -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L -#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L -#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L -#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L - -// PA_CL_VS_OUT_CNTL -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L - -// PA_CL_NANINF_CNTL -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L - -// PA_CL_CLIP_CNTL -#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L -#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L -#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L -#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L -#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L -#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L -#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000c000L -#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L -#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L - -// PA_CL_GB_VERT_CLIP_ADJ -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_GB_VERT_DISC_ADJ -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_GB_HORZ_CLIP_ADJ -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_GB_HORZ_DISC_ADJ -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_0_X -#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_0_Y -#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_0_Z -#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_0_W -#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_1_X -#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_1_Y -#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_1_Z -#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_1_W -#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_2_X -#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_2_Y -#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_2_Z -#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_2_W -#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_3_X -#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_3_Y -#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_3_Z -#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_3_W -#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_4_X -#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_4_Y -#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_4_Z -#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_4_W -#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_5_X -#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_5_Y -#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_5_Z -#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_UCP_5_W -#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_POINT_X_RAD -#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_POINT_Y_RAD -#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_POINT_SIZE -#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffffL - -// PA_CL_POINT_CULL_RAD -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffffL - -// PA_SU_VTX_CNTL -#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L -#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L -#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L - -// PA_SU_POINT_SIZE -#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL -#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L - -// PA_SU_POINT_MINMAX -#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL -#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L - -// PA_SU_LINE_CNTL -#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL - -// PA_SU_LINE_STIPPLE_CNTL -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L - -// PA_SU_LINE_STIPPLE_SCALE -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffffL - -// PA_SU_PRIM_FILTER_CNTL -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000ff00L -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L - -// PA_SU_SMALL_PRIM_FILTER_CNTL -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L - -// PA_CL_OBJPRIM_ID_CNTL -#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L -#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L -#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L - -// PA_CL_NGG_CNTL -#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L -#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L - -// PA_SU_OVER_RASTERIZATION_CNTL -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L -#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L - -// PA_SU_SC_MODE_CNTL -#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L -#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L -#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L -#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L -#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L -#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L - -// PA_SU_POLY_OFFSET_DB_FMT_CNTL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000ffL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L - -// PA_SU_POLY_OFFSET_CLAMP -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffffL - -// PA_SU_POLY_OFFSET_FRONT_SCALE -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL - -// PA_SU_POLY_OFFSET_FRONT_OFFSET -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL - -// PA_SU_POLY_OFFSET_BACK_SCALE -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL - -// PA_SU_POLY_OFFSET_BACK_OFFSET -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL - -// PA_SU_HARDWARE_SCREEN_OFFSET -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001ffL -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01ff0000L - -// PA_SC_AA_CONFIG -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L -#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0c000000L - -// PA_SC_AA_MASK_X0Y0_X1Y0 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000ffffL -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000L - -// PA_SC_AA_MASK_X0Y1_X1Y1 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000ffffL -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000L - -// PA_SC_SHADER_CONTROL -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L -#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L -#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L - -// PA_SC_BINNER_CNTL_0 -#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L -#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001c00L -#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003e000L -#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L -#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07f80000L -#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L - -// PA_SC_BINNER_CNTL_1 -#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000ffffL -#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xffff0000L - -// PA_SC_CONSERVATIVE_RASTERIZATION_CNTL -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001eL -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003c0L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK \ - 0x00008000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L - -// PA_SC_NGG_MODE_CNTL -#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007ffL - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000L - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000fL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000f0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000f00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000f000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000f0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00f00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0f000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000L - -// PA_SC_CENTROID_PRIORITY_0 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000fL -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000f0L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000f00L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000f000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000f0000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00f00000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0f000000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000L - -// PA_SC_CENTROID_PRIORITY_1 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000fL -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000f0L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000f00L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000f000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000f0000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00f00000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0f000000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000L - -// PA_SC_CLIPRECT_0_TL -#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_0_BR -#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_1_TL -#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_1_BR -#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_2_TL -#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_2_BR -#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_3_TL -#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_3_BR -#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007fffL -#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_CLIPRECT_RULE -#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000ffffL - -// PA_SC_EDGERULE -#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000fL -#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000f0L -#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000f00L -#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003f000L -#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00fc0000L -#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0f000000L -#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000L - -// PA_SC_LINE_CNTL -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L -#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L - -// PA_SC_LINE_STIPPLE -#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L - -// PA_SC_MODE_CNTL_0 -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L -#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L -#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L -#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L - -// PA_SC_MODE_CNTL_1 -#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00f00000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L - -// PA_SC_RASTER_CONFIG -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000cL -#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L -#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L -#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L -#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L -#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000c00L -#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L -#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000c000L -#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L -#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000c0000L -#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L -#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L -#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1c000000L -#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xe0000000L - -// PA_SC_RASTER_CONFIG_1 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001cL -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000e0L - -// PA_SC_SCREEN_EXTENT_CONTROL -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000cL - -// PA_SC_TILE_STEERING_OVERRIDE -#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L - -// PA_SC_RIGHT_VERT_GRID -#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000ffL -#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000ff00L -#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00ff0000L -#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xff000000L - -// PA_SC_LEFT_VERT_GRID -#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000ffL -#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000ff00L -#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00ff0000L -#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xff000000L - -// PA_SC_HORIZ_GRID -#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000ffL -#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000ff00L -#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00ff0000L -#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xff000000L - -// PA_SC_FOV_WINDOW_LR -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000ffL -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000ff00L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00ff0000L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xff000000L - -// PA_SC_FOV_WINDOW_TB -#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000ffL -#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000ff00L - -// PA_SC_GENERIC_SCISSOR_TL -#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007fffL -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_GENERIC_SCISSOR_BR -#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007fffL -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_SCREEN_SCISSOR_TL -#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000ffffL -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000L - -// PA_SC_SCREEN_SCISSOR_BR -#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000ffffL -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000L - -// PA_SC_WINDOW_OFFSET -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000ffffL -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000L - -// PA_SC_WINDOW_SCISSOR_TL -#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007fffL -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_WINDOW_SCISSOR_BR -#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007fffL -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_0_TL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_1_TL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_2_TL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_3_TL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_4_TL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_5_TL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_6_TL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_7_TL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_8_TL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_9_TL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_10_TL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_11_TL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_12_TL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_13_TL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_14_TL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_15_TL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000L -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L - -// PA_SC_VPORT_SCISSOR_0_BR -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_1_BR -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_2_BR -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_3_BR -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_4_BR -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_5_BR -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_6_BR -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_7_BR -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_8_BR -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_9_BR -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_10_BR -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_11_BR -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_12_BR -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_13_BR -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_14_BR -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_SCISSOR_15_BR -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007fffL -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000L - -// PA_SC_VPORT_ZMIN_0 -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_1 -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_2 -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_3 -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_4 -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_5 -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_6 -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_7 -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_8 -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_9 -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_10 -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_11 -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_12 -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_13 -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_14 -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMIN_15 -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_0 -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_1 -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_2 -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_3 -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_4 -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_5 -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_6 -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_7 -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_8 -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_9 -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_10 -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_11 -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_12 -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_13 -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_14 -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SC_VPORT_ZMAX_15 -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffffL - -// PA_SU_LINE_STIPPLE_VALUE -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00ffffffL - -// PA_SC_LINE_STIPPLE_STATE -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L - -// PA_SC_SCREEN_EXTENT_MIN_0 -#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000L - -// PA_SC_SCREEN_EXTENT_MAX_0 -#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000L - -// PA_SC_SCREEN_EXTENT_MIN_1 -#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000L - -// PA_SC_SCREEN_EXTENT_MAX_1 -#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000ffffL -#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000L - -// PA_SC_P3D_TRAP_SCREEN_HV_EN -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L - -// PA_SC_P3D_TRAP_SCREEN_H -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003fffL - -// PA_SC_P3D_TRAP_SCREEN_V -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003fffL - -// PA_SC_P3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000ffffL - -// PA_SC_P3D_TRAP_SCREEN_COUNT -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000ffffL - -// PA_SC_HP3D_TRAP_SCREEN_HV_EN -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L - -// PA_SC_HP3D_TRAP_SCREEN_H -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003fffL - -// PA_SC_HP3D_TRAP_SCREEN_V -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003fffL - -// PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000ffffL - -// PA_SC_HP3D_TRAP_SCREEN_COUNT -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000ffffL - -// PA_SC_TRAP_SCREEN_HV_EN -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L - -// PA_SC_TRAP_SCREEN_H -#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003fffL - -// PA_SC_TRAP_SCREEN_V -#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003fffL - -// PA_SC_TRAP_SCREEN_OCCURRENCE -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000ffffL - -// PA_SC_TRAP_SCREEN_COUNT -#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000ffffL - -// PA_SU_PERFCOUNTER0_LO -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SU_PERFCOUNTER0_HI -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL - -// PA_SU_PERFCOUNTER1_LO -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SU_PERFCOUNTER1_HI -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL - -// PA_SU_PERFCOUNTER2_LO -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SU_PERFCOUNTER2_HI -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL - -// PA_SU_PERFCOUNTER3_LO -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SU_PERFCOUNTER3_HI -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL - -// PA_SC_PERFCOUNTER0_LO -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER0_HI -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER1_LO -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER1_HI -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER2_LO -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER2_HI -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER3_LO -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER3_HI -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER4_LO -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER4_HI -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER5_LO -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER5_HI -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER6_LO -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER6_HI -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER7_LO -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// PA_SC_PERFCOUNTER7_HI -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// PA_SU_PERFCOUNTER0_SELECT -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L - -// PA_SU_PERFCOUNTER0_SELECT1 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L - -// PA_SU_PERFCOUNTER1_SELECT -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L - -// PA_SU_PERFCOUNTER1_SELECT1 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L - -// PA_SU_PERFCOUNTER2_SELECT -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003ffL -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L - -// PA_SU_PERFCOUNTER3_SELECT -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003ffL -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L - -// PA_SC_PERFCOUNTER0_SELECT -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003ffL -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L - -// PA_SC_PERFCOUNTER0_SELECT1 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L - -// PA_SC_PERFCOUNTER1_SELECT -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003ffL - -// PA_SC_PERFCOUNTER2_SELECT -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003ffL - -// PA_SC_PERFCOUNTER3_SELECT -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003ffL - -// PA_SC_PERFCOUNTER4_SELECT -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003ffL - -// PA_SC_PERFCOUNTER5_SELECT -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003ffL - -// PA_SC_PERFCOUNTER6_SELECT -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003ffL - -// PA_SC_PERFCOUNTER7_SELECT -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003ffL - -// CGTT_PA_CLK_CTRL -#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK 0x00800000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L - -// CGTT_SC_CLK_CTRL0 -#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL -#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L -#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L -#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L - -// CGTT_SC_CLK_CTRL1 -#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL -#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L -#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L -#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L - -// CLIPPER_DEBUG_REG00 -#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL -#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L -#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L -#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L -#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L - -// CLIPPER_DEBUG_REG01 -#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL -#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L -#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L -#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L -#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L -#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L -#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L -#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L - -// CLIPPER_DEBUG_REG02 -#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L -#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L -#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L -#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L - -// CLIPPER_DEBUG_REG03 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG04 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG05 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG06 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG07 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG08 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG09 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG10 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG11 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L -#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L -#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L -#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L -#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L - -// CLIPPER_DEBUG_REG12 -#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL -#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG13 -#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L -#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L -#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L -#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L -#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L -#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L -#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L -#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L -#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L -#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L -#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L -#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L - -// CLIPPER_DEBUG_REG14 -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L -#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L -#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L -#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG15 -#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L -#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG16 -#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG17 -#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG18 -#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L - -// CLIPPER_DEBUG_REG19 -#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL -#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L -#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L -#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L -#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L -#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L -#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L -#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L -#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L -#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L - -// SXIFCCG_DEBUG_REG0 -#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x0000003fL -#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x000001c0L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00000e00L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x0000f000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x03ff0000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x0c000000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000L - -// SXIFCCG_DEBUG_REG1 -#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x0000007fL -#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00000380L -#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x00007c00L -#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L -#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0x000f0000L -#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00300000L -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x00400000L -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x00800000L -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0x0f000000L -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000L - -// SXIFCCG_DEBUG_REG2 -#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x0000007fL -#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000180L -#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x00007e00L -#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x00008000L -#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x007f0000L -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x03800000L -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000L - -// SXIFCCG_DEBUG_REG3 -#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0x000000ffL -#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x00000f00L -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x00001000L -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x00002000L -#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x001fc000L -#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00600000L -#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00800000L -#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x01000000L -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x02000000L -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x04000000L -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x08000000L -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000L -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000L -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000L -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000L - -// SETUP_DEBUG_REG0 -#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x00000003L -#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000003cL -#define SETUP_DEBUG_REG0__pmode_state_MASK 0x00003f00L -#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00004000L -#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00008000L -#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x00030000L -#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00040000L -#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00080000L -#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00100000L -#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00200000L -#define SETUP_DEBUG_REG0__event_id_gated_MASK 0x0fc00000L -#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000L -#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000L -#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000L -#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000L - -// SETUP_DEBUG_REG1 -#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0x0000ffffL -#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000L - -// SETUP_DEBUG_REG2 -#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0x0000ffffL -#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000L - -// SETUP_DEBUG_REG3 -#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0x0000ffffL -#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000L - -// SETUP_DEBUG_REG4 -#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x00003fffL -#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00004000L -#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00008000L -#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x00070000L -#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00080000L -#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x00700000L -#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00800000L -#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x03000000L -#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000L -#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000L -#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000L - -// SETUP_DEBUG_REG5 -#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x00003fffL -#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x0fffc000L -#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000L -#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000L -#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000L - -// PA_SC_DEBUG_REG0 -#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x00000003L -#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0x0000000cL - -// PA_SC_DEBUG_REG1 -#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x00000003L -#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0x0000000cL - -// RMI_GENERAL_CNTL -#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L -#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001fffeL -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L -#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L -#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L -#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01e00000L -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L - -// RMI_GENERAL_CNTL1 -#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000fL -#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L -#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000c0L -#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L -#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L -#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L - -// RMI_GENERAL_STATUS -#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L -#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L -#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L -#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L -#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L -#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L -#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L -#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L -#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L -#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L -#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L -#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L -#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L -#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L -#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1fe00000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L -#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L - -// RMI_SUBBLOCK_STATUS0 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007fL -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000fe00L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L -#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0ffc0000L - -// RMI_SUBBLOCK_STATUS1 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003ffL -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000ffc00L -#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3ff00000L - -// RMI_SUBBLOCK_STATUS2 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001ffL -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003fe00L - -// RMI_SUBBLOCK_STATUS3 -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003ffL -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000ffc00L - -// RMI_XBAR_CONFIG -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003cL -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L -#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000f00L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L - -// RMI_PROBE_POP_LOGIC_CNTL -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007fL -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L -#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001fc00L -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L - -// RMI_UTC_XNACK_N_MISC_CNTL -#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000ffL -#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000f00L -#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L -#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L - -// RMI_DEMUX_CNTL -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003fc0L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000c000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3fc00000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xc0000000L - -// RMI_UTCL1_CNTL1 -#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000ff80L -#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L -#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000L - -// RMI_UTCL1_CNTL2 -#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000ffL -#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01e00000L -#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L -#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L - -// RMI_UTC_UNIT_CONFIG -#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000ffffL - -// RMI_TCIW_FORMATTER0_CNTL -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001feL -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007fe00L -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07f80000L -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L -#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L -#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L - -// RMI_TCIW_FORMATTER1_CNTL -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001feL -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007fe00L -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07f80000L -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L -#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L -#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L - -// RMI_SCOREBOARD_CNTL -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001ffe00L - -// RMI_SCOREBOARD_STATUS0 -#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003fffcL -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L -#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L - -// RMI_SCOREBOARD_STATUS1 -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000fffL -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L -#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07ff8000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L - -// RMI_SCOREBOARD_STATUS2 -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000fffL -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01ffe000L -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L - -// RMI_XBAR_ARBITER_CONFIG -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000c0L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000ff00L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00c00000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xff000000L - -// RMI_XBAR_ARBITER_CONFIG_1 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000ffL -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000ff00L -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00ff0000L -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xff000000L - -// RMI_CLOCK_CNTRL -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001fL -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003e0L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007c00L -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000f8000L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01f00000L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3e000000L - -// RMI_UTCL1_STATUS -#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L - -// RMI_DEBUG0 -#define RMI_DEBUG0__RTS_RTR_DEBUG_MUX_SEL_MASK 0x0000001fL -#define RMI_DEBUG0__XBAR_ARB_DEBUG_MUX_SEL_MASK 0x00000060L -#define RMI_DEBUG0__DEMUX_ARB_DEBUG_MUX_SEL_MASK 0x00000180L -#define RMI_DEBUG0__DISABLE_MUX_SEL_MASK 0x00003e00L -#define RMI_DEBUG0__DISABLE_MUX_SEL_UPDATE_MASK 0x00004000L -#define RMI_DEBUG0__DISABLE_STATUS_MUX_SEL_MASK 0x000f8000L -#define RMI_DEBUG0__STALL_DEBUG_MUX_SEL_MASK 0x01f00000L -#define RMI_DEBUG0__UTCL1_INFLIGHT_WATERMARK_MASK 0xfe000000L - -// RMI_DEBUG1 -#define RMI_DEBUG1__REQ_BYPASS_DETECTION_DEBUG_MUX_SEL_MASK 0x0000000fL -#define RMI_DEBUG1__CONSUMER_FIFO_CNT_MUX_SEL_MASK 0x00000030L - -// RMI_DEBUG2 -#define RMI_DEBUG2__DEMUX_ARB_DEBUG_MUX_STATE_MASK 0x0000000fL -#define RMI_DEBUG2__DISABLE_STATUS_MUX_STATE_MASK 0x00000010L -#define RMI_DEBUG2__RTS_RTR_DEBUG_MUX_STATE_MASK 0x00000060L -#define RMI_DEBUG2__CONSUMER_FIFO_DEBIT_CNT_MASK 0x00001f80L -#define RMI_DEBUG2__CONSUMER_FIFO_FREE_SPACE_CNT_MASK 0x0007e000L - -// RMI_DEBUG3 -#define RMI_DEBUG3__XBAR_ARB_DEBUG_MUX_STATE_MASK 0x0000000fL -#define RMI_DEBUG3__UTC_IN_STALL_SOURCE_MASK 0x00000070L -#define RMI_DEBUG3__UTC_OUT_STALL_SOURCE_MASK 0x00000380L -#define RMI_DEBUG3__TCIW0_PRODUCER_CREDIT_CNT_MASK 0x0000fc00L -#define RMI_DEBUG3__TCIW1_PRODUCER_CREDIT_CNT_MASK 0x003f0000L -#define RMI_DEBUG3__STALL_DEBUG_MUX_STATE_MASK 0x03c00000L -#define RMI_DEBUG3__REQ_BYPASS_DETECTION_DEBUG_MUX_STATE_MASK 0x1c000000L -#define RMI_DEBUG3__UTCL1_INFLIGHT_WATERMARK_HIT_PROBE0_MASK 0x20000000L -#define RMI_DEBUG3__UTCL1_INFLIGHT_WATERMARK_HIT_PROBE1_MASK 0x40000000L - -// RMI_DEBUG4 -#define RMI_DEBUG4__FORCE_NON_RETRY_XNACK_PER_VMID_MASK 0x0000ffffL -#define RMI_DEBUG4__FORCE_INSTANT_RETRY_PER_VMID_MASK 0xffff0000L - -// RMI_XNACK_DEBUG -#define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000ffffL - -// RMI_SPARE -#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L -#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L -#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L -#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L -#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L -#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L -#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L -#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L -#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000ff00L -#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xffff0000L - -// RMI_SPARE_1 -#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L -#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L -#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L -#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L -#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L -#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L -#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L -#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L -#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000ff00L -#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xffff0000L - -// RMI_SPARE_2 -#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L -#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L -#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L -#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L -#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L -#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L -#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L -#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L -#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000f00L -#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000f000L -#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00ff0000L -#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xff000000L - -// RMI_PERFCOUNTER0_LO -#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// RMI_PERFCOUNTER1_LO -#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// RMI_PERFCOUNTER2_LO -#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// RMI_PERFCOUNTER3_LO -#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL - -// RMI_PERFCOUNTER0_HI -#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// RMI_PERFCOUNTER1_HI -#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// RMI_PERFCOUNTER2_HI -#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// RMI_PERFCOUNTER3_HI -#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL - -// RMI_PERFCOUNTER0_SELECT -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007fc00L -#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L - -// RMI_PERFCOUNTER0_SELECT1 -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// RMI_PERFCOUNTER1_SELECT -#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL -#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L - -// RMI_PERFCOUNTER2_SELECT -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007fc00L -#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L - -// RMI_PERFCOUNTER2_SELECT1 -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001ffL -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007fc00L -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0f000000L -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xf0000000L - -// RMI_PERFCOUNTER3_SELECT -#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL -#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L - -// RMI_PERF_COUNTER_CNTL -#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L -#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000cL -#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000c0L -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003c00L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007c000L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01f80000L -#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L -#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L - -// RMI_CGTT_SCLK_CTRL -#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - -// port_a_addr -#define port_a_addr__Index_MASK 0x000000ffL -#define port_a_addr__Reserved_MASK 0x7fffff00L -#define port_a_addr__ReadEnable_MASK 0x80000000L - -// port_a_data_lo -#define port_a_data_lo__Data_MASK 0xffffffffL - -// port_a_data_hi -#define port_a_data_hi__Data_MASK 0xffffffffL - -// port_b_addr -#define port_b_addr__Index_MASK 0x000000ffL -#define port_b_addr__Reserved_MASK 0x7fffff00L -#define port_b_addr__ReadEnable_MASK 0x80000000L - -// port_b_data_lo -#define port_b_data_lo__Data_MASK 0xffffffffL - -// port_b_data_hi -#define port_b_data_hi__Data_MASK 0xffffffffL - -// port_c_addr -#define port_c_addr__Index_MASK 0x000000ffL -#define port_c_addr__Reserved_MASK 0x7fffff00L -#define port_c_addr__ReadEnable_MASK 0x80000000L - -// port_c_data_lo -#define port_c_data_lo__Data_MASK 0xffffffffL - -// port_c_data_hi -#define port_c_data_hi__Data_MASK 0xffffffffL - -// port_d_addr -#define port_d_addr__Index_MASK 0x000000ffL -#define port_d_addr__Reserved_MASK 0x7fffff00L -#define port_d_addr__ReadEnable_MASK 0x80000000L - -// port_d_data_lo -#define port_d_data_lo__Data_MASK 0xffffffffL - -// port_d_data_hi -#define port_d_data_hi__Data_MASK 0xffffffffL - -// DEBUG_BUS_RSMU -#define DEBUG_BUS_RSMU__iSCH_RSMU_RTR_MASK 0x00000001L -#define DEBUG_BUS_RSMU__oRSMU_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_RSMU__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_RSMU__oRSMU_BLOCK_FAO_MASK 0x00000008L -#define DEBUG_BUS_RSMU__oRSMU_PIPE_BUSY_MASK 0x00000010L -#define DEBUG_BUS_RSMU__iRSMU_READ_PENDING_MASK 0x00000020L -#define DEBUG_BUS_RSMU__iIGNORE_FAO_MASK 0x00000040L -#define DEBUG_BUS_RSMU__RSMU_ISYNC_FAILED_MASK 0x00000080L -#define DEBUG_BUS_RSMU__RSMU_FIFO_EMPTY_MASK 0x00000100L -#define DEBUG_BUS_RSMU__RSMU_FIFO_FULL_MASK 0x00000200L -#define DEBUG_BUS_RSMU__iRSMU_GRBM_REG_SEND_MASK 0x00000400L -#define DEBUG_BUS_RSMU__oGRBM_RLC_PWR_STALLED_MASK 0x00000800L -#define DEBUG_BUS_RSMU__oGRBM_RLC_NONGFX3D_STALLED_MASK 0x00001000L -#define DEBUG_BUS_RSMU__Reserved0_MASK 0xffffe000L - -// DEBUG_BUS_RLC -#define DEBUG_BUS_RLC__iSCH_RLC_RTR_MASK 0x00000001L -#define DEBUG_BUS_RLC__oRLC_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_RLC__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_RLC__oRLC_BLOCK_FAO_MASK 0x00000008L -#define DEBUG_BUS_RLC__oRLC_PIPE_BUSY_MASK 0x00000010L -#define DEBUG_BUS_RLC__iRLC_READ_PENDING_MASK 0x00000020L -#define DEBUG_BUS_RLC__RLC_ISYNC_FAILED_MASK 0x00000040L -#define DEBUG_BUS_RLC__RLC_FIFO_EMPTY_MASK 0x00000080L -#define DEBUG_BUS_RLC__RLC_FIFO_FULL_MASK 0x00000100L -#define DEBUG_BUS_RLC__iRLC_GRBM_REG_SEND_MASK 0x00000200L -#define DEBUG_BUS_RLC__Reserved0_MASK 0xfffffc00L - -// DEBUG_BUS_ME0PIPE0_PF -#define DEBUG_BUS_ME0PIPE0_PF__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME0PIPE0_PF__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME0PIPE0_PF__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME0PIPE0_PF__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME0PIPE0_PF__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME0PIPE0_PF__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME0PIPE0_PF__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME0PIPE0_PF__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME0PIPE0_PF__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME0PIPE0_PF__oPIPE_AVAIL_SPACE_MASK 0x00001e00L -#define DEBUG_BUS_ME0PIPE0_PF__Reserved0_MASK 0xffffe000L - -// DEBUG_BUS_ME0PIPE0_CF -#define DEBUG_BUS_ME0PIPE0_CF__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME0PIPE0_CF__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME0PIPE0_CF__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME0PIPE0_CF__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME0PIPE0_CF__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME0PIPE0_CF__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME0PIPE0_CF__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME0PIPE0_CF__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME0PIPE0_CF__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME0PIPE0_CF__oPIPE_AVAIL_SPACE_MASK 0x00001e00L -#define DEBUG_BUS_ME0PIPE0_CF__Reserved0_MASK 0xffffe000L - -// DEBUG_BUS_ME0PIPE1_PF -#define DEBUG_BUS_ME0PIPE1_PF__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME0PIPE1_PF__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME0PIPE1_PF__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME0PIPE1_PF__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME0PIPE1_PF__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME0PIPE1_PF__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME0PIPE1_PF__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME0PIPE1_PF__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME0PIPE1_PF__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME0PIPE1_PF__oPIPE_AVAIL_SPACE_MASK 0x00001e00L -#define DEBUG_BUS_ME0PIPE1_PF__Reserved0_MASK 0xffffe000L - -// DEBUG_BUS_ME0PIPE1_CF -#define DEBUG_BUS_ME0PIPE1_CF__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME0PIPE1_CF__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME0PIPE1_CF__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME0PIPE1_CF__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME0PIPE1_CF__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME0PIPE1_CF__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME0PIPE1_CF__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME0PIPE1_CF__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME0PIPE1_CF__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME0PIPE1_CF__oPIPE_AVAIL_SPACE_MASK 0x00001e00L -#define DEBUG_BUS_ME0PIPE1_CF__Reserved0_MASK 0xffffe000L - -// DEBUG_BUS_ME1PIPE0 -#define DEBUG_BUS_ME1PIPE0__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME1PIPE0__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME1PIPE0__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME1PIPE0__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME1PIPE0__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME1PIPE0__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME1PIPE0__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME1PIPE0__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME1PIPE0__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME1PIPE0__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_ME1PIPE1 -#define DEBUG_BUS_ME1PIPE1__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME1PIPE1__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME1PIPE1__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME1PIPE1__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME1PIPE1__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME1PIPE1__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME1PIPE1__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME1PIPE1__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME1PIPE1__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME1PIPE1__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_ME1PIPE2 -#define DEBUG_BUS_ME1PIPE2__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME1PIPE2__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME1PIPE2__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME1PIPE2__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME1PIPE2__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME1PIPE2__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME1PIPE2__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME1PIPE2__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME1PIPE2__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME1PIPE2__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_ME1PIPE3 -#define DEBUG_BUS_ME1PIPE3__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME1PIPE3__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME1PIPE3__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME1PIPE3__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME1PIPE3__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME1PIPE3__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME1PIPE3__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME1PIPE3__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME1PIPE3__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME1PIPE3__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_ME2PIPE0 -#define DEBUG_BUS_ME2PIPE0__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME2PIPE0__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME2PIPE0__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME2PIPE0__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME2PIPE0__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME2PIPE0__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME2PIPE0__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME2PIPE0__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME2PIPE0__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME2PIPE0__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_ME2PIPE1 -#define DEBUG_BUS_ME2PIPE1__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME2PIPE1__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME2PIPE1__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME2PIPE1__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME2PIPE1__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME2PIPE1__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME2PIPE1__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME2PIPE1__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME2PIPE1__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME2PIPE1__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_ME2PIPE2 -#define DEBUG_BUS_ME2PIPE2__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME2PIPE2__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME2PIPE2__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME2PIPE2__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME2PIPE2__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME2PIPE2__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME2PIPE2__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME2PIPE2__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME2PIPE2__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME2PIPE2__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_ME2PIPE3 -#define DEBUG_BUS_ME2PIPE3__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_ME2PIPE3__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_ME2PIPE3__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_ME2PIPE3__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_ME2PIPE3__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_ME2PIPE3__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_ME2PIPE3__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_ME2PIPE3__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_ME2PIPE3__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_ME2PIPE3__Reserved0_MASK 0xfffffe00L - -// DEBUG_BUS_GDS_DMA -#define DEBUG_BUS_GDS_DMA__iSCH_PIPE_RTR_MASK 0x00000001L -#define DEBUG_BUS_GDS_DMA__oPIPE_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_GDS_DMA__iOTHER_BLOCK_FAO_MASK 0x00000004L -#define DEBUG_BUS_GDS_DMA__oPIPE_BUSY_MASK 0x00000008L -#define DEBUG_BUS_GDS_DMA__iPIPE_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_GDS_DMA__PIPE_ISYNC_FAILED_MASK 0x00000020L -#define DEBUG_BUS_GDS_DMA__PIPE_FIFO_EMPTY_MASK 0x00000040L -#define DEBUG_BUS_GDS_DMA__PIPE_FIFO_FULL_MASK 0x00000080L -#define DEBUG_BUS_GDS_DMA__iCPG_GRBM_REG_SEND_MASK 0x00000100L -#define DEBUG_BUS_GDS_DMA__oPIPE_AVAIL_SPACE_MASK 0x00001e00L -#define DEBUG_BUS_GDS_DMA__Reserved0_MASK 0xffffe000L - -// DEBUG_BUS_SCH0 -#define DEBUG_BUS_SCH0__oSCH_SEND_SYSTEM_MASK 0x00000001L -#define DEBUG_BUS_SCH0__oSCH_SEND_GRAPHICS_TARG_PWR_MASKED_MASK 0x0000000eL -#define DEBUG_BUS_SCH0__oSCH_SEND_GRAPHICS_TARG_MASK 0x00000070L -#define DEBUG_BUS_SCH0__iPWR_REQUEST_HALT_GFX_TARG_MASK 0x00000080L -#define DEBUG_BUS_SCH0__iPWR_REQUEST_HALT_TARG_MASK 0x00000100L -#define DEBUG_BUS_SCH0__oRBB_GDS_DMA_REQUEST_MASK 0x00000200L -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE3_REQUEST_MASK 0x00000400L -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE2_REQUEST_MASK 0x00000800L -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE1_REQUEST_MASK 0x00001000L -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE0_REQUEST_MASK 0x00002000L -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE3_REQUEST_MASK 0x00004000L -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE2_REQUEST_MASK 0x00008000L -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE1_REQUEST_MASK 0x00010000L -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE0_REQUEST_MASK 0x00020000L -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE1_CF_REQUEST_MASK 0x00040000L -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE1_PF_REQUEST_MASK 0x00080000L -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE0_CF_REQUEST_MASK 0x00100000L -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE0_PF_REQUEST_MASK 0x00200000L -#define DEBUG_BUS_SCH0__oRBB_RLC_REQUEST_MASK 0x00400000L -#define DEBUG_BUS_SCH0__oRBB_RSMU_REQUEST_MASK 0x00800000L -#define DEBUG_BUS_SCH0__Reserved0_MASK 0xff000000L - -// DEBUG_BUS_SCH1 -#define DEBUG_BUS_SCH1__oGDS_DMA_READ_PENDING_MASK 0x00000001L -#define DEBUG_BUS_SCH1__oME2PIPE3_READ_PENDING_MASK 0x00000002L -#define DEBUG_BUS_SCH1__oME2PIPE2_READ_PENDING_MASK 0x00000004L -#define DEBUG_BUS_SCH1__oME2PIPE1_READ_PENDING_MASK 0x00000008L -#define DEBUG_BUS_SCH1__oME2PIPE0_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_SCH1__oME1PIPE3_READ_PENDING_MASK 0x00000020L -#define DEBUG_BUS_SCH1__oME1PIPE2_READ_PENDING_MASK 0x00000040L -#define DEBUG_BUS_SCH1__oME1PIPE1_READ_PENDING_MASK 0x00000080L -#define DEBUG_BUS_SCH1__oME1PIPE0_READ_PENDING_MASK 0x00000100L -#define DEBUG_BUS_SCH1__oME0PIPE1_CF_READ_PENDING_MASK 0x00000200L -#define DEBUG_BUS_SCH1__oME0PIPE1_PF_READ_PENDING_MASK 0x00000400L -#define DEBUG_BUS_SCH1__oME0PIPE0_CF_READ_PENDING_MASK 0x00000800L -#define DEBUG_BUS_SCH1__oME0PIPE0_PF_READ_PENDING_MASK 0x00001000L -#define DEBUG_BUS_SCH1__oRLC_READ_PENDING_MASK 0x00002000L -#define DEBUG_BUS_SCH1__oRSMU_READ_PENDING_MASK 0x00004000L -#define DEBUG_BUS_SCH1__GFX_XFER_STARTED_MASK 0x00008000L -#define DEBUG_BUS_SCH1__GFX_XFER_PENDING_MASK 0x00010000L -#define DEBUG_BUS_SCH1__GFX_CLOCK_DOMAIN_BUSY_MASK 0x00020000L -#define DEBUG_BUS_SCH1__SCH_CLKEN_MASK 0x00040000L -#define DEBUG_BUS_SCH1__GFX_PREFIX_STAGE_RDY_MASK 0x00080000L -#define DEBUG_BUS_SCH1__oRBB_CPF_REQUEST_MASK 0x00100000L -#define DEBUG_BUS_SCH1__oCPF_READ_PENDING_MASK 0x00200000L -#define DEBUG_BUS_SCH1__oRBB_INTR_REQUEST_MASK 0x00400000L -#define DEBUG_BUS_SCH1__Reserved0_MASK 0xff800000L - -// DEBUG_BUS_SCH2 -#define DEBUG_BUS_SCH2__oSCH_READ_GDS_DMA_MASK 0x00000001L -#define DEBUG_BUS_SCH2__oSCH_READ_CPC_MASK 0x00000002L -#define DEBUG_BUS_SCH2__oSCH_READ_CPG_MASK 0x00000004L -#define DEBUG_BUS_SCH2__oSCH_READ_RLC_MASK 0x00000008L -#define DEBUG_BUS_SCH2__oSCH_READ_RSMU_MASK 0x00000010L -#define DEBUG_BUS_SCH2__oSCH_READ_COMPLETE_MASK 0x00000020L -#define DEBUG_BUS_SCH2__oSCH_READ_PIPEID_MASK 0x000000c0L -#define DEBUG_BUS_SCH2__oSCH_READ_MEID_MASK 0x00000300L -#define DEBUG_BUS_SCH2__oSCH_SEND_GRAPHICS_TARG_GDS_GFX_PWR_MASKED_MASK 0x00001c00L -#define DEBUG_BUS_SCH2__oSCH_SEND_GRAPHICS_TARG_GDS_PWR_MASKED_MASK 0x0000e000L -#define DEBUG_BUS_SCH2__oSCH_SEND_GRAPHICS_TARG_GDS_MASKED_MASK 0x00070000L -#define DEBUG_BUS_SCH2__GRBM_IS_TRAPPED_MASK 0x00080000L -#define DEBUG_BUS_SCH2__Reserved0_MASK 0xfff00000L - -// DEBUG_BUS_SCH3 -#define DEBUG_BUS_SCH3__iRSMU_GRBM_READ_VALID_MASK 0x00000001L -#define DEBUG_BUS_SCH3__iGDS_GRBM_READ_FED_MASK 0x00000002L -#define DEBUG_BUS_SCH3__iGDS_GRBM_READ_COMPLETE_MASK 0x00000004L -#define DEBUG_BUS_SCH3__iGDS_GRBM_READ_VALID_MASK 0x00000008L -#define DEBUG_BUS_SCH3__iDBGU_GRBM_READ_VALID_MASK 0x00000010L -#define DEBUG_BUS_SCH3__iRLC_GRBM_READ_VALID_MASK 0x00000020L -#define DEBUG_BUS_SCH3__iCPF_GRBM_READ_VALID_MASK 0x00000040L -#define DEBUG_BUS_SCH3__iCPC_GRBM_READ_VALID_MASK 0x00000080L -#define DEBUG_BUS_SCH3__iCPG_GRBM_READ_VALID_MASK 0x00000100L -#define DEBUG_BUS_SCH3__iREAD_TIMEOUT_ERROR_MASK 0x00000200L -#define DEBUG_BUS_SCH3__iGRBM_READ_VALID_MASK 0x00000400L -#define DEBUG_BUS_SCH3__iSE3SPI_GRBM_READ0_VALID_MASK 0x00000800L -#define DEBUG_BUS_SCH3__iSE2SPI_GRBM_READ0_VALID_MASK 0x00001000L -#define DEBUG_BUS_SCH3__iSE1SPI_GRBM_READ0_VALID_MASK 0x00002000L -#define DEBUG_BUS_SCH3__iSE0SPI_GRBM_READ0_VALID_MASK 0x00004000L -#define DEBUG_BUS_SCH3__TARG_GRBM_READ_VALID_MASK 0x00008000L -#define DEBUG_BUS_SCH3__GDS_BURST_READ_ACTIVE_MASK 0x00010000L -#define DEBUG_BUS_SCH3__READ_TIMEOUT_BOTH_MASK 0x00020000L -#define DEBUG_BUS_SCH3__READ_TIMEOUT_GRBM_MASK 0x00040000L -#define DEBUG_BUS_SCH3__READ_TIMEOUT_RSMU_MASK 0x00080000L -#define DEBUG_BUS_SCH3__ONE_READ_PENDING_MASK 0x00100000L -#define DEBUG_BUS_SCH3__GRAPHICS_READ_PENDING_MASK 0x00200000L -#define DEBUG_BUS_SCH3__SYSTEM_READ_PENDING_MASK 0x00400000L -#define DEBUG_BUS_SCH3__TWO_READ_PENDING_MASK 0x00800000L -#define DEBUG_BUS_SCH3__Reserved0_MASK 0xff000000L - -// DEBUG_BUS_SCH_CNTL0 -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE3_SCH_RTS_MASK 0x00000001L -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE2_SCH_RTS_MASK 0x00000002L -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE1_SCH_RTS_MASK 0x00000004L -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE0_SCH_RTS_MASK 0x00000008L -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE3_SCH_RTS_MASK 0x00000010L -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE2_SCH_RTS_MASK 0x00000020L -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE1_SCH_RTS_MASK 0x00000040L -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE0_SCH_RTS_MASK 0x00000080L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE3_RTR_MASK 0x00000100L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE2_RTR_MASK 0x00000200L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE1_RTR_MASK 0x00000400L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE0_RTR_MASK 0x00000800L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE3_RTR_MASK 0x00001000L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE2_RTR_MASK 0x00002000L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE1_RTR_MASK 0x00004000L -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE0_RTR_MASK 0x00008000L -#define DEBUG_BUS_SCH_CNTL0__Reserved0_MASK 0xffff0000L - -// DEBUG_BUS_SCH_CNTL1 -#define DEBUG_BUS_SCH_CNTL1__iGDS_DMA_SCH_RTS_MASK 0x00000001L -#define DEBUG_BUS_SCH_CNTL1__iME0PIPE1_CF_SCH_RTS_MASK 0x00000004L -#define DEBUG_BUS_SCH_CNTL1__iME0PIPE0_PF_SCH_RTS_MASK 0x00000010L -#define DEBUG_BUS_SCH_CNTL1__iRLC_SCH_RTS_MASK 0x00000020L -#define DEBUG_BUS_SCH_CNTL1__iRSMU_SCH_RTS_MASK 0x00000040L -#define DEBUG_BUS_SCH_CNTL1__oSCH_GDS_DMA_RTR_MASK 0x00000080L -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE1_CF_RTR_MASK 0x00000100L -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE1_PF_RTR_MASK 0x00000200L -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE0_CF_RTR_MASK 0x00000400L -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE0_PF_RTR_MASK 0x00000800L -#define DEBUG_BUS_SCH_CNTL1__oSCH_RLC_RTR_MASK 0x00001000L -#define DEBUG_BUS_SCH_CNTL1__oSCH_RSMU_RTR_MASK 0x00002000L -#define DEBUG_BUS_SCH_CNTL1__iCPF_SCH_RTS_MASK 0x00004000L -#define DEBUG_BUS_SCH_CNTL1__oSCH_CPF_RTR_MASK 0x00008000L -#define DEBUG_BUS_SCH_CNTL1__iINTR_SCH_RTS_MASK 0x00010000L -#define DEBUG_BUS_SCH_CNTL1__oSCH_INTR_RTR_MASK 0x00020000L -#define DEBUG_BUS_SCH_CNTL1__Reserved0_MASK 0xfffc0000L - -// DEBUG_BUS_SCH_CNTL2 -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE3_RTS_MASK 0x00000001L -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE2_RTS_MASK 0x00000002L -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE1_RTS_MASK 0x00000004L -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE0_RTS_MASK 0x00000008L -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE3_RTS_MASK 0x00000010L -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE2_RTS_MASK 0x00000020L -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE1_RTS_MASK 0x00000040L -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE0_RTS_MASK 0x00000080L -#define DEBUG_BUS_SCH_CNTL2__GDS_DMA_RTS_MASK 0x00000100L -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE1_CF_RTS_MASK 0x00000200L -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE1_PF_RTS_MASK 0x00000400L -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE0_CF_RTS_MASK 0x00000800L -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE0_PF_RTS_MASK 0x00001000L -#define DEBUG_BUS_SCH_CNTL2__RLC_RTS_MASK 0x00002000L -#define DEBUG_BUS_SCH_CNTL2__RSMU_RTS_MASK 0x00004000L -#define DEBUG_BUS_SCH_CNTL2__CPF_RTS_MASK 0x00008000L -#define DEBUG_BUS_SCH_CNTL2__INTR_RTS_MASK 0x00010000L -#define DEBUG_BUS_SCH_CNTL2__Reserved0_MASK 0xfffe0000L - -// DEBUG_BUS_SCH_CNTL3 -#define DEBUG_BUS_SCH_CNTL3__ME2PIPE_PRIORITY_ONE_EXISTS_MASK 0x00000001L -#define DEBUG_BUS_SCH_CNTL3__ME1PIPE_PRIORITY_ONE_EXISTS_MASK 0x00000002L -#define DEBUG_BUS_SCH_CNTL3__ME0PIPE_PRIORITY_ONE_EXISTS_MASK 0x00000004L -#define DEBUG_BUS_SCH_CNTL3__NEW_ME_SWITCH_MASK 0x00000008L -#define DEBUG_BUS_SCH_CNTL3__xXFER_ID_MASK 0x000000f0L -#define DEBUG_BUS_SCH_CNTL3__XFER_ME_ID_MASK 0x00000f00L -#define DEBUG_BUS_SCH_CNTL3__xXFER_ME0PIPE1_ID_MASK 0x0000f000L -#define DEBUG_BUS_SCH_CNTL3__xXFER_ME0PIPE0_ID_MASK 0x000f0000L -#define DEBUG_BUS_SCH_CNTL3__CPF_XFC_MASK 0x00100000L -#define DEBUG_BUS_SCH_CNTL3__INTR_XFC_MASK 0x00200000L -#define DEBUG_BUS_SCH_CNTL3__Reserved0_MASK 0xffc00000L - -// DEBUG_BUS_SCH_CNTL4 -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE3_CNT_NONZERO_MASK 0x00000001L -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE2_CNT_NONZERO_MASK 0x00000002L -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE1_CNT_NONZERO_MASK 0x00000004L -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE0_CNT_NONZERO_MASK 0x00000008L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE3_CNT_NONZERO_MASK 0x00000010L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE2_CNT_NONZERO_MASK 0x00000020L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE1_CNT_NONZERO_MASK 0x00000040L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE0_CNT_NONZERO_MASK 0x00000080L -#define DEBUG_BUS_SCH_CNTL4__GDS_DMA_CNT_NONZERO_MASK 0x00000100L -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE1_CNT_NONZERO_MASK 0x00000200L -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE0_CNT_NONZERO_MASK 0x00000400L -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE3_XFC_MASK 0x00000800L -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE2_XFC_MASK 0x00001000L -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE1_XFC_MASK 0x00002000L -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE0_XFC_MASK 0x00004000L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE3_XFC_MASK 0x00008000L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE2_XFC_MASK 0x00010000L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE1_XFC_MASK 0x00020000L -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE0_XFC_MASK 0x00040000L -#define DEBUG_BUS_SCH_CNTL4__GDS_DMA_XFC_MASK 0x00080000L -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE1_XFC_MASK 0x00100000L -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE0_XFC_MASK 0x00200000L -#define DEBUG_BUS_SCH_CNTL4__RLC_XFC_MASK 0x00400000L -#define DEBUG_BUS_SCH_CNTL4__RSMU_XFC_MASK 0x00800000L -#define DEBUG_BUS_SCH_CNTL4__Reserved0_MASK 0xff000000L - -// DEBUG_BUS_SCH_ME0PIPE0_WD_DMA -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__STOP_DMA_REQUEST_MASK 0x00000001L -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__iME0PIPEX_SKEW_TOP_THRESHOLD_MASK 0x0000007eL -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__SIZE_CNT_MASK 0x00001f80L -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__VGT_DRAW_INITIATOR_MASK 0x00002000L -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__VGT_DMA_SIZE_REQ_MASK 0x00004000L -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__Reserved0_MASK 0xffff8000L - -// DEBUG_BUS_SCH_ME0PIPE1_WD_DMA -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__STOP_DMA_REQUEST_MASK 0x00000001L -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__iME0PIPEX_SKEW_TOP_THRESHOLD_MASK 0x0000007eL -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__SIZE_CNT_MASK 0x00001f80L -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__VGT_DRAW_INITIATOR_MASK 0x00002000L -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__VGT_DMA_SIZE_REQ_MASK 0x00004000L -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__Reserved0_MASK 0xffff8000L - -// DEBUG_BUS_SCH_HAND0 -#define DEBUG_BUS_SCH_HAND0__SE0SPI_ME0PIPE0_AVAIL_CNT0_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND0__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND0__SE0SPI_ME0PIPE1_AVAIL_CNT0_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND0__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND1 -#define DEBUG_BUS_SCH_HAND1__SE1SPI_ME0PIPE0_AVAIL_CNT0_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND1__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND1__SE1SPI_ME0PIPE1_AVAIL_CNT0_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND1__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND2 -#define DEBUG_BUS_SCH_HAND2__SE2SPI_ME0PIPE0_AVAIL_CNT0_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND2__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND2__SE2SPI_ME0PIPE1_AVAIL_CNT0_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND2__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND3 -#define DEBUG_BUS_SCH_HAND3__SE3SPI_ME0PIPE0_AVAIL_CNT0_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND3__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND3__SE3SPI_ME0PIPE1_AVAIL_CNT0_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND3__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND4 -#define DEBUG_BUS_SCH_HAND4__SE0SPI_ME0PIPE0_AVAIL_CNT1_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND4__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND4__SE0SPI_ME0PIPE1_AVAIL_CNT1_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND4__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND5 -#define DEBUG_BUS_SCH_HAND5__SE1SPI_ME0PIPE0_AVAIL_CNT1_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND5__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND5__SE1SPI_ME0PIPE1_AVAIL_CNT1_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND5__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND6 -#define DEBUG_BUS_SCH_HAND6__SE2SPI_ME0PIPE0_AVAIL_CNT1_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND6__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND6__SE2SPI_ME0PIPE1_AVAIL_CNT1_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND6__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND7 -#define DEBUG_BUS_SCH_HAND7__SE3SPI_ME0PIPE0_AVAIL_CNT1_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND7__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND7__SE3SPI_ME0PIPE1_AVAIL_CNT1_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND7__Reserved1_MASK 0xffffc000L - -// DEBUG_BUS_SCH_HAND8 -#define DEBUG_BUS_SCH_HAND8__GDS_AVAIL_CNT_MASK 0x0000001fL -#define DEBUG_BUS_SCH_HAND8__Reserved0_MASK 0x000000e0L -#define DEBUG_BUS_SCH_HAND8__RSMU_AVAIL_CNT_MASK 0x00000700L -#define DEBUG_BUS_SCH_HAND8__Reserved1_MASK 0x0000f800L -#define DEBUG_BUS_SCH_HAND8__CPF_AVAIL_CNT_MASK 0x000f0000L -#define DEBUG_BUS_SCH_HAND8__CPG_AVAIL_CNT_MASK 0x00f00000L -#define DEBUG_BUS_SCH_HAND8__Reserved2_MASK 0xff000000L - -// DEBUG_BUS_SCH_HAND9 -#define DEBUG_BUS_SCH_HAND9__WD_ME0PIPE0_AVAIL_CNT_MASK 0x0000003fL -#define DEBUG_BUS_SCH_HAND9__Reserved0_MASK 0x000000c0L -#define DEBUG_BUS_SCH_HAND9__WD_ME0PIPE1_AVAIL_CNT_MASK 0x00003f00L -#define DEBUG_BUS_SCH_HAND9__Reserved1_MASK 0x0000c000L -#define DEBUG_BUS_SCH_HAND9__iGRAPHICS_RBB_XFC_GFX_PWR_MASKED_MASK 0x00070000L -#define DEBUG_BUS_SCH_HAND9__Reserved2_MASK 0xfff80000L - -// DEBUG_BUS_SCH_HAND10 -#define DEBUG_BUS_SCH_HAND10__iSYSTEM_RBB_XFC_MASK 0x00000001L -#define DEBUG_BUS_SCH_HAND10__iGRAPHICS_RBB_XFC_PWR_MASKED_MASK 0x0000000eL -#define DEBUG_BUS_SCH_HAND10__iGRAPHICS_RBB_XFC_MASK 0x00000070L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_GDS_DMA_RDY_MASK 0x00000080L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE3_RDY_MASK 0x00000100L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE2_RDY_MASK 0x00000200L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE1_RDY_MASK 0x00000400L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE0_RDY_MASK 0x00000800L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE3_RDY_MASK 0x00001000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE2_RDY_MASK 0x00002000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE1_RDY_MASK 0x00004000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE0_RDY_MASK 0x00008000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE1_CF_RDY_MASK 0x00010000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE1_PF_RDY_MASK 0x00020000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE0_CF_RDY_MASK 0x00040000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE0_PF_RDY_MASK 0x00080000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_RLC_RDY_MASK 0x00100000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_RSMU_RDY_MASK 0x00200000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_CPF_RDY_MASK 0x00400000L -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_INTR_RDY_MASK 0x00800000L -#define DEBUG_BUS_SCH_HAND10__Reserved0_MASK 0xff000000L - -// DEBUG_BUS_SCH_HAND11 -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE1_WD_DMA_DRAW_INIT_REQUESTS_MASK 0x00000001L -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE1_WD_DMA_REQUESTS_MASK 0x00000002L -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE0_WD_DMA_DRAW_INIT_REQUESTS_MASK 0x00000004L -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE0_WD_DMA_REQUESTS_MASK 0x00000008L -#define DEBUG_BUS_SCH_HAND11__iREAD_TIMEOUT_BOTH_MASK 0x00000010L -#define DEBUG_BUS_SCH_HAND11__iONE_READ_PENDING_MASK 0x00000020L -#define DEBUG_BUS_SCH_HAND11__iGRAPHICS_READ_PENDING_MASK 0x00000040L -#define DEBUG_BUS_SCH_HAND11__GRAPHICS_RBB_XFC_GDS_GFX_PWR_MASKED_MASK 0x00000380L -#define DEBUG_BUS_SCH_HAND11__GRAPHICS_RBB_XFC_GDS_PWR_MASKED_MASK 0x00001c00L -#define DEBUG_BUS_SCH_HAND11__GRAPHICS_RBB_XFC_GDS_MASKED_MASK 0x0000e000L -#define DEBUG_BUS_SCH_HAND11__TARGETS_RDY_SYSTEM_MASK 0x00010000L -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_GDS_DMA_AF_MASK 0x00020000L -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_MECPIPES_AF_MASK 0x00040000L -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_ME0PIPE1_AF_MASK 0x00080000L -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_ME0PIPE0_AF_MASK 0x00100000L -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_GRAPHICS_MASK 0x00200000L -#define DEBUG_BUS_SCH_HAND11__oALL_TARGETS_FLUSHED_MASK 0x00400000L -#define DEBUG_BUS_SCH_HAND11__oALL_GFX_TARGETS_FLUSHED_MASK 0x00800000L -#define DEBUG_BUS_SCH_HAND11__Reserved0_MASK 0xff000000L - -// DEBUG_BUS_SCH_HAND12 -#define DEBUG_BUS_SCH_HAND12__GDS_DMA_READ_PENDING_MASK 0x00000001L -#define DEBUG_BUS_SCH_HAND12__ME2PIPE3_READ_PENDING_MASK 0x00000002L -#define DEBUG_BUS_SCH_HAND12__ME2PIPE2_READ_PENDING_MASK 0x00000004L -#define DEBUG_BUS_SCH_HAND12__ME2PIPE1_READ_PENDING_MASK 0x00000008L -#define DEBUG_BUS_SCH_HAND12__ME2PIPE0_READ_PENDING_MASK 0x00000010L -#define DEBUG_BUS_SCH_HAND12__ME1PIPE3_READ_PENDING_MASK 0x00000020L -#define DEBUG_BUS_SCH_HAND12__ME1PIPE2_READ_PENDING_MASK 0x00000040L -#define DEBUG_BUS_SCH_HAND12__ME1PIPE1_READ_PENDING_MASK 0x00000080L -#define DEBUG_BUS_SCH_HAND12__ME1PIPE0_READ_PENDING_MASK 0x00000100L -#define DEBUG_BUS_SCH_HAND12__ME0PIPE1_CF_READ_PENDING_MASK 0x00000200L -#define DEBUG_BUS_SCH_HAND12__ME0PIPE1_PF_READ_PENDING_MASK 0x00000400L -#define DEBUG_BUS_SCH_HAND12__ME0PIPE0_CF_READ_PENDING_MASK 0x00000800L -#define DEBUG_BUS_SCH_HAND12__ME0PIPE0_PF_READ_PENDING_MASK 0x00001000L -#define DEBUG_BUS_SCH_HAND12__RLC_READ_PENDING_MASK 0x00002000L -#define DEBUG_BUS_SCH_HAND12__RSMU_READ_PENDING_MASK 0x00004000L -#define DEBUG_BUS_SCH_HAND12__READ_PENDING_MASK 0x00008000L -#define DEBUG_BUS_SCH_HAND12__CPF_READ_PENDING_MASK 0x00010000L -#define DEBUG_BUS_SCH_HAND12__oTARGETS_RDY_CPF_AF_MASK 0x00020000L -#define DEBUG_BUS_SCH_HAND12__Reserved0_MASK 0xfffc0000L - -// DEBUG_BUS_REG0 -#define DEBUG_BUS_REG0__COMPUTE_PIPE_BUSY_MASK 0x00000001L -#define DEBUG_BUS_REG0__GFX_PIPE_BUSY_MASK 0x00000002L -#define DEBUG_BUS_REG0__CORE_COMPUTE_BUSY_F_MASK 0x00000004L -#define DEBUG_BUS_REG0__CORE_GFX_BUSY_F_MASK 0x00000008L -#define DEBUG_BUS_REG0__iGDS_DMA_PIPE_BUSY_MASK 0x00000010L -#define DEBUG_BUS_REG0__iME2PIPE3_PIPE_BUSY_MASK 0x00000020L -#define DEBUG_BUS_REG0__iME2PIPE2_PIPE_BUSY_MASK 0x00000040L -#define DEBUG_BUS_REG0__iME2PIPE1_PIPE_BUSY_MASK 0x00000080L -#define DEBUG_BUS_REG0__iME2PIPE0_PIPE_BUSY_MASK 0x00000100L -#define DEBUG_BUS_REG0__iME1PIPE3_PIPE_BUSY_MASK 0x00000200L -#define DEBUG_BUS_REG0__iME1PIPE2_PIPE_BUSY_MASK 0x00000400L -#define DEBUG_BUS_REG0__iME1PIPE1_PIPE_BUSY_MASK 0x00000800L -#define DEBUG_BUS_REG0__iME1PIPE0_PIPE_BUSY_MASK 0x00001000L -#define DEBUG_BUS_REG0__iME0PIPE1_CF_PIPE_BUSY_MASK 0x00002000L -#define DEBUG_BUS_REG0__iME0PIPE1_PF_PIPE_BUSY_MASK 0x00004000L -#define DEBUG_BUS_REG0__iME0PIPE0_CF_PIPE_BUSY_MASK 0x00008000L -#define DEBUG_BUS_REG0__iME0PIPE0_PF_PIPE_BUSY_MASK 0x00010000L -#define DEBUG_BUS_REG0__iRLC_PIPE_BUSY_MASK 0x00020000L -#define DEBUG_BUS_REG0__iCPF_PIPE_BUSY_MASK 0x00040000L -#define DEBUG_BUS_REG0__iRSMU_PIPE_BUSY_MASK 0x00080000L -#define DEBUG_BUS_REG0__GRBM_BUSY_MASK 0x00100000L -#define DEBUG_BUS_REG0__Reserved0_MASK 0xffe00000L - -// DEBUG_BUS_REG1 -#define DEBUG_BUS_REG1__INT_xXFER_ID_MASK 0x00000003L -#define DEBUG_BUS_REG1__INT_XFER_ID_MASK 0x0000000cL -#define DEBUG_BUS_REG1__qIH_INTR_CREDIT_CNT_MASK 0x00000030L -#define DEBUG_BUS_REG1__qGUI_IDLE_INT_DETECTED_MASK 0x00000040L -#define DEBUG_BUS_REG1__qRDERR_INT_DETECTED_MASK 0x00000080L -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE_TARG_MASK 0x00000100L -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE_MASK 0x00000200L -#define DEBUG_BUS_REG1__PWR_REQUEST_REJECTED_MASK 0x00000400L -#define DEBUG_BUS_REG1__PWR_REQUEST_ACCEPTED_MASK 0x00000800L -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT_TARG_MASK 0x00001000L -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT_MASK 0x00002000L -#define DEBUG_BUS_REG1__oPWR_REQUEST_HALT_TARG_MASK 0x00004000L -#define DEBUG_BUS_REG1__PWR_REQUEST_COMPLETE_MASK 0x00008000L -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE_GFX_TARG_MASK 0x00010000L -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE_GFX_MASK 0x00020000L -#define DEBUG_BUS_REG1__PWR_REQUEST_GFX_REJECTED_MASK 0x00040000L -#define DEBUG_BUS_REG1__PWR_REQUEST_GFX_ACCEPTED_MASK 0x00080000L -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT_GFX_TARG_MASK 0x00100000L -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT_GFX_MASK 0x00200000L -#define DEBUG_BUS_REG1__oPWR_REQUEST_HALT_GFX_TARG_MASK 0x00400000L -#define DEBUG_BUS_REG1__PWR_REQUEST_GFX_COMPLETE_MASK 0x00800000L -#define DEBUG_BUS_REG1__Reserved0_MASK 0xff000000L - -// DEBUG_BUS_REG2 -#define DEBUG_BUS_REG2__REGBUS_ADDR_MASK 0x0000ffffL -#define DEBUG_BUS_REG2__REGBUS_WD_MASK 0x003f0000L -#define DEBUG_BUS_REG2__REGBUS_RE_MASK 0x00400000L -#define DEBUG_BUS_REG2__REGBUS_WE_MASK 0x00800000L -#define DEBUG_BUS_REG2__Reserved0_MASK 0xff000000L - -// wbuf_DEBUG_DATA -#define wbuf_DEBUG_DATA__Reserved0_MASK 0x0000003fL -#define wbuf_DEBUG_DATA__write_buff_valid_MASK 0x00000040L -#define wbuf_DEBUG_DATA__wr_pixel_ptr_nxt_MASK 0x00000f80L -#define wbuf_DEBUG_DATA__last_pixel_ptr_MASK 0x00001000L -#define wbuf_DEBUG_DATA__cstate_3to0_MASK 0x0001e000L -#define wbuf_DEBUG_DATA__buff_write_MASK 0x00020000L -#define wbuf_DEBUG_DATA__flush_request_MASK 0x00040000L -#define wbuf_DEBUG_DATA__wr_buffer_wr_complete_MASK 0x00080000L -#define wbuf_DEBUG_DATA__wbuf_fifo_empty_MASK 0x00100000L -#define wbuf_DEBUG_DATA__wbuf_fifo_full_MASK 0x00200000L -#define wbuf_DEBUG_DATA__Reserved1_MASK 0xffc00000L - -// rbuf_DEBUG_DATA -#define rbuf_DEBUG_DATA__tag_hit_MASK 0x00000001L -#define rbuf_DEBUG_DATA__tag_miss_MASK 0x00000002L -#define rbuf_DEBUG_DATA__pixel_addr_mask_MASK 0x0001fffcL -#define rbuf_DEBUG_DATA__pixel_vld_MASK 0x00020000L -#define rbuf_DEBUG_DATA__data_ready_MASK 0x00040000L -#define rbuf_DEBUG_DATA__awaiting_data_MASK 0x00080000L -#define rbuf_DEBUG_DATA__addr_fifo_full_MASK 0x00100000L -#define rbuf_DEBUG_DATA__addr_fifo_empty_MASK 0x00200000L -#define rbuf_DEBUG_DATA__buffer_loaded_MASK 0x00400000L -#define rbuf_DEBUG_DATA__buffer_invalid_MASK 0x00800000L -#define rbuf_DEBUG_DATA__Reserved0_MASK 0xff000000L - -// oa_wc0_DEBUG_DATA -#define oa_wc0_DEBUG_DATA__ds_full_MASK 0x00000001L -#define oa_wc0_DEBUG_DATA__credit_cnt_MASK 0x00000002L -#define oa_wc0_DEBUG_DATA__ord_idx_free_MASK 0x00000004L -#define oa_wc0_DEBUG_DATA__cmd_write_MASK 0x00000008L -#define oa_wc0_DEBUG_DATA__app_sel_MASK 0x000000f0L -#define oa_wc0_DEBUG_DATA__req_MASK 0x0007ff00L -#define oa_wc0_DEBUG_DATA__Reserved0_MASK 0xfff80000L - -// oa_wc1_DEBUG_DATA -#define oa_wc1_DEBUG_DATA__pipe0_busy_MASK 0x00000001L -#define oa_wc1_DEBUG_DATA__pipe1_busy_MASK 0x00000002L -#define oa_wc1_DEBUG_DATA__pipe2_busy_MASK 0x00000004L -#define oa_wc1_DEBUG_DATA__pipe3_busy_MASK 0x00000008L -#define oa_wc1_DEBUG_DATA__pipe4_busy_MASK 0x00000010L -#define oa_wc1_DEBUG_DATA__pipe5_busy_MASK 0x00000020L -#define oa_wc1_DEBUG_DATA__pipe6_busy_MASK 0x00000040L -#define oa_wc1_DEBUG_DATA__pipe7_busy_MASK 0x00000080L -#define oa_wc1_DEBUG_DATA__pipe8_busy_MASK 0x00000100L -#define oa_wc1_DEBUG_DATA__pipe9_busy_MASK 0x00000200L -#define oa_wc1_DEBUG_DATA__Pipe10_busy_MASK 0x00000400L -#define oa_wc1_DEBUG_DATA__pipe0_busy0_MASK 0x00000800L -#define oa_wc1_DEBUG_DATA__pipe0_busy1_MASK 0x00001000L -#define oa_wc1_DEBUG_DATA__pipe0_busy2_MASK 0x00002000L -#define oa_wc1_DEBUG_DATA__pipe0_busy3_MASK 0x00004000L -#define oa_wc1_DEBUG_DATA__pipe0_busy4_MASK 0x00008000L -#define oa_wc1_DEBUG_DATA__pipe0_busy5_MASK 0x00010000L -#define oa_wc1_DEBUG_DATA__pipe0_busy6_MASK 0x00020000L -#define oa_wc1_DEBUG_DATA__pipe0_busy7_MASK 0x00040000L -#define oa_wc1_DEBUG_DATA__Reserved0_MASK 0xfff80000L - -// gws_DEBUG_DATA -#define gws_DEBUG_DATA__gws_busy_MASK 0x00000001L -#define gws_DEBUG_DATA__gws_req_MASK 0x00000002L -#define gws_DEBUG_DATA__gws_out_stall_MASK 0x00000004L -#define gws_DEBUG_DATA__cur_reso_5to0_MASK 0x000001f8L -#define gws_DEBUG_DATA__cur_reso_head_valid_MASK 0x00000200L -#define gws_DEBUG_DATA__cur_reso_head_dirty_MASK 0x00000400L -#define gws_DEBUG_DATA__cur_reso_head_flag_MASK 0x00000800L -#define gws_DEBUG_DATA__cur_reso_fed_MASK 0x00001000L -#define gws_DEBUG_DATA__cur_reso_barrier_MASK 0x00002000L -#define gws_DEBUG_DATA__cur_reso_flag_MASK 0x00004000L -#define gws_DEBUG_DATA__cur_reso_count_MASK 0x00008000L -#define gws_DEBUG_DATA__credit_cnt_MASK 0x00010000L -#define gws_DEBUG_DATA__cmd_write_MASK 0x00020000L -#define gws_DEBUG_DATA__grbm_gws_reso_wr_MASK 0x00040000L -#define gws_DEBUG_DATA__grbm_gws_reso_rd_MASK 0x00080000L -#define gws_DEBUG_DATA__ram_read_busy_MASK 0x00100000L -#define gws_DEBUG_DATA__gws_bulkfree_MASK 0x00200000L -#define gws_DEBUG_DATA__ram_gws_re_MASK 0x00400000L -#define gws_DEBUG_DATA__ram_gws_we_MASK 0x00800000L -#define gws_DEBUG_DATA__Reserved0_MASK 0xff000000L - -// alloc_DEBUG_DATA -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_write_dis_MASK 0x00000001L -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_dec_error_MASK 0x00000002L -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_alloc_opco_error_MASK 0x00000004L -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_dealloc_opco_error_MASK 0x00000008L -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_wrap_opco_error_MASK 0x00000010L -#define alloc_DEBUG_DATA__Reserved0_MASK 0x000000e0L -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_error_ds_address_MASK 0x003fff00L -#define alloc_DEBUG_DATA__Reserved1_MASK 0xffc00000L - -// ord_app_DEBUG_DATA -#define ord_app_DEBUG_DATA__fifo_busy_MASK 0x00000001L -#define ord_app_DEBUG_DATA__ord_busy_MASK 0x00000002L -#define ord_app_DEBUG_DATA__gws_busy_MASK 0x00000004L -#define ord_app_DEBUG_DATA__Reserved0_MASK 0x00000008L -#define ord_app_DEBUG_DATA__sh0_cmd_fifo_empty_MASK 0x00000010L -#define ord_app_DEBUG_DATA__sh1_cmd_fifo_empty_MASK 0x00000020L -#define ord_app_DEBUG_DATA__sh2_cmd_fifo_empty_MASK 0x00000040L -#define ord_app_DEBUG_DATA__sh3_cmd_fifo_empty_MASK 0x00000080L -#define ord_app_DEBUG_DATA__sh0_data_fifo_empty_MASK 0x00000100L -#define ord_app_DEBUG_DATA__sh1_data_fifo_empty_MASK 0x00000200L -#define ord_app_DEBUG_DATA__sh2_data_fifo_empty_MASK 0x00000400L -#define ord_app_DEBUG_DATA__sh3_data_fifo_empty_MASK 0x00000800L -#define ord_app_DEBUG_DATA__Reserved1_MASK 0xfffff000L - -// GPM_CMN_debug_0_data -#define GPM_CMN_debug_0_data__Reserved1_MASK 0x000003ffL -#define GPM_CMN_debug_0_data__Rlc_gpm_busy_MASK 0x00000400L -#define GPM_CMN_debug_0_data__Rlc_spm_busy_MASK 0x00000800L -#define GPM_CMN_debug_0_data__Reserved0_MASK 0xfffff000L - -// GPM_CMN_debug_1_data -#define GPM_CMN_debug_1_data__loadRTS_MASK 0x00000001L -#define GPM_CMN_debug_1_data__loadValid_MASK 0x00000002L -#define GPM_CMN_debug_1_data__loadSel_MASK 0x0000000cL -#define GPM_CMN_debug_1_data__MC_LOAD_wrreq_flushed_MASK 0x00000010L -#define GPM_CMN_debug_1_data__RLC_GPM_CMN_miu_rd_vld_MASK 0x00000020L -#define GPM_CMN_debug_1_data__GRBMCLIENT_LOAD_rsp_valid_MASK 0x00000040L -#define GPM_CMN_debug_1_data__LOAD_SCRATCH_rreg_valid_MASK 0x00000080L -#define GPM_CMN_debug_1_data__loadRtnThreadId_MASK 0x00000300L -#define GPM_CMN_debug_1_data__RLC_GPM_CMN_miu_rd_rts_MASK 0x00000400L -#define GPM_CMN_debug_1_data__LOAD_GRBMCLIENT_read_MASK 0x00000800L -#define GPM_CMN_debug_1_data__loadGlobalFifoEmpty_MASK 0x00001000L -#define GPM_CMN_debug_1_data__loadGlobalFifoFull_MASK 0x00002000L -#define GPM_CMN_debug_1_data__loadMemFifoEmpty_MASK 0x00004000L -#define GPM_CMN_debug_1_data__loadMemFifoFull_MASK 0x00008000L -#define GPM_CMN_debug_1_data__loadRegFifoEmpty_MASK 0x00010000L -#define GPM_CMN_debug_1_data__loadRegFifoFull_MASK 0x00020000L -#define GPM_CMN_debug_1_data__loadRTR_MASK 0x00040000L -#define GPM_CMN_debug_1_data__SMU_RLC_clock_on_MASK 0x00080000L -#define GPM_CMN_debug_1_data__load_global_pending_MASK 0x00100000L -#define GPM_CMN_debug_1_data__loadLocalValid_MASK 0x00200000L -#define GPM_CMN_debug_1_data__loadRegValid_MASK 0x00400000L -#define GPM_CMN_debug_1_data__loadMemValid_MASK 0x00800000L -#define GPM_CMN_debug_1_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_2_data -#define GPM_CMN_debug_2_data__storeRTR_0_MASK 0x00000001L -#define GPM_CMN_debug_2_data__storeRTS_MASK 0x00000002L -#define GPM_CMN_debug_2_data__storeSel_MASK 0x0000000cL -#define GPM_CMN_debug_2_data__storeMemFifoFull_MASK 0x00000010L -#define GPM_CMN_debug_2_data__GRBMCLIENT_STORE_write_done_MASK 0x00000020L -#define GPM_CMN_debug_2_data__UcodeBusyFlag_MASK 0x00000040L -#define GPM_CMN_debug_2_data__STORE_RLCV_SCRATCH_wreg_valid_MASK 0x00000080L -#define GPM_CMN_debug_2_data__STORE_IH_ctxid2_we_MASK 0x00000100L -#define GPM_CMN_debug_2_data__STORE_SCRATCH_wreg_valid_MASK 0x00000200L -#define GPM_CMN_debug_2_data__STORE_GRBMT_wreg_valid_MASK 0x00000400L -#define GPM_CMN_debug_2_data__STORE_IH_intrid_we_MASK 0x00000800L -#define GPM_CMN_debug_2_data__STORE_IH_ctxid_we_MASK 0x00001000L -#define GPM_CMN_debug_2_data__storeRTR_2_MASK 0x00002000L -#define GPM_CMN_debug_2_data__RLCC_GCPM_cgcg_request_MASK 0x00004000L -#define GPM_CMN_debug_2_data__storeRTR_1_MASK 0x00008000L -#define GPM_CMN_debug_2_data__STORE_IR1_intrsp_send_MASK 0x00010000L -#define GPM_CMN_debug_2_data__STORE_IR0_intrsp_send_MASK 0x00020000L -#define GPM_CMN_debug_2_data__STORE_GRBMCLIENT_meid_MASK 0x000c0000L -#define GPM_CMN_debug_2_data__STORE_GRBMCLIENT_pipeid_MASK 0x00300000L -#define GPM_CMN_debug_2_data__Reserved0_MASK 0xffc00000L - -// GPM_CMN_debug_3_data -#define GPM_CMN_debug_3_data__Credit_count_MASK 0x0000003fL -#define GPM_CMN_debug_3_data__Credit_available_MASK 0x00000040L -#define GPM_CMN_debug_3_data__Sm_count_MASK 0x00000380L -#define GPM_CMN_debug_3_data__Disable_state_machine_MASK 0x00000400L -#define GPM_CMN_debug_3_data__Enable_state_machine_MASK 0x00000800L -#define GPM_CMN_debug_3_data__Interrupt_send_MASK 0x00001000L -#define GPM_CMN_debug_3_data__STORE_IH_write_done_MASK 0x00002000L -#define GPM_CMN_debug_3_data__STORE_IH_intrid2_we_MASK 0x00004000L -#define GPM_CMN_debug_3_data__STORE_IH_intrid_we_MASK 0x00008000L -#define GPM_CMN_debug_3_data__STORE_IH_ctxid2_we_MASK 0x00010000L -#define GPM_CMN_debug_3_data__STORE_IH_ctxid_we_MASK 0x00020000L -#define GPM_CMN_debug_3_data__Reserved0_MASK 0xfffc0000L - -// GPM_CMN_debug_4_data -#define GPM_CMN_debug_4_data__LOAD_SSCRATCH_rreg_valid_MASK 0x00000001L -#define GPM_CMN_debug_4_data__LOAD_SCRATCH_rreg_threadid_MASK 0x00000006L -#define GPM_CMN_debug_4_data__LOAD_SCRATCH_rreg_instrsel_MASK 0x00000018L -#define GPM_CMN_debug_4_data__STORE_SCRATCH_wreg_valid_MASK 0x00000020L -#define GPM_CMN_debug_4_data__LoadScratchRamReQ2_MASK 0x00000040L -#define GPM_CMN_debug_4_data__LoadScratchRamReQ1_MASK 0x00000080L -#define GPM_CMN_debug_4_data__ScratchRamRdEn_MASK 0x00000100L -#define GPM_CMN_debug_4_data__ScratchRamWrEn_MASK 0x00000200L -#define GPM_CMN_debug_4_data__SCRATCH_LOAD_rsp_threadid_MASK 0x00000c00L -#define GPM_CMN_debug_4_data__SCRATCH_LOAD_rsp_instrsel_MASK 0x00003000L -#define GPM_CMN_debug_4_data__SCRATCH_LOAD_rsp_valid_MASK 0x00004000L -#define GPM_CMN_debug_4_data__ScratchRamRdAddr_8to0_MASK 0x00ff8000L -#define GPM_CMN_debug_4_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_5_data -#define GPM_CMN_debug_5_data__Serdes_ctrl_Debug_MASK 0x00000001L -#define GPM_CMN_debug_5_data__Cgcg_cgls_ctrl_Debug_MASK 0x001ffffeL -#define GPM_CMN_debug_5_data__Reserved0_MASK 0xffe00000L - -// GPM_CMN_debug_6_data -#define GPM_CMN_debug_6_data__IR0_LOAD_interrupt_id_8_MASK 0x00000001L -#define GPM_CMN_debug_6_data__IR1_LOAD_interrupt_id_8_MASK 0x00000002L -#define GPM_CMN_debug_6_data__IR2_LOAD_interrupt_id_8_MASK 0x00000004L -#define GPM_CMN_debug_6_data__GFX_pwr_stalled_status_MASK 0x00000008L -#define GPM_CMN_debug_6_data__GRBMT_LOAD_rlc_lb_cntr_stop_flag_MASK 0x00000010L -#define GPM_CMN_debug_6_data__GRBMT_LOAD_rlc_lb_cntr_start_flag_MASK 0x00000020L -#define GPM_CMN_debug_6_data__GRBMT_LOAD_rlc_lb_cntr_max_flag_MASK 0x00000040L -#define GPM_CMN_debug_6_data__GFX_power_status_MASK 0x00000080L -#define GPM_CMN_debug_6_data__GFX_clock_status_MASK 0x00000100L -#define GPM_CMN_debug_6_data__GFX_ls_status_MASK 0x00000200L -#define GPM_CMN_debug_6_data__GPM_STAT_pipeline_power_status_MASK 0x00000400L -#define GPM_CMN_debug_6_data__GPM_STAT_cntx_idle_being_processed_MASK 0x00000800L -#define GPM_CMN_debug_6_data__GPM_STAT_cntx_busy_being_processed_MASK 0x00001000L -#define GPM_CMN_debug_6_data__GPM_STAT_gfx_idle_being_processed_MASK 0x00002000L -#define GPM_CMN_debug_6_data__GPM_STAT_cmp_busy_being_processed_MASK 0x00004000L -#define GPM_CMN_debug_6_data__GPM_STAT_saving_registers_MASK 0x00008000L -#define GPM_CMN_debug_6_data__GPM_STAT_restoring_registers_MASK 0x00010000L -#define GPM_CMN_debug_6_data__GPM_STAT_gfx3d_blocks_changing_power_state_MASK 0x00020000L -#define GPM_CMN_debug_6_data__GPM_STAT_cmp_blocks_changing_power_state_MASK 0x00040000L -#define GPM_CMN_debug_6_data__GPM_STAT_static_cu_powering_up_MASK 0x00080000L -#define GPM_CMN_debug_6_data__GPM_STAT_static_cu_powering_down_MASK 0x00100000L -#define GPM_CMN_debug_6_data__GPM_STAT_dyn_cu_powering_up_MASK 0x00200000L -#define GPM_CMN_debug_6_data__GPM_STAT_dyn_cu_powering_down_MASK 0x00400000L -#define GPM_CMN_debug_6_data__GPM_STAT_aborted_pd_sequence_MASK 0x00800000L -#define GPM_CMN_debug_6_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_7_data -#define GPM_CMN_debug_7_data__f32DebugBus_23to0_MASK 0x00ffffffL -#define GPM_CMN_debug_7_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_8_data -#define GPM_CMN_debug_8_data__f32DebugBus_47to24_MASK 0x00ffffffL -#define GPM_CMN_debug_8_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_9_data -#define GPM_CMN_debug_9_data__f32DebugBus_71to48_MASK 0x00ffffffL -#define GPM_CMN_debug_9_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_10_data -#define GPM_CMN_debug_10_data__f32DebugBus_95to72_MASK 0x00ffffffL -#define GPM_CMN_debug_10_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_11_data -#define GPM_CMN_debug_11_data__f32DebugBus_119to96_MASK 0x00ffffffL -#define GPM_CMN_debug_11_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_12_data -#define GPM_CMN_debug_12_data__f32DebugBus_143to120_MASK 0x00ffffffL -#define GPM_CMN_debug_12_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_13_data -#define GPM_CMN_debug_13_data__f32DebugBus_167to144_MASK 0x00ffffffL -#define GPM_CMN_debug_13_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_14_data -#define GPM_CMN_debug_14_data__f32DebugBus_191to168_MASK 0x00ffffffL -#define GPM_CMN_debug_14_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_15_data -#define GPM_CMN_debug_15_data__f32DebugBus_215to192_MASK 0x00ffffffL -#define GPM_CMN_debug_15_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_16_data -#define GPM_CMN_debug_16_data__f32DebugBus_239to216_MASK 0x00ffffffL -#define GPM_CMN_debug_16_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_17_data -#define GPM_CMN_debug_17_data__f32DebugBus_263to240_MASK 0x00ffffffL -#define GPM_CMN_debug_17_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_18_data -#define GPM_CMN_debug_18_data__f32DebugBus_287to264_MASK 0x00ffffffL -#define GPM_CMN_debug_18_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_19_data -#define GPM_CMN_debug_19_data__f32DebugBus_311to288_MASK 0x00ffffffL -#define GPM_CMN_debug_19_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_20_data -#define GPM_CMN_debug_20_data__f32DebugBus_335to312_MASK 0x00ffffffL -#define GPM_CMN_debug_20_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_21_data -#define GPM_CMN_debug_21_data__f32DebugBus_359to336_MASK 0x00ffffffL -#define GPM_CMN_debug_21_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_22_data -#define GPM_CMN_debug_22_data__f32DebugBus_383to360_MASK 0x00ffffffL -#define GPM_CMN_debug_22_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_23_data -#define GPM_CMN_debug_23_data__f32DebugBus_407to384_MASK 0x00ffffffL -#define GPM_CMN_debug_23_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_24_data -#define GPM_CMN_debug_24_data__f32DebugBus_431to408_MASK 0x00ffffffL -#define GPM_CMN_debug_24_data__Reserved0_MASK 0xff000000L - -// GPM_CMN_debug_25_data -#define GPM_CMN_debug_25_data__f32DebugBus_447to432_MASK 0x0000ffffL -#define GPM_CMN_debug_25_data__GRBM_SCRATCH_rreg_valid_MASK 0x00010000L -#define GPM_CMN_debug_25_data__GRBM_SCRATCH_wreg_valid_MASK 0x00020000L -#define GPM_CMN_debug_25_data__Unassigned_MASK 0x00fc0000L -#define GPM_CMN_debug_25_data__Reserved0_MASK 0xff000000L - -// SPM_CMN_debug_0_data -#define SPM_CMN_debug_0_data__Reserved1_MASK 0x0000000fL -#define SPM_CMN_debug_0_data__SpmInterrupteDetected_MASK 0x00000010L -#define SPM_CMN_debug_0_data__McFifoEmpty_MASK 0x00000020L -#define SPM_CMN_debug_0_data__GlobalFifoEmpty_MASK 0x00000040L -#define SPM_CMN_debug_0_data__WptrFifoEmpty_MASK 0x00000080L -#define SPM_CMN_debug_0_data__GlobalFifoFull_MASK 0x00000100L -#define SPM_CMN_debug_0_data__SpmCurrentState_MASK 0x00000e00L -#define SPM_CMN_debug_0_data__SeSegmentDone_MASK 0x00001000L -#define SPM_CMN_debug_0_data__GlobalSegmentDone_MASK 0x00002000L -#define SPM_CMN_debug_0_data__WptrFifoFull_MASK 0x00004000L -#define SPM_CMN_debug_0_data__McFifoFull_MASK 0x00008000L -#define SPM_CMN_debug_0_data__SampleTimerExpired_MASK 0x00010000L -#define SPM_CMN_debug_0_data__SpmStopCounting_MASK 0x00020000L -#define SPM_CMN_debug_0_data__SpmStartCounting_MASK 0x00040000L -#define SPM_CMN_debug_0_data__StopSampleTimer_MASK 0x00080000L -#define SPM_CMN_debug_0_data__StartSampleTimer_MASK 0x00100000L -#define SPM_CMN_debug_0_data__SpmStall_MASK 0x00200000L -#define SPM_CMN_debug_0_data__SpmDebugStall_MASK 0x00400000L -#define SPM_CMN_debug_0_data__SpmRingAlmostFull_q_MASK 0x00800000L -#define SPM_CMN_debug_0_data__Reserved0_MASK 0xff000000L - -// SPM_CMN_debug_1_data -#define SPM_CMN_debug_1_data__Reserved1_MASK 0x0000001fL -#define SPM_CMN_debug_1_data__SpmId_MASK 0x00000020L -#define SPM_CMN_debug_1_data__SpmDeSerCurrentState_MASK 0x00000fc0L -#define SPM_CMN_debug_1_data__Se3FifoFull_MASK 0x00001000L -#define SPM_CMN_debug_1_data__Se3FifoEmpty_MASK 0x00002000L -#define SPM_CMN_debug_1_data__Se3SegmentDone_MASK 0x00004000L -#define SPM_CMN_debug_1_data__Se2FifoFull_MASK 0x00008000L -#define SPM_CMN_debug_1_data__Se2FifoEmpty_MASK 0x00010000L -#define SPM_CMN_debug_1_data__Se2SegmentDone_MASK 0x00020000L -#define SPM_CMN_debug_1_data__Se1FifoFull_MASK 0x00040000L -#define SPM_CMN_debug_1_data__Se1FifoEmpty_MASK 0x00080000L -#define SPM_CMN_debug_1_data__Se1SegmentDone_MASK 0x00100000L -#define SPM_CMN_debug_1_data__Se0FifoFull_MASK 0x00200000L -#define SPM_CMN_debug_1_data__Se0FifoEmpty_MASK 0x00400000L -#define SPM_CMN_debug_1_data__Se0SegmentDone_MASK 0x00800000L -#define SPM_CMN_debug_1_data__Reserved0_MASK 0xff000000L - -// SPM_CMN_debug_2_data -#define SPM_CMN_debug_2_data__Reserved0_MASK 0xffffffffL - -// SPM_CMN_debug_3_data -#define SPM_CMN_debug_3_data__Reserved0_MASK 0xffffffffL - -// SPM_CMN_debug_4_data -#define SPM_CMN_debug_4_data__Reserved0_MASK 0xffffffffL - -// SPM_CMN_debug_5_data -#define SPM_CMN_debug_5_data__Reserved0_MASK 0xffffffffL - -// SPM_CMN_debug_6_data -#define SPM_CMN_debug_6_data__Reserved0_MASK 0xffffffffL - -// SPM_CMN_debug_7_data -#define SPM_CMN_debug_7_data__Reserved0_MASK 0xffffffffL - -// SPM_CMN_debug_8_data -#define SPM_CMN_debug_8_data__Reserved0_MASK 0xffffffffL - -// SPM_CMN_debug_9_data -#define SPM_CMN_debug_9_data__Reserved0_MASK 0xffffffffL - -// SRM_CMN_debug_0_data -#define SRM_CMN_debug_0_data__SrmGpmAbort_MASK 0x00000001L -#define SRM_CMN_debug_0_data__SrmCmdArb_MASK 0x00000006L -#define SRM_CMN_debug_0_data__SrmCmdDone_MASK 0x00000008L -#define SRM_CMN_debug_0_data__SrmState_MASK 0x000000f0L -#define SRM_CMN_debug_0_data__SrmCmdIndexSel_MASK 0x00000700L -#define SRM_CMN_debug_0_data__SrmGpmCmdFifoEmpty_MASK 0x00000800L -#define SRM_CMN_debug_0_data__SrmAramRamRdEn_MASK 0x00001000L -#define SRM_CMN_debug_0_data__SrmAramRamWrEn_MASK 0x00002000L -#define SRM_CMN_debug_0_data__SrmAramRamWrAddr_MASK 0x00ffc000L -#define SRM_CMN_debug_0_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_1_data -#define SRM_CMN_debug_1_data__SrmAramRamWrData_MASK 0x00ffffffL -#define SRM_CMN_debug_1_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_2_data -#define SRM_CMN_debug_2_data__SrmAramRamWrData_MASK 0x00ffffffL -#define SRM_CMN_debug_2_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_3_data -#define SRM_CMN_debug_3_data__SrmDramRamWrData_MASK 0x00000fffL -#define SRM_CMN_debug_3_data__SrmDramRamWrAddr_9to0_MASK 0x003ff000L -#define SRM_CMN_debug_3_data__SrmDramRamWrEn_MASK 0x00400000L -#define SRM_CMN_debug_3_data__SrmDramRamRdEn_MASK 0x00800000L -#define SRM_CMN_debug_3_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_4_data -#define SRM_CMN_debug_4_data__SrmDramRamWrData_31to12_MASK 0x003fffffL -#define SRM_CMN_debug_4_data__RLC_SRM_CMN_grbmc_wr_rtr_MASK 0x00400000L -#define SRM_CMN_debug_4_data__SrmDramRamRdEn_MASK 0x00800000L -#define SRM_CMN_debug_4_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_5_data -#define SRM_CMN_debug_5_data__SrmGrbmcWrFifoWrData_23to0_MASK 0x00ffffffL -#define SRM_CMN_debug_5_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_6_data -#define SRM_CMN_debug_6_data__SrmGrbmcWrFifoWrData_47to24_MASK 0x00ffffffL -#define SRM_CMN_debug_6_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_7_data -#define SRM_CMN_debug_7_data__SrmGrbmcWrFifoWrData_71to48_MASK 0x00ffffffL -#define SRM_CMN_debug_7_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_8_data -#define SRM_CMN_debug_8_data__SrmGrbmcWrFifoWrData_79to72_MASK 0x000000ffL -#define SRM_CMN_debug_8_data__SrmGrbmcRdFifoWe_MASK 0x00000100L -#define SRM_CMN_debug_8_data__SrmGrbmcRdFifoRe_MASK 0x00000200L -#define SRM_CMN_debug_8_data__SrmGrbmcRdFifoWrData_13to0_MASK 0x00fffc00L -#define SRM_CMN_debug_8_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_9_data -#define SRM_CMN_debug_9_data__SrmGrbmcRdFifoWrData_37to14_MASK 0x00ffffffL -#define SRM_CMN_debug_9_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_10_data -#define SRM_CMN_debug_10_data__SrmGrbmcRdFifoWrData_47to38_MASK 0x000003ffL -#define SRM_CMN_debug_10_data__RLC_SRM_CMN_grbmc_rd_rtn_data_11to0_MASK 0x003ffc00L -#define SRM_CMN_debug_10_data__SrmGrbmcRdRtnFifoRd_MASK 0x00400000L -#define SRM_CMN_debug_10_data__RLC_SRM_CMN_grbmc_rd_rtn_valid_MASK 0x00800000L -#define SRM_CMN_debug_10_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_11_data -#define SRM_CMN_debug_11_data__RLC_SRM_CMN_grbmc_rd_rtn_data_31to12_MASK 0x000fffffL -#define SRM_CMN_debug_11_data__SrmGpmCmdFifoRd_MASK 0x00100000L -#define SRM_CMN_debug_11_data__SrmGpmCommand_We_MASK 0x00200000L -#define SRM_CMN_debug_11_data__Reserved0_MASK 0xffc00000L - -// SRM_CMN_debug_12_data -#define SRM_CMN_debug_12_data__Reg_wd_31to12_MASK 0x0007ffffL -#define SRM_CMN_debug_12_data__SrmGpmCmdFifoRdData_3to0_MASK 0x00f80000L -#define SRM_CMN_debug_12_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_13_data -#define SRM_CMN_debug_13_data__SrmGpmCmdFifoRdData_27to4_MASK 0x00ffffffL -#define SRM_CMN_debug_13_data__Reserved0_MASK 0xff000000L - -// SRM_CMN_debug_14_data -#define SRM_CMN_debug_14_data__SrmGpmCmdFifoRdData_31to28_MASK 0x0000000fL -#define SRM_CMN_debug_14_data__SrmRlcvCmdFifoRd_MASK 0x00000010L -#define SRM_CMN_debug_14_data__SrmRlcvCommand_we_MASK 0x00000020L -#define SRM_CMN_debug_14_data__Reg_wd_11to0_MASK 0x0003ffc0L -#define SRM_CMN_debug_14_data__Reserved0_MASK 0xfffc0000L - -// SRM_CMN_debug_15_data -#define SRM_CMN_debug_15_data__Reserved0_MASK 0xffffffffL - -// CB_DEBUGBUS_1 -#define CB_DEBUGBUS_1__CB_BUSY_MASK 0x00000001L -#define CB_DEBUGBUS_1__DB_CB_TILE_VALID_READY_MASK 0x00000002L -#define CB_DEBUGBUS_1__DB_CB_TILE_VALID_READYB_MASK 0x00000004L -#define CB_DEBUGBUS_1__DB_CB_TILE_VALIDB_READY_MASK 0x00000008L -#define CB_DEBUGBUS_1__DB_CB_TILE_VALIDB_READYB_MASK 0x00000010L -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALID_READY_MASK 0x00000020L -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALID_READYB_MASK 0x00000040L -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALIDB_READY_MASK 0x00000080L -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALIDB_READYB_MASK 0x00000100L -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALID_READY_MASK 0x00000200L -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALID_READYB_MASK 0x00000400L -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK 0x00000800L -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALIDB_READYB_MASK 0x00001000L -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALID_READY_MASK 0x00002000L -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALID_READYB_MASK 0x00004000L -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALIDB_READY_MASK 0x00008000L -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALIDB_READYB_MASK 0x00010000L -#define CB_DEBUGBUS_1__CM_FC_TILE_VALID_READY_MASK 0x00020000L -#define CB_DEBUGBUS_1__CM_FC_TILE_VALID_READYB_MASK 0x00040000L -#define CB_DEBUGBUS_1__CM_FC_TILE_VALIDB_READY_MASK 0x00080000L -#define CB_DEBUGBUS_1__CM_FC_TILE_VALIDB_READYB_MASK 0x00100000L -#define CB_DEBUGBUS_1__FC_CLEAR_QUAD_VALID_READY_MASK 0x00200000L -#define CB_DEBUGBUS_1__FC_CLEAR_QUAD_VALID_READYB_MASK 0x00400000L -#define CB_DEBUGBUS_1__FC_CLEAR_QUAD_VALIDB_READY_MASK 0x00800000L -#define CB_DEBUGBUS_1__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_2 -#define CB_DEBUGBUS_2__FC_CLEAR_QUAD_VALIDB_READYB_MASK 0x00000001L -#define CB_DEBUGBUS_2__FC_QUAD_RESIDENCY_STALL_MASK 0x00000002L -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALID_READY_MASK 0x00000004L -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALID_READYB_MASK 0x00000008L -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALIDB_READY_MASK 0x00000010L -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALIDB_READYB_MASK 0x00000020L -#define CB_DEBUGBUS_2__FOP_IN_VALID_READY_MASK 0x00000040L -#define CB_DEBUGBUS_2__FOP_IN_VALID_READYB_MASK 0x00000080L -#define CB_DEBUGBUS_2__FOP_IN_VALIDB_READY_MASK 0x00000100L -#define CB_DEBUGBUS_2__FOP_IN_VALIDB_READYB_MASK 0x00000200L -#define CB_DEBUGBUS_2__FOP_FMASK_RAW_STALL_MASK 0x00000400L -#define CB_DEBUGBUS_2__FOP_FMASK_BYPASS_STALL_MASK 0x00000800L -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALID_READY_MASK 0x00001000L -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALID_READYB_MASK 0x00002000L -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALIDB_READY_MASK 0x00004000L -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALIDB_READYB_MASK 0x00008000L -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALID_READY_MASK 0x00010000L -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALID_READYB_MASK 0x00020000L -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALIDB_READY_MASK 0x00040000L -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALIDB_READYB_MASK 0x00080000L -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALID_READY_MASK 0x00100000L -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALID_READYB_MASK 0x00200000L -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY_MASK 0x00400000L -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB_MASK 0x00800000L -#define CB_DEBUGBUS_2__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_3 -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALID_READY_MASK 0x00000001L -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALID_READYB_MASK 0x00000002L -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY_MASK 0x00000004L -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB_MASK 0x00000008L -#define CB_DEBUGBUS_3__CC_BC_CS_FRAG_VALID_MASK 0x00000010L -#define CB_DEBUGBUS_3__CC_SF_FULL_MASK 0x00000020L -#define CB_DEBUGBUS_3__CC_RB_FULL_MASK 0x00000040L -#define CB_DEBUGBUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL_MASK 0x00000080L -#define CB_DEBUGBUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL_MASK 0x00000100L -#define CB_DEBUGBUS_3__CM_TQ_FULL_MASK 0x00000200L -#define CB_DEBUGBUS_3__CM_TILE_RESIDENCY_STALL_MASK 0x00000400L -#define CB_DEBUGBUS_3__LQUAD_NO_TILE_MASK 0x00000800L -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_R_MASK 0x00001000L -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR_MASK 0x00002000L -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR_MASK 0x00004000L -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR_MASK 0x00008000L -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR_MASK 0x00010000L -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR_MASK 0x00020000L -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR_MASK 0x00040000L -#define CB_DEBUGBUS_3__CM_CACHE_HIT_MASK 0x00080000L -#define CB_DEBUGBUS_3__CM_CACHE_TAG_MISS_MASK 0x00100000L -#define CB_DEBUGBUS_3__CM_CACHE_SECTOR_MISS_MASK 0x00200000L -#define CB_DEBUGBUS_3__CM_CACHE_REEVICTION_STALL_MASK 0x00400000L -#define CB_DEBUGBUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x00800000L -#define CB_DEBUGBUS_3__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_4 -#define CB_DEBUGBUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x00000001L -#define CB_DEBUGBUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x00000002L -#define CB_DEBUGBUS_4__CM_CACHE_READ_OUTPUT_STALL_MASK 0x00000004L -#define CB_DEBUGBUS_4__CM_CACHE_WRITE_OUTPUT_STALL_MASK 0x00000008L -#define CB_DEBUGBUS_4__CM_CACHE_ACK_OUTPUT_STALL_MASK 0x00000010L -#define CB_DEBUGBUS_4__CM_CACHE_STALL_MASK 0x00000020L -#define CB_DEBUGBUS_4__FC_CACHE_HIT_MASK 0x00000040L -#define CB_DEBUGBUS_4__FC_CACHE_TAG_MISS_MASK 0x00000080L -#define CB_DEBUGBUS_4__FC_CACHE_SECTOR_MISS_MASK 0x00000100L -#define CB_DEBUGBUS_4__FC_CACHE_REEVICTION_STALL_MASK 0x00000200L -#define CB_DEBUGBUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x00000400L -#define CB_DEBUGBUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x00000800L -#define CB_DEBUGBUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x00001000L -#define CB_DEBUGBUS_4__FC_CACHE_READ_OUTPUT_STALL_MASK 0x00002000L -#define CB_DEBUGBUS_4__FC_CACHE_WRITE_OUTPUT_STALL_MASK 0x00004000L -#define CB_DEBUGBUS_4__FC_CACHE_ACK_OUTPUT_STALL_MASK 0x00008000L -#define CB_DEBUGBUS_4__FC_CACHE_STALL_MASK 0x00010000L -#define CB_DEBUGBUS_4__CC_CACHE_HIT_MASK 0x00020000L -#define CB_DEBUGBUS_4__CC_CACHE_TAG_MISS_MASK 0x00040000L -#define CB_DEBUGBUS_4__CC_CACHE_SECTOR_MISS_MASK 0x00080000L -#define CB_DEBUGBUS_4__CC_CACHE_REEVICTION_STALL_MASK 0x00100000L -#define CB_DEBUGBUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x00200000L -#define CB_DEBUGBUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x00400000L -#define CB_DEBUGBUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x00800000L -#define CB_DEBUGBUS_4__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_5 -#define CB_DEBUGBUS_5__CC_CACHE_READ_OUTPUT_STALL_MASK 0x00000001L -#define CB_DEBUGBUS_5__CC_CACHE_WRITE_OUTPUT_STALL_MASK 0x00000002L -#define CB_DEBUGBUS_5__CC_CACHE_ACK_OUTPUT_STALL_MASK 0x00000004L -#define CB_DEBUGBUS_5__CC_CACHE_STALL_MASK 0x00000008L -#define CB_DEBUGBUS_5__CC_CACHE_WA_TO_RMW_CONVERSION_MASK 0x00000010L -#define CB_DEBUGBUS_5__CM_CACHE_FLUSH_MASK 0x00000020L -#define CB_DEBUGBUS_5__CM_CACHE_TAGS_FLUSHED_MASK 0x00000040L -#define CB_DEBUGBUS_5__CM_CACHE_SECTORS_FLUSHED_MASK 0x00000080L -#define CB_DEBUGBUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x00000100L -#define CB_DEBUGBUS_5__FC_CACHE_FLUSH_MASK 0x00000200L -#define CB_DEBUGBUS_5__FC_CACHE_TAGS_FLUSHED_MASK 0x00000400L -#define CB_DEBUGBUS_5__FC_CACHE_SECTORS_FLUSHED_MASK 0x00003800L -#define CB_DEBUGBUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x0001c000L -#define CB_DEBUGBUS_5__CC_CACHE_FLUSH_MASK 0x00020000L -#define CB_DEBUGBUS_5__CC_CACHE_TAGS_FLUSHED_MASK 0x00040000L -#define CB_DEBUGBUS_5__CC_CACHE_SECTORS_FLUSHED_MASK 0x00380000L - -// CB_DEBUGBUS_6 -#define CB_DEBUGBUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x00000007L -#define CB_DEBUGBUS_6__CM_MC_READ_REQUEST_MASK 0x00000008L -#define CB_DEBUGBUS_6__FC_MC_READ_REQUEST_MASK 0x00000010L -#define CB_DEBUGBUS_6__CC_MC_READ_REQUEST_MASK 0x00000020L -#define CB_DEBUGBUS_6__CM_MC_WRITE_REQUEST_MASK 0x00000040L -#define CB_DEBUGBUS_6__FC_MC_WRITE_REQUEST_MASK 0x00000080L -#define CB_DEBUGBUS_6__CC_MC_WRITE_REQUEST_MASK 0x00000100L -#define CB_DEBUGBUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x0001fe00L - -// CB_DEBUGBUS_7 -#define CB_DEBUGBUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x000007ffL -#define CB_DEBUGBUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x001ff800L - -// CB_DEBUGBUS_8 -#define CB_DEBUGBUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x000000ffL -#define CB_DEBUGBUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x0007ff00L -#define CB_DEBUGBUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE_MASK 0x00080000L -#define CB_DEBUGBUS_8__FC_SEQUENCER_FMASK_DECOMPRESS_MASK 0x00100000L -#define CB_DEBUGBUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR_MASK 0x00200000L -#define CB_DEBUGBUS_8__FC_SEQUENCER_CLEAR_MASK 0x00400000L - -// CB_DEBUGBUS_9 -#define CB_DEBUGBUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x000003ffL -#define CB_DEBUGBUS_9__CC_SURFACE_SYNC_MASK 0x00000400L -#define CB_DEBUGBUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK 0x00000800L -#define CB_DEBUGBUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT_MASK 0x00001000L -#define CB_DEBUGBUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT_MASK 0x00002000L -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_QUAD_MASK 0x00004000L -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_PIXEL_MASK 0x00078000L -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT_MASK 0x00080000L -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_TILE_MASK 0x00100000L -#define CB_DEBUGBUS_9__EVENT_ALL_MASK 0x00200000L -#define CB_DEBUGBUS_9__EVENT_CACHE_FLUSH_TS_MASK 0x00400000L -#define CB_DEBUGBUS_9__EVENT_CONTEXT_DONE_MASK 0x00800000L -#define CB_DEBUGBUS_9__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_10 -#define CB_DEBUGBUS_10__EVENT_CACHE_FLUSH_MASK 0x00000001L -#define CB_DEBUGBUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000002L -#define CB_DEBUGBUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT_MASK 0x00000004L -#define CB_DEBUGBUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS_MASK 0x00000008L -#define CB_DEBUGBUS_10__EVENT_FLUSH_AND_INV_CB_META_MASK 0x00000010L -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XC_MASK 0x00000020L -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XD_MASK 0x00000040L -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XE_MASK 0x00000080L -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XF_MASK 0x00000100L -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XC_MASK 0x00000200L -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XD_MASK 0x00000400L -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XE_MASK 0x00000800L -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XF_MASK 0x00001000L -#define CB_DEBUGBUS_10__CORE_SCLK_VLD_MASK 0x00002000L -#define CB_DEBUGBUS_10__REG_SCLK0_VLD_MASK 0x00004000L -#define CB_DEBUGBUS_10__REG_SCLK1_VLD_MASK 0x00008000L -#define CB_DEBUGBUS_10__MERGE_TILE_ONLY_VALID_READY_MASK 0x00010000L -#define CB_DEBUGBUS_10__MERGE_TILE_ONLY_VALID_READYB_MASK 0x00020000L -#define CB_DEBUGBUS_10__FC_QUAD_RDLAT_FIFO_FULL_MASK 0x00040000L -#define CB_DEBUGBUS_10__FC_TILE_RDLAT_FIFO_FULL_MASK 0x00080000L -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE_MASK 0x00100000L -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE_MASK 0x00200000L -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE_MASK 0x00400000L -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE_MASK 0x00800000L -#define CB_DEBUGBUS_10__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_11 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE_MASK 0x00000001L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE_MASK 0x00000002L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE_MASK 0x00000004L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE_MASK 0x00000008L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE_MASK 0x00000010L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE_MASK 0x00000020L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE_MASK 0x00000040L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE_MASK 0x00000080L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE_MASK 0x00000100L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE_MASK 0x00000200L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE_MASK 0x00000400L -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK 0x00000800L -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_1_FRAGMENT_MASK 0x00001000L -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_2_FRAGMENTS_MASK 0x00002000L -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_3_FRAGMENTS_MASK 0x00004000L -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_4_FRAGMENTS_MASK 0x00008000L -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_5_FRAGMENTS_MASK 0x00010000L -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_6_FRAGMENTS_MASK 0x00020000L -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_7_FRAGMENTS_MASK 0x00040000L -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_1_FRAGMENT_MASK 0x00080000L -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS_MASK 0x00100000L -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS_MASK 0x00200000L -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS_MASK 0x00400000L -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS_MASK 0x00800000L -#define CB_DEBUGBUS_11__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_12 -#define CB_DEBUGBUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS_MASK 0x00000001L -#define CB_DEBUGBUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS_MASK 0x00000002L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0_MASK 0x00000004L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1_MASK 0x00000008L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2_MASK 0x00000010L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3_MASK 0x00000020L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4_MASK 0x00000040L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5_MASK 0x00000080L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6_MASK 0x00000100L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7_MASK 0x00000200L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0_MASK 0x00000400L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK 0x00000800L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2_MASK 0x00001000L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3_MASK 0x00002000L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4_MASK 0x00004000L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5_MASK 0x00008000L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6_MASK 0x00010000L -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7_MASK 0x00020000L -#define CB_DEBUGBUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST_MASK 0x00040000L -#define CB_DEBUGBUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS_MASK 0x00080000L -#define CB_DEBUGBUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS_MASK 0x00100000L -#define CB_DEBUGBUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT_MASK 0x00200000L -#define CB_DEBUGBUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID_MASK 0x00400000L -#define CB_DEBUGBUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK_MASK 0x00800000L -#define CB_DEBUGBUS_12__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_13 -#define CB_DEBUGBUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL_MASK 0x00000001L -#define CB_DEBUGBUS_13__FC_DOC_QTILE_CAM_MISS_MASK 0x00000002L -#define CB_DEBUGBUS_13__FC_DOC_QTILE_CAM_HIT_MASK 0x00000004L -#define CB_DEBUGBUS_13__FC_DOC_CLINE_CAM_MISS_MASK 0x00000008L -#define CB_DEBUGBUS_13__FC_DOC_CLINE_CAM_HIT_MASK 0x00000010L -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_1_SECTOR_MASK 0x00000020L -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_2_SECTORS_MASK 0x00000040L -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_3_SECTORS_MASK 0x00000080L -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_4_SECTORS_MASK 0x00000100L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_HIT_MASK 0x00000200L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_TAG_MISS_MASK 0x00000400L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_SECTOR_MISS_MASK 0x00000800L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL_MASK 0x00001000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x00002000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x00004000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x00008000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL_MASK 0x00010000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL_MASK 0x00020000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL_MASK 0x00040000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_STALL_MASK 0x00080000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_FLUSH_MASK 0x00100000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED_MASK 0x00200000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x00400000L -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED_MASK 0x00800000L -#define CB_DEBUGBUS_13__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_14 -#define CB_DEBUGBUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x000007ffL -#define CB_DEBUGBUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT_MASK 0x003ff800L -#define CB_DEBUGBUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT_MASK 0x00400000L -#define CB_DEBUGBUS_14__CC_PF_DCC_RDREQ_STALL_MASK 0x00800000L -#define CB_DEBUGBUS_14__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_15 -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1_MASK 0x00000007L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1_MASK 0x00000018L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2_MASK 0x00000060L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3_MASK 0x00000180L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1_MASK 0x00000600L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2_MASK 0x00001800L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3_MASK 0x00006000L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4_MASK 0x00018000L -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5_MASK 0x00060000L - -// CB_DEBUGBUS_16 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1_MASK 0x00000001L -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2_MASK 0x00000002L -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3_MASK 0x00000004L -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4_MASK 0x00000008L -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5_MASK 0x00000010L -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6_MASK 0x00000020L -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7_MASK 0x00000040L - -// CB_DEBUGBUS_17 -#define CB_DEBUGBUS_17__TILE_INTFC_BUSY_MASK 0x00000001L -#define CB_DEBUGBUS_17__MU_BUSY_MASK 0x00000002L -#define CB_DEBUGBUS_17__TQ_BUSY_MASK 0x00000004L -#define CB_DEBUGBUS_17__AC_BUSY_MASK 0x00000008L -#define CB_DEBUGBUS_17__CRW_BUSY_MASK 0x00000010L -#define CB_DEBUGBUS_17__CACHE_CTRL_BUSY_MASK 0x00000020L -#define CB_DEBUGBUS_17__MC_WR_PENDING_MASK 0x00000040L -#define CB_DEBUGBUS_17__FC_WR_PENDING_MASK 0x00000080L -#define CB_DEBUGBUS_17__FC_RD_PENDING_MASK 0x00000100L -#define CB_DEBUGBUS_17__EVICT_PENDING_MASK 0x00000200L -#define CB_DEBUGBUS_17__LAST_RD_ARB_WINNER_MASK 0x00000400L -#define CB_DEBUGBUS_17__MU_STATE_MASK 0x0007f800L - -// CB_DEBUGBUS_18 -#define CB_DEBUGBUS_18__TILE_RETIREMENT_BUSY_MASK 0x00000001L -#define CB_DEBUGBUS_18__FOP_BUSY_MASK 0x00000002L -#define CB_DEBUGBUS_18__CLEAR_BUSY_MASK 0x00000004L -#define CB_DEBUGBUS_18__LAT_BUSY_MASK 0x00000008L -#define CB_DEBUGBUS_18__CACHE_CTL_BUSY_MASK 0x00000010L -#define CB_DEBUGBUS_18__ADDR_BUSY_MASK 0x00000020L -#define CB_DEBUGBUS_18__MERGE_BUSY_MASK 0x00000040L -#define CB_DEBUGBUS_18__QUAD_BUSY_MASK 0x00000080L -#define CB_DEBUGBUS_18__TILE_BUSY_MASK 0x00000100L -#define CB_DEBUGBUS_18__DCC_BUSY_MASK 0x00000200L -#define CB_DEBUGBUS_18__DOC_BUSY_MASK 0x00000400L -#define CB_DEBUGBUS_18__DAG_BUSY_MASK 0x00000800L -#define CB_DEBUGBUS_18__DOC_STALL_MASK 0x00001000L -#define CB_DEBUGBUS_18__DOC_QT_CAM_FULL_MASK 0x00002000L -#define CB_DEBUGBUS_18__DOC_CL_CAM_FULL_MASK 0x00004000L -#define CB_DEBUGBUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x00008000L -#define CB_DEBUGBUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x00010000L -#define CB_DEBUGBUS_18__DCS_READ_WINNER_LAST_MASK 0x00020000L -#define CB_DEBUGBUS_18__DCS_READ_EV_PENDING_MASK 0x00040000L -#define CB_DEBUGBUS_18__DCS_WRITE_CC_PENDING_MASK 0x00080000L -#define CB_DEBUGBUS_18__DCS_READ_CC_PENDING_MASK 0x00100000L -#define CB_DEBUGBUS_18__DCS_WRITE_MC_PENDING_MASK 0x00200000L - -// CB_DEBUGBUS_19 -#define CB_DEBUGBUS_19__SURF_SYNC_STATE_MASK 0x00000003L -#define CB_DEBUGBUS_19__SURF_SYNC_START_MASK 0x00000004L -#define CB_DEBUGBUS_19__SF_BUSY_MASK 0x00000008L -#define CB_DEBUGBUS_19__CS_BUSY_MASK 0x00000010L -#define CB_DEBUGBUS_19__RB_BUSY_MASK 0x00000020L -#define CB_DEBUGBUS_19__DS_BUSY_MASK 0x00000040L -#define CB_DEBUGBUS_19__TB_BUSY_MASK 0x00000080L -#define CB_DEBUGBUS_19__IB_BUSY_MASK 0x00000100L -#define CB_DEBUGBUS_19__DRR_BUSY_MASK 0x00000200L -#define CB_DEBUGBUS_19__DF_BUSY_MASK 0x00000400L -#define CB_DEBUGBUS_19__DD_BUSY_MASK 0x00000800L -#define CB_DEBUGBUS_19__DC_BUSY_MASK 0x00001000L -#define CB_DEBUGBUS_19__DK_BUSY_MASK 0x00002000L -#define CB_DEBUGBUS_19__DF_SKID_FIFO_EMPTY_MASK 0x00004000L -#define CB_DEBUGBUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x00008000L -#define CB_DEBUGBUS_19__DD_READY_MASK 0x00010000L -#define CB_DEBUGBUS_19__DC_FIFO_FULL_MASK 0x00020000L -#define CB_DEBUGBUS_19__DC_READY_MASK 0x00040000L - -// CB_DEBUGBUS_20 -#define CB_DEBUGBUS_20__MC_RDREQ_CREDITS_MASK 0x0000003fL -#define CB_DEBUGBUS_20__MC_WRREQ_CREDITS_MASK 0x00000fc0L -#define CB_DEBUGBUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x00001000L -#define CB_DEBUGBUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x00002000L -#define CB_DEBUGBUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x00004000L -#define CB_DEBUGBUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x00010000L -#define CB_DEBUGBUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x00020000L -#define CB_DEBUGBUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x00040000L -#define CB_DEBUGBUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x00100000L -#define CB_DEBUGBUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x00200000L -#define CB_DEBUGBUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x00400000L -#define CB_DEBUGBUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x00800000L -#define CB_DEBUGBUS_20__Reserved0_MASK 0xff000000L - -// CB_DEBUGBUS_21 -#define CB_DEBUGBUS_21__CM_BUSY_MASK 0x00000001L -#define CB_DEBUGBUS_21__FC_BUSY_MASK 0x00000002L -#define CB_DEBUGBUS_21__CC_BUSY_MASK 0x00000004L -#define CB_DEBUGBUS_21__BB_BUSY_MASK 0x00000008L -#define CB_DEBUGBUS_21__MA_BUSY_MASK 0x00000010L -#define CB_DEBUGBUS_21__CORE_SCLK_VLD_MASK 0x00000020L -#define CB_DEBUGBUS_21__REG_SCLK1_VLD_MASK 0x00000040L -#define CB_DEBUGBUS_21__REG_SCLK0_VLD_MASK 0x00000080L - -// CB_DEBUGBUS_22 -#define CB_DEBUGBUS_22__OUTSTANDING_MC_READS_MASK 0x00000fffL -#define CB_DEBUGBUS_22__OUTSTANDING_MC_WRITES_MASK 0x00fff000L -#define CB_DEBUGBUS_22__Reserved0_MASK 0xff000000L - -// PA_DEBUG00_0 -#define PA_DEBUG00_0__clip_ga_bc_fifo_write_MASK 0x00000001L -#define PA_DEBUG00_0__su_clip_baryc_free_MASK 0x00000006L -#define PA_DEBUG00_0__clip_to_ga_fifo_write_MASK 0x00000008L -#define PA_DEBUG00_0__clip_to_ga_fifo_full_MASK 0x00000010L -#define PA_DEBUG00_0__primic_to_clprim_fifo_empty_MASK 0x00000020L -#define PA_DEBUG00_0__primic_to_clprim_fifo_full_MASK 0x00000040L -#define PA_DEBUG00_0__clip_to_outsm_fifo_empty_MASK 0x00000080L -#define PA_DEBUG00_0__clip_to_outsm_fifo_full_MASK 0x00000100L -#define PA_DEBUG00_0__vgt_to_clipp_fifo_empty_MASK 0x00000200L -#define PA_DEBUG00_0__vgt_to_clipp_fifo_full_MASK 0x00000400L -#define PA_DEBUG00_0__vgt_to_clips_fifo_empty_MASK 0x00000800L -#define PA_DEBUG00_0__vgt_to_clips_fifo_full_MASK 0x00001000L -#define PA_DEBUG00_0__clipcode_fifo_fifo_empty_MASK 0x00002000L -#define PA_DEBUG00_0__clipcode_fifo_full_MASK 0x00004000L -#define PA_DEBUG00_0__vte_out_clip_fifo_fifo_empty_MASK 0x00008000L -#define PA_DEBUG00_0__vte_out_clip_fifo_fifo_full_MASK 0x00010000L -#define PA_DEBUG00_0__vte_out_orig_fifo_fifo_empty_MASK 0x00020000L -#define PA_DEBUG00_0__vte_out_orig_fifo_fifo_full_MASK 0x00040000L -#define PA_DEBUG00_0__ccgen_to_clipcc_fifo_empty_MASK 0x00080000L -#define PA_DEBUG00_0__ccgen_to_clipcc_fifo_full_MASK 0x00100000L -#define PA_DEBUG00_0__clip_to_outsm_fifo_write_MASK 0x00200000L -#define PA_DEBUG00_0__vte_out_orig_fifo_fifo_write_MASK 0x00400000L -#define PA_DEBUG00_0__vgt_to_clipp_fifo_write_MASK 0x00800000L -#define PA_DEBUG00_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG00_1 -#define PA_DEBUG00_1__vertex_fifo_entriesavailable_MASK 0x0000000fL -#define PA_DEBUG00_1__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x00000010L -#define PA_DEBUG00_1__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x00000020L -#define PA_DEBUG00_1__available_positions_MASK 0x00001fc0L -#define PA_DEBUG00_1__current_state_MASK 0x00006000L -#define PA_DEBUG00_1__vertex_fifo_empty_MASK 0x00008000L -#define PA_DEBUG00_1__vertex_fifo_full_MASK 0x00010000L -#define PA_DEBUG00_1__sx0_receive_fifo_empty_MASK 0x00020000L -#define PA_DEBUG00_1__sx0_receive_fifo_full_MASK 0x00040000L -#define PA_DEBUG00_1__vgt_to_ccgen_fifo_empty_MASK 0x00080000L -#define PA_DEBUG00_1__vgt_to_ccgen_fifo_full_MASK 0x00100000L -#define PA_DEBUG00_1__ccgen_to_clipcc_fifo_full_MASK 0x00200000L -#define PA_DEBUG00_1__sx0_receive_fifo_write_MASK 0x00400000L -#define PA_DEBUG00_1__ccgen_to_clipcc_write_MASK 0x00800000L -#define PA_DEBUG00_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG01_0 -#define PA_DEBUG01_0__clip_extra_bc_valid_MASK 0x00000007L -#define PA_DEBUG01_0__clip_vert_vte_valid_MASK 0x00000020L -#define PA_DEBUG01_0__clip_to_outsm_vertex_deallocate_MASK 0x000001c0L -#define PA_DEBUG01_0__clip_to_outsm_deallocate_slot_MASK 0x00000e00L -#define PA_DEBUG01_0__clip_to_outsm_null_primitive_MASK 0x00001000L -#define PA_DEBUG01_0__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00002000L -#define PA_DEBUG01_0__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00004000L -#define PA_DEBUG01_0__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00008000L -#define PA_DEBUG01_0__vte_out_clip_rd_extra_bc_valid_MASK 0x00010000L -#define PA_DEBUG01_0__vte_out_clip_rd_vte_naninf_kill_MASK 0x00020000L -#define PA_DEBUG01_0__vte_out_clip_rd_vertex_store_indx_MASK 0x000c0000L -#define PA_DEBUG01_0__clip_ga_bc_fifo_write_MASK 0x00100000L -#define PA_DEBUG01_0__clip_to_ga_fifo_write_MASK 0x00200000L -#define PA_DEBUG01_0__vte_out_clip_fifo_fifo_advanceread_MASK 0x00400000L -#define PA_DEBUG01_0__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L -#define PA_DEBUG01_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG01_1 -#define PA_DEBUG01_1__ALWAYS_ZERO_MASK 0x000000ffL -#define PA_DEBUG01_1__clip_extra_bc_valid_MASK 0x00000700L -#define PA_DEBUG01_1__clip_vert_vte_valid_MASK 0x00003800L -#define PA_DEBUG01_1__clip_to_outsm_vertex_deallocate_MASK 0x0000c000L -#define PA_DEBUG01_1__vte_out_clip_rd_extra_bc_valid_MASK 0x00010000L -#define PA_DEBUG01_1__vte_out_clip_rd_vte_naninf_kill_MASK 0x00020000L -#define PA_DEBUG01_1__vte_out_clip_rd_vertex_store_indx_MASK 0x000c0000L -#define PA_DEBUG01_1__clip_ga_bc_fifo_write_MASK 0x00100000L -#define PA_DEBUG01_1__clip_to_ga_fifo_write_MASK 0x00200000L -#define PA_DEBUG01_1__vte_out_clip_fifo_fifo_advanceread_MASK 0x00400000L -#define PA_DEBUG01_1__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L -#define PA_DEBUG01_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG02_0 -#define PA_DEBUG02_0__clip_to_outsm_vertex_store_indx_2_MASK 0x0000000fL -#define PA_DEBUG02_0__clip_to_outsm_vertex_store_indx_1_MASK 0x000000f0L -#define PA_DEBUG02_0__clip_to_outsm_vertex_store_indx_0_MASK 0x00000f00L -#define PA_DEBUG02_0__clip_to_clipga_extra_bc_coords_MASK 0x00001000L -#define PA_DEBUG02_0__clip_to_clipga_vte_naninf_kill_MASK 0x00002000L -#define PA_DEBUG02_0__clip_to_outsm_end_of_packet_MASK 0x00004000L -#define PA_DEBUG02_0__clip_to_outsm_first_prim_of_slot_MASK 0x00008000L -#define PA_DEBUG02_0__clip_to_outsm_clipped_prim_MASK 0x00010000L -#define PA_DEBUG02_0__clip_to_outsm_null_primitive_MASK 0x00020000L -#define PA_DEBUG02_0__clip_ga_bc_fifo_full_MASK 0x00040000L -#define PA_DEBUG02_0__clip_to_ga_fifo_full_MASK 0x00080000L -#define PA_DEBUG02_0__clip_ga_bc_fifo_write_MASK 0x00100000L -#define PA_DEBUG02_0__clip_to_ga_fifo_write_MASK 0x00200000L -#define PA_DEBUG02_0__clip_to_outsm_fifo_advanceread_MASK 0x40000000L -#define PA_DEBUG02_0__clip_to_outsm_fifo_empty_MASK 0x80000000L - -// PA_DEBUG02_1 -#define PA_DEBUG02_1__clip_extra_bc_valid_MASK 0x00000007L -#define PA_DEBUG02_1__clip_vert_vte_valid_MASK 0x00000038L -#define PA_DEBUG02_1__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L -#define PA_DEBUG02_1__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L -#define PA_DEBUG02_1__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L -#define PA_DEBUG02_1__clip_to_outsm_clipped_prim_MASK 0x00010000L -#define PA_DEBUG02_1__clip_to_outsm_null_primitive_MASK 0x00020000L -#define PA_DEBUG02_1__clip_ga_bc_fifo_full_MASK 0x00040000L -#define PA_DEBUG02_1__clip_to_ga_fifo_full_MASK 0x00080000L -#define PA_DEBUG02_1__clip_ga_bc_fifo_write_MASK 0x00100000L -#define PA_DEBUG02_1__clip_to_ga_fifo_write_MASK 0x00200000L -#define PA_DEBUG02_1__clip_to_outsm_fifo_advanceread_MASK 0x00400000L -#define PA_DEBUG02_1__clip_to_outsm_fifo_empty_MASK 0x00800000L -#define PA_DEBUG02_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG03_0 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_clip_code_or_MASK 0x0000003fL -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00007000L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00008000L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG03_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG03_1 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_event_id_MASK 0x0000c000L -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG03_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG04_0 -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x00000007L -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x000001f8L -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x00007e00L -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x001f8000L -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG04_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG04_1 -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007ffL -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f800L -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x001f0000L -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG04_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG05_0 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_clip_code_or_MASK 0x0000003fL -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_event_id_MASK 0x00000fc0L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00007000L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00008000L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG05_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG05_1 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_event_id_MASK 0x0000c000L -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG05_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG06_0 -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x00000007L -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x000001f8L -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x00007e00L -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x001f8000L -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG06_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG06_1 -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007ffL -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f800L -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x001f0000L -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG06_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG07_0 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_clip_code_or_MASK 0x0000003fL -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_event_id_MASK 0x00000fc0L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00007000L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00008000L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG07_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG07_1 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_event_id_MASK 0x0000c000L -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG07_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG08_0 -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x00000007L -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x000001f8L -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x00007e00L -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x001f8000L -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG08_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG08_1 -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007ffL -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f800L -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x001f0000L -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG08_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG09_0 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_clip_code_or_MASK 0x0000003fL -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_event_id_MASK 0x00000fc0L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00007000L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00008000L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG09_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG09_1 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_event_id_MASK 0x0000c000L -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x00070000L -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x00080000L -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_end_of_packet_MASK 0x00100000L -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG09_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG10_0 -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x00000007L -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x000001f8L -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x00007e00L -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x001f8000L -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_null_primitive_MASK 0x00400000L -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG10_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG10_1 -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007ffL -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f800L -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x001f0000L -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_event_MASK 0x00200000L -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_null_primitive_MASK 0x00400000L - -// PA_DEBUG11_0 -#define PA_DEBUG11_0__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000000fL -#define PA_DEBUG11_0__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000000f0L -#define PA_DEBUG11_0__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L -#define PA_DEBUG11_0__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L -#define PA_DEBUG11_0__clipsm3_clip_to_clipga_prim_valid_MASK 0x00010000L -#define PA_DEBUG11_0__clipsm2_clip_to_clipga_prim_valid_MASK 0x00020000L -#define PA_DEBUG11_0__clipsm1_clip_to_clipga_prim_valid_MASK 0x00040000L -#define PA_DEBUG11_0__clipsm0_clip_to_clipga_prim_valid_MASK 0x00080000L -#define PA_DEBUG11_0__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00100000L -#define PA_DEBUG11_0__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00200000L -#define PA_DEBUG11_0__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00400000L -#define PA_DEBUG11_0__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00800000L -#define PA_DEBUG11_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG11_1 -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_event_MASK 0x00000001L -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_event_MASK 0x00000002L -#define PA_DEBUG11_1__clipsm1_clip_to_clipga_event_MASK 0x00000004L -#define PA_DEBUG11_1__clipsm0_clip_to_clipga_event_MASK 0x00000008L -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L -#define PA_DEBUG11_1__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L -#define PA_DEBUG11_1__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_prim_valid_MASK 0x00010000L -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_prim_valid_MASK 0x00020000L -#define PA_DEBUG11_1__clipsm1_clip_to_clipga_prim_valid_MASK 0x00040000L -#define PA_DEBUG11_1__clipsm0_clip_to_clipga_prim_valid_MASK 0x00080000L -#define PA_DEBUG11_1__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00100000L -#define PA_DEBUG11_1__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00200000L -#define PA_DEBUG11_1__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00400000L -#define PA_DEBUG11_1__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00800000L -#define PA_DEBUG11_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG12_0 -#define PA_DEBUG12_0__clip_priority_available_vte_out_clip_MASK 0x0000001fL -#define PA_DEBUG12_0__clip_priority_available_clip_verts_MASK 0x000003e0L -#define PA_DEBUG12_0__clip_priority_seq_indx_out_MASK 0x00000c00L -#define PA_DEBUG12_0__clip_priority_seq_indx_vert_MASK 0x00003000L -#define PA_DEBUG12_0__clip_priority_seq_indx_load_MASK 0x0000c000L -#define PA_DEBUG12_0__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00010000L -#define PA_DEBUG12_0__clipsm3_clprim_to_clip_prim_valid_MASK 0x00020000L -#define PA_DEBUG12_0__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00040000L -#define PA_DEBUG12_0__clipsm2_clprim_to_clip_prim_valid_MASK 0x00080000L -#define PA_DEBUG12_0__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00100000L -#define PA_DEBUG12_0__clipsm1_clprim_to_clip_prim_valid_MASK 0x00200000L -#define PA_DEBUG12_0__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00400000L -#define PA_DEBUG12_0__clipsm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG12_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG12_1 -#define PA_DEBUG12_1__ALWAYS_ZERO_MASK 0x000000ffL -#define PA_DEBUG12_1__clip_priority_available_vte_out_clip_MASK 0x00001f00L -#define PA_DEBUG12_1__clip_priority_available_clip_verts_MASK 0x0000e000L -#define PA_DEBUG12_1__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00010000L -#define PA_DEBUG12_1__clipsm3_clprim_to_clip_prim_valid_MASK 0x00020000L -#define PA_DEBUG12_1__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00040000L -#define PA_DEBUG12_1__clipsm2_clprim_to_clip_prim_valid_MASK 0x00080000L -#define PA_DEBUG12_1__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00100000L -#define PA_DEBUG12_1__clipsm1_clprim_to_clip_prim_valid_MASK 0x00200000L -#define PA_DEBUG12_1__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00400000L -#define PA_DEBUG12_1__clipsm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG12_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG13_0 -#define PA_DEBUG13_0__vertval_bits_vertex_cc_next_valid_MASK 0x0000000fL -#define PA_DEBUG13_0__clipcc_vertex_store_indx_MASK 0x00000030L -#define PA_DEBUG13_0__vte_out_orig_fifo_fifo_empty_MASK 0x00000040L -#define PA_DEBUG13_0__clipcode_fifo_fifo_empty_MASK 0x00000080L -#define PA_DEBUG13_0__ccgen_to_clipcc_fifo_empty_MASK 0x00000100L -#define PA_DEBUG13_0__clip_priority_seq_indx_out_cnt_MASK 0x00001e00L -#define PA_DEBUG13_0__outsm_clr_rd_orig_vertices_MASK 0x00006000L -#define PA_DEBUG13_0__outsm_clr_rd_clipsm_wait_MASK 0x00008000L -#define PA_DEBUG13_0__outsm_clr_fifo_contents_MASK 0x001f0000L -#define PA_DEBUG13_0__outsm_clr_fifo_full_MASK 0x00200000L -#define PA_DEBUG13_0__outsm_clr_fifo_advanceread_MASK 0x00400000L -#define PA_DEBUG13_0__outsm_clr_fifo_write_MASK 0x00800000L -#define PA_DEBUG13_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG13_1 -#define PA_DEBUG13_1__clprim_in_back_state_var_indx_MASK 0x00000007L -#define PA_DEBUG13_1__point_clip_candidate_MASK 0x00000008L -#define PA_DEBUG13_1__prim_nan_kill_MASK 0x00000010L -#define PA_DEBUG13_1__clprim_clip_primitive_MASK 0x00000020L -#define PA_DEBUG13_1__clprim_cull_primitive_MASK 0x00000040L -#define PA_DEBUG13_1__prim_back_valid_MASK 0x00000080L -#define PA_DEBUG13_1__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L -#define PA_DEBUG13_1__clipcc_vertex_store_indx_MASK 0x00003000L -#define PA_DEBUG13_1__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L -#define PA_DEBUG13_1__clipcode_fifo_fifo_empty_MASK 0x00008000L -#define PA_DEBUG13_1__outsm_clr_fifo_contents_MASK 0x001f0000L -#define PA_DEBUG13_1__outsm_clr_fifo_full_MASK 0x00200000L -#define PA_DEBUG13_1__outsm_clr_fifo_advanceread_MASK 0x00400000L -#define PA_DEBUG13_1__outsm_clr_fifo_write_MASK 0x00800000L -#define PA_DEBUG13_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG14_0 -#define PA_DEBUG14_0__clprim_in_back_vertex_store_indx_1_MASK 0x0000000fL -#define PA_DEBUG14_0__clprim_in_back_vertex_store_indx_0_MASK 0x000003f0L -#define PA_DEBUG14_0__outputclprimtoclip_null_primitive_MASK 0x00000400L -#define PA_DEBUG14_0__clprim_in_back_end_of_packet_MASK 0x00000800L -#define PA_DEBUG14_0__clprim_in_back_first_prim_of_slot_MASK 0x00001000L -#define PA_DEBUG14_0__clprim_in_back_deallocate_slot_MASK 0x0000e000L -#define PA_DEBUG14_0__clprim_in_back_event_id_MASK 0x003f0000L -#define PA_DEBUG14_0__clprim_in_back_event_MASK 0x00400000L -#define PA_DEBUG14_0__prim_back_valid_MASK 0x00800000L -#define PA_DEBUG14_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG14_1 -#define PA_DEBUG14_1__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL -#define PA_DEBUG14_1__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L -#define PA_DEBUG14_1__clprim_in_back_vertex_store_indx_0_MASK 0x0000f000L -#define PA_DEBUG14_1__clprim_in_back_event_id_MASK 0x003f0000L -#define PA_DEBUG14_1__clprim_in_back_event_MASK 0x00400000L -#define PA_DEBUG14_1__prim_back_valid_MASK 0x00800000L -#define PA_DEBUG14_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG15_0 -#define PA_DEBUG15_0__vertval_bits_vertex_vertex_store_msb_MASK 0x000000ffL -#define PA_DEBUG15_0__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x00001f00L -#define PA_DEBUG15_0__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x0003e000L -#define PA_DEBUG15_0__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x007c0000L -#define PA_DEBUG15_0__primic_to_clprim_valid_MASK 0x00800000L -#define PA_DEBUG15_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG15_1 -#define PA_DEBUG15_1__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL -#define PA_DEBUG15_1__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x00030000L -#define PA_DEBUG15_1__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x007c0000L -#define PA_DEBUG15_1__primic_to_clprim_valid_MASK 0x00800000L -#define PA_DEBUG15_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG16_0 -#define PA_DEBUG16_0__sm0_clip_vert_cnt_MASK 0x0000001fL -#define PA_DEBUG16_0__sm0_vertex_clip_cnt_MASK 0x000003e0L -#define PA_DEBUG16_0__sm0_inv_to_clip_data_valid_1_MASK 0x00000400L -#define PA_DEBUG16_0__sm0_inv_to_clip_data_valid_0_MASK 0x00000800L -#define PA_DEBUG16_0__sm0_current_state_MASK 0x0007f000L -#define PA_DEBUG16_0__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG16_0__sm0_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG16_0__sm0_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG16_0__sm0_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG16_0__sm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG16_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG16_1 -#define PA_DEBUG16_1__sm0_prim_end_state_MASK 0x0000007fL -#define PA_DEBUG16_1__sm0_ps_expand_MASK 0x00000080L -#define PA_DEBUG16_1__sm0_clip_vert_cnt_MASK 0x00001f00L -#define PA_DEBUG16_1__sm0_vertex_clip_cnt_MASK 0x0000e000L -#define PA_DEBUG16_1__sm0_current_state_MASK 0x00070000L -#define PA_DEBUG16_1__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG16_1__sm0_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG16_1__sm0_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG16_1__sm0_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG16_1__sm0_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG16_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG17_0 -#define PA_DEBUG17_0__sm1_clip_vert_cnt_MASK 0x0000001fL -#define PA_DEBUG17_0__sm1_vertex_clip_cnt_MASK 0x000003e0L -#define PA_DEBUG17_0__sm1_inv_to_clip_data_valid_1_MASK 0x00000400L -#define PA_DEBUG17_0__sm1_inv_to_clip_data_valid_0_MASK 0x00000800L -#define PA_DEBUG17_0__sm1_current_state_MASK 0x0007f000L -#define PA_DEBUG17_0__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG17_0__sm1_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG17_0__sm1_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG17_0__sm1_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG17_0__sm1_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG17_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG17_1 -#define PA_DEBUG17_1__sm1_prim_end_state_MASK 0x0000007fL -#define PA_DEBUG17_1__sm1_ps_expand_MASK 0x00000080L -#define PA_DEBUG17_1__sm1_clip_vert_cnt_MASK 0x00001f00L -#define PA_DEBUG17_1__sm1_vertex_clip_cnt_MASK 0x0000e000L -#define PA_DEBUG17_1__sm1_current_state_MASK 0x00070000L -#define PA_DEBUG17_1__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG17_1__sm1_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG17_1__sm1_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG17_1__sm1_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG17_1__sm1_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG17_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG18_0 -#define PA_DEBUG18_0__sm2_clip_vert_cnt_MASK 0x0000001fL -#define PA_DEBUG18_0__sm2_vertex_clip_cnt_MASK 0x000003e0L -#define PA_DEBUG18_0__sm2_inv_to_clip_data_valid_1_MASK 0x00000400L -#define PA_DEBUG18_0__sm2_inv_to_clip_data_valid_0_MASK 0x00000800L -#define PA_DEBUG18_0__sm2_current_state_MASK 0x0007f000L -#define PA_DEBUG18_0__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG18_0__sm2_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG18_0__sm2_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG18_0__sm2_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG18_0__sm2_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG18_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG18_1 -#define PA_DEBUG18_1__sm2_prim_end_state_MASK 0x0000007fL -#define PA_DEBUG18_1__sm2_ps_expand_MASK 0x00000080L -#define PA_DEBUG18_1__sm2_clip_vert_cnt_MASK 0x00001f00L -#define PA_DEBUG18_1__sm2_vertex_clip_cnt_MASK 0x0000e000L -#define PA_DEBUG18_1__sm2_current_state_MASK 0x00070000L -#define PA_DEBUG18_1__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG18_1__sm2_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG18_1__sm2_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG18_1__sm2_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG18_1__sm2_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG18_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG19_0 -#define PA_DEBUG19_0__sm3_clip_vert_cnt_MASK 0x0000001fL -#define PA_DEBUG19_0__sm3_vertex_clip_cnt_MASK 0x000003e0L -#define PA_DEBUG19_0__sm3_inv_to_clip_data_valid_1_MASK 0x00000400L -#define PA_DEBUG19_0__sm3_inv_to_clip_data_valid_0_MASK 0x00000800L -#define PA_DEBUG19_0__sm3_current_state_MASK 0x0007f000L -#define PA_DEBUG19_0__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG19_0__sm3_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG19_0__sm3_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG19_0__sm3_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG19_0__sm3_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG19_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG19_1 -#define PA_DEBUG19_1__sm3_prim_end_state_MASK 0x0000007fL -#define PA_DEBUG19_1__sm3_ps_expand_MASK 0x00000080L -#define PA_DEBUG19_1__sm3_clip_vert_cnt_MASK 0x00001f00L -#define PA_DEBUG19_1__sm3_vertex_clip_cnt_MASK 0x0000e000L -#define PA_DEBUG19_1__sm3_current_state_MASK 0x00070000L -#define PA_DEBUG19_1__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x00080000L -#define PA_DEBUG19_1__sm3_clip_to_outsm_fifo_full_MASK 0x00100000L -#define PA_DEBUG19_1__sm3_highest_priority_seq_MASK 0x00200000L -#define PA_DEBUG19_1__sm3_outputcliptoga_0_MASK 0x00400000L -#define PA_DEBUG19_1__sm3_clprim_to_clip_prim_valid_MASK 0x00800000L -#define PA_DEBUG19_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG20_0 -#define PA_DEBUG20_0__point_address_MASK 0x00000001L -#define PA_DEBUG20_0__sx_pending_rd_state_var_indx_MASK 0x0000000eL -#define PA_DEBUG20_0__sx_pending_rd_req_mask_MASK 0x000000f0L -#define PA_DEBUG20_0__sx_pending_rd_pci_MASK 0x0003ff00L -#define PA_DEBUG20_0__sx_pending_rd_aux_sel_MASK 0x000c0000L -#define PA_DEBUG20_0__sx_pending_rd_sp_id_MASK 0x00300000L -#define PA_DEBUG20_0__sx_pending_rd_aux_inc_MASK 0x00400000L -#define PA_DEBUG20_0__sx_pending_rd_advance_MASK 0x00800000L -#define PA_DEBUG20_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG20_1 -#define PA_DEBUG20_1__position_address_MASK 0x0000003fL -#define PA_DEBUG20_1__point_address_MASK 0x000001c0L -#define PA_DEBUG20_1__sx_pending_rd_state_var_indx_MASK 0x00000e00L -#define PA_DEBUG20_1__sx_pending_rd_req_mask_MASK 0x0000f000L -#define PA_DEBUG20_1__sx_pending_rd_pci_MASK 0x00030000L -#define PA_DEBUG20_1__sx_pending_rd_aux_sel_MASK 0x000c0000L -#define PA_DEBUG20_1__sx_pending_rd_sp_id_MASK 0x00300000L -#define PA_DEBUG20_1__sx_pending_rd_aux_inc_MASK 0x00400000L -#define PA_DEBUG20_1__sx_pending_rd_advance_MASK 0x00800000L -#define PA_DEBUG20_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG21_0 -#define PA_DEBUG21_0__sx_receive_indx_MASK 0x00000003L -#define PA_DEBUG21_0__sx_pending_fifo_contents_MASK 0x0000007cL -#define PA_DEBUG21_0__statevar_bits_vs_out_misc_vec_ena_MASK 0x00000080L -#define PA_DEBUG21_0__statevar_bits_disable_sp_MASK 0x00000f00L -#define PA_DEBUG21_0__aux_sel_MASK 0x00003000L -#define PA_DEBUG21_0__sx_to_pa_empty_1_MASK 0x00004000L -#define PA_DEBUG21_0__sx_to_pa_empty_0_MASK 0x00008000L -#define PA_DEBUG21_0__pasx_req_cnt_1_MASK 0x000f0000L -#define PA_DEBUG21_0__pasx_req_cnt_0_MASK 0x00f00000L -#define PA_DEBUG21_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG21_1 -#define PA_DEBUG21_1__available_positions_MASK 0x0000007fL -#define PA_DEBUG21_1__sx_receive_indx_MASK 0x00000380L -#define PA_DEBUG21_1__sx_pending_fifo_contents_MASK 0x00007c00L -#define PA_DEBUG21_1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L -#define PA_DEBUG21_1__pasx_req_cnt_1_MASK 0x000f0000L -#define PA_DEBUG21_1__pasx_req_cnt_0_MASK 0x00f00000L -#define PA_DEBUG21_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG22_0 -#define PA_DEBUG22_0__su_aux_MASK 0x00000001L -#define PA_DEBUG22_0__sx_request_indx_MASK 0x0000007eL -#define PA_DEBUG22_0__req_active_verts_loaded_MASK 0x00000080L -#define PA_DEBUG22_0__req_active_verts_MASK 0x00007f00L -#define PA_DEBUG22_0__vgt_to_ccgen_state_var_indx_MASK 0x00038000L -#define PA_DEBUG22_0__vgt_to_ccgen_active_verts_MASK 0x00fc0000L -#define PA_DEBUG22_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG22_1 -#define PA_DEBUG22_1__param_cache_base_MASK 0x0000007fL -#define PA_DEBUG22_1__su_aux_MASK 0x00000180L -#define PA_DEBUG22_1__sx_request_indx_MASK 0x00007e00L -#define PA_DEBUG22_1__req_active_verts_loaded_MASK 0x00008000L -#define PA_DEBUG22_1__vgt_to_ccgen_state_var_indx_MASK 0x00030000L -#define PA_DEBUG22_1__vgt_to_ccgen_active_verts_MASK 0x00fc0000L -#define PA_DEBUG22_1__Reserved0_MASK 0xff000000L - -// PA_DEBUG23_0 -#define PA_DEBUG23_0__su_baryc_cntl_state_MASK 0x00000003L -#define PA_DEBUG23_0__su_cntl_state_MASK 0x0000003cL -#define PA_DEBUG23_0__ALWAYS_ZERO_MASK 0x000000c0L -#define PA_DEBUG23_0__pmode_state_MASK 0x00003f00L -#define PA_DEBUG23_0__ge_stallb_MASK 0x00004000L -#define PA_DEBUG23_0__geom_enable_MASK 0x00008000L -#define PA_DEBUG23_0__su_clip_baryc_free_MASK 0x00030000L -#define PA_DEBUG23_0__su_clip_rtr_MASK 0x00040000L -#define PA_DEBUG23_0__pfifo_busy_MASK 0x00080000L -#define PA_DEBUG23_0__su_cntl_busy_MASK 0x00100000L -#define PA_DEBUG23_0__geom_busy_MASK 0x00200000L -#define PA_DEBUG23_0__event_id_gated_1to0_MASK 0x00c00000L -#define PA_DEBUG23_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG24_0 -#define PA_DEBUG24_0__event_id_gated_5to2_MASK 0x0000000fL -#define PA_DEBUG24_0__event_gated_MASK 0x00000010L -#define PA_DEBUG24_0__pmode_prim_gated_MASK 0x00000020L -#define PA_DEBUG24_0__su_dyn_sclk_vld_MASK 0x00000040L -#define PA_DEBUG24_0__cl_dyn_sclk_vld_MASK 0x00000080L -#define PA_DEBUG24_0__y_sort0_gated_23_8_MASK 0x00ffff00L -#define PA_DEBUG24_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG25_0 -#define PA_DEBUG25_0__x_sort0_gated_23_8_MASK 0x0000ffffL -#define PA_DEBUG25_0__y_sort1_gated_15_8_MASK 0x00ff0000L -#define PA_DEBUG25_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG26_0 -#define PA_DEBUG26_0__y_sort1_gated_23_16_MASK 0x000000ffL -#define PA_DEBUG26_0__x_sort1_gated_23_8_MASK 0x00ffff00L -#define PA_DEBUG26_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG27_0 -#define PA_DEBUG27_0__y_sort2_gated_23_8_MASK 0x0000ffffL -#define PA_DEBUG27_0__x_sort2_gated_15_8_MASK 0x00ff0000L -#define PA_DEBUG27_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG28_0 -#define PA_DEBUG28_0__x_sort2_gated_23to16_MASK 0x000000ffL -#define PA_DEBUG28_0__attr_indx_sort0_gated_MASK 0x003fff00L -#define PA_DEBUG28_0__null_prim_gated_MASK 0x00400000L -#define PA_DEBUG28_0__backfacing_gated_MASK 0x00800000L -#define PA_DEBUG28_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG29_0 -#define PA_DEBUG29_0__st_indx_gated_MASK 0x00000007L -#define PA_DEBUG29_0__clipped_gated_MASK 0x00000008L -#define PA_DEBUG29_0__dealloc_slot_gated_MASK 0x00000070L -#define PA_DEBUG29_0__xmajor_gated_MASK 0x00000080L -#define PA_DEBUG29_0__diamond_rule_gated_MASK 0x00000300L -#define PA_DEBUG29_0__type_gated_MASK 0x00001c00L -#define PA_DEBUG29_0__fpov_gated_MASK 0x00006000L -#define PA_DEBUG29_0__eop_gated_MASK 0x00008000L -#define PA_DEBUG29_0__attr_indx_sort2_gated_7to0_MASK 0x00ff0000L -#define PA_DEBUG29_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG30_0 -#define PA_DEBUG30_0__attr_indx_sort2_gated_13to8_MASK 0x0000003fL -#define PA_DEBUG30_0__attr_indx_sort1_gated_MASK 0x000fffc0L -#define PA_DEBUG30_0__provoking_vtx_gated_MASK 0x00300000L -#define PA_DEBUG30_0__valid_prim_gated_MASK 0x00400000L -#define PA_DEBUG30_0__pa_reg_sclk_vld_MASK 0x00800000L -#define PA_DEBUG30_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG31_0 -#define PA_DEBUG31_0__VGT_PA_clipv_send_q_MASK 0x00000001L -#define PA_DEBUG31_0__VGT_PA_clips_send_q_MASK 0x00000002L -#define PA_DEBUG31_0__VGT_PA_clipp_send_q_MASK 0x00000004L -#define PA_DEBUG31_0__PA0_SC0_send_q_MASK 0x00000008L -#define PA_DEBUG31_0__PA0_SC1_send_q_MASK 0x00000010L -#define PA_DEBUG31_0__PA_PA_pascDataOut_send0_q_MASK 0x00000020L -#define PA_DEBUG31_0__PA_PA_pascDataOut_send1_q_MASK 0x00000040L -#define PA_DEBUG31_0__vte_busy_MASK 0x00000080L -#define PA_DEBUG31_0__clipper_busy_MASK 0x00000100L -#define PA_DEBUG31_0__su_busy_MASK 0x00000200L -#define PA_DEBUG31_0__su_busy_debug_hold_busy_MASK 0x00000400L -#define PA_DEBUG31_0__su_busy_debug_valid_prim_gated_MASK 0x00000800L -#define PA_DEBUG31_0__su_busy_debug_su_cntl_busy_MASK 0x00001000L -#define PA_DEBUG31_0__su_busy_debug_geom_busy_MASK 0x00002000L -#define PA_DEBUG31_0__su_busy_debug_pfifo_busy_MASK 0x00004000L -#define PA_DEBUG31_0__vte_busy_debug_veu_busy_MASK 0x00008000L -#define PA_DEBUG31_0__vte_busy_debug_ib_busy_MASK 0x00010000L -#define PA_DEBUG31_0__clipper_busy_debug_outsm_clr_fifo_not_empty_MASK 0x00020000L -#define PA_DEBUG31_0__clipper_busy_debug_clipsm3_clprim_to_clip_prim_valid_MASK 0x00040000L -#define PA_DEBUG31_0__clipper_busy_debug_clipsm2_clprim_to_clip_prim_valid_MASK 0x00080000L -#define PA_DEBUG31_0__clipper_busy_debug_clipsm1_clprim_to_clip_prim_valid_MASK 0x00100000L -#define PA_DEBUG31_0__clipper_busy_debug_clipsm0_clprim_to_clip_prim_valid_MASK 0x00200000L -#define PA_DEBUG31_0__clipper_busy_debug_primic_to_clprim_valid_MASK 0x00400000L -#define PA_DEBUG31_0__clipper_busy_debug_clipsm_clip_to_outsm_fifo_write_MASK 0x00800000L -#define PA_DEBUG31_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG32_0 -#define PA_DEBUG32_0__clipper_busy_debug_clipsm3_current_state_not_empty_MASK 0x00000001L -#define PA_DEBUG32_0__clipper_busy_debug_clipsm2_current_state_not_empty_MASK 0x00000002L -#define PA_DEBUG32_0__clipper_busy_debug_clipsm1_current_state_not_empty_MASK 0x00000004L -#define PA_DEBUG32_0__clipper_busy_debug_clipsm0_current_state_not_empty_MASK 0x00000008L -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_ga_bc_busy_MASK 0x00000010L -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_ga_fifo_write_MASK 0x00000020L -#define PA_DEBUG32_0__clipper_busy_debug_prim_back_valid_MASK 0x00000040L -#define PA_DEBUG32_0__clipper_busy_debug_next_prim_back_valid_MASK 0x00000080L -#define PA_DEBUG32_0__clipper_busy_debug_primic_to_clprim_fifo_not_empty_MASK 0x00000100L -#define PA_DEBUG32_0__clipper_busy_debug_primic_to_clprim_fifo_write_MASK 0x00000200L -#define PA_DEBUG32_0__clipper_busy_debug_sx_pending_fifo_not_empty_MASK 0x00000400L -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_outsm_fifo_busy_MASK 0x00000800L -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_outsm_fifo_write_MASK 0x00001000L -#define PA_DEBUG32_0__clipper_busy_debug_clipcode_fifo_fifo_busy_MASK 0x00002000L -#define PA_DEBUG32_0__clipper_busy_debug_clipcode_fifo_fifo_write_MASK 0x00004000L -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_clip_fifo_fifo_busy_MASK 0x00008000L -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_clip_fifo_fifo_write_MASK 0x00010000L -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_orig_fifo_fifo_busy_MASK 0x00020000L -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_orig_fifo_fifo_write_MASK 0x00040000L -#define PA_DEBUG32_0__clipper_busy_debug_ccgen_to_clipcc_fifo_busy_MASK 0x00080000L -#define PA_DEBUG32_0__clipper_busy_debug_ccgen_to_clipcc_fifo_write_MASK 0x00100000L -#define PA_DEBUG32_0__clipper_busy_debug_vgt_to_clipp_fifo_busy_MASK 0x00200000L -#define PA_DEBUG32_0__clipper_busy_debug_vgt_to_clipp_fifo_write_MASK 0x00400000L -#define PA_DEBUG32_0__clipper_busy_debug_vgt_to_clips_fifo_busy_MASK 0x00800000L -#define PA_DEBUG32_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG33_0 -#define PA_DEBUG33_0__clipper_busy_debug_vgt_to_clips_fifo_write_MASK 0x00000001L -#define PA_DEBUG33_0__PA_SE3SC_freeze_MASK 0x00000010L -#define PA_DEBUG33_0__Reserved0_MASK 0xffffffe0L - -// PA_DEBUG34_0 -#define PA_DEBUG34_0__ngg_sideband_utc_driver_tag_MASK 0x000000ffL -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rtr_out_MASK 0x00000100L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rts_out_MASK 0x00000200L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rts_in_MASK 0x00000400L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rtr_in_MASK 0x00000800L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_busy_MASK 0x00001000L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_outcl1_send_valid_MASK 0x00002000L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_iutcl1_send_ready_MASK 0x00004000L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_iclient_send_valid_MASK 0x00008000L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_oclient_send_ready_MASK 0x00010000L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_outcl1_send_vmid_MASK 0x001e0000L -#define PA_DEBUG34_0__ngg_sideband_utc_driver_outcl1_send_type_MASK 0x00600000L -#define PA_DEBUG34_0__Reserved0_MASK 0xff800000L - -// PA_DEBUG34_1 -#define PA_DEBUG34_1__ngg_utcl1_debug00_MASK 0xffffffffL - -// PA_DEBUG35_0 -#define PA_DEBUG35_0__ngg_index_utc_driver_tag_MASK 0x000000ffL -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_read_MASK 0x00000100L -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_empty_MASK 0x00000200L -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_write_MASK 0x00000400L -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_full_MASK 0x00000800L -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_busy_MASK 0x00001000L -#define PA_DEBUG35_0__ngg_index_utc_driver_outcl1_send_valid_MASK 0x00002000L -#define PA_DEBUG35_0__ngg_index_utc_driver_iutcl1_send_ready_MASK 0x00004000L -#define PA_DEBUG35_0__ngg_index_utc_driver_iclient_send_valid_MASK 0x00008000L -#define PA_DEBUG35_0__ngg_index_utc_driver_oclient_send_ready_MASK 0x00010000L -#define PA_DEBUG35_0__ngg_index_utc_driver_outcl1_send_vmid_MASK 0x001e0000L -#define PA_DEBUG35_0__ngg_index_utc_driver_outcl1_send_type_MASK 0x00600000L -#define PA_DEBUG35_0__Reserved0_MASK 0xff800000L - -// PA_DEBUG35_1 -#define PA_DEBUG35_1__ngg_utcl1_debug01_MASK 0xffffffffL - -// PA_DEBUG36_0 -#define PA_DEBUG36_0__ngg_position_utc_driver_tag_MASK 0x000000ffL -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_read_MASK 0x00000100L -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_empty_MASK 0x00000200L -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_write_MASK 0x00000400L -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_full_MASK 0x00000800L -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_busy_MASK 0x00001000L -#define PA_DEBUG36_0__ngg_position_utc_driver_outcl1_send_valid_MASK 0x00002000L -#define PA_DEBUG36_0__ngg_position_utc_driver_iutcl1_send_ready_MASK 0x00004000L -#define PA_DEBUG36_0__ngg_position_utc_driver_iclient_send_valid_MASK 0x00008000L -#define PA_DEBUG36_0__ngg_position_utc_driver_oclient_send_ready_MASK 0x00010000L -#define PA_DEBUG36_0__ngg_position_utc_driver_outcl1_send_vmid_MASK 0x001e0000L -#define PA_DEBUG36_0__ngg_position_utc_driver_outcl1_send_type_MASK 0x00600000L -#define PA_DEBUG36_0__Reserved0_MASK 0xff800000L - -// PA_DEBUG36_1 -#define PA_DEBUG36_1__ngg_utcl1_debug02_MASK 0xffffffffL - -// PA_DEBUG37_0 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_busy_MASK 0x00000001L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rtr_out_MASK 0x00000002L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rts_out_MASK 0x00000004L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rtr_in_MASK 0x00000008L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rts_in_MASK 0x00000010L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_drop_MASK 0x00000020L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_perf_cntr_en_MASK \ - 0x00000040L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_space_MASK 0x00000080L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_rd_tmz_encr_MASK \ - 0x00000100L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_io_MASK 0x00000200L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_snoop_MASK 0x00000400L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_mtype_MASK 0x00003800L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_vmid_MASK 0x0003c000L -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_tag_MASK 0x03fc0000L -#define PA_DEBUG37_0__Reserved0_MASK 0xfc000000L - -// PA_DEBUG37_1 -#define PA_DEBUG37_1__ngg_utcl1_debug03_MASK 0xffffffffL - -// PA_DEBUG38_0 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_busy_MASK 0x00000001L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rtr_out_MASK 0x00000002L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rts_out_MASK 0x00000004L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rtr_in_MASK 0x00000008L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rts_in_MASK 0x00000010L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_drop_MASK 0x00000020L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_perf_cntr_en_MASK 0x00000040L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_space_MASK 0x00000080L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_rd_tmz_encr_MASK 0x00000100L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_io_MASK 0x00000200L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_snoop_MASK 0x00000400L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_mtype_MASK 0x00003800L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_vmid_MASK 0x0003c000L -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_tag_MASK 0x03fc0000L -#define PA_DEBUG38_0__Reserved0_MASK 0xfc000000L - -// PA_DEBUG38_1 -#define PA_DEBUG38_1__ngg_utcl1_debug04_MASK 0xffffffffL - -// PA_DEBUG39_0 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_busy_MASK 0x00000001L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rtr_out_MASK 0x00000002L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rts_out_MASK 0x00000004L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rtr_in_MASK 0x00000008L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rts_in_MASK 0x00000010L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_drop_MASK 0x00000020L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_perf_cntr_en_MASK \ - 0x00000040L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_space_MASK 0x00000080L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_rd_tmz_encr_MASK \ - 0x00000100L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_io_MASK 0x00000200L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_snoop_MASK 0x00000400L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_mtype_MASK 0x00003800L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_vmid_MASK 0x0003c000L -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_tag_MASK 0x03fc0000L -#define PA_DEBUG39_0__Reserved0_MASK 0xfc000000L - -// PA_DEBUG39_1 -#define PA_DEBUG39_1__ngg_utcl1_debug05_MASK 0xffffffffL - -// PA_DEBUG40_0 -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_current_client_count_MASK 0x00000003L -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_istream0_client_tag_MASK 0x3fc00000L -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_ostream0_client_rtr_MASK 0x40000000L -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_istream0_client_rts_MASK 0x80000000L - -// PA_DEBUG40_1 -#define PA_DEBUG40_1__ngg_utcl1_debug06_MASK 0xffffffffL - -// PA_DEBUG41_0 -#define PA_DEBUG41_0__ngg_debug_tc_if_credit_count_overflow_MASK 0x00000001L -#define PA_DEBUG41_0__ngg_debug_tc_if_credit_count_underflow_MASK 0x00000002L -#define PA_DEBUG41_0__ngg_debug_tc_if_credits_MASK 0x0000007cL -#define PA_DEBUG41_0__ngg_debug_tc_if_obusy_MASK 0x00000080L -#define PA_DEBUG41_0__ngg_debug_tc_if_ooutstanding_tc_requests_exist_MASK 0x00000100L -#define PA_DEBUG41_0__ngg_debug_tc_if_irdret_vld_MASK 0x00000200L -#define PA_DEBUG41_0__ngg_debug_tc_if_irdreq_free_MASK 0x00000400L -#define PA_DEBUG41_0__ngg_debug_tc_if_ordreq_send_MASK 0x00000800L -#define PA_DEBUG41_0__ngg_debug_tc_if_ordreq_clken_MASK 0x00001000L -#define PA_DEBUG41_0__ngg_debug_tc_if_ortr_in_MASK 0x00002000L -#define PA_DEBUG41_0__ngg_debug_tc_if_irts_in_MASK 0x00004000L -#define PA_DEBUG41_0__ngg_debug_tc_if_reg_valid1_MASK 0x00008000L -#define PA_DEBUG41_0__ngg_debug_tc_if_reg_valid0_MASK 0x00010000L -#define PA_DEBUG41_0__ngg_debug_tc_if_data_rd_ptr_MASK 0x00020000L -#define PA_DEBUG41_0__ngg_debug_tc_if_data_wr_ptr_MASK 0x00040000L -#define PA_DEBUG41_0__ngg_debug_tc_if_outstanding_tc_requests_MASK 0x1ff80000L -#define PA_DEBUG41_0__Reserved0_MASK 0xe0000000L - -// PA_DEBUG41_1 -#define PA_DEBUG41_1__ngg_utcl1_debug07_MASK 0xffffffffL - -// PA_DEBUG42_0 -#define PA_DEBUG42_0__ngg_debug_sideband_sideband_tokens_not_max_value_MASK 0x00000001L -#define PA_DEBUG42_0__ngg_debug_sideband_pending_subgroup_count_not_zero_MASK 0x00000002L -#define PA_DEBUG42_0__ngg_debug_sideband_wait_counter_busy_MASK 0x00000004L -#define PA_DEBUG42_0__ngg_debug_sideband_current_state_MASK 0x00000038L -#define PA_DEBUG42_0__ngg_debug_sideband_sideband_tokens_underflow_MASK 0x00000040L -#define PA_DEBUG42_0__ngg_debug_sideband_sideband_tokens_overflow_MASK 0x00000080L -#define PA_DEBUG42_0__ngg_debug_sideband_current_dword_pointer_MASK 0x00000f00L -#define PA_DEBUG42_0__ngg_debug_sideband_pending_subgroup_count_range_MASK 0x0001f000L -#define PA_DEBUG42_0__ngg_debug_sideband_valid_dword_count_MASK 0x003e0000L -#define PA_DEBUG42_0__ngg_debug_sideband_itc_return_empty_MASK 0x00400000L -#define PA_DEBUG42_0__ngg_debug_sideband_current_sideband_is_object_id_MASK 0x00800000L -#define PA_DEBUG42_0__ngg_debug_sideband_current_sideband_event_bit_set_MASK 0x01000000L -#define PA_DEBUG42_0__ngg_debug_sideband_have_available_sideband_tokens_MASK 0x02000000L -#define PA_DEBUG42_0__Reserved0_MASK 0xfc000000L - -// PA_DEBUG42_1 -#define PA_DEBUG42_1__ngg_utcl1_debug08_MASK 0xffffffffL - -// PA_DEBUG43_0 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_ovmid_MASK 0x0000000fL -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_vmid_fifo_busy_MASK 0x00000010L -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_vmid_fifo_empty_MASK 0x00000020L -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_vmid_fifo_full_MASK 0x00000040L -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_sideband_pop_bit_fifo_empty_MASK 0x00000080L -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_sideband_pop_bit_fifo_busy_MASK 0x00000100L -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_sideband_pop_bit_fifo_full_MASK 0x00000200L -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_current_state_MASK 0x00000400L -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_osideband_active_MASK 0x00000800L -#define PA_DEBUG43_0__Reserved0_MASK 0xfffff000L - -// PA_DEBUG43_1 -#define PA_DEBUG43_1__ngg_utcl1_debug09_MASK 0xffffffffL - -// PA_DEBUG44_0 -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents1_underflow_MASK 0x00000001L -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents1_overflow_MASK 0x00000002L -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents0_underflow_MASK 0x00000004L -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents0_overflow_MASK 0x00000008L -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents0_MASK 0x00000ff0L -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents1_MASK 0x000ff000L -#define PA_DEBUG44_0__Reserved0_MASK 0xfff00000L - -// PA_DEBUG44_1 -#define PA_DEBUG44_1__ngg_utcl1_debug10_MASK 0xffffffffL - -// PA_DEBUG45_0 -#define PA_DEBUG45_0__ngg_debug_index_index_tokens_underflow_MASK 0x00000001L -#define PA_DEBUG45_0__ngg_debug_index_index_tokens_overflow_MASK 0x00000002L -#define PA_DEBUG45_0__ngg_debug_index_index_tokens_MASK 0x000000fcL -#define PA_DEBUG45_0__ngg_debug_index_prim_indices_fifo_busy_MASK 0x00000100L -#define PA_DEBUG45_0__ngg_debug_index_index_receive_fifo_busy_MASK 0x00000200L -#define PA_DEBUG45_0__ngg_debug_index_current_receive_state_MASK 0x00000400L -#define PA_DEBUG45_0__ngg_debug_index_current_fetch_state_MASK 0x00000800L -#define PA_DEBUG45_0__ngg_debug_index_sideband_data_context_id_bits_MASK 0x00007000L -#define PA_DEBUG45_0__ngg_debug_index_sideband_data_eop_bit_MASK 0x00008000L -#define PA_DEBUG45_0__ngg_debug_index_sideband_data_event_bit_MASK 0x00010000L -#define PA_DEBUG45_0__ngg_debug_index_final_receive_dword_of_subgroup_MASK 0x00020000L -#define PA_DEBUG45_0__ngg_debug_index_final_receive_cacheline_this_subgroup_MASK 0x00040000L -#define PA_DEBUG45_0__ngg_debug_index_current_receive_first_dword_pointer_MASK 0x00780000L -#define PA_DEBUG45_0__ngg_debug_index_current_receive_finalt_dword_pointer_MASK 0x07800000L -#define PA_DEBUG45_0__ngg_debug_index_index_receive_fifo_empty_MASK 0x08000000L -#define PA_DEBUG45_0__ngg_debug_index_index_receive_fifo_full_MASK 0x10000000L -#define PA_DEBUG45_0__ngg_debug_index_have_available_index_tokens_MASK 0x20000000L -#define PA_DEBUG45_0__Reserved0_MASK 0xc0000000L - -// PA_DEBUG45_1 -#define PA_DEBUG45_1__ngg_utcl1_debug11_MASK 0xffffffffL - -// PA_DEBUG46_0 -#define PA_DEBUG46_0__ngg_debug_position_request_position_tokens_underflow_MASK 0x00000001L -#define PA_DEBUG46_0__ngg_debug_position_request_position_tokens_overflow_MASK 0x00000002L -#define PA_DEBUG46_0__ngg_debug_position_request_have_available_position_tokens_MASK 0x00000004L -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_busy_MASK 0x00000008L -#define PA_DEBUG46_0__ngg_debug_position_request_prev_select_end_cacheline_address_MASK 0x00000010L -#define PA_DEBUG46_0__ngg_debug_position_request_prev_pos_cacheline_valid_MASK 0x00000020L -#define PA_DEBUG46_0__ngg_debug_position_request_active_pos_req_fosg_MASK 0x00000040L -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_miss_count_MASK 0x00000180L -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_final_prim_MASK 0x00000200L -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_first_prim_MASK 0x00000400L -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_null_prim_MASK 0x00000800L -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_prim_valid_MASK 0x00001000L -#define PA_DEBUG46_0__ngg_debug_position_request_packer_object_id_valid_MASK 0x00002000L -#define PA_DEBUG46_0__ngg_debug_position_request_packer_sideband_valid_MASK 0x00004000L -#define PA_DEBUG46_0__ngg_debug_position_request_current_state_MASK 0x00018000L -#define PA_DEBUG46_0__ngg_debug_position_request_ipa_to_wd_dealloc_index_full_MASK 0x00020000L -#define PA_DEBUG46_0__ngg_debug_position_request_iposreq_to_posrtn_s_fifo_full_MASK 0x00040000L -#define PA_DEBUG46_0__ngg_debug_position_request_iposreq_to_posrtn_v_fifo_full_MASK 0x00080000L -#define PA_DEBUG46_0__ngg_debug_position_request_ifetch_to_primic_s_fifo_full_MASK 0x00100000L -#define PA_DEBUG46_0__ngg_debug_position_request_ifetch_to_primic_p_fifo_full_MASK 0x00200000L -#define PA_DEBUG46_0__ngg_debug_position_request_another_pos_fetch_MASK 0x00400000L -#define PA_DEBUG46_0__ngg_debug_position_request_end_prev_diff_MASK 0x00800000L -#define PA_DEBUG46_0__ngg_debug_position_request_start_prev_diff_MASK 0x01000000L -#define PA_DEBUG46_0__ngg_debug_position_request_end_start_diff_MASK 0x02000000L -#define PA_DEBUG46_0__Reserved0_MASK 0xfc000000L - -// PA_DEBUG46_1 -#define PA_DEBUG46_1__ngg_utcl1_debug12_MASK 0xffffffffL - -// PA_DEBUG47_0 -#define PA_DEBUG47_0__ngg_debug_position_reuse_sideband_fifo_full_MASK 0x00000001L -#define PA_DEBUG47_0__ngg_debug_position_reuse_sideband_fifo_empty_MASK 0x00000002L -#define PA_DEBUG47_0__ngg_debug_position_reuse_sideband_fifo_busy_MASK 0x00000004L -#define PA_DEBUG47_0__ngg_debug_position_reuse_prim_fifo_full_MASK 0x00000008L -#define PA_DEBUG47_0__ngg_debug_position_reuse_output_prim_empty_MASK 0x00000010L -#define PA_DEBUG47_0__ngg_debug_position_reuse_prim_fifo_busy_MASK 0x00000020L -#define PA_DEBUG47_0__ngg_debug_position_reuse_current_state_MASK 0x00000040L -#define PA_DEBUG47_0__ngg_debug_position_reuse_iinput_sideband_valid_MASK 0x00000080L -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_stream_id_MASK 0x00000300L -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_eop_bit_MASK 0x00000400L -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_event_id_MASK 0x0001f800L -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_event_second_cycle_MASK \ - 0x00020000L -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_event_bit_MASK 0x00040000L -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_state_id_MASK 0x00380000L -#define PA_DEBUG47_0__Reserved0_MASK 0xffc00000L - -// PA_DEBUG47_1 -#define PA_DEBUG47_1__ngg_utcl1_debug13_MASK 0xffffffffL - -// PA_DEBUG48_0 -#define PA_DEBUG48_0__ngg_debug_position_return_ifetch_to_sxif_fifo_full_MASK 0x00000001L -#define PA_DEBUG48_0__ngg_debug_position_return_ipa_to_wd_dealloc_position_full_MASK 0x00000002L -#define PA_DEBUG48_0__ngg_debug_position_return_itc_return_empty_MASK 0x00000004L -#define PA_DEBUG48_0__ngg_debug_position_return_oposreq_to_posrtn_v_fifo_full_MASK 0x00000008L -#define PA_DEBUG48_0__ngg_debug_position_return_oposreq_to_posrtn_s_fifo_full_MASK 0x00000010L -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_v_fifo_busy_MASK 0x00000020L -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_s_fifo_busy_MASK 0x00000040L -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_v_fifo_empty_MASK 0x00000080L -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_s_fifo_empty_MASK 0x00000100L -#define PA_DEBUG48_0__ngg_debug_position_return_active_pos_return_state_MASK 0x00000600L -#define PA_DEBUG48_0__ngg_debug_position_return_cache_pos_index_MASK 0x00001800L -#define PA_DEBUG48_0__ngg_debug_position_return_active_pos_return_first_vert_MASK 0x00002000L -#define PA_DEBUG48_0__ngg_debug_position_return_active_pos_return_cache_pos_index_MASK 0x0000c000L -#define PA_DEBUG48_0__Reserved0_MASK 0xffff0000L - -// PA_DEBUG48_1 -#define PA_DEBUG48_1__ngg_utcl1_debug14_MASK 0xffffffffL - -// PA_DEBUG49_0 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_memreg0_busy_MASK 0x00000001L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_oreturn_empty_stream0_MASK 0x00000002L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_return_data_read_reg_full_stream0_MASK 0x00000004L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_memreg1_busy_MASK 0x00000008L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_oreturn_empty_stream1_MASK 0x00000010L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_return_data_read_reg_full_stream1_MASK 0x00000020L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_memreg2_busy_MASK 0x00000040L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_oreturn_empty_stream2_MASK 0x00000080L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_return_data_read_reg_full_stream2_MASK 0x00000100L -#define PA_DEBUG49_0__ngg_debug_tc_return_if_crawler_busy_MASK 0x00000200L -#define PA_DEBUG49_0__Reserved0_MASK 0xfffffc00L - -// PA_DEBUG49_1 -#define PA_DEBUG49_1__ngg_utcl1_debug15_MASK 0xffffffffL - -// PA_DEBUG50_0 -#define PA_DEBUG50_0__ngg_debug_return_crawler_encountered_error_writing_to_busy_location_stream0_MASK \ - 0x00000001L -#define PA_DEBUG50_0__ngg_debug_return_crawler_encountered_error_writing_to_busy_location_stream1_MASK \ - 0x00000002L -#define PA_DEBUG50_0__ngg_debug_return_crawler_encountered_error_writing_to_busy_location_stream2_MASK \ - 0x00000004L -#define PA_DEBUG50_0__ngg_debug_return_crawler_memory_data_valid_stream0_count_MASK 0x000001f8L -#define PA_DEBUG50_0__ngg_debug_return_crawler_memory_data_valid_stream1_count_MASK 0x00007e00L -#define PA_DEBUG50_0__ngg_debug_return_crawler_memory_data_valid_stream2_count_MASK 0x007f8000L -#define PA_DEBUG50_0__ngg_debug_return_crawler_obusy_MASK 0x00800000L -#define PA_DEBUG50_0__Reserved0_MASK 0xff000000L - -// PA_DEBUG50_1 -#define PA_DEBUG50_1__ngg_utcl1_debug16_MASK 0xffffffffL - -// PA_DEBUG51_0 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_pa_to_wd_dealloc_fifo_read_MASK 0x00000001L -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_pa_to_wd_dealloc_fifo_empty_MASK 0x00000002L -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_position_full_MASK 0x00000004L -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_index_full_MASK 0x00000008L -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_fifo_busy_MASK 0x00000010L -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_amount_MASK 0x0000ffe0L -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_state_var_index_MASK 0x00070000L -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_type_MASK 0x00080000L -#define PA_DEBUG51_0__Reserved0_MASK 0xfff00000L - -// PA_DEBUG52_0 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iutcl1_busy_MASK 0x00000001L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iposition_requester_idle_MASK 0x00000002L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iindex_requester_idle_MASK 0x00000004L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_isideband_requester_idle_MASK 0x00000008L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iposition_utcl1_return_busy_MASK 0x00000010L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iindex_utcl1_return_busy_MASK 0x00000020L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_isideband_utcl1_return_busy_MASK 0x00000040L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iposition_utcl1_send_busy_MASK 0x00000080L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iindex_utcl1_send_busy_MASK 0x00000100L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_isideband_utcl1_send_busy_MASK 0x00000200L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_ioutstanding_tc_requests_exist_MASK 0x00000400L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_all_clean_MASK 0x00000800L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_vmid_count_MASK 0x0000f000L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_oclean_MASK 0x00010000L -#define PA_DEBUG52_0__ngg_debug_shootdown_control_current_state_MASK 0x000e0000L -#define PA_DEBUG52_0__Reserved0_MASK 0xfff00000L - -// PA_DEBUG53_0 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_tc_credit_count_overflow_MASK 0x00000001L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_tc_credit_count_underflow_MASK 0x00000002L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sideband_tokens_overflow_MASK 0x00000004L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sideband_tokens_underflow_MASK 0x00000008L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents0_overflow_MASK 0x00000010L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents0_underflow_MASK 0x00000020L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents1_overflow_MASK 0x00000040L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents1_underflow_MASK 0x00000080L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_index_tokens_overflow_MASK 0x00000100L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_index_tokens_underflow_MASK 0x00000200L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_position_tokens_overflow_MASK 0x00000400L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_position_tokens_underflow_MASK 0x00000800L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_writing_to_busy_location_stream0_MASK \ - 0x00001000L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_writing_to_busy_location_stream1_MASK \ - 0x00002000L -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_writing_to_busy_location_stream2_MASK \ - 0x00004000L -#define PA_DEBUG53_0__Reserved0_MASK 0xffff8000L - -// PA_DEBUG54_0 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_sideband_pop_bit_fifo_full_MASK 0x00000001L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_vmid_fifo_full_MASK 0x00000002L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_sbmem_full_MASK 0x00000004L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_index_receive_fifo_full_MASK 0x00000008L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_prim_indices_fifo_full_MASK 0x00000010L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_prim_fifo_full_MASK 0x00000020L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_sideband_fifo_full_MASK 0x00000040L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_posreq_to_posrtn_v_fifo_full_MASK 0x00000080L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_posreq_to_posrtn_s_fifo_full_MASK 0x00000100L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_return_data_full_stream0_MASK 0x00000200L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_return_data_full_stream1_MASK 0x00000400L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_return_data_full_stream2_MASK 0x00000800L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_pa_to_wd_dealloc_index_full_MASK 0x00001000L -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_pa_to_wd_dealloc_position_full_MASK \ - 0x00002000L -#define PA_DEBUG54_0__Reserved0_MASK 0xffffc000L - -// PA_DEBUG55_0 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_sideband_pop_bit_fifo_empty_MASK 0x00000001L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_vmid_fifo_empty_MASK 0x00000002L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_sbmem_empty_MASK 0x00000004L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_index_receive_fifo_empty_MASK 0x00000008L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_prim_indices_fifo_empty_MASK 0x00000010L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_prim_fifo_empty_MASK 0x00000020L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_sideband_fifo_empty_MASK 0x00000040L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_posreq_to_posrtn_v_fifo_empty_MASK \ - 0x00000080L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_posreq_to_posrtn_s_fifo_empty_MASK \ - 0x00000100L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_return_data_empty_stream0_MASK 0x00000200L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_return_data_empty_stream1_MASK 0x00000400L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_return_data_empty_stream2_MASK 0x00000800L -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_pa_to_wd_dealloc_fifo_empty_MASK 0x00001000L -#define PA_DEBUG55_0__Reserved0_MASK 0xffffe000L - -// Idebug0 -#define Idebug0__cmd_debug_info00_MASK 0x00001fffL -#define Idebug0__Reserved0_MASK 0xffffe000L - -// Idebug1 -#define Idebug1__data_debug_info00_MASK 0x0001ffffL -#define Idebug1__Reserved0_MASK 0xfffe0000L - -// Idebug2 -#define Idebug2__cmd_debug_info01_MASK 0x00001fffL -#define Idebug2__Reserved0_MASK 0xffffe000L - -// Idebug3 -#define Idebug3__data_debug_info01_MASK 0x0001ffffL -#define Idebug3__Reserved0_MASK 0xfffe0000L - -// Idebug4 -#define Idebug4__cmd_debug_info10_MASK 0x00001fffL -#define Idebug4__Reserved0_MASK 0xffffe000L - -// Idebug5 -#define Idebug5__data_debug_info10_MASK 0x0001ffffL -#define Idebug5__Reserved0_MASK 0xfffe0000L - -// Idebug6 -#define Idebug6__cmd_debug_info11_MASK 0x00001fffL -#define Idebug6__Reserved0_MASK 0xffffe000L - -// Idebug7 -#define Idebug7__data_debug_info11_MASK 0x0001ffffL -#define Idebug7__Reserved0_MASK 0xfffe0000L - -// Idebug8 -#define Idebug8__cmd_debug_info20_MASK 0x00001fffL -#define Idebug8__Reserved0_MASK 0xffffe000L - -// Idebug9 -#define Idebug9__data_debug_info20_MASK 0x0001ffffL -#define Idebug9__Reserved0_MASK 0xfffe0000L - -// Idebug11 -#define Idebug11__cmd_debug_info30_MASK 0x00001fffL -#define Idebug11__Reserved0_MASK 0xffffe000L - -// Idebug12 -#define Idebug12__data_debug_info30_MASK 0x0001ffffL -#define Idebug12__Reserved0_MASK 0xfffe0000L - -// signal_debug_00 -#define signal_debug_00__current_shader_format_MASK 0x00000007L -#define signal_debug_00__number_of_mrts_no_z_MASK 0x00000078L -#define signal_debug_00__number_of_position_vectors_MASK 0x00000380L -#define signal_debug_00__number_of_valid_buff0_quads_in_previous_phases_MASK 0x00003c00L -#define signal_debug_00__number_of_valid_buff1_quads_in_previous_phases_MASK 0x0003c000L -#define signal_debug_00__number_of_valid_buff0_quads_in_this_phase_MASK 0x001c0000L -#define signal_debug_00__number_of_valid_buff1_quads_in_this_phase_MASK 0x00e00000L -#define signal_debug_00__Reserved0_MASK 0xff000000L - -// signal_debug_01 -#define signal_debug_01__current_shader_format_MASK 0x00000007L -#define signal_debug_01__number_of_mrts_no_z_MASK 0x00000078L -#define signal_debug_01__number_of_position_vectors_MASK 0x00000380L -#define signal_debug_01__number_of_valid_buff0_quads_in_previous_phases_MASK 0x00003c00L -#define signal_debug_01__number_of_valid_buff1_quads_in_previous_phases_MASK 0x0003c000L -#define signal_debug_01__number_of_valid_buff0_quads_in_this_phase_MASK 0x001c0000L -#define signal_debug_01__number_of_valid_buff1_quads_in_this_phase_MASK 0x00e00000L -#define signal_debug_01__Reserved0_MASK 0xff000000L - -// signal_debug_02 -#define signal_debug_02__sq_sx_expcmd1_empty_MASK 0x00000001L -#define signal_debug_02__sq_sx_expcmd0_empty_MASK 0x00000002L -#define signal_debug_02__sq_sx_expcmd1_full_MASK 0x00000004L -#define signal_debug_02__sq_sx_expcmd0_full_MASK 0x00000008L -#define signal_debug_02__spi_sx_expaddr1_empty_MASK 0x00000010L -#define signal_debug_02__spi_sx_expaddr0_empty_MASK 0x00000020L -#define signal_debug_02__spi_sx_expaddr1_full_MASK 0x00000040L -#define signal_debug_02__spi_sx_expaddr0_full_MASK 0x00000080L -#define signal_debug_02__sx_position_scoreboard_debug_15to0_MASK 0x00ffff00L -#define signal_debug_02__Reserved0_MASK 0xff000000L - -// signal_debug_03 -#define signal_debug_03__bank3_write_quad_select_MASK 0x00000003L -#define signal_debug_03__bank2_write_quad_select_MASK 0x0000000cL -#define signal_debug_03__bank1_write_quad_select_MASK 0x00000030L -#define signal_debug_03__Bank0_write_quad_select_MASK 0x000000c0L -#define signal_debug_03__write_enables_MASK 0x00ffff00L -#define signal_debug_03__Reserved0_MASK 0xff000000L - -// signal_debug_04 -#define signal_debug_04__read_phase_count_MASK 0x00000003L -#define signal_debug_04__aux_count_MASK 0x0000001cL -#define signal_debug_04__side_cycle_MASK 0x00000020L -#define signal_debug_04__requester_state_id_MASK 0x000003c0L -#define signal_debug_04__requester_empty_MASK 0x00000400L -#define signal_debug_04__requester_full_MASK 0x00000800L -#define signal_debug_04__pos_req_buff_empty_MASK 0x00001000L -#define signal_debug_04__pos_req_buff_full_MASK 0x00002000L -#define signal_debug_04__number_of_valid_quads_in_previous_phases_MASK 0x0003c000L -#define signal_debug_04__sx_position_scoreboard_debug_21to16_MASK 0x00fc0000L -#define signal_debug_04__Reserved0_MASK 0xff000000L - -// signal_debug_05 -#define signal_debug_05__sh_sx_expcmd1_pos_MASK 0x00000002L -#define signal_debug_05__sx_position_scoreboard_debug_30to22_MASK 0x000007fcL -#define signal_debug_05__traffic_to_db0_MASK 0x00000800L -#define signal_debug_05__scoreboard_read_data_qualified_mask_odd_db_11to0_MASK 0x00fff000L -#define signal_debug_05__Reserved0_MASK 0xff000000L - -// signal_debug_06 -#define signal_debug_06__sx_color_scoreboard_debug_max_36to13_MASK 0x00ffffffL -#define signal_debug_06__Reserved0_MASK 0xff000000L - -// signal_debug_07 -#define signal_debug_07__sx_color_scoreboard_debug_max_60to37_MASK 0x00ffffffL -#define signal_debug_07__Reserved0_MASK 0xff000000L - -// signal_debug_08 -#define signal_debug_08__sx_color_scoreboard_debug_max_84to61_MASK 0x00ffffffL -#define signal_debug_08__Reserved0_MASK 0xff000000L - -// signal_debug_09 -#define signal_debug_09__sx_color_scoreboard_debug_max_108to85_MASK 0x00ffffffL -#define signal_debug_09__Reserved0_MASK 0xff000000L - -// signal_debug_10 -#define signal_debug_10__sx_color_scoreboard_debug_max_132to109_MASK 0x00ffffffL -#define signal_debug_10__Reserved0_MASK 0xff000000L - -// signal_debug_11 -#define signal_debug_11__sx_color_scoreboard_debug_max_156to133_MASK 0x00ffffffL -#define signal_debug_11__Reserved0_MASK 0xff000000L - -// signal_debug_12 -#define signal_debug_12__sx_color_scoreboard_debug_max_160to157_MASK 0x0000000fL -#define signal_debug_12__sx_color_requester0_debug_19to0_MASK 0x00fffff0L -#define signal_debug_12__Reserved0_MASK 0xff000000L - -// signal_debug_13 -#define signal_debug_13__sx_color_requester0_debug_43to20_MASK 0x00ffffffL -#define signal_debug_13__Reserved0_MASK 0xff000000L - -// signal_debug_14 -#define signal_debug_14__sx_color_requester0_debug_61to44_MASK 0x0003ffffL -#define signal_debug_14__sx_color_dbif0_debug_MASK 0x007c0000L -#define signal_debug_14__sx_color_buff0_valids_debug_0_MASK 0x00800000L -#define signal_debug_14__Reserved0_MASK 0xff000000L - -// signal_debug_15 -#define signal_debug_15__sx_color_buff0_valids_debug_15to1_MASK 0x00007fffL -#define signal_debug_15__sx_color_requester1_debug_8to0_MASK 0x00ff8000L -#define signal_debug_15__Reserved0_MASK 0xff000000L - -// signal_debug_16 -#define signal_debug_16__sx_color_requester1_debug_32to9_MASK 0x00ffffffL -#define signal_debug_16__Reserved0_MASK 0xff000000L - -// signal_debug_17 -#define signal_debug_17__sx_color_requester1_debug_56to33_MASK 0x00ffffffL -#define signal_debug_17__Reserved0_MASK 0xff000000L - -// signal_debug_18 -#define signal_debug_18__sx_color_requester1_debug_61to57_MASK 0x0000001fL -#define signal_debug_18__sx_color_dbif1_debug_MASK 0x000003e0L -#define signal_debug_18__sx_color_buff1_valids_debug_13to0_MASK 0x00fffc00L -#define signal_debug_18__Reserved0_MASK 0xff000000L - -// signal_debug_19 -#define signal_debug_19__sx_color_buff1_valids_debug_15to14_MASK 0x00000003L -#define signal_debug_19__sx_color_requester2_debug_21to0_MASK 0x00fffffcL -#define signal_debug_19__Reserved0_MASK 0xff000000L - -// signal_debug_20 -#define signal_debug_20__sx_color_requester2_debug_45to22_MASK 0x00000003L - -// signal_debug_21 -#define signal_debug_21__sx_color_requester2_debug_61to46_MASK 0x0000ffffL -#define signal_debug_21__sx_color_dbif2_debug_MASK 0x001f0000L -#define signal_debug_21__sx_color_buff2_valids_debug_2to0_MASK 0x00e00000L -#define signal_debug_21__Reserved0_MASK 0xff000000L - -// signal_debug_22 -#define signal_debug_22__sx_color_buff2_valids_debug_15to3_MASK 0x00001fffL -#define signal_debug_22__sx_color_requester3_debug_10to0_MASK 0x00ffe000L -#define signal_debug_22__Reserved0_MASK 0xff000000L - -// signal_debug_23 -#define signal_debug_23__sx_color_requester3_debug_34to11_MASK 0x00ffffffL -#define signal_debug_23__Reserved0_MASK 0xff000000L - -// signal_debug_24 -#define signal_debug_24__sx_color_requester3_debug_58to35_MASK 0x00ffffffL -#define signal_debug_24__Reserved0_MASK 0xff000000L - -// signal_debug_25 -#define signal_debug_25__sx_color_requester3_debug_61to59_MASK 0x00000007L -#define signal_debug_25__sx_color_dbif3_debug_MASK 0x000000f8L -#define signal_debug_25__sx_color_buff3_valids_debug_MASK 0x00ffff00L -#define signal_debug_25__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_0 -#define SC_DBG_REG_0__ps_busy_d1_MASK 0x00000001L -#define SC_DBG_REG_0__ps_pa0_sc_fifo_empty_MASK 0x00000002L -#define SC_DBG_REG_0__ps_pa0_sc_fifo_full_MASK 0x00000004L -#define SC_DBG_REG_0__ps_pa1_sc_fifo_empty_MASK 0x00000008L -#define SC_DBG_REG_0__ps_pa1_sc_fifo_full_MASK 0x00000010L -#define SC_DBG_REG_0__ps_pa_sc_freeze_b_MASK 0x00000020L -#define SC_DBG_REG_0__pw_ps_freeze_b_MASK 0x00000040L -#define SC_DBG_REG_0__pff_pw_full_MASK 0x00000080L -#define SC_DBG_REG_0__Reserved2_MASK 0x00000100L -#define SC_DBG_REG_0__op_oc_rtr_MASK 0x00000200L -#define SC_DBG_REG_0__pk0_pm_bc_full_fz_MASK 0x00000400L -#define SC_DBG_REG_0__pk0_pm_spi_full_fz_MASK 0x00000800L -#define SC_DBG_REG_0__sc_reg_sclk_vld_MASK 0x00001000L -#define SC_DBG_REG_0__grp0_sc_dyn_sclk_vld_MASK 0x00002000L -#define SC_DBG_REG_0__grp1_sc_dyn_sclk_vld_MASK 0x00004000L -#define SC_DBG_REG_0__grp2_sc_dyn_sclk_vld_MASK 0x00008000L -#define SC_DBG_REG_0__Reserved1_MASK 0x001c0000L -#define SC_DBG_REG_0__scf_scb_current_credit_MASK 0x00e00000L -#define SC_DBG_REG_0__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_1 -#define SC_DBG_REG_1__qp_tp_tileff_rtr_MASK 0x00000001L -#define SC_DBG_REG_1__Reserved4_MASK 0x0000000eL -#define SC_DBG_REG_1__qp_tp_dbff_rtr_MASK 0x00000010L -#define SC_DBG_REG_1__Reserved3_MASK 0x000000e0L -#define SC_DBG_REG_1__qp0_pm_tileff_empty_MASK 0x00000100L -#define SC_DBG_REG_1__qp1_pm_tileff_empty_MASK 0x00000200L -#define SC_DBG_REG_1__Reserved2_MASK 0x00000c00L -#define SC_DBG_REG_1__qp0_pm_dbtileff_empty_MASK 0x00001000L -#define SC_DBG_REG_1__qp1_pm_dbtileff_empty_MASK 0x00002000L -#define SC_DBG_REG_1__Reserved1_MASK 0x000fc000L -#define SC_DBG_REG_1__qp0_pm_dbquadff_full_MASK 0x00100000L -#define SC_DBG_REG_1__qp1_pm_dbquadff_full_MASK 0x00200000L -#define SC_DBG_REG_1__Reserved0_MASK 0xffc00000L - -// SC_DBG_REG_2 -#define SC_DBG_REG_2__ta0_pm_quadff_empty_MASK 0x00000001L -#define SC_DBG_REG_2__ta1_pm_quadff_empty_MASK 0x00000002L -#define SC_DBG_REG_2__Reserved1_MASK 0x0000000cL -#define SC_DBG_REG_2__ta0_pm_dbquadff_empty_MASK 0x00000010L -#define SC_DBG_REG_2__ta1_pm_dbquadff_empty_MASK 0x00000020L -#define SC_DBG_REG_2__Reserved0_MASK 0xffffffc0L - -// SC_DBG_REG_3 -#define SC_DBG_REG_3__Reserved0_MASK 0xffffffffL - -// SC_DBG_REG_4 -#define SC_DBG_REG_4__qz0_pm_qp_tile_event_MASK 0x00000001L -#define SC_DBG_REG_4__qz0_pm_qp_tile_event_id_MASK 0x0000007eL -#define SC_DBG_REG_4__qz1_pm_qp_tile_event_MASK 0x00000080L -#define SC_DBG_REG_4__qz1_pm_qp_tile_event_id_MASK 0x00003f00L -#define SC_DBG_REG_4__Reserved0_MASK 0xffffc000L - -// SC_DBG_REG_5 -#define SC_DBG_REG_5__ps_pa0_sc_fifo_empty_dbg_q_MASK 0x00000001L -#define SC_DBG_REG_5__ps_pa1_sc_fifo_empty_dbg_q_MASK 0x00000002L -#define SC_DBG_REG_5__pa0_sc_data_fifo_rd_dbg_q_MASK 0x00000004L -#define SC_DBG_REG_5__pa1_sc_data_fifo_rd_dbg_q_MASK 0x00000008L -#define SC_DBG_REG_5__pa_select_dbg_q_0_MASK 0x00000010L -#define SC_DBG_REG_5__eop_pop_synced_after_null_prim_dbg_q_MASK 0x00000020L -#define SC_DBG_REG_5__pa0_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q_MASK 0x00000040L -#define SC_DBG_REG_5__pa1_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q_MASK 0x00000080L -#define SC_DBG_REG_5__pa0_popped_suppressed_eop_dbg_q_MASK 0x00000100L -#define SC_DBG_REG_5__pa1_popped_suppressed_eop_dbg_q_MASK 0x00000200L -#define SC_DBG_REG_5__dp_event_dbg_q_MASK 0x00000400L -#define SC_DBG_REG_5__dp_event_id_dbg_q_MASK 0x0001f800L -#define SC_DBG_REG_5__dp_eopg_dbg_q_MASK 0x00020000L -#define SC_DBG_REG_5__dp_eopkt_dbg_q_MASK 0x00040000L -#define SC_DBG_REG_5__dp_phase_dbg_q_MASK 0x00180000L -#define SC_DBG_REG_5__ring_state_dbg_q_2to0_MASK 0x00e00000L -#define SC_DBG_REG_5__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_6 -#define SC_DBG_REG_6__ps_pa0_sc_fifo_empty_dbg_q_MASK 0x00000001L -#define SC_DBG_REG_6__ps_pa1_sc_fifo_empty_dbg_q_MASK 0x00000002L -#define SC_DBG_REG_6__pa0_sc_data_fifo_rd_dbg_q_MASK 0x00000004L -#define SC_DBG_REG_6__pa1_sc_data_fifo_rd_dbg_q_MASK 0x00000008L -#define SC_DBG_REG_6__pa_select_dbg_q_MASK 0x00000030L -#define SC_DBG_REG_6__eop_pop_synced_after_null_prim_dbg_q_MASK 0x00000040L -#define SC_DBG_REG_6__pa0_pop_null_prim_eopbcast_bubble_ld_ctl_MASK 0x00000080L -#define SC_DBG_REG_6__pa1_pop_null_prim_eopbcast_bubble_ld_ctl_MASK 0x00000100L -#define SC_DBG_REG_6__pa0_popped_suppressed_eop_dbg_q_MASK 0x00000200L -#define SC_DBG_REG_6__pa1_popped_suppressed_eop_dbg_q_MASK 0x00000400L -#define SC_DBG_REG_6__dp_event_dbg_q_MASK 0x00000800L -#define SC_DBG_REG_6__dp_stateid_dbg_q_MASK 0x00007000L -#define SC_DBG_REG_6__dp_on_last_phase_dbg_q_MASK 0x00008000L -#define SC_DBG_REG_6__Reserved1_MASK 0x00010000L -#define SC_DBG_REG_6__ps_pa_sc_freeze_b_dbg_q_MASK 0x00020000L -#define SC_DBG_REG_6__dp_eopg_dbg_q_MASK 0x00040000L -#define SC_DBG_REG_6__dp_eopkt_dbg_q_MASK 0x00080000L -#define SC_DBG_REG_6__dp_phase_dbg_q_MASK 0x00300000L -#define SC_DBG_REG_6__ts_event_fifo_full_dbg_q_MASK 0x00400000L -#define SC_DBG_REG_6__ring_ptr_sel_dbg_q_MASK 0x00800000L -#define SC_DBG_REG_6__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_7 -#define SC_DBG_REG_7__ps_pa0_sc_fifo_empty_dbg_q_MASK 0x00000001L -#define SC_DBG_REG_7__ps_pa1_sc_fifo_empty_dbg_q_MASK 0x00000002L -#define SC_DBG_REG_7__pa0_sc_data_fifo_rd_dbg_q_MASK 0x00000004L -#define SC_DBG_REG_7__pa1_sc_data_fifo_rd_dbg_q_MASK 0x00000008L -#define SC_DBG_REG_7__pa_select_dbg_q_0_MASK 0x00000010L -#define SC_DBG_REG_7__eop_pop_synced_after_null_prim_dbg_q_MASK 0x00000020L -#define SC_DBG_REG_7__pa_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q_MASK 0x00000040L -#define SC_DBG_REG_7__pa0_popped_suppressed_eop_dbg_q_MASK 0x00000100L -#define SC_DBG_REG_7__pa1_popped_suppressed_eop_dbg_q_MASK 0x00000200L -#define SC_DBG_REG_7__dp_event_dbg_q_MASK 0x00000400L -#define SC_DBG_REG_7__dp_event_id_dbg_q_MASK 0x0001f800L -#define SC_DBG_REG_7__dp_eopg_dbg_q_MASK 0x00020000L -#define SC_DBG_REG_7__dp_eopkt_dbg_q_MASK 0x00040000L -#define SC_DBG_REG_7__ring_state_dbg_q_MASK 0x00780000L -#define SC_DBG_REG_7__OoO_eop_pop_sync_all_nulls_dbg_q_MASK 0x00800000L -#define SC_DBG_REG_7__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_8 -#define SC_DBG_REG_8__ps_pa0_sc_fifo_empty_dbg_q_MASK 0x00000001L -#define SC_DBG_REG_8__ps_pa1_sc_fifo_empty_dbg_q_MASK 0x00000002L -#define SC_DBG_REG_8__pa0_sc_data_fifo_rd_dbg_q_MASK 0x00000004L -#define SC_DBG_REG_8__pa1_sc_data_fifo_rd_dbg_q_MASK 0x00000008L -#define SC_DBG_REG_8__pa_select_dbg_q_MASK 0x00000030L -#define SC_DBG_REG_8__eop_pop_synced_after_null_prim_dbg_q_MASK 0x00000040L -#define SC_DBG_REG_8__pa0_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q_MASK 0x00000080L -#define SC_DBG_REG_8__pa1_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q_MASK 0x00000100L -#define SC_DBG_REG_8__pa0_popped_suppressed_eop_dbg_q_MASK 0x00000200L -#define SC_DBG_REG_8__pa1_popped_suppressed_eop_dbg_q_MASK 0x00000400L -#define SC_DBG_REG_8__dp_event_dbg_q_MASK 0x00000800L -#define SC_DBG_REG_8__dp_stateid_dbg_q_MASK 0x00007000L -#define SC_DBG_REG_8__dp_phase_dbg_q_MASK 0x00018000L -#define SC_DBG_REG_8__ps_pa_sc_freeze_b_dbg_q_MASK 0x00020000L -#define SC_DBG_REG_8__dp_eopg_dbg_q_MASK 0x00040000L -#define SC_DBG_REG_8__dp_eopkt_dbg_q_MASK 0x00080000L -#define SC_DBG_REG_8__OoO_eop_pop_sync_all_nulls_dbg_q_MASK 0x00100000L -#define SC_DBG_REG_8__ts_event_fifo_full_dbg_q_MASK 0x00200000L -#define SC_DBG_REG_8__ring_state_dbg_q_1to0_MASK 0x00c00000L -#define SC_DBG_REG_8__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_9 -#define SC_DBG_REG_9__ps_pa0_sc_fifo_empty_dbg_q_MASK 0x00000001L -#define SC_DBG_REG_9__ps_pa1_sc_fifo_empty_dbg_q_MASK 0x00000002L -#define SC_DBG_REG_9__ps_pa2_sc_fifo_empty_dbg_q_MASK 0x00000004L -#define SC_DBG_REG_9__ps_pa3_sc_fifo_empty_dbg_q_MASK 0x00000008L -#define SC_DBG_REG_9__pa0_sc_data_fifo_rd_dbg_q_MASK 0x00000010L -#define SC_DBG_REG_9__pa1_sc_data_fifo_rd_dbg_q_MASK 0x00000020L -#define SC_DBG_REG_9__pa2_sc_data_fifo_rd_dbg_q_MASK 0x00000040L -#define SC_DBG_REG_9__pa3_sc_data_fifo_rd_dbg_q_MASK 0x00000080L -#define SC_DBG_REG_9__pa_select_dbg_q_MASK 0x00000300L -#define SC_DBG_REG_9__eop_pop_synced_MASK 0x00000400L -#define SC_DBG_REG_9__pa_popped_suppressed_eop_dbg_q_MASK 0x00000800L -#define SC_DBG_REG_9__dp_event_dbg_q_MASK 0x00001000L -#define SC_DBG_REG_9__dp_event_id_dbg_q_MASK 0x0007e000L -#define SC_DBG_REG_9__dp_eopg_dbg_q_MASK 0x00080000L -#define SC_DBG_REG_9__dp_eopkt_dbg_q_MASK 0x00100000L -#define SC_DBG_REG_9__ring_state_dbg_q_2to0_MASK 0x00e00000L -#define SC_DBG_REG_9__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_10 -#define SC_DBG_REG_10__ps_pa0_sc_fifo_empty_dbg_q_MASK 0x00000001L -#define SC_DBG_REG_10__ps_pa1_sc_fifo_empty_dbg_q_MASK 0x00000002L -#define SC_DBG_REG_10__ps_pa2_sc_fifo_empty_dbg_q_MASK 0x00000004L -#define SC_DBG_REG_10__ps_pa3_sc_fifo_empty_dbg_q_MASK 0x00000008L -#define SC_DBG_REG_10__pa0_sc_data_fifo_rd_dbg_q_MASK 0x00000010L -#define SC_DBG_REG_10__pa1_sc_data_fifo_rd_dbg_q_MASK 0x00000020L -#define SC_DBG_REG_10__pa2_sc_data_fifo_rd_dbg_q_MASK 0x00000040L -#define SC_DBG_REG_10__pa3_sc_data_fifo_rd_dbg_q_MASK 0x00000080L -#define SC_DBG_REG_10__pa_select_dbg_q_MASK 0x00000300L -#define SC_DBG_REG_10__eop_pop_synced_MASK 0x00000400L -#define SC_DBG_REG_10__pa_popped_suppressed_eop_dbg_q_MASK 0x00000800L -#define SC_DBG_REG_10__dp_event_dbg_q_MASK 0x00001000L -#define SC_DBG_REG_10__dp_stateid_dbg_q_MASK 0x0000e000L -#define SC_DBG_REG_10__dp_eopg_dbg_q_MASK 0x00010000L -#define SC_DBG_REG_10__dp_eopkt_dbg_q_MASK 0x00020000L -#define SC_DBG_REG_10__dp_phase_dbg_q_MASK 0x000c0000L -#define SC_DBG_REG_10__ring_state_dbg_q_MASK 0x00f00000L -#define SC_DBG_REG_10__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_11 -#define SC_DBG_REG_11__tp_qz_freeze_b_MASK 0x00000001L -#define SC_DBG_REG_11__ef_tp_event_MASK 0x00000002L -#define SC_DBG_REG_11__send_tile_MASK 0x00000004L -#define SC_DBG_REG_11__need_to_send_MASK 0x00000008L -#define SC_DBG_REG_11__num_sent_tiles_MASK 0x000000f0L -#define SC_DBG_REG_11__remaining_mask_MASK 0x00000100L -#define SC_DBG_REG_11__ef_tp_last_supertile_of_prim_MASK 0x00000200L -#define SC_DBG_REG_11__ef_tp_pass_empty_prim_MASK 0x00000400L -#define SC_DBG_REG_11__ef_tp_db_has_ordercull_entry_MASK 0x00000800L -#define SC_DBG_REG_11__ef_tp_db_has_last_tile_in_supertile_MASK 0x00001000L -#define SC_DBG_REG_11__last_supertile_of_prim_MASK 0x00002000L -#define SC_DBG_REG_11__last_tile_of_supertile_MASK 0x00004000L -#define SC_DBG_REG_11__s0_idle_MASK 0x00008000L -#define SC_DBG_REG_11__s1_idle_MASK 0x00010000L -#define SC_DBG_REG_11__s2_idle_MASK 0x00020000L -#define SC_DBG_REG_11__ef_tp_rts_and_n_ef_tp_rtr_MASK 0x00040000L -#define SC_DBG_REG_11__tp_qz_tile_rts_and_n_tp_qz_tile_rtr_MASK 0x00080000L -#define SC_DBG_REG_11__ef_keep_rts_and_n_ef_keep_rtr_MASK 0x00100000L -#define SC_DBG_REG_11__s0_rts_and_n_s0_rtr_MASK 0x00200000L -#define SC_DBG_REG_11__s1_rts_and_n_s1_rtr_MASK 0x00400000L -#define SC_DBG_REG_11__s2_rts_and_n_s2_rtr_MASK 0x00800000L -#define SC_DBG_REG_11__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_12 -#define SC_DBG_REG_12__z_tc_exp_MASK 0x000001ffL -#define SC_DBG_REG_12__qz_out_backface_MASK 0x00000200L -#define SC_DBG_REG_12__qm_db_id_MASK 0x00000c00L -#define SC_DBG_REG_12__qm_z_mask_needed_MASK 0x00001000L -#define SC_DBG_REG_12__qm_valid_MASK 0x00002000L -#define SC_DBG_REG_12__qm_covered_MASK 0x00004000L -#define SC_DBG_REG_12__qm_event_id_MASK 0x001f8000L -#define SC_DBG_REG_12__qm_event_MASK 0x00200000L -#define SC_DBG_REG_12__Reserved0_MASK 0xffc00000L - -// SC_DBG_REG_13 -#define SC_DBG_REG_13__qz_out_state_id_MASK 0x00000007L -#define SC_DBG_REG_13__qz_out_multi_sample_MASK 0x00000008L -#define SC_DBG_REG_13__int_freeze_b_MASK 0x00000010L -#define SC_DBG_REG_13__valid_MASK 0x00000020L -#define SC_DBG_REG_13__valid_out_MASK 0x00000040L -#define SC_DBG_REG_13__Reserved0_MASK 0xffffff80L - -// SC_DBG_REG_14 -#define SC_DBG_REG_14__Reserved0_MASK 0xffffffffL - -// SC_DBG_REG_15 -#define SC_DBG_REG_15__Reserved0_MASK 0xffffffffL - -// SC_DBG_REG_16 -#define SC_DBG_REG_16__r0_mask_MASK 0x0000ffffL -#define SC_DBG_REG_16__Reserved0_MASK 0xffff0000L - -// SC_DBG_REG_17 -#define SC_DBG_REG_17__r0_qd_picker_mask_MASK 0x000000ffL -#define SC_DBG_REG_17__Reserved0_MASK 0xffffff00L - -// SC_DBG_REG_18 -#define SC_DBG_REG_18__tilefifo_empty_MASK 0x00000001L -#define SC_DBG_REG_18__tilefifo_full_MASK 0x00000002L -#define SC_DBG_REG_18__tile_mask_fifo_empty_MASK 0x00000004L -#define SC_DBG_REG_18__tile_mask_fifo_full_MASK 0x00000008L -#define SC_DBG_REG_18__rslt_fifo_empty_MASK 0x00000010L -#define SC_DBG_REG_18__rslt_fifo_full_MASK 0x00000020L -#define SC_DBG_REG_18__pop_fifo_r0_MASK 0x00000040L -#define SC_DBG_REG_18__r0_last_tile_of_prim_MASK 0x00000080L -#define SC_DBG_REG_18__last_quad_MASK 0x00000100L -#define SC_DBG_REG_18__rslt_r0_SC_CR_MSAA_NUM_SAMPLES_MASK 0x00000e00L -#define SC_DBG_REG_18__rslt_r0_SC_CR_TILE_RATE_MASK 0x00001000L -#define SC_DBG_REG_18__rslt_r0_SC_CR_WOE_MASK 0x00002000L -#define SC_DBG_REG_18__rslt_r0_SC_CR_KILL_PIX_MASK 0x00004000L -#define SC_DBG_REG_18__rslt_r0_SC_TD_ZMASK_NEEDED_MASK 0x00008000L -#define SC_DBG_REG_18__qs_quad0_valid_MASK 0x00010000L -#define SC_DBG_REG_18__qs_quad1_valid_MASK 0x00020000L -#define SC_DBG_REG_18__qs_quad2_valid_MASK 0x00040000L -#define SC_DBG_REG_18__qs_quad3_valid_MASK 0x00080000L -#define SC_DBG_REG_18__qd_y_MASK 0x00300000L -#define SC_DBG_REG_18__qd_x_MASK 0x00c00000L -#define SC_DBG_REG_18__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_19 -#define SC_DBG_REG_19__r0_bit_cnt_MASK 0x0000001fL -#define SC_DBG_REG_19__Reserved0_MASK 0xffffffe0L - -// SC_DBG_REG_20 -#define SC_DBG_REG_20__squadfifo_empty_MASK 0x00000001L -#define SC_DBG_REG_20__squadfifo_full_MASK 0x00000002L -#define SC_DBG_REG_20__dbsc_quadfifo_empty_MASK 0x00000004L -#define SC_DBG_REG_20__dbsc_quadfifo_full_MASK 0x00000008L -#define SC_DBG_REG_20__quadfifo_empty_MASK 0x00000010L -#define SC_DBG_REG_20__quadfifo_full_MASK 0x00000020L -#define SC_DBG_REG_20__quadzfifo_empty_MASK 0x00000040L -#define SC_DBG_REG_20__quadzfifo_full_MASK 0x00000080L -#define SC_DBG_REG_20__Reserved0_MASK 0xffffff00L - -// SC_DBG_REG_21 -#define SC_DBG_REG_21__ta_tr_quadcnt_MASK 0x0000001fL -#define SC_DBG_REG_21__ta_tr_lasttile_MASK 0x00000020L -#define SC_DBG_REG_21__ta_tr_stateid_MASK 0x000001c0L -#define SC_DBG_REG_21__ta_tr_eventid_MASK 0x00007e00L -#define SC_DBG_REG_21__ta_tr_event_MASK 0x00008000L -#define SC_DBG_REG_21__ta_tr_rts_MASK 0x00010000L -#define SC_DBG_REG_21__ta_tr_rtr_MASK 0x00020000L -#define SC_DBG_REG_21__quads_rdy_MASK 0x00040000L -#define SC_DBG_REG_21__last_quad_MASK 0x00080000L -#define SC_DBG_REG_21__quad_cnt_MASK 0x00f00000L -#define SC_DBG_REG_21__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_22 -#define SC_DBG_REG_22__quad_cnt_5_MASK 0x00000001L -#define SC_DBG_REG_22__qp_rtr_MASK 0x00000002L -#define SC_DBG_REG_22__Reserved0_MASK 0xfffffffcL - -// SC_DBG_REG_23 -#define SC_DBG_REG_23__pdf_pipe0_empty_MASK 0x00000001L -#define SC_DBG_REG_23__pdf_pipe1_empty_MASK 0x00000002L -#define SC_DBG_REG_23__pdf_full_MASK 0x00000004L -#define SC_DBG_REG_23__pdf_pipe0_busy_MASK 0x00000008L -#define SC_DBG_REG_23__pdf_pipe1_busy_MASK 0x00000010L -#define SC_DBG_REG_23__qs_pipe0_empty_MASK 0x00000020L -#define SC_DBG_REG_23__qs_pipe1_empty_MASK 0x00000040L -#define SC_DBG_REG_23__Reserved2_MASK 0x00000180L -#define SC_DBG_REG_23__qs_pipe0_full_MASK 0x00000200L -#define SC_DBG_REG_23__qs_pipe1_full_MASK 0x00000400L -#define SC_DBG_REG_23__Reserved1_MASK 0x00001800L -#define SC_DBG_REG_23__qs_pipe0_busy_MASK 0x00002000L -#define SC_DBG_REG_23__qs_pipe1_busy_MASK 0x00004000L -#define SC_DBG_REG_23__Reserved0_MASK 0xffff8000L - -// SC_DBG_REG_24 -#define SC_DBG_REG_24__Reserved1_MASK 0x0000000fL -#define SC_DBG_REG_24__pkr_qd0_prim_misc_mx_PKR_PRIM_MISC_PA_ID_MASK 0x00000030L -#define SC_DBG_REG_24__pkr_qd1_prim_misc_mx_PKR_PRIM_MISC_PA_ID_MASK 0x000000c0L -#define SC_DBG_REG_24__Reserved0_MASK 0xffffe000L - -// SC_DBG_REG_25 -#define SC_DBG_REG_25__pkr_qd0_hit_MASK 0x00000001L -#define SC_DBG_REG_25__pkr_qd1_hit_MASK 0x00000002L -#define SC_DBG_REG_25__Reserved0_MASK 0x0000000cL -#define SC_DBG_REG_25__pkr_ds_end_of_vector_MASK 0x00000010L -#define SC_DBG_REG_25__pkr_qd0_first_MASK 0x00000020L -#define SC_DBG_REG_25__pkr_qd1_first_MASK 0x00000040L -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_2_MASK 0x00000080L -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_3_MASK 0x00000100L -#define SC_DBG_REG_25__pkr_ds_ctl_only_cmd_MASK 0x00000200L -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_0_MASK 0x00000400L -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_1_MASK 0x00000800L -#define SC_DBG_REG_25__pkr_send_row_MASK 0x00001000L -#define SC_DBG_REG_25__pkr_curr_row_qdcnt_MASK 0x0000e000L -#define SC_DBG_REG_25__pkr_curr_qds_per_vector_MASK 0x000f0000L -#define SC_DBG_REG_25__dbg_spi_full_fz_MASK 0x00100000L -#define SC_DBG_REG_25__dbg_bc_full_fz_MASK 0x00200000L -#define SC_DBG_REG_25__pkr_primdata_dealloc_0_MASK 0x01c00000L - -// SC_DBG_REG_26 -#define SC_DBG_REG_26__pkr_primdata_dealloc_0_MASK 0x00000001L -#define SC_DBG_REG_26__pkr_primdata_dealloc_1_MASK 0x0000000eL -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_0_MASK 0x00000010L -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_1_MASK 0x00000020L -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_2_MASK 0x00000040L -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_3_MASK 0x00000080L - -// SC_DBG_REG_27 -#define SC_DBG_REG_27__cb0_context_done_count_neq0_MASK 0x00000001L -#define SC_DBG_REG_27__cb1_context_done_count_neq0_MASK 0x00000002L -#define SC_DBG_REG_27__cb2_context_done_count_neq0_MASK 0x00000004L -#define SC_DBG_REG_27__cb3_context_done_count_neq0_MASK 0x00000008L -#define SC_DBG_REG_27__cb4_context_done_count_neq0_MASK 0x00000010L -#define SC_DBG_REG_27__cb0_eop_count_neq0_MASK 0x00000020L -#define SC_DBG_REG_27__cb1_eop_count_neq0_MASK 0x00000040L -#define SC_DBG_REG_27__cb2_eop_count_neq0_MASK 0x00000080L -#define SC_DBG_REG_27__cb3_eop_count_neq0_MASK 0x00000100L -#define SC_DBG_REG_27__cb4_eop_count_neq0_MASK 0x00000200L -#define SC_DBG_REG_27__cb0_sync_clean_MASK 0x00000400L -#define SC_DBG_REG_27__cb1_sync_clean_MASK 0x00000800L -#define SC_DBG_REG_27__cb2_sync_clean_MASK 0x00001000L -#define SC_DBG_REG_27__cb3_sync_clean_MASK 0x00002000L -#define SC_DBG_REG_27__cb4_sync_clean_MASK 0x00004000L -#define SC_DBG_REG_27__db0_sync_clean_MASK 0x00008000L -#define SC_DBG_REG_27__db1_sync_clean_MASK 0x00010000L -#define SC_DBG_REG_27__db2_sync_clean_MASK 0x00020000L -#define SC_DBG_REG_27__db3_sync_clean_MASK 0x00040000L -#define SC_DBG_REG_27__db4_sync_clean_MASK 0x00080000L -#define SC_DBG_REG_27__cpg_sync0_clean_MASK 0x00100000L -#define SC_DBG_REG_27__sync0_none_clean_MASK 0x00200000L -#define SC_DBG_REG_27__sync0_all_clean_MASK 0x00400000L -#define SC_DBG_REG_27__sync0_clean_count_MASK 0x00800000L -#define SC_DBG_REG_27__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_28 -#define SC_DBG_REG_28__sync0_clean_count_MASK 0x00000003L -#define SC_DBG_REG_28__cpg_sync1_clean_MASK 0x00000004L -#define SC_DBG_REG_28__sync1_none_clean_MASK 0x00000008L -#define SC_DBG_REG_28__sync1_all_clean_MASK 0x00000010L -#define SC_DBG_REG_28__sync1_clean_count_MASK 0x000000e0L - -// SC_DBG_REG_29 -#define SC_DBG_REG_29__sclk_dyn_vld_MASK 0x00000001L -#define SC_DBG_REG_29__pa_select_MASK 0x00000006L -#define SC_DBG_REG_29__Reserved1_MASK 0x00000008L -#define SC_DBG_REG_29__ps_pa_sc_data_valid_MASK 0x00000010L -#define SC_DBG_REG_29__ps_pa0_sc_fifo_empty_MASK 0x00000020L -#define SC_DBG_REG_29__ps_pa1_sc_fifo_empty_MASK 0x00000040L -#define SC_DBG_REG_29__dp_eopg_MASK 0x00000080L -#define SC_DBG_REG_29__dp_event_MASK 0x00000100L -#define SC_DBG_REG_29__phase_MASK 0x00000600L -#define SC_DBG_REG_29__pw_ps_freeze_b_MASK 0x00000800L -#define SC_DBG_REG_29__ps_pa_sc_freeze_b_MASK 0x00001000L -#define SC_DBG_REG_29__ps_pff_we_MASK 0x00002000L -#define SC_DBG_REG_29__ps_zff_we_MASK 0x00004000L -#define SC_DBG_REG_29__pre_rts_MASK 0x00008000L -#define SC_DBG_REG_29__rts_d1_MASK 0x00010000L -#define SC_DBG_REG_29__rts_d2_MASK 0x00020000L -#define SC_DBG_REG_29__rts_d3_MASK 0x00040000L -#define SC_DBG_REG_29__ps_pse_rts_MASK 0x00080000L -#define SC_DBG_REG_29__pa_index_hp3d_OoO_MASK 0x00300000L -#define SC_DBG_REG_29__pa_index_p3d_OoO_MASK 0x00c00000L -#define SC_DBG_REG_29__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_30 -#define SC_DBG_REG_30__pa_index_hp3d_IoO_MASK 0x00000003L -#define SC_DBG_REG_30__pa_index_p3d_IoO_MASK 0x0000000cL -#define SC_DBG_REG_30__ring_state_2to0_MASK 0x00000070L -#define SC_DBG_REG_30__multicycle_bubble_freeze_MASK 0x00000080L - -// SC_DBG_REG_31 -#define SC_DBG_REG_31__phase_d1_MASK 0x00000003L -#define SC_DBG_REG_31__event_mod_MASK 0x00000004L -#define SC_DBG_REG_31__event_id_mod_MASK 0x000001f8L -#define SC_DBG_REG_31__end_of_pkt_d1_MASK 0x00000200L -#define SC_DBG_REG_31__clip_prim_d1_MASK 0x00000400L -#define SC_DBG_REG_31__null_prim_mod_MASK 0x00000800L -#define SC_DBG_REG_31__first_prim_of_vector_0_d1_MASK 0x00001000L -#define SC_DBG_REG_31__first_prim_of_vector_1_d1_MASK 0x00002000L -#define SC_DBG_REG_31__dealloc_0_d1_MASK 0x0000c000L -#define SC_DBG_REG_31__dealloc_1_d1_MASK 0x00030000L -#define SC_DBG_REG_31__last_prim_of_vector_0_d1_MASK 0x00040000L -#define SC_DBG_REG_31__last_prim_of_vector_1_d1_MASK 0x00080000L -#define SC_DBG_REG_31__st_indx_d1_MASK 0x00700000L -#define SC_DBG_REG_31__first_prim_of_vector_2_d1_MASK 0x00800000L -#define SC_DBG_REG_31__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_32 -#define SC_DBG_REG_32__first_prim_of_vector_3_d1_MASK 0x00000001L -#define SC_DBG_REG_32__dealloc_2_d1_MASK 0x00000006L -#define SC_DBG_REG_32__dealloc_3_d1_MASK 0x00000018L -#define SC_DBG_REG_32__last_prim_of_vector_2_d1_MASK 0x00000020L -#define SC_DBG_REG_32__last_prim_of_vector_3_d1_MASK 0x00000040L -#define SC_DBG_REG_32__ts_event_fifo_full_MASK 0x00000080L - -// SC_DBG_REG_33 -#define SC_DBG_REG_33__pa0_ps_data_send_MASK 0x00000001L -#define SC_DBG_REG_33__ps_pa0_sc_fifo_empty_MASK 0x00000002L -#define SC_DBG_REG_33__pa1_ps_data_send_MASK 0x00000004L -#define SC_DBG_REG_33__ps_pa1_sc_fifo_empty_MASK 0x00000008L -#define SC_DBG_REG_33__busy_processing_multicycle_prim_MASK 0x00000010L -#define SC_DBG_REG_33__busy_cnt_MASK 0x00003fe0L -#define SC_DBG_REG_33__ctx_done_fifo_empty_MASK 0x00004000L -#define SC_DBG_REG_33__pa2_ps_data_send_MASK 0x00008000L -#define SC_DBG_REG_33__ps_pa2_sc_fifo_empty_MASK 0x00010000L -#define SC_DBG_REG_33__pa3_ps_data_send_MASK 0x00020000L -#define SC_DBG_REG_33__ps_pa3_sc_fifo_empty_MASK 0x00040000L -#define SC_DBG_REG_33__scb_busy_MASK 0x00080000L -#define SC_DBG_REG_33__scf_scb_interface_busy_MASK 0x00100000L -#define SC_DBG_REG_33__backend_busy_MASK 0x00200000L -#define SC_DBG_REG_33__bm_busy_MASK 0x00400000L -#define SC_DBG_REG_33__se_rb_active_pipe_mask_MASK 0x00800000L -#define SC_DBG_REG_33__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_34 -#define SC_DBG_REG_34__se_rb_active_pipe_mask_MASK 0x0000007fL -#define SC_DBG_REG_34__ts_event_fifo_empty_MASK 0x00000080L -#define SC_DBG_REG_34__Reserved0_MASK 0xffffff00L - -// SC_DBG_REG_35 -#define SC_DBG_REG_35__rc_rtr_dly_MASK 0x00000001L -#define SC_DBG_REG_35__zff_pw_full_d1_MASK 0x00000002L -#define SC_DBG_REG_35__pff_pw_full_d1_MASK 0x00000004L -#define SC_DBG_REG_35__pipe_freeze_b_MASK 0x00000008L -#define SC_DBG_REG_35__prim_rts_MASK 0x00000010L -#define SC_DBG_REG_35__next_prim_rts_dly_MASK 0x00000020L -#define SC_DBG_REG_35__next_prim_rtr_dly_MASK 0x00000040L -#define SC_DBG_REG_35__pre_stage1_rts_d1_MASK 0x00000080L -#define SC_DBG_REG_35__stage0_rts_MASK 0x00000100L -#define SC_DBG_REG_35__phase_rts_dly_MASK 0x00000200L -#define SC_DBG_REG_35__end_of_prim_s1_dly_MASK 0x00000400L -#define SC_DBG_REG_35__pass_empty_prim_s1_MASK 0x00000800L -#define SC_DBG_REG_35__event_s1_MASK 0x00001000L -#define SC_DBG_REG_35__event_id_s1_MASK 0x0007e000L -#define SC_DBG_REG_35__Reserved0_MASK 0xfff80000L - -// SC_DBG_REG_36 -#define SC_DBG_REG_36__Reserved0_MASK 0xffffffffL - -// SC_DBG_REG_37 -#define SC_DBG_REG_37__x_curr_s1_MASK 0x00001fffL -#define SC_DBG_REG_37__y_curr_s1_MASK 0x00ffe000L -#define SC_DBG_REG_37__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_38 -#define SC_DBG_REG_38__y_curr_s1_MASK 0x00000003L -#define SC_DBG_REG_38__x_dir_s1_MASK 0x00000004L -#define SC_DBG_REG_38__y_dir_s1_MASK 0x00000008L -#define SC_DBG_REG_38__Reserved0_MASK 0xffff0000L - -// SC_DBG_REG_39 -#define SC_DBG_REG_39__supertile_mask_debug_15to0_MASK 0x0000ffffL -#define SC_DBG_REG_39__Reserved0_MASK 0xffff0000L - -// SC_DBG_REG_40 -#define SC_DBG_REG_40__pw_bm_rts_and_n_pw_bm_rtr_MASK 0x00000001L -#define SC_DBG_REG_40__pw_bm_rts_and_n_po_rts_MASK 0x00000002L -#define SC_DBG_REG_40__po_rts_and_n_po_rtr_MASK 0x00000004L -#define SC_DBG_REG_40__po_bm_rts_and_n_po_bm_rtr_MASK 0x00000008L -#define SC_DBG_REG_40__bm_be0_rts_and_n_bm_be0_rtr_MASK 0x00000010L -#define SC_DBG_REG_40__bm_be1_rts_and_n_bm_be1_rtr_MASK 0x00000020L -#define SC_DBG_REG_40__pw_bm_rts_and_po_rts_and_pff_bm_empty_MASK 0x00000040L -#define SC_DBG_REG_40__be0_db0_has_last_tile_in_supertile_lit_tile_MASK 0x00000080L -#define SC_DBG_REG_40__be0_db0_has_last_tile_in_supertile_MASK 0x00000100L -#define SC_DBG_REG_40__be0_db1_has_last_tile_in_supertile_lit_tile_MASK 0x00000200L -#define SC_DBG_REG_40__be0_db1_has_last_tile_in_supertile_MASK 0x00000400L -#define SC_DBG_REG_40__backend0_tile_mask_zero_not_event_MASK 0x00000800L -#define SC_DBG_REG_40__backend0_tile_mask_zero_MASK 0x00001000L -#define SC_DBG_REG_40__be1_db0_has_last_tile_in_supertile_lit_tile_MASK 0x00002000L -#define SC_DBG_REG_40__be1_db0_has_last_tile_in_supertile_MASK 0x00004000L -#define SC_DBG_REG_40__be1_db1_has_last_tile_in_supertile_lit_tile_MASK 0x00008000L -#define SC_DBG_REG_40__be1_db1_has_last_tile_in_supertile_MASK 0x00010000L -#define SC_DBG_REG_40__backend1_tile_mask_zero_not_event_MASK 0x00020000L -#define SC_DBG_REG_40__backend1_tile_mask_zero_MASK 0x00040000L -#define SC_DBG_REG_40__Reserved0_MASK 0xfff80000L - -// SC_DBG_REG_41 -#define SC_DBG_REG_41__Reserved0_MASK 0xffffffffL - -// SC_DBG_REG_42 -#define SC_DBG_REG_42__bm_busy_MASK 0x00000001L -#define SC_DBG_REG_42__fifo_backend0_idle_MASK 0x00000002L -#define SC_DBG_REG_42__fifo_backend1_idle_MASK 0x00000004L -#define SC_DBG_REG_42__po_bm_stage_idle_MASK 0x00000008L -#define SC_DBG_REG_42__pw_bm_event_MASK 0x00000010L -#define SC_DBG_REG_42__pw_bm_last_supertile_of_prim_MASK 0x00000020L -#define SC_DBG_REG_42__pw_bm_pass_empty_prim_MASK 0x00000040L -#define SC_DBG_REG_42__pff_bm_empty_MASK 0x00000080L -#define SC_DBG_REG_42__bm_be0_db0_has_last_tile_in_supertile_MASK 0x00000100L -#define SC_DBG_REG_42__event_pipe_id_sh0_MASK 0x00000600L -#define SC_DBG_REG_42__event_pipe_id_sh1_MASK 0x00001800L -#define SC_DBG_REG_42__Reserved0_MASK 0xffffe000L - -// SC_DBG_REG_43 -#define SC_DBG_REG_43__ps_busy_MASK 0x00000001L -#define SC_DBG_REG_43__ps_pm_backend_busy_MASK 0x00000002L -#define SC_DBG_REG_43__ps_pm_bm_busy_MASK 0x00000004L -#define SC_DBG_REG_43__ps_pm_arb_pa_sc_busy_MASK 0x00000008L -#define SC_DBG_REG_43__ps_pm_arb_sc_busy_MASK 0x00000010L -#define SC_DBG_REG_43__ps_pm_scf_scb_interface_busy_MASK 0x00000020L -#define SC_DBG_REG_43__ps_pm_scb_busy_MASK 0x00000040L -#define SC_DBG_REG_43__ctx_done_fifo_empty_MASK 0x00000080L -#define SC_DBG_REG_43__ts_event_fifo_empty_MASK 0x00000100L -#define SC_DBG_REG_43__ps_pa0_sc_fifo_empty_MASK 0x00000200L -#define SC_DBG_REG_43__ps_pa1_sc_fifo_empty_MASK 0x00000400L -#define SC_DBG_REG_43__ps_pa2_sc_fifo_empty_MASK 0x00000800L -#define SC_DBG_REG_43__ps_pa3_sc_fifo_empty_MASK 0x00001000L -#define SC_DBG_REG_43__ta0_pm_quadff_empty_MASK 0x00002000L -#define SC_DBG_REG_43__ta1_pm_quadff_empty_MASK 0x00004000L -#define SC_DBG_REG_43__ta0_pm_dbquadff_empty_MASK 0x00008000L -#define SC_DBG_REG_43__ta1_pm_dbquadff_empty_MASK 0x00010000L -#define SC_DBG_REG_43__qp0_pm_tileff_empty_MASK 0x00020000L -#define SC_DBG_REG_43__qp1_pm_tileff_empty_MASK 0x00040000L -#define SC_DBG_REG_43__qp0_pm_dbtileff_empty_MASK 0x00080000L -#define SC_DBG_REG_43__qp1_pm_dbtileff_empty_MASK 0x00100000L -#define SC_DBG_REG_43__pff_bm_empty_MASK 0x00200000L -#define SC_DBG_REG_43__pw_bm_rtr_MASK 0x00400000L -#define SC_DBG_REG_43__pw_bm_rts_MASK 0x00800000L -#define SC_DBG_REG_43__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_44 -#define SC_DBG_REG_44__tp_qz_freeze_b_MASK 0x00000001L -#define SC_DBG_REG_44__ef_tp_event_MASK 0x00000002L -#define SC_DBG_REG_44__send_tile_MASK 0x00000004L -#define SC_DBG_REG_44__need_to_send_MASK 0x00000008L -#define SC_DBG_REG_44__num_sent_tiles_MASK 0x000000f0L -#define SC_DBG_REG_44__remaining_mask_MASK 0x00000100L -#define SC_DBG_REG_44__ef_tp_last_supertile_of_prim_MASK 0x00000200L -#define SC_DBG_REG_44__ef_tp_pass_empty_prim_MASK 0x00000400L -#define SC_DBG_REG_44__ef_tp_db_has_ordercull_entry_MASK 0x00000800L -#define SC_DBG_REG_44__ef_tp_db_has_last_tile_in_supertile_MASK 0x00001000L -#define SC_DBG_REG_44__last_supertile_of_prim_MASK 0x00002000L -#define SC_DBG_REG_44__last_tile_of_supertile_MASK 0x00004000L -#define SC_DBG_REG_44__s0_idle_MASK 0x00008000L -#define SC_DBG_REG_44__s1_idle_MASK 0x00010000L -#define SC_DBG_REG_44__s2_idle_MASK 0x00020000L -#define SC_DBG_REG_44__ef_tp_rts_and_n_ef_tp_rtr_MASK 0x00040000L -#define SC_DBG_REG_44__tp_qz_tile_rts_and_n_tp_qz_tile_rtr_MASK 0x00080000L -#define SC_DBG_REG_44__ef_keep_rts_and_n_ef_keep_rtr_MASK 0x00100000L -#define SC_DBG_REG_44__s0_rts_and_n_s0_rtr_MASK 0x00200000L -#define SC_DBG_REG_44__s1_rts_and_n_s1_rtr_MASK 0x00400000L -#define SC_DBG_REG_44__s2_rts_and_n_s2_rtr_MASK 0x00800000L -#define SC_DBG_REG_44__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_45 -#define SC_DBG_REG_45__z_tc_exp_MASK 0x000001ffL -#define SC_DBG_REG_45__qz_out_backface_MASK 0x00000200L -#define SC_DBG_REG_45__qm_db_id_MASK 0x00000c00L -#define SC_DBG_REG_45__qm_z_mask_needed_MASK 0x00001000L -#define SC_DBG_REG_45__qm_valid_MASK 0x00002000L -#define SC_DBG_REG_45__qm_covered_MASK 0x00004000L -#define SC_DBG_REG_45__qm_event_id_MASK 0x001f8000L -#define SC_DBG_REG_45__qm_event_MASK 0x00200000L -#define SC_DBG_REG_45__Reserved0_MASK 0xffc00000L - -// SC_DBG_REG_46 -#define SC_DBG_REG_46__qz_out_state_id_MASK 0x00000007L -#define SC_DBG_REG_46__qz_out_multi_sample_MASK 0x00000008L -#define SC_DBG_REG_46__int_freeze_b_MASK 0x00000010L -#define SC_DBG_REG_46__valid_MASK 0x00000020L -#define SC_DBG_REG_46__valid_out_MASK 0x00000040L -#define SC_DBG_REG_46__Reserved0_MASK 0xffffff80L - -// SC_DBG_REG_47 -#define SC_DBG_REG_47__r0_mask_MASK 0x0000ffffL -#define SC_DBG_REG_47__Reserved0_MASK 0xffff0000L - -// SC_DBG_REG_48 -#define SC_DBG_REG_48__r0_qd_picker_mask_MASK 0x000000ffL -#define SC_DBG_REG_48__Reserved0_MASK 0xffffff00L - -// SC_DBG_REG_49 -#define SC_DBG_REG_49__r0_mask_MASK 0x0000ffffL -#define SC_DBG_REG_49__r0_qd_picker_mask_MASK 0x00ff0000L -#define SC_DBG_REG_49__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_50 -#define SC_DBG_REG_50__r0_qd_picker_mask_MASK 0x000000ffL -#define SC_DBG_REG_50__Reserved0_MASK 0xffffff00L - -// SC_DBG_REG_51 -#define SC_DBG_REG_51__tilefifo_empty_MASK 0x00000001L -#define SC_DBG_REG_51__tilefifo_full_MASK 0x00000002L -#define SC_DBG_REG_51__tile_mask_fifo_empty_MASK 0x00000004L -#define SC_DBG_REG_51__tile_mask_fifo_full_MASK 0x00000008L -#define SC_DBG_REG_51__rslt_fifo_empty_MASK 0x00000010L -#define SC_DBG_REG_51__rslt_fifo_full_MASK 0x00000020L -#define SC_DBG_REG_51__pop_fifo_r0_MASK 0x00000040L -#define SC_DBG_REG_51__r0_last_tile_of_prim_MASK 0x00000080L -#define SC_DBG_REG_51__last_quad_MASK 0x00000100L -#define SC_DBG_REG_51__rslt_r0_SC_CR_MSAA_NUM_SAMPLES_MASK 0x00000e00L -#define SC_DBG_REG_51__rslt_r0_SC_CR_TILE_RATE_MASK 0x00001000L -#define SC_DBG_REG_51__rslt_r0_SC_CR_WOE_MASK 0x00002000L -#define SC_DBG_REG_51__rslt_r0_SC_CR_KILL_PIX_MASK 0x00004000L -#define SC_DBG_REG_51__rslt_r0_SC_TD_ZMASK_NEEDED_MASK 0x00008000L -#define SC_DBG_REG_51__qs_quad0_valid_MASK 0x00010000L -#define SC_DBG_REG_51__qs_quad1_valid_MASK 0x00020000L -#define SC_DBG_REG_51__qs_quad2_valid_MASK 0x00040000L -#define SC_DBG_REG_51__qs_quad3_valid_MASK 0x00080000L -#define SC_DBG_REG_51__qd_y_MASK 0x00300000L -#define SC_DBG_REG_51__qd_x_MASK 0x00c00000L -#define SC_DBG_REG_51__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_52 -#define SC_DBG_REG_52__r0_bit_cnt_MASK 0x0000001fL -#define SC_DBG_REG_52__Reserved0_MASK 0xffffffe0L - -// SC_DBG_REG_53 -#define SC_DBG_REG_53__squadfifo_empty_MASK 0x00000001L -#define SC_DBG_REG_53__squadfifo_full_MASK 0x00000002L -#define SC_DBG_REG_53__dbsc_quadfifo_empty_MASK 0x00000004L -#define SC_DBG_REG_53__dbsc_quadfifo_full_MASK 0x00000008L -#define SC_DBG_REG_53__quadfifo_empty_MASK 0x00000010L -#define SC_DBG_REG_53__quadfifo_full_MASK 0x00000020L -#define SC_DBG_REG_53__quadzfifo_empty_MASK 0x00000040L -#define SC_DBG_REG_53__quadzfifo_full_MASK 0x00000080L -#define SC_DBG_REG_53__Reserved0_MASK 0xffffff00L - -// SC_DBG_REG_54 -#define SC_DBG_REG_54__ta_tr_quadcnt_MASK 0x0000001fL -#define SC_DBG_REG_54__ta_tr_lasttile_MASK 0x00000020L -#define SC_DBG_REG_54__ta_tr_stateid_MASK 0x000001c0L -#define SC_DBG_REG_54__ta_tr_eventid_MASK 0x00007e00L -#define SC_DBG_REG_54__ta_tr_event_MASK 0x00008000L -#define SC_DBG_REG_54__ta_tr_rts_MASK 0x00010000L -#define SC_DBG_REG_54__ta_tr_rtr_MASK 0x00020000L -#define SC_DBG_REG_54__quads_rdy_MASK 0x00040000L -#define SC_DBG_REG_54__last_quad_MASK 0x00080000L -#define SC_DBG_REG_54__quad_cnt_MASK 0x00f00000L -#define SC_DBG_REG_54__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_55 -#define SC_DBG_REG_55__quad_cnt_5_MASK 0x00000001L -#define SC_DBG_REG_55__qp_rtr_MASK 0x00000002L -#define SC_DBG_REG_55__Reserved0_MASK 0xfffffffcL - -// SC_DBG_REG_56 -#define SC_DBG_REG_56__op_oc_0_push_MASK 0x00000001L -#define SC_DBG_REG_56__op_oc_0_dbid_MASK 0x00000006L -#define SC_DBG_REG_56__Reserved2_MASK 0x00000038L -#define SC_DBG_REG_56__n_op_oc_stall_MASK 0x00000040L -#define SC_DBG_REG_56__qp_oc_0_rts_MASK 0x00000080L -#define SC_DBG_REG_56__qp_oc_0_val_MASK 0x00000100L -#define SC_DBG_REG_56__qp_oc_0_rtr_MASK 0x00000200L -#define SC_DBG_REG_56__Reserved1_MASK 0x0000fc00L -#define SC_DBG_REG_56__qp_oc_1_rts_MASK 0x00010000L -#define SC_DBG_REG_56__qp_oc_1_val_MASK 0x00020000L -#define SC_DBG_REG_56__qp_oc_1_rtr_MASK 0x00040000L -#define SC_DBG_REG_56__Reserved0_MASK 0xfff80000L - -// SC_DBG_REG_57 -#define SC_DBG_REG_57__pre_cull_0_empty_MASK 0x00000001L -#define SC_DBG_REG_57__pre_cull_1_empty_MASK 0x00000002L -#define SC_DBG_REG_57__Reserved2_MASK 0x00000004L -#define SC_DBG_REG_57__pre_cull_1_full_MASK 0x00000008L -#define SC_DBG_REG_57__pre_cull_0_full_MASK 0x00000010L -#define SC_DBG_REG_57__cullrslt_0_empty_MASK 0x00000020L -#define SC_DBG_REG_57__cullrslt_0_full_MASK 0x00000040L -#define SC_DBG_REG_57__cullrslt_1_empty_MASK 0x00000080L -#define SC_DBG_REG_57__cullrslt_1_full_MASK 0x00000100L -#define SC_DBG_REG_57__Reserved1_MASK 0x00001e00L -#define SC_DBG_REG_57__pre_cull_0_dbid_MASK 0x00006000L -#define SC_DBG_REG_57__pre_cull_1_dbid_MASK 0x00018000L -#define SC_DBG_REG_57__Reserved0_MASK 0xfffe0000L - -// SC_DBG_REG_58 -#define SC_DBG_REG_58__post_cull_0_empty_MASK 0x00000001L -#define SC_DBG_REG_58__post_cull_1_empty_MASK 0x00000002L -#define SC_DBG_REG_58__Reserved1_MASK 0x0000000cL -#define SC_DBG_REG_58__post_cull_full_MASK 0x00000010L -#define SC_DBG_REG_58__oc_tr_0_rts_MASK 0x00000020L -#define SC_DBG_REG_58__oc_tr_0_dbid_MASK 0x000000c0L -#define SC_DBG_REG_58__oc_tr_0_rtr_MASK 0x00000100L -#define SC_DBG_REG_58__oc_tr_1_rts_MASK 0x00000200L -#define SC_DBG_REG_58__oc_tr_1_dbid_MASK 0x00000c00L -#define SC_DBG_REG_58__oc_tr_1_rtr_MASK 0x00001000L -#define SC_DBG_REG_58__Reserved0_MASK 0xffffe000L - -// SC_DBG_REG_59 -#define SC_DBG_REG_59__qfifo_re0_MASK 0x00000001L -#define SC_DBG_REG_59__qfifo_re1_MASK 0x00000002L -#define SC_DBG_REG_59__empty0_MASK 0x00000004L -#define SC_DBG_REG_59__empty1_MASK 0x00000008L -#define SC_DBG_REG_59__tr_pk_0_valid_MASK 0x00000010L -#define SC_DBG_REG_59__tr_pk_1_valid_MASK 0x00000020L -#define SC_DBG_REG_59__quad1_rtr_MASK 0x00000040L -#define SC_DBG_REG_59__quad0_rts_MASK 0x00000080L -#define SC_DBG_REG_59__quad1_rts_MASK 0x00000200L -#define SC_DBG_REG_59__quad0_drop_MASK 0x00000400L -#define SC_DBG_REG_59__quad1_drop_MASK 0x00000800L -#define SC_DBG_REG_59__quad0_ta0_qd0_rtr_MASK 0x00001000L -#define SC_DBG_REG_59__quad0_ta0_qd1_rtr_MASK 0x00002000L -#define SC_DBG_REG_59__quad0_ta1_qd0_rtr_MASK 0x00004000L -#define SC_DBG_REG_59__quad0_ta1_qd1_rtr_MASK 0x00008000L -#define SC_DBG_REG_59__quad1_ta0_qd0_rtr_MASK 0x00010000L -#define SC_DBG_REG_59__quad1_ta0_qd1_rtr_MASK 0x00020000L -#define SC_DBG_REG_59__quad1_ta1_qd0_rtr_MASK 0x00040000L -#define SC_DBG_REG_59__quad1_ta1_qd1_rtr_MASK 0x00080000L -#define SC_DBG_REG_59__quad0_import_z_MASK 0x00100000L -#define SC_DBG_REG_59__quad1_import_z_MASK 0x00200000L -#define SC_DBG_REG_59__quad0_stateid_1to0_MASK 0x00c00000L -#define SC_DBG_REG_59__Reserved0_MASK 0xff000000L - -// SC_DBG_REG_60 -#define SC_DBG_REG_60__quad0_stateid_2_MASK 0x00000001L -#define SC_DBG_REG_60__quad1_stateid_MASK 0x0000000eL -#define SC_DBG_REG_60__qfifo0_event_MASK 0x00000010L -#define SC_DBG_REG_60__qfifo1_event_MASK 0x00000020L -#define SC_DBG_REG_60__Reserved0_MASK 0xffffffc0L - -// SC_DBG_REG_61 -#define SC_DBG_REG_61__oc_tr_0_rts_and_n_oc_tr_0_rtr_MASK 0x00000001L -#define SC_DBG_REG_61__oc_tr_1_rts_and_n_oc_tr_1_rtr_MASK 0x00000002L -#define SC_DBG_REG_61__ta0_tr_rts_and_n_ta0_tr_rtr_MASK 0x00000004L -#define SC_DBG_REG_61__ta1_tr_rts_and_n_ta1_tr_rtr_MASK 0x00000008L -#define SC_DBG_REG_61__n_empty1_and_n_tr_pk_1_rtr_MASK 0x00000010L -#define SC_DBG_REG_61__n_empty0_and_n_tr_pk_0_rtr_MASK 0x00000020L -#define SC_DBG_REG_61__n_empty0_and_n_empty1_and_qfifo1_stall_MASK 0x00000040L -#define SC_DBG_REG_61__quad0_rts_and_n_quad0_rtr_MASK 0x00000080L -#define SC_DBG_REG_61__quad1_rts_and_n_quad1_rtr_MASK 0x00000100L -#define SC_DBG_REG_61__ta0_qd1_rts_and_n_ta0_qd1_rtr_MASK 0x00000200L -#define SC_DBG_REG_61__ta0_qd0_rts_and_n_ta0_qd0_rtr_MASK 0x00000400L -#define SC_DBG_REG_61__ta1_qd1_rts_and_n_ta1_qd1_rtr_MASK 0x00000800L -#define SC_DBG_REG_61__ta1_qd0_rts_and_n_ta1_qd0_rtr_MASK 0x00001000L -#define SC_DBG_REG_61__Reserved0_MASK 0xffffe000L - -// SC_DBG_REG_62 -#define SC_DBG_REG_62__ta0_tr_rts_MASK 0x00000001L -#define SC_DBG_REG_62__ta0_tr_event_MASK 0x00000002L -#define SC_DBG_REG_62__ta0_tr_eventid_MASK 0x000000fcL -#define SC_DBG_REG_62__ta0_tr_quadcnt_MASK 0x00001f00L -#define SC_DBG_REG_62__ta0_tr_lastquad_MASK 0x00002000L -#define SC_DBG_REG_62__ta0_tr_lasttile_MASK 0x00004000L -#define SC_DBG_REG_62__ta0_tr_rtr_MASK 0x00008000L -#define SC_DBG_REG_62__Reserved0_MASK 0xffff0000L - -// SC_DBG_REG_63 -#define SC_DBG_REG_63__ta1_tr_rts_MASK 0x00000001L -#define SC_DBG_REG_63__ta1_tr_event_MASK 0x00000002L -#define SC_DBG_REG_63__ta1_tr_eventid_MASK 0x000000fcL -#define SC_DBG_REG_63__ta1_tr_quadcnt_MASK 0x00001f00L -#define SC_DBG_REG_63__ta1_tr_lastquad_MASK 0x00002000L -#define SC_DBG_REG_63__ta1_tr_lasttile_MASK 0x00004000L -#define SC_DBG_REG_63__ta1_tr_rtr_MASK 0x00008000L -#define SC_DBG_REG_63__Reserved0_MASK 0xffff0000L - -// WD_DBG_REG_0 -#define WD_DBG_REG_0__wd_busy_extended_MASK 0x00000001L -#define WD_DBG_REG_0__wd_nodma_busy_extended_MASK 0x00000002L -#define WD_DBG_REG_0__wd_busy_MASK 0x00000004L -#define WD_DBG_REG_0__wd_nodma_busy_MASK 0x00000008L -#define WD_DBG_REG_0__rbiu_busy_MASK 0x00000010L -#define WD_DBG_REG_0__spl_dma_busy_MASK 0x00000020L -#define WD_DBG_REG_0__spl_di_busy_MASK 0x00000040L -#define WD_DBG_REG_0__vgt0_active_q_MASK 0x00000080L -#define WD_DBG_REG_0__vgt1_active_q_MASK 0x00000100L -#define WD_DBG_REG_0__spl_dma_p1_busy_MASK 0x00000200L -#define WD_DBG_REG_0__rbiu_dr_p1_fifo_busy_MASK 0x00000400L -#define WD_DBG_REG_0__rbiu_di_p1_fifo_busy_MASK 0x00000800L -#define WD_DBG_REG_0__Reserved2_MASK 0x00001000L -#define WD_DBG_REG_0__rbiu_dr_fifo_busy_MASK 0x00002000L -#define WD_DBG_REG_0__rbiu_spl_dr_valid_MASK 0x00004000L -#define WD_DBG_REG_0__spl_rbiu_dr_read_MASK 0x00008000L -#define WD_DBG_REG_0__Reserved1_MASK 0x00010000L -#define WD_DBG_REG_0__rbiu_di_fifo_busy_MASK 0x00020000L -#define WD_DBG_REG_0__rbiu_spl_di_valid_MASK 0x00040000L -#define WD_DBG_REG_0__spl_rbiu_di_read_MASK 0x00080000L -#define WD_DBG_REG_0__se0_synced_q_MASK 0x00100000L -#define WD_DBG_REG_0__se1_synced_q_MASK 0x00200000L -#define WD_DBG_REG_0__se2_synced_q_MASK 0x00400000L -#define WD_DBG_REG_0__se3_synced_q_MASK 0x00800000L -#define WD_DBG_REG_0__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_1 -#define WD_DBG_REG_1__reg_clk_busy_MASK 0x00000001L -#define WD_DBG_REG_1__input_clk_busy_MASK 0x00000002L -#define WD_DBG_REG_1__core_clk_busy_MASK 0x00000004L -#define WD_DBG_REG_1__vgt2_active_q_MASK 0x00000008L -#define WD_DBG_REG_1__sclk_reg_vld_MASK 0x00000010L -#define WD_DBG_REG_1__sclk_input_vld_MASK 0x00000020L -#define WD_DBG_REG_1__sclk_core_vld_MASK 0x00000040L -#define WD_DBG_REG_1__vgt3_active_q_MASK 0x00000080L -#define WD_DBG_REG_1__grbm_fifo_empty_MASK 0x00000100L -#define WD_DBG_REG_1__grbm_fifo_full_MASK 0x00000200L -#define WD_DBG_REG_1__grbm_fifo_we_MASK 0x00000400L -#define WD_DBG_REG_1__grbm_fifo_re_MASK 0x00000800L -#define WD_DBG_REG_1__draw_initiator_valid_q_MASK 0x00001000L -#define WD_DBG_REG_1__event_initiator_valid_q_MASK 0x00002000L -#define WD_DBG_REG_1__event_addr_valid_q_MASK 0x00004000L -#define WD_DBG_REG_1__dma_request_valid_q_MASK 0x00008000L -#define WD_DBG_REG_1__Reserved1_MASK 0x00010000L -#define WD_DBG_REG_1__min_indx_valid_q_MASK 0x00020000L -#define WD_DBG_REG_1__max_indx_valid_q_MASK 0x00040000L -#define WD_DBG_REG_1__indx_offset_valid_q_MASK 0x00080000L -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_0_MASK 0x00100000L -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_1_MASK 0x00200000L -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_2_MASK 0x00400000L -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_3_MASK 0x00800000L -#define WD_DBG_REG_1__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_2 -#define WD_DBG_REG_2__grbm_fifo_rdata_reg_id_4_MASK 0x00000001L -#define WD_DBG_REG_2__grbm_fifo_rdata_state_0_MASK 0x00000002L -#define WD_DBG_REG_2__grbm_fifo_rdata_state_1_MASK 0x00000004L -#define WD_DBG_REG_2__grbm_fifo_rdata_state_2_MASK 0x00000008L -#define WD_DBG_REG_2__free_cnt_q_0_MASK 0x00000010L -#define WD_DBG_REG_2__free_cnt_q_1_MASK 0x00000020L -#define WD_DBG_REG_2__free_cnt_q_2_MASK 0x00000040L -#define WD_DBG_REG_2__free_cnt_q_3_MASK 0x00000080L -#define WD_DBG_REG_2__free_cnt_q_4_MASK 0x00000100L -#define WD_DBG_REG_2__free_cnt_q_5_MASK 0x00000200L -#define WD_DBG_REG_2__rbiu_di_fifo_we_MASK 0x00000400L -#define WD_DBG_REG_2__rbiu_dr_fifo_we_MASK 0x00000800L -#define WD_DBG_REG_2__rbiu_di_fifo_empty_MASK 0x00001000L -#define WD_DBG_REG_2__rbiu_di_fifo_full_MASK 0x00002000L -#define WD_DBG_REG_2__rbiu_dr_fifo_empty_MASK 0x00004000L -#define WD_DBG_REG_2__rbiu_dr_fifo_full_MASK 0x00008000L -#define WD_DBG_REG_2__p1_grbm_fifo_empty_MASK 0x00010000L -#define WD_DBG_REG_2__p1_grbm_fifo_full_MASK 0x00020000L -#define WD_DBG_REG_2__p1_grbm_fifo_we_MASK 0x00040000L -#define WD_DBG_REG_2__p1_grbm_fifo_re_MASK 0x00080000L -#define WD_DBG_REG_2__p1_draw_initiator_valid_q_MASK 0x00100000L -#define WD_DBG_REG_2__p1_event_initiator_valid_q_MASK 0x00200000L -#define WD_DBG_REG_2__p1_event_addr_valid_q_MASK 0x00400000L -#define WD_DBG_REG_2__p1_dma_request_valid_q_MASK 0x00800000L -#define WD_DBG_REG_2__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_3 -#define WD_DBG_REG_3__Reserved1_MASK 0x00000001L -#define WD_DBG_REG_3__p1_min_indx_valid_q_MASK 0x00000002L -#define WD_DBG_REG_3__p1_max_indx_valid_q_MASK 0x00000004L -#define WD_DBG_REG_3__p1_indx_offset_valid_q_MASK 0x00000008L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_0_MASK 0x00000010L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_1_MASK 0x00000020L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_2_MASK 0x00000040L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_3_MASK 0x00000080L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_4_MASK 0x00000100L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_state_5_MASK 0x00000200L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_state_6_MASK 0x00000400L -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_state_7_MASK 0x00000800L -#define WD_DBG_REG_3__p1_free_cnt_q_0_MASK 0x00001000L -#define WD_DBG_REG_3__p1_free_cnt_q_1_MASK 0x00002000L -#define WD_DBG_REG_3__p1_free_cnt_q_2_MASK 0x00004000L -#define WD_DBG_REG_3__p1_free_cnt_q_3_MASK 0x00008000L -#define WD_DBG_REG_3__p1_free_cnt_q_4_MASK 0x00010000L -#define WD_DBG_REG_3__p1_free_cnt_q_5_MASK 0x00020000L -#define WD_DBG_REG_3__p1_rbiu_di_fifo_we_MASK 0x00040000L -#define WD_DBG_REG_3__p1_rbiu_dr_fifo_we_MASK 0x00080000L -#define WD_DBG_REG_3__p1_rbiu_di_fifo_empty_MASK 0x00100000L -#define WD_DBG_REG_3__p1_rbiu_di_fifo_full_MASK 0x00200000L -#define WD_DBG_REG_3__p1_rbiu_dr_fifo_empty_MASK 0x00400000L -#define WD_DBG_REG_3__p1_rbiu_dr_fifo_full_MASK 0x00800000L -#define WD_DBG_REG_3__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_4 -#define WD_DBG_REG_4__rbiu_spl_dr_valid_MASK 0x00000001L -#define WD_DBG_REG_4__Reserved1_MASK 0x00000002L -#define WD_DBG_REG_4__pipe0_dr_MASK 0x00000004L -#define WD_DBG_REG_4__pipe0_rtr_MASK 0x00000008L -#define WD_DBG_REG_4__pipe1_dr_MASK 0x00000010L -#define WD_DBG_REG_4__pipe1_rtr_MASK 0x00000020L -#define WD_DBG_REG_4__wd_subdma_fifo_empty_MASK 0x00000040L -#define WD_DBG_REG_4__wd_subdma_fifo_full_MASK 0x00000080L -#define WD_DBG_REG_4__dma_buf_type_p0_q_0_MASK 0x00000100L -#define WD_DBG_REG_4__dma_buf_type_p0_q_1_MASK 0x00000200L -#define WD_DBG_REG_4__dma_zero_indices_p0_q_MASK 0x00000400L -#define WD_DBG_REG_4__dma_req_path_p3_q_MASK 0x00000800L -#define WD_DBG_REG_4__dma_not_eop_p1_q_MASK 0x00001000L -#define WD_DBG_REG_4__out_of_range_p4_MASK 0x00002000L -#define WD_DBG_REG_4__last_sub_dma_p3_q_MASK 0x00004000L -#define WD_DBG_REG_4__last_rdreq_of_sub_dma_p4_MASK 0x00008000L -#define WD_DBG_REG_4__WD_IA_dma_send_d_MASK 0x00010000L -#define WD_DBG_REG_4__WD_IA_dma_rtr_MASK 0x00020000L -#define WD_DBG_REG_4__WD_IA1_dma_send_d_MASK 0x00040000L -#define WD_DBG_REG_4__WD_IA1_dma_rtr_MASK 0x00080000L -#define WD_DBG_REG_4__last_inst_of_dma_p2_MASK 0x00100000L -#define WD_DBG_REG_4__last_sd_of_inst_p2_MASK 0x00200000L -#define WD_DBG_REG_4__last_sd_of_dma_p2_MASK 0x00400000L -#define WD_DBG_REG_4__Reserved0_MASK 0x80000000L - -// WD_DBG_REG_5 -#define WD_DBG_REG_5__WD_IA_dma_busy_MASK 0x00000001L -#define WD_DBG_REG_5__WD_IA1_dma_busy_MASK 0x00000002L -#define WD_DBG_REG_5__send_to_ia1_p3_q_MASK 0x00000004L -#define WD_DBG_REG_5__dma_wd_switch_on_eop_p3_q_MASK 0x00000008L -#define WD_DBG_REG_5__pipe3_dr_MASK 0x00000010L -#define WD_DBG_REG_5__pipe3_rtr_MASK 0x00000020L -#define WD_DBG_REG_5__wd_dma2draw_fifo_empty_MASK 0x00000040L -#define WD_DBG_REG_5__wd_dma2draw_fifo_full_MASK 0x00000080L -#define WD_DBG_REG_5__rbiu_spl_di_valid_MASK 0x00000100L -#define WD_DBG_REG_5__spl_rbiu_di_read_MASK 0x00000200L -#define WD_DBG_REG_5__rbiu_spl_p1_di_valid_MASK 0x00000400L -#define WD_DBG_REG_5__spl_rbiu_p1_di_read_MASK 0x00000800L -#define WD_DBG_REG_5__pipe0_dr_MASK 0x00001000L -#define WD_DBG_REG_5__pipe0_rtr_MASK 0x00002000L -#define WD_DBG_REG_5__pipe1_dr_MASK 0x00004000L -#define WD_DBG_REG_5__pipe1_rtr_MASK 0x00008000L -#define WD_DBG_REG_5__pipe2_dr_MASK 0x00010000L -#define WD_DBG_REG_5__pipe2_rtr_MASK 0x00020000L -#define WD_DBG_REG_5__pipe3_ld_MASK 0x00040000L -#define WD_DBG_REG_5__WD_IA_draw_send_d_MASK 0x00100000L -#define WD_DBG_REG_5__WD_IA_draw_rtr_MASK 0x00200000L -#define WD_DBG_REG_5__di_type_p0_0_MASK 0x00400000L -#define WD_DBG_REG_5__di_type_p0_1_MASK 0x00800000L -#define WD_DBG_REG_5__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_6 -#define WD_DBG_REG_6__di_state_sel_p1_q_0_MASK 0x00000001L -#define WD_DBG_REG_6__di_state_sel_p1_q_1_MASK 0x00000002L -#define WD_DBG_REG_6__di_state_sel_p1_q_2_MASK 0x00000004L -#define WD_DBG_REG_6__di_wd_switch_on_eop_p1_q_MASK 0x00000008L -#define WD_DBG_REG_6__rbiu_spl_pipe0_lockout_MASK 0x00000010L -#define WD_DBG_REG_6__last_inst_of_di_p2_MASK 0x00000020L -#define WD_DBG_REG_6__last_sd_of_inst_p2_MASK 0x00000040L -#define WD_DBG_REG_6__last_sd_of_di_p2_MASK 0x00000080L -#define WD_DBG_REG_6__not_eop_wait_p1_q_MASK 0x00000100L -#define WD_DBG_REG_6__not_eop_wait_q_MASK 0x00000200L -#define WD_DBG_REG_6__ext_event_wait_p1_q_MASK 0x00000400L -#define WD_DBG_REG_6__ext_event_wait_q_MASK 0x00000800L -#define WD_DBG_REG_6__WD_IA1_draw_send_d_MASK 0x00001000L -#define WD_DBG_REG_6__WD_IA1_draw_rtr_MASK 0x00002000L -#define WD_DBG_REG_6__send_to_ia1_q_MASK 0x00004000L -#define WD_DBG_REG_6__dual_ia_mode_MASK 0x00008000L -#define WD_DBG_REG_6__p1_rbiu_spl_dr_valid_MASK 0x00010000L -#define WD_DBG_REG_6__Reserved1_MASK 0x00020000L -#define WD_DBG_REG_6__p1_pipe0_dr_MASK 0x00040000L -#define WD_DBG_REG_6__p1_pipe0_rtr_MASK 0x00080000L -#define WD_DBG_REG_6__p1_pipe1_dr_MASK 0x00100000L -#define WD_DBG_REG_6__p1_pipe1_rtr_MASK 0x00200000L -#define WD_DBG_REG_6__p1_wd_subdma_fifo_empty_MASK 0x00400000L -#define WD_DBG_REG_6__p1_wd_subdma_fifo_full_MASK 0x00800000L -#define WD_DBG_REG_6__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_7 -#define WD_DBG_REG_7__p1_dma_buf_type_p0_q_0_MASK 0x00000001L -#define WD_DBG_REG_7__p1_dma_buf_type_p0_q_1_MASK 0x00000002L -#define WD_DBG_REG_7__p1_dma_zero_indices_p0_q_MASK 0x00000004L -#define WD_DBG_REG_7__p1_dma_req_path_p3_q_MASK 0x00000008L -#define WD_DBG_REG_7__p1_dma_not_eop_p1_q_MASK 0x00000010L -#define WD_DBG_REG_7__p1_out_of_range_p4_MASK 0x00000020L -#define WD_DBG_REG_7__p1_last_sub_dma_p3_q_MASK 0x00000040L -#define WD_DBG_REG_7__p1_last_rdreq_of_sub_dma_p4_MASK 0x00000080L -#define WD_DBG_REG_7__p1_WD_IA_dma_send_d_MASK 0x00000100L -#define WD_DBG_REG_7__p1_WD_IA_dma_rtr_MASK 0x00000200L -#define WD_DBG_REG_7__p1_WD_IA1_dma_send_d_MASK 0x00000400L -#define WD_DBG_REG_7__p1_WD_IA1_dma_rtr_MASK 0x00000800L -#define WD_DBG_REG_7__p1_last_inst_of_dma_p2_MASK 0x00001000L -#define WD_DBG_REG_7__p1_last_sd_of_inst_p2_MASK 0x00002000L -#define WD_DBG_REG_7__p1_last_sd_of_dma_p2_MASK 0x00004000L -#define WD_DBG_REG_7__Reserved1_MASK 0x00008000L -#define WD_DBG_REG_7__p1_WD_IA_dma_busy_MASK 0x00010000L -#define WD_DBG_REG_7__p1_WD_IA1_dma_busy_MASK 0x00020000L -#define WD_DBG_REG_7__p1_send_to_ia1_p3_q_MASK 0x00040000L -#define WD_DBG_REG_7__p1_dma_wd_switch_on_eop_p3_q_MASK 0x00080000L -#define WD_DBG_REG_7__p1_pipe3_dr_MASK 0x00100000L -#define WD_DBG_REG_7__p1_pipe3_rtr_MASK 0x00200000L -#define WD_DBG_REG_7__p1_wd_dma2draw_fifo_empty_MASK 0x00400000L -#define WD_DBG_REG_7__p1_wd_dma2draw_fifo_full_MASK 0x00800000L -#define WD_DBG_REG_7__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_8 -#define WD_DBG_REG_8__Reserved16_MASK 0x00000001L -#define WD_DBG_REG_8__Reserved15_MASK 0x00000002L -#define WD_DBG_REG_8__Reserved14_MASK 0x00000004L -#define WD_DBG_REG_8__Reserved13_MASK 0x00000008L -#define WD_DBG_REG_8__Reserved12_MASK 0x00000010L -#define WD_DBG_REG_8__Reserved11_MASK 0x00000020L -#define WD_DBG_REG_8__Reserved10_MASK 0x00000040L -#define WD_DBG_REG_8__Reserved9_MASK 0x00000080L -#define WD_DBG_REG_8__Reserved8_MASK 0x00000100L -#define WD_DBG_REG_8__Reserved7_MASK 0x00000200L -#define WD_DBG_REG_8__Reserved6_MASK 0x00000400L -#define WD_DBG_REG_8__Reserved5_MASK 0x00000800L -#define WD_DBG_REG_8__Reserved4_MASK 0x00001000L -#define WD_DBG_REG_8__Reserved3_MASK 0x00002000L -#define WD_DBG_REG_8__Reserved2_MASK 0x00004000L -#define WD_DBG_REG_8__Reserved1_MASK 0x00008000L -#define WD_DBG_REG_8__WD_IA_draw_eop_0_MASK 0x00010000L -#define WD_DBG_REG_8__WD_IA_draw_eop_1_MASK 0x00020000L -#define WD_DBG_REG_8__WD_IA_draw_eop_2_MASK 0x00040000L -#define WD_DBG_REG_8__WD_IA_draw_eop_3_MASK 0x00080000L -#define WD_DBG_REG_8__WD_IA_draw_eop_4_MASK 0x00100000L -#define WD_DBG_REG_8__WD_IA_draw_eop_5_MASK 0x00200000L -#define WD_DBG_REG_8__WD_IA_draw_eop_6_MASK 0x00400000L -#define WD_DBG_REG_8__WD_IA_draw_eop_7_MASK 0x00800000L -#define WD_DBG_REG_8__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_9 -#define WD_DBG_REG_9__WD_IA_draw_eop_8_MASK 0x00000001L -#define WD_DBG_REG_9__WD_IA_draw_eop_9_MASK 0x00000002L -#define WD_DBG_REG_9__WD_IA_draw_eop_10_MASK 0x00000004L -#define WD_DBG_REG_9__WD_IA_draw_eop_11_MASK 0x00000008L -#define WD_DBG_REG_9__WD_IA_draw_eop_12_MASK 0x00000010L -#define WD_DBG_REG_9__WD_IA_draw_eop_13_MASK 0x00000020L -#define WD_DBG_REG_9__WD_IA_draw_eop_14_MASK 0x00000040L -#define WD_DBG_REG_9__WD_IA_draw_eop_15_MASK 0x00000080L -#define WD_DBG_REG_9__WD_IA_draw_eop_16_MASK 0x00000100L -#define WD_DBG_REG_9__WD_IA_draw_eop_17_MASK 0x00000200L -#define WD_DBG_REG_9__WD_IA_draw_eop_18_MASK 0x00000400L -#define WD_DBG_REG_9__WD_IA_draw_eop_19_MASK 0x00000800L -#define WD_DBG_REG_9__WD_IA_draw_eop_20_MASK 0x00001000L -#define WD_DBG_REG_9__WD_IA_draw_eop_21_MASK 0x00002000L -#define WD_DBG_REG_9__WD_IA_draw_eop_22_MASK 0x00004000L -#define WD_DBG_REG_9__WD_IA_draw_eop_23_MASK 0x00008000L -#define WD_DBG_REG_9__WD_IA_draw_eop_24_MASK 0x00010000L -#define WD_DBG_REG_9__WD_IA_draw_eop_25_MASK 0x00020000L -#define WD_DBG_REG_9__WD_IA_draw_eop_26_MASK 0x00040000L -#define WD_DBG_REG_9__WD_IA_draw_eop_27_MASK 0x00080000L -#define WD_DBG_REG_9__WD_IA_draw_eop_28_MASK 0x00100000L -#define WD_DBG_REG_9__WD_IA_draw_eop_29_MASK 0x00200000L -#define WD_DBG_REG_9__WD_IA_draw_eop_30_MASK 0x00400000L -#define WD_DBG_REG_9__WD_IA_draw_eop_31_MASK 0x00800000L -#define WD_DBG_REG_9__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_10 -#define WD_DBG_REG_10__SE0VGT_WD_thdgrp_send_in_MASK 0x00000001L -#define WD_DBG_REG_10__wd_arb_se0_input_fifo_re_MASK 0x00000002L -#define WD_DBG_REG_10__wd_arb_se0_input_fifo_empty_MASK 0x00000004L -#define WD_DBG_REG_10__wd_arb_se0_input_fifo_full_MASK 0x00000008L -#define WD_DBG_REG_10__SE1VGT_WD_thdgrp_send_in_MASK 0x00000010L -#define WD_DBG_REG_10__wd_arb_se1_input_fifo_re_MASK 0x00000020L -#define WD_DBG_REG_10__wd_arb_se1_input_fifo_empty_MASK 0x00000040L -#define WD_DBG_REG_10__wd_arb_se1_input_fifo_full_MASK 0x00000080L -#define WD_DBG_REG_10__SE2VGT_WD_thdgrp_send_in_MASK 0x00000100L -#define WD_DBG_REG_10__wd_arb_se2_input_fifo_re_MASK 0x00000200L -#define WD_DBG_REG_10__wd_arb_se2_input_fifo_empty_MASK 0x00000400L -#define WD_DBG_REG_10__wd_arb_se2_input_fifo_full_MASK 0x00000800L -#define WD_DBG_REG_10__SE3VGT_WD_thdgrp_send_in_MASK 0x00001000L -#define WD_DBG_REG_10__wd_arb_se3_input_fifo_re_MASK 0x00002000L -#define WD_DBG_REG_10__wd_arb_se3_input_fifo_empty_MASK 0x00004000L -#define WD_DBG_REG_10__wd_arb_se3_input_fifo_full_MASK 0x00008000L -#define WD_DBG_REG_10__te11_arb_state_q_0_MASK 0x00010000L -#define WD_DBG_REG_10__te11_arb_state_q_1_MASK 0x00020000L -#define WD_DBG_REG_10__te11_arb_state_q_2_MASK 0x00040000L -#define WD_DBG_REG_10__Reserved1_MASK 0x00080000L -#define WD_DBG_REG_10__se0_thdgrp_is_event_MASK 0x00100000L -#define WD_DBG_REG_10__se0_thdgrp_eop_MASK 0x00200000L -#define WD_DBG_REG_10__se1_thdgrp_is_event_MASK 0x00400000L -#define WD_DBG_REG_10__se1_thdgrp_eop_MASK 0x00800000L -#define WD_DBG_REG_10__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_11 -#define WD_DBG_REG_11__se2_thdgrp_is_event_MASK 0x00000001L -#define WD_DBG_REG_11__se2_thdgrp_eop_MASK 0x00000002L -#define WD_DBG_REG_11__se3_thdgrp_is_event_MASK 0x00000004L -#define WD_DBG_REG_11__se3_thdgrp_eop_MASK 0x00000008L -#define WD_DBG_REG_11__tfreq_arb_tgroup_rtr_MASK 0x00000010L -#define WD_DBG_REG_11__arb_tfreq_tgroup_rts_MASK 0x00000020L -#define WD_DBG_REG_11__arb_tfreq_tgroup_event_MASK 0x00000040L -#define WD_DBG_REG_11__te11_arb_busy_MASK 0x00000080L -#define WD_DBG_REG_11__pipe0_dr_MASK 0x00000100L -#define WD_DBG_REG_11__pipe1_dr_MASK 0x00000200L -#define WD_DBG_REG_11__pipe0_rtr_MASK 0x00000400L -#define WD_DBG_REG_11__pipe1_rtr_MASK 0x00000800L -#define WD_DBG_REG_11__tfreq_tg_fifo_empty_MASK 0x00001000L -#define WD_DBG_REG_11__tfreq_tg_fifo_full_MASK 0x00002000L -#define WD_DBG_REG_11__tf_data_fifo_busy_q_MASK 0x00004000L -#define WD_DBG_REG_11__tf_data_fifo_rtr_q_MASK 0x00008000L -#define WD_DBG_REG_11__tf_skid_fifo_empty_MASK 0x00010000L -#define WD_DBG_REG_11__tf_skid_fifo_full_MASK 0x00020000L -#define WD_DBG_REG_11__wd_tc_rdreq_rtr_q_MASK 0x00040000L -#define WD_DBG_REG_11__last_req_of_tg_p2_MASK 0x00080000L -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_0_MASK 0x00100000L -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_1_MASK 0x00200000L -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_2_MASK 0x00400000L -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_3_MASK 0x00800000L -#define WD_DBG_REG_11__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_12 -#define WD_DBG_REG_12__se0spi_wd_hs_done_cnt_q_4_MASK 0x00000001L -#define WD_DBG_REG_12__se0spi_wd_hs_done_cnt_q_5_MASK 0x00000002L -#define WD_DBG_REG_12__event_flag_p1_q_MASK 0x00000004L -#define WD_DBG_REG_12__null_flag_p1_q_MASK 0x00000008L -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_0_MASK 0x00000010L -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_1_MASK 0x00000020L -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_2_MASK 0x00000040L -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_3_MASK 0x00000080L -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_4_MASK 0x00000100L -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_5_MASK 0x00000200L -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_6_MASK 0x00000400L -#define WD_DBG_REG_12__second_tf_ret_data_q_MASK 0x00000800L -#define WD_DBG_REG_12__first_req_of_tg_p1_q_MASK 0x00001000L -#define WD_DBG_REG_12__WD_TC_rdreq_send_out_MASK 0x00002000L -#define WD_DBG_REG_12__WD_TC_rdnfo_stall_out_MASK 0x00004000L -#define WD_DBG_REG_12__TC_WD_rdret_valid_in_MASK 0x00008000L -#define WD_DBG_REG_12__pipe0_dr_MASK 0x00010000L -#define WD_DBG_REG_12__pipec_tf_dr_MASK 0x00020000L -#define WD_DBG_REG_12__pipe2_dr_MASK 0x00040000L -#define WD_DBG_REG_12__event_or_null_flags_p0_q_MASK 0x00080000L -#define WD_DBG_REG_12__pipe0_rtr_MASK 0x00100000L -#define WD_DBG_REG_12__pipe1_rtr_MASK 0x00200000L -#define WD_DBG_REG_12__pipec_tf_rtr_MASK 0x00400000L -#define WD_DBG_REG_12__pipe2_rtr_MASK 0x00800000L -#define WD_DBG_REG_12__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_13 -#define WD_DBG_REG_13__ttp_patch_fifo_full_MASK 0x00000001L -#define WD_DBG_REG_13__ttp_patch_fifo_empty_MASK 0x00000002L -#define WD_DBG_REG_13__ttp_tf_fifo_empty_MASK 0x00000004L -#define WD_DBG_REG_13__Reserved8_MASK 0x00000008L -#define WD_DBG_REG_13__Reserved7_MASK 0x00000010L -#define WD_DBG_REG_13__Reserved6_MASK 0x00000020L -#define WD_DBG_REG_13__Reserved5_MASK 0x00000040L -#define WD_DBG_REG_13__Reserved4_MASK 0x00000080L -#define WD_DBG_REG_13__tf_fetch_state_q_0_MASK 0x00000100L -#define WD_DBG_REG_13__tf_fetch_state_q_1_MASK 0x00000200L -#define WD_DBG_REG_13__tf_fetch_state_q_2_MASK 0x00000400L -#define WD_DBG_REG_13__last_patch_of_tg_MASK 0x00000800L -#define WD_DBG_REG_13__tf_pointer_p0_q_0_MASK 0x00001000L -#define WD_DBG_REG_13__tf_pointer_p0_q_1_MASK 0x00002000L -#define WD_DBG_REG_13__tf_pointer_p0_q_2_MASK 0x00004000L -#define WD_DBG_REG_13__tf_pointer_p0_q_3_MASK 0x00008000L -#define WD_DBG_REG_13__dynamic_hs_p0_q_MASK 0x00010000L -#define WD_DBG_REG_13__first_fetch_of_tg_p0_q_MASK 0x00020000L -#define WD_DBG_REG_13__mem_is_even_MASK 0x00040000L -#define WD_DBG_REG_13__Reserved3_MASK 0x00080000L -#define WD_DBG_REG_13__Reserved2_MASK 0x00100000L -#define WD_DBG_REG_13__Reserved1_MASK 0x00200000L -#define WD_DBG_REG_13__pipe4_dr_MASK 0x00400000L -#define WD_DBG_REG_13__pipe4_rtr_MASK 0x00800000L -#define WD_DBG_REG_13__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_14 -#define WD_DBG_REG_14__ttp_pd_patch_rts_MASK 0x00000001L -#define WD_DBG_REG_14__ttp_pd_is_event_MASK 0x00000002L -#define WD_DBG_REG_14__ttp_pd_eopg_MASK 0x00000004L -#define WD_DBG_REG_14__ttp_pd_eop_MASK 0x00000008L -#define WD_DBG_REG_14__pipe0_dr_MASK 0x00000010L -#define WD_DBG_REG_14__pipe1_dr_MASK 0x00000020L -#define WD_DBG_REG_14__pipe0_rtr_MASK 0x00000040L -#define WD_DBG_REG_14__pipe1_rtr_MASK 0x00000080L -#define WD_DBG_REG_14__donut_en_p1_q_MASK 0x00000100L -#define WD_DBG_REG_14__donut_se_switch_p2_MASK 0x00000200L -#define WD_DBG_REG_14__patch_se_switch_p2_MASK 0x00000400L -#define WD_DBG_REG_14__last_donut_switch_p2_MASK 0x00000800L -#define WD_DBG_REG_14__last_donut_of_patch_p2_MASK 0x00001000L -#define WD_DBG_REG_14__is_event_p1_q_MASK 0x00002000L -#define WD_DBG_REG_14__eopg_p1_q_MASK 0x00004000L -#define WD_DBG_REG_14__eop_p1_q_MASK 0x00008000L -#define WD_DBG_REG_14__patch_accum_q_0_MASK 0x00010000L -#define WD_DBG_REG_14__patch_accum_q_1_MASK 0x00020000L -#define WD_DBG_REG_14__patch_accum_q_2_MASK 0x00040000L -#define WD_DBG_REG_14__patch_accum_q_3_MASK 0x00080000L -#define WD_DBG_REG_14__patch_accum_q_4_MASK 0x00100000L -#define WD_DBG_REG_14__patch_accum_q_5_MASK 0x00200000L -#define WD_DBG_REG_14__patch_accum_q_6_MASK 0x00400000L -#define WD_DBG_REG_14__patch_accum_q_7_MASK 0x00800000L -#define WD_DBG_REG_14__Reserved0_MASK 0xff000000L - -// WD_DBG_REG_15 -#define WD_DBG_REG_15__wd_te11_out_se0_fifo_full_MASK 0x00000001L -#define WD_DBG_REG_15__wd_te11_out_se0_fifo_empty_MASK 0x00000002L -#define WD_DBG_REG_15__wd_te11_out_se1_fifo_full_MASK 0x00000004L -#define WD_DBG_REG_15__wd_te11_out_se1_fifo_empty_MASK 0x00000008L -#define WD_DBG_REG_15__wd_te11_out_se2_fifo_full_MASK 0x00000010L -#define WD_DBG_REG_15__wd_te11_out_se2_fifo_empty_MASK 0x00000020L -#define WD_DBG_REG_15__wd_te11_out_se3_fifo_full_MASK 0x00000040L -#define WD_DBG_REG_15__wd_te11_out_se3_fifo_empty_MASK 0x00000080L -#define WD_DBG_REG_15__Reserved15_MASK 0x00000100L -#define WD_DBG_REG_15__Reserved14_MASK 0x00000200L -#define WD_DBG_REG_15__Reserved13_MASK 0x00000400L -#define WD_DBG_REG_15__Reserved12_MASK 0x00000800L -#define WD_DBG_REG_15__Reserved11_MASK 0x00001000L -#define WD_DBG_REG_15__Reserved10_MASK 0x00002000L -#define WD_DBG_REG_15__Reserved9_MASK 0x00004000L -#define WD_DBG_REG_15__Reserved8_MASK 0x00008000L -#define WD_DBG_REG_15__Reserved7_MASK 0x00010000L -#define WD_DBG_REG_15__Reserved6_MASK 0x00020000L -#define WD_DBG_REG_15__Reserved5_MASK 0x00040000L -#define WD_DBG_REG_15__Reserved4_MASK 0x00080000L -#define WD_DBG_REG_15__Reserved3_MASK 0x00100000L -#define WD_DBG_REG_15__Reserved2_MASK 0x00200000L -#define WD_DBG_REG_15__Reserved1_MASK 0x00400000L -#define WD_DBG_REG_15__Reserved0_MASK 0x80000000L - -// IA_DBG_REG_0 -#define IA_DBG_REG_0__ia_busy_extended_MASK 0x00000001L -#define IA_DBG_REG_0__ia_nodma_busy_extended_MASK 0x00000002L -#define IA_DBG_REG_0__ia_busy_MASK 0x00000004L -#define IA_DBG_REG_0__ia_nodma_busy_MASK 0x00000008L -#define IA_DBG_REG_0__Reserved11_MASK 0x00000010L -#define IA_DBG_REG_0__dma_req_busy_MASK 0x00000020L -#define IA_DBG_REG_0__dma_busy_MASK 0x00000040L -#define IA_DBG_REG_0__mc_xl8r_busy_MASK 0x00000080L -#define IA_DBG_REG_0__grp_busy_MASK 0x00000100L -#define IA_DBG_REG_0__Reserved10_MASK 0x00000200L -#define IA_DBG_REG_0__dma_grp_valid_MASK 0x00000400L -#define IA_DBG_REG_0__grp_dma_read_MASK 0x00000800L -#define IA_DBG_REG_0__dma_grp_hp_valid_MASK 0x00001000L -#define IA_DBG_REG_0__grp_dma_hp_read_MASK 0x00002000L -#define IA_DBG_REG_0__Reserved9_MASK 0x00004000L -#define IA_DBG_REG_0__Reserved8_MASK 0x00008000L -#define IA_DBG_REG_0__Reserved7_MASK 0x00010000L -#define IA_DBG_REG_0__Reserved6_MASK 0x00020000L -#define IA_DBG_REG_0__Reserved5_MASK 0x00040000L -#define IA_DBG_REG_0__Reserved4_MASK 0x00080000L -#define IA_DBG_REG_0__Reserved3_MASK 0x00100000L -#define IA_DBG_REG_0__Reserved2_MASK 0x00200000L -#define IA_DBG_REG_0__Reserved1_MASK 0x00400000L -#define IA_DBG_REG_0__Reserved0_MASK 0x80000000L - -// IA_DBG_REG_1 -#define IA_DBG_REG_1__reg_clk_busy_MASK 0x00000001L -#define IA_DBG_REG_1__core_clk_busy_MASK 0x00000002L -#define IA_DBG_REG_1__Reserved4_MASK 0x00000004L -#define IA_DBG_REG_1__Reserved3_MASK 0x00000008L -#define IA_DBG_REG_1__sclk_reg_vld_MASK 0x00000010L -#define IA_DBG_REG_1__sclk_core_vld_MASK 0x00000020L -#define IA_DBG_REG_1__Reserved2_MASK 0x00000040L -#define IA_DBG_REG_1__Reserved1_MASK 0x00000080L -#define IA_DBG_REG_1__dma_input_fifo_empty_MASK 0x00000100L -#define IA_DBG_REG_1__dma_input_fifo_full_MASK 0x00000200L -#define IA_DBG_REG_1__start_new_packet_MASK 0x00000400L -#define IA_DBG_REG_1__dma_rdreq_dr_q_MASK 0x00000800L -#define IA_DBG_REG_1__dma_zero_indices_q_MASK 0x00001000L -#define IA_DBG_REG_1__dma_buf_type_q_MASK 0x00002000L -#define IA_DBG_REG_1__dma_req_path_q_MASK 0x00008000L -#define IA_DBG_REG_1__discard_1st_chunk_MASK 0x00010000L -#define IA_DBG_REG_1__discard_2nd_chunk_MASK 0x00020000L -#define IA_DBG_REG_1__second_tc_ret_data_q_MASK 0x00040000L -#define IA_DBG_REG_1__dma_tc_ret_sel_q_MASK 0x00080000L -#define IA_DBG_REG_1__last_rdreq_in_dma_op_MASK 0x00100000L -#define IA_DBG_REG_1__dma_mask_fifo_empty_MASK 0x00200000L -#define IA_DBG_REG_1__dma_data_fifo_empty_q_MASK 0x00400000L -#define IA_DBG_REG_1__dma_data_fifo_full_MASK 0x00800000L -#define IA_DBG_REG_1__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_2 -#define IA_DBG_REG_2__dma_req_fifo_empty_MASK 0x00000001L -#define IA_DBG_REG_2__dma_req_fifo_full_MASK 0x00000002L -#define IA_DBG_REG_2__stage2_dr_MASK 0x00000004L -#define IA_DBG_REG_2__stage2_rtr_MASK 0x00000008L -#define IA_DBG_REG_2__stage3_dr_MASK 0x00000010L -#define IA_DBG_REG_2__stage3_rtr_MASK 0x00000020L -#define IA_DBG_REG_2__stage4_dr_MASK 0x00000040L -#define IA_DBG_REG_2__stage4_rtr_MASK 0x00000080L -#define IA_DBG_REG_2__dma_skid_fifo_empty_MASK 0x00000100L -#define IA_DBG_REG_2__dma_skid_fifo_full_MASK 0x00000200L -#define IA_DBG_REG_2__dma_grp_valid_MASK 0x00000400L -#define IA_DBG_REG_2__grp_dma_read_MASK 0x00000800L -#define IA_DBG_REG_2__current_data_valid_MASK 0x00001000L -#define IA_DBG_REG_2__out_of_range_r2_q_MASK 0x00002000L -#define IA_DBG_REG_2__dma_mask_fifo_we_MASK 0x00004000L -#define IA_DBG_REG_2__dma_ret_data_we_q_MASK 0x00008000L -#define IA_DBG_REG_2__hp_dma_input_fifo_empty_MASK 0x00010000L -#define IA_DBG_REG_2__hp_dma_input_fifo_full_MASK 0x00020000L -#define IA_DBG_REG_2__hp_start_new_packet_MASK 0x00040000L -#define IA_DBG_REG_2__hp_dma_rdreq_dr_q_MASK 0x00080000L -#define IA_DBG_REG_2__hp_dma_zero_indices_q_MASK 0x00100000L -#define IA_DBG_REG_2__hp_dma_buf_type_q_0_MASK 0x00200000L -#define IA_DBG_REG_2__hp_dma_buf_type_q_1_MASK 0x00400000L -#define IA_DBG_REG_2__hp_dma_req_path_q_MASK 0x00800000L -#define IA_DBG_REG_2__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_3 -#define IA_DBG_REG_3__hp_discard_1st_chunk_MASK 0x00000001L -#define IA_DBG_REG_3__hp_discard_2nd_chunk_MASK 0x00000002L -#define IA_DBG_REG_3__hp_second_tc_ret_data_q_MASK 0x00000004L -#define IA_DBG_REG_3__hp_dma_tc_ret_sel_q_MASK 0x00000008L -#define IA_DBG_REG_3__hp_last_rdreq_in_dma_op_MASK 0x00000010L -#define IA_DBG_REG_3__hp_dma_mask_fifo_empty_MASK 0x00000020L -#define IA_DBG_REG_3__hp_dma_data_fifo_empty_q_MASK 0x00000040L -#define IA_DBG_REG_3__hp_dma_data_fifo_full_MASK 0x00000080L -#define IA_DBG_REG_3__hp_dma_req_fifo_empty_MASK 0x00000100L -#define IA_DBG_REG_3__hp_dma_req_fifo_full_MASK 0x00000200L -#define IA_DBG_REG_3__hp_stage2_dr_MASK 0x00000400L -#define IA_DBG_REG_3__hp_stage2_rtr_MASK 0x00000800L -#define IA_DBG_REG_3__hp_stage3_dr_MASK 0x00001000L -#define IA_DBG_REG_3__hp_stage3_rtr_MASK 0x00002000L -#define IA_DBG_REG_3__hp_stage4_dr_MASK 0x00004000L -#define IA_DBG_REG_3__hp_stage4_rtr_MASK 0x00008000L -#define IA_DBG_REG_3__hp_dma_skid_fifo_empty_MASK 0x00010000L -#define IA_DBG_REG_3__hp_dma_skid_fifo_full_MASK 0x00020000L -#define IA_DBG_REG_3__hp_dma_grp_valid_MASK 0x00040000L -#define IA_DBG_REG_3__hp_grp_dma_read_MASK 0x00080000L -#define IA_DBG_REG_3__hp_current_data_valid_MASK 0x00100000L -#define IA_DBG_REG_3__hp_out_of_range_r2_q_MASK 0x00200000L -#define IA_DBG_REG_3__hp_dma_mask_fifo_we_MASK 0x00400000L -#define IA_DBG_REG_3__hp_dma_ret_data_we_q_MASK 0x00800000L -#define IA_DBG_REG_3__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_4 -#define IA_DBG_REG_4__dma_pipe0_rdreq_valid_MASK 0x00000001L -#define IA_DBG_REG_4__dma_pipe0_rdreq_read_MASK 0x00000002L -#define IA_DBG_REG_4__dma_pipe0_rdreq_null_out_MASK 0x00000004L -#define IA_DBG_REG_4__dma_pipe0_rdreq_eop_out_MASK 0x00000008L -#define IA_DBG_REG_4__dma_pipe0_rdreq_use_tc_out_MASK 0x00000010L -#define IA_DBG_REG_4__grp_dma_draw_is_pipe0_MASK 0x00000020L -#define IA_DBG_REG_4__must_service_pipe0_req_MASK 0x00000040L -#define IA_DBG_REG_4__send_pipe1_req_MASK 0x00000080L -#define IA_DBG_REG_4__dma_pipe1_rdreq_valid_MASK 0x00000100L -#define IA_DBG_REG_4__dma_pipe1_rdreq_read_MASK 0x00000200L -#define IA_DBG_REG_4__dma_pipe1_rdreq_null_out_MASK 0x00000400L -#define IA_DBG_REG_4__dma_pipe1_rdreq_eop_out_MASK 0x00000800L -#define IA_DBG_REG_4__dma_pipe1_rdreq_use_tc_out_MASK 0x00001000L -#define IA_DBG_REG_4__ia_mc_rdreq_rtr_q_MASK 0x00002000L -#define IA_DBG_REG_4__mc_out_rtr_MASK 0x00004000L -#define IA_DBG_REG_4__dma_rdreq_send_out_MASK 0x00008000L -#define IA_DBG_REG_4__pipe0_dr_MASK 0x00010000L -#define IA_DBG_REG_4__pipe0_rtr_MASK 0x00020000L -#define IA_DBG_REG_4__ia_tc_rdreq_rtr_q_MASK 0x00040000L -#define IA_DBG_REG_4__tc_out_rtr_MASK 0x00080000L -#define IA_DBG_REG_4__pair0_valid_p1_MASK 0x00100000L -#define IA_DBG_REG_4__pair1_valid_p1_MASK 0x00200000L -#define IA_DBG_REG_4__pair2_valid_p1_MASK 0x00400000L -#define IA_DBG_REG_4__pair3_valid_p1_MASK 0x00800000L -#define IA_DBG_REG_4__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_5 -#define IA_DBG_REG_5__tc_req_count_q_0_MASK 0x00000001L -#define IA_DBG_REG_5__tc_req_count_q_1_MASK 0x00000002L -#define IA_DBG_REG_5__discard_1st_chunk_MASK 0x00000004L -#define IA_DBG_REG_5__discard_2nd_chunk_MASK 0x00000008L -#define IA_DBG_REG_5__last_tc_req_p1_MASK 0x00000010L -#define IA_DBG_REG_5__IA_TC_rdreq_send_out_MASK 0x00000020L -#define IA_DBG_REG_5__TC_IA_rdret_valid_in_MASK 0x00000040L -#define IA_DBG_REG_5__TAP_IA_rdret_vld_in_MASK 0x00000080L -#define IA_DBG_REG_5__pipe0_dr_MASK 0x00000100L -#define IA_DBG_REG_5__pipe1_dr_MASK 0x00000200L -#define IA_DBG_REG_5__pipe2_dr_MASK 0x00000400L -#define IA_DBG_REG_5__pipe3_dr_MASK 0x00000800L -#define IA_DBG_REG_5__pipe4_dr_MASK 0x00001000L -#define IA_DBG_REG_5__pipe5_dr_MASK 0x00002000L -#define IA_DBG_REG_5__grp_se0_fifo_empty_MASK 0x00004000L -#define IA_DBG_REG_5__grp_se0_fifo_full_MASK 0x00008000L -#define IA_DBG_REG_5__pipe0_rtr_MASK 0x00010000L -#define IA_DBG_REG_5__pipe1_rtr_MASK 0x00020000L -#define IA_DBG_REG_5__pipe2_rtr_MASK 0x00040000L -#define IA_DBG_REG_5__pipe3_rtr_MASK 0x00080000L -#define IA_DBG_REG_5__pipe4_rtr_MASK 0x00100000L -#define IA_DBG_REG_5__pipe5_rtr_MASK 0x00200000L -#define IA_DBG_REG_5__ia_vgt_prim_rtr_q_MASK 0x00400000L -#define IA_DBG_REG_5__ia_se1vgt_prim_rtr_q_MASK 0x00800000L -#define IA_DBG_REG_5__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_6 -#define IA_DBG_REG_6__di_major_mode_p1_q_MASK 0x00000001L -#define IA_DBG_REG_6__gs_mode_p1_q_0_MASK 0x00000002L -#define IA_DBG_REG_6__gs_mode_p1_q_1_MASK 0x00000004L -#define IA_DBG_REG_6__gs_mode_p1_q_2_MASK 0x00000008L -#define IA_DBG_REG_6__di_event_flag_p1_q_MASK 0x00000010L -#define IA_DBG_REG_6__di_state_sel_p1_q_0_MASK 0x00000020L -#define IA_DBG_REG_6__di_state_sel_p1_q_1_MASK 0x00000040L -#define IA_DBG_REG_6__di_state_sel_p1_q_2_MASK 0x00000080L -#define IA_DBG_REG_6__draw_opaq_en_p1_q_MASK 0x00000100L -#define IA_DBG_REG_6__draw_opaq_active_q_MASK 0x00000200L -#define IA_DBG_REG_6__di_source_select_p1_q_0_MASK 0x00000400L -#define IA_DBG_REG_6__di_source_select_p1_q_1_MASK 0x00000800L -#define IA_DBG_REG_6__ready_to_read_di_MASK 0x00001000L -#define IA_DBG_REG_6__di_first_group_of_draw_q_MASK 0x00002000L -#define IA_DBG_REG_6__last_shift_of_draw_MASK 0x00004000L -#define IA_DBG_REG_6__current_shift_is_vect1_q_MASK 0x00008000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_0_MASK 0x00010000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_1_MASK 0x00020000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_2_MASK 0x00040000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_3_MASK 0x00080000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_4_MASK 0x00100000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_5_MASK 0x00200000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_6_MASK 0x00400000L -#define IA_DBG_REG_6__di_index_counter_q_15_0_7_MASK 0x00800000L -#define IA_DBG_REG_6__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_7 -#define IA_DBG_REG_7__di_index_counter_q_15_0_8_MASK 0x00000001L -#define IA_DBG_REG_7__di_index_counter_q_15_0_9_MASK 0x00000002L -#define IA_DBG_REG_7__di_index_counter_q_15_0_10_MASK 0x00000004L -#define IA_DBG_REG_7__di_index_counter_q_15_0_11_MASK 0x00000008L -#define IA_DBG_REG_7__di_index_counter_q_15_0_12_MASK 0x00000010L -#define IA_DBG_REG_7__di_index_counter_q_15_0_13_MASK 0x00000020L -#define IA_DBG_REG_7__di_index_counter_q_15_0_14_MASK 0x00000040L -#define IA_DBG_REG_7__di_index_counter_q_15_0_15_MASK 0x00000080L -#define IA_DBG_REG_7__instanceid_13_0_0_MASK 0x00000100L -#define IA_DBG_REG_7__instanceid_13_0_1_MASK 0x00000200L -#define IA_DBG_REG_7__instanceid_13_0_2_MASK 0x00000400L -#define IA_DBG_REG_7__instanceid_13_0_3_MASK 0x00000800L -#define IA_DBG_REG_7__instanceid_13_0_4_MASK 0x00001000L -#define IA_DBG_REG_7__instanceid_13_0_5_MASK 0x00002000L -#define IA_DBG_REG_7__instanceid_13_0_6_MASK 0x00004000L -#define IA_DBG_REG_7__instanceid_13_0_7_MASK 0x00008000L -#define IA_DBG_REG_7__instanceid_13_0_8_MASK 0x00010000L -#define IA_DBG_REG_7__instanceid_13_0_9_MASK 0x00020000L -#define IA_DBG_REG_7__instanceid_13_0_10_MASK 0x00040000L -#define IA_DBG_REG_7__instanceid_13_0_11_MASK 0x00080000L -#define IA_DBG_REG_7__instanceid_13_0_12_MASK 0x00100000L -#define IA_DBG_REG_7__instanceid_13_0_13_MASK 0x00200000L -#define IA_DBG_REG_7__draw_input_fifo_full_MASK 0x00400000L -#define IA_DBG_REG_7__draw_input_fifo_empty_MASK 0x00800000L -#define IA_DBG_REG_7__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_8 -#define IA_DBG_REG_8__current_shift_q_0_MASK 0x00000001L -#define IA_DBG_REG_8__current_shift_q_1_MASK 0x00000002L -#define IA_DBG_REG_8__current_shift_q_2_MASK 0x00000004L -#define IA_DBG_REG_8__current_shift_q_3_MASK 0x00000008L -#define IA_DBG_REG_8__current_stride_pre_0_MASK 0x00000010L -#define IA_DBG_REG_8__current_stride_pre_1_MASK 0x00000020L -#define IA_DBG_REG_8__current_stride_pre_2_MASK 0x00000040L -#define IA_DBG_REG_8__current_stride_pre_3_MASK 0x00000080L -#define IA_DBG_REG_8__current_stride_q_0_MASK 0x00000100L -#define IA_DBG_REG_8__current_stride_q_1_MASK 0x00000200L -#define IA_DBG_REG_8__current_stride_q_2_MASK 0x00000400L -#define IA_DBG_REG_8__current_stride_q_3_MASK 0x00000800L -#define IA_DBG_REG_8__current_stride_q_4_MASK 0x00001000L -#define IA_DBG_REG_8__first_group_partial_MASK 0x00002000L -#define IA_DBG_REG_8__second_group_partial_MASK 0x00004000L -#define IA_DBG_REG_8__curr_prim_partial_MASK 0x00008000L -#define IA_DBG_REG_8__next_stride_q_0_MASK 0x00010000L -#define IA_DBG_REG_8__next_stride_q_1_MASK 0x00020000L -#define IA_DBG_REG_8__next_stride_q_2_MASK 0x00040000L -#define IA_DBG_REG_8__next_stride_q_3_MASK 0x00080000L -#define IA_DBG_REG_8__next_stride_q_4_MASK 0x00100000L -#define IA_DBG_REG_8__next_group_partial_MASK 0x00200000L -#define IA_DBG_REG_8__after_group_partial_MASK 0x00400000L -#define IA_DBG_REG_8__extract_group_MASK 0x00800000L -#define IA_DBG_REG_8__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_9 -#define IA_DBG_REG_9__grp_shift_debug_data_0_MASK 0x00000001L -#define IA_DBG_REG_9__grp_shift_debug_data_1_MASK 0x00000002L -#define IA_DBG_REG_9__grp_shift_debug_data_2_MASK 0x00000004L -#define IA_DBG_REG_9__grp_shift_debug_data_3_MASK 0x00000008L -#define IA_DBG_REG_9__grp_shift_debug_data_4_MASK 0x00000010L -#define IA_DBG_REG_9__grp_shift_debug_data_5_MASK 0x00000020L -#define IA_DBG_REG_9__grp_shift_debug_data_6_MASK 0x00000040L -#define IA_DBG_REG_9__grp_shift_debug_data_7_MASK 0x00000080L -#define IA_DBG_REG_9__reset_indx_state_q_0_MASK 0x00000100L -#define IA_DBG_REG_9__reset_indx_state_q_1_MASK 0x00000200L -#define IA_DBG_REG_9__reset_indx_state_q_2_MASK 0x00000400L -#define IA_DBG_REG_9__reset_indx_state_q_3_MASK 0x00000800L -#define IA_DBG_REG_9__shift_vect_valid_p2_q_0_MASK 0x00001000L -#define IA_DBG_REG_9__shift_vect_valid_p2_q_1_MASK 0x00002000L -#define IA_DBG_REG_9__shift_vect_valid_p2_q_2_MASK 0x00004000L -#define IA_DBG_REG_9__shift_vect_valid_p2_q_3_MASK 0x00008000L -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_0_MASK 0x00010000L -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_1_MASK 0x00020000L -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_2_MASK 0x00040000L -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_3_MASK 0x00080000L -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_0_MASK 0x00100000L -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_1_MASK 0x00200000L -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_2_MASK 0x00400000L -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_3_MASK 0x00800000L -#define IA_DBG_REG_9__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_10 -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_0_MASK 0x00000001L -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_1_MASK 0x00000002L -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_2_MASK 0x00000004L -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_3_MASK 0x00000008L -#define IA_DBG_REG_10__num_indx_in_group_p2_q_0_MASK 0x00000010L -#define IA_DBG_REG_10__num_indx_in_group_p2_q_1_MASK 0x00000020L -#define IA_DBG_REG_10__num_indx_in_group_p2_q_2_MASK 0x00000040L -#define IA_DBG_REG_10__last_group_of_draw_p2_q_MASK 0x00000080L -#define IA_DBG_REG_10__shift_event_flag_p2_q_MASK 0x00000100L -#define IA_DBG_REG_10__indx_shift_is_one_p2_q_MASK 0x00000200L -#define IA_DBG_REG_10__indx_shift_is_two_p2_q_MASK 0x00000400L -#define IA_DBG_REG_10__indx_stride_is_four_p2_q_MASK 0x00000800L -#define IA_DBG_REG_10__shift_prim1_reset_p3_q_MASK 0x00001000L -#define IA_DBG_REG_10__shift_prim1_partial_p3_q_MASK 0x00002000L -#define IA_DBG_REG_10__shift_prim0_reset_p3_q_MASK 0x00004000L -#define IA_DBG_REG_10__shift_prim0_partial_p3_q_MASK 0x00008000L -#define IA_DBG_REG_10__di_prim_type_p1_q_0_MASK 0x00010000L -#define IA_DBG_REG_10__di_prim_type_p1_q_1_MASK 0x00020000L -#define IA_DBG_REG_10__di_prim_type_p1_q_2_MASK 0x00040000L -#define IA_DBG_REG_10__di_prim_type_p1_q_3_MASK 0x00080000L -#define IA_DBG_REG_10__di_prim_type_p1_q_4_MASK 0x00100000L -#define IA_DBG_REG_10__two_cycle_xfer_p1_q_MASK 0x00200000L -#define IA_DBG_REG_10__two_prim_input_p1_q_MASK 0x00400000L -#define IA_DBG_REG_10__shift_vect_end_of_packet_p5_q_MASK 0x00800000L -#define IA_DBG_REG_10__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_11 -#define IA_DBG_REG_11__last_group_of_inst_p5_q_MASK 0x00000001L -#define IA_DBG_REG_11__shift_prim1_null_flag_p5_q_MASK 0x00000002L -#define IA_DBG_REG_11__shift_prim0_null_flag_p5_q_MASK 0x00000004L -#define IA_DBG_REG_11__grp_continued_MASK 0x00000008L -#define IA_DBG_REG_11__grp_state_sel_0_MASK 0x00000010L -#define IA_DBG_REG_11__grp_state_sel_1_MASK 0x00000020L -#define IA_DBG_REG_11__grp_state_sel_2_MASK 0x00000040L -#define IA_DBG_REG_11__grp_sub_prim_type_0_MASK 0x00000080L -#define IA_DBG_REG_11__grp_sub_prim_type_1_MASK 0x00000100L -#define IA_DBG_REG_11__grp_sub_prim_type_2_MASK 0x00000200L -#define IA_DBG_REG_11__grp_sub_prim_type_3_MASK 0x00000400L -#define IA_DBG_REG_11__grp_sub_prim_type_4_MASK 0x00000800L -#define IA_DBG_REG_11__grp_sub_prim_type_5_MASK 0x00001000L -#define IA_DBG_REG_11__grp_output_path_0_MASK 0x00002000L -#define IA_DBG_REG_11__grp_output_path_1_MASK 0x00004000L -#define IA_DBG_REG_11__grp_output_path_2_MASK 0x00008000L -#define IA_DBG_REG_11__grp_null_primitive_MASK 0x00010000L -#define IA_DBG_REG_11__grp_eop_MASK 0x00020000L -#define IA_DBG_REG_11__grp_eopg_MASK 0x00040000L -#define IA_DBG_REG_11__grp_event_flag_MASK 0x00080000L -#define IA_DBG_REG_11__grp_components_valid_0_MASK 0x00100000L -#define IA_DBG_REG_11__grp_components_valid_1_MASK 0x00200000L -#define IA_DBG_REG_11__grp_components_valid_2_MASK 0x00400000L -#define IA_DBG_REG_11__grp_components_valid_3_MASK 0x00800000L -#define IA_DBG_REG_11__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_12 -#define IA_DBG_REG_12__send_to_se1_p6_MASK 0x00000001L -#define IA_DBG_REG_12__gfx_se_switch_p6_MASK 0x00000002L -#define IA_DBG_REG_12__null_eoi_xfer_prim1_p6_MASK 0x00000004L -#define IA_DBG_REG_12__null_eoi_xfer_prim0_p6_MASK 0x00000008L -#define IA_DBG_REG_12__prim1_eoi_p6_MASK 0x00000010L -#define IA_DBG_REG_12__prim0_eoi_p6_MASK 0x00000020L -#define IA_DBG_REG_12__prim1_valid_eopg_p6_MASK 0x00000040L -#define IA_DBG_REG_12__prim0_valid_eopg_p6_MASK 0x00000080L -#define IA_DBG_REG_12__prim1_to_other_se_p6_MASK 0x00000100L -#define IA_DBG_REG_12__eopg_on_last_prim_p6_MASK 0x00000200L -#define IA_DBG_REG_12__eopg_between_prims_p6_MASK 0x00000400L -#define IA_DBG_REG_12__prim_count_eq_group_size_p6_MASK 0x00000800L -#define IA_DBG_REG_12__prim_count_gt_group_size_p6_MASK 0x00001000L -#define IA_DBG_REG_12__two_prim_output_p5_q_MASK 0x00002000L -#define IA_DBG_REG_12__Reserved2_MASK 0x00004000L -#define IA_DBG_REG_12__Reserved1_MASK 0x00008000L -#define IA_DBG_REG_12__shift_vect_end_of_packet_p5_q_MASK 0x00010000L -#define IA_DBG_REG_12__prim1_xfer_p6_MASK 0x00020000L -#define IA_DBG_REG_12__grp_se1_fifo_empty_MASK 0x00040000L -#define IA_DBG_REG_12__grp_se1_fifo_full_MASK 0x00080000L -#define IA_DBG_REG_12__prim_counter_q_0_MASK 0x00100000L -#define IA_DBG_REG_12__prim_counter_q_1_MASK 0x00200000L -#define IA_DBG_REG_12__prim_counter_q_2_MASK 0x00400000L -#define IA_DBG_REG_12__prim_counter_q_3_MASK 0x00800000L -#define IA_DBG_REG_12__Reserved0_MASK 0xff000000L - -// IA_DBG_REG_13 -#define IA_DBG_REG_13__prim_counter_q_0_MASK 0x00000001L -#define IA_DBG_REG_13__prim_counter_q_1_MASK 0x00000002L -#define IA_DBG_REG_13__prim_counter_q_2_MASK 0x00000004L -#define IA_DBG_REG_13__prim_counter_q_3_MASK 0x00000008L -#define IA_DBG_REG_13__prim_counter_q_4_MASK 0x00000010L -#define IA_DBG_REG_13__prim_counter_q_5_MASK 0x00000020L -#define IA_DBG_REG_13__prim_counter_q_6_MASK 0x00000040L -#define IA_DBG_REG_13__prim_counter_q_7_MASK 0x00000080L -#define IA_DBG_REG_13__Reserved15_MASK 0x00000100L -#define IA_DBG_REG_13__Reserved14_MASK 0x00000200L -#define IA_DBG_REG_13__Reserved13_MASK 0x00000400L -#define IA_DBG_REG_13__Reserved12_MASK 0x00000800L -#define IA_DBG_REG_13__Reserved11_MASK 0x00001000L -#define IA_DBG_REG_13__Reserved10_MASK 0x00002000L -#define IA_DBG_REG_13__Reserved9_MASK 0x00004000L -#define IA_DBG_REG_13__Reserved8_MASK 0x00008000L -#define IA_DBG_REG_13__Reserved7_MASK 0x00010000L -#define IA_DBG_REG_13__Reserved6_MASK 0x00020000L -#define IA_DBG_REG_13__Reserved5_MASK 0x00040000L -#define IA_DBG_REG_13__Reserved4_MASK 0x00080000L -#define IA_DBG_REG_13__Reserved3_MASK 0x00100000L -#define IA_DBG_REG_13__Reserved2_MASK 0x00200000L -#define IA_DBG_REG_13__Reserved1_MASK 0x00400000L -#define IA_DBG_REG_13__Reserved0_MASK 0x80000000L - -// IA_DBG_REG_14 -#define IA_DBG_REG_14__Reserved23_MASK 0x00000001L -#define IA_DBG_REG_14__Reserved22_MASK 0x00000002L -#define IA_DBG_REG_14__Reserved21_MASK 0x00000004L -#define IA_DBG_REG_14__Reserved20_MASK 0x00000008L -#define IA_DBG_REG_14__Reserved19_MASK 0x00000010L -#define IA_DBG_REG_14__Reserved18_MASK 0x00000020L -#define IA_DBG_REG_14__Reserved17_MASK 0x00000040L -#define IA_DBG_REG_14__Reserved16_MASK 0x00000080L -#define IA_DBG_REG_14__Reserved15_MASK 0x00000100L -#define IA_DBG_REG_14__Reserved14_MASK 0x00000200L -#define IA_DBG_REG_14__Reserved13_MASK 0x00000400L -#define IA_DBG_REG_14__Reserved12_MASK 0x00000800L -#define IA_DBG_REG_14__Reserved11_MASK 0x00001000L -#define IA_DBG_REG_14__Reserved10_MASK 0x00002000L -#define IA_DBG_REG_14__Reserved9_MASK 0x00004000L -#define IA_DBG_REG_14__Reserved8_MASK 0x00008000L -#define IA_DBG_REG_14__Reserved7_MASK 0x00010000L -#define IA_DBG_REG_14__Reserved6_MASK 0x00020000L -#define IA_DBG_REG_14__Reserved5_MASK 0x00040000L -#define IA_DBG_REG_14__Reserved4_MASK 0x00080000L -#define IA_DBG_REG_14__Reserved3_MASK 0x00100000L -#define IA_DBG_REG_14__Reserved2_MASK 0x00200000L -#define IA_DBG_REG_14__Reserved1_MASK 0x00400000L -#define IA_DBG_REG_14__Reserved0_MASK 0x80000000L - -// IA_DBG_REG_15 -#define IA_DBG_REG_15__Reserved23_MASK 0x00000001L -#define IA_DBG_REG_15__Reserved22_MASK 0x00000002L -#define IA_DBG_REG_15__Reserved21_MASK 0x00000004L -#define IA_DBG_REG_15__Reserved20_MASK 0x00000008L -#define IA_DBG_REG_15__Reserved19_MASK 0x00000010L -#define IA_DBG_REG_15__Reserved18_MASK 0x00000020L -#define IA_DBG_REG_15__Reserved17_MASK 0x00000040L -#define IA_DBG_REG_15__Reserved16_MASK 0x00000080L -#define IA_DBG_REG_15__Reserved15_MASK 0x00000100L -#define IA_DBG_REG_15__Reserved14_MASK 0x00000200L -#define IA_DBG_REG_15__Reserved13_MASK 0x00000400L -#define IA_DBG_REG_15__Reserved12_MASK 0x00000800L -#define IA_DBG_REG_15__Reserved11_MASK 0x00001000L -#define IA_DBG_REG_15__Reserved10_MASK 0x00002000L -#define IA_DBG_REG_15__Reserved9_MASK 0x00004000L -#define IA_DBG_REG_15__Reserved8_MASK 0x00008000L -#define IA_DBG_REG_15__Reserved7_MASK 0x00010000L -#define IA_DBG_REG_15__Reserved6_MASK 0x00020000L -#define IA_DBG_REG_15__Reserved5_MASK 0x00040000L -#define IA_DBG_REG_15__Reserved4_MASK 0x00080000L -#define IA_DBG_REG_15__Reserved3_MASK 0x00100000L -#define IA_DBG_REG_15__Reserved2_MASK 0x00200000L -#define IA_DBG_REG_15__Reserved1_MASK 0x00400000L -#define IA_DBG_REG_15__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_0 -#define VGT_DBG_REG_0__vgt_busy_extended_MASK 0x00000001L -#define VGT_DBG_REG_0__Reserved8_MASK 0x00000002L -#define VGT_DBG_REG_0__vgt_busy_MASK 0x00000004L -#define VGT_DBG_REG_0__Reserved7_MASK 0x00000008L -#define VGT_DBG_REG_0__Reserved6_MASK 0x00000010L -#define VGT_DBG_REG_0__Reserved5_MASK 0x00000020L -#define VGT_DBG_REG_0__Reserved4_MASK 0x00000040L -#define VGT_DBG_REG_0__Reserved3_MASK 0x00000080L -#define VGT_DBG_REG_0__pi_busy_MASK 0x00000100L -#define VGT_DBG_REG_0__vr_pi_busy_MASK 0x00000200L -#define VGT_DBG_REG_0__pt_pi_busy_MASK 0x00000400L -#define VGT_DBG_REG_0__te_pi_busy_MASK 0x00000800L -#define VGT_DBG_REG_0__gs_busy_MASK 0x00001000L -#define VGT_DBG_REG_0__rcm_busy_MASK 0x00002000L -#define VGT_DBG_REG_0__tm_busy_MASK 0x00004000L -#define VGT_DBG_REG_0__cm_busy_MASK 0x00008000L -#define VGT_DBG_REG_0__gog_busy_MASK 0x00010000L -#define VGT_DBG_REG_0__frmt_busy_MASK 0x00020000L -#define VGT_DBG_REG_0__Reserved2_MASK 0x00040000L -#define VGT_DBG_REG_0__te11_pi_busy_MASK 0x00080000L -#define VGT_DBG_REG_0__Reserved1_MASK 0x00100000L -#define VGT_DBG_REG_0__combined_out_busy_MASK 0x00200000L -#define VGT_DBG_REG_0__spi_vs_interfaces_busy_MASK 0x00400000L -#define VGT_DBG_REG_0__pa_interfaces_busy_MASK 0x00800000L -#define VGT_DBG_REG_0__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_1 -#define VGT_DBG_REG_1__reg_clk_busy_MASK 0x00000001L -#define VGT_DBG_REG_1__Reserved13_MASK 0x00000002L -#define VGT_DBG_REG_1__core_clk_busy_MASK 0x00000004L -#define VGT_DBG_REG_1__gs_clk_busy_MASK 0x00000008L -#define VGT_DBG_REG_1__Reserved12_MASK 0x00000010L -#define VGT_DBG_REG_1__sclk_core_vld_MASK 0x00000020L -#define VGT_DBG_REG_1__sclk_gs_vld_MASK 0x00000040L -#define VGT_DBG_REG_1__Reserved11_MASK 0x00000080L -#define VGT_DBG_REG_1__Reserved10_MASK 0x00000100L -#define VGT_DBG_REG_1__Reserved9_MASK 0x00000200L -#define VGT_DBG_REG_1__Reserved8_MASK 0x00000400L -#define VGT_DBG_REG_1__Reserved7_MASK 0x00000800L -#define VGT_DBG_REG_1__Reserved6_MASK 0x00001000L -#define VGT_DBG_REG_1__Reserved5_MASK 0x00002000L -#define VGT_DBG_REG_1__Reserved4_MASK 0x00004000L -#define VGT_DBG_REG_1__Reserved3_MASK 0x00008000L -#define VGT_DBG_REG_1__Reserved2_MASK 0x00010000L -#define VGT_DBG_REG_1__Reserved1_MASK 0x00020000L -#define VGT_DBG_REG_1__pi_vr_valid_MASK 0x00040000L -#define VGT_DBG_REG_1__vr_pi_read_MASK 0x00080000L -#define VGT_DBG_REG_1__pi_pt_valid_MASK 0x00100000L -#define VGT_DBG_REG_1__pt_pi_read_MASK 0x00200000L -#define VGT_DBG_REG_1__pi_te_valid_MASK 0x00400000L -#define VGT_DBG_REG_1__te_grp_read_MASK 0x00800000L -#define VGT_DBG_REG_1__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_2 -#define VGT_DBG_REG_2__vr_out_indx_valid_MASK 0x00000001L -#define VGT_DBG_REG_2__Reserved5_MASK 0x00000002L -#define VGT_DBG_REG_2__vr_out_prim_valid_MASK 0x00000004L -#define VGT_DBG_REG_2__Reserved4_MASK 0x00000008L -#define VGT_DBG_REG_2__pt_out_indx_valid_MASK 0x00000010L -#define VGT_DBG_REG_2__Reserved3_MASK 0x00000020L -#define VGT_DBG_REG_2__pt_out_prim_valid_MASK 0x00000040L -#define VGT_DBG_REG_2__Reserved2_MASK 0x00000080L -#define VGT_DBG_REG_2__te_out_data_valid_MASK 0x00000100L -#define VGT_DBG_REG_2__Reserved1_MASK 0x00000200L -#define VGT_DBG_REG_2__pi_gs_valid_MASK 0x00000400L -#define VGT_DBG_REG_2__gs_pi_read_MASK 0x00000800L -#define VGT_DBG_REG_2__gog_out_indx_valid_MASK 0x00001000L -#define VGT_DBG_REG_2__out_indx_read_MASK 0x00002000L -#define VGT_DBG_REG_2__gog_out_prim_valid_MASK 0x00004000L -#define VGT_DBG_REG_2__out_prim_read_MASK 0x00008000L -#define VGT_DBG_REG_2__hs_grp_busy_MASK 0x00010000L -#define VGT_DBG_REG_2__hs_noif_busy_MASK 0x00020000L -#define VGT_DBG_REG_2__tfmmIsBusy_MASK 0x00040000L -#define VGT_DBG_REG_2__lsVertIfBusy_0_MASK 0x00080000L -#define VGT_DBG_REG_2__te11_hs_tess_input_rtr_MASK 0x00100000L -#define VGT_DBG_REG_2__lsWaveIfBusy_0_MASK 0x00200000L -#define VGT_DBG_REG_2__hs_te11_tess_input_rts_MASK 0x00400000L -#define VGT_DBG_REG_2__grpModBusy_MASK 0x00800000L -#define VGT_DBG_REG_2__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_3 -#define VGT_DBG_REG_3__lsVertFifoEmpty_MASK 0x00000001L -#define VGT_DBG_REG_3__lsWaveFifoEmpty_MASK 0x00000002L -#define VGT_DBG_REG_3__hsVertFifoEmpty_MASK 0x00000004L -#define VGT_DBG_REG_3__hsWaveFifoEmpty_MASK 0x00000008L -#define VGT_DBG_REG_3__hsInputFifoEmpty_MASK 0x00000010L -#define VGT_DBG_REG_3__hsTifFifoEmpty_MASK 0x00000020L -#define VGT_DBG_REG_3__lsVertFifoFull_MASK 0x00000040L -#define VGT_DBG_REG_3__lsWaveFifoFull_MASK 0x00000080L -#define VGT_DBG_REG_3__hsVertFifoFull_MASK 0x00000100L -#define VGT_DBG_REG_3__hsWaveFifoFull_MASK 0x00000200L -#define VGT_DBG_REG_3__hsInputFifoFull_MASK 0x00000400L -#define VGT_DBG_REG_3__hsTifFifoFull_MASK 0x00000800L -#define VGT_DBG_REG_3__p0_rtr_MASK 0x00001000L -#define VGT_DBG_REG_3__p1_rtr_MASK 0x00002000L -#define VGT_DBG_REG_3__p0_dr_MASK 0x00004000L -#define VGT_DBG_REG_3__p1_dr_MASK 0x00008000L -#define VGT_DBG_REG_3__p0_rts_MASK 0x00010000L -#define VGT_DBG_REG_3__p1_rts_MASK 0x00020000L -#define VGT_DBG_REG_3__ls_sh_id_MASK 0x00040000L -#define VGT_DBG_REG_3__lsFwaveFlag_MASK 0x00080000L -#define VGT_DBG_REG_3__lsWaveSendFlush_MASK 0x00100000L -#define VGT_DBG_REG_3__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_3__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_3__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_4 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_0_MASK 0x00000001L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_1_MASK 0x00000002L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_2_MASK 0x00000004L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_3_MASK 0x00000008L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_4_MASK 0x00000010L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_5_MASK 0x00000020L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_6_MASK 0x00000040L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_7_MASK 0x00000080L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_8_MASK 0x00000100L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_9_MASK 0x00000200L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_10_MASK 0x00000400L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_11_MASK 0x00000800L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_12_MASK 0x00001000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_13_MASK 0x00002000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_14_MASK 0x00004000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_15_MASK 0x00008000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_16_MASK 0x00010000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_17_MASK 0x00020000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_18_MASK 0x00040000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_19_MASK 0x00080000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_20_MASK 0x00100000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_21_MASK 0x00200000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_22_MASK 0x00400000L -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_23_MASK 0x00800000L -#define VGT_DBG_REG_4__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_5 -#define VGT_DBG_REG_5__dependent_st_cut_mode_q_0_MASK 0x00000001L -#define VGT_DBG_REG_5__dependent_st_cut_mode_q_1_MASK 0x00000002L -#define VGT_DBG_REG_5__Reserved6_MASK 0x00000004L -#define VGT_DBG_REG_5__Reserved5_MASK 0x00000008L -#define VGT_DBG_REG_5__Reserved4_MASK 0x00000010L -#define VGT_DBG_REG_5__Reserved3_MASK 0x00000020L -#define VGT_DBG_REG_5__Reserved2_MASK 0x00000040L -#define VGT_DBG_REG_5__Reserved1_MASK 0x00000080L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_0_MASK 0x00000100L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_1_MASK 0x00000200L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_2_MASK 0x00000400L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_3_MASK 0x00000800L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_4_MASK 0x00001000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_5_MASK 0x00002000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_6_MASK 0x00004000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_7_MASK 0x00008000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_8_MASK 0x00010000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_9_MASK 0x00020000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_10_MASK 0x00040000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_11_MASK 0x00080000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_12_MASK 0x00100000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_13_MASK 0x00200000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_14_MASK 0x00400000L -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_15_MASK 0x00800000L -#define VGT_DBG_REG_5__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_6 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_16_MASK 0x00000001L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_17_MASK 0x00000002L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_18_MASK 0x00000004L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_19_MASK 0x00000008L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_20_MASK 0x00000010L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_21_MASK 0x00000020L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_22_MASK 0x00000040L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_23_MASK 0x00000080L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_24_MASK 0x00000100L -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_25_MASK 0x00000200L -#define VGT_DBG_REG_6__active_sm_r0_q_0_MASK 0x00000400L -#define VGT_DBG_REG_6__active_sm_r0_q_1_MASK 0x00000800L -#define VGT_DBG_REG_6__active_sm_r0_q_2_MASK 0x00001000L -#define VGT_DBG_REG_6__active_sm_r0_q_3_MASK 0x00002000L -#define VGT_DBG_REG_6__add_gs_rb_space_r1_q_MASK 0x00004000L -#define VGT_DBG_REG_6__add_gs_rb_space_r0_q_MASK 0x00008000L -#define VGT_DBG_REG_6__cm_state0_0_MASK 0x00010000L -#define VGT_DBG_REG_6__cm_state0_1_MASK 0x00020000L -#define VGT_DBG_REG_6__cm_state1_0_MASK 0x00040000L -#define VGT_DBG_REG_6__cm_state1_1_MASK 0x00080000L -#define VGT_DBG_REG_6__cm_state2_0_MASK 0x00100000L -#define VGT_DBG_REG_6__cm_state2_1_MASK 0x00200000L -#define VGT_DBG_REG_6__cm_state3_0_MASK 0x00400000L -#define VGT_DBG_REG_6__cm_state3_1_MASK 0x00800000L -#define VGT_DBG_REG_6__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_7 -#define VGT_DBG_REG_7__cm_state4_0_MASK 0x00000001L -#define VGT_DBG_REG_7__cm_state4_1_MASK 0x00000002L -#define VGT_DBG_REG_7__cm_state5_0_MASK 0x00000004L -#define VGT_DBG_REG_7__cm_state5_1_MASK 0x00000008L -#define VGT_DBG_REG_7__cm_state6_0_MASK 0x00000010L -#define VGT_DBG_REG_7__cm_state6_1_MASK 0x00000020L -#define VGT_DBG_REG_7__cm_state7_0_MASK 0x00000040L -#define VGT_DBG_REG_7__cm_state7_1_MASK 0x00000080L -#define VGT_DBG_REG_7__cm_state8_0_MASK 0x00000100L -#define VGT_DBG_REG_7__cm_state8_1_MASK 0x00000200L -#define VGT_DBG_REG_7__cm_state9_0_MASK 0x00000400L -#define VGT_DBG_REG_7__cm_state9_1_MASK 0x00000800L -#define VGT_DBG_REG_7__cm_state10_0_MASK 0x00001000L -#define VGT_DBG_REG_7__cm_state10_1_MASK 0x00002000L -#define VGT_DBG_REG_7__cm_state11_0_MASK 0x00004000L -#define VGT_DBG_REG_7__cm_state11_1_MASK 0x00008000L -#define VGT_DBG_REG_7__cm_state12_0_MASK 0x00010000L -#define VGT_DBG_REG_7__cm_state12_1_MASK 0x00020000L -#define VGT_DBG_REG_7__cm_state13_0_MASK 0x00040000L -#define VGT_DBG_REG_7__cm_state13_1_MASK 0x00080000L -#define VGT_DBG_REG_7__cm_state14_0_MASK 0x00100000L -#define VGT_DBG_REG_7__cm_state14_1_MASK 0x00200000L -#define VGT_DBG_REG_7__cm_state15_0_MASK 0x00400000L -#define VGT_DBG_REG_7__cm_state15_1_MASK 0x00800000L -#define VGT_DBG_REG_7__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_8 -#define VGT_DBG_REG_8__pipe0_dr_MASK 0x00000001L -#define VGT_DBG_REG_8__gsc0_dr_MASK 0x00000002L -#define VGT_DBG_REG_8__pipe1_dr_MASK 0x00000004L -#define VGT_DBG_REG_8__tm_pt_event_rtr_MASK 0x00000008L -#define VGT_DBG_REG_8__pipe0_rtr_MASK 0x00000010L -#define VGT_DBG_REG_8__gsc0_rtr_MASK 0x00000020L -#define VGT_DBG_REG_8__pipe1_rtr_MASK 0x00000040L -#define VGT_DBG_REG_8__last_indx_of_prim_p1_q_MASK 0x00000080L -#define VGT_DBG_REG_8__indices_to_send_p0_q_0_MASK 0x00000100L -#define VGT_DBG_REG_8__indices_to_send_p0_q_1_MASK 0x00000200L -#define VGT_DBG_REG_8__event_flag_p1_q_MASK 0x00000400L -#define VGT_DBG_REG_8__eop_p1_q_MASK 0x00000800L -#define VGT_DBG_REG_8__gs_out_prim_type_p0_q_0_MASK 0x00001000L -#define VGT_DBG_REG_8__gs_out_prim_type_p0_q_1_MASK 0x00002000L -#define VGT_DBG_REG_8__gsc_null_primitive_p0_q_MASK 0x00004000L -#define VGT_DBG_REG_8__gsc_eop_p0_q_MASK 0x00008000L -#define VGT_DBG_REG_8__gsc_2cycle_output_MASK 0x00010000L -#define VGT_DBG_REG_8__gsc_2nd_cycle_p0_q_MASK 0x00020000L -#define VGT_DBG_REG_8__last_indx_of_vsprim_MASK 0x00040000L -#define VGT_DBG_REG_8__first_vsprim_of_gsprim_p0_q_MASK 0x00080000L -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_0_MASK 0x00100000L -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_1_MASK 0x00200000L -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_2_MASK 0x00400000L -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_3_MASK 0x00800000L -#define VGT_DBG_REG_8__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_9 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_4_MASK 0x00000001L -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_5_MASK 0x00000002L -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_6_MASK 0x00000004L -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_7_MASK 0x00000008L -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_8_MASK 0x00000010L -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_9_MASK 0x00000020L -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_10_MASK 0x00000040L -#define VGT_DBG_REG_9__last_vsprim_of_gsprim_MASK 0x00000080L -#define VGT_DBG_REG_9__con_state_q_0_MASK 0x00000100L -#define VGT_DBG_REG_9__con_state_q_1_MASK 0x00000200L -#define VGT_DBG_REG_9__con_state_q_2_MASK 0x00000400L -#define VGT_DBG_REG_9__con_state_q_3_MASK 0x00000800L -#define VGT_DBG_REG_9__second_cycle_q_MASK 0x00001000L -#define VGT_DBG_REG_9__process_tri_middle_p0_q_MASK 0x00002000L -#define VGT_DBG_REG_9__process_tri_1st_2nd_half_p0_q_MASK 0x00004000L -#define VGT_DBG_REG_9__process_tri_center_poly_p0_q_MASK 0x00008000L -#define VGT_DBG_REG_9__pipe0_patch_dr_MASK 0x00010000L -#define VGT_DBG_REG_9__pipe0_edge_dr_MASK 0x00020000L -#define VGT_DBG_REG_9__pipe1_dr_MASK 0x00040000L -#define VGT_DBG_REG_9__pipe0_patch_rtr_MASK 0x00080000L -#define VGT_DBG_REG_9__pipe0_edge_rtr_MASK 0x00100000L -#define VGT_DBG_REG_9__pipe1_rtr_MASK 0x00200000L -#define VGT_DBG_REG_9__outer_parity_p0_q_MASK 0x00400000L -#define VGT_DBG_REG_9__parallel_parity_p0_q_MASK 0x00800000L -#define VGT_DBG_REG_9__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_10 -#define VGT_DBG_REG_10__first_ring_of_patch_p0_q_MASK 0x00000001L -#define VGT_DBG_REG_10__last_ring_of_patch_p0_q_MASK 0x00000002L -#define VGT_DBG_REG_10__last_edge_of_outer_ring_p0_q_MASK 0x00000004L -#define VGT_DBG_REG_10__last_point_of_outer_ring_p1_MASK 0x00000008L -#define VGT_DBG_REG_10__last_point_of_inner_ring_p1_MASK 0x00000010L -#define VGT_DBG_REG_10__outer_edge_tf_eq_one_p0_q_MASK 0x00000020L -#define VGT_DBG_REG_10__advance_outer_point_p1_MASK 0x00000040L -#define VGT_DBG_REG_10__advance_inner_point_p1_MASK 0x00000080L -#define VGT_DBG_REG_10__next_ring_is_rect_p0_q_MASK 0x00000100L -#define VGT_DBG_REG_10__pipe1_outer1_rtr_MASK 0x00000200L -#define VGT_DBG_REG_10__pipe1_outer2_rtr_MASK 0x00000400L -#define VGT_DBG_REG_10__pipe1_inner1_rtr_MASK 0x00000800L -#define VGT_DBG_REG_10__pipe1_inner2_rtr_MASK 0x00001000L -#define VGT_DBG_REG_10__pipe1_patch_rtr_MASK 0x00002000L -#define VGT_DBG_REG_10__pipe1_edge_rtr_MASK 0x00004000L -#define VGT_DBG_REG_10__use_stored_inner_q_ring2_MASK 0x00008000L -#define VGT_DBG_REG_10__con_state_q_0_MASK 0x00010000L -#define VGT_DBG_REG_10__con_state_q_1_MASK 0x00020000L -#define VGT_DBG_REG_10__con_state_q_2_MASK 0x00040000L -#define VGT_DBG_REG_10__con_state_q_3_MASK 0x00080000L -#define VGT_DBG_REG_10__second_cycle_q_MASK 0x00100000L -#define VGT_DBG_REG_10__process_tri_middle_p0_q_MASK 0x00200000L -#define VGT_DBG_REG_10__process_tri_1st_2nd_half_p0_q_MASK 0x00400000L -#define VGT_DBG_REG_10__process_tri_center_poly_p0_q_MASK 0x00800000L -#define VGT_DBG_REG_10__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_11 -#define VGT_DBG_REG_11__pipe0_patch_dr_MASK 0x00000001L -#define VGT_DBG_REG_11__pipe0_edge_dr_MASK 0x00000002L -#define VGT_DBG_REG_11__pipe1_dr_MASK 0x00000004L -#define VGT_DBG_REG_11__pipe0_patch_rtr_MASK 0x00000008L -#define VGT_DBG_REG_11__pipe0_edge_rtr_MASK 0x00000010L -#define VGT_DBG_REG_11__pipe1_rtr_MASK 0x00000020L -#define VGT_DBG_REG_11__outer_parity_p0_q_MASK 0x00000040L -#define VGT_DBG_REG_11__parallel_parity_p0_q_MASK 0x00000080L -#define VGT_DBG_REG_11__first_ring_of_patch_p0_q_MASK 0x00000100L -#define VGT_DBG_REG_11__last_ring_of_patch_p0_q_MASK 0x00000200L -#define VGT_DBG_REG_11__last_edge_of_outer_ring_p0_q_MASK 0x00000400L -#define VGT_DBG_REG_11__last_point_of_outer_ring_p1_MASK 0x00000800L -#define VGT_DBG_REG_11__last_point_of_inner_ring_p1_MASK 0x00001000L -#define VGT_DBG_REG_11__outer_edge_tf_eq_one_p0_q_MASK 0x00002000L -#define VGT_DBG_REG_11__advance_outer_point_p1_MASK 0x00004000L -#define VGT_DBG_REG_11__advance_inner_point_p1_MASK 0x00008000L -#define VGT_DBG_REG_11__next_ring_is_rect_p0_q_MASK 0x00010000L -#define VGT_DBG_REG_11__pipe1_outer1_rtr_MASK 0x00020000L -#define VGT_DBG_REG_11__pipe1_outer2_rtr_MASK 0x00040000L -#define VGT_DBG_REG_11__pipe1_inner1_rtr_MASK 0x00080000L -#define VGT_DBG_REG_11__pipe1_inner2_rtr_MASK 0x00100000L -#define VGT_DBG_REG_11__pipe1_patch_rtr_MASK 0x00200000L -#define VGT_DBG_REG_11__pipe1_edge_rtr_MASK 0x00400000L -#define VGT_DBG_REG_11__use_stored_inner_q_ring3_MASK 0x00800000L -#define VGT_DBG_REG_11__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_12 -#define VGT_DBG_REG_12__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_12__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_12__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_12__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_12__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_12__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_12__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_12__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_12__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_12__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_12__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_12__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_12__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_12__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_12__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_12__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_12__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_12__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_12__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_12__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_12__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_12__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_12__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_12__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_13 -#define VGT_DBG_REG_13__Reserved8_MASK 0x00000001L -#define VGT_DBG_REG_13__Reserved7_MASK 0x00000002L -#define VGT_DBG_REG_13__Reserved6_MASK 0x00000004L -#define VGT_DBG_REG_13__Reserved5_MASK 0x00000008L -#define VGT_DBG_REG_13__Reserved4_MASK 0x00000010L -#define VGT_DBG_REG_13__Reserved3_MASK 0x00000020L -#define VGT_DBG_REG_13__Reserved2_MASK 0x00000040L -#define VGT_DBG_REG_13__Reserved1_MASK 0x00000080L -#define VGT_DBG_REG_13__pipe0_dr_MASK 0x00000100L -#define VGT_DBG_REG_13__pipe0_rtr_MASK 0x00000200L -#define VGT_DBG_REG_13__pipe1_outer_dr_MASK 0x00000400L -#define VGT_DBG_REG_13__pipe1_inner_dr_MASK 0x00000800L -#define VGT_DBG_REG_13__pipe2_outer_dr_MASK 0x00001000L -#define VGT_DBG_REG_13__pipe2_inner_dr_MASK 0x00002000L -#define VGT_DBG_REG_13__pipe3_outer_dr_MASK 0x00004000L -#define VGT_DBG_REG_13__pipe3_inner_dr_MASK 0x00008000L -#define VGT_DBG_REG_13__pipe4_outer_dr_MASK 0x00010000L -#define VGT_DBG_REG_13__pipe4_inner_dr_MASK 0x00020000L -#define VGT_DBG_REG_13__pipe5_outer_dr_MASK 0x00040000L -#define VGT_DBG_REG_13__pipe5_inner_dr_MASK 0x00080000L -#define VGT_DBG_REG_13__pipe2_outer_rtr_MASK 0x00100000L -#define VGT_DBG_REG_13__pipe2_inner_rtr_MASK 0x00200000L -#define VGT_DBG_REG_13__pipe3_outer_rtr_MASK 0x00400000L -#define VGT_DBG_REG_13__pipe3_inner_rtr_MASK 0x00800000L -#define VGT_DBG_REG_13__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_14 -#define VGT_DBG_REG_14__pipe4_outer_rtr_MASK 0x00000001L -#define VGT_DBG_REG_14__pipe4_inner_rtr_MASK 0x00000002L -#define VGT_DBG_REG_14__pipe5_outer_rtr_MASK 0x00000004L -#define VGT_DBG_REG_14__pipe5_inner_rtr_MASK 0x00000008L -#define VGT_DBG_REG_14__pg_con_outer_point1_rts_MASK 0x00000010L -#define VGT_DBG_REG_14__pg_con_outer_point2_rts_MASK 0x00000020L -#define VGT_DBG_REG_14__pg_con_inner_point1_rts_MASK 0x00000040L -#define VGT_DBG_REG_14__pg_con_inner_point2_rts_MASK 0x00000080L -#define VGT_DBG_REG_14__pg_patch_fifo_empty_MASK 0x00000100L -#define VGT_DBG_REG_14__pg_edge_fifo_empty_MASK 0x00000200L -#define VGT_DBG_REG_14__pg_inner3_perp_fifo_empty_MASK 0x00000400L -#define VGT_DBG_REG_14__pg_patch_fifo_full_MASK 0x00000800L -#define VGT_DBG_REG_14__pg_edge_fifo_full_MASK 0x00001000L -#define VGT_DBG_REG_14__pg_inner_perp_fifo_full_MASK 0x00002000L -#define VGT_DBG_REG_14__outer_ring_done_q_MASK 0x00004000L -#define VGT_DBG_REG_14__inner_ring_done_q_MASK 0x00008000L -#define VGT_DBG_REG_14__first_ring_of_patch_MASK 0x00010000L -#define VGT_DBG_REG_14__last_ring_of_patch_MASK 0x00020000L -#define VGT_DBG_REG_14__last_edge_of_outer_ring_MASK 0x00040000L -#define VGT_DBG_REG_14__last_point_of_outer_edge_MASK 0x00080000L -#define VGT_DBG_REG_14__last_edge_of_inner_ring_MASK 0x00100000L -#define VGT_DBG_REG_14__last_point_of_inner_edge_MASK 0x00200000L -#define VGT_DBG_REG_14__last_patch_of_tg_p0_q_MASK 0x00400000L -#define VGT_DBG_REG_14__event_null_special_p0_q_MASK 0x00800000L -#define VGT_DBG_REG_14__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_15 -#define VGT_DBG_REG_15__event_flag_p5_q_MASK 0x00000001L -#define VGT_DBG_REG_15__first_point_of_patch_p5_q_MASK 0x00000002L -#define VGT_DBG_REG_15__first_point_of_edge_p5_q_MASK 0x00000004L -#define VGT_DBG_REG_15__last_patch_of_tg_p5_q_MASK 0x00000008L -#define VGT_DBG_REG_15__tess_topology_p5_q_0_MASK 0x00000010L -#define VGT_DBG_REG_15__tess_topology_p5_q_1_MASK 0x00000020L -#define VGT_DBG_REG_15__pipe5_inner3_rtr_MASK 0x00000040L -#define VGT_DBG_REG_15__pipe5_inner2_rtr_MASK 0x00000080L -#define VGT_DBG_REG_15__pg_edge_fifo3_full_MASK 0x00000100L -#define VGT_DBG_REG_15__pg_edge_fifo2_full_MASK 0x00000200L -#define VGT_DBG_REG_15__pg_inner3_point_fifo_full_MASK 0x00000400L -#define VGT_DBG_REG_15__pg_outer3_point_fifo_full_MASK 0x00000800L -#define VGT_DBG_REG_15__pg_inner2_point_fifo_full_MASK 0x00001000L -#define VGT_DBG_REG_15__pg_outer2_point_fifo_full_MASK 0x00002000L -#define VGT_DBG_REG_15__pg_inner_point_fifo_full_MASK 0x00004000L -#define VGT_DBG_REG_15__pg_outer_point_fifo_full_MASK 0x00008000L -#define VGT_DBG_REG_15__inner2_fifos_rtr_MASK 0x00010000L -#define VGT_DBG_REG_15__inner_fifos_rtr_MASK 0x00020000L -#define VGT_DBG_REG_15__outer_fifos_rtr_MASK 0x00040000L -#define VGT_DBG_REG_15__fifos_rtr_MASK 0x00080000L -#define VGT_DBG_REG_15__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_15__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_15__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_15__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_16 -#define VGT_DBG_REG_16__pipe0_patch_dr_MASK 0x00000001L -#define VGT_DBG_REG_16__ring3_pipe1_dr_MASK 0x00000002L -#define VGT_DBG_REG_16__pipe1_dr_MASK 0x00000004L -#define VGT_DBG_REG_16__pipe2_dr_MASK 0x00000008L -#define VGT_DBG_REG_16__pipe0_patch_rtr_MASK 0x00000010L -#define VGT_DBG_REG_16__ring2_pipe1_dr_MASK 0x00000020L -#define VGT_DBG_REG_16__ring1_pipe1_dr_MASK 0x00000040L -#define VGT_DBG_REG_16__pipe2_rtr_MASK 0x00000080L -#define VGT_DBG_REG_16__pipe3_dr_MASK 0x00000100L -#define VGT_DBG_REG_16__pipe3_rtr_MASK 0x00000200L -#define VGT_DBG_REG_16__ring2_in_sync_q_MASK 0x00000400L -#define VGT_DBG_REG_16__ring1_in_sync_q_MASK 0x00000800L -#define VGT_DBG_REG_16__pipe1_patch_rtr_MASK 0x00001000L -#define VGT_DBG_REG_16__ring3_in_sync_q_MASK 0x00002000L -#define VGT_DBG_REG_16__tm_te11_event_rtr_MASK 0x00004000L -#define VGT_DBG_REG_16__first_prim_of_patch_q_MASK 0x00008000L -#define VGT_DBG_REG_16__con_prim_fifo_full_MASK 0x00010000L -#define VGT_DBG_REG_16__con_vert_fifo_full_MASK 0x00020000L -#define VGT_DBG_REG_16__con_prim_fifo_empty_MASK 0x00040000L -#define VGT_DBG_REG_16__con_vert_fifo_empty_MASK 0x00080000L -#define VGT_DBG_REG_16__last_patch_of_tg_p0_q_MASK 0x00100000L -#define VGT_DBG_REG_16__ring3_valid_p2_MASK 0x00200000L -#define VGT_DBG_REG_16__ring2_valid_p2_MASK 0x00400000L -#define VGT_DBG_REG_16__ring1_valid_p2_MASK 0x00800000L -#define VGT_DBG_REG_16__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_17 -#define VGT_DBG_REG_17__tess_type_p0_q_0_MASK 0x00000001L -#define VGT_DBG_REG_17__tess_type_p0_q_1_MASK 0x00000002L -#define VGT_DBG_REG_17__tess_topology_p0_q_0_MASK 0x00000004L -#define VGT_DBG_REG_17__tess_topology_p0_q_1_MASK 0x00000008L -#define VGT_DBG_REG_17__te11_out_vert_gs_en_MASK 0x00000010L -#define VGT_DBG_REG_17__con_ring3_busy_MASK 0x00000020L -#define VGT_DBG_REG_17__con_ring2_busy_MASK 0x00000040L -#define VGT_DBG_REG_17__con_ring1_busy_MASK 0x00000080L -#define VGT_DBG_REG_17__con_state_q_0_MASK 0x00000100L -#define VGT_DBG_REG_17__con_state_q_1_MASK 0x00000200L -#define VGT_DBG_REG_17__con_state_q_2_MASK 0x00000400L -#define VGT_DBG_REG_17__con_state_q_3_MASK 0x00000800L -#define VGT_DBG_REG_17__second_cycle_q_MASK 0x00001000L -#define VGT_DBG_REG_17__process_tri_middle_p0_q_MASK 0x00002000L -#define VGT_DBG_REG_17__process_tri_1st_2nd_half_p0_q_MASK 0x00004000L -#define VGT_DBG_REG_17__process_tri_center_poly_p0_q_MASK 0x00008000L -#define VGT_DBG_REG_17__pipe0_patch_dr_MASK 0x00010000L -#define VGT_DBG_REG_17__pipe0_edge_dr_MASK 0x00020000L -#define VGT_DBG_REG_17__pipe1_dr_MASK 0x00040000L -#define VGT_DBG_REG_17__pipe0_patch_rtr_MASK 0x00080000L -#define VGT_DBG_REG_17__pipe0_edge_rtr_MASK 0x00100000L -#define VGT_DBG_REG_17__pipe1_rtr_MASK 0x00200000L -#define VGT_DBG_REG_17__outer_parity_p0_q_MASK 0x00400000L -#define VGT_DBG_REG_17__parallel_parity_p0_q_MASK 0x00800000L -#define VGT_DBG_REG_17__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_18 -#define VGT_DBG_REG_18__first_ring_of_patch_p0_q_MASK 0x00000001L -#define VGT_DBG_REG_18__last_ring_of_patch_p0_q_MASK 0x00000002L -#define VGT_DBG_REG_18__last_edge_of_outer_ring_p0_q_MASK 0x00000004L -#define VGT_DBG_REG_18__last_point_of_outer_ring_p1_MASK 0x00000008L -#define VGT_DBG_REG_18__last_point_of_inner_ring_p1_MASK 0x00000010L -#define VGT_DBG_REG_18__outer_edge_tf_eq_one_p0_q_MASK 0x00000020L -#define VGT_DBG_REG_18__advance_outer_point_p1_MASK 0x00000040L -#define VGT_DBG_REG_18__advance_inner_point_p1_MASK 0x00000080L -#define VGT_DBG_REG_18__next_ring_is_rect_p0_q_MASK 0x00000100L -#define VGT_DBG_REG_18__pipe1_outer1_rtr_MASK 0x00000200L -#define VGT_DBG_REG_18__pipe1_outer2_rtr_MASK 0x00000400L -#define VGT_DBG_REG_18__pipe1_inner1_rtr_MASK 0x00000800L -#define VGT_DBG_REG_18__pipe1_inner2_rtr_MASK 0x00001000L -#define VGT_DBG_REG_18__pipe1_patch_rtr_MASK 0x00002000L -#define VGT_DBG_REG_18__pipe1_edge_rtr_MASK 0x00004000L -#define VGT_DBG_REG_18__use_stored_inner_q_ring1_MASK 0x00008000L -#define VGT_DBG_REG_18__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_18__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_18__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_18__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_18__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_18__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_18__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_18__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_19 -#define VGT_DBG_REG_19__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_19__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_19__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_19__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_19__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_19__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_19__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_19__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_19__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_19__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_19__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_19__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_19__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_19__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_19__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_19__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_19__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_19__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_19__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_19__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_19__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_19__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_19__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_19__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_20 -#define VGT_DBG_REG_20__Reserved16_MASK 0x00000001L -#define VGT_DBG_REG_20__Reserved15_MASK 0x00000002L -#define VGT_DBG_REG_20__Reserved14_MASK 0x00000004L -#define VGT_DBG_REG_20__Reserved13_MASK 0x00000008L -#define VGT_DBG_REG_20__Reserved12_MASK 0x00000010L -#define VGT_DBG_REG_20__Reserved11_MASK 0x00000020L -#define VGT_DBG_REG_20__Reserved10_MASK 0x00000040L -#define VGT_DBG_REG_20__Reserved9_MASK 0x00000080L -#define VGT_DBG_REG_20__Reserved8_MASK 0x00000100L -#define VGT_DBG_REG_20__Reserved7_MASK 0x00000200L -#define VGT_DBG_REG_20__Reserved6_MASK 0x00000400L -#define VGT_DBG_REG_20__Reserved5_MASK 0x00000800L -#define VGT_DBG_REG_20__Reserved4_MASK 0x00001000L -#define VGT_DBG_REG_20__Reserved3_MASK 0x00002000L -#define VGT_DBG_REG_20__Reserved2_MASK 0x00004000L -#define VGT_DBG_REG_20__Reserved1_MASK 0x00008000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_0_MASK 0x00010000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_1_MASK 0x00020000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_2_MASK 0x00040000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_3_MASK 0x00080000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_4_MASK 0x00100000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_5_MASK 0x00200000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_6_MASK 0x00400000L -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_7_MASK 0x00800000L -#define VGT_DBG_REG_20__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_21 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_8_MASK 0x00000001L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_9_MASK 0x00000002L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_10_MASK 0x00000004L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_11_MASK 0x00000008L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_12_MASK 0x00000010L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_13_MASK 0x00000020L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_14_MASK 0x00000040L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_15_MASK 0x00000080L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_16_MASK 0x00000100L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_17_MASK 0x00000200L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_18_MASK 0x00000400L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_19_MASK 0x00000800L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_20_MASK 0x00001000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_21_MASK 0x00002000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_22_MASK 0x00004000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_23_MASK 0x00008000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_24_MASK 0x00010000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_25_MASK 0x00020000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_26_MASK 0x00040000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_27_MASK 0x00080000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_28_MASK 0x00100000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_29_MASK 0x00200000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_30_MASK 0x00400000L -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_31_MASK 0x00800000L -#define VGT_DBG_REG_21__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_22 -#define VGT_DBG_REG_22__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_22__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_22__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_22__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_22__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_22__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_22__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_22__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_22__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_22__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_22__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_22__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_22__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_22__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_22__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_22__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_22__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_22__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_22__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_22__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_22__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_22__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_22__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_22__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_23 -#define VGT_DBG_REG_23__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_23__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_23__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_23__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_23__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_23__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_23__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_23__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_23__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_23__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_23__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_23__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_23__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_23__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_23__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_23__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_23__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_23__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_23__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_23__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_23__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_23__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_23__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_23__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_24 -#define VGT_DBG_REG_24__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_24__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_24__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_24__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_24__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_24__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_24__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_24__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_24__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_24__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_24__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_24__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_24__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_24__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_24__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_24__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_24__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_24__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_24__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_24__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_24__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_24__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_24__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_24__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_25 -#define VGT_DBG_REG_25__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_25__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_25__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_25__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_25__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_25__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_25__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_25__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_25__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_25__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_25__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_25__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_25__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_25__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_25__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_25__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_25__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_25__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_25__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_25__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_25__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_25__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_25__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_25__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_26 -#define VGT_DBG_REG_26__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_26__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_26__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_26__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_26__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_26__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_26__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_26__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_26__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_26__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_26__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_26__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_26__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_26__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_26__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_26__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_26__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_26__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_26__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_26__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_26__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_26__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_26__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_26__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_27 -#define VGT_DBG_REG_27__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_27__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_27__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_27__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_27__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_27__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_27__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_27__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_27__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_27__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_27__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_27__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_27__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_27__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_27__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_27__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_27__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_27__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_27__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_27__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_27__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_27__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_27__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_27__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_28 -#define VGT_DBG_REG_28__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_28__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_28__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_28__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_28__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_28__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_28__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_28__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_28__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_28__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_28__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_28__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_28__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_28__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_28__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_28__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_28__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_28__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_28__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_28__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_28__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_28__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_28__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_28__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_29 -#define VGT_DBG_REG_29__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_29__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_29__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_29__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_29__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_29__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_29__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_29__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_29__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_29__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_29__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_29__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_29__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_29__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_29__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_29__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_29__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_29__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_29__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_29__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_29__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_29__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_29__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_29__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_30 -#define VGT_DBG_REG_30__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_30__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_30__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_30__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_30__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_30__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_30__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_30__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_30__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_30__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_30__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_30__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_30__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_30__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_30__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_30__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_30__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_30__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_30__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_30__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_30__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_30__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_30__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_30__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_31 -#define VGT_DBG_REG_31__Reserved23_MASK 0x00000001L -#define VGT_DBG_REG_31__Reserved22_MASK 0x00000002L -#define VGT_DBG_REG_31__Reserved21_MASK 0x00000004L -#define VGT_DBG_REG_31__Reserved20_MASK 0x00000008L -#define VGT_DBG_REG_31__Reserved19_MASK 0x00000010L -#define VGT_DBG_REG_31__Reserved18_MASK 0x00000020L -#define VGT_DBG_REG_31__Reserved17_MASK 0x00000040L -#define VGT_DBG_REG_31__Reserved16_MASK 0x00000080L -#define VGT_DBG_REG_31__Reserved15_MASK 0x00000100L -#define VGT_DBG_REG_31__Reserved14_MASK 0x00000200L -#define VGT_DBG_REG_31__Reserved13_MASK 0x00000400L -#define VGT_DBG_REG_31__Reserved12_MASK 0x00000800L -#define VGT_DBG_REG_31__Reserved11_MASK 0x00001000L -#define VGT_DBG_REG_31__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_31__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_31__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_31__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_31__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_31__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_31__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_31__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_31__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_31__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_31__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_32 -#define VGT_DBG_REG_32__vgt_busy_extended_MASK 0x00000001L -#define VGT_DBG_REG_32__Reserved8_MASK 0x00000002L -#define VGT_DBG_REG_32__vgt_busy_MASK 0x00000004L -#define VGT_DBG_REG_32__Reserved7_MASK 0x00000008L -#define VGT_DBG_REG_32__Reserved6_MASK 0x00000010L -#define VGT_DBG_REG_32__Reserved5_MASK 0x00000020L -#define VGT_DBG_REG_32__Reserved4_MASK 0x00000040L -#define VGT_DBG_REG_32__Reserved3_MASK 0x00000080L -#define VGT_DBG_REG_32__pi_busy_MASK 0x00000100L -#define VGT_DBG_REG_32__vr_pi_busy_MASK 0x00000200L -#define VGT_DBG_REG_32__pt_pi_busy_MASK 0x00000400L -#define VGT_DBG_REG_32__te_pi_busy_MASK 0x00000800L -#define VGT_DBG_REG_32__gs_busy_MASK 0x00001000L -#define VGT_DBG_REG_32__rcm_busy_MASK 0x00002000L -#define VGT_DBG_REG_32__tm_busy_MASK 0x00004000L -#define VGT_DBG_REG_32__cm_busy_MASK 0x00008000L -#define VGT_DBG_REG_32__gog_busy_MASK 0x00010000L -#define VGT_DBG_REG_32__frmt_busy_MASK 0x00020000L -#define VGT_DBG_REG_32__Reserved2_MASK 0x00040000L -#define VGT_DBG_REG_32__te11_pi_busy_MASK 0x00080000L -#define VGT_DBG_REG_32__Reserved1_MASK 0x00100000L -#define VGT_DBG_REG_32__combined_out_busy_MASK 0x00200000L -#define VGT_DBG_REG_32__spi_vs_interfaces_busy_MASK 0x00400000L -#define VGT_DBG_REG_32__pa_interfaces_busy_MASK 0x00800000L -#define VGT_DBG_REG_32__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_33 -#define VGT_DBG_REG_33__reg_clk_busy_MASK 0x00000001L -#define VGT_DBG_REG_33__Reserved13_MASK 0x00000002L -#define VGT_DBG_REG_33__core_clk_busy_MASK 0x00000004L -#define VGT_DBG_REG_33__gs_clk_busy_MASK 0x00000008L -#define VGT_DBG_REG_33__Reserved12_MASK 0x00000010L -#define VGT_DBG_REG_33__sclk_core_vld_MASK 0x00000020L -#define VGT_DBG_REG_33__sclk_gs_vld_MASK 0x00000040L -#define VGT_DBG_REG_33__Reserved11_MASK 0x00000080L -#define VGT_DBG_REG_33__Reserved10_MASK 0x00000100L -#define VGT_DBG_REG_33__Reserved9_MASK 0x00000200L -#define VGT_DBG_REG_33__Reserved8_MASK 0x00000400L -#define VGT_DBG_REG_33__Reserved7_MASK 0x00000800L -#define VGT_DBG_REG_33__Reserved6_MASK 0x00001000L -#define VGT_DBG_REG_33__Reserved5_MASK 0x00002000L -#define VGT_DBG_REG_33__Reserved4_MASK 0x00004000L -#define VGT_DBG_REG_33__Reserved3_MASK 0x00008000L -#define VGT_DBG_REG_33__Reserved2_MASK 0x00010000L -#define VGT_DBG_REG_33__Reserved1_MASK 0x00020000L -#define VGT_DBG_REG_33__pi_vr_valid_MASK 0x00040000L -#define VGT_DBG_REG_33__vr_pi_read_MASK 0x00080000L -#define VGT_DBG_REG_33__pi_pt_valid_MASK 0x00100000L -#define VGT_DBG_REG_33__pt_pi_read_MASK 0x00200000L -#define VGT_DBG_REG_33__pi_te_valid_MASK 0x00400000L -#define VGT_DBG_REG_33__te_grp_read_MASK 0x00800000L -#define VGT_DBG_REG_33__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_34 -#define VGT_DBG_REG_34__vr_out_indx_valid_MASK 0x00000001L -#define VGT_DBG_REG_34__Reserved5_MASK 0x00000002L -#define VGT_DBG_REG_34__vr_out_prim_valid_MASK 0x00000004L -#define VGT_DBG_REG_34__Reserved4_MASK 0x00000008L -#define VGT_DBG_REG_34__pt_out_indx_valid_MASK 0x00000010L -#define VGT_DBG_REG_34__Reserved3_MASK 0x00000020L -#define VGT_DBG_REG_34__pt_out_prim_valid_MASK 0x00000040L -#define VGT_DBG_REG_34__Reserved2_MASK 0x00000080L -#define VGT_DBG_REG_34__te_out_data_valid_MASK 0x00000100L -#define VGT_DBG_REG_34__Reserved1_MASK 0x00000200L -#define VGT_DBG_REG_34__pi_gs_valid_MASK 0x00000400L -#define VGT_DBG_REG_34__gs_pi_read_MASK 0x00000800L -#define VGT_DBG_REG_34__gog_out_indx_valid_MASK 0x00001000L -#define VGT_DBG_REG_34__out_indx_read_MASK 0x00002000L -#define VGT_DBG_REG_34__gog_out_prim_valid_MASK 0x00004000L -#define VGT_DBG_REG_34__out_prim_read_MASK 0x00008000L -#define VGT_DBG_REG_34__hs_grp_busy_MASK 0x00010000L -#define VGT_DBG_REG_34__hs_noif_busy_MASK 0x00020000L -#define VGT_DBG_REG_34__tfmmIsBusy_MASK 0x00040000L -#define VGT_DBG_REG_34__lsVertIfBusy_0_MASK 0x00080000L -#define VGT_DBG_REG_34__te11_hs_tess_input_rtr_MASK 0x00100000L -#define VGT_DBG_REG_34__lsWaveIfBusy_0_MASK 0x00200000L -#define VGT_DBG_REG_34__hs_te11_tess_input_rts_MASK 0x00400000L -#define VGT_DBG_REG_34__grpModBusy_MASK 0x00800000L -#define VGT_DBG_REG_34__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_35 -#define VGT_DBG_REG_35__lsVertFifoEmpty_MASK 0x00000001L -#define VGT_DBG_REG_35__lsWaveFifoEmpty_MASK 0x00000002L -#define VGT_DBG_REG_35__hsVertFifoEmpty_MASK 0x00000004L -#define VGT_DBG_REG_35__hsWaveFifoEmpty_MASK 0x00000008L -#define VGT_DBG_REG_35__hsInputFifoEmpty_MASK 0x00000010L -#define VGT_DBG_REG_35__hsTifFifoEmpty_MASK 0x00000020L -#define VGT_DBG_REG_35__lsVertFifoFull_MASK 0x00000040L -#define VGT_DBG_REG_35__lsWaveFifoFull_MASK 0x00000080L -#define VGT_DBG_REG_35__hsVertFifoFull_MASK 0x00000100L -#define VGT_DBG_REG_35__hsWaveFifoFull_MASK 0x00000200L -#define VGT_DBG_REG_35__hsInputFifoFull_MASK 0x00000400L -#define VGT_DBG_REG_35__hsTifFifoFull_MASK 0x00000800L -#define VGT_DBG_REG_35__p0_rtr_MASK 0x00001000L -#define VGT_DBG_REG_35__p1_rtr_MASK 0x00002000L -#define VGT_DBG_REG_35__p0_dr_MASK 0x00004000L -#define VGT_DBG_REG_35__p1_dr_MASK 0x00008000L -#define VGT_DBG_REG_35__p0_rts_MASK 0x00010000L -#define VGT_DBG_REG_35__p1_rts_MASK 0x00020000L -#define VGT_DBG_REG_35__ls_sh_id_MASK 0x00040000L -#define VGT_DBG_REG_35__lsFwaveFlag_MASK 0x00080000L -#define VGT_DBG_REG_35__lsWaveSendFlush_MASK 0x00100000L -#define VGT_DBG_REG_35__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_35__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_35__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_36 -#define VGT_DBG_REG_36__lsTgRelInd_0_MASK 0x00000001L -#define VGT_DBG_REG_36__lsTgRelInd_1_MASK 0x00000002L -#define VGT_DBG_REG_36__lsTgRelInd_2_MASK 0x00000004L -#define VGT_DBG_REG_36__lsTgRelInd_3_MASK 0x00000008L -#define VGT_DBG_REG_36__lsTgRelInd_4_MASK 0x00000010L -#define VGT_DBG_REG_36__lsTgRelInd_5_MASK 0x00000020L -#define VGT_DBG_REG_36__lsTgRelInd_6_MASK 0x00000040L -#define VGT_DBG_REG_36__lsTgRelInd_7_MASK 0x00000080L -#define VGT_DBG_REG_36__lsTgRelInd_8_MASK 0x00000100L -#define VGT_DBG_REG_36__lsTgRelInd_9_MASK 0x00000200L -#define VGT_DBG_REG_36__lsTgRelInd_10_MASK 0x00000400L -#define VGT_DBG_REG_36__lsTgRelInd_11_MASK 0x00000800L -#define VGT_DBG_REG_36__lsWaveRelInd_0_MASK 0x00001000L -#define VGT_DBG_REG_36__lsWaveRelInd_1_MASK 0x00002000L -#define VGT_DBG_REG_36__lsWaveRelInd_2_MASK 0x00004000L -#define VGT_DBG_REG_36__lsWaveRelInd_3_MASK 0x00008000L -#define VGT_DBG_REG_36__lsWaveRelInd_4_MASK 0x00010000L -#define VGT_DBG_REG_36__lsWaveRelInd_5_MASK 0x00020000L -#define VGT_DBG_REG_36__lsPatchCnt_0_MASK 0x00040000L -#define VGT_DBG_REG_36__lsPatchCnt_1_MASK 0x00080000L -#define VGT_DBG_REG_36__lsPatchCnt_2_MASK 0x00100000L -#define VGT_DBG_REG_36__lsPatchCnt_3_MASK 0x00200000L -#define VGT_DBG_REG_36__lsPatchCnt_4_MASK 0x00400000L -#define VGT_DBG_REG_36__lsPatchCnt_5_MASK 0x00800000L -#define VGT_DBG_REG_36__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_37 -#define VGT_DBG_REG_37__lsPatchCnt_6_MASK 0x00000001L -#define VGT_DBG_REG_37__lsPatchCnt_7_MASK 0x00000002L -#define VGT_DBG_REG_37__hsWaveRelInd_0_MASK 0x00000004L -#define VGT_DBG_REG_37__hsWaveRelInd_1_MASK 0x00000008L -#define VGT_DBG_REG_37__hsWaveRelInd_2_MASK 0x00000010L -#define VGT_DBG_REG_37__hsWaveRelInd_3_MASK 0x00000020L -#define VGT_DBG_REG_37__hsWaveRelInd_4_MASK 0x00000040L -#define VGT_DBG_REG_37__hsWaveRelInd_5_MASK 0x00000080L -#define VGT_DBG_REG_37__hsPatchCnt_0_MASK 0x00000100L -#define VGT_DBG_REG_37__hsPatchCnt_1_MASK 0x00000200L -#define VGT_DBG_REG_37__hsPatchCnt_2_MASK 0x00000400L -#define VGT_DBG_REG_37__hsPatchCnt_3_MASK 0x00000800L -#define VGT_DBG_REG_37__hsPatchCnt_4_MASK 0x00001000L -#define VGT_DBG_REG_37__hsPatchCnt_5_MASK 0x00002000L -#define VGT_DBG_REG_37__hsPatchCnt_6_MASK 0x00004000L -#define VGT_DBG_REG_37__hsPatchCnt_7_MASK 0x00008000L -#define VGT_DBG_REG_37__hsPrimId_15_0_0_MASK 0x00010000L -#define VGT_DBG_REG_37__hsPrimId_15_0_1_MASK 0x00020000L -#define VGT_DBG_REG_37__hsPrimId_15_0_2_MASK 0x00040000L -#define VGT_DBG_REG_37__hsPrimId_15_0_3_MASK 0x00080000L -#define VGT_DBG_REG_37__hsPrimId_15_0_4_MASK 0x00100000L -#define VGT_DBG_REG_37__hsPrimId_15_0_5_MASK 0x00200000L -#define VGT_DBG_REG_37__hsPrimId_15_0_6_MASK 0x00400000L -#define VGT_DBG_REG_37__hsPrimId_15_0_7_MASK 0x00800000L -#define VGT_DBG_REG_37__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_38 -#define VGT_DBG_REG_38__hsPrimId_15_0_8_MASK 0x00000001L -#define VGT_DBG_REG_38__hsPrimId_15_0_9_MASK 0x00000002L -#define VGT_DBG_REG_38__hsPrimId_15_0_10_MASK 0x00000004L -#define VGT_DBG_REG_38__hsPrimId_15_0_11_MASK 0x00000008L -#define VGT_DBG_REG_38__hsPrimId_15_0_12_MASK 0x00000010L -#define VGT_DBG_REG_38__hsPrimId_15_0_13_MASK 0x00000020L -#define VGT_DBG_REG_38__hsPrimId_15_0_14_MASK 0x00000040L -#define VGT_DBG_REG_38__hsPrimId_15_0_15_MASK 0x00000080L -#define VGT_DBG_REG_38__hsCpCnt_0_MASK 0x00000100L -#define VGT_DBG_REG_38__hsCpCnt_1_MASK 0x00000200L -#define VGT_DBG_REG_38__hsCpCnt_2_MASK 0x00000400L -#define VGT_DBG_REG_38__hsCpCnt_3_MASK 0x00000800L -#define VGT_DBG_REG_38__hsCpCnt_4_MASK 0x00001000L -#define VGT_DBG_REG_38__hsWaveSendFlush_MASK 0x00002000L -#define VGT_DBG_REG_38__hsFwaveFlag_MASK 0x00004000L -#define VGT_DBG_REG_38__Reserved4_MASK 0x00008000L -#define VGT_DBG_REG_38__Reserved3_MASK 0x00010000L -#define VGT_DBG_REG_38__Reserved2_MASK 0x00020000L -#define VGT_DBG_REG_38__Reserved1_MASK 0x00040000L -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_0_MASK 0x00080000L -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_1_MASK 0x00100000L -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_2_MASK 0x00200000L -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_3_MASK 0x00400000L -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_4_MASK 0x00800000L -#define VGT_DBG_REG_38__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_39 -#define VGT_DBG_REG_39__Reserved9_MASK 0x00000001L -#define VGT_DBG_REG_39__Reserved8_MASK 0x00000002L -#define VGT_DBG_REG_39__Reserved7_MASK 0x00000004L -#define VGT_DBG_REG_39__hsVertCreditCnt_0_0_MASK 0x00000008L -#define VGT_DBG_REG_39__hsVertCreditCnt_0_2_MASK 0x00000010L -#define VGT_DBG_REG_39__hsVertCreditCnt_0_3_MASK 0x00000020L -#define VGT_DBG_REG_39__hsVertCreditCnt_0_4_MASK 0x00000040L -#define VGT_DBG_REG_39__hsVertCreditCnt_0_5_MASK 0x00000080L -#define VGT_DBG_REG_39__Reserved6_MASK 0x00000100L -#define VGT_DBG_REG_39__Reserved5_MASK 0x00000200L -#define VGT_DBG_REG_39__Reserved4_MASK 0x00000400L -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_0_MASK 0x00000800L -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_1_MASK 0x00001000L -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_2_MASK 0x00002000L -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_3_MASK 0x00004000L -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_4_MASK 0x00008000L -#define VGT_DBG_REG_39__Reserved3_MASK 0x00010000L -#define VGT_DBG_REG_39__Reserved2_MASK 0x00020000L -#define VGT_DBG_REG_39__Reserved1_MASK 0x00040000L -#define VGT_DBG_REG_39__lsVertCreditCnt_0_0_MASK 0x00080000L -#define VGT_DBG_REG_39__lsVertCreditCnt_0_1_MASK 0x00100000L -#define VGT_DBG_REG_39__lsVertCreditCnt_0_2_MASK 0x00200000L -#define VGT_DBG_REG_39__lsVertCreditCnt_0_3_MASK 0x00400000L -#define VGT_DBG_REG_39__lsVertCreditCnt_0_4_MASK 0x00800000L -#define VGT_DBG_REG_39__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_40 -#define VGT_DBG_REG_40__debug_BASE_0_MASK 0x00000001L -#define VGT_DBG_REG_40__debug_BASE_1_MASK 0x00000002L -#define VGT_DBG_REG_40__debug_BASE_2_MASK 0x00000004L -#define VGT_DBG_REG_40__debug_BASE_3_MASK 0x00000008L -#define VGT_DBG_REG_40__debug_BASE_4_MASK 0x00000010L -#define VGT_DBG_REG_40__debug_BASE_5_MASK 0x00000020L -#define VGT_DBG_REG_40__debug_BASE_6_MASK 0x00000040L -#define VGT_DBG_REG_40__debug_BASE_7_MASK 0x00000080L -#define VGT_DBG_REG_40__debug_BASE_8_MASK 0x00000100L -#define VGT_DBG_REG_40__debug_BASE_9_MASK 0x00000200L -#define VGT_DBG_REG_40__debug_BASE_10_MASK 0x00000400L -#define VGT_DBG_REG_40__debug_BASE_11_MASK 0x00000800L -#define VGT_DBG_REG_40__debug_BASE_12_MASK 0x00001000L -#define VGT_DBG_REG_40__debug_BASE_13_MASK 0x00002000L -#define VGT_DBG_REG_40__debug_BASE_14_MASK 0x00004000L -#define VGT_DBG_REG_40__debug_BASE_15_MASK 0x00008000L -#define VGT_DBG_REG_40__debug_SIZE_0_MASK 0x00010000L -#define VGT_DBG_REG_40__debug_SIZE_1_MASK 0x00020000L -#define VGT_DBG_REG_40__debug_SIZE_2_MASK 0x00040000L -#define VGT_DBG_REG_40__debug_SIZE_3_MASK 0x00080000L -#define VGT_DBG_REG_40__debug_SIZE_4_MASK 0x00100000L -#define VGT_DBG_REG_40__debug_SIZE_5_MASK 0x00200000L -#define VGT_DBG_REG_40__debug_SIZE_6_MASK 0x00400000L -#define VGT_DBG_REG_40__debug_SIZE_7_MASK 0x00800000L -#define VGT_DBG_REG_40__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_41 -#define VGT_DBG_REG_41__debug_SIZE_8_MASK 0x00000001L -#define VGT_DBG_REG_41__debug_SIZE_9_MASK 0x00000002L -#define VGT_DBG_REG_41__debug_SIZE_10_MASK 0x00000004L -#define VGT_DBG_REG_41__debug_SIZE_11_MASK 0x00000008L -#define VGT_DBG_REG_41__debug_SIZE_12_MASK 0x00000010L -#define VGT_DBG_REG_41__debug_SIZE_13_MASK 0x00000020L -#define VGT_DBG_REG_41__debug_SIZE_14_MASK 0x00000040L -#define VGT_DBG_REG_41__debug_SIZE_15_MASK 0x00000080L -#define VGT_DBG_REG_41__debug_tfmmFifoEmpty_MASK 0x00000100L -#define VGT_DBG_REG_41__debug_tfmmFifoFull_MASK 0x00000200L -#define VGT_DBG_REG_41__hs_pipe0_dr_MASK 0x00000400L -#define VGT_DBG_REG_41__hs_pipe0_rtr_MASK 0x00000800L -#define VGT_DBG_REG_41__hs_pipe1_rtr_MASK 0x00001000L -#define VGT_DBG_REG_41__Reserved10_MASK 0x00002000L -#define VGT_DBG_REG_41__Reserved9_MASK 0x00004000L -#define VGT_DBG_REG_41__Reserved8_MASK 0x00008000L -#define VGT_DBG_REG_41__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_41__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_41__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_41__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_41__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_41__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_41__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_41__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_42 -#define VGT_DBG_REG_42__TF_addr_0_MASK 0x00000001L -#define VGT_DBG_REG_42__TF_addr_1_MASK 0x00000002L -#define VGT_DBG_REG_42__TF_addr_2_MASK 0x00000004L -#define VGT_DBG_REG_42__TF_addr_3_MASK 0x00000008L -#define VGT_DBG_REG_42__TF_addr_4_MASK 0x00000010L -#define VGT_DBG_REG_42__TF_addr_5_MASK 0x00000020L -#define VGT_DBG_REG_42__TF_addr_6_MASK 0x00000040L -#define VGT_DBG_REG_42__TF_addr_7_MASK 0x00000080L -#define VGT_DBG_REG_42__TF_addr_8_MASK 0x00000100L -#define VGT_DBG_REG_42__TF_addr_9_MASK 0x00000200L -#define VGT_DBG_REG_42__TF_addr_10_MASK 0x00000400L -#define VGT_DBG_REG_42__TF_addr_11_MASK 0x00000800L -#define VGT_DBG_REG_42__TF_addr_12_MASK 0x00001000L -#define VGT_DBG_REG_42__TF_addr_13_MASK 0x00002000L -#define VGT_DBG_REG_42__TF_addr_14_MASK 0x00004000L -#define VGT_DBG_REG_42__TF_addr_15_MASK 0x00008000L -#define VGT_DBG_REG_42__rcm_busy_q_MASK 0x00010000L -#define VGT_DBG_REG_42__rcm_noif_busy_q_MASK 0x00020000L -#define VGT_DBG_REG_42__r1_inst_rtr_MASK 0x00040000L -#define VGT_DBG_REG_42__spi_gsprim_fifo_busy_q_MASK 0x00080000L -#define VGT_DBG_REG_42__spi_esvert_fifo_busy_q_MASK 0x00100000L -#define VGT_DBG_REG_42__gs_tbl_valid_r3_q_MASK 0x00200000L -#define VGT_DBG_REG_42__valid_r0_q_MASK 0x00400000L -#define VGT_DBG_REG_42__valid_r1_q_MASK 0x00800000L -#define VGT_DBG_REG_42__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_43 -#define VGT_DBG_REG_43__valid_r2_MASK 0x00000001L -#define VGT_DBG_REG_43__valid_r2_q_MASK 0x00000002L -#define VGT_DBG_REG_43__r0_rtr_MASK 0x00000004L -#define VGT_DBG_REG_43__r1_rtr_MASK 0x00000008L -#define VGT_DBG_REG_43__r2_indx_rtr_MASK 0x00000010L -#define VGT_DBG_REG_43__r2_rtr_MASK 0x00000020L -#define VGT_DBG_REG_43__es_gs_rtr_MASK 0x00000040L -#define VGT_DBG_REG_43__gs_event_fifo_rtr_MASK 0x00000080L -#define VGT_DBG_REG_43__tm_rcm_gs_event_rtr_MASK 0x00000100L -#define VGT_DBG_REG_43__gs_tbl_r3_rtr_MASK 0x00000200L -#define VGT_DBG_REG_43__prim_skid_fifo_empty_MASK 0x00000400L -#define VGT_DBG_REG_43__VGT_SPI_gsprim_rtr_q_MASK 0x00000800L -#define VGT_DBG_REG_43__tm_rcm_gs_tbl_rtr_MASK 0x00001000L -#define VGT_DBG_REG_43__tm_rcm_es_tbl_rtr_MASK 0x00002000L -#define VGT_DBG_REG_43__VGT_SPI_esvert_rtr_q_MASK 0x00004000L -#define VGT_DBG_REG_43__r2_no_bp_rtr_MASK 0x00008000L -#define VGT_DBG_REG_43__hold_for_es_flush_MASK 0x00010000L -#define VGT_DBG_REG_43__gs_event_fifo_empty_MASK 0x00020000L -#define VGT_DBG_REG_43__gsprim_buff_empty_q_MASK 0x00040000L -#define VGT_DBG_REG_43__gsprim_buff_full_q_MASK 0x00080000L -#define VGT_DBG_REG_43__te_prim_fifo_empty_MASK 0x00100000L -#define VGT_DBG_REG_43__te_prim_fifo_full_MASK 0x00200000L -#define VGT_DBG_REG_43__te_vert_fifo_empty_MASK 0x00400000L -#define VGT_DBG_REG_43__te_vert_fifo_full_MASK 0x00800000L -#define VGT_DBG_REG_43__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_44 -#define VGT_DBG_REG_44__indices_to_send_r2_q_0_MASK 0x00000001L -#define VGT_DBG_REG_44__indices_to_send_r2_q_1_MASK 0x00000002L -#define VGT_DBG_REG_44__valid_indices_r3_MASK 0x00000004L -#define VGT_DBG_REG_44__gs_eov_r3_MASK 0x00000008L -#define VGT_DBG_REG_44__eop_indx_r3_MASK 0x00000010L -#define VGT_DBG_REG_44__eop_prim_r3_MASK 0x00000020L -#define VGT_DBG_REG_44__es_eov_r3_MASK 0x00000040L -#define VGT_DBG_REG_44__es_tbl_state_r3_q_0_MASK 0x00000080L -#define VGT_DBG_REG_44__pending_es_send_r3_q_MASK 0x00000100L -#define VGT_DBG_REG_44__pending_es_flush_r3_MASK 0x00000200L -#define VGT_DBG_REG_44__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x00000400L -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_0_MASK 0x00000800L -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_1_MASK 0x00001000L -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_2_MASK 0x00002000L -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_3_MASK 0x00004000L -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_4_MASK 0x00008000L -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_5_MASK 0x00010000L -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_6_MASK 0x00020000L -#define VGT_DBG_REG_44__gs_tbl_eop_r3_q_MASK 0x00040000L -#define VGT_DBG_REG_44__gs_tbl_state_r3_q_0_MASK 0x00080000L -#define VGT_DBG_REG_44__gs_tbl_state_r3_q_1_MASK 0x00100000L -#define VGT_DBG_REG_44__gs_tbl_state_r3_q_2_MASK 0x00200000L -#define VGT_DBG_REG_44__gs_pending_state_r3_q_MASK 0x00400000L -#define VGT_DBG_REG_44__invalidate_rb_roll_over_q_MASK 0x00800000L -#define VGT_DBG_REG_44__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_45 -#define VGT_DBG_REG_45__gs_instancing_state_q_MASK 0x00000001L -#define VGT_DBG_REG_45__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x00000002L -#define VGT_DBG_REG_45__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x00000004L -#define VGT_DBG_REG_45__pre_r0_rtr_MASK 0x00000008L -#define VGT_DBG_REG_45__valid_r3_q_MASK 0x00000010L -#define VGT_DBG_REG_45__valid_pre_r0_q_MASK 0x00000020L -#define VGT_DBG_REG_45__Reserved3_MASK 0x00000040L -#define VGT_DBG_REG_45__off_chip_hs_r2_q_MASK 0x00000080L -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_0_MASK 0x00000100L -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_1_MASK 0x00000200L -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_2_MASK 0x00000400L -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_3_MASK 0x00000800L -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_4_MASK 0x00001000L -#define VGT_DBG_REG_45__eopg_r2_q_MASK 0x00002000L -#define VGT_DBG_REG_45__eotg_r2_q_MASK 0x00004000L -#define VGT_DBG_REG_45__onchip_gs_en_r0_q_0_MASK 0x00008000L -#define VGT_DBG_REG_45__onchip_gs_en_r0_q_1_MASK 0x00010000L -#define VGT_DBG_REG_45__Reserved2_MASK 0x00020000L -#define VGT_DBG_REG_45__Reserved1_MASK 0x00040000L -#define VGT_DBG_REG_45__rcm_mem_gsprim_re_qq_MASK 0x00080000L -#define VGT_DBG_REG_45__rcm_mem_gsprim_re_q_MASK 0x00100000L -#define VGT_DBG_REG_45__gs_rb_space_avail_r3_q_9_0_0_MASK 0x00200000L -#define VGT_DBG_REG_45__gs_rb_space_avail_r3_q_9_0_1_MASK 0x00400000L -#define VGT_DBG_REG_45__gs_rb_space_avail_r3_q_9_0_2_MASK 0x00800000L -#define VGT_DBG_REG_45__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_46 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_3_MASK 0x00000001L -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_4_MASK 0x00000002L -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_5_MASK 0x00000004L -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_6_MASK 0x00000008L -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_7_MASK 0x00000010L -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_8_MASK 0x00000020L -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_9_MASK 0x00000040L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_0_MASK 0x00000080L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_1_MASK 0x00000100L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_2_MASK 0x00000200L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_3_MASK 0x00000400L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_4_MASK 0x00000800L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_5_MASK 0x00001000L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_6_MASK 0x00002000L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_7_MASK 0x00004000L -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_8_MASK 0x00008000L -#define VGT_DBG_REG_46__tm_busy_q_MASK 0x00010000L -#define VGT_DBG_REG_46__tm_noif_busy_q_MASK 0x00020000L -#define VGT_DBG_REG_46__tm_out_busy_q_MASK 0x00040000L -#define VGT_DBG_REG_46__es_rb_dealloc_fifo_busy_MASK 0x00080000L -#define VGT_DBG_REG_46__vs_dealloc_tbl_busy_MASK 0x00100000L -#define VGT_DBG_REG_46__Reserved1_MASK 0x00200000L -#define VGT_DBG_REG_46__spi_gsthread_fifo_busy_MASK 0x00400000L -#define VGT_DBG_REG_46__spi_esthread_fifo_busy_MASK 0x00800000L -#define VGT_DBG_REG_46__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_47 -#define VGT_DBG_REG_47__hold_eswave_MASK 0x00000001L -#define VGT_DBG_REG_47__es_rb_roll_over_r3_MASK 0x00000002L -#define VGT_DBG_REG_47__counters_busy_r0_MASK 0x00000004L -#define VGT_DBG_REG_47__counters_avail_r0_MASK 0x00000008L -#define VGT_DBG_REG_47__counters_available_r0_MASK 0x00000010L -#define VGT_DBG_REG_47__vs_event_fifo_rtr_MASK 0x00000020L -#define VGT_DBG_REG_47__VGT_SPI_gsthread_rtr_q_MASK 0x00000040L -#define VGT_DBG_REG_47__VGT_SPI_esthread_rtr_q_MASK 0x00000080L -#define VGT_DBG_REG_47__gs_issue_rtr_MASK 0x00000100L -#define VGT_DBG_REG_47__tm_pt_event_rtr_MASK 0x00000200L -#define VGT_DBG_REG_47__Reserved1_MASK 0x00000400L -#define VGT_DBG_REG_47__gs_r0_rtr_MASK 0x00000800L -#define VGT_DBG_REG_47__es_r0_rtr_MASK 0x00001000L -#define VGT_DBG_REG_47__gog_tm_vs_event_rtr_MASK 0x00002000L -#define VGT_DBG_REG_47__tm_rcm_gs_event_rtr_MASK 0x00004000L -#define VGT_DBG_REG_47__tm_rcm_gs_tbl_rtr_MASK 0x00008000L -#define VGT_DBG_REG_47__tm_rcm_es_tbl_rtr_MASK 0x00010000L -#define VGT_DBG_REG_47__vs_event_fifo_empty_MASK 0x00020000L -#define VGT_DBG_REG_47__vs_event_fifo_full_MASK 0x00040000L -#define VGT_DBG_REG_47__es_rb_dealloc_fifo_full_MASK 0x00080000L -#define VGT_DBG_REG_47__vs_dealloc_tbl_full_MASK 0x00100000L -#define VGT_DBG_REG_47__send_event_q_MASK 0x00200000L -#define VGT_DBG_REG_47__es_tbl_empty_MASK 0x00400000L -#define VGT_DBG_REG_47__no_active_states_r0_MASK 0x00800000L -#define VGT_DBG_REG_47__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_48 -#define VGT_DBG_REG_48__gs_state0_r0_q_0_MASK 0x00000001L -#define VGT_DBG_REG_48__gs_state0_r0_q_1_MASK 0x00000002L -#define VGT_DBG_REG_48__gs_state0_r0_q_2_MASK 0x00000004L -#define VGT_DBG_REG_48__gs_state1_r0_q_0_MASK 0x00000008L -#define VGT_DBG_REG_48__gs_state1_r0_q_1_MASK 0x00000010L -#define VGT_DBG_REG_48__gs_state1_r0_q_2_MASK 0x00000020L -#define VGT_DBG_REG_48__gs_state2_r0_q_0_MASK 0x00000040L -#define VGT_DBG_REG_48__gs_state2_r0_q_1_MASK 0x00000080L -#define VGT_DBG_REG_48__gs_state2_r0_q_2_MASK 0x00000100L -#define VGT_DBG_REG_48__gs_state3_r0_q_0_MASK 0x00000200L -#define VGT_DBG_REG_48__gs_state3_r0_q_1_MASK 0x00000400L -#define VGT_DBG_REG_48__gs_state3_r0_q_2_MASK 0x00000800L -#define VGT_DBG_REG_48__gs_state4_r0_q_0_MASK 0x00001000L -#define VGT_DBG_REG_48__gs_state4_r0_q_1_MASK 0x00002000L -#define VGT_DBG_REG_48__gs_state4_r0_q_2_MASK 0x00004000L -#define VGT_DBG_REG_48__gs_state5_r0_q_0_MASK 0x00008000L -#define VGT_DBG_REG_48__gs_state5_r0_q_1_MASK 0x00010000L -#define VGT_DBG_REG_48__gs_state5_r0_q_2_MASK 0x00020000L -#define VGT_DBG_REG_48__gs_state6_r0_q_0_MASK 0x00040000L -#define VGT_DBG_REG_48__gs_state6_r0_q_1_MASK 0x00080000L -#define VGT_DBG_REG_48__gs_state6_r0_q_2_MASK 0x00100000L -#define VGT_DBG_REG_48__gs_state7_r0_q_0_MASK 0x00200000L -#define VGT_DBG_REG_48__gs_state7_r0_q_1_MASK 0x00400000L -#define VGT_DBG_REG_48__gs_state7_r0_q_2_MASK 0x00800000L -#define VGT_DBG_REG_48__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_49 -#define VGT_DBG_REG_49__gs_state8_r0_q_0_MASK 0x00000001L -#define VGT_DBG_REG_49__gs_state8_r0_q_1_MASK 0x00000002L -#define VGT_DBG_REG_49__gs_state8_r0_q_2_MASK 0x00000004L -#define VGT_DBG_REG_49__gs_state9_r0_q_0_MASK 0x00000008L -#define VGT_DBG_REG_49__gs_state9_r0_q_1_MASK 0x00000010L -#define VGT_DBG_REG_49__gs_state9_r0_q_2_MASK 0x00000020L -#define VGT_DBG_REG_49__hold_eswave_eop_MASK 0x00000040L -#define VGT_DBG_REG_49__Reserved1_MASK 0x00000080L -#define VGT_DBG_REG_49__gs_state10_r0_q_0_MASK 0x00000100L -#define VGT_DBG_REG_49__gs_state10_r0_q_1_MASK 0x00000200L -#define VGT_DBG_REG_49__gs_state10_r0_q_2_MASK 0x00000400L -#define VGT_DBG_REG_49__gs_state11_r0_q_0_MASK 0x00000800L -#define VGT_DBG_REG_49__gs_state11_r0_q_1_MASK 0x00001000L -#define VGT_DBG_REG_49__gs_state11_r0_q_2_MASK 0x00002000L -#define VGT_DBG_REG_49__gs_state12_r0_q_0_MASK 0x00004000L -#define VGT_DBG_REG_49__gs_state12_r0_q_1_MASK 0x00008000L -#define VGT_DBG_REG_49__gs_state12_r0_q_2_MASK 0x00010000L -#define VGT_DBG_REG_49__gs_state13_r0_q_0_MASK 0x00020000L -#define VGT_DBG_REG_49__gs_state13_r0_q_1_MASK 0x00040000L -#define VGT_DBG_REG_49__gs_state13_r0_q_2_MASK 0x00080000L -#define VGT_DBG_REG_49__gs_state14_r0_q_0_MASK 0x00100000L -#define VGT_DBG_REG_49__gs_state14_r0_q_1_MASK 0x00200000L -#define VGT_DBG_REG_49__gs_state14_r0_q_2_MASK 0x00400000L -#define VGT_DBG_REG_49__gs_state15_r0_q_0_MASK 0x00800000L -#define VGT_DBG_REG_49__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_50 -#define VGT_DBG_REG_50__gs_state15_r0_q_1_MASK 0x00000001L -#define VGT_DBG_REG_50__gs_state15_r0_q_2_MASK 0x00000002L -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_0_MASK 0x00000004L -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_1_MASK 0x00000008L -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_2_MASK 0x00000010L -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_3_MASK 0x00000020L -#define VGT_DBG_REG_50__gsfetch_done_fifo_cnt_q_not_0_MASK 0x00000040L -#define VGT_DBG_REG_50__gsfetch_done_cnt_q_not_0_MASK 0x00000080L -#define VGT_DBG_REG_50__es_tbl_full_MASK 0x00000100L -#define VGT_DBG_REG_50__Reserved6_MASK 0x00000200L -#define VGT_DBG_REG_50__Reserved5_MASK 0x00000400L -#define VGT_DBG_REG_50__active_cm_sm_r0_q_0_MASK 0x00000800L -#define VGT_DBG_REG_50__active_cm_sm_r0_q_1_MASK 0x00001000L -#define VGT_DBG_REG_50__active_cm_sm_r0_q_2_MASK 0x00002000L -#define VGT_DBG_REG_50__active_cm_sm_r0_q_3_MASK 0x00004000L -#define VGT_DBG_REG_50__active_cm_sm_r0_q_4_MASK 0x00008000L -#define VGT_DBG_REG_50__Reserved4_MASK 0x00010000L -#define VGT_DBG_REG_50__Reserved3_MASK 0x00020000L -#define VGT_DBG_REG_50__Reserved2_MASK 0x00040000L -#define VGT_DBG_REG_50__Reserved1_MASK 0x00080000L -#define VGT_DBG_REG_50__gsfetch_done_fifo_full_MASK 0x00100000L -#define VGT_DBG_REG_50__gs_rb_space_avail_r0_MASK 0x00200000L -#define VGT_DBG_REG_50__smx_es_done_cnt_r0_q_not_0_MASK 0x00400000L -#define VGT_DBG_REG_50__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_51 -#define VGT_DBG_REG_51__Reserved15_MASK 0x00000001L -#define VGT_DBG_REG_51__vs_done_cnt_q_not_0_MASK 0x00000002L -#define VGT_DBG_REG_51__es_flush_cnt_busy_q_MASK 0x00000004L -#define VGT_DBG_REG_51__gs_tbl_full_r0_MASK 0x00000008L -#define VGT_DBG_REG_51__Reserved14_MASK 0x00000010L -#define VGT_DBG_REG_51__Reserved13_MASK 0x00000020L -#define VGT_DBG_REG_51__Reserved12_MASK 0x00000040L -#define VGT_DBG_REG_51__Reserved11_MASK 0x00000080L -#define VGT_DBG_REG_51__Reserved10_MASK 0x00000100L -#define VGT_DBG_REG_51__Reserved9_MASK 0x00000200L -#define VGT_DBG_REG_51__Reserved8_MASK 0x00000400L -#define VGT_DBG_REG_51__Reserved7_MASK 0x00000800L -#define VGT_DBG_REG_51__Reserved6_MASK 0x00001000L -#define VGT_DBG_REG_51__se1spi_gsthread_fifo_busy_MASK 0x00002000L -#define VGT_DBG_REG_51__Reserved5_MASK 0x00004000L -#define VGT_DBG_REG_51__Reserved4_MASK 0x00008000L -#define VGT_DBG_REG_51__Reserved3_MASK 0x00010000L -#define VGT_DBG_REG_51__VGT_SE1SPI_gsthread_rtr_q_MASK 0x00020000L -#define VGT_DBG_REG_51__smx1_es_done_cnt_r0_q_not_0_MASK 0x00040000L -#define VGT_DBG_REG_51__se1spi_esthread_fifo_busy_MASK 0x00080000L -#define VGT_DBG_REG_51__Reserved2_MASK 0x00100000L -#define VGT_DBG_REG_51__gsfetch_done_se1_cnt_q_not_0_MASK 0x00200000L -#define VGT_DBG_REG_51__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_51__VGT_SE1SPI_esthread_rtr_q_MASK 0x00800000L -#define VGT_DBG_REG_51__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_52 -#define VGT_DBG_REG_52__cm_busy_q_MASK 0x00000001L -#define VGT_DBG_REG_52__counters_busy_q_MASK 0x00000002L -#define VGT_DBG_REG_52__output_fifo_empty_MASK 0x00000004L -#define VGT_DBG_REG_52__output_fifo_full_MASK 0x00000008L -#define VGT_DBG_REG_52__counters_full_MASK 0x00000010L -#define VGT_DBG_REG_52__active_sm_q_0_MASK 0x00000020L -#define VGT_DBG_REG_52__active_sm_q_1_MASK 0x00000040L -#define VGT_DBG_REG_52__active_sm_q_2_MASK 0x00000080L -#define VGT_DBG_REG_52__active_sm_q_3_MASK 0x00000100L -#define VGT_DBG_REG_52__active_sm_q_4_MASK 0x00000200L -#define VGT_DBG_REG_52__entry_rdptr_q_0_MASK 0x00000400L -#define VGT_DBG_REG_52__entry_rdptr_q_1_MASK 0x00000800L -#define VGT_DBG_REG_52__entry_rdptr_q_2_MASK 0x00001000L -#define VGT_DBG_REG_52__entry_rdptr_q_3_MASK 0x00002000L -#define VGT_DBG_REG_52__entry_rdptr_q_4_MASK 0x00004000L -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_0_MASK 0x00008000L -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_1_MASK 0x00010000L -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_2_MASK 0x00020000L -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_3_MASK 0x00040000L -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_4_MASK 0x00080000L -#define VGT_DBG_REG_52__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_52__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_52__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_52__Reserved0_MASK 0x80000000L - -// VGT_DBG_REG_53 -#define VGT_DBG_REG_53__Reserved5_MASK 0x00000001L -#define VGT_DBG_REG_53__Reserved4_MASK 0x00000002L -#define VGT_DBG_REG_53__st_cut_mode_q_0_MASK 0x00000004L -#define VGT_DBG_REG_53__st_cut_mode_q_1_MASK 0x00000008L -#define VGT_DBG_REG_53__gs_done_array_q_not_0_MASK 0x00000010L -#define VGT_DBG_REG_53__Reserved3_MASK 0x00000020L -#define VGT_DBG_REG_53__Reserved2_MASK 0x00000040L -#define VGT_DBG_REG_53__Reserved1_MASK 0x00000080L -#define VGT_DBG_REG_53__gog_busy_MASK 0x00000100L -#define VGT_DBG_REG_53__gog_state_q_1_MASK 0x00000200L -#define VGT_DBG_REG_53__gog_state_q_2_MASK 0x00000400L -#define VGT_DBG_REG_53__gog_state_q_3_MASK 0x00000800L -#define VGT_DBG_REG_53__r0_rtr_MASK 0x00001000L -#define VGT_DBG_REG_53__r1_rtr_MASK 0x00002000L -#define VGT_DBG_REG_53__r1_upstream_rtr_MASK 0x00004000L -#define VGT_DBG_REG_53__r2_vs_tbl_rtr_MASK 0x00008000L -#define VGT_DBG_REG_53__r2_prim_rtr_MASK 0x00010000L -#define VGT_DBG_REG_53__r2_indx_rtr_MASK 0x00020000L -#define VGT_DBG_REG_53__r2_rtr_MASK 0x00040000L -#define VGT_DBG_REG_53__gog_tm_vs_event_rtr_MASK 0x00080000L -#define VGT_DBG_REG_53__r3_force_vs_tbl_we_rtr_MASK 0x00100000L -#define VGT_DBG_REG_53__indx_valid_r2_q_MASK 0x00200000L -#define VGT_DBG_REG_53__prim_valid_r2_q_MASK 0x00400000L -#define VGT_DBG_REG_53__valid_r2_q_MASK 0x00800000L -#define VGT_DBG_REG_53__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_54 -#define VGT_DBG_REG_54__prim_valid_r1_q_MASK 0x00000001L -#define VGT_DBG_REG_54__indx_valid_r1_q_MASK 0x00000002L -#define VGT_DBG_REG_54__valid_r1_q_MASK 0x00000004L -#define VGT_DBG_REG_54__indx_valid_r0_q_MASK 0x00000008L -#define VGT_DBG_REG_54__prim_valid_r0_q_MASK 0x00000010L -#define VGT_DBG_REG_54__valid_r0_q_MASK 0x00000020L -#define VGT_DBG_REG_54__send_event_q_MASK 0x00000040L -#define VGT_DBG_REG_54__SPARE24_MASK 0x00000080L -#define VGT_DBG_REG_54__vert_seen_since_sopg_r2_q_MASK 0x00000100L -#define VGT_DBG_REG_54__gog_out_prim_state_sel_0_MASK 0x00000200L -#define VGT_DBG_REG_54__gog_out_prim_state_sel_1_MASK 0x00000400L -#define VGT_DBG_REG_54__gog_out_prim_state_sel_2_MASK 0x00000800L -#define VGT_DBG_REG_54__multiple_streams_en_r1_q_MASK 0x00001000L -#define VGT_DBG_REG_54__vs_vert_count_r2_q_not_0_MASK 0x00002000L -#define VGT_DBG_REG_54__num_gs_r2_q_not_0_MASK 0x00004000L -#define VGT_DBG_REG_54__new_vs_thread_r2_MASK 0x00008000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_0_MASK 0x00010000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_1_MASK 0x00020000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_2_MASK 0x00040000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_3_MASK 0x00080000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_4_MASK 0x00100000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_5_MASK 0x00200000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx1_5_0_0_MASK 0x00400000L -#define VGT_DBG_REG_54__gog_out_prim_rel_indx1_5_0_1_MASK 0x00800000L -#define VGT_DBG_REG_54__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_55 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_2_MASK 0x00000001L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_3_MASK 0x00000002L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_4_MASK 0x00000004L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_5_MASK 0x00000008L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_0_MASK 0x00000010L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_1_MASK 0x00000020L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_2_MASK 0x00000040L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_3_MASK 0x00000080L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_4_MASK 0x00000100L -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_5_MASK 0x00000200L -#define VGT_DBG_REG_55__gog_out_indx_13_0_0_MASK 0x00000400L -#define VGT_DBG_REG_55__gog_out_indx_13_0_1_MASK 0x00000800L -#define VGT_DBG_REG_55__gog_out_indx_13_0_2_MASK 0x00001000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_3_MASK 0x00002000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_4_MASK 0x00004000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_5_MASK 0x00008000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_6_MASK 0x00010000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_7_MASK 0x00020000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_8_MASK 0x00040000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_9_MASK 0x00080000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_10_MASK 0x00100000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_11_MASK 0x00200000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_12_MASK 0x00400000L -#define VGT_DBG_REG_55__gog_out_indx_13_0_13_MASK 0x00800000L -#define VGT_DBG_REG_55__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_56 -#define VGT_DBG_REG_56__grp_vr_valid_MASK 0x00000001L -#define VGT_DBG_REG_56__pipe0_dr_MASK 0x00000002L -#define VGT_DBG_REG_56__pipe1_dr_MASK 0x00000004L -#define VGT_DBG_REG_56__vr_grp_read_MASK 0x00000008L -#define VGT_DBG_REG_56__pipe0_rtr_MASK 0x00000010L -#define VGT_DBG_REG_56__pipe1_rtr_MASK 0x00000020L -#define VGT_DBG_REG_56__out_vr_indx_read_MASK 0x00000040L -#define VGT_DBG_REG_56__out_vr_prim_read_MASK 0x00000080L -#define VGT_DBG_REG_56__indices_to_send_q_0_MASK 0x00000100L -#define VGT_DBG_REG_56__indices_to_send_q_1_MASK 0x00000200L -#define VGT_DBG_REG_56__indices_to_send_q_2_MASK 0x00000400L -#define VGT_DBG_REG_56__valid_indices_MASK 0x00000800L -#define VGT_DBG_REG_56__last_indx_of_prim_MASK 0x00001000L -#define VGT_DBG_REG_56__indx0_new_d_MASK 0x00002000L -#define VGT_DBG_REG_56__indx1_new_d_MASK 0x00004000L -#define VGT_DBG_REG_56__indx2_new_d_MASK 0x00008000L -#define VGT_DBG_REG_56__indx2_hit_d_MASK 0x00010000L -#define VGT_DBG_REG_56__indx1_hit_d_MASK 0x00020000L -#define VGT_DBG_REG_56__indx0_hit_d_MASK 0x00040000L -#define VGT_DBG_REG_56__st_vertex_reuse_off_r0_q_MASK 0x00080000L -#define VGT_DBG_REG_56__last_group_of_instance_r0_q_MASK 0x00100000L -#define VGT_DBG_REG_56__null_primitive_r0_q_MASK 0x00200000L -#define VGT_DBG_REG_56__eop_r0_q_MASK 0x00400000L -#define VGT_DBG_REG_56__eject_vtx_vect_r1_d_MASK 0x00800000L -#define VGT_DBG_REG_56__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_57 -#define VGT_DBG_REG_57__sub_prim_type_r0_q_0_MASK 0x00000001L -#define VGT_DBG_REG_57__sub_prim_type_r0_q_1_MASK 0x00000002L -#define VGT_DBG_REG_57__sub_prim_type_r0_q_2_MASK 0x00000004L -#define VGT_DBG_REG_57__gs_scenario_a_r0_q_MASK 0x00000008L -#define VGT_DBG_REG_57__gs_scenario_b_r0_q_MASK 0x00000010L -#define VGT_DBG_REG_57__components_valid_r0_q_29_MASK 0x00000020L -#define VGT_DBG_REG_57__components_valid_r0_q_30_MASK 0x00000040L -#define VGT_DBG_REG_57__components_valid_r0_q_31_MASK 0x00000080L -#define VGT_DBG_REG_57__separate_out_busy_q_MASK 0x00000100L -#define VGT_DBG_REG_57__separate_out_indx_busy_q_MASK 0x00000200L -#define VGT_DBG_REG_57__prim_buffer_empty_MASK 0x00000400L -#define VGT_DBG_REG_57__prim_buffer_full_MASK 0x00000800L -#define VGT_DBG_REG_57__pa_clips_fifo_busy_q_MASK 0x00001000L -#define VGT_DBG_REG_57__pa_clipp_fifo_busy_q_MASK 0x00002000L -#define VGT_DBG_REG_57__VGT_PA_clips_rtr_q_MASK 0x00004000L -#define VGT_DBG_REG_57__VGT_PA_clipp_rtr_q_MASK 0x00008000L -#define VGT_DBG_REG_57__spi_vsthread_fifo_busy_q_MASK 0x00010000L -#define VGT_DBG_REG_57__spi_vsvert_fifo_busy_q_MASK 0x00020000L -#define VGT_DBG_REG_57__pa_clipv_fifo_busy_q_MASK 0x00040000L -#define VGT_DBG_REG_57__hold_prim_MASK 0x00080000L -#define VGT_DBG_REG_57__VGT_SPI_vsthread_rtr_q_MASK 0x00100000L -#define VGT_DBG_REG_57__VGT_SPI_vsvert_rtr_q_MASK 0x00200000L -#define VGT_DBG_REG_57__VGT_PA_clipv_rtr_q_MASK 0x00400000L -#define VGT_DBG_REG_57__new_packet_q_MASK 0x00800000L -#define VGT_DBG_REG_57__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_58 -#define VGT_DBG_REG_58__buffered_prim_event_MASK 0x00000001L -#define VGT_DBG_REG_58__buffered_prim_null_primitive_MASK 0x00000002L -#define VGT_DBG_REG_58__buffered_prim_eop_MASK 0x00000004L -#define VGT_DBG_REG_58__buffered_prim_eject_vtx_vect_MASK 0x00000008L -#define VGT_DBG_REG_58__buffered_prim_type_event_0_MASK 0x00000010L -#define VGT_DBG_REG_58__buffered_prim_type_event_1_MASK 0x00000020L -#define VGT_DBG_REG_58__buffered_prim_type_event_2_MASK 0x00000040L -#define VGT_DBG_REG_58__buffered_prim_type_event_3_MASK 0x00000080L -#define VGT_DBG_REG_58__buffered_prim_type_event_4_MASK 0x00000100L -#define VGT_DBG_REG_58__buffered_prim_type_event_5_MASK 0x00000200L -#define VGT_DBG_REG_58__VGT_SE1SPI_vswave_rtr_q_MASK 0x00000400L -#define VGT_DBG_REG_58__VGT_SE1SPI_vsvert_rtr_q_MASK 0x00000800L -#define VGT_DBG_REG_58__num_new_unique_rel_indx_0_MASK 0x00001000L -#define VGT_DBG_REG_58__num_new_unique_rel_indx_1_MASK 0x00002000L -#define VGT_DBG_REG_58__null_terminate_vtx_vector_MASK 0x00004000L -#define VGT_DBG_REG_58__filter_event_MASK 0x00008000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_0_MASK 0x00010000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_1_MASK 0x00020000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_2_MASK 0x00040000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_3_MASK 0x00080000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_4_MASK 0x00100000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_5_MASK 0x00200000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_6_MASK 0x00400000L -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_7_MASK 0x00800000L -#define VGT_DBG_REG_58__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_59 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_8_MASK 0x00000001L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_9_MASK 0x00000002L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_10_MASK 0x00000004L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_11_MASK 0x00000008L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_12_MASK 0x00000010L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_13_MASK 0x00000020L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_14_MASK 0x00000040L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_15_MASK 0x00000080L -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x00000100L -#define VGT_DBG_REG_59__Reserved1_MASK 0x00000200L -#define VGT_DBG_REG_59__alloc_counter_q_0_MASK 0x00000400L -#define VGT_DBG_REG_59__alloc_counter_q_1_MASK 0x00000800L -#define VGT_DBG_REG_59__alloc_counter_q_2_MASK 0x00001000L -#define VGT_DBG_REG_59__alloc_counter_q_3_MASK 0x00002000L -#define VGT_DBG_REG_59__curr_dealloc_distance_q_0_MASK 0x00004000L -#define VGT_DBG_REG_59__curr_dealloc_distance_q_1_MASK 0x00008000L -#define VGT_DBG_REG_59__curr_dealloc_distance_q_2_MASK 0x00010000L -#define VGT_DBG_REG_59__curr_dealloc_distance_q_3_MASK 0x00020000L -#define VGT_DBG_REG_59__curr_dealloc_distance_q_4_MASK 0x00040000L -#define VGT_DBG_REG_59__curr_dealloc_distance_q_5_MASK 0x00080000L -#define VGT_DBG_REG_59__curr_dealloc_distance_q_6_MASK 0x00100000L -#define VGT_DBG_REG_59__new_allocate_q_MASK 0x00200000L -#define VGT_DBG_REG_59__curr_slot_in_vtx_vect_q_not_0_MASK 0x00400000L -#define VGT_DBG_REG_59__int_vtx_counter_q_not_0_MASK 0x00800000L -#define VGT_DBG_REG_59__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_60 -#define VGT_DBG_REG_60__out_indx_fifo_empty_MASK 0x00000001L -#define VGT_DBG_REG_60__indx_side_fifo_empty_MASK 0x00000002L -#define VGT_DBG_REG_60__pipe0_dr_MASK 0x00000004L -#define VGT_DBG_REG_60__pipe1_dr_MASK 0x00000008L -#define VGT_DBG_REG_60__pipe2_dr_MASK 0x00000010L -#define VGT_DBG_REG_60__vsthread_buff_empty_MASK 0x00000020L -#define VGT_DBG_REG_60__out_indx_fifo_full_MASK 0x00000040L -#define VGT_DBG_REG_60__indx_side_fifo_full_MASK 0x00000080L -#define VGT_DBG_REG_60__pipe0_rtr_MASK 0x00000100L -#define VGT_DBG_REG_60__pipe1_rtr_MASK 0x00000200L -#define VGT_DBG_REG_60__pipe2_rtr_MASK 0x00000400L -#define VGT_DBG_REG_60__vsthread_buff_full_MASK 0x00000800L -#define VGT_DBG_REG_60__interfaces_rtr_MASK 0x00001000L -#define VGT_DBG_REG_60__indx_count_q_not_0_MASK 0x00002000L -#define VGT_DBG_REG_60__wait_for_external_eopg_q_MASK 0x00004000L -#define VGT_DBG_REG_60__full_state_p1_q_MASK 0x00008000L -#define VGT_DBG_REG_60__indx_side_indx_valid_MASK 0x00010000L -#define VGT_DBG_REG_60__stateid_p0_q_0_MASK 0x00020000L -#define VGT_DBG_REG_60__stateid_p0_q_1_MASK 0x00040000L -#define VGT_DBG_REG_60__stateid_p0_q_2_MASK 0x00080000L -#define VGT_DBG_REG_60__is_event_p0_q_MASK 0x00100000L -#define VGT_DBG_REG_60__lshs_dealloc_p1_MASK 0x00200000L -#define VGT_DBG_REG_60__stream_id_r2_q_MASK 0x00400000L -#define VGT_DBG_REG_60__vtx_vect_counter_q_not_0_MASK 0x00800000L -#define VGT_DBG_REG_60__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_61 -#define VGT_DBG_REG_61__cm_state16_0_MASK 0x00000001L -#define VGT_DBG_REG_61__cm_state16_1_MASK 0x00000002L -#define VGT_DBG_REG_61__cm_state17_0_MASK 0x00000004L -#define VGT_DBG_REG_61__cm_state17_1_MASK 0x00000008L -#define VGT_DBG_REG_61__cm_state18_0_MASK 0x00000010L -#define VGT_DBG_REG_61__cm_state18_1_MASK 0x00000020L -#define VGT_DBG_REG_61__cm_state19_0_MASK 0x00000040L -#define VGT_DBG_REG_61__cm_state19_1_MASK 0x00000080L -#define VGT_DBG_REG_61__cm_state20_0_MASK 0x00000100L -#define VGT_DBG_REG_61__cm_state20_1_MASK 0x00000200L -#define VGT_DBG_REG_61__cm_state21_0_MASK 0x00000400L -#define VGT_DBG_REG_61__cm_state21_1_MASK 0x00000800L -#define VGT_DBG_REG_61__cm_state22_0_MASK 0x00001000L -#define VGT_DBG_REG_61__cm_state22_1_MASK 0x00002000L -#define VGT_DBG_REG_61__cm_state23_0_MASK 0x00004000L -#define VGT_DBG_REG_61__cm_state23_1_MASK 0x00008000L -#define VGT_DBG_REG_61__buff_full_p1_MASK 0x00010000L -#define VGT_DBG_REG_61__strmout_valid_p1_MASK 0x00020000L -#define VGT_DBG_REG_61__eotg_r2_q_MASK 0x00040000L -#define VGT_DBG_REG_61__null_r2_q_MASK 0x00080000L -#define VGT_DBG_REG_61__p0_dr_MASK 0x00100000L -#define VGT_DBG_REG_61__p0_rtr_MASK 0x00200000L -#define VGT_DBG_REG_61__eopg_p0_q_MASK 0x00400000L -#define VGT_DBG_REG_61__p0_nobp_MASK 0x00800000L -#define VGT_DBG_REG_61__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_62 -#define VGT_DBG_REG_62__cm_state24_0_MASK 0x00000001L -#define VGT_DBG_REG_62__cm_state24_1_MASK 0x00000002L -#define VGT_DBG_REG_62__cm_state25_0_MASK 0x00000004L -#define VGT_DBG_REG_62__cm_state25_1_MASK 0x00000008L -#define VGT_DBG_REG_62__cm_state26_0_MASK 0x00000010L -#define VGT_DBG_REG_62__cm_state26_1_MASK 0x00000020L -#define VGT_DBG_REG_62__cm_state27_0_MASK 0x00000040L -#define VGT_DBG_REG_62__cm_state27_1_MASK 0x00000080L -#define VGT_DBG_REG_62__cm_state28_0_MASK 0x00000100L -#define VGT_DBG_REG_62__cm_state28_1_MASK 0x00000200L -#define VGT_DBG_REG_62__cm_state29_0_MASK 0x00000400L -#define VGT_DBG_REG_62__cm_state29_1_MASK 0x00000800L -#define VGT_DBG_REG_62__cm_state30_0_MASK 0x00001000L -#define VGT_DBG_REG_62__cm_state30_1_MASK 0x00002000L -#define VGT_DBG_REG_62__cm_state31_0_MASK 0x00004000L -#define VGT_DBG_REG_62__cm_state31_1_MASK 0x00008000L -#define VGT_DBG_REG_62__frmt_busy_MASK 0x00010000L -#define VGT_DBG_REG_62__rcm_frmt_vert_rtr_MASK 0x00020000L -#define VGT_DBG_REG_62__rcm_frmt_prim_rtr_MASK 0x00040000L -#define VGT_DBG_REG_62__prim_r3_rtr_MASK 0x00080000L -#define VGT_DBG_REG_62__prim_r2_rtr_MASK 0x00100000L -#define VGT_DBG_REG_62__vert_r3_rtr_MASK 0x00200000L -#define VGT_DBG_REG_62__vert_r2_rtr_MASK 0x00400000L -#define VGT_DBG_REG_62__vert_r1_rtr_MASK 0x00800000L -#define VGT_DBG_REG_62__Reserved0_MASK 0xff000000L - -// VGT_DBG_REG_63 -#define VGT_DBG_REG_63__vert_r0_rtr_MASK 0x00000001L -#define VGT_DBG_REG_63__prim_fifo_empty_MASK 0x00000002L -#define VGT_DBG_REG_63__prim_fifo_full_MASK 0x00000004L -#define VGT_DBG_REG_63__vert_dr_r2_q_MASK 0x00000008L -#define VGT_DBG_REG_63__prim_dr_r2_q_MASK 0x00000010L -#define VGT_DBG_REG_63__vert_dr_r1_q_MASK 0x00000020L -#define VGT_DBG_REG_63__vert_dr_r0_q_MASK 0x00000040L -#define VGT_DBG_REG_63__new_verts_r2_q_0_MASK 0x00000080L -#define VGT_DBG_REG_63__new_verts_r2_q_1_MASK 0x00000100L -#define VGT_DBG_REG_63__verts_sent_r2_q_0_MASK 0x00000200L -#define VGT_DBG_REG_63__verts_sent_r2_q_1_MASK 0x00000400L -#define VGT_DBG_REG_63__verts_sent_r2_q_2_MASK 0x00000800L -#define VGT_DBG_REG_63__verts_sent_r2_q_3_MASK 0x00001000L -#define VGT_DBG_REG_63__prim_state_sel_r2_q_0_MASK 0x00002000L -#define VGT_DBG_REG_63__prim_state_sel_r2_q_1_MASK 0x00004000L -#define VGT_DBG_REG_63__prim_state_sel_r2_q_2_MASK 0x00008000L -#define VGT_DBG_REG_63__Reserved7_MASK 0x00010000L -#define VGT_DBG_REG_63__Reserved6_MASK 0x00020000L -#define VGT_DBG_REG_63__Reserved5_MASK 0x00040000L -#define VGT_DBG_REG_63__Reserved4_MASK 0x00080000L -#define VGT_DBG_REG_63__Reserved3_MASK 0x00100000L -#define VGT_DBG_REG_63__Reserved2_MASK 0x00200000L -#define VGT_DBG_REG_63__Reserved1_MASK 0x00400000L -#define VGT_DBG_REG_63__Reserved0_MASK 0x80000000L - -// spi_vs_wave_ctl0 -#define spi_vs_wave_ctl0__f_double_data_MASK 0x00000001L -#define spi_vs_wave_ctl0__f_vs_vert_gs_on_MASK 0x00000002L -#define spi_vs_wave_ctl0__f_gpr_ld_line_sel_MASK 0x0000003cL -#define spi_vs_wave_ctl0__wave_buffer_fifo_empty_MASK 0x00000040L -#define spi_vs_wave_ctl0__vs_wave_first_subgrp_MASK 0x00000080L -#define spi_vs_wave_ctl0__gsc_vsc_group_cu_id_MASK 0x00000f00L -#define spi_vs_wave_ctl0__vs_gdbg_en_q_MASK 0x00001000L -#define spi_vs_wave_ctl0__tr_fits_MASK 0x00002000L -#define spi_vs_wave_ctl0__vs_wave_cnt_lt_lim_MASK 0x00004000L -#define spi_vs_wave_ctl0__pipe_id_MASK 0x00008000L -#define spi_vs_wave_ctl0__late_alloc_lt_lim_MASK 0x00010000L -#define spi_vs_wave_ctl0__outstanding_waves_MASK 0x001e0000L -#define spi_vs_wave_ctl0__outstanding_events_MASK 0x00e00000L -#define spi_vs_wave_ctl0__Reserved0_MASK 0xff000000L - -// spi_vs_wave_ctl1 -#define spi_vs_wave_ctl1__crawler_is_event_MASK 0x00000001L -#define spi_vs_wave_ctl1__stall_events_MASK 0x00000002L -#define spi_vs_wave_ctl1__wave_done_crawler_id_MASK 0x00000ffcL -#define spi_vs_wave_ctl1__wave_done_MASK 0x00001000L -#define spi_vs_wave_ctl1__crawler_full_MASK 0x00002000L -#define spi_vs_wave_ctl1__crawler_empty_MASK 0x00004000L -#define spi_vs_wave_ctl1__crawler_rd_MASK 0x00ff8000L -#define spi_vs_wave_ctl1__Reserved0_MASK 0xff000000L - -// spi_vs_wave_ctl2 -#define spi_vs_wave_ctl2__res_alloc_state_MASK 0x00000003L -#define spi_vs_wave_ctl2__vsc_ra_rts_MASK 0x00000004L -#define spi_vs_wave_ctl2__clocks_on_MASK 0x00000008L -#define spi_vs_wave_ctl2__UNUSED_vsc_ra_alloc_req1_MASK 0x00000010L -#define spi_vs_wave_ctl2__vsc_ra_alloc_req0_MASK 0x00000020L -#define spi_vs_wave_ctl2__UNUSED_vsc_pc_posb1_alloc_req_MASK 0x00000040L -#define spi_vs_wave_ctl2__vsc_pc_posb0_alloc_req_MASK 0x00000080L -#define spi_vs_wave_ctl2__vsc_ra_cu_id_MASK 0x00000f00L -#define spi_vs_wave_ctl2__hsc_group_cu_id_MASK 0x0000f000L -#define spi_vs_wave_ctl2__hsc_group_fifo_empty_MASK 0x00010000L -#define spi_vs_wave_ctl2__vs_wave_first_wave_MASK 0x00020000L -#define spi_vs_wave_ctl2__vs_wave_stateid_MASK 0x001c0000L -#define spi_vs_wave_ctl2__vs_wave_is_event_MASK 0x00200000L -#define spi_vs_wave_ctl2__vgt_vswave_fifo_empty_MASK 0x00400000L -#define spi_vs_wave_ctl2__gsc_vsc_group_fifo_empty_MASK 0x00800000L -#define spi_vs_wave_ctl2__Reserved0_MASK 0xff000000L - -// spi_gs_wave_ctl0 -#define spi_gs_wave_ctl0__f_double_data_MASK 0x00000001L -#define spi_gs_wave_ctl0__f_gpr_ld_buf_sel_MASK 0x00000006L -#define spi_gs_wave_ctl0__wave_buffer_fifo_empty_MASK 0x00000008L -#define spi_gs_wave_ctl0__gsc_vsc_group_fifo_empty_MASK 0x00000010L -#define spi_gs_wave_ctl0__gs_gdbg_en_q_MASK 0x00000020L -#define spi_gs_wave_ctl0__tr_fits_MASK 0x00000040L -#define spi_gs_wave_ctl0__gs_wave_cnt_lt_lim_MASK 0x00000080L -#define spi_gs_wave_ctl0__pipe_id_MASK 0x00000300L -#define spi_gs_wave_ctl0__outstanding_waves_MASK 0x00003c00L -#define spi_gs_wave_ctl0__outstanding_events_MASK 0x0001c000L -#define spi_gs_wave_ctl0__Reserved0_MASK 0xfffe0000L - -// spi_gs_wave_ctl1 -#define spi_gs_wave_ctl1__crawler_rd_MASK 0x0000007fL -#define spi_gs_wave_ctl1__crawler_is_event_MASK 0x00000080L -#define spi_gs_wave_ctl1__stall_events_MASK 0x00000100L -#define spi_gs_wave_ctl1__wave_done_crawler_id_MASK 0x0007fe00L -#define spi_gs_wave_ctl1__wave_done_MASK 0x00080000L -#define spi_gs_wave_ctl1__crawler_full_MASK 0x00100000L -#define spi_gs_wave_ctl1__crawler_empty_MASK 0x00200000L -#define spi_gs_wave_ctl1__Reserved0_MASK 0xffc00000L - -// spi_gs_wave_ctl2 -#define spi_gs_wave_ctl2__res_alloc_state_MASK 0x00000001L -#define spi_gs_wave_ctl2__clocks_on_MASK 0x00000002L -#define spi_gs_wave_ctl2__gsc_ra_rts_MASK 0x00000004L -#define spi_gs_wave_ctl2__UNUSED_gsc_ra_alloc_req1_MASK 0x00000008L -#define spi_gs_wave_ctl2__gsc_ra_alloc_req0_MASK 0x00000010L -#define spi_gs_wave_ctl2__gs_wave_stateid_MASK 0x000000e0L -#define spi_gs_wave_ctl2__gs_wave_is_event_MASK 0x00000100L -#define spi_gs_wave_ctl2__vgt_gswave_fifo_empty_MASK 0x00000200L -#define spi_gs_wave_ctl2__gs_group_fifo_full_MASK 0x00000400L -#define spi_gs_wave_ctl2__gs_wave_first_subgrp_MASK 0x00000800L -#define spi_gs_wave_ctl2__gsc_ra0_cu_id_MASK 0x0000f000L -#define spi_gs_wave_ctl2__esc_gsc_group_cu_id_MASK 0x000f0000L -#define spi_gs_wave_ctl2__gs_onchip_MASK 0x00300000L -#define spi_gs_wave_ctl2__Reserved0_MASK 0xffc00000L - -// spi_es_wave_ctl0 -#define spi_es_wave_ctl0__f_double_data_MASK 0x00000001L -#define spi_es_wave_ctl0__f_gpr_ld_buf_sel_MASK 0x00000006L -#define spi_es_wave_ctl0__wave_buffer_fifo_empty_MASK 0x00000008L -#define spi_es_wave_ctl0__esc_gsc_group_fifo_empty_MASK 0x00000010L -#define spi_es_wave_ctl0__es_gdbg_en_q_MASK 0x00000020L -#define spi_es_wave_ctl0__tr_fits_MASK 0x00000040L -#define spi_es_wave_ctl0__es_wave_cnt_lt_lim_MASK 0x00000080L -#define spi_es_wave_ctl0__pipe_id_MASK 0x00000300L -#define spi_es_wave_ctl0__outstanding_waves_MASK 0x00003c00L -#define spi_es_wave_ctl0__outstanding_events_MASK 0x0001c000L -#define spi_es_wave_ctl0__gs_onchip_MASK 0x00060000L -#define spi_es_wave_ctl0__es_wave_offchip_MASK 0x00080000L -#define spi_es_wave_ctl0__es_wave_first_subgrp_MASK 0x00100000L -#define spi_es_wave_ctl0__esc_ra0_is_ds_MASK 0x00200000L -#define spi_es_wave_ctl0__Reserved0_MASK 0xffc00000L - -// spi_es_wave_ctl1 -#define spi_es_wave_ctl1__crawler_is_event_MASK 0x00000001L -#define spi_es_wave_ctl1__stall_events_MASK 0x00000002L -#define spi_es_wave_ctl1__wave_done_crawler_id_MASK 0x00000ffcL -#define spi_es_wave_ctl1__wave_done_MASK 0x00001000L -#define spi_es_wave_ctl1__crawler_full_MASK 0x00002000L -#define spi_es_wave_ctl1__crawler_empty_MASK 0x00004000L -#define spi_es_wave_ctl1__crawler_rd_MASK 0x00ff8000L -#define spi_es_wave_ctl1__Reserved0_MASK 0xff000000L - -// spi_es_wave_ctl2 -#define spi_es_wave_ctl2__res_alloc_state_MASK 0x00000001L -#define spi_es_wave_ctl2__esc_ra_rts_MASK 0x00000002L -#define spi_es_wave_ctl2__clocks_on_MASK 0x00000004L -#define spi_es_wave_ctl2__esc_ra_alloc_req1_MASK 0x00000008L -#define spi_es_wave_ctl2__esc_ra_alloc_req0_MASK 0x00000010L -#define spi_es_wave_ctl2__esc_ra_cu_id_MASK 0x000001e0L -#define spi_es_wave_ctl2__hsc_group_cu_id_MASK 0x00001e00L -#define spi_es_wave_ctl2__hsc_group_fifo_empty_MASK 0x00002000L -#define spi_es_wave_ctl2__es_wave_first_wave_MASK 0x00004000L -#define spi_es_wave_ctl2__es_wave_stateid_MASK 0x00038000L -#define spi_es_wave_ctl2__es_wave_is_event_MASK 0x00040000L -#define spi_es_wave_ctl2__vgt_eswave_fifo_empty_MASK 0x00080000L -#define spi_es_wave_ctl2__es_group_fifo_full_MASK 0x00100000L -#define spi_es_wave_ctl2__Reserved0_MASK 0xffe00000L - -// spi_hs_wave_ctl0 -#define spi_hs_wave_ctl0__f_gpr_ld_line_sel_MASK 0x00000003L -#define spi_hs_wave_ctl0__wave_buffer_fifo_empty_MASK 0x00000004L -#define spi_hs_wave_ctl0__hsc_group_fifo_empty_MASK 0x00000008L -#define spi_hs_wave_ctl0__hs_gdbg_en_q_MASK 0x00000010L -#define spi_hs_wave_ctl0__tr_fits_MASK 0x00000020L -#define spi_hs_wave_ctl0__hs_wave_cnt_lt_lim_MASK 0x00000040L -#define spi_hs_wave_ctl0__pipe_id_MASK 0x00000180L -#define spi_hs_wave_ctl0__outstanding_waves_MASK 0x00001e00L -#define spi_hs_wave_ctl0__outstanding_events_MASK 0x0000e000L -#define spi_hs_wave_ctl0__es_is_ds_MASK 0x00010000L -#define spi_hs_wave_ctl0__Reserved0_MASK 0xfffe0000L - -// spi_hs_wave_ctl1 -#define spi_hs_wave_ctl1__crawler_rd_MASK 0x0000007fL -#define spi_hs_wave_ctl1__crawler_is_event_MASK 0x00000080L -#define spi_hs_wave_ctl1__stall_events_MASK 0x00000100L -#define spi_hs_wave_ctl1__wave_done_crawler_id_MASK 0x0007fe00L -#define spi_hs_wave_ctl1__wave_done_MASK 0x00080000L -#define spi_hs_wave_ctl1__crawler_full_MASK 0x00100000L -#define spi_hs_wave_ctl1__crawler_empty_MASK 0x00200000L -#define spi_hs_wave_ctl1__Reserved0_MASK 0xffc00000L - -// spi_hs_wave_ctl2 -#define spi_hs_wave_ctl2__res_alloc_state_MASK 0x00000001L -#define spi_hs_wave_ctl2__hsc_ra_rts_MASK 0x00000002L -#define spi_hs_wave_ctl2__clocks_on_MASK 0x00000004L -#define spi_hs_wave_ctl2__UNUSED_hsc_ra_alloc_req1_MASK 0x00000008L -#define spi_hs_wave_ctl2__hsc_ra_alloc_req0_MASK 0x00000010L -#define spi_hs_wave_ctl2__hsc_ra_cu_id_MASK 0x000001e0L -#define spi_hs_wave_ctl2__lsc_hsc_group_cu_id_MASK 0x00001e00L -#define spi_hs_wave_ctl2__lsc_hsc_group_fifo_empty_MASK 0x00002000L -#define spi_hs_wave_ctl2__hs_group_fifo_full_MASK 0x00004000L -#define spi_hs_wave_ctl2__hs_wave_first_wave_MASK 0x00008000L -#define spi_hs_wave_ctl2__hs_wave_stateid_MASK 0x00070000L -#define spi_hs_wave_ctl2__hs_wave_is_event_MASK 0x00080000L -#define spi_hs_wave_ctl2__vgt_hswave_fifo_empty_MASK 0x00100000L -#define spi_hs_wave_ctl2__Reserved0_MASK 0xffe00000L - -// spi_ls_wave_ctl0 -#define spi_ls_wave_ctl0__f_vsr_ld_buf_sel_MASK 0x00000003L -#define spi_ls_wave_ctl0__wave_buffer_fifo_empty_MASK 0x00000004L -#define spi_ls_wave_ctl0__lsc_hsc_group_fifo_empty_MASK 0x00000008L -#define spi_ls_wave_ctl0__ls_gdbg_en_q_MASK 0x00000010L -#define spi_ls_wave_ctl0__tr_fits_MASK 0x00000020L -#define spi_ls_wave_ctl0__ls_wave_cnt_lt_lim_MASK 0x00000040L -#define spi_ls_wave_ctl0__pipe_id_MASK 0x00000180L -#define spi_ls_wave_ctl0__outstanding_waves_MASK 0x00001e00L -#define spi_ls_wave_ctl0__outstanding_events_MASK 0x0000e000L -#define spi_ls_wave_ctl0__Reserved0_MASK 0xffff0000L - -// spi_ls_wave_ctl1 -#define spi_ls_wave_ctl1__crawler_rd_MASK 0x0000007fL -#define spi_ls_wave_ctl1__crawler_is_event_MASK 0x00000080L -#define spi_ls_wave_ctl1__stall_events_MASK 0x00000100L -#define spi_ls_wave_ctl1__wave_done_crawler_id_MASK 0x0007fe00L -#define spi_ls_wave_ctl1__wave_done_MASK 0x00080000L -#define spi_ls_wave_ctl1__crawler_full_MASK 0x00100000L -#define spi_ls_wave_ctl1__crawler_empty_MASK 0x00200000L -#define spi_ls_wave_ctl1__Reserved0_MASK 0xffc00000L - -// spi_ls_wave_ctl2 -#define spi_ls_wave_ctl2__res_alloc_state_MASK 0x00000003L -#define spi_ls_wave_ctl2__lsc_ra_rts_MASK 0x00000004L -#define spi_ls_wave_ctl2__clocks_on_MASK 0x00000008L -#define spi_ls_wave_ctl2__UNUSED_lsc_ra_alloc_req1_MASK 0x00000010L -#define spi_ls_wave_ctl2__lsc_ra_alloc_req0_MASK 0x00000020L -#define spi_ls_wave_ctl2__lsc_olm_alloc_req_MASK 0x00000040L -#define spi_ls_wave_ctl2__Reserved1_MASK 0x00000780L -#define spi_ls_wave_ctl2__ls_group_fifo_full_MASK 0x00000800L -#define spi_ls_wave_ctl2__ls_wave_first_wave_MASK 0x00001000L -#define spi_ls_wave_ctl2__ls_wave_stateid_MASK 0x0000e000L -#define spi_ls_wave_ctl2__ls_wave_is_event_MASK 0x00010000L -#define spi_ls_wave_ctl2__vgt_lswave_fifo_empty_MASK 0x00020000L -#define spi_ls_wave_ctl2__Reserved0_MASK 0xfffc0000L - -// spi_cs_ctl_gfx0 -#define spi_cs_ctl_gfx0__UNUSED_remaining_threads1_MASK 0x0000007fL -#define spi_cs_ctl_gfx0__remaining_threads0_MASK 0x00003f80L -#define spi_cs_ctl_gfx0__UNUSED_csc_ra1_last_wave_MASK 0x00004000L -#define spi_cs_ctl_gfx0__csc_ra0_last_wave_MASK 0x00008000L -#define spi_cs_ctl_gfx0__UNUSED_csc_ra1_first_wave_MASK 0x00010000L -#define spi_cs_ctl_gfx0__csc_ra0_first_wave_MASK 0x00020000L -#define spi_cs_ctl_gfx0__csdata_is_state_MASK 0x00040000L -#define spi_cs_ctl_gfx0__csdata_is_event_MASK 0x00080000L -#define spi_cs_ctl_gfx0__cpg_csdata_fifo_empty_MASK 0x00100000L -#define spi_cs_ctl_gfx0__cpg_csdata_fifo_full_MASK 0x00200000L -#define spi_cs_ctl_gfx0__Reserved0_MASK 0xffc00000L - -// spi_cs_ctl_gfx1 -#define spi_cs_ctl_gfx1__crw_event_id_MASK 0x0000003fL -#define spi_cs_ctl_gfx1__crw_event_valid_MASK 0x00000040L -#define spi_cs_ctl_gfx1__stall_events_MASK 0x00000080L -#define spi_cs_ctl_gfx1__wave_done_crawler_id_MASK 0x0003ff00L -#define spi_cs_ctl_gfx1__wave_done_MASK 0x00040000L -#define spi_cs_ctl_gfx1__crawler_full_MASK 0x00080000L -#define spi_cs_ctl_gfx1__crawler_empty_MASK 0x00100000L -#define spi_cs_ctl_gfx1__event_count_MASK 0x00e00000L -#define spi_cs_ctl_gfx1__Reserved0_MASK 0xff000000L - -// spi_cs_ctl_gfx2 -#define spi_cs_ctl_gfx2__send_to_shader_array_0_MASK 0x00000001L -#define spi_cs_ctl_gfx2__wave_count_MASK 0x0000007eL -#define spi_cs_ctl_gfx2__waves_sent0_d_MASK 0x00001f80L -#define spi_cs_ctl_gfx2__UNUSED_stall1_MASK 0x00002000L -#define spi_cs_ctl_gfx2__stall0_MASK 0x00004000L -#define spi_cs_ctl_gfx2__UNUSED_res_alloc_req1_MASK 0x00008000L -#define spi_cs_ctl_gfx2__res_alloc_req0_MASK 0x00010000L -#define spi_cs_ctl_gfx2__UNUSED_current_state1_q_MASK 0x000e0000L -#define spi_cs_ctl_gfx2__current_state0_q_MASK 0x00700000L -#define spi_cs_ctl_gfx2__Reserved0_MASK 0xff800000L - -// spi_cs_ctl0 -#define spi_cs_ctl0__Reserved3_MASK 0x0000007fL -#define spi_cs_ctl0__remaining_threads0_MASK 0x00003f80L -#define spi_cs_ctl0__Reserved2_MASK 0x00004000L -#define spi_cs_ctl0__csc_ca_last_wave_MASK 0x00008000L -#define spi_cs_ctl0__Reserved1_MASK 0x00010000L -#define spi_cs_ctl0__csc_ca_first_wave_MASK 0x00020000L -#define spi_cs_ctl0__csdata_is_state_MASK 0x00040000L -#define spi_cs_ctl0__csdata_is_event_MASK 0x00080000L -#define spi_cs_ctl0__cpc_csdata_fifo_empty_MASK 0x00100000L -#define spi_cs_ctl0__cpc_csdata_fifo_full_MASK 0x00200000L -#define spi_cs_ctl0__Reserved0_MASK 0xffc00000L - -// spi_cs_ctl1 -#define spi_cs_ctl1__crw_event_id_MASK 0x0000003fL -#define spi_cs_ctl1__crw_event_valid_MASK 0x00000040L -#define spi_cs_ctl1__stall_events_MASK 0x00000080L -#define spi_cs_ctl1__wave_done_crawler_id_MASK 0x0003ff00L -#define spi_cs_ctl1__wave_done_MASK 0x00040000L -#define spi_cs_ctl1__crawler_full_MASK 0x00080000L -#define spi_cs_ctl1__crawler_empty_MASK 0x00100000L -#define spi_cs_ctl1__event_count_MASK 0x00e00000L -#define spi_cs_ctl1__Reserved0_MASK 0xff000000L - -// spi_cs_ctl2 -#define spi_cs_ctl2__send_to_shader_array_0_MASK 0x00000001L -#define spi_cs_ctl2__wave_count_MASK 0x0000007eL -#define spi_cs_ctl2__waves_sent0_d_MASK 0x00001f80L -#define spi_cs_ctl2__Reserved3_MASK 0x00002000L -#define spi_cs_ctl2__stall0_MASK 0x00004000L -#define spi_cs_ctl2__Reserved2_MASK 0x00008000L -#define spi_cs_ctl2__res_alloc_req0_MASK 0x00010000L -#define spi_cs_ctl2__Reserved1_MASK 0x000e0000L -#define spi_cs_ctl2__current_state0_q_MASK 0x00700000L -#define spi_cs_ctl2__Reserved0_MASK 0xff800000L - -// spi_gfx_tmp_ring_mgr -#define spi_gfx_tmp_ring_mgr__trm_tr_slots_used_MASK 0x000001ffL -#define spi_gfx_tmp_ring_mgr__trm_hs_lock_MASK 0x00000200L -#define spi_gfx_tmp_ring_mgr__Reserved0_MASK 0xfffffc00L - -// spi_cs_wave_gfx_ctl -#define spi_cs_wave_gfx_ctl__tr_slots_used0_MASK 0x000001ffL -#define spi_cs_wave_gfx_ctl__loader_state_q_MASK 0x00000600L -#define spi_cs_wave_gfx_ctl__Reserved2_MASK 0x00003800L -#define spi_cs_wave_gfx_ctl__csdata_is_private_MASK 0x00004000L -#define spi_cs_wave_gfx_ctl__csdata_is_tg_MASK 0x00008000L -#define spi_cs_wave_gfx_ctl__Reserved1_MASK 0x00030000L -#define spi_cs_wave_gfx_ctl__csc_ra0_first_req_dispatch_MASK 0x00040000L -#define spi_cs_wave_gfx_ctl__Reserved0_MASK 0xfff80000L - -// spi_cs_wave_ctl -#define spi_cs_wave_ctl__tr_slots_used_MASK 0x000001ffL -#define spi_cs_wave_ctl__loader_state_q_MASK 0x00000e00L -#define spi_cs_wave_ctl__halt_state_q_MASK 0x00007000L -#define spi_cs_wave_ctl__csdata_is_private_MASK 0x00008000L -#define spi_cs_wave_ctl__csdata_is_tg_MASK 0x00010000L -#define spi_cs_wave_ctl__csc_ca_last_tg_MASK 0x00020000L -#define spi_cs_wave_ctl__csc_ca_first_tg_MASK 0x00040000L -#define spi_cs_wave_ctl__csc_ca_first_req_dispatch_MASK 0x00080000L -#define spi_cs_wave_ctl__Reserved0_MASK 0xfff00000L - -// spi_ps_ctl0_0 -#define spi_ps_ctl0_0__new_vector1_save_q_MASK 0x00000001L -#define spi_ps_ctl0_0__new_vector0_save_q_MASK 0x00000002L -#define spi_ps_ctl0_0__vtx_sync_cnt_q_MASK 0x000003fcL -#define spi_ps_ctl0_0__vtx_sync_wrapped_MASK 0x00000400L -#define spi_ps_ctl0_0__ose_vtx_sync_cnt_q_MASK 0x0007f800L -#define spi_ps_ctl0_0__psc_wr_line_q_MASK 0x00380000L -#define spi_ps_ctl0_0__psc_gdbg_en_q_MASK 0x00400000L -#define spi_ps_ctl0_0__Reserved0_MASK 0xff800000L - -// spi_ps_ctl0_1 -#define spi_ps_ctl0_1__wd_end_of_wave_MASK 0x00000001L -#define spi_ps_ctl0_1__wd_fifo_empty_MASK 0x00000002L -#define spi_ps_ctl0_1__wd_fifo_full_MASK 0x00000004L -#define spi_ps_ctl0_1__ef_end_of_wave_MASK 0x00000008L -#define spi_ps_ctl0_1__ef_state_id_MASK 0x00000070L -#define spi_ps_ctl0_1__ef_event_id_MASK 0x00001f80L -#define spi_ps_ctl0_1__ef_event_MASK 0x00002000L -#define spi_ps_ctl0_1__ef_new1_MASK 0x00004000L -#define spi_ps_ctl0_1__ef_new0_MASK 0x00008000L -#define spi_ps_ctl0_1__ef_empty_MASK 0x00010000L -#define spi_ps_ctl0_1__ef_full_MASK 0x00020000L -#define spi_ps_ctl0_1__ef_new3_MASK 0x00040000L -#define spi_ps_ctl0_1__ef_new2_MASK 0x00080000L -#define spi_ps_ctl0_1__pipe_id_MASK 0x00300000L -#define spi_ps_ctl0_1__Reserved0_MASK 0xffc00000L - -// spi_ps_ctl0_2 -#define spi_ps_ctl0_2__res_alloc_state_MASK 0x00000001L -#define spi_ps_ctl0_2__psr_wave_cnt_MASK 0x0000007eL -#define spi_ps_ctl0_2__psc_read_data_MASK 0x00000f80L -#define spi_ps_ctl0_2__pc_free_cnt_MASK 0x0000f000L -#define spi_ps_ctl0_2__dealloc1_save_q_MASK 0x00070000L -#define spi_ps_ctl0_2__dealloc0_save_q_MASK 0x00380000L -#define spi_ps_ctl0_2__tr_fits_MASK 0x00400000L -#define spi_ps_ctl0_2__ps_wave_cnt_lt_lim_MASK 0x00800000L -#define spi_ps_ctl0_2__Reserved0_MASK 0xff000000L - -// spi_ps_ctl0_3 -#define spi_ps_ctl0_3__new_vector2_save_q_MASK 0x00000001L -#define spi_ps_ctl0_3__new_vector3_save_q_MASK 0x00000002L -#define spi_ps_ctl0_3__ose1_vtx_sync_cnt_q_MASK 0x000003fcL -#define spi_ps_ctl0_3__ose2_vtx_sync_cnt_q_MASK 0x0003fc00L -#define spi_ps_ctl0_3__dealloc2_save_q_MASK 0x001c0000L -#define spi_ps_ctl0_3__dealloc3_save_q_MASK 0x00e00000L -#define spi_ps_ctl0_3__Reserved0_MASK 0xff000000L - -// spi_ps_ctl0_4 -#define spi_ps_ctl0_4__crawler_rd_MASK 0x0000007fL -#define spi_ps_ctl0_4__crawler_is_event_MASK 0x00000080L -#define spi_ps_ctl0_4__stall_events_MASK 0x00000100L -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_crawler_id_q_MASK 0x0001fe00L -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_ps_pkr_id_q_MASK 0x00020000L -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_wave_type_q_MASK 0x001c0000L -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_wave_done_q_MASK 0x00200000L -#define spi_ps_ctl0_4__crawler_full_MASK 0x00400000L -#define spi_ps_ctl0_4__crawler_empty_MASK 0x00800000L -#define spi_ps_ctl0_4__Reserved0_MASK 0xff000000L - -// spi_ps_ctl1_0 -#define spi_ps_ctl1_0__new_vector1_save_q_MASK 0x00000001L -#define spi_ps_ctl1_0__new_vector0_save_q_MASK 0x00000002L -#define spi_ps_ctl1_0__vtx_sync_cnt_q_MASK 0x000003fcL -#define spi_ps_ctl1_0__vtx_sync_wrapped_MASK 0x00000400L -#define spi_ps_ctl1_0__ose_vtx_sync_cnt_q_MASK 0x0007f800L -#define spi_ps_ctl1_0__psc_wr_line_q_MASK 0x00380000L -#define spi_ps_ctl1_0__psc_gdbg_en_q_MASK 0x00400000L -#define spi_ps_ctl1_0__Reserved0_MASK 0xff800000L - -// spi_ps_ctl1_1 -#define spi_ps_ctl1_1__wd_end_of_wave_MASK 0x00000001L -#define spi_ps_ctl1_1__wd_fifo_empty_MASK 0x00000002L -#define spi_ps_ctl1_1__wd_fifo_full_MASK 0x00000004L -#define spi_ps_ctl1_1__ef_end_of_wave_MASK 0x00000008L -#define spi_ps_ctl1_1__ef_state_id_MASK 0x00000070L -#define spi_ps_ctl1_1__ef_event_id_MASK 0x00001f80L -#define spi_ps_ctl1_1__ef_event_MASK 0x00002000L -#define spi_ps_ctl1_1__ef_new1_MASK 0x00004000L -#define spi_ps_ctl1_1__ef_new0_MASK 0x00008000L -#define spi_ps_ctl1_1__ef_empty_MASK 0x00010000L -#define spi_ps_ctl1_1__ef_full_MASK 0x00020000L -#define spi_ps_ctl1_1__ef_new3_MASK 0x00040000L -#define spi_ps_ctl1_1__ef_new2_MASK 0x00080000L -#define spi_ps_ctl1_1__pipe_id_MASK 0x00300000L -#define spi_ps_ctl1_1__Reserved0_MASK 0xffc00000L - -// spi_ps_ctl1_2 -#define spi_ps_ctl1_2__res_alloc_state_MASK 0x00000001L -#define spi_ps_ctl1_2__psr_wave_cnt_MASK 0x0000007eL -#define spi_ps_ctl1_2__psc_read_data_MASK 0x00000f80L -#define spi_ps_ctl1_2__pc_free_cnt_MASK 0x0000f000L -#define spi_ps_ctl1_2__dealloc1_save_q_MASK 0x00070000L -#define spi_ps_ctl1_2__dealloc0_save_q_MASK 0x00380000L -#define spi_ps_ctl1_2__tr_fits_MASK 0x00400000L -#define spi_ps_ctl1_2__ps_wave_cnt_lt_lim_MASK 0x00800000L -#define spi_ps_ctl1_2__Reserved0_MASK 0xff000000L - -// spi_ps_ctl1_3 -#define spi_ps_ctl1_3__new_vector2_save_q_MASK 0x00000001L -#define spi_ps_ctl1_3__new_vector3_save_q_MASK 0x00000002L -#define spi_ps_ctl1_3__ose1_vtx_sync_cnt_q_MASK 0x000003fcL -#define spi_ps_ctl1_3__ose2_vtx_sync_cnt_q_MASK 0x0003fc00L -#define spi_ps_ctl1_3__dealloc2_save_q_MASK 0x001c0000L -#define spi_ps_ctl1_3__dealloc3_save_q_MASK 0x00e00000L -#define spi_ps_ctl1_3__Reserved0_MASK 0xff000000L - -// spi_ps_ctl1_4 -#define spi_ps_ctl1_4__crawler_rd_MASK 0x0000007fL -#define spi_ps_ctl1_4__crawler_is_event_MASK 0x00000080L -#define spi_ps_ctl1_4__stall_events_MASK 0x00000100L -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_crawler_id_q_7_0_MASK 0x0001fe00L -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_ps_pkr_id_q_MASK 0x00020000L -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_wave_type_q_MASK 0x001c0000L -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_wave_done_q_MASK 0x00200000L -#define spi_ps_ctl1_4__crawler_full_MASK 0x00400000L -#define spi_ps_ctl1_4__crawler_empty_MASK 0x00800000L -#define spi_ps_ctl1_4__Reserved0_MASK 0xff000000L - -// spi_pc_dealloc_ctl0 -#define spi_pc_dealloc_ctl0__decr_pc_dealloc_cnt_MASK 0x00000001L -#define spi_pc_dealloc_ctl0__pc_dealloc_min_cnt_MASK 0x000007feL -#define spi_pc_dealloc_ctl0__pc0_dealloc_cnt_MASK 0x001ff800L -#define spi_pc_dealloc_ctl0__Reserved0_MASK 0xffe00000L - -// spi_pc_dealloc_ctl1 -#define spi_pc_dealloc_ctl1__pc1_dealloc_cnt_MASK 0x000003ffL -#define spi_pc_dealloc_ctl1__pc_deallocIn0_cnt_MASK 0x000ffc00L -#define spi_pc_dealloc_ctl1__Reserved0_MASK 0xfff00000L - -// spi_pc_dealloc_ctl2 -#define spi_pc_dealloc_ctl2__pc_deallocIn1_cnt_MASK 0x000003ffL -#define spi_pc_dealloc_ctl2__pc_deallocIn2_cnt_MASK 0x000ffc00L -#define spi_pc_dealloc_ctl2__Reserved0_MASK 0xfff00000L - -// spi_pc_dealloc_ctl3 -#define spi_pc_dealloc_ctl3__pc0_deallocOut0_cnt_MASK 0x000003ffL -#define spi_pc_dealloc_ctl3__pc0_deallocOut1_cnt_MASK 0x000ffc00L -#define spi_pc_dealloc_ctl3__Reserved0_MASK 0xfff00000L - -// spi_pc_dealloc_ctl4 -#define spi_pc_dealloc_ctl4__pc0_deallocOut2_cnt_MASK 0x000003ffL -#define spi_pc_dealloc_ctl4__pc1_deallocOut0_cnt_MASK 0x000ffc00L -#define spi_pc_dealloc_ctl4__Reserved0_MASK 0xfff00000L - -// spi_pc_dealloc_ctl5 -#define spi_pc_dealloc_ctl5__pc1_deallocOut1_cnt_MASK 0x000003ffL -#define spi_pc_dealloc_ctl5__pc1_deallocOut2_cnt_MASK 0x000ffc00L -#define spi_pc_dealloc_ctl5__Reserved0_MASK 0xfff00000L - -// spi_offchip_lds_mgr0 -#define spi_offchip_lds_mgr0__es_threadgroup_done_count_MASK 0x0000007fL -#define spi_offchip_lds_mgr0__Reserved2_MASK 0x00000080L -#define spi_offchip_lds_mgr0__lds_offchip_tail_MASK 0x00007f00L -#define spi_offchip_lds_mgr0__Reserved1_MASK 0x00008000L -#define spi_offchip_lds_mgr0__lds_offchip_head_MASK 0x007f0000L -#define spi_offchip_lds_mgr0__Reserved0_MASK 0xff800000L - -// spi_offchip_lds_mgr1 -#define spi_offchip_lds_mgr1__lds_offchip_full_MASK 0x00000001L -#define spi_offchip_lds_mgr1__order_fifo_rd_MASK 0x00000002L -#define spi_offchip_lds_mgr1__order_fifo_full_MASK 0x00000004L -#define spi_offchip_lds_mgr1__order_fifo_empty_MASK 0x00000008L -#define spi_offchip_lds_mgr1__esc_olm_ds_offchip_done_MASK 0x00000010L -#define spi_offchip_lds_mgr1__vsc_olm_ds_offchip_done_MASK 0x00000020L -#define spi_offchip_lds_mgr1__Reserved1_MASK 0x000000c0L -#define spi_offchip_lds_mgr1__vs_threadgroup_done_count_MASK 0x00007f00L -#define spi_offchip_lds_mgr1__Reserved0_MASK 0xffff8000L - -// spi_lds_wr_ctl0 -#define spi_lds_wr_ctl0__state_id_MASK 0x00000007L -#define spi_lds_wr_ctl0__lds_in_fifo_empty_MASK 0x00000008L -#define spi_lds_wr_ctl0__lds_in_fifo_full_MASK 0x00000010L -#define spi_lds_wr_ctl0__lds_write_state_MASK 0x00000060L -#define spi_lds_wr_ctl0__even_debug_lds_valid_d_MASK 0x00000080L -#define spi_lds_wr_ctl0__even_debug_lds_valid_q1_MASK 0x00000100L -#define spi_lds_wr_ctl0__even_debug_lwc_pc_valid_MASK 0x00000200L -#define spi_lds_wr_ctl0__even_debug_lds_param_sent_cnt_q_MASK 0x0000fc00L -#define spi_lds_wr_ctl0__even_debug_lds_pass_cnt_q_MASK 0x000f0000L -#define spi_lds_wr_ctl0__even_debug_stall_odd_MASK 0x00100000L -#define spi_lds_wr_ctl0__Reserved0_MASK 0xffe00000L - -// spi_lds_wr_ctl1 -#define spi_lds_wr_ctl1__odd_debug_lds_valid_d_MASK 0x00000001L -#define spi_lds_wr_ctl1__odd_debug_lds_valid_q1_MASK 0x00000002L -#define spi_lds_wr_ctl1__odd_debug_lwc_pc_valid_MASK 0x00000004L -#define spi_lds_wr_ctl1__odd_debug_lds_param_sent_cnt_q_MASK 0x000001f8L -#define spi_lds_wr_ctl1__odd_debug_lds_pass_cnt_q_MASK 0x00001e00L -#define spi_lds_wr_ctl1__Reserved0_MASK 0xffffe000L - -// spi_resource_alloc0 -#define spi_resource_alloc0__Reserved1_MASK 0x00000001L -#define spi_resource_alloc0__lds_updating_cu_simd_id_q_MASK 0x0000001eL -#define spi_resource_alloc0__sgpr_updating_cu_simd_id_q_MASK 0x000007e0L -#define spi_resource_alloc0__vgpr_updating_cu_simd_id_q_MASK 0x0001f800L -#define spi_resource_alloc0__allocating_cu_simd_q_MASK 0x007e0000L -#define spi_resource_alloc0__Reserved0_MASK 0xff800000L - -// spi_resource_alloc1 -#define spi_resource_alloc1__vgpr_dealloc_pointer_23_0_MASK 0x00ffffffL -#define spi_resource_alloc1__Reserved0_MASK 0xff000000L - -// spi_resource_alloc2 -#define spi_resource_alloc2__vgpr_dealloc_pointer_47_24_MASK 0x00ffffffL -#define spi_resource_alloc2__Reserved0_MASK 0xff000000L - -// spi_resource_alloc3 -#define spi_resource_alloc3__sgpr_dealloc_pointer_23_0_MASK 0x00ffffffL -#define spi_resource_alloc3__Reserved0_MASK 0xff000000L - -// spi_resource_alloc4 -#define spi_resource_alloc4__sgpr_dealloc_pointer_47_24_MASK 0x00ffffffL -#define spi_resource_alloc4__Reserved0_MASK 0xff000000L - -// spi_resource_alloc5 -#define spi_resource_alloc5__Reserved0_MASK 0xffffffffL - -// spi_resource_alloc6 -#define spi_resource_alloc6__sgpr_max_fits_cnt_MASK 0x0000007fL -#define spi_resource_alloc6__vgpr_max_fits_cnt_MASK 0x00003f80L -#define spi_resource_alloc6__dbg_cu_simd_id_MASK 0x000fc000L -#define spi_resource_alloc6__Reserved0_MASK 0xfff00000L - -// spi_resource_alloc7 -#define spi_resource_alloc7__alloc_state_q_MASK 0x00000001L -#define spi_resource_alloc7__ts_priority_MASK 0x0000000eL -#define spi_resource_alloc7__dbg_lds_dealloc_pointer_MASK 0x000ffff0L -#define spi_resource_alloc7__Reserved0_MASK 0xfff00000L - -// spi_resource_alloc8 -#define spi_resource_alloc8__dbg_lock_mask_MASK 0x0000ffffL -#define spi_resource_alloc8__Reserved0_MASK 0xffff0000L - -// spi_resource_alloc9 -#define spi_resource_alloc9__wave_cnt_cu_simd_MASK 0x0000000fL -#define spi_resource_alloc9__vgpr_rsv_max_fits_cnt_MASK 0x000007f0L -#define spi_resource_alloc9__sgpr_rsv_max_fits_cnt_MASK 0x0003f800L -#define spi_resource_alloc9__Reserved0_MASK 0xfffc0000L - -// spi_resource_alloc10 -#define spi_resource_alloc10__barrier_cnt_per_cu_MASK 0x0000001fL -#define spi_resource_alloc10__lds_rsv_max_fits_cnt_MASK 0x00001fe0L -#define spi_resource_alloc10__Reserved1_MASK 0x00002000L -#define spi_resource_alloc10__lds_max_fits_cnt_MASK 0x003fc000L -#define spi_resource_alloc10__Reserved0_MASK 0xffc00000L - -// spi_clk_gate0 -#define spi_clk_gate0__read_ack_out_MASK 0x00000001L -#define spi_clk_gate0__program_ack_out_MASK 0x00000002L -#define spi_clk_gate0__sm_busy_out_MASK 0x00000004L -#define spi_clk_gate0__force_data_out_MASK 0x00000008L -#define spi_clk_gate0__data_out_MASK 0x00000010L -#define spi_clk_gate0__valid_out_MASK 0x00000020L -#define spi_clk_gate0__state_out_MASK 0x00000040L -#define spi_clk_gate0__program_out_MASK 0x00000080L -#define spi_clk_gate0__curr_sm_state_MASK 0x00001f00L -#define spi_clk_gate0__off_cmd_MASK 0x00002000L -#define spi_clk_gate0__all_clks_on_flag_in_MASK 0x00004000L -#define spi_clk_gate0__off_flag_in_MASK 0x00008000L -#define spi_clk_gate0__read_flag_in_MASK 0x00010000L -#define spi_clk_gate0__program_flag_in_MASK 0x00020000L -#define spi_clk_gate0__on_cmd_MASK 0x00040000L -#define spi_clk_gate0__on_flag_in_MASK 0x00080000L -#define spi_clk_gate0__force_override_in_MASK 0x00100000L -#define spi_clk_gate0__cgtt_reg_oclk_vld_MASK 0x00200000L -#define spi_clk_gate0__cgtt_dyn_oclk_vld_MASK 0x00400000L -#define spi_clk_gate0__Reserved0_MASK 0xff800000L - -// spi_clk_gate1 -#define spi_clk_gate1__off_seq_cnt_eq0_MASK 0x00000001L -#define spi_clk_gate1__off_seq_cnt_decr_MASK 0x00000002L -#define spi_clk_gate1__off_seq_cnt_ld_MASK 0x00000004L -#define spi_clk_gate1__on_seq_cnt_eq0_MASK 0x00000008L -#define spi_clk_gate1__on_seq_cnt_decr_MASK 0x00000010L -#define spi_clk_gate1__on_seq_cnt_ld_MASK 0x00000020L -#define spi_clk_gate1__blk_row_cnt_last_MASK 0x00000040L -#define spi_clk_gate1__mxn_bit_cnt_last_MASK 0x00000080L -#define spi_clk_gate1__cu_cnt_out_MASK 0x00000f00L -#define spi_clk_gate1__blk_row_cnt_out_MASK 0x0000f000L -#define spi_clk_gate1__blk_row_cnt_sel_out_MASK 0x00010000L -#define spi_clk_gate1__Reserved1_MASK 0x00020000L -#define spi_clk_gate1__mxn_bit_reg_ld_out_MASK 0x00040000L -#define spi_clk_gate1__mxn_bit_reg_shift_out_MASK 0x00080000L -#define spi_clk_gate1__Reserved0_MASK 0xfff00000L - -// spi_clk_gate2 -#define spi_clk_gate2__on_monitor_cnt_10_0_MASK 0x000007ffL -#define spi_clk_gate2__clkgate_all_on_out_MASK 0x00000800L -#define spi_clk_gate2__spi_active_in_MASK 0x00001000L -#define spi_clk_gate2__data_out_MASK 0x00002000L -#define spi_clk_gate2__on_monitor_flag_MASK 0x00004000L -#define spi_clk_gate2__off_seq_decode_MASK 0x00008000L -#define spi_clk_gate2__on_seq_decode_MASK 0x00010000L -#define spi_clk_gate2__ctrl_ls_override_MASK 0x00020000L -#define spi_clk_gate2__rss_clkgate_en_combined_MASK 0x00040000L -#define spi_clk_gate2__rss_cnt_eq0_MASK 0x00080000L -#define spi_clk_gate2__rss_cnt_ld_MASK 0x00100000L -#define spi_clk_gate2__Reserved0_MASK 0xffe00000L - -// spi_clk_gate3 -#define spi_clk_gate3__rd_row_mux_sel_MASK 0x0000001fL -#define spi_clk_gate3__rd_reg_loaded_dummy_MASK 0x00000020L -#define spi_clk_gate3__rdbus_data_MASK 0x00000040L -#define spi_clk_gate3__rdbus_valid_MASK 0x00000080L -#define spi_clk_gate3__rd_reg_loaded_MASK 0x0003ff00L -#define spi_clk_gate3__Reserved0_MASK 0xfffc0000L - -// CPC_debug_bus0_p0 -#define CPC_debug_bus0_p0__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p0__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p0__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p0__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p0__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p0 -#define CPC_debug_bus1_p0__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p0__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p0__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p0 -#define CPC_debug_bus2_p0__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p0__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p0__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p0__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p0__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p0__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p0__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p0__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p0__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p0__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p0__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p0__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p0__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p0__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p0__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p0__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p0__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p0 -#define CPC_debug_bus3_p0__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p0__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p0__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p0__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p0 -#define CPC_debug_bus4_p0__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p0__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p0__Reserved0_MASK 0xff000000L - -// CPC_debug_bus0_p1 -#define CPC_debug_bus0_p1__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p1__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p1__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p1__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p1__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p1 -#define CPC_debug_bus1_p1__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p1__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p1__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p1 -#define CPC_debug_bus2_p1__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p1__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p1__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p1__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p1__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p1__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p1__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p1__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p1__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p1__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p1__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p1__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p1__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p1__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p1__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p1__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p1__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p1 -#define CPC_debug_bus3_p1__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p1__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p1__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p1__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p1 -#define CPC_debug_bus4_p1__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p1__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p1__Reserved0_MASK 0xff000000L - -// CPC_debug_bus0_p2 -#define CPC_debug_bus0_p2__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p2__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p2__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p2__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p2__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p2 -#define CPC_debug_bus1_p2__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p2__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p2__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p2 -#define CPC_debug_bus2_p2__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p2__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p2__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p2__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p2__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p2__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p2__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p2__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p2__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p2__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p2__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p2__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p2__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p2__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p2__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p2__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p2__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p2 -#define CPC_debug_bus3_p2__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p2__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p2__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p2__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p2 -#define CPC_debug_bus4_p2__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p2__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p2__Reserved0_MASK 0xff000000L - -// CPC_debug_bus0_p3 -#define CPC_debug_bus0_p3__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p3__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p3__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p3__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p3__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p3 -#define CPC_debug_bus1_p3__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p3__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p3__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p3 -#define CPC_debug_bus2_p3__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p3__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p3__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p3__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p3__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p3__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p3__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p3__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p3__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p3__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p3__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p3__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p3__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p3__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p3__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p3__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p3__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p3 -#define CPC_debug_bus3_p3__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p3__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p3__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p3__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p3 -#define CPC_debug_bus4_p3__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p3__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p3__Reserved0_MASK 0xff000000L - -// CPC_debug_bus0_p4 -#define CPC_debug_bus0_p4__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p4__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p4__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p4__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p4__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p4 -#define CPC_debug_bus1_p4__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p4__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p4__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p4 -#define CPC_debug_bus2_p4__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p4__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p4__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p4__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p4__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p4__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p4__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p4__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p4__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p4__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p4__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p4__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p4__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p4__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p4__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p4__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p4__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p4 -#define CPC_debug_bus3_p4__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p4__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p4__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p4__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p4 -#define CPC_debug_bus4_p4__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p4__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p4__Reserved0_MASK 0xff000000L - -// CPC_debug_bus0_p5 -#define CPC_debug_bus0_p5__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p5__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p5__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p5__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p5__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p5 -#define CPC_debug_bus1_p5__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p5__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p5__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p5 -#define CPC_debug_bus2_p5__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p5__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p5__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p5__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p5__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p5__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p5__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p5__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p5__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p5__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p5__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p5__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p5__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p5__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p5__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p5__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p5__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p5 -#define CPC_debug_bus3_p5__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p5__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p5__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p5__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p5 -#define CPC_debug_bus4_p5__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p5__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p5__Reserved0_MASK 0xff000000L - -// CPC_debug_bus0_p6 -#define CPC_debug_bus0_p6__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p6__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p6__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p6__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p6__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p6 -#define CPC_debug_bus1_p6__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p6__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p6__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p6 -#define CPC_debug_bus2_p6__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p6__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p6__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p6__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p6__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p6__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p6__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p6__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p6__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p6__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p6__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p6__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p6__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p6__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p6__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p6__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p6__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p6 -#define CPC_debug_bus3_p6__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p6__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p6__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p6__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p6 -#define CPC_debug_bus4_p6__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p6__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p6__Reserved0_MASK 0xff000000L - -// CPC_debug_bus0_p7 -#define CPC_debug_bus0_p7__gd_valid_MASK 0x00000001L -#define CPC_debug_bus0_p7__gd_data_type_MASK 0x00000006L -#define CPC_debug_bus0_p7__gd_addr_MASK 0x000003f8L -#define CPC_debug_bus0_p7__gd_data_13_0_MASK 0x00fffc00L -#define CPC_debug_bus0_p7__Reserved0_MASK 0xff000000L - -// CPC_debug_bus1_p7 -#define CPC_debug_bus1_p7__gd_valid_MASK 0x00000001L -#define CPC_debug_bus1_p7__gd_data_31_14_MASK 0x0007fffeL -#define CPC_debug_bus1_p7__Reserved0_MASK 0xfff80000L - -// CPC_debug_bus2_p7 -#define CPC_debug_bus2_p7__valid_q0_MASK 0x00000001L -#define CPC_debug_bus2_p7__state_q_MASK 0x0000001eL -#define CPC_debug_bus2_p7__steering_state_q_MASK 0x000000e0L -#define CPC_debug_bus2_p7__first_thread_group_q0_MASK 0x00000100L -#define CPC_debug_bus2_p7__last_thread_group_q0_MASK 0x00000200L -#define CPC_debug_bus2_p7__kill_dispatch_mode0_MASK 0x00000400L -#define CPC_debug_bus2_p7__kill_dispatch_mode1_MASK 0x00000800L -#define CPC_debug_bus2_p7__gd_stall_MASK 0x00001000L -#define CPC_debug_bus2_p7__disp_stall_q_MASK 0x00002000L -#define CPC_debug_bus2_p7__no_serializer_is_busy_MASK 0x00004000L -#define CPC_debug_bus2_p7__gd_dispatch_busy_MASK 0x00008000L -#define CPC_debug_bus2_p7__gd_busy_MASK 0x00010000L -#define CPC_debug_bus2_p7__num_se_with_cu_active_MASK 0x000e0000L -#define CPC_debug_bus2_p7__send_num_threads_x_q_MASK 0x00100000L -#define CPC_debug_bus2_p7__send_num_threads_y_q_MASK 0x00200000L -#define CPC_debug_bus2_p7__send_num_threads_z_q_MASK 0x00400000L -#define CPC_debug_bus2_p7__Reserved0_MASK 0xff800000L - -// CPC_debug_bus3_p7 -#define CPC_debug_bus3_p7__gddata_send_MASK 0x00000001L -#define CPC_debug_bus3_p7__gddata_data_type_MASK 0x00000006L -#define CPC_debug_bus3_p7__data_x_q1_20_0_MASK 0x00fffff8L -#define CPC_debug_bus3_p7__Reserved0_MASK 0xff000000L - -// CPC_debug_bus4_p7 -#define CPC_debug_bus4_p7__data_y_q1_11_0_MASK 0x00000fffL -#define CPC_debug_bus4_p7__data_z_q1_11_0_MASK 0x00fff000L -#define CPC_debug_bus4_p7__Reserved0_MASK 0xff000000L - -// CPC_SRDebugBus_23_0 -#define CPC_SRDebugBus_23_0__SRSaveSmDebugBus_MASK 0x000001ffL -#define CPC_SRDebugBus_23_0__SRSaveTciuDebugBus_14_0_MASK 0x00fffe00L -#define CPC_SRDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPC_SRDebugBus_47_24 -#define CPC_SRDebugBus_47_24__SRSaveTciuDebugBus_20_15_MASK 0x0000003fL -#define CPC_SRDebugBus_47_24__SRSaveIntrptDebugBus_17_0_MASK 0x00ffffc0L -#define CPC_SRDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPC_SRDebugBus_71_48 -#define CPC_SRDebugBus_71_48__SRSaveIntrptDebugBus_27_18_MASK 0x000003ffL -#define CPC_SRDebugBus_71_48__crawler0_data_5_0_MASK 0x0000fc00L -#define CPC_SRDebugBus_71_48__crawler1_data_5_0_MASK 0x003f0000L -#define CPC_SRDebugBus_71_48__crawler2_data_1_0_MASK 0x00c00000L -#define CPC_SRDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPC_SRDebugBus_95_72 -#define CPC_SRDebugBus_95_72__crawler2_data_5_2_MASK 0x0000000fL -#define CPC_SRDebugBus_95_72__crawler3_data_5_0_MASK 0x000003f0L -#define CPC_SRDebugBus_95_72__Reserved0_MASK 0xfffffc00L - -// CPC_SRDebugBus_119_96 -#define CPC_SRDebugBus_119_96__Reserved0_MASK 0xffffffffL - -// CPC_QueryUnitDebugBus_23_0 -#define CPC_QueryUnitDebugBus_23_0__RegisterClkValid_MASK 0x00000003L -#define CPC_QueryUnitDebugBus_23_0__Reserved1_MASK 0x0000000cL -#define CPC_QueryUnitDebugBus_23_0__qCsinvocWrError_MASK 0x00000010L -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoEmpty_MASK 0x00000020L -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoFull_MASK 0x00000040L -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoRdEn_MASK 0x00000080L -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoWrEn_MASK 0x00000100L -#define CPC_QueryUnitDebugBus_23_0__qQueryState_MASK 0x00000e00L -#define CPC_QueryUnitDebugBus_23_0__CsinvocWrErrorThread_0_MASK 0x00001000L -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoEmpty_0_MASK 0x00002000L -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoFull_0_MASK 0x00004000L -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoRdEn_0_MASK 0x00008000L -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoWrEn_0_MASK 0x00010000L -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoEmpty_0_MASK 0x00020000L -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoFull_0_MASK 0x00040000L -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoRdEn_0_MASK 0x00080000L -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoWrEn_0_MASK 0x00100000L -#define CPC_QueryUnitDebugBus_23_0__PipeOutstandingTagCnt0_neq_0_MASK 0x00200000L -#define CPC_QueryUnitDebugBus_23_0__PipeStatsBusyThread_0_MASK 0x00400000L -#define CPC_QueryUnitDebugBus_23_0__PipeStatsPendFlagThread_0_MASK 0x00800000L -#define CPC_QueryUnitDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPC_QueryUnitDebugBus_47_24 -#define CPC_QueryUnitDebugBus_47_24__CsinvocWrErrorThread_1_MASK 0x00000001L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoEmpty_1_MASK 0x00000002L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoFull_1_MASK 0x00000004L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoRdEn_1_MASK 0x00000008L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoWrEn_1_MASK 0x00000010L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoEmpty_1_MASK 0x00000020L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoFull_1_MASK 0x00000040L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoRdEn_1_MASK 0x00000080L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoWrEn_1_MASK 0x00000100L -#define CPC_QueryUnitDebugBus_47_24__PipeOutstandingTagCnt1_neq_0_MASK 0x00000200L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsBusyThread_1_MASK 0x00000400L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsPendFlagThread_1_MASK 0x00000800L -#define CPC_QueryUnitDebugBus_47_24__CsinvocWrErrorThread_2_MASK 0x00001000L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoEmpty_2_MASK 0x00002000L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoFull_2_MASK 0x00004000L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoRdEn_2_MASK 0x00008000L -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoWrEn_2_MASK 0x00010000L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoEmpty_2_MASK 0x00020000L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoFull_2_MASK 0x00040000L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoRdEn_2_MASK 0x00080000L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoWrEn_2_MASK 0x00100000L -#define CPC_QueryUnitDebugBus_47_24__PipeOutstandingTagCnt2_neq_0_MASK 0x00200000L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsBusyThread_2_MASK 0x00400000L -#define CPC_QueryUnitDebugBus_47_24__PipeStatsPendFlagThread_2_MASK 0x00800000L -#define CPC_QueryUnitDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPC_QueryUnitDebugBus_71_48 -#define CPC_QueryUnitDebugBus_71_48__CsinvocWrErrorThread_3_MASK 0x00000001L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoEmpty_3_MASK 0x00000002L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoFull_3_MASK 0x00000004L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoRdEn_3_MASK 0x00000008L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoWrEn_3_MASK 0x00000010L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoEmpty_3_MASK 0x00000020L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoFull_3_MASK 0x00000040L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoRdEn_3_MASK 0x00000080L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoWrEn_3_MASK 0x00000100L -#define CPC_QueryUnitDebugBus_71_48__PipeOutstandingTagCnt3_neq_0_MASK 0x00000200L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsBusyThread_3_MASK 0x00000400L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsPendFlagThread_3_MASK 0x00000800L -#define CPC_QueryUnitDebugBus_71_48__CsinvocWrErrorThread_4_MASK 0x00001000L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoEmpty_4_MASK 0x00002000L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoFull_4_MASK 0x00004000L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoRdEn_4_MASK 0x00008000L -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoWrEn_4_MASK 0x00010000L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoEmpty_4_MASK 0x00020000L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoFull_4_MASK 0x00040000L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoRdEn_4_MASK 0x00080000L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoWrEn_4_MASK 0x00100000L -#define CPC_QueryUnitDebugBus_71_48__PipeOutstandingTagCnt4_neq_0_MASK 0x00200000L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsBusyThread_4_MASK 0x00400000L -#define CPC_QueryUnitDebugBus_71_48__PipeStatsPendFlagThread_4_MASK 0x00800000L -#define CPC_QueryUnitDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPC_QueryUnitDebugBus_95_72 -#define CPC_QueryUnitDebugBus_95_72__CsinvocWrErrorThread_5_MASK 0x00000001L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoEmpty_5_MASK 0x00000002L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoFull_5_MASK 0x00000004L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoRdEn_5_MASK 0x00000008L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoWrEn_5_MASK 0x00000010L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoEmpty_5_MASK 0x00000020L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoFull_5_MASK 0x00000040L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoRdEn_5_MASK 0x00000080L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoWrEn_5_MASK 0x00000100L -#define CPC_QueryUnitDebugBus_95_72__PipeOutstandingTagCnt5_neq_0_MASK 0x00000200L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsBusyThread_5_MASK 0x00000400L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsPendFlagThread_5_MASK 0x00000800L -#define CPC_QueryUnitDebugBus_95_72__CsinvocWrErrorThread_6_MASK 0x00001000L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoEmpty_6_MASK 0x00002000L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoFull_6_MASK 0x00004000L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoRdEn_6_MASK 0x00008000L -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoWrEn_6_MASK 0x00010000L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoEmpty_6_MASK 0x00020000L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoFull_6_MASK 0x00040000L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoRdEn_6_MASK 0x00080000L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoWrEn_6_MASK 0x00100000L -#define CPC_QueryUnitDebugBus_95_72__PipeOutstandingTagCnt6_neq_0_MASK 0x00200000L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsBusyThread_6_MASK 0x00400000L -#define CPC_QueryUnitDebugBus_95_72__PipeStatsPendFlagThread_6_MASK 0x00800000L -#define CPC_QueryUnitDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPC_QueryUnitDebugBus_119_96 -#define CPC_QueryUnitDebugBus_119_96__CsinvocWrErrorThread_7_MASK 0x00000001L -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoEmpty_7_MASK 0x00000002L -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoFull_7_MASK 0x00000004L -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoRdEn_7_MASK 0x00000008L -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoWrEn_7_MASK 0x00000010L -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoEmpty_7_MASK 0x00000020L -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoFull_7_MASK 0x00000040L -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoRdEn_7_MASK 0x00000080L -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoWrEn_7_MASK 0x00000100L -#define CPC_QueryUnitDebugBus_119_96__PipeOutstandingTagCnt7_neq_0_MASK 0x00000200L -#define CPC_QueryUnitDebugBus_119_96__PipeStatsBusyThread_7_MASK 0x00000400L -#define CPC_QueryUnitDebugBus_119_96__PipeStatsPendFlagThread_7_MASK 0x00000800L -#define CPC_QueryUnitDebugBus_119_96__Reserved0_MASK 0xfffff000L - -// CPC_QueryUnitDebugBus_127_120 -#define CPC_QueryUnitDebugBus_127_120__Reserved0_MASK 0xffffffffL - -// CPC_MecScratchDebugBus_7_0 -#define CPC_MecScratchDebugBus_7_0__qWrArbState_MASK 0x00000001L -#define CPC_MecScratchDebugBus_7_0__qRdClientSelect_MASK 0x00000002L -#define CPC_MecScratchDebugBus_7_0__qMec2ReadState_MASK 0x0000000cL -#define CPC_MecScratchDebugBus_7_0__qMec1ReadState_MASK 0x00000030L -#define CPC_MecScratchDebugBus_7_0__qRegReadState_MASK 0x000000c0L -#define CPC_MecScratchDebugBus_7_0__Reserved0_MASK 0xffffff00L - -// CPC_RbiuDebugBus_11_0 -#define CPC_RbiuDebugBus_11_0__qGRBM_CPC_reg_send_MASK 0x00000001L -#define CPC_RbiuDebugBus_11_0__qReadState_MASK 0x00000002L -#define CPC_RbiuDebugBus_11_0__qReadCycleCount_MASK 0x0000001cL -#define CPC_RbiuDebugBus_11_0__Reserved0_MASK 0xffffffe0L - -// CPC_RciuDebugBus_23_0 -#define CPC_RciuDebugBus_23_0__qCpcGrbmSendArb_MASK 0x00000007L -#define CPC_RciuDebugBus_23_0__qCpcGrbmPipeSend_MASK 0x00000008L -#define CPC_RciuDebugBus_23_0__OR_qMec1SendCntUnderflow_MASK 0x00000010L -#define CPC_RciuDebugBus_23_0__OR_qMec1SendCntOverflow_MASK 0x00000020L -#define CPC_RciuDebugBus_23_0__OR_qMec2SendCntUnderflow_MASK 0x00000040L -#define CPC_RciuDebugBus_23_0__OR_qMec2SendCntOverflow_MASK 0x00000080L -#define CPC_RciuDebugBus_23_0__qGrbmCpReadValid_MASK 0x00000100L -#define CPC_RciuDebugBus_23_0__qGrbmCpReadPipeId_MASK 0x00000600L -#define CPC_RciuDebugBus_23_0__qGrbmCpReadMeId_MASK 0x00001800L -#define CPC_RciuDebugBus_23_0__Mec1RciuFifoFull_3_0_MASK 0x0001e000L -#define CPC_RciuDebugBus_23_0__Mec1RciuFifoEmpty_3_0_MASK 0x001e0000L -#define CPC_RciuDebugBus_23_0__qMec1GrbmSendCnt0_neq_qMec1SendCntMax0_MASK 0x00200000L -#define CPC_RciuDebugBus_23_0__qMec1GrbmSendCnt1_neq_qMec1SendCntMax1_MASK 0x00400000L -#define CPC_RciuDebugBus_23_0__qMec1GrbmSendCnt2_neq_qMec1SendCntMax2_MASK 0x00800000L -#define CPC_RciuDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPC_RciuDebugBus_47_24 -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt3_neq_qMec1SendCntMax3_MASK 0x00000001L -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt0_eq_0_MASK 0x00000002L -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt1_eq_0_MASK 0x00000004L -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt2_eq_0_MASK 0x00000008L -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt3_eq_0_MASK 0x00000010L -#define CPC_RciuDebugBus_47_24__qMec1GrbmFree_3_0_MASK 0x000001e0L -#define CPC_RciuDebugBus_47_24__Mec1RciuRdReqFifoEmpty_3_0_MASK 0x00001e00L -#define CPC_RciuDebugBus_47_24__Mec1RciuRdReqFifoFull_3_0_MASK 0x0001e000L -#define CPC_RciuDebugBus_47_24__Mec2RciuFifoFull_3_0_MASK 0x001e0000L -#define CPC_RciuDebugBus_47_24__Mec2RciuFifoEmpty_2_0_MASK 0x00e00000L -#define CPC_RciuDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPC_RciuDebugBus_69_48 -#define CPC_RciuDebugBus_69_48__Mec2RciuFifoEmpty_3_MASK 0x00000001L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt0_neq_qMec2SendCntMax0_MASK 0x00000002L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt1_neq_qMec2SendCntMax1_MASK 0x00000004L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt2_neq_qMec2SendCntMax2_MASK 0x00000008L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt3_neq_qMec2SendCntMax3_MASK 0x00000010L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt0_eq_0_MASK 0x00000020L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt1_eq_0_MASK 0x00000040L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt2_eq_0_MASK 0x00000080L -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt3_eq_0_MASK 0x00000100L -#define CPC_RciuDebugBus_69_48__qMec2GrbmFree_3_0_MASK 0x00001e00L -#define CPC_RciuDebugBus_69_48__Mec2RciuRdReqFifoEmpty_3_0_MASK 0x0001e000L -#define CPC_RciuDebugBus_69_48__Mec2RciuRdReqFifoFull_3_0_MASK 0x001e0000L -#define CPC_RciuDebugBus_69_48__Reserved0_MASK 0xffe00000L - -// CPC_CpcRoqDebugBus_23_0 -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendPq_3_0_MASK 0x0000000fL -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendIb_3_0_MASK 0x000000f0L -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendIq_3_0_MASK 0x00000f00L -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendEop_3_0_MASK 0x0000f000L -#define CPC_CpcRoqDebugBus_23_0__Mec1_Pq_QueueFifoEmpty_3_0_MASK 0x000f0000L -#define CPC_CpcRoqDebugBus_23_0__Mec1_Pq_QueueFifoFull_3_0_MASK 0x00f00000L -#define CPC_CpcRoqDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPC_CpcRoqDebugBus_47_24 -#define CPC_CpcRoqDebugBus_47_24__Mec1_Ib_QueueFifoEmpty_3_0_MASK 0x0000000fL -#define CPC_CpcRoqDebugBus_47_24__Mec1_Ib_QueueFifoFull_3_0_MASK 0x000000f0L -#define CPC_CpcRoqDebugBus_47_24__Mec1_Iq_QueueFifoEmpty_3_0_MASK 0x00000f00L -#define CPC_CpcRoqDebugBus_47_24__Mec1_Iq_QueueFifoFull_3_0_MASK 0x0000f000L -#define CPC_CpcRoqDebugBus_47_24__Mec1_Eop_QueueFifoEmpty_3_0_MASK 0x000f0000L -#define CPC_CpcRoqDebugBus_47_24__Mec1_Eop_QueueFifoFull_3_0_MASK 0x00f00000L -#define CPC_CpcRoqDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPC_CpcRoqDebugBus_71_48 -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendPq_3_0_MASK 0x0000000fL -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendIb_3_0_MASK 0x000000f0L -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendIq_3_0_MASK 0x00000f00L -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendEop_3_0_MASK 0x0000f000L -#define CPC_CpcRoqDebugBus_71_48__Mec2_Pq_QueueFifoEmpty_3_0_MASK 0x000f0000L -#define CPC_CpcRoqDebugBus_71_48__Mec2_Pq_QueueFifoFull_3_0_MASK 0x00f00000L -#define CPC_CpcRoqDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPC_CpcRoqDebugBus_95_72 -#define CPC_CpcRoqDebugBus_95_72__Mec2_Ib_QueueFifoEmpty_3_0_MASK 0x0000000fL -#define CPC_CpcRoqDebugBus_95_72__Mec2_Ib_QueueFifoFull_3_0_MASK 0x000000f0L -#define CPC_CpcRoqDebugBus_95_72__Mec2_Iq_QueueFifoEmpty_3_0_MASK 0x00000f00L -#define CPC_CpcRoqDebugBus_95_72__Mec2_Iq_QueueFifoFull_3_0_MASK 0x0000f000L -#define CPC_CpcRoqDebugBus_95_72__Mec2_Eop_QueueFifoEmpty_3_0_MASK 0x000f0000L -#define CPC_CpcRoqDebugBus_95_72__Mec2_Eop_QueueFifoFull_3_0_MASK 0x00f00000L -#define CPC_CpcRoqDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPC_TciuDebugBus_12_0 -#define CPC_TciuDebugBus_12_0__qTcSender_MASK 0x0000000fL -#define CPC_TciuDebugBus_12_0__TcRequestFifoEmpty_MASK 0x00000010L -#define CPC_TciuDebugBus_12_0__TcRequestFifoFull_MASK 0x00000020L -#define CPC_TciuDebugBus_12_0__qCPC_CPG_tcreq_send_MASK 0x00000040L -#define CPC_TciuDebugBus_12_0__qCPC_CPG_tcreq_free_MASK 0x00000080L -#define CPC_TciuDebugBus_12_0__qCpcCpgSendCount_eq_0x8_MASK 0x00000100L -#define CPC_TciuDebugBus_12_0__qCpcCpgSendCount_eq_0_MASK 0x00000200L -#define CPC_TciuDebugBus_12_0__qTcReqCntUnderFlow_MASK 0x00000400L -#define CPC_TciuDebugBus_12_0__qTcReqCntOverFlow_MASK 0x00000800L -#define CPC_TciuDebugBus_12_0__qCPG_CPC_tcret_vld_MASK 0x00001000L -#define CPC_TciuDebugBus_12_0__Reserved0_MASK 0xffffe000L - -// CPC_Dynamic_and_Register_Clk_Valid -#define CPC_Dynamic_and_Register_Clk_Valid__RegisterClkValid_MASK 0x00000001L -#define CPC_Dynamic_and_Register_Clk_Valid__DynamicClkValid_MASK 0x00000002L -#define CPC_Dynamic_and_Register_Clk_Valid__Reserved0_MASK 0xfffffffcL - -// CPC_MecParserDebugBus_23_0 -#define CPC_MecParserDebugBus_23_0__qEnableDiscardType2_MASK 0x00000001L -#define CPC_MecParserDebugBus_23_0__MecMsgFifoEmpty_MASK 0x00000002L -#define CPC_MecParserDebugBus_23_0__MecMsgFifoFull_MASK 0x00000004L -#define CPC_MecParserDebugBus_23_0__QueueManagerQueueId_MASK 0x00000038L -#define CPC_MecParserDebugBus_23_0__QueueManagerMessage_MASK 0x00003fc0L -#define CPC_MecParserDebugBus_23_0__QueManagerFifoEmpty_MASK 0x00004000L -#define CPC_MecParserDebugBus_23_0__qBlockSwitch_MASK 0x00038000L -#define CPC_MecParserDebugBus_23_0__qMessageDwordRts_MASK 0x00040000L -#define CPC_MecParserDebugBus_23_0__qEopQueueDwordRts_MASK 0x00080000L -#define CPC_MecParserDebugBus_23_0__qIqQueueDwordRts_MASK 0x00100000L -#define CPC_MecParserDebugBus_23_0__qPcktCntPqEq0_MASK 0x00200000L -#define CPC_MecParserDebugBus_23_0__qPcktCntIbEq0_MASK 0x00400000L -#define CPC_MecParserDebugBus_23_0__qPcktCntIqEq0_MASK 0x00800000L -#define CPC_MecParserDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPC_MecParserDebugBus_47_24 -#define CPC_MecParserDebugBus_47_24__qPcktCntEopEq0_MASK 0x00000001L -#define CPC_MecParserDebugBus_47_24__qPcktCntEq0_MASK 0x00000002L -#define CPC_MecParserDebugBus_47_24__qReservedBitClean_MASK 0x00000004L -#define CPC_MecParserDebugBus_47_24__qReservedBitDirty_MASK 0x00000008L -#define CPC_MecParserDebugBus_47_24__qIndrBufCntNeq0_MASK 0x00000010L -#define CPC_MecParserDebugBus_47_24__qIbEndState_MASK 0x00000060L -#define CPC_MecParserDebugBus_47_24__IqSizeFifoEmpty_MASK 0x00000080L -#define CPC_MecParserDebugBus_47_24__IqSizeFifoFull_MASK 0x00000100L -#define CPC_MecParserDebugBus_47_24__qIqBufCntNeq0_MASK 0x00000200L -#define CPC_MecParserDebugBus_47_24__qIqQueueId_MASK 0x00001c00L -#define CPC_MecParserDebugBus_47_24__qIqEndState_MASK 0x00006000L -#define CPC_MecParserDebugBus_47_24__qPrgmStrmSelect_MASK 0x00038000L -#define CPC_MecParserDebugBus_47_24__qEopReturnStream_3_0_MASK 0x003c0000L -#define CPC_MecParserDebugBus_47_24__qIqReturnStream_1_0_MASK 0x00c00000L -#define CPC_MecParserDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPC_MecParserDebugBus_71_48 -#define CPC_MecParserDebugBus_71_48__qIqReturnStream_3_2_MASK 0x00000003L -#define CPC_MecParserDebugBus_71_48__qRegBusSelect_MASK 0x0000003cL -#define CPC_MecParserDebugBus_71_48__qMecVqid_MASK 0x0000ffc0L -#define CPC_MecParserDebugBus_71_48__qMecVqEn_MASK 0x00010000L -#define CPC_MecParserDebugBus_71_48__qMecSrcVm_MASK 0x00060000L -#define CPC_MecParserDebugBus_71_48__MecDcFifoEmpty_MASK 0x00080000L -#define CPC_MecParserDebugBus_71_48__MecDcFifoFull_MASK 0x00100000L -#define CPC_MecParserDebugBus_71_48__oMecHqdWrRts_MASK 0x00200000L -#define CPC_MecParserDebugBus_71_48__MecRciuFifoEmpty_MASK 0x00400000L -#define CPC_MecParserDebugBus_71_48__MecRciuFifoFull_MASK 0x00800000L -#define CPC_MecParserDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPC_MecParserDebugBus_95_72 -#define CPC_MecParserDebugBus_95_72__qUpdateWrAddr_MASK 0x00000001L -#define CPC_MecParserDebugBus_95_72__qMecWrOneAddr_MASK 0x00000002L -#define CPC_MecParserDebugBus_95_72__Reserved2_MASK 0x0000000cL -#define CPC_MecParserDebugBus_95_72__qPrivilegedStatePq_MASK 0x00000010L -#define CPC_MecParserDebugBus_95_72__qQueueId_MASK 0x000000e0L -#define CPC_MecParserDebugBus_95_72__qBlockCsmdRdPntrUpdate_MASK 0x00000100L -#define CPC_MecParserDebugBus_95_72__qBlockCsmdRdPntrRead_MASK 0x00000200L -#define CPC_MecParserDebugBus_95_72__qIbDrainCount_neq_0_MASK 0x00000400L -#define CPC_MecParserDebugBus_95_72__qPqDrainCount_neq_0_MASK 0x00000800L -#define CPC_MecParserDebugBus_95_72__oMecDcDiscardReq_MASK 0x00001000L -#define CPC_MecParserDebugBus_95_72__oMecDcHaltReq_MASK 0x00002000L -#define CPC_MecParserDebugBus_95_72__qPendingEopqWpFlag_Dse0_MASK 0x00004000L -#define CPC_MecParserDebugBus_95_72__oEopqWrPntrRts_MASK 0x00008000L -#define CPC_MecParserDebugBus_95_72__Reserved1_MASK 0x00010000L -#define CPC_MecParserDebugBus_95_72__qMecDmaPendingQueue_MASK 0x000e0000L -#define CPC_MecParserDebugBus_95_72__qMecDmaPendingFlag_MASK 0x00100000L -#define CPC_MecParserDebugBus_95_72__PartialFlushPendingQ0_MASK 0x00200000L -#define CPC_MecParserDebugBus_95_72__oDoorbellRts_MASK 0x00400000L -#define CPC_MecParserDebugBus_95_72__CpTcTxActionDebugBus_0_MASK 0x00800000L -#define CPC_MecParserDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPC_MecParserDebugBus_119_96 -#define CPC_MecParserDebugBus_119_96__CpTcTxActionDebugBus_3_1_MASK 0x00000007L -#define CPC_MecParserDebugBus_119_96__Reserved0_MASK 0xfffffff8L - -// CPC_F32MecDebugBus_23_0 -#define CPC_F32MecDebugBus_23_0__LdStrBufferData_23_0_MASK 0x00ffffffL -#define CPC_F32MecDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_47_24 -#define CPC_F32MecDebugBus_47_24__LdStrBufferData_47_24_MASK 0x00ffffffL -#define CPC_F32MecDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_71_48 -#define CPC_F32MecDebugBus_71_48__LdStrBufferData_63_48_MASK 0x0000ffffL -#define CPC_F32MecDebugBus_71_48__LdStrBufferAddress_7_0_MASK 0x00ff0000L -#define CPC_F32MecDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_95_72 -#define CPC_F32MecDebugBus_95_72__LdStrBufferAddress_31_8_MASK 0x00ffffffL -#define CPC_F32MecDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_119_96 -#define CPC_F32MecDebugBus_119_96__LdStrBufferAddress_47_32_MASK 0x0000ffffL -#define CPC_F32MecDebugBus_119_96__LdStrBufferInstrOp_MASK 0x00010000L -#define CPC_F32MecDebugBus_119_96__LdStrInstrSel_MASK 0x00060000L -#define CPC_F32MecDebugBus_119_96__LdStrMemSpace_MASK 0x00180000L -#define CPC_F32MecDebugBus_119_96__qLoadStoreBusy_MASK 0x00200000L -#define CPC_F32MecDebugBus_119_96__Reserved1_MASK 0x00400000L -#define CPC_F32MecDebugBus_119_96__qLoadState_B_0_MASK 0x00800000L -#define CPC_F32MecDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_143_120 -#define CPC_F32MecDebugBus_143_120__qLoadState_B_1_MASK 0x00000001L -#define CPC_F32MecDebugBus_143_120__qLoadState_A_MASK 0x00000006L -#define CPC_F32MecDebugBus_143_120__LdStrBufferEmpty_MASK 0x00000008L -#define CPC_F32MecDebugBus_143_120__LdStrBufferFull_MASK 0x00000010L -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc2Valid_B_MASK 0x00000020L -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc1Valid_B_MASK 0x00000040L -#define CPC_F32MecDebugBus_143_120__qInstrMeValid_B_MASK 0x00000080L -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc2Valid_A_MASK 0x00000100L -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc1Valid_A_MASK 0x00000200L -#define CPC_F32MecDebugBus_143_120__qInstrMeValid_A_MASK 0x00000400L -#define CPC_F32MecDebugBus_143_120__Reserved0_MASK 0xfffff800L - -// CPC_F32MecDebugBus_167_144 -#define CPC_F32MecDebugBus_167_144__Reserved1_MASK 0x0000ffffL -#define CPC_F32MecDebugBus_167_144__qLoadArbState_MASK 0x00030000L -#define CPC_F32MecDebugBus_167_144__qStoreArbState_MASK 0x000c0000L -#define CPC_F32MecDebugBus_167_144__Reserved0_MASK 0xfff00000L - -// CPC_F32MecDebugBus_191_168 -#define CPC_F32MecDebugBus_191_168__Reserved0_MASK 0xffffffffL - -// CPC_F32MecDebugBus_215_192 -#define CPC_F32MecDebugBus_215_192__qAluArbState_B_MASK 0x00000003L -#define CPC_F32MecDebugBus_215_192__qAluArbState_A_MASK 0x0000000cL -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B_MASK 0x00000010L -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B_MASK 0x00000020L -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExValid_B_MASK 0x00000040L -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A_MASK 0x00000080L -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A_MASK 0x00000100L -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExValid_A_MASK 0x00000200L -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B_MASK 0x00000400L -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B_MASK 0x00000800L -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExValid_B_MASK 0x00001000L -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A_MASK 0x00002000L -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A_MASK 0x00004000L -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExValid_A_MASK 0x00008000L -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B_MASK 0x00010000L -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B_MASK 0x00020000L -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExValid_B_MASK 0x00040000L -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A_MASK 0x00080000L -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A_MASK 0x00100000L -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExValid_A_MASK 0x00200000L -#define CPC_F32MecDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B_MASK 0x00400000L -#define CPC_F32MecDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B_MASK 0x00800000L -#define CPC_F32MecDebugBus_215_192__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_239_216 -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExValid_B_MASK 0x00000001L -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A_MASK 0x00000002L -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A_MASK 0x00000004L -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExValid_A_MASK 0x00000008L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid15_MASK 0x00000010L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid14_MASK 0x00000020L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid13_MASK 0x00000040L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid12_MASK 0x00000080L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid11_MASK 0x00000100L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid10_MASK 0x00000200L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid9_MASK 0x00000400L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid8_MASK 0x00000800L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid7_MASK 0x00001000L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid6_MASK 0x00002000L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid5_MASK 0x00004000L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid4_MASK 0x00008000L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid3_MASK 0x00010000L -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid2_MASK 0x00020000L -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid15_MASK 0x00040000L -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid14_MASK 0x00080000L -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid13_MASK 0x00100000L -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid12_MASK 0x00200000L -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid11_MASK 0x00400000L -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid10_MASK 0x00800000L -#define CPC_F32MecDebugBus_239_216__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_263_240 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid9_MASK 0x00000001L -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid8_MASK 0x00000002L -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid7_MASK 0x00000004L -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid6_MASK 0x00000008L -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid5_MASK 0x00000010L -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid4_MASK 0x00000020L -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid3_MASK 0x00000040L -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid2_MASK 0x00000080L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid15_MASK 0x00000100L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid14_MASK 0x00000200L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid13_MASK 0x00000400L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid12_MASK 0x00000800L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid11_MASK 0x00001000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid10_MASK 0x00002000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid9_MASK 0x00004000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid8_MASK 0x00008000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid7_MASK 0x00010000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid6_MASK 0x00020000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid5_MASK 0x00040000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid4_MASK 0x00080000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid3_MASK 0x00100000L -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid2_MASK 0x00200000L -#define CPC_F32MecDebugBus_263_240__DebugBus3_qGprValid15_MASK 0x00400000L -#define CPC_F32MecDebugBus_263_240__DebugBus3_qGprValid14_MASK 0x00800000L -#define CPC_F32MecDebugBus_263_240__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_287_264 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid13_MASK 0x00000001L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid12_MASK 0x00000002L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid11_MASK 0x00000004L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid10_MASK 0x00000008L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid9_MASK 0x00000010L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid8_MASK 0x00000020L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid7_MASK 0x00000040L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid6_MASK 0x00000080L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid5_MASK 0x00000100L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid4_MASK 0x00000200L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid3_MASK 0x00000400L -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid2_MASK 0x00000800L -#define CPC_F32MecDebugBus_287_264__qDecodeInstr_A_11_0_MASK 0x00fff000L -#define CPC_F32MecDebugBus_287_264__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_311_288 -#define CPC_F32MecDebugBus_311_288__qDecodeInstr_A_31_12_MASK 0x000fffffL -#define CPC_F32MecDebugBus_311_288__qDecodeInstr_B_3_0_MASK 0x00f00000L -#define CPC_F32MecDebugBus_311_288__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_335_312 -#define CPC_F32MecDebugBus_335_312__qDecodeInstr_B_27_4_MASK 0x00ffffffL -#define CPC_F32MecDebugBus_335_312__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_359_336 -#define CPC_F32MecDebugBus_359_336__qDecodeInstr_B_31_28_MASK 0x0000000fL -#define CPC_F32MecDebugBus_359_336__qDecodeAddress_A_padded_MASK 0x000ffff0L -#define CPC_F32MecDebugBus_359_336__qDecodeAddress_B_padded_3_0_MASK 0x00f00000L -#define CPC_F32MecDebugBus_359_336__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_383_360 -#define CPC_F32MecDebugBus_383_360__qDecodeAddress_B_padded_15_4_MASK 0x00000fffL -#define CPC_F32MecDebugBus_383_360__qAluIntUnitPntr_A_MASK 0x00007000L -#define CPC_F32MecDebugBus_383_360__AluIntUnitPntr_B_MASK 0x00038000L -#define CPC_F32MecDebugBus_383_360__qLdStrUnitPntr_A_MASK 0x001c0000L -#define CPC_F32MecDebugBus_383_360__qLdStrUnitPntr_B_MASK 0x00e00000L -#define CPC_F32MecDebugBus_383_360__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_407_384 -#define CPC_F32MecDebugBus_407_384__qDecodeInstrRts_A_MASK 0x00000001L -#define CPC_F32MecDebugBus_407_384__qDecodeInstrRts_B_MASK 0x00000002L -#define CPC_F32MecDebugBus_407_384__qJumpSourceRts_MASK 0x00000004L -#define CPC_F32MecDebugBus_407_384__qInstrEtsCnt_le_6_MASK 0x00000008L -#define CPC_F32MecDebugBus_407_384__Reserved1_MASK 0x000ffff0L -#define CPC_F32MecDebugBus_407_384__qThreadIdState_MASK 0x00f00000L -#define CPC_F32MecDebugBus_407_384__Reserved0_MASK 0xff000000L - -// CPC_F32MecDebugBus_431_408 -#define CPC_F32MecDebugBus_431_408__Reserved0_MASK 0xffffffffL - -// CPC_F32MecDebugBus_447_432 -#define CPC_F32MecDebugBus_447_432__Reserved0_MASK 0xffffffffL - -// CPC_UtcL2iuDebugIntf_23_0 -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_tag_MASK 0x0000007fL -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_nack_MASK 0x00000180L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_mtype_MASK 0x00000600L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_memlog_MASK 0x00000800L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_no_pte_MASK 0x00001000L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_pte_tmz_MASK 0x00002000L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_spa_MASK 0x00004000L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_io_steer_MASK 0x00008000L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_fragment_size_5_0_MASK 0x003f0000L -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_perms_granted_1_0_MASK 0x00c00000L -#define CPC_UtcL2iuDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPC_UtcL2iuDebugIntf_47_24 -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_perms_granted_2_MASK 0x00000001L -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_perms_requested_2_0_MASK 0x0000000eL -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_snoop_MASK 0x00000010L -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_valid_MASK 0x00000020L -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_perms_requested_17_0_MASK 0x00ffffc0L -#define CPC_UtcL2iuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPC_UtcL2iuDebugIntf_71_48 -#define CPC_UtcL2iuDebugIntf_71_48__iUTCL2_CPC_ret_perms_requested_35_18_MASK 0x0003ffffL -#define CPC_UtcL2iuDebugIntf_71_48__CPC_UTCL2_req_data_5_0_MASK 0x00fc0000L -#define CPC_UtcL2iuDebugIntf_71_48__Reserved0_MASK 0xff000000L - -// CPC_UtcL2iuDebugIntf_95_72 -#define CPC_UtcL2iuDebugIntf_95_72__CPC_UTCL2_req_data_15_6_MASK 0x000003ffL -#define CPC_UtcL2iuDebugIntf_95_72__qCPC_UTCL2_req_free_MASK 0x00000400L -#define CPC_UtcL2iuDebugIntf_95_72__CPC_UTCL2_req_send_MASK 0x00000800L -#define CPC_UtcL2iuDebugIntf_95_72__qUtcL2XferCycle_eq_0_MASK 0x00001000L -#define CPC_UtcL2iuDebugIntf_95_72__Reserved0_MASK 0xffffe000L - -// CPG_RbiuDebugIntf_23_0 -#define CPG_RbiuDebugIntf_23_0__GRBM_CP_reg_free_MASK 0x00000001L -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_send_MASK 0x00000002L -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_clken_MASK 0x00000004L -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_priv_MASK 0x00000008L -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_op_MASK 0x00000010L -#define CPG_RbiuDebugIntf_23_0__RdReturnValid_MASK 0x00000020L -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_addr_MASK 0x003fffc0L -#define CPG_RbiuDebugIntf_23_0__Reserved0_MASK 0xffc00000L - -// CPG_RbiuDebugIntf_47_24 -#define CPG_RbiuDebugIntf_47_24__iGRBM_CP_reg_data_11_0_MASK 0x00000fffL -#define CPG_RbiuDebugIntf_47_24__RdReturnData_11_0_MASK 0x00fff000L -#define CPG_RbiuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPG_RciuDebugIntf_23_0 -#define CPG_RciuDebugIntf_23_0__GRBM_CP_reg_free_MASK 0x00000001L -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_send_MASK 0x00000002L -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_clken_MASK 0x00000004L -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_priv_MASK 0x00000008L -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_op_MASK 0x00000010L -#define CPG_RciuDebugIntf_23_0__RdReturnValid_MASK 0x00000020L -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_addr_MASK 0x003fffc0L -#define CPG_RciuDebugIntf_23_0__Reserved0_MASK 0xffc00000L - -// CPG_RciuDebugIntf_47_24 -#define CPG_RciuDebugIntf_47_24__iGRBM_CP_reg_data_11_0_MASK 0x00000fffL -#define CPG_RciuDebugIntf_47_24__RdReturnData_11_0_MASK 0x00fff000L -#define CPG_RciuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPG_SurfSyncDebugIntf -#define CPG_SurfSyncDebugIntf__Reserved2_MASK 0x00000007L -#define CPG_SurfSyncDebugIntf__StartClient2_MASK 0x00000008L -#define CPG_SurfSyncDebugIntf__StartClient1_MASK 0x00000010L -#define CPG_SurfSyncDebugIntf__StartClient0_MASK 0x00000020L -#define CPG_SurfSyncDebugIntf__Reserved1_MASK 0x000001c0L -#define CPG_SurfSyncDebugIntf__CleanClient2_MASK 0x00000200L -#define CPG_SurfSyncDebugIntf__CleanClient1_MASK 0x00000400L -#define CPG_SurfSyncDebugIntf__CleanClient0_MASK 0x00000800L -#define CPG_SurfSyncDebugIntf__Reserved0_MASK 0xfffff000L - -// CPG_PfpParserDebugIntf_23_0 -#define CPG_PfpParserDebugIntf_23_0__qPrgmStrmXfc_MASK 0x00000001L -#define CPG_PfpParserDebugIntf_23_0__qPrgmStrmRts_MASK 0x00000002L -#define CPG_PfpParserDebugIntf_23_0__qPrgmStrmData_21_0_MASK 0x00fffffcL -#define CPG_PfpParserDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPG_PfpParserDebugIntf_47_24 -#define CPG_PfpParserDebugIntf_47_24__qPrgmStrmData_31_22_MASK 0x000003ffL -#define CPG_PfpParserDebugIntf_47_24__Reserved1_MASK 0x00000c00L -#define CPG_PfpParserDebugIntf_47_24__StoreRtr_R0_MASK 0x00001000L -#define CPG_PfpParserDebugIntf_47_24__StoreRts_MASK 0x00002000L -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceGlobal_MASK 0x00004000L -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceMemory_MASK 0x00008000L -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceMmReg_MASK 0x00010000L -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceLocal_MASK 0x00020000L -#define CPG_PfpParserDebugIntf_47_24__StoreData_5_0_MASK 0x00fc0000L -#define CPG_PfpParserDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPG_PfpParserDebugIntf_71_48 -#define CPG_PfpParserDebugIntf_71_48__StoreData_29_6_MASK 0x00ffffffL -#define CPG_PfpParserDebugIntf_71_48__Reserved0_MASK 0xff000000L - -// CPG_PfpParserDebugIntf_95_72 -#define CPG_PfpParserDebugIntf_95_72__StoreData_31_30_MASK 0x00000003L -#define CPG_PfpParserDebugIntf_95_72__qStoreAddr_21_0_MASK 0x00fffffcL -#define CPG_PfpParserDebugIntf_95_72__Reserved0_MASK 0xff000000L - -// CPG_PfpParserDebugIntf_119_96 -#define CPG_PfpParserDebugIntf_119_96__qStoreAddr_45_22_MASK 0x00ffffffL -#define CPG_PfpParserDebugIntf_119_96__Reserved0_MASK 0xff000000L - -// CPG_PfpParserDebugIntf_143_120 -#define CPG_PfpParserDebugIntf_143_120__qStoreAddr_47_46_MASK 0x00000003L -#define CPG_PfpParserDebugIntf_143_120__Reserved0_MASK 0xfffffffcL - -// CPG_MeParserDebugIntf_23_0 -#define CPG_MeParserDebugIntf_23_0__StoreRts_MASK 0x00000001L -#define CPG_MeParserDebugIntf_23_0__StMemSpaceGlobal_MASK 0x00000002L -#define CPG_MeParserDebugIntf_23_0__StMemSpaceMemory_MASK 0x00000004L -#define CPG_MeParserDebugIntf_23_0__StMemSpaceMmReg_MASK 0x00000008L -#define CPG_MeParserDebugIntf_23_0__StMemSpaceLocal_MASK 0x00000010L -#define CPG_MeParserDebugIntf_23_0__Reserved0_MASK 0xffffffe0L - -// CPG_MeParserDebugIntf_47_24 -#define CPG_MeParserDebugIntf_47_24__Reserved0_MASK 0xffffffffL - -// CPG_MeParserDebugIntf_71_48 -#define CPG_MeParserDebugIntf_71_48__Reserved0_MASK 0xffffffffL - -// CPG_MeParserDebugIntf_95_72 -#define CPG_MeParserDebugIntf_95_72__Reserved1_MASK 0x00001fffL -#define CPG_MeParserDebugIntf_95_72__qSPI0_CP_cs_done_MASK 0x00002000L -#define CPG_MeParserDebugIntf_95_72__qSPI0_CP_ps_done_R0_MASK 0x00004000L -#define CPG_MeParserDebugIntf_95_72__qSPI0_CP_partial0_flush_MASK 0x00008000L -#define CPG_MeParserDebugIntf_95_72__qSPI1_CP_cs_done_MASK 0x00010000L -#define CPG_MeParserDebugIntf_95_72__qSPI1_CP_ps_done_R0_MASK 0x00020000L -#define CPG_MeParserDebugIntf_95_72__qSPI1_CP_partial0_flush_MASK 0x00040000L -#define CPG_MeParserDebugIntf_95_72__qSPI2_CP_cs_done_MASK 0x00080000L -#define CPG_MeParserDebugIntf_95_72__qSPI2_CP_ps_done_R0_MASK 0x00100000L -#define CPG_MeParserDebugIntf_95_72__qSPI2_CP_partial0_flush_MASK 0x00200000L -#define CPG_MeParserDebugIntf_95_72__qSPI3_CP_cs_done_MASK 0x00400000L -#define CPG_MeParserDebugIntf_95_72__qSPI3_CP_ps_done_R0_MASK 0x00800000L -#define CPG_MeParserDebugIntf_95_72__Reserved0_MASK 0xff000000L - -// CPG_MeParserDebugIntf_119_96 -#define CPG_MeParserDebugIntf_119_96__qSPI3_CP_partial0_flush_MASK 0x00000001L -#define CPG_MeParserDebugIntf_119_96__Reserved0_MASK 0xfffffffeL - -// CPG_QueryUnitDebugIntf_23_0 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_sample_MASK 0x00000001L -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_incr_MASK 0x0000003eL -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_pipeid_MASK 0x00000040L -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_valid_MASK 0x00000080L -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_sample_MASK 0x00000100L -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_incr_MASK 0x00003e00L -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_pipeid_MASK 0x00004000L -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_valid_MASK 0x00008000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_sample_MASK 0x00010000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_incr_MASK 0x00020000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_pipeid_MASK 0x00040000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_valid_MASK 0x00080000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_sample_MASK 0x00100000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_incr_MASK 0x00200000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_pipeid_MASK 0x00400000L -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_valid_MASK 0x00800000L -#define CPG_QueryUnitDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPG_QueryUnitDebugIntf_47_24 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_sample_MASK 0x00000001L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_incr_MASK 0x00000002L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_pipeid_MASK 0x00000004L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_valid_MASK 0x00000008L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_sample_MASK 0x00000010L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_incr_MASK 0x000001e0L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_pipeid_MASK 0x00000200L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_valid_MASK 0x00000400L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_sample_MASK 0x00000800L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_incr_MASK 0x00001000L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_pipeid_MASK 0x00002000L -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_valid_MASK 0x00004000L -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iaprim_sample_MASK 0x00008000L -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iaprim_incr_MASK 0x00030000L -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iaprim_valid_MASK 0x00040000L -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iavert_sample_MASK 0x00080000L -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iavert_incr_MASK 0x00f00000L -#define CPG_QueryUnitDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPG_QueryUnitDebugIntf_71_48 -#define CPG_QueryUnitDebugIntf_71_48__qIA0_CP_iavert_valid_MASK 0x00000001L -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_flushed_MASK 0x00000002L -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_sample_MASK 0x00000004L -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_incr1_neq_0_MASK 0x00000008L -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_incr0_neq_0_MASK 0x00000010L -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_pipeid_MASK 0x00000020L -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_id_MASK 0x000000c0L -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_valid_MASK 0x00000100L -#define CPG_QueryUnitDebugIntf_71_48__qSE0SC_CP_eop1_done_MASK 0x00000200L -#define CPG_QueryUnitDebugIntf_71_48__qSE0SC_CP_eop0_done_MASK 0x00000400L -#define CPG_QueryUnitDebugIntf_71_48__qEopdOutstandingTagCnt_R1_neq_0_MASK 0x00000800L -#define CPG_QueryUnitDebugIntf_71_48__qEopdOutstandingTagCnt_R0_neq_0_MASK 0x00001000L -#define CPG_QueryUnitDebugIntf_71_48__qStrmOutstandingTagCnt_R1_neq_0_MASK 0x00002000L -#define CPG_QueryUnitDebugIntf_71_48__qStrmOutstandingTagCnt_R0_neq_0_MASK 0x00004000L -#define CPG_QueryUnitDebugIntf_71_48__qPipeOutstandingTagCnt_R1_neq_0_MASK 0x00008000L -#define CPG_QueryUnitDebugIntf_71_48__qPipeOutstandingTagCnt_R0_neq_0_MASK 0x00010000L -#define CPG_QueryUnitDebugIntf_71_48__Reserved0_MASK 0xfffe0000L - -// CPG_Clk_Valid -#define CPG_Clk_Valid__RegisterClkValid_MASK 0x00000001L -#define CPG_Clk_Valid__DynamicClkValid_MASK 0x00000002L -#define CPG_Clk_Valid__Reserved0_MASK 0xfffffffcL - -// CPG_DcDebugIntf0 -#define CPG_DcDebugIntf0__gd_valid_MASK 0x00000001L -#define CPG_DcDebugIntf0__gd_data_type_MASK 0x00000006L -#define CPG_DcDebugIntf0__gd_addr_MASK 0x000003f8L -#define CPG_DcDebugIntf0__gd_data_13_0_MASK 0x00fffc00L -#define CPG_DcDebugIntf0__Reserved0_MASK 0xff000000L - -// CPG_DcDebugIntf1 -#define CPG_DcDebugIntf1__gd_valid_MASK 0x00000001L -#define CPG_DcDebugIntf1__gd_data_31_14_MASK 0x0007fffeL -#define CPG_DcDebugIntf1__Reserved0_MASK 0xfff80000L - -// CPG_DcDebugIntf2 -#define CPG_DcDebugIntf2__valid_q0_MASK 0x00000001L -#define CPG_DcDebugIntf2__state_q_MASK 0x0000001eL -#define CPG_DcDebugIntf2__steering_state_q_MASK 0x000000e0L -#define CPG_DcDebugIntf2__first_thread_group_q0_MASK 0x00000100L -#define CPG_DcDebugIntf2__last_thread_group_q0_MASK 0x00000200L -#define CPG_DcDebugIntf2__kill_dispatch_mode0_MASK 0x00000400L -#define CPG_DcDebugIntf2__kill_dispatch_mode1_MASK 0x00000800L -#define CPG_DcDebugIntf2__gd_stall_MASK 0x00001000L -#define CPG_DcDebugIntf2__disp_stall_q_MASK 0x00002000L -#define CPG_DcDebugIntf2__no_serializer_is_busy_MASK 0x00004000L -#define CPG_DcDebugIntf2__gd_dispatch_busy_MASK 0x00008000L -#define CPG_DcDebugIntf2__gd_busy_MASK 0x00010000L -#define CPG_DcDebugIntf2__num_se_with_cu_active_MASK 0x000e0000L -#define CPG_DcDebugIntf2__send_num_threads_x_q_MASK 0x00100000L -#define CPG_DcDebugIntf2__send_num_threads_y_q_MASK 0x00200000L -#define CPG_DcDebugIntf2__send_num_threads_z_q_MASK 0x00400000L -#define CPG_DcDebugIntf2__Reserved0_MASK 0xff800000L - -// CPG_DcDebugIntf3 -#define CPG_DcDebugIntf3__gddata_send_MASK 0x00000001L -#define CPG_DcDebugIntf3__gddata_data_type_MASK 0x00000006L -#define CPG_DcDebugIntf3__data_x_q1_MASK 0x00fffff8L -#define CPG_DcDebugIntf3__Reserved0_MASK 0xff000000L - -// CPG_DcDebugIntf4 -#define CPG_DcDebugIntf4__data_y_q1_MASK 0x00000fffL -#define CPG_DcDebugIntf4__data_z_q1_MASK 0x00fff000L -#define CPG_DcDebugIntf4__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_23_0 -#define CPG_F32CeDebugBus_23_0__LdStrBufferData_23_0_MASK 0x00ffffffL -#define CPG_F32CeDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_47_24 -#define CPG_F32CeDebugBus_47_24__LdStrBufferData_47_24_MASK 0x00ffffffL -#define CPG_F32CeDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_71_48 -#define CPG_F32CeDebugBus_71_48__LdStrBufferData_63_48_MASK 0x0000ffffL -#define CPG_F32CeDebugBus_71_48__LdStrBufferAddress_7_0_MASK 0x00ff0000L -#define CPG_F32CeDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_95_72 -#define CPG_F32CeDebugBus_95_72__LdStrBufferAddress_31_8_MASK 0x00ffffffL -#define CPG_F32CeDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_119_96 -#define CPG_F32CeDebugBus_119_96__LdStrBufferAddress_47_32_MASK 0x0000ffffL -#define CPG_F32CeDebugBus_119_96__LdStrBufferInstrOp_MASK 0x00010000L -#define CPG_F32CeDebugBus_119_96__LdStrInstrSel_MASK 0x00060000L -#define CPG_F32CeDebugBus_119_96__LdStrMemSpace_MASK 0x00180000L -#define CPG_F32CeDebugBus_119_96__qLoadStoreBusy_MASK 0x00200000L -#define CPG_F32CeDebugBus_119_96__Reserved1_MASK 0x00400000L -#define CPG_F32CeDebugBus_119_96__qLoadState_B_0_MASK 0x00800000L -#define CPG_F32CeDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_143_120 -#define CPG_F32CeDebugBus_143_120__qLoadState_B_1_MASK 0x00000001L -#define CPG_F32CeDebugBus_143_120__qLoadState_A_MASK 0x00000006L -#define CPG_F32CeDebugBus_143_120__LdStrBufferEmpty_MASK 0x00000008L -#define CPG_F32CeDebugBus_143_120__LdStrBufferFull_MASK 0x00000010L -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc2Valid_B_MASK 0x00000020L -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc1Valid_B_MASK 0x00000040L -#define CPG_F32CeDebugBus_143_120__qInstrMeValid_B_MASK 0x00000080L -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc2Valid_A_MASK 0x00000100L -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc1Valid_A_MASK 0x00000200L -#define CPG_F32CeDebugBus_143_120__qInstrMeValid_A_MASK 0x00000400L -#define CPG_F32CeDebugBus_143_120__Reserved0_MASK 0xfffff800L - -// CPG_F32CeDebugBus_167_144 -#define CPG_F32CeDebugBus_167_144__Reserved1_MASK 0x0000ffffL -#define CPG_F32CeDebugBus_167_144__qLoadArbState_MASK 0x00030000L -#define CPG_F32CeDebugBus_167_144__qStoreArbState_MASK 0x000c0000L -#define CPG_F32CeDebugBus_167_144__Reserved0_MASK 0xfff00000L - -// CPG_F32CeDebugBus_191_168 -#define CPG_F32CeDebugBus_191_168__Reserved0_MASK 0xffffffffL - -// CPG_F32CeDebugBus_215_192 -#define CPG_F32CeDebugBus_215_192__qAluArbState_B_MASK 0x00000003L -#define CPG_F32CeDebugBus_215_192__qAluArbState_A_MASK 0x0000000cL -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B_MASK 0x00000010L -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B_MASK 0x00000020L -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExValid_B_MASK 0x00000040L -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A_MASK 0x00000080L -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A_MASK 0x00000100L -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExValid_A_MASK 0x00000200L -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B_MASK 0x00000400L -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B_MASK 0x00000800L -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExValid_B_MASK 0x00001000L -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A_MASK 0x00002000L -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A_MASK 0x00004000L -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExValid_A_MASK 0x00008000L -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B_MASK 0x00010000L -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B_MASK 0x00020000L -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExValid_B_MASK 0x00040000L -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A_MASK 0x00080000L -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A_MASK 0x00100000L -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExValid_A_MASK 0x00200000L -#define CPG_F32CeDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B_MASK 0x00400000L -#define CPG_F32CeDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B_MASK 0x00800000L -#define CPG_F32CeDebugBus_215_192__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_239_216 -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExValid_B_MASK 0x00000001L -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A_MASK 0x00000002L -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A_MASK 0x00000004L -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExValid_A_MASK 0x00000008L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid15_MASK 0x00000010L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid14_MASK 0x00000020L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid13_MASK 0x00000040L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid12_MASK 0x00000080L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid11_MASK 0x00000100L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid10_MASK 0x00000200L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid9_MASK 0x00000400L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid8_MASK 0x00000800L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid7_MASK 0x00001000L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid6_MASK 0x00002000L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid5_MASK 0x00004000L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid4_MASK 0x00008000L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid3_MASK 0x00010000L -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid2_MASK 0x00020000L -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid15_MASK 0x00040000L -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid14_MASK 0x00080000L -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid13_MASK 0x00100000L -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid12_MASK 0x00200000L -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid11_MASK 0x00400000L -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid10_MASK 0x00800000L -#define CPG_F32CeDebugBus_239_216__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_263_240 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid9_MASK 0x00000001L -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid8_MASK 0x00000002L -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid7_MASK 0x00000004L -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid6_MASK 0x00000008L -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid5_MASK 0x00000010L -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid4_MASK 0x00000020L -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid3_MASK 0x00000040L -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid2_MASK 0x00000080L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid15_MASK 0x00000100L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid14_MASK 0x00000200L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid13_MASK 0x00000400L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid12_MASK 0x00000800L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid11_MASK 0x00001000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid10_MASK 0x00002000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid9_MASK 0x00004000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid8_MASK 0x00008000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid7_MASK 0x00010000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid6_MASK 0x00020000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid5_MASK 0x00040000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid4_MASK 0x00080000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid3_MASK 0x00100000L -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid2_MASK 0x00200000L -#define CPG_F32CeDebugBus_263_240__DebugBus3_qGprValid15_MASK 0x00400000L -#define CPG_F32CeDebugBus_263_240__DebugBus3_qGprValid14_MASK 0x00800000L -#define CPG_F32CeDebugBus_263_240__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_287_264 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid13_MASK 0x00000001L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid12_MASK 0x00000002L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid11_MASK 0x00000004L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid10_MASK 0x00000008L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid9_MASK 0x00000010L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid8_MASK 0x00000020L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid7_MASK 0x00000040L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid6_MASK 0x00000080L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid5_MASK 0x00000100L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid4_MASK 0x00000200L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid3_MASK 0x00000400L -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid2_MASK 0x00000800L -#define CPG_F32CeDebugBus_287_264__qDecodeInstr_A_11_0_MASK 0x00fff000L -#define CPG_F32CeDebugBus_287_264__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_311_288 -#define CPG_F32CeDebugBus_311_288__qDecodeInstr_A_31_12_MASK 0x000fffffL -#define CPG_F32CeDebugBus_311_288__qDecodeInstr_B_3_0_MASK 0x00f00000L -#define CPG_F32CeDebugBus_311_288__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_335_312 -#define CPG_F32CeDebugBus_335_312__qDecodeInstr_B_27_4_MASK 0x00ffffffL -#define CPG_F32CeDebugBus_335_312__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_359_336 -#define CPG_F32CeDebugBus_359_336__qDecodeInstr_B_31_28_MASK 0x0000000fL -#define CPG_F32CeDebugBus_359_336__qDecodeAddress_A_padded_MASK 0x000ffff0L -#define CPG_F32CeDebugBus_359_336__qDecodeAddress_B_padded_3_0_MASK 0x00f00000L -#define CPG_F32CeDebugBus_359_336__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_383_360 -#define CPG_F32CeDebugBus_383_360__qDecodeAddress_B_padded_15_4_MASK 0x00000fffL -#define CPG_F32CeDebugBus_383_360__qAluIntUnitPntr_A_MASK 0x00007000L -#define CPG_F32CeDebugBus_383_360__AluIntUnitPntr_B_MASK 0x00038000L -#define CPG_F32CeDebugBus_383_360__qLdStrUnitPntr_A_MASK 0x001c0000L -#define CPG_F32CeDebugBus_383_360__qLdStrUnitPntr_B_MASK 0x00e00000L -#define CPG_F32CeDebugBus_383_360__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_407_384 -#define CPG_F32CeDebugBus_407_384__qDecodeInstrRts_A_MASK 0x00000001L -#define CPG_F32CeDebugBus_407_384__qDecodeInstrRts_B_MASK 0x00000002L -#define CPG_F32CeDebugBus_407_384__qJumpSourceRts_MASK 0x00000004L -#define CPG_F32CeDebugBus_407_384__qInstrEtsCnt_le_6_MASK 0x00000008L -#define CPG_F32CeDebugBus_407_384__Reserved1_MASK 0x000ffff0L -#define CPG_F32CeDebugBus_407_384__qThreadIdState_MASK 0x00f00000L -#define CPG_F32CeDebugBus_407_384__Reserved0_MASK 0xff000000L - -// CPG_F32CeDebugBus_431_408 -#define CPG_F32CeDebugBus_431_408__Reserved0_MASK 0xffffffffL - -// CPG_F32CeDebugBus_447_432 -#define CPG_F32CeDebugBus_447_432__Reserved0_MASK 0xffffffffL - -// CPG_AtcL2iuDebugIntf_23_0 -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_tag_MASK 0x0000007fL -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_xnack_MASK 0x00000180L -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_snoop_MASK 0x00000200L -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_valid_MASK 0x00000400L -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_physical_address_12_0_MASK 0x00fff800L -#define CPG_AtcL2iuDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPG_AtcL2iuDebugIntf_47_24 -#define CPG_AtcL2iuDebugIntf_47_24__qATCL2_CPG_ret_physical_address_35_13_MASK 0x007fffffL -#define CPG_AtcL2iuDebugIntf_47_24__CPG_ATCL2_req_data_0_MASK 0x00800000L -#define CPG_AtcL2iuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPG_AtcL2iuDebugIntf_71_48 -#define CPG_AtcL2iuDebugIntf_71_48__CPG_ATCL2_req_data_15_1_MASK 0x00007fffL -#define CPG_AtcL2iuDebugIntf_71_48__qCPG_ATCL2_req_free_MASK 0x00008000L -#define CPG_AtcL2iuDebugIntf_71_48__CPG_ATCL2_req_send_MASK 0x00010000L -#define CPG_AtcL2iuDebugIntf_71_48__qAtcL2XferCycle_eq_0_MASK 0x00020000L -#define CPG_AtcL2iuDebugIntf_71_48__Reserved0_MASK 0xfffc0000L - -// CPG_CeParserDebugIntf_23_0 -#define CPG_CeParserDebugIntf_23_0__qPrgmStrmXfc_MASK 0x00000001L -#define CPG_CeParserDebugIntf_23_0__qPrgmStrmRts_MASK 0x00000002L -#define CPG_CeParserDebugIntf_23_0__qPrgmStrmData_21_0_MASK 0x00fffffcL -#define CPG_CeParserDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPG_CeParserDebugIntf_47_24 -#define CPG_CeParserDebugIntf_47_24__qPrgmStrmData_31_22_MASK 0x000003ffL -#define CPG_CeParserDebugIntf_47_24__StoreRtr_2_MASK 0x00000400L -#define CPG_CeParserDebugIntf_47_24__StoreRtr_1_MASK 0x00000800L -#define CPG_CeParserDebugIntf_47_24__StoreRtr_0_MASK 0x00001000L -#define CPG_CeParserDebugIntf_47_24__StoreRts_MASK 0x00002000L -#define CPG_CeParserDebugIntf_47_24__StMemSpaceGlobal_MASK 0x00004000L -#define CPG_CeParserDebugIntf_47_24__StMemSpaceMemory_MASK 0x00008000L -#define CPG_CeParserDebugIntf_47_24__StMemSpaceMmReg_MASK 0x00010000L -#define CPG_CeParserDebugIntf_47_24__StMemSpaceLocal_MASK 0x00020000L -#define CPG_CeParserDebugIntf_47_24__StoreData_5_0_MASK 0x00fc0000L -#define CPG_CeParserDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPG_CeParserDebugIntf_71_48 -#define CPG_CeParserDebugIntf_71_48__StoreData_29_6_MASK 0x00ffffffL -#define CPG_CeParserDebugIntf_71_48__Reserved0_MASK 0xff000000L - -// CPG_CeParserDebugIntf_95_72 -#define CPG_CeParserDebugIntf_95_72__StoreData_31_30_MASK 0x00000003L -#define CPG_CeParserDebugIntf_95_72__qStoreAddr_21_0_MASK 0x00fffffcL -#define CPG_CeParserDebugIntf_95_72__Reserved0_MASK 0xff000000L - -// CPG_CeParserDebugIntf_119_96 -#define CPG_CeParserDebugIntf_119_96__qStoreAddr_45_22_MASK 0x00ffffffL -#define CPG_CeParserDebugIntf_119_96__Reserved0_MASK 0xff000000L - -// CPG_TciuDebugIntf_23_0 -#define CPG_TciuDebugIntf_23_0__CPG_TC_info_stall_MASK 0x00000001L -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_send_MASK 0x00000002L -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_vmid_MASK 0x0000003cL -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_op_MASK 0x00001fc0L -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_submask_MASK 0x001fe000L -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_fed_MASK 0x00200000L -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_tag_1_0_MASK 0x00c00000L -#define CPG_TciuDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPG_TciuDebugIntf_47_24 -#define CPG_TciuDebugIntf_47_24__CPG_TC_req_tag_9_2_MASK 0x000000ffL -#define CPG_TciuDebugIntf_47_24__CPG_TC_req_addr_15_0_MASK 0x00ffff00L -#define CPG_TciuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPG_TciuDebugIntf_71_48 -#define CPG_TciuDebugIntf_71_48__CPG_TC_req_addr_39_16_MASK 0x00ffffffL -#define CPG_TciuDebugIntf_71_48__Reserved0_MASK 0xff000000L - -// CPG_TciuDebugIntf_95_72 -#define CPG_TciuDebugIntf_95_72__CPG_TC_req_addr_41_40_MASK 0x00000003L -#define CPG_TciuDebugIntf_95_72__CPG_TC_req_subdata_21_0_MASK 0x00fffffcL -#define CPG_TciuDebugIntf_95_72__Reserved0_MASK 0xff000000L - -// CPG_TciuDebugIntf_119_96 -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_subdata_31_22_MASK 0x000003ffL -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_physical_MASK 0x00000400L -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_snoop_MASK 0x00000800L -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_mtype_MASK 0x00003000L -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_policy_MASK 0x00004000L -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_exe_MASK 0x00008000L -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_valid_MASK 0x00010000L -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_fed_MASK 0x00020000L -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_ack_MASK 0x00040000L -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_tag_4_0_MASK 0x00f80000L -#define CPG_TciuDebugIntf_119_96__Reserved0_MASK 0xff000000L - -// CPG_TciuDebugIntf_143_120 -#define CPG_TciuDebugIntf_143_120__Aligned_TC_CPG_ret_tag_9_5_MASK 0x0000001fL -#define CPG_TciuDebugIntf_143_120__Aligned_TC_CPG_ret_subdata_18_0_MASK 0x00ffffe0L -#define CPG_TciuDebugIntf_143_120__Reserved0_MASK 0xff000000L - -// CPG_TciuDebugIntf_167_144 -#define CPG_TciuDebugIntf_167_144__Aligned_TC_CPG_ret_subdata_31_19_MASK 0x00001fffL -#define CPG_TciuDebugIntf_167_144__Reserved0_MASK 0xffffe000L - -// CPG_SemaphoreDebugIntf -#define CPG_SemaphoreDebugIntf__qCPF_CPG_resp_pipeid_MASK 0x00000003L -#define CPG_SemaphoreDebugIntf__qCPF_CPG_resp_status_MASK 0x0000000cL -#define CPG_SemaphoreDebugIntf__qCPF_CPG_resp_valid_MASK 0x00000010L -#define CPG_SemaphoreDebugIntf__qCP_SEM_poll_addr_MASK 0x0001ffe0L -#define CPG_SemaphoreDebugIntf__qCP_SEM_poll_cmd_MASK 0x00020000L -#define CPG_SemaphoreDebugIntf__qCP_SEM_poll_send_MASK 0x00040000L -#define CPG_SemaphoreDebugIntf__Reserved0_MASK 0xfff80000L - -// CPG_F32PfpDebugBus_23_0 -#define CPG_F32PfpDebugBus_23_0__LdStrBufferData_23_0_MASK 0x00ffffffL -#define CPG_F32PfpDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_47_24 -#define CPG_F32PfpDebugBus_47_24__LdStrBufferData_47_24_MASK 0x00ffffffL -#define CPG_F32PfpDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_71_48 -#define CPG_F32PfpDebugBus_71_48__LdStrBufferData_63_48_MASK 0x0000ffffL -#define CPG_F32PfpDebugBus_71_48__LdStrBufferAddress_7_0_MASK 0x00ff0000L -#define CPG_F32PfpDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_95_72 -#define CPG_F32PfpDebugBus_95_72__LdStrBufferAddress_31_8_MASK 0x00ffffffL -#define CPG_F32PfpDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_119_96 -#define CPG_F32PfpDebugBus_119_96__LdStrBufferAddress_47_32_MASK 0x0000ffffL -#define CPG_F32PfpDebugBus_119_96__LdStrBufferInstrOp_MASK 0x00010000L -#define CPG_F32PfpDebugBus_119_96__LdStrInstrSel_MASK 0x00060000L -#define CPG_F32PfpDebugBus_119_96__LdStrMemSpace_MASK 0x00180000L -#define CPG_F32PfpDebugBus_119_96__qLoadStoreBusy_MASK 0x00200000L -#define CPG_F32PfpDebugBus_119_96__Reserved1_MASK 0x00400000L -#define CPG_F32PfpDebugBus_119_96__qLoadState_B_0_MASK 0x00800000L -#define CPG_F32PfpDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_143_120 -#define CPG_F32PfpDebugBus_143_120__qLoadState_B_1_MASK 0x00000001L -#define CPG_F32PfpDebugBus_143_120__qLoadState_A_MASK 0x00000006L -#define CPG_F32PfpDebugBus_143_120__LdStrBufferEmpty_MASK 0x00000008L -#define CPG_F32PfpDebugBus_143_120__LdStrBufferFull_MASK 0x00000010L -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc2Valid_B_MASK 0x00000020L -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc1Valid_B_MASK 0x00000040L -#define CPG_F32PfpDebugBus_143_120__qInstrMeValid_B_MASK 0x00000080L -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc2Valid_A_MASK 0x00000100L -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc1Valid_A_MASK 0x00000200L -#define CPG_F32PfpDebugBus_143_120__qInstrMeValid_A_MASK 0x00000400L -#define CPG_F32PfpDebugBus_143_120__Reserved0_MASK 0xfffff800L - -// CPG_F32PfpDebugBus_167_144 -#define CPG_F32PfpDebugBus_167_144__Reserved1_MASK 0x0000ffffL -#define CPG_F32PfpDebugBus_167_144__qLoadArbState_MASK 0x00030000L -#define CPG_F32PfpDebugBus_167_144__qStoreArbState_MASK 0x000c0000L -#define CPG_F32PfpDebugBus_167_144__Reserved0_MASK 0xfff00000L - -// CPG_F32PfpDebugBus_191_168 -#define CPG_F32PfpDebugBus_191_168__Reserved0_MASK 0xffffffffL - -// CPG_F32PfpDebugBus_215_192 -#define CPG_F32PfpDebugBus_215_192__qAluArbState_B_MASK 0x00000003L -#define CPG_F32PfpDebugBus_215_192__qAluArbState_A_MASK 0x0000000cL -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B_MASK 0x00000010L -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B_MASK 0x00000020L -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExValid_B_MASK 0x00000040L -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A_MASK 0x00000080L -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A_MASK 0x00000100L -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExValid_A_MASK 0x00000200L -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B_MASK 0x00000400L -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B_MASK 0x00000800L -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExValid_B_MASK 0x00001000L -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A_MASK 0x00002000L -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A_MASK 0x00004000L -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExValid_A_MASK 0x00008000L -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B_MASK 0x00010000L -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B_MASK 0x00020000L -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExValid_B_MASK 0x00040000L -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A_MASK 0x00080000L -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A_MASK 0x00100000L -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExValid_A_MASK 0x00200000L -#define CPG_F32PfpDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B_MASK 0x00400000L -#define CPG_F32PfpDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B_MASK 0x00800000L -#define CPG_F32PfpDebugBus_215_192__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_239_216 -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExValid_B_MASK 0x00000001L -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A_MASK 0x00000002L -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A_MASK 0x00000004L -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExValid_A_MASK 0x00000008L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid15_MASK 0x00000010L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid14_MASK 0x00000020L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid13_MASK 0x00000040L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid12_MASK 0x00000080L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid11_MASK 0x00000100L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid10_MASK 0x00000200L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid9_MASK 0x00000400L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid8_MASK 0x00000800L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid7_MASK 0x00001000L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid6_MASK 0x00002000L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid5_MASK 0x00004000L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid4_MASK 0x00008000L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid3_MASK 0x00010000L -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid2_MASK 0x00020000L -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid15_MASK 0x00040000L -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid14_MASK 0x00080000L -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid13_MASK 0x00100000L -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid12_MASK 0x00200000L -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid11_MASK 0x00400000L -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid10_MASK 0x00800000L -#define CPG_F32PfpDebugBus_239_216__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_263_240 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid9_MASK 0x00000001L -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid8_MASK 0x00000002L -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid7_MASK 0x00000004L -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid6_MASK 0x00000008L -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid5_MASK 0x00000010L -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid4_MASK 0x00000020L -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid3_MASK 0x00000040L -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid2_MASK 0x00000080L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid15_MASK 0x00000100L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid14_MASK 0x00000200L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid13_MASK 0x00000400L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid12_MASK 0x00000800L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid11_MASK 0x00001000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid10_MASK 0x00002000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid9_MASK 0x00004000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid8_MASK 0x00008000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid7_MASK 0x00010000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid6_MASK 0x00020000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid5_MASK 0x00040000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid4_MASK 0x00080000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid3_MASK 0x00100000L -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid2_MASK 0x00200000L -#define CPG_F32PfpDebugBus_263_240__DebugBus3_qGprValid15_MASK 0x00400000L -#define CPG_F32PfpDebugBus_263_240__DebugBus3_qGprValid14_MASK 0x00800000L -#define CPG_F32PfpDebugBus_263_240__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_287_264 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid13_MASK 0x00000001L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid12_MASK 0x00000002L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid11_MASK 0x00000004L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid10_MASK 0x00000008L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid9_MASK 0x00000010L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid8_MASK 0x00000020L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid7_MASK 0x00000040L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid6_MASK 0x00000080L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid5_MASK 0x00000100L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid4_MASK 0x00000200L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid3_MASK 0x00000400L -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid2_MASK 0x00000800L -#define CPG_F32PfpDebugBus_287_264__qDecodeInstr_A_11_0_MASK 0x00fff000L -#define CPG_F32PfpDebugBus_287_264__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_311_288 -#define CPG_F32PfpDebugBus_311_288__qDecodeInstr_A_31_12_MASK 0x000fffffL -#define CPG_F32PfpDebugBus_311_288__qDecodeInstr_B_3_0_MASK 0x00f00000L -#define CPG_F32PfpDebugBus_311_288__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_335_312 -#define CPG_F32PfpDebugBus_335_312__qDecodeInstr_B_27_4_MASK 0x00ffffffL -#define CPG_F32PfpDebugBus_335_312__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_359_336 -#define CPG_F32PfpDebugBus_359_336__qDecodeInstr_B_31_28_MASK 0x0000000fL -#define CPG_F32PfpDebugBus_359_336__qDecodeAddress_A_padded_MASK 0x000ffff0L -#define CPG_F32PfpDebugBus_359_336__qDecodeAddress_B_padded_3_0_MASK 0x00f00000L -#define CPG_F32PfpDebugBus_359_336__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_383_360 -#define CPG_F32PfpDebugBus_383_360__qDecodeAddress_B_padded_15_4_MASK 0x00000fffL -#define CPG_F32PfpDebugBus_383_360__qAluIntUnitPntr_A_MASK 0x00007000L -#define CPG_F32PfpDebugBus_383_360__AluIntUnitPntr_B_MASK 0x00038000L -#define CPG_F32PfpDebugBus_383_360__qLdStrUnitPntr_A_MASK 0x001c0000L -#define CPG_F32PfpDebugBus_383_360__qLdStrUnitPntr_B_MASK 0x00e00000L -#define CPG_F32PfpDebugBus_383_360__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_407_384 -#define CPG_F32PfpDebugBus_407_384__qDecodeInstrRts_A_MASK 0x00000001L -#define CPG_F32PfpDebugBus_407_384__qDecodeInstrRts_B_MASK 0x00000002L -#define CPG_F32PfpDebugBus_407_384__qJumpSourceRts_MASK 0x00000004L -#define CPG_F32PfpDebugBus_407_384__qInstrEtsCnt_le_6_MASK 0x00000008L -#define CPG_F32PfpDebugBus_407_384__Reserved1_MASK 0x000ffff0L -#define CPG_F32PfpDebugBus_407_384__qThreadIdState_MASK 0x00f00000L -#define CPG_F32PfpDebugBus_407_384__Reserved0_MASK 0xff000000L - -// CPG_F32PfpDebugBus_431_408 -#define CPG_F32PfpDebugBus_431_408__Reserved0_MASK 0xffffffffL - -// CPG_F32PfpDebugBus_447_432 -#define CPG_F32PfpDebugBus_447_432__Reserved0_MASK 0xffffffffL - -// CPG_F32MeDebugBus_23_0 -#define CPG_F32MeDebugBus_23_0__LdStrBufferData_23_0_MASK 0x00ffffffL -#define CPG_F32MeDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_47_24 -#define CPG_F32MeDebugBus_47_24__LdStrBufferData_47_24_MASK 0x00ffffffL -#define CPG_F32MeDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_71_48 -#define CPG_F32MeDebugBus_71_48__LdStrBufferData_63_48_MASK 0x0000ffffL -#define CPG_F32MeDebugBus_71_48__LdStrBufferAddress_7_0_MASK 0x00ff0000L -#define CPG_F32MeDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_95_72 -#define CPG_F32MeDebugBus_95_72__LdStrBufferAddress_31_8_MASK 0x00ffffffL -#define CPG_F32MeDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_119_96 -#define CPG_F32MeDebugBus_119_96__LdStrBufferAddress_47_32_MASK 0x0000ffffL -#define CPG_F32MeDebugBus_119_96__LdStrBufferInstrOp_MASK 0x00010000L -#define CPG_F32MeDebugBus_119_96__LdStrInstrSel_MASK 0x00060000L -#define CPG_F32MeDebugBus_119_96__LdStrMemSpace_MASK 0x00180000L -#define CPG_F32MeDebugBus_119_96__qLoadStoreBusy_MASK 0x00200000L -#define CPG_F32MeDebugBus_119_96__Reserved1_MASK 0x00400000L -#define CPG_F32MeDebugBus_119_96__qLoadState_B_0_MASK 0x00800000L -#define CPG_F32MeDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_143_120 -#define CPG_F32MeDebugBus_143_120__qLoadState_B_1_MASK 0x00000001L -#define CPG_F32MeDebugBus_143_120__qLoadState_A_MASK 0x00000006L -#define CPG_F32MeDebugBus_143_120__LdStrBufferEmpty_MASK 0x00000008L -#define CPG_F32MeDebugBus_143_120__LdStrBufferFull_MASK 0x00000010L -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc2Valid_B_MASK 0x00000020L -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc1Valid_B_MASK 0x00000040L -#define CPG_F32MeDebugBus_143_120__qInstrMeValid_B_MASK 0x00000080L -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc2Valid_A_MASK 0x00000100L -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc1Valid_A_MASK 0x00000200L -#define CPG_F32MeDebugBus_143_120__qInstrMeValid_A_MASK 0x00000400L -#define CPG_F32MeDebugBus_143_120__Reserved0_MASK 0xfffff800L - -// CPG_F32MeDebugBus_167_144 -#define CPG_F32MeDebugBus_167_144__Reserved1_MASK 0x0000ffffL -#define CPG_F32MeDebugBus_167_144__qLoadArbState_MASK 0x00030000L -#define CPG_F32MeDebugBus_167_144__qStoreArbState_MASK 0x000c0000L -#define CPG_F32MeDebugBus_167_144__Reserved0_MASK 0xfff00000L - -// CPG_F32MeDebugBus_191_168 -#define CPG_F32MeDebugBus_191_168__Reserved0_MASK 0xffffffffL - -// CPG_F32MeDebugBus_215_192 -#define CPG_F32MeDebugBus_215_192__qAluArbState_B_MASK 0x00000003L -#define CPG_F32MeDebugBus_215_192__qAluArbState_A_MASK 0x0000000cL -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B_MASK 0x00000010L -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B_MASK 0x00000020L -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExValid_B_MASK 0x00000040L -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A_MASK 0x00000080L -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A_MASK 0x00000100L -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExValid_A_MASK 0x00000200L -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B_MASK 0x00000400L -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B_MASK 0x00000800L -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExValid_B_MASK 0x00001000L -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A_MASK 0x00002000L -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A_MASK 0x00004000L -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExValid_A_MASK 0x00008000L -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B_MASK 0x00010000L -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B_MASK 0x00020000L -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExValid_B_MASK 0x00040000L -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A_MASK 0x00080000L -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A_MASK 0x00100000L -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExValid_A_MASK 0x00200000L -#define CPG_F32MeDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B_MASK 0x00400000L -#define CPG_F32MeDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B_MASK 0x00800000L -#define CPG_F32MeDebugBus_215_192__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_239_216 -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExValid_B_MASK 0x00000001L -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A_MASK 0x00000002L -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A_MASK 0x00000004L -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExValid_A_MASK 0x00000008L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid15_MASK 0x00000010L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid14_MASK 0x00000020L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid13_MASK 0x00000040L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid12_MASK 0x00000080L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid11_MASK 0x00000100L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid10_MASK 0x00000200L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid9_MASK 0x00000400L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid8_MASK 0x00000800L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid7_MASK 0x00001000L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid6_MASK 0x00002000L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid5_MASK 0x00004000L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid4_MASK 0x00008000L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid3_MASK 0x00010000L -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid2_MASK 0x00020000L -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid15_MASK 0x00040000L -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid14_MASK 0x00080000L -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid13_MASK 0x00100000L -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid12_MASK 0x00200000L -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid11_MASK 0x00400000L -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid10_MASK 0x00800000L -#define CPG_F32MeDebugBus_239_216__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_263_240 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid9_MASK 0x00000001L -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid8_MASK 0x00000002L -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid7_MASK 0x00000004L -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid6_MASK 0x00000008L -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid5_MASK 0x00000010L -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid4_MASK 0x00000020L -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid3_MASK 0x00000040L -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid2_MASK 0x00000080L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid15_MASK 0x00000100L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid14_MASK 0x00000200L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid13_MASK 0x00000400L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid12_MASK 0x00000800L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid11_MASK 0x00001000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid10_MASK 0x00002000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid9_MASK 0x00004000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid8_MASK 0x00008000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid7_MASK 0x00010000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid6_MASK 0x00020000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid5_MASK 0x00040000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid4_MASK 0x00080000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid3_MASK 0x00100000L -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid2_MASK 0x00200000L -#define CPG_F32MeDebugBus_263_240__DebugBus3_qGprValid15_MASK 0x00400000L -#define CPG_F32MeDebugBus_263_240__DebugBus3_qGprValid14_MASK 0x00800000L -#define CPG_F32MeDebugBus_263_240__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_287_264 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid13_MASK 0x00000001L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid12_MASK 0x00000002L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid11_MASK 0x00000004L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid10_MASK 0x00000008L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid9_MASK 0x00000010L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid8_MASK 0x00000020L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid7_MASK 0x00000040L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid6_MASK 0x00000080L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid5_MASK 0x00000100L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid4_MASK 0x00000200L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid3_MASK 0x00000400L -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid2_MASK 0x00000800L -#define CPG_F32MeDebugBus_287_264__qDecodeInstr_A_11_0_MASK 0x00fff000L -#define CPG_F32MeDebugBus_287_264__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_311_288 -#define CPG_F32MeDebugBus_311_288__qDecodeInstr_A_31_12_MASK 0x000fffffL -#define CPG_F32MeDebugBus_311_288__qDecodeInstr_B_3_0_MASK 0x00f00000L -#define CPG_F32MeDebugBus_311_288__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_335_312 -#define CPG_F32MeDebugBus_335_312__qDecodeInstr_B_27_4_MASK 0x00ffffffL -#define CPG_F32MeDebugBus_335_312__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_359_336 -#define CPG_F32MeDebugBus_359_336__qDecodeInstr_B_31_28_MASK 0x0000000fL -#define CPG_F32MeDebugBus_359_336__qDecodeAddress_A_padded_MASK 0x000ffff0L -#define CPG_F32MeDebugBus_359_336__qDecodeAddress_B_padded_3_0_MASK 0x00f00000L -#define CPG_F32MeDebugBus_359_336__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_383_360 -#define CPG_F32MeDebugBus_383_360__qDecodeAddress_B_padded_15_4_MASK 0x00000fffL -#define CPG_F32MeDebugBus_383_360__qAluIntUnitPntr_A_MASK 0x00007000L -#define CPG_F32MeDebugBus_383_360__AluIntUnitPntr_B_MASK 0x00038000L -#define CPG_F32MeDebugBus_383_360__qLdStrUnitPntr_A_MASK 0x001c0000L -#define CPG_F32MeDebugBus_383_360__qLdStrUnitPntr_B_MASK 0x00e00000L -#define CPG_F32MeDebugBus_383_360__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_407_384 -#define CPG_F32MeDebugBus_407_384__qDecodeInstrRts_A_MASK 0x00000001L -#define CPG_F32MeDebugBus_407_384__qDecodeInstrRts_B_MASK 0x00000002L -#define CPG_F32MeDebugBus_407_384__qJumpSourceRts_MASK 0x00000004L -#define CPG_F32MeDebugBus_407_384__qInstrEtsCnt_le_6_MASK 0x00000008L -#define CPG_F32MeDebugBus_407_384__Reserved1_MASK 0x000ffff0L -#define CPG_F32MeDebugBus_407_384__qThreadIdState_MASK 0x00f00000L -#define CPG_F32MeDebugBus_407_384__Reserved0_MASK 0xff000000L - -// CPG_F32MeDebugBus_431_408 -#define CPG_F32MeDebugBus_431_408__Reserved0_MASK 0xffffffffL - -// CPG_F32MeDebugBus_447_432 -#define CPG_F32MeDebugBus_447_432__Reserved0_MASK 0xffffffffL - -// CPF_RbiuDebugIntf_23_0 -#define CPF_RbiuDebugIntf_23_0__GRBM_CP_reg_free_MASK 0x00000001L -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_send_MASK 0x00000002L -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_clken_MASK 0x00000004L -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_priv_MASK 0x00000008L -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_op_MASK 0x00000010L -#define CPF_RbiuDebugIntf_23_0__RdReturnValid_MASK 0x00000020L -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_addr_MASK 0x003fffc0L -#define CPF_RbiuDebugIntf_23_0__Reserved0_MASK 0xffc00000L - -// CPF_RbiuDebugIntf_47_24 -#define CPF_RbiuDebugIntf_47_24__iGRBM_CP_reg_data_MASK 0x00000fffL -#define CPF_RbiuDebugIntf_47_24__RdReturnData_MASK 0x00fff000L -#define CPF_RbiuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPF_SemaphoreDebugIntf -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_pipeid_MASK 0x00000003L -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_meid_MASK 0x0000000cL -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_status_MASK 0x00000030L -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_send_MASK 0x00000040L -#define CPF_SemaphoreDebugIntf__Reserved0_MASK 0xffffff80L - -// CPF_Rbiu_Semaphore_DebugBus -#define CPF_Rbiu_Semaphore_DebugBus__Reserved2_MASK 0x000003ffL -#define CPF_Rbiu_Semaphore_DebugBus__qReadCycleCount_MASK 0x00001c00L -#define CPF_Rbiu_Semaphore_DebugBus__qReadState_MASK 0x00002000L -#define CPF_Rbiu_Semaphore_DebugBus__qWriteHold_MASK 0x00004000L -#define CPF_Rbiu_Semaphore_DebugBus__qFreeCountUnderflow_MASK 0x00008000L -#define CPF_Rbiu_Semaphore_DebugBus__qFreeCountOverflow_MASK 0x00010000L -#define CPF_Rbiu_Semaphore_DebugBus__qFreeCount_neq_0_MASK 0x00020000L -#define CPF_Rbiu_Semaphore_DebugBus__qGRBM_CP_reg_send_MASK 0x00040000L -#define CPF_Rbiu_Semaphore_DebugBus__GrbmCpFifoFull_MASK 0x00080000L -#define CPF_Rbiu_Semaphore_DebugBus__GrbmCpFifoEmpty_MASK 0x00100000L -#define CPF_Rbiu_Semaphore_DebugBus__Reserved1_MASK 0x00200000L -#define CPF_Rbiu_Semaphore_DebugBus__iHQD1_TCIU_rdreq_rts_MASK 0x00400000L -#define CPF_Rbiu_Semaphore_DebugBus__iCSF_TCIU_rdreq_rts_MASK 0x00800000L -#define CPF_Rbiu_Semaphore_DebugBus__Reserved0_MASK 0xff000000L - -// CPF_TciuDebugBus_47_24 -#define CPF_TciuDebugBus_47_24__XferId_MASK 0x00000007L -#define CPF_TciuDebugBus_47_24__qDmaTransCnt_MASK 0x00000078L -#define CPF_TciuDebugBus_47_24__qHqd2TransCnt_MASK 0x00000780L -#define CPF_TciuDebugBus_47_24__qHqd1TransCnt_MASK 0x00007800L -#define CPF_TciuDebugBus_47_24__qCsfTransCnt_MASK 0x00078000L -#define CPF_TciuDebugBus_47_24__DmaRts_MASK 0x00080000L -#define CPF_TciuDebugBus_47_24__Hqd2Rts_MASK 0x00100000L -#define CPF_TciuDebugBus_47_24__Hqd1Rts_MASK 0x00200000L -#define CPF_TciuDebugBus_47_24__CsfRts_MASK 0x00400000L -#define CPF_TciuDebugBus_47_24__iHQD2_TCIU_rdreq_rts_MASK 0x00800000L -#define CPF_TciuDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPF_TciuDebugBus_23_0 -#define CPF_TciuDebugBus_23_0__CpfTciuPostArbFifo_Empty_MASK 0x00000001L -#define CPF_TciuDebugBus_23_0__CpfTciuPostArbFifo_Full_MASK 0x00000002L -#define CPF_TciuDebugBus_23_0__CpfTcOutCnt_MASK 0x00000ffcL -#define CPF_TciuDebugBus_23_0__CpfTcCnt_MASK 0x0001f000L -#define CPF_TciuDebugBus_23_0__CpgTciuRdReqFifo_Empty_MASK 0x00020000L -#define CPF_TciuDebugBus_23_0__CpgTciuRdReqFifo_Full_MASK 0x00040000L -#define CPF_TciuDebugBus_23_0__TagBusy_MASK 0x00080000L -#define CPF_TciuDebugBus_23_0__oTciuBusy_MASK 0x00100000L -#define CPF_TciuDebugBus_23_0__Aligned_TcRetXferCycle_MASK 0x00200000L -#define CPF_TciuDebugBus_23_0__TcClkenWarmupRdy_MASK 0x00400000L -#define CPF_TciuDebugBus_23_0__TcRdy_MASK 0x00800000L -#define CPF_TciuDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_TciuDebugIntf_23_0 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdnfo_stall_MASK 0x00000001L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_send_MASK 0x00000002L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_exe_MASK 0x00000004L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_physical_MASK 0x00000008L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_snoop_MASK 0x00000010L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_policy_MASK 0x00000020L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_mtype_MASK 0x000000c0L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_vmid_MASK 0x00000f00L -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_tag_11_0_MASK 0x00fff000L -#define CPF_TciuDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPF_TciuDebugIntf_47_24 -#define CPF_TciuDebugIntf_47_24__CPF_TC_rdreq_tag_15_12_MASK 0x0000000fL -#define CPF_TciuDebugIntf_47_24__CPF_TC_rdreq_addr_19_0_MASK 0x00fffff0L -#define CPF_TciuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPF_TciuDebugIntf_71_48 -#define CPF_TciuDebugIntf_71_48__CPF_TC_rdreq_addr_41_20_MASK 0x003fffffL -#define CPF_TciuDebugIntf_71_48__Aligned_TC_CPF_rdret_valid_MASK 0x00400000L -#define CPF_TciuDebugIntf_71_48__Aligned_TC_CPF_rdret_fed_MASK 0x00800000L -#define CPF_TciuDebugIntf_71_48__Reserved0_MASK 0xff000000L - -// CPF_TciuDebugIntf_95_72 -#define CPF_TciuDebugIntf_95_72__Aligned_TC_CPF_rdret_tag_MASK 0x0000ffffL -#define CPF_TciuDebugIntf_95_72__Aligned_TC_CPF_rdret_subdata_7_0_MASK 0x00ff0000L -#define CPF_TciuDebugIntf_95_72__Reserved0_MASK 0xff000000L - -// CPF_TciuDebugIntf_119_96 -#define CPF_TciuDebugIntf_119_96__Aligned_TC_CPF_rdret_subdata_31_8_MASK 0x00ffffffL -#define CPF_TciuDebugIntf_119_96__Reserved0_MASK 0xff000000L - -// CPF_UtcL2iuDebugIntf_23_0 -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_tag_MASK 0x0000007fL -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_nack_MASK 0x00000180L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_mtype_MASK 0x00000600L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_memlog_MASK 0x00000800L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_no_pte_MASK 0x00001000L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_pte_tmz_MASK 0x00002000L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_spa_MASK 0x00004000L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_io_steer_MASK 0x00008000L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_fragment_size_5_0_MASK 0x003f0000L -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_perms_granted_1_0_MASK 0x00c00000L -#define CPF_UtcL2iuDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPF_UtcL2iuDebugIntf_47_24 -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_perms_granted_2_MASK 0x00000001L -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_perms_requested_2_0_MASK 0x0000000eL -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_snoop_MASK 0x00000010L -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_valid_MASK 0x00000020L -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_perms_requested_17_0_MASK 0x00ffffc0L -#define CPF_UtcL2iuDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPF_UtcL2iuDebugIntf_71_48 -#define CPF_UtcL2iuDebugIntf_71_48__iUTCL2_CPF_ret_perms_requested_35_18_MASK 0x0003ffffL -#define CPF_UtcL2iuDebugIntf_71_48__CPF_UTCL2_req_data_5_0_MASK 0x00fc0000L -#define CPF_UtcL2iuDebugIntf_71_48__Reserved0_MASK 0xff000000L - -// CPF_UtcL2iuDebugIntf_95_72 -#define CPF_UtcL2iuDebugIntf_95_72__CPF_UTCL2_req_data_15_6_MASK 0x000003ffL -#define CPF_UtcL2iuDebugIntf_95_72__qCPF_UTCL2_req_free_MASK 0x00000400L -#define CPF_UtcL2iuDebugIntf_95_72__CPF_UTCL2_req_send_MASK 0x00000800L -#define CPF_UtcL2iuDebugIntf_95_72__qUtcL2XferCycle_eq_0_MASK 0x00001000L -#define CPF_UtcL2iuDebugIntf_95_72__Reserved0_MASK 0xfffc0000L - -// CPF_HqdQueueDebugBus_23_0 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_HqdQueueDebugBus_47_24 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPF_HqdQueueDebugBus_71_48 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPF_HqdQueueDebugBus_95_72 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPF_HqdQueueDebugBus_119_96 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPF_HqdQueueDebugBus_143_120 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_143_120__Reserved0_MASK 0xff000000L - -// CPF_HqdQueueDebugBus_167_144 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_167_144__Reserved0_MASK 0xff000000L - -// CPF_HqdQueueDebugBus_191_168 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_0_qImmedPend_MASK 0x00000001L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_0_qSemEccMessageRts_MASK 0x00000002L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_0_qTimerWaitMessageRts_MASK 0x00000004L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_1_qImmedPend_MASK 0x00000008L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_1_qSemEccMessageRts_MASK 0x00000010L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_1_qTimerWaitMessageRts_MASK 0x00000020L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_2_qImmedPend_MASK 0x00000040L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_2_qSemEccMessageRts_MASK 0x00000080L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_2_qTimerWaitMessageRts_MASK 0x00000100L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_3_qImmedPend_MASK 0x00000200L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_3_qSemEccMessageRts_MASK 0x00000400L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_3_qTimerWaitMessageRts_MASK 0x00000800L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_4_qImmedPend_MASK 0x00001000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_4_qSemEccMessageRts_MASK 0x00002000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_4_qTimerWaitMessageRts_MASK 0x00004000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_5_qImmedPend_MASK 0x00008000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_5_qSemEccMessageRts_MASK 0x00010000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_5_qTimerWaitMessageRts_MASK 0x00020000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_6_qImmedPend_MASK 0x00040000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_6_qSemEccMessageRts_MASK 0x00080000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_6_qTimerWaitMessageRts_MASK 0x00100000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_7_qImmedPend_MASK 0x00200000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_7_qSemEccMessageRts_MASK 0x00400000L -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_7_qTimerWaitMessageRts_MASK 0x00800000L -#define CPF_HqdQueueDebugBus_191_168__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_23_0 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqReadPntr_neq_qPqWritePntr_MASK 0x00000002L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqWritePntr_le_qPqReadPntr_MASK 0x00000004L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_47_24 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqReadPntr_neq_qPqWritePntr_MASK 0x00000002L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqWritePntr_le_qPqReadPntr_MASK 0x00000004L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_71_48 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqReadPntr_neq_qPqWritePntr_MASK 0x00000002L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqWritePntr_le_qPqReadPntr_MASK 0x00000004L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_95_72 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqReadPntr_neq_qPqWritePntr_MASK 0x00000002L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqWritePntr_le_qPqReadPntr_MASK 0x00000004L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_119_96 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqReadPntr_neq_qPqWritePntr_MASK \ - 0x00000002L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqWritePntr_le_qPqReadPntr_MASK 0x00000004L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_143_120 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqReadPntr_neq_qPqWritePntr_MASK \ - 0x00000002L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqWritePntr_le_qPqReadPntr_MASK \ - 0x00000004L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_143_120__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_167_144 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqReadPntr_neq_qPqWritePntr_MASK \ - 0x00000002L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqWritePntr_le_qPqReadPntr_MASK \ - 0x00000004L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_167_144__Reserved0_MASK 0xff000000L - -// CPF_QueueFetcherDebugBus_191_168 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqQueueSize_neq_0_MASK 0x00000001L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqReadPntr_neq_qPqWritePntr_MASK \ - 0x00000002L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqWritePntr_le_qPqReadPntr_MASK \ - 0x00000004L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_EopqQueueSize_neq_0_MASK 0x00000008L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_IqFetcherFifoEmpty_MASK 0x00000010L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_IqFetcherFifoFull_MASK 0x00000020L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIqBufSize_eq_0_MASK 0x00000040L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIbBufSize_neq_0_MASK 0x00000080L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr_MASK \ - 0x00000100L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPreCsmdIbBufSize_eq_0_MASK 0x00000200L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedIbBufSize_neq_0_MASK 0x00000400L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqValidReqState_MASK 0x00000800L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIbValidReqState_MASK 0x00001000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIqValidReqState_MASK 0x00002000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qEopValidReqState_MASK 0x00004000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedRdPntr_neq_qPqWritePntr_MASK \ - 0x00008000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedRdPntr_eq_qHostRdPntr_MASK \ - 0x00010000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqEmpty_MASK 0x00020000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqRoqAvailCnt_neq_qPqRoqDepth_000_MASK \ - 0x00040000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIbRoqAvailCnt_neq_qIbRoqDepth_000_MASK \ - 0x00080000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIqRoqAvailCnt_neq_qIqRoqDepth_000_MASK \ - 0x00100000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qEopRoqAvailCnt_neq_qEopRoqDepth_000_MASK \ - 0x00200000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqRdPntrReportRts_MASK 0x00400000L -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqRptrTagCount_neq_0_MASK 0x00800000L -#define CPF_QueueFetcherDebugBus_191_168__Reserved0_MASK 0xff000000L - -// CPF_HqdQueMngrDebugBus_23_0 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable0_MASK 0x00000001L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable1_MASK 0x00000002L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable2_MASK 0x00000004L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable3_MASK 0x00000008L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable4_MASK 0x00000010L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable5_MASK 0x00000020L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable6_MASK 0x00000040L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable7_MASK 0x00000080L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qMappedQueue_MASK 0x00000700L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueState_MASK 0x0000f800L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable0_MASK 0x00010000L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable1_MASK 0x00020000L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable2_MASK 0x00040000L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable3_MASK 0x00080000L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable4_MASK 0x00100000L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable5_MASK 0x00200000L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable6_MASK 0x00400000L -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable7_MASK 0x00800000L -#define CPF_HqdQueMngrDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_HqdQueMngrDebugBus_47_24 -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_1_qMappedQueue_MASK 0x00000007L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_1_qQueueState_MASK 0x000000f8L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable0_MASK 0x00000100L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable1_MASK 0x00000200L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable2_MASK 0x00000400L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable3_MASK 0x00000800L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable4_MASK 0x00001000L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable5_MASK 0x00002000L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable6_MASK 0x00004000L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable7_MASK 0x00008000L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qMappedQueue_MASK 0x00070000L -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueState_MASK 0x00f80000L -#define CPF_HqdQueMngrDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPF_HqdQueMngrDebugBus_71_48 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable0_MASK 0x00000001L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable1_MASK 0x00000002L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable2_MASK 0x00000004L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable3_MASK 0x00000008L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable4_MASK 0x00000010L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable5_MASK 0x00000020L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable6_MASK 0x00000040L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable7_MASK 0x00000080L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qMappedQueue_MASK 0x00000700L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueState_MASK 0x0000f800L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable0_MASK 0x00010000L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable1_MASK 0x00020000L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable2_MASK 0x00040000L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable3_MASK 0x00080000L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable4_MASK 0x00100000L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable5_MASK 0x00200000L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable6_MASK 0x00400000L -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable7_MASK 0x00800000L -#define CPF_HqdQueMngrDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPF_HqdQueMngrDebugBus_95_72 -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_4_qMappedQueue_MASK 0x00000007L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_4_qQueueState_MASK 0x000000f8L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable0_MASK 0x00000100L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable1_MASK 0x00000200L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable2_MASK 0x00000400L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable3_MASK 0x00000800L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable4_MASK 0x00001000L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable5_MASK 0x00002000L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable6_MASK 0x00004000L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable7_MASK 0x00008000L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qMappedQueue_MASK 0x00070000L -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueState_MASK 0x00f80000L -#define CPF_HqdQueMngrDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPF_HqdQueMngrDebugBus_119_96 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable0_MASK 0x00000001L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable1_MASK 0x00000002L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable2_MASK 0x00000004L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable3_MASK 0x00000008L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable4_MASK 0x00000010L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable5_MASK 0x00000020L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable6_MASK 0x00000040L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable7_MASK 0x00000080L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qMappedQueue_MASK 0x00000700L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueState_MASK 0x0000f800L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable0_MASK 0x00010000L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable1_MASK 0x00020000L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable2_MASK 0x00040000L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable3_MASK 0x00080000L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable4_MASK 0x00100000L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable5_MASK 0x00200000L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable6_MASK 0x00400000L -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable7_MASK 0x00800000L -#define CPF_HqdQueMngrDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPF_HqdQueMngrDebugBus_127_120 -#define CPF_HqdQueMngrDebugBus_127_120__HqdQueMngr_7_qMappedQueue_MASK 0x00000007L -#define CPF_HqdQueMngrDebugBus_127_120__HqdQueMngr_7_qQueueState_MASK 0x000000f8L -#define CPF_HqdQueMngrDebugBus_127_120__HqdArbitrateDebugBus_11_0_MASK 0x000fff00L -#define CPF_HqdQueMngrDebugBus_127_120__Reserved0_MASK 0xfff00000L - -// CPF_HqdRoqCmdQueDebugBus_23_0 -#define CPF_HqdRoqCmdQueDebugBus_23_0__Mec1_HqdRoqThreadDebugBus0_MASK 0x00000fffL -#define CPF_HqdRoqCmdQueDebugBus_23_0__Mec1_HqdRoqThreadDebugBus1_MASK 0x00fff000L -#define CPF_HqdRoqCmdQueDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_HqdRoqCmdQueDebugBus_47_24 -#define CPF_HqdRoqCmdQueDebugBus_47_24__Mec1_HqdRoqThreadDebugBus2_MASK 0x00000fffL -#define CPF_HqdRoqCmdQueDebugBus_47_24__Mec1_HqdRoqThreadDebugBus3_MASK 0x00fff000L -#define CPF_HqdRoqCmdQueDebugBus_47_24__Reserved0_MASK 0xff000000L - -// CPF_HqdRoqCmdQueDebugBus_71_48 -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree0_MASK 0x0000000fL -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree1_MASK 0x000000f0L -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree2_MASK 0x00000f00L -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree3_MASK 0x0000f000L -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueSend0_MASK 0x000f0000L -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueSend1_MASK 0x00f00000L -#define CPF_HqdRoqCmdQueDebugBus_71_48__Reserved0_MASK 0xff000000L - -// CPF_HqdRoqCmdQueDebugBus_95_72 -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec1_HqdRoqThreadDebugBusqRoQueueSend2_MASK 0x0000000fL -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec1_HqdRoqThreadDebugBusqRoQueueSend3_MASK 0x000000f0L -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec1_HqdRoqThreadDebugBusPipeSelect_MASK 0x00000300L -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec2_HqdRoqThreadDebugBus0_MASK 0x003ffc00L -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec2_HqdRoqThreadDebugBus1_1_0_MASK 0x00c00000L -#define CPF_HqdRoqCmdQueDebugBus_95_72__Reserved0_MASK 0xff000000L - -// CPF_HqdRoqCmdQueDebugBus_119_96 -#define CPF_HqdRoqCmdQueDebugBus_119_96__Mec2_HqdRoqThreadDebugBus1_11_2_MASK 0x000003ffL -#define CPF_HqdRoqCmdQueDebugBus_119_96__Mec2_HqdRoqThreadDebugBus2_MASK 0x003ffc00L -#define CPF_HqdRoqCmdQueDebugBus_119_96__Mec2_HqdRoqThreadDebugBus3_1_0_MASK 0x00c00000L -#define CPF_HqdRoqCmdQueDebugBus_119_96__Reserved0_MASK 0xff000000L - -// CPF_HqdRoqCmdQueDebugBus_143_120 -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_HqdRoqThreadDebugBus3_11_2_MASK 0x000003ffL -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree0_MASK 0x00003c00L -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree1_MASK 0x0003c000L -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree2_MASK 0x003c0000L -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree3_1_0_MASK 0x00c00000L -#define CPF_HqdRoqCmdQueDebugBus_143_120__Reserved0_MASK 0xff000000L - -// CPF_HqdRoqCmdQueDebugBus_163_144 -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_qRoQueueFree3_3_2_MASK 0x00000003L -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_qRoQueueSend0_MASK 0x0000003cL -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_qRoQueueSend1_MASK 0x000003c0L -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_HqdRoqThreadDebugBusqRoQueueSend2_MASK 0x00003c00L -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_HqdRoqThreadDebugBusqRoQueueSend3_MASK 0x0003c000L -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_HqdRoqThreadDebugBusPipeSelect_MASK 0x000c0000L -#define CPF_HqdRoqCmdQueDebugBus_163_144__Reserved0_MASK 0xfff00000L - -// CPF_HqdRoqAlignDebugBus -#define CPF_HqdRoqAlignDebugBus__Mec1_qDuplicateMaskError_MASK 0x00000001L -#define CPF_HqdRoqAlignDebugBus__Mec1_qBufferDeallocCount_neq_0_MASK 0x00000002L -#define CPF_HqdRoqAlignDebugBus__Mec1_ScratchMaskRts_MASK 0x00000004L -#define CPF_HqdRoqAlignDebugBus__Mec1_BufOutEmpty_MASK 0x00000008L -#define CPF_HqdRoqAlignDebugBus__Mec1_BufOutFull_MASK 0x00000010L -#define CPF_HqdRoqAlignDebugBus__Mec1_BufferEmpty_MASK 0x00000020L -#define CPF_HqdRoqAlignDebugBus__Mec1_BufferFull_MASK 0x00000040L -#define CPF_HqdRoqAlignDebugBus__Mec1_qBufferOverFlowError_MASK 0x00000080L -#define CPF_HqdRoqAlignDebugBus__Mec1_qRdRetSendCnt_neq_0_MASK 0x00000100L -#define CPF_HqdRoqAlignDebugBus__Mec2_qDuplicateMaskError_MASK 0x00000200L -#define CPF_HqdRoqAlignDebugBus__Mec2_qBufferDeallocCount_neq_0_MASK 0x00000400L -#define CPF_HqdRoqAlignDebugBus__Mec2_ScratchMaskRts_MASK 0x00000800L -#define CPF_HqdRoqAlignDebugBus__Mec2_BufOutEmpty_MASK 0x00001000L -#define CPF_HqdRoqAlignDebugBus__Mec2_BufOutFull_MASK 0x00002000L -#define CPF_HqdRoqAlignDebugBus__Mec2_BufferEmpty_MASK 0x00004000L -#define CPF_HqdRoqAlignDebugBus__Mec2_BufferFull_MASK 0x00008000L -#define CPF_HqdRoqAlignDebugBus__Mec2_qBufferOverFlowError_MASK 0x00010000L -#define CPF_HqdRoqAlignDebugBus__Mec2_qRdRetSendCnt_neq_0_MASK 0x00020000L -#define CPF_HqdRoqAlignDebugBus__Reserved0_MASK 0xfffc0000L - -// CPF_Roq_StQueue_Align_DebugBus -#define CPF_Roq_StQueue_Align_DebugBus__qDuplicateMaskError_MASK 0x00000001L -#define CPF_Roq_StQueue_Align_DebugBus__qBufferDeallocCount_neq_0_MASK 0x00000002L -#define CPF_Roq_StQueue_Align_DebugBus__ScratchMaskRts_MASK 0x00000004L -#define CPF_Roq_StQueue_Align_DebugBus__BufOutEmpty_MASK 0x00000008L -#define CPF_Roq_StQueue_Align_DebugBus__BufOutFull_MASK 0x00000010L -#define CPF_Roq_StQueue_Align_DebugBus__BufferEmpty_MASK 0x00000020L -#define CPF_Roq_StQueue_Align_DebugBus__BufferFull_MASK 0x00000040L -#define CPF_Roq_StQueue_Align_DebugBus__qBufferOverFlowError_MASK 0x00000080L -#define CPF_Roq_StQueue_Align_DebugBus__qRdRetSendCnt_neq_0_MASK 0x00000100L -#define CPF_Roq_StQueue_Align_DebugBus__Reserved1_MASK 0x0000fe00L -#define CPF_Roq_StQueue_Align_DebugBus__qStqAvailCnt_R2_neq_qStqMaxCnt_R2_MASK 0x00010000L -#define CPF_Roq_StQueue_Align_DebugBus__qStqAvailCnt_R1_neq_qStqMaxCnt_R1_MASK 0x00020000L -#define CPF_Roq_StQueue_Align_DebugBus__qStqAvailCnt_R0_neq_qStqMaxCnt_R0_MASK 0x00040000L -#define CPF_Roq_StQueue_Align_DebugBus__qRingIdState_MASK 0x00180000L -#define CPF_Roq_StQueue_Align_DebugBus__StqRts_R2_MASK 0x00200000L -#define CPF_Roq_StQueue_Align_DebugBus__StqRts_R1_MASK 0x00400000L -#define CPF_Roq_StQueue_Align_DebugBus__StqRts_R0_MASK 0x00800000L -#define CPF_Roq_StQueue_Align_DebugBus__Reserved0_MASK 0xff000000L - -// CPF_RoqCmdQueueDebugBus_23_0 -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_RealAvailCntQueue_R2_neq_qI2_MaxCntQueue_R2_MASK \ - 0x00000001L -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_RealAvailCntQueue_R1_neq_qI2_MaxCntQueue_R1_MASK \ - 0x00000002L -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_RealAvailCntQueue_R0_neq_qI2_MaxCntQueue_R0_MASK \ - 0x00000004L -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_RealAvailCntQueue_R2_neq_qI1_MaxCntQueue_R2_MASK \ - 0x00000008L -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_RealAvailCntQueue_R1_neq_qI1_MaxCntQueue_R1_MASK \ - 0x00000010L -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_RealAvailCntQueue_R0_neq_qI1_MaxCntQueue_R0_MASK \ - 0x00000020L -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_RealAvailCntQueue_R2_neq_qRb_MaxCntQueue_R2_MASK \ - 0x00000040L -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_RealAvailCntQueue_R1_neq_qRb_MaxCntQueue_R1_MASK \ - 0x00000080L -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_RealAvailCntQueue_R0_neq_qRb_MaxCntQueue_R0_MASK \ - 0x00000100L -#define CPF_RoqCmdQueueDebugBus_23_0__Reserved1_MASK 0x00007e00L -#define CPF_RoqCmdQueueDebugBus_23_0__qRingIdState_MASK 0x00018000L -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_SlipCntQueue_R2_neq_0_MASK 0x00020000L -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_SlipCntQueue_R1_neq_0_MASK 0x00040000L -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_SlipCntQueue_R0_neq_0_MASK 0x00080000L -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_SlipCntQueue_R2_neq_0_MASK 0x00100000L -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_SlipCntQueue_R1_neq_0_MASK 0x00200000L -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_SlipCntQueue_R0_neq_0_MASK 0x00400000L -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_SlipCntQueue_R2_neq_0_MASK 0x00800000L -#define CPF_RoqCmdQueueDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_RoqCmdQueueDebugBus_47_24 -#define CPF_RoqCmdQueueDebugBus_47_24__qRb_SlipCntQueue_R1_neq_0_MASK 0x00000001L -#define CPF_RoqCmdQueueDebugBus_47_24__qRb_SlipCntQueue_R0_neq_0_MASK 0x00000002L -#define CPF_RoqCmdQueueDebugBus_47_24__I2_QueueRts_R2_MASK 0x00000004L -#define CPF_RoqCmdQueueDebugBus_47_24__I2_QueueRts_R1_MASK 0x00000008L -#define CPF_RoqCmdQueueDebugBus_47_24__I2_QueueRts_R0_MASK 0x00000010L -#define CPF_RoqCmdQueueDebugBus_47_24__I1_QueueRts_R2_MASK 0x00000020L -#define CPF_RoqCmdQueueDebugBus_47_24__I1_QueueRts_R1_MASK 0x00000040L -#define CPF_RoqCmdQueueDebugBus_47_24__I1_QueueRts_R0_MASK 0x00000080L -#define CPF_RoqCmdQueueDebugBus_47_24__Rb_QueueRts_R2_MASK 0x00000100L -#define CPF_RoqCmdQueueDebugBus_47_24__Rb_QueueRts_R1_MASK 0x00000200L -#define CPF_RoqCmdQueueDebugBus_47_24__Rb_QueueRts_R0_MASK 0x00000400L -#define CPF_RoqCmdQueueDebugBus_47_24__Reserved0_MASK 0xfffff800L - -// CPF_RoqCnstQueueDebugBus_23_0 -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_RealAvailCntQueue_R2_neq_qI2_MaxCntQueue_R2_MASK \ - 0x00000001L -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_RealAvailCntQueue_R1_neq_qI2_MaxCntQueue_R1_MASK \ - 0x00000002L -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_RealAvailCntQueue_R0_neq_qI2_MaxCntQueue_R0_MASK \ - 0x00000004L -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_RealAvailCntQueue_R2_neq_qI1_MaxCntQueue_R2_MASK \ - 0x00000008L -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_RealAvailCntQueue_R1_neq_qI1_MaxCntQueue_R1_MASK \ - 0x00000010L -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_RealAvailCntQueue_R0_neq_qI1_MaxCntQueue_R0_MASK \ - 0x00000020L -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_RealAvailCntQueue_R2_neq_qRb_MaxCntQueue_R2_MASK \ - 0x00000040L -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_RealAvailCntQueue_R1_neq_qRb_MaxCntQueue_R1_MASK \ - 0x00000080L -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_RealAvailCntQueue_R0_neq_qRb_MaxCntQueue_R0_MASK \ - 0x00000100L -#define CPF_RoqCnstQueueDebugBus_23_0__Reserved1_MASK 0x00007e00L -#define CPF_RoqCnstQueueDebugBus_23_0__qRingIdState_MASK 0x00018000L -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_SlipCntQueue_R2_neq_0_MASK 0x00020000L -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_SlipCntQueue_R1_neq_0_MASK 0x00040000L -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_SlipCntQueue_R0_neq_0_MASK 0x00080000L -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_SlipCntQueue_R2_neq_0_MASK 0x00100000L -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_SlipCntQueue_R1_neq_0_MASK 0x00200000L -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_SlipCntQueue_R0_neq_0_MASK 0x00400000L -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_SlipCntQueue_R2_neq_0_MASK 0x00800000L -#define CPF_RoqCnstQueueDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_RoqCnstQueueDebugBus_47_24 -#define CPF_RoqCnstQueueDebugBus_47_24__qRb_SlipCntQueue_R1_neq_0_MASK 0x00000001L -#define CPF_RoqCnstQueueDebugBus_47_24__qRb_SlipCntQueue_R0_neq_0_MASK 0x00000002L -#define CPF_RoqCnstQueueDebugBus_47_24__I2_QueueRts_R2_MASK 0x00000004L -#define CPF_RoqCnstQueueDebugBus_47_24__I2_QueueRts_R1_MASK 0x00000008L -#define CPF_RoqCnstQueueDebugBus_47_24__I2_QueueRts_R0_MASK 0x00000010L -#define CPF_RoqCnstQueueDebugBus_47_24__I1_QueueRts_R2_MASK 0x00000020L -#define CPF_RoqCnstQueueDebugBus_47_24__I1_QueueRts_R1_MASK 0x00000040L -#define CPF_RoqCnstQueueDebugBus_47_24__I1_QueueRts_R0_MASK 0x00000080L -#define CPF_RoqCnstQueueDebugBus_47_24__Rb_QueueRts_R2_MASK 0x00000100L -#define CPF_RoqCnstQueueDebugBus_47_24__Rb_QueueRts_R1_MASK 0x00000200L -#define CPF_RoqCnstQueueDebugBus_47_24__Rb_QueueRts_R0_MASK 0x00000400L -#define CPF_RoqCnstQueueDebugBus_47_24__Reserved0_MASK 0xfffff800L - -// CPF_WrPntrPollDebugBus_31_8 -#define CPF_WrPntrPollDebugBus_31_8__qMeId_MASK 0x00000001L -#define CPF_WrPntrPollDebugBus_31_8__startPollAll_MASK 0x00000002L -#define CPF_WrPntrPollDebugBus_31_8__queueActive_MASK 0x00000004L -#define CPF_WrPntrPollDebugBus_31_8__qWptrPollBusy_MASK 0x00000008L -#define CPF_WrPntrPollDebugBus_31_8__oWPP_TC_rdreq_rts_MASK 0x00000010L -#define CPF_WrPntrPollDebugBus_31_8__iWPP_TC_rdreq_rtr_MASK 0x00000020L -#define CPF_WrPntrPollDebugBus_31_8__IncrWptrPollCount_MASK 0x00000040L -#define CPF_WrPntrPollDebugBus_31_8__TcWppTarget_MASK 0x00000080L -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollValid_MASK 0x00000100L -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollMeId_MASK 0x00000600L -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollPipeId_MASK 0x00001800L -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollQueueId_MASK 0x0000e000L -#define CPF_WrPntrPollDebugBus_31_8__qWppFifoState_MASK 0x00030000L -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoEmpty_MASK 0x00040000L -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoFull_MASK 0x00080000L -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoRdEn_MASK 0x00100000L -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoWrEn_MASK 0x00200000L -#define CPF_WrPntrPollDebugBus_31_8__qWptrPollOutstandingTagCnt_neq_1ff_MASK 0x00400000L -#define CPF_WrPntrPollDebugBus_31_8__qWptrPollOutstandingTagCnt_neq_0_MASK 0x00800000L -#define CPF_WrPntrPollDebugBus_31_8__Reserved0_MASK 0xff000000L - -// CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24 -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qInterruptVmid_3_MASK 0x00000001L -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__Reserved1_MASK 0x000000feL -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qWptrPollState_MASK 0x00000700L -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qQueueId_MASK 0x00003800L -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qPipeId_MASK 0x0000c000L -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__Reserved0_MASK 0xffff0000L - -// CPF_InterruptDebugBus_23_0 -#define CPF_InterruptDebugBus_23_0__qCP_RLC_intrequest_id4_MASK 0x000000ffL -#define CPF_InterruptDebugBus_23_0__qInterruptRequestActive_MASK 0x00000100L -#define CPF_InterruptDebugBus_23_0__qInterruptRequestId_MASK 0x00003e00L -#define CPF_InterruptDebugBus_23_0__qInterruptQueueId_MASK 0x0001c000L -#define CPF_InterruptDebugBus_23_0__qInterruptRingId_MASK 0x00060000L -#define CPF_InterruptDebugBus_23_0__qInterruptMeId_MASK 0x00180000L -#define CPF_InterruptDebugBus_23_0__qInterruptVmid_2_0_MASK 0x00e00000L -#define CPF_InterruptDebugBus_23_0__Reserved0_MASK 0xff000000L - -// CPF_InterruptDebugIntf_23_0 -#define CPF_InterruptDebugIntf_23_0__qRLC_CP_intresponse_status_MASK 0x00000001L -#define CPF_InterruptDebugIntf_23_0__qRLC_CP_intresponse_valid_MASK 0x00000002L -#define CPF_InterruptDebugIntf_23_0__qCP_RLC_intrequest_id_MASK 0x000003fcL -#define CPF_InterruptDebugIntf_23_0__qCP_RLC_intrequest_info_13_0_MASK 0x00fffc00L -#define CPF_InterruptDebugIntf_23_0__Reserved0_MASK 0xff000000L - -// CPF_InterruptDebugIntf_47_24 -#define CPF_InterruptDebugIntf_47_24__qCP_RLC_intrequest_info_37_14_MASK 0x00ffffffL -#define CPF_InterruptDebugIntf_47_24__Reserved0_MASK 0xff000000L - -// CPF_InterruptDebugIntf_58_48 -#define CPF_InterruptDebugIntf_58_48__qCP_RLC_intrequest_info_47_38_MASK 0x000003ffL -#define CPF_InterruptDebugIntf_58_48__qCP_RLC_intrequest_valid_MASK 0x00000400L -#define CPF_InterruptDebugIntf_58_48__Reserved0_MASK 0xfffff800L - -// CPF_RciuDebugBus -#define CPF_RciuDebugBus__qCpfSendCntUnderflow_MASK 0x00000001L -#define CPF_RciuDebugBus__qCpfSendCntOverflow_MASK 0x00000002L -#define CPF_RciuDebugBus__CpfRciuFifoFull_MASK 0x00000004L -#define CPF_RciuDebugBus__CpfRciuFreeFifoEmpty_MASK 0x00000010L -#define CPF_RciuDebugBus__CpfRciuFreeFifoFull_MASK 0x00000020L -#define CPF_RciuDebugBus__SendCountHitMax_MASK 0x00000040L -#define CPF_RciuDebugBus__SendCountEqZero_MASK 0x00000080L -#define CPF_RciuDebugBus__CpfGrbmFree_MASK 0x00000100L -#define CPF_RciuDebugBus__Reserved0_MASK 0xfffffe00L - -// bci_control0_dbg_bus -#define bci_control0_dbg_bus__accum_offset23_1_0_MASK 0x00000003L -#define bci_control0_dbg_bus__accum_offset01_MASK 0x0000003cL -#define bci_control0_dbg_bus__spi_interface_full_MASK 0x00000040L -#define bci_control0_dbg_bus__start_of_wave_MASK 0x00000080L -#define bci_control0_dbg_bus__bc_state_reg2_3_0_MASK 0x00000f00L -#define bci_control0_dbg_bus__bc_op_reg2_MASK 0x00003000L -#define bci_control0_dbg_bus__bc_num_reg2_MASK 0x0000c000L -#define bci_control0_dbg_bus__start_with_bank01_MASK 0x00010000L -#define bci_control0_dbg_bus__primary_bank_MASK 0x00020000L -#define bci_control0_dbg_bus__bc_state_id_MASK 0x001c0000L -#define bci_control0_dbg_bus__in_fifo_empty_MASK 0x00200000L -#define bci_control0_dbg_bus__no_outstanding_loads_MASK 0x00400000L -#define bci_control0_dbg_bus__Reserved0_MASK 0xff800000L - -// bci_control1_dbg_bus -#define bci_control1_dbg_bus__accum_offset23_1_0_MASK 0x00000003L -#define bci_control1_dbg_bus__accum_offset01_MASK 0x0000003cL -#define bci_control1_dbg_bus__spi_interface_full_MASK 0x00000040L -#define bci_control1_dbg_bus__start_of_wave_MASK 0x00000080L -#define bci_control1_dbg_bus__bc_state_reg2_3_0_MASK 0x00000f00L -#define bci_control1_dbg_bus__bc_op_reg2_MASK 0x00003000L -#define bci_control1_dbg_bus__bc_num_reg2_MASK 0x0000c000L -#define bci_control1_dbg_bus__start_with_bank01_MASK 0x00010000L -#define bci_control1_dbg_bus__primary_bank_MASK 0x00020000L -#define bci_control1_dbg_bus__bc_state_id_MASK 0x001c0000L -#define bci_control1_dbg_bus__in_fifo_empty_MASK 0x00200000L -#define bci_control1_dbg_bus__no_outstanding_loads_MASK 0x00400000L -#define bci_control1_dbg_bus__Reserved0_MASK 0xff800000L - -// bci_pipe0_dbg_bus -#define bci_pipe0_dbg_bus__bci_pipe0_fifo_empty_MASK 0x00000001L -#define bci_pipe0_dbg_bus__pipe0_fifo_re_MASK 0x00000002L -#define bci_pipe0_dbg_bus__pipe0_fifo_we_MASK 0x00000004L -#define bci_pipe0_dbg_bus__end_of_vector_MASK 0x00000008L -#define bci_pipe0_dbg_bus__stage_row_cnt_reg_MASK 0x00000030L -#define bci_pipe0_dbg_bus__row_xfer_phase_MASK 0x000000c0L -#define bci_pipe0_dbg_bus__even_odd_boundary_reg_MASK 0x00000100L -#define bci_pipe0_dbg_bus__bc_quad0_data_is_double_quad_MASK 0x00000200L -#define bci_pipe0_dbg_bus__bc_state_reg_MASK 0x00000c00L -#define bci_pipe0_dbg_bus__bc_state_id_rb_plus_MASK 0x00007000L -#define bci_pipe0_dbg_bus__in_fifo_full_MASK 0x00008000L -#define bci_pipe0_dbg_bus__in_fifo_empty_rb_plus_MASK 0x00010000L -#define bci_pipe0_dbg_bus__Reserved0_MASK 0xfffe0000L - -// bci_pipe1_dbg_bus -#define bci_pipe1_dbg_bus__bci_pipe0_fifo_empty_MASK 0x00000001L -#define bci_pipe1_dbg_bus__pipe0_fifo_re_MASK 0x00000002L -#define bci_pipe1_dbg_bus__pipe0_fifo_we_MASK 0x00000004L -#define bci_pipe1_dbg_bus__end_of_vector_MASK 0x00000008L -#define bci_pipe1_dbg_bus__stage_row_cnt_reg_MASK 0x00000030L -#define bci_pipe1_dbg_bus__row_xfer_phase_MASK 0x000000c0L -#define bci_pipe1_dbg_bus__even_odd_boundary_reg_MASK 0x00000100L -#define bci_pipe1_dbg_bus__bc_quad0_data_is_double_quad_MASK 0x00000200L -#define bci_pipe1_dbg_bus__bc_state_reg_MASK 0x00000c00L -#define bci_pipe1_dbg_bus__bc_state_id_rb_plus_MASK 0x00007000L -#define bci_pipe1_dbg_bus__in_fifo_full_MASK 0x00008000L -#define bci_pipe1_dbg_bus__in_fifo_empty_rb_plus_MASK 0x00010000L -#define bci_pipe1_dbg_bus__Reserved0_MASK 0xfffe0000L - -// RMI_DEBUGBUS_0 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID7_MASK 0x00000001L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID6_MASK 0x00000002L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID5_MASK 0x00000004L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID4_MASK 0x00000008L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID3_MASK 0x00000010L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID2_MASK 0x00000020L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID1_MASK 0x00000040L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID0_MASK 0x00000080L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID_ALL_MASK 0x00000100L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID15_MASK 0x00000200L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID14_MASK 0x00000400L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID13_MASK 0x00000800L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID12_MASK 0x00001000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID11_MASK 0x00002000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID10_MASK 0x00004000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID9_MASK 0x00008000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID8_MASK 0x00010000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID7_MASK 0x00020000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID6_MASK 0x00040000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID5_MASK 0x00080000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID4_MASK 0x00100000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID3_MASK 0x00200000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID2_MASK 0x00400000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID1_MASK 0x00800000L -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID0_MASK 0x01000000L -#define RMI_DEBUGBUS_0__EVENT_SEND0_MASK 0x02000000L -#define RMI_DEBUGBUS_0__PERF_WINDOW0_MASK 0x04000000L -#define RMI_DEBUGBUS_0__DYN_CLK_PERF_VLD_MASK 0x08000000L -#define RMI_DEBUGBUS_0__DYN_CLK_RB0_VLD_MASK 0x10000000L -#define RMI_DEBUGBUS_0__DYN_CLK_CMN_VLD_MASK 0x20000000L -#define RMI_DEBUGBUS_0__REG_CLK_VLD_MASK 0x40000000L -#define RMI_DEBUGBUS_0__BUSY_MASK 0x80000000L - -// RMI_DEBUGBUS_1 -#define RMI_DEBUGBUS_1__RB0_RMI_RDREQ_BUSY_MASK 0x00000001L -#define RMI_DEBUGBUS_1__RB0_RMI_RDREQ_ALL_CID_MASK 0x00000002L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID7_MASK 0x00000004L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID6_MASK 0x00000008L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID5_MASK 0x00000010L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID4_MASK 0x00000020L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID3_MASK 0x00000040L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID2_MASK 0x00000080L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID1_MASK 0x00000100L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID0_MASK 0x00000200L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_BUSY_MASK 0x00000400L -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_ALL_CID_MASK 0x00000800L -#define RMI_DEBUGBUS_1__UTCL1_STALL_MULTI_MISS_MASK 0x00001000L -#define RMI_DEBUGBUS_1__UTCL1_HIT_FIFO_FULL_MASK 0x00002000L -#define RMI_DEBUGBUS_1__UTCL1_STALL_MISSFIFO_FULL_MASK 0x00004000L -#define RMI_DEBUGBUS_1__UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_MASK 0x00008000L -#define RMI_DEBUGBUS_1__UTCL1_STALL_LFIFO_NOT_RES0_MASK 0x00010000L -#define RMI_DEBUGBUS_1__UTCL1_LFIFO_FULL_MASK 0x00020000L -#define RMI_DEBUGBUS_1__UTCL1_STALL_LRU_INFLIGHT_MASK 0x00040000L -#define RMI_DEBUGBUS_1__UTCL1_STALL_INFLIGHT_MAX_MASK 0x00080000L -#define RMI_DEBUGBUS_1__UTCL1_REQUEST0_MASK 0x00100000L -#define RMI_DEBUGBUS_1__UTCL1_PERMISSION_MISS_MASK 0x00200000L -#define RMI_DEBUGBUS_1__UTCL1_TRANSLATION_MISS_MASK 0x00400000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL_MASK 0x00800000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID15_MASK 0x01000000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID14_MASK 0x02000000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID13_MASK 0x04000000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID12_MASK 0x08000000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID11_MASK 0x10000000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID10_MASK 0x20000000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID9_MASK 0x40000000L -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID8_MASK 0x80000000L - -// RMI_DEBUGBUS_2 -#define RMI_DEBUGBUS_2__RMI_UTC_REQ0_MASK 0x00000001L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK3_MASK 0x00000002L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK2_MASK 0x00000004L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK1_MASK 0x00000008L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK0_MASK 0x00000010L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID7_MASK 0x00000020L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID6_MASK 0x00000040L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID5_MASK 0x00000080L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID4_MASK 0x00000100L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID3_MASK 0x00000200L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID2_MASK 0x00000400L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID1_MASK 0x00000800L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID0_MASK 0x00001000L -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID_MASK 0x0007e000L -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_ALL_CID_MASK 0x00080000L -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_RESIDENCY_MASK 0x00100000L -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_BURST_ALL_ORONE_CID_MASK 0x00200000L -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID_MASK 0xffc00000L - -// RMI_DEBUGBUS_3 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID7_MASK 0x0000000fL -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID6_MASK 0x000000f0L -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID5_MASK 0x00000f00L -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID4_MASK 0x0000f000L -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID3_MASK 0x000f0000L -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID2_MASK 0x00f00000L -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID1_MASK 0x0f000000L -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID0_MASK 0xf0000000L - -// RMI_DEBUGBUS_4 -#define RMI_DEBUGBUS_4__RMI_UTC_BUSY0_MASK 0x00000001L -#define RMI_DEBUGBUS_4__RMI_RB0_32BRDRET_VALID_ALL_CID_MASK 0x00000002L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_RESIDENCY_MASK 0x00000004L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_BURST_ALL_ORONE_CID_MASK 0x00000008L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID_MASK 0x000003f0L -#define RMI_DEBUGBUS_4__RB0_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID_MASK 0x000ffc00L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID7_MASK 0x00100000L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID6_MASK 0x00200000L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID5_MASK 0x00400000L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID4_MASK 0x00800000L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID3_MASK 0x01000000L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID2_MASK 0x02000000L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID1_MASK 0x04000000L -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID0_MASK 0x08000000L -#define RMI_DEBUGBUS_4__RB0_RMI_32BRDREQ_ALL_CID_MASK 0xf0000000L - -// RMI_DEBUGBUS_5 -#define RMI_DEBUGBUS_5__RMI0_TC_RDREQ_ALL_CID_MASK 0x00000001L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_INFLIGHT_ALL_CID_MASK 0x000003feL -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID7_MASK 0x00000400L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID6_MASK 0x00000800L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID5_MASK 0x00001000L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID4_MASK 0x00002000L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID3_MASK 0x00004000L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID2_MASK 0x00008000L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID1_MASK 0x00010000L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID0_MASK 0x00020000L -#define RMI_DEBUGBUS_5__RMI0_TC_REQ_BUSY_MASK 0x00040000L -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_ALL_CID_MASK 0x00080000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK3_MASK 0x00100000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK2_MASK 0x00200000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK1_MASK 0x00400000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK0_MASK 0x00800000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID7_MASK 0x01000000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID6_MASK 0x02000000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID5_MASK 0x04000000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID4_MASK 0x08000000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID3_MASK 0x10000000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID2_MASK 0x20000000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID1_MASK 0x40000000L -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID0_MASK 0x80000000L - -// RMI_DEBUGBUS_6 -#define RMI_DEBUGBUS_6__XNACK_FIFO_FULL_MASK 0x00000001L -#define RMI_DEBUGBUS_6__XNACK_FIFO_NUM_USED_MASK 0x000003feL -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_XNACK_NORETRY_FAULT_MASK 0x00000400L -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_PRT_FAULT_MASK 0x00000800L -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_ALL_FAULT_MASK 0x00001000L -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_XNACK_RETRY_MASK 0x00002000L -#define RMI_DEBUGBUS_6__TC_RMI0_RDRET_VALID_ALL_CID_MASK 0x00004000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_INFLIGHT_ALL_CID_MASK 0x00ff8000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID7_MASK 0x01000000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID6_MASK 0x02000000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID5_MASK 0x04000000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID4_MASK 0x08000000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID3_MASK 0x10000000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID2_MASK 0x20000000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID1_MASK 0x40000000L -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID0_MASK 0x80000000L - -// RMI_DEBUGBUS_7 -#define RMI_DEBUGBUS_7__DEMUX_TCIW_FORMATTER0_RTS_RTRB_MASK 0x00000001L -#define RMI_DEBUGBUS_7__DEMUX_TCIW_FORMATTER0_RTSB_RTR_MASK 0x00000002L -#define RMI_DEBUGBUS_7__DEMUX_TCIW_FORMATTER0_RTS_RTR_MASK 0x00000004L -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTSB_RTRB_MASK 0x00000008L -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTS_RTRB_MASK 0x00000020L -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTSB_RTR_MASK 0x00000040L -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTS_RTR_MASK 0x00000080L -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK3_MASK 0x00000100L -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK2_MASK 0x00000200L -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK1_MASK 0x00000400L -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK0_MASK 0x00000800L -#define RMI_DEBUGBUS_7__TC_RMI0_WRRET_VALID_ALL_CID_MASK 0x00001000L -#define RMI_DEBUGBUS_7__SKID_FIFO_0_BUSY_MASK 0x00002000L -#define RMI_DEBUGBUS_7__SKID_FIFO_0_REQ_MASK 0x00004000L -#define RMI_DEBUGBUS_7__TCIW0_BUSY_MASK 0x00008000L -#define RMI_DEBUGBUS_7__TCIW0_REQ_MASK 0x00010000L -#define RMI_DEBUGBUS_7__PRT_FIFO_0_BUSY_MASK 0x00020000L -#define RMI_DEBUGBUS_7__PRT_FIFO_0_REQ_MASK 0x00040000L -#define RMI_DEBUGBUS_7__XNACK_FIFO_BUSY_MASK 0x00080000L -#define RMI_DEBUGBUS_7__LAT_FIFO_0_FULL_MASK 0x00100000L -#define RMI_DEBUGBUS_7__LAT_FIFO_0_NONBLOCKING_REQ_MASK 0x00200000L -#define RMI_DEBUGBUS_7__LAT_FIFO_0_BLOCKING_REQ_MASK 0x00400000L -#define RMI_DEBUGBUS_7__LAT_FIFO_0_NUM_USED_MASK 0x3f800000L -#define RMI_DEBUGBUS_7__UTCL1_UTCL2_REQ_MASK 0x40000000L -#define RMI_DEBUGBUS_7__UTCL1_BUSY_MASK 0x80000000L - -// RMI_DEBUGBUS_8 -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTSB_RTRB_MASK 0x00000001L -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTS_RTRB_MASK 0x00000002L -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTSB_RTR_MASK 0x00000004L -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTS_RTR_MASK 0x00000008L -#define RMI_DEBUGBUS_8__DEMUX_TCIW_FORMATTER0_RTSB_RTRB_MASK 0x00000010L -#define RMI_DEBUGBUS_8__PRT_FIFO_0_NUM_USED_MASK 0x00003fe0L -#define RMI_DEBUGBUS_8__TCIW0_INFLIGHT_COUNT_MASK 0x007fc000L -#define RMI_DEBUGBUS_8__SKID_FIFO_0_DEPTH_MASK 0xff800000L - -// RMI_DEBUGBUS_9 -#define RMI_DEBUGBUS_9__SKID_FIFO_0_OUT_RTSB_MASK 0x00000001L -#define RMI_DEBUGBUS_9__SKID_FIFO_0_OUT_RTS_MASK 0x00000002L -#define RMI_DEBUGBUS_9__SKID_FIFO_0_IN_RTSB_MASK 0x00000004L -#define RMI_DEBUGBUS_9__SKID_FIFO_0_IN_RTS_MASK 0x00000008L -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTSB_RTRB_MASK 0x00000010L -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTS_RTRB_MASK 0x00000020L -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTSB_RTR_MASK 0x00000040L -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTS_RTR_MASK 0x00000080L -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTSB_RTRB_MASK 0x00000100L -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTS_RTRB_MASK 0x00000200L -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTSB_RTR_MASK 0x00000400L -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTS_RTR_MASK 0x00000800L -#define RMI_DEBUGBUS_9__POP0_XNACK_RTSB_RTRB_MASK 0x00001000L -#define RMI_DEBUGBUS_9__POP0_XNACK_RTS_RTRB_MASK 0x00002000L -#define RMI_DEBUGBUS_9__POP0_XNACK_RTSB_RTR_MASK 0x00004000L -#define RMI_DEBUGBUS_9__POP0_XNACK_RTS_RTR_MASK 0x00008000L -#define RMI_DEBUGBUS_9__UTC_POP0_RTSB_RTRB_MASK 0x00010000L -#define RMI_DEBUGBUS_9__UTC_POP0_RTS_RTRB_MASK 0x00020000L -#define RMI_DEBUGBUS_9__UTC_POP0_RTSB_RTR_MASK 0x00040000L -#define RMI_DEBUGBUS_9__UTC_POP0_RTS_RTR_MASK 0x00080000L -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTSB_RTRB_MASK 0x00100000L -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTS_RTRB_MASK 0x00200000L -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTSB_RTR_MASK 0x00400000L -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTS_RTR_MASK 0x00800000L -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTSB_RTRB_MASK 0x01000000L -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTS_RTRB_MASK 0x02000000L -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTSB_RTR_MASK 0x04000000L -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTS_RTR_MASK 0x08000000L -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTSB_RTRB_MASK 0x10000000L -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTS_RTRB_MASK 0x20000000L -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTSB_RTR_MASK 0x40000000L -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTS_RTR_MASK 0x80000000L - -// RMI_DEBUGBUS_10 -#define RMI_DEBUGBUS_10__UTCL1_STALL_LFIFO_NOT_RES1_MASK 0x00000001L -#define RMI_DEBUGBUS_10__RB1_RMI_RDREQ_BUSY_MASK 0x00000002L -#define RMI_DEBUGBUS_10__RB1_RMI_RDREQ_ALL_CID_MASK 0x00000004L -#define RMI_DEBUGBUS_10__RB1_RMI_WRREQ_BUSY_MASK 0x00000008L -#define RMI_DEBUGBUS_10__RB1_RMI_WRREQ_ALL_CID_MASK 0x00000010L -#define RMI_DEBUGBUS_10__UTCL1_REQUEST1_MASK 0x00000020L -#define RMI_DEBUGBUS_10__EVENT_SEND1_MASK 0x00000040L -#define RMI_DEBUGBUS_10__PERF_WINDOW1_MASK 0x00000080L -#define RMI_DEBUGBUS_10__DYN_CLK_RB1_VLD_MASK 0x00000100L -#define RMI_DEBUGBUS_10__PROBE0_UTCL1_VMID_BYPASS_MASK 0x00000200L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK3_MASK 0x00000400L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK2_MASK 0x00000800L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK1_MASK 0x00001000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK0_MASK 0x00002000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID7_MASK 0x00004000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID6_MASK 0x00008000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID5_MASK 0x00010000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID4_MASK 0x00020000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID3_MASK 0x00040000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID2_MASK 0x00080000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID1_MASK 0x00100000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID0_MASK 0x00200000L -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_ALL_CID_MASK 0x00400000L -#define RMI_DEBUGBUS_10__REORDER_FIFO_0_BUSY_MASK 0x00800000L -#define RMI_DEBUGBUS_10__REORDER_FIFO_0_REQ_MASK 0x01000000L -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_DB_RTS_RTR_MASK 0x02000000L -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_CB_RTS_RTR_MASK 0x04000000L -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_IN1_RTS_RTR_MASK 0x08000000L -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_IN0_RTS_RTR_MASK 0x10000000L -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_WRITE_RTS_RTR_MASK 0x20000000L -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_READ_RTS_RTR_MASK 0x40000000L -#define RMI_DEBUGBUS_10__RESERVED0_MASK 0x80000000L - -// RMI_DEBUGBUS_11 -#define RMI_DEBUGBUS_11__RMI_UTC_REQ1_MASK 0x00000001L -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK3_MASK 0x00000002L -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK2_MASK 0x00000004L -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK1_MASK 0x00000008L -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK0_MASK 0x00000010L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID_MASK 0x000007e0L -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_ALL_CID_MASK 0x00000800L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_RESIDENCY_MASK 0x00001000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_BURST_ALL_ORONE_CID_MASK 0x00002000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID_MASK 0x00ffc000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID7_MASK 0x01000000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID6_MASK 0x02000000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID5_MASK 0x04000000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID4_MASK 0x08000000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID3_MASK 0x10000000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID2_MASK 0x20000000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID1_MASK 0x40000000L -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID0_MASK 0x80000000L - -// RMI_DEBUGBUS_12 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID7_MASK 0x0000000fL -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID6_MASK 0x000000f0L -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID5_MASK 0x00000f00L -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID4_MASK 0x0000f000L -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID3_MASK 0x000f0000L -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID2_MASK 0x00f00000L -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID1_MASK 0x0f000000L -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID0_MASK 0xf0000000L - -// RMI_DEBUGBUS_13 -#define RMI_DEBUGBUS_13__RMI_UTC_BUSY1_MASK 0x00000001L -#define RMI_DEBUGBUS_13__RMI_RB1_32BRDRET_VALID_ALL_CID_MASK 0x00000002L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_RESIDENCY_MASK 0x00000004L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_BURST_ALL_ORONE_CID_MASK 0x00000008L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID_MASK 0x000003f0L -#define RMI_DEBUGBUS_13__RB1_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID_MASK 0x000ffc00L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID7_MASK 0x00100000L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID6_MASK 0x00200000L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID5_MASK 0x00400000L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID4_MASK 0x00800000L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID3_MASK 0x01000000L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID2_MASK 0x02000000L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID1_MASK 0x04000000L -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID0_MASK 0x08000000L -#define RMI_DEBUGBUS_13__RB1_RMI_32BRDREQ_ALL_CID_MASK 0xf0000000L - -// RMI_DEBUGBUS_14 -#define RMI_DEBUGBUS_14__RMI1_TC_RDREQ_ALL_CID_MASK 0x00000001L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_INFLIGHT_ALL_CID_MASK 0x000003feL -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID7_MASK 0x00000400L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID6_MASK 0x00000800L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID5_MASK 0x00001000L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID4_MASK 0x00002000L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID3_MASK 0x00004000L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID2_MASK 0x00008000L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID1_MASK 0x00010000L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID0_MASK 0x00020000L -#define RMI_DEBUGBUS_14__RMI1_TC_REQ_BUSY_MASK 0x00040000L -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_ALL_CID_MASK 0x00080000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK3_MASK 0x00100000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK2_MASK 0x00200000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK1_MASK 0x00400000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK0_MASK 0x00800000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID7_MASK 0x01000000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID6_MASK 0x02000000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID5_MASK 0x04000000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID4_MASK 0x08000000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID3_MASK 0x10000000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID2_MASK 0x20000000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID1_MASK 0x40000000L -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID0_MASK 0x80000000L - -// RMI_DEBUGBUS_15 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID7_MASK 0x00000001L -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID6_MASK 0x00000002L -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID5_MASK 0x00000004L -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID4_MASK 0x00000008L -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID3_MASK 0x00000010L -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID2_MASK 0x00000020L -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID1_MASK 0x00000040L -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID0_MASK 0x00000080L -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_XNACK_NORETRY_FAULT_MASK 0x00000100L -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_PRT_FAULT_MASK 0x00000200L -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_ALL_FAULT_MASK 0x00000400L -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_XNACK_RETRY_MASK 0x00000800L -#define RMI_DEBUGBUS_15__RESERVED0_MASK 0x00001000L -#define RMI_DEBUGBUS_15__TC_RMI1_RDRET_VALID_ALL_CID_MASK 0x00006000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_INFLIGHT_ALL_CID_MASK 0x00ff8000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID7_MASK 0x01000000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID6_MASK 0x02000000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID5_MASK 0x04000000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID4_MASK 0x08000000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID3_MASK 0x10000000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID2_MASK 0x20000000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID1_MASK 0x40000000L -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID0_MASK 0x80000000L - -// RMI_DEBUGBUS_16 -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTSB_RTRB_MASK 0x00000001L -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTS_RTRB_MASK 0x00000002L -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTSB_RTR_MASK 0x00000004L -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTS_RTR_MASK 0x00000008L -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTSB_RTRB_MASK 0x00000010L -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTS_RTRB_MASK 0x00000020L -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTSB_RTR_MASK 0x00000040L -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTS_RTR_MASK 0x00000080L -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK3_MASK 0x00000100L -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK2_MASK 0x00000200L -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK1_MASK 0x00000400L -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK0_MASK 0x00000800L -#define RMI_DEBUGBUS_16__TC_RMI1_WRRET_VALID_ALL_CID_MASK 0x00003000L -#define RMI_DEBUGBUS_16__SKID_FIFO_1_BUSY_MASK 0x00004000L -#define RMI_DEBUGBUS_16__SKID_FIFO_1_REQ_MASK 0x00008000L -#define RMI_DEBUGBUS_16__TCIW1_BUSY_MASK 0x00010000L -#define RMI_DEBUGBUS_16__TCIW1_REQ_MASK 0x00020000L -#define RMI_DEBUGBUS_16__PRT_FIFO_1_BUSY_MASK 0x00040000L -#define RMI_DEBUGBUS_16__PRT_FIFO_1_REQ_MASK 0x00080000L -#define RMI_DEBUGBUS_16__LAT_FIFO_1_FULL_MASK 0x00100000L -#define RMI_DEBUGBUS_16__SKID_FIFO_1_OUT_RTSB_MASK 0x00200000L -#define RMI_DEBUGBUS_16__SKID_FIFO_1_OUT_RTS_MASK 0x00400000L -#define RMI_DEBUGBUS_16__LAT_FIFO_1_NONBLOCKING_REQ_MASK 0x00800000L -#define RMI_DEBUGBUS_16__LAT_FIFO_1_BLOCKING_REQ_MASK 0x01000000L -#define RMI_DEBUGBUS_16__LAT_FIFO_1_NUM_USED_MASK 0xfe000000L - -// RMI_DEBUGBUS_17 -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTSB_RTRB_MASK 0x00000001L -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTS_RTRB_MASK 0x00000002L -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTSB_RTR_MASK 0x00000004L -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTS_RTR_MASK 0x00000008L -#define RMI_DEBUGBUS_17__RESERVED0_MASK 0x00000010L -#define RMI_DEBUGBUS_17__PRT_FIFO_1_NUM_USED_MASK 0x00003fe0L -#define RMI_DEBUGBUS_17__TCIW1_INFLIGHT_COUNT_MASK 0x007fc000L -#define RMI_DEBUGBUS_17__SKID_FIFO_1_DEPTH_MASK 0xff800000L - -// RMI_DEBUGBUS_18 -#define RMI_DEBUGBUS_18__RESERVED0_MASK 0x00000003L -#define RMI_DEBUGBUS_18__SKID_FIFO_1_IN_RTSB_MASK 0x00000004L -#define RMI_DEBUGBUS_18__SKID_FIFO_1_IN_RTS_MASK 0x00000008L -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTSB_RTRB_MASK 0x00000010L -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTS_RTRB_MASK 0x00000020L -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTSB_RTR_MASK 0x00000040L -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTS_RTR_MASK 0x00000080L -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTSB_RTRB_MASK 0x00000100L -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTS_RTRB_MASK 0x00000200L -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTSB_RTR_MASK 0x00000400L -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTS_RTR_MASK 0x00000800L -#define RMI_DEBUGBUS_18__POP1_XNACK_RTSB_RTRB_MASK 0x00001000L -#define RMI_DEBUGBUS_18__POP1_XNACK_RTS_RTRB_MASK 0x00002000L -#define RMI_DEBUGBUS_18__POP1_XNACK_RTSB_RTR_MASK 0x00004000L -#define RMI_DEBUGBUS_18__POP1_XNACK_RTS_RTR_MASK 0x00008000L -#define RMI_DEBUGBUS_18__UTC_POP1_RTSB_RTRB_MASK 0x00010000L -#define RMI_DEBUGBUS_18__UTC_POP1_RTS_RTRB_MASK 0x00020000L -#define RMI_DEBUGBUS_18__UTC_POP1_RTSB_RTR_MASK 0x00040000L -#define RMI_DEBUGBUS_18__UTC_POP1_RTS_RTR_MASK 0x00080000L -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTSB_RTRB_MASK 0x00100000L -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTS_RTRB_MASK 0x00200000L -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTSB_RTR_MASK 0x00400000L -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTS_RTR_MASK 0x00800000L -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTSB_RTRB_MASK 0x01000000L -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTS_RTRB_MASK 0x02000000L -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTSB_RTR_MASK 0x04000000L -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTS_RTR_MASK 0x08000000L -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTSB_RTRB_MASK 0x10000000L -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTS_RTRB_MASK 0x20000000L -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTSB_RTR_MASK 0x40000000L -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTS_RTR_MASK 0x80000000L - -// RMI_DEBUGBUS_19 -#define RMI_DEBUGBUS_19__Reserved0_MASK 0x000003ffL -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK3_MASK 0x00000400L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK2_MASK 0x00000800L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK1_MASK 0x00001000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK0_MASK 0x00002000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID7_MASK 0x00004000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID6_MASK 0x00008000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID5_MASK 0x00010000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID4_MASK 0x00020000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID3_MASK 0x00040000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID2_MASK 0x00080000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID1_MASK 0x00100000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID0_MASK 0x00200000L -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_ALL_CID_EVENT_MASK 0x00400000L -#define RMI_DEBUGBUS_19__REORDER_FIFO_1_BUSY_MASK 0x00800000L -#define RMI_DEBUGBUS_19__REORDER_FIFO_1_REQ_MASK 0x01000000L -#define RMI_DEBUGBUS_19__PROBE1_UTCL1_VMID_BYPASS_MASK 0x02000000L -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_DB_RTS_RTR_MASK 0x04000000L -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_CB_RTS_RTR_MASK 0x08000000L -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_IN1_RTS_RTR_MASK 0x10000000L -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_IN0_RTS_RTR_MASK 0x20000000L -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_WRITE_RTS_RTR_MASK 0x40000000L -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_READ_RTS_RTR_MASK 0x80000000L - -// RMI_DEBUGBUS_20 -#define RMI_DEBUGBUS_20__RB0_WRREQ_CONSUMER_FIFO_EMPTY_MASK 0x00000001L -#define RMI_DEBUGBUS_20__RB0_RDREQ_CONSUMER_FIFO_EMPTY_MASK 0x00000002L -#define RMI_DEBUGBUS_20__RB0_WRREQ_CONSUMER_FIFO_FULL_MASK 0x00000004L -#define RMI_DEBUGBUS_20__RB0_RDREQ_CONSUMER_FIFO_FULL_MASK 0x00000008L -#define RMI_DEBUGBUS_20__RB0_WRREQ_CONSUMER_FIFO_BUSY_MASK 0x00000010L -#define RMI_DEBUGBUS_20__RB0_RDREQ_CONSUMER_FIFO_BUSY_MASK 0x00000020L -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000040L -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L -#define RMI_DEBUGBUS_20__XNACK_FIFO_EMPTY_MASK 0x00000100L -#define RMI_DEBUGBUS_20__XNACK_FIFO_FULL_MASK 0x00000200L -#define RMI_DEBUGBUS_20__UTCL1_STALL_MISSFIFO_FULL_EVENT_MASK 0x00000400L -#define RMI_DEBUGBUS_20__UTCL1_STALL_INFLIGHT_MAX_EVENT_MASK 0x00000800L -#define RMI_DEBUGBUS_20__UTCL1_STALL_LRU_INFLIGHT_EVENT_MASK 0x00001000L -#define RMI_DEBUGBUS_20__UTCL1_LFIFO_FULL_EVENT_MASK 0x00002000L -#define RMI_DEBUGBUS_20__UTCL1_HIT_FIFO_FULL_EVENT_MASK 0x00004000L -#define RMI_DEBUGBUS_20__UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_EVENT_MASK 0x00008000L -#define RMI_DEBUGBUS_20__UTCL1_STALL_LFIFO_NOT_RES_EVENT_MASK 0x00010000L -#define RMI_DEBUGBUS_20__RB1_WRREQ_CONSUMER_FIFO_EMPTY_MASK 0x00020000L -#define RMI_DEBUGBUS_20__RB1_RDREQ_CONSUMER_FIFO_EMPTY_MASK 0x00040000L -#define RMI_DEBUGBUS_20__RB1_WRREQ_CONSUMER_FIFO_FULL_MASK 0x00080000L -#define RMI_DEBUGBUS_20__RB1_RDREQ_CONSUMER_FIFO_FULL_MASK 0x00100000L -#define RMI_DEBUGBUS_20__RB1_WRREQ_CONSUMER_FIFO_BUSY_MASK 0x00200000L -#define RMI_DEBUGBUS_20__RB1_RDREQ_CONSUMER_FIFO_BUSY_MASK 0x00400000L -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00800000L -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x01000000L -#define RMI_DEBUGBUS_20__UTC_OUT_STALL_SOURCE_MASK 0x0e000000L -#define RMI_DEBUGBUS_20__UTC_IN_STALL_SOURCE_MASK 0x70000000L -#define RMI_DEBUGBUS_20__UTCL1_INFLIGHT_WATERMARK_HIT_MASK 0x80000000L - -// RMI_DEBUGBUS_21 -#define RMI_DEBUGBUS_21__TCIW0_PRODUCER_CREDIT_CNT_MASK 0x0000003fL -#define RMI_DEBUGBUS_21__TCIW1_PRODUCER_CREDIT_CNT_MASK 0x00000fc0L -#define RMI_DEBUGBUS_21__POP0_DEMUX_RTR_MASK 0x00001000L -#define RMI_DEBUGBUS_21__POP0_DEMUX_RTS_MASK 0x00002000L -#define RMI_DEBUGBUS_21__POP1_DEMUX_RTR_MASK 0x00004000L -#define RMI_DEBUGBUS_21__POP1_DEMUX_RTS_MASK 0x00008000L -#define RMI_DEBUGBUS_21__RB0RDREQCONSUMER_XBAR_RDREQ_RTR_MASK 0x00010000L -#define RMI_DEBUGBUS_21__RB0RDREQCONSUMER_XBAR_RDREQ_RTS_MASK 0x00020000L -#define RMI_DEBUGBUS_21__RB0WRREQCONSUMER_XBAR_WRREQ_RTR_MASK 0x00040000L -#define RMI_DEBUGBUS_21__RB0WRREQCONSUMER_XBAR_WRREQ_RTS_MASK 0x00080000L -#define RMI_DEBUGBUS_21__RB1RDREQCONSUMER_XBAR_RDREQ_RTR_MASK 0x00100000L -#define RMI_DEBUGBUS_21__RB1RDREQCONSUMER_XBAR_RDREQ_RTS_MASK 0x00200000L -#define RMI_DEBUGBUS_21__RB1WRREQCONSUMER_XBAR_WRREQ_RTR_MASK 0x00400000L -#define RMI_DEBUGBUS_21__RB1WRREQCONSUMER_XBAR_WRREQ_RTS_MASK 0x00800000L -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER0_RTR_MASK 0x01000000L -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER0_RTS_MASK 0x02000000L -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER1_RTR_MASK 0x04000000L -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER1_RTS_MASK 0x08000000L -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN0_RTR_MASK 0x10000000L -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN0_RTS_MASK 0x20000000L -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN1_RTR_MASK 0x40000000L -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN1_RTS_MASK 0x80000000L - -// RMI_DEBUGBUS_22 -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO0_F1_MASK 0x000000ffL -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO0_F2_MASK 0x0000ff00L -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO1_F1_MASK 0x00ff0000L -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO1_F2_MASK 0xff000000L - -// RMI_DEBUGBUS_23 -#define RMI_DEBUGBUS_23__ARBITER0_REQ_OUT_DATA_FLOPPED_EN_MASK 0x00000001L -#define RMI_DEBUGBUS_23__ARBITER0_REQ_OUT_RTS_MASK 0x00000002L -#define RMI_DEBUGBUS_23__ARBITER0_GATED_BY_WEIGHTEDRR_MASK 0x00000004L -#define RMI_DEBUGBUS_23__ARBITER0_WAITING_FOR_END_OF_BURST_MASK 0x00000008L -#define RMI_DEBUGBUS_23__ARBITER0_MASKED_REQUESTS_FOR_WRAPPING_REDUCED_MASK 0x00000010L -#define RMI_DEBUGBUS_23__ARBITER0_MASKED_REQUESTS_REDUCED_MASK 0x00000020L -#define RMI_DEBUGBUS_23__ARBITER0_REQ_OUT_STALLED_MASK 0x00000040L -#define RMI_DEBUGBUS_23__ARBITER0_ARBITER_DISABLE_D_MASK 0x00000080L -#define RMI_DEBUGBUS_23__ARBITER0_OUTPUT_STALLED_MASK 0x00000100L -#define RMI_DEBUGBUS_23__ARBITER0_CURRENT_REQUEST_ID_MASK 0x00000200L -#define RMI_DEBUGBUS_23__ARBITER0_REQ_IN_RTR_FSM_MASK 0x00000c00L -#define RMI_DEBUGBUS_23__ARBITER0_REQUEST_MASKS_MASK 0x00003000L -#define RMI_DEBUGBUS_23__Reserved0_MASK 0xffffc000L - -// RMI_DEBUGBUS_24 -#define RMI_DEBUGBUS_24__ARBITER1_REQ_OUT_DATA_FLOPPED_EN_MASK 0x00000001L -#define RMI_DEBUGBUS_24__ARBITER1_REQ_OUT_RTS_MASK 0x00000002L -#define RMI_DEBUGBUS_24__ARBITER1_GATED_BY_WEIGHTEDRR_MASK 0x00000004L -#define RMI_DEBUGBUS_24__ARBITER1_WAITING_FOR_END_OF_BURST_MASK 0x00000008L -#define RMI_DEBUGBUS_24__ARBITER1_MASKED_REQUESTS_FOR_WRAPPING_REDUCED_MASK 0x00000010L -#define RMI_DEBUGBUS_24__ARBITER1_MASKED_REQUESTS_REDUCED_MASK 0x00000020L -#define RMI_DEBUGBUS_24__ARBITER1_REQ_OUT_STALLED_MASK 0x00000040L -#define RMI_DEBUGBUS_24__ARBITER1_ARBITER_DISABLE_D_MASK 0x00000080L -#define RMI_DEBUGBUS_24__ARBITER1_OUTPUT_STALLED_MASK 0x00000100L -#define RMI_DEBUGBUS_24__ARBITER1_CURRENT_REQUEST_ID_MASK 0x00000200L -#define RMI_DEBUGBUS_24__ARBITER1_REQ_IN_RTR_FSM_MASK 0x00000c00L -#define RMI_DEBUGBUS_24__ARBITER1_REQUEST_MASKS_MASK 0x00003000L -#define RMI_DEBUGBUS_24__XBAR_CONFIG_OVERRIDE_DB_MASK 0x00004000L -#define RMI_DEBUGBUS_24__XBAR_ARBITER_DISABLE_INT_MASK 0x00008000L -#define RMI_DEBUGBUS_24__Reserved0_MASK 0xffff0000L - -// RMI_DEBUGBUS_25 -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_REENABLE_INPUT_RB0_MASK 0x00000001L -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_FLUSH_START_RB0_MASK 0x00000002L -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_REENABLE_INPUT_RB1_MASK 0x00000004L -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_FLUSH_START_RB1_MASK 0x00000008L -#define RMI_DEBUGBUS_25__RB0RDREQCONSUMER_XBAR_RDREQ_RTR_PROBE0_MASK 0x00000010L -#define RMI_DEBUGBUS_25__RB0WRREQCONSUMER_XBAR_WRREQ_RTR_PROBE0_MASK 0x00000020L -#define RMI_DEBUGBUS_25__RB1RDREQCONSUMER_XBAR_RDREQ_RTR_PROBE0_MASK 0x00000040L -#define RMI_DEBUGBUS_25__RB1WRREQCONSUMER_XBAR_WRREQ_RTR_PROBE0_MASK 0x00000080L -#define RMI_DEBUGBUS_25__RB1_WR_RTS_ARBITER_PROBE1_MASK 0x00000100L -#define RMI_DEBUGBUS_25__RB1_RD_RTS_ARBITER_PROBE1_MASK 0x00000200L -#define RMI_DEBUGBUS_25__RB0_WR_RTS_ARBITER_PROBE1_MASK 0x00000400L -#define RMI_DEBUGBUS_25__RB0_RD_RTS_ARBITER_PROBE1_MASK 0x00000800L -#define RMI_DEBUGBUS_25__RB1RDREQCONSUMER_XBAR_RDREQ_LAST_OF_REQ_BURST_MASK 0x00001000L -#define RMI_DEBUGBUS_25__RB0RDREQCONSUMER_XBAR_RDREQ_LAST_OF_REQ_BURST_MASK 0x00002000L -#define RMI_DEBUGBUS_25__RB0WRREQCONSUMER_XBAR_WRREQ_LAST_OF_REQ_BURST_MASK 0x00004000L -#define RMI_DEBUGBUS_25__RB1WRREQCONSUMER_XBAR_WRREQ_LAST_OF_REQ_BURST_MASK 0x00008000L -#define RMI_DEBUGBUS_25__RB0_WR_RTS_ARBITER_PROBE0_MASK 0x00010000L -#define RMI_DEBUGBUS_25__RB1_WR_RTS_ARBITER_PROBE0_MASK 0x00020000L -#define RMI_DEBUGBUS_25__RB0_RD_RTS_ARBITER_PROBE0_MASK 0x00040000L -#define RMI_DEBUGBUS_25__RB1_RD_RTS_ARBITER_PROBE0_MASK 0x00080000L -#define RMI_DEBUGBUS_25__RB0_WR_SEL_MASK 0x00100000L -#define RMI_DEBUGBUS_25__RB1_WR_SEL_MASK 0x00200000L -#define RMI_DEBUGBUS_25__RB0_RD_SEL_MASK 0x00400000L -#define RMI_DEBUGBUS_25__RB1_RD_SEL_MASK 0x00800000L -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB0_WR_MASK 0x01000000L -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB1_WR_MASK 0x02000000L -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB0_RD_MASK 0x04000000L -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB1_RD_MASK 0x08000000L -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB0_WR_MASK 0x10000000L -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB1_WR_MASK 0x20000000L -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB0_RD_MASK 0x40000000L -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB1_RD_MASK 0x80000000L - -// RMI_DEBUGBUS_26 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_OUT_DATA_FLOPPED_EN_MASK 0x00000001L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_OUT_RTS_MASK 0x00000002L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_GATED_BY_WEIGHTEDRR_MASK 0x00000004L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_WAITING_FOR_END_OF_BURST_MASK 0x00000008L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_MASKED_REQUESTS_FOR_WRAPPING_REDUCED_MASK 0x00000010L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_MASKED_REQUESTS_REDUCED_MASK 0x00000020L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_OUT_STALLED_MASK 0x00000040L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_ARBITER_DISABLE_D_MASK 0x00000080L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_OUTPUT_STALLED_MASK 0x00000100L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_CURRENT_REQUEST_ID_MASK 0x00000200L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_IN_RTR_FSM_MASK 0x00000c00L -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQUEST_MASKS_MASK 0x00003000L -#define RMI_DEBUGBUS_26__Reserved0_MASK 0xffffc000L - -// RMI_DEBUGBUS_27 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_OUT_DATA_FLOPPED_EN_MASK 0x00000001L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_OUT_RTS_MASK 0x00000002L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_GATED_BY_WEIGHTEDRR_MASK 0x00000004L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_WAITING_FOR_END_OF_BURST_MASK 0x00000008L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_MASKED_REQUESTS_FOR_WRAPPING_REDUCED_MASK 0x00000010L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_MASKED_REQUESTS_REDUCED_MASK 0x00000020L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_OUT_STALLED_MASK 0x00000040L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_ARBITER_DISABLE_D_MASK 0x00000080L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_OUTPUT_STALLED_MASK 0x00000100L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_CURRENT_REQUEST_ID_MASK 0x00000200L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_IN_RTR_FSM_MASK 0x00000c00L -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQUEST_MASKS_MASK 0x00003000L -#define RMI_DEBUGBUS_27__Reserved0_MASK 0xffffc000L - -// RMI_DEBUGBUS_28 -#define RMI_DEBUGBUS_28__RUNNING_CNT0_MASK 0x00000fffL -#define RMI_DEBUGBUS_28__RUNNING_CNT1_MASK 0x00fff000L -#define RMI_DEBUGBUS_28__PROBE0_SB_INVREQ_CLEAN_MASK 0x01000000L -#define RMI_DEBUGBUS_28__PROBE1_SB_INVREQ_CLEAN_MASK 0x02000000L -#define RMI_DEBUGBUS_28__RMI_SCOREBOARD_CP_VMID_INVAL_PROGRESS_MASK 0x04000000L -#define RMI_DEBUGBUS_28__CPF_RMI_INVREQ_FLUSHTYPE_INT_MASK 0x08000000L -#define RMI_DEBUGBUS_28__SB_PROBE_SESSION_ID_CURR_MASK 0x10000000L -#define RMI_DEBUGBUS_28__RTNFORMATTER0_SB_SESSION_ID_MASK 0x20000000L -#define RMI_DEBUGBUS_28__RTNFORMATTER1_SB_SESSION_ID_MASK 0x40000000L -#define RMI_DEBUGBUS_28__Reserved0_MASK 0x80000000L - -// RMI_DEBUGBUS_29 -#define RMI_DEBUGBUS_29__SNAPSHOT_CNT0_MASK 0x00000fffL -#define RMI_DEBUGBUS_29__SNAPSHOT_CNT1_MASK 0x00fff000L -#define RMI_DEBUGBUS_29__VMID_INVAL_FORCE_DONE_MASK 0x01000000L -#define RMI_DEBUGBUS_29__VMID_INVAL_WATCHDOG_IN_PROGRESS_MASK 0x02000000L -#define RMI_DEBUGBUS_29__RMI_SCOREBOARD_FLUSH_DONE_RB0_MASK 0x04000000L -#define RMI_DEBUGBUS_29__RMI_SCOREBOARD_FLUSH_DONE_RB1_MASK 0x08000000L -#define RMI_DEBUGBUS_29__CPF_RMI_INVREQ_CLEAN_MASK 0x10000000L -#define RMI_DEBUGBUS_29__CPF_RMI_INVREQ_START_MASK 0x20000000L -#define RMI_DEBUGBUS_29__CPF_RMI_INVREQ_CLEAN_NXT_MASK 0x40000000L -#define RMI_DEBUGBUS_29__Reserved0_MASK 0x80000000L - -// RMI_DEBUGBUS_30 -#define RMI_DEBUGBUS_30__UPDATE_SNAPSHOT_CNT0_MASK 0x00000001L -#define RMI_DEBUGBUS_30__UPDATE_SNAPSHOT_CNT1_MASK 0x00000002L -#define RMI_DEBUGBUS_30__UPDATE_RUNNING_CNT0_MASK 0x00000004L -#define RMI_DEBUGBUS_30__UPDATE_RUNNING_CNT1_MASK 0x00000008L -#define RMI_DEBUGBUS_30__SB_PROBE_SESSION_ID_PREV_MASK 0x00000010L -#define RMI_DEBUGBUS_30__POP0_SB_XNACK_SESSION_ID_MASK 0x00000020L -#define RMI_DEBUGBUS_30__POP0_SB_XNACK_RBID_MASK 0x00000040L -#define RMI_DEBUGBUS_30__POP0_SB_XNACK_VALID_MASK 0x00000080L -#define RMI_DEBUGBUS_30__POP1_SB_XNACK_SESSION_ID_MASK 0x00000100L -#define RMI_DEBUGBUS_30__POP1_SB_XNACK_RBID_MASK 0x00000200L -#define RMI_DEBUGBUS_30__POP1_SB_XNACK_VALID_MASK 0x00000400L -#define RMI_DEBUGBUS_30__PROBE0_SB_RBID_MASK 0x00000800L -#define RMI_DEBUGBUS_30__PROBE0_SB_VALID_MASK 0x00001000L -#define RMI_DEBUGBUS_30__PROBE1_SB_RBID_MASK 0x00002000L -#define RMI_DEBUGBUS_30__PROBE1_SB_VALID_MASK 0x00004000L -#define RMI_DEBUGBUS_30__SB_PROBE_INVREQ_VMID_VEC_MASK 0x7fff8000L -#define RMI_DEBUGBUS_30__SB_PROBE_INVREQ_START_MASK 0x80000000L - -// RMI_DEBUGBUS_31 -#define RMI_DEBUGBUS_31__RTNFORMATTER_RB_SEND_TCIW0_MASK 0x00000001L -#define RMI_DEBUGBUS_31__SEND_BOTH_HALVES_TO_RB_TCIW0_MASK 0x00000002L -#define RMI_DEBUGBUS_31__CLT_TAG_STORE_OUT_VALID_TCIW0_MASK 0x00000004L -#define RMI_DEBUGBUS_31__CLT_TAG_STORE_OUT_RMIMASK_TCIW0_MASK 0x00000018L -#define RMI_DEBUGBUS_31__SKID_FIFO_OUT_RTR_TCIW0_MASK 0x00000020L -#define RMI_DEBUGBUS_31__SKID_FIFO_OUT_RTS_TCIW0_MASK 0x00000040L -#define RMI_DEBUGBUS_31__CLT_TAG_STORE_OUT_TMP_STORE_VALID_TCIW0_MASK 0x00000080L -#define RMI_DEBUGBUS_31__RTNFORMATTER_TCIW_TAG_FREE_TCIW0_MASK 0x00000100L -#define RMI_DEBUGBUS_31__STATE_TCIW0_MASK 0x00000600L -#define RMI_DEBUGBUS_31__Reserved0_MASK 0xfffff800L - -// RMI_DEBUGBUS_32 -#define RMI_DEBUGBUS_32__RTNFORMATTER_RB_SEND_TCIW1_MASK 0x00000001L -#define RMI_DEBUGBUS_32__SEND_BOTH_HALVES_TO_RB_TCIW1_MASK 0x00000002L -#define RMI_DEBUGBUS_32__CLT_TAG_STORE_OUT_VALID_TCIW1_MASK 0x00000004L -#define RMI_DEBUGBUS_32__CLT_TAG_STORE_OUT_RMIMASK_TCIW1_MASK 0x00000018L -#define RMI_DEBUGBUS_32__SKID_FIFO_OUT_RTR_TCIW1_MASK 0x00000020L -#define RMI_DEBUGBUS_32__SKID_FIFO_OUT_RTS_TCIW1_MASK 0x00000040L -#define RMI_DEBUGBUS_32__CLT_TAG_STORE_OUT_TMP_STORE_VALID_TCIW1_MASK 0x00000080L -#define RMI_DEBUGBUS_32__RTNFORMATTER_TCIW_TAG_FREE_TCIW1_MASK 0x00000100L -#define RMI_DEBUGBUS_32__STATE_TCIW1_MASK 0x00000600L -#define RMI_DEBUGBUS_32__Reserved0_MASK 0xfffff800L - -// DB_DEBUG_BUS_0 -#define DB_DEBUG_BUS_0__BUSY_DATA0_MASK 0xffffffffL - -// DB_DEBUG_BUS_1 -#define DB_DEBUG_BUS_1__BUSY_DATA1_MASK 0xffffffffL - -// DB_DEBUG_BUS_2 -#define DB_DEBUG_BUS_2__BUSY_DATA2_MASK 0xffffffffL - -// DB_DEBUG_BUS_3 -#define DB_DEBUG_BUS_3__BUSY_DATA3_MASK 0xffffffffL - -// DB_DEBUG_BUS_4 -#define DB_DEBUG_BUS_4__STALL_DATA0_MASK 0xffffffffL - -// DB_DEBUG_BUS_5 -#define DB_DEBUG_BUS_5__STALL_DATA1_MASK 0xffffffffL - -// DB_DEBUG_BUS_6 -#define DB_DEBUG_BUS_6__STALL_DATA2_MASK 0xffffffffL - -// DB_DEBUG_BUS_7 -#define DB_DEBUG_BUS_7__STALL_DATA3_MASK 0xffffffffL - -// DB_DEBUG_BUS_8 -#define DB_DEBUG_BUS_8__STALL_DATA4_MASK 0xffffffffL - -// DB_DEBUG_BUS_9 -#define DB_DEBUG_BUS_9__STALL_DATA5_MASK 0xffffffffL - -// DB_DEBUG_BUS_A -#define DB_DEBUG_BUS_A__STALL_DATA6_MASK 0xffffffffL - -// DB_DEBUG_BUS_B -#define DB_DEBUG_BUS_B__INFO_DATA0_MASK 0xffffffffL - -// DB_DEBUG_BUS_C -#define DB_DEBUG_BUS_C__INFO_DATA1_MASK 0xffffffffL - -// DB_DEBUG_BUS_D -#define DB_DEBUG_BUS_D__INFO_DATA2_MASK 0xffffffffL - -// DB_DEBUG_BUS_E -#define DB_DEBUG_BUS_E__INFO_DATA3_MASK 0xffffffffL - -// DB_DEBUG_BUS_F -#define DB_DEBUG_BUS_F__INFO_DATA4_MASK 0xffffffffL - -// ATC_L2_CNTL -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L - -// ATC_L2_CNTL2 -#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003fL -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000c0L -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000e00L -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001f8000L - -// ATC_L2_DEBUG -#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x0000007fL -#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x00000080L -#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0x000fff00L -#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x00100000L -#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x00200000L -#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x00800000L -#define ATC_L2_DEBUG__CACHE_READ_MASK 0x02000000L -#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x04000000L -#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x08000000L -#define ATC_L2_DEBUG__IFIFO_SEND_DELAY_MASK 0x70000000L - -// ATC_L2_DEBUG2 -#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x0000001fL -#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x000000e0L -#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x00000100L -#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x00000200L -#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x00000400L -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x00000800L -#define ATC_L2_DEBUG2__ATS_SNOOP_OVERRIDE_MASK 0x00001000L -#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x00006000L -#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x00018000L -#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x001e0000L -#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x00200000L -#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_BY_ADDR_RANGE_MASK 0x00400000L -#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_BY_DOMAIN_MASK 0x00800000L -#define ATC_L2_DEBUG2__CGCG_OVERRIDE_MASK 0x01000000L - -// ATC_L2_CACHE_DATA0 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007ffffcL -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L - -// ATC_L2_CACHE_DATA1 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffffL - -// ATC_L2_CACHE_DATA2 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xffffffffL - -// ATC_L2_CNTL3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001f8L - -// ATC_L2_STATUS -#define ATC_L2_STATUS__BUSY_MASK 0x00000001L -#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffeL - -// ATC_L2_STATUS2 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000ffL -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000ff00L - -// ATC_L2_MISC_CG -#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000fc0L -#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L -#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L - -// ATC_L2_MEM_POWER_LS -#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL -#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L - -// ATC_L2_CGTT_CLK_CTRL -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00ff0000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xff000000L - -// ATC_L2_PERFCOUNTER_LO -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffffL - -// ATC_L2_PERFCOUNTER_HI -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000ffffL -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000L - -// ATC_L2_PERFCOUNTER0_CFG -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000ffL -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0f000000L -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L - -// ATC_L2_PERFCOUNTER1_CFG -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000ffL -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0f000000L -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L - -// ATC_L2_PERFCOUNTER_RSLT_CNTL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000fL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000ff00L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00ff0000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - -// VM_L2_CNTL -#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000cL -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03e00000L -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0c000000L - -// VM_L2_CNTL2 -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0c000000L -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L - -// VM_L2_CNTL3 -#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003fL -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000c0L -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001f00L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000f8000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00e00000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0f000000L -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L - -// VM_L2_STATUS -#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001fffeL -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L - -// VM_DUMMY_PAGE_FAULT_CNTL -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000fcL - -// VM_DUMMY_PAGE_FAULT_ADDR_LO32 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xffffffffL - -// VM_DUMMY_PAGE_FAULT_ADDR_HI32 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000fL - -// VM_L2_PROTECTION_FAULT_CNTL -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK \ - 0x00000002L -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK \ - 0x00000040L -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1fffe000L -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L - -// VM_L2_PROTECTION_FAULT_CNTL2 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000ffffL -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L - -// VM_L2_PROTECTION_FAULT_MM_CNTL3 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK \ - 0xffffffffL - -// VM_L2_PROTECTION_FAULT_MM_CNTL4 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK \ - 0xffffffffL - -// VM_L2_PROTECTION_FAULT_STATUS -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000eL -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000f0L -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003fe00L -#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L -#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00f00000L -#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L -#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1e000000L - -// VM_L2_PROTECTION_FAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xffffffffL - -// VM_L2_PROTECTION_FAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000fL - -// VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xffffffffL - -// VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000fL - -// VM_DEBUG -#define VM_DEBUG__FLAGS_MASK 0xffffffffL - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xffffffffL - -// VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000fL - -// VM_L2_CNTL4 -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003fL -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003ff00L -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0ffc0000L -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L - -// VM_L2_MM_GROUP_RT_CLASSES -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L - -// VM_L2_BANK_SELECT_RESERVED_CID -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001ffL -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007fc00L -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L - -// VM_L2_BANK_SELECT_RESERVED_CID2 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001ffL -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007fc00L -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L - -// VM_L2_CACHE_PARITY_CNTL -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001c0L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000e00L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000f000L - -// VM_L2_IH_LOG_CNTL -#define VM_L2_IH_LOG_CNTL__ENABLE_LOGGING_MASK 0x00000001L -#define VM_L2_IH_LOG_CNTL__USE_L_BIT_MASK 0x00000002L -#define VM_L2_IH_LOG_CNTL__REGISTER_ADDRESS_MASK 0x000ffffcL -#define VM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS_MASK 0x00100000L - -// VM_L2_IH_LOG_BUSY -#define VM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY_MASK 0x0000ffffL -#define VM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY_MASK 0xffff0000L - -// VM_L2_CGTT_CLK_CTRL -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00ff0000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xff000000L - -// VML2_SEC_MASTER -#define VML2_SEC_MASTER__UNIT_ID_MASK 0x0000003fL -#define VML2_SEC_MASTER__TRUST_LEVEL_MASK 0x000001c0L - -// VM_CONTEXT0_CNTL -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT1_CNTL -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT2_CNTL -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT3_CNTL -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT4_CNTL -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT5_CNTL -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT6_CNTL -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT7_CNTL -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT8_CNTL -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT9_CNTL -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT10_CNTL -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT11_CNTL -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT12_CNTL -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT13_CNTL -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT14_CNTL -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXT15_CNTL -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L -#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L - -// VM_CONTEXTS_DISABLE -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L - -// VM_INVALIDATE_ENG0_SEM -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG1_SEM -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG2_SEM -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG3_SEM -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG4_SEM -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG5_SEM -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG6_SEM -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG7_SEM -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG8_SEM -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG9_SEM -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG10_SEM -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG11_SEM -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG12_SEM -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG13_SEM -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG14_SEM -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG15_SEM -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG16_SEM -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG17_SEM -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L - -// VM_INVALIDATE_ENG0_REQ -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG1_REQ -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG2_REQ -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG3_REQ -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG4_REQ -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG5_REQ -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG6_REQ -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG7_REQ -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG8_REQ -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG9_REQ -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG10_REQ -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG11_REQ -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG12_REQ -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG13_REQ -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG14_REQ -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG15_REQ -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG16_REQ -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG17_REQ -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L - -// VM_INVALIDATE_ENG0_ACK -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG1_ACK -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG2_ACK -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG3_ACK -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG4_ACK -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG5_ACK -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG6_ACK -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG7_ACK -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG8_ACK -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG9_ACK -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG10_ACK -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG11_ACK -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG12_ACK -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG13_ACK -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG14_ACK -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG15_ACK -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG16_ACK -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG17_ACK -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000ffffL -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L - -// VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xfffffffeL - -// VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001fL - -// VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xffffffffL - -// VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xffffffffL - -// VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xffffffffL - -// VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000fL - -// MC_VM_L2_PERFCOUNTER0_CFG -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER1_CFG -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER2_CFG -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER3_CFG -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER4_CFG -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER5_CFG -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER6_CFG -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER7_CFG -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000ffL -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0f000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L - -// MC_VM_L2_PERFCOUNTER_RSLT_CNTL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000fL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000ff00L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00ff0000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - -// MC_VM_L2_PERFCOUNTER_LO -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffffL - -// MC_VM_L2_PERFCOUNTER_HI -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000ffffL -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF1 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF2 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF3 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF4 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF5 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF6 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF7 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF8 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF9 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF11 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF12 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF13 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF14 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000L - -// MC_VM_FB_SIZE_OFFSET_VF15 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000ffffL -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000L - -// VM_IOMMU_MMIO_CNTRL_1 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L - -// MC_VM_MARC_BASE_LO_0 -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000L - -// MC_VM_MARC_BASE_LO_1 -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000L - -// MC_VM_MARC_BASE_LO_2 -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000L - -// MC_VM_MARC_BASE_LO_3 -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000L - -// MC_VM_MARC_BASE_HI_0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000fffffL - -// MC_VM_MARC_BASE_HI_1 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000fffffL - -// MC_VM_MARC_BASE_HI_2 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000fffffL - -// MC_VM_MARC_BASE_HI_3 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000fffffL - -// MC_VM_MARC_RELOC_LO_0 -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000L - -// MC_VM_MARC_RELOC_LO_1 -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000L - -// MC_VM_MARC_RELOC_LO_2 -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000L - -// MC_VM_MARC_RELOC_LO_3 -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000L - -// MC_VM_MARC_RELOC_HI_0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000fffffL - -// MC_VM_MARC_RELOC_HI_1 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000fffffL - -// MC_VM_MARC_RELOC_HI_2 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000fffffL - -// MC_VM_MARC_RELOC_HI_3 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000fffffL - -// MC_VM_MARC_LEN_LO_0 -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000L - -// MC_VM_MARC_LEN_LO_1 -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000L - -// MC_VM_MARC_LEN_LO_2 -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000L - -// MC_VM_MARC_LEN_LO_3 -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000L - -// MC_VM_MARC_LEN_HI_0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000fffffL - -// MC_VM_MARC_LEN_HI_1 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000fffffL - -// MC_VM_MARC_LEN_HI_2 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000fffffL - -// MC_VM_MARC_LEN_HI_3 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000fffffL - -// VM_IOMMU_CONTROL_REGISTER -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L - -// VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L - -// VM_PCIE_ATS_CNTL -#define VM_PCIE_ATS_CNTL__STU_MASK 0x001f0000L -#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_0 -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_1 -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_2 -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_3 -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_4 -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_5 -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_6 -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_7 -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_8 -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_9 -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_10 -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_11 -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_12 -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_13 -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_14 -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L - -// VM_PCIE_ATS_CNTL_VF_15 -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L - -// UTCL2_CGTT_CLK_CTRL -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00ff0000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xff000000L - -// MC_VM_NB_MMIOBASE -#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffffL - -// MC_VM_NB_MMIOLIMIT -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffffL - -// MC_VM_NB_PCI_CTRL -#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L - -// MC_VM_NB_PCI_ARB -#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L - -// MC_VM_NB_TOP_OF_DRAM_SLOT1 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000L - -// MC_VM_NB_LOWER_TOP_OF_DRAM2 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000L - -// MC_VM_NB_UPPER_TOP_OF_DRAM2 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000fffL - -// MC_VM_FB_OFFSET -#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00ffffffL - -// MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xffffffffL - -// MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000fL - -// MC_VM_STEERING -#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L - -// MC_SHARED_VIRT_RESET_REQ -#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000ffffL -#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L - -// MC_MEM_POWER_LS -#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL -#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L - -// MC_VM_CACHEABLE_DRAM_ADDRESS_START -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000fffffL - -// MC_VM_CACHEABLE_DRAM_ADDRESS_END -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000fffffL - -// MC_VM_APT_CNTL -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L - -// MC_VM_LOCAL_HBM_ADDRESS_START -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000fffffL - -// MC_VM_LOCAL_HBM_ADDRESS_END -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000fffffL - -// MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L - -// MC_VM_FB_LOCATION_BASE -#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00ffffffL - -// MC_VM_FB_LOCATION_TOP -#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00ffffffL - -// MC_VM_AGP_TOP -#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00ffffffL - -// MC_VM_AGP_BOT -#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00ffffffL - -// MC_VM_AGP_BASE -#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00ffffffL - -// MC_VM_SYSTEM_APERTURE_LOW_ADDR -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3fffffffL - -// MC_VM_SYSTEM_APERTURE_HIGH_ADDR -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3fffffffL - -// MC_VM_MX_L1_TLB_CNTL -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L -#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L - -// GCEA_DRAM_RD_CLI2GRP_MAP0 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000cL -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000c0L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000c00L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000c000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000c0000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00c00000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0c000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xc0000000L - -// GCEA_DRAM_RD_CLI2GRP_MAP1 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000cL -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000c0L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000c00L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000c000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000c0000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00c00000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0c000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xc0000000L - -// GCEA_DRAM_WR_CLI2GRP_MAP0 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000cL -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000c0L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000c00L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000c000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000c0000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00c00000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0c000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xc0000000L - -// GCEA_DRAM_WR_CLI2GRP_MAP1 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000cL -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000c0L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000c00L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000c000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000c0000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00c00000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0c000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xc0000000L - -// GCEA_DRAM_RD_GRP2VC_MAP -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001c0L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000e00L - -// GCEA_DRAM_WR_GRP2VC_MAP -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001c0L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000e00L - -// GCEA_DRAM_RD_LAZY -#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001c0L -#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000e00L - -// GCEA_DRAM_WR_LAZY -#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001c0L -#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000e00L - -// GCEA_DRAM_RD_CAM_CNTL -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000fL -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000f0L -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000f00L -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000f000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01c00000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0e000000L - -// GCEA_DRAM_WR_CAM_CNTL -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000fL -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000f0L -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000f00L -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000f000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01c00000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0e000000L - -// GCEA_DRAM_PAGE_BURST -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000ffL -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000ff00L -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00ff0000L -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xff000000L - -// GCEA_DRAM_RD_PRI_AGE -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001c0L -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000e00L -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001c0000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00e00000L - -// GCEA_DRAM_WR_PRI_AGE -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001c0L -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000e00L -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001c0000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00e00000L - -// GCEA_DRAM_RD_PRI_QUEUING -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001c0L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000e00L - -// GCEA_DRAM_WR_PRI_QUEUING -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001c0L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000e00L - -// GCEA_DRAM_RD_PRI_FIXED -#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001c0L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000e00L - -// GCEA_DRAM_WR_PRI_FIXED -#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001c0L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000e00L - -// GCEA_DRAM_RD_PRI_URGENCY -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001c0L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000e00L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L - -// GCEA_DRAM_WR_PRI_URGENCY -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001c0L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000e00L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L - -// GCEA_DRAM_RD_PRI_QUANT_PRI1 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_DRAM_RD_PRI_QUANT_PRI2 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_DRAM_RD_PRI_QUANT_PRI3 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_DRAM_WR_PRI_QUANT_PRI1 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_DRAM_WR_PRI_QUANT_PRI2 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_DRAM_WR_PRI_QUANT_PRI3 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_ADDRNORM_BASE_ADDR0 -#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L -#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000f0L -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L -#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xfffff000L - -// GCEA_ADDRNORM_LIMIT_ADDR0 -#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000fL -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000c00L -#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xfffff000L - -// GCEA_ADDRNORM_BASE_ADDR1 -#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L -#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000f0L -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L -#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xfffff000L - -// GCEA_ADDRNORM_LIMIT_ADDR1 -#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000fL -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000c00L -#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xfffff000L - -// GCEA_ADDRNORM_OFFSET_ADDR1 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xfff00000L - -// GCEA_ADDRNORM_HOLE_CNTL -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000ff80L - -// GCEA_ADDRDEC_BANK_CFG -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001fL -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003e0L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001c00L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000e000L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L - -// GCEA_ADDRDEC_MISC_CFG -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000f000L -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000f0000L -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00c00000L -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003ffeL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xffffc000L - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003ffeL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xffffc000L - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003ffeL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xffffc000L - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003ffeL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xffffc000L - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003ffeL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xffffc000L - -// GCEA_ADDRDECDRAM_ADDR_HASH_PC -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003ffeL -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xffffc000L - -// GCEA_ADDRDECDRAM_ADDR_HASH_PC2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001fL - -// GCEA_ADDRDECDRAM_ADDR_HASH_CS0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xfffffffeL - -// GCEA_ADDRDECDRAM_ADDR_HASH_CS1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xfffffffeL - -// GCEA_ADDRDECDRAM_HARVEST_ENABLE -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L - -// GCEA_ADDRDEC0_BASE_ADDR_CS0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_BASE_ADDR_CS1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_BASE_ADDR_CS2 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_BASE_ADDR_CS3 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_ADDR_MASK_CS01 -#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_ADDR_MASK_CS23 -#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC0_ADDR_CFG_CS01 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000cL -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000f00L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000f000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000f0000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L - -// GCEA_ADDRDEC0_ADDR_CFG_CS23 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000cL -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000f00L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000f000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000f0000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L - -// GCEA_ADDRDEC0_ADDR_SEL_CS01 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000f000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000f0000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0f000000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xf0000000L - -// GCEA_ADDRDEC0_ADDR_SEL_CS23 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000f000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000f0000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0f000000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xf0000000L - -// GCEA_ADDRDEC0_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000f000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000f0000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00f00000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0f000000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xf0000000L - -// GCEA_ADDRDEC0_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000f000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000f0000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00f00000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0f000000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xf0000000L - -// GCEA_ADDRDEC0_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000fL -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000f0L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000f00L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000f000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000f0000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00f00000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0f000000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xf0000000L - -// GCEA_ADDRDEC0_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000fL -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000f0L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000f00L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000f000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000f0000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00f00000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0f000000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xf0000000L - -// GCEA_ADDRDEC0_RM_SEL_CS01 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_ADDRDEC0_RM_SEL_CS23 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_ADDRDEC0_RM_SEL_SECCS01 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_ADDRDEC0_RM_SEL_SECCS23 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_ADDRDEC1_BASE_ADDR_CS0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_BASE_ADDR_CS1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_BASE_ADDR_CS2 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_BASE_ADDR_CS3 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_ADDR_MASK_CS01 -#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_ADDR_MASK_CS23 -#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xfffffffeL - -// GCEA_ADDRDEC1_ADDR_CFG_CS01 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000cL -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000f00L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000f000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000f0000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L - -// GCEA_ADDRDEC1_ADDR_CFG_CS23 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000cL -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000f00L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000f000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000f0000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L - -// GCEA_ADDRDEC1_ADDR_SEL_CS01 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000f000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000f0000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0f000000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xf0000000L - -// GCEA_ADDRDEC1_ADDR_SEL_CS23 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000f000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000f0000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0f000000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xf0000000L - -// GCEA_ADDRDEC1_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000f000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000f0000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00f00000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0f000000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xf0000000L - -// GCEA_ADDRDEC1_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000f000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000f0000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00f00000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0f000000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xf0000000L - -// GCEA_ADDRDEC1_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000fL -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000f0L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000f00L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000f000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000f0000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00f00000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0f000000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xf0000000L - -// GCEA_ADDRDEC1_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000fL -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000f0L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000f00L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000f000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000f0000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00f00000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0f000000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xf0000000L - -// GCEA_ADDRDEC1_RM_SEL_CS01 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_ADDRDEC1_RM_SEL_CS23 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_ADDRDEC1_RM_SEL_SECCS01 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_ADDRDEC1_RM_SEL_SECCS23 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000fL -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000f0L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000f00L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000f000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000c0000L - -// GCEA_IO_RD_CLI2GRP_MAP0 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000cL -#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000c0L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000c00L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000c000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000c0000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00c00000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0c000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xc0000000L - -// GCEA_IO_RD_CLI2GRP_MAP1 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000cL -#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000c0L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000c00L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000c000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000c0000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00c00000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0c000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xc0000000L - -// GCEA_IO_WR_CLI2GRP_MAP0 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000cL -#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000c0L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000c00L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000c000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000c0000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00c00000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0c000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xc0000000L - -// GCEA_IO_WR_CLI2GRP_MAP1 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000cL -#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000c0L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000c00L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000c000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000c0000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00c00000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0c000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xc0000000L - -// GCEA_IO_RD_COMBINE_FLUSH -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000fL -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000f0L -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000f00L -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000f000L - -// GCEA_IO_WR_COMBINE_FLUSH -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000fL -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000f0L -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000f00L -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000f000L - -// GCEA_IO_GROUP_BURST -#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000ffL -#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000ff00L -#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00ff0000L -#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xff000000L - -// GCEA_IO_RD_PRI_AGE -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001c0L -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000e00L -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001c0000L -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00e00000L - -// GCEA_IO_WR_PRI_AGE -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001c0L -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000e00L -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001c0000L -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00e00000L - -// GCEA_IO_RD_PRI_QUEUING -#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001c0L -#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000e00L - -// GCEA_IO_WR_PRI_QUEUING -#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001c0L -#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000e00L - -// GCEA_IO_RD_PRI_FIXED -#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001c0L -#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000e00L - -// GCEA_IO_WR_PRI_FIXED -#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001c0L -#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000e00L - -// GCEA_IO_RD_PRI_URGENCY -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001c0L -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000e00L -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L - -// GCEA_IO_WR_PRI_URGENCY -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001c0L -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000e00L -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L - -// GCEA_IO_RD_PRI_URGENCY_MASK -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L - -// GCEA_IO_WR_PRI_URGENCY_MASK -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L - -// GCEA_IO_RD_PRI_QUANT_PRI1 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_IO_RD_PRI_QUANT_PRI2 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_IO_RD_PRI_QUANT_PRI3 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_IO_WR_PRI_QUANT_PRI1 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_IO_WR_PRI_QUANT_PRI2 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_IO_WR_PRI_QUANT_PRI3 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000ffL -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000ff00L -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00ff0000L -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xff000000L - -// GCEA_SDP_ARB_DRAM -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007fL -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007f00L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L -#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L - -// GCEA_SDP_ARB_FINAL -#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001fL -#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003e0L -#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007c00L -#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L -#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L -#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L - -// GCEA_SDP_DRAM_PRIORITY -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000fL -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000f0L -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000f00L -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000f000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000f0000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00f00000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0f000000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xf0000000L - -// GCEA_SDP_IO_PRIORITY -#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000fL -#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000f0L -#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000f00L -#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000f000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000f0000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00f00000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0f000000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xf0000000L - -// GCEA_SDP_CREDITS -#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000ffL -#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007f00L -#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007f0000L -#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3f000000L - -// GCEA_SDP_TAG_RESERVE0 -#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000ffL -#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000ff00L -#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00ff0000L -#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xff000000L - -// GCEA_SDP_TAG_RESERVE1 -#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000ffL -#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000ff00L -#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00ff0000L -#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xff000000L - -// GCEA_SDP_VCC_RESERVE0 -#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003fL -#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000fc0L -#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003f000L -#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00fc0000L -#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3f000000L - -// GCEA_SDP_VCC_RESERVE1 -#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003fL -#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000fc0L -#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003f000L -#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L - -// GCEA_SDP_VCD_RESERVE0 -#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003fL -#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000fc0L -#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003f000L -#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00fc0000L -#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3f000000L - -// GCEA_SDP_VCD_RESERVE1 -#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003fL -#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000fc0L -#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003f000L -#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L - -// GCEA_SDP_REQ_CNTL -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L -#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L -#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L - -// GCEA_MISC -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L -#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L -#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L -#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L -#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L -#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L -#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L -#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03e00000L -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L -#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L -#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L - -// GCEA_LATENCY_SAMPLING -#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003fc000L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3fc00000L - -// GCEA_PERFCOUNTER_LO -#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffffL - -// GCEA_PERFCOUNTER_HI -#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000ffffL -#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000L - -// GCEA_PERFCOUNTER0_CFG -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000ffL -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0f000000L -#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L - -// GCEA_PERFCOUNTER1_CFG -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000ffL -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000ff00L -#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0f000000L -#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L - -// GCEA_PERFCOUNTER_RSLT_CNTL -#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000fL -#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000ff00L -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00ff0000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - -// GCEA_MAM_CTRL -#define GCEA_MAM_CTRL__ADRAM_MODE_MASK 0x00000003L -#define GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE_MASK 0x00000004L -#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD_MASK 0x00000038L -#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE_MASK 0x00000040L -#define GCEA_MAM_CTRL__ARAM_FORCE_FLUSH_MASK 0x00000080L -#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000700L -#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000800L -#define GCEA_MAM_CTRL__ALOG_ACTIVE_MASK 0x00001000L -#define GCEA_MAM_CTRL__SDP_PRIORITY_MASK 0x0001e000L -#define GCEA_MAM_CTRL__CLIENT_ID_MASK 0x003e0000L -#define GCEA_MAM_CTRL__MAM_DISABLE_MASK 0x00400000L -#define GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE_MASK 0x07800000L -#define GCEA_MAM_CTRL__ALOG_MODE_MASK 0x08000000L -#define GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW_MASK 0x70000000L -#define GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT_MASK 0x80000000L - -// GCEA_MAM_CTRL2 -#define GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000003L -#define GCEA_MAM_CTRL2__ALOG_SPACE_MASK 0x0000000cL -#define GCEA_MAM_CTRL2__RESERVED_FIELD_MASK 0x0ffffff0L -#define GCEA_MAM_CTRL2__ADDR_HI_MASK 0xf0000000L - -// GCEA_MAM_ARAM_FLUSH_ADDR_LO -#define GCEA_MAM_ARAM_FLUSH_ADDR_LO__ADDR_LO_MASK 0xffffffffL - -// GCEA_MAM_DBIT_QUERY -#define GCEA_MAM_DBIT_QUERY__QUERY_EN_MASK 0x00000001L -#define GCEA_MAM_DBIT_QUERY__DBIT_PRESERVE_MASK 0x00000002L -#define GCEA_MAM_DBIT_QUERY__RESERVED_FIELD_MASK 0x0000000cL -#define GCEA_MAM_DBIT_QUERY__QUERY_ADDR_LO_MASK 0xfffffff0L - -// GCEA_MAM_STATUS -#define GCEA_MAM_STATUS__DBIT_QUERY_RDY_MASK 0x00000001L -#define GCEA_MAM_STATUS__DBIT_QUERY_DIRTY_MASK 0x00000002L -#define GCEA_MAM_STATUS__ALOG_CLEAN_MASK 0x00000004L -#define GCEA_MAM_STATUS__ALOG_IDLE_MASK 0x00000008L -#define GCEA_MAM_STATUS__RESERVED_FIELD_MASK 0xfffffff0L - -// GCEA_EDC_CNT -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000cL -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000c0L -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000c00L -#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L -#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000c000L -#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L -#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000c0000L -#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L -#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00c00000L -#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L -#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0c000000L -#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L - -// GCEA_EDC_CNT2 -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000cL -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000c0L -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000c00L -#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L -#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000c000L -#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L -#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000c0000L -#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L -#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00c00000L - -// GCEA_DSM_CNTL -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000c0L -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000c0000L -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L - -// GCEA_DSM_CNTLA -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000c0L -#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000c0000L -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L - -// GCEA_DSM_CNTLB -#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000c0L -#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L - -// GCEA_DSM_CNTL2 -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000c0000L -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xfc000000L - -// GCEA_DSM_CNTL2A -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000c0000L -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L - -// GCEA_DSM_CNTL2B -#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000c0L -#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L - -// GCEA_TCC_XBR_CREDITS -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003fL -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000c0L -#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003f00L -#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000c000L -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003f0000L -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00c00000L -#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3f000000L -#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xc0000000L - -// GCEA_TCC_XBR_MAXBURST -#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000fL -#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000f0L -#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000f00L -#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000f000L - -// GCEA_PROBE_CNTL -#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001fL -#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L - -// GCEA_PROBE_MAP -#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L -#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L -#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L -#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L -#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L -#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L -#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L -#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L -#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L -#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L -#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L -#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L -#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L -#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L -#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L -#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L -#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L - -// GCEA_ERR_STATUS -#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000fL -#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000f0L -#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L -#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L -#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L - -// GCEA_MISC2 -#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L -#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007cL -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000f80L - -// GCEA_SDP_BACKDOOR_CMDCREDITS0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xffffffffL - -// GCEA_SDP_BACKDOOR_CMDCREDITS1 -#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7fffffffL - -// GCEA_SDP_BACKDOOR_DATACREDITS0 -#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xffffffffL - -// GCEA_SDP_BACKDOOR_DATACREDITS1 -#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7fffffffL - -// GCEA_SDP_BACKDOOR_MISCCREDITS -#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000ffL -#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000ff00L -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007f0000L -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3f800000L - -// GCEA_SDP_ENABLE -#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L - -// GCEA_CGTT_CLK_CTRL -#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL -#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L -#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L - -// GCEA_SECURE_CTRL -#define GCEA_SECURE_CTRL__SECLEVEL_MASK 0x00000007L -#define GCEA_SECURE_CTRL__TMZ_MASK 0x00000008L -#define GCEA_SECURE_CTRL__CREST_OFFSET_MASK 0x0ffffff0L - -} // gfx9 -} // pm4_profile - -#endif diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_offset.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_offset.h deleted file mode 100644 index 664457ee94..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_offset.h +++ /dev/null @@ -1,17412 +0,0 @@ -#ifndef _greenland_OFFSET_HEADER -#define _greenland_OFFSET_HEADER -/* -* gfx9_offset.h -* -* Register Spec Release: -* -* -* (c) 2000 ATI Technologies Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against -* inadvertent publication and does not imply publication or any waiver -* of confidentiality. The year included in the foregoing notice is the -* year of creation of the work. -* -*/ - -namespace pm4_profile { -namespace gfx9 { - -// Registers from ATS block - -#define mmATC_ATS_CNTL 0x0C20 -#define mmATC_ATS_DEBUG 0x0C21 -#define mmATC_ATS_FAULT_DEBUG 0x0C22 -#define mmATC_ATS_STATUS 0x0C23 -#define mmATC_ATS_FAULT_CNTL 0x0C24 -#define mmATC_ATS_FAULT_STATUS_INFO 0x0C25 -#define mmATC_ATS_FAULT_STATUS_ADDR 0x0C26 -#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0C27 -#define mmATC_TRANS_FAULT_RSPCNTRL 0x0C28 -#define mmATC_ATS_FAULT_STATUS_INFO2 0x0C29 -#define mmATHUB_MISC_CNTL 0x0C2A -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x0C2B -#define mmATC_VMID0_PASID_MAPPING 0x0C2C -#define mmATC_VMID1_PASID_MAPPING 0x0C2D -#define mmATC_VMID2_PASID_MAPPING 0x0C2E -#define mmATC_VMID3_PASID_MAPPING 0x0C2F -#define mmATC_VMID4_PASID_MAPPING 0x0C30 -#define mmATC_VMID5_PASID_MAPPING 0x0C31 -#define mmATC_VMID6_PASID_MAPPING 0x0C32 -#define mmATC_VMID7_PASID_MAPPING 0x0C33 -#define mmATC_VMID8_PASID_MAPPING 0x0C34 -#define mmATC_VMID9_PASID_MAPPING 0x0C35 -#define mmATC_VMID10_PASID_MAPPING 0x0C36 -#define mmATC_VMID11_PASID_MAPPING 0x0C37 -#define mmATC_VMID12_PASID_MAPPING 0x0C38 -#define mmATC_VMID13_PASID_MAPPING 0x0C39 -#define mmATC_VMID14_PASID_MAPPING 0x0C3A -#define mmATC_VMID15_PASID_MAPPING 0x0C3B -#define mmATC_ATS_VMID_STATUS 0x0C3C -#define mmATC_ATS_GFX_ATCL2_STATUS 0x0C3D -#define mmATC_PERFCOUNTER0_CFG 0x0C3E -#define mmATC_PERFCOUNTER1_CFG 0x0C3F -#define mmATC_PERFCOUNTER2_CFG 0x0C40 -#define mmATC_PERFCOUNTER3_CFG 0x0C41 -#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0C42 -#define mmATC_PERFCOUNTER_LO 0x0C43 -#define mmATC_PERFCOUNTER_HI 0x0C44 -#define mmATHUB_PCIE_ATS_CNTL 0x0C45 -#define mmATHUB_PCIE_PASID_CNTL 0x0C46 -#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0C47 -#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0C48 -#define mmATHUB_COMMAND 0x0C49 -#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x0C4A -#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x0C4B -#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x0C4C -#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x0C4D -#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x0C4E -#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x0C4F -#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0C50 -#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0C51 -#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0C52 -#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0C53 -#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0C54 -#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0C55 -#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0C56 -#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0C57 -#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0C58 -#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0C59 -#define mmATHUB_MEM_POWER_LS 0x0C5A -#define mmATS_IH_CREDIT 0x0C5B -#define mmATHUB_IH_CREDIT 0x0C5C -#define mmATC_VMID16_PASID_MAPPING 0x0C5D -#define mmATC_VMID17_PASID_MAPPING 0x0C5E -#define mmATC_VMID18_PASID_MAPPING 0x0C5F -#define mmATC_VMID19_PASID_MAPPING 0x0C60 -#define mmATC_VMID20_PASID_MAPPING 0x0C61 -#define mmATC_VMID21_PASID_MAPPING 0x0C62 -#define mmATC_VMID22_PASID_MAPPING 0x0C63 -#define mmATC_VMID23_PASID_MAPPING 0x0C64 -#define mmATC_VMID24_PASID_MAPPING 0x0C65 -#define mmATC_VMID25_PASID_MAPPING 0x0C66 -#define mmATC_VMID26_PASID_MAPPING 0x0C67 -#define mmATC_VMID27_PASID_MAPPING 0x0C68 -#define mmATC_VMID28_PASID_MAPPING 0x0C69 -#define mmATC_VMID29_PASID_MAPPING 0x0C6A -#define mmATC_VMID30_PASID_MAPPING 0x0C6B -#define mmATC_VMID31_PASID_MAPPING 0x0C6C -#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x0C6D -#define mmATHUB_SHARED_VIRT_RESET_REQ 0x0C6E -#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x0C6F -#define mmATC_ATS_SDPPORT_CNTL 0x0C70 -#define mmATC_ATS_DEBUG2 0x0C71 -#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0C72 -#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0C73 - - -// Registers from XPB block - -#define mmXPB_RTR_SRC_APRTR0 0x0C7C -#define mmXPB_RTR_SRC_APRTR1 0x0C7D -#define mmXPB_RTR_SRC_APRTR2 0x0C7E -#define mmXPB_RTR_SRC_APRTR3 0x0C7F -#define mmXPB_RTR_SRC_APRTR4 0x0C80 -#define mmXPB_RTR_SRC_APRTR5 0x0C81 -#define mmXPB_RTR_SRC_APRTR6 0x0C82 -#define mmXPB_RTR_SRC_APRTR7 0x0C83 -#define mmXPB_RTR_SRC_APRTR8 0x0C84 -#define mmXPB_RTR_SRC_APRTR9 0x0C85 -#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0C86 -#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0C87 -#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0C88 -#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0C89 -#define mmXPB_RTR_DEST_MAP0 0x0C8A -#define mmXPB_RTR_DEST_MAP1 0x0C8B -#define mmXPB_RTR_DEST_MAP2 0x0C8C -#define mmXPB_RTR_DEST_MAP3 0x0C8D -#define mmXPB_RTR_DEST_MAP4 0x0C8E -#define mmXPB_RTR_DEST_MAP5 0x0C8F -#define mmXPB_RTR_DEST_MAP6 0x0C90 -#define mmXPB_RTR_DEST_MAP7 0x0C91 -#define mmXPB_RTR_DEST_MAP8 0x0C92 -#define mmXPB_RTR_DEST_MAP9 0x0C93 -#define mmXPB_XDMA_RTR_DEST_MAP0 0x0C94 -#define mmXPB_XDMA_RTR_DEST_MAP1 0x0C95 -#define mmXPB_XDMA_RTR_DEST_MAP2 0x0C96 -#define mmXPB_XDMA_RTR_DEST_MAP3 0x0C97 -#define mmXPB_CLG_CFG0 0x0C98 -#define mmXPB_CLG_CFG1 0x0C99 -#define mmXPB_CLG_CFG2 0x0C9A -#define mmXPB_CLG_CFG3 0x0C9B -#define mmXPB_CLG_CFG4 0x0C9C -#define mmXPB_CLG_CFG5 0x0C9D -#define mmXPB_CLG_CFG6 0x0C9E -#define mmXPB_CLG_CFG7 0x0C9F -#define mmXPB_CLG_EXTRA 0x0CA0 -#define mmXPB_CLG_EXTRA_MSK 0x0CA1 -#define mmXPB_LB_ADDR 0x0CA2 -#define mmXPB_WCB_STS 0x0CA3 -#define mmXPB_HST_CFG 0x0CA4 -#define mmXPB_P2P_BAR_CFG 0x0CA5 -#define mmXPB_P2P_BAR0 0x0CA6 -#define mmXPB_P2P_BAR1 0x0CA7 -#define mmXPB_P2P_BAR2 0x0CA8 -#define mmXPB_P2P_BAR3 0x0CA9 -#define mmXPB_P2P_BAR4 0x0CAA -#define mmXPB_P2P_BAR5 0x0CAB -#define mmXPB_P2P_BAR6 0x0CAC -#define mmXPB_P2P_BAR7 0x0CAD -#define mmXPB_P2P_BAR_SETUP 0x0CAE -#define mmXPB_P2P_BAR_DEBUG 0x0CAF -#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0CB0 -#define mmXPB_P2P_BAR_DELTA_BELOW 0x0CB1 -#define mmXPB_PEER_SYS_BAR0 0x0CB2 -#define mmXPB_PEER_SYS_BAR1 0x0CB3 -#define mmXPB_PEER_SYS_BAR2 0x0CB4 -#define mmXPB_PEER_SYS_BAR3 0x0CB5 -#define mmXPB_PEER_SYS_BAR4 0x0CB6 -#define mmXPB_PEER_SYS_BAR5 0x0CB7 -#define mmXPB_PEER_SYS_BAR6 0x0CB8 -#define mmXPB_PEER_SYS_BAR7 0x0CB9 -#define mmXPB_PEER_SYS_BAR8 0x0CBA -#define mmXPB_PEER_SYS_BAR9 0x0CBB -#define mmXPB_XDMA_PEER_SYS_BAR0 0x0CBC -#define mmXPB_XDMA_PEER_SYS_BAR1 0x0CBD -#define mmXPB_XDMA_PEER_SYS_BAR2 0x0CBE -#define mmXPB_XDMA_PEER_SYS_BAR3 0x0CBF -#define mmXPB_CLK_GAT 0x0CC0 -#define mmXPB_INTF_CFG 0x0CC1 -#define mmXPB_INTF_STS 0x0CC2 -#define mmXPB_PIPE_STS 0x0CC3 -#define mmXPB_SUB_CTRL 0x0CC4 -#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x0CC5 -#define mmXPB_PERF_KNOBS 0x0CC6 -#define mmXPB_STICKY 0x0CC7 -#define mmXPB_STICKY_W1C 0x0CC8 -#define mmXPB_MISC_CFG 0x0CC9 -#define mmXPB_INTF_CFG2 0x0CCA -#define mmXPB_CLG_EXTRA_RD 0x0CCB -#define mmXPB_CLG_EXTRA_MSK_RD 0x0CCC -#define mmXPB_CLG_GFX_MATCH 0x0CCD -#define mmXPB_CLG_GFX_MATCH_MSK 0x0CCE -#define mmXPB_CLG_MM_MATCH 0x0CCF -#define mmXPB_CLG_MM_MATCH_MSK 0x0CD0 -#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x0CD1 -#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x0CD2 -#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x0CD3 -#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x0CD4 -#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x0CD5 -#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x0CD6 -#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x0CD7 -#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x0CD8 -#define mmXPB_CLG_MM_UNITID_MAPPING0 0x0CD9 -#define mmXPB_CLG_MM_UNITID_MAPPING1 0x0CDA -#define mmXPB_CLG_MM_UNITID_MAPPING2 0x0CDB -#define mmXPB_CLG_MM_UNITID_MAPPING3 0x0CDC - - -// Registers from RPB block - -#define mmRPB_PASSPW_CONF 0x0CEC -#define mmRPB_BLOCKLEVEL_CONF 0x0CED -#define mmRPB_SECLEVEL_CONF 0x0CEE -#define mmRPB_TAG_CONF 0x0CEF -#define mmRPB_DBG1 0x0CF0 -#define mmRPB_EFF_CNTL 0x0CF1 -#define mmRPB_ARB_CNTL 0x0CF2 -#define mmRPB_ARB_CNTL2 0x0CF3 -#define mmRPB_BIF_CNTL 0x0CF4 -#define mmRPB_WR_SWITCH_CNTL 0x0CF5 -#define mmRPB_WR_COMBINE_CNTL 0x0CF6 -#define mmRPB_RD_SWITCH_CNTL 0x0CF7 -#define mmRPB_CID_QUEUE_WR 0x0CF8 -#define mmRPB_CID_QUEUE_RD 0x0CF9 -#define mmRPB_PERF_COUNTER_CNTL 0x0CFA -#define mmRPB_PERF_COUNTER_STATUS 0x0CFB -#define mmRPB_CID_QUEUE_EX 0x0CFC -#define mmRPB_CID_QUEUE_EX_DATA 0x0CFD -#define mmRPB_SWITCH_CNTL2 0x0CFE -#define mmRPB_DEINTRLV_COMBINE_CNTL 0x0CFF -#define mmRPB_VC_SWITCH_RDWR 0x0D00 -#define mmRPB_PERFCOUNTER_LO 0x0D01 -#define mmRPB_PERFCOUNTER_HI 0x0D02 -#define mmRPB_PERFCOUNTER0_CFG 0x0D03 -#define mmRPB_PERFCOUNTER1_CFG 0x0D04 -#define mmRPB_PERFCOUNTER2_CFG 0x0D05 -#define mmRPB_PERFCOUNTER3_CFG 0x0D06 -#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x0D07 -#define mmRPB_MISC_CG 0x0D08 -#define mmRPB_RD_QUEUE_CNTL 0x0D09 -#define mmRPB_RD_QUEUE_CNTL2 0x0D0A -#define mmRPB_WR_QUEUE_CNTL 0x0D0B -#define mmRPB_WR_QUEUE_CNTL2 0x0D0C -#define mmRPB_EA_QUEUE_WR 0x0D0D -#define mmRPB_ATS_CNTL 0x0D0E -#define mmRPB_ATS_CNTL2 0x0D0F -#define mmRPB_SDPPORT_CNTL 0x0D10 - - -// Registers from RSMU_GENERIC block - -#define mmRSMU_HCID_GENERIC 0x12000 -#define mmRSMU_SIID_GENERIC 0x12001 -#define mmRSMU_DBG_MUX_CONTROL_GENERIC 0x12002 -#define mmRSMU_SW_MMIO_PUB_IND_ADDR_0_GENERIC 0x12003 -#define mmRSMU_SW_MMIO_PUB_IND_DATA_0_GENERIC 0x12004 -#define mmRSMU_SW_MMIO_PUB_IND_ADDR_1_GENERIC 0x12005 -#define mmRSMU_SW_MMIO_PUB_IND_DATA_1_GENERIC 0x12006 -#define mmRSMU_SOFT_RESETB_GENERIC 0x12007 -#define mmRSMU_PGFSM_CONTROL_GENERIC 0x12008 -#define mmRSMU_PGFSM_WR_DATA_GENERIC 0x12009 -#define mmRSMU_PGFSM_RD_DATA_GENERIC 0x1200A -#define mmRSMU_IH_CREDIT_GENERIC 0x1200B -#define mmRSMU_IH_RESET_CNTL_GENERIC 0x1200C -#define mmRSMU_SEM_RESP_GENERIC 0x1200D -#define mmRSMU_SEM_RESET_CNTL_GENERIC 0x1200E -#define mmRSMU_VIRTUAL_WIRE_SRC_ID_GENERIC 0x12012 -#define mmRSMU_VIRTUAL_WIRE_INDEX_GENERIC 0x12013 -#define mmRSMU_SW_STRAPRX_ADDR_GENERIC 0x12014 -#define mmRSMU_SW_STRAPRX_DATA_GENERIC 0x12015 -#define mmRSMU_SW_STRAP_CONTROL_GENERIC 0x12016 -#define mmRSMU_TIMEOUT_ERROR_LOG_REG_GENERIC 0x12017 -#define mmRSMU_IP_MASTER_STATUS_GENERIC 0x12018 -#define mmRSMU_GPUREG_SCRATCH_REG_0_GENERIC 0x12019 -#define mmRSMU_GPUREG_SCRATCH_REG_1_GENERIC 0x1201A -#define mmRSMU_COLD_RESETB_GENERIC 0x400001 -#define mmRSMU_HARD_RESETB_GENERIC 0x400002 -#define mmRSMU_PUB_FUSE_ADDR_GENERIC 0x400003 -#define mmRSMU_SEC_FUSE_ADDR_GENERIC 0x400004 -#define mmRSMU_ROM_ADDR_GENERIC 0x400005 -#define mmRSMU_MEM_POWER_CTRL_GENERIC 0x400006 -#define mmRSMU_MP0_STRAPRX_ADDR_GENERIC 0x400007 -#define mmRSMU_MP0_STRAPRX_DATA_GENERIC 0x400008 -#define mmRSMU_SMS_FUSE_CFG_GENERIC 0x40000A -#define mmRSMU_SMS_FUSE_ADDR_BASE_GENERIC 0x40000B -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GENERIC 0x40000C -#define mmRSMU_STRAP_CONTROL_GENERIC 0x40000D -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC 0x40000E -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC 0x40000F -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC 0x400010 -#define mmRSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC 0x400011 -#define mmRSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC 0x400012 -#define mmRSMU_CAC_LKG_WEIGHT_0_GENERIC 0x400017 -#define mmRSMU_CAC_LKG_WEIGHT_1_GENERIC 0x400018 -#define mmRSMU_CAC_LKG_WEIGHT_2_GENERIC 0x400019 -#define mmRSMU_CAC_LKG_WEIGHT_3_GENERIC 0x40001A -#define mmRSMU_CAC_LKG_ACC_0_GENERIC 0x40001B -#define mmRSMU_CAC_LKG_ACC_1_GENERIC 0x40001C -#define mmRSMU_CAC_LKG_ACC_2_GENERIC 0x40001D -#define mmRSMU_CAC_LKG_ACC_3_GENERIC 0x40001E -#define mmRSMU_CAC_LKG_ACC_4_GENERIC 0x40001F -#define mmRSMU_CAC_LKG_ACC_5_GENERIC 0x400020 -#define mmRSMU_CAC_LKG_ACC_6_GENERIC 0x400021 -#define mmRSMU_CAC_LKG_ACC_7_GENERIC 0x400022 -#define mmRSMU_CAC_CONTROL_GENERIC 0x40002B -#define mmRSMU_CAC_WEIGHT_0_GENERIC 0x40002C -#define mmRSMU_CAC_WEIGHT_1_GENERIC 0x40002D -#define mmRSMU_CAC_WEIGHT_2_GENERIC 0x40002E -#define mmRSMU_CAC_WEIGHT_3_GENERIC 0x40002F -#define mmRSMU_CAC_WEIGHT_4_GENERIC 0x400030 -#define mmRSMU_CAC_WEIGHT_5_GENERIC 0x400031 -#define mmRSMU_CAC_WEIGHT_6_GENERIC 0x400032 -#define mmRSMU_CAC_WEIGHT_7_GENERIC 0x400033 -#define mmRSMU_CAC_ACC_0_GENERIC 0x400034 -#define mmRSMU_CAC_ACC_1_GENERIC 0x400035 -#define mmRSMU_CAC_ACC_2_GENERIC 0x400036 -#define mmRSMU_CAC_ACC_3_GENERIC 0x400037 -#define mmRSMU_CAC_ACC_4_GENERIC 0x400038 -#define mmRSMU_CAC_ACC_5_GENERIC 0x400039 -#define mmRSMU_CAC_ACC_6_GENERIC 0x40003A -#define mmRSMU_CAC_ACC_7_GENERIC 0x40003B -#define mmRSMU_CAC_ACC_8_GENERIC 0x40003C -#define mmRSMU_CAC_ACC_9_GENERIC 0x40003D -#define mmRSMU_CAC_ACC_10_GENERIC 0x40003E -#define mmRSMU_CAC_ACC_11_GENERIC 0x40003F -#define mmRSMU_CAC_ACC_12_GENERIC 0x400040 -#define mmRSMU_CAC_ACC_13_GENERIC 0x400041 -#define mmRSMU_CAC_ACC_14_GENERIC 0x400042 -#define mmRSMU_CAC_ACC_15_GENERIC 0x400043 -#define mmRSMU_CAC_AGGR_LO_GENERIC 0x400044 -#define mmRSMU_CAC_AGGR_HI_GENERIC 0x400045 -#define mmRSMU_DPM_CONTROL_GENERIC 0x40004E -#define mmRSMU_DPM_ACC_GENERIC 0x40004F -#define mmRSMU_DPM_IPCLK_REF_COUNTER_GENERIC 0x400050 -#define mmRSMU_COUNTER_0_GENERIC 0x400051 -#define mmRSMU_COUNTER_1_GENERIC 0x400052 -#define mmRSMU_PWRMGT_INTR_ENABLE_P0_GENERIC 0x400053 -#define mmRSMU_PWRMGT_INTR_ENABLE_P1_GENERIC 0x400054 -#define mmRSMU_PWRMGT_INTR_ENABLE_P2_GENERIC 0x400055 -#define mmRSMU_PWRMGT_INTR_TARGET_ADDR_P0_GENERIC 0x400056 -#define mmRSMU_PWRMGT_INTR_TARGET_ADDR_P1_GENERIC 0x400057 -#define mmRSMU_PWRMGT_INTR_TARGET_ADDR_P2_GENERIC 0x400058 -#define mmRSMU_PWRMGT_INTR_CONFIG_P0_GENERIC 0x400059 -#define mmRSMU_PWRMGT_INTR_CONFIG_P1_GENERIC 0x40005A -#define mmRSMU_PWRMGT_INTR_CONFIG_P2_GENERIC 0x40005B -#define mmRSMU_PWRMGT_INTR_STATUS_GENERIC 0x40005C -#define mmRSMU_PWRMGT_INTR_PENDING_P0_GENERIC 0x40005D -#define mmRSMU_PWRMGT_INTR_PENDING_P1_GENERIC 0x40005E -#define mmRSMU_PWRMGT_INTR_PENDING_P2_GENERIC 0x40005F -#define mmRSMU_PWRMGT_INTR_TYPE_GENERIC 0x400060 -#define mmRSMU_PWRMGT_INTR_INTERCEPT_GENERIC 0x400061 -#define mmRSMU_PWRMGT_INTR_CLEAR_GENERIC 0x400062 -#define mmRSMU_HARD_RESETB_DELAY_GENERIC 0x400063 -#define mmRSMU_MMIOPUB_SCRATCH_REG_0_GENERIC 0x400064 -#define mmRSMU_VF_ENABLE_GENERIC 0x400065 -#define mmRSMU_MGCG_CONTROL_GENERIC 0x400066 -#define mmRSMU_CUSTOM_HARD_RESETB_GENERIC 0x40006A -#define mmRSMU_SEC_AXI_MASTER_ENABLE_GENERIC 0x400200 -#define mmRSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC 0x400201 -#define mmRSMU_AXI_MASTER_QOS_CNTL_GENERIC 0x400202 -#define mmRSMU_MASTER_ERROR_COUNTER_GENERIC 0x400203 -#define mmRSMU_SLAVE_TIMEOUT_VALUE_GENERIC 0x400204 -#define mmRSMU_RESET_TIMEOUT_CONTROL_GENERIC 0x400205 -#define mmRSMU_SLAVE_ERROR_COUNTER_GENERIC 0x400206 -#define mmRSMU_AEB_LOCK_0_GENERIC 0x400207 -#define mmRSMU_AEB_LOCK_1_GENERIC 0x400208 -#define mmRSMU_AEB_OVERRIDE_0_GENERIC 0x400209 -#define mmRSMU_AEB_OVERRIDE_1_GENERIC 0x40020A -#define mmRSMU_SEC_INTR_ENABLE_GENERIC 0x40020B -#define mmRSMU_SEC_INTR_TARGET_ADDR_GENERIC 0x40020C -#define mmRSMU_SEC_INTR_CONFIG_GENERIC 0x40020D -#define mmRSMU_SEC_INTR_STATUS_GENERIC 0x40020E -#define mmRSMU_SEC_INTR_PENDING_GENERIC 0x40020F -#define mmRSMU_SEC_INTR_TYPE_GENERIC 0x400210 -#define mmRSMU_SEC_INTR_INTERCEPT_GENERIC 0x400211 -#define mmRSMU_SEC_INTR_CLEAR_GENERIC 0x400212 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_0_GENERIC 0x400213 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GENERIC 0x40024B -#define mmRSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC 0x40024C -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GENERIC 0x40024D -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GENERIC 0x40024E -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC 0x40024F -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GENERIC 0x400250 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GENERIC 0x400251 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC 0x400252 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC 0x400253 -#define mmRSMU_SEC_START_ADDR_GROUP_0_GENERIC 0x400254 -#define mmRSMU_SEC_END_ADDR_GROUP_0_GENERIC 0x400255 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_0_GENERIC 0x400256 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_0_GENERIC 0x400257 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC 0x400258 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_0_GENERIC 0x400259 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_0_GENERIC 0x40025A -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC 0x40025B -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC 0x40025C -#define mmRSMU_SEC_START_ADDR_GROUP_1_GENERIC 0x40025D -#define mmRSMU_SEC_END_ADDR_GROUP_1_GENERIC 0x40025E -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_1_GENERIC 0x40025F -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_1_GENERIC 0x400260 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC 0x400261 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_1_GENERIC 0x400262 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_1_GENERIC 0x400263 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC 0x400264 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC 0x400265 -#define mmRSMU_SEC_START_ADDR_GROUP_2_GENERIC 0x400266 -#define mmRSMU_SEC_END_ADDR_GROUP_2_GENERIC 0x400267 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_2_GENERIC 0x400268 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_2_GENERIC 0x400269 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC 0x40026A -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_2_GENERIC 0x40026B -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_2_GENERIC 0x40026C -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC 0x40026D -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC 0x40026E -#define mmRSMU_SEC_START_ADDR_GROUP_3_GENERIC 0x40026F -#define mmRSMU_SEC_END_ADDR_GROUP_3_GENERIC 0x400270 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_3_GENERIC 0x400271 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_3_GENERIC 0x400272 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC 0x400273 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_3_GENERIC 0x400274 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_3_GENERIC 0x400275 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC 0x400276 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC 0x400277 -#define mmRSMU_SEC_START_ADDR_GROUP_4_GENERIC 0x400278 -#define mmRSMU_SEC_END_ADDR_GROUP_4_GENERIC 0x400279 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_4_GENERIC 0x40027A -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_4_GENERIC 0x40027B -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC 0x40027C -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_4_GENERIC 0x40027D -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_4_GENERIC 0x40027E -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC 0x40027F -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC 0x400280 -#define mmRSMU_SEC_START_ADDR_GROUP_5_GENERIC 0x400281 -#define mmRSMU_SEC_END_ADDR_GROUP_5_GENERIC 0x400282 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_5_GENERIC 0x400283 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_5_GENERIC 0x400284 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC 0x400285 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_5_GENERIC 0x400286 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_5_GENERIC 0x400287 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC 0x400288 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC 0x400289 -#define mmRSMU_SEC_START_ADDR_GROUP_6_GENERIC 0x40028A -#define mmRSMU_SEC_END_ADDR_GROUP_6_GENERIC 0x40028B -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_6_GENERIC 0x40028C -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_6_GENERIC 0x40028D -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC 0x40028E -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_6_GENERIC 0x40028F -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_6_GENERIC 0x400290 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC 0x400291 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC 0x400292 -#define mmRSMU_SEC_START_ADDR_GROUP_7_GENERIC 0x400293 -#define mmRSMU_SEC_END_ADDR_GROUP_7_GENERIC 0x400294 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_7_GENERIC 0x400295 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_7_GENERIC 0x400296 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC 0x400297 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_7_GENERIC 0x400298 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_7_GENERIC 0x400299 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC 0x40029A -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC 0x40029B -#define mmRSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC 0x4002E5 -#define mmRSMU_MMIOSEC_SCRATCH_REG_0_GENERIC 0x4002E6 - - -// Registers from RSMU_GC block - -#define mmRSMU_HCID_GC 0x12160 -#define mmRSMU_SIID_GC 0x12161 -#define mmRSMU_DBG_MUX_CONTROL_GC 0x12162 -#define mmRSMU_SW_MMIO_PUB_IND_ADDR_0_GC 0x12163 -#define mmRSMU_SW_MMIO_PUB_IND_DATA_0_GC 0x12164 -#define mmRSMU_SW_MMIO_PUB_IND_ADDR_1_GC 0x12165 -#define mmRSMU_SW_MMIO_PUB_IND_DATA_1_GC 0x12166 -#define mmRSMU_SOFT_RESETB_GC 0x12167 -#define mmRSMU_IH_CREDIT_GC 0x1216B -#define mmRSMU_IH_RESET_CNTL_GC 0x1216C -#define mmRSMU_SEM_RESP_GC 0x1216D -#define mmRSMU_SEM_RESET_CNTL_GC 0x1216E -#define mmRSMU_SW_STRAPRX_ADDR_GC 0x12174 -#define mmRSMU_SW_STRAPRX_DATA_GC 0x12175 -#define mmRSMU_SW_STRAP_CONTROL_GC 0x12176 -#define mmRSMU_TIMEOUT_ERROR_LOG_REG_GC 0x12177 -#define mmRSMU_IP_MASTER_STATUS_GC 0x12178 -#define mmRSMU_GPUREG_SCRATCH_REG_0_GC 0x12179 -#define mmRSMU_GPUREG_SCRATCH_REG_1_GC 0x1217A -#define mmRSMU_COLD_RESETB_GC 0x402C01 -#define mmRSMU_HARD_RESETB_GC 0x402C02 -#define mmRSMU_PUB_FUSE_ADDR_GC 0x402C03 -#define mmRSMU_SEC_FUSE_ADDR_GC 0x402C04 -#define mmRSMU_MEM_POWER_CTRL_GC 0x402C06 -#define mmRSMU_MP0_STRAPRX_ADDR_GC 0x402C07 -#define mmRSMU_MP0_STRAPRX_DATA_GC 0x402C08 -#define mmRSMU_SMS_FUSE_CFG_GC 0x402C0A -#define mmRSMU_SMS_FUSE_ADDR_BASE_GC 0x402C0B -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GC 0x402C0C -#define mmRSMU_STRAP_CONTROL_GC 0x402C0D -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC 0x402C0E -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC 0x402C0F -#define mmRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC 0x402C10 -#define mmRSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC 0x402C11 -#define mmRSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC 0x402C12 -#define mmRSMU_DPM_CONTROL_GC 0x402C4E -#define mmRSMU_DPM_ACC_GC 0x402C4F -#define mmRSMU_DPM_IPCLK_REF_COUNTER_GC 0x402C50 -#define mmRSMU_COUNTER_0_GC 0x402C51 -#define mmRSMU_COUNTER_1_GC 0x402C52 -#define mmRSMU_HARD_RESETB_DELAY_GC 0x402C63 -#define mmRSMU_MMIOPUB_SCRATCH_REG_0_GC 0x402C64 -#define mmRSMU_VF_ENABLE_GC 0x402C65 -#define mmRSMU_MGCG_CONTROL_GC 0x402C66 -#define mmRSMU_RESIDENCY_COUNTER_CNTL_GC 0x402C67 -#define mmRSMU_RESIDENCY_COUNTER_GC 0x402C68 -#define mmRSMU_RESIDENCY_REF_COUNTER_GC 0x402C69 -#define mmRSMU_CUSTOM_HARD_RESETB_GC 0x402C6A -#define mmRSMU_SEC_AXI_MASTER_ENABLE_GC 0x402E00 -#define mmRSMU_SEC_SLAVE_ERROR_COUNTER_GC 0x402E01 -#define mmRSMU_AXI_MASTER_QOS_CNTL_GC 0x402E02 -#define mmRSMU_MASTER_ERROR_COUNTER_GC 0x402E03 -#define mmRSMU_SLAVE_TIMEOUT_VALUE_GC 0x402E04 -#define mmRSMU_RESET_TIMEOUT_CONTROL_GC 0x402E05 -#define mmRSMU_SLAVE_ERROR_COUNTER_GC 0x402E06 -#define mmRSMU_AEB_LOCK_0_GC 0x402E07 -#define mmRSMU_AEB_LOCK_1_GC 0x402E08 -#define mmRSMU_AEB_OVERRIDE_0_GC 0x402E09 -#define mmRSMU_AEB_OVERRIDE_1_GC 0x402E0A -#define mmRSMU_SEC_INTR_ENABLE_GC 0x402E0B -#define mmRSMU_SEC_INTR_TARGET_ADDR_GC 0x402E0C -#define mmRSMU_SEC_INTR_CONFIG_GC 0x402E0D -#define mmRSMU_SEC_INTR_STATUS_GC 0x402E0E -#define mmRSMU_SEC_INTR_PENDING_GC 0x402E0F -#define mmRSMU_SEC_INTR_TYPE_GC 0x402E10 -#define mmRSMU_SEC_INTR_INTERCEPT_GC 0x402E11 -#define mmRSMU_SEC_INTR_CLEAR_GC 0x402E12 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_0_GC 0x402E13 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_1_GC 0x402E14 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_2_GC 0x402E15 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_3_GC 0x402E16 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_5_GC 0x402E18 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_6_GC 0x402E19 -#define mmRSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC 0x402E4B -#define mmRSMU_SEC_ACCESS_CONTROL_RSMU_GC 0x402E4C -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GC 0x402E4D -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GC 0x402E4E -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC 0x402E4F -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GC 0x402E50 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GC 0x402E51 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC 0x402E52 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC 0x402E53 -#define mmRSMU_SEC_START_ADDR_GROUP_0_GC 0x402E54 -#define mmRSMU_SEC_END_ADDR_GROUP_0_GC 0x402E55 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_0_GC 0x402E56 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_0_GC 0x402E57 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_0_GC 0x402E58 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_0_GC 0x402E59 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_0_GC 0x402E5A -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_0_GC 0x402E5B -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_0_GC 0x402E5C -#define mmRSMU_SEC_START_ADDR_GROUP_1_GC 0x402E5D -#define mmRSMU_SEC_END_ADDR_GROUP_1_GC 0x402E5E -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_1_GC 0x402E5F -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_1_GC 0x402E60 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_1_GC 0x402E61 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_1_GC 0x402E62 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_1_GC 0x402E63 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_1_GC 0x402E64 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_1_GC 0x402E65 -#define mmRSMU_SEC_START_ADDR_GROUP_2_GC 0x402E66 -#define mmRSMU_SEC_END_ADDR_GROUP_2_GC 0x402E67 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_2_GC 0x402E68 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_2_GC 0x402E69 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_2_GC 0x402E6A -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_2_GC 0x402E6B -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_2_GC 0x402E6C -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_2_GC 0x402E6D -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_2_GC 0x402E6E -#define mmRSMU_SEC_START_ADDR_GROUP_3_GC 0x402E6F -#define mmRSMU_SEC_END_ADDR_GROUP_3_GC 0x402E70 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_3_GC 0x402E71 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_3_GC 0x402E72 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_3_GC 0x402E73 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_3_GC 0x402E74 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_3_GC 0x402E75 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_3_GC 0x402E76 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_3_GC 0x402E77 -#define mmRSMU_SEC_START_ADDR_GROUP_4_GC 0x402E78 -#define mmRSMU_SEC_END_ADDR_GROUP_4_GC 0x402E79 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_4_GC 0x402E7A -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_4_GC 0x402E7B -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_4_GC 0x402E7C -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_4_GC 0x402E7D -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_4_GC 0x402E7E -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_4_GC 0x402E7F -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_4_GC 0x402E80 -#define mmRSMU_SEC_START_ADDR_GROUP_5_GC 0x402E81 -#define mmRSMU_SEC_END_ADDR_GROUP_5_GC 0x402E82 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_5_GC 0x402E83 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_5_GC 0x402E84 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_5_GC 0x402E85 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_5_GC 0x402E86 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_5_GC 0x402E87 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_5_GC 0x402E88 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_5_GC 0x402E89 -#define mmRSMU_SEC_START_ADDR_GROUP_6_GC 0x402E8A -#define mmRSMU_SEC_END_ADDR_GROUP_6_GC 0x402E8B -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_6_GC 0x402E8C -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_6_GC 0x402E8D -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_6_GC 0x402E8E -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_6_GC 0x402E8F -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_6_GC 0x402E90 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_6_GC 0x402E91 -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_6_GC 0x402E92 -#define mmRSMU_SEC_START_ADDR_GROUP_7_GC 0x402E93 -#define mmRSMU_SEC_END_ADDR_GROUP_7_GC 0x402E94 -#define mmRSMU_SEC_INITID_MASK_SET0_GROUP_7_GC 0x402E95 -#define mmRSMU_SEC_UNITID_MASK_SET0_GROUP_7_GC 0x402E96 -#define mmRSMU_SEC_MISC_MASK_SET0_GROUP_7_GC 0x402E97 -#define mmRSMU_SEC_INITID_MASK_SET1_GROUP_7_GC 0x402E98 -#define mmRSMU_SEC_UNITID_MASK_SET1_GROUP_7_GC 0x402E99 -#define mmRSMU_SEC_MISC_MASK_SET1_GROUP_7_GC 0x402E9A -#define mmRSMU_SEC_ACCESS_CONTROL_GROUP_7_GC 0x402E9B -#define mmRSMU_SEC_SLAVE_ERROR_LOG_REG_GC 0x402EE5 -#define mmRSMU_MMIOSEC_SCRATCH_REG_0_GC 0x402EE6 - - -// Registers from BIF_RST block - -#define mmnbif_gpu_HARD_RST_CTRL 0x404E000 -#define mmnbif_gpu_RSMU_SOFT_RST_CTRL 0x404E001 -#define mmnbif_gpu_SELF_SOFT_RST 0x404E002 -#define mmnbif_gpu_GFX_DRV_MODE1_RST_CTRL 0x404E003 -#define mmnbif_gpu_BIF_RST_MISC_CTRL 0x404E004 -#define mmnbif_gpu_BIF_RST_MISC_CTRL2 0x404E005 -#define mmnbif_gpu_BIF_RST_MISC_CTRL3 0x404E006 -#define mmnbif_gpu_BIF_RST_GFXVF_FLR_IDLE 0x404E007 -#define mmnbif_gpu_DEV0_PF0_FLR_RST_CTRL 0x404E008 -#define mmnbif_gpu_DEV0_PF1_FLR_RST_CTRL 0x404E009 -#define mmnbif_gpu_DEV0_PF2_FLR_RST_CTRL 0x404E00A -#define mmnbif_gpu_DEV0_PF3_FLR_RST_CTRL 0x404E00B -#define mmnbif_gpu_DEV0_PF4_FLR_RST_CTRL 0x404E00C -#define mmnbif_gpu_DEV0_PF5_FLR_RST_CTRL 0x404E00D -#define mmnbif_gpu_DEV0_PF6_FLR_RST_CTRL 0x404E00E -#define mmnbif_gpu_DEV0_PF7_FLR_RST_CTRL 0x404E00F -#define mmnbif_gpu_BIF_INST_RESET_INTR_STS 0x404E010 -#define mmnbif_gpu_BIF_PF_FLR_INTR_STS 0x404E011 -#define mmnbif_gpu_BIF_D3HOTD0_INTR_STS 0x404E012 -#define mmnbif_gpu_BIF_POWER_INTR_STS 0x404E014 -#define mmnbif_gpu_BIF_PF_DSTATE_INTR_STS 0x404E015 -#define mmnbif_gpu_BIF_PF0_VF_FLR_INTR_STS 0x404E018 -#define mmnbif_gpu_BIF_INST_RESET_INTR_MASK 0x404E020 -#define mmnbif_gpu_BIF_PF_FLR_INTR_MASK 0x404E021 -#define mmnbif_gpu_BIF_D3HOTD0_INTR_MASK 0x404E022 -#define mmnbif_gpu_BIF_POWER_INTR_MASK 0x404E024 -#define mmnbif_gpu_BIF_PF_DSTATE_INTR_MASK 0x404E025 -#define mmnbif_gpu_BIF_PF0_VF_FLR_INTR_MASK 0x404E028 -#define mmnbif_gpu_BIF_PF_FLR_RST 0x404E040 -#define mmnbif_gpu_BIF_PF_FLR_PROTECT 0x404E042 -#define mmnbif_gpu_BIF_PF0_VF_FLR_RST 0x404E048 -#define mmnbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE 0x404E050 -#define mmnbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE 0x404E051 -#define mmnbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE 0x404E052 -#define mmnbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE 0x404E053 -#define mmnbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE 0x404E054 -#define mmnbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE 0x404E055 -#define mmnbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE 0x404E056 -#define mmnbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE 0x404E057 -#define mmnbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL 0x404E078 -#define mmnbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL 0x404E079 -#define mmnbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL 0x404E07A -#define mmnbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL 0x404E07B -#define mmnbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL 0x404E07C -#define mmnbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL 0x404E07D -#define mmnbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL 0x404E07E -#define mmnbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL 0x404E07F -#define mmnbif_gpu_BIF_GFX_VF_FLR_PROTECT 0x404E080 -#define mmnbif_gpu_BIF_PORT0_DSTATE_VALUE 0x404E230 - - -// Registers from BIF_MISC block - -#define mmnbif_gpu_MISC_SECURITY_SET 0x404CC00 -#define mmnbif_gpu_MISC_SCRATCH 0x404E800 -#define mmnbif_gpu_INTR_LINE_POLARITY 0x404E801 -#define mmnbif_gpu_INTR_LINE_ENABLE 0x404E802 -#define mmnbif_gpu_OUTSTANDING_VC_ALLOC 0x404E803 -#define mmnbif_gpu_BIFC_MISC_CTRL0 0x404E804 -#define mmnbif_gpu_BIFC_MISC_CTRL1 0x404E805 -#define mmnbif_gpu_BIFC_BME_ERR_LOG 0x404E806 -#define mmnbif_gpu_BIFC_RCCBIH_BME_ERR_LOG 0x404E807 -#define mmnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0x404E808 -#define mmnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0x404E809 -#define mmnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0x404E80A -#define mmnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0x404E80B -#define mmnbif_gpu_NBIF_VWIRE_CTRL 0x404E810 -#define mmnbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL 0x404E811 -#define mmnbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0 0x404E812 -#define mmnbif_gpu_NBIF_SMN_VWR_VCHG_TRIG 0x404E814 -#define mmnbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL 0x404E815 -#define mmnbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1 0x404E816 -#define mmnbif_gpu_NBIF_MGCG_CTRL 0x404E817 -#define mmnbif_gpu_NBIF_DS_CTRL_LCLK 0x404E818 -#define mmnbif_gpu_SMN_MST_CNTL0 0x404E819 -#define mmnbif_gpu_SMN_MST_EP_CNTL1 0x404E81A -#define mmnbif_gpu_SMN_MST_EP_CNTL2 0x404E81B -#define mmnbif_gpu_SMN_MST_EP_CNTL3 0x404E83C -#define mmnbif_gpu_SMN_MST_EP_CNTL4 0x404E83D -#define mmnbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL 0x404E81C -#define mmnbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0 0x404E81D -#define mmnbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1 0x404E81E -#define mmnbif_gpu_NBIF_SDP_VWR_VCHG_TRIG 0x404E81F -#define mmnbif_gpu_BME_DUMMY_CNTL_0 0x404E826 -#define mmnbif_gpu_BIFC_THT_CNTL 0x404E827 -#define mmnbif_gpu_BIFC_HSTARB_CNTL 0x404E828 -#define mmnbif_gpu_BIFC_GSI_CNTL 0x404E829 -#define mmnbif_gpu_BIFC_PCIEFUNC_CNTL 0x404E82A -#define mmnbif_gpu_BIFC_SDP_CNTL_0 0x404E82C -#define mmnbif_gpu_BIFC_PERF_CNTL_0 0x404E830 -#define mmnbif_gpu_BIFC_PERF_CNTL_1 0x404E831 -#define mmnbif_gpu_BIFC_PERF_CNT_MMIO_RD 0x404E832 -#define mmnbif_gpu_BIFC_PERF_CNT_MMIO_WR 0x404E833 -#define mmnbif_gpu_BIFC_PERF_CNT_DMA_RD 0x404E834 -#define mmnbif_gpu_BIFC_PERF_CNT_DMA_WR 0x404E835 -#define mmnbif_gpu_NBIF_REGIF_ERRSET_CTRL 0x404E836 - - -// Registers from BIF_RAS block - -#define mmnbif_gpu_BIF_RAS_LEAF0_CTRL 0x404E400 -#define mmnbif_gpu_BIF_RAS_LEAF1_CTRL 0x404E401 -#define mmnbif_gpu_BIF_RAS_LEAF2_CTRL 0x404E402 -#define mmnbif_gpu_BIF_RAS_MISC_CTRL 0x404E440 - - -// Registers from BIF_BX block - -#define mmnbif_gpu_SUM_INDEX 0x0038 -#define mmBIF_BX0_nbif_gpu_SUM_INDEX 0x0038 -#define mmnbif_gpu_SUM_INDEX_alt_1 0x404C638 -#define mmBIF_BX0_nbif_gpu_SUM_INDEX_alt_1 0x404C638 -#define mmnbif_gpu_SUM_DATA 0x0039 -#define mmBIF_BX0_nbif_gpu_SUM_DATA 0x0039 -#define mmnbif_gpu_SUM_DATA_alt_1 0x404C639 -#define mmBIF_BX0_nbif_gpu_SUM_DATA_alt_1 0x404C639 -#define mmnbif_gpu_SBIOS_SCRATCH_0 0x0048 -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_0 0x0048 -#define mmnbif_gpu_SBIOS_SCRATCH_0_alt_1 0x4048048 -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_0_alt_1 0x4048048 -#define mmnbif_gpu_SBIOS_SCRATCH_1 0x0049 -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_1 0x0049 -#define mmnbif_gpu_SBIOS_SCRATCH_1_alt_1 0x4048049 -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_1_alt_1 0x4048049 -#define mmnbif_gpu_SBIOS_SCRATCH_2 0x004A -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_2 0x004A -#define mmnbif_gpu_SBIOS_SCRATCH_2_alt_1 0x404804A -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_2_alt_1 0x404804A -#define mmnbif_gpu_SBIOS_SCRATCH_3 0x004B -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_3 0x004B -#define mmnbif_gpu_SBIOS_SCRATCH_3_alt_1 0x404804B -#define mmBIF_BX0_nbif_gpu_SBIOS_SCRATCH_3_alt_1 0x404804B -#define mmnbif_gpu_BIF_RLC_INTR_CNTL 0x0060 -#define mmBIF_BX0_nbif_gpu_BIF_RLC_INTR_CNTL 0x0060 -#define mmnbif_gpu_BIF_RLC_INTR_CNTL_alt_1 0x4048060 -#define mmBIF_BX0_nbif_gpu_BIF_RLC_INTR_CNTL_alt_1 0x4048060 -#define mmnbif_gpu_BIF_VCE_INTR_CNTL 0x0061 -#define mmBIF_BX0_nbif_gpu_BIF_VCE_INTR_CNTL 0x0061 -#define mmnbif_gpu_BIF_VCE_INTR_CNTL_alt_1 0x4048061 -#define mmBIF_BX0_nbif_gpu_BIF_VCE_INTR_CNTL_alt_1 0x4048061 -#define mmnbif_gpu_BIF_UVD_INTR_CNTL 0x0062 -#define mmBIF_BX0_nbif_gpu_BIF_UVD_INTR_CNTL 0x0062 -#define mmnbif_gpu_BIF_UVD_INTR_CNTL_alt_1 0x4048062 -#define mmBIF_BX0_nbif_gpu_BIF_UVD_INTR_CNTL_alt_1 0x4048062 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR0 0x0080 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR0 0x0080 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR0_alt_1 0x4048080 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR0_alt_1 0x4048080 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0_alt_1 0x4048081 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0_alt_1 0x4048081 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR1 0x0082 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR1 0x0082 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR1_alt_1 0x4048082 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR1_alt_1 0x4048082 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1_alt_1 0x4048083 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1_alt_1 0x4048083 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR2 0x0084 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR2 0x0084 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR2_alt_1 0x4048084 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR2_alt_1 0x4048084 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2_alt_1 0x4048085 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2_alt_1 0x4048085 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR3 0x0086 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR3 0x0086 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR3_alt_1 0x4048086 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR3_alt_1 0x4048086 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3_alt_1 0x4048087 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3_alt_1 0x4048087 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR4 0x0088 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR4 0x0088 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR4_alt_1 0x4048088 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR4_alt_1 0x4048088 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4_alt_1 0x4048089 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4_alt_1 0x4048089 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR5 0x008A -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR5 0x008A -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR5_alt_1 0x404808A -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR5_alt_1 0x404808A -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5 0x008B -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5 0x008B -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5_alt_1 0x404808B -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5_alt_1 0x404808B -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR6 0x008C -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR6 0x008C -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR6_alt_1 0x404808C -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR6_alt_1 0x404808C -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6 0x008D -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6 0x008D -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6_alt_1 0x404808D -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6_alt_1 0x404808D -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR7 0x008E -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR7 0x008E -#define mmnbif_gpu_GFX_MMIOREG_CAM_ADDR7_alt_1 0x404808E -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ADDR7_alt_1 0x404808E -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7 0x008F -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7 0x008F -#define mmnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7_alt_1 0x404808F -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7_alt_1 0x404808F -#define mmnbif_gpu_GFX_MMIOREG_CAM_CNTL 0x0090 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_CNTL 0x0090 -#define mmnbif_gpu_GFX_MMIOREG_CAM_CNTL_alt_1 0x4048090 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_CNTL_alt_1 0x4048090 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL 0x0091 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL 0x0091 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL_alt_1 0x4048091 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL_alt_1 0x4048091 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ONE_CPL 0x0092 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ONE_CPL 0x0092 -#define mmnbif_gpu_GFX_MMIOREG_CAM_ONE_CPL_alt_1 0x4048092 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_ONE_CPL_alt_1 0x4048092 -#define mmnbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 -#define mmnbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_alt_1 0x4048093 -#define mmBIF_BX0_nbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_alt_1 0x4048093 -#define mmnbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX0_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX1_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX2_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX3_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX4_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX5_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX6_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX7_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX8_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX9_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX10_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX11_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX12_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX13_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX14_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX15_nbif_gpu_MM_INDEX 0x0000 -#define mmBIF_BX16_nbif_gpu_MM_INDEX 0x0000 -#define mmnbif_gpu_MM_INDEX_alt_1 0x4048000 -#define mmBIF_BX0_nbif_gpu_MM_INDEX_alt_1 0x4048000 -#define mmnbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX0_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX1_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX2_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX3_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX4_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX5_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX6_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX7_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX8_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX9_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX10_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX11_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX12_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX13_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX14_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX15_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmBIF_BX16_nbif_gpu_MM_INDEX_HI 0x0006 -#define mmnbif_gpu_MM_INDEX_HI_alt_1 0x4048006 -#define mmBIF_BX0_nbif_gpu_MM_INDEX_HI_alt_1 0x4048006 -#define mmnbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX0_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX1_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX2_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX3_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX4_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX5_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX6_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX7_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX8_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX9_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX10_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX11_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX12_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX13_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX14_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX15_nbif_gpu_MM_DATA 0x0001 -#define mmBIF_BX16_nbif_gpu_MM_DATA 0x0001 -#define mmnbif_gpu_MM_DATA_alt_1 0x4048001 -#define mmBIF_BX0_nbif_gpu_MM_DATA_alt_1 0x4048001 -#define mmnbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX0_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX1_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX2_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX3_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX4_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX5_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX6_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX7_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX8_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX9_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX10_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX11_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX12_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX13_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX14_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX15_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmBIF_BX16_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define mmnbif_gpu_SYSHUB_INDEX_OVLP_alt_1 0x4048008 -#define mmBIF_BX0_nbif_gpu_SYSHUB_INDEX_OVLP_alt_1 0x4048008 -#define mmnbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX0_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX1_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX2_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX3_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX4_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX5_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX6_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX7_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX8_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX9_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX10_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX11_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX12_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX13_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX14_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX15_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmBIF_BX16_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define mmnbif_gpu_SYSHUB_DATA_OVLP_alt_1 0x4048009 -#define mmBIF_BX0_nbif_gpu_SYSHUB_DATA_OVLP_alt_1 0x4048009 -#define mmnbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX0_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX1_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX2_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX3_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX4_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX5_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX6_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX7_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX8_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX9_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX10_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX11_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX12_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX13_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX14_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX15_nbif_gpu_PCIE_INDEX 0x000C -#define mmBIF_BX16_nbif_gpu_PCIE_INDEX 0x000C -#define mmnbif_gpu_PCIE_INDEX_alt_1 0x404800C -#define mmBIF_BX0_nbif_gpu_PCIE_INDEX_alt_1 0x404800C -#define mmnbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX0_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX1_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX2_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX3_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX4_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX5_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX6_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX7_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX8_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX9_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX10_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX11_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX12_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX13_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX14_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX15_nbif_gpu_PCIE_DATA 0x000D -#define mmBIF_BX16_nbif_gpu_PCIE_DATA 0x000D -#define mmnbif_gpu_PCIE_DATA_alt_1 0x404800D -#define mmBIF_BX0_nbif_gpu_PCIE_DATA_alt_1 0x404800D -#define mmnbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX0_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX1_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX2_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX3_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX4_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX5_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX6_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX7_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX8_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX9_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX10_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX11_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX12_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX13_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX14_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX15_nbif_gpu_PCIE_INDEX2 0x000E -#define mmBIF_BX16_nbif_gpu_PCIE_INDEX2 0x000E -#define mmnbif_gpu_PCIE_INDEX2_alt_1 0x404800E -#define mmBIF_BX0_nbif_gpu_PCIE_INDEX2_alt_1 0x404800E -#define mmnbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX0_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX1_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX2_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX3_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX4_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX5_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX6_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX7_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX8_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX9_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX10_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX11_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX12_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX13_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX14_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX15_nbif_gpu_PCIE_DATA2 0x000F -#define mmBIF_BX16_nbif_gpu_PCIE_DATA2 0x000F -#define mmnbif_gpu_PCIE_DATA2_alt_1 0x404800F -#define mmBIF_BX0_nbif_gpu_PCIE_DATA2_alt_1 0x404800F -#define mmnbif_gpu_CC_BIF_BX_STRAP0 0x0E02 -#define mmBIF_BX0_nbif_gpu_CC_BIF_BX_STRAP0 0x0E02 -#define mmnbif_gpu_CC_BIF_BX_STRAP0_alt_1 0x4048E02 -#define mmBIF_BX0_nbif_gpu_CC_BIF_BX_STRAP0_alt_1 0x4048E02 -#define mmnbif_gpu_CC_BIF_BX_PINSTRAP0 0x0E04 -#define mmBIF_BX0_nbif_gpu_CC_BIF_BX_PINSTRAP0 0x0E04 -#define mmnbif_gpu_CC_BIF_BX_PINSTRAP0_alt_1 0x4048E04 -#define mmBIF_BX0_nbif_gpu_CC_BIF_BX_PINSTRAP0_alt_1 0x4048E04 -#define mmnbif_gpu_CC_BIF_BX_FUSESTRAP0 0x0E05 -#define mmBIF_BX0_nbif_gpu_CC_BIF_BX_FUSESTRAP0 0x0E05 -#define mmnbif_gpu_CC_BIF_BX_FUSESTRAP0_alt_1 0x4048E05 -#define mmBIF_BX0_nbif_gpu_CC_BIF_BX_FUSESTRAP0_alt_1 0x4048E05 -#define mmnbif_gpu_BIF_MM_INDACCESS_CNTL 0x0E06 -#define mmBIF_BX0_nbif_gpu_BIF_MM_INDACCESS_CNTL 0x0E06 -#define mmnbif_gpu_BIF_MM_INDACCESS_CNTL_alt_1 0x4048E06 -#define mmBIF_BX0_nbif_gpu_BIF_MM_INDACCESS_CNTL_alt_1 0x4048E06 -#define mmnbif_gpu_BUS_CNTL 0x0E07 -#define mmBIF_BX0_nbif_gpu_BUS_CNTL 0x0E07 -#define mmnbif_gpu_BUS_CNTL_alt_1 0x4048E07 -#define mmBIF_BX0_nbif_gpu_BUS_CNTL_alt_1 0x4048E07 -#define mmnbif_gpu_BIF_SCRATCH0 0x0E08 -#define mmBIF_BX0_nbif_gpu_BIF_SCRATCH0 0x0E08 -#define mmnbif_gpu_BIF_SCRATCH0_alt_1 0x4048E08 -#define mmBIF_BX0_nbif_gpu_BIF_SCRATCH0_alt_1 0x4048E08 -#define mmnbif_gpu_BIF_SCRATCH1 0x0E09 -#define mmBIF_BX0_nbif_gpu_BIF_SCRATCH1 0x0E09 -#define mmnbif_gpu_BIF_SCRATCH1_alt_1 0x4048E09 -#define mmBIF_BX0_nbif_gpu_BIF_SCRATCH1_alt_1 0x4048E09 -#define mmnbif_gpu_BX_RESET_EN 0x0E0D -#define mmBIF_BX0_nbif_gpu_BX_RESET_EN 0x0E0D -#define mmnbif_gpu_BX_RESET_EN_alt_1 0x4048E0D -#define mmBIF_BX0_nbif_gpu_BX_RESET_EN_alt_1 0x4048E0D -#define mmnbif_gpu_MM_CFGREGS_CNTL 0x0E0E -#define mmBIF_BX0_nbif_gpu_MM_CFGREGS_CNTL 0x0E0E -#define mmnbif_gpu_MM_CFGREGS_CNTL_alt_1 0x4048E0E -#define mmBIF_BX0_nbif_gpu_MM_CFGREGS_CNTL_alt_1 0x4048E0E -#define mmnbif_gpu_HW_DEBUG 0x0E0F -#define mmBIF_BX0_nbif_gpu_HW_DEBUG 0x0E0F -#define mmnbif_gpu_HW_DEBUG_alt_1 0x4048E0F -#define mmBIF_BX0_nbif_gpu_HW_DEBUG_alt_1 0x4048E0F -#define mmnbif_gpu_BX_RESET_CNTL 0x0E10 -#define mmBIF_BX0_nbif_gpu_BX_RESET_CNTL 0x0E10 -#define mmnbif_gpu_BX_RESET_CNTL_alt_1 0x4048E10 -#define mmBIF_BX0_nbif_gpu_BX_RESET_CNTL_alt_1 0x4048E10 -#define mmnbif_gpu_INTERRUPT_CNTL 0x0E11 -#define mmBIF_BX0_nbif_gpu_INTERRUPT_CNTL 0x0E11 -#define mmnbif_gpu_INTERRUPT_CNTL_alt_1 0x4048E11 -#define mmBIF_BX0_nbif_gpu_INTERRUPT_CNTL_alt_1 0x4048E11 -#define mmnbif_gpu_INTERRUPT_CNTL2 0x0E12 -#define mmBIF_BX0_nbif_gpu_INTERRUPT_CNTL2 0x0E12 -#define mmnbif_gpu_INTERRUPT_CNTL2_alt_1 0x4048E12 -#define mmBIF_BX0_nbif_gpu_INTERRUPT_CNTL2_alt_1 0x4048E12 -#define mmnbif_gpu_CLKREQB_PAD_CNTL 0x0E18 -#define mmBIF_BX0_nbif_gpu_CLKREQB_PAD_CNTL 0x0E18 -#define mmnbif_gpu_CLKREQB_PAD_CNTL_alt_1 0x4048E18 -#define mmBIF_BX0_nbif_gpu_CLKREQB_PAD_CNTL_alt_1 0x4048E18 -#define mmnbif_gpu_CLKREQB_PERF_COUNTER 0x0E19 -#define mmBIF_BX0_nbif_gpu_CLKREQB_PERF_COUNTER 0x0E19 -#define mmnbif_gpu_CLKREQB_PERF_COUNTER_alt_1 0x4048E19 -#define mmBIF_BX0_nbif_gpu_CLKREQB_PERF_COUNTER_alt_1 0x4048E19 -#define mmnbif_gpu_BIF_CLK_CTRL 0x0E1A -#define mmBIF_BX0_nbif_gpu_BIF_CLK_CTRL 0x0E1A -#define mmnbif_gpu_BIF_CLK_CTRL_alt_1 0x4048E1A -#define mmBIF_BX0_nbif_gpu_BIF_CLK_CTRL_alt_1 0x4048E1A -#define mmnbif_gpu_BIF_FEATURES_CONTROL_MISC 0x0E1B -#define mmBIF_BX0_nbif_gpu_BIF_FEATURES_CONTROL_MISC 0x0E1B -#define mmnbif_gpu_BIF_FEATURES_CONTROL_MISC_alt_1 0x4048E1B -#define mmBIF_BX0_nbif_gpu_BIF_FEATURES_CONTROL_MISC_alt_1 0x4048E1B -#define mmnbif_gpu_BIF_DOORBELL_CNTL 0x0E1C -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_CNTL 0x0E1C -#define mmnbif_gpu_BIF_DOORBELL_CNTL_alt_1 0x4048E1C -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_CNTL_alt_1 0x4048E1C -#define mmnbif_gpu_BIF_DOORBELL_INT_CNTL 0x0E1D -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_INT_CNTL 0x0E1D -#define mmnbif_gpu_BIF_DOORBELL_INT_CNTL_alt_1 0x4048E1D -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_INT_CNTL_alt_1 0x4048E1D -#define mmnbif_gpu_BIF_SLVARB_MODE 0x0E1E -#define mmBIF_BX0_nbif_gpu_BIF_SLVARB_MODE 0x0E1E -#define mmnbif_gpu_BIF_SLVARB_MODE_alt_1 0x4048E1E -#define mmBIF_BX0_nbif_gpu_BIF_SLVARB_MODE_alt_1 0x4048E1E -#define mmnbif_gpu_BIF_FB_EN 0x0E1F -#define mmBIF_BX0_nbif_gpu_BIF_FB_EN 0x0E1F -#define mmnbif_gpu_BIF_FB_EN_alt_1 0x4048E1F -#define mmBIF_BX0_nbif_gpu_BIF_FB_EN_alt_1 0x4048E1F -#define mmnbif_gpu_BIF_BUSY_DELAY_CNTR 0x0E20 -#define mmBIF_BX0_nbif_gpu_BIF_BUSY_DELAY_CNTR 0x0E20 -#define mmnbif_gpu_BIF_BUSY_DELAY_CNTR_alt_1 0x4048E20 -#define mmBIF_BX0_nbif_gpu_BIF_BUSY_DELAY_CNTR_alt_1 0x4048E20 -#define mmnbif_gpu_BIF_PERFMON_CNTL 0x0E21 -#define mmBIF_BX0_nbif_gpu_BIF_PERFMON_CNTL 0x0E21 -#define mmnbif_gpu_BIF_PERFMON_CNTL_alt_1 0x4048E21 -#define mmBIF_BX0_nbif_gpu_BIF_PERFMON_CNTL_alt_1 0x4048E21 -#define mmnbif_gpu_BIF_PERFCOUNTER0_RESULT 0x0E22 -#define mmBIF_BX0_nbif_gpu_BIF_PERFCOUNTER0_RESULT 0x0E22 -#define mmnbif_gpu_BIF_PERFCOUNTER0_RESULT_alt_1 0x4048E22 -#define mmBIF_BX0_nbif_gpu_BIF_PERFCOUNTER0_RESULT_alt_1 0x4048E22 -#define mmnbif_gpu_BIF_PERFCOUNTER1_RESULT 0x0E23 -#define mmBIF_BX0_nbif_gpu_BIF_PERFCOUNTER1_RESULT 0x0E23 -#define mmnbif_gpu_BIF_PERFCOUNTER1_RESULT_alt_1 0x4048E23 -#define mmBIF_BX0_nbif_gpu_BIF_PERFCOUNTER1_RESULT_alt_1 0x4048E23 -#define mmnbif_gpu_BIF_MST_TRANS_PENDING_VF 0x0E29 -#define mmBIF_BX0_nbif_gpu_BIF_MST_TRANS_PENDING_VF 0x0E29 -#define mmnbif_gpu_BIF_MST_TRANS_PENDING_VF_alt_1 0x4048E29 -#define mmBIF_BX0_nbif_gpu_BIF_MST_TRANS_PENDING_VF_alt_1 0x4048E29 -#define mmnbif_gpu_BIF_SLV_TRANS_PENDING_VF 0x0E2A -#define mmBIF_BX0_nbif_gpu_BIF_SLV_TRANS_PENDING_VF 0x0E2A -#define mmnbif_gpu_BIF_SLV_TRANS_PENDING_VF_alt_1 0x4048E2A -#define mmBIF_BX0_nbif_gpu_BIF_SLV_TRANS_PENDING_VF_alt_1 0x4048E2A -#define mmnbif_gpu_BACO_CNTL 0x0E2B -#define mmBIF_BX0_nbif_gpu_BACO_CNTL 0x0E2B -#define mmnbif_gpu_BACO_CNTL_alt_1 0x4048E2B -#define mmBIF_BX0_nbif_gpu_BACO_CNTL_alt_1 0x4048E2B -#define mmnbif_gpu_BIF_BACO_EXIT_TIME0 0x0E2C -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIME0 0x0E2C -#define mmnbif_gpu_BIF_BACO_EXIT_TIME0_alt_1 0x4048E2C -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIME0_alt_1 0x4048E2C -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER1 0x0E2D -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER1 0x0E2D -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER1_alt_1 0x4048E2D -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER1_alt_1 0x4048E2D -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER2 0x0E2E -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER2 0x0E2E -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER2_alt_1 0x4048E2E -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER2_alt_1 0x4048E2E -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER3 0x0E2F -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER3 0x0E2F -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER3_alt_1 0x4048E2F -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER3_alt_1 0x4048E2F -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER4 0x0E30 -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER4 0x0E30 -#define mmnbif_gpu_BIF_BACO_EXIT_TIMER4_alt_1 0x4048E30 -#define mmBIF_BX0_nbif_gpu_BIF_BACO_EXIT_TIMER4_alt_1 0x4048E30 -#define mmnbif_gpu_MEM_TYPE_CNTL 0x0E31 -#define mmBIF_BX0_nbif_gpu_MEM_TYPE_CNTL 0x0E31 -#define mmnbif_gpu_MEM_TYPE_CNTL_alt_1 0x4048E31 -#define mmBIF_BX0_nbif_gpu_MEM_TYPE_CNTL_alt_1 0x4048E31 -#define mmnbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS 0x0E33 -#define mmBIF_BX0_nbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS 0x0E33 -#define mmnbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS_alt_1 0x4048E33 -#define mmBIF_BX0_nbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS_alt_1 0x4048E33 -#define mmnbif_gpu_BIF_VDDGFX_GFX0_LOWER 0x0E34 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX0_LOWER 0x0E34 -#define mmnbif_gpu_BIF_VDDGFX_GFX0_LOWER_alt_1 0x4048E34 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX0_LOWER_alt_1 0x4048E34 -#define mmnbif_gpu_BIF_VDDGFX_GFX0_UPPER 0x0E35 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX0_UPPER 0x0E35 -#define mmnbif_gpu_BIF_VDDGFX_GFX0_UPPER_alt_1 0x4048E35 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX0_UPPER_alt_1 0x4048E35 -#define mmnbif_gpu_BIF_VDDGFX_GFX1_LOWER 0x0E36 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX1_LOWER 0x0E36 -#define mmnbif_gpu_BIF_VDDGFX_GFX1_LOWER_alt_1 0x4048E36 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX1_LOWER_alt_1 0x4048E36 -#define mmnbif_gpu_BIF_VDDGFX_GFX1_UPPER 0x0E37 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX1_UPPER 0x0E37 -#define mmnbif_gpu_BIF_VDDGFX_GFX1_UPPER_alt_1 0x4048E37 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX1_UPPER_alt_1 0x4048E37 -#define mmnbif_gpu_BIF_VDDGFX_GFX2_LOWER 0x0E38 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX2_LOWER 0x0E38 -#define mmnbif_gpu_BIF_VDDGFX_GFX2_LOWER_alt_1 0x4048E38 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX2_LOWER_alt_1 0x4048E38 -#define mmnbif_gpu_BIF_VDDGFX_GFX2_UPPER 0x0E39 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX2_UPPER 0x0E39 -#define mmnbif_gpu_BIF_VDDGFX_GFX2_UPPER_alt_1 0x4048E39 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX2_UPPER_alt_1 0x4048E39 -#define mmnbif_gpu_BIF_VDDGFX_GFX3_LOWER 0x0E3A -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX3_LOWER 0x0E3A -#define mmnbif_gpu_BIF_VDDGFX_GFX3_LOWER_alt_1 0x4048E3A -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX3_LOWER_alt_1 0x4048E3A -#define mmnbif_gpu_BIF_VDDGFX_GFX3_UPPER 0x0E3B -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX3_UPPER 0x0E3B -#define mmnbif_gpu_BIF_VDDGFX_GFX3_UPPER_alt_1 0x4048E3B -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX3_UPPER_alt_1 0x4048E3B -#define mmnbif_gpu_BIF_VDDGFX_GFX4_LOWER 0x0E3C -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX4_LOWER 0x0E3C -#define mmnbif_gpu_BIF_VDDGFX_GFX4_LOWER_alt_1 0x4048E3C -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX4_LOWER_alt_1 0x4048E3C -#define mmnbif_gpu_BIF_VDDGFX_GFX4_UPPER 0x0E3D -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX4_UPPER 0x0E3D -#define mmnbif_gpu_BIF_VDDGFX_GFX4_UPPER_alt_1 0x4048E3D -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX4_UPPER_alt_1 0x4048E3D -#define mmnbif_gpu_BIF_VDDGFX_GFX5_LOWER 0x0E3E -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX5_LOWER 0x0E3E -#define mmnbif_gpu_BIF_VDDGFX_GFX5_LOWER_alt_1 0x4048E3E -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX5_LOWER_alt_1 0x4048E3E -#define mmnbif_gpu_BIF_VDDGFX_GFX5_UPPER 0x0E3F -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX5_UPPER 0x0E3F -#define mmnbif_gpu_BIF_VDDGFX_GFX5_UPPER_alt_1 0x4048E3F -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_GFX5_UPPER_alt_1 0x4048E3F -#define mmnbif_gpu_BIF_VDDGFX_RSV1_LOWER 0x0E40 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV1_LOWER 0x0E40 -#define mmnbif_gpu_BIF_VDDGFX_RSV1_LOWER_alt_1 0x4048E40 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV1_LOWER_alt_1 0x4048E40 -#define mmnbif_gpu_BIF_VDDGFX_RSV1_UPPER 0x0E41 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV1_UPPER 0x0E41 -#define mmnbif_gpu_BIF_VDDGFX_RSV1_UPPER_alt_1 0x4048E41 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV1_UPPER_alt_1 0x4048E41 -#define mmnbif_gpu_BIF_VDDGFX_RSV2_LOWER 0x0E42 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV2_LOWER 0x0E42 -#define mmnbif_gpu_BIF_VDDGFX_RSV2_LOWER_alt_1 0x4048E42 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV2_LOWER_alt_1 0x4048E42 -#define mmnbif_gpu_BIF_VDDGFX_RSV2_UPPER 0x0E43 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV2_UPPER 0x0E43 -#define mmnbif_gpu_BIF_VDDGFX_RSV2_UPPER_alt_1 0x4048E43 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV2_UPPER_alt_1 0x4048E43 -#define mmnbif_gpu_BIF_VDDGFX_RSV3_LOWER 0x0E44 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV3_LOWER 0x0E44 -#define mmnbif_gpu_BIF_VDDGFX_RSV3_LOWER_alt_1 0x4048E44 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV3_LOWER_alt_1 0x4048E44 -#define mmnbif_gpu_BIF_VDDGFX_RSV3_UPPER 0x0E45 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV3_UPPER 0x0E45 -#define mmnbif_gpu_BIF_VDDGFX_RSV3_UPPER_alt_1 0x4048E45 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV3_UPPER_alt_1 0x4048E45 -#define mmnbif_gpu_BIF_VDDGFX_RSV4_LOWER 0x0E46 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV4_LOWER 0x0E46 -#define mmnbif_gpu_BIF_VDDGFX_RSV4_LOWER_alt_1 0x4048E46 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV4_LOWER_alt_1 0x4048E46 -#define mmnbif_gpu_BIF_VDDGFX_RSV4_UPPER 0x0E47 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV4_UPPER 0x0E47 -#define mmnbif_gpu_BIF_VDDGFX_RSV4_UPPER_alt_1 0x4048E47 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_RSV4_UPPER_alt_1 0x4048E47 -#define mmnbif_gpu_BIF_VDDGFX_FB_CMP 0x0E48 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_FB_CMP 0x0E48 -#define mmnbif_gpu_BIF_VDDGFX_FB_CMP_alt_1 0x4048E48 -#define mmBIF_BX0_nbif_gpu_BIF_VDDGFX_FB_CMP_alt_1 0x4048E48 -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER 0x0E49 -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER 0x0E49 -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER_alt_1 0x4048E49 -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER_alt_1 0x4048E49 -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER 0x0E4A -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER 0x0E4A -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER_alt_1 0x4048E4A -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER_alt_1 0x4048E4A -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER 0x0E4B -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER 0x0E4B -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER_alt_1 0x4048E4B -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER_alt_1 0x4048E4B -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER 0x0E4C -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER 0x0E4C -#define mmnbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER_alt_1 0x4048E4C -#define mmBIF_BX0_nbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER_alt_1 0x4048E4C -#define mmnbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL 0x0E4D -#define mmBIF_BX0_nbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL 0x0E4D -#define mmnbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL_alt_1 0x4048E4D -#define mmBIF_BX0_nbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL_alt_1 0x4048E4D -#define mmnbif_gpu_REMAP_HDP_REG_FLUSH_CNTL 0x0E4E -#define mmBIF_BX0_nbif_gpu_REMAP_HDP_REG_FLUSH_CNTL 0x0E4E -#define mmnbif_gpu_REMAP_HDP_REG_FLUSH_CNTL_alt_1 0x4048E4E -#define mmBIF_BX0_nbif_gpu_REMAP_HDP_REG_FLUSH_CNTL_alt_1 0x4048E4E -#define mmnbif_gpu_BIF_RB_CNTL 0x0E4F -#define mmBIF_BX0_nbif_gpu_BIF_RB_CNTL 0x0E4F -#define mmnbif_gpu_BIF_RB_CNTL_alt_1 0x4048E4F -#define mmBIF_BX0_nbif_gpu_BIF_RB_CNTL_alt_1 0x4048E4F -#define mmnbif_gpu_BIF_RB_BASE 0x0E50 -#define mmBIF_BX0_nbif_gpu_BIF_RB_BASE 0x0E50 -#define mmnbif_gpu_BIF_RB_BASE_alt_1 0x4048E50 -#define mmBIF_BX0_nbif_gpu_BIF_RB_BASE_alt_1 0x4048E50 -#define mmnbif_gpu_BIF_RB_RPTR 0x0E51 -#define mmBIF_BX0_nbif_gpu_BIF_RB_RPTR 0x0E51 -#define mmnbif_gpu_BIF_RB_RPTR_alt_1 0x4048E51 -#define mmBIF_BX0_nbif_gpu_BIF_RB_RPTR_alt_1 0x4048E51 -#define mmnbif_gpu_BIF_RB_WPTR 0x0E52 -#define mmBIF_BX0_nbif_gpu_BIF_RB_WPTR 0x0E52 -#define mmnbif_gpu_BIF_RB_WPTR_alt_1 0x4048E52 -#define mmBIF_BX0_nbif_gpu_BIF_RB_WPTR_alt_1 0x4048E52 -#define mmnbif_gpu_BIF_RB_WPTR_ADDR_HI 0x0E53 -#define mmBIF_BX0_nbif_gpu_BIF_RB_WPTR_ADDR_HI 0x0E53 -#define mmnbif_gpu_BIF_RB_WPTR_ADDR_HI_alt_1 0x4048E53 -#define mmBIF_BX0_nbif_gpu_BIF_RB_WPTR_ADDR_HI_alt_1 0x4048E53 -#define mmnbif_gpu_BIF_RB_WPTR_ADDR_LO 0x0E54 -#define mmBIF_BX0_nbif_gpu_BIF_RB_WPTR_ADDR_LO 0x0E54 -#define mmnbif_gpu_BIF_RB_WPTR_ADDR_LO_alt_1 0x4048E54 -#define mmBIF_BX0_nbif_gpu_BIF_RB_WPTR_ADDR_LO_alt_1 0x4048E54 -#define mmnbif_gpu_MAILBOX_INDEX 0x0E55 -#define mmBIF_BX0_nbif_gpu_MAILBOX_INDEX 0x0E55 -#define mmnbif_gpu_MAILBOX_INDEX_alt_1 0x4048E55 -#define mmBIF_BX0_nbif_gpu_MAILBOX_INDEX_alt_1 0x4048E55 -#define mmnbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION 0x0E62 -#define mmBIF_BX0_nbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION 0x0E62 -#define mmnbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION_alt_1 0x4048E62 -#define mmBIF_BX0_nbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION_alt_1 0x4048E62 -#define mmnbif_gpu_BIF_GMI_WRR_WEIGHT 0x0E65 -#define mmBIF_BX0_nbif_gpu_BIF_GMI_WRR_WEIGHT 0x0E65 -#define mmnbif_gpu_BIF_GMI_WRR_WEIGHT_alt_1 0x4048E65 -#define mmBIF_BX0_nbif_gpu_BIF_GMI_WRR_WEIGHT_alt_1 0x4048E65 -#define mmnbif_gpu_NBIF_STRAP_WRITE_CTRL 0x0E66 -#define mmBIF_BX0_nbif_gpu_NBIF_STRAP_WRITE_CTRL 0x0E66 -#define mmnbif_gpu_NBIF_STRAP_WRITE_CTRL_alt_1 0x4048E66 -#define mmBIF_BX0_nbif_gpu_NBIF_STRAP_WRITE_CTRL_alt_1 0x4048E66 -#define mmnbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX0_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX1_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX2_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX3_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX4_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX5_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX6_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX7_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX8_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX9_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX10_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX11_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX12_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX13_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX14_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX15_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmBIF_BX16_nbif_gpu_BIF_BME_STATUS 0x0E0B -#define mmnbif_gpu_BIF_BME_STATUS_alt_1 0x4048E0B -#define mmBIF_BX0_nbif_gpu_BIF_BME_STATUS_alt_1 0x4048E0B -#define mmnbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX0_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX1_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX2_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX3_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX4_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX5_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX6_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX7_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX8_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX9_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX10_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX11_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX12_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX13_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX14_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX15_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmBIF_BX16_nbif_gpu_BIF_ATOMIC_ERR_LOG 0x0E0C -#define mmnbif_gpu_BIF_ATOMIC_ERR_LOG_alt_1 0x4048E0C -#define mmBIF_BX0_nbif_gpu_BIF_ATOMIC_ERR_LOG_alt_1 0x4048E0C -#define mmnbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX0_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX1_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX2_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX3_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX4_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX5_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX6_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX7_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX8_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX9_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX10_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX11_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX12_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX13_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX14_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX15_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmBIF_BX16_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0E13 -#define mmnbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_alt_1 0x4048E13 -#define mmBIF_BX0_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_alt_1 0x4048E13 -#define mmnbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX0_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX1_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX2_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX3_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX4_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX5_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX6_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX7_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX8_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX9_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX10_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX11_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX12_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX13_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX14_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX15_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmBIF_BX16_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0E14 -#define mmnbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW_alt_1 0x4048E14 -#define mmBIF_BX0_nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW_alt_1 0x4048E14 -#define mmnbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX0_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX1_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX2_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX3_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX4_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX5_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX6_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX7_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX8_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX9_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX10_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX11_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX12_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX13_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX14_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX15_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmBIF_BX16_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL 0x0E15 -#define mmnbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL_alt_1 0x4048E15 -#define mmBIF_BX0_nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL_alt_1 0x4048E15 -#define mmnbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX0_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX1_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX2_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX3_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX4_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX5_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX6_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX7_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX8_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX9_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX10_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX11_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX12_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX13_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX14_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX15_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmBIF_BX16_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL 0x0E16 -#define mmnbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL_alt_1 0x4048E16 -#define mmBIF_BX0_nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL_alt_1 0x4048E16 -#define mmnbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX0_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX1_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX2_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX3_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX4_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX5_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX6_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX7_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX8_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX9_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX10_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX11_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX12_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX13_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX14_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX15_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmBIF_BX16_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL 0x0E17 -#define mmnbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL_alt_1 0x4048E17 -#define mmBIF_BX0_nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL_alt_1 0x4048E17 -#define mmnbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX0_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX1_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX2_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX3_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX4_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX5_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX6_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX7_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX8_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX9_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX10_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX11_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX12_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX13_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX14_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX15_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmBIF_BX16_nbif_gpu_GPU_HDP_FLUSH_REQ 0x0E26 -#define mmnbif_gpu_GPU_HDP_FLUSH_REQ_alt_1 0x4048E26 -#define mmBIF_BX0_nbif_gpu_GPU_HDP_FLUSH_REQ_alt_1 0x4048E26 -#define mmnbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX0_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX1_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX2_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX3_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX4_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX5_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX6_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX7_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX8_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX9_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX10_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX11_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX12_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX13_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX14_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX15_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmBIF_BX16_nbif_gpu_GPU_HDP_FLUSH_DONE 0x0E27 -#define mmnbif_gpu_GPU_HDP_FLUSH_DONE_alt_1 0x4048E27 -#define mmBIF_BX0_nbif_gpu_GPU_HDP_FLUSH_DONE_alt_1 0x4048E27 -#define mmnbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX0_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX1_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX2_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX3_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX4_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX5_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX6_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX7_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX8_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX9_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX10_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX11_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX12_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX13_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX14_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX15_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmBIF_BX16_nbif_gpu_BIF_TRANS_PENDING 0x0E28 -#define mmnbif_gpu_BIF_TRANS_PENDING_alt_1 0x4048E28 -#define mmBIF_BX0_nbif_gpu_BIF_TRANS_PENDING_alt_1 0x4048E28 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 0x0E56 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW0_alt_1 0x4048E56 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW0_alt_1 0x4048E56 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 0x0E57 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW1_alt_1 0x4048E57 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW1_alt_1 0x4048E57 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 0x0E58 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW2_alt_1 0x4048E58 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW2_alt_1 0x4048E58 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 0x0E59 -#define mmnbif_gpu_MAILBOX_MSGBUF_TRN_DW3_alt_1 0x4048E59 -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_TRN_DW3_alt_1 0x4048E59 -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 0x0E5A -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW0_alt_1 0x4048E5A -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW0_alt_1 0x4048E5A -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 0x0E5B -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW1_alt_1 0x4048E5B -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW1_alt_1 0x4048E5B -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 0x0E5C -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW2_alt_1 0x4048E5C -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW2_alt_1 0x4048E5C -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX1_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX2_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX3_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX4_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX5_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX6_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX7_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX8_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX9_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX10_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX11_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX12_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX13_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX14_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX15_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmBIF_BX16_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 0x0E5D -#define mmnbif_gpu_MAILBOX_MSGBUF_RCV_DW3_alt_1 0x4048E5D -#define mmBIF_BX0_nbif_gpu_MAILBOX_MSGBUF_RCV_DW3_alt_1 0x4048E5D -#define mmnbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX0_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX1_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX2_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX3_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX4_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX5_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX6_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX7_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX8_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX9_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX10_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX11_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX12_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX13_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX14_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX15_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmBIF_BX16_nbif_gpu_MAILBOX_CONTROL 0x0E5E -#define mmnbif_gpu_MAILBOX_CONTROL_alt_1 0x4048E5E -#define mmBIF_BX0_nbif_gpu_MAILBOX_CONTROL_alt_1 0x4048E5E -#define mmnbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX0_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX1_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX2_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX3_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX4_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX5_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX6_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX7_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX8_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX9_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX10_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX11_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX12_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX13_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX14_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX15_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmBIF_BX16_nbif_gpu_MAILBOX_INT_CNTL 0x0E5F -#define mmnbif_gpu_MAILBOX_INT_CNTL_alt_1 0x4048E5F -#define mmBIF_BX0_nbif_gpu_MAILBOX_INT_CNTL_alt_1 0x4048E5F -#define mmnbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX0_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX1_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX2_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX3_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX4_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX5_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX6_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX7_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX8_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX9_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX10_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX11_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX12_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX13_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX14_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX15_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmBIF_BX16_nbif_gpu_BIF_VMHV_MAILBOX 0x0E60 -#define mmnbif_gpu_BIF_VMHV_MAILBOX_alt_1 0x4048E60 -#define mmBIF_BX0_nbif_gpu_BIF_VMHV_MAILBOX_alt_1 0x4048E60 -#define ionbif_gpu_MM_INDEX 0x0000 -#define ioBIF_BX0_nbif_gpu_MM_INDEX 0x0000 -#define ionbif_gpu_MM_INDEX_HI 0x0006 -#define ioBIF_BX0_nbif_gpu_MM_INDEX_HI 0x0006 -#define ionbif_gpu_MM_DATA 0x0001 -#define ioBIF_BX0_nbif_gpu_MM_DATA 0x0001 -#define ionbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define ioBIF_BX0_nbif_gpu_SYSHUB_INDEX_OVLP 0x0008 -#define ionbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define ioBIF_BX0_nbif_gpu_SYSHUB_DATA_OVLP 0x0009 -#define ionbif_gpu_PCIE_INDEX 0x000C -#define ioBIF_BX0_nbif_gpu_PCIE_INDEX 0x000C -#define ionbif_gpu_PCIE_DATA 0x000D -#define ioBIF_BX0_nbif_gpu_PCIE_DATA 0x000D -#define ionbif_gpu_PCIE_INDEX2 0x000E -#define ioBIF_BX0_nbif_gpu_PCIE_INDEX2 0x000E -#define ionbif_gpu_PCIE_DATA2 0x000F -#define ioBIF_BX0_nbif_gpu_PCIE_DATA2 0x000F - - -// Registers from BIF_CFG_EPF block - -#define mmnbif_gpu_VENDOR_ID_epf 0x4050000 -#define mmBIF_CFG_EPF0_nbif_gpu_VENDOR_ID_epf 0x4050000 -#define mmBIF_CFG_EPF1_nbif_gpu_VENDOR_ID_epf 0x4050400 -#define mmnbif_gpu_DEVICE_ID_epf 0x4050000 -#define mmBIF_CFG_EPF0_nbif_gpu_DEVICE_ID_epf 0x4050000 -#define mmBIF_CFG_EPF1_nbif_gpu_DEVICE_ID_epf 0x4050400 -#define mmnbif_gpu_COMMAND_epf 0x4050001 -#define mmBIF_CFG_EPF0_nbif_gpu_COMMAND_epf 0x4050001 -#define mmBIF_CFG_EPF1_nbif_gpu_COMMAND_epf 0x4050401 -#define mmnbif_gpu_STATUS_epf 0x4050001 -#define mmBIF_CFG_EPF0_nbif_gpu_STATUS_epf 0x4050001 -#define mmBIF_CFG_EPF1_nbif_gpu_STATUS_epf 0x4050401 -#define mmnbif_gpu_REVISION_ID_epf 0x4050002 -#define mmBIF_CFG_EPF0_nbif_gpu_REVISION_ID_epf 0x4050002 -#define mmBIF_CFG_EPF1_nbif_gpu_REVISION_ID_epf 0x4050402 -#define mmnbif_gpu_PROG_INTERFACE_epf 0x4050002 -#define mmBIF_CFG_EPF0_nbif_gpu_PROG_INTERFACE_epf 0x4050002 -#define mmBIF_CFG_EPF1_nbif_gpu_PROG_INTERFACE_epf 0x4050402 -#define mmnbif_gpu_SUB_CLASS_epf 0x4050002 -#define mmBIF_CFG_EPF0_nbif_gpu_SUB_CLASS_epf 0x4050002 -#define mmBIF_CFG_EPF1_nbif_gpu_SUB_CLASS_epf 0x4050402 -#define mmnbif_gpu_BASE_CLASS_epf 0x4050002 -#define mmBIF_CFG_EPF0_nbif_gpu_BASE_CLASS_epf 0x4050002 -#define mmBIF_CFG_EPF1_nbif_gpu_BASE_CLASS_epf 0x4050402 -#define mmnbif_gpu_CACHE_LINE_epf 0x4050003 -#define mmBIF_CFG_EPF0_nbif_gpu_CACHE_LINE_epf 0x4050003 -#define mmBIF_CFG_EPF1_nbif_gpu_CACHE_LINE_epf 0x4050403 -#define mmnbif_gpu_LATENCY_epf 0x4050003 -#define mmBIF_CFG_EPF0_nbif_gpu_LATENCY_epf 0x4050003 -#define mmBIF_CFG_EPF1_nbif_gpu_LATENCY_epf 0x4050403 -#define mmnbif_gpu_HEADER_epf 0x4050003 -#define mmBIF_CFG_EPF0_nbif_gpu_HEADER_epf 0x4050003 -#define mmBIF_CFG_EPF1_nbif_gpu_HEADER_epf 0x4050403 -#define mmnbif_gpu_BIST_epf 0x4050003 -#define mmBIF_CFG_EPF0_nbif_gpu_BIST_epf 0x4050003 -#define mmBIF_CFG_EPF1_nbif_gpu_BIST_epf 0x4050403 -#define mmnbif_gpu_BASE_ADDR_1_epf 0x4050004 -#define mmBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_1_epf 0x4050004 -#define mmBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_1_epf 0x4050404 -#define mmnbif_gpu_BASE_ADDR_2_epf 0x4050005 -#define mmBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_2_epf 0x4050005 -#define mmBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_2_epf 0x4050405 -#define mmnbif_gpu_BASE_ADDR_3_epf 0x4050006 -#define mmBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_3_epf 0x4050006 -#define mmBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_3_epf 0x4050406 -#define mmnbif_gpu_BASE_ADDR_4_epf 0x4050007 -#define mmBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_4_epf 0x4050007 -#define mmBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_4_epf 0x4050407 -#define mmnbif_gpu_BASE_ADDR_5_epf 0x4050008 -#define mmBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_5_epf 0x4050008 -#define mmBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_5_epf 0x4050408 -#define mmnbif_gpu_BASE_ADDR_6_epf 0x4050009 -#define mmBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_6_epf 0x4050009 -#define mmBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_6_epf 0x4050409 -#define mmnbif_gpu_ROM_BASE_ADDR_epf 0x405000C -#define mmBIF_CFG_EPF0_nbif_gpu_ROM_BASE_ADDR_epf 0x405000C -#define mmBIF_CFG_EPF1_nbif_gpu_ROM_BASE_ADDR_epf 0x405040C -#define mmnbif_gpu_CAP_PTR_epf 0x405000D -#define mmBIF_CFG_EPF0_nbif_gpu_CAP_PTR_epf 0x405000D -#define mmBIF_CFG_EPF1_nbif_gpu_CAP_PTR_epf 0x405040D -#define mmnbif_gpu_INTERRUPT_LINE_epf 0x405000F -#define mmBIF_CFG_EPF0_nbif_gpu_INTERRUPT_LINE_epf 0x405000F -#define mmBIF_CFG_EPF1_nbif_gpu_INTERRUPT_LINE_epf 0x405040F -#define mmnbif_gpu_INTERRUPT_PIN_epf 0x405000F -#define mmBIF_CFG_EPF0_nbif_gpu_INTERRUPT_PIN_epf 0x405000F -#define mmBIF_CFG_EPF1_nbif_gpu_INTERRUPT_PIN_epf 0x405040F -#define mmnbif_gpu_ADAPTER_ID_epf 0x405000B -#define mmBIF_CFG_EPF0_nbif_gpu_ADAPTER_ID_epf 0x405000B -#define mmBIF_CFG_EPF1_nbif_gpu_ADAPTER_ID_epf 0x405040B -#define mmnbif_gpu_MIN_GRANT_epf 0x405000F -#define mmBIF_CFG_EPF0_nbif_gpu_MIN_GRANT_epf 0x405000F -#define mmBIF_CFG_EPF1_nbif_gpu_MIN_GRANT_epf 0x405040F -#define mmnbif_gpu_MAX_LATENCY_epf 0x405000F -#define mmBIF_CFG_EPF0_nbif_gpu_MAX_LATENCY_epf 0x405000F -#define mmBIF_CFG_EPF1_nbif_gpu_MAX_LATENCY_epf 0x405040F -#define mmnbif_gpu_VENDOR_CAP_LIST_epf 0x4050012 -#define mmBIF_CFG_EPF0_nbif_gpu_VENDOR_CAP_LIST_epf 0x4050012 -#define mmBIF_CFG_EPF1_nbif_gpu_VENDOR_CAP_LIST_epf 0x4050412 -#define mmnbif_gpu_ADAPTER_ID_W_epf 0x4050013 -#define mmBIF_CFG_EPF0_nbif_gpu_ADAPTER_ID_W_epf 0x4050013 -#define mmBIF_CFG_EPF1_nbif_gpu_ADAPTER_ID_W_epf 0x4050413 -#define mmnbif_gpu_PMI_CAP_LIST_epf 0x4050014 -#define mmBIF_CFG_EPF0_nbif_gpu_PMI_CAP_LIST_epf 0x4050014 -#define mmBIF_CFG_EPF1_nbif_gpu_PMI_CAP_LIST_epf 0x4050414 -#define mmnbif_gpu_PMI_CAP_epf 0x4050014 -#define mmBIF_CFG_EPF0_nbif_gpu_PMI_CAP_epf 0x4050014 -#define mmBIF_CFG_EPF1_nbif_gpu_PMI_CAP_epf 0x4050414 -#define mmnbif_gpu_PMI_STATUS_CNTL_epf 0x4050015 -#define mmBIF_CFG_EPF0_nbif_gpu_PMI_STATUS_CNTL_epf 0x4050015 -#define mmBIF_CFG_EPF1_nbif_gpu_PMI_STATUS_CNTL_epf 0x4050415 -#define mmnbif_gpu_PCIE_CAP_LIST_epf 0x4050019 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_CAP_LIST_epf 0x4050019 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_CAP_LIST_epf 0x4050419 -#define mmnbif_gpu_PCIE_CAP_epf 0x4050019 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_CAP_epf 0x4050019 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_CAP_epf 0x4050419 -#define mmnbif_gpu_DEVICE_CAP_epf 0x405001A -#define mmBIF_CFG_EPF0_nbif_gpu_DEVICE_CAP_epf 0x405001A -#define mmBIF_CFG_EPF1_nbif_gpu_DEVICE_CAP_epf 0x405041A -#define mmnbif_gpu_DEVICE_CNTL_epf 0x405001B -#define mmBIF_CFG_EPF0_nbif_gpu_DEVICE_CNTL_epf 0x405001B -#define mmBIF_CFG_EPF1_nbif_gpu_DEVICE_CNTL_epf 0x405041B -#define mmnbif_gpu_DEVICE_STATUS_epf 0x405001B -#define mmBIF_CFG_EPF0_nbif_gpu_DEVICE_STATUS_epf 0x405001B -#define mmBIF_CFG_EPF1_nbif_gpu_DEVICE_STATUS_epf 0x405041B -#define mmnbif_gpu_LINK_CAP_epf 0x405001C -#define mmBIF_CFG_EPF0_nbif_gpu_LINK_CAP_epf 0x405001C -#define mmBIF_CFG_EPF1_nbif_gpu_LINK_CAP_epf 0x405041C -#define mmnbif_gpu_LINK_CNTL_epf 0x405001D -#define mmBIF_CFG_EPF0_nbif_gpu_LINK_CNTL_epf 0x405001D -#define mmBIF_CFG_EPF1_nbif_gpu_LINK_CNTL_epf 0x405041D -#define mmnbif_gpu_LINK_STATUS_epf 0x405001D -#define mmBIF_CFG_EPF0_nbif_gpu_LINK_STATUS_epf 0x405001D -#define mmBIF_CFG_EPF1_nbif_gpu_LINK_STATUS_epf 0x405041D -#define mmnbif_gpu_DEVICE_CAP2_epf 0x4050022 -#define mmBIF_CFG_EPF0_nbif_gpu_DEVICE_CAP2_epf 0x4050022 -#define mmBIF_CFG_EPF1_nbif_gpu_DEVICE_CAP2_epf 0x4050422 -#define mmnbif_gpu_DEVICE_CNTL2_epf 0x4050023 -#define mmBIF_CFG_EPF0_nbif_gpu_DEVICE_CNTL2_epf 0x4050023 -#define mmBIF_CFG_EPF1_nbif_gpu_DEVICE_CNTL2_epf 0x4050423 -#define mmnbif_gpu_DEVICE_STATUS2_epf 0x4050023 -#define mmBIF_CFG_EPF0_nbif_gpu_DEVICE_STATUS2_epf 0x4050023 -#define mmBIF_CFG_EPF1_nbif_gpu_DEVICE_STATUS2_epf 0x4050423 -#define mmnbif_gpu_LINK_CAP2_epf 0x4050024 -#define mmBIF_CFG_EPF0_nbif_gpu_LINK_CAP2_epf 0x4050024 -#define mmBIF_CFG_EPF1_nbif_gpu_LINK_CAP2_epf 0x4050424 -#define mmnbif_gpu_LINK_CNTL2_epf 0x4050025 -#define mmBIF_CFG_EPF0_nbif_gpu_LINK_CNTL2_epf 0x4050025 -#define mmBIF_CFG_EPF1_nbif_gpu_LINK_CNTL2_epf 0x4050425 -#define mmnbif_gpu_LINK_STATUS2_epf 0x4050025 -#define mmBIF_CFG_EPF0_nbif_gpu_LINK_STATUS2_epf 0x4050025 -#define mmBIF_CFG_EPF1_nbif_gpu_LINK_STATUS2_epf 0x4050425 -#define mmnbif_gpu_SLOT_CAP2_epf 0x4050026 -#define mmBIF_CFG_EPF0_nbif_gpu_SLOT_CAP2_epf 0x4050026 -#define mmBIF_CFG_EPF1_nbif_gpu_SLOT_CAP2_epf 0x4050426 -#define mmnbif_gpu_SLOT_CNTL2_epf 0x4050027 -#define mmBIF_CFG_EPF0_nbif_gpu_SLOT_CNTL2_epf 0x4050027 -#define mmBIF_CFG_EPF1_nbif_gpu_SLOT_CNTL2_epf 0x4050427 -#define mmnbif_gpu_SLOT_STATUS2_epf 0x4050027 -#define mmBIF_CFG_EPF0_nbif_gpu_SLOT_STATUS2_epf 0x4050027 -#define mmBIF_CFG_EPF1_nbif_gpu_SLOT_STATUS2_epf 0x4050427 -#define mmnbif_gpu_MSI_CAP_LIST_epf 0x4050028 -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_CAP_LIST_epf 0x4050028 -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_CAP_LIST_epf 0x4050428 -#define mmnbif_gpu_MSI_MSG_CNTL_epf 0x4050028 -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_MSG_CNTL_epf 0x4050028 -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_MSG_CNTL_epf 0x4050428 -#define mmnbif_gpu_MSI_MSG_ADDR_LO_epf 0x4050029 -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_MSG_ADDR_LO_epf 0x4050029 -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_MSG_ADDR_LO_epf 0x4050429 -#define mmnbif_gpu_MSI_MSG_ADDR_HI_epf 0x405002A -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_MSG_ADDR_HI_epf 0x405002A -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_MSG_ADDR_HI_epf 0x405042A -#define mmnbif_gpu_MSI_MSG_DATA_64_epf 0x405002B -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_MSG_DATA_64_epf 0x405002B -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_MSG_DATA_64_epf 0x405042B -#define mmnbif_gpu_MSI_MSG_DATA_epf 0x405002A -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_MSG_DATA_epf 0x405002A -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_MSG_DATA_epf 0x405042A -#define mmnbif_gpu_MSI_MASK_epf 0x405002B -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_MASK_epf 0x405002B -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_MASK_epf 0x405042B -#define mmnbif_gpu_MSI_PENDING_epf 0x405002C -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_PENDING_epf 0x405002C -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_PENDING_epf 0x405042C -#define mmnbif_gpu_MSI_MASK_64_epf 0x405002C -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_MASK_64_epf 0x405002C -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_MASK_64_epf 0x405042C -#define mmnbif_gpu_MSI_PENDING_64_epf 0x405002D -#define mmBIF_CFG_EPF0_nbif_gpu_MSI_PENDING_64_epf 0x405002D -#define mmBIF_CFG_EPF1_nbif_gpu_MSI_PENDING_64_epf 0x405042D -#define mmnbif_gpu_MSIX_CAP_LIST_epf 0x4050030 -#define mmBIF_CFG_EPF0_nbif_gpu_MSIX_CAP_LIST_epf 0x4050030 -#define mmBIF_CFG_EPF1_nbif_gpu_MSIX_CAP_LIST_epf 0x4050430 -#define mmnbif_gpu_MSIX_MSG_CNTL_epf 0x4050030 -#define mmBIF_CFG_EPF0_nbif_gpu_MSIX_MSG_CNTL_epf 0x4050030 -#define mmBIF_CFG_EPF1_nbif_gpu_MSIX_MSG_CNTL_epf 0x4050430 -#define mmnbif_gpu_MSIX_TABLE_epf 0x4050031 -#define mmBIF_CFG_EPF0_nbif_gpu_MSIX_TABLE_epf 0x4050031 -#define mmBIF_CFG_EPF1_nbif_gpu_MSIX_TABLE_epf 0x4050431 -#define mmnbif_gpu_MSIX_PBA_epf 0x4050032 -#define mmBIF_CFG_EPF0_nbif_gpu_MSIX_PBA_epf 0x4050032 -#define mmBIF_CFG_EPF1_nbif_gpu_MSIX_PBA_epf 0x4050432 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf 0x4050040 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf 0x4050040 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf 0x4050440 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf 0x4050041 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf 0x4050041 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf 0x4050441 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC1_epf 0x4050042 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf 0x4050042 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf 0x4050442 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC2_epf 0x4050043 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf 0x4050043 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf 0x4050443 -#define mmnbif_gpu_PCIE_VC_ENH_CAP_LIST_epf 0x4050044 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf 0x4050044 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf 0x4050444 -#define mmnbif_gpu_PCIE_PORT_VC_CAP_REG1_epf 0x4050045 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf 0x4050045 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf 0x4050445 -#define mmnbif_gpu_PCIE_PORT_VC_CAP_REG2_epf 0x4050046 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf 0x4050046 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf 0x4050446 -#define mmnbif_gpu_PCIE_PORT_VC_CNTL_epf 0x4050047 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CNTL_epf 0x4050047 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CNTL_epf 0x4050447 -#define mmnbif_gpu_PCIE_PORT_VC_STATUS_epf 0x4050047 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_STATUS_epf 0x4050047 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_STATUS_epf 0x4050447 -#define mmnbif_gpu_PCIE_VC0_RESOURCE_CAP_epf 0x4050048 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf 0x4050048 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf 0x4050448 -#define mmnbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf 0x4050049 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf 0x4050049 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf 0x4050449 -#define mmnbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf 0x405004A -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf 0x405004A -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf 0x405044A -#define mmnbif_gpu_PCIE_VC1_RESOURCE_CAP_epf 0x405004B -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf 0x405004B -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf 0x405044B -#define mmnbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf 0x405004C -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf 0x405004C -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf 0x405044C -#define mmnbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf 0x405004D -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf 0x405004D -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf 0x405044D -#define mmnbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf 0x4050050 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf 0x4050050 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf 0x4050450 -#define mmnbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf 0x4050051 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf 0x4050051 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf 0x4050451 -#define mmnbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf 0x4050052 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf 0x4050052 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf 0x4050452 -#define mmnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf 0x4050054 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf 0x4050054 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf 0x4050454 -#define mmnbif_gpu_PCIE_UNCORR_ERR_STATUS_epf 0x4050055 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf 0x4050055 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf 0x4050455 -#define mmnbif_gpu_PCIE_UNCORR_ERR_MASK_epf 0x4050056 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_MASK_epf 0x4050056 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_MASK_epf 0x4050456 -#define mmnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf 0x4050057 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf 0x4050057 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf 0x4050457 -#define mmnbif_gpu_PCIE_CORR_ERR_STATUS_epf 0x4050058 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_CORR_ERR_STATUS_epf 0x4050058 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_CORR_ERR_STATUS_epf 0x4050458 -#define mmnbif_gpu_PCIE_CORR_ERR_MASK_epf 0x4050059 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_CORR_ERR_MASK_epf 0x4050059 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_CORR_ERR_MASK_epf 0x4050459 -#define mmnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf 0x405005A -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf 0x405005A -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf 0x405045A -#define mmnbif_gpu_PCIE_HDR_LOG0_epf 0x405005B -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG0_epf 0x405005B -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG0_epf 0x405045B -#define mmnbif_gpu_PCIE_HDR_LOG1_epf 0x405005C -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG1_epf 0x405005C -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG1_epf 0x405045C -#define mmnbif_gpu_PCIE_HDR_LOG2_epf 0x405005D -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG2_epf 0x405005D -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG2_epf 0x405045D -#define mmnbif_gpu_PCIE_HDR_LOG3_epf 0x405005E -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG3_epf 0x405005E -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG3_epf 0x405045E -#define mmnbif_gpu_PCIE_ROOT_ERR_CMD_epf 0x405005F -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ROOT_ERR_CMD_epf 0x405005F -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ROOT_ERR_CMD_epf 0x405045F -#define mmnbif_gpu_PCIE_ROOT_ERR_STATUS_epf 0x4050060 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ROOT_ERR_STATUS_epf 0x4050060 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ROOT_ERR_STATUS_epf 0x4050460 -#define mmnbif_gpu_PCIE_ERR_SRC_ID_epf 0x4050061 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ERR_SRC_ID_epf 0x4050061 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ERR_SRC_ID_epf 0x4050461 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG0_epf 0x4050062 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf 0x4050062 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf 0x4050462 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG1_epf 0x4050063 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf 0x4050063 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf 0x4050463 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG2_epf 0x4050064 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf 0x4050064 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf 0x4050464 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG3_epf 0x4050065 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf 0x4050065 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf 0x4050465 -#define mmnbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf 0x4050080 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf 0x4050080 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf 0x4050480 -#define mmnbif_gpu_PCIE_BAR1_CAP_epf 0x4050081 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR1_CAP_epf 0x4050081 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR1_CAP_epf 0x4050481 -#define mmnbif_gpu_PCIE_BAR1_CNTL_epf 0x4050082 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR1_CNTL_epf 0x4050082 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR1_CNTL_epf 0x4050482 -#define mmnbif_gpu_PCIE_BAR2_CAP_epf 0x4050083 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR2_CAP_epf 0x4050083 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR2_CAP_epf 0x4050483 -#define mmnbif_gpu_PCIE_BAR2_CNTL_epf 0x4050084 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR2_CNTL_epf 0x4050084 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR2_CNTL_epf 0x4050484 -#define mmnbif_gpu_PCIE_BAR3_CAP_epf 0x4050085 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR3_CAP_epf 0x4050085 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR3_CAP_epf 0x4050485 -#define mmnbif_gpu_PCIE_BAR3_CNTL_epf 0x4050086 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR3_CNTL_epf 0x4050086 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR3_CNTL_epf 0x4050486 -#define mmnbif_gpu_PCIE_BAR4_CAP_epf 0x4050087 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR4_CAP_epf 0x4050087 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR4_CAP_epf 0x4050487 -#define mmnbif_gpu_PCIE_BAR4_CNTL_epf 0x4050088 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR4_CNTL_epf 0x4050088 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR4_CNTL_epf 0x4050488 -#define mmnbif_gpu_PCIE_BAR5_CAP_epf 0x4050089 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR5_CAP_epf 0x4050089 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR5_CAP_epf 0x4050489 -#define mmnbif_gpu_PCIE_BAR5_CNTL_epf 0x405008A -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR5_CNTL_epf 0x405008A -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR5_CNTL_epf 0x405048A -#define mmnbif_gpu_PCIE_BAR6_CAP_epf 0x405008B -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR6_CAP_epf 0x405008B -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR6_CAP_epf 0x405048B -#define mmnbif_gpu_PCIE_BAR6_CNTL_epf 0x405008C -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_BAR6_CNTL_epf 0x405008C -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_BAR6_CNTL_epf 0x405048C -#define mmnbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf 0x4050090 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf 0x4050090 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf 0x4050490 -#define mmnbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf 0x4050091 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf 0x4050091 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf 0x4050491 -#define mmnbif_gpu_PCIE_PWR_BUDGET_DATA_epf 0x4050092 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_DATA_epf 0x4050092 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_DATA_epf 0x4050492 -#define mmnbif_gpu_PCIE_PWR_BUDGET_CAP_epf 0x4050093 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_CAP_epf 0x4050093 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_CAP_epf 0x4050493 -#define mmnbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf 0x4050094 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf 0x4050094 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf 0x4050494 -#define mmnbif_gpu_PCIE_DPA_CAP_epf 0x4050095 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_CAP_epf 0x4050095 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_CAP_epf 0x4050495 -#define mmnbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf 0x4050096 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf 0x4050096 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf 0x4050496 -#define mmnbif_gpu_PCIE_DPA_STATUS_epf 0x4050097 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_STATUS_epf 0x4050097 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_STATUS_epf 0x4050497 -#define mmnbif_gpu_PCIE_DPA_CNTL_epf 0x4050097 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_CNTL_epf 0x4050097 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_CNTL_epf 0x4050497 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf 0x4050098 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf 0x4050098 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf 0x4050498 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf 0x4050098 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf 0x4050098 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf 0x4050498 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf 0x4050098 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf 0x4050098 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf 0x4050498 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf 0x4050098 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf 0x4050098 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf 0x4050498 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf 0x4050099 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf 0x4050099 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf 0x4050499 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf 0x4050099 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf 0x4050099 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf 0x4050499 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf 0x4050099 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf 0x4050099 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf 0x4050499 -#define mmnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf 0x4050099 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf 0x4050099 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf 0x4050499 -#define mmnbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf 0x405009C -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf 0x405009C -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf 0x405049C -#define mmnbif_gpu_PCIE_LINK_CNTL3_epf 0x405009D -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LINK_CNTL3_epf 0x405009D -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LINK_CNTL3_epf 0x405049D -#define mmnbif_gpu_PCIE_LANE_ERROR_STATUS_epf 0x405009E -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_ERROR_STATUS_epf 0x405009E -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_ERROR_STATUS_epf 0x405049E -#define mmnbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf 0x405009F -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf 0x405009F -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf 0x405049F -#define mmnbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf 0x405009F -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf 0x405009F -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf 0x405049F -#define mmnbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf 0x40500A0 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf 0x40500A0 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf 0x40504A0 -#define mmnbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf 0x40500A0 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf 0x40500A0 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf 0x40504A0 -#define mmnbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf 0x40500A1 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf 0x40500A1 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf 0x40504A1 -#define mmnbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf 0x40500A1 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf 0x40500A1 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf 0x40504A1 -#define mmnbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf 0x40500A2 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf 0x40500A2 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf 0x40504A2 -#define mmnbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf 0x40500A2 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf 0x40500A2 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf 0x40504A2 -#define mmnbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf 0x40500A3 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf 0x40500A3 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf 0x40504A3 -#define mmnbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf 0x40500A3 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf 0x40500A3 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf 0x40504A3 -#define mmnbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf 0x40500A4 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf 0x40500A4 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf 0x40504A4 -#define mmnbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf 0x40500A4 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf 0x40500A4 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf 0x40504A4 -#define mmnbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf 0x40500A5 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf 0x40500A5 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf 0x40504A5 -#define mmnbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf 0x40500A5 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf 0x40500A5 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf 0x40504A5 -#define mmnbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf 0x40500A6 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf 0x40500A6 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf 0x40504A6 -#define mmnbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf 0x40500A6 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf 0x40500A6 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf 0x40504A6 -#define mmnbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf 0x40500A8 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf 0x40500A8 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf 0x40504A8 -#define mmnbif_gpu_PCIE_ACS_CAP_epf 0x40500A9 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_CAP_epf 0x40500A9 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_CAP_epf 0x40504A9 -#define mmnbif_gpu_PCIE_ACS_CNTL_epf 0x40500A9 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_CNTL_epf 0x40500A9 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_CNTL_epf 0x40504A9 -#define mmnbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf 0x40500AC -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf 0x40500AC -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf 0x40504AC -#define mmnbif_gpu_PCIE_ATS_CAP_epf 0x40500AD -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_CAP_epf 0x40500AD -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_CAP_epf 0x40504AD -#define mmnbif_gpu_PCIE_ATS_CNTL_epf 0x40500AD -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_CNTL_epf 0x40500AD -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_CNTL_epf 0x40504AD -#define mmnbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf 0x40500B0 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf 0x40500B0 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf 0x40504B0 -#define mmnbif_gpu_PCIE_PAGE_REQ_CNTL_epf 0x40500B1 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_CNTL_epf 0x40500B1 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_CNTL_epf 0x40504B1 -#define mmnbif_gpu_PCIE_PAGE_REQ_STATUS_epf 0x40500B1 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_STATUS_epf 0x40500B1 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_STATUS_epf 0x40504B1 -#define mmnbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf 0x40500B2 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf 0x40500B2 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf 0x40504B2 -#define mmnbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf 0x40500B3 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf 0x40500B3 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf 0x40504B3 -#define mmnbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf 0x40500B4 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf 0x40500B4 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf 0x40504B4 -#define mmnbif_gpu_PCIE_PASID_CAP_epf 0x40500B5 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_CAP_epf 0x40500B5 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_CAP_epf 0x40504B5 -#define mmnbif_gpu_PCIE_PASID_CNTL_epf 0x40500B5 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_CNTL_epf 0x40500B5 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_CNTL_epf 0x40504B5 -#define mmnbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf 0x40500B8 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf 0x40500B8 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf 0x40504B8 -#define mmnbif_gpu_PCIE_TPH_REQR_CAP_epf 0x40500B9 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_CAP_epf 0x40500B9 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_CAP_epf 0x40504B9 -#define mmnbif_gpu_PCIE_TPH_REQR_CNTL_epf 0x40500BA -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_CNTL_epf 0x40500BA -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_CNTL_epf 0x40504BA -#define mmnbif_gpu_PCIE_MC_ENH_CAP_LIST_epf 0x40500BC -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf 0x40500BC -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf 0x40504BC -#define mmnbif_gpu_PCIE_MC_CAP_epf 0x40500BD -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_CAP_epf 0x40500BD -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_CAP_epf 0x40504BD -#define mmnbif_gpu_PCIE_MC_CNTL_epf 0x40500BD -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_CNTL_epf 0x40500BD -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_CNTL_epf 0x40504BD -#define mmnbif_gpu_PCIE_MC_ADDR0_epf 0x40500BE -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ADDR0_epf 0x40500BE -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ADDR0_epf 0x40504BE -#define mmnbif_gpu_PCIE_MC_ADDR1_epf 0x40500BF -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ADDR1_epf 0x40500BF -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ADDR1_epf 0x40504BF -#define mmnbif_gpu_PCIE_MC_RCV0_epf 0x40500C0 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_RCV0_epf 0x40500C0 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_RCV0_epf 0x40504C0 -#define mmnbif_gpu_PCIE_MC_RCV1_epf 0x40500C1 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_RCV1_epf 0x40500C1 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_RCV1_epf 0x40504C1 -#define mmnbif_gpu_PCIE_MC_BLOCK_ALL0_epf 0x40500C2 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_ALL0_epf 0x40500C2 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_ALL0_epf 0x40504C2 -#define mmnbif_gpu_PCIE_MC_BLOCK_ALL1_epf 0x40500C3 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_ALL1_epf 0x40500C3 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_ALL1_epf 0x40504C3 -#define mmnbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf 0x40500C4 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf 0x40500C4 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf 0x40504C4 -#define mmnbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf 0x40500C5 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf 0x40500C5 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf 0x40504C5 -#define mmnbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf 0x40500C8 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf 0x40500C8 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf 0x40504C8 -#define mmnbif_gpu_PCIE_LTR_CAP_epf 0x40500C9 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_LTR_CAP_epf 0x40500C9 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_LTR_CAP_epf 0x40504C9 -#define mmnbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf 0x40500CA -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf 0x40500CA -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf 0x40504CA -#define mmnbif_gpu_PCIE_ARI_CAP_epf 0x40500CB -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_CAP_epf 0x40500CB -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_CAP_epf 0x40504CB -#define mmnbif_gpu_PCIE_ARI_CNTL_epf 0x40500CB -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_CNTL_epf 0x40500CB -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_CNTL_epf 0x40504CB -#define mmnbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf 0x40500CC -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf 0x40500CC -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf 0x40504CC -#define mmnbif_gpu_PCIE_SRIOV_CAP_epf 0x40500CD -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_CAP_epf 0x40500CD -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_CAP_epf 0x40504CD -#define mmnbif_gpu_PCIE_SRIOV_CONTROL_epf 0x40500CE -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_CONTROL_epf 0x40500CE -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_CONTROL_epf 0x40504CE -#define mmnbif_gpu_PCIE_SRIOV_STATUS_epf 0x40500CE -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_STATUS_epf 0x40500CE -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_STATUS_epf 0x40504CE -#define mmnbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf 0x40500CF -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf 0x40500CF -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf 0x40504CF -#define mmnbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf 0x40500CF -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf 0x40500CF -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf 0x40504CF -#define mmnbif_gpu_PCIE_SRIOV_NUM_VFS_epf 0x40500D0 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_NUM_VFS_epf 0x40500D0 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_NUM_VFS_epf 0x40504D0 -#define mmnbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf 0x40500D0 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf 0x40500D0 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf 0x40504D0 -#define mmnbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf 0x40500D1 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf 0x40500D1 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf 0x40504D1 -#define mmnbif_gpu_PCIE_SRIOV_VF_STRIDE_epf 0x40500D1 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf 0x40500D1 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf 0x40504D1 -#define mmnbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf 0x40500D2 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf 0x40500D2 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf 0x40504D2 -#define mmnbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf 0x40500D3 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf 0x40500D3 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf 0x40504D3 -#define mmnbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf 0x40500D4 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf 0x40500D4 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf 0x40504D4 -#define mmnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf 0x40500D5 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf 0x40500D5 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf 0x40504D5 -#define mmnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf 0x40500D6 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf 0x40500D6 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf 0x40504D6 -#define mmnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf 0x40500D7 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf 0x40500D7 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf 0x40504D7 -#define mmnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf 0x40500D8 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf 0x40500D8 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf 0x40504D8 -#define mmnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf 0x40500D9 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf 0x40500D9 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf 0x40504D9 -#define mmnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf 0x40500DA -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf 0x40500DA -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf 0x40504DA -#define mmnbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf 0x40500DB -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf 0x40500DB -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf 0x40504DB -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf 0x4050100 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf 0x4050100 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf 0x4050500 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf 0x4050101 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf 0x4050101 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf 0x4050501 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf 0x4050102 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf 0x4050102 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf 0x4050502 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf 0x4050103 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf 0x4050103 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf 0x4050503 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf 0x4050104 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf 0x4050104 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf 0x4050504 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf 0x4050105 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf 0x4050105 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf 0x4050505 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf 0x4050106 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf 0x4050106 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf 0x4050506 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf 0x4050107 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf 0x4050107 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf 0x4050507 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf 0x4050108 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf 0x4050108 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf 0x4050508 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf 0x4050109 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf 0x4050109 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf 0x4050509 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf 0x405010A -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf 0x405010A -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf 0x405050A -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf 0x405010B -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf 0x405010B -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf 0x405050B -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf 0x405010C -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf 0x405010C -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf 0x405050C -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf 0x405010D -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf 0x405010D -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf 0x405050D -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf 0x405010E -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf 0x405010E -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf 0x405050E -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf 0x405010F -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf 0x405010F -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf 0x405050F -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf 0x4050110 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf 0x4050110 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf 0x4050510 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf 0x4050111 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf 0x4050111 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf 0x4050511 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf 0x4050112 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf 0x4050112 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf 0x4050512 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf 0x4050113 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf 0x4050113 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf 0x4050513 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf 0x4050114 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf 0x4050114 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf 0x4050514 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf 0x4050115 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf 0x4050115 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf 0x4050515 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf 0x4050116 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf 0x4050116 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf 0x4050516 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf 0x4050117 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf 0x4050117 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf 0x4050517 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf 0x4050118 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf 0x4050118 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf 0x4050518 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf 0x4050119 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf 0x4050119 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf 0x4050519 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf 0x405011A -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf 0x405011A -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf 0x405051A -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf 0x405011B -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf 0x405011B -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf 0x405051B -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf 0x405011C -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf 0x405011C -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf 0x405051C -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf 0x405011D -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf 0x405011D -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf 0x405051D -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf 0x405011E -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf 0x405011E -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf 0x405051E -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf 0x405011F -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf 0x405011F -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf 0x405051F -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf 0x4050120 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf 0x4050120 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf 0x4050520 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf 0x4050121 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf 0x4050121 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf 0x4050521 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf 0x4050122 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf 0x4050122 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf 0x4050522 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf 0x4050123 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf 0x4050123 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf 0x4050523 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf 0x4050124 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf 0x4050124 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf 0x4050524 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf 0x4050125 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf 0x4050125 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf 0x4050525 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf 0x4050126 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf 0x4050126 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf 0x4050526 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf 0x4050127 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf 0x4050127 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf 0x4050527 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf 0x4050128 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf 0x4050128 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf 0x4050528 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf 0x4050129 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf 0x4050129 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf 0x4050529 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf 0x405012A -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf 0x405012A -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf 0x405052A -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf 0x405012B -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf 0x405012B -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf 0x405052B -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf 0x405012C -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf 0x405012C -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf 0x405052C -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf 0x405012D -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf 0x405012D -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf 0x405052D -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf 0x405012E -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf 0x405012E -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf 0x405052E -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf 0x405012F -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf 0x405012F -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf 0x405052F -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf 0x4050130 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf 0x4050130 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf 0x4050530 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf 0x4050131 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf 0x4050131 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf 0x4050531 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf 0x4050132 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf 0x4050132 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf 0x4050532 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf 0x4050133 -#define mmBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf 0x4050133 -#define mmBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf 0x4050533 -#define pcinbif_gpu_VENDOR_ID_epf 0x0000 -#define cfgnbif_gpu_VENDOR_ID_epf 0x0000 -#define pciBIF_CFG_EPF0_nbif_gpu_VENDOR_ID_epf 0x0000 -#define cfgBIF_CFG_EPF0_nbif_gpu_VENDOR_ID_epf 0x0000 -#define pciBIF_CFG_EPF1_nbif_gpu_VENDOR_ID_epf_alt_1 0x0000 -#define cfgBIF_CFG_EPF1_nbif_gpu_VENDOR_ID_epf_alt_1 0x0000 -#define pcinbif_gpu_DEVICE_ID_epf 0x0000 -#define cfgnbif_gpu_DEVICE_ID_epf 0x0000 -#define pciBIF_CFG_EPF0_nbif_gpu_DEVICE_ID_epf 0x0000 -#define cfgBIF_CFG_EPF0_nbif_gpu_DEVICE_ID_epf 0x0000 -#define pciBIF_CFG_EPF1_nbif_gpu_DEVICE_ID_epf_alt_1 0x0000 -#define cfgBIF_CFG_EPF1_nbif_gpu_DEVICE_ID_epf_alt_1 0x0000 -#define pcinbif_gpu_COMMAND_epf 0x0001 -#define cfgnbif_gpu_COMMAND_epf 0x0001 -#define pciBIF_CFG_EPF0_nbif_gpu_COMMAND_epf 0x0001 -#define cfgBIF_CFG_EPF0_nbif_gpu_COMMAND_epf 0x0001 -#define pciBIF_CFG_EPF1_nbif_gpu_COMMAND_epf_alt_1 0x0001 -#define cfgBIF_CFG_EPF1_nbif_gpu_COMMAND_epf_alt_1 0x0001 -#define pcinbif_gpu_STATUS_epf 0x0001 -#define cfgnbif_gpu_STATUS_epf 0x0001 -#define pciBIF_CFG_EPF0_nbif_gpu_STATUS_epf 0x0001 -#define cfgBIF_CFG_EPF0_nbif_gpu_STATUS_epf 0x0001 -#define pciBIF_CFG_EPF1_nbif_gpu_STATUS_epf_alt_1 0x0001 -#define cfgBIF_CFG_EPF1_nbif_gpu_STATUS_epf_alt_1 0x0001 -#define pcinbif_gpu_REVISION_ID_epf 0x0002 -#define cfgnbif_gpu_REVISION_ID_epf 0x0002 -#define pciBIF_CFG_EPF0_nbif_gpu_REVISION_ID_epf 0x0002 -#define cfgBIF_CFG_EPF0_nbif_gpu_REVISION_ID_epf 0x0002 -#define pciBIF_CFG_EPF1_nbif_gpu_REVISION_ID_epf_alt_1 0x0002 -#define cfgBIF_CFG_EPF1_nbif_gpu_REVISION_ID_epf_alt_1 0x0002 -#define pcinbif_gpu_PROG_INTERFACE_epf 0x0002 -#define cfgnbif_gpu_PROG_INTERFACE_epf 0x0002 -#define pciBIF_CFG_EPF0_nbif_gpu_PROG_INTERFACE_epf 0x0002 -#define cfgBIF_CFG_EPF0_nbif_gpu_PROG_INTERFACE_epf 0x0002 -#define pciBIF_CFG_EPF1_nbif_gpu_PROG_INTERFACE_epf_alt_1 0x0002 -#define cfgBIF_CFG_EPF1_nbif_gpu_PROG_INTERFACE_epf_alt_1 0x0002 -#define pcinbif_gpu_SUB_CLASS_epf 0x0002 -#define cfgnbif_gpu_SUB_CLASS_epf 0x0002 -#define pciBIF_CFG_EPF0_nbif_gpu_SUB_CLASS_epf 0x0002 -#define cfgBIF_CFG_EPF0_nbif_gpu_SUB_CLASS_epf 0x0002 -#define pciBIF_CFG_EPF1_nbif_gpu_SUB_CLASS_epf_alt_1 0x0002 -#define cfgBIF_CFG_EPF1_nbif_gpu_SUB_CLASS_epf_alt_1 0x0002 -#define pcinbif_gpu_BASE_CLASS_epf 0x0002 -#define cfgnbif_gpu_BASE_CLASS_epf 0x0002 -#define pciBIF_CFG_EPF0_nbif_gpu_BASE_CLASS_epf 0x0002 -#define cfgBIF_CFG_EPF0_nbif_gpu_BASE_CLASS_epf 0x0002 -#define pciBIF_CFG_EPF1_nbif_gpu_BASE_CLASS_epf_alt_1 0x0002 -#define cfgBIF_CFG_EPF1_nbif_gpu_BASE_CLASS_epf_alt_1 0x0002 -#define pcinbif_gpu_CACHE_LINE_epf 0x0003 -#define cfgnbif_gpu_CACHE_LINE_epf 0x0003 -#define pciBIF_CFG_EPF0_nbif_gpu_CACHE_LINE_epf 0x0003 -#define cfgBIF_CFG_EPF0_nbif_gpu_CACHE_LINE_epf 0x0003 -#define pciBIF_CFG_EPF1_nbif_gpu_CACHE_LINE_epf_alt_1 0x0003 -#define cfgBIF_CFG_EPF1_nbif_gpu_CACHE_LINE_epf_alt_1 0x0003 -#define pcinbif_gpu_LATENCY_epf 0x0003 -#define cfgnbif_gpu_LATENCY_epf 0x0003 -#define pciBIF_CFG_EPF0_nbif_gpu_LATENCY_epf 0x0003 -#define cfgBIF_CFG_EPF0_nbif_gpu_LATENCY_epf 0x0003 -#define pciBIF_CFG_EPF1_nbif_gpu_LATENCY_epf_alt_1 0x0003 -#define cfgBIF_CFG_EPF1_nbif_gpu_LATENCY_epf_alt_1 0x0003 -#define pcinbif_gpu_HEADER_epf 0x0003 -#define cfgnbif_gpu_HEADER_epf 0x0003 -#define pciBIF_CFG_EPF0_nbif_gpu_HEADER_epf 0x0003 -#define cfgBIF_CFG_EPF0_nbif_gpu_HEADER_epf 0x0003 -#define pciBIF_CFG_EPF1_nbif_gpu_HEADER_epf_alt_1 0x0003 -#define cfgBIF_CFG_EPF1_nbif_gpu_HEADER_epf_alt_1 0x0003 -#define pcinbif_gpu_BIST_epf 0x0003 -#define cfgnbif_gpu_BIST_epf 0x0003 -#define pciBIF_CFG_EPF0_nbif_gpu_BIST_epf 0x0003 -#define cfgBIF_CFG_EPF0_nbif_gpu_BIST_epf 0x0003 -#define pciBIF_CFG_EPF1_nbif_gpu_BIST_epf_alt_1 0x0003 -#define cfgBIF_CFG_EPF1_nbif_gpu_BIST_epf_alt_1 0x0003 -#define pcinbif_gpu_BASE_ADDR_1_epf 0x0004 -#define cfgnbif_gpu_BASE_ADDR_1_epf 0x0004 -#define pciBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_1_epf 0x0004 -#define cfgBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_1_epf 0x0004 -#define pciBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_1_epf_alt_1 0x0004 -#define cfgBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_1_epf_alt_1 0x0004 -#define pcinbif_gpu_BASE_ADDR_2_epf 0x0005 -#define cfgnbif_gpu_BASE_ADDR_2_epf 0x0005 -#define pciBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_2_epf 0x0005 -#define cfgBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_2_epf 0x0005 -#define pciBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_2_epf_alt_1 0x0005 -#define cfgBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_2_epf_alt_1 0x0005 -#define pcinbif_gpu_BASE_ADDR_3_epf 0x0006 -#define cfgnbif_gpu_BASE_ADDR_3_epf 0x0006 -#define pciBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_3_epf 0x0006 -#define cfgBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_3_epf 0x0006 -#define pciBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_3_epf_alt_1 0x0006 -#define cfgBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_3_epf_alt_1 0x0006 -#define pcinbif_gpu_BASE_ADDR_4_epf 0x0007 -#define cfgnbif_gpu_BASE_ADDR_4_epf 0x0007 -#define pciBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_4_epf 0x0007 -#define cfgBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_4_epf 0x0007 -#define pciBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_4_epf_alt_1 0x0007 -#define cfgBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_4_epf_alt_1 0x0007 -#define pcinbif_gpu_BASE_ADDR_5_epf 0x0008 -#define cfgnbif_gpu_BASE_ADDR_5_epf 0x0008 -#define pciBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_5_epf 0x0008 -#define cfgBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_5_epf 0x0008 -#define pciBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_5_epf_alt_1 0x0008 -#define cfgBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_5_epf_alt_1 0x0008 -#define pcinbif_gpu_BASE_ADDR_6_epf 0x0009 -#define cfgnbif_gpu_BASE_ADDR_6_epf 0x0009 -#define pciBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_6_epf 0x0009 -#define cfgBIF_CFG_EPF0_nbif_gpu_BASE_ADDR_6_epf 0x0009 -#define pciBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_6_epf_alt_1 0x0009 -#define cfgBIF_CFG_EPF1_nbif_gpu_BASE_ADDR_6_epf_alt_1 0x0009 -#define pcinbif_gpu_ROM_BASE_ADDR_epf 0x000C -#define cfgnbif_gpu_ROM_BASE_ADDR_epf 0x000C -#define pciBIF_CFG_EPF0_nbif_gpu_ROM_BASE_ADDR_epf 0x000C -#define cfgBIF_CFG_EPF0_nbif_gpu_ROM_BASE_ADDR_epf 0x000C -#define pciBIF_CFG_EPF1_nbif_gpu_ROM_BASE_ADDR_epf_alt_1 0x000C -#define cfgBIF_CFG_EPF1_nbif_gpu_ROM_BASE_ADDR_epf_alt_1 0x000C -#define pcinbif_gpu_CAP_PTR_epf 0x000D -#define cfgnbif_gpu_CAP_PTR_epf 0x000D -#define pciBIF_CFG_EPF0_nbif_gpu_CAP_PTR_epf 0x000D -#define cfgBIF_CFG_EPF0_nbif_gpu_CAP_PTR_epf 0x000D -#define pciBIF_CFG_EPF1_nbif_gpu_CAP_PTR_epf_alt_1 0x000D -#define cfgBIF_CFG_EPF1_nbif_gpu_CAP_PTR_epf_alt_1 0x000D -#define pcinbif_gpu_INTERRUPT_LINE_epf 0x000F -#define cfgnbif_gpu_INTERRUPT_LINE_epf 0x000F -#define pciBIF_CFG_EPF0_nbif_gpu_INTERRUPT_LINE_epf 0x000F -#define cfgBIF_CFG_EPF0_nbif_gpu_INTERRUPT_LINE_epf 0x000F -#define pciBIF_CFG_EPF1_nbif_gpu_INTERRUPT_LINE_epf_alt_1 0x000F -#define cfgBIF_CFG_EPF1_nbif_gpu_INTERRUPT_LINE_epf_alt_1 0x000F -#define pcinbif_gpu_INTERRUPT_PIN_epf 0x000F -#define cfgnbif_gpu_INTERRUPT_PIN_epf 0x000F -#define pciBIF_CFG_EPF0_nbif_gpu_INTERRUPT_PIN_epf 0x000F -#define cfgBIF_CFG_EPF0_nbif_gpu_INTERRUPT_PIN_epf 0x000F -#define pciBIF_CFG_EPF1_nbif_gpu_INTERRUPT_PIN_epf_alt_1 0x000F -#define cfgBIF_CFG_EPF1_nbif_gpu_INTERRUPT_PIN_epf_alt_1 0x000F -#define pcinbif_gpu_ADAPTER_ID_epf 0x000B -#define cfgnbif_gpu_ADAPTER_ID_epf 0x000B -#define pciBIF_CFG_EPF0_nbif_gpu_ADAPTER_ID_epf 0x000B -#define cfgBIF_CFG_EPF0_nbif_gpu_ADAPTER_ID_epf 0x000B -#define pciBIF_CFG_EPF1_nbif_gpu_ADAPTER_ID_epf_alt_1 0x000B -#define cfgBIF_CFG_EPF1_nbif_gpu_ADAPTER_ID_epf_alt_1 0x000B -#define pcinbif_gpu_MIN_GRANT_epf 0x000F -#define cfgnbif_gpu_MIN_GRANT_epf 0x000F -#define pciBIF_CFG_EPF0_nbif_gpu_MIN_GRANT_epf 0x000F -#define cfgBIF_CFG_EPF0_nbif_gpu_MIN_GRANT_epf 0x000F -#define pciBIF_CFG_EPF1_nbif_gpu_MIN_GRANT_epf_alt_1 0x000F -#define cfgBIF_CFG_EPF1_nbif_gpu_MIN_GRANT_epf_alt_1 0x000F -#define pcinbif_gpu_MAX_LATENCY_epf 0x000F -#define cfgnbif_gpu_MAX_LATENCY_epf 0x000F -#define pciBIF_CFG_EPF0_nbif_gpu_MAX_LATENCY_epf 0x000F -#define cfgBIF_CFG_EPF0_nbif_gpu_MAX_LATENCY_epf 0x000F -#define pciBIF_CFG_EPF1_nbif_gpu_MAX_LATENCY_epf_alt_1 0x000F -#define cfgBIF_CFG_EPF1_nbif_gpu_MAX_LATENCY_epf_alt_1 0x000F -#define pcinbif_gpu_VENDOR_CAP_LIST_epf 0x0012 -#define cfgnbif_gpu_VENDOR_CAP_LIST_epf 0x0012 -#define pciBIF_CFG_EPF0_nbif_gpu_VENDOR_CAP_LIST_epf 0x0012 -#define cfgBIF_CFG_EPF0_nbif_gpu_VENDOR_CAP_LIST_epf 0x0012 -#define pciBIF_CFG_EPF1_nbif_gpu_VENDOR_CAP_LIST_epf_alt_1 0x0012 -#define cfgBIF_CFG_EPF1_nbif_gpu_VENDOR_CAP_LIST_epf_alt_1 0x0012 -#define pcinbif_gpu_ADAPTER_ID_W_epf 0x0013 -#define cfgnbif_gpu_ADAPTER_ID_W_epf 0x0013 -#define pciBIF_CFG_EPF0_nbif_gpu_ADAPTER_ID_W_epf 0x0013 -#define cfgBIF_CFG_EPF0_nbif_gpu_ADAPTER_ID_W_epf 0x0013 -#define pciBIF_CFG_EPF1_nbif_gpu_ADAPTER_ID_W_epf_alt_1 0x0013 -#define cfgBIF_CFG_EPF1_nbif_gpu_ADAPTER_ID_W_epf_alt_1 0x0013 -#define pcinbif_gpu_PMI_CAP_LIST_epf 0x0014 -#define cfgnbif_gpu_PMI_CAP_LIST_epf 0x0014 -#define pciBIF_CFG_EPF0_nbif_gpu_PMI_CAP_LIST_epf 0x0014 -#define cfgBIF_CFG_EPF0_nbif_gpu_PMI_CAP_LIST_epf 0x0014 -#define pciBIF_CFG_EPF1_nbif_gpu_PMI_CAP_LIST_epf_alt_1 0x0014 -#define cfgBIF_CFG_EPF1_nbif_gpu_PMI_CAP_LIST_epf_alt_1 0x0014 -#define pcinbif_gpu_PMI_CAP_epf 0x0014 -#define cfgnbif_gpu_PMI_CAP_epf 0x0014 -#define pciBIF_CFG_EPF0_nbif_gpu_PMI_CAP_epf 0x0014 -#define cfgBIF_CFG_EPF0_nbif_gpu_PMI_CAP_epf 0x0014 -#define pciBIF_CFG_EPF1_nbif_gpu_PMI_CAP_epf_alt_1 0x0014 -#define cfgBIF_CFG_EPF1_nbif_gpu_PMI_CAP_epf_alt_1 0x0014 -#define pcinbif_gpu_PMI_STATUS_CNTL_epf 0x0015 -#define cfgnbif_gpu_PMI_STATUS_CNTL_epf 0x0015 -#define pciBIF_CFG_EPF0_nbif_gpu_PMI_STATUS_CNTL_epf 0x0015 -#define cfgBIF_CFG_EPF0_nbif_gpu_PMI_STATUS_CNTL_epf 0x0015 -#define pciBIF_CFG_EPF1_nbif_gpu_PMI_STATUS_CNTL_epf_alt_1 0x0015 -#define cfgBIF_CFG_EPF1_nbif_gpu_PMI_STATUS_CNTL_epf_alt_1 0x0015 -#define pcinbif_gpu_PCIE_CAP_LIST_epf 0x0019 -#define cfgnbif_gpu_PCIE_CAP_LIST_epf 0x0019 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_CAP_LIST_epf 0x0019 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_CAP_LIST_epf 0x0019 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_CAP_LIST_epf_alt_1 0x0019 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_CAP_LIST_epf_alt_1 0x0019 -#define pcinbif_gpu_PCIE_CAP_epf 0x0019 -#define cfgnbif_gpu_PCIE_CAP_epf 0x0019 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_CAP_epf 0x0019 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_CAP_epf 0x0019 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_CAP_epf_alt_1 0x0019 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_CAP_epf_alt_1 0x0019 -#define pcinbif_gpu_DEVICE_CAP_epf 0x001A -#define cfgnbif_gpu_DEVICE_CAP_epf 0x001A -#define pciBIF_CFG_EPF0_nbif_gpu_DEVICE_CAP_epf 0x001A -#define cfgBIF_CFG_EPF0_nbif_gpu_DEVICE_CAP_epf 0x001A -#define pciBIF_CFG_EPF1_nbif_gpu_DEVICE_CAP_epf_alt_1 0x001A -#define cfgBIF_CFG_EPF1_nbif_gpu_DEVICE_CAP_epf_alt_1 0x001A -#define pcinbif_gpu_DEVICE_CNTL_epf 0x001B -#define cfgnbif_gpu_DEVICE_CNTL_epf 0x001B -#define pciBIF_CFG_EPF0_nbif_gpu_DEVICE_CNTL_epf 0x001B -#define cfgBIF_CFG_EPF0_nbif_gpu_DEVICE_CNTL_epf 0x001B -#define pciBIF_CFG_EPF1_nbif_gpu_DEVICE_CNTL_epf_alt_1 0x001B -#define cfgBIF_CFG_EPF1_nbif_gpu_DEVICE_CNTL_epf_alt_1 0x001B -#define pcinbif_gpu_DEVICE_STATUS_epf 0x001B -#define cfgnbif_gpu_DEVICE_STATUS_epf 0x001B -#define pciBIF_CFG_EPF0_nbif_gpu_DEVICE_STATUS_epf 0x001B -#define cfgBIF_CFG_EPF0_nbif_gpu_DEVICE_STATUS_epf 0x001B -#define pciBIF_CFG_EPF1_nbif_gpu_DEVICE_STATUS_epf_alt_1 0x001B -#define cfgBIF_CFG_EPF1_nbif_gpu_DEVICE_STATUS_epf_alt_1 0x001B -#define pcinbif_gpu_LINK_CAP_epf 0x001C -#define cfgnbif_gpu_LINK_CAP_epf 0x001C -#define pciBIF_CFG_EPF0_nbif_gpu_LINK_CAP_epf 0x001C -#define cfgBIF_CFG_EPF0_nbif_gpu_LINK_CAP_epf 0x001C -#define pciBIF_CFG_EPF1_nbif_gpu_LINK_CAP_epf_alt_1 0x001C -#define cfgBIF_CFG_EPF1_nbif_gpu_LINK_CAP_epf_alt_1 0x001C -#define pcinbif_gpu_LINK_CNTL_epf 0x001D -#define cfgnbif_gpu_LINK_CNTL_epf 0x001D -#define pciBIF_CFG_EPF0_nbif_gpu_LINK_CNTL_epf 0x001D -#define cfgBIF_CFG_EPF0_nbif_gpu_LINK_CNTL_epf 0x001D -#define pciBIF_CFG_EPF1_nbif_gpu_LINK_CNTL_epf_alt_1 0x001D -#define cfgBIF_CFG_EPF1_nbif_gpu_LINK_CNTL_epf_alt_1 0x001D -#define pcinbif_gpu_LINK_STATUS_epf 0x001D -#define cfgnbif_gpu_LINK_STATUS_epf 0x001D -#define pciBIF_CFG_EPF0_nbif_gpu_LINK_STATUS_epf 0x001D -#define cfgBIF_CFG_EPF0_nbif_gpu_LINK_STATUS_epf 0x001D -#define pciBIF_CFG_EPF1_nbif_gpu_LINK_STATUS_epf_alt_1 0x001D -#define cfgBIF_CFG_EPF1_nbif_gpu_LINK_STATUS_epf_alt_1 0x001D -#define pcinbif_gpu_DEVICE_CAP2_epf 0x0022 -#define cfgnbif_gpu_DEVICE_CAP2_epf 0x0022 -#define pciBIF_CFG_EPF0_nbif_gpu_DEVICE_CAP2_epf 0x0022 -#define cfgBIF_CFG_EPF0_nbif_gpu_DEVICE_CAP2_epf 0x0022 -#define pciBIF_CFG_EPF1_nbif_gpu_DEVICE_CAP2_epf_alt_1 0x0022 -#define cfgBIF_CFG_EPF1_nbif_gpu_DEVICE_CAP2_epf_alt_1 0x0022 -#define pcinbif_gpu_DEVICE_CNTL2_epf 0x0023 -#define cfgnbif_gpu_DEVICE_CNTL2_epf 0x0023 -#define pciBIF_CFG_EPF0_nbif_gpu_DEVICE_CNTL2_epf 0x0023 -#define cfgBIF_CFG_EPF0_nbif_gpu_DEVICE_CNTL2_epf 0x0023 -#define pciBIF_CFG_EPF1_nbif_gpu_DEVICE_CNTL2_epf_alt_1 0x0023 -#define cfgBIF_CFG_EPF1_nbif_gpu_DEVICE_CNTL2_epf_alt_1 0x0023 -#define pcinbif_gpu_DEVICE_STATUS2_epf 0x0023 -#define cfgnbif_gpu_DEVICE_STATUS2_epf 0x0023 -#define pciBIF_CFG_EPF0_nbif_gpu_DEVICE_STATUS2_epf 0x0023 -#define cfgBIF_CFG_EPF0_nbif_gpu_DEVICE_STATUS2_epf 0x0023 -#define pciBIF_CFG_EPF1_nbif_gpu_DEVICE_STATUS2_epf_alt_1 0x0023 -#define cfgBIF_CFG_EPF1_nbif_gpu_DEVICE_STATUS2_epf_alt_1 0x0023 -#define pcinbif_gpu_LINK_CAP2_epf 0x0024 -#define cfgnbif_gpu_LINK_CAP2_epf 0x0024 -#define pciBIF_CFG_EPF0_nbif_gpu_LINK_CAP2_epf 0x0024 -#define cfgBIF_CFG_EPF0_nbif_gpu_LINK_CAP2_epf 0x0024 -#define pciBIF_CFG_EPF1_nbif_gpu_LINK_CAP2_epf_alt_1 0x0024 -#define cfgBIF_CFG_EPF1_nbif_gpu_LINK_CAP2_epf_alt_1 0x0024 -#define pcinbif_gpu_LINK_CNTL2_epf 0x0025 -#define cfgnbif_gpu_LINK_CNTL2_epf 0x0025 -#define pciBIF_CFG_EPF0_nbif_gpu_LINK_CNTL2_epf 0x0025 -#define cfgBIF_CFG_EPF0_nbif_gpu_LINK_CNTL2_epf 0x0025 -#define pciBIF_CFG_EPF1_nbif_gpu_LINK_CNTL2_epf_alt_1 0x0025 -#define cfgBIF_CFG_EPF1_nbif_gpu_LINK_CNTL2_epf_alt_1 0x0025 -#define pcinbif_gpu_LINK_STATUS2_epf 0x0025 -#define cfgnbif_gpu_LINK_STATUS2_epf 0x0025 -#define pciBIF_CFG_EPF0_nbif_gpu_LINK_STATUS2_epf 0x0025 -#define cfgBIF_CFG_EPF0_nbif_gpu_LINK_STATUS2_epf 0x0025 -#define pciBIF_CFG_EPF1_nbif_gpu_LINK_STATUS2_epf_alt_1 0x0025 -#define cfgBIF_CFG_EPF1_nbif_gpu_LINK_STATUS2_epf_alt_1 0x0025 -#define pcinbif_gpu_SLOT_CAP2_epf 0x0026 -#define cfgnbif_gpu_SLOT_CAP2_epf 0x0026 -#define pciBIF_CFG_EPF0_nbif_gpu_SLOT_CAP2_epf 0x0026 -#define cfgBIF_CFG_EPF0_nbif_gpu_SLOT_CAP2_epf 0x0026 -#define pciBIF_CFG_EPF1_nbif_gpu_SLOT_CAP2_epf_alt_1 0x0026 -#define cfgBIF_CFG_EPF1_nbif_gpu_SLOT_CAP2_epf_alt_1 0x0026 -#define pcinbif_gpu_SLOT_CNTL2_epf 0x0027 -#define cfgnbif_gpu_SLOT_CNTL2_epf 0x0027 -#define pciBIF_CFG_EPF0_nbif_gpu_SLOT_CNTL2_epf 0x0027 -#define cfgBIF_CFG_EPF0_nbif_gpu_SLOT_CNTL2_epf 0x0027 -#define pciBIF_CFG_EPF1_nbif_gpu_SLOT_CNTL2_epf_alt_1 0x0027 -#define cfgBIF_CFG_EPF1_nbif_gpu_SLOT_CNTL2_epf_alt_1 0x0027 -#define pcinbif_gpu_SLOT_STATUS2_epf 0x0027 -#define cfgnbif_gpu_SLOT_STATUS2_epf 0x0027 -#define pciBIF_CFG_EPF0_nbif_gpu_SLOT_STATUS2_epf 0x0027 -#define cfgBIF_CFG_EPF0_nbif_gpu_SLOT_STATUS2_epf 0x0027 -#define pciBIF_CFG_EPF1_nbif_gpu_SLOT_STATUS2_epf_alt_1 0x0027 -#define cfgBIF_CFG_EPF1_nbif_gpu_SLOT_STATUS2_epf_alt_1 0x0027 -#define pcinbif_gpu_MSI_CAP_LIST_epf 0x0028 -#define cfgnbif_gpu_MSI_CAP_LIST_epf 0x0028 -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_CAP_LIST_epf 0x0028 -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_CAP_LIST_epf 0x0028 -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_CAP_LIST_epf_alt_1 0x0028 -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_CAP_LIST_epf_alt_1 0x0028 -#define pcinbif_gpu_MSI_MSG_CNTL_epf 0x0028 -#define cfgnbif_gpu_MSI_MSG_CNTL_epf 0x0028 -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_MSG_CNTL_epf 0x0028 -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_MSG_CNTL_epf 0x0028 -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_MSG_CNTL_epf_alt_1 0x0028 -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_MSG_CNTL_epf_alt_1 0x0028 -#define pcinbif_gpu_MSI_MSG_ADDR_LO_epf 0x0029 -#define cfgnbif_gpu_MSI_MSG_ADDR_LO_epf 0x0029 -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_MSG_ADDR_LO_epf 0x0029 -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_MSG_ADDR_LO_epf 0x0029 -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_MSG_ADDR_LO_epf_alt_1 0x0029 -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_MSG_ADDR_LO_epf_alt_1 0x0029 -#define pcinbif_gpu_MSI_MSG_ADDR_HI_epf 0x002A -#define cfgnbif_gpu_MSI_MSG_ADDR_HI_epf 0x002A -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_MSG_ADDR_HI_epf 0x002A -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_MSG_ADDR_HI_epf 0x002A -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_MSG_ADDR_HI_epf_alt_1 0x002A -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_MSG_ADDR_HI_epf_alt_1 0x002A -#define pcinbif_gpu_MSI_MSG_DATA_64_epf 0x002B -#define cfgnbif_gpu_MSI_MSG_DATA_64_epf 0x002B -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_MSG_DATA_64_epf 0x002B -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_MSG_DATA_64_epf 0x002B -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_MSG_DATA_64_epf_alt_1 0x002B -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_MSG_DATA_64_epf_alt_1 0x002B -#define pcinbif_gpu_MSI_MSG_DATA_epf 0x002A -#define cfgnbif_gpu_MSI_MSG_DATA_epf 0x002A -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_MSG_DATA_epf 0x002A -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_MSG_DATA_epf 0x002A -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_MSG_DATA_epf_alt_1 0x002A -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_MSG_DATA_epf_alt_1 0x002A -#define pcinbif_gpu_MSI_MASK_epf 0x002B -#define cfgnbif_gpu_MSI_MASK_epf 0x002B -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_MASK_epf 0x002B -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_MASK_epf 0x002B -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_MASK_epf_alt_1 0x002B -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_MASK_epf_alt_1 0x002B -#define pcinbif_gpu_MSI_PENDING_epf 0x002C -#define cfgnbif_gpu_MSI_PENDING_epf 0x002C -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_PENDING_epf 0x002C -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_PENDING_epf 0x002C -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_PENDING_epf_alt_1 0x002C -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_PENDING_epf_alt_1 0x002C -#define pcinbif_gpu_MSI_MASK_64_epf 0x002C -#define cfgnbif_gpu_MSI_MASK_64_epf 0x002C -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_MASK_64_epf 0x002C -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_MASK_64_epf 0x002C -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_MASK_64_epf_alt_1 0x002C -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_MASK_64_epf_alt_1 0x002C -#define pcinbif_gpu_MSI_PENDING_64_epf 0x002D -#define cfgnbif_gpu_MSI_PENDING_64_epf 0x002D -#define pciBIF_CFG_EPF0_nbif_gpu_MSI_PENDING_64_epf 0x002D -#define cfgBIF_CFG_EPF0_nbif_gpu_MSI_PENDING_64_epf 0x002D -#define pciBIF_CFG_EPF1_nbif_gpu_MSI_PENDING_64_epf_alt_1 0x002D -#define cfgBIF_CFG_EPF1_nbif_gpu_MSI_PENDING_64_epf_alt_1 0x002D -#define pcinbif_gpu_MSIX_CAP_LIST_epf 0x0030 -#define cfgnbif_gpu_MSIX_CAP_LIST_epf 0x0030 -#define pciBIF_CFG_EPF0_nbif_gpu_MSIX_CAP_LIST_epf 0x0030 -#define cfgBIF_CFG_EPF0_nbif_gpu_MSIX_CAP_LIST_epf 0x0030 -#define pciBIF_CFG_EPF1_nbif_gpu_MSIX_CAP_LIST_epf_alt_1 0x0030 -#define cfgBIF_CFG_EPF1_nbif_gpu_MSIX_CAP_LIST_epf_alt_1 0x0030 -#define pcinbif_gpu_MSIX_MSG_CNTL_epf 0x0030 -#define cfgnbif_gpu_MSIX_MSG_CNTL_epf 0x0030 -#define pciBIF_CFG_EPF0_nbif_gpu_MSIX_MSG_CNTL_epf 0x0030 -#define cfgBIF_CFG_EPF0_nbif_gpu_MSIX_MSG_CNTL_epf 0x0030 -#define pciBIF_CFG_EPF1_nbif_gpu_MSIX_MSG_CNTL_epf_alt_1 0x0030 -#define cfgBIF_CFG_EPF1_nbif_gpu_MSIX_MSG_CNTL_epf_alt_1 0x0030 -#define pcinbif_gpu_MSIX_TABLE_epf 0x0031 -#define cfgnbif_gpu_MSIX_TABLE_epf 0x0031 -#define pciBIF_CFG_EPF0_nbif_gpu_MSIX_TABLE_epf 0x0031 -#define cfgBIF_CFG_EPF0_nbif_gpu_MSIX_TABLE_epf 0x0031 -#define pciBIF_CFG_EPF1_nbif_gpu_MSIX_TABLE_epf_alt_1 0x0031 -#define cfgBIF_CFG_EPF1_nbif_gpu_MSIX_TABLE_epf_alt_1 0x0031 -#define pcinbif_gpu_MSIX_PBA_epf 0x0032 -#define cfgnbif_gpu_MSIX_PBA_epf 0x0032 -#define pciBIF_CFG_EPF0_nbif_gpu_MSIX_PBA_epf 0x0032 -#define cfgBIF_CFG_EPF0_nbif_gpu_MSIX_PBA_epf 0x0032 -#define pciBIF_CFG_EPF1_nbif_gpu_MSIX_PBA_epf_alt_1 0x0032 -#define cfgBIF_CFG_EPF1_nbif_gpu_MSIX_PBA_epf_alt_1 0x0032 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf 0x0040 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf 0x0040 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf 0x0040 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf 0x0040 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf_alt_1 0x0040 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf_alt_1 0x0040 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf 0x0041 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf 0x0041 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf 0x0041 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf 0x0041 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf_alt_1 0x0041 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf_alt_1 0x0041 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC1_epf 0x0042 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC1_epf 0x0042 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf 0x0042 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf 0x0042 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf_alt_1 0x0042 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf_alt_1 0x0042 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC2_epf 0x0043 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC2_epf 0x0043 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf 0x0043 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf 0x0043 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf_alt_1 0x0043 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf_alt_1 0x0043 -#define pcinbif_gpu_PCIE_VC_ENH_CAP_LIST_epf 0x0044 -#define cfgnbif_gpu_PCIE_VC_ENH_CAP_LIST_epf 0x0044 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf 0x0044 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf 0x0044 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf_alt_1 0x0044 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf_alt_1 0x0044 -#define pcinbif_gpu_PCIE_PORT_VC_CAP_REG1_epf 0x0045 -#define cfgnbif_gpu_PCIE_PORT_VC_CAP_REG1_epf 0x0045 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf 0x0045 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf 0x0045 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf_alt_1 0x0045 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf_alt_1 0x0045 -#define pcinbif_gpu_PCIE_PORT_VC_CAP_REG2_epf 0x0046 -#define cfgnbif_gpu_PCIE_PORT_VC_CAP_REG2_epf 0x0046 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf 0x0046 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf 0x0046 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf_alt_1 0x0046 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf_alt_1 0x0046 -#define pcinbif_gpu_PCIE_PORT_VC_CNTL_epf 0x0047 -#define cfgnbif_gpu_PCIE_PORT_VC_CNTL_epf 0x0047 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CNTL_epf 0x0047 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_CNTL_epf 0x0047 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CNTL_epf_alt_1 0x0047 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_CNTL_epf_alt_1 0x0047 -#define pcinbif_gpu_PCIE_PORT_VC_STATUS_epf 0x0047 -#define cfgnbif_gpu_PCIE_PORT_VC_STATUS_epf 0x0047 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_STATUS_epf 0x0047 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PORT_VC_STATUS_epf 0x0047 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_STATUS_epf_alt_1 0x0047 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PORT_VC_STATUS_epf_alt_1 0x0047 -#define pcinbif_gpu_PCIE_VC0_RESOURCE_CAP_epf 0x0048 -#define cfgnbif_gpu_PCIE_VC0_RESOURCE_CAP_epf 0x0048 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf 0x0048 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf 0x0048 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf_alt_1 0x0048 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf_alt_1 0x0048 -#define pcinbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf 0x0049 -#define cfgnbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf 0x0049 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf 0x0049 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf 0x0049 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf_alt_1 0x0049 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf_alt_1 0x0049 -#define pcinbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf 0x004A -#define cfgnbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf 0x004A -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf 0x004A -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf 0x004A -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf_alt_1 0x004A -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf_alt_1 0x004A -#define pcinbif_gpu_PCIE_VC1_RESOURCE_CAP_epf 0x004B -#define cfgnbif_gpu_PCIE_VC1_RESOURCE_CAP_epf 0x004B -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf 0x004B -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf 0x004B -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf_alt_1 0x004B -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf_alt_1 0x004B -#define pcinbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf 0x004C -#define cfgnbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf 0x004C -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf 0x004C -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf 0x004C -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf_alt_1 0x004C -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf_alt_1 0x004C -#define pcinbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf 0x004D -#define cfgnbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf 0x004D -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf 0x004D -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf 0x004D -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf_alt_1 0x004D -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf_alt_1 0x004D -#define pcinbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf 0x0050 -#define cfgnbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf 0x0050 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf 0x0050 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf 0x0050 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf_alt_1 0x0050 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf_alt_1 0x0050 -#define pcinbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf 0x0051 -#define cfgnbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf 0x0051 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf 0x0051 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf 0x0051 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf_alt_1 0x0051 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf_alt_1 0x0051 -#define pcinbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf 0x0052 -#define cfgnbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf 0x0052 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf 0x0052 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf 0x0052 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf_alt_1 0x0052 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf_alt_1 0x0052 -#define pcinbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf 0x0054 -#define cfgnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf 0x0054 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf 0x0054 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf 0x0054 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf_alt_1 0x0054 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf_alt_1 0x0054 -#define pcinbif_gpu_PCIE_UNCORR_ERR_STATUS_epf 0x0055 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_STATUS_epf 0x0055 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf 0x0055 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf 0x0055 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf_alt_1 0x0055 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf_alt_1 0x0055 -#define pcinbif_gpu_PCIE_UNCORR_ERR_MASK_epf 0x0056 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_MASK_epf 0x0056 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_MASK_epf 0x0056 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_MASK_epf 0x0056 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_MASK_epf_alt_1 0x0056 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_MASK_epf_alt_1 0x0056 -#define pcinbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf 0x0057 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf 0x0057 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf 0x0057 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf 0x0057 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf_alt_1 0x0057 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf_alt_1 0x0057 -#define pcinbif_gpu_PCIE_CORR_ERR_STATUS_epf 0x0058 -#define cfgnbif_gpu_PCIE_CORR_ERR_STATUS_epf 0x0058 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_CORR_ERR_STATUS_epf 0x0058 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_CORR_ERR_STATUS_epf 0x0058 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_CORR_ERR_STATUS_epf_alt_1 0x0058 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_CORR_ERR_STATUS_epf_alt_1 0x0058 -#define pcinbif_gpu_PCIE_CORR_ERR_MASK_epf 0x0059 -#define cfgnbif_gpu_PCIE_CORR_ERR_MASK_epf 0x0059 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_CORR_ERR_MASK_epf 0x0059 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_CORR_ERR_MASK_epf 0x0059 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_CORR_ERR_MASK_epf_alt_1 0x0059 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_CORR_ERR_MASK_epf_alt_1 0x0059 -#define pcinbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf 0x005A -#define cfgnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf 0x005A -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf 0x005A -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf 0x005A -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf_alt_1 0x005A -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf_alt_1 0x005A -#define pcinbif_gpu_PCIE_HDR_LOG0_epf 0x005B -#define cfgnbif_gpu_PCIE_HDR_LOG0_epf 0x005B -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG0_epf 0x005B -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG0_epf 0x005B -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG0_epf_alt_1 0x005B -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG0_epf_alt_1 0x005B -#define pcinbif_gpu_PCIE_HDR_LOG1_epf 0x005C -#define cfgnbif_gpu_PCIE_HDR_LOG1_epf 0x005C -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG1_epf 0x005C -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG1_epf 0x005C -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG1_epf_alt_1 0x005C -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG1_epf_alt_1 0x005C -#define pcinbif_gpu_PCIE_HDR_LOG2_epf 0x005D -#define cfgnbif_gpu_PCIE_HDR_LOG2_epf 0x005D -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG2_epf 0x005D -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG2_epf 0x005D -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG2_epf_alt_1 0x005D -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG2_epf_alt_1 0x005D -#define pcinbif_gpu_PCIE_HDR_LOG3_epf 0x005E -#define cfgnbif_gpu_PCIE_HDR_LOG3_epf 0x005E -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG3_epf 0x005E -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_HDR_LOG3_epf 0x005E -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG3_epf_alt_1 0x005E -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_HDR_LOG3_epf_alt_1 0x005E -#define pcinbif_gpu_PCIE_ROOT_ERR_CMD_epf 0x005F -#define cfgnbif_gpu_PCIE_ROOT_ERR_CMD_epf 0x005F -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ROOT_ERR_CMD_epf 0x005F -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ROOT_ERR_CMD_epf 0x005F -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ROOT_ERR_CMD_epf_alt_1 0x005F -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ROOT_ERR_CMD_epf_alt_1 0x005F -#define pcinbif_gpu_PCIE_ROOT_ERR_STATUS_epf 0x0060 -#define cfgnbif_gpu_PCIE_ROOT_ERR_STATUS_epf 0x0060 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ROOT_ERR_STATUS_epf 0x0060 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ROOT_ERR_STATUS_epf 0x0060 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ROOT_ERR_STATUS_epf_alt_1 0x0060 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ROOT_ERR_STATUS_epf_alt_1 0x0060 -#define pcinbif_gpu_PCIE_ERR_SRC_ID_epf 0x0061 -#define cfgnbif_gpu_PCIE_ERR_SRC_ID_epf 0x0061 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ERR_SRC_ID_epf 0x0061 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ERR_SRC_ID_epf 0x0061 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ERR_SRC_ID_epf_alt_1 0x0061 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ERR_SRC_ID_epf_alt_1 0x0061 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG0_epf 0x0062 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG0_epf 0x0062 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf 0x0062 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf 0x0062 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf_alt_1 0x0062 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf_alt_1 0x0062 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG1_epf 0x0063 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG1_epf 0x0063 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf 0x0063 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf 0x0063 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf_alt_1 0x0063 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf_alt_1 0x0063 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG2_epf 0x0064 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG2_epf 0x0064 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf 0x0064 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf 0x0064 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf_alt_1 0x0064 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf_alt_1 0x0064 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG3_epf 0x0065 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG3_epf 0x0065 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf 0x0065 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf 0x0065 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf_alt_1 0x0065 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf_alt_1 0x0065 -#define pcinbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf 0x0080 -#define cfgnbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf 0x0080 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf 0x0080 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf 0x0080 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf_alt_1 0x0080 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf_alt_1 0x0080 -#define pcinbif_gpu_PCIE_BAR1_CAP_epf 0x0081 -#define cfgnbif_gpu_PCIE_BAR1_CAP_epf 0x0081 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR1_CAP_epf 0x0081 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR1_CAP_epf 0x0081 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR1_CAP_epf_alt_1 0x0081 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR1_CAP_epf_alt_1 0x0081 -#define pcinbif_gpu_PCIE_BAR1_CNTL_epf 0x0082 -#define cfgnbif_gpu_PCIE_BAR1_CNTL_epf 0x0082 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR1_CNTL_epf 0x0082 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR1_CNTL_epf 0x0082 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR1_CNTL_epf_alt_1 0x0082 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR1_CNTL_epf_alt_1 0x0082 -#define pcinbif_gpu_PCIE_BAR2_CAP_epf 0x0083 -#define cfgnbif_gpu_PCIE_BAR2_CAP_epf 0x0083 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR2_CAP_epf 0x0083 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR2_CAP_epf 0x0083 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR2_CAP_epf_alt_1 0x0083 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR2_CAP_epf_alt_1 0x0083 -#define pcinbif_gpu_PCIE_BAR2_CNTL_epf 0x0084 -#define cfgnbif_gpu_PCIE_BAR2_CNTL_epf 0x0084 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR2_CNTL_epf 0x0084 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR2_CNTL_epf 0x0084 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR2_CNTL_epf_alt_1 0x0084 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR2_CNTL_epf_alt_1 0x0084 -#define pcinbif_gpu_PCIE_BAR3_CAP_epf 0x0085 -#define cfgnbif_gpu_PCIE_BAR3_CAP_epf 0x0085 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR3_CAP_epf 0x0085 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR3_CAP_epf 0x0085 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR3_CAP_epf_alt_1 0x0085 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR3_CAP_epf_alt_1 0x0085 -#define pcinbif_gpu_PCIE_BAR3_CNTL_epf 0x0086 -#define cfgnbif_gpu_PCIE_BAR3_CNTL_epf 0x0086 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR3_CNTL_epf 0x0086 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR3_CNTL_epf 0x0086 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR3_CNTL_epf_alt_1 0x0086 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR3_CNTL_epf_alt_1 0x0086 -#define pcinbif_gpu_PCIE_BAR4_CAP_epf 0x0087 -#define cfgnbif_gpu_PCIE_BAR4_CAP_epf 0x0087 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR4_CAP_epf 0x0087 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR4_CAP_epf 0x0087 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR4_CAP_epf_alt_1 0x0087 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR4_CAP_epf_alt_1 0x0087 -#define pcinbif_gpu_PCIE_BAR4_CNTL_epf 0x0088 -#define cfgnbif_gpu_PCIE_BAR4_CNTL_epf 0x0088 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR4_CNTL_epf 0x0088 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR4_CNTL_epf 0x0088 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR4_CNTL_epf_alt_1 0x0088 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR4_CNTL_epf_alt_1 0x0088 -#define pcinbif_gpu_PCIE_BAR5_CAP_epf 0x0089 -#define cfgnbif_gpu_PCIE_BAR5_CAP_epf 0x0089 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR5_CAP_epf 0x0089 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR5_CAP_epf 0x0089 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR5_CAP_epf_alt_1 0x0089 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR5_CAP_epf_alt_1 0x0089 -#define pcinbif_gpu_PCIE_BAR5_CNTL_epf 0x008A -#define cfgnbif_gpu_PCIE_BAR5_CNTL_epf 0x008A -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR5_CNTL_epf 0x008A -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR5_CNTL_epf 0x008A -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR5_CNTL_epf_alt_1 0x008A -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR5_CNTL_epf_alt_1 0x008A -#define pcinbif_gpu_PCIE_BAR6_CAP_epf 0x008B -#define cfgnbif_gpu_PCIE_BAR6_CAP_epf 0x008B -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR6_CAP_epf 0x008B -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR6_CAP_epf 0x008B -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR6_CAP_epf_alt_1 0x008B -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR6_CAP_epf_alt_1 0x008B -#define pcinbif_gpu_PCIE_BAR6_CNTL_epf 0x008C -#define cfgnbif_gpu_PCIE_BAR6_CNTL_epf 0x008C -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_BAR6_CNTL_epf 0x008C -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_BAR6_CNTL_epf 0x008C -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_BAR6_CNTL_epf_alt_1 0x008C -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_BAR6_CNTL_epf_alt_1 0x008C -#define pcinbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf 0x0090 -#define cfgnbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf 0x0090 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf 0x0090 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf 0x0090 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf_alt_1 0x0090 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf_alt_1 0x0090 -#define pcinbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf 0x0091 -#define cfgnbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf 0x0091 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf 0x0091 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf 0x0091 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf_alt_1 0x0091 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf_alt_1 0x0091 -#define pcinbif_gpu_PCIE_PWR_BUDGET_DATA_epf 0x0092 -#define cfgnbif_gpu_PCIE_PWR_BUDGET_DATA_epf 0x0092 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_DATA_epf 0x0092 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_DATA_epf 0x0092 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_DATA_epf_alt_1 0x0092 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_DATA_epf_alt_1 0x0092 -#define pcinbif_gpu_PCIE_PWR_BUDGET_CAP_epf 0x0093 -#define cfgnbif_gpu_PCIE_PWR_BUDGET_CAP_epf 0x0093 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_CAP_epf 0x0093 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PWR_BUDGET_CAP_epf 0x0093 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_CAP_epf_alt_1 0x0093 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PWR_BUDGET_CAP_epf_alt_1 0x0093 -#define pcinbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf 0x0094 -#define cfgnbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf 0x0094 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf 0x0094 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf 0x0094 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf_alt_1 0x0094 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf_alt_1 0x0094 -#define pcinbif_gpu_PCIE_DPA_CAP_epf 0x0095 -#define cfgnbif_gpu_PCIE_DPA_CAP_epf 0x0095 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_CAP_epf 0x0095 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_CAP_epf 0x0095 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_CAP_epf_alt_1 0x0095 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_CAP_epf_alt_1 0x0095 -#define pcinbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf 0x0096 -#define cfgnbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf 0x0096 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf 0x0096 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf 0x0096 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf_alt_1 0x0096 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf_alt_1 0x0096 -#define pcinbif_gpu_PCIE_DPA_STATUS_epf 0x0097 -#define cfgnbif_gpu_PCIE_DPA_STATUS_epf 0x0097 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_STATUS_epf 0x0097 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_STATUS_epf 0x0097 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_STATUS_epf_alt_1 0x0097 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_STATUS_epf_alt_1 0x0097 -#define pcinbif_gpu_PCIE_DPA_CNTL_epf 0x0097 -#define cfgnbif_gpu_PCIE_DPA_CNTL_epf 0x0097 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_CNTL_epf 0x0097 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_CNTL_epf 0x0097 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_CNTL_epf_alt_1 0x0097 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_CNTL_epf_alt_1 0x0097 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf 0x0098 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf 0x0098 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf 0x0098 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf 0x0098 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf_alt_1 0x0098 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf_alt_1 0x0098 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf 0x0098 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf 0x0098 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf 0x0098 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf 0x0098 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf_alt_1 0x0098 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf_alt_1 0x0098 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf 0x0098 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf 0x0098 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf 0x0098 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf 0x0098 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf_alt_1 0x0098 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf_alt_1 0x0098 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf 0x0098 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf 0x0098 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf 0x0098 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf 0x0098 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf_alt_1 0x0098 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf_alt_1 0x0098 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf 0x0099 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf 0x0099 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf 0x0099 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf 0x0099 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf_alt_1 0x0099 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf_alt_1 0x0099 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf 0x0099 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf 0x0099 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf 0x0099 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf 0x0099 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf_alt_1 0x0099 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf_alt_1 0x0099 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf 0x0099 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf 0x0099 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf 0x0099 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf 0x0099 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf_alt_1 0x0099 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf_alt_1 0x0099 -#define pcinbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf 0x0099 -#define cfgnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf 0x0099 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf 0x0099 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf 0x0099 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf_alt_1 0x0099 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf_alt_1 0x0099 -#define pcinbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf 0x009C -#define cfgnbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf 0x009C -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf 0x009C -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf 0x009C -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf_alt_1 0x009C -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf_alt_1 0x009C -#define pcinbif_gpu_PCIE_LINK_CNTL3_epf 0x009D -#define cfgnbif_gpu_PCIE_LINK_CNTL3_epf 0x009D -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LINK_CNTL3_epf 0x009D -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LINK_CNTL3_epf 0x009D -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LINK_CNTL3_epf_alt_1 0x009D -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LINK_CNTL3_epf_alt_1 0x009D -#define pcinbif_gpu_PCIE_LANE_ERROR_STATUS_epf 0x009E -#define cfgnbif_gpu_PCIE_LANE_ERROR_STATUS_epf 0x009E -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_ERROR_STATUS_epf 0x009E -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_ERROR_STATUS_epf 0x009E -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_ERROR_STATUS_epf_alt_1 0x009E -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_ERROR_STATUS_epf_alt_1 0x009E -#define pcinbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf 0x009F -#define cfgnbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf 0x009F -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf 0x009F -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf 0x009F -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf_alt_1 0x009F -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf_alt_1 0x009F -#define pcinbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf 0x009F -#define cfgnbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf 0x009F -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf 0x009F -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf 0x009F -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf_alt_1 0x009F -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf_alt_1 0x009F -#define pcinbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf 0x00A0 -#define cfgnbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf 0x00A0 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf 0x00A0 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf 0x00A0 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf_alt_1 0x00A0 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf_alt_1 0x00A0 -#define pcinbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf 0x00A0 -#define cfgnbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf 0x00A0 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf 0x00A0 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf 0x00A0 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf_alt_1 0x00A0 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf_alt_1 0x00A0 -#define pcinbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf 0x00A1 -#define cfgnbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf 0x00A1 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf 0x00A1 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf 0x00A1 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf_alt_1 0x00A1 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf_alt_1 0x00A1 -#define pcinbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf 0x00A1 -#define cfgnbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf 0x00A1 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf 0x00A1 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf 0x00A1 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf_alt_1 0x00A1 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf_alt_1 0x00A1 -#define pcinbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf 0x00A2 -#define cfgnbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf 0x00A2 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf 0x00A2 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf 0x00A2 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf_alt_1 0x00A2 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf_alt_1 0x00A2 -#define pcinbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf 0x00A2 -#define cfgnbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf 0x00A2 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf 0x00A2 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf 0x00A2 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf_alt_1 0x00A2 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf_alt_1 0x00A2 -#define pcinbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf 0x00A3 -#define cfgnbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf 0x00A3 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf 0x00A3 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf 0x00A3 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf_alt_1 0x00A3 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf_alt_1 0x00A3 -#define pcinbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf 0x00A3 -#define cfgnbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf 0x00A3 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf 0x00A3 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf 0x00A3 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf_alt_1 0x00A3 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf_alt_1 0x00A3 -#define pcinbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf 0x00A4 -#define cfgnbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf 0x00A4 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf 0x00A4 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf 0x00A4 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf_alt_1 0x00A4 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf_alt_1 0x00A4 -#define pcinbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf 0x00A4 -#define cfgnbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf 0x00A4 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf 0x00A4 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf 0x00A4 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf_alt_1 0x00A4 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf_alt_1 0x00A4 -#define pcinbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf 0x00A5 -#define cfgnbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf 0x00A5 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf 0x00A5 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf 0x00A5 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf_alt_1 0x00A5 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf_alt_1 0x00A5 -#define pcinbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf 0x00A5 -#define cfgnbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf 0x00A5 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf 0x00A5 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf 0x00A5 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf_alt_1 0x00A5 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf_alt_1 0x00A5 -#define pcinbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf 0x00A6 -#define cfgnbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf 0x00A6 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf 0x00A6 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf 0x00A6 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf_alt_1 0x00A6 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf_alt_1 0x00A6 -#define pcinbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf 0x00A6 -#define cfgnbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf 0x00A6 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf 0x00A6 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf 0x00A6 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf_alt_1 0x00A6 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf_alt_1 0x00A6 -#define pcinbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf 0x00A8 -#define cfgnbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf 0x00A8 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf 0x00A8 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf 0x00A8 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf_alt_1 0x00A8 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf_alt_1 0x00A8 -#define pcinbif_gpu_PCIE_ACS_CAP_epf 0x00A9 -#define cfgnbif_gpu_PCIE_ACS_CAP_epf 0x00A9 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_CAP_epf 0x00A9 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_CAP_epf 0x00A9 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_CAP_epf_alt_1 0x00A9 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_CAP_epf_alt_1 0x00A9 -#define pcinbif_gpu_PCIE_ACS_CNTL_epf 0x00A9 -#define cfgnbif_gpu_PCIE_ACS_CNTL_epf 0x00A9 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_CNTL_epf 0x00A9 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ACS_CNTL_epf 0x00A9 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_CNTL_epf_alt_1 0x00A9 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ACS_CNTL_epf_alt_1 0x00A9 -#define pcinbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf 0x00AC -#define cfgnbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf 0x00AC -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf 0x00AC -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf 0x00AC -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf_alt_1 0x00AC -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf_alt_1 0x00AC -#define pcinbif_gpu_PCIE_ATS_CAP_epf 0x00AD -#define cfgnbif_gpu_PCIE_ATS_CAP_epf 0x00AD -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_CAP_epf 0x00AD -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_CAP_epf 0x00AD -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_CAP_epf_alt_1 0x00AD -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_CAP_epf_alt_1 0x00AD -#define pcinbif_gpu_PCIE_ATS_CNTL_epf 0x00AD -#define cfgnbif_gpu_PCIE_ATS_CNTL_epf 0x00AD -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_CNTL_epf 0x00AD -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ATS_CNTL_epf 0x00AD -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_CNTL_epf_alt_1 0x00AD -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ATS_CNTL_epf_alt_1 0x00AD -#define pcinbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf 0x00B0 -#define cfgnbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf 0x00B0 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf 0x00B0 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf 0x00B0 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf_alt_1 0x00B0 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf_alt_1 0x00B0 -#define pcinbif_gpu_PCIE_PAGE_REQ_CNTL_epf 0x00B1 -#define cfgnbif_gpu_PCIE_PAGE_REQ_CNTL_epf 0x00B1 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_CNTL_epf 0x00B1 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_CNTL_epf 0x00B1 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_CNTL_epf_alt_1 0x00B1 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_CNTL_epf_alt_1 0x00B1 -#define pcinbif_gpu_PCIE_PAGE_REQ_STATUS_epf 0x00B1 -#define cfgnbif_gpu_PCIE_PAGE_REQ_STATUS_epf 0x00B1 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_STATUS_epf 0x00B1 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PAGE_REQ_STATUS_epf 0x00B1 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_STATUS_epf_alt_1 0x00B1 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PAGE_REQ_STATUS_epf_alt_1 0x00B1 -#define pcinbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf 0x00B2 -#define cfgnbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf 0x00B2 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf 0x00B2 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf 0x00B2 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf_alt_1 0x00B2 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf_alt_1 0x00B2 -#define pcinbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf 0x00B3 -#define cfgnbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf 0x00B3 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf 0x00B3 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf 0x00B3 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf_alt_1 0x00B3 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf_alt_1 0x00B3 -#define pcinbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf 0x00B4 -#define cfgnbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf 0x00B4 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf 0x00B4 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf 0x00B4 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf_alt_1 0x00B4 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf_alt_1 0x00B4 -#define pcinbif_gpu_PCIE_PASID_CAP_epf 0x00B5 -#define cfgnbif_gpu_PCIE_PASID_CAP_epf 0x00B5 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_CAP_epf 0x00B5 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_CAP_epf 0x00B5 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_CAP_epf_alt_1 0x00B5 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_CAP_epf_alt_1 0x00B5 -#define pcinbif_gpu_PCIE_PASID_CNTL_epf 0x00B5 -#define cfgnbif_gpu_PCIE_PASID_CNTL_epf 0x00B5 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_CNTL_epf 0x00B5 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_PASID_CNTL_epf 0x00B5 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_CNTL_epf_alt_1 0x00B5 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_PASID_CNTL_epf_alt_1 0x00B5 -#define pcinbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf 0x00B8 -#define cfgnbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf 0x00B8 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf 0x00B8 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf 0x00B8 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf_alt_1 0x00B8 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf_alt_1 0x00B8 -#define pcinbif_gpu_PCIE_TPH_REQR_CAP_epf 0x00B9 -#define cfgnbif_gpu_PCIE_TPH_REQR_CAP_epf 0x00B9 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_CAP_epf 0x00B9 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_CAP_epf 0x00B9 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_CAP_epf_alt_1 0x00B9 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_CAP_epf_alt_1 0x00B9 -#define pcinbif_gpu_PCIE_TPH_REQR_CNTL_epf 0x00BA -#define cfgnbif_gpu_PCIE_TPH_REQR_CNTL_epf 0x00BA -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_CNTL_epf 0x00BA -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_TPH_REQR_CNTL_epf 0x00BA -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_CNTL_epf_alt_1 0x00BA -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_TPH_REQR_CNTL_epf_alt_1 0x00BA -#define pcinbif_gpu_PCIE_MC_ENH_CAP_LIST_epf 0x00BC -#define cfgnbif_gpu_PCIE_MC_ENH_CAP_LIST_epf 0x00BC -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf 0x00BC -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf 0x00BC -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf_alt_1 0x00BC -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf_alt_1 0x00BC -#define pcinbif_gpu_PCIE_MC_CAP_epf 0x00BD -#define cfgnbif_gpu_PCIE_MC_CAP_epf 0x00BD -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_CAP_epf 0x00BD -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_CAP_epf 0x00BD -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_CAP_epf_alt_1 0x00BD -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_CAP_epf_alt_1 0x00BD -#define pcinbif_gpu_PCIE_MC_CNTL_epf 0x00BD -#define cfgnbif_gpu_PCIE_MC_CNTL_epf 0x00BD -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_CNTL_epf 0x00BD -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_CNTL_epf 0x00BD -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_CNTL_epf_alt_1 0x00BD -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_CNTL_epf_alt_1 0x00BD -#define pcinbif_gpu_PCIE_MC_ADDR0_epf 0x00BE -#define cfgnbif_gpu_PCIE_MC_ADDR0_epf 0x00BE -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ADDR0_epf 0x00BE -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ADDR0_epf 0x00BE -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ADDR0_epf_alt_1 0x00BE -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ADDR0_epf_alt_1 0x00BE -#define pcinbif_gpu_PCIE_MC_ADDR1_epf 0x00BF -#define cfgnbif_gpu_PCIE_MC_ADDR1_epf 0x00BF -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ADDR1_epf 0x00BF -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_ADDR1_epf 0x00BF -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ADDR1_epf_alt_1 0x00BF -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_ADDR1_epf_alt_1 0x00BF -#define pcinbif_gpu_PCIE_MC_RCV0_epf 0x00C0 -#define cfgnbif_gpu_PCIE_MC_RCV0_epf 0x00C0 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_RCV0_epf 0x00C0 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_RCV0_epf 0x00C0 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_RCV0_epf_alt_1 0x00C0 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_RCV0_epf_alt_1 0x00C0 -#define pcinbif_gpu_PCIE_MC_RCV1_epf 0x00C1 -#define cfgnbif_gpu_PCIE_MC_RCV1_epf 0x00C1 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_RCV1_epf 0x00C1 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_RCV1_epf 0x00C1 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_RCV1_epf_alt_1 0x00C1 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_RCV1_epf_alt_1 0x00C1 -#define pcinbif_gpu_PCIE_MC_BLOCK_ALL0_epf 0x00C2 -#define cfgnbif_gpu_PCIE_MC_BLOCK_ALL0_epf 0x00C2 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_ALL0_epf 0x00C2 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_ALL0_epf 0x00C2 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_ALL0_epf_alt_1 0x00C2 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_ALL0_epf_alt_1 0x00C2 -#define pcinbif_gpu_PCIE_MC_BLOCK_ALL1_epf 0x00C3 -#define cfgnbif_gpu_PCIE_MC_BLOCK_ALL1_epf 0x00C3 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_ALL1_epf 0x00C3 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_ALL1_epf 0x00C3 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_ALL1_epf_alt_1 0x00C3 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_ALL1_epf_alt_1 0x00C3 -#define pcinbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf 0x00C4 -#define cfgnbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf 0x00C4 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf 0x00C4 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf 0x00C4 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf_alt_1 0x00C4 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf_alt_1 0x00C4 -#define pcinbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf 0x00C5 -#define cfgnbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf 0x00C5 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf 0x00C5 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf 0x00C5 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf_alt_1 0x00C5 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf_alt_1 0x00C5 -#define pcinbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf 0x00C8 -#define cfgnbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf 0x00C8 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf 0x00C8 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf 0x00C8 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf_alt_1 0x00C8 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf_alt_1 0x00C8 -#define pcinbif_gpu_PCIE_LTR_CAP_epf 0x00C9 -#define cfgnbif_gpu_PCIE_LTR_CAP_epf 0x00C9 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_LTR_CAP_epf 0x00C9 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_LTR_CAP_epf 0x00C9 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_LTR_CAP_epf_alt_1 0x00C9 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_LTR_CAP_epf_alt_1 0x00C9 -#define pcinbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf 0x00CA -#define cfgnbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf 0x00CA -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf 0x00CA -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf 0x00CA -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf_alt_1 0x00CA -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf_alt_1 0x00CA -#define pcinbif_gpu_PCIE_ARI_CAP_epf 0x00CB -#define cfgnbif_gpu_PCIE_ARI_CAP_epf 0x00CB -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_CAP_epf 0x00CB -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_CAP_epf 0x00CB -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_CAP_epf_alt_1 0x00CB -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_CAP_epf_alt_1 0x00CB -#define pcinbif_gpu_PCIE_ARI_CNTL_epf 0x00CB -#define cfgnbif_gpu_PCIE_ARI_CNTL_epf 0x00CB -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_CNTL_epf 0x00CB -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_ARI_CNTL_epf 0x00CB -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_CNTL_epf_alt_1 0x00CB -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_ARI_CNTL_epf_alt_1 0x00CB -#define pcinbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf 0x00CC -#define cfgnbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf 0x00CC -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf 0x00CC -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf 0x00CC -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf_alt_1 0x00CC -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf_alt_1 0x00CC -#define pcinbif_gpu_PCIE_SRIOV_CAP_epf 0x00CD -#define cfgnbif_gpu_PCIE_SRIOV_CAP_epf 0x00CD -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_CAP_epf 0x00CD -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_CAP_epf 0x00CD -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_CAP_epf_alt_1 0x00CD -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_CAP_epf_alt_1 0x00CD -#define pcinbif_gpu_PCIE_SRIOV_CONTROL_epf 0x00CE -#define cfgnbif_gpu_PCIE_SRIOV_CONTROL_epf 0x00CE -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_CONTROL_epf 0x00CE -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_CONTROL_epf 0x00CE -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_CONTROL_epf_alt_1 0x00CE -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_CONTROL_epf_alt_1 0x00CE -#define pcinbif_gpu_PCIE_SRIOV_STATUS_epf 0x00CE -#define cfgnbif_gpu_PCIE_SRIOV_STATUS_epf 0x00CE -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_STATUS_epf 0x00CE -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_STATUS_epf 0x00CE -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_STATUS_epf_alt_1 0x00CE -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_STATUS_epf_alt_1 0x00CE -#define pcinbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf 0x00CF -#define cfgnbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf 0x00CF -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf 0x00CF -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf 0x00CF -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf_alt_1 0x00CF -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf_alt_1 0x00CF -#define pcinbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf 0x00CF -#define cfgnbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf 0x00CF -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf 0x00CF -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf 0x00CF -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf_alt_1 0x00CF -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf_alt_1 0x00CF -#define pcinbif_gpu_PCIE_SRIOV_NUM_VFS_epf 0x00D0 -#define cfgnbif_gpu_PCIE_SRIOV_NUM_VFS_epf 0x00D0 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_NUM_VFS_epf 0x00D0 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_NUM_VFS_epf 0x00D0 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_NUM_VFS_epf_alt_1 0x00D0 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_NUM_VFS_epf_alt_1 0x00D0 -#define pcinbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf 0x00D0 -#define cfgnbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf 0x00D0 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf 0x00D0 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf 0x00D0 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf_alt_1 0x00D0 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf_alt_1 0x00D0 -#define pcinbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf 0x00D1 -#define cfgnbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf 0x00D1 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf 0x00D1 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf 0x00D1 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf_alt_1 0x00D1 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf_alt_1 0x00D1 -#define pcinbif_gpu_PCIE_SRIOV_VF_STRIDE_epf 0x00D1 -#define cfgnbif_gpu_PCIE_SRIOV_VF_STRIDE_epf 0x00D1 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf 0x00D1 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf 0x00D1 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf_alt_1 0x00D1 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf_alt_1 0x00D1 -#define pcinbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf 0x00D2 -#define cfgnbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf 0x00D2 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf 0x00D2 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf 0x00D2 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf_alt_1 0x00D2 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf_alt_1 0x00D2 -#define pcinbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf 0x00D3 -#define cfgnbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf 0x00D3 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf 0x00D3 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf 0x00D3 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf_alt_1 0x00D3 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf_alt_1 0x00D3 -#define pcinbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf 0x00D4 -#define cfgnbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf 0x00D4 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf 0x00D4 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf 0x00D4 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf_alt_1 0x00D4 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf_alt_1 0x00D4 -#define pcinbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf 0x00D5 -#define cfgnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf 0x00D5 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf 0x00D5 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf 0x00D5 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf_alt_1 0x00D5 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf_alt_1 0x00D5 -#define pcinbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf 0x00D6 -#define cfgnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf 0x00D6 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf 0x00D6 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf 0x00D6 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf_alt_1 0x00D6 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf_alt_1 0x00D6 -#define pcinbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf 0x00D7 -#define cfgnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf 0x00D7 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf 0x00D7 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf 0x00D7 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf_alt_1 0x00D7 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf_alt_1 0x00D7 -#define pcinbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf 0x00D8 -#define cfgnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf 0x00D8 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf 0x00D8 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf 0x00D8 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf_alt_1 0x00D8 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf_alt_1 0x00D8 -#define pcinbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf 0x00D9 -#define cfgnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf 0x00D9 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf 0x00D9 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf 0x00D9 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf_alt_1 0x00D9 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf_alt_1 0x00D9 -#define pcinbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf 0x00DA -#define cfgnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf 0x00DA -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf 0x00DA -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf 0x00DA -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf_alt_1 0x00DA -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf_alt_1 0x00DA -#define pcinbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf 0x00DB -#define cfgnbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf 0x00DB -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf 0x00DB -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf 0x00DB -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf_alt_1 0x00DB -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf_alt_1 0x00DB -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf 0x0100 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf 0x0100 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf 0x0100 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf 0x0100 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf_alt_1 0x0100 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf_alt_1 0x0100 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf 0x0101 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf 0x0101 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf 0x0101 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf 0x0101 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf_alt_1 0x0101 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf_alt_1 0x0101 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf 0x0102 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf 0x0102 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf 0x0102 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf 0x0102 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf_alt_1 0x0102 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf_alt_1 0x0102 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf 0x0103 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf 0x0103 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf 0x0103 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf 0x0103 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf_alt_1 0x0103 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf_alt_1 0x0103 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf 0x0104 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf 0x0104 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf 0x0104 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf 0x0104 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf_alt_1 0x0104 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf_alt_1 0x0104 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf 0x0105 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf 0x0105 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf 0x0105 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf 0x0105 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf_alt_1 0x0105 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf_alt_1 0x0105 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf 0x0106 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf 0x0106 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf 0x0106 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf 0x0106 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf_alt_1 0x0106 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf_alt_1 0x0106 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf 0x0107 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf 0x0107 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf 0x0107 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf 0x0107 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf_alt_1 0x0107 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf_alt_1 0x0107 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf 0x0108 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf 0x0108 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf 0x0108 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf 0x0108 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf_alt_1 0x0108 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf_alt_1 0x0108 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf 0x0109 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf 0x0109 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf 0x0109 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf 0x0109 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf_alt_1 0x0109 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf_alt_1 0x0109 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf 0x010A -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf 0x010A -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf 0x010A -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf 0x010A -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf_alt_1 0x010A -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf_alt_1 0x010A -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf 0x010B -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf 0x010B -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf 0x010B -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf 0x010B -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf_alt_1 0x010B -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf_alt_1 0x010B -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf 0x010C -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf 0x010C -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf 0x010C -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf 0x010C -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf_alt_1 0x010C -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf_alt_1 0x010C -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf 0x010D -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf 0x010D -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf 0x010D -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf 0x010D -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf_alt_1 0x010D -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf_alt_1 0x010D -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf 0x010E -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf 0x010E -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf 0x010E -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf 0x010E -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf_alt_1 0x010E -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf_alt_1 0x010E -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf 0x010F -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf 0x010F -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf 0x010F -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf 0x010F -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf_alt_1 0x010F -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf_alt_1 0x010F -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf 0x0110 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf 0x0110 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf 0x0110 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf 0x0110 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf_alt_1 0x0110 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf_alt_1 0x0110 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf 0x0111 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf 0x0111 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf 0x0111 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf 0x0111 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf_alt_1 0x0111 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf_alt_1 0x0111 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf 0x0112 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf 0x0112 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf 0x0112 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf 0x0112 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf_alt_1 0x0112 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf_alt_1 0x0112 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf 0x0113 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf 0x0113 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf 0x0113 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf 0x0113 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf_alt_1 0x0113 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf_alt_1 0x0113 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf 0x0114 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf 0x0114 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf 0x0114 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf 0x0114 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf_alt_1 0x0114 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf_alt_1 0x0114 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf 0x0115 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf 0x0115 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf 0x0115 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf 0x0115 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf_alt_1 0x0115 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf_alt_1 0x0115 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf 0x0116 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf 0x0116 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf 0x0116 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf 0x0116 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf_alt_1 0x0116 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf_alt_1 0x0116 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf 0x0117 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf 0x0117 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf 0x0117 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf 0x0117 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf_alt_1 0x0117 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf_alt_1 0x0117 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf 0x0118 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf 0x0118 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf 0x0118 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf 0x0118 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf_alt_1 0x0118 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf_alt_1 0x0118 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf 0x0119 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf 0x0119 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf 0x0119 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf 0x0119 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf_alt_1 0x0119 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf_alt_1 0x0119 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf 0x011A -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf 0x011A -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf 0x011A -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf 0x011A -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf_alt_1 0x011A -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf_alt_1 0x011A -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf 0x011B -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf 0x011B -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf 0x011B -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf 0x011B -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf_alt_1 0x011B -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf_alt_1 0x011B -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf 0x011C -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf 0x011C -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf 0x011C -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf 0x011C -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf_alt_1 0x011C -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf_alt_1 0x011C -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf 0x011D -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf 0x011D -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf 0x011D -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf 0x011D -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf_alt_1 0x011D -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf_alt_1 0x011D -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf 0x011E -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf 0x011E -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf 0x011E -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf 0x011E -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf_alt_1 0x011E -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf_alt_1 0x011E -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf 0x011F -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf 0x011F -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf 0x011F -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf 0x011F -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf_alt_1 0x011F -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf_alt_1 0x011F -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf 0x0120 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf 0x0120 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf 0x0120 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf 0x0120 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf_alt_1 0x0120 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf_alt_1 0x0120 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf 0x0121 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf 0x0121 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf 0x0121 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf 0x0121 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf_alt_1 0x0121 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf_alt_1 0x0121 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf 0x0122 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf 0x0122 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf 0x0122 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf 0x0122 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf_alt_1 0x0122 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf_alt_1 0x0122 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf 0x0123 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf 0x0123 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf 0x0123 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf 0x0123 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf_alt_1 0x0123 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf_alt_1 0x0123 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf 0x0124 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf 0x0124 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf 0x0124 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf 0x0124 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf_alt_1 0x0124 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf_alt_1 0x0124 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf 0x0125 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf 0x0125 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf 0x0125 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf 0x0125 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf_alt_1 0x0125 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf_alt_1 0x0125 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf 0x0126 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf 0x0126 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf 0x0126 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf 0x0126 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf_alt_1 0x0126 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf_alt_1 0x0126 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf 0x0127 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf 0x0127 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf 0x0127 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf 0x0127 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf_alt_1 0x0127 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf_alt_1 0x0127 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf 0x0128 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf 0x0128 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf 0x0128 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf 0x0128 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf_alt_1 0x0128 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf_alt_1 0x0128 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf 0x0129 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf 0x0129 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf 0x0129 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf 0x0129 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf_alt_1 0x0129 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf_alt_1 0x0129 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf 0x012A -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf 0x012A -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf 0x012A -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf 0x012A -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf_alt_1 0x012A -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf_alt_1 0x012A -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf 0x012B -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf 0x012B -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf 0x012B -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf 0x012B -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf_alt_1 0x012B -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf_alt_1 0x012B -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf 0x012C -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf 0x012C -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf 0x012C -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf 0x012C -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf_alt_1 0x012C -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf_alt_1 0x012C -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf 0x012D -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf 0x012D -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf 0x012D -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf 0x012D -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf_alt_1 0x012D -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf_alt_1 0x012D -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf 0x012E -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf 0x012E -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf 0x012E -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf 0x012E -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf_alt_1 0x012E -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf_alt_1 0x012E -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf 0x012F -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf 0x012F -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf 0x012F -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf 0x012F -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf_alt_1 0x012F -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf_alt_1 0x012F -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf 0x0130 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf 0x0130 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf 0x0130 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf 0x0130 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf_alt_1 0x0130 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf_alt_1 0x0130 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf 0x0131 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf 0x0131 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf 0x0131 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf 0x0131 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf_alt_1 0x0131 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf_alt_1 0x0131 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf 0x0132 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf 0x0132 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf 0x0132 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf 0x0132 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf_alt_1 0x0132 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf_alt_1 0x0132 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf 0x0133 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf 0x0133 -#define pciBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf 0x0133 -#define cfgBIF_CFG_EPF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf 0x0133 -#define pciBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf_alt_1 0x0133 -#define cfgBIF_CFG_EPF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf_alt_1 0x0133 - - -// Registers from BIF_CFG_EPVF block - -#define mmnbif_gpu_VENDOR_ID_epvf 0x4058000 -#define mmBIF_CFG_EPVF0_nbif_gpu_VENDOR_ID_epvf 0x4058000 -#define mmBIF_CFG_EPVF1_nbif_gpu_VENDOR_ID_epvf 0x4058400 -#define mmBIF_CFG_EPVF2_nbif_gpu_VENDOR_ID_epvf 0x4058800 -#define mmBIF_CFG_EPVF3_nbif_gpu_VENDOR_ID_epvf 0x4058C00 -#define mmBIF_CFG_EPVF4_nbif_gpu_VENDOR_ID_epvf 0x4059000 -#define mmBIF_CFG_EPVF5_nbif_gpu_VENDOR_ID_epvf 0x4059400 -#define mmBIF_CFG_EPVF6_nbif_gpu_VENDOR_ID_epvf 0x4059800 -#define mmBIF_CFG_EPVF7_nbif_gpu_VENDOR_ID_epvf 0x4059C00 -#define mmBIF_CFG_EPVF8_nbif_gpu_VENDOR_ID_epvf 0x405A000 -#define mmBIF_CFG_EPVF9_nbif_gpu_VENDOR_ID_epvf 0x405A400 -#define mmBIF_CFG_EPVF10_nbif_gpu_VENDOR_ID_epvf 0x405A800 -#define mmBIF_CFG_EPVF11_nbif_gpu_VENDOR_ID_epvf 0x405AC00 -#define mmBIF_CFG_EPVF12_nbif_gpu_VENDOR_ID_epvf 0x405B000 -#define mmBIF_CFG_EPVF13_nbif_gpu_VENDOR_ID_epvf 0x405B400 -#define mmBIF_CFG_EPVF14_nbif_gpu_VENDOR_ID_epvf 0x405B800 -#define mmBIF_CFG_EPVF15_nbif_gpu_VENDOR_ID_epvf 0x405BC00 -#define mmnbif_gpu_DEVICE_ID_epvf 0x4058000 -#define mmBIF_CFG_EPVF0_nbif_gpu_DEVICE_ID_epvf 0x4058000 -#define mmBIF_CFG_EPVF1_nbif_gpu_DEVICE_ID_epvf 0x4058400 -#define mmBIF_CFG_EPVF2_nbif_gpu_DEVICE_ID_epvf 0x4058800 -#define mmBIF_CFG_EPVF3_nbif_gpu_DEVICE_ID_epvf 0x4058C00 -#define mmBIF_CFG_EPVF4_nbif_gpu_DEVICE_ID_epvf 0x4059000 -#define mmBIF_CFG_EPVF5_nbif_gpu_DEVICE_ID_epvf 0x4059400 -#define mmBIF_CFG_EPVF6_nbif_gpu_DEVICE_ID_epvf 0x4059800 -#define mmBIF_CFG_EPVF7_nbif_gpu_DEVICE_ID_epvf 0x4059C00 -#define mmBIF_CFG_EPVF8_nbif_gpu_DEVICE_ID_epvf 0x405A000 -#define mmBIF_CFG_EPVF9_nbif_gpu_DEVICE_ID_epvf 0x405A400 -#define mmBIF_CFG_EPVF10_nbif_gpu_DEVICE_ID_epvf 0x405A800 -#define mmBIF_CFG_EPVF11_nbif_gpu_DEVICE_ID_epvf 0x405AC00 -#define mmBIF_CFG_EPVF12_nbif_gpu_DEVICE_ID_epvf 0x405B000 -#define mmBIF_CFG_EPVF13_nbif_gpu_DEVICE_ID_epvf 0x405B400 -#define mmBIF_CFG_EPVF14_nbif_gpu_DEVICE_ID_epvf 0x405B800 -#define mmBIF_CFG_EPVF15_nbif_gpu_DEVICE_ID_epvf 0x405BC00 -#define mmnbif_gpu_COMMAND_epvf 0x4058001 -#define mmBIF_CFG_EPVF0_nbif_gpu_COMMAND_epvf 0x4058001 -#define mmBIF_CFG_EPVF1_nbif_gpu_COMMAND_epvf 0x4058401 -#define mmBIF_CFG_EPVF2_nbif_gpu_COMMAND_epvf 0x4058801 -#define mmBIF_CFG_EPVF3_nbif_gpu_COMMAND_epvf 0x4058C01 -#define mmBIF_CFG_EPVF4_nbif_gpu_COMMAND_epvf 0x4059001 -#define mmBIF_CFG_EPVF5_nbif_gpu_COMMAND_epvf 0x4059401 -#define mmBIF_CFG_EPVF6_nbif_gpu_COMMAND_epvf 0x4059801 -#define mmBIF_CFG_EPVF7_nbif_gpu_COMMAND_epvf 0x4059C01 -#define mmBIF_CFG_EPVF8_nbif_gpu_COMMAND_epvf 0x405A001 -#define mmBIF_CFG_EPVF9_nbif_gpu_COMMAND_epvf 0x405A401 -#define mmBIF_CFG_EPVF10_nbif_gpu_COMMAND_epvf 0x405A801 -#define mmBIF_CFG_EPVF11_nbif_gpu_COMMAND_epvf 0x405AC01 -#define mmBIF_CFG_EPVF12_nbif_gpu_COMMAND_epvf 0x405B001 -#define mmBIF_CFG_EPVF13_nbif_gpu_COMMAND_epvf 0x405B401 -#define mmBIF_CFG_EPVF14_nbif_gpu_COMMAND_epvf 0x405B801 -#define mmBIF_CFG_EPVF15_nbif_gpu_COMMAND_epvf 0x405BC01 -#define mmnbif_gpu_STATUS_epvf 0x4058001 -#define mmBIF_CFG_EPVF0_nbif_gpu_STATUS_epvf 0x4058001 -#define mmBIF_CFG_EPVF1_nbif_gpu_STATUS_epvf 0x4058401 -#define mmBIF_CFG_EPVF2_nbif_gpu_STATUS_epvf 0x4058801 -#define mmBIF_CFG_EPVF3_nbif_gpu_STATUS_epvf 0x4058C01 -#define mmBIF_CFG_EPVF4_nbif_gpu_STATUS_epvf 0x4059001 -#define mmBIF_CFG_EPVF5_nbif_gpu_STATUS_epvf 0x4059401 -#define mmBIF_CFG_EPVF6_nbif_gpu_STATUS_epvf 0x4059801 -#define mmBIF_CFG_EPVF7_nbif_gpu_STATUS_epvf 0x4059C01 -#define mmBIF_CFG_EPVF8_nbif_gpu_STATUS_epvf 0x405A001 -#define mmBIF_CFG_EPVF9_nbif_gpu_STATUS_epvf 0x405A401 -#define mmBIF_CFG_EPVF10_nbif_gpu_STATUS_epvf 0x405A801 -#define mmBIF_CFG_EPVF11_nbif_gpu_STATUS_epvf 0x405AC01 -#define mmBIF_CFG_EPVF12_nbif_gpu_STATUS_epvf 0x405B001 -#define mmBIF_CFG_EPVF13_nbif_gpu_STATUS_epvf 0x405B401 -#define mmBIF_CFG_EPVF14_nbif_gpu_STATUS_epvf 0x405B801 -#define mmBIF_CFG_EPVF15_nbif_gpu_STATUS_epvf 0x405BC01 -#define mmnbif_gpu_REVISION_ID_epvf 0x4058002 -#define mmBIF_CFG_EPVF0_nbif_gpu_REVISION_ID_epvf 0x4058002 -#define mmBIF_CFG_EPVF1_nbif_gpu_REVISION_ID_epvf 0x4058402 -#define mmBIF_CFG_EPVF2_nbif_gpu_REVISION_ID_epvf 0x4058802 -#define mmBIF_CFG_EPVF3_nbif_gpu_REVISION_ID_epvf 0x4058C02 -#define mmBIF_CFG_EPVF4_nbif_gpu_REVISION_ID_epvf 0x4059002 -#define mmBIF_CFG_EPVF5_nbif_gpu_REVISION_ID_epvf 0x4059402 -#define mmBIF_CFG_EPVF6_nbif_gpu_REVISION_ID_epvf 0x4059802 -#define mmBIF_CFG_EPVF7_nbif_gpu_REVISION_ID_epvf 0x4059C02 -#define mmBIF_CFG_EPVF8_nbif_gpu_REVISION_ID_epvf 0x405A002 -#define mmBIF_CFG_EPVF9_nbif_gpu_REVISION_ID_epvf 0x405A402 -#define mmBIF_CFG_EPVF10_nbif_gpu_REVISION_ID_epvf 0x405A802 -#define mmBIF_CFG_EPVF11_nbif_gpu_REVISION_ID_epvf 0x405AC02 -#define mmBIF_CFG_EPVF12_nbif_gpu_REVISION_ID_epvf 0x405B002 -#define mmBIF_CFG_EPVF13_nbif_gpu_REVISION_ID_epvf 0x405B402 -#define mmBIF_CFG_EPVF14_nbif_gpu_REVISION_ID_epvf 0x405B802 -#define mmBIF_CFG_EPVF15_nbif_gpu_REVISION_ID_epvf 0x405BC02 -#define mmnbif_gpu_PROG_INTERFACE_epvf 0x4058002 -#define mmBIF_CFG_EPVF0_nbif_gpu_PROG_INTERFACE_epvf 0x4058002 -#define mmBIF_CFG_EPVF1_nbif_gpu_PROG_INTERFACE_epvf 0x4058402 -#define mmBIF_CFG_EPVF2_nbif_gpu_PROG_INTERFACE_epvf 0x4058802 -#define mmBIF_CFG_EPVF3_nbif_gpu_PROG_INTERFACE_epvf 0x4058C02 -#define mmBIF_CFG_EPVF4_nbif_gpu_PROG_INTERFACE_epvf 0x4059002 -#define mmBIF_CFG_EPVF5_nbif_gpu_PROG_INTERFACE_epvf 0x4059402 -#define mmBIF_CFG_EPVF6_nbif_gpu_PROG_INTERFACE_epvf 0x4059802 -#define mmBIF_CFG_EPVF7_nbif_gpu_PROG_INTERFACE_epvf 0x4059C02 -#define mmBIF_CFG_EPVF8_nbif_gpu_PROG_INTERFACE_epvf 0x405A002 -#define mmBIF_CFG_EPVF9_nbif_gpu_PROG_INTERFACE_epvf 0x405A402 -#define mmBIF_CFG_EPVF10_nbif_gpu_PROG_INTERFACE_epvf 0x405A802 -#define mmBIF_CFG_EPVF11_nbif_gpu_PROG_INTERFACE_epvf 0x405AC02 -#define mmBIF_CFG_EPVF12_nbif_gpu_PROG_INTERFACE_epvf 0x405B002 -#define mmBIF_CFG_EPVF13_nbif_gpu_PROG_INTERFACE_epvf 0x405B402 -#define mmBIF_CFG_EPVF14_nbif_gpu_PROG_INTERFACE_epvf 0x405B802 -#define mmBIF_CFG_EPVF15_nbif_gpu_PROG_INTERFACE_epvf 0x405BC02 -#define mmnbif_gpu_SUB_CLASS_epvf 0x4058002 -#define mmBIF_CFG_EPVF0_nbif_gpu_SUB_CLASS_epvf 0x4058002 -#define mmBIF_CFG_EPVF1_nbif_gpu_SUB_CLASS_epvf 0x4058402 -#define mmBIF_CFG_EPVF2_nbif_gpu_SUB_CLASS_epvf 0x4058802 -#define mmBIF_CFG_EPVF3_nbif_gpu_SUB_CLASS_epvf 0x4058C02 -#define mmBIF_CFG_EPVF4_nbif_gpu_SUB_CLASS_epvf 0x4059002 -#define mmBIF_CFG_EPVF5_nbif_gpu_SUB_CLASS_epvf 0x4059402 -#define mmBIF_CFG_EPVF6_nbif_gpu_SUB_CLASS_epvf 0x4059802 -#define mmBIF_CFG_EPVF7_nbif_gpu_SUB_CLASS_epvf 0x4059C02 -#define mmBIF_CFG_EPVF8_nbif_gpu_SUB_CLASS_epvf 0x405A002 -#define mmBIF_CFG_EPVF9_nbif_gpu_SUB_CLASS_epvf 0x405A402 -#define mmBIF_CFG_EPVF10_nbif_gpu_SUB_CLASS_epvf 0x405A802 -#define mmBIF_CFG_EPVF11_nbif_gpu_SUB_CLASS_epvf 0x405AC02 -#define mmBIF_CFG_EPVF12_nbif_gpu_SUB_CLASS_epvf 0x405B002 -#define mmBIF_CFG_EPVF13_nbif_gpu_SUB_CLASS_epvf 0x405B402 -#define mmBIF_CFG_EPVF14_nbif_gpu_SUB_CLASS_epvf 0x405B802 -#define mmBIF_CFG_EPVF15_nbif_gpu_SUB_CLASS_epvf 0x405BC02 -#define mmnbif_gpu_BASE_CLASS_epvf 0x4058002 -#define mmBIF_CFG_EPVF0_nbif_gpu_BASE_CLASS_epvf 0x4058002 -#define mmBIF_CFG_EPVF1_nbif_gpu_BASE_CLASS_epvf 0x4058402 -#define mmBIF_CFG_EPVF2_nbif_gpu_BASE_CLASS_epvf 0x4058802 -#define mmBIF_CFG_EPVF3_nbif_gpu_BASE_CLASS_epvf 0x4058C02 -#define mmBIF_CFG_EPVF4_nbif_gpu_BASE_CLASS_epvf 0x4059002 -#define mmBIF_CFG_EPVF5_nbif_gpu_BASE_CLASS_epvf 0x4059402 -#define mmBIF_CFG_EPVF6_nbif_gpu_BASE_CLASS_epvf 0x4059802 -#define mmBIF_CFG_EPVF7_nbif_gpu_BASE_CLASS_epvf 0x4059C02 -#define mmBIF_CFG_EPVF8_nbif_gpu_BASE_CLASS_epvf 0x405A002 -#define mmBIF_CFG_EPVF9_nbif_gpu_BASE_CLASS_epvf 0x405A402 -#define mmBIF_CFG_EPVF10_nbif_gpu_BASE_CLASS_epvf 0x405A802 -#define mmBIF_CFG_EPVF11_nbif_gpu_BASE_CLASS_epvf 0x405AC02 -#define mmBIF_CFG_EPVF12_nbif_gpu_BASE_CLASS_epvf 0x405B002 -#define mmBIF_CFG_EPVF13_nbif_gpu_BASE_CLASS_epvf 0x405B402 -#define mmBIF_CFG_EPVF14_nbif_gpu_BASE_CLASS_epvf 0x405B802 -#define mmBIF_CFG_EPVF15_nbif_gpu_BASE_CLASS_epvf 0x405BC02 -#define mmnbif_gpu_CACHE_LINE_epvf 0x4058003 -#define mmBIF_CFG_EPVF0_nbif_gpu_CACHE_LINE_epvf 0x4058003 -#define mmBIF_CFG_EPVF1_nbif_gpu_CACHE_LINE_epvf 0x4058403 -#define mmBIF_CFG_EPVF2_nbif_gpu_CACHE_LINE_epvf 0x4058803 -#define mmBIF_CFG_EPVF3_nbif_gpu_CACHE_LINE_epvf 0x4058C03 -#define mmBIF_CFG_EPVF4_nbif_gpu_CACHE_LINE_epvf 0x4059003 -#define mmBIF_CFG_EPVF5_nbif_gpu_CACHE_LINE_epvf 0x4059403 -#define mmBIF_CFG_EPVF6_nbif_gpu_CACHE_LINE_epvf 0x4059803 -#define mmBIF_CFG_EPVF7_nbif_gpu_CACHE_LINE_epvf 0x4059C03 -#define mmBIF_CFG_EPVF8_nbif_gpu_CACHE_LINE_epvf 0x405A003 -#define mmBIF_CFG_EPVF9_nbif_gpu_CACHE_LINE_epvf 0x405A403 -#define mmBIF_CFG_EPVF10_nbif_gpu_CACHE_LINE_epvf 0x405A803 -#define mmBIF_CFG_EPVF11_nbif_gpu_CACHE_LINE_epvf 0x405AC03 -#define mmBIF_CFG_EPVF12_nbif_gpu_CACHE_LINE_epvf 0x405B003 -#define mmBIF_CFG_EPVF13_nbif_gpu_CACHE_LINE_epvf 0x405B403 -#define mmBIF_CFG_EPVF14_nbif_gpu_CACHE_LINE_epvf 0x405B803 -#define mmBIF_CFG_EPVF15_nbif_gpu_CACHE_LINE_epvf 0x405BC03 -#define mmnbif_gpu_LATENCY_epvf 0x4058003 -#define mmBIF_CFG_EPVF0_nbif_gpu_LATENCY_epvf 0x4058003 -#define mmBIF_CFG_EPVF1_nbif_gpu_LATENCY_epvf 0x4058403 -#define mmBIF_CFG_EPVF2_nbif_gpu_LATENCY_epvf 0x4058803 -#define mmBIF_CFG_EPVF3_nbif_gpu_LATENCY_epvf 0x4058C03 -#define mmBIF_CFG_EPVF4_nbif_gpu_LATENCY_epvf 0x4059003 -#define mmBIF_CFG_EPVF5_nbif_gpu_LATENCY_epvf 0x4059403 -#define mmBIF_CFG_EPVF6_nbif_gpu_LATENCY_epvf 0x4059803 -#define mmBIF_CFG_EPVF7_nbif_gpu_LATENCY_epvf 0x4059C03 -#define mmBIF_CFG_EPVF8_nbif_gpu_LATENCY_epvf 0x405A003 -#define mmBIF_CFG_EPVF9_nbif_gpu_LATENCY_epvf 0x405A403 -#define mmBIF_CFG_EPVF10_nbif_gpu_LATENCY_epvf 0x405A803 -#define mmBIF_CFG_EPVF11_nbif_gpu_LATENCY_epvf 0x405AC03 -#define mmBIF_CFG_EPVF12_nbif_gpu_LATENCY_epvf 0x405B003 -#define mmBIF_CFG_EPVF13_nbif_gpu_LATENCY_epvf 0x405B403 -#define mmBIF_CFG_EPVF14_nbif_gpu_LATENCY_epvf 0x405B803 -#define mmBIF_CFG_EPVF15_nbif_gpu_LATENCY_epvf 0x405BC03 -#define mmnbif_gpu_HEADER_epvf 0x4058003 -#define mmBIF_CFG_EPVF0_nbif_gpu_HEADER_epvf 0x4058003 -#define mmBIF_CFG_EPVF1_nbif_gpu_HEADER_epvf 0x4058403 -#define mmBIF_CFG_EPVF2_nbif_gpu_HEADER_epvf 0x4058803 -#define mmBIF_CFG_EPVF3_nbif_gpu_HEADER_epvf 0x4058C03 -#define mmBIF_CFG_EPVF4_nbif_gpu_HEADER_epvf 0x4059003 -#define mmBIF_CFG_EPVF5_nbif_gpu_HEADER_epvf 0x4059403 -#define mmBIF_CFG_EPVF6_nbif_gpu_HEADER_epvf 0x4059803 -#define mmBIF_CFG_EPVF7_nbif_gpu_HEADER_epvf 0x4059C03 -#define mmBIF_CFG_EPVF8_nbif_gpu_HEADER_epvf 0x405A003 -#define mmBIF_CFG_EPVF9_nbif_gpu_HEADER_epvf 0x405A403 -#define mmBIF_CFG_EPVF10_nbif_gpu_HEADER_epvf 0x405A803 -#define mmBIF_CFG_EPVF11_nbif_gpu_HEADER_epvf 0x405AC03 -#define mmBIF_CFG_EPVF12_nbif_gpu_HEADER_epvf 0x405B003 -#define mmBIF_CFG_EPVF13_nbif_gpu_HEADER_epvf 0x405B403 -#define mmBIF_CFG_EPVF14_nbif_gpu_HEADER_epvf 0x405B803 -#define mmBIF_CFG_EPVF15_nbif_gpu_HEADER_epvf 0x405BC03 -#define mmnbif_gpu_BIST_epvf 0x4058003 -#define mmBIF_CFG_EPVF0_nbif_gpu_BIST_epvf 0x4058003 -#define mmBIF_CFG_EPVF1_nbif_gpu_BIST_epvf 0x4058403 -#define mmBIF_CFG_EPVF2_nbif_gpu_BIST_epvf 0x4058803 -#define mmBIF_CFG_EPVF3_nbif_gpu_BIST_epvf 0x4058C03 -#define mmBIF_CFG_EPVF4_nbif_gpu_BIST_epvf 0x4059003 -#define mmBIF_CFG_EPVF5_nbif_gpu_BIST_epvf 0x4059403 -#define mmBIF_CFG_EPVF6_nbif_gpu_BIST_epvf 0x4059803 -#define mmBIF_CFG_EPVF7_nbif_gpu_BIST_epvf 0x4059C03 -#define mmBIF_CFG_EPVF8_nbif_gpu_BIST_epvf 0x405A003 -#define mmBIF_CFG_EPVF9_nbif_gpu_BIST_epvf 0x405A403 -#define mmBIF_CFG_EPVF10_nbif_gpu_BIST_epvf 0x405A803 -#define mmBIF_CFG_EPVF11_nbif_gpu_BIST_epvf 0x405AC03 -#define mmBIF_CFG_EPVF12_nbif_gpu_BIST_epvf 0x405B003 -#define mmBIF_CFG_EPVF13_nbif_gpu_BIST_epvf 0x405B403 -#define mmBIF_CFG_EPVF14_nbif_gpu_BIST_epvf 0x405B803 -#define mmBIF_CFG_EPVF15_nbif_gpu_BIST_epvf 0x405BC03 -#define mmnbif_gpu_BASE_ADDR_1_epvf 0x4058004 -#define mmBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_1_epvf 0x4058004 -#define mmBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_1_epvf 0x4058404 -#define mmBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_1_epvf 0x4058804 -#define mmBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_1_epvf 0x4058C04 -#define mmBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_1_epvf 0x4059004 -#define mmBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_1_epvf 0x4059404 -#define mmBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_1_epvf 0x4059804 -#define mmBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_1_epvf 0x4059C04 -#define mmBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_1_epvf 0x405A004 -#define mmBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_1_epvf 0x405A404 -#define mmBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_1_epvf 0x405A804 -#define mmBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_1_epvf 0x405AC04 -#define mmBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_1_epvf 0x405B004 -#define mmBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_1_epvf 0x405B404 -#define mmBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_1_epvf 0x405B804 -#define mmBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_1_epvf 0x405BC04 -#define mmnbif_gpu_BASE_ADDR_2_epvf 0x4058005 -#define mmBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_2_epvf 0x4058005 -#define mmBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_2_epvf 0x4058405 -#define mmBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_2_epvf 0x4058805 -#define mmBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_2_epvf 0x4058C05 -#define mmBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_2_epvf 0x4059005 -#define mmBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_2_epvf 0x4059405 -#define mmBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_2_epvf 0x4059805 -#define mmBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_2_epvf 0x4059C05 -#define mmBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_2_epvf 0x405A005 -#define mmBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_2_epvf 0x405A405 -#define mmBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_2_epvf 0x405A805 -#define mmBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_2_epvf 0x405AC05 -#define mmBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_2_epvf 0x405B005 -#define mmBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_2_epvf 0x405B405 -#define mmBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_2_epvf 0x405B805 -#define mmBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_2_epvf 0x405BC05 -#define mmnbif_gpu_BASE_ADDR_3_epvf 0x4058006 -#define mmBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_3_epvf 0x4058006 -#define mmBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_3_epvf 0x4058406 -#define mmBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_3_epvf 0x4058806 -#define mmBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_3_epvf 0x4058C06 -#define mmBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_3_epvf 0x4059006 -#define mmBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_3_epvf 0x4059406 -#define mmBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_3_epvf 0x4059806 -#define mmBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_3_epvf 0x4059C06 -#define mmBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_3_epvf 0x405A006 -#define mmBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_3_epvf 0x405A406 -#define mmBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_3_epvf 0x405A806 -#define mmBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_3_epvf 0x405AC06 -#define mmBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_3_epvf 0x405B006 -#define mmBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_3_epvf 0x405B406 -#define mmBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_3_epvf 0x405B806 -#define mmBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_3_epvf 0x405BC06 -#define mmnbif_gpu_BASE_ADDR_4_epvf 0x4058007 -#define mmBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_4_epvf 0x4058007 -#define mmBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_4_epvf 0x4058407 -#define mmBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_4_epvf 0x4058807 -#define mmBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_4_epvf 0x4058C07 -#define mmBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_4_epvf 0x4059007 -#define mmBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_4_epvf 0x4059407 -#define mmBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_4_epvf 0x4059807 -#define mmBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_4_epvf 0x4059C07 -#define mmBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_4_epvf 0x405A007 -#define mmBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_4_epvf 0x405A407 -#define mmBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_4_epvf 0x405A807 -#define mmBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_4_epvf 0x405AC07 -#define mmBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_4_epvf 0x405B007 -#define mmBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_4_epvf 0x405B407 -#define mmBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_4_epvf 0x405B807 -#define mmBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_4_epvf 0x405BC07 -#define mmnbif_gpu_BASE_ADDR_5_epvf 0x4058008 -#define mmBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_5_epvf 0x4058008 -#define mmBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_5_epvf 0x4058408 -#define mmBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_5_epvf 0x4058808 -#define mmBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_5_epvf 0x4058C08 -#define mmBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_5_epvf 0x4059008 -#define mmBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_5_epvf 0x4059408 -#define mmBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_5_epvf 0x4059808 -#define mmBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_5_epvf 0x4059C08 -#define mmBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_5_epvf 0x405A008 -#define mmBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_5_epvf 0x405A408 -#define mmBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_5_epvf 0x405A808 -#define mmBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_5_epvf 0x405AC08 -#define mmBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_5_epvf 0x405B008 -#define mmBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_5_epvf 0x405B408 -#define mmBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_5_epvf 0x405B808 -#define mmBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_5_epvf 0x405BC08 -#define mmnbif_gpu_BASE_ADDR_6_epvf 0x4058009 -#define mmBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_6_epvf 0x4058009 -#define mmBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_6_epvf 0x4058409 -#define mmBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_6_epvf 0x4058809 -#define mmBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_6_epvf 0x4058C09 -#define mmBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_6_epvf 0x4059009 -#define mmBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_6_epvf 0x4059409 -#define mmBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_6_epvf 0x4059809 -#define mmBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_6_epvf 0x4059C09 -#define mmBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_6_epvf 0x405A009 -#define mmBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_6_epvf 0x405A409 -#define mmBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_6_epvf 0x405A809 -#define mmBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_6_epvf 0x405AC09 -#define mmBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_6_epvf 0x405B009 -#define mmBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_6_epvf 0x405B409 -#define mmBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_6_epvf 0x405B809 -#define mmBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_6_epvf 0x405BC09 -#define mmnbif_gpu_ROM_BASE_ADDR_epvf 0x405800C -#define mmBIF_CFG_EPVF0_nbif_gpu_ROM_BASE_ADDR_epvf 0x405800C -#define mmBIF_CFG_EPVF1_nbif_gpu_ROM_BASE_ADDR_epvf 0x405840C -#define mmBIF_CFG_EPVF2_nbif_gpu_ROM_BASE_ADDR_epvf 0x405880C -#define mmBIF_CFG_EPVF3_nbif_gpu_ROM_BASE_ADDR_epvf 0x4058C0C -#define mmBIF_CFG_EPVF4_nbif_gpu_ROM_BASE_ADDR_epvf 0x405900C -#define mmBIF_CFG_EPVF5_nbif_gpu_ROM_BASE_ADDR_epvf 0x405940C -#define mmBIF_CFG_EPVF6_nbif_gpu_ROM_BASE_ADDR_epvf 0x405980C -#define mmBIF_CFG_EPVF7_nbif_gpu_ROM_BASE_ADDR_epvf 0x4059C0C -#define mmBIF_CFG_EPVF8_nbif_gpu_ROM_BASE_ADDR_epvf 0x405A00C -#define mmBIF_CFG_EPVF9_nbif_gpu_ROM_BASE_ADDR_epvf 0x405A40C -#define mmBIF_CFG_EPVF10_nbif_gpu_ROM_BASE_ADDR_epvf 0x405A80C -#define mmBIF_CFG_EPVF11_nbif_gpu_ROM_BASE_ADDR_epvf 0x405AC0C -#define mmBIF_CFG_EPVF12_nbif_gpu_ROM_BASE_ADDR_epvf 0x405B00C -#define mmBIF_CFG_EPVF13_nbif_gpu_ROM_BASE_ADDR_epvf 0x405B40C -#define mmBIF_CFG_EPVF14_nbif_gpu_ROM_BASE_ADDR_epvf 0x405B80C -#define mmBIF_CFG_EPVF15_nbif_gpu_ROM_BASE_ADDR_epvf 0x405BC0C -#define mmnbif_gpu_CAP_PTR_epvf 0x405800D -#define mmBIF_CFG_EPVF0_nbif_gpu_CAP_PTR_epvf 0x405800D -#define mmBIF_CFG_EPVF1_nbif_gpu_CAP_PTR_epvf 0x405840D -#define mmBIF_CFG_EPVF2_nbif_gpu_CAP_PTR_epvf 0x405880D -#define mmBIF_CFG_EPVF3_nbif_gpu_CAP_PTR_epvf 0x4058C0D -#define mmBIF_CFG_EPVF4_nbif_gpu_CAP_PTR_epvf 0x405900D -#define mmBIF_CFG_EPVF5_nbif_gpu_CAP_PTR_epvf 0x405940D -#define mmBIF_CFG_EPVF6_nbif_gpu_CAP_PTR_epvf 0x405980D -#define mmBIF_CFG_EPVF7_nbif_gpu_CAP_PTR_epvf 0x4059C0D -#define mmBIF_CFG_EPVF8_nbif_gpu_CAP_PTR_epvf 0x405A00D -#define mmBIF_CFG_EPVF9_nbif_gpu_CAP_PTR_epvf 0x405A40D -#define mmBIF_CFG_EPVF10_nbif_gpu_CAP_PTR_epvf 0x405A80D -#define mmBIF_CFG_EPVF11_nbif_gpu_CAP_PTR_epvf 0x405AC0D -#define mmBIF_CFG_EPVF12_nbif_gpu_CAP_PTR_epvf 0x405B00D -#define mmBIF_CFG_EPVF13_nbif_gpu_CAP_PTR_epvf 0x405B40D -#define mmBIF_CFG_EPVF14_nbif_gpu_CAP_PTR_epvf 0x405B80D -#define mmBIF_CFG_EPVF15_nbif_gpu_CAP_PTR_epvf 0x405BC0D -#define mmnbif_gpu_INTERRUPT_LINE_epvf 0x405800F -#define mmBIF_CFG_EPVF0_nbif_gpu_INTERRUPT_LINE_epvf 0x405800F -#define mmBIF_CFG_EPVF1_nbif_gpu_INTERRUPT_LINE_epvf 0x405840F -#define mmBIF_CFG_EPVF2_nbif_gpu_INTERRUPT_LINE_epvf 0x405880F -#define mmBIF_CFG_EPVF3_nbif_gpu_INTERRUPT_LINE_epvf 0x4058C0F -#define mmBIF_CFG_EPVF4_nbif_gpu_INTERRUPT_LINE_epvf 0x405900F -#define mmBIF_CFG_EPVF5_nbif_gpu_INTERRUPT_LINE_epvf 0x405940F -#define mmBIF_CFG_EPVF6_nbif_gpu_INTERRUPT_LINE_epvf 0x405980F -#define mmBIF_CFG_EPVF7_nbif_gpu_INTERRUPT_LINE_epvf 0x4059C0F -#define mmBIF_CFG_EPVF8_nbif_gpu_INTERRUPT_LINE_epvf 0x405A00F -#define mmBIF_CFG_EPVF9_nbif_gpu_INTERRUPT_LINE_epvf 0x405A40F -#define mmBIF_CFG_EPVF10_nbif_gpu_INTERRUPT_LINE_epvf 0x405A80F -#define mmBIF_CFG_EPVF11_nbif_gpu_INTERRUPT_LINE_epvf 0x405AC0F -#define mmBIF_CFG_EPVF12_nbif_gpu_INTERRUPT_LINE_epvf 0x405B00F -#define mmBIF_CFG_EPVF13_nbif_gpu_INTERRUPT_LINE_epvf 0x405B40F -#define mmBIF_CFG_EPVF14_nbif_gpu_INTERRUPT_LINE_epvf 0x405B80F -#define mmBIF_CFG_EPVF15_nbif_gpu_INTERRUPT_LINE_epvf 0x405BC0F -#define mmnbif_gpu_INTERRUPT_PIN_epvf 0x405800F -#define mmBIF_CFG_EPVF0_nbif_gpu_INTERRUPT_PIN_epvf 0x405800F -#define mmBIF_CFG_EPVF1_nbif_gpu_INTERRUPT_PIN_epvf 0x405840F -#define mmBIF_CFG_EPVF2_nbif_gpu_INTERRUPT_PIN_epvf 0x405880F -#define mmBIF_CFG_EPVF3_nbif_gpu_INTERRUPT_PIN_epvf 0x4058C0F -#define mmBIF_CFG_EPVF4_nbif_gpu_INTERRUPT_PIN_epvf 0x405900F -#define mmBIF_CFG_EPVF5_nbif_gpu_INTERRUPT_PIN_epvf 0x405940F -#define mmBIF_CFG_EPVF6_nbif_gpu_INTERRUPT_PIN_epvf 0x405980F -#define mmBIF_CFG_EPVF7_nbif_gpu_INTERRUPT_PIN_epvf 0x4059C0F -#define mmBIF_CFG_EPVF8_nbif_gpu_INTERRUPT_PIN_epvf 0x405A00F -#define mmBIF_CFG_EPVF9_nbif_gpu_INTERRUPT_PIN_epvf 0x405A40F -#define mmBIF_CFG_EPVF10_nbif_gpu_INTERRUPT_PIN_epvf 0x405A80F -#define mmBIF_CFG_EPVF11_nbif_gpu_INTERRUPT_PIN_epvf 0x405AC0F -#define mmBIF_CFG_EPVF12_nbif_gpu_INTERRUPT_PIN_epvf 0x405B00F -#define mmBIF_CFG_EPVF13_nbif_gpu_INTERRUPT_PIN_epvf 0x405B40F -#define mmBIF_CFG_EPVF14_nbif_gpu_INTERRUPT_PIN_epvf 0x405B80F -#define mmBIF_CFG_EPVF15_nbif_gpu_INTERRUPT_PIN_epvf 0x405BC0F -#define mmnbif_gpu_ADAPTER_ID_epvf 0x405800B -#define mmBIF_CFG_EPVF0_nbif_gpu_ADAPTER_ID_epvf 0x405800B -#define mmBIF_CFG_EPVF1_nbif_gpu_ADAPTER_ID_epvf 0x405840B -#define mmBIF_CFG_EPVF2_nbif_gpu_ADAPTER_ID_epvf 0x405880B -#define mmBIF_CFG_EPVF3_nbif_gpu_ADAPTER_ID_epvf 0x4058C0B -#define mmBIF_CFG_EPVF4_nbif_gpu_ADAPTER_ID_epvf 0x405900B -#define mmBIF_CFG_EPVF5_nbif_gpu_ADAPTER_ID_epvf 0x405940B -#define mmBIF_CFG_EPVF6_nbif_gpu_ADAPTER_ID_epvf 0x405980B -#define mmBIF_CFG_EPVF7_nbif_gpu_ADAPTER_ID_epvf 0x4059C0B -#define mmBIF_CFG_EPVF8_nbif_gpu_ADAPTER_ID_epvf 0x405A00B -#define mmBIF_CFG_EPVF9_nbif_gpu_ADAPTER_ID_epvf 0x405A40B -#define mmBIF_CFG_EPVF10_nbif_gpu_ADAPTER_ID_epvf 0x405A80B -#define mmBIF_CFG_EPVF11_nbif_gpu_ADAPTER_ID_epvf 0x405AC0B -#define mmBIF_CFG_EPVF12_nbif_gpu_ADAPTER_ID_epvf 0x405B00B -#define mmBIF_CFG_EPVF13_nbif_gpu_ADAPTER_ID_epvf 0x405B40B -#define mmBIF_CFG_EPVF14_nbif_gpu_ADAPTER_ID_epvf 0x405B80B -#define mmBIF_CFG_EPVF15_nbif_gpu_ADAPTER_ID_epvf 0x405BC0B -#define mmnbif_gpu_PCIE_CAP_LIST_epvf 0x4058019 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_CAP_LIST_epvf 0x4058019 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_CAP_LIST_epvf 0x4058419 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_CAP_LIST_epvf 0x4058819 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_CAP_LIST_epvf 0x4058C19 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_CAP_LIST_epvf 0x4059019 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_CAP_LIST_epvf 0x4059419 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_CAP_LIST_epvf 0x4059819 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_CAP_LIST_epvf 0x4059C19 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_CAP_LIST_epvf 0x405A019 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_CAP_LIST_epvf 0x405A419 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_CAP_LIST_epvf 0x405A819 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_CAP_LIST_epvf 0x405AC19 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_CAP_LIST_epvf 0x405B019 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_CAP_LIST_epvf 0x405B419 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_CAP_LIST_epvf 0x405B819 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_CAP_LIST_epvf 0x405BC19 -#define mmnbif_gpu_PCIE_CAP_epvf 0x4058019 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_CAP_epvf 0x4058019 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_CAP_epvf 0x4058419 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_CAP_epvf 0x4058819 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_CAP_epvf 0x4058C19 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_CAP_epvf 0x4059019 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_CAP_epvf 0x4059419 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_CAP_epvf 0x4059819 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_CAP_epvf 0x4059C19 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_CAP_epvf 0x405A019 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_CAP_epvf 0x405A419 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_CAP_epvf 0x405A819 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_CAP_epvf 0x405AC19 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_CAP_epvf 0x405B019 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_CAP_epvf 0x405B419 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_CAP_epvf 0x405B819 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_CAP_epvf 0x405BC19 -#define mmnbif_gpu_DEVICE_CAP_epvf 0x405801A -#define mmBIF_CFG_EPVF0_nbif_gpu_DEVICE_CAP_epvf 0x405801A -#define mmBIF_CFG_EPVF1_nbif_gpu_DEVICE_CAP_epvf 0x405841A -#define mmBIF_CFG_EPVF2_nbif_gpu_DEVICE_CAP_epvf 0x405881A -#define mmBIF_CFG_EPVF3_nbif_gpu_DEVICE_CAP_epvf 0x4058C1A -#define mmBIF_CFG_EPVF4_nbif_gpu_DEVICE_CAP_epvf 0x405901A -#define mmBIF_CFG_EPVF5_nbif_gpu_DEVICE_CAP_epvf 0x405941A -#define mmBIF_CFG_EPVF6_nbif_gpu_DEVICE_CAP_epvf 0x405981A -#define mmBIF_CFG_EPVF7_nbif_gpu_DEVICE_CAP_epvf 0x4059C1A -#define mmBIF_CFG_EPVF8_nbif_gpu_DEVICE_CAP_epvf 0x405A01A -#define mmBIF_CFG_EPVF9_nbif_gpu_DEVICE_CAP_epvf 0x405A41A -#define mmBIF_CFG_EPVF10_nbif_gpu_DEVICE_CAP_epvf 0x405A81A -#define mmBIF_CFG_EPVF11_nbif_gpu_DEVICE_CAP_epvf 0x405AC1A -#define mmBIF_CFG_EPVF12_nbif_gpu_DEVICE_CAP_epvf 0x405B01A -#define mmBIF_CFG_EPVF13_nbif_gpu_DEVICE_CAP_epvf 0x405B41A -#define mmBIF_CFG_EPVF14_nbif_gpu_DEVICE_CAP_epvf 0x405B81A -#define mmBIF_CFG_EPVF15_nbif_gpu_DEVICE_CAP_epvf 0x405BC1A -#define mmnbif_gpu_DEVICE_CNTL_epvf 0x405801B -#define mmBIF_CFG_EPVF0_nbif_gpu_DEVICE_CNTL_epvf 0x405801B -#define mmBIF_CFG_EPVF1_nbif_gpu_DEVICE_CNTL_epvf 0x405841B -#define mmBIF_CFG_EPVF2_nbif_gpu_DEVICE_CNTL_epvf 0x405881B -#define mmBIF_CFG_EPVF3_nbif_gpu_DEVICE_CNTL_epvf 0x4058C1B -#define mmBIF_CFG_EPVF4_nbif_gpu_DEVICE_CNTL_epvf 0x405901B -#define mmBIF_CFG_EPVF5_nbif_gpu_DEVICE_CNTL_epvf 0x405941B -#define mmBIF_CFG_EPVF6_nbif_gpu_DEVICE_CNTL_epvf 0x405981B -#define mmBIF_CFG_EPVF7_nbif_gpu_DEVICE_CNTL_epvf 0x4059C1B -#define mmBIF_CFG_EPVF8_nbif_gpu_DEVICE_CNTL_epvf 0x405A01B -#define mmBIF_CFG_EPVF9_nbif_gpu_DEVICE_CNTL_epvf 0x405A41B -#define mmBIF_CFG_EPVF10_nbif_gpu_DEVICE_CNTL_epvf 0x405A81B -#define mmBIF_CFG_EPVF11_nbif_gpu_DEVICE_CNTL_epvf 0x405AC1B -#define mmBIF_CFG_EPVF12_nbif_gpu_DEVICE_CNTL_epvf 0x405B01B -#define mmBIF_CFG_EPVF13_nbif_gpu_DEVICE_CNTL_epvf 0x405B41B -#define mmBIF_CFG_EPVF14_nbif_gpu_DEVICE_CNTL_epvf 0x405B81B -#define mmBIF_CFG_EPVF15_nbif_gpu_DEVICE_CNTL_epvf 0x405BC1B -#define mmnbif_gpu_DEVICE_STATUS_epvf 0x405801B -#define mmBIF_CFG_EPVF0_nbif_gpu_DEVICE_STATUS_epvf 0x405801B -#define mmBIF_CFG_EPVF1_nbif_gpu_DEVICE_STATUS_epvf 0x405841B -#define mmBIF_CFG_EPVF2_nbif_gpu_DEVICE_STATUS_epvf 0x405881B -#define mmBIF_CFG_EPVF3_nbif_gpu_DEVICE_STATUS_epvf 0x4058C1B -#define mmBIF_CFG_EPVF4_nbif_gpu_DEVICE_STATUS_epvf 0x405901B -#define mmBIF_CFG_EPVF5_nbif_gpu_DEVICE_STATUS_epvf 0x405941B -#define mmBIF_CFG_EPVF6_nbif_gpu_DEVICE_STATUS_epvf 0x405981B -#define mmBIF_CFG_EPVF7_nbif_gpu_DEVICE_STATUS_epvf 0x4059C1B -#define mmBIF_CFG_EPVF8_nbif_gpu_DEVICE_STATUS_epvf 0x405A01B -#define mmBIF_CFG_EPVF9_nbif_gpu_DEVICE_STATUS_epvf 0x405A41B -#define mmBIF_CFG_EPVF10_nbif_gpu_DEVICE_STATUS_epvf 0x405A81B -#define mmBIF_CFG_EPVF11_nbif_gpu_DEVICE_STATUS_epvf 0x405AC1B -#define mmBIF_CFG_EPVF12_nbif_gpu_DEVICE_STATUS_epvf 0x405B01B -#define mmBIF_CFG_EPVF13_nbif_gpu_DEVICE_STATUS_epvf 0x405B41B -#define mmBIF_CFG_EPVF14_nbif_gpu_DEVICE_STATUS_epvf 0x405B81B -#define mmBIF_CFG_EPVF15_nbif_gpu_DEVICE_STATUS_epvf 0x405BC1B -#define mmnbif_gpu_LINK_CAP_epvf 0x405801C -#define mmBIF_CFG_EPVF0_nbif_gpu_LINK_CAP_epvf 0x405801C -#define mmBIF_CFG_EPVF1_nbif_gpu_LINK_CAP_epvf 0x405841C -#define mmBIF_CFG_EPVF2_nbif_gpu_LINK_CAP_epvf 0x405881C -#define mmBIF_CFG_EPVF3_nbif_gpu_LINK_CAP_epvf 0x4058C1C -#define mmBIF_CFG_EPVF4_nbif_gpu_LINK_CAP_epvf 0x405901C -#define mmBIF_CFG_EPVF5_nbif_gpu_LINK_CAP_epvf 0x405941C -#define mmBIF_CFG_EPVF6_nbif_gpu_LINK_CAP_epvf 0x405981C -#define mmBIF_CFG_EPVF7_nbif_gpu_LINK_CAP_epvf 0x4059C1C -#define mmBIF_CFG_EPVF8_nbif_gpu_LINK_CAP_epvf 0x405A01C -#define mmBIF_CFG_EPVF9_nbif_gpu_LINK_CAP_epvf 0x405A41C -#define mmBIF_CFG_EPVF10_nbif_gpu_LINK_CAP_epvf 0x405A81C -#define mmBIF_CFG_EPVF11_nbif_gpu_LINK_CAP_epvf 0x405AC1C -#define mmBIF_CFG_EPVF12_nbif_gpu_LINK_CAP_epvf 0x405B01C -#define mmBIF_CFG_EPVF13_nbif_gpu_LINK_CAP_epvf 0x405B41C -#define mmBIF_CFG_EPVF14_nbif_gpu_LINK_CAP_epvf 0x405B81C -#define mmBIF_CFG_EPVF15_nbif_gpu_LINK_CAP_epvf 0x405BC1C -#define mmnbif_gpu_LINK_CNTL_epvf 0x405801D -#define mmBIF_CFG_EPVF0_nbif_gpu_LINK_CNTL_epvf 0x405801D -#define mmBIF_CFG_EPVF1_nbif_gpu_LINK_CNTL_epvf 0x405841D -#define mmBIF_CFG_EPVF2_nbif_gpu_LINK_CNTL_epvf 0x405881D -#define mmBIF_CFG_EPVF3_nbif_gpu_LINK_CNTL_epvf 0x4058C1D -#define mmBIF_CFG_EPVF4_nbif_gpu_LINK_CNTL_epvf 0x405901D -#define mmBIF_CFG_EPVF5_nbif_gpu_LINK_CNTL_epvf 0x405941D -#define mmBIF_CFG_EPVF6_nbif_gpu_LINK_CNTL_epvf 0x405981D -#define mmBIF_CFG_EPVF7_nbif_gpu_LINK_CNTL_epvf 0x4059C1D -#define mmBIF_CFG_EPVF8_nbif_gpu_LINK_CNTL_epvf 0x405A01D -#define mmBIF_CFG_EPVF9_nbif_gpu_LINK_CNTL_epvf 0x405A41D -#define mmBIF_CFG_EPVF10_nbif_gpu_LINK_CNTL_epvf 0x405A81D -#define mmBIF_CFG_EPVF11_nbif_gpu_LINK_CNTL_epvf 0x405AC1D -#define mmBIF_CFG_EPVF12_nbif_gpu_LINK_CNTL_epvf 0x405B01D -#define mmBIF_CFG_EPVF13_nbif_gpu_LINK_CNTL_epvf 0x405B41D -#define mmBIF_CFG_EPVF14_nbif_gpu_LINK_CNTL_epvf 0x405B81D -#define mmBIF_CFG_EPVF15_nbif_gpu_LINK_CNTL_epvf 0x405BC1D -#define mmnbif_gpu_LINK_STATUS_epvf 0x405801D -#define mmBIF_CFG_EPVF0_nbif_gpu_LINK_STATUS_epvf 0x405801D -#define mmBIF_CFG_EPVF1_nbif_gpu_LINK_STATUS_epvf 0x405841D -#define mmBIF_CFG_EPVF2_nbif_gpu_LINK_STATUS_epvf 0x405881D -#define mmBIF_CFG_EPVF3_nbif_gpu_LINK_STATUS_epvf 0x4058C1D -#define mmBIF_CFG_EPVF4_nbif_gpu_LINK_STATUS_epvf 0x405901D -#define mmBIF_CFG_EPVF5_nbif_gpu_LINK_STATUS_epvf 0x405941D -#define mmBIF_CFG_EPVF6_nbif_gpu_LINK_STATUS_epvf 0x405981D -#define mmBIF_CFG_EPVF7_nbif_gpu_LINK_STATUS_epvf 0x4059C1D -#define mmBIF_CFG_EPVF8_nbif_gpu_LINK_STATUS_epvf 0x405A01D -#define mmBIF_CFG_EPVF9_nbif_gpu_LINK_STATUS_epvf 0x405A41D -#define mmBIF_CFG_EPVF10_nbif_gpu_LINK_STATUS_epvf 0x405A81D -#define mmBIF_CFG_EPVF11_nbif_gpu_LINK_STATUS_epvf 0x405AC1D -#define mmBIF_CFG_EPVF12_nbif_gpu_LINK_STATUS_epvf 0x405B01D -#define mmBIF_CFG_EPVF13_nbif_gpu_LINK_STATUS_epvf 0x405B41D -#define mmBIF_CFG_EPVF14_nbif_gpu_LINK_STATUS_epvf 0x405B81D -#define mmBIF_CFG_EPVF15_nbif_gpu_LINK_STATUS_epvf 0x405BC1D -#define mmnbif_gpu_DEVICE_CAP2_epvf 0x4058022 -#define mmBIF_CFG_EPVF0_nbif_gpu_DEVICE_CAP2_epvf 0x4058022 -#define mmBIF_CFG_EPVF1_nbif_gpu_DEVICE_CAP2_epvf 0x4058422 -#define mmBIF_CFG_EPVF2_nbif_gpu_DEVICE_CAP2_epvf 0x4058822 -#define mmBIF_CFG_EPVF3_nbif_gpu_DEVICE_CAP2_epvf 0x4058C22 -#define mmBIF_CFG_EPVF4_nbif_gpu_DEVICE_CAP2_epvf 0x4059022 -#define mmBIF_CFG_EPVF5_nbif_gpu_DEVICE_CAP2_epvf 0x4059422 -#define mmBIF_CFG_EPVF6_nbif_gpu_DEVICE_CAP2_epvf 0x4059822 -#define mmBIF_CFG_EPVF7_nbif_gpu_DEVICE_CAP2_epvf 0x4059C22 -#define mmBIF_CFG_EPVF8_nbif_gpu_DEVICE_CAP2_epvf 0x405A022 -#define mmBIF_CFG_EPVF9_nbif_gpu_DEVICE_CAP2_epvf 0x405A422 -#define mmBIF_CFG_EPVF10_nbif_gpu_DEVICE_CAP2_epvf 0x405A822 -#define mmBIF_CFG_EPVF11_nbif_gpu_DEVICE_CAP2_epvf 0x405AC22 -#define mmBIF_CFG_EPVF12_nbif_gpu_DEVICE_CAP2_epvf 0x405B022 -#define mmBIF_CFG_EPVF13_nbif_gpu_DEVICE_CAP2_epvf 0x405B422 -#define mmBIF_CFG_EPVF14_nbif_gpu_DEVICE_CAP2_epvf 0x405B822 -#define mmBIF_CFG_EPVF15_nbif_gpu_DEVICE_CAP2_epvf 0x405BC22 -#define mmnbif_gpu_DEVICE_CNTL2_epvf 0x4058023 -#define mmBIF_CFG_EPVF0_nbif_gpu_DEVICE_CNTL2_epvf 0x4058023 -#define mmBIF_CFG_EPVF1_nbif_gpu_DEVICE_CNTL2_epvf 0x4058423 -#define mmBIF_CFG_EPVF2_nbif_gpu_DEVICE_CNTL2_epvf 0x4058823 -#define mmBIF_CFG_EPVF3_nbif_gpu_DEVICE_CNTL2_epvf 0x4058C23 -#define mmBIF_CFG_EPVF4_nbif_gpu_DEVICE_CNTL2_epvf 0x4059023 -#define mmBIF_CFG_EPVF5_nbif_gpu_DEVICE_CNTL2_epvf 0x4059423 -#define mmBIF_CFG_EPVF6_nbif_gpu_DEVICE_CNTL2_epvf 0x4059823 -#define mmBIF_CFG_EPVF7_nbif_gpu_DEVICE_CNTL2_epvf 0x4059C23 -#define mmBIF_CFG_EPVF8_nbif_gpu_DEVICE_CNTL2_epvf 0x405A023 -#define mmBIF_CFG_EPVF9_nbif_gpu_DEVICE_CNTL2_epvf 0x405A423 -#define mmBIF_CFG_EPVF10_nbif_gpu_DEVICE_CNTL2_epvf 0x405A823 -#define mmBIF_CFG_EPVF11_nbif_gpu_DEVICE_CNTL2_epvf 0x405AC23 -#define mmBIF_CFG_EPVF12_nbif_gpu_DEVICE_CNTL2_epvf 0x405B023 -#define mmBIF_CFG_EPVF13_nbif_gpu_DEVICE_CNTL2_epvf 0x405B423 -#define mmBIF_CFG_EPVF14_nbif_gpu_DEVICE_CNTL2_epvf 0x405B823 -#define mmBIF_CFG_EPVF15_nbif_gpu_DEVICE_CNTL2_epvf 0x405BC23 -#define mmnbif_gpu_DEVICE_STATUS2_epvf 0x4058023 -#define mmBIF_CFG_EPVF0_nbif_gpu_DEVICE_STATUS2_epvf 0x4058023 -#define mmBIF_CFG_EPVF1_nbif_gpu_DEVICE_STATUS2_epvf 0x4058423 -#define mmBIF_CFG_EPVF2_nbif_gpu_DEVICE_STATUS2_epvf 0x4058823 -#define mmBIF_CFG_EPVF3_nbif_gpu_DEVICE_STATUS2_epvf 0x4058C23 -#define mmBIF_CFG_EPVF4_nbif_gpu_DEVICE_STATUS2_epvf 0x4059023 -#define mmBIF_CFG_EPVF5_nbif_gpu_DEVICE_STATUS2_epvf 0x4059423 -#define mmBIF_CFG_EPVF6_nbif_gpu_DEVICE_STATUS2_epvf 0x4059823 -#define mmBIF_CFG_EPVF7_nbif_gpu_DEVICE_STATUS2_epvf 0x4059C23 -#define mmBIF_CFG_EPVF8_nbif_gpu_DEVICE_STATUS2_epvf 0x405A023 -#define mmBIF_CFG_EPVF9_nbif_gpu_DEVICE_STATUS2_epvf 0x405A423 -#define mmBIF_CFG_EPVF10_nbif_gpu_DEVICE_STATUS2_epvf 0x405A823 -#define mmBIF_CFG_EPVF11_nbif_gpu_DEVICE_STATUS2_epvf 0x405AC23 -#define mmBIF_CFG_EPVF12_nbif_gpu_DEVICE_STATUS2_epvf 0x405B023 -#define mmBIF_CFG_EPVF13_nbif_gpu_DEVICE_STATUS2_epvf 0x405B423 -#define mmBIF_CFG_EPVF14_nbif_gpu_DEVICE_STATUS2_epvf 0x405B823 -#define mmBIF_CFG_EPVF15_nbif_gpu_DEVICE_STATUS2_epvf 0x405BC23 -#define mmnbif_gpu_LINK_CAP2_epvf 0x4058024 -#define mmBIF_CFG_EPVF0_nbif_gpu_LINK_CAP2_epvf 0x4058024 -#define mmBIF_CFG_EPVF1_nbif_gpu_LINK_CAP2_epvf 0x4058424 -#define mmBIF_CFG_EPVF2_nbif_gpu_LINK_CAP2_epvf 0x4058824 -#define mmBIF_CFG_EPVF3_nbif_gpu_LINK_CAP2_epvf 0x4058C24 -#define mmBIF_CFG_EPVF4_nbif_gpu_LINK_CAP2_epvf 0x4059024 -#define mmBIF_CFG_EPVF5_nbif_gpu_LINK_CAP2_epvf 0x4059424 -#define mmBIF_CFG_EPVF6_nbif_gpu_LINK_CAP2_epvf 0x4059824 -#define mmBIF_CFG_EPVF7_nbif_gpu_LINK_CAP2_epvf 0x4059C24 -#define mmBIF_CFG_EPVF8_nbif_gpu_LINK_CAP2_epvf 0x405A024 -#define mmBIF_CFG_EPVF9_nbif_gpu_LINK_CAP2_epvf 0x405A424 -#define mmBIF_CFG_EPVF10_nbif_gpu_LINK_CAP2_epvf 0x405A824 -#define mmBIF_CFG_EPVF11_nbif_gpu_LINK_CAP2_epvf 0x405AC24 -#define mmBIF_CFG_EPVF12_nbif_gpu_LINK_CAP2_epvf 0x405B024 -#define mmBIF_CFG_EPVF13_nbif_gpu_LINK_CAP2_epvf 0x405B424 -#define mmBIF_CFG_EPVF14_nbif_gpu_LINK_CAP2_epvf 0x405B824 -#define mmBIF_CFG_EPVF15_nbif_gpu_LINK_CAP2_epvf 0x405BC24 -#define mmnbif_gpu_LINK_CNTL2_epvf 0x4058025 -#define mmBIF_CFG_EPVF0_nbif_gpu_LINK_CNTL2_epvf 0x4058025 -#define mmBIF_CFG_EPVF1_nbif_gpu_LINK_CNTL2_epvf 0x4058425 -#define mmBIF_CFG_EPVF2_nbif_gpu_LINK_CNTL2_epvf 0x4058825 -#define mmBIF_CFG_EPVF3_nbif_gpu_LINK_CNTL2_epvf 0x4058C25 -#define mmBIF_CFG_EPVF4_nbif_gpu_LINK_CNTL2_epvf 0x4059025 -#define mmBIF_CFG_EPVF5_nbif_gpu_LINK_CNTL2_epvf 0x4059425 -#define mmBIF_CFG_EPVF6_nbif_gpu_LINK_CNTL2_epvf 0x4059825 -#define mmBIF_CFG_EPVF7_nbif_gpu_LINK_CNTL2_epvf 0x4059C25 -#define mmBIF_CFG_EPVF8_nbif_gpu_LINK_CNTL2_epvf 0x405A025 -#define mmBIF_CFG_EPVF9_nbif_gpu_LINK_CNTL2_epvf 0x405A425 -#define mmBIF_CFG_EPVF10_nbif_gpu_LINK_CNTL2_epvf 0x405A825 -#define mmBIF_CFG_EPVF11_nbif_gpu_LINK_CNTL2_epvf 0x405AC25 -#define mmBIF_CFG_EPVF12_nbif_gpu_LINK_CNTL2_epvf 0x405B025 -#define mmBIF_CFG_EPVF13_nbif_gpu_LINK_CNTL2_epvf 0x405B425 -#define mmBIF_CFG_EPVF14_nbif_gpu_LINK_CNTL2_epvf 0x405B825 -#define mmBIF_CFG_EPVF15_nbif_gpu_LINK_CNTL2_epvf 0x405BC25 -#define mmnbif_gpu_LINK_STATUS2_epvf 0x4058025 -#define mmBIF_CFG_EPVF0_nbif_gpu_LINK_STATUS2_epvf 0x4058025 -#define mmBIF_CFG_EPVF1_nbif_gpu_LINK_STATUS2_epvf 0x4058425 -#define mmBIF_CFG_EPVF2_nbif_gpu_LINK_STATUS2_epvf 0x4058825 -#define mmBIF_CFG_EPVF3_nbif_gpu_LINK_STATUS2_epvf 0x4058C25 -#define mmBIF_CFG_EPVF4_nbif_gpu_LINK_STATUS2_epvf 0x4059025 -#define mmBIF_CFG_EPVF5_nbif_gpu_LINK_STATUS2_epvf 0x4059425 -#define mmBIF_CFG_EPVF6_nbif_gpu_LINK_STATUS2_epvf 0x4059825 -#define mmBIF_CFG_EPVF7_nbif_gpu_LINK_STATUS2_epvf 0x4059C25 -#define mmBIF_CFG_EPVF8_nbif_gpu_LINK_STATUS2_epvf 0x405A025 -#define mmBIF_CFG_EPVF9_nbif_gpu_LINK_STATUS2_epvf 0x405A425 -#define mmBIF_CFG_EPVF10_nbif_gpu_LINK_STATUS2_epvf 0x405A825 -#define mmBIF_CFG_EPVF11_nbif_gpu_LINK_STATUS2_epvf 0x405AC25 -#define mmBIF_CFG_EPVF12_nbif_gpu_LINK_STATUS2_epvf 0x405B025 -#define mmBIF_CFG_EPVF13_nbif_gpu_LINK_STATUS2_epvf 0x405B425 -#define mmBIF_CFG_EPVF14_nbif_gpu_LINK_STATUS2_epvf 0x405B825 -#define mmBIF_CFG_EPVF15_nbif_gpu_LINK_STATUS2_epvf 0x405BC25 -#define mmnbif_gpu_SLOT_CAP2_epvf 0x4058026 -#define mmBIF_CFG_EPVF0_nbif_gpu_SLOT_CAP2_epvf 0x4058026 -#define mmBIF_CFG_EPVF1_nbif_gpu_SLOT_CAP2_epvf 0x4058426 -#define mmBIF_CFG_EPVF2_nbif_gpu_SLOT_CAP2_epvf 0x4058826 -#define mmBIF_CFG_EPVF3_nbif_gpu_SLOT_CAP2_epvf 0x4058C26 -#define mmBIF_CFG_EPVF4_nbif_gpu_SLOT_CAP2_epvf 0x4059026 -#define mmBIF_CFG_EPVF5_nbif_gpu_SLOT_CAP2_epvf 0x4059426 -#define mmBIF_CFG_EPVF6_nbif_gpu_SLOT_CAP2_epvf 0x4059826 -#define mmBIF_CFG_EPVF7_nbif_gpu_SLOT_CAP2_epvf 0x4059C26 -#define mmBIF_CFG_EPVF8_nbif_gpu_SLOT_CAP2_epvf 0x405A026 -#define mmBIF_CFG_EPVF9_nbif_gpu_SLOT_CAP2_epvf 0x405A426 -#define mmBIF_CFG_EPVF10_nbif_gpu_SLOT_CAP2_epvf 0x405A826 -#define mmBIF_CFG_EPVF11_nbif_gpu_SLOT_CAP2_epvf 0x405AC26 -#define mmBIF_CFG_EPVF12_nbif_gpu_SLOT_CAP2_epvf 0x405B026 -#define mmBIF_CFG_EPVF13_nbif_gpu_SLOT_CAP2_epvf 0x405B426 -#define mmBIF_CFG_EPVF14_nbif_gpu_SLOT_CAP2_epvf 0x405B826 -#define mmBIF_CFG_EPVF15_nbif_gpu_SLOT_CAP2_epvf 0x405BC26 -#define mmnbif_gpu_SLOT_CNTL2_epvf 0x4058027 -#define mmBIF_CFG_EPVF0_nbif_gpu_SLOT_CNTL2_epvf 0x4058027 -#define mmBIF_CFG_EPVF1_nbif_gpu_SLOT_CNTL2_epvf 0x4058427 -#define mmBIF_CFG_EPVF2_nbif_gpu_SLOT_CNTL2_epvf 0x4058827 -#define mmBIF_CFG_EPVF3_nbif_gpu_SLOT_CNTL2_epvf 0x4058C27 -#define mmBIF_CFG_EPVF4_nbif_gpu_SLOT_CNTL2_epvf 0x4059027 -#define mmBIF_CFG_EPVF5_nbif_gpu_SLOT_CNTL2_epvf 0x4059427 -#define mmBIF_CFG_EPVF6_nbif_gpu_SLOT_CNTL2_epvf 0x4059827 -#define mmBIF_CFG_EPVF7_nbif_gpu_SLOT_CNTL2_epvf 0x4059C27 -#define mmBIF_CFG_EPVF8_nbif_gpu_SLOT_CNTL2_epvf 0x405A027 -#define mmBIF_CFG_EPVF9_nbif_gpu_SLOT_CNTL2_epvf 0x405A427 -#define mmBIF_CFG_EPVF10_nbif_gpu_SLOT_CNTL2_epvf 0x405A827 -#define mmBIF_CFG_EPVF11_nbif_gpu_SLOT_CNTL2_epvf 0x405AC27 -#define mmBIF_CFG_EPVF12_nbif_gpu_SLOT_CNTL2_epvf 0x405B027 -#define mmBIF_CFG_EPVF13_nbif_gpu_SLOT_CNTL2_epvf 0x405B427 -#define mmBIF_CFG_EPVF14_nbif_gpu_SLOT_CNTL2_epvf 0x405B827 -#define mmBIF_CFG_EPVF15_nbif_gpu_SLOT_CNTL2_epvf 0x405BC27 -#define mmnbif_gpu_SLOT_STATUS2_epvf 0x4058027 -#define mmBIF_CFG_EPVF0_nbif_gpu_SLOT_STATUS2_epvf 0x4058027 -#define mmBIF_CFG_EPVF1_nbif_gpu_SLOT_STATUS2_epvf 0x4058427 -#define mmBIF_CFG_EPVF2_nbif_gpu_SLOT_STATUS2_epvf 0x4058827 -#define mmBIF_CFG_EPVF3_nbif_gpu_SLOT_STATUS2_epvf 0x4058C27 -#define mmBIF_CFG_EPVF4_nbif_gpu_SLOT_STATUS2_epvf 0x4059027 -#define mmBIF_CFG_EPVF5_nbif_gpu_SLOT_STATUS2_epvf 0x4059427 -#define mmBIF_CFG_EPVF6_nbif_gpu_SLOT_STATUS2_epvf 0x4059827 -#define mmBIF_CFG_EPVF7_nbif_gpu_SLOT_STATUS2_epvf 0x4059C27 -#define mmBIF_CFG_EPVF8_nbif_gpu_SLOT_STATUS2_epvf 0x405A027 -#define mmBIF_CFG_EPVF9_nbif_gpu_SLOT_STATUS2_epvf 0x405A427 -#define mmBIF_CFG_EPVF10_nbif_gpu_SLOT_STATUS2_epvf 0x405A827 -#define mmBIF_CFG_EPVF11_nbif_gpu_SLOT_STATUS2_epvf 0x405AC27 -#define mmBIF_CFG_EPVF12_nbif_gpu_SLOT_STATUS2_epvf 0x405B027 -#define mmBIF_CFG_EPVF13_nbif_gpu_SLOT_STATUS2_epvf 0x405B427 -#define mmBIF_CFG_EPVF14_nbif_gpu_SLOT_STATUS2_epvf 0x405B827 -#define mmBIF_CFG_EPVF15_nbif_gpu_SLOT_STATUS2_epvf 0x405BC27 -#define mmnbif_gpu_MSI_CAP_LIST_epvf 0x4058028 -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_CAP_LIST_epvf 0x4058028 -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_CAP_LIST_epvf 0x4058428 -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_CAP_LIST_epvf 0x4058828 -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_CAP_LIST_epvf 0x4058C28 -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_CAP_LIST_epvf 0x4059028 -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_CAP_LIST_epvf 0x4059428 -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_CAP_LIST_epvf 0x4059828 -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_CAP_LIST_epvf 0x4059C28 -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_CAP_LIST_epvf 0x405A028 -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_CAP_LIST_epvf 0x405A428 -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_CAP_LIST_epvf 0x405A828 -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_CAP_LIST_epvf 0x405AC28 -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_CAP_LIST_epvf 0x405B028 -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_CAP_LIST_epvf 0x405B428 -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_CAP_LIST_epvf 0x405B828 -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_CAP_LIST_epvf 0x405BC28 -#define mmnbif_gpu_MSI_MSG_CNTL_epvf 0x4058028 -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_CNTL_epvf 0x4058028 -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_CNTL_epvf 0x4058428 -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_CNTL_epvf 0x4058828 -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_CNTL_epvf 0x4058C28 -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_CNTL_epvf 0x4059028 -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_CNTL_epvf 0x4059428 -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_CNTL_epvf 0x4059828 -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_CNTL_epvf 0x4059C28 -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_CNTL_epvf 0x405A028 -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_CNTL_epvf 0x405A428 -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_CNTL_epvf 0x405A828 -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_CNTL_epvf 0x405AC28 -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_CNTL_epvf 0x405B028 -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_CNTL_epvf 0x405B428 -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_CNTL_epvf 0x405B828 -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_CNTL_epvf 0x405BC28 -#define mmnbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4058029 -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4058029 -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4058429 -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4058829 -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4058C29 -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4059029 -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4059429 -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4059829 -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x4059C29 -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405A029 -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405A429 -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405A829 -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405AC29 -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405B029 -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405B429 -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405B829 -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x405BC29 -#define mmnbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405802A -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405802A -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405842A -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405882A -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x4058C2A -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405902A -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405942A -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405982A -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x4059C2A -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405A02A -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405A42A -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405A82A -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405AC2A -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405B02A -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405B42A -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405B82A -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x405BC2A -#define mmnbif_gpu_MSI_MSG_DATA_64_epvf 0x405802B -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405802B -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405842B -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405882B -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_DATA_64_epvf 0x4058C2B -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405902B -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405942B -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405982B -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_DATA_64_epvf 0x4059C2B -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405A02B -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405A42B -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405A82B -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405AC2B -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405B02B -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405B42B -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405B82B -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_DATA_64_epvf 0x405BC2B -#define mmnbif_gpu_MSI_MSG_DATA_epvf 0x405802A -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_DATA_epvf 0x405802A -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_DATA_epvf 0x405842A -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_DATA_epvf 0x405882A -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_DATA_epvf 0x4058C2A -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_DATA_epvf 0x405902A -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_DATA_epvf 0x405942A -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_DATA_epvf 0x405982A -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_DATA_epvf 0x4059C2A -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_DATA_epvf 0x405A02A -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_DATA_epvf 0x405A42A -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_DATA_epvf 0x405A82A -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_DATA_epvf 0x405AC2A -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_DATA_epvf 0x405B02A -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_DATA_epvf 0x405B42A -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_DATA_epvf 0x405B82A -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_DATA_epvf 0x405BC2A -#define mmnbif_gpu_MSI_MASK_epvf 0x405802B -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_MASK_epvf 0x405802B -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_MASK_epvf 0x405842B -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_MASK_epvf 0x405882B -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_MASK_epvf 0x4058C2B -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_MASK_epvf 0x405902B -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_MASK_epvf 0x405942B -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_MASK_epvf 0x405982B -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_MASK_epvf 0x4059C2B -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_MASK_epvf 0x405A02B -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_MASK_epvf 0x405A42B -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_MASK_epvf 0x405A82B -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_MASK_epvf 0x405AC2B -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_MASK_epvf 0x405B02B -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_MASK_epvf 0x405B42B -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_MASK_epvf 0x405B82B -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_MASK_epvf 0x405BC2B -#define mmnbif_gpu_MSI_PENDING_epvf 0x405802C -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_PENDING_epvf 0x405802C -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_PENDING_epvf 0x405842C -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_PENDING_epvf 0x405882C -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_PENDING_epvf 0x4058C2C -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_PENDING_epvf 0x405902C -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_PENDING_epvf 0x405942C -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_PENDING_epvf 0x405982C -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_PENDING_epvf 0x4059C2C -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_PENDING_epvf 0x405A02C -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_PENDING_epvf 0x405A42C -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_PENDING_epvf 0x405A82C -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_PENDING_epvf 0x405AC2C -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_PENDING_epvf 0x405B02C -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_PENDING_epvf 0x405B42C -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_PENDING_epvf 0x405B82C -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_PENDING_epvf 0x405BC2C -#define mmnbif_gpu_MSI_MASK_64_epvf 0x405802C -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_MASK_64_epvf 0x405802C -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_MASK_64_epvf 0x405842C -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_MASK_64_epvf 0x405882C -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_MASK_64_epvf 0x4058C2C -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_MASK_64_epvf 0x405902C -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_MASK_64_epvf 0x405942C -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_MASK_64_epvf 0x405982C -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_MASK_64_epvf 0x4059C2C -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_MASK_64_epvf 0x405A02C -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_MASK_64_epvf 0x405A42C -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_MASK_64_epvf 0x405A82C -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_MASK_64_epvf 0x405AC2C -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_MASK_64_epvf 0x405B02C -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_MASK_64_epvf 0x405B42C -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_MASK_64_epvf 0x405B82C -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_MASK_64_epvf 0x405BC2C -#define mmnbif_gpu_MSI_PENDING_64_epvf 0x405802D -#define mmBIF_CFG_EPVF0_nbif_gpu_MSI_PENDING_64_epvf 0x405802D -#define mmBIF_CFG_EPVF1_nbif_gpu_MSI_PENDING_64_epvf 0x405842D -#define mmBIF_CFG_EPVF2_nbif_gpu_MSI_PENDING_64_epvf 0x405882D -#define mmBIF_CFG_EPVF3_nbif_gpu_MSI_PENDING_64_epvf 0x4058C2D -#define mmBIF_CFG_EPVF4_nbif_gpu_MSI_PENDING_64_epvf 0x405902D -#define mmBIF_CFG_EPVF5_nbif_gpu_MSI_PENDING_64_epvf 0x405942D -#define mmBIF_CFG_EPVF6_nbif_gpu_MSI_PENDING_64_epvf 0x405982D -#define mmBIF_CFG_EPVF7_nbif_gpu_MSI_PENDING_64_epvf 0x4059C2D -#define mmBIF_CFG_EPVF8_nbif_gpu_MSI_PENDING_64_epvf 0x405A02D -#define mmBIF_CFG_EPVF9_nbif_gpu_MSI_PENDING_64_epvf 0x405A42D -#define mmBIF_CFG_EPVF10_nbif_gpu_MSI_PENDING_64_epvf 0x405A82D -#define mmBIF_CFG_EPVF11_nbif_gpu_MSI_PENDING_64_epvf 0x405AC2D -#define mmBIF_CFG_EPVF12_nbif_gpu_MSI_PENDING_64_epvf 0x405B02D -#define mmBIF_CFG_EPVF13_nbif_gpu_MSI_PENDING_64_epvf 0x405B42D -#define mmBIF_CFG_EPVF14_nbif_gpu_MSI_PENDING_64_epvf 0x405B82D -#define mmBIF_CFG_EPVF15_nbif_gpu_MSI_PENDING_64_epvf 0x405BC2D -#define mmnbif_gpu_MSIX_CAP_LIST_epvf 0x4058030 -#define mmBIF_CFG_EPVF0_nbif_gpu_MSIX_CAP_LIST_epvf 0x4058030 -#define mmBIF_CFG_EPVF1_nbif_gpu_MSIX_CAP_LIST_epvf 0x4058430 -#define mmBIF_CFG_EPVF2_nbif_gpu_MSIX_CAP_LIST_epvf 0x4058830 -#define mmBIF_CFG_EPVF3_nbif_gpu_MSIX_CAP_LIST_epvf 0x4058C30 -#define mmBIF_CFG_EPVF4_nbif_gpu_MSIX_CAP_LIST_epvf 0x4059030 -#define mmBIF_CFG_EPVF5_nbif_gpu_MSIX_CAP_LIST_epvf 0x4059430 -#define mmBIF_CFG_EPVF6_nbif_gpu_MSIX_CAP_LIST_epvf 0x4059830 -#define mmBIF_CFG_EPVF7_nbif_gpu_MSIX_CAP_LIST_epvf 0x4059C30 -#define mmBIF_CFG_EPVF8_nbif_gpu_MSIX_CAP_LIST_epvf 0x405A030 -#define mmBIF_CFG_EPVF9_nbif_gpu_MSIX_CAP_LIST_epvf 0x405A430 -#define mmBIF_CFG_EPVF10_nbif_gpu_MSIX_CAP_LIST_epvf 0x405A830 -#define mmBIF_CFG_EPVF11_nbif_gpu_MSIX_CAP_LIST_epvf 0x405AC30 -#define mmBIF_CFG_EPVF12_nbif_gpu_MSIX_CAP_LIST_epvf 0x405B030 -#define mmBIF_CFG_EPVF13_nbif_gpu_MSIX_CAP_LIST_epvf 0x405B430 -#define mmBIF_CFG_EPVF14_nbif_gpu_MSIX_CAP_LIST_epvf 0x405B830 -#define mmBIF_CFG_EPVF15_nbif_gpu_MSIX_CAP_LIST_epvf 0x405BC30 -#define mmnbif_gpu_MSIX_MSG_CNTL_epvf 0x4058030 -#define mmBIF_CFG_EPVF0_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4058030 -#define mmBIF_CFG_EPVF1_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4058430 -#define mmBIF_CFG_EPVF2_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4058830 -#define mmBIF_CFG_EPVF3_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4058C30 -#define mmBIF_CFG_EPVF4_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4059030 -#define mmBIF_CFG_EPVF5_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4059430 -#define mmBIF_CFG_EPVF6_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4059830 -#define mmBIF_CFG_EPVF7_nbif_gpu_MSIX_MSG_CNTL_epvf 0x4059C30 -#define mmBIF_CFG_EPVF8_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405A030 -#define mmBIF_CFG_EPVF9_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405A430 -#define mmBIF_CFG_EPVF10_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405A830 -#define mmBIF_CFG_EPVF11_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405AC30 -#define mmBIF_CFG_EPVF12_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405B030 -#define mmBIF_CFG_EPVF13_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405B430 -#define mmBIF_CFG_EPVF14_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405B830 -#define mmBIF_CFG_EPVF15_nbif_gpu_MSIX_MSG_CNTL_epvf 0x405BC30 -#define mmnbif_gpu_MSIX_TABLE_epvf 0x4058031 -#define mmBIF_CFG_EPVF0_nbif_gpu_MSIX_TABLE_epvf 0x4058031 -#define mmBIF_CFG_EPVF1_nbif_gpu_MSIX_TABLE_epvf 0x4058431 -#define mmBIF_CFG_EPVF2_nbif_gpu_MSIX_TABLE_epvf 0x4058831 -#define mmBIF_CFG_EPVF3_nbif_gpu_MSIX_TABLE_epvf 0x4058C31 -#define mmBIF_CFG_EPVF4_nbif_gpu_MSIX_TABLE_epvf 0x4059031 -#define mmBIF_CFG_EPVF5_nbif_gpu_MSIX_TABLE_epvf 0x4059431 -#define mmBIF_CFG_EPVF6_nbif_gpu_MSIX_TABLE_epvf 0x4059831 -#define mmBIF_CFG_EPVF7_nbif_gpu_MSIX_TABLE_epvf 0x4059C31 -#define mmBIF_CFG_EPVF8_nbif_gpu_MSIX_TABLE_epvf 0x405A031 -#define mmBIF_CFG_EPVF9_nbif_gpu_MSIX_TABLE_epvf 0x405A431 -#define mmBIF_CFG_EPVF10_nbif_gpu_MSIX_TABLE_epvf 0x405A831 -#define mmBIF_CFG_EPVF11_nbif_gpu_MSIX_TABLE_epvf 0x405AC31 -#define mmBIF_CFG_EPVF12_nbif_gpu_MSIX_TABLE_epvf 0x405B031 -#define mmBIF_CFG_EPVF13_nbif_gpu_MSIX_TABLE_epvf 0x405B431 -#define mmBIF_CFG_EPVF14_nbif_gpu_MSIX_TABLE_epvf 0x405B831 -#define mmBIF_CFG_EPVF15_nbif_gpu_MSIX_TABLE_epvf 0x405BC31 -#define mmnbif_gpu_MSIX_PBA_epvf 0x4058032 -#define mmBIF_CFG_EPVF0_nbif_gpu_MSIX_PBA_epvf 0x4058032 -#define mmBIF_CFG_EPVF1_nbif_gpu_MSIX_PBA_epvf 0x4058432 -#define mmBIF_CFG_EPVF2_nbif_gpu_MSIX_PBA_epvf 0x4058832 -#define mmBIF_CFG_EPVF3_nbif_gpu_MSIX_PBA_epvf 0x4058C32 -#define mmBIF_CFG_EPVF4_nbif_gpu_MSIX_PBA_epvf 0x4059032 -#define mmBIF_CFG_EPVF5_nbif_gpu_MSIX_PBA_epvf 0x4059432 -#define mmBIF_CFG_EPVF6_nbif_gpu_MSIX_PBA_epvf 0x4059832 -#define mmBIF_CFG_EPVF7_nbif_gpu_MSIX_PBA_epvf 0x4059C32 -#define mmBIF_CFG_EPVF8_nbif_gpu_MSIX_PBA_epvf 0x405A032 -#define mmBIF_CFG_EPVF9_nbif_gpu_MSIX_PBA_epvf 0x405A432 -#define mmBIF_CFG_EPVF10_nbif_gpu_MSIX_PBA_epvf 0x405A832 -#define mmBIF_CFG_EPVF11_nbif_gpu_MSIX_PBA_epvf 0x405AC32 -#define mmBIF_CFG_EPVF12_nbif_gpu_MSIX_PBA_epvf 0x405B032 -#define mmBIF_CFG_EPVF13_nbif_gpu_MSIX_PBA_epvf 0x405B432 -#define mmBIF_CFG_EPVF14_nbif_gpu_MSIX_PBA_epvf 0x405B832 -#define mmBIF_CFG_EPVF15_nbif_gpu_MSIX_PBA_epvf 0x405BC32 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4058040 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4058040 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4058440 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4058840 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4058C40 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4059040 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4059440 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4059840 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x4059C40 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405A040 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405A440 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405A840 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405AC40 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405B040 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405B440 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405B840 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x405BC40 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4058041 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4058041 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4058441 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4058841 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4058C41 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4059041 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4059441 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4059841 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x4059C41 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405A041 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405A441 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405A841 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405AC41 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405B041 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405B441 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405B841 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x405BC41 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4058042 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4058042 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4058442 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4058842 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4058C42 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4059042 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4059442 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4059842 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x4059C42 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405A042 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405A442 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405A842 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405AC42 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405B042 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405B442 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405B842 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x405BC42 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4058043 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4058043 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4058443 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4058843 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4058C43 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4059043 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4059443 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4059843 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x4059C43 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405A043 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405A443 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405A843 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405AC43 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405B043 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405B443 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405B843 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x405BC43 -#define mmnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4058054 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4058054 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4058454 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4058854 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4058C54 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4059054 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4059454 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4059854 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x4059C54 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405A054 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405A454 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405A854 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405AC54 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405B054 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405B454 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405B854 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x405BC54 -#define mmnbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4058055 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4058055 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4058455 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4058855 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4058C55 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4059055 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4059455 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4059855 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x4059C55 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405A055 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405A455 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405A855 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405AC55 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405B055 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405B455 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405B855 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x405BC55 -#define mmnbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4058056 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4058056 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4058456 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4058856 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4058C56 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4059056 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4059456 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4059856 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x4059C56 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405A056 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405A456 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405A856 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405AC56 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405B056 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405B456 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405B856 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x405BC56 -#define mmnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4058057 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4058057 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4058457 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4058857 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4058C57 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4059057 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4059457 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4059857 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x4059C57 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405A057 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405A457 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405A857 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405AC57 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405B057 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405B457 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405B857 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x405BC57 -#define mmnbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4058058 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4058058 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4058458 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4058858 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4058C58 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4059058 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4059458 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4059858 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x4059C58 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405A058 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405A458 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405A858 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405AC58 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405B058 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405B458 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405B858 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x405BC58 -#define mmnbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4058059 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4058059 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4058459 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4058859 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4058C59 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4059059 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4059459 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4059859 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x4059C59 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405A059 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405A459 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405A859 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405AC59 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405B059 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405B459 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405B859 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x405BC59 -#define mmnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405805A -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405805A -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405845A -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405885A -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x4058C5A -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405905A -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405945A -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405985A -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x4059C5A -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405A05A -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405A45A -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405A85A -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405AC5A -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405B05A -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405B45A -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405B85A -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x405BC5A -#define mmnbif_gpu_PCIE_HDR_LOG0_epvf 0x405805B -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405805B -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405845B -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405885B -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG0_epvf 0x4058C5B -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405905B -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405945B -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405985B -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG0_epvf 0x4059C5B -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405A05B -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405A45B -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405A85B -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405AC5B -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405B05B -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405B45B -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405B85B -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG0_epvf 0x405BC5B -#define mmnbif_gpu_PCIE_HDR_LOG1_epvf 0x405805C -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405805C -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405845C -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405885C -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG1_epvf 0x4058C5C -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405905C -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405945C -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405985C -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG1_epvf 0x4059C5C -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405A05C -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405A45C -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405A85C -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405AC5C -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405B05C -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405B45C -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405B85C -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG1_epvf 0x405BC5C -#define mmnbif_gpu_PCIE_HDR_LOG2_epvf 0x405805D -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405805D -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405845D -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405885D -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG2_epvf 0x4058C5D -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405905D -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405945D -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405985D -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG2_epvf 0x4059C5D -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405A05D -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405A45D -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405A85D -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405AC5D -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405B05D -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405B45D -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405B85D -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG2_epvf 0x405BC5D -#define mmnbif_gpu_PCIE_HDR_LOG3_epvf 0x405805E -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405805E -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405845E -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405885E -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG3_epvf 0x4058C5E -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405905E -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405945E -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405985E -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG3_epvf 0x4059C5E -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405A05E -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405A45E -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405A85E -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405AC5E -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405B05E -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405B45E -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405B85E -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG3_epvf 0x405BC5E -#define mmnbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405805F -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405805F -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405845F -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405885F -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x4058C5F -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405905F -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405945F -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405985F -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x4059C5F -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405A05F -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405A45F -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405A85F -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405AC5F -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405B05F -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405B45F -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405B85F -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x405BC5F -#define mmnbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4058060 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4058060 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4058460 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4058860 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4058C60 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4059060 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4059460 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4059860 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x4059C60 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405A060 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405A460 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405A860 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405AC60 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405B060 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405B460 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405B860 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x405BC60 -#define mmnbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4058061 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4058061 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4058461 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4058861 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4058C61 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4059061 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4059461 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4059861 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x4059C61 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405A061 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405A461 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405A861 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405AC61 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405B061 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405B461 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405B861 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x405BC61 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4058062 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4058062 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4058462 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4058862 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4058C62 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4059062 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4059462 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4059862 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x4059C62 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405A062 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405A462 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405A862 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405AC62 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405B062 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405B462 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405B862 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x405BC62 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4058063 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4058063 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4058463 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4058863 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4058C63 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4059063 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4059463 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4059863 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x4059C63 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405A063 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405A463 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405A863 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405AC63 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405B063 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405B463 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405B863 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x405BC63 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4058064 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4058064 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4058464 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4058864 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4058C64 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4059064 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4059464 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4059864 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x4059C64 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405A064 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405A464 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405A864 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405AC64 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405B064 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405B464 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405B864 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x405BC64 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4058065 -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4058065 -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4058465 -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4058865 -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4058C65 -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4059065 -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4059465 -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4059865 -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x4059C65 -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405A065 -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405A465 -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405A865 -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405AC65 -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405B065 -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405B465 -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405B865 -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x405BC65 -#define mmnbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x40580AC -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x40580AC -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x40584AC -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x40588AC -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x4058CAC -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x40590AC -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x40594AC -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x40598AC -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x4059CAC -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405A0AC -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405A4AC -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405A8AC -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405ACAC -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405B0AC -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405B4AC -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405B8AC -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x405BCAC -#define mmnbif_gpu_PCIE_ATS_CAP_epvf 0x40580AD -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_CAP_epvf 0x40580AD -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_CAP_epvf 0x40584AD -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_CAP_epvf 0x40588AD -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_CAP_epvf 0x4058CAD -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_CAP_epvf 0x40590AD -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_CAP_epvf 0x40594AD -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_CAP_epvf 0x40598AD -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_CAP_epvf 0x4059CAD -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_CAP_epvf 0x405A0AD -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_CAP_epvf 0x405A4AD -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_CAP_epvf 0x405A8AD -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_CAP_epvf 0x405ACAD -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_CAP_epvf 0x405B0AD -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_CAP_epvf 0x405B4AD -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_CAP_epvf 0x405B8AD -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_CAP_epvf 0x405BCAD -#define mmnbif_gpu_PCIE_ATS_CNTL_epvf 0x40580AD -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_CNTL_epvf 0x40580AD -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_CNTL_epvf 0x40584AD -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_CNTL_epvf 0x40588AD -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_CNTL_epvf 0x4058CAD -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_CNTL_epvf 0x40590AD -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_CNTL_epvf 0x40594AD -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_CNTL_epvf 0x40598AD -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_CNTL_epvf 0x4059CAD -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405A0AD -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405A4AD -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405A8AD -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405ACAD -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405B0AD -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405B4AD -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405B8AD -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_CNTL_epvf 0x405BCAD -#define mmnbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x40580CA -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x40580CA -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x40584CA -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x40588CA -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x4058CCA -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x40590CA -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x40594CA -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x40598CA -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x4059CCA -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405A0CA -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405A4CA -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405A8CA -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405ACCA -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405B0CA -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405B4CA -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405B8CA -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x405BCCA -#define mmnbif_gpu_PCIE_ARI_CAP_epvf 0x40580CB -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_CAP_epvf 0x40580CB -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_CAP_epvf 0x40584CB -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_CAP_epvf 0x40588CB -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_CAP_epvf 0x4058CCB -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_CAP_epvf 0x40590CB -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_CAP_epvf 0x40594CB -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_CAP_epvf 0x40598CB -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_CAP_epvf 0x4059CCB -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_CAP_epvf 0x405A0CB -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_CAP_epvf 0x405A4CB -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_CAP_epvf 0x405A8CB -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_CAP_epvf 0x405ACCB -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_CAP_epvf 0x405B0CB -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_CAP_epvf 0x405B4CB -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_CAP_epvf 0x405B8CB -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_CAP_epvf 0x405BCCB -#define mmnbif_gpu_PCIE_ARI_CNTL_epvf 0x40580CB -#define mmBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_CNTL_epvf 0x40580CB -#define mmBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_CNTL_epvf 0x40584CB -#define mmBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_CNTL_epvf 0x40588CB -#define mmBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_CNTL_epvf 0x4058CCB -#define mmBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_CNTL_epvf 0x40590CB -#define mmBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_CNTL_epvf 0x40594CB -#define mmBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_CNTL_epvf 0x40598CB -#define mmBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_CNTL_epvf 0x4059CCB -#define mmBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405A0CB -#define mmBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405A4CB -#define mmBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405A8CB -#define mmBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405ACCB -#define mmBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405B0CB -#define mmBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405B4CB -#define mmBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405B8CB -#define mmBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_CNTL_epvf 0x405BCCB -#define pcinbif_gpu_VENDOR_ID_epvf 0x0000 -#define cfgnbif_gpu_VENDOR_ID_epvf 0x0000 -#define pciBIF_CFG_EPVF0_nbif_gpu_VENDOR_ID_epvf 0x0000 -#define cfgBIF_CFG_EPVF0_nbif_gpu_VENDOR_ID_epvf 0x0000 -#define pciBIF_CFG_EPVF1_nbif_gpu_VENDOR_ID_epvf_alt_1 0x0000 -#define cfgBIF_CFG_EPVF1_nbif_gpu_VENDOR_ID_epvf_alt_1 0x0000 -#define pciBIF_CFG_EPVF2_nbif_gpu_VENDOR_ID_epvf_alt_2 0x0000 -#define cfgBIF_CFG_EPVF2_nbif_gpu_VENDOR_ID_epvf_alt_2 0x0000 -#define pciBIF_CFG_EPVF3_nbif_gpu_VENDOR_ID_epvf_alt_3 0x0000 -#define cfgBIF_CFG_EPVF3_nbif_gpu_VENDOR_ID_epvf_alt_3 0x0000 -#define pciBIF_CFG_EPVF4_nbif_gpu_VENDOR_ID_epvf_alt_4 0x0000 -#define cfgBIF_CFG_EPVF4_nbif_gpu_VENDOR_ID_epvf_alt_4 0x0000 -#define pciBIF_CFG_EPVF5_nbif_gpu_VENDOR_ID_epvf_alt_5 0x0000 -#define cfgBIF_CFG_EPVF5_nbif_gpu_VENDOR_ID_epvf_alt_5 0x0000 -#define pciBIF_CFG_EPVF6_nbif_gpu_VENDOR_ID_epvf_alt_6 0x0000 -#define cfgBIF_CFG_EPVF6_nbif_gpu_VENDOR_ID_epvf_alt_6 0x0000 -#define pciBIF_CFG_EPVF7_nbif_gpu_VENDOR_ID_epvf_alt_7 0x0000 -#define cfgBIF_CFG_EPVF7_nbif_gpu_VENDOR_ID_epvf_alt_7 0x0000 -#define pciBIF_CFG_EPVF8_nbif_gpu_VENDOR_ID_epvf_alt_8 0x0000 -#define cfgBIF_CFG_EPVF8_nbif_gpu_VENDOR_ID_epvf_alt_8 0x0000 -#define pciBIF_CFG_EPVF9_nbif_gpu_VENDOR_ID_epvf_alt_9 0x0000 -#define cfgBIF_CFG_EPVF9_nbif_gpu_VENDOR_ID_epvf_alt_9 0x0000 -#define pciBIF_CFG_EPVF10_nbif_gpu_VENDOR_ID_epvf_alt_10 0x0000 -#define cfgBIF_CFG_EPVF10_nbif_gpu_VENDOR_ID_epvf_alt_10 0x0000 -#define pciBIF_CFG_EPVF11_nbif_gpu_VENDOR_ID_epvf_alt_11 0x0000 -#define cfgBIF_CFG_EPVF11_nbif_gpu_VENDOR_ID_epvf_alt_11 0x0000 -#define pciBIF_CFG_EPVF12_nbif_gpu_VENDOR_ID_epvf_alt_12 0x0000 -#define cfgBIF_CFG_EPVF12_nbif_gpu_VENDOR_ID_epvf_alt_12 0x0000 -#define pciBIF_CFG_EPVF13_nbif_gpu_VENDOR_ID_epvf_alt_13 0x0000 -#define cfgBIF_CFG_EPVF13_nbif_gpu_VENDOR_ID_epvf_alt_13 0x0000 -#define pciBIF_CFG_EPVF14_nbif_gpu_VENDOR_ID_epvf_alt_14 0x0000 -#define cfgBIF_CFG_EPVF14_nbif_gpu_VENDOR_ID_epvf_alt_14 0x0000 -#define pciBIF_CFG_EPVF15_nbif_gpu_VENDOR_ID_epvf_alt_15 0x0000 -#define cfgBIF_CFG_EPVF15_nbif_gpu_VENDOR_ID_epvf_alt_15 0x0000 -#define pcinbif_gpu_DEVICE_ID_epvf 0x0000 -#define cfgnbif_gpu_DEVICE_ID_epvf 0x0000 -#define pciBIF_CFG_EPVF0_nbif_gpu_DEVICE_ID_epvf 0x0000 -#define cfgBIF_CFG_EPVF0_nbif_gpu_DEVICE_ID_epvf 0x0000 -#define pciBIF_CFG_EPVF1_nbif_gpu_DEVICE_ID_epvf_alt_1 0x0000 -#define cfgBIF_CFG_EPVF1_nbif_gpu_DEVICE_ID_epvf_alt_1 0x0000 -#define pciBIF_CFG_EPVF2_nbif_gpu_DEVICE_ID_epvf_alt_2 0x0000 -#define cfgBIF_CFG_EPVF2_nbif_gpu_DEVICE_ID_epvf_alt_2 0x0000 -#define pciBIF_CFG_EPVF3_nbif_gpu_DEVICE_ID_epvf_alt_3 0x0000 -#define cfgBIF_CFG_EPVF3_nbif_gpu_DEVICE_ID_epvf_alt_3 0x0000 -#define pciBIF_CFG_EPVF4_nbif_gpu_DEVICE_ID_epvf_alt_4 0x0000 -#define cfgBIF_CFG_EPVF4_nbif_gpu_DEVICE_ID_epvf_alt_4 0x0000 -#define pciBIF_CFG_EPVF5_nbif_gpu_DEVICE_ID_epvf_alt_5 0x0000 -#define cfgBIF_CFG_EPVF5_nbif_gpu_DEVICE_ID_epvf_alt_5 0x0000 -#define pciBIF_CFG_EPVF6_nbif_gpu_DEVICE_ID_epvf_alt_6 0x0000 -#define cfgBIF_CFG_EPVF6_nbif_gpu_DEVICE_ID_epvf_alt_6 0x0000 -#define pciBIF_CFG_EPVF7_nbif_gpu_DEVICE_ID_epvf_alt_7 0x0000 -#define cfgBIF_CFG_EPVF7_nbif_gpu_DEVICE_ID_epvf_alt_7 0x0000 -#define pciBIF_CFG_EPVF8_nbif_gpu_DEVICE_ID_epvf_alt_8 0x0000 -#define cfgBIF_CFG_EPVF8_nbif_gpu_DEVICE_ID_epvf_alt_8 0x0000 -#define pciBIF_CFG_EPVF9_nbif_gpu_DEVICE_ID_epvf_alt_9 0x0000 -#define cfgBIF_CFG_EPVF9_nbif_gpu_DEVICE_ID_epvf_alt_9 0x0000 -#define pciBIF_CFG_EPVF10_nbif_gpu_DEVICE_ID_epvf_alt_10 0x0000 -#define cfgBIF_CFG_EPVF10_nbif_gpu_DEVICE_ID_epvf_alt_10 0x0000 -#define pciBIF_CFG_EPVF11_nbif_gpu_DEVICE_ID_epvf_alt_11 0x0000 -#define cfgBIF_CFG_EPVF11_nbif_gpu_DEVICE_ID_epvf_alt_11 0x0000 -#define pciBIF_CFG_EPVF12_nbif_gpu_DEVICE_ID_epvf_alt_12 0x0000 -#define cfgBIF_CFG_EPVF12_nbif_gpu_DEVICE_ID_epvf_alt_12 0x0000 -#define pciBIF_CFG_EPVF13_nbif_gpu_DEVICE_ID_epvf_alt_13 0x0000 -#define cfgBIF_CFG_EPVF13_nbif_gpu_DEVICE_ID_epvf_alt_13 0x0000 -#define pciBIF_CFG_EPVF14_nbif_gpu_DEVICE_ID_epvf_alt_14 0x0000 -#define cfgBIF_CFG_EPVF14_nbif_gpu_DEVICE_ID_epvf_alt_14 0x0000 -#define pciBIF_CFG_EPVF15_nbif_gpu_DEVICE_ID_epvf_alt_15 0x0000 -#define cfgBIF_CFG_EPVF15_nbif_gpu_DEVICE_ID_epvf_alt_15 0x0000 -#define pcinbif_gpu_COMMAND_epvf 0x0001 -#define cfgnbif_gpu_COMMAND_epvf 0x0001 -#define pciBIF_CFG_EPVF0_nbif_gpu_COMMAND_epvf 0x0001 -#define cfgBIF_CFG_EPVF0_nbif_gpu_COMMAND_epvf 0x0001 -#define pciBIF_CFG_EPVF1_nbif_gpu_COMMAND_epvf_alt_1 0x0001 -#define cfgBIF_CFG_EPVF1_nbif_gpu_COMMAND_epvf_alt_1 0x0001 -#define pciBIF_CFG_EPVF2_nbif_gpu_COMMAND_epvf_alt_2 0x0001 -#define cfgBIF_CFG_EPVF2_nbif_gpu_COMMAND_epvf_alt_2 0x0001 -#define pciBIF_CFG_EPVF3_nbif_gpu_COMMAND_epvf_alt_3 0x0001 -#define cfgBIF_CFG_EPVF3_nbif_gpu_COMMAND_epvf_alt_3 0x0001 -#define pciBIF_CFG_EPVF4_nbif_gpu_COMMAND_epvf_alt_4 0x0001 -#define cfgBIF_CFG_EPVF4_nbif_gpu_COMMAND_epvf_alt_4 0x0001 -#define pciBIF_CFG_EPVF5_nbif_gpu_COMMAND_epvf_alt_5 0x0001 -#define cfgBIF_CFG_EPVF5_nbif_gpu_COMMAND_epvf_alt_5 0x0001 -#define pciBIF_CFG_EPVF6_nbif_gpu_COMMAND_epvf_alt_6 0x0001 -#define cfgBIF_CFG_EPVF6_nbif_gpu_COMMAND_epvf_alt_6 0x0001 -#define pciBIF_CFG_EPVF7_nbif_gpu_COMMAND_epvf_alt_7 0x0001 -#define cfgBIF_CFG_EPVF7_nbif_gpu_COMMAND_epvf_alt_7 0x0001 -#define pciBIF_CFG_EPVF8_nbif_gpu_COMMAND_epvf_alt_8 0x0001 -#define cfgBIF_CFG_EPVF8_nbif_gpu_COMMAND_epvf_alt_8 0x0001 -#define pciBIF_CFG_EPVF9_nbif_gpu_COMMAND_epvf_alt_9 0x0001 -#define cfgBIF_CFG_EPVF9_nbif_gpu_COMMAND_epvf_alt_9 0x0001 -#define pciBIF_CFG_EPVF10_nbif_gpu_COMMAND_epvf_alt_10 0x0001 -#define cfgBIF_CFG_EPVF10_nbif_gpu_COMMAND_epvf_alt_10 0x0001 -#define pciBIF_CFG_EPVF11_nbif_gpu_COMMAND_epvf_alt_11 0x0001 -#define cfgBIF_CFG_EPVF11_nbif_gpu_COMMAND_epvf_alt_11 0x0001 -#define pciBIF_CFG_EPVF12_nbif_gpu_COMMAND_epvf_alt_12 0x0001 -#define cfgBIF_CFG_EPVF12_nbif_gpu_COMMAND_epvf_alt_12 0x0001 -#define pciBIF_CFG_EPVF13_nbif_gpu_COMMAND_epvf_alt_13 0x0001 -#define cfgBIF_CFG_EPVF13_nbif_gpu_COMMAND_epvf_alt_13 0x0001 -#define pciBIF_CFG_EPVF14_nbif_gpu_COMMAND_epvf_alt_14 0x0001 -#define cfgBIF_CFG_EPVF14_nbif_gpu_COMMAND_epvf_alt_14 0x0001 -#define pciBIF_CFG_EPVF15_nbif_gpu_COMMAND_epvf_alt_15 0x0001 -#define cfgBIF_CFG_EPVF15_nbif_gpu_COMMAND_epvf_alt_15 0x0001 -#define pcinbif_gpu_STATUS_epvf 0x0001 -#define cfgnbif_gpu_STATUS_epvf 0x0001 -#define pciBIF_CFG_EPVF0_nbif_gpu_STATUS_epvf 0x0001 -#define cfgBIF_CFG_EPVF0_nbif_gpu_STATUS_epvf 0x0001 -#define pciBIF_CFG_EPVF1_nbif_gpu_STATUS_epvf_alt_1 0x0001 -#define cfgBIF_CFG_EPVF1_nbif_gpu_STATUS_epvf_alt_1 0x0001 -#define pciBIF_CFG_EPVF2_nbif_gpu_STATUS_epvf_alt_2 0x0001 -#define cfgBIF_CFG_EPVF2_nbif_gpu_STATUS_epvf_alt_2 0x0001 -#define pciBIF_CFG_EPVF3_nbif_gpu_STATUS_epvf_alt_3 0x0001 -#define cfgBIF_CFG_EPVF3_nbif_gpu_STATUS_epvf_alt_3 0x0001 -#define pciBIF_CFG_EPVF4_nbif_gpu_STATUS_epvf_alt_4 0x0001 -#define cfgBIF_CFG_EPVF4_nbif_gpu_STATUS_epvf_alt_4 0x0001 -#define pciBIF_CFG_EPVF5_nbif_gpu_STATUS_epvf_alt_5 0x0001 -#define cfgBIF_CFG_EPVF5_nbif_gpu_STATUS_epvf_alt_5 0x0001 -#define pciBIF_CFG_EPVF6_nbif_gpu_STATUS_epvf_alt_6 0x0001 -#define cfgBIF_CFG_EPVF6_nbif_gpu_STATUS_epvf_alt_6 0x0001 -#define pciBIF_CFG_EPVF7_nbif_gpu_STATUS_epvf_alt_7 0x0001 -#define cfgBIF_CFG_EPVF7_nbif_gpu_STATUS_epvf_alt_7 0x0001 -#define pciBIF_CFG_EPVF8_nbif_gpu_STATUS_epvf_alt_8 0x0001 -#define cfgBIF_CFG_EPVF8_nbif_gpu_STATUS_epvf_alt_8 0x0001 -#define pciBIF_CFG_EPVF9_nbif_gpu_STATUS_epvf_alt_9 0x0001 -#define cfgBIF_CFG_EPVF9_nbif_gpu_STATUS_epvf_alt_9 0x0001 -#define pciBIF_CFG_EPVF10_nbif_gpu_STATUS_epvf_alt_10 0x0001 -#define cfgBIF_CFG_EPVF10_nbif_gpu_STATUS_epvf_alt_10 0x0001 -#define pciBIF_CFG_EPVF11_nbif_gpu_STATUS_epvf_alt_11 0x0001 -#define cfgBIF_CFG_EPVF11_nbif_gpu_STATUS_epvf_alt_11 0x0001 -#define pciBIF_CFG_EPVF12_nbif_gpu_STATUS_epvf_alt_12 0x0001 -#define cfgBIF_CFG_EPVF12_nbif_gpu_STATUS_epvf_alt_12 0x0001 -#define pciBIF_CFG_EPVF13_nbif_gpu_STATUS_epvf_alt_13 0x0001 -#define cfgBIF_CFG_EPVF13_nbif_gpu_STATUS_epvf_alt_13 0x0001 -#define pciBIF_CFG_EPVF14_nbif_gpu_STATUS_epvf_alt_14 0x0001 -#define cfgBIF_CFG_EPVF14_nbif_gpu_STATUS_epvf_alt_14 0x0001 -#define pciBIF_CFG_EPVF15_nbif_gpu_STATUS_epvf_alt_15 0x0001 -#define cfgBIF_CFG_EPVF15_nbif_gpu_STATUS_epvf_alt_15 0x0001 -#define pcinbif_gpu_REVISION_ID_epvf 0x0002 -#define cfgnbif_gpu_REVISION_ID_epvf 0x0002 -#define pciBIF_CFG_EPVF0_nbif_gpu_REVISION_ID_epvf 0x0002 -#define cfgBIF_CFG_EPVF0_nbif_gpu_REVISION_ID_epvf 0x0002 -#define pciBIF_CFG_EPVF1_nbif_gpu_REVISION_ID_epvf_alt_1 0x0002 -#define cfgBIF_CFG_EPVF1_nbif_gpu_REVISION_ID_epvf_alt_1 0x0002 -#define pciBIF_CFG_EPVF2_nbif_gpu_REVISION_ID_epvf_alt_2 0x0002 -#define cfgBIF_CFG_EPVF2_nbif_gpu_REVISION_ID_epvf_alt_2 0x0002 -#define pciBIF_CFG_EPVF3_nbif_gpu_REVISION_ID_epvf_alt_3 0x0002 -#define cfgBIF_CFG_EPVF3_nbif_gpu_REVISION_ID_epvf_alt_3 0x0002 -#define pciBIF_CFG_EPVF4_nbif_gpu_REVISION_ID_epvf_alt_4 0x0002 -#define cfgBIF_CFG_EPVF4_nbif_gpu_REVISION_ID_epvf_alt_4 0x0002 -#define pciBIF_CFG_EPVF5_nbif_gpu_REVISION_ID_epvf_alt_5 0x0002 -#define cfgBIF_CFG_EPVF5_nbif_gpu_REVISION_ID_epvf_alt_5 0x0002 -#define pciBIF_CFG_EPVF6_nbif_gpu_REVISION_ID_epvf_alt_6 0x0002 -#define cfgBIF_CFG_EPVF6_nbif_gpu_REVISION_ID_epvf_alt_6 0x0002 -#define pciBIF_CFG_EPVF7_nbif_gpu_REVISION_ID_epvf_alt_7 0x0002 -#define cfgBIF_CFG_EPVF7_nbif_gpu_REVISION_ID_epvf_alt_7 0x0002 -#define pciBIF_CFG_EPVF8_nbif_gpu_REVISION_ID_epvf_alt_8 0x0002 -#define cfgBIF_CFG_EPVF8_nbif_gpu_REVISION_ID_epvf_alt_8 0x0002 -#define pciBIF_CFG_EPVF9_nbif_gpu_REVISION_ID_epvf_alt_9 0x0002 -#define cfgBIF_CFG_EPVF9_nbif_gpu_REVISION_ID_epvf_alt_9 0x0002 -#define pciBIF_CFG_EPVF10_nbif_gpu_REVISION_ID_epvf_alt_10 0x0002 -#define cfgBIF_CFG_EPVF10_nbif_gpu_REVISION_ID_epvf_alt_10 0x0002 -#define pciBIF_CFG_EPVF11_nbif_gpu_REVISION_ID_epvf_alt_11 0x0002 -#define cfgBIF_CFG_EPVF11_nbif_gpu_REVISION_ID_epvf_alt_11 0x0002 -#define pciBIF_CFG_EPVF12_nbif_gpu_REVISION_ID_epvf_alt_12 0x0002 -#define cfgBIF_CFG_EPVF12_nbif_gpu_REVISION_ID_epvf_alt_12 0x0002 -#define pciBIF_CFG_EPVF13_nbif_gpu_REVISION_ID_epvf_alt_13 0x0002 -#define cfgBIF_CFG_EPVF13_nbif_gpu_REVISION_ID_epvf_alt_13 0x0002 -#define pciBIF_CFG_EPVF14_nbif_gpu_REVISION_ID_epvf_alt_14 0x0002 -#define cfgBIF_CFG_EPVF14_nbif_gpu_REVISION_ID_epvf_alt_14 0x0002 -#define pciBIF_CFG_EPVF15_nbif_gpu_REVISION_ID_epvf_alt_15 0x0002 -#define cfgBIF_CFG_EPVF15_nbif_gpu_REVISION_ID_epvf_alt_15 0x0002 -#define pcinbif_gpu_PROG_INTERFACE_epvf 0x0002 -#define cfgnbif_gpu_PROG_INTERFACE_epvf 0x0002 -#define pciBIF_CFG_EPVF0_nbif_gpu_PROG_INTERFACE_epvf 0x0002 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PROG_INTERFACE_epvf 0x0002 -#define pciBIF_CFG_EPVF1_nbif_gpu_PROG_INTERFACE_epvf_alt_1 0x0002 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PROG_INTERFACE_epvf_alt_1 0x0002 -#define pciBIF_CFG_EPVF2_nbif_gpu_PROG_INTERFACE_epvf_alt_2 0x0002 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PROG_INTERFACE_epvf_alt_2 0x0002 -#define pciBIF_CFG_EPVF3_nbif_gpu_PROG_INTERFACE_epvf_alt_3 0x0002 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PROG_INTERFACE_epvf_alt_3 0x0002 -#define pciBIF_CFG_EPVF4_nbif_gpu_PROG_INTERFACE_epvf_alt_4 0x0002 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PROG_INTERFACE_epvf_alt_4 0x0002 -#define pciBIF_CFG_EPVF5_nbif_gpu_PROG_INTERFACE_epvf_alt_5 0x0002 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PROG_INTERFACE_epvf_alt_5 0x0002 -#define pciBIF_CFG_EPVF6_nbif_gpu_PROG_INTERFACE_epvf_alt_6 0x0002 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PROG_INTERFACE_epvf_alt_6 0x0002 -#define pciBIF_CFG_EPVF7_nbif_gpu_PROG_INTERFACE_epvf_alt_7 0x0002 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PROG_INTERFACE_epvf_alt_7 0x0002 -#define pciBIF_CFG_EPVF8_nbif_gpu_PROG_INTERFACE_epvf_alt_8 0x0002 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PROG_INTERFACE_epvf_alt_8 0x0002 -#define pciBIF_CFG_EPVF9_nbif_gpu_PROG_INTERFACE_epvf_alt_9 0x0002 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PROG_INTERFACE_epvf_alt_9 0x0002 -#define pciBIF_CFG_EPVF10_nbif_gpu_PROG_INTERFACE_epvf_alt_10 0x0002 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PROG_INTERFACE_epvf_alt_10 0x0002 -#define pciBIF_CFG_EPVF11_nbif_gpu_PROG_INTERFACE_epvf_alt_11 0x0002 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PROG_INTERFACE_epvf_alt_11 0x0002 -#define pciBIF_CFG_EPVF12_nbif_gpu_PROG_INTERFACE_epvf_alt_12 0x0002 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PROG_INTERFACE_epvf_alt_12 0x0002 -#define pciBIF_CFG_EPVF13_nbif_gpu_PROG_INTERFACE_epvf_alt_13 0x0002 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PROG_INTERFACE_epvf_alt_13 0x0002 -#define pciBIF_CFG_EPVF14_nbif_gpu_PROG_INTERFACE_epvf_alt_14 0x0002 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PROG_INTERFACE_epvf_alt_14 0x0002 -#define pciBIF_CFG_EPVF15_nbif_gpu_PROG_INTERFACE_epvf_alt_15 0x0002 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PROG_INTERFACE_epvf_alt_15 0x0002 -#define pcinbif_gpu_SUB_CLASS_epvf 0x0002 -#define cfgnbif_gpu_SUB_CLASS_epvf 0x0002 -#define pciBIF_CFG_EPVF0_nbif_gpu_SUB_CLASS_epvf 0x0002 -#define cfgBIF_CFG_EPVF0_nbif_gpu_SUB_CLASS_epvf 0x0002 -#define pciBIF_CFG_EPVF1_nbif_gpu_SUB_CLASS_epvf_alt_1 0x0002 -#define cfgBIF_CFG_EPVF1_nbif_gpu_SUB_CLASS_epvf_alt_1 0x0002 -#define pciBIF_CFG_EPVF2_nbif_gpu_SUB_CLASS_epvf_alt_2 0x0002 -#define cfgBIF_CFG_EPVF2_nbif_gpu_SUB_CLASS_epvf_alt_2 0x0002 -#define pciBIF_CFG_EPVF3_nbif_gpu_SUB_CLASS_epvf_alt_3 0x0002 -#define cfgBIF_CFG_EPVF3_nbif_gpu_SUB_CLASS_epvf_alt_3 0x0002 -#define pciBIF_CFG_EPVF4_nbif_gpu_SUB_CLASS_epvf_alt_4 0x0002 -#define cfgBIF_CFG_EPVF4_nbif_gpu_SUB_CLASS_epvf_alt_4 0x0002 -#define pciBIF_CFG_EPVF5_nbif_gpu_SUB_CLASS_epvf_alt_5 0x0002 -#define cfgBIF_CFG_EPVF5_nbif_gpu_SUB_CLASS_epvf_alt_5 0x0002 -#define pciBIF_CFG_EPVF6_nbif_gpu_SUB_CLASS_epvf_alt_6 0x0002 -#define cfgBIF_CFG_EPVF6_nbif_gpu_SUB_CLASS_epvf_alt_6 0x0002 -#define pciBIF_CFG_EPVF7_nbif_gpu_SUB_CLASS_epvf_alt_7 0x0002 -#define cfgBIF_CFG_EPVF7_nbif_gpu_SUB_CLASS_epvf_alt_7 0x0002 -#define pciBIF_CFG_EPVF8_nbif_gpu_SUB_CLASS_epvf_alt_8 0x0002 -#define cfgBIF_CFG_EPVF8_nbif_gpu_SUB_CLASS_epvf_alt_8 0x0002 -#define pciBIF_CFG_EPVF9_nbif_gpu_SUB_CLASS_epvf_alt_9 0x0002 -#define cfgBIF_CFG_EPVF9_nbif_gpu_SUB_CLASS_epvf_alt_9 0x0002 -#define pciBIF_CFG_EPVF10_nbif_gpu_SUB_CLASS_epvf_alt_10 0x0002 -#define cfgBIF_CFG_EPVF10_nbif_gpu_SUB_CLASS_epvf_alt_10 0x0002 -#define pciBIF_CFG_EPVF11_nbif_gpu_SUB_CLASS_epvf_alt_11 0x0002 -#define cfgBIF_CFG_EPVF11_nbif_gpu_SUB_CLASS_epvf_alt_11 0x0002 -#define pciBIF_CFG_EPVF12_nbif_gpu_SUB_CLASS_epvf_alt_12 0x0002 -#define cfgBIF_CFG_EPVF12_nbif_gpu_SUB_CLASS_epvf_alt_12 0x0002 -#define pciBIF_CFG_EPVF13_nbif_gpu_SUB_CLASS_epvf_alt_13 0x0002 -#define cfgBIF_CFG_EPVF13_nbif_gpu_SUB_CLASS_epvf_alt_13 0x0002 -#define pciBIF_CFG_EPVF14_nbif_gpu_SUB_CLASS_epvf_alt_14 0x0002 -#define cfgBIF_CFG_EPVF14_nbif_gpu_SUB_CLASS_epvf_alt_14 0x0002 -#define pciBIF_CFG_EPVF15_nbif_gpu_SUB_CLASS_epvf_alt_15 0x0002 -#define cfgBIF_CFG_EPVF15_nbif_gpu_SUB_CLASS_epvf_alt_15 0x0002 -#define pcinbif_gpu_BASE_CLASS_epvf 0x0002 -#define cfgnbif_gpu_BASE_CLASS_epvf 0x0002 -#define pciBIF_CFG_EPVF0_nbif_gpu_BASE_CLASS_epvf 0x0002 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BASE_CLASS_epvf 0x0002 -#define pciBIF_CFG_EPVF1_nbif_gpu_BASE_CLASS_epvf_alt_1 0x0002 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BASE_CLASS_epvf_alt_1 0x0002 -#define pciBIF_CFG_EPVF2_nbif_gpu_BASE_CLASS_epvf_alt_2 0x0002 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BASE_CLASS_epvf_alt_2 0x0002 -#define pciBIF_CFG_EPVF3_nbif_gpu_BASE_CLASS_epvf_alt_3 0x0002 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BASE_CLASS_epvf_alt_3 0x0002 -#define pciBIF_CFG_EPVF4_nbif_gpu_BASE_CLASS_epvf_alt_4 0x0002 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BASE_CLASS_epvf_alt_4 0x0002 -#define pciBIF_CFG_EPVF5_nbif_gpu_BASE_CLASS_epvf_alt_5 0x0002 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BASE_CLASS_epvf_alt_5 0x0002 -#define pciBIF_CFG_EPVF6_nbif_gpu_BASE_CLASS_epvf_alt_6 0x0002 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BASE_CLASS_epvf_alt_6 0x0002 -#define pciBIF_CFG_EPVF7_nbif_gpu_BASE_CLASS_epvf_alt_7 0x0002 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BASE_CLASS_epvf_alt_7 0x0002 -#define pciBIF_CFG_EPVF8_nbif_gpu_BASE_CLASS_epvf_alt_8 0x0002 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BASE_CLASS_epvf_alt_8 0x0002 -#define pciBIF_CFG_EPVF9_nbif_gpu_BASE_CLASS_epvf_alt_9 0x0002 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BASE_CLASS_epvf_alt_9 0x0002 -#define pciBIF_CFG_EPVF10_nbif_gpu_BASE_CLASS_epvf_alt_10 0x0002 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BASE_CLASS_epvf_alt_10 0x0002 -#define pciBIF_CFG_EPVF11_nbif_gpu_BASE_CLASS_epvf_alt_11 0x0002 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BASE_CLASS_epvf_alt_11 0x0002 -#define pciBIF_CFG_EPVF12_nbif_gpu_BASE_CLASS_epvf_alt_12 0x0002 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BASE_CLASS_epvf_alt_12 0x0002 -#define pciBIF_CFG_EPVF13_nbif_gpu_BASE_CLASS_epvf_alt_13 0x0002 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BASE_CLASS_epvf_alt_13 0x0002 -#define pciBIF_CFG_EPVF14_nbif_gpu_BASE_CLASS_epvf_alt_14 0x0002 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BASE_CLASS_epvf_alt_14 0x0002 -#define pciBIF_CFG_EPVF15_nbif_gpu_BASE_CLASS_epvf_alt_15 0x0002 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BASE_CLASS_epvf_alt_15 0x0002 -#define pcinbif_gpu_CACHE_LINE_epvf 0x0003 -#define cfgnbif_gpu_CACHE_LINE_epvf 0x0003 -#define pciBIF_CFG_EPVF0_nbif_gpu_CACHE_LINE_epvf 0x0003 -#define cfgBIF_CFG_EPVF0_nbif_gpu_CACHE_LINE_epvf 0x0003 -#define pciBIF_CFG_EPVF1_nbif_gpu_CACHE_LINE_epvf_alt_1 0x0003 -#define cfgBIF_CFG_EPVF1_nbif_gpu_CACHE_LINE_epvf_alt_1 0x0003 -#define pciBIF_CFG_EPVF2_nbif_gpu_CACHE_LINE_epvf_alt_2 0x0003 -#define cfgBIF_CFG_EPVF2_nbif_gpu_CACHE_LINE_epvf_alt_2 0x0003 -#define pciBIF_CFG_EPVF3_nbif_gpu_CACHE_LINE_epvf_alt_3 0x0003 -#define cfgBIF_CFG_EPVF3_nbif_gpu_CACHE_LINE_epvf_alt_3 0x0003 -#define pciBIF_CFG_EPVF4_nbif_gpu_CACHE_LINE_epvf_alt_4 0x0003 -#define cfgBIF_CFG_EPVF4_nbif_gpu_CACHE_LINE_epvf_alt_4 0x0003 -#define pciBIF_CFG_EPVF5_nbif_gpu_CACHE_LINE_epvf_alt_5 0x0003 -#define cfgBIF_CFG_EPVF5_nbif_gpu_CACHE_LINE_epvf_alt_5 0x0003 -#define pciBIF_CFG_EPVF6_nbif_gpu_CACHE_LINE_epvf_alt_6 0x0003 -#define cfgBIF_CFG_EPVF6_nbif_gpu_CACHE_LINE_epvf_alt_6 0x0003 -#define pciBIF_CFG_EPVF7_nbif_gpu_CACHE_LINE_epvf_alt_7 0x0003 -#define cfgBIF_CFG_EPVF7_nbif_gpu_CACHE_LINE_epvf_alt_7 0x0003 -#define pciBIF_CFG_EPVF8_nbif_gpu_CACHE_LINE_epvf_alt_8 0x0003 -#define cfgBIF_CFG_EPVF8_nbif_gpu_CACHE_LINE_epvf_alt_8 0x0003 -#define pciBIF_CFG_EPVF9_nbif_gpu_CACHE_LINE_epvf_alt_9 0x0003 -#define cfgBIF_CFG_EPVF9_nbif_gpu_CACHE_LINE_epvf_alt_9 0x0003 -#define pciBIF_CFG_EPVF10_nbif_gpu_CACHE_LINE_epvf_alt_10 0x0003 -#define cfgBIF_CFG_EPVF10_nbif_gpu_CACHE_LINE_epvf_alt_10 0x0003 -#define pciBIF_CFG_EPVF11_nbif_gpu_CACHE_LINE_epvf_alt_11 0x0003 -#define cfgBIF_CFG_EPVF11_nbif_gpu_CACHE_LINE_epvf_alt_11 0x0003 -#define pciBIF_CFG_EPVF12_nbif_gpu_CACHE_LINE_epvf_alt_12 0x0003 -#define cfgBIF_CFG_EPVF12_nbif_gpu_CACHE_LINE_epvf_alt_12 0x0003 -#define pciBIF_CFG_EPVF13_nbif_gpu_CACHE_LINE_epvf_alt_13 0x0003 -#define cfgBIF_CFG_EPVF13_nbif_gpu_CACHE_LINE_epvf_alt_13 0x0003 -#define pciBIF_CFG_EPVF14_nbif_gpu_CACHE_LINE_epvf_alt_14 0x0003 -#define cfgBIF_CFG_EPVF14_nbif_gpu_CACHE_LINE_epvf_alt_14 0x0003 -#define pciBIF_CFG_EPVF15_nbif_gpu_CACHE_LINE_epvf_alt_15 0x0003 -#define cfgBIF_CFG_EPVF15_nbif_gpu_CACHE_LINE_epvf_alt_15 0x0003 -#define pcinbif_gpu_LATENCY_epvf 0x0003 -#define cfgnbif_gpu_LATENCY_epvf 0x0003 -#define pciBIF_CFG_EPVF0_nbif_gpu_LATENCY_epvf 0x0003 -#define cfgBIF_CFG_EPVF0_nbif_gpu_LATENCY_epvf 0x0003 -#define pciBIF_CFG_EPVF1_nbif_gpu_LATENCY_epvf_alt_1 0x0003 -#define cfgBIF_CFG_EPVF1_nbif_gpu_LATENCY_epvf_alt_1 0x0003 -#define pciBIF_CFG_EPVF2_nbif_gpu_LATENCY_epvf_alt_2 0x0003 -#define cfgBIF_CFG_EPVF2_nbif_gpu_LATENCY_epvf_alt_2 0x0003 -#define pciBIF_CFG_EPVF3_nbif_gpu_LATENCY_epvf_alt_3 0x0003 -#define cfgBIF_CFG_EPVF3_nbif_gpu_LATENCY_epvf_alt_3 0x0003 -#define pciBIF_CFG_EPVF4_nbif_gpu_LATENCY_epvf_alt_4 0x0003 -#define cfgBIF_CFG_EPVF4_nbif_gpu_LATENCY_epvf_alt_4 0x0003 -#define pciBIF_CFG_EPVF5_nbif_gpu_LATENCY_epvf_alt_5 0x0003 -#define cfgBIF_CFG_EPVF5_nbif_gpu_LATENCY_epvf_alt_5 0x0003 -#define pciBIF_CFG_EPVF6_nbif_gpu_LATENCY_epvf_alt_6 0x0003 -#define cfgBIF_CFG_EPVF6_nbif_gpu_LATENCY_epvf_alt_6 0x0003 -#define pciBIF_CFG_EPVF7_nbif_gpu_LATENCY_epvf_alt_7 0x0003 -#define cfgBIF_CFG_EPVF7_nbif_gpu_LATENCY_epvf_alt_7 0x0003 -#define pciBIF_CFG_EPVF8_nbif_gpu_LATENCY_epvf_alt_8 0x0003 -#define cfgBIF_CFG_EPVF8_nbif_gpu_LATENCY_epvf_alt_8 0x0003 -#define pciBIF_CFG_EPVF9_nbif_gpu_LATENCY_epvf_alt_9 0x0003 -#define cfgBIF_CFG_EPVF9_nbif_gpu_LATENCY_epvf_alt_9 0x0003 -#define pciBIF_CFG_EPVF10_nbif_gpu_LATENCY_epvf_alt_10 0x0003 -#define cfgBIF_CFG_EPVF10_nbif_gpu_LATENCY_epvf_alt_10 0x0003 -#define pciBIF_CFG_EPVF11_nbif_gpu_LATENCY_epvf_alt_11 0x0003 -#define cfgBIF_CFG_EPVF11_nbif_gpu_LATENCY_epvf_alt_11 0x0003 -#define pciBIF_CFG_EPVF12_nbif_gpu_LATENCY_epvf_alt_12 0x0003 -#define cfgBIF_CFG_EPVF12_nbif_gpu_LATENCY_epvf_alt_12 0x0003 -#define pciBIF_CFG_EPVF13_nbif_gpu_LATENCY_epvf_alt_13 0x0003 -#define cfgBIF_CFG_EPVF13_nbif_gpu_LATENCY_epvf_alt_13 0x0003 -#define pciBIF_CFG_EPVF14_nbif_gpu_LATENCY_epvf_alt_14 0x0003 -#define cfgBIF_CFG_EPVF14_nbif_gpu_LATENCY_epvf_alt_14 0x0003 -#define pciBIF_CFG_EPVF15_nbif_gpu_LATENCY_epvf_alt_15 0x0003 -#define cfgBIF_CFG_EPVF15_nbif_gpu_LATENCY_epvf_alt_15 0x0003 -#define pcinbif_gpu_HEADER_epvf 0x0003 -#define cfgnbif_gpu_HEADER_epvf 0x0003 -#define pciBIF_CFG_EPVF0_nbif_gpu_HEADER_epvf 0x0003 -#define cfgBIF_CFG_EPVF0_nbif_gpu_HEADER_epvf 0x0003 -#define pciBIF_CFG_EPVF1_nbif_gpu_HEADER_epvf_alt_1 0x0003 -#define cfgBIF_CFG_EPVF1_nbif_gpu_HEADER_epvf_alt_1 0x0003 -#define pciBIF_CFG_EPVF2_nbif_gpu_HEADER_epvf_alt_2 0x0003 -#define cfgBIF_CFG_EPVF2_nbif_gpu_HEADER_epvf_alt_2 0x0003 -#define pciBIF_CFG_EPVF3_nbif_gpu_HEADER_epvf_alt_3 0x0003 -#define cfgBIF_CFG_EPVF3_nbif_gpu_HEADER_epvf_alt_3 0x0003 -#define pciBIF_CFG_EPVF4_nbif_gpu_HEADER_epvf_alt_4 0x0003 -#define cfgBIF_CFG_EPVF4_nbif_gpu_HEADER_epvf_alt_4 0x0003 -#define pciBIF_CFG_EPVF5_nbif_gpu_HEADER_epvf_alt_5 0x0003 -#define cfgBIF_CFG_EPVF5_nbif_gpu_HEADER_epvf_alt_5 0x0003 -#define pciBIF_CFG_EPVF6_nbif_gpu_HEADER_epvf_alt_6 0x0003 -#define cfgBIF_CFG_EPVF6_nbif_gpu_HEADER_epvf_alt_6 0x0003 -#define pciBIF_CFG_EPVF7_nbif_gpu_HEADER_epvf_alt_7 0x0003 -#define cfgBIF_CFG_EPVF7_nbif_gpu_HEADER_epvf_alt_7 0x0003 -#define pciBIF_CFG_EPVF8_nbif_gpu_HEADER_epvf_alt_8 0x0003 -#define cfgBIF_CFG_EPVF8_nbif_gpu_HEADER_epvf_alt_8 0x0003 -#define pciBIF_CFG_EPVF9_nbif_gpu_HEADER_epvf_alt_9 0x0003 -#define cfgBIF_CFG_EPVF9_nbif_gpu_HEADER_epvf_alt_9 0x0003 -#define pciBIF_CFG_EPVF10_nbif_gpu_HEADER_epvf_alt_10 0x0003 -#define cfgBIF_CFG_EPVF10_nbif_gpu_HEADER_epvf_alt_10 0x0003 -#define pciBIF_CFG_EPVF11_nbif_gpu_HEADER_epvf_alt_11 0x0003 -#define cfgBIF_CFG_EPVF11_nbif_gpu_HEADER_epvf_alt_11 0x0003 -#define pciBIF_CFG_EPVF12_nbif_gpu_HEADER_epvf_alt_12 0x0003 -#define cfgBIF_CFG_EPVF12_nbif_gpu_HEADER_epvf_alt_12 0x0003 -#define pciBIF_CFG_EPVF13_nbif_gpu_HEADER_epvf_alt_13 0x0003 -#define cfgBIF_CFG_EPVF13_nbif_gpu_HEADER_epvf_alt_13 0x0003 -#define pciBIF_CFG_EPVF14_nbif_gpu_HEADER_epvf_alt_14 0x0003 -#define cfgBIF_CFG_EPVF14_nbif_gpu_HEADER_epvf_alt_14 0x0003 -#define pciBIF_CFG_EPVF15_nbif_gpu_HEADER_epvf_alt_15 0x0003 -#define cfgBIF_CFG_EPVF15_nbif_gpu_HEADER_epvf_alt_15 0x0003 -#define pcinbif_gpu_BIST_epvf 0x0003 -#define cfgnbif_gpu_BIST_epvf 0x0003 -#define pciBIF_CFG_EPVF0_nbif_gpu_BIST_epvf 0x0003 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BIST_epvf 0x0003 -#define pciBIF_CFG_EPVF1_nbif_gpu_BIST_epvf_alt_1 0x0003 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BIST_epvf_alt_1 0x0003 -#define pciBIF_CFG_EPVF2_nbif_gpu_BIST_epvf_alt_2 0x0003 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BIST_epvf_alt_2 0x0003 -#define pciBIF_CFG_EPVF3_nbif_gpu_BIST_epvf_alt_3 0x0003 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BIST_epvf_alt_3 0x0003 -#define pciBIF_CFG_EPVF4_nbif_gpu_BIST_epvf_alt_4 0x0003 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BIST_epvf_alt_4 0x0003 -#define pciBIF_CFG_EPVF5_nbif_gpu_BIST_epvf_alt_5 0x0003 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BIST_epvf_alt_5 0x0003 -#define pciBIF_CFG_EPVF6_nbif_gpu_BIST_epvf_alt_6 0x0003 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BIST_epvf_alt_6 0x0003 -#define pciBIF_CFG_EPVF7_nbif_gpu_BIST_epvf_alt_7 0x0003 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BIST_epvf_alt_7 0x0003 -#define pciBIF_CFG_EPVF8_nbif_gpu_BIST_epvf_alt_8 0x0003 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BIST_epvf_alt_8 0x0003 -#define pciBIF_CFG_EPVF9_nbif_gpu_BIST_epvf_alt_9 0x0003 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BIST_epvf_alt_9 0x0003 -#define pciBIF_CFG_EPVF10_nbif_gpu_BIST_epvf_alt_10 0x0003 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BIST_epvf_alt_10 0x0003 -#define pciBIF_CFG_EPVF11_nbif_gpu_BIST_epvf_alt_11 0x0003 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BIST_epvf_alt_11 0x0003 -#define pciBIF_CFG_EPVF12_nbif_gpu_BIST_epvf_alt_12 0x0003 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BIST_epvf_alt_12 0x0003 -#define pciBIF_CFG_EPVF13_nbif_gpu_BIST_epvf_alt_13 0x0003 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BIST_epvf_alt_13 0x0003 -#define pciBIF_CFG_EPVF14_nbif_gpu_BIST_epvf_alt_14 0x0003 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BIST_epvf_alt_14 0x0003 -#define pciBIF_CFG_EPVF15_nbif_gpu_BIST_epvf_alt_15 0x0003 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BIST_epvf_alt_15 0x0003 -#define pcinbif_gpu_BASE_ADDR_1_epvf 0x0004 -#define cfgnbif_gpu_BASE_ADDR_1_epvf 0x0004 -#define pciBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_1_epvf 0x0004 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_1_epvf 0x0004 -#define pciBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_1_epvf_alt_1 0x0004 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_1_epvf_alt_1 0x0004 -#define pciBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_1_epvf_alt_2 0x0004 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_1_epvf_alt_2 0x0004 -#define pciBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_1_epvf_alt_3 0x0004 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_1_epvf_alt_3 0x0004 -#define pciBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_1_epvf_alt_4 0x0004 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_1_epvf_alt_4 0x0004 -#define pciBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_1_epvf_alt_5 0x0004 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_1_epvf_alt_5 0x0004 -#define pciBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_1_epvf_alt_6 0x0004 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_1_epvf_alt_6 0x0004 -#define pciBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_1_epvf_alt_7 0x0004 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_1_epvf_alt_7 0x0004 -#define pciBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_1_epvf_alt_8 0x0004 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_1_epvf_alt_8 0x0004 -#define pciBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_1_epvf_alt_9 0x0004 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_1_epvf_alt_9 0x0004 -#define pciBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_1_epvf_alt_10 0x0004 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_1_epvf_alt_10 0x0004 -#define pciBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_1_epvf_alt_11 0x0004 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_1_epvf_alt_11 0x0004 -#define pciBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_1_epvf_alt_12 0x0004 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_1_epvf_alt_12 0x0004 -#define pciBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_1_epvf_alt_13 0x0004 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_1_epvf_alt_13 0x0004 -#define pciBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_1_epvf_alt_14 0x0004 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_1_epvf_alt_14 0x0004 -#define pciBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_1_epvf_alt_15 0x0004 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_1_epvf_alt_15 0x0004 -#define pcinbif_gpu_BASE_ADDR_2_epvf 0x0005 -#define cfgnbif_gpu_BASE_ADDR_2_epvf 0x0005 -#define pciBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_2_epvf 0x0005 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_2_epvf 0x0005 -#define pciBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_2_epvf_alt_1 0x0005 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_2_epvf_alt_1 0x0005 -#define pciBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_2_epvf_alt_2 0x0005 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_2_epvf_alt_2 0x0005 -#define pciBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_2_epvf_alt_3 0x0005 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_2_epvf_alt_3 0x0005 -#define pciBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_2_epvf_alt_4 0x0005 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_2_epvf_alt_4 0x0005 -#define pciBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_2_epvf_alt_5 0x0005 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_2_epvf_alt_5 0x0005 -#define pciBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_2_epvf_alt_6 0x0005 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_2_epvf_alt_6 0x0005 -#define pciBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_2_epvf_alt_7 0x0005 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_2_epvf_alt_7 0x0005 -#define pciBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_2_epvf_alt_8 0x0005 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_2_epvf_alt_8 0x0005 -#define pciBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_2_epvf_alt_9 0x0005 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_2_epvf_alt_9 0x0005 -#define pciBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_2_epvf_alt_10 0x0005 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_2_epvf_alt_10 0x0005 -#define pciBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_2_epvf_alt_11 0x0005 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_2_epvf_alt_11 0x0005 -#define pciBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_2_epvf_alt_12 0x0005 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_2_epvf_alt_12 0x0005 -#define pciBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_2_epvf_alt_13 0x0005 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_2_epvf_alt_13 0x0005 -#define pciBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_2_epvf_alt_14 0x0005 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_2_epvf_alt_14 0x0005 -#define pciBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_2_epvf_alt_15 0x0005 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_2_epvf_alt_15 0x0005 -#define pcinbif_gpu_BASE_ADDR_3_epvf 0x0006 -#define cfgnbif_gpu_BASE_ADDR_3_epvf 0x0006 -#define pciBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_3_epvf 0x0006 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_3_epvf 0x0006 -#define pciBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_3_epvf_alt_1 0x0006 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_3_epvf_alt_1 0x0006 -#define pciBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_3_epvf_alt_2 0x0006 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_3_epvf_alt_2 0x0006 -#define pciBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_3_epvf_alt_3 0x0006 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_3_epvf_alt_3 0x0006 -#define pciBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_3_epvf_alt_4 0x0006 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_3_epvf_alt_4 0x0006 -#define pciBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_3_epvf_alt_5 0x0006 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_3_epvf_alt_5 0x0006 -#define pciBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_3_epvf_alt_6 0x0006 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_3_epvf_alt_6 0x0006 -#define pciBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_3_epvf_alt_7 0x0006 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_3_epvf_alt_7 0x0006 -#define pciBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_3_epvf_alt_8 0x0006 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_3_epvf_alt_8 0x0006 -#define pciBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_3_epvf_alt_9 0x0006 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_3_epvf_alt_9 0x0006 -#define pciBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_3_epvf_alt_10 0x0006 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_3_epvf_alt_10 0x0006 -#define pciBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_3_epvf_alt_11 0x0006 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_3_epvf_alt_11 0x0006 -#define pciBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_3_epvf_alt_12 0x0006 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_3_epvf_alt_12 0x0006 -#define pciBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_3_epvf_alt_13 0x0006 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_3_epvf_alt_13 0x0006 -#define pciBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_3_epvf_alt_14 0x0006 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_3_epvf_alt_14 0x0006 -#define pciBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_3_epvf_alt_15 0x0006 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_3_epvf_alt_15 0x0006 -#define pcinbif_gpu_BASE_ADDR_4_epvf 0x0007 -#define cfgnbif_gpu_BASE_ADDR_4_epvf 0x0007 -#define pciBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_4_epvf 0x0007 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_4_epvf 0x0007 -#define pciBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_4_epvf_alt_1 0x0007 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_4_epvf_alt_1 0x0007 -#define pciBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_4_epvf_alt_2 0x0007 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_4_epvf_alt_2 0x0007 -#define pciBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_4_epvf_alt_3 0x0007 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_4_epvf_alt_3 0x0007 -#define pciBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_4_epvf_alt_4 0x0007 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_4_epvf_alt_4 0x0007 -#define pciBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_4_epvf_alt_5 0x0007 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_4_epvf_alt_5 0x0007 -#define pciBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_4_epvf_alt_6 0x0007 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_4_epvf_alt_6 0x0007 -#define pciBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_4_epvf_alt_7 0x0007 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_4_epvf_alt_7 0x0007 -#define pciBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_4_epvf_alt_8 0x0007 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_4_epvf_alt_8 0x0007 -#define pciBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_4_epvf_alt_9 0x0007 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_4_epvf_alt_9 0x0007 -#define pciBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_4_epvf_alt_10 0x0007 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_4_epvf_alt_10 0x0007 -#define pciBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_4_epvf_alt_11 0x0007 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_4_epvf_alt_11 0x0007 -#define pciBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_4_epvf_alt_12 0x0007 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_4_epvf_alt_12 0x0007 -#define pciBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_4_epvf_alt_13 0x0007 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_4_epvf_alt_13 0x0007 -#define pciBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_4_epvf_alt_14 0x0007 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_4_epvf_alt_14 0x0007 -#define pciBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_4_epvf_alt_15 0x0007 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_4_epvf_alt_15 0x0007 -#define pcinbif_gpu_BASE_ADDR_5_epvf 0x0008 -#define cfgnbif_gpu_BASE_ADDR_5_epvf 0x0008 -#define pciBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_5_epvf 0x0008 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_5_epvf 0x0008 -#define pciBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_5_epvf_alt_1 0x0008 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_5_epvf_alt_1 0x0008 -#define pciBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_5_epvf_alt_2 0x0008 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_5_epvf_alt_2 0x0008 -#define pciBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_5_epvf_alt_3 0x0008 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_5_epvf_alt_3 0x0008 -#define pciBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_5_epvf_alt_4 0x0008 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_5_epvf_alt_4 0x0008 -#define pciBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_5_epvf_alt_5 0x0008 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_5_epvf_alt_5 0x0008 -#define pciBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_5_epvf_alt_6 0x0008 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_5_epvf_alt_6 0x0008 -#define pciBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_5_epvf_alt_7 0x0008 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_5_epvf_alt_7 0x0008 -#define pciBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_5_epvf_alt_8 0x0008 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_5_epvf_alt_8 0x0008 -#define pciBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_5_epvf_alt_9 0x0008 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_5_epvf_alt_9 0x0008 -#define pciBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_5_epvf_alt_10 0x0008 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_5_epvf_alt_10 0x0008 -#define pciBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_5_epvf_alt_11 0x0008 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_5_epvf_alt_11 0x0008 -#define pciBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_5_epvf_alt_12 0x0008 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_5_epvf_alt_12 0x0008 -#define pciBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_5_epvf_alt_13 0x0008 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_5_epvf_alt_13 0x0008 -#define pciBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_5_epvf_alt_14 0x0008 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_5_epvf_alt_14 0x0008 -#define pciBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_5_epvf_alt_15 0x0008 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_5_epvf_alt_15 0x0008 -#define pcinbif_gpu_BASE_ADDR_6_epvf 0x0009 -#define cfgnbif_gpu_BASE_ADDR_6_epvf 0x0009 -#define pciBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_6_epvf 0x0009 -#define cfgBIF_CFG_EPVF0_nbif_gpu_BASE_ADDR_6_epvf 0x0009 -#define pciBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_6_epvf_alt_1 0x0009 -#define cfgBIF_CFG_EPVF1_nbif_gpu_BASE_ADDR_6_epvf_alt_1 0x0009 -#define pciBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_6_epvf_alt_2 0x0009 -#define cfgBIF_CFG_EPVF2_nbif_gpu_BASE_ADDR_6_epvf_alt_2 0x0009 -#define pciBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_6_epvf_alt_3 0x0009 -#define cfgBIF_CFG_EPVF3_nbif_gpu_BASE_ADDR_6_epvf_alt_3 0x0009 -#define pciBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_6_epvf_alt_4 0x0009 -#define cfgBIF_CFG_EPVF4_nbif_gpu_BASE_ADDR_6_epvf_alt_4 0x0009 -#define pciBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_6_epvf_alt_5 0x0009 -#define cfgBIF_CFG_EPVF5_nbif_gpu_BASE_ADDR_6_epvf_alt_5 0x0009 -#define pciBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_6_epvf_alt_6 0x0009 -#define cfgBIF_CFG_EPVF6_nbif_gpu_BASE_ADDR_6_epvf_alt_6 0x0009 -#define pciBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_6_epvf_alt_7 0x0009 -#define cfgBIF_CFG_EPVF7_nbif_gpu_BASE_ADDR_6_epvf_alt_7 0x0009 -#define pciBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_6_epvf_alt_8 0x0009 -#define cfgBIF_CFG_EPVF8_nbif_gpu_BASE_ADDR_6_epvf_alt_8 0x0009 -#define pciBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_6_epvf_alt_9 0x0009 -#define cfgBIF_CFG_EPVF9_nbif_gpu_BASE_ADDR_6_epvf_alt_9 0x0009 -#define pciBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_6_epvf_alt_10 0x0009 -#define cfgBIF_CFG_EPVF10_nbif_gpu_BASE_ADDR_6_epvf_alt_10 0x0009 -#define pciBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_6_epvf_alt_11 0x0009 -#define cfgBIF_CFG_EPVF11_nbif_gpu_BASE_ADDR_6_epvf_alt_11 0x0009 -#define pciBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_6_epvf_alt_12 0x0009 -#define cfgBIF_CFG_EPVF12_nbif_gpu_BASE_ADDR_6_epvf_alt_12 0x0009 -#define pciBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_6_epvf_alt_13 0x0009 -#define cfgBIF_CFG_EPVF13_nbif_gpu_BASE_ADDR_6_epvf_alt_13 0x0009 -#define pciBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_6_epvf_alt_14 0x0009 -#define cfgBIF_CFG_EPVF14_nbif_gpu_BASE_ADDR_6_epvf_alt_14 0x0009 -#define pciBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_6_epvf_alt_15 0x0009 -#define cfgBIF_CFG_EPVF15_nbif_gpu_BASE_ADDR_6_epvf_alt_15 0x0009 -#define pcinbif_gpu_ROM_BASE_ADDR_epvf 0x000C -#define cfgnbif_gpu_ROM_BASE_ADDR_epvf 0x000C -#define pciBIF_CFG_EPVF0_nbif_gpu_ROM_BASE_ADDR_epvf 0x000C -#define cfgBIF_CFG_EPVF0_nbif_gpu_ROM_BASE_ADDR_epvf 0x000C -#define pciBIF_CFG_EPVF1_nbif_gpu_ROM_BASE_ADDR_epvf_alt_1 0x000C -#define cfgBIF_CFG_EPVF1_nbif_gpu_ROM_BASE_ADDR_epvf_alt_1 0x000C -#define pciBIF_CFG_EPVF2_nbif_gpu_ROM_BASE_ADDR_epvf_alt_2 0x000C -#define cfgBIF_CFG_EPVF2_nbif_gpu_ROM_BASE_ADDR_epvf_alt_2 0x000C -#define pciBIF_CFG_EPVF3_nbif_gpu_ROM_BASE_ADDR_epvf_alt_3 0x000C -#define cfgBIF_CFG_EPVF3_nbif_gpu_ROM_BASE_ADDR_epvf_alt_3 0x000C -#define pciBIF_CFG_EPVF4_nbif_gpu_ROM_BASE_ADDR_epvf_alt_4 0x000C -#define cfgBIF_CFG_EPVF4_nbif_gpu_ROM_BASE_ADDR_epvf_alt_4 0x000C -#define pciBIF_CFG_EPVF5_nbif_gpu_ROM_BASE_ADDR_epvf_alt_5 0x000C -#define cfgBIF_CFG_EPVF5_nbif_gpu_ROM_BASE_ADDR_epvf_alt_5 0x000C -#define pciBIF_CFG_EPVF6_nbif_gpu_ROM_BASE_ADDR_epvf_alt_6 0x000C -#define cfgBIF_CFG_EPVF6_nbif_gpu_ROM_BASE_ADDR_epvf_alt_6 0x000C -#define pciBIF_CFG_EPVF7_nbif_gpu_ROM_BASE_ADDR_epvf_alt_7 0x000C -#define cfgBIF_CFG_EPVF7_nbif_gpu_ROM_BASE_ADDR_epvf_alt_7 0x000C -#define pciBIF_CFG_EPVF8_nbif_gpu_ROM_BASE_ADDR_epvf_alt_8 0x000C -#define cfgBIF_CFG_EPVF8_nbif_gpu_ROM_BASE_ADDR_epvf_alt_8 0x000C -#define pciBIF_CFG_EPVF9_nbif_gpu_ROM_BASE_ADDR_epvf_alt_9 0x000C -#define cfgBIF_CFG_EPVF9_nbif_gpu_ROM_BASE_ADDR_epvf_alt_9 0x000C -#define pciBIF_CFG_EPVF10_nbif_gpu_ROM_BASE_ADDR_epvf_alt_10 0x000C -#define cfgBIF_CFG_EPVF10_nbif_gpu_ROM_BASE_ADDR_epvf_alt_10 0x000C -#define pciBIF_CFG_EPVF11_nbif_gpu_ROM_BASE_ADDR_epvf_alt_11 0x000C -#define cfgBIF_CFG_EPVF11_nbif_gpu_ROM_BASE_ADDR_epvf_alt_11 0x000C -#define pciBIF_CFG_EPVF12_nbif_gpu_ROM_BASE_ADDR_epvf_alt_12 0x000C -#define cfgBIF_CFG_EPVF12_nbif_gpu_ROM_BASE_ADDR_epvf_alt_12 0x000C -#define pciBIF_CFG_EPVF13_nbif_gpu_ROM_BASE_ADDR_epvf_alt_13 0x000C -#define cfgBIF_CFG_EPVF13_nbif_gpu_ROM_BASE_ADDR_epvf_alt_13 0x000C -#define pciBIF_CFG_EPVF14_nbif_gpu_ROM_BASE_ADDR_epvf_alt_14 0x000C -#define cfgBIF_CFG_EPVF14_nbif_gpu_ROM_BASE_ADDR_epvf_alt_14 0x000C -#define pciBIF_CFG_EPVF15_nbif_gpu_ROM_BASE_ADDR_epvf_alt_15 0x000C -#define cfgBIF_CFG_EPVF15_nbif_gpu_ROM_BASE_ADDR_epvf_alt_15 0x000C -#define pcinbif_gpu_CAP_PTR_epvf 0x000D -#define cfgnbif_gpu_CAP_PTR_epvf 0x000D -#define pciBIF_CFG_EPVF0_nbif_gpu_CAP_PTR_epvf 0x000D -#define cfgBIF_CFG_EPVF0_nbif_gpu_CAP_PTR_epvf 0x000D -#define pciBIF_CFG_EPVF1_nbif_gpu_CAP_PTR_epvf_alt_1 0x000D -#define cfgBIF_CFG_EPVF1_nbif_gpu_CAP_PTR_epvf_alt_1 0x000D -#define pciBIF_CFG_EPVF2_nbif_gpu_CAP_PTR_epvf_alt_2 0x000D -#define cfgBIF_CFG_EPVF2_nbif_gpu_CAP_PTR_epvf_alt_2 0x000D -#define pciBIF_CFG_EPVF3_nbif_gpu_CAP_PTR_epvf_alt_3 0x000D -#define cfgBIF_CFG_EPVF3_nbif_gpu_CAP_PTR_epvf_alt_3 0x000D -#define pciBIF_CFG_EPVF4_nbif_gpu_CAP_PTR_epvf_alt_4 0x000D -#define cfgBIF_CFG_EPVF4_nbif_gpu_CAP_PTR_epvf_alt_4 0x000D -#define pciBIF_CFG_EPVF5_nbif_gpu_CAP_PTR_epvf_alt_5 0x000D -#define cfgBIF_CFG_EPVF5_nbif_gpu_CAP_PTR_epvf_alt_5 0x000D -#define pciBIF_CFG_EPVF6_nbif_gpu_CAP_PTR_epvf_alt_6 0x000D -#define cfgBIF_CFG_EPVF6_nbif_gpu_CAP_PTR_epvf_alt_6 0x000D -#define pciBIF_CFG_EPVF7_nbif_gpu_CAP_PTR_epvf_alt_7 0x000D -#define cfgBIF_CFG_EPVF7_nbif_gpu_CAP_PTR_epvf_alt_7 0x000D -#define pciBIF_CFG_EPVF8_nbif_gpu_CAP_PTR_epvf_alt_8 0x000D -#define cfgBIF_CFG_EPVF8_nbif_gpu_CAP_PTR_epvf_alt_8 0x000D -#define pciBIF_CFG_EPVF9_nbif_gpu_CAP_PTR_epvf_alt_9 0x000D -#define cfgBIF_CFG_EPVF9_nbif_gpu_CAP_PTR_epvf_alt_9 0x000D -#define pciBIF_CFG_EPVF10_nbif_gpu_CAP_PTR_epvf_alt_10 0x000D -#define cfgBIF_CFG_EPVF10_nbif_gpu_CAP_PTR_epvf_alt_10 0x000D -#define pciBIF_CFG_EPVF11_nbif_gpu_CAP_PTR_epvf_alt_11 0x000D -#define cfgBIF_CFG_EPVF11_nbif_gpu_CAP_PTR_epvf_alt_11 0x000D -#define pciBIF_CFG_EPVF12_nbif_gpu_CAP_PTR_epvf_alt_12 0x000D -#define cfgBIF_CFG_EPVF12_nbif_gpu_CAP_PTR_epvf_alt_12 0x000D -#define pciBIF_CFG_EPVF13_nbif_gpu_CAP_PTR_epvf_alt_13 0x000D -#define cfgBIF_CFG_EPVF13_nbif_gpu_CAP_PTR_epvf_alt_13 0x000D -#define pciBIF_CFG_EPVF14_nbif_gpu_CAP_PTR_epvf_alt_14 0x000D -#define cfgBIF_CFG_EPVF14_nbif_gpu_CAP_PTR_epvf_alt_14 0x000D -#define pciBIF_CFG_EPVF15_nbif_gpu_CAP_PTR_epvf_alt_15 0x000D -#define cfgBIF_CFG_EPVF15_nbif_gpu_CAP_PTR_epvf_alt_15 0x000D -#define pcinbif_gpu_INTERRUPT_LINE_epvf 0x000F -#define cfgnbif_gpu_INTERRUPT_LINE_epvf 0x000F -#define pciBIF_CFG_EPVF0_nbif_gpu_INTERRUPT_LINE_epvf 0x000F -#define cfgBIF_CFG_EPVF0_nbif_gpu_INTERRUPT_LINE_epvf 0x000F -#define pciBIF_CFG_EPVF1_nbif_gpu_INTERRUPT_LINE_epvf_alt_1 0x000F -#define cfgBIF_CFG_EPVF1_nbif_gpu_INTERRUPT_LINE_epvf_alt_1 0x000F -#define pciBIF_CFG_EPVF2_nbif_gpu_INTERRUPT_LINE_epvf_alt_2 0x000F -#define cfgBIF_CFG_EPVF2_nbif_gpu_INTERRUPT_LINE_epvf_alt_2 0x000F -#define pciBIF_CFG_EPVF3_nbif_gpu_INTERRUPT_LINE_epvf_alt_3 0x000F -#define cfgBIF_CFG_EPVF3_nbif_gpu_INTERRUPT_LINE_epvf_alt_3 0x000F -#define pciBIF_CFG_EPVF4_nbif_gpu_INTERRUPT_LINE_epvf_alt_4 0x000F -#define cfgBIF_CFG_EPVF4_nbif_gpu_INTERRUPT_LINE_epvf_alt_4 0x000F -#define pciBIF_CFG_EPVF5_nbif_gpu_INTERRUPT_LINE_epvf_alt_5 0x000F -#define cfgBIF_CFG_EPVF5_nbif_gpu_INTERRUPT_LINE_epvf_alt_5 0x000F -#define pciBIF_CFG_EPVF6_nbif_gpu_INTERRUPT_LINE_epvf_alt_6 0x000F -#define cfgBIF_CFG_EPVF6_nbif_gpu_INTERRUPT_LINE_epvf_alt_6 0x000F -#define pciBIF_CFG_EPVF7_nbif_gpu_INTERRUPT_LINE_epvf_alt_7 0x000F -#define cfgBIF_CFG_EPVF7_nbif_gpu_INTERRUPT_LINE_epvf_alt_7 0x000F -#define pciBIF_CFG_EPVF8_nbif_gpu_INTERRUPT_LINE_epvf_alt_8 0x000F -#define cfgBIF_CFG_EPVF8_nbif_gpu_INTERRUPT_LINE_epvf_alt_8 0x000F -#define pciBIF_CFG_EPVF9_nbif_gpu_INTERRUPT_LINE_epvf_alt_9 0x000F -#define cfgBIF_CFG_EPVF9_nbif_gpu_INTERRUPT_LINE_epvf_alt_9 0x000F -#define pciBIF_CFG_EPVF10_nbif_gpu_INTERRUPT_LINE_epvf_alt_10 0x000F -#define cfgBIF_CFG_EPVF10_nbif_gpu_INTERRUPT_LINE_epvf_alt_10 0x000F -#define pciBIF_CFG_EPVF11_nbif_gpu_INTERRUPT_LINE_epvf_alt_11 0x000F -#define cfgBIF_CFG_EPVF11_nbif_gpu_INTERRUPT_LINE_epvf_alt_11 0x000F -#define pciBIF_CFG_EPVF12_nbif_gpu_INTERRUPT_LINE_epvf_alt_12 0x000F -#define cfgBIF_CFG_EPVF12_nbif_gpu_INTERRUPT_LINE_epvf_alt_12 0x000F -#define pciBIF_CFG_EPVF13_nbif_gpu_INTERRUPT_LINE_epvf_alt_13 0x000F -#define cfgBIF_CFG_EPVF13_nbif_gpu_INTERRUPT_LINE_epvf_alt_13 0x000F -#define pciBIF_CFG_EPVF14_nbif_gpu_INTERRUPT_LINE_epvf_alt_14 0x000F -#define cfgBIF_CFG_EPVF14_nbif_gpu_INTERRUPT_LINE_epvf_alt_14 0x000F -#define pciBIF_CFG_EPVF15_nbif_gpu_INTERRUPT_LINE_epvf_alt_15 0x000F -#define cfgBIF_CFG_EPVF15_nbif_gpu_INTERRUPT_LINE_epvf_alt_15 0x000F -#define pcinbif_gpu_INTERRUPT_PIN_epvf 0x000F -#define cfgnbif_gpu_INTERRUPT_PIN_epvf 0x000F -#define pciBIF_CFG_EPVF0_nbif_gpu_INTERRUPT_PIN_epvf 0x000F -#define cfgBIF_CFG_EPVF0_nbif_gpu_INTERRUPT_PIN_epvf 0x000F -#define pciBIF_CFG_EPVF1_nbif_gpu_INTERRUPT_PIN_epvf_alt_1 0x000F -#define cfgBIF_CFG_EPVF1_nbif_gpu_INTERRUPT_PIN_epvf_alt_1 0x000F -#define pciBIF_CFG_EPVF2_nbif_gpu_INTERRUPT_PIN_epvf_alt_2 0x000F -#define cfgBIF_CFG_EPVF2_nbif_gpu_INTERRUPT_PIN_epvf_alt_2 0x000F -#define pciBIF_CFG_EPVF3_nbif_gpu_INTERRUPT_PIN_epvf_alt_3 0x000F -#define cfgBIF_CFG_EPVF3_nbif_gpu_INTERRUPT_PIN_epvf_alt_3 0x000F -#define pciBIF_CFG_EPVF4_nbif_gpu_INTERRUPT_PIN_epvf_alt_4 0x000F -#define cfgBIF_CFG_EPVF4_nbif_gpu_INTERRUPT_PIN_epvf_alt_4 0x000F -#define pciBIF_CFG_EPVF5_nbif_gpu_INTERRUPT_PIN_epvf_alt_5 0x000F -#define cfgBIF_CFG_EPVF5_nbif_gpu_INTERRUPT_PIN_epvf_alt_5 0x000F -#define pciBIF_CFG_EPVF6_nbif_gpu_INTERRUPT_PIN_epvf_alt_6 0x000F -#define cfgBIF_CFG_EPVF6_nbif_gpu_INTERRUPT_PIN_epvf_alt_6 0x000F -#define pciBIF_CFG_EPVF7_nbif_gpu_INTERRUPT_PIN_epvf_alt_7 0x000F -#define cfgBIF_CFG_EPVF7_nbif_gpu_INTERRUPT_PIN_epvf_alt_7 0x000F -#define pciBIF_CFG_EPVF8_nbif_gpu_INTERRUPT_PIN_epvf_alt_8 0x000F -#define cfgBIF_CFG_EPVF8_nbif_gpu_INTERRUPT_PIN_epvf_alt_8 0x000F -#define pciBIF_CFG_EPVF9_nbif_gpu_INTERRUPT_PIN_epvf_alt_9 0x000F -#define cfgBIF_CFG_EPVF9_nbif_gpu_INTERRUPT_PIN_epvf_alt_9 0x000F -#define pciBIF_CFG_EPVF10_nbif_gpu_INTERRUPT_PIN_epvf_alt_10 0x000F -#define cfgBIF_CFG_EPVF10_nbif_gpu_INTERRUPT_PIN_epvf_alt_10 0x000F -#define pciBIF_CFG_EPVF11_nbif_gpu_INTERRUPT_PIN_epvf_alt_11 0x000F -#define cfgBIF_CFG_EPVF11_nbif_gpu_INTERRUPT_PIN_epvf_alt_11 0x000F -#define pciBIF_CFG_EPVF12_nbif_gpu_INTERRUPT_PIN_epvf_alt_12 0x000F -#define cfgBIF_CFG_EPVF12_nbif_gpu_INTERRUPT_PIN_epvf_alt_12 0x000F -#define pciBIF_CFG_EPVF13_nbif_gpu_INTERRUPT_PIN_epvf_alt_13 0x000F -#define cfgBIF_CFG_EPVF13_nbif_gpu_INTERRUPT_PIN_epvf_alt_13 0x000F -#define pciBIF_CFG_EPVF14_nbif_gpu_INTERRUPT_PIN_epvf_alt_14 0x000F -#define cfgBIF_CFG_EPVF14_nbif_gpu_INTERRUPT_PIN_epvf_alt_14 0x000F -#define pciBIF_CFG_EPVF15_nbif_gpu_INTERRUPT_PIN_epvf_alt_15 0x000F -#define cfgBIF_CFG_EPVF15_nbif_gpu_INTERRUPT_PIN_epvf_alt_15 0x000F -#define pcinbif_gpu_ADAPTER_ID_epvf 0x000B -#define cfgnbif_gpu_ADAPTER_ID_epvf 0x000B -#define pciBIF_CFG_EPVF0_nbif_gpu_ADAPTER_ID_epvf 0x000B -#define cfgBIF_CFG_EPVF0_nbif_gpu_ADAPTER_ID_epvf 0x000B -#define pciBIF_CFG_EPVF1_nbif_gpu_ADAPTER_ID_epvf_alt_1 0x000B -#define cfgBIF_CFG_EPVF1_nbif_gpu_ADAPTER_ID_epvf_alt_1 0x000B -#define pciBIF_CFG_EPVF2_nbif_gpu_ADAPTER_ID_epvf_alt_2 0x000B -#define cfgBIF_CFG_EPVF2_nbif_gpu_ADAPTER_ID_epvf_alt_2 0x000B -#define pciBIF_CFG_EPVF3_nbif_gpu_ADAPTER_ID_epvf_alt_3 0x000B -#define cfgBIF_CFG_EPVF3_nbif_gpu_ADAPTER_ID_epvf_alt_3 0x000B -#define pciBIF_CFG_EPVF4_nbif_gpu_ADAPTER_ID_epvf_alt_4 0x000B -#define cfgBIF_CFG_EPVF4_nbif_gpu_ADAPTER_ID_epvf_alt_4 0x000B -#define pciBIF_CFG_EPVF5_nbif_gpu_ADAPTER_ID_epvf_alt_5 0x000B -#define cfgBIF_CFG_EPVF5_nbif_gpu_ADAPTER_ID_epvf_alt_5 0x000B -#define pciBIF_CFG_EPVF6_nbif_gpu_ADAPTER_ID_epvf_alt_6 0x000B -#define cfgBIF_CFG_EPVF6_nbif_gpu_ADAPTER_ID_epvf_alt_6 0x000B -#define pciBIF_CFG_EPVF7_nbif_gpu_ADAPTER_ID_epvf_alt_7 0x000B -#define cfgBIF_CFG_EPVF7_nbif_gpu_ADAPTER_ID_epvf_alt_7 0x000B -#define pciBIF_CFG_EPVF8_nbif_gpu_ADAPTER_ID_epvf_alt_8 0x000B -#define cfgBIF_CFG_EPVF8_nbif_gpu_ADAPTER_ID_epvf_alt_8 0x000B -#define pciBIF_CFG_EPVF9_nbif_gpu_ADAPTER_ID_epvf_alt_9 0x000B -#define cfgBIF_CFG_EPVF9_nbif_gpu_ADAPTER_ID_epvf_alt_9 0x000B -#define pciBIF_CFG_EPVF10_nbif_gpu_ADAPTER_ID_epvf_alt_10 0x000B -#define cfgBIF_CFG_EPVF10_nbif_gpu_ADAPTER_ID_epvf_alt_10 0x000B -#define pciBIF_CFG_EPVF11_nbif_gpu_ADAPTER_ID_epvf_alt_11 0x000B -#define cfgBIF_CFG_EPVF11_nbif_gpu_ADAPTER_ID_epvf_alt_11 0x000B -#define pciBIF_CFG_EPVF12_nbif_gpu_ADAPTER_ID_epvf_alt_12 0x000B -#define cfgBIF_CFG_EPVF12_nbif_gpu_ADAPTER_ID_epvf_alt_12 0x000B -#define pciBIF_CFG_EPVF13_nbif_gpu_ADAPTER_ID_epvf_alt_13 0x000B -#define cfgBIF_CFG_EPVF13_nbif_gpu_ADAPTER_ID_epvf_alt_13 0x000B -#define pciBIF_CFG_EPVF14_nbif_gpu_ADAPTER_ID_epvf_alt_14 0x000B -#define cfgBIF_CFG_EPVF14_nbif_gpu_ADAPTER_ID_epvf_alt_14 0x000B -#define pciBIF_CFG_EPVF15_nbif_gpu_ADAPTER_ID_epvf_alt_15 0x000B -#define cfgBIF_CFG_EPVF15_nbif_gpu_ADAPTER_ID_epvf_alt_15 0x000B -#define pcinbif_gpu_PCIE_CAP_LIST_epvf 0x0019 -#define cfgnbif_gpu_PCIE_CAP_LIST_epvf 0x0019 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_CAP_LIST_epvf 0x0019 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_CAP_LIST_epvf 0x0019 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_CAP_LIST_epvf_alt_1 0x0019 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_CAP_LIST_epvf_alt_1 0x0019 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_CAP_LIST_epvf_alt_2 0x0019 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_CAP_LIST_epvf_alt_2 0x0019 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_CAP_LIST_epvf_alt_3 0x0019 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_CAP_LIST_epvf_alt_3 0x0019 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_CAP_LIST_epvf_alt_4 0x0019 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_CAP_LIST_epvf_alt_4 0x0019 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_CAP_LIST_epvf_alt_5 0x0019 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_CAP_LIST_epvf_alt_5 0x0019 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_CAP_LIST_epvf_alt_6 0x0019 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_CAP_LIST_epvf_alt_6 0x0019 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_CAP_LIST_epvf_alt_7 0x0019 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_CAP_LIST_epvf_alt_7 0x0019 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_CAP_LIST_epvf_alt_8 0x0019 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_CAP_LIST_epvf_alt_8 0x0019 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_CAP_LIST_epvf_alt_9 0x0019 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_CAP_LIST_epvf_alt_9 0x0019 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_CAP_LIST_epvf_alt_10 0x0019 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_CAP_LIST_epvf_alt_10 0x0019 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_CAP_LIST_epvf_alt_11 0x0019 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_CAP_LIST_epvf_alt_11 0x0019 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_CAP_LIST_epvf_alt_12 0x0019 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_CAP_LIST_epvf_alt_12 0x0019 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_CAP_LIST_epvf_alt_13 0x0019 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_CAP_LIST_epvf_alt_13 0x0019 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_CAP_LIST_epvf_alt_14 0x0019 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_CAP_LIST_epvf_alt_14 0x0019 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_CAP_LIST_epvf_alt_15 0x0019 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_CAP_LIST_epvf_alt_15 0x0019 -#define pcinbif_gpu_PCIE_CAP_epvf 0x0019 -#define cfgnbif_gpu_PCIE_CAP_epvf 0x0019 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_CAP_epvf 0x0019 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_CAP_epvf 0x0019 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_CAP_epvf_alt_1 0x0019 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_CAP_epvf_alt_1 0x0019 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_CAP_epvf_alt_2 0x0019 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_CAP_epvf_alt_2 0x0019 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_CAP_epvf_alt_3 0x0019 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_CAP_epvf_alt_3 0x0019 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_CAP_epvf_alt_4 0x0019 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_CAP_epvf_alt_4 0x0019 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_CAP_epvf_alt_5 0x0019 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_CAP_epvf_alt_5 0x0019 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_CAP_epvf_alt_6 0x0019 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_CAP_epvf_alt_6 0x0019 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_CAP_epvf_alt_7 0x0019 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_CAP_epvf_alt_7 0x0019 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_CAP_epvf_alt_8 0x0019 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_CAP_epvf_alt_8 0x0019 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_CAP_epvf_alt_9 0x0019 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_CAP_epvf_alt_9 0x0019 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_CAP_epvf_alt_10 0x0019 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_CAP_epvf_alt_10 0x0019 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_CAP_epvf_alt_11 0x0019 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_CAP_epvf_alt_11 0x0019 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_CAP_epvf_alt_12 0x0019 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_CAP_epvf_alt_12 0x0019 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_CAP_epvf_alt_13 0x0019 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_CAP_epvf_alt_13 0x0019 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_CAP_epvf_alt_14 0x0019 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_CAP_epvf_alt_14 0x0019 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_CAP_epvf_alt_15 0x0019 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_CAP_epvf_alt_15 0x0019 -#define pcinbif_gpu_DEVICE_CAP_epvf 0x001A -#define cfgnbif_gpu_DEVICE_CAP_epvf 0x001A -#define pciBIF_CFG_EPVF0_nbif_gpu_DEVICE_CAP_epvf 0x001A -#define cfgBIF_CFG_EPVF0_nbif_gpu_DEVICE_CAP_epvf 0x001A -#define pciBIF_CFG_EPVF1_nbif_gpu_DEVICE_CAP_epvf_alt_1 0x001A -#define cfgBIF_CFG_EPVF1_nbif_gpu_DEVICE_CAP_epvf_alt_1 0x001A -#define pciBIF_CFG_EPVF2_nbif_gpu_DEVICE_CAP_epvf_alt_2 0x001A -#define cfgBIF_CFG_EPVF2_nbif_gpu_DEVICE_CAP_epvf_alt_2 0x001A -#define pciBIF_CFG_EPVF3_nbif_gpu_DEVICE_CAP_epvf_alt_3 0x001A -#define cfgBIF_CFG_EPVF3_nbif_gpu_DEVICE_CAP_epvf_alt_3 0x001A -#define pciBIF_CFG_EPVF4_nbif_gpu_DEVICE_CAP_epvf_alt_4 0x001A -#define cfgBIF_CFG_EPVF4_nbif_gpu_DEVICE_CAP_epvf_alt_4 0x001A -#define pciBIF_CFG_EPVF5_nbif_gpu_DEVICE_CAP_epvf_alt_5 0x001A -#define cfgBIF_CFG_EPVF5_nbif_gpu_DEVICE_CAP_epvf_alt_5 0x001A -#define pciBIF_CFG_EPVF6_nbif_gpu_DEVICE_CAP_epvf_alt_6 0x001A -#define cfgBIF_CFG_EPVF6_nbif_gpu_DEVICE_CAP_epvf_alt_6 0x001A -#define pciBIF_CFG_EPVF7_nbif_gpu_DEVICE_CAP_epvf_alt_7 0x001A -#define cfgBIF_CFG_EPVF7_nbif_gpu_DEVICE_CAP_epvf_alt_7 0x001A -#define pciBIF_CFG_EPVF8_nbif_gpu_DEVICE_CAP_epvf_alt_8 0x001A -#define cfgBIF_CFG_EPVF8_nbif_gpu_DEVICE_CAP_epvf_alt_8 0x001A -#define pciBIF_CFG_EPVF9_nbif_gpu_DEVICE_CAP_epvf_alt_9 0x001A -#define cfgBIF_CFG_EPVF9_nbif_gpu_DEVICE_CAP_epvf_alt_9 0x001A -#define pciBIF_CFG_EPVF10_nbif_gpu_DEVICE_CAP_epvf_alt_10 0x001A -#define cfgBIF_CFG_EPVF10_nbif_gpu_DEVICE_CAP_epvf_alt_10 0x001A -#define pciBIF_CFG_EPVF11_nbif_gpu_DEVICE_CAP_epvf_alt_11 0x001A -#define cfgBIF_CFG_EPVF11_nbif_gpu_DEVICE_CAP_epvf_alt_11 0x001A -#define pciBIF_CFG_EPVF12_nbif_gpu_DEVICE_CAP_epvf_alt_12 0x001A -#define cfgBIF_CFG_EPVF12_nbif_gpu_DEVICE_CAP_epvf_alt_12 0x001A -#define pciBIF_CFG_EPVF13_nbif_gpu_DEVICE_CAP_epvf_alt_13 0x001A -#define cfgBIF_CFG_EPVF13_nbif_gpu_DEVICE_CAP_epvf_alt_13 0x001A -#define pciBIF_CFG_EPVF14_nbif_gpu_DEVICE_CAP_epvf_alt_14 0x001A -#define cfgBIF_CFG_EPVF14_nbif_gpu_DEVICE_CAP_epvf_alt_14 0x001A -#define pciBIF_CFG_EPVF15_nbif_gpu_DEVICE_CAP_epvf_alt_15 0x001A -#define cfgBIF_CFG_EPVF15_nbif_gpu_DEVICE_CAP_epvf_alt_15 0x001A -#define pcinbif_gpu_DEVICE_CNTL_epvf 0x001B -#define cfgnbif_gpu_DEVICE_CNTL_epvf 0x001B -#define pciBIF_CFG_EPVF0_nbif_gpu_DEVICE_CNTL_epvf 0x001B -#define cfgBIF_CFG_EPVF0_nbif_gpu_DEVICE_CNTL_epvf 0x001B -#define pciBIF_CFG_EPVF1_nbif_gpu_DEVICE_CNTL_epvf_alt_1 0x001B -#define cfgBIF_CFG_EPVF1_nbif_gpu_DEVICE_CNTL_epvf_alt_1 0x001B -#define pciBIF_CFG_EPVF2_nbif_gpu_DEVICE_CNTL_epvf_alt_2 0x001B -#define cfgBIF_CFG_EPVF2_nbif_gpu_DEVICE_CNTL_epvf_alt_2 0x001B -#define pciBIF_CFG_EPVF3_nbif_gpu_DEVICE_CNTL_epvf_alt_3 0x001B -#define cfgBIF_CFG_EPVF3_nbif_gpu_DEVICE_CNTL_epvf_alt_3 0x001B -#define pciBIF_CFG_EPVF4_nbif_gpu_DEVICE_CNTL_epvf_alt_4 0x001B -#define cfgBIF_CFG_EPVF4_nbif_gpu_DEVICE_CNTL_epvf_alt_4 0x001B -#define pciBIF_CFG_EPVF5_nbif_gpu_DEVICE_CNTL_epvf_alt_5 0x001B -#define cfgBIF_CFG_EPVF5_nbif_gpu_DEVICE_CNTL_epvf_alt_5 0x001B -#define pciBIF_CFG_EPVF6_nbif_gpu_DEVICE_CNTL_epvf_alt_6 0x001B -#define cfgBIF_CFG_EPVF6_nbif_gpu_DEVICE_CNTL_epvf_alt_6 0x001B -#define pciBIF_CFG_EPVF7_nbif_gpu_DEVICE_CNTL_epvf_alt_7 0x001B -#define cfgBIF_CFG_EPVF7_nbif_gpu_DEVICE_CNTL_epvf_alt_7 0x001B -#define pciBIF_CFG_EPVF8_nbif_gpu_DEVICE_CNTL_epvf_alt_8 0x001B -#define cfgBIF_CFG_EPVF8_nbif_gpu_DEVICE_CNTL_epvf_alt_8 0x001B -#define pciBIF_CFG_EPVF9_nbif_gpu_DEVICE_CNTL_epvf_alt_9 0x001B -#define cfgBIF_CFG_EPVF9_nbif_gpu_DEVICE_CNTL_epvf_alt_9 0x001B -#define pciBIF_CFG_EPVF10_nbif_gpu_DEVICE_CNTL_epvf_alt_10 0x001B -#define cfgBIF_CFG_EPVF10_nbif_gpu_DEVICE_CNTL_epvf_alt_10 0x001B -#define pciBIF_CFG_EPVF11_nbif_gpu_DEVICE_CNTL_epvf_alt_11 0x001B -#define cfgBIF_CFG_EPVF11_nbif_gpu_DEVICE_CNTL_epvf_alt_11 0x001B -#define pciBIF_CFG_EPVF12_nbif_gpu_DEVICE_CNTL_epvf_alt_12 0x001B -#define cfgBIF_CFG_EPVF12_nbif_gpu_DEVICE_CNTL_epvf_alt_12 0x001B -#define pciBIF_CFG_EPVF13_nbif_gpu_DEVICE_CNTL_epvf_alt_13 0x001B -#define cfgBIF_CFG_EPVF13_nbif_gpu_DEVICE_CNTL_epvf_alt_13 0x001B -#define pciBIF_CFG_EPVF14_nbif_gpu_DEVICE_CNTL_epvf_alt_14 0x001B -#define cfgBIF_CFG_EPVF14_nbif_gpu_DEVICE_CNTL_epvf_alt_14 0x001B -#define pciBIF_CFG_EPVF15_nbif_gpu_DEVICE_CNTL_epvf_alt_15 0x001B -#define cfgBIF_CFG_EPVF15_nbif_gpu_DEVICE_CNTL_epvf_alt_15 0x001B -#define pcinbif_gpu_DEVICE_STATUS_epvf 0x001B -#define cfgnbif_gpu_DEVICE_STATUS_epvf 0x001B -#define pciBIF_CFG_EPVF0_nbif_gpu_DEVICE_STATUS_epvf 0x001B -#define cfgBIF_CFG_EPVF0_nbif_gpu_DEVICE_STATUS_epvf 0x001B -#define pciBIF_CFG_EPVF1_nbif_gpu_DEVICE_STATUS_epvf_alt_1 0x001B -#define cfgBIF_CFG_EPVF1_nbif_gpu_DEVICE_STATUS_epvf_alt_1 0x001B -#define pciBIF_CFG_EPVF2_nbif_gpu_DEVICE_STATUS_epvf_alt_2 0x001B -#define cfgBIF_CFG_EPVF2_nbif_gpu_DEVICE_STATUS_epvf_alt_2 0x001B -#define pciBIF_CFG_EPVF3_nbif_gpu_DEVICE_STATUS_epvf_alt_3 0x001B -#define cfgBIF_CFG_EPVF3_nbif_gpu_DEVICE_STATUS_epvf_alt_3 0x001B -#define pciBIF_CFG_EPVF4_nbif_gpu_DEVICE_STATUS_epvf_alt_4 0x001B -#define cfgBIF_CFG_EPVF4_nbif_gpu_DEVICE_STATUS_epvf_alt_4 0x001B -#define pciBIF_CFG_EPVF5_nbif_gpu_DEVICE_STATUS_epvf_alt_5 0x001B -#define cfgBIF_CFG_EPVF5_nbif_gpu_DEVICE_STATUS_epvf_alt_5 0x001B -#define pciBIF_CFG_EPVF6_nbif_gpu_DEVICE_STATUS_epvf_alt_6 0x001B -#define cfgBIF_CFG_EPVF6_nbif_gpu_DEVICE_STATUS_epvf_alt_6 0x001B -#define pciBIF_CFG_EPVF7_nbif_gpu_DEVICE_STATUS_epvf_alt_7 0x001B -#define cfgBIF_CFG_EPVF7_nbif_gpu_DEVICE_STATUS_epvf_alt_7 0x001B -#define pciBIF_CFG_EPVF8_nbif_gpu_DEVICE_STATUS_epvf_alt_8 0x001B -#define cfgBIF_CFG_EPVF8_nbif_gpu_DEVICE_STATUS_epvf_alt_8 0x001B -#define pciBIF_CFG_EPVF9_nbif_gpu_DEVICE_STATUS_epvf_alt_9 0x001B -#define cfgBIF_CFG_EPVF9_nbif_gpu_DEVICE_STATUS_epvf_alt_9 0x001B -#define pciBIF_CFG_EPVF10_nbif_gpu_DEVICE_STATUS_epvf_alt_10 0x001B -#define cfgBIF_CFG_EPVF10_nbif_gpu_DEVICE_STATUS_epvf_alt_10 0x001B -#define pciBIF_CFG_EPVF11_nbif_gpu_DEVICE_STATUS_epvf_alt_11 0x001B -#define cfgBIF_CFG_EPVF11_nbif_gpu_DEVICE_STATUS_epvf_alt_11 0x001B -#define pciBIF_CFG_EPVF12_nbif_gpu_DEVICE_STATUS_epvf_alt_12 0x001B -#define cfgBIF_CFG_EPVF12_nbif_gpu_DEVICE_STATUS_epvf_alt_12 0x001B -#define pciBIF_CFG_EPVF13_nbif_gpu_DEVICE_STATUS_epvf_alt_13 0x001B -#define cfgBIF_CFG_EPVF13_nbif_gpu_DEVICE_STATUS_epvf_alt_13 0x001B -#define pciBIF_CFG_EPVF14_nbif_gpu_DEVICE_STATUS_epvf_alt_14 0x001B -#define cfgBIF_CFG_EPVF14_nbif_gpu_DEVICE_STATUS_epvf_alt_14 0x001B -#define pciBIF_CFG_EPVF15_nbif_gpu_DEVICE_STATUS_epvf_alt_15 0x001B -#define cfgBIF_CFG_EPVF15_nbif_gpu_DEVICE_STATUS_epvf_alt_15 0x001B -#define pcinbif_gpu_LINK_CAP_epvf 0x001C -#define cfgnbif_gpu_LINK_CAP_epvf 0x001C -#define pciBIF_CFG_EPVF0_nbif_gpu_LINK_CAP_epvf 0x001C -#define cfgBIF_CFG_EPVF0_nbif_gpu_LINK_CAP_epvf 0x001C -#define pciBIF_CFG_EPVF1_nbif_gpu_LINK_CAP_epvf_alt_1 0x001C -#define cfgBIF_CFG_EPVF1_nbif_gpu_LINK_CAP_epvf_alt_1 0x001C -#define pciBIF_CFG_EPVF2_nbif_gpu_LINK_CAP_epvf_alt_2 0x001C -#define cfgBIF_CFG_EPVF2_nbif_gpu_LINK_CAP_epvf_alt_2 0x001C -#define pciBIF_CFG_EPVF3_nbif_gpu_LINK_CAP_epvf_alt_3 0x001C -#define cfgBIF_CFG_EPVF3_nbif_gpu_LINK_CAP_epvf_alt_3 0x001C -#define pciBIF_CFG_EPVF4_nbif_gpu_LINK_CAP_epvf_alt_4 0x001C -#define cfgBIF_CFG_EPVF4_nbif_gpu_LINK_CAP_epvf_alt_4 0x001C -#define pciBIF_CFG_EPVF5_nbif_gpu_LINK_CAP_epvf_alt_5 0x001C -#define cfgBIF_CFG_EPVF5_nbif_gpu_LINK_CAP_epvf_alt_5 0x001C -#define pciBIF_CFG_EPVF6_nbif_gpu_LINK_CAP_epvf_alt_6 0x001C -#define cfgBIF_CFG_EPVF6_nbif_gpu_LINK_CAP_epvf_alt_6 0x001C -#define pciBIF_CFG_EPVF7_nbif_gpu_LINK_CAP_epvf_alt_7 0x001C -#define cfgBIF_CFG_EPVF7_nbif_gpu_LINK_CAP_epvf_alt_7 0x001C -#define pciBIF_CFG_EPVF8_nbif_gpu_LINK_CAP_epvf_alt_8 0x001C -#define cfgBIF_CFG_EPVF8_nbif_gpu_LINK_CAP_epvf_alt_8 0x001C -#define pciBIF_CFG_EPVF9_nbif_gpu_LINK_CAP_epvf_alt_9 0x001C -#define cfgBIF_CFG_EPVF9_nbif_gpu_LINK_CAP_epvf_alt_9 0x001C -#define pciBIF_CFG_EPVF10_nbif_gpu_LINK_CAP_epvf_alt_10 0x001C -#define cfgBIF_CFG_EPVF10_nbif_gpu_LINK_CAP_epvf_alt_10 0x001C -#define pciBIF_CFG_EPVF11_nbif_gpu_LINK_CAP_epvf_alt_11 0x001C -#define cfgBIF_CFG_EPVF11_nbif_gpu_LINK_CAP_epvf_alt_11 0x001C -#define pciBIF_CFG_EPVF12_nbif_gpu_LINK_CAP_epvf_alt_12 0x001C -#define cfgBIF_CFG_EPVF12_nbif_gpu_LINK_CAP_epvf_alt_12 0x001C -#define pciBIF_CFG_EPVF13_nbif_gpu_LINK_CAP_epvf_alt_13 0x001C -#define cfgBIF_CFG_EPVF13_nbif_gpu_LINK_CAP_epvf_alt_13 0x001C -#define pciBIF_CFG_EPVF14_nbif_gpu_LINK_CAP_epvf_alt_14 0x001C -#define cfgBIF_CFG_EPVF14_nbif_gpu_LINK_CAP_epvf_alt_14 0x001C -#define pciBIF_CFG_EPVF15_nbif_gpu_LINK_CAP_epvf_alt_15 0x001C -#define cfgBIF_CFG_EPVF15_nbif_gpu_LINK_CAP_epvf_alt_15 0x001C -#define pcinbif_gpu_LINK_CNTL_epvf 0x001D -#define cfgnbif_gpu_LINK_CNTL_epvf 0x001D -#define pciBIF_CFG_EPVF0_nbif_gpu_LINK_CNTL_epvf 0x001D -#define cfgBIF_CFG_EPVF0_nbif_gpu_LINK_CNTL_epvf 0x001D -#define pciBIF_CFG_EPVF1_nbif_gpu_LINK_CNTL_epvf_alt_1 0x001D -#define cfgBIF_CFG_EPVF1_nbif_gpu_LINK_CNTL_epvf_alt_1 0x001D -#define pciBIF_CFG_EPVF2_nbif_gpu_LINK_CNTL_epvf_alt_2 0x001D -#define cfgBIF_CFG_EPVF2_nbif_gpu_LINK_CNTL_epvf_alt_2 0x001D -#define pciBIF_CFG_EPVF3_nbif_gpu_LINK_CNTL_epvf_alt_3 0x001D -#define cfgBIF_CFG_EPVF3_nbif_gpu_LINK_CNTL_epvf_alt_3 0x001D -#define pciBIF_CFG_EPVF4_nbif_gpu_LINK_CNTL_epvf_alt_4 0x001D -#define cfgBIF_CFG_EPVF4_nbif_gpu_LINK_CNTL_epvf_alt_4 0x001D -#define pciBIF_CFG_EPVF5_nbif_gpu_LINK_CNTL_epvf_alt_5 0x001D -#define cfgBIF_CFG_EPVF5_nbif_gpu_LINK_CNTL_epvf_alt_5 0x001D -#define pciBIF_CFG_EPVF6_nbif_gpu_LINK_CNTL_epvf_alt_6 0x001D -#define cfgBIF_CFG_EPVF6_nbif_gpu_LINK_CNTL_epvf_alt_6 0x001D -#define pciBIF_CFG_EPVF7_nbif_gpu_LINK_CNTL_epvf_alt_7 0x001D -#define cfgBIF_CFG_EPVF7_nbif_gpu_LINK_CNTL_epvf_alt_7 0x001D -#define pciBIF_CFG_EPVF8_nbif_gpu_LINK_CNTL_epvf_alt_8 0x001D -#define cfgBIF_CFG_EPVF8_nbif_gpu_LINK_CNTL_epvf_alt_8 0x001D -#define pciBIF_CFG_EPVF9_nbif_gpu_LINK_CNTL_epvf_alt_9 0x001D -#define cfgBIF_CFG_EPVF9_nbif_gpu_LINK_CNTL_epvf_alt_9 0x001D -#define pciBIF_CFG_EPVF10_nbif_gpu_LINK_CNTL_epvf_alt_10 0x001D -#define cfgBIF_CFG_EPVF10_nbif_gpu_LINK_CNTL_epvf_alt_10 0x001D -#define pciBIF_CFG_EPVF11_nbif_gpu_LINK_CNTL_epvf_alt_11 0x001D -#define cfgBIF_CFG_EPVF11_nbif_gpu_LINK_CNTL_epvf_alt_11 0x001D -#define pciBIF_CFG_EPVF12_nbif_gpu_LINK_CNTL_epvf_alt_12 0x001D -#define cfgBIF_CFG_EPVF12_nbif_gpu_LINK_CNTL_epvf_alt_12 0x001D -#define pciBIF_CFG_EPVF13_nbif_gpu_LINK_CNTL_epvf_alt_13 0x001D -#define cfgBIF_CFG_EPVF13_nbif_gpu_LINK_CNTL_epvf_alt_13 0x001D -#define pciBIF_CFG_EPVF14_nbif_gpu_LINK_CNTL_epvf_alt_14 0x001D -#define cfgBIF_CFG_EPVF14_nbif_gpu_LINK_CNTL_epvf_alt_14 0x001D -#define pciBIF_CFG_EPVF15_nbif_gpu_LINK_CNTL_epvf_alt_15 0x001D -#define cfgBIF_CFG_EPVF15_nbif_gpu_LINK_CNTL_epvf_alt_15 0x001D -#define pcinbif_gpu_LINK_STATUS_epvf 0x001D -#define cfgnbif_gpu_LINK_STATUS_epvf 0x001D -#define pciBIF_CFG_EPVF0_nbif_gpu_LINK_STATUS_epvf 0x001D -#define cfgBIF_CFG_EPVF0_nbif_gpu_LINK_STATUS_epvf 0x001D -#define pciBIF_CFG_EPVF1_nbif_gpu_LINK_STATUS_epvf_alt_1 0x001D -#define cfgBIF_CFG_EPVF1_nbif_gpu_LINK_STATUS_epvf_alt_1 0x001D -#define pciBIF_CFG_EPVF2_nbif_gpu_LINK_STATUS_epvf_alt_2 0x001D -#define cfgBIF_CFG_EPVF2_nbif_gpu_LINK_STATUS_epvf_alt_2 0x001D -#define pciBIF_CFG_EPVF3_nbif_gpu_LINK_STATUS_epvf_alt_3 0x001D -#define cfgBIF_CFG_EPVF3_nbif_gpu_LINK_STATUS_epvf_alt_3 0x001D -#define pciBIF_CFG_EPVF4_nbif_gpu_LINK_STATUS_epvf_alt_4 0x001D -#define cfgBIF_CFG_EPVF4_nbif_gpu_LINK_STATUS_epvf_alt_4 0x001D -#define pciBIF_CFG_EPVF5_nbif_gpu_LINK_STATUS_epvf_alt_5 0x001D -#define cfgBIF_CFG_EPVF5_nbif_gpu_LINK_STATUS_epvf_alt_5 0x001D -#define pciBIF_CFG_EPVF6_nbif_gpu_LINK_STATUS_epvf_alt_6 0x001D -#define cfgBIF_CFG_EPVF6_nbif_gpu_LINK_STATUS_epvf_alt_6 0x001D -#define pciBIF_CFG_EPVF7_nbif_gpu_LINK_STATUS_epvf_alt_7 0x001D -#define cfgBIF_CFG_EPVF7_nbif_gpu_LINK_STATUS_epvf_alt_7 0x001D -#define pciBIF_CFG_EPVF8_nbif_gpu_LINK_STATUS_epvf_alt_8 0x001D -#define cfgBIF_CFG_EPVF8_nbif_gpu_LINK_STATUS_epvf_alt_8 0x001D -#define pciBIF_CFG_EPVF9_nbif_gpu_LINK_STATUS_epvf_alt_9 0x001D -#define cfgBIF_CFG_EPVF9_nbif_gpu_LINK_STATUS_epvf_alt_9 0x001D -#define pciBIF_CFG_EPVF10_nbif_gpu_LINK_STATUS_epvf_alt_10 0x001D -#define cfgBIF_CFG_EPVF10_nbif_gpu_LINK_STATUS_epvf_alt_10 0x001D -#define pciBIF_CFG_EPVF11_nbif_gpu_LINK_STATUS_epvf_alt_11 0x001D -#define cfgBIF_CFG_EPVF11_nbif_gpu_LINK_STATUS_epvf_alt_11 0x001D -#define pciBIF_CFG_EPVF12_nbif_gpu_LINK_STATUS_epvf_alt_12 0x001D -#define cfgBIF_CFG_EPVF12_nbif_gpu_LINK_STATUS_epvf_alt_12 0x001D -#define pciBIF_CFG_EPVF13_nbif_gpu_LINK_STATUS_epvf_alt_13 0x001D -#define cfgBIF_CFG_EPVF13_nbif_gpu_LINK_STATUS_epvf_alt_13 0x001D -#define pciBIF_CFG_EPVF14_nbif_gpu_LINK_STATUS_epvf_alt_14 0x001D -#define cfgBIF_CFG_EPVF14_nbif_gpu_LINK_STATUS_epvf_alt_14 0x001D -#define pciBIF_CFG_EPVF15_nbif_gpu_LINK_STATUS_epvf_alt_15 0x001D -#define cfgBIF_CFG_EPVF15_nbif_gpu_LINK_STATUS_epvf_alt_15 0x001D -#define pcinbif_gpu_DEVICE_CAP2_epvf 0x0022 -#define cfgnbif_gpu_DEVICE_CAP2_epvf 0x0022 -#define pciBIF_CFG_EPVF0_nbif_gpu_DEVICE_CAP2_epvf 0x0022 -#define cfgBIF_CFG_EPVF0_nbif_gpu_DEVICE_CAP2_epvf 0x0022 -#define pciBIF_CFG_EPVF1_nbif_gpu_DEVICE_CAP2_epvf_alt_1 0x0022 -#define cfgBIF_CFG_EPVF1_nbif_gpu_DEVICE_CAP2_epvf_alt_1 0x0022 -#define pciBIF_CFG_EPVF2_nbif_gpu_DEVICE_CAP2_epvf_alt_2 0x0022 -#define cfgBIF_CFG_EPVF2_nbif_gpu_DEVICE_CAP2_epvf_alt_2 0x0022 -#define pciBIF_CFG_EPVF3_nbif_gpu_DEVICE_CAP2_epvf_alt_3 0x0022 -#define cfgBIF_CFG_EPVF3_nbif_gpu_DEVICE_CAP2_epvf_alt_3 0x0022 -#define pciBIF_CFG_EPVF4_nbif_gpu_DEVICE_CAP2_epvf_alt_4 0x0022 -#define cfgBIF_CFG_EPVF4_nbif_gpu_DEVICE_CAP2_epvf_alt_4 0x0022 -#define pciBIF_CFG_EPVF5_nbif_gpu_DEVICE_CAP2_epvf_alt_5 0x0022 -#define cfgBIF_CFG_EPVF5_nbif_gpu_DEVICE_CAP2_epvf_alt_5 0x0022 -#define pciBIF_CFG_EPVF6_nbif_gpu_DEVICE_CAP2_epvf_alt_6 0x0022 -#define cfgBIF_CFG_EPVF6_nbif_gpu_DEVICE_CAP2_epvf_alt_6 0x0022 -#define pciBIF_CFG_EPVF7_nbif_gpu_DEVICE_CAP2_epvf_alt_7 0x0022 -#define cfgBIF_CFG_EPVF7_nbif_gpu_DEVICE_CAP2_epvf_alt_7 0x0022 -#define pciBIF_CFG_EPVF8_nbif_gpu_DEVICE_CAP2_epvf_alt_8 0x0022 -#define cfgBIF_CFG_EPVF8_nbif_gpu_DEVICE_CAP2_epvf_alt_8 0x0022 -#define pciBIF_CFG_EPVF9_nbif_gpu_DEVICE_CAP2_epvf_alt_9 0x0022 -#define cfgBIF_CFG_EPVF9_nbif_gpu_DEVICE_CAP2_epvf_alt_9 0x0022 -#define pciBIF_CFG_EPVF10_nbif_gpu_DEVICE_CAP2_epvf_alt_10 0x0022 -#define cfgBIF_CFG_EPVF10_nbif_gpu_DEVICE_CAP2_epvf_alt_10 0x0022 -#define pciBIF_CFG_EPVF11_nbif_gpu_DEVICE_CAP2_epvf_alt_11 0x0022 -#define cfgBIF_CFG_EPVF11_nbif_gpu_DEVICE_CAP2_epvf_alt_11 0x0022 -#define pciBIF_CFG_EPVF12_nbif_gpu_DEVICE_CAP2_epvf_alt_12 0x0022 -#define cfgBIF_CFG_EPVF12_nbif_gpu_DEVICE_CAP2_epvf_alt_12 0x0022 -#define pciBIF_CFG_EPVF13_nbif_gpu_DEVICE_CAP2_epvf_alt_13 0x0022 -#define cfgBIF_CFG_EPVF13_nbif_gpu_DEVICE_CAP2_epvf_alt_13 0x0022 -#define pciBIF_CFG_EPVF14_nbif_gpu_DEVICE_CAP2_epvf_alt_14 0x0022 -#define cfgBIF_CFG_EPVF14_nbif_gpu_DEVICE_CAP2_epvf_alt_14 0x0022 -#define pciBIF_CFG_EPVF15_nbif_gpu_DEVICE_CAP2_epvf_alt_15 0x0022 -#define cfgBIF_CFG_EPVF15_nbif_gpu_DEVICE_CAP2_epvf_alt_15 0x0022 -#define pcinbif_gpu_DEVICE_CNTL2_epvf 0x0023 -#define cfgnbif_gpu_DEVICE_CNTL2_epvf 0x0023 -#define pciBIF_CFG_EPVF0_nbif_gpu_DEVICE_CNTL2_epvf 0x0023 -#define cfgBIF_CFG_EPVF0_nbif_gpu_DEVICE_CNTL2_epvf 0x0023 -#define pciBIF_CFG_EPVF1_nbif_gpu_DEVICE_CNTL2_epvf_alt_1 0x0023 -#define cfgBIF_CFG_EPVF1_nbif_gpu_DEVICE_CNTL2_epvf_alt_1 0x0023 -#define pciBIF_CFG_EPVF2_nbif_gpu_DEVICE_CNTL2_epvf_alt_2 0x0023 -#define cfgBIF_CFG_EPVF2_nbif_gpu_DEVICE_CNTL2_epvf_alt_2 0x0023 -#define pciBIF_CFG_EPVF3_nbif_gpu_DEVICE_CNTL2_epvf_alt_3 0x0023 -#define cfgBIF_CFG_EPVF3_nbif_gpu_DEVICE_CNTL2_epvf_alt_3 0x0023 -#define pciBIF_CFG_EPVF4_nbif_gpu_DEVICE_CNTL2_epvf_alt_4 0x0023 -#define cfgBIF_CFG_EPVF4_nbif_gpu_DEVICE_CNTL2_epvf_alt_4 0x0023 -#define pciBIF_CFG_EPVF5_nbif_gpu_DEVICE_CNTL2_epvf_alt_5 0x0023 -#define cfgBIF_CFG_EPVF5_nbif_gpu_DEVICE_CNTL2_epvf_alt_5 0x0023 -#define pciBIF_CFG_EPVF6_nbif_gpu_DEVICE_CNTL2_epvf_alt_6 0x0023 -#define cfgBIF_CFG_EPVF6_nbif_gpu_DEVICE_CNTL2_epvf_alt_6 0x0023 -#define pciBIF_CFG_EPVF7_nbif_gpu_DEVICE_CNTL2_epvf_alt_7 0x0023 -#define cfgBIF_CFG_EPVF7_nbif_gpu_DEVICE_CNTL2_epvf_alt_7 0x0023 -#define pciBIF_CFG_EPVF8_nbif_gpu_DEVICE_CNTL2_epvf_alt_8 0x0023 -#define cfgBIF_CFG_EPVF8_nbif_gpu_DEVICE_CNTL2_epvf_alt_8 0x0023 -#define pciBIF_CFG_EPVF9_nbif_gpu_DEVICE_CNTL2_epvf_alt_9 0x0023 -#define cfgBIF_CFG_EPVF9_nbif_gpu_DEVICE_CNTL2_epvf_alt_9 0x0023 -#define pciBIF_CFG_EPVF10_nbif_gpu_DEVICE_CNTL2_epvf_alt_10 0x0023 -#define cfgBIF_CFG_EPVF10_nbif_gpu_DEVICE_CNTL2_epvf_alt_10 0x0023 -#define pciBIF_CFG_EPVF11_nbif_gpu_DEVICE_CNTL2_epvf_alt_11 0x0023 -#define cfgBIF_CFG_EPVF11_nbif_gpu_DEVICE_CNTL2_epvf_alt_11 0x0023 -#define pciBIF_CFG_EPVF12_nbif_gpu_DEVICE_CNTL2_epvf_alt_12 0x0023 -#define cfgBIF_CFG_EPVF12_nbif_gpu_DEVICE_CNTL2_epvf_alt_12 0x0023 -#define pciBIF_CFG_EPVF13_nbif_gpu_DEVICE_CNTL2_epvf_alt_13 0x0023 -#define cfgBIF_CFG_EPVF13_nbif_gpu_DEVICE_CNTL2_epvf_alt_13 0x0023 -#define pciBIF_CFG_EPVF14_nbif_gpu_DEVICE_CNTL2_epvf_alt_14 0x0023 -#define cfgBIF_CFG_EPVF14_nbif_gpu_DEVICE_CNTL2_epvf_alt_14 0x0023 -#define pciBIF_CFG_EPVF15_nbif_gpu_DEVICE_CNTL2_epvf_alt_15 0x0023 -#define cfgBIF_CFG_EPVF15_nbif_gpu_DEVICE_CNTL2_epvf_alt_15 0x0023 -#define pcinbif_gpu_DEVICE_STATUS2_epvf 0x0023 -#define cfgnbif_gpu_DEVICE_STATUS2_epvf 0x0023 -#define pciBIF_CFG_EPVF0_nbif_gpu_DEVICE_STATUS2_epvf 0x0023 -#define cfgBIF_CFG_EPVF0_nbif_gpu_DEVICE_STATUS2_epvf 0x0023 -#define pciBIF_CFG_EPVF1_nbif_gpu_DEVICE_STATUS2_epvf_alt_1 0x0023 -#define cfgBIF_CFG_EPVF1_nbif_gpu_DEVICE_STATUS2_epvf_alt_1 0x0023 -#define pciBIF_CFG_EPVF2_nbif_gpu_DEVICE_STATUS2_epvf_alt_2 0x0023 -#define cfgBIF_CFG_EPVF2_nbif_gpu_DEVICE_STATUS2_epvf_alt_2 0x0023 -#define pciBIF_CFG_EPVF3_nbif_gpu_DEVICE_STATUS2_epvf_alt_3 0x0023 -#define cfgBIF_CFG_EPVF3_nbif_gpu_DEVICE_STATUS2_epvf_alt_3 0x0023 -#define pciBIF_CFG_EPVF4_nbif_gpu_DEVICE_STATUS2_epvf_alt_4 0x0023 -#define cfgBIF_CFG_EPVF4_nbif_gpu_DEVICE_STATUS2_epvf_alt_4 0x0023 -#define pciBIF_CFG_EPVF5_nbif_gpu_DEVICE_STATUS2_epvf_alt_5 0x0023 -#define cfgBIF_CFG_EPVF5_nbif_gpu_DEVICE_STATUS2_epvf_alt_5 0x0023 -#define pciBIF_CFG_EPVF6_nbif_gpu_DEVICE_STATUS2_epvf_alt_6 0x0023 -#define cfgBIF_CFG_EPVF6_nbif_gpu_DEVICE_STATUS2_epvf_alt_6 0x0023 -#define pciBIF_CFG_EPVF7_nbif_gpu_DEVICE_STATUS2_epvf_alt_7 0x0023 -#define cfgBIF_CFG_EPVF7_nbif_gpu_DEVICE_STATUS2_epvf_alt_7 0x0023 -#define pciBIF_CFG_EPVF8_nbif_gpu_DEVICE_STATUS2_epvf_alt_8 0x0023 -#define cfgBIF_CFG_EPVF8_nbif_gpu_DEVICE_STATUS2_epvf_alt_8 0x0023 -#define pciBIF_CFG_EPVF9_nbif_gpu_DEVICE_STATUS2_epvf_alt_9 0x0023 -#define cfgBIF_CFG_EPVF9_nbif_gpu_DEVICE_STATUS2_epvf_alt_9 0x0023 -#define pciBIF_CFG_EPVF10_nbif_gpu_DEVICE_STATUS2_epvf_alt_10 0x0023 -#define cfgBIF_CFG_EPVF10_nbif_gpu_DEVICE_STATUS2_epvf_alt_10 0x0023 -#define pciBIF_CFG_EPVF11_nbif_gpu_DEVICE_STATUS2_epvf_alt_11 0x0023 -#define cfgBIF_CFG_EPVF11_nbif_gpu_DEVICE_STATUS2_epvf_alt_11 0x0023 -#define pciBIF_CFG_EPVF12_nbif_gpu_DEVICE_STATUS2_epvf_alt_12 0x0023 -#define cfgBIF_CFG_EPVF12_nbif_gpu_DEVICE_STATUS2_epvf_alt_12 0x0023 -#define pciBIF_CFG_EPVF13_nbif_gpu_DEVICE_STATUS2_epvf_alt_13 0x0023 -#define cfgBIF_CFG_EPVF13_nbif_gpu_DEVICE_STATUS2_epvf_alt_13 0x0023 -#define pciBIF_CFG_EPVF14_nbif_gpu_DEVICE_STATUS2_epvf_alt_14 0x0023 -#define cfgBIF_CFG_EPVF14_nbif_gpu_DEVICE_STATUS2_epvf_alt_14 0x0023 -#define pciBIF_CFG_EPVF15_nbif_gpu_DEVICE_STATUS2_epvf_alt_15 0x0023 -#define cfgBIF_CFG_EPVF15_nbif_gpu_DEVICE_STATUS2_epvf_alt_15 0x0023 -#define pcinbif_gpu_LINK_CAP2_epvf 0x0024 -#define cfgnbif_gpu_LINK_CAP2_epvf 0x0024 -#define pciBIF_CFG_EPVF0_nbif_gpu_LINK_CAP2_epvf 0x0024 -#define cfgBIF_CFG_EPVF0_nbif_gpu_LINK_CAP2_epvf 0x0024 -#define pciBIF_CFG_EPVF1_nbif_gpu_LINK_CAP2_epvf_alt_1 0x0024 -#define cfgBIF_CFG_EPVF1_nbif_gpu_LINK_CAP2_epvf_alt_1 0x0024 -#define pciBIF_CFG_EPVF2_nbif_gpu_LINK_CAP2_epvf_alt_2 0x0024 -#define cfgBIF_CFG_EPVF2_nbif_gpu_LINK_CAP2_epvf_alt_2 0x0024 -#define pciBIF_CFG_EPVF3_nbif_gpu_LINK_CAP2_epvf_alt_3 0x0024 -#define cfgBIF_CFG_EPVF3_nbif_gpu_LINK_CAP2_epvf_alt_3 0x0024 -#define pciBIF_CFG_EPVF4_nbif_gpu_LINK_CAP2_epvf_alt_4 0x0024 -#define cfgBIF_CFG_EPVF4_nbif_gpu_LINK_CAP2_epvf_alt_4 0x0024 -#define pciBIF_CFG_EPVF5_nbif_gpu_LINK_CAP2_epvf_alt_5 0x0024 -#define cfgBIF_CFG_EPVF5_nbif_gpu_LINK_CAP2_epvf_alt_5 0x0024 -#define pciBIF_CFG_EPVF6_nbif_gpu_LINK_CAP2_epvf_alt_6 0x0024 -#define cfgBIF_CFG_EPVF6_nbif_gpu_LINK_CAP2_epvf_alt_6 0x0024 -#define pciBIF_CFG_EPVF7_nbif_gpu_LINK_CAP2_epvf_alt_7 0x0024 -#define cfgBIF_CFG_EPVF7_nbif_gpu_LINK_CAP2_epvf_alt_7 0x0024 -#define pciBIF_CFG_EPVF8_nbif_gpu_LINK_CAP2_epvf_alt_8 0x0024 -#define cfgBIF_CFG_EPVF8_nbif_gpu_LINK_CAP2_epvf_alt_8 0x0024 -#define pciBIF_CFG_EPVF9_nbif_gpu_LINK_CAP2_epvf_alt_9 0x0024 -#define cfgBIF_CFG_EPVF9_nbif_gpu_LINK_CAP2_epvf_alt_9 0x0024 -#define pciBIF_CFG_EPVF10_nbif_gpu_LINK_CAP2_epvf_alt_10 0x0024 -#define cfgBIF_CFG_EPVF10_nbif_gpu_LINK_CAP2_epvf_alt_10 0x0024 -#define pciBIF_CFG_EPVF11_nbif_gpu_LINK_CAP2_epvf_alt_11 0x0024 -#define cfgBIF_CFG_EPVF11_nbif_gpu_LINK_CAP2_epvf_alt_11 0x0024 -#define pciBIF_CFG_EPVF12_nbif_gpu_LINK_CAP2_epvf_alt_12 0x0024 -#define cfgBIF_CFG_EPVF12_nbif_gpu_LINK_CAP2_epvf_alt_12 0x0024 -#define pciBIF_CFG_EPVF13_nbif_gpu_LINK_CAP2_epvf_alt_13 0x0024 -#define cfgBIF_CFG_EPVF13_nbif_gpu_LINK_CAP2_epvf_alt_13 0x0024 -#define pciBIF_CFG_EPVF14_nbif_gpu_LINK_CAP2_epvf_alt_14 0x0024 -#define cfgBIF_CFG_EPVF14_nbif_gpu_LINK_CAP2_epvf_alt_14 0x0024 -#define pciBIF_CFG_EPVF15_nbif_gpu_LINK_CAP2_epvf_alt_15 0x0024 -#define cfgBIF_CFG_EPVF15_nbif_gpu_LINK_CAP2_epvf_alt_15 0x0024 -#define pcinbif_gpu_LINK_CNTL2_epvf 0x0025 -#define cfgnbif_gpu_LINK_CNTL2_epvf 0x0025 -#define pciBIF_CFG_EPVF0_nbif_gpu_LINK_CNTL2_epvf 0x0025 -#define cfgBIF_CFG_EPVF0_nbif_gpu_LINK_CNTL2_epvf 0x0025 -#define pciBIF_CFG_EPVF1_nbif_gpu_LINK_CNTL2_epvf_alt_1 0x0025 -#define cfgBIF_CFG_EPVF1_nbif_gpu_LINK_CNTL2_epvf_alt_1 0x0025 -#define pciBIF_CFG_EPVF2_nbif_gpu_LINK_CNTL2_epvf_alt_2 0x0025 -#define cfgBIF_CFG_EPVF2_nbif_gpu_LINK_CNTL2_epvf_alt_2 0x0025 -#define pciBIF_CFG_EPVF3_nbif_gpu_LINK_CNTL2_epvf_alt_3 0x0025 -#define cfgBIF_CFG_EPVF3_nbif_gpu_LINK_CNTL2_epvf_alt_3 0x0025 -#define pciBIF_CFG_EPVF4_nbif_gpu_LINK_CNTL2_epvf_alt_4 0x0025 -#define cfgBIF_CFG_EPVF4_nbif_gpu_LINK_CNTL2_epvf_alt_4 0x0025 -#define pciBIF_CFG_EPVF5_nbif_gpu_LINK_CNTL2_epvf_alt_5 0x0025 -#define cfgBIF_CFG_EPVF5_nbif_gpu_LINK_CNTL2_epvf_alt_5 0x0025 -#define pciBIF_CFG_EPVF6_nbif_gpu_LINK_CNTL2_epvf_alt_6 0x0025 -#define cfgBIF_CFG_EPVF6_nbif_gpu_LINK_CNTL2_epvf_alt_6 0x0025 -#define pciBIF_CFG_EPVF7_nbif_gpu_LINK_CNTL2_epvf_alt_7 0x0025 -#define cfgBIF_CFG_EPVF7_nbif_gpu_LINK_CNTL2_epvf_alt_7 0x0025 -#define pciBIF_CFG_EPVF8_nbif_gpu_LINK_CNTL2_epvf_alt_8 0x0025 -#define cfgBIF_CFG_EPVF8_nbif_gpu_LINK_CNTL2_epvf_alt_8 0x0025 -#define pciBIF_CFG_EPVF9_nbif_gpu_LINK_CNTL2_epvf_alt_9 0x0025 -#define cfgBIF_CFG_EPVF9_nbif_gpu_LINK_CNTL2_epvf_alt_9 0x0025 -#define pciBIF_CFG_EPVF10_nbif_gpu_LINK_CNTL2_epvf_alt_10 0x0025 -#define cfgBIF_CFG_EPVF10_nbif_gpu_LINK_CNTL2_epvf_alt_10 0x0025 -#define pciBIF_CFG_EPVF11_nbif_gpu_LINK_CNTL2_epvf_alt_11 0x0025 -#define cfgBIF_CFG_EPVF11_nbif_gpu_LINK_CNTL2_epvf_alt_11 0x0025 -#define pciBIF_CFG_EPVF12_nbif_gpu_LINK_CNTL2_epvf_alt_12 0x0025 -#define cfgBIF_CFG_EPVF12_nbif_gpu_LINK_CNTL2_epvf_alt_12 0x0025 -#define pciBIF_CFG_EPVF13_nbif_gpu_LINK_CNTL2_epvf_alt_13 0x0025 -#define cfgBIF_CFG_EPVF13_nbif_gpu_LINK_CNTL2_epvf_alt_13 0x0025 -#define pciBIF_CFG_EPVF14_nbif_gpu_LINK_CNTL2_epvf_alt_14 0x0025 -#define cfgBIF_CFG_EPVF14_nbif_gpu_LINK_CNTL2_epvf_alt_14 0x0025 -#define pciBIF_CFG_EPVF15_nbif_gpu_LINK_CNTL2_epvf_alt_15 0x0025 -#define cfgBIF_CFG_EPVF15_nbif_gpu_LINK_CNTL2_epvf_alt_15 0x0025 -#define pcinbif_gpu_LINK_STATUS2_epvf 0x0025 -#define cfgnbif_gpu_LINK_STATUS2_epvf 0x0025 -#define pciBIF_CFG_EPVF0_nbif_gpu_LINK_STATUS2_epvf 0x0025 -#define cfgBIF_CFG_EPVF0_nbif_gpu_LINK_STATUS2_epvf 0x0025 -#define pciBIF_CFG_EPVF1_nbif_gpu_LINK_STATUS2_epvf_alt_1 0x0025 -#define cfgBIF_CFG_EPVF1_nbif_gpu_LINK_STATUS2_epvf_alt_1 0x0025 -#define pciBIF_CFG_EPVF2_nbif_gpu_LINK_STATUS2_epvf_alt_2 0x0025 -#define cfgBIF_CFG_EPVF2_nbif_gpu_LINK_STATUS2_epvf_alt_2 0x0025 -#define pciBIF_CFG_EPVF3_nbif_gpu_LINK_STATUS2_epvf_alt_3 0x0025 -#define cfgBIF_CFG_EPVF3_nbif_gpu_LINK_STATUS2_epvf_alt_3 0x0025 -#define pciBIF_CFG_EPVF4_nbif_gpu_LINK_STATUS2_epvf_alt_4 0x0025 -#define cfgBIF_CFG_EPVF4_nbif_gpu_LINK_STATUS2_epvf_alt_4 0x0025 -#define pciBIF_CFG_EPVF5_nbif_gpu_LINK_STATUS2_epvf_alt_5 0x0025 -#define cfgBIF_CFG_EPVF5_nbif_gpu_LINK_STATUS2_epvf_alt_5 0x0025 -#define pciBIF_CFG_EPVF6_nbif_gpu_LINK_STATUS2_epvf_alt_6 0x0025 -#define cfgBIF_CFG_EPVF6_nbif_gpu_LINK_STATUS2_epvf_alt_6 0x0025 -#define pciBIF_CFG_EPVF7_nbif_gpu_LINK_STATUS2_epvf_alt_7 0x0025 -#define cfgBIF_CFG_EPVF7_nbif_gpu_LINK_STATUS2_epvf_alt_7 0x0025 -#define pciBIF_CFG_EPVF8_nbif_gpu_LINK_STATUS2_epvf_alt_8 0x0025 -#define cfgBIF_CFG_EPVF8_nbif_gpu_LINK_STATUS2_epvf_alt_8 0x0025 -#define pciBIF_CFG_EPVF9_nbif_gpu_LINK_STATUS2_epvf_alt_9 0x0025 -#define cfgBIF_CFG_EPVF9_nbif_gpu_LINK_STATUS2_epvf_alt_9 0x0025 -#define pciBIF_CFG_EPVF10_nbif_gpu_LINK_STATUS2_epvf_alt_10 0x0025 -#define cfgBIF_CFG_EPVF10_nbif_gpu_LINK_STATUS2_epvf_alt_10 0x0025 -#define pciBIF_CFG_EPVF11_nbif_gpu_LINK_STATUS2_epvf_alt_11 0x0025 -#define cfgBIF_CFG_EPVF11_nbif_gpu_LINK_STATUS2_epvf_alt_11 0x0025 -#define pciBIF_CFG_EPVF12_nbif_gpu_LINK_STATUS2_epvf_alt_12 0x0025 -#define cfgBIF_CFG_EPVF12_nbif_gpu_LINK_STATUS2_epvf_alt_12 0x0025 -#define pciBIF_CFG_EPVF13_nbif_gpu_LINK_STATUS2_epvf_alt_13 0x0025 -#define cfgBIF_CFG_EPVF13_nbif_gpu_LINK_STATUS2_epvf_alt_13 0x0025 -#define pciBIF_CFG_EPVF14_nbif_gpu_LINK_STATUS2_epvf_alt_14 0x0025 -#define cfgBIF_CFG_EPVF14_nbif_gpu_LINK_STATUS2_epvf_alt_14 0x0025 -#define pciBIF_CFG_EPVF15_nbif_gpu_LINK_STATUS2_epvf_alt_15 0x0025 -#define cfgBIF_CFG_EPVF15_nbif_gpu_LINK_STATUS2_epvf_alt_15 0x0025 -#define pcinbif_gpu_SLOT_CAP2_epvf 0x0026 -#define cfgnbif_gpu_SLOT_CAP2_epvf 0x0026 -#define pciBIF_CFG_EPVF0_nbif_gpu_SLOT_CAP2_epvf 0x0026 -#define cfgBIF_CFG_EPVF0_nbif_gpu_SLOT_CAP2_epvf 0x0026 -#define pciBIF_CFG_EPVF1_nbif_gpu_SLOT_CAP2_epvf_alt_1 0x0026 -#define cfgBIF_CFG_EPVF1_nbif_gpu_SLOT_CAP2_epvf_alt_1 0x0026 -#define pciBIF_CFG_EPVF2_nbif_gpu_SLOT_CAP2_epvf_alt_2 0x0026 -#define cfgBIF_CFG_EPVF2_nbif_gpu_SLOT_CAP2_epvf_alt_2 0x0026 -#define pciBIF_CFG_EPVF3_nbif_gpu_SLOT_CAP2_epvf_alt_3 0x0026 -#define cfgBIF_CFG_EPVF3_nbif_gpu_SLOT_CAP2_epvf_alt_3 0x0026 -#define pciBIF_CFG_EPVF4_nbif_gpu_SLOT_CAP2_epvf_alt_4 0x0026 -#define cfgBIF_CFG_EPVF4_nbif_gpu_SLOT_CAP2_epvf_alt_4 0x0026 -#define pciBIF_CFG_EPVF5_nbif_gpu_SLOT_CAP2_epvf_alt_5 0x0026 -#define cfgBIF_CFG_EPVF5_nbif_gpu_SLOT_CAP2_epvf_alt_5 0x0026 -#define pciBIF_CFG_EPVF6_nbif_gpu_SLOT_CAP2_epvf_alt_6 0x0026 -#define cfgBIF_CFG_EPVF6_nbif_gpu_SLOT_CAP2_epvf_alt_6 0x0026 -#define pciBIF_CFG_EPVF7_nbif_gpu_SLOT_CAP2_epvf_alt_7 0x0026 -#define cfgBIF_CFG_EPVF7_nbif_gpu_SLOT_CAP2_epvf_alt_7 0x0026 -#define pciBIF_CFG_EPVF8_nbif_gpu_SLOT_CAP2_epvf_alt_8 0x0026 -#define cfgBIF_CFG_EPVF8_nbif_gpu_SLOT_CAP2_epvf_alt_8 0x0026 -#define pciBIF_CFG_EPVF9_nbif_gpu_SLOT_CAP2_epvf_alt_9 0x0026 -#define cfgBIF_CFG_EPVF9_nbif_gpu_SLOT_CAP2_epvf_alt_9 0x0026 -#define pciBIF_CFG_EPVF10_nbif_gpu_SLOT_CAP2_epvf_alt_10 0x0026 -#define cfgBIF_CFG_EPVF10_nbif_gpu_SLOT_CAP2_epvf_alt_10 0x0026 -#define pciBIF_CFG_EPVF11_nbif_gpu_SLOT_CAP2_epvf_alt_11 0x0026 -#define cfgBIF_CFG_EPVF11_nbif_gpu_SLOT_CAP2_epvf_alt_11 0x0026 -#define pciBIF_CFG_EPVF12_nbif_gpu_SLOT_CAP2_epvf_alt_12 0x0026 -#define cfgBIF_CFG_EPVF12_nbif_gpu_SLOT_CAP2_epvf_alt_12 0x0026 -#define pciBIF_CFG_EPVF13_nbif_gpu_SLOT_CAP2_epvf_alt_13 0x0026 -#define cfgBIF_CFG_EPVF13_nbif_gpu_SLOT_CAP2_epvf_alt_13 0x0026 -#define pciBIF_CFG_EPVF14_nbif_gpu_SLOT_CAP2_epvf_alt_14 0x0026 -#define cfgBIF_CFG_EPVF14_nbif_gpu_SLOT_CAP2_epvf_alt_14 0x0026 -#define pciBIF_CFG_EPVF15_nbif_gpu_SLOT_CAP2_epvf_alt_15 0x0026 -#define cfgBIF_CFG_EPVF15_nbif_gpu_SLOT_CAP2_epvf_alt_15 0x0026 -#define pcinbif_gpu_SLOT_CNTL2_epvf 0x0027 -#define cfgnbif_gpu_SLOT_CNTL2_epvf 0x0027 -#define pciBIF_CFG_EPVF0_nbif_gpu_SLOT_CNTL2_epvf 0x0027 -#define cfgBIF_CFG_EPVF0_nbif_gpu_SLOT_CNTL2_epvf 0x0027 -#define pciBIF_CFG_EPVF1_nbif_gpu_SLOT_CNTL2_epvf_alt_1 0x0027 -#define cfgBIF_CFG_EPVF1_nbif_gpu_SLOT_CNTL2_epvf_alt_1 0x0027 -#define pciBIF_CFG_EPVF2_nbif_gpu_SLOT_CNTL2_epvf_alt_2 0x0027 -#define cfgBIF_CFG_EPVF2_nbif_gpu_SLOT_CNTL2_epvf_alt_2 0x0027 -#define pciBIF_CFG_EPVF3_nbif_gpu_SLOT_CNTL2_epvf_alt_3 0x0027 -#define cfgBIF_CFG_EPVF3_nbif_gpu_SLOT_CNTL2_epvf_alt_3 0x0027 -#define pciBIF_CFG_EPVF4_nbif_gpu_SLOT_CNTL2_epvf_alt_4 0x0027 -#define cfgBIF_CFG_EPVF4_nbif_gpu_SLOT_CNTL2_epvf_alt_4 0x0027 -#define pciBIF_CFG_EPVF5_nbif_gpu_SLOT_CNTL2_epvf_alt_5 0x0027 -#define cfgBIF_CFG_EPVF5_nbif_gpu_SLOT_CNTL2_epvf_alt_5 0x0027 -#define pciBIF_CFG_EPVF6_nbif_gpu_SLOT_CNTL2_epvf_alt_6 0x0027 -#define cfgBIF_CFG_EPVF6_nbif_gpu_SLOT_CNTL2_epvf_alt_6 0x0027 -#define pciBIF_CFG_EPVF7_nbif_gpu_SLOT_CNTL2_epvf_alt_7 0x0027 -#define cfgBIF_CFG_EPVF7_nbif_gpu_SLOT_CNTL2_epvf_alt_7 0x0027 -#define pciBIF_CFG_EPVF8_nbif_gpu_SLOT_CNTL2_epvf_alt_8 0x0027 -#define cfgBIF_CFG_EPVF8_nbif_gpu_SLOT_CNTL2_epvf_alt_8 0x0027 -#define pciBIF_CFG_EPVF9_nbif_gpu_SLOT_CNTL2_epvf_alt_9 0x0027 -#define cfgBIF_CFG_EPVF9_nbif_gpu_SLOT_CNTL2_epvf_alt_9 0x0027 -#define pciBIF_CFG_EPVF10_nbif_gpu_SLOT_CNTL2_epvf_alt_10 0x0027 -#define cfgBIF_CFG_EPVF10_nbif_gpu_SLOT_CNTL2_epvf_alt_10 0x0027 -#define pciBIF_CFG_EPVF11_nbif_gpu_SLOT_CNTL2_epvf_alt_11 0x0027 -#define cfgBIF_CFG_EPVF11_nbif_gpu_SLOT_CNTL2_epvf_alt_11 0x0027 -#define pciBIF_CFG_EPVF12_nbif_gpu_SLOT_CNTL2_epvf_alt_12 0x0027 -#define cfgBIF_CFG_EPVF12_nbif_gpu_SLOT_CNTL2_epvf_alt_12 0x0027 -#define pciBIF_CFG_EPVF13_nbif_gpu_SLOT_CNTL2_epvf_alt_13 0x0027 -#define cfgBIF_CFG_EPVF13_nbif_gpu_SLOT_CNTL2_epvf_alt_13 0x0027 -#define pciBIF_CFG_EPVF14_nbif_gpu_SLOT_CNTL2_epvf_alt_14 0x0027 -#define cfgBIF_CFG_EPVF14_nbif_gpu_SLOT_CNTL2_epvf_alt_14 0x0027 -#define pciBIF_CFG_EPVF15_nbif_gpu_SLOT_CNTL2_epvf_alt_15 0x0027 -#define cfgBIF_CFG_EPVF15_nbif_gpu_SLOT_CNTL2_epvf_alt_15 0x0027 -#define pcinbif_gpu_SLOT_STATUS2_epvf 0x0027 -#define cfgnbif_gpu_SLOT_STATUS2_epvf 0x0027 -#define pciBIF_CFG_EPVF0_nbif_gpu_SLOT_STATUS2_epvf 0x0027 -#define cfgBIF_CFG_EPVF0_nbif_gpu_SLOT_STATUS2_epvf 0x0027 -#define pciBIF_CFG_EPVF1_nbif_gpu_SLOT_STATUS2_epvf_alt_1 0x0027 -#define cfgBIF_CFG_EPVF1_nbif_gpu_SLOT_STATUS2_epvf_alt_1 0x0027 -#define pciBIF_CFG_EPVF2_nbif_gpu_SLOT_STATUS2_epvf_alt_2 0x0027 -#define cfgBIF_CFG_EPVF2_nbif_gpu_SLOT_STATUS2_epvf_alt_2 0x0027 -#define pciBIF_CFG_EPVF3_nbif_gpu_SLOT_STATUS2_epvf_alt_3 0x0027 -#define cfgBIF_CFG_EPVF3_nbif_gpu_SLOT_STATUS2_epvf_alt_3 0x0027 -#define pciBIF_CFG_EPVF4_nbif_gpu_SLOT_STATUS2_epvf_alt_4 0x0027 -#define cfgBIF_CFG_EPVF4_nbif_gpu_SLOT_STATUS2_epvf_alt_4 0x0027 -#define pciBIF_CFG_EPVF5_nbif_gpu_SLOT_STATUS2_epvf_alt_5 0x0027 -#define cfgBIF_CFG_EPVF5_nbif_gpu_SLOT_STATUS2_epvf_alt_5 0x0027 -#define pciBIF_CFG_EPVF6_nbif_gpu_SLOT_STATUS2_epvf_alt_6 0x0027 -#define cfgBIF_CFG_EPVF6_nbif_gpu_SLOT_STATUS2_epvf_alt_6 0x0027 -#define pciBIF_CFG_EPVF7_nbif_gpu_SLOT_STATUS2_epvf_alt_7 0x0027 -#define cfgBIF_CFG_EPVF7_nbif_gpu_SLOT_STATUS2_epvf_alt_7 0x0027 -#define pciBIF_CFG_EPVF8_nbif_gpu_SLOT_STATUS2_epvf_alt_8 0x0027 -#define cfgBIF_CFG_EPVF8_nbif_gpu_SLOT_STATUS2_epvf_alt_8 0x0027 -#define pciBIF_CFG_EPVF9_nbif_gpu_SLOT_STATUS2_epvf_alt_9 0x0027 -#define cfgBIF_CFG_EPVF9_nbif_gpu_SLOT_STATUS2_epvf_alt_9 0x0027 -#define pciBIF_CFG_EPVF10_nbif_gpu_SLOT_STATUS2_epvf_alt_10 0x0027 -#define cfgBIF_CFG_EPVF10_nbif_gpu_SLOT_STATUS2_epvf_alt_10 0x0027 -#define pciBIF_CFG_EPVF11_nbif_gpu_SLOT_STATUS2_epvf_alt_11 0x0027 -#define cfgBIF_CFG_EPVF11_nbif_gpu_SLOT_STATUS2_epvf_alt_11 0x0027 -#define pciBIF_CFG_EPVF12_nbif_gpu_SLOT_STATUS2_epvf_alt_12 0x0027 -#define cfgBIF_CFG_EPVF12_nbif_gpu_SLOT_STATUS2_epvf_alt_12 0x0027 -#define pciBIF_CFG_EPVF13_nbif_gpu_SLOT_STATUS2_epvf_alt_13 0x0027 -#define cfgBIF_CFG_EPVF13_nbif_gpu_SLOT_STATUS2_epvf_alt_13 0x0027 -#define pciBIF_CFG_EPVF14_nbif_gpu_SLOT_STATUS2_epvf_alt_14 0x0027 -#define cfgBIF_CFG_EPVF14_nbif_gpu_SLOT_STATUS2_epvf_alt_14 0x0027 -#define pciBIF_CFG_EPVF15_nbif_gpu_SLOT_STATUS2_epvf_alt_15 0x0027 -#define cfgBIF_CFG_EPVF15_nbif_gpu_SLOT_STATUS2_epvf_alt_15 0x0027 -#define pcinbif_gpu_MSI_CAP_LIST_epvf 0x0028 -#define cfgnbif_gpu_MSI_CAP_LIST_epvf 0x0028 -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_CAP_LIST_epvf 0x0028 -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_CAP_LIST_epvf 0x0028 -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_CAP_LIST_epvf_alt_1 0x0028 -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_CAP_LIST_epvf_alt_1 0x0028 -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_CAP_LIST_epvf_alt_2 0x0028 -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_CAP_LIST_epvf_alt_2 0x0028 -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_CAP_LIST_epvf_alt_3 0x0028 -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_CAP_LIST_epvf_alt_3 0x0028 -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_CAP_LIST_epvf_alt_4 0x0028 -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_CAP_LIST_epvf_alt_4 0x0028 -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_CAP_LIST_epvf_alt_5 0x0028 -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_CAP_LIST_epvf_alt_5 0x0028 -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_CAP_LIST_epvf_alt_6 0x0028 -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_CAP_LIST_epvf_alt_6 0x0028 -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_CAP_LIST_epvf_alt_7 0x0028 -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_CAP_LIST_epvf_alt_7 0x0028 -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_CAP_LIST_epvf_alt_8 0x0028 -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_CAP_LIST_epvf_alt_8 0x0028 -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_CAP_LIST_epvf_alt_9 0x0028 -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_CAP_LIST_epvf_alt_9 0x0028 -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_CAP_LIST_epvf_alt_10 0x0028 -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_CAP_LIST_epvf_alt_10 0x0028 -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_CAP_LIST_epvf_alt_11 0x0028 -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_CAP_LIST_epvf_alt_11 0x0028 -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_CAP_LIST_epvf_alt_12 0x0028 -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_CAP_LIST_epvf_alt_12 0x0028 -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_CAP_LIST_epvf_alt_13 0x0028 -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_CAP_LIST_epvf_alt_13 0x0028 -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_CAP_LIST_epvf_alt_14 0x0028 -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_CAP_LIST_epvf_alt_14 0x0028 -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_CAP_LIST_epvf_alt_15 0x0028 -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_CAP_LIST_epvf_alt_15 0x0028 -#define pcinbif_gpu_MSI_MSG_CNTL_epvf 0x0028 -#define cfgnbif_gpu_MSI_MSG_CNTL_epvf 0x0028 -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_CNTL_epvf 0x0028 -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_CNTL_epvf 0x0028 -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_CNTL_epvf_alt_1 0x0028 -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_CNTL_epvf_alt_1 0x0028 -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_CNTL_epvf_alt_2 0x0028 -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_CNTL_epvf_alt_2 0x0028 -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_CNTL_epvf_alt_3 0x0028 -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_CNTL_epvf_alt_3 0x0028 -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_CNTL_epvf_alt_4 0x0028 -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_CNTL_epvf_alt_4 0x0028 -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_CNTL_epvf_alt_5 0x0028 -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_CNTL_epvf_alt_5 0x0028 -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_CNTL_epvf_alt_6 0x0028 -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_CNTL_epvf_alt_6 0x0028 -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_CNTL_epvf_alt_7 0x0028 -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_CNTL_epvf_alt_7 0x0028 -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_CNTL_epvf_alt_8 0x0028 -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_CNTL_epvf_alt_8 0x0028 -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_CNTL_epvf_alt_9 0x0028 -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_CNTL_epvf_alt_9 0x0028 -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_CNTL_epvf_alt_10 0x0028 -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_CNTL_epvf_alt_10 0x0028 -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_CNTL_epvf_alt_11 0x0028 -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_CNTL_epvf_alt_11 0x0028 -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_CNTL_epvf_alt_12 0x0028 -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_CNTL_epvf_alt_12 0x0028 -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_CNTL_epvf_alt_13 0x0028 -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_CNTL_epvf_alt_13 0x0028 -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_CNTL_epvf_alt_14 0x0028 -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_CNTL_epvf_alt_14 0x0028 -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_CNTL_epvf_alt_15 0x0028 -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_CNTL_epvf_alt_15 0x0028 -#define pcinbif_gpu_MSI_MSG_ADDR_LO_epvf 0x0029 -#define cfgnbif_gpu_MSI_MSG_ADDR_LO_epvf 0x0029 -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x0029 -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_ADDR_LO_epvf 0x0029 -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_1 0x0029 -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_1 0x0029 -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_2 0x0029 -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_2 0x0029 -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_3 0x0029 -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_3 0x0029 -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_4 0x0029 -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_4 0x0029 -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_5 0x0029 -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_5 0x0029 -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_6 0x0029 -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_6 0x0029 -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_7 0x0029 -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_7 0x0029 -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_8 0x0029 -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_8 0x0029 -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_9 0x0029 -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_9 0x0029 -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_10 0x0029 -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_10 0x0029 -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_11 0x0029 -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_11 0x0029 -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_12 0x0029 -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_12 0x0029 -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_13 0x0029 -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_13 0x0029 -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_14 0x0029 -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_14 0x0029 -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_15 0x0029 -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_ADDR_LO_epvf_alt_15 0x0029 -#define pcinbif_gpu_MSI_MSG_ADDR_HI_epvf 0x002A -#define cfgnbif_gpu_MSI_MSG_ADDR_HI_epvf 0x002A -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x002A -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_ADDR_HI_epvf 0x002A -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_1 0x002A -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_1 0x002A -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_2 0x002A -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_2 0x002A -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_3 0x002A -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_3 0x002A -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_4 0x002A -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_4 0x002A -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_5 0x002A -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_5 0x002A -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_6 0x002A -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_6 0x002A -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_7 0x002A -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_7 0x002A -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_8 0x002A -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_8 0x002A -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_9 0x002A -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_9 0x002A -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_10 0x002A -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_10 0x002A -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_11 0x002A -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_11 0x002A -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_12 0x002A -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_12 0x002A -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_13 0x002A -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_13 0x002A -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_14 0x002A -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_14 0x002A -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_15 0x002A -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_ADDR_HI_epvf_alt_15 0x002A -#define pcinbif_gpu_MSI_MSG_DATA_64_epvf 0x002B -#define cfgnbif_gpu_MSI_MSG_DATA_64_epvf 0x002B -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_DATA_64_epvf 0x002B -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_DATA_64_epvf 0x002B -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_1 0x002B -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_1 0x002B -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_2 0x002B -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_2 0x002B -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_3 0x002B -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_3 0x002B -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_4 0x002B -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_4 0x002B -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_5 0x002B -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_5 0x002B -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_6 0x002B -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_6 0x002B -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_7 0x002B -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_7 0x002B -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_8 0x002B -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_8 0x002B -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_9 0x002B -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_9 0x002B -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_10 0x002B -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_10 0x002B -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_11 0x002B -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_11 0x002B -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_12 0x002B -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_12 0x002B -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_13 0x002B -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_13 0x002B -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_14 0x002B -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_14 0x002B -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_15 0x002B -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_DATA_64_epvf_alt_15 0x002B -#define pcinbif_gpu_MSI_MSG_DATA_epvf 0x002A -#define cfgnbif_gpu_MSI_MSG_DATA_epvf 0x002A -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_DATA_epvf 0x002A -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_MSG_DATA_epvf 0x002A -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_DATA_epvf_alt_1 0x002A -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_MSG_DATA_epvf_alt_1 0x002A -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_DATA_epvf_alt_2 0x002A -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_MSG_DATA_epvf_alt_2 0x002A -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_DATA_epvf_alt_3 0x002A -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_MSG_DATA_epvf_alt_3 0x002A -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_DATA_epvf_alt_4 0x002A -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_MSG_DATA_epvf_alt_4 0x002A -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_DATA_epvf_alt_5 0x002A -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_MSG_DATA_epvf_alt_5 0x002A -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_DATA_epvf_alt_6 0x002A -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_MSG_DATA_epvf_alt_6 0x002A -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_DATA_epvf_alt_7 0x002A -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_MSG_DATA_epvf_alt_7 0x002A -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_DATA_epvf_alt_8 0x002A -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_MSG_DATA_epvf_alt_8 0x002A -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_DATA_epvf_alt_9 0x002A -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_MSG_DATA_epvf_alt_9 0x002A -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_DATA_epvf_alt_10 0x002A -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_MSG_DATA_epvf_alt_10 0x002A -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_DATA_epvf_alt_11 0x002A -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_MSG_DATA_epvf_alt_11 0x002A -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_DATA_epvf_alt_12 0x002A -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_MSG_DATA_epvf_alt_12 0x002A -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_DATA_epvf_alt_13 0x002A -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_MSG_DATA_epvf_alt_13 0x002A -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_DATA_epvf_alt_14 0x002A -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_MSG_DATA_epvf_alt_14 0x002A -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_DATA_epvf_alt_15 0x002A -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_MSG_DATA_epvf_alt_15 0x002A -#define pcinbif_gpu_MSI_MASK_epvf 0x002B -#define cfgnbif_gpu_MSI_MASK_epvf 0x002B -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_MASK_epvf 0x002B -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_MASK_epvf 0x002B -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_MASK_epvf_alt_1 0x002B -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_MASK_epvf_alt_1 0x002B -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_MASK_epvf_alt_2 0x002B -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_MASK_epvf_alt_2 0x002B -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_MASK_epvf_alt_3 0x002B -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_MASK_epvf_alt_3 0x002B -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_MASK_epvf_alt_4 0x002B -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_MASK_epvf_alt_4 0x002B -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_MASK_epvf_alt_5 0x002B -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_MASK_epvf_alt_5 0x002B -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_MASK_epvf_alt_6 0x002B -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_MASK_epvf_alt_6 0x002B -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_MASK_epvf_alt_7 0x002B -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_MASK_epvf_alt_7 0x002B -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_MASK_epvf_alt_8 0x002B -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_MASK_epvf_alt_8 0x002B -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_MASK_epvf_alt_9 0x002B -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_MASK_epvf_alt_9 0x002B -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_MASK_epvf_alt_10 0x002B -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_MASK_epvf_alt_10 0x002B -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_MASK_epvf_alt_11 0x002B -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_MASK_epvf_alt_11 0x002B -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_MASK_epvf_alt_12 0x002B -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_MASK_epvf_alt_12 0x002B -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_MASK_epvf_alt_13 0x002B -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_MASK_epvf_alt_13 0x002B -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_MASK_epvf_alt_14 0x002B -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_MASK_epvf_alt_14 0x002B -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_MASK_epvf_alt_15 0x002B -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_MASK_epvf_alt_15 0x002B -#define pcinbif_gpu_MSI_PENDING_epvf 0x002C -#define cfgnbif_gpu_MSI_PENDING_epvf 0x002C -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_PENDING_epvf 0x002C -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_PENDING_epvf 0x002C -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_PENDING_epvf_alt_1 0x002C -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_PENDING_epvf_alt_1 0x002C -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_PENDING_epvf_alt_2 0x002C -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_PENDING_epvf_alt_2 0x002C -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_PENDING_epvf_alt_3 0x002C -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_PENDING_epvf_alt_3 0x002C -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_PENDING_epvf_alt_4 0x002C -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_PENDING_epvf_alt_4 0x002C -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_PENDING_epvf_alt_5 0x002C -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_PENDING_epvf_alt_5 0x002C -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_PENDING_epvf_alt_6 0x002C -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_PENDING_epvf_alt_6 0x002C -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_PENDING_epvf_alt_7 0x002C -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_PENDING_epvf_alt_7 0x002C -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_PENDING_epvf_alt_8 0x002C -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_PENDING_epvf_alt_8 0x002C -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_PENDING_epvf_alt_9 0x002C -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_PENDING_epvf_alt_9 0x002C -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_PENDING_epvf_alt_10 0x002C -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_PENDING_epvf_alt_10 0x002C -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_PENDING_epvf_alt_11 0x002C -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_PENDING_epvf_alt_11 0x002C -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_PENDING_epvf_alt_12 0x002C -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_PENDING_epvf_alt_12 0x002C -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_PENDING_epvf_alt_13 0x002C -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_PENDING_epvf_alt_13 0x002C -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_PENDING_epvf_alt_14 0x002C -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_PENDING_epvf_alt_14 0x002C -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_PENDING_epvf_alt_15 0x002C -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_PENDING_epvf_alt_15 0x002C -#define pcinbif_gpu_MSI_MASK_64_epvf 0x002C -#define cfgnbif_gpu_MSI_MASK_64_epvf 0x002C -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_MASK_64_epvf 0x002C -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_MASK_64_epvf 0x002C -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_MASK_64_epvf_alt_1 0x002C -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_MASK_64_epvf_alt_1 0x002C -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_MASK_64_epvf_alt_2 0x002C -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_MASK_64_epvf_alt_2 0x002C -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_MASK_64_epvf_alt_3 0x002C -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_MASK_64_epvf_alt_3 0x002C -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_MASK_64_epvf_alt_4 0x002C -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_MASK_64_epvf_alt_4 0x002C -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_MASK_64_epvf_alt_5 0x002C -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_MASK_64_epvf_alt_5 0x002C -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_MASK_64_epvf_alt_6 0x002C -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_MASK_64_epvf_alt_6 0x002C -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_MASK_64_epvf_alt_7 0x002C -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_MASK_64_epvf_alt_7 0x002C -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_MASK_64_epvf_alt_8 0x002C -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_MASK_64_epvf_alt_8 0x002C -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_MASK_64_epvf_alt_9 0x002C -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_MASK_64_epvf_alt_9 0x002C -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_MASK_64_epvf_alt_10 0x002C -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_MASK_64_epvf_alt_10 0x002C -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_MASK_64_epvf_alt_11 0x002C -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_MASK_64_epvf_alt_11 0x002C -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_MASK_64_epvf_alt_12 0x002C -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_MASK_64_epvf_alt_12 0x002C -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_MASK_64_epvf_alt_13 0x002C -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_MASK_64_epvf_alt_13 0x002C -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_MASK_64_epvf_alt_14 0x002C -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_MASK_64_epvf_alt_14 0x002C -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_MASK_64_epvf_alt_15 0x002C -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_MASK_64_epvf_alt_15 0x002C -#define pcinbif_gpu_MSI_PENDING_64_epvf 0x002D -#define cfgnbif_gpu_MSI_PENDING_64_epvf 0x002D -#define pciBIF_CFG_EPVF0_nbif_gpu_MSI_PENDING_64_epvf 0x002D -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSI_PENDING_64_epvf 0x002D -#define pciBIF_CFG_EPVF1_nbif_gpu_MSI_PENDING_64_epvf_alt_1 0x002D -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSI_PENDING_64_epvf_alt_1 0x002D -#define pciBIF_CFG_EPVF2_nbif_gpu_MSI_PENDING_64_epvf_alt_2 0x002D -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSI_PENDING_64_epvf_alt_2 0x002D -#define pciBIF_CFG_EPVF3_nbif_gpu_MSI_PENDING_64_epvf_alt_3 0x002D -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSI_PENDING_64_epvf_alt_3 0x002D -#define pciBIF_CFG_EPVF4_nbif_gpu_MSI_PENDING_64_epvf_alt_4 0x002D -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSI_PENDING_64_epvf_alt_4 0x002D -#define pciBIF_CFG_EPVF5_nbif_gpu_MSI_PENDING_64_epvf_alt_5 0x002D -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSI_PENDING_64_epvf_alt_5 0x002D -#define pciBIF_CFG_EPVF6_nbif_gpu_MSI_PENDING_64_epvf_alt_6 0x002D -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSI_PENDING_64_epvf_alt_6 0x002D -#define pciBIF_CFG_EPVF7_nbif_gpu_MSI_PENDING_64_epvf_alt_7 0x002D -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSI_PENDING_64_epvf_alt_7 0x002D -#define pciBIF_CFG_EPVF8_nbif_gpu_MSI_PENDING_64_epvf_alt_8 0x002D -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSI_PENDING_64_epvf_alt_8 0x002D -#define pciBIF_CFG_EPVF9_nbif_gpu_MSI_PENDING_64_epvf_alt_9 0x002D -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSI_PENDING_64_epvf_alt_9 0x002D -#define pciBIF_CFG_EPVF10_nbif_gpu_MSI_PENDING_64_epvf_alt_10 0x002D -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSI_PENDING_64_epvf_alt_10 0x002D -#define pciBIF_CFG_EPVF11_nbif_gpu_MSI_PENDING_64_epvf_alt_11 0x002D -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSI_PENDING_64_epvf_alt_11 0x002D -#define pciBIF_CFG_EPVF12_nbif_gpu_MSI_PENDING_64_epvf_alt_12 0x002D -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSI_PENDING_64_epvf_alt_12 0x002D -#define pciBIF_CFG_EPVF13_nbif_gpu_MSI_PENDING_64_epvf_alt_13 0x002D -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSI_PENDING_64_epvf_alt_13 0x002D -#define pciBIF_CFG_EPVF14_nbif_gpu_MSI_PENDING_64_epvf_alt_14 0x002D -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSI_PENDING_64_epvf_alt_14 0x002D -#define pciBIF_CFG_EPVF15_nbif_gpu_MSI_PENDING_64_epvf_alt_15 0x002D -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSI_PENDING_64_epvf_alt_15 0x002D -#define pcinbif_gpu_MSIX_CAP_LIST_epvf 0x0030 -#define cfgnbif_gpu_MSIX_CAP_LIST_epvf 0x0030 -#define pciBIF_CFG_EPVF0_nbif_gpu_MSIX_CAP_LIST_epvf 0x0030 -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSIX_CAP_LIST_epvf 0x0030 -#define pciBIF_CFG_EPVF1_nbif_gpu_MSIX_CAP_LIST_epvf_alt_1 0x0030 -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSIX_CAP_LIST_epvf_alt_1 0x0030 -#define pciBIF_CFG_EPVF2_nbif_gpu_MSIX_CAP_LIST_epvf_alt_2 0x0030 -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSIX_CAP_LIST_epvf_alt_2 0x0030 -#define pciBIF_CFG_EPVF3_nbif_gpu_MSIX_CAP_LIST_epvf_alt_3 0x0030 -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSIX_CAP_LIST_epvf_alt_3 0x0030 -#define pciBIF_CFG_EPVF4_nbif_gpu_MSIX_CAP_LIST_epvf_alt_4 0x0030 -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSIX_CAP_LIST_epvf_alt_4 0x0030 -#define pciBIF_CFG_EPVF5_nbif_gpu_MSIX_CAP_LIST_epvf_alt_5 0x0030 -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSIX_CAP_LIST_epvf_alt_5 0x0030 -#define pciBIF_CFG_EPVF6_nbif_gpu_MSIX_CAP_LIST_epvf_alt_6 0x0030 -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSIX_CAP_LIST_epvf_alt_6 0x0030 -#define pciBIF_CFG_EPVF7_nbif_gpu_MSIX_CAP_LIST_epvf_alt_7 0x0030 -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSIX_CAP_LIST_epvf_alt_7 0x0030 -#define pciBIF_CFG_EPVF8_nbif_gpu_MSIX_CAP_LIST_epvf_alt_8 0x0030 -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSIX_CAP_LIST_epvf_alt_8 0x0030 -#define pciBIF_CFG_EPVF9_nbif_gpu_MSIX_CAP_LIST_epvf_alt_9 0x0030 -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSIX_CAP_LIST_epvf_alt_9 0x0030 -#define pciBIF_CFG_EPVF10_nbif_gpu_MSIX_CAP_LIST_epvf_alt_10 0x0030 -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSIX_CAP_LIST_epvf_alt_10 0x0030 -#define pciBIF_CFG_EPVF11_nbif_gpu_MSIX_CAP_LIST_epvf_alt_11 0x0030 -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSIX_CAP_LIST_epvf_alt_11 0x0030 -#define pciBIF_CFG_EPVF12_nbif_gpu_MSIX_CAP_LIST_epvf_alt_12 0x0030 -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSIX_CAP_LIST_epvf_alt_12 0x0030 -#define pciBIF_CFG_EPVF13_nbif_gpu_MSIX_CAP_LIST_epvf_alt_13 0x0030 -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSIX_CAP_LIST_epvf_alt_13 0x0030 -#define pciBIF_CFG_EPVF14_nbif_gpu_MSIX_CAP_LIST_epvf_alt_14 0x0030 -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSIX_CAP_LIST_epvf_alt_14 0x0030 -#define pciBIF_CFG_EPVF15_nbif_gpu_MSIX_CAP_LIST_epvf_alt_15 0x0030 -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSIX_CAP_LIST_epvf_alt_15 0x0030 -#define pcinbif_gpu_MSIX_MSG_CNTL_epvf 0x0030 -#define cfgnbif_gpu_MSIX_MSG_CNTL_epvf 0x0030 -#define pciBIF_CFG_EPVF0_nbif_gpu_MSIX_MSG_CNTL_epvf 0x0030 -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSIX_MSG_CNTL_epvf 0x0030 -#define pciBIF_CFG_EPVF1_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_1 0x0030 -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_1 0x0030 -#define pciBIF_CFG_EPVF2_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_2 0x0030 -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_2 0x0030 -#define pciBIF_CFG_EPVF3_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_3 0x0030 -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_3 0x0030 -#define pciBIF_CFG_EPVF4_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_4 0x0030 -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_4 0x0030 -#define pciBIF_CFG_EPVF5_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_5 0x0030 -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_5 0x0030 -#define pciBIF_CFG_EPVF6_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_6 0x0030 -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_6 0x0030 -#define pciBIF_CFG_EPVF7_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_7 0x0030 -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_7 0x0030 -#define pciBIF_CFG_EPVF8_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_8 0x0030 -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_8 0x0030 -#define pciBIF_CFG_EPVF9_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_9 0x0030 -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_9 0x0030 -#define pciBIF_CFG_EPVF10_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_10 0x0030 -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_10 0x0030 -#define pciBIF_CFG_EPVF11_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_11 0x0030 -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_11 0x0030 -#define pciBIF_CFG_EPVF12_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_12 0x0030 -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_12 0x0030 -#define pciBIF_CFG_EPVF13_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_13 0x0030 -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_13 0x0030 -#define pciBIF_CFG_EPVF14_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_14 0x0030 -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_14 0x0030 -#define pciBIF_CFG_EPVF15_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_15 0x0030 -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSIX_MSG_CNTL_epvf_alt_15 0x0030 -#define pcinbif_gpu_MSIX_TABLE_epvf 0x0031 -#define cfgnbif_gpu_MSIX_TABLE_epvf 0x0031 -#define pciBIF_CFG_EPVF0_nbif_gpu_MSIX_TABLE_epvf 0x0031 -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSIX_TABLE_epvf 0x0031 -#define pciBIF_CFG_EPVF1_nbif_gpu_MSIX_TABLE_epvf_alt_1 0x0031 -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSIX_TABLE_epvf_alt_1 0x0031 -#define pciBIF_CFG_EPVF2_nbif_gpu_MSIX_TABLE_epvf_alt_2 0x0031 -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSIX_TABLE_epvf_alt_2 0x0031 -#define pciBIF_CFG_EPVF3_nbif_gpu_MSIX_TABLE_epvf_alt_3 0x0031 -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSIX_TABLE_epvf_alt_3 0x0031 -#define pciBIF_CFG_EPVF4_nbif_gpu_MSIX_TABLE_epvf_alt_4 0x0031 -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSIX_TABLE_epvf_alt_4 0x0031 -#define pciBIF_CFG_EPVF5_nbif_gpu_MSIX_TABLE_epvf_alt_5 0x0031 -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSIX_TABLE_epvf_alt_5 0x0031 -#define pciBIF_CFG_EPVF6_nbif_gpu_MSIX_TABLE_epvf_alt_6 0x0031 -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSIX_TABLE_epvf_alt_6 0x0031 -#define pciBIF_CFG_EPVF7_nbif_gpu_MSIX_TABLE_epvf_alt_7 0x0031 -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSIX_TABLE_epvf_alt_7 0x0031 -#define pciBIF_CFG_EPVF8_nbif_gpu_MSIX_TABLE_epvf_alt_8 0x0031 -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSIX_TABLE_epvf_alt_8 0x0031 -#define pciBIF_CFG_EPVF9_nbif_gpu_MSIX_TABLE_epvf_alt_9 0x0031 -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSIX_TABLE_epvf_alt_9 0x0031 -#define pciBIF_CFG_EPVF10_nbif_gpu_MSIX_TABLE_epvf_alt_10 0x0031 -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSIX_TABLE_epvf_alt_10 0x0031 -#define pciBIF_CFG_EPVF11_nbif_gpu_MSIX_TABLE_epvf_alt_11 0x0031 -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSIX_TABLE_epvf_alt_11 0x0031 -#define pciBIF_CFG_EPVF12_nbif_gpu_MSIX_TABLE_epvf_alt_12 0x0031 -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSIX_TABLE_epvf_alt_12 0x0031 -#define pciBIF_CFG_EPVF13_nbif_gpu_MSIX_TABLE_epvf_alt_13 0x0031 -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSIX_TABLE_epvf_alt_13 0x0031 -#define pciBIF_CFG_EPVF14_nbif_gpu_MSIX_TABLE_epvf_alt_14 0x0031 -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSIX_TABLE_epvf_alt_14 0x0031 -#define pciBIF_CFG_EPVF15_nbif_gpu_MSIX_TABLE_epvf_alt_15 0x0031 -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSIX_TABLE_epvf_alt_15 0x0031 -#define pcinbif_gpu_MSIX_PBA_epvf 0x0032 -#define cfgnbif_gpu_MSIX_PBA_epvf 0x0032 -#define pciBIF_CFG_EPVF0_nbif_gpu_MSIX_PBA_epvf 0x0032 -#define cfgBIF_CFG_EPVF0_nbif_gpu_MSIX_PBA_epvf 0x0032 -#define pciBIF_CFG_EPVF1_nbif_gpu_MSIX_PBA_epvf_alt_1 0x0032 -#define cfgBIF_CFG_EPVF1_nbif_gpu_MSIX_PBA_epvf_alt_1 0x0032 -#define pciBIF_CFG_EPVF2_nbif_gpu_MSIX_PBA_epvf_alt_2 0x0032 -#define cfgBIF_CFG_EPVF2_nbif_gpu_MSIX_PBA_epvf_alt_2 0x0032 -#define pciBIF_CFG_EPVF3_nbif_gpu_MSIX_PBA_epvf_alt_3 0x0032 -#define cfgBIF_CFG_EPVF3_nbif_gpu_MSIX_PBA_epvf_alt_3 0x0032 -#define pciBIF_CFG_EPVF4_nbif_gpu_MSIX_PBA_epvf_alt_4 0x0032 -#define cfgBIF_CFG_EPVF4_nbif_gpu_MSIX_PBA_epvf_alt_4 0x0032 -#define pciBIF_CFG_EPVF5_nbif_gpu_MSIX_PBA_epvf_alt_5 0x0032 -#define cfgBIF_CFG_EPVF5_nbif_gpu_MSIX_PBA_epvf_alt_5 0x0032 -#define pciBIF_CFG_EPVF6_nbif_gpu_MSIX_PBA_epvf_alt_6 0x0032 -#define cfgBIF_CFG_EPVF6_nbif_gpu_MSIX_PBA_epvf_alt_6 0x0032 -#define pciBIF_CFG_EPVF7_nbif_gpu_MSIX_PBA_epvf_alt_7 0x0032 -#define cfgBIF_CFG_EPVF7_nbif_gpu_MSIX_PBA_epvf_alt_7 0x0032 -#define pciBIF_CFG_EPVF8_nbif_gpu_MSIX_PBA_epvf_alt_8 0x0032 -#define cfgBIF_CFG_EPVF8_nbif_gpu_MSIX_PBA_epvf_alt_8 0x0032 -#define pciBIF_CFG_EPVF9_nbif_gpu_MSIX_PBA_epvf_alt_9 0x0032 -#define cfgBIF_CFG_EPVF9_nbif_gpu_MSIX_PBA_epvf_alt_9 0x0032 -#define pciBIF_CFG_EPVF10_nbif_gpu_MSIX_PBA_epvf_alt_10 0x0032 -#define cfgBIF_CFG_EPVF10_nbif_gpu_MSIX_PBA_epvf_alt_10 0x0032 -#define pciBIF_CFG_EPVF11_nbif_gpu_MSIX_PBA_epvf_alt_11 0x0032 -#define cfgBIF_CFG_EPVF11_nbif_gpu_MSIX_PBA_epvf_alt_11 0x0032 -#define pciBIF_CFG_EPVF12_nbif_gpu_MSIX_PBA_epvf_alt_12 0x0032 -#define cfgBIF_CFG_EPVF12_nbif_gpu_MSIX_PBA_epvf_alt_12 0x0032 -#define pciBIF_CFG_EPVF13_nbif_gpu_MSIX_PBA_epvf_alt_13 0x0032 -#define cfgBIF_CFG_EPVF13_nbif_gpu_MSIX_PBA_epvf_alt_13 0x0032 -#define pciBIF_CFG_EPVF14_nbif_gpu_MSIX_PBA_epvf_alt_14 0x0032 -#define cfgBIF_CFG_EPVF14_nbif_gpu_MSIX_PBA_epvf_alt_14 0x0032 -#define pciBIF_CFG_EPVF15_nbif_gpu_MSIX_PBA_epvf_alt_15 0x0032 -#define cfgBIF_CFG_EPVF15_nbif_gpu_MSIX_PBA_epvf_alt_15 0x0032 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x0040 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x0040 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x0040 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf 0x0040 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_1 0x0040 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_1 0x0040 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_2 0x0040 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_2 0x0040 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_3 0x0040 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_3 0x0040 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_4 0x0040 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_4 0x0040 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_5 0x0040 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_5 0x0040 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_6 0x0040 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_6 0x0040 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_7 0x0040 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_7 0x0040 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_8 0x0040 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_8 0x0040 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_9 0x0040 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_9 0x0040 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_10 0x0040 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_10 0x0040 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_11 0x0040 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_11 0x0040 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_12 0x0040 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_12 0x0040 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_13 0x0040 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_13 0x0040 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_14 0x0040 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_14 0x0040 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_15 0x0040 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf_alt_15 0x0040 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x0041 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x0041 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x0041 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf 0x0041 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_1 0x0041 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_1 0x0041 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_2 0x0041 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_2 0x0041 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_3 0x0041 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_3 0x0041 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_4 0x0041 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_4 0x0041 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_5 0x0041 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_5 0x0041 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_6 0x0041 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_6 0x0041 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_7 0x0041 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_7 0x0041 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_8 0x0041 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_8 0x0041 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_9 0x0041 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_9 0x0041 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_10 0x0041 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_10 0x0041 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_11 0x0041 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_11 0x0041 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_12 0x0041 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_12 0x0041 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_13 0x0041 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_13 0x0041 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_14 0x0041 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_14 0x0041 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_15 0x0041 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf_alt_15 0x0041 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x0042 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x0042 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x0042 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf 0x0042 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_1 0x0042 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_1 0x0042 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_2 0x0042 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_2 0x0042 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_3 0x0042 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_3 0x0042 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_4 0x0042 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_4 0x0042 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_5 0x0042 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_5 0x0042 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_6 0x0042 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_6 0x0042 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_7 0x0042 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_7 0x0042 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_8 0x0042 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_8 0x0042 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_9 0x0042 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_9 0x0042 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_10 0x0042 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_10 0x0042 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_11 0x0042 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_11 0x0042 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_12 0x0042 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_12 0x0042 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_13 0x0042 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_13 0x0042 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_14 0x0042 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_14 0x0042 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_15 0x0042 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf_alt_15 0x0042 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x0043 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x0043 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x0043 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf 0x0043 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_1 0x0043 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_1 0x0043 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_2 0x0043 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_2 0x0043 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_3 0x0043 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_3 0x0043 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_4 0x0043 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_4 0x0043 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_5 0x0043 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_5 0x0043 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_6 0x0043 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_6 0x0043 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_7 0x0043 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_7 0x0043 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_8 0x0043 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_8 0x0043 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_9 0x0043 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_9 0x0043 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_10 0x0043 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_10 0x0043 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_11 0x0043 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_11 0x0043 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_12 0x0043 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_12 0x0043 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_13 0x0043 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_13 0x0043 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_14 0x0043 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_14 0x0043 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_15 0x0043 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf_alt_15 0x0043 -#define pcinbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x0054 -#define cfgnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x0054 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x0054 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf 0x0054 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_1 0x0054 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_1 0x0054 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_2 0x0054 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_2 0x0054 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_3 0x0054 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_3 0x0054 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_4 0x0054 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_4 0x0054 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_5 0x0054 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_5 0x0054 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_6 0x0054 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_6 0x0054 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_7 0x0054 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_7 0x0054 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_8 0x0054 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_8 0x0054 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_9 0x0054 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_9 0x0054 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_10 0x0054 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_10 0x0054 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_11 0x0054 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_11 0x0054 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_12 0x0054 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_12 0x0054 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_13 0x0054 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_13 0x0054 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_14 0x0054 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_14 0x0054 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_15 0x0054 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf_alt_15 0x0054 -#define pcinbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x0055 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x0055 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x0055 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf 0x0055 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_1 0x0055 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_1 0x0055 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_2 0x0055 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_2 0x0055 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_3 0x0055 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_3 0x0055 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_4 0x0055 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_4 0x0055 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_5 0x0055 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_5 0x0055 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_6 0x0055 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_6 0x0055 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_7 0x0055 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_7 0x0055 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_8 0x0055 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_8 0x0055 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_9 0x0055 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_9 0x0055 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_10 0x0055 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_10 0x0055 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_11 0x0055 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_11 0x0055 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_12 0x0055 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_12 0x0055 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_13 0x0055 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_13 0x0055 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_14 0x0055 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_14 0x0055 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_15 0x0055 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf_alt_15 0x0055 -#define pcinbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x0056 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x0056 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x0056 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf 0x0056 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_1 0x0056 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_1 0x0056 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_2 0x0056 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_2 0x0056 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_3 0x0056 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_3 0x0056 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_4 0x0056 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_4 0x0056 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_5 0x0056 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_5 0x0056 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_6 0x0056 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_6 0x0056 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_7 0x0056 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_7 0x0056 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_8 0x0056 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_8 0x0056 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_9 0x0056 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_9 0x0056 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_10 0x0056 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_10 0x0056 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_11 0x0056 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_11 0x0056 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_12 0x0056 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_12 0x0056 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_13 0x0056 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_13 0x0056 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_14 0x0056 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_14 0x0056 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_15 0x0056 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf_alt_15 0x0056 -#define pcinbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x0057 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x0057 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x0057 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf 0x0057 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_1 0x0057 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_1 0x0057 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_2 0x0057 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_2 0x0057 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_3 0x0057 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_3 0x0057 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_4 0x0057 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_4 0x0057 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_5 0x0057 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_5 0x0057 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_6 0x0057 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_6 0x0057 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_7 0x0057 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_7 0x0057 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_8 0x0057 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_8 0x0057 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_9 0x0057 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_9 0x0057 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_10 0x0057 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_10 0x0057 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_11 0x0057 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_11 0x0057 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_12 0x0057 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_12 0x0057 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_13 0x0057 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_13 0x0057 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_14 0x0057 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_14 0x0057 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_15 0x0057 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf_alt_15 0x0057 -#define pcinbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x0058 -#define cfgnbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x0058 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x0058 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf 0x0058 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_1 0x0058 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_1 0x0058 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_2 0x0058 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_2 0x0058 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_3 0x0058 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_3 0x0058 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_4 0x0058 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_4 0x0058 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_5 0x0058 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_5 0x0058 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_6 0x0058 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_6 0x0058 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_7 0x0058 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_7 0x0058 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_8 0x0058 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_8 0x0058 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_9 0x0058 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_9 0x0058 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_10 0x0058 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_10 0x0058 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_11 0x0058 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_11 0x0058 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_12 0x0058 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_12 0x0058 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_13 0x0058 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_13 0x0058 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_14 0x0058 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_14 0x0058 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_15 0x0058 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_CORR_ERR_STATUS_epvf_alt_15 0x0058 -#define pcinbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x0059 -#define cfgnbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x0059 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x0059 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_CORR_ERR_MASK_epvf 0x0059 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_1 0x0059 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_1 0x0059 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_2 0x0059 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_2 0x0059 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_3 0x0059 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_3 0x0059 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_4 0x0059 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_4 0x0059 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_5 0x0059 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_5 0x0059 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_6 0x0059 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_6 0x0059 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_7 0x0059 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_7 0x0059 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_8 0x0059 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_8 0x0059 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_9 0x0059 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_9 0x0059 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_10 0x0059 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_10 0x0059 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_11 0x0059 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_11 0x0059 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_12 0x0059 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_12 0x0059 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_13 0x0059 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_13 0x0059 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_14 0x0059 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_14 0x0059 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_15 0x0059 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_CORR_ERR_MASK_epvf_alt_15 0x0059 -#define pcinbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x005A -#define cfgnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x005A -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x005A -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf 0x005A -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_1 0x005A -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_1 0x005A -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_2 0x005A -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_2 0x005A -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_3 0x005A -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_3 0x005A -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_4 0x005A -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_4 0x005A -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_5 0x005A -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_5 0x005A -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_6 0x005A -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_6 0x005A -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_7 0x005A -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_7 0x005A -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_8 0x005A -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_8 0x005A -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_9 0x005A -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_9 0x005A -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_10 0x005A -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_10 0x005A -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_11 0x005A -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_11 0x005A -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_12 0x005A -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_12 0x005A -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_13 0x005A -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_13 0x005A -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_14 0x005A -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_14 0x005A -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_15 0x005A -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf_alt_15 0x005A -#define pcinbif_gpu_PCIE_HDR_LOG0_epvf 0x005B -#define cfgnbif_gpu_PCIE_HDR_LOG0_epvf 0x005B -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG0_epvf 0x005B -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG0_epvf 0x005B -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_1 0x005B -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_1 0x005B -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_2 0x005B -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_2 0x005B -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_3 0x005B -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_3 0x005B -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_4 0x005B -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_4 0x005B -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_5 0x005B -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_5 0x005B -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_6 0x005B -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_6 0x005B -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_7 0x005B -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_7 0x005B -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_8 0x005B -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_8 0x005B -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_9 0x005B -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_9 0x005B -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_10 0x005B -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_10 0x005B -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_11 0x005B -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_11 0x005B -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_12 0x005B -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_12 0x005B -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_13 0x005B -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_13 0x005B -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_14 0x005B -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_14 0x005B -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_15 0x005B -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG0_epvf_alt_15 0x005B -#define pcinbif_gpu_PCIE_HDR_LOG1_epvf 0x005C -#define cfgnbif_gpu_PCIE_HDR_LOG1_epvf 0x005C -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG1_epvf 0x005C -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG1_epvf 0x005C -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_1 0x005C -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_1 0x005C -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_2 0x005C -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_2 0x005C -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_3 0x005C -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_3 0x005C -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_4 0x005C -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_4 0x005C -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_5 0x005C -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_5 0x005C -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_6 0x005C -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_6 0x005C -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_7 0x005C -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_7 0x005C -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_8 0x005C -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_8 0x005C -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_9 0x005C -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_9 0x005C -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_10 0x005C -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_10 0x005C -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_11 0x005C -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_11 0x005C -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_12 0x005C -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_12 0x005C -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_13 0x005C -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_13 0x005C -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_14 0x005C -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_14 0x005C -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_15 0x005C -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG1_epvf_alt_15 0x005C -#define pcinbif_gpu_PCIE_HDR_LOG2_epvf 0x005D -#define cfgnbif_gpu_PCIE_HDR_LOG2_epvf 0x005D -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG2_epvf 0x005D -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG2_epvf 0x005D -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_1 0x005D -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_1 0x005D -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_2 0x005D -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_2 0x005D -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_3 0x005D -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_3 0x005D -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_4 0x005D -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_4 0x005D -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_5 0x005D -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_5 0x005D -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_6 0x005D -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_6 0x005D -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_7 0x005D -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_7 0x005D -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_8 0x005D -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_8 0x005D -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_9 0x005D -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_9 0x005D -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_10 0x005D -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_10 0x005D -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_11 0x005D -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_11 0x005D -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_12 0x005D -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_12 0x005D -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_13 0x005D -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_13 0x005D -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_14 0x005D -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_14 0x005D -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_15 0x005D -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG2_epvf_alt_15 0x005D -#define pcinbif_gpu_PCIE_HDR_LOG3_epvf 0x005E -#define cfgnbif_gpu_PCIE_HDR_LOG3_epvf 0x005E -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG3_epvf 0x005E -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_HDR_LOG3_epvf 0x005E -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_1 0x005E -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_1 0x005E -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_2 0x005E -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_2 0x005E -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_3 0x005E -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_3 0x005E -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_4 0x005E -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_4 0x005E -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_5 0x005E -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_5 0x005E -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_6 0x005E -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_6 0x005E -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_7 0x005E -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_7 0x005E -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_8 0x005E -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_8 0x005E -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_9 0x005E -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_9 0x005E -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_10 0x005E -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_10 0x005E -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_11 0x005E -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_11 0x005E -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_12 0x005E -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_12 0x005E -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_13 0x005E -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_13 0x005E -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_14 0x005E -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_14 0x005E -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_15 0x005E -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_HDR_LOG3_epvf_alt_15 0x005E -#define pcinbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x005F -#define cfgnbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x005F -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x005F -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf 0x005F -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_1 0x005F -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_1 0x005F -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_2 0x005F -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_2 0x005F -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_3 0x005F -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_3 0x005F -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_4 0x005F -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_4 0x005F -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_5 0x005F -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_5 0x005F -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_6 0x005F -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_6 0x005F -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_7 0x005F -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_7 0x005F -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_8 0x005F -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_8 0x005F -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_9 0x005F -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_9 0x005F -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_10 0x005F -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_10 0x005F -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_11 0x005F -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_11 0x005F -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_12 0x005F -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_12 0x005F -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_13 0x005F -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_13 0x005F -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_14 0x005F -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_14 0x005F -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_15 0x005F -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ROOT_ERR_CMD_epvf_alt_15 0x005F -#define pcinbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x0060 -#define cfgnbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x0060 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x0060 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf 0x0060 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_1 0x0060 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_1 0x0060 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_2 0x0060 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_2 0x0060 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_3 0x0060 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_3 0x0060 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_4 0x0060 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_4 0x0060 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_5 0x0060 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_5 0x0060 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_6 0x0060 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_6 0x0060 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_7 0x0060 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_7 0x0060 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_8 0x0060 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_8 0x0060 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_9 0x0060 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_9 0x0060 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_10 0x0060 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_10 0x0060 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_11 0x0060 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_11 0x0060 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_12 0x0060 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_12 0x0060 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_13 0x0060 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_13 0x0060 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_14 0x0060 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_14 0x0060 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_15 0x0060 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf_alt_15 0x0060 -#define pcinbif_gpu_PCIE_ERR_SRC_ID_epvf 0x0061 -#define cfgnbif_gpu_PCIE_ERR_SRC_ID_epvf 0x0061 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x0061 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ERR_SRC_ID_epvf 0x0061 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_1 0x0061 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_1 0x0061 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_2 0x0061 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_2 0x0061 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_3 0x0061 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_3 0x0061 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_4 0x0061 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_4 0x0061 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_5 0x0061 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_5 0x0061 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_6 0x0061 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_6 0x0061 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_7 0x0061 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_7 0x0061 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_8 0x0061 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_8 0x0061 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_9 0x0061 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_9 0x0061 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_10 0x0061 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_10 0x0061 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_11 0x0061 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_11 0x0061 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_12 0x0061 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_12 0x0061 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_13 0x0061 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_13 0x0061 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_14 0x0061 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_14 0x0061 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_15 0x0061 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ERR_SRC_ID_epvf_alt_15 0x0061 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x0062 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x0062 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x0062 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf 0x0062 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_1 0x0062 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_1 0x0062 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_2 0x0062 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_2 0x0062 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_3 0x0062 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_3 0x0062 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_4 0x0062 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_4 0x0062 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_5 0x0062 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_5 0x0062 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_6 0x0062 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_6 0x0062 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_7 0x0062 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_7 0x0062 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_8 0x0062 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_8 0x0062 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_9 0x0062 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_9 0x0062 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_10 0x0062 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_10 0x0062 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_11 0x0062 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_11 0x0062 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_12 0x0062 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_12 0x0062 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_13 0x0062 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_13 0x0062 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_14 0x0062 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_14 0x0062 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_15 0x0062 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf_alt_15 0x0062 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x0063 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x0063 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x0063 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf 0x0063 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_1 0x0063 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_1 0x0063 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_2 0x0063 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_2 0x0063 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_3 0x0063 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_3 0x0063 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_4 0x0063 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_4 0x0063 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_5 0x0063 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_5 0x0063 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_6 0x0063 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_6 0x0063 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_7 0x0063 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_7 0x0063 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_8 0x0063 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_8 0x0063 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_9 0x0063 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_9 0x0063 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_10 0x0063 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_10 0x0063 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_11 0x0063 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_11 0x0063 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_12 0x0063 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_12 0x0063 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_13 0x0063 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_13 0x0063 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_14 0x0063 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_14 0x0063 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_15 0x0063 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf_alt_15 0x0063 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x0064 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x0064 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x0064 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf 0x0064 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_1 0x0064 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_1 0x0064 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_2 0x0064 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_2 0x0064 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_3 0x0064 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_3 0x0064 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_4 0x0064 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_4 0x0064 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_5 0x0064 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_5 0x0064 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_6 0x0064 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_6 0x0064 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_7 0x0064 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_7 0x0064 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_8 0x0064 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_8 0x0064 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_9 0x0064 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_9 0x0064 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_10 0x0064 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_10 0x0064 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_11 0x0064 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_11 0x0064 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_12 0x0064 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_12 0x0064 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_13 0x0064 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_13 0x0064 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_14 0x0064 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_14 0x0064 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_15 0x0064 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf_alt_15 0x0064 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x0065 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x0065 -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x0065 -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf 0x0065 -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_1 0x0065 -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_1 0x0065 -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_2 0x0065 -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_2 0x0065 -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_3 0x0065 -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_3 0x0065 -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_4 0x0065 -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_4 0x0065 -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_5 0x0065 -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_5 0x0065 -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_6 0x0065 -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_6 0x0065 -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_7 0x0065 -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_7 0x0065 -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_8 0x0065 -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_8 0x0065 -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_9 0x0065 -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_9 0x0065 -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_10 0x0065 -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_10 0x0065 -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_11 0x0065 -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_11 0x0065 -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_12 0x0065 -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_12 0x0065 -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_13 0x0065 -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_13 0x0065 -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_14 0x0065 -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_14 0x0065 -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_15 0x0065 -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf_alt_15 0x0065 -#define pcinbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x00AC -#define cfgnbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x00AC -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x00AC -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf 0x00AC -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_1 0x00AC -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_1 0x00AC -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_2 0x00AC -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_2 0x00AC -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_3 0x00AC -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_3 0x00AC -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_4 0x00AC -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_4 0x00AC -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_5 0x00AC -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_5 0x00AC -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_6 0x00AC -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_6 0x00AC -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_7 0x00AC -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_7 0x00AC -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_8 0x00AC -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_8 0x00AC -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_9 0x00AC -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_9 0x00AC -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_10 0x00AC -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_10 0x00AC -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_11 0x00AC -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_11 0x00AC -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_12 0x00AC -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_12 0x00AC -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_13 0x00AC -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_13 0x00AC -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_14 0x00AC -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_14 0x00AC -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_15 0x00AC -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf_alt_15 0x00AC -#define pcinbif_gpu_PCIE_ATS_CAP_epvf 0x00AD -#define cfgnbif_gpu_PCIE_ATS_CAP_epvf 0x00AD -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_CAP_epvf 0x00AD -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_CAP_epvf 0x00AD -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_CAP_epvf_alt_1 0x00AD -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_CAP_epvf_alt_1 0x00AD -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_CAP_epvf_alt_2 0x00AD -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_CAP_epvf_alt_2 0x00AD -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_CAP_epvf_alt_3 0x00AD -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_CAP_epvf_alt_3 0x00AD -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_CAP_epvf_alt_4 0x00AD -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_CAP_epvf_alt_4 0x00AD -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_CAP_epvf_alt_5 0x00AD -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_CAP_epvf_alt_5 0x00AD -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_CAP_epvf_alt_6 0x00AD -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_CAP_epvf_alt_6 0x00AD -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_CAP_epvf_alt_7 0x00AD -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_CAP_epvf_alt_7 0x00AD -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_CAP_epvf_alt_8 0x00AD -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_CAP_epvf_alt_8 0x00AD -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_CAP_epvf_alt_9 0x00AD -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_CAP_epvf_alt_9 0x00AD -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_CAP_epvf_alt_10 0x00AD -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_CAP_epvf_alt_10 0x00AD -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_CAP_epvf_alt_11 0x00AD -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_CAP_epvf_alt_11 0x00AD -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_CAP_epvf_alt_12 0x00AD -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_CAP_epvf_alt_12 0x00AD -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_CAP_epvf_alt_13 0x00AD -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_CAP_epvf_alt_13 0x00AD -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_CAP_epvf_alt_14 0x00AD -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_CAP_epvf_alt_14 0x00AD -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_CAP_epvf_alt_15 0x00AD -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_CAP_epvf_alt_15 0x00AD -#define pcinbif_gpu_PCIE_ATS_CNTL_epvf 0x00AD -#define cfgnbif_gpu_PCIE_ATS_CNTL_epvf 0x00AD -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_CNTL_epvf 0x00AD -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ATS_CNTL_epvf 0x00AD -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_1 0x00AD -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_1 0x00AD -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_2 0x00AD -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_2 0x00AD -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_3 0x00AD -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_3 0x00AD -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_4 0x00AD -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_4 0x00AD -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_5 0x00AD -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_5 0x00AD -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_6 0x00AD -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_6 0x00AD -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_7 0x00AD -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_7 0x00AD -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_8 0x00AD -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_8 0x00AD -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_9 0x00AD -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_9 0x00AD -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_10 0x00AD -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_10 0x00AD -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_11 0x00AD -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_11 0x00AD -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_12 0x00AD -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_12 0x00AD -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_13 0x00AD -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_13 0x00AD -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_14 0x00AD -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_14 0x00AD -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_15 0x00AD -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ATS_CNTL_epvf_alt_15 0x00AD -#define pcinbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x00CA -#define cfgnbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x00CA -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x00CA -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf 0x00CA -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_1 0x00CA -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_1 0x00CA -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_2 0x00CA -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_2 0x00CA -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_3 0x00CA -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_3 0x00CA -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_4 0x00CA -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_4 0x00CA -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_5 0x00CA -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_5 0x00CA -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_6 0x00CA -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_6 0x00CA -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_7 0x00CA -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_7 0x00CA -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_8 0x00CA -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_8 0x00CA -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_9 0x00CA -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_9 0x00CA -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_10 0x00CA -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_10 0x00CA -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_11 0x00CA -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_11 0x00CA -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_12 0x00CA -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_12 0x00CA -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_13 0x00CA -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_13 0x00CA -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_14 0x00CA -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_14 0x00CA -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_15 0x00CA -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf_alt_15 0x00CA -#define pcinbif_gpu_PCIE_ARI_CAP_epvf 0x00CB -#define cfgnbif_gpu_PCIE_ARI_CAP_epvf 0x00CB -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_CAP_epvf 0x00CB -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_CAP_epvf 0x00CB -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_CAP_epvf_alt_1 0x00CB -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_CAP_epvf_alt_1 0x00CB -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_CAP_epvf_alt_2 0x00CB -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_CAP_epvf_alt_2 0x00CB -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_CAP_epvf_alt_3 0x00CB -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_CAP_epvf_alt_3 0x00CB -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_CAP_epvf_alt_4 0x00CB -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_CAP_epvf_alt_4 0x00CB -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_CAP_epvf_alt_5 0x00CB -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_CAP_epvf_alt_5 0x00CB -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_CAP_epvf_alt_6 0x00CB -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_CAP_epvf_alt_6 0x00CB -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_CAP_epvf_alt_7 0x00CB -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_CAP_epvf_alt_7 0x00CB -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_CAP_epvf_alt_8 0x00CB -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_CAP_epvf_alt_8 0x00CB -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_CAP_epvf_alt_9 0x00CB -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_CAP_epvf_alt_9 0x00CB -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_CAP_epvf_alt_10 0x00CB -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_CAP_epvf_alt_10 0x00CB -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_CAP_epvf_alt_11 0x00CB -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_CAP_epvf_alt_11 0x00CB -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_CAP_epvf_alt_12 0x00CB -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_CAP_epvf_alt_12 0x00CB -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_CAP_epvf_alt_13 0x00CB -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_CAP_epvf_alt_13 0x00CB -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_CAP_epvf_alt_14 0x00CB -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_CAP_epvf_alt_14 0x00CB -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_CAP_epvf_alt_15 0x00CB -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_CAP_epvf_alt_15 0x00CB -#define pcinbif_gpu_PCIE_ARI_CNTL_epvf 0x00CB -#define cfgnbif_gpu_PCIE_ARI_CNTL_epvf 0x00CB -#define pciBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_CNTL_epvf 0x00CB -#define cfgBIF_CFG_EPVF0_nbif_gpu_PCIE_ARI_CNTL_epvf 0x00CB -#define pciBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_1 0x00CB -#define cfgBIF_CFG_EPVF1_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_1 0x00CB -#define pciBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_2 0x00CB -#define cfgBIF_CFG_EPVF2_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_2 0x00CB -#define pciBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_3 0x00CB -#define cfgBIF_CFG_EPVF3_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_3 0x00CB -#define pciBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_4 0x00CB -#define cfgBIF_CFG_EPVF4_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_4 0x00CB -#define pciBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_5 0x00CB -#define cfgBIF_CFG_EPVF5_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_5 0x00CB -#define pciBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_6 0x00CB -#define cfgBIF_CFG_EPVF6_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_6 0x00CB -#define pciBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_7 0x00CB -#define cfgBIF_CFG_EPVF7_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_7 0x00CB -#define pciBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_8 0x00CB -#define cfgBIF_CFG_EPVF8_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_8 0x00CB -#define pciBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_9 0x00CB -#define cfgBIF_CFG_EPVF9_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_9 0x00CB -#define pciBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_10 0x00CB -#define cfgBIF_CFG_EPVF10_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_10 0x00CB -#define pciBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_11 0x00CB -#define cfgBIF_CFG_EPVF11_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_11 0x00CB -#define pciBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_12 0x00CB -#define cfgBIF_CFG_EPVF12_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_12 0x00CB -#define pciBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_13 0x00CB -#define cfgBIF_CFG_EPVF13_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_13 0x00CB -#define pciBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_14 0x00CB -#define cfgBIF_CFG_EPVF14_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_14 0x00CB -#define pciBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_15 0x00CB -#define cfgBIF_CFG_EPVF15_nbif_gpu_PCIE_ARI_CNTL_epvf_alt_15 0x00CB - - -// Registers from RCC block - -#define mmnbif_gpu_RCC_BACO_CNTL_MISC 0x0DA7 -#define mmRCC0_nbif_gpu_RCC_BACO_CNTL_MISC 0x0DA7 -#define mmnbif_gpu_RCC_BACO_CNTL_MISC_alt_1 0x4048DA7 -#define mmRCC0_nbif_gpu_RCC_BACO_CNTL_MISC_alt_1 0x4048DA7 -#define mmnbif_gpu_RCC_RESET_EN 0x0DA8 -#define mmRCC0_nbif_gpu_RCC_RESET_EN 0x0DA8 -#define mmnbif_gpu_RCC_RESET_EN_alt_1 0x4048DA8 -#define mmRCC0_nbif_gpu_RCC_RESET_EN_alt_1 0x4048DA8 -#define mmnbif_gpu_RCC_VDM_SUPPORT 0x0DA9 -#define mmRCC0_nbif_gpu_RCC_VDM_SUPPORT 0x0DA9 -#define mmnbif_gpu_RCC_VDM_SUPPORT_alt_1 0x4048DA9 -#define mmRCC0_nbif_gpu_RCC_VDM_SUPPORT_alt_1 0x4048DA9 -#define mmnbif_gpu_RCC_BUS_CNTL 0x0DE1 -#define mmRCC0_nbif_gpu_RCC_BUS_CNTL 0x0DE1 -#define mmnbif_gpu_RCC_BUS_CNTL_alt_1 0x4048DE1 -#define mmRCC0_nbif_gpu_RCC_BUS_CNTL_alt_1 0x4048DE1 -#define mmnbif_gpu_RCC_CONFIG_CNTL 0x0DE2 -#define mmRCC0_nbif_gpu_RCC_CONFIG_CNTL 0x0DE2 -#define mmnbif_gpu_RCC_CONFIG_CNTL_alt_1 0x4048DE2 -#define mmRCC0_nbif_gpu_RCC_CONFIG_CNTL_alt_1 0x4048DE2 -#define mmnbif_gpu_RCC_CONFIG_F0_BASE 0x0DE6 -#define mmRCC0_nbif_gpu_RCC_CONFIG_F0_BASE 0x0DE6 -#define mmnbif_gpu_RCC_CONFIG_F0_BASE_alt_1 0x4048DE6 -#define mmRCC0_nbif_gpu_RCC_CONFIG_F0_BASE_alt_1 0x4048DE6 -#define mmnbif_gpu_RCC_CONFIG_APER_SIZE 0x0DE7 -#define mmRCC0_nbif_gpu_RCC_CONFIG_APER_SIZE 0x0DE7 -#define mmnbif_gpu_RCC_CONFIG_APER_SIZE_alt_1 0x4048DE7 -#define mmRCC0_nbif_gpu_RCC_CONFIG_APER_SIZE_alt_1 0x4048DE7 -#define mmnbif_gpu_RCC_CONFIG_REG_APER_SIZE 0x0DE8 -#define mmRCC0_nbif_gpu_RCC_CONFIG_REG_APER_SIZE 0x0DE8 -#define mmnbif_gpu_RCC_CONFIG_REG_APER_SIZE_alt_1 0x4048DE8 -#define mmRCC0_nbif_gpu_RCC_CONFIG_REG_APER_SIZE_alt_1 0x4048DE8 -#define mmnbif_gpu_RCC_XDMA_LO 0x0DE9 -#define mmRCC0_nbif_gpu_RCC_XDMA_LO 0x0DE9 -#define mmnbif_gpu_RCC_XDMA_LO_alt_1 0x4048DE9 -#define mmRCC0_nbif_gpu_RCC_XDMA_LO_alt_1 0x4048DE9 -#define mmnbif_gpu_RCC_XDMA_HI 0x0DEA -#define mmRCC0_nbif_gpu_RCC_XDMA_HI 0x0DEA -#define mmnbif_gpu_RCC_XDMA_HI_alt_1 0x4048DEA -#define mmRCC0_nbif_gpu_RCC_XDMA_HI_alt_1 0x4048DEA -#define mmnbif_gpu_RCC_FEATURES_CONTROL_MISC 0x0DEB -#define mmRCC0_nbif_gpu_RCC_FEATURES_CONTROL_MISC 0x0DEB -#define mmnbif_gpu_RCC_FEATURES_CONTROL_MISC_alt_1 0x4048DEB -#define mmRCC0_nbif_gpu_RCC_FEATURES_CONTROL_MISC_alt_1 0x4048DEB -#define mmnbif_gpu_RCC_BUSNUM_CNTL1 0x0DEC -#define mmRCC0_nbif_gpu_RCC_BUSNUM_CNTL1 0x0DEC -#define mmnbif_gpu_RCC_BUSNUM_CNTL1_alt_1 0x4048DEC -#define mmRCC0_nbif_gpu_RCC_BUSNUM_CNTL1_alt_1 0x4048DEC -#define mmnbif_gpu_RCC_BUSNUM_LIST0 0x0DED -#define mmRCC0_nbif_gpu_RCC_BUSNUM_LIST0 0x0DED -#define mmnbif_gpu_RCC_BUSNUM_LIST0_alt_1 0x4048DED -#define mmRCC0_nbif_gpu_RCC_BUSNUM_LIST0_alt_1 0x4048DED -#define mmnbif_gpu_RCC_BUSNUM_LIST1 0x0DEE -#define mmRCC0_nbif_gpu_RCC_BUSNUM_LIST1 0x0DEE -#define mmnbif_gpu_RCC_BUSNUM_LIST1_alt_1 0x4048DEE -#define mmRCC0_nbif_gpu_RCC_BUSNUM_LIST1_alt_1 0x4048DEE -#define mmnbif_gpu_RCC_BUSNUM_CNTL2 0x0DEF -#define mmRCC0_nbif_gpu_RCC_BUSNUM_CNTL2 0x0DEF -#define mmnbif_gpu_RCC_BUSNUM_CNTL2_alt_1 0x4048DEF -#define mmRCC0_nbif_gpu_RCC_BUSNUM_CNTL2_alt_1 0x4048DEF -#define mmnbif_gpu_RCC_CAPTURE_HOST_BUSNUM 0x0DF0 -#define mmRCC0_nbif_gpu_RCC_CAPTURE_HOST_BUSNUM 0x0DF0 -#define mmnbif_gpu_RCC_CAPTURE_HOST_BUSNUM_alt_1 0x4048DF0 -#define mmRCC0_nbif_gpu_RCC_CAPTURE_HOST_BUSNUM_alt_1 0x4048DF0 -#define mmnbif_gpu_RCC_HOST_BUSNUM 0x0DF1 -#define mmRCC0_nbif_gpu_RCC_HOST_BUSNUM 0x0DF1 -#define mmnbif_gpu_RCC_HOST_BUSNUM_alt_1 0x4048DF1 -#define mmRCC0_nbif_gpu_RCC_HOST_BUSNUM_alt_1 0x4048DF1 -#define mmnbif_gpu_RCC_PEER0_FB_OFFSET_HI 0x0DF2 -#define mmRCC0_nbif_gpu_RCC_PEER0_FB_OFFSET_HI 0x0DF2 -#define mmnbif_gpu_RCC_PEER0_FB_OFFSET_HI_alt_1 0x4048DF2 -#define mmRCC0_nbif_gpu_RCC_PEER0_FB_OFFSET_HI_alt_1 0x4048DF2 -#define mmnbif_gpu_RCC_PEER0_FB_OFFSET_LO 0x0DF3 -#define mmRCC0_nbif_gpu_RCC_PEER0_FB_OFFSET_LO 0x0DF3 -#define mmnbif_gpu_RCC_PEER0_FB_OFFSET_LO_alt_1 0x4048DF3 -#define mmRCC0_nbif_gpu_RCC_PEER0_FB_OFFSET_LO_alt_1 0x4048DF3 -#define mmnbif_gpu_RCC_PEER1_FB_OFFSET_HI 0x0DF4 -#define mmRCC0_nbif_gpu_RCC_PEER1_FB_OFFSET_HI 0x0DF4 -#define mmnbif_gpu_RCC_PEER1_FB_OFFSET_HI_alt_1 0x4048DF4 -#define mmRCC0_nbif_gpu_RCC_PEER1_FB_OFFSET_HI_alt_1 0x4048DF4 -#define mmnbif_gpu_RCC_PEER1_FB_OFFSET_LO 0x0DF5 -#define mmRCC0_nbif_gpu_RCC_PEER1_FB_OFFSET_LO 0x0DF5 -#define mmnbif_gpu_RCC_PEER1_FB_OFFSET_LO_alt_1 0x4048DF5 -#define mmRCC0_nbif_gpu_RCC_PEER1_FB_OFFSET_LO_alt_1 0x4048DF5 -#define mmnbif_gpu_RCC_PEER2_FB_OFFSET_HI 0x0DF6 -#define mmRCC0_nbif_gpu_RCC_PEER2_FB_OFFSET_HI 0x0DF6 -#define mmnbif_gpu_RCC_PEER2_FB_OFFSET_HI_alt_1 0x4048DF6 -#define mmRCC0_nbif_gpu_RCC_PEER2_FB_OFFSET_HI_alt_1 0x4048DF6 -#define mmnbif_gpu_RCC_PEER2_FB_OFFSET_LO 0x0DF7 -#define mmRCC0_nbif_gpu_RCC_PEER2_FB_OFFSET_LO 0x0DF7 -#define mmnbif_gpu_RCC_PEER2_FB_OFFSET_LO_alt_1 0x4048DF7 -#define mmRCC0_nbif_gpu_RCC_PEER2_FB_OFFSET_LO_alt_1 0x4048DF7 -#define mmnbif_gpu_RCC_PEER3_FB_OFFSET_HI 0x0DF8 -#define mmRCC0_nbif_gpu_RCC_PEER3_FB_OFFSET_HI 0x0DF8 -#define mmnbif_gpu_RCC_PEER3_FB_OFFSET_HI_alt_1 0x4048DF8 -#define mmRCC0_nbif_gpu_RCC_PEER3_FB_OFFSET_HI_alt_1 0x4048DF8 -#define mmnbif_gpu_RCC_PEER3_FB_OFFSET_LO 0x0DF9 -#define mmRCC0_nbif_gpu_RCC_PEER3_FB_OFFSET_LO 0x0DF9 -#define mmnbif_gpu_RCC_PEER3_FB_OFFSET_LO_alt_1 0x4048DF9 -#define mmRCC0_nbif_gpu_RCC_PEER3_FB_OFFSET_LO_alt_1 0x4048DF9 -#define mmnbif_gpu_RCC_DEVFUNCNUM_LIST0 0x0DFA -#define mmRCC0_nbif_gpu_RCC_DEVFUNCNUM_LIST0 0x0DFA -#define mmnbif_gpu_RCC_DEVFUNCNUM_LIST0_alt_1 0x4048DFA -#define mmRCC0_nbif_gpu_RCC_DEVFUNCNUM_LIST0_alt_1 0x4048DFA -#define mmnbif_gpu_RCC_DEVFUNCNUM_LIST1 0x0DFB -#define mmRCC0_nbif_gpu_RCC_DEVFUNCNUM_LIST1 0x0DFB -#define mmnbif_gpu_RCC_DEVFUNCNUM_LIST1_alt_1 0x4048DFB -#define mmRCC0_nbif_gpu_RCC_DEVFUNCNUM_LIST1_alt_1 0x4048DFB -#define mmnbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO 0x0DFC -#define mmRCC0_nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO 0x0DFC -#define mmnbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO_alt_1 0x4048DFC -#define mmRCC0_nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO_alt_1 0x4048DFC -#define mmnbif_gpu_RCC_DEV0_LINK_CNTL 0x0DFD -#define mmRCC0_nbif_gpu_RCC_DEV0_LINK_CNTL 0x0DFD -#define mmnbif_gpu_RCC_DEV0_LINK_CNTL_alt_1 0x4048DFD -#define mmRCC0_nbif_gpu_RCC_DEV0_LINK_CNTL_alt_1 0x4048DFD -#define mmnbif_gpu_RCC_CMN_LINK_CNTL 0x0DFE -#define mmRCC0_nbif_gpu_RCC_CMN_LINK_CNTL 0x0DFE -#define mmnbif_gpu_RCC_CMN_LINK_CNTL_alt_1 0x4048DFE -#define mmRCC0_nbif_gpu_RCC_CMN_LINK_CNTL_alt_1 0x4048DFE -#define mmnbif_gpu_RCC_EP_REQUESTERID_RESTORE 0x0DFF -#define mmRCC0_nbif_gpu_RCC_EP_REQUESTERID_RESTORE 0x0DFF -#define mmnbif_gpu_RCC_EP_REQUESTERID_RESTORE_alt_1 0x4048DFF -#define mmRCC0_nbif_gpu_RCC_EP_REQUESTERID_RESTORE_alt_1 0x4048DFF -#define mmnbif_gpu_RCC_LTR_LSWITCH_CNTL 0x0E00 -#define mmRCC0_nbif_gpu_RCC_LTR_LSWITCH_CNTL 0x0E00 -#define mmnbif_gpu_RCC_LTR_LSWITCH_CNTL_alt_1 0x4048E00 -#define mmRCC0_nbif_gpu_RCC_LTR_LSWITCH_CNTL_alt_1 0x4048E00 -#define mmnbif_gpu_RCC_MH_ARB_CNTL 0x0E01 -#define mmRCC0_nbif_gpu_RCC_MH_ARB_CNTL 0x0E01 -#define mmnbif_gpu_RCC_MH_ARB_CNTL_alt_1 0x4048E01 -#define mmRCC0_nbif_gpu_RCC_MH_ARB_CNTL_alt_1 0x4048E01 -#define mmnbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT0_ADDR_LO 0x10400 -#define mmnbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT1_ADDR_LO 0x10404 -#define mmnbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT2_ADDR_LO 0x10408 -#define mmnbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT0_ADDR_HI 0x10401 -#define mmnbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT1_ADDR_HI 0x10405 -#define mmnbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT2_ADDR_HI 0x10409 -#define mmnbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT0_MSG_DATA 0x10402 -#define mmnbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT1_MSG_DATA 0x10406 -#define mmnbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC0_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC1_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC2_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC3_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC4_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC5_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC6_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC7_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC8_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC9_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC10_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC11_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC12_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC13_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC14_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC15_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmRCC16_nbif_gpu_GFXMSIX_VECT2_MSG_DATA 0x1040A -#define mmnbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT0_CONTROL 0x10403 -#define mmnbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC0_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC1_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC2_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC3_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC4_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC5_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC6_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC7_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC8_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC9_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC10_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC11_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC12_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC13_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC14_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC15_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmRCC16_nbif_gpu_GFXMSIX_VECT1_CONTROL 0x10407 -#define mmnbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC0_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC1_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC2_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC3_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC4_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC5_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC6_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC7_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC8_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC9_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC10_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC11_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC12_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC13_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC14_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC15_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmRCC16_nbif_gpu_GFXMSIX_VECT2_CONTROL 0x1040B -#define mmnbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC0_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC1_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC2_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC3_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC4_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC5_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC6_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC7_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC8_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC9_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC10_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC11_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC12_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC13_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC14_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC15_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmRCC16_nbif_gpu_GFXMSIX_PBA 0x10800 -#define mmnbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC0_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC1_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC2_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC3_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC4_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC5_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC6_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC7_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC8_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC9_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC10_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC11_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC12_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC13_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC14_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC15_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmRCC16_nbif_gpu_RCC_DOORBELL_APER_EN 0x0DE0 -#define mmnbif_gpu_RCC_DOORBELL_APER_EN_alt_1 0x4048DE0 -#define mmRCC0_nbif_gpu_RCC_DOORBELL_APER_EN_alt_1 0x4048DE0 -#define mmnbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC0_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC1_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC2_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC3_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC4_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC5_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC6_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC7_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC8_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC9_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC10_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC11_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC12_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC13_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC14_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC15_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmRCC16_nbif_gpu_RCC_CONFIG_MEMSIZE 0x0DE3 -#define mmnbif_gpu_RCC_CONFIG_MEMSIZE_alt_1 0x4048DE3 -#define mmRCC0_nbif_gpu_RCC_CONFIG_MEMSIZE_alt_1 0x4048DE3 -#define mmnbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC0_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC1_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC2_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC3_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC4_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC5_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC6_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC7_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC8_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC9_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC10_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC11_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC12_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC13_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC14_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC15_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmRCC16_nbif_gpu_RCC_CONFIG_RESERVED 0x0DE4 -#define mmnbif_gpu_RCC_CONFIG_RESERVED_alt_1 0x4048DE4 -#define mmRCC0_nbif_gpu_RCC_CONFIG_RESERVED_alt_1 0x4048DE4 -#define mmnbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC0_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC1_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC2_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC3_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC4_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC5_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC6_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC7_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC8_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC9_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC10_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC11_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC12_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC13_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC14_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC15_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmRCC16_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER 0x0DE5 -#define mmnbif_gpu_RCC_IOV_FUNC_IDENTIFIER_alt_1 0x4048DE5 -#define mmRCC0_nbif_gpu_RCC_IOV_FUNC_IDENTIFIER_alt_1 0x4048DE5 - - -// Registers from RCC_DWN block - -#define mmnbif_gpu_DN_PCIE_RESERVED 0x0D60 -#define mmnbif_gpu_DN_PCIE_RESERVED_alt_1 0x4048D60 -#define mmnbif_gpu_DN_PCIE_SCRATCH 0x0D61 -#define mmnbif_gpu_DN_PCIE_SCRATCH_alt_1 0x4048D61 -#define mmnbif_gpu_DN_PCIE_HW_DEBUG 0x0D62 -#define mmnbif_gpu_DN_PCIE_HW_DEBUG_alt_1 0x4048D62 -#define mmnbif_gpu_DN_PCIE_CNTL 0x0D63 -#define mmnbif_gpu_DN_PCIE_CNTL_alt_1 0x4048D63 -#define mmnbif_gpu_DN_PCIE_CONFIG_CNTL 0x0D64 -#define mmnbif_gpu_DN_PCIE_CONFIG_CNTL_alt_1 0x4048D64 -#define mmnbif_gpu_DN_PCIE_RX_CNTL2 0x0D65 -#define mmnbif_gpu_DN_PCIE_RX_CNTL2_alt_1 0x4048D65 -#define mmnbif_gpu_DN_PCIE_BUS_CNTL 0x0D66 -#define mmnbif_gpu_DN_PCIE_BUS_CNTL_alt_1 0x4048D66 -#define mmnbif_gpu_DN_PCIE_CFG_CNTL 0x0D67 -#define mmnbif_gpu_DN_PCIE_CFG_CNTL_alt_1 0x4048D67 -#define mmnbif_gpu_DN_PCIE_STRAP_F0 0x0D68 -#define mmnbif_gpu_DN_PCIE_STRAP_F0_alt_1 0x4048D68 -#define mmnbif_gpu_DN_PCIE_STRAP_MISC 0x0D69 -#define mmnbif_gpu_DN_PCIE_STRAP_MISC_alt_1 0x4048D69 -#define mmnbif_gpu_DN_PCIE_STRAP_MISC2 0x0D6A -#define mmnbif_gpu_DN_PCIE_STRAP_MISC2_alt_1 0x4048D6A - - -// Registers from RCC_DWNP block - -#define mmnbif_gpu_PCIEP_RESERVED 0x0D6C -#define mmnbif_gpu_PCIEP_RESERVED_alt_1 0x4048D6C -#define mmnbif_gpu_PCIEP_SCRATCH 0x0D6D -#define mmnbif_gpu_PCIEP_SCRATCH_alt_1 0x4048D6D -#define mmnbif_gpu_PCIEP_HW_DEBUG 0x0D6E -#define mmnbif_gpu_PCIEP_HW_DEBUG_alt_1 0x4048D6E -#define mmnbif_gpu_PCIE_ERR_CNTL 0x0D6F -#define mmnbif_gpu_PCIE_ERR_CNTL_alt_1 0x4048D6F -#define mmnbif_gpu_PCIE_RX_CNTL 0x0D70 -#define mmnbif_gpu_PCIE_RX_CNTL_alt_1 0x4048D70 -#define mmnbif_gpu_PCIE_LC_SPEED_CNTL 0x0D71 -#define mmnbif_gpu_PCIE_LC_SPEED_CNTL_alt_1 0x4048D71 -#define mmnbif_gpu_PCIE_LC_CNTL2 0x0D72 -#define mmnbif_gpu_PCIE_LC_CNTL2_alt_1 0x4048D72 -#define mmnbif_gpu_PCIEP_STRAP_MISC 0x0D73 -#define mmnbif_gpu_PCIEP_STRAP_MISC_alt_1 0x4048D73 -#define mmnbif_gpu_LTR_MSG_INFO_FROM_EP 0x0D74 -#define mmnbif_gpu_LTR_MSG_INFO_FROM_EP_alt_1 0x4048D74 - - -// Registers from BIF_CFG_SWDS block - -#define mmnbif_gpu_VENDOR_ID_swds 0x4040000 -#define mmnbif_gpu_DEVICE_ID_swds 0x4040000 -#define mmnbif_gpu_COMMAND_swds 0x4040001 -#define mmnbif_gpu_STATUS_swds 0x4040001 -#define mmnbif_gpu_REVISION_ID_swds 0x4040002 -#define mmnbif_gpu_PROG_INTERFACE_swds 0x4040002 -#define mmnbif_gpu_SUB_CLASS_swds 0x4040002 -#define mmnbif_gpu_BASE_CLASS_swds 0x4040002 -#define mmnbif_gpu_CACHE_LINE_swds 0x4040003 -#define mmnbif_gpu_LATENCY_swds 0x4040003 -#define mmnbif_gpu_HEADER_swds 0x4040003 -#define mmnbif_gpu_BIST_swds 0x4040003 -#define mmnbif_gpu_BASE_ADDR_1_swds 0x4040004 -#define mmnbif_gpu_SUB_BUS_NUMBER_LATENCY_swds 0x4040006 -#define mmnbif_gpu_IO_BASE_LIMIT_swds 0x4040007 -#define mmnbif_gpu_SECONDARY_STATUS_swds 0x4040007 -#define mmnbif_gpu_MEM_BASE_LIMIT_swds 0x4040008 -#define mmnbif_gpu_PREF_BASE_LIMIT_swds 0x4040009 -#define mmnbif_gpu_PREF_BASE_UPPER_swds 0x404000A -#define mmnbif_gpu_PREF_LIMIT_UPPER_swds 0x404000B -#define mmnbif_gpu_IO_BASE_LIMIT_HI_swds 0x404000C -#define mmnbif_gpu_IRQ_BRIDGE_CNTL_swds 0x404000F -#define mmnbif_gpu_CAP_PTR_swds 0x404000D -#define mmnbif_gpu_INTERRUPT_LINE_swds 0x404000F -#define mmnbif_gpu_INTERRUPT_PIN_swds 0x404000F -#define mmnbif_gpu_PMI_CAP_LIST_swds 0x4040014 -#define mmnbif_gpu_PMI_CAP_swds 0x4040014 -#define mmnbif_gpu_PMI_STATUS_CNTL_swds 0x4040015 -#define mmnbif_gpu_PCIE_CAP_LIST_swds 0x4040016 -#define mmnbif_gpu_PCIE_CAP_swds 0x4040016 -#define mmnbif_gpu_DEVICE_CAP_swds 0x4040017 -#define mmnbif_gpu_DEVICE_CNTL_swds 0x4040018 -#define mmnbif_gpu_DEVICE_STATUS_swds 0x4040018 -#define mmnbif_gpu_LINK_CAP_swds 0x4040019 -#define mmnbif_gpu_LINK_CNTL_swds 0x404001A -#define mmnbif_gpu_LINK_STATUS_swds 0x404001A -#define mmnbif_gpu_SLOT_CAP_swds 0x404001B -#define mmnbif_gpu_SLOT_CNTL_swds 0x404001C -#define mmnbif_gpu_SLOT_STATUS_swds 0x404001C -#define mmnbif_gpu_DEVICE_CAP2_swds 0x404001F -#define mmnbif_gpu_DEVICE_CNTL2_swds 0x4040020 -#define mmnbif_gpu_DEVICE_STATUS2_swds 0x4040020 -#define mmnbif_gpu_LINK_CAP2_swds 0x4040021 -#define mmnbif_gpu_LINK_CNTL2_swds 0x4040022 -#define mmnbif_gpu_LINK_STATUS2_swds 0x4040022 -#define mmnbif_gpu_SLOT_CAP2_swds 0x4040023 -#define mmnbif_gpu_SLOT_CNTL2_swds 0x4040024 -#define mmnbif_gpu_SLOT_STATUS2_swds 0x4040024 -#define mmnbif_gpu_MSI_CAP_LIST_swds 0x4040028 -#define mmnbif_gpu_MSI_MSG_CNTL_swds 0x4040028 -#define mmnbif_gpu_MSI_MSG_ADDR_LO_swds 0x4040029 -#define mmnbif_gpu_MSI_MSG_ADDR_HI_swds 0x404002A -#define mmnbif_gpu_MSI_MSG_DATA_64_swds 0x404002B -#define mmnbif_gpu_MSI_MSG_DATA_swds 0x404002A -#define mmnbif_gpu_SSID_CAP_LIST_swds 0x4040030 -#define mmnbif_gpu_SSID_CAP_swds 0x4040031 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds 0x4040040 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds 0x4040041 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC1_swds 0x4040042 -#define mmnbif_gpu_PCIE_VENDOR_SPECIFIC2_swds 0x4040043 -#define mmnbif_gpu_PCIE_VC_ENH_CAP_LIST_swds 0x4040044 -#define mmnbif_gpu_PCIE_PORT_VC_CAP_REG1_swds 0x4040045 -#define mmnbif_gpu_PCIE_PORT_VC_CAP_REG2_swds 0x4040046 -#define mmnbif_gpu_PCIE_PORT_VC_CNTL_swds 0x4040047 -#define mmnbif_gpu_PCIE_PORT_VC_STATUS_swds 0x4040047 -#define mmnbif_gpu_PCIE_VC0_RESOURCE_CAP_swds 0x4040048 -#define mmnbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds 0x4040049 -#define mmnbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds 0x404004A -#define mmnbif_gpu_PCIE_VC1_RESOURCE_CAP_swds 0x404004B -#define mmnbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds 0x404004C -#define mmnbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds 0x404004D -#define mmnbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds 0x4040050 -#define mmnbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds 0x4040051 -#define mmnbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds 0x4040052 -#define mmnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds 0x4040054 -#define mmnbif_gpu_PCIE_UNCORR_ERR_STATUS_swds 0x4040055 -#define mmnbif_gpu_PCIE_UNCORR_ERR_MASK_swds 0x4040056 -#define mmnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds 0x4040057 -#define mmnbif_gpu_PCIE_CORR_ERR_STATUS_swds 0x4040058 -#define mmnbif_gpu_PCIE_CORR_ERR_MASK_swds 0x4040059 -#define mmnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds 0x404005A -#define mmnbif_gpu_PCIE_HDR_LOG0_swds 0x404005B -#define mmnbif_gpu_PCIE_HDR_LOG1_swds 0x404005C -#define mmnbif_gpu_PCIE_HDR_LOG2_swds 0x404005D -#define mmnbif_gpu_PCIE_HDR_LOG3_swds 0x404005E -#define mmnbif_gpu_PCIE_ROOT_ERR_CMD_swds 0x404005F -#define mmnbif_gpu_PCIE_ROOT_ERR_STATUS_swds 0x4040060 -#define mmnbif_gpu_PCIE_ERR_SRC_ID_swds 0x4040061 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG0_swds 0x4040062 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG1_swds 0x4040063 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG2_swds 0x4040064 -#define mmnbif_gpu_PCIE_TLP_PREFIX_LOG3_swds 0x4040065 -#define mmnbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds 0x404009C -#define mmnbif_gpu_PCIE_LINK_CNTL3_swds 0x404009D -#define mmnbif_gpu_PCIE_LANE_ERROR_STATUS_swds 0x404009E -#define mmnbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds 0x404009F -#define mmnbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds 0x404009F -#define mmnbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds 0x40400A0 -#define mmnbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds 0x40400A0 -#define mmnbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds 0x40400A1 -#define mmnbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds 0x40400A1 -#define mmnbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds 0x40400A2 -#define mmnbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds 0x40400A2 -#define mmnbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds 0x40400A3 -#define mmnbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds 0x40400A3 -#define mmnbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds 0x40400A4 -#define mmnbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds 0x40400A4 -#define mmnbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds 0x40400A5 -#define mmnbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds 0x40400A5 -#define mmnbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds 0x40400A6 -#define mmnbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds 0x40400A6 -#define mmnbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds 0x40400A8 -#define mmnbif_gpu_PCIE_ACS_CAP_swds 0x40400A9 -#define mmnbif_gpu_PCIE_ACS_CNTL_swds 0x40400A9 -#define pcinbif_gpu_VENDOR_ID_swds 0x0000 -#define cfgnbif_gpu_VENDOR_ID_swds 0x0000 -#define pcinbif_gpu_DEVICE_ID_swds 0x0000 -#define cfgnbif_gpu_DEVICE_ID_swds 0x0000 -#define pcinbif_gpu_COMMAND_swds 0x0001 -#define cfgnbif_gpu_COMMAND_swds 0x0001 -#define pcinbif_gpu_STATUS_swds 0x0001 -#define cfgnbif_gpu_STATUS_swds 0x0001 -#define pcinbif_gpu_REVISION_ID_swds 0x0002 -#define cfgnbif_gpu_REVISION_ID_swds 0x0002 -#define pcinbif_gpu_PROG_INTERFACE_swds 0x0002 -#define cfgnbif_gpu_PROG_INTERFACE_swds 0x0002 -#define pcinbif_gpu_SUB_CLASS_swds 0x0002 -#define cfgnbif_gpu_SUB_CLASS_swds 0x0002 -#define pcinbif_gpu_BASE_CLASS_swds 0x0002 -#define cfgnbif_gpu_BASE_CLASS_swds 0x0002 -#define pcinbif_gpu_CACHE_LINE_swds 0x0003 -#define cfgnbif_gpu_CACHE_LINE_swds 0x0003 -#define pcinbif_gpu_LATENCY_swds 0x0003 -#define cfgnbif_gpu_LATENCY_swds 0x0003 -#define pcinbif_gpu_HEADER_swds 0x0003 -#define cfgnbif_gpu_HEADER_swds 0x0003 -#define pcinbif_gpu_BIST_swds 0x0003 -#define cfgnbif_gpu_BIST_swds 0x0003 -#define pcinbif_gpu_BASE_ADDR_1_swds 0x0004 -#define cfgnbif_gpu_BASE_ADDR_1_swds 0x0004 -#define pcinbif_gpu_SUB_BUS_NUMBER_LATENCY_swds 0x0006 -#define cfgnbif_gpu_SUB_BUS_NUMBER_LATENCY_swds 0x0006 -#define pcinbif_gpu_IO_BASE_LIMIT_swds 0x0007 -#define cfgnbif_gpu_IO_BASE_LIMIT_swds 0x0007 -#define pcinbif_gpu_SECONDARY_STATUS_swds 0x0007 -#define cfgnbif_gpu_SECONDARY_STATUS_swds 0x0007 -#define pcinbif_gpu_MEM_BASE_LIMIT_swds 0x0008 -#define cfgnbif_gpu_MEM_BASE_LIMIT_swds 0x0008 -#define pcinbif_gpu_PREF_BASE_LIMIT_swds 0x0009 -#define cfgnbif_gpu_PREF_BASE_LIMIT_swds 0x0009 -#define pcinbif_gpu_PREF_BASE_UPPER_swds 0x000A -#define cfgnbif_gpu_PREF_BASE_UPPER_swds 0x000A -#define pcinbif_gpu_PREF_LIMIT_UPPER_swds 0x000B -#define cfgnbif_gpu_PREF_LIMIT_UPPER_swds 0x000B -#define pcinbif_gpu_IO_BASE_LIMIT_HI_swds 0x000C -#define cfgnbif_gpu_IO_BASE_LIMIT_HI_swds 0x000C -#define pcinbif_gpu_IRQ_BRIDGE_CNTL_swds 0x000F -#define cfgnbif_gpu_IRQ_BRIDGE_CNTL_swds 0x000F -#define pcinbif_gpu_CAP_PTR_swds 0x000D -#define cfgnbif_gpu_CAP_PTR_swds 0x000D -#define pcinbif_gpu_INTERRUPT_LINE_swds 0x000F -#define cfgnbif_gpu_INTERRUPT_LINE_swds 0x000F -#define pcinbif_gpu_INTERRUPT_PIN_swds 0x000F -#define cfgnbif_gpu_INTERRUPT_PIN_swds 0x000F -#define pcinbif_gpu_PMI_CAP_LIST_swds 0x0014 -#define cfgnbif_gpu_PMI_CAP_LIST_swds 0x0014 -#define pcinbif_gpu_PMI_CAP_swds 0x0014 -#define cfgnbif_gpu_PMI_CAP_swds 0x0014 -#define pcinbif_gpu_PMI_STATUS_CNTL_swds 0x0015 -#define cfgnbif_gpu_PMI_STATUS_CNTL_swds 0x0015 -#define pcinbif_gpu_PCIE_CAP_LIST_swds 0x0016 -#define cfgnbif_gpu_PCIE_CAP_LIST_swds 0x0016 -#define pcinbif_gpu_PCIE_CAP_swds 0x0016 -#define cfgnbif_gpu_PCIE_CAP_swds 0x0016 -#define pcinbif_gpu_DEVICE_CAP_swds 0x0017 -#define cfgnbif_gpu_DEVICE_CAP_swds 0x0017 -#define pcinbif_gpu_DEVICE_CNTL_swds 0x0018 -#define cfgnbif_gpu_DEVICE_CNTL_swds 0x0018 -#define pcinbif_gpu_DEVICE_STATUS_swds 0x0018 -#define cfgnbif_gpu_DEVICE_STATUS_swds 0x0018 -#define pcinbif_gpu_LINK_CAP_swds 0x0019 -#define cfgnbif_gpu_LINK_CAP_swds 0x0019 -#define pcinbif_gpu_LINK_CNTL_swds 0x001A -#define cfgnbif_gpu_LINK_CNTL_swds 0x001A -#define pcinbif_gpu_LINK_STATUS_swds 0x001A -#define cfgnbif_gpu_LINK_STATUS_swds 0x001A -#define pcinbif_gpu_SLOT_CAP_swds 0x001B -#define cfgnbif_gpu_SLOT_CAP_swds 0x001B -#define pcinbif_gpu_SLOT_CNTL_swds 0x001C -#define cfgnbif_gpu_SLOT_CNTL_swds 0x001C -#define pcinbif_gpu_SLOT_STATUS_swds 0x001C -#define cfgnbif_gpu_SLOT_STATUS_swds 0x001C -#define pcinbif_gpu_DEVICE_CAP2_swds 0x001F -#define cfgnbif_gpu_DEVICE_CAP2_swds 0x001F -#define pcinbif_gpu_DEVICE_CNTL2_swds 0x0020 -#define cfgnbif_gpu_DEVICE_CNTL2_swds 0x0020 -#define pcinbif_gpu_DEVICE_STATUS2_swds 0x0020 -#define cfgnbif_gpu_DEVICE_STATUS2_swds 0x0020 -#define pcinbif_gpu_LINK_CAP2_swds 0x0021 -#define cfgnbif_gpu_LINK_CAP2_swds 0x0021 -#define pcinbif_gpu_LINK_CNTL2_swds 0x0022 -#define cfgnbif_gpu_LINK_CNTL2_swds 0x0022 -#define pcinbif_gpu_LINK_STATUS2_swds 0x0022 -#define cfgnbif_gpu_LINK_STATUS2_swds 0x0022 -#define pcinbif_gpu_SLOT_CAP2_swds 0x0023 -#define cfgnbif_gpu_SLOT_CAP2_swds 0x0023 -#define pcinbif_gpu_SLOT_CNTL2_swds 0x0024 -#define cfgnbif_gpu_SLOT_CNTL2_swds 0x0024 -#define pcinbif_gpu_SLOT_STATUS2_swds 0x0024 -#define cfgnbif_gpu_SLOT_STATUS2_swds 0x0024 -#define pcinbif_gpu_MSI_CAP_LIST_swds 0x0028 -#define cfgnbif_gpu_MSI_CAP_LIST_swds 0x0028 -#define pcinbif_gpu_MSI_MSG_CNTL_swds 0x0028 -#define cfgnbif_gpu_MSI_MSG_CNTL_swds 0x0028 -#define pcinbif_gpu_MSI_MSG_ADDR_LO_swds 0x0029 -#define cfgnbif_gpu_MSI_MSG_ADDR_LO_swds 0x0029 -#define pcinbif_gpu_MSI_MSG_ADDR_HI_swds 0x002A -#define cfgnbif_gpu_MSI_MSG_ADDR_HI_swds 0x002A -#define pcinbif_gpu_MSI_MSG_DATA_64_swds 0x002B -#define cfgnbif_gpu_MSI_MSG_DATA_64_swds 0x002B -#define pcinbif_gpu_MSI_MSG_DATA_swds 0x002A -#define cfgnbif_gpu_MSI_MSG_DATA_swds 0x002A -#define pcinbif_gpu_SSID_CAP_LIST_swds 0x0030 -#define cfgnbif_gpu_SSID_CAP_LIST_swds 0x0030 -#define pcinbif_gpu_SSID_CAP_swds 0x0031 -#define cfgnbif_gpu_SSID_CAP_swds 0x0031 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds 0x0040 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds 0x0040 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds 0x0041 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds 0x0041 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC1_swds 0x0042 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC1_swds 0x0042 -#define pcinbif_gpu_PCIE_VENDOR_SPECIFIC2_swds 0x0043 -#define cfgnbif_gpu_PCIE_VENDOR_SPECIFIC2_swds 0x0043 -#define pcinbif_gpu_PCIE_VC_ENH_CAP_LIST_swds 0x0044 -#define cfgnbif_gpu_PCIE_VC_ENH_CAP_LIST_swds 0x0044 -#define pcinbif_gpu_PCIE_PORT_VC_CAP_REG1_swds 0x0045 -#define cfgnbif_gpu_PCIE_PORT_VC_CAP_REG1_swds 0x0045 -#define pcinbif_gpu_PCIE_PORT_VC_CAP_REG2_swds 0x0046 -#define cfgnbif_gpu_PCIE_PORT_VC_CAP_REG2_swds 0x0046 -#define pcinbif_gpu_PCIE_PORT_VC_CNTL_swds 0x0047 -#define cfgnbif_gpu_PCIE_PORT_VC_CNTL_swds 0x0047 -#define pcinbif_gpu_PCIE_PORT_VC_STATUS_swds 0x0047 -#define cfgnbif_gpu_PCIE_PORT_VC_STATUS_swds 0x0047 -#define pcinbif_gpu_PCIE_VC0_RESOURCE_CAP_swds 0x0048 -#define cfgnbif_gpu_PCIE_VC0_RESOURCE_CAP_swds 0x0048 -#define pcinbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds 0x0049 -#define cfgnbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds 0x0049 -#define pcinbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds 0x004A -#define cfgnbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds 0x004A -#define pcinbif_gpu_PCIE_VC1_RESOURCE_CAP_swds 0x004B -#define cfgnbif_gpu_PCIE_VC1_RESOURCE_CAP_swds 0x004B -#define pcinbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds 0x004C -#define cfgnbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds 0x004C -#define pcinbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds 0x004D -#define cfgnbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds 0x004D -#define pcinbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds 0x0050 -#define cfgnbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds 0x0050 -#define pcinbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds 0x0051 -#define cfgnbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds 0x0051 -#define pcinbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds 0x0052 -#define cfgnbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds 0x0052 -#define pcinbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds 0x0054 -#define cfgnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds 0x0054 -#define pcinbif_gpu_PCIE_UNCORR_ERR_STATUS_swds 0x0055 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_STATUS_swds 0x0055 -#define pcinbif_gpu_PCIE_UNCORR_ERR_MASK_swds 0x0056 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_MASK_swds 0x0056 -#define pcinbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds 0x0057 -#define cfgnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds 0x0057 -#define pcinbif_gpu_PCIE_CORR_ERR_STATUS_swds 0x0058 -#define cfgnbif_gpu_PCIE_CORR_ERR_STATUS_swds 0x0058 -#define pcinbif_gpu_PCIE_CORR_ERR_MASK_swds 0x0059 -#define cfgnbif_gpu_PCIE_CORR_ERR_MASK_swds 0x0059 -#define pcinbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds 0x005A -#define cfgnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds 0x005A -#define pcinbif_gpu_PCIE_HDR_LOG0_swds 0x005B -#define cfgnbif_gpu_PCIE_HDR_LOG0_swds 0x005B -#define pcinbif_gpu_PCIE_HDR_LOG1_swds 0x005C -#define cfgnbif_gpu_PCIE_HDR_LOG1_swds 0x005C -#define pcinbif_gpu_PCIE_HDR_LOG2_swds 0x005D -#define cfgnbif_gpu_PCIE_HDR_LOG2_swds 0x005D -#define pcinbif_gpu_PCIE_HDR_LOG3_swds 0x005E -#define cfgnbif_gpu_PCIE_HDR_LOG3_swds 0x005E -#define pcinbif_gpu_PCIE_ROOT_ERR_CMD_swds 0x005F -#define cfgnbif_gpu_PCIE_ROOT_ERR_CMD_swds 0x005F -#define pcinbif_gpu_PCIE_ROOT_ERR_STATUS_swds 0x0060 -#define cfgnbif_gpu_PCIE_ROOT_ERR_STATUS_swds 0x0060 -#define pcinbif_gpu_PCIE_ERR_SRC_ID_swds 0x0061 -#define cfgnbif_gpu_PCIE_ERR_SRC_ID_swds 0x0061 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG0_swds 0x0062 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG0_swds 0x0062 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG1_swds 0x0063 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG1_swds 0x0063 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG2_swds 0x0064 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG2_swds 0x0064 -#define pcinbif_gpu_PCIE_TLP_PREFIX_LOG3_swds 0x0065 -#define cfgnbif_gpu_PCIE_TLP_PREFIX_LOG3_swds 0x0065 -#define pcinbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds 0x009C -#define cfgnbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds 0x009C -#define pcinbif_gpu_PCIE_LINK_CNTL3_swds 0x009D -#define cfgnbif_gpu_PCIE_LINK_CNTL3_swds 0x009D -#define pcinbif_gpu_PCIE_LANE_ERROR_STATUS_swds 0x009E -#define cfgnbif_gpu_PCIE_LANE_ERROR_STATUS_swds 0x009E -#define pcinbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds 0x009F -#define cfgnbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds 0x009F -#define pcinbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds 0x009F -#define cfgnbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds 0x009F -#define pcinbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds 0x00A0 -#define cfgnbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds 0x00A0 -#define pcinbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds 0x00A0 -#define cfgnbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds 0x00A0 -#define pcinbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds 0x00A1 -#define cfgnbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds 0x00A1 -#define pcinbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds 0x00A1 -#define cfgnbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds 0x00A1 -#define pcinbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds 0x00A2 -#define cfgnbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds 0x00A2 -#define pcinbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds 0x00A2 -#define cfgnbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds 0x00A2 -#define pcinbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds 0x00A3 -#define cfgnbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds 0x00A3 -#define pcinbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds 0x00A3 -#define cfgnbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds 0x00A3 -#define pcinbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds 0x00A4 -#define cfgnbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds 0x00A4 -#define pcinbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds 0x00A4 -#define cfgnbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds 0x00A4 -#define pcinbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds 0x00A5 -#define cfgnbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds 0x00A5 -#define pcinbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds 0x00A5 -#define cfgnbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds 0x00A5 -#define pcinbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds 0x00A6 -#define cfgnbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds 0x00A6 -#define pcinbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds 0x00A6 -#define cfgnbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds 0x00A6 -#define pcinbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds 0x00A8 -#define cfgnbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds 0x00A8 -#define pcinbif_gpu_PCIE_ACS_CAP_swds 0x00A9 -#define cfgnbif_gpu_PCIE_ACS_CAP_swds 0x00A9 -#define pcinbif_gpu_PCIE_ACS_CNTL_swds 0x00A9 -#define cfgnbif_gpu_PCIE_ACS_CNTL_swds 0x00A9 - - -// Registers from BIF_CFG_RC block - - -// Registers from RCC_SHADOW_REG block - -#define mmnbif_gpu_SHADOW_COMMAND 0x404C001 -#define mmnbif_gpu_SHADOW_BASE_ADDR_1 0x404C004 -#define mmnbif_gpu_SHADOW_BASE_ADDR_2 0x404C005 -#define mmnbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY 0x404C006 -#define mmnbif_gpu_SHADOW_IO_BASE_LIMIT 0x404C007 -#define mmnbif_gpu_SHADOW_MEM_BASE_LIMIT 0x404C008 -#define mmnbif_gpu_SHADOW_PREF_BASE_LIMIT 0x404C009 -#define mmnbif_gpu_SHADOW_PREF_BASE_UPPER 0x404C00A -#define mmnbif_gpu_SHADOW_PREF_LIMIT_UPPER 0x404C00B -#define mmnbif_gpu_SHADOW_IO_BASE_LIMIT_HI 0x404C00C -#define mmnbif_gpu_SHADOW_IRQ_BRIDGE_CNTL 0x404C00F -#define mmnbif_gpu_SUC_INDEX 0x404C038 -#define mmnbif_gpu_SUC_DATA 0x404C039 -#define pcinbif_gpu_SHADOW_COMMAND 0x0001 -#define cfgnbif_gpu_SHADOW_COMMAND 0x0001 -#define pcinbif_gpu_SHADOW_BASE_ADDR_1 0x0004 -#define cfgnbif_gpu_SHADOW_BASE_ADDR_1 0x0004 -#define pcinbif_gpu_SHADOW_BASE_ADDR_2 0x0005 -#define cfgnbif_gpu_SHADOW_BASE_ADDR_2 0x0005 -#define pcinbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY 0x0006 -#define cfgnbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY 0x0006 -#define pcinbif_gpu_SHADOW_IO_BASE_LIMIT 0x0007 -#define cfgnbif_gpu_SHADOW_IO_BASE_LIMIT 0x0007 -#define pcinbif_gpu_SHADOW_MEM_BASE_LIMIT 0x0008 -#define cfgnbif_gpu_SHADOW_MEM_BASE_LIMIT 0x0008 -#define pcinbif_gpu_SHADOW_PREF_BASE_LIMIT 0x0009 -#define cfgnbif_gpu_SHADOW_PREF_BASE_LIMIT 0x0009 -#define pcinbif_gpu_SHADOW_PREF_BASE_UPPER 0x000A -#define cfgnbif_gpu_SHADOW_PREF_BASE_UPPER 0x000A -#define pcinbif_gpu_SHADOW_PREF_LIMIT_UPPER 0x000B -#define cfgnbif_gpu_SHADOW_PREF_LIMIT_UPPER 0x000B -#define pcinbif_gpu_SHADOW_IO_BASE_LIMIT_HI 0x000C -#define cfgnbif_gpu_SHADOW_IO_BASE_LIMIT_HI 0x000C -#define pcinbif_gpu_SHADOW_IRQ_BRIDGE_CNTL 0x000F -#define cfgnbif_gpu_SHADOW_IRQ_BRIDGE_CNTL 0x000F - - -// Registers from RCC_EP block - -#define mmnbif_gpu_EP_PCIE_SCRATCH 0x0D43 -#define mmnbif_gpu_EP_PCIE_SCRATCH_alt_1 0x4048D43 -#define mmnbif_gpu_EP_PCIE_HW_DEBUG 0x0D44 -#define mmnbif_gpu_EP_PCIE_HW_DEBUG_alt_1 0x4048D44 -#define mmnbif_gpu_EP_PCIE_CNTL 0x0D45 -#define mmnbif_gpu_EP_PCIE_CNTL_alt_1 0x4048D45 -#define mmnbif_gpu_EP_PCIE_INT_CNTL 0x0D46 -#define mmnbif_gpu_EP_PCIE_INT_CNTL_alt_1 0x4048D46 -#define mmnbif_gpu_EP_PCIE_INT_STATUS 0x0D47 -#define mmnbif_gpu_EP_PCIE_INT_STATUS_alt_1 0x4048D47 -#define mmnbif_gpu_EP_PCIE_RX_CNTL2 0x0D48 -#define mmnbif_gpu_EP_PCIE_RX_CNTL2_alt_1 0x4048D48 -#define mmnbif_gpu_EP_PCIE_BUS_CNTL 0x0D49 -#define mmnbif_gpu_EP_PCIE_BUS_CNTL_alt_1 0x4048D49 -#define mmnbif_gpu_EP_PCIE_CFG_CNTL 0x0D4A -#define mmnbif_gpu_EP_PCIE_CFG_CNTL_alt_1 0x4048D4A -#define mmnbif_gpu_EP_PCIE_OBFF_CNTL 0x0D4B -#define mmnbif_gpu_EP_PCIE_OBFF_CNTL_alt_1 0x4048D4B -#define mmnbif_gpu_EP_PCIE_TX_LTR_CNTL 0x0D4C -#define mmnbif_gpu_EP_PCIE_TX_LTR_CNTL_alt_1 0x4048D4C -#define mmnbif_gpu_EP_PCIE_STRAP_MISC 0x0D4F -#define mmnbif_gpu_EP_PCIE_STRAP_MISC_alt_1 0x4048D4F -#define mmnbif_gpu_EP_PCIE_STRAP_MISC2 0x0D50 -#define mmnbif_gpu_EP_PCIE_STRAP_MISC2_alt_1 0x4048D50 -#define mmnbif_gpu_EP_PCIE_STRAP_PI 0x0D51 -#define mmnbif_gpu_EP_PCIE_STRAP_PI_alt_1 0x4048D51 -#define mmnbif_gpu_EP_PCIE_F0_DPA_CAP 0x0D52 -#define mmnbif_gpu_EP_PCIE_F0_DPA_CAP_alt_1 0x4048D52 -#define mmnbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0D53 -#define mmnbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR_alt_1 0x4048D53 -#define mmnbif_gpu_EP_PCIE_F0_DPA_CNTL 0x0D53 -#define mmnbif_gpu_EP_PCIE_F0_DPA_CNTL_alt_1 0x4048D53 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0D53 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_alt_1 0x4048D53 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_alt_1 0x4048D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_alt_1 0x4048D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_alt_1 0x4048D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_alt_1 0x4048D54 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0D55 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_alt_1 0x4048D55 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0D55 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_alt_1 0x4048D55 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0D55 -#define mmnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_alt_1 0x4048D55 -#define mmnbif_gpu_EP_PCIE_PME_CONTROL 0x0D55 -#define mmnbif_gpu_EP_PCIE_PME_CONTROL_alt_1 0x4048D55 -#define mmnbif_gpu_EP_PCIEP_RESERVED 0x0D56 -#define mmnbif_gpu_EP_PCIEP_RESERVED_alt_1 0x4048D56 -#define mmnbif_gpu_EP_PCIEP_HW_DEBUG 0x0D57 -#define mmnbif_gpu_EP_PCIEP_HW_DEBUG_alt_1 0x4048D57 -#define mmnbif_gpu_EP_PCIE_TX_CNTL 0x0D58 -#define mmnbif_gpu_EP_PCIE_TX_CNTL_alt_1 0x4048D58 -#define mmnbif_gpu_EP_PCIE_TX_REQUESTER_ID 0x0D59 -#define mmnbif_gpu_EP_PCIE_TX_REQUESTER_ID_alt_1 0x4048D59 -#define mmnbif_gpu_EP_PCIE_ERR_CNTL 0x0D5A -#define mmnbif_gpu_EP_PCIE_ERR_CNTL_alt_1 0x4048D5A -#define mmnbif_gpu_EP_PCIE_RX_CNTL 0x0D5B -#define mmnbif_gpu_EP_PCIE_RX_CNTL_alt_1 0x4048D5B -#define mmnbif_gpu_EP_PCIE_LC_SPEED_CNTL 0x0D5C -#define mmnbif_gpu_EP_PCIE_LC_SPEED_CNTL_alt_1 0x4048D5C - - -// Registers from GDC block - -#define mmnbif_gpu_A2S_CNTL_CL0 0x0EB0 -#define mmnbif_gpu_A2S_CNTL_CL0_alt_1 0x500EB0 -#define mmnbif_gpu_A2S_CNTL_CL1 0x0EB1 -#define mmnbif_gpu_A2S_CNTL_CL1_alt_1 0x500EB1 -#define mmnbif_gpu_A2S_CNTL_CL2 0x0EB2 -#define mmnbif_gpu_A2S_CNTL_CL2_alt_1 0x500EB2 -#define mmnbif_gpu_A2S_CNTL_CL3 0x0EB3 -#define mmnbif_gpu_A2S_CNTL_CL3_alt_1 0x500EB3 -#define mmnbif_gpu_A2S_CNTL_CL4 0x0EB4 -#define mmnbif_gpu_A2S_CNTL_CL4_alt_1 0x500EB4 -#define mmnbif_gpu_A2S_CNTL_SW0 0x0ED0 -#define mmnbif_gpu_A2S_CNTL_SW0_alt_1 0x500ED0 -#define mmnbif_gpu_A2S_CNTL_SW1 0x0ED1 -#define mmnbif_gpu_A2S_CNTL_SW1_alt_1 0x500ED1 -#define mmnbif_gpu_A2S_CNTL_SW2 0x0ED2 -#define mmnbif_gpu_A2S_CNTL_SW2_alt_1 0x500ED2 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL0 0x0F00 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL0_alt_1 0x500F00 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL1 0x0F01 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL1_alt_1 0x500F01 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL2 0x0F02 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL2_alt_1 0x500F02 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL3 0x0F03 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL3_alt_1 0x500F03 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL4 0x0F04 -#define mmnbif_gpu_A2S_CNTL2_SEC_CL4_alt_1 0x500F04 -#define mmnbif_gpu_NGDC_MGCG_CTRL 0x0EE0 -#define mmnbif_gpu_NGDC_MGCG_CTRL_alt_1 0x500EE0 -#define mmnbif_gpu_A2S_MISC_CNTL 0x0EE1 -#define mmnbif_gpu_A2S_MISC_CNTL_alt_1 0x500EE1 -#define mmnbif_gpu_NGDC_SDP_PORT_CTRL 0x0EE2 -#define mmnbif_gpu_NGDC_SDP_PORT_CTRL_alt_1 0x500EE2 -#define mmnbif_gpu_BIF_SDMA0_DOORBELL_RANGE 0x0EF0 -#define mmnbif_gpu_BIF_SDMA0_DOORBELL_RANGE_alt_1 0x500EF0 -#define mmnbif_gpu_BIF_SDMA1_DOORBELL_RANGE 0x0EF1 -#define mmnbif_gpu_BIF_SDMA1_DOORBELL_RANGE_alt_1 0x500EF1 -#define mmnbif_gpu_BIF_IH_DOORBELL_RANGE 0x0EF2 -#define mmnbif_gpu_BIF_IH_DOORBELL_RANGE_alt_1 0x500EF2 -#define mmnbif_gpu_BIF_MMSCH0_DOORBELL_RANGE 0x0EF3 -#define mmnbif_gpu_BIF_MMSCH0_DOORBELL_RANGE_alt_1 0x500EF3 -#define mmnbif_gpu_S2A_MISC_CNTL 0x0EFF -#define mmnbif_gpu_S2A_MISC_CNTL_alt_1 0x500EFF - - -// Registers from GDC_RAS block - -#define mmnbif_gpu_GDC_RAS_LEAF0_CTRL 0x507E00 -#define mmnbif_gpu_GDC_RAS_LEAF1_CTRL 0x507E01 -#define mmnbif_gpu_GDC_RAS_LEAF2_CTRL 0x507E02 -#define mmnbif_gpu_GDC_RAS_LEAF3_CTRL 0x507E03 -#define mmnbif_gpu_GDC_RAS_LEAF4_CTRL 0x507E04 -#define mmnbif_gpu_GDC_RAS_LEAF5_CTRL 0x507E05 - - -// Registers from NBIF_SION block - -#define mmnbif_gpu_SION_CL0_RdRsp_BurstTarget_REG0 0x507800 -#define mmnbif_gpu_SION_CL0_RdRsp_BurstTarget_REG1 0x507801 -#define mmnbif_gpu_SION_CL0_RdRsp_TimeSlot_REG0 0x507802 -#define mmnbif_gpu_SION_CL0_RdRsp_TimeSlot_REG1 0x507803 -#define mmnbif_gpu_SION_CL0_WrRsp_BurstTarget_REG0 0x507804 -#define mmnbif_gpu_SION_CL0_WrRsp_BurstTarget_REG1 0x507805 -#define mmnbif_gpu_SION_CL0_WrRsp_TimeSlot_REG0 0x507806 -#define mmnbif_gpu_SION_CL0_WrRsp_TimeSlot_REG1 0x507807 -#define mmnbif_gpu_SION_CL0_Req_BurstTarget_REG0 0x507808 -#define mmnbif_gpu_SION_CL0_Req_BurstTarget_REG1 0x507809 -#define mmnbif_gpu_SION_CL0_Req_TimeSlot_REG0 0x50780A -#define mmnbif_gpu_SION_CL0_Req_TimeSlot_REG1 0x50780B -#define mmnbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG0 0x50780C -#define mmnbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG1 0x50780D -#define mmnbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG0 0x50780E -#define mmnbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG1 0x50780F -#define mmnbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x507810 -#define mmnbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x507811 -#define mmnbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x507812 -#define mmnbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x507813 -#define mmnbif_gpu_SION_CL1_RdRsp_BurstTarget_REG0 0x507814 -#define mmnbif_gpu_SION_CL1_RdRsp_BurstTarget_REG1 0x507815 -#define mmnbif_gpu_SION_CL1_RdRsp_TimeSlot_REG0 0x507816 -#define mmnbif_gpu_SION_CL1_RdRsp_TimeSlot_REG1 0x507817 -#define mmnbif_gpu_SION_CL1_WrRsp_BurstTarget_REG0 0x507818 -#define mmnbif_gpu_SION_CL1_WrRsp_BurstTarget_REG1 0x507819 -#define mmnbif_gpu_SION_CL1_WrRsp_TimeSlot_REG0 0x50781A -#define mmnbif_gpu_SION_CL1_WrRsp_TimeSlot_REG1 0x50781B -#define mmnbif_gpu_SION_CL1_Req_BurstTarget_REG0 0x50781C -#define mmnbif_gpu_SION_CL1_Req_BurstTarget_REG1 0x50781D -#define mmnbif_gpu_SION_CL1_Req_TimeSlot_REG0 0x50781E -#define mmnbif_gpu_SION_CL1_Req_TimeSlot_REG1 0x50781F -#define mmnbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG0 0x507820 -#define mmnbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG1 0x507821 -#define mmnbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG0 0x507822 -#define mmnbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG1 0x507823 -#define mmnbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x507824 -#define mmnbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x507825 -#define mmnbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x507826 -#define mmnbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x507827 -#define mmnbif_gpu_SION_CL2_RdRsp_BurstTarget_REG0 0x507828 -#define mmnbif_gpu_SION_CL2_RdRsp_BurstTarget_REG1 0x507829 -#define mmnbif_gpu_SION_CL2_RdRsp_TimeSlot_REG0 0x50782A -#define mmnbif_gpu_SION_CL2_RdRsp_TimeSlot_REG1 0x50782B -#define mmnbif_gpu_SION_CL2_WrRsp_BurstTarget_REG0 0x50782C -#define mmnbif_gpu_SION_CL2_WrRsp_BurstTarget_REG1 0x50782D -#define mmnbif_gpu_SION_CL2_WrRsp_TimeSlot_REG0 0x50782E -#define mmnbif_gpu_SION_CL2_WrRsp_TimeSlot_REG1 0x50782F -#define mmnbif_gpu_SION_CL2_Req_BurstTarget_REG0 0x507830 -#define mmnbif_gpu_SION_CL2_Req_BurstTarget_REG1 0x507831 -#define mmnbif_gpu_SION_CL2_Req_TimeSlot_REG0 0x507832 -#define mmnbif_gpu_SION_CL2_Req_TimeSlot_REG1 0x507833 -#define mmnbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG0 0x507834 -#define mmnbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG1 0x507835 -#define mmnbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG0 0x507836 -#define mmnbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG1 0x507837 -#define mmnbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x507838 -#define mmnbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x507839 -#define mmnbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x50783A -#define mmnbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x50783B -#define mmnbif_gpu_SION_CL3_RdRsp_BurstTarget_REG0 0x50783C -#define mmnbif_gpu_SION_CL3_RdRsp_BurstTarget_REG1 0x50783D -#define mmnbif_gpu_SION_CL3_RdRsp_TimeSlot_REG0 0x50783E -#define mmnbif_gpu_SION_CL3_RdRsp_TimeSlot_REG1 0x50783F -#define mmnbif_gpu_SION_CL3_WrRsp_BurstTarget_REG0 0x507840 -#define mmnbif_gpu_SION_CL3_WrRsp_BurstTarget_REG1 0x507841 -#define mmnbif_gpu_SION_CL3_WrRsp_TimeSlot_REG0 0x507842 -#define mmnbif_gpu_SION_CL3_WrRsp_TimeSlot_REG1 0x507843 -#define mmnbif_gpu_SION_CL3_Req_BurstTarget_REG0 0x507844 -#define mmnbif_gpu_SION_CL3_Req_BurstTarget_REG1 0x507845 -#define mmnbif_gpu_SION_CL3_Req_TimeSlot_REG0 0x507846 -#define mmnbif_gpu_SION_CL3_Req_TimeSlot_REG1 0x507847 -#define mmnbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG0 0x507848 -#define mmnbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG1 0x507849 -#define mmnbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG0 0x50784A -#define mmnbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG1 0x50784B -#define mmnbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG0 0x50784C -#define mmnbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG1 0x50784D -#define mmnbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG0 0x50784E -#define mmnbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG1 0x50784F -#define mmnbif_gpu_SION_CL4_RdRsp_BurstTarget_REG0 0x507850 -#define mmnbif_gpu_SION_CL4_RdRsp_BurstTarget_REG1 0x507851 -#define mmnbif_gpu_SION_CL4_RdRsp_TimeSlot_REG0 0x507852 -#define mmnbif_gpu_SION_CL4_RdRsp_TimeSlot_REG1 0x507853 -#define mmnbif_gpu_SION_CL4_WrRsp_BurstTarget_REG0 0x507854 -#define mmnbif_gpu_SION_CL4_WrRsp_BurstTarget_REG1 0x507855 -#define mmnbif_gpu_SION_CL4_WrRsp_TimeSlot_REG0 0x507856 -#define mmnbif_gpu_SION_CL4_WrRsp_TimeSlot_REG1 0x507857 -#define mmnbif_gpu_SION_CL4_Req_BurstTarget_REG0 0x507858 -#define mmnbif_gpu_SION_CL4_Req_BurstTarget_REG1 0x507859 -#define mmnbif_gpu_SION_CL4_Req_TimeSlot_REG0 0x50785A -#define mmnbif_gpu_SION_CL4_Req_TimeSlot_REG1 0x50785B -#define mmnbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG0 0x50785C -#define mmnbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG1 0x50785D -#define mmnbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG0 0x50785E -#define mmnbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG1 0x50785F -#define mmnbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG0 0x507860 -#define mmnbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG1 0x507861 -#define mmnbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG0 0x507862 -#define mmnbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG1 0x507863 -#define mmnbif_gpu_SION_CL5_RdRsp_BurstTarget_REG0 0x507864 -#define mmnbif_gpu_SION_CL5_RdRsp_BurstTarget_REG1 0x507865 -#define mmnbif_gpu_SION_CL5_RdRsp_TimeSlot_REG0 0x507866 -#define mmnbif_gpu_SION_CL5_RdRsp_TimeSlot_REG1 0x507867 -#define mmnbif_gpu_SION_CL5_WrRsp_BurstTarget_REG0 0x507868 -#define mmnbif_gpu_SION_CL5_WrRsp_BurstTarget_REG1 0x507869 -#define mmnbif_gpu_SION_CL5_WrRsp_TimeSlot_REG0 0x50786A -#define mmnbif_gpu_SION_CL5_WrRsp_TimeSlot_REG1 0x50786B -#define mmnbif_gpu_SION_CL5_Req_BurstTarget_REG0 0x50786C -#define mmnbif_gpu_SION_CL5_Req_BurstTarget_REG1 0x50786D -#define mmnbif_gpu_SION_CL5_Req_TimeSlot_REG0 0x50786E -#define mmnbif_gpu_SION_CL5_Req_TimeSlot_REG1 0x50786F -#define mmnbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG0 0x507870 -#define mmnbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG1 0x507871 -#define mmnbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG0 0x507872 -#define mmnbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG1 0x507873 -#define mmnbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG0 0x507874 -#define mmnbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG1 0x507875 -#define mmnbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG0 0x507876 -#define mmnbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG1 0x507877 -#define mmnbif_gpu_SION_CNTL_REG0 0x507878 -#define mmnbif_gpu_SION_CNTL_REG1 0x507879 - - -// Registers from RCC_STRAP block - -#define mmnbif_gpu_RCC_BIF_STRAP0 0x0D20 -#define mmnbif_gpu_RCC_BIF_STRAP0_alt_1 0x4048D20 -#define mmnbif_gpu_RCC_BIF_STRAP0_alt_2 0x404C500 -#define mmnbif_gpu_RCC_BIF_STRAP1 0x0D21 -#define mmnbif_gpu_RCC_BIF_STRAP1_alt_1 0x4048D21 -#define mmnbif_gpu_RCC_BIF_STRAP1_alt_2 0x404C501 -#define mmnbif_gpu_RCC_BIF_STRAP2 0x0D22 -#define mmnbif_gpu_RCC_BIF_STRAP2_alt_1 0x4048D22 -#define mmnbif_gpu_RCC_BIF_STRAP2_alt_2 0x404C502 -#define mmnbif_gpu_RCC_BIF_STRAP3 0x0D23 -#define mmnbif_gpu_RCC_BIF_STRAP3_alt_1 0x4048D23 -#define mmnbif_gpu_RCC_BIF_STRAP3_alt_2 0x404C503 -#define mmnbif_gpu_RCC_BIF_STRAP4 0x0D24 -#define mmnbif_gpu_RCC_BIF_STRAP4_alt_1 0x4048D24 -#define mmnbif_gpu_RCC_BIF_STRAP4_alt_2 0x404C504 -#define mmnbif_gpu_RCC_BIF_STRAP5 0x0D25 -#define mmnbif_gpu_RCC_BIF_STRAP5_alt_1 0x4048D25 -#define mmnbif_gpu_RCC_BIF_STRAP5_alt_2 0x404C505 -#define mmnbif_gpu_RCC_BIF_STRAP6 0x0D26 -#define mmnbif_gpu_RCC_BIF_STRAP6_alt_1 0x4048D26 -#define mmnbif_gpu_RCC_BIF_STRAP6_alt_2 0x404C506 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP0 0x0D27 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP0_alt_1 0x4048D27 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP0_alt_2 0x404C400 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP1 0x0D28 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP1_alt_1 0x4048D28 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP1_alt_2 0x404C401 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP2 0x0D29 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP2_alt_1 0x4048D29 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP2_alt_2 0x404C402 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP3 0x0D2A -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP3_alt_1 0x4048D2A -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP3_alt_2 0x404C403 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP4 0x0D2B -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP4_alt_1 0x4048D2B -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP4_alt_2 0x404C404 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP5 0x0D2C -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP5_alt_1 0x4048D2C -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP5_alt_2 0x404C405 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP6 0x0D2D -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP6_alt_1 0x4048D2D -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP6_alt_2 0x404C406 -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP7 0x0D2E -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP7_alt_1 0x4048D2E -#define mmnbif_gpu_RCC_DEV0_PORT_STRAP7_alt_2 0x404C407 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP0 0x0D2F -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP0_alt_1 0x4048D2F -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP0_alt_2 0x404D000 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP1 0x0D30 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP1_alt_1 0x4048D30 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP1_alt_2 0x404D001 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP13 0x0D31 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP13_alt_1 0x4048D31 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP13_alt_2 0x404D00D -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP2 0x0D32 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP2_alt_1 0x4048D32 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP2_alt_2 0x404D002 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP3 0x0D33 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP3_alt_1 0x4048D33 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP3_alt_2 0x404D003 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP4 0x0D34 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP4_alt_1 0x4048D34 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP4_alt_2 0x404D004 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP5 0x0D35 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP5_alt_1 0x4048D35 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP5_alt_2 0x404D005 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP8 0x0D36 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP8_alt_1 0x4048D36 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP8_alt_2 0x404D008 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP9 0x0D37 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP9_alt_1 0x4048D37 -#define mmnbif_gpu_RCC_DEV0_EPF0_STRAP9_alt_2 0x404D009 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP0 0x0D38 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP0_alt_1 0x4048D38 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP0_alt_2 0x404D080 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP10 0x0D39 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP10_alt_1 0x4048D39 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP10_alt_2 0x404D08A -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP11 0x0D3A -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP11_alt_1 0x4048D3A -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP11_alt_2 0x404D08B -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP12 0x0D3B -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP12_alt_1 0x4048D3B -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP12_alt_2 0x404D08C -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP13 0x0D3C -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP13_alt_1 0x4048D3C -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP13_alt_2 0x404D08D -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP2 0x0D3D -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP2_alt_1 0x4048D3D -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP2_alt_2 0x404D082 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP3 0x0D3E -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP3_alt_1 0x4048D3E -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP3_alt_2 0x404D083 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP4 0x0D3F -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP4_alt_1 0x4048D3F -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP4_alt_2 0x404D084 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP5 0x0D40 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP5_alt_1 0x4048D40 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP5_alt_2 0x404D085 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP6 0x0D41 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP6_alt_1 0x4048D41 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP6_alt_2 0x404D086 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP7 0x0D42 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP7_alt_1 0x4048D42 -#define mmnbif_gpu_RCC_DEV0_EPF1_STRAP7_alt_2 0x404D087 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP0 0x404C480 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP1 0x404C481 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP2 0x404C482 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP3 0x404C483 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP4 0x404C484 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP5 0x404C485 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP6 0x404C486 -#define mmnbif_gpu_RCC_DEV1_PORT_STRAP7 0x404C487 -#define mmnbif_gpu_RCC_DEV0_EPF2_STRAP0 0x404D100 -#define mmnbif_gpu_RCC_DEV0_EPF2_STRAP13 0x404D10D -#define mmnbif_gpu_RCC_DEV0_EPF2_STRAP2 0x404D102 -#define mmnbif_gpu_RCC_DEV0_EPF2_STRAP3 0x404D103 -#define mmnbif_gpu_RCC_DEV0_EPF2_STRAP4 0x404D104 -#define mmnbif_gpu_RCC_DEV0_EPF2_STRAP5 0x404D105 -#define mmnbif_gpu_RCC_DEV0_EPF2_STRAP6 0x404D106 -#define mmnbif_gpu_RCC_DEV0_EPF3_STRAP0 0x404D180 -#define mmnbif_gpu_RCC_DEV0_EPF3_STRAP13 0x404D18D -#define mmnbif_gpu_RCC_DEV0_EPF3_STRAP2 0x404D182 -#define mmnbif_gpu_RCC_DEV0_EPF3_STRAP3 0x404D183 -#define mmnbif_gpu_RCC_DEV0_EPF3_STRAP4 0x404D184 -#define mmnbif_gpu_RCC_DEV0_EPF3_STRAP5 0x404D185 -#define mmnbif_gpu_RCC_DEV0_EPF3_STRAP6 0x404D186 -#define mmnbif_gpu_RCC_DEV0_EPF4_STRAP0 0x404D200 -#define mmnbif_gpu_RCC_DEV0_EPF4_STRAP13 0x404D20D -#define mmnbif_gpu_RCC_DEV0_EPF4_STRAP2 0x404D202 -#define mmnbif_gpu_RCC_DEV0_EPF4_STRAP3 0x404D203 -#define mmnbif_gpu_RCC_DEV0_EPF4_STRAP4 0x404D204 -#define mmnbif_gpu_RCC_DEV0_EPF4_STRAP5 0x404D205 -#define mmnbif_gpu_RCC_DEV0_EPF4_STRAP6 0x404D206 -#define mmnbif_gpu_RCC_DEV0_EPF5_STRAP0 0x404D280 -#define mmnbif_gpu_RCC_DEV0_EPF5_STRAP13 0x404D28D -#define mmnbif_gpu_RCC_DEV0_EPF5_STRAP2 0x404D282 -#define mmnbif_gpu_RCC_DEV0_EPF5_STRAP3 0x404D283 -#define mmnbif_gpu_RCC_DEV0_EPF5_STRAP4 0x404D284 -#define mmnbif_gpu_RCC_DEV0_EPF5_STRAP5 0x404D285 -#define mmnbif_gpu_RCC_DEV0_EPF5_STRAP6 0x404D286 -#define mmnbif_gpu_RCC_DEV0_EPF6_STRAP0 0x404D300 -#define mmnbif_gpu_RCC_DEV0_EPF6_STRAP13 0x404D30D -#define mmnbif_gpu_RCC_DEV0_EPF6_STRAP2 0x404D302 -#define mmnbif_gpu_RCC_DEV0_EPF6_STRAP3 0x404D303 -#define mmnbif_gpu_RCC_DEV0_EPF6_STRAP4 0x404D304 -#define mmnbif_gpu_RCC_DEV0_EPF6_STRAP5 0x404D305 -#define mmnbif_gpu_RCC_DEV0_EPF6_STRAP6 0x404D306 -#define mmnbif_gpu_RCC_DEV0_EPF7_STRAP0 0x404D380 -#define mmnbif_gpu_RCC_DEV0_EPF7_STRAP13 0x404D38D -#define mmnbif_gpu_RCC_DEV0_EPF7_STRAP2 0x404D382 -#define mmnbif_gpu_RCC_DEV0_EPF7_STRAP3 0x404D383 -#define mmnbif_gpu_RCC_DEV0_EPF7_STRAP4 0x404D384 -#define mmnbif_gpu_RCC_DEV0_EPF7_STRAP5 0x404D385 -#define mmnbif_gpu_RCC_DEV0_EPF7_STRAP6 0x404D386 -#define mmnbif_gpu_RCC_DEV1_EPF0_STRAP0 0x404D400 -#define mmnbif_gpu_RCC_DEV1_EPF0_STRAP13 0x404D40D -#define mmnbif_gpu_RCC_DEV1_EPF0_STRAP2 0x404D402 -#define mmnbif_gpu_RCC_DEV1_EPF0_STRAP3 0x404D403 -#define mmnbif_gpu_RCC_DEV1_EPF0_STRAP4 0x404D404 -#define mmnbif_gpu_RCC_DEV1_EPF0_STRAP5 0x404D405 -#define mmnbif_gpu_RCC_DEV1_EPF0_STRAP6 0x404D406 -#define mmnbif_gpu_RCC_DEV1_EPF1_STRAP0 0x404D480 -#define mmnbif_gpu_RCC_DEV1_EPF1_STRAP13 0x404D48D -#define mmnbif_gpu_RCC_DEV1_EPF1_STRAP2 0x404D482 -#define mmnbif_gpu_RCC_DEV1_EPF1_STRAP3 0x404D483 -#define mmnbif_gpu_RCC_DEV1_EPF1_STRAP4 0x404D484 -#define mmnbif_gpu_RCC_DEV1_EPF1_STRAP5 0x404D485 -#define mmnbif_gpu_RCC_DEV1_EPF1_STRAP6 0x404D486 -#define mmnbif_gpu_RCC_DEV1_EPF2_STRAP0 0x404D500 -#define mmnbif_gpu_RCC_DEV1_EPF2_STRAP13 0x404D50D -#define mmnbif_gpu_RCC_DEV1_EPF2_STRAP2 0x404D502 -#define mmnbif_gpu_RCC_DEV1_EPF2_STRAP3 0x404D503 -#define mmnbif_gpu_RCC_DEV1_EPF2_STRAP4 0x404D504 -#define mmnbif_gpu_RCC_DEV1_EPF2_STRAP5 0x404D505 -#define mmnbif_gpu_RCC_DEV1_EPF2_STRAP6 0x404D506 - - -// Registers from GDC_RST block - -#define mmnbif_gpu_SHUB_PF_FLR_RST 0x507C00 -#define mmnbif_gpu_SHUB_GFX_DRV_MODE1_RST 0x507C01 -#define mmnbif_gpu_SHUB_LINK_RESET 0x507C02 -#define mmnbif_gpu_SHUB_PF0_VF_FLR_RST 0x507C08 -#define mmnbif_gpu_SHUB_HARD_RST_CTRL 0x507C10 -#define mmnbif_gpu_SHUB_SOFT_RST_CTRL 0x507C11 -#define mmnbif_gpu_SHUB_SDP_PORT_RST 0x507C12 - - -// Registers from PCIEMSIX block - -#define mmnbif_gpu_PCIEMSIX_VECT0_ADDR_LO 0x405C000 -#define mmnbif_gpu_PCIEMSIX_VECT1_ADDR_LO 0x405C004 -#define mmnbif_gpu_PCIEMSIX_VECT2_ADDR_LO 0x405C008 -#define mmnbif_gpu_PCIEMSIX_VECT3_ADDR_LO 0x405C00C -#define mmnbif_gpu_PCIEMSIX_VECT4_ADDR_LO 0x405C010 -#define mmnbif_gpu_PCIEMSIX_VECT5_ADDR_LO 0x405C014 -#define mmnbif_gpu_PCIEMSIX_VECT6_ADDR_LO 0x405C018 -#define mmnbif_gpu_PCIEMSIX_VECT7_ADDR_LO 0x405C01C -#define mmnbif_gpu_PCIEMSIX_VECT8_ADDR_LO 0x405C020 -#define mmnbif_gpu_PCIEMSIX_VECT9_ADDR_LO 0x405C024 -#define mmnbif_gpu_PCIEMSIX_VECT10_ADDR_LO 0x405C028 -#define mmnbif_gpu_PCIEMSIX_VECT11_ADDR_LO 0x405C02C -#define mmnbif_gpu_PCIEMSIX_VECT12_ADDR_LO 0x405C030 -#define mmnbif_gpu_PCIEMSIX_VECT13_ADDR_LO 0x405C034 -#define mmnbif_gpu_PCIEMSIX_VECT14_ADDR_LO 0x405C038 -#define mmnbif_gpu_PCIEMSIX_VECT15_ADDR_LO 0x405C03C -#define mmnbif_gpu_PCIEMSIX_VECT16_ADDR_LO 0x405C040 -#define mmnbif_gpu_PCIEMSIX_VECT17_ADDR_LO 0x405C044 -#define mmnbif_gpu_PCIEMSIX_VECT18_ADDR_LO 0x405C048 -#define mmnbif_gpu_PCIEMSIX_VECT19_ADDR_LO 0x405C04C -#define mmnbif_gpu_PCIEMSIX_VECT20_ADDR_LO 0x405C050 -#define mmnbif_gpu_PCIEMSIX_VECT21_ADDR_LO 0x405C054 -#define mmnbif_gpu_PCIEMSIX_VECT22_ADDR_LO 0x405C058 -#define mmnbif_gpu_PCIEMSIX_VECT23_ADDR_LO 0x405C05C -#define mmnbif_gpu_PCIEMSIX_VECT24_ADDR_LO 0x405C060 -#define mmnbif_gpu_PCIEMSIX_VECT25_ADDR_LO 0x405C064 -#define mmnbif_gpu_PCIEMSIX_VECT26_ADDR_LO 0x405C068 -#define mmnbif_gpu_PCIEMSIX_VECT27_ADDR_LO 0x405C06C -#define mmnbif_gpu_PCIEMSIX_VECT28_ADDR_LO 0x405C070 -#define mmnbif_gpu_PCIEMSIX_VECT29_ADDR_LO 0x405C074 -#define mmnbif_gpu_PCIEMSIX_VECT30_ADDR_LO 0x405C078 -#define mmnbif_gpu_PCIEMSIX_VECT31_ADDR_LO 0x405C07C -#define mmnbif_gpu_PCIEMSIX_VECT0_ADDR_HI 0x405C001 -#define mmnbif_gpu_PCIEMSIX_VECT1_ADDR_HI 0x405C005 -#define mmnbif_gpu_PCIEMSIX_VECT2_ADDR_HI 0x405C009 -#define mmnbif_gpu_PCIEMSIX_VECT3_ADDR_HI 0x405C00D -#define mmnbif_gpu_PCIEMSIX_VECT4_ADDR_HI 0x405C011 -#define mmnbif_gpu_PCIEMSIX_VECT5_ADDR_HI 0x405C015 -#define mmnbif_gpu_PCIEMSIX_VECT6_ADDR_HI 0x405C019 -#define mmnbif_gpu_PCIEMSIX_VECT7_ADDR_HI 0x405C01D -#define mmnbif_gpu_PCIEMSIX_VECT8_ADDR_HI 0x405C021 -#define mmnbif_gpu_PCIEMSIX_VECT9_ADDR_HI 0x405C025 -#define mmnbif_gpu_PCIEMSIX_VECT10_ADDR_HI 0x405C029 -#define mmnbif_gpu_PCIEMSIX_VECT11_ADDR_HI 0x405C02D -#define mmnbif_gpu_PCIEMSIX_VECT12_ADDR_HI 0x405C031 -#define mmnbif_gpu_PCIEMSIX_VECT13_ADDR_HI 0x405C035 -#define mmnbif_gpu_PCIEMSIX_VECT14_ADDR_HI 0x405C039 -#define mmnbif_gpu_PCIEMSIX_VECT15_ADDR_HI 0x405C03D -#define mmnbif_gpu_PCIEMSIX_VECT16_ADDR_HI 0x405C041 -#define mmnbif_gpu_PCIEMSIX_VECT17_ADDR_HI 0x405C045 -#define mmnbif_gpu_PCIEMSIX_VECT18_ADDR_HI 0x405C049 -#define mmnbif_gpu_PCIEMSIX_VECT19_ADDR_HI 0x405C04D -#define mmnbif_gpu_PCIEMSIX_VECT20_ADDR_HI 0x405C051 -#define mmnbif_gpu_PCIEMSIX_VECT21_ADDR_HI 0x405C055 -#define mmnbif_gpu_PCIEMSIX_VECT22_ADDR_HI 0x405C059 -#define mmnbif_gpu_PCIEMSIX_VECT23_ADDR_HI 0x405C05D -#define mmnbif_gpu_PCIEMSIX_VECT24_ADDR_HI 0x405C061 -#define mmnbif_gpu_PCIEMSIX_VECT25_ADDR_HI 0x405C065 -#define mmnbif_gpu_PCIEMSIX_VECT26_ADDR_HI 0x405C069 -#define mmnbif_gpu_PCIEMSIX_VECT27_ADDR_HI 0x405C06D -#define mmnbif_gpu_PCIEMSIX_VECT28_ADDR_HI 0x405C071 -#define mmnbif_gpu_PCIEMSIX_VECT29_ADDR_HI 0x405C075 -#define mmnbif_gpu_PCIEMSIX_VECT30_ADDR_HI 0x405C079 -#define mmnbif_gpu_PCIEMSIX_VECT31_ADDR_HI 0x405C07D -#define mmnbif_gpu_PCIEMSIX_VECT0_MSG_DATA 0x405C002 -#define mmnbif_gpu_PCIEMSIX_VECT1_MSG_DATA 0x405C006 -#define mmnbif_gpu_PCIEMSIX_VECT2_MSG_DATA 0x405C00A -#define mmnbif_gpu_PCIEMSIX_VECT3_MSG_DATA 0x405C00E -#define mmnbif_gpu_PCIEMSIX_VECT4_MSG_DATA 0x405C012 -#define mmnbif_gpu_PCIEMSIX_VECT5_MSG_DATA 0x405C016 -#define mmnbif_gpu_PCIEMSIX_VECT6_MSG_DATA 0x405C01A -#define mmnbif_gpu_PCIEMSIX_VECT7_MSG_DATA 0x405C01E -#define mmnbif_gpu_PCIEMSIX_VECT8_MSG_DATA 0x405C022 -#define mmnbif_gpu_PCIEMSIX_VECT9_MSG_DATA 0x405C026 -#define mmnbif_gpu_PCIEMSIX_VECT10_MSG_DATA 0x405C02A -#define mmnbif_gpu_PCIEMSIX_VECT11_MSG_DATA 0x405C02E -#define mmnbif_gpu_PCIEMSIX_VECT12_MSG_DATA 0x405C032 -#define mmnbif_gpu_PCIEMSIX_VECT13_MSG_DATA 0x405C036 -#define mmnbif_gpu_PCIEMSIX_VECT14_MSG_DATA 0x405C03A -#define mmnbif_gpu_PCIEMSIX_VECT15_MSG_DATA 0x405C03E -#define mmnbif_gpu_PCIEMSIX_VECT16_MSG_DATA 0x405C042 -#define mmnbif_gpu_PCIEMSIX_VECT17_MSG_DATA 0x405C046 -#define mmnbif_gpu_PCIEMSIX_VECT18_MSG_DATA 0x405C04A -#define mmnbif_gpu_PCIEMSIX_VECT19_MSG_DATA 0x405C04E -#define mmnbif_gpu_PCIEMSIX_VECT20_MSG_DATA 0x405C052 -#define mmnbif_gpu_PCIEMSIX_VECT21_MSG_DATA 0x405C056 -#define mmnbif_gpu_PCIEMSIX_VECT22_MSG_DATA 0x405C05A -#define mmnbif_gpu_PCIEMSIX_VECT23_MSG_DATA 0x405C05E -#define mmnbif_gpu_PCIEMSIX_VECT24_MSG_DATA 0x405C062 -#define mmnbif_gpu_PCIEMSIX_VECT25_MSG_DATA 0x405C066 -#define mmnbif_gpu_PCIEMSIX_VECT26_MSG_DATA 0x405C06A -#define mmnbif_gpu_PCIEMSIX_VECT27_MSG_DATA 0x405C06E -#define mmnbif_gpu_PCIEMSIX_VECT28_MSG_DATA 0x405C072 -#define mmnbif_gpu_PCIEMSIX_VECT29_MSG_DATA 0x405C076 -#define mmnbif_gpu_PCIEMSIX_VECT30_MSG_DATA 0x405C07A -#define mmnbif_gpu_PCIEMSIX_VECT31_MSG_DATA 0x405C07E -#define mmnbif_gpu_PCIEMSIX_VECT0_CONTROL 0x405C003 -#define mmnbif_gpu_PCIEMSIX_VECT1_CONTROL 0x405C007 -#define mmnbif_gpu_PCIEMSIX_VECT2_CONTROL 0x405C00B -#define mmnbif_gpu_PCIEMSIX_VECT3_CONTROL 0x405C00F -#define mmnbif_gpu_PCIEMSIX_VECT4_CONTROL 0x405C013 -#define mmnbif_gpu_PCIEMSIX_VECT5_CONTROL 0x405C017 -#define mmnbif_gpu_PCIEMSIX_VECT6_CONTROL 0x405C01B -#define mmnbif_gpu_PCIEMSIX_VECT7_CONTROL 0x405C01F -#define mmnbif_gpu_PCIEMSIX_VECT8_CONTROL 0x405C023 -#define mmnbif_gpu_PCIEMSIX_VECT9_CONTROL 0x405C027 -#define mmnbif_gpu_PCIEMSIX_VECT10_CONTROL 0x405C02B -#define mmnbif_gpu_PCIEMSIX_VECT11_CONTROL 0x405C02F -#define mmnbif_gpu_PCIEMSIX_VECT12_CONTROL 0x405C033 -#define mmnbif_gpu_PCIEMSIX_VECT13_CONTROL 0x405C037 -#define mmnbif_gpu_PCIEMSIX_VECT14_CONTROL 0x405C03B -#define mmnbif_gpu_PCIEMSIX_VECT15_CONTROL 0x405C03F -#define mmnbif_gpu_PCIEMSIX_VECT16_CONTROL 0x405C043 -#define mmnbif_gpu_PCIEMSIX_VECT17_CONTROL 0x405C047 -#define mmnbif_gpu_PCIEMSIX_VECT18_CONTROL 0x405C04B -#define mmnbif_gpu_PCIEMSIX_VECT19_CONTROL 0x405C04F -#define mmnbif_gpu_PCIEMSIX_VECT20_CONTROL 0x405C053 -#define mmnbif_gpu_PCIEMSIX_VECT21_CONTROL 0x405C057 -#define mmnbif_gpu_PCIEMSIX_VECT22_CONTROL 0x405C05B -#define mmnbif_gpu_PCIEMSIX_VECT23_CONTROL 0x405C05F -#define mmnbif_gpu_PCIEMSIX_VECT24_CONTROL 0x405C063 -#define mmnbif_gpu_PCIEMSIX_VECT25_CONTROL 0x405C067 -#define mmnbif_gpu_PCIEMSIX_VECT26_CONTROL 0x405C06B -#define mmnbif_gpu_PCIEMSIX_VECT27_CONTROL 0x405C06F -#define mmnbif_gpu_PCIEMSIX_VECT28_CONTROL 0x405C073 -#define mmnbif_gpu_PCIEMSIX_VECT29_CONTROL 0x405C077 -#define mmnbif_gpu_PCIEMSIX_VECT30_CONTROL 0x405C07B -#define mmnbif_gpu_PCIEMSIX_VECT31_CONTROL 0x405C07F -#define mmnbif_gpu_PCIEMSIX_PBA 0x405C400 - - -// Registers from RCC_PFC block - -#define mmnbif_gpu_RCC_PFC_LTR_CNTL 0x404D040 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_LTR_CNTL 0x404D040 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_LTR_CNTL 0x404D0C0 -#define mmnbif_gpu_RCC_PFC_PME_RESTORE 0x404D041 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_PME_RESTORE 0x404D041 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_PME_RESTORE 0x404D0C1 -#define mmnbif_gpu_RCC_PFC_STICKY_RESTORE_0 0x404D042 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_STICKY_RESTORE_0 0x404D042 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_STICKY_RESTORE_0 0x404D0C2 -#define mmnbif_gpu_RCC_PFC_STICKY_RESTORE_1 0x404D043 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_STICKY_RESTORE_1 0x404D043 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_STICKY_RESTORE_1 0x404D0C3 -#define mmnbif_gpu_RCC_PFC_STICKY_RESTORE_2 0x404D044 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_STICKY_RESTORE_2 0x404D044 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_STICKY_RESTORE_2 0x404D0C4 -#define mmnbif_gpu_RCC_PFC_STICKY_RESTORE_3 0x404D045 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_STICKY_RESTORE_3 0x404D045 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_STICKY_RESTORE_3 0x404D0C5 -#define mmnbif_gpu_RCC_PFC_STICKY_RESTORE_4 0x404D046 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_STICKY_RESTORE_4 0x404D046 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_STICKY_RESTORE_4 0x404D0C6 -#define mmnbif_gpu_RCC_PFC_STICKY_RESTORE_5 0x404D047 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_STICKY_RESTORE_5 0x404D047 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_STICKY_RESTORE_5 0x404D0C7 -#define mmnbif_gpu_RCC_PFC_AUXPWR_CNTL 0x404D048 -#define mmRCC_PFC0_nbif_gpu_RCC_PFC_AUXPWR_CNTL 0x404D048 -#define mmRCC_PFC1_nbif_gpu_RCC_PFC_AUXPWR_CNTL 0x404D0C8 - - -// Registers from IH block - -#define mmIH_VMID_0_LUT 0x10A0 -#define mmIH_VMID_1_LUT 0x10A1 -#define mmIH_VMID_2_LUT 0x10A2 -#define mmIH_VMID_3_LUT 0x10A3 -#define mmIH_VMID_4_LUT 0x10A4 -#define mmIH_VMID_5_LUT 0x10A5 -#define mmIH_VMID_6_LUT 0x10A6 -#define mmIH_VMID_7_LUT 0x10A7 -#define mmIH_VMID_8_LUT 0x10A8 -#define mmIH_VMID_9_LUT 0x10A9 -#define mmIH_VMID_10_LUT 0x10AA -#define mmIH_VMID_11_LUT 0x10AB -#define mmIH_VMID_12_LUT 0x10AC -#define mmIH_VMID_13_LUT 0x10AD -#define mmIH_VMID_14_LUT 0x10AE -#define mmIH_VMID_15_LUT 0x10AF -#define mmIH_VMID_0_LUT_MM 0x10B0 -#define mmIH_VMID_1_LUT_MM 0x10B1 -#define mmIH_VMID_2_LUT_MM 0x10B2 -#define mmIH_VMID_3_LUT_MM 0x10B3 -#define mmIH_VMID_4_LUT_MM 0x10B4 -#define mmIH_VMID_5_LUT_MM 0x10B5 -#define mmIH_VMID_6_LUT_MM 0x10B6 -#define mmIH_VMID_7_LUT_MM 0x10B7 -#define mmIH_VMID_8_LUT_MM 0x10B8 -#define mmIH_VMID_9_LUT_MM 0x10B9 -#define mmIH_VMID_10_LUT_MM 0x10BA -#define mmIH_VMID_11_LUT_MM 0x10BB -#define mmIH_VMID_12_LUT_MM 0x10BC -#define mmIH_VMID_13_LUT_MM 0x10BD -#define mmIH_VMID_14_LUT_MM 0x10BE -#define mmIH_VMID_15_LUT_MM 0x10BF -#define mmIH_COOKIE_0 0x10C0 -#define mmIH_COOKIE_1 0x10C1 -#define mmIH_COOKIE_2 0x10C2 -#define mmIH_COOKIE_3 0x10C3 -#define mmIH_COOKIE_4 0x10C4 -#define mmIH_COOKIE_5 0x10C5 -#define mmIH_COOKIE_6 0x10C6 -#define mmIH_COOKIE_7 0x10C7 -#define mmIH_REGISTER_LAST_PART0 0x10DF -#define mmIH_RB_CNTL 0x1120 -#define mmIH_RB_BASE 0x1121 -#define mmIH_RB_BASE_HI 0x1122 -#define mmIH_RB_RPTR 0x1123 -#define mmIH_RB_WPTR 0x1124 -#define mmIH_RB_WPTR_ADDR_HI 0x1125 -#define mmIH_RB_WPTR_ADDR_LO 0x1126 -#define mmIH_DOORBELL_RPTR 0x1127 -#define mmIH_RB_CNTL_RING1 0x1128 -#define mmIH_RB_BASE_RING1 0x1129 -#define mmIH_RB_BASE_HI_RING1 0x112A -#define mmIH_RB_RPTR_RING1 0x112B -#define mmIH_RB_WPTR_RING1 0x112C -#define mmIH_DOORBELL_RPTR_RING1 0x112F -#define mmIH_RB_CNTL_RING2 0x1130 -#define mmIH_RB_BASE_RING2 0x1131 -#define mmIH_RB_BASE_HI_RING2 0x1132 -#define mmIH_RB_RPTR_RING2 0x1133 -#define mmIH_RB_WPTR_RING2 0x1134 -#define mmIH_DOORBELL_RPTR_RING2 0x1137 -#define mmIH_VERSION 0x1138 -#define mmIH_CNTL 0x1160 -#define mmIH_CNTL2 0x1161 -#define mmIH_STATUS 0x1162 -#define mmIH_PERFMON_CNTL 0x1163 -#define mmIH_PERFCOUNTER0_RESULT 0x1164 -#define mmIH_PERFCOUNTER1_RESULT 0x1165 -#define mmIH_DEBUG 0x1166 -#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x1167 -#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x1168 -#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x1169 -#define mmIH_DSM_MATCH_FIELD_CONTROL 0x116A -#define mmIH_DSM_MATCH_DATA_CONTROL 0x116B -#define mmIH_DSM_MATCH_FCN_ID 0x116C -#define mmIH_LIMIT_INT_RATE_CNTL 0x116D -#define mmIH_VF_RB_STATUS 0x116E -#define mmIH_VF_RB_STATUS2 0x116F -#define mmIH_VF_RB1_STATUS 0x1170 -#define mmIH_VF_RB1_STATUS2 0x1171 -#define mmIH_VF_RB2_STATUS 0x1172 -#define mmIH_VF_RB2_STATUS2 0x1173 -#define mmIH_INT_FLOOD_CNTL 0x1175 -#define mmIH_RB0_INT_FLOOD_STATUS 0x1176 -#define mmIH_RB1_INT_FLOOD_STATUS 0x1177 -#define mmIH_RB2_INT_FLOOD_STATUS 0x1178 -#define mmIH_INT_FLOOD_STATUS 0x1179 -#define mmIH_STORM_CLIENT_LIST_CNTL 0x117A -#define mmIH_CLK_CTRL 0x117B -#define mmIH_INT_FLAGS 0x117C -#define mmIH_LAST_INT_INFO0 0x117D -#define mmIH_LAST_INT_INFO1 0x117E -#define mmIH_LAST_INT_INFO2 0x117F -#define mmIH_SCRATCH 0x1180 -#define mmIH_CLIENT_CREDIT_ERROR 0x1181 -#define mmIH_GPU_IOV_VIOLATION_LOG 0x1182 -#define mmIH_COOKIE_REC_VIOLATION_LOG 0x1183 -#define mmIH_CREDIT_STATUS 0x1184 -#define mmIH_MMHUB_ERROR 0x1185 -#define mmIH_DEBUG_INDEX 0x1186 -#define mmIH_DEBUG_DATA 0x1187 -#define mmIH_REGISTER_LAST_PART2 0x119F -#define mmIH_ACTIVE_FCN_ID 0x1220 -#define mmIH_VIRT_RESET_REQ 0x1221 -#define mmIH_CLIENT_CFG 0x1224 -#define mmIH_CLIENT_CFG_INDEX 0x1228 -#define mmIH_CLIENT_CFG_DATA 0x1229 -#define mmIH_CID_REMAP_INDEX 0x122A -#define mmIH_CID_REMAP_DATA 0x122B -#define mmIH_CHICKEN 0x122C -#define mmIH_MMHUB_TLVL 0x122D -#define mmIH_REGISTER_LAST_PART1 0x123F - - -// Registers from SEM block - -#define mmSEM_REQ_INPUT_0 0x10E0 -#define mmSEM_REQ_INPUT_1 0x10E1 -#define mmSEM_REQ_INPUT_2 0x10E2 -#define mmSEM_REQ_INPUT_3 0x10E3 -#define mmSEM_REGISTER_LAST_PART0 0x111F -#define mmSEM_CLK_CTRL 0x11A0 -#define mmSEM_UTC_CREDIT 0x11A1 -#define mmSEM_UTC_CONFIG 0x11A2 -#define mmSEM_UTCL2_TRAN_EN_LUT 0x11A3 -#define mmSEM_MCIF_CONFIG 0x11A4 -#define mmSEM_PERFMON_CNTL 0x11A5 -#define mmSEM_PERFCOUNTER0_RESULT 0x11A6 -#define mmSEM_PERFCOUNTER1_RESULT 0x11A7 -#define mmSEM_STATUS 0x11A8 -#define mmSEM_MAILBOX_CLIENTCONFIG 0x11A9 -#define mmSEM_MAILBOX 0x11AA -#define mmSEM_MAILBOX_CONTROL 0x11AB -#define mmSEM_CHICKEN_BITS 0x11AC -#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x11AD -#define mmSEM_GPU_IOV_VIOLATION_LOG 0x11AE -#define mmSEM_OUTSTANDING_THRESHOLD 0x11AF -#define mmSEM_REGISTER_LAST_PART2 0x121F -#define mmSEM_ACTIVE_FCN_ID 0x1240 -#define mmSEM_VIRT_RESET_REQ 0x1241 -#define mmSEM_RESP_SDMA0 0x1244 -#define mmSEM_RESP_SDMA1 0x1245 -#define mmSEM_RESP_UVD 0x1246 -#define mmSEM_RESP_VCE_0 0x1247 -#define mmSEM_RESP_ACP 0x1248 -#define mmSEM_RESP_ISP 0x1249 -#define mmSEM_RESP_VCE_1 0x124A -#define mmSEM_RESP_VP8 0x124B -#define mmSEM_RESP_GC 0x124C -#define mmSEM_CID_REMAP_INDEX 0x1250 -#define mmSEM_CID_REMAP_DATA 0x1251 -#define mmSEM_ATOMIC_OP_LUT 0x1252 -#define mmSEM_EDC_CONFIG 0x1253 -#define mmSEM_CHICKEN_BITS2 0x1254 -#define mmSEM_MMHUB_TLVL 0x1255 -#define mmSEM_REGISTER_LAST_PART1 0x125F - - -// Registers from SDMA block - -#define mmSDMA0_UCODE_ADDR 0x1260 -#define mmSDMA0_UCODE_DATA 0x1261 -#define mmSDMA0_REGISTER_SECURITY_CNTL 0x1262 -#define mmSDMA0_VM_CNTL 0x1264 -#define mmSDMA0_VM_CTX_LO 0x1265 -#define mmSDMA0_VM_CTX_HI 0x1266 -#define mmSDMA0_ACTIVE_FCN_ID 0x1267 -#define mmSDMA0_VM_CTX_CNTL 0x1268 -#define mmSDMA0_VIRT_RESET_REQ 0x1269 -#define mmSDMA0_CONTEXT_REG_TYPE0 0x126B -#define mmSDMA0_CONTEXT_REG_TYPE1 0x126C -#define mmSDMA0_CONTEXT_REG_TYPE2 0x126D -#define mmSDMA0_CONTEXT_REG_TYPE3 0x126E -#define mmSDMA0_PUB_REG_TYPE0 0x126F -#define mmSDMA0_PUB_REG_TYPE1 0x1270 -#define mmSDMA0_PUB_REG_TYPE2 0x1271 -#define mmSDMA0_PUB_REG_TYPE3 0x1272 -#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x1279 -#define mmSDMA0_POWER_CNTL 0x127A -#define mmSDMA0_CLK_CTRL 0x127B -#define mmSDMA0_CNTL 0x127C -#define mmSDMA0_CHICKEN_BITS 0x127D -#define mmSDMA0_GB_ADDR_CONFIG 0x127E -#define mmSDMA0_GB_ADDR_CONFIG_READ 0x127F -#define mmSDMA0_RB_RPTR_FETCH_HI 0x1280 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x1281 -#define mmSDMA0_RB_RPTR_FETCH 0x1282 -#define mmSDMA0_IB_OFFSET_FETCH 0x1283 -#define mmSDMA0_PROGRAM 0x1284 -#define mmSDMA0_STATUS_REG 0x1285 -#define mmSDMA0_STATUS1_REG 0x1286 -#define mmSDMA0_RD_BURST_CNTL 0x1287 -#define mmSDMA0_HBM_PAGE_CONFIG 0x1288 -#define mmSDMA0_UCODE_CHECKSUM 0x1289 -#define mmSDMA0_F32_CNTL 0x128A -#define mmSDMA0_FREEZE 0x128B -#define mmSDMA0_PHASE0_QUANTUM 0x128C -#define mmSDMA0_PHASE1_QUANTUM 0x128D -#define mmSDMA_POWER_GATING 0x128E -#define mmSDMA_PGFSM_CONFIG 0x128F -#define mmSDMA_PGFSM_WRITE 0x1290 -#define mmSDMA_PGFSM_READ 0x1291 -#define mmSDMA0_EDC_CONFIG 0x1292 -#define mmSDMA0_BA_THRESHOLD 0x1293 -#define mmSDMA0_ID 0x1294 -#define mmSDMA0_VERSION 0x1295 -#define mmSDMA0_EDC_COUNTER 0x1296 -#define mmSDMA0_EDC_COUNTER_CLEAR 0x1297 -#define mmSDMA0_STATUS2_REG 0x1298 -#define mmSDMA0_ATOMIC_CNTL 0x1299 -#define mmSDMA0_ATOMIC_PREOP_LO 0x129A -#define mmSDMA0_ATOMIC_PREOP_HI 0x129B -#define mmSDMA0_UTCL1_CNTL 0x129C -#define mmSDMA0_UTCL1_WATERMK 0x129D -#define mmSDMA0_UTCL1_RD_STATUS 0x129E -#define mmSDMA0_UTCL1_WR_STATUS 0x129F -#define mmSDMA0_UTCL1_INV0 0x12A0 -#define mmSDMA0_UTCL1_INV1 0x12A1 -#define mmSDMA0_UTCL1_INV2 0x12A2 -#define mmSDMA0_UTCL1_RD_XNACK0 0x12A3 -#define mmSDMA0_UTCL1_RD_XNACK1 0x12A4 -#define mmSDMA0_UTCL1_WR_XNACK0 0x12A5 -#define mmSDMA0_UTCL1_WR_XNACK1 0x12A6 -#define mmSDMA0_UTCL1_TIMEOUT 0x12A7 -#define mmSDMA0_UTCL1_PAGE 0x12A8 -#define mmSDMA0_POWER_CNTL_IDLE 0x12A9 -#define mmSDMA0_RELAX_ORDERING_LUT 0x12AA -#define mmSDMA0_CHICKEN_BITS_2 0x12AB -#define mmSDMA0_STATUS3_REG 0x12AC -#define mmSDMA0_PHYSICAL_ADDR_LO 0x12AD -#define mmSDMA0_PHYSICAL_ADDR_HI 0x12AE -#define mmSDMA0_PHASE2_QUANTUM 0x12AF -#define mmSDMA0_ERROR_LOG 0x12B0 -#define mmSDMA0_PUB_DUMMY_REG0 0x12B1 -#define mmSDMA0_PUB_DUMMY_REG1 0x12B2 -#define mmSDMA0_PUB_DUMMY_REG2 0x12B3 -#define mmSDMA0_PUB_DUMMY_REG3 0x12B4 -#define mmSDMA0_F32_COUNTER 0x12B5 -#define mmSDMA0_UNBREAKABLE 0x12B6 -#define mmSDMA0_PERFMON_CNTL 0x12B7 -#define mmSDMA0_PERFCOUNTER0_RESULT 0x12B8 -#define mmSDMA0_PERFCOUNTER1_RESULT 0x12B9 -#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x12BA -#define mmSDMA0_CRD_CNTL 0x12BB -#define mmSDMA0_MMHUB_TRUSTLVL 0x12BC -#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x12BD -#define mmSDMA0_ULV_CNTL 0x12BE -#define mmSDMA0_EA_DBIT_ADDR_DATA 0x12C0 -#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x12C1 -#define mmSDMA0_GFX_RB_CNTL 0x12E0 -#define mmSDMA0_GFX_RB_BASE 0x12E1 -#define mmSDMA0_GFX_RB_BASE_HI 0x12E2 -#define mmSDMA0_GFX_RB_RPTR 0x12E3 -#define mmSDMA0_GFX_RB_RPTR_HI 0x12E4 -#define mmSDMA0_GFX_RB_WPTR 0x12E5 -#define mmSDMA0_GFX_RB_WPTR_HI 0x12E6 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x12E7 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x12E8 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x12E9 -#define mmSDMA0_GFX_IB_CNTL 0x12EA -#define mmSDMA0_GFX_IB_RPTR 0x12EB -#define mmSDMA0_GFX_IB_OFFSET 0x12EC -#define mmSDMA0_GFX_IB_BASE_LO 0x12ED -#define mmSDMA0_GFX_IB_BASE_HI 0x12EE -#define mmSDMA0_GFX_IB_SIZE 0x12EF -#define mmSDMA0_GFX_SKIP_CNTL 0x12F0 -#define mmSDMA0_GFX_CONTEXT_STATUS 0x12F1 -#define mmSDMA0_GFX_DOORBELL 0x12F2 -#define mmSDMA0_GFX_CONTEXT_CNTL 0x12F3 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY0 0x12F4 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY1 0x12F5 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY2 0x12F6 -#define mmSDMA0_GFX_DRM_WRAPPEDKEY3 0x12F7 -#define mmSDMA0_GFX_DRM_COUNTERKEY0 0x12F8 -#define mmSDMA0_GFX_DRM_COUNTERKEY1 0x12F9 -#define mmSDMA0_GFX_DRM_COUNTERKEY2 0x12FA -#define mmSDMA0_GFX_DRM_COUNTERKEY3 0x12FB -#define mmSDMA0_GFX_DRM_COUNTERDATA0 0x12FC -#define mmSDMA0_GFX_DRM_COUNTERDATA1 0x12FD -#define mmSDMA0_GFX_DRM_COUNTERDATA2 0x12FE -#define mmSDMA0_GFX_DRM_COUNTERDATA3 0x12FF -#define mmSDMA0_GFX_DRM_OFFSET 0x1300 -#define mmSDMA0_GFX_DRM_IVLOAD0 0x1301 -#define mmSDMA0_GFX_DRM_IVLOAD1 0x1302 -#define mmSDMA0_GFX_DRM_IVLOAD2 0x1303 -#define mmSDMA0_GFX_DRM_IVLOAD3 0x1304 -#define mmSDMA0_GFX_DRM_IVLOAD4 0x1305 -#define mmSDMA0_GFX_DRM_UNROLLKEY 0x1306 -#define mmSDMA0_GFX_AES 0x1307 -#define mmSDMA0_GFX_STATUS 0x1308 -#define mmSDMA0_GFX_DOORBELL_LOG 0x1309 -#define mmSDMA0_GFX_WATERMARK 0x130A -#define mmSDMA0_GFX_DOORBELL_OFFSET 0x130B -#define mmSDMA0_GFX_CSA_ADDR_LO 0x130C -#define mmSDMA0_GFX_CSA_ADDR_HI 0x130D -#define mmSDMA0_GFX_IB_SUB_REMAIN 0x130F -#define mmSDMA0_GFX_PREEMPT 0x1310 -#define mmSDMA0_GFX_DUMMY_REG 0x1311 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x1312 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x1313 -#define mmSDMA0_GFX_RB_AQL_CNTL 0x1314 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x1315 -#define mmSDMA0_GFX_MIDCMD_DATA0 0x1320 -#define mmSDMA0_GFX_MIDCMD_DATA1 0x1321 -#define mmSDMA0_GFX_MIDCMD_DATA2 0x1322 -#define mmSDMA0_GFX_MIDCMD_DATA3 0x1323 -#define mmSDMA0_GFX_MIDCMD_DATA4 0x1324 -#define mmSDMA0_GFX_MIDCMD_DATA5 0x1325 -#define mmSDMA0_GFX_MIDCMD_DATA6 0x1326 -#define mmSDMA0_GFX_MIDCMD_DATA7 0x1327 -#define mmSDMA0_GFX_MIDCMD_DATA8 0x1328 -#define mmSDMA0_GFX_MIDCMD_CNTL 0x1329 -#define mmSDMA0_PAGE_RB_CNTL 0x1340 -#define mmSDMA0_PAGE_RB_BASE 0x1341 -#define mmSDMA0_PAGE_RB_BASE_HI 0x1342 -#define mmSDMA0_PAGE_RB_RPTR 0x1343 -#define mmSDMA0_PAGE_RB_RPTR_HI 0x1344 -#define mmSDMA0_PAGE_RB_WPTR 0x1345 -#define mmSDMA0_PAGE_RB_WPTR_HI 0x1346 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x1347 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x1348 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x1349 -#define mmSDMA0_PAGE_IB_CNTL 0x134A -#define mmSDMA0_PAGE_IB_RPTR 0x134B -#define mmSDMA0_PAGE_IB_OFFSET 0x134C -#define mmSDMA0_PAGE_IB_BASE_LO 0x134D -#define mmSDMA0_PAGE_IB_BASE_HI 0x134E -#define mmSDMA0_PAGE_IB_SIZE 0x134F -#define mmSDMA0_PAGE_SKIP_CNTL 0x1350 -#define mmSDMA0_PAGE_CONTEXT_STATUS 0x1351 -#define mmSDMA0_PAGE_DOORBELL 0x1352 -#define mmSDMA0_PAGE_STATUS 0x1368 -#define mmSDMA0_PAGE_DOORBELL_LOG 0x1369 -#define mmSDMA0_PAGE_WATERMARK 0x136A -#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x136B -#define mmSDMA0_PAGE_CSA_ADDR_LO 0x136C -#define mmSDMA0_PAGE_CSA_ADDR_HI 0x136D -#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x136F -#define mmSDMA0_PAGE_PREEMPT 0x1370 -#define mmSDMA0_PAGE_DUMMY_REG 0x1371 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x1372 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x1373 -#define mmSDMA0_PAGE_RB_AQL_CNTL 0x1374 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x1375 -#define mmSDMA0_PAGE_MIDCMD_DATA0 0x1380 -#define mmSDMA0_PAGE_MIDCMD_DATA1 0x1381 -#define mmSDMA0_PAGE_MIDCMD_DATA2 0x1382 -#define mmSDMA0_PAGE_MIDCMD_DATA3 0x1383 -#define mmSDMA0_PAGE_MIDCMD_DATA4 0x1384 -#define mmSDMA0_PAGE_MIDCMD_DATA5 0x1385 -#define mmSDMA0_PAGE_MIDCMD_DATA6 0x1386 -#define mmSDMA0_PAGE_MIDCMD_DATA7 0x1387 -#define mmSDMA0_PAGE_MIDCMD_DATA8 0x1388 -#define mmSDMA0_PAGE_MIDCMD_CNTL 0x1389 -#define mmSDMA0_RLC0_RB_CNTL 0x13A0 -#define mmSDMA0_RLC0_RB_BASE 0x13A1 -#define mmSDMA0_RLC0_RB_BASE_HI 0x13A2 -#define mmSDMA0_RLC0_RB_RPTR 0x13A3 -#define mmSDMA0_RLC0_RB_RPTR_HI 0x13A4 -#define mmSDMA0_RLC0_RB_WPTR 0x13A5 -#define mmSDMA0_RLC0_RB_WPTR_HI 0x13A6 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x13A7 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x13A8 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x13A9 -#define mmSDMA0_RLC0_IB_CNTL 0x13AA -#define mmSDMA0_RLC0_IB_RPTR 0x13AB -#define mmSDMA0_RLC0_IB_OFFSET 0x13AC -#define mmSDMA0_RLC0_IB_BASE_LO 0x13AD -#define mmSDMA0_RLC0_IB_BASE_HI 0x13AE -#define mmSDMA0_RLC0_IB_SIZE 0x13AF -#define mmSDMA0_RLC0_SKIP_CNTL 0x13B0 -#define mmSDMA0_RLC0_CONTEXT_STATUS 0x13B1 -#define mmSDMA0_RLC0_DOORBELL 0x13B2 -#define mmSDMA0_RLC0_STATUS 0x13C8 -#define mmSDMA0_RLC0_DOORBELL_LOG 0x13C9 -#define mmSDMA0_RLC0_WATERMARK 0x13CA -#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x13CB -#define mmSDMA0_RLC0_CSA_ADDR_LO 0x13CC -#define mmSDMA0_RLC0_CSA_ADDR_HI 0x13CD -#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x13CF -#define mmSDMA0_RLC0_PREEMPT 0x13D0 -#define mmSDMA0_RLC0_DUMMY_REG 0x13D1 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x13D2 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x13D3 -#define mmSDMA0_RLC0_RB_AQL_CNTL 0x13D4 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x13D5 -#define mmSDMA0_RLC0_MIDCMD_DATA0 0x13E0 -#define mmSDMA0_RLC0_MIDCMD_DATA1 0x13E1 -#define mmSDMA0_RLC0_MIDCMD_DATA2 0x13E2 -#define mmSDMA0_RLC0_MIDCMD_DATA3 0x13E3 -#define mmSDMA0_RLC0_MIDCMD_DATA4 0x13E4 -#define mmSDMA0_RLC0_MIDCMD_DATA5 0x13E5 -#define mmSDMA0_RLC0_MIDCMD_DATA6 0x13E6 -#define mmSDMA0_RLC0_MIDCMD_DATA7 0x13E7 -#define mmSDMA0_RLC0_MIDCMD_DATA8 0x13E8 -#define mmSDMA0_RLC0_MIDCMD_CNTL 0x13E9 -#define mmSDMA0_RLC1_RB_CNTL 0x1400 -#define mmSDMA0_RLC1_RB_BASE 0x1401 -#define mmSDMA0_RLC1_RB_BASE_HI 0x1402 -#define mmSDMA0_RLC1_RB_RPTR 0x1403 -#define mmSDMA0_RLC1_RB_RPTR_HI 0x1404 -#define mmSDMA0_RLC1_RB_WPTR 0x1405 -#define mmSDMA0_RLC1_RB_WPTR_HI 0x1406 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x1407 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x1408 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x1409 -#define mmSDMA0_RLC1_IB_CNTL 0x140A -#define mmSDMA0_RLC1_IB_RPTR 0x140B -#define mmSDMA0_RLC1_IB_OFFSET 0x140C -#define mmSDMA0_RLC1_IB_BASE_LO 0x140D -#define mmSDMA0_RLC1_IB_BASE_HI 0x140E -#define mmSDMA0_RLC1_IB_SIZE 0x140F -#define mmSDMA0_RLC1_SKIP_CNTL 0x1410 -#define mmSDMA0_RLC1_CONTEXT_STATUS 0x1411 -#define mmSDMA0_RLC1_DOORBELL 0x1412 -#define mmSDMA0_RLC1_STATUS 0x1428 -#define mmSDMA0_RLC1_DOORBELL_LOG 0x1429 -#define mmSDMA0_RLC1_WATERMARK 0x142A -#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x142B -#define mmSDMA0_RLC1_CSA_ADDR_LO 0x142C -#define mmSDMA0_RLC1_CSA_ADDR_HI 0x142D -#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x142F -#define mmSDMA0_RLC1_PREEMPT 0x1430 -#define mmSDMA0_RLC1_DUMMY_REG 0x1431 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x1432 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x1433 -#define mmSDMA0_RLC1_RB_AQL_CNTL 0x1434 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x1435 -#define mmSDMA0_RLC1_MIDCMD_DATA0 0x1440 -#define mmSDMA0_RLC1_MIDCMD_DATA1 0x1441 -#define mmSDMA0_RLC1_MIDCMD_DATA2 0x1442 -#define mmSDMA0_RLC1_MIDCMD_DATA3 0x1443 -#define mmSDMA0_RLC1_MIDCMD_DATA4 0x1444 -#define mmSDMA0_RLC1_MIDCMD_DATA5 0x1445 -#define mmSDMA0_RLC1_MIDCMD_DATA6 0x1446 -#define mmSDMA0_RLC1_MIDCMD_DATA7 0x1447 -#define mmSDMA0_RLC1_MIDCMD_DATA8 0x1448 -#define mmSDMA0_RLC1_MIDCMD_CNTL 0x1449 - - -// Registers from SDMA1 block - -#define mmSDMA1_UCODE_ADDR 0x1460 -#define mmSDMA1_UCODE_DATA 0x1461 -#define mmSDMA1_REGISTER_SECURITY_CNTL 0x1462 -#define mmSDMA1_VM_CNTL 0x1464 -#define mmSDMA1_VM_CTX_LO 0x1465 -#define mmSDMA1_VM_CTX_HI 0x1466 -#define mmSDMA1_ACTIVE_FCN_ID 0x1467 -#define mmSDMA1_VM_CTX_CNTL 0x1468 -#define mmSDMA1_VIRT_RESET_REQ 0x1469 -#define mmSDMA1_CONTEXT_REG_TYPE0 0x146B -#define mmSDMA1_CONTEXT_REG_TYPE1 0x146C -#define mmSDMA1_CONTEXT_REG_TYPE2 0x146D -#define mmSDMA1_CONTEXT_REG_TYPE3 0x146E -#define mmSDMA1_PUB_REG_TYPE0 0x146F -#define mmSDMA1_PUB_REG_TYPE1 0x1470 -#define mmSDMA1_PUB_REG_TYPE2 0x1471 -#define mmSDMA1_PUB_REG_TYPE3 0x1472 -#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x1479 -#define mmSDMA1_POWER_CNTL 0x147A -#define mmSDMA1_CLK_CTRL 0x147B -#define mmSDMA1_CNTL 0x147C -#define mmSDMA1_CHICKEN_BITS 0x147D -#define mmSDMA1_GB_ADDR_CONFIG 0x147E -#define mmSDMA1_GB_ADDR_CONFIG_READ 0x147F -#define mmSDMA1_RB_RPTR_FETCH_HI 0x1480 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x1481 -#define mmSDMA1_RB_RPTR_FETCH 0x1482 -#define mmSDMA1_IB_OFFSET_FETCH 0x1483 -#define mmSDMA1_PROGRAM 0x1484 -#define mmSDMA1_STATUS_REG 0x1485 -#define mmSDMA1_STATUS1_REG 0x1486 -#define mmSDMA1_RD_BURST_CNTL 0x1487 -#define mmSDMA1_HBM_PAGE_CONFIG 0x1488 -#define mmSDMA1_UCODE_CHECKSUM 0x1489 -#define mmSDMA1_F32_CNTL 0x148A -#define mmSDMA1_FREEZE 0x148B -#define mmSDMA1_PHASE0_QUANTUM 0x148C -#define mmSDMA1_PHASE1_QUANTUM 0x148D -#define mmSDMA1_EDC_CONFIG 0x1492 -#define mmSDMA1_BA_THRESHOLD 0x1493 -#define mmSDMA1_ID 0x1494 -#define mmSDMA1_VERSION 0x1495 -#define mmSDMA1_EDC_COUNTER 0x1496 -#define mmSDMA1_EDC_COUNTER_CLEAR 0x1497 -#define mmSDMA1_STATUS2_REG 0x1498 -#define mmSDMA1_ATOMIC_CNTL 0x1499 -#define mmSDMA1_ATOMIC_PREOP_LO 0x149A -#define mmSDMA1_ATOMIC_PREOP_HI 0x149B -#define mmSDMA1_UTCL1_CNTL 0x149C -#define mmSDMA1_UTCL1_WATERMK 0x149D -#define mmSDMA1_UTCL1_RD_STATUS 0x149E -#define mmSDMA1_UTCL1_WR_STATUS 0x149F -#define mmSDMA1_UTCL1_INV0 0x14A0 -#define mmSDMA1_UTCL1_INV1 0x14A1 -#define mmSDMA1_UTCL1_INV2 0x14A2 -#define mmSDMA1_UTCL1_RD_XNACK0 0x14A3 -#define mmSDMA1_UTCL1_RD_XNACK1 0x14A4 -#define mmSDMA1_UTCL1_WR_XNACK0 0x14A5 -#define mmSDMA1_UTCL1_WR_XNACK1 0x14A6 -#define mmSDMA1_UTCL1_TIMEOUT 0x14A7 -#define mmSDMA1_UTCL1_PAGE 0x14A8 -#define mmSDMA1_POWER_CNTL_IDLE 0x14A9 -#define mmSDMA1_RELAX_ORDERING_LUT 0x14AA -#define mmSDMA1_CHICKEN_BITS_2 0x14AB -#define mmSDMA1_STATUS3_REG 0x14AC -#define mmSDMA1_PHYSICAL_ADDR_LO 0x14AD -#define mmSDMA1_PHYSICAL_ADDR_HI 0x14AE -#define mmSDMA1_PHASE2_QUANTUM 0x14AF -#define mmSDMA1_ERROR_LOG 0x14B0 -#define mmSDMA1_PUB_DUMMY_REG0 0x14B1 -#define mmSDMA1_PUB_DUMMY_REG1 0x14B2 -#define mmSDMA1_PUB_DUMMY_REG2 0x14B3 -#define mmSDMA1_PUB_DUMMY_REG3 0x14B4 -#define mmSDMA1_F32_COUNTER 0x14B5 -#define mmSDMA1_UNBREAKABLE 0x14B6 -#define mmSDMA1_PERFMON_CNTL 0x14B7 -#define mmSDMA1_PERFCOUNTER0_RESULT 0x14B8 -#define mmSDMA1_PERFCOUNTER1_RESULT 0x14B9 -#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x14BA -#define mmSDMA1_CRD_CNTL 0x14BB -#define mmSDMA1_MMHUB_TRUSTLVL 0x14BC -#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x14BD -#define mmSDMA1_ULV_CNTL 0x14BE -#define mmSDMA1_EA_DBIT_ADDR_DATA 0x14C0 -#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x14C1 -#define mmSDMA1_GFX_RB_CNTL 0x14E0 -#define mmSDMA1_GFX_RB_BASE 0x14E1 -#define mmSDMA1_GFX_RB_BASE_HI 0x14E2 -#define mmSDMA1_GFX_RB_RPTR 0x14E3 -#define mmSDMA1_GFX_RB_RPTR_HI 0x14E4 -#define mmSDMA1_GFX_RB_WPTR 0x14E5 -#define mmSDMA1_GFX_RB_WPTR_HI 0x14E6 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x14E7 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x14E8 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x14E9 -#define mmSDMA1_GFX_IB_CNTL 0x14EA -#define mmSDMA1_GFX_IB_RPTR 0x14EB -#define mmSDMA1_GFX_IB_OFFSET 0x14EC -#define mmSDMA1_GFX_IB_BASE_LO 0x14ED -#define mmSDMA1_GFX_IB_BASE_HI 0x14EE -#define mmSDMA1_GFX_IB_SIZE 0x14EF -#define mmSDMA1_GFX_SKIP_CNTL 0x14F0 -#define mmSDMA1_GFX_CONTEXT_STATUS 0x14F1 -#define mmSDMA1_GFX_DOORBELL 0x14F2 -#define mmSDMA1_GFX_CONTEXT_CNTL 0x14F3 -#define mmSDMA1_GFX_AES 0x1507 -#define mmSDMA1_GFX_STATUS 0x1508 -#define mmSDMA1_GFX_DOORBELL_LOG 0x1509 -#define mmSDMA1_GFX_WATERMARK 0x150A -#define mmSDMA1_GFX_DOORBELL_OFFSET 0x150B -#define mmSDMA1_GFX_CSA_ADDR_LO 0x150C -#define mmSDMA1_GFX_CSA_ADDR_HI 0x150D -#define mmSDMA1_GFX_IB_SUB_REMAIN 0x150F -#define mmSDMA1_GFX_PREEMPT 0x1510 -#define mmSDMA1_GFX_DUMMY_REG 0x1511 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x1512 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x1513 -#define mmSDMA1_GFX_RB_AQL_CNTL 0x1514 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x1515 -#define mmSDMA1_GFX_MIDCMD_DATA0 0x1520 -#define mmSDMA1_GFX_MIDCMD_DATA1 0x1521 -#define mmSDMA1_GFX_MIDCMD_DATA2 0x1522 -#define mmSDMA1_GFX_MIDCMD_DATA3 0x1523 -#define mmSDMA1_GFX_MIDCMD_DATA4 0x1524 -#define mmSDMA1_GFX_MIDCMD_DATA5 0x1525 -#define mmSDMA1_GFX_MIDCMD_DATA6 0x1526 -#define mmSDMA1_GFX_MIDCMD_DATA7 0x1527 -#define mmSDMA1_GFX_MIDCMD_DATA8 0x1528 -#define mmSDMA1_GFX_MIDCMD_CNTL 0x1529 -#define mmSDMA1_PAGE_RB_CNTL 0x1540 -#define mmSDMA1_PAGE_RB_BASE 0x1541 -#define mmSDMA1_PAGE_RB_BASE_HI 0x1542 -#define mmSDMA1_PAGE_RB_RPTR 0x1543 -#define mmSDMA1_PAGE_RB_RPTR_HI 0x1544 -#define mmSDMA1_PAGE_RB_WPTR 0x1545 -#define mmSDMA1_PAGE_RB_WPTR_HI 0x1546 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x1547 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x1548 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x1549 -#define mmSDMA1_PAGE_IB_CNTL 0x154A -#define mmSDMA1_PAGE_IB_RPTR 0x154B -#define mmSDMA1_PAGE_IB_OFFSET 0x154C -#define mmSDMA1_PAGE_IB_BASE_LO 0x154D -#define mmSDMA1_PAGE_IB_BASE_HI 0x154E -#define mmSDMA1_PAGE_IB_SIZE 0x154F -#define mmSDMA1_PAGE_SKIP_CNTL 0x1550 -#define mmSDMA1_PAGE_CONTEXT_STATUS 0x1551 -#define mmSDMA1_PAGE_DOORBELL 0x1552 -#define mmSDMA1_PAGE_STATUS 0x1568 -#define mmSDMA1_PAGE_DOORBELL_LOG 0x1569 -#define mmSDMA1_PAGE_WATERMARK 0x156A -#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x156B -#define mmSDMA1_PAGE_CSA_ADDR_LO 0x156C -#define mmSDMA1_PAGE_CSA_ADDR_HI 0x156D -#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x156F -#define mmSDMA1_PAGE_PREEMPT 0x1570 -#define mmSDMA1_PAGE_DUMMY_REG 0x1571 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x1572 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x1573 -#define mmSDMA1_PAGE_RB_AQL_CNTL 0x1574 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x1575 -#define mmSDMA1_PAGE_MIDCMD_DATA0 0x1580 -#define mmSDMA1_PAGE_MIDCMD_DATA1 0x1581 -#define mmSDMA1_PAGE_MIDCMD_DATA2 0x1582 -#define mmSDMA1_PAGE_MIDCMD_DATA3 0x1583 -#define mmSDMA1_PAGE_MIDCMD_DATA4 0x1584 -#define mmSDMA1_PAGE_MIDCMD_DATA5 0x1585 -#define mmSDMA1_PAGE_MIDCMD_DATA6 0x1586 -#define mmSDMA1_PAGE_MIDCMD_DATA7 0x1587 -#define mmSDMA1_PAGE_MIDCMD_DATA8 0x1588 -#define mmSDMA1_PAGE_MIDCMD_CNTL 0x1589 -#define mmSDMA1_RLC0_RB_CNTL 0x15A0 -#define mmSDMA1_RLC0_RB_BASE 0x15A1 -#define mmSDMA1_RLC0_RB_BASE_HI 0x15A2 -#define mmSDMA1_RLC0_RB_RPTR 0x15A3 -#define mmSDMA1_RLC0_RB_RPTR_HI 0x15A4 -#define mmSDMA1_RLC0_RB_WPTR 0x15A5 -#define mmSDMA1_RLC0_RB_WPTR_HI 0x15A6 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x15A7 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x15A8 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x15A9 -#define mmSDMA1_RLC0_IB_CNTL 0x15AA -#define mmSDMA1_RLC0_IB_RPTR 0x15AB -#define mmSDMA1_RLC0_IB_OFFSET 0x15AC -#define mmSDMA1_RLC0_IB_BASE_LO 0x15AD -#define mmSDMA1_RLC0_IB_BASE_HI 0x15AE -#define mmSDMA1_RLC0_IB_SIZE 0x15AF -#define mmSDMA1_RLC0_SKIP_CNTL 0x15B0 -#define mmSDMA1_RLC0_CONTEXT_STATUS 0x15B1 -#define mmSDMA1_RLC0_DOORBELL 0x15B2 -#define mmSDMA1_RLC0_STATUS 0x15C8 -#define mmSDMA1_RLC0_DOORBELL_LOG 0x15C9 -#define mmSDMA1_RLC0_WATERMARK 0x15CA -#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x15CB -#define mmSDMA1_RLC0_CSA_ADDR_LO 0x15CC -#define mmSDMA1_RLC0_CSA_ADDR_HI 0x15CD -#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x15CF -#define mmSDMA1_RLC0_PREEMPT 0x15D0 -#define mmSDMA1_RLC0_DUMMY_REG 0x15D1 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x15D2 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x15D3 -#define mmSDMA1_RLC0_RB_AQL_CNTL 0x15D4 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x15D5 -#define mmSDMA1_RLC0_MIDCMD_DATA0 0x15E0 -#define mmSDMA1_RLC0_MIDCMD_DATA1 0x15E1 -#define mmSDMA1_RLC0_MIDCMD_DATA2 0x15E2 -#define mmSDMA1_RLC0_MIDCMD_DATA3 0x15E3 -#define mmSDMA1_RLC0_MIDCMD_DATA4 0x15E4 -#define mmSDMA1_RLC0_MIDCMD_DATA5 0x15E5 -#define mmSDMA1_RLC0_MIDCMD_DATA6 0x15E6 -#define mmSDMA1_RLC0_MIDCMD_DATA7 0x15E7 -#define mmSDMA1_RLC0_MIDCMD_DATA8 0x15E8 -#define mmSDMA1_RLC0_MIDCMD_CNTL 0x15E9 -#define mmSDMA1_RLC1_RB_CNTL 0x1600 -#define mmSDMA1_RLC1_RB_BASE 0x1601 -#define mmSDMA1_RLC1_RB_BASE_HI 0x1602 -#define mmSDMA1_RLC1_RB_RPTR 0x1603 -#define mmSDMA1_RLC1_RB_RPTR_HI 0x1604 -#define mmSDMA1_RLC1_RB_WPTR 0x1605 -#define mmSDMA1_RLC1_RB_WPTR_HI 0x1606 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x1607 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x1608 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x1609 -#define mmSDMA1_RLC1_IB_CNTL 0x160A -#define mmSDMA1_RLC1_IB_RPTR 0x160B -#define mmSDMA1_RLC1_IB_OFFSET 0x160C -#define mmSDMA1_RLC1_IB_BASE_LO 0x160D -#define mmSDMA1_RLC1_IB_BASE_HI 0x160E -#define mmSDMA1_RLC1_IB_SIZE 0x160F -#define mmSDMA1_RLC1_SKIP_CNTL 0x1610 -#define mmSDMA1_RLC1_CONTEXT_STATUS 0x1611 -#define mmSDMA1_RLC1_DOORBELL 0x1612 -#define mmSDMA1_RLC1_STATUS 0x1628 -#define mmSDMA1_RLC1_DOORBELL_LOG 0x1629 -#define mmSDMA1_RLC1_WATERMARK 0x162A -#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x162B -#define mmSDMA1_RLC1_CSA_ADDR_LO 0x162C -#define mmSDMA1_RLC1_CSA_ADDR_HI 0x162D -#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x162F -#define mmSDMA1_RLC1_PREEMPT 0x1630 -#define mmSDMA1_RLC1_DUMMY_REG 0x1631 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x1632 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x1633 -#define mmSDMA1_RLC1_RB_AQL_CNTL 0x1634 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x1635 -#define mmSDMA1_RLC1_MIDCMD_DATA0 0x1640 -#define mmSDMA1_RLC1_MIDCMD_DATA1 0x1641 -#define mmSDMA1_RLC1_MIDCMD_DATA2 0x1642 -#define mmSDMA1_RLC1_MIDCMD_DATA3 0x1643 -#define mmSDMA1_RLC1_MIDCMD_DATA4 0x1644 -#define mmSDMA1_RLC1_MIDCMD_DATA5 0x1645 -#define mmSDMA1_RLC1_MIDCMD_DATA6 0x1646 -#define mmSDMA1_RLC1_MIDCMD_DATA7 0x1647 -#define mmSDMA1_RLC1_MIDCMD_DATA8 0x1648 -#define mmSDMA1_RLC1_MIDCMD_CNTL 0x1649 - - -// Registers from MP0_CRU block - -#define mmMP0_SMNIF_ERROR 0xC04000 -#define mmMP0_SFUSE_PUB 0xC04001 -#define mmMP0_FW_DEBUG_CNT0 0xC04002 -#define mmMP0_FW_DEBUG_CNT1 0xC04003 -#define mmMP0_FW_DEBUG_CNT2 0xC04004 -#define mmMP0_FW_DEBUG_CNT3 0xC04005 -#define mmMP0_FW_DEBUG_SIGNAL0 0xC04006 -#define mmMP0_FW_DEBUG_SIGNAL1 0xC04007 -#define mmMP0_DSM_ENABLE 0xC04008 -#define mmMP0_SOC_INFO 0xC04009 -#define mmMP0_MUTEX_0 0xC0400A -#define mmMP0_MUTEX_1 0xC0400B -#define mmMP0_MUTEX_2 0xC0400C -#define mmMP0_MUTEX_3 0xC0400D -#define mmMP0_PUB_SCRATCH0 0xC0400E -#define mmMP0_PUB_SCRATCH1 0xC0400F -#define mmMP0_PUB_SCRATCH2 0xC04010 -#define mmMP0_PUB_SCRATCH3 0xC04011 -#define mmMP0_RSMU_SECINTR 0xC04040 -#define mmMP0_FW_INTF 0xC04041 -#define mmMP0_FW_CHRONO_LO 0xC04042 -#define mmMP0_FW_CHRONO_HI 0xC04043 -#define mmMP0_PIC0_MASK_0 0xC04080 -#define mmMP0_PIC0_MASK_1 0xC04081 -#define mmMP0_PIC0_MASK_2 0xC04082 -#define mmMP0_PIC0_MASK_3 0xC04083 -#define mmMP0_PIC0_STATUS_0 0xC040AC -#define mmMP0_PIC0_STATUS_1 0xC040AD -#define mmMP0_PIC0_STATUS_2 0xC040AE -#define mmMP0_PIC0_STATUS_3 0xC040AF -#define mmMP0_PIC0_INTR 0xC040B0 -#define mmMP0_PIC0_ID 0xC040B1 -#define mmMP0_PIC1_MASK_0 0xC040C0 -#define mmMP0_PIC1_MASK_1 0xC040C1 -#define mmMP0_PIC1_MASK_2 0xC040C2 -#define mmMP0_PIC1_MASK_3 0xC040C3 -#define mmMP0_PIC1_STATUS_0 0xC040EC -#define mmMP0_PIC1_STATUS_1 0xC040ED -#define mmMP0_PIC1_STATUS_2 0xC040EE -#define mmMP0_PIC1_STATUS_3 0xC040EF -#define mmMP0_PIC1_INTR 0xC040F0 -#define mmMP0_PIC1_ID 0xC040F1 -#define mmMP0_TIMER_0_CTRL0 0xC04100 -#define mmMP0_TIMER_1_CTRL0 0xC04109 -#define mmMP0_TIMER_2_CTRL0 0xC04112 -#define mmMP0_TIMER_3_CTRL0 0xC0411B -#define mmMP0_TIMER_0_CTRL1 0xC04101 -#define mmMP0_TIMER_1_CTRL1 0xC0410A -#define mmMP0_TIMER_2_CTRL1 0xC04113 -#define mmMP0_TIMER_3_CTRL1 0xC0411C -#define mmMP0_TIMER_0_CMP0_AUTOINC 0xC04102 -#define mmMP0_TIMER_1_CMP0_AUTOINC 0xC0410B -#define mmMP0_TIMER_2_CMP0_AUTOINC 0xC04114 -#define mmMP0_TIMER_3_CMP0_AUTOINC 0xC0411D -#define mmMP0_TIMER_0_INTEN 0xC04103 -#define mmMP0_TIMER_1_INTEN 0xC0410C -#define mmMP0_TIMER_2_INTEN 0xC04115 -#define mmMP0_TIMER_3_INTEN 0xC0411E -#define mmMP0_TIMER_OCMP0_0_0 0xC04104 -#define mmMP0_TIMER_OCMP0_1_0 0xC0410D -#define mmMP0_TIMER_OCMP0_2_0 0xC04116 -#define mmMP0_TIMER_OCMP0_3_0 0xC0411F -#define mmMP0_TIMER_OCMP0_0_1 0xC04105 -#define mmMP0_TIMER_OCMP0_1_1 0xC0410E -#define mmMP0_TIMER_OCMP0_2_1 0xC04117 -#define mmMP0_TIMER_OCMP0_3_1 0xC04120 -#define mmMP0_TIMER_OCMP0_0_2 0xC04106 -#define mmMP0_TIMER_OCMP0_1_2 0xC0410F -#define mmMP0_TIMER_OCMP0_2_2 0xC04118 -#define mmMP0_TIMER_OCMP0_3_2 0xC04121 -#define mmMP0_TIMER_OCMP0_0_3 0xC04107 -#define mmMP0_TIMER_OCMP0_1_3 0xC04110 -#define mmMP0_TIMER_OCMP0_2_3 0xC04119 -#define mmMP0_TIMER_OCMP0_3_3 0xC04122 -#define mmMP0_TIMER_0_CNT 0xC04108 -#define mmMP0_TIMER_1_CNT 0xC04111 -#define mmMP0_TIMER_2_CNT 0xC0411A -#define mmMP0_TIMER_3_CNT 0xC04123 -#define mmMP0_C2PMSG_0 0xC04140 -#define mmMP0_C2PMSG_1 0xC04141 -#define mmMP0_C2PMSG_2 0xC04142 -#define mmMP0_C2PMSG_3 0xC04143 -#define mmMP0_C2PMSG_4 0xC04144 -#define mmMP0_C2PMSG_5 0xC04145 -#define mmMP0_C2PMSG_6 0xC04146 -#define mmMP0_C2PMSG_7 0xC04147 -#define mmMP0_C2PMSG_8 0xC04148 -#define mmMP0_C2PMSG_9 0xC04149 -#define mmMP0_C2PMSG_10 0xC0414A -#define mmMP0_C2PMSG_11 0xC0414B -#define mmMP0_C2PMSG_12 0xC0414C -#define mmMP0_C2PMSG_13 0xC0414D -#define mmMP0_C2PMSG_14 0xC0414E -#define mmMP0_C2PMSG_15 0xC0414F -#define mmMP0_C2PMSG_16 0xC04150 -#define mmMP0_C2PMSG_17 0xC04151 -#define mmMP0_C2PMSG_18 0xC04152 -#define mmMP0_C2PMSG_19 0xC04153 -#define mmMP0_C2PMSG_20 0xC04154 -#define mmMP0_C2PMSG_21 0xC04155 -#define mmMP0_C2PMSG_22 0xC04156 -#define mmMP0_C2PMSG_23 0xC04157 -#define mmMP0_C2PMSG_24 0xC04158 -#define mmMP0_C2PMSG_25 0xC04159 -#define mmMP0_C2PMSG_26 0xC0415A -#define mmMP0_C2PMSG_27 0xC0415B -#define mmMP0_C2PMSG_28 0xC0415C -#define mmMP0_C2PMSG_29 0xC0415D -#define mmMP0_C2PMSG_30 0xC0415E -#define mmMP0_C2PMSG_31 0xC0415F -#define mmMP0_C2PMSG_32 0xC04260 -#define mmMP0_C2PMSG_33 0xC04261 -#define mmMP0_C2PMSG_34 0xC04262 -#define mmMP0_C2PMSG_35 0xC04263 -#define mmMP0_C2PMSG_36 0xC04264 -#define mmMP0_C2PMSG_37 0xC04265 -#define mmMP0_C2PMSG_38 0xC04266 -#define mmMP0_C2PMSG_39 0xC04267 -#define mmMP0_C2PMSG_40 0xC04268 -#define mmMP0_C2PMSG_41 0xC04269 -#define mmMP0_C2PMSG_42 0xC0426A -#define mmMP0_C2PMSG_43 0xC0426B -#define mmMP0_C2PMSG_44 0xC0426C -#define mmMP0_C2PMSG_45 0xC0426D -#define mmMP0_C2PMSG_46 0xC0426E -#define mmMP0_C2PMSG_47 0xC0426F -#define mmMP0_C2PMSG_48 0xC04270 -#define mmMP0_C2PMSG_49 0xC04271 -#define mmMP0_C2PMSG_50 0xC04272 -#define mmMP0_C2PMSG_51 0xC04273 -#define mmMP0_C2PMSG_52 0xC04274 -#define mmMP0_C2PMSG_53 0xC04275 -#define mmMP0_C2PMSG_54 0xC04276 -#define mmMP0_C2PMSG_55 0xC04277 -#define mmMP0_C2PMSG_56 0xC04278 -#define mmMP0_C2PMSG_57 0xC04279 -#define mmMP0_C2PMSG_58 0xC0427A -#define mmMP0_C2PMSG_59 0xC0427B -#define mmMP0_C2PMSG_60 0xC0427C -#define mmMP0_C2PMSG_61 0xC0427D -#define mmMP0_C2PMSG_62 0xC0427E -#define mmMP0_C2PMSG_63 0xC0427F -#define mmMP0_C2PMSG_64 0xC04280 -#define mmMP0_C2PMSG_65 0xC04281 -#define mmMP0_C2PMSG_66 0xC04282 -#define mmMP0_C2PMSG_67 0xC04283 -#define mmMP0_C2PMSG_68 0xC04284 -#define mmMP0_C2PMSG_69 0xC04285 -#define mmMP0_C2PMSG_70 0xC04286 -#define mmMP0_C2PMSG_71 0xC04287 -#define mmMP0_C2PMSG_72 0xC04288 -#define mmMP0_C2PMSG_73 0xC04289 -#define mmMP0_C2PMSG_74 0xC0428A -#define mmMP0_C2PMSG_75 0xC0428B -#define mmMP0_C2PMSG_76 0xC0428C -#define mmMP0_C2PMSG_77 0xC0428D -#define mmMP0_C2PMSG_78 0xC0428E -#define mmMP0_C2PMSG_79 0xC0428F -#define mmMP0_C2PMSG_80 0xC04290 -#define mmMP0_C2PMSG_81 0xC04291 -#define mmMP0_C2PMSG_82 0xC04292 -#define mmMP0_C2PMSG_83 0xC04293 -#define mmMP0_C2PMSG_84 0xC04294 -#define mmMP0_C2PMSG_85 0xC04295 -#define mmMP0_C2PMSG_86 0xC04296 -#define mmMP0_C2PMSG_87 0xC04297 -#define mmMP0_C2PMSG_88 0xC04298 -#define mmMP0_C2PMSG_89 0xC04299 -#define mmMP0_C2PMSG_90 0xC0429A -#define mmMP0_C2PMSG_91 0xC0429B -#define mmMP0_C2PMSG_92 0xC0429C -#define mmMP0_C2PMSG_93 0xC0429D -#define mmMP0_C2PMSG_94 0xC0429E -#define mmMP0_C2PMSG_95 0xC0429F -#define mmMP0_P2CMSG_0 0xC041A0 -#define mmMP0_P2CMSG_1 0xC041A1 -#define mmMP0_P2CMSG_2 0xC041A2 -#define mmMP0_P2CMSG_3 0xC041A3 -#define mmMP0_P2CMSG_INTEN 0xC041A4 -#define mmMP0_P2CMSG_INTSTS 0xC041A5 -#define mmMP0_C2PMSG_ATTR_0 0xC041A6 -#define mmMP0_C2PMSG_ATTR_1 0xC041A7 -#define mmMP0_C2PMSG_ATTR_2 0xC041A8 -#define mmMP0_C2PMSG_ATTR_3 0xC041A9 -#define mmMP0_C2PMSG_ATTR_4 0xC041AA -#define mmMP0_C2PMSG_ATTR_5 0xC041AB -#define mmMP0_P2CMSG_ATTR 0xC041AC -#define mmMP0_P2SMSG_0 0xC041C0 -#define mmMP0_P2SMSG_1 0xC041C1 -#define mmMP0_P2SMSG_2 0xC041C2 -#define mmMP0_P2SMSG_3 0xC041C3 -#define mmMP0_P2SMSG_ATTR 0xC041C4 -#define mmMP0_S2PMSG_ATTR 0xC041C5 -#define mmMP0_P2SMSG_INTSTS 0xC041C6 -#define mmMP0_S2PMSG_0 0xC041C7 -#define mmMP0_PUB_RSMU_HCID 0xC041E0 -#define mmMP0_PUB_RSMU_SIID 0xC041E1 -#define mmMP0_SAM_IH_EXT_ERR_INTR 0xC04240 -#define mmMP0_SAM_IH_EXT_ERR_INTR_STATUS 0xC04241 -#define mmMP0_REVID 0xC80000 -#define mmMP0_RSMU_HCID 0xC80001 -#define mmMP0_RSMU_SIID 0xC80002 -#define mmMP0_RAM_REPAIR_DONE 0xC80003 -#define mmMP0_RAM_REPAIR_RESULT 0xC80004 -#define mmMP0_FUSE_HARVESTING 0xC80005 -#define mmMP0_FUSE_RMBITS 0xC80006 -#define mmMP0_SMS_CFG 0xC80007 -#define mmMP0_FUSE_SMS_0 0xC80008 -#define mmMP0_FUSE_SMS_1 0xC80009 -#define mmMP0_FUSE_SMS_2 0xC8000A -#define mmMP0_FUSE_SMS_3 0xC8000B -#define mmMP0_FUSE_SMS_4 0xC8000C -#define mmMP0_FUSE_SMS_5 0xC8000D -#define mmMP0_FUSE_SMS_6 0xC8000E -#define mmMP0_FUSE_SMS_7 0xC8000F -#define mmMP0_ACC_VIO_INTSTS 0xC80010 -#define mmMP0_TDR_MISC0_STATUS 0xC80011 -#define mmMP0_FW_OVERRIDE 0xC80012 -#define mmMP0_BOOTROM_REVID 0xC80013 -#define mmMP0_CRU_CPU_CTRL_STS 0xC80014 -#define mmMP0_SFUSE_SEC 0xC80015 -#define mmMP0_COLD_BOOT_EVENTS 0xC80016 -#define mmMP0_WARM_BOOT_EVENTS 0xC80017 -#define mmMP0_NSWORLD_P2CMSG_INTR_CTRL 0xC80018 -#define mmMP0_NSWORLD_P2CMSG_CTRL 0xC80019 -#define mmMP0_NSWORLD_C2PMSG_CTRL 0xC8001A -#define mmMP0_NSWORLD_C2PMSG_CTRL_1 0xC8001B -#define mmMP0_NSWORLD_C2PMSG_CTRL_2 0xC8001C -#define mmMP0_NSWORLD_P2SMSG_CTRL 0xC8001D -#define mmMP0_NSWORLD_S2PMSG_CTRL 0xC8001E -#define mmMP0_NSWORLD_PIC0_CTRL_0 0xC8001F -#define mmMP0_NSWORLD_PIC0_CTRL_1 0xC80020 -#define mmMP0_NSWORLD_PIC0_CTRL_2 0xC80021 -#define mmMP0_NSWORLD_PIC0_CTRL_3 0xC80022 -#define mmMP0_NSWORLD_PIC1_CTRL_0 0xC80023 -#define mmMP0_NSWORLD_PIC1_CTRL_1 0xC80024 -#define mmMP0_NSWORLD_PIC1_CTRL_2 0xC80025 -#define mmMP0_NSWORLD_PIC1_CTRL_3 0xC80026 -#define mmMP0_NSWORLD_TIMER_CTRL 0xC80027 -#define mmMP0_EVCNTCTL 0xC80028 -#define mmMP0_EVCNTSEL 0xC80029 -#define mmMP0_EVCNT0 0xC8002A -#define mmMP0_EVCNT1 0xC8002B -#define mmMP0_EVCNTHI 0xC8002C -#define mmMP0_J2P_MBOX0 0xC8002D -#define mmMP0_J2P_MBOX1 0xC8002E -#define mmMP0_J2P_ATTR 0xC8002F -#define mmMP0_CRU_ACC_VIO_INTSTS 0xC80030 -#define mmMP0_ACC_VIOL_LOG0 0xC80031 -#define mmMP0_ACC_VIOL_LOG1 0xC80032 -#define mmMP0_SEC_SCRATCH0 0xC80033 -#define mmMP0_SEC_SCRATCH1 0xC80034 -#define mmMP0_SEC_SCRATCH2 0xC80035 -#define mmMP0_SEC_SCRATCH3 0xC80036 -#define mmMP0_STICKY 0xC80037 -#define mmMP0_CRU_MISC_CTRL 0xC80038 -#define mmMP0_SOFT_RESET_CTRL 0xC80039 -#define mmMP0_NS_PROT_FAULT_STATUS_0 0xC8003A -#define mmMP0_FW_STATUS 0xC8003B -#define mmMP0_ROM_FW_CNTL 0xC8003C -#define mmMP0_FW_MISC_CTRL 0xC8003D -#define mmMP0_AEB_STATUS_0 0xC8003E -#define mmMP0_AEB_STATUS_1 0xC8003F -#define mmMP0_AEB_JTAG_DBG_CTRL 0xC80040 -#define mmMP0_AEB_JTAG_DBG_CTRL_LOCK 0xC80041 -#define mmMP0_AEB_CNTL_0 0xC80042 -#define mmMP0_AEB_CNTL_1 0xC80043 -#define mmMP0_PIC0_LEVEL_0 0xC80084 -#define mmMP0_PIC0_LEVEL_1 0xC80085 -#define mmMP0_PIC0_LEVEL_2 0xC80086 -#define mmMP0_PIC0_LEVEL_3 0xC80087 -#define mmMP0_PIC0_EDGE_0 0xC80088 -#define mmMP0_PIC0_EDGE_1 0xC80089 -#define mmMP0_PIC0_EDGE_2 0xC8008A -#define mmMP0_PIC0_EDGE_3 0xC8008B -#define mmMP0_PIC0_PRIORITY_0 0xC8008C -#define mmMP0_PIC0_PRIORITY_1 0xC8008D -#define mmMP0_PIC0_PRIORITY_2 0xC8008E -#define mmMP0_PIC0_PRIORITY_3 0xC8008F -#define mmMP0_PIC0_PRIORITY_4 0xC80090 -#define mmMP0_PIC0_PRIORITY_5 0xC80091 -#define mmMP0_PIC0_PRIORITY_6 0xC80092 -#define mmMP0_PIC0_PRIORITY_7 0xC80093 -#define mmMP0_PIC0_PRIORITY_8 0xC80094 -#define mmMP0_PIC0_PRIORITY_9 0xC80095 -#define mmMP0_PIC0_PRIORITY_10 0xC80096 -#define mmMP0_PIC0_PRIORITY_11 0xC80097 -#define mmMP0_PIC0_PRIORITY_12 0xC80098 -#define mmMP0_PIC0_PRIORITY_13 0xC80099 -#define mmMP0_PIC0_PRIORITY_14 0xC8009A -#define mmMP0_PIC0_PRIORITY_15 0xC8009B -#define mmMP0_PIC0_PRIORITY_16 0xC8009C -#define mmMP0_PIC0_PRIORITY_17 0xC8009D -#define mmMP0_PIC0_PRIORITY_18 0xC8009E -#define mmMP0_PIC0_PRIORITY_19 0xC8009F -#define mmMP0_PIC0_PRIORITY_20 0xC800A0 -#define mmMP0_PIC0_PRIORITY_21 0xC800A1 -#define mmMP0_PIC0_PRIORITY_22 0xC800A2 -#define mmMP0_PIC0_PRIORITY_23 0xC800A3 -#define mmMP0_PIC0_PRIORITY_24 0xC800A4 -#define mmMP0_PIC0_PRIORITY_25 0xC800A5 -#define mmMP0_PIC0_PRIORITY_26 0xC800A6 -#define mmMP0_PIC0_PRIORITY_27 0xC800A7 -#define mmMP0_PIC0_PRIORITY_28 0xC800A8 -#define mmMP0_PIC0_PRIORITY_29 0xC800A9 -#define mmMP0_PIC0_PRIORITY_30 0xC800AA -#define mmMP0_PIC0_PRIORITY_31 0xC800AB -#define mmMP0_PIC1_LEVEL_0 0xC800C4 -#define mmMP0_PIC1_LEVEL_1 0xC800C5 -#define mmMP0_PIC1_LEVEL_2 0xC800C6 -#define mmMP0_PIC1_LEVEL_3 0xC800C7 -#define mmMP0_PIC1_EDGE_0 0xC800C8 -#define mmMP0_PIC1_EDGE_1 0xC800C9 -#define mmMP0_PIC1_EDGE_2 0xC800CA -#define mmMP0_PIC1_EDGE_3 0xC800CB -#define mmMP0_PIC1_PRIORITY_0 0xC800CC -#define mmMP0_PIC1_PRIORITY_1 0xC800CD -#define mmMP0_PIC1_PRIORITY_2 0xC800CE -#define mmMP0_PIC1_PRIORITY_3 0xC800CF -#define mmMP0_PIC1_PRIORITY_4 0xC800D0 -#define mmMP0_PIC1_PRIORITY_5 0xC800D1 -#define mmMP0_PIC1_PRIORITY_6 0xC800D2 -#define mmMP0_PIC1_PRIORITY_7 0xC800D3 -#define mmMP0_PIC1_PRIORITY_8 0xC800D4 -#define mmMP0_PIC1_PRIORITY_9 0xC800D5 -#define mmMP0_PIC1_PRIORITY_10 0xC800D6 -#define mmMP0_PIC1_PRIORITY_11 0xC800D7 -#define mmMP0_PIC1_PRIORITY_12 0xC800D8 -#define mmMP0_PIC1_PRIORITY_13 0xC800D9 -#define mmMP0_PIC1_PRIORITY_14 0xC800DA -#define mmMP0_PIC1_PRIORITY_15 0xC800DB -#define mmMP0_PIC1_PRIORITY_16 0xC800DC -#define mmMP0_PIC1_PRIORITY_17 0xC800DD -#define mmMP0_PIC1_PRIORITY_18 0xC800DE -#define mmMP0_PIC1_PRIORITY_19 0xC800DF -#define mmMP0_PIC1_PRIORITY_20 0xC800E0 -#define mmMP0_PIC1_PRIORITY_21 0xC800E1 -#define mmMP0_PIC1_PRIORITY_22 0xC800E2 -#define mmMP0_PIC1_PRIORITY_23 0xC800E3 -#define mmMP0_PIC1_PRIORITY_24 0xC800E4 -#define mmMP0_PIC1_PRIORITY_25 0xC800E5 -#define mmMP0_PIC1_PRIORITY_26 0xC800E6 -#define mmMP0_PIC1_PRIORITY_27 0xC800E7 -#define mmMP0_PIC1_PRIORITY_28 0xC800E8 -#define mmMP0_PIC1_PRIORITY_29 0xC800E9 -#define mmMP0_PIC1_PRIORITY_30 0xC800EA -#define mmMP0_PIC1_PRIORITY_31 0xC800EB -#define mmMP0_SAM_IH_EXT_ERR_INTR_ACK 0xC80240 -#define mmMP0_RSMU_SECINTR_FETCH0 0xC80280 -#define mmMP0_RSMU_SECINTR_FETCH1 0xC80281 -#define mmMP0_RSMU_SECINTR_STATUS 0xC80282 -#define mmMP0_RSMU_SECINTR_FLUSH0 0xC80283 -#define mmMP0_RSMU_SECINTR_FLUSH1 0xC80284 -#define mmMP0_RSMU_SECINTR_CTRL 0xC80285 -#define mmMP0_RSMU_SECINTR_OFCNT 0xC80286 - - -// Registers from MP0_CRU_SMN block - -#define mmMP0_SMN_SAM_IH_EXT_ERR_INTR 0x16040 -#define mmMP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS 0x16041 -#define mmMP0_SMN_C2PMSG_32 0x16060 -#define mmMP0_SMN_C2PMSG_33 0x16061 -#define mmMP0_SMN_C2PMSG_34 0x16062 -#define mmMP0_SMN_C2PMSG_35 0x16063 -#define mmMP0_SMN_C2PMSG_36 0x16064 -#define mmMP0_SMN_C2PMSG_37 0x16065 -#define mmMP0_SMN_C2PMSG_38 0x16066 -#define mmMP0_SMN_C2PMSG_39 0x16067 -#define mmMP0_SMN_C2PMSG_40 0x16068 -#define mmMP0_SMN_C2PMSG_41 0x16069 -#define mmMP0_SMN_C2PMSG_42 0x1606A -#define mmMP0_SMN_C2PMSG_43 0x1606B -#define mmMP0_SMN_C2PMSG_44 0x1606C -#define mmMP0_SMN_C2PMSG_45 0x1606D -#define mmMP0_SMN_C2PMSG_46 0x1606E -#define mmMP0_SMN_C2PMSG_47 0x1606F -#define mmMP0_SMN_C2PMSG_48 0x16070 -#define mmMP0_SMN_C2PMSG_49 0x16071 -#define mmMP0_SMN_C2PMSG_50 0x16072 -#define mmMP0_SMN_C2PMSG_51 0x16073 -#define mmMP0_SMN_C2PMSG_52 0x16074 -#define mmMP0_SMN_C2PMSG_53 0x16075 -#define mmMP0_SMN_C2PMSG_54 0x16076 -#define mmMP0_SMN_C2PMSG_55 0x16077 -#define mmMP0_SMN_C2PMSG_56 0x16078 -#define mmMP0_SMN_C2PMSG_57 0x16079 -#define mmMP0_SMN_C2PMSG_58 0x1607A -#define mmMP0_SMN_C2PMSG_59 0x1607B -#define mmMP0_SMN_C2PMSG_60 0x1607C -#define mmMP0_SMN_C2PMSG_61 0x1607D -#define mmMP0_SMN_C2PMSG_62 0x1607E -#define mmMP0_SMN_C2PMSG_63 0x1607F -#define mmMP0_SMN_C2PMSG_64 0x16080 -#define mmMP0_SMN_C2PMSG_65 0x16081 -#define mmMP0_SMN_C2PMSG_66 0x16082 -#define mmMP0_SMN_C2PMSG_67 0x16083 -#define mmMP0_SMN_C2PMSG_68 0x16084 -#define mmMP0_SMN_C2PMSG_69 0x16085 -#define mmMP0_SMN_C2PMSG_70 0x16086 -#define mmMP0_SMN_C2PMSG_71 0x16087 -#define mmMP0_SMN_C2PMSG_72 0x16088 -#define mmMP0_SMN_C2PMSG_73 0x16089 -#define mmMP0_SMN_C2PMSG_74 0x1608A -#define mmMP0_SMN_C2PMSG_75 0x1608B -#define mmMP0_SMN_C2PMSG_76 0x1608C -#define mmMP0_SMN_C2PMSG_77 0x1608D -#define mmMP0_SMN_C2PMSG_78 0x1608E -#define mmMP0_SMN_C2PMSG_79 0x1608F -#define mmMP0_SMN_C2PMSG_80 0x16090 -#define mmMP0_SMN_C2PMSG_81 0x16091 -#define mmMP0_SMN_C2PMSG_82 0x16092 -#define mmMP0_SMN_C2PMSG_83 0x16093 -#define mmMP0_SMN_C2PMSG_84 0x16094 -#define mmMP0_SMN_C2PMSG_85 0x16095 -#define mmMP0_SMN_C2PMSG_86 0x16096 -#define mmMP0_SMN_C2PMSG_87 0x16097 -#define mmMP0_SMN_C2PMSG_88 0x16098 -#define mmMP0_SMN_C2PMSG_89 0x16099 -#define mmMP0_SMN_C2PMSG_90 0x1609A -#define mmMP0_SMN_C2PMSG_91 0x1609B -#define mmMP0_SMN_C2PMSG_92 0x1609C -#define mmMP0_SMN_C2PMSG_93 0x1609D -#define mmMP0_SMN_C2PMSG_94 0x1609E -#define mmMP0_SMN_C2PMSG_95 0x1609F - - -// Registers from MP0_CRU_RSMU block - -#define mmMP0_RSMU_PUB_RSMU_HCID 0x13FE0 -#define mmMP0_RSMU_PUB_RSMU_SIID 0x13FE1 - - -// Registers from MP0_MMU block - -#define mmMP0_MMU_SRAM_FLOP_START_ADDR 0xC84000 -#define mmMP0_MMU_SRAM_ACC_VIOLATION_LOG_ADDR 0xC84001 -#define mmMP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS 0xC84002 -#define mmMP0_MMU_MISC_CNTL 0xC84003 -#define mmMP0_MMU_ACCESS_ERR_LOG 0xC84004 -#define mmMP0_MMU_SRAM_UNSECURE_BAR 0xC84005 -#define mmMP0_MMU_SCRATCH_0 0xC84006 -#define mmMP0_MMU_SCRATCH_1 0xC84007 -#define mmMP0_MMU_SCRATCH_2 0xC84008 -#define mmMP0_MMU_SCRATCH_3 0xC84009 -#define mmMP0_MMU_SCRATCH_4 0xC8400A -#define mmMP0_MMU_SCRATCH_5 0xC8400B -#define mmMP0_MMU_SCRATCH_6 0xC8400C -#define mmMP0_MMU_SCRATCH_7 0xC8400D -#define mmMP0_MCA_ACCESS_CNTL 0xC0C000 -#define mmMP0_MCA_ACCESS_WR_DATA 0xC0C001 -#define mmMP0_MCA_ACCESS_RD_DATA 0xC0C002 - - -// Registers from MP0_HUBIF block - -#define mmMP0_MMHUB_SOC_TLB0_1 0xC90000 -#define mmMP0_MMHUB_SOC_TLB0_2 0xC90004 -#define mmMP0_MMHUB_SOC_TLB0_3 0xC90008 -#define mmMP0_MMHUB_SOC_TLB0_4 0xC9000C -#define mmMP0_MMHUB_SOC_TLB0_5 0xC90010 -#define mmMP0_MMHUB_SOC_TLB0_6 0xC90014 -#define mmMP0_MMHUB_SOC_TLB0_7 0xC90018 -#define mmMP0_MMHUB_SOC_TLB0_8 0xC9001C -#define mmMP0_MMHUB_SOC_TLB0_9 0xC90020 -#define mmMP0_MMHUB_SOC_TLB0_10 0xC90024 -#define mmMP0_MMHUB_SOC_TLB0_11 0xC90028 -#define mmMP0_MMHUB_SOC_TLB0_12 0xC9002C -#define mmMP0_MMHUB_SOC_TLB0_13 0xC90030 -#define mmMP0_MMHUB_SOC_TLB0_14 0xC90034 -#define mmMP0_MMHUB_SOC_TLB0_15 0xC90038 -#define mmMP0_MMHUB_SOC_TLB0_16 0xC9003C -#define mmMP0_MMHUB_SOC_TLB0_17 0xC90040 -#define mmMP0_MMHUB_SOC_TLB0_18 0xC90044 -#define mmMP0_MMHUB_SOC_TLB0_19 0xC90048 -#define mmMP0_MMHUB_SOC_TLB0_20 0xC9004C -#define mmMP0_MMHUB_SOC_TLB0_21 0xC90050 -#define mmMP0_MMHUB_SOC_TLB0_22 0xC90054 -#define mmMP0_MMHUB_SOC_TLB0_23 0xC90058 -#define mmMP0_MMHUB_SOC_TLB0_24 0xC9005C -#define mmMP0_MMHUB_SOC_TLB0_25 0xC90060 -#define mmMP0_MMHUB_SOC_TLB0_26 0xC90064 -#define mmMP0_MMHUB_SOC_TLB0_27 0xC90068 -#define mmMP0_MMHUB_SOC_TLB0_28 0xC9006C -#define mmMP0_MMHUB_SOC_TLB0_29 0xC90070 -#define mmMP0_MMHUB_SOC_TLB0_30 0xC90074 -#define mmMP0_MMHUB_SOC_TLB0_31 0xC90078 -#define mmMP0_MMHUB_SOC_TLB0_32 0xC9007C -#define mmMP0_MMHUB_SOC_TLB0_33 0xC90080 -#define mmMP0_MMHUB_SOC_TLB0_34 0xC90084 -#define mmMP0_MMHUB_SOC_TLB0_35 0xC90088 -#define mmMP0_MMHUB_SOC_TLB0_36 0xC9008C -#define mmMP0_MMHUB_SOC_TLB0_37 0xC90090 -#define mmMP0_MMHUB_SOC_TLB0_38 0xC90094 -#define mmMP0_MMHUB_SOC_TLB0_39 0xC90098 -#define mmMP0_MMHUB_SOC_TLB0_40 0xC9009C -#define mmMP0_MMHUB_SOC_TLB0_41 0xC900A0 -#define mmMP0_MMHUB_SOC_TLB0_42 0xC900A4 -#define mmMP0_MMHUB_SOC_TLB0_43 0xC900A8 -#define mmMP0_MMHUB_SOC_TLB0_44 0xC900AC -#define mmMP0_MMHUB_SOC_TLB0_45 0xC900B0 -#define mmMP0_MMHUB_SOC_TLB0_46 0xC900B4 -#define mmMP0_MMHUB_SOC_TLB0_47 0xC900B8 -#define mmMP0_MMHUB_SOC_TLB0_48 0xC900BC -#define mmMP0_MMHUB_SOC_TLB0_49 0xC900C0 -#define mmMP0_MMHUB_SOC_TLB0_50 0xC900C4 -#define mmMP0_MMHUB_SOC_TLB0_51 0xC900C8 -#define mmMP0_MMHUB_SOC_TLB0_52 0xC900CC -#define mmMP0_MMHUB_SOC_TLB0_53 0xC900D0 -#define mmMP0_MMHUB_SOC_TLB0_54 0xC900D4 -#define mmMP0_MMHUB_SOC_TLB0_55 0xC900D8 -#define mmMP0_MMHUB_SOC_TLB0_56 0xC900DC -#define mmMP0_MMHUB_SOC_TLB0_57 0xC900E0 -#define mmMP0_MMHUB_SOC_TLB0_58 0xC900E4 -#define mmMP0_MMHUB_SOC_TLB0_59 0xC900E8 -#define mmMP0_MMHUB_SOC_TLB0_60 0xC900EC -#define mmMP0_MMHUB_SOC_TLB0_61 0xC900F0 -#define mmMP0_MMHUB_SOC_TLB0_62 0xC900F4 -#define mmMP0_MMHUB_SOC_TLB1_1 0xC90001 -#define mmMP0_MMHUB_SOC_TLB1_2 0xC90005 -#define mmMP0_MMHUB_SOC_TLB1_3 0xC90009 -#define mmMP0_MMHUB_SOC_TLB1_4 0xC9000D -#define mmMP0_MMHUB_SOC_TLB1_5 0xC90011 -#define mmMP0_MMHUB_SOC_TLB1_6 0xC90015 -#define mmMP0_MMHUB_SOC_TLB1_7 0xC90019 -#define mmMP0_MMHUB_SOC_TLB1_8 0xC9001D -#define mmMP0_MMHUB_SOC_TLB1_9 0xC90021 -#define mmMP0_MMHUB_SOC_TLB1_10 0xC90025 -#define mmMP0_MMHUB_SOC_TLB1_11 0xC90029 -#define mmMP0_MMHUB_SOC_TLB1_12 0xC9002D -#define mmMP0_MMHUB_SOC_TLB1_13 0xC90031 -#define mmMP0_MMHUB_SOC_TLB1_14 0xC90035 -#define mmMP0_MMHUB_SOC_TLB1_15 0xC90039 -#define mmMP0_MMHUB_SOC_TLB1_16 0xC9003D -#define mmMP0_MMHUB_SOC_TLB1_17 0xC90041 -#define mmMP0_MMHUB_SOC_TLB1_18 0xC90045 -#define mmMP0_MMHUB_SOC_TLB1_19 0xC90049 -#define mmMP0_MMHUB_SOC_TLB1_20 0xC9004D -#define mmMP0_MMHUB_SOC_TLB1_21 0xC90051 -#define mmMP0_MMHUB_SOC_TLB1_22 0xC90055 -#define mmMP0_MMHUB_SOC_TLB1_23 0xC90059 -#define mmMP0_MMHUB_SOC_TLB1_24 0xC9005D -#define mmMP0_MMHUB_SOC_TLB1_25 0xC90061 -#define mmMP0_MMHUB_SOC_TLB1_26 0xC90065 -#define mmMP0_MMHUB_SOC_TLB1_27 0xC90069 -#define mmMP0_MMHUB_SOC_TLB1_28 0xC9006D -#define mmMP0_MMHUB_SOC_TLB1_29 0xC90071 -#define mmMP0_MMHUB_SOC_TLB1_30 0xC90075 -#define mmMP0_MMHUB_SOC_TLB1_31 0xC90079 -#define mmMP0_MMHUB_SOC_TLB1_32 0xC9007D -#define mmMP0_MMHUB_SOC_TLB1_33 0xC90081 -#define mmMP0_MMHUB_SOC_TLB1_34 0xC90085 -#define mmMP0_MMHUB_SOC_TLB1_35 0xC90089 -#define mmMP0_MMHUB_SOC_TLB1_36 0xC9008D -#define mmMP0_MMHUB_SOC_TLB1_37 0xC90091 -#define mmMP0_MMHUB_SOC_TLB1_38 0xC90095 -#define mmMP0_MMHUB_SOC_TLB1_39 0xC90099 -#define mmMP0_MMHUB_SOC_TLB1_40 0xC9009D -#define mmMP0_MMHUB_SOC_TLB1_41 0xC900A1 -#define mmMP0_MMHUB_SOC_TLB1_42 0xC900A5 -#define mmMP0_MMHUB_SOC_TLB1_43 0xC900A9 -#define mmMP0_MMHUB_SOC_TLB1_44 0xC900AD -#define mmMP0_MMHUB_SOC_TLB1_45 0xC900B1 -#define mmMP0_MMHUB_SOC_TLB1_46 0xC900B5 -#define mmMP0_MMHUB_SOC_TLB1_47 0xC900B9 -#define mmMP0_MMHUB_SOC_TLB1_48 0xC900BD -#define mmMP0_MMHUB_SOC_TLB1_49 0xC900C1 -#define mmMP0_MMHUB_SOC_TLB1_50 0xC900C5 -#define mmMP0_MMHUB_SOC_TLB1_51 0xC900C9 -#define mmMP0_MMHUB_SOC_TLB1_52 0xC900CD -#define mmMP0_MMHUB_SOC_TLB1_53 0xC900D1 -#define mmMP0_MMHUB_SOC_TLB1_54 0xC900D5 -#define mmMP0_MMHUB_SOC_TLB1_55 0xC900D9 -#define mmMP0_MMHUB_SOC_TLB1_56 0xC900DD -#define mmMP0_MMHUB_SOC_TLB1_57 0xC900E1 -#define mmMP0_MMHUB_SOC_TLB1_58 0xC900E5 -#define mmMP0_MMHUB_SOC_TLB1_59 0xC900E9 -#define mmMP0_MMHUB_SOC_TLB1_60 0xC900ED -#define mmMP0_MMHUB_SOC_TLB1_61 0xC900F1 -#define mmMP0_MMHUB_SOC_TLB1_62 0xC900F5 -#define mmMP0_MMHUB_SOC_TLB2_1 0xC90002 -#define mmMP0_MMHUB_SOC_TLB2_2 0xC90006 -#define mmMP0_MMHUB_SOC_TLB2_3 0xC9000A -#define mmMP0_MMHUB_SOC_TLB2_4 0xC9000E -#define mmMP0_MMHUB_SOC_TLB2_5 0xC90012 -#define mmMP0_MMHUB_SOC_TLB2_6 0xC90016 -#define mmMP0_MMHUB_SOC_TLB2_7 0xC9001A -#define mmMP0_MMHUB_SOC_TLB2_8 0xC9001E -#define mmMP0_MMHUB_SOC_TLB2_9 0xC90022 -#define mmMP0_MMHUB_SOC_TLB2_10 0xC90026 -#define mmMP0_MMHUB_SOC_TLB2_11 0xC9002A -#define mmMP0_MMHUB_SOC_TLB2_12 0xC9002E -#define mmMP0_MMHUB_SOC_TLB2_13 0xC90032 -#define mmMP0_MMHUB_SOC_TLB2_14 0xC90036 -#define mmMP0_MMHUB_SOC_TLB2_15 0xC9003A -#define mmMP0_MMHUB_SOC_TLB2_16 0xC9003E -#define mmMP0_MMHUB_SOC_TLB2_17 0xC90042 -#define mmMP0_MMHUB_SOC_TLB2_18 0xC90046 -#define mmMP0_MMHUB_SOC_TLB2_19 0xC9004A -#define mmMP0_MMHUB_SOC_TLB2_20 0xC9004E -#define mmMP0_MMHUB_SOC_TLB2_21 0xC90052 -#define mmMP0_MMHUB_SOC_TLB2_22 0xC90056 -#define mmMP0_MMHUB_SOC_TLB2_23 0xC9005A -#define mmMP0_MMHUB_SOC_TLB2_24 0xC9005E -#define mmMP0_MMHUB_SOC_TLB2_25 0xC90062 -#define mmMP0_MMHUB_SOC_TLB2_26 0xC90066 -#define mmMP0_MMHUB_SOC_TLB2_27 0xC9006A -#define mmMP0_MMHUB_SOC_TLB2_28 0xC9006E -#define mmMP0_MMHUB_SOC_TLB2_29 0xC90072 -#define mmMP0_MMHUB_SOC_TLB2_30 0xC90076 -#define mmMP0_MMHUB_SOC_TLB2_31 0xC9007A -#define mmMP0_MMHUB_SOC_TLB2_32 0xC9007E -#define mmMP0_MMHUB_SOC_TLB2_33 0xC90082 -#define mmMP0_MMHUB_SOC_TLB2_34 0xC90086 -#define mmMP0_MMHUB_SOC_TLB2_35 0xC9008A -#define mmMP0_MMHUB_SOC_TLB2_36 0xC9008E -#define mmMP0_MMHUB_SOC_TLB2_37 0xC90092 -#define mmMP0_MMHUB_SOC_TLB2_38 0xC90096 -#define mmMP0_MMHUB_SOC_TLB2_39 0xC9009A -#define mmMP0_MMHUB_SOC_TLB2_40 0xC9009E -#define mmMP0_MMHUB_SOC_TLB2_41 0xC900A2 -#define mmMP0_MMHUB_SOC_TLB2_42 0xC900A6 -#define mmMP0_MMHUB_SOC_TLB2_43 0xC900AA -#define mmMP0_MMHUB_SOC_TLB2_44 0xC900AE -#define mmMP0_MMHUB_SOC_TLB2_45 0xC900B2 -#define mmMP0_MMHUB_SOC_TLB2_46 0xC900B6 -#define mmMP0_MMHUB_SOC_TLB2_47 0xC900BA -#define mmMP0_MMHUB_SOC_TLB2_48 0xC900BE -#define mmMP0_MMHUB_SOC_TLB2_49 0xC900C2 -#define mmMP0_MMHUB_SOC_TLB2_50 0xC900C6 -#define mmMP0_MMHUB_SOC_TLB2_51 0xC900CA -#define mmMP0_MMHUB_SOC_TLB2_52 0xC900CE -#define mmMP0_MMHUB_SOC_TLB2_53 0xC900D2 -#define mmMP0_MMHUB_SOC_TLB2_54 0xC900D6 -#define mmMP0_MMHUB_SOC_TLB2_55 0xC900DA -#define mmMP0_MMHUB_SOC_TLB2_56 0xC900DE -#define mmMP0_MMHUB_SOC_TLB2_57 0xC900E2 -#define mmMP0_MMHUB_SOC_TLB2_58 0xC900E6 -#define mmMP0_MMHUB_SOC_TLB2_59 0xC900EA -#define mmMP0_MMHUB_SOC_TLB2_60 0xC900EE -#define mmMP0_MMHUB_SOC_TLB2_61 0xC900F2 -#define mmMP0_MMHUB_SOC_TLB2_62 0xC900F6 -#define mmMP0_MMHUB_SOC_TLB3_1 0xC90003 -#define mmMP0_MMHUB_SOC_TLB3_2 0xC90007 -#define mmMP0_MMHUB_SOC_TLB3_3 0xC9000B -#define mmMP0_MMHUB_SOC_TLB3_4 0xC9000F -#define mmMP0_MMHUB_SOC_TLB3_5 0xC90013 -#define mmMP0_MMHUB_SOC_TLB3_6 0xC90017 -#define mmMP0_MMHUB_SOC_TLB3_7 0xC9001B -#define mmMP0_MMHUB_SOC_TLB3_8 0xC9001F -#define mmMP0_MMHUB_SOC_TLB3_9 0xC90023 -#define mmMP0_MMHUB_SOC_TLB3_10 0xC90027 -#define mmMP0_MMHUB_SOC_TLB3_11 0xC9002B -#define mmMP0_MMHUB_SOC_TLB3_12 0xC9002F -#define mmMP0_MMHUB_SOC_TLB3_13 0xC90033 -#define mmMP0_MMHUB_SOC_TLB3_14 0xC90037 -#define mmMP0_MMHUB_SOC_TLB3_15 0xC9003B -#define mmMP0_MMHUB_SOC_TLB3_16 0xC9003F -#define mmMP0_MMHUB_SOC_TLB3_17 0xC90043 -#define mmMP0_MMHUB_SOC_TLB3_18 0xC90047 -#define mmMP0_MMHUB_SOC_TLB3_19 0xC9004B -#define mmMP0_MMHUB_SOC_TLB3_20 0xC9004F -#define mmMP0_MMHUB_SOC_TLB3_21 0xC90053 -#define mmMP0_MMHUB_SOC_TLB3_22 0xC90057 -#define mmMP0_MMHUB_SOC_TLB3_23 0xC9005B -#define mmMP0_MMHUB_SOC_TLB3_24 0xC9005F -#define mmMP0_MMHUB_SOC_TLB3_25 0xC90063 -#define mmMP0_MMHUB_SOC_TLB3_26 0xC90067 -#define mmMP0_MMHUB_SOC_TLB3_27 0xC9006B -#define mmMP0_MMHUB_SOC_TLB3_28 0xC9006F -#define mmMP0_MMHUB_SOC_TLB3_29 0xC90073 -#define mmMP0_MMHUB_SOC_TLB3_30 0xC90077 -#define mmMP0_MMHUB_SOC_TLB3_31 0xC9007B -#define mmMP0_MMHUB_SOC_TLB3_32 0xC9007F -#define mmMP0_MMHUB_SOC_TLB3_33 0xC90083 -#define mmMP0_MMHUB_SOC_TLB3_34 0xC90087 -#define mmMP0_MMHUB_SOC_TLB3_35 0xC9008B -#define mmMP0_MMHUB_SOC_TLB3_36 0xC9008F -#define mmMP0_MMHUB_SOC_TLB3_37 0xC90093 -#define mmMP0_MMHUB_SOC_TLB3_38 0xC90097 -#define mmMP0_MMHUB_SOC_TLB3_39 0xC9009B -#define mmMP0_MMHUB_SOC_TLB3_40 0xC9009F -#define mmMP0_MMHUB_SOC_TLB3_41 0xC900A3 -#define mmMP0_MMHUB_SOC_TLB3_42 0xC900A7 -#define mmMP0_MMHUB_SOC_TLB3_43 0xC900AB -#define mmMP0_MMHUB_SOC_TLB3_44 0xC900AF -#define mmMP0_MMHUB_SOC_TLB3_45 0xC900B3 -#define mmMP0_MMHUB_SOC_TLB3_46 0xC900B7 -#define mmMP0_MMHUB_SOC_TLB3_47 0xC900BB -#define mmMP0_MMHUB_SOC_TLB3_48 0xC900BF -#define mmMP0_MMHUB_SOC_TLB3_49 0xC900C3 -#define mmMP0_MMHUB_SOC_TLB3_50 0xC900C7 -#define mmMP0_MMHUB_SOC_TLB3_51 0xC900CB -#define mmMP0_MMHUB_SOC_TLB3_52 0xC900CF -#define mmMP0_MMHUB_SOC_TLB3_53 0xC900D3 -#define mmMP0_MMHUB_SOC_TLB3_54 0xC900D7 -#define mmMP0_MMHUB_SOC_TLB3_55 0xC900DB -#define mmMP0_MMHUB_SOC_TLB3_56 0xC900DF -#define mmMP0_MMHUB_SOC_TLB3_57 0xC900E3 -#define mmMP0_MMHUB_SOC_TLB3_58 0xC900E7 -#define mmMP0_MMHUB_SOC_TLB3_59 0xC900EB -#define mmMP0_MMHUB_SOC_TLB3_60 0xC900EF -#define mmMP0_MMHUB_SOC_TLB3_61 0xC900F3 -#define mmMP0_MMHUB_SOC_TLB3_62 0xC900F7 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 0xC900F8 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 0xC900F9 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 0xC900FA -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 0xC900FB -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 0xC900FC -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 0xC900FD -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 0xC900FE -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 0xC900FF -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 0xC90100 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 0xC90101 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 0xC90102 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 0xC90103 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 0xC90104 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 0xC90105 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 0xC90106 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 0xC90107 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 0xC90108 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 0xC90109 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 0xC9010A -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 0xC9010B -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 0xC9010C -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 0xC9010D -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 0xC9010E -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 0xC9010F -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 0xC90110 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 0xC90111 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 0xC90112 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 0xC90113 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 0xC90114 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 0xC90115 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 0xC90116 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 0xC90117 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 0xC90118 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 0xC90119 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 0xC9011A -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 0xC9011B -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 0xC9011C -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 0xC9011D -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 0xC9011E -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 0xC9011F -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 0xC90120 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 0xC90121 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 0xC90122 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 0xC90123 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 0xC90124 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 0xC90125 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 0xC90126 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 0xC90127 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 0xC90128 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 0xC90129 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 0xC9012A -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 0xC9012B -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 0xC9012C -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 0xC9012D -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 0xC9012E -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 0xC9012F -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 0xC90130 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 0xC90131 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 0xC90132 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 0xC90133 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 0xC90134 -#define mmMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 0xC90135 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_1 0xC90136 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_2 0xC90137 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_3 0xC90138 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_4 0xC90139 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_5 0xC9013A -#define mmMP0_MMHUB_TLB_ATTRIBUTE_6 0xC9013B -#define mmMP0_MMHUB_TLB_ATTRIBUTE_7 0xC9013C -#define mmMP0_MMHUB_TLB_ATTRIBUTE_8 0xC9013D -#define mmMP0_MMHUB_TLB_ATTRIBUTE_9 0xC9013E -#define mmMP0_MMHUB_TLB_ATTRIBUTE_10 0xC9013F -#define mmMP0_MMHUB_TLB_ATTRIBUTE_11 0xC90140 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_12 0xC90141 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_13 0xC90142 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_14 0xC90143 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_15 0xC90144 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_16 0xC90145 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_17 0xC90146 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_18 0xC90147 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_19 0xC90148 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_20 0xC90149 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_21 0xC9014A -#define mmMP0_MMHUB_TLB_ATTRIBUTE_22 0xC9014B -#define mmMP0_MMHUB_TLB_ATTRIBUTE_23 0xC9014C -#define mmMP0_MMHUB_TLB_ATTRIBUTE_24 0xC9014D -#define mmMP0_MMHUB_TLB_ATTRIBUTE_25 0xC9014E -#define mmMP0_MMHUB_TLB_ATTRIBUTE_26 0xC9014F -#define mmMP0_MMHUB_TLB_ATTRIBUTE_27 0xC90150 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_28 0xC90151 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_29 0xC90152 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_30 0xC90153 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_31 0xC90154 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_32 0xC90155 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_33 0xC90156 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_34 0xC90157 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_35 0xC90158 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_36 0xC90159 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_37 0xC9015A -#define mmMP0_MMHUB_TLB_ATTRIBUTE_38 0xC9015B -#define mmMP0_MMHUB_TLB_ATTRIBUTE_39 0xC9015C -#define mmMP0_MMHUB_TLB_ATTRIBUTE_40 0xC9015D -#define mmMP0_MMHUB_TLB_ATTRIBUTE_41 0xC9015E -#define mmMP0_MMHUB_TLB_ATTRIBUTE_42 0xC9015F -#define mmMP0_MMHUB_TLB_ATTRIBUTE_43 0xC90160 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_44 0xC90161 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_45 0xC90162 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_46 0xC90163 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_47 0xC90164 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_48 0xC90165 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_49 0xC90166 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_50 0xC90167 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_51 0xC90168 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_52 0xC90169 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_53 0xC9016A -#define mmMP0_MMHUB_TLB_ATTRIBUTE_54 0xC9016B -#define mmMP0_MMHUB_TLB_ATTRIBUTE_55 0xC9016C -#define mmMP0_MMHUB_TLB_ATTRIBUTE_56 0xC9016D -#define mmMP0_MMHUB_TLB_ATTRIBUTE_57 0xC9016E -#define mmMP0_MMHUB_TLB_ATTRIBUTE_58 0xC9016F -#define mmMP0_MMHUB_TLB_ATTRIBUTE_59 0xC90170 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_60 0xC90171 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_61 0xC90172 -#define mmMP0_MMHUB_TLB_ATTRIBUTE_62 0xC90173 -#define mmMP0_MMHUB_INT_STATUS 0xC90174 -#define mmMP0_MMHUB_WR_INT_ADDR 0xC90175 -#define mmMP0_MMHUB_WR_INT_OTHER 0xC90176 -#define mmMP0_MMHUB_RD_INT_ADDR 0xC90177 -#define mmMP0_MMHUB_RD_INT_OTHER 0xC90178 -#define mmMP0_MMHUB_REG_INT_ADDR 0xC90179 -#define mmMP0_MMHUB_REG_INT_OTHER 0xC9017A -#define mmMP0_MMHUB_AXCACHE_CFG 0xC9017B -#define mmMP0_MMHUB_DS_OVERRIDE 0xC9017C -#define mmMP0_MMHUB_OUTSTANDING 0xC9017D -#define mmMP0_SYSHUB_SOC_TLB0_1 0xC8C000 -#define mmMP0_SYSHUB_SOC_TLB0_2 0xC8C004 -#define mmMP0_SYSHUB_SOC_TLB0_3 0xC8C008 -#define mmMP0_SYSHUB_SOC_TLB0_4 0xC8C00C -#define mmMP0_SYSHUB_SOC_TLB0_5 0xC8C010 -#define mmMP0_SYSHUB_SOC_TLB0_6 0xC8C014 -#define mmMP0_SYSHUB_SOC_TLB0_7 0xC8C018 -#define mmMP0_SYSHUB_SOC_TLB0_8 0xC8C01C -#define mmMP0_SYSHUB_SOC_TLB0_9 0xC8C020 -#define mmMP0_SYSHUB_SOC_TLB0_10 0xC8C024 -#define mmMP0_SYSHUB_SOC_TLB0_11 0xC8C028 -#define mmMP0_SYSHUB_SOC_TLB0_12 0xC8C02C -#define mmMP0_SYSHUB_SOC_TLB0_13 0xC8C030 -#define mmMP0_SYSHUB_SOC_TLB0_14 0xC8C034 -#define mmMP0_SYSHUB_SOC_TLB0_15 0xC8C038 -#define mmMP0_SYSHUB_SOC_TLB0_16 0xC8C03C -#define mmMP0_SYSHUB_SOC_TLB0_17 0xC8C040 -#define mmMP0_SYSHUB_SOC_TLB0_18 0xC8C044 -#define mmMP0_SYSHUB_SOC_TLB0_19 0xC8C048 -#define mmMP0_SYSHUB_SOC_TLB0_20 0xC8C04C -#define mmMP0_SYSHUB_SOC_TLB0_21 0xC8C050 -#define mmMP0_SYSHUB_SOC_TLB0_22 0xC8C054 -#define mmMP0_SYSHUB_SOC_TLB0_23 0xC8C058 -#define mmMP0_SYSHUB_SOC_TLB0_24 0xC8C05C -#define mmMP0_SYSHUB_SOC_TLB0_25 0xC8C060 -#define mmMP0_SYSHUB_SOC_TLB0_26 0xC8C064 -#define mmMP0_SYSHUB_SOC_TLB0_27 0xC8C068 -#define mmMP0_SYSHUB_SOC_TLB0_28 0xC8C06C -#define mmMP0_SYSHUB_SOC_TLB0_29 0xC8C070 -#define mmMP0_SYSHUB_SOC_TLB0_30 0xC8C074 -#define mmMP0_SYSHUB_SOC_TLB0_31 0xC8C078 -#define mmMP0_SYSHUB_SOC_TLB0_32 0xC8C07C -#define mmMP0_SYSHUB_SOC_TLB0_33 0xC8C080 -#define mmMP0_SYSHUB_SOC_TLB0_34 0xC8C084 -#define mmMP0_SYSHUB_SOC_TLB0_35 0xC8C088 -#define mmMP0_SYSHUB_SOC_TLB0_36 0xC8C08C -#define mmMP0_SYSHUB_SOC_TLB0_37 0xC8C090 -#define mmMP0_SYSHUB_SOC_TLB0_38 0xC8C094 -#define mmMP0_SYSHUB_SOC_TLB0_39 0xC8C098 -#define mmMP0_SYSHUB_SOC_TLB0_40 0xC8C09C -#define mmMP0_SYSHUB_SOC_TLB0_41 0xC8C0A0 -#define mmMP0_SYSHUB_SOC_TLB0_42 0xC8C0A4 -#define mmMP0_SYSHUB_SOC_TLB0_43 0xC8C0A8 -#define mmMP0_SYSHUB_SOC_TLB0_44 0xC8C0AC -#define mmMP0_SYSHUB_SOC_TLB0_45 0xC8C0B0 -#define mmMP0_SYSHUB_SOC_TLB0_46 0xC8C0B4 -#define mmMP0_SYSHUB_SOC_TLB0_47 0xC8C0B8 -#define mmMP0_SYSHUB_SOC_TLB0_48 0xC8C0BC -#define mmMP0_SYSHUB_SOC_TLB0_49 0xC8C0C0 -#define mmMP0_SYSHUB_SOC_TLB0_50 0xC8C0C4 -#define mmMP0_SYSHUB_SOC_TLB0_51 0xC8C0C8 -#define mmMP0_SYSHUB_SOC_TLB0_52 0xC8C0CC -#define mmMP0_SYSHUB_SOC_TLB0_53 0xC8C0D0 -#define mmMP0_SYSHUB_SOC_TLB0_54 0xC8C0D4 -#define mmMP0_SYSHUB_SOC_TLB0_55 0xC8C0D8 -#define mmMP0_SYSHUB_SOC_TLB0_56 0xC8C0DC -#define mmMP0_SYSHUB_SOC_TLB0_57 0xC8C0E0 -#define mmMP0_SYSHUB_SOC_TLB0_58 0xC8C0E4 -#define mmMP0_SYSHUB_SOC_TLB0_59 0xC8C0E8 -#define mmMP0_SYSHUB_SOC_TLB0_60 0xC8C0EC -#define mmMP0_SYSHUB_SOC_TLB0_61 0xC8C0F0 -#define mmMP0_SYSHUB_SOC_TLB0_62 0xC8C0F4 -#define mmMP0_SYSHUB_SOC_TLB1_1 0xC8C001 -#define mmMP0_SYSHUB_SOC_TLB1_2 0xC8C005 -#define mmMP0_SYSHUB_SOC_TLB1_3 0xC8C009 -#define mmMP0_SYSHUB_SOC_TLB1_4 0xC8C00D -#define mmMP0_SYSHUB_SOC_TLB1_5 0xC8C011 -#define mmMP0_SYSHUB_SOC_TLB1_6 0xC8C015 -#define mmMP0_SYSHUB_SOC_TLB1_7 0xC8C019 -#define mmMP0_SYSHUB_SOC_TLB1_8 0xC8C01D -#define mmMP0_SYSHUB_SOC_TLB1_9 0xC8C021 -#define mmMP0_SYSHUB_SOC_TLB1_10 0xC8C025 -#define mmMP0_SYSHUB_SOC_TLB1_11 0xC8C029 -#define mmMP0_SYSHUB_SOC_TLB1_12 0xC8C02D -#define mmMP0_SYSHUB_SOC_TLB1_13 0xC8C031 -#define mmMP0_SYSHUB_SOC_TLB1_14 0xC8C035 -#define mmMP0_SYSHUB_SOC_TLB1_15 0xC8C039 -#define mmMP0_SYSHUB_SOC_TLB1_16 0xC8C03D -#define mmMP0_SYSHUB_SOC_TLB1_17 0xC8C041 -#define mmMP0_SYSHUB_SOC_TLB1_18 0xC8C045 -#define mmMP0_SYSHUB_SOC_TLB1_19 0xC8C049 -#define mmMP0_SYSHUB_SOC_TLB1_20 0xC8C04D -#define mmMP0_SYSHUB_SOC_TLB1_21 0xC8C051 -#define mmMP0_SYSHUB_SOC_TLB1_22 0xC8C055 -#define mmMP0_SYSHUB_SOC_TLB1_23 0xC8C059 -#define mmMP0_SYSHUB_SOC_TLB1_24 0xC8C05D -#define mmMP0_SYSHUB_SOC_TLB1_25 0xC8C061 -#define mmMP0_SYSHUB_SOC_TLB1_26 0xC8C065 -#define mmMP0_SYSHUB_SOC_TLB1_27 0xC8C069 -#define mmMP0_SYSHUB_SOC_TLB1_28 0xC8C06D -#define mmMP0_SYSHUB_SOC_TLB1_29 0xC8C071 -#define mmMP0_SYSHUB_SOC_TLB1_30 0xC8C075 -#define mmMP0_SYSHUB_SOC_TLB1_31 0xC8C079 -#define mmMP0_SYSHUB_SOC_TLB1_32 0xC8C07D -#define mmMP0_SYSHUB_SOC_TLB1_33 0xC8C081 -#define mmMP0_SYSHUB_SOC_TLB1_34 0xC8C085 -#define mmMP0_SYSHUB_SOC_TLB1_35 0xC8C089 -#define mmMP0_SYSHUB_SOC_TLB1_36 0xC8C08D -#define mmMP0_SYSHUB_SOC_TLB1_37 0xC8C091 -#define mmMP0_SYSHUB_SOC_TLB1_38 0xC8C095 -#define mmMP0_SYSHUB_SOC_TLB1_39 0xC8C099 -#define mmMP0_SYSHUB_SOC_TLB1_40 0xC8C09D -#define mmMP0_SYSHUB_SOC_TLB1_41 0xC8C0A1 -#define mmMP0_SYSHUB_SOC_TLB1_42 0xC8C0A5 -#define mmMP0_SYSHUB_SOC_TLB1_43 0xC8C0A9 -#define mmMP0_SYSHUB_SOC_TLB1_44 0xC8C0AD -#define mmMP0_SYSHUB_SOC_TLB1_45 0xC8C0B1 -#define mmMP0_SYSHUB_SOC_TLB1_46 0xC8C0B5 -#define mmMP0_SYSHUB_SOC_TLB1_47 0xC8C0B9 -#define mmMP0_SYSHUB_SOC_TLB1_48 0xC8C0BD -#define mmMP0_SYSHUB_SOC_TLB1_49 0xC8C0C1 -#define mmMP0_SYSHUB_SOC_TLB1_50 0xC8C0C5 -#define mmMP0_SYSHUB_SOC_TLB1_51 0xC8C0C9 -#define mmMP0_SYSHUB_SOC_TLB1_52 0xC8C0CD -#define mmMP0_SYSHUB_SOC_TLB1_53 0xC8C0D1 -#define mmMP0_SYSHUB_SOC_TLB1_54 0xC8C0D5 -#define mmMP0_SYSHUB_SOC_TLB1_55 0xC8C0D9 -#define mmMP0_SYSHUB_SOC_TLB1_56 0xC8C0DD -#define mmMP0_SYSHUB_SOC_TLB1_57 0xC8C0E1 -#define mmMP0_SYSHUB_SOC_TLB1_58 0xC8C0E5 -#define mmMP0_SYSHUB_SOC_TLB1_59 0xC8C0E9 -#define mmMP0_SYSHUB_SOC_TLB1_60 0xC8C0ED -#define mmMP0_SYSHUB_SOC_TLB1_61 0xC8C0F1 -#define mmMP0_SYSHUB_SOC_TLB1_62 0xC8C0F5 -#define mmMP0_SYSHUB_SOC_TLB2_1 0xC8C002 -#define mmMP0_SYSHUB_SOC_TLB2_2 0xC8C006 -#define mmMP0_SYSHUB_SOC_TLB2_3 0xC8C00A -#define mmMP0_SYSHUB_SOC_TLB2_4 0xC8C00E -#define mmMP0_SYSHUB_SOC_TLB2_5 0xC8C012 -#define mmMP0_SYSHUB_SOC_TLB2_6 0xC8C016 -#define mmMP0_SYSHUB_SOC_TLB2_7 0xC8C01A -#define mmMP0_SYSHUB_SOC_TLB2_8 0xC8C01E -#define mmMP0_SYSHUB_SOC_TLB2_9 0xC8C022 -#define mmMP0_SYSHUB_SOC_TLB2_10 0xC8C026 -#define mmMP0_SYSHUB_SOC_TLB2_11 0xC8C02A -#define mmMP0_SYSHUB_SOC_TLB2_12 0xC8C02E -#define mmMP0_SYSHUB_SOC_TLB2_13 0xC8C032 -#define mmMP0_SYSHUB_SOC_TLB2_14 0xC8C036 -#define mmMP0_SYSHUB_SOC_TLB2_15 0xC8C03A -#define mmMP0_SYSHUB_SOC_TLB2_16 0xC8C03E -#define mmMP0_SYSHUB_SOC_TLB2_17 0xC8C042 -#define mmMP0_SYSHUB_SOC_TLB2_18 0xC8C046 -#define mmMP0_SYSHUB_SOC_TLB2_19 0xC8C04A -#define mmMP0_SYSHUB_SOC_TLB2_20 0xC8C04E -#define mmMP0_SYSHUB_SOC_TLB2_21 0xC8C052 -#define mmMP0_SYSHUB_SOC_TLB2_22 0xC8C056 -#define mmMP0_SYSHUB_SOC_TLB2_23 0xC8C05A -#define mmMP0_SYSHUB_SOC_TLB2_24 0xC8C05E -#define mmMP0_SYSHUB_SOC_TLB2_25 0xC8C062 -#define mmMP0_SYSHUB_SOC_TLB2_26 0xC8C066 -#define mmMP0_SYSHUB_SOC_TLB2_27 0xC8C06A -#define mmMP0_SYSHUB_SOC_TLB2_28 0xC8C06E -#define mmMP0_SYSHUB_SOC_TLB2_29 0xC8C072 -#define mmMP0_SYSHUB_SOC_TLB2_30 0xC8C076 -#define mmMP0_SYSHUB_SOC_TLB2_31 0xC8C07A -#define mmMP0_SYSHUB_SOC_TLB2_32 0xC8C07E -#define mmMP0_SYSHUB_SOC_TLB2_33 0xC8C082 -#define mmMP0_SYSHUB_SOC_TLB2_34 0xC8C086 -#define mmMP0_SYSHUB_SOC_TLB2_35 0xC8C08A -#define mmMP0_SYSHUB_SOC_TLB2_36 0xC8C08E -#define mmMP0_SYSHUB_SOC_TLB2_37 0xC8C092 -#define mmMP0_SYSHUB_SOC_TLB2_38 0xC8C096 -#define mmMP0_SYSHUB_SOC_TLB2_39 0xC8C09A -#define mmMP0_SYSHUB_SOC_TLB2_40 0xC8C09E -#define mmMP0_SYSHUB_SOC_TLB2_41 0xC8C0A2 -#define mmMP0_SYSHUB_SOC_TLB2_42 0xC8C0A6 -#define mmMP0_SYSHUB_SOC_TLB2_43 0xC8C0AA -#define mmMP0_SYSHUB_SOC_TLB2_44 0xC8C0AE -#define mmMP0_SYSHUB_SOC_TLB2_45 0xC8C0B2 -#define mmMP0_SYSHUB_SOC_TLB2_46 0xC8C0B6 -#define mmMP0_SYSHUB_SOC_TLB2_47 0xC8C0BA -#define mmMP0_SYSHUB_SOC_TLB2_48 0xC8C0BE -#define mmMP0_SYSHUB_SOC_TLB2_49 0xC8C0C2 -#define mmMP0_SYSHUB_SOC_TLB2_50 0xC8C0C6 -#define mmMP0_SYSHUB_SOC_TLB2_51 0xC8C0CA -#define mmMP0_SYSHUB_SOC_TLB2_52 0xC8C0CE -#define mmMP0_SYSHUB_SOC_TLB2_53 0xC8C0D2 -#define mmMP0_SYSHUB_SOC_TLB2_54 0xC8C0D6 -#define mmMP0_SYSHUB_SOC_TLB2_55 0xC8C0DA -#define mmMP0_SYSHUB_SOC_TLB2_56 0xC8C0DE -#define mmMP0_SYSHUB_SOC_TLB2_57 0xC8C0E2 -#define mmMP0_SYSHUB_SOC_TLB2_58 0xC8C0E6 -#define mmMP0_SYSHUB_SOC_TLB2_59 0xC8C0EA -#define mmMP0_SYSHUB_SOC_TLB2_60 0xC8C0EE -#define mmMP0_SYSHUB_SOC_TLB2_61 0xC8C0F2 -#define mmMP0_SYSHUB_SOC_TLB2_62 0xC8C0F6 -#define mmMP0_SYSHUB_SOC_TLB3_1 0xC8C003 -#define mmMP0_SYSHUB_SOC_TLB3_2 0xC8C007 -#define mmMP0_SYSHUB_SOC_TLB3_3 0xC8C00B -#define mmMP0_SYSHUB_SOC_TLB3_4 0xC8C00F -#define mmMP0_SYSHUB_SOC_TLB3_5 0xC8C013 -#define mmMP0_SYSHUB_SOC_TLB3_6 0xC8C017 -#define mmMP0_SYSHUB_SOC_TLB3_7 0xC8C01B -#define mmMP0_SYSHUB_SOC_TLB3_8 0xC8C01F -#define mmMP0_SYSHUB_SOC_TLB3_9 0xC8C023 -#define mmMP0_SYSHUB_SOC_TLB3_10 0xC8C027 -#define mmMP0_SYSHUB_SOC_TLB3_11 0xC8C02B -#define mmMP0_SYSHUB_SOC_TLB3_12 0xC8C02F -#define mmMP0_SYSHUB_SOC_TLB3_13 0xC8C033 -#define mmMP0_SYSHUB_SOC_TLB3_14 0xC8C037 -#define mmMP0_SYSHUB_SOC_TLB3_15 0xC8C03B -#define mmMP0_SYSHUB_SOC_TLB3_16 0xC8C03F -#define mmMP0_SYSHUB_SOC_TLB3_17 0xC8C043 -#define mmMP0_SYSHUB_SOC_TLB3_18 0xC8C047 -#define mmMP0_SYSHUB_SOC_TLB3_19 0xC8C04B -#define mmMP0_SYSHUB_SOC_TLB3_20 0xC8C04F -#define mmMP0_SYSHUB_SOC_TLB3_21 0xC8C053 -#define mmMP0_SYSHUB_SOC_TLB3_22 0xC8C057 -#define mmMP0_SYSHUB_SOC_TLB3_23 0xC8C05B -#define mmMP0_SYSHUB_SOC_TLB3_24 0xC8C05F -#define mmMP0_SYSHUB_SOC_TLB3_25 0xC8C063 -#define mmMP0_SYSHUB_SOC_TLB3_26 0xC8C067 -#define mmMP0_SYSHUB_SOC_TLB3_27 0xC8C06B -#define mmMP0_SYSHUB_SOC_TLB3_28 0xC8C06F -#define mmMP0_SYSHUB_SOC_TLB3_29 0xC8C073 -#define mmMP0_SYSHUB_SOC_TLB3_30 0xC8C077 -#define mmMP0_SYSHUB_SOC_TLB3_31 0xC8C07B -#define mmMP0_SYSHUB_SOC_TLB3_32 0xC8C07F -#define mmMP0_SYSHUB_SOC_TLB3_33 0xC8C083 -#define mmMP0_SYSHUB_SOC_TLB3_34 0xC8C087 -#define mmMP0_SYSHUB_SOC_TLB3_35 0xC8C08B -#define mmMP0_SYSHUB_SOC_TLB3_36 0xC8C08F -#define mmMP0_SYSHUB_SOC_TLB3_37 0xC8C093 -#define mmMP0_SYSHUB_SOC_TLB3_38 0xC8C097 -#define mmMP0_SYSHUB_SOC_TLB3_39 0xC8C09B -#define mmMP0_SYSHUB_SOC_TLB3_40 0xC8C09F -#define mmMP0_SYSHUB_SOC_TLB3_41 0xC8C0A3 -#define mmMP0_SYSHUB_SOC_TLB3_42 0xC8C0A7 -#define mmMP0_SYSHUB_SOC_TLB3_43 0xC8C0AB -#define mmMP0_SYSHUB_SOC_TLB3_44 0xC8C0AF -#define mmMP0_SYSHUB_SOC_TLB3_45 0xC8C0B3 -#define mmMP0_SYSHUB_SOC_TLB3_46 0xC8C0B7 -#define mmMP0_SYSHUB_SOC_TLB3_47 0xC8C0BB -#define mmMP0_SYSHUB_SOC_TLB3_48 0xC8C0BF -#define mmMP0_SYSHUB_SOC_TLB3_49 0xC8C0C3 -#define mmMP0_SYSHUB_SOC_TLB3_50 0xC8C0C7 -#define mmMP0_SYSHUB_SOC_TLB3_51 0xC8C0CB -#define mmMP0_SYSHUB_SOC_TLB3_52 0xC8C0CF -#define mmMP0_SYSHUB_SOC_TLB3_53 0xC8C0D3 -#define mmMP0_SYSHUB_SOC_TLB3_54 0xC8C0D7 -#define mmMP0_SYSHUB_SOC_TLB3_55 0xC8C0DB -#define mmMP0_SYSHUB_SOC_TLB3_56 0xC8C0DF -#define mmMP0_SYSHUB_SOC_TLB3_57 0xC8C0E3 -#define mmMP0_SYSHUB_SOC_TLB3_58 0xC8C0E7 -#define mmMP0_SYSHUB_SOC_TLB3_59 0xC8C0EB -#define mmMP0_SYSHUB_SOC_TLB3_60 0xC8C0EF -#define mmMP0_SYSHUB_SOC_TLB3_61 0xC8C0F3 -#define mmMP0_SYSHUB_SOC_TLB3_62 0xC8C0F7 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 0xC8C0F8 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 0xC8C0F9 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 0xC8C0FA -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 0xC8C0FB -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 0xC8C0FC -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 0xC8C0FD -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 0xC8C0FE -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 0xC8C0FF -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 0xC8C100 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 0xC8C101 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 0xC8C102 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 0xC8C103 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 0xC8C104 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 0xC8C105 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 0xC8C106 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 0xC8C107 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 0xC8C108 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 0xC8C109 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 0xC8C10A -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 0xC8C10B -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 0xC8C10C -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 0xC8C10D -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 0xC8C10E -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 0xC8C10F -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 0xC8C110 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 0xC8C111 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 0xC8C112 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 0xC8C113 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 0xC8C114 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 0xC8C115 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 0xC8C116 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 0xC8C117 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 0xC8C118 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 0xC8C119 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 0xC8C11A -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 0xC8C11B -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 0xC8C11C -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 0xC8C11D -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 0xC8C11E -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 0xC8C11F -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 0xC8C120 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 0xC8C121 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 0xC8C122 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 0xC8C123 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 0xC8C124 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 0xC8C125 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 0xC8C126 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 0xC8C127 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 0xC8C128 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 0xC8C129 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 0xC8C12A -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 0xC8C12B -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 0xC8C12C -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 0xC8C12D -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 0xC8C12E -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 0xC8C12F -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 0xC8C130 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 0xC8C131 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 0xC8C132 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 0xC8C133 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 0xC8C134 -#define mmMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 0xC8C135 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_1 0xC8C136 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_2 0xC8C137 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_3 0xC8C138 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_4 0xC8C139 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_5 0xC8C13A -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_6 0xC8C13B -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_7 0xC8C13C -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_8 0xC8C13D -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_9 0xC8C13E -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_10 0xC8C13F -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_11 0xC8C140 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_12 0xC8C141 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_13 0xC8C142 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_14 0xC8C143 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_15 0xC8C144 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_16 0xC8C145 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_17 0xC8C146 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_18 0xC8C147 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_19 0xC8C148 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_20 0xC8C149 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_21 0xC8C14A -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_22 0xC8C14B -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_23 0xC8C14C -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_24 0xC8C14D -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_25 0xC8C14E -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_26 0xC8C14F -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_27 0xC8C150 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_28 0xC8C151 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_29 0xC8C152 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_30 0xC8C153 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_31 0xC8C154 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_32 0xC8C155 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_33 0xC8C156 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_34 0xC8C157 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_35 0xC8C158 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_36 0xC8C159 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_37 0xC8C15A -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_38 0xC8C15B -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_39 0xC8C15C -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_40 0xC8C15D -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_41 0xC8C15E -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_42 0xC8C15F -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_43 0xC8C160 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_44 0xC8C161 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_45 0xC8C162 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_46 0xC8C163 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_47 0xC8C164 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_48 0xC8C165 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_49 0xC8C166 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_50 0xC8C167 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_51 0xC8C168 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_52 0xC8C169 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_53 0xC8C16A -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_54 0xC8C16B -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_55 0xC8C16C -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_56 0xC8C16D -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_57 0xC8C16E -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_58 0xC8C16F -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_59 0xC8C170 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_60 0xC8C171 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_61 0xC8C172 -#define mmMP0_SYSHUB_TLB_ATTRIBUTE_62 0xC8C173 -#define mmMP0_SYSHUB_INT_STATUS 0xC8C174 -#define mmMP0_SYSHUB_WR_INT_ADDR 0xC8C175 -#define mmMP0_SYSHUB_WR_INT_OTHER 0xC8C176 -#define mmMP0_SYSHUB_RD_INT_ADDR 0xC8C177 -#define mmMP0_SYSHUB_RD_INT_OTHER 0xC8C178 -#define mmMP0_SYSHUB_REG_INT_ADDR 0xC8C179 -#define mmMP0_SYSHUB_REG_INT_OTHER 0xC8C17A -#define mmMP0_SYSHUB_AXCACHE_CFG 0xC8C17B -#define mmMP0_SYSHUB_DS_OVERRIDE 0xC8C17C -#define mmMP0_SYSHUB_OUTSTANDING 0xC8C17D - - -// Registers from MP1_CRU block - -#define mmMP1_SMNIF_ERROR 0xC04000 -#define mmMP1_LX3_PDEBUGPC 0xC04001 -#define mmMP1_LX3_PWAITMODE 0xC04002 -#define mmMP1_IH_MP0SW_INT_CTXID 0xC04003 -#define mmMP1_IH_MP1SW_INT_CTXID 0xC04004 -#define mmMP1_IH_DISP_TIMER_ID 0xC04005 -#define mmMP1_FW_DEBUG_CNT0 0xC04006 -#define mmMP1_FW_DEBUG_CNT1 0xC04007 -#define mmMP1_FW_DEBUG_CNT2 0xC04008 -#define mmMP1_FW_DEBUG_CNT3 0xC04009 -#define mmMP1_FW_DEBUG_SIGNAL0 0xC0400A -#define mmMP1_FW_DEBUG_SIGNAL1 0xC0400B -#define mmMP1_DSM_ENABLE 0xC0400C -#define mmMP1_FIRMWARE_FLAGS 0xC0400D -#define mmMP1_MUTEX_0 0xC0400E -#define mmMP1_MUTEX_1 0xC0400F -#define mmMP1_MUTEX_2 0xC04010 -#define mmMP1_MUTEX_3 0xC04011 -#define mmMP1_PUB_SCRATCH0 0xC04012 -#define mmMP1_PUB_SCRATCH1 0xC04013 -#define mmMP1_PUB_SCRATCH2 0xC04014 -#define mmMP1_PUB_SCRATCH3 0xC04015 -#define mmMP1_FW_CHRONO_LO 0xC04016 -#define mmMP1_FW_CHRONO_HI 0xC04017 -#define mmMP1_C2PMSG_0 0xC04140 -#define mmMP1_C2PMSG_1 0xC04141 -#define mmMP1_C2PMSG_2 0xC04142 -#define mmMP1_C2PMSG_3 0xC04143 -#define mmMP1_C2PMSG_4 0xC04144 -#define mmMP1_C2PMSG_5 0xC04145 -#define mmMP1_C2PMSG_6 0xC04146 -#define mmMP1_C2PMSG_7 0xC04147 -#define mmMP1_C2PMSG_8 0xC04148 -#define mmMP1_C2PMSG_9 0xC04149 -#define mmMP1_C2PMSG_10 0xC0414A -#define mmMP1_C2PMSG_11 0xC0414B -#define mmMP1_C2PMSG_12 0xC0414C -#define mmMP1_C2PMSG_13 0xC0414D -#define mmMP1_C2PMSG_14 0xC0414E -#define mmMP1_C2PMSG_15 0xC0414F -#define mmMP1_C2PMSG_16 0xC04150 -#define mmMP1_C2PMSG_17 0xC04151 -#define mmMP1_C2PMSG_18 0xC04152 -#define mmMP1_C2PMSG_19 0xC04153 -#define mmMP1_C2PMSG_20 0xC04154 -#define mmMP1_C2PMSG_21 0xC04155 -#define mmMP1_C2PMSG_22 0xC04156 -#define mmMP1_C2PMSG_23 0xC04157 -#define mmMP1_C2PMSG_24 0xC04158 -#define mmMP1_C2PMSG_25 0xC04159 -#define mmMP1_C2PMSG_26 0xC0415A -#define mmMP1_C2PMSG_27 0xC0415B -#define mmMP1_C2PMSG_28 0xC0415C -#define mmMP1_C2PMSG_29 0xC0415D -#define mmMP1_C2PMSG_30 0xC0415E -#define mmMP1_C2PMSG_31 0xC0415F -#define mmMP1_C2PMSG_32 0xC04260 -#define mmMP1_C2PMSG_33 0xC04261 -#define mmMP1_C2PMSG_34 0xC04262 -#define mmMP1_C2PMSG_35 0xC04263 -#define mmMP1_C2PMSG_36 0xC04264 -#define mmMP1_C2PMSG_37 0xC04265 -#define mmMP1_C2PMSG_38 0xC04266 -#define mmMP1_C2PMSG_39 0xC04267 -#define mmMP1_C2PMSG_40 0xC04268 -#define mmMP1_C2PMSG_41 0xC04269 -#define mmMP1_C2PMSG_42 0xC0426A -#define mmMP1_C2PMSG_43 0xC0426B -#define mmMP1_C2PMSG_44 0xC0426C -#define mmMP1_C2PMSG_45 0xC0426D -#define mmMP1_C2PMSG_46 0xC0426E -#define mmMP1_C2PMSG_47 0xC0426F -#define mmMP1_C2PMSG_48 0xC04270 -#define mmMP1_C2PMSG_49 0xC04271 -#define mmMP1_C2PMSG_50 0xC04272 -#define mmMP1_C2PMSG_51 0xC04273 -#define mmMP1_C2PMSG_52 0xC04274 -#define mmMP1_C2PMSG_53 0xC04275 -#define mmMP1_C2PMSG_54 0xC04276 -#define mmMP1_C2PMSG_55 0xC04277 -#define mmMP1_C2PMSG_56 0xC04278 -#define mmMP1_C2PMSG_57 0xC04279 -#define mmMP1_C2PMSG_58 0xC0427A -#define mmMP1_C2PMSG_59 0xC0427B -#define mmMP1_C2PMSG_60 0xC0427C -#define mmMP1_C2PMSG_61 0xC0427D -#define mmMP1_C2PMSG_62 0xC0427E -#define mmMP1_C2PMSG_63 0xC0427F -#define mmMP1_C2PMSG_64 0xC04280 -#define mmMP1_C2PMSG_65 0xC04281 -#define mmMP1_C2PMSG_66 0xC04282 -#define mmMP1_C2PMSG_67 0xC04283 -#define mmMP1_C2PMSG_68 0xC04284 -#define mmMP1_C2PMSG_69 0xC04285 -#define mmMP1_C2PMSG_70 0xC04286 -#define mmMP1_C2PMSG_71 0xC04287 -#define mmMP1_C2PMSG_72 0xC04288 -#define mmMP1_C2PMSG_73 0xC04289 -#define mmMP1_C2PMSG_74 0xC0428A -#define mmMP1_C2PMSG_75 0xC0428B -#define mmMP1_C2PMSG_76 0xC0428C -#define mmMP1_C2PMSG_77 0xC0428D -#define mmMP1_C2PMSG_78 0xC0428E -#define mmMP1_C2PMSG_79 0xC0428F -#define mmMP1_C2PMSG_80 0xC04290 -#define mmMP1_C2PMSG_81 0xC04291 -#define mmMP1_C2PMSG_82 0xC04292 -#define mmMP1_C2PMSG_83 0xC04293 -#define mmMP1_C2PMSG_84 0xC04294 -#define mmMP1_C2PMSG_85 0xC04295 -#define mmMP1_C2PMSG_86 0xC04296 -#define mmMP1_C2PMSG_87 0xC04297 -#define mmMP1_C2PMSG_88 0xC04298 -#define mmMP1_C2PMSG_89 0xC04299 -#define mmMP1_C2PMSG_90 0xC0429A -#define mmMP1_C2PMSG_91 0xC0429B -#define mmMP1_C2PMSG_92 0xC0429C -#define mmMP1_C2PMSG_93 0xC0429D -#define mmMP1_C2PMSG_94 0xC0429E -#define mmMP1_C2PMSG_95 0xC0429F -#define mmMP1_P2CMSG_0 0xC041A0 -#define mmMP1_P2CMSG_1 0xC041A1 -#define mmMP1_P2CMSG_2 0xC041A2 -#define mmMP1_P2CMSG_3 0xC041A3 -#define mmMP1_P2CMSG_INTEN 0xC041A4 -#define mmMP1_P2CMSG_INTSTS 0xC041A5 -#define mmMP1_P2SMSG_0 0xC041C0 -#define mmMP1_P2SMSG_1 0xC041C1 -#define mmMP1_P2SMSG_2 0xC041C2 -#define mmMP1_P2SMSG_3 0xC041C3 -#define mmMP1_P2SMSG_INTSTS 0xC041C4 -#define mmMP1_S2PMSG_0 0xC041C5 -#define mmMP1_PUB_RSMU_HCID 0xC041E0 -#define mmMP1_PUB_RSMU_SIID 0xC041E1 -#define mmMP1_SRBMTMR_0_CTRL0 0xC04200 -#define mmMP1_SRBMTMR_1_CTRL0 0xC04206 -#define mmMP1_SRBMTMR_0_CTRL1 0xC04201 -#define mmMP1_SRBMTMR_1_CTRL1 0xC04207 -#define mmMP1_SRBMTMR_0_CMP_AUTOINC 0xC04202 -#define mmMP1_SRBMTMR_1_CMP_AUTOINC 0xC04208 -#define mmMP1_SRBMTMR_0_INTEN 0xC04203 -#define mmMP1_SRBMTMR_1_INTEN 0xC04209 -#define mmMP1_SRBMTMR_OCMP_0_0 0xC04204 -#define mmMP1_SRBMTMR_OCMP_1_0 0xC0420A -#define mmMP1_SRBMTMR_0_CNT 0xC04205 -#define mmMP1_SRBMTMR_1_CNT 0xC0420B -#define mmMP1_ACP2MP_RESP 0xC04240 -#define mmMP1_DC2MP_RESP 0xC04241 -#define mmMP1_UVD2MP_RESP 0xC04242 -#define mmMP1_VCE2MP_RESP 0xC04243 -#define mmMP1_RLC2MP_RESP 0xC04244 -#define mmMP1_IH_MP0SW_INT 0xC042C0 -#define mmMP1_IH_MP1SW_INT 0xC042C1 -#define mmMP1_IH_SW_INT_CTRL 0xC042C2 -#define mmMP1_IH_DISPTMR0_INT_CTRL 0xC042C3 -#define mmMP1_IH_DISPTMR1_INT_CTRL 0xC042C4 -#define mmMP1_FPS_CNT 0xC042C5 -#define mmMP1_REVID 0xC80000 -#define mmMP1_RSMU_HCID 0xC80001 -#define mmMP1_RSMU_SIID 0xC80002 -#define mmMP1_RAM_REPAIR_DONE 0xC80003 -#define mmMP1_RAM_REPAIR_RESULT 0xC80004 -#define mmMP1_FUSE_HARVESTING 0xC80005 -#define mmMP1_FUSE_RMBITS 0xC80006 -#define mmMP1_SMS_CFG 0xC80007 -#define mmMP1_FUSE_SMS_0 0xC80008 -#define mmMP1_FUSE_SMS_1 0xC80009 -#define mmMP1_FUSE_SMS_2 0xC8000A -#define mmMP1_FUSE_SMS_3 0xC8000B -#define mmMP1_FUSE_SMS_4 0xC8000C -#define mmMP1_FUSE_SMS_5 0xC8000D -#define mmMP1_FUSE_SMS_6 0xC8000E -#define mmMP1_FUSE_SMS_7 0xC8000F -#define mmMP1_ACC_VIO_INTSTS 0xC80010 -#define mmMP1_TDR_MISC0_STATUS 0xC80011 -#define mmMP1_EVCNTCTL 0xC80012 -#define mmMP1_EVCNTSEL 0xC80013 -#define mmMP1_EVCNT0 0xC80014 -#define mmMP1_EVCNT1 0xC80015 -#define mmMP1_EVCNTHI 0xC80016 -#define mmMP1_J2P_MBOX0 0xC80017 -#define mmMP1_J2P_MBOX1 0xC80018 -#define mmMP1_J2P_ATTR 0xC80019 -#define mmMP1_CRU_ACC_VIO_INTSTS 0xC8001A -#define mmMP1_ACC_VIOL_LOG0 0xC8001B -#define mmMP1_ACC_VIOL_LOG1 0xC8001C -#define mmMP1_SEC_SCRATCH0 0xC8001D -#define mmMP1_SEC_SCRATCH1 0xC8001E -#define mmMP1_SEC_SCRATCH2 0xC8001F -#define mmMP1_SEC_SCRATCH3 0xC80020 -#define mmMP1_STICKY 0xC80021 -#define mmMP1_CRU_MISC_CTRL 0xC80022 -#define mmMP1_SOFT_RESET_CTRL 0xC80023 -#define mmMP1_NS_PROT_FAULT_STATUS_0 0xC80024 -#define mmMP1_FW_MISC_CTRL 0xC80025 -#define mmMP1_AEB_STATUS_0 0xC80026 -#define mmMP1_PIC0_MASK_0 0xC80080 -#define mmMP1_PIC0_LEVEL_0 0xC80081 -#define mmMP1_PIC0_EDGE_0 0xC80082 -#define mmMP1_PIC0_PRIORITY_0 0xC80083 -#define mmMP1_PIC0_PRIORITY_1 0xC80084 -#define mmMP1_PIC0_STATUS_0 0xC80085 -#define mmMP1_PIC0_INTR 0xC80086 -#define mmMP1_PIC0_ID 0xC80087 -#define mmMP1_PIC1_MASK_0 0xC800C0 -#define mmMP1_PIC1_MASK_1 0xC800C1 -#define mmMP1_PIC1_MASK_2 0xC800C2 -#define mmMP1_PIC1_MASK_3 0xC800C3 -#define mmMP1_PIC1_LEVEL_0 0xC800C4 -#define mmMP1_PIC1_LEVEL_1 0xC800C5 -#define mmMP1_PIC1_LEVEL_2 0xC800C6 -#define mmMP1_PIC1_LEVEL_3 0xC800C7 -#define mmMP1_PIC1_EDGE_0 0xC800C8 -#define mmMP1_PIC1_EDGE_1 0xC800C9 -#define mmMP1_PIC1_EDGE_2 0xC800CA -#define mmMP1_PIC1_EDGE_3 0xC800CB -#define mmMP1_PIC1_PRIORITY_0 0xC800CC -#define mmMP1_PIC1_PRIORITY_1 0xC800CD -#define mmMP1_PIC1_PRIORITY_2 0xC800CE -#define mmMP1_PIC1_PRIORITY_3 0xC800CF -#define mmMP1_PIC1_PRIORITY_4 0xC800D0 -#define mmMP1_PIC1_PRIORITY_5 0xC800D1 -#define mmMP1_PIC1_PRIORITY_6 0xC800D2 -#define mmMP1_PIC1_PRIORITY_7 0xC800D3 -#define mmMP1_PIC1_PRIORITY_8 0xC800D4 -#define mmMP1_PIC1_PRIORITY_9 0xC800D5 -#define mmMP1_PIC1_PRIORITY_10 0xC800D6 -#define mmMP1_PIC1_PRIORITY_11 0xC800D7 -#define mmMP1_PIC1_PRIORITY_12 0xC800D8 -#define mmMP1_PIC1_PRIORITY_13 0xC800D9 -#define mmMP1_PIC1_PRIORITY_14 0xC800DA -#define mmMP1_PIC1_PRIORITY_15 0xC800DB -#define mmMP1_PIC1_PRIORITY_16 0xC800DC -#define mmMP1_PIC1_PRIORITY_17 0xC800DD -#define mmMP1_PIC1_PRIORITY_18 0xC800DE -#define mmMP1_PIC1_PRIORITY_19 0xC800DF -#define mmMP1_PIC1_PRIORITY_20 0xC800E0 -#define mmMP1_PIC1_PRIORITY_21 0xC800E1 -#define mmMP1_PIC1_PRIORITY_22 0xC800E2 -#define mmMP1_PIC1_PRIORITY_23 0xC800E3 -#define mmMP1_PIC1_PRIORITY_24 0xC800E4 -#define mmMP1_PIC1_PRIORITY_25 0xC800E5 -#define mmMP1_PIC1_PRIORITY_26 0xC800E6 -#define mmMP1_PIC1_PRIORITY_27 0xC800E7 -#define mmMP1_PIC1_PRIORITY_28 0xC800E8 -#define mmMP1_PIC1_PRIORITY_29 0xC800E9 -#define mmMP1_PIC1_PRIORITY_30 0xC800EA -#define mmMP1_PIC1_PRIORITY_31 0xC800EB -#define mmMP1_PIC1_STATUS_0 0xC800EC -#define mmMP1_PIC1_STATUS_1 0xC800ED -#define mmMP1_PIC1_STATUS_2 0xC800EE -#define mmMP1_PIC1_STATUS_3 0xC800EF -#define mmMP1_PIC1_INTR 0xC800F0 -#define mmMP1_PIC1_ID 0xC800F1 -#define mmMP1_TIMER_0_CTRL0 0xC80100 -#define mmMP1_TIMER_1_CTRL0 0xC80109 -#define mmMP1_TIMER_2_CTRL0 0xC80112 -#define mmMP1_TIMER_3_CTRL0 0xC8011B -#define mmMP1_TIMER_4_CTRL0 0xC80124 -#define mmMP1_TIMER_5_CTRL0 0xC8012D -#define mmMP1_TIMER_6_CTRL0 0xC80136 -#define mmMP1_TIMER_7_CTRL0 0xC8013F -#define mmMP1_TIMER_0_CTRL1 0xC80101 -#define mmMP1_TIMER_1_CTRL1 0xC8010A -#define mmMP1_TIMER_2_CTRL1 0xC80113 -#define mmMP1_TIMER_3_CTRL1 0xC8011C -#define mmMP1_TIMER_4_CTRL1 0xC80125 -#define mmMP1_TIMER_5_CTRL1 0xC8012E -#define mmMP1_TIMER_6_CTRL1 0xC80137 -#define mmMP1_TIMER_7_CTRL1 0xC80140 -#define mmMP1_TIMER_0_CMP_AUTOINC 0xC80102 -#define mmMP1_TIMER_1_CMP_AUTOINC 0xC8010B -#define mmMP1_TIMER_2_CMP_AUTOINC 0xC80114 -#define mmMP1_TIMER_3_CMP_AUTOINC 0xC8011D -#define mmMP1_TIMER_4_CMP_AUTOINC 0xC80126 -#define mmMP1_TIMER_5_CMP_AUTOINC 0xC8012F -#define mmMP1_TIMER_6_CMP_AUTOINC 0xC80138 -#define mmMP1_TIMER_7_CMP_AUTOINC 0xC80141 -#define mmMP1_TIMER_0_INTEN 0xC80103 -#define mmMP1_TIMER_1_INTEN 0xC8010C -#define mmMP1_TIMER_2_INTEN 0xC80115 -#define mmMP1_TIMER_3_INTEN 0xC8011E -#define mmMP1_TIMER_4_INTEN 0xC80127 -#define mmMP1_TIMER_5_INTEN 0xC80130 -#define mmMP1_TIMER_6_INTEN 0xC80139 -#define mmMP1_TIMER_7_INTEN 0xC80142 -#define mmMP1_TIMER_OCMP_0_0 0xC80104 -#define mmMP1_TIMER_OCMP_1_0 0xC8010D -#define mmMP1_TIMER_OCMP_2_0 0xC80116 -#define mmMP1_TIMER_OCMP_3_0 0xC8011F -#define mmMP1_TIMER_OCMP_4_0 0xC80128 -#define mmMP1_TIMER_OCMP_5_0 0xC80131 -#define mmMP1_TIMER_OCMP_6_0 0xC8013A -#define mmMP1_TIMER_OCMP_7_0 0xC80143 -#define mmMP1_TIMER_OCMP_0_1 0xC80105 -#define mmMP1_TIMER_OCMP_1_1 0xC8010E -#define mmMP1_TIMER_OCMP_2_1 0xC80117 -#define mmMP1_TIMER_OCMP_3_1 0xC80120 -#define mmMP1_TIMER_OCMP_4_1 0xC80129 -#define mmMP1_TIMER_OCMP_5_1 0xC80132 -#define mmMP1_TIMER_OCMP_6_1 0xC8013B -#define mmMP1_TIMER_OCMP_7_1 0xC80144 -#define mmMP1_TIMER_OCMP_0_2 0xC80106 -#define mmMP1_TIMER_OCMP_1_2 0xC8010F -#define mmMP1_TIMER_OCMP_2_2 0xC80118 -#define mmMP1_TIMER_OCMP_3_2 0xC80121 -#define mmMP1_TIMER_OCMP_4_2 0xC8012A -#define mmMP1_TIMER_OCMP_5_2 0xC80133 -#define mmMP1_TIMER_OCMP_6_2 0xC8013C -#define mmMP1_TIMER_OCMP_7_2 0xC80145 -#define mmMP1_TIMER_OCMP_0_3 0xC80107 -#define mmMP1_TIMER_OCMP_1_3 0xC80110 -#define mmMP1_TIMER_OCMP_2_3 0xC80119 -#define mmMP1_TIMER_OCMP_3_3 0xC80122 -#define mmMP1_TIMER_OCMP_4_3 0xC8012B -#define mmMP1_TIMER_OCMP_5_3 0xC80134 -#define mmMP1_TIMER_OCMP_6_3 0xC8013D -#define mmMP1_TIMER_OCMP_7_3 0xC80146 -#define mmMP1_TIMER_0_CNT 0xC80108 -#define mmMP1_TIMER_1_CNT 0xC80111 -#define mmMP1_TIMER_2_CNT 0xC8011A -#define mmMP1_TIMER_3_CNT 0xC80123 -#define mmMP1_TIMER_4_CNT 0xC8012C -#define mmMP1_TIMER_5_CNT 0xC80135 -#define mmMP1_TIMER_6_CNT 0xC8013E -#define mmMP1_TIMER_7_CNT 0xC80147 -#define mmMP1_C2PMSG_ATTR_0 0xC80240 -#define mmMP1_C2PMSG_ATTR_1 0xC80241 -#define mmMP1_C2PMSG_ATTR_2 0xC80242 -#define mmMP1_C2PMSG_ATTR_3 0xC80243 -#define mmMP1_C2PMSG_ATTR_4 0xC80244 -#define mmMP1_C2PMSG_ATTR_5 0xC80245 -#define mmMP1_P2CMSG_ATTR 0xC80246 -#define mmMP1_S2PMSG_ATTR 0xC80247 -#define mmMP1_P2SMSG_ATTR 0xC80248 - - -// Registers from MP1_CRU_SMN block - -#define mmMP1_SMN_SRBMTMR_0_CTRL0 0x16200 -#define mmMP1_SMN_SRBMTMR_1_CTRL0 0x16206 -#define mmMP1_SMN_SRBMTMR_0_CTRL1 0x16201 -#define mmMP1_SMN_SRBMTMR_1_CTRL1 0x16207 -#define mmMP1_SMN_SRBMTMR_0_CMP_AUTOINC 0x16202 -#define mmMP1_SMN_SRBMTMR_1_CMP_AUTOINC 0x16208 -#define mmMP1_SMN_SRBMTMR_0_INTEN 0x16203 -#define mmMP1_SMN_SRBMTMR_1_INTEN 0x16209 -#define mmMP1_SMN_SRBMTMR_OCMP_0_0 0x16204 -#define mmMP1_SMN_SRBMTMR_OCMP_1_0 0x1620A -#define mmMP1_SMN_SRBMTMR_0_CNT 0x16205 -#define mmMP1_SMN_SRBMTMR_1_CNT 0x1620B -#define mmMP1_SMN_ACP2MP_RESP 0x16240 -#define mmMP1_SMN_DC2MP_RESP 0x16241 -#define mmMP1_SMN_UVD2MP_RESP 0x16242 -#define mmMP1_SMN_VCE2MP_RESP 0x16243 -#define mmMP1_SMN_RLC2MP_RESP 0x16244 -#define mmMP1_SMN_C2PMSG_32 0x16260 -#define mmMP1_SMN_C2PMSG_33 0x16261 -#define mmMP1_SMN_C2PMSG_34 0x16262 -#define mmMP1_SMN_C2PMSG_35 0x16263 -#define mmMP1_SMN_C2PMSG_36 0x16264 -#define mmMP1_SMN_C2PMSG_37 0x16265 -#define mmMP1_SMN_C2PMSG_38 0x16266 -#define mmMP1_SMN_C2PMSG_39 0x16267 -#define mmMP1_SMN_C2PMSG_40 0x16268 -#define mmMP1_SMN_C2PMSG_41 0x16269 -#define mmMP1_SMN_C2PMSG_42 0x1626A -#define mmMP1_SMN_C2PMSG_43 0x1626B -#define mmMP1_SMN_C2PMSG_44 0x1626C -#define mmMP1_SMN_C2PMSG_45 0x1626D -#define mmMP1_SMN_C2PMSG_46 0x1626E -#define mmMP1_SMN_C2PMSG_47 0x1626F -#define mmMP1_SMN_C2PMSG_48 0x16270 -#define mmMP1_SMN_C2PMSG_49 0x16271 -#define mmMP1_SMN_C2PMSG_50 0x16272 -#define mmMP1_SMN_C2PMSG_51 0x16273 -#define mmMP1_SMN_C2PMSG_52 0x16274 -#define mmMP1_SMN_C2PMSG_53 0x16275 -#define mmMP1_SMN_C2PMSG_54 0x16276 -#define mmMP1_SMN_C2PMSG_55 0x16277 -#define mmMP1_SMN_C2PMSG_56 0x16278 -#define mmMP1_SMN_C2PMSG_57 0x16279 -#define mmMP1_SMN_C2PMSG_58 0x1627A -#define mmMP1_SMN_C2PMSG_59 0x1627B -#define mmMP1_SMN_C2PMSG_60 0x1627C -#define mmMP1_SMN_C2PMSG_61 0x1627D -#define mmMP1_SMN_C2PMSG_62 0x1627E -#define mmMP1_SMN_C2PMSG_63 0x1627F -#define mmMP1_SMN_C2PMSG_64 0x16280 -#define mmMP1_SMN_C2PMSG_65 0x16281 -#define mmMP1_SMN_C2PMSG_66 0x16282 -#define mmMP1_SMN_C2PMSG_67 0x16283 -#define mmMP1_SMN_C2PMSG_68 0x16284 -#define mmMP1_SMN_C2PMSG_69 0x16285 -#define mmMP1_SMN_C2PMSG_70 0x16286 -#define mmMP1_SMN_C2PMSG_71 0x16287 -#define mmMP1_SMN_C2PMSG_72 0x16288 -#define mmMP1_SMN_C2PMSG_73 0x16289 -#define mmMP1_SMN_C2PMSG_74 0x1628A -#define mmMP1_SMN_C2PMSG_75 0x1628B -#define mmMP1_SMN_C2PMSG_76 0x1628C -#define mmMP1_SMN_C2PMSG_77 0x1628D -#define mmMP1_SMN_C2PMSG_78 0x1628E -#define mmMP1_SMN_C2PMSG_79 0x1628F -#define mmMP1_SMN_C2PMSG_80 0x16290 -#define mmMP1_SMN_C2PMSG_81 0x16291 -#define mmMP1_SMN_C2PMSG_82 0x16292 -#define mmMP1_SMN_C2PMSG_83 0x16293 -#define mmMP1_SMN_C2PMSG_84 0x16294 -#define mmMP1_SMN_C2PMSG_85 0x16295 -#define mmMP1_SMN_C2PMSG_86 0x16296 -#define mmMP1_SMN_C2PMSG_87 0x16297 -#define mmMP1_SMN_C2PMSG_88 0x16298 -#define mmMP1_SMN_C2PMSG_89 0x16299 -#define mmMP1_SMN_C2PMSG_90 0x1629A -#define mmMP1_SMN_C2PMSG_91 0x1629B -#define mmMP1_SMN_C2PMSG_92 0x1629C -#define mmMP1_SMN_C2PMSG_93 0x1629D -#define mmMP1_SMN_C2PMSG_94 0x1629E -#define mmMP1_SMN_C2PMSG_95 0x1629F -#define mmMP1_SMN_IH_MP0SW_INT 0x162C0 -#define mmMP1_SMN_IH_MP1SW_INT 0x162C1 -#define mmMP1_SMN_IH_SW_INT_CTRL 0x162C2 -#define mmMP1_SMN_IH_DISPTMR0_INT_CTRL 0x162C3 -#define mmMP1_SMN_IH_DISPTMR1_INT_CTRL 0x162C4 -#define mmMP1_SMN_FPS_CNT 0x162C5 - - -// Registers from MP1_CRU_RSMU block - -#define mmMP1_RSMU_PUB_RSMU_HCID 0x12020 -#define mmMP1_RSMU_PUB_RSMU_SIID 0x12021 - - -// Registers from MP1_MMU block - -#define mmMP1_PMI_0_START 0xC84000 -#define mmMP1_PMI_0_FIFO 0xC84001 -#define mmMP1_PMI_0_STATUS 0xC84002 -#define mmMP1_PMI_0_READ_POINTER 0xC84003 -#define mmMP1_PMI_0_WRITE_POINTER 0xC84004 -#define mmMP1_PMI_1_START 0xC84005 -#define mmMP1_PMI_1_FIFO 0xC84006 -#define mmMP1_PMI_1_STATUS 0xC84007 -#define mmMP1_PMI_1_READ_POINTER 0xC84008 -#define mmMP1_PMI_1_WRITE_POINTER 0xC84009 -#define mmMP1_PMI_2_START 0xC8400A -#define mmMP1_PMI_2_FIFO 0xC8400B -#define mmMP1_PMI_2_STATUS 0xC8400C -#define mmMP1_PMI_2_READ_POINTER 0xC8400D -#define mmMP1_PMI_2_WRITE_POINTER 0xC8400E -#define mmMP1_PMI_OUT_CONFIG 0xC8400F -#define mmMP1_PMI_RELOAD 0xC84010 -#define mmMP1_PMI_INTERRUPT_CONTROL 0xC84011 -#define mmMP1_MMU_SRAM_ACC_VIOLATION_LOG_ADDR 0xC84012 -#define mmMP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS 0xC84013 -#define mmMP1_MMU_MISC_CNTL 0xC84014 -#define mmMP1_MMU_ACCESS_ERR_LOG 0xC84015 -#define mmMP1_MMU_SRAM_UNSECURE_BAR 0xC84016 -#define mmMP1_MMU_SCRATCH_0 0xC84017 -#define mmMP1_MMU_SCRATCH_1 0xC84018 -#define mmMP1_MMU_SCRATCH_2 0xC84019 -#define mmMP1_MMU_SCRATCH_3 0xC8401A -#define mmMP1_MMU_SCRATCH_4 0xC8401B -#define mmMP1_MMU_SCRATCH_5 0xC8401C -#define mmMP1_MMU_SCRATCH_6 0xC8401D -#define mmMP1_MMU_SCRATCH_7 0xC8401E -#define mmMP1_MCA_ACCESS_CNTL 0xC0C000 -#define mmMP1_MCA_ACCESS_WR_DATA 0xC0C001 -#define mmMP1_MCA_ACCESS_RD_DATA 0xC0C002 -#define mmMP1_PMI_0 0xC0C003 -#define mmMP1_PMI_1 0xC0C004 -#define mmMP1_PMI_2 0xC0C005 - - -// Registers from MP1_HUBIF block - -#define mmMP1_MMHUB_SOC_TLB0_1 0xC90000 -#define mmMP1_MMHUB_SOC_TLB0_2 0xC90004 -#define mmMP1_MMHUB_SOC_TLB0_3 0xC90008 -#define mmMP1_MMHUB_SOC_TLB0_4 0xC9000C -#define mmMP1_MMHUB_SOC_TLB0_5 0xC90010 -#define mmMP1_MMHUB_SOC_TLB0_6 0xC90014 -#define mmMP1_MMHUB_SOC_TLB0_7 0xC90018 -#define mmMP1_MMHUB_SOC_TLB0_8 0xC9001C -#define mmMP1_MMHUB_SOC_TLB0_9 0xC90020 -#define mmMP1_MMHUB_SOC_TLB0_10 0xC90024 -#define mmMP1_MMHUB_SOC_TLB0_11 0xC90028 -#define mmMP1_MMHUB_SOC_TLB0_12 0xC9002C -#define mmMP1_MMHUB_SOC_TLB0_13 0xC90030 -#define mmMP1_MMHUB_SOC_TLB0_14 0xC90034 -#define mmMP1_MMHUB_SOC_TLB0_15 0xC90038 -#define mmMP1_MMHUB_SOC_TLB0_16 0xC9003C -#define mmMP1_MMHUB_SOC_TLB0_17 0xC90040 -#define mmMP1_MMHUB_SOC_TLB0_18 0xC90044 -#define mmMP1_MMHUB_SOC_TLB0_19 0xC90048 -#define mmMP1_MMHUB_SOC_TLB0_20 0xC9004C -#define mmMP1_MMHUB_SOC_TLB0_21 0xC90050 -#define mmMP1_MMHUB_SOC_TLB0_22 0xC90054 -#define mmMP1_MMHUB_SOC_TLB0_23 0xC90058 -#define mmMP1_MMHUB_SOC_TLB0_24 0xC9005C -#define mmMP1_MMHUB_SOC_TLB0_25 0xC90060 -#define mmMP1_MMHUB_SOC_TLB0_26 0xC90064 -#define mmMP1_MMHUB_SOC_TLB0_27 0xC90068 -#define mmMP1_MMHUB_SOC_TLB0_28 0xC9006C -#define mmMP1_MMHUB_SOC_TLB0_29 0xC90070 -#define mmMP1_MMHUB_SOC_TLB0_30 0xC90074 -#define mmMP1_MMHUB_SOC_TLB0_31 0xC90078 -#define mmMP1_MMHUB_SOC_TLB0_32 0xC9007C -#define mmMP1_MMHUB_SOC_TLB0_33 0xC90080 -#define mmMP1_MMHUB_SOC_TLB0_34 0xC90084 -#define mmMP1_MMHUB_SOC_TLB0_35 0xC90088 -#define mmMP1_MMHUB_SOC_TLB0_36 0xC9008C -#define mmMP1_MMHUB_SOC_TLB0_37 0xC90090 -#define mmMP1_MMHUB_SOC_TLB0_38 0xC90094 -#define mmMP1_MMHUB_SOC_TLB0_39 0xC90098 -#define mmMP1_MMHUB_SOC_TLB0_40 0xC9009C -#define mmMP1_MMHUB_SOC_TLB0_41 0xC900A0 -#define mmMP1_MMHUB_SOC_TLB0_42 0xC900A4 -#define mmMP1_MMHUB_SOC_TLB0_43 0xC900A8 -#define mmMP1_MMHUB_SOC_TLB0_44 0xC900AC -#define mmMP1_MMHUB_SOC_TLB0_45 0xC900B0 -#define mmMP1_MMHUB_SOC_TLB0_46 0xC900B4 -#define mmMP1_MMHUB_SOC_TLB0_47 0xC900B8 -#define mmMP1_MMHUB_SOC_TLB0_48 0xC900BC -#define mmMP1_MMHUB_SOC_TLB0_49 0xC900C0 -#define mmMP1_MMHUB_SOC_TLB0_50 0xC900C4 -#define mmMP1_MMHUB_SOC_TLB0_51 0xC900C8 -#define mmMP1_MMHUB_SOC_TLB0_52 0xC900CC -#define mmMP1_MMHUB_SOC_TLB0_53 0xC900D0 -#define mmMP1_MMHUB_SOC_TLB0_54 0xC900D4 -#define mmMP1_MMHUB_SOC_TLB0_55 0xC900D8 -#define mmMP1_MMHUB_SOC_TLB0_56 0xC900DC -#define mmMP1_MMHUB_SOC_TLB0_57 0xC900E0 -#define mmMP1_MMHUB_SOC_TLB0_58 0xC900E4 -#define mmMP1_MMHUB_SOC_TLB0_59 0xC900E8 -#define mmMP1_MMHUB_SOC_TLB0_60 0xC900EC -#define mmMP1_MMHUB_SOC_TLB0_61 0xC900F0 -#define mmMP1_MMHUB_SOC_TLB0_62 0xC900F4 -#define mmMP1_MMHUB_SOC_TLB1_1 0xC90001 -#define mmMP1_MMHUB_SOC_TLB1_2 0xC90005 -#define mmMP1_MMHUB_SOC_TLB1_3 0xC90009 -#define mmMP1_MMHUB_SOC_TLB1_4 0xC9000D -#define mmMP1_MMHUB_SOC_TLB1_5 0xC90011 -#define mmMP1_MMHUB_SOC_TLB1_6 0xC90015 -#define mmMP1_MMHUB_SOC_TLB1_7 0xC90019 -#define mmMP1_MMHUB_SOC_TLB1_8 0xC9001D -#define mmMP1_MMHUB_SOC_TLB1_9 0xC90021 -#define mmMP1_MMHUB_SOC_TLB1_10 0xC90025 -#define mmMP1_MMHUB_SOC_TLB1_11 0xC90029 -#define mmMP1_MMHUB_SOC_TLB1_12 0xC9002D -#define mmMP1_MMHUB_SOC_TLB1_13 0xC90031 -#define mmMP1_MMHUB_SOC_TLB1_14 0xC90035 -#define mmMP1_MMHUB_SOC_TLB1_15 0xC90039 -#define mmMP1_MMHUB_SOC_TLB1_16 0xC9003D -#define mmMP1_MMHUB_SOC_TLB1_17 0xC90041 -#define mmMP1_MMHUB_SOC_TLB1_18 0xC90045 -#define mmMP1_MMHUB_SOC_TLB1_19 0xC90049 -#define mmMP1_MMHUB_SOC_TLB1_20 0xC9004D -#define mmMP1_MMHUB_SOC_TLB1_21 0xC90051 -#define mmMP1_MMHUB_SOC_TLB1_22 0xC90055 -#define mmMP1_MMHUB_SOC_TLB1_23 0xC90059 -#define mmMP1_MMHUB_SOC_TLB1_24 0xC9005D -#define mmMP1_MMHUB_SOC_TLB1_25 0xC90061 -#define mmMP1_MMHUB_SOC_TLB1_26 0xC90065 -#define mmMP1_MMHUB_SOC_TLB1_27 0xC90069 -#define mmMP1_MMHUB_SOC_TLB1_28 0xC9006D -#define mmMP1_MMHUB_SOC_TLB1_29 0xC90071 -#define mmMP1_MMHUB_SOC_TLB1_30 0xC90075 -#define mmMP1_MMHUB_SOC_TLB1_31 0xC90079 -#define mmMP1_MMHUB_SOC_TLB1_32 0xC9007D -#define mmMP1_MMHUB_SOC_TLB1_33 0xC90081 -#define mmMP1_MMHUB_SOC_TLB1_34 0xC90085 -#define mmMP1_MMHUB_SOC_TLB1_35 0xC90089 -#define mmMP1_MMHUB_SOC_TLB1_36 0xC9008D -#define mmMP1_MMHUB_SOC_TLB1_37 0xC90091 -#define mmMP1_MMHUB_SOC_TLB1_38 0xC90095 -#define mmMP1_MMHUB_SOC_TLB1_39 0xC90099 -#define mmMP1_MMHUB_SOC_TLB1_40 0xC9009D -#define mmMP1_MMHUB_SOC_TLB1_41 0xC900A1 -#define mmMP1_MMHUB_SOC_TLB1_42 0xC900A5 -#define mmMP1_MMHUB_SOC_TLB1_43 0xC900A9 -#define mmMP1_MMHUB_SOC_TLB1_44 0xC900AD -#define mmMP1_MMHUB_SOC_TLB1_45 0xC900B1 -#define mmMP1_MMHUB_SOC_TLB1_46 0xC900B5 -#define mmMP1_MMHUB_SOC_TLB1_47 0xC900B9 -#define mmMP1_MMHUB_SOC_TLB1_48 0xC900BD -#define mmMP1_MMHUB_SOC_TLB1_49 0xC900C1 -#define mmMP1_MMHUB_SOC_TLB1_50 0xC900C5 -#define mmMP1_MMHUB_SOC_TLB1_51 0xC900C9 -#define mmMP1_MMHUB_SOC_TLB1_52 0xC900CD -#define mmMP1_MMHUB_SOC_TLB1_53 0xC900D1 -#define mmMP1_MMHUB_SOC_TLB1_54 0xC900D5 -#define mmMP1_MMHUB_SOC_TLB1_55 0xC900D9 -#define mmMP1_MMHUB_SOC_TLB1_56 0xC900DD -#define mmMP1_MMHUB_SOC_TLB1_57 0xC900E1 -#define mmMP1_MMHUB_SOC_TLB1_58 0xC900E5 -#define mmMP1_MMHUB_SOC_TLB1_59 0xC900E9 -#define mmMP1_MMHUB_SOC_TLB1_60 0xC900ED -#define mmMP1_MMHUB_SOC_TLB1_61 0xC900F1 -#define mmMP1_MMHUB_SOC_TLB1_62 0xC900F5 -#define mmMP1_MMHUB_SOC_TLB2_1 0xC90002 -#define mmMP1_MMHUB_SOC_TLB2_2 0xC90006 -#define mmMP1_MMHUB_SOC_TLB2_3 0xC9000A -#define mmMP1_MMHUB_SOC_TLB2_4 0xC9000E -#define mmMP1_MMHUB_SOC_TLB2_5 0xC90012 -#define mmMP1_MMHUB_SOC_TLB2_6 0xC90016 -#define mmMP1_MMHUB_SOC_TLB2_7 0xC9001A -#define mmMP1_MMHUB_SOC_TLB2_8 0xC9001E -#define mmMP1_MMHUB_SOC_TLB2_9 0xC90022 -#define mmMP1_MMHUB_SOC_TLB2_10 0xC90026 -#define mmMP1_MMHUB_SOC_TLB2_11 0xC9002A -#define mmMP1_MMHUB_SOC_TLB2_12 0xC9002E -#define mmMP1_MMHUB_SOC_TLB2_13 0xC90032 -#define mmMP1_MMHUB_SOC_TLB2_14 0xC90036 -#define mmMP1_MMHUB_SOC_TLB2_15 0xC9003A -#define mmMP1_MMHUB_SOC_TLB2_16 0xC9003E -#define mmMP1_MMHUB_SOC_TLB2_17 0xC90042 -#define mmMP1_MMHUB_SOC_TLB2_18 0xC90046 -#define mmMP1_MMHUB_SOC_TLB2_19 0xC9004A -#define mmMP1_MMHUB_SOC_TLB2_20 0xC9004E -#define mmMP1_MMHUB_SOC_TLB2_21 0xC90052 -#define mmMP1_MMHUB_SOC_TLB2_22 0xC90056 -#define mmMP1_MMHUB_SOC_TLB2_23 0xC9005A -#define mmMP1_MMHUB_SOC_TLB2_24 0xC9005E -#define mmMP1_MMHUB_SOC_TLB2_25 0xC90062 -#define mmMP1_MMHUB_SOC_TLB2_26 0xC90066 -#define mmMP1_MMHUB_SOC_TLB2_27 0xC9006A -#define mmMP1_MMHUB_SOC_TLB2_28 0xC9006E -#define mmMP1_MMHUB_SOC_TLB2_29 0xC90072 -#define mmMP1_MMHUB_SOC_TLB2_30 0xC90076 -#define mmMP1_MMHUB_SOC_TLB2_31 0xC9007A -#define mmMP1_MMHUB_SOC_TLB2_32 0xC9007E -#define mmMP1_MMHUB_SOC_TLB2_33 0xC90082 -#define mmMP1_MMHUB_SOC_TLB2_34 0xC90086 -#define mmMP1_MMHUB_SOC_TLB2_35 0xC9008A -#define mmMP1_MMHUB_SOC_TLB2_36 0xC9008E -#define mmMP1_MMHUB_SOC_TLB2_37 0xC90092 -#define mmMP1_MMHUB_SOC_TLB2_38 0xC90096 -#define mmMP1_MMHUB_SOC_TLB2_39 0xC9009A -#define mmMP1_MMHUB_SOC_TLB2_40 0xC9009E -#define mmMP1_MMHUB_SOC_TLB2_41 0xC900A2 -#define mmMP1_MMHUB_SOC_TLB2_42 0xC900A6 -#define mmMP1_MMHUB_SOC_TLB2_43 0xC900AA -#define mmMP1_MMHUB_SOC_TLB2_44 0xC900AE -#define mmMP1_MMHUB_SOC_TLB2_45 0xC900B2 -#define mmMP1_MMHUB_SOC_TLB2_46 0xC900B6 -#define mmMP1_MMHUB_SOC_TLB2_47 0xC900BA -#define mmMP1_MMHUB_SOC_TLB2_48 0xC900BE -#define mmMP1_MMHUB_SOC_TLB2_49 0xC900C2 -#define mmMP1_MMHUB_SOC_TLB2_50 0xC900C6 -#define mmMP1_MMHUB_SOC_TLB2_51 0xC900CA -#define mmMP1_MMHUB_SOC_TLB2_52 0xC900CE -#define mmMP1_MMHUB_SOC_TLB2_53 0xC900D2 -#define mmMP1_MMHUB_SOC_TLB2_54 0xC900D6 -#define mmMP1_MMHUB_SOC_TLB2_55 0xC900DA -#define mmMP1_MMHUB_SOC_TLB2_56 0xC900DE -#define mmMP1_MMHUB_SOC_TLB2_57 0xC900E2 -#define mmMP1_MMHUB_SOC_TLB2_58 0xC900E6 -#define mmMP1_MMHUB_SOC_TLB2_59 0xC900EA -#define mmMP1_MMHUB_SOC_TLB2_60 0xC900EE -#define mmMP1_MMHUB_SOC_TLB2_61 0xC900F2 -#define mmMP1_MMHUB_SOC_TLB2_62 0xC900F6 -#define mmMP1_MMHUB_SOC_TLB3_1 0xC90003 -#define mmMP1_MMHUB_SOC_TLB3_2 0xC90007 -#define mmMP1_MMHUB_SOC_TLB3_3 0xC9000B -#define mmMP1_MMHUB_SOC_TLB3_4 0xC9000F -#define mmMP1_MMHUB_SOC_TLB3_5 0xC90013 -#define mmMP1_MMHUB_SOC_TLB3_6 0xC90017 -#define mmMP1_MMHUB_SOC_TLB3_7 0xC9001B -#define mmMP1_MMHUB_SOC_TLB3_8 0xC9001F -#define mmMP1_MMHUB_SOC_TLB3_9 0xC90023 -#define mmMP1_MMHUB_SOC_TLB3_10 0xC90027 -#define mmMP1_MMHUB_SOC_TLB3_11 0xC9002B -#define mmMP1_MMHUB_SOC_TLB3_12 0xC9002F -#define mmMP1_MMHUB_SOC_TLB3_13 0xC90033 -#define mmMP1_MMHUB_SOC_TLB3_14 0xC90037 -#define mmMP1_MMHUB_SOC_TLB3_15 0xC9003B -#define mmMP1_MMHUB_SOC_TLB3_16 0xC9003F -#define mmMP1_MMHUB_SOC_TLB3_17 0xC90043 -#define mmMP1_MMHUB_SOC_TLB3_18 0xC90047 -#define mmMP1_MMHUB_SOC_TLB3_19 0xC9004B -#define mmMP1_MMHUB_SOC_TLB3_20 0xC9004F -#define mmMP1_MMHUB_SOC_TLB3_21 0xC90053 -#define mmMP1_MMHUB_SOC_TLB3_22 0xC90057 -#define mmMP1_MMHUB_SOC_TLB3_23 0xC9005B -#define mmMP1_MMHUB_SOC_TLB3_24 0xC9005F -#define mmMP1_MMHUB_SOC_TLB3_25 0xC90063 -#define mmMP1_MMHUB_SOC_TLB3_26 0xC90067 -#define mmMP1_MMHUB_SOC_TLB3_27 0xC9006B -#define mmMP1_MMHUB_SOC_TLB3_28 0xC9006F -#define mmMP1_MMHUB_SOC_TLB3_29 0xC90073 -#define mmMP1_MMHUB_SOC_TLB3_30 0xC90077 -#define mmMP1_MMHUB_SOC_TLB3_31 0xC9007B -#define mmMP1_MMHUB_SOC_TLB3_32 0xC9007F -#define mmMP1_MMHUB_SOC_TLB3_33 0xC90083 -#define mmMP1_MMHUB_SOC_TLB3_34 0xC90087 -#define mmMP1_MMHUB_SOC_TLB3_35 0xC9008B -#define mmMP1_MMHUB_SOC_TLB3_36 0xC9008F -#define mmMP1_MMHUB_SOC_TLB3_37 0xC90093 -#define mmMP1_MMHUB_SOC_TLB3_38 0xC90097 -#define mmMP1_MMHUB_SOC_TLB3_39 0xC9009B -#define mmMP1_MMHUB_SOC_TLB3_40 0xC9009F -#define mmMP1_MMHUB_SOC_TLB3_41 0xC900A3 -#define mmMP1_MMHUB_SOC_TLB3_42 0xC900A7 -#define mmMP1_MMHUB_SOC_TLB3_43 0xC900AB -#define mmMP1_MMHUB_SOC_TLB3_44 0xC900AF -#define mmMP1_MMHUB_SOC_TLB3_45 0xC900B3 -#define mmMP1_MMHUB_SOC_TLB3_46 0xC900B7 -#define mmMP1_MMHUB_SOC_TLB3_47 0xC900BB -#define mmMP1_MMHUB_SOC_TLB3_48 0xC900BF -#define mmMP1_MMHUB_SOC_TLB3_49 0xC900C3 -#define mmMP1_MMHUB_SOC_TLB3_50 0xC900C7 -#define mmMP1_MMHUB_SOC_TLB3_51 0xC900CB -#define mmMP1_MMHUB_SOC_TLB3_52 0xC900CF -#define mmMP1_MMHUB_SOC_TLB3_53 0xC900D3 -#define mmMP1_MMHUB_SOC_TLB3_54 0xC900D7 -#define mmMP1_MMHUB_SOC_TLB3_55 0xC900DB -#define mmMP1_MMHUB_SOC_TLB3_56 0xC900DF -#define mmMP1_MMHUB_SOC_TLB3_57 0xC900E3 -#define mmMP1_MMHUB_SOC_TLB3_58 0xC900E7 -#define mmMP1_MMHUB_SOC_TLB3_59 0xC900EB -#define mmMP1_MMHUB_SOC_TLB3_60 0xC900EF -#define mmMP1_MMHUB_SOC_TLB3_61 0xC900F3 -#define mmMP1_MMHUB_SOC_TLB3_62 0xC900F7 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 0xC900F8 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 0xC900F9 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 0xC900FA -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 0xC900FB -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 0xC900FC -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 0xC900FD -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 0xC900FE -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 0xC900FF -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 0xC90100 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 0xC90101 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 0xC90102 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 0xC90103 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 0xC90104 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 0xC90105 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 0xC90106 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 0xC90107 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 0xC90108 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 0xC90109 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 0xC9010A -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 0xC9010B -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 0xC9010C -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 0xC9010D -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 0xC9010E -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 0xC9010F -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 0xC90110 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 0xC90111 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 0xC90112 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 0xC90113 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 0xC90114 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 0xC90115 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 0xC90116 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 0xC90117 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 0xC90118 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 0xC90119 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 0xC9011A -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 0xC9011B -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 0xC9011C -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 0xC9011D -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 0xC9011E -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 0xC9011F -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 0xC90120 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 0xC90121 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 0xC90122 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 0xC90123 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 0xC90124 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 0xC90125 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 0xC90126 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 0xC90127 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 0xC90128 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 0xC90129 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 0xC9012A -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 0xC9012B -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 0xC9012C -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 0xC9012D -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 0xC9012E -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 0xC9012F -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 0xC90130 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 0xC90131 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 0xC90132 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 0xC90133 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 0xC90134 -#define mmMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 0xC90135 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_1 0xC90136 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_2 0xC90137 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_3 0xC90138 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_4 0xC90139 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_5 0xC9013A -#define mmMP1_MMHUB_TLB_ATTRIBUTE_6 0xC9013B -#define mmMP1_MMHUB_TLB_ATTRIBUTE_7 0xC9013C -#define mmMP1_MMHUB_TLB_ATTRIBUTE_8 0xC9013D -#define mmMP1_MMHUB_TLB_ATTRIBUTE_9 0xC9013E -#define mmMP1_MMHUB_TLB_ATTRIBUTE_10 0xC9013F -#define mmMP1_MMHUB_TLB_ATTRIBUTE_11 0xC90140 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_12 0xC90141 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_13 0xC90142 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_14 0xC90143 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_15 0xC90144 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_16 0xC90145 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_17 0xC90146 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_18 0xC90147 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_19 0xC90148 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_20 0xC90149 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_21 0xC9014A -#define mmMP1_MMHUB_TLB_ATTRIBUTE_22 0xC9014B -#define mmMP1_MMHUB_TLB_ATTRIBUTE_23 0xC9014C -#define mmMP1_MMHUB_TLB_ATTRIBUTE_24 0xC9014D -#define mmMP1_MMHUB_TLB_ATTRIBUTE_25 0xC9014E -#define mmMP1_MMHUB_TLB_ATTRIBUTE_26 0xC9014F -#define mmMP1_MMHUB_TLB_ATTRIBUTE_27 0xC90150 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_28 0xC90151 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_29 0xC90152 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_30 0xC90153 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_31 0xC90154 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_32 0xC90155 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_33 0xC90156 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_34 0xC90157 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_35 0xC90158 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_36 0xC90159 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_37 0xC9015A -#define mmMP1_MMHUB_TLB_ATTRIBUTE_38 0xC9015B -#define mmMP1_MMHUB_TLB_ATTRIBUTE_39 0xC9015C -#define mmMP1_MMHUB_TLB_ATTRIBUTE_40 0xC9015D -#define mmMP1_MMHUB_TLB_ATTRIBUTE_41 0xC9015E -#define mmMP1_MMHUB_TLB_ATTRIBUTE_42 0xC9015F -#define mmMP1_MMHUB_TLB_ATTRIBUTE_43 0xC90160 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_44 0xC90161 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_45 0xC90162 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_46 0xC90163 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_47 0xC90164 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_48 0xC90165 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_49 0xC90166 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_50 0xC90167 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_51 0xC90168 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_52 0xC90169 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_53 0xC9016A -#define mmMP1_MMHUB_TLB_ATTRIBUTE_54 0xC9016B -#define mmMP1_MMHUB_TLB_ATTRIBUTE_55 0xC9016C -#define mmMP1_MMHUB_TLB_ATTRIBUTE_56 0xC9016D -#define mmMP1_MMHUB_TLB_ATTRIBUTE_57 0xC9016E -#define mmMP1_MMHUB_TLB_ATTRIBUTE_58 0xC9016F -#define mmMP1_MMHUB_TLB_ATTRIBUTE_59 0xC90170 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_60 0xC90171 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_61 0xC90172 -#define mmMP1_MMHUB_TLB_ATTRIBUTE_62 0xC90173 -#define mmMP1_MMHUB_INT_STATUS 0xC90174 -#define mmMP1_MMHUB_WR_INT_ADDR 0xC90175 -#define mmMP1_MMHUB_WR_INT_OTHER 0xC90176 -#define mmMP1_MMHUB_RD_INT_ADDR 0xC90177 -#define mmMP1_MMHUB_RD_INT_OTHER 0xC90178 -#define mmMP1_MMHUB_REG_INT_ADDR 0xC90179 -#define mmMP1_MMHUB_REG_INT_OTHER 0xC9017A -#define mmMP1_MMHUB_AXCACHE_CFG 0xC9017B -#define mmMP1_MMHUB_DS_OVERRIDE 0xC9017C -#define mmMP1_MMHUB_OUTSTANDING 0xC9017D -#define mmMP1_SYSHUB_SOC_TLB0_1 0xC8C000 -#define mmMP1_SYSHUB_SOC_TLB0_2 0xC8C004 -#define mmMP1_SYSHUB_SOC_TLB0_3 0xC8C008 -#define mmMP1_SYSHUB_SOC_TLB0_4 0xC8C00C -#define mmMP1_SYSHUB_SOC_TLB0_5 0xC8C010 -#define mmMP1_SYSHUB_SOC_TLB0_6 0xC8C014 -#define mmMP1_SYSHUB_SOC_TLB0_7 0xC8C018 -#define mmMP1_SYSHUB_SOC_TLB0_8 0xC8C01C -#define mmMP1_SYSHUB_SOC_TLB0_9 0xC8C020 -#define mmMP1_SYSHUB_SOC_TLB0_10 0xC8C024 -#define mmMP1_SYSHUB_SOC_TLB0_11 0xC8C028 -#define mmMP1_SYSHUB_SOC_TLB0_12 0xC8C02C -#define mmMP1_SYSHUB_SOC_TLB0_13 0xC8C030 -#define mmMP1_SYSHUB_SOC_TLB0_14 0xC8C034 -#define mmMP1_SYSHUB_SOC_TLB0_15 0xC8C038 -#define mmMP1_SYSHUB_SOC_TLB0_16 0xC8C03C -#define mmMP1_SYSHUB_SOC_TLB0_17 0xC8C040 -#define mmMP1_SYSHUB_SOC_TLB0_18 0xC8C044 -#define mmMP1_SYSHUB_SOC_TLB0_19 0xC8C048 -#define mmMP1_SYSHUB_SOC_TLB0_20 0xC8C04C -#define mmMP1_SYSHUB_SOC_TLB0_21 0xC8C050 -#define mmMP1_SYSHUB_SOC_TLB0_22 0xC8C054 -#define mmMP1_SYSHUB_SOC_TLB0_23 0xC8C058 -#define mmMP1_SYSHUB_SOC_TLB0_24 0xC8C05C -#define mmMP1_SYSHUB_SOC_TLB0_25 0xC8C060 -#define mmMP1_SYSHUB_SOC_TLB0_26 0xC8C064 -#define mmMP1_SYSHUB_SOC_TLB0_27 0xC8C068 -#define mmMP1_SYSHUB_SOC_TLB0_28 0xC8C06C -#define mmMP1_SYSHUB_SOC_TLB0_29 0xC8C070 -#define mmMP1_SYSHUB_SOC_TLB0_30 0xC8C074 -#define mmMP1_SYSHUB_SOC_TLB0_31 0xC8C078 -#define mmMP1_SYSHUB_SOC_TLB0_32 0xC8C07C -#define mmMP1_SYSHUB_SOC_TLB0_33 0xC8C080 -#define mmMP1_SYSHUB_SOC_TLB0_34 0xC8C084 -#define mmMP1_SYSHUB_SOC_TLB0_35 0xC8C088 -#define mmMP1_SYSHUB_SOC_TLB0_36 0xC8C08C -#define mmMP1_SYSHUB_SOC_TLB0_37 0xC8C090 -#define mmMP1_SYSHUB_SOC_TLB0_38 0xC8C094 -#define mmMP1_SYSHUB_SOC_TLB0_39 0xC8C098 -#define mmMP1_SYSHUB_SOC_TLB0_40 0xC8C09C -#define mmMP1_SYSHUB_SOC_TLB0_41 0xC8C0A0 -#define mmMP1_SYSHUB_SOC_TLB0_42 0xC8C0A4 -#define mmMP1_SYSHUB_SOC_TLB0_43 0xC8C0A8 -#define mmMP1_SYSHUB_SOC_TLB0_44 0xC8C0AC -#define mmMP1_SYSHUB_SOC_TLB0_45 0xC8C0B0 -#define mmMP1_SYSHUB_SOC_TLB0_46 0xC8C0B4 -#define mmMP1_SYSHUB_SOC_TLB0_47 0xC8C0B8 -#define mmMP1_SYSHUB_SOC_TLB0_48 0xC8C0BC -#define mmMP1_SYSHUB_SOC_TLB0_49 0xC8C0C0 -#define mmMP1_SYSHUB_SOC_TLB0_50 0xC8C0C4 -#define mmMP1_SYSHUB_SOC_TLB0_51 0xC8C0C8 -#define mmMP1_SYSHUB_SOC_TLB0_52 0xC8C0CC -#define mmMP1_SYSHUB_SOC_TLB0_53 0xC8C0D0 -#define mmMP1_SYSHUB_SOC_TLB0_54 0xC8C0D4 -#define mmMP1_SYSHUB_SOC_TLB0_55 0xC8C0D8 -#define mmMP1_SYSHUB_SOC_TLB0_56 0xC8C0DC -#define mmMP1_SYSHUB_SOC_TLB0_57 0xC8C0E0 -#define mmMP1_SYSHUB_SOC_TLB0_58 0xC8C0E4 -#define mmMP1_SYSHUB_SOC_TLB0_59 0xC8C0E8 -#define mmMP1_SYSHUB_SOC_TLB0_60 0xC8C0EC -#define mmMP1_SYSHUB_SOC_TLB0_61 0xC8C0F0 -#define mmMP1_SYSHUB_SOC_TLB0_62 0xC8C0F4 -#define mmMP1_SYSHUB_SOC_TLB1_1 0xC8C001 -#define mmMP1_SYSHUB_SOC_TLB1_2 0xC8C005 -#define mmMP1_SYSHUB_SOC_TLB1_3 0xC8C009 -#define mmMP1_SYSHUB_SOC_TLB1_4 0xC8C00D -#define mmMP1_SYSHUB_SOC_TLB1_5 0xC8C011 -#define mmMP1_SYSHUB_SOC_TLB1_6 0xC8C015 -#define mmMP1_SYSHUB_SOC_TLB1_7 0xC8C019 -#define mmMP1_SYSHUB_SOC_TLB1_8 0xC8C01D -#define mmMP1_SYSHUB_SOC_TLB1_9 0xC8C021 -#define mmMP1_SYSHUB_SOC_TLB1_10 0xC8C025 -#define mmMP1_SYSHUB_SOC_TLB1_11 0xC8C029 -#define mmMP1_SYSHUB_SOC_TLB1_12 0xC8C02D -#define mmMP1_SYSHUB_SOC_TLB1_13 0xC8C031 -#define mmMP1_SYSHUB_SOC_TLB1_14 0xC8C035 -#define mmMP1_SYSHUB_SOC_TLB1_15 0xC8C039 -#define mmMP1_SYSHUB_SOC_TLB1_16 0xC8C03D -#define mmMP1_SYSHUB_SOC_TLB1_17 0xC8C041 -#define mmMP1_SYSHUB_SOC_TLB1_18 0xC8C045 -#define mmMP1_SYSHUB_SOC_TLB1_19 0xC8C049 -#define mmMP1_SYSHUB_SOC_TLB1_20 0xC8C04D -#define mmMP1_SYSHUB_SOC_TLB1_21 0xC8C051 -#define mmMP1_SYSHUB_SOC_TLB1_22 0xC8C055 -#define mmMP1_SYSHUB_SOC_TLB1_23 0xC8C059 -#define mmMP1_SYSHUB_SOC_TLB1_24 0xC8C05D -#define mmMP1_SYSHUB_SOC_TLB1_25 0xC8C061 -#define mmMP1_SYSHUB_SOC_TLB1_26 0xC8C065 -#define mmMP1_SYSHUB_SOC_TLB1_27 0xC8C069 -#define mmMP1_SYSHUB_SOC_TLB1_28 0xC8C06D -#define mmMP1_SYSHUB_SOC_TLB1_29 0xC8C071 -#define mmMP1_SYSHUB_SOC_TLB1_30 0xC8C075 -#define mmMP1_SYSHUB_SOC_TLB1_31 0xC8C079 -#define mmMP1_SYSHUB_SOC_TLB1_32 0xC8C07D -#define mmMP1_SYSHUB_SOC_TLB1_33 0xC8C081 -#define mmMP1_SYSHUB_SOC_TLB1_34 0xC8C085 -#define mmMP1_SYSHUB_SOC_TLB1_35 0xC8C089 -#define mmMP1_SYSHUB_SOC_TLB1_36 0xC8C08D -#define mmMP1_SYSHUB_SOC_TLB1_37 0xC8C091 -#define mmMP1_SYSHUB_SOC_TLB1_38 0xC8C095 -#define mmMP1_SYSHUB_SOC_TLB1_39 0xC8C099 -#define mmMP1_SYSHUB_SOC_TLB1_40 0xC8C09D -#define mmMP1_SYSHUB_SOC_TLB1_41 0xC8C0A1 -#define mmMP1_SYSHUB_SOC_TLB1_42 0xC8C0A5 -#define mmMP1_SYSHUB_SOC_TLB1_43 0xC8C0A9 -#define mmMP1_SYSHUB_SOC_TLB1_44 0xC8C0AD -#define mmMP1_SYSHUB_SOC_TLB1_45 0xC8C0B1 -#define mmMP1_SYSHUB_SOC_TLB1_46 0xC8C0B5 -#define mmMP1_SYSHUB_SOC_TLB1_47 0xC8C0B9 -#define mmMP1_SYSHUB_SOC_TLB1_48 0xC8C0BD -#define mmMP1_SYSHUB_SOC_TLB1_49 0xC8C0C1 -#define mmMP1_SYSHUB_SOC_TLB1_50 0xC8C0C5 -#define mmMP1_SYSHUB_SOC_TLB1_51 0xC8C0C9 -#define mmMP1_SYSHUB_SOC_TLB1_52 0xC8C0CD -#define mmMP1_SYSHUB_SOC_TLB1_53 0xC8C0D1 -#define mmMP1_SYSHUB_SOC_TLB1_54 0xC8C0D5 -#define mmMP1_SYSHUB_SOC_TLB1_55 0xC8C0D9 -#define mmMP1_SYSHUB_SOC_TLB1_56 0xC8C0DD -#define mmMP1_SYSHUB_SOC_TLB1_57 0xC8C0E1 -#define mmMP1_SYSHUB_SOC_TLB1_58 0xC8C0E5 -#define mmMP1_SYSHUB_SOC_TLB1_59 0xC8C0E9 -#define mmMP1_SYSHUB_SOC_TLB1_60 0xC8C0ED -#define mmMP1_SYSHUB_SOC_TLB1_61 0xC8C0F1 -#define mmMP1_SYSHUB_SOC_TLB1_62 0xC8C0F5 -#define mmMP1_SYSHUB_SOC_TLB2_1 0xC8C002 -#define mmMP1_SYSHUB_SOC_TLB2_2 0xC8C006 -#define mmMP1_SYSHUB_SOC_TLB2_3 0xC8C00A -#define mmMP1_SYSHUB_SOC_TLB2_4 0xC8C00E -#define mmMP1_SYSHUB_SOC_TLB2_5 0xC8C012 -#define mmMP1_SYSHUB_SOC_TLB2_6 0xC8C016 -#define mmMP1_SYSHUB_SOC_TLB2_7 0xC8C01A -#define mmMP1_SYSHUB_SOC_TLB2_8 0xC8C01E -#define mmMP1_SYSHUB_SOC_TLB2_9 0xC8C022 -#define mmMP1_SYSHUB_SOC_TLB2_10 0xC8C026 -#define mmMP1_SYSHUB_SOC_TLB2_11 0xC8C02A -#define mmMP1_SYSHUB_SOC_TLB2_12 0xC8C02E -#define mmMP1_SYSHUB_SOC_TLB2_13 0xC8C032 -#define mmMP1_SYSHUB_SOC_TLB2_14 0xC8C036 -#define mmMP1_SYSHUB_SOC_TLB2_15 0xC8C03A -#define mmMP1_SYSHUB_SOC_TLB2_16 0xC8C03E -#define mmMP1_SYSHUB_SOC_TLB2_17 0xC8C042 -#define mmMP1_SYSHUB_SOC_TLB2_18 0xC8C046 -#define mmMP1_SYSHUB_SOC_TLB2_19 0xC8C04A -#define mmMP1_SYSHUB_SOC_TLB2_20 0xC8C04E -#define mmMP1_SYSHUB_SOC_TLB2_21 0xC8C052 -#define mmMP1_SYSHUB_SOC_TLB2_22 0xC8C056 -#define mmMP1_SYSHUB_SOC_TLB2_23 0xC8C05A -#define mmMP1_SYSHUB_SOC_TLB2_24 0xC8C05E -#define mmMP1_SYSHUB_SOC_TLB2_25 0xC8C062 -#define mmMP1_SYSHUB_SOC_TLB2_26 0xC8C066 -#define mmMP1_SYSHUB_SOC_TLB2_27 0xC8C06A -#define mmMP1_SYSHUB_SOC_TLB2_28 0xC8C06E -#define mmMP1_SYSHUB_SOC_TLB2_29 0xC8C072 -#define mmMP1_SYSHUB_SOC_TLB2_30 0xC8C076 -#define mmMP1_SYSHUB_SOC_TLB2_31 0xC8C07A -#define mmMP1_SYSHUB_SOC_TLB2_32 0xC8C07E -#define mmMP1_SYSHUB_SOC_TLB2_33 0xC8C082 -#define mmMP1_SYSHUB_SOC_TLB2_34 0xC8C086 -#define mmMP1_SYSHUB_SOC_TLB2_35 0xC8C08A -#define mmMP1_SYSHUB_SOC_TLB2_36 0xC8C08E -#define mmMP1_SYSHUB_SOC_TLB2_37 0xC8C092 -#define mmMP1_SYSHUB_SOC_TLB2_38 0xC8C096 -#define mmMP1_SYSHUB_SOC_TLB2_39 0xC8C09A -#define mmMP1_SYSHUB_SOC_TLB2_40 0xC8C09E -#define mmMP1_SYSHUB_SOC_TLB2_41 0xC8C0A2 -#define mmMP1_SYSHUB_SOC_TLB2_42 0xC8C0A6 -#define mmMP1_SYSHUB_SOC_TLB2_43 0xC8C0AA -#define mmMP1_SYSHUB_SOC_TLB2_44 0xC8C0AE -#define mmMP1_SYSHUB_SOC_TLB2_45 0xC8C0B2 -#define mmMP1_SYSHUB_SOC_TLB2_46 0xC8C0B6 -#define mmMP1_SYSHUB_SOC_TLB2_47 0xC8C0BA -#define mmMP1_SYSHUB_SOC_TLB2_48 0xC8C0BE -#define mmMP1_SYSHUB_SOC_TLB2_49 0xC8C0C2 -#define mmMP1_SYSHUB_SOC_TLB2_50 0xC8C0C6 -#define mmMP1_SYSHUB_SOC_TLB2_51 0xC8C0CA -#define mmMP1_SYSHUB_SOC_TLB2_52 0xC8C0CE -#define mmMP1_SYSHUB_SOC_TLB2_53 0xC8C0D2 -#define mmMP1_SYSHUB_SOC_TLB2_54 0xC8C0D6 -#define mmMP1_SYSHUB_SOC_TLB2_55 0xC8C0DA -#define mmMP1_SYSHUB_SOC_TLB2_56 0xC8C0DE -#define mmMP1_SYSHUB_SOC_TLB2_57 0xC8C0E2 -#define mmMP1_SYSHUB_SOC_TLB2_58 0xC8C0E6 -#define mmMP1_SYSHUB_SOC_TLB2_59 0xC8C0EA -#define mmMP1_SYSHUB_SOC_TLB2_60 0xC8C0EE -#define mmMP1_SYSHUB_SOC_TLB2_61 0xC8C0F2 -#define mmMP1_SYSHUB_SOC_TLB2_62 0xC8C0F6 -#define mmMP1_SYSHUB_SOC_TLB3_1 0xC8C003 -#define mmMP1_SYSHUB_SOC_TLB3_2 0xC8C007 -#define mmMP1_SYSHUB_SOC_TLB3_3 0xC8C00B -#define mmMP1_SYSHUB_SOC_TLB3_4 0xC8C00F -#define mmMP1_SYSHUB_SOC_TLB3_5 0xC8C013 -#define mmMP1_SYSHUB_SOC_TLB3_6 0xC8C017 -#define mmMP1_SYSHUB_SOC_TLB3_7 0xC8C01B -#define mmMP1_SYSHUB_SOC_TLB3_8 0xC8C01F -#define mmMP1_SYSHUB_SOC_TLB3_9 0xC8C023 -#define mmMP1_SYSHUB_SOC_TLB3_10 0xC8C027 -#define mmMP1_SYSHUB_SOC_TLB3_11 0xC8C02B -#define mmMP1_SYSHUB_SOC_TLB3_12 0xC8C02F -#define mmMP1_SYSHUB_SOC_TLB3_13 0xC8C033 -#define mmMP1_SYSHUB_SOC_TLB3_14 0xC8C037 -#define mmMP1_SYSHUB_SOC_TLB3_15 0xC8C03B -#define mmMP1_SYSHUB_SOC_TLB3_16 0xC8C03F -#define mmMP1_SYSHUB_SOC_TLB3_17 0xC8C043 -#define mmMP1_SYSHUB_SOC_TLB3_18 0xC8C047 -#define mmMP1_SYSHUB_SOC_TLB3_19 0xC8C04B -#define mmMP1_SYSHUB_SOC_TLB3_20 0xC8C04F -#define mmMP1_SYSHUB_SOC_TLB3_21 0xC8C053 -#define mmMP1_SYSHUB_SOC_TLB3_22 0xC8C057 -#define mmMP1_SYSHUB_SOC_TLB3_23 0xC8C05B -#define mmMP1_SYSHUB_SOC_TLB3_24 0xC8C05F -#define mmMP1_SYSHUB_SOC_TLB3_25 0xC8C063 -#define mmMP1_SYSHUB_SOC_TLB3_26 0xC8C067 -#define mmMP1_SYSHUB_SOC_TLB3_27 0xC8C06B -#define mmMP1_SYSHUB_SOC_TLB3_28 0xC8C06F -#define mmMP1_SYSHUB_SOC_TLB3_29 0xC8C073 -#define mmMP1_SYSHUB_SOC_TLB3_30 0xC8C077 -#define mmMP1_SYSHUB_SOC_TLB3_31 0xC8C07B -#define mmMP1_SYSHUB_SOC_TLB3_32 0xC8C07F -#define mmMP1_SYSHUB_SOC_TLB3_33 0xC8C083 -#define mmMP1_SYSHUB_SOC_TLB3_34 0xC8C087 -#define mmMP1_SYSHUB_SOC_TLB3_35 0xC8C08B -#define mmMP1_SYSHUB_SOC_TLB3_36 0xC8C08F -#define mmMP1_SYSHUB_SOC_TLB3_37 0xC8C093 -#define mmMP1_SYSHUB_SOC_TLB3_38 0xC8C097 -#define mmMP1_SYSHUB_SOC_TLB3_39 0xC8C09B -#define mmMP1_SYSHUB_SOC_TLB3_40 0xC8C09F -#define mmMP1_SYSHUB_SOC_TLB3_41 0xC8C0A3 -#define mmMP1_SYSHUB_SOC_TLB3_42 0xC8C0A7 -#define mmMP1_SYSHUB_SOC_TLB3_43 0xC8C0AB -#define mmMP1_SYSHUB_SOC_TLB3_44 0xC8C0AF -#define mmMP1_SYSHUB_SOC_TLB3_45 0xC8C0B3 -#define mmMP1_SYSHUB_SOC_TLB3_46 0xC8C0B7 -#define mmMP1_SYSHUB_SOC_TLB3_47 0xC8C0BB -#define mmMP1_SYSHUB_SOC_TLB3_48 0xC8C0BF -#define mmMP1_SYSHUB_SOC_TLB3_49 0xC8C0C3 -#define mmMP1_SYSHUB_SOC_TLB3_50 0xC8C0C7 -#define mmMP1_SYSHUB_SOC_TLB3_51 0xC8C0CB -#define mmMP1_SYSHUB_SOC_TLB3_52 0xC8C0CF -#define mmMP1_SYSHUB_SOC_TLB3_53 0xC8C0D3 -#define mmMP1_SYSHUB_SOC_TLB3_54 0xC8C0D7 -#define mmMP1_SYSHUB_SOC_TLB3_55 0xC8C0DB -#define mmMP1_SYSHUB_SOC_TLB3_56 0xC8C0DF -#define mmMP1_SYSHUB_SOC_TLB3_57 0xC8C0E3 -#define mmMP1_SYSHUB_SOC_TLB3_58 0xC8C0E7 -#define mmMP1_SYSHUB_SOC_TLB3_59 0xC8C0EB -#define mmMP1_SYSHUB_SOC_TLB3_60 0xC8C0EF -#define mmMP1_SYSHUB_SOC_TLB3_61 0xC8C0F3 -#define mmMP1_SYSHUB_SOC_TLB3_62 0xC8C0F7 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 0xC8C0F8 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 0xC8C0F9 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 0xC8C0FA -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 0xC8C0FB -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 0xC8C0FC -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 0xC8C0FD -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 0xC8C0FE -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 0xC8C0FF -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 0xC8C100 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 0xC8C101 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 0xC8C102 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 0xC8C103 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 0xC8C104 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 0xC8C105 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 0xC8C106 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 0xC8C107 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 0xC8C108 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 0xC8C109 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 0xC8C10A -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 0xC8C10B -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 0xC8C10C -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 0xC8C10D -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 0xC8C10E -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 0xC8C10F -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 0xC8C110 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 0xC8C111 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 0xC8C112 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 0xC8C113 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 0xC8C114 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 0xC8C115 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 0xC8C116 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 0xC8C117 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 0xC8C118 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 0xC8C119 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 0xC8C11A -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 0xC8C11B -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 0xC8C11C -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 0xC8C11D -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 0xC8C11E -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 0xC8C11F -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 0xC8C120 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 0xC8C121 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 0xC8C122 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 0xC8C123 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 0xC8C124 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 0xC8C125 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 0xC8C126 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 0xC8C127 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 0xC8C128 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 0xC8C129 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 0xC8C12A -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 0xC8C12B -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 0xC8C12C -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 0xC8C12D -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 0xC8C12E -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 0xC8C12F -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 0xC8C130 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 0xC8C131 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 0xC8C132 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 0xC8C133 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 0xC8C134 -#define mmMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 0xC8C135 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_1 0xC8C136 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_2 0xC8C137 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_3 0xC8C138 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_4 0xC8C139 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_5 0xC8C13A -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_6 0xC8C13B -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_7 0xC8C13C -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_8 0xC8C13D -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_9 0xC8C13E -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_10 0xC8C13F -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_11 0xC8C140 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_12 0xC8C141 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_13 0xC8C142 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_14 0xC8C143 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_15 0xC8C144 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_16 0xC8C145 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_17 0xC8C146 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_18 0xC8C147 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_19 0xC8C148 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_20 0xC8C149 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_21 0xC8C14A -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_22 0xC8C14B -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_23 0xC8C14C -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_24 0xC8C14D -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_25 0xC8C14E -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_26 0xC8C14F -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_27 0xC8C150 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_28 0xC8C151 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_29 0xC8C152 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_30 0xC8C153 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_31 0xC8C154 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_32 0xC8C155 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_33 0xC8C156 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_34 0xC8C157 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_35 0xC8C158 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_36 0xC8C159 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_37 0xC8C15A -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_38 0xC8C15B -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_39 0xC8C15C -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_40 0xC8C15D -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_41 0xC8C15E -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_42 0xC8C15F -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_43 0xC8C160 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_44 0xC8C161 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_45 0xC8C162 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_46 0xC8C163 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_47 0xC8C164 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_48 0xC8C165 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_49 0xC8C166 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_50 0xC8C167 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_51 0xC8C168 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_52 0xC8C169 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_53 0xC8C16A -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_54 0xC8C16B -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_55 0xC8C16C -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_56 0xC8C16D -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_57 0xC8C16E -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_58 0xC8C16F -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_59 0xC8C170 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_60 0xC8C171 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_61 0xC8C172 -#define mmMP1_SYSHUB_TLB_ATTRIBUTE_62 0xC8C173 -#define mmMP1_SYSHUB_INT_STATUS 0xC8C174 -#define mmMP1_SYSHUB_WR_INT_ADDR 0xC8C175 -#define mmMP1_SYSHUB_WR_INT_OTHER 0xC8C176 -#define mmMP1_SYSHUB_RD_INT_ADDR 0xC8C177 -#define mmMP1_SYSHUB_RD_INT_OTHER 0xC8C178 -#define mmMP1_SYSHUB_REG_INT_ADDR 0xC8C179 -#define mmMP1_SYSHUB_REG_INT_OTHER 0xC8C17A -#define mmMP1_SYSHUB_AXCACHE_CFG 0xC8C17B -#define mmMP1_SYSHUB_DS_OVERRIDE 0xC8C17C -#define mmMP1_SYSHUB_OUTSTANDING 0xC8C17D - - -// Registers from MP_HUBIF block - -#define mmMP_HUBIF_SOC_TLB0_1 0x0000 -#define mmMP_HUBIF_SOC_TLB0_2 0x0004 -#define mmMP_HUBIF_SOC_TLB0_3 0x0008 -#define mmMP_HUBIF_SOC_TLB0_4 0x000C -#define mmMP_HUBIF_SOC_TLB0_5 0x0010 -#define mmMP_HUBIF_SOC_TLB0_6 0x0014 -#define mmMP_HUBIF_SOC_TLB0_7 0x0018 -#define mmMP_HUBIF_SOC_TLB0_8 0x001C -#define mmMP_HUBIF_SOC_TLB0_9 0x0020 -#define mmMP_HUBIF_SOC_TLB0_10 0x0024 -#define mmMP_HUBIF_SOC_TLB0_11 0x0028 -#define mmMP_HUBIF_SOC_TLB0_12 0x002C -#define mmMP_HUBIF_SOC_TLB0_13 0x0030 -#define mmMP_HUBIF_SOC_TLB0_14 0x0034 -#define mmMP_HUBIF_SOC_TLB0_15 0x0038 -#define mmMP_HUBIF_SOC_TLB0_16 0x003C -#define mmMP_HUBIF_SOC_TLB0_17 0x0040 -#define mmMP_HUBIF_SOC_TLB0_18 0x0044 -#define mmMP_HUBIF_SOC_TLB0_19 0x0048 -#define mmMP_HUBIF_SOC_TLB0_20 0x004C -#define mmMP_HUBIF_SOC_TLB0_21 0x0050 -#define mmMP_HUBIF_SOC_TLB0_22 0x0054 -#define mmMP_HUBIF_SOC_TLB0_23 0x0058 -#define mmMP_HUBIF_SOC_TLB0_24 0x005C -#define mmMP_HUBIF_SOC_TLB0_25 0x0060 -#define mmMP_HUBIF_SOC_TLB0_26 0x0064 -#define mmMP_HUBIF_SOC_TLB0_27 0x0068 -#define mmMP_HUBIF_SOC_TLB0_28 0x006C -#define mmMP_HUBIF_SOC_TLB0_29 0x0070 -#define mmMP_HUBIF_SOC_TLB0_30 0x0074 -#define mmMP_HUBIF_SOC_TLB0_31 0x0078 -#define mmMP_HUBIF_SOC_TLB0_32 0x007C -#define mmMP_HUBIF_SOC_TLB0_33 0x0080 -#define mmMP_HUBIF_SOC_TLB0_34 0x0084 -#define mmMP_HUBIF_SOC_TLB0_35 0x0088 -#define mmMP_HUBIF_SOC_TLB0_36 0x008C -#define mmMP_HUBIF_SOC_TLB0_37 0x0090 -#define mmMP_HUBIF_SOC_TLB0_38 0x0094 -#define mmMP_HUBIF_SOC_TLB0_39 0x0098 -#define mmMP_HUBIF_SOC_TLB0_40 0x009C -#define mmMP_HUBIF_SOC_TLB0_41 0x00A0 -#define mmMP_HUBIF_SOC_TLB0_42 0x00A4 -#define mmMP_HUBIF_SOC_TLB0_43 0x00A8 -#define mmMP_HUBIF_SOC_TLB0_44 0x00AC -#define mmMP_HUBIF_SOC_TLB0_45 0x00B0 -#define mmMP_HUBIF_SOC_TLB0_46 0x00B4 -#define mmMP_HUBIF_SOC_TLB0_47 0x00B8 -#define mmMP_HUBIF_SOC_TLB0_48 0x00BC -#define mmMP_HUBIF_SOC_TLB0_49 0x00C0 -#define mmMP_HUBIF_SOC_TLB0_50 0x00C4 -#define mmMP_HUBIF_SOC_TLB0_51 0x00C8 -#define mmMP_HUBIF_SOC_TLB0_52 0x00CC -#define mmMP_HUBIF_SOC_TLB0_53 0x00D0 -#define mmMP_HUBIF_SOC_TLB0_54 0x00D4 -#define mmMP_HUBIF_SOC_TLB0_55 0x00D8 -#define mmMP_HUBIF_SOC_TLB0_56 0x00DC -#define mmMP_HUBIF_SOC_TLB0_57 0x00E0 -#define mmMP_HUBIF_SOC_TLB0_58 0x00E4 -#define mmMP_HUBIF_SOC_TLB0_59 0x00E8 -#define mmMP_HUBIF_SOC_TLB0_60 0x00EC -#define mmMP_HUBIF_SOC_TLB0_61 0x00F0 -#define mmMP_HUBIF_SOC_TLB0_62 0x00F4 -#define mmMP_HUBIF_SOC_TLB1_1 0x0001 -#define mmMP_HUBIF_SOC_TLB1_2 0x0005 -#define mmMP_HUBIF_SOC_TLB1_3 0x0009 -#define mmMP_HUBIF_SOC_TLB1_4 0x000D -#define mmMP_HUBIF_SOC_TLB1_5 0x0011 -#define mmMP_HUBIF_SOC_TLB1_6 0x0015 -#define mmMP_HUBIF_SOC_TLB1_7 0x0019 -#define mmMP_HUBIF_SOC_TLB1_8 0x001D -#define mmMP_HUBIF_SOC_TLB1_9 0x0021 -#define mmMP_HUBIF_SOC_TLB1_10 0x0025 -#define mmMP_HUBIF_SOC_TLB1_11 0x0029 -#define mmMP_HUBIF_SOC_TLB1_12 0x002D -#define mmMP_HUBIF_SOC_TLB1_13 0x0031 -#define mmMP_HUBIF_SOC_TLB1_14 0x0035 -#define mmMP_HUBIF_SOC_TLB1_15 0x0039 -#define mmMP_HUBIF_SOC_TLB1_16 0x003D -#define mmMP_HUBIF_SOC_TLB1_17 0x0041 -#define mmMP_HUBIF_SOC_TLB1_18 0x0045 -#define mmMP_HUBIF_SOC_TLB1_19 0x0049 -#define mmMP_HUBIF_SOC_TLB1_20 0x004D -#define mmMP_HUBIF_SOC_TLB1_21 0x0051 -#define mmMP_HUBIF_SOC_TLB1_22 0x0055 -#define mmMP_HUBIF_SOC_TLB1_23 0x0059 -#define mmMP_HUBIF_SOC_TLB1_24 0x005D -#define mmMP_HUBIF_SOC_TLB1_25 0x0061 -#define mmMP_HUBIF_SOC_TLB1_26 0x0065 -#define mmMP_HUBIF_SOC_TLB1_27 0x0069 -#define mmMP_HUBIF_SOC_TLB1_28 0x006D -#define mmMP_HUBIF_SOC_TLB1_29 0x0071 -#define mmMP_HUBIF_SOC_TLB1_30 0x0075 -#define mmMP_HUBIF_SOC_TLB1_31 0x0079 -#define mmMP_HUBIF_SOC_TLB1_32 0x007D -#define mmMP_HUBIF_SOC_TLB1_33 0x0081 -#define mmMP_HUBIF_SOC_TLB1_34 0x0085 -#define mmMP_HUBIF_SOC_TLB1_35 0x0089 -#define mmMP_HUBIF_SOC_TLB1_36 0x008D -#define mmMP_HUBIF_SOC_TLB1_37 0x0091 -#define mmMP_HUBIF_SOC_TLB1_38 0x0095 -#define mmMP_HUBIF_SOC_TLB1_39 0x0099 -#define mmMP_HUBIF_SOC_TLB1_40 0x009D -#define mmMP_HUBIF_SOC_TLB1_41 0x00A1 -#define mmMP_HUBIF_SOC_TLB1_42 0x00A5 -#define mmMP_HUBIF_SOC_TLB1_43 0x00A9 -#define mmMP_HUBIF_SOC_TLB1_44 0x00AD -#define mmMP_HUBIF_SOC_TLB1_45 0x00B1 -#define mmMP_HUBIF_SOC_TLB1_46 0x00B5 -#define mmMP_HUBIF_SOC_TLB1_47 0x00B9 -#define mmMP_HUBIF_SOC_TLB1_48 0x00BD -#define mmMP_HUBIF_SOC_TLB1_49 0x00C1 -#define mmMP_HUBIF_SOC_TLB1_50 0x00C5 -#define mmMP_HUBIF_SOC_TLB1_51 0x00C9 -#define mmMP_HUBIF_SOC_TLB1_52 0x00CD -#define mmMP_HUBIF_SOC_TLB1_53 0x00D1 -#define mmMP_HUBIF_SOC_TLB1_54 0x00D5 -#define mmMP_HUBIF_SOC_TLB1_55 0x00D9 -#define mmMP_HUBIF_SOC_TLB1_56 0x00DD -#define mmMP_HUBIF_SOC_TLB1_57 0x00E1 -#define mmMP_HUBIF_SOC_TLB1_58 0x00E5 -#define mmMP_HUBIF_SOC_TLB1_59 0x00E9 -#define mmMP_HUBIF_SOC_TLB1_60 0x00ED -#define mmMP_HUBIF_SOC_TLB1_61 0x00F1 -#define mmMP_HUBIF_SOC_TLB1_62 0x00F5 -#define mmMP_HUBIF_SOC_TLB2_1 0x0002 -#define mmMP_HUBIF_SOC_TLB2_2 0x0006 -#define mmMP_HUBIF_SOC_TLB2_3 0x000A -#define mmMP_HUBIF_SOC_TLB2_4 0x000E -#define mmMP_HUBIF_SOC_TLB2_5 0x0012 -#define mmMP_HUBIF_SOC_TLB2_6 0x0016 -#define mmMP_HUBIF_SOC_TLB2_7 0x001A -#define mmMP_HUBIF_SOC_TLB2_8 0x001E -#define mmMP_HUBIF_SOC_TLB2_9 0x0022 -#define mmMP_HUBIF_SOC_TLB2_10 0x0026 -#define mmMP_HUBIF_SOC_TLB2_11 0x002A -#define mmMP_HUBIF_SOC_TLB2_12 0x002E -#define mmMP_HUBIF_SOC_TLB2_13 0x0032 -#define mmMP_HUBIF_SOC_TLB2_14 0x0036 -#define mmMP_HUBIF_SOC_TLB2_15 0x003A -#define mmMP_HUBIF_SOC_TLB2_16 0x003E -#define mmMP_HUBIF_SOC_TLB2_17 0x0042 -#define mmMP_HUBIF_SOC_TLB2_18 0x0046 -#define mmMP_HUBIF_SOC_TLB2_19 0x004A -#define mmMP_HUBIF_SOC_TLB2_20 0x004E -#define mmMP_HUBIF_SOC_TLB2_21 0x0052 -#define mmMP_HUBIF_SOC_TLB2_22 0x0056 -#define mmMP_HUBIF_SOC_TLB2_23 0x005A -#define mmMP_HUBIF_SOC_TLB2_24 0x005E -#define mmMP_HUBIF_SOC_TLB2_25 0x0062 -#define mmMP_HUBIF_SOC_TLB2_26 0x0066 -#define mmMP_HUBIF_SOC_TLB2_27 0x006A -#define mmMP_HUBIF_SOC_TLB2_28 0x006E -#define mmMP_HUBIF_SOC_TLB2_29 0x0072 -#define mmMP_HUBIF_SOC_TLB2_30 0x0076 -#define mmMP_HUBIF_SOC_TLB2_31 0x007A -#define mmMP_HUBIF_SOC_TLB2_32 0x007E -#define mmMP_HUBIF_SOC_TLB2_33 0x0082 -#define mmMP_HUBIF_SOC_TLB2_34 0x0086 -#define mmMP_HUBIF_SOC_TLB2_35 0x008A -#define mmMP_HUBIF_SOC_TLB2_36 0x008E -#define mmMP_HUBIF_SOC_TLB2_37 0x0092 -#define mmMP_HUBIF_SOC_TLB2_38 0x0096 -#define mmMP_HUBIF_SOC_TLB2_39 0x009A -#define mmMP_HUBIF_SOC_TLB2_40 0x009E -#define mmMP_HUBIF_SOC_TLB2_41 0x00A2 -#define mmMP_HUBIF_SOC_TLB2_42 0x00A6 -#define mmMP_HUBIF_SOC_TLB2_43 0x00AA -#define mmMP_HUBIF_SOC_TLB2_44 0x00AE -#define mmMP_HUBIF_SOC_TLB2_45 0x00B2 -#define mmMP_HUBIF_SOC_TLB2_46 0x00B6 -#define mmMP_HUBIF_SOC_TLB2_47 0x00BA -#define mmMP_HUBIF_SOC_TLB2_48 0x00BE -#define mmMP_HUBIF_SOC_TLB2_49 0x00C2 -#define mmMP_HUBIF_SOC_TLB2_50 0x00C6 -#define mmMP_HUBIF_SOC_TLB2_51 0x00CA -#define mmMP_HUBIF_SOC_TLB2_52 0x00CE -#define mmMP_HUBIF_SOC_TLB2_53 0x00D2 -#define mmMP_HUBIF_SOC_TLB2_54 0x00D6 -#define mmMP_HUBIF_SOC_TLB2_55 0x00DA -#define mmMP_HUBIF_SOC_TLB2_56 0x00DE -#define mmMP_HUBIF_SOC_TLB2_57 0x00E2 -#define mmMP_HUBIF_SOC_TLB2_58 0x00E6 -#define mmMP_HUBIF_SOC_TLB2_59 0x00EA -#define mmMP_HUBIF_SOC_TLB2_60 0x00EE -#define mmMP_HUBIF_SOC_TLB2_61 0x00F2 -#define mmMP_HUBIF_SOC_TLB2_62 0x00F6 -#define mmMP_HUBIF_SOC_TLB3_1 0x0003 -#define mmMP_HUBIF_SOC_TLB3_2 0x0007 -#define mmMP_HUBIF_SOC_TLB3_3 0x000B -#define mmMP_HUBIF_SOC_TLB3_4 0x000F -#define mmMP_HUBIF_SOC_TLB3_5 0x0013 -#define mmMP_HUBIF_SOC_TLB3_6 0x0017 -#define mmMP_HUBIF_SOC_TLB3_7 0x001B -#define mmMP_HUBIF_SOC_TLB3_8 0x001F -#define mmMP_HUBIF_SOC_TLB3_9 0x0023 -#define mmMP_HUBIF_SOC_TLB3_10 0x0027 -#define mmMP_HUBIF_SOC_TLB3_11 0x002B -#define mmMP_HUBIF_SOC_TLB3_12 0x002F -#define mmMP_HUBIF_SOC_TLB3_13 0x0033 -#define mmMP_HUBIF_SOC_TLB3_14 0x0037 -#define mmMP_HUBIF_SOC_TLB3_15 0x003B -#define mmMP_HUBIF_SOC_TLB3_16 0x003F -#define mmMP_HUBIF_SOC_TLB3_17 0x0043 -#define mmMP_HUBIF_SOC_TLB3_18 0x0047 -#define mmMP_HUBIF_SOC_TLB3_19 0x004B -#define mmMP_HUBIF_SOC_TLB3_20 0x004F -#define mmMP_HUBIF_SOC_TLB3_21 0x0053 -#define mmMP_HUBIF_SOC_TLB3_22 0x0057 -#define mmMP_HUBIF_SOC_TLB3_23 0x005B -#define mmMP_HUBIF_SOC_TLB3_24 0x005F -#define mmMP_HUBIF_SOC_TLB3_25 0x0063 -#define mmMP_HUBIF_SOC_TLB3_26 0x0067 -#define mmMP_HUBIF_SOC_TLB3_27 0x006B -#define mmMP_HUBIF_SOC_TLB3_28 0x006F -#define mmMP_HUBIF_SOC_TLB3_29 0x0073 -#define mmMP_HUBIF_SOC_TLB3_30 0x0077 -#define mmMP_HUBIF_SOC_TLB3_31 0x007B -#define mmMP_HUBIF_SOC_TLB3_32 0x007F -#define mmMP_HUBIF_SOC_TLB3_33 0x0083 -#define mmMP_HUBIF_SOC_TLB3_34 0x0087 -#define mmMP_HUBIF_SOC_TLB3_35 0x008B -#define mmMP_HUBIF_SOC_TLB3_36 0x008F -#define mmMP_HUBIF_SOC_TLB3_37 0x0093 -#define mmMP_HUBIF_SOC_TLB3_38 0x0097 -#define mmMP_HUBIF_SOC_TLB3_39 0x009B -#define mmMP_HUBIF_SOC_TLB3_40 0x009F -#define mmMP_HUBIF_SOC_TLB3_41 0x00A3 -#define mmMP_HUBIF_SOC_TLB3_42 0x00A7 -#define mmMP_HUBIF_SOC_TLB3_43 0x00AB -#define mmMP_HUBIF_SOC_TLB3_44 0x00AF -#define mmMP_HUBIF_SOC_TLB3_45 0x00B3 -#define mmMP_HUBIF_SOC_TLB3_46 0x00B7 -#define mmMP_HUBIF_SOC_TLB3_47 0x00BB -#define mmMP_HUBIF_SOC_TLB3_48 0x00BF -#define mmMP_HUBIF_SOC_TLB3_49 0x00C3 -#define mmMP_HUBIF_SOC_TLB3_50 0x00C7 -#define mmMP_HUBIF_SOC_TLB3_51 0x00CB -#define mmMP_HUBIF_SOC_TLB3_52 0x00CF -#define mmMP_HUBIF_SOC_TLB3_53 0x00D3 -#define mmMP_HUBIF_SOC_TLB3_54 0x00D7 -#define mmMP_HUBIF_SOC_TLB3_55 0x00DB -#define mmMP_HUBIF_SOC_TLB3_56 0x00DF -#define mmMP_HUBIF_SOC_TLB3_57 0x00E3 -#define mmMP_HUBIF_SOC_TLB3_58 0x00E7 -#define mmMP_HUBIF_SOC_TLB3_59 0x00EB -#define mmMP_HUBIF_SOC_TLB3_60 0x00EF -#define mmMP_HUBIF_SOC_TLB3_61 0x00F3 -#define mmMP_HUBIF_SOC_TLB3_62 0x00F7 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_1 0x00F8 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_2 0x00F9 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_3 0x00FA -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_4 0x00FB -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_5 0x00FC -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_6 0x00FD -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_7 0x00FE -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_8 0x00FF -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_9 0x0100 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_10 0x0101 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_11 0x0102 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_12 0x0103 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_13 0x0104 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_14 0x0105 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_15 0x0106 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_16 0x0107 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_17 0x0108 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_18 0x0109 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_19 0x010A -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_20 0x010B -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_21 0x010C -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_22 0x010D -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_23 0x010E -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_24 0x010F -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_25 0x0110 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_26 0x0111 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_27 0x0112 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_28 0x0113 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_29 0x0114 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_30 0x0115 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_31 0x0116 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_32 0x0117 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_33 0x0118 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_34 0x0119 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_35 0x011A -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_36 0x011B -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_37 0x011C -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_38 0x011D -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_39 0x011E -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_40 0x011F -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_41 0x0120 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_42 0x0121 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_43 0x0122 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_44 0x0123 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_45 0x0124 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_46 0x0125 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_47 0x0126 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_48 0x0127 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_49 0x0128 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_50 0x0129 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_51 0x012A -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_52 0x012B -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_53 0x012C -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_54 0x012D -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_55 0x012E -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_56 0x012F -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_57 0x0130 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_58 0x0131 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_59 0x0132 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_60 0x0133 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_61 0x0134 -#define mmMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_62 0x0135 -#define mmMP_HUBIF_TLB_ATTRIBUTE_1 0x0136 -#define mmMP_HUBIF_TLB_ATTRIBUTE_2 0x0137 -#define mmMP_HUBIF_TLB_ATTRIBUTE_3 0x0138 -#define mmMP_HUBIF_TLB_ATTRIBUTE_4 0x0139 -#define mmMP_HUBIF_TLB_ATTRIBUTE_5 0x013A -#define mmMP_HUBIF_TLB_ATTRIBUTE_6 0x013B -#define mmMP_HUBIF_TLB_ATTRIBUTE_7 0x013C -#define mmMP_HUBIF_TLB_ATTRIBUTE_8 0x013D -#define mmMP_HUBIF_TLB_ATTRIBUTE_9 0x013E -#define mmMP_HUBIF_TLB_ATTRIBUTE_10 0x013F -#define mmMP_HUBIF_TLB_ATTRIBUTE_11 0x0140 -#define mmMP_HUBIF_TLB_ATTRIBUTE_12 0x0141 -#define mmMP_HUBIF_TLB_ATTRIBUTE_13 0x0142 -#define mmMP_HUBIF_TLB_ATTRIBUTE_14 0x0143 -#define mmMP_HUBIF_TLB_ATTRIBUTE_15 0x0144 -#define mmMP_HUBIF_TLB_ATTRIBUTE_16 0x0145 -#define mmMP_HUBIF_TLB_ATTRIBUTE_17 0x0146 -#define mmMP_HUBIF_TLB_ATTRIBUTE_18 0x0147 -#define mmMP_HUBIF_TLB_ATTRIBUTE_19 0x0148 -#define mmMP_HUBIF_TLB_ATTRIBUTE_20 0x0149 -#define mmMP_HUBIF_TLB_ATTRIBUTE_21 0x014A -#define mmMP_HUBIF_TLB_ATTRIBUTE_22 0x014B -#define mmMP_HUBIF_TLB_ATTRIBUTE_23 0x014C -#define mmMP_HUBIF_TLB_ATTRIBUTE_24 0x014D -#define mmMP_HUBIF_TLB_ATTRIBUTE_25 0x014E -#define mmMP_HUBIF_TLB_ATTRIBUTE_26 0x014F -#define mmMP_HUBIF_TLB_ATTRIBUTE_27 0x0150 -#define mmMP_HUBIF_TLB_ATTRIBUTE_28 0x0151 -#define mmMP_HUBIF_TLB_ATTRIBUTE_29 0x0152 -#define mmMP_HUBIF_TLB_ATTRIBUTE_30 0x0153 -#define mmMP_HUBIF_TLB_ATTRIBUTE_31 0x0154 -#define mmMP_HUBIF_TLB_ATTRIBUTE_32 0x0155 -#define mmMP_HUBIF_TLB_ATTRIBUTE_33 0x0156 -#define mmMP_HUBIF_TLB_ATTRIBUTE_34 0x0157 -#define mmMP_HUBIF_TLB_ATTRIBUTE_35 0x0158 -#define mmMP_HUBIF_TLB_ATTRIBUTE_36 0x0159 -#define mmMP_HUBIF_TLB_ATTRIBUTE_37 0x015A -#define mmMP_HUBIF_TLB_ATTRIBUTE_38 0x015B -#define mmMP_HUBIF_TLB_ATTRIBUTE_39 0x015C -#define mmMP_HUBIF_TLB_ATTRIBUTE_40 0x015D -#define mmMP_HUBIF_TLB_ATTRIBUTE_41 0x015E -#define mmMP_HUBIF_TLB_ATTRIBUTE_42 0x015F -#define mmMP_HUBIF_TLB_ATTRIBUTE_43 0x0160 -#define mmMP_HUBIF_TLB_ATTRIBUTE_44 0x0161 -#define mmMP_HUBIF_TLB_ATTRIBUTE_45 0x0162 -#define mmMP_HUBIF_TLB_ATTRIBUTE_46 0x0163 -#define mmMP_HUBIF_TLB_ATTRIBUTE_47 0x0164 -#define mmMP_HUBIF_TLB_ATTRIBUTE_48 0x0165 -#define mmMP_HUBIF_TLB_ATTRIBUTE_49 0x0166 -#define mmMP_HUBIF_TLB_ATTRIBUTE_50 0x0167 -#define mmMP_HUBIF_TLB_ATTRIBUTE_51 0x0168 -#define mmMP_HUBIF_TLB_ATTRIBUTE_52 0x0169 -#define mmMP_HUBIF_TLB_ATTRIBUTE_53 0x016A -#define mmMP_HUBIF_TLB_ATTRIBUTE_54 0x016B -#define mmMP_HUBIF_TLB_ATTRIBUTE_55 0x016C -#define mmMP_HUBIF_TLB_ATTRIBUTE_56 0x016D -#define mmMP_HUBIF_TLB_ATTRIBUTE_57 0x016E -#define mmMP_HUBIF_TLB_ATTRIBUTE_58 0x016F -#define mmMP_HUBIF_TLB_ATTRIBUTE_59 0x0170 -#define mmMP_HUBIF_TLB_ATTRIBUTE_60 0x0171 -#define mmMP_HUBIF_TLB_ATTRIBUTE_61 0x0172 -#define mmMP_HUBIF_TLB_ATTRIBUTE_62 0x0173 -#define mmMP_HUBIF_INT_STATUS 0x0174 -#define mmMP_HUBIF_WR_INT_ADDR 0x0175 -#define mmMP_HUBIF_WR_INT_OTHER 0x0176 -#define mmMP_HUBIF_RD_INT_ADDR 0x0177 -#define mmMP_HUBIF_RD_INT_OTHER 0x0178 -#define mmMP_HUBIF_REG_INT_ADDR 0x0179 -#define mmMP_HUBIF_REG_INT_OTHER 0x017A -#define mmMP_HUBIF_AXCACHE_CFG 0x017B -#define mmMP_HUBIF_DS_OVERRIDE 0x017C -#define mmMP_HUBIF_OUTSTANDING 0x017D - - -// Registers from MP_HUBIF_NB block - -#define mmHUBIF_NB_AX_ADDR_LO 0xCA0000 -#define mmHUBIF_NB_AX_MISC 0xCA0001 -#define mmHUBIF_NB_AX_MISC_2 0xCA0002 -#define mmHUBIF_NB_WSTRB0 0xCA0003 -#define mmHUBIF_NB_WSTRB1 0xCA0004 -#define mmHUBIF_NB_WDATA0 0xCA0005 -#define mmHUBIF_NB_WDATA1 0xCA0006 -#define mmHUBIF_NB_WDATA2 0xCA0007 -#define mmHUBIF_NB_WDATA3 0xCA0008 -#define mmHUBIF_NB_WDATA4 0xCA0009 -#define mmHUBIF_NB_WDATA5 0xCA000A -#define mmHUBIF_NB_WDATA6 0xCA000B -#define mmHUBIF_NB_WDATA7 0xCA000C -#define mmHUBIF_NB_WDATA8 0xCA000D -#define mmHUBIF_NB_WDATA9 0xCA000E -#define mmHUBIF_NB_WDATA10 0xCA000F -#define mmHUBIF_NB_WDATA11 0xCA0010 -#define mmHUBIF_NB_WDATA12 0xCA0011 -#define mmHUBIF_NB_WDATA13 0xCA0012 -#define mmHUBIF_NB_WDATA14 0xCA0013 -#define mmHUBIF_NB_WDATA15 0xCA0014 -#define mmHUBIF_NB_RDATA0 0xCA0015 -#define mmHUBIF_NB_RDATA1 0xCA0016 -#define mmHUBIF_NB_RDATA2 0xCA0017 -#define mmHUBIF_NB_RDATA3 0xCA0018 -#define mmHUBIF_NB_RDATA4 0xCA0019 -#define mmHUBIF_NB_RDATA5 0xCA001A -#define mmHUBIF_NB_RDATA6 0xCA001B -#define mmHUBIF_NB_RDATA7 0xCA001C -#define mmHUBIF_NB_RDATA8 0xCA001D -#define mmHUBIF_NB_RDATA9 0xCA001E -#define mmHUBIF_NB_RDATA10 0xCA001F -#define mmHUBIF_NB_RDATA11 0xCA0020 -#define mmHUBIF_NB_RDATA12 0xCA0021 -#define mmHUBIF_NB_RDATA13 0xCA0022 -#define mmHUBIF_NB_RDATA14 0xCA0023 -#define mmHUBIF_NB_RDATA15 0xCA0024 -#define mmHUBIF_NB_AXI_RESP 0xCA0025 -#define mmHUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS 0xCA0026 -#define mmHUBIF_ACC_VIOLATION_LOG_ADDR 0xCA0027 - - -// Registers from MP_SMNIF block - -#define mmSMNIF_TLB_0 0xC88000 -#define mmSMNIF_TLB_1 0xC88001 -#define mmSMNIF_TLB_2 0xC88002 -#define mmSMNIF_TLB_3 0xC88003 -#define mmSMNIF_TLB_4 0xC88004 -#define mmSMNIF_TLB_5 0xC88005 -#define mmSMNIF_TLB_6 0xC88006 -#define mmSMNIF_TLB_7 0xC88007 -#define mmSMNIF_TLB_8 0xC88008 -#define mmSMNIF_TLB_9 0xC88009 -#define mmSMNIF_TLB_10 0xC8800A -#define mmSMNIF_TLB_11 0xC8800B -#define mmSMNIF_TLB_12 0xC8800C -#define mmSMNIF_TLB_13 0xC8800D -#define mmSMNIF_TLB_14 0xC8800E -#define mmSMNIF_TLB_15 0xC8800F -#define mmSMNIF_TLV0 0xC88010 -#define mmSMNIF_TLV1 0xC88011 -#define mmSMNIF_TLV2 0xC88012 -#define mmSMNIF_TLV3 0xC88013 -#define mmSMNIF_TLB_QOS 0xC88014 -#define mmSMNIF_ACC_VIOLATION_LOG_ADDR 0xC88015 -#define mmSMNIF_ACC_VIOLATION_LOG_STATUS 0xC88016 -#define mmSMNIF_LPBK_WR_VIOL_ADDR 0xC88017 -#define mmSMNIF_LPBK_WR_VIOL_STATUS 0xC88018 -#define mmSMNIF_LPBK_RD_VIOL_ADDR 0xC88019 -#define mmSMNIF_LPBK_RD_VIOL_STATUS 0xC8801A -#define mmSMNIF_MISC_CTRL 0xC8801B -#define mmSMNIF_REQ_CNT 0xC8801C -#define mmSMNIF_SCRATCH0 0xC8801D -#define mmSMNIF_SCRATCH1 0xC8801E -#define mmSMNIF_SCRATCH2 0xC8801F -#define mmSMNIF_SCRATCH3 0xC88020 -#define mmSMNIF_SECURE_CTRL 0xC88021 -#define mmSMNIF_TLVMASK_SECURE 0xC88022 -#define mmSMNIF_TLVMASK_NONSECURE 0xC88023 -#define mmSMNIF_TLR_0 0xC88024 -#define mmSMNIF_TLR_ADDR_0 0xC88025 -#define mmSMNIF_TLR_1 0xC88026 -#define mmSMNIF_TLR_ADDR_1 0xC88027 -#define mmSMNIF_TLR_2 0xC88028 -#define mmSMNIF_TLR_ADDR_2 0xC88029 -#define mmSMNIF_TLR_3 0xC8802A -#define mmSMNIF_TLR_ADDR_3 0xC8802B -#define mmSMNIF_TLR_4 0xC8802C -#define mmSMNIF_TLR_ADDR_4 0xC8802D -#define mmSMNIF_TLR_5 0xC8802E -#define mmSMNIF_TLR_ADDR_5 0xC8802F -#define mmSMNIF_TLR_6 0xC88030 -#define mmSMNIF_TLR_ADDR_6 0xC88031 -#define mmSMNIF_TLR_7 0xC88032 -#define mmSMNIF_TLR_ADDR_7 0xC88033 -#define mmSMNIF_TLR_8 0xC88034 -#define mmSMNIF_TLR_ADDR_8 0xC88035 -#define mmSMNIF_TLR_9 0xC88036 -#define mmSMNIF_TLR_ADDR_9 0xC88037 -#define mmSMNIF_TLR_10 0xC88038 -#define mmSMNIF_TLR_ADDR_10 0xC88039 -#define mmSMNIF_TLR_11 0xC8803A -#define mmSMNIF_TLR_ADDR_11 0xC8803B -#define mmSMNIF_TLR_12 0xC8803C -#define mmSMNIF_TLR_ADDR_12 0xC8803D -#define mmSMNIF_TLR_13 0xC8803E -#define mmSMNIF_TLR_ADDR_13 0xC8803F -#define mmSMNIF_TLR_14 0xC88040 -#define mmSMNIF_TLR_ADDR_14 0xC88041 -#define mmSMNIF_TLR_15 0xC88042 -#define mmSMNIF_TLR_ADDR_15 0xC88043 - - -// Registers from MP_ROM block - -#define mmMP_ROM_ACC_VIOLATION_LOG_ADDR 0xC98000 -#define mmMP_ROM_ACC_VIOLATION_LOG_STATUS 0xC98001 -#define mmMP_ROM_MISC_CNTL 0xC98002 -#define mmMP_ROM_SCRATCH_0 0xC98003 -#define mmMP_ROM_SCRATCH_1 0xC98004 -#define mmMP_ROM_SCRATCH_2 0xC98005 -#define mmMP_ROM_SCRATCH_3 0xC98006 - - -// Registers from MP_DMAC block - -#define mmDMAC_ACC_VIOLATION_LOG_ADDR 0xC9C400 -#define mmDMAC_ACC_VIOLATION_LOG_STATUS 0xC9C401 -#define mmDMAC_MISC_CTRL 0xC9C402 - - -// Registers from SMUIO block - -#define mmSMUSVI0_PLANE1_LOAD 0x16800 -#define mmSMUSVI0_PLANE0_LOAD 0x16801 -#define mmSMUSVI0_TFN 0x16802 -#define mmSMUSVI0_TEL_PLANE1 0x16803 -#define mmSMUSVI0_TEL_PLANE0 0x16804 -#define mmSMUSVI1_TEL_PLANE0 0x16805 -#define mmSMUSVI1_PLANE0_LOAD 0x16806 -#define mmSMUSVI1_TFN 0x16807 -#define mmSMUSVI1_PLANE0_PSI0 0x16808 -#define mmSMUSVI0_MISC_VID_STATUS 0x16809 -#define mmSMUSVI0_PWR_CTL_MISC 0x1680A -#define mmSMUSVI0_PLANE_VIDCHG 0x1680B -#define mmSMUSVI1_PLANE_VIDCHG 0x1680C -#define mmSMUSVI_WARMRESET_TARGET_VID 0x1680D -#define mmSMUSVI_WARMRESET_SEL 0x1680E -#define mmSMUSVI0_PLANE0_VIDCHGBUSY 0x1680F -#define mmSMUSVI0_PLANE1_VIDCHGBUSY 0x16810 -#define mmSMUSVI1_PLANE0_VIDCHGBUSY 0x16811 -#define mmSMUSVI1_PLANE1_VIDCHGBUSY 0x16812 -#define mmSMUSVI0_PLANE0_CURRENTVID 0x16813 -#define mmSMUSVI1_PLANE0_CURRENTVID 0x16814 -#define mmSMUSVI0_PLANE1_CURRENTVID 0x16815 -#define mmSMUSVI_ALL_CPU_IN_CC6 0x16816 -#define mmSMUSVI_BOOTVID 0x16817 -#define mmSMUSVI_STARTUP_VID_COMPLETE 0x16818 -#define mmSMUSVI_WARM_RESET 0x16819 -#define mmSMUSVI_SVC0 0x1681A -#define mmSMUSVI_SVD0 0x1681B -#define mmSMUSVI_SVT0 0x1681C -#define mmSMUSVI_PLANE_USAGE 0x1681D -#define mmSMUIO_MCM_CONFIG 0x1681E -#define mmSMUSVI_STARTUP_VID_EN 0x1681F -#define mmSMUSVI_STARTUP_VID_TRIGGER 0x16820 -#define mmSMUIO_RESET_SEL 0x16821 -#define mmSMUIO_MP_RESET_INTR 0x16822 -#define mmSMUIO_RESET_DELAY 0x16823 -#define mmROM_CNTL 0x16824 -#define mmPAGE_MIRROR_CNTL 0x16825 -#define mmROM_STATUS 0x16826 -#define mmCGTT_ROM_CLK_CTRL0 0x16827 -#define mmROM_INDEX 0x16828 -#define mmROM_DATA 0x16829 -#define mmROM_START 0x1682A -#define mmROM_SW_CNTL 0x1682B -#define mmROM_SW_STATUS 0x1682C -#define mmROM_SW_COMMAND 0x1682D -#define mmROM_SW_DATA_1 0x1682E -#define mmROM_SW_DATA_2 0x1682F -#define mmROM_SW_DATA_3 0x16830 -#define mmROM_SW_DATA_4 0x16831 -#define mmROM_SW_DATA_5 0x16832 -#define mmROM_SW_DATA_6 0x16833 -#define mmROM_SW_DATA_7 0x16834 -#define mmROM_SW_DATA_8 0x16835 -#define mmROM_SW_DATA_9 0x16836 -#define mmROM_SW_DATA_10 0x16837 -#define mmROM_SW_DATA_11 0x16838 -#define mmROM_SW_DATA_12 0x16839 -#define mmROM_SW_DATA_13 0x1683A -#define mmROM_SW_DATA_14 0x1683B -#define mmROM_SW_DATA_15 0x1683C -#define mmROM_SW_DATA_16 0x1683D -#define mmROM_SW_DATA_17 0x1683E -#define mmROM_SW_DATA_18 0x1683F -#define mmROM_SW_DATA_19 0x16840 -#define mmROM_SW_DATA_20 0x16841 -#define mmROM_SW_DATA_21 0x16842 -#define mmROM_SW_DATA_22 0x16843 -#define mmROM_SW_DATA_23 0x16844 -#define mmROM_SW_DATA_24 0x16845 -#define mmROM_SW_DATA_25 0x16846 -#define mmROM_SW_DATA_26 0x16847 -#define mmROM_SW_DATA_27 0x16848 -#define mmROM_SW_DATA_28 0x16849 -#define mmROM_SW_DATA_29 0x1684A -#define mmROM_SW_DATA_30 0x1684B -#define mmROM_SW_DATA_31 0x1684C -#define mmROM_SW_DATA_32 0x1684D -#define mmROM_SW_DATA_33 0x1684E -#define mmROM_SW_DATA_34 0x1684F -#define mmROM_SW_DATA_35 0x16850 -#define mmROM_SW_DATA_36 0x16851 -#define mmROM_SW_DATA_37 0x16852 -#define mmROM_SW_DATA_38 0x16853 -#define mmROM_SW_DATA_39 0x16854 -#define mmROM_SW_DATA_40 0x16855 -#define mmROM_SW_DATA_41 0x16856 -#define mmROM_SW_DATA_42 0x16857 -#define mmROM_SW_DATA_43 0x16858 -#define mmROM_SW_DATA_44 0x16859 -#define mmROM_SW_DATA_45 0x1685A -#define mmROM_SW_DATA_46 0x1685B -#define mmROM_SW_DATA_47 0x1685C -#define mmROM_SW_DATA_48 0x1685D -#define mmROM_SW_DATA_49 0x1685E -#define mmROM_SW_DATA_50 0x1685F -#define mmROM_SW_DATA_51 0x16860 -#define mmROM_SW_DATA_52 0x16861 -#define mmROM_SW_DATA_53 0x16862 -#define mmROM_SW_DATA_54 0x16863 -#define mmROM_SW_DATA_55 0x16864 -#define mmROM_SW_DATA_56 0x16865 -#define mmROM_SW_DATA_57 0x16866 -#define mmROM_SW_DATA_58 0x16867 -#define mmROM_SW_DATA_59 0x16868 -#define mmROM_SW_DATA_60 0x16869 -#define mmROM_SW_DATA_61 0x1686A -#define mmROM_SW_DATA_62 0x1686B -#define mmROM_SW_DATA_63 0x1686C -#define mmROM_SW_DATA_64 0x1686D -#define mmSMU_GPIOPAD_SW_INT_STAT 0x1686E -#define mmSMU_GPIOPAD_MASK 0x1686F -#define mmSMU_GPIOPAD_A 0x16870 -#define mmSMU_GPIOPAD_TXIMPSEL 0x16871 -#define mmSMU_GPIOPAD_EN 0x16872 -#define mmSMU_GPIOPAD_Y 0x16873 -#define mmSMU_GPIOPAD_RXEN 0x16874 -#define mmSMU_GPIOPAD_RCVR_SEL0 0x16875 -#define mmSMU_GPIOPAD_RCVR_SEL1 0x16876 -#define mmSMU_GPIOPAD_PU_EN 0x16877 -#define mmSMU_GPIOPAD_PD_EN 0x16878 -#define mmSMU_GPIOPAD_PINSTRAPS 0x16879 -#define mmSMU_GPIOPAD_INT_STAT_EN 0x1687A -#define mmSMU_GPIOPAD_INT_STAT 0x1687B -#define mmSMU_GPIOPAD_INT_STAT_AK 0x1687C -#define mmSMU_GPIOPAD_INT_EN 0x1687D -#define mmSMU_GPIOPAD_INT_TYPE 0x1687E -#define mmSMU_GPIOPAD_INT_POLARITY 0x1687F -#define mmROM_CC_BIF_PINSTRAP 0x16880 -#define mmIO_SMUIO_PINSTRAP 0x16881 -#define mmSMUIO_PCC_CONTROL 0x16882 -#define mmSMUIO_PCC_GPIO_SELECT 0x16883 -#define mmSMUIO_GPIO_INT_SELECT 0x16884 -#define mmSMIO_INDEX 0x16885 -#define mmS0_VID_SMIO_CNTL 0x16886 -#define mmS1_VID_SMIO_CNTL 0x16887 -#define mmOPEN_DRAIN_SELECT 0x16888 -#define mmSMIO_ENABLE 0x16889 -#define mmCPL_VDDCR_SOC_IDLE 0x1688A -#define mmROM_SW_SECURE 0x1688B - - -// Registers from GDS block - -#define mmGDS_CONFIG 0x25C0 -#define mmGDS_CNTL_STATUS 0x25C1 -#define mmGDS_ENHANCE2 0x25C2 -#define mmGDS_PROTECTION_FAULT 0x25C3 -#define mmGDS_VM_PROTECTION_FAULT 0x25C4 -#define mmGDS_EDC_CNT 0x25C5 -#define mmGDS_EDC_GRBM_CNT 0x25C6 -#define mmGDS_EDC_OA_DED 0x25C7 -#define mmGDS_DEBUG_CNTL 0x25C8 -#define mmGDS_DEBUG_DATA 0x25C9 -#define mmGDS_DSM_CNTL 0x25CA -#define mmGDS_EDC_OA_PHY_CNT 0x25CB -#define mmGDS_EDC_OA_PIPE_CNT 0x25CC -#define mmGDS_DSM_CNTL2 0x25CD -#define mmGDS_WD_GDS_CSB 0x25CE -#define mmGDS_VMID0_BASE 0x3300 -#define mmGDS_VMID1_BASE 0x3302 -#define mmGDS_VMID2_BASE 0x3304 -#define mmGDS_VMID3_BASE 0x3306 -#define mmGDS_VMID4_BASE 0x3308 -#define mmGDS_VMID5_BASE 0x330A -#define mmGDS_VMID6_BASE 0x330C -#define mmGDS_VMID7_BASE 0x330E -#define mmGDS_VMID8_BASE 0x3310 -#define mmGDS_VMID9_BASE 0x3312 -#define mmGDS_VMID10_BASE 0x3314 -#define mmGDS_VMID11_BASE 0x3316 -#define mmGDS_VMID12_BASE 0x3318 -#define mmGDS_VMID13_BASE 0x331A -#define mmGDS_VMID14_BASE 0x331C -#define mmGDS_VMID15_BASE 0x331E -#define mmGDS_VMID0_SIZE 0x3301 -#define mmGDS_VMID1_SIZE 0x3303 -#define mmGDS_VMID2_SIZE 0x3305 -#define mmGDS_VMID3_SIZE 0x3307 -#define mmGDS_VMID4_SIZE 0x3309 -#define mmGDS_VMID5_SIZE 0x330B -#define mmGDS_VMID6_SIZE 0x330D -#define mmGDS_VMID7_SIZE 0x330F -#define mmGDS_VMID8_SIZE 0x3311 -#define mmGDS_VMID9_SIZE 0x3313 -#define mmGDS_VMID10_SIZE 0x3315 -#define mmGDS_VMID11_SIZE 0x3317 -#define mmGDS_VMID12_SIZE 0x3319 -#define mmGDS_VMID13_SIZE 0x331B -#define mmGDS_VMID14_SIZE 0x331D -#define mmGDS_VMID15_SIZE 0x331F -#define mmGDS_GWS_VMID0 0x3320 -#define mmGDS_GWS_VMID1 0x3321 -#define mmGDS_GWS_VMID2 0x3322 -#define mmGDS_GWS_VMID3 0x3323 -#define mmGDS_GWS_VMID4 0x3324 -#define mmGDS_GWS_VMID5 0x3325 -#define mmGDS_GWS_VMID6 0x3326 -#define mmGDS_GWS_VMID7 0x3327 -#define mmGDS_GWS_VMID8 0x3328 -#define mmGDS_GWS_VMID9 0x3329 -#define mmGDS_GWS_VMID10 0x332A -#define mmGDS_GWS_VMID11 0x332B -#define mmGDS_GWS_VMID12 0x332C -#define mmGDS_GWS_VMID13 0x332D -#define mmGDS_GWS_VMID14 0x332E -#define mmGDS_GWS_VMID15 0x332F -#define mmGDS_OA_VMID0 0x3330 -#define mmGDS_OA_VMID1 0x3331 -#define mmGDS_OA_VMID2 0x3332 -#define mmGDS_OA_VMID3 0x3333 -#define mmGDS_OA_VMID4 0x3334 -#define mmGDS_OA_VMID5 0x3335 -#define mmGDS_OA_VMID6 0x3336 -#define mmGDS_OA_VMID7 0x3337 -#define mmGDS_OA_VMID8 0x3338 -#define mmGDS_OA_VMID9 0x3339 -#define mmGDS_OA_VMID10 0x333A -#define mmGDS_OA_VMID11 0x333B -#define mmGDS_OA_VMID12 0x333C -#define mmGDS_OA_VMID13 0x333D -#define mmGDS_OA_VMID14 0x333E -#define mmGDS_OA_VMID15 0x333F -#define mmGDS_GWS_RESET0 0x3344 -#define mmGDS_GWS_RESET1 0x3345 -#define mmGDS_GWS_RESOURCE_RESET 0x3346 -#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 -#define mmGDS_OA_RESET_MASK 0x3349 -#define mmGDS_OA_RESET 0x334A -#define mmGDS_ENHANCE 0x334B -#define mmGDS_OA_CGPG_RESTORE 0x334C -#define mmGDS_CS_CTXSW_STATUS 0x334D -#define mmGDS_CS_CTXSW_CNT0 0x334E -#define mmGDS_CS_CTXSW_CNT1 0x334F -#define mmGDS_CS_CTXSW_CNT2 0x3350 -#define mmGDS_CS_CTXSW_CNT3 0x3351 -#define mmGDS_GFX_CTXSW_STATUS 0x3352 -#define mmGDS_VS_CTXSW_CNT0 0x3353 -#define mmGDS_VS_CTXSW_CNT1 0x3354 -#define mmGDS_VS_CTXSW_CNT2 0x3355 -#define mmGDS_VS_CTXSW_CNT3 0x3356 -#define mmGDS_PS0_CTXSW_CNT0 0x3357 -#define mmGDS_PS1_CTXSW_CNT0 0x335B -#define mmGDS_PS2_CTXSW_CNT0 0x335F -#define mmGDS_PS3_CTXSW_CNT0 0x3363 -#define mmGDS_PS4_CTXSW_CNT0 0x3367 -#define mmGDS_PS5_CTXSW_CNT0 0x336B -#define mmGDS_PS6_CTXSW_CNT0 0x336F -#define mmGDS_PS7_CTXSW_CNT0 0x3373 -#define mmGDS_PS0_CTXSW_CNT1 0x3358 -#define mmGDS_PS1_CTXSW_CNT1 0x335C -#define mmGDS_PS2_CTXSW_CNT1 0x3360 -#define mmGDS_PS3_CTXSW_CNT1 0x3364 -#define mmGDS_PS4_CTXSW_CNT1 0x3368 -#define mmGDS_PS5_CTXSW_CNT1 0x336C -#define mmGDS_PS6_CTXSW_CNT1 0x3370 -#define mmGDS_PS7_CTXSW_CNT1 0x3374 -#define mmGDS_PS0_CTXSW_CNT2 0x3359 -#define mmGDS_PS1_CTXSW_CNT2 0x335D -#define mmGDS_PS2_CTXSW_CNT2 0x3361 -#define mmGDS_PS3_CTXSW_CNT2 0x3365 -#define mmGDS_PS4_CTXSW_CNT2 0x3369 -#define mmGDS_PS5_CTXSW_CNT2 0x336D -#define mmGDS_PS6_CTXSW_CNT2 0x3371 -#define mmGDS_PS7_CTXSW_CNT2 0x3375 -#define mmGDS_PS0_CTXSW_CNT3 0x335A -#define mmGDS_PS1_CTXSW_CNT3 0x335E -#define mmGDS_PS2_CTXSW_CNT3 0x3362 -#define mmGDS_PS3_CTXSW_CNT3 0x3366 -#define mmGDS_PS4_CTXSW_CNT3 0x336A -#define mmGDS_PS5_CTXSW_CNT3 0x336E -#define mmGDS_PS6_CTXSW_CNT3 0x3372 -#define mmGDS_PS7_CTXSW_CNT3 0x3376 -#define mmGDS_GS_CTXSW_CNT0 0x3377 -#define mmGDS_GS_CTXSW_CNT1 0x3378 -#define mmGDS_GS_CTXSW_CNT2 0x3379 -#define mmGDS_GS_CTXSW_CNT3 0x337A -#define mmGDS_RD_ADDR 0xC400 -#define mmGDS_RD_DATA 0xC401 -#define mmGDS_RD_BURST_ADDR 0xC402 -#define mmGDS_RD_BURST_COUNT 0xC403 -#define mmGDS_RD_BURST_DATA 0xC404 -#define mmGDS_WR_ADDR 0xC405 -#define mmGDS_WR_DATA 0xC406 -#define mmGDS_WR_BURST_ADDR 0xC407 -#define mmGDS_WR_BURST_DATA 0xC408 -#define mmGDS_WRITE_COMPLETE 0xC409 -#define mmGDS_ATOM_CNTL 0xC40A -#define mmGDS_ATOM_COMPLETE 0xC40B -#define mmGDS_ATOM_BASE 0xC40C -#define mmGDS_ATOM_SIZE 0xC40D -#define mmGDS_ATOM_OFFSET0 0xC40E -#define mmGDS_ATOM_OFFSET1 0xC40F -#define mmGDS_ATOM_DST 0xC410 -#define mmGDS_ATOM_OP 0xC411 -#define mmGDS_ATOM_SRC0 0xC412 -#define mmGDS_ATOM_SRC0_U 0xC413 -#define mmGDS_ATOM_SRC1 0xC414 -#define mmGDS_ATOM_SRC1_U 0xC415 -#define mmGDS_ATOM_READ0 0xC416 -#define mmGDS_ATOM_READ0_U 0xC417 -#define mmGDS_ATOM_READ1 0xC418 -#define mmGDS_ATOM_READ1_U 0xC419 -#define mmGDS_GWS_RESOURCE_CNTL 0xC41A -#define mmGDS_GWS_RESOURCE 0xC41B -#define mmGDS_GWS_RESOURCE_CNT 0xC41C -#define mmGDS_OA_CNTL 0xC41D -#define mmGDS_OA_COUNTER 0xC41E -#define mmGDS_OA_ADDRESS 0xC41F -#define mmGDS_OA_INCDEC 0xC420 -#define mmGDS_OA_RING_SIZE 0xC421 -#define mmGDS_PERFCOUNTER0_LO 0xD280 -#define mmGDS_PERFCOUNTER1_LO 0xD282 -#define mmGDS_PERFCOUNTER2_LO 0xD284 -#define mmGDS_PERFCOUNTER3_LO 0xD286 -#define mmGDS_PERFCOUNTER0_HI 0xD281 -#define mmGDS_PERFCOUNTER1_HI 0xD283 -#define mmGDS_PERFCOUNTER2_HI 0xD285 -#define mmGDS_PERFCOUNTER3_HI 0xD287 -#define mmGDS_PERFCOUNTER0_SELECT 0xDA80 -#define mmGDS_PERFCOUNTER1_SELECT 0xDA81 -#define mmGDS_PERFCOUNTER2_SELECT 0xDA82 -#define mmGDS_PERFCOUNTER3_SELECT 0xDA83 -#define mmGDS_PERFCOUNTER0_SELECT1 0xDA84 -#define mmCGTT_GDS_CLK_CTRL 0xF0A0 - - -// Registers from CB block - -#define mmCB_HW_CONTROL 0x2680 -#define mmCB_HW_CONTROL_1 0x2681 -#define mmCB_HW_CONTROL_2 0x2682 -#define mmCB_HW_CONTROL_3 0x2683 -#define mmCB_HW_MEM_ARBITER_RD 0x2686 -#define mmCB_HW_MEM_ARBITER_WR 0x2687 -#define mmCB_DCC_CONFIG 0x2688 -#define mmCB_DEBUG_BUS_1 0x2699 -#define mmCB_DEBUG_BUS_2 0x269A -#define mmCB_DEBUG_BUS_3 0x269B -#define mmCB_DEBUG_BUS_4 0x269C -#define mmCB_DEBUG_BUS_5 0x269D -#define mmCB_DEBUG_BUS_6 0x269E -#define mmCB_DEBUG_BUS_7 0x269F -#define mmCB_DEBUG_BUS_8 0x26A0 -#define mmCB_DEBUG_BUS_9 0x26A1 -#define mmCB_DEBUG_BUS_10 0x26A2 -#define mmCB_DEBUG_BUS_11 0x26A3 -#define mmCB_DEBUG_BUS_12 0x26A4 -#define mmCB_DEBUG_BUS_13 0x26A5 -#define mmCB_DEBUG_BUS_14 0x26A6 -#define mmCB_DEBUG_BUS_15 0x26A7 -#define mmCB_DEBUG_BUS_16 0x26A8 -#define mmCB_DEBUG_BUS_17 0x26A9 -#define mmCB_DEBUG_BUS_18 0x26AA -#define mmCB_DEBUG_BUS_19 0x26AB -#define mmCB_DEBUG_BUS_20 0x26AC -#define mmCB_DEBUG_BUS_21 0x26AD -#define mmCB_DEBUG_BUS_22 0x26AE -#define mmCB_BLEND_RED 0xA105 -#define mmCB_BLEND_GREEN 0xA106 -#define mmCB_BLEND_BLUE 0xA107 -#define mmCB_BLEND_ALPHA 0xA108 -#define mmCB_DCC_CONTROL 0xA109 -#define mmCB_COLOR_CONTROL 0xA202 -#define mmCB_BLEND0_CONTROL 0xA1E0 -#define mmCB_BLEND1_CONTROL 0xA1E1 -#define mmCB_BLEND2_CONTROL 0xA1E2 -#define mmCB_BLEND3_CONTROL 0xA1E3 -#define mmCB_BLEND4_CONTROL 0xA1E4 -#define mmCB_BLEND5_CONTROL 0xA1E5 -#define mmCB_BLEND6_CONTROL 0xA1E6 -#define mmCB_BLEND7_CONTROL 0xA1E7 -#define mmCB_MRT0_EPITCH 0xA1E8 -#define mmCB_MRT1_EPITCH 0xA1E9 -#define mmCB_MRT2_EPITCH 0xA1EA -#define mmCB_MRT3_EPITCH 0xA1EB -#define mmCB_MRT4_EPITCH 0xA1EC -#define mmCB_MRT5_EPITCH 0xA1ED -#define mmCB_MRT6_EPITCH 0xA1EE -#define mmCB_MRT7_EPITCH 0xA1EF -#define mmCB_COLOR0_BASE 0xA318 -#define mmCB_COLOR1_BASE 0xA327 -#define mmCB_COLOR2_BASE 0xA336 -#define mmCB_COLOR3_BASE 0xA345 -#define mmCB_COLOR4_BASE 0xA354 -#define mmCB_COLOR5_BASE 0xA363 -#define mmCB_COLOR6_BASE 0xA372 -#define mmCB_COLOR7_BASE 0xA381 -#define mmCB_COLOR0_BASE_EXT 0xA319 -#define mmCB_COLOR1_BASE_EXT 0xA328 -#define mmCB_COLOR2_BASE_EXT 0xA337 -#define mmCB_COLOR3_BASE_EXT 0xA346 -#define mmCB_COLOR4_BASE_EXT 0xA355 -#define mmCB_COLOR5_BASE_EXT 0xA364 -#define mmCB_COLOR6_BASE_EXT 0xA373 -#define mmCB_COLOR7_BASE_EXT 0xA382 -#define mmCB_COLOR0_ATTRIB2 0xA31A -#define mmCB_COLOR1_ATTRIB2 0xA329 -#define mmCB_COLOR2_ATTRIB2 0xA338 -#define mmCB_COLOR3_ATTRIB2 0xA347 -#define mmCB_COLOR4_ATTRIB2 0xA356 -#define mmCB_COLOR5_ATTRIB2 0xA365 -#define mmCB_COLOR6_ATTRIB2 0xA374 -#define mmCB_COLOR7_ATTRIB2 0xA383 -#define mmCB_COLOR0_VIEW 0xA31B -#define mmCB_COLOR1_VIEW 0xA32A -#define mmCB_COLOR2_VIEW 0xA339 -#define mmCB_COLOR3_VIEW 0xA348 -#define mmCB_COLOR4_VIEW 0xA357 -#define mmCB_COLOR5_VIEW 0xA366 -#define mmCB_COLOR6_VIEW 0xA375 -#define mmCB_COLOR7_VIEW 0xA384 -#define mmCB_COLOR0_INFO 0xA31C -#define mmCB_COLOR1_INFO 0xA32B -#define mmCB_COLOR2_INFO 0xA33A -#define mmCB_COLOR3_INFO 0xA349 -#define mmCB_COLOR4_INFO 0xA358 -#define mmCB_COLOR5_INFO 0xA367 -#define mmCB_COLOR6_INFO 0xA376 -#define mmCB_COLOR7_INFO 0xA385 -#define mmCB_COLOR0_ATTRIB 0xA31D -#define mmCB_COLOR1_ATTRIB 0xA32C -#define mmCB_COLOR2_ATTRIB 0xA33B -#define mmCB_COLOR3_ATTRIB 0xA34A -#define mmCB_COLOR4_ATTRIB 0xA359 -#define mmCB_COLOR5_ATTRIB 0xA368 -#define mmCB_COLOR6_ATTRIB 0xA377 -#define mmCB_COLOR7_ATTRIB 0xA386 -#define mmCB_COLOR0_DCC_CONTROL 0xA31E -#define mmCB_COLOR1_DCC_CONTROL 0xA32D -#define mmCB_COLOR2_DCC_CONTROL 0xA33C -#define mmCB_COLOR3_DCC_CONTROL 0xA34B -#define mmCB_COLOR4_DCC_CONTROL 0xA35A -#define mmCB_COLOR5_DCC_CONTROL 0xA369 -#define mmCB_COLOR6_DCC_CONTROL 0xA378 -#define mmCB_COLOR7_DCC_CONTROL 0xA387 -#define mmCB_COLOR0_CMASK 0xA31F -#define mmCB_COLOR1_CMASK 0xA32E -#define mmCB_COLOR2_CMASK 0xA33D -#define mmCB_COLOR3_CMASK 0xA34C -#define mmCB_COLOR4_CMASK 0xA35B -#define mmCB_COLOR5_CMASK 0xA36A -#define mmCB_COLOR6_CMASK 0xA379 -#define mmCB_COLOR7_CMASK 0xA388 -#define mmCB_COLOR0_CMASK_BASE_EXT 0xA320 -#define mmCB_COLOR1_CMASK_BASE_EXT 0xA32F -#define mmCB_COLOR2_CMASK_BASE_EXT 0xA33E -#define mmCB_COLOR3_CMASK_BASE_EXT 0xA34D -#define mmCB_COLOR4_CMASK_BASE_EXT 0xA35C -#define mmCB_COLOR5_CMASK_BASE_EXT 0xA36B -#define mmCB_COLOR6_CMASK_BASE_EXT 0xA37A -#define mmCB_COLOR7_CMASK_BASE_EXT 0xA389 -#define mmCB_COLOR0_FMASK 0xA321 -#define mmCB_COLOR1_FMASK 0xA330 -#define mmCB_COLOR2_FMASK 0xA33F -#define mmCB_COLOR3_FMASK 0xA34E -#define mmCB_COLOR4_FMASK 0xA35D -#define mmCB_COLOR5_FMASK 0xA36C -#define mmCB_COLOR6_FMASK 0xA37B -#define mmCB_COLOR7_FMASK 0xA38A -#define mmCB_COLOR0_FMASK_BASE_EXT 0xA322 -#define mmCB_COLOR1_FMASK_BASE_EXT 0xA331 -#define mmCB_COLOR2_FMASK_BASE_EXT 0xA340 -#define mmCB_COLOR3_FMASK_BASE_EXT 0xA34F -#define mmCB_COLOR4_FMASK_BASE_EXT 0xA35E -#define mmCB_COLOR5_FMASK_BASE_EXT 0xA36D -#define mmCB_COLOR6_FMASK_BASE_EXT 0xA37C -#define mmCB_COLOR7_FMASK_BASE_EXT 0xA38B -#define mmCB_COLOR0_CLEAR_WORD0 0xA323 -#define mmCB_COLOR1_CLEAR_WORD0 0xA332 -#define mmCB_COLOR2_CLEAR_WORD0 0xA341 -#define mmCB_COLOR3_CLEAR_WORD0 0xA350 -#define mmCB_COLOR4_CLEAR_WORD0 0xA35F -#define mmCB_COLOR5_CLEAR_WORD0 0xA36E -#define mmCB_COLOR6_CLEAR_WORD0 0xA37D -#define mmCB_COLOR7_CLEAR_WORD0 0xA38C -#define mmCB_COLOR0_CLEAR_WORD1 0xA324 -#define mmCB_COLOR1_CLEAR_WORD1 0xA333 -#define mmCB_COLOR2_CLEAR_WORD1 0xA342 -#define mmCB_COLOR3_CLEAR_WORD1 0xA351 -#define mmCB_COLOR4_CLEAR_WORD1 0xA360 -#define mmCB_COLOR5_CLEAR_WORD1 0xA36F -#define mmCB_COLOR6_CLEAR_WORD1 0xA37E -#define mmCB_COLOR7_CLEAR_WORD1 0xA38D -#define mmCB_COLOR0_DCC_BASE 0xA325 -#define mmCB_COLOR1_DCC_BASE 0xA334 -#define mmCB_COLOR2_DCC_BASE 0xA343 -#define mmCB_COLOR3_DCC_BASE 0xA352 -#define mmCB_COLOR4_DCC_BASE 0xA361 -#define mmCB_COLOR5_DCC_BASE 0xA370 -#define mmCB_COLOR6_DCC_BASE 0xA37F -#define mmCB_COLOR7_DCC_BASE 0xA38E -#define mmCB_COLOR0_DCC_BASE_EXT 0xA326 -#define mmCB_COLOR1_DCC_BASE_EXT 0xA335 -#define mmCB_COLOR2_DCC_BASE_EXT 0xA344 -#define mmCB_COLOR3_DCC_BASE_EXT 0xA353 -#define mmCB_COLOR4_DCC_BASE_EXT 0xA362 -#define mmCB_COLOR5_DCC_BASE_EXT 0xA371 -#define mmCB_COLOR6_DCC_BASE_EXT 0xA380 -#define mmCB_COLOR7_DCC_BASE_EXT 0xA38F -#define mmCB_TARGET_MASK 0xA08E -#define mmCB_SHADER_MASK 0xA08F -#define mmCB_PERFCOUNTER0_LO 0xD406 -#define mmCB_PERFCOUNTER1_LO 0xD408 -#define mmCB_PERFCOUNTER2_LO 0xD40A -#define mmCB_PERFCOUNTER3_LO 0xD40C -#define mmCB_PERFCOUNTER0_HI 0xD407 -#define mmCB_PERFCOUNTER1_HI 0xD409 -#define mmCB_PERFCOUNTER2_HI 0xD40B -#define mmCB_PERFCOUNTER3_HI 0xD40D -#define mmCB_PERFCOUNTER_FILTER 0xDC00 -#define mmCB_PERFCOUNTER0_SELECT 0xDC01 -#define mmCB_PERFCOUNTER0_SELECT1 0xDC02 -#define mmCB_PERFCOUNTER1_SELECT 0xDC03 -#define mmCB_PERFCOUNTER2_SELECT 0xDC04 -#define mmCB_PERFCOUNTER3_SELECT 0xDC05 -#define mmCB_CGTT_SCLK_CTRL 0xF0A8 - - -// Registers from SC block - - -// Registers from TC block - - -// Registers from GC_CAC block - -#define mmGC_CAC_CTRL_1 0x3284 -#define mmGC_CAC_CTRL_2 0x3285 -#define mmGC_CAC_CGTT_CLK_CTRL 0x3286 -#define mmGC_CAC_AGGR_LOWER 0x3287 -#define mmGC_CAC_AGGR_UPPER 0x3288 -#define mmGC_CAC_SOFT_CTRL 0x328D -#define mmGC_DIDT_CTRL0 0x328E -#define mmGC_DIDT_CTRL1 0x328F -#define mmGC_DIDT_CTRL2 0x3290 -#define mmGC_DIDT_WEIGHT 0x3291 -#define mmGC_DIDT_WEIGHT_1 0x3292 -#define mmGC_EDC_CTRL 0x3293 -#define mmGC_EDC_THRESHOLD 0x3294 -#define mmGC_EDC_STATUS 0x3295 -#define mmGC_EDC_OVERFLOW 0x3296 -#define mmGC_EDC_ROLLING_POWER_DELTA 0x3297 -#define mmGC_DIDT_DROOP_CTRL 0x3298 -#define mmGC_EDC_DROOP_CTRL 0x3299 -#define mmGC_CAC_IND_INDEX 0x329A -#define mmGC_CAC_IND_DATA 0x329B -#define mmSE_CAC_CGTT_CLK_CTRL 0x329C -#define mmSE_CAC_IND_INDEX 0x329D -#define mmSE_CAC_IND_DATA 0x329E - - -// Registers from RLC block - -#define mmRLC_GPM_PERF_COUNT_0 0xC140 -#define mmRLC_GPM_PERF_COUNT_1 0xC141 -#define mmRLC_PERFCOUNTER0_LO 0xD480 -#define mmRLC_PERFCOUNTER1_LO 0xD482 -#define mmRLC_PERFCOUNTER0_HI 0xD481 -#define mmRLC_PERFCOUNTER1_HI 0xD483 -#define mmRLC_PERFMON_CLK_CNTL 0xDCBF -#define mmRLC_PERFMON_CNTL 0xDCC0 -#define mmRLC_PERFCOUNTER0_SELECT 0xDCC1 -#define mmRLC_PERFCOUNTER1_SELECT 0xDCC2 -#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0xDCC3 -#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0xDCC4 -#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0xDCC5 -#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0xDCC6 -#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0xDCC7 -#define mmRLC_SPM_PERFMON_CNTL 0xDC80 -#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xDC81 -#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xDC82 -#define mmRLC_SPM_PERFMON_RING_SIZE 0xDC83 -#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xDC84 -#define mmRLC_SPM_SE_MUXSEL_ADDR 0xDC85 -#define mmRLC_SPM_SE_MUXSEL_DATA 0xDC86 -#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xDC87 -#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xDC88 -#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xDC89 -#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xDC8A -#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xDC8B -#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xDC8C -#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xDC8D -#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xDC8E -#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xDC90 -#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xDC91 -#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xDC92 -#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xDC93 -#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xDC94 -#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xDC95 -#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xDC96 -#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xDC97 -#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xDC98 -#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xDC9A -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xDC9B -#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xDC9C -#define mmRLC_SPM_RING_RDPTR 0xDC9D -#define mmRLC_SPM_SEGMENT_THRESHOLD 0xDC9E -#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xDC9F -#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xDCA0 -#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xDCA1 -#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xDCA2 -#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0xDCA3 -#define mmRLC_CNTL 0xEC00 -#define mmRLC_DEBUG_SELECT 0xEC01 -#define mmRLC_DEBUG 0xEC02 -#define mmRLC_STAT 0xEC04 -#define mmRLC_INT_STAT 0xEC18 -#define mmRLC_SAFE_MODE 0xEC05 -#define mmRLC_MEM_SLP_CNTL 0xEC06 -#define mmSMU_RLC_RESPONSE 0xEC07 -#define mmRLC_RLCV_SAFE_MODE 0xEC08 -#define mmRLC_SMU_SAFE_MODE 0xEC09 -#define mmRLC_RLCV_COMMAND 0xEC0A -#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0xEC0C -#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0xEC0D -#define mmRLC_GPM_TIMER_INT_0 0xEC0E -#define mmRLC_GPM_TIMER_INT_1 0xEC0F -#define mmRLC_GPM_TIMER_INT_2 0xEC10 -#define mmRLC_GPM_TIMER_INT_3 0xEC15 -#define mmRLC_GPM_TIMER_CTRL 0xEC11 -#define mmRLC_GPM_TIMER_STAT 0xEC13 -#define mmRLC_LB_CNTL 0xEC19 -#define mmRLC_LB_CNTR_MAX 0xEC12 -#define mmRLC_LB_CNTR_INIT 0xEC1B -#define mmRLC_LOAD_BALANCE_CNTR 0xEC1C -#define mmRLC_JUMP_TABLE_RESTORE 0xEC1E -#define mmRLC_PG_DELAY_2 0xEC1F -#define mmRLC_GPM_DEBUG_INST_HIST 0xEC14 -#define mmRLC_GPM_DEBUG_SELECT 0xEC20 -#define mmRLC_GPM_DEBUG 0xEC21 -#define mmRLC_GPM_DEBUG_INST_A 0xEC22 -#define mmRLC_GPM_DEBUG_INST_B 0xEC23 -#define mmRLC_GPM_DEBUG_INST_ADDR 0xEC1D -#define mmRLC_SEMAPHORE_0 0xECC7 -#define mmRLC_SEMAPHORE_1 0xECC8 -#define mmRLC_RLCV_SPARE_INT 0xEF30 -#define mmRLC_GPU_CLOCK_COUNT_LSB 0xEC24 -#define mmRLC_GPU_CLOCK_COUNT_MSB 0xEC25 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0xEC26 -#define mmRLC_UCODE_CNTL 0xEC27 -#define mmRLC_GPM_STAT 0xEC40 -#define mmRLC_GPU_CLOCK_32_RES_SEL 0xEC41 -#define mmRLC_GPU_CLOCK_32 0xEC42 -#define mmRLC_PG_CNTL 0xEC43 -#define mmRLC_GPM_THREAD_PRIORITY 0xEC44 -#define mmRLC_GPM_THREAD_ENABLE 0xEC45 -#define mmRLC_CGTT_MGCG_OVERRIDE 0xEC48 -#define mmRLC_CGCG_CGLS_CTRL 0xEC49 -#define mmRLC_CGCG_RAMP_CTRL 0xEC4A -#define mmRLC_CGCG_CGLS_CTRL_3D 0xECC5 -#define mmRLC_CGCG_RAMP_CTRL_3D 0xECC6 -#define mmRLC_DYN_PG_STATUS 0xEC4B -#define mmRLC_DYN_PG_REQUEST 0xEC4C -#define mmRLC_PG_DELAY 0xEC4D -#define mmRLC_CU_STATUS 0xEC4E -#define mmRLC_LB_INIT_CU_MASK 0xEC4F -#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0xEC50 -#define mmRLC_LB_PARAMS 0xEC51 -#define mmRLC_THREAD1_DELAY 0xEC52 -#define mmRLC_LB_THR_CONFIG_1 0xECBF -#define mmRLC_LB_THR_CONFIG_2 0xECB8 -#define mmRLC_LB_THR_CONFIG_3 0xECB9 -#define mmRLC_LB_THR_CONFIG_4 0xECBA -#define mmRLC_LB_DEBUG_1 0xECBB -#define mmRLC_PG_ALWAYS_ON_CU_MASK 0xEC53 -#define mmRLC_MAX_PG_CU 0xEC54 -#define mmRLC_AUTO_PG_CTRL 0xEC55 -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0xEC56 -#define mmRLC_SERDES_RD_MASTER_INDEX 0xEC59 -#define mmRLC_SERDES_RD_DATA_0 0xEC5A -#define mmRLC_SERDES_RD_DATA_1 0xEC5B -#define mmRLC_SERDES_RD_DATA_2 0xEC5C -#define mmRLC_SERDES_WR_CU_MASTER_MASK 0xEC5D -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xEC5E -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1 0xEC16 -#define mmRLC_SERDES_NONCU_MASTER_BUSY_1 0xEC17 -#define mmRLC_SERDES_WR_CTRL 0xEC5F -#define mmRLC_SERDES_WR_DATA 0xEC60 -#define mmRLC_SERDES_CU_MASTER_BUSY 0xEC61 -#define mmRLC_SERDES_NONCU_MASTER_BUSY 0xEC62 -#define mmRLC_GPM_GENERAL_0 0xEC63 -#define mmRLC_GPM_GENERAL_1 0xEC64 -#define mmRLC_GPM_GENERAL_2 0xEC65 -#define mmRLC_GPM_GENERAL_3 0xEC66 -#define mmRLC_GPM_GENERAL_4 0xEC67 -#define mmRLC_GPM_GENERAL_5 0xEC68 -#define mmRLC_GPM_GENERAL_6 0xEC69 -#define mmRLC_GPM_GENERAL_7 0xEC6A -#define mmRLC_GPM_SCRATCH_ADDR 0xEC6C -#define mmRLC_GPM_SCRATCH_DATA 0xEC6D -#define mmRLC_STATIC_PG_STATUS 0xEC6E -#define mmRLC_GPR_REG1 0xEC79 -#define mmRLC_GPR_REG2 0xEC7A -#define mmRLC_MGCG_CTRL 0xEC1A -#define mmRLC_GPM_THREAD_RESET 0xEC28 -#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0xEC29 -#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0xEC2A -#define mmRLC_FIREWALL_VIOLATION 0xEC2B -#define mmRLC_SPM_MC_CNTL 0xEC71 -#define mmRLC_SPM_INT_CNTL 0xEC72 -#define mmRLC_SPM_INT_STATUS 0xEC73 -#define mmRLC_SPM_DEBUG_SELECT 0xEC74 -#define mmRLC_SPM_DEBUG 0xEC75 -#define mmRLC_SMU_MESSAGE 0xEC76 -#define mmRLC_GPM_LOG_SIZE 0xEC77 -#define mmRLC_GPM_LOG_CONT 0xEC7B -#define mmRLC_PG_DELAY_3 0xEC78 -#define mmRLC_GPM_INT_DISABLE_TH0 0xEC7C -#define mmRLC_GPM_INT_DISABLE_TH1 0xEC7D -#define mmRLC_GPM_INT_FORCE_TH0 0xEC7E -#define mmRLC_GPM_INT_FORCE_TH1 0xEC7F -#define mmRLC_SRM_CNTL 0xEC80 -#define mmRLC_SRM_DEBUG_SELECT 0xEC81 -#define mmRLC_SRM_DEBUG 0xEC82 -#define mmRLC_SRM_ARAM_ADDR 0xEC83 -#define mmRLC_SRM_ARAM_DATA 0xEC84 -#define mmRLC_SRM_DRAM_ADDR 0xEC85 -#define mmRLC_SRM_DRAM_DATA 0xEC86 -#define mmRLC_SRM_GPM_COMMAND 0xEC87 -#define mmRLC_SRM_GPM_COMMAND_STATUS 0xEC88 -#define mmRLC_SRM_RLCV_COMMAND 0xEC89 -#define mmRLC_SRM_RLCV_COMMAND_STATUS 0xEC8A -#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xEC8B -#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0xEC8C -#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0xEC8D -#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0xEC8E -#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xEC8F -#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0xEC90 -#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0xEC91 -#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0xEC92 -#define mmRLC_SRM_INDEX_CNTL_DATA_0 0xEC93 -#define mmRLC_SRM_INDEX_CNTL_DATA_1 0xEC94 -#define mmRLC_SRM_INDEX_CNTL_DATA_2 0xEC95 -#define mmRLC_SRM_INDEX_CNTL_DATA_3 0xEC96 -#define mmRLC_SRM_INDEX_CNTL_DATA_4 0xEC97 -#define mmRLC_SRM_INDEX_CNTL_DATA_5 0xEC98 -#define mmRLC_SRM_INDEX_CNTL_DATA_6 0xEC99 -#define mmRLC_SRM_INDEX_CNTL_DATA_7 0xEC9A -#define mmRLC_SRM_STAT 0xEC9B -#define mmRLC_SRM_GPM_ABORT 0xEC9C -#define mmRLC_CSIB_ADDR_LO 0xECA2 -#define mmRLC_CSIB_ADDR_HI 0xECA3 -#define mmRLC_CSIB_LENGTH 0xECA4 -#define mmRLC_SMU_COMMAND 0xECA9 -#define mmRLC_CP_SCHEDULERS 0xECAA -#define mmRLC_SMU_ARGUMENT_1 0xECAB -#define mmRLC_SMU_ARGUMENT_2 0xECAC -#define mmRLC_GPM_GENERAL_8 0xECAD -#define mmRLC_GPM_GENERAL_9 0xECAE -#define mmRLC_GPM_GENERAL_10 0xECAF -#define mmRLC_GPM_GENERAL_11 0xECB0 -#define mmRLC_GPM_GENERAL_12 0xECB1 -#define mmRLC_UTCL2_CNTL 0xECD9 -#define mmRLC_GPM_UTCL1_CNTL_0 0xECB2 -#define mmRLC_GPM_UTCL1_CNTL_1 0xECB3 -#define mmRLC_GPM_UTCL1_CNTL_2 0xECB4 -#define mmRLC_SPM_UTCL1_CNTL 0xECB5 -#define mmRLC_PREWALKER_UTCL1_CNTL 0xECCD -#define mmRLC_PREWALKER_UTCL1_TRIG 0xECCE -#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0xECCF -#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0xECD0 -#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0xECD1 -#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0xECD2 -#define mmRLC_DSM_TRIG 0xECD3 -#define mmRLC_UTCL1_STATUS_2 0xECB6 -#define mmRLC_SPM_UTCL1_ERROR_1 0xECBC -#define mmRLC_SPM_UTCL1_ERROR_2 0xECBD -#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0xECBE -#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0xECC0 -#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0xECC1 -#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0xECC2 -#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0xECC3 -#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0xECC4 -#define mmRLC_CP_EOF_INT 0xECCA -#define mmRLC_CP_EOF_INT_CNT 0xECCB -#define mmRLC_R2I_CNTL_0 0xECD5 -#define mmRLC_R2I_CNTL_1 0xECD6 -#define mmRLC_R2I_CNTL_2 0xECD7 -#define mmRLC_R2I_CNTL_3 0xECD8 -#define mmRLC_SPARE_INT 0xECCC -#define mmRLC_UTCL1_STATUS 0xECD4 -#define mmRLC_LBPW_CU_STAT 0xECDA -#define mmRLC_DS_CNTL 0xECDB -#define mmCGTT_RLC_CLK_CTRL 0xF0B5 -#define mmRLC_GFX_RM_CNTL 0xF0B6 -#define mmRLC_CLK_CNTL 0xFB31 -#define mmRLC_GPM_UCODE_ADDR 0xF83C -#define mmRLC_GPM_UCODE_DATA 0xF83D -#define mmRLC_GC_FUSESTRAP_RELOAD 0xFB07 -#define mmRLC_GC_FUSESTRAP_GC_WRITE_DISABLE 0xFB08 -#define mmRLC_GC_FUSESTRAP_CC_WRITE_DISABLE 0xFB09 -#define mmRLC_GC_FUSESTRAP_DEBE_0 0xFB0A -#define mmRLC_GC_FUSESTRAP_DEBE_1 0xFB0B -#define mmRLC_GC_FUSESTRAP_DEBE_2 0xFB0C -#define mmRLC_GC_FUSESTRAP_DEBE_3 0xFB0D -#define mmRLC_GC_FUSESTRAP_DPFP_RATE 0xFB0E -#define mmRLC_GC_FUSESTRAP_DISABLE_EDC 0xFB0F -#define mmRLC_HYP_SEMAPHORE_2 0xFB2E -#define mmRLC_HYP_SEMAPHORE_3 0xFB2F -#define mmRLC_GPU_IOV_VF_ENABLE 0xFB00 -#define mmRLC_GPU_IOV_CFG_REG1 0xFB35 -#define mmRLC_GPU_IOV_CFG_REG2 0xFB36 -#define mmRLC_GPU_IOV_SCH_BLOCK 0xFB34 -#define mmRLC_GPU_IOV_CFG_REG6 0xFB06 -#define mmRLC_GPU_IOV_CFG_REG8 0xFB20 -#define mmRLC_GPU_IOV_UCODE_ADDR 0xFB42 -#define mmRLC_GPU_IOV_UCODE_DATA 0xFB43 -#define mmRLC_GPU_IOV_SCRATCH_ADDR 0xFB44 -#define mmRLC_GPU_IOV_SCRATCH_DATA 0xFB45 -#define mmRLC_GPU_IOV_F32_CNTL 0xFB46 -#define mmRLC_GPU_IOV_F32_RESET 0xFB47 -#define mmRLC_GPU_IOV_SDMA0_STATUS 0xFB48 -#define mmRLC_GPU_IOV_SDMA1_STATUS 0xFB49 -#define mmRLC_GPU_IOV_SMU_RESPONSE 0xFB4A -#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0xFB4C -#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0xFB50 -#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0xFB51 -#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0xFB37 -#define mmRLC_GPU_IOV_SCH_0 0xFB38 -#define mmRLC_GPU_IOV_SCH_1 0xFB3B -#define mmRLC_GPU_IOV_SCH_2 0xFB3C -#define mmRLC_GPU_IOV_SCH_3 0xFB3A -#define mmRLC_GPU_IOV_RLC_RESPONSE 0xFB4D -#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0xFB39 -#define mmRLC_RLCV_TIMER_INT_0 0xFB25 -#define mmRLC_RLCV_TIMER_CTRL 0xFB26 -#define mmRLC_RLCV_TIMER_STAT 0xFB27 -#define mmRLC_GPU_IOV_INT_DISABLE 0xFB4E -#define mmRLC_GPU_IOV_INT_FORCE 0xFB4F -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0xFB2A -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0xFB2B -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0xFB2C -#define mmRLC_GPU_IOV_VF_MASK 0xFB2D -#define mmRLC_REG_PRIV_LEVEL_A 0xFF00 -#define mmRLC_REG_PRIV_LEVEL_B 0xFF01 -#define mmRLC_REG_PRIV_LEVEL_C 0xFF02 -#define mmRLC_REG_PRIV_LEVEL_D 0xFF03 -#define mmRLC_REG_PRIV_LEVEL_E 0xFF04 -#define mmRLC_REG_PRIV_LEVEL_F 0xFF05 -#define mmRLC_REG_PRIV_LEVEL_G 0xFF06 -#define mmRLC_REG_PRIV_LEVEL_H 0xFF07 -#define mmRLC_REG_PRIV_LEVEL_I 0xFF08 -#define mmRLC_REG_PRIV_LEVEL_J 0xFF09 -#define mmRLC_REG_PRIV_LEVEL_K 0xFF0A -#define mmRLC_REG_PRIV_LEVEL_L 0xFF0B -#define mmRLC_REG_PRIV_LEVEL_M 0xFF0C -#define mmRLC_REG_PRIV_LEVEL_N 0xFF0D -#define mmRLC_REG_PRIV_LEVEL_O 0xFF0E -#define mmRLC_REG_PRIV_LEVEL_P 0xFF0F -#define mmRLC_REG_SEC_INT_STATUS 0xFF10 -#define mmRLC_FWL_FIRST_VIOL_ADDR 0xFF11 - - -// Registers from SPI block - -#define mmSPI_PS_MAX_WAVE_ID 0x243A -#define mmSPI_START_PHASE 0x243B -#define mmSPI_GFX_CNTL 0x243C -#define mmSPI_DEBUG_CNTL 0x2441 -#define mmSPI_DEBUG_READ 0x2442 -#define mmSPI_DSM_CNTL 0x2443 -#define mmSPI_DSM_CNTL2 0x2444 -#define mmSPI_EDC_CNT 0x2445 -#define mmSPI_DEBUG_BUSY 0x2450 -#define mmSPI_CONFIG_PS_CU_EN 0x2452 -#define mmSPI_WF_LIFETIME_CNTL 0x24AA -#define mmSPI_WF_LIFETIME_LIMIT_0 0x24AB -#define mmSPI_WF_LIFETIME_LIMIT_1 0x24AC -#define mmSPI_WF_LIFETIME_LIMIT_2 0x24AD -#define mmSPI_WF_LIFETIME_LIMIT_3 0x24AE -#define mmSPI_WF_LIFETIME_LIMIT_4 0x24AF -#define mmSPI_WF_LIFETIME_LIMIT_5 0x24B0 -#define mmSPI_WF_LIFETIME_LIMIT_6 0x24B1 -#define mmSPI_WF_LIFETIME_LIMIT_7 0x24B2 -#define mmSPI_WF_LIFETIME_LIMIT_8 0x24B3 -#define mmSPI_WF_LIFETIME_LIMIT_9 0x24B4 -#define mmSPI_WF_LIFETIME_STATUS_0 0x24B5 -#define mmSPI_WF_LIFETIME_STATUS_1 0x24B6 -#define mmSPI_WF_LIFETIME_STATUS_2 0x24B7 -#define mmSPI_WF_LIFETIME_STATUS_3 0x24B8 -#define mmSPI_WF_LIFETIME_STATUS_4 0x24B9 -#define mmSPI_WF_LIFETIME_STATUS_5 0x24BA -#define mmSPI_WF_LIFETIME_STATUS_6 0x24BB -#define mmSPI_WF_LIFETIME_STATUS_7 0x24BC -#define mmSPI_WF_LIFETIME_STATUS_8 0x24BD -#define mmSPI_WF_LIFETIME_STATUS_9 0x24BE -#define mmSPI_WF_LIFETIME_STATUS_10 0x24BF -#define mmSPI_WF_LIFETIME_STATUS_11 0x24C0 -#define mmSPI_WF_LIFETIME_STATUS_12 0x24C1 -#define mmSPI_WF_LIFETIME_STATUS_13 0x24C2 -#define mmSPI_WF_LIFETIME_STATUS_14 0x24C3 -#define mmSPI_WF_LIFETIME_STATUS_15 0x24C4 -#define mmSPI_WF_LIFETIME_STATUS_16 0x24C5 -#define mmSPI_WF_LIFETIME_STATUS_17 0x24C6 -#define mmSPI_WF_LIFETIME_STATUS_18 0x24C7 -#define mmSPI_WF_LIFETIME_STATUS_19 0x24C8 -#define mmSPI_WF_LIFETIME_STATUS_20 0x24C9 -#define mmSPI_WF_LIFETIME_DEBUG 0x24CA -#define mmSPI_SLAVE_DEBUG_BUSY 0x24D3 -#define mmSPI_LB_CTR_CTRL 0x24D4 -#define mmSPI_LB_CU_MASK 0x24D5 -#define mmSPI_LB_DATA_REG 0x24D6 -#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24D7 -#define mmSPI_GDS_CREDITS 0x24D8 -#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24D9 -#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24DA -#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24DB -#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24DC -#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24DD -#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24DE -#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24DF -#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24E0 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24E1 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24E2 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24E3 -#define mmSPI_LB_DATA_WAVES 0x24E4 -#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x24E5 -#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x24E6 -#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x24E7 -#define mmSPIS_DEBUG_READ 0x24EA -#define mmBCI_DEBUG_READ 0x24EB -#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24EC -#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ED -#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24EE -#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24EF -#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24F0 -#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24F1 -#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24F2 -#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24F3 -#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24F4 -#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24F5 -#define mmSPI_SHADER_PGM_LO_PS 0x2C08 -#define mmSPI_SHADER_PGM_HI_PS 0x2C09 -#define mmSPI_SHADER_PGM_RSRC1_PS 0x2C0A -#define mmSPI_SHADER_PGM_RSRC2_PS 0x2C0B -#define mmSPI_SHADER_PGM_RSRC3_PS 0x2C07 -#define mmSPI_SHADER_USER_DATA_PS_0 0x2C0C -#define mmSPI_SHADER_USER_DATA_PS_1 0x2C0D -#define mmSPI_SHADER_USER_DATA_PS_2 0x2C0E -#define mmSPI_SHADER_USER_DATA_PS_3 0x2C0F -#define mmSPI_SHADER_USER_DATA_PS_4 0x2C10 -#define mmSPI_SHADER_USER_DATA_PS_5 0x2C11 -#define mmSPI_SHADER_USER_DATA_PS_6 0x2C12 -#define mmSPI_SHADER_USER_DATA_PS_7 0x2C13 -#define mmSPI_SHADER_USER_DATA_PS_8 0x2C14 -#define mmSPI_SHADER_USER_DATA_PS_9 0x2C15 -#define mmSPI_SHADER_USER_DATA_PS_10 0x2C16 -#define mmSPI_SHADER_USER_DATA_PS_11 0x2C17 -#define mmSPI_SHADER_USER_DATA_PS_12 0x2C18 -#define mmSPI_SHADER_USER_DATA_PS_13 0x2C19 -#define mmSPI_SHADER_USER_DATA_PS_14 0x2C1A -#define mmSPI_SHADER_USER_DATA_PS_15 0x2C1B -#define mmSPI_SHADER_USER_DATA_PS_16 0x2C1C -#define mmSPI_SHADER_USER_DATA_PS_17 0x2C1D -#define mmSPI_SHADER_USER_DATA_PS_18 0x2C1E -#define mmSPI_SHADER_USER_DATA_PS_19 0x2C1F -#define mmSPI_SHADER_USER_DATA_PS_20 0x2C20 -#define mmSPI_SHADER_USER_DATA_PS_21 0x2C21 -#define mmSPI_SHADER_USER_DATA_PS_22 0x2C22 -#define mmSPI_SHADER_USER_DATA_PS_23 0x2C23 -#define mmSPI_SHADER_USER_DATA_PS_24 0x2C24 -#define mmSPI_SHADER_USER_DATA_PS_25 0x2C25 -#define mmSPI_SHADER_USER_DATA_PS_26 0x2C26 -#define mmSPI_SHADER_USER_DATA_PS_27 0x2C27 -#define mmSPI_SHADER_USER_DATA_PS_28 0x2C28 -#define mmSPI_SHADER_USER_DATA_PS_29 0x2C29 -#define mmSPI_SHADER_USER_DATA_PS_30 0x2C2A -#define mmSPI_SHADER_USER_DATA_PS_31 0x2C2B -#define mmSPI_SHADER_PGM_LO_VS 0x2C48 -#define mmSPI_SHADER_PGM_HI_VS 0x2C49 -#define mmSPI_SHADER_PGM_RSRC1_VS 0x2C4A -#define mmSPI_SHADER_PGM_RSRC2_VS 0x2C4B -#define mmSPI_SHADER_PGM_RSRC3_VS 0x2C46 -#define mmSPI_SHADER_LATE_ALLOC_VS 0x2C47 -#define mmSPI_SHADER_USER_DATA_VS_0 0x2C4C -#define mmSPI_SHADER_USER_DATA_VS_1 0x2C4D -#define mmSPI_SHADER_USER_DATA_VS_2 0x2C4E -#define mmSPI_SHADER_USER_DATA_VS_3 0x2C4F -#define mmSPI_SHADER_USER_DATA_VS_4 0x2C50 -#define mmSPI_SHADER_USER_DATA_VS_5 0x2C51 -#define mmSPI_SHADER_USER_DATA_VS_6 0x2C52 -#define mmSPI_SHADER_USER_DATA_VS_7 0x2C53 -#define mmSPI_SHADER_USER_DATA_VS_8 0x2C54 -#define mmSPI_SHADER_USER_DATA_VS_9 0x2C55 -#define mmSPI_SHADER_USER_DATA_VS_10 0x2C56 -#define mmSPI_SHADER_USER_DATA_VS_11 0x2C57 -#define mmSPI_SHADER_USER_DATA_VS_12 0x2C58 -#define mmSPI_SHADER_USER_DATA_VS_13 0x2C59 -#define mmSPI_SHADER_USER_DATA_VS_14 0x2C5A -#define mmSPI_SHADER_USER_DATA_VS_15 0x2C5B -#define mmSPI_SHADER_USER_DATA_VS_16 0x2C5C -#define mmSPI_SHADER_USER_DATA_VS_17 0x2C5D -#define mmSPI_SHADER_USER_DATA_VS_18 0x2C5E -#define mmSPI_SHADER_USER_DATA_VS_19 0x2C5F -#define mmSPI_SHADER_USER_DATA_VS_20 0x2C60 -#define mmSPI_SHADER_USER_DATA_VS_21 0x2C61 -#define mmSPI_SHADER_USER_DATA_VS_22 0x2C62 -#define mmSPI_SHADER_USER_DATA_VS_23 0x2C63 -#define mmSPI_SHADER_USER_DATA_VS_24 0x2C64 -#define mmSPI_SHADER_USER_DATA_VS_25 0x2C65 -#define mmSPI_SHADER_USER_DATA_VS_26 0x2C66 -#define mmSPI_SHADER_USER_DATA_VS_27 0x2C67 -#define mmSPI_SHADER_USER_DATA_VS_28 0x2C68 -#define mmSPI_SHADER_USER_DATA_VS_29 0x2C69 -#define mmSPI_SHADER_USER_DATA_VS_30 0x2C6A -#define mmSPI_SHADER_USER_DATA_VS_31 0x2C6B -#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x2C7C -#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x2C82 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x2C83 -#define mmSPI_SHADER_PGM_LO_GS 0x2C88 -#define mmSPI_SHADER_PGM_HI_GS 0x2C89 -#define mmSPI_SHADER_PGM_LO_ES 0x2C84 -#define mmSPI_SHADER_PGM_HI_ES 0x2C85 -#define mmSPI_SHADER_PGM_RSRC1_GS 0x2C8A -#define mmSPI_SHADER_PGM_RSRC2_GS 0x2C8B -#define mmSPI_SHADER_PGM_RSRC3_GS 0x2C87 -#define mmSPI_SHADER_PGM_RSRC4_GS 0x2C81 -#define mmSPI_SHADER_USER_DATA_ES_0 0x2CCC -#define mmSPI_SHADER_USER_DATA_ES_1 0x2CCD -#define mmSPI_SHADER_USER_DATA_ES_2 0x2CCE -#define mmSPI_SHADER_USER_DATA_ES_3 0x2CCF -#define mmSPI_SHADER_USER_DATA_ES_4 0x2CD0 -#define mmSPI_SHADER_USER_DATA_ES_5 0x2CD1 -#define mmSPI_SHADER_USER_DATA_ES_6 0x2CD2 -#define mmSPI_SHADER_USER_DATA_ES_7 0x2CD3 -#define mmSPI_SHADER_USER_DATA_ES_8 0x2CD4 -#define mmSPI_SHADER_USER_DATA_ES_9 0x2CD5 -#define mmSPI_SHADER_USER_DATA_ES_10 0x2CD6 -#define mmSPI_SHADER_USER_DATA_ES_11 0x2CD7 -#define mmSPI_SHADER_USER_DATA_ES_12 0x2CD8 -#define mmSPI_SHADER_USER_DATA_ES_13 0x2CD9 -#define mmSPI_SHADER_USER_DATA_ES_14 0x2CDA -#define mmSPI_SHADER_USER_DATA_ES_15 0x2CDB -#define mmSPI_SHADER_USER_DATA_ES_16 0x2CDC -#define mmSPI_SHADER_USER_DATA_ES_17 0x2CDD -#define mmSPI_SHADER_USER_DATA_ES_18 0x2CDE -#define mmSPI_SHADER_USER_DATA_ES_19 0x2CDF -#define mmSPI_SHADER_USER_DATA_ES_20 0x2CE0 -#define mmSPI_SHADER_USER_DATA_ES_21 0x2CE1 -#define mmSPI_SHADER_USER_DATA_ES_22 0x2CE2 -#define mmSPI_SHADER_USER_DATA_ES_23 0x2CE3 -#define mmSPI_SHADER_USER_DATA_ES_24 0x2CE4 -#define mmSPI_SHADER_USER_DATA_ES_25 0x2CE5 -#define mmSPI_SHADER_USER_DATA_ES_26 0x2CE6 -#define mmSPI_SHADER_USER_DATA_ES_27 0x2CE7 -#define mmSPI_SHADER_USER_DATA_ES_28 0x2CE8 -#define mmSPI_SHADER_USER_DATA_ES_29 0x2CE9 -#define mmSPI_SHADER_USER_DATA_ES_30 0x2CEA -#define mmSPI_SHADER_USER_DATA_ES_31 0x2CEB -#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x2D02 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x2D03 -#define mmSPI_SHADER_PGM_LO_HS 0x2D08 -#define mmSPI_SHADER_PGM_HI_HS 0x2D09 -#define mmSPI_SHADER_PGM_LO_LS 0x2D04 -#define mmSPI_SHADER_PGM_HI_LS 0x2D05 -#define mmSPI_SHADER_PGM_RSRC1_HS 0x2D0A -#define mmSPI_SHADER_PGM_RSRC2_HS 0x2D0B -#define mmSPI_SHADER_PGM_RSRC3_HS 0x2D07 -#define mmSPI_SHADER_PGM_RSRC4_HS 0x2D01 -#define mmSPI_SHADER_USER_DATA_LS_0 0x2D0C -#define mmSPI_SHADER_USER_DATA_LS_1 0x2D0D -#define mmSPI_SHADER_USER_DATA_LS_2 0x2D0E -#define mmSPI_SHADER_USER_DATA_LS_3 0x2D0F -#define mmSPI_SHADER_USER_DATA_LS_4 0x2D10 -#define mmSPI_SHADER_USER_DATA_LS_5 0x2D11 -#define mmSPI_SHADER_USER_DATA_LS_6 0x2D12 -#define mmSPI_SHADER_USER_DATA_LS_7 0x2D13 -#define mmSPI_SHADER_USER_DATA_LS_8 0x2D14 -#define mmSPI_SHADER_USER_DATA_LS_9 0x2D15 -#define mmSPI_SHADER_USER_DATA_LS_10 0x2D16 -#define mmSPI_SHADER_USER_DATA_LS_11 0x2D17 -#define mmSPI_SHADER_USER_DATA_LS_12 0x2D18 -#define mmSPI_SHADER_USER_DATA_LS_13 0x2D19 -#define mmSPI_SHADER_USER_DATA_LS_14 0x2D1A -#define mmSPI_SHADER_USER_DATA_LS_15 0x2D1B -#define mmSPI_SHADER_USER_DATA_LS_16 0x2D1C -#define mmSPI_SHADER_USER_DATA_LS_17 0x2D1D -#define mmSPI_SHADER_USER_DATA_LS_18 0x2D1E -#define mmSPI_SHADER_USER_DATA_LS_19 0x2D1F -#define mmSPI_SHADER_USER_DATA_LS_20 0x2D20 -#define mmSPI_SHADER_USER_DATA_LS_21 0x2D21 -#define mmSPI_SHADER_USER_DATA_LS_22 0x2D22 -#define mmSPI_SHADER_USER_DATA_LS_23 0x2D23 -#define mmSPI_SHADER_USER_DATA_LS_24 0x2D24 -#define mmSPI_SHADER_USER_DATA_LS_25 0x2D25 -#define mmSPI_SHADER_USER_DATA_LS_26 0x2D26 -#define mmSPI_SHADER_USER_DATA_LS_27 0x2D27 -#define mmSPI_SHADER_USER_DATA_LS_28 0x2D28 -#define mmSPI_SHADER_USER_DATA_LS_29 0x2D29 -#define mmSPI_SHADER_USER_DATA_LS_30 0x2D2A -#define mmSPI_SHADER_USER_DATA_LS_31 0x2D2B -#define mmSPI_SHADER_USER_DATA_COMMON_0 0x2D4C -#define mmSPI_SHADER_USER_DATA_COMMON_1 0x2D4D -#define mmSPI_SHADER_USER_DATA_COMMON_2 0x2D4E -#define mmSPI_SHADER_USER_DATA_COMMON_3 0x2D4F -#define mmSPI_SHADER_USER_DATA_COMMON_4 0x2D50 -#define mmSPI_SHADER_USER_DATA_COMMON_5 0x2D51 -#define mmSPI_SHADER_USER_DATA_COMMON_6 0x2D52 -#define mmSPI_SHADER_USER_DATA_COMMON_7 0x2D53 -#define mmSPI_SHADER_USER_DATA_COMMON_8 0x2D54 -#define mmSPI_SHADER_USER_DATA_COMMON_9 0x2D55 -#define mmSPI_SHADER_USER_DATA_COMMON_10 0x2D56 -#define mmSPI_SHADER_USER_DATA_COMMON_11 0x2D57 -#define mmSPI_SHADER_USER_DATA_COMMON_12 0x2D58 -#define mmSPI_SHADER_USER_DATA_COMMON_13 0x2D59 -#define mmSPI_SHADER_USER_DATA_COMMON_14 0x2D5A -#define mmSPI_SHADER_USER_DATA_COMMON_15 0x2D5B -#define mmSPI_SHADER_USER_DATA_COMMON_16 0x2D5C -#define mmSPI_SHADER_USER_DATA_COMMON_17 0x2D5D -#define mmSPI_SHADER_USER_DATA_COMMON_18 0x2D5E -#define mmSPI_SHADER_USER_DATA_COMMON_19 0x2D5F -#define mmSPI_SHADER_USER_DATA_COMMON_20 0x2D60 -#define mmSPI_SHADER_USER_DATA_COMMON_21 0x2D61 -#define mmSPI_SHADER_USER_DATA_COMMON_22 0x2D62 -#define mmSPI_SHADER_USER_DATA_COMMON_23 0x2D63 -#define mmSPI_SHADER_USER_DATA_COMMON_24 0x2D64 -#define mmSPI_SHADER_USER_DATA_COMMON_25 0x2D65 -#define mmSPI_SHADER_USER_DATA_COMMON_26 0x2D66 -#define mmSPI_SHADER_USER_DATA_COMMON_27 0x2D67 -#define mmSPI_SHADER_USER_DATA_COMMON_28 0x2D68 -#define mmSPI_SHADER_USER_DATA_COMMON_29 0x2D69 -#define mmSPI_SHADER_USER_DATA_COMMON_30 0x2D6A -#define mmSPI_SHADER_USER_DATA_COMMON_31 0x2D6B -#define mmSPI_ARB_PRIORITY 0x31C0 -#define mmSPI_ARB_CYCLES_0 0x31C1 -#define mmSPI_ARB_CYCLES_1 0x31C2 -#define mmSPI_CDBG_SYS_GFX 0x31C3 -#define mmSPI_CDBG_SYS_HP3D 0x31C4 -#define mmSPI_CDBG_SYS_CS0 0x31C5 -#define mmSPI_CDBG_SYS_CS1 0x31C6 -#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31C7 -#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31C8 -#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31C9 -#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31CA -#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31CB -#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31CC -#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31CD -#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31CE -#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31CF -#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31D0 -#define mmSPI_GDBG_WAVE_CNTL 0x31D1 -#define mmSPI_GDBG_TRAP_CONFIG 0x31D2 -#define mmSPI_GDBG_TRAP_MASK 0x31D3 -#define mmSPI_GDBG_WAVE_CNTL2 0x31D4 -#define mmSPI_GDBG_WAVE_CNTL3 0x31D5 -#define mmSPI_GDBG_TRAP_DATA0 0x31D8 -#define mmSPI_GDBG_TRAP_DATA1 0x31D9 -#define mmSPI_RESET_DEBUG 0x31DA -#define mmSPI_COMPUTE_QUEUE_RESET 0x31DB -#define mmSPI_RESOURCE_RESERVE_CU_0 0x31DC -#define mmSPI_RESOURCE_RESERVE_CU_1 0x31DD -#define mmSPI_RESOURCE_RESERVE_CU_2 0x31DE -#define mmSPI_RESOURCE_RESERVE_CU_3 0x31DF -#define mmSPI_RESOURCE_RESERVE_CU_4 0x31E0 -#define mmSPI_RESOURCE_RESERVE_CU_5 0x31E1 -#define mmSPI_RESOURCE_RESERVE_CU_6 0x31E2 -#define mmSPI_RESOURCE_RESERVE_CU_7 0x31E3 -#define mmSPI_RESOURCE_RESERVE_CU_8 0x31E4 -#define mmSPI_RESOURCE_RESERVE_CU_9 0x31E5 -#define mmSPI_RESOURCE_RESERVE_CU_10 0x31F0 -#define mmSPI_RESOURCE_RESERVE_CU_11 0x31F1 -#define mmSPI_RESOURCE_RESERVE_CU_12 0x31F4 -#define mmSPI_RESOURCE_RESERVE_CU_13 0x31F5 -#define mmSPI_RESOURCE_RESERVE_CU_14 0x31F6 -#define mmSPI_RESOURCE_RESERVE_CU_15 0x31F7 -#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31E6 -#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31E7 -#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31E8 -#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31E9 -#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31EA -#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31EB -#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31EC -#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ED -#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31EE -#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31EF -#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31F2 -#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31F3 -#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x31F8 -#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x31F9 -#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x31FA -#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x31FB -#define mmSPI_COMPUTE_WF_CTX_SAVE 0x31FC -#define mmSPI_ARB_CNTL_0 0x31FD -#define mmSPI_PS_INPUT_CNTL_0 0xA191 -#define mmSPI_PS_INPUT_CNTL_1 0xA192 -#define mmSPI_PS_INPUT_CNTL_2 0xA193 -#define mmSPI_PS_INPUT_CNTL_3 0xA194 -#define mmSPI_PS_INPUT_CNTL_4 0xA195 -#define mmSPI_PS_INPUT_CNTL_5 0xA196 -#define mmSPI_PS_INPUT_CNTL_6 0xA197 -#define mmSPI_PS_INPUT_CNTL_7 0xA198 -#define mmSPI_PS_INPUT_CNTL_8 0xA199 -#define mmSPI_PS_INPUT_CNTL_9 0xA19A -#define mmSPI_PS_INPUT_CNTL_10 0xA19B -#define mmSPI_PS_INPUT_CNTL_11 0xA19C -#define mmSPI_PS_INPUT_CNTL_12 0xA19D -#define mmSPI_PS_INPUT_CNTL_13 0xA19E -#define mmSPI_PS_INPUT_CNTL_14 0xA19F -#define mmSPI_PS_INPUT_CNTL_15 0xA1A0 -#define mmSPI_PS_INPUT_CNTL_16 0xA1A1 -#define mmSPI_PS_INPUT_CNTL_17 0xA1A2 -#define mmSPI_PS_INPUT_CNTL_18 0xA1A3 -#define mmSPI_PS_INPUT_CNTL_19 0xA1A4 -#define mmSPI_PS_INPUT_CNTL_20 0xA1A5 -#define mmSPI_PS_INPUT_CNTL_21 0xA1A6 -#define mmSPI_PS_INPUT_CNTL_22 0xA1A7 -#define mmSPI_PS_INPUT_CNTL_23 0xA1A8 -#define mmSPI_PS_INPUT_CNTL_24 0xA1A9 -#define mmSPI_PS_INPUT_CNTL_25 0xA1AA -#define mmSPI_PS_INPUT_CNTL_26 0xA1AB -#define mmSPI_PS_INPUT_CNTL_27 0xA1AC -#define mmSPI_PS_INPUT_CNTL_28 0xA1AD -#define mmSPI_PS_INPUT_CNTL_29 0xA1AE -#define mmSPI_PS_INPUT_CNTL_30 0xA1AF -#define mmSPI_PS_INPUT_CNTL_31 0xA1B0 -#define mmSPI_VS_OUT_CONFIG 0xA1B1 -#define mmSPI_PS_INPUT_ENA 0xA1B3 -#define mmSPI_PS_INPUT_ADDR 0xA1B4 -#define mmSPI_INTERP_CONTROL_0 0xA1B5 -#define mmSPI_PS_IN_CONTROL 0xA1B6 -#define mmSPI_BARYC_CNTL 0xA1B8 -#define mmSPI_TMPRING_SIZE 0xA1BA -#define mmSPI_SHADER_POS_FORMAT 0xA1C3 -#define mmSPI_SHADER_Z_FORMAT 0xA1C4 -#define mmSPI_SHADER_COL_FORMAT 0xA1C5 -#define mmSPI_CONFIG_CNTL 0xC440 -#define mmSPI_CONFIG_CNTL_1 0xC441 -#define mmSPI_CONFIG_CNTL_2 0xC442 -#define mmSPI_PERFCOUNTER0_HI 0xD180 -#define mmSPI_PERFCOUNTER0_LO 0xD181 -#define mmSPI_PERFCOUNTER1_HI 0xD182 -#define mmSPI_PERFCOUNTER1_LO 0xD183 -#define mmSPI_PERFCOUNTER2_HI 0xD184 -#define mmSPI_PERFCOUNTER2_LO 0xD185 -#define mmSPI_PERFCOUNTER3_HI 0xD186 -#define mmSPI_PERFCOUNTER3_LO 0xD187 -#define mmSPI_PERFCOUNTER4_HI 0xD188 -#define mmSPI_PERFCOUNTER4_LO 0xD189 -#define mmSPI_PERFCOUNTER5_HI 0xD18A -#define mmSPI_PERFCOUNTER5_LO 0xD18B -#define mmSPI_PERFCOUNTER0_SELECT 0xD980 -#define mmSPI_PERFCOUNTER1_SELECT 0xD981 -#define mmSPI_PERFCOUNTER2_SELECT 0xD982 -#define mmSPI_PERFCOUNTER3_SELECT 0xD983 -#define mmSPI_PERFCOUNTER0_SELECT1 0xD984 -#define mmSPI_PERFCOUNTER1_SELECT1 0xD985 -#define mmSPI_PERFCOUNTER2_SELECT1 0xD986 -#define mmSPI_PERFCOUNTER3_SELECT1 0xD987 -#define mmSPI_PERFCOUNTER4_SELECT 0xD988 -#define mmSPI_PERFCOUNTER5_SELECT 0xD989 -#define mmSPI_PERFCOUNTER_BINS 0xD98A -#define mmCGTS_SM_CTRL_REG 0xF000 -#define mmCGTS_RD_CTRL_REG 0xF001 -#define mmCGTS_RD_REG 0xF002 -#define mmCGTS_TCC_DISABLE 0xF003 -#define mmCGTS_USER_TCC_DISABLE 0xF004 -#define mmCGTS_CU0_SP0_CTRL_REG 0xF008 -#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xF009 -#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xF00A -#define mmCGTS_CU0_SP1_CTRL_REG 0xF00B -#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xF00C -#define mmCGTS_CU0_TCPI_CTRL_REG 0xF058 -#define mmCGTS_CU1_SP0_CTRL_REG 0xF00D -#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xF00E -#define mmCGTS_CU1_TA_SQC_CTRL_REG 0xF00F -#define mmCGTS_CU1_SP1_CTRL_REG 0xF010 -#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xF011 -#define mmCGTS_CU1_TCPI_CTRL_REG 0xF059 -#define mmCGTS_CU2_SP0_CTRL_REG 0xF012 -#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xF013 -#define mmCGTS_CU2_TA_SQC_CTRL_REG 0xF014 -#define mmCGTS_CU2_SP1_CTRL_REG 0xF015 -#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xF016 -#define mmCGTS_CU2_TCPI_CTRL_REG 0xF05A -#define mmCGTS_CU3_SP0_CTRL_REG 0xF017 -#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xF018 -#define mmCGTS_CU3_TA_SQC_CTRL_REG 0xF019 -#define mmCGTS_CU3_SP1_CTRL_REG 0xF01A -#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xF01B -#define mmCGTS_CU3_TCPI_CTRL_REG 0xF05B -#define mmCGTS_CU4_SP0_CTRL_REG 0xF01C -#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xF01D -#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xF01E -#define mmCGTS_CU4_SP1_CTRL_REG 0xF01F -#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xF020 -#define mmCGTS_CU4_TCPI_CTRL_REG 0xF05C -#define mmCGTS_CU5_SP0_CTRL_REG 0xF021 -#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xF022 -#define mmCGTS_CU5_TA_SQC_CTRL_REG 0xF023 -#define mmCGTS_CU5_SP1_CTRL_REG 0xF024 -#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xF025 -#define mmCGTS_CU5_TCPI_CTRL_REG 0xF05D -#define mmCGTS_CU6_SP0_CTRL_REG 0xF026 -#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xF027 -#define mmCGTS_CU6_TA_SQC_CTRL_REG 0xF028 -#define mmCGTS_CU6_SP1_CTRL_REG 0xF029 -#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xF02A -#define mmCGTS_CU6_TCPI_CTRL_REG 0xF05E -#define mmCGTS_CU7_SP0_CTRL_REG 0xF02B -#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xF02C -#define mmCGTS_CU7_TA_SQC_CTRL_REG 0xF02D -#define mmCGTS_CU7_SP1_CTRL_REG 0xF02E -#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xF02F -#define mmCGTS_CU7_TCPI_CTRL_REG 0xF05F -#define mmCGTS_CU8_SP0_CTRL_REG 0xF030 -#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xF031 -#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xF032 -#define mmCGTS_CU8_SP1_CTRL_REG 0xF033 -#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xF034 -#define mmCGTS_CU8_TCPI_CTRL_REG 0xF060 -#define mmCGTS_CU9_SP0_CTRL_REG 0xF035 -#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xF036 -#define mmCGTS_CU9_TA_SQC_CTRL_REG 0xF037 -#define mmCGTS_CU9_SP1_CTRL_REG 0xF038 -#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xF039 -#define mmCGTS_CU9_TCPI_CTRL_REG 0xF061 -#define mmCGTS_CU10_SP0_CTRL_REG 0xF03A -#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xF03B -#define mmCGTS_CU10_TA_SQC_CTRL_REG 0xF03C -#define mmCGTS_CU10_SP1_CTRL_REG 0xF03D -#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xF03E -#define mmCGTS_CU10_TCPI_CTRL_REG 0xF062 -#define mmCGTS_CU11_SP0_CTRL_REG 0xF03F -#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xF040 -#define mmCGTS_CU11_TA_SQC_CTRL_REG 0xF041 -#define mmCGTS_CU11_SP1_CTRL_REG 0xF042 -#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xF043 -#define mmCGTS_CU11_TCPI_CTRL_REG 0xF063 -#define mmCGTS_CU12_SP0_CTRL_REG 0xF044 -#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xF045 -#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xF046 -#define mmCGTS_CU12_SP1_CTRL_REG 0xF047 -#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xF048 -#define mmCGTS_CU12_TCPI_CTRL_REG 0xF064 -#define mmCGTS_CU13_SP0_CTRL_REG 0xF049 -#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xF04A -#define mmCGTS_CU13_TA_SQC_CTRL_REG 0xF04B -#define mmCGTS_CU13_SP1_CTRL_REG 0xF04C -#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xF04D -#define mmCGTS_CU13_TCPI_CTRL_REG 0xF065 -#define mmCGTS_CU14_SP0_CTRL_REG 0xF04E -#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xF04F -#define mmCGTS_CU14_TA_SQC_CTRL_REG 0xF050 -#define mmCGTS_CU14_SP1_CTRL_REG 0xF051 -#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xF052 -#define mmCGTS_CU14_TCPI_CTRL_REG 0xF066 -#define mmCGTS_CU15_SP0_CTRL_REG 0xF053 -#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xF054 -#define mmCGTS_CU15_TA_SQC_CTRL_REG 0xF055 -#define mmCGTS_CU15_SP1_CTRL_REG 0xF056 -#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xF057 -#define mmCGTS_CU15_TCPI_CTRL_REG 0xF067 -#define mmCGTT_SPI_CLK_CTRL 0xF080 -#define mmCGTT_PC_CLK_CTRL 0xF081 -#define mmCGTT_BCI_CLK_CTRL 0xF082 - - -// Registers from SQ block - -#define mmSQ_CONFIG 0x2300 -#define mmSQC_CONFIG 0x2301 -#define mmLDS_CONFIG 0x2302 -#define mmSQC_DSM_CNTL 0x2320 -#define mmSQC_DSM_CNTLA 0x2321 -#define mmSQC_DSM_CNTLB 0x2322 -#define mmSQC_DSM_CNTL2 0x2325 -#define mmSQC_DSM_CNTL2A 0x2326 -#define mmSQC_DSM_CNTL2B 0x2327 -#define mmSQC_EDC_FUE_CNTL 0x232B -#define mmSQC_EDC_CNT2 0x232C -#define mmSQC_EDC_CNT3 0x232D -#define mmSQ_RANDOM_WAVE_PRI 0x2303 -#define mmSQ_REG_CREDITS 0x2304 -#define mmSQ_FIFO_SIZES 0x2305 -#define mmSQ_DSM_CNTL 0x2306 -#define mmSQ_DSM_CNTL2 0x2307 -#define mmSQ_RUNTIME_CONFIG 0x2308 -#define mmCC_GC_SHADER_RATE_CONFIG 0x2312 -#define mmGC_USER_SHADER_RATE_CONFIG 0x2313 -#define mmSQ_INTERRUPT_AUTO_MASK 0x2314 -#define mmSQ_INTERRUPT_MSG_CTRL 0x2315 -#define mmSQ_DEBUG_PERFCOUNT_TRAP 0x2316 -#define mmSQ_UTCL1_CNTL1 0x2317 -#define mmSQ_UTCL1_CNTL2 0x2318 -#define mmSQ_UTCL1_STATUS 0x2319 -#define mmSQ_TIME_HI 0x237C -#define mmSQ_TIME_LO 0x237D -#define mmSQ_LB_CTR_CTRL 0x2398 -#define mmSQ_LB_DATA0 0x2399 -#define mmSQ_LB_DATA1 0x239A -#define mmSQ_LB_DATA2 0x239B -#define mmSQ_LB_DATA3 0x239C -#define mmSQ_LB_CTR_SEL 0x239D -#define mmSQ_LB_CTR0_CU 0x239E -#define mmSQ_LB_CTR1_CU 0x239F -#define mmSQ_LB_CTR2_CU 0x23A0 -#define mmSQ_LB_CTR3_CU 0x23A1 -#define mmSQC_EDC_CNT 0x23A2 -#define mmSQ_EDC_SEC_CNT 0x23A3 -#define mmSQ_EDC_DED_CNT 0x23A4 -#define mmSQ_EDC_INFO 0x23A5 -#define mmSQ_EDC_CNT 0x23A6 -#define mmSQ_EDC_FUE_CNTL 0x23A7 -#define mmSQ_BUF_RSRC_WORD0 0x23C0 -#define mmSQ_BUF_RSRC_WORD1 0x23C1 -#define mmSQ_BUF_RSRC_WORD2 0x23C2 -#define mmSQ_BUF_RSRC_WORD3 0x23C3 -#define mmSQ_IMG_RSRC_WORD0 0x23C4 -#define mmSQ_IMG_RSRC_WORD1 0x23C5 -#define mmSQ_IMG_RSRC_WORD2 0x23C6 -#define mmSQ_IMG_RSRC_WORD3 0x23C7 -#define mmSQ_IMG_RSRC_WORD4 0x23C8 -#define mmSQ_IMG_RSRC_WORD5 0x23C9 -#define mmSQ_IMG_RSRC_WORD6 0x23CA -#define mmSQ_IMG_RSRC_WORD7 0x23CB -#define mmSQ_IMG_SAMP_WORD0 0x23CC -#define mmSQ_IMG_SAMP_WORD1 0x23CD -#define mmSQ_IMG_SAMP_WORD2 0x23CE -#define mmSQ_IMG_SAMP_WORD3 0x23CF -#define mmSQ_FLAT_SCRATCH_WORD0 0x23D0 -#define mmSQ_FLAT_SCRATCH_WORD1 0x23D1 -#define mmSQ_M0_GPR_IDX_WORD 0x23D2 -#define mmSQ_IND_INDEX 0x2378 -#define mmSQ_CMD 0x237B -#define mmSQ_IND_DATA 0x2379 -#define mmSQ_REG_TIMESTAMP 0x2374 -#define mmSQ_CMD_TIMESTAMP 0x2375 -#define mmSQ_DEBUG_STS_GLOBAL 0x2309 -#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 -#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 -#define mmSH_MEM_BASES 0x230A -#define mmSH_MEM_CONFIG 0x230D -#define mmSQ_SHADER_TBA_LO 0x231C -#define mmSQ_SHADER_TBA_HI 0x231D -#define mmSQ_SHADER_TMA_LO 0x231E -#define mmSQ_SHADER_TMA_HI 0x231F -#define mmSQ_THREAD_TRACE_WORD_CMN 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23B1 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23B1 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23B1 -#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_MISC 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23B0 -#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23B1 -#define mmSQ_WREXEC_EXEC_LO 0x23B1 -#define mmSQ_WREXEC_EXEC_HI 0x23B1 -#define mmSQC_ICACHE_UTCL1_CNTL1 0x23D3 -#define mmSQC_ICACHE_UTCL1_CNTL2 0x23D4 -#define mmSQC_DCACHE_UTCL1_CNTL1 0x23D5 -#define mmSQC_DCACHE_UTCL1_CNTL2 0x23D6 -#define mmSQC_ICACHE_UTCL1_STATUS 0x23D7 -#define mmSQC_DCACHE_UTCL1_STATUS 0x23D8 -#define mmSQC_CACHES 0xC348 -#define mmSQC_WRITEBACK 0xC349 -#define mmSQ_THREAD_TRACE_BASE 0xC330 -#define mmSQ_THREAD_TRACE_BASE2 0xC337 -#define mmSQ_THREAD_TRACE_SIZE 0xC331 -#define mmSQ_THREAD_TRACE_MASK 0xC332 -#define mmSQ_THREAD_TRACE_USERDATA_0 0xC340 -#define mmSQ_THREAD_TRACE_USERDATA_1 0xC341 -#define mmSQ_THREAD_TRACE_USERDATA_2 0xC342 -#define mmSQ_THREAD_TRACE_USERDATA_3 0xC343 -#define mmSQ_THREAD_TRACE_MODE 0xC336 -#define mmSQ_THREAD_TRACE_CTRL 0xC335 -#define mmSQ_THREAD_TRACE_TOKEN_MASK 0xC333 -#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0xC338 -#define mmSQ_THREAD_TRACE_PERF_MASK 0xC334 -#define mmSQ_THREAD_TRACE_WPTR 0xC339 -#define mmSQ_THREAD_TRACE_STATUS 0xC33A -#define mmSQ_THREAD_TRACE_CNTR 0xC33C -#define mmSQ_THREAD_TRACE_HIWATER 0xC33B -#define mmSQ_PERFCOUNTER0_LO 0xD1C0 -#define mmSQ_PERFCOUNTER1_LO 0xD1C2 -#define mmSQ_PERFCOUNTER2_LO 0xD1C4 -#define mmSQ_PERFCOUNTER3_LO 0xD1C6 -#define mmSQ_PERFCOUNTER4_LO 0xD1C8 -#define mmSQ_PERFCOUNTER5_LO 0xD1CA -#define mmSQ_PERFCOUNTER6_LO 0xD1CC -#define mmSQ_PERFCOUNTER7_LO 0xD1CE -#define mmSQ_PERFCOUNTER8_LO 0xD1D0 -#define mmSQ_PERFCOUNTER9_LO 0xD1D2 -#define mmSQ_PERFCOUNTER10_LO 0xD1D4 -#define mmSQ_PERFCOUNTER11_LO 0xD1D6 -#define mmSQ_PERFCOUNTER12_LO 0xD1D8 -#define mmSQ_PERFCOUNTER13_LO 0xD1DA -#define mmSQ_PERFCOUNTER14_LO 0xD1DC -#define mmSQ_PERFCOUNTER15_LO 0xD1DE -#define mmSQ_PERFCOUNTER0_HI 0xD1C1 -#define mmSQ_PERFCOUNTER1_HI 0xD1C3 -#define mmSQ_PERFCOUNTER2_HI 0xD1C5 -#define mmSQ_PERFCOUNTER3_HI 0xD1C7 -#define mmSQ_PERFCOUNTER4_HI 0xD1C9 -#define mmSQ_PERFCOUNTER5_HI 0xD1CB -#define mmSQ_PERFCOUNTER6_HI 0xD1CD -#define mmSQ_PERFCOUNTER7_HI 0xD1CF -#define mmSQ_PERFCOUNTER8_HI 0xD1D1 -#define mmSQ_PERFCOUNTER9_HI 0xD1D3 -#define mmSQ_PERFCOUNTER10_HI 0xD1D5 -#define mmSQ_PERFCOUNTER11_HI 0xD1D7 -#define mmSQ_PERFCOUNTER12_HI 0xD1D9 -#define mmSQ_PERFCOUNTER13_HI 0xD1DB -#define mmSQ_PERFCOUNTER14_HI 0xD1DD -#define mmSQ_PERFCOUNTER15_HI 0xD1DF -#define mmSQ_PERFCOUNTER_CTRL 0xD9E0 -#define mmSQ_PERFCOUNTER_MASK 0xD9E1 -#define mmSQ_PERFCOUNTER_CTRL2 0xD9E2 -#define mmSQ_PERFCOUNTER0_SELECT 0xD9C0 -#define mmSQ_PERFCOUNTER1_SELECT 0xD9C1 -#define mmSQ_PERFCOUNTER2_SELECT 0xD9C2 -#define mmSQ_PERFCOUNTER3_SELECT 0xD9C3 -#define mmSQ_PERFCOUNTER4_SELECT 0xD9C4 -#define mmSQ_PERFCOUNTER5_SELECT 0xD9C5 -#define mmSQ_PERFCOUNTER6_SELECT 0xD9C6 -#define mmSQ_PERFCOUNTER7_SELECT 0xD9C7 -#define mmSQ_PERFCOUNTER8_SELECT 0xD9C8 -#define mmSQ_PERFCOUNTER9_SELECT 0xD9C9 -#define mmSQ_PERFCOUNTER10_SELECT 0xD9CA -#define mmSQ_PERFCOUNTER11_SELECT 0xD9CB -#define mmSQ_PERFCOUNTER12_SELECT 0xD9CC -#define mmSQ_PERFCOUNTER13_SELECT 0xD9CD -#define mmSQ_PERFCOUNTER14_SELECT 0xD9CE -#define mmSQ_PERFCOUNTER15_SELECT 0xD9CF -#define mmCGTT_SQ_CLK_CTRL 0xF08C -#define mmCGTT_SQG_CLK_CTRL 0xF08D -#define mmSQ_ALU_CLK_CTRL 0xF08E -#define mmSQ_TEX_CLK_CTRL 0xF08F -#define mmSQ_LDS_CLK_CTRL 0xF090 -#define mmSQ_POWER_THROTTLE 0xF091 -#define mmSQ_POWER_THROTTLE2 0xF092 - - -// Registers from COMP block - -#define mmCOMPUTE_DISPATCH_INITIATOR 0x2E00 -#define mmCOMPUTE_DIM_X 0x2E01 -#define mmCOMPUTE_DIM_Y 0x2E02 -#define mmCOMPUTE_DIM_Z 0x2E03 -#define mmCOMPUTE_START_X 0x2E04 -#define mmCOMPUTE_START_Y 0x2E05 -#define mmCOMPUTE_START_Z 0x2E06 -#define mmCOMPUTE_NUM_THREAD_X 0x2E07 -#define mmCOMPUTE_NUM_THREAD_Y 0x2E08 -#define mmCOMPUTE_NUM_THREAD_Z 0x2E09 -#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2E0A -#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2E0B -#define mmCOMPUTE_PGM_LO 0x2E0C -#define mmCOMPUTE_PGM_HI 0x2E0D -#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x2E0E -#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x2E0F -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x2E10 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x2E11 -#define mmCOMPUTE_PGM_RSRC1 0x2E12 -#define mmCOMPUTE_PGM_RSRC2 0x2E13 -#define mmCOMPUTE_VMID 0x2E14 -#define mmCOMPUTE_RESOURCE_LIMITS 0x2E15 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2E16 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2E17 -#define mmCOMPUTE_TMPRING_SIZE 0x2E18 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2E19 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2E1A -#define mmCOMPUTE_RESTART_X 0x2E1B -#define mmCOMPUTE_RESTART_Y 0x2E1C -#define mmCOMPUTE_RESTART_Z 0x2E1D -#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2E1E -#define mmCOMPUTE_MISC_RESERVED 0x2E1F -#define mmCOMPUTE_DISPATCH_ID 0x2E20 -#define mmCOMPUTE_THREADGROUP_ID 0x2E21 -#define mmCOMPUTE_RELAUNCH 0x2E22 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x2E23 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x2E24 -#define mmCOMPUTE_USER_DATA_0 0x2E40 -#define mmCOMPUTE_USER_DATA_1 0x2E41 -#define mmCOMPUTE_USER_DATA_2 0x2E42 -#define mmCOMPUTE_USER_DATA_3 0x2E43 -#define mmCOMPUTE_USER_DATA_4 0x2E44 -#define mmCOMPUTE_USER_DATA_5 0x2E45 -#define mmCOMPUTE_USER_DATA_6 0x2E46 -#define mmCOMPUTE_USER_DATA_7 0x2E47 -#define mmCOMPUTE_USER_DATA_8 0x2E48 -#define mmCOMPUTE_USER_DATA_9 0x2E49 -#define mmCOMPUTE_USER_DATA_10 0x2E4A -#define mmCOMPUTE_USER_DATA_11 0x2E4B -#define mmCOMPUTE_USER_DATA_12 0x2E4C -#define mmCOMPUTE_USER_DATA_13 0x2E4D -#define mmCOMPUTE_USER_DATA_14 0x2E4E -#define mmCOMPUTE_USER_DATA_15 0x2E4F -#define mmCOMPUTE_NOWHERE 0x2E7F - - -// Registers from VGT block - -#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 -#define mmVGT_DMA_CONTROL 0x2272 -#define mmVGT_VTX_VECT_EJECT_REG 0x222C -#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222D -#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222E -#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222F -#define mmVGT_LAST_COPY_STATE 0x2230 -#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226F -#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 -#define mmVGT_CACHE_INVALIDATION 0x2231 -#define mmVGT_RESET_DEBUG 0x2232 -#define mmVGT_STRMOUT_DELAY 0x2233 -#define mmVGT_FIFO_DEPTHS 0x2234 -#define mmVGT_GS_VERTEX_REUSE 0x2235 -#define mmVGT_MC_LAT_CNTL 0x2236 -#define mmIA_CNTL_STATUS 0x2237 -#define mmVGT_DMA_LS_HS_CONFIG 0x2273 -#define mmVGT_SYS_CONFIG 0x2263 -#define mmWD_BUF_RESOURCE_1 0x2276 -#define mmWD_BUF_RESOURCE_2 0x2277 -#define mmVGT_VS_MAX_WAVE_ID 0x2268 -#define mmVGT_GS_MAX_WAVE_ID 0x2269 -#define mmWD_CNTL_STATUS 0x223F -#define mmGFX_PIPE_CONTROL 0x226D -#define mmVGT_DEBUG_CNTL 0x2238 -#define mmVGT_DEBUG_DATA 0x2239 -#define mmIA_DEBUG_CNTL 0x223A -#define mmIA_DEBUG_DATA 0x223B -#define mmVGT_CNTL_STATUS 0x223C -#define mmWD_DEBUG_CNTL 0x223D -#define mmWD_DEBUG_DATA 0x223E -#define mmWD_QOS 0x2242 -#define mmWD_UTCL1_CNTL 0x2243 -#define mmWD_UTCL1_STATUS 0x2244 -#define mmIA_UTCL1_CNTL 0x2246 -#define mmIA_UTCL1_STATUS 0x2247 -#define mmCC_GC_PRIM_CONFIG 0x2240 -#define mmGC_USER_PRIM_CONFIG 0x2241 -#define mmCS_COPY_STATE 0xA1F3 -#define mmGFX_COPY_STATE 0xA1F4 -#define mmVGT_DRAW_INITIATOR 0xA1FC -#define mmVGT_DRAW_PAYLOAD_CNTL 0xA2A6 -#define mmVGT_INDEX_PAYLOAD_CNTL 0xA2A7 -#define mmVGT_EVENT_INITIATOR 0xA2A4 -#define mmVGT_DMA_EVENT_INITIATOR 0xA2E7 -#define mmVGT_EVENT_ADDRESS_REG 0xA1FE -#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0xA2A5 -#define mmVGT_DMA_BASE_HI 0xA1F9 -#define mmVGT_DMA_BASE 0xA1FA -#define mmVGT_DMA_INDEX_TYPE 0xA29F -#define mmVGT_DMA_NUM_INSTANCES 0xA2A2 -#define mmIA_ENHANCE 0xA29C -#define mmVGT_DMA_SIZE 0xA29D -#define mmVGT_DMA_MAX_SIZE 0xA29E -#define mmVGT_IMMED_DATA 0xA1FD -#define mmVGT_PRIMITIVEID_EN 0xA2A1 -#define mmVGT_PRIMITIVEID_RESET 0xA2A3 -#define mmVGT_VTX_CNT_EN 0xA2AE -#define mmVGT_REUSE_OFF 0xA2AD -#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8 -#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9 -#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316 -#define mmVGT_OUT_DEALLOC_CNTL 0xA317 -#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103 -#define mmVGT_ENHANCE 0xA294 -#define mmVGT_OUTPUT_PATH_CNTL 0xA284 -#define mmVGT_HOS_CNTL 0xA285 -#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286 -#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287 -#define mmVGT_HOS_REUSE_DEPTH 0xA288 -#define mmVGT_GROUP_PRIM_TYPE 0xA289 -#define mmVGT_GROUP_FIRST_DECR 0xA28A -#define mmVGT_GROUP_DECR 0xA28B -#define mmVGT_GROUP_VECT_0_CNTL 0xA28C -#define mmVGT_GROUP_VECT_1_CNTL 0xA28D -#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E -#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F -#define mmVGT_GS_MODE 0xA290 -#define mmVGT_GS_ONCHIP_CNTL 0xA291 -#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B -#define mmVGT_GS_PER_ES 0xA295 -#define mmVGT_ES_PER_GS 0xA296 -#define mmVGT_GS_PER_VS 0xA297 -#define mmVGT_STRMOUT_CONFIG 0xA2E5 -#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4 -#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8 -#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC -#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0 -#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7 -#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB -#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF -#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3 -#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5 -#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9 -#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD -#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1 -#define mmVGT_STRMOUT_BUFFER_CONFIG 0xA2E6 -#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA -#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB -#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC -#define mmVGT_GS_MAX_VERT_OUT 0xA2CE -#define mmVGT_SHADER_STAGES_EN 0xA2D5 -#define mmVGT_DISPATCH_DRAW_INDEX 0xA2DD -#define mmVGT_LS_HS_CONFIG 0xA2D6 -#define mmVGT_TF_PARAM 0xA2DB -#define mmVGT_TESS_DISTRIBUTION 0xA2D4 -#define mmVGT_GS_INSTANCE_CNT 0xA2E4 -#define mmVGT_GSVS_RING_OFFSET_1 0xA298 -#define mmVGT_GSVS_RING_OFFSET_2 0xA299 -#define mmVGT_GSVS_RING_OFFSET_3 0xA29A -#define mmVGT_ESGS_RING_ITEMSIZE 0xA2AB -#define mmVGT_GSVS_RING_ITEMSIZE 0xA2AC -#define mmVGT_GS_VERT_ITEMSIZE 0xA2D7 -#define mmVGT_GS_VERT_ITEMSIZE_1 0xA2D8 -#define mmVGT_GS_VERT_ITEMSIZE_2 0xA2D9 -#define mmVGT_GS_VERT_ITEMSIZE_3 0xA2DA -#define mmWD_ENHANCE 0xA2A0 -#define mmVGT_OBJECT_ID 0xC259 -#define mmVGT_INDEX_TYPE 0xC243 -#define mmVGT_NUM_INDICES 0xC24C -#define mmVGT_NUM_INSTANCES 0xC24D -#define mmVGT_PRIMITIVE_TYPE 0xC242 -#define mmVGT_MAX_VTX_INDX 0xC248 -#define mmVGT_MIN_VTX_INDX 0xC249 -#define mmVGT_INDX_OFFSET 0xC24A -#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xC24B -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xC244 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xC245 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xC246 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xC247 -#define mmVGT_TF_RING_SIZE 0xC24E -#define mmVGT_HS_OFFCHIP_PARAM 0xC24F -#define mmVGT_TF_MEMORY_BASE 0xC250 -#define mmVGT_TF_MEMORY_BASE_HI 0xC251 -#define mmWD_POS_BUF_BASE 0xC252 -#define mmWD_POS_BUF_BASE_HI 0xC253 -#define mmWD_CNTL_SB_BUF_BASE 0xC254 -#define mmWD_CNTL_SB_BUF_BASE_HI 0xC255 -#define mmWD_INDEX_BUF_BASE 0xC256 -#define mmWD_INDEX_BUF_BASE_HI 0xC257 -#define mmIA_MULTI_VGT_PARAM 0xC258 -#define mmVGT_GSVS_RING_SIZE 0xC241 -#define mmVGT_INSTANCE_BASE_ID 0xC25A -#define mmVGT_PERFCOUNTER0_LO 0xD090 -#define mmVGT_PERFCOUNTER1_LO 0xD092 -#define mmVGT_PERFCOUNTER2_LO 0xD094 -#define mmVGT_PERFCOUNTER3_LO 0xD096 -#define mmVGT_PERFCOUNTER0_HI 0xD091 -#define mmVGT_PERFCOUNTER1_HI 0xD093 -#define mmVGT_PERFCOUNTER2_HI 0xD095 -#define mmVGT_PERFCOUNTER3_HI 0xD097 -#define mmIA_PERFCOUNTER0_LO 0xD088 -#define mmIA_PERFCOUNTER1_LO 0xD08A -#define mmIA_PERFCOUNTER2_LO 0xD08C -#define mmIA_PERFCOUNTER3_LO 0xD08E -#define mmIA_PERFCOUNTER0_HI 0xD089 -#define mmIA_PERFCOUNTER1_HI 0xD08B -#define mmIA_PERFCOUNTER2_HI 0xD08D -#define mmIA_PERFCOUNTER3_HI 0xD08F -#define mmWD_PERFCOUNTER0_LO 0xD080 -#define mmWD_PERFCOUNTER1_LO 0xD082 -#define mmWD_PERFCOUNTER2_LO 0xD084 -#define mmWD_PERFCOUNTER3_LO 0xD086 -#define mmWD_PERFCOUNTER0_HI 0xD081 -#define mmWD_PERFCOUNTER1_HI 0xD083 -#define mmWD_PERFCOUNTER2_HI 0xD085 -#define mmWD_PERFCOUNTER3_HI 0xD087 -#define mmVGT_PERFCOUNTER_SEID_MASK 0xD894 -#define mmVGT_PERFCOUNTER0_SELECT 0xD88C -#define mmVGT_PERFCOUNTER1_SELECT 0xD88D -#define mmVGT_PERFCOUNTER2_SELECT 0xD88E -#define mmVGT_PERFCOUNTER3_SELECT 0xD88F -#define mmVGT_PERFCOUNTER0_SELECT1 0xD890 -#define mmVGT_PERFCOUNTER1_SELECT1 0xD891 -#define mmIA_PERFCOUNTER0_SELECT 0xD884 -#define mmIA_PERFCOUNTER1_SELECT 0xD885 -#define mmIA_PERFCOUNTER2_SELECT 0xD886 -#define mmIA_PERFCOUNTER3_SELECT 0xD887 -#define mmIA_PERFCOUNTER0_SELECT1 0xD888 -#define mmWD_PERFCOUNTER0_SELECT 0xD880 -#define mmWD_PERFCOUNTER1_SELECT 0xD881 -#define mmWD_PERFCOUNTER2_SELECT 0xD882 -#define mmWD_PERFCOUNTER3_SELECT 0xD883 -#define mmCGTT_VGT_CLK_CTRL 0xF084 -#define mmCGTT_IA_CLK_CTRL 0xF085 -#define mmCGTT_WD_CLK_CTRL 0xF086 - - -// Registers from GB block - -#define mmCC_RB_REDUNDANCY 0x263C -#define mmCC_RB_BACKEND_DISABLE 0x263D -#define mmGC_USER_RB_REDUNDANCY 0x26DE -#define mmGC_USER_RB_BACKEND_DISABLE 0x26DF -#define mmGB_ADDR_CONFIG 0x263E -#define mmGB_ADDR_CONFIG_READ 0x2642 -#define mmGB_BACKEND_MAP 0x263F -#define mmGB_GPU_ID 0x2640 -#define mmCC_RB_DAISY_CHAIN 0x2641 -#define mmGB_TILE_MODE0 0x2644 -#define mmGB_TILE_MODE1 0x2645 -#define mmGB_TILE_MODE2 0x2646 -#define mmGB_TILE_MODE3 0x2647 -#define mmGB_TILE_MODE4 0x2648 -#define mmGB_TILE_MODE5 0x2649 -#define mmGB_TILE_MODE6 0x264A -#define mmGB_TILE_MODE7 0x264B -#define mmGB_TILE_MODE8 0x264C -#define mmGB_TILE_MODE9 0x264D -#define mmGB_TILE_MODE10 0x264E -#define mmGB_TILE_MODE11 0x264F -#define mmGB_TILE_MODE12 0x2650 -#define mmGB_TILE_MODE13 0x2651 -#define mmGB_TILE_MODE14 0x2652 -#define mmGB_TILE_MODE15 0x2653 -#define mmGB_TILE_MODE16 0x2654 -#define mmGB_TILE_MODE17 0x2655 -#define mmGB_TILE_MODE18 0x2656 -#define mmGB_TILE_MODE19 0x2657 -#define mmGB_TILE_MODE20 0x2658 -#define mmGB_TILE_MODE21 0x2659 -#define mmGB_TILE_MODE22 0x265A -#define mmGB_TILE_MODE23 0x265B -#define mmGB_TILE_MODE24 0x265C -#define mmGB_TILE_MODE25 0x265D -#define mmGB_TILE_MODE26 0x265E -#define mmGB_TILE_MODE27 0x265F -#define mmGB_TILE_MODE28 0x2660 -#define mmGB_TILE_MODE29 0x2661 -#define mmGB_TILE_MODE30 0x2662 -#define mmGB_TILE_MODE31 0x2663 -#define mmGB_MACROTILE_MODE0 0x2664 -#define mmGB_MACROTILE_MODE1 0x2665 -#define mmGB_MACROTILE_MODE2 0x2666 -#define mmGB_MACROTILE_MODE3 0x2667 -#define mmGB_MACROTILE_MODE4 0x2668 -#define mmGB_MACROTILE_MODE5 0x2669 -#define mmGB_MACROTILE_MODE6 0x266A -#define mmGB_MACROTILE_MODE7 0x266B -#define mmGB_MACROTILE_MODE8 0x266C -#define mmGB_MACROTILE_MODE9 0x266D -#define mmGB_MACROTILE_MODE10 0x266E -#define mmGB_MACROTILE_MODE11 0x266F -#define mmGB_MACROTILE_MODE12 0x2670 -#define mmGB_MACROTILE_MODE13 0x2671 -#define mmGB_MACROTILE_MODE14 0x2672 -#define mmGB_MACROTILE_MODE15 0x2673 -#define mmGB_EDC_MODE 0x307E -#define mmCC_GC_EDC_CONFIG 0x3098 -#define mmRAS_SIGNATURE_CONTROL 0x3380 -#define mmRAS_SIGNATURE_MASK 0x3381 -#define mmRAS_SX_SIGNATURE0 0x3382 -#define mmRAS_SX_SIGNATURE1 0x3383 -#define mmRAS_SX_SIGNATURE2 0x3384 -#define mmRAS_SX_SIGNATURE3 0x3385 -#define mmRAS_DB_SIGNATURE0 0x338B -#define mmRAS_PA_SIGNATURE0 0x338C -#define mmRAS_VGT_SIGNATURE0 0x338D -#define mmRAS_SQ_SIGNATURE0 0x338E -#define mmRAS_SC_SIGNATURE0 0x338F -#define mmRAS_SC_SIGNATURE1 0x3390 -#define mmRAS_SC_SIGNATURE2 0x3391 -#define mmRAS_SC_SIGNATURE3 0x3392 -#define mmRAS_SC_SIGNATURE4 0x3393 -#define mmRAS_SC_SIGNATURE5 0x3394 -#define mmRAS_SC_SIGNATURE6 0x3395 -#define mmRAS_SC_SIGNATURE7 0x3396 -#define mmRAS_IA_SIGNATURE0 0x3397 -#define mmRAS_IA_SIGNATURE1 0x3398 -#define mmRAS_SPI_SIGNATURE0 0x3399 -#define mmRAS_SPI_SIGNATURE1 0x339A -#define mmRAS_TA_SIGNATURE0 0x339B -#define mmRAS_TD_SIGNATURE0 0x339C -#define mmRAS_CB_SIGNATURE0 0x339D -#define mmRAS_BCI_SIGNATURE0 0x339E -#define mmRAS_BCI_SIGNATURE1 0x339F -#define mmRAS_TA_SIGNATURE1 0x33A0 - - -// Registers from TP block - -#define mmTD_CNTL 0x2525 -#define mmTD_STATUS 0x2526 -#define mmTD_DEBUG_INDEX 0x2528 -#define mmTD_DEBUG_DATA 0x2529 -#define mmTD_DSM_CNTL 0x252F -#define mmTD_DSM_CNTL2 0x2530 -#define mmTD_SCRATCH 0x2533 -#define mmTA_CNTL 0x2541 -#define mmTA_CNTL_AUX 0x2542 -#define mmTA_RESERVED_010C 0x2543 -#define mmTA_GRAD_ADJ 0x2544 -#define mmTA_STATUS 0x2548 -#define mmTA_DEBUG_INDEX 0x254C -#define mmTA_DEBUG_DATA 0x254D -#define mmTA_SCRATCH 0x2564 -#define mmTCP_INVALIDATE 0x2B00 -#define mmTCP_STATUS 0x2B01 -#define mmTCP_CNTL 0x2B02 -#define mmTCP_CHAN_STEER_LO 0x2B03 -#define mmTCP_CHAN_STEER_HI 0x2B04 -#define mmTCP_ADDR_CONFIG 0x2B05 -#define mmTCP_CREDIT 0x2B06 -#define mmTCP_DEBUG_INDEX 0x2B07 -#define mmTCP_DEBUG_DATA 0x2B08 -#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2B16 -#define mmTCP_EDC_CNT 0x2B17 -#define mmTC_CFG_L1_LOAD_POLICY0 0x2B1A -#define mmTC_CFG_L1_LOAD_POLICY1 0x2B1B -#define mmTC_CFG_L1_STORE_POLICY 0x2B1C -#define mmTC_CFG_L2_LOAD_POLICY0 0x2B1D -#define mmTC_CFG_L2_LOAD_POLICY1 0x2B1E -#define mmTC_CFG_L2_STORE_POLICY0 0x2B1F -#define mmTC_CFG_L2_STORE_POLICY1 0x2B20 -#define mmTC_CFG_L2_ATOMIC_POLICY 0x2B21 -#define mmTC_CFG_L1_VOLATILE 0x2B22 -#define mmTC_CFG_L2_VOLATILE 0x2B23 -#define mmTCI_STATUS 0x2B61 -#define mmTCI_CNTL_1 0x2B62 -#define mmTCI_CNTL_2 0x2B63 -#define mmTCP_WATCH0_ADDR_H 0x32A0 -#define mmTCP_WATCH1_ADDR_H 0x32A3 -#define mmTCP_WATCH2_ADDR_H 0x32A6 -#define mmTCP_WATCH3_ADDR_H 0x32A9 -#define mmTCP_WATCH0_ADDR_L 0x32A1 -#define mmTCP_WATCH1_ADDR_L 0x32A4 -#define mmTCP_WATCH2_ADDR_L 0x32A7 -#define mmTCP_WATCH3_ADDR_L 0x32AA -#define mmTCP_WATCH0_CNTL 0x32A2 -#define mmTCP_WATCH1_CNTL 0x32A5 -#define mmTCP_WATCH2_CNTL 0x32A8 -#define mmTCP_WATCH3_CNTL 0x32AB -#define mmTCP_GATCL1_CNTL 0x32B0 -#define mmTCP_ATC_EDC_GATCL1_CNT 0x32B1 -#define mmTCP_GATCL1_DSM_CNTL 0x32B2 -#define mmTCP_CNTL2 0x32B4 -#define mmTCP_UTCL1_CNTL1 0x32B5 -#define mmTCP_UTCL1_CNTL2 0x32B6 -#define mmTCP_UTCL1_STATUS 0x32B7 -#define mmTCP_PERFCOUNTER_FILTER 0x32B9 -#define mmTCP_PERFCOUNTER_FILTER_EN 0x32BA -#define mmTA_BC_BASE_ADDR 0xA020 -#define mmTA_BC_BASE_ADDR_HI 0xA021 -#define mmTA_CS_BC_BASE_ADDR 0xC380 -#define mmTA_CS_BC_BASE_ADDR_HI 0xC381 -#define mmTA_GRAD_ADJ_UCONFIG 0xC382 -#define mmTD_PERFCOUNTER0_LO 0xD300 -#define mmTD_PERFCOUNTER1_LO 0xD302 -#define mmTD_PERFCOUNTER0_HI 0xD301 -#define mmTD_PERFCOUNTER1_HI 0xD303 -#define mmTA_PERFCOUNTER0_LO 0xD2C0 -#define mmTA_PERFCOUNTER1_LO 0xD2C2 -#define mmTA_PERFCOUNTER0_HI 0xD2C1 -#define mmTA_PERFCOUNTER1_HI 0xD2C3 -#define mmTCP_PERFCOUNTER0_LO 0xD340 -#define mmTCP_PERFCOUNTER1_LO 0xD342 -#define mmTCP_PERFCOUNTER2_LO 0xD344 -#define mmTCP_PERFCOUNTER3_LO 0xD346 -#define mmTCP_PERFCOUNTER0_HI 0xD341 -#define mmTCP_PERFCOUNTER1_HI 0xD343 -#define mmTCP_PERFCOUNTER2_HI 0xD345 -#define mmTCP_PERFCOUNTER3_HI 0xD347 -#define mmTD_PERFCOUNTER0_SELECT 0xDB00 -#define mmTD_PERFCOUNTER1_SELECT 0xDB02 -#define mmTD_PERFCOUNTER0_SELECT1 0xDB01 -#define mmTA_PERFCOUNTER0_SELECT 0xDAC0 -#define mmTA_PERFCOUNTER1_SELECT 0xDAC2 -#define mmTA_PERFCOUNTER0_SELECT1 0xDAC1 -#define mmTCP_PERFCOUNTER0_SELECT 0xDB40 -#define mmTCP_PERFCOUNTER1_SELECT 0xDB42 -#define mmTCP_PERFCOUNTER0_SELECT1 0xDB41 -#define mmTCP_PERFCOUNTER1_SELECT1 0xDB43 -#define mmTCP_PERFCOUNTER2_SELECT 0xDB44 -#define mmTCP_PERFCOUNTER3_SELECT 0xDB45 -#define mmTD_CGTT_CTRL 0xF09C -#define mmTA_CGTT_CTRL 0xF09D -#define mmCGTT_TCPI_CLK_CTRL 0xF09E -#define mmCGTT_TCPF_CLK_CTRL 0xF0C1 -#define mmCGTT_TCI_CLK_CTRL 0xF09F - - -// Registers from TCC block - -#define mmTCC_CTRL 0x2B80 -#define mmTCC_CTRL2 0x2B81 -#define mmTCC_EDC_CNT 0x2B82 -#define mmTCC_EDC_CNT2 0x2B83 -#define mmTCC_REDUNDANCY 0x2B84 -#define mmTCC_EXE_DISABLE 0x2B85 -#define mmTCC_DSM_CNTL 0x2B86 -#define mmTCC_DSM_CNTLA 0x2B87 -#define mmTCC_DSM_CNTL2 0x2B88 -#define mmTCC_DSM_CNTL2A 0x2B89 -#define mmTCC_DSM_CNTL2B 0x2B8A -#define mmTCC_WBINVL2 0x2B8B -#define mmTCC_SOFT_RESET 0x2B8C -#define mmTCA_CTRL 0x2BC0 -#define mmTCA_BURST_MASK 0x2BC1 -#define mmTCA_BURST_CTRL 0x2BC2 -#define mmTCA_DSM_CNTL 0x2BC3 -#define mmTCA_DSM_CNTL2 0x2BC4 -#define mmTCA_EDC_CNT 0x2BC5 -#define mmTCC_PERFCOUNTER0_LO 0xD380 -#define mmTCC_PERFCOUNTER1_LO 0xD382 -#define mmTCC_PERFCOUNTER2_LO 0xD384 -#define mmTCC_PERFCOUNTER3_LO 0xD386 -#define mmTCC_PERFCOUNTER0_HI 0xD381 -#define mmTCC_PERFCOUNTER1_HI 0xD383 -#define mmTCC_PERFCOUNTER2_HI 0xD385 -#define mmTCC_PERFCOUNTER3_HI 0xD387 -#define mmTCA_PERFCOUNTER0_LO 0xD390 -#define mmTCA_PERFCOUNTER1_LO 0xD392 -#define mmTCA_PERFCOUNTER2_LO 0xD394 -#define mmTCA_PERFCOUNTER3_LO 0xD396 -#define mmTCA_PERFCOUNTER0_HI 0xD391 -#define mmTCA_PERFCOUNTER1_HI 0xD393 -#define mmTCA_PERFCOUNTER2_HI 0xD395 -#define mmTCA_PERFCOUNTER3_HI 0xD397 -#define mmTCC_PERFCOUNTER0_SELECT 0xDB80 -#define mmTCC_PERFCOUNTER1_SELECT 0xDB82 -#define mmTCC_PERFCOUNTER0_SELECT1 0xDB81 -#define mmTCC_PERFCOUNTER1_SELECT1 0xDB83 -#define mmTCC_PERFCOUNTER2_SELECT 0xDB84 -#define mmTCC_PERFCOUNTER3_SELECT 0xDB85 -#define mmTCA_PERFCOUNTER0_SELECT 0xDB90 -#define mmTCA_PERFCOUNTER1_SELECT 0xDB92 -#define mmTCA_PERFCOUNTER0_SELECT1 0xDB91 -#define mmTCA_PERFCOUNTER1_SELECT1 0xDB93 -#define mmTCA_PERFCOUNTER2_SELECT 0xDB94 -#define mmTCA_PERFCOUNTER3_SELECT 0xDB95 -#define mmTCC_CGTT_SCLK_CTRL 0xF0AC -#define mmTCA_CGTT_SCLK_CTRL 0xF0AD - - -// Registers from GRBM block - -#define mmGRBM_CNTL 0x2000 -#define mmGRBM_SKEW_CNTL 0x2001 -#define mmGRBM_PWR_CNTL 0x2003 -#define mmGRBM_STATUS 0x2004 -#define mmGRBM_STATUS2 0x2002 -#define mmGRBM_STATUS_SE0 0x2005 -#define mmGRBM_STATUS_SE1 0x2006 -#define mmGRBM_STATUS_SE2 0x200E -#define mmGRBM_STATUS_SE3 0x200F -#define mmGRBM_SOFT_RESET 0x2008 -#define mmGRBM_DEBUG_CNTL 0x2009 -#define mmGRBM_DEBUG_DATA 0x200A -#define mmGRBM_CGTT_CLK_CNTL 0x200B -#define mmGRBM_GFX_CLKEN_CNTL 0x200C -#define mmGRBM_WAIT_IDLE_CLOCKS 0x200D -#define mmGRBM_DEBUG 0x2014 -#define mmGRBM_DEBUG_SNAPSHOT 0x2015 -#define mmGRBM_RSMU_READ_ERROR 0x2028 -#define mmGRBM_CHICKEN_BITS 0x2029 -#define mmGRBM_READ_ERROR 0x2016 -#define mmGRBM_READ_ERROR2 0x2017 -#define mmGRBM_INT_CNTL 0x2018 -#define mmGRBM_TRAP_OP 0x2019 -#define mmGRBM_TRAP_ADDR 0x201A -#define mmGRBM_TRAP_ADDR_MSK 0x201B -#define mmGRBM_TRAP_WD 0x201C -#define mmGRBM_TRAP_WD_MSK 0x201D -#define mmGRBM_DSM_BYPASS 0x201E -#define mmGRBM_IOV_ERROR 0x2020 -#define mmGRBM_WRITE_ERROR 0x201F -#define mmGRBM_GFX_CNTL 0x2022 -#define mmGRBM_RSMU_CFG 0x2023 -#define mmGRBM_IH_CREDIT 0x2024 -#define mmGRBM_PWR_CNTL2 0x2025 -#define mmGRBM_UTCL2_INVAL_RANGE_START 0x2026 -#define mmGRBM_UTCL2_INVAL_RANGE_END 0x2027 -#define mmGRBM_CHIP_REVISION 0x2021 -#define mmGRBM_SCRATCH_REG0 0x2040 -#define mmGRBM_SCRATCH_REG1 0x2041 -#define mmGRBM_SCRATCH_REG2 0x2042 -#define mmGRBM_SCRATCH_REG3 0x2043 -#define mmGRBM_SCRATCH_REG4 0x2044 -#define mmGRBM_SCRATCH_REG5 0x2045 -#define mmGRBM_SCRATCH_REG6 0x2046 -#define mmGRBM_SCRATCH_REG7 0x2047 -#define mmDEBUG_INDEX 0x203C -#define mmDEBUG_DATA 0x203D -#define mmGRBM_NOWHERE 0x203F -#define mmGRBM_GFX_INDEX 0xC200 -#define mmGRBM_PERFCOUNTER0_LO 0xD040 -#define mmGRBM_PERFCOUNTER0_HI 0xD041 -#define mmGRBM_PERFCOUNTER1_LO 0xD043 -#define mmGRBM_PERFCOUNTER1_HI 0xD044 -#define mmGRBM_SE0_PERFCOUNTER_LO 0xD045 -#define mmGRBM_SE0_PERFCOUNTER_HI 0xD046 -#define mmGRBM_SE1_PERFCOUNTER_LO 0xD047 -#define mmGRBM_SE1_PERFCOUNTER_HI 0xD048 -#define mmGRBM_SE2_PERFCOUNTER_LO 0xD049 -#define mmGRBM_SE2_PERFCOUNTER_HI 0xD04A -#define mmGRBM_SE3_PERFCOUNTER_LO 0xD04B -#define mmGRBM_SE3_PERFCOUNTER_HI 0xD04C -#define mmGRBM_PERFCOUNTER0_SELECT 0xD840 -#define mmGRBM_PERFCOUNTER1_SELECT 0xD841 -#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xD842 -#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xD843 -#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xD844 -#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xD845 -#define mmGRBM_HYP_CAM_INDEX 0xFA04 -#define mmGRBM_CAM_INDEX 0xFA04 -#define mmGRBM_HYP_CAM_DATA 0xFA05 -#define mmGRBM_CAM_DATA 0xFA05 -#define mmGRBM_GFX_CNTL_SR_SELECT 0xFA02 -#define mmGRBM_GFX_CNTL_SR_DATA 0xFA03 -#define mmGRBM_GFX_INDEX_SR_SELECT 0xFA00 -#define mmGRBM_GFX_INDEX_SR_DATA 0xFA01 -#define mmGRBM_SRCID_CAM_INDEX 0xFE00 -#define mmGRBM_SRCID_CAM_DATA 0xFE01 -#define mmGRBM_PF_ONLY_RANGE0 0xFE02 -#define mmGRBM_PF_ONLY_RANGE1 0xFE03 -#define mmGRBM_PF_ONLY_RANGE2 0xFE04 -#define mmGRBM_PF_ONLY_RANGE3 0xFE05 -#define mmGRBM_PF_ONLY_RANGE4 0xFE06 -#define mmGRBM_PF_ONLY_RANGE5 0xFE07 -#define mmGRBM_PF_ONLY_RANGE6 0xFE08 -#define mmGRBM_PF_ONLY_RANGE7 0xFE09 -#define mmGRBM_IOV_ENABLE 0xFE0A - - -// Registers from CP block - -#define mmCP_CPC_DEBUG_CNTL 0x2080 -#define mmCP_CPC_DEBUG_DATA 0x2081 -#define mmCP_CPF_DEBUG_CNTL 0x2082 -#define mmCP_CPF_DEBUG_DATA 0x2083 -#define mmCP_CPC_STATUS 0x2084 -#define mmCP_CPC_BUSY_STAT 0x2085 -#define mmCP_CPC_STALLED_STAT1 0x2086 -#define mmCP_CPF_STATUS 0x2087 -#define mmCP_CPF_BUSY_STAT 0x2088 -#define mmCP_CPF_STALLED_STAT1 0x2089 -#define mmCP_CPC_GRBM_FREE_COUNT 0x208B -#define mmCP_CPC_PRIV_VIOLATION_ADDR 0x208C -#define mmCP_MEC_CNTL 0x208D -#define mmCP_MEC_ME1_HEADER_DUMP 0x208E -#define mmCP_MEC_ME2_HEADER_DUMP 0x208F -#define mmCP_CPC_SCRATCH_INDEX 0x2090 -#define mmCP_CPC_SCRATCH_DATA 0x2091 -#define mmCP_CPF_GRBM_FREE_COUNT 0x2092 -#define mmCP_CPC_HALT_HYST_COUNT 0x20A7 -#define mmCP_PRT_LOD_STATS_CNTL0 0x20AD -#define mmCP_PRT_LOD_STATS_CNTL1 0x20AE -#define mmCP_PRT_LOD_STATS_CNTL2 0x20AF -#define mmCP_PRT_LOD_STATS_CNTL3 0x20B0 -#define mmCP_CE_COMPARE_COUNT 0x20C0 -#define mmCP_CE_DE_COUNT 0x20C1 -#define mmCP_DE_CE_COUNT 0x20C2 -#define mmCP_DE_LAST_INVAL_COUNT 0x20C3 -#define mmCP_DE_DE_COUNT 0x20C4 -#define mmCP_STALLED_STAT1 0x219D -#define mmCP_STALLED_STAT2 0x219E -#define mmCP_STALLED_STAT3 0x219C -#define mmCP_BUSY_STAT 0x219F -#define mmCP_STAT 0x21A0 -#define mmCP_ME_HEADER_DUMP 0x21A1 -#define mmCP_PFP_HEADER_DUMP 0x21A2 -#define mmCP_GRBM_FREE_COUNT 0x21A3 -#define mmCP_CE_HEADER_DUMP 0x21A4 -#define mmCP_PFP_INSTR_PNTR 0x21A5 -#define mmCP_ME_INSTR_PNTR 0x21A6 -#define mmCP_CE_INSTR_PNTR 0x21A7 -#define mmCP_MEC1_INSTR_PNTR 0x21A8 -#define mmCP_MEC2_INSTR_PNTR 0x21A9 -#define mmCP_CSF_STAT 0x21B4 -#define mmCP_ME_CNTL 0x21B6 -#define mmCP_CNTX_STAT 0x21B8 -#define mmCP_ME_PREEMPTION 0x21B9 -#define mmCP_RB0_RPTR 0x21C0 -#define mmCP_RB_RPTR 0x21C0 -#define mmCP_RB1_RPTR 0x21BF -#define mmCP_RB2_RPTR 0x21BE -#define mmCP_RB_WPTR_DELAY 0x21C1 -#define mmCP_RB_WPTR_POLL_CNTL 0x21C2 -#define mmCP_ROQ_THRESHOLDS 0x21BC -#define mmCP_MEQ_STQ_THRESHOLD 0x21BD -#define mmCP_ROQ1_THRESHOLDS 0x21D5 -#define mmCP_ROQ2_THRESHOLDS 0x21D6 -#define mmCP_STQ_THRESHOLDS 0x21D7 -#define mmCP_QUEUE_THRESHOLDS 0x21D8 -#define mmCP_MEQ_THRESHOLDS 0x21D9 -#define mmCP_ROQ_AVAIL 0x21DA -#define mmCP_STQ_AVAIL 0x21DB -#define mmCP_ROQ2_AVAIL 0x21DC -#define mmCP_MEQ_AVAIL 0x21DD -#define mmCP_CMD_INDEX 0x21DE -#define mmCP_CMD_DATA 0x21DF -#define mmCP_ROQ_RB_STAT 0x21E0 -#define mmCP_ROQ_IB1_STAT 0x21E1 -#define mmCP_ROQ_IB2_STAT 0x21E2 -#define mmCP_STQ_STAT 0x21E3 -#define mmCP_STQ_WR_STAT 0x21E4 -#define mmCP_MEQ_STAT 0x21E5 -#define mmCP_CEQ1_AVAIL 0x21E6 -#define mmCP_CEQ2_AVAIL 0x21E7 -#define mmCP_CE_ROQ_RB_STAT 0x21E8 -#define mmCP_CE_ROQ_IB1_STAT 0x21E9 -#define mmCP_CE_ROQ_IB2_STAT 0x21EA -#define mmCP_INT_STAT_DEBUG 0x21F7 -#define mmCP_DEBUG_CNTL 0x21F8 -#define mmCP_DEBUG_DATA 0x21F9 -#define mmCP_PRIV_VIOLATION_ADDR 0x21FA -#define mmCP_DFY_CNTL 0x3020 -#define mmCP_DFY_STAT 0x3021 -#define mmCP_DFY_ADDR_HI 0x3022 -#define mmCP_DFY_ADDR_LO 0x3023 -#define mmCP_DFY_DATA_0 0x3024 -#define mmCP_DFY_DATA_1 0x3025 -#define mmCP_DFY_DATA_2 0x3026 -#define mmCP_DFY_DATA_3 0x3027 -#define mmCP_DFY_DATA_4 0x3028 -#define mmCP_DFY_DATA_5 0x3029 -#define mmCP_DFY_DATA_6 0x302A -#define mmCP_DFY_DATA_7 0x302B -#define mmCP_DFY_DATA_8 0x302C -#define mmCP_DFY_DATA_9 0x302D -#define mmCP_DFY_DATA_10 0x302E -#define mmCP_DFY_DATA_11 0x302F -#define mmCP_DFY_DATA_12 0x3030 -#define mmCP_DFY_DATA_13 0x3031 -#define mmCP_DFY_DATA_14 0x3032 -#define mmCP_DFY_DATA_15 0x3033 -#define mmCP_DFY_CMD 0x3034 -#define mmCP_EOPQ_WAIT_TIME 0x3035 -#define mmCP_CPC_MGCG_SYNC_CNTL 0x3036 -#define mmCPC_INT_INFO 0x3037 -#define mmCPC_INT_ADDR 0x3039 -#define mmCPC_INT_PASID 0x303A -#define mmCP_GFX_ERROR 0x303B -#define mmCPG_UTCL1_CNTL 0x303C -#define mmCPC_UTCL1_CNTL 0x303D -#define mmCPF_UTCL1_CNTL 0x303E -#define mmCP_AQL_SMM_STATUS 0x303F -#define mmCP_RB0_BASE 0x3040 -#define mmCP_RB0_BASE_HI 0x30B1 -#define mmCP_RB_BASE 0x3040 -#define mmCP_RB1_BASE 0x3060 -#define mmCP_RB1_BASE_HI 0x30B2 -#define mmCP_RB2_BASE 0x3065 -#define mmCP_RB0_CNTL 0x3041 -#define mmCP_RB_CNTL 0x3041 -#define mmCP_RB1_CNTL 0x3061 -#define mmCP_RB2_CNTL 0x3066 -#define mmCP_RB_RPTR_WR 0x3042 -#define mmCP_RB0_RPTR_ADDR 0x3043 -#define mmCP_RB_RPTR_ADDR 0x3043 -#define mmCP_RB1_RPTR_ADDR 0x3062 -#define mmCP_RB2_RPTR_ADDR 0x3067 -#define mmCP_RB0_RPTR_ADDR_HI 0x3044 -#define mmCP_RB_RPTR_ADDR_HI 0x3044 -#define mmCP_RB1_RPTR_ADDR_HI 0x3063 -#define mmCP_RB2_RPTR_ADDR_HI 0x3068 -#define mmCP_RB0_ACTIVE 0x3069 -#define mmCP_RB_ACTIVE 0x3069 -#define mmCP_RB0_BUFSZ_MASK 0x3045 -#define mmCP_RB_BUFSZ_MASK 0x3045 -#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 -#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 -#define mmGC_PRIV_MODE 0x3048 -#define mmCP_INT_CNTL 0x3049 -#define mmCP_INT_CNTL_RING0 0x306A -#define mmCP_INT_CNTL_RING1 0x306B -#define mmCP_INT_CNTL_RING2 0x306C -#define mmCP_INT_STATUS 0x304A -#define mmCP_INT_STATUS_RING0 0x306D -#define mmCP_INT_STATUS_RING1 0x306E -#define mmCP_INT_STATUS_RING2 0x306F -#define mmCP_DEVICE_ID 0x304B -#define mmCP_RING_PRIORITY_CNTS 0x304C -#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304C -#define mmCP_RING0_PRIORITY 0x304D -#define mmCP_ME0_PIPE0_PRIORITY 0x304D -#define mmCP_RING1_PRIORITY 0x304E -#define mmCP_ME0_PIPE1_PRIORITY 0x304E -#define mmCP_RING2_PRIORITY 0x304F -#define mmCP_ME0_PIPE2_PRIORITY 0x304F -#define mmCP_FATAL_ERROR 0x3050 -#define mmCP_RB_VMID 0x3051 -#define mmCP_ME0_PIPE0_VMID 0x3052 -#define mmCP_ME0_PIPE1_VMID 0x3053 -#define mmCP_RB0_WPTR 0x3054 -#define mmCP_RB_WPTR 0x3054 -#define mmCP_RB0_WPTR_HI 0x3055 -#define mmCP_RB_WPTR_HI 0x3055 -#define mmCP_RB1_WPTR 0x3056 -#define mmCP_RB1_WPTR_HI 0x3057 -#define mmCP_RB2_WPTR 0x3058 -#define mmCP_RB_DOORBELL_CONTROL 0x3059 -#define mmCP_RB_DOORBELL_RANGE_LOWER 0x305A -#define mmCP_RB_DOORBELL_RANGE_UPPER 0x305B -#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x305C -#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x305D -#define mmCPG_UTCL1_ERROR 0x305E -#define mmCPC_UTCL1_ERROR 0x305F -#define mmCP_IB1_PRIV_BASE_LO 0x3070 -#define mmCP_IB1_PRIV_BASE_HI 0x3071 -#define mmCP_IB1_PRIV_BUFSZ 0x3072 -#define mmCP_ME_F32_INTERRUPT 0x3073 -#define mmCP_PFP_F32_INTERRUPT 0x3074 -#define mmCP_CE_F32_INTERRUPT 0x3075 -#define mmCP_MEC1_F32_INTERRUPT 0x3076 -#define mmCP_MEC2_F32_INTERRUPT 0x3077 -#define mmCP_MEC1_F32_INT_DIS 0x30BD -#define mmCP_MEC2_F32_INT_DIS 0x30BE -#define mmCP_VIRT_STATUS 0x3038 -#define mmCP_PWR_CNTL 0x3078 -#define mmCP_MEM_SLP_CNTL 0x3079 -#define mmCP_ECC_FIRSTOCCURRENCE 0x307A -#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307B -#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307C -#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307D -#define mmCP_DEBUG 0x307F -#define mmCP_CPF_DEBUG 0x3080 -#define mmCP_CPC_DEBUG 0x3081 -#define mmCP_PQ_WPTR_POLL_CNTL 0x3083 -#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 -#define mmCPC_INT_CNTL 0x30B4 -#define mmCP_ME1_PIPE0_INT_CNTL 0x3085 -#define mmCP_ME1_PIPE1_INT_CNTL 0x3086 -#define mmCP_ME1_PIPE2_INT_CNTL 0x3087 -#define mmCP_ME1_PIPE3_INT_CNTL 0x3088 -#define mmCP_ME2_PIPE0_INT_CNTL 0x3089 -#define mmCP_ME2_PIPE1_INT_CNTL 0x308A -#define mmCP_ME2_PIPE2_INT_CNTL 0x308B -#define mmCP_ME2_PIPE3_INT_CNTL 0x308C -#define mmCPC_INT_STATUS 0x30B5 -#define mmCP_ME1_PIPE0_INT_STATUS 0x308D -#define mmCP_ME1_PIPE1_INT_STATUS 0x308E -#define mmCP_ME1_PIPE2_INT_STATUS 0x308F -#define mmCP_ME1_PIPE3_INT_STATUS 0x3090 -#define mmCP_ME2_PIPE0_INT_STATUS 0x3091 -#define mmCP_ME2_PIPE1_INT_STATUS 0x3092 -#define mmCP_ME2_PIPE2_INT_STATUS 0x3093 -#define mmCP_ME2_PIPE3_INT_STATUS 0x3094 -#define mmCP_ME1_INT_STAT_DEBUG 0x3095 -#define mmCP_ME2_INT_STAT_DEBUG 0x3096 -#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 -#define mmCP_ME1_PIPE0_PRIORITY 0x309A -#define mmCP_ME1_PIPE1_PRIORITY 0x309B -#define mmCP_ME1_PIPE2_PRIORITY 0x309C -#define mmCP_ME1_PIPE3_PRIORITY 0x309D -#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309E -#define mmCP_ME2_PIPE0_PRIORITY 0x309F -#define mmCP_ME2_PIPE1_PRIORITY 0x30A0 -#define mmCP_ME2_PIPE2_PRIORITY 0x30A1 -#define mmCP_ME2_PIPE3_PRIORITY 0x30A2 -#define mmCP_CE_PRGRM_CNTR_START 0x30A3 -#define mmCP_PFP_PRGRM_CNTR_START 0x30A4 -#define mmCP_ME_PRGRM_CNTR_START 0x30A5 -#define mmCP_MEC1_PRGRM_CNTR_START 0x30A6 -#define mmCP_MEC2_PRGRM_CNTR_START 0x30A7 -#define mmCP_CE_INTR_ROUTINE_START 0x30A8 -#define mmCP_PFP_INTR_ROUTINE_START 0x30A9 -#define mmCP_ME_INTR_ROUTINE_START 0x30AA -#define mmCP_MEC1_INTR_ROUTINE_START 0x30AB -#define mmCP_MEC2_INTR_ROUTINE_START 0x30AC -#define mmCP_CONTEXT_CNTL 0x30AD -#define mmCP_MAX_CONTEXT 0x30AE -#define mmCP_IQ_WAIT_TIME1 0x30AF -#define mmCP_IQ_WAIT_TIME2 0x30B0 -#define mmCP_VMID_RESET 0x30B3 -#define mmCP_VMID_PREEMPT 0x30B6 -#define mmCP_VMID_STATUS 0x30BF -#define mmCPC_INT_CNTX_ID 0x30B7 -#define mmCP_PQ_STATUS 0x30B8 -#define mmCP_CPC_IC_BASE_LO 0x30B9 -#define mmCP_CPC_IC_BASE_HI 0x30BA -#define mmCP_CPC_IC_BASE_CNTL 0x30BB -#define mmCP_CPC_IC_OP_CNTL 0x30BC -#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x3180 -#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x3181 -#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x3182 -#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x3183 -#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x3184 -#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x3185 -#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x3186 -#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x3187 -#define mmCP_RB_DOORBELL_CLEAR 0x3188 -#define mmCP_GFX_MQD_CONTROL 0x31A0 -#define mmCP_GFX_MQD_BASE_ADDR 0x31A1 -#define mmCP_GFX_MQD_BASE_ADDR_HI 0x31A2 -#define mmCP_RB_STATUS 0x31A3 -#define mmCPG_UTCL1_STATUS 0x31B4 -#define mmCPC_UTCL1_STATUS 0x31B5 -#define mmCPF_UTCL1_STATUS 0x31B6 -#define mmCP_SD_CNTL 0x31B7 -#define mmCP_TMZ_CNTL 0x31B8 -#define mmCP_SOFT_RESET_CNTL 0x31B9 -#define mmCP_CPC_GFX_CNTL 0x31BA -#define mmCP_SECURE_TMZ 0x31BB -#define mmCP_GFX_SECURE_REQ0 0x31BC -#define mmCP_HQD_SECURE_REQ0 0x3200 -#define mmCP_HQD_GFX_CONTROL 0x323E -#define mmCP_HQD_GFX_STATUS 0x323F -#define mmCP_HPD_ROQ_OFFSETS 0x3240 -#define mmCP_HPD_STATUS0 0x3241 -#define mmCP_HPD_UTCL1_CNTL 0x3242 -#define mmCP_HPD_UTCL1_ERROR 0x3243 -#define mmCP_HPD_UTCL1_ERROR_ADDR 0x3244 -#define mmCP_MQD_BASE_ADDR 0x3245 -#define mmCP_MQD_BASE_ADDR_HI 0x3246 -#define mmCP_HQD_ACTIVE 0x3247 -#define mmCP_HQD_VMID 0x3248 -#define mmCP_HQD_PERSISTENT_STATE 0x3249 -#define mmCP_HQD_PIPE_PRIORITY 0x324A -#define mmCP_HQD_QUEUE_PRIORITY 0x324B -#define mmCP_HQD_QUANTUM 0x324C -#define mmCP_HQD_PQ_BASE 0x324D -#define mmCP_HQD_PQ_BASE_HI 0x324E -#define mmCP_HQD_PQ_RPTR 0x324F -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 -#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 -#define mmCP_HQD_PQ_CONTROL 0x3256 -#define mmCP_HQD_IB_BASE_ADDR 0x3257 -#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 -#define mmCP_HQD_IB_RPTR 0x3259 -#define mmCP_HQD_IB_CONTROL 0x325A -#define mmCP_HQD_IQ_TIMER 0x325B -#define mmCP_HQD_IQ_RPTR 0x325C -#define mmCP_HQD_DEQUEUE_REQUEST 0x325D -#define mmCP_HQD_DMA_OFFLOAD 0x325E -#define mmCP_HQD_OFFLOAD 0x325E -#define mmCP_HQD_SEMA_CMD 0x325F -#define mmCP_HQD_MSG_TYPE 0x3260 -#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 -#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 -#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 -#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 -#define mmCP_HQD_HQ_SCHEDULER0 0x3265 -#define mmCP_HQD_HQ_STATUS0 0x3265 -#define mmCP_HQD_HQ_SCHEDULER1 0x3266 -#define mmCP_HQD_HQ_CONTROL0 0x3266 -#define mmCP_MQD_CONTROL 0x3267 -#define mmCP_HQD_HQ_STATUS1 0x3268 -#define mmCP_HQD_HQ_CONTROL1 0x3269 -#define mmCP_HQD_EOP_BASE_ADDR 0x326A -#define mmCP_HQD_EOP_BASE_ADDR_HI 0x326B -#define mmCP_HQD_EOP_CONTROL 0x326C -#define mmCP_HQD_EOP_RPTR 0x326D -#define mmCP_HQD_EOP_WPTR 0x326E -#define mmCP_HQD_EOP_EVENTS 0x326F -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x3270 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x3271 -#define mmCP_HQD_CTX_SAVE_CONTROL 0x3272 -#define mmCP_HQD_CNTL_STACK_OFFSET 0x3273 -#define mmCP_HQD_CNTL_STACK_SIZE 0x3274 -#define mmCP_HQD_WG_STATE_OFFSET 0x3275 -#define mmCP_HQD_CTX_SAVE_SIZE 0x3276 -#define mmCP_HQD_GDS_RESOURCE_STATE 0x3277 -#define mmCP_HQD_ERROR 0x3278 -#define mmCP_HQD_EOP_WPTR_MEM 0x3279 -#define mmCP_HQD_AQL_CONTROL 0x327A -#define mmCP_HQD_PQ_WPTR_LO 0x327B -#define mmCP_HQD_PQ_WPTR_HI 0x327C -#define mmCOHER_DEST_BASE_0 0xA092 -#define mmCOHER_DEST_BASE_1 0xA093 -#define mmCOHER_DEST_BASE_2 0xA07E -#define mmCOHER_DEST_BASE_3 0xA07F -#define mmCOHER_DEST_BASE_HI_0 0xA07A -#define mmCOHER_DEST_BASE_HI_1 0xA07B -#define mmCOHER_DEST_BASE_HI_2 0xA07C -#define mmCOHER_DEST_BASE_HI_3 0xA07D -#define mmCP_PERFMON_CNTX_CNTL 0xA0D8 -#define mmCP_RINGID 0xA0D9 -#define mmCP_PIPEID 0xA0D9 -#define mmCP_VMID 0xA0DA -#define mmCP_EOP_DONE_EVENT_CNTL 0xC0D5 -#define mmCP_EOP_DONE_DATA_CNTL 0xC0D6 -#define mmCP_EOP_DONE_CNTX_ID 0xC0D7 -#define mmCP_EOP_DONE_ADDR_LO 0xC000 -#define mmCP_EOP_DONE_ADDR_HI 0xC001 -#define mmCP_EOP_DONE_DATA_LO 0xC002 -#define mmCP_EOP_DONE_DATA_HI 0xC003 -#define mmCP_EOP_LAST_FENCE_LO 0xC004 -#define mmCP_EOP_LAST_FENCE_HI 0xC005 -#define mmCP_STREAM_OUT_ADDR_LO 0xC006 -#define mmCP_STREAM_OUT_ADDR_HI 0xC007 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xC008 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xC009 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xC00A -#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xC00B -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xC00C -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xC00D -#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xC00E -#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xC00F -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xC010 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xC011 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xC012 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xC013 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xC014 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xC015 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xC016 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xC017 -#define mmCP_PIPE_STATS_ADDR_LO 0xC018 -#define mmCP_PIPE_STATS_ADDR_HI 0xC019 -#define mmCP_VGT_IAVERT_COUNT_LO 0xC01A -#define mmCP_VGT_IAVERT_COUNT_HI 0xC01B -#define mmCP_VGT_IAPRIM_COUNT_LO 0xC01C -#define mmCP_VGT_IAPRIM_COUNT_HI 0xC01D -#define mmCP_VGT_GSPRIM_COUNT_LO 0xC01E -#define mmCP_VGT_GSPRIM_COUNT_HI 0xC01F -#define mmCP_VGT_VSINVOC_COUNT_LO 0xC020 -#define mmCP_VGT_VSINVOC_COUNT_HI 0xC021 -#define mmCP_VGT_GSINVOC_COUNT_LO 0xC022 -#define mmCP_VGT_GSINVOC_COUNT_HI 0xC023 -#define mmCP_VGT_HSINVOC_COUNT_LO 0xC024 -#define mmCP_VGT_HSINVOC_COUNT_HI 0xC025 -#define mmCP_VGT_DSINVOC_COUNT_LO 0xC026 -#define mmCP_VGT_DSINVOC_COUNT_HI 0xC027 -#define mmCP_PA_CINVOC_COUNT_LO 0xC028 -#define mmCP_PA_CINVOC_COUNT_HI 0xC029 -#define mmCP_PA_CPRIM_COUNT_LO 0xC02A -#define mmCP_PA_CPRIM_COUNT_HI 0xC02B -#define mmCP_SC_PSINVOC_COUNT0_LO 0xC02C -#define mmCP_SC_PSINVOC_COUNT0_HI 0xC02D -#define mmCP_SC_PSINVOC_COUNT1_LO 0xC02E -#define mmCP_SC_PSINVOC_COUNT1_HI 0xC02F -#define mmCP_VGT_CSINVOC_COUNT_LO 0xC030 -#define mmCP_VGT_CSINVOC_COUNT_HI 0xC031 -#define mmCP_PIPE_STATS_CONTROL 0xC03D -#define mmCP_STREAM_OUT_CONTROL 0xC03E -#define mmCP_STRMOUT_CNTL 0xC03F -#define mmSCRATCH_REG0 0xC040 -#define mmGUI_SCRATCH_REG0 0xC040 -#define mmSCRATCH_REG1 0xC041 -#define mmGUI_SCRATCH_REG1 0xC041 -#define mmSCRATCH_REG2 0xC042 -#define mmGUI_SCRATCH_REG2 0xC042 -#define mmSCRATCH_REG3 0xC043 -#define mmGUI_SCRATCH_REG3 0xC043 -#define mmSCRATCH_REG4 0xC044 -#define mmGUI_SCRATCH_REG4 0xC044 -#define mmSCRATCH_REG5 0xC045 -#define mmGUI_SCRATCH_REG5 0xC045 -#define mmSCRATCH_REG6 0xC046 -#define mmGUI_SCRATCH_REG6 0xC046 -#define mmSCRATCH_REG7 0xC047 -#define mmGUI_SCRATCH_REG7 0xC047 -#define mmCP_APPEND_DATA_HI 0xC04C -#define mmCP_APPEND_LAST_CS_FENCE_HI 0xC04D -#define mmCP_APPEND_LAST_PS_FENCE_HI 0xC04E -#define mmSCRATCH_UMSK 0xC050 -#define mmSCRATCH_ADDR 0xC051 -#define mmCP_PFP_ATOMIC_PREOP_LO 0xC052 -#define mmCP_PFP_ATOMIC_PREOP_HI 0xC053 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xC054 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xC055 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xC056 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xC057 -#define mmCP_APPEND_ADDR_LO 0xC058 -#define mmCP_APPEND_ADDR_HI 0xC059 -#define mmCP_APPEND_DATA_LO 0xC05A -#define mmCP_APPEND_LAST_CS_FENCE_LO 0xC05B -#define mmCP_APPEND_LAST_PS_FENCE_LO 0xC05C -#define mmCP_ATOMIC_PREOP_LO 0xC05D -#define mmCP_ME_ATOMIC_PREOP_LO 0xC05D -#define mmCP_ATOMIC_PREOP_HI 0xC05E -#define mmCP_ME_ATOMIC_PREOP_HI 0xC05E -#define mmCP_GDS_ATOMIC0_PREOP_LO 0xC05F -#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xC05F -#define mmCP_GDS_ATOMIC0_PREOP_HI 0xC060 -#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xC060 -#define mmCP_GDS_ATOMIC1_PREOP_LO 0xC061 -#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xC061 -#define mmCP_GDS_ATOMIC1_PREOP_HI 0xC062 -#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xC062 -#define mmCP_ME_MC_WADDR_LO 0xC069 -#define mmCP_ME_MC_WADDR_HI 0xC06A -#define mmCP_ME_MC_WDATA_LO 0xC06B -#define mmCP_ME_MC_WDATA_HI 0xC06C -#define mmCP_ME_MC_RADDR_LO 0xC06D -#define mmCP_ME_MC_RADDR_HI 0xC06E -#define mmCP_SEM_WAIT_TIMER 0xC06F -#define mmCP_SIG_SEM_ADDR_LO 0xC070 -#define mmCP_SIG_SEM_ADDR_HI 0xC071 -#define mmCP_WAIT_SEM_ADDR_LO 0xC075 -#define mmCP_WAIT_SEM_ADDR_HI 0xC076 -#define mmCP_WAIT_REG_MEM_TIMEOUT 0xC074 -#define mmCP_COHER_START_DELAY 0xC07B -#define mmCP_COHER_CNTL 0xC07C -#define mmCP_COHER_SIZE 0xC07D -#define mmCP_COHER_SIZE_HI 0xC08C -#define mmCP_COHER_BASE 0xC07E -#define mmCP_COHER_BASE_HI 0xC079 -#define mmCP_COHER_STATUS 0xC07F -#define mmCP_DMA_PIO_SRC_ADDR 0xC064 -#define mmCP_DMA_PIO_SRC_ADDR_HI 0xC065 -#define mmCP_DMA_PIO_DST_ADDR 0xC066 -#define mmCP_DMA_PIO_DST_ADDR_HI 0xC067 -#define mmCP_DMA_PIO_CONTROL 0xC063 -#define mmCP_DMA_PIO_COMMAND 0xC0E8 -#define mmCP_DMA_ME_SRC_ADDR 0xC080 -#define mmCP_DMA_ME_SRC_ADDR_HI 0xC081 -#define mmCP_DMA_ME_DST_ADDR 0xC082 -#define mmCP_DMA_ME_DST_ADDR_HI 0xC083 -#define mmCP_DMA_ME_CONTROL 0xC078 -#define mmCP_DMA_ME_COMMAND 0xC084 -#define mmCP_DMA_PFP_SRC_ADDR 0xC085 -#define mmCP_DMA_PFP_SRC_ADDR_HI 0xC086 -#define mmCP_DMA_PFP_DST_ADDR 0xC087 -#define mmCP_DMA_PFP_DST_ADDR_HI 0xC088 -#define mmCP_DMA_PFP_CONTROL 0xC077 -#define mmCP_DMA_PFP_COMMAND 0xC089 -#define mmCP_DMA_CNTL 0xC08A -#define mmCP_DMA_READ_TAGS 0xC08B -#define mmCP_PFP_IB_CONTROL 0xC08D -#define mmCP_PFP_LOAD_CONTROL 0xC08E -#define mmCP_SCRATCH_INDEX 0xC08F -#define mmCP_SCRATCH_DATA 0xC090 -#define mmCP_RB_OFFSET 0xC091 -#define mmCP_IB1_OFFSET 0xC092 -#define mmCP_IB2_OFFSET 0xC093 -#define mmCP_IB1_PREAMBLE_BEGIN 0xC094 -#define mmCP_IB1_PREAMBLE_END 0xC095 -#define mmCP_IB2_PREAMBLE_BEGIN 0xC096 -#define mmCP_IB2_PREAMBLE_END 0xC097 -#define mmCP_CE_IB1_OFFSET 0xC098 -#define mmCP_CE_IB2_OFFSET 0xC099 -#define mmCP_CE_COUNTER 0xC09A -#define mmCP_CE_RB_OFFSET 0xC09B -#define mmCP_PFP_COMPLETION_STATUS 0xC0EC -#define mmCP_CE_COMPLETION_STATUS 0xC0ED -#define mmCP_PRED_NOT_VISIBLE 0xC0EE -#define mmCP_PFP_METADATA_BASE_ADDR 0xC0F0 -#define mmCP_PFP_METADATA_BASE_ADDR_HI 0xC0F1 -#define mmCP_CE_METADATA_BASE_ADDR 0xC0F2 -#define mmCP_CE_METADATA_BASE_ADDR_HI 0xC0F3 -#define mmCP_DRAW_INDX_INDR_ADDR 0xC0F4 -#define mmCP_DRAW_INDX_INDR_ADDR_HI 0xC0F5 -#define mmCP_DISPATCH_INDR_ADDR 0xC0F6 -#define mmCP_DISPATCH_INDR_ADDR_HI 0xC0F7 -#define mmCP_INDEX_BASE_ADDR 0xC0F8 -#define mmCP_INDEX_BASE_ADDR_HI 0xC0F9 -#define mmCP_INDEX_TYPE 0xC0FA -#define mmCP_GDS_BKUP_ADDR 0xC0FB -#define mmCP_GDS_BKUP_ADDR_HI 0xC0FC -#define mmCP_SAMPLE_STATUS 0xC0FD -#define mmCP_ME_COHER_CNTL 0xC0FE -#define mmCP_ME_COHER_SIZE 0xC0FF -#define mmCP_ME_COHER_SIZE_HI 0xC100 -#define mmCP_ME_COHER_BASE 0xC101 -#define mmCP_ME_COHER_BASE_HI 0xC102 -#define mmCP_ME_COHER_STATUS 0xC103 -#define mmCP_CE_INIT_CMD_BUFSZ 0xC0BD -#define mmCP_CE_IB1_CMD_BUFSZ 0xC0BE -#define mmCP_CE_IB2_CMD_BUFSZ 0xC0BF -#define mmCP_IB1_CMD_BUFSZ 0xC0C0 -#define mmCP_IB2_CMD_BUFSZ 0xC0C1 -#define mmCP_ST_CMD_BUFSZ 0xC0C2 -#define mmCP_CE_INIT_BASE_LO 0xC0C3 -#define mmCP_CE_INIT_BASE_HI 0xC0C4 -#define mmCP_CE_INIT_BUFSZ 0xC0C5 -#define mmCP_CE_IB1_BASE_LO 0xC0C6 -#define mmCP_CE_IB1_BASE_HI 0xC0C7 -#define mmCP_CE_IB1_BUFSZ 0xC0C8 -#define mmCP_CE_IB2_BASE_LO 0xC0C9 -#define mmCP_CE_IB2_BASE_HI 0xC0CA -#define mmCP_CE_IB2_BUFSZ 0xC0CB -#define mmCP_IB1_BASE_LO 0xC0CC -#define mmCP_IB1_BASE_HI 0xC0CD -#define mmCP_IB1_BUFSZ 0xC0CE -#define mmCP_IB2_BASE_LO 0xC0CF -#define mmCP_IB2_BASE_HI 0xC0D0 -#define mmCP_IB2_BUFSZ 0xC0D1 -#define mmCP_ST_BASE_LO 0xC0D2 -#define mmCP_ST_BASE_HI 0xC0D3 -#define mmCP_ST_BUFSZ 0xC0D4 -#define mmCPG_PERFCOUNTER1_LO 0xD000 -#define mmCPG_PERFCOUNTER1_HI 0xD001 -#define mmCPG_PERFCOUNTER0_LO 0xD002 -#define mmCPG_PERFCOUNTER0_HI 0xD003 -#define mmCPC_PERFCOUNTER1_LO 0xD004 -#define mmCPC_PERFCOUNTER1_HI 0xD005 -#define mmCPC_PERFCOUNTER0_LO 0xD006 -#define mmCPC_PERFCOUNTER0_HI 0xD007 -#define mmCPF_PERFCOUNTER1_LO 0xD008 -#define mmCPF_PERFCOUNTER1_HI 0xD009 -#define mmCPF_PERFCOUNTER0_LO 0xD00A -#define mmCPF_PERFCOUNTER0_HI 0xD00B -#define mmCPF_LATENCY_STATS_DATA 0xD00C -#define mmCPG_LATENCY_STATS_DATA 0xD00D -#define mmCPC_LATENCY_STATS_DATA 0xD00E -#define mmCPG_PERFCOUNTER1_SELECT 0xD800 -#define mmCPG_PERFCOUNTER0_SELECT1 0xD801 -#define mmCPG_PERFCOUNTER0_SELECT 0xD802 -#define mmCPC_PERFCOUNTER1_SELECT 0xD803 -#define mmCPC_PERFCOUNTER0_SELECT1 0xD804 -#define mmCPC_PERFCOUNTER0_SELECT 0xD809 -#define mmCPF_PERFCOUNTER1_SELECT 0xD805 -#define mmCPF_PERFCOUNTER0_SELECT1 0xD806 -#define mmCPF_PERFCOUNTER0_SELECT 0xD807 -#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0xD80A -#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0xD80B -#define mmCPF_LATENCY_STATS_SELECT 0xD80C -#define mmCPG_LATENCY_STATS_SELECT 0xD80D -#define mmCPC_LATENCY_STATS_SELECT 0xD80E -#define mmCP_DRAW_OBJECT 0xD810 -#define mmCP_DRAW_OBJECT_COUNTER 0xD811 -#define mmCP_DRAW_WINDOW_MASK_HI 0xD812 -#define mmCP_DRAW_WINDOW_HI 0xD813 -#define mmCP_DRAW_WINDOW_LO 0xD814 -#define mmCP_DRAW_WINDOW_CNTL 0xD815 -#define mmCP_PERFMON_CNTL 0xD808 -#define mmCGTT_CPC_CLK_CTRL 0xF0B2 -#define mmCGTT_CPF_CLK_CTRL 0xF0B1 -#define mmCGTT_CP_CLK_CTRL 0xF0B0 -#define mmCP_HYP_PFP_UCODE_ADDR 0xF814 -#define mmCP_PFP_UCODE_ADDR 0xF814 -#define mmCP_HYP_PFP_UCODE_DATA 0xF815 -#define mmCP_PFP_UCODE_DATA 0xF815 -#define mmCP_HYP_ME_UCODE_ADDR 0xF816 -#define mmCP_ME_RAM_RADDR 0xF816 -#define mmCP_ME_RAM_WADDR 0xF816 -#define mmCP_HYP_ME_UCODE_DATA 0xF817 -#define mmCP_ME_RAM_DATA 0xF817 -#define mmCP_HYP_CE_UCODE_ADDR 0xF818 -#define mmCP_CE_UCODE_ADDR 0xF818 -#define mmCP_HYP_CE_UCODE_DATA 0xF819 -#define mmCP_CE_UCODE_DATA 0xF819 -#define mmCP_HYP_MEC1_UCODE_ADDR 0xF81A -#define mmCP_MEC_ME1_UCODE_ADDR 0xF81A -#define mmCP_HYP_MEC1_UCODE_DATA 0xF81B -#define mmCP_MEC_ME1_UCODE_DATA 0xF81B -#define mmCP_HYP_MEC2_UCODE_ADDR 0xF81C -#define mmCP_MEC_ME2_UCODE_ADDR 0xF81C -#define mmCP_HYP_MEC2_UCODE_DATA 0xF81D -#define mmCP_MEC_ME2_UCODE_DATA 0xF81D -#define mmCP_HYP_PFP_UCODE_CHKSUM 0xF81E -#define mmCP_HYP_CE_UCODE_CHKSUM 0xF81F -#define mmCP_HYP_ME_UCODE_CHKSUM 0xF820 -#define mmCP_HYP_MEC_ME1_UCODE_CHKSUM 0xF821 -#define mmCP_HYP_MEC_ME2_UCODE_CHKSUM 0xF822 -#define mmCP_HYP_CONFIG_RANGE_BASE_1 0xF804 -#define mmCP_HYP_CONFIG_RANGE_END_1 0xF805 -#define mmCP_HYP_SHADER_RANGE_BASE 0xF806 -#define mmCP_HYP_SHADER_RANGE_END 0xF807 -#define mmCP_HYP_CONFIG_RANGE_BASE_2 0xF808 -#define mmCP_HYP_CONFIG_RANGE_END_2 0xF809 -#define mmCP_HYP_CONTEXT_RANGE_BASE 0xF80A -#define mmCP_HYP_CONTEXT_RANGE_END 0xF80B -#define mmCP_HYP_UCONFIG_RANGE_BASE 0xF80C -#define mmCP_HYP_UCONFIG_RANGE_END 0xF80D -#define mmCP_HYP_CPC_SECURE_REG0 0xF824 -#define mmCP_HYP_CPC_SECURE_REG1 0xF825 -#define mmCP_HYP_CPC_SECURE_REG2 0xF826 -#define mmCP_HYP_CPC_SECURE_REG3 0xF827 -#define mmCP_HYP_FIREWALL_MODIFIED_MASK 0xF830 -#define mmCP_PSP_REG_PRIV_LEVEL_A 0xFC00 -#define mmCP_PSP_REG_PRIV_LEVEL_B 0xFC01 -#define mmCP_PSP_REG_PRIV_LEVEL_C 0xFC02 -#define mmCP_PSP_REG_PRIV_LEVEL_D 0xFC03 -#define mmCP_PSP_REG_PRIV_LEVEL_E 0xFC04 -#define mmCP_PSP_REG_PRIV_LEVEL_F 0xFC05 -#define mmCP_PSP_REG_PRIV_LEVEL_G 0xFC06 -#define mmCP_PSP_REG_PRIV_LEVEL_H 0xFC07 -#define mmCP_PSP_REG_PRIV_LEVEL_I 0xFC08 -#define mmCP_PSP_REG_PRIV_LEVEL_J 0xFC09 -#define mmCP_PSP_REG_PRIV_LEVEL_K 0xFC0A -#define mmCP_PSP_REG_PRIV_LEVEL_L 0xFC0B -#define mmCP_PSP_REG_PRIV_LEVEL_M 0xFC0C -#define mmCP_PSP_REG_PRIV_LEVEL_N 0xFC0D -#define mmCP_PSP_REG_PRIV_LEVEL_O 0xFC0E -#define mmCP_PSP_REG_PRIV_LEVEL_P 0xFC0F -#define mmCPG_PSP_DEBUG 0xFC10 -#define mmCPC_PSP_DEBUG 0xFC11 -#define mmCPF_PSP_DEBUG 0xFC12 -#define mmCP_PSP_FIREWALL_MODIFIED_MASK 0xFC13 - - -// Registers from SQ_UC block - -#define mmSQ_SOPK 0x237F -#define mmSQ_VINTRP 0x237F -#define mmSQ_SCRATCH_0 0x237F -#define mmSQ_VOP3_0 0x237F -#define mmSQ_FLAT_0 0x237F -#define mmSQ_SMEM_0 0x237F -#define mmSQ_VOP3P_0 0x237F -#define mmSQ_EXP_0 0x237F -#define mmSQ_VOP3P_1 0x237F -#define mmSQ_SOP1 0x237F -#define mmSQ_DS_0 0x237F -#define mmSQ_VOP_DPP 0x237F -#define mmSQ_MUBUF_0 0x237F -#define mmSQ_VOP1 0x237F -#define mmSQ_GLBL_0 0x237F -#define mmSQ_VOP2 0x237F -#define mmSQ_GLBL_1 0x237F -#define mmSQ_MTBUF_0 0x237F -#define mmSQ_SOPP 0x237F -#define mmSQ_VOP_SDWA 0x237F -#define mmSQ_VOP3_0_SDST_ENC 0x237F -#define mmSQ_MIMG_0 0x237F -#define mmSQ_VOPC 0x237F -#define mmSQ_VOP_SDWA_SDST_ENC 0x237F -#define mmSQ_EXP_1 0x237F -#define mmSQ_SMEM_1 0x237F -#define mmSQ_MTBUF_1 0x237F -#define mmSQ_FLAT_1 0x237F -#define mmSQ_SOPC 0x237F -#define mmSQ_MIMG_1 0x237F -#define mmSQ_VOP3_1 0x237F -#define mmSQ_DS_1 0x237F -#define mmSQ_MUBUF_1 0x237F -#define mmSQ_SOP2 0x237F -#define mmSQ_INST 0x237F -#define mmSQ_SCRATCH_1 0x237F - - -// Registers from DIDT block - -#define mmDIDT_IND_INDEX 0x3280 -#define mmDIDT_IND_DATA 0x3281 - - -// Registers from SX block - -#define mmSX_DEBUG_BUSY 0x2414 -#define mmSX_DEBUG_BUSY_2 0x2415 -#define mmSX_DEBUG_BUSY_3 0x2416 -#define mmSX_DEBUG_BUSY_4 0x2417 -#define mmSX_DEBUG_BUSY_5 0x2418 -#define mmSX_DEBUG_1 0x2419 -#define mmSX_PS_DOWNCONVERT 0xA1D5 -#define mmSX_BLEND_OPT_EPSILON 0xA1D6 -#define mmSX_BLEND_OPT_CONTROL 0xA1D7 -#define mmSX_MRT0_BLEND_OPT 0xA1D8 -#define mmSX_MRT1_BLEND_OPT 0xA1D9 -#define mmSX_MRT2_BLEND_OPT 0xA1DA -#define mmSX_MRT3_BLEND_OPT 0xA1DB -#define mmSX_MRT4_BLEND_OPT 0xA1DC -#define mmSX_MRT5_BLEND_OPT 0xA1DD -#define mmSX_MRT6_BLEND_OPT 0xA1DE -#define mmSX_MRT7_BLEND_OPT 0xA1DF -#define mmSX_PERFCOUNTER0_LO 0xD240 -#define mmSX_PERFCOUNTER0_HI 0xD241 -#define mmSX_PERFCOUNTER1_LO 0xD242 -#define mmSX_PERFCOUNTER1_HI 0xD243 -#define mmSX_PERFCOUNTER2_LO 0xD244 -#define mmSX_PERFCOUNTER2_HI 0xD245 -#define mmSX_PERFCOUNTER3_LO 0xD246 -#define mmSX_PERFCOUNTER3_HI 0xD247 -#define mmSX_PERFCOUNTER0_SELECT 0xDA40 -#define mmSX_PERFCOUNTER1_SELECT 0xDA41 -#define mmSX_PERFCOUNTER2_SELECT 0xDA42 -#define mmSX_PERFCOUNTER3_SELECT 0xDA43 -#define mmSX_PERFCOUNTER0_SELECT1 0xDA44 -#define mmSX_PERFCOUNTER1_SELECT1 0xDA45 -#define mmCGTT_SX_CLK_CTRL0 0xF094 -#define mmCGTT_SX_CLK_CTRL1 0xF095 -#define mmCGTT_SX_CLK_CTRL2 0xF096 -#define mmCGTT_SX_CLK_CTRL3 0xF097 -#define mmCGTT_SX_CLK_CTRL4 0xF098 - - -// Registers from DB block - -#define mmDB_DEBUG 0x260C -#define mmDB_DEBUG2 0x260D -#define mmDB_DEBUG3 0x260E -#define mmDB_DEBUG4 0x260F -#define mmDB_RMI_CACHE_POLICY 0x261E -#define mmDB_CREDIT_LIMIT 0x2614 -#define mmDB_WATERMARKS 0x2615 -#define mmDB_EXCEPTION_CONTROL 0x261A -#define mmDB_SUBTILE_CONTROL 0x2616 -#define mmDB_FREE_CACHELINES 0x2617 -#define mmDB_FIFO_DEPTH1 0x2618 -#define mmDB_FIFO_DEPTH2 0x2619 -#define mmDB_RING_CONTROL 0x261B -#define mmDB_MEM_ARB_WATERMARKS 0x261C -#define mmDB_DFSM_CONFIG 0x2630 -#define mmDB_DFSM_WATERMARK 0x2631 -#define mmDB_DFSM_TILES_IN_FLIGHT 0x2632 -#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x2633 -#define mmDB_DFSM_WATCHDOG 0x2634 -#define mmDB_DFSM_FLUSH_ENABLE 0x2635 -#define mmDB_DFSM_FLUSH_AUX_EVENT 0x2636 -#define mmDB_READ_DEBUG_0 0x2620 -#define mmDB_READ_DEBUG_1 0x2621 -#define mmDB_READ_DEBUG_2 0x2622 -#define mmDB_READ_DEBUG_3 0x2623 -#define mmDB_READ_DEBUG_4 0x2624 -#define mmDB_READ_DEBUG_5 0x2625 -#define mmDB_READ_DEBUG_6 0x2626 -#define mmDB_READ_DEBUG_7 0x2627 -#define mmDB_READ_DEBUG_8 0x2628 -#define mmDB_READ_DEBUG_9 0x2629 -#define mmDB_READ_DEBUG_A 0x262A -#define mmDB_READ_DEBUG_B 0x262B -#define mmDB_READ_DEBUG_C 0x262C -#define mmDB_READ_DEBUG_D 0x262D -#define mmDB_READ_DEBUG_E 0x262E -#define mmDB_READ_DEBUG_F 0x262F -#define mmDB_Z_READ_BASE 0xA010 -#define mmDB_Z_READ_BASE_HI 0xA011 -#define mmDB_STENCIL_READ_BASE 0xA012 -#define mmDB_STENCIL_READ_BASE_HI 0xA013 -#define mmDB_Z_WRITE_BASE 0xA014 -#define mmDB_Z_WRITE_BASE_HI 0xA015 -#define mmDB_STENCIL_WRITE_BASE 0xA016 -#define mmDB_STENCIL_WRITE_BASE_HI 0xA017 -#define mmDB_DFSM_CONTROL 0xA018 -#define mmDB_Z_INFO 0xA00E -#define mmDB_Z_INFO2 0xA01A -#define mmDB_STENCIL_INFO 0xA00F -#define mmDB_STENCIL_INFO2 0xA01B -#define mmDB_DEPTH_SIZE 0xA007 -#define mmDB_DEPTH_VIEW 0xA002 -#define mmDB_RENDER_FILTER 0xA019 -#define mmDB_RENDER_CONTROL 0xA000 -#define mmDB_COUNT_CONTROL 0xA001 -#define mmDB_RENDER_OVERRIDE 0xA003 -#define mmDB_RENDER_OVERRIDE2 0xA004 -#define mmDB_EQAA 0xA201 -#define mmDB_SHADER_CONTROL 0xA203 -#define mmDB_DEPTH_BOUNDS_MIN 0xA008 -#define mmDB_DEPTH_BOUNDS_MAX 0xA009 -#define mmDB_STENCIL_CLEAR 0xA00A -#define mmDB_DEPTH_CLEAR 0xA00B -#define mmDB_HTILE_DATA_BASE 0xA005 -#define mmDB_HTILE_DATA_BASE_HI 0xA006 -#define mmDB_HTILE_SURFACE 0xA2AF -#define mmDB_PRELOAD_CONTROL 0xA2B2 -#define mmDB_STENCILREFMASK 0xA10C -#define mmDB_STENCILREFMASK_BF 0xA10D -#define mmDB_SRESULTS_COMPARE_STATE0 0xA2B0 -#define mmDB_SRESULTS_COMPARE_STATE1 0xA2B1 -#define mmDB_DEPTH_CONTROL 0xA200 -#define mmDB_STENCIL_CONTROL 0xA10B -#define mmDB_ALPHA_TO_MASK 0xA2DC -#define mmDB_ZPASS_COUNT_LOW 0xC3FE -#define mmDB_ZPASS_COUNT_HI 0xC3FF -#define mmDB_OCCLUSION_COUNT0_LOW 0xC3C0 -#define mmDB_OCCLUSION_COUNT0_HI 0xC3C1 -#define mmDB_OCCLUSION_COUNT1_LOW 0xC3C2 -#define mmDB_OCCLUSION_COUNT1_HI 0xC3C3 -#define mmDB_OCCLUSION_COUNT2_LOW 0xC3C4 -#define mmDB_OCCLUSION_COUNT2_HI 0xC3C5 -#define mmDB_OCCLUSION_COUNT3_LOW 0xC3C6 -#define mmDB_OCCLUSION_COUNT3_HI 0xC3C7 -#define mmDB_PERFCOUNTER0_LO 0xD440 -#define mmDB_PERFCOUNTER1_LO 0xD442 -#define mmDB_PERFCOUNTER2_LO 0xD444 -#define mmDB_PERFCOUNTER3_LO 0xD446 -#define mmDB_PERFCOUNTER0_HI 0xD441 -#define mmDB_PERFCOUNTER1_HI 0xD443 -#define mmDB_PERFCOUNTER2_HI 0xD445 -#define mmDB_PERFCOUNTER3_HI 0xD447 -#define mmDB_PERFCOUNTER0_SELECT 0xDC40 -#define mmDB_PERFCOUNTER1_SELECT 0xDC42 -#define mmDB_PERFCOUNTER2_SELECT 0xDC44 -#define mmDB_PERFCOUNTER3_SELECT 0xDC46 -#define mmDB_PERFCOUNTER0_SELECT1 0xDC41 -#define mmDB_PERFCOUNTER1_SELECT1 0xDC43 -#define mmDB_CGTT_CLK_CTRL_0 0xF0A4 - - -// Registers from TA block - - -// Registers from PA block - -#define mmPA_CL_ENHANCE 0x2285 -#define mmPA_CL_RESET_DEBUG 0x2286 -#define mmPA_SIDEBAND_REQUEST_DELAYS 0x22FB -#define mmPA_UTCL1_CNTL1 0x22F9 -#define mmPA_UTCL1_CNTL2 0x22FA -#define mmPA_SC_ENHANCE 0x22FC -#define mmPA_SC_ENHANCE_1 0x22FD -#define mmPA_SC_DSM_CNTL 0x22FE -#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x22FF -#define mmPA_SC_FIFO_SIZE 0x22F3 -#define mmPA_SC_IF_FIFO_SIZE 0x22F5 -#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x22F8 -#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22C9 -#define mmPA_SC_BINNER_EVENT_CNTL_0 0x22CC -#define mmPA_SC_BINNER_EVENT_CNTL_1 0x22CD -#define mmPA_SC_BINNER_EVENT_CNTL_2 0x22CE -#define mmPA_SC_BINNER_EVENT_CNTL_3 0x22CF -#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x22D0 -#define mmPA_SC_BINNER_PERF_CNTL_0 0x22D1 -#define mmPA_SC_BINNER_PERF_CNTL_1 0x22D2 -#define mmPA_SC_BINNER_PERF_CNTL_2 0x22D3 -#define mmPA_SC_BINNER_PERF_CNTL_3 0x22D4 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22C0 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22C1 -#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22C2 -#define mmPA_CL_CNTL_STATUS 0x2284 -#define mmPA_SU_CNTL_STATUS 0x2294 -#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 -#define mmPA_SU_DEBUG_CNTL 0x2280 -#define mmPA_SU_DEBUG_DATA 0x2281 -#define mmPA_SC_DEBUG_CNTL 0x22F6 -#define mmPA_SC_DEBUG_DATA 0x22F7 -#define mmPA_CL_VPORT_XSCALE 0xA10F -#define mmPA_CL_VPORT_XOFFSET 0xA110 -#define mmPA_CL_VPORT_YSCALE 0xA111 -#define mmPA_CL_VPORT_YOFFSET 0xA112 -#define mmPA_CL_VPORT_ZSCALE 0xA113 -#define mmPA_CL_VPORT_ZOFFSET 0xA114 -#define mmPA_CL_VPORT_XSCALE_1 0xA115 -#define mmPA_CL_VPORT_XSCALE_2 0xA11B -#define mmPA_CL_VPORT_XSCALE_3 0xA121 -#define mmPA_CL_VPORT_XSCALE_4 0xA127 -#define mmPA_CL_VPORT_XSCALE_5 0xA12D -#define mmPA_CL_VPORT_XSCALE_6 0xA133 -#define mmPA_CL_VPORT_XSCALE_7 0xA139 -#define mmPA_CL_VPORT_XSCALE_8 0xA13F -#define mmPA_CL_VPORT_XSCALE_9 0xA145 -#define mmPA_CL_VPORT_XSCALE_10 0xA14B -#define mmPA_CL_VPORT_XSCALE_11 0xA151 -#define mmPA_CL_VPORT_XSCALE_12 0xA157 -#define mmPA_CL_VPORT_XSCALE_13 0xA15D -#define mmPA_CL_VPORT_XSCALE_14 0xA163 -#define mmPA_CL_VPORT_XSCALE_15 0xA169 -#define mmPA_CL_VPORT_XOFFSET_1 0xA116 -#define mmPA_CL_VPORT_XOFFSET_2 0xA11C -#define mmPA_CL_VPORT_XOFFSET_3 0xA122 -#define mmPA_CL_VPORT_XOFFSET_4 0xA128 -#define mmPA_CL_VPORT_XOFFSET_5 0xA12E -#define mmPA_CL_VPORT_XOFFSET_6 0xA134 -#define mmPA_CL_VPORT_XOFFSET_7 0xA13A -#define mmPA_CL_VPORT_XOFFSET_8 0xA140 -#define mmPA_CL_VPORT_XOFFSET_9 0xA146 -#define mmPA_CL_VPORT_XOFFSET_10 0xA14C -#define mmPA_CL_VPORT_XOFFSET_11 0xA152 -#define mmPA_CL_VPORT_XOFFSET_12 0xA158 -#define mmPA_CL_VPORT_XOFFSET_13 0xA15E -#define mmPA_CL_VPORT_XOFFSET_14 0xA164 -#define mmPA_CL_VPORT_XOFFSET_15 0xA16A -#define mmPA_CL_VPORT_YSCALE_1 0xA117 -#define mmPA_CL_VPORT_YSCALE_2 0xA11D -#define mmPA_CL_VPORT_YSCALE_3 0xA123 -#define mmPA_CL_VPORT_YSCALE_4 0xA129 -#define mmPA_CL_VPORT_YSCALE_5 0xA12F -#define mmPA_CL_VPORT_YSCALE_6 0xA135 -#define mmPA_CL_VPORT_YSCALE_7 0xA13B -#define mmPA_CL_VPORT_YSCALE_8 0xA141 -#define mmPA_CL_VPORT_YSCALE_9 0xA147 -#define mmPA_CL_VPORT_YSCALE_10 0xA14D -#define mmPA_CL_VPORT_YSCALE_11 0xA153 -#define mmPA_CL_VPORT_YSCALE_12 0xA159 -#define mmPA_CL_VPORT_YSCALE_13 0xA15F -#define mmPA_CL_VPORT_YSCALE_14 0xA165 -#define mmPA_CL_VPORT_YSCALE_15 0xA16B -#define mmPA_CL_VPORT_YOFFSET_1 0xA118 -#define mmPA_CL_VPORT_YOFFSET_2 0xA11E -#define mmPA_CL_VPORT_YOFFSET_3 0xA124 -#define mmPA_CL_VPORT_YOFFSET_4 0xA12A -#define mmPA_CL_VPORT_YOFFSET_5 0xA130 -#define mmPA_CL_VPORT_YOFFSET_6 0xA136 -#define mmPA_CL_VPORT_YOFFSET_7 0xA13C -#define mmPA_CL_VPORT_YOFFSET_8 0xA142 -#define mmPA_CL_VPORT_YOFFSET_9 0xA148 -#define mmPA_CL_VPORT_YOFFSET_10 0xA14E -#define mmPA_CL_VPORT_YOFFSET_11 0xA154 -#define mmPA_CL_VPORT_YOFFSET_12 0xA15A -#define mmPA_CL_VPORT_YOFFSET_13 0xA160 -#define mmPA_CL_VPORT_YOFFSET_14 0xA166 -#define mmPA_CL_VPORT_YOFFSET_15 0xA16C -#define mmPA_CL_VPORT_ZSCALE_1 0xA119 -#define mmPA_CL_VPORT_ZSCALE_2 0xA11F -#define mmPA_CL_VPORT_ZSCALE_3 0xA125 -#define mmPA_CL_VPORT_ZSCALE_4 0xA12B -#define mmPA_CL_VPORT_ZSCALE_5 0xA131 -#define mmPA_CL_VPORT_ZSCALE_6 0xA137 -#define mmPA_CL_VPORT_ZSCALE_7 0xA13D -#define mmPA_CL_VPORT_ZSCALE_8 0xA143 -#define mmPA_CL_VPORT_ZSCALE_9 0xA149 -#define mmPA_CL_VPORT_ZSCALE_10 0xA14F -#define mmPA_CL_VPORT_ZSCALE_11 0xA155 -#define mmPA_CL_VPORT_ZSCALE_12 0xA15B -#define mmPA_CL_VPORT_ZSCALE_13 0xA161 -#define mmPA_CL_VPORT_ZSCALE_14 0xA167 -#define mmPA_CL_VPORT_ZSCALE_15 0xA16D -#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A -#define mmPA_CL_VPORT_ZOFFSET_2 0xA120 -#define mmPA_CL_VPORT_ZOFFSET_3 0xA126 -#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C -#define mmPA_CL_VPORT_ZOFFSET_5 0xA132 -#define mmPA_CL_VPORT_ZOFFSET_6 0xA138 -#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E -#define mmPA_CL_VPORT_ZOFFSET_8 0xA144 -#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A -#define mmPA_CL_VPORT_ZOFFSET_10 0xA150 -#define mmPA_CL_VPORT_ZOFFSET_11 0xA156 -#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C -#define mmPA_CL_VPORT_ZOFFSET_13 0xA162 -#define mmPA_CL_VPORT_ZOFFSET_14 0xA168 -#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E -#define mmPA_CL_VTE_CNTL 0xA206 -#define mmPA_CL_VS_OUT_CNTL 0xA207 -#define mmPA_CL_NANINF_CNTL 0xA208 -#define mmPA_CL_CLIP_CNTL 0xA204 -#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA2FA -#define mmPA_CL_GB_VERT_DISC_ADJ 0xA2FB -#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA2FC -#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA2FD -#define mmPA_CL_UCP_0_X 0xA16F -#define mmPA_CL_UCP_0_Y 0xA170 -#define mmPA_CL_UCP_0_Z 0xA171 -#define mmPA_CL_UCP_0_W 0xA172 -#define mmPA_CL_UCP_1_X 0xA173 -#define mmPA_CL_UCP_1_Y 0xA174 -#define mmPA_CL_UCP_1_Z 0xA175 -#define mmPA_CL_UCP_1_W 0xA176 -#define mmPA_CL_UCP_2_X 0xA177 -#define mmPA_CL_UCP_2_Y 0xA178 -#define mmPA_CL_UCP_2_Z 0xA179 -#define mmPA_CL_UCP_2_W 0xA17A -#define mmPA_CL_UCP_3_X 0xA17B -#define mmPA_CL_UCP_3_Y 0xA17C -#define mmPA_CL_UCP_3_Z 0xA17D -#define mmPA_CL_UCP_3_W 0xA17E -#define mmPA_CL_UCP_4_X 0xA17F -#define mmPA_CL_UCP_4_Y 0xA180 -#define mmPA_CL_UCP_4_Z 0xA181 -#define mmPA_CL_UCP_4_W 0xA182 -#define mmPA_CL_UCP_5_X 0xA183 -#define mmPA_CL_UCP_5_Y 0xA184 -#define mmPA_CL_UCP_5_Z 0xA185 -#define mmPA_CL_UCP_5_W 0xA186 -#define mmPA_CL_POINT_X_RAD 0xA1F5 -#define mmPA_CL_POINT_Y_RAD 0xA1F6 -#define mmPA_CL_POINT_SIZE 0xA1F7 -#define mmPA_CL_POINT_CULL_RAD 0xA1F8 -#define mmPA_SU_VTX_CNTL 0xA2F9 -#define mmPA_SU_POINT_SIZE 0xA280 -#define mmPA_SU_POINT_MINMAX 0xA281 -#define mmPA_SU_LINE_CNTL 0xA282 -#define mmPA_SU_LINE_STIPPLE_CNTL 0xA209 -#define mmPA_SU_LINE_STIPPLE_SCALE 0xA20A -#define mmPA_SU_PRIM_FILTER_CNTL 0xA20B -#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0xA20C -#define mmPA_CL_OBJPRIM_ID_CNTL 0xA20D -#define mmPA_CL_NGG_CNTL 0xA20E -#define mmPA_SU_OVER_RASTERIZATION_CNTL 0xA20F -#define mmPA_SU_SC_MODE_CNTL 0xA205 -#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA2DE -#define mmPA_SU_POLY_OFFSET_CLAMP 0xA2DF -#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA2E0 -#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA2E1 -#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA2E2 -#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA2E3 -#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xA08D -#define mmPA_SC_AA_CONFIG 0xA2F8 -#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xA30E -#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xA30F -#define mmPA_SC_SHADER_CONTROL 0xA310 -#define mmPA_SC_BINNER_CNTL_0 0xA311 -#define mmPA_SC_BINNER_CNTL_1 0xA312 -#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0xA313 -#define mmPA_SC_NGG_MODE_CNTL 0xA314 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xA2FE -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xA2FF -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xA300 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xA301 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xA302 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xA303 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xA304 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xA305 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xA306 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xA307 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xA308 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xA309 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xA30A -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xA30B -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xA30C -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xA30D -#define mmPA_SC_CENTROID_PRIORITY_0 0xA2F5 -#define mmPA_SC_CENTROID_PRIORITY_1 0xA2F6 -#define mmPA_SC_CLIPRECT_0_TL 0xA084 -#define mmPA_SC_CLIPRECT_0_BR 0xA085 -#define mmPA_SC_CLIPRECT_1_TL 0xA086 -#define mmPA_SC_CLIPRECT_1_BR 0xA087 -#define mmPA_SC_CLIPRECT_2_TL 0xA088 -#define mmPA_SC_CLIPRECT_2_BR 0xA089 -#define mmPA_SC_CLIPRECT_3_TL 0xA08A -#define mmPA_SC_CLIPRECT_3_BR 0xA08B -#define mmPA_SC_CLIPRECT_RULE 0xA083 -#define mmPA_SC_EDGERULE 0xA08C -#define mmPA_SC_LINE_CNTL 0xA2F7 -#define mmPA_SC_LINE_STIPPLE 0xA283 -#define mmPA_SC_MODE_CNTL_0 0xA292 -#define mmPA_SC_MODE_CNTL_1 0xA293 -#define mmPA_SC_RASTER_CONFIG 0xA0D4 -#define mmPA_SC_RASTER_CONFIG_1 0xA0D5 -#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xA0D6 -#define mmPA_SC_TILE_STEERING_OVERRIDE 0xA0D7 -#define mmPA_SC_RIGHT_VERT_GRID 0xA0E8 -#define mmPA_SC_LEFT_VERT_GRID 0xA0E9 -#define mmPA_SC_HORIZ_GRID 0xA0EA -#define mmPA_SC_FOV_WINDOW_LR 0xA0EB -#define mmPA_SC_FOV_WINDOW_TB 0xA0EC -#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090 -#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091 -#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C -#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D -#define mmPA_SC_WINDOW_OFFSET 0xA080 -#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081 -#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082 -#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094 -#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096 -#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098 -#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A -#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C -#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E -#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0 -#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2 -#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4 -#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6 -#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8 -#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA -#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC -#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE -#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0 -#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2 -#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095 -#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097 -#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099 -#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B -#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D -#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F -#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1 -#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3 -#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5 -#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7 -#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9 -#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB -#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD -#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF -#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1 -#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3 -#define mmPA_SC_VPORT_ZMIN_0 0xA0B4 -#define mmPA_SC_VPORT_ZMIN_1 0xA0B6 -#define mmPA_SC_VPORT_ZMIN_2 0xA0B8 -#define mmPA_SC_VPORT_ZMIN_3 0xA0BA -#define mmPA_SC_VPORT_ZMIN_4 0xA0BC -#define mmPA_SC_VPORT_ZMIN_5 0xA0BE -#define mmPA_SC_VPORT_ZMIN_6 0xA0C0 -#define mmPA_SC_VPORT_ZMIN_7 0xA0C2 -#define mmPA_SC_VPORT_ZMIN_8 0xA0C4 -#define mmPA_SC_VPORT_ZMIN_9 0xA0C6 -#define mmPA_SC_VPORT_ZMIN_10 0xA0C8 -#define mmPA_SC_VPORT_ZMIN_11 0xA0CA -#define mmPA_SC_VPORT_ZMIN_12 0xA0CC -#define mmPA_SC_VPORT_ZMIN_13 0xA0CE -#define mmPA_SC_VPORT_ZMIN_14 0xA0D0 -#define mmPA_SC_VPORT_ZMIN_15 0xA0D2 -#define mmPA_SC_VPORT_ZMAX_0 0xA0B5 -#define mmPA_SC_VPORT_ZMAX_1 0xA0B7 -#define mmPA_SC_VPORT_ZMAX_2 0xA0B9 -#define mmPA_SC_VPORT_ZMAX_3 0xA0BB -#define mmPA_SC_VPORT_ZMAX_4 0xA0BD -#define mmPA_SC_VPORT_ZMAX_5 0xA0BF -#define mmPA_SC_VPORT_ZMAX_6 0xA0C1 -#define mmPA_SC_VPORT_ZMAX_7 0xA0C3 -#define mmPA_SC_VPORT_ZMAX_8 0xA0C5 -#define mmPA_SC_VPORT_ZMAX_9 0xA0C7 -#define mmPA_SC_VPORT_ZMAX_10 0xA0C9 -#define mmPA_SC_VPORT_ZMAX_11 0xA0CB -#define mmPA_SC_VPORT_ZMAX_12 0xA0CD -#define mmPA_SC_VPORT_ZMAX_13 0xA0CF -#define mmPA_SC_VPORT_ZMAX_14 0xA0D1 -#define mmPA_SC_VPORT_ZMAX_15 0xA0D3 -#define mmPA_SU_LINE_STIPPLE_VALUE 0xC280 -#define mmPA_SC_LINE_STIPPLE_STATE 0xC281 -#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xC284 -#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xC285 -#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xC286 -#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xC28B -#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xC2A0 -#define mmPA_SC_P3D_TRAP_SCREEN_H 0xC2A1 -#define mmPA_SC_P3D_TRAP_SCREEN_V 0xC2A2 -#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xC2A3 -#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xC2A4 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xC2A8 -#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xC2A9 -#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xC2AA -#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xC2AB -#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xC2AC -#define mmPA_SC_TRAP_SCREEN_HV_EN 0xC2B0 -#define mmPA_SC_TRAP_SCREEN_H 0xC2B1 -#define mmPA_SC_TRAP_SCREEN_V 0xC2B2 -#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xC2B3 -#define mmPA_SC_TRAP_SCREEN_COUNT 0xC2B4 -#define mmPA_SU_PERFCOUNTER0_LO 0xD100 -#define mmPA_SU_PERFCOUNTER0_HI 0xD101 -#define mmPA_SU_PERFCOUNTER1_LO 0xD102 -#define mmPA_SU_PERFCOUNTER1_HI 0xD103 -#define mmPA_SU_PERFCOUNTER2_LO 0xD104 -#define mmPA_SU_PERFCOUNTER2_HI 0xD105 -#define mmPA_SU_PERFCOUNTER3_LO 0xD106 -#define mmPA_SU_PERFCOUNTER3_HI 0xD107 -#define mmPA_SC_PERFCOUNTER0_LO 0xD140 -#define mmPA_SC_PERFCOUNTER0_HI 0xD141 -#define mmPA_SC_PERFCOUNTER1_LO 0xD142 -#define mmPA_SC_PERFCOUNTER1_HI 0xD143 -#define mmPA_SC_PERFCOUNTER2_LO 0xD144 -#define mmPA_SC_PERFCOUNTER2_HI 0xD145 -#define mmPA_SC_PERFCOUNTER3_LO 0xD146 -#define mmPA_SC_PERFCOUNTER3_HI 0xD147 -#define mmPA_SC_PERFCOUNTER4_LO 0xD148 -#define mmPA_SC_PERFCOUNTER4_HI 0xD149 -#define mmPA_SC_PERFCOUNTER5_LO 0xD14A -#define mmPA_SC_PERFCOUNTER5_HI 0xD14B -#define mmPA_SC_PERFCOUNTER6_LO 0xD14C -#define mmPA_SC_PERFCOUNTER6_HI 0xD14D -#define mmPA_SC_PERFCOUNTER7_LO 0xD14E -#define mmPA_SC_PERFCOUNTER7_HI 0xD14F -#define mmPA_SU_PERFCOUNTER0_SELECT 0xD900 -#define mmPA_SU_PERFCOUNTER0_SELECT1 0xD901 -#define mmPA_SU_PERFCOUNTER1_SELECT 0xD902 -#define mmPA_SU_PERFCOUNTER1_SELECT1 0xD903 -#define mmPA_SU_PERFCOUNTER2_SELECT 0xD904 -#define mmPA_SU_PERFCOUNTER3_SELECT 0xD905 -#define mmPA_SC_PERFCOUNTER0_SELECT 0xD940 -#define mmPA_SC_PERFCOUNTER0_SELECT1 0xD941 -#define mmPA_SC_PERFCOUNTER1_SELECT 0xD942 -#define mmPA_SC_PERFCOUNTER2_SELECT 0xD943 -#define mmPA_SC_PERFCOUNTER3_SELECT 0xD944 -#define mmPA_SC_PERFCOUNTER4_SELECT 0xD945 -#define mmPA_SC_PERFCOUNTER5_SELECT 0xD946 -#define mmPA_SC_PERFCOUNTER6_SELECT 0xD947 -#define mmPA_SC_PERFCOUNTER7_SELECT 0xD948 -#define mmCGTT_PA_CLK_CTRL 0xF088 -#define mmCGTT_SC_CLK_CTRL0 0xF089 -#define mmCGTT_SC_CLK_CTRL1 0xF08A - - -// Registers from RMI block - -#define mmRMI_GENERAL_CNTL 0x2780 -#define mmRMI_GENERAL_CNTL1 0x2781 -#define mmRMI_GENERAL_STATUS 0x2782 -#define mmRMI_SUBBLOCK_STATUS0 0x2783 -#define mmRMI_SUBBLOCK_STATUS1 0x2784 -#define mmRMI_SUBBLOCK_STATUS2 0x2785 -#define mmRMI_SUBBLOCK_STATUS3 0x2786 -#define mmRMI_XBAR_CONFIG 0x2787 -#define mmRMI_PROBE_POP_LOGIC_CNTL 0x2788 -#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x2789 -#define mmRMI_DEMUX_CNTL 0x278A -#define mmRMI_UTCL1_CNTL1 0x278B -#define mmRMI_UTCL1_CNTL2 0x278C -#define mmRMI_UTC_UNIT_CONFIG 0x278D -#define mmRMI_TCIW_FORMATTER0_CNTL 0x278E -#define mmRMI_TCIW_FORMATTER1_CNTL 0x278F -#define mmRMI_SCOREBOARD_CNTL 0x2790 -#define mmRMI_SCOREBOARD_STATUS0 0x2791 -#define mmRMI_SCOREBOARD_STATUS1 0x2792 -#define mmRMI_SCOREBOARD_STATUS2 0x2793 -#define mmRMI_XBAR_ARBITER_CONFIG 0x2794 -#define mmRMI_XBAR_ARBITER_CONFIG_1 0x2795 -#define mmRMI_CLOCK_CNTRL 0x2796 -#define mmRMI_UTCL1_STATUS 0x2797 -#define mmRMI_DEBUG0 0x2798 -#define mmRMI_DEBUG1 0x2799 -#define mmRMI_DEBUG2 0x279A -#define mmRMI_DEBUG3 0x279B -#define mmRMI_DEBUG4 0x279C -#define mmRMI_XNACK_DEBUG 0x279D -#define mmRMI_SPARE 0x279E -#define mmRMI_SPARE_1 0x279F -#define mmRMI_SPARE_2 0x27A0 -#define mmRMI_PERFCOUNTER0_LO 0xD4C0 -#define mmRMI_PERFCOUNTER1_LO 0xD4C2 -#define mmRMI_PERFCOUNTER2_LO 0xD4C4 -#define mmRMI_PERFCOUNTER3_LO 0xD4C6 -#define mmRMI_PERFCOUNTER0_HI 0xD4C1 -#define mmRMI_PERFCOUNTER1_HI 0xD4C3 -#define mmRMI_PERFCOUNTER2_HI 0xD4C5 -#define mmRMI_PERFCOUNTER3_HI 0xD4C7 -#define mmRMI_PERFCOUNTER0_SELECT 0xDD00 -#define mmRMI_PERFCOUNTER0_SELECT1 0xDD01 -#define mmRMI_PERFCOUNTER1_SELECT 0xDD02 -#define mmRMI_PERFCOUNTER2_SELECT 0xDD03 -#define mmRMI_PERFCOUNTER2_SELECT1 0xDD04 -#define mmRMI_PERFCOUNTER3_SELECT 0xDD05 -#define mmRMI_PERF_COUNTER_CNTL 0xDD06 -#define mmRMI_CGTT_SCLK_CTRL 0xF0C0 - - -// Registers from DBGU_GFX block - -#define mmport_a_addr 0x27C0 -#define mmport_a_data_lo 0x27C1 -#define mmport_a_data_hi 0x27C2 -#define mmport_b_addr 0x27C3 -#define mmport_b_data_lo 0x27C4 -#define mmport_b_data_hi 0x27C5 -#define mmport_c_addr 0x27C6 -#define mmport_c_data_lo 0x27C7 -#define mmport_c_data_hi 0x27C8 -#define mmport_d_addr 0x27C9 -#define mmport_d_data_lo 0x27CA -#define mmport_d_data_hi 0x27CB - - -// Registers from GRBM_DEBUGBUS block - - -// Registers from GDS_DEBUGBUS block - - -// Registers from RLC_DEBUGBUS block - - -// Registers from CB_DEBUGBUS block - - -// Registers from PA_DEBUGBUS block - - -// Registers from PC_DEBUGBUS block - - -// Registers from SX_DEBUGBUS block - - -// Registers from SC_DEBUGBUS block - - -// Registers from WD_DEBUGBUS block - - -// Registers from IA_DEBUGBUS block - - -// Registers from VGT_DEBUGBUS block - - -// Registers from SPI_DEBUGBUS block - - -// Registers from CPC_DEBUGBUS block - - -// Registers from CPG_DEBUGBUS block - - -// Registers from CPF_DEBUGBUS block - - -// Registers from BCI_DEBUGBUS block - - -// Registers from RMI_DEBUGBUS block - - -// Registers from DB_DEBUGBUS block - - -// Registers from ATCL2 block - -#define mmATC_L2_CNTL 0x2800 -#define mmATC_L2_CNTL2 0x2801 -#define mmATC_L2_DEBUG 0x2802 -#define mmATC_L2_DEBUG2 0x2803 -#define mmATC_L2_CACHE_DATA0 0x2804 -#define mmATC_L2_CACHE_DATA1 0x2805 -#define mmATC_L2_CACHE_DATA2 0x2806 -#define mmATC_L2_CNTL3 0x2807 -#define mmATC_L2_STATUS 0x2808 -#define mmATC_L2_STATUS2 0x2809 -#define mmATC_L2_MISC_CG 0x280A -#define mmATC_L2_MEM_POWER_LS 0x280B -#define mmATC_L2_CGTT_CLK_CTRL 0x280C - - -// Registers from ATCL2PFCNTR block - -#define mmATC_L2_PERFCOUNTER_LO 0xD500 -#define mmATC_L2_PERFCOUNTER_HI 0xD501 - - -// Registers from ATCL2PFCNTL block - -#define mmATC_L2_PERFCOUNTER0_CFG 0xDD40 -#define mmATC_L2_PERFCOUNTER1_CFG 0xDD41 -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0xDD42 - - -// Registers from VML2PF block - -#define mmVM_L2_CNTL 0x2840 -#define mmVM_L2_CNTL2 0x2841 -#define mmVM_L2_CNTL3 0x2842 -#define mmVM_L2_STATUS 0x2843 -#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x2844 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x2845 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x2846 -#define mmVM_L2_PROTECTION_FAULT_CNTL 0x2847 -#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x2848 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x2849 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x284A -#define mmVM_L2_PROTECTION_FAULT_STATUS 0x284B -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x284C -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x284D -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x284E -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x284F -#define mmVM_DEBUG 0x2850 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x2851 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x2852 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x2853 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x2854 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x2855 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x2856 -#define mmVM_L2_CNTL4 0x2857 -#define mmVM_L2_MM_GROUP_RT_CLASSES 0x2858 -#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x2859 -#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x285A -#define mmVM_L2_CACHE_PARITY_CNTL 0x285B -#define mmVM_L2_IH_LOG_CNTL 0x285C -#define mmVM_L2_IH_LOG_BUSY 0x285D -#define mmVM_L2_CGTT_CLK_CTRL 0x285E -#define mmVML2_SEC_MASTER 0x285F - - -// Registers from VML2VC block - -#define mmVM_CONTEXT0_CNTL 0x2880 -#define mmVM_CONTEXT1_CNTL 0x2881 -#define mmVM_CONTEXT2_CNTL 0x2882 -#define mmVM_CONTEXT3_CNTL 0x2883 -#define mmVM_CONTEXT4_CNTL 0x2884 -#define mmVM_CONTEXT5_CNTL 0x2885 -#define mmVM_CONTEXT6_CNTL 0x2886 -#define mmVM_CONTEXT7_CNTL 0x2887 -#define mmVM_CONTEXT8_CNTL 0x2888 -#define mmVM_CONTEXT9_CNTL 0x2889 -#define mmVM_CONTEXT10_CNTL 0x288A -#define mmVM_CONTEXT11_CNTL 0x288B -#define mmVM_CONTEXT12_CNTL 0x288C -#define mmVM_CONTEXT13_CNTL 0x288D -#define mmVM_CONTEXT14_CNTL 0x288E -#define mmVM_CONTEXT15_CNTL 0x288F -#define mmVM_CONTEXTS_DISABLE 0x2890 -#define mmVM_INVALIDATE_ENG0_SEM 0x2891 -#define mmVM_INVALIDATE_ENG1_SEM 0x2892 -#define mmVM_INVALIDATE_ENG2_SEM 0x2893 -#define mmVM_INVALIDATE_ENG3_SEM 0x2894 -#define mmVM_INVALIDATE_ENG4_SEM 0x2895 -#define mmVM_INVALIDATE_ENG5_SEM 0x2896 -#define mmVM_INVALIDATE_ENG6_SEM 0x2897 -#define mmVM_INVALIDATE_ENG7_SEM 0x2898 -#define mmVM_INVALIDATE_ENG8_SEM 0x2899 -#define mmVM_INVALIDATE_ENG9_SEM 0x289A -#define mmVM_INVALIDATE_ENG10_SEM 0x289B -#define mmVM_INVALIDATE_ENG11_SEM 0x289C -#define mmVM_INVALIDATE_ENG12_SEM 0x289D -#define mmVM_INVALIDATE_ENG13_SEM 0x289E -#define mmVM_INVALIDATE_ENG14_SEM 0x289F -#define mmVM_INVALIDATE_ENG15_SEM 0x28A0 -#define mmVM_INVALIDATE_ENG16_SEM 0x28A1 -#define mmVM_INVALIDATE_ENG17_SEM 0x28A2 -#define mmVM_INVALIDATE_ENG0_REQ 0x28A3 -#define mmVM_INVALIDATE_ENG1_REQ 0x28A4 -#define mmVM_INVALIDATE_ENG2_REQ 0x28A5 -#define mmVM_INVALIDATE_ENG3_REQ 0x28A6 -#define mmVM_INVALIDATE_ENG4_REQ 0x28A7 -#define mmVM_INVALIDATE_ENG5_REQ 0x28A8 -#define mmVM_INVALIDATE_ENG6_REQ 0x28A9 -#define mmVM_INVALIDATE_ENG7_REQ 0x28AA -#define mmVM_INVALIDATE_ENG8_REQ 0x28AB -#define mmVM_INVALIDATE_ENG9_REQ 0x28AC -#define mmVM_INVALIDATE_ENG10_REQ 0x28AD -#define mmVM_INVALIDATE_ENG11_REQ 0x28AE -#define mmVM_INVALIDATE_ENG12_REQ 0x28AF -#define mmVM_INVALIDATE_ENG13_REQ 0x28B0 -#define mmVM_INVALIDATE_ENG14_REQ 0x28B1 -#define mmVM_INVALIDATE_ENG15_REQ 0x28B2 -#define mmVM_INVALIDATE_ENG16_REQ 0x28B3 -#define mmVM_INVALIDATE_ENG17_REQ 0x28B4 -#define mmVM_INVALIDATE_ENG0_ACK 0x28B5 -#define mmVM_INVALIDATE_ENG1_ACK 0x28B6 -#define mmVM_INVALIDATE_ENG2_ACK 0x28B7 -#define mmVM_INVALIDATE_ENG3_ACK 0x28B8 -#define mmVM_INVALIDATE_ENG4_ACK 0x28B9 -#define mmVM_INVALIDATE_ENG5_ACK 0x28BA -#define mmVM_INVALIDATE_ENG6_ACK 0x28BB -#define mmVM_INVALIDATE_ENG7_ACK 0x28BC -#define mmVM_INVALIDATE_ENG8_ACK 0x28BD -#define mmVM_INVALIDATE_ENG9_ACK 0x28BE -#define mmVM_INVALIDATE_ENG10_ACK 0x28BF -#define mmVM_INVALIDATE_ENG11_ACK 0x28C0 -#define mmVM_INVALIDATE_ENG12_ACK 0x28C1 -#define mmVM_INVALIDATE_ENG13_ACK 0x28C2 -#define mmVM_INVALIDATE_ENG14_ACK 0x28C3 -#define mmVM_INVALIDATE_ENG15_ACK 0x28C4 -#define mmVM_INVALIDATE_ENG16_ACK 0x28C5 -#define mmVM_INVALIDATE_ENG17_ACK 0x28C6 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x28C7 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x28C8 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x28C9 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x28CA -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x28CB -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x28CC -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x28CD -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x28CE -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x28CF -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x28D0 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x28D1 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x28D2 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x28D3 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x28D4 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x28D5 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x28D6 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x28D7 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x28D8 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x28D9 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x28DA -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x28DB -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x28DC -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x28DD -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x28DE -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x28DF -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x28E0 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x28E1 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x28E2 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x28E3 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x28E4 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x28E5 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x28E6 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x28E7 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x28E8 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x28E9 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x28EA -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x28EB -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x28EC -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x28ED -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x28EE -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x28EF -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x28F0 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x28F1 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x28F2 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x28F3 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x28F4 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x28F5 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x28F6 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x28F7 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x28F8 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x28F9 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x28FA -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x28FB -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x28FC -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x28FD -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x28FE -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x28FF -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x2900 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x2901 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x2902 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x2903 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x2904 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x2905 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x2906 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x2907 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x2908 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x2909 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x290A -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x290B -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x290C -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x290D -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x290E -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x290F -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x2910 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x2911 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x2912 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x2913 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x2914 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x2915 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x2916 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x2917 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x2918 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x2919 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x291A -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x291B -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x291C -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x291D -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x291E -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x291F -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x2920 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x2921 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x2922 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x2923 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x2924 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x2925 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x2926 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x2927 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x2928 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x2929 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x292A -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x292B -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x292C -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x292D -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x292E -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x292F -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x2930 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x2931 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x2932 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x2933 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x2934 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x2935 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x2936 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x2937 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x2938 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x2939 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x293A -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x293B -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x293C -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x293D -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x293E -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x293F -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x2940 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x2941 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x2942 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x2943 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x2944 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x2945 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x2946 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x2947 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x2948 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x2949 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x294A - - -// Registers from VML2PL block - -#define mmMC_VM_L2_PERFCOUNTER0_CFG 0xDD4C -#define mmMC_VM_L2_PERFCOUNTER1_CFG 0xDD4D -#define mmMC_VM_L2_PERFCOUNTER2_CFG 0xDD4E -#define mmMC_VM_L2_PERFCOUNTER3_CFG 0xDD4F -#define mmMC_VM_L2_PERFCOUNTER4_CFG 0xDD50 -#define mmMC_VM_L2_PERFCOUNTER5_CFG 0xDD51 -#define mmMC_VM_L2_PERFCOUNTER6_CFG 0xDD52 -#define mmMC_VM_L2_PERFCOUNTER7_CFG 0xDD53 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0xDD54 - - -// Registers from VML2PR block - -#define mmMC_VM_L2_PERFCOUNTER_LO 0xD508 -#define mmMC_VM_L2_PERFCOUNTER_HI 0xD509 - - -// Registers from VMSHAREDHV block - -#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xFA80 -#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xFA81 -#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xFA82 -#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xFA83 -#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xFA84 -#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xFA85 -#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xFA86 -#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xFA87 -#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xFA88 -#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xFA89 -#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xFA8A -#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xFA8B -#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xFA8C -#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xFA8D -#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xFA8E -#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xFA8F -#define mmVM_IOMMU_MMIO_CNTRL_1 0xFA90 -#define mmMC_VM_MARC_BASE_LO_0 0xFA91 -#define mmMC_VM_MARC_BASE_LO_1 0xFA92 -#define mmMC_VM_MARC_BASE_LO_2 0xFA93 -#define mmMC_VM_MARC_BASE_LO_3 0xFA94 -#define mmMC_VM_MARC_BASE_HI_0 0xFA95 -#define mmMC_VM_MARC_BASE_HI_1 0xFA96 -#define mmMC_VM_MARC_BASE_HI_2 0xFA97 -#define mmMC_VM_MARC_BASE_HI_3 0xFA98 -#define mmMC_VM_MARC_RELOC_LO_0 0xFA99 -#define mmMC_VM_MARC_RELOC_LO_1 0xFA9A -#define mmMC_VM_MARC_RELOC_LO_2 0xFA9B -#define mmMC_VM_MARC_RELOC_LO_3 0xFA9C -#define mmMC_VM_MARC_RELOC_HI_0 0xFA9D -#define mmMC_VM_MARC_RELOC_HI_1 0xFA9E -#define mmMC_VM_MARC_RELOC_HI_2 0xFA9F -#define mmMC_VM_MARC_RELOC_HI_3 0xFAA0 -#define mmMC_VM_MARC_LEN_LO_0 0xFAA1 -#define mmMC_VM_MARC_LEN_LO_1 0xFAA2 -#define mmMC_VM_MARC_LEN_LO_2 0xFAA3 -#define mmMC_VM_MARC_LEN_LO_3 0xFAA4 -#define mmMC_VM_MARC_LEN_HI_0 0xFAA5 -#define mmMC_VM_MARC_LEN_HI_1 0xFAA6 -#define mmMC_VM_MARC_LEN_HI_2 0xFAA7 -#define mmMC_VM_MARC_LEN_HI_3 0xFAA8 -#define mmVM_IOMMU_CONTROL_REGISTER 0xFAA9 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0xFAAA -#define mmVM_PCIE_ATS_CNTL 0xFAAB -#define mmVM_PCIE_ATS_CNTL_VF_0 0xFAAC -#define mmVM_PCIE_ATS_CNTL_VF_1 0xFAAD -#define mmVM_PCIE_ATS_CNTL_VF_2 0xFAAE -#define mmVM_PCIE_ATS_CNTL_VF_3 0xFAAF -#define mmVM_PCIE_ATS_CNTL_VF_4 0xFAB0 -#define mmVM_PCIE_ATS_CNTL_VF_5 0xFAB1 -#define mmVM_PCIE_ATS_CNTL_VF_6 0xFAB2 -#define mmVM_PCIE_ATS_CNTL_VF_7 0xFAB3 -#define mmVM_PCIE_ATS_CNTL_VF_8 0xFAB4 -#define mmVM_PCIE_ATS_CNTL_VF_9 0xFAB5 -#define mmVM_PCIE_ATS_CNTL_VF_10 0xFAB6 -#define mmVM_PCIE_ATS_CNTL_VF_11 0xFAB7 -#define mmVM_PCIE_ATS_CNTL_VF_12 0xFAB8 -#define mmVM_PCIE_ATS_CNTL_VF_13 0xFAB9 -#define mmVM_PCIE_ATS_CNTL_VF_14 0xFABA -#define mmVM_PCIE_ATS_CNTL_VF_15 0xFABB -#define mmUTCL2_CGTT_CLK_CTRL 0xFABC - - -// Registers from VMSHAREDPF block - -#define mmMC_VM_NB_MMIOBASE 0x2964 -#define mmMC_VM_NB_MMIOLIMIT 0x2965 -#define mmMC_VM_NB_PCI_CTRL 0x2966 -#define mmMC_VM_NB_PCI_ARB 0x2967 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x2968 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x2969 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x296A -#define mmMC_VM_FB_OFFSET 0x296B -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x296C -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x296D -#define mmMC_VM_STEERING 0x296E -#define mmMC_SHARED_VIRT_RESET_REQ 0x296F -#define mmMC_MEM_POWER_LS 0x2970 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x2971 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x2972 -#define mmMC_VM_APT_CNTL 0x2973 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x2974 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x2975 -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x2976 - - -// Registers from VMSHAREDVC block - -#define mmMC_VM_FB_LOCATION_BASE 0x2980 -#define mmMC_VM_FB_LOCATION_TOP 0x2981 -#define mmMC_VM_AGP_TOP 0x2982 -#define mmMC_VM_AGP_BOT 0x2983 -#define mmMC_VM_AGP_BASE 0x2984 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2985 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2986 -#define mmMC_VM_MX_L1_TLB_CNTL 0x2987 - - -// Registers from GC_EA block - -#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x2A00 -#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x2A01 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x2A02 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x2A03 -#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x2A04 -#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x2A05 -#define mmGCEA_DRAM_RD_LAZY 0x2A06 -#define mmGCEA_DRAM_WR_LAZY 0x2A07 -#define mmGCEA_DRAM_RD_CAM_CNTL 0x2A08 -#define mmGCEA_DRAM_WR_CAM_CNTL 0x2A09 -#define mmGCEA_DRAM_PAGE_BURST 0x2A0A -#define mmGCEA_DRAM_RD_PRI_AGE 0x2A0B -#define mmGCEA_DRAM_WR_PRI_AGE 0x2A0C -#define mmGCEA_DRAM_RD_PRI_QUEUING 0x2A0D -#define mmGCEA_DRAM_WR_PRI_QUEUING 0x2A0E -#define mmGCEA_DRAM_RD_PRI_FIXED 0x2A0F -#define mmGCEA_DRAM_WR_PRI_FIXED 0x2A10 -#define mmGCEA_DRAM_RD_PRI_URGENCY 0x2A11 -#define mmGCEA_DRAM_WR_PRI_URGENCY 0x2A12 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x2A13 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x2A14 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x2A15 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x2A16 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x2A17 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x2A18 -#define mmGCEA_ADDRNORM_BASE_ADDR0 0x2A32 -#define mmGCEA_ADDRNORM_LIMIT_ADDR0 0x2A33 -#define mmGCEA_ADDRNORM_BASE_ADDR1 0x2A34 -#define mmGCEA_ADDRNORM_LIMIT_ADDR1 0x2A35 -#define mmGCEA_ADDRNORM_OFFSET_ADDR1 0x2A36 -#define mmGCEA_ADDRNORM_HOLE_CNTL 0x2A41 -#define mmGCEA_ADDRDEC_BANK_CFG 0x2A42 -#define mmGCEA_ADDRDEC_MISC_CFG 0x2A43 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 0x2A44 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 0x2A45 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 0x2A46 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 0x2A47 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 0x2A48 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC 0x2A49 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 0x2A4A -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 0x2A4B -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 0x2A4C -#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x2A4D -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 0x2A58 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 0x2A59 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 0x2A5A -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 0x2A5B -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x2A5C -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x2A5D -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x2A5E -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x2A5F -#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 0x2A60 -#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 0x2A61 -#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x2A62 -#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x2A63 -#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 0x2A64 -#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 0x2A65 -#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 0x2A66 -#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 0x2A67 -#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x2A68 -#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x2A69 -#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x2A6A -#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x2A6B -#define mmGCEA_ADDRDEC0_RM_SEL_CS01 0x2A6C -#define mmGCEA_ADDRDEC0_RM_SEL_CS23 0x2A6D -#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 0x2A6E -#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 0x2A6F -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 0x2A70 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 0x2A71 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 0x2A72 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 0x2A73 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x2A74 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x2A75 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x2A76 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x2A77 -#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 0x2A78 -#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 0x2A79 -#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x2A7A -#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x2A7B -#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 0x2A7C -#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 0x2A7D -#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 0x2A7E -#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 0x2A7F -#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x2A80 -#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x2A81 -#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x2A82 -#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x2A83 -#define mmGCEA_ADDRDEC1_RM_SEL_CS01 0x2A84 -#define mmGCEA_ADDRDEC1_RM_SEL_CS23 0x2A85 -#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 0x2A86 -#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 0x2A87 -#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x2AD0 -#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x2AD1 -#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x2AD2 -#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x2AD3 -#define mmGCEA_IO_RD_COMBINE_FLUSH 0x2AD4 -#define mmGCEA_IO_WR_COMBINE_FLUSH 0x2AD5 -#define mmGCEA_IO_GROUP_BURST 0x2AD6 -#define mmGCEA_IO_RD_PRI_AGE 0x2AD7 -#define mmGCEA_IO_WR_PRI_AGE 0x2AD8 -#define mmGCEA_IO_RD_PRI_QUEUING 0x2AD9 -#define mmGCEA_IO_WR_PRI_QUEUING 0x2ADA -#define mmGCEA_IO_RD_PRI_FIXED 0x2ADB -#define mmGCEA_IO_WR_PRI_FIXED 0x2ADC -#define mmGCEA_IO_RD_PRI_URGENCY 0x2ADD -#define mmGCEA_IO_WR_PRI_URGENCY 0x2ADE -#define mmGCEA_IO_RD_PRI_URGENCY_MASK 0x2ADF -#define mmGCEA_IO_WR_PRI_URGENCY_MASK 0x2AE0 -#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x2AE1 -#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x2AE2 -#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x2AE3 -#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x2AE4 -#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x2AE5 -#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x2AE6 -#define mmGCEA_SDP_ARB_DRAM 0x2AE7 -#define mmGCEA_SDP_ARB_FINAL 0x2AE9 -#define mmGCEA_SDP_DRAM_PRIORITY 0x2AEA -#define mmGCEA_SDP_IO_PRIORITY 0x2AEC -#define mmGCEA_SDP_CREDITS 0x2AED -#define mmGCEA_SDP_TAG_RESERVE0 0x2AEE -#define mmGCEA_SDP_TAG_RESERVE1 0x2AEF -#define mmGCEA_SDP_VCC_RESERVE0 0x2AF0 -#define mmGCEA_SDP_VCC_RESERVE1 0x2AF1 -#define mmGCEA_SDP_VCD_RESERVE0 0x2AF2 -#define mmGCEA_SDP_VCD_RESERVE1 0x2AF3 -#define mmGCEA_SDP_REQ_CNTL 0x2AF4 -#define mmGCEA_MISC 0x2AF5 -#define mmGCEA_LATENCY_SAMPLING 0x2AF6 -#define mmGCEA_PERFCOUNTER_LO 0x2AF7 -#define mmGCEA_PERFCOUNTER_HI 0x2AF8 -#define mmGCEA_PERFCOUNTER0_CFG 0x2AF9 -#define mmGCEA_PERFCOUNTER1_CFG 0x2AFA -#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x2AFB -#define mmGCEA_MAM_CTRL 0x2AFC -#define mmGCEA_MAM_CTRL2 0x2AFD -#define mmGCEA_MAM_ARAM_FLUSH_ADDR_LO 0x2AFE -#define mmGCEA_MAM_DBIT_QUERY 0x2AFF -#define mmGCEA_MAM_STATUS 0x2700 -#define mmGCEA_EDC_CNT 0x2701 -#define mmGCEA_EDC_CNT2 0x2702 -#define mmGCEA_DSM_CNTL 0x2703 -#define mmGCEA_DSM_CNTLA 0x2704 -#define mmGCEA_DSM_CNTLB 0x2705 -#define mmGCEA_DSM_CNTL2 0x2706 -#define mmGCEA_DSM_CNTL2A 0x2707 -#define mmGCEA_DSM_CNTL2B 0x2708 -#define mmGCEA_TCC_XBR_CREDITS 0x2709 -#define mmGCEA_TCC_XBR_MAXBURST 0x270A -#define mmGCEA_PROBE_CNTL 0x270B -#define mmGCEA_PROBE_MAP 0x270C -#define mmGCEA_ERR_STATUS 0x270D -#define mmGCEA_MISC2 0x270E -#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 0x270F -#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 0x2710 -#define mmGCEA_SDP_BACKDOOR_DATACREDITS0 0x2711 -#define mmGCEA_SDP_BACKDOOR_DATACREDITS1 0x2712 -#define mmGCEA_SDP_BACKDOOR_MISCCREDITS 0x2713 -#define mmGCEA_SDP_ENABLE 0x2714 -#define mmGCEA_CGTT_CLK_CTRL 0xF0C4 -#define mmGCEA_SECURE_CTRL 0xFC40 - -} // gfx9 -} // pm4_profile - -#endif diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_pm4_it_opcodes.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_pm4_it_opcodes.h deleted file mode 100644 index 2162d0fb71..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_pm4_it_opcodes.h +++ /dev/null @@ -1,149 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS AUTO-GENERATED BY PITGEN (vA) -// !!!! DO NOT EDIT BY HAND !!!! -////////////////////////////////////////////////////////////////////////////////// -// Project: 10xx or later -// Description: -// -// PM4 PacketType3 IT_OpCode Definitions -// Extracted From ME and PFP F32 Microcode Jump Tables: -// -////////////////////////////////////////////////////////////////////////////////// -// -// Trade secret of ATI Technologies, Inc. -// Copyright 1999, ATI Technologies, Inc., (unpublished) -// -// All rights reserved. This notice is intended as a precaution against -// inadvertent publication and does not imply publication or any waiver -// of confidentiality. The year included in the foregoing notice is the -// year of creation of the work. -////////////////////////////////////////////////////////////////////////////////// - -#ifndef PM4_IT_OPCODES_H -#define PM4_IT_OPCODES_H - -namespace pm4_profile { -namespace gfx9 { - -// typedef enum IT_OpCodeType { -enum IT_OpCodeType { - IT_NOP = 0x10, - IT_SET_BASE = 0x11, - IT_CLEAR_STATE = 0x12, - IT_INDEX_BUFFER_SIZE = 0x13, - IT_DISPATCH_DIRECT = 0x15, - IT_DISPATCH_INDIRECT = 0x16, - IT_INDIRECT_BUFFER_END = 0x17, - IT_INDIRECT_BUFFER_CNST_END = 0x19, - IT_ATOMIC_GDS = 0x1D, - IT_ATOMIC_MEM = 0x1E, - IT_OCCLUSION_QUERY = 0x1F, - IT_SET_PREDICATION = 0x20, - IT_REG_RMW = 0x21, - IT_COND_EXEC = 0x22, - IT_PRED_EXEC = 0x23, - IT_DRAW_INDIRECT = 0x24, - IT_DRAW_INDEX_INDIRECT = 0x25, - IT_INDEX_BASE = 0x26, - IT_DRAW_INDEX_2 = 0x27, - IT_CONTEXT_CONTROL = 0x28, - IT_INDEX_TYPE = 0x2A, - IT_DRAW_INDIRECT_MULTI = 0x2C, - IT_DRAW_INDEX_AUTO = 0x2D, - IT_NUM_INSTANCES = 0x2F, - IT_DRAW_INDEX_MULTI_AUTO = 0x30, - IT_INDIRECT_BUFFER_CNST = 0x33, - IT_STRMOUT_BUFFER_UPDATE = 0x34, - IT_DRAW_INDEX_OFFSET_2 = 0x35, - IT_WRITE_DATA = 0x37, - IT_DRAW_INDEX_INDIRECT_MULTI = 0x38, - IT_MEM_SEMAPHORE = 0x39, - IT_DRAW_INDEX_MULTI_INST = 0x3A, - IT_WAIT_REG_MEM = 0x3C, - IT_INDIRECT_BUFFER = 0x3F, - IT_COND_INDIRECT_BUFFER = 0x3F, - IT_COPY_DATA = 0x40, - IT_PFP_SYNC_ME = 0x42, - IT_ME_INITIALIZE = 0x44, - IT_COND_WRITE = 0x45, - IT_EVENT_WRITE = 0x46, - IT_RELEASE_MEM = 0x49, - IT_PREAMBLE_CNTL = 0x4A, - IT_DMA_DATA = 0x50, - IT_CONTEXT_REG_RMW = 0x51, - IT_GFX_CNTX_UPDATE = 0x52, - IT_BLK_CNTX_UPDATE = 0x53, - IT_INCR_UPDT_STATE = 0x55, - IT_ACQUIRE_MEM = 0x58, - IT_REWIND = 0x59, - IT_GEN_PDEPTE = 0x5B, - IT_PRIME_UTCL2 = 0x5D, - IT_LOAD_UCONFIG_REG = 0x5E, - IT_LOAD_SH_REG = 0x5F, - IT_LOAD_CONFIG_REG = 0x60, - IT_LOAD_CONTEXT_REG = 0x61, - IT_SET_CONFIG_REG = 0x68, - IT_SET_CONTEXT_REG = 0x69, - IT_SET_CONTEXT_REG_INDEX = 0x6A, - IT_SET_SH_REG_DI = 0x72, - IT_SET_SH_REG = 0x76, - IT_SET_SH_REG_OFFSET = 0x77, - IT_SET_QUEUE_REG = 0x78, - IT_SET_UCONFIG_REG = 0x79, - IT_SET_UCONFIG_REG_INDEX = 0x7A, - IT_FORWARD_HEADER = 0x7C, - IT_SCRATCH_RAM_WRITE = 0x7D, - IT_SCRATCH_RAM_READ = 0x7E, - IT_LOAD_CONST_RAM = 0x80, - IT_WRITE_CONST_RAM = 0x81, - IT_DUMP_CONST_RAM = 0x83, - IT_INCREMENT_CE_COUNTER = 0x84, - IT_INCREMENT_DE_COUNTER = 0x85, - IT_WAIT_ON_CE_COUNTER = 0x86, - IT_WAIT_ON_DE_COUNTER_DIFF = 0x88, - IT_SWITCH_BUFFER = 0x8B, - IT_DISPATCH_DRAW_PREAMBLE = 0x8C, - IT_DISPATCH_DRAW = 0x8D, - IT_COND_PREEMPT = 0x8E, - IT_DRAW_MULTI_PREAMBLE = 0x8F, - IT_FRAME_CONTROL = 0x90, - IT_INDEX_ATTRIBUTES_INDIRECT = 0x91, - IT_WAIT_REG_MEM64 = 0x93, - IT_GET_LOD_STATS = 0x94, - IT_COPY_DATA_RB = 0x96, - IT_DMA_DATA_FILL_MULTI = 0x9A, - IT_SET_SH_REG_INDEX = 0x9B, - IT_EOP_BUFFER_END = 0x18, - IT_INTR_BUFFER_END = 0x1A, - IT_CP_DMA = 0x41, - IT_SURFACE_SYNC = 0x43, - IT_EVENT_WRITE_EOP = 0x47, - IT_EVENT_WRITE_EOS = 0x48, - IT_INTERRUPT = 0x5A, - IT_INDIRECT_BUFFER_PASID = 0x5C, - IT_LOAD_COMPUTE_STATE = 0x62, - IT_SET_CONTEXT_REG_INDIRECT = 0x73, - IT_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C, - IT_DISPATCH_DRAW_ACE = 0x8D, - IT_HDP_FLUSH = 0x95, - IT_SECURE_CONTROL = 0x97, - IT_INVALIDATE_TLBS = 0x98, - IT_AQL_PACKET = 0x99, - IT_SET_RESOURCES = 0xA0, - IT_MAP_PROCESS = 0xA1, - IT_MAP_QUEUES = 0xA2, - IT_UNMAP_QUEUES = 0xA3, - IT_QUERY_STATUS = 0xA4, - IT_RUN_LIST = 0xA5, - IT_MAP_PROCESS_VM = 0xA6 -}; -//} IT_OpCodeType; - -#define PM4_TYPE_0 0 -#define PM4_TYPE_2 2 -#define PM4_TYPE_3 3 - -} // gfx9 -} // pm4_profile - -#endif // PM4_IT_OPCODES_H diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_pm4defs.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_pm4defs.h deleted file mode 100644 index d86b720204..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_pm4defs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* -*************************************************************************************************** -* -* Trade secret of Advanced Micro Devices, Inc. -* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against inadvertent publication and -* does not imply publication or any waiver of confidentiality. The year included in the foregoing -* notice is the year of creation of the work. -* -*************************************************************************************************** -*/ - -#ifndef _GFX9_PM4DEFS_H_ -#define _GFX9_PM4DEFS_H_ - -/****************************************************************************** -* -* gfx9_pm4defs.h -* -* GFX9 PM4 definitions, typedefs, and enumerations. -* -******************************************************************************/ - -#define COPY_DATA_SEL_REG 0 ///< Mem-mapped register -#define COPY_DATA_SEL_SRC_SYS_PERF_COUNTER 4 ///< Privileged memory performance counter -#define COPY_DATA_SEL_COUNT_1DW 0 ///< Copy 1 word (32 bits) -#define COPY_DATA_SEL_COUNT_2DW 1 ///< Copy 2 words (64 bits) - -#endif // _GFX9_PM4DEFS_H_ diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_shift.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_shift.h deleted file mode 100644 index 86a99a77c2..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_shift.h +++ /dev/null @@ -1,63386 +0,0 @@ -#if !defined(_greenland_SHIFT_HEADER) -#define _greenland_SHIFT_HEADER -/* -* greenland_shift.h -* -* Register Spec Release: -* -* -* (c) 2000 ATI Technologies Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against -* inadvertent publication and does not imply publication or any waiver -* of confidentiality. The year included in the foregoing notice is the -* year of creation of the work. -* -*/ - -namespace pm4_profile { -namespace gfx9 { - -// ATC_ATS_CNTL -#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 -#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 -#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 -#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 -#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 -#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x00000014 -#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x00000015 -#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x00000016 - -// ATC_ATS_DEBUG -#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x00000000 -#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x00000001 -#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x00000002 -#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x00000005 -#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x00000006 -#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x00000007 -#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x00000008 -#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x00000009 -#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0x0000000a -#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0x0000000e -#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0x0000000f -#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x00000010 -#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x00000011 -#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x00000012 -#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x00000013 -#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x00000014 -#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x00000015 -#define ATC_ATS_DEBUG__DISABLE_MULTIPLE_INVALIDATIONS__SHIFT 0x00000016 -#define ATC_ATS_DEBUG__DROP_PAGE_REQUEST_WHEN_FULL__SHIFT 0x00000017 -#define ATC_ATS_DEBUG__EFFECTIVE_TRANS_WORK_QUEUE_SIZE__SHIFT 0x00000018 -#define ATC_ATS_DEBUG__EFFECTIVE_PR_WORK_QUEUE_SIZE__SHIFT 0x0000001b -#define ATC_ATS_DEBUG__DISABLE_VMID16_PASID_MAPPING__SHIFT 0x0000001f - -// ATC_ATS_FAULT_DEBUG -#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000000 -#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x00000001 - -// ATC_ATS_STATUS -#define ATC_ATS_STATUS__BUSY__SHIFT 0x00000000 -#define ATC_ATS_STATUS__CRASHED__SHIFT 0x00000001 -#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000002 -#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x00000003 -#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x00000006 - -// ATC_ATS_FAULT_CNTL -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x00000000 -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0x0000000a -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x00000014 - -// ATC_ATS_FAULT_STATUS_INFO -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x00000000 -#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0x0000000a -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0x0000000f -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x00000010 -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x00000011 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x00000012 -#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x00000013 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x00000018 - -// ATC_ATS_FAULT_STATUS_ADDR -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x00000000 - -// ATC_ATS_DEFAULT_PAGE_LOW -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x00000000 - -// ATC_TRANS_FAULT_RSPCNTRL -#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x00000000 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x00000001 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x00000002 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x00000003 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x00000004 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x00000005 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x00000006 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x00000007 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x00000008 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x00000009 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0x0000000a -#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0x0000000b -#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0x0000000c -#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0x0000000d -#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0x0000000e -#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0x0000000f -#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x00000010 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x00000011 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x00000012 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x00000013 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x00000014 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x00000015 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x00000016 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x00000017 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x00000018 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x00000019 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x0000001a -#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x0000001b -#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x0000001c -#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x0000001d -#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x0000001e -#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x0000001f - -// ATC_ATS_FAULT_STATUS_INFO2 -#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x00000000 -#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x00000001 -#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x00000009 - -// ATHUB_MISC_CNTL -#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x00000006 -#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x00000012 -#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x00000013 -#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x00000014 -#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x00000015 -#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x0000001b -#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x0000001c - -// ATC_VMID_PASID_MAPPING_UPDATE_STATUS -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x00000000 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x00000001 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x00000002 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x00000003 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x00000004 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x00000005 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x00000006 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x00000007 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x00000008 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x00000009 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0x0000000a -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0x0000000b -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0x0000000c -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0x0000000d -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0x0000000e -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0x0000000f -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x00000010 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x00000011 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x00000012 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x00000013 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x00000014 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x00000015 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x00000016 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x00000017 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x00000018 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x00000019 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x0000001a -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x0000001b -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x0000001c -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x0000001d -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x0000001e -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x0000001f - -// ATC_VMID0_PASID_MAPPING -#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID1_PASID_MAPPING -#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID2_PASID_MAPPING -#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID3_PASID_MAPPING -#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID4_PASID_MAPPING -#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID5_PASID_MAPPING -#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID6_PASID_MAPPING -#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID7_PASID_MAPPING -#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID8_PASID_MAPPING -#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID9_PASID_MAPPING -#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID10_PASID_MAPPING -#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID11_PASID_MAPPING -#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID12_PASID_MAPPING -#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID13_PASID_MAPPING -#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID14_PASID_MAPPING -#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID15_PASID_MAPPING -#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_ATS_VMID_STATUS -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x00000000 -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x00000001 -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x00000002 -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x00000003 -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x00000004 -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x00000005 -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x00000006 -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x00000007 -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x00000008 -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x00000009 -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0x0000000a -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0x0000000b -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0x0000000c -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0x0000000d -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0x0000000e -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0x0000000f -#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x00000010 -#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x00000011 -#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x00000012 -#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x00000013 -#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x00000014 -#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x00000015 -#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x00000016 -#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x00000017 -#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x00000018 -#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x00000019 -#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x0000001a -#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x0000001b -#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x0000001c -#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x0000001d -#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x0000001e -#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x0000001f - -// ATC_ATS_GFX_ATCL2_STATUS -#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x00000000 - -// ATC_PERFCOUNTER0_CFG -#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x00000000 -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x00000018 -#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x0000001c -#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x0000001d - -// ATC_PERFCOUNTER1_CFG -#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x00000000 -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x00000018 -#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x0000001c -#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x0000001d - -// ATC_PERFCOUNTER2_CFG -#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x00000000 -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x00000018 -#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x0000001c -#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x0000001d - -// ATC_PERFCOUNTER3_CFG -#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x00000000 -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x00000018 -#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x0000001c -#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x0000001d - -// ATC_PERFCOUNTER_RSLT_CNTL -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x00000008 -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x00000010 -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x00000018 -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x00000019 -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x0000001a - -// ATC_PERFCOUNTER_LO -#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x00000000 - -// ATC_PERFCOUNTER_HI -#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x00000000 -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x00000010 - -// ATHUB_PCIE_ATS_CNTL -#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x00000010 -#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_PASID_CNTL -#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x00000010 -#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x00000011 -#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x00000012 - -// ATHUB_PCIE_PAGE_REQ_CNTL -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x00000000 -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x00000001 - -// ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC -#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x00000000 - -// ATHUB_COMMAND -#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x00000002 - -// ATHUB_PCIE_ATS_CNTL_VF_0 -#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_1 -#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_2 -#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_3 -#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_4 -#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_5 -#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_6 -#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_7 -#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_8 -#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_9 -#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_10 -#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_11 -#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_12 -#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_13 -#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_14 -#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_PCIE_ATS_CNTL_VF_15 -#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x0000001f - -// ATHUB_MEM_POWER_LS -#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000 -#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006 - -// ATS_IH_CREDIT -#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x00000000 -#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x00000010 - -// ATHUB_IH_CREDIT -#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x00000000 -#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x00000010 - -// ATC_VMID16_PASID_MAPPING -#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID17_PASID_MAPPING -#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID18_PASID_MAPPING -#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID19_PASID_MAPPING -#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID20_PASID_MAPPING -#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID21_PASID_MAPPING -#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID22_PASID_MAPPING -#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID23_PASID_MAPPING -#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID24_PASID_MAPPING -#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID25_PASID_MAPPING -#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID26_PASID_MAPPING -#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID27_PASID_MAPPING -#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID28_PASID_MAPPING -#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID29_PASID_MAPPING -#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID30_PASID_MAPPING -#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_VMID31_PASID_MAPPING -#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x00000000 -#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x0000001e -#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x0000001f - -// ATC_ATS_MMHUB_ATCL2_STATUS -#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x00000000 - -// ATHUB_SHARED_VIRT_RESET_REQ -#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x00000000 -#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x0000001f - -// ATHUB_SHARED_ACTIVE_FCN_ID -#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x00000000 -#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x0000001f - -// ATC_ATS_SDPPORT_CNTL -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x00000000 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x00000001 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x00000003 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x00000007 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x00000008 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x00000009 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0x0000000d -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0x0000000e -#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0x0000000f -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x00000010 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x00000011 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x00000012 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x00000013 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x00000014 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x00000015 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x00000016 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x00000017 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x00000018 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x00000019 - -// ATC_ATS_DEBUG2 -#define ATC_ATS_DEBUG2__PRI_STOP_TIME__SHIFT 0x00000000 -#define ATC_ATS_DEBUG2__MAPPING_MULTIPLE_INVALIDATE_ALL_UTCL2__SHIFT 0x00000004 -#define ATC_ATS_DEBUG2__MAPPING_DIFF_SINGLE_INVALIDATE_ALL_UTCL2__SHIFT 0x00000005 -#define ATC_ATS_DEBUG2__SNAPSHOT_FOR_WQ__SHIFT 0x00000006 -#define ATC_ATS_DEBUG2__MAPPING_SAVE_MODE__SHIFT 0x00000007 -#define ATC_ATS_DEBUG2__HOST_TRANS_MISS_MODE__SHIFT 0x00000008 -#define ATC_ATS_DEBUG2__LOG_NONFLUSH_TYPE_INVALIDATION__SHIFT 0x00000009 -#define ATC_ATS_DEBUG2__ALWAYS_BUSY__SHIFT 0x0000000a -#define ATC_ATS_DEBUG2__DISABLE_LOG_FUNCTION__SHIFT 0x0000000b -#define ATC_ATS_DEBUG2__DISABLE_PRI_RESET_WHEN_FAILURE__SHIFT 0x0000000c -#define ATC_ATS_DEBUG2__TRANS_RET_SNOOP_CNTL__SHIFT 0x0000000d -#define ATC_ATS_DEBUG2__EFFECTIVE_LOG_FIFO_DEPTH__SHIFT 0x00000018 -#define ATC_ATS_DEBUG2__FAULT_ON_NOENOUGH_PERMISSIONS__SHIFT 0x0000001c - -// ATC_ATS_VMID_SNAPSHOT_GFX_STAT -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x00000000 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x00000001 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x00000002 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x00000003 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x00000004 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x00000005 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x00000006 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x00000007 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x00000008 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x00000009 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0x0000000a -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0x0000000b -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0x0000000c -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0x0000000d -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0x0000000e -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0x0000000f - -// ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x00000000 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x00000001 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x00000002 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x00000003 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x00000004 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x00000005 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x00000006 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x00000007 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x00000008 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x00000009 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0x0000000a -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0x0000000b -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0x0000000c -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0x0000000d -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0x0000000e -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0x0000000f - -// XPB_RTR_SRC_APRTR0 -#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR1 -#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR2 -#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR3 -#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR4 -#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR5 -#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR6 -#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR7 -#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR8 -#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_SRC_APRTR9 -#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x00000000 - -// XPB_XDMA_RTR_SRC_APRTR0 -#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 - -// XPB_XDMA_RTR_SRC_APRTR1 -#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 - -// XPB_XDMA_RTR_SRC_APRTR2 -#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 - -// XPB_XDMA_RTR_SRC_APRTR3 -#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 - -// XPB_RTR_DEST_MAP0 -#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP1 -#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP2 -#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP3 -#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP4 -#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP5 -#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP6 -#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP7 -#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP8 -#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_RTR_DEST_MAP9 -#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x00000000 -#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x00000014 -#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x00000019 -#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_XDMA_RTR_DEST_MAP0 -#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 -#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_XDMA_RTR_DEST_MAP1 -#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 -#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_XDMA_RTR_DEST_MAP2 -#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 -#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_XDMA_RTR_DEST_MAP3 -#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 -#define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 -#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a - -// XPB_CLG_CFG0 -#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_CFG1 -#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_CFG2 -#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_CFG3 -#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_CFG4 -#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_CFG5 -#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_CFG6 -#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_CFG7 -#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x00000000 -#define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x00000004 -#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x00000007 -#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0x0000000a -#define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0x0000000e - -// XPB_CLG_EXTRA -#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x00000000 -#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x00000006 -#define XPB_CLG_EXTRA__VLD0__SHIFT 0x0000000b -#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0x0000000c -#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0x0000000f -#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x00000015 -#define XPB_CLG_EXTRA__VLD1__SHIFT 0x0000001a -#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x0000001b - -// XPB_CLG_EXTRA_MSK -#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x00000000 -#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x00000006 -#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0x0000000b -#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x00000011 - -// XPB_LB_ADDR -#define XPB_LB_ADDR__CMP0__SHIFT 0x00000000 -#define XPB_LB_ADDR__MASK0__SHIFT 0x0000000a -#define XPB_LB_ADDR__CMP1__SHIFT 0x00000014 -#define XPB_LB_ADDR__MASK1__SHIFT 0x0000001a - -// XPB_WCB_STS -#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x00000000 -#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000010 -#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000017 - -// XPB_HST_CFG -#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x00000000 - -// XPB_P2P_BAR_CFG -#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x00000000 -#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x00000006 -#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x00000007 -#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x00000008 -#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x00000009 -#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0x0000000a -#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0x0000000b -#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0x0000000c - -// XPB_P2P_BAR0 -#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR0__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR0__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR1 -#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR1__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR1__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR2 -#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR2__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR2__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR3 -#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR3__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR3__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR4 -#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR4__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR4__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR5 -#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR5__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR5__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR6 -#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR6__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR6__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR7 -#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x00000000 -#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x00000004 -#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR7__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR7__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR_SETUP -#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x00000000 -#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x00000008 -#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0x0000000c -#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0x0000000d -#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0x0000000e -#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0x0000000f -#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x00000010 - -// XPB_P2P_BAR_DEBUG -#define XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x00000000 -#define XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x00000008 -#define XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0x0000000c - -// XPB_P2P_BAR_DELTA_ABOVE -#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x00000000 -#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x00000008 - -// XPB_P2P_BAR_DELTA_BELOW -#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x00000000 -#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x00000008 - -// XPB_PEER_SYS_BAR0 -#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR1 -#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR2 -#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR3 -#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR4 -#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR5 -#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR6 -#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR7 -#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR8 -#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x00000001 - -// XPB_PEER_SYS_BAR9 -#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x00000000 -#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x00000001 - -// XPB_XDMA_PEER_SYS_BAR0 -#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 -#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x00000001 - -// XPB_XDMA_PEER_SYS_BAR1 -#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 -#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x00000001 - -// XPB_XDMA_PEER_SYS_BAR2 -#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 -#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x00000001 - -// XPB_XDMA_PEER_SYS_BAR3 -#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 -#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x00000001 - -// XPB_CLK_GAT -#define XPB_CLK_GAT__ONDLY__SHIFT 0x00000000 -#define XPB_CLK_GAT__OFFDLY__SHIFT 0x00000006 -#define XPB_CLK_GAT__RDYDLY__SHIFT 0x0000000c -#define XPB_CLK_GAT__ENABLE__SHIFT 0x00000012 -#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x00000013 - -// XPB_INTF_CFG -#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x00000000 -#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x00000008 -#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x00000010 -#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x00000017 -#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x00000018 -#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x00000019 -#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x0000001a -#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x0000001b -#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x0000001d -#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x0000001e -#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x0000001f - -// XPB_INTF_STS -#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x00000000 -#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x00000008 -#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0x0000000f -#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x00000010 -#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x00000011 -#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x00000012 -#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x00000013 - -// XPB_PIPE_STS -#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x00000000 -#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000001 -#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000008 -#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0x0000000f -#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x00000010 -#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x00000011 -#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x00000012 -#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x00000013 -#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x00000014 -#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x00000015 -#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x00000016 -#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x00000017 -#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x00000018 - -// XPB_SUB_CTRL -#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x00000000 -#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x00000001 -#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x00000002 -#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x00000003 -#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x00000004 -#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x00000005 -#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x00000006 -#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x00000007 -#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x00000008 -#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x00000009 -#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0x0000000a -#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0x0000000b -#define XPB_SUB_CTRL__RESET_RET__SHIFT 0x0000000c -#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0x0000000d -#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0x0000000e -#define XPB_SUB_CTRL__RESET_HST__SHIFT 0x0000000f -#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x00000010 -#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x00000011 -#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x00000012 -#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x00000013 - -// XPB_MAP_INVERT_FLUSH_NUM_LSB -#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x00000000 - -// XPB_PERF_KNOBS -#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x00000000 -#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x00000006 -#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0x0000000c - -// XPB_STICKY -#define XPB_STICKY__BITS__SHIFT 0x00000000 - -// XPB_STICKY_W1C -#define XPB_STICKY_W1C__BITS__SHIFT 0x00000000 - -// XPB_MISC_CFG -#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x00000000 -#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x00000008 -#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x00000010 -#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x00000018 -#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x0000001f - -// XPB_INTF_CFG2 -#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x00000000 - -// XPB_CLG_EXTRA_RD -#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x00000000 -#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x00000006 -#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x0000000b -#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0x0000000c -#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0x0000000f -#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x00000015 -#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x0000001a -#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x0000001b - -// XPB_CLG_EXTRA_MSK_RD -#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x00000000 -#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x00000006 -#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0x0000000b -#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x00000011 - -// XPB_CLG_GFX_MATCH -#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x00000000 -#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x00000006 -#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0x0000000c -#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x00000012 -#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x00000018 -#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x00000019 -#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x0000001a -#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x0000001b - -// XPB_CLG_GFX_MATCH_MSK -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x00000000 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x00000006 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x0000000c -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x00000012 - -// XPB_CLG_MM_MATCH -#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x00000000 -#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x00000006 -#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0x0000000c -#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x00000012 -#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x00000018 -#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x00000019 -#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x0000001a -#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x0000001b - -// XPB_CLG_MM_MATCH_MSK -#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x00000000 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x00000006 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x0000000c -#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x00000012 - -// XPB_CLG_GFX_UNITID_MAPPING0 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_GFX_UNITID_MAPPING1 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_GFX_UNITID_MAPPING2 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_GFX_UNITID_MAPPING3 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_GFX_UNITID_MAPPING4 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_GFX_UNITID_MAPPING5 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_GFX_UNITID_MAPPING6 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_GFX_UNITID_MAPPING7 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_MM_UNITID_MAPPING0 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_MM_UNITID_MAPPING1 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_MM_UNITID_MAPPING2 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x00000006 - -// XPB_CLG_MM_UNITID_MAPPING3 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x00000000 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x00000005 -#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x00000006 - -// RPB_PASSPW_CONF -#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x00000000 -#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x00000001 -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x00000002 -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x00000003 -#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x00000004 -#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x00000005 -#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x00000006 -#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x00000007 -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x00000008 -#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x00000009 -#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0x0000000a -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0x0000000b -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0x0000000c -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0x0000000d -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0x0000000e -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0x0000000f -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x00000010 -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x00000011 - -// RPB_BLOCKLEVEL_CONF -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x00000000 -#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x00000002 -#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x00000004 -#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x00000006 -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x00000008 -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0x0000000a -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0x0000000c -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x0000000e -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x0000000f -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x00000010 -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x00000011 - -// RPB_SECLEVEL_CONF -#define RPB_SECLEVEL_CONF__ATC_SECLEVEL__SHIFT 0x00000000 - -// RPB_TAG_CONF -#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x00000000 -#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x00000008 -#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x00000010 - -// RPB_DBG1 -#define RPB_DBG1__RPB_IO_RD__SHIFT 0x00000000 -#define RPB_DBG1__RPB_OUTSTANDING_RD_32B__SHIFT 0x00000008 -#define RPB_DBG1__DEBUG_BITS__SHIFT 0x00000014 - -// RPB_EFF_CNTL -#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x00000000 -#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x00000008 - -// RPB_ARB_CNTL -#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x00000000 -#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x00000008 -#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x00000010 -#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x00000018 -#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x00000019 - -// RPB_ARB_CNTL2 -#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x00000000 -#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x00000008 -#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x00000010 - -// RPB_BIF_CNTL -#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x00000000 -#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x00000008 -#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x00000010 -#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x00000011 -#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x00000012 -#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x00000013 -#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x0000001b -#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x0000001c -#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x0000001d -#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x0000001e - -// RPB_WR_SWITCH_CNTL -#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 -#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000007 -#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x0000000e -#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000015 -#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x0000001c - -// RPB_WR_COMBINE_CNTL -#define RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x00000000 -#define RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x00000002 -#define RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x00000006 - -// RPB_RD_SWITCH_CNTL -#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 -#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000007 -#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x0000000e -#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000015 -#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x0000001c - -// RPB_CID_QUEUE_WR -#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x00000000 -#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x00000005 -#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x0000000b -#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x0000000c -#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0x0000000f -#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x00000012 - -// RPB_CID_QUEUE_RD -#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x00000000 -#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x00000005 -#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x0000000b -#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0x0000000e - -// RPB_PERF_COUNTER_CNTL -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 -#define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x00000002 -#define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x00000003 -#define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x00000004 -#define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x00000005 -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x00000009 -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0x0000000e -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x00000013 -#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x00000018 - -// RPB_PERF_COUNTER_STATUS -#define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x00000000 - -// RPB_CID_QUEUE_EX -#define RPB_CID_QUEUE_EX__START__SHIFT 0x00000000 -#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x00000001 - -// RPB_CID_QUEUE_EX_DATA -#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x00000000 -#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x00000010 - -// RPB_SWITCH_CNTL2 -#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x00000000 -#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x00000007 -#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0x0000000e -#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x00000015 - -// RPB_DEINTRLV_COMBINE_CNTL -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x00000000 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x00000004 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x00000005 - -// RPB_VC_SWITCH_RDWR -#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x00000000 -#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x00000002 -#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0x0000000a - -// RPB_PERFCOUNTER_LO -#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x00000000 - -// RPB_PERFCOUNTER_HI -#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x00000000 -#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x00000010 - -// RPB_PERFCOUNTER0_CFG -#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x00000000 -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x00000018 -#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x0000001c -#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x0000001d - -// RPB_PERFCOUNTER1_CFG -#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x00000000 -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x00000018 -#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x0000001c -#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x0000001d - -// RPB_PERFCOUNTER2_CFG -#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x00000000 -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x00000018 -#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x0000001c -#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x0000001d - -// RPB_PERFCOUNTER3_CFG -#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x00000000 -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x00000018 -#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x0000001c -#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x0000001d - -// RPB_PERFCOUNTER_RSLT_CNTL -#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 -#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x00000008 -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x00000010 -#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x00000018 -#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x00000019 -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x0000001a - -// RPB_MISC_CG -#define RPB_MISC_CG__ONDLY__SHIFT 0x00000000 -#define RPB_MISC_CG__OFFDLY__SHIFT 0x00000006 -#define RPB_MISC_CG__RDYDLY__SHIFT 0x0000000c -#define RPB_MISC_CG__ENABLE__SHIFT 0x00000012 -#define RPB_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013 -#define RPB_MISC_CG__PG_EN__SHIFT 0x00000014 -#define RPB_MISC_CG__PG_IDLE_CYCLE__SHIFT 0x00000015 - -// RPB_RD_QUEUE_CNTL -#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x00000000 -#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x00000001 -#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x00000002 -#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x00000003 -#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x00000004 -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x00000005 -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0x0000000a -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x00000010 -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x00000015 - -// RPB_RD_QUEUE_CNTL2 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x00000000 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x00000005 -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0x0000000b -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x00000010 - -// RPB_WR_QUEUE_CNTL -#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x00000000 -#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x00000001 -#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x00000002 -#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x00000003 -#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x00000004 -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x00000005 -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0x0000000a -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x00000010 -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x00000015 - -// RPB_WR_QUEUE_CNTL2 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x00000000 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x00000005 -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0x0000000b -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x00000010 - -// RPB_EA_QUEUE_WR -#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x00000000 -#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x00000005 -#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x00000008 -#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0x0000000b - -// RPB_ATS_CNTL -#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x00000000 -#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x00000001 -#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x00000002 -#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x00000007 -#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0x0000000f -#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x00000013 -#define RPB_ATS_CNTL__WR_AT__SHIFT 0x00000017 -#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x00000019 - -// RPB_ATS_CNTL2 -#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x00000000 -#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x00000006 -#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0x0000000c -#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0x0000000f -#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x00000012 - -// RPB_SDPPORT_CNTL -#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x00000000 -#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x00000001 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x00000003 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x00000004 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x00000005 -#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x00000006 -#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0x0000000a -#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0x0000000b -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0x0000000d -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0x0000000e -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0x0000000f -#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x00000010 -#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x00000014 -#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x00000015 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x00000016 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x00000017 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x00000018 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x00000019 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x0000001a -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x0000001b - -// RSMU_HCID_GENERIC -#define RSMU_HCID_GENERIC__RSMU_HCID_HwRev__SHIFT 0x00000000 -#define RSMU_HCID_GENERIC__RSMU_HCID_HwMinVer__SHIFT 0x00000006 -#define RSMU_HCID_GENERIC__RSMU_HCID_HwMajVer__SHIFT 0x0000000d -#define RSMU_HCID_GENERIC__RSMU_HCID_HwID__SHIFT 0x00000014 - -// RSMU_SIID_GENERIC -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfRev__SHIFT 0x00000000 -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfMinVer__SHIFT 0x00000006 -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfMajVer__SHIFT 0x0000000d -#define RSMU_SIID_GENERIC__RSMU_SIID_SwIfID__SHIFT 0x00000014 - -// RSMU_DBG_MUX_CONTROL_GENERIC -#define RSMU_DBG_MUX_CONTROL_GENERIC__RSMU_DBG_MUX_SELECT__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_ADDR_0_GENERIC -#define RSMU_SW_MMIO_PUB_IND_ADDR_0_GENERIC__RSMU_SW_MMIO_PUB_IND_ADDR_0__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_DATA_0_GENERIC -#define RSMU_SW_MMIO_PUB_IND_DATA_0_GENERIC__RSMU_SW_MMIO_PUB_IND_DATA_0__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_ADDR_1_GENERIC -#define RSMU_SW_MMIO_PUB_IND_ADDR_1_GENERIC__RSMU_SW_MMIO_PUB_IND_ADDR_1__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_DATA_1_GENERIC -#define RSMU_SW_MMIO_PUB_IND_DATA_1_GENERIC__RSMU_SW_MMIO_PUB_IND_DATA_1__SHIFT 0x00000000 - -// RSMU_SOFT_RESETB_GENERIC -#define RSMU_SOFT_RESETB_GENERIC__RSMU_SOFT_RESETB__SHIFT 0x00000000 -#define RSMU_SOFT_RESETB_GENERIC__RSMU_MASTER_SOFT_RESET_FENCE_ENABLE__SHIFT 0x00000002 -#define RSMU_SOFT_RESETB_GENERIC__RSMU_SLAVE_SOFT_RESET_TIMEOUT_ENABLE__SHIFT 0x00000004 - -// RSMU_PGFSM_CONTROL_GENERIC -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_SW_CONTROL__SHIFT 0x00000000 -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_CMD__SHIFT 0x00000001 -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_ADDR__SHIFT 0x00000004 -#define RSMU_PGFSM_CONTROL_GENERIC__RSMU_PGFSM_SELECT__SHIFT 0x00000008 - -// RSMU_PGFSM_WR_DATA_GENERIC -#define RSMU_PGFSM_WR_DATA_GENERIC__RSMU_PGFSM_WR_DATA__SHIFT 0x00000000 - -// RSMU_PGFSM_RD_DATA_GENERIC -#define RSMU_PGFSM_RD_DATA_GENERIC__RSMU_PGFSM_RD_DATA__SHIFT 0x00000000 - -// RSMU_IH_CREDIT_GENERIC -#define RSMU_IH_CREDIT_GENERIC__RSMU_IH_CREDIT__SHIFT 0x00000000 - -// RSMU_IH_RESET_CNTL_GENERIC -#define RSMU_IH_RESET_CNTL_GENERIC__RSMU_IH_RESET__SHIFT 0x00000000 -#define RSMU_IH_RESET_CNTL_GENERIC__RSMU_IH_HARD_RESET_ENABLE__SHIFT 0x00000001 -#define RSMU_IH_RESET_CNTL_GENERIC__RSMU_IH_SOFT_RESET_ENABLE__SHIFT 0x00000002 - -// RSMU_SEM_RESP_GENERIC -#define RSMU_SEM_RESP_GENERIC__RSMU_SEM_RESP__SHIFT 0x00000000 - -// RSMU_SEM_RESET_CNTL_GENERIC -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_RESET__SHIFT 0x00000000 -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_HARD_RESET_ENABLE__SHIFT 0x00000001 -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_SOFT_RESET_ENABLE__SHIFT 0x00000002 -#define RSMU_SEM_RESET_CNTL_GENERIC__RSMU_SEM_RESET_PROTECT_ENABLE__SHIFT 0x00000003 - -// RSMU_VIRTUAL_WIRE_SRC_ID_GENERIC -#define RSMU_VIRTUAL_WIRE_SRC_ID_GENERIC__RSMU_VIRTUAL_WIRE_SRC_ID__SHIFT 0x00000000 - -// RSMU_VIRTUAL_WIRE_INDEX_GENERIC -#define RSMU_VIRTUAL_WIRE_INDEX_GENERIC__RSMU_VIRTUAL_WIRE_INDEX__SHIFT 0x00000000 - -// RSMU_SW_STRAPRX_ADDR_GENERIC -#define RSMU_SW_STRAPRX_ADDR_GENERIC__RSMU_SW_STRAPRX_ADDR__SHIFT 0x00000000 - -// RSMU_SW_STRAPRX_DATA_GENERIC -#define RSMU_SW_STRAPRX_DATA_GENERIC__RSMU_SW_STRAPRX_DATA__SHIFT 0x00000000 - -// RSMU_SW_STRAP_CONTROL_GENERIC -#define RSMU_SW_STRAP_CONTROL_GENERIC__RSMU_SW_PUB_FUSE_RELOAD__SHIFT 0x00000000 -#define RSMU_SW_STRAP_CONTROL_GENERIC__RSMU_SW_ROM_RELOAD__SHIFT 0x00000001 - -// RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_ADDR__SHIFT 0x00000000 -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_APERTUREID__SHIFT 0x00000014 -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_INITIATORID__SHIFT 0x00000016 -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_OP__SHIFT 0x0000001e -#define RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC__RSMU_TIMEOUT_ERROR_OUTSTANDING__SHIFT 0x0000001f - -// RSMU_IP_MASTER_STATUS_GENERIC -#define RSMU_IP_MASTER_STATUS_GENERIC__RSMU_IP_MASTER_REQ_PENDING__SHIFT 0x00000000 -#define RSMU_IP_MASTER_STATUS_GENERIC__RSMU_IP_MASTER_RESP_PENDING__SHIFT 0x00000001 - -// RSMU_GPUREG_SCRATCH_REG_0_GENERIC -#define RSMU_GPUREG_SCRATCH_REG_0_GENERIC__RSMU_GPUREG_SCRATCH_REG_0__SHIFT 0x00000000 - -// RSMU_GPUREG_SCRATCH_REG_1_GENERIC -#define RSMU_GPUREG_SCRATCH_REG_1_GENERIC__RSMU_GPUREG_SCRATCH_REG_1__SHIFT 0x00000000 - -// RSMU_COLD_RESETB_GENERIC -#define RSMU_COLD_RESETB_GENERIC__RSMU_COLD_RESETB__SHIFT 0x00000000 - -// RSMU_HARD_RESETB_GENERIC -#define RSMU_HARD_RESETB_GENERIC__RSMU_HARD_RESETB__SHIFT 0x00000000 -#define RSMU_HARD_RESETB_GENERIC__RSMU_MASTER_HARD_RESET_FENCE_ENABLE__SHIFT 0x00000002 -#define RSMU_HARD_RESETB_GENERIC__RSMU_SLAVE_HARD_RESET_TIMEOUT_ENABLE__SHIFT 0x00000005 - -// RSMU_PUB_FUSE_ADDR_GENERIC -#define RSMU_PUB_FUSE_ADDR_GENERIC__RSMU_PUB_FUSE_START_ADDR__SHIFT 0x00000000 -#define RSMU_PUB_FUSE_ADDR_GENERIC__RSMU_PUB_FUSE_END_ADDR__SHIFT 0x00000010 - -// RSMU_SEC_FUSE_ADDR_GENERIC -#define RSMU_SEC_FUSE_ADDR_GENERIC__RSMU_SEC_FUSE_START_ADDR__SHIFT 0x00000000 -#define RSMU_SEC_FUSE_ADDR_GENERIC__RSMU_SEC_FUSE_END_ADDR__SHIFT 0x00000010 - -// RSMU_ROM_ADDR_GENERIC -#define RSMU_ROM_ADDR_GENERIC__RSMU_ROM_START_ADDR__SHIFT 0x00000000 -#define RSMU_ROM_ADDR_GENERIC__RSMU_ROM_END_ADDR__SHIFT 0x00000010 - -// RSMU_MEM_POWER_CTRL_GENERIC -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_FUSE_RM_FUSES__SHIFT 0x00000000 -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_RF_BC1__SHIFT 0x00000009 -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_RF_BC2__SHIFT 0x0000000a -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_PDP_BC1__SHIFT 0x0000000b -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_PDP_BC2__SHIFT 0x0000000c -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_HD_BC1__SHIFT 0x0000000d -#define RSMU_MEM_POWER_CTRL_GENERIC__RSMU_MEM_POWER_CTRL_HD_BC2__SHIFT 0x0000000e - -// RSMU_MP0_STRAPRX_ADDR_GENERIC -#define RSMU_MP0_STRAPRX_ADDR_GENERIC__RSMU_MP0_STRAPRX_ADDR__SHIFT 0x00000000 - -// RSMU_MP0_STRAPRX_DATA_GENERIC -#define RSMU_MP0_STRAPRX_DATA_GENERIC__RSMU_MP0_STRAPRX_DATA__SHIFT 0x00000000 - -// RSMU_SMS_FUSE_CFG_GENERIC -#define RSMU_SMS_FUSE_CFG_GENERIC__RSMU_SMS_FUSE_RESETB__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_CFG_GENERIC__RSMU_SMS_FUSE_RUN_BIHR__SHIFT 0x00000001 -#define RSMU_SMS_FUSE_CFG_GENERIC__RSMU_SMS_FUSE_RUN_MBIST__SHIFT 0x00000002 - -// RSMU_SMS_FUSE_ADDR_BASE_GENERIC -#define RSMU_SMS_FUSE_ADDR_BASE_GENERIC__RSMU_SMS_FUSE_ADDR_BASE__SHIFT 0x00000000 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP0__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP1__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP2__SHIFT 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP3__SHIFT 0x00000018 - -// RSMU_STRAP_CONTROL_GENERIC -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PUB_FUSE_READY__SHIFT 0x00000000 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PUB_FUSE_VALID__SHIFT 0x00000001 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PUB_FUSE_RELOAD__SHIFT 0x00000002 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_ROM_READY__SHIFT 0x00000003 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_ROM_VALID__SHIFT 0x00000004 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_ROM_RELOAD__SHIFT 0x00000005 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_PIN_RELOAD__SHIFT 0x00000006 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SEC_FUSE_READY__SHIFT 0x00000007 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SEC_FUSE_VALID__SHIFT 0x00000008 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP0__SHIFT 0x00000009 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP1__SHIFT 0x0000000a -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP2__SHIFT 0x0000000b -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_READY_GRP3__SHIFT 0x0000000c -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP0__SHIFT 0x0000000d -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP1__SHIFT 0x0000000e -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP2__SHIFT 0x0000000f -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_VALID_GRP3__SHIFT 0x00000010 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP0__SHIFT 0x00000011 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP1__SHIFT 0x00000012 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP2__SHIFT 0x00000013 -#define RSMU_STRAP_CONTROL_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP3__SHIFT 0x00000014 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP4__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP5__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP6__SHIFT 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP7__SHIFT 0x00000018 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP8__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP9__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP10__SHIFT \ - 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP11__SHIFT \ - 0x00000018 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP12__SHIFT \ - 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP13__SHIFT \ - 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP14__SHIFT \ - 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP15__SHIFT \ - 0x00000018 - -// RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP4__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP5__SHIFT 0x00000001 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP6__SHIFT 0x00000002 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP7__SHIFT 0x00000003 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP8__SHIFT 0x00000004 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP9__SHIFT 0x00000005 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP10__SHIFT 0x00000006 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP11__SHIFT 0x00000007 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP12__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP13__SHIFT 0x00000009 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP14__SHIFT 0x0000000a -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_READY_GRP15__SHIFT 0x0000000b - -// RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP4__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP5__SHIFT 0x00000001 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP6__SHIFT 0x00000002 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP7__SHIFT 0x00000003 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP8__SHIFT 0x00000004 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP9__SHIFT 0x00000005 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP10__SHIFT 0x00000006 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP11__SHIFT 0x00000007 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP12__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP13__SHIFT 0x00000009 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP14__SHIFT 0x0000000a -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_VALID_GRP15__SHIFT 0x0000000b -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP4__SHIFT \ - 0x0000000c -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP5__SHIFT \ - 0x0000000d -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP6__SHIFT \ - 0x0000000e -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP7__SHIFT \ - 0x0000000f -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP8__SHIFT \ - 0x00000010 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP9__SHIFT \ - 0x00000011 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP10__SHIFT \ - 0x00000012 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP11__SHIFT \ - 0x00000013 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP12__SHIFT \ - 0x00000014 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP13__SHIFT \ - 0x00000015 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP14__SHIFT \ - 0x00000016 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC__RSMU_SMS_FUSE_BIST_FAIL_GRP15__SHIFT \ - 0x00000017 - -// RSMU_CAC_LKG_WEIGHT_0_GENERIC -#define RSMU_CAC_LKG_WEIGHT_0_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_0__SHIFT 0x00000000 -#define RSMU_CAC_LKG_WEIGHT_0_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_0__SHIFT 0x00000010 - -// RSMU_CAC_LKG_WEIGHT_1_GENERIC -#define RSMU_CAC_LKG_WEIGHT_1_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_1__SHIFT 0x00000000 -#define RSMU_CAC_LKG_WEIGHT_1_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_1__SHIFT 0x00000010 - -// RSMU_CAC_LKG_WEIGHT_2_GENERIC -#define RSMU_CAC_LKG_WEIGHT_2_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_2__SHIFT 0x00000000 -#define RSMU_CAC_LKG_WEIGHT_2_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_2__SHIFT 0x00000010 - -// RSMU_CAC_LKG_WEIGHT_3_GENERIC -#define RSMU_CAC_LKG_WEIGHT_3_GENERIC__RSMU_CAC_LKG_WEIGHT_LO_3__SHIFT 0x00000000 -#define RSMU_CAC_LKG_WEIGHT_3_GENERIC__RSMU_CAC_LKG_WEIGHT_HI_3__SHIFT 0x00000010 - -// RSMU_CAC_LKG_ACC_0_GENERIC -#define RSMU_CAC_LKG_ACC_0_GENERIC__RSMU_CAC_LKG_ACC_0__SHIFT 0x00000000 - -// RSMU_CAC_LKG_ACC_1_GENERIC -#define RSMU_CAC_LKG_ACC_1_GENERIC__RSMU_CAC_LKG_ACC_1__SHIFT 0x00000000 - -// RSMU_CAC_LKG_ACC_2_GENERIC -#define RSMU_CAC_LKG_ACC_2_GENERIC__RSMU_CAC_LKG_ACC_2__SHIFT 0x00000000 - -// RSMU_CAC_LKG_ACC_3_GENERIC -#define RSMU_CAC_LKG_ACC_3_GENERIC__RSMU_CAC_LKG_ACC_3__SHIFT 0x00000000 - -// RSMU_CAC_LKG_ACC_4_GENERIC -#define RSMU_CAC_LKG_ACC_4_GENERIC__RSMU_CAC_LKG_ACC_4__SHIFT 0x00000000 - -// RSMU_CAC_LKG_ACC_5_GENERIC -#define RSMU_CAC_LKG_ACC_5_GENERIC__RSMU_CAC_LKG_ACC_5__SHIFT 0x00000000 - -// RSMU_CAC_LKG_ACC_6_GENERIC -#define RSMU_CAC_LKG_ACC_6_GENERIC__RSMU_CAC_LKG_ACC_6__SHIFT 0x00000000 - -// RSMU_CAC_LKG_ACC_7_GENERIC -#define RSMU_CAC_LKG_ACC_7_GENERIC__RSMU_CAC_LKG_ACC_7__SHIFT 0x00000000 - -// RSMU_CAC_CONTROL_GENERIC -#define RSMU_CAC_CONTROL_GENERIC__RSMU_CAC_WINDOW__SHIFT 0x00000000 -#define RSMU_CAC_CONTROL_GENERIC__RSMU_CAC_ENABLE__SHIFT 0x0000001f - -// RSMU_CAC_WEIGHT_0_GENERIC -#define RSMU_CAC_WEIGHT_0_GENERIC__CAC_WEIGHT_LO_0__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_0_GENERIC__CAC_WEIGHT_HI_0__SHIFT 0x00000010 - -// RSMU_CAC_WEIGHT_1_GENERIC -#define RSMU_CAC_WEIGHT_1_GENERIC__CAC_WEIGHT_LO_1__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_1_GENERIC__CAC_WEIGHT_HI_1__SHIFT 0x00000010 - -// RSMU_CAC_WEIGHT_2_GENERIC -#define RSMU_CAC_WEIGHT_2_GENERIC__CAC_WEIGHT_LO_2__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_2_GENERIC__CAC_WEIGHT_HI_2__SHIFT 0x00000010 - -// RSMU_CAC_WEIGHT_3_GENERIC -#define RSMU_CAC_WEIGHT_3_GENERIC__CAC_WEIGHT_LO_3__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_3_GENERIC__CAC_WEIGHT_HI_3__SHIFT 0x00000010 - -// RSMU_CAC_WEIGHT_4_GENERIC -#define RSMU_CAC_WEIGHT_4_GENERIC__CAC_WEIGHT_LO_4__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_4_GENERIC__CAC_WEIGHT_HI_4__SHIFT 0x00000010 - -// RSMU_CAC_WEIGHT_5_GENERIC -#define RSMU_CAC_WEIGHT_5_GENERIC__CAC_WEIGHT_LO_5__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_5_GENERIC__CAC_WEIGHT_HI_5__SHIFT 0x00000010 - -// RSMU_CAC_WEIGHT_6_GENERIC -#define RSMU_CAC_WEIGHT_6_GENERIC__CAC_WEIGHT_LO_6__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_6_GENERIC__CAC_WEIGHT_HI_6__SHIFT 0x00000010 - -// RSMU_CAC_WEIGHT_7_GENERIC -#define RSMU_CAC_WEIGHT_7_GENERIC__CAC_WEIGHT_LO_7__SHIFT 0x00000000 -#define RSMU_CAC_WEIGHT_7_GENERIC__CAC_WEIGHT_HI_7__SHIFT 0x00000010 - -// RSMU_CAC_ACC_0_GENERIC -#define RSMU_CAC_ACC_0_GENERIC__RSMU_CAC_ACC_0__SHIFT 0x00000000 - -// RSMU_CAC_ACC_1_GENERIC -#define RSMU_CAC_ACC_1_GENERIC__RSMU_CAC_ACC_1__SHIFT 0x00000000 - -// RSMU_CAC_ACC_2_GENERIC -#define RSMU_CAC_ACC_2_GENERIC__RSMU_CAC_ACC_2__SHIFT 0x00000000 - -// RSMU_CAC_ACC_3_GENERIC -#define RSMU_CAC_ACC_3_GENERIC__RSMU_CAC_ACC_3__SHIFT 0x00000000 - -// RSMU_CAC_ACC_4_GENERIC -#define RSMU_CAC_ACC_4_GENERIC__RSMU_CAC_ACC_4__SHIFT 0x00000000 - -// RSMU_CAC_ACC_5_GENERIC -#define RSMU_CAC_ACC_5_GENERIC__RSMU_CAC_ACC_5__SHIFT 0x00000000 - -// RSMU_CAC_ACC_6_GENERIC -#define RSMU_CAC_ACC_6_GENERIC__RSMU_CAC_ACC_6__SHIFT 0x00000000 - -// RSMU_CAC_ACC_7_GENERIC -#define RSMU_CAC_ACC_7_GENERIC__RSMU_CAC_ACC_7__SHIFT 0x00000000 - -// RSMU_CAC_ACC_8_GENERIC -#define RSMU_CAC_ACC_8_GENERIC__RSMU_CAC_ACC_8__SHIFT 0x00000000 - -// RSMU_CAC_ACC_9_GENERIC -#define RSMU_CAC_ACC_9_GENERIC__RSMU_CAC_ACC_9__SHIFT 0x00000000 - -// RSMU_CAC_ACC_10_GENERIC -#define RSMU_CAC_ACC_10_GENERIC__RSMU_CAC_ACC_10__SHIFT 0x00000000 - -// RSMU_CAC_ACC_11_GENERIC -#define RSMU_CAC_ACC_11_GENERIC__RSMU_CAC_ACC_11__SHIFT 0x00000000 - -// RSMU_CAC_ACC_12_GENERIC -#define RSMU_CAC_ACC_12_GENERIC__RSMU_CAC_ACC_12__SHIFT 0x00000000 - -// RSMU_CAC_ACC_13_GENERIC -#define RSMU_CAC_ACC_13_GENERIC__RSMU_CAC_ACC_13__SHIFT 0x00000000 - -// RSMU_CAC_ACC_14_GENERIC -#define RSMU_CAC_ACC_14_GENERIC__RSMU_CAC_ACC_14__SHIFT 0x00000000 - -// RSMU_CAC_ACC_15_GENERIC -#define RSMU_CAC_ACC_15_GENERIC__RSMU_CAC_ACC_15__SHIFT 0x00000000 - -// RSMU_CAC_AGGR_LO_GENERIC -#define RSMU_CAC_AGGR_LO_GENERIC__RSMU_CAC_AGGR_LO__SHIFT 0x00000000 - -// RSMU_CAC_AGGR_HI_GENERIC -#define RSMU_CAC_AGGR_HI_GENERIC__RSMU_CAC_AGGR_HI__SHIFT 0x00000000 - -// RSMU_DPM_CONTROL_GENERIC -#define RSMU_DPM_CONTROL_GENERIC__RSMU_DPM_ACC_RESET__SHIFT 0x00000000 -#define RSMU_DPM_CONTROL_GENERIC__RSMU_DPM_ACC_START__SHIFT 0x00000001 -#define RSMU_DPM_CONTROL_GENERIC__RSMU_DPM_BUSY_MASK__SHIFT 0x00000002 - -// RSMU_DPM_ACC_GENERIC -#define RSMU_DPM_ACC_GENERIC__RSMU_DPM_ACC__SHIFT 0x00000000 - -// RSMU_DPM_IPCLK_REF_COUNTER_GENERIC -#define RSMU_DPM_IPCLK_REF_COUNTER_GENERIC__RSMU_DPM_IPCLK_REF_COUNTER__SHIFT 0x00000000 - -// RSMU_COUNTER_0_GENERIC -#define RSMU_COUNTER_0_GENERIC__RSMU_COUNTER_0__SHIFT 0x00000000 - -// RSMU_COUNTER_1_GENERIC -#define RSMU_COUNTER_1_GENERIC__RSMU_COUNTER_1__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_ENABLE_P0_GENERIC -#define RSMU_PWRMGT_INTR_ENABLE_P0_GENERIC__RSMU_PWRMGT_INTR_ENABLE_P0__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_ENABLE_P1_GENERIC -#define RSMU_PWRMGT_INTR_ENABLE_P1_GENERIC__RSMU_PWRMGT_INTR_ENABLE_P1__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_ENABLE_P2_GENERIC -#define RSMU_PWRMGT_INTR_ENABLE_P2_GENERIC__RSMU_PWRMGT_INTR_ENABLE_P2__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_TARGET_ADDR_P0_GENERIC -#define RSMU_PWRMGT_INTR_TARGET_ADDR_P0_GENERIC__RSMU_PWRMGT_INTR_TARGET_ADDR_P0__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_TARGET_ADDR_P1_GENERIC -#define RSMU_PWRMGT_INTR_TARGET_ADDR_P1_GENERIC__RSMU_PWRMGT_INTR_TARGET_ADDR_P1__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_TARGET_ADDR_P2_GENERIC -#define RSMU_PWRMGT_INTR_TARGET_ADDR_P2_GENERIC__RSMU_PWRMGT_INTR_TARGET_ADDR_P2__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_CONFIG_P0_GENERIC -#define RSMU_PWRMGT_INTR_CONFIG_P0_GENERIC__RSMU_PWRMGT_INTR_CONFIG_VC_P0__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_CONFIG_P1_GENERIC -#define RSMU_PWRMGT_INTR_CONFIG_P1_GENERIC__RSMU_PWRMGT_INTR_CONFIG_VC_P1__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_CONFIG_P2_GENERIC -#define RSMU_PWRMGT_INTR_CONFIG_P2_GENERIC__RSMU_PWRMGT_INTR_CONFIG_VC_P2__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_STATUS_GENERIC -#define RSMU_PWRMGT_INTR_STATUS_GENERIC__RSMU_PWRMGT_INTR_STATUS__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_PENDING_P0_GENERIC -#define RSMU_PWRMGT_INTR_PENDING_P0_GENERIC__RSMU_PWRMGT_INTR_PENDING_P0__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_PENDING_P1_GENERIC -#define RSMU_PWRMGT_INTR_PENDING_P1_GENERIC__RSMU_PWRMGT_INTR_PENDING_P1__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_PENDING_P2_GENERIC -#define RSMU_PWRMGT_INTR_PENDING_P2_GENERIC__RSMU_PWRMGT_INTR_PENDING_P2__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_TYPE_GENERIC -#define RSMU_PWRMGT_INTR_TYPE_GENERIC__RSMU_PWRMGT_INTR_TYPE__SHIFT 0x00000000 - -// RSMU_PWRMGT_INTR_INTERCEPT_GENERIC -#define RSMU_PWRMGT_INTR_INTERCEPT_GENERIC__RSMU_PWRMGT_INTR_OVERRIDE__SHIFT 0x00000000 -#define RSMU_PWRMGT_INTR_INTERCEPT_GENERIC__RSMU_PWRMGT_INTR_VALUE__SHIFT 0x00000010 - -// RSMU_PWRMGT_INTR_CLEAR_GENERIC -#define RSMU_PWRMGT_INTR_CLEAR_GENERIC__RSMU_PWRMGT_INTR_CLEAR__SHIFT 0x00000000 - -// RSMU_HARD_RESETB_DELAY_GENERIC -#define RSMU_HARD_RESETB_DELAY_GENERIC__RSMU_HARD_RESETB_DELAY__SHIFT 0x00000000 - -// RSMU_MMIOPUB_SCRATCH_REG_0_GENERIC -#define RSMU_MMIOPUB_SCRATCH_REG_0_GENERIC__RSMU_MMIOPUB_SCRATCH_REG_0__SHIFT 0x00000000 - -// RSMU_VF_ENABLE_GENERIC -#define RSMU_VF_ENABLE_GENERIC__RSMU_VF_ENABLE__SHIFT 0x00000000 - -// RSMU_MGCG_CONTROL_GENERIC -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_AXI_SLAVE_MGCG_OVERRIDE__SHIFT 0x00000000 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_AXI_MASTER_MGCG_OVERRIDE__SHIFT 0x00000001 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_SEC_INTR_MGCG_OVERRIDE__SHIFT 0x00000002 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_PWRMGT_INTR_MGCG_OVERRIDE__SHIFT 0x00000003 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_REG_WRAPPER_MGCG_OVERRIDE__SHIFT 0x00000004 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_STRAP_MASTER_MGCG_OVERRIDE__SHIFT 0x00000005 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_VWIRE_SRC_MGCG_OVERRIDE__SHIFT 0x00000006 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_REGIF_MASTER_MGCG_OVERRIDE__SHIFT 0x00000007 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_PGFSM_MGCG_OVERRIDE__SHIFT 0x00000008 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_IH_MGCG_OVERRIDE__SHIFT 0x00000009 -#define RSMU_MGCG_CONTROL_GENERIC__RSMU_SEM_MGCG_OVERRIDE__SHIFT 0x0000000a - -// RSMU_CUSTOM_HARD_RESETB_GENERIC -#define RSMU_CUSTOM_HARD_RESETB_GENERIC__RSMU_CUSTOM_HARD_RESETB__SHIFT 0x00000000 - -// RSMU_SEC_AXI_MASTER_ENABLE_GENERIC -#define RSMU_SEC_AXI_MASTER_ENABLE_GENERIC__RSMU_SEC_AXI_MASTER_ENABLE__SHIFT 0x00000000 - -// RSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC__RSMU_SEC_SLAVE_ERROR_COUNTER__SHIFT 0x00000000 -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC__RSMU_SEC_SLAVE_ERROR_COUNTER_RSMU__SHIFT 0x00000010 - -// RSMU_AXI_MASTER_QOS_CNTL_GENERIC -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_MASTER_QOS_OVRD_MODE__SHIFT 0x00000000 -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_MASTER_QOS_OVRD_VALUE__SHIFT 0x00000001 -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_AWQOS_OVRD_MODE__SHIFT 0x00000005 -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_AWQOS_OVRD_VALUE__SHIFT 0x00000006 -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_ARQOS_OVRD_MODE__SHIFT 0x0000000a -#define RSMU_AXI_MASTER_QOS_CNTL_GENERIC__RSMU_IP_MASTER_ARQOS_OVRD_VALUE__SHIFT 0x0000000b - -// RSMU_MASTER_ERROR_COUNTER_GENERIC -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_SMN_SLVERR_COUNTER__SHIFT 0x00000000 -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_SMN_DECERR_COUNTER__SHIFT 0x00000008 -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_MASTER_SLVERR_COUNTER__SHIFT 0x00000010 -#define RSMU_MASTER_ERROR_COUNTER_GENERIC__RSMU_MASTER_DECERR_COUNTER__SHIFT 0x00000018 - -// RSMU_SLAVE_TIMEOUT_VALUE_GENERIC -#define RSMU_SLAVE_TIMEOUT_VALUE_GENERIC__RSMU_SLAVE_TIMEOUT_VALUE__SHIFT 0x00000000 - -// RSMU_RESET_TIMEOUT_CONTROL_GENERIC -#define RSMU_RESET_TIMEOUT_CONTROL_GENERIC__RSMU_SLAVE_TIMEOUT_ENABLE__SHIFT 0x00000000 -#define RSMU_RESET_TIMEOUT_CONTROL_GENERIC__RSMU_SLAVE_RESET_TIMEOUT_VALUE__SHIFT 0x00000001 - -// RSMU_SLAVE_ERROR_COUNTER_GENERIC -#define RSMU_SLAVE_ERROR_COUNTER_GENERIC__RSMU_SLAVE_ERROR_COUNTER__SHIFT 0x00000000 - -// RSMU_AEB_LOCK_0_GENERIC -#define RSMU_AEB_LOCK_0_GENERIC__RSMU_AEB_LOCK_0__SHIFT 0x00000003 - -// RSMU_AEB_LOCK_1_GENERIC -#define RSMU_AEB_LOCK_1_GENERIC__RSMU_AEB_LOCK_1__SHIFT 0x00000000 - -// RSMU_AEB_OVERRIDE_0_GENERIC -#define RSMU_AEB_OVERRIDE_0_GENERIC__RSMU_AEB_OVERRIDE_0__SHIFT 0x00000003 - -// RSMU_AEB_OVERRIDE_1_GENERIC -#define RSMU_AEB_OVERRIDE_1_GENERIC__RSMU_AEB_OVERRIDE_1__SHIFT 0x00000000 - -// RSMU_SEC_INTR_ENABLE_GENERIC -#define RSMU_SEC_INTR_ENABLE_GENERIC__RSMU_SEC_INTR_ENABLE__SHIFT 0x00000000 - -// RSMU_SEC_INTR_TARGET_ADDR_GENERIC -#define RSMU_SEC_INTR_TARGET_ADDR_GENERIC__RSMU_SEC_INTR_TARGET_ADDR__SHIFT 0x00000000 - -// RSMU_SEC_INTR_CONFIG_GENERIC -#define RSMU_SEC_INTR_CONFIG_GENERIC__RSMU_SEC_INTR_CONFIG_VC__SHIFT 0x00000000 - -// RSMU_SEC_INTR_STATUS_GENERIC -#define RSMU_SEC_INTR_STATUS_GENERIC__RSMU_SEC_INTR_STATUS__SHIFT 0x00000000 - -// RSMU_SEC_INTR_PENDING_GENERIC -#define RSMU_SEC_INTR_PENDING_GENERIC__RSMU_SEC_INTR_PENDING__SHIFT 0x00000000 - -// RSMU_SEC_INTR_TYPE_GENERIC -#define RSMU_SEC_INTR_TYPE_GENERIC__RSMU_SEC_INTR_TYPE__SHIFT 0x00000000 - -// RSMU_SEC_INTR_INTERCEPT_GENERIC -#define RSMU_SEC_INTR_INTERCEPT_GENERIC__RSMU_SEC_INTR_OVERRIDE__SHIFT 0x00000000 -#define RSMU_SEC_INTR_INTERCEPT_GENERIC__RSMU_SEC_INTR_VALUE__SHIFT 0x00000010 - -// RSMU_SEC_INTR_CLEAR_GENERIC -#define RSMU_SEC_INTR_CLEAR_GENERIC__RSMU_SEC_INTR_CLEAR__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_0_GENERIC -#define RSMU_SEC_MASTER_TRUST_LEVEL_0_GENERIC__RSMU_SEC_MASTER_TRUST_LEVEL_0__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GENERIC -#define RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GENERIC__RSMU_SEC_MASTER_TRUST_LEVEL_RSMU__SHIFT 0x00000000 - -// RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE1__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE2__SHIFT 0x00000001 -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC__RSMU_SEC_TLVL_MASK_RSMU_RANGE2__SHIFT 0x00000002 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_DEFAULT__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_DEFAULT__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_DEFAULT__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_DEFAULT__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_0_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_0_GENERIC__RSMU_SEC_START_ADDR_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_0_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_0_GENERIC__RSMU_SEC_END_ADDR_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_0_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_0__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_0__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_0__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_0__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_0__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_0_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_0__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_0__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_0__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_0__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_0__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_0__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_0__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_0__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_0__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_0__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_0__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_0__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_0__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_1_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_1_GENERIC__RSMU_SEC_START_ADDR_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_1_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_1_GENERIC__RSMU_SEC_END_ADDR_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_1_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_1__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_1__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_1__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_1__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_1__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_1_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_1__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_1__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_1__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_1__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_1__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_1__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_1__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_1__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_1__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_1__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_1__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_1__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_1__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_2_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_2_GENERIC__RSMU_SEC_START_ADDR_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_2_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_2_GENERIC__RSMU_SEC_END_ADDR_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_2_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_2__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_2__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_2__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_2__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_2__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_2_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_2__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_2__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_2__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_2__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_2__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_2__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_2__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_2__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_2__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_2__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_2__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_2__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_2__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_3_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_3_GENERIC__RSMU_SEC_START_ADDR_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_3_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_3_GENERIC__RSMU_SEC_END_ADDR_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_3_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_3__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_3__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_3__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_3__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_3__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_3_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_3__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_3__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_3__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_3__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_3__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_3__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_3__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_3__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_3__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_3__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_3__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_3__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_3__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_4_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_4_GENERIC__RSMU_SEC_START_ADDR_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_4_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_4_GENERIC__RSMU_SEC_END_ADDR_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_4_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_4__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_4__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_4__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_4__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_4__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_4_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_4__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_4__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_4__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_4__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_4__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_4__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_4__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_4__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_4__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_4__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_4__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_4__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_4__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_5_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_5_GENERIC__RSMU_SEC_START_ADDR_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_5_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_5_GENERIC__RSMU_SEC_END_ADDR_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_5_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_5__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_5__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_5__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_5__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_5__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_5_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_5__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_5__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_5__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_5__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_5__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_5__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_5__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_5__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_5__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_5__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_5__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_5__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_5__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_6_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_6_GENERIC__RSMU_SEC_START_ADDR_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_6_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_6_GENERIC__RSMU_SEC_END_ADDR_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_6_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_6__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_6__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_6__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_6__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_6__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_6_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_6__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_6__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_6__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_6__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_6__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_6__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_6__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_6__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_6__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_6__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_6__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_6__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_6__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_7_GENERIC -#define RSMU_SEC_START_ADDR_GROUP_7_GENERIC__RSMU_SEC_START_ADDR_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_7_GENERIC -#define RSMU_SEC_END_ADDR_GROUP_7_GENERIC__RSMU_SEC_END_ADDR_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_7_GENERIC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_INITID_MASK_SET0_GROUP_7__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GENERIC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_UNITID_MASK_SET0_GROUP_7__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_TLVL_MASK_SET0_GROUP_7__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_RW_MASK_SET0_GROUP_7__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC__RSMU_SEC_VF_MASK_SET0_GROUP_7__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_7_GENERIC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_INITID_MASK_SET1_GROUP_7__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GENERIC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_UNITID_MASK_SET1_GROUP_7__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_TLVL_MASK_SET1_GROUP_7__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_RW_MASK_SET1_GROUP_7__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC__RSMU_SEC_VF_MASK_SET1_GROUP_7__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_7__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_7__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_7__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_7__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_7__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_7__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_7__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_7__SHIFT \ - 0x0000000f - -// RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_ADDR__SHIFT 0x00000000 -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_APERTUREID__SHIFT 0x00000014 -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_INITIATORID__SHIFT 0x00000016 -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_OP__SHIFT 0x0000001e -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC__RSMU_SEC_SLAVE_ERROR_OUTSTANDING__SHIFT 0x0000001f - -// RSMU_MMIOSEC_SCRATCH_REG_0_GENERIC -#define RSMU_MMIOSEC_SCRATCH_REG_0_GENERIC__RSMU_MMIOSEC_SCRATCH_REG_0__SHIFT 0x00000000 - -// RSMU_HCID_GC -#define RSMU_HCID_GC__RSMU_HCID_HwRev__SHIFT 0x00000000 -#define RSMU_HCID_GC__RSMU_HCID_HwMinVer__SHIFT 0x00000006 -#define RSMU_HCID_GC__RSMU_HCID_HwMajVer__SHIFT 0x0000000d -#define RSMU_HCID_GC__RSMU_HCID_HwID__SHIFT 0x00000014 - -// RSMU_SIID_GC -#define RSMU_SIID_GC__RSMU_SIID_SwIfRev__SHIFT 0x00000000 -#define RSMU_SIID_GC__RSMU_SIID_SwIfMinVer__SHIFT 0x00000006 -#define RSMU_SIID_GC__RSMU_SIID_SwIfMajVer__SHIFT 0x0000000d -#define RSMU_SIID_GC__RSMU_SIID_SwIfID__SHIFT 0x00000014 - -// RSMU_DBG_MUX_CONTROL_GC -#define RSMU_DBG_MUX_CONTROL_GC__RSMU_DBG_MUX_SELECT__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_ADDR_0_GC -#define RSMU_SW_MMIO_PUB_IND_ADDR_0_GC__RSMU_SW_MMIO_PUB_IND_ADDR_0__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_DATA_0_GC -#define RSMU_SW_MMIO_PUB_IND_DATA_0_GC__RSMU_SW_MMIO_PUB_IND_DATA_0__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_ADDR_1_GC -#define RSMU_SW_MMIO_PUB_IND_ADDR_1_GC__RSMU_SW_MMIO_PUB_IND_ADDR_1__SHIFT 0x00000000 - -// RSMU_SW_MMIO_PUB_IND_DATA_1_GC -#define RSMU_SW_MMIO_PUB_IND_DATA_1_GC__RSMU_SW_MMIO_PUB_IND_DATA_1__SHIFT 0x00000000 - -// RSMU_SOFT_RESETB_GC -#define RSMU_SOFT_RESETB_GC__RSMU_SOFT_RESETB__SHIFT 0x00000000 -#define RSMU_SOFT_RESETB_GC__RSMU_MASTER_SOFT_RESET_FENCE_ENABLE__SHIFT 0x00000002 -#define RSMU_SOFT_RESETB_GC__RSMU_SLAVE_SOFT_RESET_TIMEOUT_ENABLE__SHIFT 0x00000004 - -// RSMU_IH_CREDIT_GC -#define RSMU_IH_CREDIT_GC__RSMU_IH_CREDIT__SHIFT 0x00000000 - -// RSMU_IH_RESET_CNTL_GC -#define RSMU_IH_RESET_CNTL_GC__RSMU_IH_RESET__SHIFT 0x00000000 -#define RSMU_IH_RESET_CNTL_GC__RSMU_IH_HARD_RESET_ENABLE__SHIFT 0x00000001 -#define RSMU_IH_RESET_CNTL_GC__RSMU_IH_SOFT_RESET_ENABLE__SHIFT 0x00000002 - -// RSMU_SEM_RESP_GC -#define RSMU_SEM_RESP_GC__RSMU_SEM_RESP__SHIFT 0x00000000 - -// RSMU_SEM_RESET_CNTL_GC -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_RESET__SHIFT 0x00000000 -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_HARD_RESET_ENABLE__SHIFT 0x00000001 -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_SOFT_RESET_ENABLE__SHIFT 0x00000002 -#define RSMU_SEM_RESET_CNTL_GC__RSMU_SEM_RESET_PROTECT_ENABLE__SHIFT 0x00000003 - -// RSMU_SW_STRAPRX_ADDR_GC -#define RSMU_SW_STRAPRX_ADDR_GC__RSMU_SW_STRAPRX_ADDR__SHIFT 0x00000000 - -// RSMU_SW_STRAPRX_DATA_GC -#define RSMU_SW_STRAPRX_DATA_GC__RSMU_SW_STRAPRX_DATA__SHIFT 0x00000000 - -// RSMU_SW_STRAP_CONTROL_GC -#define RSMU_SW_STRAP_CONTROL_GC__RSMU_SW_PUB_FUSE_RELOAD__SHIFT 0x00000000 -#define RSMU_SW_STRAP_CONTROL_GC__RSMU_SW_ROM_RELOAD__SHIFT 0x00000001 - -// RSMU_TIMEOUT_ERROR_LOG_REG_GC -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_ADDR__SHIFT 0x00000000 -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_APERTUREID__SHIFT 0x00000014 -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_INITIATORID__SHIFT 0x00000016 -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_OP__SHIFT 0x0000001e -#define RSMU_TIMEOUT_ERROR_LOG_REG_GC__RSMU_TIMEOUT_ERROR_OUTSTANDING__SHIFT 0x0000001f - -// RSMU_IP_MASTER_STATUS_GC -#define RSMU_IP_MASTER_STATUS_GC__RSMU_IP_MASTER_REQ_PENDING__SHIFT 0x00000000 -#define RSMU_IP_MASTER_STATUS_GC__RSMU_IP_MASTER_RESP_PENDING__SHIFT 0x00000001 - -// RSMU_GPUREG_SCRATCH_REG_0_GC -#define RSMU_GPUREG_SCRATCH_REG_0_GC__RSMU_GPUREG_SCRATCH_REG_0__SHIFT 0x00000000 - -// RSMU_GPUREG_SCRATCH_REG_1_GC -#define RSMU_GPUREG_SCRATCH_REG_1_GC__RSMU_GPUREG_SCRATCH_REG_1__SHIFT 0x00000000 - -// RSMU_COLD_RESETB_GC -#define RSMU_COLD_RESETB_GC__RSMU_COLD_RESETB__SHIFT 0x00000000 - -// RSMU_HARD_RESETB_GC -#define RSMU_HARD_RESETB_GC__RSMU_HARD_RESETB__SHIFT 0x00000000 -#define RSMU_HARD_RESETB_GC__RSMU_MASTER_HARD_RESET_FENCE_ENABLE__SHIFT 0x00000002 -#define RSMU_HARD_RESETB_GC__RSMU_SLAVE_HARD_RESET_TIMEOUT_ENABLE__SHIFT 0x00000005 - -// RSMU_PUB_FUSE_ADDR_GC -#define RSMU_PUB_FUSE_ADDR_GC__RSMU_PUB_FUSE_START_ADDR__SHIFT 0x00000000 -#define RSMU_PUB_FUSE_ADDR_GC__RSMU_PUB_FUSE_END_ADDR__SHIFT 0x00000010 - -// RSMU_SEC_FUSE_ADDR_GC -#define RSMU_SEC_FUSE_ADDR_GC__RSMU_SEC_FUSE_START_ADDR__SHIFT 0x00000000 -#define RSMU_SEC_FUSE_ADDR_GC__RSMU_SEC_FUSE_END_ADDR__SHIFT 0x00000010 - -// RSMU_MEM_POWER_CTRL_GC -#define RSMU_MEM_POWER_CTRL_GC__RSMU_FUSE_RM_FUSES__SHIFT 0x00000000 -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_RF_BC1__SHIFT 0x00000009 -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_RF_BC2__SHIFT 0x0000000a -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_PDP_BC1__SHIFT 0x0000000b -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_PDP_BC2__SHIFT 0x0000000c -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_HD_BC1__SHIFT 0x0000000d -#define RSMU_MEM_POWER_CTRL_GC__RSMU_MEM_POWER_CTRL_HD_BC2__SHIFT 0x0000000e - -// RSMU_MP0_STRAPRX_ADDR_GC -#define RSMU_MP0_STRAPRX_ADDR_GC__RSMU_MP0_STRAPRX_ADDR__SHIFT 0x00000000 - -// RSMU_MP0_STRAPRX_DATA_GC -#define RSMU_MP0_STRAPRX_DATA_GC__RSMU_MP0_STRAPRX_DATA__SHIFT 0x00000000 - -// RSMU_SMS_FUSE_CFG_GC -#define RSMU_SMS_FUSE_CFG_GC__RSMU_SMS_FUSE_RESETB__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_CFG_GC__RSMU_SMS_FUSE_RUN_BIHR__SHIFT 0x00000001 -#define RSMU_SMS_FUSE_CFG_GC__RSMU_SMS_FUSE_RUN_MBIST__SHIFT 0x00000002 - -// RSMU_SMS_FUSE_ADDR_BASE_GC -#define RSMU_SMS_FUSE_ADDR_BASE_GC__RSMU_SMS_FUSE_ADDR_BASE__SHIFT 0x00000000 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP0__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP1__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP2__SHIFT 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP3__SHIFT 0x00000018 - -// RSMU_STRAP_CONTROL_GC -#define RSMU_STRAP_CONTROL_GC__RSMU_PUB_FUSE_READY__SHIFT 0x00000000 -#define RSMU_STRAP_CONTROL_GC__RSMU_PUB_FUSE_VALID__SHIFT 0x00000001 -#define RSMU_STRAP_CONTROL_GC__RSMU_PUB_FUSE_RELOAD__SHIFT 0x00000002 -#define RSMU_STRAP_CONTROL_GC__RSMU_ROM_READY__SHIFT 0x00000003 -#define RSMU_STRAP_CONTROL_GC__RSMU_ROM_VALID__SHIFT 0x00000004 -#define RSMU_STRAP_CONTROL_GC__RSMU_ROM_RELOAD__SHIFT 0x00000005 -#define RSMU_STRAP_CONTROL_GC__RSMU_PIN_RELOAD__SHIFT 0x00000006 -#define RSMU_STRAP_CONTROL_GC__RSMU_SEC_FUSE_READY__SHIFT 0x00000007 -#define RSMU_STRAP_CONTROL_GC__RSMU_SEC_FUSE_VALID__SHIFT 0x00000008 -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP0__SHIFT 0x00000009 -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP1__SHIFT 0x0000000a -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP2__SHIFT 0x0000000b -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_READY_GRP3__SHIFT 0x0000000c -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP0__SHIFT 0x0000000d -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP1__SHIFT 0x0000000e -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP2__SHIFT 0x0000000f -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_VALID_GRP3__SHIFT 0x00000010 -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP0__SHIFT 0x00000011 -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP1__SHIFT 0x00000012 -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP2__SHIFT 0x00000013 -#define RSMU_STRAP_CONTROL_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP3__SHIFT 0x00000014 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP4__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP5__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP6__SHIFT 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP7__SHIFT 0x00000018 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP8__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP9__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP10__SHIFT 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP11__SHIFT 0x00000018 - -// RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP12__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP13__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP14__SHIFT 0x00000010 -#define RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC__RSMU_SMS_FUSE_ADDR_OFFSET_GRP15__SHIFT 0x00000018 - -// RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP4__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP5__SHIFT 0x00000001 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP6__SHIFT 0x00000002 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP7__SHIFT 0x00000003 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP8__SHIFT 0x00000004 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP9__SHIFT 0x00000005 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP10__SHIFT 0x00000006 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP11__SHIFT 0x00000007 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP12__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP13__SHIFT 0x00000009 -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP14__SHIFT 0x0000000a -#define RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_READY_GRP15__SHIFT 0x0000000b - -// RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP4__SHIFT 0x00000000 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP5__SHIFT 0x00000001 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP6__SHIFT 0x00000002 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP7__SHIFT 0x00000003 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP8__SHIFT 0x00000004 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP9__SHIFT 0x00000005 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP10__SHIFT 0x00000006 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP11__SHIFT 0x00000007 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP12__SHIFT 0x00000008 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP13__SHIFT 0x00000009 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP14__SHIFT 0x0000000a -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_VALID_GRP15__SHIFT 0x0000000b -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP4__SHIFT 0x0000000c -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP5__SHIFT 0x0000000d -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP6__SHIFT 0x0000000e -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP7__SHIFT 0x0000000f -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP8__SHIFT 0x00000010 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP9__SHIFT 0x00000011 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP10__SHIFT 0x00000012 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP11__SHIFT 0x00000013 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP12__SHIFT 0x00000014 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP13__SHIFT 0x00000015 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP14__SHIFT 0x00000016 -#define RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC__RSMU_SMS_FUSE_BIST_FAIL_GRP15__SHIFT 0x00000017 - -// RSMU_DPM_CONTROL_GC -#define RSMU_DPM_CONTROL_GC__RSMU_DPM_ACC_RESET__SHIFT 0x00000000 -#define RSMU_DPM_CONTROL_GC__RSMU_DPM_ACC_START__SHIFT 0x00000001 -#define RSMU_DPM_CONTROL_GC__RSMU_DPM_BUSY_MASK__SHIFT 0x00000002 - -// RSMU_DPM_ACC_GC -#define RSMU_DPM_ACC_GC__RSMU_DPM_ACC__SHIFT 0x00000000 - -// RSMU_DPM_IPCLK_REF_COUNTER_GC -#define RSMU_DPM_IPCLK_REF_COUNTER_GC__RSMU_DPM_IPCLK_REF_COUNTER__SHIFT 0x00000000 - -// RSMU_COUNTER_0_GC -#define RSMU_COUNTER_0_GC__RSMU_COUNTER_0__SHIFT 0x00000000 - -// RSMU_COUNTER_1_GC -#define RSMU_COUNTER_1_GC__RSMU_COUNTER_1__SHIFT 0x00000000 - -// RSMU_HARD_RESETB_DELAY_GC -#define RSMU_HARD_RESETB_DELAY_GC__RSMU_HARD_RESETB_DELAY__SHIFT 0x00000000 - -// RSMU_MMIOPUB_SCRATCH_REG_0_GC -#define RSMU_MMIOPUB_SCRATCH_REG_0_GC__RSMU_MMIOPUB_SCRATCH_REG_0__SHIFT 0x00000000 - -// RSMU_VF_ENABLE_GC -#define RSMU_VF_ENABLE_GC__RSMU_VF_ENABLE__SHIFT 0x00000000 - -// RSMU_MGCG_CONTROL_GC -#define RSMU_MGCG_CONTROL_GC__RSMU_AXI_SLAVE_MGCG_OVERRIDE__SHIFT 0x00000000 -#define RSMU_MGCG_CONTROL_GC__RSMU_AXI_MASTER_MGCG_OVERRIDE__SHIFT 0x00000001 -#define RSMU_MGCG_CONTROL_GC__RSMU_SEC_INTR_MGCG_OVERRIDE__SHIFT 0x00000002 -#define RSMU_MGCG_CONTROL_GC__RSMU_PWRMGT_INTR_MGCG_OVERRIDE__SHIFT 0x00000003 -#define RSMU_MGCG_CONTROL_GC__RSMU_REG_WRAPPER_MGCG_OVERRIDE__SHIFT 0x00000004 -#define RSMU_MGCG_CONTROL_GC__RSMU_STRAP_MASTER_MGCG_OVERRIDE__SHIFT 0x00000005 -#define RSMU_MGCG_CONTROL_GC__RSMU_VWIRE_SRC_MGCG_OVERRIDE__SHIFT 0x00000006 -#define RSMU_MGCG_CONTROL_GC__RSMU_REGIF_MASTER_MGCG_OVERRIDE__SHIFT 0x00000007 -#define RSMU_MGCG_CONTROL_GC__RSMU_PGFSM_MGCG_OVERRIDE__SHIFT 0x00000008 -#define RSMU_MGCG_CONTROL_GC__RSMU_IH_MGCG_OVERRIDE__SHIFT 0x00000009 -#define RSMU_MGCG_CONTROL_GC__RSMU_SEM_MGCG_OVERRIDE__SHIFT 0x0000000a - -// RSMU_RESIDENCY_COUNTER_CNTL_GC -#define RSMU_RESIDENCY_COUNTER_CNTL_GC__RSMU_RESIDENCY_COUNTER_RESET__SHIFT 0x00000000 -#define RSMU_RESIDENCY_COUNTER_CNTL_GC__RSMU_RESIDENCY_COUNTER_START__SHIFT 0x00000001 -#define RSMU_RESIDENCY_COUNTER_CNTL_GC__RSMU_RESIDENCY_COUNTER_SELECT__SHIFT 0x00000002 - -// RSMU_RESIDENCY_COUNTER_GC -#define RSMU_RESIDENCY_COUNTER_GC__RSMU_RESIDENCY_COUNTER__SHIFT 0x00000000 - -// RSMU_RESIDENCY_REF_COUNTER_GC -#define RSMU_RESIDENCY_REF_COUNTER_GC__RSMU_RESIDENCY_REF_COUNTER__SHIFT 0x00000000 - -// RSMU_CUSTOM_HARD_RESETB_GC -#define RSMU_CUSTOM_HARD_RESETB_GC__RSMU_CUSTOM_HARD_RESETB__SHIFT 0x00000000 - -// RSMU_SEC_AXI_MASTER_ENABLE_GC -#define RSMU_SEC_AXI_MASTER_ENABLE_GC__RSMU_SEC_AXI_MASTER_ENABLE__SHIFT 0x00000000 - -// RSMU_SEC_SLAVE_ERROR_COUNTER_GC -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GC__RSMU_SEC_SLAVE_ERROR_COUNTER__SHIFT 0x00000000 -#define RSMU_SEC_SLAVE_ERROR_COUNTER_GC__RSMU_SEC_SLAVE_ERROR_COUNTER_RSMU__SHIFT 0x00000010 - -// RSMU_AXI_MASTER_QOS_CNTL_GC -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_MASTER_QOS_OVRD_MODE__SHIFT 0x00000000 -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_MASTER_QOS_OVRD_VALUE__SHIFT 0x00000001 -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_AWQOS_OVRD_MODE__SHIFT 0x00000005 -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_AWQOS_OVRD_VALUE__SHIFT 0x00000006 -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_ARQOS_OVRD_MODE__SHIFT 0x0000000a -#define RSMU_AXI_MASTER_QOS_CNTL_GC__RSMU_IP_MASTER_ARQOS_OVRD_VALUE__SHIFT 0x0000000b - -// RSMU_MASTER_ERROR_COUNTER_GC -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_SMN_SLVERR_COUNTER__SHIFT 0x00000000 -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_SMN_DECERR_COUNTER__SHIFT 0x00000008 -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_MASTER_SLVERR_COUNTER__SHIFT 0x00000010 -#define RSMU_MASTER_ERROR_COUNTER_GC__RSMU_MASTER_DECERR_COUNTER__SHIFT 0x00000018 - -// RSMU_SLAVE_TIMEOUT_VALUE_GC -#define RSMU_SLAVE_TIMEOUT_VALUE_GC__RSMU_SLAVE_TIMEOUT_VALUE__SHIFT 0x00000000 - -// RSMU_RESET_TIMEOUT_CONTROL_GC -#define RSMU_RESET_TIMEOUT_CONTROL_GC__RSMU_SLAVE_TIMEOUT_ENABLE__SHIFT 0x00000000 -#define RSMU_RESET_TIMEOUT_CONTROL_GC__RSMU_SLAVE_RESET_TIMEOUT_VALUE__SHIFT 0x00000001 - -// RSMU_SLAVE_ERROR_COUNTER_GC -#define RSMU_SLAVE_ERROR_COUNTER_GC__RSMU_SLAVE_ERROR_COUNTER__SHIFT 0x00000000 - -// RSMU_AEB_LOCK_0_GC -#define RSMU_AEB_LOCK_0_GC__RSMU_AEB_LOCK_0__SHIFT 0x00000003 - -// RSMU_AEB_LOCK_1_GC -#define RSMU_AEB_LOCK_1_GC__RSMU_AEB_LOCK_1__SHIFT 0x00000000 - -// RSMU_AEB_OVERRIDE_0_GC -#define RSMU_AEB_OVERRIDE_0_GC__RSMU_AEB_OVERRIDE_0__SHIFT 0x00000003 - -// RSMU_AEB_OVERRIDE_1_GC -#define RSMU_AEB_OVERRIDE_1_GC__RSMU_AEB_OVERRIDE_1__SHIFT 0x00000000 - -// RSMU_SEC_INTR_ENABLE_GC -#define RSMU_SEC_INTR_ENABLE_GC__RSMU_SEC_INTR_ENABLE__SHIFT 0x00000000 - -// RSMU_SEC_INTR_TARGET_ADDR_GC -#define RSMU_SEC_INTR_TARGET_ADDR_GC__RSMU_SEC_INTR_TARGET_ADDR__SHIFT 0x00000000 - -// RSMU_SEC_INTR_CONFIG_GC -#define RSMU_SEC_INTR_CONFIG_GC__RSMU_SEC_INTR_CONFIG_VC__SHIFT 0x00000000 - -// RSMU_SEC_INTR_STATUS_GC -#define RSMU_SEC_INTR_STATUS_GC__RSMU_SEC_INTR_STATUS__SHIFT 0x00000000 - -// RSMU_SEC_INTR_PENDING_GC -#define RSMU_SEC_INTR_PENDING_GC__RSMU_SEC_INTR_PENDING__SHIFT 0x00000000 - -// RSMU_SEC_INTR_TYPE_GC -#define RSMU_SEC_INTR_TYPE_GC__RSMU_SEC_INTR_TYPE__SHIFT 0x00000000 - -// RSMU_SEC_INTR_INTERCEPT_GC -#define RSMU_SEC_INTR_INTERCEPT_GC__RSMU_SEC_INTR_OVERRIDE__SHIFT 0x00000000 -#define RSMU_SEC_INTR_INTERCEPT_GC__RSMU_SEC_INTR_VALUE__SHIFT 0x00000010 - -// RSMU_SEC_INTR_CLEAR_GC -#define RSMU_SEC_INTR_CLEAR_GC__RSMU_SEC_INTR_CLEAR__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_0_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_0_GC__RSMU_SEC_MASTER_TRUST_LEVEL_0__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_1_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_1_GC__RSMU_SEC_MASTER_TRUST_LEVEL_1__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_2_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_2_GC__RSMU_SEC_MASTER_TRUST_LEVEL_2__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_3_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_3_GC__RSMU_SEC_MASTER_TRUST_LEVEL_3__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_5_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_5_GC__RSMU_SEC_MASTER_TRUST_LEVEL_5__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_6_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_6_GC__RSMU_SEC_MASTER_TRUST_LEVEL_6__SHIFT 0x00000000 - -// RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC -#define RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC__RSMU_SEC_MASTER_TRUST_LEVEL_RSMU__SHIFT 0x00000000 - -// RSMU_SEC_ACCESS_CONTROL_RSMU_GC -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE1__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GC__RSMU_SEC_CHECK_ENABLE_RSMU_RANGE2__SHIFT 0x00000001 -#define RSMU_SEC_ACCESS_CONTROL_RSMU_GC__RSMU_SEC_TLVL_MASK_RSMU_RANGE2__SHIFT 0x00000002 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_RW_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC__RSMU_SEC_VF_MASK_SET0_GROUP_DEFAULT__SHIFT \ - 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_RW_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC__RSMU_SEC_VF_MASK_SET1_GROUP_DEFAULT__SHIFT \ - 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_DEFAULT__SHIFT \ - 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_DEFAULT__SHIFT \ - 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_DEFAULT__SHIFT \ - 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_DEFAULT__SHIFT \ - 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_DEFAULT__SHIFT \ - 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_DEFAULT__SHIFT \ - 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_0_GC -#define RSMU_SEC_START_ADDR_GROUP_0_GC__RSMU_SEC_START_ADDR_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_0_GC -#define RSMU_SEC_END_ADDR_GROUP_0_GC__RSMU_SEC_END_ADDR_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_0_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_0_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_0__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC__RSMU_SEC_RW_MASK_SET0_GROUP_0__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC__RSMU_SEC_VF_MASK_SET0_GROUP_0__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_0_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_0_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_0__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_0__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC__RSMU_SEC_RW_MASK_SET1_GROUP_0__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC__RSMU_SEC_VF_MASK_SET1_GROUP_0__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_0__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_0__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_0__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_0__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_0__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_0__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_0__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_0__SHIFT 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_1_GC -#define RSMU_SEC_START_ADDR_GROUP_1_GC__RSMU_SEC_START_ADDR_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_1_GC -#define RSMU_SEC_END_ADDR_GROUP_1_GC__RSMU_SEC_END_ADDR_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_1_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_1_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_1__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC__RSMU_SEC_RW_MASK_SET0_GROUP_1__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC__RSMU_SEC_VF_MASK_SET0_GROUP_1__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_1_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_1_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_1__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_1__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC__RSMU_SEC_RW_MASK_SET1_GROUP_1__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC__RSMU_SEC_VF_MASK_SET1_GROUP_1__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_1__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_1__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_1__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_1__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_1__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_1__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_1__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_1__SHIFT 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_2_GC -#define RSMU_SEC_START_ADDR_GROUP_2_GC__RSMU_SEC_START_ADDR_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_2_GC -#define RSMU_SEC_END_ADDR_GROUP_2_GC__RSMU_SEC_END_ADDR_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_2_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_2_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_2__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC__RSMU_SEC_RW_MASK_SET0_GROUP_2__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC__RSMU_SEC_VF_MASK_SET0_GROUP_2__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_2_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_2_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_2__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_2__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC__RSMU_SEC_RW_MASK_SET1_GROUP_2__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC__RSMU_SEC_VF_MASK_SET1_GROUP_2__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_2__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_2__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_2__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_2__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_2__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_2__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_2__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_2__SHIFT 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_3_GC -#define RSMU_SEC_START_ADDR_GROUP_3_GC__RSMU_SEC_START_ADDR_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_3_GC -#define RSMU_SEC_END_ADDR_GROUP_3_GC__RSMU_SEC_END_ADDR_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_3_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_3_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_3__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC__RSMU_SEC_RW_MASK_SET0_GROUP_3__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC__RSMU_SEC_VF_MASK_SET0_GROUP_3__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_3_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_3_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_3__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_3__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC__RSMU_SEC_RW_MASK_SET1_GROUP_3__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC__RSMU_SEC_VF_MASK_SET1_GROUP_3__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_3__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_3__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_3__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_3__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_3__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_3__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_3__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_3__SHIFT 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_4_GC -#define RSMU_SEC_START_ADDR_GROUP_4_GC__RSMU_SEC_START_ADDR_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_4_GC -#define RSMU_SEC_END_ADDR_GROUP_4_GC__RSMU_SEC_END_ADDR_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_4_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_4_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_4__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC__RSMU_SEC_RW_MASK_SET0_GROUP_4__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC__RSMU_SEC_VF_MASK_SET0_GROUP_4__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_4_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_4_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_4__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_4__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC__RSMU_SEC_RW_MASK_SET1_GROUP_4__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC__RSMU_SEC_VF_MASK_SET1_GROUP_4__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_4__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_4__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_4__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_4__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_4__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_4__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_4__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_4__SHIFT 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_5_GC -#define RSMU_SEC_START_ADDR_GROUP_5_GC__RSMU_SEC_START_ADDR_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_5_GC -#define RSMU_SEC_END_ADDR_GROUP_5_GC__RSMU_SEC_END_ADDR_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_5_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_5_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_5__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC__RSMU_SEC_RW_MASK_SET0_GROUP_5__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC__RSMU_SEC_VF_MASK_SET0_GROUP_5__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_5_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_5_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_5__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_5__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC__RSMU_SEC_RW_MASK_SET1_GROUP_5__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC__RSMU_SEC_VF_MASK_SET1_GROUP_5__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_5__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_5__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_5__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_5__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_5__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_5__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_5__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_5__SHIFT 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_6_GC -#define RSMU_SEC_START_ADDR_GROUP_6_GC__RSMU_SEC_START_ADDR_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_6_GC -#define RSMU_SEC_END_ADDR_GROUP_6_GC__RSMU_SEC_END_ADDR_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_6_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_6_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_6__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC__RSMU_SEC_RW_MASK_SET0_GROUP_6__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC__RSMU_SEC_VF_MASK_SET0_GROUP_6__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_6_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_6_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_6__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_6__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC__RSMU_SEC_RW_MASK_SET1_GROUP_6__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC__RSMU_SEC_VF_MASK_SET1_GROUP_6__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_6__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_6__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_6__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_6__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_6__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_6__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_6__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_6__SHIFT 0x0000000f - -// RSMU_SEC_START_ADDR_GROUP_7_GC -#define RSMU_SEC_START_ADDR_GROUP_7_GC__RSMU_SEC_START_ADDR_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_END_ADDR_GROUP_7_GC -#define RSMU_SEC_END_ADDR_GROUP_7_GC__RSMU_SEC_END_ADDR_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_INITID_MASK_SET0_GROUP_7_GC -#define RSMU_SEC_INITID_MASK_SET0_GROUP_7_GC__RSMU_SEC_INITID_MASK_SET0_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GC -#define RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GC__RSMU_SEC_UNITID_MASK_SET0_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC__RSMU_SEC_TLVL_MASK_SET0_GROUP_7__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC__RSMU_SEC_RW_MASK_SET0_GROUP_7__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC__RSMU_SEC_VF_MASK_SET0_GROUP_7__SHIFT 0x0000000a - -// RSMU_SEC_INITID_MASK_SET1_GROUP_7_GC -#define RSMU_SEC_INITID_MASK_SET1_GROUP_7_GC__RSMU_SEC_INITID_MASK_SET1_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GC -#define RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GC__RSMU_SEC_UNITID_MASK_SET1_GROUP_7__SHIFT 0x00000000 - -// RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC__RSMU_SEC_TLVL_MASK_SET1_GROUP_7__SHIFT 0x00000000 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC__RSMU_SEC_RW_MASK_SET1_GROUP_7__SHIFT 0x00000008 -#define RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC__RSMU_SEC_VF_MASK_SET1_GROUP_7__SHIFT 0x0000000a - -// RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_ENABLE_SET0_GROUP_7__SHIFT 0x00000000 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_EXCLUDE_SET0_GROUP_7__SHIFT 0x00000003 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_ENABLE_SET1_GROUP_7__SHIFT 0x00000006 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_CHECK_EXCLUDE_SET1_GROUP_7__SHIFT 0x00000009 -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_ENABLE_SET0_GROUP_7__SHIFT 0x0000000c -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET0_GROUP_7__SHIFT 0x0000000d -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_ENABLE_SET1_GROUP_7__SHIFT 0x0000000e -#define RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC__RSMU_SEC_VF_CHECK_EXCLUDE_SET1_GROUP_7__SHIFT 0x0000000f - -// RSMU_SEC_SLAVE_ERROR_LOG_REG_GC -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_ADDR__SHIFT 0x00000000 -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_APERTUREID__SHIFT 0x00000014 -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_INITIATORID__SHIFT 0x00000016 -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_OP__SHIFT 0x0000001e -#define RSMU_SEC_SLAVE_ERROR_LOG_REG_GC__RSMU_SEC_SLAVE_ERROR_OUTSTANDING__SHIFT 0x0000001f - -// RSMU_MMIOSEC_SCRATCH_REG_0_GC -#define RSMU_MMIOSEC_SCRATCH_REG_0_GC__RSMU_MMIOSEC_SCRATCH_REG_0__SHIFT 0x00000000 - -// nbif_gpu_HARD_RST_CTRL -#define nbif_gpu_HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x00000000 -#define nbif_gpu_HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x00000001 -#define nbif_gpu_HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x00000002 -#define nbif_gpu_HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x00000003 -#define nbif_gpu_HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x00000004 -#define nbif_gpu_HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x00000005 -#define nbif_gpu_HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x00000006 -#define nbif_gpu_HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x00000007 -#define nbif_gpu_HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x0000001c -#define nbif_gpu_HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x0000001d -#define nbif_gpu_HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x0000001e -#define nbif_gpu_HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x0000001f - -// nbif_gpu_RSMU_SOFT_RST_CTRL -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x00000000 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x00000001 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x00000002 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x00000003 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x00000004 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x00000005 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x00000006 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x00000007 -#define nbif_gpu_RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x0000001c -#define nbif_gpu_RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x0000001d -#define nbif_gpu_RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x0000001e -#define nbif_gpu_RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x0000001f - -// nbif_gpu_SELF_SOFT_RST -#define nbif_gpu_SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x00000000 -#define nbif_gpu_SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x00000001 -#define nbif_gpu_SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x00000002 -#define nbif_gpu_SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x00000003 -#define nbif_gpu_SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x00000004 -#define nbif_gpu_SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x00000005 -#define nbif_gpu_SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x00000006 -#define nbif_gpu_SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x00000007 -#define nbif_gpu_SELF_SOFT_RST__SDP_PORT_RST__SHIFT 0x0000001b -#define nbif_gpu_SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x0000001c -#define nbif_gpu_SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x0000001d -#define nbif_gpu_SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x0000001e -#define nbif_gpu_SELF_SOFT_RST__CORE_RST__SHIFT 0x0000001f - -// nbif_gpu_GFX_DRV_MODE1_RST_CTRL -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT 0x00000000 -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x00000001 -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x00000002 -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT 0x00000003 -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x00000004 -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT 0x00000005 -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x00000006 -#define nbif_gpu_GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT 0x00000007 - -// nbif_gpu_BIF_RST_MISC_CTRL -#define nbif_gpu_BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x00000000 -#define nbif_gpu_BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x00000002 -#define nbif_gpu_BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x00000004 -#define nbif_gpu_BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x00000005 -#define nbif_gpu_BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x00000006 -#define nbif_gpu_BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x00000008 -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x00000009 -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0x0000000a -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0x0000000d -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0x0000000f -#define nbif_gpu_BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x00000011 -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x00000017 -#define nbif_gpu_BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x00000018 - -// nbif_gpu_BIF_RST_MISC_CTRL2 -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT 0x00000000 -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT 0x00000001 -#define nbif_gpu_BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT 0x00000002 -#define nbif_gpu_BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT 0x0000000f -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x00000010 -#define nbif_gpu_BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x00000011 -#define nbif_gpu_BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x00000012 -#define nbif_gpu_BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x0000001f - -// nbif_gpu_BIF_RST_MISC_CTRL3 -#define nbif_gpu_BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x00000000 -#define nbif_gpu_BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x00000004 -#define nbif_gpu_BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x00000006 -#define nbif_gpu_BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x00000007 -#define nbif_gpu_BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0x0000000a -#define nbif_gpu_BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0x0000000d - -// nbif_gpu_BIF_RST_GFXVF_FLR_IDLE -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x00000000 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x00000001 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x00000002 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x00000003 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x00000004 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x00000005 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x00000006 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x00000007 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x00000008 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x00000009 -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0x0000000a -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0x0000000b -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0x0000000c -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0x0000000d -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0x0000000e -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0x0000000f -#define nbif_gpu_BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x0000001f - -// nbif_gpu_DEV0_PF0_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x00000005 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x00000006 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x00000007 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x00000008 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x00000009 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0x0000000a -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0x0000000b -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0x0000000c -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0x0000000d -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0x0000000e -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0x0000000f -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x00000010 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_DEV0_PF1_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_DEV0_PF2_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_DEV0_PF3_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_DEV0_PF4_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_DEV0_PF5_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_DEV0_PF6_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_DEV0_PF7_FLR_RST_CTRL -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x00000011 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x00000012 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x00000017 -#define nbif_gpu_DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x00000019 - -// nbif_gpu_BIF_INST_RESET_INTR_STS -#define nbif_gpu_BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x00000000 -#define nbif_gpu_BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x00000001 -#define nbif_gpu_BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x00000002 -#define nbif_gpu_BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x00000003 -#define nbif_gpu_BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x00000004 - -// nbif_gpu_BIF_PF_FLR_INTR_STS -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x00000007 - -// nbif_gpu_BIF_D3HOTD0_INTR_STS -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x00000000 -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x00000001 -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x00000002 -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x00000003 -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x00000004 -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x00000005 -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x00000006 -#define nbif_gpu_BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x00000007 - -// nbif_gpu_BIF_POWER_INTR_STS -#define nbif_gpu_BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x00000000 -#define nbif_gpu_BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x00000010 - -// nbif_gpu_BIF_PF_DSTATE_INTR_STS -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x00000007 - -// nbif_gpu_BIF_PF0_VF_FLR_INTR_STS -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x00000007 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x00000008 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x00000009 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0x0000000a -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0x0000000b -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0x0000000c -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0x0000000d -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0x0000000e -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0x0000000f -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x0000001f - -// nbif_gpu_BIF_INST_RESET_INTR_MASK -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x00000000 -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x00000001 -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x00000002 -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x00000003 -#define nbif_gpu_BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x00000004 - -// nbif_gpu_BIF_PF_FLR_INTR_MASK -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x00000007 - -// nbif_gpu_BIF_D3HOTD0_INTR_MASK -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x00000000 -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x00000001 -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x00000002 -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x00000003 -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x00000004 -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x00000005 -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x00000006 -#define nbif_gpu_BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x00000007 - -// nbif_gpu_BIF_POWER_INTR_MASK -#define nbif_gpu_BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x00000000 -#define nbif_gpu_BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x00000010 - -// nbif_gpu_BIF_PF_DSTATE_INTR_MASK -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x00000007 - -// nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x00000007 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x00000008 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x00000009 -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0x0000000a -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0x0000000b -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0x0000000c -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0x0000000d -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0x0000000e -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0x0000000f -#define nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x0000001f - -// nbif_gpu_BIF_PF_FLR_RST -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x00000007 - -// nbif_gpu_BIF_PF_FLR_PROTECT -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT__SHIFT 0x00000007 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE__SHIFT 0x00000010 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE__SHIFT 0x00000011 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE__SHIFT 0x00000012 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE__SHIFT 0x00000013 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE__SHIFT 0x00000014 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE__SHIFT 0x00000015 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE__SHIFT 0x00000016 -#define nbif_gpu_BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE__SHIFT 0x00000017 - -// nbif_gpu_BIF_PF0_VF_FLR_RST -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x00000000 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x00000001 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x00000002 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x00000003 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x00000004 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x00000005 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x00000006 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x00000007 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x00000008 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x00000009 -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0x0000000a -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0x0000000b -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0x0000000c -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0x0000000d -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0x0000000e -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0x0000000f -#define nbif_gpu_BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x0000001f - -// nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE -#define nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x00000002 -#define nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x00000000 -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x00000001 -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x00000002 -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x00000003 -#define nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x00000004 - -// nbif_gpu_BIF_GFX_VF_FLR_PROTECT -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF0_FLR_PROTECT__SHIFT 0x00000000 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF1_FLR_PROTECT__SHIFT 0x00000001 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF2_FLR_PROTECT__SHIFT 0x00000002 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF3_FLR_PROTECT__SHIFT 0x00000003 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF4_FLR_PROTECT__SHIFT 0x00000004 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF5_FLR_PROTECT__SHIFT 0x00000005 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF6_FLR_PROTECT__SHIFT 0x00000006 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF7_FLR_PROTECT__SHIFT 0x00000007 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF8_FLR_PROTECT__SHIFT 0x00000008 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF9_FLR_PROTECT__SHIFT 0x00000009 -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF10_FLR_PROTECT__SHIFT 0x0000000a -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF11_FLR_PROTECT__SHIFT 0x0000000b -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF12_FLR_PROTECT__SHIFT 0x0000000c -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF13_FLR_PROTECT__SHIFT 0x0000000d -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF14_FLR_PROTECT__SHIFT 0x0000000e -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__VF15_FLR_PROTECT__SHIFT 0x0000000f -#define nbif_gpu_BIF_GFX_VF_FLR_PROTECT__PF0_SOFTPF_FLR_PROTECT__SHIFT 0x0000001f - -// nbif_gpu_BIF_PORT0_DSTATE_VALUE -#define nbif_gpu_BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x00000010 - -// nbif_gpu_MISC_SECURITY_SET -#define nbif_gpu_MISC_SECURITY_SET__SMN_VWR_SECURITY_SEL__SHIFT 0x00000000 -#define nbif_gpu_MISC_SECURITY_SET__SDP_VWR_SECURITY_SEL__SHIFT 0x00000003 -#define nbif_gpu_MISC_SECURITY_SET__BIFSELF_DMA_SECLEVEL__SHIFT 0x00000006 -#define nbif_gpu_MISC_SECURITY_SET__CFG_RSP_DBGMSK__SHIFT 0x00000009 -#define nbif_gpu_MISC_SECURITY_SET__MMIO_RSP_DBGMSK__SHIFT 0x0000000a - -// nbif_gpu_MISC_SCRATCH -#define nbif_gpu_MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x00000000 - -// nbif_gpu_INTR_LINE_POLARITY -#define nbif_gpu_INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x00000000 - -// nbif_gpu_INTR_LINE_ENABLE -#define nbif_gpu_INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x00000000 - -// nbif_gpu_OUTSTANDING_VC_ALLOC -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x00000000 -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x00000002 -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x00000004 -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x00000006 -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x00000008 -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0x0000000a -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0x0000000c -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0x0000000e -#define nbif_gpu_OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x00000010 -#define nbif_gpu_OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x00000018 -#define nbif_gpu_OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x0000001a -#define nbif_gpu_OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x0000001c - -// nbif_gpu_BIFC_MISC_CTRL0 -#define nbif_gpu_BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x00000000 -#define nbif_gpu_BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x00000001 -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x00000008 -#define nbif_gpu_BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x00000009 -#define nbif_gpu_BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0x0000000a -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x00000010 -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x00000011 -#define nbif_gpu_BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x00000018 -#define nbif_gpu_BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x00000019 -#define nbif_gpu_BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x0000001a -#define nbif_gpu_BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x0000001b -#define nbif_gpu_BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x0000001f - -// nbif_gpu_BIFC_MISC_CTRL1 -#define nbif_gpu_BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x00000000 -#define nbif_gpu_BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x00000001 -#define nbif_gpu_BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x00000002 -#define nbif_gpu_BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x00000003 -#define nbif_gpu_BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x00000004 -#define nbif_gpu_BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x00000005 -#define nbif_gpu_BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x00000006 -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x00000007 -#define nbif_gpu_BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x00000008 -#define nbif_gpu_BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0x0000000a -#define nbif_gpu_BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0x0000000c -#define nbif_gpu_BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0x0000000d -#define nbif_gpu_BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0x0000000e -#define nbif_gpu_BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0x0000000f -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x00000010 -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x00000011 -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x00000012 -#define nbif_gpu_BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x00000013 - -// nbif_gpu_BIFC_BME_ERR_LOG -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F1__SHIFT 0x00000001 -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F2__SHIFT 0x00000002 -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F3__SHIFT 0x00000003 -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F4__SHIFT 0x00000004 -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F5__SHIFT 0x00000005 -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F6__SHIFT 0x00000006 -#define nbif_gpu_BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_F7__SHIFT 0x00000007 -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F1__SHIFT 0x00000011 -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F2__SHIFT 0x00000012 -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F3__SHIFT 0x00000013 -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F4__SHIFT 0x00000014 -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F5__SHIFT 0x00000015 -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F6__SHIFT 0x00000016 -#define nbif_gpu_BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_F7__SHIFT 0x00000017 - -// nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x00000001 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x00000002 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x00000003 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x00000004 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x00000005 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x00000006 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x00000007 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x00000010 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x00000011 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x00000012 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x00000013 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x00000014 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x00000015 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x00000016 -#define nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x00000017 - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x00000002 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x00000006 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x00000008 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0x0000000a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0x0000000c -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x00000010 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x00000012 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x00000016 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x00000018 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x0000001a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x0000001c - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x00000000 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x00000002 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x00000006 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x00000008 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0x0000000a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0x0000000c -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x00000010 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x00000012 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x00000016 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x00000018 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x0000001a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x0000001c - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x00000000 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x00000002 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x00000006 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x00000008 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0x0000000a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0x0000000c -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x00000010 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x00000012 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x00000016 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x00000018 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x0000001a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x0000001c - -// nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x00000000 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x00000002 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x00000006 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x00000008 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0x0000000a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0x0000000c -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x00000010 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x00000012 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x00000016 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x00000018 -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x0000001a -#define nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x0000001c - -// nbif_gpu_NBIF_VWIRE_CTRL -#define nbif_gpu_NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x00000000 -#define nbif_gpu_NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x00000004 -#define nbif_gpu_NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x00000008 -#define nbif_gpu_NBIF_VWIRE_CTRL__SMN_VWR_DBGMSK__SHIFT 0x00000009 -#define nbif_gpu_NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x00000010 -#define nbif_gpu_NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x00000014 -#define nbif_gpu_NBIF_VWIRE_CTRL__SDP_VWR_DBGMSK__SHIFT 0x00000019 -#define nbif_gpu_NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x0000001a - -// nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x00000006 - -// nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x00000006 - -// nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x00000006 - -// nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x00000006 - -// nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x00000006 - -// nbif_gpu_NBIF_MGCG_CTRL -#define nbif_gpu_NBIF_MGCG_CTRL__NBIF_MGCG_EN__SHIFT 0x00000000 -#define nbif_gpu_NBIF_MGCG_CTRL__NBIF_MGCG_MODE__SHIFT 0x00000001 -#define nbif_gpu_NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__SHIFT 0x00000002 - -// nbif_gpu_NBIF_DS_CTRL_LCLK -#define nbif_gpu_NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x00000000 -#define nbif_gpu_NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x00000010 - -// nbif_gpu_SMN_MST_CNTL0 -#define nbif_gpu_SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x00000000 -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x00000008 -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x00000009 -#define nbif_gpu_SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0x0000000a -#define nbif_gpu_SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0x0000000b -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x00000010 -#define nbif_gpu_SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x00000014 -#define nbif_gpu_SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x00000018 -#define nbif_gpu_SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x0000001c - -// nbif_gpu_SMN_MST_EP_CNTL1 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x00000000 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x00000001 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x00000002 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x00000003 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x00000004 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x00000005 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x00000006 -#define nbif_gpu_SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x00000007 - -// nbif_gpu_SMN_MST_EP_CNTL2 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x00000000 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x00000001 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x00000002 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x00000003 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x00000004 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x00000005 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x00000006 -#define nbif_gpu_SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x00000007 - -// nbif_gpu_SMN_MST_EP_CNTL3 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x00000000 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x00000001 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x00000002 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x00000003 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x00000004 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x00000005 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x00000006 -#define nbif_gpu_SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x00000007 - -// nbif_gpu_SMN_MST_EP_CNTL4 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x00000000 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x00000001 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x00000002 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x00000003 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x00000004 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x00000005 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x00000006 -#define nbif_gpu_SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x00000007 - -// nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x00000006 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x00000007 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x00000018 - -// nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x00000006 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x00000007 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x00000018 - -// nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x00000006 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x00000007 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x00000018 - -// nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x00000000 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x00000001 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x00000002 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x00000003 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x00000004 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x00000005 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x00000006 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x00000007 -#define nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x00000018 - -// nbif_gpu_BME_DUMMY_CNTL_0 -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x00000002 -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x00000004 -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x00000006 -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x00000008 -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0x0000000a -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0x0000000c -#define nbif_gpu_BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0x0000000e - -// nbif_gpu_BIFC_THT_CNTL -#define nbif_gpu_BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x00000000 -#define nbif_gpu_BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x00000004 -#define nbif_gpu_BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x00000008 - -// nbif_gpu_BIFC_HSTARB_CNTL -#define nbif_gpu_BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x00000000 - -// nbif_gpu_BIFC_GSI_CNTL -#define nbif_gpu_BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x00000000 -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x00000002 -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x00000005 -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x00000006 -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x00000007 -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x00000008 -#define nbif_gpu_BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x00000009 -#define nbif_gpu_BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0x0000000a -#define nbif_gpu_BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0x0000000c - -// nbif_gpu_BIFC_PCIEFUNC_CNTL -#define nbif_gpu_BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x00000000 -#define nbif_gpu_BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x00000010 - -// nbif_gpu_BIFC_SDP_CNTL_0 -#define nbif_gpu_BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x00000000 -#define nbif_gpu_BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x00000006 -#define nbif_gpu_BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x0000000c -#define nbif_gpu_BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x00000012 -#define nbif_gpu_BIFC_SDP_CNTL_0__RCC_GMI_DBGMSK__SHIFT 0x00000018 -#define nbif_gpu_BIFC_SDP_CNTL_0__BIH_GMI_DBGMSK__SHIFT 0x00000019 - -// nbif_gpu_BIFC_PERF_CNTL_0 -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x00000000 -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x00000001 -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x00000008 -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x00000009 -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x00000010 -#define nbif_gpu_BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x00000018 - -// nbif_gpu_BIFC_PERF_CNTL_1 -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x00000000 -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x00000001 -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x00000008 -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x00000009 -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x00000010 -#define nbif_gpu_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x00000018 - -// nbif_gpu_BIFC_PERF_CNT_MMIO_RD -#define nbif_gpu_BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x00000000 - -// nbif_gpu_BIFC_PERF_CNT_MMIO_WR -#define nbif_gpu_BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x00000000 - -// nbif_gpu_BIFC_PERF_CNT_DMA_RD -#define nbif_gpu_BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x00000000 - -// nbif_gpu_BIFC_PERF_CNT_DMA_WR -#define nbif_gpu_BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x00000000 - -// nbif_gpu_NBIF_REGIF_ERRSET_CTRL -#define nbif_gpu_NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x00000000 - -// nbif_gpu_BIF_RAS_LEAF0_CTRL -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_BIF_RAS_LEAF1_CTRL -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_BIF_RAS_LEAF2_CTRL -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_BIF_RAS_MISC_CTRL -#define nbif_gpu_BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x00000000 - -// nbif_gpu_SUM_INDEX -#define nbif_gpu_SUM_INDEX__SUM_INDEX__SHIFT 0x00000000 - -// nbif_gpu_SUM_DATA -#define nbif_gpu_SUM_DATA__SUM_DATA__SHIFT 0x00000000 - -// nbif_gpu_SBIOS_SCRATCH_0 -#define nbif_gpu_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x00000000 - -// nbif_gpu_SBIOS_SCRATCH_1 -#define nbif_gpu_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x00000000 - -// nbif_gpu_SBIOS_SCRATCH_2 -#define nbif_gpu_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x00000000 - -// nbif_gpu_SBIOS_SCRATCH_3 -#define nbif_gpu_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x00000000 - -// nbif_gpu_BIF_RLC_INTR_CNTL -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x00000000 -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x00000001 -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x00000002 -#define nbif_gpu_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x00000003 - -// nbif_gpu_BIF_VCE_INTR_CNTL -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x00000000 -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x00000001 -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x00000002 -#define nbif_gpu_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x00000003 - -// nbif_gpu_BIF_UVD_INTR_CNTL -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x00000000 -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x00000001 -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x00000002 -#define nbif_gpu_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x00000003 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR0 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR1 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR2 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR3 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR4 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR5 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR6 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ADDR7 -#define nbif_gpu_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7 -#define nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_CNTL -#define nbif_gpu_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL -#define nbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_ONE_CPL -#define nbif_gpu_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x00000000 - -// nbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL -#define nbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x00000000 - -// nbif_gpu_MM_INDEX -#define nbif_gpu_MM_INDEX__MM_OFFSET__SHIFT 0x00000000 -#define nbif_gpu_MM_INDEX__MM_APER__SHIFT 0x0000001f - -// nbif_gpu_MM_INDEX_HI -#define nbif_gpu_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x00000000 - -// nbif_gpu_MM_DATA -#define nbif_gpu_MM_DATA__MM_DATA__SHIFT 0x00000000 - -// nbif_gpu_SYSHUB_INDEX_OVLP -#define nbif_gpu_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x00000000 - -// nbif_gpu_SYSHUB_DATA_OVLP -#define nbif_gpu_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIE_INDEX -#define nbif_gpu_PCIE_INDEX__PCIE_INDEX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DATA -#define nbif_gpu_PCIE_DATA__PCIE_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIE_INDEX2 -#define nbif_gpu_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DATA2 -#define nbif_gpu_PCIE_DATA2__PCIE_DATA2__SHIFT 0x00000000 - -// nbif_gpu_CC_BIF_BX_STRAP0 -#define nbif_gpu_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x00000019 - -// nbif_gpu_CC_BIF_BX_PINSTRAP0 - -// nbif_gpu_CC_BIF_BX_FUSESTRAP0 -#define nbif_gpu_CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x00000001 - -// nbif_gpu_BIF_MM_INDACCESS_CNTL -#define nbif_gpu_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x00000000 -#define nbif_gpu_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x00000001 - -// nbif_gpu_BUS_CNTL -#define nbif_gpu_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x00000003 -#define nbif_gpu_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x00000004 -#define nbif_gpu_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x00000005 -#define nbif_gpu_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x00000006 -#define nbif_gpu_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x00000007 -#define nbif_gpu_BUS_CNTL__SET_AZ_TC__SHIFT 0x0000000a -#define nbif_gpu_BUS_CNTL__SET_MC_TC__SHIFT 0x0000000d -#define nbif_gpu_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x00000010 -#define nbif_gpu_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x00000011 -#define nbif_gpu_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x00000012 -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x00000013 -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x00000014 -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x00000015 -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x00000016 -#define nbif_gpu_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x00000017 -#define nbif_gpu_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x00000018 - -// nbif_gpu_BIF_SCRATCH0 -#define nbif_gpu_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x00000000 - -// nbif_gpu_BIF_SCRATCH1 -#define nbif_gpu_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x00000000 - -// nbif_gpu_BX_RESET_EN -#define nbif_gpu_BX_RESET_EN__COR_RESET_EN__SHIFT 0x00000000 -#define nbif_gpu_BX_RESET_EN__REG_RESET_EN__SHIFT 0x00000001 -#define nbif_gpu_BX_RESET_EN__STY_RESET_EN__SHIFT 0x00000002 -#define nbif_gpu_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x00000008 -#define nbif_gpu_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x00000010 - -// nbif_gpu_MM_CFGREGS_CNTL -#define nbif_gpu_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x00000000 -#define nbif_gpu_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x00000006 -#define nbif_gpu_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x0000001f - -// nbif_gpu_HW_DEBUG -#define nbif_gpu_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define nbif_gpu_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define nbif_gpu_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define nbif_gpu_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define nbif_gpu_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define nbif_gpu_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define nbif_gpu_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define nbif_gpu_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define nbif_gpu_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define nbif_gpu_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define nbif_gpu_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define nbif_gpu_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define nbif_gpu_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define nbif_gpu_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define nbif_gpu_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define nbif_gpu_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f -#define nbif_gpu_HW_DEBUG__HW_16_DEBUG__SHIFT 0x00000010 -#define nbif_gpu_HW_DEBUG__HW_17_DEBUG__SHIFT 0x00000011 -#define nbif_gpu_HW_DEBUG__HW_18_DEBUG__SHIFT 0x00000012 -#define nbif_gpu_HW_DEBUG__HW_19_DEBUG__SHIFT 0x00000013 -#define nbif_gpu_HW_DEBUG__HW_20_DEBUG__SHIFT 0x00000014 -#define nbif_gpu_HW_DEBUG__HW_21_DEBUG__SHIFT 0x00000015 -#define nbif_gpu_HW_DEBUG__HW_22_DEBUG__SHIFT 0x00000016 -#define nbif_gpu_HW_DEBUG__HW_23_DEBUG__SHIFT 0x00000017 -#define nbif_gpu_HW_DEBUG__HW_24_DEBUG__SHIFT 0x00000018 -#define nbif_gpu_HW_DEBUG__HW_25_DEBUG__SHIFT 0x00000019 -#define nbif_gpu_HW_DEBUG__HW_26_DEBUG__SHIFT 0x0000001a -#define nbif_gpu_HW_DEBUG__HW_27_DEBUG__SHIFT 0x0000001b -#define nbif_gpu_HW_DEBUG__HW_28_DEBUG__SHIFT 0x0000001c -#define nbif_gpu_HW_DEBUG__HW_29_DEBUG__SHIFT 0x0000001d -#define nbif_gpu_HW_DEBUG__HW_30_DEBUG__SHIFT 0x0000001e -#define nbif_gpu_HW_DEBUG__HW_31_DEBUG__SHIFT 0x0000001f - -// nbif_gpu_BX_RESET_CNTL -#define nbif_gpu_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x00000000 - -// nbif_gpu_INTERRUPT_CNTL -#define nbif_gpu_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x00000000 -#define nbif_gpu_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x00000001 -#define nbif_gpu_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x00000003 -#define nbif_gpu_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x00000004 -#define nbif_gpu_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x00000008 -#define nbif_gpu_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0x0000000f - -// nbif_gpu_INTERRUPT_CNTL2 -#define nbif_gpu_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x00000000 - -// nbif_gpu_CLKREQB_PAD_CNTL -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x00000000 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x00000001 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x00000002 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x00000003 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x00000005 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x00000006 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x00000007 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x00000008 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x00000009 -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0x0000000a -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0x0000000b -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0x0000000c -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0x0000000d -#define nbif_gpu_CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x00000018 - -// nbif_gpu_CLKREQB_PERF_COUNTER -#define nbif_gpu_CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x00000000 - -// nbif_gpu_BIF_CLK_CTRL -#define nbif_gpu_BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x00000000 -#define nbif_gpu_BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x00000001 - -// nbif_gpu_BIF_FEATURES_CONTROL_MISC -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x00000000 -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x00000001 -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x00000002 -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x00000003 -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x00000009 -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x0000000a -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x0000000b -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0x0000000c -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0x0000000d -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0x0000000e -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0x0000000f -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x00000011 -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x00000012 -#define nbif_gpu_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT \ - 0x00000018 - -// nbif_gpu_BIF_DOORBELL_CNTL -#define nbif_gpu_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x00000000 -#define nbif_gpu_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x00000001 -#define nbif_gpu_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x00000002 -#define nbif_gpu_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x00000003 -#define nbif_gpu_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x00000004 -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x00000018 -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x00000019 -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x0000001a -#define nbif_gpu_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x0000001b - -// nbif_gpu_BIF_DOORBELL_INT_CNTL -#define nbif_gpu_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x00000000 -#define nbif_gpu_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x00000010 - -// nbif_gpu_BIF_SLVARB_MODE -#define nbif_gpu_BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x00000000 - -// nbif_gpu_BIF_FB_EN -#define nbif_gpu_BIF_FB_EN__FB_READ_EN__SHIFT 0x00000000 -#define nbif_gpu_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x00000001 - -// nbif_gpu_BIF_BUSY_DELAY_CNTR -#define nbif_gpu_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x00000000 - -// nbif_gpu_BIF_PERFMON_CNTL -#define nbif_gpu_BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x00000000 -#define nbif_gpu_BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x00000001 -#define nbif_gpu_BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x00000002 -#define nbif_gpu_BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000008 -#define nbif_gpu_BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000d - -// nbif_gpu_BIF_PERFCOUNTER0_RESULT -#define nbif_gpu_BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 - -// nbif_gpu_BIF_PERFCOUNTER1_RESULT -#define nbif_gpu_BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 - -// nbif_gpu_BIF_MST_TRANS_PENDING_VF -#define nbif_gpu_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x00000000 - -// nbif_gpu_BIF_SLV_TRANS_PENDING_VF -#define nbif_gpu_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x00000000 - -// nbif_gpu_BACO_CNTL -#define nbif_gpu_BACO_CNTL__BACO_EN__SHIFT 0x00000000 -#define nbif_gpu_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x00000001 -#define nbif_gpu_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x00000002 -#define nbif_gpu_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x00000003 -#define nbif_gpu_BACO_CNTL__BACO_MODE__SHIFT 0x00000008 -#define nbif_gpu_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x00000009 -#define nbif_gpu_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x0000001f - -// nbif_gpu_BIF_BACO_EXIT_TIME0 -#define nbif_gpu_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x00000000 - -// nbif_gpu_BIF_BACO_EXIT_TIMER1 -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x00000000 -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x0000001a -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x0000001b -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x0000001c -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x0000001d -#define nbif_gpu_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x0000001f - -// nbif_gpu_BIF_BACO_EXIT_TIMER2 -#define nbif_gpu_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x00000000 - -// nbif_gpu_BIF_BACO_EXIT_TIMER3 -#define nbif_gpu_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x00000000 - -// nbif_gpu_BIF_BACO_EXIT_TIMER4 -#define nbif_gpu_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x00000000 - -// nbif_gpu_MEM_TYPE_CNTL -#define nbif_gpu_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x00000000 - -// nbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS -#define nbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x00000000 - -// nbif_gpu_BIF_VDDGFX_GFX0_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_GFX0_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_GFX1_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_GFX1_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_GFX2_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_GFX2_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_GFX3_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_GFX3_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_GFX4_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_GFX4_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_GFX5_LOWER -#define nbif_gpu_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_GFX5_UPPER -#define nbif_gpu_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_RSV1_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_RSV1_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_RSV2_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_RSV2_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_RSV3_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_RSV3_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_RSV4_LOWER -#define nbif_gpu_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x0000001e -#define nbif_gpu_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_VDDGFX_RSV4_UPPER -#define nbif_gpu_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_VDDGFX_FB_CMP -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x00000000 -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x00000001 -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x00000002 -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x00000003 -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x00000004 -#define nbif_gpu_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x00000005 - -// nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER -#define nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER -#define nbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x00000002 - -// nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER -#define nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x00000002 -#define nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x0000001f - -// nbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER -#define nbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x00000002 - -// nbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL -#define nbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x00000002 - -// nbif_gpu_REMAP_HDP_REG_FLUSH_CNTL -#define nbif_gpu_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x00000002 - -// nbif_gpu_BIF_RB_CNTL -#define nbif_gpu_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define nbif_gpu_BIF_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define nbif_gpu_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008 -#define nbif_gpu_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009 -#define nbif_gpu_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x00000011 -#define nbif_gpu_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f - -// nbif_gpu_BIF_RB_BASE -#define nbif_gpu_BIF_RB_BASE__ADDR__SHIFT 0x00000000 - -// nbif_gpu_BIF_RB_RPTR -#define nbif_gpu_BIF_RB_RPTR__OFFSET__SHIFT 0x00000002 - -// nbif_gpu_BIF_RB_WPTR -#define nbif_gpu_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x00000000 -#define nbif_gpu_BIF_RB_WPTR__OFFSET__SHIFT 0x00000002 - -// nbif_gpu_BIF_RB_WPTR_ADDR_HI -#define nbif_gpu_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// nbif_gpu_BIF_RB_WPTR_ADDR_LO -#define nbif_gpu_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// nbif_gpu_MAILBOX_INDEX -#define nbif_gpu_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x00000000 - -// nbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION -#define nbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x00000000 - -// nbif_gpu_BIF_GMI_WRR_WEIGHT -#define nbif_gpu_BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x00000000 -#define nbif_gpu_BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x00000008 -#define nbif_gpu_BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x00000010 - -// nbif_gpu_NBIF_STRAP_WRITE_CTRL -#define nbif_gpu_NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x00000000 - -// nbif_gpu_BIF_BME_STATUS -#define nbif_gpu_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x00000000 -#define nbif_gpu_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x00000010 - -// nbif_gpu_BIF_ATOMIC_ERR_LOG -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x00000000 -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x00000001 -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x00000010 -#define nbif_gpu_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x00000011 - -// nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT \ - 0x00000000 - -// nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT \ - 0x00000000 - -// nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x00000000 -#define nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x00000008 - -// nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL -#define nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x00000000 - -// nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL -#define nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x00000000 - -// nbif_gpu_GPU_HDP_FLUSH_REQ -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x00000000 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x00000001 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x00000002 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x00000003 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x00000004 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x00000005 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x00000006 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x00000007 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x00000008 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x00000009 -#define nbif_gpu_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0x0000000a -#define nbif_gpu_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0x0000000b - -// nbif_gpu_GPU_HDP_FLUSH_DONE -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x00000000 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x00000001 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x00000002 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x00000003 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x00000004 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x00000005 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x00000006 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x00000007 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x00000008 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x00000009 -#define nbif_gpu_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0x0000000a -#define nbif_gpu_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0x0000000b - -// nbif_gpu_BIF_TRANS_PENDING -#define nbif_gpu_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x00000000 -#define nbif_gpu_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x00000001 - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 -#define nbif_gpu_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 -#define nbif_gpu_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x00000000 - -// nbif_gpu_MAILBOX_CONTROL -#define nbif_gpu_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x00000000 -#define nbif_gpu_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x00000001 -#define nbif_gpu_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x00000008 -#define nbif_gpu_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x00000009 - -// nbif_gpu_MAILBOX_INT_CNTL -#define nbif_gpu_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x00000000 -#define nbif_gpu_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x00000001 - -// nbif_gpu_BIF_VMHV_MAILBOX -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x00000000 -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x00000001 -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x00000008 -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0x0000000f -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x00000010 -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x00000017 -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x00000018 -#define nbif_gpu_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x00000019 - -// nbif_gpu_VENDOR_ID_epf -#define nbif_gpu_VENDOR_ID_epf__VENDOR_ID__SHIFT 0x00000000 - -// nbif_gpu_DEVICE_ID_epf -#define nbif_gpu_DEVICE_ID_epf__DEVICE_ID__SHIFT 0x00000000 - -// nbif_gpu_COMMAND_epf -#define nbif_gpu_COMMAND_epf__IO_ACCESS_EN__SHIFT 0x00000000 -#define nbif_gpu_COMMAND_epf__MEM_ACCESS_EN__SHIFT 0x00000001 -#define nbif_gpu_COMMAND_epf__BUS_MASTER_EN__SHIFT 0x00000002 -#define nbif_gpu_COMMAND_epf__SPECIAL_CYCLE_EN__SHIFT 0x00000003 -#define nbif_gpu_COMMAND_epf__MEM_WRITE_INVALIDATE_EN__SHIFT 0x00000004 -#define nbif_gpu_COMMAND_epf__PAL_SNOOP_EN__SHIFT 0x00000005 -#define nbif_gpu_COMMAND_epf__PARITY_ERROR_RESPONSE__SHIFT 0x00000006 -#define nbif_gpu_COMMAND_epf__AD_STEPPING__SHIFT 0x00000007 -#define nbif_gpu_COMMAND_epf__SERR_EN__SHIFT 0x00000008 -#define nbif_gpu_COMMAND_epf__FAST_B2B_EN__SHIFT 0x00000009 -#define nbif_gpu_COMMAND_epf__INT_DIS__SHIFT 0x0000000a - -// nbif_gpu_STATUS_epf -#define nbif_gpu_STATUS_epf__INT_STATUS__SHIFT 0x00000003 -#define nbif_gpu_STATUS_epf__CAP_LIST__SHIFT 0x00000004 -#define nbif_gpu_STATUS_epf__PCI_66_EN__SHIFT 0x00000005 -#define nbif_gpu_STATUS_epf__FAST_BACK_CAPABLE__SHIFT 0x00000007 -#define nbif_gpu_STATUS_epf__MASTER_DATA_PARITY_ERROR__SHIFT 0x00000008 -#define nbif_gpu_STATUS_epf__DEVSEL_TIMING__SHIFT 0x00000009 -#define nbif_gpu_STATUS_epf__SIGNAL_TARGET_ABORT__SHIFT 0x0000000b -#define nbif_gpu_STATUS_epf__RECEIVED_TARGET_ABORT__SHIFT 0x0000000c -#define nbif_gpu_STATUS_epf__RECEIVED_MASTER_ABORT__SHIFT 0x0000000d -#define nbif_gpu_STATUS_epf__SIGNALED_SYSTEM_ERROR__SHIFT 0x0000000e -#define nbif_gpu_STATUS_epf__PARITY_ERROR_DETECTED__SHIFT 0x0000000f - -// nbif_gpu_REVISION_ID_epf -#define nbif_gpu_REVISION_ID_epf__MINOR_REV_ID__SHIFT 0x00000000 -#define nbif_gpu_REVISION_ID_epf__MAJOR_REV_ID__SHIFT 0x00000004 - -// nbif_gpu_PROG_INTERFACE_epf -#define nbif_gpu_PROG_INTERFACE_epf__PROG_INTERFACE__SHIFT 0x00000000 - -// nbif_gpu_SUB_CLASS_epf -#define nbif_gpu_SUB_CLASS_epf__SUB_CLASS__SHIFT 0x00000000 - -// nbif_gpu_BASE_CLASS_epf -#define nbif_gpu_BASE_CLASS_epf__BASE_CLASS__SHIFT 0x00000000 - -// nbif_gpu_CACHE_LINE_epf -#define nbif_gpu_CACHE_LINE_epf__CACHE_LINE_SIZE__SHIFT 0x00000000 - -// nbif_gpu_LATENCY_epf -#define nbif_gpu_LATENCY_epf__LATENCY_TIMER__SHIFT 0x00000000 - -// nbif_gpu_HEADER_epf -#define nbif_gpu_HEADER_epf__HEADER_TYPE__SHIFT 0x00000000 -#define nbif_gpu_HEADER_epf__DEVICE_TYPE__SHIFT 0x00000007 - -// nbif_gpu_BIST_epf -#define nbif_gpu_BIST_epf__BIST_COMP__SHIFT 0x00000000 -#define nbif_gpu_BIST_epf__BIST_STRT__SHIFT 0x00000006 -#define nbif_gpu_BIST_epf__BIST_CAP__SHIFT 0x00000007 - -// nbif_gpu_BASE_ADDR_1_epf -#define nbif_gpu_BASE_ADDR_1_epf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_2_epf -#define nbif_gpu_BASE_ADDR_2_epf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_3_epf -#define nbif_gpu_BASE_ADDR_3_epf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_4_epf -#define nbif_gpu_BASE_ADDR_4_epf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_5_epf -#define nbif_gpu_BASE_ADDR_5_epf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_6_epf -#define nbif_gpu_BASE_ADDR_6_epf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_ROM_BASE_ADDR_epf -#define nbif_gpu_ROM_BASE_ADDR_epf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_CAP_PTR_epf -#define nbif_gpu_CAP_PTR_epf__CAP_PTR__SHIFT 0x00000000 - -// nbif_gpu_INTERRUPT_LINE_epf -#define nbif_gpu_INTERRUPT_LINE_epf__INTERRUPT_LINE__SHIFT 0x00000000 - -// nbif_gpu_INTERRUPT_PIN_epf -#define nbif_gpu_INTERRUPT_PIN_epf__INTERRUPT_PIN__SHIFT 0x00000000 - -// nbif_gpu_ADAPTER_ID_epf -#define nbif_gpu_ADAPTER_ID_epf__SUBSYSTEM_VENDOR_ID__SHIFT 0x00000000 -#define nbif_gpu_ADAPTER_ID_epf__SUBSYSTEM_ID__SHIFT 0x00000010 - -// nbif_gpu_MIN_GRANT_epf -#define nbif_gpu_MIN_GRANT_epf__MIN_GNT__SHIFT 0x00000000 - -// nbif_gpu_MAX_LATENCY_epf -#define nbif_gpu_MAX_LATENCY_epf__MAX_LAT__SHIFT 0x00000000 - -// nbif_gpu_VENDOR_CAP_LIST_epf -#define nbif_gpu_VENDOR_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_VENDOR_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000008 -#define nbif_gpu_VENDOR_CAP_LIST_epf__LENGTH__SHIFT 0x00000010 - -// nbif_gpu_ADAPTER_ID_W_epf -#define nbif_gpu_ADAPTER_ID_W_epf__SUBSYSTEM_VENDOR_ID__SHIFT 0x00000000 -#define nbif_gpu_ADAPTER_ID_W_epf__SUBSYSTEM_ID__SHIFT 0x00000010 - -// nbif_gpu_PMI_CAP_LIST_epf -#define nbif_gpu_PMI_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PMI_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_PMI_CAP_epf -#define nbif_gpu_PMI_CAP_epf__VERSION__SHIFT 0x00000000 -#define nbif_gpu_PMI_CAP_epf__PME_CLOCK__SHIFT 0x00000003 -#define nbif_gpu_PMI_CAP_epf__DEV_SPECIFIC_INIT__SHIFT 0x00000005 -#define nbif_gpu_PMI_CAP_epf__AUX_CURRENT__SHIFT 0x00000006 -#define nbif_gpu_PMI_CAP_epf__D1_SUPPORT__SHIFT 0x00000009 -#define nbif_gpu_PMI_CAP_epf__D2_SUPPORT__SHIFT 0x0000000a -#define nbif_gpu_PMI_CAP_epf__PME_SUPPORT__SHIFT 0x0000000b - -// nbif_gpu_PMI_STATUS_CNTL_epf -#define nbif_gpu_PMI_STATUS_CNTL_epf__POWER_STATE__SHIFT 0x00000000 -#define nbif_gpu_PMI_STATUS_CNTL_epf__NO_SOFT_RESET__SHIFT 0x00000003 -#define nbif_gpu_PMI_STATUS_CNTL_epf__PME_EN__SHIFT 0x00000008 -#define nbif_gpu_PMI_STATUS_CNTL_epf__DATA_SELECT__SHIFT 0x00000009 -#define nbif_gpu_PMI_STATUS_CNTL_epf__DATA_SCALE__SHIFT 0x0000000d -#define nbif_gpu_PMI_STATUS_CNTL_epf__PME_STATUS__SHIFT 0x0000000f -#define nbif_gpu_PMI_STATUS_CNTL_epf__B2_B3_SUPPORT__SHIFT 0x00000016 -#define nbif_gpu_PMI_STATUS_CNTL_epf__BUS_PWR_EN__SHIFT 0x00000017 -#define nbif_gpu_PMI_STATUS_CNTL_epf__PMI_DATA__SHIFT 0x00000018 - -// nbif_gpu_PCIE_CAP_LIST_epf -#define nbif_gpu_PCIE_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_PCIE_CAP_epf -#define nbif_gpu_PCIE_CAP_epf__VERSION__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CAP_epf__DEVICE_TYPE__SHIFT 0x00000004 -#define nbif_gpu_PCIE_CAP_epf__SLOT_IMPLEMENTED__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CAP_epf__INT_MESSAGE_NUM__SHIFT 0x00000009 - -// nbif_gpu_DEVICE_CAP_epf -#define nbif_gpu_DEVICE_CAP_epf__MAX_PAYLOAD_SUPPORT__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CAP_epf__PHANTOM_FUNC__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_CAP_epf__EXTENDED_TAG__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CAP_epf__L0S_ACCEPTABLE_LATENCY__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CAP_epf__L1_ACCEPTABLE_LATENCY__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CAP_epf__ROLE_BASED_ERR_REPORTING__SHIFT 0x0000000f -#define nbif_gpu_DEVICE_CAP_epf__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x00000012 -#define nbif_gpu_DEVICE_CAP_epf__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x0000001a -#define nbif_gpu_DEVICE_CAP_epf__FLR_CAPABLE__SHIFT 0x0000001c - -// nbif_gpu_DEVICE_CNTL_epf -#define nbif_gpu_DEVICE_CNTL_epf__CORR_ERR_EN__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CNTL_epf__NON_FATAL_ERR_EN__SHIFT 0x00000001 -#define nbif_gpu_DEVICE_CNTL_epf__FATAL_ERR_EN__SHIFT 0x00000002 -#define nbif_gpu_DEVICE_CNTL_epf__USR_REPORT_EN__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_CNTL_epf__RELAXED_ORD_EN__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CNTL_epf__MAX_PAYLOAD_SIZE__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CNTL_epf__EXTENDED_TAG_EN__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CNTL_epf__PHANTOM_FUNC_EN__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CNTL_epf__AUX_POWER_PM_EN__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CNTL_epf__NO_SNOOP_EN__SHIFT 0x0000000b -#define nbif_gpu_DEVICE_CNTL_epf__MAX_READ_REQUEST_SIZE__SHIFT 0x0000000c -#define nbif_gpu_DEVICE_CNTL_epf__INITIATE_FLR__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_STATUS_epf -#define nbif_gpu_DEVICE_STATUS_epf__CORR_ERR__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_STATUS_epf__NON_FATAL_ERR__SHIFT 0x00000001 -#define nbif_gpu_DEVICE_STATUS_epf__FATAL_ERR__SHIFT 0x00000002 -#define nbif_gpu_DEVICE_STATUS_epf__USR_DETECTED__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_STATUS_epf__AUX_PWR__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_STATUS_epf__TRANSACTIONS_PEND__SHIFT 0x00000005 - -// nbif_gpu_LINK_CAP_epf -#define nbif_gpu_LINK_CAP_epf__LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_CAP_epf__LINK_WIDTH__SHIFT 0x00000004 -#define nbif_gpu_LINK_CAP_epf__PM_SUPPORT__SHIFT 0x0000000a -#define nbif_gpu_LINK_CAP_epf__L0S_EXIT_LATENCY__SHIFT 0x0000000c -#define nbif_gpu_LINK_CAP_epf__L1_EXIT_LATENCY__SHIFT 0x0000000f -#define nbif_gpu_LINK_CAP_epf__CLOCK_POWER_MANAGEMENT__SHIFT 0x00000012 -#define nbif_gpu_LINK_CAP_epf__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x00000013 -#define nbif_gpu_LINK_CAP_epf__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x00000014 -#define nbif_gpu_LINK_CAP_epf__LINK_BW_NOTIFICATION_CAP__SHIFT 0x00000015 -#define nbif_gpu_LINK_CAP_epf__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x00000016 -#define nbif_gpu_LINK_CAP_epf__PORT_NUMBER__SHIFT 0x00000018 - -// nbif_gpu_LINK_CNTL_epf -#define nbif_gpu_LINK_CNTL_epf__PM_CONTROL__SHIFT 0x00000000 -#define nbif_gpu_LINK_CNTL_epf__READ_CPL_BOUNDARY__SHIFT 0x00000003 -#define nbif_gpu_LINK_CNTL_epf__LINK_DIS__SHIFT 0x00000004 -#define nbif_gpu_LINK_CNTL_epf__RETRAIN_LINK__SHIFT 0x00000005 -#define nbif_gpu_LINK_CNTL_epf__COMMON_CLOCK_CFG__SHIFT 0x00000006 -#define nbif_gpu_LINK_CNTL_epf__EXTENDED_SYNC__SHIFT 0x00000007 -#define nbif_gpu_LINK_CNTL_epf__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x00000008 -#define nbif_gpu_LINK_CNTL_epf__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x00000009 -#define nbif_gpu_LINK_CNTL_epf__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0x0000000a -#define nbif_gpu_LINK_CNTL_epf__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0x0000000b - -// nbif_gpu_LINK_STATUS_epf -#define nbif_gpu_LINK_STATUS_epf__CURRENT_LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_STATUS_epf__NEGOTIATED_LINK_WIDTH__SHIFT 0x00000004 -#define nbif_gpu_LINK_STATUS_epf__LINK_TRAINING__SHIFT 0x0000000b -#define nbif_gpu_LINK_STATUS_epf__SLOT_CLOCK_CFG__SHIFT 0x0000000c -#define nbif_gpu_LINK_STATUS_epf__DL_ACTIVE__SHIFT 0x0000000d -#define nbif_gpu_LINK_STATUS_epf__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x0000000e -#define nbif_gpu_LINK_STATUS_epf__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_CAP2_epf -#define nbif_gpu_DEVICE_CAP2_epf__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CAP2_epf__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CAP2_epf__ARI_FORWARDING_SUPPORTED__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CAP2_epf__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CAP2_epf__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x00000007 -#define nbif_gpu_DEVICE_CAP2_epf__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CAP2_epf__CAS128_CMPLT_SUPPORTED__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CAP2_epf__NO_RO_ENABLED_P2P_PASSING__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CAP2_epf__LTR_SUPPORTED__SHIFT 0x0000000b -#define nbif_gpu_DEVICE_CAP2_epf__TPH_CPLR_SUPPORTED__SHIFT 0x0000000c -#define nbif_gpu_DEVICE_CAP2_epf__OBFF_SUPPORTED__SHIFT 0x00000012 -#define nbif_gpu_DEVICE_CAP2_epf__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x00000014 -#define nbif_gpu_DEVICE_CAP2_epf__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x00000015 -#define nbif_gpu_DEVICE_CAP2_epf__MAX_END_END_TLP_PREFIXES__SHIFT 0x00000016 - -// nbif_gpu_DEVICE_CNTL2_epf -#define nbif_gpu_DEVICE_CNTL2_epf__CPL_TIMEOUT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CNTL2_epf__CPL_TIMEOUT_DIS__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CNTL2_epf__ARI_FORWARDING_EN__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CNTL2_epf__ATOMICOP_REQUEST_EN__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CNTL2_epf__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x00000007 -#define nbif_gpu_DEVICE_CNTL2_epf__IDO_REQUEST_ENABLE__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CNTL2_epf__IDO_COMPLETION_ENABLE__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CNTL2_epf__LTR_EN__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CNTL2_epf__OBFF_EN__SHIFT 0x0000000d -#define nbif_gpu_DEVICE_CNTL2_epf__END_END_TLP_PREFIX_BLOCKING__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_STATUS2_epf -#define nbif_gpu_DEVICE_STATUS2_epf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_LINK_CAP2_epf -#define nbif_gpu_LINK_CAP2_epf__SUPPORTED_LINK_SPEED__SHIFT 0x00000001 -#define nbif_gpu_LINK_CAP2_epf__CROSSLINK_SUPPORTED__SHIFT 0x00000008 -#define nbif_gpu_LINK_CAP2_epf__RESERVED__SHIFT 0x00000009 - -// nbif_gpu_LINK_CNTL2_epf -#define nbif_gpu_LINK_CNTL2_epf__TARGET_LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_CNTL2_epf__ENTER_COMPLIANCE__SHIFT 0x00000004 -#define nbif_gpu_LINK_CNTL2_epf__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x00000005 -#define nbif_gpu_LINK_CNTL2_epf__SELECTABLE_DEEMPHASIS__SHIFT 0x00000006 -#define nbif_gpu_LINK_CNTL2_epf__XMIT_MARGIN__SHIFT 0x00000007 -#define nbif_gpu_LINK_CNTL2_epf__ENTER_MOD_COMPLIANCE__SHIFT 0x0000000a -#define nbif_gpu_LINK_CNTL2_epf__COMPLIANCE_SOS__SHIFT 0x0000000b -#define nbif_gpu_LINK_CNTL2_epf__COMPLIANCE_DEEMPHASIS__SHIFT 0x0000000c - -// nbif_gpu_LINK_STATUS2_epf -#define nbif_gpu_LINK_STATUS2_epf__CUR_DEEMPHASIS_LEVEL__SHIFT 0x00000000 -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_COMPLETE__SHIFT 0x00000001 -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x00000002 -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x00000003 -#define nbif_gpu_LINK_STATUS2_epf__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x00000004 -#define nbif_gpu_LINK_STATUS2_epf__LINK_EQUALIZATION_REQUEST__SHIFT 0x00000005 - -// nbif_gpu_SLOT_CAP2_epf -#define nbif_gpu_SLOT_CAP2_epf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_SLOT_CNTL2_epf -#define nbif_gpu_SLOT_CNTL2_epf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_SLOT_STATUS2_epf -#define nbif_gpu_SLOT_STATUS2_epf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_MSI_CAP_LIST_epf -#define nbif_gpu_MSI_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_MSI_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_MSI_MSG_CNTL_epf -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_EN__SHIFT 0x00000000 -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_MULTI_CAP__SHIFT 0x00000001 -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_MULTI_EN__SHIFT 0x00000004 -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_64BIT__SHIFT 0x00000007 -#define nbif_gpu_MSI_MSG_CNTL_epf__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x00000008 - -// nbif_gpu_MSI_MSG_ADDR_LO_epf -#define nbif_gpu_MSI_MSG_ADDR_LO_epf__MSI_MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_MSI_MSG_ADDR_HI_epf -#define nbif_gpu_MSI_MSG_ADDR_HI_epf__MSI_MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_MSI_MSG_DATA_64_epf -#define nbif_gpu_MSI_MSG_DATA_64_epf__MSI_DATA_64__SHIFT 0x00000000 - -// nbif_gpu_MSI_MSG_DATA_epf -#define nbif_gpu_MSI_MSG_DATA_epf__MSI_DATA__SHIFT 0x00000000 - -// nbif_gpu_MSI_MASK_epf -#define nbif_gpu_MSI_MASK_epf__MSI_MASK__SHIFT 0x00000000 - -// nbif_gpu_MSI_PENDING_epf -#define nbif_gpu_MSI_PENDING_epf__MSI_PENDING__SHIFT 0x00000000 - -// nbif_gpu_MSI_MASK_64_epf -#define nbif_gpu_MSI_MASK_64_epf__MSI_MASK_64__SHIFT 0x00000000 - -// nbif_gpu_MSI_PENDING_64_epf -#define nbif_gpu_MSI_PENDING_64_epf__MSI_PENDING_64__SHIFT 0x00000000 - -// nbif_gpu_MSIX_CAP_LIST_epf -#define nbif_gpu_MSIX_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_MSIX_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_MSIX_MSG_CNTL_epf -#define nbif_gpu_MSIX_MSG_CNTL_epf__MSIX_TABLE_SIZE__SHIFT 0x00000000 -#define nbif_gpu_MSIX_MSG_CNTL_epf__MSIX_FUNC_MASK__SHIFT 0x0000000e -#define nbif_gpu_MSIX_MSG_CNTL_epf__MSIX_EN__SHIFT 0x0000000f - -// nbif_gpu_MSIX_TABLE_epf -#define nbif_gpu_MSIX_TABLE_epf__MSIX_TABLE_BIR__SHIFT 0x00000000 -#define nbif_gpu_MSIX_TABLE_epf__MSIX_TABLE_OFFSET__SHIFT 0x00000003 - -// nbif_gpu_MSIX_PBA_epf -#define nbif_gpu_MSIX_PBA_epf__MSIX_PBA_BIR__SHIFT 0x00000000 -#define nbif_gpu_MSIX_PBA_epf__MSIX_PBA_OFFSET__SHIFT 0x00000003 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf__VSEC_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf__VSEC_REV__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf__VSEC_LENGTH__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf__SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf__SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__EXT_VC_COUNT__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__REF_CLK__SHIFT 0x00000008 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0x0000000a - -// nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf__VC_ARB_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf__VC_ARB_TABLE_OFFSET__SHIFT 0x00000018 - -// nbif_gpu_PCIE_PORT_VC_CNTL_epf -#define nbif_gpu_PCIE_PORT_VC_CNTL_epf__LOAD_VC_ARB_TABLE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PORT_VC_CNTL_epf__VC_ARB_SELECT__SHIFT 0x00000001 - -// nbif_gpu_PCIE_PORT_VC_STATUS_epf -#define nbif_gpu_PCIE_PORT_VC_STATUS_epf__VC_ARB_TABLE_STATUS__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__PORT_ARB_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__REJECT_SNOOP_TRANS__SHIFT 0x0000000f -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__MAX_TIME_SLOTS__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf__PORT_ARB_TABLE_OFFSET__SHIFT 0x00000018 - -// nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__TC_VC_MAP_TC0__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__TC_VC_MAP_TC1_7__SHIFT 0x00000001 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__LOAD_PORT_ARB_TABLE__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__PORT_ARB_SELECT__SHIFT 0x00000011 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__VC_ID__SHIFT 0x00000018 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf__VC_ENABLE__SHIFT 0x0000001f - -// nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf__PORT_ARB_TABLE_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf__VC_NEGOTIATION_PENDING__SHIFT 0x00000001 - -// nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__PORT_ARB_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__REJECT_SNOOP_TRANS__SHIFT 0x0000000f -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__MAX_TIME_SLOTS__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf__PORT_ARB_TABLE_OFFSET__SHIFT 0x00000018 - -// nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__TC_VC_MAP_TC0__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__TC_VC_MAP_TC1_7__SHIFT 0x00000001 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__LOAD_PORT_ARB_TABLE__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__PORT_ARB_SELECT__SHIFT 0x00000011 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__VC_ID__SHIFT 0x00000018 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf__VC_ENABLE__SHIFT 0x0000001f - -// nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf__PORT_ARB_TABLE_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf__VC_NEGOTIATION_PENDING__SHIFT 0x00000001 - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf__SERIAL_NUMBER_LO__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf__SERIAL_NUMBER_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__DLP_ERR_STATUS__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__SURPDN_ERR_STATUS__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__PSN_ERR_STATUS__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__FC_ERR_STATUS__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__CPL_TIMEOUT_STATUS__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__CPL_ABORT_ERR_STATUS__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__UNEXP_CPL_STATUS__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__RCV_OVFL_STATUS__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__MAL_TLP_STATUS__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__ECRC_ERR_STATUS__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__UNSUPP_REQ_ERR_STATUS__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__ACS_VIOLATION_STATUS__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__UNCORR_INT_ERR_STATUS__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__MC_BLOCKED_TLP_STATUS__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x00000019 - -// nbif_gpu_PCIE_UNCORR_ERR_MASK_epf -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__DLP_ERR_MASK__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__SURPDN_ERR_MASK__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__PSN_ERR_MASK__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__FC_ERR_MASK__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__CPL_TIMEOUT_MASK__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__CPL_ABORT_ERR_MASK__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__UNEXP_CPL_MASK__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__RCV_OVFL_MASK__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__MAL_TLP_MASK__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__ECRC_ERR_MASK__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__UNSUPP_REQ_ERR_MASK__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__ACS_VIOLATION_MASK__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__UNCORR_INT_ERR_MASK__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__MC_BLOCKED_TLP_MASK__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epf__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x00000019 - -// nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__DLP_ERR_SEVERITY__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__SURPDN_ERR_SEVERITY__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__PSN_ERR_SEVERITY__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__FC_ERR_SEVERITY__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__CPL_TIMEOUT_SEVERITY__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__CPL_ABORT_ERR_SEVERITY__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__UNEXP_CPL_SEVERITY__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__RCV_OVFL_SEVERITY__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__MAL_TLP_SEVERITY__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__ECRC_ERR_SEVERITY__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__ACS_VIOLATION_SEVERITY__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__UNCORR_INT_ERR_SEVERITY__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x00000019 - -// nbif_gpu_PCIE_CORR_ERR_STATUS_epf -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__RCV_ERR_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__BAD_TLP_STATUS__SHIFT 0x00000006 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__BAD_DLLP_STATUS__SHIFT 0x00000007 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0x0000000c -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x0000000d -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__CORR_INT_ERR_STATUS__SHIFT 0x0000000e -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epf__HDR_LOG_OVFL_STATUS__SHIFT 0x0000000f - -// nbif_gpu_PCIE_CORR_ERR_MASK_epf -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__RCV_ERR_MASK__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__BAD_TLP_MASK__SHIFT 0x00000006 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__BAD_DLLP_MASK__SHIFT 0x00000007 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0x0000000c -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0x0000000d -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__CORR_INT_ERR_MASK__SHIFT 0x0000000e -#define nbif_gpu_PCIE_CORR_ERR_MASK_epf__HDR_LOG_OVFL_MASK__SHIFT 0x0000000f - -// nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__FIRST_ERR_PTR__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_GEN_CAP__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_GEN_EN__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_CHECK_CAP__SHIFT 0x00000007 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__ECRC_CHECK_EN__SHIFT 0x00000008 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__MULTI_HDR_RECD_CAP__SHIFT 0x00000009 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__MULTI_HDR_RECD_EN__SHIFT 0x0000000a -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf__TLP_PREFIX_LOG_PRESENT__SHIFT 0x0000000b - -// nbif_gpu_PCIE_HDR_LOG0_epf -#define nbif_gpu_PCIE_HDR_LOG0_epf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG1_epf -#define nbif_gpu_PCIE_HDR_LOG1_epf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG2_epf -#define nbif_gpu_PCIE_HDR_LOG2_epf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG3_epf -#define nbif_gpu_PCIE_HDR_LOG3_epf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_ROOT_ERR_CMD_epf -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epf__CORR_ERR_REP_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epf__NONFATAL_ERR_REP_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epf__FATAL_ERR_REP_EN__SHIFT 0x00000002 - -// nbif_gpu_PCIE_ROOT_ERR_STATUS_epf -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__ERR_CORR_RCVD__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__MULT_ERR_CORR_RCVD__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x00000002 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x00000003 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x00000004 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__FATAL_ERROR_MSG_RCVD__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epf__ADV_ERR_INT_MSG_NUM__SHIFT 0x0000001b - -// nbif_gpu_PCIE_ERR_SRC_ID_epf -#define nbif_gpu_PCIE_ERR_SRC_ID_epf__ERR_CORR_SRC_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ERR_SRC_ID_epf__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x00000010 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_BAR1_CAP_epf -#define nbif_gpu_PCIE_BAR1_CAP_epf__BAR_SIZE_SUPPORTED__SHIFT 0x00000004 - -// nbif_gpu_PCIE_BAR1_CNTL_epf -#define nbif_gpu_PCIE_BAR1_CNTL_epf__BAR_INDEX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_BAR1_CNTL_epf__BAR_TOTAL_NUM__SHIFT 0x00000005 -#define nbif_gpu_PCIE_BAR1_CNTL_epf__BAR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_BAR2_CAP_epf -#define nbif_gpu_PCIE_BAR2_CAP_epf__BAR_SIZE_SUPPORTED__SHIFT 0x00000004 - -// nbif_gpu_PCIE_BAR2_CNTL_epf -#define nbif_gpu_PCIE_BAR2_CNTL_epf__BAR_INDEX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_BAR2_CNTL_epf__BAR_TOTAL_NUM__SHIFT 0x00000005 -#define nbif_gpu_PCIE_BAR2_CNTL_epf__BAR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_BAR3_CAP_epf -#define nbif_gpu_PCIE_BAR3_CAP_epf__BAR_SIZE_SUPPORTED__SHIFT 0x00000004 - -// nbif_gpu_PCIE_BAR3_CNTL_epf -#define nbif_gpu_PCIE_BAR3_CNTL_epf__BAR_INDEX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_BAR3_CNTL_epf__BAR_TOTAL_NUM__SHIFT 0x00000005 -#define nbif_gpu_PCIE_BAR3_CNTL_epf__BAR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_BAR4_CAP_epf -#define nbif_gpu_PCIE_BAR4_CAP_epf__BAR_SIZE_SUPPORTED__SHIFT 0x00000004 - -// nbif_gpu_PCIE_BAR4_CNTL_epf -#define nbif_gpu_PCIE_BAR4_CNTL_epf__BAR_INDEX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_BAR4_CNTL_epf__BAR_TOTAL_NUM__SHIFT 0x00000005 -#define nbif_gpu_PCIE_BAR4_CNTL_epf__BAR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_BAR5_CAP_epf -#define nbif_gpu_PCIE_BAR5_CAP_epf__BAR_SIZE_SUPPORTED__SHIFT 0x00000004 - -// nbif_gpu_PCIE_BAR5_CNTL_epf -#define nbif_gpu_PCIE_BAR5_CNTL_epf__BAR_INDEX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_BAR5_CNTL_epf__BAR_TOTAL_NUM__SHIFT 0x00000005 -#define nbif_gpu_PCIE_BAR5_CNTL_epf__BAR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_BAR6_CAP_epf -#define nbif_gpu_PCIE_BAR6_CAP_epf__BAR_SIZE_SUPPORTED__SHIFT 0x00000004 - -// nbif_gpu_PCIE_BAR6_CNTL_epf -#define nbif_gpu_PCIE_BAR6_CNTL_epf__BAR_INDEX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_BAR6_CNTL_epf__BAR_TOTAL_NUM__SHIFT 0x00000005 -#define nbif_gpu_PCIE_BAR6_CNTL_epf__BAR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf__DATA_SELECT__SHIFT 0x00000000 - -// nbif_gpu_PCIE_PWR_BUDGET_DATA_epf -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__BASE_POWER__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__DATA_SCALE__SHIFT 0x00000008 -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__PM_SUB_STATE__SHIFT 0x0000000a -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__PM_STATE__SHIFT 0x0000000d -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__TYPE__SHIFT 0x0000000f -#define nbif_gpu_PCIE_PWR_BUDGET_DATA_epf__POWER_RAIL__SHIFT 0x00000012 - -// nbif_gpu_PCIE_PWR_BUDGET_CAP_epf -#define nbif_gpu_PCIE_PWR_BUDGET_CAP_epf__SYSTEM_ALLOCATED__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_DPA_CAP_epf -#define nbif_gpu_PCIE_DPA_CAP_epf__SUBSTATE_MAX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_DPA_CAP_epf__TRANS_LAT_UNIT__SHIFT 0x00000008 -#define nbif_gpu_PCIE_DPA_CAP_epf__PWR_ALLOC_SCALE__SHIFT 0x0000000c -#define nbif_gpu_PCIE_DPA_CAP_epf__TRANS_LAT_VAL_0__SHIFT 0x00000010 -#define nbif_gpu_PCIE_DPA_CAP_epf__TRANS_LAT_VAL_1__SHIFT 0x00000018 - -// nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf -#define nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf__TRANS_LAT_INDICATOR_BITS__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_STATUS_epf -#define nbif_gpu_PCIE_DPA_STATUS_epf__SUBSTATE_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_DPA_STATUS_epf__SUBSTATE_CNTL_ENABLED__SHIFT 0x00000008 - -// nbif_gpu_PCIE_DPA_CNTL_epf -#define nbif_gpu_PCIE_DPA_CNTL_epf__SUBSTATE_CNTL__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf -#define nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_LINK_CNTL3_epf -#define nbif_gpu_PCIE_LINK_CNTL3_epf__PERFORM_EQUALIZATION__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LINK_CNTL3_epf__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_LINK_CNTL3_epf__RESERVED__SHIFT 0x00000002 - -// nbif_gpu_PCIE_LANE_ERROR_STATUS_epf -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_epf__LANE_ERROR_STATUS_BITS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_epf__RESERVED__SHIFT 0x00000010 - -// nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_ACS_CAP_epf -#define nbif_gpu_PCIE_ACS_CAP_epf__SOURCE_VALIDATION__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ACS_CAP_epf__TRANSLATION_BLOCKING__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ACS_CAP_epf__P2P_REQUEST_REDIRECT__SHIFT 0x00000002 -#define nbif_gpu_PCIE_ACS_CAP_epf__P2P_COMPLETION_REDIRECT__SHIFT 0x00000003 -#define nbif_gpu_PCIE_ACS_CAP_epf__UPSTREAM_FORWARDING__SHIFT 0x00000004 -#define nbif_gpu_PCIE_ACS_CAP_epf__P2P_EGRESS_CONTROL__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ACS_CAP_epf__DIRECT_TRANSLATED_P2P__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ACS_CAP_epf__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_ACS_CNTL_epf -#define nbif_gpu_PCIE_ACS_CNTL_epf__SOURCE_VALIDATION_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ACS_CNTL_epf__TRANSLATION_BLOCKING_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ACS_CNTL_epf__P2P_REQUEST_REDIRECT_EN__SHIFT 0x00000002 -#define nbif_gpu_PCIE_ACS_CNTL_epf__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x00000003 -#define nbif_gpu_PCIE_ACS_CNTL_epf__UPSTREAM_FORWARDING_EN__SHIFT 0x00000004 -#define nbif_gpu_PCIE_ACS_CNTL_epf__P2P_EGRESS_CONTROL_EN__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ACS_CNTL_epf__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x00000006 - -// nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_ATS_CAP_epf -#define nbif_gpu_PCIE_ATS_CAP_epf__INVALIDATE_Q_DEPTH__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ATS_CAP_epf__PAGE_ALIGNED_REQUEST__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ATS_CAP_epf__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x00000006 - -// nbif_gpu_PCIE_ATS_CNTL_epf -#define nbif_gpu_PCIE_ATS_CNTL_epf__STU__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ATS_CNTL_epf__ATC_ENABLE__SHIFT 0x0000000f - -// nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_PAGE_REQ_CNTL_epf -#define nbif_gpu_PCIE_PAGE_REQ_CNTL_epf__PRI_ENABLE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PAGE_REQ_CNTL_epf__PRI_RESET__SHIFT 0x00000001 - -// nbif_gpu_PCIE_PAGE_REQ_STATUS_epf -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__RESPONSE_FAILURE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x00000001 -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__STOPPED__SHIFT 0x00000008 -#define nbif_gpu_PCIE_PAGE_REQ_STATUS_epf__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf -#define nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x00000000 - -// nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf -#define nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_PASID_CAP_epf -#define nbif_gpu_PCIE_PASID_CAP_epf__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x00000001 -#define nbif_gpu_PCIE_PASID_CAP_epf__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x00000002 -#define nbif_gpu_PCIE_PASID_CAP_epf__MAX_PASID_WIDTH__SHIFT 0x00000008 - -// nbif_gpu_PCIE_PASID_CNTL_epf -#define nbif_gpu_PCIE_PASID_CNTL_epf__PASID_ENABLE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PASID_CNTL_epf__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x00000001 -#define nbif_gpu_PCIE_PASID_CNTL_epf__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x00000002 - -// nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_TPH_REQR_CAP_epf -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x00000000 -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x00000001 -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x00000002 -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x00000008 -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x00000009 -#define nbif_gpu_PCIE_TPH_REQR_CAP_epf__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x00000010 - -// nbif_gpu_PCIE_TPH_REQR_CNTL_epf -#define nbif_gpu_PCIE_TPH_REQR_CNTL_epf__TPH_REQR_ST_MODE_SEL__SHIFT 0x00000000 -#define nbif_gpu_PCIE_TPH_REQR_CNTL_epf__TPH_REQR_EN__SHIFT 0x00000008 - -// nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_MC_CAP_epf -#define nbif_gpu_PCIE_MC_CAP_epf__MC_MAX_GROUP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_MC_CAP_epf__MC_WIN_SIZE_REQ__SHIFT 0x00000008 -#define nbif_gpu_PCIE_MC_CAP_epf__MC_ECRC_REGEN_SUPP__SHIFT 0x0000000f - -// nbif_gpu_PCIE_MC_CNTL_epf -#define nbif_gpu_PCIE_MC_CNTL_epf__MC_NUM_GROUP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_MC_CNTL_epf__MC_ENABLE__SHIFT 0x0000000f - -// nbif_gpu_PCIE_MC_ADDR0_epf -#define nbif_gpu_PCIE_MC_ADDR0_epf__MC_INDEX_POS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_MC_ADDR0_epf__MC_BASE_ADDR_0__SHIFT 0x0000000c - -// nbif_gpu_PCIE_MC_ADDR1_epf -#define nbif_gpu_PCIE_MC_ADDR1_epf__MC_BASE_ADDR_1__SHIFT 0x00000000 - -// nbif_gpu_PCIE_MC_RCV0_epf -#define nbif_gpu_PCIE_MC_RCV0_epf__MC_RECEIVE_0__SHIFT 0x00000000 - -// nbif_gpu_PCIE_MC_RCV1_epf -#define nbif_gpu_PCIE_MC_RCV1_epf__MC_RECEIVE_1__SHIFT 0x00000000 - -// nbif_gpu_PCIE_MC_BLOCK_ALL0_epf -#define nbif_gpu_PCIE_MC_BLOCK_ALL0_epf__MC_BLOCK_ALL_0__SHIFT 0x00000000 - -// nbif_gpu_PCIE_MC_BLOCK_ALL1_epf -#define nbif_gpu_PCIE_MC_BLOCK_ALL1_epf__MC_BLOCK_ALL_1__SHIFT 0x00000000 - -// nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf -#define nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x00000000 - -// nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf -#define nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x00000000 - -// nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_LTR_CAP_epf -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_S_LATENCY_SCALE__SHIFT 0x0000000a -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x00000010 -#define nbif_gpu_PCIE_LTR_CAP_epf__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x0000001a - -// nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_ARI_CAP_epf -#define nbif_gpu_PCIE_ARI_CAP_epf__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ARI_CAP_epf__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ARI_CAP_epf__ARI_NEXT_FUNC_NUM__SHIFT 0x00000008 - -// nbif_gpu_PCIE_ARI_CNTL_epf -#define nbif_gpu_PCIE_ARI_CNTL_epf__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ARI_CNTL_epf__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ARI_CNTL_epf__ARI_FUNCTION_GROUP__SHIFT 0x00000004 - -// nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf -#define nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_SRIOV_CAP_epf -#define nbif_gpu_PCIE_SRIOV_CAP_epf__SRIOV_VF_MIGRATION_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_SRIOV_CAP_epf__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x00000001 -#define nbif_gpu_PCIE_SRIOV_CAP_epf__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x00000015 - -// nbif_gpu_PCIE_SRIOV_CONTROL_epf -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_ENABLE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x00000001 -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x00000002 -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_VF_MSE__SHIFT 0x00000003 -#define nbif_gpu_PCIE_SRIOV_CONTROL_epf__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x00000004 - -// nbif_gpu_PCIE_SRIOV_STATUS_epf -#define nbif_gpu_PCIE_SRIOV_STATUS_epf__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf -#define nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf__SRIOV_INITIAL_VFS__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf -#define nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf__SRIOV_TOTAL_VFS__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_NUM_VFS_epf -#define nbif_gpu_PCIE_SRIOV_NUM_VFS_epf__SRIOV_NUM_VFS__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf -#define nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf__SRIOV_FUNC_DEP_LINK__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf -#define nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf__SRIOV_FIRST_VF_OFFSET__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf -#define nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf__SRIOV_VF_STRIDE__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf -#define nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf__SRIOV_VF_DEVICE_ID__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf -#define nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf -#define nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf__VF_BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf__VF_BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf__VF_BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf__VF_BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf__VF_BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf -#define nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf__VF_BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf -#define nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT \ - 0x00000000 -#define nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT \ - 0x00000003 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf__VSEC_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf__VSEC_REV__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf__VSEC_LENGTH__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf__VF_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf__VF_NUM__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_CMD_COMPLETE_INTR_EN__SHIFT \ - 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT \ - 0x00000001 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_HANG_NEED_FLR_INTR_EN__SHIFT \ - 0x00000002 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT \ - 0x00000003 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_CMD_COMPLETE_INTR_EN__SHIFT \ - 0x00000008 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT \ - 0x00000009 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_HANG_NEED_FLR_INTR_EN__SHIFT \ - 0x0000000a -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT \ - 0x0000000b -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_CMD_COMPLETE_INTR_EN__SHIFT \ - 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT \ - 0x00000011 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_HANG_NEED_FLR_INTR_EN__SHIFT \ - 0x00000012 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT \ - 0x00000013 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT \ - 0x00000018 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT \ - 0x00000019 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT \ - 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT \ - 0x00000001 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT \ - 0x00000002 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT \ - 0x00000003 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT \ - 0x00000008 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT \ - 0x00000009 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT \ - 0x0000000a -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT \ - 0x0000000b -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT \ - 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT \ - 0x00000011 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT \ - 0x00000012 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT \ - 0x00000013 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT \ - 0x00000018 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT \ - 0x00000019 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf__SOFT_PF_FLR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__VF_INDEX__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__TRN_MSG_DATA__SHIFT 0x00000008 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__TRN_MSG_VALID__SHIFT 0x0000000f -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__RCV_MSG_DATA__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf__RCV_MSG_ACK__SHIFT 0x00000018 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF0_TRN_ACK__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF0_RCV_VALID__SHIFT 0x00000001 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF1_TRN_ACK__SHIFT 0x00000002 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF1_RCV_VALID__SHIFT 0x00000003 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF2_TRN_ACK__SHIFT 0x00000004 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF2_RCV_VALID__SHIFT 0x00000005 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF3_TRN_ACK__SHIFT 0x00000006 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF3_RCV_VALID__SHIFT 0x00000007 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF4_TRN_ACK__SHIFT 0x00000008 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF4_RCV_VALID__SHIFT 0x00000009 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF5_TRN_ACK__SHIFT 0x0000000a -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF5_RCV_VALID__SHIFT 0x0000000b -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF6_TRN_ACK__SHIFT 0x0000000c -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF6_RCV_VALID__SHIFT 0x0000000d -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF7_TRN_ACK__SHIFT 0x0000000e -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF7_RCV_VALID__SHIFT 0x0000000f -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF8_TRN_ACK__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF8_RCV_VALID__SHIFT 0x00000011 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF9_TRN_ACK__SHIFT 0x00000012 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF9_RCV_VALID__SHIFT 0x00000013 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF10_TRN_ACK__SHIFT 0x00000014 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF10_RCV_VALID__SHIFT 0x00000015 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF11_TRN_ACK__SHIFT 0x00000016 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF11_RCV_VALID__SHIFT 0x00000017 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF12_TRN_ACK__SHIFT 0x00000018 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF12_RCV_VALID__SHIFT 0x00000019 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF13_TRN_ACK__SHIFT 0x0000001a -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF13_RCV_VALID__SHIFT 0x0000001b -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF14_TRN_ACK__SHIFT 0x0000001c -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF14_RCV_VALID__SHIFT 0x0000001d -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF15_TRN_ACK__SHIFT 0x0000001e -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf__VF15_RCV_VALID__SHIFT 0x0000001f - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf__PF_TRN_ACK__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf__PF_RCV_VALID__SHIFT 0x00000001 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf__CONTEXT_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf__LOC__SHIFT 0x00000007 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf__CONTEXT_OFFSET__SHIFT 0x0000000a - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf__TOTAL_FB_AVAILABLE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf__TOTAL_FB_CONSUMED__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf__UVDSCH_OFFSET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf__VCESCH_OFFSET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf__GFXSCH_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf__VF0_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf__VF0_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf__VF1_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf__VF1_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf__VF2_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf__VF2_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf__VF3_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf__VF3_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf__VF4_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf__VF4_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf__VF5_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf__VF5_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf__VF6_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf__VF6_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf__VF7_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf__VF7_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf__VF8_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf__VF8_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf__VF9_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf__VF9_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf__VF10_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf__VF10_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf__VF11_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf__VF11_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf__VF12_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf__VF12_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf__VF13_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf__VF13_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf__VF14_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf__VF14_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf__VF15_FB_SIZE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf__VF15_FB_OFFSET__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf__DW0__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf__DW1__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf__DW2__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf__DW3__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf__DW4__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf__DW5__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf__DW6__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf__DW7__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf__DW0__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf__DW1__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf__DW2__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf__DW3__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf__DW4__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf__DW5__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf__DW6__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf__DW7__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf__DW0__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf__DW1__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf__DW2__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf__DW3__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf__DW4__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf__DW5__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf__DW6__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf__DW7__SHIFT 0x00000000 - -// nbif_gpu_VENDOR_ID_epvf -#define nbif_gpu_VENDOR_ID_epvf__VENDOR_ID__SHIFT 0x00000000 - -// nbif_gpu_DEVICE_ID_epvf -#define nbif_gpu_DEVICE_ID_epvf__DEVICE_ID__SHIFT 0x00000000 - -// nbif_gpu_COMMAND_epvf -#define nbif_gpu_COMMAND_epvf__IO_ACCESS_EN__SHIFT 0x00000000 -#define nbif_gpu_COMMAND_epvf__MEM_ACCESS_EN__SHIFT 0x00000001 -#define nbif_gpu_COMMAND_epvf__BUS_MASTER_EN__SHIFT 0x00000002 -#define nbif_gpu_COMMAND_epvf__SPECIAL_CYCLE_EN__SHIFT 0x00000003 -#define nbif_gpu_COMMAND_epvf__MEM_WRITE_INVALIDATE_EN__SHIFT 0x00000004 -#define nbif_gpu_COMMAND_epvf__PAL_SNOOP_EN__SHIFT 0x00000005 -#define nbif_gpu_COMMAND_epvf__PARITY_ERROR_RESPONSE__SHIFT 0x00000006 -#define nbif_gpu_COMMAND_epvf__AD_STEPPING__SHIFT 0x00000007 -#define nbif_gpu_COMMAND_epvf__SERR_EN__SHIFT 0x00000008 -#define nbif_gpu_COMMAND_epvf__FAST_B2B_EN__SHIFT 0x00000009 -#define nbif_gpu_COMMAND_epvf__INT_DIS__SHIFT 0x0000000a - -// nbif_gpu_STATUS_epvf -#define nbif_gpu_STATUS_epvf__INT_STATUS__SHIFT 0x00000003 -#define nbif_gpu_STATUS_epvf__CAP_LIST__SHIFT 0x00000004 -#define nbif_gpu_STATUS_epvf__PCI_66_EN__SHIFT 0x00000005 -#define nbif_gpu_STATUS_epvf__FAST_BACK_CAPABLE__SHIFT 0x00000007 -#define nbif_gpu_STATUS_epvf__MASTER_DATA_PARITY_ERROR__SHIFT 0x00000008 -#define nbif_gpu_STATUS_epvf__DEVSEL_TIMING__SHIFT 0x00000009 -#define nbif_gpu_STATUS_epvf__SIGNAL_TARGET_ABORT__SHIFT 0x0000000b -#define nbif_gpu_STATUS_epvf__RECEIVED_TARGET_ABORT__SHIFT 0x0000000c -#define nbif_gpu_STATUS_epvf__RECEIVED_MASTER_ABORT__SHIFT 0x0000000d -#define nbif_gpu_STATUS_epvf__SIGNALED_SYSTEM_ERROR__SHIFT 0x0000000e -#define nbif_gpu_STATUS_epvf__PARITY_ERROR_DETECTED__SHIFT 0x0000000f - -// nbif_gpu_REVISION_ID_epvf -#define nbif_gpu_REVISION_ID_epvf__MINOR_REV_ID__SHIFT 0x00000000 -#define nbif_gpu_REVISION_ID_epvf__MAJOR_REV_ID__SHIFT 0x00000004 - -// nbif_gpu_PROG_INTERFACE_epvf -#define nbif_gpu_PROG_INTERFACE_epvf__PROG_INTERFACE__SHIFT 0x00000000 - -// nbif_gpu_SUB_CLASS_epvf -#define nbif_gpu_SUB_CLASS_epvf__SUB_CLASS__SHIFT 0x00000000 - -// nbif_gpu_BASE_CLASS_epvf -#define nbif_gpu_BASE_CLASS_epvf__BASE_CLASS__SHIFT 0x00000000 - -// nbif_gpu_CACHE_LINE_epvf -#define nbif_gpu_CACHE_LINE_epvf__CACHE_LINE_SIZE__SHIFT 0x00000000 - -// nbif_gpu_LATENCY_epvf -#define nbif_gpu_LATENCY_epvf__LATENCY_TIMER__SHIFT 0x00000000 - -// nbif_gpu_HEADER_epvf -#define nbif_gpu_HEADER_epvf__HEADER_TYPE__SHIFT 0x00000000 -#define nbif_gpu_HEADER_epvf__DEVICE_TYPE__SHIFT 0x00000007 - -// nbif_gpu_BIST_epvf -#define nbif_gpu_BIST_epvf__BIST_COMP__SHIFT 0x00000000 -#define nbif_gpu_BIST_epvf__BIST_STRT__SHIFT 0x00000006 -#define nbif_gpu_BIST_epvf__BIST_CAP__SHIFT 0x00000007 - -// nbif_gpu_BASE_ADDR_1_epvf -#define nbif_gpu_BASE_ADDR_1_epvf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_2_epvf -#define nbif_gpu_BASE_ADDR_2_epvf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_3_epvf -#define nbif_gpu_BASE_ADDR_3_epvf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_4_epvf -#define nbif_gpu_BASE_ADDR_4_epvf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_5_epvf -#define nbif_gpu_BASE_ADDR_5_epvf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_BASE_ADDR_6_epvf -#define nbif_gpu_BASE_ADDR_6_epvf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_ROM_BASE_ADDR_epvf -#define nbif_gpu_ROM_BASE_ADDR_epvf__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_CAP_PTR_epvf -#define nbif_gpu_CAP_PTR_epvf__CAP_PTR__SHIFT 0x00000000 - -// nbif_gpu_INTERRUPT_LINE_epvf -#define nbif_gpu_INTERRUPT_LINE_epvf__INTERRUPT_LINE__SHIFT 0x00000000 - -// nbif_gpu_INTERRUPT_PIN_epvf -#define nbif_gpu_INTERRUPT_PIN_epvf__INTERRUPT_PIN__SHIFT 0x00000000 - -// nbif_gpu_ADAPTER_ID_epvf -#define nbif_gpu_ADAPTER_ID_epvf__SUBSYSTEM_VENDOR_ID__SHIFT 0x00000000 -#define nbif_gpu_ADAPTER_ID_epvf__SUBSYSTEM_ID__SHIFT 0x00000010 - -// nbif_gpu_PCIE_CAP_LIST_epvf -#define nbif_gpu_PCIE_CAP_LIST_epvf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CAP_LIST_epvf__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_PCIE_CAP_epvf -#define nbif_gpu_PCIE_CAP_epvf__VERSION__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CAP_epvf__DEVICE_TYPE__SHIFT 0x00000004 -#define nbif_gpu_PCIE_CAP_epvf__SLOT_IMPLEMENTED__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CAP_epvf__INT_MESSAGE_NUM__SHIFT 0x00000009 - -// nbif_gpu_DEVICE_CAP_epvf -#define nbif_gpu_DEVICE_CAP_epvf__MAX_PAYLOAD_SUPPORT__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CAP_epvf__PHANTOM_FUNC__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_CAP_epvf__EXTENDED_TAG__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CAP_epvf__L0S_ACCEPTABLE_LATENCY__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CAP_epvf__L1_ACCEPTABLE_LATENCY__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CAP_epvf__ROLE_BASED_ERR_REPORTING__SHIFT 0x0000000f -#define nbif_gpu_DEVICE_CAP_epvf__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x00000012 -#define nbif_gpu_DEVICE_CAP_epvf__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x0000001a -#define nbif_gpu_DEVICE_CAP_epvf__FLR_CAPABLE__SHIFT 0x0000001c - -// nbif_gpu_DEVICE_CNTL_epvf -#define nbif_gpu_DEVICE_CNTL_epvf__CORR_ERR_EN__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CNTL_epvf__NON_FATAL_ERR_EN__SHIFT 0x00000001 -#define nbif_gpu_DEVICE_CNTL_epvf__FATAL_ERR_EN__SHIFT 0x00000002 -#define nbif_gpu_DEVICE_CNTL_epvf__USR_REPORT_EN__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_CNTL_epvf__RELAXED_ORD_EN__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CNTL_epvf__MAX_PAYLOAD_SIZE__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CNTL_epvf__EXTENDED_TAG_EN__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CNTL_epvf__PHANTOM_FUNC_EN__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CNTL_epvf__AUX_POWER_PM_EN__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CNTL_epvf__NO_SNOOP_EN__SHIFT 0x0000000b -#define nbif_gpu_DEVICE_CNTL_epvf__MAX_READ_REQUEST_SIZE__SHIFT 0x0000000c -#define nbif_gpu_DEVICE_CNTL_epvf__INITIATE_FLR__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_STATUS_epvf -#define nbif_gpu_DEVICE_STATUS_epvf__CORR_ERR__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_STATUS_epvf__NON_FATAL_ERR__SHIFT 0x00000001 -#define nbif_gpu_DEVICE_STATUS_epvf__FATAL_ERR__SHIFT 0x00000002 -#define nbif_gpu_DEVICE_STATUS_epvf__USR_DETECTED__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_STATUS_epvf__AUX_PWR__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_STATUS_epvf__TRANSACTIONS_PEND__SHIFT 0x00000005 - -// nbif_gpu_LINK_CAP_epvf -#define nbif_gpu_LINK_CAP_epvf__LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_CAP_epvf__LINK_WIDTH__SHIFT 0x00000004 -#define nbif_gpu_LINK_CAP_epvf__PM_SUPPORT__SHIFT 0x0000000a -#define nbif_gpu_LINK_CAP_epvf__L0S_EXIT_LATENCY__SHIFT 0x0000000c -#define nbif_gpu_LINK_CAP_epvf__L1_EXIT_LATENCY__SHIFT 0x0000000f -#define nbif_gpu_LINK_CAP_epvf__CLOCK_POWER_MANAGEMENT__SHIFT 0x00000012 -#define nbif_gpu_LINK_CAP_epvf__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x00000013 -#define nbif_gpu_LINK_CAP_epvf__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x00000014 -#define nbif_gpu_LINK_CAP_epvf__LINK_BW_NOTIFICATION_CAP__SHIFT 0x00000015 -#define nbif_gpu_LINK_CAP_epvf__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x00000016 -#define nbif_gpu_LINK_CAP_epvf__PORT_NUMBER__SHIFT 0x00000018 - -// nbif_gpu_LINK_CNTL_epvf -#define nbif_gpu_LINK_CNTL_epvf__PM_CONTROL__SHIFT 0x00000000 -#define nbif_gpu_LINK_CNTL_epvf__READ_CPL_BOUNDARY__SHIFT 0x00000003 -#define nbif_gpu_LINK_CNTL_epvf__LINK_DIS__SHIFT 0x00000004 -#define nbif_gpu_LINK_CNTL_epvf__RETRAIN_LINK__SHIFT 0x00000005 -#define nbif_gpu_LINK_CNTL_epvf__COMMON_CLOCK_CFG__SHIFT 0x00000006 -#define nbif_gpu_LINK_CNTL_epvf__EXTENDED_SYNC__SHIFT 0x00000007 -#define nbif_gpu_LINK_CNTL_epvf__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x00000008 -#define nbif_gpu_LINK_CNTL_epvf__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x00000009 -#define nbif_gpu_LINK_CNTL_epvf__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0x0000000a -#define nbif_gpu_LINK_CNTL_epvf__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0x0000000b - -// nbif_gpu_LINK_STATUS_epvf -#define nbif_gpu_LINK_STATUS_epvf__CURRENT_LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_STATUS_epvf__NEGOTIATED_LINK_WIDTH__SHIFT 0x00000004 -#define nbif_gpu_LINK_STATUS_epvf__LINK_TRAINING__SHIFT 0x0000000b -#define nbif_gpu_LINK_STATUS_epvf__SLOT_CLOCK_CFG__SHIFT 0x0000000c -#define nbif_gpu_LINK_STATUS_epvf__DL_ACTIVE__SHIFT 0x0000000d -#define nbif_gpu_LINK_STATUS_epvf__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x0000000e -#define nbif_gpu_LINK_STATUS_epvf__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_CAP2_epvf -#define nbif_gpu_DEVICE_CAP2_epvf__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CAP2_epvf__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CAP2_epvf__ARI_FORWARDING_SUPPORTED__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CAP2_epvf__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CAP2_epvf__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x00000007 -#define nbif_gpu_DEVICE_CAP2_epvf__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CAP2_epvf__CAS128_CMPLT_SUPPORTED__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CAP2_epvf__NO_RO_ENABLED_P2P_PASSING__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CAP2_epvf__LTR_SUPPORTED__SHIFT 0x0000000b -#define nbif_gpu_DEVICE_CAP2_epvf__TPH_CPLR_SUPPORTED__SHIFT 0x0000000c -#define nbif_gpu_DEVICE_CAP2_epvf__OBFF_SUPPORTED__SHIFT 0x00000012 -#define nbif_gpu_DEVICE_CAP2_epvf__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x00000014 -#define nbif_gpu_DEVICE_CAP2_epvf__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x00000015 -#define nbif_gpu_DEVICE_CAP2_epvf__MAX_END_END_TLP_PREFIXES__SHIFT 0x00000016 - -// nbif_gpu_DEVICE_CNTL2_epvf -#define nbif_gpu_DEVICE_CNTL2_epvf__CPL_TIMEOUT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CNTL2_epvf__CPL_TIMEOUT_DIS__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CNTL2_epvf__ARI_FORWARDING_EN__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CNTL2_epvf__ATOMICOP_REQUEST_EN__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CNTL2_epvf__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x00000007 -#define nbif_gpu_DEVICE_CNTL2_epvf__IDO_REQUEST_ENABLE__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CNTL2_epvf__IDO_COMPLETION_ENABLE__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CNTL2_epvf__LTR_EN__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CNTL2_epvf__OBFF_EN__SHIFT 0x0000000d -#define nbif_gpu_DEVICE_CNTL2_epvf__END_END_TLP_PREFIX_BLOCKING__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_STATUS2_epvf -#define nbif_gpu_DEVICE_STATUS2_epvf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_LINK_CAP2_epvf -#define nbif_gpu_LINK_CAP2_epvf__SUPPORTED_LINK_SPEED__SHIFT 0x00000001 -#define nbif_gpu_LINK_CAP2_epvf__CROSSLINK_SUPPORTED__SHIFT 0x00000008 -#define nbif_gpu_LINK_CAP2_epvf__RESERVED__SHIFT 0x00000009 - -// nbif_gpu_LINK_CNTL2_epvf -#define nbif_gpu_LINK_CNTL2_epvf__TARGET_LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_CNTL2_epvf__ENTER_COMPLIANCE__SHIFT 0x00000004 -#define nbif_gpu_LINK_CNTL2_epvf__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x00000005 -#define nbif_gpu_LINK_CNTL2_epvf__SELECTABLE_DEEMPHASIS__SHIFT 0x00000006 -#define nbif_gpu_LINK_CNTL2_epvf__XMIT_MARGIN__SHIFT 0x00000007 -#define nbif_gpu_LINK_CNTL2_epvf__ENTER_MOD_COMPLIANCE__SHIFT 0x0000000a -#define nbif_gpu_LINK_CNTL2_epvf__COMPLIANCE_SOS__SHIFT 0x0000000b -#define nbif_gpu_LINK_CNTL2_epvf__COMPLIANCE_DEEMPHASIS__SHIFT 0x0000000c - -// nbif_gpu_LINK_STATUS2_epvf -#define nbif_gpu_LINK_STATUS2_epvf__CUR_DEEMPHASIS_LEVEL__SHIFT 0x00000000 -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_COMPLETE__SHIFT 0x00000001 -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x00000002 -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x00000003 -#define nbif_gpu_LINK_STATUS2_epvf__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x00000004 -#define nbif_gpu_LINK_STATUS2_epvf__LINK_EQUALIZATION_REQUEST__SHIFT 0x00000005 - -// nbif_gpu_SLOT_CAP2_epvf -#define nbif_gpu_SLOT_CAP2_epvf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_SLOT_CNTL2_epvf -#define nbif_gpu_SLOT_CNTL2_epvf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_SLOT_STATUS2_epvf -#define nbif_gpu_SLOT_STATUS2_epvf__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_MSI_CAP_LIST_epvf -#define nbif_gpu_MSI_CAP_LIST_epvf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_MSI_CAP_LIST_epvf__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_MSI_MSG_CNTL_epvf -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_EN__SHIFT 0x00000000 -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_MULTI_CAP__SHIFT 0x00000001 -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_MULTI_EN__SHIFT 0x00000004 -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_64BIT__SHIFT 0x00000007 -#define nbif_gpu_MSI_MSG_CNTL_epvf__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x00000008 - -// nbif_gpu_MSI_MSG_ADDR_LO_epvf -#define nbif_gpu_MSI_MSG_ADDR_LO_epvf__MSI_MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_MSI_MSG_ADDR_HI_epvf -#define nbif_gpu_MSI_MSG_ADDR_HI_epvf__MSI_MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_MSI_MSG_DATA_64_epvf -#define nbif_gpu_MSI_MSG_DATA_64_epvf__MSI_DATA_64__SHIFT 0x00000000 - -// nbif_gpu_MSI_MSG_DATA_epvf -#define nbif_gpu_MSI_MSG_DATA_epvf__MSI_DATA__SHIFT 0x00000000 - -// nbif_gpu_MSI_MASK_epvf -#define nbif_gpu_MSI_MASK_epvf__MSI_MASK__SHIFT 0x00000000 - -// nbif_gpu_MSI_PENDING_epvf -#define nbif_gpu_MSI_PENDING_epvf__MSI_PENDING__SHIFT 0x00000000 - -// nbif_gpu_MSI_MASK_64_epvf -#define nbif_gpu_MSI_MASK_64_epvf__MSI_MASK_64__SHIFT 0x00000000 - -// nbif_gpu_MSI_PENDING_64_epvf -#define nbif_gpu_MSI_PENDING_64_epvf__MSI_PENDING_64__SHIFT 0x00000000 - -// nbif_gpu_MSIX_CAP_LIST_epvf -#define nbif_gpu_MSIX_CAP_LIST_epvf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_MSIX_CAP_LIST_epvf__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_MSIX_MSG_CNTL_epvf -#define nbif_gpu_MSIX_MSG_CNTL_epvf__MSIX_TABLE_SIZE__SHIFT 0x00000000 -#define nbif_gpu_MSIX_MSG_CNTL_epvf__MSIX_FUNC_MASK__SHIFT 0x0000000e -#define nbif_gpu_MSIX_MSG_CNTL_epvf__MSIX_EN__SHIFT 0x0000000f - -// nbif_gpu_MSIX_TABLE_epvf -#define nbif_gpu_MSIX_TABLE_epvf__MSIX_TABLE_BIR__SHIFT 0x00000000 -#define nbif_gpu_MSIX_TABLE_epvf__MSIX_TABLE_OFFSET__SHIFT 0x00000003 - -// nbif_gpu_MSIX_PBA_epvf -#define nbif_gpu_MSIX_PBA_epvf__MSIX_PBA_BIR__SHIFT 0x00000000 -#define nbif_gpu_MSIX_PBA_epvf__MSIX_PBA_OFFSET__SHIFT 0x00000003 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf__VSEC_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf__VSEC_REV__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf__VSEC_LENGTH__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf__SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf -#define nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf__SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__DLP_ERR_STATUS__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__SURPDN_ERR_STATUS__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__PSN_ERR_STATUS__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__FC_ERR_STATUS__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__CPL_TIMEOUT_STATUS__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__CPL_ABORT_ERR_STATUS__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__UNEXP_CPL_STATUS__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__RCV_OVFL_STATUS__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__MAL_TLP_STATUS__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__ECRC_ERR_STATUS__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__UNSUPP_REQ_ERR_STATUS__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__ACS_VIOLATION_STATUS__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__UNCORR_INT_ERR_STATUS__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__MC_BLOCKED_TLP_STATUS__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x00000019 - -// nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__DLP_ERR_MASK__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__SURPDN_ERR_MASK__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__PSN_ERR_MASK__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__FC_ERR_MASK__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__CPL_TIMEOUT_MASK__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__CPL_ABORT_ERR_MASK__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__UNEXP_CPL_MASK__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__RCV_OVFL_MASK__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__MAL_TLP_MASK__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__ECRC_ERR_MASK__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__UNSUPP_REQ_ERR_MASK__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__ACS_VIOLATION_MASK__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__UNCORR_INT_ERR_MASK__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__MC_BLOCKED_TLP_MASK__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x00000019 - -// nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__DLP_ERR_SEVERITY__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__SURPDN_ERR_SEVERITY__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__PSN_ERR_SEVERITY__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__FC_ERR_SEVERITY__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__CPL_TIMEOUT_SEVERITY__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__CPL_ABORT_ERR_SEVERITY__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__UNEXP_CPL_SEVERITY__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__RCV_OVFL_SEVERITY__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__MAL_TLP_SEVERITY__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__ECRC_ERR_SEVERITY__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__ACS_VIOLATION_SEVERITY__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__UNCORR_INT_ERR_SEVERITY__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x00000019 - -// nbif_gpu_PCIE_CORR_ERR_STATUS_epvf -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__RCV_ERR_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__BAD_TLP_STATUS__SHIFT 0x00000006 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__BAD_DLLP_STATUS__SHIFT 0x00000007 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0x0000000c -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x0000000d -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__CORR_INT_ERR_STATUS__SHIFT 0x0000000e -#define nbif_gpu_PCIE_CORR_ERR_STATUS_epvf__HDR_LOG_OVFL_STATUS__SHIFT 0x0000000f - -// nbif_gpu_PCIE_CORR_ERR_MASK_epvf -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__RCV_ERR_MASK__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__BAD_TLP_MASK__SHIFT 0x00000006 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__BAD_DLLP_MASK__SHIFT 0x00000007 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0x0000000c -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0x0000000d -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__CORR_INT_ERR_MASK__SHIFT 0x0000000e -#define nbif_gpu_PCIE_CORR_ERR_MASK_epvf__HDR_LOG_OVFL_MASK__SHIFT 0x0000000f - -// nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__FIRST_ERR_PTR__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_GEN_CAP__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_GEN_EN__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_CHECK_CAP__SHIFT 0x00000007 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__ECRC_CHECK_EN__SHIFT 0x00000008 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__MULTI_HDR_RECD_CAP__SHIFT 0x00000009 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__MULTI_HDR_RECD_EN__SHIFT 0x0000000a -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf__TLP_PREFIX_LOG_PRESENT__SHIFT 0x0000000b - -// nbif_gpu_PCIE_HDR_LOG0_epvf -#define nbif_gpu_PCIE_HDR_LOG0_epvf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG1_epvf -#define nbif_gpu_PCIE_HDR_LOG1_epvf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG2_epvf -#define nbif_gpu_PCIE_HDR_LOG2_epvf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG3_epvf -#define nbif_gpu_PCIE_HDR_LOG3_epvf__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_ROOT_ERR_CMD_epvf -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epvf__CORR_ERR_REP_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epvf__NONFATAL_ERR_REP_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ROOT_ERR_CMD_epvf__FATAL_ERR_REP_EN__SHIFT 0x00000002 - -// nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__ERR_CORR_RCVD__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__MULT_ERR_CORR_RCVD__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x00000002 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x00000003 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x00000004 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__FATAL_ERROR_MSG_RCVD__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf__ADV_ERR_INT_MSG_NUM__SHIFT 0x0000001b - -// nbif_gpu_PCIE_ERR_SRC_ID_epvf -#define nbif_gpu_PCIE_ERR_SRC_ID_epvf__ERR_CORR_SRC_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ERR_SRC_ID_epvf__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x00000010 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf -#define nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_ATS_CAP_epvf -#define nbif_gpu_PCIE_ATS_CAP_epvf__INVALIDATE_Q_DEPTH__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ATS_CAP_epvf__PAGE_ALIGNED_REQUEST__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ATS_CAP_epvf__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x00000006 - -// nbif_gpu_PCIE_ATS_CNTL_epvf -#define nbif_gpu_PCIE_ATS_CNTL_epvf__STU__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ATS_CNTL_epvf__ATC_ENABLE__SHIFT 0x0000000f - -// nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_ARI_CAP_epvf -#define nbif_gpu_PCIE_ARI_CAP_epvf__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ARI_CAP_epvf__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ARI_CAP_epvf__ARI_NEXT_FUNC_NUM__SHIFT 0x00000008 - -// nbif_gpu_PCIE_ARI_CNTL_epvf -#define nbif_gpu_PCIE_ARI_CNTL_epvf__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ARI_CNTL_epvf__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ARI_CNTL_epvf__ARI_FUNCTION_GROUP__SHIFT 0x00000004 - -// nbif_gpu_RCC_BACO_CNTL_MISC -#define nbif_gpu_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x00000000 -#define nbif_gpu_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x00000001 - -// nbif_gpu_RCC_RESET_EN -#define nbif_gpu_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0x0000000f - -// nbif_gpu_RCC_VDM_SUPPORT -#define nbif_gpu_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x00000000 -#define nbif_gpu_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x00000001 -#define nbif_gpu_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x00000002 -#define nbif_gpu_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x00000003 -#define nbif_gpu_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x00000004 - -// nbif_gpu_RCC_BUS_CNTL -#define nbif_gpu_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x00000002 -#define nbif_gpu_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x00000003 -#define nbif_gpu_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x00000004 -#define nbif_gpu_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x00000005 -#define nbif_gpu_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x00000006 -#define nbif_gpu_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x00000007 -#define nbif_gpu_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x00000008 -#define nbif_gpu_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0x0000000c -#define nbif_gpu_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0x0000000d -#define nbif_gpu_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x00000010 -#define nbif_gpu_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x00000011 -#define nbif_gpu_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x00000012 -#define nbif_gpu_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x00000013 -#define nbif_gpu_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x00000014 -#define nbif_gpu_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x00000015 -#define nbif_gpu_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x00000018 -#define nbif_gpu_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x00000019 -#define nbif_gpu_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x0000001c -#define nbif_gpu_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x0000001d - -// nbif_gpu_RCC_CONFIG_CNTL -#define nbif_gpu_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x00000000 -#define nbif_gpu_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x00000002 -#define nbif_gpu_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x00000003 - -// nbif_gpu_RCC_CONFIG_F0_BASE -#define nbif_gpu_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x00000000 - -// nbif_gpu_RCC_CONFIG_APER_SIZE -#define nbif_gpu_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x00000000 - -// nbif_gpu_RCC_CONFIG_REG_APER_SIZE -#define nbif_gpu_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x00000000 - -// nbif_gpu_RCC_XDMA_LO -#define nbif_gpu_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x00000000 -#define nbif_gpu_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x0000001f - -// nbif_gpu_RCC_XDMA_HI -#define nbif_gpu_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x00000000 - -// nbif_gpu_RCC_FEATURES_CONTROL_MISC -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x00000004 -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x00000005 -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x00000006 -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x00000008 -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x00000009 -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0x0000000a -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0x0000000b -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0x0000000c -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0x0000000d -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0x0000000e -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0x0000000f -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x00000010 -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x00000011 -#define nbif_gpu_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x00000012 - -// nbif_gpu_RCC_BUSNUM_CNTL1 -#define nbif_gpu_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x00000000 - -// nbif_gpu_RCC_BUSNUM_LIST0 -#define nbif_gpu_RCC_BUSNUM_LIST0__ID0__SHIFT 0x00000000 -#define nbif_gpu_RCC_BUSNUM_LIST0__ID1__SHIFT 0x00000008 -#define nbif_gpu_RCC_BUSNUM_LIST0__ID2__SHIFT 0x00000010 -#define nbif_gpu_RCC_BUSNUM_LIST0__ID3__SHIFT 0x00000018 - -// nbif_gpu_RCC_BUSNUM_LIST1 -#define nbif_gpu_RCC_BUSNUM_LIST1__ID4__SHIFT 0x00000000 -#define nbif_gpu_RCC_BUSNUM_LIST1__ID5__SHIFT 0x00000008 -#define nbif_gpu_RCC_BUSNUM_LIST1__ID6__SHIFT 0x00000010 -#define nbif_gpu_RCC_BUSNUM_LIST1__ID7__SHIFT 0x00000018 - -// nbif_gpu_RCC_BUSNUM_CNTL2 -#define nbif_gpu_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x00000000 -#define nbif_gpu_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x00000008 -#define nbif_gpu_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x00000010 -#define nbif_gpu_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x00000011 - -// nbif_gpu_RCC_CAPTURE_HOST_BUSNUM -#define nbif_gpu_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x00000000 - -// nbif_gpu_RCC_HOST_BUSNUM -#define nbif_gpu_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x00000000 - -// nbif_gpu_RCC_PEER0_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x00000000 - -// nbif_gpu_RCC_PEER0_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x00000000 -#define nbif_gpu_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x0000001f - -// nbif_gpu_RCC_PEER1_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x00000000 - -// nbif_gpu_RCC_PEER1_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x00000000 -#define nbif_gpu_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x0000001f - -// nbif_gpu_RCC_PEER2_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x00000000 - -// nbif_gpu_RCC_PEER2_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x00000000 -#define nbif_gpu_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x0000001f - -// nbif_gpu_RCC_PEER3_FB_OFFSET_HI -#define nbif_gpu_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x00000000 - -// nbif_gpu_RCC_PEER3_FB_OFFSET_LO -#define nbif_gpu_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x00000000 -#define nbif_gpu_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEVFUNCNUM_LIST0 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEVFUNCNUM_LIST1 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x00000018 - -// nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO -#define nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT 0x00000000 -#define nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_LINK_CNTL -#define nbif_gpu_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x00000008 - -// nbif_gpu_RCC_CMN_LINK_CNTL -#define nbif_gpu_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x00000000 -#define nbif_gpu_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x00000001 -#define nbif_gpu_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x00000002 -#define nbif_gpu_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x00000003 - -// nbif_gpu_RCC_EP_REQUESTERID_RESTORE -#define nbif_gpu_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x00000000 -#define nbif_gpu_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x00000008 - -// nbif_gpu_RCC_LTR_LSWITCH_CNTL -#define nbif_gpu_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x00000000 - -// nbif_gpu_RCC_MH_ARB_CNTL -#define nbif_gpu_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x00000000 -#define nbif_gpu_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x00000001 - -// nbif_gpu_GFXMSIX_VECT0_ADDR_LO -#define nbif_gpu_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_GFXMSIX_VECT1_ADDR_LO -#define nbif_gpu_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_GFXMSIX_VECT2_ADDR_LO -#define nbif_gpu_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_GFXMSIX_VECT0_ADDR_HI -#define nbif_gpu_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT1_ADDR_HI -#define nbif_gpu_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT2_ADDR_HI -#define nbif_gpu_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT0_MSG_DATA -#define nbif_gpu_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT1_MSG_DATA -#define nbif_gpu_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT2_MSG_DATA -#define nbif_gpu_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT0_CONTROL -#define nbif_gpu_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT1_CONTROL -#define nbif_gpu_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_VECT2_CONTROL -#define nbif_gpu_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_GFXMSIX_PBA -#define nbif_gpu_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x00000000 -#define nbif_gpu_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x00000001 -#define nbif_gpu_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x00000002 - -// nbif_gpu_RCC_DOORBELL_APER_EN -#define nbif_gpu_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x00000000 - -// nbif_gpu_RCC_CONFIG_MEMSIZE -#define nbif_gpu_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x00000000 - -// nbif_gpu_RCC_CONFIG_RESERVED -#define nbif_gpu_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x00000000 - -// nbif_gpu_RCC_IOV_FUNC_IDENTIFIER -#define nbif_gpu_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x00000000 -#define nbif_gpu_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x0000001f - -// nbif_gpu_DN_PCIE_RESERVED -#define nbif_gpu_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x00000000 - -// nbif_gpu_DN_PCIE_SCRATCH -#define nbif_gpu_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_DN_PCIE_HW_DEBUG -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define nbif_gpu_DN_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f - -// nbif_gpu_DN_PCIE_CNTL -#define nbif_gpu_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x00000000 -#define nbif_gpu_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x00000007 -#define nbif_gpu_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x0000001e - -// nbif_gpu_DN_PCIE_CONFIG_CNTL -#define nbif_gpu_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x00000019 - -// nbif_gpu_DN_PCIE_RX_CNTL2 -#define nbif_gpu_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x0000001c - -// nbif_gpu_DN_PCIE_BUS_CNTL -#define nbif_gpu_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x00000007 -#define nbif_gpu_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x00000008 - -// nbif_gpu_DN_PCIE_CFG_CNTL -#define nbif_gpu_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x00000000 -#define nbif_gpu_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x00000001 -#define nbif_gpu_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x00000002 - -// nbif_gpu_DN_PCIE_STRAP_F0 -#define nbif_gpu_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x00000000 -#define nbif_gpu_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x00000011 -#define nbif_gpu_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x00000015 - -// nbif_gpu_DN_PCIE_STRAP_MISC -#define nbif_gpu_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x00000018 -#define nbif_gpu_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x0000001d - -// nbif_gpu_DN_PCIE_STRAP_MISC2 -#define nbif_gpu_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x00000002 - -// nbif_gpu_PCIEP_RESERVED -#define nbif_gpu_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x00000000 - -// nbif_gpu_PCIEP_SCRATCH -#define nbif_gpu_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_PCIEP_HW_DEBUG -#define nbif_gpu_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define nbif_gpu_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define nbif_gpu_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define nbif_gpu_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define nbif_gpu_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define nbif_gpu_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define nbif_gpu_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f - -// nbif_gpu_PCIE_ERR_CNTL -#define nbif_gpu_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x00000008 -#define nbif_gpu_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x0000000b -#define nbif_gpu_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x00000011 - -// nbif_gpu_PCIE_RX_CNTL -#define nbif_gpu_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x00000008 -#define nbif_gpu_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x00000009 -#define nbif_gpu_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x00000014 -#define nbif_gpu_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x00000015 -#define nbif_gpu_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x0000001b - -// nbif_gpu_PCIE_LC_SPEED_CNTL -#define nbif_gpu_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x00000001 - -// nbif_gpu_PCIE_LC_CNTL2 -#define nbif_gpu_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x0000001b - -// nbif_gpu_PCIEP_STRAP_MISC -#define nbif_gpu_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0x0000000a - -// nbif_gpu_LTR_MSG_INFO_FROM_EP -#define nbif_gpu_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x00000000 - -// nbif_gpu_VENDOR_ID_swds -#define nbif_gpu_VENDOR_ID_swds__VENDOR_ID__SHIFT 0x00000000 - -// nbif_gpu_DEVICE_ID_swds -#define nbif_gpu_DEVICE_ID_swds__DEVICE_ID__SHIFT 0x00000000 - -// nbif_gpu_COMMAND_swds -#define nbif_gpu_COMMAND_swds__IOEN_DN__SHIFT 0x00000000 -#define nbif_gpu_COMMAND_swds__MEMEN_DN__SHIFT 0x00000001 -#define nbif_gpu_COMMAND_swds__BUS_MASTER_EN__SHIFT 0x00000002 -#define nbif_gpu_COMMAND_swds__SPECIAL_CYCLE_EN__SHIFT 0x00000003 -#define nbif_gpu_COMMAND_swds__MEM_WRITE_INVALIDATE_EN__SHIFT 0x00000004 -#define nbif_gpu_COMMAND_swds__PAL_SNOOP_EN__SHIFT 0x00000005 -#define nbif_gpu_COMMAND_swds__PARITY_ERROR_RESPONSE__SHIFT 0x00000006 -#define nbif_gpu_COMMAND_swds__AD_STEPPING__SHIFT 0x00000007 -#define nbif_gpu_COMMAND_swds__SERR_EN__SHIFT 0x00000008 -#define nbif_gpu_COMMAND_swds__FAST_B2B_EN__SHIFT 0x00000009 -#define nbif_gpu_COMMAND_swds__INT_DIS__SHIFT 0x0000000a - -// nbif_gpu_STATUS_swds -#define nbif_gpu_STATUS_swds__INT_STATUS__SHIFT 0x00000003 -#define nbif_gpu_STATUS_swds__CAP_LIST__SHIFT 0x00000004 -#define nbif_gpu_STATUS_swds__PCI_66_EN__SHIFT 0x00000005 -#define nbif_gpu_STATUS_swds__FAST_BACK_CAPABLE__SHIFT 0x00000007 -#define nbif_gpu_STATUS_swds__MASTER_DATA_PARITY_ERROR__SHIFT 0x00000008 -#define nbif_gpu_STATUS_swds__DEVSEL_TIMING__SHIFT 0x00000009 -#define nbif_gpu_STATUS_swds__SIGNAL_TARGET_ABORT__SHIFT 0x0000000b -#define nbif_gpu_STATUS_swds__RECEIVED_TARGET_ABORT__SHIFT 0x0000000c -#define nbif_gpu_STATUS_swds__RECEIVED_MASTER_ABORT__SHIFT 0x0000000d -#define nbif_gpu_STATUS_swds__SIGNALED_SYSTEM_ERROR__SHIFT 0x0000000e -#define nbif_gpu_STATUS_swds__PARITY_ERROR_DETECTED__SHIFT 0x0000000f - -// nbif_gpu_REVISION_ID_swds -#define nbif_gpu_REVISION_ID_swds__MINOR_REV_ID__SHIFT 0x00000000 -#define nbif_gpu_REVISION_ID_swds__MAJOR_REV_ID__SHIFT 0x00000004 - -// nbif_gpu_PROG_INTERFACE_swds -#define nbif_gpu_PROG_INTERFACE_swds__PROG_INTERFACE__SHIFT 0x00000000 - -// nbif_gpu_SUB_CLASS_swds -#define nbif_gpu_SUB_CLASS_swds__SUB_CLASS__SHIFT 0x00000000 - -// nbif_gpu_BASE_CLASS_swds -#define nbif_gpu_BASE_CLASS_swds__BASE_CLASS__SHIFT 0x00000000 - -// nbif_gpu_CACHE_LINE_swds -#define nbif_gpu_CACHE_LINE_swds__CACHE_LINE_SIZE__SHIFT 0x00000000 - -// nbif_gpu_LATENCY_swds -#define nbif_gpu_LATENCY_swds__LATENCY_TIMER__SHIFT 0x00000000 - -// nbif_gpu_HEADER_swds -#define nbif_gpu_HEADER_swds__HEADER_TYPE__SHIFT 0x00000000 -#define nbif_gpu_HEADER_swds__DEVICE_TYPE__SHIFT 0x00000007 - -// nbif_gpu_BIST_swds -#define nbif_gpu_BIST_swds__BIST_COMP__SHIFT 0x00000000 -#define nbif_gpu_BIST_swds__BIST_STRT__SHIFT 0x00000006 -#define nbif_gpu_BIST_swds__BIST_CAP__SHIFT 0x00000007 - -// nbif_gpu_BASE_ADDR_1_swds -#define nbif_gpu_BASE_ADDR_1_swds__BASE_ADDR__SHIFT 0x00000000 - -// nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__PRIMARY_BUS__SHIFT 0x00000000 -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__SECONDARY_BUS__SHIFT 0x00000008 -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__SUB_BUS_NUM__SHIFT 0x00000010 -#define nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds__SECONDARY_LATENCY_TIMER__SHIFT 0x00000018 - -// nbif_gpu_IO_BASE_LIMIT_swds -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_BASE_TYPE__SHIFT 0x00000000 -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_BASE__SHIFT 0x00000004 -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_LIMIT_TYPE__SHIFT 0x00000008 -#define nbif_gpu_IO_BASE_LIMIT_swds__IO_LIMIT__SHIFT 0x0000000c - -// nbif_gpu_SECONDARY_STATUS_swds -#define nbif_gpu_SECONDARY_STATUS_swds__CAP_LIST__SHIFT 0x00000004 -#define nbif_gpu_SECONDARY_STATUS_swds__PCI_66_EN__SHIFT 0x00000005 -#define nbif_gpu_SECONDARY_STATUS_swds__FAST_BACK_CAPABLE__SHIFT 0x00000007 -#define nbif_gpu_SECONDARY_STATUS_swds__MASTER_DATA_PARITY_ERROR__SHIFT 0x00000008 -#define nbif_gpu_SECONDARY_STATUS_swds__DEVSEL_TIMING__SHIFT 0x00000009 -#define nbif_gpu_SECONDARY_STATUS_swds__SIGNAL_TARGET_ABORT__SHIFT 0x0000000b -#define nbif_gpu_SECONDARY_STATUS_swds__RECEIVED_TARGET_ABORT__SHIFT 0x0000000c -#define nbif_gpu_SECONDARY_STATUS_swds__RECEIVED_MASTER_ABORT__SHIFT 0x0000000d -#define nbif_gpu_SECONDARY_STATUS_swds__RECEIVED_SYSTEM_ERROR__SHIFT 0x0000000e -#define nbif_gpu_SECONDARY_STATUS_swds__PARITY_ERROR_DETECTED__SHIFT 0x0000000f - -// nbif_gpu_MEM_BASE_LIMIT_swds -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_BASE_TYPE__SHIFT 0x00000000 -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_BASE_31_20__SHIFT 0x00000004 -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_LIMIT_TYPE__SHIFT 0x00000010 -#define nbif_gpu_MEM_BASE_LIMIT_swds__MEM_LIMIT_31_20__SHIFT 0x00000014 - -// nbif_gpu_PREF_BASE_LIMIT_swds -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_BASE_TYPE__SHIFT 0x00000000 -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_BASE_31_20__SHIFT 0x00000004 -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_LIMIT_TYPE__SHIFT 0x00000010 -#define nbif_gpu_PREF_BASE_LIMIT_swds__PREF_MEM_LIMIT_31_20__SHIFT 0x00000014 - -// nbif_gpu_PREF_BASE_UPPER_swds -#define nbif_gpu_PREF_BASE_UPPER_swds__PREF_BASE_UPPER__SHIFT 0x00000000 - -// nbif_gpu_PREF_LIMIT_UPPER_swds -#define nbif_gpu_PREF_LIMIT_UPPER_swds__PREF_LIMIT_UPPER__SHIFT 0x00000000 - -// nbif_gpu_IO_BASE_LIMIT_HI_swds -#define nbif_gpu_IO_BASE_LIMIT_HI_swds__IO_BASE_31_16__SHIFT 0x00000000 -#define nbif_gpu_IO_BASE_LIMIT_HI_swds__IO_LIMIT_31_16__SHIFT 0x00000010 - -// nbif_gpu_IRQ_BRIDGE_CNTL_swds -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__PARITY_RESPONSE_EN__SHIFT 0x00000000 -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__SERR_EN__SHIFT 0x00000001 -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__ISA_EN__SHIFT 0x00000002 -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__VGA_EN__SHIFT 0x00000003 -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__VGA_DEC__SHIFT 0x00000004 -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__MASTER_ABORT_MODE__SHIFT 0x00000005 -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__SECONDARY_BUS_RESET__SHIFT 0x00000006 -#define nbif_gpu_IRQ_BRIDGE_CNTL_swds__FAST_B2B_EN__SHIFT 0x00000007 - -// nbif_gpu_CAP_PTR_swds -#define nbif_gpu_CAP_PTR_swds__CAP_PTR__SHIFT 0x00000000 - -// nbif_gpu_INTERRUPT_LINE_swds -#define nbif_gpu_INTERRUPT_LINE_swds__INTERRUPT_LINE__SHIFT 0x00000000 - -// nbif_gpu_INTERRUPT_PIN_swds -#define nbif_gpu_INTERRUPT_PIN_swds__INTERRUPT_PIN__SHIFT 0x00000000 - -// nbif_gpu_PMI_CAP_LIST_swds -#define nbif_gpu_PMI_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PMI_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_PMI_CAP_swds -#define nbif_gpu_PMI_CAP_swds__VERSION__SHIFT 0x00000000 -#define nbif_gpu_PMI_CAP_swds__PME_CLOCK__SHIFT 0x00000003 -#define nbif_gpu_PMI_CAP_swds__DEV_SPECIFIC_INIT__SHIFT 0x00000005 -#define nbif_gpu_PMI_CAP_swds__AUX_CURRENT__SHIFT 0x00000006 -#define nbif_gpu_PMI_CAP_swds__D1_SUPPORT__SHIFT 0x00000009 -#define nbif_gpu_PMI_CAP_swds__D2_SUPPORT__SHIFT 0x0000000a -#define nbif_gpu_PMI_CAP_swds__PME_SUPPORT__SHIFT 0x0000000b - -// nbif_gpu_PMI_STATUS_CNTL_swds -#define nbif_gpu_PMI_STATUS_CNTL_swds__POWER_STATE__SHIFT 0x00000000 -#define nbif_gpu_PMI_STATUS_CNTL_swds__NO_SOFT_RESET__SHIFT 0x00000003 -#define nbif_gpu_PMI_STATUS_CNTL_swds__PME_EN__SHIFT 0x00000008 -#define nbif_gpu_PMI_STATUS_CNTL_swds__DATA_SELECT__SHIFT 0x00000009 -#define nbif_gpu_PMI_STATUS_CNTL_swds__DATA_SCALE__SHIFT 0x0000000d -#define nbif_gpu_PMI_STATUS_CNTL_swds__PME_STATUS__SHIFT 0x0000000f -#define nbif_gpu_PMI_STATUS_CNTL_swds__B2_B3_SUPPORT__SHIFT 0x00000016 -#define nbif_gpu_PMI_STATUS_CNTL_swds__BUS_PWR_EN__SHIFT 0x00000017 -#define nbif_gpu_PMI_STATUS_CNTL_swds__PMI_DATA__SHIFT 0x00000018 - -// nbif_gpu_PCIE_CAP_LIST_swds -#define nbif_gpu_PCIE_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_PCIE_CAP_swds -#define nbif_gpu_PCIE_CAP_swds__VERSION__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CAP_swds__DEVICE_TYPE__SHIFT 0x00000004 -#define nbif_gpu_PCIE_CAP_swds__SLOT_IMPLEMENTED__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CAP_swds__INT_MESSAGE_NUM__SHIFT 0x00000009 - -// nbif_gpu_DEVICE_CAP_swds -#define nbif_gpu_DEVICE_CAP_swds__MAX_PAYLOAD_SUPPORT__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CAP_swds__PHANTOM_FUNC__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_CAP_swds__EXTENDED_TAG__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CAP_swds__L0S_ACCEPTABLE_LATENCY__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CAP_swds__L1_ACCEPTABLE_LATENCY__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CAP_swds__ROLE_BASED_ERR_REPORTING__SHIFT 0x0000000f -#define nbif_gpu_DEVICE_CAP_swds__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x00000012 -#define nbif_gpu_DEVICE_CAP_swds__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x0000001a -#define nbif_gpu_DEVICE_CAP_swds__FLR_CAPABLE__SHIFT 0x0000001c - -// nbif_gpu_DEVICE_CNTL_swds -#define nbif_gpu_DEVICE_CNTL_swds__CORR_ERR_EN__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CNTL_swds__NON_FATAL_ERR_EN__SHIFT 0x00000001 -#define nbif_gpu_DEVICE_CNTL_swds__FATAL_ERR_EN__SHIFT 0x00000002 -#define nbif_gpu_DEVICE_CNTL_swds__USR_REPORT_EN__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_CNTL_swds__RELAXED_ORD_EN__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CNTL_swds__MAX_PAYLOAD_SIZE__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CNTL_swds__EXTENDED_TAG_EN__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CNTL_swds__PHANTOM_FUNC_EN__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CNTL_swds__AUX_POWER_PM_EN__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CNTL_swds__NO_SNOOP_EN__SHIFT 0x0000000b -#define nbif_gpu_DEVICE_CNTL_swds__MAX_READ_REQUEST_SIZE__SHIFT 0x0000000c -#define nbif_gpu_DEVICE_CNTL_swds__BRIDGE_CFG_RETRY_EN__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_STATUS_swds -#define nbif_gpu_DEVICE_STATUS_swds__CORR_ERR__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_STATUS_swds__NON_FATAL_ERR__SHIFT 0x00000001 -#define nbif_gpu_DEVICE_STATUS_swds__FATAL_ERR__SHIFT 0x00000002 -#define nbif_gpu_DEVICE_STATUS_swds__USR_DETECTED__SHIFT 0x00000003 -#define nbif_gpu_DEVICE_STATUS_swds__AUX_PWR__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_STATUS_swds__TRANSACTIONS_PEND__SHIFT 0x00000005 - -// nbif_gpu_LINK_CAP_swds -#define nbif_gpu_LINK_CAP_swds__LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_CAP_swds__LINK_WIDTH__SHIFT 0x00000004 -#define nbif_gpu_LINK_CAP_swds__PM_SUPPORT__SHIFT 0x0000000a -#define nbif_gpu_LINK_CAP_swds__L0S_EXIT_LATENCY__SHIFT 0x0000000c -#define nbif_gpu_LINK_CAP_swds__L1_EXIT_LATENCY__SHIFT 0x0000000f -#define nbif_gpu_LINK_CAP_swds__CLOCK_POWER_MANAGEMENT__SHIFT 0x00000012 -#define nbif_gpu_LINK_CAP_swds__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x00000013 -#define nbif_gpu_LINK_CAP_swds__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x00000014 -#define nbif_gpu_LINK_CAP_swds__LINK_BW_NOTIFICATION_CAP__SHIFT 0x00000015 -#define nbif_gpu_LINK_CAP_swds__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x00000016 -#define nbif_gpu_LINK_CAP_swds__PORT_NUMBER__SHIFT 0x00000018 - -// nbif_gpu_LINK_CNTL_swds -#define nbif_gpu_LINK_CNTL_swds__PM_CONTROL__SHIFT 0x00000000 -#define nbif_gpu_LINK_CNTL_swds__READ_CPL_BOUNDARY__SHIFT 0x00000003 -#define nbif_gpu_LINK_CNTL_swds__LINK_DIS__SHIFT 0x00000004 -#define nbif_gpu_LINK_CNTL_swds__RETRAIN_LINK__SHIFT 0x00000005 -#define nbif_gpu_LINK_CNTL_swds__COMMON_CLOCK_CFG__SHIFT 0x00000006 -#define nbif_gpu_LINK_CNTL_swds__EXTENDED_SYNC__SHIFT 0x00000007 -#define nbif_gpu_LINK_CNTL_swds__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x00000008 -#define nbif_gpu_LINK_CNTL_swds__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x00000009 -#define nbif_gpu_LINK_CNTL_swds__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0x0000000a -#define nbif_gpu_LINK_CNTL_swds__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0x0000000b - -// nbif_gpu_LINK_STATUS_swds -#define nbif_gpu_LINK_STATUS_swds__CURRENT_LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_STATUS_swds__NEGOTIATED_LINK_WIDTH__SHIFT 0x00000004 -#define nbif_gpu_LINK_STATUS_swds__LINK_TRAINING__SHIFT 0x0000000b -#define nbif_gpu_LINK_STATUS_swds__SLOT_CLOCK_CFG__SHIFT 0x0000000c -#define nbif_gpu_LINK_STATUS_swds__DL_ACTIVE__SHIFT 0x0000000d -#define nbif_gpu_LINK_STATUS_swds__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x0000000e -#define nbif_gpu_LINK_STATUS_swds__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x0000000f - -// nbif_gpu_SLOT_CAP_swds -#define nbif_gpu_SLOT_CAP_swds__ATTN_BUTTON_PRESENT__SHIFT 0x00000000 -#define nbif_gpu_SLOT_CAP_swds__PWR_CONTROLLER_PRESENT__SHIFT 0x00000001 -#define nbif_gpu_SLOT_CAP_swds__MRL_SENSOR_PRESENT__SHIFT 0x00000002 -#define nbif_gpu_SLOT_CAP_swds__ATTN_INDICATOR_PRESENT__SHIFT 0x00000003 -#define nbif_gpu_SLOT_CAP_swds__PWR_INDICATOR_PRESENT__SHIFT 0x00000004 -#define nbif_gpu_SLOT_CAP_swds__HOTPLUG_SURPRISE__SHIFT 0x00000005 -#define nbif_gpu_SLOT_CAP_swds__HOTPLUG_CAPABLE__SHIFT 0x00000006 -#define nbif_gpu_SLOT_CAP_swds__SLOT_PWR_LIMIT_VALUE__SHIFT 0x00000007 -#define nbif_gpu_SLOT_CAP_swds__SLOT_PWR_LIMIT_SCALE__SHIFT 0x0000000f -#define nbif_gpu_SLOT_CAP_swds__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x00000011 -#define nbif_gpu_SLOT_CAP_swds__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x00000012 -#define nbif_gpu_SLOT_CAP_swds__PHYSICAL_SLOT_NUM__SHIFT 0x00000013 - -// nbif_gpu_SLOT_CNTL_swds -#define nbif_gpu_SLOT_CNTL_swds__ATTN_BUTTON_PRESSED_EN__SHIFT 0x00000000 -#define nbif_gpu_SLOT_CNTL_swds__PWR_FAULT_DETECTED_EN__SHIFT 0x00000001 -#define nbif_gpu_SLOT_CNTL_swds__MRL_SENSOR_CHANGED_EN__SHIFT 0x00000002 -#define nbif_gpu_SLOT_CNTL_swds__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x00000003 -#define nbif_gpu_SLOT_CNTL_swds__COMMAND_COMPLETED_INTR_EN__SHIFT 0x00000004 -#define nbif_gpu_SLOT_CNTL_swds__HOTPLUG_INTR_EN__SHIFT 0x00000005 -#define nbif_gpu_SLOT_CNTL_swds__ATTN_INDICATOR_CNTL__SHIFT 0x00000006 -#define nbif_gpu_SLOT_CNTL_swds__PWR_INDICATOR_CNTL__SHIFT 0x00000008 -#define nbif_gpu_SLOT_CNTL_swds__PWR_CONTROLLER_CNTL__SHIFT 0x0000000a -#define nbif_gpu_SLOT_CNTL_swds__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0x0000000b -#define nbif_gpu_SLOT_CNTL_swds__DL_STATE_CHANGED_EN__SHIFT 0x0000000c - -// nbif_gpu_SLOT_STATUS_swds -#define nbif_gpu_SLOT_STATUS_swds__ATTN_BUTTON_PRESSED__SHIFT 0x00000000 -#define nbif_gpu_SLOT_STATUS_swds__PWR_FAULT_DETECTED__SHIFT 0x00000001 -#define nbif_gpu_SLOT_STATUS_swds__MRL_SENSOR_CHANGED__SHIFT 0x00000002 -#define nbif_gpu_SLOT_STATUS_swds__PRESENCE_DETECT_CHANGED__SHIFT 0x00000003 -#define nbif_gpu_SLOT_STATUS_swds__COMMAND_COMPLETED__SHIFT 0x00000004 -#define nbif_gpu_SLOT_STATUS_swds__MRL_SENSOR_STATE__SHIFT 0x00000005 -#define nbif_gpu_SLOT_STATUS_swds__PRESENCE_DETECT_STATE__SHIFT 0x00000006 -#define nbif_gpu_SLOT_STATUS_swds__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x00000007 -#define nbif_gpu_SLOT_STATUS_swds__DL_STATE_CHANGED__SHIFT 0x00000008 - -// nbif_gpu_DEVICE_CAP2_swds -#define nbif_gpu_DEVICE_CAP2_swds__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CAP2_swds__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CAP2_swds__ARI_FORWARDING_SUPPORTED__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CAP2_swds__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CAP2_swds__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x00000007 -#define nbif_gpu_DEVICE_CAP2_swds__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CAP2_swds__CAS128_CMPLT_SUPPORTED__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CAP2_swds__NO_RO_ENABLED_P2P_PASSING__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CAP2_swds__LTR_SUPPORTED__SHIFT 0x0000000b -#define nbif_gpu_DEVICE_CAP2_swds__TPH_CPLR_SUPPORTED__SHIFT 0x0000000c -#define nbif_gpu_DEVICE_CAP2_swds__OBFF_SUPPORTED__SHIFT 0x00000012 -#define nbif_gpu_DEVICE_CAP2_swds__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x00000014 -#define nbif_gpu_DEVICE_CAP2_swds__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x00000015 -#define nbif_gpu_DEVICE_CAP2_swds__MAX_END_END_TLP_PREFIXES__SHIFT 0x00000016 - -// nbif_gpu_DEVICE_CNTL2_swds -#define nbif_gpu_DEVICE_CNTL2_swds__CPL_TIMEOUT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_DEVICE_CNTL2_swds__CPL_TIMEOUT_DIS__SHIFT 0x00000004 -#define nbif_gpu_DEVICE_CNTL2_swds__ARI_FORWARDING_EN__SHIFT 0x00000005 -#define nbif_gpu_DEVICE_CNTL2_swds__ATOMICOP_REQUEST_EN__SHIFT 0x00000006 -#define nbif_gpu_DEVICE_CNTL2_swds__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x00000007 -#define nbif_gpu_DEVICE_CNTL2_swds__IDO_REQUEST_ENABLE__SHIFT 0x00000008 -#define nbif_gpu_DEVICE_CNTL2_swds__IDO_COMPLETION_ENABLE__SHIFT 0x00000009 -#define nbif_gpu_DEVICE_CNTL2_swds__LTR_EN__SHIFT 0x0000000a -#define nbif_gpu_DEVICE_CNTL2_swds__OBFF_EN__SHIFT 0x0000000d -#define nbif_gpu_DEVICE_CNTL2_swds__END_END_TLP_PREFIX_BLOCKING__SHIFT 0x0000000f - -// nbif_gpu_DEVICE_STATUS2_swds -#define nbif_gpu_DEVICE_STATUS2_swds__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_LINK_CAP2_swds -#define nbif_gpu_LINK_CAP2_swds__SUPPORTED_LINK_SPEED__SHIFT 0x00000001 -#define nbif_gpu_LINK_CAP2_swds__CROSSLINK_SUPPORTED__SHIFT 0x00000008 -#define nbif_gpu_LINK_CAP2_swds__RESERVED__SHIFT 0x00000009 - -// nbif_gpu_LINK_CNTL2_swds -#define nbif_gpu_LINK_CNTL2_swds__TARGET_LINK_SPEED__SHIFT 0x00000000 -#define nbif_gpu_LINK_CNTL2_swds__ENTER_COMPLIANCE__SHIFT 0x00000004 -#define nbif_gpu_LINK_CNTL2_swds__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x00000005 -#define nbif_gpu_LINK_CNTL2_swds__SELECTABLE_DEEMPHASIS__SHIFT 0x00000006 -#define nbif_gpu_LINK_CNTL2_swds__XMIT_MARGIN__SHIFT 0x00000007 -#define nbif_gpu_LINK_CNTL2_swds__ENTER_MOD_COMPLIANCE__SHIFT 0x0000000a -#define nbif_gpu_LINK_CNTL2_swds__COMPLIANCE_SOS__SHIFT 0x0000000b -#define nbif_gpu_LINK_CNTL2_swds__COMPLIANCE_DEEMPHASIS__SHIFT 0x0000000c - -// nbif_gpu_LINK_STATUS2_swds -#define nbif_gpu_LINK_STATUS2_swds__CUR_DEEMPHASIS_LEVEL__SHIFT 0x00000000 -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_COMPLETE__SHIFT 0x00000001 -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x00000002 -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x00000003 -#define nbif_gpu_LINK_STATUS2_swds__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x00000004 -#define nbif_gpu_LINK_STATUS2_swds__LINK_EQUALIZATION_REQUEST__SHIFT 0x00000005 - -// nbif_gpu_SLOT_CAP2_swds -#define nbif_gpu_SLOT_CAP2_swds__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_SLOT_CNTL2_swds -#define nbif_gpu_SLOT_CNTL2_swds__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_SLOT_STATUS2_swds -#define nbif_gpu_SLOT_STATUS2_swds__RESERVED__SHIFT 0x00000000 - -// nbif_gpu_MSI_CAP_LIST_swds -#define nbif_gpu_MSI_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_MSI_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_MSI_MSG_CNTL_swds -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_EN__SHIFT 0x00000000 -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_MULTI_CAP__SHIFT 0x00000001 -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_MULTI_EN__SHIFT 0x00000004 -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_64BIT__SHIFT 0x00000007 -#define nbif_gpu_MSI_MSG_CNTL_swds__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x00000008 - -// nbif_gpu_MSI_MSG_ADDR_LO_swds -#define nbif_gpu_MSI_MSG_ADDR_LO_swds__MSI_MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_MSI_MSG_ADDR_HI_swds -#define nbif_gpu_MSI_MSG_ADDR_HI_swds__MSI_MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_MSI_MSG_DATA_64_swds -#define nbif_gpu_MSI_MSG_DATA_64_swds__MSI_DATA_64__SHIFT 0x00000000 - -// nbif_gpu_MSI_MSG_DATA_swds -#define nbif_gpu_MSI_MSG_DATA_swds__MSI_DATA__SHIFT 0x00000000 - -// nbif_gpu_SSID_CAP_LIST_swds -#define nbif_gpu_SSID_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_SSID_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000008 - -// nbif_gpu_SSID_CAP_swds -#define nbif_gpu_SSID_CAP_swds__SUBSYSTEM_VENDOR_ID__SHIFT 0x00000000 -#define nbif_gpu_SSID_CAP_swds__SUBSYSTEM_ID__SHIFT 0x00000010 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds__VSEC_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds__VSEC_REV__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds__VSEC_LENGTH__SHIFT 0x00000014 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC1_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC1_swds__SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VENDOR_SPECIFIC2_swds -#define nbif_gpu_PCIE_VENDOR_SPECIFIC2_swds__SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__EXT_VC_COUNT__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x00000004 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__REF_CLK__SHIFT 0x00000008 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0x0000000a - -// nbif_gpu_PCIE_PORT_VC_CAP_REG2_swds -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_swds__VC_ARB_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PORT_VC_CAP_REG2_swds__VC_ARB_TABLE_OFFSET__SHIFT 0x00000018 - -// nbif_gpu_PCIE_PORT_VC_CNTL_swds -#define nbif_gpu_PCIE_PORT_VC_CNTL_swds__LOAD_VC_ARB_TABLE__SHIFT 0x00000000 -#define nbif_gpu_PCIE_PORT_VC_CNTL_swds__VC_ARB_SELECT__SHIFT 0x00000001 - -// nbif_gpu_PCIE_PORT_VC_STATUS_swds -#define nbif_gpu_PCIE_PORT_VC_STATUS_swds__VC_ARB_TABLE_STATUS__SHIFT 0x00000000 - -// nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__PORT_ARB_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__REJECT_SNOOP_TRANS__SHIFT 0x0000000f -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__MAX_TIME_SLOTS__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds__PORT_ARB_TABLE_OFFSET__SHIFT 0x00000018 - -// nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__TC_VC_MAP_TC0__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__TC_VC_MAP_TC1_7__SHIFT 0x00000001 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__LOAD_PORT_ARB_TABLE__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__PORT_ARB_SELECT__SHIFT 0x00000011 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__VC_ID__SHIFT 0x00000018 -#define nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds__VC_ENABLE__SHIFT 0x0000001f - -// nbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds__PORT_ARB_TABLE_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds__VC_NEGOTIATION_PENDING__SHIFT 0x00000001 - -// nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__PORT_ARB_CAP__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__REJECT_SNOOP_TRANS__SHIFT 0x0000000f -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__MAX_TIME_SLOTS__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds__PORT_ARB_TABLE_OFFSET__SHIFT 0x00000018 - -// nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__TC_VC_MAP_TC0__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__TC_VC_MAP_TC1_7__SHIFT 0x00000001 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__LOAD_PORT_ARB_TABLE__SHIFT 0x00000010 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__PORT_ARB_SELECT__SHIFT 0x00000011 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__VC_ID__SHIFT 0x00000018 -#define nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds__VC_ENABLE__SHIFT 0x0000001f - -// nbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds__PORT_ARB_TABLE_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds__VC_NEGOTIATION_PENDING__SHIFT 0x00000001 - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds__SERIAL_NUMBER_LO__SHIFT 0x00000000 - -// nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds -#define nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds__SERIAL_NUMBER_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__DLP_ERR_STATUS__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__SURPDN_ERR_STATUS__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__PSN_ERR_STATUS__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__FC_ERR_STATUS__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__CPL_TIMEOUT_STATUS__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__CPL_ABORT_ERR_STATUS__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__UNEXP_CPL_STATUS__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__RCV_OVFL_STATUS__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__MAL_TLP_STATUS__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__ECRC_ERR_STATUS__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__UNSUPP_REQ_ERR_STATUS__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__ACS_VIOLATION_STATUS__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__UNCORR_INT_ERR_STATUS__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__MC_BLOCKED_TLP_STATUS__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x00000019 - -// nbif_gpu_PCIE_UNCORR_ERR_MASK_swds -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__DLP_ERR_MASK__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__SURPDN_ERR_MASK__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__PSN_ERR_MASK__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__FC_ERR_MASK__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__CPL_TIMEOUT_MASK__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__CPL_ABORT_ERR_MASK__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__UNEXP_CPL_MASK__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__RCV_OVFL_MASK__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__MAL_TLP_MASK__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__ECRC_ERR_MASK__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__UNSUPP_REQ_ERR_MASK__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__ACS_VIOLATION_MASK__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__UNCORR_INT_ERR_MASK__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__MC_BLOCKED_TLP_MASK__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_MASK_swds__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x00000019 - -// nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__DLP_ERR_SEVERITY__SHIFT 0x00000004 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__SURPDN_ERR_SEVERITY__SHIFT 0x00000005 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__PSN_ERR_SEVERITY__SHIFT 0x0000000c -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__FC_ERR_SEVERITY__SHIFT 0x0000000d -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__CPL_TIMEOUT_SEVERITY__SHIFT 0x0000000e -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__CPL_ABORT_ERR_SEVERITY__SHIFT 0x0000000f -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__UNEXP_CPL_SEVERITY__SHIFT 0x00000010 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__RCV_OVFL_SEVERITY__SHIFT 0x00000011 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__MAL_TLP_SEVERITY__SHIFT 0x00000012 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__ECRC_ERR_SEVERITY__SHIFT 0x00000013 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x00000014 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__ACS_VIOLATION_SEVERITY__SHIFT 0x00000015 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__UNCORR_INT_ERR_SEVERITY__SHIFT 0x00000016 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x00000017 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x00000018 -#define nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x00000019 - -// nbif_gpu_PCIE_CORR_ERR_STATUS_swds -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__RCV_ERR_STATUS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__BAD_TLP_STATUS__SHIFT 0x00000006 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__BAD_DLLP_STATUS__SHIFT 0x00000007 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0x0000000c -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x0000000d -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__CORR_INT_ERR_STATUS__SHIFT 0x0000000e -#define nbif_gpu_PCIE_CORR_ERR_STATUS_swds__HDR_LOG_OVFL_STATUS__SHIFT 0x0000000f - -// nbif_gpu_PCIE_CORR_ERR_MASK_swds -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__RCV_ERR_MASK__SHIFT 0x00000000 -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__BAD_TLP_MASK__SHIFT 0x00000006 -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__BAD_DLLP_MASK__SHIFT 0x00000007 -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x00000008 -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0x0000000c -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0x0000000d -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__CORR_INT_ERR_MASK__SHIFT 0x0000000e -#define nbif_gpu_PCIE_CORR_ERR_MASK_swds__HDR_LOG_OVFL_MASK__SHIFT 0x0000000f - -// nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__FIRST_ERR_PTR__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_GEN_CAP__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_GEN_EN__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_CHECK_CAP__SHIFT 0x00000007 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__ECRC_CHECK_EN__SHIFT 0x00000008 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__MULTI_HDR_RECD_CAP__SHIFT 0x00000009 -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__MULTI_HDR_RECD_EN__SHIFT 0x0000000a -#define nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds__TLP_PREFIX_LOG_PRESENT__SHIFT 0x0000000b - -// nbif_gpu_PCIE_HDR_LOG0_swds -#define nbif_gpu_PCIE_HDR_LOG0_swds__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG1_swds -#define nbif_gpu_PCIE_HDR_LOG1_swds__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG2_swds -#define nbif_gpu_PCIE_HDR_LOG2_swds__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_HDR_LOG3_swds -#define nbif_gpu_PCIE_HDR_LOG3_swds__TLP_HDR__SHIFT 0x00000000 - -// nbif_gpu_PCIE_ROOT_ERR_CMD_swds -#define nbif_gpu_PCIE_ROOT_ERR_CMD_swds__CORR_ERR_REP_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ROOT_ERR_CMD_swds__NONFATAL_ERR_REP_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ROOT_ERR_CMD_swds__FATAL_ERR_REP_EN__SHIFT 0x00000002 - -// nbif_gpu_PCIE_ROOT_ERR_STATUS_swds -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__ERR_CORR_RCVD__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__MULT_ERR_CORR_RCVD__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x00000002 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x00000003 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x00000004 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__FATAL_ERROR_MSG_RCVD__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ROOT_ERR_STATUS_swds__ADV_ERR_INT_MSG_NUM__SHIFT 0x0000001b - -// nbif_gpu_PCIE_ERR_SRC_ID_swds -#define nbif_gpu_PCIE_ERR_SRC_ID_swds__ERR_CORR_SRC_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ERR_SRC_ID_swds__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x00000010 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG0_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG0_swds__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG1_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG1_swds__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG2_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG2_swds__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_TLP_PREFIX_LOG3_swds -#define nbif_gpu_PCIE_TLP_PREFIX_LOG3_swds__TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_LINK_CNTL3_swds -#define nbif_gpu_PCIE_LINK_CNTL3_swds__PERFORM_EQUALIZATION__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LINK_CNTL3_swds__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_LINK_CNTL3_swds__RESERVED__SHIFT 0x00000002 - -// nbif_gpu_PCIE_LANE_ERROR_STATUS_swds -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_swds__LANE_ERROR_STATUS_BITS__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_ERROR_STATUS_swds__RESERVED__SHIFT 0x00000010 - -// nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x00000000 -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT \ - 0x00000004 -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_TX_PRESET__SHIFT 0x00000008 -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0000000c -#define nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds__RESERVED__SHIFT 0x0000000f - -// nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds__CAP_ID__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds__CAP_VER__SHIFT 0x00000010 -#define nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds__NEXT_PTR__SHIFT 0x00000014 - -// nbif_gpu_PCIE_ACS_CAP_swds -#define nbif_gpu_PCIE_ACS_CAP_swds__SOURCE_VALIDATION__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ACS_CAP_swds__TRANSLATION_BLOCKING__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ACS_CAP_swds__P2P_REQUEST_REDIRECT__SHIFT 0x00000002 -#define nbif_gpu_PCIE_ACS_CAP_swds__P2P_COMPLETION_REDIRECT__SHIFT 0x00000003 -#define nbif_gpu_PCIE_ACS_CAP_swds__UPSTREAM_FORWARDING__SHIFT 0x00000004 -#define nbif_gpu_PCIE_ACS_CAP_swds__P2P_EGRESS_CONTROL__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ACS_CAP_swds__DIRECT_TRANSLATED_P2P__SHIFT 0x00000006 -#define nbif_gpu_PCIE_ACS_CAP_swds__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_ACS_CNTL_swds -#define nbif_gpu_PCIE_ACS_CNTL_swds__SOURCE_VALIDATION_EN__SHIFT 0x00000000 -#define nbif_gpu_PCIE_ACS_CNTL_swds__TRANSLATION_BLOCKING_EN__SHIFT 0x00000001 -#define nbif_gpu_PCIE_ACS_CNTL_swds__P2P_REQUEST_REDIRECT_EN__SHIFT 0x00000002 -#define nbif_gpu_PCIE_ACS_CNTL_swds__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x00000003 -#define nbif_gpu_PCIE_ACS_CNTL_swds__UPSTREAM_FORWARDING_EN__SHIFT 0x00000004 -#define nbif_gpu_PCIE_ACS_CNTL_swds__P2P_EGRESS_CONTROL_EN__SHIFT 0x00000005 -#define nbif_gpu_PCIE_ACS_CNTL_swds__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x00000006 - -// nbif_gpu_SHADOW_COMMAND -#define nbif_gpu_SHADOW_COMMAND__IOEN_UP__SHIFT 0x00000000 -#define nbif_gpu_SHADOW_COMMAND__MEMEN_UP__SHIFT 0x00000001 - -// nbif_gpu_SHADOW_BASE_ADDR_1 -#define nbif_gpu_SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x00000000 - -// nbif_gpu_SHADOW_BASE_ADDR_2 -#define nbif_gpu_SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x00000000 - -// nbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY -#define nbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x00000008 -#define nbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x00000010 - -// nbif_gpu_SHADOW_IO_BASE_LIMIT -#define nbif_gpu_SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x00000004 -#define nbif_gpu_SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0x0000000c - -// nbif_gpu_SHADOW_MEM_BASE_LIMIT -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x00000000 -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x00000004 -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x00000010 -#define nbif_gpu_SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x00000014 - -// nbif_gpu_SHADOW_PREF_BASE_LIMIT -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x00000000 -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x00000004 -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x00000010 -#define nbif_gpu_SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x00000014 - -// nbif_gpu_SHADOW_PREF_BASE_UPPER -#define nbif_gpu_SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x00000000 - -// nbif_gpu_SHADOW_PREF_LIMIT_UPPER -#define nbif_gpu_SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x00000000 - -// nbif_gpu_SHADOW_IO_BASE_LIMIT_HI -#define nbif_gpu_SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x00000000 -#define nbif_gpu_SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x00000010 - -// nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x00000002 -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x00000003 -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x00000004 -#define nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x00000006 - -// nbif_gpu_SUC_INDEX -#define nbif_gpu_SUC_INDEX__SUC_INDEX__SHIFT 0x00000000 - -// nbif_gpu_SUC_DATA -#define nbif_gpu_SUC_DATA__SUC_DATA__SHIFT 0x00000000 - -// nbif_gpu_EP_PCIE_SCRATCH -#define nbif_gpu_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x00000000 - -// nbif_gpu_EP_PCIE_HW_DEBUG -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define nbif_gpu_EP_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f - -// nbif_gpu_EP_PCIE_CNTL -#define nbif_gpu_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x00000007 -#define nbif_gpu_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x00000008 -#define nbif_gpu_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x0000001e - -// nbif_gpu_EP_PCIE_INT_CNTL -#define nbif_gpu_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x00000001 -#define nbif_gpu_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x00000002 -#define nbif_gpu_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x00000003 -#define nbif_gpu_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x00000004 -#define nbif_gpu_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x00000006 - -// nbif_gpu_EP_PCIE_INT_STATUS -#define nbif_gpu_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x00000001 -#define nbif_gpu_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x00000002 -#define nbif_gpu_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x00000003 -#define nbif_gpu_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x00000004 -#define nbif_gpu_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x00000006 - -// nbif_gpu_EP_PCIE_RX_CNTL2 -#define nbif_gpu_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x00000000 - -// nbif_gpu_EP_PCIE_BUS_CNTL -#define nbif_gpu_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x00000007 - -// nbif_gpu_EP_PCIE_CFG_CNTL -#define nbif_gpu_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x00000001 -#define nbif_gpu_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x00000002 - -// nbif_gpu_EP_PCIE_OBFF_CNTL -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x00000001 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x00000002 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x00000003 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x00000004 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x00000008 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0x0000000c -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x00000010 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x00000011 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x00000012 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x00000013 -#define nbif_gpu_EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x00000014 - -// nbif_gpu_EP_PCIE_TX_LTR_CNTL -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x00000003 -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x00000006 -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x00000007 -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0x0000000a -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0x0000000d -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0x0000000e -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0x0000000f -#define nbif_gpu_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x00000010 - -// nbif_gpu_EP_PCIE_STRAP_MISC -#define nbif_gpu_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x0000001d - -// nbif_gpu_EP_PCIE_STRAP_MISC2 -#define nbif_gpu_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x00000004 - -// nbif_gpu_EP_PCIE_STRAP_PI - -// nbif_gpu_EP_PCIE_F0_DPA_CAP -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x00000008 -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0x0000000c -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x00000010 -#define nbif_gpu_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x00000018 - -// nbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR -#define nbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x00000000 - -// nbif_gpu_EP_PCIE_F0_DPA_CNTL -#define nbif_gpu_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x00000008 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 -#define nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 - -// nbif_gpu_EP_PCIE_PME_CONTROL -#define nbif_gpu_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x00000000 - -// nbif_gpu_EP_PCIEP_RESERVED -#define nbif_gpu_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x00000000 - -// nbif_gpu_EP_PCIEP_HW_DEBUG -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e -#define nbif_gpu_EP_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f - -// nbif_gpu_EP_PCIE_TX_CNTL -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0x0000000a -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0x0000000c -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x00000018 -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x00000019 -#define nbif_gpu_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x0000001a - -// nbif_gpu_EP_PCIE_TX_REQUESTER_ID -#define nbif_gpu_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x00000003 -#define nbif_gpu_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x00000008 - -// nbif_gpu_EP_PCIE_ERR_CNTL -#define nbif_gpu_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x00000008 -#define nbif_gpu_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x00000011 -#define nbif_gpu_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x00000012 -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x00000018 -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x00000019 -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x0000001a -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x0000001b -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x0000001c -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x0000001d -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x0000001e -#define nbif_gpu_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x0000001f - -// nbif_gpu_EP_PCIE_RX_CNTL -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x00000008 -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x00000009 -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x00000014 -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x00000015 -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x00000016 -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x00000018 -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x00000019 -#define nbif_gpu_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x0000001a - -// nbif_gpu_EP_PCIE_LC_SPEED_CNTL -#define nbif_gpu_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x00000000 -#define nbif_gpu_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x00000001 - -// nbif_gpu_A2S_CNTL_CL0 -#define nbif_gpu_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x00000002 -#define nbif_gpu_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x00000004 -#define nbif_gpu_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0x0000000e -#define nbif_gpu_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x00000012 -#define nbif_gpu_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x00000014 - -// nbif_gpu_A2S_CNTL_CL1 -#define nbif_gpu_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x00000002 -#define nbif_gpu_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x00000004 -#define nbif_gpu_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_CL1__DATERR_MAP__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0x0000000e -#define nbif_gpu_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x00000012 -#define nbif_gpu_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x00000014 - -// nbif_gpu_A2S_CNTL_CL2 -#define nbif_gpu_A2S_CNTL_CL2__NSNOOP_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT 0x00000002 -#define nbif_gpu_A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT 0x00000004 -#define nbif_gpu_A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_CL2__BLKLVL_MAP__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_CL2__DATERR_MAP__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT 0x0000000e -#define nbif_gpu_A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_CL2__RESP_WR_MAP__SHIFT 0x00000012 -#define nbif_gpu_A2S_CNTL_CL2__RESP_RD_MAP__SHIFT 0x00000014 - -// nbif_gpu_A2S_CNTL_CL3 -#define nbif_gpu_A2S_CNTL_CL3__NSNOOP_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT 0x00000002 -#define nbif_gpu_A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT 0x00000004 -#define nbif_gpu_A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_CL3__BLKLVL_MAP__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_CL3__DATERR_MAP__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT 0x0000000e -#define nbif_gpu_A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_CL3__RESP_WR_MAP__SHIFT 0x00000012 -#define nbif_gpu_A2S_CNTL_CL3__RESP_RD_MAP__SHIFT 0x00000014 - -// nbif_gpu_A2S_CNTL_CL4 -#define nbif_gpu_A2S_CNTL_CL4__NSNOOP_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT 0x00000002 -#define nbif_gpu_A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT 0x00000004 -#define nbif_gpu_A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_CL4__BLKLVL_MAP__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_CL4__DATERR_MAP__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT 0x0000000e -#define nbif_gpu_A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_CL4__RESP_WR_MAP__SHIFT 0x00000012 -#define nbif_gpu_A2S_CNTL_CL4__RESP_RD_MAP__SHIFT 0x00000014 - -// nbif_gpu_A2S_CNTL_SW0 -#define nbif_gpu_A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT 0x00000003 -#define nbif_gpu_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT 0x00000007 -#define nbif_gpu_A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x00000009 -#define nbif_gpu_A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x0000000b -#define nbif_gpu_A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x00000018 - -// nbif_gpu_A2S_CNTL_SW1 -#define nbif_gpu_A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT 0x00000003 -#define nbif_gpu_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT 0x00000007 -#define nbif_gpu_A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x00000009 -#define nbif_gpu_A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x0000000b -#define nbif_gpu_A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x00000018 - -// nbif_gpu_A2S_CNTL_SW2 -#define nbif_gpu_A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT 0x00000003 -#define nbif_gpu_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x00000006 -#define nbif_gpu_A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT 0x00000007 -#define nbif_gpu_A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT 0x00000008 -#define nbif_gpu_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x00000009 -#define nbif_gpu_A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x0000000a -#define nbif_gpu_A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x0000000b -#define nbif_gpu_A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x0000000c -#define nbif_gpu_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x00000010 -#define nbif_gpu_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x00000018 - -// nbif_gpu_A2S_CNTL2_SEC_CL0 -#define nbif_gpu_A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL2_SEC_CL0__DBGMSK_MAP__SHIFT 0x00000003 - -// nbif_gpu_A2S_CNTL2_SEC_CL1 -#define nbif_gpu_A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL2_SEC_CL1__DBGMSK_MAP__SHIFT 0x00000003 - -// nbif_gpu_A2S_CNTL2_SEC_CL2 -#define nbif_gpu_A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL2_SEC_CL2__DBGMSK_MAP__SHIFT 0x00000003 - -// nbif_gpu_A2S_CNTL2_SEC_CL3 -#define nbif_gpu_A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL2_SEC_CL3__DBGMSK_MAP__SHIFT 0x00000003 - -// nbif_gpu_A2S_CNTL2_SEC_CL4 -#define nbif_gpu_A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT 0x00000000 -#define nbif_gpu_A2S_CNTL2_SEC_CL4__DBGMSK_MAP__SHIFT 0x00000003 - -// nbif_gpu_NGDC_MGCG_CTRL -#define nbif_gpu_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x00000000 -#define nbif_gpu_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x00000001 -#define nbif_gpu_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x00000002 - -// nbif_gpu_A2S_MISC_CNTL -#define nbif_gpu_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x00000000 -#define nbif_gpu_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x00000002 - -// nbif_gpu_NGDC_SDP_PORT_CTRL -#define nbif_gpu_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x00000000 - -// nbif_gpu_BIF_SDMA0_DOORBELL_RANGE -#define nbif_gpu_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x00000002 -#define nbif_gpu_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x00000010 - -// nbif_gpu_BIF_SDMA1_DOORBELL_RANGE -#define nbif_gpu_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x00000002 -#define nbif_gpu_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x00000010 - -// nbif_gpu_BIF_IH_DOORBELL_RANGE -#define nbif_gpu_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x00000002 -#define nbif_gpu_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x00000010 - -// nbif_gpu_BIF_MMSCH0_DOORBELL_RANGE -#define nbif_gpu_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x00000002 -#define nbif_gpu_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x00000010 - -// nbif_gpu_S2A_MISC_CNTL -#define nbif_gpu_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x00000000 -#define nbif_gpu_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x00000001 -#define nbif_gpu_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x00000002 - -// nbif_gpu_GDC_RAS_LEAF0_CTRL -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_GDC_RAS_LEAF1_CTRL -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_GDC_RAS_LEAF2_CTRL -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_GDC_RAS_LEAF3_CTRL -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_GDC_RAS_LEAF4_CTRL -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_GDC_RAS_LEAF5_CTRL -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x00000000 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x00000001 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x00000002 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x00000004 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x00000005 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x00000006 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x00000010 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x00000011 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x00000012 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x00000013 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x00000014 -#define nbif_gpu_GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x00000015 - -// nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG0 -#define nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG1 -#define nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG0 -#define nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG1 -#define nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_Req_BurstTarget_REG0 -#define nbif_gpu_SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_Req_BurstTarget_REG1 -#define nbif_gpu_SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_Req_TimeSlot_REG0 -#define nbif_gpu_SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_Req_TimeSlot_REG1 -#define nbif_gpu_SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG0 -#define nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x00000000 - -// nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG1 -#define nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x00000000 - -// nbif_gpu_SION_CNTL_REG0 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x00000000 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x00000001 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x00000002 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x00000003 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x00000004 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x00000005 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x00000006 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x00000007 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x00000008 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x00000009 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0x0000000a -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0x0000000b -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0x0000000c -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0x0000000d -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0x0000000e -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0x0000000f -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x00000010 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x00000011 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x00000012 -#define nbif_gpu_SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x00000013 - -// nbif_gpu_SION_CNTL_REG1 -#define nbif_gpu_SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x00000000 -#define nbif_gpu_SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x00000008 - -// nbif_gpu_RCC_BIF_STRAP0 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_GEN3_DIS_PIN__SHIFT 0x00000000 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT 0x00000001 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x00000002 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x00000003 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x00000006 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x00000007 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x00000008 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x00000009 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0x0000000a -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0x0000000b -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0x0000000c -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0x0000000d -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x0000000e -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x0000000f -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x00000010 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x00000011 -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x0000001a -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x0000001b -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_GPUIOV_SEC_LVL_OVRD_EN__SHIFT 0x0000001c -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x0000001d -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x0000001e -#define nbif_gpu_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x0000001f - -// nbif_gpu_RCC_BIF_STRAP1 -#define nbif_gpu_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x00000000 -#define nbif_gpu_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x00000001 -#define nbif_gpu_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x00000002 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x00000003 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT 0x00000004 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x00000005 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x00000008 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x00000009 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0x0000000a -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0x0000000c -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0x0000000d -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0x0000000f -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x00000011 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x00000012 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_GPUIOV_SEC_LVL_OVRD_VAL__SHIFT 0x00000013 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x00000016 -#define nbif_gpu_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x00000017 - -// nbif_gpu_RCC_BIF_STRAP2 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x00000000 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SATA_DID_RAID_EN_0__SHIFT 0x00000001 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SATA_DID_RAID_EN_1__SHIFT 0x00000002 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x00000003 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x00000004 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x00000005 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x00000006 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_PCIE_SEC_LVL_OVRD_EN__SHIFT 0x00000007 -#define nbif_gpu_RCC_BIF_STRAP2__STRAP_PCIE_SEC_LVL_OVRD_VAL__SHIFT 0x00000008 -#define nbif_gpu_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0x0000000b -#define nbif_gpu_RCC_BIF_STRAP2__RESERVED2_BIF_STRAP2__SHIFT 0x0000000e - -// nbif_gpu_RCC_BIF_STRAP3 -#define nbif_gpu_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x00000000 -#define nbif_gpu_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x00000010 - -// nbif_gpu_RCC_BIF_STRAP4 -#define nbif_gpu_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x00000000 -#define nbif_gpu_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x00000010 - -// nbif_gpu_RCC_BIF_STRAP5 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x00000000 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x00000010 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x00000011 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x00000012 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x00000013 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x00000014 -#define nbif_gpu_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x00000015 - -// nbif_gpu_RCC_BIF_STRAP6 -#define nbif_gpu_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV0_PORT_STRAP0 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x00000003 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x00000005 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_PORT_STRAP1 -#define nbif_gpu_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_PORT_STRAP2 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x00000003 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x00000005 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x00000006 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0x0000000c -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0x0000000d -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0x0000000f -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x0000001d - -// nbif_gpu_RCC_DEV0_PORT_STRAP3 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x00000003 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x00000006 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT \ - 0x0000000b -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT \ - 0x0000000e -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT \ - 0x00000012 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT \ - 0x00000015 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x0000001b -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_PORT_STRAP4 -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_PORT_STRAP5 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x0000001b -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_PORT_STRAP6 -#define nbif_gpu_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x00000001 - -// nbif_gpu_RCC_DEV0_PORT_STRAP7 -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0x0000000c -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x0000001d - -// nbif_gpu_RCC_DEV0_EPF0_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF0_STRAP1 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF0_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF0_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x00000006 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0x0000000f -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x0000001b -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT \ - 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT \ - 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF0_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF0_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF0_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV0_EPF0_STRAP8 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x00000003 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x00000005 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0x0000000c -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x0000001b -#define nbif_gpu_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x0000001e - -// nbif_gpu_RCC_DEV0_EPF0_STRAP9 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP9__STRAP_SECURE_ID_DEV0_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF0_STRAP9__STRAP_SECURE_LVL_DEV0_F0__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF1_STRAP10 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x00000001 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP11 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x00000001 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP12 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x00000001 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF1_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF1_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x00000019 - -// nbif_gpu_RCC_DEV0_EPF1_STRAP7 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x00000001 - -// nbif_gpu_RCC_DEV1_PORT_STRAP0 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x00000003 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x00000005 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_PORT_STRAP1 -#define nbif_gpu_RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV1_PORT_STRAP2 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x00000003 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x00000005 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x00000006 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0x0000000c -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0x0000000d -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0x0000000f -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x0000001d - -// nbif_gpu_RCC_DEV1_PORT_STRAP3 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x00000003 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x00000006 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT \ - 0x0000000b -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT \ - 0x0000000e -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT \ - 0x00000012 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT \ - 0x00000015 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x0000001b -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_PORT_STRAP4 -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV1_PORT_STRAP5 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x0000001b -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_PORT_STRAP6 -#define nbif_gpu_RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x00000001 - -// nbif_gpu_RCC_DEV1_PORT_STRAP7 -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0x0000000c -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x0000001d - -// nbif_gpu_RCC_DEV0_EPF2_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF2_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF2_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF2_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF2_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF2_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF2_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x00000009 - -// nbif_gpu_RCC_DEV0_EPF3_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF3_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF3_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF3_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF3_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF3_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x00000014 - -// nbif_gpu_RCC_DEV0_EPF3_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT 0x00000004 - -// nbif_gpu_RCC_DEV0_EPF4_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF4_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF4_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF4_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF4_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF4_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x00000014 - -// nbif_gpu_RCC_DEV0_EPF4_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x00000011 - -// nbif_gpu_RCC_DEV0_EPF5_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF5_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF5_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF5_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF5_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF5_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV0_EPF5_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x00000011 - -// nbif_gpu_RCC_DEV0_EPF6_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF6_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF6_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF6_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF6_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF6_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV0_EPF6_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x00000011 - -// nbif_gpu_RCC_DEV0_EPF7_STRAP0 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF7_STRAP13 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV0_EPF7_STRAP2 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV0_EPF7_STRAP3 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV0_EPF7_STRAP4 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV0_EPF7_STRAP5 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV0_EPF7_STRAP6 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x00000011 - -// nbif_gpu_RCC_DEV1_EPF0_STRAP0 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_EPF0_STRAP13 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV1_EPF0_STRAP2 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0x0000000f -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV1_EPF0_STRAP3 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV1_EPF0_STRAP4 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_EPF0_STRAP5 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV1_EPF0_STRAP6 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT 0x00000004 - -// nbif_gpu_RCC_DEV1_EPF1_STRAP0 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_EPF1_STRAP13 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV1_EPF1_STRAP2 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV1_EPF1_STRAP3 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV1_EPF1_STRAP4 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_EPF1_STRAP5 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV1_EPF1_STRAP6 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x00000019 - -// nbif_gpu_RCC_DEV1_EPF2_STRAP0 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT 0x0000001d -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT 0x0000001e -#define nbif_gpu_RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_EPF2_STRAP13 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT 0x00000010 - -// nbif_gpu_RCC_DEV1_EPF2_STRAP2 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT 0x00000007 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT 0x0000000e -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT 0x00000018 - -// nbif_gpu_RCC_DEV1_EPF2_STRAP3 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT 0x00000002 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT 0x00000012 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT 0x00000013 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT 0x00000019 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT 0x0000001a -#define nbif_gpu_RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT 0x0000001b - -// nbif_gpu_RCC_DEV1_EPF2_STRAP4 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT 0x00000014 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT 0x00000015 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT 0x00000016 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT 0x00000017 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT 0x0000001c -#define nbif_gpu_RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT 0x0000001f - -// nbif_gpu_RCC_DEV1_EPF2_STRAP5 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT 0x00000000 - -// nbif_gpu_RCC_DEV1_EPF2_STRAP6 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT 0x00000000 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x00000001 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT 0x00000004 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT 0x00000008 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x00000009 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT 0x00000010 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x00000011 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT 0x00000018 -#define nbif_gpu_RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x00000019 - -// nbif_gpu_SHUB_PF_FLR_RST -#define nbif_gpu_SHUB_PF_FLR_RST__PF0_FLR_RST__SHIFT 0x00000000 -#define nbif_gpu_SHUB_PF_FLR_RST__PF1_FLR_RST__SHIFT 0x00000001 -#define nbif_gpu_SHUB_PF_FLR_RST__PF2_FLR_RST__SHIFT 0x00000002 -#define nbif_gpu_SHUB_PF_FLR_RST__PF3_FLR_RST__SHIFT 0x00000003 -#define nbif_gpu_SHUB_PF_FLR_RST__PF4_FLR_RST__SHIFT 0x00000004 -#define nbif_gpu_SHUB_PF_FLR_RST__PF5_FLR_RST__SHIFT 0x00000005 -#define nbif_gpu_SHUB_PF_FLR_RST__PF6_FLR_RST__SHIFT 0x00000006 -#define nbif_gpu_SHUB_PF_FLR_RST__PF7_FLR_RST__SHIFT 0x00000007 - -// nbif_gpu_SHUB_GFX_DRV_MODE1_RST -#define nbif_gpu_SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__SHIFT 0x00000000 - -// nbif_gpu_SHUB_LINK_RESET -#define nbif_gpu_SHUB_LINK_RESET__LINK_RESET__SHIFT 0x00000000 - -// nbif_gpu_SHUB_PF0_VF_FLR_RST -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x00000000 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x00000001 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x00000002 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x00000003 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x00000004 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x00000005 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x00000006 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x00000007 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x00000008 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x00000009 -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0x0000000a -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0x0000000b -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0x0000000c -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0x0000000d -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0x0000000e -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0x0000000f -#define nbif_gpu_SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x0000001f - -// nbif_gpu_SHUB_HARD_RST_CTRL -#define nbif_gpu_SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x00000000 -#define nbif_gpu_SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x00000001 -#define nbif_gpu_SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x00000002 -#define nbif_gpu_SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x00000003 -#define nbif_gpu_SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x00000004 - -// nbif_gpu_SHUB_SOFT_RST_CTRL -#define nbif_gpu_SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x00000000 -#define nbif_gpu_SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x00000001 -#define nbif_gpu_SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x00000002 -#define nbif_gpu_SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x00000003 -#define nbif_gpu_SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x00000004 - -// nbif_gpu_SHUB_SDP_PORT_RST -#define nbif_gpu_SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT0_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT1_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT2_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT3_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT4_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT5_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT6_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT7_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT8_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT9_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT10_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT11_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT12_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT13_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT14_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT15_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT16_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT17_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT18_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT19_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT20_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT21_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT22_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT23_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT24_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT25_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT26_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT27_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT28_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT29_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT30_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT31_ADDR_LO -#define nbif_gpu_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x00000002 - -// nbif_gpu_PCIEMSIX_VECT0_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT1_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT2_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT3_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT4_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT5_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT6_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT7_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT8_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT9_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT10_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT11_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT12_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT13_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT14_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT15_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT16_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT17_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT18_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT19_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT20_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT21_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT22_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT23_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT24_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT25_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT26_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT27_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT28_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT29_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT30_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT31_ADDR_HI -#define nbif_gpu_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT0_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT1_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT2_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT3_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT4_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT5_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT6_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT7_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT8_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT9_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT10_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT11_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT12_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT13_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT14_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT15_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT16_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT17_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT18_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT19_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT20_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT21_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT22_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT23_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT24_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT25_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT26_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT27_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT28_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT29_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT30_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT31_MSG_DATA -#define nbif_gpu_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT0_CONTROL -#define nbif_gpu_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT1_CONTROL -#define nbif_gpu_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT2_CONTROL -#define nbif_gpu_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT3_CONTROL -#define nbif_gpu_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT4_CONTROL -#define nbif_gpu_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT5_CONTROL -#define nbif_gpu_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT6_CONTROL -#define nbif_gpu_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT7_CONTROL -#define nbif_gpu_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT8_CONTROL -#define nbif_gpu_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT9_CONTROL -#define nbif_gpu_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT10_CONTROL -#define nbif_gpu_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT11_CONTROL -#define nbif_gpu_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT12_CONTROL -#define nbif_gpu_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT13_CONTROL -#define nbif_gpu_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT14_CONTROL -#define nbif_gpu_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT15_CONTROL -#define nbif_gpu_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT16_CONTROL -#define nbif_gpu_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT17_CONTROL -#define nbif_gpu_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT18_CONTROL -#define nbif_gpu_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT19_CONTROL -#define nbif_gpu_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT20_CONTROL -#define nbif_gpu_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT21_CONTROL -#define nbif_gpu_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT22_CONTROL -#define nbif_gpu_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT23_CONTROL -#define nbif_gpu_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT24_CONTROL -#define nbif_gpu_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT25_CONTROL -#define nbif_gpu_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT26_CONTROL -#define nbif_gpu_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT27_CONTROL -#define nbif_gpu_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT28_CONTROL -#define nbif_gpu_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT29_CONTROL -#define nbif_gpu_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT30_CONTROL -#define nbif_gpu_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_VECT31_CONTROL -#define nbif_gpu_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x00000000 - -// nbif_gpu_PCIEMSIX_PBA -#define nbif_gpu_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x00000000 - -// nbif_gpu_RCC_PFC_LTR_CNTL -#define nbif_gpu_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x00000000 -#define nbif_gpu_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0x0000000a -#define nbif_gpu_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0x0000000f -#define nbif_gpu_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x00000010 -#define nbif_gpu_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x0000001a -#define nbif_gpu_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x0000001f - -// nbif_gpu_RCC_PFC_PME_RESTORE -#define nbif_gpu_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x00000000 -#define nbif_gpu_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x00000008 - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_0 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x00000000 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x00000001 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x00000002 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x00000003 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x00000004 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x00000005 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x00000006 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x00000007 - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_1 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x00000000 - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_2 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x00000000 - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_3 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x00000000 - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_4 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x00000000 - -// nbif_gpu_RCC_PFC_STICKY_RESTORE_5 -#define nbif_gpu_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x00000000 - -// nbif_gpu_RCC_PFC_AUXPWR_CNTL -#define nbif_gpu_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x00000000 -#define nbif_gpu_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x00000003 - -// IH_VMID_0_LUT -#define IH_VMID_0_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_1_LUT -#define IH_VMID_1_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_2_LUT -#define IH_VMID_2_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_3_LUT -#define IH_VMID_3_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_4_LUT -#define IH_VMID_4_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_5_LUT -#define IH_VMID_5_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_6_LUT -#define IH_VMID_6_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_7_LUT -#define IH_VMID_7_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_8_LUT -#define IH_VMID_8_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_9_LUT -#define IH_VMID_9_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_10_LUT -#define IH_VMID_10_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_11_LUT -#define IH_VMID_11_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_12_LUT -#define IH_VMID_12_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_13_LUT -#define IH_VMID_13_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_14_LUT -#define IH_VMID_14_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_15_LUT -#define IH_VMID_15_LUT__PASID__SHIFT 0x00000000 - -// IH_VMID_0_LUT_MM -#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_1_LUT_MM -#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_2_LUT_MM -#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_3_LUT_MM -#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_4_LUT_MM -#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_5_LUT_MM -#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_6_LUT_MM -#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_7_LUT_MM -#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_8_LUT_MM -#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_9_LUT_MM -#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_10_LUT_MM -#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_11_LUT_MM -#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_12_LUT_MM -#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_13_LUT_MM -#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_14_LUT_MM -#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_VMID_15_LUT_MM -#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x00000000 - -// IH_COOKIE_0 -#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x00000000 -#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x00000008 -#define IH_COOKIE_0__RING_ID__SHIFT 0x00000010 -#define IH_COOKIE_0__VM_ID__SHIFT 0x00000018 -#define IH_COOKIE_0__RESERVED__SHIFT 0x0000001c -#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x0000001f - -// IH_COOKIE_1 -#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x00000000 - -// IH_COOKIE_2 -#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x00000000 -#define IH_COOKIE_2__RESERVED__SHIFT 0x00000010 -#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x0000001f - -// IH_COOKIE_3 -#define IH_COOKIE_3__PAS_ID__SHIFT 0x00000000 -#define IH_COOKIE_3__RESERVED__SHIFT 0x00000010 -#define IH_COOKIE_3__PASID_SRC__SHIFT 0x0000001f - -// IH_COOKIE_4 -#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x00000000 - -// IH_COOKIE_5 -#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x00000000 - -// IH_COOKIE_6 -#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x00000000 - -// IH_COOKIE_7 -#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x00000000 - -// IH_REGISTER_LAST_PART0 -#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x00000000 - -// IH_RB_CNTL -#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007 -#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008 -#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000009 -#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0x0000000a -#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0x0000000c -#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010 -#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x00000011 -#define IH_RB_CNTL__MC_SWAP__SHIFT 0x00000012 -#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x00000014 -#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x00000015 -#define IH_RB_CNTL__MC_RO__SHIFT 0x00000016 -#define IH_RB_CNTL__MC_VMID__SHIFT 0x00000018 -#define IH_RB_CNTL__MC_SPACE__SHIFT 0x0000001c -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f - -// IH_RB_BASE -#define IH_RB_BASE__ADDR__SHIFT 0x00000000 - -// IH_RB_BASE_HI -#define IH_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// IH_RB_RPTR -#define IH_RB_RPTR__OFFSET__SHIFT 0x00000002 - -// IH_RB_WPTR -#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000 -#define IH_RB_WPTR__OFFSET__SHIFT 0x00000002 -#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x00000012 -#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x00000013 - -// IH_RB_WPTR_ADDR_HI -#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// IH_RB_WPTR_ADDR_LO -#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// IH_DOORBELL_RPTR -#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x00000000 -#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x0000001c - -// IH_RB_CNTL_RING1 -#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x00000000 -#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x00000001 -#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x00000007 -#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000009 -#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0x0000000a -#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0x0000000c -#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010 -#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x00000012 -#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x00000014 -#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x00000016 -#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x00000018 -#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x0000001c -#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f - -// IH_RB_BASE_RING1 -#define IH_RB_BASE_RING1__ADDR__SHIFT 0x00000000 - -// IH_RB_BASE_HI_RING1 -#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x00000000 - -// IH_RB_RPTR_RING1 -#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x00000002 - -// IH_RB_WPTR_RING1 -#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x00000000 -#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x00000002 -#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x00000012 -#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x00000013 - -// IH_DOORBELL_RPTR_RING1 -#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x00000000 -#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x0000001c - -// IH_RB_CNTL_RING2 -#define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x00000000 -#define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x00000001 -#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x00000007 -#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000009 -#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0x0000000a -#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0x0000000c -#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010 -#define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x00000012 -#define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x00000014 -#define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x00000016 -#define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x00000018 -#define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x0000001c -#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f - -// IH_RB_BASE_RING2 -#define IH_RB_BASE_RING2__ADDR__SHIFT 0x00000000 - -// IH_RB_BASE_HI_RING2 -#define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x00000000 - -// IH_RB_RPTR_RING2 -#define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x00000002 - -// IH_RB_WPTR_RING2 -#define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x00000000 -#define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x00000002 -#define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x00000012 -#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x00000013 - -// IH_DOORBELL_RPTR_RING2 -#define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x00000000 -#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x0000001c - -// IH_VERSION -#define IH_VERSION__MINVER__SHIFT 0x00000000 -#define IH_VERSION__MAJVER__SHIFT 0x00000008 -#define IH_VERSION__REV__SHIFT 0x00000010 - -// IH_CNTL -#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000000 -#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x00000006 -#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x00000008 -#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014 - -// IH_CNTL2 -#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x00000000 -#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x00000008 - -// IH_STATUS -#define IH_STATUS__IDLE__SHIFT 0x00000000 -#define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001 -#define IH_STATUS__BUFFER_IDLE__SHIFT 0x00000002 -#define IH_STATUS__RB_FULL__SHIFT 0x00000003 -#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004 -#define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005 -#define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006 -#define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007 -#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008 -#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009 -#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a -#define IH_STATUS__SWITCH_READY__SHIFT 0x0000000b -#define IH_STATUS__RB1_FULL__SHIFT 0x0000000c -#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0x0000000d -#define IH_STATUS__RB1_OVERFLOW__SHIFT 0x0000000e -#define IH_STATUS__RB2_FULL__SHIFT 0x0000000f -#define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x00000010 -#define IH_STATUS__RB2_OVERFLOW__SHIFT 0x00000011 -#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x00000012 - -// IH_PERFMON_CNTL -#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x00000000 -#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x00000001 -#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002 -#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x00000010 -#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x00000011 -#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x00000012 - -// IH_PERFCOUNTER0_RESULT -#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// IH_PERFCOUNTER1_RESULT -#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// IH_DEBUG -#define IH_DEBUG__DBG_SEL_VF__SHIFT 0x00000003 -#define IH_DEBUG__DBG_SEL_VFID__SHIFT 0x00000004 -#define IH_DEBUG__DBG_SEL_IH_RING_ID__SHIFT 0x0000000c - -// IH_DSM_MATCH_VALUE_BIT_31_0 -#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x00000000 - -// IH_DSM_MATCH_VALUE_BIT_63_32 -#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x00000000 - -// IH_DSM_MATCH_VALUE_BIT_95_64 -#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x00000000 - -// IH_DSM_MATCH_FIELD_CONTROL -#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x00000000 -#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x00000001 -#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x00000002 -#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x00000003 -#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x00000004 -#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x00000005 -#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x00000006 - -// IH_DSM_MATCH_DATA_CONTROL -#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x00000000 - -// IH_DSM_MATCH_FCN_ID -#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x00000000 -#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x00000001 - -// IH_LIMIT_INT_RATE_CNTL -#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x00000000 -#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x00000001 -#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x00000005 -#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x00000011 -#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x00000015 - -// IH_VF_RB_STATUS -#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x00000000 -#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x00000010 - -// IH_VF_RB_STATUS2 -#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x00000000 -#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x00000010 - -// IH_VF_RB1_STATUS -#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x00000000 -#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x00000010 - -// IH_VF_RB1_STATUS2 -#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x00000000 - -// IH_VF_RB2_STATUS -#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x00000000 -#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT 0x00000010 - -// IH_VF_RB2_STATUS2 -#define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x00000000 - -// IH_INT_FLOOD_CNTL -#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x00000000 -#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x00000003 -#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x00000004 - -// IH_RB0_INT_FLOOD_STATUS -#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x00000000 -#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x0000001f - -// IH_RB1_INT_FLOOD_STATUS -#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x00000000 -#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x0000001f - -// IH_RB2_INT_FLOOD_STATUS -#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x00000000 -#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x0000001f - -// IH_INT_FLOOD_STATUS -#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x00000000 -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x00000008 -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x00000010 -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x00000018 -#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x0000001c -#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x0000001e - -// IH_STORM_CLIENT_LIST_CNTL -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x00000001 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x00000002 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x00000003 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x00000004 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x00000005 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x00000006 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x00000007 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x00000008 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x00000009 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0x0000000a -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0x0000000b -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0x0000000c -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0x0000000d -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0x0000000e -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0x0000000f -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x00000010 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x00000011 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x00000012 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x00000013 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x00000014 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x00000015 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x00000016 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x00000017 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x00000018 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x00000019 -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x0000001a -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x0000001b -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x0000001c -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x0000001d -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x0000001e -#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x0000001f - -// IH_CLK_CTRL -#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x0000001b -#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x0000001c -#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x0000001d -#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x0000001e -#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x0000001f - -// IH_INT_FLAGS -#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x00000000 -#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x00000001 -#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x00000002 -#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x00000003 -#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x00000004 -#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x00000005 -#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x00000006 -#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x00000007 -#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x00000008 -#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x00000009 -#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0x0000000a -#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0x0000000b -#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0x0000000c -#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0x0000000d -#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0x0000000e -#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0x0000000f -#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x00000010 -#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x00000011 -#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x00000012 -#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x00000013 -#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x00000014 -#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x00000015 -#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x00000016 -#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x00000017 -#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x00000018 -#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x00000019 -#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x0000001a -#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x0000001b -#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x0000001c -#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x0000001d -#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x0000001e -#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x0000001f - -// IH_LAST_INT_INFO0 -#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x00000000 -#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x00000008 -#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x00000010 -#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x00000018 - -// IH_LAST_INT_INFO1 -#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x00000000 - -// IH_LAST_INT_INFO2 -#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x00000000 -#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x00000010 -#define IH_LAST_INT_INFO2__VF__SHIFT 0x00000014 - -// IH_SCRATCH -#define IH_SCRATCH__DATA__SHIFT 0x00000000 - -// IH_CLIENT_CREDIT_ERROR -#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x00000000 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x00000001 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x00000002 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x00000003 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x00000004 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x00000005 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x00000006 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x00000007 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x00000008 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x00000009 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0x0000000a -#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0x0000000b -#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0x0000000c -#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0x0000000d -#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0x0000000e -#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0x0000000f -#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x00000010 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x00000011 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x00000012 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x00000013 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x00000014 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x00000015 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x00000016 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x00000017 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x00000018 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x00000019 -#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x0000001a -#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x0000001b -#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x0000001c -#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x0000001d -#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x0000001e -#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x0000001f - -// IH_GPU_IOV_VIOLATION_LOG -#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x00000000 -#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x00000001 -#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x00000002 -#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x00000012 -#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x00000013 -#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x00000014 -#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x00000018 - -// IH_COOKIE_REC_VIOLATION_LOG -#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x00000000 -#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x00000010 -#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x00000018 - -// IH_CREDIT_STATUS -#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x00000001 -#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x00000002 -#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x00000003 -#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x00000004 -#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x00000005 -#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x00000006 -#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x00000007 -#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x00000008 -#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x00000009 -#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0x0000000a -#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0x0000000b -#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0x0000000c -#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0x0000000d -#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0x0000000e -#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0x0000000f -#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x00000010 -#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x00000011 -#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x00000012 -#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x00000013 -#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x00000014 -#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x00000015 -#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x00000016 -#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x00000017 -#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x00000018 -#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x00000019 -#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x0000001a -#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x0000001b -#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x0000001c -#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x0000001d -#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x0000001e -#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x0000001f - -// IH_MMHUB_ERROR -#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x00000001 -#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x00000002 -#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x00000003 -#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x00000005 -#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x00000006 -#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x00000007 - -// IH_DEBUG_INDEX -#define IH_DEBUG_INDEX__INDEX__SHIFT 0x00000000 - -// IH_DEBUG_DATA -#define IH_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// IH_REGISTER_LAST_PART2 -#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x00000000 - -// IH_ACTIVE_FCN_ID -#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x00000000 -#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x00000004 -#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x0000001f - -// IH_VIRT_RESET_REQ -#define IH_VIRT_RESET_REQ__VF__SHIFT 0x00000000 -#define IH_VIRT_RESET_REQ__PF__SHIFT 0x0000001f - -// IH_CLIENT_CFG -#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x00000000 - -// IH_CLIENT_CFG_INDEX -#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x00000000 - -// IH_CLIENT_CFG_DATA -#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x00000000 -#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x00000012 -#define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x00000014 -#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x00000016 -#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x00000018 - -// IH_CID_REMAP_INDEX -#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x00000000 - -// IH_CID_REMAP_DATA -#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x00000000 -#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x00000008 -#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x00000010 - -// IH_CHICKEN -#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x00000000 - -// IH_MMHUB_TLVL -#define IH_MMHUB_TLVL__IV_TLVL__SHIFT 0x00000000 -#define IH_MMHUB_TLVL__WPTR_WB_TLVL__SHIFT 0x00000004 - -// IH_REGISTER_LAST_PART1 -#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x00000000 - -// SEM_REQ_INPUT_0 -#define SEM_REQ_INPUT_0__DATA__SHIFT 0x00000000 - -// SEM_REQ_INPUT_1 -#define SEM_REQ_INPUT_1__DATA__SHIFT 0x00000000 - -// SEM_REQ_INPUT_2 -#define SEM_REQ_INPUT_2__DATA__SHIFT 0x00000000 - -// SEM_REQ_INPUT_3 -#define SEM_REQ_INPUT_3__DATA__SHIFT 0x00000000 - -// SEM_REGISTER_LAST_PART0 -#define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x00000000 - -// SEM_CLK_CTRL -#define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define SEM_CLK_CTRL__RESERVED__SHIFT 0x0000000c -#define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define SEM_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define SEM_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define SEM_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// SEM_UTC_CREDIT -#define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x00000000 -#define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x00000008 - -// SEM_UTC_CONFIG -#define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x00000000 -#define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x00000003 -#define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x00000004 -#define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x00000005 - -// SEM_UTCL2_TRAN_EN_LUT -#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x00000000 -#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x00000001 -#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x00000002 -#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x00000003 -#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x00000004 -#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x00000005 -#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x00000006 -#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x00000007 -#define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x00000008 -#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x0000001f - -// SEM_MCIF_CONFIG -#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000 -#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x00000002 -#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x00000008 - -// SEM_PERFMON_CNTL -#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x00000000 -#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x00000001 -#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002 -#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x0000000a -#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x0000000b -#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000c - -// SEM_PERFCOUNTER0_RESULT -#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// SEM_PERFCOUNTER1_RESULT -#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// SEM_STATUS -#define SEM_STATUS__SEM_IDLE__SHIFT 0x00000000 -#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x00000001 -#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x00000002 -#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x00000003 -#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x00000004 -#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x00000005 -#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x00000006 -#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x00000007 -#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x00000008 -#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x00000009 -#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0x0000000a -#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0x0000000b -#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0x0000000c -#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0x0000000d -#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0x0000000e -#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0x0000000f -#define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x00000010 -#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x00000011 -#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x00000012 -#define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x00000013 -#define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x00000014 -#define SEM_STATUS__MIF_IDLE__SHIFT 0x00000015 -#define SEM_STATUS__REGISTER_IDLE__SHIFT 0x00000016 -#define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x00000017 -#define SEM_STATUS__SWITCH_READY__SHIFT 0x0000001f - -// SEM_MAILBOX_CLIENTCONFIG -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000 -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003 -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006 -#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009 -#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0x0000000c -#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f -#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x00000012 -#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x00000015 - -// SEM_MAILBOX -#define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000000 -#define SEM_MAILBOX__RESERVED__SHIFT 0x00000010 - -// SEM_MAILBOX_CONTROL -#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000000 -#define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x00000010 - -// SEM_CHICKEN_BITS -#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x00000000 -#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x00000001 -#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x00000002 -#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x00000003 -#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x00000006 -#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x00000007 -#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x00000008 -#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0x0000000a -#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0x0000000c -#define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0x0000000e -#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0x0000000f -#define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x00000010 -#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x00000012 - -// SEM_MAILBOX_CLIENTCONFIG_EXTRA -#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x00000000 - -// SEM_GPU_IOV_VIOLATION_LOG -#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x00000000 -#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x00000001 -#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x00000002 -#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x00000012 -#define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x00000013 -#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x00000014 -#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x00000018 - -// SEM_OUTSTANDING_THRESHOLD -#define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x00000000 - -// SEM_REGISTER_LAST_PART2 -#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x00000000 - -// SEM_ACTIVE_FCN_ID -#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x00000000 -#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x0000001f - -// SEM_VIRT_RESET_REQ -#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x00000000 -#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x0000001f - -// SEM_RESP_SDMA0 -#define SEM_RESP_SDMA0__ADDR__SHIFT 0x00000002 - -// SEM_RESP_SDMA1 -#define SEM_RESP_SDMA1__ADDR__SHIFT 0x00000002 - -// SEM_RESP_UVD -#define SEM_RESP_UVD__ADDR__SHIFT 0x00000002 - -// SEM_RESP_VCE_0 -#define SEM_RESP_VCE_0__ADDR__SHIFT 0x00000002 - -// SEM_RESP_ACP -#define SEM_RESP_ACP__ADDR__SHIFT 0x00000002 - -// SEM_RESP_ISP -#define SEM_RESP_ISP__ADDR__SHIFT 0x00000002 - -// SEM_RESP_VCE_1 -#define SEM_RESP_VCE_1__ADDR__SHIFT 0x00000002 - -// SEM_RESP_VP8 -#define SEM_RESP_VP8__ADDR__SHIFT 0x00000002 - -// SEM_RESP_GC -#define SEM_RESP_GC__ADDR__SHIFT 0x00000002 - -// SEM_CID_REMAP_INDEX -#define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x00000000 - -// SEM_CID_REMAP_DATA -#define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x00000000 -#define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x00000008 -#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x00000010 - -// SEM_ATOMIC_OP_LUT -#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x00000000 -#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x00000007 -#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0x0000000e -#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x00000015 - -// SEM_EDC_CONFIG -#define SEM_EDC_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x00000001 - -// SEM_CHICKEN_BITS2 -#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x00000000 - -// SEM_MMHUB_TLVL -#define SEM_MMHUB_TLVL__VALUE__SHIFT 0x00000000 - -// SEM_REGISTER_LAST_PART1 -#define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x00000000 - -// SDMA0_UCODE_ADDR -#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x00000000 - -// SDMA0_UCODE_DATA -#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x00000000 - -// SDMA0_REGISTER_SECURITY_CNTL -#define SDMA0_REGISTER_SECURITY_CNTL__ENABLE__SHIFT 0x00000000 - -// SDMA0_VM_CNTL -#define SDMA0_VM_CNTL__CMD__SHIFT 0x00000000 - -// SDMA0_VM_CTX_LO -#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_VM_CTX_HI -#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_ACTIVE_FCN_ID -#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x00000000 -#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x00000004 -#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x0000001f - -// SDMA0_VM_CTX_CNTL -#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x00000000 -#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x00000004 - -// SDMA0_VIRT_RESET_REQ -#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x00000000 -#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x0000001f - -// SDMA0_CONTEXT_REG_TYPE0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x00000000 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x00000001 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x00000002 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x00000003 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x00000004 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x00000005 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x00000006 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x00000007 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x00000008 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x00000009 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0x0000000a -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0x0000000b -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0x0000000c -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0x0000000d -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0x0000000e -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0x0000000f -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x00000010 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x00000011 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x00000012 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x00000013 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY0__SHIFT 0x00000014 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY1__SHIFT 0x00000015 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY2__SHIFT 0x00000016 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_WRAPPEDKEY3__SHIFT 0x00000017 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY0__SHIFT 0x00000018 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY1__SHIFT 0x00000019 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY2__SHIFT 0x0000001a -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERKEY3__SHIFT 0x0000001b -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA0__SHIFT 0x0000001c -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA1__SHIFT 0x0000001d -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA2__SHIFT 0x0000001e -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DRM_COUNTERDATA3__SHIFT 0x0000001f - -// SDMA0_CONTEXT_REG_TYPE1 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_OFFSET__SHIFT 0x00000000 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD0__SHIFT 0x00000001 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD1__SHIFT 0x00000002 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD2__SHIFT 0x00000003 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD3__SHIFT 0x00000004 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_IVLOAD4__SHIFT 0x00000005 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DRM_UNROLLKEY__SHIFT 0x00000006 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_AES__SHIFT 0x00000007 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x00000008 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x00000009 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0x0000000a -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0x0000000b -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0x0000000c -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0x0000000d -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0x0000000e -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0x0000000f -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x00000010 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x00000011 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000012 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000013 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x00000014 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x00000015 -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x00000016 - -// SDMA0_CONTEXT_REG_TYPE2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x00000000 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x00000001 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x00000002 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x00000003 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x00000004 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x00000005 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x00000006 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x00000007 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x00000008 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x00000009 -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x0000000a - -// SDMA0_CONTEXT_REG_TYPE3 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x00000000 - -// SDMA0_PUB_REG_TYPE0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x00000000 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x00000001 -#define SDMA0_PUB_REG_TYPE0__SDMA0_REGISTER_SECURITY_CNTL__SHIFT 0x00000002 -#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x00000003 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x00000004 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x00000005 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x00000006 -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x00000007 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x00000008 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x00000009 -#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0x0000000a -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0x0000000b -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0x0000000c -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0x0000000d -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0x0000000e -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0x0000000f -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x00000010 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x00000011 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x00000012 -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x00000013 -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x00000019 -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x0000001a -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x0000001b -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x0000001c -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x0000001d -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x0000001e -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x0000001f - -// SDMA0_PUB_REG_TYPE1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x00000000 -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x00000001 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x00000002 -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x00000003 -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x00000004 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x00000005 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x00000006 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x00000007 -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x00000008 -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x00000009 -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0x0000000a -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0x0000000b -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0x0000000c -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0x0000000d -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0x0000000e -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0x0000000f -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x00000010 -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x00000011 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x00000012 -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x00000013 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x00000014 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x00000015 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x00000016 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x00000017 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x00000018 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x00000019 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x0000001a -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x0000001b -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x0000001c -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x0000001d -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x0000001e -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x0000001f - -// SDMA0_PUB_REG_TYPE2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x00000000 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x00000001 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x00000002 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x00000003 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x00000004 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x00000005 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x00000006 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x00000007 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x00000008 -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x00000009 -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0x0000000a -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0x0000000b -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0x0000000c -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0x0000000d -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0x0000000e -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0x0000000f -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x00000010 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x00000011 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x00000012 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x00000013 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x00000014 -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x00000015 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x00000016 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x00000017 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x00000018 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x00000019 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x0000001a -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x0000001b -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x0000001c -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x0000001d -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x0000001e -#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x0000001f - -// SDMA0_PUB_REG_TYPE3 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x00000000 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x00000001 -#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x00000002 - -// SDMA0_CONTEXT_GROUP_BOUNDARY -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x00000000 - -// SDMA0_POWER_CNTL -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x00000000 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x00000001 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x00000002 -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x00000008 -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x00000009 -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0x0000000a -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0x0000000b -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0x0000000c - -// SDMA0_CLK_CTRL -#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0x0000000c -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// SDMA0_CNTL -#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x00000000 -#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x00000001 -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x00000002 -#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x00000003 -#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000005 -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x00000011 -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x00000012 -#define SDMA0_CNTL__DRM_RESTORE_ENABLE__SHIFT 0x00000013 -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x0000001c -#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x0000001d -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x0000001e - -// SDMA0_CHICKEN_BITS -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x00000000 -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x00000001 -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x00000002 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x00000008 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0x0000000a -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x00000010 -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x00000011 -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x00000014 -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x00000017 -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x00000019 -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x0000001a -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x0000001c -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x0000001e - -// SDMA0_GB_ADDR_CONFIG -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0x0000000c -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x00000013 - -// SDMA0_GB_ADDR_CONFIG_READ -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x00000000 -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0x0000000c -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x00000013 - -// SDMA0_RB_RPTR_FETCH_HI -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x00000000 - -// SDMA0_RB_RPTR_FETCH -#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x00000002 - -// SDMA0_IB_OFFSET_FETCH -#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x00000002 - -// SDMA0_PROGRAM -#define SDMA0_PROGRAM__STREAM__SHIFT 0x00000000 - -// SDMA0_STATUS_REG -#define SDMA0_STATUS_REG__IDLE__SHIFT 0x00000000 -#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x00000001 -#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x00000002 -#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x00000003 -#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x00000004 -#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x00000005 -#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x00000006 -#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x00000007 -#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x00000008 -#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x00000009 -#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0x0000000a -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0x0000000b -#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0x0000000c -#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0x0000000d -#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0x0000000e -#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0x0000000f -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x00000010 -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x00000011 -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x00000012 -#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x00000013 -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x00000014 -#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x00000015 -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x00000016 -#define SDMA0_STATUS_REG__DRM_IDLE__SHIFT 0x00000017 -#define SDMA0_STATUS_REG__DRM_MASK_FULL__SHIFT 0x00000018 -#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x00000019 -#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x0000001a -#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x0000001b -#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x0000001c -#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x0000001e -#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x0000001f - -// SDMA0_STATUS1_REG -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x00000000 -#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x00000001 -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x00000002 -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x00000003 -#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x00000004 -#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x00000005 -#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x00000006 -#define SDMA0_STATUS1_REG__CE_DRM_IDLE__SHIFT 0x00000007 -#define SDMA0_STATUS1_REG__CE_DRM1_IDLE__SHIFT 0x00000008 -#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x00000009 -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0x0000000a -#define SDMA0_STATUS1_REG__CE_DRM_FULL__SHIFT 0x0000000b -#define SDMA0_STATUS1_REG__CE_DRM1_FULL__SHIFT 0x0000000c -#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0x0000000d -#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0x0000000e -#define SDMA0_STATUS1_REG__EX_START__SHIFT 0x0000000f -#define SDMA0_STATUS1_REG__DRM_CTX_RESTORE__SHIFT 0x00000010 -#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x00000011 -#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x00000012 - -// SDMA0_RD_BURST_CNTL -#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x00000000 - -// SDMA0_HBM_PAGE_CONFIG -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x00000000 - -// SDMA0_UCODE_CHECKSUM -#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x00000000 - -// SDMA0_F32_CNTL -#define SDMA0_F32_CNTL__HALT__SHIFT 0x00000000 -#define SDMA0_F32_CNTL__STEP__SHIFT 0x00000001 -#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x00000002 - -// SDMA0_FREEZE -#define SDMA0_FREEZE__PREEMPT__SHIFT 0x00000000 -#define SDMA0_FREEZE__FREEZE__SHIFT 0x00000004 -#define SDMA0_FREEZE__FROZEN__SHIFT 0x00000005 -#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x00000006 - -// SDMA0_PHASE0_QUANTUM -#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x00000000 -#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x00000008 -#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x0000001e - -// SDMA0_PHASE1_QUANTUM -#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x00000000 -#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x00000008 -#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x0000001e - -// SDMA_POWER_GATING -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x00000000 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x00000001 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x00000002 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x00000003 -#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x00000004 - -// SDMA_PGFSM_CONFIG -#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x00000000 -#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x00000008 -#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x00000009 -#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0x0000000a -#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0x0000000b -#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0x0000000c -#define SDMA_PGFSM_CONFIG__READ__SHIFT 0x0000000d -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x0000001b -#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x0000001c - -// SDMA_PGFSM_WRITE -#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x00000000 - -// SDMA_PGFSM_READ -#define SDMA_PGFSM_READ__VALUE__SHIFT 0x00000000 - -// SDMA0_EDC_CONFIG -#define SDMA0_EDC_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x00000001 -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x00000002 - -// SDMA0_BA_THRESHOLD -#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x00000000 -#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x00000010 - -// SDMA0_ID -#define SDMA0_ID__DEVICE_ID__SHIFT 0x00000000 - -// SDMA0_VERSION -#define SDMA0_VERSION__MINVER__SHIFT 0x00000000 -#define SDMA0_VERSION__MAJVER__SHIFT 0x00000008 -#define SDMA0_VERSION__REV__SHIFT 0x00000010 - -// SDMA0_EDC_COUNTER -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x00000000 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x00000001 -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x00000002 -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x00000003 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x00000004 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x00000005 -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x00000006 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x00000007 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x00000008 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x00000009 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x0000000a -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x0000000b -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0x0000000c -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0x0000000d -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0x0000000e -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x0000000f -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x00000010 - -// SDMA0_EDC_COUNTER_CLEAR -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x00000000 - -// SDMA0_STATUS2_REG -#define SDMA0_STATUS2_REG__ID__SHIFT 0x00000000 -#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x00000002 -#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x00000010 - -// SDMA0_ATOMIC_CNTL -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x00000000 -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x0000001f - -// SDMA0_ATOMIC_PREOP_LO -#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x00000000 - -// SDMA0_ATOMIC_PREOP_HI -#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x00000000 - -// SDMA0_UTCL1_CNTL -#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x00000000 -#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x00000001 -#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x0000000b -#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x0000000e -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x00000018 -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x0000001d - -// SDMA0_UTCL1_WATERMK -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x00000000 -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x0000000a -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x00000012 -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x0000001a - -// SDMA0_UTCL1_RD_STATUS -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x00000000 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x00000001 -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x00000002 -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x00000003 -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x00000004 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x00000005 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x00000006 -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x00000007 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x00000008 -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x00000009 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x0000000a -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x0000000b -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x0000000c -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0x0000000d -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x0000000e -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0x0000000f -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x00000010 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x00000011 -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x00000012 -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x00000013 -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x00000014 -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x00000015 -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x00000016 -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x0000001a -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x0000001d -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x0000001e -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x0000001f - -// SDMA0_UTCL1_WR_STATUS -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x00000000 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x00000001 -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x00000002 -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x00000003 -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x00000004 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x00000005 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x00000006 -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x00000007 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x00000008 -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x00000009 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x0000000a -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x0000000b -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x0000000c -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0x0000000d -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x0000000e -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0x0000000f -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x00000010 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x00000011 -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x00000012 -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x00000013 -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x00000014 -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x00000015 -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x00000016 -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x00000019 -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x0000001c -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x0000001d -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x0000001e -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x0000001f - -// SDMA0_UTCL1_INV0 -#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x00000000 -#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x00000001 -#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x00000002 -#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x00000003 -#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x00000004 -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x00000005 -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x00000006 -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x00000007 -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x00000008 -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x00000009 -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0x0000000a -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0x0000000b -#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0x0000000c -#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x0000001c - -// SDMA0_UTCL1_INV1 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x00000000 - -// SDMA0_UTCL1_INV2 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x00000000 - -// SDMA0_UTCL1_RD_XNACK0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x00000000 - -// SDMA0_UTCL1_RD_XNACK1 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x00000000 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x00000004 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x00000008 -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x0000001a - -// SDMA0_UTCL1_WR_XNACK0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x00000000 - -// SDMA0_UTCL1_WR_XNACK1 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x00000000 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x00000004 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x00000008 -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x0000001a - -// SDMA0_UTCL1_TIMEOUT -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x00000000 -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x00000010 - -// SDMA0_UTCL1_PAGE -#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x00000000 -#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x00000001 -#define SDMA0_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x00000005 -#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x00000006 -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x00000009 - -// SDMA0_POWER_CNTL_IDLE -#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x00000000 -#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x00000010 -#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x00000018 - -// SDMA0_RELAX_ORDERING_LUT -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x00000000 -#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x00000001 -#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x00000002 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x00000003 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x00000004 -#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x00000005 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x00000006 -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x00000008 -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x00000009 -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0x0000000a -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0x0000000b -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0x0000000c -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0x0000000d -#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0x0000000e -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x0000001b -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x0000001c -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x0000001d -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x0000001e -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x0000001f - -// SDMA0_CHICKEN_BITS_2 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x00000000 - -// SDMA0_STATUS3_REG -#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x00000000 -#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x00000010 -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x00000014 - -// SDMA0_PHYSICAL_ADDR_LO -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x00000000 -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x00000001 -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x00000002 -#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0x0000000c - -// SDMA0_PHYSICAL_ADDR_HI -#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_PHASE2_QUANTUM -#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x00000000 -#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x00000008 -#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x0000001e - -// SDMA0_ERROR_LOG -#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x00000000 -#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x00000010 - -// SDMA0_PUB_DUMMY_REG0 -#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x00000000 - -// SDMA0_PUB_DUMMY_REG1 -#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x00000000 - -// SDMA0_PUB_DUMMY_REG2 -#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x00000000 - -// SDMA0_PUB_DUMMY_REG3 -#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x00000000 - -// SDMA0_F32_COUNTER -#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x00000000 - -// SDMA0_UNBREAKABLE -#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x00000000 - -// SDMA0_PERFMON_CNTL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x00000000 -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x00000001 -#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002 -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x0000000a -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x0000000b -#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000c - -// SDMA0_PERFCOUNTER0_RESULT -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// SDMA0_PERFCOUNTER1_RESULT -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// SDMA0_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x00000000 -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0x0000000e -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x0000001c - -// SDMA0_CRD_CNTL -#define SDMA0_CRD_CNTL__DRM_CREDIT__SHIFT 0x00000000 -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000007 -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d - -// SDMA0_MMHUB_TRUSTLVL -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x00000000 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x00000003 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x00000006 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x00000009 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0x0000000c -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0x0000000f -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x00000012 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x00000015 - -// SDMA0_GPU_IOV_VIOLATION_LOG -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x00000000 -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x00000001 -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x00000002 -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x00000012 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x00000013 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x00000014 -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x00000018 - -// SDMA0_ULV_CNTL -#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x00000000 -#define SDMA0_ULV_CNTL__ENTER_ULV_STATUS__SHIFT 0x0000001f - -// SDMA0_EA_DBIT_ADDR_DATA -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x00000000 - -// SDMA0_EA_DBIT_ADDR_INDEX -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_RB_CNTL -#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA0_GFX_RB_BASE -#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA0_GFX_RB_BASE_HI -#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_GFX_RB_RPTR -#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_GFX_RB_RPTR_HI -#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_GFX_RB_WPTR -#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_GFX_RB_WPTR_HI -#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_GFX_RB_WPTR_POLL_CNTL -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA0_GFX_RB_RPTR_ADDR_HI -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_GFX_RB_RPTR_ADDR_LO -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_GFX_IB_CNTL -#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA0_GFX_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA0_GFX_IB_RPTR -#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA0_GFX_IB_OFFSET -#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_GFX_IB_BASE_LO -#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA0_GFX_IB_BASE_HI -#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_GFX_IB_SIZE -#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA0_GFX_SKIP_CNTL -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA0_GFX_CONTEXT_STATUS -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA0_GFX_DOORBELL -#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA0_GFX_CONTEXT_CNTL -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x00000010 -#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x00000018 - -// SDMA0_GFX_DRM_WRAPPEDKEY0 -#define SDMA0_GFX_DRM_WRAPPEDKEY0__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_WRAPPEDKEY1 -#define SDMA0_GFX_DRM_WRAPPEDKEY1__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_WRAPPEDKEY2 -#define SDMA0_GFX_DRM_WRAPPEDKEY2__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_WRAPPEDKEY3 -#define SDMA0_GFX_DRM_WRAPPEDKEY3__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERKEY0 -#define SDMA0_GFX_DRM_COUNTERKEY0__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERKEY1 -#define SDMA0_GFX_DRM_COUNTERKEY1__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERKEY2 -#define SDMA0_GFX_DRM_COUNTERKEY2__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERKEY3 -#define SDMA0_GFX_DRM_COUNTERKEY3__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERDATA0 -#define SDMA0_GFX_DRM_COUNTERDATA0__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERDATA1 -#define SDMA0_GFX_DRM_COUNTERDATA1__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERDATA2 -#define SDMA0_GFX_DRM_COUNTERDATA2__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_COUNTERDATA3 -#define SDMA0_GFX_DRM_COUNTERDATA3__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_OFFSET -#define SDMA0_GFX_DRM_OFFSET__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_IVLOAD0 -#define SDMA0_GFX_DRM_IVLOAD0__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_IVLOAD1 -#define SDMA0_GFX_DRM_IVLOAD1__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_IVLOAD2 -#define SDMA0_GFX_DRM_IVLOAD2__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_IVLOAD3 -#define SDMA0_GFX_DRM_IVLOAD3__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_IVLOAD4 -#define SDMA0_GFX_DRM_IVLOAD4__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_DRM_UNROLLKEY -#define SDMA0_GFX_DRM_UNROLLKEY__VALUE__SHIFT 0x00000000 - -// SDMA0_GFX_AES -#define SDMA0_GFX_AES__AES_TRUSTED__SHIFT 0x00000000 - -// SDMA0_GFX_STATUS -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA0_GFX_DOORBELL_LOG -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA0_GFX_WATERMARK -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA0_GFX_DOORBELL_OFFSET -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_GFX_CSA_ADDR_LO -#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_GFX_CSA_ADDR_HI -#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_GFX_IB_SUB_REMAIN -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA0_GFX_PREEMPT -#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA0_GFX_DUMMY_REG -#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA0_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_GFX_RB_AQL_CNTL -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA0_GFX_MINOR_PTR_UPDATE -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA1 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA2 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA3 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA4 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA5 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA6 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA7 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_DATA8 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA0_GFX_MIDCMD_CNTL -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// SDMA0_PAGE_RB_CNTL -#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA0_PAGE_RB_BASE -#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_BASE_HI -#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_RPTR -#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_RPTR_HI -#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_WPTR -#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_WPTR_HI -#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_WPTR_POLL_CNTL -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA0_PAGE_RB_RPTR_ADDR_HI -#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_RPTR_ADDR_LO -#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_PAGE_IB_CNTL -#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA0_PAGE_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA0_PAGE_IB_RPTR -#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA0_PAGE_IB_OFFSET -#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_PAGE_IB_BASE_LO -#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA0_PAGE_IB_BASE_HI -#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_PAGE_IB_SIZE -#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA0_PAGE_SKIP_CNTL -#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA0_PAGE_CONTEXT_STATUS -#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA0_PAGE_DOORBELL -#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA0_PAGE_STATUS -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA0_PAGE_DOORBELL_LOG -#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA0_PAGE_WATERMARK -#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA0_PAGE_DOORBELL_OFFSET -#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_PAGE_CSA_ADDR_LO -#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_PAGE_CSA_ADDR_HI -#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_PAGE_IB_SUB_REMAIN -#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA0_PAGE_PREEMPT -#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA0_PAGE_DUMMY_REG -#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_PAGE_RB_AQL_CNTL -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA0_PAGE_MINOR_PTR_UPDATE -#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA0 -#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA1 -#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA2 -#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA3 -#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA4 -#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA5 -#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA6 -#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA7 -#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_DATA8 -#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA0_PAGE_MIDCMD_CNTL -#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// SDMA0_RLC0_RB_CNTL -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA0_RLC0_RB_BASE -#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_BASE_HI -#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_RPTR -#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_RPTR_HI -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_WPTR -#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_WPTR_HI -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_WPTR_POLL_CNTL -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA0_RLC0_RB_RPTR_ADDR_HI -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_RPTR_ADDR_LO -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_RLC0_IB_CNTL -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA0_RLC0_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA0_RLC0_IB_RPTR -#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA0_RLC0_IB_OFFSET -#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_RLC0_IB_BASE_LO -#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA0_RLC0_IB_BASE_HI -#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC0_IB_SIZE -#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA0_RLC0_SKIP_CNTL -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA0_RLC0_CONTEXT_STATUS -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA0_RLC0_DOORBELL -#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA0_RLC0_STATUS -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA0_RLC0_DOORBELL_LOG -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA0_RLC0_WATERMARK -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA0_RLC0_DOORBELL_OFFSET -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_RLC0_CSA_ADDR_LO -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_RLC0_CSA_ADDR_HI -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC0_IB_SUB_REMAIN -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA0_RLC0_PREEMPT -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA0_RLC0_DUMMY_REG -#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_RLC0_RB_AQL_CNTL -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA0_RLC0_MINOR_PTR_UPDATE -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA1 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA2 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA3 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA4 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA5 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA6 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA7 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_DATA8 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA0_RLC0_MIDCMD_CNTL -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// SDMA0_RLC1_RB_CNTL -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA0_RLC1_RB_BASE -#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_BASE_HI -#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_RPTR -#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_RPTR_HI -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_WPTR -#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_WPTR_HI -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_WPTR_POLL_CNTL -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA0_RLC1_RB_RPTR_ADDR_HI -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_RPTR_ADDR_LO -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_RLC1_IB_CNTL -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA0_RLC1_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA0_RLC1_IB_RPTR -#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA0_RLC1_IB_OFFSET -#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_RLC1_IB_BASE_LO -#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA0_RLC1_IB_BASE_HI -#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC1_IB_SIZE -#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA0_RLC1_SKIP_CNTL -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA0_RLC1_CONTEXT_STATUS -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA0_RLC1_DOORBELL -#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA0_RLC1_STATUS -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA0_RLC1_DOORBELL_LOG -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA0_RLC1_WATERMARK -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA0_RLC1_DOORBELL_OFFSET -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA0_RLC1_CSA_ADDR_LO -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_RLC1_CSA_ADDR_HI -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC1_IB_SUB_REMAIN -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA0_RLC1_PREEMPT -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA0_RLC1_DUMMY_REG -#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA0_RLC1_RB_AQL_CNTL -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA0_RLC1_MINOR_PTR_UPDATE -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA1 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA2 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA3 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA4 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA5 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA6 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA7 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_DATA8 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA0_RLC1_MIDCMD_CNTL -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// SDMA1_UCODE_ADDR -#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x00000000 - -// SDMA1_UCODE_DATA -#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x00000000 - -// SDMA1_REGISTER_SECURITY_CNTL -#define SDMA1_REGISTER_SECURITY_CNTL__ENABLE__SHIFT 0x00000000 - -// SDMA1_VM_CNTL -#define SDMA1_VM_CNTL__CMD__SHIFT 0x00000000 - -// SDMA1_VM_CTX_LO -#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_VM_CTX_HI -#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_ACTIVE_FCN_ID -#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x00000000 -#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x00000004 -#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x0000001f - -// SDMA1_VM_CTX_CNTL -#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x00000000 -#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x00000004 - -// SDMA1_VIRT_RESET_REQ -#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x00000000 -#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x0000001f - -// SDMA1_CONTEXT_REG_TYPE0 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x00000000 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x00000001 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x00000002 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x00000003 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x00000004 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x00000005 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x00000006 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x00000007 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x00000008 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x00000009 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0x0000000a -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0x0000000b -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0x0000000c -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0x0000000d -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0x0000000e -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0x0000000f -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x00000010 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x00000011 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x00000012 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x00000013 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY0__SHIFT 0x00000014 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY1__SHIFT 0x00000015 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY2__SHIFT 0x00000016 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_WRAPPEDKEY3__SHIFT 0x00000017 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY0__SHIFT 0x00000018 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY1__SHIFT 0x00000019 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY2__SHIFT 0x0000001a -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERKEY3__SHIFT 0x0000001b -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA0__SHIFT 0x0000001c -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA1__SHIFT 0x0000001d -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA2__SHIFT 0x0000001e -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DRM_COUNTERDATA3__SHIFT 0x0000001f - -// SDMA1_CONTEXT_REG_TYPE1 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_OFFSET__SHIFT 0x00000000 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD0__SHIFT 0x00000001 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD1__SHIFT 0x00000002 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD2__SHIFT 0x00000003 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD3__SHIFT 0x00000004 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_IVLOAD4__SHIFT 0x00000005 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DRM_UNROLLKEY__SHIFT 0x00000006 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_AES__SHIFT 0x00000007 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x00000008 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x00000009 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0x0000000a -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0x0000000b -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0x0000000c -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0x0000000d -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0x0000000e -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0x0000000f -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x00000010 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x00000011 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000012 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000013 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x00000014 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x00000015 -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x00000016 - -// SDMA1_CONTEXT_REG_TYPE2 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x00000000 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x00000001 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x00000002 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x00000003 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x00000004 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x00000005 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x00000006 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x00000007 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x00000008 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x00000009 -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x0000000a - -// SDMA1_CONTEXT_REG_TYPE3 -#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x00000000 - -// SDMA1_PUB_REG_TYPE0 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x00000000 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x00000001 -#define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL__SHIFT 0x00000002 -#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x00000003 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x00000004 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x00000005 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x00000006 -#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x00000007 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x00000008 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x00000009 -#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0x0000000a -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0x0000000b -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0x0000000c -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0x0000000d -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0x0000000e -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0x0000000f -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x00000010 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x00000011 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x00000012 -#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x00000013 -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x00000019 -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x0000001a -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x0000001b -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x0000001c -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x0000001d -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x0000001e -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x0000001f - -// SDMA1_PUB_REG_TYPE1 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x00000000 -#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x00000001 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x00000002 -#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x00000003 -#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x00000004 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x00000005 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x00000006 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x00000007 -#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x00000008 -#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x00000009 -#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0x0000000a -#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0x0000000b -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0x0000000c -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0x0000000d -#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0x0000000e -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0x0000000f -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x00000010 -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x00000011 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x00000012 -#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x00000013 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x00000014 -#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x00000015 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x00000016 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x00000017 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x00000018 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x00000019 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x0000001a -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x0000001b -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x0000001c -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x0000001d -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x0000001e -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x0000001f - -// SDMA1_PUB_REG_TYPE2 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x00000000 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x00000001 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x00000002 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x00000003 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x00000004 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x00000005 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x00000006 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x00000007 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x00000008 -#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x00000009 -#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0x0000000a -#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0x0000000b -#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0x0000000c -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0x0000000d -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0x0000000e -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0x0000000f -#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x00000010 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x00000011 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x00000012 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x00000013 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x00000014 -#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x00000015 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x00000016 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x00000017 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x00000018 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x00000019 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x0000001a -#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x0000001b -#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x0000001c -#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x0000001d -#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x0000001e -#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x0000001f - -// SDMA1_PUB_REG_TYPE3 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x00000000 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x00000001 -#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x00000002 - -// SDMA1_CONTEXT_GROUP_BOUNDARY -#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x00000000 - -// SDMA1_POWER_CNTL -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x00000008 -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x00000009 -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0x0000000a -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0x0000000b -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0x0000000c - -// SDMA1_CLK_CTRL -#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0x0000000c -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// SDMA1_CNTL -#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x00000000 -#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x00000001 -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x00000002 -#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x00000003 -#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000005 -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x00000011 -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x00000012 -#define SDMA1_CNTL__DRM_RESTORE_ENABLE__SHIFT 0x00000013 -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x0000001c -#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x0000001d -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x0000001e - -// SDMA1_CHICKEN_BITS -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x00000000 -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x00000001 -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x00000002 -#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x00000008 -#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0x0000000a -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x00000010 -#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x00000011 -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x00000014 -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x00000017 -#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x00000019 -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x0000001a -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x0000001c -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x0000001e - -// SDMA1_GB_ADDR_CONFIG -#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 -#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 -#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 -#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0x0000000c -#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x00000013 - -// SDMA1_GB_ADDR_CONFIG_READ -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x00000000 -#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 -#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0x0000000c -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x00000013 - -// SDMA1_RB_RPTR_FETCH_HI -#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x00000000 - -// SDMA1_RB_RPTR_FETCH -#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x00000002 - -// SDMA1_IB_OFFSET_FETCH -#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x00000002 - -// SDMA1_PROGRAM -#define SDMA1_PROGRAM__STREAM__SHIFT 0x00000000 - -// SDMA1_STATUS_REG -#define SDMA1_STATUS_REG__IDLE__SHIFT 0x00000000 -#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x00000001 -#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x00000002 -#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x00000003 -#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x00000004 -#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x00000005 -#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x00000006 -#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x00000007 -#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x00000008 -#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x00000009 -#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0x0000000a -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0x0000000b -#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0x0000000c -#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0x0000000d -#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0x0000000e -#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0x0000000f -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x00000010 -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x00000011 -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x00000012 -#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x00000013 -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x00000014 -#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x00000015 -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x00000016 -#define SDMA1_STATUS_REG__DRM_IDLE__SHIFT 0x00000017 -#define SDMA1_STATUS_REG__DRM_MASK_FULL__SHIFT 0x00000018 -#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x00000019 -#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x0000001a -#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x0000001b -#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x0000001c -#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x0000001e -#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x0000001f - -// SDMA1_STATUS1_REG -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x00000000 -#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x00000001 -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x00000002 -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x00000003 -#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x00000004 -#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x00000005 -#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x00000006 -#define SDMA1_STATUS1_REG__CE_DRM_IDLE__SHIFT 0x00000007 -#define SDMA1_STATUS1_REG__CE_DRM1_IDLE__SHIFT 0x00000008 -#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x00000009 -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0x0000000a -#define SDMA1_STATUS1_REG__CE_DRM_FULL__SHIFT 0x0000000b -#define SDMA1_STATUS1_REG__CE_DRM1_FULL__SHIFT 0x0000000c -#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0x0000000d -#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0x0000000e -#define SDMA1_STATUS1_REG__EX_START__SHIFT 0x0000000f -#define SDMA1_STATUS1_REG__DRM_CTX_RESTORE__SHIFT 0x00000010 -#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x00000011 -#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x00000012 - -// SDMA1_RD_BURST_CNTL -#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x00000000 - -// SDMA1_HBM_PAGE_CONFIG -#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x00000000 - -// SDMA1_UCODE_CHECKSUM -#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x00000000 - -// SDMA1_F32_CNTL -#define SDMA1_F32_CNTL__HALT__SHIFT 0x00000000 -#define SDMA1_F32_CNTL__STEP__SHIFT 0x00000001 -#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x00000002 - -// SDMA1_FREEZE -#define SDMA1_FREEZE__PREEMPT__SHIFT 0x00000000 -#define SDMA1_FREEZE__FREEZE__SHIFT 0x00000004 -#define SDMA1_FREEZE__FROZEN__SHIFT 0x00000005 -#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x00000006 - -// SDMA1_PHASE0_QUANTUM -#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x00000000 -#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x00000008 -#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x0000001e - -// SDMA1_PHASE1_QUANTUM -#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x00000000 -#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x00000008 -#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x0000001e - -// SDMA1_EDC_CONFIG -#define SDMA1_EDC_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x00000001 -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x00000002 - -// SDMA1_BA_THRESHOLD -#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x00000000 -#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x00000010 - -// SDMA1_ID -#define SDMA1_ID__DEVICE_ID__SHIFT 0x00000000 - -// SDMA1_VERSION -#define SDMA1_VERSION__MINVER__SHIFT 0x00000000 -#define SDMA1_VERSION__MAJVER__SHIFT 0x00000008 -#define SDMA1_VERSION__REV__SHIFT 0x00000010 - -// SDMA1_EDC_COUNTER -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x00000000 -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x00000001 -#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x00000002 -#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x00000003 -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x00000004 -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x00000005 -#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x00000006 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x00000007 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x00000008 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x00000009 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x0000000a -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x0000000b -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0x0000000c -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0x0000000d -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0x0000000e -#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x0000000f -#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x00000010 - -// SDMA1_EDC_COUNTER_CLEAR -#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x00000000 - -// SDMA1_STATUS2_REG -#define SDMA1_STATUS2_REG__ID__SHIFT 0x00000000 -#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x00000002 -#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x00000010 - -// SDMA1_ATOMIC_CNTL -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x00000000 -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x0000001f - -// SDMA1_ATOMIC_PREOP_LO -#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x00000000 - -// SDMA1_ATOMIC_PREOP_HI -#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x00000000 - -// SDMA1_UTCL1_CNTL -#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x00000000 -#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x00000001 -#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x0000000b -#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x0000000e -#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x00000018 -#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x0000001d - -// SDMA1_UTCL1_WATERMK -#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x00000000 -#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x0000000a -#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x00000012 -#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x0000001a - -// SDMA1_UTCL1_RD_STATUS -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x00000000 -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x00000001 -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x00000002 -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x00000003 -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x00000004 -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x00000005 -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x00000006 -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x00000007 -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x00000008 -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x00000009 -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x0000000a -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x0000000b -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x0000000c -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0x0000000d -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x0000000e -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0x0000000f -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x00000010 -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x00000011 -#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x00000012 -#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x00000013 -#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x00000014 -#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x00000015 -#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x00000016 -#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x0000001a -#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x0000001d -#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x0000001e -#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x0000001f - -// SDMA1_UTCL1_WR_STATUS -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x00000000 -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x00000001 -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x00000002 -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x00000003 -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x00000004 -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x00000005 -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x00000006 -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x00000007 -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x00000008 -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x00000009 -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x0000000a -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x0000000b -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x0000000c -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0x0000000d -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x0000000e -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0x0000000f -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x00000010 -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x00000011 -#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x00000012 -#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x00000013 -#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x00000014 -#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x00000015 -#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x00000016 -#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x00000019 -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x0000001c -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x0000001d -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x0000001e -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x0000001f - -// SDMA1_UTCL1_INV0 -#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x00000000 -#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x00000001 -#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x00000002 -#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x00000003 -#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x00000004 -#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x00000005 -#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x00000006 -#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x00000007 -#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x00000008 -#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x00000009 -#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0x0000000a -#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0x0000000b -#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0x0000000c -#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x0000001c - -// SDMA1_UTCL1_INV1 -#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x00000000 - -// SDMA1_UTCL1_INV2 -#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x00000000 - -// SDMA1_UTCL1_RD_XNACK0 -#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x00000000 - -// SDMA1_UTCL1_RD_XNACK1 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x00000000 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x00000004 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x00000008 -#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x0000001a - -// SDMA1_UTCL1_WR_XNACK0 -#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x00000000 - -// SDMA1_UTCL1_WR_XNACK1 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x00000000 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x00000004 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x00000008 -#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x0000001a - -// SDMA1_UTCL1_TIMEOUT -#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x00000000 -#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x00000010 - -// SDMA1_UTCL1_PAGE -#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x00000000 -#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x00000001 -#define SDMA1_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x00000005 -#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x00000006 -#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x00000009 - -// SDMA1_POWER_CNTL_IDLE -#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x00000000 -#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x00000010 -#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x00000018 - -// SDMA1_RELAX_ORDERING_LUT -#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x00000000 -#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x00000001 -#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x00000002 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x00000003 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x00000004 -#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x00000005 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x00000006 -#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x00000008 -#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x00000009 -#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0x0000000a -#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0x0000000b -#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0x0000000c -#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0x0000000d -#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0x0000000e -#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x0000001b -#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x0000001c -#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x0000001d -#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x0000001e -#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x0000001f - -// SDMA1_CHICKEN_BITS_2 -#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x00000000 - -// SDMA1_STATUS3_REG -#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x00000000 -#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x00000010 -#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x00000014 - -// SDMA1_PHYSICAL_ADDR_LO -#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x00000000 -#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x00000001 -#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x00000002 -#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0x0000000c - -// SDMA1_PHYSICAL_ADDR_HI -#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_PHASE2_QUANTUM -#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x00000000 -#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x00000008 -#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x0000001e - -// SDMA1_ERROR_LOG -#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x00000000 -#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x00000010 - -// SDMA1_PUB_DUMMY_REG0 -#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x00000000 - -// SDMA1_PUB_DUMMY_REG1 -#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x00000000 - -// SDMA1_PUB_DUMMY_REG2 -#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x00000000 - -// SDMA1_PUB_DUMMY_REG3 -#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x00000000 - -// SDMA1_F32_COUNTER -#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x00000000 - -// SDMA1_UNBREAKABLE -#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x00000000 - -// SDMA1_PERFMON_CNTL -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x00000000 -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x00000001 -#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002 -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x0000000a -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x0000000b -#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000c - -// SDMA1_PERFCOUNTER0_RESULT -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// SDMA1_PERFCOUNTER1_RESULT -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000 - -// SDMA1_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x00000000 -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0x0000000e -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x0000001c - -// SDMA1_CRD_CNTL -#define SDMA1_CRD_CNTL__DRM_CREDIT__SHIFT 0x00000000 -#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000007 -#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d - -// SDMA1_MMHUB_TRUSTLVL -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x00000000 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x00000003 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x00000006 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x00000009 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0x0000000c -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0x0000000f -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x00000012 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x00000015 - -// SDMA1_GPU_IOV_VIOLATION_LOG -#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x00000000 -#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x00000001 -#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x00000002 -#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x00000012 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x00000013 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x00000014 -#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x00000018 - -// SDMA1_ULV_CNTL -#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x00000000 -#define SDMA1_ULV_CNTL__ENTER_ULV_STATUS__SHIFT 0x0000001f - -// SDMA1_EA_DBIT_ADDR_DATA -#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x00000000 - -// SDMA1_EA_DBIT_ADDR_INDEX -#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x00000000 - -// SDMA1_GFX_RB_CNTL -#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA1_GFX_RB_BASE -#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA1_GFX_RB_BASE_HI -#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_GFX_RB_RPTR -#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_GFX_RB_RPTR_HI -#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_GFX_RB_WPTR -#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_GFX_RB_WPTR_HI -#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_GFX_RB_WPTR_POLL_CNTL -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA1_GFX_RB_RPTR_ADDR_HI -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_GFX_RB_RPTR_ADDR_LO -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_GFX_IB_CNTL -#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA1_GFX_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA1_GFX_IB_RPTR -#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA1_GFX_IB_OFFSET -#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_GFX_IB_BASE_LO -#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA1_GFX_IB_BASE_HI -#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_GFX_IB_SIZE -#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA1_GFX_SKIP_CNTL -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA1_GFX_CONTEXT_STATUS -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA1_GFX_DOORBELL -#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA1_GFX_CONTEXT_CNTL -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x00000010 -#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x00000018 - -// SDMA1_GFX_AES -#define SDMA1_GFX_AES__AES_TRUSTED__SHIFT 0x00000000 - -// SDMA1_GFX_STATUS -#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA1_GFX_DOORBELL_LOG -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA1_GFX_WATERMARK -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA1_GFX_DOORBELL_OFFSET -#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_GFX_CSA_ADDR_LO -#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_GFX_CSA_ADDR_HI -#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_GFX_IB_SUB_REMAIN -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA1_GFX_PREEMPT -#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA1_GFX_DUMMY_REG -#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA1_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_GFX_RB_AQL_CNTL -#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA1_GFX_MINOR_PTR_UPDATE -#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA0 -#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA1 -#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA2 -#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA3 -#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA4 -#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA5 -#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA6 -#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA7 -#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_DATA8 -#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA1_GFX_MIDCMD_CNTL -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// SDMA1_PAGE_RB_CNTL -#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA1_PAGE_RB_BASE -#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_BASE_HI -#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_RPTR -#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_RPTR_HI -#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_WPTR -#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_WPTR_HI -#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_WPTR_POLL_CNTL -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA1_PAGE_RB_RPTR_ADDR_HI -#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_RPTR_ADDR_LO -#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_PAGE_IB_CNTL -#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA1_PAGE_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA1_PAGE_IB_RPTR -#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA1_PAGE_IB_OFFSET -#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_PAGE_IB_BASE_LO -#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA1_PAGE_IB_BASE_HI -#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_PAGE_IB_SIZE -#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA1_PAGE_SKIP_CNTL -#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA1_PAGE_CONTEXT_STATUS -#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA1_PAGE_DOORBELL -#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA1_PAGE_STATUS -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA1_PAGE_DOORBELL_LOG -#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA1_PAGE_WATERMARK -#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA1_PAGE_DOORBELL_OFFSET -#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_PAGE_CSA_ADDR_LO -#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_PAGE_CSA_ADDR_HI -#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_PAGE_IB_SUB_REMAIN -#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA1_PAGE_PREEMPT -#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA1_PAGE_DUMMY_REG -#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_PAGE_RB_AQL_CNTL -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA1_PAGE_MINOR_PTR_UPDATE -#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA0 -#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA1 -#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA2 -#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA3 -#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA4 -#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA5 -#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA6 -#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA7 -#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_DATA8 -#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA1_PAGE_MIDCMD_CNTL -#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// SDMA1_RLC0_RB_CNTL -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA1_RLC0_RB_BASE -#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_BASE_HI -#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_RPTR -#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_RPTR_HI -#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_WPTR -#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_WPTR_HI -#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_WPTR_POLL_CNTL -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA1_RLC0_RB_RPTR_ADDR_HI -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_RPTR_ADDR_LO -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_RLC0_IB_CNTL -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA1_RLC0_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA1_RLC0_IB_RPTR -#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA1_RLC0_IB_OFFSET -#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_RLC0_IB_BASE_LO -#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA1_RLC0_IB_BASE_HI -#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC0_IB_SIZE -#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA1_RLC0_SKIP_CNTL -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA1_RLC0_CONTEXT_STATUS -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA1_RLC0_DOORBELL -#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA1_RLC0_STATUS -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA1_RLC0_DOORBELL_LOG -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA1_RLC0_WATERMARK -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA1_RLC0_DOORBELL_OFFSET -#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_RLC0_CSA_ADDR_LO -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_RLC0_CSA_ADDR_HI -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC0_IB_SUB_REMAIN -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA1_RLC0_PREEMPT -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA1_RLC0_DUMMY_REG -#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_RLC0_RB_AQL_CNTL -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA1_RLC0_MINOR_PTR_UPDATE -#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA0 -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA1 -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA2 -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA3 -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA4 -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA5 -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA6 -#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA7 -#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_DATA8 -#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA1_RLC0_MIDCMD_CNTL -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// SDMA1_RLC1_RB_CNTL -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x00000001 -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 -#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x00000017 -#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x00000018 - -// SDMA1_RLC1_RB_BASE -#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_BASE_HI -#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_RPTR -#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_RPTR_HI -#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_WPTR -#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_WPTR_HI -#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_WPTR_POLL_CNTL -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x00000001 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x00000002 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x00000004 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// SDMA1_RLC1_RB_RPTR_ADDR_HI -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_RPTR_ADDR_LO -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_RLC1_IB_CNTL -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 -#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x00000010 -#define SDMA1_RLC1_IB_CNTL__IB_PRIV__SHIFT 0x0000001f - -// SDMA1_RLC1_IB_RPTR -#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x00000002 - -// SDMA1_RLC1_IB_OFFSET -#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_RLC1_IB_BASE_LO -#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x00000005 - -// SDMA1_RLC1_IB_BASE_HI -#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC1_IB_SIZE -#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x00000000 - -// SDMA1_RLC1_SKIP_CNTL -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 - -// SDMA1_RLC1_CONTEXT_STATUS -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x00000008 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x00000009 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a - -// SDMA1_RLC1_DOORBELL -#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x0000001c -#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x0000001e - -// SDMA1_RLC1_STATUS -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000000 -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x00000008 - -// SDMA1_RLC1_DOORBELL_LOG -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 -#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x00000002 - -// SDMA1_RLC1_WATERMARK -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x00000000 -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x00000010 - -// SDMA1_RLC1_DOORBELL_OFFSET -#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 - -// SDMA1_RLC1_CSA_ADDR_LO -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_RLC1_CSA_ADDR_HI -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC1_IB_SUB_REMAIN -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 - -// SDMA1_RLC1_PREEMPT -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 - -// SDMA1_RLC1_DUMMY_REG -#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x00000000 - -// SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x00000002 - -// SDMA1_RLC1_RB_AQL_CNTL -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 -#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 - -// SDMA1_RLC1_MINOR_PTR_UPDATE -#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA0 -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA1 -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA2 -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA3 -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA4 -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA5 -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA6 -#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA7 -#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_DATA8 -#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x00000000 - -// SDMA1_RLC1_MIDCMD_CNTL -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x00000000 -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x00000001 -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x00000004 -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x00000008 - -// MP0_SMNIF_ERROR -#define MP0_SMNIF_ERROR__RESERVED__SHIFT 0x00000000 - -// MP0_SFUSE_PUB -#define MP0_SFUSE_PUB__DATA__SHIFT 0x00000000 - -// MP0_FW_DEBUG_CNT0 -#define MP0_FW_DEBUG_CNT0__DATA__SHIFT 0x00000000 - -// MP0_FW_DEBUG_CNT1 -#define MP0_FW_DEBUG_CNT1__DATA__SHIFT 0x00000000 - -// MP0_FW_DEBUG_CNT2 -#define MP0_FW_DEBUG_CNT2__DATA__SHIFT 0x00000000 - -// MP0_FW_DEBUG_CNT3 -#define MP0_FW_DEBUG_CNT3__DATA__SHIFT 0x00000000 - -// MP0_FW_DEBUG_SIGNAL0 -#define MP0_FW_DEBUG_SIGNAL0__DATA__SHIFT 0x00000000 - -// MP0_FW_DEBUG_SIGNAL1 -#define MP0_FW_DEBUG_SIGNAL1__DATA__SHIFT 0x00000000 - -// MP0_DSM_ENABLE -#define MP0_DSM_ENABLE__MP0_ENB_EDBGREQ__SHIFT 0x00000000 -#define MP0_DSM_ENABLE__MP0_ENB_DBGRESTART__SHIFT 0x00000001 -#define MP0_DSM_ENABLE__MP0_ENB_UNUSED__SHIFT 0x00000002 -#define MP0_DSM_ENABLE__MP0_ENB_DSMINT__SHIFT 0x00000003 - -// MP0_SOC_INFO -#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x00000000 -#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x00000002 - -// MP0_MUTEX_0 -#define MP0_MUTEX_0__MUTEX__SHIFT 0x00000000 - -// MP0_MUTEX_1 -#define MP0_MUTEX_1__MUTEX__SHIFT 0x00000000 - -// MP0_MUTEX_2 -#define MP0_MUTEX_2__MUTEX__SHIFT 0x00000000 - -// MP0_MUTEX_3 -#define MP0_MUTEX_3__MUTEX__SHIFT 0x00000000 - -// MP0_PUB_SCRATCH0 -#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x00000000 - -// MP0_PUB_SCRATCH1 -#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x00000000 - -// MP0_PUB_SCRATCH2 -#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x00000000 - -// MP0_PUB_SCRATCH3 -#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x00000000 - -// MP0_RSMU_SECINTR -#define MP0_RSMU_SECINTR__RESEREVED__SHIFT 0x00000000 - -// MP0_FW_INTF -#define MP0_FW_INTF__FRA_BOOT_TDR__SHIFT 0x00000000 -#define MP0_FW_INTF__FUSE_VALID__SHIFT 0x00000001 -#define MP0_FW_INTF__FUSE_ERROR__SHIFT 0x00000002 -#define MP0_FW_INTF__FUSE_SSTATE__SHIFT 0x00000003 -#define MP0_FW_INTF__FRA_EN_TDR__SHIFT 0x00000007 -#define MP0_FW_INTF__AEB_VALID__SHIFT 0x00000008 -#define MP0_FW_INTF__AEB_DATA__SHIFT 0x00000009 -#define MP0_FW_INTF__SS_UNK__SHIFT 0x00000010 -#define MP0_FW_INTF__SS_BLANK__SHIFT 0x00000011 -#define MP0_FW_INTF__SS_PROTO__SHIFT 0x00000012 -#define MP0_FW_INTF__SS_SECURE__SHIFT 0x00000013 -#define MP0_FW_INTF__SS_FRA__SHIFT 0x00000014 -#define MP0_FW_INTF__SS_NOTR__SHIFT 0x00000015 - -// MP0_FW_CHRONO_LO -#define MP0_FW_CHRONO_LO__COUNT__SHIFT 0x00000000 - -// MP0_FW_CHRONO_HI -#define MP0_FW_CHRONO_HI__COUNT__SHIFT 0x00000000 - -// MP0_PIC0_MASK_0 -#define MP0_PIC0_MASK_0__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC0_MASK_0__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC0_MASK_0__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC0_MASK_0__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC0_MASK_0__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC0_MASK_0__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC0_MASK_0__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC0_MASK_0__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC0_MASK_0__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC0_MASK_0__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC0_MASK_0__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC0_MASK_0__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC0_MASK_0__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC0_MASK_0__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC0_MASK_0__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC0_MASK_0__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC0_MASK_0__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC0_MASK_0__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC0_MASK_0__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC0_MASK_0__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC0_MASK_0__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC0_MASK_0__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC0_MASK_0__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC0_MASK_0__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC0_MASK_0__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC0_MASK_0__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC0_MASK_0__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC0_MASK_0__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC0_MASK_0__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC0_MASK_0__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC0_MASK_0__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC0_MASK_0__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC0_MASK_1 -#define MP0_PIC0_MASK_1__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC0_MASK_1__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC0_MASK_1__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC0_MASK_1__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC0_MASK_1__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC0_MASK_1__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC0_MASK_1__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC0_MASK_1__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC0_MASK_1__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC0_MASK_1__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC0_MASK_1__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC0_MASK_1__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC0_MASK_1__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC0_MASK_1__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC0_MASK_1__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC0_MASK_1__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC0_MASK_1__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC0_MASK_1__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC0_MASK_1__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC0_MASK_1__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC0_MASK_1__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC0_MASK_1__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC0_MASK_1__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC0_MASK_1__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC0_MASK_1__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC0_MASK_1__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC0_MASK_1__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC0_MASK_1__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC0_MASK_1__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC0_MASK_1__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC0_MASK_1__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC0_MASK_1__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC0_MASK_2 -#define MP0_PIC0_MASK_2__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC0_MASK_2__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC0_MASK_2__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC0_MASK_2__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC0_MASK_2__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC0_MASK_2__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC0_MASK_2__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC0_MASK_2__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC0_MASK_2__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC0_MASK_2__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC0_MASK_2__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC0_MASK_2__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC0_MASK_2__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC0_MASK_2__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC0_MASK_2__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC0_MASK_2__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC0_MASK_2__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC0_MASK_2__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC0_MASK_2__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC0_MASK_2__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC0_MASK_2__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC0_MASK_2__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC0_MASK_2__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC0_MASK_2__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC0_MASK_2__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC0_MASK_2__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC0_MASK_2__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC0_MASK_2__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC0_MASK_2__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC0_MASK_2__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC0_MASK_2__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC0_MASK_2__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC0_MASK_3 -#define MP0_PIC0_MASK_3__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC0_MASK_3__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC0_MASK_3__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC0_MASK_3__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC0_MASK_3__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC0_MASK_3__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC0_MASK_3__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC0_MASK_3__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC0_MASK_3__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC0_MASK_3__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC0_MASK_3__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC0_MASK_3__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC0_MASK_3__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC0_MASK_3__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC0_MASK_3__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC0_MASK_3__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC0_MASK_3__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC0_MASK_3__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC0_MASK_3__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC0_MASK_3__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC0_MASK_3__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC0_MASK_3__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC0_MASK_3__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC0_MASK_3__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC0_MASK_3__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC0_MASK_3__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC0_MASK_3__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC0_MASK_3__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC0_MASK_3__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC0_MASK_3__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC0_MASK_3__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC0_MASK_3__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC0_STATUS_0 -#define MP0_PIC0_STATUS_0__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC0_STATUS_0__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC0_STATUS_0__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC0_STATUS_0__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC0_STATUS_0__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC0_STATUS_0__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC0_STATUS_0__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC0_STATUS_0__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC0_STATUS_0__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC0_STATUS_0__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC0_STATUS_0__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC0_STATUS_0__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC0_STATUS_0__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC0_STATUS_0__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC0_STATUS_0__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC0_STATUS_0__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC0_STATUS_0__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC0_STATUS_0__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC0_STATUS_0__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC0_STATUS_0__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC0_STATUS_0__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC0_STATUS_0__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC0_STATUS_0__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC0_STATUS_0__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC0_STATUS_0__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC0_STATUS_0__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC0_STATUS_0__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC0_STATUS_0__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC0_STATUS_0__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC0_STATUS_0__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC0_STATUS_0__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC0_STATUS_0__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC0_STATUS_1 -#define MP0_PIC0_STATUS_1__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC0_STATUS_1__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC0_STATUS_1__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC0_STATUS_1__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC0_STATUS_1__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC0_STATUS_1__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC0_STATUS_1__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC0_STATUS_1__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC0_STATUS_1__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC0_STATUS_1__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC0_STATUS_1__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC0_STATUS_1__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC0_STATUS_1__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC0_STATUS_1__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC0_STATUS_1__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC0_STATUS_1__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC0_STATUS_1__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC0_STATUS_1__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC0_STATUS_1__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC0_STATUS_1__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC0_STATUS_1__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC0_STATUS_1__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC0_STATUS_1__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC0_STATUS_1__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC0_STATUS_1__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC0_STATUS_1__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC0_STATUS_1__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC0_STATUS_1__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC0_STATUS_1__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC0_STATUS_1__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC0_STATUS_1__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC0_STATUS_1__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC0_STATUS_2 -#define MP0_PIC0_STATUS_2__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC0_STATUS_2__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC0_STATUS_2__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC0_STATUS_2__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC0_STATUS_2__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC0_STATUS_2__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC0_STATUS_2__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC0_STATUS_2__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC0_STATUS_2__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC0_STATUS_2__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC0_STATUS_2__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC0_STATUS_2__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC0_STATUS_2__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC0_STATUS_2__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC0_STATUS_2__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC0_STATUS_2__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC0_STATUS_2__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC0_STATUS_2__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC0_STATUS_2__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC0_STATUS_2__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC0_STATUS_2__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC0_STATUS_2__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC0_STATUS_2__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC0_STATUS_2__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC0_STATUS_2__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC0_STATUS_2__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC0_STATUS_2__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC0_STATUS_2__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC0_STATUS_2__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC0_STATUS_2__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC0_STATUS_2__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC0_STATUS_2__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC0_STATUS_3 -#define MP0_PIC0_STATUS_3__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC0_STATUS_3__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC0_STATUS_3__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC0_STATUS_3__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC0_STATUS_3__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC0_STATUS_3__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC0_STATUS_3__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC0_STATUS_3__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC0_STATUS_3__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC0_STATUS_3__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC0_STATUS_3__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC0_STATUS_3__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC0_STATUS_3__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC0_STATUS_3__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC0_STATUS_3__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC0_STATUS_3__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC0_STATUS_3__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC0_STATUS_3__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC0_STATUS_3__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC0_STATUS_3__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC0_STATUS_3__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC0_STATUS_3__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC0_STATUS_3__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC0_STATUS_3__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC0_STATUS_3__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC0_STATUS_3__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC0_STATUS_3__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC0_STATUS_3__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC0_STATUS_3__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC0_STATUS_3__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC0_STATUS_3__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC0_STATUS_3__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC0_INTR -#define MP0_PIC0_INTR__INTR_LINE__SHIFT 0x00000000 -#define MP0_PIC0_INTR__RESERVED__SHIFT 0x00000001 - -// MP0_PIC0_ID -#define MP0_PIC0_ID__INTR_ID__SHIFT 0x00000000 -#define MP0_PIC0_ID__RESERVED__SHIFT 0x00000008 - -// MP0_PIC1_MASK_0 -#define MP0_PIC1_MASK_0__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC1_MASK_0__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC1_MASK_0__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC1_MASK_0__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC1_MASK_0__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC1_MASK_0__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC1_MASK_0__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC1_MASK_0__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC1_MASK_0__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC1_MASK_0__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC1_MASK_0__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC1_MASK_0__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC1_MASK_0__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC1_MASK_0__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC1_MASK_0__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC1_MASK_0__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC1_MASK_0__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC1_MASK_0__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC1_MASK_0__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC1_MASK_0__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC1_MASK_0__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC1_MASK_0__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC1_MASK_0__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC1_MASK_0__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC1_MASK_0__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC1_MASK_0__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC1_MASK_0__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC1_MASK_0__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC1_MASK_0__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC1_MASK_0__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC1_MASK_0__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC1_MASK_0__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC1_MASK_1 -#define MP0_PIC1_MASK_1__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC1_MASK_1__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC1_MASK_1__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC1_MASK_1__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC1_MASK_1__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC1_MASK_1__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC1_MASK_1__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC1_MASK_1__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC1_MASK_1__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC1_MASK_1__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC1_MASK_1__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC1_MASK_1__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC1_MASK_1__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC1_MASK_1__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC1_MASK_1__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC1_MASK_1__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC1_MASK_1__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC1_MASK_1__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC1_MASK_1__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC1_MASK_1__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC1_MASK_1__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC1_MASK_1__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC1_MASK_1__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC1_MASK_1__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC1_MASK_1__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC1_MASK_1__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC1_MASK_1__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC1_MASK_1__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC1_MASK_1__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC1_MASK_1__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC1_MASK_1__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC1_MASK_1__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC1_MASK_2 -#define MP0_PIC1_MASK_2__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC1_MASK_2__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC1_MASK_2__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC1_MASK_2__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC1_MASK_2__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC1_MASK_2__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC1_MASK_2__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC1_MASK_2__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC1_MASK_2__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC1_MASK_2__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC1_MASK_2__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC1_MASK_2__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC1_MASK_2__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC1_MASK_2__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC1_MASK_2__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC1_MASK_2__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC1_MASK_2__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC1_MASK_2__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC1_MASK_2__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC1_MASK_2__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC1_MASK_2__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC1_MASK_2__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC1_MASK_2__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC1_MASK_2__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC1_MASK_2__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC1_MASK_2__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC1_MASK_2__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC1_MASK_2__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC1_MASK_2__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC1_MASK_2__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC1_MASK_2__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC1_MASK_2__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC1_MASK_3 -#define MP0_PIC1_MASK_3__INTR_MASK_0__SHIFT 0x00000000 -#define MP0_PIC1_MASK_3__INTR_MASK_1__SHIFT 0x00000001 -#define MP0_PIC1_MASK_3__INTR_MASK_2__SHIFT 0x00000002 -#define MP0_PIC1_MASK_3__INTR_MASK_3__SHIFT 0x00000003 -#define MP0_PIC1_MASK_3__INTR_MASK_4__SHIFT 0x00000004 -#define MP0_PIC1_MASK_3__INTR_MASK_5__SHIFT 0x00000005 -#define MP0_PIC1_MASK_3__INTR_MASK_6__SHIFT 0x00000006 -#define MP0_PIC1_MASK_3__INTR_MASK_7__SHIFT 0x00000007 -#define MP0_PIC1_MASK_3__INTR_MASK_8__SHIFT 0x00000008 -#define MP0_PIC1_MASK_3__INTR_MASK_9__SHIFT 0x00000009 -#define MP0_PIC1_MASK_3__INTR_MASK_10__SHIFT 0x0000000a -#define MP0_PIC1_MASK_3__INTR_MASK_11__SHIFT 0x0000000b -#define MP0_PIC1_MASK_3__INTR_MASK_12__SHIFT 0x0000000c -#define MP0_PIC1_MASK_3__INTR_MASK_13__SHIFT 0x0000000d -#define MP0_PIC1_MASK_3__INTR_MASK_14__SHIFT 0x0000000e -#define MP0_PIC1_MASK_3__INTR_MASK_15__SHIFT 0x0000000f -#define MP0_PIC1_MASK_3__INTR_MASK_16__SHIFT 0x00000010 -#define MP0_PIC1_MASK_3__INTR_MASK_17__SHIFT 0x00000011 -#define MP0_PIC1_MASK_3__INTR_MASK_18__SHIFT 0x00000012 -#define MP0_PIC1_MASK_3__INTR_MASK_19__SHIFT 0x00000013 -#define MP0_PIC1_MASK_3__INTR_MASK_20__SHIFT 0x00000014 -#define MP0_PIC1_MASK_3__INTR_MASK_21__SHIFT 0x00000015 -#define MP0_PIC1_MASK_3__INTR_MASK_22__SHIFT 0x00000016 -#define MP0_PIC1_MASK_3__INTR_MASK_23__SHIFT 0x00000017 -#define MP0_PIC1_MASK_3__INTR_MASK_24__SHIFT 0x00000018 -#define MP0_PIC1_MASK_3__INTR_MASK_25__SHIFT 0x00000019 -#define MP0_PIC1_MASK_3__INTR_MASK_26__SHIFT 0x0000001a -#define MP0_PIC1_MASK_3__INTR_MASK_27__SHIFT 0x0000001b -#define MP0_PIC1_MASK_3__INTR_MASK_28__SHIFT 0x0000001c -#define MP0_PIC1_MASK_3__INTR_MASK_29__SHIFT 0x0000001d -#define MP0_PIC1_MASK_3__INTR_MASK_30__SHIFT 0x0000001e -#define MP0_PIC1_MASK_3__INTR_MASK_31__SHIFT 0x0000001f - -// MP0_PIC1_STATUS_0 -#define MP0_PIC1_STATUS_0__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC1_STATUS_0__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC1_STATUS_0__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC1_STATUS_0__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC1_STATUS_0__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC1_STATUS_0__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC1_STATUS_0__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC1_STATUS_0__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC1_STATUS_0__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC1_STATUS_0__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC1_STATUS_0__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC1_STATUS_0__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC1_STATUS_0__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC1_STATUS_0__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC1_STATUS_0__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC1_STATUS_0__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC1_STATUS_0__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC1_STATUS_0__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC1_STATUS_0__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC1_STATUS_0__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC1_STATUS_0__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC1_STATUS_0__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC1_STATUS_0__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC1_STATUS_0__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC1_STATUS_0__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC1_STATUS_0__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC1_STATUS_0__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC1_STATUS_0__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC1_STATUS_0__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC1_STATUS_0__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC1_STATUS_0__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC1_STATUS_0__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC1_STATUS_1 -#define MP0_PIC1_STATUS_1__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC1_STATUS_1__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC1_STATUS_1__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC1_STATUS_1__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC1_STATUS_1__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC1_STATUS_1__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC1_STATUS_1__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC1_STATUS_1__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC1_STATUS_1__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC1_STATUS_1__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC1_STATUS_1__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC1_STATUS_1__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC1_STATUS_1__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC1_STATUS_1__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC1_STATUS_1__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC1_STATUS_1__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC1_STATUS_1__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC1_STATUS_1__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC1_STATUS_1__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC1_STATUS_1__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC1_STATUS_1__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC1_STATUS_1__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC1_STATUS_1__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC1_STATUS_1__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC1_STATUS_1__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC1_STATUS_1__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC1_STATUS_1__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC1_STATUS_1__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC1_STATUS_1__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC1_STATUS_1__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC1_STATUS_1__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC1_STATUS_1__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC1_STATUS_2 -#define MP0_PIC1_STATUS_2__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC1_STATUS_2__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC1_STATUS_2__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC1_STATUS_2__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC1_STATUS_2__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC1_STATUS_2__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC1_STATUS_2__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC1_STATUS_2__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC1_STATUS_2__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC1_STATUS_2__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC1_STATUS_2__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC1_STATUS_2__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC1_STATUS_2__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC1_STATUS_2__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC1_STATUS_2__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC1_STATUS_2__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC1_STATUS_2__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC1_STATUS_2__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC1_STATUS_2__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC1_STATUS_2__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC1_STATUS_2__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC1_STATUS_2__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC1_STATUS_2__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC1_STATUS_2__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC1_STATUS_2__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC1_STATUS_2__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC1_STATUS_2__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC1_STATUS_2__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC1_STATUS_2__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC1_STATUS_2__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC1_STATUS_2__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC1_STATUS_2__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC1_STATUS_3 -#define MP0_PIC1_STATUS_3__INTR_FLAG_0__SHIFT 0x00000000 -#define MP0_PIC1_STATUS_3__INTR_FLAG_1__SHIFT 0x00000001 -#define MP0_PIC1_STATUS_3__INTR_FLAG_2__SHIFT 0x00000002 -#define MP0_PIC1_STATUS_3__INTR_FLAG_3__SHIFT 0x00000003 -#define MP0_PIC1_STATUS_3__INTR_FLAG_4__SHIFT 0x00000004 -#define MP0_PIC1_STATUS_3__INTR_FLAG_5__SHIFT 0x00000005 -#define MP0_PIC1_STATUS_3__INTR_FLAG_6__SHIFT 0x00000006 -#define MP0_PIC1_STATUS_3__INTR_FLAG_7__SHIFT 0x00000007 -#define MP0_PIC1_STATUS_3__INTR_FLAG_8__SHIFT 0x00000008 -#define MP0_PIC1_STATUS_3__INTR_FLAG_9__SHIFT 0x00000009 -#define MP0_PIC1_STATUS_3__INTR_FLAG_10__SHIFT 0x0000000a -#define MP0_PIC1_STATUS_3__INTR_FLAG_11__SHIFT 0x0000000b -#define MP0_PIC1_STATUS_3__INTR_FLAG_12__SHIFT 0x0000000c -#define MP0_PIC1_STATUS_3__INTR_FLAG_13__SHIFT 0x0000000d -#define MP0_PIC1_STATUS_3__INTR_FLAG_14__SHIFT 0x0000000e -#define MP0_PIC1_STATUS_3__INTR_FLAG_15__SHIFT 0x0000000f -#define MP0_PIC1_STATUS_3__INTR_FLAG_16__SHIFT 0x00000010 -#define MP0_PIC1_STATUS_3__INTR_FLAG_17__SHIFT 0x00000011 -#define MP0_PIC1_STATUS_3__INTR_FLAG_18__SHIFT 0x00000012 -#define MP0_PIC1_STATUS_3__INTR_FLAG_19__SHIFT 0x00000013 -#define MP0_PIC1_STATUS_3__INTR_FLAG_20__SHIFT 0x00000014 -#define MP0_PIC1_STATUS_3__INTR_FLAG_21__SHIFT 0x00000015 -#define MP0_PIC1_STATUS_3__INTR_FLAG_22__SHIFT 0x00000016 -#define MP0_PIC1_STATUS_3__INTR_FLAG_23__SHIFT 0x00000017 -#define MP0_PIC1_STATUS_3__INTR_FLAG_24__SHIFT 0x00000018 -#define MP0_PIC1_STATUS_3__INTR_FLAG_25__SHIFT 0x00000019 -#define MP0_PIC1_STATUS_3__INTR_FLAG_26__SHIFT 0x0000001a -#define MP0_PIC1_STATUS_3__INTR_FLAG_27__SHIFT 0x0000001b -#define MP0_PIC1_STATUS_3__INTR_FLAG_28__SHIFT 0x0000001c -#define MP0_PIC1_STATUS_3__INTR_FLAG_29__SHIFT 0x0000001d -#define MP0_PIC1_STATUS_3__INTR_FLAG_30__SHIFT 0x0000001e -#define MP0_PIC1_STATUS_3__INTR_FLAG_31__SHIFT 0x0000001f - -// MP0_PIC1_INTR -#define MP0_PIC1_INTR__INTR_LINE__SHIFT 0x00000000 -#define MP0_PIC1_INTR__RESERVED__SHIFT 0x00000001 - -// MP0_PIC1_ID -#define MP0_PIC1_ID__INTR_ID__SHIFT 0x00000000 -#define MP0_PIC1_ID__RESERVED__SHIFT 0x00000008 - -// MP0_TIMER_0_CTRL0 -#define MP0_TIMER_0_CTRL0__START__SHIFT 0x00000000 -#define MP0_TIMER_0_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP0_TIMER_0_CTRL0__DEC__SHIFT 0x00000010 -#define MP0_TIMER_0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP0_TIMER_1_CTRL0 -#define MP0_TIMER_1_CTRL0__START__SHIFT 0x00000000 -#define MP0_TIMER_1_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP0_TIMER_1_CTRL0__DEC__SHIFT 0x00000010 -#define MP0_TIMER_1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP0_TIMER_2_CTRL0 -#define MP0_TIMER_2_CTRL0__START__SHIFT 0x00000000 -#define MP0_TIMER_2_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP0_TIMER_2_CTRL0__DEC__SHIFT 0x00000010 -#define MP0_TIMER_2_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP0_TIMER_3_CTRL0 -#define MP0_TIMER_3_CTRL0__START__SHIFT 0x00000000 -#define MP0_TIMER_3_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP0_TIMER_3_CTRL0__DEC__SHIFT 0x00000010 -#define MP0_TIMER_3_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP0_TIMER_0_CTRL1 -#define MP0_TIMER_0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP0_TIMER_0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP0_TIMER_0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP0_TIMER_0_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP0_TIMER_1_CTRL1 -#define MP0_TIMER_1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP0_TIMER_1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP0_TIMER_1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP0_TIMER_1_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP0_TIMER_2_CTRL1 -#define MP0_TIMER_2_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP0_TIMER_2_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP0_TIMER_2_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP0_TIMER_2_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP0_TIMER_3_CTRL1 -#define MP0_TIMER_3_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP0_TIMER_3_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP0_TIMER_3_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP0_TIMER_3_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP0_TIMER_0_CMP0_AUTOINC -#define MP0_TIMER_0_CMP0_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP0_TIMER_0_CMP0_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_1_CMP0_AUTOINC -#define MP0_TIMER_1_CMP0_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP0_TIMER_1_CMP0_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_2_CMP0_AUTOINC -#define MP0_TIMER_2_CMP0_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP0_TIMER_2_CMP0_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_3_CMP0_AUTOINC -#define MP0_TIMER_3_CMP0_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP0_TIMER_3_CMP0_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_0_INTEN -#define MP0_TIMER_0_INTEN__INTEN__SHIFT 0x00000000 -#define MP0_TIMER_0_INTEN__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_1_INTEN -#define MP0_TIMER_1_INTEN__INTEN__SHIFT 0x00000000 -#define MP0_TIMER_1_INTEN__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_2_INTEN -#define MP0_TIMER_2_INTEN__INTEN__SHIFT 0x00000000 -#define MP0_TIMER_2_INTEN__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_3_INTEN -#define MP0_TIMER_3_INTEN__INTEN__SHIFT 0x00000000 -#define MP0_TIMER_3_INTEN__RESERVED__SHIFT 0x00000004 - -// MP0_TIMER_OCMP0_0_0 -#define MP0_TIMER_OCMP0_0_0__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_1_0 -#define MP0_TIMER_OCMP0_1_0__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_2_0 -#define MP0_TIMER_OCMP0_2_0__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_3_0 -#define MP0_TIMER_OCMP0_3_0__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_0_1 -#define MP0_TIMER_OCMP0_0_1__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_1_1 -#define MP0_TIMER_OCMP0_1_1__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_2_1 -#define MP0_TIMER_OCMP0_2_1__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_3_1 -#define MP0_TIMER_OCMP0_3_1__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_0_2 -#define MP0_TIMER_OCMP0_0_2__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_1_2 -#define MP0_TIMER_OCMP0_1_2__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_2_2 -#define MP0_TIMER_OCMP0_2_2__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_3_2 -#define MP0_TIMER_OCMP0_3_2__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_0_3 -#define MP0_TIMER_OCMP0_0_3__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_1_3 -#define MP0_TIMER_OCMP0_1_3__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_2_3 -#define MP0_TIMER_OCMP0_2_3__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_OCMP0_3_3 -#define MP0_TIMER_OCMP0_3_3__OCMP0__SHIFT 0x00000000 - -// MP0_TIMER_0_CNT -#define MP0_TIMER_0_CNT__COUNT__SHIFT 0x00000000 - -// MP0_TIMER_1_CNT -#define MP0_TIMER_1_CNT__COUNT__SHIFT 0x00000000 - -// MP0_TIMER_2_CNT -#define MP0_TIMER_2_CNT__COUNT__SHIFT 0x00000000 - -// MP0_TIMER_3_CNT -#define MP0_TIMER_3_CNT__COUNT__SHIFT 0x00000000 - -// MP0_C2PMSG_0 -#define MP0_C2PMSG_0__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_1 -#define MP0_C2PMSG_1__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_2 -#define MP0_C2PMSG_2__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_3 -#define MP0_C2PMSG_3__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_4 -#define MP0_C2PMSG_4__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_5 -#define MP0_C2PMSG_5__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_6 -#define MP0_C2PMSG_6__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_7 -#define MP0_C2PMSG_7__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_8 -#define MP0_C2PMSG_8__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_9 -#define MP0_C2PMSG_9__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_10 -#define MP0_C2PMSG_10__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_11 -#define MP0_C2PMSG_11__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_12 -#define MP0_C2PMSG_12__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_13 -#define MP0_C2PMSG_13__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_14 -#define MP0_C2PMSG_14__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_15 -#define MP0_C2PMSG_15__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_16 -#define MP0_C2PMSG_16__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_17 -#define MP0_C2PMSG_17__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_18 -#define MP0_C2PMSG_18__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_19 -#define MP0_C2PMSG_19__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_20 -#define MP0_C2PMSG_20__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_21 -#define MP0_C2PMSG_21__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_22 -#define MP0_C2PMSG_22__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_23 -#define MP0_C2PMSG_23__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_24 -#define MP0_C2PMSG_24__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_25 -#define MP0_C2PMSG_25__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_26 -#define MP0_C2PMSG_26__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_27 -#define MP0_C2PMSG_27__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_28 -#define MP0_C2PMSG_28__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_29 -#define MP0_C2PMSG_29__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_30 -#define MP0_C2PMSG_30__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_31 -#define MP0_C2PMSG_31__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_32 -#define MP0_C2PMSG_32__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_33 -#define MP0_C2PMSG_33__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_34 -#define MP0_C2PMSG_34__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_35 -#define MP0_C2PMSG_35__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_36 -#define MP0_C2PMSG_36__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_37 -#define MP0_C2PMSG_37__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_38 -#define MP0_C2PMSG_38__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_39 -#define MP0_C2PMSG_39__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_40 -#define MP0_C2PMSG_40__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_41 -#define MP0_C2PMSG_41__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_42 -#define MP0_C2PMSG_42__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_43 -#define MP0_C2PMSG_43__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_44 -#define MP0_C2PMSG_44__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_45 -#define MP0_C2PMSG_45__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_46 -#define MP0_C2PMSG_46__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_47 -#define MP0_C2PMSG_47__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_48 -#define MP0_C2PMSG_48__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_49 -#define MP0_C2PMSG_49__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_50 -#define MP0_C2PMSG_50__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_51 -#define MP0_C2PMSG_51__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_52 -#define MP0_C2PMSG_52__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_53 -#define MP0_C2PMSG_53__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_54 -#define MP0_C2PMSG_54__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_55 -#define MP0_C2PMSG_55__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_56 -#define MP0_C2PMSG_56__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_57 -#define MP0_C2PMSG_57__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_58 -#define MP0_C2PMSG_58__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_59 -#define MP0_C2PMSG_59__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_60 -#define MP0_C2PMSG_60__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_61 -#define MP0_C2PMSG_61__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_62 -#define MP0_C2PMSG_62__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_63 -#define MP0_C2PMSG_63__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_64 -#define MP0_C2PMSG_64__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_65 -#define MP0_C2PMSG_65__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_66 -#define MP0_C2PMSG_66__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_67 -#define MP0_C2PMSG_67__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_68 -#define MP0_C2PMSG_68__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_69 -#define MP0_C2PMSG_69__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_70 -#define MP0_C2PMSG_70__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_71 -#define MP0_C2PMSG_71__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_72 -#define MP0_C2PMSG_72__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_73 -#define MP0_C2PMSG_73__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_74 -#define MP0_C2PMSG_74__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_75 -#define MP0_C2PMSG_75__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_76 -#define MP0_C2PMSG_76__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_77 -#define MP0_C2PMSG_77__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_78 -#define MP0_C2PMSG_78__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_79 -#define MP0_C2PMSG_79__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_80 -#define MP0_C2PMSG_80__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_81 -#define MP0_C2PMSG_81__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_82 -#define MP0_C2PMSG_82__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_83 -#define MP0_C2PMSG_83__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_84 -#define MP0_C2PMSG_84__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_85 -#define MP0_C2PMSG_85__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_86 -#define MP0_C2PMSG_86__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_87 -#define MP0_C2PMSG_87__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_88 -#define MP0_C2PMSG_88__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_89 -#define MP0_C2PMSG_89__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_90 -#define MP0_C2PMSG_90__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_91 -#define MP0_C2PMSG_91__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_92 -#define MP0_C2PMSG_92__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_93 -#define MP0_C2PMSG_93__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_94 -#define MP0_C2PMSG_94__CONTENT__SHIFT 0x00000000 - -// MP0_C2PMSG_95 -#define MP0_C2PMSG_95__CONTENT__SHIFT 0x00000000 - -// MP0_P2CMSG_0 -#define MP0_P2CMSG_0__CONTENT__SHIFT 0x00000000 - -// MP0_P2CMSG_1 -#define MP0_P2CMSG_1__CONTENT__SHIFT 0x00000000 - -// MP0_P2CMSG_2 -#define MP0_P2CMSG_2__CONTENT__SHIFT 0x00000000 - -// MP0_P2CMSG_3 -#define MP0_P2CMSG_3__CONTENT__SHIFT 0x00000000 - -// MP0_P2CMSG_INTEN -#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x00000000 - -// MP0_P2CMSG_INTSTS -#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x00000003 - -// MP0_C2PMSG_ATTR_0 -#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x00000000 - -// MP0_C2PMSG_ATTR_1 -#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x00000000 - -// MP0_C2PMSG_ATTR_2 -#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x00000000 - -// MP0_C2PMSG_ATTR_3 -#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x00000000 - -// MP0_C2PMSG_ATTR_4 -#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x00000000 - -// MP0_C2PMSG_ATTR_5 -#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x00000000 - -// MP0_P2CMSG_ATTR -#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x00000000 - -// MP0_P2SMSG_0 -#define MP0_P2SMSG_0__CONTENT__SHIFT 0x00000000 - -// MP0_P2SMSG_1 -#define MP0_P2SMSG_1__CONTENT__SHIFT 0x00000000 - -// MP0_P2SMSG_2 -#define MP0_P2SMSG_2__CONTENT__SHIFT 0x00000000 - -// MP0_P2SMSG_3 -#define MP0_P2SMSG_3__CONTENT__SHIFT 0x00000000 - -// MP0_P2SMSG_ATTR -#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x00000000 - -// MP0_S2PMSG_ATTR -#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x00000000 - -// MP0_P2SMSG_INTSTS -#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x00000003 - -// MP0_S2PMSG_0 -#define MP0_S2PMSG_0__CONTENT__SHIFT 0x00000000 - -// MP0_PUB_RSMU_HCID -#define MP0_PUB_RSMU_HCID__HwRev__SHIFT 0x00000000 -#define MP0_PUB_RSMU_HCID__HwMinVer__SHIFT 0x00000006 -#define MP0_PUB_RSMU_HCID__HwMajVer__SHIFT 0x0000000d -#define MP0_PUB_RSMU_HCID__HwID__SHIFT 0x00000014 - -// MP0_PUB_RSMU_SIID -#define MP0_PUB_RSMU_SIID__SwIfRev__SHIFT 0x00000000 -#define MP0_PUB_RSMU_SIID__SwIfMinVer__SHIFT 0x00000006 -#define MP0_PUB_RSMU_SIID__SwIfMajVer__SHIFT 0x0000000d -#define MP0_PUB_RSMU_SIID__SwIfID__SHIFT 0x00000014 - -// MP0_SAM_IH_EXT_ERR_INTR -#define MP0_SAM_IH_EXT_ERR_INTR__UVD__SHIFT 0x00000000 -#define MP0_SAM_IH_EXT_ERR_INTR__VCE__SHIFT 0x00000001 -#define MP0_SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x00000002 -#define MP0_SAM_IH_EXT_ERR_INTR__VP8__SHIFT 0x00000003 - -// MP0_SAM_IH_EXT_ERR_INTR_STATUS -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT 0x00000000 -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT 0x00000001 -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x00000002 -#define MP0_SAM_IH_EXT_ERR_INTR_STATUS__VP8__SHIFT 0x00000003 - -// MP0_REVID -#define MP0_REVID__REVID__SHIFT 0x00000000 - -// MP0_RSMU_HCID -#define MP0_RSMU_HCID__HwRev__SHIFT 0x00000000 -#define MP0_RSMU_HCID__HwMinVer__SHIFT 0x00000006 -#define MP0_RSMU_HCID__HwMajVer__SHIFT 0x0000000d -#define MP0_RSMU_HCID__HwID__SHIFT 0x00000014 - -// MP0_RSMU_SIID -#define MP0_RSMU_SIID__SwIfRev__SHIFT 0x00000000 -#define MP0_RSMU_SIID__SwIfMinVer__SHIFT 0x00000006 -#define MP0_RSMU_SIID__SwIfMajVer__SHIFT 0x0000000d -#define MP0_RSMU_SIID__SwIfID__SHIFT 0x00000014 - -// MP0_RAM_REPAIR_DONE -#define MP0_RAM_REPAIR_DONE__STATUS__SHIFT 0x00000000 - -// MP0_RAM_REPAIR_RESULT -#define MP0_RAM_REPAIR_RESULT__PASS__SHIFT 0x00000000 - -// MP0_FUSE_HARVESTING -#define MP0_FUSE_HARVESTING__DATA__SHIFT 0x00000000 - -// MP0_FUSE_RMBITS -#define MP0_FUSE_RMBITS__RM__SHIFT 0x00000000 -#define MP0_FUSE_RMBITS__RM_RESERVED__SHIFT 0x00000009 -#define MP0_FUSE_RMBITS__BC__SHIFT 0x00000010 -#define MP0_FUSE_RMBITS__BC_RESERVED__SHIFT 0x00000016 - -// MP0_SMS_CFG -#define MP0_SMS_CFG__SMS_RESETB__SHIFT 0x00000000 -#define MP0_SMS_CFG__RUN_BIHR__SHIFT 0x00000008 -#define MP0_SMS_CFG__RUN_MBIST__SHIFT 0x00000009 -#define MP0_SMS_CFG__SMS_FUSE_VALID__SHIFT 0x00000010 -#define MP0_SMS_CFG__SMS_NEXT_FETCH__SHIFT 0x00000018 -#define MP0_SMS_CFG__RAM_REPAIR_DONE__SHIFT 0x00000019 -#define MP0_SMS_CFG__RAM_BIST_FAIL__SHIFT 0x0000001a - -// MP0_FUSE_SMS_0 -#define MP0_FUSE_SMS_0__DATA__SHIFT 0x00000000 - -// MP0_FUSE_SMS_1 -#define MP0_FUSE_SMS_1__DATA__SHIFT 0x00000000 - -// MP0_FUSE_SMS_2 -#define MP0_FUSE_SMS_2__DATA__SHIFT 0x00000000 - -// MP0_FUSE_SMS_3 -#define MP0_FUSE_SMS_3__DATA__SHIFT 0x00000000 - -// MP0_FUSE_SMS_4 -#define MP0_FUSE_SMS_4__DATA__SHIFT 0x00000000 - -// MP0_FUSE_SMS_5 -#define MP0_FUSE_SMS_5__DATA__SHIFT 0x00000000 - -// MP0_FUSE_SMS_6 -#define MP0_FUSE_SMS_6__DATA__SHIFT 0x00000000 - -// MP0_FUSE_SMS_7 -#define MP0_FUSE_SMS_7__DATA__SHIFT 0x00000000 - -// MP0_ACC_VIO_INTSTS -#define MP0_ACC_VIO_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP0_ACC_VIO_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP0_ACC_VIO_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP0_ACC_VIO_INTSTS__INTSTS3__SHIFT 0x00000003 -#define MP0_ACC_VIO_INTSTS__INTSTS4__SHIFT 0x00000004 -#define MP0_ACC_VIO_INTSTS__INTSTS5__SHIFT 0x00000005 -#define MP0_ACC_VIO_INTSTS__INTSTS6__SHIFT 0x00000006 -#define MP0_ACC_VIO_INTSTS__INTSTS7__SHIFT 0x00000007 -#define MP0_ACC_VIO_INTSTS__INTSTS8__SHIFT 0x00000008 -#define MP0_ACC_VIO_INTSTS__INTSTS9__SHIFT 0x00000009 -#define MP0_ACC_VIO_INTSTS__INTSTS10__SHIFT 0x0000000a -#define MP0_ACC_VIO_INTSTS__INTSTS11__SHIFT 0x0000000b -#define MP0_ACC_VIO_INTSTS__INTSTS12__SHIFT 0x0000000c -#define MP0_ACC_VIO_INTSTS__INTSTS13__SHIFT 0x0000000d -#define MP0_ACC_VIO_INTSTS__INTSTS14__SHIFT 0x0000000e -#define MP0_ACC_VIO_INTSTS__INTSTS15__SHIFT 0x0000000f -#define MP0_ACC_VIO_INTSTS__INTSTS16__SHIFT 0x00000010 -#define MP0_ACC_VIO_INTSTS__INTSTS17__SHIFT 0x00000011 -#define MP0_ACC_VIO_INTSTS__INTSTS18__SHIFT 0x00000012 -#define MP0_ACC_VIO_INTSTS__INTSTS19__SHIFT 0x00000013 -#define MP0_ACC_VIO_INTSTS__INTSTS20__SHIFT 0x00000014 -#define MP0_ACC_VIO_INTSTS__INTSTS21__SHIFT 0x00000015 -#define MP0_ACC_VIO_INTSTS__INTSTS22__SHIFT 0x00000016 -#define MP0_ACC_VIO_INTSTS__INTSTS23__SHIFT 0x00000017 -#define MP0_ACC_VIO_INTSTS__INTSTS24__SHIFT 0x00000018 -#define MP0_ACC_VIO_INTSTS__INTSTS25__SHIFT 0x00000019 -#define MP0_ACC_VIO_INTSTS__INTSTS26__SHIFT 0x0000001a -#define MP0_ACC_VIO_INTSTS__INTSTS27__SHIFT 0x0000001b -#define MP0_ACC_VIO_INTSTS__INTSTS28__SHIFT 0x0000001c -#define MP0_ACC_VIO_INTSTS__INTSTS29__SHIFT 0x0000001d -#define MP0_ACC_VIO_INTSTS__INTSTS30__SHIFT 0x0000001e -#define MP0_ACC_VIO_INTSTS__INTSTS31__SHIFT 0x0000001f - -// MP0_TDR_MISC0_STATUS -#define MP0_TDR_MISC0_STATUS__DATA__SHIFT 0x00000000 - -// MP0_FW_OVERRIDE -#define MP0_FW_OVERRIDE__FORCE_SS_NOTR__SHIFT 0x00000000 -#define MP0_FW_OVERRIDE__RESERVED__SHIFT 0x00000001 - -// MP0_BOOTROM_REVID -#define MP0_BOOTROM_REVID__REVID__SHIFT 0x00000000 - -// MP0_CRU_CPU_CTRL_STS -#define MP0_CRU_CPU_CTRL_STS__EVENTI__SHIFT 0x00000000 -#define MP0_CRU_CPU_CTRL_STS__EVENTO__SHIFT 0x00000001 -#define MP0_CRU_CPU_CTRL_STS__TEINIT__SHIFT 0x00000002 -#define MP0_CRU_CPU_CTRL_STS__CP15SDISABLE__SHIFT 0x00000003 -#define MP0_CRU_CPU_CTRL_STS__L1RSTDISABLE__SHIFT 0x00000004 -#define MP0_CRU_CPU_CTRL_STS__PCLKENDBG__SHIFT 0x00000005 -#define MP0_CRU_CPU_CTRL_STS__CLUSTERID__SHIFT 0x00000006 - -// MP0_SFUSE_SEC -#define MP0_SFUSE_SEC__CPU_DBG_SEL__SHIFT 0x00000000 -#define MP0_SFUSE_SEC__DATA__SHIFT 0x00000001 - -// MP0_COLD_BOOT_EVENTS -#define MP0_COLD_BOOT_EVENTS__COLD_BOOT_SEQ_DONE__SHIFT 0x00000000 -#define MP0_COLD_BOOT_EVENTS__RESERVED__SHIFT 0x00000001 - -// MP0_WARM_BOOT_EVENTS -#define MP0_WARM_BOOT_EVENTS__WARM_BOOT_SEQ_DONE__SHIFT 0x00000000 -#define MP0_WARM_BOOT_EVENTS__RESERVED__SHIFT 0x00000001 - -// MP0_NSWORLD_P2CMSG_INTR_CTRL -#define MP0_NSWORLD_P2CMSG_INTR_CTRL__P2CMSG_INTEN_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_P2CMSG_CTRL -#define MP0_NSWORLD_P2CMSG_CTRL__P2CMSG_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_C2PMSG_CTRL -#define MP0_NSWORLD_C2PMSG_CTRL__C2PMSG_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_C2PMSG_CTRL_1 -#define MP0_NSWORLD_C2PMSG_CTRL_1__C2PMSG_NSENB_1__SHIFT 0x00000000 - -// MP0_NSWORLD_C2PMSG_CTRL_2 -#define MP0_NSWORLD_C2PMSG_CTRL_2__C2PMSG_NSENB_2__SHIFT 0x00000000 - -// MP0_NSWORLD_P2SMSG_CTRL -#define MP0_NSWORLD_P2SMSG_CTRL__P2SMSG_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_S2PMSG_CTRL -#define MP0_NSWORLD_S2PMSG_CTRL__S2PMSG_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC0_CTRL_0 -#define MP0_NSWORLD_PIC0_CTRL_0__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC0_CTRL_1 -#define MP0_NSWORLD_PIC0_CTRL_1__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC0_CTRL_2 -#define MP0_NSWORLD_PIC0_CTRL_2__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC0_CTRL_3 -#define MP0_NSWORLD_PIC0_CTRL_3__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC1_CTRL_0 -#define MP0_NSWORLD_PIC1_CTRL_0__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC1_CTRL_1 -#define MP0_NSWORLD_PIC1_CTRL_1__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC1_CTRL_2 -#define MP0_NSWORLD_PIC1_CTRL_2__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_PIC1_CTRL_3 -#define MP0_NSWORLD_PIC1_CTRL_3__PIC_NSENB__SHIFT 0x00000000 - -// MP0_NSWORLD_TIMER_CTRL -#define MP0_NSWORLD_TIMER_CTRL__TIMER_0_NSENB__SHIFT 0x00000000 -#define MP0_NSWORLD_TIMER_CTRL__TIMER_1_NSENB__SHIFT 0x00000001 -#define MP0_NSWORLD_TIMER_CTRL__TIMER_2_NSENB__SHIFT 0x00000002 -#define MP0_NSWORLD_TIMER_CTRL__TIMER_3_NSENB__SHIFT 0x00000003 - -// MP0_EVCNTCTL -#define MP0_EVCNTCTL__EVENTCNT_EN__SHIFT 0x00000000 -#define MP0_EVCNTCTL__EVENTCNT_RSTB__SHIFT 0x00000001 -#define MP0_EVCNTCTL__EVENTCNT_SHADOW__SHIFT 0x00000002 - -// MP0_EVCNTSEL -#define MP0_EVCNTSEL__EVENT0_BLK__SHIFT 0x00000000 -#define MP0_EVCNTSEL__EVENT0_SEL__SHIFT 0x00000008 -#define MP0_EVCNTSEL__EVENT1_BLK__SHIFT 0x00000010 -#define MP0_EVCNTSEL__EVENT1_SEL__SHIFT 0x00000018 - -// MP0_EVCNT0 -#define MP0_EVCNT0__EVENTCNT0__SHIFT 0x00000000 - -// MP0_EVCNT1 -#define MP0_EVCNT1__EVENTCNT1__SHIFT 0x00000000 - -// MP0_EVCNTHI -#define MP0_EVCNTHI__EVENTCNT0_HI__SHIFT 0x00000000 -#define MP0_EVCNTHI__EVENTCNT1_HI__SHIFT 0x00000010 - -// MP0_J2P_MBOX0 -#define MP0_J2P_MBOX0__MBX__SHIFT 0x00000000 - -// MP0_J2P_MBOX1 -#define MP0_J2P_MBOX1__MBX__SHIFT 0x00000000 - -// MP0_J2P_ATTR -#define MP0_J2P_ATTR__J2P_ATTR__SHIFT 0x00000000 - -// MP0_CRU_ACC_VIO_INTSTS -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS3__SHIFT 0x00000003 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS4__SHIFT 0x00000004 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS5__SHIFT 0x00000005 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS6__SHIFT 0x00000006 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS7__SHIFT 0x00000007 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS8__SHIFT 0x00000008 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS9__SHIFT 0x00000009 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS10__SHIFT 0x0000000a -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS11__SHIFT 0x0000000b -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS12__SHIFT 0x0000000c -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS13__SHIFT 0x0000000d -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS14__SHIFT 0x0000000e -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS15__SHIFT 0x0000000f -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS16__SHIFT 0x00000010 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS17__SHIFT 0x00000011 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS18__SHIFT 0x00000012 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS19__SHIFT 0x00000013 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS20__SHIFT 0x00000014 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS21__SHIFT 0x00000015 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS22__SHIFT 0x00000016 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS23__SHIFT 0x00000017 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS24__SHIFT 0x00000018 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS25__SHIFT 0x00000019 -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS26__SHIFT 0x0000001a -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS27__SHIFT 0x0000001b -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS28__SHIFT 0x0000001c -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS29__SHIFT 0x0000001d -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS30__SHIFT 0x0000001e -#define MP0_CRU_ACC_VIO_INTSTS__INTSTS31__SHIFT 0x0000001f - -// MP0_ACC_VIOL_LOG0 -#define MP0_ACC_VIOL_LOG0__AXI_ACC_VIO_LOG__SHIFT 0x00000000 -#define MP0_ACC_VIOL_LOG0__AXI_LOG_CLEAR__SHIFT 0x0000001f - -// MP0_ACC_VIOL_LOG1 -#define MP0_ACC_VIOL_LOG1__AXI_ACC_VIO_ADDR__SHIFT 0x00000000 - -// MP0_SEC_SCRATCH0 -#define MP0_SEC_SCRATCH0__DATA__SHIFT 0x00000000 - -// MP0_SEC_SCRATCH1 -#define MP0_SEC_SCRATCH1__DATA__SHIFT 0x00000000 - -// MP0_SEC_SCRATCH2 -#define MP0_SEC_SCRATCH2__DATA__SHIFT 0x00000000 - -// MP0_SEC_SCRATCH3 -#define MP0_SEC_SCRATCH3__DATA__SHIFT 0x00000000 - -// MP0_STICKY -#define MP0_STICKY__DATA__SHIFT 0x00000000 - -// MP0_CRU_MISC_CTRL -#define MP0_CRU_MISC_CTRL__ERROR_RESPONSE_ON_ACCVIOL__SHIFT 0x00000000 - -// MP0_SOFT_RESET_CTRL -#define MP0_SOFT_RESET_CTRL__MP_MMU_RESET__SHIFT 0x00000000 -#define MP0_SOFT_RESET_CTRL__MP_CPU_RESET__SHIFT 0x00000001 -#define MP0_SOFT_RESET_CTRL__MP_SMNIF_RESET__SHIFT 0x00000002 -#define MP0_SOFT_RESET_CTRL__MP_ROM_RESET__SHIFT 0x00000003 -#define MP0_SOFT_RESET_CTRL__MP_DAP_RESET__SHIFT 0x00000004 -#define MP0_SOFT_RESET_CTRL__MP_DRM_RESET__SHIFT 0x00000005 -#define MP0_SOFT_RESET_CTRL__MP_SHUBIF_RESET__SHIFT 0x00000008 -#define MP0_SOFT_RESET_CTRL__MP_MHUBIF_RESET__SHIFT 0x00000009 - -// MP0_NS_PROT_FAULT_STATUS_0 -#define MP0_NS_PROT_FAULT_STATUS_0__MMU_CFG_NS0_VIOL__SHIFT 0x00000000 -#define MP0_NS_PROT_FAULT_STATUS_0__MMU_SRAM_NS0_VIOL__SHIFT 0x00000001 -#define MP0_NS_PROT_FAULT_STATUS_0__ROM_NS0_VIOL__SHIFT 0x00000002 -#define MP0_NS_PROT_FAULT_STATUS_0__ROM_CFG_NS0_VIOL__SHIFT 0x00000003 -#define MP0_NS_PROT_FAULT_STATUS_0__CRU_NS0_VIOL__SHIFT 0x00000004 - -// MP0_FW_STATUS -#define MP0_FW_STATUS__FW_STATUS__SHIFT 0x00000000 - -// MP0_ROM_FW_CNTL -#define MP0_ROM_FW_CNTL__ROM_FW_FLOW_CNTL__SHIFT 0x00000000 - -// MP0_FW_MISC_CTRL -#define MP0_FW_MISC_CTRL__MP_FW_VALUE__SHIFT 0x00000000 - -// MP0_AEB_STATUS_0 -#define MP0_AEB_STATUS_0__MP0_AEB_DBG_BUS_en__SHIFT 0x00000000 -#define MP0_AEB_STATUS_0__MP0_AEB_CPU_DBG_TDRs_en__SHIFT 0x00000001 -#define MP0_AEB_STATUS_0__MP0_AEB_JTAG_AXI_master_en__SHIFT 0x00000002 -#define MP0_AEB_STATUS_0__MP0_AEB_ROM_content_visible_en__SHIFT 0x00000003 -#define MP0_AEB_STATUS_0__MP0_AEB_ROM_keys_visible_en__SHIFT 0x00000004 -#define MP0_AEB_STATUS_0__MP0_AEB_SCAN_DUMP_en__SHIFT 0x00000005 - -// MP0_AEB_STATUS_1 -#define MP0_AEB_STATUS_1__MP1_AEB_DBG_BUS_en__SHIFT 0x00000000 -#define MP0_AEB_STATUS_1__MP1_AEB_CPU_DBG_TDRs_en__SHIFT 0x00000001 -#define MP0_AEB_STATUS_1__MP1_AEB_JTAG_AXI_master_en__SHIFT 0x00000002 -#define MP0_AEB_STATUS_1__MP1_AEB_SCAN_DUMP_en__SHIFT 0x00000003 - -// MP0_AEB_JTAG_DBG_CTRL -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_DBG_BUS_en__SHIFT 0x00000000 -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_CPU_DBG_TDRs_en__SHIFT 0x00000001 -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_JTAG_AXI_master_en__SHIFT 0x00000002 -#define MP0_AEB_JTAG_DBG_CTRL__MP1_AEB_OVRD_SCAN_DUMP_en__SHIFT 0x00000003 - -// MP0_AEB_JTAG_DBG_CTRL_LOCK -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_DBG_BUS_en__SHIFT 0x00000000 -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_CPU_DBG_TDRs_en__SHIFT 0x00000001 -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_JTAG_AXI_master_en__SHIFT 0x00000002 -#define MP0_AEB_JTAG_DBG_CTRL_LOCK__MP1_AEB_LOCK_OVRD_SCAN_DUMP_en__SHIFT 0x00000003 - -// MP0_AEB_CNTL_0 -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_DBG_BUS_en__SHIFT 0x00000000 -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_CPU_DBG_TDRs_en__SHIFT 0x00000001 -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_JTAG_AXI_master_en__SHIFT 0x00000002 -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_ROM_content_visible_en__SHIFT 0x00000003 -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_ROM_keys_visible_en__SHIFT 0x00000004 -#define MP0_AEB_CNTL_0__MP0_AEB_DIS_SCAN_DUMP_en__SHIFT 0x00000005 - -// MP0_AEB_CNTL_1 -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_DBG_BUS_en__SHIFT 0x00000000 -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_CPU_DBG_TDRs_en__SHIFT 0x00000001 -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_JTAG_AXI_master_en__SHIFT 0x00000002 -#define MP0_AEB_CNTL_1__MP1_AEB_DIS_SCAN_DUMP_en__SHIFT 0x00000003 - -// MP0_PIC0_LEVEL_0 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_LEVEL_0__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_LEVEL_1 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_LEVEL_1__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_LEVEL_2 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_LEVEL_2__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_LEVEL_3 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_LEVEL_3__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_EDGE_0 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_EDGE_0__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_EDGE_1 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_EDGE_1__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_EDGE_2 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_EDGE_2__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_EDGE_3 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC0_EDGE_3__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC0_PRIORITY_0 -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_0__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_1 -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_1__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_2 -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_2__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_3 -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_3__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_4 -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_4__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_5 -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_5__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_6 -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_6__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_7 -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_7__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_8 -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_8__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_9 -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_9__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_10 -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_10__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_11 -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_11__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_12 -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_12__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_13 -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_13__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_14 -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_14__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_15 -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_15__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_16 -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_16__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_17 -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_17__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_18 -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_18__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_19 -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_19__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_20 -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_20__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_21 -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_21__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_22 -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_22__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_23 -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_23__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_24 -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_24__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_25 -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_25__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_26 -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_26__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_27 -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_27__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_28 -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_28__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_29 -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_29__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_30 -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_30__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC0_PRIORITY_31 -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC0_PRIORITY_31__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_LEVEL_0 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_LEVEL_0__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_LEVEL_1 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_LEVEL_1__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_LEVEL_2 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_LEVEL_2__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_LEVEL_3 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_LEVEL_3__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_EDGE_0 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_EDGE_0__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_EDGE_1 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_EDGE_1__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_EDGE_2 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_EDGE_2__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_EDGE_3 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP0_PIC1_EDGE_3__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP0_PIC1_PRIORITY_0 -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_0__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_1 -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_1__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_2 -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_2__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_3 -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_3__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_4 -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_4__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_5 -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_5__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_6 -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_6__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_7 -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_7__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_8 -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_8__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_9 -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_9__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_10 -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_10__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_11 -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_11__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_12 -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_12__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_13 -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_13__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_14 -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_14__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_15 -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_15__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_16 -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_16__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_17 -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_17__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_18 -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_18__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_19 -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_19__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_20 -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_20__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_21 -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_21__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_22 -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_22__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_23 -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_23__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_24 -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_24__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_25 -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_25__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_26 -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_26__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_27 -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_27__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_28 -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_28__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_29 -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_29__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_30 -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_30__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_PIC1_PRIORITY_31 -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP0_PIC1_PRIORITY_31__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP0_SAM_IH_EXT_ERR_INTR_ACK -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__UVD__SHIFT 0x00000000 -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__VCE__SHIFT 0x00000001 -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__ISP__SHIFT 0x00000002 -#define MP0_SAM_IH_EXT_ERR_INTR_ACK__VP8__SHIFT 0x00000003 - -// MP0_RSMU_SECINTR_FETCH0 -#define MP0_RSMU_SECINTR_FETCH0__UNIT_ID__SHIFT 0x00000000 -#define MP0_RSMU_SECINTR_FETCH0__INIT_ID__SHIFT 0x00000006 - -// MP0_RSMU_SECINTR_FETCH1 -#define MP0_RSMU_SECINTR_FETCH1__WDATA__SHIFT 0x00000000 - -// MP0_RSMU_SECINTR_STATUS -#define MP0_RSMU_SECINTR_STATUS__IFIFO_COUNT__SHIFT 0x00000000 -#define MP0_RSMU_SECINTR_STATUS__DFIFO_COUNT__SHIFT 0x00000008 -#define MP0_RSMU_SECINTR_STATUS__FIFO_NOTEMPTY__SHIFT 0x00000010 -#define MP0_RSMU_SECINTR_STATUS__FIFO_HALF__SHIFT 0x00000011 -#define MP0_RSMU_SECINTR_STATUS__FIFO_FULL__SHIFT 0x00000012 - -// MP0_RSMU_SECINTR_FLUSH0 -#define MP0_RSMU_SECINTR_FLUSH0__RESERVED__SHIFT 0x00000000 - -// MP0_RSMU_SECINTR_FLUSH1 -#define MP0_RSMU_SECINTR_FLUSH1__RESERVED__SHIFT 0x00000000 - -// MP0_RSMU_SECINTR_CTRL -#define MP0_RSMU_SECINTR_CTRL__FIFO_SELECT__SHIFT 0x00000000 -#define MP0_RSMU_SECINTR_CTRL__CLR_OFCNT__SHIFT 0x00000002 - -// MP0_RSMU_SECINTR_OFCNT -#define MP0_RSMU_SECINTR_OFCNT__OFCNT__SHIFT 0x00000000 - -// MP0_SMN_SAM_IH_EXT_ERR_INTR -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__UVD__SHIFT 0x00000000 -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__VCE__SHIFT 0x00000001 -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x00000002 -#define MP0_SMN_SAM_IH_EXT_ERR_INTR__VP8__SHIFT 0x00000003 - -// MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT 0x00000000 -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT 0x00000001 -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x00000002 -#define MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS__VP8__SHIFT 0x00000003 - -// MP0_SMN_C2PMSG_32 -#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_33 -#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_34 -#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_35 -#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_36 -#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_37 -#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_38 -#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_39 -#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_40 -#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_41 -#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_42 -#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_43 -#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_44 -#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_45 -#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_46 -#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_47 -#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_48 -#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_49 -#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_50 -#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_51 -#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_52 -#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_53 -#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_54 -#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_55 -#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_56 -#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_57 -#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_58 -#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_59 -#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_60 -#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_61 -#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_62 -#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_63 -#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_64 -#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_65 -#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_66 -#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_67 -#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_68 -#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_69 -#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_70 -#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_71 -#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_72 -#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_73 -#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_74 -#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_75 -#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_76 -#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_77 -#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_78 -#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_79 -#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_80 -#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_81 -#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_82 -#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_83 -#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_84 -#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_85 -#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_86 -#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_87 -#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_88 -#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_89 -#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_90 -#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_91 -#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_92 -#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_93 -#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_94 -#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x00000000 - -// MP0_SMN_C2PMSG_95 -#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x00000000 - -// MP0_RSMU_PUB_RSMU_HCID -#define MP0_RSMU_PUB_RSMU_HCID__HwRev__SHIFT 0x00000000 -#define MP0_RSMU_PUB_RSMU_HCID__HwMinVer__SHIFT 0x00000006 -#define MP0_RSMU_PUB_RSMU_HCID__HwMajVer__SHIFT 0x0000000d -#define MP0_RSMU_PUB_RSMU_HCID__HwID__SHIFT 0x00000014 - -// MP0_RSMU_PUB_RSMU_SIID -#define MP0_RSMU_PUB_RSMU_SIID__SwIfRev__SHIFT 0x00000000 -#define MP0_RSMU_PUB_RSMU_SIID__SwIfMinVer__SHIFT 0x00000006 -#define MP0_RSMU_PUB_RSMU_SIID__SwIfMajVer__SHIFT 0x0000000d -#define MP0_RSMU_PUB_RSMU_SIID__SwIfID__SHIFT 0x00000014 - -// MP0_MMU_SRAM_FLOP_START_ADDR -#define MP0_MMU_SRAM_FLOP_START_ADDR__VALUE__SHIFT 0x00000000 - -// MP0_MMU_SRAM_ACC_VIOLATION_LOG_ADDR -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_ADDR__ADDRESS__SHIFT 0x00000000 - -// MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_UNSECURE_BAR__SHIFT 0x00000001 -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_OP__SHIFT 0x00000003 -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE__SHIFT 0x00000004 -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_PERMISSION__SHIFT 0x00000006 -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_UNIT_ID__SHIFT 0x00000008 -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_INIT_ID__SHIFT 0x0000000e -#define MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x00000016 - -// MP0_MMU_MISC_CNTL -#define MP0_MMU_MISC_CNTL__ALLOW_UNPRIVILIGED_REG_ACC__SHIFT 0x00000000 -#define MP0_MMU_MISC_CNTL__RETURN_ERR_ON_VIOLATED_READ__SHIFT 0x00000001 -#define MP0_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_PSRAM__SHIFT 0x00000002 -#define MP0_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_CPU__SHIFT 0x00000003 -#define MP0_MMU_MISC_CNTL__ENABLE_RAM_FLOPS__SHIFT 0x00000004 -#define MP0_MMU_MISC_CNTL__RESERVED2__SHIFT 0x00000005 -#define MP0_MMU_MISC_CNTL__MEM_SLEEP_TIMEOUT__SHIFT 0x00000008 -#define MP0_MMU_MISC_CNTL__CLK_GATE_EN__SHIFT 0x00000010 -#define MP0_MMU_MISC_CNTL__CLK_GATE_OVERRIDE__SHIFT 0x00000011 -#define MP0_MMU_MISC_CNTL__CLK_GATE_TIMEOUT__SHIFT 0x00000012 -#define MP0_MMU_MISC_CNTL__REGCLK_STATUS__SHIFT 0x00000016 -#define MP0_MMU_MISC_CNTL__SYSCLK_STATUS__SHIFT 0x00000017 -#define MP0_MMU_MISC_CNTL__MEM_DEEP_SLEEP_EN__SHIFT 0x00000018 -#define MP0_MMU_MISC_CNTL__MEM_DEEP_SLEEP_STATUS__SHIFT 0x00000019 -#define MP0_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0000001a -#define MP0_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_STATUS__SHIFT 0x0000001b -#define MP0_MMU_MISC_CNTL__MEM_PG_DLY__SHIFT 0x0000001c - -// MP0_MMU_ACCESS_ERR_LOG -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_BLOCK__SHIFT 0x00000001 -#define MP0_MMU_ACCESS_ERR_LOG__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x00000003 -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_UNIT_ID__SHIFT 0x00000008 -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_INIT_ID__SHIFT 0x0000000e -#define MP0_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_PROT__SHIFT 0x00000016 - -// MP0_MMU_SRAM_UNSECURE_BAR -#define MP0_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR__SHIFT 0x00000000 -#define MP0_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR_LOCK__SHIFT 0x00000019 - -// MP0_MMU_SCRATCH_0 -#define MP0_MMU_SCRATCH_0__RESERVED__SHIFT 0x00000000 - -// MP0_MMU_SCRATCH_1 -#define MP0_MMU_SCRATCH_1__RESERVED__SHIFT 0x00000000 - -// MP0_MMU_SCRATCH_2 -#define MP0_MMU_SCRATCH_2__RESERVED__SHIFT 0x00000000 - -// MP0_MMU_SCRATCH_3 -#define MP0_MMU_SCRATCH_3__RESERVED__SHIFT 0x00000000 - -// MP0_MMU_SCRATCH_4 -#define MP0_MMU_SCRATCH_4__RESERVED__SHIFT 0x00000000 - -// MP0_MMU_SCRATCH_5 -#define MP0_MMU_SCRATCH_5__RESERVED__SHIFT 0x00000000 - -// MP0_MMU_SCRATCH_6 -#define MP0_MMU_SCRATCH_6__RESERVED__SHIFT 0x00000000 - -// MP0_MMU_SCRATCH_7 -#define MP0_MMU_SCRATCH_7__RESERVED__SHIFT 0x00000000 - -// MP0_MCA_ACCESS_CNTL -#define MP0_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_EN__SHIFT 0x00000000 -#define MP0_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_RD_WR_SEL__SHIFT 0x00000001 -#define MP0_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_REG_SEL__SHIFT 0x00000002 - -// MP0_MCA_ACCESS_WR_DATA -#define MP0_MCA_ACCESS_WR_DATA__MCA_ACCESS_WR_DATA__SHIFT 0x00000000 - -// MP0_MCA_ACCESS_RD_DATA -#define MP0_MCA_ACCESS_RD_DATA__MCA_ACCESS_RD_DATA__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_1 -#define MP0_MMHUB_SOC_TLB0_1__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_2 -#define MP0_MMHUB_SOC_TLB0_2__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_3 -#define MP0_MMHUB_SOC_TLB0_3__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_4 -#define MP0_MMHUB_SOC_TLB0_4__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_5 -#define MP0_MMHUB_SOC_TLB0_5__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_6 -#define MP0_MMHUB_SOC_TLB0_6__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_7 -#define MP0_MMHUB_SOC_TLB0_7__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_8 -#define MP0_MMHUB_SOC_TLB0_8__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_9 -#define MP0_MMHUB_SOC_TLB0_9__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_10 -#define MP0_MMHUB_SOC_TLB0_10__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_11 -#define MP0_MMHUB_SOC_TLB0_11__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_12 -#define MP0_MMHUB_SOC_TLB0_12__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_13 -#define MP0_MMHUB_SOC_TLB0_13__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_14 -#define MP0_MMHUB_SOC_TLB0_14__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_15 -#define MP0_MMHUB_SOC_TLB0_15__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_16 -#define MP0_MMHUB_SOC_TLB0_16__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_17 -#define MP0_MMHUB_SOC_TLB0_17__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_18 -#define MP0_MMHUB_SOC_TLB0_18__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_19 -#define MP0_MMHUB_SOC_TLB0_19__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_20 -#define MP0_MMHUB_SOC_TLB0_20__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_21 -#define MP0_MMHUB_SOC_TLB0_21__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_22 -#define MP0_MMHUB_SOC_TLB0_22__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_23 -#define MP0_MMHUB_SOC_TLB0_23__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_24 -#define MP0_MMHUB_SOC_TLB0_24__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_25 -#define MP0_MMHUB_SOC_TLB0_25__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_26 -#define MP0_MMHUB_SOC_TLB0_26__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_27 -#define MP0_MMHUB_SOC_TLB0_27__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_28 -#define MP0_MMHUB_SOC_TLB0_28__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_29 -#define MP0_MMHUB_SOC_TLB0_29__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_30 -#define MP0_MMHUB_SOC_TLB0_30__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_31 -#define MP0_MMHUB_SOC_TLB0_31__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_32 -#define MP0_MMHUB_SOC_TLB0_32__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_33 -#define MP0_MMHUB_SOC_TLB0_33__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_34 -#define MP0_MMHUB_SOC_TLB0_34__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_35 -#define MP0_MMHUB_SOC_TLB0_35__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_36 -#define MP0_MMHUB_SOC_TLB0_36__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_37 -#define MP0_MMHUB_SOC_TLB0_37__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_38 -#define MP0_MMHUB_SOC_TLB0_38__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_39 -#define MP0_MMHUB_SOC_TLB0_39__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_40 -#define MP0_MMHUB_SOC_TLB0_40__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_41 -#define MP0_MMHUB_SOC_TLB0_41__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_42 -#define MP0_MMHUB_SOC_TLB0_42__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_43 -#define MP0_MMHUB_SOC_TLB0_43__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_44 -#define MP0_MMHUB_SOC_TLB0_44__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_45 -#define MP0_MMHUB_SOC_TLB0_45__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_46 -#define MP0_MMHUB_SOC_TLB0_46__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_47 -#define MP0_MMHUB_SOC_TLB0_47__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_48 -#define MP0_MMHUB_SOC_TLB0_48__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_49 -#define MP0_MMHUB_SOC_TLB0_49__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_50 -#define MP0_MMHUB_SOC_TLB0_50__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_51 -#define MP0_MMHUB_SOC_TLB0_51__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_52 -#define MP0_MMHUB_SOC_TLB0_52__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_53 -#define MP0_MMHUB_SOC_TLB0_53__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_54 -#define MP0_MMHUB_SOC_TLB0_54__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_55 -#define MP0_MMHUB_SOC_TLB0_55__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_56 -#define MP0_MMHUB_SOC_TLB0_56__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_57 -#define MP0_MMHUB_SOC_TLB0_57__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_58 -#define MP0_MMHUB_SOC_TLB0_58__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_59 -#define MP0_MMHUB_SOC_TLB0_59__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_60 -#define MP0_MMHUB_SOC_TLB0_60__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_61 -#define MP0_MMHUB_SOC_TLB0_61__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB0_62 -#define MP0_MMHUB_SOC_TLB0_62__SOC_ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB1_1 -#define MP0_MMHUB_SOC_TLB1_1__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_1__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_1__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_2 -#define MP0_MMHUB_SOC_TLB1_2__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_2__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_2__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_3 -#define MP0_MMHUB_SOC_TLB1_3__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_3__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_3__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_4 -#define MP0_MMHUB_SOC_TLB1_4__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_4__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_4__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_5 -#define MP0_MMHUB_SOC_TLB1_5__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_5__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_5__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_6 -#define MP0_MMHUB_SOC_TLB1_6__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_6__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_6__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_7 -#define MP0_MMHUB_SOC_TLB1_7__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_7__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_7__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_8 -#define MP0_MMHUB_SOC_TLB1_8__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_8__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_8__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_9 -#define MP0_MMHUB_SOC_TLB1_9__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_9__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_9__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_10 -#define MP0_MMHUB_SOC_TLB1_10__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_10__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_10__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_11 -#define MP0_MMHUB_SOC_TLB1_11__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_11__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_11__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_12 -#define MP0_MMHUB_SOC_TLB1_12__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_12__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_12__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_13 -#define MP0_MMHUB_SOC_TLB1_13__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_13__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_13__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_14 -#define MP0_MMHUB_SOC_TLB1_14__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_14__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_14__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_15 -#define MP0_MMHUB_SOC_TLB1_15__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_15__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_15__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_16 -#define MP0_MMHUB_SOC_TLB1_16__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_16__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_16__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_17 -#define MP0_MMHUB_SOC_TLB1_17__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_17__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_17__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_18 -#define MP0_MMHUB_SOC_TLB1_18__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_18__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_18__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_19 -#define MP0_MMHUB_SOC_TLB1_19__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_19__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_19__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_20 -#define MP0_MMHUB_SOC_TLB1_20__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_20__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_20__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_21 -#define MP0_MMHUB_SOC_TLB1_21__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_21__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_21__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_22 -#define MP0_MMHUB_SOC_TLB1_22__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_22__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_22__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_23 -#define MP0_MMHUB_SOC_TLB1_23__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_23__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_23__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_24 -#define MP0_MMHUB_SOC_TLB1_24__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_24__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_24__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_25 -#define MP0_MMHUB_SOC_TLB1_25__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_25__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_25__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_26 -#define MP0_MMHUB_SOC_TLB1_26__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_26__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_26__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_27 -#define MP0_MMHUB_SOC_TLB1_27__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_27__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_27__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_28 -#define MP0_MMHUB_SOC_TLB1_28__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_28__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_28__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_29 -#define MP0_MMHUB_SOC_TLB1_29__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_29__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_29__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_30 -#define MP0_MMHUB_SOC_TLB1_30__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_30__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_30__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_31 -#define MP0_MMHUB_SOC_TLB1_31__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_31__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_31__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_32 -#define MP0_MMHUB_SOC_TLB1_32__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_32__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_32__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_33 -#define MP0_MMHUB_SOC_TLB1_33__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_33__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_33__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_34 -#define MP0_MMHUB_SOC_TLB1_34__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_34__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_34__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_35 -#define MP0_MMHUB_SOC_TLB1_35__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_35__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_35__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_36 -#define MP0_MMHUB_SOC_TLB1_36__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_36__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_36__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_37 -#define MP0_MMHUB_SOC_TLB1_37__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_37__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_37__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_38 -#define MP0_MMHUB_SOC_TLB1_38__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_38__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_38__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_39 -#define MP0_MMHUB_SOC_TLB1_39__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_39__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_39__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_40 -#define MP0_MMHUB_SOC_TLB1_40__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_40__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_40__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_41 -#define MP0_MMHUB_SOC_TLB1_41__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_41__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_41__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_42 -#define MP0_MMHUB_SOC_TLB1_42__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_42__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_42__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_43 -#define MP0_MMHUB_SOC_TLB1_43__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_43__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_43__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_44 -#define MP0_MMHUB_SOC_TLB1_44__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_44__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_44__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_45 -#define MP0_MMHUB_SOC_TLB1_45__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_45__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_45__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_46 -#define MP0_MMHUB_SOC_TLB1_46__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_46__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_46__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_47 -#define MP0_MMHUB_SOC_TLB1_47__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_47__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_47__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_48 -#define MP0_MMHUB_SOC_TLB1_48__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_48__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_48__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_49 -#define MP0_MMHUB_SOC_TLB1_49__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_49__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_49__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_50 -#define MP0_MMHUB_SOC_TLB1_50__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_50__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_50__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_51 -#define MP0_MMHUB_SOC_TLB1_51__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_51__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_51__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_52 -#define MP0_MMHUB_SOC_TLB1_52__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_52__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_52__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_53 -#define MP0_MMHUB_SOC_TLB1_53__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_53__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_53__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_54 -#define MP0_MMHUB_SOC_TLB1_54__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_54__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_54__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_55 -#define MP0_MMHUB_SOC_TLB1_55__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_55__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_55__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_56 -#define MP0_MMHUB_SOC_TLB1_56__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_56__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_56__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_57 -#define MP0_MMHUB_SOC_TLB1_57__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_57__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_57__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_58 -#define MP0_MMHUB_SOC_TLB1_58__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_58__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_58__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_59 -#define MP0_MMHUB_SOC_TLB1_59__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_59__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_59__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_60 -#define MP0_MMHUB_SOC_TLB1_60__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_60__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_60__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_61 -#define MP0_MMHUB_SOC_TLB1_61__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_61__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_61__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB1_62 -#define MP0_MMHUB_SOC_TLB1_62__COHERENCE__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB1_62__SEG_SIZE__SHIFT 0x00000001 -#define MP0_MMHUB_SOC_TLB1_62__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_MMHUB_SOC_TLB2_1 -#define MP0_MMHUB_SOC_TLB2_1__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_2 -#define MP0_MMHUB_SOC_TLB2_2__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_3 -#define MP0_MMHUB_SOC_TLB2_3__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_4 -#define MP0_MMHUB_SOC_TLB2_4__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_5 -#define MP0_MMHUB_SOC_TLB2_5__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_6 -#define MP0_MMHUB_SOC_TLB2_6__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_7 -#define MP0_MMHUB_SOC_TLB2_7__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_8 -#define MP0_MMHUB_SOC_TLB2_8__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_9 -#define MP0_MMHUB_SOC_TLB2_9__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_10 -#define MP0_MMHUB_SOC_TLB2_10__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_11 -#define MP0_MMHUB_SOC_TLB2_11__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_12 -#define MP0_MMHUB_SOC_TLB2_12__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_13 -#define MP0_MMHUB_SOC_TLB2_13__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_14 -#define MP0_MMHUB_SOC_TLB2_14__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_15 -#define MP0_MMHUB_SOC_TLB2_15__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_16 -#define MP0_MMHUB_SOC_TLB2_16__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_17 -#define MP0_MMHUB_SOC_TLB2_17__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_18 -#define MP0_MMHUB_SOC_TLB2_18__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_19 -#define MP0_MMHUB_SOC_TLB2_19__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_20 -#define MP0_MMHUB_SOC_TLB2_20__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_21 -#define MP0_MMHUB_SOC_TLB2_21__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_22 -#define MP0_MMHUB_SOC_TLB2_22__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_23 -#define MP0_MMHUB_SOC_TLB2_23__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_24 -#define MP0_MMHUB_SOC_TLB2_24__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_25 -#define MP0_MMHUB_SOC_TLB2_25__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_26 -#define MP0_MMHUB_SOC_TLB2_26__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_27 -#define MP0_MMHUB_SOC_TLB2_27__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_28 -#define MP0_MMHUB_SOC_TLB2_28__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_29 -#define MP0_MMHUB_SOC_TLB2_29__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_30 -#define MP0_MMHUB_SOC_TLB2_30__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_31 -#define MP0_MMHUB_SOC_TLB2_31__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_32 -#define MP0_MMHUB_SOC_TLB2_32__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_33 -#define MP0_MMHUB_SOC_TLB2_33__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_34 -#define MP0_MMHUB_SOC_TLB2_34__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_35 -#define MP0_MMHUB_SOC_TLB2_35__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_36 -#define MP0_MMHUB_SOC_TLB2_36__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_37 -#define MP0_MMHUB_SOC_TLB2_37__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_38 -#define MP0_MMHUB_SOC_TLB2_38__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_39 -#define MP0_MMHUB_SOC_TLB2_39__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_40 -#define MP0_MMHUB_SOC_TLB2_40__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_41 -#define MP0_MMHUB_SOC_TLB2_41__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_42 -#define MP0_MMHUB_SOC_TLB2_42__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_43 -#define MP0_MMHUB_SOC_TLB2_43__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_44 -#define MP0_MMHUB_SOC_TLB2_44__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_45 -#define MP0_MMHUB_SOC_TLB2_45__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_46 -#define MP0_MMHUB_SOC_TLB2_46__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_47 -#define MP0_MMHUB_SOC_TLB2_47__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_48 -#define MP0_MMHUB_SOC_TLB2_48__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_49 -#define MP0_MMHUB_SOC_TLB2_49__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_50 -#define MP0_MMHUB_SOC_TLB2_50__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_51 -#define MP0_MMHUB_SOC_TLB2_51__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_52 -#define MP0_MMHUB_SOC_TLB2_52__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_53 -#define MP0_MMHUB_SOC_TLB2_53__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_54 -#define MP0_MMHUB_SOC_TLB2_54__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_55 -#define MP0_MMHUB_SOC_TLB2_55__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_56 -#define MP0_MMHUB_SOC_TLB2_56__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_57 -#define MP0_MMHUB_SOC_TLB2_57__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_58 -#define MP0_MMHUB_SOC_TLB2_58__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_59 -#define MP0_MMHUB_SOC_TLB2_59__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_60 -#define MP0_MMHUB_SOC_TLB2_60__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_61 -#define MP0_MMHUB_SOC_TLB2_61__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB2_62 -#define MP0_MMHUB_SOC_TLB2_62__AWUSER__SHIFT 0x00000000 - -// MP0_MMHUB_SOC_TLB3_1 -#define MP0_MMHUB_SOC_TLB3_1__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_1__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_2 -#define MP0_MMHUB_SOC_TLB3_2__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_2__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_3 -#define MP0_MMHUB_SOC_TLB3_3__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_3__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_4 -#define MP0_MMHUB_SOC_TLB3_4__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_4__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_5 -#define MP0_MMHUB_SOC_TLB3_5__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_5__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_6 -#define MP0_MMHUB_SOC_TLB3_6__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_6__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_7 -#define MP0_MMHUB_SOC_TLB3_7__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_7__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_8 -#define MP0_MMHUB_SOC_TLB3_8__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_8__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_9 -#define MP0_MMHUB_SOC_TLB3_9__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_9__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_10 -#define MP0_MMHUB_SOC_TLB3_10__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_10__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_11 -#define MP0_MMHUB_SOC_TLB3_11__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_11__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_12 -#define MP0_MMHUB_SOC_TLB3_12__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_12__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_13 -#define MP0_MMHUB_SOC_TLB3_13__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_13__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_14 -#define MP0_MMHUB_SOC_TLB3_14__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_14__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_15 -#define MP0_MMHUB_SOC_TLB3_15__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_15__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_16 -#define MP0_MMHUB_SOC_TLB3_16__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_16__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_17 -#define MP0_MMHUB_SOC_TLB3_17__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_17__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_18 -#define MP0_MMHUB_SOC_TLB3_18__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_18__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_19 -#define MP0_MMHUB_SOC_TLB3_19__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_19__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_20 -#define MP0_MMHUB_SOC_TLB3_20__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_20__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_21 -#define MP0_MMHUB_SOC_TLB3_21__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_21__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_22 -#define MP0_MMHUB_SOC_TLB3_22__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_22__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_23 -#define MP0_MMHUB_SOC_TLB3_23__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_23__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_24 -#define MP0_MMHUB_SOC_TLB3_24__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_24__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_25 -#define MP0_MMHUB_SOC_TLB3_25__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_25__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_26 -#define MP0_MMHUB_SOC_TLB3_26__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_26__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_27 -#define MP0_MMHUB_SOC_TLB3_27__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_27__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_28 -#define MP0_MMHUB_SOC_TLB3_28__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_28__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_29 -#define MP0_MMHUB_SOC_TLB3_29__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_29__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_30 -#define MP0_MMHUB_SOC_TLB3_30__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_30__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_31 -#define MP0_MMHUB_SOC_TLB3_31__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_31__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_32 -#define MP0_MMHUB_SOC_TLB3_32__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_32__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_33 -#define MP0_MMHUB_SOC_TLB3_33__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_33__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_34 -#define MP0_MMHUB_SOC_TLB3_34__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_34__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_35 -#define MP0_MMHUB_SOC_TLB3_35__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_35__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_36 -#define MP0_MMHUB_SOC_TLB3_36__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_36__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_37 -#define MP0_MMHUB_SOC_TLB3_37__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_37__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_38 -#define MP0_MMHUB_SOC_TLB3_38__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_38__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_39 -#define MP0_MMHUB_SOC_TLB3_39__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_39__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_40 -#define MP0_MMHUB_SOC_TLB3_40__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_40__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_41 -#define MP0_MMHUB_SOC_TLB3_41__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_41__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_42 -#define MP0_MMHUB_SOC_TLB3_42__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_42__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_43 -#define MP0_MMHUB_SOC_TLB3_43__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_43__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_44 -#define MP0_MMHUB_SOC_TLB3_44__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_44__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_45 -#define MP0_MMHUB_SOC_TLB3_45__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_45__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_46 -#define MP0_MMHUB_SOC_TLB3_46__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_46__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_47 -#define MP0_MMHUB_SOC_TLB3_47__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_47__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_48 -#define MP0_MMHUB_SOC_TLB3_48__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_48__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_49 -#define MP0_MMHUB_SOC_TLB3_49__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_49__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_50 -#define MP0_MMHUB_SOC_TLB3_50__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_50__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_51 -#define MP0_MMHUB_SOC_TLB3_51__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_51__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_52 -#define MP0_MMHUB_SOC_TLB3_52__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_52__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_53 -#define MP0_MMHUB_SOC_TLB3_53__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_53__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_54 -#define MP0_MMHUB_SOC_TLB3_54__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_54__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_55 -#define MP0_MMHUB_SOC_TLB3_55__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_55__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_56 -#define MP0_MMHUB_SOC_TLB3_56__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_56__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_57 -#define MP0_MMHUB_SOC_TLB3_57__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_57__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_58 -#define MP0_MMHUB_SOC_TLB3_58__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_58__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_59 -#define MP0_MMHUB_SOC_TLB3_59__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_59__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_60 -#define MP0_MMHUB_SOC_TLB3_60__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_60__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_61 -#define MP0_MMHUB_SOC_TLB3_61__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_61__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_SOC_TLB3_62 -#define MP0_MMHUB_SOC_TLB3_62__ARUSER__SHIFT 0x00000000 -#define MP0_MMHUB_SOC_TLB3_62__WUSER__SHIFT 0x0000001a - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_MMHUB_TLB_ATTRIBUTE_1 -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_2 -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_3 -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_4 -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_5 -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_6 -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_7 -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_8 -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_9 -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_10 -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_11 -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_12 -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_13 -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_14 -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_15 -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_16 -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_17 -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_18 -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_19 -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_20 -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_21 -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_22 -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_23 -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_24 -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_25 -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_26 -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_27 -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_28 -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_29 -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_30 -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_31 -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_32 -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_33 -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_34 -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_35 -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_36 -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_37 -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_38 -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_39 -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_40 -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_41 -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_42 -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_43 -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_44 -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_45 -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_46 -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_47 -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_48 -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_49 -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_50 -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_51 -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_52 -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_53 -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_54 -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_55 -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_56 -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_57 -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_58 -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_59 -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_60 -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_61 -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_TLB_ATTRIBUTE_62 -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_MMHUB_INT_STATUS -#define MP0_MMHUB_INT_STATUS__RD_ERROR__SHIFT 0x00000000 -#define MP0_MMHUB_INT_STATUS__WR_ERROR__SHIFT 0x00000001 -#define MP0_MMHUB_INT_STATUS__REG_ERROR__SHIFT 0x00000002 - -// MP0_MMHUB_WR_INT_ADDR -#define MP0_MMHUB_WR_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_WR_INT_OTHER -#define MP0_MMHUB_WR_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP0_MMHUB_WR_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP0_MMHUB_WR_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP0_MMHUB_WR_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP0_MMHUB_WR_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP0_MMHUB_WR_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP0_MMHUB_WR_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP0_MMHUB_WR_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP0_MMHUB_RD_INT_ADDR -#define MP0_MMHUB_RD_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_RD_INT_OTHER -#define MP0_MMHUB_RD_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP0_MMHUB_RD_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP0_MMHUB_RD_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP0_MMHUB_RD_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP0_MMHUB_RD_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP0_MMHUB_RD_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP0_MMHUB_RD_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP0_MMHUB_RD_INT_OTHER__ERROR_LENGTH__SHIFT 0x0000001a -#define MP0_MMHUB_RD_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP0_MMHUB_REG_INT_ADDR -#define MP0_MMHUB_REG_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP0_MMHUB_REG_INT_OTHER -#define MP0_MMHUB_REG_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP0_MMHUB_REG_INT_OTHER__ERROR_AES__SHIFT 0x00000014 -#define MP0_MMHUB_REG_INT_OTHER__ERROR_MST__SHIFT 0x00000015 -#define MP0_MMHUB_REG_INT_OTHER__ERROR_ADDR__SHIFT 0x00000016 -#define MP0_MMHUB_REG_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP0_MMHUB_REG_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP0_MMHUB_AXCACHE_CFG -#define MP0_MMHUB_AXCACHE_CFG__ARCACHE_NONCOH__SHIFT 0x00000000 -#define MP0_MMHUB_AXCACHE_CFG__ARCACHE_COH__SHIFT 0x00000004 -#define MP0_MMHUB_AXCACHE_CFG__AWCACHE_NONCOH__SHIFT 0x00000008 -#define MP0_MMHUB_AXCACHE_CFG__AWCACHE_COH__SHIFT 0x0000000c -#define MP0_MMHUB_AXCACHE_CFG__QOSW__SHIFT 0x00000010 -#define MP0_MMHUB_AXCACHE_CFG__QOSR__SHIFT 0x00000014 - -// MP0_MMHUB_DS_OVERRIDE -#define MP0_MMHUB_DS_OVERRIDE__DS_CNT__SHIFT 0x00000000 -#define MP0_MMHUB_DS_OVERRIDE__DS_DISABLE__SHIFT 0x0000000b - -// MP0_MMHUB_OUTSTANDING -#define MP0_MMHUB_OUTSTANDING__PENDING_WR__SHIFT 0x00000000 -#define MP0_MMHUB_OUTSTANDING__PENDING_RD__SHIFT 0x00000010 - -// MP0_SYSHUB_SOC_TLB0_1 -#define MP0_SYSHUB_SOC_TLB0_1__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_2 -#define MP0_SYSHUB_SOC_TLB0_2__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_3 -#define MP0_SYSHUB_SOC_TLB0_3__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_4 -#define MP0_SYSHUB_SOC_TLB0_4__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_5 -#define MP0_SYSHUB_SOC_TLB0_5__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_6 -#define MP0_SYSHUB_SOC_TLB0_6__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_7 -#define MP0_SYSHUB_SOC_TLB0_7__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_8 -#define MP0_SYSHUB_SOC_TLB0_8__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_9 -#define MP0_SYSHUB_SOC_TLB0_9__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_10 -#define MP0_SYSHUB_SOC_TLB0_10__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_11 -#define MP0_SYSHUB_SOC_TLB0_11__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_12 -#define MP0_SYSHUB_SOC_TLB0_12__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_13 -#define MP0_SYSHUB_SOC_TLB0_13__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_14 -#define MP0_SYSHUB_SOC_TLB0_14__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_15 -#define MP0_SYSHUB_SOC_TLB0_15__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_16 -#define MP0_SYSHUB_SOC_TLB0_16__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_17 -#define MP0_SYSHUB_SOC_TLB0_17__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_18 -#define MP0_SYSHUB_SOC_TLB0_18__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_19 -#define MP0_SYSHUB_SOC_TLB0_19__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_20 -#define MP0_SYSHUB_SOC_TLB0_20__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_21 -#define MP0_SYSHUB_SOC_TLB0_21__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_22 -#define MP0_SYSHUB_SOC_TLB0_22__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_23 -#define MP0_SYSHUB_SOC_TLB0_23__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_24 -#define MP0_SYSHUB_SOC_TLB0_24__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_25 -#define MP0_SYSHUB_SOC_TLB0_25__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_26 -#define MP0_SYSHUB_SOC_TLB0_26__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_27 -#define MP0_SYSHUB_SOC_TLB0_27__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_28 -#define MP0_SYSHUB_SOC_TLB0_28__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_29 -#define MP0_SYSHUB_SOC_TLB0_29__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_30 -#define MP0_SYSHUB_SOC_TLB0_30__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_31 -#define MP0_SYSHUB_SOC_TLB0_31__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_32 -#define MP0_SYSHUB_SOC_TLB0_32__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_33 -#define MP0_SYSHUB_SOC_TLB0_33__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_34 -#define MP0_SYSHUB_SOC_TLB0_34__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_35 -#define MP0_SYSHUB_SOC_TLB0_35__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_36 -#define MP0_SYSHUB_SOC_TLB0_36__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_37 -#define MP0_SYSHUB_SOC_TLB0_37__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_38 -#define MP0_SYSHUB_SOC_TLB0_38__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_39 -#define MP0_SYSHUB_SOC_TLB0_39__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_40 -#define MP0_SYSHUB_SOC_TLB0_40__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_41 -#define MP0_SYSHUB_SOC_TLB0_41__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_42 -#define MP0_SYSHUB_SOC_TLB0_42__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_43 -#define MP0_SYSHUB_SOC_TLB0_43__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_44 -#define MP0_SYSHUB_SOC_TLB0_44__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_45 -#define MP0_SYSHUB_SOC_TLB0_45__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_46 -#define MP0_SYSHUB_SOC_TLB0_46__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_47 -#define MP0_SYSHUB_SOC_TLB0_47__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_48 -#define MP0_SYSHUB_SOC_TLB0_48__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_49 -#define MP0_SYSHUB_SOC_TLB0_49__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_50 -#define MP0_SYSHUB_SOC_TLB0_50__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_51 -#define MP0_SYSHUB_SOC_TLB0_51__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_52 -#define MP0_SYSHUB_SOC_TLB0_52__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_53 -#define MP0_SYSHUB_SOC_TLB0_53__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_54 -#define MP0_SYSHUB_SOC_TLB0_54__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_55 -#define MP0_SYSHUB_SOC_TLB0_55__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_56 -#define MP0_SYSHUB_SOC_TLB0_56__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_57 -#define MP0_SYSHUB_SOC_TLB0_57__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_58 -#define MP0_SYSHUB_SOC_TLB0_58__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_59 -#define MP0_SYSHUB_SOC_TLB0_59__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_60 -#define MP0_SYSHUB_SOC_TLB0_60__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_61 -#define MP0_SYSHUB_SOC_TLB0_61__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB0_62 -#define MP0_SYSHUB_SOC_TLB0_62__SOC_ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB1_1 -#define MP0_SYSHUB_SOC_TLB1_1__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_1__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_1__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_2 -#define MP0_SYSHUB_SOC_TLB1_2__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_2__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_2__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_3 -#define MP0_SYSHUB_SOC_TLB1_3__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_3__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_3__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_4 -#define MP0_SYSHUB_SOC_TLB1_4__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_4__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_4__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_5 -#define MP0_SYSHUB_SOC_TLB1_5__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_5__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_5__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_6 -#define MP0_SYSHUB_SOC_TLB1_6__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_6__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_6__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_7 -#define MP0_SYSHUB_SOC_TLB1_7__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_7__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_7__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_8 -#define MP0_SYSHUB_SOC_TLB1_8__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_8__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_8__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_9 -#define MP0_SYSHUB_SOC_TLB1_9__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_9__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_9__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_10 -#define MP0_SYSHUB_SOC_TLB1_10__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_10__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_10__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_11 -#define MP0_SYSHUB_SOC_TLB1_11__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_11__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_11__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_12 -#define MP0_SYSHUB_SOC_TLB1_12__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_12__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_12__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_13 -#define MP0_SYSHUB_SOC_TLB1_13__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_13__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_13__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_14 -#define MP0_SYSHUB_SOC_TLB1_14__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_14__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_14__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_15 -#define MP0_SYSHUB_SOC_TLB1_15__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_15__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_15__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_16 -#define MP0_SYSHUB_SOC_TLB1_16__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_16__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_16__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_17 -#define MP0_SYSHUB_SOC_TLB1_17__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_17__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_17__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_18 -#define MP0_SYSHUB_SOC_TLB1_18__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_18__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_18__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_19 -#define MP0_SYSHUB_SOC_TLB1_19__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_19__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_19__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_20 -#define MP0_SYSHUB_SOC_TLB1_20__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_20__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_20__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_21 -#define MP0_SYSHUB_SOC_TLB1_21__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_21__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_21__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_22 -#define MP0_SYSHUB_SOC_TLB1_22__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_22__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_22__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_23 -#define MP0_SYSHUB_SOC_TLB1_23__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_23__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_23__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_24 -#define MP0_SYSHUB_SOC_TLB1_24__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_24__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_24__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_25 -#define MP0_SYSHUB_SOC_TLB1_25__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_25__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_25__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_26 -#define MP0_SYSHUB_SOC_TLB1_26__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_26__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_26__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_27 -#define MP0_SYSHUB_SOC_TLB1_27__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_27__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_27__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_28 -#define MP0_SYSHUB_SOC_TLB1_28__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_28__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_28__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_29 -#define MP0_SYSHUB_SOC_TLB1_29__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_29__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_29__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_30 -#define MP0_SYSHUB_SOC_TLB1_30__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_30__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_30__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_31 -#define MP0_SYSHUB_SOC_TLB1_31__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_31__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_31__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_32 -#define MP0_SYSHUB_SOC_TLB1_32__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_32__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_32__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_33 -#define MP0_SYSHUB_SOC_TLB1_33__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_33__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_33__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_34 -#define MP0_SYSHUB_SOC_TLB1_34__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_34__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_34__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_35 -#define MP0_SYSHUB_SOC_TLB1_35__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_35__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_35__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_36 -#define MP0_SYSHUB_SOC_TLB1_36__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_36__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_36__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_37 -#define MP0_SYSHUB_SOC_TLB1_37__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_37__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_37__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_38 -#define MP0_SYSHUB_SOC_TLB1_38__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_38__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_38__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_39 -#define MP0_SYSHUB_SOC_TLB1_39__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_39__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_39__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_40 -#define MP0_SYSHUB_SOC_TLB1_40__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_40__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_40__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_41 -#define MP0_SYSHUB_SOC_TLB1_41__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_41__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_41__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_42 -#define MP0_SYSHUB_SOC_TLB1_42__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_42__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_42__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_43 -#define MP0_SYSHUB_SOC_TLB1_43__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_43__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_43__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_44 -#define MP0_SYSHUB_SOC_TLB1_44__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_44__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_44__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_45 -#define MP0_SYSHUB_SOC_TLB1_45__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_45__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_45__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_46 -#define MP0_SYSHUB_SOC_TLB1_46__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_46__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_46__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_47 -#define MP0_SYSHUB_SOC_TLB1_47__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_47__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_47__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_48 -#define MP0_SYSHUB_SOC_TLB1_48__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_48__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_48__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_49 -#define MP0_SYSHUB_SOC_TLB1_49__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_49__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_49__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_50 -#define MP0_SYSHUB_SOC_TLB1_50__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_50__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_50__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_51 -#define MP0_SYSHUB_SOC_TLB1_51__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_51__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_51__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_52 -#define MP0_SYSHUB_SOC_TLB1_52__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_52__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_52__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_53 -#define MP0_SYSHUB_SOC_TLB1_53__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_53__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_53__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_54 -#define MP0_SYSHUB_SOC_TLB1_54__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_54__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_54__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_55 -#define MP0_SYSHUB_SOC_TLB1_55__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_55__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_55__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_56 -#define MP0_SYSHUB_SOC_TLB1_56__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_56__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_56__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_57 -#define MP0_SYSHUB_SOC_TLB1_57__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_57__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_57__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_58 -#define MP0_SYSHUB_SOC_TLB1_58__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_58__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_58__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_59 -#define MP0_SYSHUB_SOC_TLB1_59__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_59__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_59__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_60 -#define MP0_SYSHUB_SOC_TLB1_60__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_60__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_60__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_61 -#define MP0_SYSHUB_SOC_TLB1_61__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_61__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_61__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB1_62 -#define MP0_SYSHUB_SOC_TLB1_62__COHERENCE__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB1_62__SEG_SIZE__SHIFT 0x00000001 -#define MP0_SYSHUB_SOC_TLB1_62__SEG_OFFSET__SHIFT 0x00000005 - -// MP0_SYSHUB_SOC_TLB2_1 -#define MP0_SYSHUB_SOC_TLB2_1__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_2 -#define MP0_SYSHUB_SOC_TLB2_2__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_3 -#define MP0_SYSHUB_SOC_TLB2_3__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_4 -#define MP0_SYSHUB_SOC_TLB2_4__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_5 -#define MP0_SYSHUB_SOC_TLB2_5__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_6 -#define MP0_SYSHUB_SOC_TLB2_6__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_7 -#define MP0_SYSHUB_SOC_TLB2_7__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_8 -#define MP0_SYSHUB_SOC_TLB2_8__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_9 -#define MP0_SYSHUB_SOC_TLB2_9__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_10 -#define MP0_SYSHUB_SOC_TLB2_10__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_11 -#define MP0_SYSHUB_SOC_TLB2_11__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_12 -#define MP0_SYSHUB_SOC_TLB2_12__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_13 -#define MP0_SYSHUB_SOC_TLB2_13__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_14 -#define MP0_SYSHUB_SOC_TLB2_14__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_15 -#define MP0_SYSHUB_SOC_TLB2_15__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_16 -#define MP0_SYSHUB_SOC_TLB2_16__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_17 -#define MP0_SYSHUB_SOC_TLB2_17__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_18 -#define MP0_SYSHUB_SOC_TLB2_18__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_19 -#define MP0_SYSHUB_SOC_TLB2_19__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_20 -#define MP0_SYSHUB_SOC_TLB2_20__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_21 -#define MP0_SYSHUB_SOC_TLB2_21__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_22 -#define MP0_SYSHUB_SOC_TLB2_22__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_23 -#define MP0_SYSHUB_SOC_TLB2_23__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_24 -#define MP0_SYSHUB_SOC_TLB2_24__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_25 -#define MP0_SYSHUB_SOC_TLB2_25__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_26 -#define MP0_SYSHUB_SOC_TLB2_26__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_27 -#define MP0_SYSHUB_SOC_TLB2_27__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_28 -#define MP0_SYSHUB_SOC_TLB2_28__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_29 -#define MP0_SYSHUB_SOC_TLB2_29__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_30 -#define MP0_SYSHUB_SOC_TLB2_30__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_31 -#define MP0_SYSHUB_SOC_TLB2_31__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_32 -#define MP0_SYSHUB_SOC_TLB2_32__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_33 -#define MP0_SYSHUB_SOC_TLB2_33__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_34 -#define MP0_SYSHUB_SOC_TLB2_34__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_35 -#define MP0_SYSHUB_SOC_TLB2_35__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_36 -#define MP0_SYSHUB_SOC_TLB2_36__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_37 -#define MP0_SYSHUB_SOC_TLB2_37__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_38 -#define MP0_SYSHUB_SOC_TLB2_38__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_39 -#define MP0_SYSHUB_SOC_TLB2_39__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_40 -#define MP0_SYSHUB_SOC_TLB2_40__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_41 -#define MP0_SYSHUB_SOC_TLB2_41__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_42 -#define MP0_SYSHUB_SOC_TLB2_42__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_43 -#define MP0_SYSHUB_SOC_TLB2_43__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_44 -#define MP0_SYSHUB_SOC_TLB2_44__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_45 -#define MP0_SYSHUB_SOC_TLB2_45__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_46 -#define MP0_SYSHUB_SOC_TLB2_46__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_47 -#define MP0_SYSHUB_SOC_TLB2_47__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_48 -#define MP0_SYSHUB_SOC_TLB2_48__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_49 -#define MP0_SYSHUB_SOC_TLB2_49__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_50 -#define MP0_SYSHUB_SOC_TLB2_50__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_51 -#define MP0_SYSHUB_SOC_TLB2_51__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_52 -#define MP0_SYSHUB_SOC_TLB2_52__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_53 -#define MP0_SYSHUB_SOC_TLB2_53__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_54 -#define MP0_SYSHUB_SOC_TLB2_54__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_55 -#define MP0_SYSHUB_SOC_TLB2_55__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_56 -#define MP0_SYSHUB_SOC_TLB2_56__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_57 -#define MP0_SYSHUB_SOC_TLB2_57__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_58 -#define MP0_SYSHUB_SOC_TLB2_58__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_59 -#define MP0_SYSHUB_SOC_TLB2_59__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_60 -#define MP0_SYSHUB_SOC_TLB2_60__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_61 -#define MP0_SYSHUB_SOC_TLB2_61__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB2_62 -#define MP0_SYSHUB_SOC_TLB2_62__AWUSER__SHIFT 0x00000000 - -// MP0_SYSHUB_SOC_TLB3_1 -#define MP0_SYSHUB_SOC_TLB3_1__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_1__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_2 -#define MP0_SYSHUB_SOC_TLB3_2__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_2__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_3 -#define MP0_SYSHUB_SOC_TLB3_3__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_3__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_4 -#define MP0_SYSHUB_SOC_TLB3_4__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_4__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_5 -#define MP0_SYSHUB_SOC_TLB3_5__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_5__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_6 -#define MP0_SYSHUB_SOC_TLB3_6__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_6__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_7 -#define MP0_SYSHUB_SOC_TLB3_7__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_7__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_8 -#define MP0_SYSHUB_SOC_TLB3_8__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_8__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_9 -#define MP0_SYSHUB_SOC_TLB3_9__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_9__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_10 -#define MP0_SYSHUB_SOC_TLB3_10__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_10__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_11 -#define MP0_SYSHUB_SOC_TLB3_11__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_11__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_12 -#define MP0_SYSHUB_SOC_TLB3_12__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_12__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_13 -#define MP0_SYSHUB_SOC_TLB3_13__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_13__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_14 -#define MP0_SYSHUB_SOC_TLB3_14__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_14__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_15 -#define MP0_SYSHUB_SOC_TLB3_15__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_15__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_16 -#define MP0_SYSHUB_SOC_TLB3_16__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_16__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_17 -#define MP0_SYSHUB_SOC_TLB3_17__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_17__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_18 -#define MP0_SYSHUB_SOC_TLB3_18__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_18__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_19 -#define MP0_SYSHUB_SOC_TLB3_19__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_19__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_20 -#define MP0_SYSHUB_SOC_TLB3_20__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_20__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_21 -#define MP0_SYSHUB_SOC_TLB3_21__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_21__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_22 -#define MP0_SYSHUB_SOC_TLB3_22__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_22__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_23 -#define MP0_SYSHUB_SOC_TLB3_23__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_23__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_24 -#define MP0_SYSHUB_SOC_TLB3_24__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_24__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_25 -#define MP0_SYSHUB_SOC_TLB3_25__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_25__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_26 -#define MP0_SYSHUB_SOC_TLB3_26__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_26__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_27 -#define MP0_SYSHUB_SOC_TLB3_27__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_27__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_28 -#define MP0_SYSHUB_SOC_TLB3_28__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_28__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_29 -#define MP0_SYSHUB_SOC_TLB3_29__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_29__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_30 -#define MP0_SYSHUB_SOC_TLB3_30__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_30__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_31 -#define MP0_SYSHUB_SOC_TLB3_31__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_31__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_32 -#define MP0_SYSHUB_SOC_TLB3_32__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_32__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_33 -#define MP0_SYSHUB_SOC_TLB3_33__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_33__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_34 -#define MP0_SYSHUB_SOC_TLB3_34__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_34__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_35 -#define MP0_SYSHUB_SOC_TLB3_35__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_35__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_36 -#define MP0_SYSHUB_SOC_TLB3_36__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_36__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_37 -#define MP0_SYSHUB_SOC_TLB3_37__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_37__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_38 -#define MP0_SYSHUB_SOC_TLB3_38__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_38__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_39 -#define MP0_SYSHUB_SOC_TLB3_39__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_39__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_40 -#define MP0_SYSHUB_SOC_TLB3_40__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_40__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_41 -#define MP0_SYSHUB_SOC_TLB3_41__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_41__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_42 -#define MP0_SYSHUB_SOC_TLB3_42__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_42__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_43 -#define MP0_SYSHUB_SOC_TLB3_43__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_43__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_44 -#define MP0_SYSHUB_SOC_TLB3_44__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_44__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_45 -#define MP0_SYSHUB_SOC_TLB3_45__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_45__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_46 -#define MP0_SYSHUB_SOC_TLB3_46__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_46__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_47 -#define MP0_SYSHUB_SOC_TLB3_47__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_47__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_48 -#define MP0_SYSHUB_SOC_TLB3_48__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_48__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_49 -#define MP0_SYSHUB_SOC_TLB3_49__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_49__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_50 -#define MP0_SYSHUB_SOC_TLB3_50__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_50__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_51 -#define MP0_SYSHUB_SOC_TLB3_51__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_51__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_52 -#define MP0_SYSHUB_SOC_TLB3_52__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_52__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_53 -#define MP0_SYSHUB_SOC_TLB3_53__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_53__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_54 -#define MP0_SYSHUB_SOC_TLB3_54__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_54__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_55 -#define MP0_SYSHUB_SOC_TLB3_55__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_55__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_56 -#define MP0_SYSHUB_SOC_TLB3_56__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_56__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_57 -#define MP0_SYSHUB_SOC_TLB3_57__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_57__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_58 -#define MP0_SYSHUB_SOC_TLB3_58__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_58__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_59 -#define MP0_SYSHUB_SOC_TLB3_59__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_59__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_60 -#define MP0_SYSHUB_SOC_TLB3_60__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_60__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_61 -#define MP0_SYSHUB_SOC_TLB3_61__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_61__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_SOC_TLB3_62 -#define MP0_SYSHUB_SOC_TLB3_62__ARUSER__SHIFT 0x00000000 -#define MP0_SYSHUB_SOC_TLB3_62__WUSER__SHIFT 0x0000001a - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB__SHIFT 0x00000000 - -// MP0_SYSHUB_TLB_ATTRIBUTE_1 -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_2 -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_3 -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_4 -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_5 -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_6 -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_7 -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_8 -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_9 -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_10 -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_11 -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_12 -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_13 -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_14 -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_15 -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_16 -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_17 -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_18 -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_19 -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_20 -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_21 -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_22 -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_23 -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_24 -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_25 -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_26 -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_27 -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_28 -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_29 -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_30 -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_31 -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_32 -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_33 -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_34 -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_35 -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_36 -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_37 -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_38 -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_39 -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_40 -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_41 -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_42 -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_43 -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_44 -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_45 -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_46 -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_47 -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_48 -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_49 -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_50 -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_51 -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_52 -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_53 -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_54 -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_55 -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_56 -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_57 -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_58 -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_59 -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_60 -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_61 -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_TLB_ATTRIBUTE_62 -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_CCP__SHIFT 0x00000017 -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB__SHIFT 0x0000001e -#define MP0_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP0_SYSHUB_INT_STATUS -#define MP0_SYSHUB_INT_STATUS__RD_ERROR__SHIFT 0x00000000 -#define MP0_SYSHUB_INT_STATUS__WR_ERROR__SHIFT 0x00000001 -#define MP0_SYSHUB_INT_STATUS__REG_ERROR__SHIFT 0x00000002 - -// MP0_SYSHUB_WR_INT_ADDR -#define MP0_SYSHUB_WR_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_WR_INT_OTHER -#define MP0_SYSHUB_WR_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP0_SYSHUB_WR_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP0_SYSHUB_WR_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP0_SYSHUB_RD_INT_ADDR -#define MP0_SYSHUB_RD_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_RD_INT_OTHER -#define MP0_SYSHUB_RD_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP0_SYSHUB_RD_INT_OTHER__ERROR_LENGTH__SHIFT 0x0000001a -#define MP0_SYSHUB_RD_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP0_SYSHUB_REG_INT_ADDR -#define MP0_SYSHUB_REG_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP0_SYSHUB_REG_INT_OTHER -#define MP0_SYSHUB_REG_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_AES__SHIFT 0x00000014 -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_MST__SHIFT 0x00000015 -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_ADDR__SHIFT 0x00000016 -#define MP0_SYSHUB_REG_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP0_SYSHUB_REG_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP0_SYSHUB_AXCACHE_CFG -#define MP0_SYSHUB_AXCACHE_CFG__ARCACHE_NONCOH__SHIFT 0x00000000 -#define MP0_SYSHUB_AXCACHE_CFG__ARCACHE_COH__SHIFT 0x00000004 -#define MP0_SYSHUB_AXCACHE_CFG__AWCACHE_NONCOH__SHIFT 0x00000008 -#define MP0_SYSHUB_AXCACHE_CFG__AWCACHE_COH__SHIFT 0x0000000c -#define MP0_SYSHUB_AXCACHE_CFG__QOSW__SHIFT 0x00000010 -#define MP0_SYSHUB_AXCACHE_CFG__QOSR__SHIFT 0x00000014 - -// MP0_SYSHUB_DS_OVERRIDE -#define MP0_SYSHUB_DS_OVERRIDE__DS_CNT__SHIFT 0x00000000 -#define MP0_SYSHUB_DS_OVERRIDE__DS_DISABLE__SHIFT 0x0000000b - -// MP0_SYSHUB_OUTSTANDING -#define MP0_SYSHUB_OUTSTANDING__PENDING_WR__SHIFT 0x00000000 -#define MP0_SYSHUB_OUTSTANDING__PENDING_RD__SHIFT 0x00000010 - -// MP1_SMNIF_ERROR -#define MP1_SMNIF_ERROR__RESERVED__SHIFT 0x00000000 - -// MP1_LX3_PDEBUGPC -#define MP1_LX3_PDEBUGPC__PDEBUGPC__SHIFT 0x00000000 - -// MP1_LX3_PWAITMODE -#define MP1_LX3_PWAITMODE__PWAITMODE__SHIFT 0x00000000 - -// MP1_IH_MP0SW_INT_CTXID -#define MP1_IH_MP0SW_INT_CTXID__CTXID__SHIFT 0x00000000 - -// MP1_IH_MP1SW_INT_CTXID -#define MP1_IH_MP1SW_INT_CTXID__CTXID__SHIFT 0x00000000 - -// MP1_IH_DISP_TIMER_ID -#define MP1_IH_DISP_TIMER_ID__DISP_T0_INT_ID__SHIFT 0x00000000 -#define MP1_IH_DISP_TIMER_ID__DISP_T1_INT_ID__SHIFT 0x00000008 - -// MP1_FW_DEBUG_CNT0 -#define MP1_FW_DEBUG_CNT0__DATA__SHIFT 0x00000000 - -// MP1_FW_DEBUG_CNT1 -#define MP1_FW_DEBUG_CNT1__DATA__SHIFT 0x00000000 - -// MP1_FW_DEBUG_CNT2 -#define MP1_FW_DEBUG_CNT2__DATA__SHIFT 0x00000000 - -// MP1_FW_DEBUG_CNT3 -#define MP1_FW_DEBUG_CNT3__DATA__SHIFT 0x00000000 - -// MP1_FW_DEBUG_SIGNAL0 -#define MP1_FW_DEBUG_SIGNAL0__DATA__SHIFT 0x00000000 - -// MP1_FW_DEBUG_SIGNAL1 -#define MP1_FW_DEBUG_SIGNAL1__DATA__SHIFT 0x00000000 - -// MP1_DSM_ENABLE -#define MP1_DSM_ENABLE__MP1_ENB_BREAKINRELAY__SHIFT 0x00000000 -#define MP1_DSM_ENABLE__MP1_ENB_CROSSTRIGGERIN__SHIFT 0x00000001 -#define MP1_DSM_ENABLE__MP1_ENB_DSMINT__SHIFT 0x00000002 -#define MP1_DSM_ENABLE__MP1_ENB_UNUSED__SHIFT 0x00000003 - -// MP1_FIRMWARE_FLAGS -#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x00000000 -#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x00000001 - -// MP1_MUTEX_0 -#define MP1_MUTEX_0__MUTEX__SHIFT 0x00000000 - -// MP1_MUTEX_1 -#define MP1_MUTEX_1__MUTEX__SHIFT 0x00000000 - -// MP1_MUTEX_2 -#define MP1_MUTEX_2__MUTEX__SHIFT 0x00000000 - -// MP1_MUTEX_3 -#define MP1_MUTEX_3__MUTEX__SHIFT 0x00000000 - -// MP1_PUB_SCRATCH0 -#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x00000000 - -// MP1_PUB_SCRATCH1 -#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x00000000 - -// MP1_PUB_SCRATCH2 -#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x00000000 - -// MP1_PUB_SCRATCH3 -#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x00000000 - -// MP1_FW_CHRONO_LO -#define MP1_FW_CHRONO_LO__COUNT__SHIFT 0x00000000 - -// MP1_FW_CHRONO_HI -#define MP1_FW_CHRONO_HI__COUNT__SHIFT 0x00000000 - -// MP1_C2PMSG_0 -#define MP1_C2PMSG_0__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_1 -#define MP1_C2PMSG_1__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_2 -#define MP1_C2PMSG_2__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_3 -#define MP1_C2PMSG_3__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_4 -#define MP1_C2PMSG_4__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_5 -#define MP1_C2PMSG_5__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_6 -#define MP1_C2PMSG_6__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_7 -#define MP1_C2PMSG_7__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_8 -#define MP1_C2PMSG_8__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_9 -#define MP1_C2PMSG_9__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_10 -#define MP1_C2PMSG_10__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_11 -#define MP1_C2PMSG_11__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_12 -#define MP1_C2PMSG_12__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_13 -#define MP1_C2PMSG_13__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_14 -#define MP1_C2PMSG_14__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_15 -#define MP1_C2PMSG_15__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_16 -#define MP1_C2PMSG_16__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_17 -#define MP1_C2PMSG_17__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_18 -#define MP1_C2PMSG_18__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_19 -#define MP1_C2PMSG_19__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_20 -#define MP1_C2PMSG_20__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_21 -#define MP1_C2PMSG_21__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_22 -#define MP1_C2PMSG_22__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_23 -#define MP1_C2PMSG_23__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_24 -#define MP1_C2PMSG_24__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_25 -#define MP1_C2PMSG_25__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_26 -#define MP1_C2PMSG_26__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_27 -#define MP1_C2PMSG_27__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_28 -#define MP1_C2PMSG_28__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_29 -#define MP1_C2PMSG_29__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_30 -#define MP1_C2PMSG_30__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_31 -#define MP1_C2PMSG_31__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_32 -#define MP1_C2PMSG_32__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_33 -#define MP1_C2PMSG_33__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_34 -#define MP1_C2PMSG_34__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_35 -#define MP1_C2PMSG_35__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_36 -#define MP1_C2PMSG_36__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_37 -#define MP1_C2PMSG_37__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_38 -#define MP1_C2PMSG_38__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_39 -#define MP1_C2PMSG_39__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_40 -#define MP1_C2PMSG_40__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_41 -#define MP1_C2PMSG_41__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_42 -#define MP1_C2PMSG_42__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_43 -#define MP1_C2PMSG_43__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_44 -#define MP1_C2PMSG_44__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_45 -#define MP1_C2PMSG_45__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_46 -#define MP1_C2PMSG_46__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_47 -#define MP1_C2PMSG_47__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_48 -#define MP1_C2PMSG_48__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_49 -#define MP1_C2PMSG_49__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_50 -#define MP1_C2PMSG_50__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_51 -#define MP1_C2PMSG_51__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_52 -#define MP1_C2PMSG_52__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_53 -#define MP1_C2PMSG_53__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_54 -#define MP1_C2PMSG_54__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_55 -#define MP1_C2PMSG_55__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_56 -#define MP1_C2PMSG_56__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_57 -#define MP1_C2PMSG_57__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_58 -#define MP1_C2PMSG_58__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_59 -#define MP1_C2PMSG_59__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_60 -#define MP1_C2PMSG_60__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_61 -#define MP1_C2PMSG_61__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_62 -#define MP1_C2PMSG_62__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_63 -#define MP1_C2PMSG_63__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_64 -#define MP1_C2PMSG_64__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_65 -#define MP1_C2PMSG_65__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_66 -#define MP1_C2PMSG_66__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_67 -#define MP1_C2PMSG_67__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_68 -#define MP1_C2PMSG_68__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_69 -#define MP1_C2PMSG_69__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_70 -#define MP1_C2PMSG_70__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_71 -#define MP1_C2PMSG_71__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_72 -#define MP1_C2PMSG_72__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_73 -#define MP1_C2PMSG_73__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_74 -#define MP1_C2PMSG_74__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_75 -#define MP1_C2PMSG_75__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_76 -#define MP1_C2PMSG_76__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_77 -#define MP1_C2PMSG_77__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_78 -#define MP1_C2PMSG_78__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_79 -#define MP1_C2PMSG_79__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_80 -#define MP1_C2PMSG_80__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_81 -#define MP1_C2PMSG_81__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_82 -#define MP1_C2PMSG_82__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_83 -#define MP1_C2PMSG_83__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_84 -#define MP1_C2PMSG_84__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_85 -#define MP1_C2PMSG_85__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_86 -#define MP1_C2PMSG_86__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_87 -#define MP1_C2PMSG_87__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_88 -#define MP1_C2PMSG_88__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_89 -#define MP1_C2PMSG_89__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_90 -#define MP1_C2PMSG_90__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_91 -#define MP1_C2PMSG_91__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_92 -#define MP1_C2PMSG_92__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_93 -#define MP1_C2PMSG_93__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_94 -#define MP1_C2PMSG_94__CONTENT__SHIFT 0x00000000 - -// MP1_C2PMSG_95 -#define MP1_C2PMSG_95__CONTENT__SHIFT 0x00000000 - -// MP1_P2CMSG_0 -#define MP1_P2CMSG_0__CONTENT__SHIFT 0x00000000 - -// MP1_P2CMSG_1 -#define MP1_P2CMSG_1__CONTENT__SHIFT 0x00000000 - -// MP1_P2CMSG_2 -#define MP1_P2CMSG_2__CONTENT__SHIFT 0x00000000 - -// MP1_P2CMSG_3 -#define MP1_P2CMSG_3__CONTENT__SHIFT 0x00000000 - -// MP1_P2CMSG_INTEN -#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x00000000 - -// MP1_P2CMSG_INTSTS -#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x00000003 - -// MP1_P2SMSG_0 -#define MP1_P2SMSG_0__CONTENT__SHIFT 0x00000000 - -// MP1_P2SMSG_1 -#define MP1_P2SMSG_1__CONTENT__SHIFT 0x00000000 - -// MP1_P2SMSG_2 -#define MP1_P2SMSG_2__CONTENT__SHIFT 0x00000000 - -// MP1_P2SMSG_3 -#define MP1_P2SMSG_3__CONTENT__SHIFT 0x00000000 - -// MP1_P2SMSG_INTSTS -#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x00000003 - -// MP1_S2PMSG_0 -#define MP1_S2PMSG_0__CONTENT__SHIFT 0x00000000 - -// MP1_PUB_RSMU_HCID -#define MP1_PUB_RSMU_HCID__HwRev__SHIFT 0x00000000 -#define MP1_PUB_RSMU_HCID__HwMinVer__SHIFT 0x00000006 -#define MP1_PUB_RSMU_HCID__HwMajVer__SHIFT 0x0000000d -#define MP1_PUB_RSMU_HCID__HwID__SHIFT 0x00000014 - -// MP1_PUB_RSMU_SIID -#define MP1_PUB_RSMU_SIID__SwIfRev__SHIFT 0x00000000 -#define MP1_PUB_RSMU_SIID__SwIfMinVer__SHIFT 0x00000006 -#define MP1_PUB_RSMU_SIID__SwIfMajVer__SHIFT 0x0000000d -#define MP1_PUB_RSMU_SIID__SwIfID__SHIFT 0x00000014 - -// MP1_SRBMTMR_0_CTRL0 -#define MP1_SRBMTMR_0_CTRL0__START__SHIFT 0x00000000 -#define MP1_SRBMTMR_0_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_SRBMTMR_0_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_SRBMTMR_0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_SRBMTMR_1_CTRL0 -#define MP1_SRBMTMR_1_CTRL0__START__SHIFT 0x00000000 -#define MP1_SRBMTMR_1_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_SRBMTMR_1_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_SRBMTMR_1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_SRBMTMR_0_CTRL1 -#define MP1_SRBMTMR_0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_SRBMTMR_0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_SRBMTMR_0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_SRBMTMR_0_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_SRBMTMR_1_CTRL1 -#define MP1_SRBMTMR_1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_SRBMTMR_1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_SRBMTMR_1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_SRBMTMR_1_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_SRBMTMR_0_CMP_AUTOINC -#define MP1_SRBMTMR_0_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_SRBMTMR_0_CMP_AUTOINC__RESERVED__SHIFT 0x00000001 - -// MP1_SRBMTMR_1_CMP_AUTOINC -#define MP1_SRBMTMR_1_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_SRBMTMR_1_CMP_AUTOINC__RESERVED__SHIFT 0x00000001 - -// MP1_SRBMTMR_0_INTEN -#define MP1_SRBMTMR_0_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_SRBMTMR_0_INTEN__RESERVED__SHIFT 0x00000001 - -// MP1_SRBMTMR_1_INTEN -#define MP1_SRBMTMR_1_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_SRBMTMR_1_INTEN__RESERVED__SHIFT 0x00000001 - -// MP1_SRBMTMR_OCMP_0_0 -#define MP1_SRBMTMR_OCMP_0_0__OCMP__SHIFT 0x00000000 - -// MP1_SRBMTMR_OCMP_1_0 -#define MP1_SRBMTMR_OCMP_1_0__OCMP__SHIFT 0x00000000 - -// MP1_SRBMTMR_0_CNT -#define MP1_SRBMTMR_0_CNT__COUNT__SHIFT 0x00000000 - -// MP1_SRBMTMR_1_CNT -#define MP1_SRBMTMR_1_CNT__COUNT__SHIFT 0x00000000 - -// MP1_ACP2MP_RESP -#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_DC2MP_RESP -#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_UVD2MP_RESP -#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_VCE2MP_RESP -#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_RLC2MP_RESP -#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_IH_MP0SW_INT -#define MP1_IH_MP0SW_INT__VALID__SHIFT 0x00000000 -#define MP1_IH_MP0SW_INT__ID__SHIFT 0x00000001 - -// MP1_IH_MP1SW_INT -#define MP1_IH_MP1SW_INT__VALID__SHIFT 0x00000000 -#define MP1_IH_MP1SW_INT__ID__SHIFT 0x00000001 - -// MP1_IH_SW_INT_CTRL -#define MP1_IH_SW_INT_CTRL__MAX_CREDIT_VALUE__SHIFT 0x00000000 -#define MP1_IH_SW_INT_CTRL__MP0_SW_TRIG_MASK__SHIFT 0x00000005 -#define MP1_IH_SW_INT_CTRL__MP0_SW_INT_ACK__SHIFT 0x00000006 -#define MP1_IH_SW_INT_CTRL__MP1_SW_TRIG_MASK__SHIFT 0x00000007 -#define MP1_IH_SW_INT_CTRL__MP1_SW_INT_ACK__SHIFT 0x00000008 - -// MP1_IH_DISPTMR0_INT_CTRL -#define MP1_IH_DISPTMR0_INT_CTRL__STATUS__SHIFT 0x00000000 -#define MP1_IH_DISPTMR0_INT_CTRL__UNMASK__SHIFT 0x00000001 -#define MP1_IH_DISPTMR0_INT_CTRL__TYPE__SHIFT 0x00000002 -#define MP1_IH_DISPTMR0_INT_CTRL__ACK__SHIFT 0x00000003 -#define MP1_IH_DISPTMR0_INT_CTRL__MASK__SHIFT 0x00000004 - -// MP1_IH_DISPTMR1_INT_CTRL -#define MP1_IH_DISPTMR1_INT_CTRL__STATUS__SHIFT 0x00000000 -#define MP1_IH_DISPTMR1_INT_CTRL__UNMASK__SHIFT 0x00000001 -#define MP1_IH_DISPTMR1_INT_CTRL__TYPE__SHIFT 0x00000002 -#define MP1_IH_DISPTMR1_INT_CTRL__ACK__SHIFT 0x00000003 -#define MP1_IH_DISPTMR1_INT_CTRL__MASK__SHIFT 0x00000004 - -// MP1_FPS_CNT -#define MP1_FPS_CNT__COUNT__SHIFT 0x00000000 - -// MP1_REVID -#define MP1_REVID__REVID__SHIFT 0x00000000 - -// MP1_RSMU_HCID -#define MP1_RSMU_HCID__HwRev__SHIFT 0x00000000 -#define MP1_RSMU_HCID__HwMinVer__SHIFT 0x00000006 -#define MP1_RSMU_HCID__HwMajVer__SHIFT 0x0000000d -#define MP1_RSMU_HCID__HwID__SHIFT 0x00000014 - -// MP1_RSMU_SIID -#define MP1_RSMU_SIID__SwIfRev__SHIFT 0x00000000 -#define MP1_RSMU_SIID__SwIfMinVer__SHIFT 0x00000006 -#define MP1_RSMU_SIID__SwIfMajVer__SHIFT 0x0000000d -#define MP1_RSMU_SIID__SwIfID__SHIFT 0x00000014 - -// MP1_RAM_REPAIR_DONE -#define MP1_RAM_REPAIR_DONE__STATUS__SHIFT 0x00000000 - -// MP1_RAM_REPAIR_RESULT -#define MP1_RAM_REPAIR_RESULT__PASS__SHIFT 0x00000000 - -// MP1_FUSE_HARVESTING -#define MP1_FUSE_HARVESTING__DATA__SHIFT 0x00000000 - -// MP1_FUSE_RMBITS -#define MP1_FUSE_RMBITS__RM__SHIFT 0x00000000 -#define MP1_FUSE_RMBITS__RM_RESERVED__SHIFT 0x00000009 -#define MP1_FUSE_RMBITS__BC__SHIFT 0x00000010 -#define MP1_FUSE_RMBITS__BC_RESERVED__SHIFT 0x00000016 - -// MP1_SMS_CFG -#define MP1_SMS_CFG__SMS_RESETB__SHIFT 0x00000000 -#define MP1_SMS_CFG__RUN_BIHR__SHIFT 0x00000008 -#define MP1_SMS_CFG__RUN_MBIST__SHIFT 0x00000009 -#define MP1_SMS_CFG__SMS_FUSE_VALID__SHIFT 0x00000010 -#define MP1_SMS_CFG__SMS_NEXT_FETCH__SHIFT 0x00000018 -#define MP1_SMS_CFG__RAM_REPAIR_DONE__SHIFT 0x00000019 -#define MP1_SMS_CFG__RAM_BIST_FAIL__SHIFT 0x0000001a - -// MP1_FUSE_SMS_0 -#define MP1_FUSE_SMS_0__DATA__SHIFT 0x00000000 - -// MP1_FUSE_SMS_1 -#define MP1_FUSE_SMS_1__DATA__SHIFT 0x00000000 - -// MP1_FUSE_SMS_2 -#define MP1_FUSE_SMS_2__DATA__SHIFT 0x00000000 - -// MP1_FUSE_SMS_3 -#define MP1_FUSE_SMS_3__DATA__SHIFT 0x00000000 - -// MP1_FUSE_SMS_4 -#define MP1_FUSE_SMS_4__DATA__SHIFT 0x00000000 - -// MP1_FUSE_SMS_5 -#define MP1_FUSE_SMS_5__DATA__SHIFT 0x00000000 - -// MP1_FUSE_SMS_6 -#define MP1_FUSE_SMS_6__DATA__SHIFT 0x00000000 - -// MP1_FUSE_SMS_7 -#define MP1_FUSE_SMS_7__DATA__SHIFT 0x00000000 - -// MP1_ACC_VIO_INTSTS -#define MP1_ACC_VIO_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP1_ACC_VIO_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP1_ACC_VIO_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP1_ACC_VIO_INTSTS__INTSTS3__SHIFT 0x00000003 -#define MP1_ACC_VIO_INTSTS__INTSTS4__SHIFT 0x00000004 -#define MP1_ACC_VIO_INTSTS__INTSTS5__SHIFT 0x00000005 -#define MP1_ACC_VIO_INTSTS__INTSTS6__SHIFT 0x00000006 -#define MP1_ACC_VIO_INTSTS__INTSTS7__SHIFT 0x00000007 -#define MP1_ACC_VIO_INTSTS__INTSTS8__SHIFT 0x00000008 -#define MP1_ACC_VIO_INTSTS__INTSTS9__SHIFT 0x00000009 -#define MP1_ACC_VIO_INTSTS__INTSTS10__SHIFT 0x0000000a -#define MP1_ACC_VIO_INTSTS__INTSTS11__SHIFT 0x0000000b -#define MP1_ACC_VIO_INTSTS__INTSTS12__SHIFT 0x0000000c -#define MP1_ACC_VIO_INTSTS__INTSTS13__SHIFT 0x0000000d -#define MP1_ACC_VIO_INTSTS__INTSTS14__SHIFT 0x0000000e -#define MP1_ACC_VIO_INTSTS__INTSTS15__SHIFT 0x0000000f -#define MP1_ACC_VIO_INTSTS__INTSTS16__SHIFT 0x00000010 -#define MP1_ACC_VIO_INTSTS__INTSTS17__SHIFT 0x00000011 -#define MP1_ACC_VIO_INTSTS__INTSTS18__SHIFT 0x00000012 -#define MP1_ACC_VIO_INTSTS__INTSTS19__SHIFT 0x00000013 -#define MP1_ACC_VIO_INTSTS__INTSTS20__SHIFT 0x00000014 -#define MP1_ACC_VIO_INTSTS__INTSTS21__SHIFT 0x00000015 -#define MP1_ACC_VIO_INTSTS__INTSTS22__SHIFT 0x00000016 -#define MP1_ACC_VIO_INTSTS__INTSTS23__SHIFT 0x00000017 -#define MP1_ACC_VIO_INTSTS__INTSTS24__SHIFT 0x00000018 -#define MP1_ACC_VIO_INTSTS__INTSTS25__SHIFT 0x00000019 -#define MP1_ACC_VIO_INTSTS__INTSTS26__SHIFT 0x0000001a -#define MP1_ACC_VIO_INTSTS__INTSTS27__SHIFT 0x0000001b -#define MP1_ACC_VIO_INTSTS__INTSTS28__SHIFT 0x0000001c -#define MP1_ACC_VIO_INTSTS__INTSTS29__SHIFT 0x0000001d -#define MP1_ACC_VIO_INTSTS__INTSTS30__SHIFT 0x0000001e -#define MP1_ACC_VIO_INTSTS__INTSTS31__SHIFT 0x0000001f - -// MP1_TDR_MISC0_STATUS -#define MP1_TDR_MISC0_STATUS__DATA__SHIFT 0x00000000 - -// MP1_EVCNTCTL -#define MP1_EVCNTCTL__EVENTCNT_EN__SHIFT 0x00000000 -#define MP1_EVCNTCTL__EVENTCNT_RSTB__SHIFT 0x00000001 -#define MP1_EVCNTCTL__EVENTCNT_SHADOW__SHIFT 0x00000002 - -// MP1_EVCNTSEL -#define MP1_EVCNTSEL__EVENT0_BLK__SHIFT 0x00000000 -#define MP1_EVCNTSEL__EVENT0_SEL__SHIFT 0x00000008 -#define MP1_EVCNTSEL__EVENT1_BLK__SHIFT 0x00000010 -#define MP1_EVCNTSEL__EVENT1_SEL__SHIFT 0x00000018 - -// MP1_EVCNT0 -#define MP1_EVCNT0__EVENTCNT0__SHIFT 0x00000000 - -// MP1_EVCNT1 -#define MP1_EVCNT1__EVENTCNT1__SHIFT 0x00000000 - -// MP1_EVCNTHI -#define MP1_EVCNTHI__EVENTCNT0_HI__SHIFT 0x00000000 -#define MP1_EVCNTHI__EVENTCNT1_HI__SHIFT 0x00000010 - -// MP1_J2P_MBOX0 -#define MP1_J2P_MBOX0__MBX__SHIFT 0x00000000 - -// MP1_J2P_MBOX1 -#define MP1_J2P_MBOX1__MBX__SHIFT 0x00000000 - -// MP1_J2P_ATTR -#define MP1_J2P_ATTR__J2P_ATTR__SHIFT 0x00000000 - -// MP1_CRU_ACC_VIO_INTSTS -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS0__SHIFT 0x00000000 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS1__SHIFT 0x00000001 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS2__SHIFT 0x00000002 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS3__SHIFT 0x00000003 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS4__SHIFT 0x00000004 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS5__SHIFT 0x00000005 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS6__SHIFT 0x00000006 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS7__SHIFT 0x00000007 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS8__SHIFT 0x00000008 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS9__SHIFT 0x00000009 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS10__SHIFT 0x0000000a -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS11__SHIFT 0x0000000b -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS12__SHIFT 0x0000000c -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS13__SHIFT 0x0000000d -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS14__SHIFT 0x0000000e -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS15__SHIFT 0x0000000f -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS16__SHIFT 0x00000010 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS17__SHIFT 0x00000011 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS18__SHIFT 0x00000012 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS19__SHIFT 0x00000013 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS20__SHIFT 0x00000014 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS21__SHIFT 0x00000015 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS22__SHIFT 0x00000016 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS23__SHIFT 0x00000017 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS24__SHIFT 0x00000018 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS25__SHIFT 0x00000019 -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS26__SHIFT 0x0000001a -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS27__SHIFT 0x0000001b -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS28__SHIFT 0x0000001c -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS29__SHIFT 0x0000001d -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS30__SHIFT 0x0000001e -#define MP1_CRU_ACC_VIO_INTSTS__INTSTS31__SHIFT 0x0000001f - -// MP1_ACC_VIOL_LOG0 -#define MP1_ACC_VIOL_LOG0__AXI_ACC_VIO_LOG__SHIFT 0x00000000 -#define MP1_ACC_VIOL_LOG0__AXI_LOG_CLEAR__SHIFT 0x0000001f - -// MP1_ACC_VIOL_LOG1 -#define MP1_ACC_VIOL_LOG1__AXI_ACC_VIO_ADDR__SHIFT 0x00000000 - -// MP1_SEC_SCRATCH0 -#define MP1_SEC_SCRATCH0__DATA__SHIFT 0x00000000 - -// MP1_SEC_SCRATCH1 -#define MP1_SEC_SCRATCH1__DATA__SHIFT 0x00000000 - -// MP1_SEC_SCRATCH2 -#define MP1_SEC_SCRATCH2__DATA__SHIFT 0x00000000 - -// MP1_SEC_SCRATCH3 -#define MP1_SEC_SCRATCH3__DATA__SHIFT 0x00000000 - -// MP1_STICKY -#define MP1_STICKY__DATA__SHIFT 0x00000000 - -// MP1_CRU_MISC_CTRL -#define MP1_CRU_MISC_CTRL__ERROR_RESPONSE_ON_ACCVIOL__SHIFT 0x00000000 - -// MP1_SOFT_RESET_CTRL -#define MP1_SOFT_RESET_CTRL__MP_MMU_RESET__SHIFT 0x00000000 -#define MP1_SOFT_RESET_CTRL__MP_CPU_RESET__SHIFT 0x00000001 -#define MP1_SOFT_RESET_CTRL__MP_SMNIF_RESET__SHIFT 0x00000002 -#define MP1_SOFT_RESET_CTRL__MP_DMAC_RESET__SHIFT 0x00000003 -#define MP1_SOFT_RESET_CTRL__MP_HUBIFNB_RESET__SHIFT 0x00000004 -#define MP1_SOFT_RESET_CTRL__MP_SHUBIF_RESET__SHIFT 0x00000008 -#define MP1_SOFT_RESET_CTRL__MP_MHUBIF_RESET__SHIFT 0x00000009 - -// MP1_NS_PROT_FAULT_STATUS_0 -#define MP1_NS_PROT_FAULT_STATUS_0__MMU_CFG_NS0_VIOL__SHIFT 0x00000000 -#define MP1_NS_PROT_FAULT_STATUS_0__MMU_SRAM_NS0_VIOL__SHIFT 0x00000001 -#define MP1_NS_PROT_FAULT_STATUS_0__CRU_NS0_VIOL__SHIFT 0x00000004 - -// MP1_FW_MISC_CTRL -#define MP1_FW_MISC_CTRL__MP_FW_VALUE__SHIFT 0x00000000 - -// MP1_AEB_STATUS_0 -#define MP1_AEB_STATUS_0__MP1_AEB_DBG_BUS_en__SHIFT 0x00000000 -#define MP1_AEB_STATUS_0__MP1_AEB_CPU_DBG_TDRs_en__SHIFT 0x00000001 -#define MP1_AEB_STATUS_0__MP1_AEB_JTAG_AXI_master_en__SHIFT 0x00000002 -#define MP1_AEB_STATUS_0__MP1_AEB_DIS_SCAN_DUMP_en__SHIFT 0x00000003 - -// MP1_PIC0_MASK_0 -#define MP1_PIC0_MASK_0__INTR_MASK_0__SHIFT 0x00000000 -#define MP1_PIC0_MASK_0__INTR_MASK_1__SHIFT 0x00000001 -#define MP1_PIC0_MASK_0__INTR_MASK_2__SHIFT 0x00000002 -#define MP1_PIC0_MASK_0__INTR_MASK_3__SHIFT 0x00000003 -#define MP1_PIC0_MASK_0__INTR_MASK_4__SHIFT 0x00000004 -#define MP1_PIC0_MASK_0__INTR_MASK_5__SHIFT 0x00000005 -#define MP1_PIC0_MASK_0__INTR_MASK_6__SHIFT 0x00000006 -#define MP1_PIC0_MASK_0__INTR_MASK_7__SHIFT 0x00000007 - -// MP1_PIC0_LEVEL_0 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC0_LEVEL_0__INTR_TRIGGER_7__SHIFT 0x00000007 - -// MP1_PIC0_EDGE_0 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC0_EDGE_0__INTR_TRIGGER_7__SHIFT 0x00000007 - -// MP1_PIC0_PRIORITY_0 -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC0_PRIORITY_0__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC0_PRIORITY_1 -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC0_PRIORITY_1__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC0_STATUS_0 -#define MP1_PIC0_STATUS_0__INTR_FLAG_0__SHIFT 0x00000000 -#define MP1_PIC0_STATUS_0__INTR_FLAG_1__SHIFT 0x00000001 -#define MP1_PIC0_STATUS_0__INTR_FLAG_2__SHIFT 0x00000002 -#define MP1_PIC0_STATUS_0__INTR_FLAG_3__SHIFT 0x00000003 -#define MP1_PIC0_STATUS_0__INTR_FLAG_4__SHIFT 0x00000004 -#define MP1_PIC0_STATUS_0__INTR_FLAG_5__SHIFT 0x00000005 -#define MP1_PIC0_STATUS_0__INTR_FLAG_6__SHIFT 0x00000006 -#define MP1_PIC0_STATUS_0__INTR_FLAG_7__SHIFT 0x00000007 - -// MP1_PIC0_INTR -#define MP1_PIC0_INTR__INTR_LINE__SHIFT 0x00000000 -#define MP1_PIC0_INTR__RESERVED__SHIFT 0x00000001 - -// MP1_PIC0_ID -#define MP1_PIC0_ID__INTR_ID__SHIFT 0x00000000 -#define MP1_PIC0_ID__RESERVED__SHIFT 0x00000008 - -// MP1_PIC1_MASK_0 -#define MP1_PIC1_MASK_0__INTR_MASK_0__SHIFT 0x00000000 -#define MP1_PIC1_MASK_0__INTR_MASK_1__SHIFT 0x00000001 -#define MP1_PIC1_MASK_0__INTR_MASK_2__SHIFT 0x00000002 -#define MP1_PIC1_MASK_0__INTR_MASK_3__SHIFT 0x00000003 -#define MP1_PIC1_MASK_0__INTR_MASK_4__SHIFT 0x00000004 -#define MP1_PIC1_MASK_0__INTR_MASK_5__SHIFT 0x00000005 -#define MP1_PIC1_MASK_0__INTR_MASK_6__SHIFT 0x00000006 -#define MP1_PIC1_MASK_0__INTR_MASK_7__SHIFT 0x00000007 -#define MP1_PIC1_MASK_0__INTR_MASK_8__SHIFT 0x00000008 -#define MP1_PIC1_MASK_0__INTR_MASK_9__SHIFT 0x00000009 -#define MP1_PIC1_MASK_0__INTR_MASK_10__SHIFT 0x0000000a -#define MP1_PIC1_MASK_0__INTR_MASK_11__SHIFT 0x0000000b -#define MP1_PIC1_MASK_0__INTR_MASK_12__SHIFT 0x0000000c -#define MP1_PIC1_MASK_0__INTR_MASK_13__SHIFT 0x0000000d -#define MP1_PIC1_MASK_0__INTR_MASK_14__SHIFT 0x0000000e -#define MP1_PIC1_MASK_0__INTR_MASK_15__SHIFT 0x0000000f -#define MP1_PIC1_MASK_0__INTR_MASK_16__SHIFT 0x00000010 -#define MP1_PIC1_MASK_0__INTR_MASK_17__SHIFT 0x00000011 -#define MP1_PIC1_MASK_0__INTR_MASK_18__SHIFT 0x00000012 -#define MP1_PIC1_MASK_0__INTR_MASK_19__SHIFT 0x00000013 -#define MP1_PIC1_MASK_0__INTR_MASK_20__SHIFT 0x00000014 -#define MP1_PIC1_MASK_0__INTR_MASK_21__SHIFT 0x00000015 -#define MP1_PIC1_MASK_0__INTR_MASK_22__SHIFT 0x00000016 -#define MP1_PIC1_MASK_0__INTR_MASK_23__SHIFT 0x00000017 -#define MP1_PIC1_MASK_0__INTR_MASK_24__SHIFT 0x00000018 -#define MP1_PIC1_MASK_0__INTR_MASK_25__SHIFT 0x00000019 -#define MP1_PIC1_MASK_0__INTR_MASK_26__SHIFT 0x0000001a -#define MP1_PIC1_MASK_0__INTR_MASK_27__SHIFT 0x0000001b -#define MP1_PIC1_MASK_0__INTR_MASK_28__SHIFT 0x0000001c -#define MP1_PIC1_MASK_0__INTR_MASK_29__SHIFT 0x0000001d -#define MP1_PIC1_MASK_0__INTR_MASK_30__SHIFT 0x0000001e -#define MP1_PIC1_MASK_0__INTR_MASK_31__SHIFT 0x0000001f - -// MP1_PIC1_MASK_1 -#define MP1_PIC1_MASK_1__INTR_MASK_0__SHIFT 0x00000000 -#define MP1_PIC1_MASK_1__INTR_MASK_1__SHIFT 0x00000001 -#define MP1_PIC1_MASK_1__INTR_MASK_2__SHIFT 0x00000002 -#define MP1_PIC1_MASK_1__INTR_MASK_3__SHIFT 0x00000003 -#define MP1_PIC1_MASK_1__INTR_MASK_4__SHIFT 0x00000004 -#define MP1_PIC1_MASK_1__INTR_MASK_5__SHIFT 0x00000005 -#define MP1_PIC1_MASK_1__INTR_MASK_6__SHIFT 0x00000006 -#define MP1_PIC1_MASK_1__INTR_MASK_7__SHIFT 0x00000007 -#define MP1_PIC1_MASK_1__INTR_MASK_8__SHIFT 0x00000008 -#define MP1_PIC1_MASK_1__INTR_MASK_9__SHIFT 0x00000009 -#define MP1_PIC1_MASK_1__INTR_MASK_10__SHIFT 0x0000000a -#define MP1_PIC1_MASK_1__INTR_MASK_11__SHIFT 0x0000000b -#define MP1_PIC1_MASK_1__INTR_MASK_12__SHIFT 0x0000000c -#define MP1_PIC1_MASK_1__INTR_MASK_13__SHIFT 0x0000000d -#define MP1_PIC1_MASK_1__INTR_MASK_14__SHIFT 0x0000000e -#define MP1_PIC1_MASK_1__INTR_MASK_15__SHIFT 0x0000000f -#define MP1_PIC1_MASK_1__INTR_MASK_16__SHIFT 0x00000010 -#define MP1_PIC1_MASK_1__INTR_MASK_17__SHIFT 0x00000011 -#define MP1_PIC1_MASK_1__INTR_MASK_18__SHIFT 0x00000012 -#define MP1_PIC1_MASK_1__INTR_MASK_19__SHIFT 0x00000013 -#define MP1_PIC1_MASK_1__INTR_MASK_20__SHIFT 0x00000014 -#define MP1_PIC1_MASK_1__INTR_MASK_21__SHIFT 0x00000015 -#define MP1_PIC1_MASK_1__INTR_MASK_22__SHIFT 0x00000016 -#define MP1_PIC1_MASK_1__INTR_MASK_23__SHIFT 0x00000017 -#define MP1_PIC1_MASK_1__INTR_MASK_24__SHIFT 0x00000018 -#define MP1_PIC1_MASK_1__INTR_MASK_25__SHIFT 0x00000019 -#define MP1_PIC1_MASK_1__INTR_MASK_26__SHIFT 0x0000001a -#define MP1_PIC1_MASK_1__INTR_MASK_27__SHIFT 0x0000001b -#define MP1_PIC1_MASK_1__INTR_MASK_28__SHIFT 0x0000001c -#define MP1_PIC1_MASK_1__INTR_MASK_29__SHIFT 0x0000001d -#define MP1_PIC1_MASK_1__INTR_MASK_30__SHIFT 0x0000001e -#define MP1_PIC1_MASK_1__INTR_MASK_31__SHIFT 0x0000001f - -// MP1_PIC1_MASK_2 -#define MP1_PIC1_MASK_2__INTR_MASK_0__SHIFT 0x00000000 -#define MP1_PIC1_MASK_2__INTR_MASK_1__SHIFT 0x00000001 -#define MP1_PIC1_MASK_2__INTR_MASK_2__SHIFT 0x00000002 -#define MP1_PIC1_MASK_2__INTR_MASK_3__SHIFT 0x00000003 -#define MP1_PIC1_MASK_2__INTR_MASK_4__SHIFT 0x00000004 -#define MP1_PIC1_MASK_2__INTR_MASK_5__SHIFT 0x00000005 -#define MP1_PIC1_MASK_2__INTR_MASK_6__SHIFT 0x00000006 -#define MP1_PIC1_MASK_2__INTR_MASK_7__SHIFT 0x00000007 -#define MP1_PIC1_MASK_2__INTR_MASK_8__SHIFT 0x00000008 -#define MP1_PIC1_MASK_2__INTR_MASK_9__SHIFT 0x00000009 -#define MP1_PIC1_MASK_2__INTR_MASK_10__SHIFT 0x0000000a -#define MP1_PIC1_MASK_2__INTR_MASK_11__SHIFT 0x0000000b -#define MP1_PIC1_MASK_2__INTR_MASK_12__SHIFT 0x0000000c -#define MP1_PIC1_MASK_2__INTR_MASK_13__SHIFT 0x0000000d -#define MP1_PIC1_MASK_2__INTR_MASK_14__SHIFT 0x0000000e -#define MP1_PIC1_MASK_2__INTR_MASK_15__SHIFT 0x0000000f -#define MP1_PIC1_MASK_2__INTR_MASK_16__SHIFT 0x00000010 -#define MP1_PIC1_MASK_2__INTR_MASK_17__SHIFT 0x00000011 -#define MP1_PIC1_MASK_2__INTR_MASK_18__SHIFT 0x00000012 -#define MP1_PIC1_MASK_2__INTR_MASK_19__SHIFT 0x00000013 -#define MP1_PIC1_MASK_2__INTR_MASK_20__SHIFT 0x00000014 -#define MP1_PIC1_MASK_2__INTR_MASK_21__SHIFT 0x00000015 -#define MP1_PIC1_MASK_2__INTR_MASK_22__SHIFT 0x00000016 -#define MP1_PIC1_MASK_2__INTR_MASK_23__SHIFT 0x00000017 -#define MP1_PIC1_MASK_2__INTR_MASK_24__SHIFT 0x00000018 -#define MP1_PIC1_MASK_2__INTR_MASK_25__SHIFT 0x00000019 -#define MP1_PIC1_MASK_2__INTR_MASK_26__SHIFT 0x0000001a -#define MP1_PIC1_MASK_2__INTR_MASK_27__SHIFT 0x0000001b -#define MP1_PIC1_MASK_2__INTR_MASK_28__SHIFT 0x0000001c -#define MP1_PIC1_MASK_2__INTR_MASK_29__SHIFT 0x0000001d -#define MP1_PIC1_MASK_2__INTR_MASK_30__SHIFT 0x0000001e -#define MP1_PIC1_MASK_2__INTR_MASK_31__SHIFT 0x0000001f - -// MP1_PIC1_MASK_3 -#define MP1_PIC1_MASK_3__INTR_MASK_0__SHIFT 0x00000000 -#define MP1_PIC1_MASK_3__INTR_MASK_1__SHIFT 0x00000001 -#define MP1_PIC1_MASK_3__INTR_MASK_2__SHIFT 0x00000002 -#define MP1_PIC1_MASK_3__INTR_MASK_3__SHIFT 0x00000003 -#define MP1_PIC1_MASK_3__INTR_MASK_4__SHIFT 0x00000004 -#define MP1_PIC1_MASK_3__INTR_MASK_5__SHIFT 0x00000005 -#define MP1_PIC1_MASK_3__INTR_MASK_6__SHIFT 0x00000006 -#define MP1_PIC1_MASK_3__INTR_MASK_7__SHIFT 0x00000007 -#define MP1_PIC1_MASK_3__INTR_MASK_8__SHIFT 0x00000008 -#define MP1_PIC1_MASK_3__INTR_MASK_9__SHIFT 0x00000009 -#define MP1_PIC1_MASK_3__INTR_MASK_10__SHIFT 0x0000000a -#define MP1_PIC1_MASK_3__INTR_MASK_11__SHIFT 0x0000000b -#define MP1_PIC1_MASK_3__INTR_MASK_12__SHIFT 0x0000000c -#define MP1_PIC1_MASK_3__INTR_MASK_13__SHIFT 0x0000000d -#define MP1_PIC1_MASK_3__INTR_MASK_14__SHIFT 0x0000000e -#define MP1_PIC1_MASK_3__INTR_MASK_15__SHIFT 0x0000000f -#define MP1_PIC1_MASK_3__INTR_MASK_16__SHIFT 0x00000010 -#define MP1_PIC1_MASK_3__INTR_MASK_17__SHIFT 0x00000011 -#define MP1_PIC1_MASK_3__INTR_MASK_18__SHIFT 0x00000012 -#define MP1_PIC1_MASK_3__INTR_MASK_19__SHIFT 0x00000013 -#define MP1_PIC1_MASK_3__INTR_MASK_20__SHIFT 0x00000014 -#define MP1_PIC1_MASK_3__INTR_MASK_21__SHIFT 0x00000015 -#define MP1_PIC1_MASK_3__INTR_MASK_22__SHIFT 0x00000016 -#define MP1_PIC1_MASK_3__INTR_MASK_23__SHIFT 0x00000017 -#define MP1_PIC1_MASK_3__INTR_MASK_24__SHIFT 0x00000018 -#define MP1_PIC1_MASK_3__INTR_MASK_25__SHIFT 0x00000019 -#define MP1_PIC1_MASK_3__INTR_MASK_26__SHIFT 0x0000001a -#define MP1_PIC1_MASK_3__INTR_MASK_27__SHIFT 0x0000001b -#define MP1_PIC1_MASK_3__INTR_MASK_28__SHIFT 0x0000001c -#define MP1_PIC1_MASK_3__INTR_MASK_29__SHIFT 0x0000001d -#define MP1_PIC1_MASK_3__INTR_MASK_30__SHIFT 0x0000001e -#define MP1_PIC1_MASK_3__INTR_MASK_31__SHIFT 0x0000001f - -// MP1_PIC1_LEVEL_0 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_LEVEL_0__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_LEVEL_1 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_LEVEL_1__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_LEVEL_2 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_LEVEL_2__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_LEVEL_3 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_LEVEL_3__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_EDGE_0 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_EDGE_0__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_EDGE_1 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_EDGE_1__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_EDGE_2 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_EDGE_2__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_EDGE_3 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_0__SHIFT 0x00000000 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_1__SHIFT 0x00000001 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_2__SHIFT 0x00000002 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_3__SHIFT 0x00000003 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_4__SHIFT 0x00000004 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_5__SHIFT 0x00000005 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_6__SHIFT 0x00000006 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_7__SHIFT 0x00000007 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_8__SHIFT 0x00000008 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_9__SHIFT 0x00000009 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_10__SHIFT 0x0000000a -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_11__SHIFT 0x0000000b -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_12__SHIFT 0x0000000c -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_13__SHIFT 0x0000000d -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_14__SHIFT 0x0000000e -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_15__SHIFT 0x0000000f -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_16__SHIFT 0x00000010 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_17__SHIFT 0x00000011 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_18__SHIFT 0x00000012 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_19__SHIFT 0x00000013 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_20__SHIFT 0x00000014 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_21__SHIFT 0x00000015 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_22__SHIFT 0x00000016 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_23__SHIFT 0x00000017 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_24__SHIFT 0x00000018 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_25__SHIFT 0x00000019 -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_26__SHIFT 0x0000001a -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_27__SHIFT 0x0000001b -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_28__SHIFT 0x0000001c -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_29__SHIFT 0x0000001d -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_30__SHIFT 0x0000001e -#define MP1_PIC1_EDGE_3__INTR_TRIGGER_31__SHIFT 0x0000001f - -// MP1_PIC1_PRIORITY_0 -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_0__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_1 -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_1__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_2 -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_2__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_3 -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_3__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_4 -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_4__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_5 -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_5__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_6 -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_6__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_7 -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_7__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_8 -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_8__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_9 -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_9__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_10 -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_10__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_11 -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_11__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_12 -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_12__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_13 -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_13__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_14 -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_14__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_15 -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_15__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_16 -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_16__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_17 -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_17__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_18 -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_18__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_19 -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_19__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_20 -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_20__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_21 -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_21__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_22 -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_22__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_23 -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_23__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_24 -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_24__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_25 -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_25__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_26 -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_26__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_27 -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_27__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_28 -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_28__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_29 -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_29__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_30 -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_30__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_PRIORITY_31 -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_0__SHIFT 0x00000000 -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_1__SHIFT 0x00000008 -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_2__SHIFT 0x00000010 -#define MP1_PIC1_PRIORITY_31__INTR_PRIORITY_3__SHIFT 0x00000018 - -// MP1_PIC1_STATUS_0 -#define MP1_PIC1_STATUS_0__INTR_FLAG_0__SHIFT 0x00000000 -#define MP1_PIC1_STATUS_0__INTR_FLAG_1__SHIFT 0x00000001 -#define MP1_PIC1_STATUS_0__INTR_FLAG_2__SHIFT 0x00000002 -#define MP1_PIC1_STATUS_0__INTR_FLAG_3__SHIFT 0x00000003 -#define MP1_PIC1_STATUS_0__INTR_FLAG_4__SHIFT 0x00000004 -#define MP1_PIC1_STATUS_0__INTR_FLAG_5__SHIFT 0x00000005 -#define MP1_PIC1_STATUS_0__INTR_FLAG_6__SHIFT 0x00000006 -#define MP1_PIC1_STATUS_0__INTR_FLAG_7__SHIFT 0x00000007 -#define MP1_PIC1_STATUS_0__INTR_FLAG_8__SHIFT 0x00000008 -#define MP1_PIC1_STATUS_0__INTR_FLAG_9__SHIFT 0x00000009 -#define MP1_PIC1_STATUS_0__INTR_FLAG_10__SHIFT 0x0000000a -#define MP1_PIC1_STATUS_0__INTR_FLAG_11__SHIFT 0x0000000b -#define MP1_PIC1_STATUS_0__INTR_FLAG_12__SHIFT 0x0000000c -#define MP1_PIC1_STATUS_0__INTR_FLAG_13__SHIFT 0x0000000d -#define MP1_PIC1_STATUS_0__INTR_FLAG_14__SHIFT 0x0000000e -#define MP1_PIC1_STATUS_0__INTR_FLAG_15__SHIFT 0x0000000f -#define MP1_PIC1_STATUS_0__INTR_FLAG_16__SHIFT 0x00000010 -#define MP1_PIC1_STATUS_0__INTR_FLAG_17__SHIFT 0x00000011 -#define MP1_PIC1_STATUS_0__INTR_FLAG_18__SHIFT 0x00000012 -#define MP1_PIC1_STATUS_0__INTR_FLAG_19__SHIFT 0x00000013 -#define MP1_PIC1_STATUS_0__INTR_FLAG_20__SHIFT 0x00000014 -#define MP1_PIC1_STATUS_0__INTR_FLAG_21__SHIFT 0x00000015 -#define MP1_PIC1_STATUS_0__INTR_FLAG_22__SHIFT 0x00000016 -#define MP1_PIC1_STATUS_0__INTR_FLAG_23__SHIFT 0x00000017 -#define MP1_PIC1_STATUS_0__INTR_FLAG_24__SHIFT 0x00000018 -#define MP1_PIC1_STATUS_0__INTR_FLAG_25__SHIFT 0x00000019 -#define MP1_PIC1_STATUS_0__INTR_FLAG_26__SHIFT 0x0000001a -#define MP1_PIC1_STATUS_0__INTR_FLAG_27__SHIFT 0x0000001b -#define MP1_PIC1_STATUS_0__INTR_FLAG_28__SHIFT 0x0000001c -#define MP1_PIC1_STATUS_0__INTR_FLAG_29__SHIFT 0x0000001d -#define MP1_PIC1_STATUS_0__INTR_FLAG_30__SHIFT 0x0000001e -#define MP1_PIC1_STATUS_0__INTR_FLAG_31__SHIFT 0x0000001f - -// MP1_PIC1_STATUS_1 -#define MP1_PIC1_STATUS_1__INTR_FLAG_0__SHIFT 0x00000000 -#define MP1_PIC1_STATUS_1__INTR_FLAG_1__SHIFT 0x00000001 -#define MP1_PIC1_STATUS_1__INTR_FLAG_2__SHIFT 0x00000002 -#define MP1_PIC1_STATUS_1__INTR_FLAG_3__SHIFT 0x00000003 -#define MP1_PIC1_STATUS_1__INTR_FLAG_4__SHIFT 0x00000004 -#define MP1_PIC1_STATUS_1__INTR_FLAG_5__SHIFT 0x00000005 -#define MP1_PIC1_STATUS_1__INTR_FLAG_6__SHIFT 0x00000006 -#define MP1_PIC1_STATUS_1__INTR_FLAG_7__SHIFT 0x00000007 -#define MP1_PIC1_STATUS_1__INTR_FLAG_8__SHIFT 0x00000008 -#define MP1_PIC1_STATUS_1__INTR_FLAG_9__SHIFT 0x00000009 -#define MP1_PIC1_STATUS_1__INTR_FLAG_10__SHIFT 0x0000000a -#define MP1_PIC1_STATUS_1__INTR_FLAG_11__SHIFT 0x0000000b -#define MP1_PIC1_STATUS_1__INTR_FLAG_12__SHIFT 0x0000000c -#define MP1_PIC1_STATUS_1__INTR_FLAG_13__SHIFT 0x0000000d -#define MP1_PIC1_STATUS_1__INTR_FLAG_14__SHIFT 0x0000000e -#define MP1_PIC1_STATUS_1__INTR_FLAG_15__SHIFT 0x0000000f -#define MP1_PIC1_STATUS_1__INTR_FLAG_16__SHIFT 0x00000010 -#define MP1_PIC1_STATUS_1__INTR_FLAG_17__SHIFT 0x00000011 -#define MP1_PIC1_STATUS_1__INTR_FLAG_18__SHIFT 0x00000012 -#define MP1_PIC1_STATUS_1__INTR_FLAG_19__SHIFT 0x00000013 -#define MP1_PIC1_STATUS_1__INTR_FLAG_20__SHIFT 0x00000014 -#define MP1_PIC1_STATUS_1__INTR_FLAG_21__SHIFT 0x00000015 -#define MP1_PIC1_STATUS_1__INTR_FLAG_22__SHIFT 0x00000016 -#define MP1_PIC1_STATUS_1__INTR_FLAG_23__SHIFT 0x00000017 -#define MP1_PIC1_STATUS_1__INTR_FLAG_24__SHIFT 0x00000018 -#define MP1_PIC1_STATUS_1__INTR_FLAG_25__SHIFT 0x00000019 -#define MP1_PIC1_STATUS_1__INTR_FLAG_26__SHIFT 0x0000001a -#define MP1_PIC1_STATUS_1__INTR_FLAG_27__SHIFT 0x0000001b -#define MP1_PIC1_STATUS_1__INTR_FLAG_28__SHIFT 0x0000001c -#define MP1_PIC1_STATUS_1__INTR_FLAG_29__SHIFT 0x0000001d -#define MP1_PIC1_STATUS_1__INTR_FLAG_30__SHIFT 0x0000001e -#define MP1_PIC1_STATUS_1__INTR_FLAG_31__SHIFT 0x0000001f - -// MP1_PIC1_STATUS_2 -#define MP1_PIC1_STATUS_2__INTR_FLAG_0__SHIFT 0x00000000 -#define MP1_PIC1_STATUS_2__INTR_FLAG_1__SHIFT 0x00000001 -#define MP1_PIC1_STATUS_2__INTR_FLAG_2__SHIFT 0x00000002 -#define MP1_PIC1_STATUS_2__INTR_FLAG_3__SHIFT 0x00000003 -#define MP1_PIC1_STATUS_2__INTR_FLAG_4__SHIFT 0x00000004 -#define MP1_PIC1_STATUS_2__INTR_FLAG_5__SHIFT 0x00000005 -#define MP1_PIC1_STATUS_2__INTR_FLAG_6__SHIFT 0x00000006 -#define MP1_PIC1_STATUS_2__INTR_FLAG_7__SHIFT 0x00000007 -#define MP1_PIC1_STATUS_2__INTR_FLAG_8__SHIFT 0x00000008 -#define MP1_PIC1_STATUS_2__INTR_FLAG_9__SHIFT 0x00000009 -#define MP1_PIC1_STATUS_2__INTR_FLAG_10__SHIFT 0x0000000a -#define MP1_PIC1_STATUS_2__INTR_FLAG_11__SHIFT 0x0000000b -#define MP1_PIC1_STATUS_2__INTR_FLAG_12__SHIFT 0x0000000c -#define MP1_PIC1_STATUS_2__INTR_FLAG_13__SHIFT 0x0000000d -#define MP1_PIC1_STATUS_2__INTR_FLAG_14__SHIFT 0x0000000e -#define MP1_PIC1_STATUS_2__INTR_FLAG_15__SHIFT 0x0000000f -#define MP1_PIC1_STATUS_2__INTR_FLAG_16__SHIFT 0x00000010 -#define MP1_PIC1_STATUS_2__INTR_FLAG_17__SHIFT 0x00000011 -#define MP1_PIC1_STATUS_2__INTR_FLAG_18__SHIFT 0x00000012 -#define MP1_PIC1_STATUS_2__INTR_FLAG_19__SHIFT 0x00000013 -#define MP1_PIC1_STATUS_2__INTR_FLAG_20__SHIFT 0x00000014 -#define MP1_PIC1_STATUS_2__INTR_FLAG_21__SHIFT 0x00000015 -#define MP1_PIC1_STATUS_2__INTR_FLAG_22__SHIFT 0x00000016 -#define MP1_PIC1_STATUS_2__INTR_FLAG_23__SHIFT 0x00000017 -#define MP1_PIC1_STATUS_2__INTR_FLAG_24__SHIFT 0x00000018 -#define MP1_PIC1_STATUS_2__INTR_FLAG_25__SHIFT 0x00000019 -#define MP1_PIC1_STATUS_2__INTR_FLAG_26__SHIFT 0x0000001a -#define MP1_PIC1_STATUS_2__INTR_FLAG_27__SHIFT 0x0000001b -#define MP1_PIC1_STATUS_2__INTR_FLAG_28__SHIFT 0x0000001c -#define MP1_PIC1_STATUS_2__INTR_FLAG_29__SHIFT 0x0000001d -#define MP1_PIC1_STATUS_2__INTR_FLAG_30__SHIFT 0x0000001e -#define MP1_PIC1_STATUS_2__INTR_FLAG_31__SHIFT 0x0000001f - -// MP1_PIC1_STATUS_3 -#define MP1_PIC1_STATUS_3__INTR_FLAG_0__SHIFT 0x00000000 -#define MP1_PIC1_STATUS_3__INTR_FLAG_1__SHIFT 0x00000001 -#define MP1_PIC1_STATUS_3__INTR_FLAG_2__SHIFT 0x00000002 -#define MP1_PIC1_STATUS_3__INTR_FLAG_3__SHIFT 0x00000003 -#define MP1_PIC1_STATUS_3__INTR_FLAG_4__SHIFT 0x00000004 -#define MP1_PIC1_STATUS_3__INTR_FLAG_5__SHIFT 0x00000005 -#define MP1_PIC1_STATUS_3__INTR_FLAG_6__SHIFT 0x00000006 -#define MP1_PIC1_STATUS_3__INTR_FLAG_7__SHIFT 0x00000007 -#define MP1_PIC1_STATUS_3__INTR_FLAG_8__SHIFT 0x00000008 -#define MP1_PIC1_STATUS_3__INTR_FLAG_9__SHIFT 0x00000009 -#define MP1_PIC1_STATUS_3__INTR_FLAG_10__SHIFT 0x0000000a -#define MP1_PIC1_STATUS_3__INTR_FLAG_11__SHIFT 0x0000000b -#define MP1_PIC1_STATUS_3__INTR_FLAG_12__SHIFT 0x0000000c -#define MP1_PIC1_STATUS_3__INTR_FLAG_13__SHIFT 0x0000000d -#define MP1_PIC1_STATUS_3__INTR_FLAG_14__SHIFT 0x0000000e -#define MP1_PIC1_STATUS_3__INTR_FLAG_15__SHIFT 0x0000000f -#define MP1_PIC1_STATUS_3__INTR_FLAG_16__SHIFT 0x00000010 -#define MP1_PIC1_STATUS_3__INTR_FLAG_17__SHIFT 0x00000011 -#define MP1_PIC1_STATUS_3__INTR_FLAG_18__SHIFT 0x00000012 -#define MP1_PIC1_STATUS_3__INTR_FLAG_19__SHIFT 0x00000013 -#define MP1_PIC1_STATUS_3__INTR_FLAG_20__SHIFT 0x00000014 -#define MP1_PIC1_STATUS_3__INTR_FLAG_21__SHIFT 0x00000015 -#define MP1_PIC1_STATUS_3__INTR_FLAG_22__SHIFT 0x00000016 -#define MP1_PIC1_STATUS_3__INTR_FLAG_23__SHIFT 0x00000017 -#define MP1_PIC1_STATUS_3__INTR_FLAG_24__SHIFT 0x00000018 -#define MP1_PIC1_STATUS_3__INTR_FLAG_25__SHIFT 0x00000019 -#define MP1_PIC1_STATUS_3__INTR_FLAG_26__SHIFT 0x0000001a -#define MP1_PIC1_STATUS_3__INTR_FLAG_27__SHIFT 0x0000001b -#define MP1_PIC1_STATUS_3__INTR_FLAG_28__SHIFT 0x0000001c -#define MP1_PIC1_STATUS_3__INTR_FLAG_29__SHIFT 0x0000001d -#define MP1_PIC1_STATUS_3__INTR_FLAG_30__SHIFT 0x0000001e -#define MP1_PIC1_STATUS_3__INTR_FLAG_31__SHIFT 0x0000001f - -// MP1_PIC1_INTR -#define MP1_PIC1_INTR__INTR_LINE__SHIFT 0x00000000 -#define MP1_PIC1_INTR__RESERVED__SHIFT 0x00000001 - -// MP1_PIC1_ID -#define MP1_PIC1_ID__INTR_ID__SHIFT 0x00000000 -#define MP1_PIC1_ID__RESERVED__SHIFT 0x00000008 - -// MP1_TIMER_0_CTRL0 -#define MP1_TIMER_0_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_0_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_0_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_1_CTRL0 -#define MP1_TIMER_1_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_1_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_1_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_2_CTRL0 -#define MP1_TIMER_2_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_2_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_2_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_2_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_3_CTRL0 -#define MP1_TIMER_3_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_3_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_3_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_3_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_4_CTRL0 -#define MP1_TIMER_4_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_4_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_4_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_4_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_5_CTRL0 -#define MP1_TIMER_5_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_5_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_5_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_5_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_6_CTRL0 -#define MP1_TIMER_6_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_6_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_6_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_6_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_7_CTRL0 -#define MP1_TIMER_7_CTRL0__START__SHIFT 0x00000000 -#define MP1_TIMER_7_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_TIMER_7_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_TIMER_7_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_TIMER_0_CTRL1 -#define MP1_TIMER_0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_0_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_1_CTRL1 -#define MP1_TIMER_1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_1_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_2_CTRL1 -#define MP1_TIMER_2_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_2_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_2_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_2_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_3_CTRL1 -#define MP1_TIMER_3_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_3_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_3_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_3_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_4_CTRL1 -#define MP1_TIMER_4_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_4_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_4_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_4_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_5_CTRL1 -#define MP1_TIMER_5_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_5_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_5_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_5_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_6_CTRL1 -#define MP1_TIMER_6_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_6_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_6_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_6_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_7_CTRL1 -#define MP1_TIMER_7_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_TIMER_7_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_TIMER_7_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_TIMER_7_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_TIMER_0_CMP_AUTOINC -#define MP1_TIMER_0_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_0_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_1_CMP_AUTOINC -#define MP1_TIMER_1_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_1_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_2_CMP_AUTOINC -#define MP1_TIMER_2_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_2_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_3_CMP_AUTOINC -#define MP1_TIMER_3_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_3_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_4_CMP_AUTOINC -#define MP1_TIMER_4_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_4_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_5_CMP_AUTOINC -#define MP1_TIMER_5_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_5_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_6_CMP_AUTOINC -#define MP1_TIMER_6_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_6_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_7_CMP_AUTOINC -#define MP1_TIMER_7_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_TIMER_7_CMP_AUTOINC__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_0_INTEN -#define MP1_TIMER_0_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_0_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_1_INTEN -#define MP1_TIMER_1_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_1_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_2_INTEN -#define MP1_TIMER_2_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_2_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_3_INTEN -#define MP1_TIMER_3_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_3_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_4_INTEN -#define MP1_TIMER_4_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_4_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_5_INTEN -#define MP1_TIMER_5_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_5_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_6_INTEN -#define MP1_TIMER_6_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_6_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_7_INTEN -#define MP1_TIMER_7_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_TIMER_7_INTEN__RESERVED__SHIFT 0x00000004 - -// MP1_TIMER_OCMP_0_0 -#define MP1_TIMER_OCMP_0_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_1_0 -#define MP1_TIMER_OCMP_1_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_2_0 -#define MP1_TIMER_OCMP_2_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_3_0 -#define MP1_TIMER_OCMP_3_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_4_0 -#define MP1_TIMER_OCMP_4_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_5_0 -#define MP1_TIMER_OCMP_5_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_6_0 -#define MP1_TIMER_OCMP_6_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_7_0 -#define MP1_TIMER_OCMP_7_0__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_0_1 -#define MP1_TIMER_OCMP_0_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_1_1 -#define MP1_TIMER_OCMP_1_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_2_1 -#define MP1_TIMER_OCMP_2_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_3_1 -#define MP1_TIMER_OCMP_3_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_4_1 -#define MP1_TIMER_OCMP_4_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_5_1 -#define MP1_TIMER_OCMP_5_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_6_1 -#define MP1_TIMER_OCMP_6_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_7_1 -#define MP1_TIMER_OCMP_7_1__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_0_2 -#define MP1_TIMER_OCMP_0_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_1_2 -#define MP1_TIMER_OCMP_1_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_2_2 -#define MP1_TIMER_OCMP_2_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_3_2 -#define MP1_TIMER_OCMP_3_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_4_2 -#define MP1_TIMER_OCMP_4_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_5_2 -#define MP1_TIMER_OCMP_5_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_6_2 -#define MP1_TIMER_OCMP_6_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_7_2 -#define MP1_TIMER_OCMP_7_2__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_0_3 -#define MP1_TIMER_OCMP_0_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_1_3 -#define MP1_TIMER_OCMP_1_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_2_3 -#define MP1_TIMER_OCMP_2_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_3_3 -#define MP1_TIMER_OCMP_3_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_4_3 -#define MP1_TIMER_OCMP_4_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_5_3 -#define MP1_TIMER_OCMP_5_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_6_3 -#define MP1_TIMER_OCMP_6_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_OCMP_7_3 -#define MP1_TIMER_OCMP_7_3__OCMP__SHIFT 0x00000000 - -// MP1_TIMER_0_CNT -#define MP1_TIMER_0_CNT__COUNT__SHIFT 0x00000000 - -// MP1_TIMER_1_CNT -#define MP1_TIMER_1_CNT__COUNT__SHIFT 0x00000000 - -// MP1_TIMER_2_CNT -#define MP1_TIMER_2_CNT__COUNT__SHIFT 0x00000000 - -// MP1_TIMER_3_CNT -#define MP1_TIMER_3_CNT__COUNT__SHIFT 0x00000000 - -// MP1_TIMER_4_CNT -#define MP1_TIMER_4_CNT__COUNT__SHIFT 0x00000000 - -// MP1_TIMER_5_CNT -#define MP1_TIMER_5_CNT__COUNT__SHIFT 0x00000000 - -// MP1_TIMER_6_CNT -#define MP1_TIMER_6_CNT__COUNT__SHIFT 0x00000000 - -// MP1_TIMER_7_CNT -#define MP1_TIMER_7_CNT__COUNT__SHIFT 0x00000000 - -// MP1_C2PMSG_ATTR_0 -#define MP1_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x00000000 - -// MP1_C2PMSG_ATTR_1 -#define MP1_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x00000000 - -// MP1_C2PMSG_ATTR_2 -#define MP1_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x00000000 - -// MP1_C2PMSG_ATTR_3 -#define MP1_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x00000000 - -// MP1_C2PMSG_ATTR_4 -#define MP1_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x00000000 - -// MP1_C2PMSG_ATTR_5 -#define MP1_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x00000000 - -// MP1_P2CMSG_ATTR -#define MP1_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x00000000 - -// MP1_S2PMSG_ATTR -#define MP1_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x00000000 - -// MP1_P2SMSG_ATTR -#define MP1_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x00000000 - -// MP1_SMN_SRBMTMR_0_CTRL0 -#define MP1_SMN_SRBMTMR_0_CTRL0__START__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_0_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_SMN_SRBMTMR_0_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_SMN_SRBMTMR_0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_SMN_SRBMTMR_1_CTRL0 -#define MP1_SMN_SRBMTMR_1_CTRL0__START__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_1_CTRL0__CLEAR__SHIFT 0x00000008 -#define MP1_SMN_SRBMTMR_1_CTRL0__DEC__SHIFT 0x00000010 -#define MP1_SMN_SRBMTMR_1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x00000018 - -// MP1_SMN_SRBMTMR_0_CTRL1 -#define MP1_SMN_SRBMTMR_0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_SMN_SRBMTMR_0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_SMN_SRBMTMR_0_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_SMN_SRBMTMR_1_CTRL1 -#define MP1_SMN_SRBMTMR_1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x00000008 -#define MP1_SMN_SRBMTMR_1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x00000010 -#define MP1_SMN_SRBMTMR_1_CTRL1__RESERVED__SHIFT 0x00000018 - -// MP1_SMN_SRBMTMR_0_CMP_AUTOINC -#define MP1_SMN_SRBMTMR_0_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_0_CMP_AUTOINC__RESERVED_RW__SHIFT 0x00000001 -#define MP1_SMN_SRBMTMR_0_CMP_AUTOINC__RESERVED__SHIFT 0x00000002 - -// MP1_SMN_SRBMTMR_1_CMP_AUTOINC -#define MP1_SMN_SRBMTMR_1_CMP_AUTOINC__AUTOINC__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_1_CMP_AUTOINC__RESERVED_RW__SHIFT 0x00000001 -#define MP1_SMN_SRBMTMR_1_CMP_AUTOINC__RESERVED__SHIFT 0x00000002 - -// MP1_SMN_SRBMTMR_0_INTEN -#define MP1_SMN_SRBMTMR_0_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_0_INTEN__RESERVED__SHIFT 0x00000001 - -// MP1_SMN_SRBMTMR_1_INTEN -#define MP1_SMN_SRBMTMR_1_INTEN__INTEN__SHIFT 0x00000000 -#define MP1_SMN_SRBMTMR_1_INTEN__RESERVED__SHIFT 0x00000001 - -// MP1_SMN_SRBMTMR_OCMP_0_0 -#define MP1_SMN_SRBMTMR_OCMP_0_0__OCMP__SHIFT 0x00000000 - -// MP1_SMN_SRBMTMR_OCMP_1_0 -#define MP1_SMN_SRBMTMR_OCMP_1_0__OCMP__SHIFT 0x00000000 - -// MP1_SMN_SRBMTMR_0_CNT -#define MP1_SMN_SRBMTMR_0_CNT__COUNT__SHIFT 0x00000000 - -// MP1_SMN_SRBMTMR_1_CNT -#define MP1_SMN_SRBMTMR_1_CNT__COUNT__SHIFT 0x00000000 - -// MP1_SMN_ACP2MP_RESP -#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_DC2MP_RESP -#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_UVD2MP_RESP -#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_VCE2MP_RESP -#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_RLC2MP_RESP -#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_32 -#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_33 -#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_34 -#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_35 -#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_36 -#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_37 -#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_38 -#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_39 -#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_40 -#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_41 -#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_42 -#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_43 -#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_44 -#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_45 -#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_46 -#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_47 -#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_48 -#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_49 -#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_50 -#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_51 -#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_52 -#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_53 -#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_54 -#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_55 -#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_56 -#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_57 -#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_58 -#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_59 -#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_60 -#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_61 -#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_62 -#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_63 -#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_64 -#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_65 -#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_66 -#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_67 -#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_68 -#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_69 -#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_70 -#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_71 -#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_72 -#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_73 -#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_74 -#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_75 -#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_76 -#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_77 -#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_78 -#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_79 -#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_80 -#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_81 -#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_82 -#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_83 -#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_84 -#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_85 -#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_86 -#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_87 -#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_88 -#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_89 -#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_90 -#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_91 -#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_92 -#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_93 -#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_94 -#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_C2PMSG_95 -#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x00000000 - -// MP1_SMN_IH_MP0SW_INT -#define MP1_SMN_IH_MP0SW_INT__VALID__SHIFT 0x00000000 -#define MP1_SMN_IH_MP0SW_INT__ID__SHIFT 0x00000001 - -// MP1_SMN_IH_MP1SW_INT -#define MP1_SMN_IH_MP1SW_INT__VALID__SHIFT 0x00000000 -#define MP1_SMN_IH_MP1SW_INT__ID__SHIFT 0x00000001 - -// MP1_SMN_IH_SW_INT_CTRL -#define MP1_SMN_IH_SW_INT_CTRL__MAX_CREDIT_VALUE__SHIFT 0x00000000 -#define MP1_SMN_IH_SW_INT_CTRL__MP0_SW_TRIG_MASK__SHIFT 0x00000005 -#define MP1_SMN_IH_SW_INT_CTRL__MP0_SW_INT_ACK__SHIFT 0x00000006 -#define MP1_SMN_IH_SW_INT_CTRL__MP1_SW_TRIG_MASK__SHIFT 0x00000007 -#define MP1_SMN_IH_SW_INT_CTRL__MP1_SW_INT_ACK__SHIFT 0x00000008 - -// MP1_SMN_IH_DISPTMR0_INT_CTRL -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__STATUS__SHIFT 0x00000000 -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__UNMASK__SHIFT 0x00000001 -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__TYPE__SHIFT 0x00000002 -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__ACK__SHIFT 0x00000003 -#define MP1_SMN_IH_DISPTMR0_INT_CTRL__MASK__SHIFT 0x00000004 - -// MP1_SMN_IH_DISPTMR1_INT_CTRL -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__STATUS__SHIFT 0x00000000 -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__UNMASK__SHIFT 0x00000001 -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__TYPE__SHIFT 0x00000002 -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__ACK__SHIFT 0x00000003 -#define MP1_SMN_IH_DISPTMR1_INT_CTRL__MASK__SHIFT 0x00000004 - -// MP1_SMN_FPS_CNT -#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x00000000 - -// MP1_RSMU_PUB_RSMU_HCID -#define MP1_RSMU_PUB_RSMU_HCID__HwRev__SHIFT 0x00000000 -#define MP1_RSMU_PUB_RSMU_HCID__HwMinVer__SHIFT 0x00000006 -#define MP1_RSMU_PUB_RSMU_HCID__HwMajVer__SHIFT 0x0000000d -#define MP1_RSMU_PUB_RSMU_HCID__HwID__SHIFT 0x00000014 - -// MP1_RSMU_PUB_RSMU_SIID -#define MP1_RSMU_PUB_RSMU_SIID__SwIfRev__SHIFT 0x00000000 -#define MP1_RSMU_PUB_RSMU_SIID__SwIfMinVer__SHIFT 0x00000006 -#define MP1_RSMU_PUB_RSMU_SIID__SwIfMajVer__SHIFT 0x0000000d -#define MP1_RSMU_PUB_RSMU_SIID__SwIfID__SHIFT 0x00000014 - -// MP1_PMI_0_START -#define MP1_PMI_0_START__ADDR__SHIFT 0x00000000 -#define MP1_PMI_0_START__ENABLE__SHIFT 0x0000001f - -// MP1_PMI_0_FIFO -#define MP1_PMI_0_FIFO__DEPTH__SHIFT 0x00000000 - -// MP1_PMI_0_STATUS -#define MP1_PMI_0_STATUS__FULL__SHIFT 0x00000000 -#define MP1_PMI_0_STATUS__EMPTY__SHIFT 0x00000001 - -// MP1_PMI_0_READ_POINTER -#define MP1_PMI_0_READ_POINTER__CURRENT__SHIFT 0x00000000 - -// MP1_PMI_0_WRITE_POINTER -#define MP1_PMI_0_WRITE_POINTER__CURRENT__SHIFT 0x00000000 - -// MP1_PMI_1_START -#define MP1_PMI_1_START__ADDR__SHIFT 0x00000000 -#define MP1_PMI_1_START__ENABLE__SHIFT 0x0000001f - -// MP1_PMI_1_FIFO -#define MP1_PMI_1_FIFO__DEPTH__SHIFT 0x00000000 - -// MP1_PMI_1_STATUS -#define MP1_PMI_1_STATUS__FULL__SHIFT 0x00000000 -#define MP1_PMI_1_STATUS__EMPTY__SHIFT 0x00000001 - -// MP1_PMI_1_READ_POINTER -#define MP1_PMI_1_READ_POINTER__CURRENT__SHIFT 0x00000000 - -// MP1_PMI_1_WRITE_POINTER -#define MP1_PMI_1_WRITE_POINTER__CURRENT__SHIFT 0x00000000 - -// MP1_PMI_2_START -#define MP1_PMI_2_START__ADDR__SHIFT 0x00000000 -#define MP1_PMI_2_START__ENABLE__SHIFT 0x0000001f - -// MP1_PMI_2_FIFO -#define MP1_PMI_2_FIFO__DEPTH__SHIFT 0x00000000 - -// MP1_PMI_2_STATUS -#define MP1_PMI_2_STATUS__FULL__SHIFT 0x00000000 -#define MP1_PMI_2_STATUS__EMPTY__SHIFT 0x00000001 - -// MP1_PMI_2_READ_POINTER -#define MP1_PMI_2_READ_POINTER__CURRENT__SHIFT 0x00000000 - -// MP1_PMI_2_WRITE_POINTER -#define MP1_PMI_2_WRITE_POINTER__CURRENT__SHIFT 0x00000000 - -// MP1_PMI_OUT_CONFIG -#define MP1_PMI_OUT_CONFIG__PMI0_OUT_SEL__SHIFT 0x00000000 -#define MP1_PMI_OUT_CONFIG__PMI1_OUT_SEL__SHIFT 0x00000002 -#define MP1_PMI_OUT_CONFIG__PMI2_OUT_SEL__SHIFT 0x00000004 - -// MP1_PMI_RELOAD -#define MP1_PMI_RELOAD__PMI_PARAMETERS__SHIFT 0x00000000 - -// MP1_PMI_INTERRUPT_CONTROL -#define MP1_PMI_INTERRUPT_CONTROL__PMI_PENDING__SHIFT 0x00000000 -#define MP1_PMI_INTERRUPT_CONTROL__PMI_INTERRUPT_MASK__SHIFT 0x00000003 - -// MP1_MMU_SRAM_ACC_VIOLATION_LOG_ADDR -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_ADDR__ADDRESS__SHIFT 0x00000000 - -// MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_UNSECURE_BAR__SHIFT 0x00000001 -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_OP__SHIFT 0x00000003 -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE__SHIFT 0x00000004 -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_PERMISSION__SHIFT 0x00000006 -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_UNIT_ID__SHIFT 0x00000008 -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_AXI_INIT_ID__SHIFT 0x0000000e -#define MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x00000016 - -// MP1_MMU_MISC_CNTL -#define MP1_MMU_MISC_CNTL__ALLOW_UNPRIVILIGED_REG_ACC__SHIFT 0x00000000 -#define MP1_MMU_MISC_CNTL__RETURN_ERR_ON_VIOLATED_READ__SHIFT 0x00000001 -#define MP1_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_PSRAM__SHIFT 0x00000002 -#define MP1_MMU_MISC_CNTL__ENABLE_MEM_CHECKS_CPU__SHIFT 0x00000003 -#define MP1_MMU_MISC_CNTL__RESERVED2__SHIFT 0x00000004 -#define MP1_MMU_MISC_CNTL__MEM_SLEEP_TIMEOUT__SHIFT 0x00000008 -#define MP1_MMU_MISC_CNTL__CLK_GATE_EN__SHIFT 0x00000010 -#define MP1_MMU_MISC_CNTL__CLK_GATE_OVERRIDE__SHIFT 0x00000011 -#define MP1_MMU_MISC_CNTL__CLK_GATE_TIMEOUT__SHIFT 0x00000012 -#define MP1_MMU_MISC_CNTL__REGCLK_STATUS__SHIFT 0x00000016 -#define MP1_MMU_MISC_CNTL__SYSCLK_STATUS__SHIFT 0x00000017 -#define MP1_MMU_MISC_CNTL__MEM_DEEP_SLEEP_EN__SHIFT 0x00000018 -#define MP1_MMU_MISC_CNTL__MEM_DEEP_SLEEP_STATUS__SHIFT 0x00000019 -#define MP1_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0000001a -#define MP1_MMU_MISC_CNTL__MEM_LIGHT_SLEEP_STATUS__SHIFT 0x0000001b -#define MP1_MMU_MISC_CNTL__MEM_PG_DLY__SHIFT 0x0000001c - -// MP1_MMU_ACCESS_ERR_LOG -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_BLOCK__SHIFT 0x00000001 -#define MP1_MMU_ACCESS_ERR_LOG__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x00000003 -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_UNIT_ID__SHIFT 0x00000008 -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_INIT_ID__SHIFT 0x0000000e -#define MP1_MMU_ACCESS_ERR_LOG__AXI_ACC_VIOLATION_AXI_PROT__SHIFT 0x00000016 - -// MP1_MMU_SRAM_UNSECURE_BAR -#define MP1_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR__SHIFT 0x00000000 -#define MP1_MMU_SRAM_UNSECURE_BAR__SRAM_UNSECURE_BAR_LOCK__SHIFT 0x00000019 - -// MP1_MMU_SCRATCH_0 -#define MP1_MMU_SCRATCH_0__RESERVED__SHIFT 0x00000000 - -// MP1_MMU_SCRATCH_1 -#define MP1_MMU_SCRATCH_1__RESERVED__SHIFT 0x00000000 - -// MP1_MMU_SCRATCH_2 -#define MP1_MMU_SCRATCH_2__RESERVED__SHIFT 0x00000000 - -// MP1_MMU_SCRATCH_3 -#define MP1_MMU_SCRATCH_3__RESERVED__SHIFT 0x00000000 - -// MP1_MMU_SCRATCH_4 -#define MP1_MMU_SCRATCH_4__RESERVED__SHIFT 0x00000000 - -// MP1_MMU_SCRATCH_5 -#define MP1_MMU_SCRATCH_5__RESERVED__SHIFT 0x00000000 - -// MP1_MMU_SCRATCH_6 -#define MP1_MMU_SCRATCH_6__RESERVED__SHIFT 0x00000000 - -// MP1_MMU_SCRATCH_7 -#define MP1_MMU_SCRATCH_7__RESERVED__SHIFT 0x00000000 - -// MP1_MCA_ACCESS_CNTL -#define MP1_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_EN__SHIFT 0x00000000 -#define MP1_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_RD_WR_SEL__SHIFT 0x00000001 -#define MP1_MCA_ACCESS_CNTL__MCA_ACCESS_CNTL_EXT_ACCESS_REG_SEL__SHIFT 0x00000002 - -// MP1_MCA_ACCESS_WR_DATA -#define MP1_MCA_ACCESS_WR_DATA__MCA_ACCESS_WR_DATA__SHIFT 0x00000000 - -// MP1_MCA_ACCESS_RD_DATA -#define MP1_MCA_ACCESS_RD_DATA__MCA_ACCESS_RD_DATA__SHIFT 0x00000000 - -// MP1_PMI_0 -#define MP1_PMI_0__DATA__SHIFT 0x00000000 -#define MP1_PMI_0__AxId__SHIFT 0x00000010 - -// MP1_PMI_1 -#define MP1_PMI_1__DATA__SHIFT 0x00000000 -#define MP1_PMI_1__AxId__SHIFT 0x00000010 - -// MP1_PMI_2 -#define MP1_PMI_2__DATA__SHIFT 0x00000000 -#define MP1_PMI_2__AxId__SHIFT 0x00000010 - -// MP1_MMHUB_SOC_TLB0_1 -#define MP1_MMHUB_SOC_TLB0_1__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_2 -#define MP1_MMHUB_SOC_TLB0_2__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_3 -#define MP1_MMHUB_SOC_TLB0_3__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_4 -#define MP1_MMHUB_SOC_TLB0_4__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_5 -#define MP1_MMHUB_SOC_TLB0_5__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_6 -#define MP1_MMHUB_SOC_TLB0_6__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_7 -#define MP1_MMHUB_SOC_TLB0_7__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_8 -#define MP1_MMHUB_SOC_TLB0_8__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_9 -#define MP1_MMHUB_SOC_TLB0_9__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_10 -#define MP1_MMHUB_SOC_TLB0_10__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_11 -#define MP1_MMHUB_SOC_TLB0_11__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_12 -#define MP1_MMHUB_SOC_TLB0_12__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_13 -#define MP1_MMHUB_SOC_TLB0_13__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_14 -#define MP1_MMHUB_SOC_TLB0_14__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_15 -#define MP1_MMHUB_SOC_TLB0_15__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_16 -#define MP1_MMHUB_SOC_TLB0_16__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_17 -#define MP1_MMHUB_SOC_TLB0_17__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_18 -#define MP1_MMHUB_SOC_TLB0_18__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_19 -#define MP1_MMHUB_SOC_TLB0_19__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_20 -#define MP1_MMHUB_SOC_TLB0_20__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_21 -#define MP1_MMHUB_SOC_TLB0_21__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_22 -#define MP1_MMHUB_SOC_TLB0_22__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_23 -#define MP1_MMHUB_SOC_TLB0_23__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_24 -#define MP1_MMHUB_SOC_TLB0_24__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_25 -#define MP1_MMHUB_SOC_TLB0_25__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_26 -#define MP1_MMHUB_SOC_TLB0_26__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_27 -#define MP1_MMHUB_SOC_TLB0_27__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_28 -#define MP1_MMHUB_SOC_TLB0_28__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_29 -#define MP1_MMHUB_SOC_TLB0_29__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_30 -#define MP1_MMHUB_SOC_TLB0_30__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_31 -#define MP1_MMHUB_SOC_TLB0_31__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_32 -#define MP1_MMHUB_SOC_TLB0_32__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_33 -#define MP1_MMHUB_SOC_TLB0_33__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_34 -#define MP1_MMHUB_SOC_TLB0_34__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_35 -#define MP1_MMHUB_SOC_TLB0_35__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_36 -#define MP1_MMHUB_SOC_TLB0_36__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_37 -#define MP1_MMHUB_SOC_TLB0_37__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_38 -#define MP1_MMHUB_SOC_TLB0_38__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_39 -#define MP1_MMHUB_SOC_TLB0_39__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_40 -#define MP1_MMHUB_SOC_TLB0_40__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_41 -#define MP1_MMHUB_SOC_TLB0_41__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_42 -#define MP1_MMHUB_SOC_TLB0_42__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_43 -#define MP1_MMHUB_SOC_TLB0_43__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_44 -#define MP1_MMHUB_SOC_TLB0_44__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_45 -#define MP1_MMHUB_SOC_TLB0_45__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_46 -#define MP1_MMHUB_SOC_TLB0_46__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_47 -#define MP1_MMHUB_SOC_TLB0_47__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_48 -#define MP1_MMHUB_SOC_TLB0_48__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_49 -#define MP1_MMHUB_SOC_TLB0_49__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_50 -#define MP1_MMHUB_SOC_TLB0_50__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_51 -#define MP1_MMHUB_SOC_TLB0_51__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_52 -#define MP1_MMHUB_SOC_TLB0_52__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_53 -#define MP1_MMHUB_SOC_TLB0_53__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_54 -#define MP1_MMHUB_SOC_TLB0_54__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_55 -#define MP1_MMHUB_SOC_TLB0_55__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_56 -#define MP1_MMHUB_SOC_TLB0_56__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_57 -#define MP1_MMHUB_SOC_TLB0_57__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_58 -#define MP1_MMHUB_SOC_TLB0_58__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_59 -#define MP1_MMHUB_SOC_TLB0_59__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_60 -#define MP1_MMHUB_SOC_TLB0_60__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_61 -#define MP1_MMHUB_SOC_TLB0_61__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB0_62 -#define MP1_MMHUB_SOC_TLB0_62__SOC_ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB1_1 -#define MP1_MMHUB_SOC_TLB1_1__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_1__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_1__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_2 -#define MP1_MMHUB_SOC_TLB1_2__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_2__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_2__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_3 -#define MP1_MMHUB_SOC_TLB1_3__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_3__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_3__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_4 -#define MP1_MMHUB_SOC_TLB1_4__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_4__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_4__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_5 -#define MP1_MMHUB_SOC_TLB1_5__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_5__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_5__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_6 -#define MP1_MMHUB_SOC_TLB1_6__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_6__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_6__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_7 -#define MP1_MMHUB_SOC_TLB1_7__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_7__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_7__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_8 -#define MP1_MMHUB_SOC_TLB1_8__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_8__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_8__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_9 -#define MP1_MMHUB_SOC_TLB1_9__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_9__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_9__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_10 -#define MP1_MMHUB_SOC_TLB1_10__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_10__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_10__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_11 -#define MP1_MMHUB_SOC_TLB1_11__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_11__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_11__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_12 -#define MP1_MMHUB_SOC_TLB1_12__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_12__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_12__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_13 -#define MP1_MMHUB_SOC_TLB1_13__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_13__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_13__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_14 -#define MP1_MMHUB_SOC_TLB1_14__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_14__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_14__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_15 -#define MP1_MMHUB_SOC_TLB1_15__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_15__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_15__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_16 -#define MP1_MMHUB_SOC_TLB1_16__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_16__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_16__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_17 -#define MP1_MMHUB_SOC_TLB1_17__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_17__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_17__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_18 -#define MP1_MMHUB_SOC_TLB1_18__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_18__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_18__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_19 -#define MP1_MMHUB_SOC_TLB1_19__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_19__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_19__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_20 -#define MP1_MMHUB_SOC_TLB1_20__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_20__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_20__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_21 -#define MP1_MMHUB_SOC_TLB1_21__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_21__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_21__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_22 -#define MP1_MMHUB_SOC_TLB1_22__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_22__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_22__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_23 -#define MP1_MMHUB_SOC_TLB1_23__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_23__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_23__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_24 -#define MP1_MMHUB_SOC_TLB1_24__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_24__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_24__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_25 -#define MP1_MMHUB_SOC_TLB1_25__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_25__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_25__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_26 -#define MP1_MMHUB_SOC_TLB1_26__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_26__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_26__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_27 -#define MP1_MMHUB_SOC_TLB1_27__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_27__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_27__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_28 -#define MP1_MMHUB_SOC_TLB1_28__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_28__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_28__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_29 -#define MP1_MMHUB_SOC_TLB1_29__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_29__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_29__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_30 -#define MP1_MMHUB_SOC_TLB1_30__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_30__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_30__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_31 -#define MP1_MMHUB_SOC_TLB1_31__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_31__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_31__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_32 -#define MP1_MMHUB_SOC_TLB1_32__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_32__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_32__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_33 -#define MP1_MMHUB_SOC_TLB1_33__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_33__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_33__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_34 -#define MP1_MMHUB_SOC_TLB1_34__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_34__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_34__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_35 -#define MP1_MMHUB_SOC_TLB1_35__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_35__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_35__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_36 -#define MP1_MMHUB_SOC_TLB1_36__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_36__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_36__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_37 -#define MP1_MMHUB_SOC_TLB1_37__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_37__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_37__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_38 -#define MP1_MMHUB_SOC_TLB1_38__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_38__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_38__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_39 -#define MP1_MMHUB_SOC_TLB1_39__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_39__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_39__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_40 -#define MP1_MMHUB_SOC_TLB1_40__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_40__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_40__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_41 -#define MP1_MMHUB_SOC_TLB1_41__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_41__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_41__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_42 -#define MP1_MMHUB_SOC_TLB1_42__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_42__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_42__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_43 -#define MP1_MMHUB_SOC_TLB1_43__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_43__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_43__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_44 -#define MP1_MMHUB_SOC_TLB1_44__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_44__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_44__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_45 -#define MP1_MMHUB_SOC_TLB1_45__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_45__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_45__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_46 -#define MP1_MMHUB_SOC_TLB1_46__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_46__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_46__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_47 -#define MP1_MMHUB_SOC_TLB1_47__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_47__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_47__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_48 -#define MP1_MMHUB_SOC_TLB1_48__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_48__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_48__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_49 -#define MP1_MMHUB_SOC_TLB1_49__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_49__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_49__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_50 -#define MP1_MMHUB_SOC_TLB1_50__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_50__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_50__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_51 -#define MP1_MMHUB_SOC_TLB1_51__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_51__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_51__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_52 -#define MP1_MMHUB_SOC_TLB1_52__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_52__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_52__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_53 -#define MP1_MMHUB_SOC_TLB1_53__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_53__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_53__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_54 -#define MP1_MMHUB_SOC_TLB1_54__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_54__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_54__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_55 -#define MP1_MMHUB_SOC_TLB1_55__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_55__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_55__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_56 -#define MP1_MMHUB_SOC_TLB1_56__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_56__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_56__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_57 -#define MP1_MMHUB_SOC_TLB1_57__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_57__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_57__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_58 -#define MP1_MMHUB_SOC_TLB1_58__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_58__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_58__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_59 -#define MP1_MMHUB_SOC_TLB1_59__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_59__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_59__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_60 -#define MP1_MMHUB_SOC_TLB1_60__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_60__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_60__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_61 -#define MP1_MMHUB_SOC_TLB1_61__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_61__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_61__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB1_62 -#define MP1_MMHUB_SOC_TLB1_62__COHERENCE__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB1_62__SEG_SIZE__SHIFT 0x00000001 -#define MP1_MMHUB_SOC_TLB1_62__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_MMHUB_SOC_TLB2_1 -#define MP1_MMHUB_SOC_TLB2_1__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_2 -#define MP1_MMHUB_SOC_TLB2_2__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_3 -#define MP1_MMHUB_SOC_TLB2_3__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_4 -#define MP1_MMHUB_SOC_TLB2_4__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_5 -#define MP1_MMHUB_SOC_TLB2_5__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_6 -#define MP1_MMHUB_SOC_TLB2_6__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_7 -#define MP1_MMHUB_SOC_TLB2_7__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_8 -#define MP1_MMHUB_SOC_TLB2_8__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_9 -#define MP1_MMHUB_SOC_TLB2_9__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_10 -#define MP1_MMHUB_SOC_TLB2_10__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_11 -#define MP1_MMHUB_SOC_TLB2_11__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_12 -#define MP1_MMHUB_SOC_TLB2_12__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_13 -#define MP1_MMHUB_SOC_TLB2_13__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_14 -#define MP1_MMHUB_SOC_TLB2_14__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_15 -#define MP1_MMHUB_SOC_TLB2_15__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_16 -#define MP1_MMHUB_SOC_TLB2_16__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_17 -#define MP1_MMHUB_SOC_TLB2_17__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_18 -#define MP1_MMHUB_SOC_TLB2_18__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_19 -#define MP1_MMHUB_SOC_TLB2_19__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_20 -#define MP1_MMHUB_SOC_TLB2_20__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_21 -#define MP1_MMHUB_SOC_TLB2_21__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_22 -#define MP1_MMHUB_SOC_TLB2_22__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_23 -#define MP1_MMHUB_SOC_TLB2_23__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_24 -#define MP1_MMHUB_SOC_TLB2_24__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_25 -#define MP1_MMHUB_SOC_TLB2_25__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_26 -#define MP1_MMHUB_SOC_TLB2_26__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_27 -#define MP1_MMHUB_SOC_TLB2_27__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_28 -#define MP1_MMHUB_SOC_TLB2_28__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_29 -#define MP1_MMHUB_SOC_TLB2_29__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_30 -#define MP1_MMHUB_SOC_TLB2_30__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_31 -#define MP1_MMHUB_SOC_TLB2_31__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_32 -#define MP1_MMHUB_SOC_TLB2_32__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_33 -#define MP1_MMHUB_SOC_TLB2_33__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_34 -#define MP1_MMHUB_SOC_TLB2_34__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_35 -#define MP1_MMHUB_SOC_TLB2_35__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_36 -#define MP1_MMHUB_SOC_TLB2_36__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_37 -#define MP1_MMHUB_SOC_TLB2_37__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_38 -#define MP1_MMHUB_SOC_TLB2_38__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_39 -#define MP1_MMHUB_SOC_TLB2_39__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_40 -#define MP1_MMHUB_SOC_TLB2_40__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_41 -#define MP1_MMHUB_SOC_TLB2_41__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_42 -#define MP1_MMHUB_SOC_TLB2_42__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_43 -#define MP1_MMHUB_SOC_TLB2_43__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_44 -#define MP1_MMHUB_SOC_TLB2_44__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_45 -#define MP1_MMHUB_SOC_TLB2_45__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_46 -#define MP1_MMHUB_SOC_TLB2_46__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_47 -#define MP1_MMHUB_SOC_TLB2_47__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_48 -#define MP1_MMHUB_SOC_TLB2_48__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_49 -#define MP1_MMHUB_SOC_TLB2_49__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_50 -#define MP1_MMHUB_SOC_TLB2_50__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_51 -#define MP1_MMHUB_SOC_TLB2_51__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_52 -#define MP1_MMHUB_SOC_TLB2_52__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_53 -#define MP1_MMHUB_SOC_TLB2_53__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_54 -#define MP1_MMHUB_SOC_TLB2_54__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_55 -#define MP1_MMHUB_SOC_TLB2_55__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_56 -#define MP1_MMHUB_SOC_TLB2_56__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_57 -#define MP1_MMHUB_SOC_TLB2_57__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_58 -#define MP1_MMHUB_SOC_TLB2_58__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_59 -#define MP1_MMHUB_SOC_TLB2_59__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_60 -#define MP1_MMHUB_SOC_TLB2_60__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_61 -#define MP1_MMHUB_SOC_TLB2_61__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB2_62 -#define MP1_MMHUB_SOC_TLB2_62__AWUSER__SHIFT 0x00000000 - -// MP1_MMHUB_SOC_TLB3_1 -#define MP1_MMHUB_SOC_TLB3_1__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_1__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_2 -#define MP1_MMHUB_SOC_TLB3_2__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_2__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_3 -#define MP1_MMHUB_SOC_TLB3_3__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_3__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_4 -#define MP1_MMHUB_SOC_TLB3_4__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_4__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_5 -#define MP1_MMHUB_SOC_TLB3_5__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_5__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_6 -#define MP1_MMHUB_SOC_TLB3_6__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_6__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_7 -#define MP1_MMHUB_SOC_TLB3_7__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_7__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_8 -#define MP1_MMHUB_SOC_TLB3_8__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_8__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_9 -#define MP1_MMHUB_SOC_TLB3_9__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_9__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_10 -#define MP1_MMHUB_SOC_TLB3_10__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_10__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_11 -#define MP1_MMHUB_SOC_TLB3_11__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_11__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_12 -#define MP1_MMHUB_SOC_TLB3_12__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_12__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_13 -#define MP1_MMHUB_SOC_TLB3_13__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_13__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_14 -#define MP1_MMHUB_SOC_TLB3_14__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_14__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_15 -#define MP1_MMHUB_SOC_TLB3_15__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_15__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_16 -#define MP1_MMHUB_SOC_TLB3_16__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_16__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_17 -#define MP1_MMHUB_SOC_TLB3_17__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_17__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_18 -#define MP1_MMHUB_SOC_TLB3_18__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_18__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_19 -#define MP1_MMHUB_SOC_TLB3_19__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_19__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_20 -#define MP1_MMHUB_SOC_TLB3_20__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_20__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_21 -#define MP1_MMHUB_SOC_TLB3_21__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_21__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_22 -#define MP1_MMHUB_SOC_TLB3_22__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_22__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_23 -#define MP1_MMHUB_SOC_TLB3_23__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_23__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_24 -#define MP1_MMHUB_SOC_TLB3_24__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_24__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_25 -#define MP1_MMHUB_SOC_TLB3_25__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_25__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_26 -#define MP1_MMHUB_SOC_TLB3_26__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_26__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_27 -#define MP1_MMHUB_SOC_TLB3_27__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_27__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_28 -#define MP1_MMHUB_SOC_TLB3_28__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_28__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_29 -#define MP1_MMHUB_SOC_TLB3_29__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_29__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_30 -#define MP1_MMHUB_SOC_TLB3_30__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_30__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_31 -#define MP1_MMHUB_SOC_TLB3_31__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_31__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_32 -#define MP1_MMHUB_SOC_TLB3_32__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_32__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_33 -#define MP1_MMHUB_SOC_TLB3_33__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_33__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_34 -#define MP1_MMHUB_SOC_TLB3_34__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_34__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_35 -#define MP1_MMHUB_SOC_TLB3_35__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_35__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_36 -#define MP1_MMHUB_SOC_TLB3_36__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_36__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_37 -#define MP1_MMHUB_SOC_TLB3_37__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_37__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_38 -#define MP1_MMHUB_SOC_TLB3_38__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_38__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_39 -#define MP1_MMHUB_SOC_TLB3_39__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_39__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_40 -#define MP1_MMHUB_SOC_TLB3_40__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_40__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_41 -#define MP1_MMHUB_SOC_TLB3_41__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_41__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_42 -#define MP1_MMHUB_SOC_TLB3_42__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_42__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_43 -#define MP1_MMHUB_SOC_TLB3_43__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_43__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_44 -#define MP1_MMHUB_SOC_TLB3_44__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_44__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_45 -#define MP1_MMHUB_SOC_TLB3_45__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_45__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_46 -#define MP1_MMHUB_SOC_TLB3_46__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_46__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_47 -#define MP1_MMHUB_SOC_TLB3_47__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_47__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_48 -#define MP1_MMHUB_SOC_TLB3_48__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_48__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_49 -#define MP1_MMHUB_SOC_TLB3_49__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_49__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_50 -#define MP1_MMHUB_SOC_TLB3_50__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_50__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_51 -#define MP1_MMHUB_SOC_TLB3_51__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_51__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_52 -#define MP1_MMHUB_SOC_TLB3_52__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_52__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_53 -#define MP1_MMHUB_SOC_TLB3_53__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_53__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_54 -#define MP1_MMHUB_SOC_TLB3_54__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_54__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_55 -#define MP1_MMHUB_SOC_TLB3_55__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_55__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_56 -#define MP1_MMHUB_SOC_TLB3_56__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_56__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_57 -#define MP1_MMHUB_SOC_TLB3_57__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_57__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_58 -#define MP1_MMHUB_SOC_TLB3_58__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_58__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_59 -#define MP1_MMHUB_SOC_TLB3_59__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_59__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_60 -#define MP1_MMHUB_SOC_TLB3_60__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_60__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_61 -#define MP1_MMHUB_SOC_TLB3_61__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_61__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_SOC_TLB3_62 -#define MP1_MMHUB_SOC_TLB3_62__ARUSER__SHIFT 0x00000000 -#define MP1_MMHUB_SOC_TLB3_62__WUSER__SHIFT 0x0000001a - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_MMHUB_TLB_ATTRIBUTE_1 -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_2 -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_3 -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_4 -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_5 -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_6 -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_7 -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_8 -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_9 -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_10 -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_11 -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_12 -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_13 -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_14 -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_15 -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_16 -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_17 -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_18 -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_19 -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_20 -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_21 -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_22 -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_23 -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_24 -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_25 -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_26 -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_27 -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_28 -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_29 -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_30 -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_31 -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_32 -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_33 -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_34 -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_35 -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_36 -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_37 -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_38 -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_39 -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_40 -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_41 -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_42 -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_43 -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_44 -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_45 -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_46 -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_47 -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_48 -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_49 -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_50 -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_51 -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_52 -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_53 -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_54 -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_55 -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_56 -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_57 -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_58 -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_59 -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_60 -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_61 -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_TLB_ATTRIBUTE_62 -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_MMHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_MMHUB_INT_STATUS -#define MP1_MMHUB_INT_STATUS__RD_ERROR__SHIFT 0x00000000 -#define MP1_MMHUB_INT_STATUS__WR_ERROR__SHIFT 0x00000001 -#define MP1_MMHUB_INT_STATUS__REG_ERROR__SHIFT 0x00000002 - -// MP1_MMHUB_WR_INT_ADDR -#define MP1_MMHUB_WR_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_WR_INT_OTHER -#define MP1_MMHUB_WR_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP1_MMHUB_WR_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP1_MMHUB_WR_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP1_MMHUB_WR_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP1_MMHUB_WR_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP1_MMHUB_WR_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP1_MMHUB_WR_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP1_MMHUB_WR_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP1_MMHUB_RD_INT_ADDR -#define MP1_MMHUB_RD_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_RD_INT_OTHER -#define MP1_MMHUB_RD_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP1_MMHUB_RD_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP1_MMHUB_RD_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP1_MMHUB_RD_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP1_MMHUB_RD_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP1_MMHUB_RD_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP1_MMHUB_RD_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP1_MMHUB_RD_INT_OTHER__ERROR_LENGTH__SHIFT 0x0000001a -#define MP1_MMHUB_RD_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP1_MMHUB_REG_INT_ADDR -#define MP1_MMHUB_REG_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP1_MMHUB_REG_INT_OTHER -#define MP1_MMHUB_REG_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP1_MMHUB_REG_INT_OTHER__ERROR_AES__SHIFT 0x00000014 -#define MP1_MMHUB_REG_INT_OTHER__ERROR_MST__SHIFT 0x00000015 -#define MP1_MMHUB_REG_INT_OTHER__ERROR_ADDR__SHIFT 0x00000016 -#define MP1_MMHUB_REG_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP1_MMHUB_REG_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP1_MMHUB_AXCACHE_CFG -#define MP1_MMHUB_AXCACHE_CFG__ARCACHE_NONCOH__SHIFT 0x00000000 -#define MP1_MMHUB_AXCACHE_CFG__ARCACHE_COH__SHIFT 0x00000004 -#define MP1_MMHUB_AXCACHE_CFG__AWCACHE_NONCOH__SHIFT 0x00000008 -#define MP1_MMHUB_AXCACHE_CFG__AWCACHE_COH__SHIFT 0x0000000c -#define MP1_MMHUB_AXCACHE_CFG__QOSW__SHIFT 0x00000010 -#define MP1_MMHUB_AXCACHE_CFG__QOSR__SHIFT 0x00000014 - -// MP1_MMHUB_DS_OVERRIDE -#define MP1_MMHUB_DS_OVERRIDE__DS_CNT__SHIFT 0x00000000 -#define MP1_MMHUB_DS_OVERRIDE__DS_DISABLE__SHIFT 0x0000000b - -// MP1_MMHUB_OUTSTANDING -#define MP1_MMHUB_OUTSTANDING__PENDING_WR__SHIFT 0x00000000 -#define MP1_MMHUB_OUTSTANDING__PENDING_RD__SHIFT 0x00000010 - -// MP1_SYSHUB_SOC_TLB0_1 -#define MP1_SYSHUB_SOC_TLB0_1__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_2 -#define MP1_SYSHUB_SOC_TLB0_2__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_3 -#define MP1_SYSHUB_SOC_TLB0_3__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_4 -#define MP1_SYSHUB_SOC_TLB0_4__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_5 -#define MP1_SYSHUB_SOC_TLB0_5__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_6 -#define MP1_SYSHUB_SOC_TLB0_6__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_7 -#define MP1_SYSHUB_SOC_TLB0_7__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_8 -#define MP1_SYSHUB_SOC_TLB0_8__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_9 -#define MP1_SYSHUB_SOC_TLB0_9__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_10 -#define MP1_SYSHUB_SOC_TLB0_10__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_11 -#define MP1_SYSHUB_SOC_TLB0_11__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_12 -#define MP1_SYSHUB_SOC_TLB0_12__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_13 -#define MP1_SYSHUB_SOC_TLB0_13__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_14 -#define MP1_SYSHUB_SOC_TLB0_14__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_15 -#define MP1_SYSHUB_SOC_TLB0_15__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_16 -#define MP1_SYSHUB_SOC_TLB0_16__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_17 -#define MP1_SYSHUB_SOC_TLB0_17__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_18 -#define MP1_SYSHUB_SOC_TLB0_18__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_19 -#define MP1_SYSHUB_SOC_TLB0_19__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_20 -#define MP1_SYSHUB_SOC_TLB0_20__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_21 -#define MP1_SYSHUB_SOC_TLB0_21__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_22 -#define MP1_SYSHUB_SOC_TLB0_22__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_23 -#define MP1_SYSHUB_SOC_TLB0_23__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_24 -#define MP1_SYSHUB_SOC_TLB0_24__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_25 -#define MP1_SYSHUB_SOC_TLB0_25__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_26 -#define MP1_SYSHUB_SOC_TLB0_26__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_27 -#define MP1_SYSHUB_SOC_TLB0_27__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_28 -#define MP1_SYSHUB_SOC_TLB0_28__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_29 -#define MP1_SYSHUB_SOC_TLB0_29__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_30 -#define MP1_SYSHUB_SOC_TLB0_30__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_31 -#define MP1_SYSHUB_SOC_TLB0_31__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_32 -#define MP1_SYSHUB_SOC_TLB0_32__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_33 -#define MP1_SYSHUB_SOC_TLB0_33__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_34 -#define MP1_SYSHUB_SOC_TLB0_34__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_35 -#define MP1_SYSHUB_SOC_TLB0_35__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_36 -#define MP1_SYSHUB_SOC_TLB0_36__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_37 -#define MP1_SYSHUB_SOC_TLB0_37__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_38 -#define MP1_SYSHUB_SOC_TLB0_38__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_39 -#define MP1_SYSHUB_SOC_TLB0_39__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_40 -#define MP1_SYSHUB_SOC_TLB0_40__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_41 -#define MP1_SYSHUB_SOC_TLB0_41__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_42 -#define MP1_SYSHUB_SOC_TLB0_42__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_43 -#define MP1_SYSHUB_SOC_TLB0_43__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_44 -#define MP1_SYSHUB_SOC_TLB0_44__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_45 -#define MP1_SYSHUB_SOC_TLB0_45__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_46 -#define MP1_SYSHUB_SOC_TLB0_46__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_47 -#define MP1_SYSHUB_SOC_TLB0_47__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_48 -#define MP1_SYSHUB_SOC_TLB0_48__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_49 -#define MP1_SYSHUB_SOC_TLB0_49__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_50 -#define MP1_SYSHUB_SOC_TLB0_50__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_51 -#define MP1_SYSHUB_SOC_TLB0_51__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_52 -#define MP1_SYSHUB_SOC_TLB0_52__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_53 -#define MP1_SYSHUB_SOC_TLB0_53__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_54 -#define MP1_SYSHUB_SOC_TLB0_54__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_55 -#define MP1_SYSHUB_SOC_TLB0_55__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_56 -#define MP1_SYSHUB_SOC_TLB0_56__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_57 -#define MP1_SYSHUB_SOC_TLB0_57__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_58 -#define MP1_SYSHUB_SOC_TLB0_58__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_59 -#define MP1_SYSHUB_SOC_TLB0_59__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_60 -#define MP1_SYSHUB_SOC_TLB0_60__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_61 -#define MP1_SYSHUB_SOC_TLB0_61__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB0_62 -#define MP1_SYSHUB_SOC_TLB0_62__SOC_ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB1_1 -#define MP1_SYSHUB_SOC_TLB1_1__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_1__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_1__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_2 -#define MP1_SYSHUB_SOC_TLB1_2__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_2__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_2__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_3 -#define MP1_SYSHUB_SOC_TLB1_3__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_3__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_3__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_4 -#define MP1_SYSHUB_SOC_TLB1_4__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_4__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_4__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_5 -#define MP1_SYSHUB_SOC_TLB1_5__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_5__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_5__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_6 -#define MP1_SYSHUB_SOC_TLB1_6__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_6__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_6__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_7 -#define MP1_SYSHUB_SOC_TLB1_7__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_7__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_7__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_8 -#define MP1_SYSHUB_SOC_TLB1_8__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_8__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_8__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_9 -#define MP1_SYSHUB_SOC_TLB1_9__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_9__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_9__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_10 -#define MP1_SYSHUB_SOC_TLB1_10__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_10__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_10__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_11 -#define MP1_SYSHUB_SOC_TLB1_11__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_11__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_11__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_12 -#define MP1_SYSHUB_SOC_TLB1_12__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_12__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_12__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_13 -#define MP1_SYSHUB_SOC_TLB1_13__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_13__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_13__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_14 -#define MP1_SYSHUB_SOC_TLB1_14__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_14__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_14__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_15 -#define MP1_SYSHUB_SOC_TLB1_15__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_15__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_15__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_16 -#define MP1_SYSHUB_SOC_TLB1_16__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_16__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_16__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_17 -#define MP1_SYSHUB_SOC_TLB1_17__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_17__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_17__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_18 -#define MP1_SYSHUB_SOC_TLB1_18__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_18__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_18__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_19 -#define MP1_SYSHUB_SOC_TLB1_19__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_19__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_19__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_20 -#define MP1_SYSHUB_SOC_TLB1_20__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_20__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_20__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_21 -#define MP1_SYSHUB_SOC_TLB1_21__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_21__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_21__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_22 -#define MP1_SYSHUB_SOC_TLB1_22__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_22__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_22__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_23 -#define MP1_SYSHUB_SOC_TLB1_23__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_23__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_23__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_24 -#define MP1_SYSHUB_SOC_TLB1_24__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_24__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_24__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_25 -#define MP1_SYSHUB_SOC_TLB1_25__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_25__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_25__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_26 -#define MP1_SYSHUB_SOC_TLB1_26__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_26__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_26__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_27 -#define MP1_SYSHUB_SOC_TLB1_27__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_27__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_27__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_28 -#define MP1_SYSHUB_SOC_TLB1_28__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_28__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_28__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_29 -#define MP1_SYSHUB_SOC_TLB1_29__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_29__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_29__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_30 -#define MP1_SYSHUB_SOC_TLB1_30__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_30__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_30__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_31 -#define MP1_SYSHUB_SOC_TLB1_31__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_31__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_31__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_32 -#define MP1_SYSHUB_SOC_TLB1_32__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_32__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_32__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_33 -#define MP1_SYSHUB_SOC_TLB1_33__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_33__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_33__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_34 -#define MP1_SYSHUB_SOC_TLB1_34__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_34__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_34__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_35 -#define MP1_SYSHUB_SOC_TLB1_35__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_35__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_35__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_36 -#define MP1_SYSHUB_SOC_TLB1_36__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_36__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_36__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_37 -#define MP1_SYSHUB_SOC_TLB1_37__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_37__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_37__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_38 -#define MP1_SYSHUB_SOC_TLB1_38__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_38__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_38__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_39 -#define MP1_SYSHUB_SOC_TLB1_39__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_39__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_39__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_40 -#define MP1_SYSHUB_SOC_TLB1_40__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_40__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_40__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_41 -#define MP1_SYSHUB_SOC_TLB1_41__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_41__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_41__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_42 -#define MP1_SYSHUB_SOC_TLB1_42__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_42__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_42__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_43 -#define MP1_SYSHUB_SOC_TLB1_43__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_43__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_43__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_44 -#define MP1_SYSHUB_SOC_TLB1_44__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_44__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_44__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_45 -#define MP1_SYSHUB_SOC_TLB1_45__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_45__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_45__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_46 -#define MP1_SYSHUB_SOC_TLB1_46__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_46__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_46__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_47 -#define MP1_SYSHUB_SOC_TLB1_47__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_47__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_47__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_48 -#define MP1_SYSHUB_SOC_TLB1_48__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_48__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_48__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_49 -#define MP1_SYSHUB_SOC_TLB1_49__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_49__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_49__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_50 -#define MP1_SYSHUB_SOC_TLB1_50__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_50__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_50__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_51 -#define MP1_SYSHUB_SOC_TLB1_51__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_51__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_51__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_52 -#define MP1_SYSHUB_SOC_TLB1_52__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_52__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_52__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_53 -#define MP1_SYSHUB_SOC_TLB1_53__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_53__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_53__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_54 -#define MP1_SYSHUB_SOC_TLB1_54__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_54__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_54__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_55 -#define MP1_SYSHUB_SOC_TLB1_55__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_55__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_55__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_56 -#define MP1_SYSHUB_SOC_TLB1_56__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_56__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_56__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_57 -#define MP1_SYSHUB_SOC_TLB1_57__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_57__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_57__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_58 -#define MP1_SYSHUB_SOC_TLB1_58__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_58__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_58__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_59 -#define MP1_SYSHUB_SOC_TLB1_59__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_59__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_59__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_60 -#define MP1_SYSHUB_SOC_TLB1_60__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_60__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_60__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_61 -#define MP1_SYSHUB_SOC_TLB1_61__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_61__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_61__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB1_62 -#define MP1_SYSHUB_SOC_TLB1_62__COHERENCE__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB1_62__SEG_SIZE__SHIFT 0x00000001 -#define MP1_SYSHUB_SOC_TLB1_62__SEG_OFFSET__SHIFT 0x00000005 - -// MP1_SYSHUB_SOC_TLB2_1 -#define MP1_SYSHUB_SOC_TLB2_1__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_2 -#define MP1_SYSHUB_SOC_TLB2_2__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_3 -#define MP1_SYSHUB_SOC_TLB2_3__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_4 -#define MP1_SYSHUB_SOC_TLB2_4__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_5 -#define MP1_SYSHUB_SOC_TLB2_5__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_6 -#define MP1_SYSHUB_SOC_TLB2_6__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_7 -#define MP1_SYSHUB_SOC_TLB2_7__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_8 -#define MP1_SYSHUB_SOC_TLB2_8__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_9 -#define MP1_SYSHUB_SOC_TLB2_9__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_10 -#define MP1_SYSHUB_SOC_TLB2_10__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_11 -#define MP1_SYSHUB_SOC_TLB2_11__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_12 -#define MP1_SYSHUB_SOC_TLB2_12__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_13 -#define MP1_SYSHUB_SOC_TLB2_13__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_14 -#define MP1_SYSHUB_SOC_TLB2_14__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_15 -#define MP1_SYSHUB_SOC_TLB2_15__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_16 -#define MP1_SYSHUB_SOC_TLB2_16__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_17 -#define MP1_SYSHUB_SOC_TLB2_17__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_18 -#define MP1_SYSHUB_SOC_TLB2_18__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_19 -#define MP1_SYSHUB_SOC_TLB2_19__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_20 -#define MP1_SYSHUB_SOC_TLB2_20__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_21 -#define MP1_SYSHUB_SOC_TLB2_21__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_22 -#define MP1_SYSHUB_SOC_TLB2_22__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_23 -#define MP1_SYSHUB_SOC_TLB2_23__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_24 -#define MP1_SYSHUB_SOC_TLB2_24__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_25 -#define MP1_SYSHUB_SOC_TLB2_25__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_26 -#define MP1_SYSHUB_SOC_TLB2_26__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_27 -#define MP1_SYSHUB_SOC_TLB2_27__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_28 -#define MP1_SYSHUB_SOC_TLB2_28__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_29 -#define MP1_SYSHUB_SOC_TLB2_29__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_30 -#define MP1_SYSHUB_SOC_TLB2_30__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_31 -#define MP1_SYSHUB_SOC_TLB2_31__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_32 -#define MP1_SYSHUB_SOC_TLB2_32__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_33 -#define MP1_SYSHUB_SOC_TLB2_33__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_34 -#define MP1_SYSHUB_SOC_TLB2_34__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_35 -#define MP1_SYSHUB_SOC_TLB2_35__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_36 -#define MP1_SYSHUB_SOC_TLB2_36__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_37 -#define MP1_SYSHUB_SOC_TLB2_37__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_38 -#define MP1_SYSHUB_SOC_TLB2_38__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_39 -#define MP1_SYSHUB_SOC_TLB2_39__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_40 -#define MP1_SYSHUB_SOC_TLB2_40__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_41 -#define MP1_SYSHUB_SOC_TLB2_41__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_42 -#define MP1_SYSHUB_SOC_TLB2_42__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_43 -#define MP1_SYSHUB_SOC_TLB2_43__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_44 -#define MP1_SYSHUB_SOC_TLB2_44__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_45 -#define MP1_SYSHUB_SOC_TLB2_45__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_46 -#define MP1_SYSHUB_SOC_TLB2_46__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_47 -#define MP1_SYSHUB_SOC_TLB2_47__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_48 -#define MP1_SYSHUB_SOC_TLB2_48__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_49 -#define MP1_SYSHUB_SOC_TLB2_49__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_50 -#define MP1_SYSHUB_SOC_TLB2_50__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_51 -#define MP1_SYSHUB_SOC_TLB2_51__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_52 -#define MP1_SYSHUB_SOC_TLB2_52__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_53 -#define MP1_SYSHUB_SOC_TLB2_53__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_54 -#define MP1_SYSHUB_SOC_TLB2_54__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_55 -#define MP1_SYSHUB_SOC_TLB2_55__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_56 -#define MP1_SYSHUB_SOC_TLB2_56__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_57 -#define MP1_SYSHUB_SOC_TLB2_57__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_58 -#define MP1_SYSHUB_SOC_TLB2_58__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_59 -#define MP1_SYSHUB_SOC_TLB2_59__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_60 -#define MP1_SYSHUB_SOC_TLB2_60__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_61 -#define MP1_SYSHUB_SOC_TLB2_61__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB2_62 -#define MP1_SYSHUB_SOC_TLB2_62__AWUSER__SHIFT 0x00000000 - -// MP1_SYSHUB_SOC_TLB3_1 -#define MP1_SYSHUB_SOC_TLB3_1__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_1__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_2 -#define MP1_SYSHUB_SOC_TLB3_2__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_2__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_3 -#define MP1_SYSHUB_SOC_TLB3_3__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_3__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_4 -#define MP1_SYSHUB_SOC_TLB3_4__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_4__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_5 -#define MP1_SYSHUB_SOC_TLB3_5__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_5__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_6 -#define MP1_SYSHUB_SOC_TLB3_6__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_6__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_7 -#define MP1_SYSHUB_SOC_TLB3_7__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_7__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_8 -#define MP1_SYSHUB_SOC_TLB3_8__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_8__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_9 -#define MP1_SYSHUB_SOC_TLB3_9__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_9__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_10 -#define MP1_SYSHUB_SOC_TLB3_10__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_10__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_11 -#define MP1_SYSHUB_SOC_TLB3_11__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_11__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_12 -#define MP1_SYSHUB_SOC_TLB3_12__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_12__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_13 -#define MP1_SYSHUB_SOC_TLB3_13__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_13__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_14 -#define MP1_SYSHUB_SOC_TLB3_14__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_14__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_15 -#define MP1_SYSHUB_SOC_TLB3_15__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_15__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_16 -#define MP1_SYSHUB_SOC_TLB3_16__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_16__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_17 -#define MP1_SYSHUB_SOC_TLB3_17__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_17__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_18 -#define MP1_SYSHUB_SOC_TLB3_18__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_18__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_19 -#define MP1_SYSHUB_SOC_TLB3_19__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_19__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_20 -#define MP1_SYSHUB_SOC_TLB3_20__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_20__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_21 -#define MP1_SYSHUB_SOC_TLB3_21__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_21__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_22 -#define MP1_SYSHUB_SOC_TLB3_22__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_22__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_23 -#define MP1_SYSHUB_SOC_TLB3_23__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_23__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_24 -#define MP1_SYSHUB_SOC_TLB3_24__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_24__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_25 -#define MP1_SYSHUB_SOC_TLB3_25__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_25__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_26 -#define MP1_SYSHUB_SOC_TLB3_26__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_26__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_27 -#define MP1_SYSHUB_SOC_TLB3_27__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_27__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_28 -#define MP1_SYSHUB_SOC_TLB3_28__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_28__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_29 -#define MP1_SYSHUB_SOC_TLB3_29__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_29__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_30 -#define MP1_SYSHUB_SOC_TLB3_30__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_30__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_31 -#define MP1_SYSHUB_SOC_TLB3_31__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_31__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_32 -#define MP1_SYSHUB_SOC_TLB3_32__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_32__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_33 -#define MP1_SYSHUB_SOC_TLB3_33__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_33__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_34 -#define MP1_SYSHUB_SOC_TLB3_34__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_34__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_35 -#define MP1_SYSHUB_SOC_TLB3_35__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_35__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_36 -#define MP1_SYSHUB_SOC_TLB3_36__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_36__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_37 -#define MP1_SYSHUB_SOC_TLB3_37__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_37__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_38 -#define MP1_SYSHUB_SOC_TLB3_38__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_38__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_39 -#define MP1_SYSHUB_SOC_TLB3_39__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_39__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_40 -#define MP1_SYSHUB_SOC_TLB3_40__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_40__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_41 -#define MP1_SYSHUB_SOC_TLB3_41__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_41__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_42 -#define MP1_SYSHUB_SOC_TLB3_42__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_42__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_43 -#define MP1_SYSHUB_SOC_TLB3_43__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_43__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_44 -#define MP1_SYSHUB_SOC_TLB3_44__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_44__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_45 -#define MP1_SYSHUB_SOC_TLB3_45__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_45__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_46 -#define MP1_SYSHUB_SOC_TLB3_46__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_46__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_47 -#define MP1_SYSHUB_SOC_TLB3_47__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_47__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_48 -#define MP1_SYSHUB_SOC_TLB3_48__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_48__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_49 -#define MP1_SYSHUB_SOC_TLB3_49__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_49__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_50 -#define MP1_SYSHUB_SOC_TLB3_50__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_50__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_51 -#define MP1_SYSHUB_SOC_TLB3_51__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_51__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_52 -#define MP1_SYSHUB_SOC_TLB3_52__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_52__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_53 -#define MP1_SYSHUB_SOC_TLB3_53__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_53__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_54 -#define MP1_SYSHUB_SOC_TLB3_54__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_54__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_55 -#define MP1_SYSHUB_SOC_TLB3_55__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_55__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_56 -#define MP1_SYSHUB_SOC_TLB3_56__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_56__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_57 -#define MP1_SYSHUB_SOC_TLB3_57__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_57__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_58 -#define MP1_SYSHUB_SOC_TLB3_58__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_58__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_59 -#define MP1_SYSHUB_SOC_TLB3_59__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_59__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_60 -#define MP1_SYSHUB_SOC_TLB3_60__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_60__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_61 -#define MP1_SYSHUB_SOC_TLB3_61__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_61__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_SOC_TLB3_62 -#define MP1_SYSHUB_SOC_TLB3_62__ARUSER__SHIFT 0x00000000 -#define MP1_SYSHUB_SOC_TLB3_62__WUSER__SHIFT 0x0000001a - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB__SHIFT 0x00000000 - -// MP1_SYSHUB_TLB_ATTRIBUTE_1 -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_1__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_2 -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_2__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_3 -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_3__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_4 -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_4__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_5 -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_5__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_6 -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_6__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_7 -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_7__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_8 -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_8__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_9 -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_9__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_10 -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_10__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_11 -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_11__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_12 -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_12__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_13 -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_13__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_14 -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_14__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_15 -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_15__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_16 -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_16__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_17 -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_17__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_18 -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_18__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_19 -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_19__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_20 -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_20__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_21 -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_21__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_22 -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_22__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_23 -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_23__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_24 -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_24__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_25 -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_25__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_26 -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_26__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_27 -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_27__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_28 -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_28__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_29 -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_29__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_30 -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_30__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_31 -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_31__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_32 -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_32__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_33 -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_33__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_34 -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_34__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_35 -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_35__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_36 -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_36__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_37 -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_37__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_38 -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_38__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_39 -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_39__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_40 -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_40__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_41 -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_41__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_42 -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_42__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_43 -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_43__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_44 -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_44__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_45 -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_45__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_46 -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_46__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_47 -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_47__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_48 -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_48__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_49 -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_49__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_50 -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_50__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_51 -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_51__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_52 -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_52__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_53 -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_53__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_54 -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_54__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_55 -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_55__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_56 -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_56__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_57 -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_57__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_58 -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_58__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_59 -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_59__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_60 -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_60__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_61 -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_61__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_TLB_ATTRIBUTE_62 -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_DMA__SHIFT 0x00000017 -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PUB__SHIFT 0x0000001e -#define MP1_SYSHUB_TLB_ATTRIBUTE_62__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP1_SYSHUB_INT_STATUS -#define MP1_SYSHUB_INT_STATUS__RD_ERROR__SHIFT 0x00000000 -#define MP1_SYSHUB_INT_STATUS__WR_ERROR__SHIFT 0x00000001 -#define MP1_SYSHUB_INT_STATUS__REG_ERROR__SHIFT 0x00000002 - -// MP1_SYSHUB_WR_INT_ADDR -#define MP1_SYSHUB_WR_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_WR_INT_OTHER -#define MP1_SYSHUB_WR_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP1_SYSHUB_WR_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP1_SYSHUB_WR_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP1_SYSHUB_RD_INT_ADDR -#define MP1_SYSHUB_RD_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_RD_INT_OTHER -#define MP1_SYSHUB_RD_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP1_SYSHUB_RD_INT_OTHER__ERROR_LENGTH__SHIFT 0x0000001a -#define MP1_SYSHUB_RD_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP1_SYSHUB_REG_INT_ADDR -#define MP1_SYSHUB_REG_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP1_SYSHUB_REG_INT_OTHER -#define MP1_SYSHUB_REG_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_AES__SHIFT 0x00000014 -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_MST__SHIFT 0x00000015 -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_ADDR__SHIFT 0x00000016 -#define MP1_SYSHUB_REG_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP1_SYSHUB_REG_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP1_SYSHUB_AXCACHE_CFG -#define MP1_SYSHUB_AXCACHE_CFG__ARCACHE_NONCOH__SHIFT 0x00000000 -#define MP1_SYSHUB_AXCACHE_CFG__ARCACHE_COH__SHIFT 0x00000004 -#define MP1_SYSHUB_AXCACHE_CFG__AWCACHE_NONCOH__SHIFT 0x00000008 -#define MP1_SYSHUB_AXCACHE_CFG__AWCACHE_COH__SHIFT 0x0000000c -#define MP1_SYSHUB_AXCACHE_CFG__QOSW__SHIFT 0x00000010 -#define MP1_SYSHUB_AXCACHE_CFG__QOSR__SHIFT 0x00000014 - -// MP1_SYSHUB_DS_OVERRIDE -#define MP1_SYSHUB_DS_OVERRIDE__DS_CNT__SHIFT 0x00000000 -#define MP1_SYSHUB_DS_OVERRIDE__DS_DISABLE__SHIFT 0x0000000b - -// MP1_SYSHUB_OUTSTANDING -#define MP1_SYSHUB_OUTSTANDING__PENDING_WR__SHIFT 0x00000000 -#define MP1_SYSHUB_OUTSTANDING__PENDING_RD__SHIFT 0x00000010 - -// MP_HUBIF_SOC_TLB0_1 -#define MP_HUBIF_SOC_TLB0_1__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_2 -#define MP_HUBIF_SOC_TLB0_2__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_3 -#define MP_HUBIF_SOC_TLB0_3__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_4 -#define MP_HUBIF_SOC_TLB0_4__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_5 -#define MP_HUBIF_SOC_TLB0_5__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_6 -#define MP_HUBIF_SOC_TLB0_6__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_7 -#define MP_HUBIF_SOC_TLB0_7__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_8 -#define MP_HUBIF_SOC_TLB0_8__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_9 -#define MP_HUBIF_SOC_TLB0_9__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_10 -#define MP_HUBIF_SOC_TLB0_10__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_11 -#define MP_HUBIF_SOC_TLB0_11__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_12 -#define MP_HUBIF_SOC_TLB0_12__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_13 -#define MP_HUBIF_SOC_TLB0_13__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_14 -#define MP_HUBIF_SOC_TLB0_14__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_15 -#define MP_HUBIF_SOC_TLB0_15__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_16 -#define MP_HUBIF_SOC_TLB0_16__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_17 -#define MP_HUBIF_SOC_TLB0_17__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_18 -#define MP_HUBIF_SOC_TLB0_18__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_19 -#define MP_HUBIF_SOC_TLB0_19__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_20 -#define MP_HUBIF_SOC_TLB0_20__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_21 -#define MP_HUBIF_SOC_TLB0_21__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_22 -#define MP_HUBIF_SOC_TLB0_22__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_23 -#define MP_HUBIF_SOC_TLB0_23__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_24 -#define MP_HUBIF_SOC_TLB0_24__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_25 -#define MP_HUBIF_SOC_TLB0_25__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_26 -#define MP_HUBIF_SOC_TLB0_26__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_27 -#define MP_HUBIF_SOC_TLB0_27__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_28 -#define MP_HUBIF_SOC_TLB0_28__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_29 -#define MP_HUBIF_SOC_TLB0_29__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_30 -#define MP_HUBIF_SOC_TLB0_30__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_31 -#define MP_HUBIF_SOC_TLB0_31__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_32 -#define MP_HUBIF_SOC_TLB0_32__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_33 -#define MP_HUBIF_SOC_TLB0_33__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_34 -#define MP_HUBIF_SOC_TLB0_34__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_35 -#define MP_HUBIF_SOC_TLB0_35__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_36 -#define MP_HUBIF_SOC_TLB0_36__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_37 -#define MP_HUBIF_SOC_TLB0_37__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_38 -#define MP_HUBIF_SOC_TLB0_38__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_39 -#define MP_HUBIF_SOC_TLB0_39__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_40 -#define MP_HUBIF_SOC_TLB0_40__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_41 -#define MP_HUBIF_SOC_TLB0_41__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_42 -#define MP_HUBIF_SOC_TLB0_42__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_43 -#define MP_HUBIF_SOC_TLB0_43__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_44 -#define MP_HUBIF_SOC_TLB0_44__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_45 -#define MP_HUBIF_SOC_TLB0_45__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_46 -#define MP_HUBIF_SOC_TLB0_46__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_47 -#define MP_HUBIF_SOC_TLB0_47__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_48 -#define MP_HUBIF_SOC_TLB0_48__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_49 -#define MP_HUBIF_SOC_TLB0_49__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_50 -#define MP_HUBIF_SOC_TLB0_50__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_51 -#define MP_HUBIF_SOC_TLB0_51__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_52 -#define MP_HUBIF_SOC_TLB0_52__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_53 -#define MP_HUBIF_SOC_TLB0_53__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_54 -#define MP_HUBIF_SOC_TLB0_54__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_55 -#define MP_HUBIF_SOC_TLB0_55__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_56 -#define MP_HUBIF_SOC_TLB0_56__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_57 -#define MP_HUBIF_SOC_TLB0_57__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_58 -#define MP_HUBIF_SOC_TLB0_58__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_59 -#define MP_HUBIF_SOC_TLB0_59__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_60 -#define MP_HUBIF_SOC_TLB0_60__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_61 -#define MP_HUBIF_SOC_TLB0_61__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB0_62 -#define MP_HUBIF_SOC_TLB0_62__SOC_ADDR__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB1_1 -#define MP_HUBIF_SOC_TLB1_1__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_1__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_1__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_2 -#define MP_HUBIF_SOC_TLB1_2__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_2__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_2__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_3 -#define MP_HUBIF_SOC_TLB1_3__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_3__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_3__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_4 -#define MP_HUBIF_SOC_TLB1_4__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_4__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_4__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_5 -#define MP_HUBIF_SOC_TLB1_5__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_5__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_5__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_6 -#define MP_HUBIF_SOC_TLB1_6__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_6__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_6__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_7 -#define MP_HUBIF_SOC_TLB1_7__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_7__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_7__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_8 -#define MP_HUBIF_SOC_TLB1_8__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_8__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_8__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_9 -#define MP_HUBIF_SOC_TLB1_9__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_9__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_9__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_10 -#define MP_HUBIF_SOC_TLB1_10__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_10__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_10__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_11 -#define MP_HUBIF_SOC_TLB1_11__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_11__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_11__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_12 -#define MP_HUBIF_SOC_TLB1_12__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_12__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_12__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_13 -#define MP_HUBIF_SOC_TLB1_13__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_13__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_13__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_14 -#define MP_HUBIF_SOC_TLB1_14__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_14__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_14__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_15 -#define MP_HUBIF_SOC_TLB1_15__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_15__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_15__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_16 -#define MP_HUBIF_SOC_TLB1_16__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_16__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_16__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_17 -#define MP_HUBIF_SOC_TLB1_17__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_17__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_17__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_18 -#define MP_HUBIF_SOC_TLB1_18__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_18__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_18__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_19 -#define MP_HUBIF_SOC_TLB1_19__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_19__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_19__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_20 -#define MP_HUBIF_SOC_TLB1_20__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_20__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_20__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_21 -#define MP_HUBIF_SOC_TLB1_21__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_21__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_21__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_22 -#define MP_HUBIF_SOC_TLB1_22__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_22__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_22__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_23 -#define MP_HUBIF_SOC_TLB1_23__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_23__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_23__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_24 -#define MP_HUBIF_SOC_TLB1_24__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_24__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_24__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_25 -#define MP_HUBIF_SOC_TLB1_25__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_25__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_25__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_26 -#define MP_HUBIF_SOC_TLB1_26__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_26__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_26__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_27 -#define MP_HUBIF_SOC_TLB1_27__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_27__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_27__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_28 -#define MP_HUBIF_SOC_TLB1_28__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_28__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_28__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_29 -#define MP_HUBIF_SOC_TLB1_29__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_29__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_29__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_30 -#define MP_HUBIF_SOC_TLB1_30__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_30__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_30__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_31 -#define MP_HUBIF_SOC_TLB1_31__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_31__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_31__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_32 -#define MP_HUBIF_SOC_TLB1_32__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_32__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_32__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_33 -#define MP_HUBIF_SOC_TLB1_33__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_33__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_33__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_34 -#define MP_HUBIF_SOC_TLB1_34__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_34__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_34__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_35 -#define MP_HUBIF_SOC_TLB1_35__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_35__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_35__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_36 -#define MP_HUBIF_SOC_TLB1_36__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_36__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_36__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_37 -#define MP_HUBIF_SOC_TLB1_37__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_37__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_37__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_38 -#define MP_HUBIF_SOC_TLB1_38__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_38__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_38__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_39 -#define MP_HUBIF_SOC_TLB1_39__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_39__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_39__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_40 -#define MP_HUBIF_SOC_TLB1_40__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_40__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_40__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_41 -#define MP_HUBIF_SOC_TLB1_41__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_41__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_41__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_42 -#define MP_HUBIF_SOC_TLB1_42__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_42__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_42__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_43 -#define MP_HUBIF_SOC_TLB1_43__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_43__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_43__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_44 -#define MP_HUBIF_SOC_TLB1_44__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_44__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_44__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_45 -#define MP_HUBIF_SOC_TLB1_45__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_45__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_45__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_46 -#define MP_HUBIF_SOC_TLB1_46__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_46__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_46__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_47 -#define MP_HUBIF_SOC_TLB1_47__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_47__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_47__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_48 -#define MP_HUBIF_SOC_TLB1_48__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_48__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_48__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_49 -#define MP_HUBIF_SOC_TLB1_49__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_49__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_49__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_50 -#define MP_HUBIF_SOC_TLB1_50__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_50__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_50__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_51 -#define MP_HUBIF_SOC_TLB1_51__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_51__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_51__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_52 -#define MP_HUBIF_SOC_TLB1_52__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_52__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_52__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_53 -#define MP_HUBIF_SOC_TLB1_53__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_53__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_53__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_54 -#define MP_HUBIF_SOC_TLB1_54__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_54__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_54__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_55 -#define MP_HUBIF_SOC_TLB1_55__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_55__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_55__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_56 -#define MP_HUBIF_SOC_TLB1_56__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_56__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_56__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_57 -#define MP_HUBIF_SOC_TLB1_57__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_57__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_57__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_58 -#define MP_HUBIF_SOC_TLB1_58__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_58__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_58__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_59 -#define MP_HUBIF_SOC_TLB1_59__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_59__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_59__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_60 -#define MP_HUBIF_SOC_TLB1_60__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_60__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_60__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_61 -#define MP_HUBIF_SOC_TLB1_61__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_61__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_61__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB1_62 -#define MP_HUBIF_SOC_TLB1_62__COHERENCE__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB1_62__SEG_SIZE__SHIFT 0x00000001 -#define MP_HUBIF_SOC_TLB1_62__SEG_OFFSET__SHIFT 0x00000005 - -// MP_HUBIF_SOC_TLB2_1 -#define MP_HUBIF_SOC_TLB2_1__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_2 -#define MP_HUBIF_SOC_TLB2_2__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_3 -#define MP_HUBIF_SOC_TLB2_3__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_4 -#define MP_HUBIF_SOC_TLB2_4__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_5 -#define MP_HUBIF_SOC_TLB2_5__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_6 -#define MP_HUBIF_SOC_TLB2_6__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_7 -#define MP_HUBIF_SOC_TLB2_7__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_8 -#define MP_HUBIF_SOC_TLB2_8__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_9 -#define MP_HUBIF_SOC_TLB2_9__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_10 -#define MP_HUBIF_SOC_TLB2_10__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_11 -#define MP_HUBIF_SOC_TLB2_11__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_12 -#define MP_HUBIF_SOC_TLB2_12__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_13 -#define MP_HUBIF_SOC_TLB2_13__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_14 -#define MP_HUBIF_SOC_TLB2_14__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_15 -#define MP_HUBIF_SOC_TLB2_15__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_16 -#define MP_HUBIF_SOC_TLB2_16__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_17 -#define MP_HUBIF_SOC_TLB2_17__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_18 -#define MP_HUBIF_SOC_TLB2_18__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_19 -#define MP_HUBIF_SOC_TLB2_19__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_20 -#define MP_HUBIF_SOC_TLB2_20__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_21 -#define MP_HUBIF_SOC_TLB2_21__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_22 -#define MP_HUBIF_SOC_TLB2_22__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_23 -#define MP_HUBIF_SOC_TLB2_23__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_24 -#define MP_HUBIF_SOC_TLB2_24__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_25 -#define MP_HUBIF_SOC_TLB2_25__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_26 -#define MP_HUBIF_SOC_TLB2_26__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_27 -#define MP_HUBIF_SOC_TLB2_27__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_28 -#define MP_HUBIF_SOC_TLB2_28__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_29 -#define MP_HUBIF_SOC_TLB2_29__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_30 -#define MP_HUBIF_SOC_TLB2_30__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_31 -#define MP_HUBIF_SOC_TLB2_31__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_32 -#define MP_HUBIF_SOC_TLB2_32__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_33 -#define MP_HUBIF_SOC_TLB2_33__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_34 -#define MP_HUBIF_SOC_TLB2_34__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_35 -#define MP_HUBIF_SOC_TLB2_35__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_36 -#define MP_HUBIF_SOC_TLB2_36__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_37 -#define MP_HUBIF_SOC_TLB2_37__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_38 -#define MP_HUBIF_SOC_TLB2_38__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_39 -#define MP_HUBIF_SOC_TLB2_39__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_40 -#define MP_HUBIF_SOC_TLB2_40__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_41 -#define MP_HUBIF_SOC_TLB2_41__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_42 -#define MP_HUBIF_SOC_TLB2_42__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_43 -#define MP_HUBIF_SOC_TLB2_43__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_44 -#define MP_HUBIF_SOC_TLB2_44__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_45 -#define MP_HUBIF_SOC_TLB2_45__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_46 -#define MP_HUBIF_SOC_TLB2_46__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_47 -#define MP_HUBIF_SOC_TLB2_47__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_48 -#define MP_HUBIF_SOC_TLB2_48__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_49 -#define MP_HUBIF_SOC_TLB2_49__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_50 -#define MP_HUBIF_SOC_TLB2_50__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_51 -#define MP_HUBIF_SOC_TLB2_51__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_52 -#define MP_HUBIF_SOC_TLB2_52__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_53 -#define MP_HUBIF_SOC_TLB2_53__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_54 -#define MP_HUBIF_SOC_TLB2_54__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_55 -#define MP_HUBIF_SOC_TLB2_55__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_56 -#define MP_HUBIF_SOC_TLB2_56__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_57 -#define MP_HUBIF_SOC_TLB2_57__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_58 -#define MP_HUBIF_SOC_TLB2_58__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_59 -#define MP_HUBIF_SOC_TLB2_59__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_60 -#define MP_HUBIF_SOC_TLB2_60__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_61 -#define MP_HUBIF_SOC_TLB2_61__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB2_62 -#define MP_HUBIF_SOC_TLB2_62__AWUSER__SHIFT 0x00000000 - -// MP_HUBIF_SOC_TLB3_1 -#define MP_HUBIF_SOC_TLB3_1__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_1__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_2 -#define MP_HUBIF_SOC_TLB3_2__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_2__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_3 -#define MP_HUBIF_SOC_TLB3_3__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_3__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_4 -#define MP_HUBIF_SOC_TLB3_4__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_4__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_5 -#define MP_HUBIF_SOC_TLB3_5__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_5__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_6 -#define MP_HUBIF_SOC_TLB3_6__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_6__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_7 -#define MP_HUBIF_SOC_TLB3_7__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_7__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_8 -#define MP_HUBIF_SOC_TLB3_8__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_8__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_9 -#define MP_HUBIF_SOC_TLB3_9__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_9__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_10 -#define MP_HUBIF_SOC_TLB3_10__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_10__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_11 -#define MP_HUBIF_SOC_TLB3_11__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_11__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_12 -#define MP_HUBIF_SOC_TLB3_12__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_12__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_13 -#define MP_HUBIF_SOC_TLB3_13__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_13__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_14 -#define MP_HUBIF_SOC_TLB3_14__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_14__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_15 -#define MP_HUBIF_SOC_TLB3_15__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_15__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_16 -#define MP_HUBIF_SOC_TLB3_16__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_16__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_17 -#define MP_HUBIF_SOC_TLB3_17__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_17__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_18 -#define MP_HUBIF_SOC_TLB3_18__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_18__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_19 -#define MP_HUBIF_SOC_TLB3_19__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_19__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_20 -#define MP_HUBIF_SOC_TLB3_20__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_20__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_21 -#define MP_HUBIF_SOC_TLB3_21__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_21__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_22 -#define MP_HUBIF_SOC_TLB3_22__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_22__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_23 -#define MP_HUBIF_SOC_TLB3_23__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_23__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_24 -#define MP_HUBIF_SOC_TLB3_24__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_24__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_25 -#define MP_HUBIF_SOC_TLB3_25__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_25__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_26 -#define MP_HUBIF_SOC_TLB3_26__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_26__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_27 -#define MP_HUBIF_SOC_TLB3_27__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_27__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_28 -#define MP_HUBIF_SOC_TLB3_28__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_28__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_29 -#define MP_HUBIF_SOC_TLB3_29__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_29__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_30 -#define MP_HUBIF_SOC_TLB3_30__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_30__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_31 -#define MP_HUBIF_SOC_TLB3_31__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_31__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_32 -#define MP_HUBIF_SOC_TLB3_32__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_32__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_33 -#define MP_HUBIF_SOC_TLB3_33__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_33__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_34 -#define MP_HUBIF_SOC_TLB3_34__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_34__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_35 -#define MP_HUBIF_SOC_TLB3_35__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_35__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_36 -#define MP_HUBIF_SOC_TLB3_36__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_36__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_37 -#define MP_HUBIF_SOC_TLB3_37__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_37__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_38 -#define MP_HUBIF_SOC_TLB3_38__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_38__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_39 -#define MP_HUBIF_SOC_TLB3_39__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_39__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_40 -#define MP_HUBIF_SOC_TLB3_40__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_40__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_41 -#define MP_HUBIF_SOC_TLB3_41__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_41__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_42 -#define MP_HUBIF_SOC_TLB3_42__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_42__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_43 -#define MP_HUBIF_SOC_TLB3_43__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_43__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_44 -#define MP_HUBIF_SOC_TLB3_44__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_44__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_45 -#define MP_HUBIF_SOC_TLB3_45__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_45__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_46 -#define MP_HUBIF_SOC_TLB3_46__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_46__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_47 -#define MP_HUBIF_SOC_TLB3_47__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_47__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_48 -#define MP_HUBIF_SOC_TLB3_48__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_48__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_49 -#define MP_HUBIF_SOC_TLB3_49__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_49__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_50 -#define MP_HUBIF_SOC_TLB3_50__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_50__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_51 -#define MP_HUBIF_SOC_TLB3_51__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_51__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_52 -#define MP_HUBIF_SOC_TLB3_52__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_52__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_53 -#define MP_HUBIF_SOC_TLB3_53__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_53__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_54 -#define MP_HUBIF_SOC_TLB3_54__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_54__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_55 -#define MP_HUBIF_SOC_TLB3_55__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_55__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_56 -#define MP_HUBIF_SOC_TLB3_56__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_56__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_57 -#define MP_HUBIF_SOC_TLB3_57__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_57__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_58 -#define MP_HUBIF_SOC_TLB3_58__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_58__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_59 -#define MP_HUBIF_SOC_TLB3_59__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_59__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_60 -#define MP_HUBIF_SOC_TLB3_60__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_60__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_61 -#define MP_HUBIF_SOC_TLB3_61__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_61__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_SOC_TLB3_62 -#define MP_HUBIF_SOC_TLB3_62__ARUSER__SHIFT 0x00000000 -#define MP_HUBIF_SOC_TLB3_62__WUSER__SHIFT 0x0000001a - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_1 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_1__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_2 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_2__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_3 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_3__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_4 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_4__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_5 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_5__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_6 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_6__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_7 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_7__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_8 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_8__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_9 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_9__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_10 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_10__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_11 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_11__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_12 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_12__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_13 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_13__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_14 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_14__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_15 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_15__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_16 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_16__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_17 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_17__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_18 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_18__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_19 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_19__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_20 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_20__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_21 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_21__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_22 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_22__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_23 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_23__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_24 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_24__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_25 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_25__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_26 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_26__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_27 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_27__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_28 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_28__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_29 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_29__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_30 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_30__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_31 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_31__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_32 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_32__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_33 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_33__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_34 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_34__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_35 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_35__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_36 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_36__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_37 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_37__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_38 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_38__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_39 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_39__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_40 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_40__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_41 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_41__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_42 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_42__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_43 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_43__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_44 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_44__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_45 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_45__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_46 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_46__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_47 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_47__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_48 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_48__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_49 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_49__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_50 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_50__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_51 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_51__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_52 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_52__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_53 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_53__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_54 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_54__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_55 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_55__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_56 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_56__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_57 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_57__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_58 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_58__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_59 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_59__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_60 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_60__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_61 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_61__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_62 -#define MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_62__RW_ATTRIB__SHIFT 0x00000000 - -// MP_HUBIF_TLB_ATTRIBUTE_1 -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_1__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_2 -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_2__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_3 -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_3__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_4 -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_4__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_5 -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_5__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_6 -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_6__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_7 -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_7__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_8 -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_8__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_9 -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_9__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_10 -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_10__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_11 -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_11__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_12 -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_12__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_13 -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_13__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_14 -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_14__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_15 -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_15__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_16 -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_16__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_17 -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_17__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_18 -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_18__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_19 -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_19__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_20 -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_20__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_21 -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_21__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_22 -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_22__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_23 -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_23__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_24 -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_24__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_25 -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_25__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_26 -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_26__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_27 -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_27__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_28 -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_28__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_29 -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_29__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_30 -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_30__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_31 -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_31__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_32 -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_32__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_33 -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_33__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_34 -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_34__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_35 -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_35__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_36 -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_36__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_37 -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_37__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_38 -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_38__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_39 -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_39__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_40 -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_40__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_41 -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_41__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_42 -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_42__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_43 -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_43__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_44 -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_44__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_45 -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_45__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_46 -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_46__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_47 -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_47__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_48 -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_48__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_49 -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_49__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_50 -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_50__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_51 -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_51__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_52 -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_52__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_53 -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_53__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_54 -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_54__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_55 -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_55__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_56 -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_56__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_57 -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_57__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_58 -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_58__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_59 -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_59__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_60 -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_60__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_61 -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_61__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_TLB_ATTRIBUTE_62 -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_ARPROT_1__SHIFT 0x00000000 -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_AWPROT_1__SHIFT 0x00000001 -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_AES_KEY_SEL__SHIFT 0x0000000d -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_AES_EN__SHIFT 0x0000000f -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_CCP__SHIFT 0x00000017 -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_PUB__SHIFT 0x0000001e -#define MP_HUBIF_TLB_ATTRIBUTE_62__MA_PSP_PRIV__SHIFT 0x0000001f - -// MP_HUBIF_INT_STATUS -#define MP_HUBIF_INT_STATUS__RD_ERROR__SHIFT 0x00000000 -#define MP_HUBIF_INT_STATUS__WR_ERROR__SHIFT 0x00000001 -#define MP_HUBIF_INT_STATUS__REG_ERROR__SHIFT 0x00000002 - -// MP_HUBIF_WR_INT_ADDR -#define MP_HUBIF_WR_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP_HUBIF_WR_INT_OTHER -#define MP_HUBIF_WR_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP_HUBIF_WR_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP_HUBIF_WR_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP_HUBIF_WR_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP_HUBIF_WR_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP_HUBIF_WR_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP_HUBIF_WR_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP_HUBIF_WR_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP_HUBIF_RD_INT_ADDR -#define MP_HUBIF_RD_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP_HUBIF_RD_INT_OTHER -#define MP_HUBIF_RD_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP_HUBIF_RD_INT_OTHER__ERROR_TLB__SHIFT 0x00000014 -#define MP_HUBIF_RD_INT_OTHER__ERROR_PAGE__SHIFT 0x00000015 -#define MP_HUBIF_RD_INT_OTHER__ERROR_ATTRIB__SHIFT 0x00000016 -#define MP_HUBIF_RD_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP_HUBIF_RD_INT_OTHER__ERROR_MST__SHIFT 0x00000018 -#define MP_HUBIF_RD_INT_OTHER__ERROR_AES__SHIFT 0x00000019 -#define MP_HUBIF_RD_INT_OTHER__ERROR_LENGTH__SHIFT 0x0000001a -#define MP_HUBIF_RD_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP_HUBIF_REG_INT_ADDR -#define MP_HUBIF_REG_INT_ADDR__ADDR__SHIFT 0x00000000 - -// MP_HUBIF_REG_INT_OTHER -#define MP_HUBIF_REG_INT_OTHER__AXI_ID__SHIFT 0x00000000 -#define MP_HUBIF_REG_INT_OTHER__ERROR_AES__SHIFT 0x00000014 -#define MP_HUBIF_REG_INT_OTHER__ERROR_MST__SHIFT 0x00000015 -#define MP_HUBIF_REG_INT_OTHER__ERROR_ADDR__SHIFT 0x00000016 -#define MP_HUBIF_REG_INT_OTHER__ERROR_PROT__SHIFT 0x00000017 -#define MP_HUBIF_REG_INT_OTHER__INT_CLEAR__SHIFT 0x0000001f - -// MP_HUBIF_AXCACHE_CFG -#define MP_HUBIF_AXCACHE_CFG__ARCACHE_NONCOH__SHIFT 0x00000000 -#define MP_HUBIF_AXCACHE_CFG__ARCACHE_COH__SHIFT 0x00000004 -#define MP_HUBIF_AXCACHE_CFG__AWCACHE_NONCOH__SHIFT 0x00000008 -#define MP_HUBIF_AXCACHE_CFG__AWCACHE_COH__SHIFT 0x0000000c -#define MP_HUBIF_AXCACHE_CFG__QOSW__SHIFT 0x00000010 -#define MP_HUBIF_AXCACHE_CFG__QOSR__SHIFT 0x00000014 - -// MP_HUBIF_DS_OVERRIDE -#define MP_HUBIF_DS_OVERRIDE__DS_CNT__SHIFT 0x00000000 -#define MP_HUBIF_DS_OVERRIDE__DS_DISABLE__SHIFT 0x0000000b - -// MP_HUBIF_OUTSTANDING -#define MP_HUBIF_OUTSTANDING__PENDING_WR__SHIFT 0x00000000 -#define MP_HUBIF_OUTSTANDING__PENDING_RD__SHIFT 0x00000010 - -// HUBIF_NB_AX_ADDR_LO -#define HUBIF_NB_AX_ADDR_LO__AX_ADDR_LO__SHIFT 0x00000000 - -// HUBIF_NB_AX_MISC -#define HUBIF_NB_AX_MISC__AX_ADDR_HI__SHIFT 0x00000000 -#define HUBIF_NB_AX_MISC__AX_ID__SHIFT 0x00000010 -#define HUBIF_NB_AX_MISC__AX_QOS__SHIFT 0x00000018 - -// HUBIF_NB_AX_MISC_2 -#define HUBIF_NB_AX_MISC_2__AX_LEN__SHIFT 0x00000000 -#define HUBIF_NB_AX_MISC_2__AX_SIZE__SHIFT 0x00000008 -#define HUBIF_NB_AX_MISC_2__AX_BURST__SHIFT 0x0000000b -#define HUBIF_NB_AX_MISC_2__AX_CACHE__SHIFT 0x0000000d -#define HUBIF_NB_AX_MISC_2__AX_PROT__SHIFT 0x00000011 -#define HUBIF_NB_AX_MISC_2__AX_USER__SHIFT 0x00000014 -#define HUBIF_NB_AX_MISC_2__AX_LOCK__SHIFT 0x0000001a -#define HUBIF_NB_AX_MISC_2__AX_OPCODE__SHIFT 0x0000001c -#define HUBIF_NB_AX_MISC_2__AX_TRAN_STRT__SHIFT 0x0000001d -#define HUBIF_NB_AX_MISC_2__AX_TRAN_END__SHIFT 0x0000001e - -// HUBIF_NB_WSTRB0 -#define HUBIF_NB_WSTRB0__AX_WSTRB__SHIFT 0x00000000 - -// HUBIF_NB_WSTRB1 -#define HUBIF_NB_WSTRB1__AX_WSTRB__SHIFT 0x00000000 - -// HUBIF_NB_WDATA0 -#define HUBIF_NB_WDATA0__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA1 -#define HUBIF_NB_WDATA1__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA2 -#define HUBIF_NB_WDATA2__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA3 -#define HUBIF_NB_WDATA3__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA4 -#define HUBIF_NB_WDATA4__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA5 -#define HUBIF_NB_WDATA5__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA6 -#define HUBIF_NB_WDATA6__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA7 -#define HUBIF_NB_WDATA7__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA8 -#define HUBIF_NB_WDATA8__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA9 -#define HUBIF_NB_WDATA9__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA10 -#define HUBIF_NB_WDATA10__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA11 -#define HUBIF_NB_WDATA11__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA12 -#define HUBIF_NB_WDATA12__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA13 -#define HUBIF_NB_WDATA13__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA14 -#define HUBIF_NB_WDATA14__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_WDATA15 -#define HUBIF_NB_WDATA15__AX_WDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA0 -#define HUBIF_NB_RDATA0__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA1 -#define HUBIF_NB_RDATA1__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA2 -#define HUBIF_NB_RDATA2__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA3 -#define HUBIF_NB_RDATA3__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA4 -#define HUBIF_NB_RDATA4__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA5 -#define HUBIF_NB_RDATA5__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA6 -#define HUBIF_NB_RDATA6__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA7 -#define HUBIF_NB_RDATA7__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA8 -#define HUBIF_NB_RDATA8__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA9 -#define HUBIF_NB_RDATA9__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA10 -#define HUBIF_NB_RDATA10__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA11 -#define HUBIF_NB_RDATA11__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA12 -#define HUBIF_NB_RDATA12__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA13 -#define HUBIF_NB_RDATA13__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA14 -#define HUBIF_NB_RDATA14__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_RDATA15 -#define HUBIF_NB_RDATA15__AX_RDATA__SHIFT 0x00000000 - -// HUBIF_NB_AXI_RESP -#define HUBIF_NB_AXI_RESP__AXI_RESP__SHIFT 0x00000000 - -// HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ACC_VIOLATION_TYPE__SHIFT 0x00000001 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x00000003 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__REG_CLK_STS__SHIFT 0x00000004 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__ALLOW_NON_PRIV_REG_ACC__SHIFT 0x00000005 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__WRITE_REQ_CNT_EN__SHIFT 0x00000006 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__READ_REQ_CNT_EN__SHIFT 0x00000007 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__AXI_ID__SHIFT 0x00000008 -#define HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS__AXI_APROT__SHIFT 0x0000001a - -// HUBIF_ACC_VIOLATION_LOG_ADDR -#define HUBIF_ACC_VIOLATION_LOG_ADDR__AXI_ADDR__SHIFT 0x00000000 - -// SMNIF_TLB_0 -#define SMNIF_TLB_0__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_0__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_1 -#define SMNIF_TLB_1__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_1__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_2 -#define SMNIF_TLB_2__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_2__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_3 -#define SMNIF_TLB_3__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_3__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_4 -#define SMNIF_TLB_4__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_4__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_5 -#define SMNIF_TLB_5__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_5__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_6 -#define SMNIF_TLB_6__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_6__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_7 -#define SMNIF_TLB_7__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_7__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_8 -#define SMNIF_TLB_8__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_8__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_9 -#define SMNIF_TLB_9__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_9__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_10 -#define SMNIF_TLB_10__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_10__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_11 -#define SMNIF_TLB_11__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_11__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_12 -#define SMNIF_TLB_12__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_12__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_13 -#define SMNIF_TLB_13__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_13__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_14 -#define SMNIF_TLB_14__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_14__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLB_15 -#define SMNIF_TLB_15__SMN_ADDR_LOWER__SHIFT 0x00000000 -#define SMNIF_TLB_15__SMN_ADDR_UPPER__SHIFT 0x00000010 - -// SMNIF_TLV0 -#define SMNIF_TLV0__TLB0__SHIFT 0x00000000 -#define SMNIF_TLV0__TLB1__SHIFT 0x00000004 -#define SMNIF_TLV0__TLB2__SHIFT 0x00000008 -#define SMNIF_TLV0__TLB3__SHIFT 0x0000000c -#define SMNIF_TLV0__TLB4__SHIFT 0x00000010 -#define SMNIF_TLV0__TLB5__SHIFT 0x00000014 -#define SMNIF_TLV0__TLB6__SHIFT 0x00000018 -#define SMNIF_TLV0__TLB7__SHIFT 0x0000001c - -// SMNIF_TLV1 -#define SMNIF_TLV1__TLB8__SHIFT 0x00000000 -#define SMNIF_TLV1__TLB9__SHIFT 0x00000004 -#define SMNIF_TLV1__TLB10__SHIFT 0x00000008 -#define SMNIF_TLV1__TLB11__SHIFT 0x0000000c -#define SMNIF_TLV1__TLB12__SHIFT 0x00000010 -#define SMNIF_TLV1__TLB13__SHIFT 0x00000014 -#define SMNIF_TLV1__TLB14__SHIFT 0x00000018 -#define SMNIF_TLV1__TLB15__SHIFT 0x0000001c - -// SMNIF_TLV2 -#define SMNIF_TLV2__TLB16__SHIFT 0x00000000 -#define SMNIF_TLV2__TLB17__SHIFT 0x00000004 -#define SMNIF_TLV2__TLB18__SHIFT 0x00000008 -#define SMNIF_TLV2__TLB19__SHIFT 0x0000000c -#define SMNIF_TLV2__TLB20__SHIFT 0x00000010 -#define SMNIF_TLV2__TLB21__SHIFT 0x00000014 -#define SMNIF_TLV2__TLB22__SHIFT 0x00000018 -#define SMNIF_TLV2__TLB23__SHIFT 0x0000001c - -// SMNIF_TLV3 -#define SMNIF_TLV3__TLB24__SHIFT 0x00000000 -#define SMNIF_TLV3__TLB25__SHIFT 0x00000004 -#define SMNIF_TLV3__TLB26__SHIFT 0x00000008 -#define SMNIF_TLV3__TLB27__SHIFT 0x0000000c -#define SMNIF_TLV3__TLB28__SHIFT 0x00000010 -#define SMNIF_TLV3__TLB29__SHIFT 0x00000014 -#define SMNIF_TLV3__TLB30__SHIFT 0x00000018 -#define SMNIF_TLV3__TLB31__SHIFT 0x0000001c - -// SMNIF_TLB_QOS -#define SMNIF_TLB_QOS__TLB_QOS__SHIFT 0x00000000 - -// SMNIF_ACC_VIOLATION_LOG_ADDR -#define SMNIF_ACC_VIOLATION_LOG_ADDR__AXI_ADDR__SHIFT 0x00000000 - -// SMNIF_ACC_VIOLATION_LOG_STATUS -#define SMNIF_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define SMNIF_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE__SHIFT 0x00000001 -#define SMNIF_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x00000003 -#define SMNIF_ACC_VIOLATION_LOG_STATUS__AXI_ID__SHIFT 0x00000008 -#define SMNIF_ACC_VIOLATION_LOG_STATUS__AXI_PROT__SHIFT 0x0000001a - -// SMNIF_LPBK_WR_VIOL_ADDR -#define SMNIF_LPBK_WR_VIOL_ADDR__AXI_ADDR__SHIFT 0x00000000 - -// SMNIF_LPBK_WR_VIOL_STATUS -#define SMNIF_LPBK_WR_VIOL_STATUS__VIOL_DET__SHIFT 0x00000000 -#define SMNIF_LPBK_WR_VIOL_STATUS__VIOL_CLEAR__SHIFT 0x00000003 -#define SMNIF_LPBK_WR_VIOL_STATUS__AXI_ID__SHIFT 0x00000008 -#define SMNIF_LPBK_WR_VIOL_STATUS__AXI_PROT__SHIFT 0x0000001a - -// SMNIF_LPBK_RD_VIOL_ADDR -#define SMNIF_LPBK_RD_VIOL_ADDR__AXI_ADDR__SHIFT 0x00000000 - -// SMNIF_LPBK_RD_VIOL_STATUS -#define SMNIF_LPBK_RD_VIOL_STATUS__VIOL_DET__SHIFT 0x00000000 -#define SMNIF_LPBK_RD_VIOL_STATUS__VIOL_CLEAR__SHIFT 0x00000003 -#define SMNIF_LPBK_RD_VIOL_STATUS__AXI_ID__SHIFT 0x00000008 -#define SMNIF_LPBK_RD_VIOL_STATUS__AXI_PROT__SHIFT 0x0000001a - -// SMNIF_MISC_CTRL -#define SMNIF_MISC_CTRL__CLK_GATE_EN__SHIFT 0x00000000 -#define SMNIF_MISC_CTRL__CLK_GATE_OVERRIDE__SHIFT 0x00000001 -#define SMNIF_MISC_CTRL__CLK_GATE_TIMEOUT__SHIFT 0x00000002 -#define SMNIF_MISC_CTRL__REG_CLK_STS__SHIFT 0x00000010 -#define SMNIF_MISC_CTRL__ALLOW_NON_PRIV_REG_ACC__SHIFT 0x00000011 -#define SMNIF_MISC_CTRL__WRITE_REQ_CNT_EN__SHIFT 0x00000012 -#define SMNIF_MISC_CTRL__READ_REQ_CNT_EN__SHIFT 0x00000013 -#define SMNIF_MISC_CTRL__FORCE_INGRESS_PROT__SHIFT 0x00000018 - -// SMNIF_REQ_CNT -#define SMNIF_REQ_CNT__WRITE_REQ_CNT__SHIFT 0x00000000 -#define SMNIF_REQ_CNT__READ_REQ_CNT__SHIFT 0x00000008 - -// SMNIF_SCRATCH0 -#define SMNIF_SCRATCH0__DATA__SHIFT 0x00000000 - -// SMNIF_SCRATCH1 -#define SMNIF_SCRATCH1__DATA__SHIFT 0x00000000 - -// SMNIF_SCRATCH2 -#define SMNIF_SCRATCH2__DATA__SHIFT 0x00000000 - -// SMNIF_SCRATCH3 -#define SMNIF_SCRATCH3__DATA__SHIFT 0x00000000 - -// SMNIF_SECURE_CTRL -#define SMNIF_SECURE_CTRL__ALLOW_NONMP_SRAM_ACCESS__SHIFT 0x00000000 - -// SMNIF_TLVMASK_SECURE -#define SMNIF_TLVMASK_SECURE__TLV0_MASK__SHIFT 0x00000000 -#define SMNIF_TLVMASK_SECURE__TLV1_MASK__SHIFT 0x00000004 -#define SMNIF_TLVMASK_SECURE__TLV2_MASK__SHIFT 0x00000008 -#define SMNIF_TLVMASK_SECURE__TLV3_MASK__SHIFT 0x0000000c -#define SMNIF_TLVMASK_SECURE__TLV4_MASK__SHIFT 0x00000010 -#define SMNIF_TLVMASK_SECURE__TLV5_MASK__SHIFT 0x00000014 -#define SMNIF_TLVMASK_SECURE__TLV6_MASK__SHIFT 0x00000018 -#define SMNIF_TLVMASK_SECURE__TLV7_MASK__SHIFT 0x0000001c - -// SMNIF_TLVMASK_NONSECURE -#define SMNIF_TLVMASK_NONSECURE__TLV0_NSMASK__SHIFT 0x00000000 -#define SMNIF_TLVMASK_NONSECURE__TLV1_NSMASK__SHIFT 0x00000004 -#define SMNIF_TLVMASK_NONSECURE__TLV2_NSMASK__SHIFT 0x00000008 -#define SMNIF_TLVMASK_NONSECURE__TLV3_NSMASK__SHIFT 0x0000000c -#define SMNIF_TLVMASK_NONSECURE__TLV4_NSMASK__SHIFT 0x00000010 -#define SMNIF_TLVMASK_NONSECURE__TLV5_NSMASK__SHIFT 0x00000014 -#define SMNIF_TLVMASK_NONSECURE__TLV6_NSMASK__SHIFT 0x00000018 -#define SMNIF_TLVMASK_NONSECURE__TLV7_NSMASK__SHIFT 0x0000001c - -// SMNIF_TLR_0 -#define SMNIF_TLR_0__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_0__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_0__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_0__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_0__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_0 -#define SMNIF_TLR_ADDR_0__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_0__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_1 -#define SMNIF_TLR_1__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_1__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_1__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_1__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_1__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_1 -#define SMNIF_TLR_ADDR_1__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_1__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_2 -#define SMNIF_TLR_2__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_2__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_2__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_2__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_2__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_2 -#define SMNIF_TLR_ADDR_2__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_2__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_3 -#define SMNIF_TLR_3__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_3__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_3__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_3__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_3__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_3 -#define SMNIF_TLR_ADDR_3__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_3__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_4 -#define SMNIF_TLR_4__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_4__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_4__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_4__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_4__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_4 -#define SMNIF_TLR_ADDR_4__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_4__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_5 -#define SMNIF_TLR_5__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_5__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_5__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_5__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_5__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_5 -#define SMNIF_TLR_ADDR_5__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_5__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_6 -#define SMNIF_TLR_6__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_6__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_6__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_6__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_6__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_6 -#define SMNIF_TLR_ADDR_6__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_6__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_7 -#define SMNIF_TLR_7__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_7__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_7__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_7__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_7__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_7 -#define SMNIF_TLR_ADDR_7__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_7__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_8 -#define SMNIF_TLR_8__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_8__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_8__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_8__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_8__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_8 -#define SMNIF_TLR_ADDR_8__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_8__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_9 -#define SMNIF_TLR_9__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_9__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_9__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_9__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_9__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_9 -#define SMNIF_TLR_ADDR_9__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_9__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_10 -#define SMNIF_TLR_10__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_10__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_10__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_10__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_10__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_10 -#define SMNIF_TLR_ADDR_10__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_10__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_11 -#define SMNIF_TLR_11__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_11__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_11__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_11__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_11__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_11 -#define SMNIF_TLR_ADDR_11__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_11__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_12 -#define SMNIF_TLR_12__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_12__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_12__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_12__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_12__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_12 -#define SMNIF_TLR_ADDR_12__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_12__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_13 -#define SMNIF_TLR_13__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_13__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_13__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_13__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_13__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_13 -#define SMNIF_TLR_ADDR_13__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_13__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_14 -#define SMNIF_TLR_14__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_14__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_14__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_14__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_14__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_14 -#define SMNIF_TLR_ADDR_14__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_14__END_ADDR__SHIFT 0x00000010 - -// SMNIF_TLR_15 -#define SMNIF_TLR_15__MASK__SHIFT 0x00000000 -#define SMNIF_TLR_15__RD_ACC__SHIFT 0x00000008 -#define SMNIF_TLR_15__WR_ACC__SHIFT 0x00000009 -#define SMNIF_TLR_15__SLV_ADDR__SHIFT 0x0000000a -#define SMNIF_TLR_15__VALID__SHIFT 0x0000000f - -// SMNIF_TLR_ADDR_15 -#define SMNIF_TLR_ADDR_15__START_ADDR__SHIFT 0x00000000 -#define SMNIF_TLR_ADDR_15__END_ADDR__SHIFT 0x00000010 - -// MP_ROM_ACC_VIOLATION_LOG_ADDR -#define MP_ROM_ACC_VIOLATION_LOG_ADDR__ADDRESS__SHIFT 0x00000000 - -// MP_ROM_ACC_VIOLATION_LOG_STATUS -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_BLOCK__SHIFT 0x00000001 -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE__SHIFT 0x00000003 -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_PROT__SHIFT 0x00000005 -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_UNIT_ID__SHIFT 0x00000008 -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_INIT_ID__SHIFT 0x0000000e -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ROM_WRITE_DETECTED__SHIFT 0x00000018 -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__UNSECURE_ROM_ACC_DETECTED__SHIFT 0x00000019 -#define MP_ROM_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x0000001f - -// MP_ROM_MISC_CNTL -#define MP_ROM_MISC_CNTL__DISABLE_ROM__SHIFT 0x00000000 -#define MP_ROM_MISC_CNTL__ALLOW_UNPRIVILIGED_REG_ACC__SHIFT 0x00000001 -#define MP_ROM_MISC_CNTL__ALLOW_UNPRIVILIGED_ROM_ACC__SHIFT 0x00000002 -#define MP_ROM_MISC_CNTL__RETURN_ERR_ON_VIOLATED_READ__SHIFT 0x00000003 -#define MP_ROM_MISC_CNTL__HIDE_ROM_KEY__SHIFT 0x00000004 -#define MP_ROM_MISC_CNTL__CLK_GATE_EN__SHIFT 0x00000010 -#define MP_ROM_MISC_CNTL__CLK_GATE_OVERRIDE__SHIFT 0x00000011 -#define MP_ROM_MISC_CNTL__CLK_GATE_TIMEOUT__SHIFT 0x00000012 -#define MP_ROM_MISC_CNTL__REGCLK_STATUS__SHIFT 0x00000016 -#define MP_ROM_MISC_CNTL__SYSCLK_STATUS__SHIFT 0x00000017 - -// MP_ROM_SCRATCH_0 -#define MP_ROM_SCRATCH_0__RESERVED__SHIFT 0x00000000 - -// MP_ROM_SCRATCH_1 -#define MP_ROM_SCRATCH_1__RESERVED__SHIFT 0x00000000 - -// MP_ROM_SCRATCH_2 -#define MP_ROM_SCRATCH_2__RESERVED__SHIFT 0x00000000 - -// MP_ROM_SCRATCH_3 -#define MP_ROM_SCRATCH_3__RESERVED__SHIFT 0x00000000 - -// DMAC_ACC_VIOLATION_LOG_ADDR -#define DMAC_ACC_VIOLATION_LOG_ADDR__AXI_ADDR__SHIFT 0x00000000 - -// DMAC_ACC_VIOLATION_LOG_STATUS -#define DMAC_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_DETECTED__SHIFT 0x00000000 -#define DMAC_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_TYPE__SHIFT 0x00000001 -#define DMAC_ACC_VIOLATION_LOG_STATUS__ACC_VIOLATION_LOG_CLEAR__SHIFT 0x00000003 -#define DMAC_ACC_VIOLATION_LOG_STATUS__AXI_ID__SHIFT 0x00000008 -#define DMAC_ACC_VIOLATION_LOG_STATUS__AXI_APROT__SHIFT 0x0000001a - -// DMAC_MISC_CTRL -#define DMAC_MISC_CTRL__ALLOW_NON_PRIV_REG_ACC__SHIFT 0x00000000 - -// SMUSVI0_PLANE1_LOAD -#define SMUSVI0_PLANE1_LOAD__SVI0_LOADLINE_PLANE1__SHIFT 0x00000000 -#define SMUSVI0_PLANE1_LOAD__SVI0_PSI1_PLANE1__SHIFT 0x00000005 -#define SMUSVI0_PLANE1_LOAD__WAITVIDCOMPDIS__SHIFT 0x0000001e -#define SMUSVI0_PLANE1_LOAD__SVIBUSY__SHIFT 0x0000001f - -// SMUSVI0_PLANE0_LOAD -#define SMUSVI0_PLANE0_LOAD__SVI0_LOADLINE_PLANE0__SHIFT 0x00000000 -#define SMUSVI0_PLANE0_LOAD__SVI0_PSI1_PLANE0__SHIFT 0x00000005 - -// SMUSVI0_TFN -#define SMUSVI0_TFN__SVI0_TFN_PLANE0__SHIFT 0x00000000 -#define SMUSVI0_TFN__SVI0_TFN_PLANE1__SHIFT 0x00000001 - -// SMUSVI0_TEL_PLANE1 -#define SMUSVI0_TEL_PLANE1__SVI0_PLANE1_IDDCOR__SHIFT 0x00000000 -#define SMUSVI0_TEL_PLANE1__SVI0_PLANE1_VDDCOR__SHIFT 0x00000010 - -// SMUSVI0_TEL_PLANE0 -#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x00000000 -#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x00000010 - -// SMUSVI1_TEL_PLANE0 -#define SMUSVI1_TEL_PLANE0__SVI1_PLANE0_IDDCOR__SHIFT 0x00000000 -#define SMUSVI1_TEL_PLANE0__SVI1_PLANE0_VDDCOR__SHIFT 0x00000010 - -// SMUSVI1_PLANE0_LOAD -#define SMUSVI1_PLANE0_LOAD__SVI1_LOADLINE_PLANE0__SHIFT 0x00000000 -#define SMUSVI1_PLANE0_LOAD__SVI1_PSI1_PLANE0__SHIFT 0x00000005 -#define SMUSVI1_PLANE0_LOAD__SVIBUSY1__SHIFT 0x0000001f - -// SMUSVI1_TFN -#define SMUSVI1_TFN__SVI1_TFN_PLANE0__SHIFT 0x00000000 -#define SMUSVI1_TFN__SVI1_TFN_PLANE1__SHIFT 0x00000001 - -// SMUSVI1_PLANE0_PSI0 -#define SMUSVI1_PLANE0_PSI0__SVI1_PLANE0_PSI_VID__SHIFT 0x00000000 -#define SMUSVI1_PLANE0_PSI0__SVI1_PLANE0_PSI_VID_EN__SHIFT 0x00000008 - -// SMUSVI0_MISC_VID_STATUS -#define SMUSVI0_MISC_VID_STATUS__MAX_VID__SHIFT 0x00000000 -#define SMUSVI0_MISC_VID_STATUS__MIN_VID__SHIFT 0x0000000a -#define SMUSVI0_MISC_VID_STATUS__SVI0_PLANE0_PSI_VID__SHIFT 0x00000017 -#define SMUSVI0_MISC_VID_STATUS__SVI0_PLANE0_PSI_VID_EN__SHIFT 0x0000001f - -// SMUSVI0_PWR_CTL_MISC -#define SMUSVI0_PWR_CTL_MISC__SVI0_PLANE1_PSIVID__SHIFT 0x00000000 -#define SMUSVI0_PWR_CTL_MISC__SVI0_PLANE1_PSIVIDEN__SHIFT 0x00000007 -#define SMUSVI0_PWR_CTL_MISC__SVI0_PLANE1_PSIVID_HI__SHIFT 0x00000008 -#define SMUSVI0_PWR_CTL_MISC__SVI2HIGHFREQSEL__SHIFT 0x0000000e - -// SMUSVI0_PLANE_VIDCHG -#define SMUSVI0_PLANE_VIDCHG__SVI0_VIDPLANE__SHIFT 0x00000000 -#define SMUSVI0_PLANE_VIDCHG__SVI0_VIDCHGZEROVID__SHIFT 0x00000005 -#define SMUSVI0_PLANE_VIDCHG__SVI0_VIDCHGRAMP__SHIFT 0x00000006 -#define SMUSVI0_PLANE_VIDCHG__SVI0_VSTIME__SHIFT 0x00000007 -#define SMUSVI0_PLANE_VIDCHG__SVI0_VID__SHIFT 0x00000010 - -// SMUSVI1_PLANE_VIDCHG -#define SMUSVI1_PLANE_VIDCHG__SVI1_VIDPLANE__SHIFT 0x00000000 -#define SMUSVI1_PLANE_VIDCHG__SVI1_VIDCHGZEROVID__SHIFT 0x00000005 -#define SMUSVI1_PLANE_VIDCHG__SVI1_VIDCHGRAMP__SHIFT 0x00000006 -#define SMUSVI1_PLANE_VIDCHG__SVI1_VSTIME__SHIFT 0x00000007 -#define SMUSVI1_PLANE_VIDCHG__SVI1_VID__SHIFT 0x00000010 - -// SMUSVI_WARMRESET_TARGET_VID -#define SMUSVI_WARMRESET_TARGET_VID__SVI0_PLANE0_WARMRESET_TAGET_VID__SHIFT 0x00000000 -#define SMUSVI_WARMRESET_TARGET_VID__SVI0_PLANE1_WARMRESET_TAGET_VID__SHIFT 0x00000008 -#define SMUSVI_WARMRESET_TARGET_VID__SVI1_PLANE0_WARMRESET_TAGET_VID__SHIFT 0x00000010 -#define SMUSVI_WARMRESET_TARGET_VID__SVI1_PLANE1_WARMRESET_TAGET_VID__SHIFT 0x00000018 - -// SMUSVI_WARMRESET_SEL -#define SMUSVI_WARMRESET_SEL__SVI0_PLANE0_WARMRESET_SEL__SHIFT 0x00000000 -#define SMUSVI_WARMRESET_SEL__SVI0_PLANE1_WARMRESET_SEL__SHIFT 0x00000002 -#define SMUSVI_WARMRESET_SEL__SVI1_PLANE0_WARMRESET_SEL__SHIFT 0x00000004 -#define SMUSVI_WARMRESET_SEL__SVI1_PLANE1_WARMRESET_SEL__SHIFT 0x00000006 - -// SMUSVI0_PLANE0_VIDCHGBUSY -#define SMUSVI0_PLANE0_VIDCHGBUSY__SVI0_PLANE0_VID_CHGBUSY__SHIFT 0x00000000 - -// SMUSVI0_PLANE1_VIDCHGBUSY -#define SMUSVI0_PLANE1_VIDCHGBUSY__SVI0_PLANE1_VID_CHGBUSY__SHIFT 0x00000000 - -// SMUSVI1_PLANE0_VIDCHGBUSY -#define SMUSVI1_PLANE0_VIDCHGBUSY__SVI1_PLANE0_VID_CHGBUSY__SHIFT 0x00000000 - -// SMUSVI1_PLANE1_VIDCHGBUSY -#define SMUSVI1_PLANE1_VIDCHGBUSY__SVI1_PLANE1_VID_CHGBUSY__SHIFT 0x00000000 - -// SMUSVI0_PLANE0_CURRENTVID -#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x00000018 - -// SMUSVI1_PLANE0_CURRENTVID -#define SMUSVI1_PLANE0_CURRENTVID__CURRENT_SVI1_PLANE0_VID__SHIFT 0x00000018 - -// SMUSVI0_PLANE1_CURRENTVID -#define SMUSVI0_PLANE1_CURRENTVID__CURRENT_SVI0_PLANE1_VID__SHIFT 0x00000018 - -// SMUSVI_ALL_CPU_IN_CC6 -#define SMUSVI_ALL_CPU_IN_CC6__ALL_CPU_IN_CC6__SHIFT 0x00000000 - -// SMUSVI_BOOTVID -#define SMUSVI_BOOTVID__BOOTSVD_VR0__SHIFT 0x00000000 -#define SMUSVI_BOOTVID__BOOTSVC_VR0__SHIFT 0x00000001 -#define SMUSVI_BOOTVID__BOOTSVD_VR1__SHIFT 0x00000002 -#define SMUSVI_BOOTVID__BOOTSVC_VR1__SHIFT 0x00000003 -#define SMUSVI_BOOTVID__SVI0_PLANE1_STARTUP_COMPL_EN__SHIFT 0x00000008 -#define SMUSVI_BOOTVID__SVI0_PLANE0_STARTUP_COMPL_EN__SHIFT 0x00000009 -#define SMUSVI_BOOTVID__SVI1_PLANE0_STARTUP_COMPL_EN__SHIFT 0x0000000a - -// SMUSVI_STARTUP_VID_COMPLETE -#define SMUSVI_STARTUP_VID_COMPLETE__STARTUP_SVI1_PLANE0_COMPLETE__SHIFT 0x00000000 -#define SMUSVI_STARTUP_VID_COMPLETE__STARTUP_SVI0_PLANE0_COMPLETE__SHIFT 0x00000001 -#define SMUSVI_STARTUP_VID_COMPLETE__STARTUP_SVI0_PLANE1_COMPLETE__SHIFT 0x00000002 - -// SMUSVI_WARM_RESET -#define SMUSVI_WARM_RESET__WARM_RESET__SHIFT 0x00000000 - -// SMUSVI_SVC0 -#define SMUSVI_SVC0__SCHMEN__SHIFT 0x00000001 -#define SMUSVI_SVC0__PU__SHIFT 0x00000002 -#define SMUSVI_SVC0__PD__SHIFT 0x00000003 -#define SMUSVI_SVC0__S0__SHIFT 0x00000006 -#define SMUSVI_SVC0__S1__SHIFT 0x00000007 -#define SMUSVI_SVC0__OE_OVERRIDE__SHIFT 0x00000011 -#define SMUSVI_SVC0__OE__SHIFT 0x00000012 -#define SMUSVI_SVC0__A_OVERRIDE__SHIFT 0x00000013 -#define SMUSVI_SVC0__A__SHIFT 0x00000014 -#define SMUSVI_SVC0__Y__SHIFT 0x0000001f - -// SMUSVI_SVD0 -#define SMUSVI_SVD0__SCHMEN__SHIFT 0x00000001 -#define SMUSVI_SVD0__PU__SHIFT 0x00000002 -#define SMUSVI_SVD0__PD__SHIFT 0x00000003 -#define SMUSVI_SVD0__S0__SHIFT 0x00000006 -#define SMUSVI_SVD0__S1__SHIFT 0x00000007 -#define SMUSVI_SVD0__OE_OVERRIDE__SHIFT 0x00000011 -#define SMUSVI_SVD0__OE__SHIFT 0x00000012 -#define SMUSVI_SVD0__A_OVERRIDE__SHIFT 0x00000013 -#define SMUSVI_SVD0__A__SHIFT 0x00000014 -#define SMUSVI_SVD0__Y__SHIFT 0x0000001f - -// SMUSVI_SVT0 -#define SMUSVI_SVT0__SCHMEN__SHIFT 0x00000000 -#define SMUSVI_SVT0__OE__SHIFT 0x00000001 -#define SMUSVI_SVT0__PU__SHIFT 0x00000002 -#define SMUSVI_SVT0__PD__SHIFT 0x00000003 -#define SMUSVI_SVT0__S0__SHIFT 0x00000006 -#define SMUSVI_SVT0__S1__SHIFT 0x00000007 -#define SMUSVI_SVT0__A__SHIFT 0x00000014 -#define SMUSVI_SVT0__Y__SHIFT 0x0000001f - -// SMUSVI_PLANE_USAGE -#define SMUSVI_PLANE_USAGE__SVI0_PLANE0_USAGE__SHIFT 0x00000000 -#define SMUSVI_PLANE_USAGE__SVI0_PLANE1_USAGE__SHIFT 0x00000001 -#define SMUSVI_PLANE_USAGE__SVI1_PLANE0_USAGE__SHIFT 0x00000002 -#define SMUSVI_PLANE_USAGE__SVI1_PLANE1_USAGE__SHIFT 0x00000003 - -// SMUIO_MCM_CONFIG -#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x00000000 -#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x00000002 -#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x00000005 - -// SMUSVI_STARTUP_VID_EN -#define SMUSVI_STARTUP_VID_EN__STARTUP_VID_EN__SHIFT 0x00000000 - -// SMUSVI_STARTUP_VID_TRIGGER -#define SMUSVI_STARTUP_VID_TRIGGER__STARTUP_VID_TRIGGER__SHIFT 0x00000000 - -// SMUIO_RESET_SEL -#define SMUIO_RESET_SEL__SMUIO_RESET_SEL__SHIFT 0x00000000 - -// SMUIO_MP_RESET_INTR -#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x00000000 - -// SMUIO_RESET_DELAY -#define SMUIO_RESET_DELAY__SMUIO_RESET_DELAY__SHIFT 0x00000000 - -// ROM_CNTL -#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x00000000 - -// PAGE_MIRROR_CNTL -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x00000000 -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x00000018 -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x00000019 -#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x0000001a - -// ROM_STATUS -#define ROM_STATUS__ROM_BUSY__SHIFT 0x00000000 - -// CGTT_ROM_CLK_CTRL0 -#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 -#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// ROM_INDEX -#define ROM_INDEX__ROM_INDEX__SHIFT 0x00000000 - -// ROM_DATA -#define ROM_DATA__ROM_DATA__SHIFT 0x00000000 - -// ROM_START -#define ROM_START__ROM_START__SHIFT 0x00000000 - -// ROM_SW_CNTL -#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x00000000 -#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x00000010 -#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x00000012 - -// ROM_SW_STATUS -#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x00000000 - -// ROM_SW_COMMAND -#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x00000000 -#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x00000008 - -// ROM_SW_DATA_1 -#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_2 -#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_3 -#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_4 -#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_5 -#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_6 -#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_7 -#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_8 -#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_9 -#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_10 -#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_11 -#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_12 -#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_13 -#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_14 -#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_15 -#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_16 -#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_17 -#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_18 -#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_19 -#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_20 -#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_21 -#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_22 -#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_23 -#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_24 -#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_25 -#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_26 -#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_27 -#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_28 -#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_29 -#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_30 -#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_31 -#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_32 -#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_33 -#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_34 -#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_35 -#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_36 -#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_37 -#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_38 -#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_39 -#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_40 -#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_41 -#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_42 -#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_43 -#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_44 -#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_45 -#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_46 -#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_47 -#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_48 -#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_49 -#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_50 -#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_51 -#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_52 -#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_53 -#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_54 -#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_55 -#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_56 -#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_57 -#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_58 -#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_59 -#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_60 -#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_61 -#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_62 -#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_63 -#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x00000000 - -// ROM_SW_DATA_64 -#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x00000000 - -// SMU_GPIOPAD_SW_INT_STAT -#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000 - -// SMU_GPIOPAD_MASK -#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000 - -// SMU_GPIOPAD_A -#define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x00000000 - -// SMU_GPIOPAD_TXIMPSEL -#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x00000000 - -// SMU_GPIOPAD_EN -#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000 - -// SMU_GPIOPAD_Y -#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000 - -// SMU_GPIOPAD_RXEN -#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x00000000 - -// SMU_GPIOPAD_RCVR_SEL0 -#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x00000000 - -// SMU_GPIOPAD_RCVR_SEL1 -#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x00000000 - -// SMU_GPIOPAD_PU_EN -#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000 - -// SMU_GPIOPAD_PD_EN -#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000 - -// SMU_GPIOPAD_PINSTRAPS -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019 -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d -#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e - -// SMU_GPIOPAD_INT_STAT_EN -#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000 -#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f - -// SMU_GPIOPAD_INT_STAT -#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000 -#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f - -// SMU_GPIOPAD_INT_STAT_AK -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019 -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b -#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c -#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f - -// SMU_GPIOPAD_INT_EN -#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000 -#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f - -// SMU_GPIOPAD_INT_TYPE -#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000 -#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f - -// SMU_GPIOPAD_INT_POLARITY -#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000 -#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f - -// ROM_CC_BIF_PINSTRAP -#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x00000000 -#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_PIN__SHIFT 0x00000001 -#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x00000004 -#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x00000007 -#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x00000008 -#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x00000009 -#define ROM_CC_BIF_PINSTRAP__BIF_TX_HALF_SWING__SHIFT 0x0000000a - -// IO_SMUIO_PINSTRAP -#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x00000000 -#define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x00000003 -#define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x00000005 -#define IO_SMUIO_PINSTRAP__TX_DEEMPH_EN__SHIFT 0x00000008 - -// SMUIO_PCC_CONTROL -#define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x00000000 - -// SMUIO_PCC_GPIO_SELECT -#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x00000000 - -// SMUIO_GPIO_INT_SELECT -#define SMUIO_GPIO_INT_SELECT__GPIO_INT_SELECT__SHIFT 0x00000000 - -// SMIO_INDEX -#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x00000000 - -// S0_VID_SMIO_CNTL -#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x00000000 - -// S1_VID_SMIO_CNTL -#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x00000000 - -// OPEN_DRAIN_SELECT -#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x00000000 -#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x0000001f - -// SMIO_ENABLE -#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x00000000 - -// CPL_VDDCR_SOC_IDLE -#define CPL_VDDCR_SOC_IDLE__CPL_VDDCR_SOC_IDLE__SHIFT 0x00000000 - -// ROM_SW_SECURE -#define ROM_SW_SECURE__ROM_WR_ACCESS_DISABLE__SHIFT 0x00000000 - -// GDS_CONFIG -#define GDS_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x00000001 -#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003 -#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005 -#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x00000007 - -// GDS_CNTL_STATUS -#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x00000000 -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x00000001 -#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x00000002 -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x00000003 -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x00000004 -#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005 -#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x00000006 -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x00000007 -#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x00000008 -#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x00000009 -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0x0000000a -#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0x0000000b -#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0x0000000c -#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0x0000000d -#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0x0000000e - -// GDS_ENHANCE2 -#define GDS_ENHANCE2__MISC__SHIFT 0x00000000 -#define GDS_ENHANCE2__UNUSED__SHIFT 0x00000010 - -// GDS_PROTECTION_FAULT -#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x00000000 -#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x00000001 -#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x00000002 -#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x00000003 -#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x00000006 -#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0x0000000a -#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0x0000000c -#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x00000010 - -// GDS_VM_PROTECTION_FAULT -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x00000000 -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x00000001 -#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x00000002 -#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x00000003 -#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x00000004 -#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x00000005 -#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x00000008 -#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x00000010 - -// GDS_EDC_CNT -#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x00000000 -#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x00000002 -#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x00000004 -#define GDS_EDC_CNT__UNUSED__SHIFT 0x00000006 - -// GDS_EDC_GRBM_CNT -#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x00000000 -#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x00000002 -#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x00000004 - -// GDS_EDC_OA_DED -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x00000000 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x00000001 -#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x00000002 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x00000003 -#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x00000004 -#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x00000005 -#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x00000006 -#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x00000007 -#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x00000008 -#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x00000009 -#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0x0000000a -#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0x0000000b -#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0x0000000c - -// GDS_DEBUG_CNTL -#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x00000000 -#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x00000005 - -// GDS_DEBUG_DATA -#define GDS_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// GDS_DSM_CNTL -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x00000000 -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x00000001 -#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x00000003 -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x00000004 -#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x00000006 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x00000007 -#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x00000009 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0x0000000a -#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000b -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0x0000000c -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0x0000000d -#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000e -#define GDS_DSM_CNTL__UNUSED__SHIFT 0x0000000f - -// GDS_EDC_OA_PHY_CNT -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x00000000 -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x00000002 -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x00000004 -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x00000006 -#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x00000008 -#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0x0000000a - -// GDS_EDC_OA_PIPE_CNT -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x00000000 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x00000002 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x00000004 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x00000006 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x00000008 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0x0000000a -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0x0000000c -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0x0000000e -#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x00000010 - -// GDS_DSM_CNTL2 -#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define GDS_DSM_CNTL2__UNUSED__SHIFT 0x0000000f -#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x0000001a - -// GDS_WD_GDS_CSB -#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x00000000 -#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0x0000000d - -// GDS_VMID0_BASE -#define GDS_VMID0_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID1_BASE -#define GDS_VMID1_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID2_BASE -#define GDS_VMID2_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID3_BASE -#define GDS_VMID3_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID4_BASE -#define GDS_VMID4_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID5_BASE -#define GDS_VMID5_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID6_BASE -#define GDS_VMID6_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID7_BASE -#define GDS_VMID7_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID8_BASE -#define GDS_VMID8_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID9_BASE -#define GDS_VMID9_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID10_BASE -#define GDS_VMID10_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID11_BASE -#define GDS_VMID11_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID12_BASE -#define GDS_VMID12_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID13_BASE -#define GDS_VMID13_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID14_BASE -#define GDS_VMID14_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID15_BASE -#define GDS_VMID15_BASE__BASE__SHIFT 0x00000000 - -// GDS_VMID0_SIZE -#define GDS_VMID0_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID1_SIZE -#define GDS_VMID1_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID2_SIZE -#define GDS_VMID2_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID3_SIZE -#define GDS_VMID3_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID4_SIZE -#define GDS_VMID4_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID5_SIZE -#define GDS_VMID5_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID6_SIZE -#define GDS_VMID6_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID7_SIZE -#define GDS_VMID7_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID8_SIZE -#define GDS_VMID8_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID9_SIZE -#define GDS_VMID9_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID10_SIZE -#define GDS_VMID10_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID11_SIZE -#define GDS_VMID11_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID12_SIZE -#define GDS_VMID12_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID13_SIZE -#define GDS_VMID13_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID14_SIZE -#define GDS_VMID14_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_VMID15_SIZE -#define GDS_VMID15_SIZE__SIZE__SHIFT 0x00000000 - -// GDS_GWS_VMID0 -#define GDS_GWS_VMID0__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID0__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID1 -#define GDS_GWS_VMID1__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID1__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID2 -#define GDS_GWS_VMID2__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID2__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID3 -#define GDS_GWS_VMID3__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID3__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID4 -#define GDS_GWS_VMID4__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID4__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID5 -#define GDS_GWS_VMID5__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID5__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID6 -#define GDS_GWS_VMID6__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID6__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID7 -#define GDS_GWS_VMID7__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID7__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID8 -#define GDS_GWS_VMID8__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID8__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID9 -#define GDS_GWS_VMID9__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID9__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID10 -#define GDS_GWS_VMID10__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID10__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID11 -#define GDS_GWS_VMID11__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID11__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID12 -#define GDS_GWS_VMID12__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID12__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID13 -#define GDS_GWS_VMID13__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID13__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID14 -#define GDS_GWS_VMID14__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID14__SIZE__SHIFT 0x00000010 - -// GDS_GWS_VMID15 -#define GDS_GWS_VMID15__BASE__SHIFT 0x00000000 -#define GDS_GWS_VMID15__SIZE__SHIFT 0x00000010 - -// GDS_OA_VMID0 -#define GDS_OA_VMID0__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID0__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID1 -#define GDS_OA_VMID1__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID1__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID2 -#define GDS_OA_VMID2__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID2__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID3 -#define GDS_OA_VMID3__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID3__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID4 -#define GDS_OA_VMID4__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID4__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID5 -#define GDS_OA_VMID5__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID5__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID6 -#define GDS_OA_VMID6__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID6__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID7 -#define GDS_OA_VMID7__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID7__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID8 -#define GDS_OA_VMID8__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID8__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID9 -#define GDS_OA_VMID9__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID9__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID10 -#define GDS_OA_VMID10__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID10__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID11 -#define GDS_OA_VMID11__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID11__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID12 -#define GDS_OA_VMID12__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID12__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID13 -#define GDS_OA_VMID13__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID13__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID14 -#define GDS_OA_VMID14__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID14__UNUSED__SHIFT 0x00000010 - -// GDS_OA_VMID15 -#define GDS_OA_VMID15__MASK__SHIFT 0x00000000 -#define GDS_OA_VMID15__UNUSED__SHIFT 0x00000010 - -// GDS_GWS_RESET0 -#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x00000000 -#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x00000001 -#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x00000002 -#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x00000003 -#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x00000004 -#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x00000005 -#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x00000006 -#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x00000007 -#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x00000008 -#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x00000009 -#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0x0000000a -#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0x0000000b -#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0x0000000c -#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0x0000000d -#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0x0000000e -#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0x0000000f -#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x00000010 -#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x00000011 -#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x00000012 -#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x00000013 -#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x00000014 -#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x00000015 -#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x00000016 -#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x00000017 -#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x00000018 -#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x00000019 -#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x0000001a -#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x0000001b -#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x0000001c -#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x0000001d -#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x0000001e -#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x0000001f - -// GDS_GWS_RESET1 -#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x00000000 -#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x00000001 -#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x00000002 -#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x00000003 -#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x00000004 -#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x00000005 -#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x00000006 -#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x00000007 -#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x00000008 -#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x00000009 -#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0x0000000a -#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0x0000000b -#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0x0000000c -#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0x0000000d -#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0x0000000e -#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0x0000000f -#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x00000010 -#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x00000011 -#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x00000012 -#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x00000013 -#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x00000014 -#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x00000015 -#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x00000016 -#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x00000017 -#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x00000018 -#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x00000019 -#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x0000001a -#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x0000001b -#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x0000001c -#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x0000001d -#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x0000001e -#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x0000001f - -// GDS_GWS_RESOURCE_RESET -#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x00000000 -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x00000008 - -// GDS_COMPUTE_MAX_WAVE_ID -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 - -// GDS_OA_RESET_MASK -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x00000000 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x00000001 -#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x00000002 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x00000003 -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x00000004 -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x00000005 -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x00000006 -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x00000007 -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x00000008 -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x00000009 -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0x0000000a -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0x0000000b -#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0x0000000c - -// GDS_OA_RESET -#define GDS_OA_RESET__RESET__SHIFT 0x00000000 -#define GDS_OA_RESET__PIPE_ID__SHIFT 0x00000008 - -// GDS_ENHANCE -#define GDS_ENHANCE__MISC__SHIFT 0x00000000 -#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x00000010 -#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x00000011 -#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x00000012 -#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x00000013 -#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x00000014 -#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x00000015 -#define GDS_ENHANCE__UNUSED__SHIFT 0x00000016 - -// GDS_OA_CGPG_RESTORE -#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x00000000 -#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x00000008 -#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0x0000000c -#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x00000010 -#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x00000014 - -// GDS_CS_CTXSW_STATUS -#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x00000000 -#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x00000001 -#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x00000002 - -// GDS_CS_CTXSW_CNT0 -#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_CS_CTXSW_CNT1 -#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_CS_CTXSW_CNT2 -#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_CS_CTXSW_CNT3 -#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_GFX_CTXSW_STATUS -#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x00000000 -#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x00000001 -#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x00000002 - -// GDS_VS_CTXSW_CNT0 -#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_VS_CTXSW_CNT1 -#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_VS_CTXSW_CNT2 -#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_VS_CTXSW_CNT3 -#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS0_CTXSW_CNT0 -#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS1_CTXSW_CNT0 -#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS2_CTXSW_CNT0 -#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS3_CTXSW_CNT0 -#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS4_CTXSW_CNT0 -#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS5_CTXSW_CNT0 -#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS6_CTXSW_CNT0 -#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS7_CTXSW_CNT0 -#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_PS0_CTXSW_CNT1 -#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS1_CTXSW_CNT1 -#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS2_CTXSW_CNT1 -#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS3_CTXSW_CNT1 -#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS4_CTXSW_CNT1 -#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS5_CTXSW_CNT1 -#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS6_CTXSW_CNT1 -#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS7_CTXSW_CNT1 -#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_PS0_CTXSW_CNT2 -#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS1_CTXSW_CNT2 -#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS2_CTXSW_CNT2 -#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS3_CTXSW_CNT2 -#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS4_CTXSW_CNT2 -#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS5_CTXSW_CNT2 -#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS6_CTXSW_CNT2 -#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS7_CTXSW_CNT2 -#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_PS0_CTXSW_CNT3 -#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS1_CTXSW_CNT3 -#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS2_CTXSW_CNT3 -#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS3_CTXSW_CNT3 -#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS4_CTXSW_CNT3 -#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS5_CTXSW_CNT3 -#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS6_CTXSW_CNT3 -#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_PS7_CTXSW_CNT3 -#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_GS_CTXSW_CNT0 -#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x00000000 -#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x00000010 - -// GDS_GS_CTXSW_CNT1 -#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x00000000 -#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x00000010 - -// GDS_GS_CTXSW_CNT2 -#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x00000000 -#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x00000010 - -// GDS_GS_CTXSW_CNT3 -#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x00000000 -#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x00000010 - -// GDS_RD_ADDR -#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x00000000 - -// GDS_RD_DATA -#define GDS_RD_DATA__READ_DATA__SHIFT 0x00000000 - -// GDS_RD_BURST_ADDR -#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x00000000 - -// GDS_RD_BURST_COUNT -#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x00000000 - -// GDS_RD_BURST_DATA -#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x00000000 - -// GDS_WR_ADDR -#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x00000000 - -// GDS_WR_DATA -#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x00000000 - -// GDS_WR_BURST_ADDR -#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x00000000 - -// GDS_WR_BURST_DATA -#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x00000000 - -// GDS_WRITE_COMPLETE -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x00000000 - -// GDS_ATOM_CNTL -#define GDS_ATOM_CNTL__AINC__SHIFT 0x00000000 -#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x00000006 -#define GDS_ATOM_CNTL__DMODE__SHIFT 0x00000008 -#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x0000000a - -// GDS_ATOM_COMPLETE -#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x00000000 -#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x00000001 - -// GDS_ATOM_BASE -#define GDS_ATOM_BASE__BASE__SHIFT 0x00000000 -#define GDS_ATOM_BASE__UNUSED__SHIFT 0x00000010 - -// GDS_ATOM_SIZE -#define GDS_ATOM_SIZE__SIZE__SHIFT 0x00000000 -#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x00000010 - -// GDS_ATOM_OFFSET0 -#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x00000000 -#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x00000008 - -// GDS_ATOM_OFFSET1 -#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x00000000 -#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x00000008 - -// GDS_ATOM_DST -#define GDS_ATOM_DST__DST__SHIFT 0x00000000 - -// GDS_ATOM_OP -#define GDS_ATOM_OP__OP__SHIFT 0x00000000 -#define GDS_ATOM_OP__UNUSED__SHIFT 0x00000008 - -// GDS_ATOM_SRC0 -#define GDS_ATOM_SRC0__DATA__SHIFT 0x00000000 - -// GDS_ATOM_SRC0_U -#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x00000000 - -// GDS_ATOM_SRC1 -#define GDS_ATOM_SRC1__DATA__SHIFT 0x00000000 - -// GDS_ATOM_SRC1_U -#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x00000000 - -// GDS_ATOM_READ0 -#define GDS_ATOM_READ0__DATA__SHIFT 0x00000000 - -// GDS_ATOM_READ0_U -#define GDS_ATOM_READ0_U__DATA__SHIFT 0x00000000 - -// GDS_ATOM_READ1 -#define GDS_ATOM_READ1__DATA__SHIFT 0x00000000 - -// GDS_ATOM_READ1_U -#define GDS_ATOM_READ1_U__DATA__SHIFT 0x00000000 - -// GDS_GWS_RESOURCE_CNTL -#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x00000000 -#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x00000006 - -// GDS_GWS_RESOURCE -#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x00000000 -#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x00000001 -#define GDS_GWS_RESOURCE__TYPE__SHIFT 0x0000000d -#define GDS_GWS_RESOURCE__DED__SHIFT 0x0000000e -#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x0000000f -#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x00000010 -#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x0000001c -#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x0000001d -#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x0000001e -#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x0000001f - -// GDS_GWS_RESOURCE_CNT -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x00000000 -#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x00000010 - -// GDS_OA_CNTL -#define GDS_OA_CNTL__INDEX__SHIFT 0x00000000 -#define GDS_OA_CNTL__UNUSED__SHIFT 0x00000004 - -// GDS_OA_COUNTER -#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x00000000 - -// GDS_OA_ADDRESS -#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x00000000 -#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x00000010 -#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x00000014 -#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x00000016 -#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x0000001e -#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x0000001f - -// GDS_OA_INCDEC -#define GDS_OA_INCDEC__VALUE__SHIFT 0x00000000 -#define GDS_OA_INCDEC__INCDEC__SHIFT 0x0000001f - -// GDS_OA_RING_SIZE -#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x00000000 - -// GDS_PERFCOUNTER0_LO -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GDS_PERFCOUNTER1_LO -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GDS_PERFCOUNTER2_LO -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GDS_PERFCOUNTER3_LO -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GDS_PERFCOUNTER0_HI -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GDS_PERFCOUNTER1_HI -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GDS_PERFCOUNTER2_HI -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GDS_PERFCOUNTER3_HI -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GDS_PERFCOUNTER0_SELECT -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// GDS_PERFCOUNTER1_SELECT -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// GDS_PERFCOUNTER2_SELECT -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// GDS_PERFCOUNTER3_SELECT -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// GDS_PERFCOUNTER0_SELECT1 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a - -// CGTT_GDS_CLK_CTRL -#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// GDS_DEBUG_REG0 -#define GDS_DEBUG_REG0__spare1__SHIFT 0x00000000 -#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x00000006 -#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x00000007 -#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0x0000000c -#define GDS_DEBUG_REG0__cstate__SHIFT 0x0000000d -#define GDS_DEBUG_REG0__buff_write__SHIFT 0x00000011 -#define GDS_DEBUG_REG0__flush_request__SHIFT 0x00000012 -#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x00000013 -#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x00000014 -#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x00000015 -#define GDS_DEBUG_REG0__spare__SHIFT 0x00000016 - -// GDS_DEBUG_REG1 -#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x00000000 -#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x00000001 -#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x00000002 -#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x00000011 -#define GDS_DEBUG_REG1__data_ready__SHIFT 0x00000012 -#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x00000013 -#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x00000014 -#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x00000015 -#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x00000016 -#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x00000017 -#define GDS_DEBUG_REG1__spare__SHIFT 0x00000018 - -// GDS_DEBUG_REG2 -#define GDS_DEBUG_REG2__ds_full__SHIFT 0x00000000 -#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x00000001 -#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x00000002 -#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x00000003 -#define GDS_DEBUG_REG2__app_sel__SHIFT 0x00000004 -#define GDS_DEBUG_REG2__req__SHIFT 0x00000008 -#define GDS_DEBUG_REG2__spare__SHIFT 0x00000017 - -// GDS_DEBUG_REG3 -#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x00000000 -#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0x0000000b -#define GDS_DEBUG_REG3__spare__SHIFT 0x0000000f - -// GDS_DEBUG_REG4 -#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x00000000 -#define GDS_DEBUG_REG4__gws_req__SHIFT 0x00000001 -#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x00000002 -#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x00000003 -#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x00000009 -#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0x0000000a -#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0x0000000b -#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0x0000000c -#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0x0000000d -#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0x0000000e -#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0x0000000f -#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x00000010 -#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x00000011 -#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x00000012 -#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x00000013 -#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x00000014 -#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x00000015 -#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x00000016 -#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x00000017 -#define GDS_DEBUG_REG4__spare__SHIFT 0x00000018 - -// GDS_DEBUG_REG5 -#define GDS_DEBUG_REG5__write_dis__SHIFT 0x00000000 -#define GDS_DEBUG_REG5__dec_error__SHIFT 0x00000001 -#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x00000002 -#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x00000003 -#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x00000004 -#define GDS_DEBUG_REG5__spare__SHIFT 0x00000005 -#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x00000008 -#define GDS_DEBUG_REG5__spare1__SHIFT 0x00000016 - -// GDS_DEBUG_REG6 -#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x00000000 -#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x00000001 -#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x00000005 -#define GDS_DEBUG_REG6__spare__SHIFT 0x00000015 - -// GDS_DEBUG_REG7 -#define GDS_DEBUG_REG7__csb_inc_total__SHIFT 0x00000000 - -// GDS_DEBUG_REG8 -#define GDS_DEBUG_REG8__csb_dec_total__SHIFT 0x00000000 - -// CB_HW_CONTROL -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000 -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006 -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010 -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x00000012 -#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013 -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x00000015 -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016 -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f - -// CB_HW_CONTROL_1 -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000 -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005 -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011 -#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x0000001a - -// CB_HW_CONTROL_2 -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000 -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008 -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x00000018 -#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x0000001c - -// CB_HW_CONTROL_3 -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x00000000 -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x00000001 -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x00000002 -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x00000003 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x00000004 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x00000005 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x00000006 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x00000007 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x00000008 -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x00000009 -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0x0000000a -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0x0000000b -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0x0000000c -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0x0000000d -#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0x0000000e -#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0x0000000f -#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x00000010 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x00000011 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x00000012 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x00000013 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x00000014 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x00000015 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x00000016 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x00000017 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x00000018 -#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x00000019 -#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x0000001a -#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x0000001b -#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x0000001c - -// CB_HW_MEM_ARBITER_RD -#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x00000000 -#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x00000002 -#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x00000006 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0x0000000a -#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0x0000000c -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0x0000000e -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x00000010 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x00000012 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x00000014 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x00000016 -#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x00000017 -#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x0000001a -#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x0000001d - -// CB_HW_MEM_ARBITER_WR -#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x00000000 -#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x00000002 -#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x00000006 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0x0000000a -#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0x0000000c -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0x0000000e -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x00000010 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x00000012 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x00000014 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x00000016 -#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x00000017 -#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x0000001a -#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x0000001d - -// CB_DCC_CONFIG -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x00000000 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000005 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x00000006 -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x00000008 -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x00000010 -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x00000018 -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x0000001c - -// CB_DEBUG_BUS_1 - -// CB_DEBUG_BUS_2 - -// CB_DEBUG_BUS_3 - -// CB_DEBUG_BUS_4 - -// CB_DEBUG_BUS_5 - -// CB_DEBUG_BUS_6 - -// CB_DEBUG_BUS_7 - -// CB_DEBUG_BUS_8 - -// CB_DEBUG_BUS_9 - -// CB_DEBUG_BUS_10 - -// CB_DEBUG_BUS_11 - -// CB_DEBUG_BUS_12 - -// CB_DEBUG_BUS_13 - -// CB_DEBUG_BUS_14 - -// CB_DEBUG_BUS_15 - -// CB_DEBUG_BUS_16 - -// CB_DEBUG_BUS_17 -#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x00000000 -#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x00000001 -#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x00000002 -#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x00000003 -#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x00000004 -#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x00000005 -#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x00000006 -#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x00000007 -#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x00000008 -#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x00000009 -#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0x0000000a -#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0x0000000b - -// CB_DEBUG_BUS_18 -#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x00000000 -#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x00000001 -#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x00000002 -#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x00000003 -#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x00000004 -#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x00000005 -#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x00000006 -#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x00000007 -#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x00000008 -#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x00000009 -#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0x0000000a -#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0x0000000b -#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0x0000000c -#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0x0000000d -#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0x0000000e -#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0x0000000f -#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x00000010 -#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x00000011 -#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x00000012 -#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x00000013 -#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x00000014 -#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x00000015 - -// CB_DEBUG_BUS_19 -#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x00000000 -#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x00000002 -#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x00000003 -#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x00000004 -#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x00000005 -#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x00000006 -#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x00000007 -#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x00000008 -#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x00000009 -#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0x0000000a -#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0x0000000b -#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0x0000000c -#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0x0000000d -#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0x0000000e -#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0x0000000f -#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x00000010 -#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x00000011 -#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x00000012 - -// CB_DEBUG_BUS_20 -#define CB_DEBUG_BUS_20__RDREQ_CM_FIFO_EMPTY__SHIFT 0x00000000 -#define CB_DEBUG_BUS_20__RDREQ_DC_FIFO_EMPTY__SHIFT 0x00000001 -#define CB_DEBUG_BUS_20__RDREQ_FC_FIFO_EMPTY__SHIFT 0x00000002 -#define CB_DEBUG_BUS_20__RDREQ_CC_FIFO_EMPTY__SHIFT 0x00000003 -#define CB_DEBUG_BUS_20__RDREQ_RMI_FIFO_EMPTY__SHIFT 0x00000004 -#define CB_DEBUG_BUS_20__RDREQ_CREDITS_USED__SHIFT 0x00000005 -#define CB_DEBUG_BUS_20__WRREQ_CM_FIFO_EMPTY__SHIFT 0x0000000c -#define CB_DEBUG_BUS_20__WRREQ_DC_FIFO_EMPTY__SHIFT 0x0000000d -#define CB_DEBUG_BUS_20__WRREQ_FC_FIFO_EMPTY__SHIFT 0x0000000e -#define CB_DEBUG_BUS_20__WRREQ_CC_FIFO_EMPTY__SHIFT 0x0000000f -#define CB_DEBUG_BUS_20__WRREQ_RMI_FIFO_EMPTY__SHIFT 0x00000010 -#define CB_DEBUG_BUS_20__WRREQ_CREDITS_USED__SHIFT 0x00000011 - -// CB_DEBUG_BUS_21 -#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x00000000 -#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x00000001 -#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x00000002 -#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x00000003 -#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x00000004 -#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x00000005 -#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x00000006 -#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x00000007 - -// CB_DEBUG_BUS_22 -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x00000000 -#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0x0000000c - -// CB_BLEND_RED -#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 - -// CB_BLEND_GREEN -#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 - -// CB_BLEND_BLUE -#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 - -// CB_BLEND_ALPHA -#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 - -// CB_DCC_CONTROL -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x00000001 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x00000002 - -// CB_COLOR_CONTROL -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x00000000 -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003 -#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004 -#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010 - -// CB_BLEND0_CONTROL -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_BLEND1_CONTROL -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_BLEND2_CONTROL -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_BLEND3_CONTROL -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_BLEND4_CONTROL -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_BLEND5_CONTROL -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_BLEND6_CONTROL -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_BLEND7_CONTROL -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d -#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e -#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f - -// CB_MRT0_EPITCH -#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_MRT1_EPITCH -#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_MRT2_EPITCH -#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_MRT3_EPITCH -#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_MRT4_EPITCH -#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_MRT5_EPITCH -#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_MRT6_EPITCH -#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_MRT7_EPITCH -#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x00000000 - -// CB_COLOR0_BASE -#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_BASE -#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_BASE -#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_BASE -#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_BASE -#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_BASE -#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_BASE -#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_BASE -#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR0_BASE_EXT -#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_BASE_EXT -#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_BASE_EXT -#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_BASE_EXT -#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_BASE_EXT -#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_BASE_EXT -#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_BASE_EXT -#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_BASE_EXT -#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR0_ATTRIB2 -#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR1_ATTRIB2 -#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR2_ATTRIB2 -#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR3_ATTRIB2 -#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR4_ATTRIB2 -#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR5_ATTRIB2 -#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR6_ATTRIB2 -#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR7_ATTRIB2 -#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x00000000 -#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0x0000000e -#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x0000001c - -// CB_COLOR0_VIEW -#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR1_VIEW -#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR2_VIEW -#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR3_VIEW -#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR4_VIEW -#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR5_VIEW -#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR6_VIEW -#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR7_VIEW -#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000 -#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x00000018 - -// CB_COLOR0_INFO -#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR1_INFO -#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR2_INFO -#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR3_INFO -#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR4_INFO -#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR5_INFO -#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR6_INFO -#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR7_INFO -#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000 -#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002 -#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008 -#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b -#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d -#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e -#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f -#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010 -#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 -#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012 -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x0000001b -#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x0000001c -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x0000001d - -// CB_COLOR0_ATTRIB -#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR1_ATTRIB -#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR2_ATTRIB -#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR3_ATTRIB -#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR4_ATTRIB -#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR5_ATTRIB -#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR6_ATTRIB -#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR7_ATTRIB -#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x00000000 -#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0x0000000b -#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 -#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x00000012 -#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x00000017 -#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x0000001c -#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x0000001e -#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x0000001f - -// CB_COLOR0_DCC_CONTROL -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR1_DCC_CONTROL -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR2_DCC_CONTROL -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR3_DCC_CONTROL -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR4_DCC_CONTROL -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR5_DCC_CONTROL -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR6_DCC_CONTROL -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR7_DCC_CONTROL -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x00000000 -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x00000001 -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x00000002 -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000004 -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x00000005 -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x00000007 -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x00000009 -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0x0000000a -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0x0000000e - -// CB_COLOR0_CMASK -#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_CMASK -#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_CMASK -#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_CMASK -#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_CMASK -#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_CMASK -#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_CMASK -#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_CMASK -#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR0_CMASK_BASE_EXT -#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_CMASK_BASE_EXT -#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_CMASK_BASE_EXT -#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_CMASK_BASE_EXT -#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_CMASK_BASE_EXT -#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_CMASK_BASE_EXT -#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_CMASK_BASE_EXT -#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_CMASK_BASE_EXT -#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR0_FMASK -#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_FMASK -#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_FMASK -#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_FMASK -#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_FMASK -#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_FMASK -#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_FMASK -#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_FMASK -#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR0_FMASK_BASE_EXT -#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_FMASK_BASE_EXT -#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_FMASK_BASE_EXT -#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_FMASK_BASE_EXT -#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_FMASK_BASE_EXT -#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_FMASK_BASE_EXT -#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_FMASK_BASE_EXT -#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_FMASK_BASE_EXT -#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR0_CLEAR_WORD0 -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR1_CLEAR_WORD0 -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR2_CLEAR_WORD0 -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR3_CLEAR_WORD0 -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR4_CLEAR_WORD0 -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR5_CLEAR_WORD0 -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR6_CLEAR_WORD0 -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR7_CLEAR_WORD0 -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 - -// CB_COLOR0_CLEAR_WORD1 -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR1_CLEAR_WORD1 -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR2_CLEAR_WORD1 -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR3_CLEAR_WORD1 -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR4_CLEAR_WORD1 -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR5_CLEAR_WORD1 -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR6_CLEAR_WORD1 -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR7_CLEAR_WORD1 -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 - -// CB_COLOR0_DCC_BASE -#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_DCC_BASE -#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_DCC_BASE -#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_DCC_BASE -#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_DCC_BASE -#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_DCC_BASE -#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_DCC_BASE -#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_DCC_BASE -#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR0_DCC_BASE_EXT -#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR1_DCC_BASE_EXT -#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR2_DCC_BASE_EXT -#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR3_DCC_BASE_EXT -#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR4_DCC_BASE_EXT -#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR5_DCC_BASE_EXT -#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR6_DCC_BASE_EXT -#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_COLOR7_DCC_BASE_EXT -#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x00000000 - -// CB_TARGET_MASK -#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000 -#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004 -#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008 -#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c -#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010 -#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014 -#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018 -#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c - -// CB_SHADER_MASK -#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000 -#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004 -#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008 -#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c -#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010 -#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014 -#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018 -#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c - -// CB_PERFCOUNTER0_LO -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CB_PERFCOUNTER1_LO -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CB_PERFCOUNTER2_LO -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CB_PERFCOUNTER3_LO -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CB_PERFCOUNTER0_HI -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CB_PERFCOUNTER1_HI -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CB_PERFCOUNTER2_HI -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CB_PERFCOUNTER3_HI -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CB_PERFCOUNTER_FILTER -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x00000000 -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x00000001 -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x00000004 -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x00000005 -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0x0000000a -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0x0000000b -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0x0000000c -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0x0000000d -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x00000011 -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x00000012 -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x00000015 -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x00000016 - -// CB_PERFCOUNTER0_SELECT -#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// CB_PERFCOUNTER0_SELECT1 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// CB_PERFCOUNTER1_SELECT -#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// CB_PERFCOUNTER2_SELECT -#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// CB_PERFCOUNTER3_SELECT -#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// CB_CGTT_SCLK_CTRL -#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// GC_CAC_CTRL_1 -#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x00000000 -#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x00000018 - -// GC_CAC_CTRL_2 -#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x00000000 -#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x00000001 -#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x00000002 - -// GC_CAC_CGTT_CLK_CTRL -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f - -// GC_CAC_AGGR_LOWER -#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x00000000 - -// GC_CAC_AGGR_UPPER -#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x00000000 - -// GC_CAC_SOFT_CTRL -#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x00000000 -#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x00000001 - -// GC_DIDT_CTRL0 -#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x00000000 -#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x00000001 -#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x00000003 -#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000004 -#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000005 - -// GC_DIDT_CTRL1 -#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x00000000 -#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x00000010 - -// GC_DIDT_CTRL2 -#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0x0000000e -#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x0000001a -#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x0000001f - -// GC_DIDT_WEIGHT -#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x00000000 -#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x00000008 -#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x00000010 -#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x00000018 - -// GC_DIDT_WEIGHT_1 -#define GC_DIDT_WEIGHT_1__DBR_WEIGHT__SHIFT 0x00000000 - -// GC_EDC_CTRL -#define GC_EDC_CTRL__EDC_EN__SHIFT 0x00000000 -#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x00000001 -#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x00000002 -#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x00000003 -#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x00000009 -#define GC_EDC_CTRL__UNUSED_0__SHIFT 0x0000000a - -// GC_EDC_THRESHOLD -#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x00000000 - -// GC_EDC_STATUS -#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x00000000 -#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x00000003 - -// GC_EDC_OVERFLOW -#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x00000000 -#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x00000001 -#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x00000011 -#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x00000012 - -// GC_EDC_ROLLING_POWER_DELTA -#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x00000000 - -// GC_DIDT_DROOP_CTRL -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x00000000 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x00000001 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0x0000000f -#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x00000013 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x0000001f - -// GC_EDC_DROOP_CTRL -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x00000000 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x00000001 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0x0000000f -#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x00000014 -#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x00000015 - -// GC_CAC_IND_INDEX -#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x00000000 - -// GC_CAC_IND_DATA -#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x00000000 - -// SE_CAC_CGTT_CLK_CTRL -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f - -// SE_CAC_IND_INDEX -#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x00000000 - -// SE_CAC_IND_DATA -#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x00000000 - -// GC_CAC_CNTL -#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x00000000 -#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x00000001 -#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x00000011 -#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x00000017 -#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x0000001f - -// GC_CAC_OVR_SEL -#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x00000000 - -// GC_CAC_OVR_VAL -#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x00000000 - -// GC_CAC_WEIGHT_BCI_0 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CB_0 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CB_1 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CBR_0 -#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CBR_1 -#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CP_0 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CP_1 -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_DB_0 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_DB_1 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_DBR_0 -#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_DBR_1 -#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_GDS_0 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_GDS_1 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_IA_0 -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_LDS_0 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_LDS_1 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_PA_0 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_PC_0 -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SC_0 -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SPI_0 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SPI_1 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SPI_2 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SQ_0 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SQ_1 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SQ_2 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SQ_3 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SQ_4 -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SX_0 -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_SXRB_0 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TA_0 -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TCC_0 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TCC_1 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TCC_2 -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TCP_0 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TCP_1 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TCP_2 -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TD_0 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TD_1 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_TD_2 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_VGT_0 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_VGT_1 -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_RMI_0 -#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_WD_0 -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_EA_0 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_EA_1 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_EA_2 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ATCL2_0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ATCL2_1 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ATCL2_2 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ROUTER_0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ROUTER_1 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ROUTER_2 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ROUTER_3 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_ROUTER_4 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_VML2_0 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_VML2_1 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_VML2_2 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_0 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_1 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_2 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_3 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_4 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_5 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_6 -#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_CU_7 -#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15__SHIFT 0x00000010 - -// GC_CAC_ACC_BCI0 -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_BCI1 -#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CB0 -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CB1 -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CB2 -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CB3 -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CBR0 -#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CBR1 -#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CBR2 -#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CBR3 -#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CP0 -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CP1 -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CP2 -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DB0 -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DB1 -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DB2 -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DB3 -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DBR0 -#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DBR1 -#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DBR2 -#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_DBR3 -#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_GDS0 -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_GDS1 -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_GDS2 -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_GDS3 -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_IA0 -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_LDS0 -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_LDS1 -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_LDS2 -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_LDS3 -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_PA0 -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_PA1 -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_PC0 -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SC0 -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SPI0 -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SPI1 -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SPI2 -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SPI3 -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SPI4 -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SPI5 -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ0_LOWER -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ0_UPPER -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ1_LOWER -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ1_UPPER -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ2_LOWER -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ2_UPPER -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ3_LOWER -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ3_UPPER -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ4_LOWER -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ4_UPPER -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ5_LOWER -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ5_UPPER -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ6_LOWER -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ6_UPPER -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ7_LOWER -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ7_UPPER -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SQ8_LOWER -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SQ8_UPPER -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x00000000 -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x00000008 - -// GC_CAC_ACC_SX0 -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SXRB0 -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_SXRB1 -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TA0 -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCC0 -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCC1 -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCC2 -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCC3 -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCC4 -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCP0 -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCP1 -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCP2 -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCP3 -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TCP4 -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TD0 -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TD1 -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TD2 -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TD3 -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TD4 -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_TD5 -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_VGT0 -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_VGT1 -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_VGT2 -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_RMI0 -#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_WD0 -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_EA0 -#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_EA1 -#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_EA2 -#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_EA3 -#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_EA4 -#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_EA5 -#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ATCL20 -#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ATCL21 -#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ATCL22 -#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ATCL23 -#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ATCL24 -#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER0 -#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER1 -#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER2 -#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER3 -#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER4 -#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER5 -#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER6 -#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER7 -#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER8 -#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_ROUTER9 -#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_VML20 -#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_VML21 -#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_VML22 -#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_VML23 -#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_VML24 -#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU0 -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU1 -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU2 -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU3 -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU4 -#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU5 -#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU6 -#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU7 -#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU8 -#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU9 -#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU10 -#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU11 -#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU12 -#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU13 -#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU14 -#define GC_CAC_ACC_CU14__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_CU15 -#define GC_CAC_ACC_CU15__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_OVRD_BCI -#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x00000002 - -// GC_CAC_OVRD_CB -#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x00000004 - -// GC_CAC_OVRD_CBR -#define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT 0x00000004 - -// GC_CAC_OVRD_CP -#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x00000003 - -// GC_CAC_OVRD_DB -#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x00000004 - -// GC_CAC_OVRD_DBR -#define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT 0x00000004 - -// GC_CAC_OVRD_GDS -#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x00000004 - -// GC_CAC_OVRD_IA -#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_LDS -#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x00000004 - -// GC_CAC_OVRD_PA -#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x00000002 - -// GC_CAC_OVRD_PC -#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_SC -#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_SPI -#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x00000006 - -// GC_CAC_OVRD_CU -#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_SQ -#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x00000009 - -// GC_CAC_OVRD_SX -#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_SXRB -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_TA -#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_TCC -#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x00000005 - -// GC_CAC_OVRD_TCP -#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x00000005 - -// GC_CAC_OVRD_TD -#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x00000006 - -// GC_CAC_OVRD_VGT -#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x00000003 - -// GC_CAC_OVRD_RMI -#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_WD -#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x00000001 - -// GC_CAC_OVRD_EA -#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x00000006 - -// GC_CAC_OVRD_UTCL2_ATCL2 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x00000005 - -// GC_CAC_OVRD_UTCL2_ROUTER -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0x0000000a - -// GC_CAC_OVRD_UTCL2_VML2 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x00000005 - -// GC_CAC_WEIGHT_UTCL2_WALKER_0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_WALKER_1 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x00000010 - -// GC_CAC_WEIGHT_UTCL2_WALKER_2 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x00000000 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x00000010 - -// GC_CAC_ACC_UTCL2_WALKER0 -#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_WALKER1 -#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_WALKER2 -#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_WALKER3 -#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_ACC_UTCL2_WALKER4 -#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x00000000 - -// GC_CAC_OVRD_UTCL2_WALKER -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x00000000 -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x00000005 - -// SE_CAC_CNTL -#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x00000000 -#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x00000001 -#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x00000011 -#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x00000017 -#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x0000001f - -// SE_CAC_OVR_SEL -#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x00000000 - -// SE_CAC_OVR_VAL -#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x00000000 - -// RLC_GPM_PERF_COUNT_0 -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x00000000 -#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x00000004 -#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x00000008 -#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0x0000000c -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x00000010 -#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x00000012 -#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x00000014 -#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x00000015 - -// RLC_GPM_PERF_COUNT_1 -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x00000000 -#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x00000004 -#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x00000008 -#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0x0000000c -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x00000010 -#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x00000012 -#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x00000014 -#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x00000015 - -// RLC_PERFCOUNTER0_LO -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// RLC_PERFCOUNTER1_LO -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// RLC_PERFCOUNTER0_HI -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// RLC_PERFCOUNTER1_HI -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// RLC_PERFMON_CLK_CNTL -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x00000000 - -// RLC_PERFMON_CNTL -#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a - -// RLC_PERFCOUNTER0_SELECT -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 - -// RLC_PERFCOUNTER1_SELECT -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 - -// RLC_GPU_IOV_PERF_CNT_CNTL -#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x00000000 -#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x00000001 -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x00000002 -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x00000003 - -// RLC_GPU_IOV_PERF_CNT_WR_ADDR -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x00000000 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x00000004 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x00000006 - -// RLC_GPU_IOV_PERF_CNT_WR_DATA -#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x00000000 - -// RLC_GPU_IOV_PERF_CNT_RD_ADDR -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x00000000 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x00000004 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x00000006 - -// RLC_GPU_IOV_PERF_CNT_RD_DATA -#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x00000000 - -// RLC_SPM_PERFMON_CNTL -#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x00000000 -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0x0000000c -#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0x0000000e -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x00000010 - -// RLC_SPM_PERFMON_RING_BASE_LO -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x00000000 - -// RLC_SPM_PERFMON_RING_BASE_HI -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x00000000 -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x00000010 - -// RLC_SPM_PERFMON_RING_SIZE -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x00000000 - -// RLC_SPM_PERFMON_SEGMENT_SIZE -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x00000000 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x00000008 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0x0000000b -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x00000010 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x00000015 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x0000001a -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x0000001f - -// RLC_SPM_SE_MUXSEL_ADDR -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x00000000 - -// RLC_SPM_SE_MUXSEL_DATA -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x00000000 - -// RLC_SPM_CPG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_CPC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_CPF_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_CB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_DB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_PA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_GDS_PERFMON_SAMPLE_DELAY -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_IA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_SC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_TCC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_TCA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_TCP_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_TA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_TD_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_VGT_PERFMON_SAMPLE_DELAY -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_SPI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_SQG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_SX_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_GLOBAL_MUXSEL_ADDR -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x00000000 - -// RLC_SPM_GLOBAL_MUXSEL_DATA -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x00000000 - -// RLC_SPM_RING_RDPTR -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x00000000 - -// RLC_SPM_SEGMENT_THRESHOLD -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x00000000 - -// RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_SPM_RMI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x00000000 -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x00000008 - -// RLC_CNTL -#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x00000000 -#define RLC_CNTL__FORCE_RETRY__SHIFT 0x00000001 -#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x00000002 -#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x00000003 -#define RLC_CNTL__RESERVED__SHIFT 0x00000004 - -// RLC_DEBUG_SELECT -#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x00000000 -#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x00000008 - -// RLC_DEBUG -#define RLC_DEBUG__DATA__SHIFT 0x00000000 - -// RLC_STAT -#define RLC_STAT__RLC_BUSY__SHIFT 0x00000000 -#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x00000001 -#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x00000002 -#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x00000003 -#define RLC_STAT__MC_BUSY__SHIFT 0x00000004 -#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x00000005 -#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x00000006 -#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x00000007 -#define RLC_STAT__RESERVED__SHIFT 0x00000008 - -// RLC_INT_STAT -#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x00000000 -#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x00000008 -#define RLC_INT_STAT__RESERVED__SHIFT 0x00000009 - -// RLC_SAFE_MODE -#define RLC_SAFE_MODE__CMD__SHIFT 0x00000000 -#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x00000001 -#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x00000005 -#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x00000008 -#define RLC_SAFE_MODE__RESERVED__SHIFT 0x0000000c - -// RLC_MEM_SLP_CNTL -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x00000000 -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x00000001 -#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x00000007 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x00000008 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x00000010 -#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 - -// SMU_RLC_RESPONSE -#define SMU_RLC_RESPONSE__RESP__SHIFT 0x00000000 - -// RLC_RLCV_SAFE_MODE -#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x00000000 -#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x00000001 -#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x00000005 -#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x00000008 -#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0x0000000c - -// RLC_SMU_SAFE_MODE -#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x00000000 -#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x00000001 -#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x00000005 -#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x00000008 -#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0x0000000c - -// RLC_RLCV_COMMAND -#define RLC_RLCV_COMMAND__CMD__SHIFT 0x00000000 -#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x00000004 - -// RLC_REFCLOCK_TIMESTAMP_LSB -#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x00000000 - -// RLC_REFCLOCK_TIMESTAMP_MSB -#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x00000000 - -// RLC_GPM_TIMER_INT_0 -#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x00000000 - -// RLC_GPM_TIMER_INT_1 -#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x00000000 - -// RLC_GPM_TIMER_INT_2 -#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x00000000 - -// RLC_GPM_TIMER_INT_3 -#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x00000000 - -// RLC_GPM_TIMER_CTRL -#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x00000000 -#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x00000001 -#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x00000002 -#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x00000003 -#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x00000004 - -// RLC_GPM_TIMER_STAT -#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x00000000 -#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x00000001 -#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x00000002 -#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x00000003 -#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x00000004 - -// RLC_LB_CNTL -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x00000000 -#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x00000001 -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x00000002 -#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x00000003 -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x00000004 -#define RLC_LB_CNTL__RESERVED__SHIFT 0x0000000c - -// RLC_LB_CNTR_MAX -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x00000000 - -// RLC_LB_CNTR_INIT -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x00000000 - -// RLC_LOAD_BALANCE_CNTR -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x00000000 - -// RLC_JUMP_TABLE_RESTORE -#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x00000000 - -// RLC_PG_DELAY_2 -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x00000000 -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x00000008 -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x00000010 - -// RLC_GPM_DEBUG_INST_HIST -#define RLC_GPM_DEBUG_INST_HIST__DEBUG_ENABLE__SHIFT 0x00000000 -#define RLC_GPM_DEBUG_INST_HIST__INSTRUCTION_HISTORY_SAVE_INTERVAL__SHIFT 0x00000001 -#define RLC_GPM_DEBUG_INST_HIST__RESERVED__SHIFT 0x00000004 - -// RLC_GPM_DEBUG_SELECT -#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x00000000 -#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x00000008 -#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0x0000000a - -// RLC_GPM_DEBUG -#define RLC_GPM_DEBUG__DATA__SHIFT 0x00000000 - -// RLC_GPM_DEBUG_INST_A -#define RLC_GPM_DEBUG_INST_A__INST_A__SHIFT 0x00000000 - -// RLC_GPM_DEBUG_INST_B -#define RLC_GPM_DEBUG_INST_B__INST_B__SHIFT 0x00000000 - -// RLC_GPM_DEBUG_INST_ADDR -#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A__SHIFT 0x00000000 -#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B__SHIFT 0x00000010 - -// RLC_SEMAPHORE_0 -#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x00000000 -#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x00000005 - -// RLC_SEMAPHORE_1 -#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x00000000 -#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x00000005 - -// RLC_RLCV_SPARE_INT -#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x00000000 -#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x00000001 - -// RLC_GPU_CLOCK_COUNT_LSB -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x00000000 - -// RLC_GPU_CLOCK_COUNT_MSB -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x00000000 - -// RLC_CAPTURE_GPU_CLOCK_COUNT -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x00000000 -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x00000001 - -// RLC_UCODE_CNTL -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x00000000 - -// RLC_GPM_STAT -#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x00000000 -#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x00000001 -#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x00000002 -#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x00000003 -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x00000004 -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x00000005 -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x00000006 -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x00000007 -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x00000008 -#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x00000009 -#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0x0000000a -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0x0000000b -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0x0000000c -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0x0000000d -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0x0000000e -#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0x0000000f -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x00000010 -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x00000011 -#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x00000012 -#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x00000013 -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x00000014 -#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x00000015 -#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x00000016 -#define RLC_GPM_STAT__RESERVED__SHIFT 0x00000017 -#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x00000018 - -// RLC_GPU_CLOCK_32_RES_SEL -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000 -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x00000006 - -// RLC_GPU_CLOCK_32 -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x00000000 - -// RLC_PG_CNTL -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x00000000 -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x00000001 -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x00000002 -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x00000003 -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x00000004 -#define RLC_PG_CNTL__RESERVED__SHIFT 0x00000005 -#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0x0000000e -#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0x0000000f -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x00000010 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x00000011 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x00000012 -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x00000013 -#define RLC_PG_CNTL__RESERVED1__SHIFT 0x00000014 - -// RLC_GPM_THREAD_PRIORITY -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x00000000 -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x00000008 -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x00000010 -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x00000018 - -// RLC_GPM_THREAD_ENABLE -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x00000000 -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x00000001 -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x00000002 -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x00000003 -#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x00000004 - -// RLC_CGTT_MGCG_OVERRIDE -#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x00000000 -#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x00000001 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x00000002 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x00000003 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x00000004 -#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x00000005 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x00000006 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x00000007 -#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x00000008 - -// RLC_CGCG_CGLS_CTRL -#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x00000000 -#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x00000001 -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x00000002 -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x00000008 -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x0000001b -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x0000001c -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x0000001d -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x0000001f - -// RLC_CGCG_RAMP_CTRL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x00000000 -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x00000004 -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x00000008 -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0x0000000c -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x00000010 -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x0000001c - -// RLC_CGCG_CGLS_CTRL_3D -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x00000000 -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x00000001 -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x00000002 -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x00000008 -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x0000001b -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x0000001c -#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x0000001d -#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x0000001f - -// RLC_CGCG_RAMP_CTRL_3D -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x00000000 -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x00000004 -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x00000008 -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0x0000000c -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x00000010 -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x0000001c - -// RLC_DYN_PG_STATUS -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 - -// RLC_DYN_PG_REQUEST -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x00000000 - -// RLC_PG_DELAY -#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x00000000 -#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x00000008 -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x00000010 -#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x00000018 - -// RLC_CU_STATUS -#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x00000000 - -// RLC_LB_INIT_CU_MASK -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x00000000 - -// RLC_LB_ALWAYS_ACTIVE_CU_MASK -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x00000000 - -// RLC_LB_PARAMS -#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x00000000 -#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x00000001 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x00000008 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x00000010 - -// RLC_THREAD1_DELAY -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x00000000 -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x00000008 -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x00000010 -#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x00000018 - -// RLC_LB_THR_CONFIG_1 -#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x00000000 - -// RLC_LB_THR_CONFIG_2 -#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x00000000 - -// RLC_LB_THR_CONFIG_3 -#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x00000000 - -// RLC_LB_THR_CONFIG_4 -#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x00000000 - -// RLC_LB_DEBUG_1 -#define RLC_LB_DEBUG_1__DATA__SHIFT 0x00000000 - -// RLC_PG_ALWAYS_ON_CU_MASK -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x00000000 - -// RLC_MAX_PG_CU -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x00000000 -#define RLC_MAX_PG_CU__SPARE__SHIFT 0x00000008 - -// RLC_AUTO_PG_CTRL -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x00000000 -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x00000001 -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x00000002 -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x00000003 -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x00000013 - -// RLC_SMU_GRBM_REG_SAVE_CTRL -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x00000000 -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x00000001 - -// RLC_SERDES_RD_MASTER_INDEX -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x00000000 -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x00000004 -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x00000006 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x00000009 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0x0000000c -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0x0000000d -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x00000011 -#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x00000013 - -// RLC_SERDES_RD_DATA_0 -#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x00000000 - -// RLC_SERDES_RD_DATA_1 -#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x00000000 - -// RLC_SERDES_RD_DATA_2 -#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x00000000 - -// RLC_SERDES_WR_CU_MASTER_MASK -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x00000000 - -// RLC_SERDES_WR_NONCU_MASTER_MASK -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x00000000 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x00000010 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x00000011 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x00000012 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x00000013 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x00000014 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x00000015 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x00000016 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x00000017 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x00000018 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x00000019 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x0000001a - -// RLC_SERDES_WR_NONCU_MASTER_MASK_1 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x00000000 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x00000010 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x00000011 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x00000012 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x00000013 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x00000014 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x00000015 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x00000016 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x00000017 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x00000018 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x00000019 - -// RLC_SERDES_NONCU_MASTER_BUSY_1 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x00000000 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x00000010 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x00000011 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x00000012 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x00000013 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x00000014 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x00000015 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x00000016 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x00000017 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x00000018 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x00000019 - -// RLC_SERDES_WR_CTRL -#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x00000000 -#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x00000008 -#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x00000009 -#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0x0000000a -#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0x0000000b -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0x0000000c -#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0x0000000d -#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0x0000000e -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0x0000000f -#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x00000010 -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x0000001a -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x0000001b -#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x0000001c - -// RLC_SERDES_WR_DATA -#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x00000000 - -// RLC_SERDES_CU_MASTER_BUSY -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x00000000 - -// RLC_SERDES_NONCU_MASTER_BUSY -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x00000000 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x00000010 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x00000011 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x00000012 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x00000013 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x00000014 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x00000015 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x00000016 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x00000017 -#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x00000018 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x00000019 -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x0000001a - -// RLC_GPM_GENERAL_0 -#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_1 -#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_2 -#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_3 -#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_4 -#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_5 -#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_6 -#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_7 -#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x00000000 - -// RLC_GPM_SCRATCH_ADDR -#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x00000000 -#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x00000009 - -// RLC_GPM_SCRATCH_DATA -#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x00000000 - -// RLC_STATIC_PG_STATUS -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 - -// RLC_GPR_REG1 -#define RLC_GPR_REG1__DATA__SHIFT 0x00000000 - -// RLC_GPR_REG2 -#define RLC_GPR_REG2__DATA__SHIFT 0x00000000 - -// RLC_MGCG_CTRL -#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x00000000 -#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x00000001 -#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x00000002 -#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x00000003 -#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x00000007 -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0x0000000f -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x00000010 -#define RLC_MGCG_CTRL__SPARE__SHIFT 0x00000011 - -// RLC_GPM_THREAD_RESET -#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x00000000 -#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x00000001 -#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x00000002 -#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x00000003 -#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x00000004 - -// RLC_GPM_CP_DMA_COMPLETE_T0 -#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x00000000 -#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x00000001 - -// RLC_GPM_CP_DMA_COMPLETE_T1 -#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x00000000 -#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x00000001 - -// RLC_FIREWALL_VIOLATION -#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x00000000 - -// RLC_SPM_MC_CNTL -#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x00000000 -#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x00000004 -#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x00000005 -#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x00000006 -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x00000007 -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x00000008 -#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x0000000a - -// RLC_SPM_INT_CNTL -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x00000000 -#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x00000001 - -// RLC_SPM_INT_STATUS -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x00000000 -#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x00000001 - -// RLC_SPM_DEBUG_SELECT -#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x00000000 -#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x00000008 -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0x0000000f -#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x00000010 - -// RLC_SPM_DEBUG -#define RLC_SPM_DEBUG__DATA__SHIFT 0x00000000 - -// RLC_SMU_MESSAGE -#define RLC_SMU_MESSAGE__CMD__SHIFT 0x00000000 - -// RLC_GPM_LOG_SIZE -#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x00000000 - -// RLC_GPM_LOG_CONT -#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x00000000 - -// RLC_PG_DELAY_3 -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x00000000 -#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x00000008 - -// RLC_GPM_INT_DISABLE_TH0 -#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x00000000 - -// RLC_GPM_INT_DISABLE_TH1 -#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x00000000 - -// RLC_GPM_INT_FORCE_TH0 -#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x00000000 - -// RLC_GPM_INT_FORCE_TH1 -#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x00000000 - -// RLC_SRM_CNTL -#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x00000000 -#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x00000001 -#define RLC_SRM_CNTL__RESERVED__SHIFT 0x00000002 - -// RLC_SRM_DEBUG_SELECT -#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x00000000 -#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x00000008 - -// RLC_SRM_DEBUG -#define RLC_SRM_DEBUG__DATA__SHIFT 0x00000000 - -// RLC_SRM_ARAM_ADDR -#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x00000000 -#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0x0000000c - -// RLC_SRM_ARAM_DATA -#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x00000000 - -// RLC_SRM_DRAM_ADDR -#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x00000000 -#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0x0000000c - -// RLC_SRM_DRAM_DATA -#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x00000000 - -// RLC_SRM_GPM_COMMAND -#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x00000000 -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x00000001 -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x00000002 -#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x00000005 -#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x00000011 -#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x0000001d -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x0000001f - -// RLC_SRM_GPM_COMMAND_STATUS -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x00000000 -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x00000001 -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x00000002 - -// RLC_SRM_RLCV_COMMAND -#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x00000000 -#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x00000001 -#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x00000004 -#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x00000010 -#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x0000001c -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x0000001f - -// RLC_SRM_RLCV_COMMAND_STATUS -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x00000000 -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x00000001 -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x00000002 - -// RLC_SRM_INDEX_CNTL_ADDR_0 -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_ADDR_1 -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_ADDR_2 -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_ADDR_3 -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_ADDR_4 -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_ADDR_5 -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_ADDR_6 -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_ADDR_7 -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x00000000 -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x00000010 - -// RLC_SRM_INDEX_CNTL_DATA_0 -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x00000000 - -// RLC_SRM_INDEX_CNTL_DATA_1 -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x00000000 - -// RLC_SRM_INDEX_CNTL_DATA_2 -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x00000000 - -// RLC_SRM_INDEX_CNTL_DATA_3 -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x00000000 - -// RLC_SRM_INDEX_CNTL_DATA_4 -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x00000000 - -// RLC_SRM_INDEX_CNTL_DATA_5 -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x00000000 - -// RLC_SRM_INDEX_CNTL_DATA_6 -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x00000000 - -// RLC_SRM_INDEX_CNTL_DATA_7 -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x00000000 - -// RLC_SRM_STAT -#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x00000000 -#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x00000001 -#define RLC_SRM_STAT__RESERVED__SHIFT 0x00000002 - -// RLC_SRM_GPM_ABORT -#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x00000000 -#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x00000001 - -// RLC_CSIB_ADDR_LO -#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x00000000 - -// RLC_CSIB_ADDR_HI -#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x00000000 - -// RLC_CSIB_LENGTH -#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x00000000 - -// RLC_SMU_COMMAND -#define RLC_SMU_COMMAND__CMD__SHIFT 0x00000000 - -// RLC_CP_SCHEDULERS -#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x00000000 -#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x00000008 -#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x00000010 -#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x00000018 - -// RLC_SMU_ARGUMENT_1 -#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x00000000 - -// RLC_SMU_ARGUMENT_2 -#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_8 -#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_9 -#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_10 -#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_11 -#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x00000000 - -// RLC_GPM_GENERAL_12 -#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x00000000 - -// RLC_UTCL2_CNTL -#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x00000000 -#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x00000001 - -// RLC_GPM_UTCL1_CNTL_0 -#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x00000018 -#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x00000019 -#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x0000001a -#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x0000001c -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x0000001e - -// RLC_GPM_UTCL1_CNTL_1 -#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x00000018 -#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x00000019 -#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x0000001a -#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x0000001c -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x0000001e - -// RLC_GPM_UTCL1_CNTL_2 -#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x00000018 -#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x00000019 -#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x0000001a -#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x0000001c -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x0000001e - -// RLC_SPM_UTCL1_CNTL -#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x00000018 -#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x00000019 -#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x0000001a -#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x0000001c -#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x0000001e - -// RLC_PREWALKER_UTCL1_CNTL -#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x00000018 -#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x00000019 -#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x0000001a -#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x0000001c -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x0000001e - -// RLC_PREWALKER_UTCL1_TRIG -#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x00000000 -#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x00000001 -#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x00000005 -#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x00000006 -#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x00000007 -#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x00000008 -#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x00000009 -#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x0000001f - -// RLC_PREWALKER_UTCL1_ADDR_LSB -#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x00000000 - -// RLC_PREWALKER_UTCL1_ADDR_MSB -#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x00000000 - -// RLC_PREWALKER_UTCL1_SIZE_LSB -#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x00000000 - -// RLC_PREWALKER_UTCL1_SIZE_MSB -#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x00000000 - -// RLC_DSM_TRIG -#define RLC_DSM_TRIG__S__SHIFT 0x00000000 - -// RLC_UTCL1_STATUS_2 -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x00000000 -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x00000001 -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x00000002 -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x00000003 -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x00000004 -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x00000005 -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x00000006 -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x00000007 -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x00000008 -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x00000009 -#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0x0000000a - -// RLC_SPM_UTCL1_ERROR_1 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x00000000 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x00000002 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x00000006 - -// RLC_SPM_UTCL1_ERROR_2 -#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x00000000 - -// RLC_GPM_UTCL1_TH0_ERROR_1 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x00000000 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x00000002 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x00000006 - -// RLC_GPM_UTCL1_TH0_ERROR_2 -#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x00000000 - -// RLC_GPM_UTCL1_TH1_ERROR_1 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x00000000 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x00000002 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x00000006 - -// RLC_GPM_UTCL1_TH1_ERROR_2 -#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x00000000 - -// RLC_GPM_UTCL1_TH2_ERROR_1 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x00000000 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x00000002 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x00000006 - -// RLC_GPM_UTCL1_TH2_ERROR_2 -#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x00000000 - -// RLC_CP_EOF_INT -#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x00000000 -#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x00000001 - -// RLC_CP_EOF_INT_CNT -#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x00000000 - -// RLC_R2I_CNTL_0 -#define RLC_R2I_CNTL_0__Data__SHIFT 0x00000000 - -// RLC_R2I_CNTL_1 -#define RLC_R2I_CNTL_1__Data__SHIFT 0x00000000 - -// RLC_R2I_CNTL_2 -#define RLC_R2I_CNTL_2__Data__SHIFT 0x00000000 - -// RLC_R2I_CNTL_3 -#define RLC_R2I_CNTL_3__Data__SHIFT 0x00000000 - -// RLC_SPARE_INT -#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x00000000 -#define RLC_SPARE_INT__RESERVED__SHIFT 0x00000001 - -// RLC_UTCL1_STATUS -#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 -#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x00000003 -#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x00000008 -#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0x0000000e -#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x00000010 -#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x00000016 -#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x00000018 -#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x0000001e - -// RLC_LBPW_CU_STAT -#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x00000000 -#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x00000010 - -// RLC_DS_CNTL -#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x00000000 -#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x00000001 -#define RLC_DS_CNTL__RESRVED__SHIFT 0x00000002 -#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x00000010 -#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x00000011 -#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x00000012 - -// CGTT_RLC_CLK_CTRL -#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f - -// RLC_GFX_RM_CNTL -#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x00000000 -#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x00000001 - -// RLC_CLK_CNTL -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x00000000 -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x00000001 -#define RLC_CLK_CNTL__RESERVED__SHIFT 0x00000002 - -// RLC_GPM_UCODE_ADDR -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 -#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0x0000000e - -// RLC_GPM_UCODE_DATA -#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// RLC_GC_FUSESTRAP_RELOAD -#define RLC_GC_FUSESTRAP_RELOAD__RELOAD__SHIFT 0x00000000 -#define RLC_GC_FUSESTRAP_RELOAD__RESERVED__SHIFT 0x00000001 - -// RLC_GC_FUSESTRAP_GC_WRITE_DISABLE -#define RLC_GC_FUSESTRAP_GC_WRITE_DISABLE__GLOBAL_WRITE_DIS__SHIFT 0x00000000 -#define RLC_GC_FUSESTRAP_GC_WRITE_DISABLE__RESERVED__SHIFT 0x00000001 - -// RLC_GC_FUSESTRAP_CC_WRITE_DISABLE -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__CU_WRITE_DIS__SHIFT 0x00000000 -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__TCC_WRITE_DIS__SHIFT 0x00000001 -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__RB_WRITE_DIS__SHIFT 0x00000002 -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__PRIM_WRITE_DIS__SHIFT 0x00000003 -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__RATE_WRITE_DIS__SHIFT 0x00000004 -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__EDC_WRITE_DIS__SHIFT 0x00000005 -#define RLC_GC_FUSESTRAP_CC_WRITE_DISABLE__RESERVED__SHIFT 0x00000006 - -// RLC_GC_FUSESTRAP_DEBE_0 -#define RLC_GC_FUSESTRAP_DEBE_0__DEBE_31_0__SHIFT 0x00000000 - -// RLC_GC_FUSESTRAP_DEBE_1 -#define RLC_GC_FUSESTRAP_DEBE_1__DEBE_63_32__SHIFT 0x00000000 - -// RLC_GC_FUSESTRAP_DEBE_2 -#define RLC_GC_FUSESTRAP_DEBE_2__DEBE_95_64__SHIFT 0x00000000 - -// RLC_GC_FUSESTRAP_DEBE_3 -#define RLC_GC_FUSESTRAP_DEBE_3__DEBE_127_96__SHIFT 0x00000000 - -// RLC_GC_FUSESTRAP_DPFP_RATE -#define RLC_GC_FUSESTRAP_DPFP_RATE__DPFP_RATE__SHIFT 0x00000000 -#define RLC_GC_FUSESTRAP_DPFP_RATE__RESERVED__SHIFT 0x00000002 - -// RLC_GC_FUSESTRAP_DISABLE_EDC -#define RLC_GC_FUSESTRAP_DISABLE_EDC__DISABLE_EDC__SHIFT 0x00000000 -#define RLC_GC_FUSESTRAP_DISABLE_EDC__RESERVED__SHIFT 0x00000001 - -// RLC_HYP_SEMAPHORE_2 -#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x00000000 -#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x00000005 - -// RLC_HYP_SEMAPHORE_3 -#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x00000000 -#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x00000005 - -// RLC_GPU_IOV_VF_ENABLE -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x00000000 -#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x00000001 -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x00000010 - -// RLC_GPU_IOV_CFG_REG1 -#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x00000000 -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x00000004 -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x00000005 -#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x00000006 -#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x00000008 -#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x00000010 -#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x00000018 - -// RLC_GPU_IOV_CFG_REG2 -#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x00000000 -#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x00000004 - -// RLC_GPU_IOV_SCH_BLOCK -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x00000000 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x00000004 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x00000008 -#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x00000010 - -// RLC_GPU_IOV_CFG_REG6 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x00000000 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x00000007 -#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x00000008 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0x0000000a - -// RLC_GPU_IOV_CFG_REG8 -#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x00000000 - -// RLC_GPU_IOV_UCODE_ADDR -#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 -#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0x0000000c - -// RLC_GPU_IOV_UCODE_DATA -#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// RLC_GPU_IOV_SCRATCH_ADDR -#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x00000000 -#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x00000009 - -// RLC_GPU_IOV_SCRATCH_DATA -#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x00000000 - -// RLC_GPU_IOV_F32_CNTL -#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x00000000 -#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x00000001 - -// RLC_GPU_IOV_F32_RESET -#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x00000000 -#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x00000001 - -// RLC_GPU_IOV_SDMA0_STATUS -#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x00000000 -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x00000001 -#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x00000008 -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x00000009 -#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0x0000000c -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0x0000000d - -// RLC_GPU_IOV_SDMA1_STATUS -#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x00000000 -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x00000001 -#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x00000008 -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x00000009 -#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0x0000000c -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0x0000000d - -// RLC_GPU_IOV_SMU_RESPONSE -#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x00000000 - -// RLC_GPU_IOV_VIRT_RESET_REQ -#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x00000000 -#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x00000010 -#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x0000001f - -// RLC_GPU_IOV_SDMA0_BUSY_STATUS -#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x00000000 - -// RLC_GPU_IOV_SDMA1_BUSY_STATUS -#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x00000000 - -// RLC_GPU_IOV_VM_BUSY_STATUS -#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x00000000 - -// RLC_GPU_IOV_SCH_0 -#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x00000000 - -// RLC_GPU_IOV_SCH_1 -#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x00000000 - -// RLC_GPU_IOV_SCH_2 -#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x00000000 - -// RLC_GPU_IOV_SCH_3 -#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x00000000 - -// RLC_GPU_IOV_RLC_RESPONSE -#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x00000000 - -// RLC_GPU_IOV_ACTIVE_FCN_ID -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x00000000 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x00000004 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x0000001f - -// RLC_RLCV_TIMER_INT_0 -#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x00000000 - -// RLC_RLCV_TIMER_CTRL -#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x00000000 -#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x00000001 - -// RLC_RLCV_TIMER_STAT -#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x00000000 -#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x00000001 - -// RLC_GPU_IOV_INT_DISABLE -#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x00000000 - -// RLC_GPU_IOV_INT_FORCE -#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x00000000 - -// RLC_GPU_IOV_VF_DOORBELL_STATUS -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x00000000 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x00000010 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x0000001f - -// RLC_GPU_IOV_VF_DOORBELL_STATUS_SET -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x00000000 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x00000010 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x0000001f - -// RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x00000000 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x00000010 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x0000001f - -// RLC_GPU_IOV_VF_MASK -#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x00000000 -#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x00000010 - -// RLC_REG_PRIV_LEVEL_A -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL0__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL1__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL2__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL3__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL4__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL5__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL6__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL7__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL8__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL9__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL10__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL11__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL12__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL13__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL14__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_A__PRIV_LEVEL15__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_B -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL16__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL17__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL18__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL19__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL20__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL21__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL22__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL23__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL24__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL25__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL26__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL27__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL28__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL29__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL30__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_B__PRIV_LEVEL31__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_C -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL32__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL33__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL34__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL35__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL36__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL37__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL38__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL39__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL40__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL41__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL42__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL43__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL44__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL45__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL46__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_C__PRIV_LEVEL47__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_D -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL48__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL49__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL50__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL51__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL52__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL53__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL54__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL55__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL56__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL57__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL58__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL59__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL60__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL61__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL62__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_D__PRIV_LEVEL63__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_E -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL64__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL65__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL66__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL67__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL68__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL69__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL70__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL71__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL72__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL73__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL74__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL75__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL76__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL77__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL78__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_E__PRIV_LEVEL79__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_F -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL80__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL81__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL82__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL83__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL84__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL85__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL86__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL87__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL88__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL89__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL90__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL91__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL92__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL93__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL94__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_F__PRIV_LEVEL95__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_G -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL96__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL97__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL98__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL99__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL100__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL101__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL102__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL103__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL104__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL105__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL106__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL107__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL108__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL109__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL110__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_G__PRIV_LEVEL111__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_H -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL112__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL113__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL114__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL115__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL116__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL117__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL118__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL119__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL120__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL121__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL122__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL123__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL124__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL125__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL126__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_H__PRIV_LEVEL127__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_I -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL128__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL129__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL130__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL131__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL132__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL133__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL134__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL135__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL136__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL137__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL138__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL139__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL140__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL141__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL142__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_I__PRIV_LEVEL143__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_J -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL144__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL145__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL146__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL147__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL148__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL149__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL150__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL151__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL152__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL153__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL154__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL155__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL156__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL157__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL158__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_J__PRIV_LEVEL159__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_K -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL160__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL161__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL162__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL163__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL164__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL165__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL166__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL167__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL168__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL169__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL170__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL171__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL172__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL173__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL174__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_K__PRIV_LEVEL175__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_L -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL176__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL177__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL178__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL179__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL180__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL181__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL182__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL183__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL184__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL185__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL186__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL187__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL188__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL189__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL190__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_L__PRIV_LEVEL191__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_M -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL192__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL193__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL194__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL195__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL196__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL197__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL198__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL199__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL200__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL201__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL202__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL203__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL204__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL205__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL206__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_M__PRIV_LEVEL207__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_N -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL208__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL209__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL210__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL211__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL212__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL213__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL214__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL215__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL216__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL217__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL218__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL219__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL220__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL221__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL222__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_N__PRIV_LEVEL223__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_O -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL224__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL225__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL226__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL227__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL228__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL229__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL230__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL231__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL232__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL233__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL234__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL235__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL236__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL237__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL238__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_O__PRIV_LEVEL239__SHIFT 0x0000001e - -// RLC_REG_PRIV_LEVEL_P -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL240__SHIFT 0x00000000 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL241__SHIFT 0x00000002 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL242__SHIFT 0x00000004 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL243__SHIFT 0x00000006 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL244__SHIFT 0x00000008 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL245__SHIFT 0x0000000a -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL246__SHIFT 0x0000000c -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL247__SHIFT 0x0000000e -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL248__SHIFT 0x00000010 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL249__SHIFT 0x00000012 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL250__SHIFT 0x00000014 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL251__SHIFT 0x00000016 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL252__SHIFT 0x00000018 -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL253__SHIFT 0x0000001a -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL254__SHIFT 0x0000001c -#define RLC_REG_PRIV_LEVEL_P__PRIV_LEVEL255__SHIFT 0x0000001e - -// RLC_REG_SEC_INT_STATUS -#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT__SHIFT 0x00000000 -#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_OVERFLOW__SHIFT 0x00000010 -#define RLC_REG_SEC_INT_STATUS__RESERVED__SHIFT 0x00000011 - -// RLC_FWL_FIRST_VIOL_ADDR -#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x00000000 -#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x00000012 -#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT 0x00000013 - -// SPI_PS_MAX_WAVE_ID -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 -#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x00000010 - -// SPI_START_PHASE -#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x00000000 -#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x00000002 -#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x00000004 - -// SPI_GFX_CNTL -#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x00000000 - -// SPI_DEBUG_CNTL -#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x00000000 -#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x00000001 -#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x00000004 -#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0x0000000a -#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x00000010 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x00000011 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x00000012 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x00000013 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x00000014 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x00000015 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x00000016 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x00000017 -#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x00000018 -#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x00000019 -#define SPI_DEBUG_CNTL__BCI_PIPE_PER_STAGE_CG_OVERRIDE__SHIFT 0x0000001e -#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x0000001f - -// SPI_DEBUG_READ -#define SPI_DEBUG_READ__DATA__SHIFT 0x00000000 - -// SPI_DSM_CNTL -#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define SPI_DSM_CNTL__UNUSED__SHIFT 0x00000003 - -// SPI_DSM_CNTL2 -#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x00000004 -#define SPI_DSM_CNTL2__UNUSED__SHIFT 0x0000000a - -// SPI_EDC_CNT -#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x00000000 - -// SPI_DEBUG_BUSY -#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x00000000 -#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x00000001 -#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x00000002 -#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x00000003 -#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x00000004 -#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x00000005 -#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x00000006 -#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x00000007 -#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x00000008 -#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x00000009 -#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x0000000a -#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x0000000b -#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0x0000000c -#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0x0000000d -#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0x0000000e -#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0x0000000f -#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x00000010 -#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x00000011 -#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x00000012 -#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x00000013 -#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x00000014 -#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x00000015 -#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x00000016 -#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x00000017 - -// SPI_CONFIG_PS_CU_EN -#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x00000000 -#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x00000001 -#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x00000010 - -// SPI_WF_LIFETIME_CNTL -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x00000004 - -// SPI_WF_LIFETIME_LIMIT_0 -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_1 -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_2 -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_3 -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_4 -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_5 -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_6 -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_7 -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_8 -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_LIMIT_9 -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_0 -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_1 -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_2 -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_3 -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_4 -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_5 -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_6 -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_7 -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_8 -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_9 -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_10 -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_11 -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_12 -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_13 -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_14 -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_15 -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_16 -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_17 -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_18 -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_19 -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_STATUS_20 -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x0000001f - -// SPI_WF_LIFETIME_DEBUG -#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x00000000 -#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x0000001f - -// SPI_SLAVE_DEBUG_BUSY -#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x00000000 -#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x00000001 -#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x00000002 -#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x00000003 -#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x00000004 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x00000005 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x00000006 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x00000007 -#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x00000008 -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x00000009 -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x0000000a -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0x0000000b -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0x0000000c -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0x0000000d -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0x0000000e -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0x0000000f -#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x00000010 -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x00000011 -#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x00000012 -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x00000013 -#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x00000014 -#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x00000015 -#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x00000016 - -// SPI_LB_CTR_CTRL -#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x00000000 -#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x00000001 -#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x00000003 -#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x00000004 - -// SPI_LB_CU_MASK -#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x00000000 - -// SPI_LB_DATA_REG -#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x00000000 - -// SPI_PG_ENABLE_STATIC_CU_MASK -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x00000000 - -// SPI_GDS_CREDITS -#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x00000000 -#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x00000008 -#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x00000010 - -// SPI_SX_EXPORT_BUFFER_SIZES -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x00000000 -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x00000010 - -// SPI_SX_SCOREBOARD_BUFFER_SIZES -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x00000000 -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_STATUS -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x00000000 - -// SPI_CSQ_WF_ACTIVE_COUNT_0 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_COUNT_1 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_COUNT_2 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_COUNT_3 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_COUNT_4 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_COUNT_5 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_COUNT_6 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x00000010 - -// SPI_CSQ_WF_ACTIVE_COUNT_7 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x00000000 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x00000010 - -// SPI_LB_DATA_WAVES -#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x00000000 -#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x00000010 - -// SPI_LB_DATA_PERCU_WAVE_HSGS -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x00000000 -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x00000010 - -// SPI_LB_DATA_PERCU_WAVE_VSPS -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x00000000 -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x00000010 - -// SPI_LB_DATA_PERCU_WAVE_CS -#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x00000000 - -// SPIS_DEBUG_READ -#define SPIS_DEBUG_READ__DATA__SHIFT 0x00000000 - -// BCI_DEBUG_READ -#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000 - -// SPI_P0_TRAP_SCREEN_PSBA_LO -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x00000000 - -// SPI_P0_TRAP_SCREEN_PSBA_HI -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x00000000 - -// SPI_P0_TRAP_SCREEN_PSMA_LO -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x00000000 - -// SPI_P0_TRAP_SCREEN_PSMA_HI -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x00000000 - -// SPI_P0_TRAP_SCREEN_GPR_MIN -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x00000000 -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x00000006 - -// SPI_P1_TRAP_SCREEN_PSBA_LO -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x00000000 - -// SPI_P1_TRAP_SCREEN_PSBA_HI -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x00000000 - -// SPI_P1_TRAP_SCREEN_PSMA_LO -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x00000000 - -// SPI_P1_TRAP_SCREEN_PSMA_HI -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x00000000 - -// SPI_P1_TRAP_SCREEN_GPR_MIN -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x00000000 -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x00000006 - -// SPI_SHADER_PGM_LO_PS -#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_HI_PS -#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_RSRC1_PS -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x0000001c -#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x0000001d - -// SPI_SHADER_PGM_RSRC2_PS -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x00000008 -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x00000019 -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x0000001a -#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x0000001b -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x0000001c - -// SPI_SHADER_PGM_RSRC3_PS -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x0000001a - -// SPI_SHADER_USER_DATA_PS_0 -#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_1 -#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_2 -#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_3 -#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_4 -#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_5 -#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_6 -#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_7 -#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_8 -#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_9 -#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_10 -#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_11 -#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_12 -#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_13 -#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_14 -#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_15 -#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_16 -#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_17 -#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_18 -#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_19 -#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_20 -#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_21 -#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_22 -#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_23 -#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_24 -#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_25 -#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_26 -#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_27 -#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_28 -#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_29 -#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_30 -#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_PS_31 -#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x00000000 - -// SPI_SHADER_PGM_LO_VS -#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_HI_VS -#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_RSRC1_VS -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x0000001a -#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x0000001e -#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x0000001f - -// SPI_SHADER_PGM_RSRC2_VS -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x00000008 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x00000009 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0x0000000b -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0x0000000d -#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x0000001b -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x0000001c - -// SPI_SHADER_PGM_RSRC3_VS -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x0000001a - -// SPI_SHADER_LATE_ALLOC_VS -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_0 -#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_1 -#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_2 -#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_3 -#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_4 -#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_5 -#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_6 -#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_7 -#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_8 -#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_9 -#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_10 -#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_11 -#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_12 -#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_13 -#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_14 -#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_15 -#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_16 -#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_17 -#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_18 -#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_19 -#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_20 -#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_21 -#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_22 -#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_23 -#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_24 -#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_25 -#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_26 -#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_27 -#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_28 -#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_29 -#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_30 -#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_VS_31 -#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x00000000 - -// SPI_SHADER_PGM_RSRC2_GS_VS -#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x00000012 -#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x00000013 -#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x0000001b -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x0000001c - -// SPI_SHADER_USER_DATA_ADDR_LO_GS -#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ADDR_HI_GS -#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_LO_GS -#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_HI_GS -#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_LO_ES -#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_HI_ES -#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_RSRC1_GS -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x00000018 -#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x0000001c -#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x0000001d -#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x0000001f - -// SPI_SHADER_PGM_RSRC2_GS -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x00000012 -#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x00000013 -#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x0000001b -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x0000001c - -// SPI_SHADER_PGM_RSRC3_GS -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x0000001a - -// SPI_SHADER_PGM_RSRC4_GS -#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x00000007 - -// SPI_SHADER_USER_DATA_ES_0 -#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_1 -#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_2 -#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_3 -#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_4 -#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_5 -#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_6 -#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_7 -#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_8 -#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_9 -#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_10 -#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_11 -#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_12 -#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_13 -#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_14 -#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_15 -#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_16 -#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_17 -#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_18 -#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_19 -#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_20 -#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_21 -#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_22 -#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_23 -#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_24 -#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_25 -#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_26 -#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_27 -#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_28 -#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_29 -#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_30 -#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ES_31 -#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ADDR_LO_HS -#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_ADDR_HI_HS -#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_LO_HS -#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_HI_HS -#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_LO_LS -#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_HI_LS -#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x00000000 - -// SPI_SHADER_PGM_RSRC1_HS -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0x0000000c -#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x00000014 -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x00000015 -#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x00000016 -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x00000017 -#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x0000001b -#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x0000001c -#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x0000001e - -// SPI_SHADER_PGM_RSRC2_HS -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x00000001 -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x00000007 -#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x00000010 -#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x0000001b -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x0000001c - -// SPI_SHADER_PGM_RSRC3_HS -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x00000000 -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x00000006 -#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0x0000000a -#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x00000010 - -// SPI_SHADER_PGM_RSRC4_HS -#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_0 -#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_1 -#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_2 -#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_3 -#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_4 -#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_5 -#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_6 -#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_7 -#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_8 -#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_9 -#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_10 -#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_11 -#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_12 -#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_13 -#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_14 -#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_15 -#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_16 -#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_17 -#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_18 -#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_19 -#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_20 -#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_21 -#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_22 -#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_23 -#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_24 -#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_25 -#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_26 -#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_27 -#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_28 -#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_29 -#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_30 -#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_LS_31 -#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_0 -#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_1 -#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_2 -#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_3 -#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_4 -#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_5 -#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_6 -#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_7 -#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_8 -#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_9 -#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_10 -#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_11 -#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_12 -#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_13 -#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_14 -#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_15 -#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_16 -#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_17 -#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_18 -#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_19 -#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_20 -#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_21 -#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_22 -#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_23 -#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_24 -#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_25 -#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_26 -#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_27 -#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_28 -#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_29 -#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_30 -#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x00000000 - -// SPI_SHADER_USER_DATA_COMMON_31 -#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x00000000 - -// SPI_ARB_PRIORITY -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x00000000 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x00000003 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x00000006 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x00000009 -#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0x0000000c -#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0x0000000e -#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x00000010 -#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x00000012 - -// SPI_ARB_CYCLES_0 -#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x00000000 -#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x00000010 - -// SPI_ARB_CYCLES_1 -#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x00000000 -#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x00000010 - -// SPI_CDBG_SYS_GFX -#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x00000000 -#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x00000001 -#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x00000002 -#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x00000003 -#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x00000004 -#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x00000005 -#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x00000006 - -// SPI_CDBG_SYS_HP3D -#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x00000000 -#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x00000001 -#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x00000002 -#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x00000003 -#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x00000004 -#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x00000005 - -// SPI_CDBG_SYS_CS0 -#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x00000000 -#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x00000008 -#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x00000010 -#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x00000018 - -// SPI_CDBG_SYS_CS1 -#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x00000000 -#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x00000008 -#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x00000010 -#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x00000018 - -// SPI_WCL_PIPE_PERCENT_GFX -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x00000000 -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x00000007 -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0x0000000c -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x00000011 -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x00000016 - -// SPI_WCL_PIPE_PERCENT_HP3D -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x00000000 -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0x0000000c -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x00000016 - -// SPI_WCL_PIPE_PERCENT_CS0 -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x00000000 - -// SPI_WCL_PIPE_PERCENT_CS1 -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x00000000 - -// SPI_WCL_PIPE_PERCENT_CS2 -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x00000000 - -// SPI_WCL_PIPE_PERCENT_CS3 -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x00000000 - -// SPI_WCL_PIPE_PERCENT_CS4 -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x00000000 - -// SPI_WCL_PIPE_PERCENT_CS5 -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x00000000 - -// SPI_WCL_PIPE_PERCENT_CS6 -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x00000000 - -// SPI_WCL_PIPE_PERCENT_CS7 -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x00000000 - -// SPI_GDBG_WAVE_CNTL -#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x00000000 -#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x00000001 - -// SPI_GDBG_TRAP_CONFIG -#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x00000000 -#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x00000002 -#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x00000004 -#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x00000007 -#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x00000008 -#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x00000009 -#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0x0000000f -#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x00000010 - -// SPI_GDBG_TRAP_MASK -#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x00000000 -#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x00000009 - -// SPI_GDBG_WAVE_CNTL2 -#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x00000000 -#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x00000010 - -// SPI_GDBG_WAVE_CNTL3 -#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x00000000 -#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x00000001 -#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x00000002 -#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x00000003 -#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x00000004 -#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x00000005 -#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x00000006 -#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x00000007 -#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x00000008 -#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x00000009 -#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0x0000000a -#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0x0000000b -#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0x0000000c -#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0x0000000d -#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x0000001c - -// SPI_GDBG_TRAP_DATA0 -#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x00000000 - -// SPI_GDBG_TRAP_DATA1 -#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x00000000 - -// SPI_RESET_DEBUG -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x00000000 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x00000001 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x00000002 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x00000003 -#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x00000004 - -// SPI_COMPUTE_QUEUE_RESET -#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x00000000 - -// SPI_RESOURCE_RESERVE_CU_0 -#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_1 -#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_2 -#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_3 -#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_4 -#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_5 -#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_6 -#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_7 -#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_8 -#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_9 -#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_10 -#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_11 -#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_12 -#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_13 -#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_14 -#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_CU_15 -#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x00000004 -#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x00000008 -#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0x0000000c -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0x0000000f - -// SPI_RESOURCE_RESERVE_EN_CU_0 -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_1 -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_2 -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_3 -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_4 -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_5 -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_6 -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_7 -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_8 -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_9 -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_10 -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_11 -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_12 -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_13 -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_14 -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_RESOURCE_RESERVE_EN_CU_15 -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x00000000 -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x00000001 -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x00000010 -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x00000018 - -// SPI_COMPUTE_WF_CTX_SAVE -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x00000000 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x00000001 -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x00000002 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x0000001e -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x0000001f - -// SPI_ARB_CNTL_0 -#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x00000000 -#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x00000004 -#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x00000008 - -// SPI_PS_INPUT_CNTL_0 -#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_1 -#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_2 -#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_3 -#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_4 -#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_5 -#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_6 -#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_7 -#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_8 -#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_9 -#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_10 -#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_11 -#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_12 -#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_13 -#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_14 -#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_15 -#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_16 -#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_17 -#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_18 -#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_19 -#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0x0000000d -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x00000011 -#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x00000017 -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_20 -#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_21 -#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_22 -#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_23 -#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_24 -#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_25 -#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_26 -#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_27 -#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_28 -#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_29 -#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_30 -#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_PS_INPUT_CNTL_31 -#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x00000000 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x00000008 -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0x0000000a -#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x00000012 -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x00000013 -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x00000014 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x00000015 -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x00000018 -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x00000019 - -// SPI_VS_OUT_CONFIG -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x00000001 -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x00000006 - -// SPI_PS_INPUT_ENA -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x00000000 -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x00000001 -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x00000002 -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x00000005 -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x00000006 -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x00000008 -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x00000009 -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0x0000000a -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0x0000000b -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0x0000000c -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0x0000000d -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0x0000000f - -// SPI_PS_INPUT_ADDR -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x00000000 -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x00000001 -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x00000002 -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x00000005 -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x00000006 -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x00000008 -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x00000009 -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0x0000000a -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0x0000000b -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0x0000000c -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0x0000000d -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0x0000000f - -// SPI_INTERP_CONTROL_0 -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x00000000 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x00000001 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x00000002 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x00000005 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x00000008 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0x0000000b -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0x0000000e - -// SPI_PS_IN_CONTROL -#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000 -#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x00000006 -#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x00000007 -#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x00000008 -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0x0000000e - -// SPI_BARYC_CNTL -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x00000000 -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x00000004 -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x00000008 -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0x0000000c -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x00000010 -#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x00000014 -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x00000018 - -// SPI_TMPRING_SIZE -#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x00000000 -#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c - -// SPI_SHADER_POS_FORMAT -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x00000000 -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x00000004 -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x00000008 -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0x0000000c - -// SPI_SHADER_Z_FORMAT -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x00000000 - -// SPI_SHADER_COL_FORMAT -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x00000000 -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x00000004 -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x00000008 -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0x0000000c -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x00000010 -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x00000014 -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x00000018 -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x0000001c - -// SPI_CONFIG_CNTL -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x00000000 -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x00000015 -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x00000018 -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x00000019 -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x0000001a -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x0000001b -#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x0000001c -#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x0000001d -#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x0000001e - -// SPI_CONFIG_CNTL_1 -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x00000000 -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x00000004 -#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x00000005 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x00000006 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x00000007 -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x00000008 -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x00000009 -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0x0000000a -#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0x0000000e -#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0x0000000f -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x00000010 - -// SPI_CONFIG_CNTL_2 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x00000000 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x00000004 - -// SPI_PERFCOUNTER0_HI -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SPI_PERFCOUNTER0_LO -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SPI_PERFCOUNTER1_HI -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SPI_PERFCOUNTER1_LO -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SPI_PERFCOUNTER2_HI -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SPI_PERFCOUNTER2_LO -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SPI_PERFCOUNTER3_HI -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SPI_PERFCOUNTER3_LO -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SPI_PERFCOUNTER4_HI -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SPI_PERFCOUNTER4_LO -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SPI_PERFCOUNTER5_HI -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SPI_PERFCOUNTER5_LO -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SPI_PERFCOUNTER0_SELECT -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SPI_PERFCOUNTER1_SELECT -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SPI_PERFCOUNTER2_SELECT -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SPI_PERFCOUNTER3_SELECT -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SPI_PERFCOUNTER0_SELECT1 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// SPI_PERFCOUNTER1_SELECT1 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// SPI_PERFCOUNTER2_SELECT1 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// SPI_PERFCOUNTER3_SELECT1 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// SPI_PERFCOUNTER4_SELECT -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 - -// SPI_PERFCOUNTER5_SELECT -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 - -// SPI_PERFCOUNTER_BINS -#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x00000000 -#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x00000004 -#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x00000008 -#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0x0000000c -#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x00000010 -#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x00000014 -#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x00000018 -#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x0000001c - -// CGTS_SM_CTRL_REG -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000 -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004 -#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c -#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010 -#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011 -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014 -#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015 -#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018 - -// CGTS_RD_CTRL_REG -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000 -#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008 - -// CGTS_RD_REG -#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000 - -// CGTS_TCC_DISABLE -#define CGTS_TCC_DISABLE__WRITE_DIS__SHIFT 0x00000000 -#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 - -// CGTS_USER_TCC_DISABLE -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 - -// CGTS_CU0_SP0_CTRL_REG -#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU0_LDS_SQ_CTRL_REG -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU0_TA_SQC_CTRL_REG -#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x00000010 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU0_SP1_CTRL_REG -#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU0_TD_TCP_CTRL_REG -#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU0_TCPI_CTRL_REG -#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU1_SP0_CTRL_REG -#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU1_LDS_SQ_CTRL_REG -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU1_TA_SQC_CTRL_REG -#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU1_SP1_CTRL_REG -#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU1_TD_TCP_CTRL_REG -#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU1_TCPI_CTRL_REG -#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU2_SP0_CTRL_REG -#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU2_LDS_SQ_CTRL_REG -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU2_TA_SQC_CTRL_REG -#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU2_SP1_CTRL_REG -#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU2_TD_TCP_CTRL_REG -#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU2_TCPI_CTRL_REG -#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU3_SP0_CTRL_REG -#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU3_LDS_SQ_CTRL_REG -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU3_TA_SQC_CTRL_REG -#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x00000010 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU3_SP1_CTRL_REG -#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU3_TD_TCP_CTRL_REG -#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU3_TCPI_CTRL_REG -#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU4_SP0_CTRL_REG -#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU4_LDS_SQ_CTRL_REG -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU4_TA_SQC_CTRL_REG -#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU4_SP1_CTRL_REG -#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU4_TD_TCP_CTRL_REG -#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU4_TCPI_CTRL_REG -#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU5_SP0_CTRL_REG -#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU5_LDS_SQ_CTRL_REG -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU5_TA_SQC_CTRL_REG -#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU5_SP1_CTRL_REG -#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU5_TD_TCP_CTRL_REG -#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU5_TCPI_CTRL_REG -#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU6_SP0_CTRL_REG -#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU6_LDS_SQ_CTRL_REG -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU6_TA_SQC_CTRL_REG -#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x00000010 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU6_SP1_CTRL_REG -#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU6_TD_TCP_CTRL_REG -#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU6_TCPI_CTRL_REG -#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU7_SP0_CTRL_REG -#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU7_LDS_SQ_CTRL_REG -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU7_TA_SQC_CTRL_REG -#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU7_SP1_CTRL_REG -#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU7_TD_TCP_CTRL_REG -#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU7_TCPI_CTRL_REG -#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU8_SP0_CTRL_REG -#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU8_LDS_SQ_CTRL_REG -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU8_TA_SQC_CTRL_REG -#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU8_SP1_CTRL_REG -#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU8_TD_TCP_CTRL_REG -#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU8_TCPI_CTRL_REG -#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU9_SP0_CTRL_REG -#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU9_LDS_SQ_CTRL_REG -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU9_TA_SQC_CTRL_REG -#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x00000010 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU9_SP1_CTRL_REG -#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU9_TD_TCP_CTRL_REG -#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU9_TCPI_CTRL_REG -#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU10_SP0_CTRL_REG -#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU10_LDS_SQ_CTRL_REG -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU10_TA_SQC_CTRL_REG -#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU10_SP1_CTRL_REG -#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU10_TD_TCP_CTRL_REG -#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU10_TCPI_CTRL_REG -#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU11_SP0_CTRL_REG -#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU11_LDS_SQ_CTRL_REG -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU11_TA_SQC_CTRL_REG -#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU11_SP1_CTRL_REG -#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU11_TD_TCP_CTRL_REG -#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU11_TCPI_CTRL_REG -#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU12_SP0_CTRL_REG -#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU12_LDS_SQ_CTRL_REG -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU12_TA_SQC_CTRL_REG -#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x00000010 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU12_SP1_CTRL_REG -#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU12_TD_TCP_CTRL_REG -#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU12_TCPI_CTRL_REG -#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU13_SP0_CTRL_REG -#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU13_LDS_SQ_CTRL_REG -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU13_TA_SQC_CTRL_REG -#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU13_SP1_CTRL_REG -#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU13_TD_TCP_CTRL_REG -#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU13_TCPI_CTRL_REG -#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU14_SP0_CTRL_REG -#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU14_LDS_SQ_CTRL_REG -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU14_TA_SQC_CTRL_REG -#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b - -// CGTS_CU14_SP1_CTRL_REG -#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU14_TD_TCP_CTRL_REG -#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU14_TCPI_CTRL_REG -#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTS_CU15_SP0_CTRL_REG -#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x00000000 -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x00000010 -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU15_LDS_SQ_CTRL_REG -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x00000000 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x00000010 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU15_TA_SQC_CTRL_REG -#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x00000000 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x00000010 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU15_SP1_CTRL_REG -#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x00000000 -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x00000010 -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU15_TD_TCP_CTRL_REG -#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x00000000 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x00000010 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x00000017 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x00000018 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x0000001a -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x0000001b - -// CGTS_CU15_TCPI_CTRL_REG -#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x00000000 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x00000007 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x00000008 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x0000000a -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x0000000b -#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0x0000000c - -// CGTT_SPI_CLK_CTRL -#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// CGTT_PC_CLK_CTRL -#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 -#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x00000019 -#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x0000001a -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// CGTT_BCI_CLK_CTRL -#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018 -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019 -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// SQ_CONFIG -#define SQ_CONFIG__UNUSED__SHIFT 0x00000000 -#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x00000007 -#define SQ_CONFIG__DEBUG_EN__SHIFT 0x00000008 -#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x00000009 -#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0x0000000a -#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0x0000000b -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0x0000000c -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0x0000000d -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0x0000000e -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0x0000000f -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x00000010 -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x00000011 -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x00000012 -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x00000013 -#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x00000015 -#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x0000001c -#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x0000001d -#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x0000001e -#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x0000001f - -// SQC_CONFIG -#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x00000000 -#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x00000002 -#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x00000004 -#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x00000006 -#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x00000007 -#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x00000008 -#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x00000009 -#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0x0000000a -#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x0000000b -#define SQC_CONFIG__EVICT_LRU__SHIFT 0x0000000c -#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0x0000000e -#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0x0000000f -#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x00000010 -#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x00000018 -#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x0000001a - -// LDS_CONFIG -#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x00000000 -#define LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT 0x00000001 - -// SQC_DSM_CNTL -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x00000003 -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000006 -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x00000009 -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x0000000b -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0000000c -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x0000000e -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x0000000f -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x00000011 -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000012 -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000014 - -// SQC_DSM_CNTLA -#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000003 -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000006 -#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 -#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000009 -#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000b -#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0000000c -#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000e -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x0000000f -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000011 -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000012 -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000014 -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000015 -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x00000017 -#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000018 -#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x0000001a - -// SQC_DSM_CNTLB -#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000003 -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000006 -#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 -#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000009 -#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000b -#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0000000c -#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000e -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x0000000f -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000011 -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000012 -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000014 -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000015 -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x00000017 -#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x00000018 -#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x0000001a - -// SQC_DSM_CNTL2 -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x0000000f -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x00000011 -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000012 -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x00000014 -#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x0000001a - -// SQC_DSM_CNTL2A -#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0000000f -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000011 -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000012 -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000014 -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000015 -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x00000017 -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000018 -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000001a - -// SQC_DSM_CNTL2B -#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0000000f -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000011 -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000012 -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000014 -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000015 -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x00000017 -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000018 -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000001a - -// SQC_EDC_FUE_CNTL -#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x00000000 -#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x00000010 - -// SQC_EDC_CNT2 -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x00000000 -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x00000002 -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x00000004 -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x00000006 -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x00000008 -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x0000000a -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x0000000c -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x0000000e -#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x00000010 -#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x00000012 -#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x00000014 -#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x00000016 -#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x00000018 -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x0000001a -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x0000001c - -// SQC_EDC_CNT3 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x00000000 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x00000002 -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x00000004 -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x00000006 -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x00000008 -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x0000000a -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x0000000c -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x0000000e -#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x00000010 -#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x00000012 -#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x00000014 -#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x00000016 -#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x00000018 - -// SQ_RANDOM_WAVE_PRI -#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x00000000 -#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x00000007 -#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0x0000000a - -// SQ_REG_CREDITS -#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x00000000 -#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x00000008 -#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x0000001c -#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x0000001d -#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x0000001e -#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x0000001f - -// SQ_FIFO_SIZES -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x00000000 -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x00000008 -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x00000010 -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x00000012 - -// SQ_DSM_CNTL -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x00000000 -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x00000001 -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x00000002 -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x00000003 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x00000008 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x00000009 -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0x0000000a -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x00000010 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x00000011 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x00000012 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x00000013 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x00000014 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x00000015 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x00000018 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x00000019 -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x0000001a - -// SQ_DSM_CNTL2 -#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0x0000000e -#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x00000014 -#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x0000001a - -// SQ_RUNTIME_CONFIG -#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x00000000 - -// CC_GC_SHADER_RATE_CONFIG -#define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x00000001 -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x00000004 - -// GC_USER_SHADER_RATE_CONFIG -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x00000001 -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x00000004 - -// SQ_INTERRUPT_AUTO_MASK -#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x00000000 - -// SQ_INTERRUPT_MSG_CTRL -#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x00000000 - -// SQ_DEBUG_PERFCOUNT_TRAP -#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT 0x00000000 -#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT 0x00000001 -#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT 0x00000004 - -// SQ_UTCL1_CNTL1 -#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x00000000 -#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x00000001 -#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x00000002 -#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x00000003 -#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x00000005 -#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x00000007 -#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x00000010 -#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x00000011 -#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x00000012 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x00000013 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x00000017 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x00000018 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x00000019 -#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x0000001a -#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x0000001b -#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x0000001c -#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x0000001e - -// SQ_UTCL1_CNTL2 -#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x00000000 -#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x00000008 -#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x00000009 -#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0x0000000a -#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0x0000000b -#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0x0000000c -#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0x0000000d -#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0x0000000e -#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0x0000000f -#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x00000010 -#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x0000001a -#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x0000001c - -// SQ_UTCL1_STATUS -#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 -#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x00000003 -#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x00000010 - -// SQ_TIME_HI -#define SQ_TIME_HI__TIME__SHIFT 0x00000000 - -// SQ_TIME_LO -#define SQ_TIME_LO__TIME__SHIFT 0x00000000 - -// SQ_LB_CTR_CTRL -#define SQ_LB_CTR_CTRL__START__SHIFT 0x00000000 -#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x00000001 -#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x00000002 - -// SQ_LB_DATA0 -#define SQ_LB_DATA0__DATA__SHIFT 0x00000000 - -// SQ_LB_DATA1 -#define SQ_LB_DATA1__DATA__SHIFT 0x00000000 - -// SQ_LB_DATA2 -#define SQ_LB_DATA2__DATA__SHIFT 0x00000000 - -// SQ_LB_DATA3 -#define SQ_LB_DATA3__DATA__SHIFT 0x00000000 - -// SQ_LB_CTR_SEL -#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x00000000 -#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x00000004 -#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x00000008 -#define SQ_LB_CTR_SEL__SEL3__SHIFT 0x0000000c - -// SQ_LB_CTR0_CU -#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x00000000 -#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x00000010 - -// SQ_LB_CTR1_CU -#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x00000000 -#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x00000010 - -// SQ_LB_CTR2_CU -#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x00000000 -#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x00000010 - -// SQ_LB_CTR3_CU -#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x00000000 -#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x00000010 - -// SQC_EDC_CNT -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x00000000 -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x00000002 -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x00000004 -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x00000006 -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x00000008 -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x0000000a -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x0000000c -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0x0000000e -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x00000010 -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x00000012 -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x00000014 -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x00000016 -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x00000018 -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x0000001a -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x0000001c -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x0000001e - -// SQ_EDC_SEC_CNT -#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x00000000 -#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x00000008 -#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x00000010 - -// SQ_EDC_DED_CNT -#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x00000000 -#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x00000008 -#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x00000010 - -// SQ_EDC_INFO -#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x00000000 -#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x00000004 -#define SQ_EDC_INFO__SOURCE__SHIFT 0x00000006 -#define SQ_EDC_INFO__VM_ID__SHIFT 0x00000009 - -// SQ_EDC_CNT -#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x00000000 -#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x00000002 -#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x00000004 -#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x00000006 -#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x00000008 -#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0x0000000a -#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0x0000000c -#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0x0000000e -#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x00000010 -#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x00000012 -#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x00000014 -#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x00000016 -#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x00000018 -#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x0000001a - -// SQ_EDC_FUE_CNTL -#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x00000000 -#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x00000010 - -// SQ_BUF_RSRC_WORD0 -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 - -// SQ_BUF_RSRC_WORD1 -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x00000010 -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x0000001e -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x0000001f - -// SQ_BUF_RSRC_WORD2 -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x00000000 - -// SQ_BUF_RSRC_WORD3 -#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 -#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0x0000000c -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0x0000000f -#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x00000013 -#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x00000014 -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x00000015 -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x00000017 -#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x0000001b -#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x0000001e - -// SQ_IMG_RSRC_WORD0 -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 - -// SQ_IMG_RSRC_WORD1 -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x00000008 -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x00000014 -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x0000001a -#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x0000001e -#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x0000001f - -// SQ_IMG_RSRC_WORD2 -#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0x0000000e -#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x0000001c - -// SQ_IMG_RSRC_WORD3 -#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 -#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0x0000000c -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x00000010 -#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x00000014 -#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x0000001c - -// SQ_IMG_RSRC_WORD4 -#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0x0000000d -#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x0000001d - -// SQ_IMG_RSRC_WORD5 -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0x0000000d -#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x00000011 -#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x00000019 -#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x0000001a -#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x0000001b -#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x0000001c - -// SQ_IMG_RSRC_WORD6 -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x00000000 -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0x0000000c -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x00000014 -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x00000015 -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x00000016 -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x00000017 -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x00000018 -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x0000001c - -// SQ_IMG_RSRC_WORD7 -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x00000000 - -// SQ_IMG_SAMP_WORD0 -#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x00000003 -#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x00000006 -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x00000009 -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0x0000000c -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0x0000000f -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x00000010 -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x00000013 -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x00000014 -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x00000015 -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x0000001b -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x0000001c -#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x0000001d -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x0000001f - -// SQ_IMG_SAMP_WORD1 -#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0x0000000c -#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x00000018 -#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x0000001c - -// SQ_IMG_SAMP_WORD2 -#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0x0000000e -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x00000014 -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x00000016 -#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x00000018 -#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x0000001a -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x0000001c -#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x0000001d -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x0000001e -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x0000001f - -// SQ_IMG_SAMP_WORD3 -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x00000000 -#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0x0000000c -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x0000001e - -// SQ_FLAT_SCRATCH_WORD0 -#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x00000000 - -// SQ_FLAT_SCRATCH_WORD1 -#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x00000000 - -// SQ_M0_GPR_IDX_WORD -#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x00000000 -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0x0000000c -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0x0000000d -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0x0000000e -#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0x0000000f - -// SQ_IND_INDEX -#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x00000000 -#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004 -#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x00000006 -#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0x0000000c -#define SQ_IND_INDEX__FORCE_READ__SHIFT 0x0000000d -#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0x0000000e -#define SQ_IND_INDEX__UNINDEXED__SHIFT 0x0000000f -#define SQ_IND_INDEX__INDEX__SHIFT 0x00000010 - -// SQ_CMD -#define SQ_CMD__CMD__SHIFT 0x00000000 -#define SQ_CMD__MODE__SHIFT 0x00000004 -#define SQ_CMD__CHECK_VMID__SHIFT 0x00000007 -#define SQ_CMD__DATA__SHIFT 0x00000008 -#define SQ_CMD__WAVE_ID__SHIFT 0x00000010 -#define SQ_CMD__SIMD_ID__SHIFT 0x00000014 -#define SQ_CMD__QUEUE_ID__SHIFT 0x00000018 -#define SQ_CMD__VM_ID__SHIFT 0x0000001c - -// SQ_IND_DATA -#define SQ_IND_DATA__DATA__SHIFT 0x00000000 - -// SQ_REG_TIMESTAMP -#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x00000000 - -// SQ_CMD_TIMESTAMP -#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x00000000 - -// SQ_DEBUG_STS_GLOBAL -#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 -#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 -#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 - -// SQ_DEBUG_STS_GLOBAL2 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 -#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 - -// SQ_DEBUG_STS_GLOBAL3 -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 -#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 - -// SH_MEM_BASES -#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x00000000 -#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x00000010 - -// SH_MEM_CONFIG -#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x00000000 -#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x00000003 -#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0x0000000c -#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0x0000000d - -// SQ_SHADER_TBA_LO -#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x00000000 - -// SQ_SHADER_TBA_HI -#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x00000000 - -// SQ_SHADER_TMA_LO -#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x00000000 - -// SQ_SHADER_TMA_HI -#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_WORD_CMN -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x00000004 - -// SQ_THREAD_TRACE_WORD_INST -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0x0000000b - -// SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0x0000000f -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x00000010 - -// SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x00000010 - -// SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x00000010 - -// SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_WORD_WAVE -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0x0000000e - -// SQ_THREAD_TRACE_WORD_MISC -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0x0000000d - -// SQ_THREAD_TRACE_WORD_WAVE_START -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x00000015 -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x00000016 -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x0000001d - -// SQ_THREAD_TRACE_WORD_REG_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x00000007 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0x0000000f -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x00000010 - -// SQ_THREAD_TRACE_WORD_REG_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x00000007 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x00000010 - -// SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_WORD_EVENT -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0x0000000a - -// SQ_THREAD_TRACE_WORD_ISSUE -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x00000008 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x00000012 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x00000014 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x00000016 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x00000018 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x0000001a - -// SQ_THREAD_TRACE_WORD_PERF_1_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x00000004 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0x0000000a -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x00000019 - -// SQ_THREAD_TRACE_WORD_PERF_2_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x00000013 - -// SQ_WREXEC_EXEC_LO -#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x00000000 - -// SQ_WREXEC_EXEC_HI -#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x00000000 -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x0000001a -#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x0000001b -#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x0000001c -#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x0000001f - -// SQC_ICACHE_UTCL1_CNTL1 -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x00000000 -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x00000001 -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x00000002 -#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x00000003 -#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x00000005 -#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x00000007 -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x00000011 -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x00000012 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x00000013 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x00000017 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x00000018 -#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x00000019 -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x0000001a -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x0000001b -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x0000001c -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x0000001e - -// SQC_ICACHE_UTCL1_CNTL2 -#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x00000000 -#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x00000008 -#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x00000009 -#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0x0000000a -#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0x0000000b -#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0x0000000c -#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0x0000000d -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0x0000000e -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0x0000000f -#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x00000010 -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x00000012 -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x00000013 -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x00000014 -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x00000015 -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x0000001a - -// SQC_DCACHE_UTCL1_CNTL1 -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x00000000 -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x00000001 -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x00000002 -#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x00000003 -#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x00000005 -#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x00000007 -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x00000011 -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x00000012 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x00000013 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x00000017 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x00000018 -#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x00000019 -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x0000001a -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x0000001b -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x0000001c -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x0000001e - -// SQC_DCACHE_UTCL1_CNTL2 -#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x00000000 -#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x00000008 -#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x00000009 -#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0x0000000a -#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0x0000000b -#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0x0000000c -#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0x0000000d -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0x0000000e -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0x0000000f -#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x00000010 -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x00000012 -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x00000013 -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x00000014 -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x00000015 -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x0000001a - -// SQC_ICACHE_UTCL1_STATUS -#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 - -// SQC_DCACHE_UTCL1_STATUS -#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 - -// SQC_CACHES -#define SQC_CACHES__TARGET_INST__SHIFT 0x00000000 -#define SQC_CACHES__TARGET_DATA__SHIFT 0x00000001 -#define SQC_CACHES__INVALIDATE__SHIFT 0x00000002 -#define SQC_CACHES__WRITEBACK__SHIFT 0x00000003 -#define SQC_CACHES__VOL__SHIFT 0x00000004 -#define SQC_CACHES__COMPLETE__SHIFT 0x00000010 - -// SQC_WRITEBACK -#define SQC_WRITEBACK__DWB__SHIFT 0x00000000 -#define SQC_WRITEBACK__DIRTY__SHIFT 0x00000001 - -// SQ_THREAD_TRACE_BASE -#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_BASE2 -#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_SIZE -#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_MASK -#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x00000005 -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x00000007 -#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x00000008 -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0x0000000e -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0x0000000f - -// SQ_THREAD_TRACE_USERDATA_0 -#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_USERDATA_1 -#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_USERDATA_2 -#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_USERDATA_3 -#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_MODE -#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x00000003 -#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x00000006 -#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x00000009 -#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0x0000000c -#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0x0000000f -#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x00000012 -#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x00000015 -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x00000017 -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x00000019 -#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x0000001a -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x0000001b -#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x0000001d -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x0000001e -#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x0000001f - -// SQ_THREAD_TRACE_CTRL -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x0000001f - -// SQ_THREAD_TRACE_TOKEN_MASK -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x00000018 - -// SQ_THREAD_TRACE_TOKEN_MASK2 -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_PERF_MASK -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x00000010 - -// SQ_THREAD_TRACE_WPTR -#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x0000001e - -// SQ_THREAD_TRACE_STATUS -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x00000000 -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x00000010 -#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x0000001c -#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x0000001d -#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x0000001e -#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x0000001f - -// SQ_THREAD_TRACE_CNTR -#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x00000000 - -// SQ_THREAD_TRACE_HIWATER -#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x00000000 - -// SQ_PERFCOUNTER0_LO -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER1_LO -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER2_LO -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER3_LO -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER4_LO -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER5_LO -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER6_LO -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER7_LO -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER8_LO -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER9_LO -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER10_LO -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER11_LO -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER12_LO -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER13_LO -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER14_LO -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER15_LO -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SQ_PERFCOUNTER0_HI -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER1_HI -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER2_HI -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER3_HI -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER4_HI -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER5_HI -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER6_HI -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER7_HI -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER8_HI -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER9_HI -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER10_HI -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER11_HI -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER12_HI -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER13_HI -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER14_HI -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER15_HI -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SQ_PERFCOUNTER_CTRL -#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x00000000 -#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x00000001 -#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x00000002 -#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x00000003 -#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x00000004 -#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x00000005 -#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x00000006 -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x00000008 -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0x0000000d - -// SQ_PERFCOUNTER_MASK -#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x00000000 -#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x00000010 - -// SQ_PERFCOUNTER_CTRL2 -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x00000000 - -// SQ_PERFCOUNTER0_SELECT -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER1_SELECT -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER2_SELECT -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER3_SELECT -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER4_SELECT -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER5_SELECT -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER6_SELECT -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER7_SELECT -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER8_SELECT -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER9_SELECT -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER10_SELECT -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER11_SELECT -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER12_SELECT -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER13_SELECT -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER14_SELECT -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x0000001c - -// SQ_PERFCOUNTER15_SELECT -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x00000000 -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x00000014 -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x00000018 -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x0000001c - -// CGTT_SQ_CLK_CTRL -#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x0000001d -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// CGTT_SQG_CLK_CTRL -#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x0000001c -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x0000001d -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// SQ_ALU_CLK_CTRL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 - -// SQ_TEX_CLK_CTRL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 - -// SQ_LDS_CLK_CTRL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 - -// SQ_POWER_THROTTLE -#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x00000000 -#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x00000010 -#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x0000001e - -// SQ_POWER_THROTTLE2 -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x0000001f - -// SQ_WAVE_INST_DW0 -#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x00000000 - -// SQ_WAVE_INST_DW1 -#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x00000000 - -// SQ_WAVE_PC_LO -#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x00000000 - -// SQ_WAVE_PC_HI -#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x00000000 - -// SQ_WAVE_IB_DBG0 -#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x00000000 -#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x00000003 -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x00000004 -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x00000005 -#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x00000008 -#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0x0000000a -#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x00000010 -#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x00000018 -#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x0000001a -#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x0000001b -#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x0000001d -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x0000001e -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x0000001f - -// SQ_WAVE_IB_DBG1 -#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x00000000 -#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x00000001 -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x00000002 -#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x00000004 -#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x0000000b -#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x00000012 -#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x00000019 - -// SQ_WAVE_FLUSH_IB -#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x00000000 - -// SQ_WAVE_EXEC_LO -#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x00000000 - -// SQ_WAVE_EXEC_HI -#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x00000000 - -// SQ_WAVE_STATUS -#define SQ_WAVE_STATUS__SCC__SHIFT 0x00000000 -#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x00000001 -#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x00000003 -#define SQ_WAVE_STATUS__PRIV__SHIFT 0x00000005 -#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x00000006 -#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x00000007 -#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x00000008 -#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x00000009 -#define SQ_WAVE_STATUS__VCCZ__SHIFT 0x0000000a -#define SQ_WAVE_STATUS__IN_TG__SHIFT 0x0000000b -#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0x0000000c -#define SQ_WAVE_STATUS__HALT__SHIFT 0x0000000d -#define SQ_WAVE_STATUS__TRAP__SHIFT 0x0000000e -#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0x0000000f -#define SQ_WAVE_STATUS__VALID__SHIFT 0x00000010 -#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x00000011 -#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x00000012 -#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x00000013 -#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x00000014 -#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x00000015 -#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x00000016 -#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x00000017 -#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x0000001b - -// SQ_WAVE_MODE -#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x00000000 -#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x00000004 -#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x00000008 -#define SQ_WAVE_MODE__IEEE__SHIFT 0x00000009 -#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0x0000000a -#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0x0000000b -#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0x0000000c -#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x00000017 -#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x00000018 -#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x00000019 -#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x0000001a -#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x0000001b -#define SQ_WAVE_MODE__VSKIP__SHIFT 0x0000001c -#define SQ_WAVE_MODE__CSP__SHIFT 0x0000001d - -// SQ_WAVE_TRAPSTS -#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x00000000 -#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0x0000000a -#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0x0000000b -#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0x0000000c -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x00000010 -#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x0000001c -#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x0000001d - -// SQ_WAVE_HW_ID -#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x00000000 -#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x00000004 -#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x00000006 -#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x00000008 -#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0x0000000c -#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0x0000000d -#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x00000010 -#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x00000014 -#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x00000018 -#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x0000001b -#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x0000001e - -// SQ_WAVE_GPR_ALLOC -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x00000000 -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x00000008 -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x00000010 -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x00000018 - -// SQ_WAVE_LDS_ALLOC -#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x00000000 -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0x0000000c - -// SQ_WAVE_IB_STS -#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x00000000 -#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x00000004 -#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x00000008 -#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0x0000000c -#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0x0000000f -#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x00000010 -#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x00000016 - -// SQ_WAVE_M0 -#define SQ_WAVE_M0__M0__SHIFT 0x00000000 - -// SQ_WAVE_TTMP0 -#define SQ_WAVE_TTMP0__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP1 -#define SQ_WAVE_TTMP1__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP2 -#define SQ_WAVE_TTMP2__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP3 -#define SQ_WAVE_TTMP3__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP4 -#define SQ_WAVE_TTMP4__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP5 -#define SQ_WAVE_TTMP5__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP6 -#define SQ_WAVE_TTMP6__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP7 -#define SQ_WAVE_TTMP7__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP8 -#define SQ_WAVE_TTMP8__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP9 -#define SQ_WAVE_TTMP9__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP10 -#define SQ_WAVE_TTMP10__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP11 -#define SQ_WAVE_TTMP11__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP12 -#define SQ_WAVE_TTMP12__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP13 -#define SQ_WAVE_TTMP13__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP14 -#define SQ_WAVE_TTMP14__DATA__SHIFT 0x00000000 - -// SQ_WAVE_TTMP15 -#define SQ_WAVE_TTMP15__DATA__SHIFT 0x00000000 - -// SQ_DEBUG_STS_LOCAL -#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 -#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004 - -// SQ_DEBUG_CTRL_LOCAL -#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x00000000 - -// SQ_INTERRUPT_WORD_CMN_HI -#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x00000008 -#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0x0000000a - -// SQ_INTERRUPT_WORD_AUTO_LO -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x00000001 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x00000002 -#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x00000003 -#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x00000004 -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x00000005 -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x00000006 -#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x00000007 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x00000008 - -// SQ_INTERRUPT_WORD_AUTO_HI -#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x00000008 -#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0x0000000a - -// SQ_INTERRUPT_WORD_WAVE_LO -#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x00000018 -#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x00000019 -#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x0000001a -#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x0000001e - -// SQ_INTERRUPT_WORD_WAVE_HI -#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x00000004 -#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x00000008 -#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0x0000000a - -// SQ_INTERRUPT_WORD_CMN_CTXID -#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x00000018 -#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x0000001a - -// SQ_INTERRUPT_WORD_AUTO_CTXID -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x00000001 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x00000002 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x00000003 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x00000004 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x00000005 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x00000006 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x00000007 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x00000008 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x00000018 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x0000001a - -// SQ_INTERRUPT_WORD_WAVE_CTXID -#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x00000000 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0x0000000c -#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0x0000000d -#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0x0000000e -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x00000012 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x00000014 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x00000018 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x0000001a - -// COMPUTE_DISPATCH_INITIATOR -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000 -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001 -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x00000004 -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x00000005 -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x00000006 -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0x0000000a -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0x0000000b -#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0x0000000c -#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0x0000000e - -// COMPUTE_DIM_X -#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000 - -// COMPUTE_DIM_Y -#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000 - -// COMPUTE_DIM_Z -#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000 - -// COMPUTE_START_X -#define COMPUTE_START_X__START__SHIFT 0x00000000 - -// COMPUTE_START_Y -#define COMPUTE_START_Y__START__SHIFT 0x00000000 - -// COMPUTE_START_Z -#define COMPUTE_START_Z__START__SHIFT 0x00000000 - -// COMPUTE_NUM_THREAD_X -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000 -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010 - -// COMPUTE_NUM_THREAD_Y -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000 -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010 - -// COMPUTE_NUM_THREAD_Z -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000 -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010 - -// COMPUTE_PIPELINESTAT_ENABLE -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x00000000 - -// COMPUTE_PERFCOUNT_ENABLE -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x00000000 - -// COMPUTE_PGM_LO -#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000 - -// COMPUTE_PGM_HI -#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000 - -// COMPUTE_DISPATCH_PKT_ADDR_LO -#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x00000000 - -// COMPUTE_DISPATCH_PKT_ADDR_HI -#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x00000000 - -// COMPUTE_DISPATCH_SCRATCH_BASE_LO -#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x00000000 - -// COMPUTE_DISPATCH_SCRATCH_BASE_HI -#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x00000000 - -// COMPUTE_PGM_RSRC1 -#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000 -#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006 -#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a -#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c -#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014 -#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015 -#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016 -#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017 -#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x00000018 -#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x00000019 -#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x0000001a - -// COMPUTE_PGM_RSRC2 -#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000 -#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001 -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006 -#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007 -#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008 -#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009 -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0x0000000d -#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f -#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018 -#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x0000001f - -// COMPUTE_VMID -#define COMPUTE_VMID__DATA__SHIFT 0x00000000 - -// COMPUTE_RESOURCE_LIMITS -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000 -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010 -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016 -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x00000017 -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x00000018 -#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x0000001b - -// COMPUTE_STATIC_THREAD_MGMT_SE0 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010 - -// COMPUTE_STATIC_THREAD_MGMT_SE1 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010 - -// COMPUTE_TMPRING_SIZE -#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000 -#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c - -// COMPUTE_STATIC_THREAD_MGMT_SE2 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x00000010 - -// COMPUTE_STATIC_THREAD_MGMT_SE3 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x00000000 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x00000010 - -// COMPUTE_RESTART_X -#define COMPUTE_RESTART_X__RESTART__SHIFT 0x00000000 - -// COMPUTE_RESTART_Y -#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x00000000 - -// COMPUTE_RESTART_Z -#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x00000000 - -// COMPUTE_THREAD_TRACE_ENABLE -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x00000000 - -// COMPUTE_MISC_RESERVED -#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x00000000 -#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x00000002 -#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x00000003 -#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x00000004 -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x00000005 - -// COMPUTE_DISPATCH_ID -#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x00000000 - -// COMPUTE_THREADGROUP_ID -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x00000000 - -// COMPUTE_RELAUNCH -#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x00000000 -#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x0000001e -#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x0000001f - -// COMPUTE_WAVE_RESTORE_ADDR_LO -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x00000000 - -// COMPUTE_WAVE_RESTORE_ADDR_HI -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_0 -#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_1 -#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_2 -#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_3 -#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_4 -#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_5 -#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_6 -#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_7 -#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_8 -#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_9 -#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_10 -#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_11 -#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_12 -#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_13 -#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_14 -#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000 - -// COMPUTE_USER_DATA_15 -#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000 - -// COMPUTE_NOWHERE -#define COMPUTE_NOWHERE__DATA__SHIFT 0x00000000 - -// CSPRIV_CONNECT -#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x00000000 -#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x00000015 -#define CSPRIV_CONNECT__RELAUNCH_WAVES__SHIFT 0x00000018 -#define CSPRIV_CONNECT__QSWITCH_MODE__SHIFT 0x00000019 -#define CSPRIV_CONNECT__VMID__SHIFT 0x0000001a -#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x0000001f - -// CSPRIV_CONNECT2 -#define CSPRIV_CONNECT2__DOORBELL_OFFSET__SHIFT 0x00000000 - -// CSPRIV_THREAD_TRACE_TG0 -#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x00000000 - -// CSPRIV_THREAD_TRACE_TG1 -#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x00000000 - -// CSPRIV_THREAD_TRACE_TG2 -#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x00000000 - -// CSPRIV_THREAD_TRACE_TG3 -#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x00000000 -#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0x0000000c -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x00000018 -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x00000019 -#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x0000001a -#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x0000001b -#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x0000001c - -// CSPRIV_THREAD_TRACE_EVENT -#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x00000000 - -// VGT_DMA_PRIMITIVE_TYPE -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x00000000 - -// VGT_DMA_CONTROL -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x00000000 -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x00000011 -#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x00000013 -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x00000014 -#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x00000015 -#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x00000016 -#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x00000017 - -// VGT_VTX_VECT_EJECT_REG -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 - -// VGT_DMA_DATA_FIFO_DEPTH -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x00000000 -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x00000009 - -// VGT_DMA_REQ_FIFO_DEPTH -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x00000000 - -// VGT_DRAW_INIT_FIFO_DEPTH -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x00000000 - -// VGT_LAST_COPY_STATE -#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 -#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 - -// CC_GC_SHADER_ARRAY_CONFIG -#define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 - -// GC_USER_SHADER_ARRAY_CONFIG -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 - -// VGT_CACHE_INVALIDATION -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x00000000 -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x00000004 -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x00000005 -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x00000006 -#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x00000009 -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0x0000000b -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0x0000000c -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0x0000000d -#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x00000010 -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x00000015 -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x00000016 -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x00000019 -#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x0000001c -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x0000001d - -// VGT_RESET_DEBUG -#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x00000000 -#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x00000001 -#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x00000002 - -// VGT_STRMOUT_DELAY -#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x00000000 -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x00000008 -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0x0000000b -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0x0000000e -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x00000011 - -// VGT_FIFO_DEPTHS -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x00000000 -#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x00000007 -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x00000008 -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x00000016 - -// VGT_GS_VERTEX_REUSE -#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x00000000 - -// VGT_MC_LAT_CNTL -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x00000000 - -// IA_CNTL_STATUS -#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x00000000 -#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x00000001 -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x00000002 -#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x00000003 -#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x00000004 - -// VGT_DMA_LS_HS_CONFIG -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x00000008 - -// VGT_SYS_CONFIG -#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x00000000 -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x00000001 -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x00000007 - -// WD_BUF_RESOURCE_1 -#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x00000000 -#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x00000010 - -// WD_BUF_RESOURCE_2 -#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x00000000 -#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0x0000000f -#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x00000010 - -// VGT_VS_MAX_WAVE_ID -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 - -// VGT_GS_MAX_WAVE_ID -#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 - -// WD_CNTL_STATUS -#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x00000000 -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x00000001 -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x00000002 -#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x00000003 - -// GFX_PIPE_CONTROL -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x00000000 -#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0x0000000d -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x00000010 - -// VGT_DEBUG_CNTL -#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 -#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x00000006 - -// VGT_DEBUG_DATA -#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// IA_DEBUG_CNTL -#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x00000000 -#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x00000006 - -// IA_DEBUG_DATA -#define IA_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// VGT_CNTL_STATUS -#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000001 -#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000002 -#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000003 -#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x00000004 -#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000005 -#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x00000006 -#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x00000007 -#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x00000008 -#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x00000009 -#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0x0000000a - -// WD_DEBUG_CNTL -#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x00000000 -#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x00000006 - -// WD_DEBUG_DATA -#define WD_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// WD_QOS -#define WD_QOS__DRAW_STALL__SHIFT 0x00000000 - -// WD_UTCL1_CNTL -#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x00000017 -#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x00000018 -#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x00000019 -#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x0000001a -#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x0000001c -#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d - -// WD_UTCL1_STATUS -#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 -#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x00000008 -#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x00000010 -#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x00000018 - -// IA_UTCL1_CNTL -#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x00000017 -#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x00000018 -#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x00000019 -#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x0000001a -#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x0000001c -#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d - -// IA_UTCL1_STATUS -#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 -#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x00000008 -#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x00000010 -#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x00000018 - -// CC_GC_PRIM_CONFIG -#define CC_GC_PRIM_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x00000010 -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x00000018 - -// GC_USER_PRIM_CONFIG -#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x00000010 -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x00000018 - -// CS_COPY_STATE -#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 - -// GFX_COPY_STATE -#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 - -// VGT_DRAW_INITIATOR -#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000000 -#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x00000002 -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x00000004 -#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x00000005 -#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x00000006 -#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x00000007 -#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x00000008 -#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x0000001d - -// VGT_DRAW_PAYLOAD_CNTL -#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x00000000 -#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x00000001 -#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x00000002 -#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x00000003 - -// VGT_INDEX_PAYLOAD_CNTL -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x00000000 - -// VGT_EVENT_INITIATOR -#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 -#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x0000000a -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x0000001b - -// VGT_DMA_EVENT_INITIATOR -#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 -#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x0000000a -#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x0000001b - -// VGT_EVENT_ADDRESS_REG -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x00000000 - -// VGT_GS_MAX_PRIMS_PER_SUBGROUP -#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x00000000 - -// VGT_DMA_BASE_HI -#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x00000000 - -// VGT_DMA_BASE -#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 - -// VGT_DMA_INDEX_TYPE -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 -#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x00000002 -#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x00000004 -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x00000006 -#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x00000008 -#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x00000009 -#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0x0000000a - -// VGT_DMA_NUM_INSTANCES -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 - -// IA_ENHANCE -#define IA_ENHANCE__MISC__SHIFT 0x00000000 - -// VGT_DMA_SIZE -#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x00000000 - -// VGT_DMA_MAX_SIZE -#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x00000000 - -// VGT_IMMED_DATA -#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 - -// VGT_PRIMITIVEID_EN -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x00000000 -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x00000001 -#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x00000002 - -// VGT_PRIMITIVEID_RESET -#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x00000000 - -// VGT_VTX_CNT_EN -#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x00000000 - -// VGT_REUSE_OFF -#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x00000000 - -// VGT_INSTANCE_STEP_RATE_0 -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x00000000 - -// VGT_INSTANCE_STEP_RATE_1 -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x00000000 - -// VGT_VERTEX_REUSE_BLOCK_CNTL -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 - -// VGT_OUT_DEALLOC_CNTL -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 - -// VGT_MULTI_PRIM_IB_RESET_INDX -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 - -// VGT_ENHANCE -#define VGT_ENHANCE__MISC__SHIFT 0x00000000 - -// VGT_OUTPUT_PATH_CNTL -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x00000000 - -// VGT_HOS_CNTL -#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x00000000 - -// VGT_HOS_MAX_TESS_LEVEL -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x00000000 - -// VGT_HOS_MIN_TESS_LEVEL -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x00000000 - -// VGT_HOS_REUSE_DEPTH -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x00000000 - -// VGT_GROUP_PRIM_TYPE -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x00000000 -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0x0000000e -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0x0000000f -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x00000010 - -// VGT_GROUP_FIRST_DECR -#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x00000000 - -// VGT_GROUP_DECR -#define VGT_GROUP_DECR__DECR__SHIFT 0x00000000 - -// VGT_GROUP_VECT_0_CNTL -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x00000000 -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x00000001 -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x00000002 -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x00000003 -#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x00000008 -#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x00000010 - -// VGT_GROUP_VECT_1_CNTL -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x00000000 -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x00000001 -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x00000002 -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x00000003 -#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x00000008 -#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x00000010 - -// VGT_GROUP_VECT_0_FMT_CNTL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x00000000 -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x00000008 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x00000010 -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x00000018 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c - -// VGT_GROUP_VECT_1_FMT_CNTL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x00000000 -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x00000008 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x00000010 -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x00000018 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c - -// VGT_GS_MODE -#define VGT_GS_MODE__MODE__SHIFT 0x00000000 -#define VGT_GS_MODE__RESERVED_0__SHIFT 0x00000003 -#define VGT_GS_MODE__CUT_MODE__SHIFT 0x00000004 -#define VGT_GS_MODE__RESERVED_1__SHIFT 0x00000006 -#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0x0000000b -#define VGT_GS_MODE__RESERVED_2__SHIFT 0x0000000c -#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0x0000000d -#define VGT_GS_MODE__RESERVED_3__SHIFT 0x0000000e -#define VGT_GS_MODE__RESERVED_4__SHIFT 0x0000000f -#define VGT_GS_MODE__RESERVED_5__SHIFT 0x00000010 -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x00000011 -#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x00000012 -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x00000013 -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x00000014 -#define VGT_GS_MODE__ONCHIP__SHIFT 0x00000015 - -// VGT_GS_ONCHIP_CNTL -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x00000000 -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0x0000000b -#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x00000016 - -// VGT_GS_OUT_PRIM_TYPE -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x00000000 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x00000008 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x00000010 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x00000016 -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x0000001f - -// VGT_GS_PER_ES -#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x00000000 - -// VGT_ES_PER_GS -#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x00000000 - -// VGT_GS_PER_VS -#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x00000000 - -// VGT_STRMOUT_CONFIG -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x00000000 -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x00000001 -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x00000002 -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x00000003 -#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x00000004 -#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x00000007 -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x00000008 -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x0000001f - -// VGT_STRMOUT_BUFFER_SIZE_0 -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_SIZE_1 -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_SIZE_2 -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_SIZE_3 -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_OFFSET_0 -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_OFFSET_1 -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_OFFSET_2 -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_OFFSET_3 -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x00000000 - -// VGT_STRMOUT_VTX_STRIDE_0 -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x00000000 - -// VGT_STRMOUT_VTX_STRIDE_1 -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x00000000 - -// VGT_STRMOUT_VTX_STRIDE_2 -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x00000000 - -// VGT_STRMOUT_VTX_STRIDE_3 -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_CONFIG -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x00000000 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x00000004 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x00000008 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0x0000000c - -// VGT_STRMOUT_DRAW_OPAQUE_OFFSET -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x00000000 - -// VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x00000000 - -// VGT_GS_MAX_VERT_OUT -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x00000000 - -// VGT_SHADER_STAGES_EN -#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x00000000 -#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x00000002 -#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x00000003 -#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x00000005 -#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x00000006 -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x00000009 -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0x0000000a -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0x0000000b -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0x0000000c -#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0x0000000d -#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0x0000000e -#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0x0000000f -#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x00000013 - -// VGT_DISPATCH_DRAW_INDEX -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x00000000 - -// VGT_LS_HS_CONFIG -#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x00000000 -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x00000008 -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0x0000000e - -// VGT_TF_PARAM -#define VGT_TF_PARAM__TYPE__SHIFT 0x00000000 -#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x00000002 -#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x00000005 -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x00000008 -#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x00000009 -#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0x0000000e -#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0x0000000f -#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x00000011 - -// VGT_TESS_DISTRIBUTION -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x00000000 -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x00000008 -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x00000010 -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x00000018 -#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x0000001d - -// VGT_GS_INSTANCE_CNT -#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x00000000 -#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x00000002 - -// VGT_GSVS_RING_OFFSET_1 -#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x00000000 - -// VGT_GSVS_RING_OFFSET_2 -#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x00000000 - -// VGT_GSVS_RING_OFFSET_3 -#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x00000000 - -// VGT_ESGS_RING_ITEMSIZE -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 - -// VGT_GSVS_RING_ITEMSIZE -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 - -// VGT_GS_VERT_ITEMSIZE -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 - -// VGT_GS_VERT_ITEMSIZE_1 -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x00000000 - -// VGT_GS_VERT_ITEMSIZE_2 -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x00000000 - -// VGT_GS_VERT_ITEMSIZE_3 -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x00000000 - -// WD_ENHANCE -#define WD_ENHANCE__MISC__SHIFT 0x00000000 - -// VGT_OBJECT_ID -#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x00000000 - -// VGT_INDEX_TYPE -#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 -#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x00000008 - -// VGT_NUM_INDICES -#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x00000000 - -// VGT_NUM_INSTANCES -#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 - -// VGT_PRIMITIVE_TYPE -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x00000000 - -// VGT_MAX_VTX_INDX -#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 - -// VGT_MIN_VTX_INDX -#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 - -// VGT_INDX_OFFSET -#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 - -// VGT_MULTI_PRIM_IB_RESET_EN -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x00000000 -#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x00000001 - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_1 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_2 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x00000000 - -// VGT_STRMOUT_BUFFER_FILLED_SIZE_3 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x00000000 - -// VGT_TF_RING_SIZE -#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x00000000 - -// VGT_HS_OFFCHIP_PARAM -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x00000000 -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x00000009 - -// VGT_TF_MEMORY_BASE -#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x00000000 - -// VGT_TF_MEMORY_BASE_HI -#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// WD_POS_BUF_BASE -#define WD_POS_BUF_BASE__BASE__SHIFT 0x00000000 - -// WD_POS_BUF_BASE_HI -#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// WD_CNTL_SB_BUF_BASE -#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x00000000 - -// WD_CNTL_SB_BUF_BASE_HI -#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// WD_INDEX_BUF_BASE -#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x00000000 - -// WD_INDEX_BUF_BASE_HI -#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// IA_MULTI_VGT_PARAM -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x00000000 -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x00000010 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x00000011 -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x00000012 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x00000013 -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x00000014 -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x00000015 -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x00000016 -#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x00000017 - -// VGT_GSVS_RING_SIZE -#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 - -// VGT_INSTANCE_BASE_ID -#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x00000000 - -// VGT_PERFCOUNTER0_LO -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// VGT_PERFCOUNTER1_LO -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// VGT_PERFCOUNTER2_LO -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// VGT_PERFCOUNTER3_LO -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// VGT_PERFCOUNTER0_HI -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// VGT_PERFCOUNTER1_HI -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// VGT_PERFCOUNTER2_HI -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// VGT_PERFCOUNTER3_HI -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// IA_PERFCOUNTER0_LO -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// IA_PERFCOUNTER1_LO -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// IA_PERFCOUNTER2_LO -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// IA_PERFCOUNTER3_LO -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// IA_PERFCOUNTER0_HI -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// IA_PERFCOUNTER1_HI -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// IA_PERFCOUNTER2_HI -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// IA_PERFCOUNTER3_HI -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// WD_PERFCOUNTER0_LO -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// WD_PERFCOUNTER1_LO -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// WD_PERFCOUNTER2_LO -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// WD_PERFCOUNTER3_LO -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// WD_PERFCOUNTER0_HI -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// WD_PERFCOUNTER1_HI -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// WD_PERFCOUNTER2_HI -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// WD_PERFCOUNTER3_HI -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// VGT_PERFCOUNTER_SEID_MASK -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x00000000 - -// VGT_PERFCOUNTER0_SELECT -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// VGT_PERFCOUNTER1_SELECT -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// VGT_PERFCOUNTER2_SELECT -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// VGT_PERFCOUNTER3_SELECT -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// VGT_PERFCOUNTER0_SELECT1 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// VGT_PERFCOUNTER1_SELECT1 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// IA_PERFCOUNTER0_SELECT -#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// IA_PERFCOUNTER1_SELECT -#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// IA_PERFCOUNTER2_SELECT -#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// IA_PERFCOUNTER3_SELECT -#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// IA_PERFCOUNTER0_SELECT1 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// WD_PERFCOUNTER0_SELECT -#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// WD_PERFCOUNTER1_SELECT -#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// WD_PERFCOUNTER2_SELECT -#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// WD_PERFCOUNTER3_SELECT -#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// CGTT_VGT_CLK_CTRL -#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x0000000f -#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x00000010 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x00000018 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x00000019 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x0000001a -#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x0000001b -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x0000001c -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// CGTT_IA_CLK_CTRL -#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 -#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// CGTT_WD_CLK_CTRL -#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x0000000f -#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x00000010 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x00000019 -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x0000001a -#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x0000001b -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x0000001c -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001d -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x0000001e -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f - -// VGT_DEBUG_REG0 -#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x00000000 -#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x00000001 -#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x00000002 -#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x00000003 -#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x00000004 -#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x00000005 -#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x00000006 -#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x00000007 -#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x00000008 -#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x00000009 -#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0x0000000a -#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0x0000000b -#define VGT_DEBUG_REG0__gs_busy__SHIFT 0x0000000c -#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0x0000000d -#define VGT_DEBUG_REG0__tm_busy__SHIFT 0x0000000e -#define VGT_DEBUG_REG0__cm_busy__SHIFT 0x0000000f -#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x00000010 -#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x00000011 -#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x00000012 -#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x00000013 -#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x00000014 -#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x00000015 -#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x00000016 -#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x00000017 -#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 -#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x00000019 -#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a -#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x0000001b -#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x0000001c -#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d -#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x0000001e -#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x0000001f - -// VGT_DEBUG_REG1 -#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x00000000 -#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x00000001 -#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x00000002 -#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x00000003 -#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x00000004 -#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x00000005 -#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x00000006 -#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x00000007 -#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x00000008 -#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x00000009 -#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0x0000000a -#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0x0000000b -#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0x0000000c -#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0x0000000d -#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0x0000000e -#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000f -#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000010 -#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x00000011 -#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000012 -#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x00000013 -#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000014 -#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x00000015 -#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000016 -#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x00000017 -#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000018 -#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x00000019 -#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x0000001a -#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x0000001b -#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x0000001c -#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x0000001d -#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x0000001e -#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x0000001f - -// VGT_DEBUG_REG2 -#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x00000000 -#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x00000001 -#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x00000002 -#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x00000003 -#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x00000005 -#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x00000006 -#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x00000007 -#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x00000008 -#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x00000009 -#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0x0000000a -#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0x0000000b -#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0x0000000c -#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0x0000000d -#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0x0000000e -#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0x0000000f -#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x00000010 -#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x00000011 -#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x00000012 -#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x00000013 -#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x00000014 -#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x00000015 -#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x00000016 -#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x00000017 -#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x00000018 -#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x00000019 -#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x0000001a -#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x0000001b -#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x0000001c -#define VGT_DEBUG_REG2__SPARE__SHIFT 0x0000001d - -// VGT_DEBUG_REG3 -#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x00000000 -#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0x0000000c -#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x00000012 -#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x0000001a - -// VGT_DEBUG_REG4 -#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x00000000 -#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x00000008 -#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x00000018 -#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x0000001d -#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x0000001e -#define VGT_DEBUG_REG4__SPARE__SHIFT 0x0000001f - -// VGT_DEBUG_REG5 -#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x00000000 -#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x00000003 -#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x00000008 -#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0x0000000b -#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x00000010 -#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x00000013 -#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x00000018 -#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x0000001b - -// VGT_DEBUG_REG6 -#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x00000000 -#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x00000010 - -// VGT_DEBUG_REG7 -#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x00000000 -#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x00000001 -#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x00000003 -#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG7__SPARE__SHIFT 0x00000005 -#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x00000010 - -// VGT_DEBUG_REG8 -#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x00000001 -#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x00000002 -#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x00000003 -#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x00000008 -#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0x0000000a -#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0x0000000e -#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0x0000000f -#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x00000010 -#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x00000011 -#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x00000012 -#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x00000014 -#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x00000015 -#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x00000017 -#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x00000018 -#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x00000019 -#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x0000001c -#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x0000001d -#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x0000001e -#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x0000001f - -// VGT_DEBUG_REG9 -#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x00000002 -#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x00000003 -#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x00000004 -#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x00000005 -#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x00000006 -#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x00000007 -#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x00000008 -#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x00000009 -#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0x0000000a -#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x00000017 -#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x00000019 -#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x0000001a -#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x0000001c -#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x0000001d -#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x0000001e -#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x0000001f - -// VGT_DEBUG_REG10 -#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x00000009 -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0x0000000b -#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0x0000000d -#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x00000017 - -// VGT_DEBUG_REG11 -#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x00000001 -#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x00000002 -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x00000003 -#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x00000004 -#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x00000005 -#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x00000006 -#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x00000007 -#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x00000008 -#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x00000009 -#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0x0000000a -#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0x0000000b -#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0x0000000c -#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x00000010 -#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x00000011 -#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x00000012 -#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x00000013 -#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x00000014 -#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x00000015 -#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x00000016 -#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x00000017 -#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x00000018 -#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x00000019 -#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x0000001a -#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x0000001b -#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x0000001c -#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x0000001d -#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x0000001e -#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x0000001f - -// VGT_DEBUG_REG12 -#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x00000003 -#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x0000001e -#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x0000001f - -// VGT_DEBUG_REG13 -#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x00000003 -#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x00000012 -#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x00000016 -#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x00000017 -#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x00000018 -#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x00000019 -#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x0000001a -#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x0000001b - -// VGT_DEBUG_REG14 -#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x00000000 -#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x00000004 -#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x00000005 -#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x00000006 -#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x00000007 -#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x00000009 -#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0x0000000b -#define VGT_DEBUG_REG14__SPARE2__SHIFT 0x0000000c -#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x00000015 -#define VGT_DEBUG_REG14__SPARE__SHIFT 0x00000016 -#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x00000019 -#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x0000001a -#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x0000001b -#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x0000001c -#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x0000001d -#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x0000001e -#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x0000001f - -// VGT_DEBUG_REG15 -#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x00000001 -#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x00000002 -#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x00000003 -#define VGT_DEBUG_REG15__counters_full__SHIFT 0x00000004 -#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x00000014 -#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x0000001c -#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x0000001d - -// VGT_DEBUG_REG16 -#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x00000000 -#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x00000001 -#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x00000005 -#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x00000006 -#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x00000007 -#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x00000008 -#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x00000009 -#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0x0000000a -#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0x0000000d -#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x00000010 -#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x00000017 -#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x00000019 -#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x0000001c -#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x0000001d -#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x0000001e -#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x0000001f - -// VGT_DEBUG_REG17 -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x00000000 -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x00000006 -#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0x0000000c -#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x00000012 - -// VGT_DEBUG_REG18 -#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x00000000 -#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x00000001 -#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x00000003 -#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x00000005 -#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x00000006 -#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x00000007 -#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x00000008 -#define VGT_DEBUG_REG18__valid_indices__SHIFT 0x0000000b -#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0x0000000c -#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0x0000000d -#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0x0000000e -#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0x0000000f -#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x00000010 -#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x00000011 -#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x00000012 -#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x00000017 -#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x0000001c -#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x0000001d - -// VGT_DEBUG_REG19 -#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x00000001 -#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x00000002 -#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x00000003 -#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x00000008 -#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG19__hold_prim__SHIFT 0x0000000b -#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0x0000000d -#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x00000010 -#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x00000011 -#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x00000012 -#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x00000013 -#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x00000014 -#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x0000001c -#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x0000001e -#define VGT_DEBUG_REG19__filter_event__SHIFT 0x0000001f - -// VGT_DEBUG_REG20 -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x00000000 -#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x00000010 -#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x00000011 -#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x0000001d -#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x0000001e -#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x0000001f - -// VGT_DEBUG_REG21 -#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x00000000 -#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x00000001 -#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x00000003 -#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x00000004 -#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x00000005 -#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x00000006 -#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x00000007 -#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x00000008 -#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x00000009 -#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0x0000000a -#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0x0000000b -#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0x0000000d -#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x00000010 -#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x00000015 -#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x00000016 -#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x00000017 -#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x00000018 -#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x00000019 -#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x0000001b -#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x0000001c -#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x0000001d -#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x0000001e -#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x0000001f - -// VGT_DEBUG_REG22 -#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x00000000 -#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x00000002 -#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x00000004 -#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x00000006 -#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x00000008 -#define VGT_DEBUG_REG22__cm_state21__SHIFT 0x0000000a -#define VGT_DEBUG_REG22__cm_state22__SHIFT 0x0000000c -#define VGT_DEBUG_REG22__cm_state23__SHIFT 0x0000000e -#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x00000010 -#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x00000012 -#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x00000014 -#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x00000016 -#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x00000018 -#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x0000001a -#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x0000001c -#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x0000001e - -// VGT_DEBUG_REG23 -#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x00000000 -#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x00000001 -#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x00000002 -#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x00000003 -#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x00000005 -#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x00000006 -#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x00000007 -#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x00000008 -#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x00000009 -#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0x0000000a -#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0x0000000d -#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG23__SPARE__SHIFT 0x00000018 - -// VGT_DEBUG_REG24 -#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x00000000 -#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x0000001a - -// VGT_DEBUG_REG25 -#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x00000000 -#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x0000001e -#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x0000001f - -// VGT_DEBUG_REG26 -#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x00000000 -#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x00000002 -#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x00000004 -#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x00000006 -#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x00000008 -#define VGT_DEBUG_REG26__cm_state5__SHIFT 0x0000000a -#define VGT_DEBUG_REG26__cm_state6__SHIFT 0x0000000c -#define VGT_DEBUG_REG26__cm_state7__SHIFT 0x0000000e -#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x00000010 -#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x00000012 -#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x00000014 -#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x00000016 -#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x00000018 -#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x0000001a -#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x0000001c -#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x0000001e - -// VGT_DEBUG_REG27 -#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x00000000 -#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x00000001 -#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x00000003 -#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x00000005 -#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x00000006 -#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x00000008 -#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x00000010 -#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x00000012 -#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x00000013 -#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x0000001f - -// VGT_DEBUG_REG28 -#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x00000008 -#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x00000009 -#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0x0000000a -#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x00000010 -#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x00000013 -#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x00000014 -#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x00000016 -#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x00000017 -#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x00000019 -#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x0000001a -#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x0000001c -#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x0000001d -#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x0000001e -#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x0000001f - -// VGT_DEBUG_REG29 -#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x00000008 -#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x00000009 -#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0x0000000a -#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x00000010 -#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x00000013 -#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x00000014 -#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x00000016 -#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x00000017 -#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x00000019 -#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x0000001a -#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x0000001c -#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x0000001d -#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x0000001e -#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x0000001f - -// VGT_DEBUG_REG30 -#define VGT_DEBUG_REG30__te_vert_fifo_full__SHIFT 0x00000000 -#define VGT_DEBUG_REG30__te_pg_prim_fifo_full__SHIFT 0x00000001 -#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG30__pipe1_dr__SHIFT 0x00000003 -#define VGT_DEBUG_REG30__esvert_fifo_empty__SHIFT 0x00000004 -#define VGT_DEBUG_REG30__gsprim_fifo_empty__SHIFT 0x00000005 -#define VGT_DEBUG_REG30__gswave_fifo_empty__SHIFT 0x00000006 -#define VGT_DEBUG_REG30__eswave_fifo_empty__SHIFT 0x00000007 -#define VGT_DEBUG_REG30__vgt_subgrp_grant_fifo_empty__SHIFT 0x00000008 -#define VGT_DEBUG_REG30__subgrp_data_fifo_empty__SHIFT 0x00000009 -#define VGT_DEBUG_REG30__VGT_SPI_esvert_busy__SHIFT 0x0000000a -#define VGT_DEBUG_REG30__VGT_SPI_gsprim_busy__SHIFT 0x0000000b -#define VGT_DEBUG_REG30__VGT_WD_subgrp_req_busy__SHIFT 0x0000000c -#define VGT_DEBUG_REG30__VGT_SPI_subgrp_busy__SHIFT 0x0000000d -#define VGT_DEBUG_REG30__te_pg_prim_fifo_empty__SHIFT 0x0000000e -#define VGT_DEBUG_REG30__te_vert_fifo_empty__SHIFT 0x0000000f -#define VGT_DEBUG_REG30__new_indices_p2__SHIFT 0x00000010 -#define VGT_DEBUG_REG30__eosg_p2__SHIFT 0x00000012 -#define VGT_DEBUG_REG30__SPARE__SHIFT 0x00000013 - -// VGT_DEBUG_REG31 -#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x00000000 -#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x00000001 -#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x00000003 -#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x00000004 -#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x00000005 -#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x00000006 -#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x00000007 -#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x00000008 -#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x00000009 -#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0x0000000a -#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0x0000000b -#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0x0000000e -#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0x0000000f -#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x00000010 -#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x00000011 -#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x00000012 -#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x00000013 -#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x00000014 -#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x00000015 -#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x00000016 -#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x00000017 -#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x00000018 -#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x00000019 -#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x0000001a -#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x0000001b -#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x0000001c -#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x0000001d -#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x0000001e -#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x0000001f - -// VGT_DEBUG_REG32 -#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x00000000 -#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x00000001 -#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x00000002 -#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x00000003 -#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x00000004 -#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x00000005 -#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x00000008 -#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x00000009 -#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0x0000000c -#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0x0000000e -#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0x0000000f -#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x00000010 -#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x00000011 -#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x00000012 -#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x00000013 -#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x00000014 -#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x00000015 -#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x00000016 -#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x00000017 -#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x00000018 -#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x00000019 -#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x0000001a -#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG32__SPARE__SHIFT 0x0000001c - -// VGT_DEBUG_REG33 -#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x00000000 -#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x00000001 -#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x00000002 -#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x00000003 -#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x00000004 -#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x00000005 -#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x00000006 -#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x00000007 -#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x00000008 -#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x00000009 -#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0x0000000a -#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0x0000000b -#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0x0000000d -#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0x0000000e -#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x00000010 -#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x00000011 -#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x00000012 -#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x00000013 -#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x00000014 -#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x00000015 -#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x00000016 -#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x00000017 -#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x0000001a -#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x0000001c -#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x0000001d -#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x0000001e -#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x0000001f - -// VGT_DEBUG_REG34 -#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x00000000 -#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x00000004 -#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x00000005 -#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 -#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x00000007 -#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x00000008 -#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x00000009 -#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0x0000000a -#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0x0000000b -#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0x0000000c -#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0x0000000d -#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0x0000000e -#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0x0000000f -#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x00000010 -#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x00000011 -#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 -#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x00000013 -#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x00000014 -#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 -#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x00000016 -#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x00000017 -#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x00000018 -#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x00000019 -#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x0000001a -#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x0000001b -#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x0000001c -#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x0000001d -#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x0000001e -#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x0000001f - -// VGT_DEBUG_REG36 -#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x00000000 - -// IA_DEBUG_REG0 -#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x00000000 -#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x00000001 -#define IA_DEBUG_REG0__ia_busy__SHIFT 0x00000002 -#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x00000003 -#define IA_DEBUG_REG0__SPARE0__SHIFT 0x00000004 -#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x00000005 -#define IA_DEBUG_REG0__dma_busy__SHIFT 0x00000006 -#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x00000007 -#define IA_DEBUG_REG0__grp_busy__SHIFT 0x00000008 -#define IA_DEBUG_REG0__SPARE1__SHIFT 0x00000009 -#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0x0000000a -#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0x0000000b -#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0x0000000c -#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0x0000000d -#define IA_DEBUG_REG0__SPARE2__SHIFT 0x0000000e -#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 -#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x00000019 -#define IA_DEBUG_REG0__SPARE3__SHIFT 0x0000001a -#define IA_DEBUG_REG0__SPARE4__SHIFT 0x0000001b -#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x0000001c -#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d -#define IA_DEBUG_REG0__SPARE5__SHIFT 0x0000001e -#define IA_DEBUG_REG0__SPARE6__SHIFT 0x0000001f - -// IA_DEBUG_REG1 -#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x00000000 -#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x00000001 -#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x00000002 -#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x00000003 -#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x00000004 -#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x00000005 -#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x00000007 -#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x00000008 -#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x00000009 -#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0x0000000a -#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0x0000000b -#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0x0000000c -#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0x0000000d -#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0x0000000e -#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0x0000000f -#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x00000010 -#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x00000011 -#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x00000012 -#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x00000013 -#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x00000014 -#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x00000015 -#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x00000016 -#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x00000017 -#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x00000018 -#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x00000019 -#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x0000001a -#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x0000001b -#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x0000001c -#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x0000001d -#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x0000001e -#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x0000001f - -// IA_DEBUG_REG2 -#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x00000000 -#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x00000001 -#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x00000002 -#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x00000003 -#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x00000004 -#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x00000005 -#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x00000007 -#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x00000008 -#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x00000009 -#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0x0000000a -#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0x0000000b -#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0x0000000c -#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0x0000000d -#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0x0000000e -#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0x0000000f -#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x00000010 -#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x00000011 -#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x00000012 -#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x00000013 -#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x00000014 -#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x00000015 -#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x00000016 -#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x00000017 -#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x00000018 -#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x00000019 -#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x0000001a -#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x0000001b -#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x0000001c -#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x0000001d -#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x0000001e -#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x0000001f - -// IA_DEBUG_REG3 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x00000000 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x00000001 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x00000002 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x00000003 -#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x00000004 -#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x00000005 -#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x00000006 -#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x00000007 -#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x00000008 -#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x00000009 -#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0x0000000a -#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0x0000000b -#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0x0000000c -#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0x0000000d -#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0x0000000e -#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0x0000000f -#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x00000010 -#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x00000011 -#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x00000012 -#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x00000013 -#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x00000014 -#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x00000015 -#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x00000016 -#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x00000017 -#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x00000018 -#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x0000001a -#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x0000001b -#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x0000001c -#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x0000001d -#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x0000001e -#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x0000001f - -// IA_DEBUG_REG4 -#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x00000000 -#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x00000001 -#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x00000002 -#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x00000003 -#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x00000004 -#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x00000005 -#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x00000006 -#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x00000007 -#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x00000008 -#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x00000009 -#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0x0000000a -#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0x0000000b -#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0x0000000c -#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0x0000000d -#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0x0000000e -#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0x0000000f -#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x00000010 -#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x00000011 -#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x00000014 -#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x00000015 -#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x00000018 -#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x00000019 -#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x0000001a -#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x0000001c -#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x0000001d -#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x0000001e -#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x0000001f - -// IA_DEBUG_REG5 -#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x00000000 -#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x00000010 -#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x0000001e -#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x0000001f - -// IA_DEBUG_REG6 -#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x00000000 -#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x00000004 -#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x00000008 -#define IA_DEBUG_REG6__first_group_partial__SHIFT 0x0000000d -#define IA_DEBUG_REG6__second_group_partial__SHIFT 0x0000000e -#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0x0000000f -#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x00000010 -#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x00000015 -#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x00000016 -#define IA_DEBUG_REG6__extract_group__SHIFT 0x00000017 -#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x00000018 - -// IA_DEBUG_REG7 -#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x00000000 -#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x00000004 -#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x00000008 -#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0x0000000c -#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x00000010 -#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x00000014 -#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x00000017 -#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x00000018 -#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x00000019 -#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x0000001a -#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x0000001b -#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x0000001c -#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x0000001d -#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x0000001e -#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x0000001f - -// IA_DEBUG_REG8 -#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x00000000 -#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x00000005 -#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x00000006 -#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x00000007 -#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x00000008 -#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x00000009 -#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0x0000000a -#define IA_DEBUG_REG8__grp_continued__SHIFT 0x0000000b -#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0x0000000c -#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0x0000000f -#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x00000015 -#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x00000018 -#define IA_DEBUG_REG8__grp_eop__SHIFT 0x00000019 -#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x0000001a -#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x0000001b -#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x0000001c - -// IA_DEBUG_REG9 -#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x00000000 -#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x00000001 -#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x00000002 -#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x00000003 -#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x00000004 -#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x00000005 -#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x00000006 -#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x00000007 -#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x00000008 -#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x00000009 -#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0x0000000a -#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0x0000000b -#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0x0000000c -#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0x0000000d -#define IA_DEBUG_REG9__SPARE0__SHIFT 0x0000000e -#define IA_DEBUG_REG9__SPARE1__SHIFT 0x0000000f -#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x00000010 -#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x00000011 -#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x00000012 -#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x00000013 -#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x00000014 - -// WD_DEBUG_REG0 -#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x00000000 -#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x00000001 -#define WD_DEBUG_REG0__wd_busy__SHIFT 0x00000002 -#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x00000003 -#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x00000004 -#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x00000005 -#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x00000006 -#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x00000007 -#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x00000008 -#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x00000009 -#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0x0000000a -#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0x0000000b -#define WD_DEBUG_REG0__SPARE2__SHIFT 0x0000000c -#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0x0000000d -#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0x0000000e -#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0x0000000f -#define WD_DEBUG_REG0__SPARE3__SHIFT 0x00000010 -#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x00000011 -#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x00000012 -#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x00000013 -#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x00000014 -#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x00000015 -#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x00000016 -#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x00000017 -#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 -#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x00000019 -#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a -#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x0000001b -#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x0000001c -#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x0000001d -#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001e -#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x0000001f - -// WD_DEBUG_REG1 -#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x00000000 -#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x00000001 -#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x00000002 -#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x00000003 -#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x00000004 -#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x00000005 -#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x00000006 -#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x00000007 -#define WD_DEBUG_REG1__SPARE0__SHIFT 0x00000008 -#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x00000009 -#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0x0000000a -#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0x0000000b -#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0x0000000c -#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x00000011 -#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x00000014 -#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x0000001a -#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x0000001b -#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x0000001c -#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x0000001d -#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x0000001e -#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x0000001f - -// WD_DEBUG_REG2 -#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x00000000 -#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x00000001 -#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x00000002 -#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x00000003 -#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x00000004 -#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x00000005 -#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x00000006 -#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x00000007 -#define WD_DEBUG_REG2__SPARE0__SHIFT 0x00000008 -#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x00000009 -#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0x0000000a -#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0x0000000b -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0x0000000c -#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x00000011 -#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x00000014 -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x0000001a -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x0000001b -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x0000001c -#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x0000001d -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x0000001e -#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x0000001f - -// WD_DEBUG_REG3 -#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x00000000 -#define WD_DEBUG_REG3__SPARE0__SHIFT 0x00000001 -#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x00000002 -#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x00000003 -#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x00000004 -#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x00000005 -#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x00000006 -#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x00000007 -#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x00000008 -#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0x0000000a -#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0x0000000b -#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0x0000000c -#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0x0000000d -#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0x0000000e -#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0x0000000f -#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x00000010 -#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x00000011 -#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x00000012 -#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x00000013 -#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x00000014 -#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x00000015 -#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x00000016 -#define WD_DEBUG_REG3__SPARE1__SHIFT 0x00000017 -#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x00000018 -#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x00000019 -#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x0000001a -#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x0000001b -#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x0000001c -#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x0000001d -#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x0000001e -#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x0000001f - -// WD_DEBUG_REG4 -#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x00000000 -#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x00000001 -#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x00000002 -#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x00000003 -#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x00000004 -#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x00000005 -#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x00000006 -#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x00000007 -#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x00000008 -#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x00000009 -#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0x0000000a -#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0x0000000b -#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0x0000000c -#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0x0000000d -#define WD_DEBUG_REG4__di_type_p0__SHIFT 0x0000000e -#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x00000010 -#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x00000013 -#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x00000014 -#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x00000015 -#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x00000016 -#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x00000017 -#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x00000018 -#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x00000019 -#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x0000001a -#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x0000001b -#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x0000001c -#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x0000001d -#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x0000001e -#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x0000001f - -// WD_DEBUG_REG5 -#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x00000000 -#define WD_DEBUG_REG5__SPARE0__SHIFT 0x00000001 -#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x00000002 -#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x00000003 -#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x00000004 -#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x00000005 -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x00000006 -#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x00000007 -#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x00000008 -#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0x0000000a -#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0x0000000b -#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0x0000000c -#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0x0000000d -#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0x0000000e -#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0x0000000f -#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x00000010 -#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x00000011 -#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x00000012 -#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x00000013 -#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x00000014 -#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x00000015 -#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x00000016 -#define WD_DEBUG_REG5__SPARE1__SHIFT 0x00000017 -#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x00000018 -#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x00000019 -#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x0000001a -#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x0000001b -#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x0000001c -#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x0000001d -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x0000001e -#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x0000001f - -// WD_DEBUG_REG6 -#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x00000000 - -// WD_DEBUG_REG7 -#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x00000000 -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x00000001 -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x00000002 -#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x00000003 -#define WD_DEBUG_REG7__SPARE0__SHIFT 0x00000004 -#define WD_DEBUG_REG7__SPARE1__SHIFT 0x00000008 -#define WD_DEBUG_REG7__SPARE2__SHIFT 0x0000000c -#define WD_DEBUG_REG7__SPARE3__SHIFT 0x00000010 -#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x00000014 -#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x00000015 -#define WD_DEBUG_REG7__SPARE4__SHIFT 0x00000016 -#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x0000001c -#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x0000001d -#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x0000001e -#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x0000001f - -// WD_DEBUG_REG8 -#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x00000000 -#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x00000001 -#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x00000002 -#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x00000003 -#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x00000004 -#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x00000005 -#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x00000006 -#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x00000007 -#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x00000008 -#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x00000009 -#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0x0000000a -#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0x0000000b -#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0x0000000c -#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x00000012 -#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x00000013 -#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x00000014 -#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x0000001b -#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x0000001c -#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x0000001d -#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x0000001e -#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x0000001f - -// WD_DEBUG_REG9 -#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x00000000 -#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x00000001 -#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x00000002 -#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x00000003 -#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x00000004 -#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x00000005 -#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x00000006 -#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x00000007 -#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x00000008 -#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x00000009 -#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0x0000000a -#define WD_DEBUG_REG9__SPARE0__SHIFT 0x0000000b -#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x00000010 -#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x00000013 -#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x00000014 -#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x00000018 -#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x00000019 -#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x0000001a -#define WD_DEBUG_REG9__SPARE1__SHIFT 0x0000001b -#define WD_DEBUG_REG9__SPARE2__SHIFT 0x0000001c -#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x0000001e -#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x0000001f - -// WD_DEBUG_REG10 -#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x00000000 -#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x00000001 -#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x00000002 -#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x00000003 -#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x00000004 -#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x00000005 -#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x00000006 -#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x00000007 -#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x00000008 -#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x00000009 -#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0x0000000a -#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0x0000000b -#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0x0000000c -#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0x0000000d -#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0x0000000e -#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0x0000000f -#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x00000010 -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x00000018 -#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x00000019 -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x0000001a -#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x0000001b -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x0000001c -#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x0000001d -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x0000001e -#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x0000001f - -// WD_DEBUG_REG11 -#define WD_DEBUG_REG11__WD_SE0VGT_subgrp_grant_busy__SHIFT 0x00000000 -#define WD_DEBUG_REG11__WD_SE1VGT_subgrp_grant_busy__SHIFT 0x00000001 -#define WD_DEBUG_REG11__WD_SE2VGT_subgrp_grant_busy__SHIFT 0x00000002 -#define WD_DEBUG_REG11__WD_SE3VGT_subgrp_grant_busy__SHIFT 0x00000003 -#define WD_DEBUG_REG11__WD_SE0PA_sideband_active_busy__SHIFT 0x00000004 -#define WD_DEBUG_REG11__WD_SE1PA_sideband_active_busy__SHIFT 0x00000005 -#define WD_DEBUG_REG11__WD_SE2PA_sideband_active_busy__SHIFT 0x00000006 -#define WD_DEBUG_REG11__WD_SE3PA_sideband_active_busy__SHIFT 0x00000007 -#define WD_DEBUG_REG11__wd_sm_rm_req_valid__SHIFT 0x00000008 -#define WD_DEBUG_REG11__wd_sm_rm_req_eopg__SHIFT 0x00000009 -#define WD_DEBUG_REG11__wd_sm_rm_req_null__SHIFT 0x0000000a -#define WD_DEBUG_REG11__wd_sm_rm_req_state_sel__SHIFT 0x0000000b -#define WD_DEBUG_REG11__wd_sm_rm_req_eop__SHIFT 0x0000000e -#define WD_DEBUG_REG11__wd_sm_rm_req_is_event__SHIFT 0x0000000f -#define WD_DEBUG_REG11__curr_fe_id__SHIFT 0x00000010 -#define WD_DEBUG_REG11__SE0_subgrp_fifo_empty__SHIFT 0x00000012 -#define WD_DEBUG_REG11__SE2_subgrp_fifo_empty__SHIFT 0x00000013 -#define WD_DEBUG_REG11__SE1_subgrp_fifo_empty__SHIFT 0x00000014 -#define WD_DEBUG_REG11__SE3_subgrp_fifo_empty__SHIFT 0x00000015 -#define WD_DEBUG_REG11__SE0_subgrp_fifo_full__SHIFT 0x00000016 -#define WD_DEBUG_REG11__SE1_subgrp_fifo_full__SHIFT 0x00000017 -#define WD_DEBUG_REG11__SE2_subgrp_fifo_full__SHIFT 0x00000018 -#define WD_DEBUG_REG11__SE3_subgrp_fifo_full__SHIFT 0x00000019 -#define WD_DEBUG_REG11__SPARE__SHIFT 0x0000001a - -// WD_DEBUG_REG12 -#define WD_DEBUG_REG12__wd_csbm_sm_max_waves__SHIFT 0x00000000 -#define WD_DEBUG_REG12__SPARE1__SHIFT 0x00000003 -#define WD_DEBUG_REG12__wd_csbm_sm_ordered_id_mode__SHIFT 0x00000006 -#define WD_DEBUG_REG12__wd_csbm_sm_null_subgrp__SHIFT 0x00000007 -#define WD_DEBUG_REG12__wd_csbm_sm_curr_fe_id__SHIFT 0x00000008 -#define WD_DEBUG_REG12__wd_csbm_sm_fe_id__SHIFT 0x0000000a -#define WD_DEBUG_REG12__SPARE0__SHIFT 0x0000000c - -// WD_DEBUG_REG13 -#define WD_DEBUG_REG13__decr_p2__SHIFT 0x00000000 -#define WD_DEBUG_REG13__pe0_ld__SHIFT 0x00000001 -#define WD_DEBUG_REG13__ptpos0_ld__SHIFT 0x00000002 -#define WD_DEBUG_REG13__ptpar0_ld__SHIFT 0x00000003 -#define WD_DEBUG_REG13__pipe0_ld__SHIFT 0x00000004 -#define WD_DEBUG_REG13__pipe1_ld__SHIFT 0x00000005 -#define WD_DEBUG_REG13__pipe2_ld__SHIFT 0x00000006 -#define WD_DEBUG_REG13__SPARE0__SHIFT 0x00000007 - -// CC_RB_REDUNDANCY -#define CC_RB_REDUNDANCY__WRITE_DIS__SHIFT 0x00000000 -#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008 -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c -#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010 -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014 - -// CC_RB_BACKEND_DISABLE -#define CC_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT 0x00000000 -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 - -// GC_USER_RB_REDUNDANCY -#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008 -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c -#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010 -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014 - -// GC_USER_RB_BACKEND_DISABLE -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 - -// GB_ADDR_CONFIG -#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 -#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x00000006 -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 -#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0x0000000c -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x00000013 -#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000015 -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 -#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x0000001a -#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e -#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x0000001f - -// GB_ADDR_CONFIG_READ -#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x00000000 -#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 -#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x00000006 -#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 -#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0x0000000c -#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 -#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x00000013 -#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x00000015 -#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 -#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x0000001a -#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x0000001c -#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x0000001e -#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x0000001f - -// GB_BACKEND_MAP -#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x00000000 - -// GB_GPU_ID -#define GB_GPU_ID__GPU_ID__SHIFT 0x00000000 - -// CC_RB_DAISY_CHAIN -#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000 -#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004 -#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008 -#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c -#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010 -#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014 -#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018 -#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c - -// GB_TILE_MODE0 -#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE1 -#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE2 -#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE3 -#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE4 -#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE5 -#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE6 -#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE7 -#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE8 -#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE9 -#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE10 -#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE11 -#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE12 -#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE13 -#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE14 -#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE15 -#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE16 -#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE17 -#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE18 -#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE19 -#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE20 -#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE21 -#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE22 -#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE23 -#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE24 -#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE25 -#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE26 -#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE27 -#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE28 -#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE29 -#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE30 -#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_TILE_MODE31 -#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x00000002 -#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x00000006 -#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0x0000000b -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 -#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x00000019 - -// GB_MACROTILE_MODE0 -#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE1 -#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE2 -#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE3 -#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE4 -#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE5 -#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE6 -#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE7 -#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE8 -#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE9 -#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE10 -#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE11 -#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE12 -#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE13 -#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE14 -#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x00000006 - -// GB_MACROTILE_MODE15 -#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x00000000 -#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x00000002 -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x00000004 -#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x00000006 - -// GB_EDC_MODE -#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x0000000f -#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x00000010 -#define GB_EDC_MODE__GATE_FUE__SHIFT 0x00000011 -#define GB_EDC_MODE__DED_MODE__SHIFT 0x00000014 -#define GB_EDC_MODE__PROP_FED__SHIFT 0x0000001d -#define GB_EDC_MODE__BYPASS__SHIFT 0x0000001f - -// CC_GC_EDC_CONFIG -#define CC_GC_EDC_CONFIG__WRITE_DIS__SHIFT 0x00000000 -#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x00000001 - -// RAS_SIGNATURE_CONTROL -#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x00000000 - -// RAS_SIGNATURE_MASK -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x00000000 - -// RAS_SX_SIGNATURE0 -#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_SX_SIGNATURE1 -#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 - -// RAS_SX_SIGNATURE2 -#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 - -// RAS_SX_SIGNATURE3 -#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 - -// RAS_DB_SIGNATURE0 -#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_PA_SIGNATURE0 -#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_VGT_SIGNATURE0 -#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_SQ_SIGNATURE0 -#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE0 -#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE1 -#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE2 -#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE3 -#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE4 -#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE5 -#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE6 -#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x00000000 - -// RAS_SC_SIGNATURE7 -#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x00000000 - -// RAS_IA_SIGNATURE0 -#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_IA_SIGNATURE1 -#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 - -// RAS_SPI_SIGNATURE0 -#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_SPI_SIGNATURE1 -#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 - -// RAS_TA_SIGNATURE0 -#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_TD_SIGNATURE0 -#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_CB_SIGNATURE0 -#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_BCI_SIGNATURE0 -#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 - -// RAS_BCI_SIGNATURE1 -#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 - -// RAS_TA_SIGNATURE1 -#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 - -// TD_CNTL -#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x00000000 -#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x00000004 -#define TD_CNTL__PAD_STALL_EN__SHIFT 0x00000008 -#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x00000009 -#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0x0000000b -#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0x0000000f -#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x00000010 -#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x00000012 -#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x00000013 -#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x00000014 -#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x00000015 -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x00000017 -#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x00000018 - -// TD_STATUS -#define TD_STATUS__BUSY__SHIFT 0x0000001f - -// TD_DEBUG_INDEX -#define TD_DEBUG_INDEX__INDEX__SHIFT 0x00000000 - -// TD_DEBUG_DATA -#define TD_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// TD_DSM_CNTL -#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x00000003 -#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x00000006 -#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 - -// TD_DSM_CNTL2 -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x0000001a - -// TD_SCRATCH -#define TD_SCRATCH__SCRATCH__SHIFT 0x00000000 - -// TA_CNTL -#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x00000000 -#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x00000009 -#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0x0000000d -#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x00000010 -#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x00000016 - -// TA_CNTL_AUX -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x00000000 -#define TA_CNTL_AUX__RESERVED__SHIFT 0x00000001 -#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x00000005 -#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x00000006 -#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x00000007 -#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x00000009 -#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0x0000000a -#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0x0000000c -#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0x0000000d -#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0x0000000e -#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0x0000000f -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x00000010 -#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x00000011 -#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x00000012 -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x00000013 -#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x00000014 -#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x00000015 -#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x00000016 -#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x00000017 -#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x00000018 -#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x00000019 -#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x0000001a -#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x0000001b -#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x0000001c -#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x0000001d -#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x0000001e - -// TA_RESERVED_010C -#define TA_RESERVED_010C__Unused__SHIFT 0x00000000 - -// TA_GRAD_ADJ -#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x00000000 -#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x00000008 -#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x00000010 -#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x00000018 - -// TA_STATUS -#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0x0000000c -#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0x0000000d -#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0x0000000e -#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x00000010 -#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x00000011 -#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x00000012 -#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x00000014 -#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x00000015 -#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x00000016 -#define TA_STATUS__IN_BUSY__SHIFT 0x00000018 -#define TA_STATUS__FG_BUSY__SHIFT 0x00000019 -#define TA_STATUS__LA_BUSY__SHIFT 0x0000001a -#define TA_STATUS__FL_BUSY__SHIFT 0x0000001b -#define TA_STATUS__TA_BUSY__SHIFT 0x0000001c -#define TA_STATUS__FA_BUSY__SHIFT 0x0000001d -#define TA_STATUS__AL_BUSY__SHIFT 0x0000001e -#define TA_STATUS__BUSY__SHIFT 0x0000001f - -// TA_DEBUG_INDEX -#define TA_DEBUG_INDEX__INDEX__SHIFT 0x00000000 - -// TA_DEBUG_DATA -#define TA_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// TA_SCRATCH -#define TA_SCRATCH__SCRATCH__SHIFT 0x00000000 - -// TCP_INVALIDATE -#define TCP_INVALIDATE__START__SHIFT 0x00000000 - -// TCP_STATUS -#define TCP_STATUS__TCP_BUSY__SHIFT 0x00000000 -#define TCP_STATUS__INPUT_BUSY__SHIFT 0x00000001 -#define TCP_STATUS__ADRS_BUSY__SHIFT 0x00000002 -#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x00000003 -#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x00000004 -#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x00000005 -#define TCP_STATUS__READ_BUSY__SHIFT 0x00000006 -#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x00000007 -#define TCP_STATUS__VM_BUSY__SHIFT 0x00000008 - -// TCP_CNTL -#define TCP_CNTL__FORCE_HIT__SHIFT 0x00000000 -#define TCP_CNTL__FORCE_MISS__SHIFT 0x00000001 -#define TCP_CNTL__L1_SIZE__SHIFT 0x00000002 -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x00000004 -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x00000005 -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0x0000000f -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x00000016 -#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x0000001c -#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x0000001d -#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x0000001e - -// TCP_CHAN_STEER_LO -#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x00000000 -#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x00000004 -#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x00000008 -#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0x0000000c -#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x00000010 -#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x00000014 -#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x00000018 -#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x0000001c - -// TCP_CHAN_STEER_HI -#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x00000000 -#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x00000004 -#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x00000008 -#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0x0000000c -#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x00000010 -#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x00000014 -#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x00000018 -#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x0000001c - -// TCP_ADDR_CONFIG -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x00000000 -#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x00000004 -#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x00000006 -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x00000009 - -// TCP_CREDIT -#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x00000000 -#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x00000010 -#define TCP_CREDIT__TD_CREDIT__SHIFT 0x0000001d - -// TCP_DEBUG_INDEX -#define TCP_DEBUG_INDEX__INDEX__SHIFT 0x00000000 - -// TCP_DEBUG_DATA -#define TCP_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// TCP_BUFFER_ADDR_HASH_CNTL -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x00000000 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x00000008 -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x00000010 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x00000018 - -// TCP_EDC_CNT -#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x00000000 -#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x00000008 -#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x00000010 - -// TC_CFG_L1_LOAD_POLICY0 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x00000000 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x00000002 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x00000004 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x00000006 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x00000008 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0x0000000a -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0x0000000c -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0x0000000e -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x00000010 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x00000012 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x00000014 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x00000016 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x00000018 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x0000001a -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x0000001c -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x0000001e - -// TC_CFG_L1_LOAD_POLICY1 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x00000000 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x00000002 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x00000004 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x00000006 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x00000008 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0x0000000a -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0x0000000c -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0x0000000e -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x00000010 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x00000012 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x00000014 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x00000016 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x00000018 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x0000001a -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x0000001c -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x0000001e - -// TC_CFG_L1_STORE_POLICY -#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x00000000 -#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x00000001 -#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x00000002 -#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x00000003 -#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x00000004 -#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x00000005 -#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x00000006 -#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x00000007 -#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x00000008 -#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x00000009 -#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0x0000000a -#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0x0000000b -#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0x0000000c -#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0x0000000d -#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0x0000000e -#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0x0000000f -#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x00000010 -#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x00000011 -#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x00000012 -#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x00000013 -#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x00000014 -#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x00000015 -#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x00000016 -#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x00000017 -#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x00000018 -#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x00000019 -#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x0000001a -#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x0000001b -#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x0000001c -#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x0000001d -#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x0000001e -#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x0000001f - -// TC_CFG_L2_LOAD_POLICY0 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x00000000 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x00000002 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x00000004 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x00000006 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x00000008 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0x0000000a -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0x0000000c -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0x0000000e -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x00000010 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x00000012 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x00000014 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x00000016 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x00000018 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x0000001a -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x0000001c -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x0000001e - -// TC_CFG_L2_LOAD_POLICY1 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x00000000 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x00000002 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x00000004 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x00000006 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x00000008 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0x0000000a -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0x0000000c -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0x0000000e -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x00000010 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x00000012 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x00000014 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x00000016 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x00000018 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x0000001a -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x0000001c -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x0000001e - -// TC_CFG_L2_STORE_POLICY0 -#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x00000000 -#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x00000002 -#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x00000004 -#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x00000006 -#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x00000008 -#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0x0000000a -#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0x0000000c -#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0x0000000e -#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x00000010 -#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x00000012 -#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x00000014 -#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x00000016 -#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x00000018 -#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x0000001a -#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x0000001c -#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x0000001e - -// TC_CFG_L2_STORE_POLICY1 -#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x00000000 -#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x00000002 -#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x00000004 -#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x00000006 -#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x00000008 -#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0x0000000a -#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0x0000000c -#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0x0000000e -#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x00000010 -#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x00000012 -#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x00000014 -#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x00000016 -#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x00000018 -#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x0000001a -#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x0000001c -#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x0000001e - -// TC_CFG_L2_ATOMIC_POLICY -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x00000000 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x00000002 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x00000004 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x00000006 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x00000008 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0x0000000a -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0x0000000c -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0x0000000e -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x00000010 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x00000012 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x00000014 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x00000016 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x00000018 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x0000001a -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x0000001c -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x0000001e - -// TC_CFG_L1_VOLATILE -#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x00000000 - -// TC_CFG_L2_VOLATILE -#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x00000000 - -// TCI_STATUS -#define TCI_STATUS__TCI_BUSY__SHIFT 0x00000000 - -// TCI_CNTL_1 -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x00000000 -#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x00000010 -#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x00000018 - -// TCI_CNTL_2 -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x00000000 -#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x00000001 - -// TCP_WATCH0_ADDR_H -#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x00000000 - -// TCP_WATCH1_ADDR_H -#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x00000000 - -// TCP_WATCH2_ADDR_H -#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x00000000 - -// TCP_WATCH3_ADDR_H -#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x00000000 - -// TCP_WATCH0_ADDR_L -#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x00000006 - -// TCP_WATCH1_ADDR_L -#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x00000006 - -// TCP_WATCH2_ADDR_L -#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x00000006 - -// TCP_WATCH3_ADDR_L -#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x00000006 - -// TCP_WATCH0_CNTL -#define TCP_WATCH0_CNTL__MASK__SHIFT 0x00000000 -#define TCP_WATCH0_CNTL__VMID__SHIFT 0x00000018 -#define TCP_WATCH0_CNTL__ATC__SHIFT 0x0000001c -#define TCP_WATCH0_CNTL__MODE__SHIFT 0x0000001d -#define TCP_WATCH0_CNTL__VALID__SHIFT 0x0000001f - -// TCP_WATCH1_CNTL -#define TCP_WATCH1_CNTL__MASK__SHIFT 0x00000000 -#define TCP_WATCH1_CNTL__VMID__SHIFT 0x00000018 -#define TCP_WATCH1_CNTL__ATC__SHIFT 0x0000001c -#define TCP_WATCH1_CNTL__MODE__SHIFT 0x0000001d -#define TCP_WATCH1_CNTL__VALID__SHIFT 0x0000001f - -// TCP_WATCH2_CNTL -#define TCP_WATCH2_CNTL__MASK__SHIFT 0x00000000 -#define TCP_WATCH2_CNTL__VMID__SHIFT 0x00000018 -#define TCP_WATCH2_CNTL__ATC__SHIFT 0x0000001c -#define TCP_WATCH2_CNTL__MODE__SHIFT 0x0000001d -#define TCP_WATCH2_CNTL__VALID__SHIFT 0x0000001f - -// TCP_WATCH3_CNTL -#define TCP_WATCH3_CNTL__MASK__SHIFT 0x00000000 -#define TCP_WATCH3_CNTL__VMID__SHIFT 0x00000018 -#define TCP_WATCH3_CNTL__ATC__SHIFT 0x0000001c -#define TCP_WATCH3_CNTL__MODE__SHIFT 0x0000001d -#define TCP_WATCH3_CNTL__VALID__SHIFT 0x0000001f - -// TCP_GATCL1_CNTL -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x00000019 -#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x0000001a -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x0000001b -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x0000001c -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x0000001e - -// TCP_ATC_EDC_GATCL1_CNT -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x00000000 - -// TCP_GATCL1_DSM_CNTL -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x00000000 -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x00000001 -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x00000002 - -// TCP_CNTL2 -#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x00000000 - -// TCP_UTCL1_CNTL1 -#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x00000000 -#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x00000001 -#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x00000002 -#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x00000003 -#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x00000005 -#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x00000007 -#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x00000013 -#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x00000017 -#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x00000018 -#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x00000019 -#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x0000001a -#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x0000001c -#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x0000001e - -// TCP_UTCL1_CNTL2 -#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x00000000 -#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x00000009 -#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0x0000000a -#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0x0000000c -#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0x0000000e -#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0x0000000f -#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x0000001a - -// TCP_UTCL1_STATUS -#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 - -// TCP_PERFCOUNTER_FILTER -#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x00000000 -#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x00000001 -#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x00000002 -#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x00000005 -#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0x0000000b -#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x0000000f -#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x00000014 -#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x00000016 -#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x00000019 -#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x0000001a -#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x0000001b -#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x0000001c - -// TCP_PERFCOUNTER_FILTER_EN -#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x00000000 -#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x00000001 -#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x00000002 -#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x00000003 -#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x00000004 -#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x00000005 -#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x00000006 -#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x00000007 -#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x00000008 -#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x00000009 -#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0x0000000a -#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0x0000000b - -// TA_BC_BASE_ADDR -#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 - -// TA_BC_BASE_ADDR_HI -#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 - -// TA_CS_BC_BASE_ADDR -#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 - -// TA_CS_BC_BASE_ADDR_HI -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 - -// TA_GRAD_ADJ_UCONFIG -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x00000000 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x00000008 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x00000010 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x00000018 - -// TD_PERFCOUNTER0_LO -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TD_PERFCOUNTER1_LO -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TD_PERFCOUNTER0_HI -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TD_PERFCOUNTER1_HI -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TA_PERFCOUNTER0_LO -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TA_PERFCOUNTER1_LO -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TA_PERFCOUNTER0_HI -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TA_PERFCOUNTER1_HI -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCP_PERFCOUNTER0_LO -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCP_PERFCOUNTER1_LO -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCP_PERFCOUNTER2_LO -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCP_PERFCOUNTER3_LO -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCP_PERFCOUNTER0_HI -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCP_PERFCOUNTER1_HI -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCP_PERFCOUNTER2_HI -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCP_PERFCOUNTER3_HI -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TD_PERFCOUNTER0_SELECT -#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TD_PERFCOUNTER1_SELECT -#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TD_PERFCOUNTER0_SELECT1 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// TA_PERFCOUNTER0_SELECT -#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TA_PERFCOUNTER1_SELECT -#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TA_PERFCOUNTER0_SELECT1 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// TCP_PERFCOUNTER0_SELECT -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCP_PERFCOUNTER1_SELECT -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCP_PERFCOUNTER0_SELECT1 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// TCP_PERFCOUNTER1_SELECT1 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// TCP_PERFCOUNTER2_SELECT -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCP_PERFCOUNTER3_SELECT -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TD_CGTT_CTRL -#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// TA_CGTT_CTRL -#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// CGTT_TCPI_CLK_CTRL -#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0x0000000c -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// CGTT_TCPF_CLK_CTRL -#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0x0000000c -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// CGTT_TCI_CLK_CTRL -#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// TCC_CTRL -#define TCC_CTRL__CACHE_SIZE__SHIFT 0x00000000 -#define TCC_CTRL__RATE__SHIFT 0x00000002 -#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x00000004 -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x00000008 -#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0x0000000c -#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x00000010 -#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x00000015 -#define TCC_CTRL__MDC_SIZE__SHIFT 0x00000018 -#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x0000001a -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x0000001c - -// TCC_CTRL2 -#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x00000000 - -// TCC_EDC_CNT -#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x00000000 -#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x00000002 -#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x00000004 -#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x00000006 -#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x00000008 -#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0x0000000a -#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0x0000000c -#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0x0000000e -#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x00000010 -#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x00000012 -#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x00000014 -#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x00000016 -#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x00000018 -#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x0000001a -#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x0000001c -#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x0000001e - -// TCC_EDC_CNT2 -#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x00000000 -#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x00000002 -#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x00000004 -#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x00000006 -#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x00000008 - -// TCC_REDUNDANCY -#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x00000000 -#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x00000001 - -// TCC_EXE_DISABLE -#define TCC_EXE_DISABLE__WRITE_DIS__SHIFT 0x00000000 -#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x00000001 - -// TCC_DSM_CNTL -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x00000000 -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000002 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x00000003 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000005 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x00000006 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000008 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x00000009 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000000b -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0x0000000c -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000000e -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0x0000000f -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000011 -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x00000012 -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000014 -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x00000015 -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000017 -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x00000018 -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000001a -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x0000001b -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000001d - -// TCC_DSM_CNTLA -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x00000000 -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000002 -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x00000003 -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000005 -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x00000006 -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000008 -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x00000009 -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000000b -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0000000c -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000000e -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0000000f -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000011 -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x00000012 -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000014 -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x00000015 -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000017 -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x00000018 -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000001a -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x0000001b -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x0000001d - -// TCC_DSM_CNTL2 -#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0x0000000f -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x00000011 -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x00000012 -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x00000014 -#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x00000015 -#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x00000017 -#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x0000001a - -// TCC_DSM_CNTL2A -#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0x0000000f -#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x00000011 -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x00000012 -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x00000014 -#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000015 -#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000017 -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000018 -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x0000001a -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0000001b -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x0000001d - -// TCC_DSM_CNTL2B -#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x00000005 - -// TCC_WBINVL2 -#define TCC_WBINVL2__DONE__SHIFT 0x00000004 - -// TCC_SOFT_RESET -#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x00000000 - -// TCA_CTRL -#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x00000000 -#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x00000004 -#define TCA_CTRL__RB_AS_TCI__SHIFT 0x00000005 -#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x00000006 -#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x00000007 - -// TCA_BURST_MASK -#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x00000000 - -// TCA_BURST_CTRL -#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x00000000 -#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x00000003 -#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x00000004 -#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x00000005 -#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x00000006 -#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x00000007 -#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x00000008 -#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x00000009 -#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0x0000000a -#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0x0000000b -#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0x0000000c -#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0x0000000d -#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0x0000000e - -// TCA_DSM_CNTL -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x00000000 -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000002 -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x00000003 -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x00000005 - -// TCA_DSM_CNTL2 -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x0000001a - -// TCA_EDC_CNT -#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x00000000 -#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x00000002 - -// TCC_PERFCOUNTER0_LO -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCC_PERFCOUNTER1_LO -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCC_PERFCOUNTER2_LO -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCC_PERFCOUNTER3_LO -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCC_PERFCOUNTER0_HI -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCC_PERFCOUNTER1_HI -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCC_PERFCOUNTER2_HI -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCC_PERFCOUNTER3_HI -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCA_PERFCOUNTER0_LO -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCA_PERFCOUNTER1_LO -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCA_PERFCOUNTER2_LO -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCA_PERFCOUNTER3_LO -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// TCA_PERFCOUNTER0_HI -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCA_PERFCOUNTER1_HI -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCA_PERFCOUNTER2_HI -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCA_PERFCOUNTER3_HI -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// TCC_PERFCOUNTER0_SELECT -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCC_PERFCOUNTER1_SELECT -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCC_PERFCOUNTER0_SELECT1 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c - -// TCC_PERFCOUNTER1_SELECT1 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c - -// TCC_PERFCOUNTER2_SELECT -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCC_PERFCOUNTER3_SELECT -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCA_PERFCOUNTER0_SELECT -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCA_PERFCOUNTER1_SELECT -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCA_PERFCOUNTER0_SELECT1 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c - -// TCA_PERFCOUNTER1_SELECT1 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c - -// TCA_PERFCOUNTER2_SELECT -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCA_PERFCOUNTER3_SELECT -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// TCC_CGTT_SCLK_CTRL -#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// TCA_CGTT_SCLK_CTRL -#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// GRBM_CNTL -#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 -#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x0000001f - -// GRBM_SKEW_CNTL -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 -#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000006 - -// GRBM_PWR_CNTL -#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x00000000 -#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x00000002 -#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x00000004 -#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x00000006 -#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0x0000000e -#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0x0000000f - -// GRBM_STATUS -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x00000000 -#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x00000005 -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x00000007 -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x00000008 -#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x00000009 -#define GRBM_STATUS__DB_CLEAN__SHIFT 0x0000000c -#define GRBM_STATUS__CB_CLEAN__SHIFT 0x0000000d -#define GRBM_STATUS__TA_BUSY__SHIFT 0x0000000e -#define GRBM_STATUS__GDS_BUSY__SHIFT 0x0000000f -#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x00000010 -#define GRBM_STATUS__VGT_BUSY__SHIFT 0x00000011 -#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x00000012 -#define GRBM_STATUS__IA_BUSY__SHIFT 0x00000013 -#define GRBM_STATUS__SX_BUSY__SHIFT 0x00000014 -#define GRBM_STATUS__WD_BUSY__SHIFT 0x00000015 -#define GRBM_STATUS__SPI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS__BCI_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS__SC_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS__PA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS__DB_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x0000001c -#define GRBM_STATUS__CP_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS__CB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f - -// GRBM_STATUS2 -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x00000000 -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x00000004 -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x00000005 -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x00000006 -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x00000007 -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x00000008 -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x00000009 -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0x0000000a -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0x0000000b -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0x0000000c -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0x0000000d -#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0x0000000e -#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0x0000000f -#define GRBM_STATUS2__EA_BUSY__SHIFT 0x00000010 -#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x00000011 -#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x00000012 -#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x00000013 -#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x00000014 -#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS2__TC_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x0000001a -#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x0000001c -#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x0000001f - -// GRBM_STATUS_SE0 -#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x00000001 -#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x00000002 -#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x00000015 -#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x0000001b -#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x0000001f - -// GRBM_STATUS_SE1 -#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x00000001 -#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x00000002 -#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x00000015 -#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x0000001b -#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x0000001f - -// GRBM_STATUS_SE2 -#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x00000001 -#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x00000002 -#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x00000015 -#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x0000001b -#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x0000001f - -// GRBM_STATUS_SE3 -#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x00000001 -#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x00000002 -#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x00000015 -#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x00000016 -#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x00000017 -#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x00000018 -#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x00000019 -#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x0000001a -#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x0000001b -#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x0000001d -#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x0000001e -#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x0000001f - -// GRBM_SOFT_RESET -#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 -#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x00000002 -#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x00000010 -#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x00000011 -#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x00000012 -#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x00000013 -#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x00000014 -#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x00000015 -#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x00000016 - -// GRBM_DEBUG_CNTL -#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x00000000 - -// GRBM_DEBUG_DATA -#define GRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// GRBM_CGTT_CLK_CNTL -#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x00000000 -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e - -// GRBM_GFX_CLKEN_CNTL -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 - -// GRBM_WAIT_IDLE_CLOCKS -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x00000000 - -// GRBM_DEBUG -#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000001 -#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x00000005 -#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000006 -#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000007 -#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x00000008 -#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x0000000c -#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0x0000000d -#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x0000001f - -// GRBM_DEBUG_SNAPSHOT -#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x00000000 -#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x00000001 -#define GRBM_DEBUG_SNAPSHOT__RSMU_RDY__SHIFT 0x00000002 -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x00000003 -#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x00000004 -#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x00000005 -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x00000006 -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x00000007 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x00000008 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x00000009 -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0x0000000a -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0x0000000b -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0x0000000c -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0x0000000d -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0x0000000e -#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0x0000000f -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x00000010 -#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x00000011 -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x00000012 -#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x00000013 -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x00000014 -#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x00000015 - -// GRBM_RSMU_READ_ERROR -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x00000002 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x00000014 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x00000015 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x0000001b -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x0000001f - -// GRBM_CHICKEN_BITS -#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x00000000 - -// GRBM_READ_ERROR -#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 -#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x00000014 -#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x00000016 -#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f - -// GRBM_READ_ERROR2 -#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x00000010 -#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x00000011 -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x00000012 -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x00000013 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x00000014 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x00000015 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x00000016 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x00000017 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x00000018 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x00000019 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x0000001a -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x0000001b -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x0000001c -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x0000001d -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x0000001e -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x0000001f - -// GRBM_INT_CNTL -#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x00000000 -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x00000013 - -// GRBM_TRAP_OP -#define GRBM_TRAP_OP__RW__SHIFT 0x00000000 - -// GRBM_TRAP_ADDR -#define GRBM_TRAP_ADDR__DATA__SHIFT 0x00000000 - -// GRBM_TRAP_ADDR_MSK -#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x00000000 - -// GRBM_TRAP_WD -#define GRBM_TRAP_WD__DATA__SHIFT 0x00000000 - -// GRBM_TRAP_WD_MSK -#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x00000000 - -// GRBM_DSM_BYPASS -#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x00000000 -#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x00000002 - -// GRBM_IOV_ERROR -#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x00000002 -#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x00000014 -#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x0000001a -#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x0000001b -#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x0000001f - -// GRBM_WRITE_ERROR -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x00000000 -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x00000001 -#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x00000002 -#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x00000005 -#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0x0000000c -#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0x0000000d -#define GRBM_WRITE_ERROR__TMZ__SHIFT 0x00000011 -#define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT 0x00000012 -#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x00000014 -#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x00000016 -#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x0000001f - -// GRBM_GFX_CNTL -#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x00000000 -#define GRBM_GFX_CNTL__MEID__SHIFT 0x00000002 -#define GRBM_GFX_CNTL__VMID__SHIFT 0x00000004 -#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x00000008 - -// GRBM_RSMU_CFG -#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x00000000 -#define GRBM_RSMU_CFG__QOS__SHIFT 0x0000000c -#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x00000010 -#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x00000011 - -// GRBM_IH_CREDIT -#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x00000000 -#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x00000010 - -// GRBM_PWR_CNTL2 -#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x00000010 -#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x00000014 - -// GRBM_UTCL2_INVAL_RANGE_START -#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x00000000 - -// GRBM_UTCL2_INVAL_RANGE_END -#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x00000000 - -// GRBM_CHIP_REVISION -#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG0 -#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG1 -#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG2 -#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG3 -#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG4 -#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG5 -#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG6 -#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 - -// GRBM_SCRATCH_REG7 -#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 - -// DEBUG_INDEX -#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x00000000 - -// DEBUG_DATA -#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 - -// GRBM_NOWHERE -#define GRBM_NOWHERE__DATA__SHIFT 0x00000000 - -// GRBM_GFX_INDEX -#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x00000000 -#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x00000008 -#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x00000010 -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x0000001d -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x0000001e -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x0000001f - -// GRBM_PERFCOUNTER0_LO -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GRBM_PERFCOUNTER0_HI -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GRBM_PERFCOUNTER1_LO -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GRBM_PERFCOUNTER1_HI -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GRBM_SE0_PERFCOUNTER_LO -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GRBM_SE0_PERFCOUNTER_HI -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GRBM_SE1_PERFCOUNTER_LO -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GRBM_SE1_PERFCOUNTER_HI -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GRBM_SE2_PERFCOUNTER_LO -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GRBM_SE2_PERFCOUNTER_HI -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GRBM_SE3_PERFCOUNTER_LO -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// GRBM_SE3_PERFCOUNTER_HI -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// GRBM_PERFCOUNTER0_SELECT -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c -#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001d -#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001e -#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001f - -// GRBM_PERFCOUNTER1_SELECT -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c -#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001d -#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001e -#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001f - -// GRBM_SE0_PERFCOUNTER_SELECT -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 - -// GRBM_SE1_PERFCOUNTER_SELECT -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 - -// GRBM_SE2_PERFCOUNTER_SELECT -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 - -// GRBM_SE3_PERFCOUNTER_SELECT -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 -#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 - -// GRBM_HYP_CAM_INDEX -#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 - -// GRBM_CAM_INDEX -#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 - -// GRBM_HYP_CAM_DATA -#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 - -// GRBM_CAM_DATA -#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 -#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 - -// GRBM_GFX_CNTL_SR_SELECT -#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x00000000 - -// GRBM_GFX_CNTL_SR_DATA -#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x00000000 -#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x00000002 -#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x00000004 -#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x00000008 - -// GRBM_GFX_INDEX_SR_SELECT -#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x00000000 - -// GRBM_GFX_INDEX_SR_DATA -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x00000000 -#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x00000008 -#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x00000010 -#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x0000001d -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x0000001e -#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x0000001f - -// GRBM_SRCID_CAM_INDEX -#define GRBM_SRCID_CAM_INDEX__INDEX__SHIFT 0x00000000 - -// GRBM_SRCID_CAM_DATA -#define GRBM_SRCID_CAM_DATA__PROG_SRCID__SHIFT 0x00000000 - -// GRBM_PF_ONLY_RANGE0 -#define GRBM_PF_ONLY_RANGE0__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE0__END__SHIFT 0x00000010 - -// GRBM_PF_ONLY_RANGE1 -#define GRBM_PF_ONLY_RANGE1__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE1__END__SHIFT 0x00000010 - -// GRBM_PF_ONLY_RANGE2 -#define GRBM_PF_ONLY_RANGE2__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE2__END__SHIFT 0x00000010 - -// GRBM_PF_ONLY_RANGE3 -#define GRBM_PF_ONLY_RANGE3__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE3__END__SHIFT 0x00000010 - -// GRBM_PF_ONLY_RANGE4 -#define GRBM_PF_ONLY_RANGE4__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE4__END__SHIFT 0x00000010 - -// GRBM_PF_ONLY_RANGE5 -#define GRBM_PF_ONLY_RANGE5__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE5__END__SHIFT 0x00000010 - -// GRBM_PF_ONLY_RANGE6 -#define GRBM_PF_ONLY_RANGE6__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE6__END__SHIFT 0x00000010 - -// GRBM_PF_ONLY_RANGE7 -#define GRBM_PF_ONLY_RANGE7__START__SHIFT 0x00000000 -#define GRBM_PF_ONLY_RANGE7__END__SHIFT 0x00000010 - -// GRBM_IOV_ENABLE -#define GRBM_IOV_ENABLE__PF_ONLY_RANGE_ENABLE__SHIFT 0x00000000 -#define GRBM_IOV_ENABLE__IOV_ERROR_CHECK_ENABLE__SHIFT 0x0000001f - -// CP_CPC_DEBUG_CNTL -#define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x00000000 -#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT 0x00000010 -#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT 0x0000001f - -// CP_CPC_DEBUG_DATA -#define CP_CPC_DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 - -// CP_CPF_DEBUG_CNTL -#define CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x00000000 -#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT 0x00000010 -#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT 0x0000001f - -// CP_CPF_DEBUG_DATA -#define CP_CPF_DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 - -// CP_CPC_STATUS -#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x00000000 -#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x00000001 -#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x00000002 -#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x00000003 -#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x00000004 -#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x00000005 -#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x00000006 -#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x00000007 -#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0x0000000a -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0x0000000b -#define CP_CPC_STATUS__QU_BUSY__SHIFT 0x0000000c -#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0x0000000d -#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0x0000000e -#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x0000001d -#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x0000001e -#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x0000001f - -// CP_CPC_BUSY_STAT -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x00000000 -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x00000001 -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x00000002 -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x00000003 -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x00000004 -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x00000005 -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x00000006 -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x00000007 -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x00000008 -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x00000009 -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0x0000000a -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0x0000000b -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0x0000000c -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0x0000000d -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x00000010 -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x00000011 -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x00000012 -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x00000013 -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x00000014 -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x00000015 -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x00000016 -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x00000017 -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x00000018 -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x00000019 -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x0000001a -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x0000001b -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x0000001c -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x0000001d - -// CP_CPC_STALLED_STAT1 -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x00000003 -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x00000004 -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x00000006 -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x00000008 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x00000009 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0x0000000a -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0x0000000d -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x00000010 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x00000011 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x00000012 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x00000015 -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x00000016 -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x00000017 -#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x00000018 - -// CP_CPF_STATUS -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x00000000 -#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x00000001 -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x00000004 -#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x00000005 -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x00000006 -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x00000007 -#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x00000008 -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x00000009 -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000000a -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000000b -#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0x0000000c -#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0x0000000d -#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0x0000000e -#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0x0000000f -#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x00000010 -#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x00000011 -#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x0000001a -#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x0000001b -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x0000001c -#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x0000001e -#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x0000001f - -// CP_CPF_BUSY_STAT -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000 -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x00000001 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x00000002 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000003 -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x00000004 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x00000005 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x00000006 -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x00000007 -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x00000008 -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x00000009 -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0x0000000b -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0x0000000c -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0x0000000d -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0x0000000e -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0x0000000f -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x00000010 -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x00000011 -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x00000012 -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x00000013 -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x00000014 -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x00000015 -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x00000016 -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x00000017 -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x00000018 -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x00000019 -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x0000001a -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x0000001b -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x0000001c -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x0000001d -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x0000001e -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x0000001f - -// CP_CPF_STALLED_STAT1 -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x00000000 -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x00000001 -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x00000002 -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x00000003 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x00000005 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x00000006 -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x00000007 -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x00000008 -#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x00000009 -#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0x0000000a -#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0x0000000b - -// CP_CPC_GRBM_FREE_COUNT -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000 - -// CP_CPC_PRIV_VIOLATION_ADDR -#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x00000000 - -// CP_MEC_CNTL -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x00000004 -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x00000010 -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x00000011 -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x00000012 -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x00000013 -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x00000014 -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x00000015 -#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x0000001c -#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x0000001d -#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x0000001e -#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x0000001f - -// CP_MEC_ME1_HEADER_DUMP -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x00000000 - -// CP_MEC_ME2_HEADER_DUMP -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x00000000 - -// CP_CPC_SCRATCH_INDEX -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000 - -// CP_CPC_SCRATCH_DATA -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000 - -// CP_CPF_GRBM_FREE_COUNT -#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000 - -// CP_CPC_HALT_HYST_COUNT -#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x00000000 - -// CP_PRT_LOD_STATS_CNTL0 -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x00000000 - -// CP_PRT_LOD_STATS_CNTL1 -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x00000000 - -// CP_PRT_LOD_STATS_CNTL2 -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x00000000 - -// CP_PRT_LOD_STATS_CNTL3 -#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x00000002 -#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0x0000000a -#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x00000012 -#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x00000013 -#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x00000017 -#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x0000001c - -// CP_CE_COMPARE_COUNT -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x00000000 - -// CP_CE_DE_COUNT -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x00000000 - -// CP_DE_CE_COUNT -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x00000000 - -// CP_DE_LAST_INVAL_COUNT -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x00000000 - -// CP_DE_DE_COUNT -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x00000000 - -// CP_STALLED_STAT1 -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x00000000 -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x00000002 -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x00000004 -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0x0000000a -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0x0000000b -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x0000000c -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x0000000d -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0x0000000e -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0x0000000f -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x00000017 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x00000018 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x00000019 -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x0000001a -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x0000001b -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x0000001c -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x0000001d - -// CP_STALLED_STAT2 -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x00000001 -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x00000002 -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x00000004 -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x00000005 -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x00000008 -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x00000009 -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0x0000000a -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0x0000000b -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0x0000000c -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0x0000000d -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0x0000000e -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0x0000000f -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000010 -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000011 -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x00000012 -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x00000013 -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x00000014 -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x00000015 -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x00000016 -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x00000017 -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x00000018 -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x00000019 -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x0000001a -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x0000001b -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x0000001c -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x0000001d -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x0000001e -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x0000001f - -// CP_STALLED_STAT3 -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x00000001 -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x00000002 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x00000003 -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x00000004 -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x00000005 -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000006 -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000007 -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0x0000000a -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0x0000000b -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0x0000000c -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0x0000000d -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0x0000000e -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0x0000000f -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x00000010 -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x00000011 -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x00000012 -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x00000013 -#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x00000014 - -// CP_BUSY_STAT -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000 -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006 -#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007 -#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008 -#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009 -#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f -#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011 -#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012 -#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013 -#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014 -#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015 -#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016 - -// CP_STAT -#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x00000009 -#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0x0000000a -#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0x0000000b -#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0x0000000c -#define CP_STAT__DC_BUSY__SHIFT 0x0000000d -#define CP_STAT__UTCL2IU_BUSY__SHIFT 0x0000000e -#define CP_STAT__PFP_BUSY__SHIFT 0x0000000f -#define CP_STAT__MEQ_BUSY__SHIFT 0x00000010 -#define CP_STAT__ME_BUSY__SHIFT 0x00000011 -#define CP_STAT__QUERY_BUSY__SHIFT 0x00000012 -#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x00000013 -#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x00000014 -#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x00000015 -#define CP_STAT__DMA_BUSY__SHIFT 0x00000016 -#define CP_STAT__RCIU_BUSY__SHIFT 0x00000017 -#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x00000018 -#define CP_STAT__CE_BUSY__SHIFT 0x0000001a -#define CP_STAT__TCIU_BUSY__SHIFT 0x0000001b -#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x0000001c -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000001d -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000001e -#define CP_STAT__CP_BUSY__SHIFT 0x0000001f - -// CP_ME_HEADER_DUMP -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000 - -// CP_PFP_HEADER_DUMP -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000 - -// CP_GRBM_FREE_COUNT -#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010 - -// CP_CE_HEADER_DUMP -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000 - -// CP_PFP_INSTR_PNTR -#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x00000000 - -// CP_ME_INSTR_PNTR -#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x00000000 - -// CP_CE_INSTR_PNTR -#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x00000000 - -// CP_MEC1_INSTR_PNTR -#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x00000000 - -// CP_MEC2_INSTR_PNTR -#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x00000000 - -// CP_CSF_STAT -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008 - -// CP_ME_CNTL -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x00000004 -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x00000006 -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x00000008 -#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x00000010 -#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x00000011 -#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x00000012 -#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x00000013 -#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x00000014 -#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x00000015 -#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018 -#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019 -#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a -#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b -#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c -#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d - -// CP_CNTX_STAT -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x00000000 -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x00000008 -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014 -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c - -// CP_ME_PREEMPTION -#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x00000000 - -// CP_RB0_RPTR -#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000 - -// CP_RB_RPTR -#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 - -// CP_RB1_RPTR -#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000 - -// CP_RB2_RPTR -#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000 - -// CP_RB_WPTR_DELAY -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c - -// CP_RB_WPTR_POLL_CNTL -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000 -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 - -// CP_ROQ_THRESHOLDS -#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x00000000 -#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x00000008 - -// CP_MEQ_STQ_THRESHOLD -#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x00000000 - -// CP_ROQ1_THRESHOLDS -#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000 -#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008 -#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010 -#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018 - -// CP_ROQ2_THRESHOLDS -#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000 -#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008 -#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010 -#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018 - -// CP_STQ_THRESHOLDS -#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x00000000 -#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x00000008 -#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x00000010 - -// CP_QUEUE_THRESHOLDS -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000 -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008 - -// CP_MEQ_THRESHOLDS -#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000 -#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008 - -// CP_ROQ_AVAIL -#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000 -#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010 - -// CP_STQ_AVAIL -#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x00000000 - -// CP_ROQ2_AVAIL -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000 - -// CP_MEQ_AVAIL -#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 - -// CP_CMD_INDEX -#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 -#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0x0000000c -#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 - -// CP_CMD_DATA -#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 - -// CP_ROQ_RB_STAT -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x00000000 -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x00000010 - -// CP_ROQ_IB1_STAT -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x00000000 -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x00000010 - -// CP_ROQ_IB2_STAT -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x00000000 -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x00000010 - -// CP_STQ_STAT -#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x00000000 - -// CP_STQ_WR_STAT -#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x00000000 - -// CP_MEQ_STAT -#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 -#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 - -// CP_CEQ1_AVAIL -#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000 -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010 - -// CP_CEQ2_AVAIL -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000 - -// CP_CE_ROQ_RB_STAT -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000 -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010 - -// CP_CE_ROQ_IB1_STAT -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000 -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010 - -// CP_CE_ROQ_IB2_STAT -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000 -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010 - -// CP_INT_STAT_DEBUG -#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0x0000000b -#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e -#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x00000010 -#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011 -#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x00000012 -#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013 -#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014 -#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x00000015 -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016 -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017 -#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018 -#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a -#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b -#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d -#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e -#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f - -// CP_DEBUG_CNTL -#define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x00000000 -#define CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT 0x00000010 -#define CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT 0x0000001f - -// CP_DEBUG_DATA -#define CP_DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 - -// CP_PRIV_VIOLATION_ADDR -#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x00000000 - -// CP_DFY_CNTL -#define CP_DFY_CNTL__POLICY__SHIFT 0x00000000 -#define CP_DFY_CNTL__MTYPE__SHIFT 0x00000002 -#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x0000001a -#define CP_DFY_CNTL__WRITE_DIS__SHIFT 0x0000001b -#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x0000001c -#define CP_DFY_CNTL__MODE__SHIFT 0x0000001d -#define CP_DFY_CNTL__ENABLE__SHIFT 0x0000001f - -// CP_DFY_STAT -#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x00000000 -#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x00000010 -#define CP_DFY_STAT__BUSY__SHIFT 0x0000001f - -// CP_DFY_ADDR_HI -#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_DFY_ADDR_LO -#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x00000005 - -// CP_DFY_DATA_0 -#define CP_DFY_DATA_0__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_1 -#define CP_DFY_DATA_1__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_2 -#define CP_DFY_DATA_2__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_3 -#define CP_DFY_DATA_3__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_4 -#define CP_DFY_DATA_4__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_5 -#define CP_DFY_DATA_5__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_6 -#define CP_DFY_DATA_6__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_7 -#define CP_DFY_DATA_7__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_8 -#define CP_DFY_DATA_8__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_9 -#define CP_DFY_DATA_9__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_10 -#define CP_DFY_DATA_10__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_11 -#define CP_DFY_DATA_11__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_12 -#define CP_DFY_DATA_12__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_13 -#define CP_DFY_DATA_13__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_14 -#define CP_DFY_DATA_14__DATA__SHIFT 0x00000000 - -// CP_DFY_DATA_15 -#define CP_DFY_DATA_15__DATA__SHIFT 0x00000000 - -// CP_DFY_CMD -#define CP_DFY_CMD__OFFSET__SHIFT 0x00000000 -#define CP_DFY_CMD__SIZE__SHIFT 0x00000010 - -// CP_EOPQ_WAIT_TIME -#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x00000000 -#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0x0000000a - -// CP_CPC_MGCG_SYNC_CNTL -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x00000000 -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x00000008 - -// CPC_INT_INFO -#define CPC_INT_INFO__ADDR_HI__SHIFT 0x00000000 -#define CPC_INT_INFO__TYPE__SHIFT 0x00000010 -#define CPC_INT_INFO__VMID__SHIFT 0x00000014 -#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x0000001c - -// CPC_INT_ADDR -#define CPC_INT_ADDR__ADDR__SHIFT 0x00000000 - -// CPC_INT_PASID -#define CPC_INT_PASID__PASID__SHIFT 0x00000000 - -// CP_GFX_ERROR -#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x00000000 -#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x00000004 -#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x00000005 -#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x00000006 -#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x00000007 -#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x00000008 -#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x00000009 -#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0x0000000a -#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0x0000000b -#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0x0000000c -#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0x0000000d -#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0x0000000e -#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0x0000000f -#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x00000010 -#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x00000011 -#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x00000012 -#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x00000013 -#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x00000014 -#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x00000015 -#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x00000016 -#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x00000017 -#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x00000018 -#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x00000019 -#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x0000001a -#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x0000001b -#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x0000001c -#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x0000001d -#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x0000001e -#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x0000001f - -// CPG_UTCL1_CNTL -#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x00000017 -#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x00000018 -#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x00000019 -#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x0000001a -#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x0000001c -#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0000001e - -// CPC_UTCL1_CNTL -#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x00000018 -#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x00000019 -#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x0000001a -#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x0000001c -#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0000001e - -// CPF_UTCL1_CNTL -#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x00000000 -#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x00000017 -#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x00000018 -#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x00000019 -#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x0000001a -#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x0000001b -#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x0000001c -#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x0000001d -#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0000001e -#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x0000001f - -// CP_AQL_SMM_STATUS -#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x00000000 - -// CP_RB0_BASE -#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000 - -// CP_RB0_BASE_HI -#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 - -// CP_RB_BASE -#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000 - -// CP_RB1_BASE -#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000 - -// CP_RB1_BASE_HI -#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 - -// CP_RB2_BASE -#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000 - -// CP_RB0_CNTL -#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x00000011 -#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018 -#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f - -// CP_RB_CNTL -#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x00000018 -#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f - -// CP_RB1_CNTL -#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x00000018 -#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f - -// CP_RB2_CNTL -#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 -#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 -#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x00000018 -#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b -#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f - -// CP_RB_RPTR_WR -#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 - -// CP_RB0_RPTR_ADDR -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 - -// CP_RB_RPTR_ADDR -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 - -// CP_RB1_RPTR_ADDR -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 - -// CP_RB2_RPTR_ADDR -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 - -// CP_RB0_RPTR_ADDR_HI -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 - -// CP_RB_RPTR_ADDR_HI -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 - -// CP_RB1_RPTR_ADDR_HI -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 - -// CP_RB2_RPTR_ADDR_HI -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 - -// CP_RB0_ACTIVE -#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x00000000 - -// CP_RB_ACTIVE -#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x00000000 - -// CP_RB0_BUFSZ_MASK -#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x00000000 - -// CP_RB_BUFSZ_MASK -#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x00000000 - -// CP_RB_WPTR_POLL_ADDR_LO -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000002 - -// CP_RB_WPTR_POLL_ADDR_HI -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000000 - -// GC_PRIV_MODE -#define GC_PRIV_MODE__MC_PRIV_MODE__SHIFT 0x00000000 - -// CP_INT_CNTL -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0x0000000b -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x00000012 -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x00000015 -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_INT_CNTL_RING0 -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0x0000000b -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x00000012 -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x00000015 -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_INT_CNTL_RING1 -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0x0000000b -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x00000012 -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x00000015 -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_INT_CNTL_RING2 -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0x0000000b -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x00000012 -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x00000015 -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_INT_STATUS -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0x0000000b -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x00000010 -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x00000012 -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x00000015 -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x0000001d -#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x0000001e -#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x0000001f - -// CP_INT_STATUS_RING0 -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0x0000000b -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x00000010 -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x00000012 -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x00000013 -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x00000015 -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x0000001d -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x0000001e -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x0000001f - -// CP_INT_STATUS_RING1 -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0x0000000b -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x00000010 -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x00000012 -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x00000015 -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x0000001d -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x0000001e -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x0000001f - -// CP_INT_STATUS_RING2 -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0x0000000b -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e -#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x00000010 -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x00000012 -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x00000015 -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017 -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x0000001d -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x0000001e -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x0000001f - -// CP_DEVICE_ID -#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x00000000 - -// CP_RING_PRIORITY_CNTS -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 - -// CP_ME0_PIPE_PRIORITY_CNTS -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 - -// CP_RING0_PRIORITY -#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME0_PIPE0_PRIORITY -#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_RING1_PRIORITY -#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME0_PIPE1_PRIORITY -#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_RING2_PRIORITY -#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME0_PIPE2_PRIORITY -#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_FATAL_ERROR -#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x00000000 -#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x00000001 -#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x00000002 -#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x00000003 -#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x00000004 - -// CP_RB_VMID -#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000 -#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008 -#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010 - -// CP_ME0_PIPE0_VMID -#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x00000000 - -// CP_ME0_PIPE1_VMID -#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x00000000 - -// CP_RB0_WPTR -#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000 - -// CP_RB_WPTR -#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 - -// CP_RB0_WPTR_HI -#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x00000000 - -// CP_RB_WPTR_HI -#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x00000000 - -// CP_RB1_WPTR -#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000 - -// CP_RB1_WPTR_HI -#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x00000000 - -// CP_RB2_WPTR -#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000 - -// CP_RB_DOORBELL_CONTROL -#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x00000001 -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_RANGE_LOWER -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x00000002 - -// CP_RB_DOORBELL_RANGE_UPPER -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x00000002 - -// CP_MEC_DOORBELL_RANGE_LOWER -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x00000002 - -// CP_MEC_DOORBELL_RANGE_UPPER -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x00000002 - -// CPG_UTCL1_ERROR -#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x00000000 - -// CPC_UTCL1_ERROR -#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x00000000 - -// CP_IB1_PRIV_BASE_LO -#define CP_IB1_PRIV_BASE_LO__IB1_PRIV_BASE_LO__SHIFT 0x00000002 - -// CP_IB1_PRIV_BASE_HI -#define CP_IB1_PRIV_BASE_HI__IB1_PRIV_BASE_HI__SHIFT 0x00000000 - -// CP_IB1_PRIV_BUFSZ -#define CP_IB1_PRIV_BUFSZ__IB1_PRIV_BUFSZ__SHIFT 0x00000000 - -// CP_ME_F32_INTERRUPT -#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x00000000 -#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x00000001 -#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x00000002 -#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x00000003 - -// CP_PFP_F32_INTERRUPT -#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x00000000 -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x00000001 -#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x00000002 -#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x00000003 - -// CP_CE_F32_INTERRUPT -#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x00000000 -#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x00000001 -#define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT 0x00000002 -#define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT 0x00000003 - -// CP_MEC1_F32_INTERRUPT -#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x00000000 -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x00000001 -#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x00000002 -#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x00000003 -#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x00000004 -#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x00000005 -#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x00000006 -#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x00000007 -#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x00000008 -#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x00000009 -#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0x0000000a -#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0x0000000b -#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0x0000000c -#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0x0000000d -#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0x0000000e -#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0x0000000f - -// CP_MEC2_F32_INTERRUPT -#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x00000000 -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x00000001 -#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x00000002 -#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x00000003 -#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x00000004 -#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x00000005 -#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x00000006 -#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x00000007 -#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x00000008 -#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x00000009 -#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0x0000000a -#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0x0000000b -#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0x0000000c -#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0x0000000d -#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0x0000000e -#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0x0000000f - -// CP_MEC1_F32_INT_DIS -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x00000000 -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x00000001 -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x00000002 -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x00000003 -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x00000004 -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x00000005 -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x00000006 -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x00000007 -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x00000008 -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x00000009 -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0x0000000a -#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0x0000000b -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0x0000000c -#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0x0000000d -#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0x0000000e -#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0x0000000f - -// CP_MEC2_F32_INT_DIS -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x00000000 -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x00000001 -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x00000002 -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x00000003 -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x00000004 -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x00000005 -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x00000006 -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x00000007 -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x00000008 -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x00000009 -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0x0000000a -#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0x0000000b -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0x0000000c -#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0x0000000d -#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0x0000000e -#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0x0000000f - -// CP_VIRT_STATUS -#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x00000000 - -// CP_PWR_CNTL -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x00000000 -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x00000001 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x00000008 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x00000009 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0x0000000a -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0x0000000b -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x00000010 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x00000011 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x00000012 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x00000013 - -// CP_MEM_SLP_CNTL -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000 -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001 -#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x00000007 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010 -#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 - -// CP_ECC_FIRSTOCCURRENCE -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000 -#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x00000004 -#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x00000008 -#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0x0000000a -#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0x0000000c -#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010 - -// CP_ECC_FIRSTOCCURRENCE_RING0 -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x00000000 - -// CP_ECC_FIRSTOCCURRENCE_RING1 -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x00000000 - -// CP_ECC_FIRSTOCCURRENCE_RING2 -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x00000000 - -// CP_DEBUG -#define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT 0x00000010 -#define CP_DEBUG__BUSY_EXTENDER__SHIFT 0x00000013 -#define CP_DEBUG__INTERRUPT_DISABLE__SHIFT 0x00000016 -#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 -#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x00000018 -#define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x00000019 -#define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x0000001a -#define CP_DEBUG__CPG_TC_MTYPE_OVERRIDE__SHIFT 0x0000001b -#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x0000001c -#define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x0000001d -#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT 0x0000001e -#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT 0x0000001f - -// CP_CPF_DEBUG -#define CP_CPF_DEBUG__BUSY_EXTENDER__SHIFT 0x00000013 -#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x00000018 -#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x00000019 -#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT 0x0000001d -#define CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE__SHIFT 0x0000001e -#define CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT 0x0000001f - -// CP_CPC_DEBUG -#define CP_CPC_DEBUG__BUSY_EXTENDER__SHIFT 0x00000013 -#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT 0x00000015 -#define CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT 0x00000016 -#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x00000018 -#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x00000019 -#define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x0000001a -#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x0000001c -#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x0000001d -#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT 0x0000001f - -// CP_PQ_WPTR_POLL_CNTL -#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x00000000 -#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x0000001d -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x0000001e -#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x0000001f - -// CP_PQ_WPTR_POLL_CNTL1 -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x00000000 - -// CPC_INT_CNTL -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME1_PIPE0_INT_CNTL -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME1_PIPE1_INT_CNTL -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME1_PIPE2_INT_CNTL -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME1_PIPE3_INT_CNTL -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME2_PIPE0_INT_CNTL -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME2_PIPE1_INT_CNTL -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME2_PIPE2_INT_CNTL -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CP_ME2_PIPE3_INT_CNTL -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0x0000000c -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0x0000000d -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0x0000000f -#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x00000010 -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f - -// CPC_INT_STATUS -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME1_PIPE0_INT_STATUS -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME1_PIPE1_INT_STATUS -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME1_PIPE2_INT_STATUS -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME1_PIPE3_INT_STATUS -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME2_PIPE0_INT_STATUS -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME2_PIPE1_INT_STATUS -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME2_PIPE2_INT_STATUS -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME2_PIPE3_INT_STATUS -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0x0000000c -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0x0000000d -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0x0000000e -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x00000010 -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x00000011 -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x00000017 -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x00000018 -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x0000001a -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x0000001b -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x0000001d -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x0000001e -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x0000001f - -// CP_ME1_INT_STAT_DEBUG -#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0x0000000c -#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0x0000000d -#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e -#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x00000010 -#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011 -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017 -#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018 -#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a -#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b -#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d -#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e -#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f - -// CP_ME2_INT_STAT_DEBUG -#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0x0000000c -#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0x0000000d -#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e -#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0x0000000f -#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x00000010 -#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011 -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017 -#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018 -#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a -#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b -#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d -#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e -#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f - -// CP_ME1_PIPE_PRIORITY_CNTS -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 - -// CP_ME1_PIPE0_PRIORITY -#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME1_PIPE1_PRIORITY -#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME1_PIPE2_PRIORITY -#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME1_PIPE3_PRIORITY -#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME2_PIPE_PRIORITY_CNTS -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 - -// CP_ME2_PIPE0_PRIORITY -#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME2_PIPE1_PRIORITY -#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME2_PIPE2_PRIORITY -#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_ME2_PIPE3_PRIORITY -#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x00000000 - -// CP_CE_PRGRM_CNTR_START -#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x00000000 - -// CP_PFP_PRGRM_CNTR_START -#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x00000000 - -// CP_ME_PRGRM_CNTR_START -#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x00000000 - -// CP_MEC1_PRGRM_CNTR_START -#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x00000000 - -// CP_MEC2_PRGRM_CNTR_START -#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x00000000 - -// CP_CE_INTR_ROUTINE_START -#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x00000000 - -// CP_PFP_INTR_ROUTINE_START -#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x00000000 - -// CP_ME_INTR_ROUTINE_START -#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x00000000 - -// CP_MEC1_INTR_ROUTINE_START -#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x00000000 - -// CP_MEC2_INTR_ROUTINE_START -#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x00000000 - -// CP_CONTEXT_CNTL -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x00000000 -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x00000004 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x00000010 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x00000014 - -// CP_MAX_CONTEXT -#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x00000000 - -// CP_IQ_WAIT_TIME1 -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x00000000 -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x00000008 -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x00000010 -#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x00000018 - -// CP_IQ_WAIT_TIME2 -#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x00000000 -#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x00000008 -#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x00000010 -#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x00000018 - -// CP_VMID_RESET -#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x00000000 - -// CP_VMID_PREEMPT -#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x00000000 -#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x00000010 - -// CP_VMID_STATUS -#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x00000000 -#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x00000010 - -// CPC_INT_CNTX_ID -#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x00000000 - -// CP_PQ_STATUS -#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x00000000 -#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x00000001 - -// CP_CPC_IC_BASE_LO -#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0x0000000c - -// CP_CPC_IC_BASE_HI -#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x00000000 - -// CP_CPC_IC_BASE_CNTL -#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x00000000 -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x00000018 - -// CP_CPC_IC_OP_CNTL -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x00000000 -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x00000004 -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x00000005 - -// CP_RB_DOORBELL_CONTROL_SCH_0 -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CONTROL_SCH_1 -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CONTROL_SCH_2 -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CONTROL_SCH_3 -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CONTROL_SCH_4 -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CONTROL_SCH_5 -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CONTROL_SCH_6 -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CONTROL_SCH_7 -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x0000001e -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_RB_DOORBELL_CLEAR -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x00000000 -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x00000008 -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x00000009 -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0x0000000a -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0x0000000b -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0x0000000c -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0x0000000d - -// CP_GFX_MQD_CONTROL -#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x00000000 -#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x00000008 -#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x00000017 -#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x00000018 - -// CP_GFX_MQD_BASE_ADDR -#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x00000002 - -// CP_GFX_MQD_BASE_ADDR_HI -#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x00000000 - -// CP_RB_STATUS -#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x00000000 -#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x00000001 - -// CPG_UTCL1_STATUS -#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 -#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x00000008 -#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x00000010 -#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x00000018 - -// CPC_UTCL1_STATUS -#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 -#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x00000008 -#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x00000010 -#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x00000018 - -// CPF_UTCL1_STATUS -#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 -#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x00000008 -#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x00000010 -#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x00000018 - -// CP_SD_CNTL -#define CP_SD_CNTL__CPF_EN__SHIFT 0x00000000 -#define CP_SD_CNTL__CPG_EN__SHIFT 0x00000001 -#define CP_SD_CNTL__CPC_EN__SHIFT 0x00000002 -#define CP_SD_CNTL__RLC_EN__SHIFT 0x00000003 -#define CP_SD_CNTL__SPI_EN__SHIFT 0x00000004 -#define CP_SD_CNTL__WD_EN__SHIFT 0x00000005 -#define CP_SD_CNTL__IA_EN__SHIFT 0x00000006 -#define CP_SD_CNTL__PA_EN__SHIFT 0x00000007 -#define CP_SD_CNTL__RMI_EN__SHIFT 0x00000008 -#define CP_SD_CNTL__EA_EN__SHIFT 0x00000009 - -// CP_TMZ_CNTL -#define CP_TMZ_CNTL__PTE_DISABLE__SHIFT 0x00000000 - -// CP_SOFT_RESET_CNTL -#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x00000000 -#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x00000001 -#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x00000002 -#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x00000003 -#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x00000004 -#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x00000005 -#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x00000006 - -// CP_CPC_GFX_CNTL -#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x00000000 -#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x00000003 -#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x00000005 -#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x00000007 - -// CP_SECURE_TMZ -#define CP_SECURE_TMZ__TMZ__SHIFT 0x00000000 - -// CP_GFX_SECURE_REQ0 -#define CP_GFX_SECURE_REQ0__REQ_TYPE__SHIFT 0x00000000 -#define CP_GFX_SECURE_REQ0__RSP_TYPE__SHIFT 0x00000008 -#define CP_GFX_SECURE_REQ0__RSP_EN__SHIFT 0x0000001e -#define CP_GFX_SECURE_REQ0__REQ_EN__SHIFT 0x0000001f - -// CP_HQD_SECURE_REQ0 -#define CP_HQD_SECURE_REQ0__REQ_TYPE__SHIFT 0x00000000 -#define CP_HQD_SECURE_REQ0__RSP_TYPE__SHIFT 0x00000008 -#define CP_HQD_SECURE_REQ0__RSP_EN__SHIFT 0x0000001e -#define CP_HQD_SECURE_REQ0__REQ_EN__SHIFT 0x0000001f - -// CP_HQD_GFX_CONTROL -#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x00000000 -#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x00000004 -#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0x0000000f - -// CP_HQD_GFX_STATUS -#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x00000000 - -// CP_HPD_ROQ_OFFSETS -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x00000000 -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x00000008 -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x00000010 - -// CP_HPD_STATUS0 -#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x00000000 -#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x00000005 -#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x00000008 -#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x00000010 -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x00000011 -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x00000012 -#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x00000014 -#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x0000001f - -// CP_HPD_UTCL1_CNTL -#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x00000000 - -// CP_HPD_UTCL1_ERROR -#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x00000000 -#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x00000010 -#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x00000014 - -// CP_HPD_UTCL1_ERROR_ADDR -#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0x0000000c - -// CP_MQD_BASE_ADDR -#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x00000002 - -// CP_MQD_BASE_ADDR_HI -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x00000000 - -// CP_HQD_ACTIVE -#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x00000000 -#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x00000001 - -// CP_HQD_VMID -#define CP_HQD_VMID__VMID__SHIFT 0x00000000 -#define CP_HQD_VMID__IB_VMID__SHIFT 0x00000008 -#define CP_HQD_VMID__VQID__SHIFT 0x00000010 - -// CP_HQD_PERSISTENT_STATE -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x00000000 -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x00000008 -#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x00000015 -#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x00000016 -#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x00000017 -#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x00000018 -#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x00000019 -#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x0000001a -#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x0000001b -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x0000001c -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x0000001d -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x0000001e -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x0000001f - -// CP_HQD_PIPE_PRIORITY -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x00000000 - -// CP_HQD_QUEUE_PRIORITY -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x00000000 - -// CP_HQD_QUANTUM -#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x00000000 -#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x00000004 -#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x00000008 -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x0000001f - -// CP_HQD_PQ_BASE -#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x00000000 - -// CP_HQD_PQ_BASE_HI -#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_HQD_PQ_RPTR -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x00000000 - -// CP_HQD_PQ_RPTR_REPORT_ADDR -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x00000002 - -// CP_HQD_PQ_RPTR_REPORT_ADDR_HI -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x00000000 - -// CP_HQD_PQ_WPTR_POLL_ADDR -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x00000003 - -// CP_HQD_PQ_WPTR_POLL_ADDR_HI -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x00000000 - -// CP_HQD_PQ_DOORBELL_CONTROL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x00000000 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x00000001 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x00000002 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x0000001c -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x0000001d -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x0000001e -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x0000001f - -// CP_HQD_PQ_CONTROL -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x00000000 -#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x00000006 -#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x00000007 -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x00000008 -#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0x0000000e -#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0x0000000f -#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x00000010 -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x00000011 -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x00000014 -#define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x00000016 -#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x00000017 -#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x00000018 -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x00000019 -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x0000001b -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x0000001c -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x0000001d -#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x0000001e -#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x0000001f - -// CP_HQD_IB_BASE_ADDR -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x00000002 - -// CP_HQD_IB_BASE_ADDR_HI -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x00000000 - -// CP_HQD_IB_RPTR -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x00000000 - -// CP_HQD_IB_CONTROL -#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x00000000 -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x00000014 -#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x00000017 -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x00000018 -#define CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT 0x0000001e -#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x0000001f - -// CP_HQD_IQ_TIMER -#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x00000000 -#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x00000008 -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0x0000000b -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0x0000000c -#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0x0000000e -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x00000010 -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x00000016 -#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x00000017 -#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x00000018 -#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x00000019 -#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x0000001c -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x0000001d -#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x0000001e -#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x0000001f - -// CP_HQD_IQ_RPTR -#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x00000000 - -// CP_HQD_DEQUEUE_REQUEST -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x00000000 -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x00000004 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x00000008 -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x00000009 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0x0000000a - -// CP_HQD_DMA_OFFLOAD -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x00000000 - -// CP_HQD_OFFLOAD -#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x00000000 -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x00000001 -#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x00000002 -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x00000003 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x00000004 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x00000005 - -// CP_HQD_SEMA_CMD -#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x00000000 -#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x00000001 - -// CP_HQD_MSG_TYPE -#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x00000000 -#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x00000004 - -// CP_HQD_ATOMIC0_PREOP_LO -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x00000000 - -// CP_HQD_ATOMIC0_PREOP_HI -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x00000000 - -// CP_HQD_ATOMIC1_PREOP_LO -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x00000000 - -// CP_HQD_ATOMIC1_PREOP_HI -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x00000000 - -// CP_HQD_HQ_SCHEDULER0 -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x00000000 - -// CP_HQD_HQ_STATUS0 -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x00000000 -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x00000002 -#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x00000004 -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x00000007 -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x00000008 -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x00000009 -#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0x0000000a -#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x0000001e -#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x0000001f - -// CP_HQD_HQ_SCHEDULER1 -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x00000000 - -// CP_HQD_HQ_CONTROL0 -#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x00000000 - -// CP_MQD_CONTROL -#define CP_MQD_CONTROL__VMID__SHIFT 0x00000000 -#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x00000008 -#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0x0000000c -#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0x0000000d -#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x00000017 -#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x00000018 - -// CP_HQD_HQ_STATUS1 -#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x00000000 - -// CP_HQD_HQ_CONTROL1 -#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x00000000 - -// CP_HQD_EOP_BASE_ADDR -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x00000000 - -// CP_HQD_EOP_BASE_ADDR_HI -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x00000000 - -// CP_HQD_EOP_CONTROL -#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x00000000 -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x00000008 -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0x0000000c -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0x0000000d -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0x0000000e -#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x00000015 -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x00000016 -#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x00000017 -#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x00000018 -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x0000001d -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x0000001f - -// CP_HQD_EOP_RPTR -#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x00000000 -#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x0000001c -#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x0000001d -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x0000001e -#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x0000001f - -// CP_HQD_EOP_WPTR -#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x00000000 -#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0x0000000f -#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x00000010 - -// CP_HQD_EOP_EVENTS -#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x00000000 -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x00000010 - -// CP_HQD_CTX_SAVE_BASE_ADDR_LO -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0x0000000c - -// CP_HQD_CTX_SAVE_BASE_ADDR_HI -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_HQD_CTX_SAVE_CONTROL -#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x00000003 -#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x00000017 - -// CP_HQD_CNTL_STACK_OFFSET -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x00000002 - -// CP_HQD_CNTL_STACK_SIZE -#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0x0000000c - -// CP_HQD_WG_STATE_OFFSET -#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x00000002 - -// CP_HQD_CTX_SAVE_SIZE -#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0x0000000c - -// CP_HQD_GDS_RESOURCE_STATE -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x00000000 -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x00000001 -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x00000004 -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0x0000000c - -// CP_HQD_ERROR -#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x00000000 -#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x00000004 -#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x00000005 -#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x00000008 -#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x00000009 -#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0x0000000a -#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0x0000000b -#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0x0000000c -#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0x0000000d -#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0x0000000e -#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x0000000f -#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x00000010 -#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x00000011 -#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x00000012 -#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x00000013 - -// CP_HQD_EOP_WPTR_MEM -#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x00000000 - -// CP_HQD_AQL_CONTROL -#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x00000000 -#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0x0000000f -#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x00000010 -#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x0000001f - -// CP_HQD_PQ_WPTR_LO -#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x00000000 - -// CP_HQD_PQ_WPTR_HI -#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x00000000 - -// COHER_DEST_BASE_0 -#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000 - -// COHER_DEST_BASE_1 -#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000 - -// COHER_DEST_BASE_2 -#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000 - -// COHER_DEST_BASE_3 -#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000 - -// COHER_DEST_BASE_HI_0 -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x00000000 - -// COHER_DEST_BASE_HI_1 -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x00000000 - -// COHER_DEST_BASE_HI_2 -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x00000000 - -// COHER_DEST_BASE_HI_3 -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x00000000 - -// CP_PERFMON_CNTX_CNTL -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f - -// CP_RINGID -#define CP_RINGID__RINGID__SHIFT 0x00000000 - -// CP_PIPEID -#define CP_PIPEID__PIPE_ID__SHIFT 0x00000000 - -// CP_VMID -#define CP_VMID__VMID__SHIFT 0x00000000 - -// CP_EOP_DONE_EVENT_CNTL -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x00000000 -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0x0000000c -#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x00000019 -#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x0000001c - -// CP_EOP_DONE_DATA_CNTL -#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x00000010 -#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x00000018 -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x0000001d - -// CP_EOP_DONE_CNTX_ID -#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x00000000 - -// CP_EOP_DONE_ADDR_LO -#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x00000002 - -// CP_EOP_DONE_ADDR_HI -#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_EOP_DONE_DATA_LO -#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x00000000 - -// CP_EOP_DONE_DATA_HI -#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x00000000 - -// CP_EOP_LAST_FENCE_LO -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000 - -// CP_EOP_LAST_FENCE_HI -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000 - -// CP_STREAM_OUT_ADDR_LO -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x00000002 - -// CP_STREAM_OUT_ADDR_HI -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT0_LO -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT0_HI -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT0_LO -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT0_HI -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT1_LO -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT1_HI -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT1_LO -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT1_HI -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT2_LO -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT2_HI -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT2_LO -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT2_HI -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT3_LO -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_WRITTEN_COUNT3_HI -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT3_LO -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000 - -// CP_NUM_PRIM_NEEDED_COUNT3_HI -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000 - -// CP_PIPE_STATS_ADDR_LO -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002 - -// CP_PIPE_STATS_ADDR_HI -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000 - -// CP_VGT_IAVERT_COUNT_LO -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_IAVERT_COUNT_HI -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x00000000 - -// CP_VGT_IAPRIM_COUNT_LO -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_IAPRIM_COUNT_HI -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x00000000 - -// CP_VGT_GSPRIM_COUNT_LO -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_GSPRIM_COUNT_HI -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x00000000 - -// CP_VGT_VSINVOC_COUNT_LO -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_VSINVOC_COUNT_HI -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x00000000 - -// CP_VGT_GSINVOC_COUNT_LO -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_GSINVOC_COUNT_HI -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x00000000 - -// CP_VGT_HSINVOC_COUNT_LO -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_HSINVOC_COUNT_HI -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x00000000 - -// CP_VGT_DSINVOC_COUNT_LO -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_DSINVOC_COUNT_HI -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x00000000 - -// CP_PA_CINVOC_COUNT_LO -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000 - -// CP_PA_CINVOC_COUNT_HI -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000 - -// CP_PA_CPRIM_COUNT_LO -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000 - -// CP_PA_CPRIM_COUNT_HI -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000 - -// CP_SC_PSINVOC_COUNT0_LO -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x00000000 - -// CP_SC_PSINVOC_COUNT0_HI -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000 - -// CP_SC_PSINVOC_COUNT1_LO -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x00000000 - -// CP_SC_PSINVOC_COUNT1_HI -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x00000000 - -// CP_VGT_CSINVOC_COUNT_LO -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x00000000 - -// CP_VGT_CSINVOC_COUNT_HI -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x00000000 - -// CP_PIPE_STATS_CONTROL -#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x00000019 - -// CP_STREAM_OUT_CONTROL -#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x00000019 - -// CP_STRMOUT_CNTL -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x00000000 - -// SCRATCH_REG0 -#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 -#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 - -// SCRATCH_REG1 -#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 -#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 - -// SCRATCH_REG2 -#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 -#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 - -// SCRATCH_REG3 -#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 -#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 - -// SCRATCH_REG4 -#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 -#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 - -// SCRATCH_REG5 -#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 -#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 - -// SCRATCH_REG6 -#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 -#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 - -// SCRATCH_REG7 -#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 -#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 - -// CP_APPEND_DATA_HI -#define CP_APPEND_DATA_HI__DATA__SHIFT 0x00000000 - -// CP_APPEND_LAST_CS_FENCE_HI -#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x00000000 - -// CP_APPEND_LAST_PS_FENCE_HI -#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x00000000 - -// SCRATCH_UMSK -#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x00000000 -#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x00000010 - -// SCRATCH_ADDR -#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x00000000 - -// CP_PFP_ATOMIC_PREOP_LO -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000 - -// CP_PFP_ATOMIC_PREOP_HI -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000 - -// CP_PFP_GDS_ATOMIC0_PREOP_LO -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000 - -// CP_PFP_GDS_ATOMIC0_PREOP_HI -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000 - -// CP_PFP_GDS_ATOMIC1_PREOP_LO -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000 - -// CP_PFP_GDS_ATOMIC1_PREOP_HI -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000 - -// CP_APPEND_ADDR_LO -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002 - -// CP_APPEND_ADDR_HI -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000 -#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010 -#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x00000019 -#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d - -// CP_APPEND_DATA_LO -#define CP_APPEND_DATA_LO__DATA__SHIFT 0x00000000 - -// CP_APPEND_LAST_CS_FENCE_LO -#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x00000000 - -// CP_APPEND_LAST_PS_FENCE_LO -#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x00000000 - -// CP_ATOMIC_PREOP_LO -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000 - -// CP_ME_ATOMIC_PREOP_LO -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000 - -// CP_ATOMIC_PREOP_HI -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000 - -// CP_ME_ATOMIC_PREOP_HI -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000 - -// CP_GDS_ATOMIC0_PREOP_LO -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000 - -// CP_ME_GDS_ATOMIC0_PREOP_LO -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000 - -// CP_GDS_ATOMIC0_PREOP_HI -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000 - -// CP_ME_GDS_ATOMIC0_PREOP_HI -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000 - -// CP_GDS_ATOMIC1_PREOP_LO -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000 - -// CP_ME_GDS_ATOMIC1_PREOP_LO -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000 - -// CP_GDS_ATOMIC1_PREOP_HI -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000 - -// CP_ME_GDS_ATOMIC1_PREOP_HI -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000 - -// CP_ME_MC_WADDR_LO -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002 - -// CP_ME_MC_WADDR_HI -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000 -#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x00000016 - -// CP_ME_MC_WDATA_LO -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000 - -// CP_ME_MC_WDATA_HI -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000 - -// CP_ME_MC_RADDR_LO -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002 - -// CP_ME_MC_RADDR_HI -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000 -#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x00000016 - -// CP_SEM_WAIT_TIMER -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x00000000 - -// CP_SIG_SEM_ADDR_LO -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 - -// CP_SIG_SEM_ADDR_HI -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d - -// CP_WAIT_SEM_ADDR_LO -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 - -// CP_WAIT_SEM_ADDR_HI -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d - -// CP_WAIT_REG_MEM_TIMEOUT -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x00000000 - -// CP_COHER_START_DELAY -#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000 - -// CP_COHER_CNTL -#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x00000003 -#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x00000004 -#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x00000005 -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0x0000000f -#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012 -#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016 -#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017 -#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019 -#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x0000001c -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x0000001e - -// CP_COHER_SIZE -#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000 - -// CP_COHER_SIZE_HI -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000 - -// CP_COHER_BASE -#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000 - -// CP_COHER_BASE_HI -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000 - -// CP_COHER_STATUS -#define CP_COHER_STATUS__MEID__SHIFT 0x00000018 -#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f - -// CP_DMA_PIO_SRC_ADDR -#define CP_DMA_PIO_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 - -// CP_DMA_PIO_SRC_ADDR_HI -#define CP_DMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 - -// CP_DMA_PIO_DST_ADDR -#define CP_DMA_PIO_DST_ADDR__DST_ADDR__SHIFT 0x00000000 - -// CP_DMA_PIO_DST_ADDR_HI -#define CP_DMA_PIO_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 - -// CP_DMA_PIO_CONTROL -#define CP_DMA_PIO_CONTROL__MEMLOG_CLEAR__SHIFT 0x0000000a -#define CP_DMA_PIO_CONTROL__SRC_CACHE_POLICY__SHIFT 0x0000000d -#define CP_DMA_PIO_CONTROL__DST_SELECT__SHIFT 0x00000014 -#define CP_DMA_PIO_CONTROL__DST_CACHE_POLICY__SHIFT 0x00000019 -#define CP_DMA_PIO_CONTROL__SRC_SELECT__SHIFT 0x0000001d - -// CP_DMA_PIO_COMMAND -#define CP_DMA_PIO_COMMAND__BYTE_COUNT__SHIFT 0x00000000 -#define CP_DMA_PIO_COMMAND__SAS__SHIFT 0x0000001a -#define CP_DMA_PIO_COMMAND__DAS__SHIFT 0x0000001b -#define CP_DMA_PIO_COMMAND__SAIC__SHIFT 0x0000001c -#define CP_DMA_PIO_COMMAND__DAIC__SHIFT 0x0000001d -#define CP_DMA_PIO_COMMAND__RAW_WAIT__SHIFT 0x0000001e -#define CP_DMA_PIO_COMMAND__DIS_WC__SHIFT 0x0000001f - -// CP_DMA_ME_SRC_ADDR -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 - -// CP_DMA_ME_SRC_ADDR_HI -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 - -// CP_DMA_ME_DST_ADDR -#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000 - -// CP_DMA_ME_DST_ADDR_HI -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 - -// CP_DMA_ME_CONTROL -#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0x0000000a -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0x0000000d -#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x00000014 -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x00000019 -#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x0000001d - -// CP_DMA_ME_COMMAND -#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000 -#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a -#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b -#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c -#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d -#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e -#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x0000001f - -// CP_DMA_PFP_SRC_ADDR -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 - -// CP_DMA_PFP_SRC_ADDR_HI -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 - -// CP_DMA_PFP_DST_ADDR -#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000 - -// CP_DMA_PFP_DST_ADDR_HI -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 - -// CP_DMA_PFP_CONTROL -#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0x0000000a -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0x0000000d -#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x00000014 -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x00000019 -#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x0000001d - -// CP_DMA_PFP_COMMAND -#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000 -#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a -#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b -#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c -#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d -#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e -#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x0000001f - -// CP_DMA_CNTL -#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x00000000 -#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004 -#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010 -#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c -#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d -#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e - -// CP_DMA_READ_TAGS -#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000 -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c - -// CP_PFP_IB_CONTROL -#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000 - -// CP_PFP_LOAD_CONTROL -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000 -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001 -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010 -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018 - -// CP_SCRATCH_INDEX -#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000 - -// CP_SCRATCH_DATA -#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000 - -// CP_RB_OFFSET -#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000 - -// CP_IB1_OFFSET -#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000 - -// CP_IB2_OFFSET -#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000 - -// CP_IB1_PREAMBLE_BEGIN -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000 - -// CP_IB1_PREAMBLE_END -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000 - -// CP_IB2_PREAMBLE_BEGIN -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000 - -// CP_IB2_PREAMBLE_END -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000 - -// CP_CE_IB1_OFFSET -#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000 - -// CP_CE_IB2_OFFSET -#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000 - -// CP_CE_COUNTER -#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x00000000 - -// CP_CE_RB_OFFSET -#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000 - -// CP_PFP_COMPLETION_STATUS -#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x00000000 - -// CP_CE_COMPLETION_STATUS -#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x00000000 - -// CP_PRED_NOT_VISIBLE -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x00000000 - -// CP_PFP_METADATA_BASE_ADDR -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x00000000 - -// CP_PFP_METADATA_BASE_ADDR_HI -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_CE_METADATA_BASE_ADDR -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x00000000 - -// CP_CE_METADATA_BASE_ADDR_HI -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_DRAW_INDX_INDR_ADDR -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x00000000 - -// CP_DRAW_INDX_INDR_ADDR_HI -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_DISPATCH_INDR_ADDR -#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x00000000 - -// CP_DISPATCH_INDR_ADDR_HI -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_INDEX_BASE_ADDR -#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x00000000 - -// CP_INDEX_BASE_ADDR_HI -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_INDEX_TYPE -#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 - -// CP_GDS_BKUP_ADDR -#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x00000000 - -// CP_GDS_BKUP_ADDR_HI -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x00000000 - -// CP_SAMPLE_STATUS -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x00000000 -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x00000001 -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x00000002 -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x00000003 -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x00000004 -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x00000005 -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x00000006 -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x00000007 - -// CP_ME_COHER_CNTL -#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000 -#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001 -#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006 -#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007 -#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008 -#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009 -#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a -#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b -#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c -#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d -#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e -#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013 -#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015 - -// CP_ME_COHER_SIZE -#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000 - -// CP_ME_COHER_SIZE_HI -#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000 - -// CP_ME_COHER_BASE -#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000 - -// CP_ME_COHER_BASE_HI -#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000 - -// CP_ME_COHER_STATUS -#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000 -#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x0000001f - -// CP_CE_INIT_CMD_BUFSZ -#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x00000000 - -// CP_CE_IB1_CMD_BUFSZ -#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x00000000 - -// CP_CE_IB2_CMD_BUFSZ -#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x00000000 - -// CP_IB1_CMD_BUFSZ -#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x00000000 - -// CP_IB2_CMD_BUFSZ -#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x00000000 - -// CP_ST_CMD_BUFSZ -#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x00000000 - -// CP_CE_INIT_BASE_LO -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005 - -// CP_CE_INIT_BASE_HI -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000 - -// CP_CE_INIT_BUFSZ -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000 - -// CP_CE_IB1_BASE_LO -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 - -// CP_CE_IB1_BASE_HI -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 - -// CP_CE_IB1_BUFSZ -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 - -// CP_CE_IB2_BASE_LO -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 - -// CP_CE_IB2_BASE_HI -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 - -// CP_CE_IB2_BUFSZ -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 - -// CP_IB1_BASE_LO -#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 - -// CP_IB1_BASE_HI -#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 - -// CP_IB1_BUFSZ -#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 - -// CP_IB2_BASE_LO -#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 - -// CP_IB2_BASE_HI -#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 - -// CP_IB2_BUFSZ -#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 - -// CP_ST_BASE_LO -#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x00000002 - -// CP_ST_BASE_HI -#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x00000000 - -// CP_ST_BUFSZ -#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 - -// CPG_PERFCOUNTER1_LO -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CPG_PERFCOUNTER1_HI -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CPG_PERFCOUNTER0_LO -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CPG_PERFCOUNTER0_HI -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CPC_PERFCOUNTER1_LO -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CPC_PERFCOUNTER1_HI -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CPC_PERFCOUNTER0_LO -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CPC_PERFCOUNTER0_HI -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CPF_PERFCOUNTER1_LO -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CPF_PERFCOUNTER1_HI -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CPF_PERFCOUNTER0_LO -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// CPF_PERFCOUNTER0_HI -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// CPF_LATENCY_STATS_DATA -#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x00000000 - -// CPG_LATENCY_STATS_DATA -#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x00000000 - -// CPC_LATENCY_STATS_DATA -#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x00000000 - -// CPG_PERFCOUNTER1_SELECT -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x00000000 -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0x0000000a -#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014 -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x00000018 -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x0000001c - -// CPG_PERFCOUNTER0_SELECT1 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x00000000 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0x0000000a -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x00000018 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x0000001c - -// CPG_PERFCOUNTER0_SELECT -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x00000000 -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0x0000000a -#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014 -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x00000018 -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x0000001c - -// CPC_PERFCOUNTER1_SELECT -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x00000000 -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0x0000000a -#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014 -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x00000018 -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x0000001c - -// CPC_PERFCOUNTER0_SELECT1 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x00000000 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0x0000000a -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x00000018 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x0000001c - -// CPC_PERFCOUNTER0_SELECT -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x00000000 -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0x0000000a -#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014 -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x00000018 -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x0000001c - -// CPF_PERFCOUNTER1_SELECT -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x00000000 -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0x0000000a -#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014 -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x00000018 -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x0000001c - -// CPF_PERFCOUNTER0_SELECT1 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x00000000 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0x0000000a -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x00000018 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x0000001c - -// CPF_PERFCOUNTER0_SELECT -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x00000000 -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0x0000000a -#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014 -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x00000018 -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x0000001c - -// CPF_TC_PERF_COUNTER_WINDOW_SELECT -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x00000000 -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x0000001e -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x0000001f - -// CPG_TC_PERF_COUNTER_WINDOW_SELECT -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x00000000 -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x0000001e -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x0000001f - -// CPF_LATENCY_STATS_SELECT -#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x00000000 -#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x0000001e -#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x0000001f - -// CPG_LATENCY_STATS_SELECT -#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x00000000 -#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x0000001e -#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x0000001f - -// CPC_LATENCY_STATS_SELECT -#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x00000000 -#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x0000001e -#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x0000001f - -// CP_DRAW_OBJECT -#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x00000000 - -// CP_DRAW_OBJECT_COUNTER -#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x00000000 - -// CP_DRAW_WINDOW_MASK_HI -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x00000000 - -// CP_DRAW_WINDOW_HI -#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x00000000 - -// CP_DRAW_WINDOW_LO -#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x00000000 -#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x00000010 - -// CP_DRAW_WINDOW_CNTL -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x00000000 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x00000001 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x00000002 -#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x00000008 - -// CP_PERFMON_CNTL -#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x00000004 -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a - -// CGTT_CPC_CLK_CTRL -#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0x0000000f -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x0000001d -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f - -// CGTT_CPF_CLK_CTRL -#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0x0000000f -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x0000001d -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f - -// CGTT_CP_CLK_CTRL -#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0x0000000f -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x0000001d -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f - -// CP_HYP_PFP_UCODE_ADDR -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_PFP_UCODE_ADDR -#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_HYP_PFP_UCODE_DATA -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_PFP_UCODE_DATA -#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_HYP_ME_UCODE_ADDR -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_ME_RAM_RADDR -#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 - -// CP_ME_RAM_WADDR -#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 - -// CP_HYP_ME_UCODE_DATA -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_ME_RAM_DATA -#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 - -// CP_HYP_CE_UCODE_ADDR -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_CE_UCODE_ADDR -#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_HYP_CE_UCODE_DATA -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_CE_UCODE_DATA -#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_HYP_MEC1_UCODE_ADDR -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_MEC_ME1_UCODE_ADDR -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_HYP_MEC1_UCODE_DATA -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_MEC_ME1_UCODE_DATA -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_HYP_MEC2_UCODE_ADDR -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_MEC_ME2_UCODE_ADDR -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 - -// CP_HYP_MEC2_UCODE_DATA -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_MEC_ME2_UCODE_DATA -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 - -// CP_HYP_PFP_UCODE_CHKSUM -#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x00000000 - -// CP_HYP_CE_UCODE_CHKSUM -#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x00000000 - -// CP_HYP_ME_UCODE_CHKSUM -#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x00000000 - -// CP_HYP_MEC_ME1_UCODE_CHKSUM -#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x00000000 - -// CP_HYP_MEC_ME2_UCODE_CHKSUM -#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x00000000 - -// CP_HYP_CONFIG_RANGE_BASE_1 -#define CP_HYP_CONFIG_RANGE_BASE_1__BASE__SHIFT 0x00000000 - -// CP_HYP_CONFIG_RANGE_END_1 -#define CP_HYP_CONFIG_RANGE_END_1__END__SHIFT 0x00000000 - -// CP_HYP_SHADER_RANGE_BASE -#define CP_HYP_SHADER_RANGE_BASE__BASE__SHIFT 0x00000000 - -// CP_HYP_SHADER_RANGE_END -#define CP_HYP_SHADER_RANGE_END__END__SHIFT 0x00000000 - -// CP_HYP_CONFIG_RANGE_BASE_2 -#define CP_HYP_CONFIG_RANGE_BASE_2__BASE__SHIFT 0x00000000 - -// CP_HYP_CONFIG_RANGE_END_2 -#define CP_HYP_CONFIG_RANGE_END_2__END__SHIFT 0x00000000 - -// CP_HYP_CONTEXT_RANGE_BASE -#define CP_HYP_CONTEXT_RANGE_BASE__BASE__SHIFT 0x00000000 - -// CP_HYP_CONTEXT_RANGE_END -#define CP_HYP_CONTEXT_RANGE_END__END__SHIFT 0x00000000 - -// CP_HYP_UCONFIG_RANGE_BASE -#define CP_HYP_UCONFIG_RANGE_BASE__BASE__SHIFT 0x00000000 - -// CP_HYP_UCONFIG_RANGE_END -#define CP_HYP_UCONFIG_RANGE_END__END__SHIFT 0x00000000 - -// CP_HYP_CPC_SECURE_REG0 -#define CP_HYP_CPC_SECURE_REG0__DATA__SHIFT 0x00000000 - -// CP_HYP_CPC_SECURE_REG1 -#define CP_HYP_CPC_SECURE_REG1__DATA__SHIFT 0x00000000 - -// CP_HYP_CPC_SECURE_REG2 -#define CP_HYP_CPC_SECURE_REG2__DATA__SHIFT 0x00000000 - -// CP_HYP_CPC_SECURE_REG3 -#define CP_HYP_CPC_SECURE_REG3__DATA__SHIFT 0x00000000 - -// CP_HYP_FIREWALL_MODIFIED_MASK -#define CP_HYP_FIREWALL_MODIFIED_MASK__ME0_PIPE_MASK__SHIFT 0x00000000 -#define CP_HYP_FIREWALL_MODIFIED_MASK__ME1_PIPE_MASK__SHIFT 0x00000008 -#define CP_HYP_FIREWALL_MODIFIED_MASK__ME2_PIPE_MASK__SHIFT 0x00000010 - -// CP_PSP_REG_PRIV_LEVEL_A -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL0__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL1__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL2__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL3__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL4__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL5__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL6__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL7__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL8__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL9__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL10__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL11__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL12__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL13__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL14__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_A__PRIV_LEVEL15__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_B -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL16__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL17__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL18__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL19__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL20__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL21__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL22__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL23__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL24__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL25__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL26__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL27__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL28__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL29__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL30__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_B__PRIV_LEVEL31__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_C -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL32__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL33__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL34__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL35__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL36__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL37__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL38__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL39__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL40__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL41__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL42__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL43__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL44__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL45__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL46__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_C__PRIV_LEVEL47__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_D -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL48__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL49__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL50__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL51__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL52__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL53__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL54__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL55__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL56__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL57__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL58__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL59__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL60__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL61__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL62__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_D__PRIV_LEVEL63__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_E -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL64__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL65__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL66__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL67__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL68__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL69__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL70__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL71__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL72__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL73__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL74__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL75__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL76__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL77__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL78__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_E__PRIV_LEVEL79__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_F -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL80__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL81__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL82__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL83__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL84__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL85__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL86__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL87__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL88__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL89__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL90__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL91__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL92__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL93__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL94__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_F__PRIV_LEVEL95__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_G -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL96__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL97__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL98__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL99__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL100__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL101__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL102__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL103__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL104__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL105__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL106__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL107__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL108__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL109__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL110__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_G__PRIV_LEVEL111__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_H -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL112__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL113__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL114__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL115__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL116__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL117__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL118__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL119__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL120__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL121__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL122__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL123__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL124__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL125__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL126__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_H__PRIV_LEVEL127__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_I -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL128__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL129__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL130__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL131__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL132__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL133__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL134__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL135__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL136__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL137__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL138__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL139__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL140__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL141__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL142__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_I__PRIV_LEVEL143__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_J -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL144__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL145__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL146__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL147__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL148__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL149__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL150__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL151__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL152__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL153__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL154__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL155__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL156__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL157__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL158__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_J__PRIV_LEVEL159__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_K -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL160__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL161__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL162__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL163__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL164__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL165__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL166__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL167__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL168__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL169__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL170__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL171__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL172__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL173__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL174__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_K__PRIV_LEVEL175__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_L -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL176__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL177__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL178__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL179__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL180__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL181__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL182__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL183__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL184__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL185__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL186__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL187__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL188__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL189__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL190__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_L__PRIV_LEVEL191__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_M -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL192__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL193__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL194__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL195__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL196__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL197__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL198__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL199__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL200__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL201__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL202__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL203__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL204__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL205__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL206__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_M__PRIV_LEVEL207__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_N -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL208__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL209__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL210__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL211__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL212__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL213__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL214__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL215__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL216__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL217__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL218__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL219__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL220__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL221__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL222__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_N__PRIV_LEVEL223__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_O -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL224__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL225__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL226__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL227__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL228__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL229__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL230__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL231__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL232__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL233__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL234__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL235__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL236__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL237__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL238__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_O__PRIV_LEVEL239__SHIFT 0x0000001e - -// CP_PSP_REG_PRIV_LEVEL_P -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL240__SHIFT 0x00000000 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL241__SHIFT 0x00000002 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL242__SHIFT 0x00000004 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL243__SHIFT 0x00000006 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL244__SHIFT 0x00000008 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL245__SHIFT 0x0000000a -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL246__SHIFT 0x0000000c -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL247__SHIFT 0x0000000e -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL248__SHIFT 0x00000010 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL249__SHIFT 0x00000012 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL250__SHIFT 0x00000014 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL251__SHIFT 0x00000016 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL252__SHIFT 0x00000018 -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL253__SHIFT 0x0000001a -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL254__SHIFT 0x0000001c -#define CP_PSP_REG_PRIV_LEVEL_P__PRIV_LEVEL255__SHIFT 0x0000001e - -// CPG_PSP_DEBUG -#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x00000000 -#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x00000002 - -// CPC_PSP_DEBUG -#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x00000000 -#define CPC_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x00000002 - -// CPF_PSP_DEBUG -#define CPF_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x00000000 -#define CPF_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x00000002 - -// CP_PSP_FIREWALL_MODIFIED_MASK -#define CP_PSP_FIREWALL_MODIFIED_MASK__ME0_PIPE_MASK__SHIFT 0x00000000 -#define CP_PSP_FIREWALL_MODIFIED_MASK__ME1_PIPE_MASK__SHIFT 0x00000008 -#define CP_PSP_FIREWALL_MODIFIED_MASK__ME2_PIPE_MASK__SHIFT 0x00000010 - -// SQ_SOPK -#define SQ_SOPK__SIMM16__SHIFT 0x00000000 -#define SQ_SOPK__SDST__SHIFT 0x00000010 -#define SQ_SOPK__OP__SHIFT 0x00000017 -#define SQ_SOPK__ENCODING__SHIFT 0x0000001c - -// SQ_VINTRP -#define SQ_VINTRP__VSRC__SHIFT 0x00000000 -#define SQ_VINTRP__ATTRCHAN__SHIFT 0x00000008 -#define SQ_VINTRP__ATTR__SHIFT 0x0000000a -#define SQ_VINTRP__OP__SHIFT 0x00000010 -#define SQ_VINTRP__VDST__SHIFT 0x00000012 -#define SQ_VINTRP__ENCODING__SHIFT 0x0000001a - -// SQ_SCRATCH_0 -#define SQ_SCRATCH_0__OFFSET__SHIFT 0x00000000 -#define SQ_SCRATCH_0__LDS__SHIFT 0x0000000d -#define SQ_SCRATCH_0__SEG__SHIFT 0x0000000e -#define SQ_SCRATCH_0__GLC__SHIFT 0x00000010 -#define SQ_SCRATCH_0__SLC__SHIFT 0x00000011 -#define SQ_SCRATCH_0__OP__SHIFT 0x00000012 -#define SQ_SCRATCH_0__ENCODING__SHIFT 0x0000001a - -// SQ_VOP3_0 -#define SQ_VOP3_0__VDST__SHIFT 0x00000000 -#define SQ_VOP3_0__ABS__SHIFT 0x00000008 -#define SQ_VOP3_0__OP_SEL__SHIFT 0x0000000b -#define SQ_VOP3_0__CLAMP__SHIFT 0x0000000f -#define SQ_VOP3_0__OP__SHIFT 0x00000010 -#define SQ_VOP3_0__ENCODING__SHIFT 0x0000001a - -// SQ_FLAT_0 -#define SQ_FLAT_0__OFFSET__SHIFT 0x00000000 -#define SQ_FLAT_0__LDS__SHIFT 0x0000000d -#define SQ_FLAT_0__SEG__SHIFT 0x0000000e -#define SQ_FLAT_0__GLC__SHIFT 0x00000010 -#define SQ_FLAT_0__SLC__SHIFT 0x00000011 -#define SQ_FLAT_0__OP__SHIFT 0x00000012 -#define SQ_FLAT_0__ENCODING__SHIFT 0x0000001a - -// SQ_SMEM_0 -#define SQ_SMEM_0__SBASE__SHIFT 0x00000000 -#define SQ_SMEM_0__SDATA__SHIFT 0x00000006 -#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0x0000000e -#define SQ_SMEM_0__NV__SHIFT 0x0000000f -#define SQ_SMEM_0__GLC__SHIFT 0x00000010 -#define SQ_SMEM_0__IMM__SHIFT 0x00000011 -#define SQ_SMEM_0__OP__SHIFT 0x00000012 -#define SQ_SMEM_0__ENCODING__SHIFT 0x0000001a - -// SQ_VOP3P_0 -#define SQ_VOP3P_0__VDST__SHIFT 0x00000000 -#define SQ_VOP3P_0__NEG_HI__SHIFT 0x00000008 -#define SQ_VOP3P_0__OP_SEL__SHIFT 0x0000000b -#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0x0000000e -#define SQ_VOP3P_0__CLAMP__SHIFT 0x0000000f -#define SQ_VOP3P_0__OP__SHIFT 0x00000010 -#define SQ_VOP3P_0__ENCODING__SHIFT 0x00000017 - -// SQ_EXP_0 -#define SQ_EXP_0__EN__SHIFT 0x00000000 -#define SQ_EXP_0__TGT__SHIFT 0x00000004 -#define SQ_EXP_0__COMPR__SHIFT 0x0000000a -#define SQ_EXP_0__DONE__SHIFT 0x0000000b -#define SQ_EXP_0__VM__SHIFT 0x0000000c -#define SQ_EXP_0__ENCODING__SHIFT 0x0000001a - -// SQ_VOP3P_1 -#define SQ_VOP3P_1__SRC0__SHIFT 0x00000000 -#define SQ_VOP3P_1__SRC1__SHIFT 0x00000009 -#define SQ_VOP3P_1__SRC2__SHIFT 0x00000012 -#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x0000001b -#define SQ_VOP3P_1__NEG__SHIFT 0x0000001d - -// SQ_SOP1 -#define SQ_SOP1__SSRC0__SHIFT 0x00000000 -#define SQ_SOP1__OP__SHIFT 0x00000008 -#define SQ_SOP1__SDST__SHIFT 0x00000010 -#define SQ_SOP1__ENCODING__SHIFT 0x00000017 - -// SQ_DS_0 -#define SQ_DS_0__OFFSET0__SHIFT 0x00000000 -#define SQ_DS_0__OFFSET1__SHIFT 0x00000008 -#define SQ_DS_0__GDS__SHIFT 0x00000010 -#define SQ_DS_0__OP__SHIFT 0x00000011 -#define SQ_DS_0__ENCODING__SHIFT 0x0000001a - -// SQ_VOP_DPP -#define SQ_VOP_DPP__SRC0__SHIFT 0x00000000 -#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x00000008 -#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x00000013 -#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x00000014 -#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x00000015 -#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x00000016 -#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x00000017 -#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x00000018 -#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x0000001c - -// SQ_MUBUF_0 -#define SQ_MUBUF_0__OFFSET__SHIFT 0x00000000 -#define SQ_MUBUF_0__OFFEN__SHIFT 0x0000000c -#define SQ_MUBUF_0__IDXEN__SHIFT 0x0000000d -#define SQ_MUBUF_0__GLC__SHIFT 0x0000000e -#define SQ_MUBUF_0__LDS__SHIFT 0x00000010 -#define SQ_MUBUF_0__SLC__SHIFT 0x00000011 -#define SQ_MUBUF_0__OP__SHIFT 0x00000012 -#define SQ_MUBUF_0__ENCODING__SHIFT 0x0000001a - -// SQ_VOP1 -#define SQ_VOP1__SRC0__SHIFT 0x00000000 -#define SQ_VOP1__OP__SHIFT 0x00000009 -#define SQ_VOP1__VDST__SHIFT 0x00000011 -#define SQ_VOP1__ENCODING__SHIFT 0x00000019 - -// SQ_GLBL_0 -#define SQ_GLBL_0__OFFSET__SHIFT 0x00000000 -#define SQ_GLBL_0__LDS__SHIFT 0x0000000d -#define SQ_GLBL_0__SEG__SHIFT 0x0000000e -#define SQ_GLBL_0__GLC__SHIFT 0x00000010 -#define SQ_GLBL_0__SLC__SHIFT 0x00000011 -#define SQ_GLBL_0__OP__SHIFT 0x00000012 -#define SQ_GLBL_0__ENCODING__SHIFT 0x0000001a - -// SQ_VOP2 -#define SQ_VOP2__SRC0__SHIFT 0x00000000 -#define SQ_VOP2__VSRC1__SHIFT 0x00000009 -#define SQ_VOP2__VDST__SHIFT 0x00000011 -#define SQ_VOP2__OP__SHIFT 0x00000019 -#define SQ_VOP2__ENCODING__SHIFT 0x0000001f - -// SQ_GLBL_1 -#define SQ_GLBL_1__ADDR__SHIFT 0x00000000 -#define SQ_GLBL_1__DATA__SHIFT 0x00000008 -#define SQ_GLBL_1__SADDR__SHIFT 0x00000010 -#define SQ_GLBL_1__NV__SHIFT 0x00000017 -#define SQ_GLBL_1__VDST__SHIFT 0x00000018 - -// SQ_MTBUF_0 -#define SQ_MTBUF_0__OFFSET__SHIFT 0x00000000 -#define SQ_MTBUF_0__OFFEN__SHIFT 0x0000000c -#define SQ_MTBUF_0__IDXEN__SHIFT 0x0000000d -#define SQ_MTBUF_0__GLC__SHIFT 0x0000000e -#define SQ_MTBUF_0__OP__SHIFT 0x0000000f -#define SQ_MTBUF_0__DFMT__SHIFT 0x00000013 -#define SQ_MTBUF_0__NFMT__SHIFT 0x00000017 -#define SQ_MTBUF_0__ENCODING__SHIFT 0x0000001a - -// SQ_SOPP -#define SQ_SOPP__SIMM16__SHIFT 0x00000000 -#define SQ_SOPP__OP__SHIFT 0x00000010 -#define SQ_SOPP__ENCODING__SHIFT 0x00000017 - -// SQ_VOP_SDWA -#define SQ_VOP_SDWA__SRC0__SHIFT 0x00000000 -#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x00000008 -#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0x0000000b -#define SQ_VOP_SDWA__CLAMP__SHIFT 0x0000000d -#define SQ_VOP_SDWA__OMOD__SHIFT 0x0000000e -#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x00000010 -#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x00000013 -#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x00000014 -#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x00000015 -#define SQ_VOP_SDWA__S0__SHIFT 0x00000017 -#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x00000018 -#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x0000001b -#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x0000001c -#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x0000001d -#define SQ_VOP_SDWA__S1__SHIFT 0x0000001f - -// SQ_VOP3_0_SDST_ENC -#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x00000000 -#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x00000008 -#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0x0000000f -#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x00000010 -#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x0000001a - -// SQ_MIMG_0 -#define SQ_MIMG_0__OPM__SHIFT 0x00000000 -#define SQ_MIMG_0__DMASK__SHIFT 0x00000008 -#define SQ_MIMG_0__UNORM__SHIFT 0x0000000c -#define SQ_MIMG_0__GLC__SHIFT 0x0000000d -#define SQ_MIMG_0__DA__SHIFT 0x0000000e -#define SQ_MIMG_0__A16__SHIFT 0x0000000f -#define SQ_MIMG_0__TFE__SHIFT 0x00000010 -#define SQ_MIMG_0__LWE__SHIFT 0x00000011 -#define SQ_MIMG_0__OP__SHIFT 0x00000012 -#define SQ_MIMG_0__SLC__SHIFT 0x00000019 -#define SQ_MIMG_0__ENCODING__SHIFT 0x0000001a - -// SQ_VOPC -#define SQ_VOPC__SRC0__SHIFT 0x00000000 -#define SQ_VOPC__VSRC1__SHIFT 0x00000009 -#define SQ_VOPC__OP__SHIFT 0x00000011 -#define SQ_VOPC__ENCODING__SHIFT 0x00000019 - -// SQ_VOP_SDWA_SDST_ENC -#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x00000000 -#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x00000008 -#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0x0000000f -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x00000010 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x00000013 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x00000014 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x00000015 -#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x00000017 -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x00000018 -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x0000001b -#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x0000001c -#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x0000001d -#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x0000001f - -// SQ_EXP_1 -#define SQ_EXP_1__VSRC0__SHIFT 0x00000000 -#define SQ_EXP_1__VSRC1__SHIFT 0x00000008 -#define SQ_EXP_1__VSRC2__SHIFT 0x00000010 -#define SQ_EXP_1__VSRC3__SHIFT 0x00000018 - -// SQ_SMEM_1 -#define SQ_SMEM_1__OFFSET__SHIFT 0x00000000 -#define SQ_SMEM_1__SOFFSET__SHIFT 0x00000019 - -// SQ_MTBUF_1 -#define SQ_MTBUF_1__VADDR__SHIFT 0x00000000 -#define SQ_MTBUF_1__VDATA__SHIFT 0x00000008 -#define SQ_MTBUF_1__SRSRC__SHIFT 0x00000010 -#define SQ_MTBUF_1__SLC__SHIFT 0x00000016 -#define SQ_MTBUF_1__TFE__SHIFT 0x00000017 -#define SQ_MTBUF_1__SOFFSET__SHIFT 0x00000018 - -// SQ_FLAT_1 -#define SQ_FLAT_1__ADDR__SHIFT 0x00000000 -#define SQ_FLAT_1__DATA__SHIFT 0x00000008 -#define SQ_FLAT_1__SADDR__SHIFT 0x00000010 -#define SQ_FLAT_1__NV__SHIFT 0x00000017 -#define SQ_FLAT_1__VDST__SHIFT 0x00000018 - -// SQ_SOPC -#define SQ_SOPC__SSRC0__SHIFT 0x00000000 -#define SQ_SOPC__SSRC1__SHIFT 0x00000008 -#define SQ_SOPC__OP__SHIFT 0x00000010 -#define SQ_SOPC__ENCODING__SHIFT 0x00000017 - -// SQ_MIMG_1 -#define SQ_MIMG_1__VADDR__SHIFT 0x00000000 -#define SQ_MIMG_1__VDATA__SHIFT 0x00000008 -#define SQ_MIMG_1__SRSRC__SHIFT 0x00000010 -#define SQ_MIMG_1__SSAMP__SHIFT 0x00000015 -#define SQ_MIMG_1__D16__SHIFT 0x0000001f - -// SQ_VOP3_1 -#define SQ_VOP3_1__SRC0__SHIFT 0x00000000 -#define SQ_VOP3_1__SRC1__SHIFT 0x00000009 -#define SQ_VOP3_1__SRC2__SHIFT 0x00000012 -#define SQ_VOP3_1__OMOD__SHIFT 0x0000001b -#define SQ_VOP3_1__NEG__SHIFT 0x0000001d - -// SQ_DS_1 -#define SQ_DS_1__ADDR__SHIFT 0x00000000 -#define SQ_DS_1__DATA0__SHIFT 0x00000008 -#define SQ_DS_1__DATA1__SHIFT 0x00000010 -#define SQ_DS_1__VDST__SHIFT 0x00000018 - -// SQ_MUBUF_1 -#define SQ_MUBUF_1__VADDR__SHIFT 0x00000000 -#define SQ_MUBUF_1__VDATA__SHIFT 0x00000008 -#define SQ_MUBUF_1__SRSRC__SHIFT 0x00000010 -#define SQ_MUBUF_1__TFE__SHIFT 0x00000017 -#define SQ_MUBUF_1__SOFFSET__SHIFT 0x00000018 - -// SQ_SOP2 -#define SQ_SOP2__SSRC0__SHIFT 0x00000000 -#define SQ_SOP2__SSRC1__SHIFT 0x00000008 -#define SQ_SOP2__SDST__SHIFT 0x00000010 -#define SQ_SOP2__OP__SHIFT 0x00000017 -#define SQ_SOP2__ENCODING__SHIFT 0x0000001e - -// SQ_INST -#define SQ_INST__ENCODING__SHIFT 0x00000000 - -// SQ_SCRATCH_1 -#define SQ_SCRATCH_1__ADDR__SHIFT 0x00000000 -#define SQ_SCRATCH_1__DATA__SHIFT 0x00000008 -#define SQ_SCRATCH_1__SADDR__SHIFT 0x00000010 -#define SQ_SCRATCH_1__NV__SHIFT 0x00000017 -#define SQ_SCRATCH_1__VDST__SHIFT 0x00000018 - -// DIDT_IND_INDEX -#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x00000000 - -// DIDT_IND_DATA -#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x00000000 - -// DIDT_SQ_CTRL0 -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x00000000 -#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x00000001 -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x00000003 -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000004 -#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x00000005 -#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x00000006 -#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x00000007 -#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x00000008 -#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x00000018 -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x00000019 -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x0000001a -#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x0000001b - -// DIDT_SQ_CTRL1 -#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x00000000 -#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x00000010 - -// DIDT_SQ_CTRL2 -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0x0000000e -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x0000001a -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x0000001f - -// DIDT_SQ_STALL_CTRL -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000000 -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000006 -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x0000000c -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x00000012 -#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x00000018 - -// DIDT_SQ_TUNING_CTRL -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000000 -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000e - -// DIDT_SQ_STALL_AUTO_RELEASE_CTRL -#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x00000000 - -// DIDT_SQ_CTRL3 -#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x00000000 -#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000001 -#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x00000002 -#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x00000009 -#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x0000000e -#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x00000017 -#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x00000018 -#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x00000019 -#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x0000001b -#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x0000001c - -// DIDT_SQ_STALL_PATTERN_1_2 -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_SQ_STALL_PATTERN_3_4 -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_SQ_STALL_PATTERN_5_6 -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_SQ_STALL_PATTERN_7 -#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_SQ_WEIGHT0_3 -#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x00000000 -#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x00000008 -#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x00000010 -#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x00000018 - -// DIDT_SQ_WEIGHT4_7 -#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x00000000 -#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x00000008 -#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x00000010 -#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x00000018 - -// DIDT_SQ_WEIGHT8_11 -#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x00000000 -#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x00000008 -#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x00000010 -#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x00000018 - -// DIDT_SQ_EDC_CTRL -#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x00000000 -#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x00000001 -#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x00000002 -#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x00000003 -#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x00000009 -#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x00000011 -#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x00000012 -#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x00000013 -#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x00000015 -#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x00000017 - -// DIDT_SQ_EDC_THRESHOLD -#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x00000000 - -// DIDT_SQ_EDC_STALL_PATTERN_1_2 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_SQ_EDC_STALL_PATTERN_3_4 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_SQ_EDC_STALL_PATTERN_5_6 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_SQ_EDC_STALL_PATTERN_7 -#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_SQ_EDC_STATUS -#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x00000001 - -// DIDT_SQ_EDC_STALL_DELAY_1 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x00000008 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0x00000010 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x00000018 - -// DIDT_SQ_EDC_STALL_DELAY_2 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x00000008 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0x00000010 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x00000018 - -// DIDT_SQ_EDC_STALL_DELAY_3 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x00000008 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0x00000010 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT 0x00000018 - -// DIDT_SQ_EDC_STALL_DELAY_4 -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT 0x00000000 -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT 0x00000008 -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT 0x00000010 -#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT 0x00000018 - -// DIDT_SQ_EDC_OVERFLOW -#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x00000000 -#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x00000001 - -// DIDT_SQ_EDC_ROLLING_POWER_DELTA -#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x00000000 - -// DIDT_DB_CTRL0 -#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x00000000 -#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x00000001 -#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x00000003 -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000004 -#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x00000005 -#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x00000006 -#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x00000007 -#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x00000008 -#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x00000018 -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x00000019 -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x0000001a -#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x0000001b - -// DIDT_DB_CTRL1 -#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x00000000 -#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x00000010 - -// DIDT_DB_CTRL2 -#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0x0000000e -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x0000001a -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x0000001f - -// DIDT_DB_STALL_CTRL -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000000 -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000006 -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x0000000c -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x00000012 -#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x00000018 - -// DIDT_DB_TUNING_CTRL -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000000 -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000e - -// DIDT_DB_STALL_AUTO_RELEASE_CTRL -#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x00000000 - -// DIDT_DB_CTRL3 -#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x00000000 -#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000001 -#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x00000002 -#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x00000009 -#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x0000000e -#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x00000017 -#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x00000018 -#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x00000019 -#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x0000001b -#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x0000001c - -// DIDT_DB_STALL_PATTERN_1_2 -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DB_STALL_PATTERN_3_4 -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DB_STALL_PATTERN_5_6 -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DB_STALL_PATTERN_7 -#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_DB_WEIGHT0_3 -#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x00000000 -#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x00000008 -#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x00000010 -#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x00000018 - -// DIDT_DB_WEIGHT4_7 -#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x00000000 -#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x00000008 -#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x00000010 -#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x00000018 - -// DIDT_DB_WEIGHT8_11 -#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x00000000 -#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x00000008 -#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x00000010 -#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x00000018 - -// DIDT_DB_EDC_CTRL -#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x00000000 -#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x00000001 -#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x00000002 -#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x00000003 -#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x00000009 -#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x00000011 -#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x00000012 -#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x00000013 -#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x00000015 -#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x00000017 - -// DIDT_DB_EDC_THRESHOLD -#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x00000000 - -// DIDT_DB_EDC_STALL_PATTERN_1_2 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DB_EDC_STALL_PATTERN_3_4 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DB_EDC_STALL_PATTERN_5_6 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DB_EDC_STALL_PATTERN_7 -#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_DB_EDC_STATUS -#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x00000000 -#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x00000001 - -// DIDT_DB_EDC_STALL_DELAY_1 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x00000000 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x00000006 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0x0000000c -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0x00000012 -#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x00000018 - -// DIDT_DB_EDC_OVERFLOW -#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x00000000 -#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x00000001 - -// DIDT_DB_EDC_ROLLING_POWER_DELTA -#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x00000000 - -// DIDT_TD_CTRL0 -#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x00000000 -#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x00000001 -#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x00000003 -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000004 -#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x00000005 -#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x00000006 -#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x00000007 -#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x00000008 -#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x00000018 -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x00000019 -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x0000001a -#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x0000001b - -// DIDT_TD_CTRL1 -#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x00000000 -#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x00000010 - -// DIDT_TD_CTRL2 -#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0x0000000e -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x0000001a -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x0000001f - -// DIDT_TD_STALL_CTRL -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000000 -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000006 -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x0000000c -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x00000012 -#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x00000018 - -// DIDT_TD_TUNING_CTRL -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000000 -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000e - -// DIDT_TD_STALL_AUTO_RELEASE_CTRL -#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x00000000 - -// DIDT_TD_CTRL3 -#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x00000000 -#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000001 -#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x00000002 -#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x00000009 -#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x0000000e -#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x00000017 -#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x00000018 -#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x00000019 -#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x0000001b -#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x0000001c - -// DIDT_TD_STALL_PATTERN_1_2 -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TD_STALL_PATTERN_3_4 -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TD_STALL_PATTERN_5_6 -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TD_STALL_PATTERN_7 -#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_TD_WEIGHT0_3 -#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x00000000 -#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x00000008 -#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x00000010 -#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x00000018 - -// DIDT_TD_WEIGHT4_7 -#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x00000000 -#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x00000008 -#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x00000010 -#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x00000018 - -// DIDT_TD_WEIGHT8_11 -#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x00000000 -#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x00000008 -#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x00000010 -#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x00000018 - -// DIDT_TD_EDC_CTRL -#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x00000000 -#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x00000001 -#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x00000002 -#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x00000003 -#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x00000009 -#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x00000011 -#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x00000012 -#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x00000013 -#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x00000015 -#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x00000017 - -// DIDT_TD_EDC_THRESHOLD -#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x00000000 - -// DIDT_TD_EDC_STALL_PATTERN_1_2 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TD_EDC_STALL_PATTERN_3_4 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TD_EDC_STALL_PATTERN_5_6 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TD_EDC_STALL_PATTERN_7 -#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_TD_EDC_STATUS -#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x00000000 -#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x00000001 - -// DIDT_TD_EDC_STALL_DELAY_1 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x00000008 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0x00000010 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x00000018 - -// DIDT_TD_EDC_STALL_DELAY_2 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x00000008 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0x00000010 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x00000018 - -// DIDT_TD_EDC_STALL_DELAY_3 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x00000008 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0x00000010 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT 0x00000018 - -// DIDT_TD_EDC_STALL_DELAY_4 -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT 0x00000000 -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT 0x00000008 -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14__SHIFT 0x00000010 -#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15__SHIFT 0x00000018 - -// DIDT_TD_EDC_OVERFLOW -#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x00000000 -#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x00000001 - -// DIDT_TD_EDC_ROLLING_POWER_DELTA -#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x00000000 - -// DIDT_TCP_CTRL0 -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x00000000 -#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x00000001 -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x00000003 -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000004 -#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x00000005 -#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x00000006 -#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x00000007 -#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x00000008 -#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x00000018 -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x00000019 -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x0000001a -#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x0000001b - -// DIDT_TCP_CTRL1 -#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x00000000 -#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x00000010 - -// DIDT_TCP_CTRL2 -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0x0000000e -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x0000001a -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x0000001f - -// DIDT_TCP_STALL_CTRL -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000000 -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000006 -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x0000000c -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x00000012 -#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x00000018 - -// DIDT_TCP_TUNING_CTRL -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000000 -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000e - -// DIDT_TCP_STALL_AUTO_RELEASE_CTRL -#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x00000000 - -// DIDT_TCP_CTRL3 -#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x00000000 -#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000001 -#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x00000002 -#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x00000009 -#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x0000000e -#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x00000017 -#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x00000018 -#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x00000019 -#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x0000001b -#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x0000001c - -// DIDT_TCP_STALL_PATTERN_1_2 -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TCP_STALL_PATTERN_3_4 -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TCP_STALL_PATTERN_5_6 -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TCP_STALL_PATTERN_7 -#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_TCP_WEIGHT0_3 -#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x00000000 -#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x00000008 -#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x00000010 -#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x00000018 - -// DIDT_TCP_WEIGHT4_7 -#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x00000000 -#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x00000008 -#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x00000010 -#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x00000018 - -// DIDT_TCP_WEIGHT8_11 -#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x00000000 -#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x00000008 -#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x00000010 -#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x00000018 - -// DIDT_TCP_EDC_CTRL -#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x00000000 -#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x00000001 -#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x00000002 -#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x00000003 -#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x00000009 -#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x00000011 -#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x00000012 -#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x00000013 -#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x00000015 -#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x00000017 - -// DIDT_TCP_EDC_THRESHOLD -#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x00000000 - -// DIDT_TCP_EDC_STALL_PATTERN_1_2 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TCP_EDC_STALL_PATTERN_3_4 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TCP_EDC_STALL_PATTERN_5_6 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_TCP_EDC_STALL_PATTERN_7 -#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_TCP_EDC_STATUS -#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x00000001 - -// DIDT_TCP_EDC_STALL_DELAY_1 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x00000008 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0x00000010 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x00000018 - -// DIDT_TCP_EDC_STALL_DELAY_2 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x00000008 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0x00000010 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x00000018 - -// DIDT_TCP_EDC_STALL_DELAY_3 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x00000008 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0x00000010 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT 0x00000018 - -// DIDT_TCP_EDC_STALL_DELAY_4 -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT 0x00000000 -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT 0x00000008 -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14__SHIFT 0x00000010 -#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15__SHIFT 0x00000018 - -// DIDT_TCP_EDC_OVERFLOW -#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x00000000 -#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x00000001 - -// DIDT_TCP_EDC_ROLLING_POWER_DELTA -#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x00000000 - -// DIDT_DBR_CTRL0 -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x00000000 -#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x00000001 -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x00000003 -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000004 -#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x00000005 -#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x00000006 -#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x00000007 -#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x00000008 -#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x00000018 -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x00000019 -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x0000001a -#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x0000001b - -// DIDT_DBR_CTRL1 -#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x00000000 -#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x00000010 - -// DIDT_DBR_CTRL2 -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x00000000 -#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0x0000000e -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 -#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x0000001a -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b -#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x0000001f - -// DIDT_DBR_STALL_CTRL -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000000 -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000006 -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x0000000c -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x00000012 -#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x00000018 - -// DIDT_DBR_TUNING_CTRL -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000000 -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000e - -// DIDT_DBR_STALL_AUTO_RELEASE_CTRL -#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x00000000 - -// DIDT_DBR_CTRL3 -#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x00000000 -#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x00000001 -#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x00000002 -#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x00000009 -#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x0000000e -#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x00000017 -#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x00000018 -#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x00000019 -#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x0000001b -#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x0000001c - -// DIDT_DBR_STALL_PATTERN_1_2 -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DBR_STALL_PATTERN_3_4 -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DBR_STALL_PATTERN_5_6 -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DBR_STALL_PATTERN_7 -#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_DBR_WEIGHT0_3 -#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x00000000 -#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x00000008 -#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x00000010 -#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x00000018 - -// DIDT_DBR_WEIGHT4_7 -#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x00000000 -#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x00000008 -#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x00000010 -#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x00000018 - -// DIDT_DBR_WEIGHT8_11 -#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x00000000 -#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x00000008 -#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x00000010 -#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x00000018 - -// DIDT_DBR_EDC_CTRL -#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x00000000 -#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x00000001 -#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x00000002 -#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x00000003 -#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x00000004 -#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x00000009 -#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x00000011 -#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x00000012 -#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x00000013 -#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x00000015 -#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x00000016 -#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x00000017 - -// DIDT_DBR_EDC_THRESHOLD -#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x00000000 - -// DIDT_DBR_EDC_STALL_PATTERN_1_2 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x00000000 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x00000010 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DBR_EDC_STALL_PATTERN_3_4 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x00000000 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x00000010 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DBR_EDC_STALL_PATTERN_5_6 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x00000000 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0x0000000f -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x00000010 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x0000001f - -// DIDT_DBR_EDC_STALL_PATTERN_7 -#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x00000000 -#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0x0000000f - -// DIDT_DBR_EDC_STATUS -#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x00000000 -#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x00000001 -#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x00000004 - -// DIDT_DBR_EDC_STALL_DELAY_1 -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x00000000 -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1__SHIFT 0x00000003 -#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x00000006 - -// DIDT_DBR_EDC_OVERFLOW -#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x00000000 -#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x00000001 - -// DIDT_DBR_EDC_ROLLING_POWER_DELTA -#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x00000000 - -// DIDT_SQ_STALL_EVENT_COUNTER -#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x00000000 - -// DIDT_DB_STALL_EVENT_COUNTER -#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x00000000 - -// DIDT_TD_STALL_EVENT_COUNTER -#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x00000000 - -// DIDT_TCP_STALL_EVENT_COUNTER -#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x00000000 - -// DIDT_DBR_STALL_EVENT_COUNTER -#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x00000000 - -// SX_DEBUG_BUSY -#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x00000000 -#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x00000001 -#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x00000002 -#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x00000003 -#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x00000004 -#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x00000005 -#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x00000006 -#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x00000007 -#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x00000008 -#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x00000009 -#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0x0000000a -#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0x0000000b -#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0x0000000d -#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0x0000000e -#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0x0000000f -#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x00000010 -#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x00000011 -#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x00000012 -#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x00000013 -#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x00000014 -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x00000015 -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x00000016 -#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x00000017 -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x00000018 -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x00000019 -#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x0000001a -#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x0000001b -#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x0000001c -#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x0000001d -#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x0000001e -#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x0000001f - -// SX_DEBUG_BUSY_2 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x00000001 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x00000002 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x00000003 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x00000004 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x00000005 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x00000006 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x00000007 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x00000008 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x00000009 -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x0000000a -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x0000000b -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x0000000d -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x0000000e -#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x0000000f -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x00000010 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x00000011 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x00000012 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x00000013 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x00000014 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x00000015 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x00000016 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x00000017 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x00000018 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x00000019 -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x0000001a -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x0000001b -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x0000001c -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x0000001d -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x0000001e -#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x0000001f - -// SX_DEBUG_BUSY_3 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x00000001 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x00000002 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x00000003 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x00000004 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x00000005 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x00000006 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x00000007 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x00000008 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x00000009 -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x0000000a -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x0000000b -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x0000000d -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x0000000e -#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x0000000f -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x00000010 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x00000011 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x00000012 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x00000013 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x00000014 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x00000015 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x00000016 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x00000017 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x00000018 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x00000019 -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x0000001a -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x0000001b -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x0000001c -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x0000001d -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x0000001e -#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x0000001f - -// SX_DEBUG_BUSY_4 -#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0__SHIFT 0x00000001 -#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE__SHIFT 0x00000002 -#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY__SHIFT 0x00000003 -#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY__SHIFT 0x00000004 -#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0__SHIFT 0x00000005 -#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE__SHIFT 0x00000006 -#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY__SHIFT 0x00000007 -#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY__SHIFT 0x00000008 -#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0__SHIFT 0x00000009 -#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE__SHIFT 0x0000000a -#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY__SHIFT 0x0000000b -#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY__SHIFT 0x0000000c -#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0__SHIFT 0x0000000d -#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE__SHIFT 0x0000000e -#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY__SHIFT 0x0000000f -#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY__SHIFT 0x00000010 -#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x00000011 -#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY__SHIFT 0x00000012 -#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE__SHIFT 0x00000013 -#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x00000014 -#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY__SHIFT 0x00000015 -#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE__SHIFT 0x00000016 -#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x00000017 -#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY__SHIFT 0x00000018 -#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE__SHIFT 0x00000019 -#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x0000001a -#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY__SHIFT 0x0000001b -#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE__SHIFT 0x0000001c -#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x0000001d -#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x0000001e -#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x0000001f - -// SX_DEBUG_BUSY_5 -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x00000000 -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x00000001 -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x00000002 -#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O__SHIFT 0x00000003 -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x00000004 -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0x00000005 -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2__SHIFT 0x00000006 -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3__SHIFT 0x00000007 -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4__SHIFT 0x00000008 -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5__SHIFT 0x00000009 -#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O__SHIFT 0x0000000a -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1__SHIFT 0x0000000b -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0x0000000c -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2__SHIFT 0x0000000d -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3__SHIFT 0x0000000e -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4__SHIFT 0x0000000f -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x00000010 -#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O__SHIFT 0x00000011 -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x00000012 -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x00000013 -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x00000014 -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x00000015 -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x00000016 -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x00000017 -#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O__SHIFT 0x00000018 -#define SX_DEBUG_BUSY_5__RESERVED__SHIFT 0x00000019 - -// SX_DEBUG_1 -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x00000000 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000008 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000009 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000000a -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0x0000000b -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0x0000000c -#define SX_DEBUG_1__PC_CFG__SHIFT 0x0000000d -#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x0000000e - -// SX_PS_DOWNCONVERT -#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x00000000 -#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x00000004 -#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x00000008 -#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0x0000000c -#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x00000010 -#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x00000014 -#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x00000018 -#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x0000001c - -// SX_BLEND_OPT_EPSILON -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x00000000 -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x00000004 -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x00000008 -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0x0000000c -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x00000010 -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x00000014 -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x00000018 -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x0000001c - -// SX_BLEND_OPT_CONTROL -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x00000000 -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x00000001 -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x00000004 -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x00000005 -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x00000008 -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x00000009 -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0x0000000c -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0x0000000d -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x00000010 -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x00000011 -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x00000014 -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x00000015 -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x00000018 -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x00000019 -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x0000001c -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x0000001d -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x0000001f - -// SX_MRT0_BLEND_OPT -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_MRT1_BLEND_OPT -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_MRT2_BLEND_OPT -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_MRT3_BLEND_OPT -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_MRT4_BLEND_OPT -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_MRT5_BLEND_OPT -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_MRT6_BLEND_OPT -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_MRT7_BLEND_OPT -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x00000000 -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x00000004 -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x00000008 -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x00000010 -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x00000014 -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x00000018 - -// SX_PERFCOUNTER0_LO -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SX_PERFCOUNTER0_HI -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SX_PERFCOUNTER1_LO -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SX_PERFCOUNTER1_HI -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SX_PERFCOUNTER2_LO -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SX_PERFCOUNTER2_HI -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SX_PERFCOUNTER3_LO -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// SX_PERFCOUNTER3_HI -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// SX_PERFCOUNTER0_SELECT -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// SX_PERFCOUNTER1_SELECT -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// SX_PERFCOUNTER2_SELECT -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// SX_PERFCOUNTER3_SELECT -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// SX_PERFCOUNTER0_SELECT1 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a - -// SX_PERFCOUNTER1_SELECT1 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a - -// CGTT_SX_CLK_CTRL0 -#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// CGTT_SX_CLK_CTRL1 -#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT 0x00000018 -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// CGTT_SX_CLK_CTRL2 -#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000d -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT 0x00000018 -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// CGTT_SX_CLK_CTRL3 -#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000d -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT 0x00000018 -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// CGTT_SX_CLK_CTRL4 -#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT 0x00000018 -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// DB_DEBUG -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x00000000 -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x00000001 -#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x00000002 -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x00000003 -#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x00000004 -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x00000006 -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x00000007 -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x00000008 -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0x0000000a -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0x0000000c -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0x0000000e -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0x0000000f -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x00000010 -#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x00000011 -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x00000012 -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x00000013 -#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x00000015 -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x00000016 -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x00000017 -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x00000018 -#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x0000001c -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x0000001d -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x0000001e -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x0000001f - -// DB_DEBUG2 -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x00000000 -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x00000001 -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x00000002 -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x00000003 -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004 -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x00000005 -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x00000006 -#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x00000007 -#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x00000008 -#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x00000009 -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0x0000000e -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0x0000000f -#define DB_DEBUG2__RESERVED__SHIFT 0x00000010 -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x00000011 -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x00000012 -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x00000013 -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x0000001c -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x0000001d -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x0000001e -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x0000001f - -// DB_DEBUG3 -#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x00000000 -#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x00000001 -#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x00000002 -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x00000003 -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x00000004 -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x00000005 -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x00000006 -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x00000007 -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x00000008 -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x00000009 -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0x0000000a -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0x0000000b -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0x0000000c -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0x0000000d -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0x0000000e -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0x0000000f -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x00000010 -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x00000011 -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x00000012 -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x00000013 -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x00000014 -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x00000015 -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x00000016 -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x00000017 -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x00000018 -#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x00000019 -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x0000001a -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x0000001b -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x0000001c -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x0000001d -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x0000001e -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x0000001f - -// DB_DEBUG4 -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x00000000 -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x00000001 -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x00000002 -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x00000003 -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x00000004 -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x00000005 -#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x00000006 -#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x00000007 -#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x00000008 -#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x00000009 -#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0x0000000a -#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0x0000000b -#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0x0000000c -#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0x0000000d -#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0x0000000e -#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0x0000000f -#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x00000010 -#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x00000011 -#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x00000012 -#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x00000013 - -// DB_RMI_CACHE_POLICY -#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x00000000 -#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x00000001 -#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x00000002 -#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x00000008 -#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x00000009 -#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0x0000000a -#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0x0000000b -#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x00000010 -#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x00000011 -#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x00000012 -#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x00000013 -#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x00000018 -#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x00000019 -#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x0000001a -#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x0000001b - -// DB_CREDIT_LIMIT -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x00000000 -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x00000005 -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0x0000000a -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x00000018 - -// DB_WATERMARKS -#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x00000000 -#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x00000005 -#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0x0000000b -#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x0000000f -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x00000014 -#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x0000001e -#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x0000001f - -// DB_EXCEPTION_CONTROL -#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x00000000 -#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x00000001 -#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x00000002 - -// DB_SUBTILE_CONTROL -#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x00000000 -#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x00000002 -#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x00000004 -#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x00000006 -#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x00000008 -#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0x0000000a -#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0x0000000c -#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0x0000000e -#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x00000010 -#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x00000012 - -// DB_FREE_CACHELINES -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x00000000 -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x00000007 -#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x0000000e -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x00000014 -#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x00000018 - -// DB_FIFO_DEPTH1 -#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x00000000 -#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x00000005 -#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a -#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x00000010 -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x00000015 - -// DB_FIFO_DEPTH2 -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x00000000 -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x00000008 -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x0000000f -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x00000019 - -// DB_RING_CONTROL -#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x00000000 - -// DB_MEM_ARB_WATERMARKS -#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x00000000 -#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x00000008 -#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x00000010 -#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x00000018 - -// DB_DFSM_CONFIG -#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x00000000 -#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x00000001 -#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x00000002 -#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x00000003 -#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x00000008 - -// DB_DFSM_WATERMARK -#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x00000000 -#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x00000010 - -// DB_DFSM_TILES_IN_FLIGHT -#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x00000000 -#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x00000010 - -// DB_DFSM_PRIMS_IN_FLIGHT -#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x00000000 -#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x00000010 - -// DB_DFSM_WATCHDOG -#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x00000000 - -// DB_DFSM_FLUSH_ENABLE -#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x00000000 -#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x00000018 -#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x0000001c - -// DB_DFSM_FLUSH_AUX_EVENT -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x00000000 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x00000008 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x00000010 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x00000018 - -// DB_READ_DEBUG_0 -#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x00000000 - -// DB_READ_DEBUG_1 -#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x00000000 - -// DB_READ_DEBUG_2 -#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x00000000 - -// DB_READ_DEBUG_3 -#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_4 -#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_5 -#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_6 -#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_7 -#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_8 -#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_9 -#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_A -#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_B -#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_C -#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_D -#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_E -#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x00000000 - -// DB_READ_DEBUG_F -#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x00000000 - -// DB_Z_READ_BASE -#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x00000000 - -// DB_Z_READ_BASE_HI -#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// DB_STENCIL_READ_BASE -#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x00000000 - -// DB_STENCIL_READ_BASE_HI -#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// DB_Z_WRITE_BASE -#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x00000000 - -// DB_Z_WRITE_BASE_HI -#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// DB_STENCIL_WRITE_BASE -#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x00000000 - -// DB_STENCIL_WRITE_BASE_HI -#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// DB_DFSM_CONTROL -#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x00000000 -#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x00000002 -#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x00000003 - -// DB_Z_INFO -#define DB_Z_INFO__FORMAT__SHIFT 0x00000000 -#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x00000002 -#define DB_Z_INFO__SW_MODE__SHIFT 0x00000004 -#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0x0000000c -#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0x0000000d -#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0x0000000f -#define DB_Z_INFO__MAXMIP__SHIFT 0x00000010 -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x00000017 -#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b -#define DB_Z_INFO__READ_SIZE__SHIFT 0x0000001c -#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x0000001d -#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x0000001e -#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x0000001f - -// DB_Z_INFO2 -#define DB_Z_INFO2__EPITCH__SHIFT 0x00000000 - -// DB_STENCIL_INFO -#define DB_STENCIL_INFO__FORMAT__SHIFT 0x00000000 -#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x00000004 -#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0x0000000c -#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0x0000000d -#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0x0000000f -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x0000001d -#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x0000001e - -// DB_STENCIL_INFO2 -#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x00000000 - -// DB_DEPTH_SIZE -#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x00000000 -#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x00000010 - -// DB_DEPTH_VIEW -#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x00000000 -#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x0000000d -#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x00000018 -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x00000019 -#define DB_DEPTH_VIEW__MIPID__SHIFT 0x0000001a - -// DB_RENDER_FILTER -#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x00000000 - -// DB_RENDER_CONTROL -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000000 -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x00000001 -#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x00000002 -#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x00000003 -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x00000004 -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x00000005 -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x00000006 -#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x00000007 -#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x00000008 -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0x0000000c - -// DB_COUNT_CONTROL -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x00000000 -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x00000001 -#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x00000004 -#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x00000008 -#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0x0000000c -#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x00000010 -#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x00000014 -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x00000018 -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x0000001c - -// DB_RENDER_OVERRIDE -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x00000000 -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x00000002 -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x00000004 -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x00000006 -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x00000007 -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x00000008 -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x00000009 -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0x0000000a -#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0x0000000b -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0x0000000c -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x0000000d -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0x0000000f -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x00000010 -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x00000011 -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x00000012 -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x00000013 -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x00000015 -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x0000001a -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x0000001b -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x0000001c -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x0000001d -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x0000001e -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x0000001f - -// DB_RENDER_OVERRIDE2 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x00000000 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x00000002 -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000005 -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000006 -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x00000007 -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x00000008 -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x00000009 -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x0000000a -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0x0000000b -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0x0000000c -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0x0000000f -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x00000012 -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x00000015 -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x00000016 -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x00000017 -#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x00000019 - -// DB_EQAA -#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x00000000 -#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x00000004 -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x00000008 -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0x0000000c -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x00000010 -#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x00000011 -#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x00000012 -#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x00000013 -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x00000014 -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x00000015 -#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x00000018 -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x0000001b - -// DB_SHADER_CONTROL -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x00000000 -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x00000001 -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x00000002 -#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x00000004 -#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x00000006 -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x00000007 -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x00000008 -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x00000009 -#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0x0000000a -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0x0000000b -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0x0000000c -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x0000000d -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0x0000000f -#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x00000010 -#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x00000011 -#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x00000014 - -// DB_DEPTH_BOUNDS_MIN -#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x00000000 - -// DB_DEPTH_BOUNDS_MAX -#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x00000000 - -// DB_STENCIL_CLEAR -#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x00000000 - -// DB_DEPTH_CLEAR -#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 - -// DB_HTILE_DATA_BASE -#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x00000000 - -// DB_HTILE_DATA_BASE_HI -#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x00000000 - -// DB_HTILE_SURFACE -#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x00000001 -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x00000002 -#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x00000003 -#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x00000004 -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0x0000000a -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x00000010 -#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x00000012 -#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x00000013 - -// DB_PRELOAD_CONTROL -#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x00000000 -#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x00000008 -#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x00000010 -#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x00000018 - -// DB_STENCILREFMASK -#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x00000000 -#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 -#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 -#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x00000018 - -// DB_STENCILREFMASK_BF -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x00000000 -#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x00000018 - -// DB_SRESULTS_COMPARE_STATE0 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x00000000 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x00000004 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0x0000000c -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x00000018 - -// DB_SRESULTS_COMPARE_STATE1 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x00000000 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x00000004 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0x0000000c -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x00000018 - -// DB_DEPTH_CONTROL -#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x00000000 -#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x00000001 -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x00000003 -#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x00000004 -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 -#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x00000008 -#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x00000014 -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x0000001e -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x0000001f - -// DB_STENCIL_CONTROL -#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x00000000 -#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x00000004 -#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x00000008 -#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0x0000000c -#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x00000010 -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x00000014 - -// DB_ALPHA_TO_MASK -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000000 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000008 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000000a -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000000c -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000000e -#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x00000010 - -// DB_ZPASS_COUNT_LOW -#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x00000000 - -// DB_ZPASS_COUNT_HI -#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT0_LOW -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT0_HI -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT1_LOW -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT1_HI -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT2_LOW -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT2_HI -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT3_LOW -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x00000000 - -// DB_OCCLUSION_COUNT3_HI -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x00000000 - -// DB_PERFCOUNTER0_LO -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// DB_PERFCOUNTER1_LO -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// DB_PERFCOUNTER2_LO -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// DB_PERFCOUNTER3_LO -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// DB_PERFCOUNTER0_HI -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// DB_PERFCOUNTER1_HI -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// DB_PERFCOUNTER2_HI -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// DB_PERFCOUNTER3_HI -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// DB_PERFCOUNTER0_SELECT -#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// DB_PERFCOUNTER1_SELECT -#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// DB_PERFCOUNTER2_SELECT -#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// DB_PERFCOUNTER3_SELECT -#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// DB_PERFCOUNTER0_SELECT1 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// DB_PERFCOUNTER1_SELECT1 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// DB_CGTT_CLK_CTRL_0 -#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x00000000 -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x0000000c -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// PA_CL_ENHANCE -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 -#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001 -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x00000003 -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x00000004 -#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x00000005 -#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x00000006 -#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x00000007 -#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x00000008 -#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x00000009 -#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0x0000000b -#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0x0000000c -#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0x0000000e -#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c -#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d -#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e -#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f - -// PA_CL_RESET_DEBUG -#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x00000000 - -// PA_SIDEBAND_REQUEST_DELAYS -#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x00000000 -#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x00000010 - -// PA_UTCL1_CNTL1 -#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x00000000 -#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x00000001 -#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x00000002 -#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x00000003 -#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x00000005 -#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x00000007 -#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x00000010 -#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x00000011 -#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x00000012 -#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x00000013 -#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x00000017 -#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x00000018 -#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x00000019 -#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x0000001a -#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x0000001b -#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x0000001c -#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x0000001e - -// PA_UTCL1_CNTL2 -#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x00000000 -#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x00000008 -#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x00000009 -#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0x0000000a -#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0x0000000b -#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0x0000000c -#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0x0000000d -#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0x0000000e -#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0x0000000f -#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x00000010 -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x00000012 -#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x00000013 -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x00000014 -#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x00000015 -#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x00000019 -#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x0000001a -#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x0000001b - -// PA_SC_ENHANCE -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x00000000 -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x00000001 -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x00000002 -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x00000003 -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x00000004 -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x00000005 -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x00000006 -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x00000007 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x00000008 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x00000009 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0x0000000a -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0x0000000b -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0x0000000c -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0x0000000d -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x0000000e -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x0000000f -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x00000010 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x00000011 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x00000012 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000013 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000014 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x00000015 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x00000016 -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x00000017 -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x00000018 -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x00000019 -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x0000001a -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x0000001b -#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x0000001c -#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x0000001d - -// PA_SC_ENHANCE_1 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x00000000 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x00000001 -#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x00000003 -#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x00000004 -#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x00000005 -#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x00000006 -#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x00000007 -#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x00000008 -#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x00000009 -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0x0000000a -#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0x0000000b -#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0x0000000c -#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0x0000000d -#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0x0000000e -#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0x0000000f -#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x00000010 -#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x00000011 -#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x00000012 -#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x00000013 -#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x00000014 -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x00000015 -#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x00000016 -#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x00000017 - -// PA_SC_DSM_CNTL -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x00000000 -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x00000001 - -// PA_SC_TILE_STEERING_CREST_OVERRIDE -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x00000000 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x00000001 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x00000005 - -// PA_SC_FIFO_SIZE -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x00000000 -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x00000006 -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0x0000000f -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x00000015 - -// PA_SC_IF_FIFO_SIZE -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x00000000 -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x00000006 -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0x0000000c -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x00000012 - -// PA_SC_PKR_WAVE_TABLE_CNTL -#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x00000000 - -// PA_SC_FORCE_EOV_MAX_CNTS -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x00000000 -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x00000010 - -// PA_SC_BINNER_EVENT_CNTL_0 -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x00000000 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x00000002 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x00000004 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x00000006 -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x00000008 -#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0x0000000a -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0x0000000c -#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0x0000000e -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x00000010 -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x00000012 -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x00000014 -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x00000016 -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x00000018 -#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x0000001a -#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x0000001c -#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x0000001e - -// PA_SC_BINNER_EVENT_CNTL_1 -#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x00000000 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x00000002 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x00000004 -#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x00000006 -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x00000008 -#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0x0000000a -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0x0000000c -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0x0000000e -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x00000010 -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x00000012 -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x00000014 -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x00000016 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x00000018 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x0000001a -#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x0000001c -#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x0000001e - -// PA_SC_BINNER_EVENT_CNTL_2 -#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x00000000 -#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x00000002 -#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x00000004 -#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x00000006 -#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x00000008 -#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0x0000000a -#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0x0000000c -#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0x0000000e -#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x00000010 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x00000012 -#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x00000014 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x00000016 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x00000018 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x0000001a -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x0000001c -#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x0000001e - -// PA_SC_BINNER_EVENT_CNTL_3 -#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x00000000 -#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x00000002 -#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x00000004 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x00000006 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x00000008 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0x0000000a -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0x0000000c -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0x0000000e -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x00000010 -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x00000012 -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x00000014 -#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x00000016 -#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x00000018 -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x0000001a -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x0000001c -#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x0000001e - -// PA_SC_BINNER_TIMEOUT_COUNTER -#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x00000000 - -// PA_SC_BINNER_PERF_CNTL_0 -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x00000000 -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0000000a -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x00000014 -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x00000017 - -// PA_SC_BINNER_PERF_CNTL_1 -#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x00000000 -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x00000005 -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0x0000000a - -// PA_SC_BINNER_PERF_CNTL_2 -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x00000000 -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0x0000000b - -// PA_SC_BINNER_PERF_CNTL_3 -#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x00000000 - -// PA_SC_P3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x00000000 - -// PA_SC_HP3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x00000000 - -// PA_SC_TRAP_SCREEN_HV_LOCK -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x00000000 - -// PA_CL_CNTL_STATUS -#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x00000000 -#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x00000001 -#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x00000002 - -// PA_SU_CNTL_STATUS -#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f - -// PA_SC_FIFO_DEPTH_CNTL -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x00000000 - -// PA_SU_DEBUG_CNTL -#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 - -// PA_SU_DEBUG_DATA -#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// PA_SC_DEBUG_CNTL -#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 -#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS__SHIFT 0x00000008 - -// PA_SC_DEBUG_DATA -#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_1 -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_2 -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_3 -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_4 -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_5 -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_6 -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_7 -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_8 -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_9 -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_10 -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_11 -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_12 -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_13 -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_14 -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XSCALE_15 -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_1 -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_2 -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_3 -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_4 -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_5 -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_6 -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_7 -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_8 -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_9 -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_10 -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_11 -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_12 -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_13 -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_14 -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_XOFFSET_15 -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_1 -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_2 -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_3 -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_4 -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_5 -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_6 -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_7 -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_8 -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_9 -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_10 -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_11 -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_12 -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_13 -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_14 -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YSCALE_15 -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_1 -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_2 -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_3 -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_4 -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_5 -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_6 -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_7 -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_8 -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_9 -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_10 -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_11 -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_12 -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_13 -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_14 -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_YOFFSET_15 -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_1 -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_2 -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_3 -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_4 -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_5 -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_6 -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_7 -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_8 -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_9 -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_10 -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_11 -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_12 -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_13 -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_14 -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZSCALE_15 -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_1 -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_2 -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_3 -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_4 -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_5 -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_6 -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_7 -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_8 -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_9 -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_10 -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_11 -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_12 -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_13 -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_14 -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VPORT_ZOFFSET_15 -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x00000000 - -// PA_CL_VTE_CNTL -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 -#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 -#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 -#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b - -// PA_CL_VS_OUT_CNTL -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x00000000 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x00000001 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x00000002 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x00000003 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x00000004 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x00000005 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x00000006 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x00000007 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x00000008 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x00000009 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0x0000000a -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0x0000000b -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0x0000000c -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0x0000000d -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0x0000000e -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0x0000000f -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x00000010 -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x00000011 -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x00000012 -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x00000013 -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x00000014 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x00000015 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x00000016 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x00000017 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x00000018 -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x00000019 -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x0000001a -#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x0000001b - -// PA_CL_NANINF_CNTL -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x00000000 -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x00000001 -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x00000002 -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x00000003 -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x00000004 -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x00000005 -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x00000006 -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x00000007 -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x00000008 -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x00000009 -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0x0000000a -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0x0000000b -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0x0000000c -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0x0000000d -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0x0000000e -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x00000014 - -// PA_CL_CLIP_CNTL -#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000 -#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x00000001 -#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x00000002 -#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x00000003 -#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x00000004 -#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x00000005 -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0x0000000d -#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0x0000000e -#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x00000011 -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 -#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x00000016 -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x00000018 -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x00000019 -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x0000001a -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x0000001b - -// PA_CL_GB_VERT_CLIP_ADJ -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_GB_VERT_DISC_ADJ -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_GB_HORZ_CLIP_ADJ -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_GB_HORZ_DISC_ADJ -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_0_X -#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_0_Y -#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_0_Z -#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_0_W -#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_1_X -#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_1_Y -#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_1_Z -#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_1_W -#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_2_X -#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_2_Y -#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_2_Z -#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_2_W -#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_3_X -#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_3_Y -#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_3_Z -#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_3_W -#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_4_X -#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_4_Y -#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_4_Z -#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_4_W -#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_5_X -#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_5_Y -#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_5_Z -#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_UCP_5_W -#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_POINT_X_RAD -#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_POINT_Y_RAD -#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_POINT_SIZE -#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x00000000 - -// PA_CL_POINT_CULL_RAD -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x00000000 - -// PA_SU_VTX_CNTL -#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 -#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 -#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 - -// PA_SU_POINT_SIZE -#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 -#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 - -// PA_SU_POINT_MINMAX -#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 -#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 - -// PA_SU_LINE_CNTL -#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 - -// PA_SU_LINE_STIPPLE_CNTL -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x00000000 -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x00000002 -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x00000003 -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x00000004 - -// PA_SU_LINE_STIPPLE_SCALE -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x00000000 - -// PA_SU_PRIM_FILTER_CNTL -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x00000000 -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x00000001 -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x00000002 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x00000003 -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x00000004 -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x00000005 -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x00000006 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x00000007 -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x00000008 -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x0000001e -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x0000001f - -// PA_SU_SMALL_PRIM_FILTER_CNTL -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x00000000 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x00000001 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x00000002 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x00000003 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x00000004 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x00000005 - -// PA_CL_OBJPRIM_ID_CNTL -#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x00000000 -#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x00000001 -#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x00000002 - -// PA_CL_NGG_CNTL -#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x00000000 -#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x00000001 - -// PA_SU_OVER_RASTERIZATION_CNTL -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x00000000 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x00000001 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x00000002 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x00000003 -#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x00000004 - -// PA_SU_SC_MODE_CNTL -#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 -#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 -#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 -#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 -#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x00000016 -#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x00000017 - -// PA_SU_POLY_OFFSET_DB_FMT_CNTL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x00000000 -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x00000008 - -// PA_SU_POLY_OFFSET_CLAMP -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x00000000 - -// PA_SU_POLY_OFFSET_FRONT_SCALE -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 - -// PA_SU_POLY_OFFSET_FRONT_OFFSET -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 - -// PA_SU_POLY_OFFSET_BACK_SCALE -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 - -// PA_SU_POLY_OFFSET_BACK_OFFSET -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 - -// PA_SU_HARDWARE_SCREEN_OFFSET -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x00000000 -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x00000010 - -// PA_SC_AA_CONFIG -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x00000004 -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x00000014 -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x00000018 -#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x0000001a - -// PA_SC_AA_MASK_X0Y0_X1Y0 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x00000000 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x00000010 - -// PA_SC_AA_MASK_X0Y1_X1Y1 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x00000000 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x00000010 - -// PA_SC_SHADER_CONTROL -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x00000000 -#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x00000002 -#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x00000003 - -// PA_SC_BINNER_CNTL_0 -#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x00000000 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x00000002 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x00000003 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x00000004 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x00000007 -#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0x0000000a -#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0x0000000d -#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x00000012 -#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x00000013 -#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x0000001b - -// PA_SC_BINNER_CNTL_1 -#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x00000000 -#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x00000010 - -// PA_SC_CONSERVATIVE_RASTERIZATION_CNTL -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x00000000 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x00000001 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x00000005 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x00000006 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0x0000000a -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0x0000000b -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0x0000000c -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0x0000000d -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0x0000000e -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT \ - 0x0000000f -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x00000010 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x00000012 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x00000013 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x00000014 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x00000015 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x00000016 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x00000017 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x00000018 - -// PA_SC_NGG_MODE_CNTL -#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x00000000 - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x0000001c - -// PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x00000000 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x00000004 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x00000008 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0x0000000c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x00000010 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x00000014 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x00000018 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x0000001c - -// PA_SC_CENTROID_PRIORITY_0 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x00000000 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x00000004 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x00000008 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0x0000000c -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x00000010 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x00000014 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x00000018 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x0000001c - -// PA_SC_CENTROID_PRIORITY_1 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x00000000 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x00000004 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x00000008 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0x0000000c -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x00000010 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x00000014 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x00000018 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x0000001c - -// PA_SC_CLIPRECT_0_TL -#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_0_BR -#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_1_TL -#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_1_BR -#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_2_TL -#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_2_BR -#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_3_TL -#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_3_BR -#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_CLIPRECT_RULE -#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x00000000 - -// PA_SC_EDGERULE -#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x00000000 -#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x00000004 -#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x00000008 -#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0x0000000c -#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x00000012 -#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x00000018 -#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x0000001c - -// PA_SC_LINE_CNTL -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 -#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0x0000000b -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0x0000000c - -// PA_SC_LINE_STIPPLE -#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d - -// PA_SC_MODE_CNTL_0 -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x00000000 -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x00000001 -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x00000002 -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x00000003 -#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x00000004 -#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x00000005 -#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x00000006 - -// PA_SC_MODE_CNTL_1 -#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x00000000 -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x00000001 -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x00000002 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x00000003 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x00000004 -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x00000007 -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x00000008 -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x00000009 -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0x0000000a -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0x0000000b -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0x0000000c -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0x0000000d -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0x0000000e -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0x0000000f -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x00000010 -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x00000011 -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x00000012 -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x00000013 -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x00000014 -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x00000018 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x00000019 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x0000001a -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x0000001b -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x0000001c - -// PA_SC_RASTER_CONFIG -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x00000000 -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x00000002 -#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x00000004 -#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x00000006 -#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x00000007 -#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x00000008 -#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0x0000000a -#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0x0000000c -#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0x0000000e -#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x00000010 -#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x00000012 -#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x00000014 -#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x00000018 -#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x0000001a -#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x0000001d - -// PA_SC_RASTER_CONFIG_1 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x00000000 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x00000002 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x00000005 - -// PA_SC_SCREEN_EXTENT_CONTROL -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x00000000 -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x00000002 - -// PA_SC_TILE_STEERING_OVERRIDE -#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x00000000 -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x00000001 -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x00000005 -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x00000008 - -// PA_SC_RIGHT_VERT_GRID -#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x00000000 -#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x00000008 -#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x00000010 -#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x00000018 - -// PA_SC_LEFT_VERT_GRID -#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x00000000 -#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x00000008 -#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x00000010 -#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x00000018 - -// PA_SC_HORIZ_GRID -#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x00000000 -#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x00000008 -#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x00000010 -#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x00000018 - -// PA_SC_FOV_WINDOW_LR -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x00000000 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x00000008 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x00000010 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x00000018 - -// PA_SC_FOV_WINDOW_TB -#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x00000000 -#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x00000008 - -// PA_SC_GENERIC_SCISSOR_TL -#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_GENERIC_SCISSOR_BR -#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_SCREEN_SCISSOR_TL -#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 - -// PA_SC_SCREEN_SCISSOR_BR -#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_WINDOW_OFFSET -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 - -// PA_SC_WINDOW_SCISSOR_TL -#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_WINDOW_SCISSOR_BR -#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_0_TL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_1_TL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_2_TL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_3_TL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_4_TL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_5_TL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_6_TL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_7_TL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_8_TL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_9_TL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_10_TL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_11_TL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_12_TL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_13_TL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_14_TL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_15_TL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x00000010 -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f - -// PA_SC_VPORT_SCISSOR_0_BR -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_1_BR -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_2_BR -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_3_BR -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_4_BR -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_5_BR -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_6_BR -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_7_BR -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_8_BR -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_9_BR -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_10_BR -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_11_BR -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_12_BR -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_13_BR -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_14_BR -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_SCISSOR_15_BR -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x00000000 -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x00000010 - -// PA_SC_VPORT_ZMIN_0 -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_1 -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_2 -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_3 -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_4 -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_5 -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_6 -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_7 -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_8 -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_9 -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_10 -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_11 -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_12 -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_13 -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_14 -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMIN_15 -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_0 -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_1 -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_2 -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_3 -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_4 -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_5 -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_6 -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_7 -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_8 -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_9 -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_10 -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_11 -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_12 -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_13 -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_14 -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SC_VPORT_ZMAX_15 -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x00000000 - -// PA_SU_LINE_STIPPLE_VALUE -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x00000000 - -// PA_SC_LINE_STIPPLE_STATE -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 - -// PA_SC_SCREEN_EXTENT_MIN_0 -#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x00000000 -#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x00000010 - -// PA_SC_SCREEN_EXTENT_MAX_0 -#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x00000000 -#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x00000010 - -// PA_SC_SCREEN_EXTENT_MIN_1 -#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x00000000 -#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x00000010 - -// PA_SC_SCREEN_EXTENT_MAX_1 -#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x00000000 -#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x00000010 - -// PA_SC_P3D_TRAP_SCREEN_HV_EN -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x00000000 -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x00000001 - -// PA_SC_P3D_TRAP_SCREEN_H -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x00000000 - -// PA_SC_P3D_TRAP_SCREEN_V -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x00000000 - -// PA_SC_P3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x00000000 - -// PA_SC_P3D_TRAP_SCREEN_COUNT -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x00000000 - -// PA_SC_HP3D_TRAP_SCREEN_HV_EN -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x00000000 -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x00000001 - -// PA_SC_HP3D_TRAP_SCREEN_H -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x00000000 - -// PA_SC_HP3D_TRAP_SCREEN_V -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x00000000 - -// PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x00000000 - -// PA_SC_HP3D_TRAP_SCREEN_COUNT -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x00000000 - -// PA_SC_TRAP_SCREEN_HV_EN -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x00000000 -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x00000001 - -// PA_SC_TRAP_SCREEN_H -#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x00000000 - -// PA_SC_TRAP_SCREEN_V -#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x00000000 - -// PA_SC_TRAP_SCREEN_OCCURRENCE -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x00000000 - -// PA_SC_TRAP_SCREEN_COUNT -#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER0_LO -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER0_HI -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER1_LO -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER1_HI -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER2_LO -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER2_HI -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER3_LO -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER3_HI -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER0_LO -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER0_HI -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER1_LO -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER1_HI -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER2_LO -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER2_HI -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER3_LO -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER3_HI -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER4_LO -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER4_HI -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER5_LO -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER5_HI -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER6_LO -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER6_HI -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER7_LO -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER7_HI -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// PA_SU_PERFCOUNTER0_SELECT -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// PA_SU_PERFCOUNTER0_SELECT1 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a - -// PA_SU_PERFCOUNTER1_SELECT -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// PA_SU_PERFCOUNTER1_SELECT1 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a - -// PA_SU_PERFCOUNTER2_SELECT -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// PA_SU_PERFCOUNTER3_SELECT -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// PA_SC_PERFCOUNTER0_SELECT -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 - -// PA_SC_PERFCOUNTER0_SELECT1 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a - -// PA_SC_PERFCOUNTER1_SELECT -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER2_SELECT -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER3_SELECT -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER4_SELECT -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER5_SELECT -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER6_SELECT -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 - -// PA_SC_PERFCOUNTER7_SELECT -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 - -// CGTT_PA_CLK_CTRL -#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT 0x00000017 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f - -// CGTT_SC_CLK_CTRL0 -#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x00000010 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x00000011 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x00000012 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x00000013 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x00000014 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x00000015 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x00000016 -#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x00000017 -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x00000018 -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x00000019 -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001a -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001b -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001c -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001d -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001e -#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x0000001f - -// CGTT_SC_CLK_CTRL1 -#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000 -#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004 -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x00000011 -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x00000012 -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x00000013 -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x00000014 -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x00000015 -#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x00000016 -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x00000019 -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x0000001a -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x0000001b -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x0000001c -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x0000001d -#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x0000001e - -// CLIPPER_DEBUG_REG00 -#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009 -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG01 -#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG02 -#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG03 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG04 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG05 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG06 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG07 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG08 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG09 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG10 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG11 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001 -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002 -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004 -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005 -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG12 -#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016 -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019 -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG13 -#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003 -#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004 -#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005 -#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e -#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f -#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011 -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017 -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG14 -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006 -#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c -#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018 -#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG15 -#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010 -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015 -#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a -#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG16 -#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG17 -#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG18 -#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// CLIPPER_DEBUG_REG19 -#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000 -#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007 -#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008 -#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012 -#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013 -#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014 -#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b -#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c -#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d -#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e -#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f - -// SXIFCCG_DEBUG_REG0 -#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x00000006 -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000009 -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x0000000c -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000010 -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001a -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x0000001c -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e -#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x0000001f - -// SXIFCCG_DEBUG_REG1 -#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x00000007 -#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0x0000000a -#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x0000000f -#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x00000010 -#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x00000016 -#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x00000017 -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x00000018 -#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x0000001c - -// SXIFCCG_DEBUG_REG2 -#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000007 -#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000009 -#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000000f -#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000010 -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000017 -#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x0000001a - -// SXIFCCG_DEBUG_REG3 -#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x00000000 -#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000008 -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0x0000000c -#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0x0000000d -#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x0000000e -#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x00000015 -#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x00000017 -#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x00000018 -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000019 -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x0000001a -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x0000001b -#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x0000001c -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001d -#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x0000001e -#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x0000001f - -// SETUP_DEBUG_REG0 -#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x00000000 -#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000002 -#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000008 -#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000e -#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000f -#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x00000010 -#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x00000012 -#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x00000013 -#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000014 -#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000015 -#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x00000016 -#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x0000001c -#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x0000001d -#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x0000001e -#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x0000001f - -// SETUP_DEBUG_REG1 -#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x00000000 -#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x00000010 - -// SETUP_DEBUG_REG2 -#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x00000000 -#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x00000010 - -// SETUP_DEBUG_REG3 -#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x00000000 -#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x00000010 - -// SETUP_DEBUG_REG4 -#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 -#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000e -#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000f -#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x00000010 -#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000013 -#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000014 -#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000017 -#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000018 -#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x0000001a -#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001d -#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001f - -// SETUP_DEBUG_REG5 -#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 -#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000e -#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x0000001c -#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x0000001e -#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x0000001f - -// PA_SC_DEBUG_REG0 -#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x00000000 -#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x00000002 - -// PA_SC_DEBUG_REG1 -#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x00000000 -#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x00000002 - -// RMI_GENERAL_CNTL -#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x00000000 -#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x00000001 -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x00000011 -#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x00000013 -#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x00000014 -#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x00000015 -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x00000019 -#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x0000001a -#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x0000001b -#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x0000001c -#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x0000001d -#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x0000001e - -// RMI_GENERAL_CNTL1 -#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x00000000 -#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x00000004 -#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x00000006 -#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x00000008 -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x00000009 -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0x0000000a -#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0x0000000b -#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0x0000000c - -// RMI_GENERAL_STATUS -#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x00000000 -#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x00000001 -#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x00000002 -#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x00000003 -#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x00000004 -#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x00000005 -#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x00000006 -#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x00000007 -#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x00000008 -#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x00000009 -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0x0000000a -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0x0000000b -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0x0000000c -#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0x0000000d -#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0x0000000e -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0x0000000f -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x00000010 -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x00000011 -#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x00000012 -#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x00000013 -#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x00000014 -#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x00000015 -#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x0000001d -#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x0000001e -#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x0000001f - -// RMI_SUBBLOCK_STATUS0 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x00000000 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x00000007 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x00000008 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x00000009 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x00000010 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x00000011 -#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x00000012 - -// RMI_SUBBLOCK_STATUS1 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x00000000 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0x0000000a -#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x00000014 - -// RMI_SUBBLOCK_STATUS2 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x00000000 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x00000009 - -// RMI_SUBBLOCK_STATUS3 -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x00000000 -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0x0000000a - -// RMI_XBAR_CONFIG -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x00000000 -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x00000002 -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x00000006 -#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x00000007 -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x00000008 -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0x0000000c -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0x0000000d -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0x0000000e - -// RMI_PROBE_POP_LOGIC_CNTL -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x00000000 -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x00000007 -#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x00000008 -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0x0000000a -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x00000011 - -// RMI_UTC_XNACK_N_MISC_CNTL -#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x00000000 -#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x00000008 -#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0x0000000c -#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0x0000000d - -// RMI_DEMUX_CNTL -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x00000000 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x00000001 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x00000004 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x00000006 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0x0000000e -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x00000010 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x00000011 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x00000014 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x00000016 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x0000001e - -// RMI_UTCL1_CNTL1 -#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x00000000 -#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x00000001 -#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x00000002 -#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x00000003 -#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x00000005 -#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x00000007 -#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x00000010 -#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x00000011 -#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x00000012 -#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x00000013 -#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x00000017 -#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x00000018 -#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x00000019 -#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x0000001a -#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x0000001b -#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x0000001c -#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x0000001e - -// RMI_UTCL1_CNTL2 -#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x00000000 -#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x00000009 -#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0x0000000a -#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0x0000000b -#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0x0000000c -#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0x0000000d -#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0x0000000e -#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0x0000000f -#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x00000010 -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x00000012 -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x00000013 -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x00000014 -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x00000015 -#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x00000019 -#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x0000001a - -// RMI_UTC_UNIT_CONFIG -#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x00000000 - -// RMI_TCIW_FORMATTER0_CNTL -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x00000000 -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x00000001 -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x00000009 -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x00000013 -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x0000001b -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x0000001c -#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x0000001d -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x0000001e -#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x0000001f - -// RMI_TCIW_FORMATTER1_CNTL -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x00000000 -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x00000001 -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x00000009 -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x00000013 -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x0000001b -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x0000001c -#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x0000001d -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x0000001e -#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x0000001f - -// RMI_SCOREBOARD_CNTL -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x00000000 -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x00000001 -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x00000002 -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x00000003 -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x00000004 -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x00000005 -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x00000006 -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x00000007 -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x00000008 -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x00000009 - -// RMI_SCOREBOARD_STATUS0 -#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x00000000 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x00000001 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x00000002 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x00000012 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x00000013 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x00000014 -#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x00000015 - -// RMI_SCOREBOARD_STATUS1 -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x00000000 -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0x0000000c -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0x0000000d -#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0x0000000e -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0x0000000f -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x0000001b -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x0000001c -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x0000001d -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x0000001e - -// RMI_SCOREBOARD_STATUS2 -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x00000000 -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0x0000000c -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0x0000000d -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x00000019 -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x0000001a -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x0000001b -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x0000001c -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x0000001d -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x0000001e -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x0000001f - -// RMI_XBAR_ARBITER_CONFIG -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x00000000 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x00000002 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x00000003 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x00000004 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x00000006 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x00000008 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x00000010 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x00000012 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x00000013 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x00000014 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x00000016 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x00000018 - -// RMI_XBAR_ARBITER_CONFIG_1 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x00000000 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x00000008 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x00000010 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x00000018 - -// RMI_CLOCK_CNTRL -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x00000000 -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x00000005 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0x0000000a -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0x0000000f -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x00000014 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x00000019 - -// RMI_UTCL1_STATUS -#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x00000000 -#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x00000001 -#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x00000002 - -// RMI_DEBUG0 -#define RMI_DEBUG0__RTS_RTR_DEBUG_MUX_SEL__SHIFT 0x00000000 -#define RMI_DEBUG0__XBAR_ARB_DEBUG_MUX_SEL__SHIFT 0x00000005 -#define RMI_DEBUG0__DEMUX_ARB_DEBUG_MUX_SEL__SHIFT 0x00000007 -#define RMI_DEBUG0__DISABLE_MUX_SEL__SHIFT 0x00000009 -#define RMI_DEBUG0__DISABLE_MUX_SEL_UPDATE__SHIFT 0x0000000e -#define RMI_DEBUG0__DISABLE_STATUS_MUX_SEL__SHIFT 0x0000000f -#define RMI_DEBUG0__STALL_DEBUG_MUX_SEL__SHIFT 0x00000014 -#define RMI_DEBUG0__UTCL1_INFLIGHT_WATERMARK__SHIFT 0x00000019 - -// RMI_DEBUG1 -#define RMI_DEBUG1__REQ_BYPASS_DETECTION_DEBUG_MUX_SEL__SHIFT 0x00000000 -#define RMI_DEBUG1__CONSUMER_FIFO_CNT_MUX_SEL__SHIFT 0x00000004 - -// RMI_DEBUG2 -#define RMI_DEBUG2__DEMUX_ARB_DEBUG_MUX_STATE__SHIFT 0x00000000 -#define RMI_DEBUG2__DISABLE_STATUS_MUX_STATE__SHIFT 0x00000004 -#define RMI_DEBUG2__RTS_RTR_DEBUG_MUX_STATE__SHIFT 0x00000005 -#define RMI_DEBUG2__CONSUMER_FIFO_DEBIT_CNT__SHIFT 0x00000007 -#define RMI_DEBUG2__CONSUMER_FIFO_FREE_SPACE_CNT__SHIFT 0x0000000d - -// RMI_DEBUG3 -#define RMI_DEBUG3__XBAR_ARB_DEBUG_MUX_STATE__SHIFT 0x00000000 -#define RMI_DEBUG3__UTC_IN_STALL_SOURCE__SHIFT 0x00000004 -#define RMI_DEBUG3__UTC_OUT_STALL_SOURCE__SHIFT 0x00000007 -#define RMI_DEBUG3__TCIW0_PRODUCER_CREDIT_CNT__SHIFT 0x0000000a -#define RMI_DEBUG3__TCIW1_PRODUCER_CREDIT_CNT__SHIFT 0x00000010 -#define RMI_DEBUG3__STALL_DEBUG_MUX_STATE__SHIFT 0x00000016 -#define RMI_DEBUG3__REQ_BYPASS_DETECTION_DEBUG_MUX_STATE__SHIFT 0x0000001a -#define RMI_DEBUG3__UTCL1_INFLIGHT_WATERMARK_HIT_PROBE0__SHIFT 0x0000001d -#define RMI_DEBUG3__UTCL1_INFLIGHT_WATERMARK_HIT_PROBE1__SHIFT 0x0000001e - -// RMI_DEBUG4 -#define RMI_DEBUG4__FORCE_NON_RETRY_XNACK_PER_VMID__SHIFT 0x00000000 -#define RMI_DEBUG4__FORCE_INSTANT_RETRY_PER_VMID__SHIFT 0x00000010 - -// RMI_XNACK_DEBUG -#define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x00000000 - -// RMI_SPARE -#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x00000000 -#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x00000001 -#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x00000002 -#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x00000003 -#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x00000004 -#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x00000005 -#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x00000006 -#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x00000007 -#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x00000008 -#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x00000010 - -// RMI_SPARE_1 -#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x00000000 -#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x00000001 -#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x00000002 -#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x00000003 -#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x00000004 -#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x00000005 -#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x00000006 -#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x00000007 -#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x00000008 -#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x00000010 - -// RMI_SPARE_2 -#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x00000000 -#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x00000001 -#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x00000002 -#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x00000003 -#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x00000004 -#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x00000005 -#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x00000006 -#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x00000007 -#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x00000008 -#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0x0000000c -#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x00000010 -#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x00000018 - -// RMI_PERFCOUNTER0_LO -#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// RMI_PERFCOUNTER1_LO -#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// RMI_PERFCOUNTER2_LO -#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// RMI_PERFCOUNTER3_LO -#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 - -// RMI_PERFCOUNTER0_HI -#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// RMI_PERFCOUNTER1_HI -#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// RMI_PERFCOUNTER2_HI -#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// RMI_PERFCOUNTER3_HI -#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 - -// RMI_PERFCOUNTER0_SELECT -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c - -// RMI_PERFCOUNTER0_SELECT1 -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// RMI_PERFCOUNTER1_SELECT -#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 -#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c - -// RMI_PERFCOUNTER2_SELECT -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a -#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018 -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c - -// RMI_PERFCOUNTER2_SELECT1 -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x00000000 -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0x0000000a -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x00000018 -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x0000001c - -// RMI_PERFCOUNTER3_SELECT -#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 -#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c - -// RMI_PERF_COUNTER_CNTL -#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x00000000 -#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x00000002 -#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x00000004 -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x00000006 -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x00000008 -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0x0000000a -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0x0000000e -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x00000013 -#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x00000019 -#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x0000001a - -// RMI_CGTT_SCLK_CTRL -#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x00000010 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x00000011 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x00000012 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x00000013 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x00000014 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x00000015 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x00000016 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x00000017 -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f - -// port_a_addr -#define port_a_addr__Index__SHIFT 0x00000000 -#define port_a_addr__Reserved__SHIFT 0x00000008 -#define port_a_addr__ReadEnable__SHIFT 0x0000001f - -// port_a_data_lo -#define port_a_data_lo__Data__SHIFT 0x00000000 - -// port_a_data_hi -#define port_a_data_hi__Data__SHIFT 0x00000000 - -// port_b_addr -#define port_b_addr__Index__SHIFT 0x00000000 -#define port_b_addr__Reserved__SHIFT 0x00000008 -#define port_b_addr__ReadEnable__SHIFT 0x0000001f - -// port_b_data_lo -#define port_b_data_lo__Data__SHIFT 0x00000000 - -// port_b_data_hi -#define port_b_data_hi__Data__SHIFT 0x00000000 - -// port_c_addr -#define port_c_addr__Index__SHIFT 0x00000000 -#define port_c_addr__Reserved__SHIFT 0x00000008 -#define port_c_addr__ReadEnable__SHIFT 0x0000001f - -// port_c_data_lo -#define port_c_data_lo__Data__SHIFT 0x00000000 - -// port_c_data_hi -#define port_c_data_hi__Data__SHIFT 0x00000000 - -// port_d_addr -#define port_d_addr__Index__SHIFT 0x00000000 -#define port_d_addr__Reserved__SHIFT 0x00000008 -#define port_d_addr__ReadEnable__SHIFT 0x0000001f - -// port_d_data_lo -#define port_d_data_lo__Data__SHIFT 0x00000000 - -// port_d_data_hi -#define port_d_data_hi__Data__SHIFT 0x00000000 - -// DEBUG_BUS_RSMU -#define DEBUG_BUS_RSMU__iSCH_RSMU_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_RSMU__oRSMU_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_RSMU__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_RSMU__oRSMU_BLOCK_FAO__SHIFT 0x00000003 -#define DEBUG_BUS_RSMU__oRSMU_PIPE_BUSY__SHIFT 0x00000004 -#define DEBUG_BUS_RSMU__iRSMU_READ_PENDING__SHIFT 0x00000005 -#define DEBUG_BUS_RSMU__iIGNORE_FAO__SHIFT 0x00000006 -#define DEBUG_BUS_RSMU__RSMU_ISYNC_FAILED__SHIFT 0x00000007 -#define DEBUG_BUS_RSMU__RSMU_FIFO_EMPTY__SHIFT 0x00000008 -#define DEBUG_BUS_RSMU__RSMU_FIFO_FULL__SHIFT 0x00000009 -#define DEBUG_BUS_RSMU__iRSMU_GRBM_REG_SEND__SHIFT 0x0000000a -#define DEBUG_BUS_RSMU__oGRBM_RLC_PWR_STALLED__SHIFT 0x0000000b -#define DEBUG_BUS_RSMU__oGRBM_RLC_NONGFX3D_STALLED__SHIFT 0x0000000c -#define DEBUG_BUS_RSMU__Reserved0__SHIFT 0x0000000d - -// DEBUG_BUS_RLC -#define DEBUG_BUS_RLC__iSCH_RLC_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_RLC__oRLC_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_RLC__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_RLC__oRLC_BLOCK_FAO__SHIFT 0x00000003 -#define DEBUG_BUS_RLC__oRLC_PIPE_BUSY__SHIFT 0x00000004 -#define DEBUG_BUS_RLC__iRLC_READ_PENDING__SHIFT 0x00000005 -#define DEBUG_BUS_RLC__RLC_ISYNC_FAILED__SHIFT 0x00000006 -#define DEBUG_BUS_RLC__RLC_FIFO_EMPTY__SHIFT 0x00000007 -#define DEBUG_BUS_RLC__RLC_FIFO_FULL__SHIFT 0x00000008 -#define DEBUG_BUS_RLC__iRLC_GRBM_REG_SEND__SHIFT 0x00000009 -#define DEBUG_BUS_RLC__Reserved0__SHIFT 0x0000000a - -// DEBUG_BUS_ME0PIPE0_PF -#define DEBUG_BUS_ME0PIPE0_PF__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME0PIPE0_PF__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME0PIPE0_PF__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME0PIPE0_PF__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME0PIPE0_PF__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME0PIPE0_PF__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME0PIPE0_PF__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME0PIPE0_PF__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME0PIPE0_PF__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME0PIPE0_PF__oPIPE_AVAIL_SPACE__SHIFT 0x00000009 -#define DEBUG_BUS_ME0PIPE0_PF__Reserved0__SHIFT 0x0000000d - -// DEBUG_BUS_ME0PIPE0_CF -#define DEBUG_BUS_ME0PIPE0_CF__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME0PIPE0_CF__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME0PIPE0_CF__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME0PIPE0_CF__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME0PIPE0_CF__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME0PIPE0_CF__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME0PIPE0_CF__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME0PIPE0_CF__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME0PIPE0_CF__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME0PIPE0_CF__oPIPE_AVAIL_SPACE__SHIFT 0x00000009 -#define DEBUG_BUS_ME0PIPE0_CF__Reserved0__SHIFT 0x0000000d - -// DEBUG_BUS_ME0PIPE1_PF -#define DEBUG_BUS_ME0PIPE1_PF__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME0PIPE1_PF__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME0PIPE1_PF__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME0PIPE1_PF__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME0PIPE1_PF__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME0PIPE1_PF__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME0PIPE1_PF__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME0PIPE1_PF__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME0PIPE1_PF__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME0PIPE1_PF__oPIPE_AVAIL_SPACE__SHIFT 0x00000009 -#define DEBUG_BUS_ME0PIPE1_PF__Reserved0__SHIFT 0x0000000d - -// DEBUG_BUS_ME0PIPE1_CF -#define DEBUG_BUS_ME0PIPE1_CF__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME0PIPE1_CF__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME0PIPE1_CF__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME0PIPE1_CF__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME0PIPE1_CF__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME0PIPE1_CF__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME0PIPE1_CF__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME0PIPE1_CF__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME0PIPE1_CF__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME0PIPE1_CF__oPIPE_AVAIL_SPACE__SHIFT 0x00000009 -#define DEBUG_BUS_ME0PIPE1_CF__Reserved0__SHIFT 0x0000000d - -// DEBUG_BUS_ME1PIPE0 -#define DEBUG_BUS_ME1PIPE0__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME1PIPE0__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME1PIPE0__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME1PIPE0__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME1PIPE0__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME1PIPE0__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME1PIPE0__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME1PIPE0__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME1PIPE0__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME1PIPE0__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_ME1PIPE1 -#define DEBUG_BUS_ME1PIPE1__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME1PIPE1__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME1PIPE1__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME1PIPE1__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME1PIPE1__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME1PIPE1__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME1PIPE1__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME1PIPE1__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME1PIPE1__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME1PIPE1__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_ME1PIPE2 -#define DEBUG_BUS_ME1PIPE2__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME1PIPE2__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME1PIPE2__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME1PIPE2__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME1PIPE2__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME1PIPE2__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME1PIPE2__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME1PIPE2__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME1PIPE2__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME1PIPE2__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_ME1PIPE3 -#define DEBUG_BUS_ME1PIPE3__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME1PIPE3__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME1PIPE3__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME1PIPE3__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME1PIPE3__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME1PIPE3__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME1PIPE3__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME1PIPE3__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME1PIPE3__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME1PIPE3__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_ME2PIPE0 -#define DEBUG_BUS_ME2PIPE0__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME2PIPE0__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME2PIPE0__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME2PIPE0__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME2PIPE0__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME2PIPE0__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME2PIPE0__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME2PIPE0__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME2PIPE0__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME2PIPE0__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_ME2PIPE1 -#define DEBUG_BUS_ME2PIPE1__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME2PIPE1__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME2PIPE1__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME2PIPE1__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME2PIPE1__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME2PIPE1__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME2PIPE1__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME2PIPE1__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME2PIPE1__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME2PIPE1__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_ME2PIPE2 -#define DEBUG_BUS_ME2PIPE2__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME2PIPE2__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME2PIPE2__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME2PIPE2__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME2PIPE2__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME2PIPE2__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME2PIPE2__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME2PIPE2__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME2PIPE2__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME2PIPE2__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_ME2PIPE3 -#define DEBUG_BUS_ME2PIPE3__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_ME2PIPE3__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_ME2PIPE3__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_ME2PIPE3__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_ME2PIPE3__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_ME2PIPE3__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_ME2PIPE3__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_ME2PIPE3__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_ME2PIPE3__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_ME2PIPE3__Reserved0__SHIFT 0x00000009 - -// DEBUG_BUS_GDS_DMA -#define DEBUG_BUS_GDS_DMA__iSCH_PIPE_RTR__SHIFT 0x00000000 -#define DEBUG_BUS_GDS_DMA__oPIPE_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_GDS_DMA__iOTHER_BLOCK_FAO__SHIFT 0x00000002 -#define DEBUG_BUS_GDS_DMA__oPIPE_BUSY__SHIFT 0x00000003 -#define DEBUG_BUS_GDS_DMA__iPIPE_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_GDS_DMA__PIPE_ISYNC_FAILED__SHIFT 0x00000005 -#define DEBUG_BUS_GDS_DMA__PIPE_FIFO_EMPTY__SHIFT 0x00000006 -#define DEBUG_BUS_GDS_DMA__PIPE_FIFO_FULL__SHIFT 0x00000007 -#define DEBUG_BUS_GDS_DMA__iCPG_GRBM_REG_SEND__SHIFT 0x00000008 -#define DEBUG_BUS_GDS_DMA__oPIPE_AVAIL_SPACE__SHIFT 0x00000009 -#define DEBUG_BUS_GDS_DMA__Reserved0__SHIFT 0x0000000d - -// DEBUG_BUS_SCH0 -#define DEBUG_BUS_SCH0__oSCH_SEND_SYSTEM__SHIFT 0x00000000 -#define DEBUG_BUS_SCH0__oSCH_SEND_GRAPHICS_TARG_PWR_MASKED__SHIFT 0x00000001 -#define DEBUG_BUS_SCH0__oSCH_SEND_GRAPHICS_TARG__SHIFT 0x00000004 -#define DEBUG_BUS_SCH0__iPWR_REQUEST_HALT_GFX_TARG__SHIFT 0x00000007 -#define DEBUG_BUS_SCH0__iPWR_REQUEST_HALT_TARG__SHIFT 0x00000008 -#define DEBUG_BUS_SCH0__oRBB_GDS_DMA_REQUEST__SHIFT 0x00000009 -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE3_REQUEST__SHIFT 0x0000000a -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE2_REQUEST__SHIFT 0x0000000b -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE1_REQUEST__SHIFT 0x0000000c -#define DEBUG_BUS_SCH0__oRBB_ME2PIPE0_REQUEST__SHIFT 0x0000000d -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE3_REQUEST__SHIFT 0x0000000e -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE2_REQUEST__SHIFT 0x0000000f -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE1_REQUEST__SHIFT 0x00000010 -#define DEBUG_BUS_SCH0__oRBB_ME1PIPE0_REQUEST__SHIFT 0x00000011 -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE1_CF_REQUEST__SHIFT 0x00000012 -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE1_PF_REQUEST__SHIFT 0x00000013 -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE0_CF_REQUEST__SHIFT 0x00000014 -#define DEBUG_BUS_SCH0__oRBB_ME0PIPE0_PF_REQUEST__SHIFT 0x00000015 -#define DEBUG_BUS_SCH0__oRBB_RLC_REQUEST__SHIFT 0x00000016 -#define DEBUG_BUS_SCH0__oRBB_RSMU_REQUEST__SHIFT 0x00000017 -#define DEBUG_BUS_SCH0__Reserved0__SHIFT 0x00000018 - -// DEBUG_BUS_SCH1 -#define DEBUG_BUS_SCH1__oGDS_DMA_READ_PENDING__SHIFT 0x00000000 -#define DEBUG_BUS_SCH1__oME2PIPE3_READ_PENDING__SHIFT 0x00000001 -#define DEBUG_BUS_SCH1__oME2PIPE2_READ_PENDING__SHIFT 0x00000002 -#define DEBUG_BUS_SCH1__oME2PIPE1_READ_PENDING__SHIFT 0x00000003 -#define DEBUG_BUS_SCH1__oME2PIPE0_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_SCH1__oME1PIPE3_READ_PENDING__SHIFT 0x00000005 -#define DEBUG_BUS_SCH1__oME1PIPE2_READ_PENDING__SHIFT 0x00000006 -#define DEBUG_BUS_SCH1__oME1PIPE1_READ_PENDING__SHIFT 0x00000007 -#define DEBUG_BUS_SCH1__oME1PIPE0_READ_PENDING__SHIFT 0x00000008 -#define DEBUG_BUS_SCH1__oME0PIPE1_CF_READ_PENDING__SHIFT 0x00000009 -#define DEBUG_BUS_SCH1__oME0PIPE1_PF_READ_PENDING__SHIFT 0x0000000a -#define DEBUG_BUS_SCH1__oME0PIPE0_CF_READ_PENDING__SHIFT 0x0000000b -#define DEBUG_BUS_SCH1__oME0PIPE0_PF_READ_PENDING__SHIFT 0x0000000c -#define DEBUG_BUS_SCH1__oRLC_READ_PENDING__SHIFT 0x0000000d -#define DEBUG_BUS_SCH1__oRSMU_READ_PENDING__SHIFT 0x0000000e -#define DEBUG_BUS_SCH1__GFX_XFER_STARTED__SHIFT 0x0000000f -#define DEBUG_BUS_SCH1__GFX_XFER_PENDING__SHIFT 0x00000010 -#define DEBUG_BUS_SCH1__GFX_CLOCK_DOMAIN_BUSY__SHIFT 0x00000011 -#define DEBUG_BUS_SCH1__SCH_CLKEN__SHIFT 0x00000012 -#define DEBUG_BUS_SCH1__GFX_PREFIX_STAGE_RDY__SHIFT 0x00000013 -#define DEBUG_BUS_SCH1__oRBB_CPF_REQUEST__SHIFT 0x00000014 -#define DEBUG_BUS_SCH1__oCPF_READ_PENDING__SHIFT 0x00000015 -#define DEBUG_BUS_SCH1__oRBB_INTR_REQUEST__SHIFT 0x00000016 -#define DEBUG_BUS_SCH1__Reserved0__SHIFT 0x00000017 - -// DEBUG_BUS_SCH2 -#define DEBUG_BUS_SCH2__oSCH_READ_GDS_DMA__SHIFT 0x00000000 -#define DEBUG_BUS_SCH2__oSCH_READ_CPC__SHIFT 0x00000001 -#define DEBUG_BUS_SCH2__oSCH_READ_CPG__SHIFT 0x00000002 -#define DEBUG_BUS_SCH2__oSCH_READ_RLC__SHIFT 0x00000003 -#define DEBUG_BUS_SCH2__oSCH_READ_RSMU__SHIFT 0x00000004 -#define DEBUG_BUS_SCH2__oSCH_READ_COMPLETE__SHIFT 0x00000005 -#define DEBUG_BUS_SCH2__oSCH_READ_PIPEID__SHIFT 0x00000006 -#define DEBUG_BUS_SCH2__oSCH_READ_MEID__SHIFT 0x00000008 -#define DEBUG_BUS_SCH2__oSCH_SEND_GRAPHICS_TARG_GDS_GFX_PWR_MASKED__SHIFT 0x0000000a -#define DEBUG_BUS_SCH2__oSCH_SEND_GRAPHICS_TARG_GDS_PWR_MASKED__SHIFT 0x0000000d -#define DEBUG_BUS_SCH2__oSCH_SEND_GRAPHICS_TARG_GDS_MASKED__SHIFT 0x00000010 -#define DEBUG_BUS_SCH2__GRBM_IS_TRAPPED__SHIFT 0x00000013 -#define DEBUG_BUS_SCH2__Reserved0__SHIFT 0x00000014 - -// DEBUG_BUS_SCH3 -#define DEBUG_BUS_SCH3__iRSMU_GRBM_READ_VALID__SHIFT 0x00000000 -#define DEBUG_BUS_SCH3__iGDS_GRBM_READ_FED__SHIFT 0x00000001 -#define DEBUG_BUS_SCH3__iGDS_GRBM_READ_COMPLETE__SHIFT 0x00000002 -#define DEBUG_BUS_SCH3__iGDS_GRBM_READ_VALID__SHIFT 0x00000003 -#define DEBUG_BUS_SCH3__iDBGU_GRBM_READ_VALID__SHIFT 0x00000004 -#define DEBUG_BUS_SCH3__iRLC_GRBM_READ_VALID__SHIFT 0x00000005 -#define DEBUG_BUS_SCH3__iCPF_GRBM_READ_VALID__SHIFT 0x00000006 -#define DEBUG_BUS_SCH3__iCPC_GRBM_READ_VALID__SHIFT 0x00000007 -#define DEBUG_BUS_SCH3__iCPG_GRBM_READ_VALID__SHIFT 0x00000008 -#define DEBUG_BUS_SCH3__iREAD_TIMEOUT_ERROR__SHIFT 0x00000009 -#define DEBUG_BUS_SCH3__iGRBM_READ_VALID__SHIFT 0x0000000a -#define DEBUG_BUS_SCH3__iSE3SPI_GRBM_READ0_VALID__SHIFT 0x0000000b -#define DEBUG_BUS_SCH3__iSE2SPI_GRBM_READ0_VALID__SHIFT 0x0000000c -#define DEBUG_BUS_SCH3__iSE1SPI_GRBM_READ0_VALID__SHIFT 0x0000000d -#define DEBUG_BUS_SCH3__iSE0SPI_GRBM_READ0_VALID__SHIFT 0x0000000e -#define DEBUG_BUS_SCH3__TARG_GRBM_READ_VALID__SHIFT 0x0000000f -#define DEBUG_BUS_SCH3__GDS_BURST_READ_ACTIVE__SHIFT 0x00000010 -#define DEBUG_BUS_SCH3__READ_TIMEOUT_BOTH__SHIFT 0x00000011 -#define DEBUG_BUS_SCH3__READ_TIMEOUT_GRBM__SHIFT 0x00000012 -#define DEBUG_BUS_SCH3__READ_TIMEOUT_RSMU__SHIFT 0x00000013 -#define DEBUG_BUS_SCH3__ONE_READ_PENDING__SHIFT 0x00000014 -#define DEBUG_BUS_SCH3__GRAPHICS_READ_PENDING__SHIFT 0x00000015 -#define DEBUG_BUS_SCH3__SYSTEM_READ_PENDING__SHIFT 0x00000016 -#define DEBUG_BUS_SCH3__TWO_READ_PENDING__SHIFT 0x00000017 -#define DEBUG_BUS_SCH3__Reserved0__SHIFT 0x00000018 - -// DEBUG_BUS_SCH_CNTL0 -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE3_SCH_RTS__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE2_SCH_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE1_SCH_RTS__SHIFT 0x00000002 -#define DEBUG_BUS_SCH_CNTL0__iME2PIPE0_SCH_RTS__SHIFT 0x00000003 -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE3_SCH_RTS__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE2_SCH_RTS__SHIFT 0x00000005 -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE1_SCH_RTS__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_CNTL0__iME1PIPE0_SCH_RTS__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE3_RTR__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE2_RTR__SHIFT 0x00000009 -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE1_RTR__SHIFT 0x0000000a -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME2PIPE0_RTR__SHIFT 0x0000000b -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE3_RTR__SHIFT 0x0000000c -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE2_RTR__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE1_RTR__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_CNTL0__oSCH_ME1PIPE0_RTR__SHIFT 0x0000000f -#define DEBUG_BUS_SCH_CNTL0__Reserved0__SHIFT 0x00000010 - -// DEBUG_BUS_SCH_CNTL1 -#define DEBUG_BUS_SCH_CNTL1__iGDS_DMA_SCH_RTS__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_CNTL1__iME0PIPE1_CF_SCH_RTS__SHIFT 0x00000002 -#define DEBUG_BUS_SCH_CNTL1__iME0PIPE0_PF_SCH_RTS__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_CNTL1__iRLC_SCH_RTS__SHIFT 0x00000005 -#define DEBUG_BUS_SCH_CNTL1__iRSMU_SCH_RTS__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_CNTL1__oSCH_GDS_DMA_RTR__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE1_CF_RTR__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE1_PF_RTR__SHIFT 0x00000009 -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE0_CF_RTR__SHIFT 0x0000000a -#define DEBUG_BUS_SCH_CNTL1__oSCH_ME0PIPE0_PF_RTR__SHIFT 0x0000000b -#define DEBUG_BUS_SCH_CNTL1__oSCH_RLC_RTR__SHIFT 0x0000000c -#define DEBUG_BUS_SCH_CNTL1__oSCH_RSMU_RTR__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_CNTL1__iCPF_SCH_RTS__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_CNTL1__oSCH_CPF_RTR__SHIFT 0x0000000f -#define DEBUG_BUS_SCH_CNTL1__iINTR_SCH_RTS__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_CNTL1__oSCH_INTR_RTR__SHIFT 0x00000011 -#define DEBUG_BUS_SCH_CNTL1__Reserved0__SHIFT 0x00000012 - -// DEBUG_BUS_SCH_CNTL2 -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE3_RTS__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE2_RTS__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE1_RTS__SHIFT 0x00000002 -#define DEBUG_BUS_SCH_CNTL2__ME2PIPE0_RTS__SHIFT 0x00000003 -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE3_RTS__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE2_RTS__SHIFT 0x00000005 -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE1_RTS__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_CNTL2__ME1PIPE0_RTS__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_CNTL2__GDS_DMA_RTS__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE1_CF_RTS__SHIFT 0x00000009 -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE1_PF_RTS__SHIFT 0x0000000a -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE0_CF_RTS__SHIFT 0x0000000b -#define DEBUG_BUS_SCH_CNTL2__ME0PIPE0_PF_RTS__SHIFT 0x0000000c -#define DEBUG_BUS_SCH_CNTL2__RLC_RTS__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_CNTL2__RSMU_RTS__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_CNTL2__CPF_RTS__SHIFT 0x0000000f -#define DEBUG_BUS_SCH_CNTL2__INTR_RTS__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_CNTL2__Reserved0__SHIFT 0x00000011 - -// DEBUG_BUS_SCH_CNTL3 -#define DEBUG_BUS_SCH_CNTL3__ME2PIPE_PRIORITY_ONE_EXISTS__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_CNTL3__ME1PIPE_PRIORITY_ONE_EXISTS__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_CNTL3__ME0PIPE_PRIORITY_ONE_EXISTS__SHIFT 0x00000002 -#define DEBUG_BUS_SCH_CNTL3__NEW_ME_SWITCH__SHIFT 0x00000003 -#define DEBUG_BUS_SCH_CNTL3__xXFER_ID__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_CNTL3__XFER_ME_ID__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_CNTL3__xXFER_ME0PIPE1_ID__SHIFT 0x0000000c -#define DEBUG_BUS_SCH_CNTL3__xXFER_ME0PIPE0_ID__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_CNTL3__CPF_XFC__SHIFT 0x00000014 -#define DEBUG_BUS_SCH_CNTL3__INTR_XFC__SHIFT 0x00000015 -#define DEBUG_BUS_SCH_CNTL3__Reserved0__SHIFT 0x00000016 - -// DEBUG_BUS_SCH_CNTL4 -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE3_CNT_NONZERO__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE2_CNT_NONZERO__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE1_CNT_NONZERO__SHIFT 0x00000002 -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE0_CNT_NONZERO__SHIFT 0x00000003 -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE3_CNT_NONZERO__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE2_CNT_NONZERO__SHIFT 0x00000005 -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE1_CNT_NONZERO__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE0_CNT_NONZERO__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_CNTL4__GDS_DMA_CNT_NONZERO__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE1_CNT_NONZERO__SHIFT 0x00000009 -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE0_CNT_NONZERO__SHIFT 0x0000000a -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE3_XFC__SHIFT 0x0000000b -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE2_XFC__SHIFT 0x0000000c -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE1_XFC__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_CNTL4__ME2PIPE0_XFC__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE3_XFC__SHIFT 0x0000000f -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE2_XFC__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE1_XFC__SHIFT 0x00000011 -#define DEBUG_BUS_SCH_CNTL4__ME1PIPE0_XFC__SHIFT 0x00000012 -#define DEBUG_BUS_SCH_CNTL4__GDS_DMA_XFC__SHIFT 0x00000013 -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE1_XFC__SHIFT 0x00000014 -#define DEBUG_BUS_SCH_CNTL4__ME0PIPE0_XFC__SHIFT 0x00000015 -#define DEBUG_BUS_SCH_CNTL4__RLC_XFC__SHIFT 0x00000016 -#define DEBUG_BUS_SCH_CNTL4__RSMU_XFC__SHIFT 0x00000017 -#define DEBUG_BUS_SCH_CNTL4__Reserved0__SHIFT 0x00000018 - -// DEBUG_BUS_SCH_ME0PIPE0_WD_DMA -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__STOP_DMA_REQUEST__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__iME0PIPEX_SKEW_TOP_THRESHOLD__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__SIZE_CNT__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__VGT_DRAW_INITIATOR__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__VGT_DMA_SIZE_REQ__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_ME0PIPE0_WD_DMA__Reserved0__SHIFT 0x0000000f - -// DEBUG_BUS_SCH_ME0PIPE1_WD_DMA -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__STOP_DMA_REQUEST__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__iME0PIPEX_SKEW_TOP_THRESHOLD__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__SIZE_CNT__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__VGT_DRAW_INITIATOR__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__VGT_DMA_SIZE_REQ__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_ME0PIPE1_WD_DMA__Reserved0__SHIFT 0x0000000f - -// DEBUG_BUS_SCH_HAND0 -#define DEBUG_BUS_SCH_HAND0__SE0SPI_ME0PIPE0_AVAIL_CNT0__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND0__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND0__SE0SPI_ME0PIPE1_AVAIL_CNT0__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND0__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND1 -#define DEBUG_BUS_SCH_HAND1__SE1SPI_ME0PIPE0_AVAIL_CNT0__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND1__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND1__SE1SPI_ME0PIPE1_AVAIL_CNT0__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND1__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND2 -#define DEBUG_BUS_SCH_HAND2__SE2SPI_ME0PIPE0_AVAIL_CNT0__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND2__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND2__SE2SPI_ME0PIPE1_AVAIL_CNT0__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND2__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND3 -#define DEBUG_BUS_SCH_HAND3__SE3SPI_ME0PIPE0_AVAIL_CNT0__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND3__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND3__SE3SPI_ME0PIPE1_AVAIL_CNT0__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND3__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND4 -#define DEBUG_BUS_SCH_HAND4__SE0SPI_ME0PIPE0_AVAIL_CNT1__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND4__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND4__SE0SPI_ME0PIPE1_AVAIL_CNT1__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND4__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND5 -#define DEBUG_BUS_SCH_HAND5__SE1SPI_ME0PIPE0_AVAIL_CNT1__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND5__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND5__SE1SPI_ME0PIPE1_AVAIL_CNT1__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND5__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND6 -#define DEBUG_BUS_SCH_HAND6__SE2SPI_ME0PIPE0_AVAIL_CNT1__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND6__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND6__SE2SPI_ME0PIPE1_AVAIL_CNT1__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND6__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND7 -#define DEBUG_BUS_SCH_HAND7__SE3SPI_ME0PIPE0_AVAIL_CNT1__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND7__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND7__SE3SPI_ME0PIPE1_AVAIL_CNT1__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND7__Reserved1__SHIFT 0x0000000e - -// DEBUG_BUS_SCH_HAND8 -#define DEBUG_BUS_SCH_HAND8__GDS_AVAIL_CNT__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND8__Reserved0__SHIFT 0x00000005 -#define DEBUG_BUS_SCH_HAND8__RSMU_AVAIL_CNT__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND8__Reserved1__SHIFT 0x0000000b -#define DEBUG_BUS_SCH_HAND8__CPF_AVAIL_CNT__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_HAND8__CPG_AVAIL_CNT__SHIFT 0x00000014 -#define DEBUG_BUS_SCH_HAND8__Reserved2__SHIFT 0x00000018 - -// DEBUG_BUS_SCH_HAND9 -#define DEBUG_BUS_SCH_HAND9__WD_ME0PIPE0_AVAIL_CNT__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND9__Reserved0__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND9__WD_ME0PIPE1_AVAIL_CNT__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND9__Reserved1__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_HAND9__iGRAPHICS_RBB_XFC_GFX_PWR_MASKED__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_HAND9__Reserved2__SHIFT 0x00000013 - -// DEBUG_BUS_SCH_HAND10 -#define DEBUG_BUS_SCH_HAND10__iSYSTEM_RBB_XFC__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND10__iGRAPHICS_RBB_XFC_PWR_MASKED__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_HAND10__iGRAPHICS_RBB_XFC__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_GDS_DMA_RDY__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE3_RDY__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE2_RDY__SHIFT 0x00000009 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE1_RDY__SHIFT 0x0000000a -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME2PIPE0_RDY__SHIFT 0x0000000b -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE3_RDY__SHIFT 0x0000000c -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE2_RDY__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE1_RDY__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME1PIPE0_RDY__SHIFT 0x0000000f -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE1_CF_RDY__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE1_PF_RDY__SHIFT 0x00000011 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE0_CF_RDY__SHIFT 0x00000012 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_ME0PIPE0_PF_RDY__SHIFT 0x00000013 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_RLC_RDY__SHIFT 0x00000014 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_RSMU_RDY__SHIFT 0x00000015 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_CPF_RDY__SHIFT 0x00000016 -#define DEBUG_BUS_SCH_HAND10__oTARGETS_FOR_INTR_RDY__SHIFT 0x00000017 -#define DEBUG_BUS_SCH_HAND10__Reserved0__SHIFT 0x00000018 - -// DEBUG_BUS_SCH_HAND11 -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE1_WD_DMA_DRAW_INIT_REQUESTS__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE1_WD_DMA_REQUESTS__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE0_WD_DMA_DRAW_INIT_REQUESTS__SHIFT 0x00000002 -#define DEBUG_BUS_SCH_HAND11__iALLOW_ME0PIPE0_WD_DMA_REQUESTS__SHIFT 0x00000003 -#define DEBUG_BUS_SCH_HAND11__iREAD_TIMEOUT_BOTH__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_HAND11__iONE_READ_PENDING__SHIFT 0x00000005 -#define DEBUG_BUS_SCH_HAND11__iGRAPHICS_READ_PENDING__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND11__GRAPHICS_RBB_XFC_GDS_GFX_PWR_MASKED__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_HAND11__GRAPHICS_RBB_XFC_GDS_PWR_MASKED__SHIFT 0x0000000a -#define DEBUG_BUS_SCH_HAND11__GRAPHICS_RBB_XFC_GDS_MASKED__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_HAND11__TARGETS_RDY_SYSTEM__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_GDS_DMA_AF__SHIFT 0x00000011 -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_MECPIPES_AF__SHIFT 0x00000012 -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_ME0PIPE1_AF__SHIFT 0x00000013 -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_ME0PIPE0_AF__SHIFT 0x00000014 -#define DEBUG_BUS_SCH_HAND11__oTARGETS_RDY_GRAPHICS__SHIFT 0x00000015 -#define DEBUG_BUS_SCH_HAND11__oALL_TARGETS_FLUSHED__SHIFT 0x00000016 -#define DEBUG_BUS_SCH_HAND11__oALL_GFX_TARGETS_FLUSHED__SHIFT 0x00000017 -#define DEBUG_BUS_SCH_HAND11__Reserved0__SHIFT 0x00000018 - -// DEBUG_BUS_SCH_HAND12 -#define DEBUG_BUS_SCH_HAND12__GDS_DMA_READ_PENDING__SHIFT 0x00000000 -#define DEBUG_BUS_SCH_HAND12__ME2PIPE3_READ_PENDING__SHIFT 0x00000001 -#define DEBUG_BUS_SCH_HAND12__ME2PIPE2_READ_PENDING__SHIFT 0x00000002 -#define DEBUG_BUS_SCH_HAND12__ME2PIPE1_READ_PENDING__SHIFT 0x00000003 -#define DEBUG_BUS_SCH_HAND12__ME2PIPE0_READ_PENDING__SHIFT 0x00000004 -#define DEBUG_BUS_SCH_HAND12__ME1PIPE3_READ_PENDING__SHIFT 0x00000005 -#define DEBUG_BUS_SCH_HAND12__ME1PIPE2_READ_PENDING__SHIFT 0x00000006 -#define DEBUG_BUS_SCH_HAND12__ME1PIPE1_READ_PENDING__SHIFT 0x00000007 -#define DEBUG_BUS_SCH_HAND12__ME1PIPE0_READ_PENDING__SHIFT 0x00000008 -#define DEBUG_BUS_SCH_HAND12__ME0PIPE1_CF_READ_PENDING__SHIFT 0x00000009 -#define DEBUG_BUS_SCH_HAND12__ME0PIPE1_PF_READ_PENDING__SHIFT 0x0000000a -#define DEBUG_BUS_SCH_HAND12__ME0PIPE0_CF_READ_PENDING__SHIFT 0x0000000b -#define DEBUG_BUS_SCH_HAND12__ME0PIPE0_PF_READ_PENDING__SHIFT 0x0000000c -#define DEBUG_BUS_SCH_HAND12__RLC_READ_PENDING__SHIFT 0x0000000d -#define DEBUG_BUS_SCH_HAND12__RSMU_READ_PENDING__SHIFT 0x0000000e -#define DEBUG_BUS_SCH_HAND12__READ_PENDING__SHIFT 0x0000000f -#define DEBUG_BUS_SCH_HAND12__CPF_READ_PENDING__SHIFT 0x00000010 -#define DEBUG_BUS_SCH_HAND12__oTARGETS_RDY_CPF_AF__SHIFT 0x00000011 -#define DEBUG_BUS_SCH_HAND12__Reserved0__SHIFT 0x00000012 - -// DEBUG_BUS_REG0 -#define DEBUG_BUS_REG0__COMPUTE_PIPE_BUSY__SHIFT 0x00000000 -#define DEBUG_BUS_REG0__GFX_PIPE_BUSY__SHIFT 0x00000001 -#define DEBUG_BUS_REG0__CORE_COMPUTE_BUSY_F__SHIFT 0x00000002 -#define DEBUG_BUS_REG0__CORE_GFX_BUSY_F__SHIFT 0x00000003 -#define DEBUG_BUS_REG0__iGDS_DMA_PIPE_BUSY__SHIFT 0x00000004 -#define DEBUG_BUS_REG0__iME2PIPE3_PIPE_BUSY__SHIFT 0x00000005 -#define DEBUG_BUS_REG0__iME2PIPE2_PIPE_BUSY__SHIFT 0x00000006 -#define DEBUG_BUS_REG0__iME2PIPE1_PIPE_BUSY__SHIFT 0x00000007 -#define DEBUG_BUS_REG0__iME2PIPE0_PIPE_BUSY__SHIFT 0x00000008 -#define DEBUG_BUS_REG0__iME1PIPE3_PIPE_BUSY__SHIFT 0x00000009 -#define DEBUG_BUS_REG0__iME1PIPE2_PIPE_BUSY__SHIFT 0x0000000a -#define DEBUG_BUS_REG0__iME1PIPE1_PIPE_BUSY__SHIFT 0x0000000b -#define DEBUG_BUS_REG0__iME1PIPE0_PIPE_BUSY__SHIFT 0x0000000c -#define DEBUG_BUS_REG0__iME0PIPE1_CF_PIPE_BUSY__SHIFT 0x0000000d -#define DEBUG_BUS_REG0__iME0PIPE1_PF_PIPE_BUSY__SHIFT 0x0000000e -#define DEBUG_BUS_REG0__iME0PIPE0_CF_PIPE_BUSY__SHIFT 0x0000000f -#define DEBUG_BUS_REG0__iME0PIPE0_PF_PIPE_BUSY__SHIFT 0x00000010 -#define DEBUG_BUS_REG0__iRLC_PIPE_BUSY__SHIFT 0x00000011 -#define DEBUG_BUS_REG0__iCPF_PIPE_BUSY__SHIFT 0x00000012 -#define DEBUG_BUS_REG0__iRSMU_PIPE_BUSY__SHIFT 0x00000013 -#define DEBUG_BUS_REG0__GRBM_BUSY__SHIFT 0x00000014 -#define DEBUG_BUS_REG0__Reserved0__SHIFT 0x00000015 - -// DEBUG_BUS_REG1 -#define DEBUG_BUS_REG1__INT_xXFER_ID__SHIFT 0x00000000 -#define DEBUG_BUS_REG1__INT_XFER_ID__SHIFT 0x00000002 -#define DEBUG_BUS_REG1__qIH_INTR_CREDIT_CNT__SHIFT 0x00000004 -#define DEBUG_BUS_REG1__qGUI_IDLE_INT_DETECTED__SHIFT 0x00000006 -#define DEBUG_BUS_REG1__qRDERR_INT_DETECTED__SHIFT 0x00000007 -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE_TARG__SHIFT 0x00000008 -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE__SHIFT 0x00000009 -#define DEBUG_BUS_REG1__PWR_REQUEST_REJECTED__SHIFT 0x0000000a -#define DEBUG_BUS_REG1__PWR_REQUEST_ACCEPTED__SHIFT 0x0000000b -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT_TARG__SHIFT 0x0000000c -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT__SHIFT 0x0000000d -#define DEBUG_BUS_REG1__oPWR_REQUEST_HALT_TARG__SHIFT 0x0000000e -#define DEBUG_BUS_REG1__PWR_REQUEST_COMPLETE__SHIFT 0x0000000f -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE_GFX_TARG__SHIFT 0x00000010 -#define DEBUG_BUS_REG1__PWR_REQUEST_RELEASE_GFX__SHIFT 0x00000011 -#define DEBUG_BUS_REG1__PWR_REQUEST_GFX_REJECTED__SHIFT 0x00000012 -#define DEBUG_BUS_REG1__PWR_REQUEST_GFX_ACCEPTED__SHIFT 0x00000013 -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT_GFX_TARG__SHIFT 0x00000014 -#define DEBUG_BUS_REG1__PWR_REQUEST_HALT_GFX__SHIFT 0x00000015 -#define DEBUG_BUS_REG1__oPWR_REQUEST_HALT_GFX_TARG__SHIFT 0x00000016 -#define DEBUG_BUS_REG1__PWR_REQUEST_GFX_COMPLETE__SHIFT 0x00000017 -#define DEBUG_BUS_REG1__Reserved0__SHIFT 0x00000018 - -// DEBUG_BUS_REG2 -#define DEBUG_BUS_REG2__REGBUS_ADDR__SHIFT 0x00000000 -#define DEBUG_BUS_REG2__REGBUS_WD__SHIFT 0x00000010 -#define DEBUG_BUS_REG2__REGBUS_RE__SHIFT 0x00000016 -#define DEBUG_BUS_REG2__REGBUS_WE__SHIFT 0x00000017 -#define DEBUG_BUS_REG2__Reserved0__SHIFT 0x00000018 - -// wbuf_DEBUG_DATA -#define wbuf_DEBUG_DATA__Reserved0__SHIFT 0x00000000 -#define wbuf_DEBUG_DATA__write_buff_valid__SHIFT 0x00000006 -#define wbuf_DEBUG_DATA__wr_pixel_ptr_nxt__SHIFT 0x00000007 -#define wbuf_DEBUG_DATA__last_pixel_ptr__SHIFT 0x0000000c -#define wbuf_DEBUG_DATA__cstate_3to0__SHIFT 0x0000000d -#define wbuf_DEBUG_DATA__buff_write__SHIFT 0x00000011 -#define wbuf_DEBUG_DATA__flush_request__SHIFT 0x00000012 -#define wbuf_DEBUG_DATA__wr_buffer_wr_complete__SHIFT 0x00000013 -#define wbuf_DEBUG_DATA__wbuf_fifo_empty__SHIFT 0x00000014 -#define wbuf_DEBUG_DATA__wbuf_fifo_full__SHIFT 0x00000015 -#define wbuf_DEBUG_DATA__Reserved1__SHIFT 0x00000016 - -// rbuf_DEBUG_DATA -#define rbuf_DEBUG_DATA__tag_hit__SHIFT 0x00000000 -#define rbuf_DEBUG_DATA__tag_miss__SHIFT 0x00000001 -#define rbuf_DEBUG_DATA__pixel_addr_mask__SHIFT 0x00000002 -#define rbuf_DEBUG_DATA__pixel_vld__SHIFT 0x00000011 -#define rbuf_DEBUG_DATA__data_ready__SHIFT 0x00000012 -#define rbuf_DEBUG_DATA__awaiting_data__SHIFT 0x00000013 -#define rbuf_DEBUG_DATA__addr_fifo_full__SHIFT 0x00000014 -#define rbuf_DEBUG_DATA__addr_fifo_empty__SHIFT 0x00000015 -#define rbuf_DEBUG_DATA__buffer_loaded__SHIFT 0x00000016 -#define rbuf_DEBUG_DATA__buffer_invalid__SHIFT 0x00000017 -#define rbuf_DEBUG_DATA__Reserved0__SHIFT 0x00000018 - -// oa_wc0_DEBUG_DATA -#define oa_wc0_DEBUG_DATA__ds_full__SHIFT 0x00000000 -#define oa_wc0_DEBUG_DATA__credit_cnt__SHIFT 0x00000001 -#define oa_wc0_DEBUG_DATA__ord_idx_free__SHIFT 0x00000002 -#define oa_wc0_DEBUG_DATA__cmd_write__SHIFT 0x00000003 -#define oa_wc0_DEBUG_DATA__app_sel__SHIFT 0x00000004 -#define oa_wc0_DEBUG_DATA__req__SHIFT 0x00000008 -#define oa_wc0_DEBUG_DATA__Reserved0__SHIFT 0x00000013 - -// oa_wc1_DEBUG_DATA -#define oa_wc1_DEBUG_DATA__pipe0_busy__SHIFT 0x00000000 -#define oa_wc1_DEBUG_DATA__pipe1_busy__SHIFT 0x00000001 -#define oa_wc1_DEBUG_DATA__pipe2_busy__SHIFT 0x00000002 -#define oa_wc1_DEBUG_DATA__pipe3_busy__SHIFT 0x00000003 -#define oa_wc1_DEBUG_DATA__pipe4_busy__SHIFT 0x00000004 -#define oa_wc1_DEBUG_DATA__pipe5_busy__SHIFT 0x00000005 -#define oa_wc1_DEBUG_DATA__pipe6_busy__SHIFT 0x00000006 -#define oa_wc1_DEBUG_DATA__pipe7_busy__SHIFT 0x00000007 -#define oa_wc1_DEBUG_DATA__pipe8_busy__SHIFT 0x00000008 -#define oa_wc1_DEBUG_DATA__pipe9_busy__SHIFT 0x00000009 -#define oa_wc1_DEBUG_DATA__Pipe10_busy__SHIFT 0x0000000a -#define oa_wc1_DEBUG_DATA__pipe0_busy0__SHIFT 0x0000000b -#define oa_wc1_DEBUG_DATA__pipe0_busy1__SHIFT 0x0000000c -#define oa_wc1_DEBUG_DATA__pipe0_busy2__SHIFT 0x0000000d -#define oa_wc1_DEBUG_DATA__pipe0_busy3__SHIFT 0x0000000e -#define oa_wc1_DEBUG_DATA__pipe0_busy4__SHIFT 0x0000000f -#define oa_wc1_DEBUG_DATA__pipe0_busy5__SHIFT 0x00000010 -#define oa_wc1_DEBUG_DATA__pipe0_busy6__SHIFT 0x00000011 -#define oa_wc1_DEBUG_DATA__pipe0_busy7__SHIFT 0x00000012 -#define oa_wc1_DEBUG_DATA__Reserved0__SHIFT 0x00000013 - -// gws_DEBUG_DATA -#define gws_DEBUG_DATA__gws_busy__SHIFT 0x00000000 -#define gws_DEBUG_DATA__gws_req__SHIFT 0x00000001 -#define gws_DEBUG_DATA__gws_out_stall__SHIFT 0x00000002 -#define gws_DEBUG_DATA__cur_reso_5to0__SHIFT 0x00000003 -#define gws_DEBUG_DATA__cur_reso_head_valid__SHIFT 0x00000009 -#define gws_DEBUG_DATA__cur_reso_head_dirty__SHIFT 0x0000000a -#define gws_DEBUG_DATA__cur_reso_head_flag__SHIFT 0x0000000b -#define gws_DEBUG_DATA__cur_reso_fed__SHIFT 0x0000000c -#define gws_DEBUG_DATA__cur_reso_barrier__SHIFT 0x0000000d -#define gws_DEBUG_DATA__cur_reso_flag__SHIFT 0x0000000e -#define gws_DEBUG_DATA__cur_reso_count__SHIFT 0x0000000f -#define gws_DEBUG_DATA__credit_cnt__SHIFT 0x00000010 -#define gws_DEBUG_DATA__cmd_write__SHIFT 0x00000011 -#define gws_DEBUG_DATA__grbm_gws_reso_wr__SHIFT 0x00000012 -#define gws_DEBUG_DATA__grbm_gws_reso_rd__SHIFT 0x00000013 -#define gws_DEBUG_DATA__ram_read_busy__SHIFT 0x00000014 -#define gws_DEBUG_DATA__gws_bulkfree__SHIFT 0x00000015 -#define gws_DEBUG_DATA__ram_gws_re__SHIFT 0x00000016 -#define gws_DEBUG_DATA__ram_gws_we__SHIFT 0x00000017 -#define gws_DEBUG_DATA__Reserved0__SHIFT 0x00000018 - -// alloc_DEBUG_DATA -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_write_dis__SHIFT 0x00000000 -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_dec_error__SHIFT 0x00000001 -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_alloc_opco_error__SHIFT 0x00000002 -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_dealloc_opco_error__SHIFT 0x00000003 -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_wrap_opco_error__SHIFT 0x00000004 -#define alloc_DEBUG_DATA__Reserved0__SHIFT 0x00000005 -#define alloc_DEBUG_DATA__GDS_DEBUG_REG5_error_ds_address__SHIFT 0x00000008 -#define alloc_DEBUG_DATA__Reserved1__SHIFT 0x00000016 - -// ord_app_DEBUG_DATA -#define ord_app_DEBUG_DATA__fifo_busy__SHIFT 0x00000000 -#define ord_app_DEBUG_DATA__ord_busy__SHIFT 0x00000001 -#define ord_app_DEBUG_DATA__gws_busy__SHIFT 0x00000002 -#define ord_app_DEBUG_DATA__Reserved0__SHIFT 0x00000003 -#define ord_app_DEBUG_DATA__sh0_cmd_fifo_empty__SHIFT 0x00000004 -#define ord_app_DEBUG_DATA__sh1_cmd_fifo_empty__SHIFT 0x00000005 -#define ord_app_DEBUG_DATA__sh2_cmd_fifo_empty__SHIFT 0x00000006 -#define ord_app_DEBUG_DATA__sh3_cmd_fifo_empty__SHIFT 0x00000007 -#define ord_app_DEBUG_DATA__sh0_data_fifo_empty__SHIFT 0x00000008 -#define ord_app_DEBUG_DATA__sh1_data_fifo_empty__SHIFT 0x00000009 -#define ord_app_DEBUG_DATA__sh2_data_fifo_empty__SHIFT 0x0000000a -#define ord_app_DEBUG_DATA__sh3_data_fifo_empty__SHIFT 0x0000000b -#define ord_app_DEBUG_DATA__Reserved1__SHIFT 0x0000000c - -// GPM_CMN_debug_0_data -#define GPM_CMN_debug_0_data__Reserved1__SHIFT 0x00000000 -#define GPM_CMN_debug_0_data__Rlc_gpm_busy__SHIFT 0x0000000a -#define GPM_CMN_debug_0_data__Rlc_spm_busy__SHIFT 0x0000000b -#define GPM_CMN_debug_0_data__Reserved0__SHIFT 0x0000000c - -// GPM_CMN_debug_1_data -#define GPM_CMN_debug_1_data__loadRTS__SHIFT 0x00000000 -#define GPM_CMN_debug_1_data__loadValid__SHIFT 0x00000001 -#define GPM_CMN_debug_1_data__loadSel__SHIFT 0x00000002 -#define GPM_CMN_debug_1_data__MC_LOAD_wrreq_flushed__SHIFT 0x00000004 -#define GPM_CMN_debug_1_data__RLC_GPM_CMN_miu_rd_vld__SHIFT 0x00000005 -#define GPM_CMN_debug_1_data__GRBMCLIENT_LOAD_rsp_valid__SHIFT 0x00000006 -#define GPM_CMN_debug_1_data__LOAD_SCRATCH_rreg_valid__SHIFT 0x00000007 -#define GPM_CMN_debug_1_data__loadRtnThreadId__SHIFT 0x00000008 -#define GPM_CMN_debug_1_data__RLC_GPM_CMN_miu_rd_rts__SHIFT 0x0000000a -#define GPM_CMN_debug_1_data__LOAD_GRBMCLIENT_read__SHIFT 0x0000000b -#define GPM_CMN_debug_1_data__loadGlobalFifoEmpty__SHIFT 0x0000000c -#define GPM_CMN_debug_1_data__loadGlobalFifoFull__SHIFT 0x0000000d -#define GPM_CMN_debug_1_data__loadMemFifoEmpty__SHIFT 0x0000000e -#define GPM_CMN_debug_1_data__loadMemFifoFull__SHIFT 0x0000000f -#define GPM_CMN_debug_1_data__loadRegFifoEmpty__SHIFT 0x00000010 -#define GPM_CMN_debug_1_data__loadRegFifoFull__SHIFT 0x00000011 -#define GPM_CMN_debug_1_data__loadRTR__SHIFT 0x00000012 -#define GPM_CMN_debug_1_data__SMU_RLC_clock_on__SHIFT 0x00000013 -#define GPM_CMN_debug_1_data__load_global_pending__SHIFT 0x00000014 -#define GPM_CMN_debug_1_data__loadLocalValid__SHIFT 0x00000015 -#define GPM_CMN_debug_1_data__loadRegValid__SHIFT 0x00000016 -#define GPM_CMN_debug_1_data__loadMemValid__SHIFT 0x00000017 -#define GPM_CMN_debug_1_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_2_data -#define GPM_CMN_debug_2_data__storeRTR_0__SHIFT 0x00000000 -#define GPM_CMN_debug_2_data__storeRTS__SHIFT 0x00000001 -#define GPM_CMN_debug_2_data__storeSel__SHIFT 0x00000002 -#define GPM_CMN_debug_2_data__storeMemFifoFull__SHIFT 0x00000004 -#define GPM_CMN_debug_2_data__GRBMCLIENT_STORE_write_done__SHIFT 0x00000005 -#define GPM_CMN_debug_2_data__UcodeBusyFlag__SHIFT 0x00000006 -#define GPM_CMN_debug_2_data__STORE_RLCV_SCRATCH_wreg_valid__SHIFT 0x00000007 -#define GPM_CMN_debug_2_data__STORE_IH_ctxid2_we__SHIFT 0x00000008 -#define GPM_CMN_debug_2_data__STORE_SCRATCH_wreg_valid__SHIFT 0x00000009 -#define GPM_CMN_debug_2_data__STORE_GRBMT_wreg_valid__SHIFT 0x0000000a -#define GPM_CMN_debug_2_data__STORE_IH_intrid_we__SHIFT 0x0000000b -#define GPM_CMN_debug_2_data__STORE_IH_ctxid_we__SHIFT 0x0000000c -#define GPM_CMN_debug_2_data__storeRTR_2__SHIFT 0x0000000d -#define GPM_CMN_debug_2_data__RLCC_GCPM_cgcg_request__SHIFT 0x0000000e -#define GPM_CMN_debug_2_data__storeRTR_1__SHIFT 0x0000000f -#define GPM_CMN_debug_2_data__STORE_IR1_intrsp_send__SHIFT 0x00000010 -#define GPM_CMN_debug_2_data__STORE_IR0_intrsp_send__SHIFT 0x00000011 -#define GPM_CMN_debug_2_data__STORE_GRBMCLIENT_meid__SHIFT 0x00000012 -#define GPM_CMN_debug_2_data__STORE_GRBMCLIENT_pipeid__SHIFT 0x00000014 -#define GPM_CMN_debug_2_data__Reserved0__SHIFT 0x00000016 - -// GPM_CMN_debug_3_data -#define GPM_CMN_debug_3_data__Credit_count__SHIFT 0x00000000 -#define GPM_CMN_debug_3_data__Credit_available__SHIFT 0x00000006 -#define GPM_CMN_debug_3_data__Sm_count__SHIFT 0x00000007 -#define GPM_CMN_debug_3_data__Disable_state_machine__SHIFT 0x0000000a -#define GPM_CMN_debug_3_data__Enable_state_machine__SHIFT 0x0000000b -#define GPM_CMN_debug_3_data__Interrupt_send__SHIFT 0x0000000c -#define GPM_CMN_debug_3_data__STORE_IH_write_done__SHIFT 0x0000000d -#define GPM_CMN_debug_3_data__STORE_IH_intrid2_we__SHIFT 0x0000000e -#define GPM_CMN_debug_3_data__STORE_IH_intrid_we__SHIFT 0x0000000f -#define GPM_CMN_debug_3_data__STORE_IH_ctxid2_we__SHIFT 0x00000010 -#define GPM_CMN_debug_3_data__STORE_IH_ctxid_we__SHIFT 0x00000011 -#define GPM_CMN_debug_3_data__Reserved0__SHIFT 0x00000012 - -// GPM_CMN_debug_4_data -#define GPM_CMN_debug_4_data__LOAD_SSCRATCH_rreg_valid__SHIFT 0x00000000 -#define GPM_CMN_debug_4_data__LOAD_SCRATCH_rreg_threadid__SHIFT 0x00000001 -#define GPM_CMN_debug_4_data__LOAD_SCRATCH_rreg_instrsel__SHIFT 0x00000003 -#define GPM_CMN_debug_4_data__STORE_SCRATCH_wreg_valid__SHIFT 0x00000005 -#define GPM_CMN_debug_4_data__LoadScratchRamReQ2__SHIFT 0x00000006 -#define GPM_CMN_debug_4_data__LoadScratchRamReQ1__SHIFT 0x00000007 -#define GPM_CMN_debug_4_data__ScratchRamRdEn__SHIFT 0x00000008 -#define GPM_CMN_debug_4_data__ScratchRamWrEn__SHIFT 0x00000009 -#define GPM_CMN_debug_4_data__SCRATCH_LOAD_rsp_threadid__SHIFT 0x0000000a -#define GPM_CMN_debug_4_data__SCRATCH_LOAD_rsp_instrsel__SHIFT 0x0000000c -#define GPM_CMN_debug_4_data__SCRATCH_LOAD_rsp_valid__SHIFT 0x0000000e -#define GPM_CMN_debug_4_data__ScratchRamRdAddr_8to0__SHIFT 0x0000000f -#define GPM_CMN_debug_4_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_5_data -#define GPM_CMN_debug_5_data__Serdes_ctrl_Debug__SHIFT 0x00000000 -#define GPM_CMN_debug_5_data__Cgcg_cgls_ctrl_Debug__SHIFT 0x00000001 -#define GPM_CMN_debug_5_data__Reserved0__SHIFT 0x00000015 - -// GPM_CMN_debug_6_data -#define GPM_CMN_debug_6_data__IR0_LOAD_interrupt_id_8__SHIFT 0x00000000 -#define GPM_CMN_debug_6_data__IR1_LOAD_interrupt_id_8__SHIFT 0x00000001 -#define GPM_CMN_debug_6_data__IR2_LOAD_interrupt_id_8__SHIFT 0x00000002 -#define GPM_CMN_debug_6_data__GFX_pwr_stalled_status__SHIFT 0x00000003 -#define GPM_CMN_debug_6_data__GRBMT_LOAD_rlc_lb_cntr_stop_flag__SHIFT 0x00000004 -#define GPM_CMN_debug_6_data__GRBMT_LOAD_rlc_lb_cntr_start_flag__SHIFT 0x00000005 -#define GPM_CMN_debug_6_data__GRBMT_LOAD_rlc_lb_cntr_max_flag__SHIFT 0x00000006 -#define GPM_CMN_debug_6_data__GFX_power_status__SHIFT 0x00000007 -#define GPM_CMN_debug_6_data__GFX_clock_status__SHIFT 0x00000008 -#define GPM_CMN_debug_6_data__GFX_ls_status__SHIFT 0x00000009 -#define GPM_CMN_debug_6_data__GPM_STAT_pipeline_power_status__SHIFT 0x0000000a -#define GPM_CMN_debug_6_data__GPM_STAT_cntx_idle_being_processed__SHIFT 0x0000000b -#define GPM_CMN_debug_6_data__GPM_STAT_cntx_busy_being_processed__SHIFT 0x0000000c -#define GPM_CMN_debug_6_data__GPM_STAT_gfx_idle_being_processed__SHIFT 0x0000000d -#define GPM_CMN_debug_6_data__GPM_STAT_cmp_busy_being_processed__SHIFT 0x0000000e -#define GPM_CMN_debug_6_data__GPM_STAT_saving_registers__SHIFT 0x0000000f -#define GPM_CMN_debug_6_data__GPM_STAT_restoring_registers__SHIFT 0x00000010 -#define GPM_CMN_debug_6_data__GPM_STAT_gfx3d_blocks_changing_power_state__SHIFT 0x00000011 -#define GPM_CMN_debug_6_data__GPM_STAT_cmp_blocks_changing_power_state__SHIFT 0x00000012 -#define GPM_CMN_debug_6_data__GPM_STAT_static_cu_powering_up__SHIFT 0x00000013 -#define GPM_CMN_debug_6_data__GPM_STAT_static_cu_powering_down__SHIFT 0x00000014 -#define GPM_CMN_debug_6_data__GPM_STAT_dyn_cu_powering_up__SHIFT 0x00000015 -#define GPM_CMN_debug_6_data__GPM_STAT_dyn_cu_powering_down__SHIFT 0x00000016 -#define GPM_CMN_debug_6_data__GPM_STAT_aborted_pd_sequence__SHIFT 0x00000017 -#define GPM_CMN_debug_6_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_7_data -#define GPM_CMN_debug_7_data__f32DebugBus_23to0__SHIFT 0x00000000 -#define GPM_CMN_debug_7_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_8_data -#define GPM_CMN_debug_8_data__f32DebugBus_47to24__SHIFT 0x00000000 -#define GPM_CMN_debug_8_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_9_data -#define GPM_CMN_debug_9_data__f32DebugBus_71to48__SHIFT 0x00000000 -#define GPM_CMN_debug_9_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_10_data -#define GPM_CMN_debug_10_data__f32DebugBus_95to72__SHIFT 0x00000000 -#define GPM_CMN_debug_10_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_11_data -#define GPM_CMN_debug_11_data__f32DebugBus_119to96__SHIFT 0x00000000 -#define GPM_CMN_debug_11_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_12_data -#define GPM_CMN_debug_12_data__f32DebugBus_143to120__SHIFT 0x00000000 -#define GPM_CMN_debug_12_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_13_data -#define GPM_CMN_debug_13_data__f32DebugBus_167to144__SHIFT 0x00000000 -#define GPM_CMN_debug_13_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_14_data -#define GPM_CMN_debug_14_data__f32DebugBus_191to168__SHIFT 0x00000000 -#define GPM_CMN_debug_14_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_15_data -#define GPM_CMN_debug_15_data__f32DebugBus_215to192__SHIFT 0x00000000 -#define GPM_CMN_debug_15_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_16_data -#define GPM_CMN_debug_16_data__f32DebugBus_239to216__SHIFT 0x00000000 -#define GPM_CMN_debug_16_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_17_data -#define GPM_CMN_debug_17_data__f32DebugBus_263to240__SHIFT 0x00000000 -#define GPM_CMN_debug_17_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_18_data -#define GPM_CMN_debug_18_data__f32DebugBus_287to264__SHIFT 0x00000000 -#define GPM_CMN_debug_18_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_19_data -#define GPM_CMN_debug_19_data__f32DebugBus_311to288__SHIFT 0x00000000 -#define GPM_CMN_debug_19_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_20_data -#define GPM_CMN_debug_20_data__f32DebugBus_335to312__SHIFT 0x00000000 -#define GPM_CMN_debug_20_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_21_data -#define GPM_CMN_debug_21_data__f32DebugBus_359to336__SHIFT 0x00000000 -#define GPM_CMN_debug_21_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_22_data -#define GPM_CMN_debug_22_data__f32DebugBus_383to360__SHIFT 0x00000000 -#define GPM_CMN_debug_22_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_23_data -#define GPM_CMN_debug_23_data__f32DebugBus_407to384__SHIFT 0x00000000 -#define GPM_CMN_debug_23_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_24_data -#define GPM_CMN_debug_24_data__f32DebugBus_431to408__SHIFT 0x00000000 -#define GPM_CMN_debug_24_data__Reserved0__SHIFT 0x00000018 - -// GPM_CMN_debug_25_data -#define GPM_CMN_debug_25_data__f32DebugBus_447to432__SHIFT 0x00000000 -#define GPM_CMN_debug_25_data__GRBM_SCRATCH_rreg_valid__SHIFT 0x00000010 -#define GPM_CMN_debug_25_data__GRBM_SCRATCH_wreg_valid__SHIFT 0x00000011 -#define GPM_CMN_debug_25_data__Unassigned__SHIFT 0x00000012 -#define GPM_CMN_debug_25_data__Reserved0__SHIFT 0x00000018 - -// SPM_CMN_debug_0_data -#define SPM_CMN_debug_0_data__Reserved1__SHIFT 0x00000000 -#define SPM_CMN_debug_0_data__SpmInterrupteDetected__SHIFT 0x00000004 -#define SPM_CMN_debug_0_data__McFifoEmpty__SHIFT 0x00000005 -#define SPM_CMN_debug_0_data__GlobalFifoEmpty__SHIFT 0x00000006 -#define SPM_CMN_debug_0_data__WptrFifoEmpty__SHIFT 0x00000007 -#define SPM_CMN_debug_0_data__GlobalFifoFull__SHIFT 0x00000008 -#define SPM_CMN_debug_0_data__SpmCurrentState__SHIFT 0x00000009 -#define SPM_CMN_debug_0_data__SeSegmentDone__SHIFT 0x0000000c -#define SPM_CMN_debug_0_data__GlobalSegmentDone__SHIFT 0x0000000d -#define SPM_CMN_debug_0_data__WptrFifoFull__SHIFT 0x0000000e -#define SPM_CMN_debug_0_data__McFifoFull__SHIFT 0x0000000f -#define SPM_CMN_debug_0_data__SampleTimerExpired__SHIFT 0x00000010 -#define SPM_CMN_debug_0_data__SpmStopCounting__SHIFT 0x00000011 -#define SPM_CMN_debug_0_data__SpmStartCounting__SHIFT 0x00000012 -#define SPM_CMN_debug_0_data__StopSampleTimer__SHIFT 0x00000013 -#define SPM_CMN_debug_0_data__StartSampleTimer__SHIFT 0x00000014 -#define SPM_CMN_debug_0_data__SpmStall__SHIFT 0x00000015 -#define SPM_CMN_debug_0_data__SpmDebugStall__SHIFT 0x00000016 -#define SPM_CMN_debug_0_data__SpmRingAlmostFull_q__SHIFT 0x00000017 -#define SPM_CMN_debug_0_data__Reserved0__SHIFT 0x00000018 - -// SPM_CMN_debug_1_data -#define SPM_CMN_debug_1_data__Reserved1__SHIFT 0x00000000 -#define SPM_CMN_debug_1_data__SpmId__SHIFT 0x00000005 -#define SPM_CMN_debug_1_data__SpmDeSerCurrentState__SHIFT 0x00000006 -#define SPM_CMN_debug_1_data__Se3FifoFull__SHIFT 0x0000000c -#define SPM_CMN_debug_1_data__Se3FifoEmpty__SHIFT 0x0000000d -#define SPM_CMN_debug_1_data__Se3SegmentDone__SHIFT 0x0000000e -#define SPM_CMN_debug_1_data__Se2FifoFull__SHIFT 0x0000000f -#define SPM_CMN_debug_1_data__Se2FifoEmpty__SHIFT 0x00000010 -#define SPM_CMN_debug_1_data__Se2SegmentDone__SHIFT 0x00000011 -#define SPM_CMN_debug_1_data__Se1FifoFull__SHIFT 0x00000012 -#define SPM_CMN_debug_1_data__Se1FifoEmpty__SHIFT 0x00000013 -#define SPM_CMN_debug_1_data__Se1SegmentDone__SHIFT 0x00000014 -#define SPM_CMN_debug_1_data__Se0FifoFull__SHIFT 0x00000015 -#define SPM_CMN_debug_1_data__Se0FifoEmpty__SHIFT 0x00000016 -#define SPM_CMN_debug_1_data__Se0SegmentDone__SHIFT 0x00000017 -#define SPM_CMN_debug_1_data__Reserved0__SHIFT 0x00000018 - -// SPM_CMN_debug_2_data -#define SPM_CMN_debug_2_data__Reserved0__SHIFT 0x00000000 - -// SPM_CMN_debug_3_data -#define SPM_CMN_debug_3_data__Reserved0__SHIFT 0x00000000 - -// SPM_CMN_debug_4_data -#define SPM_CMN_debug_4_data__Reserved0__SHIFT 0x00000000 - -// SPM_CMN_debug_5_data -#define SPM_CMN_debug_5_data__Reserved0__SHIFT 0x00000000 - -// SPM_CMN_debug_6_data -#define SPM_CMN_debug_6_data__Reserved0__SHIFT 0x00000000 - -// SPM_CMN_debug_7_data -#define SPM_CMN_debug_7_data__Reserved0__SHIFT 0x00000000 - -// SPM_CMN_debug_8_data -#define SPM_CMN_debug_8_data__Reserved0__SHIFT 0x00000000 - -// SPM_CMN_debug_9_data -#define SPM_CMN_debug_9_data__Reserved0__SHIFT 0x00000000 - -// SRM_CMN_debug_0_data -#define SRM_CMN_debug_0_data__SrmGpmAbort__SHIFT 0x00000000 -#define SRM_CMN_debug_0_data__SrmCmdArb__SHIFT 0x00000001 -#define SRM_CMN_debug_0_data__SrmCmdDone__SHIFT 0x00000003 -#define SRM_CMN_debug_0_data__SrmState__SHIFT 0x00000004 -#define SRM_CMN_debug_0_data__SrmCmdIndexSel__SHIFT 0x00000008 -#define SRM_CMN_debug_0_data__SrmGpmCmdFifoEmpty__SHIFT 0x0000000b -#define SRM_CMN_debug_0_data__SrmAramRamRdEn__SHIFT 0x0000000c -#define SRM_CMN_debug_0_data__SrmAramRamWrEn__SHIFT 0x0000000d -#define SRM_CMN_debug_0_data__SrmAramRamWrAddr__SHIFT 0x0000000e -#define SRM_CMN_debug_0_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_1_data -#define SRM_CMN_debug_1_data__SrmAramRamWrData__SHIFT 0x00000000 -#define SRM_CMN_debug_1_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_2_data -#define SRM_CMN_debug_2_data__SrmAramRamWrData__SHIFT 0x00000000 -#define SRM_CMN_debug_2_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_3_data -#define SRM_CMN_debug_3_data__SrmDramRamWrData__SHIFT 0x00000000 -#define SRM_CMN_debug_3_data__SrmDramRamWrAddr_9to0__SHIFT 0x0000000c -#define SRM_CMN_debug_3_data__SrmDramRamWrEn__SHIFT 0x00000016 -#define SRM_CMN_debug_3_data__SrmDramRamRdEn__SHIFT 0x00000017 -#define SRM_CMN_debug_3_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_4_data -#define SRM_CMN_debug_4_data__SrmDramRamWrData_31to12__SHIFT 0x00000000 -#define SRM_CMN_debug_4_data__RLC_SRM_CMN_grbmc_wr_rtr__SHIFT 0x00000016 -#define SRM_CMN_debug_4_data__SrmDramRamRdEn__SHIFT 0x00000017 -#define SRM_CMN_debug_4_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_5_data -#define SRM_CMN_debug_5_data__SrmGrbmcWrFifoWrData_23to0__SHIFT 0x00000000 -#define SRM_CMN_debug_5_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_6_data -#define SRM_CMN_debug_6_data__SrmGrbmcWrFifoWrData_47to24__SHIFT 0x00000000 -#define SRM_CMN_debug_6_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_7_data -#define SRM_CMN_debug_7_data__SrmGrbmcWrFifoWrData_71to48__SHIFT 0x00000000 -#define SRM_CMN_debug_7_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_8_data -#define SRM_CMN_debug_8_data__SrmGrbmcWrFifoWrData_79to72__SHIFT 0x00000000 -#define SRM_CMN_debug_8_data__SrmGrbmcRdFifoWe__SHIFT 0x00000008 -#define SRM_CMN_debug_8_data__SrmGrbmcRdFifoRe__SHIFT 0x00000009 -#define SRM_CMN_debug_8_data__SrmGrbmcRdFifoWrData_13to0__SHIFT 0x0000000a -#define SRM_CMN_debug_8_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_9_data -#define SRM_CMN_debug_9_data__SrmGrbmcRdFifoWrData_37to14__SHIFT 0x00000000 -#define SRM_CMN_debug_9_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_10_data -#define SRM_CMN_debug_10_data__SrmGrbmcRdFifoWrData_47to38__SHIFT 0x00000000 -#define SRM_CMN_debug_10_data__RLC_SRM_CMN_grbmc_rd_rtn_data_11to0__SHIFT 0x0000000a -#define SRM_CMN_debug_10_data__SrmGrbmcRdRtnFifoRd__SHIFT 0x00000016 -#define SRM_CMN_debug_10_data__RLC_SRM_CMN_grbmc_rd_rtn_valid__SHIFT 0x00000017 -#define SRM_CMN_debug_10_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_11_data -#define SRM_CMN_debug_11_data__RLC_SRM_CMN_grbmc_rd_rtn_data_31to12__SHIFT 0x00000000 -#define SRM_CMN_debug_11_data__SrmGpmCmdFifoRd__SHIFT 0x00000014 -#define SRM_CMN_debug_11_data__SrmGpmCommand_We__SHIFT 0x00000015 -#define SRM_CMN_debug_11_data__Reserved0__SHIFT 0x00000016 - -// SRM_CMN_debug_12_data -#define SRM_CMN_debug_12_data__Reg_wd_31to12__SHIFT 0x00000000 -#define SRM_CMN_debug_12_data__SrmGpmCmdFifoRdData_3to0__SHIFT 0x00000013 -#define SRM_CMN_debug_12_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_13_data -#define SRM_CMN_debug_13_data__SrmGpmCmdFifoRdData_27to4__SHIFT 0x00000000 -#define SRM_CMN_debug_13_data__Reserved0__SHIFT 0x00000018 - -// SRM_CMN_debug_14_data -#define SRM_CMN_debug_14_data__SrmGpmCmdFifoRdData_31to28__SHIFT 0x00000000 -#define SRM_CMN_debug_14_data__SrmRlcvCmdFifoRd__SHIFT 0x00000004 -#define SRM_CMN_debug_14_data__SrmRlcvCommand_we__SHIFT 0x00000005 -#define SRM_CMN_debug_14_data__Reg_wd_11to0__SHIFT 0x00000006 -#define SRM_CMN_debug_14_data__Reserved0__SHIFT 0x00000012 - -// SRM_CMN_debug_15_data -#define SRM_CMN_debug_15_data__Reserved0__SHIFT 0x00000000 - -// CB_DEBUGBUS_1 -#define CB_DEBUGBUS_1__CB_BUSY__SHIFT 0x00000000 -#define CB_DEBUGBUS_1__DB_CB_TILE_VALID_READY__SHIFT 0x00000001 -#define CB_DEBUGBUS_1__DB_CB_TILE_VALID_READYB__SHIFT 0x00000002 -#define CB_DEBUGBUS_1__DB_CB_TILE_VALIDB_READY__SHIFT 0x00000003 -#define CB_DEBUGBUS_1__DB_CB_TILE_VALIDB_READYB__SHIFT 0x00000004 -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALID_READY__SHIFT 0x00000005 -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALID_READYB__SHIFT 0x00000006 -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALIDB_READY__SHIFT 0x00000007 -#define CB_DEBUGBUS_1__DB_CB_LQUAD_VALIDB_READYB__SHIFT 0x00000008 -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALID_READY__SHIFT 0x00000009 -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALID_READYB__SHIFT 0x0000000a -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALIDB_READY__SHIFT 0x0000000b -#define CB_DEBUGBUS_1__CB_TAP_WRREQ_VALIDB_READYB__SHIFT 0x0000000c -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALID_READY__SHIFT 0x0000000d -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALID_READYB__SHIFT 0x0000000e -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALIDB_READY__SHIFT 0x0000000f -#define CB_DEBUGBUS_1__CB_TAP_RDREQ_VALIDB_READYB__SHIFT 0x00000010 -#define CB_DEBUGBUS_1__CM_FC_TILE_VALID_READY__SHIFT 0x00000011 -#define CB_DEBUGBUS_1__CM_FC_TILE_VALID_READYB__SHIFT 0x00000012 -#define CB_DEBUGBUS_1__CM_FC_TILE_VALIDB_READY__SHIFT 0x00000013 -#define CB_DEBUGBUS_1__CM_FC_TILE_VALIDB_READYB__SHIFT 0x00000014 -#define CB_DEBUGBUS_1__FC_CLEAR_QUAD_VALID_READY__SHIFT 0x00000015 -#define CB_DEBUGBUS_1__FC_CLEAR_QUAD_VALID_READYB__SHIFT 0x00000016 -#define CB_DEBUGBUS_1__FC_CLEAR_QUAD_VALIDB_READY__SHIFT 0x00000017 -#define CB_DEBUGBUS_1__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_2 -#define CB_DEBUGBUS_2__FC_CLEAR_QUAD_VALIDB_READYB__SHIFT 0x00000000 -#define CB_DEBUGBUS_2__FC_QUAD_RESIDENCY_STALL__SHIFT 0x00000001 -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALID_READY__SHIFT 0x00000002 -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALID_READYB__SHIFT 0x00000003 -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALIDB_READY__SHIFT 0x00000004 -#define CB_DEBUGBUS_2__FC_CC_QUADFRAG_VALIDB_READYB__SHIFT 0x00000005 -#define CB_DEBUGBUS_2__FOP_IN_VALID_READY__SHIFT 0x00000006 -#define CB_DEBUGBUS_2__FOP_IN_VALID_READYB__SHIFT 0x00000007 -#define CB_DEBUGBUS_2__FOP_IN_VALIDB_READY__SHIFT 0x00000008 -#define CB_DEBUGBUS_2__FOP_IN_VALIDB_READYB__SHIFT 0x00000009 -#define CB_DEBUGBUS_2__FOP_FMASK_RAW_STALL__SHIFT 0x0000000a -#define CB_DEBUGBUS_2__FOP_FMASK_BYPASS_STALL__SHIFT 0x0000000b -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALID_READY__SHIFT 0x0000000c -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALID_READYB__SHIFT 0x0000000d -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALIDB_READY__SHIFT 0x0000000e -#define CB_DEBUGBUS_2__CC_IB_TB_FRAG_VALIDB_READYB__SHIFT 0x0000000f -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALID_READY__SHIFT 0x00000010 -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALID_READYB__SHIFT 0x00000011 -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALIDB_READY__SHIFT 0x00000012 -#define CB_DEBUGBUS_2__CC_IB_SR_FRAG_VALIDB_READYB__SHIFT 0x00000013 -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALID_READY__SHIFT 0x00000014 -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALID_READYB__SHIFT 0x00000015 -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY__SHIFT 0x00000016 -#define CB_DEBUGBUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB__SHIFT 0x00000017 -#define CB_DEBUGBUS_2__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_3 -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALID_READY__SHIFT 0x00000000 -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALID_READYB__SHIFT 0x00000001 -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY__SHIFT 0x00000002 -#define CB_DEBUGBUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB__SHIFT 0x00000003 -#define CB_DEBUGBUS_3__CC_BC_CS_FRAG_VALID__SHIFT 0x00000004 -#define CB_DEBUGBUS_3__CC_SF_FULL__SHIFT 0x00000005 -#define CB_DEBUGBUS_3__CC_RB_FULL__SHIFT 0x00000006 -#define CB_DEBUGBUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x00000007 -#define CB_DEBUGBUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x00000008 -#define CB_DEBUGBUS_3__CM_TQ_FULL__SHIFT 0x00000009 -#define CB_DEBUGBUS_3__CM_TILE_RESIDENCY_STALL__SHIFT 0x0000000a -#define CB_DEBUGBUS_3__LQUAD_NO_TILE__SHIFT 0x0000000b -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_R__SHIFT 0x0000000c -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR__SHIFT 0x0000000d -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR__SHIFT 0x0000000e -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR__SHIFT 0x0000000f -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR__SHIFT 0x00000010 -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR__SHIFT 0x00000011 -#define CB_DEBUGBUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR__SHIFT 0x00000012 -#define CB_DEBUGBUS_3__CM_CACHE_HIT__SHIFT 0x00000013 -#define CB_DEBUGBUS_3__CM_CACHE_TAG_MISS__SHIFT 0x00000014 -#define CB_DEBUGBUS_3__CM_CACHE_SECTOR_MISS__SHIFT 0x00000015 -#define CB_DEBUGBUS_3__CM_CACHE_REEVICTION_STALL__SHIFT 0x00000016 -#define CB_DEBUGBUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x00000017 -#define CB_DEBUGBUS_3__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_4 -#define CB_DEBUGBUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x00000000 -#define CB_DEBUGBUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x00000001 -#define CB_DEBUGBUS_4__CM_CACHE_READ_OUTPUT_STALL__SHIFT 0x00000002 -#define CB_DEBUGBUS_4__CM_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x00000003 -#define CB_DEBUGBUS_4__CM_CACHE_ACK_OUTPUT_STALL__SHIFT 0x00000004 -#define CB_DEBUGBUS_4__CM_CACHE_STALL__SHIFT 0x00000005 -#define CB_DEBUGBUS_4__FC_CACHE_HIT__SHIFT 0x00000006 -#define CB_DEBUGBUS_4__FC_CACHE_TAG_MISS__SHIFT 0x00000007 -#define CB_DEBUGBUS_4__FC_CACHE_SECTOR_MISS__SHIFT 0x00000008 -#define CB_DEBUGBUS_4__FC_CACHE_REEVICTION_STALL__SHIFT 0x00000009 -#define CB_DEBUGBUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x0000000a -#define CB_DEBUGBUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x0000000b -#define CB_DEBUGBUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x0000000c -#define CB_DEBUGBUS_4__FC_CACHE_READ_OUTPUT_STALL__SHIFT 0x0000000d -#define CB_DEBUGBUS_4__FC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x0000000e -#define CB_DEBUGBUS_4__FC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x0000000f -#define CB_DEBUGBUS_4__FC_CACHE_STALL__SHIFT 0x00000010 -#define CB_DEBUGBUS_4__CC_CACHE_HIT__SHIFT 0x00000011 -#define CB_DEBUGBUS_4__CC_CACHE_TAG_MISS__SHIFT 0x00000012 -#define CB_DEBUGBUS_4__CC_CACHE_SECTOR_MISS__SHIFT 0x00000013 -#define CB_DEBUGBUS_4__CC_CACHE_REEVICTION_STALL__SHIFT 0x00000014 -#define CB_DEBUGBUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x00000015 -#define CB_DEBUGBUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x00000016 -#define CB_DEBUGBUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x00000017 -#define CB_DEBUGBUS_4__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_5 -#define CB_DEBUGBUS_5__CC_CACHE_READ_OUTPUT_STALL__SHIFT 0x00000000 -#define CB_DEBUGBUS_5__CC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x00000001 -#define CB_DEBUGBUS_5__CC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x00000002 -#define CB_DEBUGBUS_5__CC_CACHE_STALL__SHIFT 0x00000003 -#define CB_DEBUGBUS_5__CC_CACHE_WA_TO_RMW_CONVERSION__SHIFT 0x00000004 -#define CB_DEBUGBUS_5__CM_CACHE_FLUSH__SHIFT 0x00000005 -#define CB_DEBUGBUS_5__CM_CACHE_TAGS_FLUSHED__SHIFT 0x00000006 -#define CB_DEBUGBUS_5__CM_CACHE_SECTORS_FLUSHED__SHIFT 0x00000007 -#define CB_DEBUGBUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x00000008 -#define CB_DEBUGBUS_5__FC_CACHE_FLUSH__SHIFT 0x00000009 -#define CB_DEBUGBUS_5__FC_CACHE_TAGS_FLUSHED__SHIFT 0x0000000a -#define CB_DEBUGBUS_5__FC_CACHE_SECTORS_FLUSHED__SHIFT 0x0000000b -#define CB_DEBUGBUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x0000000e -#define CB_DEBUGBUS_5__CC_CACHE_FLUSH__SHIFT 0x00000011 -#define CB_DEBUGBUS_5__CC_CACHE_TAGS_FLUSHED__SHIFT 0x00000012 -#define CB_DEBUGBUS_5__CC_CACHE_SECTORS_FLUSHED__SHIFT 0x00000013 - -// CB_DEBUGBUS_6 -#define CB_DEBUGBUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x00000000 -#define CB_DEBUGBUS_6__CM_MC_READ_REQUEST__SHIFT 0x00000003 -#define CB_DEBUGBUS_6__FC_MC_READ_REQUEST__SHIFT 0x00000004 -#define CB_DEBUGBUS_6__CC_MC_READ_REQUEST__SHIFT 0x00000005 -#define CB_DEBUGBUS_6__CM_MC_WRITE_REQUEST__SHIFT 0x00000006 -#define CB_DEBUGBUS_6__FC_MC_WRITE_REQUEST__SHIFT 0x00000007 -#define CB_DEBUGBUS_6__CC_MC_WRITE_REQUEST__SHIFT 0x00000008 -#define CB_DEBUGBUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x00000009 - -// CB_DEBUGBUS_7 -#define CB_DEBUGBUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x00000000 -#define CB_DEBUGBUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x0000000b - -// CB_DEBUGBUS_8 -#define CB_DEBUGBUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x00000000 -#define CB_DEBUGBUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x00000008 -#define CB_DEBUGBUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__SHIFT 0x00000013 -#define CB_DEBUGBUS_8__FC_SEQUENCER_FMASK_DECOMPRESS__SHIFT 0x00000014 -#define CB_DEBUGBUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR__SHIFT 0x00000015 -#define CB_DEBUGBUS_8__FC_SEQUENCER_CLEAR__SHIFT 0x00000016 - -// CB_DEBUGBUS_9 -#define CB_DEBUGBUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x00000000 -#define CB_DEBUGBUS_9__CC_SURFACE_SYNC__SHIFT 0x0000000a -#define CB_DEBUGBUS_9__TWO_PROBE_QUAD_FRAGMENT__SHIFT 0x0000000b -#define CB_DEBUGBUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT__SHIFT 0x0000000c -#define CB_DEBUGBUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SHIFT 0x0000000d -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_QUAD__SHIFT 0x0000000e -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_PIXEL__SHIFT 0x0000000f -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT__SHIFT 0x00000013 -#define CB_DEBUGBUS_9__DEBUG_BUS_DRAWN_TILE__SHIFT 0x00000014 -#define CB_DEBUGBUS_9__EVENT_ALL__SHIFT 0x00000015 -#define CB_DEBUGBUS_9__EVENT_CACHE_FLUSH_TS__SHIFT 0x00000016 -#define CB_DEBUGBUS_9__EVENT_CONTEXT_DONE__SHIFT 0x00000017 -#define CB_DEBUGBUS_9__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_10 -#define CB_DEBUGBUS_10__EVENT_CACHE_FLUSH__SHIFT 0x00000000 -#define CB_DEBUGBUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x00000001 -#define CB_DEBUGBUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT__SHIFT 0x00000002 -#define CB_DEBUGBUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x00000003 -#define CB_DEBUGBUS_10__EVENT_FLUSH_AND_INV_CB_META__SHIFT 0x00000004 -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XC__SHIFT 0x00000005 -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XD__SHIFT 0x00000006 -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XE__SHIFT 0x00000007 -#define CB_DEBUGBUS_10__CMASK_READ_DATA_0XF__SHIFT 0x00000008 -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XC__SHIFT 0x00000009 -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XD__SHIFT 0x0000000a -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XE__SHIFT 0x0000000b -#define CB_DEBUGBUS_10__CMASK_WRITE_DATA_0XF__SHIFT 0x0000000c -#define CB_DEBUGBUS_10__CORE_SCLK_VLD__SHIFT 0x0000000d -#define CB_DEBUGBUS_10__REG_SCLK0_VLD__SHIFT 0x0000000e -#define CB_DEBUGBUS_10__REG_SCLK1_VLD__SHIFT 0x0000000f -#define CB_DEBUGBUS_10__MERGE_TILE_ONLY_VALID_READY__SHIFT 0x00000010 -#define CB_DEBUGBUS_10__MERGE_TILE_ONLY_VALID_READYB__SHIFT 0x00000011 -#define CB_DEBUGBUS_10__FC_QUAD_RDLAT_FIFO_FULL__SHIFT 0x00000012 -#define CB_DEBUGBUS_10__FC_TILE_RDLAT_FIFO_FULL__SHIFT 0x00000013 -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SHIFT 0x00000014 -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x00000015 -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x00000016 -#define CB_DEBUGBUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x00000017 -#define CB_DEBUGBUS_10__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_11 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x00000000 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x00000001 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x00000002 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x00000003 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SHIFT 0x00000004 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SHIFT 0x00000005 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SHIFT 0x00000006 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SHIFT 0x00000007 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SHIFT 0x00000008 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SHIFT 0x00000009 -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SHIFT 0x0000000a -#define CB_DEBUGBUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SHIFT 0x0000000b -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_1_FRAGMENT__SHIFT 0x0000000c -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_2_FRAGMENTS__SHIFT 0x0000000d -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_3_FRAGMENTS__SHIFT 0x0000000e -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_4_FRAGMENTS__SHIFT 0x0000000f -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_5_FRAGMENTS__SHIFT 0x00000010 -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_6_FRAGMENTS__SHIFT 0x00000011 -#define CB_DEBUGBUS_11__FOP_QUAD_ADDED_7_FRAGMENTS__SHIFT 0x00000012 -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_1_FRAGMENT__SHIFT 0x00000013 -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS__SHIFT 0x00000014 -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS__SHIFT 0x00000015 -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS__SHIFT 0x00000016 -#define CB_DEBUGBUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS__SHIFT 0x00000017 -#define CB_DEBUGBUS_11__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_12 -#define CB_DEBUGBUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS__SHIFT 0x00000000 -#define CB_DEBUGBUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS__SHIFT 0x00000001 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0__SHIFT 0x00000002 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1__SHIFT 0x00000003 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2__SHIFT 0x00000004 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3__SHIFT 0x00000005 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4__SHIFT 0x00000006 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5__SHIFT 0x00000007 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6__SHIFT 0x00000008 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7__SHIFT 0x00000009 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0__SHIFT 0x0000000a -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1__SHIFT 0x0000000b -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2__SHIFT 0x0000000c -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3__SHIFT 0x0000000d -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4__SHIFT 0x0000000e -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5__SHIFT 0x0000000f -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6__SHIFT 0x00000010 -#define CB_DEBUGBUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7__SHIFT 0x00000011 -#define CB_DEBUGBUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST__SHIFT 0x00000012 -#define CB_DEBUGBUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS__SHIFT 0x00000013 -#define CB_DEBUGBUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS__SHIFT 0x00000014 -#define CB_DEBUGBUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT__SHIFT 0x00000015 -#define CB_DEBUGBUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID__SHIFT 0x00000016 -#define CB_DEBUGBUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK__SHIFT 0x00000017 -#define CB_DEBUGBUS_12__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_13 -#define CB_DEBUGBUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL__SHIFT 0x00000000 -#define CB_DEBUGBUS_13__FC_DOC_QTILE_CAM_MISS__SHIFT 0x00000001 -#define CB_DEBUGBUS_13__FC_DOC_QTILE_CAM_HIT__SHIFT 0x00000002 -#define CB_DEBUGBUS_13__FC_DOC_CLINE_CAM_MISS__SHIFT 0x00000003 -#define CB_DEBUGBUS_13__FC_DOC_CLINE_CAM_HIT__SHIFT 0x00000004 -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_1_SECTOR__SHIFT 0x00000005 -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_2_SECTORS__SHIFT 0x00000006 -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_3_SECTORS__SHIFT 0x00000007 -#define CB_DEBUGBUS_13__FC_DOC_OVERWROTE_4_SECTORS__SHIFT 0x00000008 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_HIT__SHIFT 0x00000009 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_TAG_MISS__SHIFT 0x0000000a -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_SECTOR_MISS__SHIFT 0x0000000b -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL__SHIFT 0x0000000c -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x0000000d -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x0000000e -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x0000000f -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL__SHIFT 0x00000010 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x00000011 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x00000012 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_STALL__SHIFT 0x00000013 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_FLUSH__SHIFT 0x00000014 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED__SHIFT 0x00000015 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x00000016 -#define CB_DEBUGBUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED__SHIFT 0x00000017 -#define CB_DEBUGBUS_13__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_14 -#define CB_DEBUGBUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x00000000 -#define CB_DEBUGBUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x0000000b -#define CB_DEBUGBUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT__SHIFT 0x00000016 -#define CB_DEBUGBUS_14__CC_PF_DCC_RDREQ_STALL__SHIFT 0x00000017 -#define CB_DEBUGBUS_14__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_15 -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1__SHIFT 0x00000000 -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1__SHIFT 0x00000003 -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2__SHIFT 0x00000005 -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3__SHIFT 0x00000007 -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1__SHIFT 0x00000009 -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2__SHIFT 0x0000000b -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3__SHIFT 0x0000000d -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4__SHIFT 0x0000000f -#define CB_DEBUGBUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5__SHIFT 0x00000011 - -// CB_DEBUGBUS_16 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1__SHIFT 0x00000000 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2__SHIFT 0x00000001 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3__SHIFT 0x00000002 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4__SHIFT 0x00000003 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5__SHIFT 0x00000004 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6__SHIFT 0x00000005 -#define CB_DEBUGBUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7__SHIFT 0x00000006 - -// CB_DEBUGBUS_17 -#define CB_DEBUGBUS_17__TILE_INTFC_BUSY__SHIFT 0x00000000 -#define CB_DEBUGBUS_17__MU_BUSY__SHIFT 0x00000001 -#define CB_DEBUGBUS_17__TQ_BUSY__SHIFT 0x00000002 -#define CB_DEBUGBUS_17__AC_BUSY__SHIFT 0x00000003 -#define CB_DEBUGBUS_17__CRW_BUSY__SHIFT 0x00000004 -#define CB_DEBUGBUS_17__CACHE_CTRL_BUSY__SHIFT 0x00000005 -#define CB_DEBUGBUS_17__MC_WR_PENDING__SHIFT 0x00000006 -#define CB_DEBUGBUS_17__FC_WR_PENDING__SHIFT 0x00000007 -#define CB_DEBUGBUS_17__FC_RD_PENDING__SHIFT 0x00000008 -#define CB_DEBUGBUS_17__EVICT_PENDING__SHIFT 0x00000009 -#define CB_DEBUGBUS_17__LAST_RD_ARB_WINNER__SHIFT 0x0000000a -#define CB_DEBUGBUS_17__MU_STATE__SHIFT 0x0000000b - -// CB_DEBUGBUS_18 -#define CB_DEBUGBUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x00000000 -#define CB_DEBUGBUS_18__FOP_BUSY__SHIFT 0x00000001 -#define CB_DEBUGBUS_18__CLEAR_BUSY__SHIFT 0x00000002 -#define CB_DEBUGBUS_18__LAT_BUSY__SHIFT 0x00000003 -#define CB_DEBUGBUS_18__CACHE_CTL_BUSY__SHIFT 0x00000004 -#define CB_DEBUGBUS_18__ADDR_BUSY__SHIFT 0x00000005 -#define CB_DEBUGBUS_18__MERGE_BUSY__SHIFT 0x00000006 -#define CB_DEBUGBUS_18__QUAD_BUSY__SHIFT 0x00000007 -#define CB_DEBUGBUS_18__TILE_BUSY__SHIFT 0x00000008 -#define CB_DEBUGBUS_18__DCC_BUSY__SHIFT 0x00000009 -#define CB_DEBUGBUS_18__DOC_BUSY__SHIFT 0x0000000a -#define CB_DEBUGBUS_18__DAG_BUSY__SHIFT 0x0000000b -#define CB_DEBUGBUS_18__DOC_STALL__SHIFT 0x0000000c -#define CB_DEBUGBUS_18__DOC_QT_CAM_FULL__SHIFT 0x0000000d -#define CB_DEBUGBUS_18__DOC_CL_CAM_FULL__SHIFT 0x0000000e -#define CB_DEBUGBUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0x0000000f -#define CB_DEBUGBUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x00000010 -#define CB_DEBUGBUS_18__DCS_READ_WINNER_LAST__SHIFT 0x00000011 -#define CB_DEBUGBUS_18__DCS_READ_EV_PENDING__SHIFT 0x00000012 -#define CB_DEBUGBUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x00000013 -#define CB_DEBUGBUS_18__DCS_READ_CC_PENDING__SHIFT 0x00000014 -#define CB_DEBUGBUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x00000015 - -// CB_DEBUGBUS_19 -#define CB_DEBUGBUS_19__SURF_SYNC_STATE__SHIFT 0x00000000 -#define CB_DEBUGBUS_19__SURF_SYNC_START__SHIFT 0x00000002 -#define CB_DEBUGBUS_19__SF_BUSY__SHIFT 0x00000003 -#define CB_DEBUGBUS_19__CS_BUSY__SHIFT 0x00000004 -#define CB_DEBUGBUS_19__RB_BUSY__SHIFT 0x00000005 -#define CB_DEBUGBUS_19__DS_BUSY__SHIFT 0x00000006 -#define CB_DEBUGBUS_19__TB_BUSY__SHIFT 0x00000007 -#define CB_DEBUGBUS_19__IB_BUSY__SHIFT 0x00000008 -#define CB_DEBUGBUS_19__DRR_BUSY__SHIFT 0x00000009 -#define CB_DEBUGBUS_19__DF_BUSY__SHIFT 0x0000000a -#define CB_DEBUGBUS_19__DD_BUSY__SHIFT 0x0000000b -#define CB_DEBUGBUS_19__DC_BUSY__SHIFT 0x0000000c -#define CB_DEBUGBUS_19__DK_BUSY__SHIFT 0x0000000d -#define CB_DEBUGBUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0x0000000e -#define CB_DEBUGBUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0x0000000f -#define CB_DEBUGBUS_19__DD_READY__SHIFT 0x00000010 -#define CB_DEBUGBUS_19__DC_FIFO_FULL__SHIFT 0x00000011 -#define CB_DEBUGBUS_19__DC_READY__SHIFT 0x00000012 - -// CB_DEBUGBUS_20 -#define CB_DEBUGBUS_20__MC_RDREQ_CREDITS__SHIFT 0x00000000 -#define CB_DEBUGBUS_20__MC_WRREQ_CREDITS__SHIFT 0x00000006 -#define CB_DEBUGBUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0x0000000c -#define CB_DEBUGBUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0x0000000d -#define CB_DEBUGBUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0x0000000e -#define CB_DEBUGBUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x00000010 -#define CB_DEBUGBUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x00000011 -#define CB_DEBUGBUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x00000012 -#define CB_DEBUGBUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x00000014 -#define CB_DEBUGBUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x00000015 -#define CB_DEBUGBUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x00000016 -#define CB_DEBUGBUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x00000017 -#define CB_DEBUGBUS_20__Reserved0__SHIFT 0x00000018 - -// CB_DEBUGBUS_21 -#define CB_DEBUGBUS_21__CM_BUSY__SHIFT 0x00000000 -#define CB_DEBUGBUS_21__FC_BUSY__SHIFT 0x00000001 -#define CB_DEBUGBUS_21__CC_BUSY__SHIFT 0x00000002 -#define CB_DEBUGBUS_21__BB_BUSY__SHIFT 0x00000003 -#define CB_DEBUGBUS_21__MA_BUSY__SHIFT 0x00000004 -#define CB_DEBUGBUS_21__CORE_SCLK_VLD__SHIFT 0x00000005 -#define CB_DEBUGBUS_21__REG_SCLK1_VLD__SHIFT 0x00000006 -#define CB_DEBUGBUS_21__REG_SCLK0_VLD__SHIFT 0x00000007 - -// CB_DEBUGBUS_22 -#define CB_DEBUGBUS_22__OUTSTANDING_MC_READS__SHIFT 0x00000000 -#define CB_DEBUGBUS_22__OUTSTANDING_MC_WRITES__SHIFT 0x0000000c -#define CB_DEBUGBUS_22__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG00_0 -#define PA_DEBUG00_0__clip_ga_bc_fifo_write__SHIFT 0x00000000 -#define PA_DEBUG00_0__su_clip_baryc_free__SHIFT 0x00000001 -#define PA_DEBUG00_0__clip_to_ga_fifo_write__SHIFT 0x00000003 -#define PA_DEBUG00_0__clip_to_ga_fifo_full__SHIFT 0x00000004 -#define PA_DEBUG00_0__primic_to_clprim_fifo_empty__SHIFT 0x00000005 -#define PA_DEBUG00_0__primic_to_clprim_fifo_full__SHIFT 0x00000006 -#define PA_DEBUG00_0__clip_to_outsm_fifo_empty__SHIFT 0x00000007 -#define PA_DEBUG00_0__clip_to_outsm_fifo_full__SHIFT 0x00000008 -#define PA_DEBUG00_0__vgt_to_clipp_fifo_empty__SHIFT 0x00000009 -#define PA_DEBUG00_0__vgt_to_clipp_fifo_full__SHIFT 0x0000000a -#define PA_DEBUG00_0__vgt_to_clips_fifo_empty__SHIFT 0x0000000b -#define PA_DEBUG00_0__vgt_to_clips_fifo_full__SHIFT 0x0000000c -#define PA_DEBUG00_0__clipcode_fifo_fifo_empty__SHIFT 0x0000000d -#define PA_DEBUG00_0__clipcode_fifo_full__SHIFT 0x0000000e -#define PA_DEBUG00_0__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000f -#define PA_DEBUG00_0__vte_out_clip_fifo_fifo_full__SHIFT 0x00000010 -#define PA_DEBUG00_0__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000011 -#define PA_DEBUG00_0__vte_out_orig_fifo_fifo_full__SHIFT 0x00000012 -#define PA_DEBUG00_0__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000013 -#define PA_DEBUG00_0__ccgen_to_clipcc_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG00_0__clip_to_outsm_fifo_write__SHIFT 0x00000015 -#define PA_DEBUG00_0__vte_out_orig_fifo_fifo_write__SHIFT 0x00000016 -#define PA_DEBUG00_0__vgt_to_clipp_fifo_write__SHIFT 0x00000017 -#define PA_DEBUG00_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG00_1 -#define PA_DEBUG00_1__vertex_fifo_entriesavailable__SHIFT 0x00000000 -#define PA_DEBUG00_1__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0x00000004 -#define PA_DEBUG00_1__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0x00000005 -#define PA_DEBUG00_1__available_positions__SHIFT 0x00000006 -#define PA_DEBUG00_1__current_state__SHIFT 0x0000000d -#define PA_DEBUG00_1__vertex_fifo_empty__SHIFT 0x0000000f -#define PA_DEBUG00_1__vertex_fifo_full__SHIFT 0x00000010 -#define PA_DEBUG00_1__sx0_receive_fifo_empty__SHIFT 0x00000011 -#define PA_DEBUG00_1__sx0_receive_fifo_full__SHIFT 0x00000012 -#define PA_DEBUG00_1__vgt_to_ccgen_fifo_empty__SHIFT 0x00000013 -#define PA_DEBUG00_1__vgt_to_ccgen_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG00_1__ccgen_to_clipcc_fifo_full__SHIFT 0x00000015 -#define PA_DEBUG00_1__sx0_receive_fifo_write__SHIFT 0x00000016 -#define PA_DEBUG00_1__ccgen_to_clipcc_write__SHIFT 0x00000017 -#define PA_DEBUG00_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG01_0 -#define PA_DEBUG01_0__clip_extra_bc_valid__SHIFT 0x00000000 -#define PA_DEBUG01_0__clip_vert_vte_valid__SHIFT 0x00000005 -#define PA_DEBUG01_0__clip_to_outsm_vertex_deallocate__SHIFT 0x00000006 -#define PA_DEBUG01_0__clip_to_outsm_deallocate_slot__SHIFT 0x00000009 -#define PA_DEBUG01_0__clip_to_outsm_null_primitive__SHIFT 0x0000000c -#define PA_DEBUG01_0__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x0000000d -#define PA_DEBUG01_0__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x0000000e -#define PA_DEBUG01_0__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x0000000f -#define PA_DEBUG01_0__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000010 -#define PA_DEBUG01_0__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000011 -#define PA_DEBUG01_0__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000012 -#define PA_DEBUG01_0__clip_ga_bc_fifo_write__SHIFT 0x00000014 -#define PA_DEBUG01_0__clip_to_ga_fifo_write__SHIFT 0x00000015 -#define PA_DEBUG01_0__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x00000016 -#define PA_DEBUG01_0__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017 -#define PA_DEBUG01_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG01_1 -#define PA_DEBUG01_1__ALWAYS_ZERO__SHIFT 0x00000000 -#define PA_DEBUG01_1__clip_extra_bc_valid__SHIFT 0x00000008 -#define PA_DEBUG01_1__clip_vert_vte_valid__SHIFT 0x0000000b -#define PA_DEBUG01_1__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e -#define PA_DEBUG01_1__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000010 -#define PA_DEBUG01_1__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000011 -#define PA_DEBUG01_1__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000012 -#define PA_DEBUG01_1__clip_ga_bc_fifo_write__SHIFT 0x00000014 -#define PA_DEBUG01_1__clip_to_ga_fifo_write__SHIFT 0x00000015 -#define PA_DEBUG01_1__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x00000016 -#define PA_DEBUG01_1__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017 -#define PA_DEBUG01_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG02_0 -#define PA_DEBUG02_0__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000000 -#define PA_DEBUG02_0__clip_to_outsm_vertex_store_indx_1__SHIFT 0x00000004 -#define PA_DEBUG02_0__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000008 -#define PA_DEBUG02_0__clip_to_clipga_extra_bc_coords__SHIFT 0x0000000c -#define PA_DEBUG02_0__clip_to_clipga_vte_naninf_kill__SHIFT 0x0000000d -#define PA_DEBUG02_0__clip_to_outsm_end_of_packet__SHIFT 0x0000000e -#define PA_DEBUG02_0__clip_to_outsm_first_prim_of_slot__SHIFT 0x0000000f -#define PA_DEBUG02_0__clip_to_outsm_clipped_prim__SHIFT 0x00000010 -#define PA_DEBUG02_0__clip_to_outsm_null_primitive__SHIFT 0x00000011 -#define PA_DEBUG02_0__clip_ga_bc_fifo_full__SHIFT 0x00000012 -#define PA_DEBUG02_0__clip_to_ga_fifo_full__SHIFT 0x00000013 -#define PA_DEBUG02_0__clip_ga_bc_fifo_write__SHIFT 0x00000014 -#define PA_DEBUG02_0__clip_to_ga_fifo_write__SHIFT 0x00000015 -#define PA_DEBUG02_0__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e -#define PA_DEBUG02_0__clip_to_outsm_fifo_empty__SHIFT 0x0000001f - -// PA_DEBUG02_1 -#define PA_DEBUG02_1__clip_extra_bc_valid__SHIFT 0x00000000 -#define PA_DEBUG02_1__clip_vert_vte_valid__SHIFT 0x00000003 -#define PA_DEBUG02_1__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006 -#define PA_DEBUG02_1__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008 -#define PA_DEBUG02_1__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c -#define PA_DEBUG02_1__clip_to_outsm_clipped_prim__SHIFT 0x00000010 -#define PA_DEBUG02_1__clip_to_outsm_null_primitive__SHIFT 0x00000011 -#define PA_DEBUG02_1__clip_ga_bc_fifo_full__SHIFT 0x00000012 -#define PA_DEBUG02_1__clip_to_ga_fifo_full__SHIFT 0x00000013 -#define PA_DEBUG02_1__clip_ga_bc_fifo_write__SHIFT 0x00000014 -#define PA_DEBUG02_1__clip_to_ga_fifo_write__SHIFT 0x00000015 -#define PA_DEBUG02_1__clip_to_outsm_fifo_advanceread__SHIFT 0x00000016 -#define PA_DEBUG02_1__clip_to_outsm_fifo_empty__SHIFT 0x00000017 -#define PA_DEBUG02_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG03_0 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x0000000c -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000000f -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG03_0__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG03_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG03_1 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG03_1__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG03_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG04_0 -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x00000003 -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000009 -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x0000000f -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG04_0__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG04_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG04_1 -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000010 -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG04_1__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG04_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG05_0 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_event_id__SHIFT 0x00000006 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x0000000c -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000000f -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG05_0__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG05_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG05_1 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG05_1__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG05_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG06_0 -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x00000003 -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000009 -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x0000000f -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG06_0__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG06_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG06_1 -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000010 -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG06_1__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG06_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG07_0 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_event_id__SHIFT 0x00000006 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x0000000c -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000000f -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG07_0__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG07_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG07_1 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG07_1__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG07_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG08_0 -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x00000003 -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000009 -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x0000000f -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG08_0__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG08_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG08_1 -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000010 -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG08_1__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG08_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG09_0 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_event_id__SHIFT 0x00000006 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x0000000c -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x0000000f -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG09_0__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG09_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG09_1 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000010 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000013 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x00000014 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG09_1__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG09_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG10_0 -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x00000003 -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000009 -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x0000000f -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x00000016 -#define PA_DEBUG10_0__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG10_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG10_1 -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000000 -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000010 -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_event__SHIFT 0x00000015 -#define PA_DEBUG10_1__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x00000016 - -// PA_DEBUG11_0 -#define PA_DEBUG11_0__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000000 -#define PA_DEBUG11_0__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000004 -#define PA_DEBUG11_0__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008 -#define PA_DEBUG11_0__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c -#define PA_DEBUG11_0__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000010 -#define PA_DEBUG11_0__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000011 -#define PA_DEBUG11_0__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x00000012 -#define PA_DEBUG11_0__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x00000013 -#define PA_DEBUG11_0__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014 -#define PA_DEBUG11_0__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 -#define PA_DEBUG11_0__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000016 -#define PA_DEBUG11_0__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000017 -#define PA_DEBUG11_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG11_1 -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_event__SHIFT 0x00000000 -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_event__SHIFT 0x00000001 -#define PA_DEBUG11_1__clipsm1_clip_to_clipga_event__SHIFT 0x00000002 -#define PA_DEBUG11_1__clipsm0_clip_to_clipga_event__SHIFT 0x00000003 -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004 -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005 -#define PA_DEBUG11_1__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006 -#define PA_DEBUG11_1__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007 -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008 -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c -#define PA_DEBUG11_1__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000010 -#define PA_DEBUG11_1__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000011 -#define PA_DEBUG11_1__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x00000012 -#define PA_DEBUG11_1__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x00000013 -#define PA_DEBUG11_1__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014 -#define PA_DEBUG11_1__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 -#define PA_DEBUG11_1__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000016 -#define PA_DEBUG11_1__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000017 -#define PA_DEBUG11_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG12_0 -#define PA_DEBUG12_0__clip_priority_available_vte_out_clip__SHIFT 0x00000000 -#define PA_DEBUG12_0__clip_priority_available_clip_verts__SHIFT 0x00000005 -#define PA_DEBUG12_0__clip_priority_seq_indx_out__SHIFT 0x0000000a -#define PA_DEBUG12_0__clip_priority_seq_indx_vert__SHIFT 0x0000000c -#define PA_DEBUG12_0__clip_priority_seq_indx_load__SHIFT 0x0000000e -#define PA_DEBUG12_0__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000010 -#define PA_DEBUG12_0__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000011 -#define PA_DEBUG12_0__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000012 -#define PA_DEBUG12_0__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x00000013 -#define PA_DEBUG12_0__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000014 -#define PA_DEBUG12_0__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x00000015 -#define PA_DEBUG12_0__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000016 -#define PA_DEBUG12_0__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG12_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG12_1 -#define PA_DEBUG12_1__ALWAYS_ZERO__SHIFT 0x00000000 -#define PA_DEBUG12_1__clip_priority_available_vte_out_clip__SHIFT 0x00000008 -#define PA_DEBUG12_1__clip_priority_available_clip_verts__SHIFT 0x0000000d -#define PA_DEBUG12_1__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000010 -#define PA_DEBUG12_1__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000011 -#define PA_DEBUG12_1__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000012 -#define PA_DEBUG12_1__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x00000013 -#define PA_DEBUG12_1__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000014 -#define PA_DEBUG12_1__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x00000015 -#define PA_DEBUG12_1__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000016 -#define PA_DEBUG12_1__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG12_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG13_0 -#define PA_DEBUG13_0__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000000 -#define PA_DEBUG13_0__clipcc_vertex_store_indx__SHIFT 0x00000004 -#define PA_DEBUG13_0__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000006 -#define PA_DEBUG13_0__clipcode_fifo_fifo_empty__SHIFT 0x00000007 -#define PA_DEBUG13_0__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000008 -#define PA_DEBUG13_0__clip_priority_seq_indx_out_cnt__SHIFT 0x00000009 -#define PA_DEBUG13_0__outsm_clr_rd_orig_vertices__SHIFT 0x0000000d -#define PA_DEBUG13_0__outsm_clr_rd_clipsm_wait__SHIFT 0x0000000f -#define PA_DEBUG13_0__outsm_clr_fifo_contents__SHIFT 0x00000010 -#define PA_DEBUG13_0__outsm_clr_fifo_full__SHIFT 0x00000015 -#define PA_DEBUG13_0__outsm_clr_fifo_advanceread__SHIFT 0x00000016 -#define PA_DEBUG13_0__outsm_clr_fifo_write__SHIFT 0x00000017 -#define PA_DEBUG13_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG13_1 -#define PA_DEBUG13_1__clprim_in_back_state_var_indx__SHIFT 0x00000000 -#define PA_DEBUG13_1__point_clip_candidate__SHIFT 0x00000003 -#define PA_DEBUG13_1__prim_nan_kill__SHIFT 0x00000004 -#define PA_DEBUG13_1__clprim_clip_primitive__SHIFT 0x00000005 -#define PA_DEBUG13_1__clprim_cull_primitive__SHIFT 0x00000006 -#define PA_DEBUG13_1__prim_back_valid__SHIFT 0x00000007 -#define PA_DEBUG13_1__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008 -#define PA_DEBUG13_1__clipcc_vertex_store_indx__SHIFT 0x0000000c -#define PA_DEBUG13_1__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e -#define PA_DEBUG13_1__clipcode_fifo_fifo_empty__SHIFT 0x0000000f -#define PA_DEBUG13_1__outsm_clr_fifo_contents__SHIFT 0x00000010 -#define PA_DEBUG13_1__outsm_clr_fifo_full__SHIFT 0x00000015 -#define PA_DEBUG13_1__outsm_clr_fifo_advanceread__SHIFT 0x00000016 -#define PA_DEBUG13_1__outsm_clr_fifo_write__SHIFT 0x00000017 -#define PA_DEBUG13_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG14_0 -#define PA_DEBUG14_0__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000000 -#define PA_DEBUG14_0__clprim_in_back_vertex_store_indx_0__SHIFT 0x00000004 -#define PA_DEBUG14_0__outputclprimtoclip_null_primitive__SHIFT 0x0000000a -#define PA_DEBUG14_0__clprim_in_back_end_of_packet__SHIFT 0x0000000b -#define PA_DEBUG14_0__clprim_in_back_first_prim_of_slot__SHIFT 0x0000000c -#define PA_DEBUG14_0__clprim_in_back_deallocate_slot__SHIFT 0x0000000d -#define PA_DEBUG14_0__clprim_in_back_event_id__SHIFT 0x00000010 -#define PA_DEBUG14_0__clprim_in_back_event__SHIFT 0x00000016 -#define PA_DEBUG14_0__prim_back_valid__SHIFT 0x00000017 -#define PA_DEBUG14_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG14_1 -#define PA_DEBUG14_1__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000 -#define PA_DEBUG14_1__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006 -#define PA_DEBUG14_1__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c -#define PA_DEBUG14_1__clprim_in_back_event_id__SHIFT 0x00000010 -#define PA_DEBUG14_1__clprim_in_back_event__SHIFT 0x00000016 -#define PA_DEBUG14_1__prim_back_valid__SHIFT 0x00000017 -#define PA_DEBUG14_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG15_0 -#define PA_DEBUG15_0__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 -#define PA_DEBUG15_0__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000008 -#define PA_DEBUG15_0__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x0000000d -#define PA_DEBUG15_0__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x00000012 -#define PA_DEBUG15_0__primic_to_clprim_valid__SHIFT 0x00000017 -#define PA_DEBUG15_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG15_1 -#define PA_DEBUG15_1__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 -#define PA_DEBUG15_1__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000010 -#define PA_DEBUG15_1__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x00000012 -#define PA_DEBUG15_1__primic_to_clprim_valid__SHIFT 0x00000017 -#define PA_DEBUG15_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG16_0 -#define PA_DEBUG16_0__sm0_clip_vert_cnt__SHIFT 0x00000000 -#define PA_DEBUG16_0__sm0_vertex_clip_cnt__SHIFT 0x00000005 -#define PA_DEBUG16_0__sm0_inv_to_clip_data_valid_1__SHIFT 0x0000000a -#define PA_DEBUG16_0__sm0_inv_to_clip_data_valid_0__SHIFT 0x0000000b -#define PA_DEBUG16_0__sm0_current_state__SHIFT 0x0000000c -#define PA_DEBUG16_0__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG16_0__sm0_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG16_0__sm0_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG16_0__sm0_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG16_0__sm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG16_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG16_1 -#define PA_DEBUG16_1__sm0_prim_end_state__SHIFT 0x00000000 -#define PA_DEBUG16_1__sm0_ps_expand__SHIFT 0x00000007 -#define PA_DEBUG16_1__sm0_clip_vert_cnt__SHIFT 0x00000008 -#define PA_DEBUG16_1__sm0_vertex_clip_cnt__SHIFT 0x0000000d -#define PA_DEBUG16_1__sm0_current_state__SHIFT 0x00000010 -#define PA_DEBUG16_1__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG16_1__sm0_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG16_1__sm0_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG16_1__sm0_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG16_1__sm0_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG16_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG17_0 -#define PA_DEBUG17_0__sm1_clip_vert_cnt__SHIFT 0x00000000 -#define PA_DEBUG17_0__sm1_vertex_clip_cnt__SHIFT 0x00000005 -#define PA_DEBUG17_0__sm1_inv_to_clip_data_valid_1__SHIFT 0x0000000a -#define PA_DEBUG17_0__sm1_inv_to_clip_data_valid_0__SHIFT 0x0000000b -#define PA_DEBUG17_0__sm1_current_state__SHIFT 0x0000000c -#define PA_DEBUG17_0__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG17_0__sm1_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG17_0__sm1_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG17_0__sm1_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG17_0__sm1_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG17_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG17_1 -#define PA_DEBUG17_1__sm1_prim_end_state__SHIFT 0x00000000 -#define PA_DEBUG17_1__sm1_ps_expand__SHIFT 0x00000007 -#define PA_DEBUG17_1__sm1_clip_vert_cnt__SHIFT 0x00000008 -#define PA_DEBUG17_1__sm1_vertex_clip_cnt__SHIFT 0x0000000d -#define PA_DEBUG17_1__sm1_current_state__SHIFT 0x00000010 -#define PA_DEBUG17_1__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG17_1__sm1_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG17_1__sm1_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG17_1__sm1_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG17_1__sm1_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG17_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG18_0 -#define PA_DEBUG18_0__sm2_clip_vert_cnt__SHIFT 0x00000000 -#define PA_DEBUG18_0__sm2_vertex_clip_cnt__SHIFT 0x00000005 -#define PA_DEBUG18_0__sm2_inv_to_clip_data_valid_1__SHIFT 0x0000000a -#define PA_DEBUG18_0__sm2_inv_to_clip_data_valid_0__SHIFT 0x0000000b -#define PA_DEBUG18_0__sm2_current_state__SHIFT 0x0000000c -#define PA_DEBUG18_0__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG18_0__sm2_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG18_0__sm2_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG18_0__sm2_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG18_0__sm2_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG18_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG18_1 -#define PA_DEBUG18_1__sm2_prim_end_state__SHIFT 0x00000000 -#define PA_DEBUG18_1__sm2_ps_expand__SHIFT 0x00000007 -#define PA_DEBUG18_1__sm2_clip_vert_cnt__SHIFT 0x00000008 -#define PA_DEBUG18_1__sm2_vertex_clip_cnt__SHIFT 0x0000000d -#define PA_DEBUG18_1__sm2_current_state__SHIFT 0x00000010 -#define PA_DEBUG18_1__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG18_1__sm2_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG18_1__sm2_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG18_1__sm2_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG18_1__sm2_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG18_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG19_0 -#define PA_DEBUG19_0__sm3_clip_vert_cnt__SHIFT 0x00000000 -#define PA_DEBUG19_0__sm3_vertex_clip_cnt__SHIFT 0x00000005 -#define PA_DEBUG19_0__sm3_inv_to_clip_data_valid_1__SHIFT 0x0000000a -#define PA_DEBUG19_0__sm3_inv_to_clip_data_valid_0__SHIFT 0x0000000b -#define PA_DEBUG19_0__sm3_current_state__SHIFT 0x0000000c -#define PA_DEBUG19_0__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG19_0__sm3_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG19_0__sm3_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG19_0__sm3_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG19_0__sm3_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG19_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG19_1 -#define PA_DEBUG19_1__sm3_prim_end_state__SHIFT 0x00000000 -#define PA_DEBUG19_1__sm3_ps_expand__SHIFT 0x00000007 -#define PA_DEBUG19_1__sm3_clip_vert_cnt__SHIFT 0x00000008 -#define PA_DEBUG19_1__sm3_vertex_clip_cnt__SHIFT 0x0000000d -#define PA_DEBUG19_1__sm3_current_state__SHIFT 0x00000010 -#define PA_DEBUG19_1__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x00000013 -#define PA_DEBUG19_1__sm3_clip_to_outsm_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG19_1__sm3_highest_priority_seq__SHIFT 0x00000015 -#define PA_DEBUG19_1__sm3_outputcliptoga_0__SHIFT 0x00000016 -#define PA_DEBUG19_1__sm3_clprim_to_clip_prim_valid__SHIFT 0x00000017 -#define PA_DEBUG19_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG20_0 -#define PA_DEBUG20_0__point_address__SHIFT 0x00000000 -#define PA_DEBUG20_0__sx_pending_rd_state_var_indx__SHIFT 0x00000001 -#define PA_DEBUG20_0__sx_pending_rd_req_mask__SHIFT 0x00000004 -#define PA_DEBUG20_0__sx_pending_rd_pci__SHIFT 0x00000008 -#define PA_DEBUG20_0__sx_pending_rd_aux_sel__SHIFT 0x00000012 -#define PA_DEBUG20_0__sx_pending_rd_sp_id__SHIFT 0x00000014 -#define PA_DEBUG20_0__sx_pending_rd_aux_inc__SHIFT 0x00000016 -#define PA_DEBUG20_0__sx_pending_rd_advance__SHIFT 0x00000017 -#define PA_DEBUG20_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG20_1 -#define PA_DEBUG20_1__position_address__SHIFT 0x00000000 -#define PA_DEBUG20_1__point_address__SHIFT 0x00000006 -#define PA_DEBUG20_1__sx_pending_rd_state_var_indx__SHIFT 0x00000009 -#define PA_DEBUG20_1__sx_pending_rd_req_mask__SHIFT 0x0000000c -#define PA_DEBUG20_1__sx_pending_rd_pci__SHIFT 0x00000010 -#define PA_DEBUG20_1__sx_pending_rd_aux_sel__SHIFT 0x00000012 -#define PA_DEBUG20_1__sx_pending_rd_sp_id__SHIFT 0x00000014 -#define PA_DEBUG20_1__sx_pending_rd_aux_inc__SHIFT 0x00000016 -#define PA_DEBUG20_1__sx_pending_rd_advance__SHIFT 0x00000017 -#define PA_DEBUG20_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG21_0 -#define PA_DEBUG21_0__sx_receive_indx__SHIFT 0x00000000 -#define PA_DEBUG21_0__sx_pending_fifo_contents__SHIFT 0x00000002 -#define PA_DEBUG21_0__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x00000007 -#define PA_DEBUG21_0__statevar_bits_disable_sp__SHIFT 0x00000008 -#define PA_DEBUG21_0__aux_sel__SHIFT 0x0000000c -#define PA_DEBUG21_0__sx_to_pa_empty_1__SHIFT 0x0000000e -#define PA_DEBUG21_0__sx_to_pa_empty_0__SHIFT 0x0000000f -#define PA_DEBUG21_0__pasx_req_cnt_1__SHIFT 0x00000010 -#define PA_DEBUG21_0__pasx_req_cnt_0__SHIFT 0x00000014 -#define PA_DEBUG21_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG21_1 -#define PA_DEBUG21_1__available_positions__SHIFT 0x00000000 -#define PA_DEBUG21_1__sx_receive_indx__SHIFT 0x00000007 -#define PA_DEBUG21_1__sx_pending_fifo_contents__SHIFT 0x0000000a -#define PA_DEBUG21_1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x0000000f -#define PA_DEBUG21_1__pasx_req_cnt_1__SHIFT 0x00000010 -#define PA_DEBUG21_1__pasx_req_cnt_0__SHIFT 0x00000014 -#define PA_DEBUG21_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG22_0 -#define PA_DEBUG22_0__su_aux__SHIFT 0x00000000 -#define PA_DEBUG22_0__sx_request_indx__SHIFT 0x00000001 -#define PA_DEBUG22_0__req_active_verts_loaded__SHIFT 0x00000007 -#define PA_DEBUG22_0__req_active_verts__SHIFT 0x00000008 -#define PA_DEBUG22_0__vgt_to_ccgen_state_var_indx__SHIFT 0x0000000f -#define PA_DEBUG22_0__vgt_to_ccgen_active_verts__SHIFT 0x00000012 -#define PA_DEBUG22_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG22_1 -#define PA_DEBUG22_1__param_cache_base__SHIFT 0x00000000 -#define PA_DEBUG22_1__su_aux__SHIFT 0x00000007 -#define PA_DEBUG22_1__sx_request_indx__SHIFT 0x00000009 -#define PA_DEBUG22_1__req_active_verts_loaded__SHIFT 0x0000000f -#define PA_DEBUG22_1__vgt_to_ccgen_state_var_indx__SHIFT 0x00000010 -#define PA_DEBUG22_1__vgt_to_ccgen_active_verts__SHIFT 0x00000012 -#define PA_DEBUG22_1__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG23_0 -#define PA_DEBUG23_0__su_baryc_cntl_state__SHIFT 0x00000000 -#define PA_DEBUG23_0__su_cntl_state__SHIFT 0x00000002 -#define PA_DEBUG23_0__ALWAYS_ZERO__SHIFT 0x00000006 -#define PA_DEBUG23_0__pmode_state__SHIFT 0x00000008 -#define PA_DEBUG23_0__ge_stallb__SHIFT 0x0000000e -#define PA_DEBUG23_0__geom_enable__SHIFT 0x0000000f -#define PA_DEBUG23_0__su_clip_baryc_free__SHIFT 0x00000010 -#define PA_DEBUG23_0__su_clip_rtr__SHIFT 0x00000012 -#define PA_DEBUG23_0__pfifo_busy__SHIFT 0x00000013 -#define PA_DEBUG23_0__su_cntl_busy__SHIFT 0x00000014 -#define PA_DEBUG23_0__geom_busy__SHIFT 0x00000015 -#define PA_DEBUG23_0__event_id_gated_1to0__SHIFT 0x00000016 -#define PA_DEBUG23_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG24_0 -#define PA_DEBUG24_0__event_id_gated_5to2__SHIFT 0x00000000 -#define PA_DEBUG24_0__event_gated__SHIFT 0x00000004 -#define PA_DEBUG24_0__pmode_prim_gated__SHIFT 0x00000005 -#define PA_DEBUG24_0__su_dyn_sclk_vld__SHIFT 0x00000006 -#define PA_DEBUG24_0__cl_dyn_sclk_vld__SHIFT 0x00000007 -#define PA_DEBUG24_0__y_sort0_gated_23_8__SHIFT 0x00000008 -#define PA_DEBUG24_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG25_0 -#define PA_DEBUG25_0__x_sort0_gated_23_8__SHIFT 0x00000000 -#define PA_DEBUG25_0__y_sort1_gated_15_8__SHIFT 0x00000010 -#define PA_DEBUG25_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG26_0 -#define PA_DEBUG26_0__y_sort1_gated_23_16__SHIFT 0x00000000 -#define PA_DEBUG26_0__x_sort1_gated_23_8__SHIFT 0x00000008 -#define PA_DEBUG26_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG27_0 -#define PA_DEBUG27_0__y_sort2_gated_23_8__SHIFT 0x00000000 -#define PA_DEBUG27_0__x_sort2_gated_15_8__SHIFT 0x00000010 -#define PA_DEBUG27_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG28_0 -#define PA_DEBUG28_0__x_sort2_gated_23to16__SHIFT 0x00000000 -#define PA_DEBUG28_0__attr_indx_sort0_gated__SHIFT 0x00000008 -#define PA_DEBUG28_0__null_prim_gated__SHIFT 0x00000016 -#define PA_DEBUG28_0__backfacing_gated__SHIFT 0x00000017 -#define PA_DEBUG28_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG29_0 -#define PA_DEBUG29_0__st_indx_gated__SHIFT 0x00000000 -#define PA_DEBUG29_0__clipped_gated__SHIFT 0x00000003 -#define PA_DEBUG29_0__dealloc_slot_gated__SHIFT 0x00000004 -#define PA_DEBUG29_0__xmajor_gated__SHIFT 0x00000007 -#define PA_DEBUG29_0__diamond_rule_gated__SHIFT 0x00000008 -#define PA_DEBUG29_0__type_gated__SHIFT 0x0000000a -#define PA_DEBUG29_0__fpov_gated__SHIFT 0x0000000d -#define PA_DEBUG29_0__eop_gated__SHIFT 0x0000000f -#define PA_DEBUG29_0__attr_indx_sort2_gated_7to0__SHIFT 0x00000010 -#define PA_DEBUG29_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG30_0 -#define PA_DEBUG30_0__attr_indx_sort2_gated_13to8__SHIFT 0x00000000 -#define PA_DEBUG30_0__attr_indx_sort1_gated__SHIFT 0x00000006 -#define PA_DEBUG30_0__provoking_vtx_gated__SHIFT 0x00000014 -#define PA_DEBUG30_0__valid_prim_gated__SHIFT 0x00000016 -#define PA_DEBUG30_0__pa_reg_sclk_vld__SHIFT 0x00000017 -#define PA_DEBUG30_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG31_0 -#define PA_DEBUG31_0__VGT_PA_clipv_send_q__SHIFT 0x00000000 -#define PA_DEBUG31_0__VGT_PA_clips_send_q__SHIFT 0x00000001 -#define PA_DEBUG31_0__VGT_PA_clipp_send_q__SHIFT 0x00000002 -#define PA_DEBUG31_0__PA0_SC0_send_q__SHIFT 0x00000003 -#define PA_DEBUG31_0__PA0_SC1_send_q__SHIFT 0x00000004 -#define PA_DEBUG31_0__PA_PA_pascDataOut_send0_q__SHIFT 0x00000005 -#define PA_DEBUG31_0__PA_PA_pascDataOut_send1_q__SHIFT 0x00000006 -#define PA_DEBUG31_0__vte_busy__SHIFT 0x00000007 -#define PA_DEBUG31_0__clipper_busy__SHIFT 0x00000008 -#define PA_DEBUG31_0__su_busy__SHIFT 0x00000009 -#define PA_DEBUG31_0__su_busy_debug_hold_busy__SHIFT 0x0000000a -#define PA_DEBUG31_0__su_busy_debug_valid_prim_gated__SHIFT 0x0000000b -#define PA_DEBUG31_0__su_busy_debug_su_cntl_busy__SHIFT 0x0000000c -#define PA_DEBUG31_0__su_busy_debug_geom_busy__SHIFT 0x0000000d -#define PA_DEBUG31_0__su_busy_debug_pfifo_busy__SHIFT 0x0000000e -#define PA_DEBUG31_0__vte_busy_debug_veu_busy__SHIFT 0x0000000f -#define PA_DEBUG31_0__vte_busy_debug_ib_busy__SHIFT 0x00000010 -#define PA_DEBUG31_0__clipper_busy_debug_outsm_clr_fifo_not_empty__SHIFT 0x00000011 -#define PA_DEBUG31_0__clipper_busy_debug_clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000012 -#define PA_DEBUG31_0__clipper_busy_debug_clipsm2_clprim_to_clip_prim_valid__SHIFT 0x00000013 -#define PA_DEBUG31_0__clipper_busy_debug_clipsm1_clprim_to_clip_prim_valid__SHIFT 0x00000014 -#define PA_DEBUG31_0__clipper_busy_debug_clipsm0_clprim_to_clip_prim_valid__SHIFT 0x00000015 -#define PA_DEBUG31_0__clipper_busy_debug_primic_to_clprim_valid__SHIFT 0x00000016 -#define PA_DEBUG31_0__clipper_busy_debug_clipsm_clip_to_outsm_fifo_write__SHIFT 0x00000017 -#define PA_DEBUG31_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG32_0 -#define PA_DEBUG32_0__clipper_busy_debug_clipsm3_current_state_not_empty__SHIFT 0x00000000 -#define PA_DEBUG32_0__clipper_busy_debug_clipsm2_current_state_not_empty__SHIFT 0x00000001 -#define PA_DEBUG32_0__clipper_busy_debug_clipsm1_current_state_not_empty__SHIFT 0x00000002 -#define PA_DEBUG32_0__clipper_busy_debug_clipsm0_current_state_not_empty__SHIFT 0x00000003 -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_ga_bc_busy__SHIFT 0x00000004 -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_ga_fifo_write__SHIFT 0x00000005 -#define PA_DEBUG32_0__clipper_busy_debug_prim_back_valid__SHIFT 0x00000006 -#define PA_DEBUG32_0__clipper_busy_debug_next_prim_back_valid__SHIFT 0x00000007 -#define PA_DEBUG32_0__clipper_busy_debug_primic_to_clprim_fifo_not_empty__SHIFT 0x00000008 -#define PA_DEBUG32_0__clipper_busy_debug_primic_to_clprim_fifo_write__SHIFT 0x00000009 -#define PA_DEBUG32_0__clipper_busy_debug_sx_pending_fifo_not_empty__SHIFT 0x0000000a -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_outsm_fifo_busy__SHIFT 0x0000000b -#define PA_DEBUG32_0__clipper_busy_debug_clip_to_outsm_fifo_write__SHIFT 0x0000000c -#define PA_DEBUG32_0__clipper_busy_debug_clipcode_fifo_fifo_busy__SHIFT 0x0000000d -#define PA_DEBUG32_0__clipper_busy_debug_clipcode_fifo_fifo_write__SHIFT 0x0000000e -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_clip_fifo_fifo_busy__SHIFT 0x0000000f -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_clip_fifo_fifo_write__SHIFT 0x00000010 -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_orig_fifo_fifo_busy__SHIFT 0x00000011 -#define PA_DEBUG32_0__clipper_busy_debug_vte_out_orig_fifo_fifo_write__SHIFT 0x00000012 -#define PA_DEBUG32_0__clipper_busy_debug_ccgen_to_clipcc_fifo_busy__SHIFT 0x00000013 -#define PA_DEBUG32_0__clipper_busy_debug_ccgen_to_clipcc_fifo_write__SHIFT 0x00000014 -#define PA_DEBUG32_0__clipper_busy_debug_vgt_to_clipp_fifo_busy__SHIFT 0x00000015 -#define PA_DEBUG32_0__clipper_busy_debug_vgt_to_clipp_fifo_write__SHIFT 0x00000016 -#define PA_DEBUG32_0__clipper_busy_debug_vgt_to_clips_fifo_busy__SHIFT 0x00000017 -#define PA_DEBUG32_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG33_0 -#define PA_DEBUG33_0__clipper_busy_debug_vgt_to_clips_fifo_write__SHIFT 0x00000000 -#define PA_DEBUG33_0__PA_SE3SC_freeze__SHIFT 0x00000004 -#define PA_DEBUG33_0__Reserved0__SHIFT 0x00000005 - -// PA_DEBUG34_0 -#define PA_DEBUG34_0__ngg_sideband_utc_driver_tag__SHIFT 0x00000000 -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rtr_out__SHIFT 0x00000008 -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rts_out__SHIFT 0x00000009 -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rts_in__SHIFT 0x0000000a -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_rtr_in__SHIFT 0x0000000b -#define PA_DEBUG34_0__ngg_sideband_utc_driver_client_send_reg_busy__SHIFT 0x0000000c -#define PA_DEBUG34_0__ngg_sideband_utc_driver_outcl1_send_valid__SHIFT 0x0000000d -#define PA_DEBUG34_0__ngg_sideband_utc_driver_iutcl1_send_ready__SHIFT 0x0000000e -#define PA_DEBUG34_0__ngg_sideband_utc_driver_iclient_send_valid__SHIFT 0x0000000f -#define PA_DEBUG34_0__ngg_sideband_utc_driver_oclient_send_ready__SHIFT 0x00000010 -#define PA_DEBUG34_0__ngg_sideband_utc_driver_outcl1_send_vmid__SHIFT 0x00000011 -#define PA_DEBUG34_0__ngg_sideband_utc_driver_outcl1_send_type__SHIFT 0x00000015 -#define PA_DEBUG34_0__Reserved0__SHIFT 0x00000017 - -// PA_DEBUG34_1 -#define PA_DEBUG34_1__ngg_utcl1_debug00__SHIFT 0x00000000 - -// PA_DEBUG35_0 -#define PA_DEBUG35_0__ngg_index_utc_driver_tag__SHIFT 0x00000000 -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_read__SHIFT 0x00000008 -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_empty__SHIFT 0x00000009 -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_write__SHIFT 0x0000000a -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_full__SHIFT 0x0000000b -#define PA_DEBUG35_0__ngg_index_utc_driver_client_send_fifo_busy__SHIFT 0x0000000c -#define PA_DEBUG35_0__ngg_index_utc_driver_outcl1_send_valid__SHIFT 0x0000000d -#define PA_DEBUG35_0__ngg_index_utc_driver_iutcl1_send_ready__SHIFT 0x0000000e -#define PA_DEBUG35_0__ngg_index_utc_driver_iclient_send_valid__SHIFT 0x0000000f -#define PA_DEBUG35_0__ngg_index_utc_driver_oclient_send_ready__SHIFT 0x00000010 -#define PA_DEBUG35_0__ngg_index_utc_driver_outcl1_send_vmid__SHIFT 0x00000011 -#define PA_DEBUG35_0__ngg_index_utc_driver_outcl1_send_type__SHIFT 0x00000015 -#define PA_DEBUG35_0__Reserved0__SHIFT 0x00000017 - -// PA_DEBUG35_1 -#define PA_DEBUG35_1__ngg_utcl1_debug01__SHIFT 0x00000000 - -// PA_DEBUG36_0 -#define PA_DEBUG36_0__ngg_position_utc_driver_tag__SHIFT 0x00000000 -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_read__SHIFT 0x00000008 -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_empty__SHIFT 0x00000009 -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_write__SHIFT 0x0000000a -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_full__SHIFT 0x0000000b -#define PA_DEBUG36_0__ngg_position_utc_driver_client_send_fifo_busy__SHIFT 0x0000000c -#define PA_DEBUG36_0__ngg_position_utc_driver_outcl1_send_valid__SHIFT 0x0000000d -#define PA_DEBUG36_0__ngg_position_utc_driver_iutcl1_send_ready__SHIFT 0x0000000e -#define PA_DEBUG36_0__ngg_position_utc_driver_iclient_send_valid__SHIFT 0x0000000f -#define PA_DEBUG36_0__ngg_position_utc_driver_oclient_send_ready__SHIFT 0x00000010 -#define PA_DEBUG36_0__ngg_position_utc_driver_outcl1_send_vmid__SHIFT 0x00000011 -#define PA_DEBUG36_0__ngg_position_utc_driver_outcl1_send_type__SHIFT 0x00000015 -#define PA_DEBUG36_0__Reserved0__SHIFT 0x00000017 - -// PA_DEBUG36_1 -#define PA_DEBUG36_1__ngg_utcl1_debug02__SHIFT 0x00000000 - -// PA_DEBUG37_0 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_busy__SHIFT 0x00000000 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rtr_out__SHIFT 0x00000001 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rts_out__SHIFT 0x00000002 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rtr_in__SHIFT 0x00000003 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_rts_in__SHIFT 0x00000004 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_drop__SHIFT 0x00000005 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_perf_cntr_en__SHIFT \ - 0x00000006 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_space__SHIFT 0x00000007 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_rd_tmz_encr__SHIFT \ - 0x00000008 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_io__SHIFT 0x00000009 -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_snoop__SHIFT 0x0000000a -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_mtype__SHIFT 0x0000000b -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_vmid__SHIFT 0x0000000e -#define PA_DEBUG37_0__ngg_debug_sideband_utc_receiver_output_reg_dataout_tag__SHIFT 0x00000012 -#define PA_DEBUG37_0__Reserved0__SHIFT 0x0000001a - -// PA_DEBUG37_1 -#define PA_DEBUG37_1__ngg_utcl1_debug03__SHIFT 0x00000000 - -// PA_DEBUG38_0 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_busy__SHIFT 0x00000000 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rtr_out__SHIFT 0x00000001 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rts_out__SHIFT 0x00000002 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rtr_in__SHIFT 0x00000003 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_rts_in__SHIFT 0x00000004 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_drop__SHIFT 0x00000005 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_perf_cntr_en__SHIFT 0x00000006 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_space__SHIFT 0x00000007 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_rd_tmz_encr__SHIFT 0x00000008 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_io__SHIFT 0x00000009 -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_snoop__SHIFT 0x0000000a -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_mtype__SHIFT 0x0000000b -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_vmid__SHIFT 0x0000000e -#define PA_DEBUG38_0__ngg_debug_index_utc_receiver_output_reg_dataout_tag__SHIFT 0x00000012 -#define PA_DEBUG38_0__Reserved0__SHIFT 0x0000001a - -// PA_DEBUG38_1 -#define PA_DEBUG38_1__ngg_utcl1_debug04__SHIFT 0x00000000 - -// PA_DEBUG39_0 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_busy__SHIFT 0x00000000 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rtr_out__SHIFT 0x00000001 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rts_out__SHIFT 0x00000002 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rtr_in__SHIFT 0x00000003 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_rts_in__SHIFT 0x00000004 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_drop__SHIFT 0x00000005 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_perf_cntr_en__SHIFT \ - 0x00000006 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_space__SHIFT 0x00000007 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_rd_tmz_encr__SHIFT \ - 0x00000008 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_io__SHIFT 0x00000009 -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_snoop__SHIFT 0x0000000a -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_mtype__SHIFT 0x0000000b -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_vmid__SHIFT 0x0000000e -#define PA_DEBUG39_0__ngg_debug_position_utc_receiver_output_reg_dataout_tag__SHIFT 0x00000012 -#define PA_DEBUG39_0__Reserved0__SHIFT 0x0000001a - -// PA_DEBUG39_1 -#define PA_DEBUG39_1__ngg_utcl1_debug05__SHIFT 0x00000000 - -// PA_DEBUG40_0 -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_current_client_count__SHIFT 0x00000000 -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_istream0_client_tag__SHIFT 0x00000016 -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_ostream0_client_rtr__SHIFT 0x0000001e -#define PA_DEBUG40_0__ngg_debug_tc_request_arbiter_istream0_client_rts__SHIFT 0x0000001f - -// PA_DEBUG40_1 -#define PA_DEBUG40_1__ngg_utcl1_debug06__SHIFT 0x00000000 - -// PA_DEBUG41_0 -#define PA_DEBUG41_0__ngg_debug_tc_if_credit_count_overflow__SHIFT 0x00000000 -#define PA_DEBUG41_0__ngg_debug_tc_if_credit_count_underflow__SHIFT 0x00000001 -#define PA_DEBUG41_0__ngg_debug_tc_if_credits__SHIFT 0x00000002 -#define PA_DEBUG41_0__ngg_debug_tc_if_obusy__SHIFT 0x00000007 -#define PA_DEBUG41_0__ngg_debug_tc_if_ooutstanding_tc_requests_exist__SHIFT 0x00000008 -#define PA_DEBUG41_0__ngg_debug_tc_if_irdret_vld__SHIFT 0x00000009 -#define PA_DEBUG41_0__ngg_debug_tc_if_irdreq_free__SHIFT 0x0000000a -#define PA_DEBUG41_0__ngg_debug_tc_if_ordreq_send__SHIFT 0x0000000b -#define PA_DEBUG41_0__ngg_debug_tc_if_ordreq_clken__SHIFT 0x0000000c -#define PA_DEBUG41_0__ngg_debug_tc_if_ortr_in__SHIFT 0x0000000d -#define PA_DEBUG41_0__ngg_debug_tc_if_irts_in__SHIFT 0x0000000e -#define PA_DEBUG41_0__ngg_debug_tc_if_reg_valid1__SHIFT 0x0000000f -#define PA_DEBUG41_0__ngg_debug_tc_if_reg_valid0__SHIFT 0x00000010 -#define PA_DEBUG41_0__ngg_debug_tc_if_data_rd_ptr__SHIFT 0x00000011 -#define PA_DEBUG41_0__ngg_debug_tc_if_data_wr_ptr__SHIFT 0x00000012 -#define PA_DEBUG41_0__ngg_debug_tc_if_outstanding_tc_requests__SHIFT 0x00000013 -#define PA_DEBUG41_0__Reserved0__SHIFT 0x0000001d - -// PA_DEBUG41_1 -#define PA_DEBUG41_1__ngg_utcl1_debug07__SHIFT 0x00000000 - -// PA_DEBUG42_0 -#define PA_DEBUG42_0__ngg_debug_sideband_sideband_tokens_not_max_value__SHIFT 0x00000000 -#define PA_DEBUG42_0__ngg_debug_sideband_pending_subgroup_count_not_zero__SHIFT 0x00000001 -#define PA_DEBUG42_0__ngg_debug_sideband_wait_counter_busy__SHIFT 0x00000002 -#define PA_DEBUG42_0__ngg_debug_sideband_current_state__SHIFT 0x00000003 -#define PA_DEBUG42_0__ngg_debug_sideband_sideband_tokens_underflow__SHIFT 0x00000006 -#define PA_DEBUG42_0__ngg_debug_sideband_sideband_tokens_overflow__SHIFT 0x00000007 -#define PA_DEBUG42_0__ngg_debug_sideband_current_dword_pointer__SHIFT 0x00000008 -#define PA_DEBUG42_0__ngg_debug_sideband_pending_subgroup_count_range__SHIFT 0x0000000c -#define PA_DEBUG42_0__ngg_debug_sideband_valid_dword_count__SHIFT 0x00000011 -#define PA_DEBUG42_0__ngg_debug_sideband_itc_return_empty__SHIFT 0x00000016 -#define PA_DEBUG42_0__ngg_debug_sideband_current_sideband_is_object_id__SHIFT 0x00000017 -#define PA_DEBUG42_0__ngg_debug_sideband_current_sideband_event_bit_set__SHIFT 0x00000018 -#define PA_DEBUG42_0__ngg_debug_sideband_have_available_sideband_tokens__SHIFT 0x00000019 -#define PA_DEBUG42_0__Reserved0__SHIFT 0x0000001a - -// PA_DEBUG42_1 -#define PA_DEBUG42_1__ngg_utcl1_debug08__SHIFT 0x00000000 - -// PA_DEBUG43_0 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_ovmid__SHIFT 0x00000000 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_vmid_fifo_busy__SHIFT 0x00000004 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_vmid_fifo_empty__SHIFT 0x00000005 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_vmid_fifo_full__SHIFT 0x00000006 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_sideband_pop_bit_fifo_empty__SHIFT 0x00000007 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_sideband_pop_bit_fifo_busy__SHIFT 0x00000008 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_sideband_pop_bit_fifo_full__SHIFT 0x00000009 -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_current_state__SHIFT 0x0000000a -#define PA_DEBUG43_0__ngg_debug_sideband_wdif_osideband_active__SHIFT 0x0000000b -#define PA_DEBUG43_0__Reserved0__SHIFT 0x0000000c - -// PA_DEBUG43_1 -#define PA_DEBUG43_1__ngg_utcl1_debug09__SHIFT 0x00000000 - -// PA_DEBUG44_0 -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents1_underflow__SHIFT 0x00000000 -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents1_overflow__SHIFT 0x00000001 -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents0_underflow__SHIFT 0x00000002 -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents0_overflow__SHIFT 0x00000003 -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents0__SHIFT 0x00000004 -#define PA_DEBUG44_0__ngg_debug_sideband_memory_contents1__SHIFT 0x0000000c -#define PA_DEBUG44_0__Reserved0__SHIFT 0x00000014 - -// PA_DEBUG44_1 -#define PA_DEBUG44_1__ngg_utcl1_debug10__SHIFT 0x00000000 - -// PA_DEBUG45_0 -#define PA_DEBUG45_0__ngg_debug_index_index_tokens_underflow__SHIFT 0x00000000 -#define PA_DEBUG45_0__ngg_debug_index_index_tokens_overflow__SHIFT 0x00000001 -#define PA_DEBUG45_0__ngg_debug_index_index_tokens__SHIFT 0x00000002 -#define PA_DEBUG45_0__ngg_debug_index_prim_indices_fifo_busy__SHIFT 0x00000008 -#define PA_DEBUG45_0__ngg_debug_index_index_receive_fifo_busy__SHIFT 0x00000009 -#define PA_DEBUG45_0__ngg_debug_index_current_receive_state__SHIFT 0x0000000a -#define PA_DEBUG45_0__ngg_debug_index_current_fetch_state__SHIFT 0x0000000b -#define PA_DEBUG45_0__ngg_debug_index_sideband_data_context_id_bits__SHIFT 0x0000000c -#define PA_DEBUG45_0__ngg_debug_index_sideband_data_eop_bit__SHIFT 0x0000000f -#define PA_DEBUG45_0__ngg_debug_index_sideband_data_event_bit__SHIFT 0x00000010 -#define PA_DEBUG45_0__ngg_debug_index_final_receive_dword_of_subgroup__SHIFT 0x00000011 -#define PA_DEBUG45_0__ngg_debug_index_final_receive_cacheline_this_subgroup__SHIFT 0x00000012 -#define PA_DEBUG45_0__ngg_debug_index_current_receive_first_dword_pointer__SHIFT 0x00000013 -#define PA_DEBUG45_0__ngg_debug_index_current_receive_finalt_dword_pointer__SHIFT 0x00000017 -#define PA_DEBUG45_0__ngg_debug_index_index_receive_fifo_empty__SHIFT 0x0000001b -#define PA_DEBUG45_0__ngg_debug_index_index_receive_fifo_full__SHIFT 0x0000001c -#define PA_DEBUG45_0__ngg_debug_index_have_available_index_tokens__SHIFT 0x0000001d -#define PA_DEBUG45_0__Reserved0__SHIFT 0x0000001e - -// PA_DEBUG45_1 -#define PA_DEBUG45_1__ngg_utcl1_debug11__SHIFT 0x00000000 - -// PA_DEBUG46_0 -#define PA_DEBUG46_0__ngg_debug_position_request_position_tokens_underflow__SHIFT 0x00000000 -#define PA_DEBUG46_0__ngg_debug_position_request_position_tokens_overflow__SHIFT 0x00000001 -#define PA_DEBUG46_0__ngg_debug_position_request_have_available_position_tokens__SHIFT 0x00000002 -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_busy__SHIFT 0x00000003 -#define PA_DEBUG46_0__ngg_debug_position_request_prev_select_end_cacheline_address__SHIFT 0x00000004 -#define PA_DEBUG46_0__ngg_debug_position_request_prev_pos_cacheline_valid__SHIFT 0x00000005 -#define PA_DEBUG46_0__ngg_debug_position_request_active_pos_req_fosg__SHIFT 0x00000006 -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_miss_count__SHIFT 0x00000007 -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_final_prim__SHIFT 0x00000009 -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_first_prim__SHIFT 0x0000000a -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_null_prim__SHIFT 0x0000000b -#define PA_DEBUG46_0__ngg_debug_position_request_reuse_prim_valid__SHIFT 0x0000000c -#define PA_DEBUG46_0__ngg_debug_position_request_packer_object_id_valid__SHIFT 0x0000000d -#define PA_DEBUG46_0__ngg_debug_position_request_packer_sideband_valid__SHIFT 0x0000000e -#define PA_DEBUG46_0__ngg_debug_position_request_current_state__SHIFT 0x0000000f -#define PA_DEBUG46_0__ngg_debug_position_request_ipa_to_wd_dealloc_index_full__SHIFT 0x00000011 -#define PA_DEBUG46_0__ngg_debug_position_request_iposreq_to_posrtn_s_fifo_full__SHIFT 0x00000012 -#define PA_DEBUG46_0__ngg_debug_position_request_iposreq_to_posrtn_v_fifo_full__SHIFT 0x00000013 -#define PA_DEBUG46_0__ngg_debug_position_request_ifetch_to_primic_s_fifo_full__SHIFT 0x00000014 -#define PA_DEBUG46_0__ngg_debug_position_request_ifetch_to_primic_p_fifo_full__SHIFT 0x00000015 -#define PA_DEBUG46_0__ngg_debug_position_request_another_pos_fetch__SHIFT 0x00000016 -#define PA_DEBUG46_0__ngg_debug_position_request_end_prev_diff__SHIFT 0x00000017 -#define PA_DEBUG46_0__ngg_debug_position_request_start_prev_diff__SHIFT 0x00000018 -#define PA_DEBUG46_0__ngg_debug_position_request_end_start_diff__SHIFT 0x00000019 -#define PA_DEBUG46_0__Reserved0__SHIFT 0x0000001a - -// PA_DEBUG46_1 -#define PA_DEBUG46_1__ngg_utcl1_debug12__SHIFT 0x00000000 - -// PA_DEBUG47_0 -#define PA_DEBUG47_0__ngg_debug_position_reuse_sideband_fifo_full__SHIFT 0x00000000 -#define PA_DEBUG47_0__ngg_debug_position_reuse_sideband_fifo_empty__SHIFT 0x00000001 -#define PA_DEBUG47_0__ngg_debug_position_reuse_sideband_fifo_busy__SHIFT 0x00000002 -#define PA_DEBUG47_0__ngg_debug_position_reuse_prim_fifo_full__SHIFT 0x00000003 -#define PA_DEBUG47_0__ngg_debug_position_reuse_output_prim_empty__SHIFT 0x00000004 -#define PA_DEBUG47_0__ngg_debug_position_reuse_prim_fifo_busy__SHIFT 0x00000005 -#define PA_DEBUG47_0__ngg_debug_position_reuse_current_state__SHIFT 0x00000006 -#define PA_DEBUG47_0__ngg_debug_position_reuse_iinput_sideband_valid__SHIFT 0x00000007 -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_stream_id__SHIFT 0x00000008 -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_eop_bit__SHIFT 0x0000000a -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_event_id__SHIFT 0x0000000b -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_event_second_cycle__SHIFT \ - 0x00000011 -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_event_bit__SHIFT 0x00000012 -#define PA_DEBUG47_0__ngg_debug_position_reuse_input_sideband_dword_state_id__SHIFT 0x00000013 -#define PA_DEBUG47_0__Reserved0__SHIFT 0x00000016 - -// PA_DEBUG47_1 -#define PA_DEBUG47_1__ngg_utcl1_debug13__SHIFT 0x00000000 - -// PA_DEBUG48_0 -#define PA_DEBUG48_0__ngg_debug_position_return_ifetch_to_sxif_fifo_full__SHIFT 0x00000000 -#define PA_DEBUG48_0__ngg_debug_position_return_ipa_to_wd_dealloc_position_full__SHIFT 0x00000001 -#define PA_DEBUG48_0__ngg_debug_position_return_itc_return_empty__SHIFT 0x00000002 -#define PA_DEBUG48_0__ngg_debug_position_return_oposreq_to_posrtn_v_fifo_full__SHIFT 0x00000003 -#define PA_DEBUG48_0__ngg_debug_position_return_oposreq_to_posrtn_s_fifo_full__SHIFT 0x00000004 -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_v_fifo_busy__SHIFT 0x00000005 -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_s_fifo_busy__SHIFT 0x00000006 -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_v_fifo_empty__SHIFT 0x00000007 -#define PA_DEBUG48_0__ngg_debug_position_return_posreq_to_posrtn_s_fifo_empty__SHIFT 0x00000008 -#define PA_DEBUG48_0__ngg_debug_position_return_active_pos_return_state__SHIFT 0x00000009 -#define PA_DEBUG48_0__ngg_debug_position_return_cache_pos_index__SHIFT 0x0000000b -#define PA_DEBUG48_0__ngg_debug_position_return_active_pos_return_first_vert__SHIFT 0x0000000d -#define PA_DEBUG48_0__ngg_debug_position_return_active_pos_return_cache_pos_index__SHIFT 0x0000000e -#define PA_DEBUG48_0__Reserved0__SHIFT 0x00000010 - -// PA_DEBUG48_1 -#define PA_DEBUG48_1__ngg_utcl1_debug14__SHIFT 0x00000000 - -// PA_DEBUG49_0 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_memreg0_busy__SHIFT 0x00000000 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_oreturn_empty_stream0__SHIFT 0x00000001 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_return_data_read_reg_full_stream0__SHIFT 0x00000002 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_memreg1_busy__SHIFT 0x00000003 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_oreturn_empty_stream1__SHIFT 0x00000004 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_return_data_read_reg_full_stream1__SHIFT 0x00000005 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_memreg2_busy__SHIFT 0x00000006 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_oreturn_empty_stream2__SHIFT 0x00000007 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_return_data_read_reg_full_stream2__SHIFT 0x00000008 -#define PA_DEBUG49_0__ngg_debug_tc_return_if_crawler_busy__SHIFT 0x00000009 -#define PA_DEBUG49_0__Reserved0__SHIFT 0x0000000a - -// PA_DEBUG49_1 -#define PA_DEBUG49_1__ngg_utcl1_debug15__SHIFT 0x00000000 - -// PA_DEBUG50_0 -#define PA_DEBUG50_0__ngg_debug_return_crawler_encountered_error_writing_to_busy_location_stream0__SHIFT \ - 0x00000000 -#define PA_DEBUG50_0__ngg_debug_return_crawler_encountered_error_writing_to_busy_location_stream1__SHIFT \ - 0x00000001 -#define PA_DEBUG50_0__ngg_debug_return_crawler_encountered_error_writing_to_busy_location_stream2__SHIFT \ - 0x00000002 -#define PA_DEBUG50_0__ngg_debug_return_crawler_memory_data_valid_stream0_count__SHIFT 0x00000003 -#define PA_DEBUG50_0__ngg_debug_return_crawler_memory_data_valid_stream1_count__SHIFT 0x00000009 -#define PA_DEBUG50_0__ngg_debug_return_crawler_memory_data_valid_stream2_count__SHIFT 0x0000000f -#define PA_DEBUG50_0__ngg_debug_return_crawler_obusy__SHIFT 0x00000017 -#define PA_DEBUG50_0__Reserved0__SHIFT 0x00000018 - -// PA_DEBUG50_1 -#define PA_DEBUG50_1__ngg_utcl1_debug16__SHIFT 0x00000000 - -// PA_DEBUG51_0 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_pa_to_wd_dealloc_fifo_read__SHIFT 0x00000000 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_pa_to_wd_dealloc_fifo_empty__SHIFT 0x00000001 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_position_full__SHIFT 0x00000002 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_index_full__SHIFT 0x00000003 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_fifo_busy__SHIFT 0x00000004 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_amount__SHIFT 0x00000005 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_state_var_index__SHIFT 0x00000010 -#define PA_DEBUG51_0__ngg_debug_wd_dealloc_opa_to_wd_dealloc_type__SHIFT 0x00000013 -#define PA_DEBUG51_0__Reserved0__SHIFT 0x00000014 - -// PA_DEBUG52_0 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iutcl1_busy__SHIFT 0x00000000 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iposition_requester_idle__SHIFT 0x00000001 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iindex_requester_idle__SHIFT 0x00000002 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_isideband_requester_idle__SHIFT 0x00000003 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iposition_utcl1_return_busy__SHIFT 0x00000004 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iindex_utcl1_return_busy__SHIFT 0x00000005 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_isideband_utcl1_return_busy__SHIFT 0x00000006 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iposition_utcl1_send_busy__SHIFT 0x00000007 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_iindex_utcl1_send_busy__SHIFT 0x00000008 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_isideband_utcl1_send_busy__SHIFT 0x00000009 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_ioutstanding_tc_requests_exist__SHIFT 0x0000000a -#define PA_DEBUG52_0__ngg_debug_shootdown_control_all_clean__SHIFT 0x0000000b -#define PA_DEBUG52_0__ngg_debug_shootdown_control_vmid_count__SHIFT 0x0000000c -#define PA_DEBUG52_0__ngg_debug_shootdown_control_oclean__SHIFT 0x00000010 -#define PA_DEBUG52_0__ngg_debug_shootdown_control_current_state__SHIFT 0x00000011 -#define PA_DEBUG52_0__Reserved0__SHIFT 0x00000014 - -// PA_DEBUG53_0 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_tc_credit_count_overflow__SHIFT 0x00000000 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_tc_credit_count_underflow__SHIFT \ - 0x00000001 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sideband_tokens_overflow__SHIFT 0x00000002 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sideband_tokens_underflow__SHIFT \ - 0x00000003 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents0_overflow__SHIFT 0x00000004 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents0_underflow__SHIFT \ - 0x00000005 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents1_overflow__SHIFT 0x00000006 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_sbmem_contents1_underflow__SHIFT \ - 0x00000007 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_index_tokens_overflow__SHIFT 0x00000008 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_index_tokens_underflow__SHIFT 0x00000009 -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_position_tokens_overflow__SHIFT 0x0000000a -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_position_tokens_underflow__SHIFT \ - 0x0000000b -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_writing_to_busy_location_stream0__SHIFT \ - 0x0000000c -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_writing_to_busy_location_stream1__SHIFT \ - 0x0000000d -#define PA_DEBUG53_0__ngg_debug_fatal_events_status_fatal_writing_to_busy_location_stream2__SHIFT \ - 0x0000000e -#define PA_DEBUG53_0__Reserved0__SHIFT 0x0000000f - -// PA_DEBUG54_0 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_sideband_pop_bit_fifo_full__SHIFT 0x00000000 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_vmid_fifo_full__SHIFT 0x00000001 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_sbmem_full__SHIFT 0x00000002 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_index_receive_fifo_full__SHIFT 0x00000003 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_prim_indices_fifo_full__SHIFT 0x00000004 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_prim_fifo_full__SHIFT 0x00000005 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_sideband_fifo_full__SHIFT 0x00000006 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_posreq_to_posrtn_v_fifo_full__SHIFT 0x00000007 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_posreq_to_posrtn_s_fifo_full__SHIFT 0x00000008 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_return_data_full_stream0__SHIFT 0x00000009 -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_return_data_full_stream1__SHIFT 0x0000000a -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_return_data_full_stream2__SHIFT 0x0000000b -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_pa_to_wd_dealloc_index_full__SHIFT 0x0000000c -#define PA_DEBUG54_0__ngg_debug_fifo_full_status_fifo_pa_to_wd_dealloc_position_full__SHIFT \ - 0x0000000d -#define PA_DEBUG54_0__Reserved0__SHIFT 0x0000000e - -// PA_DEBUG55_0 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_sideband_pop_bit_fifo_empty__SHIFT 0x00000000 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_vmid_fifo_empty__SHIFT 0x00000001 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_sbmem_empty__SHIFT 0x00000002 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_index_receive_fifo_empty__SHIFT 0x00000003 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_prim_indices_fifo_empty__SHIFT 0x00000004 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_prim_fifo_empty__SHIFT 0x00000005 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_sideband_fifo_empty__SHIFT 0x00000006 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_posreq_to_posrtn_v_fifo_empty__SHIFT \ - 0x00000007 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_posreq_to_posrtn_s_fifo_empty__SHIFT \ - 0x00000008 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_return_data_empty_stream0__SHIFT 0x00000009 -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_return_data_empty_stream1__SHIFT 0x0000000a -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_return_data_empty_stream2__SHIFT 0x0000000b -#define PA_DEBUG55_0__ngg_debug_fifo_empty_status_fifo_pa_to_wd_dealloc_fifo_empty__SHIFT 0x0000000c -#define PA_DEBUG55_0__Reserved0__SHIFT 0x0000000d - -// Idebug0 -#define Idebug0__cmd_debug_info00__SHIFT 0x00000000 -#define Idebug0__Reserved0__SHIFT 0x0000000d - -// Idebug1 -#define Idebug1__data_debug_info00__SHIFT 0x00000000 -#define Idebug1__Reserved0__SHIFT 0x00000011 - -// Idebug2 -#define Idebug2__cmd_debug_info01__SHIFT 0x00000000 -#define Idebug2__Reserved0__SHIFT 0x0000000d - -// Idebug3 -#define Idebug3__data_debug_info01__SHIFT 0x00000000 -#define Idebug3__Reserved0__SHIFT 0x00000011 - -// Idebug4 -#define Idebug4__cmd_debug_info10__SHIFT 0x00000000 -#define Idebug4__Reserved0__SHIFT 0x0000000d - -// Idebug5 -#define Idebug5__data_debug_info10__SHIFT 0x00000000 -#define Idebug5__Reserved0__SHIFT 0x00000011 - -// Idebug6 -#define Idebug6__cmd_debug_info11__SHIFT 0x00000000 -#define Idebug6__Reserved0__SHIFT 0x0000000d - -// Idebug7 -#define Idebug7__data_debug_info11__SHIFT 0x00000000 -#define Idebug7__Reserved0__SHIFT 0x00000011 - -// Idebug8 -#define Idebug8__cmd_debug_info20__SHIFT 0x00000000 -#define Idebug8__Reserved0__SHIFT 0x0000000d - -// Idebug9 -#define Idebug9__data_debug_info20__SHIFT 0x00000000 -#define Idebug9__Reserved0__SHIFT 0x00000011 - -// Idebug11 -#define Idebug11__cmd_debug_info30__SHIFT 0x00000000 -#define Idebug11__Reserved0__SHIFT 0x0000000d - -// Idebug12 -#define Idebug12__data_debug_info30__SHIFT 0x00000000 -#define Idebug12__Reserved0__SHIFT 0x00000011 - -// signal_debug_00 -#define signal_debug_00__current_shader_format__SHIFT 0x00000000 -#define signal_debug_00__number_of_mrts_no_z__SHIFT 0x00000003 -#define signal_debug_00__number_of_position_vectors__SHIFT 0x00000007 -#define signal_debug_00__number_of_valid_buff0_quads_in_previous_phases__SHIFT 0x0000000a -#define signal_debug_00__number_of_valid_buff1_quads_in_previous_phases__SHIFT 0x0000000e -#define signal_debug_00__number_of_valid_buff0_quads_in_this_phase__SHIFT 0x00000012 -#define signal_debug_00__number_of_valid_buff1_quads_in_this_phase__SHIFT 0x00000015 -#define signal_debug_00__Reserved0__SHIFT 0x00000018 - -// signal_debug_01 -#define signal_debug_01__current_shader_format__SHIFT 0x00000000 -#define signal_debug_01__number_of_mrts_no_z__SHIFT 0x00000003 -#define signal_debug_01__number_of_position_vectors__SHIFT 0x00000007 -#define signal_debug_01__number_of_valid_buff0_quads_in_previous_phases__SHIFT 0x0000000a -#define signal_debug_01__number_of_valid_buff1_quads_in_previous_phases__SHIFT 0x0000000e -#define signal_debug_01__number_of_valid_buff0_quads_in_this_phase__SHIFT 0x00000012 -#define signal_debug_01__number_of_valid_buff1_quads_in_this_phase__SHIFT 0x00000015 -#define signal_debug_01__Reserved0__SHIFT 0x00000018 - -// signal_debug_02 -#define signal_debug_02__sq_sx_expcmd1_empty__SHIFT 0x00000000 -#define signal_debug_02__sq_sx_expcmd0_empty__SHIFT 0x00000001 -#define signal_debug_02__sq_sx_expcmd1_full__SHIFT 0x00000002 -#define signal_debug_02__sq_sx_expcmd0_full__SHIFT 0x00000003 -#define signal_debug_02__spi_sx_expaddr1_empty__SHIFT 0x00000004 -#define signal_debug_02__spi_sx_expaddr0_empty__SHIFT 0x00000005 -#define signal_debug_02__spi_sx_expaddr1_full__SHIFT 0x00000006 -#define signal_debug_02__spi_sx_expaddr0_full__SHIFT 0x00000007 -#define signal_debug_02__sx_position_scoreboard_debug_15to0__SHIFT 0x00000008 -#define signal_debug_02__Reserved0__SHIFT 0x00000018 - -// signal_debug_03 -#define signal_debug_03__bank3_write_quad_select__SHIFT 0x00000000 -#define signal_debug_03__bank2_write_quad_select__SHIFT 0x00000002 -#define signal_debug_03__bank1_write_quad_select__SHIFT 0x00000004 -#define signal_debug_03__Bank0_write_quad_select__SHIFT 0x00000006 -#define signal_debug_03__write_enables__SHIFT 0x00000008 -#define signal_debug_03__Reserved0__SHIFT 0x00000018 - -// signal_debug_04 -#define signal_debug_04__read_phase_count__SHIFT 0x00000000 -#define signal_debug_04__aux_count__SHIFT 0x00000002 -#define signal_debug_04__side_cycle__SHIFT 0x00000005 -#define signal_debug_04__requester_state_id__SHIFT 0x00000006 -#define signal_debug_04__requester_empty__SHIFT 0x0000000a -#define signal_debug_04__requester_full__SHIFT 0x0000000b -#define signal_debug_04__pos_req_buff_empty__SHIFT 0x0000000c -#define signal_debug_04__pos_req_buff_full__SHIFT 0x0000000d -#define signal_debug_04__number_of_valid_quads_in_previous_phases__SHIFT 0x0000000e -#define signal_debug_04__sx_position_scoreboard_debug_21to16__SHIFT 0x00000012 -#define signal_debug_04__Reserved0__SHIFT 0x00000018 - -// signal_debug_05 -#define signal_debug_05__sh_sx_expcmd1_pos__SHIFT 0x00000001 -#define signal_debug_05__sx_position_scoreboard_debug_30to22__SHIFT 0x00000002 -#define signal_debug_05__traffic_to_db0__SHIFT 0x0000000b -#define signal_debug_05__scoreboard_read_data_qualified_mask_odd_db_11to0__SHIFT 0x0000000c -#define signal_debug_05__Reserved0__SHIFT 0x00000018 - -// signal_debug_06 -#define signal_debug_06__sx_color_scoreboard_debug_max_36to13__SHIFT 0x00000000 -#define signal_debug_06__Reserved0__SHIFT 0x00000018 - -// signal_debug_07 -#define signal_debug_07__sx_color_scoreboard_debug_max_60to37__SHIFT 0x00000000 -#define signal_debug_07__Reserved0__SHIFT 0x00000018 - -// signal_debug_08 -#define signal_debug_08__sx_color_scoreboard_debug_max_84to61__SHIFT 0x00000000 -#define signal_debug_08__Reserved0__SHIFT 0x00000018 - -// signal_debug_09 -#define signal_debug_09__sx_color_scoreboard_debug_max_108to85__SHIFT 0x00000000 -#define signal_debug_09__Reserved0__SHIFT 0x00000018 - -// signal_debug_10 -#define signal_debug_10__sx_color_scoreboard_debug_max_132to109__SHIFT 0x00000000 -#define signal_debug_10__Reserved0__SHIFT 0x00000018 - -// signal_debug_11 -#define signal_debug_11__sx_color_scoreboard_debug_max_156to133__SHIFT 0x00000000 -#define signal_debug_11__Reserved0__SHIFT 0x00000018 - -// signal_debug_12 -#define signal_debug_12__sx_color_scoreboard_debug_max_160to157__SHIFT 0x00000000 -#define signal_debug_12__sx_color_requester0_debug_19to0__SHIFT 0x00000004 -#define signal_debug_12__Reserved0__SHIFT 0x00000018 - -// signal_debug_13 -#define signal_debug_13__sx_color_requester0_debug_43to20__SHIFT 0x00000000 -#define signal_debug_13__Reserved0__SHIFT 0x00000018 - -// signal_debug_14 -#define signal_debug_14__sx_color_requester0_debug_61to44__SHIFT 0x00000000 -#define signal_debug_14__sx_color_dbif0_debug__SHIFT 0x00000012 -#define signal_debug_14__sx_color_buff0_valids_debug_0__SHIFT 0x00000017 -#define signal_debug_14__Reserved0__SHIFT 0x00000018 - -// signal_debug_15 -#define signal_debug_15__sx_color_buff0_valids_debug_15to1__SHIFT 0x00000000 -#define signal_debug_15__sx_color_requester1_debug_8to0__SHIFT 0x0000000f -#define signal_debug_15__Reserved0__SHIFT 0x00000018 - -// signal_debug_16 -#define signal_debug_16__sx_color_requester1_debug_32to9__SHIFT 0x00000000 -#define signal_debug_16__Reserved0__SHIFT 0x00000018 - -// signal_debug_17 -#define signal_debug_17__sx_color_requester1_debug_56to33__SHIFT 0x00000000 -#define signal_debug_17__Reserved0__SHIFT 0x00000018 - -// signal_debug_18 -#define signal_debug_18__sx_color_requester1_debug_61to57__SHIFT 0x00000000 -#define signal_debug_18__sx_color_dbif1_debug__SHIFT 0x00000005 -#define signal_debug_18__sx_color_buff1_valids_debug_13to0__SHIFT 0x0000000a -#define signal_debug_18__Reserved0__SHIFT 0x00000018 - -// signal_debug_19 -#define signal_debug_19__sx_color_buff1_valids_debug_15to14__SHIFT 0x00000000 -#define signal_debug_19__sx_color_requester2_debug_21to0__SHIFT 0x00000002 -#define signal_debug_19__Reserved0__SHIFT 0x00000018 - -// signal_debug_20 -#define signal_debug_20__sx_color_requester2_debug_45to22__SHIFT 0x00000000 - -// signal_debug_21 -#define signal_debug_21__sx_color_requester2_debug_61to46__SHIFT 0x00000000 -#define signal_debug_21__sx_color_dbif2_debug__SHIFT 0x00000010 -#define signal_debug_21__sx_color_buff2_valids_debug_2to0__SHIFT 0x00000015 -#define signal_debug_21__Reserved0__SHIFT 0x00000018 - -// signal_debug_22 -#define signal_debug_22__sx_color_buff2_valids_debug_15to3__SHIFT 0x00000000 -#define signal_debug_22__sx_color_requester3_debug_10to0__SHIFT 0x0000000d -#define signal_debug_22__Reserved0__SHIFT 0x00000018 - -// signal_debug_23 -#define signal_debug_23__sx_color_requester3_debug_34to11__SHIFT 0x00000000 -#define signal_debug_23__Reserved0__SHIFT 0x00000018 - -// signal_debug_24 -#define signal_debug_24__sx_color_requester3_debug_58to35__SHIFT 0x00000000 -#define signal_debug_24__Reserved0__SHIFT 0x00000018 - -// signal_debug_25 -#define signal_debug_25__sx_color_requester3_debug_61to59__SHIFT 0x00000000 -#define signal_debug_25__sx_color_dbif3_debug__SHIFT 0x00000003 -#define signal_debug_25__sx_color_buff3_valids_debug__SHIFT 0x00000008 -#define signal_debug_25__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_0 -#define SC_DBG_REG_0__ps_busy_d1__SHIFT 0x00000000 -#define SC_DBG_REG_0__ps_pa0_sc_fifo_empty__SHIFT 0x00000001 -#define SC_DBG_REG_0__ps_pa0_sc_fifo_full__SHIFT 0x00000002 -#define SC_DBG_REG_0__ps_pa1_sc_fifo_empty__SHIFT 0x00000003 -#define SC_DBG_REG_0__ps_pa1_sc_fifo_full__SHIFT 0x00000004 -#define SC_DBG_REG_0__ps_pa_sc_freeze_b__SHIFT 0x00000005 -#define SC_DBG_REG_0__pw_ps_freeze_b__SHIFT 0x00000006 -#define SC_DBG_REG_0__pff_pw_full__SHIFT 0x00000007 -#define SC_DBG_REG_0__Reserved2__SHIFT 0x00000008 -#define SC_DBG_REG_0__op_oc_rtr__SHIFT 0x00000009 -#define SC_DBG_REG_0__pk0_pm_bc_full_fz__SHIFT 0x0000000a -#define SC_DBG_REG_0__pk0_pm_spi_full_fz__SHIFT 0x0000000b -#define SC_DBG_REG_0__sc_reg_sclk_vld__SHIFT 0x0000000c -#define SC_DBG_REG_0__grp0_sc_dyn_sclk_vld__SHIFT 0x0000000d -#define SC_DBG_REG_0__grp1_sc_dyn_sclk_vld__SHIFT 0x0000000e -#define SC_DBG_REG_0__grp2_sc_dyn_sclk_vld__SHIFT 0x0000000f -#define SC_DBG_REG_0__Reserved1__SHIFT 0x00000012 -#define SC_DBG_REG_0__scf_scb_current_credit__SHIFT 0x00000015 -#define SC_DBG_REG_0__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_1 -#define SC_DBG_REG_1__qp_tp_tileff_rtr__SHIFT 0x00000000 -#define SC_DBG_REG_1__Reserved4__SHIFT 0x00000001 -#define SC_DBG_REG_1__qp_tp_dbff_rtr__SHIFT 0x00000004 -#define SC_DBG_REG_1__Reserved3__SHIFT 0x00000005 -#define SC_DBG_REG_1__qp0_pm_tileff_empty__SHIFT 0x00000008 -#define SC_DBG_REG_1__qp1_pm_tileff_empty__SHIFT 0x00000009 -#define SC_DBG_REG_1__Reserved2__SHIFT 0x0000000a -#define SC_DBG_REG_1__qp0_pm_dbtileff_empty__SHIFT 0x0000000c -#define SC_DBG_REG_1__qp1_pm_dbtileff_empty__SHIFT 0x0000000d -#define SC_DBG_REG_1__Reserved1__SHIFT 0x0000000e -#define SC_DBG_REG_1__qp0_pm_dbquadff_full__SHIFT 0x00000014 -#define SC_DBG_REG_1__qp1_pm_dbquadff_full__SHIFT 0x00000015 -#define SC_DBG_REG_1__Reserved0__SHIFT 0x00000016 - -// SC_DBG_REG_2 -#define SC_DBG_REG_2__ta0_pm_quadff_empty__SHIFT 0x00000000 -#define SC_DBG_REG_2__ta1_pm_quadff_empty__SHIFT 0x00000001 -#define SC_DBG_REG_2__Reserved1__SHIFT 0x00000002 -#define SC_DBG_REG_2__ta0_pm_dbquadff_empty__SHIFT 0x00000004 -#define SC_DBG_REG_2__ta1_pm_dbquadff_empty__SHIFT 0x00000005 -#define SC_DBG_REG_2__Reserved0__SHIFT 0x00000006 - -// SC_DBG_REG_3 -#define SC_DBG_REG_3__Reserved0__SHIFT 0x00000000 - -// SC_DBG_REG_4 -#define SC_DBG_REG_4__qz0_pm_qp_tile_event__SHIFT 0x00000000 -#define SC_DBG_REG_4__qz0_pm_qp_tile_event_id__SHIFT 0x00000001 -#define SC_DBG_REG_4__qz1_pm_qp_tile_event__SHIFT 0x00000007 -#define SC_DBG_REG_4__qz1_pm_qp_tile_event_id__SHIFT 0x00000008 -#define SC_DBG_REG_4__Reserved0__SHIFT 0x0000000e - -// SC_DBG_REG_5 -#define SC_DBG_REG_5__ps_pa0_sc_fifo_empty_dbg_q__SHIFT 0x00000000 -#define SC_DBG_REG_5__ps_pa1_sc_fifo_empty_dbg_q__SHIFT 0x00000001 -#define SC_DBG_REG_5__pa0_sc_data_fifo_rd_dbg_q__SHIFT 0x00000002 -#define SC_DBG_REG_5__pa1_sc_data_fifo_rd_dbg_q__SHIFT 0x00000003 -#define SC_DBG_REG_5__pa_select_dbg_q_0__SHIFT 0x00000004 -#define SC_DBG_REG_5__eop_pop_synced_after_null_prim_dbg_q__SHIFT 0x00000005 -#define SC_DBG_REG_5__pa0_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q__SHIFT 0x00000006 -#define SC_DBG_REG_5__pa1_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q__SHIFT 0x00000007 -#define SC_DBG_REG_5__pa0_popped_suppressed_eop_dbg_q__SHIFT 0x00000008 -#define SC_DBG_REG_5__pa1_popped_suppressed_eop_dbg_q__SHIFT 0x00000009 -#define SC_DBG_REG_5__dp_event_dbg_q__SHIFT 0x0000000a -#define SC_DBG_REG_5__dp_event_id_dbg_q__SHIFT 0x0000000b -#define SC_DBG_REG_5__dp_eopg_dbg_q__SHIFT 0x00000011 -#define SC_DBG_REG_5__dp_eopkt_dbg_q__SHIFT 0x00000012 -#define SC_DBG_REG_5__dp_phase_dbg_q__SHIFT 0x00000013 -#define SC_DBG_REG_5__ring_state_dbg_q_2to0__SHIFT 0x00000015 -#define SC_DBG_REG_5__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_6 -#define SC_DBG_REG_6__ps_pa0_sc_fifo_empty_dbg_q__SHIFT 0x00000000 -#define SC_DBG_REG_6__ps_pa1_sc_fifo_empty_dbg_q__SHIFT 0x00000001 -#define SC_DBG_REG_6__pa0_sc_data_fifo_rd_dbg_q__SHIFT 0x00000002 -#define SC_DBG_REG_6__pa1_sc_data_fifo_rd_dbg_q__SHIFT 0x00000003 -#define SC_DBG_REG_6__pa_select_dbg_q__SHIFT 0x00000004 -#define SC_DBG_REG_6__eop_pop_synced_after_null_prim_dbg_q__SHIFT 0x00000006 -#define SC_DBG_REG_6__pa0_pop_null_prim_eopbcast_bubble_ld_ctl__SHIFT 0x00000007 -#define SC_DBG_REG_6__pa1_pop_null_prim_eopbcast_bubble_ld_ctl__SHIFT 0x00000008 -#define SC_DBG_REG_6__pa0_popped_suppressed_eop_dbg_q__SHIFT 0x00000009 -#define SC_DBG_REG_6__pa1_popped_suppressed_eop_dbg_q__SHIFT 0x0000000a -#define SC_DBG_REG_6__dp_event_dbg_q__SHIFT 0x0000000b -#define SC_DBG_REG_6__dp_stateid_dbg_q__SHIFT 0x0000000c -#define SC_DBG_REG_6__dp_on_last_phase_dbg_q__SHIFT 0x0000000f -#define SC_DBG_REG_6__Reserved1__SHIFT 0x00000010 -#define SC_DBG_REG_6__ps_pa_sc_freeze_b_dbg_q__SHIFT 0x00000011 -#define SC_DBG_REG_6__dp_eopg_dbg_q__SHIFT 0x00000012 -#define SC_DBG_REG_6__dp_eopkt_dbg_q__SHIFT 0x00000013 -#define SC_DBG_REG_6__dp_phase_dbg_q__SHIFT 0x00000014 -#define SC_DBG_REG_6__ts_event_fifo_full_dbg_q__SHIFT 0x00000016 -#define SC_DBG_REG_6__ring_ptr_sel_dbg_q__SHIFT 0x00000017 -#define SC_DBG_REG_6__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_7 -#define SC_DBG_REG_7__ps_pa0_sc_fifo_empty_dbg_q__SHIFT 0x00000000 -#define SC_DBG_REG_7__ps_pa1_sc_fifo_empty_dbg_q__SHIFT 0x00000001 -#define SC_DBG_REG_7__pa0_sc_data_fifo_rd_dbg_q__SHIFT 0x00000002 -#define SC_DBG_REG_7__pa1_sc_data_fifo_rd_dbg_q__SHIFT 0x00000003 -#define SC_DBG_REG_7__pa_select_dbg_q_0__SHIFT 0x00000004 -#define SC_DBG_REG_7__eop_pop_synced_after_null_prim_dbg_q__SHIFT 0x00000005 -#define SC_DBG_REG_7__pa_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q__SHIFT 0x00000006 -#define SC_DBG_REG_7__pa0_popped_suppressed_eop_dbg_q__SHIFT 0x00000008 -#define SC_DBG_REG_7__pa1_popped_suppressed_eop_dbg_q__SHIFT 0x00000009 -#define SC_DBG_REG_7__dp_event_dbg_q__SHIFT 0x0000000a -#define SC_DBG_REG_7__dp_event_id_dbg_q__SHIFT 0x0000000b -#define SC_DBG_REG_7__dp_eopg_dbg_q__SHIFT 0x00000011 -#define SC_DBG_REG_7__dp_eopkt_dbg_q__SHIFT 0x00000012 -#define SC_DBG_REG_7__ring_state_dbg_q__SHIFT 0x00000013 -#define SC_DBG_REG_7__OoO_eop_pop_sync_all_nulls_dbg_q__SHIFT 0x00000017 -#define SC_DBG_REG_7__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_8 -#define SC_DBG_REG_8__ps_pa0_sc_fifo_empty_dbg_q__SHIFT 0x00000000 -#define SC_DBG_REG_8__ps_pa1_sc_fifo_empty_dbg_q__SHIFT 0x00000001 -#define SC_DBG_REG_8__pa0_sc_data_fifo_rd_dbg_q__SHIFT 0x00000002 -#define SC_DBG_REG_8__pa1_sc_data_fifo_rd_dbg_q__SHIFT 0x00000003 -#define SC_DBG_REG_8__pa_select_dbg_q__SHIFT 0x00000004 -#define SC_DBG_REG_8__eop_pop_synced_after_null_prim_dbg_q__SHIFT 0x00000006 -#define SC_DBG_REG_8__pa0_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q__SHIFT 0x00000007 -#define SC_DBG_REG_8__pa1_pop_null_prim_eopbcast_bubble_ld_ctl_dbg_q__SHIFT 0x00000008 -#define SC_DBG_REG_8__pa0_popped_suppressed_eop_dbg_q__SHIFT 0x00000009 -#define SC_DBG_REG_8__pa1_popped_suppressed_eop_dbg_q__SHIFT 0x0000000a -#define SC_DBG_REG_8__dp_event_dbg_q__SHIFT 0x0000000b -#define SC_DBG_REG_8__dp_stateid_dbg_q__SHIFT 0x0000000c -#define SC_DBG_REG_8__dp_phase_dbg_q__SHIFT 0x0000000f -#define SC_DBG_REG_8__ps_pa_sc_freeze_b_dbg_q__SHIFT 0x00000011 -#define SC_DBG_REG_8__dp_eopg_dbg_q__SHIFT 0x00000012 -#define SC_DBG_REG_8__dp_eopkt_dbg_q__SHIFT 0x00000013 -#define SC_DBG_REG_8__OoO_eop_pop_sync_all_nulls_dbg_q__SHIFT 0x00000014 -#define SC_DBG_REG_8__ts_event_fifo_full_dbg_q__SHIFT 0x00000015 -#define SC_DBG_REG_8__ring_state_dbg_q_1to0__SHIFT 0x00000016 -#define SC_DBG_REG_8__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_9 -#define SC_DBG_REG_9__ps_pa0_sc_fifo_empty_dbg_q__SHIFT 0x00000000 -#define SC_DBG_REG_9__ps_pa1_sc_fifo_empty_dbg_q__SHIFT 0x00000001 -#define SC_DBG_REG_9__ps_pa2_sc_fifo_empty_dbg_q__SHIFT 0x00000002 -#define SC_DBG_REG_9__ps_pa3_sc_fifo_empty_dbg_q__SHIFT 0x00000003 -#define SC_DBG_REG_9__pa0_sc_data_fifo_rd_dbg_q__SHIFT 0x00000004 -#define SC_DBG_REG_9__pa1_sc_data_fifo_rd_dbg_q__SHIFT 0x00000005 -#define SC_DBG_REG_9__pa2_sc_data_fifo_rd_dbg_q__SHIFT 0x00000006 -#define SC_DBG_REG_9__pa3_sc_data_fifo_rd_dbg_q__SHIFT 0x00000007 -#define SC_DBG_REG_9__pa_select_dbg_q__SHIFT 0x00000008 -#define SC_DBG_REG_9__eop_pop_synced__SHIFT 0x0000000a -#define SC_DBG_REG_9__pa_popped_suppressed_eop_dbg_q__SHIFT 0x0000000b -#define SC_DBG_REG_9__dp_event_dbg_q__SHIFT 0x0000000c -#define SC_DBG_REG_9__dp_event_id_dbg_q__SHIFT 0x0000000d -#define SC_DBG_REG_9__dp_eopg_dbg_q__SHIFT 0x00000013 -#define SC_DBG_REG_9__dp_eopkt_dbg_q__SHIFT 0x00000014 -#define SC_DBG_REG_9__ring_state_dbg_q_2to0__SHIFT 0x00000015 -#define SC_DBG_REG_9__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_10 -#define SC_DBG_REG_10__ps_pa0_sc_fifo_empty_dbg_q__SHIFT 0x00000000 -#define SC_DBG_REG_10__ps_pa1_sc_fifo_empty_dbg_q__SHIFT 0x00000001 -#define SC_DBG_REG_10__ps_pa2_sc_fifo_empty_dbg_q__SHIFT 0x00000002 -#define SC_DBG_REG_10__ps_pa3_sc_fifo_empty_dbg_q__SHIFT 0x00000003 -#define SC_DBG_REG_10__pa0_sc_data_fifo_rd_dbg_q__SHIFT 0x00000004 -#define SC_DBG_REG_10__pa1_sc_data_fifo_rd_dbg_q__SHIFT 0x00000005 -#define SC_DBG_REG_10__pa2_sc_data_fifo_rd_dbg_q__SHIFT 0x00000006 -#define SC_DBG_REG_10__pa3_sc_data_fifo_rd_dbg_q__SHIFT 0x00000007 -#define SC_DBG_REG_10__pa_select_dbg_q__SHIFT 0x00000008 -#define SC_DBG_REG_10__eop_pop_synced__SHIFT 0x0000000a -#define SC_DBG_REG_10__pa_popped_suppressed_eop_dbg_q__SHIFT 0x0000000b -#define SC_DBG_REG_10__dp_event_dbg_q__SHIFT 0x0000000c -#define SC_DBG_REG_10__dp_stateid_dbg_q__SHIFT 0x0000000d -#define SC_DBG_REG_10__dp_eopg_dbg_q__SHIFT 0x00000010 -#define SC_DBG_REG_10__dp_eopkt_dbg_q__SHIFT 0x00000011 -#define SC_DBG_REG_10__dp_phase_dbg_q__SHIFT 0x00000012 -#define SC_DBG_REG_10__ring_state_dbg_q__SHIFT 0x00000014 -#define SC_DBG_REG_10__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_11 -#define SC_DBG_REG_11__tp_qz_freeze_b__SHIFT 0x00000000 -#define SC_DBG_REG_11__ef_tp_event__SHIFT 0x00000001 -#define SC_DBG_REG_11__send_tile__SHIFT 0x00000002 -#define SC_DBG_REG_11__need_to_send__SHIFT 0x00000003 -#define SC_DBG_REG_11__num_sent_tiles__SHIFT 0x00000004 -#define SC_DBG_REG_11__remaining_mask__SHIFT 0x00000008 -#define SC_DBG_REG_11__ef_tp_last_supertile_of_prim__SHIFT 0x00000009 -#define SC_DBG_REG_11__ef_tp_pass_empty_prim__SHIFT 0x0000000a -#define SC_DBG_REG_11__ef_tp_db_has_ordercull_entry__SHIFT 0x0000000b -#define SC_DBG_REG_11__ef_tp_db_has_last_tile_in_supertile__SHIFT 0x0000000c -#define SC_DBG_REG_11__last_supertile_of_prim__SHIFT 0x0000000d -#define SC_DBG_REG_11__last_tile_of_supertile__SHIFT 0x0000000e -#define SC_DBG_REG_11__s0_idle__SHIFT 0x0000000f -#define SC_DBG_REG_11__s1_idle__SHIFT 0x00000010 -#define SC_DBG_REG_11__s2_idle__SHIFT 0x00000011 -#define SC_DBG_REG_11__ef_tp_rts_and_n_ef_tp_rtr__SHIFT 0x00000012 -#define SC_DBG_REG_11__tp_qz_tile_rts_and_n_tp_qz_tile_rtr__SHIFT 0x00000013 -#define SC_DBG_REG_11__ef_keep_rts_and_n_ef_keep_rtr__SHIFT 0x00000014 -#define SC_DBG_REG_11__s0_rts_and_n_s0_rtr__SHIFT 0x00000015 -#define SC_DBG_REG_11__s1_rts_and_n_s1_rtr__SHIFT 0x00000016 -#define SC_DBG_REG_11__s2_rts_and_n_s2_rtr__SHIFT 0x00000017 -#define SC_DBG_REG_11__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_12 -#define SC_DBG_REG_12__z_tc_exp__SHIFT 0x00000000 -#define SC_DBG_REG_12__qz_out_backface__SHIFT 0x00000009 -#define SC_DBG_REG_12__qm_db_id__SHIFT 0x0000000a -#define SC_DBG_REG_12__qm_z_mask_needed__SHIFT 0x0000000c -#define SC_DBG_REG_12__qm_valid__SHIFT 0x0000000d -#define SC_DBG_REG_12__qm_covered__SHIFT 0x0000000e -#define SC_DBG_REG_12__qm_event_id__SHIFT 0x0000000f -#define SC_DBG_REG_12__qm_event__SHIFT 0x00000015 -#define SC_DBG_REG_12__Reserved0__SHIFT 0x00000016 - -// SC_DBG_REG_13 -#define SC_DBG_REG_13__qz_out_state_id__SHIFT 0x00000000 -#define SC_DBG_REG_13__qz_out_multi_sample__SHIFT 0x00000003 -#define SC_DBG_REG_13__int_freeze_b__SHIFT 0x00000004 -#define SC_DBG_REG_13__valid__SHIFT 0x00000005 -#define SC_DBG_REG_13__valid_out__SHIFT 0x00000006 -#define SC_DBG_REG_13__Reserved0__SHIFT 0x00000007 - -// SC_DBG_REG_14 -#define SC_DBG_REG_14__Reserved0__SHIFT 0x00000000 - -// SC_DBG_REG_15 -#define SC_DBG_REG_15__Reserved0__SHIFT 0x00000000 - -// SC_DBG_REG_16 -#define SC_DBG_REG_16__r0_mask__SHIFT 0x00000000 -#define SC_DBG_REG_16__Reserved0__SHIFT 0x00000010 - -// SC_DBG_REG_17 -#define SC_DBG_REG_17__r0_qd_picker_mask__SHIFT 0x00000000 -#define SC_DBG_REG_17__Reserved0__SHIFT 0x00000008 - -// SC_DBG_REG_18 -#define SC_DBG_REG_18__tilefifo_empty__SHIFT 0x00000000 -#define SC_DBG_REG_18__tilefifo_full__SHIFT 0x00000001 -#define SC_DBG_REG_18__tile_mask_fifo_empty__SHIFT 0x00000002 -#define SC_DBG_REG_18__tile_mask_fifo_full__SHIFT 0x00000003 -#define SC_DBG_REG_18__rslt_fifo_empty__SHIFT 0x00000004 -#define SC_DBG_REG_18__rslt_fifo_full__SHIFT 0x00000005 -#define SC_DBG_REG_18__pop_fifo_r0__SHIFT 0x00000006 -#define SC_DBG_REG_18__r0_last_tile_of_prim__SHIFT 0x00000007 -#define SC_DBG_REG_18__last_quad__SHIFT 0x00000008 -#define SC_DBG_REG_18__rslt_r0_SC_CR_MSAA_NUM_SAMPLES__SHIFT 0x00000009 -#define SC_DBG_REG_18__rslt_r0_SC_CR_TILE_RATE__SHIFT 0x0000000c -#define SC_DBG_REG_18__rslt_r0_SC_CR_WOE__SHIFT 0x0000000d -#define SC_DBG_REG_18__rslt_r0_SC_CR_KILL_PIX__SHIFT 0x0000000e -#define SC_DBG_REG_18__rslt_r0_SC_TD_ZMASK_NEEDED__SHIFT 0x0000000f -#define SC_DBG_REG_18__qs_quad0_valid__SHIFT 0x00000010 -#define SC_DBG_REG_18__qs_quad1_valid__SHIFT 0x00000011 -#define SC_DBG_REG_18__qs_quad2_valid__SHIFT 0x00000012 -#define SC_DBG_REG_18__qs_quad3_valid__SHIFT 0x00000013 -#define SC_DBG_REG_18__qd_y__SHIFT 0x00000014 -#define SC_DBG_REG_18__qd_x__SHIFT 0x00000016 -#define SC_DBG_REG_18__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_19 -#define SC_DBG_REG_19__r0_bit_cnt__SHIFT 0x00000000 -#define SC_DBG_REG_19__Reserved0__SHIFT 0x00000005 - -// SC_DBG_REG_20 -#define SC_DBG_REG_20__squadfifo_empty__SHIFT 0x00000000 -#define SC_DBG_REG_20__squadfifo_full__SHIFT 0x00000001 -#define SC_DBG_REG_20__dbsc_quadfifo_empty__SHIFT 0x00000002 -#define SC_DBG_REG_20__dbsc_quadfifo_full__SHIFT 0x00000003 -#define SC_DBG_REG_20__quadfifo_empty__SHIFT 0x00000004 -#define SC_DBG_REG_20__quadfifo_full__SHIFT 0x00000005 -#define SC_DBG_REG_20__quadzfifo_empty__SHIFT 0x00000006 -#define SC_DBG_REG_20__quadzfifo_full__SHIFT 0x00000007 -#define SC_DBG_REG_20__Reserved0__SHIFT 0x00000008 - -// SC_DBG_REG_21 -#define SC_DBG_REG_21__ta_tr_quadcnt__SHIFT 0x00000000 -#define SC_DBG_REG_21__ta_tr_lasttile__SHIFT 0x00000005 -#define SC_DBG_REG_21__ta_tr_stateid__SHIFT 0x00000006 -#define SC_DBG_REG_21__ta_tr_eventid__SHIFT 0x00000009 -#define SC_DBG_REG_21__ta_tr_event__SHIFT 0x0000000f -#define SC_DBG_REG_21__ta_tr_rts__SHIFT 0x00000010 -#define SC_DBG_REG_21__ta_tr_rtr__SHIFT 0x00000011 -#define SC_DBG_REG_21__quads_rdy__SHIFT 0x00000012 -#define SC_DBG_REG_21__last_quad__SHIFT 0x00000013 -#define SC_DBG_REG_21__quad_cnt__SHIFT 0x00000014 -#define SC_DBG_REG_21__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_22 -#define SC_DBG_REG_22__quad_cnt_5__SHIFT 0x00000000 -#define SC_DBG_REG_22__qp_rtr__SHIFT 0x00000001 -#define SC_DBG_REG_22__Reserved0__SHIFT 0x00000002 - -// SC_DBG_REG_23 -#define SC_DBG_REG_23__pdf_pipe0_empty__SHIFT 0x00000000 -#define SC_DBG_REG_23__pdf_pipe1_empty__SHIFT 0x00000001 -#define SC_DBG_REG_23__pdf_full__SHIFT 0x00000002 -#define SC_DBG_REG_23__pdf_pipe0_busy__SHIFT 0x00000003 -#define SC_DBG_REG_23__pdf_pipe1_busy__SHIFT 0x00000004 -#define SC_DBG_REG_23__qs_pipe0_empty__SHIFT 0x00000005 -#define SC_DBG_REG_23__qs_pipe1_empty__SHIFT 0x00000006 -#define SC_DBG_REG_23__Reserved2__SHIFT 0x00000007 -#define SC_DBG_REG_23__qs_pipe0_full__SHIFT 0x00000009 -#define SC_DBG_REG_23__qs_pipe1_full__SHIFT 0x0000000a -#define SC_DBG_REG_23__Reserved1__SHIFT 0x0000000b -#define SC_DBG_REG_23__qs_pipe0_busy__SHIFT 0x0000000d -#define SC_DBG_REG_23__qs_pipe1_busy__SHIFT 0x0000000e -#define SC_DBG_REG_23__Reserved0__SHIFT 0x0000000f - -// SC_DBG_REG_24 -#define SC_DBG_REG_24__Reserved1__SHIFT 0x00000000 -#define SC_DBG_REG_24__pkr_qd0_prim_misc_mx_PKR_PRIM_MISC_PA_ID__SHIFT 0x00000004 -#define SC_DBG_REG_24__pkr_qd1_prim_misc_mx_PKR_PRIM_MISC_PA_ID__SHIFT 0x00000006 -#define SC_DBG_REG_24__Reserved0__SHIFT 0x0000000d - -// SC_DBG_REG_25 -#define SC_DBG_REG_25__pkr_qd0_hit__SHIFT 0x00000000 -#define SC_DBG_REG_25__pkr_qd1_hit__SHIFT 0x00000001 -#define SC_DBG_REG_25__Reserved0__SHIFT 0x00000002 -#define SC_DBG_REG_25__pkr_ds_end_of_vector__SHIFT 0x00000004 -#define SC_DBG_REG_25__pkr_qd0_first__SHIFT 0x00000005 -#define SC_DBG_REG_25__pkr_qd1_first__SHIFT 0x00000006 -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_2__SHIFT 0x00000007 -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_3__SHIFT 0x00000008 -#define SC_DBG_REG_25__pkr_ds_ctl_only_cmd__SHIFT 0x00000009 -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_0__SHIFT 0x0000000a -#define SC_DBG_REG_25__pkr_curr_vector_contains_fpov_1__SHIFT 0x0000000b -#define SC_DBG_REG_25__pkr_send_row__SHIFT 0x0000000c -#define SC_DBG_REG_25__pkr_curr_row_qdcnt__SHIFT 0x0000000d -#define SC_DBG_REG_25__pkr_curr_qds_per_vector__SHIFT 0x00000010 -#define SC_DBG_REG_25__dbg_spi_full_fz__SHIFT 0x00000014 -#define SC_DBG_REG_25__dbg_bc_full_fz__SHIFT 0x00000015 -#define SC_DBG_REG_25__pkr_primdata_dealloc_0__SHIFT 0x00000016 - -// SC_DBG_REG_26 -#define SC_DBG_REG_26__pkr_primdata_dealloc_0__SHIFT 0x00000000 -#define SC_DBG_REG_26__pkr_primdata_dealloc_1__SHIFT 0x00000001 -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_0__SHIFT 0x00000004 -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_1__SHIFT 0x00000005 -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_2__SHIFT 0x00000006 -#define SC_DBG_REG_26__pkr_curr_vector_contains_dealloc_3__SHIFT 0x00000007 - -// SC_DBG_REG_27 -#define SC_DBG_REG_27__cb0_context_done_count_neq0__SHIFT 0x00000000 -#define SC_DBG_REG_27__cb1_context_done_count_neq0__SHIFT 0x00000001 -#define SC_DBG_REG_27__cb2_context_done_count_neq0__SHIFT 0x00000002 -#define SC_DBG_REG_27__cb3_context_done_count_neq0__SHIFT 0x00000003 -#define SC_DBG_REG_27__cb4_context_done_count_neq0__SHIFT 0x00000004 -#define SC_DBG_REG_27__cb0_eop_count_neq0__SHIFT 0x00000005 -#define SC_DBG_REG_27__cb1_eop_count_neq0__SHIFT 0x00000006 -#define SC_DBG_REG_27__cb2_eop_count_neq0__SHIFT 0x00000007 -#define SC_DBG_REG_27__cb3_eop_count_neq0__SHIFT 0x00000008 -#define SC_DBG_REG_27__cb4_eop_count_neq0__SHIFT 0x00000009 -#define SC_DBG_REG_27__cb0_sync_clean__SHIFT 0x0000000a -#define SC_DBG_REG_27__cb1_sync_clean__SHIFT 0x0000000b -#define SC_DBG_REG_27__cb2_sync_clean__SHIFT 0x0000000c -#define SC_DBG_REG_27__cb3_sync_clean__SHIFT 0x0000000d -#define SC_DBG_REG_27__cb4_sync_clean__SHIFT 0x0000000e -#define SC_DBG_REG_27__db0_sync_clean__SHIFT 0x0000000f -#define SC_DBG_REG_27__db1_sync_clean__SHIFT 0x00000010 -#define SC_DBG_REG_27__db2_sync_clean__SHIFT 0x00000011 -#define SC_DBG_REG_27__db3_sync_clean__SHIFT 0x00000012 -#define SC_DBG_REG_27__db4_sync_clean__SHIFT 0x00000013 -#define SC_DBG_REG_27__cpg_sync0_clean__SHIFT 0x00000014 -#define SC_DBG_REG_27__sync0_none_clean__SHIFT 0x00000015 -#define SC_DBG_REG_27__sync0_all_clean__SHIFT 0x00000016 -#define SC_DBG_REG_27__sync0_clean_count__SHIFT 0x00000017 -#define SC_DBG_REG_27__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_28 -#define SC_DBG_REG_28__sync0_clean_count__SHIFT 0x00000000 -#define SC_DBG_REG_28__cpg_sync1_clean__SHIFT 0x00000002 -#define SC_DBG_REG_28__sync1_none_clean__SHIFT 0x00000003 -#define SC_DBG_REG_28__sync1_all_clean__SHIFT 0x00000004 -#define SC_DBG_REG_28__sync1_clean_count__SHIFT 0x00000005 - -// SC_DBG_REG_29 -#define SC_DBG_REG_29__sclk_dyn_vld__SHIFT 0x00000000 -#define SC_DBG_REG_29__pa_select__SHIFT 0x00000001 -#define SC_DBG_REG_29__Reserved1__SHIFT 0x00000003 -#define SC_DBG_REG_29__ps_pa_sc_data_valid__SHIFT 0x00000004 -#define SC_DBG_REG_29__ps_pa0_sc_fifo_empty__SHIFT 0x00000005 -#define SC_DBG_REG_29__ps_pa1_sc_fifo_empty__SHIFT 0x00000006 -#define SC_DBG_REG_29__dp_eopg__SHIFT 0x00000007 -#define SC_DBG_REG_29__dp_event__SHIFT 0x00000008 -#define SC_DBG_REG_29__phase__SHIFT 0x00000009 -#define SC_DBG_REG_29__pw_ps_freeze_b__SHIFT 0x0000000b -#define SC_DBG_REG_29__ps_pa_sc_freeze_b__SHIFT 0x0000000c -#define SC_DBG_REG_29__ps_pff_we__SHIFT 0x0000000d -#define SC_DBG_REG_29__ps_zff_we__SHIFT 0x0000000e -#define SC_DBG_REG_29__pre_rts__SHIFT 0x0000000f -#define SC_DBG_REG_29__rts_d1__SHIFT 0x00000010 -#define SC_DBG_REG_29__rts_d2__SHIFT 0x00000011 -#define SC_DBG_REG_29__rts_d3__SHIFT 0x00000012 -#define SC_DBG_REG_29__ps_pse_rts__SHIFT 0x00000013 -#define SC_DBG_REG_29__pa_index_hp3d_OoO__SHIFT 0x00000014 -#define SC_DBG_REG_29__pa_index_p3d_OoO__SHIFT 0x00000016 -#define SC_DBG_REG_29__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_30 -#define SC_DBG_REG_30__pa_index_hp3d_IoO__SHIFT 0x00000000 -#define SC_DBG_REG_30__pa_index_p3d_IoO__SHIFT 0x00000002 -#define SC_DBG_REG_30__ring_state_2to0__SHIFT 0x00000004 -#define SC_DBG_REG_30__multicycle_bubble_freeze__SHIFT 0x00000007 - -// SC_DBG_REG_31 -#define SC_DBG_REG_31__phase_d1__SHIFT 0x00000000 -#define SC_DBG_REG_31__event_mod__SHIFT 0x00000002 -#define SC_DBG_REG_31__event_id_mod__SHIFT 0x00000003 -#define SC_DBG_REG_31__end_of_pkt_d1__SHIFT 0x00000009 -#define SC_DBG_REG_31__clip_prim_d1__SHIFT 0x0000000a -#define SC_DBG_REG_31__null_prim_mod__SHIFT 0x0000000b -#define SC_DBG_REG_31__first_prim_of_vector_0_d1__SHIFT 0x0000000c -#define SC_DBG_REG_31__first_prim_of_vector_1_d1__SHIFT 0x0000000d -#define SC_DBG_REG_31__dealloc_0_d1__SHIFT 0x0000000e -#define SC_DBG_REG_31__dealloc_1_d1__SHIFT 0x00000010 -#define SC_DBG_REG_31__last_prim_of_vector_0_d1__SHIFT 0x00000012 -#define SC_DBG_REG_31__last_prim_of_vector_1_d1__SHIFT 0x00000013 -#define SC_DBG_REG_31__st_indx_d1__SHIFT 0x00000014 -#define SC_DBG_REG_31__first_prim_of_vector_2_d1__SHIFT 0x00000017 -#define SC_DBG_REG_31__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_32 -#define SC_DBG_REG_32__first_prim_of_vector_3_d1__SHIFT 0x00000000 -#define SC_DBG_REG_32__dealloc_2_d1__SHIFT 0x00000001 -#define SC_DBG_REG_32__dealloc_3_d1__SHIFT 0x00000003 -#define SC_DBG_REG_32__last_prim_of_vector_2_d1__SHIFT 0x00000005 -#define SC_DBG_REG_32__last_prim_of_vector_3_d1__SHIFT 0x00000006 -#define SC_DBG_REG_32__ts_event_fifo_full__SHIFT 0x00000007 - -// SC_DBG_REG_33 -#define SC_DBG_REG_33__pa0_ps_data_send__SHIFT 0x00000000 -#define SC_DBG_REG_33__ps_pa0_sc_fifo_empty__SHIFT 0x00000001 -#define SC_DBG_REG_33__pa1_ps_data_send__SHIFT 0x00000002 -#define SC_DBG_REG_33__ps_pa1_sc_fifo_empty__SHIFT 0x00000003 -#define SC_DBG_REG_33__busy_processing_multicycle_prim__SHIFT 0x00000004 -#define SC_DBG_REG_33__busy_cnt__SHIFT 0x00000005 -#define SC_DBG_REG_33__ctx_done_fifo_empty__SHIFT 0x0000000e -#define SC_DBG_REG_33__pa2_ps_data_send__SHIFT 0x0000000f -#define SC_DBG_REG_33__ps_pa2_sc_fifo_empty__SHIFT 0x00000010 -#define SC_DBG_REG_33__pa3_ps_data_send__SHIFT 0x00000011 -#define SC_DBG_REG_33__ps_pa3_sc_fifo_empty__SHIFT 0x00000012 -#define SC_DBG_REG_33__scb_busy__SHIFT 0x00000013 -#define SC_DBG_REG_33__scf_scb_interface_busy__SHIFT 0x00000014 -#define SC_DBG_REG_33__backend_busy__SHIFT 0x00000015 -#define SC_DBG_REG_33__bm_busy__SHIFT 0x00000016 -#define SC_DBG_REG_33__se_rb_active_pipe_mask__SHIFT 0x00000017 -#define SC_DBG_REG_33__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_34 -#define SC_DBG_REG_34__se_rb_active_pipe_mask__SHIFT 0x00000000 -#define SC_DBG_REG_34__ts_event_fifo_empty__SHIFT 0x00000007 -#define SC_DBG_REG_34__Reserved0__SHIFT 0x00000008 - -// SC_DBG_REG_35 -#define SC_DBG_REG_35__rc_rtr_dly__SHIFT 0x00000000 -#define SC_DBG_REG_35__zff_pw_full_d1__SHIFT 0x00000001 -#define SC_DBG_REG_35__pff_pw_full_d1__SHIFT 0x00000002 -#define SC_DBG_REG_35__pipe_freeze_b__SHIFT 0x00000003 -#define SC_DBG_REG_35__prim_rts__SHIFT 0x00000004 -#define SC_DBG_REG_35__next_prim_rts_dly__SHIFT 0x00000005 -#define SC_DBG_REG_35__next_prim_rtr_dly__SHIFT 0x00000006 -#define SC_DBG_REG_35__pre_stage1_rts_d1__SHIFT 0x00000007 -#define SC_DBG_REG_35__stage0_rts__SHIFT 0x00000008 -#define SC_DBG_REG_35__phase_rts_dly__SHIFT 0x00000009 -#define SC_DBG_REG_35__end_of_prim_s1_dly__SHIFT 0x0000000a -#define SC_DBG_REG_35__pass_empty_prim_s1__SHIFT 0x0000000b -#define SC_DBG_REG_35__event_s1__SHIFT 0x0000000c -#define SC_DBG_REG_35__event_id_s1__SHIFT 0x0000000d -#define SC_DBG_REG_35__Reserved0__SHIFT 0x00000013 - -// SC_DBG_REG_36 -#define SC_DBG_REG_36__Reserved0__SHIFT 0x00000000 - -// SC_DBG_REG_37 -#define SC_DBG_REG_37__x_curr_s1__SHIFT 0x00000000 -#define SC_DBG_REG_37__y_curr_s1__SHIFT 0x0000000d -#define SC_DBG_REG_37__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_38 -#define SC_DBG_REG_38__y_curr_s1__SHIFT 0x00000000 -#define SC_DBG_REG_38__x_dir_s1__SHIFT 0x00000002 -#define SC_DBG_REG_38__y_dir_s1__SHIFT 0x00000003 -#define SC_DBG_REG_38__Reserved0__SHIFT 0x00000010 - -// SC_DBG_REG_39 -#define SC_DBG_REG_39__supertile_mask_debug_15to0__SHIFT 0x00000000 -#define SC_DBG_REG_39__Reserved0__SHIFT 0x00000010 - -// SC_DBG_REG_40 -#define SC_DBG_REG_40__pw_bm_rts_and_n_pw_bm_rtr__SHIFT 0x00000000 -#define SC_DBG_REG_40__pw_bm_rts_and_n_po_rts__SHIFT 0x00000001 -#define SC_DBG_REG_40__po_rts_and_n_po_rtr__SHIFT 0x00000002 -#define SC_DBG_REG_40__po_bm_rts_and_n_po_bm_rtr__SHIFT 0x00000003 -#define SC_DBG_REG_40__bm_be0_rts_and_n_bm_be0_rtr__SHIFT 0x00000004 -#define SC_DBG_REG_40__bm_be1_rts_and_n_bm_be1_rtr__SHIFT 0x00000005 -#define SC_DBG_REG_40__pw_bm_rts_and_po_rts_and_pff_bm_empty__SHIFT 0x00000006 -#define SC_DBG_REG_40__be0_db0_has_last_tile_in_supertile_lit_tile__SHIFT 0x00000007 -#define SC_DBG_REG_40__be0_db0_has_last_tile_in_supertile__SHIFT 0x00000008 -#define SC_DBG_REG_40__be0_db1_has_last_tile_in_supertile_lit_tile__SHIFT 0x00000009 -#define SC_DBG_REG_40__be0_db1_has_last_tile_in_supertile__SHIFT 0x0000000a -#define SC_DBG_REG_40__backend0_tile_mask_zero_not_event__SHIFT 0x0000000b -#define SC_DBG_REG_40__backend0_tile_mask_zero__SHIFT 0x0000000c -#define SC_DBG_REG_40__be1_db0_has_last_tile_in_supertile_lit_tile__SHIFT 0x0000000d -#define SC_DBG_REG_40__be1_db0_has_last_tile_in_supertile__SHIFT 0x0000000e -#define SC_DBG_REG_40__be1_db1_has_last_tile_in_supertile_lit_tile__SHIFT 0x0000000f -#define SC_DBG_REG_40__be1_db1_has_last_tile_in_supertile__SHIFT 0x00000010 -#define SC_DBG_REG_40__backend1_tile_mask_zero_not_event__SHIFT 0x00000011 -#define SC_DBG_REG_40__backend1_tile_mask_zero__SHIFT 0x00000012 -#define SC_DBG_REG_40__Reserved0__SHIFT 0x00000013 - -// SC_DBG_REG_41 -#define SC_DBG_REG_41__Reserved0__SHIFT 0x00000000 - -// SC_DBG_REG_42 -#define SC_DBG_REG_42__bm_busy__SHIFT 0x00000000 -#define SC_DBG_REG_42__fifo_backend0_idle__SHIFT 0x00000001 -#define SC_DBG_REG_42__fifo_backend1_idle__SHIFT 0x00000002 -#define SC_DBG_REG_42__po_bm_stage_idle__SHIFT 0x00000003 -#define SC_DBG_REG_42__pw_bm_event__SHIFT 0x00000004 -#define SC_DBG_REG_42__pw_bm_last_supertile_of_prim__SHIFT 0x00000005 -#define SC_DBG_REG_42__pw_bm_pass_empty_prim__SHIFT 0x00000006 -#define SC_DBG_REG_42__pff_bm_empty__SHIFT 0x00000007 -#define SC_DBG_REG_42__bm_be0_db0_has_last_tile_in_supertile__SHIFT 0x00000008 -#define SC_DBG_REG_42__event_pipe_id_sh0__SHIFT 0x00000009 -#define SC_DBG_REG_42__event_pipe_id_sh1__SHIFT 0x0000000b -#define SC_DBG_REG_42__Reserved0__SHIFT 0x0000000d - -// SC_DBG_REG_43 -#define SC_DBG_REG_43__ps_busy__SHIFT 0x00000000 -#define SC_DBG_REG_43__ps_pm_backend_busy__SHIFT 0x00000001 -#define SC_DBG_REG_43__ps_pm_bm_busy__SHIFT 0x00000002 -#define SC_DBG_REG_43__ps_pm_arb_pa_sc_busy__SHIFT 0x00000003 -#define SC_DBG_REG_43__ps_pm_arb_sc_busy__SHIFT 0x00000004 -#define SC_DBG_REG_43__ps_pm_scf_scb_interface_busy__SHIFT 0x00000005 -#define SC_DBG_REG_43__ps_pm_scb_busy__SHIFT 0x00000006 -#define SC_DBG_REG_43__ctx_done_fifo_empty__SHIFT 0x00000007 -#define SC_DBG_REG_43__ts_event_fifo_empty__SHIFT 0x00000008 -#define SC_DBG_REG_43__ps_pa0_sc_fifo_empty__SHIFT 0x00000009 -#define SC_DBG_REG_43__ps_pa1_sc_fifo_empty__SHIFT 0x0000000a -#define SC_DBG_REG_43__ps_pa2_sc_fifo_empty__SHIFT 0x0000000b -#define SC_DBG_REG_43__ps_pa3_sc_fifo_empty__SHIFT 0x0000000c -#define SC_DBG_REG_43__ta0_pm_quadff_empty__SHIFT 0x0000000d -#define SC_DBG_REG_43__ta1_pm_quadff_empty__SHIFT 0x0000000e -#define SC_DBG_REG_43__ta0_pm_dbquadff_empty__SHIFT 0x0000000f -#define SC_DBG_REG_43__ta1_pm_dbquadff_empty__SHIFT 0x00000010 -#define SC_DBG_REG_43__qp0_pm_tileff_empty__SHIFT 0x00000011 -#define SC_DBG_REG_43__qp1_pm_tileff_empty__SHIFT 0x00000012 -#define SC_DBG_REG_43__qp0_pm_dbtileff_empty__SHIFT 0x00000013 -#define SC_DBG_REG_43__qp1_pm_dbtileff_empty__SHIFT 0x00000014 -#define SC_DBG_REG_43__pff_bm_empty__SHIFT 0x00000015 -#define SC_DBG_REG_43__pw_bm_rtr__SHIFT 0x00000016 -#define SC_DBG_REG_43__pw_bm_rts__SHIFT 0x00000017 -#define SC_DBG_REG_43__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_44 -#define SC_DBG_REG_44__tp_qz_freeze_b__SHIFT 0x00000000 -#define SC_DBG_REG_44__ef_tp_event__SHIFT 0x00000001 -#define SC_DBG_REG_44__send_tile__SHIFT 0x00000002 -#define SC_DBG_REG_44__need_to_send__SHIFT 0x00000003 -#define SC_DBG_REG_44__num_sent_tiles__SHIFT 0x00000004 -#define SC_DBG_REG_44__remaining_mask__SHIFT 0x00000008 -#define SC_DBG_REG_44__ef_tp_last_supertile_of_prim__SHIFT 0x00000009 -#define SC_DBG_REG_44__ef_tp_pass_empty_prim__SHIFT 0x0000000a -#define SC_DBG_REG_44__ef_tp_db_has_ordercull_entry__SHIFT 0x0000000b -#define SC_DBG_REG_44__ef_tp_db_has_last_tile_in_supertile__SHIFT 0x0000000c -#define SC_DBG_REG_44__last_supertile_of_prim__SHIFT 0x0000000d -#define SC_DBG_REG_44__last_tile_of_supertile__SHIFT 0x0000000e -#define SC_DBG_REG_44__s0_idle__SHIFT 0x0000000f -#define SC_DBG_REG_44__s1_idle__SHIFT 0x00000010 -#define SC_DBG_REG_44__s2_idle__SHIFT 0x00000011 -#define SC_DBG_REG_44__ef_tp_rts_and_n_ef_tp_rtr__SHIFT 0x00000012 -#define SC_DBG_REG_44__tp_qz_tile_rts_and_n_tp_qz_tile_rtr__SHIFT 0x00000013 -#define SC_DBG_REG_44__ef_keep_rts_and_n_ef_keep_rtr__SHIFT 0x00000014 -#define SC_DBG_REG_44__s0_rts_and_n_s0_rtr__SHIFT 0x00000015 -#define SC_DBG_REG_44__s1_rts_and_n_s1_rtr__SHIFT 0x00000016 -#define SC_DBG_REG_44__s2_rts_and_n_s2_rtr__SHIFT 0x00000017 -#define SC_DBG_REG_44__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_45 -#define SC_DBG_REG_45__z_tc_exp__SHIFT 0x00000000 -#define SC_DBG_REG_45__qz_out_backface__SHIFT 0x00000009 -#define SC_DBG_REG_45__qm_db_id__SHIFT 0x0000000a -#define SC_DBG_REG_45__qm_z_mask_needed__SHIFT 0x0000000c -#define SC_DBG_REG_45__qm_valid__SHIFT 0x0000000d -#define SC_DBG_REG_45__qm_covered__SHIFT 0x0000000e -#define SC_DBG_REG_45__qm_event_id__SHIFT 0x0000000f -#define SC_DBG_REG_45__qm_event__SHIFT 0x00000015 -#define SC_DBG_REG_45__Reserved0__SHIFT 0x00000016 - -// SC_DBG_REG_46 -#define SC_DBG_REG_46__qz_out_state_id__SHIFT 0x00000000 -#define SC_DBG_REG_46__qz_out_multi_sample__SHIFT 0x00000003 -#define SC_DBG_REG_46__int_freeze_b__SHIFT 0x00000004 -#define SC_DBG_REG_46__valid__SHIFT 0x00000005 -#define SC_DBG_REG_46__valid_out__SHIFT 0x00000006 -#define SC_DBG_REG_46__Reserved0__SHIFT 0x00000007 - -// SC_DBG_REG_47 -#define SC_DBG_REG_47__r0_mask__SHIFT 0x00000000 -#define SC_DBG_REG_47__Reserved0__SHIFT 0x00000010 - -// SC_DBG_REG_48 -#define SC_DBG_REG_48__r0_qd_picker_mask__SHIFT 0x00000000 -#define SC_DBG_REG_48__Reserved0__SHIFT 0x00000008 - -// SC_DBG_REG_49 -#define SC_DBG_REG_49__r0_mask__SHIFT 0x00000000 -#define SC_DBG_REG_49__r0_qd_picker_mask__SHIFT 0x00000010 -#define SC_DBG_REG_49__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_50 -#define SC_DBG_REG_50__r0_qd_picker_mask__SHIFT 0x00000000 -#define SC_DBG_REG_50__Reserved0__SHIFT 0x00000008 - -// SC_DBG_REG_51 -#define SC_DBG_REG_51__tilefifo_empty__SHIFT 0x00000000 -#define SC_DBG_REG_51__tilefifo_full__SHIFT 0x00000001 -#define SC_DBG_REG_51__tile_mask_fifo_empty__SHIFT 0x00000002 -#define SC_DBG_REG_51__tile_mask_fifo_full__SHIFT 0x00000003 -#define SC_DBG_REG_51__rslt_fifo_empty__SHIFT 0x00000004 -#define SC_DBG_REG_51__rslt_fifo_full__SHIFT 0x00000005 -#define SC_DBG_REG_51__pop_fifo_r0__SHIFT 0x00000006 -#define SC_DBG_REG_51__r0_last_tile_of_prim__SHIFT 0x00000007 -#define SC_DBG_REG_51__last_quad__SHIFT 0x00000008 -#define SC_DBG_REG_51__rslt_r0_SC_CR_MSAA_NUM_SAMPLES__SHIFT 0x00000009 -#define SC_DBG_REG_51__rslt_r0_SC_CR_TILE_RATE__SHIFT 0x0000000c -#define SC_DBG_REG_51__rslt_r0_SC_CR_WOE__SHIFT 0x0000000d -#define SC_DBG_REG_51__rslt_r0_SC_CR_KILL_PIX__SHIFT 0x0000000e -#define SC_DBG_REG_51__rslt_r0_SC_TD_ZMASK_NEEDED__SHIFT 0x0000000f -#define SC_DBG_REG_51__qs_quad0_valid__SHIFT 0x00000010 -#define SC_DBG_REG_51__qs_quad1_valid__SHIFT 0x00000011 -#define SC_DBG_REG_51__qs_quad2_valid__SHIFT 0x00000012 -#define SC_DBG_REG_51__qs_quad3_valid__SHIFT 0x00000013 -#define SC_DBG_REG_51__qd_y__SHIFT 0x00000014 -#define SC_DBG_REG_51__qd_x__SHIFT 0x00000016 -#define SC_DBG_REG_51__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_52 -#define SC_DBG_REG_52__r0_bit_cnt__SHIFT 0x00000000 -#define SC_DBG_REG_52__Reserved0__SHIFT 0x00000005 - -// SC_DBG_REG_53 -#define SC_DBG_REG_53__squadfifo_empty__SHIFT 0x00000000 -#define SC_DBG_REG_53__squadfifo_full__SHIFT 0x00000001 -#define SC_DBG_REG_53__dbsc_quadfifo_empty__SHIFT 0x00000002 -#define SC_DBG_REG_53__dbsc_quadfifo_full__SHIFT 0x00000003 -#define SC_DBG_REG_53__quadfifo_empty__SHIFT 0x00000004 -#define SC_DBG_REG_53__quadfifo_full__SHIFT 0x00000005 -#define SC_DBG_REG_53__quadzfifo_empty__SHIFT 0x00000006 -#define SC_DBG_REG_53__quadzfifo_full__SHIFT 0x00000007 -#define SC_DBG_REG_53__Reserved0__SHIFT 0x00000008 - -// SC_DBG_REG_54 -#define SC_DBG_REG_54__ta_tr_quadcnt__SHIFT 0x00000000 -#define SC_DBG_REG_54__ta_tr_lasttile__SHIFT 0x00000005 -#define SC_DBG_REG_54__ta_tr_stateid__SHIFT 0x00000006 -#define SC_DBG_REG_54__ta_tr_eventid__SHIFT 0x00000009 -#define SC_DBG_REG_54__ta_tr_event__SHIFT 0x0000000f -#define SC_DBG_REG_54__ta_tr_rts__SHIFT 0x00000010 -#define SC_DBG_REG_54__ta_tr_rtr__SHIFT 0x00000011 -#define SC_DBG_REG_54__quads_rdy__SHIFT 0x00000012 -#define SC_DBG_REG_54__last_quad__SHIFT 0x00000013 -#define SC_DBG_REG_54__quad_cnt__SHIFT 0x00000014 -#define SC_DBG_REG_54__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_55 -#define SC_DBG_REG_55__quad_cnt_5__SHIFT 0x00000000 -#define SC_DBG_REG_55__qp_rtr__SHIFT 0x00000001 -#define SC_DBG_REG_55__Reserved0__SHIFT 0x00000002 - -// SC_DBG_REG_56 -#define SC_DBG_REG_56__op_oc_0_push__SHIFT 0x00000000 -#define SC_DBG_REG_56__op_oc_0_dbid__SHIFT 0x00000001 -#define SC_DBG_REG_56__Reserved2__SHIFT 0x00000003 -#define SC_DBG_REG_56__n_op_oc_stall__SHIFT 0x00000006 -#define SC_DBG_REG_56__qp_oc_0_rts__SHIFT 0x00000007 -#define SC_DBG_REG_56__qp_oc_0_val__SHIFT 0x00000008 -#define SC_DBG_REG_56__qp_oc_0_rtr__SHIFT 0x00000009 -#define SC_DBG_REG_56__Reserved1__SHIFT 0x0000000a -#define SC_DBG_REG_56__qp_oc_1_rts__SHIFT 0x00000010 -#define SC_DBG_REG_56__qp_oc_1_val__SHIFT 0x00000011 -#define SC_DBG_REG_56__qp_oc_1_rtr__SHIFT 0x00000012 -#define SC_DBG_REG_56__Reserved0__SHIFT 0x00000013 - -// SC_DBG_REG_57 -#define SC_DBG_REG_57__pre_cull_0_empty__SHIFT 0x00000000 -#define SC_DBG_REG_57__pre_cull_1_empty__SHIFT 0x00000001 -#define SC_DBG_REG_57__Reserved2__SHIFT 0x00000002 -#define SC_DBG_REG_57__pre_cull_1_full__SHIFT 0x00000003 -#define SC_DBG_REG_57__pre_cull_0_full__SHIFT 0x00000004 -#define SC_DBG_REG_57__cullrslt_0_empty__SHIFT 0x00000005 -#define SC_DBG_REG_57__cullrslt_0_full__SHIFT 0x00000006 -#define SC_DBG_REG_57__cullrslt_1_empty__SHIFT 0x00000007 -#define SC_DBG_REG_57__cullrslt_1_full__SHIFT 0x00000008 -#define SC_DBG_REG_57__Reserved1__SHIFT 0x00000009 -#define SC_DBG_REG_57__pre_cull_0_dbid__SHIFT 0x0000000d -#define SC_DBG_REG_57__pre_cull_1_dbid__SHIFT 0x0000000f -#define SC_DBG_REG_57__Reserved0__SHIFT 0x00000011 - -// SC_DBG_REG_58 -#define SC_DBG_REG_58__post_cull_0_empty__SHIFT 0x00000000 -#define SC_DBG_REG_58__post_cull_1_empty__SHIFT 0x00000001 -#define SC_DBG_REG_58__Reserved1__SHIFT 0x00000002 -#define SC_DBG_REG_58__post_cull_full__SHIFT 0x00000004 -#define SC_DBG_REG_58__oc_tr_0_rts__SHIFT 0x00000005 -#define SC_DBG_REG_58__oc_tr_0_dbid__SHIFT 0x00000006 -#define SC_DBG_REG_58__oc_tr_0_rtr__SHIFT 0x00000008 -#define SC_DBG_REG_58__oc_tr_1_rts__SHIFT 0x00000009 -#define SC_DBG_REG_58__oc_tr_1_dbid__SHIFT 0x0000000a -#define SC_DBG_REG_58__oc_tr_1_rtr__SHIFT 0x0000000c -#define SC_DBG_REG_58__Reserved0__SHIFT 0x0000000d - -// SC_DBG_REG_59 -#define SC_DBG_REG_59__qfifo_re0__SHIFT 0x00000000 -#define SC_DBG_REG_59__qfifo_re1__SHIFT 0x00000001 -#define SC_DBG_REG_59__empty0__SHIFT 0x00000002 -#define SC_DBG_REG_59__empty1__SHIFT 0x00000003 -#define SC_DBG_REG_59__tr_pk_0_valid__SHIFT 0x00000004 -#define SC_DBG_REG_59__tr_pk_1_valid__SHIFT 0x00000005 -#define SC_DBG_REG_59__quad1_rtr__SHIFT 0x00000006 -#define SC_DBG_REG_59__quad0_rts__SHIFT 0x00000007 -#define SC_DBG_REG_59__quad1_rts__SHIFT 0x00000009 -#define SC_DBG_REG_59__quad0_drop__SHIFT 0x0000000a -#define SC_DBG_REG_59__quad1_drop__SHIFT 0x0000000b -#define SC_DBG_REG_59__quad0_ta0_qd0_rtr__SHIFT 0x0000000c -#define SC_DBG_REG_59__quad0_ta0_qd1_rtr__SHIFT 0x0000000d -#define SC_DBG_REG_59__quad0_ta1_qd0_rtr__SHIFT 0x0000000e -#define SC_DBG_REG_59__quad0_ta1_qd1_rtr__SHIFT 0x0000000f -#define SC_DBG_REG_59__quad1_ta0_qd0_rtr__SHIFT 0x00000010 -#define SC_DBG_REG_59__quad1_ta0_qd1_rtr__SHIFT 0x00000011 -#define SC_DBG_REG_59__quad1_ta1_qd0_rtr__SHIFT 0x00000012 -#define SC_DBG_REG_59__quad1_ta1_qd1_rtr__SHIFT 0x00000013 -#define SC_DBG_REG_59__quad0_import_z__SHIFT 0x00000014 -#define SC_DBG_REG_59__quad1_import_z__SHIFT 0x00000015 -#define SC_DBG_REG_59__quad0_stateid_1to0__SHIFT 0x00000016 -#define SC_DBG_REG_59__Reserved0__SHIFT 0x00000018 - -// SC_DBG_REG_60 -#define SC_DBG_REG_60__quad0_stateid_2__SHIFT 0x00000000 -#define SC_DBG_REG_60__quad1_stateid__SHIFT 0x00000001 -#define SC_DBG_REG_60__qfifo0_event__SHIFT 0x00000004 -#define SC_DBG_REG_60__qfifo1_event__SHIFT 0x00000005 -#define SC_DBG_REG_60__Reserved0__SHIFT 0x00000006 - -// SC_DBG_REG_61 -#define SC_DBG_REG_61__oc_tr_0_rts_and_n_oc_tr_0_rtr__SHIFT 0x00000000 -#define SC_DBG_REG_61__oc_tr_1_rts_and_n_oc_tr_1_rtr__SHIFT 0x00000001 -#define SC_DBG_REG_61__ta0_tr_rts_and_n_ta0_tr_rtr__SHIFT 0x00000002 -#define SC_DBG_REG_61__ta1_tr_rts_and_n_ta1_tr_rtr__SHIFT 0x00000003 -#define SC_DBG_REG_61__n_empty1_and_n_tr_pk_1_rtr__SHIFT 0x00000004 -#define SC_DBG_REG_61__n_empty0_and_n_tr_pk_0_rtr__SHIFT 0x00000005 -#define SC_DBG_REG_61__n_empty0_and_n_empty1_and_qfifo1_stall__SHIFT 0x00000006 -#define SC_DBG_REG_61__quad0_rts_and_n_quad0_rtr__SHIFT 0x00000007 -#define SC_DBG_REG_61__quad1_rts_and_n_quad1_rtr__SHIFT 0x00000008 -#define SC_DBG_REG_61__ta0_qd1_rts_and_n_ta0_qd1_rtr__SHIFT 0x00000009 -#define SC_DBG_REG_61__ta0_qd0_rts_and_n_ta0_qd0_rtr__SHIFT 0x0000000a -#define SC_DBG_REG_61__ta1_qd1_rts_and_n_ta1_qd1_rtr__SHIFT 0x0000000b -#define SC_DBG_REG_61__ta1_qd0_rts_and_n_ta1_qd0_rtr__SHIFT 0x0000000c -#define SC_DBG_REG_61__Reserved0__SHIFT 0x0000000d - -// SC_DBG_REG_62 -#define SC_DBG_REG_62__ta0_tr_rts__SHIFT 0x00000000 -#define SC_DBG_REG_62__ta0_tr_event__SHIFT 0x00000001 -#define SC_DBG_REG_62__ta0_tr_eventid__SHIFT 0x00000002 -#define SC_DBG_REG_62__ta0_tr_quadcnt__SHIFT 0x00000008 -#define SC_DBG_REG_62__ta0_tr_lastquad__SHIFT 0x0000000d -#define SC_DBG_REG_62__ta0_tr_lasttile__SHIFT 0x0000000e -#define SC_DBG_REG_62__ta0_tr_rtr__SHIFT 0x0000000f -#define SC_DBG_REG_62__Reserved0__SHIFT 0x00000010 - -// SC_DBG_REG_63 -#define SC_DBG_REG_63__ta1_tr_rts__SHIFT 0x00000000 -#define SC_DBG_REG_63__ta1_tr_event__SHIFT 0x00000001 -#define SC_DBG_REG_63__ta1_tr_eventid__SHIFT 0x00000002 -#define SC_DBG_REG_63__ta1_tr_quadcnt__SHIFT 0x00000008 -#define SC_DBG_REG_63__ta1_tr_lastquad__SHIFT 0x0000000d -#define SC_DBG_REG_63__ta1_tr_lasttile__SHIFT 0x0000000e -#define SC_DBG_REG_63__ta1_tr_rtr__SHIFT 0x0000000f -#define SC_DBG_REG_63__Reserved0__SHIFT 0x00000010 - -// WD_DBG_REG_0 -#define WD_DBG_REG_0__wd_busy_extended__SHIFT 0x00000000 -#define WD_DBG_REG_0__wd_nodma_busy_extended__SHIFT 0x00000001 -#define WD_DBG_REG_0__wd_busy__SHIFT 0x00000002 -#define WD_DBG_REG_0__wd_nodma_busy__SHIFT 0x00000003 -#define WD_DBG_REG_0__rbiu_busy__SHIFT 0x00000004 -#define WD_DBG_REG_0__spl_dma_busy__SHIFT 0x00000005 -#define WD_DBG_REG_0__spl_di_busy__SHIFT 0x00000006 -#define WD_DBG_REG_0__vgt0_active_q__SHIFT 0x00000007 -#define WD_DBG_REG_0__vgt1_active_q__SHIFT 0x00000008 -#define WD_DBG_REG_0__spl_dma_p1_busy__SHIFT 0x00000009 -#define WD_DBG_REG_0__rbiu_dr_p1_fifo_busy__SHIFT 0x0000000a -#define WD_DBG_REG_0__rbiu_di_p1_fifo_busy__SHIFT 0x0000000b -#define WD_DBG_REG_0__Reserved2__SHIFT 0x0000000c -#define WD_DBG_REG_0__rbiu_dr_fifo_busy__SHIFT 0x0000000d -#define WD_DBG_REG_0__rbiu_spl_dr_valid__SHIFT 0x0000000e -#define WD_DBG_REG_0__spl_rbiu_dr_read__SHIFT 0x0000000f -#define WD_DBG_REG_0__Reserved1__SHIFT 0x00000010 -#define WD_DBG_REG_0__rbiu_di_fifo_busy__SHIFT 0x00000011 -#define WD_DBG_REG_0__rbiu_spl_di_valid__SHIFT 0x00000012 -#define WD_DBG_REG_0__spl_rbiu_di_read__SHIFT 0x00000013 -#define WD_DBG_REG_0__se0_synced_q__SHIFT 0x00000014 -#define WD_DBG_REG_0__se1_synced_q__SHIFT 0x00000015 -#define WD_DBG_REG_0__se2_synced_q__SHIFT 0x00000016 -#define WD_DBG_REG_0__se3_synced_q__SHIFT 0x00000017 -#define WD_DBG_REG_0__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_1 -#define WD_DBG_REG_1__reg_clk_busy__SHIFT 0x00000000 -#define WD_DBG_REG_1__input_clk_busy__SHIFT 0x00000001 -#define WD_DBG_REG_1__core_clk_busy__SHIFT 0x00000002 -#define WD_DBG_REG_1__vgt2_active_q__SHIFT 0x00000003 -#define WD_DBG_REG_1__sclk_reg_vld__SHIFT 0x00000004 -#define WD_DBG_REG_1__sclk_input_vld__SHIFT 0x00000005 -#define WD_DBG_REG_1__sclk_core_vld__SHIFT 0x00000006 -#define WD_DBG_REG_1__vgt3_active_q__SHIFT 0x00000007 -#define WD_DBG_REG_1__grbm_fifo_empty__SHIFT 0x00000008 -#define WD_DBG_REG_1__grbm_fifo_full__SHIFT 0x00000009 -#define WD_DBG_REG_1__grbm_fifo_we__SHIFT 0x0000000a -#define WD_DBG_REG_1__grbm_fifo_re__SHIFT 0x0000000b -#define WD_DBG_REG_1__draw_initiator_valid_q__SHIFT 0x0000000c -#define WD_DBG_REG_1__event_initiator_valid_q__SHIFT 0x0000000d -#define WD_DBG_REG_1__event_addr_valid_q__SHIFT 0x0000000e -#define WD_DBG_REG_1__dma_request_valid_q__SHIFT 0x0000000f -#define WD_DBG_REG_1__Reserved1__SHIFT 0x00000010 -#define WD_DBG_REG_1__min_indx_valid_q__SHIFT 0x00000011 -#define WD_DBG_REG_1__max_indx_valid_q__SHIFT 0x00000012 -#define WD_DBG_REG_1__indx_offset_valid_q__SHIFT 0x00000013 -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_0__SHIFT 0x00000014 -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_1__SHIFT 0x00000015 -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_2__SHIFT 0x00000016 -#define WD_DBG_REG_1__grbm_fifo_rdata_reg_id_3__SHIFT 0x00000017 -#define WD_DBG_REG_1__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_2 -#define WD_DBG_REG_2__grbm_fifo_rdata_reg_id_4__SHIFT 0x00000000 -#define WD_DBG_REG_2__grbm_fifo_rdata_state_0__SHIFT 0x00000001 -#define WD_DBG_REG_2__grbm_fifo_rdata_state_1__SHIFT 0x00000002 -#define WD_DBG_REG_2__grbm_fifo_rdata_state_2__SHIFT 0x00000003 -#define WD_DBG_REG_2__free_cnt_q_0__SHIFT 0x00000004 -#define WD_DBG_REG_2__free_cnt_q_1__SHIFT 0x00000005 -#define WD_DBG_REG_2__free_cnt_q_2__SHIFT 0x00000006 -#define WD_DBG_REG_2__free_cnt_q_3__SHIFT 0x00000007 -#define WD_DBG_REG_2__free_cnt_q_4__SHIFT 0x00000008 -#define WD_DBG_REG_2__free_cnt_q_5__SHIFT 0x00000009 -#define WD_DBG_REG_2__rbiu_di_fifo_we__SHIFT 0x0000000a -#define WD_DBG_REG_2__rbiu_dr_fifo_we__SHIFT 0x0000000b -#define WD_DBG_REG_2__rbiu_di_fifo_empty__SHIFT 0x0000000c -#define WD_DBG_REG_2__rbiu_di_fifo_full__SHIFT 0x0000000d -#define WD_DBG_REG_2__rbiu_dr_fifo_empty__SHIFT 0x0000000e -#define WD_DBG_REG_2__rbiu_dr_fifo_full__SHIFT 0x0000000f -#define WD_DBG_REG_2__p1_grbm_fifo_empty__SHIFT 0x00000010 -#define WD_DBG_REG_2__p1_grbm_fifo_full__SHIFT 0x00000011 -#define WD_DBG_REG_2__p1_grbm_fifo_we__SHIFT 0x00000012 -#define WD_DBG_REG_2__p1_grbm_fifo_re__SHIFT 0x00000013 -#define WD_DBG_REG_2__p1_draw_initiator_valid_q__SHIFT 0x00000014 -#define WD_DBG_REG_2__p1_event_initiator_valid_q__SHIFT 0x00000015 -#define WD_DBG_REG_2__p1_event_addr_valid_q__SHIFT 0x00000016 -#define WD_DBG_REG_2__p1_dma_request_valid_q__SHIFT 0x00000017 -#define WD_DBG_REG_2__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_3 -#define WD_DBG_REG_3__Reserved1__SHIFT 0x00000000 -#define WD_DBG_REG_3__p1_min_indx_valid_q__SHIFT 0x00000001 -#define WD_DBG_REG_3__p1_max_indx_valid_q__SHIFT 0x00000002 -#define WD_DBG_REG_3__p1_indx_offset_valid_q__SHIFT 0x00000003 -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_0__SHIFT 0x00000004 -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_1__SHIFT 0x00000005 -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_2__SHIFT 0x00000006 -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_3__SHIFT 0x00000007 -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_reg_id_4__SHIFT 0x00000008 -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_state_5__SHIFT 0x00000009 -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_state_6__SHIFT 0x0000000a -#define WD_DBG_REG_3__p1_grbm_fifo_rdata_state_7__SHIFT 0x0000000b -#define WD_DBG_REG_3__p1_free_cnt_q_0__SHIFT 0x0000000c -#define WD_DBG_REG_3__p1_free_cnt_q_1__SHIFT 0x0000000d -#define WD_DBG_REG_3__p1_free_cnt_q_2__SHIFT 0x0000000e -#define WD_DBG_REG_3__p1_free_cnt_q_3__SHIFT 0x0000000f -#define WD_DBG_REG_3__p1_free_cnt_q_4__SHIFT 0x00000010 -#define WD_DBG_REG_3__p1_free_cnt_q_5__SHIFT 0x00000011 -#define WD_DBG_REG_3__p1_rbiu_di_fifo_we__SHIFT 0x00000012 -#define WD_DBG_REG_3__p1_rbiu_dr_fifo_we__SHIFT 0x00000013 -#define WD_DBG_REG_3__p1_rbiu_di_fifo_empty__SHIFT 0x00000014 -#define WD_DBG_REG_3__p1_rbiu_di_fifo_full__SHIFT 0x00000015 -#define WD_DBG_REG_3__p1_rbiu_dr_fifo_empty__SHIFT 0x00000016 -#define WD_DBG_REG_3__p1_rbiu_dr_fifo_full__SHIFT 0x00000017 -#define WD_DBG_REG_3__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_4 -#define WD_DBG_REG_4__rbiu_spl_dr_valid__SHIFT 0x00000000 -#define WD_DBG_REG_4__Reserved1__SHIFT 0x00000001 -#define WD_DBG_REG_4__pipe0_dr__SHIFT 0x00000002 -#define WD_DBG_REG_4__pipe0_rtr__SHIFT 0x00000003 -#define WD_DBG_REG_4__pipe1_dr__SHIFT 0x00000004 -#define WD_DBG_REG_4__pipe1_rtr__SHIFT 0x00000005 -#define WD_DBG_REG_4__wd_subdma_fifo_empty__SHIFT 0x00000006 -#define WD_DBG_REG_4__wd_subdma_fifo_full__SHIFT 0x00000007 -#define WD_DBG_REG_4__dma_buf_type_p0_q_0__SHIFT 0x00000008 -#define WD_DBG_REG_4__dma_buf_type_p0_q_1__SHIFT 0x00000009 -#define WD_DBG_REG_4__dma_zero_indices_p0_q__SHIFT 0x0000000a -#define WD_DBG_REG_4__dma_req_path_p3_q__SHIFT 0x0000000b -#define WD_DBG_REG_4__dma_not_eop_p1_q__SHIFT 0x0000000c -#define WD_DBG_REG_4__out_of_range_p4__SHIFT 0x0000000d -#define WD_DBG_REG_4__last_sub_dma_p3_q__SHIFT 0x0000000e -#define WD_DBG_REG_4__last_rdreq_of_sub_dma_p4__SHIFT 0x0000000f -#define WD_DBG_REG_4__WD_IA_dma_send_d__SHIFT 0x00000010 -#define WD_DBG_REG_4__WD_IA_dma_rtr__SHIFT 0x00000011 -#define WD_DBG_REG_4__WD_IA1_dma_send_d__SHIFT 0x00000012 -#define WD_DBG_REG_4__WD_IA1_dma_rtr__SHIFT 0x00000013 -#define WD_DBG_REG_4__last_inst_of_dma_p2__SHIFT 0x00000014 -#define WD_DBG_REG_4__last_sd_of_inst_p2__SHIFT 0x00000015 -#define WD_DBG_REG_4__last_sd_of_dma_p2__SHIFT 0x00000016 -#define WD_DBG_REG_4__Reserved0__SHIFT 0x0000001f - -// WD_DBG_REG_5 -#define WD_DBG_REG_5__WD_IA_dma_busy__SHIFT 0x00000000 -#define WD_DBG_REG_5__WD_IA1_dma_busy__SHIFT 0x00000001 -#define WD_DBG_REG_5__send_to_ia1_p3_q__SHIFT 0x00000002 -#define WD_DBG_REG_5__dma_wd_switch_on_eop_p3_q__SHIFT 0x00000003 -#define WD_DBG_REG_5__pipe3_dr__SHIFT 0x00000004 -#define WD_DBG_REG_5__pipe3_rtr__SHIFT 0x00000005 -#define WD_DBG_REG_5__wd_dma2draw_fifo_empty__SHIFT 0x00000006 -#define WD_DBG_REG_5__wd_dma2draw_fifo_full__SHIFT 0x00000007 -#define WD_DBG_REG_5__rbiu_spl_di_valid__SHIFT 0x00000008 -#define WD_DBG_REG_5__spl_rbiu_di_read__SHIFT 0x00000009 -#define WD_DBG_REG_5__rbiu_spl_p1_di_valid__SHIFT 0x0000000a -#define WD_DBG_REG_5__spl_rbiu_p1_di_read__SHIFT 0x0000000b -#define WD_DBG_REG_5__pipe0_dr__SHIFT 0x0000000c -#define WD_DBG_REG_5__pipe0_rtr__SHIFT 0x0000000d -#define WD_DBG_REG_5__pipe1_dr__SHIFT 0x0000000e -#define WD_DBG_REG_5__pipe1_rtr__SHIFT 0x0000000f -#define WD_DBG_REG_5__pipe2_dr__SHIFT 0x00000010 -#define WD_DBG_REG_5__pipe2_rtr__SHIFT 0x00000011 -#define WD_DBG_REG_5__pipe3_ld__SHIFT 0x00000012 -#define WD_DBG_REG_5__WD_IA_draw_send_d__SHIFT 0x00000014 -#define WD_DBG_REG_5__WD_IA_draw_rtr__SHIFT 0x00000015 -#define WD_DBG_REG_5__di_type_p0_0__SHIFT 0x00000016 -#define WD_DBG_REG_5__di_type_p0_1__SHIFT 0x00000017 -#define WD_DBG_REG_5__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_6 -#define WD_DBG_REG_6__di_state_sel_p1_q_0__SHIFT 0x00000000 -#define WD_DBG_REG_6__di_state_sel_p1_q_1__SHIFT 0x00000001 -#define WD_DBG_REG_6__di_state_sel_p1_q_2__SHIFT 0x00000002 -#define WD_DBG_REG_6__di_wd_switch_on_eop_p1_q__SHIFT 0x00000003 -#define WD_DBG_REG_6__rbiu_spl_pipe0_lockout__SHIFT 0x00000004 -#define WD_DBG_REG_6__last_inst_of_di_p2__SHIFT 0x00000005 -#define WD_DBG_REG_6__last_sd_of_inst_p2__SHIFT 0x00000006 -#define WD_DBG_REG_6__last_sd_of_di_p2__SHIFT 0x00000007 -#define WD_DBG_REG_6__not_eop_wait_p1_q__SHIFT 0x00000008 -#define WD_DBG_REG_6__not_eop_wait_q__SHIFT 0x00000009 -#define WD_DBG_REG_6__ext_event_wait_p1_q__SHIFT 0x0000000a -#define WD_DBG_REG_6__ext_event_wait_q__SHIFT 0x0000000b -#define WD_DBG_REG_6__WD_IA1_draw_send_d__SHIFT 0x0000000c -#define WD_DBG_REG_6__WD_IA1_draw_rtr__SHIFT 0x0000000d -#define WD_DBG_REG_6__send_to_ia1_q__SHIFT 0x0000000e -#define WD_DBG_REG_6__dual_ia_mode__SHIFT 0x0000000f -#define WD_DBG_REG_6__p1_rbiu_spl_dr_valid__SHIFT 0x00000010 -#define WD_DBG_REG_6__Reserved1__SHIFT 0x00000011 -#define WD_DBG_REG_6__p1_pipe0_dr__SHIFT 0x00000012 -#define WD_DBG_REG_6__p1_pipe0_rtr__SHIFT 0x00000013 -#define WD_DBG_REG_6__p1_pipe1_dr__SHIFT 0x00000014 -#define WD_DBG_REG_6__p1_pipe1_rtr__SHIFT 0x00000015 -#define WD_DBG_REG_6__p1_wd_subdma_fifo_empty__SHIFT 0x00000016 -#define WD_DBG_REG_6__p1_wd_subdma_fifo_full__SHIFT 0x00000017 -#define WD_DBG_REG_6__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_7 -#define WD_DBG_REG_7__p1_dma_buf_type_p0_q_0__SHIFT 0x00000000 -#define WD_DBG_REG_7__p1_dma_buf_type_p0_q_1__SHIFT 0x00000001 -#define WD_DBG_REG_7__p1_dma_zero_indices_p0_q__SHIFT 0x00000002 -#define WD_DBG_REG_7__p1_dma_req_path_p3_q__SHIFT 0x00000003 -#define WD_DBG_REG_7__p1_dma_not_eop_p1_q__SHIFT 0x00000004 -#define WD_DBG_REG_7__p1_out_of_range_p4__SHIFT 0x00000005 -#define WD_DBG_REG_7__p1_last_sub_dma_p3_q__SHIFT 0x00000006 -#define WD_DBG_REG_7__p1_last_rdreq_of_sub_dma_p4__SHIFT 0x00000007 -#define WD_DBG_REG_7__p1_WD_IA_dma_send_d__SHIFT 0x00000008 -#define WD_DBG_REG_7__p1_WD_IA_dma_rtr__SHIFT 0x00000009 -#define WD_DBG_REG_7__p1_WD_IA1_dma_send_d__SHIFT 0x0000000a -#define WD_DBG_REG_7__p1_WD_IA1_dma_rtr__SHIFT 0x0000000b -#define WD_DBG_REG_7__p1_last_inst_of_dma_p2__SHIFT 0x0000000c -#define WD_DBG_REG_7__p1_last_sd_of_inst_p2__SHIFT 0x0000000d -#define WD_DBG_REG_7__p1_last_sd_of_dma_p2__SHIFT 0x0000000e -#define WD_DBG_REG_7__Reserved1__SHIFT 0x0000000f -#define WD_DBG_REG_7__p1_WD_IA_dma_busy__SHIFT 0x00000010 -#define WD_DBG_REG_7__p1_WD_IA1_dma_busy__SHIFT 0x00000011 -#define WD_DBG_REG_7__p1_send_to_ia1_p3_q__SHIFT 0x00000012 -#define WD_DBG_REG_7__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x00000013 -#define WD_DBG_REG_7__p1_pipe3_dr__SHIFT 0x00000014 -#define WD_DBG_REG_7__p1_pipe3_rtr__SHIFT 0x00000015 -#define WD_DBG_REG_7__p1_wd_dma2draw_fifo_empty__SHIFT 0x00000016 -#define WD_DBG_REG_7__p1_wd_dma2draw_fifo_full__SHIFT 0x00000017 -#define WD_DBG_REG_7__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_8 -#define WD_DBG_REG_8__Reserved16__SHIFT 0x00000000 -#define WD_DBG_REG_8__Reserved15__SHIFT 0x00000001 -#define WD_DBG_REG_8__Reserved14__SHIFT 0x00000002 -#define WD_DBG_REG_8__Reserved13__SHIFT 0x00000003 -#define WD_DBG_REG_8__Reserved12__SHIFT 0x00000004 -#define WD_DBG_REG_8__Reserved11__SHIFT 0x00000005 -#define WD_DBG_REG_8__Reserved10__SHIFT 0x00000006 -#define WD_DBG_REG_8__Reserved9__SHIFT 0x00000007 -#define WD_DBG_REG_8__Reserved8__SHIFT 0x00000008 -#define WD_DBG_REG_8__Reserved7__SHIFT 0x00000009 -#define WD_DBG_REG_8__Reserved6__SHIFT 0x0000000a -#define WD_DBG_REG_8__Reserved5__SHIFT 0x0000000b -#define WD_DBG_REG_8__Reserved4__SHIFT 0x0000000c -#define WD_DBG_REG_8__Reserved3__SHIFT 0x0000000d -#define WD_DBG_REG_8__Reserved2__SHIFT 0x0000000e -#define WD_DBG_REG_8__Reserved1__SHIFT 0x0000000f -#define WD_DBG_REG_8__WD_IA_draw_eop_0__SHIFT 0x00000010 -#define WD_DBG_REG_8__WD_IA_draw_eop_1__SHIFT 0x00000011 -#define WD_DBG_REG_8__WD_IA_draw_eop_2__SHIFT 0x00000012 -#define WD_DBG_REG_8__WD_IA_draw_eop_3__SHIFT 0x00000013 -#define WD_DBG_REG_8__WD_IA_draw_eop_4__SHIFT 0x00000014 -#define WD_DBG_REG_8__WD_IA_draw_eop_5__SHIFT 0x00000015 -#define WD_DBG_REG_8__WD_IA_draw_eop_6__SHIFT 0x00000016 -#define WD_DBG_REG_8__WD_IA_draw_eop_7__SHIFT 0x00000017 -#define WD_DBG_REG_8__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_9 -#define WD_DBG_REG_9__WD_IA_draw_eop_8__SHIFT 0x00000000 -#define WD_DBG_REG_9__WD_IA_draw_eop_9__SHIFT 0x00000001 -#define WD_DBG_REG_9__WD_IA_draw_eop_10__SHIFT 0x00000002 -#define WD_DBG_REG_9__WD_IA_draw_eop_11__SHIFT 0x00000003 -#define WD_DBG_REG_9__WD_IA_draw_eop_12__SHIFT 0x00000004 -#define WD_DBG_REG_9__WD_IA_draw_eop_13__SHIFT 0x00000005 -#define WD_DBG_REG_9__WD_IA_draw_eop_14__SHIFT 0x00000006 -#define WD_DBG_REG_9__WD_IA_draw_eop_15__SHIFT 0x00000007 -#define WD_DBG_REG_9__WD_IA_draw_eop_16__SHIFT 0x00000008 -#define WD_DBG_REG_9__WD_IA_draw_eop_17__SHIFT 0x00000009 -#define WD_DBG_REG_9__WD_IA_draw_eop_18__SHIFT 0x0000000a -#define WD_DBG_REG_9__WD_IA_draw_eop_19__SHIFT 0x0000000b -#define WD_DBG_REG_9__WD_IA_draw_eop_20__SHIFT 0x0000000c -#define WD_DBG_REG_9__WD_IA_draw_eop_21__SHIFT 0x0000000d -#define WD_DBG_REG_9__WD_IA_draw_eop_22__SHIFT 0x0000000e -#define WD_DBG_REG_9__WD_IA_draw_eop_23__SHIFT 0x0000000f -#define WD_DBG_REG_9__WD_IA_draw_eop_24__SHIFT 0x00000010 -#define WD_DBG_REG_9__WD_IA_draw_eop_25__SHIFT 0x00000011 -#define WD_DBG_REG_9__WD_IA_draw_eop_26__SHIFT 0x00000012 -#define WD_DBG_REG_9__WD_IA_draw_eop_27__SHIFT 0x00000013 -#define WD_DBG_REG_9__WD_IA_draw_eop_28__SHIFT 0x00000014 -#define WD_DBG_REG_9__WD_IA_draw_eop_29__SHIFT 0x00000015 -#define WD_DBG_REG_9__WD_IA_draw_eop_30__SHIFT 0x00000016 -#define WD_DBG_REG_9__WD_IA_draw_eop_31__SHIFT 0x00000017 -#define WD_DBG_REG_9__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_10 -#define WD_DBG_REG_10__SE0VGT_WD_thdgrp_send_in__SHIFT 0x00000000 -#define WD_DBG_REG_10__wd_arb_se0_input_fifo_re__SHIFT 0x00000001 -#define WD_DBG_REG_10__wd_arb_se0_input_fifo_empty__SHIFT 0x00000002 -#define WD_DBG_REG_10__wd_arb_se0_input_fifo_full__SHIFT 0x00000003 -#define WD_DBG_REG_10__SE1VGT_WD_thdgrp_send_in__SHIFT 0x00000004 -#define WD_DBG_REG_10__wd_arb_se1_input_fifo_re__SHIFT 0x00000005 -#define WD_DBG_REG_10__wd_arb_se1_input_fifo_empty__SHIFT 0x00000006 -#define WD_DBG_REG_10__wd_arb_se1_input_fifo_full__SHIFT 0x00000007 -#define WD_DBG_REG_10__SE2VGT_WD_thdgrp_send_in__SHIFT 0x00000008 -#define WD_DBG_REG_10__wd_arb_se2_input_fifo_re__SHIFT 0x00000009 -#define WD_DBG_REG_10__wd_arb_se2_input_fifo_empty__SHIFT 0x0000000a -#define WD_DBG_REG_10__wd_arb_se2_input_fifo_full__SHIFT 0x0000000b -#define WD_DBG_REG_10__SE3VGT_WD_thdgrp_send_in__SHIFT 0x0000000c -#define WD_DBG_REG_10__wd_arb_se3_input_fifo_re__SHIFT 0x0000000d -#define WD_DBG_REG_10__wd_arb_se3_input_fifo_empty__SHIFT 0x0000000e -#define WD_DBG_REG_10__wd_arb_se3_input_fifo_full__SHIFT 0x0000000f -#define WD_DBG_REG_10__te11_arb_state_q_0__SHIFT 0x00000010 -#define WD_DBG_REG_10__te11_arb_state_q_1__SHIFT 0x00000011 -#define WD_DBG_REG_10__te11_arb_state_q_2__SHIFT 0x00000012 -#define WD_DBG_REG_10__Reserved1__SHIFT 0x00000013 -#define WD_DBG_REG_10__se0_thdgrp_is_event__SHIFT 0x00000014 -#define WD_DBG_REG_10__se0_thdgrp_eop__SHIFT 0x00000015 -#define WD_DBG_REG_10__se1_thdgrp_is_event__SHIFT 0x00000016 -#define WD_DBG_REG_10__se1_thdgrp_eop__SHIFT 0x00000017 -#define WD_DBG_REG_10__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_11 -#define WD_DBG_REG_11__se2_thdgrp_is_event__SHIFT 0x00000000 -#define WD_DBG_REG_11__se2_thdgrp_eop__SHIFT 0x00000001 -#define WD_DBG_REG_11__se3_thdgrp_is_event__SHIFT 0x00000002 -#define WD_DBG_REG_11__se3_thdgrp_eop__SHIFT 0x00000003 -#define WD_DBG_REG_11__tfreq_arb_tgroup_rtr__SHIFT 0x00000004 -#define WD_DBG_REG_11__arb_tfreq_tgroup_rts__SHIFT 0x00000005 -#define WD_DBG_REG_11__arb_tfreq_tgroup_event__SHIFT 0x00000006 -#define WD_DBG_REG_11__te11_arb_busy__SHIFT 0x00000007 -#define WD_DBG_REG_11__pipe0_dr__SHIFT 0x00000008 -#define WD_DBG_REG_11__pipe1_dr__SHIFT 0x00000009 -#define WD_DBG_REG_11__pipe0_rtr__SHIFT 0x0000000a -#define WD_DBG_REG_11__pipe1_rtr__SHIFT 0x0000000b -#define WD_DBG_REG_11__tfreq_tg_fifo_empty__SHIFT 0x0000000c -#define WD_DBG_REG_11__tfreq_tg_fifo_full__SHIFT 0x0000000d -#define WD_DBG_REG_11__tf_data_fifo_busy_q__SHIFT 0x0000000e -#define WD_DBG_REG_11__tf_data_fifo_rtr_q__SHIFT 0x0000000f -#define WD_DBG_REG_11__tf_skid_fifo_empty__SHIFT 0x00000010 -#define WD_DBG_REG_11__tf_skid_fifo_full__SHIFT 0x00000011 -#define WD_DBG_REG_11__wd_tc_rdreq_rtr_q__SHIFT 0x00000012 -#define WD_DBG_REG_11__last_req_of_tg_p2__SHIFT 0x00000013 -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_0__SHIFT 0x00000014 -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_1__SHIFT 0x00000015 -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_2__SHIFT 0x00000016 -#define WD_DBG_REG_11__se0spi_wd_hs_done_cnt_q_3__SHIFT 0x00000017 -#define WD_DBG_REG_11__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_12 -#define WD_DBG_REG_12__se0spi_wd_hs_done_cnt_q_4__SHIFT 0x00000000 -#define WD_DBG_REG_12__se0spi_wd_hs_done_cnt_q_5__SHIFT 0x00000001 -#define WD_DBG_REG_12__event_flag_p1_q__SHIFT 0x00000002 -#define WD_DBG_REG_12__null_flag_p1_q__SHIFT 0x00000003 -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_0__SHIFT 0x00000004 -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_1__SHIFT 0x00000005 -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_2__SHIFT 0x00000006 -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_3__SHIFT 0x00000007 -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_4__SHIFT 0x00000008 -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_5__SHIFT 0x00000009 -#define WD_DBG_REG_12__tf_data_fifo_cnt_q_6__SHIFT 0x0000000a -#define WD_DBG_REG_12__second_tf_ret_data_q__SHIFT 0x0000000b -#define WD_DBG_REG_12__first_req_of_tg_p1_q__SHIFT 0x0000000c -#define WD_DBG_REG_12__WD_TC_rdreq_send_out__SHIFT 0x0000000d -#define WD_DBG_REG_12__WD_TC_rdnfo_stall_out__SHIFT 0x0000000e -#define WD_DBG_REG_12__TC_WD_rdret_valid_in__SHIFT 0x0000000f -#define WD_DBG_REG_12__pipe0_dr__SHIFT 0x00000010 -#define WD_DBG_REG_12__pipec_tf_dr__SHIFT 0x00000011 -#define WD_DBG_REG_12__pipe2_dr__SHIFT 0x00000012 -#define WD_DBG_REG_12__event_or_null_flags_p0_q__SHIFT 0x00000013 -#define WD_DBG_REG_12__pipe0_rtr__SHIFT 0x00000014 -#define WD_DBG_REG_12__pipe1_rtr__SHIFT 0x00000015 -#define WD_DBG_REG_12__pipec_tf_rtr__SHIFT 0x00000016 -#define WD_DBG_REG_12__pipe2_rtr__SHIFT 0x00000017 -#define WD_DBG_REG_12__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_13 -#define WD_DBG_REG_13__ttp_patch_fifo_full__SHIFT 0x00000000 -#define WD_DBG_REG_13__ttp_patch_fifo_empty__SHIFT 0x00000001 -#define WD_DBG_REG_13__ttp_tf_fifo_empty__SHIFT 0x00000002 -#define WD_DBG_REG_13__Reserved8__SHIFT 0x00000003 -#define WD_DBG_REG_13__Reserved7__SHIFT 0x00000004 -#define WD_DBG_REG_13__Reserved6__SHIFT 0x00000005 -#define WD_DBG_REG_13__Reserved5__SHIFT 0x00000006 -#define WD_DBG_REG_13__Reserved4__SHIFT 0x00000007 -#define WD_DBG_REG_13__tf_fetch_state_q_0__SHIFT 0x00000008 -#define WD_DBG_REG_13__tf_fetch_state_q_1__SHIFT 0x00000009 -#define WD_DBG_REG_13__tf_fetch_state_q_2__SHIFT 0x0000000a -#define WD_DBG_REG_13__last_patch_of_tg__SHIFT 0x0000000b -#define WD_DBG_REG_13__tf_pointer_p0_q_0__SHIFT 0x0000000c -#define WD_DBG_REG_13__tf_pointer_p0_q_1__SHIFT 0x0000000d -#define WD_DBG_REG_13__tf_pointer_p0_q_2__SHIFT 0x0000000e -#define WD_DBG_REG_13__tf_pointer_p0_q_3__SHIFT 0x0000000f -#define WD_DBG_REG_13__dynamic_hs_p0_q__SHIFT 0x00000010 -#define WD_DBG_REG_13__first_fetch_of_tg_p0_q__SHIFT 0x00000011 -#define WD_DBG_REG_13__mem_is_even__SHIFT 0x00000012 -#define WD_DBG_REG_13__Reserved3__SHIFT 0x00000013 -#define WD_DBG_REG_13__Reserved2__SHIFT 0x00000014 -#define WD_DBG_REG_13__Reserved1__SHIFT 0x00000015 -#define WD_DBG_REG_13__pipe4_dr__SHIFT 0x00000016 -#define WD_DBG_REG_13__pipe4_rtr__SHIFT 0x00000017 -#define WD_DBG_REG_13__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_14 -#define WD_DBG_REG_14__ttp_pd_patch_rts__SHIFT 0x00000000 -#define WD_DBG_REG_14__ttp_pd_is_event__SHIFT 0x00000001 -#define WD_DBG_REG_14__ttp_pd_eopg__SHIFT 0x00000002 -#define WD_DBG_REG_14__ttp_pd_eop__SHIFT 0x00000003 -#define WD_DBG_REG_14__pipe0_dr__SHIFT 0x00000004 -#define WD_DBG_REG_14__pipe1_dr__SHIFT 0x00000005 -#define WD_DBG_REG_14__pipe0_rtr__SHIFT 0x00000006 -#define WD_DBG_REG_14__pipe1_rtr__SHIFT 0x00000007 -#define WD_DBG_REG_14__donut_en_p1_q__SHIFT 0x00000008 -#define WD_DBG_REG_14__donut_se_switch_p2__SHIFT 0x00000009 -#define WD_DBG_REG_14__patch_se_switch_p2__SHIFT 0x0000000a -#define WD_DBG_REG_14__last_donut_switch_p2__SHIFT 0x0000000b -#define WD_DBG_REG_14__last_donut_of_patch_p2__SHIFT 0x0000000c -#define WD_DBG_REG_14__is_event_p1_q__SHIFT 0x0000000d -#define WD_DBG_REG_14__eopg_p1_q__SHIFT 0x0000000e -#define WD_DBG_REG_14__eop_p1_q__SHIFT 0x0000000f -#define WD_DBG_REG_14__patch_accum_q_0__SHIFT 0x00000010 -#define WD_DBG_REG_14__patch_accum_q_1__SHIFT 0x00000011 -#define WD_DBG_REG_14__patch_accum_q_2__SHIFT 0x00000012 -#define WD_DBG_REG_14__patch_accum_q_3__SHIFT 0x00000013 -#define WD_DBG_REG_14__patch_accum_q_4__SHIFT 0x00000014 -#define WD_DBG_REG_14__patch_accum_q_5__SHIFT 0x00000015 -#define WD_DBG_REG_14__patch_accum_q_6__SHIFT 0x00000016 -#define WD_DBG_REG_14__patch_accum_q_7__SHIFT 0x00000017 -#define WD_DBG_REG_14__Reserved0__SHIFT 0x00000018 - -// WD_DBG_REG_15 -#define WD_DBG_REG_15__wd_te11_out_se0_fifo_full__SHIFT 0x00000000 -#define WD_DBG_REG_15__wd_te11_out_se0_fifo_empty__SHIFT 0x00000001 -#define WD_DBG_REG_15__wd_te11_out_se1_fifo_full__SHIFT 0x00000002 -#define WD_DBG_REG_15__wd_te11_out_se1_fifo_empty__SHIFT 0x00000003 -#define WD_DBG_REG_15__wd_te11_out_se2_fifo_full__SHIFT 0x00000004 -#define WD_DBG_REG_15__wd_te11_out_se2_fifo_empty__SHIFT 0x00000005 -#define WD_DBG_REG_15__wd_te11_out_se3_fifo_full__SHIFT 0x00000006 -#define WD_DBG_REG_15__wd_te11_out_se3_fifo_empty__SHIFT 0x00000007 -#define WD_DBG_REG_15__Reserved15__SHIFT 0x00000008 -#define WD_DBG_REG_15__Reserved14__SHIFT 0x00000009 -#define WD_DBG_REG_15__Reserved13__SHIFT 0x0000000a -#define WD_DBG_REG_15__Reserved12__SHIFT 0x0000000b -#define WD_DBG_REG_15__Reserved11__SHIFT 0x0000000c -#define WD_DBG_REG_15__Reserved10__SHIFT 0x0000000d -#define WD_DBG_REG_15__Reserved9__SHIFT 0x0000000e -#define WD_DBG_REG_15__Reserved8__SHIFT 0x0000000f -#define WD_DBG_REG_15__Reserved7__SHIFT 0x00000010 -#define WD_DBG_REG_15__Reserved6__SHIFT 0x00000011 -#define WD_DBG_REG_15__Reserved5__SHIFT 0x00000012 -#define WD_DBG_REG_15__Reserved4__SHIFT 0x00000013 -#define WD_DBG_REG_15__Reserved3__SHIFT 0x00000014 -#define WD_DBG_REG_15__Reserved2__SHIFT 0x00000015 -#define WD_DBG_REG_15__Reserved1__SHIFT 0x00000016 -#define WD_DBG_REG_15__Reserved0__SHIFT 0x0000001f - -// IA_DBG_REG_0 -#define IA_DBG_REG_0__ia_busy_extended__SHIFT 0x00000000 -#define IA_DBG_REG_0__ia_nodma_busy_extended__SHIFT 0x00000001 -#define IA_DBG_REG_0__ia_busy__SHIFT 0x00000002 -#define IA_DBG_REG_0__ia_nodma_busy__SHIFT 0x00000003 -#define IA_DBG_REG_0__Reserved11__SHIFT 0x00000004 -#define IA_DBG_REG_0__dma_req_busy__SHIFT 0x00000005 -#define IA_DBG_REG_0__dma_busy__SHIFT 0x00000006 -#define IA_DBG_REG_0__mc_xl8r_busy__SHIFT 0x00000007 -#define IA_DBG_REG_0__grp_busy__SHIFT 0x00000008 -#define IA_DBG_REG_0__Reserved10__SHIFT 0x00000009 -#define IA_DBG_REG_0__dma_grp_valid__SHIFT 0x0000000a -#define IA_DBG_REG_0__grp_dma_read__SHIFT 0x0000000b -#define IA_DBG_REG_0__dma_grp_hp_valid__SHIFT 0x0000000c -#define IA_DBG_REG_0__grp_dma_hp_read__SHIFT 0x0000000d -#define IA_DBG_REG_0__Reserved9__SHIFT 0x0000000e -#define IA_DBG_REG_0__Reserved8__SHIFT 0x0000000f -#define IA_DBG_REG_0__Reserved7__SHIFT 0x00000010 -#define IA_DBG_REG_0__Reserved6__SHIFT 0x00000011 -#define IA_DBG_REG_0__Reserved5__SHIFT 0x00000012 -#define IA_DBG_REG_0__Reserved4__SHIFT 0x00000013 -#define IA_DBG_REG_0__Reserved3__SHIFT 0x00000014 -#define IA_DBG_REG_0__Reserved2__SHIFT 0x00000015 -#define IA_DBG_REG_0__Reserved1__SHIFT 0x00000016 -#define IA_DBG_REG_0__Reserved0__SHIFT 0x0000001f - -// IA_DBG_REG_1 -#define IA_DBG_REG_1__reg_clk_busy__SHIFT 0x00000000 -#define IA_DBG_REG_1__core_clk_busy__SHIFT 0x00000001 -#define IA_DBG_REG_1__Reserved4__SHIFT 0x00000002 -#define IA_DBG_REG_1__Reserved3__SHIFT 0x00000003 -#define IA_DBG_REG_1__sclk_reg_vld__SHIFT 0x00000004 -#define IA_DBG_REG_1__sclk_core_vld__SHIFT 0x00000005 -#define IA_DBG_REG_1__Reserved2__SHIFT 0x00000006 -#define IA_DBG_REG_1__Reserved1__SHIFT 0x00000007 -#define IA_DBG_REG_1__dma_input_fifo_empty__SHIFT 0x00000008 -#define IA_DBG_REG_1__dma_input_fifo_full__SHIFT 0x00000009 -#define IA_DBG_REG_1__start_new_packet__SHIFT 0x0000000a -#define IA_DBG_REG_1__dma_rdreq_dr_q__SHIFT 0x0000000b -#define IA_DBG_REG_1__dma_zero_indices_q__SHIFT 0x0000000c -#define IA_DBG_REG_1__dma_buf_type_q__SHIFT 0x0000000d -#define IA_DBG_REG_1__dma_req_path_q__SHIFT 0x0000000f -#define IA_DBG_REG_1__discard_1st_chunk__SHIFT 0x00000010 -#define IA_DBG_REG_1__discard_2nd_chunk__SHIFT 0x00000011 -#define IA_DBG_REG_1__second_tc_ret_data_q__SHIFT 0x00000012 -#define IA_DBG_REG_1__dma_tc_ret_sel_q__SHIFT 0x00000013 -#define IA_DBG_REG_1__last_rdreq_in_dma_op__SHIFT 0x00000014 -#define IA_DBG_REG_1__dma_mask_fifo_empty__SHIFT 0x00000015 -#define IA_DBG_REG_1__dma_data_fifo_empty_q__SHIFT 0x00000016 -#define IA_DBG_REG_1__dma_data_fifo_full__SHIFT 0x00000017 -#define IA_DBG_REG_1__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_2 -#define IA_DBG_REG_2__dma_req_fifo_empty__SHIFT 0x00000000 -#define IA_DBG_REG_2__dma_req_fifo_full__SHIFT 0x00000001 -#define IA_DBG_REG_2__stage2_dr__SHIFT 0x00000002 -#define IA_DBG_REG_2__stage2_rtr__SHIFT 0x00000003 -#define IA_DBG_REG_2__stage3_dr__SHIFT 0x00000004 -#define IA_DBG_REG_2__stage3_rtr__SHIFT 0x00000005 -#define IA_DBG_REG_2__stage4_dr__SHIFT 0x00000006 -#define IA_DBG_REG_2__stage4_rtr__SHIFT 0x00000007 -#define IA_DBG_REG_2__dma_skid_fifo_empty__SHIFT 0x00000008 -#define IA_DBG_REG_2__dma_skid_fifo_full__SHIFT 0x00000009 -#define IA_DBG_REG_2__dma_grp_valid__SHIFT 0x0000000a -#define IA_DBG_REG_2__grp_dma_read__SHIFT 0x0000000b -#define IA_DBG_REG_2__current_data_valid__SHIFT 0x0000000c -#define IA_DBG_REG_2__out_of_range_r2_q__SHIFT 0x0000000d -#define IA_DBG_REG_2__dma_mask_fifo_we__SHIFT 0x0000000e -#define IA_DBG_REG_2__dma_ret_data_we_q__SHIFT 0x0000000f -#define IA_DBG_REG_2__hp_dma_input_fifo_empty__SHIFT 0x00000010 -#define IA_DBG_REG_2__hp_dma_input_fifo_full__SHIFT 0x00000011 -#define IA_DBG_REG_2__hp_start_new_packet__SHIFT 0x00000012 -#define IA_DBG_REG_2__hp_dma_rdreq_dr_q__SHIFT 0x00000013 -#define IA_DBG_REG_2__hp_dma_zero_indices_q__SHIFT 0x00000014 -#define IA_DBG_REG_2__hp_dma_buf_type_q_0__SHIFT 0x00000015 -#define IA_DBG_REG_2__hp_dma_buf_type_q_1__SHIFT 0x00000016 -#define IA_DBG_REG_2__hp_dma_req_path_q__SHIFT 0x00000017 -#define IA_DBG_REG_2__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_3 -#define IA_DBG_REG_3__hp_discard_1st_chunk__SHIFT 0x00000000 -#define IA_DBG_REG_3__hp_discard_2nd_chunk__SHIFT 0x00000001 -#define IA_DBG_REG_3__hp_second_tc_ret_data_q__SHIFT 0x00000002 -#define IA_DBG_REG_3__hp_dma_tc_ret_sel_q__SHIFT 0x00000003 -#define IA_DBG_REG_3__hp_last_rdreq_in_dma_op__SHIFT 0x00000004 -#define IA_DBG_REG_3__hp_dma_mask_fifo_empty__SHIFT 0x00000005 -#define IA_DBG_REG_3__hp_dma_data_fifo_empty_q__SHIFT 0x00000006 -#define IA_DBG_REG_3__hp_dma_data_fifo_full__SHIFT 0x00000007 -#define IA_DBG_REG_3__hp_dma_req_fifo_empty__SHIFT 0x00000008 -#define IA_DBG_REG_3__hp_dma_req_fifo_full__SHIFT 0x00000009 -#define IA_DBG_REG_3__hp_stage2_dr__SHIFT 0x0000000a -#define IA_DBG_REG_3__hp_stage2_rtr__SHIFT 0x0000000b -#define IA_DBG_REG_3__hp_stage3_dr__SHIFT 0x0000000c -#define IA_DBG_REG_3__hp_stage3_rtr__SHIFT 0x0000000d -#define IA_DBG_REG_3__hp_stage4_dr__SHIFT 0x0000000e -#define IA_DBG_REG_3__hp_stage4_rtr__SHIFT 0x0000000f -#define IA_DBG_REG_3__hp_dma_skid_fifo_empty__SHIFT 0x00000010 -#define IA_DBG_REG_3__hp_dma_skid_fifo_full__SHIFT 0x00000011 -#define IA_DBG_REG_3__hp_dma_grp_valid__SHIFT 0x00000012 -#define IA_DBG_REG_3__hp_grp_dma_read__SHIFT 0x00000013 -#define IA_DBG_REG_3__hp_current_data_valid__SHIFT 0x00000014 -#define IA_DBG_REG_3__hp_out_of_range_r2_q__SHIFT 0x00000015 -#define IA_DBG_REG_3__hp_dma_mask_fifo_we__SHIFT 0x00000016 -#define IA_DBG_REG_3__hp_dma_ret_data_we_q__SHIFT 0x00000017 -#define IA_DBG_REG_3__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_4 -#define IA_DBG_REG_4__dma_pipe0_rdreq_valid__SHIFT 0x00000000 -#define IA_DBG_REG_4__dma_pipe0_rdreq_read__SHIFT 0x00000001 -#define IA_DBG_REG_4__dma_pipe0_rdreq_null_out__SHIFT 0x00000002 -#define IA_DBG_REG_4__dma_pipe0_rdreq_eop_out__SHIFT 0x00000003 -#define IA_DBG_REG_4__dma_pipe0_rdreq_use_tc_out__SHIFT 0x00000004 -#define IA_DBG_REG_4__grp_dma_draw_is_pipe0__SHIFT 0x00000005 -#define IA_DBG_REG_4__must_service_pipe0_req__SHIFT 0x00000006 -#define IA_DBG_REG_4__send_pipe1_req__SHIFT 0x00000007 -#define IA_DBG_REG_4__dma_pipe1_rdreq_valid__SHIFT 0x00000008 -#define IA_DBG_REG_4__dma_pipe1_rdreq_read__SHIFT 0x00000009 -#define IA_DBG_REG_4__dma_pipe1_rdreq_null_out__SHIFT 0x0000000a -#define IA_DBG_REG_4__dma_pipe1_rdreq_eop_out__SHIFT 0x0000000b -#define IA_DBG_REG_4__dma_pipe1_rdreq_use_tc_out__SHIFT 0x0000000c -#define IA_DBG_REG_4__ia_mc_rdreq_rtr_q__SHIFT 0x0000000d -#define IA_DBG_REG_4__mc_out_rtr__SHIFT 0x0000000e -#define IA_DBG_REG_4__dma_rdreq_send_out__SHIFT 0x0000000f -#define IA_DBG_REG_4__pipe0_dr__SHIFT 0x00000010 -#define IA_DBG_REG_4__pipe0_rtr__SHIFT 0x00000011 -#define IA_DBG_REG_4__ia_tc_rdreq_rtr_q__SHIFT 0x00000012 -#define IA_DBG_REG_4__tc_out_rtr__SHIFT 0x00000013 -#define IA_DBG_REG_4__pair0_valid_p1__SHIFT 0x00000014 -#define IA_DBG_REG_4__pair1_valid_p1__SHIFT 0x00000015 -#define IA_DBG_REG_4__pair2_valid_p1__SHIFT 0x00000016 -#define IA_DBG_REG_4__pair3_valid_p1__SHIFT 0x00000017 -#define IA_DBG_REG_4__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_5 -#define IA_DBG_REG_5__tc_req_count_q_0__SHIFT 0x00000000 -#define IA_DBG_REG_5__tc_req_count_q_1__SHIFT 0x00000001 -#define IA_DBG_REG_5__discard_1st_chunk__SHIFT 0x00000002 -#define IA_DBG_REG_5__discard_2nd_chunk__SHIFT 0x00000003 -#define IA_DBG_REG_5__last_tc_req_p1__SHIFT 0x00000004 -#define IA_DBG_REG_5__IA_TC_rdreq_send_out__SHIFT 0x00000005 -#define IA_DBG_REG_5__TC_IA_rdret_valid_in__SHIFT 0x00000006 -#define IA_DBG_REG_5__TAP_IA_rdret_vld_in__SHIFT 0x00000007 -#define IA_DBG_REG_5__pipe0_dr__SHIFT 0x00000008 -#define IA_DBG_REG_5__pipe1_dr__SHIFT 0x00000009 -#define IA_DBG_REG_5__pipe2_dr__SHIFT 0x0000000a -#define IA_DBG_REG_5__pipe3_dr__SHIFT 0x0000000b -#define IA_DBG_REG_5__pipe4_dr__SHIFT 0x0000000c -#define IA_DBG_REG_5__pipe5_dr__SHIFT 0x0000000d -#define IA_DBG_REG_5__grp_se0_fifo_empty__SHIFT 0x0000000e -#define IA_DBG_REG_5__grp_se0_fifo_full__SHIFT 0x0000000f -#define IA_DBG_REG_5__pipe0_rtr__SHIFT 0x00000010 -#define IA_DBG_REG_5__pipe1_rtr__SHIFT 0x00000011 -#define IA_DBG_REG_5__pipe2_rtr__SHIFT 0x00000012 -#define IA_DBG_REG_5__pipe3_rtr__SHIFT 0x00000013 -#define IA_DBG_REG_5__pipe4_rtr__SHIFT 0x00000014 -#define IA_DBG_REG_5__pipe5_rtr__SHIFT 0x00000015 -#define IA_DBG_REG_5__ia_vgt_prim_rtr_q__SHIFT 0x00000016 -#define IA_DBG_REG_5__ia_se1vgt_prim_rtr_q__SHIFT 0x00000017 -#define IA_DBG_REG_5__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_6 -#define IA_DBG_REG_6__di_major_mode_p1_q__SHIFT 0x00000000 -#define IA_DBG_REG_6__gs_mode_p1_q_0__SHIFT 0x00000001 -#define IA_DBG_REG_6__gs_mode_p1_q_1__SHIFT 0x00000002 -#define IA_DBG_REG_6__gs_mode_p1_q_2__SHIFT 0x00000003 -#define IA_DBG_REG_6__di_event_flag_p1_q__SHIFT 0x00000004 -#define IA_DBG_REG_6__di_state_sel_p1_q_0__SHIFT 0x00000005 -#define IA_DBG_REG_6__di_state_sel_p1_q_1__SHIFT 0x00000006 -#define IA_DBG_REG_6__di_state_sel_p1_q_2__SHIFT 0x00000007 -#define IA_DBG_REG_6__draw_opaq_en_p1_q__SHIFT 0x00000008 -#define IA_DBG_REG_6__draw_opaq_active_q__SHIFT 0x00000009 -#define IA_DBG_REG_6__di_source_select_p1_q_0__SHIFT 0x0000000a -#define IA_DBG_REG_6__di_source_select_p1_q_1__SHIFT 0x0000000b -#define IA_DBG_REG_6__ready_to_read_di__SHIFT 0x0000000c -#define IA_DBG_REG_6__di_first_group_of_draw_q__SHIFT 0x0000000d -#define IA_DBG_REG_6__last_shift_of_draw__SHIFT 0x0000000e -#define IA_DBG_REG_6__current_shift_is_vect1_q__SHIFT 0x0000000f -#define IA_DBG_REG_6__di_index_counter_q_15_0_0__SHIFT 0x00000010 -#define IA_DBG_REG_6__di_index_counter_q_15_0_1__SHIFT 0x00000011 -#define IA_DBG_REG_6__di_index_counter_q_15_0_2__SHIFT 0x00000012 -#define IA_DBG_REG_6__di_index_counter_q_15_0_3__SHIFT 0x00000013 -#define IA_DBG_REG_6__di_index_counter_q_15_0_4__SHIFT 0x00000014 -#define IA_DBG_REG_6__di_index_counter_q_15_0_5__SHIFT 0x00000015 -#define IA_DBG_REG_6__di_index_counter_q_15_0_6__SHIFT 0x00000016 -#define IA_DBG_REG_6__di_index_counter_q_15_0_7__SHIFT 0x00000017 -#define IA_DBG_REG_6__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_7 -#define IA_DBG_REG_7__di_index_counter_q_15_0_8__SHIFT 0x00000000 -#define IA_DBG_REG_7__di_index_counter_q_15_0_9__SHIFT 0x00000001 -#define IA_DBG_REG_7__di_index_counter_q_15_0_10__SHIFT 0x00000002 -#define IA_DBG_REG_7__di_index_counter_q_15_0_11__SHIFT 0x00000003 -#define IA_DBG_REG_7__di_index_counter_q_15_0_12__SHIFT 0x00000004 -#define IA_DBG_REG_7__di_index_counter_q_15_0_13__SHIFT 0x00000005 -#define IA_DBG_REG_7__di_index_counter_q_15_0_14__SHIFT 0x00000006 -#define IA_DBG_REG_7__di_index_counter_q_15_0_15__SHIFT 0x00000007 -#define IA_DBG_REG_7__instanceid_13_0_0__SHIFT 0x00000008 -#define IA_DBG_REG_7__instanceid_13_0_1__SHIFT 0x00000009 -#define IA_DBG_REG_7__instanceid_13_0_2__SHIFT 0x0000000a -#define IA_DBG_REG_7__instanceid_13_0_3__SHIFT 0x0000000b -#define IA_DBG_REG_7__instanceid_13_0_4__SHIFT 0x0000000c -#define IA_DBG_REG_7__instanceid_13_0_5__SHIFT 0x0000000d -#define IA_DBG_REG_7__instanceid_13_0_6__SHIFT 0x0000000e -#define IA_DBG_REG_7__instanceid_13_0_7__SHIFT 0x0000000f -#define IA_DBG_REG_7__instanceid_13_0_8__SHIFT 0x00000010 -#define IA_DBG_REG_7__instanceid_13_0_9__SHIFT 0x00000011 -#define IA_DBG_REG_7__instanceid_13_0_10__SHIFT 0x00000012 -#define IA_DBG_REG_7__instanceid_13_0_11__SHIFT 0x00000013 -#define IA_DBG_REG_7__instanceid_13_0_12__SHIFT 0x00000014 -#define IA_DBG_REG_7__instanceid_13_0_13__SHIFT 0x00000015 -#define IA_DBG_REG_7__draw_input_fifo_full__SHIFT 0x00000016 -#define IA_DBG_REG_7__draw_input_fifo_empty__SHIFT 0x00000017 -#define IA_DBG_REG_7__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_8 -#define IA_DBG_REG_8__current_shift_q_0__SHIFT 0x00000000 -#define IA_DBG_REG_8__current_shift_q_1__SHIFT 0x00000001 -#define IA_DBG_REG_8__current_shift_q_2__SHIFT 0x00000002 -#define IA_DBG_REG_8__current_shift_q_3__SHIFT 0x00000003 -#define IA_DBG_REG_8__current_stride_pre_0__SHIFT 0x00000004 -#define IA_DBG_REG_8__current_stride_pre_1__SHIFT 0x00000005 -#define IA_DBG_REG_8__current_stride_pre_2__SHIFT 0x00000006 -#define IA_DBG_REG_8__current_stride_pre_3__SHIFT 0x00000007 -#define IA_DBG_REG_8__current_stride_q_0__SHIFT 0x00000008 -#define IA_DBG_REG_8__current_stride_q_1__SHIFT 0x00000009 -#define IA_DBG_REG_8__current_stride_q_2__SHIFT 0x0000000a -#define IA_DBG_REG_8__current_stride_q_3__SHIFT 0x0000000b -#define IA_DBG_REG_8__current_stride_q_4__SHIFT 0x0000000c -#define IA_DBG_REG_8__first_group_partial__SHIFT 0x0000000d -#define IA_DBG_REG_8__second_group_partial__SHIFT 0x0000000e -#define IA_DBG_REG_8__curr_prim_partial__SHIFT 0x0000000f -#define IA_DBG_REG_8__next_stride_q_0__SHIFT 0x00000010 -#define IA_DBG_REG_8__next_stride_q_1__SHIFT 0x00000011 -#define IA_DBG_REG_8__next_stride_q_2__SHIFT 0x00000012 -#define IA_DBG_REG_8__next_stride_q_3__SHIFT 0x00000013 -#define IA_DBG_REG_8__next_stride_q_4__SHIFT 0x00000014 -#define IA_DBG_REG_8__next_group_partial__SHIFT 0x00000015 -#define IA_DBG_REG_8__after_group_partial__SHIFT 0x00000016 -#define IA_DBG_REG_8__extract_group__SHIFT 0x00000017 -#define IA_DBG_REG_8__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_9 -#define IA_DBG_REG_9__grp_shift_debug_data_0__SHIFT 0x00000000 -#define IA_DBG_REG_9__grp_shift_debug_data_1__SHIFT 0x00000001 -#define IA_DBG_REG_9__grp_shift_debug_data_2__SHIFT 0x00000002 -#define IA_DBG_REG_9__grp_shift_debug_data_3__SHIFT 0x00000003 -#define IA_DBG_REG_9__grp_shift_debug_data_4__SHIFT 0x00000004 -#define IA_DBG_REG_9__grp_shift_debug_data_5__SHIFT 0x00000005 -#define IA_DBG_REG_9__grp_shift_debug_data_6__SHIFT 0x00000006 -#define IA_DBG_REG_9__grp_shift_debug_data_7__SHIFT 0x00000007 -#define IA_DBG_REG_9__reset_indx_state_q_0__SHIFT 0x00000008 -#define IA_DBG_REG_9__reset_indx_state_q_1__SHIFT 0x00000009 -#define IA_DBG_REG_9__reset_indx_state_q_2__SHIFT 0x0000000a -#define IA_DBG_REG_9__reset_indx_state_q_3__SHIFT 0x0000000b -#define IA_DBG_REG_9__shift_vect_valid_p2_q_0__SHIFT 0x0000000c -#define IA_DBG_REG_9__shift_vect_valid_p2_q_1__SHIFT 0x0000000d -#define IA_DBG_REG_9__shift_vect_valid_p2_q_2__SHIFT 0x0000000e -#define IA_DBG_REG_9__shift_vect_valid_p2_q_3__SHIFT 0x0000000f -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_0__SHIFT 0x00000010 -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_1__SHIFT 0x00000011 -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_2__SHIFT 0x00000012 -#define IA_DBG_REG_9__shift_vect1_valid_p2_q_3__SHIFT 0x00000013 -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_0__SHIFT 0x00000014 -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_1__SHIFT 0x00000015 -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_2__SHIFT 0x00000016 -#define IA_DBG_REG_9__shift_vect0_reset_match_p2_q_3__SHIFT 0x00000017 -#define IA_DBG_REG_9__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_10 -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_0__SHIFT 0x00000000 -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_1__SHIFT 0x00000001 -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_2__SHIFT 0x00000002 -#define IA_DBG_REG_10__shift_vect1_reset_match_p2_q_3__SHIFT 0x00000003 -#define IA_DBG_REG_10__num_indx_in_group_p2_q_0__SHIFT 0x00000004 -#define IA_DBG_REG_10__num_indx_in_group_p2_q_1__SHIFT 0x00000005 -#define IA_DBG_REG_10__num_indx_in_group_p2_q_2__SHIFT 0x00000006 -#define IA_DBG_REG_10__last_group_of_draw_p2_q__SHIFT 0x00000007 -#define IA_DBG_REG_10__shift_event_flag_p2_q__SHIFT 0x00000008 -#define IA_DBG_REG_10__indx_shift_is_one_p2_q__SHIFT 0x00000009 -#define IA_DBG_REG_10__indx_shift_is_two_p2_q__SHIFT 0x0000000a -#define IA_DBG_REG_10__indx_stride_is_four_p2_q__SHIFT 0x0000000b -#define IA_DBG_REG_10__shift_prim1_reset_p3_q__SHIFT 0x0000000c -#define IA_DBG_REG_10__shift_prim1_partial_p3_q__SHIFT 0x0000000d -#define IA_DBG_REG_10__shift_prim0_reset_p3_q__SHIFT 0x0000000e -#define IA_DBG_REG_10__shift_prim0_partial_p3_q__SHIFT 0x0000000f -#define IA_DBG_REG_10__di_prim_type_p1_q_0__SHIFT 0x00000010 -#define IA_DBG_REG_10__di_prim_type_p1_q_1__SHIFT 0x00000011 -#define IA_DBG_REG_10__di_prim_type_p1_q_2__SHIFT 0x00000012 -#define IA_DBG_REG_10__di_prim_type_p1_q_3__SHIFT 0x00000013 -#define IA_DBG_REG_10__di_prim_type_p1_q_4__SHIFT 0x00000014 -#define IA_DBG_REG_10__two_cycle_xfer_p1_q__SHIFT 0x00000015 -#define IA_DBG_REG_10__two_prim_input_p1_q__SHIFT 0x00000016 -#define IA_DBG_REG_10__shift_vect_end_of_packet_p5_q__SHIFT 0x00000017 -#define IA_DBG_REG_10__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_11 -#define IA_DBG_REG_11__last_group_of_inst_p5_q__SHIFT 0x00000000 -#define IA_DBG_REG_11__shift_prim1_null_flag_p5_q__SHIFT 0x00000001 -#define IA_DBG_REG_11__shift_prim0_null_flag_p5_q__SHIFT 0x00000002 -#define IA_DBG_REG_11__grp_continued__SHIFT 0x00000003 -#define IA_DBG_REG_11__grp_state_sel_0__SHIFT 0x00000004 -#define IA_DBG_REG_11__grp_state_sel_1__SHIFT 0x00000005 -#define IA_DBG_REG_11__grp_state_sel_2__SHIFT 0x00000006 -#define IA_DBG_REG_11__grp_sub_prim_type_0__SHIFT 0x00000007 -#define IA_DBG_REG_11__grp_sub_prim_type_1__SHIFT 0x00000008 -#define IA_DBG_REG_11__grp_sub_prim_type_2__SHIFT 0x00000009 -#define IA_DBG_REG_11__grp_sub_prim_type_3__SHIFT 0x0000000a -#define IA_DBG_REG_11__grp_sub_prim_type_4__SHIFT 0x0000000b -#define IA_DBG_REG_11__grp_sub_prim_type_5__SHIFT 0x0000000c -#define IA_DBG_REG_11__grp_output_path_0__SHIFT 0x0000000d -#define IA_DBG_REG_11__grp_output_path_1__SHIFT 0x0000000e -#define IA_DBG_REG_11__grp_output_path_2__SHIFT 0x0000000f -#define IA_DBG_REG_11__grp_null_primitive__SHIFT 0x00000010 -#define IA_DBG_REG_11__grp_eop__SHIFT 0x00000011 -#define IA_DBG_REG_11__grp_eopg__SHIFT 0x00000012 -#define IA_DBG_REG_11__grp_event_flag__SHIFT 0x00000013 -#define IA_DBG_REG_11__grp_components_valid_0__SHIFT 0x00000014 -#define IA_DBG_REG_11__grp_components_valid_1__SHIFT 0x00000015 -#define IA_DBG_REG_11__grp_components_valid_2__SHIFT 0x00000016 -#define IA_DBG_REG_11__grp_components_valid_3__SHIFT 0x00000017 -#define IA_DBG_REG_11__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_12 -#define IA_DBG_REG_12__send_to_se1_p6__SHIFT 0x00000000 -#define IA_DBG_REG_12__gfx_se_switch_p6__SHIFT 0x00000001 -#define IA_DBG_REG_12__null_eoi_xfer_prim1_p6__SHIFT 0x00000002 -#define IA_DBG_REG_12__null_eoi_xfer_prim0_p6__SHIFT 0x00000003 -#define IA_DBG_REG_12__prim1_eoi_p6__SHIFT 0x00000004 -#define IA_DBG_REG_12__prim0_eoi_p6__SHIFT 0x00000005 -#define IA_DBG_REG_12__prim1_valid_eopg_p6__SHIFT 0x00000006 -#define IA_DBG_REG_12__prim0_valid_eopg_p6__SHIFT 0x00000007 -#define IA_DBG_REG_12__prim1_to_other_se_p6__SHIFT 0x00000008 -#define IA_DBG_REG_12__eopg_on_last_prim_p6__SHIFT 0x00000009 -#define IA_DBG_REG_12__eopg_between_prims_p6__SHIFT 0x0000000a -#define IA_DBG_REG_12__prim_count_eq_group_size_p6__SHIFT 0x0000000b -#define IA_DBG_REG_12__prim_count_gt_group_size_p6__SHIFT 0x0000000c -#define IA_DBG_REG_12__two_prim_output_p5_q__SHIFT 0x0000000d -#define IA_DBG_REG_12__Reserved2__SHIFT 0x0000000e -#define IA_DBG_REG_12__Reserved1__SHIFT 0x0000000f -#define IA_DBG_REG_12__shift_vect_end_of_packet_p5_q__SHIFT 0x00000010 -#define IA_DBG_REG_12__prim1_xfer_p6__SHIFT 0x00000011 -#define IA_DBG_REG_12__grp_se1_fifo_empty__SHIFT 0x00000012 -#define IA_DBG_REG_12__grp_se1_fifo_full__SHIFT 0x00000013 -#define IA_DBG_REG_12__prim_counter_q_0__SHIFT 0x00000014 -#define IA_DBG_REG_12__prim_counter_q_1__SHIFT 0x00000015 -#define IA_DBG_REG_12__prim_counter_q_2__SHIFT 0x00000016 -#define IA_DBG_REG_12__prim_counter_q_3__SHIFT 0x00000017 -#define IA_DBG_REG_12__Reserved0__SHIFT 0x00000018 - -// IA_DBG_REG_13 -#define IA_DBG_REG_13__prim_counter_q_0__SHIFT 0x00000000 -#define IA_DBG_REG_13__prim_counter_q_1__SHIFT 0x00000001 -#define IA_DBG_REG_13__prim_counter_q_2__SHIFT 0x00000002 -#define IA_DBG_REG_13__prim_counter_q_3__SHIFT 0x00000003 -#define IA_DBG_REG_13__prim_counter_q_4__SHIFT 0x00000004 -#define IA_DBG_REG_13__prim_counter_q_5__SHIFT 0x00000005 -#define IA_DBG_REG_13__prim_counter_q_6__SHIFT 0x00000006 -#define IA_DBG_REG_13__prim_counter_q_7__SHIFT 0x00000007 -#define IA_DBG_REG_13__Reserved15__SHIFT 0x00000008 -#define IA_DBG_REG_13__Reserved14__SHIFT 0x00000009 -#define IA_DBG_REG_13__Reserved13__SHIFT 0x0000000a -#define IA_DBG_REG_13__Reserved12__SHIFT 0x0000000b -#define IA_DBG_REG_13__Reserved11__SHIFT 0x0000000c -#define IA_DBG_REG_13__Reserved10__SHIFT 0x0000000d -#define IA_DBG_REG_13__Reserved9__SHIFT 0x0000000e -#define IA_DBG_REG_13__Reserved8__SHIFT 0x0000000f -#define IA_DBG_REG_13__Reserved7__SHIFT 0x00000010 -#define IA_DBG_REG_13__Reserved6__SHIFT 0x00000011 -#define IA_DBG_REG_13__Reserved5__SHIFT 0x00000012 -#define IA_DBG_REG_13__Reserved4__SHIFT 0x00000013 -#define IA_DBG_REG_13__Reserved3__SHIFT 0x00000014 -#define IA_DBG_REG_13__Reserved2__SHIFT 0x00000015 -#define IA_DBG_REG_13__Reserved1__SHIFT 0x00000016 -#define IA_DBG_REG_13__Reserved0__SHIFT 0x0000001f - -// IA_DBG_REG_14 -#define IA_DBG_REG_14__Reserved23__SHIFT 0x00000000 -#define IA_DBG_REG_14__Reserved22__SHIFT 0x00000001 -#define IA_DBG_REG_14__Reserved21__SHIFT 0x00000002 -#define IA_DBG_REG_14__Reserved20__SHIFT 0x00000003 -#define IA_DBG_REG_14__Reserved19__SHIFT 0x00000004 -#define IA_DBG_REG_14__Reserved18__SHIFT 0x00000005 -#define IA_DBG_REG_14__Reserved17__SHIFT 0x00000006 -#define IA_DBG_REG_14__Reserved16__SHIFT 0x00000007 -#define IA_DBG_REG_14__Reserved15__SHIFT 0x00000008 -#define IA_DBG_REG_14__Reserved14__SHIFT 0x00000009 -#define IA_DBG_REG_14__Reserved13__SHIFT 0x0000000a -#define IA_DBG_REG_14__Reserved12__SHIFT 0x0000000b -#define IA_DBG_REG_14__Reserved11__SHIFT 0x0000000c -#define IA_DBG_REG_14__Reserved10__SHIFT 0x0000000d -#define IA_DBG_REG_14__Reserved9__SHIFT 0x0000000e -#define IA_DBG_REG_14__Reserved8__SHIFT 0x0000000f -#define IA_DBG_REG_14__Reserved7__SHIFT 0x00000010 -#define IA_DBG_REG_14__Reserved6__SHIFT 0x00000011 -#define IA_DBG_REG_14__Reserved5__SHIFT 0x00000012 -#define IA_DBG_REG_14__Reserved4__SHIFT 0x00000013 -#define IA_DBG_REG_14__Reserved3__SHIFT 0x00000014 -#define IA_DBG_REG_14__Reserved2__SHIFT 0x00000015 -#define IA_DBG_REG_14__Reserved1__SHIFT 0x00000016 -#define IA_DBG_REG_14__Reserved0__SHIFT 0x0000001f - -// IA_DBG_REG_15 -#define IA_DBG_REG_15__Reserved23__SHIFT 0x00000000 -#define IA_DBG_REG_15__Reserved22__SHIFT 0x00000001 -#define IA_DBG_REG_15__Reserved21__SHIFT 0x00000002 -#define IA_DBG_REG_15__Reserved20__SHIFT 0x00000003 -#define IA_DBG_REG_15__Reserved19__SHIFT 0x00000004 -#define IA_DBG_REG_15__Reserved18__SHIFT 0x00000005 -#define IA_DBG_REG_15__Reserved17__SHIFT 0x00000006 -#define IA_DBG_REG_15__Reserved16__SHIFT 0x00000007 -#define IA_DBG_REG_15__Reserved15__SHIFT 0x00000008 -#define IA_DBG_REG_15__Reserved14__SHIFT 0x00000009 -#define IA_DBG_REG_15__Reserved13__SHIFT 0x0000000a -#define IA_DBG_REG_15__Reserved12__SHIFT 0x0000000b -#define IA_DBG_REG_15__Reserved11__SHIFT 0x0000000c -#define IA_DBG_REG_15__Reserved10__SHIFT 0x0000000d -#define IA_DBG_REG_15__Reserved9__SHIFT 0x0000000e -#define IA_DBG_REG_15__Reserved8__SHIFT 0x0000000f -#define IA_DBG_REG_15__Reserved7__SHIFT 0x00000010 -#define IA_DBG_REG_15__Reserved6__SHIFT 0x00000011 -#define IA_DBG_REG_15__Reserved5__SHIFT 0x00000012 -#define IA_DBG_REG_15__Reserved4__SHIFT 0x00000013 -#define IA_DBG_REG_15__Reserved3__SHIFT 0x00000014 -#define IA_DBG_REG_15__Reserved2__SHIFT 0x00000015 -#define IA_DBG_REG_15__Reserved1__SHIFT 0x00000016 -#define IA_DBG_REG_15__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_0 -#define VGT_DBG_REG_0__vgt_busy_extended__SHIFT 0x00000000 -#define VGT_DBG_REG_0__Reserved8__SHIFT 0x00000001 -#define VGT_DBG_REG_0__vgt_busy__SHIFT 0x00000002 -#define VGT_DBG_REG_0__Reserved7__SHIFT 0x00000003 -#define VGT_DBG_REG_0__Reserved6__SHIFT 0x00000004 -#define VGT_DBG_REG_0__Reserved5__SHIFT 0x00000005 -#define VGT_DBG_REG_0__Reserved4__SHIFT 0x00000006 -#define VGT_DBG_REG_0__Reserved3__SHIFT 0x00000007 -#define VGT_DBG_REG_0__pi_busy__SHIFT 0x00000008 -#define VGT_DBG_REG_0__vr_pi_busy__SHIFT 0x00000009 -#define VGT_DBG_REG_0__pt_pi_busy__SHIFT 0x0000000a -#define VGT_DBG_REG_0__te_pi_busy__SHIFT 0x0000000b -#define VGT_DBG_REG_0__gs_busy__SHIFT 0x0000000c -#define VGT_DBG_REG_0__rcm_busy__SHIFT 0x0000000d -#define VGT_DBG_REG_0__tm_busy__SHIFT 0x0000000e -#define VGT_DBG_REG_0__cm_busy__SHIFT 0x0000000f -#define VGT_DBG_REG_0__gog_busy__SHIFT 0x00000010 -#define VGT_DBG_REG_0__frmt_busy__SHIFT 0x00000011 -#define VGT_DBG_REG_0__Reserved2__SHIFT 0x00000012 -#define VGT_DBG_REG_0__te11_pi_busy__SHIFT 0x00000013 -#define VGT_DBG_REG_0__Reserved1__SHIFT 0x00000014 -#define VGT_DBG_REG_0__combined_out_busy__SHIFT 0x00000015 -#define VGT_DBG_REG_0__spi_vs_interfaces_busy__SHIFT 0x00000016 -#define VGT_DBG_REG_0__pa_interfaces_busy__SHIFT 0x00000017 -#define VGT_DBG_REG_0__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_1 -#define VGT_DBG_REG_1__reg_clk_busy__SHIFT 0x00000000 -#define VGT_DBG_REG_1__Reserved13__SHIFT 0x00000001 -#define VGT_DBG_REG_1__core_clk_busy__SHIFT 0x00000002 -#define VGT_DBG_REG_1__gs_clk_busy__SHIFT 0x00000003 -#define VGT_DBG_REG_1__Reserved12__SHIFT 0x00000004 -#define VGT_DBG_REG_1__sclk_core_vld__SHIFT 0x00000005 -#define VGT_DBG_REG_1__sclk_gs_vld__SHIFT 0x00000006 -#define VGT_DBG_REG_1__Reserved11__SHIFT 0x00000007 -#define VGT_DBG_REG_1__Reserved10__SHIFT 0x00000008 -#define VGT_DBG_REG_1__Reserved9__SHIFT 0x00000009 -#define VGT_DBG_REG_1__Reserved8__SHIFT 0x0000000a -#define VGT_DBG_REG_1__Reserved7__SHIFT 0x0000000b -#define VGT_DBG_REG_1__Reserved6__SHIFT 0x0000000c -#define VGT_DBG_REG_1__Reserved5__SHIFT 0x0000000d -#define VGT_DBG_REG_1__Reserved4__SHIFT 0x0000000e -#define VGT_DBG_REG_1__Reserved3__SHIFT 0x0000000f -#define VGT_DBG_REG_1__Reserved2__SHIFT 0x00000010 -#define VGT_DBG_REG_1__Reserved1__SHIFT 0x00000011 -#define VGT_DBG_REG_1__pi_vr_valid__SHIFT 0x00000012 -#define VGT_DBG_REG_1__vr_pi_read__SHIFT 0x00000013 -#define VGT_DBG_REG_1__pi_pt_valid__SHIFT 0x00000014 -#define VGT_DBG_REG_1__pt_pi_read__SHIFT 0x00000015 -#define VGT_DBG_REG_1__pi_te_valid__SHIFT 0x00000016 -#define VGT_DBG_REG_1__te_grp_read__SHIFT 0x00000017 -#define VGT_DBG_REG_1__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_2 -#define VGT_DBG_REG_2__vr_out_indx_valid__SHIFT 0x00000000 -#define VGT_DBG_REG_2__Reserved5__SHIFT 0x00000001 -#define VGT_DBG_REG_2__vr_out_prim_valid__SHIFT 0x00000002 -#define VGT_DBG_REG_2__Reserved4__SHIFT 0x00000003 -#define VGT_DBG_REG_2__pt_out_indx_valid__SHIFT 0x00000004 -#define VGT_DBG_REG_2__Reserved3__SHIFT 0x00000005 -#define VGT_DBG_REG_2__pt_out_prim_valid__SHIFT 0x00000006 -#define VGT_DBG_REG_2__Reserved2__SHIFT 0x00000007 -#define VGT_DBG_REG_2__te_out_data_valid__SHIFT 0x00000008 -#define VGT_DBG_REG_2__Reserved1__SHIFT 0x00000009 -#define VGT_DBG_REG_2__pi_gs_valid__SHIFT 0x0000000a -#define VGT_DBG_REG_2__gs_pi_read__SHIFT 0x0000000b -#define VGT_DBG_REG_2__gog_out_indx_valid__SHIFT 0x0000000c -#define VGT_DBG_REG_2__out_indx_read__SHIFT 0x0000000d -#define VGT_DBG_REG_2__gog_out_prim_valid__SHIFT 0x0000000e -#define VGT_DBG_REG_2__out_prim_read__SHIFT 0x0000000f -#define VGT_DBG_REG_2__hs_grp_busy__SHIFT 0x00000010 -#define VGT_DBG_REG_2__hs_noif_busy__SHIFT 0x00000011 -#define VGT_DBG_REG_2__tfmmIsBusy__SHIFT 0x00000012 -#define VGT_DBG_REG_2__lsVertIfBusy_0__SHIFT 0x00000013 -#define VGT_DBG_REG_2__te11_hs_tess_input_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_2__lsWaveIfBusy_0__SHIFT 0x00000015 -#define VGT_DBG_REG_2__hs_te11_tess_input_rts__SHIFT 0x00000016 -#define VGT_DBG_REG_2__grpModBusy__SHIFT 0x00000017 -#define VGT_DBG_REG_2__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_3 -#define VGT_DBG_REG_3__lsVertFifoEmpty__SHIFT 0x00000000 -#define VGT_DBG_REG_3__lsWaveFifoEmpty__SHIFT 0x00000001 -#define VGT_DBG_REG_3__hsVertFifoEmpty__SHIFT 0x00000002 -#define VGT_DBG_REG_3__hsWaveFifoEmpty__SHIFT 0x00000003 -#define VGT_DBG_REG_3__hsInputFifoEmpty__SHIFT 0x00000004 -#define VGT_DBG_REG_3__hsTifFifoEmpty__SHIFT 0x00000005 -#define VGT_DBG_REG_3__lsVertFifoFull__SHIFT 0x00000006 -#define VGT_DBG_REG_3__lsWaveFifoFull__SHIFT 0x00000007 -#define VGT_DBG_REG_3__hsVertFifoFull__SHIFT 0x00000008 -#define VGT_DBG_REG_3__hsWaveFifoFull__SHIFT 0x00000009 -#define VGT_DBG_REG_3__hsInputFifoFull__SHIFT 0x0000000a -#define VGT_DBG_REG_3__hsTifFifoFull__SHIFT 0x0000000b -#define VGT_DBG_REG_3__p0_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_3__p1_rtr__SHIFT 0x0000000d -#define VGT_DBG_REG_3__p0_dr__SHIFT 0x0000000e -#define VGT_DBG_REG_3__p1_dr__SHIFT 0x0000000f -#define VGT_DBG_REG_3__p0_rts__SHIFT 0x00000010 -#define VGT_DBG_REG_3__p1_rts__SHIFT 0x00000011 -#define VGT_DBG_REG_3__ls_sh_id__SHIFT 0x00000012 -#define VGT_DBG_REG_3__lsFwaveFlag__SHIFT 0x00000013 -#define VGT_DBG_REG_3__lsWaveSendFlush__SHIFT 0x00000014 -#define VGT_DBG_REG_3__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_3__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_3__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_4 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_0__SHIFT 0x00000000 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_1__SHIFT 0x00000001 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_2__SHIFT 0x00000002 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_3__SHIFT 0x00000003 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_4__SHIFT 0x00000004 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_5__SHIFT 0x00000005 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_6__SHIFT 0x00000006 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_7__SHIFT 0x00000007 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_8__SHIFT 0x00000008 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_9__SHIFT 0x00000009 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_10__SHIFT 0x0000000a -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_11__SHIFT 0x0000000b -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_12__SHIFT 0x0000000c -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_13__SHIFT 0x0000000d -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_14__SHIFT 0x0000000e -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_15__SHIFT 0x0000000f -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_16__SHIFT 0x00000010 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_17__SHIFT 0x00000011 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_18__SHIFT 0x00000012 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_19__SHIFT 0x00000013 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_20__SHIFT 0x00000014 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_21__SHIFT 0x00000015 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_22__SHIFT 0x00000016 -#define VGT_DBG_REG_4__avail_es_rb_space_r0_q_23_0_23__SHIFT 0x00000017 -#define VGT_DBG_REG_4__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_5 -#define VGT_DBG_REG_5__dependent_st_cut_mode_q_0__SHIFT 0x00000000 -#define VGT_DBG_REG_5__dependent_st_cut_mode_q_1__SHIFT 0x00000001 -#define VGT_DBG_REG_5__Reserved6__SHIFT 0x00000002 -#define VGT_DBG_REG_5__Reserved5__SHIFT 0x00000003 -#define VGT_DBG_REG_5__Reserved4__SHIFT 0x00000004 -#define VGT_DBG_REG_5__Reserved3__SHIFT 0x00000005 -#define VGT_DBG_REG_5__Reserved2__SHIFT 0x00000006 -#define VGT_DBG_REG_5__Reserved1__SHIFT 0x00000007 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_0__SHIFT 0x00000008 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_1__SHIFT 0x00000009 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_2__SHIFT 0x0000000a -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_3__SHIFT 0x0000000b -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_4__SHIFT 0x0000000c -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_5__SHIFT 0x0000000d -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_6__SHIFT 0x0000000e -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_7__SHIFT 0x0000000f -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_8__SHIFT 0x00000010 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_9__SHIFT 0x00000011 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_10__SHIFT 0x00000012 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_11__SHIFT 0x00000013 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_12__SHIFT 0x00000014 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_13__SHIFT 0x00000015 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_14__SHIFT 0x00000016 -#define VGT_DBG_REG_5__avail_gs_rb_space_r0_q_25_0_15__SHIFT 0x00000017 -#define VGT_DBG_REG_5__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_6 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_16__SHIFT 0x00000000 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_17__SHIFT 0x00000001 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_18__SHIFT 0x00000002 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_19__SHIFT 0x00000003 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_20__SHIFT 0x00000004 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_21__SHIFT 0x00000005 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_22__SHIFT 0x00000006 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_23__SHIFT 0x00000007 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_24__SHIFT 0x00000008 -#define VGT_DBG_REG_6__avail_gs_rb_space_r0_q_25_0_25__SHIFT 0x00000009 -#define VGT_DBG_REG_6__active_sm_r0_q_0__SHIFT 0x0000000a -#define VGT_DBG_REG_6__active_sm_r0_q_1__SHIFT 0x0000000b -#define VGT_DBG_REG_6__active_sm_r0_q_2__SHIFT 0x0000000c -#define VGT_DBG_REG_6__active_sm_r0_q_3__SHIFT 0x0000000d -#define VGT_DBG_REG_6__add_gs_rb_space_r1_q__SHIFT 0x0000000e -#define VGT_DBG_REG_6__add_gs_rb_space_r0_q__SHIFT 0x0000000f -#define VGT_DBG_REG_6__cm_state0_0__SHIFT 0x00000010 -#define VGT_DBG_REG_6__cm_state0_1__SHIFT 0x00000011 -#define VGT_DBG_REG_6__cm_state1_0__SHIFT 0x00000012 -#define VGT_DBG_REG_6__cm_state1_1__SHIFT 0x00000013 -#define VGT_DBG_REG_6__cm_state2_0__SHIFT 0x00000014 -#define VGT_DBG_REG_6__cm_state2_1__SHIFT 0x00000015 -#define VGT_DBG_REG_6__cm_state3_0__SHIFT 0x00000016 -#define VGT_DBG_REG_6__cm_state3_1__SHIFT 0x00000017 -#define VGT_DBG_REG_6__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_7 -#define VGT_DBG_REG_7__cm_state4_0__SHIFT 0x00000000 -#define VGT_DBG_REG_7__cm_state4_1__SHIFT 0x00000001 -#define VGT_DBG_REG_7__cm_state5_0__SHIFT 0x00000002 -#define VGT_DBG_REG_7__cm_state5_1__SHIFT 0x00000003 -#define VGT_DBG_REG_7__cm_state6_0__SHIFT 0x00000004 -#define VGT_DBG_REG_7__cm_state6_1__SHIFT 0x00000005 -#define VGT_DBG_REG_7__cm_state7_0__SHIFT 0x00000006 -#define VGT_DBG_REG_7__cm_state7_1__SHIFT 0x00000007 -#define VGT_DBG_REG_7__cm_state8_0__SHIFT 0x00000008 -#define VGT_DBG_REG_7__cm_state8_1__SHIFT 0x00000009 -#define VGT_DBG_REG_7__cm_state9_0__SHIFT 0x0000000a -#define VGT_DBG_REG_7__cm_state9_1__SHIFT 0x0000000b -#define VGT_DBG_REG_7__cm_state10_0__SHIFT 0x0000000c -#define VGT_DBG_REG_7__cm_state10_1__SHIFT 0x0000000d -#define VGT_DBG_REG_7__cm_state11_0__SHIFT 0x0000000e -#define VGT_DBG_REG_7__cm_state11_1__SHIFT 0x0000000f -#define VGT_DBG_REG_7__cm_state12_0__SHIFT 0x00000010 -#define VGT_DBG_REG_7__cm_state12_1__SHIFT 0x00000011 -#define VGT_DBG_REG_7__cm_state13_0__SHIFT 0x00000012 -#define VGT_DBG_REG_7__cm_state13_1__SHIFT 0x00000013 -#define VGT_DBG_REG_7__cm_state14_0__SHIFT 0x00000014 -#define VGT_DBG_REG_7__cm_state14_1__SHIFT 0x00000015 -#define VGT_DBG_REG_7__cm_state15_0__SHIFT 0x00000016 -#define VGT_DBG_REG_7__cm_state15_1__SHIFT 0x00000017 -#define VGT_DBG_REG_7__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_8 -#define VGT_DBG_REG_8__pipe0_dr__SHIFT 0x00000000 -#define VGT_DBG_REG_8__gsc0_dr__SHIFT 0x00000001 -#define VGT_DBG_REG_8__pipe1_dr__SHIFT 0x00000002 -#define VGT_DBG_REG_8__tm_pt_event_rtr__SHIFT 0x00000003 -#define VGT_DBG_REG_8__pipe0_rtr__SHIFT 0x00000004 -#define VGT_DBG_REG_8__gsc0_rtr__SHIFT 0x00000005 -#define VGT_DBG_REG_8__pipe1_rtr__SHIFT 0x00000006 -#define VGT_DBG_REG_8__last_indx_of_prim_p1_q__SHIFT 0x00000007 -#define VGT_DBG_REG_8__indices_to_send_p0_q_0__SHIFT 0x00000008 -#define VGT_DBG_REG_8__indices_to_send_p0_q_1__SHIFT 0x00000009 -#define VGT_DBG_REG_8__event_flag_p1_q__SHIFT 0x0000000a -#define VGT_DBG_REG_8__eop_p1_q__SHIFT 0x0000000b -#define VGT_DBG_REG_8__gs_out_prim_type_p0_q_0__SHIFT 0x0000000c -#define VGT_DBG_REG_8__gs_out_prim_type_p0_q_1__SHIFT 0x0000000d -#define VGT_DBG_REG_8__gsc_null_primitive_p0_q__SHIFT 0x0000000e -#define VGT_DBG_REG_8__gsc_eop_p0_q__SHIFT 0x0000000f -#define VGT_DBG_REG_8__gsc_2cycle_output__SHIFT 0x00000010 -#define VGT_DBG_REG_8__gsc_2nd_cycle_p0_q__SHIFT 0x00000011 -#define VGT_DBG_REG_8__last_indx_of_vsprim__SHIFT 0x00000012 -#define VGT_DBG_REG_8__first_vsprim_of_gsprim_p0_q__SHIFT 0x00000013 -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_0__SHIFT 0x00000014 -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_1__SHIFT 0x00000015 -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_2__SHIFT 0x00000016 -#define VGT_DBG_REG_8__gsc_indx_count_p0_q_3__SHIFT 0x00000017 -#define VGT_DBG_REG_8__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_9 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_4__SHIFT 0x00000000 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_5__SHIFT 0x00000001 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_6__SHIFT 0x00000002 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_7__SHIFT 0x00000003 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_8__SHIFT 0x00000004 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_9__SHIFT 0x00000005 -#define VGT_DBG_REG_9__gsc_indx_count_p0_q_10__SHIFT 0x00000006 -#define VGT_DBG_REG_9__last_vsprim_of_gsprim__SHIFT 0x00000007 -#define VGT_DBG_REG_9__con_state_q_0__SHIFT 0x00000008 -#define VGT_DBG_REG_9__con_state_q_1__SHIFT 0x00000009 -#define VGT_DBG_REG_9__con_state_q_2__SHIFT 0x0000000a -#define VGT_DBG_REG_9__con_state_q_3__SHIFT 0x0000000b -#define VGT_DBG_REG_9__second_cycle_q__SHIFT 0x0000000c -#define VGT_DBG_REG_9__process_tri_middle_p0_q__SHIFT 0x0000000d -#define VGT_DBG_REG_9__process_tri_1st_2nd_half_p0_q__SHIFT 0x0000000e -#define VGT_DBG_REG_9__process_tri_center_poly_p0_q__SHIFT 0x0000000f -#define VGT_DBG_REG_9__pipe0_patch_dr__SHIFT 0x00000010 -#define VGT_DBG_REG_9__pipe0_edge_dr__SHIFT 0x00000011 -#define VGT_DBG_REG_9__pipe1_dr__SHIFT 0x00000012 -#define VGT_DBG_REG_9__pipe0_patch_rtr__SHIFT 0x00000013 -#define VGT_DBG_REG_9__pipe0_edge_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_9__pipe1_rtr__SHIFT 0x00000015 -#define VGT_DBG_REG_9__outer_parity_p0_q__SHIFT 0x00000016 -#define VGT_DBG_REG_9__parallel_parity_p0_q__SHIFT 0x00000017 -#define VGT_DBG_REG_9__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_10 -#define VGT_DBG_REG_10__first_ring_of_patch_p0_q__SHIFT 0x00000000 -#define VGT_DBG_REG_10__last_ring_of_patch_p0_q__SHIFT 0x00000001 -#define VGT_DBG_REG_10__last_edge_of_outer_ring_p0_q__SHIFT 0x00000002 -#define VGT_DBG_REG_10__last_point_of_outer_ring_p1__SHIFT 0x00000003 -#define VGT_DBG_REG_10__last_point_of_inner_ring_p1__SHIFT 0x00000004 -#define VGT_DBG_REG_10__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000005 -#define VGT_DBG_REG_10__advance_outer_point_p1__SHIFT 0x00000006 -#define VGT_DBG_REG_10__advance_inner_point_p1__SHIFT 0x00000007 -#define VGT_DBG_REG_10__next_ring_is_rect_p0_q__SHIFT 0x00000008 -#define VGT_DBG_REG_10__pipe1_outer1_rtr__SHIFT 0x00000009 -#define VGT_DBG_REG_10__pipe1_outer2_rtr__SHIFT 0x0000000a -#define VGT_DBG_REG_10__pipe1_inner1_rtr__SHIFT 0x0000000b -#define VGT_DBG_REG_10__pipe1_inner2_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_10__pipe1_patch_rtr__SHIFT 0x0000000d -#define VGT_DBG_REG_10__pipe1_edge_rtr__SHIFT 0x0000000e -#define VGT_DBG_REG_10__use_stored_inner_q_ring2__SHIFT 0x0000000f -#define VGT_DBG_REG_10__con_state_q_0__SHIFT 0x00000010 -#define VGT_DBG_REG_10__con_state_q_1__SHIFT 0x00000011 -#define VGT_DBG_REG_10__con_state_q_2__SHIFT 0x00000012 -#define VGT_DBG_REG_10__con_state_q_3__SHIFT 0x00000013 -#define VGT_DBG_REG_10__second_cycle_q__SHIFT 0x00000014 -#define VGT_DBG_REG_10__process_tri_middle_p0_q__SHIFT 0x00000015 -#define VGT_DBG_REG_10__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000016 -#define VGT_DBG_REG_10__process_tri_center_poly_p0_q__SHIFT 0x00000017 -#define VGT_DBG_REG_10__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_11 -#define VGT_DBG_REG_11__pipe0_patch_dr__SHIFT 0x00000000 -#define VGT_DBG_REG_11__pipe0_edge_dr__SHIFT 0x00000001 -#define VGT_DBG_REG_11__pipe1_dr__SHIFT 0x00000002 -#define VGT_DBG_REG_11__pipe0_patch_rtr__SHIFT 0x00000003 -#define VGT_DBG_REG_11__pipe0_edge_rtr__SHIFT 0x00000004 -#define VGT_DBG_REG_11__pipe1_rtr__SHIFT 0x00000005 -#define VGT_DBG_REG_11__outer_parity_p0_q__SHIFT 0x00000006 -#define VGT_DBG_REG_11__parallel_parity_p0_q__SHIFT 0x00000007 -#define VGT_DBG_REG_11__first_ring_of_patch_p0_q__SHIFT 0x00000008 -#define VGT_DBG_REG_11__last_ring_of_patch_p0_q__SHIFT 0x00000009 -#define VGT_DBG_REG_11__last_edge_of_outer_ring_p0_q__SHIFT 0x0000000a -#define VGT_DBG_REG_11__last_point_of_outer_ring_p1__SHIFT 0x0000000b -#define VGT_DBG_REG_11__last_point_of_inner_ring_p1__SHIFT 0x0000000c -#define VGT_DBG_REG_11__outer_edge_tf_eq_one_p0_q__SHIFT 0x0000000d -#define VGT_DBG_REG_11__advance_outer_point_p1__SHIFT 0x0000000e -#define VGT_DBG_REG_11__advance_inner_point_p1__SHIFT 0x0000000f -#define VGT_DBG_REG_11__next_ring_is_rect_p0_q__SHIFT 0x00000010 -#define VGT_DBG_REG_11__pipe1_outer1_rtr__SHIFT 0x00000011 -#define VGT_DBG_REG_11__pipe1_outer2_rtr__SHIFT 0x00000012 -#define VGT_DBG_REG_11__pipe1_inner1_rtr__SHIFT 0x00000013 -#define VGT_DBG_REG_11__pipe1_inner2_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_11__pipe1_patch_rtr__SHIFT 0x00000015 -#define VGT_DBG_REG_11__pipe1_edge_rtr__SHIFT 0x00000016 -#define VGT_DBG_REG_11__use_stored_inner_q_ring3__SHIFT 0x00000017 -#define VGT_DBG_REG_11__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_12 -#define VGT_DBG_REG_12__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_12__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_12__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_12__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_12__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_12__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_12__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_12__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_12__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_12__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_12__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_12__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_12__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_12__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_12__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_12__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_12__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_12__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_12__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_12__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_12__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_12__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_12__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_12__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_13 -#define VGT_DBG_REG_13__Reserved8__SHIFT 0x00000000 -#define VGT_DBG_REG_13__Reserved7__SHIFT 0x00000001 -#define VGT_DBG_REG_13__Reserved6__SHIFT 0x00000002 -#define VGT_DBG_REG_13__Reserved5__SHIFT 0x00000003 -#define VGT_DBG_REG_13__Reserved4__SHIFT 0x00000004 -#define VGT_DBG_REG_13__Reserved3__SHIFT 0x00000005 -#define VGT_DBG_REG_13__Reserved2__SHIFT 0x00000006 -#define VGT_DBG_REG_13__Reserved1__SHIFT 0x00000007 -#define VGT_DBG_REG_13__pipe0_dr__SHIFT 0x00000008 -#define VGT_DBG_REG_13__pipe0_rtr__SHIFT 0x00000009 -#define VGT_DBG_REG_13__pipe1_outer_dr__SHIFT 0x0000000a -#define VGT_DBG_REG_13__pipe1_inner_dr__SHIFT 0x0000000b -#define VGT_DBG_REG_13__pipe2_outer_dr__SHIFT 0x0000000c -#define VGT_DBG_REG_13__pipe2_inner_dr__SHIFT 0x0000000d -#define VGT_DBG_REG_13__pipe3_outer_dr__SHIFT 0x0000000e -#define VGT_DBG_REG_13__pipe3_inner_dr__SHIFT 0x0000000f -#define VGT_DBG_REG_13__pipe4_outer_dr__SHIFT 0x00000010 -#define VGT_DBG_REG_13__pipe4_inner_dr__SHIFT 0x00000011 -#define VGT_DBG_REG_13__pipe5_outer_dr__SHIFT 0x00000012 -#define VGT_DBG_REG_13__pipe5_inner_dr__SHIFT 0x00000013 -#define VGT_DBG_REG_13__pipe2_outer_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_13__pipe2_inner_rtr__SHIFT 0x00000015 -#define VGT_DBG_REG_13__pipe3_outer_rtr__SHIFT 0x00000016 -#define VGT_DBG_REG_13__pipe3_inner_rtr__SHIFT 0x00000017 -#define VGT_DBG_REG_13__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_14 -#define VGT_DBG_REG_14__pipe4_outer_rtr__SHIFT 0x00000000 -#define VGT_DBG_REG_14__pipe4_inner_rtr__SHIFT 0x00000001 -#define VGT_DBG_REG_14__pipe5_outer_rtr__SHIFT 0x00000002 -#define VGT_DBG_REG_14__pipe5_inner_rtr__SHIFT 0x00000003 -#define VGT_DBG_REG_14__pg_con_outer_point1_rts__SHIFT 0x00000004 -#define VGT_DBG_REG_14__pg_con_outer_point2_rts__SHIFT 0x00000005 -#define VGT_DBG_REG_14__pg_con_inner_point1_rts__SHIFT 0x00000006 -#define VGT_DBG_REG_14__pg_con_inner_point2_rts__SHIFT 0x00000007 -#define VGT_DBG_REG_14__pg_patch_fifo_empty__SHIFT 0x00000008 -#define VGT_DBG_REG_14__pg_edge_fifo_empty__SHIFT 0x00000009 -#define VGT_DBG_REG_14__pg_inner3_perp_fifo_empty__SHIFT 0x0000000a -#define VGT_DBG_REG_14__pg_patch_fifo_full__SHIFT 0x0000000b -#define VGT_DBG_REG_14__pg_edge_fifo_full__SHIFT 0x0000000c -#define VGT_DBG_REG_14__pg_inner_perp_fifo_full__SHIFT 0x0000000d -#define VGT_DBG_REG_14__outer_ring_done_q__SHIFT 0x0000000e -#define VGT_DBG_REG_14__inner_ring_done_q__SHIFT 0x0000000f -#define VGT_DBG_REG_14__first_ring_of_patch__SHIFT 0x00000010 -#define VGT_DBG_REG_14__last_ring_of_patch__SHIFT 0x00000011 -#define VGT_DBG_REG_14__last_edge_of_outer_ring__SHIFT 0x00000012 -#define VGT_DBG_REG_14__last_point_of_outer_edge__SHIFT 0x00000013 -#define VGT_DBG_REG_14__last_edge_of_inner_ring__SHIFT 0x00000014 -#define VGT_DBG_REG_14__last_point_of_inner_edge__SHIFT 0x00000015 -#define VGT_DBG_REG_14__last_patch_of_tg_p0_q__SHIFT 0x00000016 -#define VGT_DBG_REG_14__event_null_special_p0_q__SHIFT 0x00000017 -#define VGT_DBG_REG_14__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_15 -#define VGT_DBG_REG_15__event_flag_p5_q__SHIFT 0x00000000 -#define VGT_DBG_REG_15__first_point_of_patch_p5_q__SHIFT 0x00000001 -#define VGT_DBG_REG_15__first_point_of_edge_p5_q__SHIFT 0x00000002 -#define VGT_DBG_REG_15__last_patch_of_tg_p5_q__SHIFT 0x00000003 -#define VGT_DBG_REG_15__tess_topology_p5_q_0__SHIFT 0x00000004 -#define VGT_DBG_REG_15__tess_topology_p5_q_1__SHIFT 0x00000005 -#define VGT_DBG_REG_15__pipe5_inner3_rtr__SHIFT 0x00000006 -#define VGT_DBG_REG_15__pipe5_inner2_rtr__SHIFT 0x00000007 -#define VGT_DBG_REG_15__pg_edge_fifo3_full__SHIFT 0x00000008 -#define VGT_DBG_REG_15__pg_edge_fifo2_full__SHIFT 0x00000009 -#define VGT_DBG_REG_15__pg_inner3_point_fifo_full__SHIFT 0x0000000a -#define VGT_DBG_REG_15__pg_outer3_point_fifo_full__SHIFT 0x0000000b -#define VGT_DBG_REG_15__pg_inner2_point_fifo_full__SHIFT 0x0000000c -#define VGT_DBG_REG_15__pg_outer2_point_fifo_full__SHIFT 0x0000000d -#define VGT_DBG_REG_15__pg_inner_point_fifo_full__SHIFT 0x0000000e -#define VGT_DBG_REG_15__pg_outer_point_fifo_full__SHIFT 0x0000000f -#define VGT_DBG_REG_15__inner2_fifos_rtr__SHIFT 0x00000010 -#define VGT_DBG_REG_15__inner_fifos_rtr__SHIFT 0x00000011 -#define VGT_DBG_REG_15__outer_fifos_rtr__SHIFT 0x00000012 -#define VGT_DBG_REG_15__fifos_rtr__SHIFT 0x00000013 -#define VGT_DBG_REG_15__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_15__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_15__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_15__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_16 -#define VGT_DBG_REG_16__pipe0_patch_dr__SHIFT 0x00000000 -#define VGT_DBG_REG_16__ring3_pipe1_dr__SHIFT 0x00000001 -#define VGT_DBG_REG_16__pipe1_dr__SHIFT 0x00000002 -#define VGT_DBG_REG_16__pipe2_dr__SHIFT 0x00000003 -#define VGT_DBG_REG_16__pipe0_patch_rtr__SHIFT 0x00000004 -#define VGT_DBG_REG_16__ring2_pipe1_dr__SHIFT 0x00000005 -#define VGT_DBG_REG_16__ring1_pipe1_dr__SHIFT 0x00000006 -#define VGT_DBG_REG_16__pipe2_rtr__SHIFT 0x00000007 -#define VGT_DBG_REG_16__pipe3_dr__SHIFT 0x00000008 -#define VGT_DBG_REG_16__pipe3_rtr__SHIFT 0x00000009 -#define VGT_DBG_REG_16__ring2_in_sync_q__SHIFT 0x0000000a -#define VGT_DBG_REG_16__ring1_in_sync_q__SHIFT 0x0000000b -#define VGT_DBG_REG_16__pipe1_patch_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_16__ring3_in_sync_q__SHIFT 0x0000000d -#define VGT_DBG_REG_16__tm_te11_event_rtr__SHIFT 0x0000000e -#define VGT_DBG_REG_16__first_prim_of_patch_q__SHIFT 0x0000000f -#define VGT_DBG_REG_16__con_prim_fifo_full__SHIFT 0x00000010 -#define VGT_DBG_REG_16__con_vert_fifo_full__SHIFT 0x00000011 -#define VGT_DBG_REG_16__con_prim_fifo_empty__SHIFT 0x00000012 -#define VGT_DBG_REG_16__con_vert_fifo_empty__SHIFT 0x00000013 -#define VGT_DBG_REG_16__last_patch_of_tg_p0_q__SHIFT 0x00000014 -#define VGT_DBG_REG_16__ring3_valid_p2__SHIFT 0x00000015 -#define VGT_DBG_REG_16__ring2_valid_p2__SHIFT 0x00000016 -#define VGT_DBG_REG_16__ring1_valid_p2__SHIFT 0x00000017 -#define VGT_DBG_REG_16__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_17 -#define VGT_DBG_REG_17__tess_type_p0_q_0__SHIFT 0x00000000 -#define VGT_DBG_REG_17__tess_type_p0_q_1__SHIFT 0x00000001 -#define VGT_DBG_REG_17__tess_topology_p0_q_0__SHIFT 0x00000002 -#define VGT_DBG_REG_17__tess_topology_p0_q_1__SHIFT 0x00000003 -#define VGT_DBG_REG_17__te11_out_vert_gs_en__SHIFT 0x00000004 -#define VGT_DBG_REG_17__con_ring3_busy__SHIFT 0x00000005 -#define VGT_DBG_REG_17__con_ring2_busy__SHIFT 0x00000006 -#define VGT_DBG_REG_17__con_ring1_busy__SHIFT 0x00000007 -#define VGT_DBG_REG_17__con_state_q_0__SHIFT 0x00000008 -#define VGT_DBG_REG_17__con_state_q_1__SHIFT 0x00000009 -#define VGT_DBG_REG_17__con_state_q_2__SHIFT 0x0000000a -#define VGT_DBG_REG_17__con_state_q_3__SHIFT 0x0000000b -#define VGT_DBG_REG_17__second_cycle_q__SHIFT 0x0000000c -#define VGT_DBG_REG_17__process_tri_middle_p0_q__SHIFT 0x0000000d -#define VGT_DBG_REG_17__process_tri_1st_2nd_half_p0_q__SHIFT 0x0000000e -#define VGT_DBG_REG_17__process_tri_center_poly_p0_q__SHIFT 0x0000000f -#define VGT_DBG_REG_17__pipe0_patch_dr__SHIFT 0x00000010 -#define VGT_DBG_REG_17__pipe0_edge_dr__SHIFT 0x00000011 -#define VGT_DBG_REG_17__pipe1_dr__SHIFT 0x00000012 -#define VGT_DBG_REG_17__pipe0_patch_rtr__SHIFT 0x00000013 -#define VGT_DBG_REG_17__pipe0_edge_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_17__pipe1_rtr__SHIFT 0x00000015 -#define VGT_DBG_REG_17__outer_parity_p0_q__SHIFT 0x00000016 -#define VGT_DBG_REG_17__parallel_parity_p0_q__SHIFT 0x00000017 -#define VGT_DBG_REG_17__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_18 -#define VGT_DBG_REG_18__first_ring_of_patch_p0_q__SHIFT 0x00000000 -#define VGT_DBG_REG_18__last_ring_of_patch_p0_q__SHIFT 0x00000001 -#define VGT_DBG_REG_18__last_edge_of_outer_ring_p0_q__SHIFT 0x00000002 -#define VGT_DBG_REG_18__last_point_of_outer_ring_p1__SHIFT 0x00000003 -#define VGT_DBG_REG_18__last_point_of_inner_ring_p1__SHIFT 0x00000004 -#define VGT_DBG_REG_18__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000005 -#define VGT_DBG_REG_18__advance_outer_point_p1__SHIFT 0x00000006 -#define VGT_DBG_REG_18__advance_inner_point_p1__SHIFT 0x00000007 -#define VGT_DBG_REG_18__next_ring_is_rect_p0_q__SHIFT 0x00000008 -#define VGT_DBG_REG_18__pipe1_outer1_rtr__SHIFT 0x00000009 -#define VGT_DBG_REG_18__pipe1_outer2_rtr__SHIFT 0x0000000a -#define VGT_DBG_REG_18__pipe1_inner1_rtr__SHIFT 0x0000000b -#define VGT_DBG_REG_18__pipe1_inner2_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_18__pipe1_patch_rtr__SHIFT 0x0000000d -#define VGT_DBG_REG_18__pipe1_edge_rtr__SHIFT 0x0000000e -#define VGT_DBG_REG_18__use_stored_inner_q_ring1__SHIFT 0x0000000f -#define VGT_DBG_REG_18__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_18__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_18__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_18__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_18__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_18__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_18__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_18__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_19 -#define VGT_DBG_REG_19__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_19__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_19__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_19__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_19__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_19__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_19__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_19__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_19__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_19__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_19__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_19__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_19__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_19__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_19__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_19__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_19__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_19__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_19__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_19__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_19__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_19__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_19__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_19__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_20 -#define VGT_DBG_REG_20__Reserved16__SHIFT 0x00000000 -#define VGT_DBG_REG_20__Reserved15__SHIFT 0x00000001 -#define VGT_DBG_REG_20__Reserved14__SHIFT 0x00000002 -#define VGT_DBG_REG_20__Reserved13__SHIFT 0x00000003 -#define VGT_DBG_REG_20__Reserved12__SHIFT 0x00000004 -#define VGT_DBG_REG_20__Reserved11__SHIFT 0x00000005 -#define VGT_DBG_REG_20__Reserved10__SHIFT 0x00000006 -#define VGT_DBG_REG_20__Reserved9__SHIFT 0x00000007 -#define VGT_DBG_REG_20__Reserved8__SHIFT 0x00000008 -#define VGT_DBG_REG_20__Reserved7__SHIFT 0x00000009 -#define VGT_DBG_REG_20__Reserved6__SHIFT 0x0000000a -#define VGT_DBG_REG_20__Reserved5__SHIFT 0x0000000b -#define VGT_DBG_REG_20__Reserved4__SHIFT 0x0000000c -#define VGT_DBG_REG_20__Reserved3__SHIFT 0x0000000d -#define VGT_DBG_REG_20__Reserved2__SHIFT 0x0000000e -#define VGT_DBG_REG_20__Reserved1__SHIFT 0x0000000f -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_0__SHIFT 0x00000010 -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_1__SHIFT 0x00000011 -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_2__SHIFT 0x00000012 -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_3__SHIFT 0x00000013 -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_4__SHIFT 0x00000014 -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_5__SHIFT 0x00000015 -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_6__SHIFT 0x00000016 -#define VGT_DBG_REG_20__VGT_PA_clipp_eop_7__SHIFT 0x00000017 -#define VGT_DBG_REG_20__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_21 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_8__SHIFT 0x00000000 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_9__SHIFT 0x00000001 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_10__SHIFT 0x00000002 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_11__SHIFT 0x00000003 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_12__SHIFT 0x00000004 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_13__SHIFT 0x00000005 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_14__SHIFT 0x00000006 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_15__SHIFT 0x00000007 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_16__SHIFT 0x00000008 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_17__SHIFT 0x00000009 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_18__SHIFT 0x0000000a -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_19__SHIFT 0x0000000b -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_20__SHIFT 0x0000000c -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_21__SHIFT 0x0000000d -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_22__SHIFT 0x0000000e -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_23__SHIFT 0x0000000f -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_24__SHIFT 0x00000010 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_25__SHIFT 0x00000011 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_26__SHIFT 0x00000012 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_27__SHIFT 0x00000013 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_28__SHIFT 0x00000014 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_29__SHIFT 0x00000015 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_30__SHIFT 0x00000016 -#define VGT_DBG_REG_21__VGT_PA_clipp_eop_31__SHIFT 0x00000017 -#define VGT_DBG_REG_21__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_22 -#define VGT_DBG_REG_22__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_22__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_22__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_22__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_22__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_22__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_22__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_22__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_22__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_22__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_22__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_22__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_22__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_22__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_22__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_22__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_22__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_22__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_22__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_22__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_22__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_22__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_22__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_22__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_23 -#define VGT_DBG_REG_23__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_23__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_23__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_23__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_23__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_23__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_23__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_23__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_23__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_23__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_23__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_23__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_23__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_23__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_23__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_23__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_23__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_23__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_23__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_23__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_23__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_23__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_23__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_23__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_24 -#define VGT_DBG_REG_24__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_24__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_24__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_24__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_24__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_24__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_24__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_24__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_24__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_24__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_24__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_24__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_24__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_24__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_24__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_24__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_24__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_24__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_24__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_24__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_24__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_24__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_24__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_24__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_25 -#define VGT_DBG_REG_25__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_25__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_25__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_25__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_25__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_25__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_25__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_25__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_25__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_25__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_25__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_25__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_25__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_25__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_25__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_25__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_25__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_25__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_25__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_25__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_25__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_25__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_25__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_25__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_26 -#define VGT_DBG_REG_26__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_26__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_26__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_26__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_26__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_26__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_26__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_26__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_26__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_26__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_26__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_26__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_26__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_26__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_26__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_26__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_26__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_26__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_26__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_26__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_26__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_26__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_26__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_26__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_27 -#define VGT_DBG_REG_27__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_27__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_27__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_27__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_27__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_27__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_27__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_27__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_27__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_27__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_27__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_27__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_27__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_27__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_27__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_27__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_27__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_27__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_27__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_27__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_27__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_27__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_27__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_27__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_28 -#define VGT_DBG_REG_28__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_28__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_28__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_28__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_28__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_28__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_28__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_28__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_28__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_28__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_28__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_28__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_28__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_28__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_28__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_28__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_28__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_28__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_28__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_28__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_28__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_28__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_28__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_28__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_29 -#define VGT_DBG_REG_29__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_29__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_29__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_29__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_29__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_29__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_29__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_29__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_29__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_29__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_29__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_29__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_29__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_29__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_29__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_29__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_29__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_29__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_29__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_29__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_29__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_29__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_29__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_29__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_30 -#define VGT_DBG_REG_30__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_30__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_30__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_30__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_30__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_30__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_30__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_30__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_30__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_30__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_30__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_30__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_30__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_30__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_30__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_30__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_30__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_30__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_30__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_30__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_30__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_30__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_30__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_30__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_31 -#define VGT_DBG_REG_31__Reserved23__SHIFT 0x00000000 -#define VGT_DBG_REG_31__Reserved22__SHIFT 0x00000001 -#define VGT_DBG_REG_31__Reserved21__SHIFT 0x00000002 -#define VGT_DBG_REG_31__Reserved20__SHIFT 0x00000003 -#define VGT_DBG_REG_31__Reserved19__SHIFT 0x00000004 -#define VGT_DBG_REG_31__Reserved18__SHIFT 0x00000005 -#define VGT_DBG_REG_31__Reserved17__SHIFT 0x00000006 -#define VGT_DBG_REG_31__Reserved16__SHIFT 0x00000007 -#define VGT_DBG_REG_31__Reserved15__SHIFT 0x00000008 -#define VGT_DBG_REG_31__Reserved14__SHIFT 0x00000009 -#define VGT_DBG_REG_31__Reserved13__SHIFT 0x0000000a -#define VGT_DBG_REG_31__Reserved12__SHIFT 0x0000000b -#define VGT_DBG_REG_31__Reserved11__SHIFT 0x0000000c -#define VGT_DBG_REG_31__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_31__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_31__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_31__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_31__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_31__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_31__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_31__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_31__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_31__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_31__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_32 -#define VGT_DBG_REG_32__vgt_busy_extended__SHIFT 0x00000000 -#define VGT_DBG_REG_32__Reserved8__SHIFT 0x00000001 -#define VGT_DBG_REG_32__vgt_busy__SHIFT 0x00000002 -#define VGT_DBG_REG_32__Reserved7__SHIFT 0x00000003 -#define VGT_DBG_REG_32__Reserved6__SHIFT 0x00000004 -#define VGT_DBG_REG_32__Reserved5__SHIFT 0x00000005 -#define VGT_DBG_REG_32__Reserved4__SHIFT 0x00000006 -#define VGT_DBG_REG_32__Reserved3__SHIFT 0x00000007 -#define VGT_DBG_REG_32__pi_busy__SHIFT 0x00000008 -#define VGT_DBG_REG_32__vr_pi_busy__SHIFT 0x00000009 -#define VGT_DBG_REG_32__pt_pi_busy__SHIFT 0x0000000a -#define VGT_DBG_REG_32__te_pi_busy__SHIFT 0x0000000b -#define VGT_DBG_REG_32__gs_busy__SHIFT 0x0000000c -#define VGT_DBG_REG_32__rcm_busy__SHIFT 0x0000000d -#define VGT_DBG_REG_32__tm_busy__SHIFT 0x0000000e -#define VGT_DBG_REG_32__cm_busy__SHIFT 0x0000000f -#define VGT_DBG_REG_32__gog_busy__SHIFT 0x00000010 -#define VGT_DBG_REG_32__frmt_busy__SHIFT 0x00000011 -#define VGT_DBG_REG_32__Reserved2__SHIFT 0x00000012 -#define VGT_DBG_REG_32__te11_pi_busy__SHIFT 0x00000013 -#define VGT_DBG_REG_32__Reserved1__SHIFT 0x00000014 -#define VGT_DBG_REG_32__combined_out_busy__SHIFT 0x00000015 -#define VGT_DBG_REG_32__spi_vs_interfaces_busy__SHIFT 0x00000016 -#define VGT_DBG_REG_32__pa_interfaces_busy__SHIFT 0x00000017 -#define VGT_DBG_REG_32__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_33 -#define VGT_DBG_REG_33__reg_clk_busy__SHIFT 0x00000000 -#define VGT_DBG_REG_33__Reserved13__SHIFT 0x00000001 -#define VGT_DBG_REG_33__core_clk_busy__SHIFT 0x00000002 -#define VGT_DBG_REG_33__gs_clk_busy__SHIFT 0x00000003 -#define VGT_DBG_REG_33__Reserved12__SHIFT 0x00000004 -#define VGT_DBG_REG_33__sclk_core_vld__SHIFT 0x00000005 -#define VGT_DBG_REG_33__sclk_gs_vld__SHIFT 0x00000006 -#define VGT_DBG_REG_33__Reserved11__SHIFT 0x00000007 -#define VGT_DBG_REG_33__Reserved10__SHIFT 0x00000008 -#define VGT_DBG_REG_33__Reserved9__SHIFT 0x00000009 -#define VGT_DBG_REG_33__Reserved8__SHIFT 0x0000000a -#define VGT_DBG_REG_33__Reserved7__SHIFT 0x0000000b -#define VGT_DBG_REG_33__Reserved6__SHIFT 0x0000000c -#define VGT_DBG_REG_33__Reserved5__SHIFT 0x0000000d -#define VGT_DBG_REG_33__Reserved4__SHIFT 0x0000000e -#define VGT_DBG_REG_33__Reserved3__SHIFT 0x0000000f -#define VGT_DBG_REG_33__Reserved2__SHIFT 0x00000010 -#define VGT_DBG_REG_33__Reserved1__SHIFT 0x00000011 -#define VGT_DBG_REG_33__pi_vr_valid__SHIFT 0x00000012 -#define VGT_DBG_REG_33__vr_pi_read__SHIFT 0x00000013 -#define VGT_DBG_REG_33__pi_pt_valid__SHIFT 0x00000014 -#define VGT_DBG_REG_33__pt_pi_read__SHIFT 0x00000015 -#define VGT_DBG_REG_33__pi_te_valid__SHIFT 0x00000016 -#define VGT_DBG_REG_33__te_grp_read__SHIFT 0x00000017 -#define VGT_DBG_REG_33__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_34 -#define VGT_DBG_REG_34__vr_out_indx_valid__SHIFT 0x00000000 -#define VGT_DBG_REG_34__Reserved5__SHIFT 0x00000001 -#define VGT_DBG_REG_34__vr_out_prim_valid__SHIFT 0x00000002 -#define VGT_DBG_REG_34__Reserved4__SHIFT 0x00000003 -#define VGT_DBG_REG_34__pt_out_indx_valid__SHIFT 0x00000004 -#define VGT_DBG_REG_34__Reserved3__SHIFT 0x00000005 -#define VGT_DBG_REG_34__pt_out_prim_valid__SHIFT 0x00000006 -#define VGT_DBG_REG_34__Reserved2__SHIFT 0x00000007 -#define VGT_DBG_REG_34__te_out_data_valid__SHIFT 0x00000008 -#define VGT_DBG_REG_34__Reserved1__SHIFT 0x00000009 -#define VGT_DBG_REG_34__pi_gs_valid__SHIFT 0x0000000a -#define VGT_DBG_REG_34__gs_pi_read__SHIFT 0x0000000b -#define VGT_DBG_REG_34__gog_out_indx_valid__SHIFT 0x0000000c -#define VGT_DBG_REG_34__out_indx_read__SHIFT 0x0000000d -#define VGT_DBG_REG_34__gog_out_prim_valid__SHIFT 0x0000000e -#define VGT_DBG_REG_34__out_prim_read__SHIFT 0x0000000f -#define VGT_DBG_REG_34__hs_grp_busy__SHIFT 0x00000010 -#define VGT_DBG_REG_34__hs_noif_busy__SHIFT 0x00000011 -#define VGT_DBG_REG_34__tfmmIsBusy__SHIFT 0x00000012 -#define VGT_DBG_REG_34__lsVertIfBusy_0__SHIFT 0x00000013 -#define VGT_DBG_REG_34__te11_hs_tess_input_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_34__lsWaveIfBusy_0__SHIFT 0x00000015 -#define VGT_DBG_REG_34__hs_te11_tess_input_rts__SHIFT 0x00000016 -#define VGT_DBG_REG_34__grpModBusy__SHIFT 0x00000017 -#define VGT_DBG_REG_34__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_35 -#define VGT_DBG_REG_35__lsVertFifoEmpty__SHIFT 0x00000000 -#define VGT_DBG_REG_35__lsWaveFifoEmpty__SHIFT 0x00000001 -#define VGT_DBG_REG_35__hsVertFifoEmpty__SHIFT 0x00000002 -#define VGT_DBG_REG_35__hsWaveFifoEmpty__SHIFT 0x00000003 -#define VGT_DBG_REG_35__hsInputFifoEmpty__SHIFT 0x00000004 -#define VGT_DBG_REG_35__hsTifFifoEmpty__SHIFT 0x00000005 -#define VGT_DBG_REG_35__lsVertFifoFull__SHIFT 0x00000006 -#define VGT_DBG_REG_35__lsWaveFifoFull__SHIFT 0x00000007 -#define VGT_DBG_REG_35__hsVertFifoFull__SHIFT 0x00000008 -#define VGT_DBG_REG_35__hsWaveFifoFull__SHIFT 0x00000009 -#define VGT_DBG_REG_35__hsInputFifoFull__SHIFT 0x0000000a -#define VGT_DBG_REG_35__hsTifFifoFull__SHIFT 0x0000000b -#define VGT_DBG_REG_35__p0_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_35__p1_rtr__SHIFT 0x0000000d -#define VGT_DBG_REG_35__p0_dr__SHIFT 0x0000000e -#define VGT_DBG_REG_35__p1_dr__SHIFT 0x0000000f -#define VGT_DBG_REG_35__p0_rts__SHIFT 0x00000010 -#define VGT_DBG_REG_35__p1_rts__SHIFT 0x00000011 -#define VGT_DBG_REG_35__ls_sh_id__SHIFT 0x00000012 -#define VGT_DBG_REG_35__lsFwaveFlag__SHIFT 0x00000013 -#define VGT_DBG_REG_35__lsWaveSendFlush__SHIFT 0x00000014 -#define VGT_DBG_REG_35__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_35__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_35__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_36 -#define VGT_DBG_REG_36__lsTgRelInd_0__SHIFT 0x00000000 -#define VGT_DBG_REG_36__lsTgRelInd_1__SHIFT 0x00000001 -#define VGT_DBG_REG_36__lsTgRelInd_2__SHIFT 0x00000002 -#define VGT_DBG_REG_36__lsTgRelInd_3__SHIFT 0x00000003 -#define VGT_DBG_REG_36__lsTgRelInd_4__SHIFT 0x00000004 -#define VGT_DBG_REG_36__lsTgRelInd_5__SHIFT 0x00000005 -#define VGT_DBG_REG_36__lsTgRelInd_6__SHIFT 0x00000006 -#define VGT_DBG_REG_36__lsTgRelInd_7__SHIFT 0x00000007 -#define VGT_DBG_REG_36__lsTgRelInd_8__SHIFT 0x00000008 -#define VGT_DBG_REG_36__lsTgRelInd_9__SHIFT 0x00000009 -#define VGT_DBG_REG_36__lsTgRelInd_10__SHIFT 0x0000000a -#define VGT_DBG_REG_36__lsTgRelInd_11__SHIFT 0x0000000b -#define VGT_DBG_REG_36__lsWaveRelInd_0__SHIFT 0x0000000c -#define VGT_DBG_REG_36__lsWaveRelInd_1__SHIFT 0x0000000d -#define VGT_DBG_REG_36__lsWaveRelInd_2__SHIFT 0x0000000e -#define VGT_DBG_REG_36__lsWaveRelInd_3__SHIFT 0x0000000f -#define VGT_DBG_REG_36__lsWaveRelInd_4__SHIFT 0x00000010 -#define VGT_DBG_REG_36__lsWaveRelInd_5__SHIFT 0x00000011 -#define VGT_DBG_REG_36__lsPatchCnt_0__SHIFT 0x00000012 -#define VGT_DBG_REG_36__lsPatchCnt_1__SHIFT 0x00000013 -#define VGT_DBG_REG_36__lsPatchCnt_2__SHIFT 0x00000014 -#define VGT_DBG_REG_36__lsPatchCnt_3__SHIFT 0x00000015 -#define VGT_DBG_REG_36__lsPatchCnt_4__SHIFT 0x00000016 -#define VGT_DBG_REG_36__lsPatchCnt_5__SHIFT 0x00000017 -#define VGT_DBG_REG_36__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_37 -#define VGT_DBG_REG_37__lsPatchCnt_6__SHIFT 0x00000000 -#define VGT_DBG_REG_37__lsPatchCnt_7__SHIFT 0x00000001 -#define VGT_DBG_REG_37__hsWaveRelInd_0__SHIFT 0x00000002 -#define VGT_DBG_REG_37__hsWaveRelInd_1__SHIFT 0x00000003 -#define VGT_DBG_REG_37__hsWaveRelInd_2__SHIFT 0x00000004 -#define VGT_DBG_REG_37__hsWaveRelInd_3__SHIFT 0x00000005 -#define VGT_DBG_REG_37__hsWaveRelInd_4__SHIFT 0x00000006 -#define VGT_DBG_REG_37__hsWaveRelInd_5__SHIFT 0x00000007 -#define VGT_DBG_REG_37__hsPatchCnt_0__SHIFT 0x00000008 -#define VGT_DBG_REG_37__hsPatchCnt_1__SHIFT 0x00000009 -#define VGT_DBG_REG_37__hsPatchCnt_2__SHIFT 0x0000000a -#define VGT_DBG_REG_37__hsPatchCnt_3__SHIFT 0x0000000b -#define VGT_DBG_REG_37__hsPatchCnt_4__SHIFT 0x0000000c -#define VGT_DBG_REG_37__hsPatchCnt_5__SHIFT 0x0000000d -#define VGT_DBG_REG_37__hsPatchCnt_6__SHIFT 0x0000000e -#define VGT_DBG_REG_37__hsPatchCnt_7__SHIFT 0x0000000f -#define VGT_DBG_REG_37__hsPrimId_15_0_0__SHIFT 0x00000010 -#define VGT_DBG_REG_37__hsPrimId_15_0_1__SHIFT 0x00000011 -#define VGT_DBG_REG_37__hsPrimId_15_0_2__SHIFT 0x00000012 -#define VGT_DBG_REG_37__hsPrimId_15_0_3__SHIFT 0x00000013 -#define VGT_DBG_REG_37__hsPrimId_15_0_4__SHIFT 0x00000014 -#define VGT_DBG_REG_37__hsPrimId_15_0_5__SHIFT 0x00000015 -#define VGT_DBG_REG_37__hsPrimId_15_0_6__SHIFT 0x00000016 -#define VGT_DBG_REG_37__hsPrimId_15_0_7__SHIFT 0x00000017 -#define VGT_DBG_REG_37__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_38 -#define VGT_DBG_REG_38__hsPrimId_15_0_8__SHIFT 0x00000000 -#define VGT_DBG_REG_38__hsPrimId_15_0_9__SHIFT 0x00000001 -#define VGT_DBG_REG_38__hsPrimId_15_0_10__SHIFT 0x00000002 -#define VGT_DBG_REG_38__hsPrimId_15_0_11__SHIFT 0x00000003 -#define VGT_DBG_REG_38__hsPrimId_15_0_12__SHIFT 0x00000004 -#define VGT_DBG_REG_38__hsPrimId_15_0_13__SHIFT 0x00000005 -#define VGT_DBG_REG_38__hsPrimId_15_0_14__SHIFT 0x00000006 -#define VGT_DBG_REG_38__hsPrimId_15_0_15__SHIFT 0x00000007 -#define VGT_DBG_REG_38__hsCpCnt_0__SHIFT 0x00000008 -#define VGT_DBG_REG_38__hsCpCnt_1__SHIFT 0x00000009 -#define VGT_DBG_REG_38__hsCpCnt_2__SHIFT 0x0000000a -#define VGT_DBG_REG_38__hsCpCnt_3__SHIFT 0x0000000b -#define VGT_DBG_REG_38__hsCpCnt_4__SHIFT 0x0000000c -#define VGT_DBG_REG_38__hsWaveSendFlush__SHIFT 0x0000000d -#define VGT_DBG_REG_38__hsFwaveFlag__SHIFT 0x0000000e -#define VGT_DBG_REG_38__Reserved4__SHIFT 0x0000000f -#define VGT_DBG_REG_38__Reserved3__SHIFT 0x00000010 -#define VGT_DBG_REG_38__Reserved2__SHIFT 0x00000011 -#define VGT_DBG_REG_38__Reserved1__SHIFT 0x00000012 -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_0__SHIFT 0x00000013 -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_1__SHIFT 0x00000014 -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_2__SHIFT 0x00000015 -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_3__SHIFT 0x00000016 -#define VGT_DBG_REG_38__hsWaveCreditCnt_0_4__SHIFT 0x00000017 -#define VGT_DBG_REG_38__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_39 -#define VGT_DBG_REG_39__Reserved9__SHIFT 0x00000000 -#define VGT_DBG_REG_39__Reserved8__SHIFT 0x00000001 -#define VGT_DBG_REG_39__Reserved7__SHIFT 0x00000002 -#define VGT_DBG_REG_39__hsVertCreditCnt_0_0__SHIFT 0x00000003 -#define VGT_DBG_REG_39__hsVertCreditCnt_0_2__SHIFT 0x00000004 -#define VGT_DBG_REG_39__hsVertCreditCnt_0_3__SHIFT 0x00000005 -#define VGT_DBG_REG_39__hsVertCreditCnt_0_4__SHIFT 0x00000006 -#define VGT_DBG_REG_39__hsVertCreditCnt_0_5__SHIFT 0x00000007 -#define VGT_DBG_REG_39__Reserved6__SHIFT 0x00000008 -#define VGT_DBG_REG_39__Reserved5__SHIFT 0x00000009 -#define VGT_DBG_REG_39__Reserved4__SHIFT 0x0000000a -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_0__SHIFT 0x0000000b -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_1__SHIFT 0x0000000c -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_2__SHIFT 0x0000000d -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_3__SHIFT 0x0000000e -#define VGT_DBG_REG_39__lsWaveCreditCnt_0_4__SHIFT 0x0000000f -#define VGT_DBG_REG_39__Reserved3__SHIFT 0x00000010 -#define VGT_DBG_REG_39__Reserved2__SHIFT 0x00000011 -#define VGT_DBG_REG_39__Reserved1__SHIFT 0x00000012 -#define VGT_DBG_REG_39__lsVertCreditCnt_0_0__SHIFT 0x00000013 -#define VGT_DBG_REG_39__lsVertCreditCnt_0_1__SHIFT 0x00000014 -#define VGT_DBG_REG_39__lsVertCreditCnt_0_2__SHIFT 0x00000015 -#define VGT_DBG_REG_39__lsVertCreditCnt_0_3__SHIFT 0x00000016 -#define VGT_DBG_REG_39__lsVertCreditCnt_0_4__SHIFT 0x00000017 -#define VGT_DBG_REG_39__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_40 -#define VGT_DBG_REG_40__debug_BASE_0__SHIFT 0x00000000 -#define VGT_DBG_REG_40__debug_BASE_1__SHIFT 0x00000001 -#define VGT_DBG_REG_40__debug_BASE_2__SHIFT 0x00000002 -#define VGT_DBG_REG_40__debug_BASE_3__SHIFT 0x00000003 -#define VGT_DBG_REG_40__debug_BASE_4__SHIFT 0x00000004 -#define VGT_DBG_REG_40__debug_BASE_5__SHIFT 0x00000005 -#define VGT_DBG_REG_40__debug_BASE_6__SHIFT 0x00000006 -#define VGT_DBG_REG_40__debug_BASE_7__SHIFT 0x00000007 -#define VGT_DBG_REG_40__debug_BASE_8__SHIFT 0x00000008 -#define VGT_DBG_REG_40__debug_BASE_9__SHIFT 0x00000009 -#define VGT_DBG_REG_40__debug_BASE_10__SHIFT 0x0000000a -#define VGT_DBG_REG_40__debug_BASE_11__SHIFT 0x0000000b -#define VGT_DBG_REG_40__debug_BASE_12__SHIFT 0x0000000c -#define VGT_DBG_REG_40__debug_BASE_13__SHIFT 0x0000000d -#define VGT_DBG_REG_40__debug_BASE_14__SHIFT 0x0000000e -#define VGT_DBG_REG_40__debug_BASE_15__SHIFT 0x0000000f -#define VGT_DBG_REG_40__debug_SIZE_0__SHIFT 0x00000010 -#define VGT_DBG_REG_40__debug_SIZE_1__SHIFT 0x00000011 -#define VGT_DBG_REG_40__debug_SIZE_2__SHIFT 0x00000012 -#define VGT_DBG_REG_40__debug_SIZE_3__SHIFT 0x00000013 -#define VGT_DBG_REG_40__debug_SIZE_4__SHIFT 0x00000014 -#define VGT_DBG_REG_40__debug_SIZE_5__SHIFT 0x00000015 -#define VGT_DBG_REG_40__debug_SIZE_6__SHIFT 0x00000016 -#define VGT_DBG_REG_40__debug_SIZE_7__SHIFT 0x00000017 -#define VGT_DBG_REG_40__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_41 -#define VGT_DBG_REG_41__debug_SIZE_8__SHIFT 0x00000000 -#define VGT_DBG_REG_41__debug_SIZE_9__SHIFT 0x00000001 -#define VGT_DBG_REG_41__debug_SIZE_10__SHIFT 0x00000002 -#define VGT_DBG_REG_41__debug_SIZE_11__SHIFT 0x00000003 -#define VGT_DBG_REG_41__debug_SIZE_12__SHIFT 0x00000004 -#define VGT_DBG_REG_41__debug_SIZE_13__SHIFT 0x00000005 -#define VGT_DBG_REG_41__debug_SIZE_14__SHIFT 0x00000006 -#define VGT_DBG_REG_41__debug_SIZE_15__SHIFT 0x00000007 -#define VGT_DBG_REG_41__debug_tfmmFifoEmpty__SHIFT 0x00000008 -#define VGT_DBG_REG_41__debug_tfmmFifoFull__SHIFT 0x00000009 -#define VGT_DBG_REG_41__hs_pipe0_dr__SHIFT 0x0000000a -#define VGT_DBG_REG_41__hs_pipe0_rtr__SHIFT 0x0000000b -#define VGT_DBG_REG_41__hs_pipe1_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_41__Reserved10__SHIFT 0x0000000d -#define VGT_DBG_REG_41__Reserved9__SHIFT 0x0000000e -#define VGT_DBG_REG_41__Reserved8__SHIFT 0x0000000f -#define VGT_DBG_REG_41__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_41__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_41__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_41__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_41__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_41__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_41__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_41__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_42 -#define VGT_DBG_REG_42__TF_addr_0__SHIFT 0x00000000 -#define VGT_DBG_REG_42__TF_addr_1__SHIFT 0x00000001 -#define VGT_DBG_REG_42__TF_addr_2__SHIFT 0x00000002 -#define VGT_DBG_REG_42__TF_addr_3__SHIFT 0x00000003 -#define VGT_DBG_REG_42__TF_addr_4__SHIFT 0x00000004 -#define VGT_DBG_REG_42__TF_addr_5__SHIFT 0x00000005 -#define VGT_DBG_REG_42__TF_addr_6__SHIFT 0x00000006 -#define VGT_DBG_REG_42__TF_addr_7__SHIFT 0x00000007 -#define VGT_DBG_REG_42__TF_addr_8__SHIFT 0x00000008 -#define VGT_DBG_REG_42__TF_addr_9__SHIFT 0x00000009 -#define VGT_DBG_REG_42__TF_addr_10__SHIFT 0x0000000a -#define VGT_DBG_REG_42__TF_addr_11__SHIFT 0x0000000b -#define VGT_DBG_REG_42__TF_addr_12__SHIFT 0x0000000c -#define VGT_DBG_REG_42__TF_addr_13__SHIFT 0x0000000d -#define VGT_DBG_REG_42__TF_addr_14__SHIFT 0x0000000e -#define VGT_DBG_REG_42__TF_addr_15__SHIFT 0x0000000f -#define VGT_DBG_REG_42__rcm_busy_q__SHIFT 0x00000010 -#define VGT_DBG_REG_42__rcm_noif_busy_q__SHIFT 0x00000011 -#define VGT_DBG_REG_42__r1_inst_rtr__SHIFT 0x00000012 -#define VGT_DBG_REG_42__spi_gsprim_fifo_busy_q__SHIFT 0x00000013 -#define VGT_DBG_REG_42__spi_esvert_fifo_busy_q__SHIFT 0x00000014 -#define VGT_DBG_REG_42__gs_tbl_valid_r3_q__SHIFT 0x00000015 -#define VGT_DBG_REG_42__valid_r0_q__SHIFT 0x00000016 -#define VGT_DBG_REG_42__valid_r1_q__SHIFT 0x00000017 -#define VGT_DBG_REG_42__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_43 -#define VGT_DBG_REG_43__valid_r2__SHIFT 0x00000000 -#define VGT_DBG_REG_43__valid_r2_q__SHIFT 0x00000001 -#define VGT_DBG_REG_43__r0_rtr__SHIFT 0x00000002 -#define VGT_DBG_REG_43__r1_rtr__SHIFT 0x00000003 -#define VGT_DBG_REG_43__r2_indx_rtr__SHIFT 0x00000004 -#define VGT_DBG_REG_43__r2_rtr__SHIFT 0x00000005 -#define VGT_DBG_REG_43__es_gs_rtr__SHIFT 0x00000006 -#define VGT_DBG_REG_43__gs_event_fifo_rtr__SHIFT 0x00000007 -#define VGT_DBG_REG_43__tm_rcm_gs_event_rtr__SHIFT 0x00000008 -#define VGT_DBG_REG_43__gs_tbl_r3_rtr__SHIFT 0x00000009 -#define VGT_DBG_REG_43__prim_skid_fifo_empty__SHIFT 0x0000000a -#define VGT_DBG_REG_43__VGT_SPI_gsprim_rtr_q__SHIFT 0x0000000b -#define VGT_DBG_REG_43__tm_rcm_gs_tbl_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_43__tm_rcm_es_tbl_rtr__SHIFT 0x0000000d -#define VGT_DBG_REG_43__VGT_SPI_esvert_rtr_q__SHIFT 0x0000000e -#define VGT_DBG_REG_43__r2_no_bp_rtr__SHIFT 0x0000000f -#define VGT_DBG_REG_43__hold_for_es_flush__SHIFT 0x00000010 -#define VGT_DBG_REG_43__gs_event_fifo_empty__SHIFT 0x00000011 -#define VGT_DBG_REG_43__gsprim_buff_empty_q__SHIFT 0x00000012 -#define VGT_DBG_REG_43__gsprim_buff_full_q__SHIFT 0x00000013 -#define VGT_DBG_REG_43__te_prim_fifo_empty__SHIFT 0x00000014 -#define VGT_DBG_REG_43__te_prim_fifo_full__SHIFT 0x00000015 -#define VGT_DBG_REG_43__te_vert_fifo_empty__SHIFT 0x00000016 -#define VGT_DBG_REG_43__te_vert_fifo_full__SHIFT 0x00000017 -#define VGT_DBG_REG_43__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_44 -#define VGT_DBG_REG_44__indices_to_send_r2_q_0__SHIFT 0x00000000 -#define VGT_DBG_REG_44__indices_to_send_r2_q_1__SHIFT 0x00000001 -#define VGT_DBG_REG_44__valid_indices_r3__SHIFT 0x00000002 -#define VGT_DBG_REG_44__gs_eov_r3__SHIFT 0x00000003 -#define VGT_DBG_REG_44__eop_indx_r3__SHIFT 0x00000004 -#define VGT_DBG_REG_44__eop_prim_r3__SHIFT 0x00000005 -#define VGT_DBG_REG_44__es_eov_r3__SHIFT 0x00000006 -#define VGT_DBG_REG_44__es_tbl_state_r3_q_0__SHIFT 0x00000007 -#define VGT_DBG_REG_44__pending_es_send_r3_q__SHIFT 0x00000008 -#define VGT_DBG_REG_44__pending_es_flush_r3__SHIFT 0x00000009 -#define VGT_DBG_REG_44__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0x0000000a -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_0__SHIFT 0x0000000b -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_1__SHIFT 0x0000000c -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_2__SHIFT 0x0000000d -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_3__SHIFT 0x0000000e -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_4__SHIFT 0x0000000f -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_5__SHIFT 0x00000010 -#define VGT_DBG_REG_44__gs_tbl_prim_cnt_r3_q_6__SHIFT 0x00000011 -#define VGT_DBG_REG_44__gs_tbl_eop_r3_q__SHIFT 0x00000012 -#define VGT_DBG_REG_44__gs_tbl_state_r3_q_0__SHIFT 0x00000013 -#define VGT_DBG_REG_44__gs_tbl_state_r3_q_1__SHIFT 0x00000014 -#define VGT_DBG_REG_44__gs_tbl_state_r3_q_2__SHIFT 0x00000015 -#define VGT_DBG_REG_44__gs_pending_state_r3_q__SHIFT 0x00000016 -#define VGT_DBG_REG_44__invalidate_rb_roll_over_q__SHIFT 0x00000017 -#define VGT_DBG_REG_44__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_45 -#define VGT_DBG_REG_45__gs_instancing_state_q__SHIFT 0x00000000 -#define VGT_DBG_REG_45__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x00000001 -#define VGT_DBG_REG_45__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x00000002 -#define VGT_DBG_REG_45__pre_r0_rtr__SHIFT 0x00000003 -#define VGT_DBG_REG_45__valid_r3_q__SHIFT 0x00000004 -#define VGT_DBG_REG_45__valid_pre_r0_q__SHIFT 0x00000005 -#define VGT_DBG_REG_45__Reserved3__SHIFT 0x00000006 -#define VGT_DBG_REG_45__off_chip_hs_r2_q__SHIFT 0x00000007 -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_0__SHIFT 0x00000008 -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_1__SHIFT 0x00000009 -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_2__SHIFT 0x0000000a -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_3__SHIFT 0x0000000b -#define VGT_DBG_REG_45__index_buffer_depth_r1_q_4__SHIFT 0x0000000c -#define VGT_DBG_REG_45__eopg_r2_q__SHIFT 0x0000000d -#define VGT_DBG_REG_45__eotg_r2_q__SHIFT 0x0000000e -#define VGT_DBG_REG_45__onchip_gs_en_r0_q_0__SHIFT 0x0000000f -#define VGT_DBG_REG_45__onchip_gs_en_r0_q_1__SHIFT 0x00000010 -#define VGT_DBG_REG_45__Reserved2__SHIFT 0x00000011 -#define VGT_DBG_REG_45__Reserved1__SHIFT 0x00000012 -#define VGT_DBG_REG_45__rcm_mem_gsprim_re_qq__SHIFT 0x00000013 -#define VGT_DBG_REG_45__rcm_mem_gsprim_re_q__SHIFT 0x00000014 -#define VGT_DBG_REG_45__gs_rb_space_avail_r3_q_9_0_0__SHIFT 0x00000015 -#define VGT_DBG_REG_45__gs_rb_space_avail_r3_q_9_0_1__SHIFT 0x00000016 -#define VGT_DBG_REG_45__gs_rb_space_avail_r3_q_9_0_2__SHIFT 0x00000017 -#define VGT_DBG_REG_45__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_46 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_3__SHIFT 0x00000000 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_4__SHIFT 0x00000001 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_5__SHIFT 0x00000002 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_6__SHIFT 0x00000003 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_7__SHIFT 0x00000004 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_8__SHIFT 0x00000005 -#define VGT_DBG_REG_46__gs_rb_space_avail_r3_q_9_0_9__SHIFT 0x00000006 -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_0__SHIFT 0x00000007 -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_1__SHIFT 0x00000008 -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_2__SHIFT 0x00000009 -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_3__SHIFT 0x0000000a -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_4__SHIFT 0x0000000b -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_5__SHIFT 0x0000000c -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_6__SHIFT 0x0000000d -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_7__SHIFT 0x0000000e -#define VGT_DBG_REG_46__es_rb_space_avail_r2_q_8_0_8__SHIFT 0x0000000f -#define VGT_DBG_REG_46__tm_busy_q__SHIFT 0x00000010 -#define VGT_DBG_REG_46__tm_noif_busy_q__SHIFT 0x00000011 -#define VGT_DBG_REG_46__tm_out_busy_q__SHIFT 0x00000012 -#define VGT_DBG_REG_46__es_rb_dealloc_fifo_busy__SHIFT 0x00000013 -#define VGT_DBG_REG_46__vs_dealloc_tbl_busy__SHIFT 0x00000014 -#define VGT_DBG_REG_46__Reserved1__SHIFT 0x00000015 -#define VGT_DBG_REG_46__spi_gsthread_fifo_busy__SHIFT 0x00000016 -#define VGT_DBG_REG_46__spi_esthread_fifo_busy__SHIFT 0x00000017 -#define VGT_DBG_REG_46__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_47 -#define VGT_DBG_REG_47__hold_eswave__SHIFT 0x00000000 -#define VGT_DBG_REG_47__es_rb_roll_over_r3__SHIFT 0x00000001 -#define VGT_DBG_REG_47__counters_busy_r0__SHIFT 0x00000002 -#define VGT_DBG_REG_47__counters_avail_r0__SHIFT 0x00000003 -#define VGT_DBG_REG_47__counters_available_r0__SHIFT 0x00000004 -#define VGT_DBG_REG_47__vs_event_fifo_rtr__SHIFT 0x00000005 -#define VGT_DBG_REG_47__VGT_SPI_gsthread_rtr_q__SHIFT 0x00000006 -#define VGT_DBG_REG_47__VGT_SPI_esthread_rtr_q__SHIFT 0x00000007 -#define VGT_DBG_REG_47__gs_issue_rtr__SHIFT 0x00000008 -#define VGT_DBG_REG_47__tm_pt_event_rtr__SHIFT 0x00000009 -#define VGT_DBG_REG_47__Reserved1__SHIFT 0x0000000a -#define VGT_DBG_REG_47__gs_r0_rtr__SHIFT 0x0000000b -#define VGT_DBG_REG_47__es_r0_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_47__gog_tm_vs_event_rtr__SHIFT 0x0000000d -#define VGT_DBG_REG_47__tm_rcm_gs_event_rtr__SHIFT 0x0000000e -#define VGT_DBG_REG_47__tm_rcm_gs_tbl_rtr__SHIFT 0x0000000f -#define VGT_DBG_REG_47__tm_rcm_es_tbl_rtr__SHIFT 0x00000010 -#define VGT_DBG_REG_47__vs_event_fifo_empty__SHIFT 0x00000011 -#define VGT_DBG_REG_47__vs_event_fifo_full__SHIFT 0x00000012 -#define VGT_DBG_REG_47__es_rb_dealloc_fifo_full__SHIFT 0x00000013 -#define VGT_DBG_REG_47__vs_dealloc_tbl_full__SHIFT 0x00000014 -#define VGT_DBG_REG_47__send_event_q__SHIFT 0x00000015 -#define VGT_DBG_REG_47__es_tbl_empty__SHIFT 0x00000016 -#define VGT_DBG_REG_47__no_active_states_r0__SHIFT 0x00000017 -#define VGT_DBG_REG_47__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_48 -#define VGT_DBG_REG_48__gs_state0_r0_q_0__SHIFT 0x00000000 -#define VGT_DBG_REG_48__gs_state0_r0_q_1__SHIFT 0x00000001 -#define VGT_DBG_REG_48__gs_state0_r0_q_2__SHIFT 0x00000002 -#define VGT_DBG_REG_48__gs_state1_r0_q_0__SHIFT 0x00000003 -#define VGT_DBG_REG_48__gs_state1_r0_q_1__SHIFT 0x00000004 -#define VGT_DBG_REG_48__gs_state1_r0_q_2__SHIFT 0x00000005 -#define VGT_DBG_REG_48__gs_state2_r0_q_0__SHIFT 0x00000006 -#define VGT_DBG_REG_48__gs_state2_r0_q_1__SHIFT 0x00000007 -#define VGT_DBG_REG_48__gs_state2_r0_q_2__SHIFT 0x00000008 -#define VGT_DBG_REG_48__gs_state3_r0_q_0__SHIFT 0x00000009 -#define VGT_DBG_REG_48__gs_state3_r0_q_1__SHIFT 0x0000000a -#define VGT_DBG_REG_48__gs_state3_r0_q_2__SHIFT 0x0000000b -#define VGT_DBG_REG_48__gs_state4_r0_q_0__SHIFT 0x0000000c -#define VGT_DBG_REG_48__gs_state4_r0_q_1__SHIFT 0x0000000d -#define VGT_DBG_REG_48__gs_state4_r0_q_2__SHIFT 0x0000000e -#define VGT_DBG_REG_48__gs_state5_r0_q_0__SHIFT 0x0000000f -#define VGT_DBG_REG_48__gs_state5_r0_q_1__SHIFT 0x00000010 -#define VGT_DBG_REG_48__gs_state5_r0_q_2__SHIFT 0x00000011 -#define VGT_DBG_REG_48__gs_state6_r0_q_0__SHIFT 0x00000012 -#define VGT_DBG_REG_48__gs_state6_r0_q_1__SHIFT 0x00000013 -#define VGT_DBG_REG_48__gs_state6_r0_q_2__SHIFT 0x00000014 -#define VGT_DBG_REG_48__gs_state7_r0_q_0__SHIFT 0x00000015 -#define VGT_DBG_REG_48__gs_state7_r0_q_1__SHIFT 0x00000016 -#define VGT_DBG_REG_48__gs_state7_r0_q_2__SHIFT 0x00000017 -#define VGT_DBG_REG_48__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_49 -#define VGT_DBG_REG_49__gs_state8_r0_q_0__SHIFT 0x00000000 -#define VGT_DBG_REG_49__gs_state8_r0_q_1__SHIFT 0x00000001 -#define VGT_DBG_REG_49__gs_state8_r0_q_2__SHIFT 0x00000002 -#define VGT_DBG_REG_49__gs_state9_r0_q_0__SHIFT 0x00000003 -#define VGT_DBG_REG_49__gs_state9_r0_q_1__SHIFT 0x00000004 -#define VGT_DBG_REG_49__gs_state9_r0_q_2__SHIFT 0x00000005 -#define VGT_DBG_REG_49__hold_eswave_eop__SHIFT 0x00000006 -#define VGT_DBG_REG_49__Reserved1__SHIFT 0x00000007 -#define VGT_DBG_REG_49__gs_state10_r0_q_0__SHIFT 0x00000008 -#define VGT_DBG_REG_49__gs_state10_r0_q_1__SHIFT 0x00000009 -#define VGT_DBG_REG_49__gs_state10_r0_q_2__SHIFT 0x0000000a -#define VGT_DBG_REG_49__gs_state11_r0_q_0__SHIFT 0x0000000b -#define VGT_DBG_REG_49__gs_state11_r0_q_1__SHIFT 0x0000000c -#define VGT_DBG_REG_49__gs_state11_r0_q_2__SHIFT 0x0000000d -#define VGT_DBG_REG_49__gs_state12_r0_q_0__SHIFT 0x0000000e -#define VGT_DBG_REG_49__gs_state12_r0_q_1__SHIFT 0x0000000f -#define VGT_DBG_REG_49__gs_state12_r0_q_2__SHIFT 0x00000010 -#define VGT_DBG_REG_49__gs_state13_r0_q_0__SHIFT 0x00000011 -#define VGT_DBG_REG_49__gs_state13_r0_q_1__SHIFT 0x00000012 -#define VGT_DBG_REG_49__gs_state13_r0_q_2__SHIFT 0x00000013 -#define VGT_DBG_REG_49__gs_state14_r0_q_0__SHIFT 0x00000014 -#define VGT_DBG_REG_49__gs_state14_r0_q_1__SHIFT 0x00000015 -#define VGT_DBG_REG_49__gs_state14_r0_q_2__SHIFT 0x00000016 -#define VGT_DBG_REG_49__gs_state15_r0_q_0__SHIFT 0x00000017 -#define VGT_DBG_REG_49__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_50 -#define VGT_DBG_REG_50__gs_state15_r0_q_1__SHIFT 0x00000000 -#define VGT_DBG_REG_50__gs_state15_r0_q_2__SHIFT 0x00000001 -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_0__SHIFT 0x00000002 -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_1__SHIFT 0x00000003 -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_2__SHIFT 0x00000004 -#define VGT_DBG_REG_50__gs_tbl_wrptr_r0_q_3_0_3__SHIFT 0x00000005 -#define VGT_DBG_REG_50__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x00000006 -#define VGT_DBG_REG_50__gsfetch_done_cnt_q_not_0__SHIFT 0x00000007 -#define VGT_DBG_REG_50__es_tbl_full__SHIFT 0x00000008 -#define VGT_DBG_REG_50__Reserved6__SHIFT 0x00000009 -#define VGT_DBG_REG_50__Reserved5__SHIFT 0x0000000a -#define VGT_DBG_REG_50__active_cm_sm_r0_q_0__SHIFT 0x0000000b -#define VGT_DBG_REG_50__active_cm_sm_r0_q_1__SHIFT 0x0000000c -#define VGT_DBG_REG_50__active_cm_sm_r0_q_2__SHIFT 0x0000000d -#define VGT_DBG_REG_50__active_cm_sm_r0_q_3__SHIFT 0x0000000e -#define VGT_DBG_REG_50__active_cm_sm_r0_q_4__SHIFT 0x0000000f -#define VGT_DBG_REG_50__Reserved4__SHIFT 0x00000010 -#define VGT_DBG_REG_50__Reserved3__SHIFT 0x00000011 -#define VGT_DBG_REG_50__Reserved2__SHIFT 0x00000012 -#define VGT_DBG_REG_50__Reserved1__SHIFT 0x00000013 -#define VGT_DBG_REG_50__gsfetch_done_fifo_full__SHIFT 0x00000014 -#define VGT_DBG_REG_50__gs_rb_space_avail_r0__SHIFT 0x00000015 -#define VGT_DBG_REG_50__smx_es_done_cnt_r0_q_not_0__SHIFT 0x00000016 -#define VGT_DBG_REG_50__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_51 -#define VGT_DBG_REG_51__Reserved15__SHIFT 0x00000000 -#define VGT_DBG_REG_51__vs_done_cnt_q_not_0__SHIFT 0x00000001 -#define VGT_DBG_REG_51__es_flush_cnt_busy_q__SHIFT 0x00000002 -#define VGT_DBG_REG_51__gs_tbl_full_r0__SHIFT 0x00000003 -#define VGT_DBG_REG_51__Reserved14__SHIFT 0x00000004 -#define VGT_DBG_REG_51__Reserved13__SHIFT 0x00000005 -#define VGT_DBG_REG_51__Reserved12__SHIFT 0x00000006 -#define VGT_DBG_REG_51__Reserved11__SHIFT 0x00000007 -#define VGT_DBG_REG_51__Reserved10__SHIFT 0x00000008 -#define VGT_DBG_REG_51__Reserved9__SHIFT 0x00000009 -#define VGT_DBG_REG_51__Reserved8__SHIFT 0x0000000a -#define VGT_DBG_REG_51__Reserved7__SHIFT 0x0000000b -#define VGT_DBG_REG_51__Reserved6__SHIFT 0x0000000c -#define VGT_DBG_REG_51__se1spi_gsthread_fifo_busy__SHIFT 0x0000000d -#define VGT_DBG_REG_51__Reserved5__SHIFT 0x0000000e -#define VGT_DBG_REG_51__Reserved4__SHIFT 0x0000000f -#define VGT_DBG_REG_51__Reserved3__SHIFT 0x00000010 -#define VGT_DBG_REG_51__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x00000011 -#define VGT_DBG_REG_51__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x00000012 -#define VGT_DBG_REG_51__se1spi_esthread_fifo_busy__SHIFT 0x00000013 -#define VGT_DBG_REG_51__Reserved2__SHIFT 0x00000014 -#define VGT_DBG_REG_51__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x00000015 -#define VGT_DBG_REG_51__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_51__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x00000017 -#define VGT_DBG_REG_51__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_52 -#define VGT_DBG_REG_52__cm_busy_q__SHIFT 0x00000000 -#define VGT_DBG_REG_52__counters_busy_q__SHIFT 0x00000001 -#define VGT_DBG_REG_52__output_fifo_empty__SHIFT 0x00000002 -#define VGT_DBG_REG_52__output_fifo_full__SHIFT 0x00000003 -#define VGT_DBG_REG_52__counters_full__SHIFT 0x00000004 -#define VGT_DBG_REG_52__active_sm_q_0__SHIFT 0x00000005 -#define VGT_DBG_REG_52__active_sm_q_1__SHIFT 0x00000006 -#define VGT_DBG_REG_52__active_sm_q_2__SHIFT 0x00000007 -#define VGT_DBG_REG_52__active_sm_q_3__SHIFT 0x00000008 -#define VGT_DBG_REG_52__active_sm_q_4__SHIFT 0x00000009 -#define VGT_DBG_REG_52__entry_rdptr_q_0__SHIFT 0x0000000a -#define VGT_DBG_REG_52__entry_rdptr_q_1__SHIFT 0x0000000b -#define VGT_DBG_REG_52__entry_rdptr_q_2__SHIFT 0x0000000c -#define VGT_DBG_REG_52__entry_rdptr_q_3__SHIFT 0x0000000d -#define VGT_DBG_REG_52__entry_rdptr_q_4__SHIFT 0x0000000e -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_0__SHIFT 0x0000000f -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_1__SHIFT 0x00000010 -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_2__SHIFT 0x00000011 -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_3__SHIFT 0x00000012 -#define VGT_DBG_REG_52__cntr_tbl_wrptr_q_4__SHIFT 0x00000013 -#define VGT_DBG_REG_52__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_52__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_52__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_52__Reserved0__SHIFT 0x0000001f - -// VGT_DBG_REG_53 -#define VGT_DBG_REG_53__Reserved5__SHIFT 0x00000000 -#define VGT_DBG_REG_53__Reserved4__SHIFT 0x00000001 -#define VGT_DBG_REG_53__st_cut_mode_q_0__SHIFT 0x00000002 -#define VGT_DBG_REG_53__st_cut_mode_q_1__SHIFT 0x00000003 -#define VGT_DBG_REG_53__gs_done_array_q_not_0__SHIFT 0x00000004 -#define VGT_DBG_REG_53__Reserved3__SHIFT 0x00000005 -#define VGT_DBG_REG_53__Reserved2__SHIFT 0x00000006 -#define VGT_DBG_REG_53__Reserved1__SHIFT 0x00000007 -#define VGT_DBG_REG_53__gog_busy__SHIFT 0x00000008 -#define VGT_DBG_REG_53__gog_state_q_1__SHIFT 0x00000009 -#define VGT_DBG_REG_53__gog_state_q_2__SHIFT 0x0000000a -#define VGT_DBG_REG_53__gog_state_q_3__SHIFT 0x0000000b -#define VGT_DBG_REG_53__r0_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_53__r1_rtr__SHIFT 0x0000000d -#define VGT_DBG_REG_53__r1_upstream_rtr__SHIFT 0x0000000e -#define VGT_DBG_REG_53__r2_vs_tbl_rtr__SHIFT 0x0000000f -#define VGT_DBG_REG_53__r2_prim_rtr__SHIFT 0x00000010 -#define VGT_DBG_REG_53__r2_indx_rtr__SHIFT 0x00000011 -#define VGT_DBG_REG_53__r2_rtr__SHIFT 0x00000012 -#define VGT_DBG_REG_53__gog_tm_vs_event_rtr__SHIFT 0x00000013 -#define VGT_DBG_REG_53__r3_force_vs_tbl_we_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_53__indx_valid_r2_q__SHIFT 0x00000015 -#define VGT_DBG_REG_53__prim_valid_r2_q__SHIFT 0x00000016 -#define VGT_DBG_REG_53__valid_r2_q__SHIFT 0x00000017 -#define VGT_DBG_REG_53__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_54 -#define VGT_DBG_REG_54__prim_valid_r1_q__SHIFT 0x00000000 -#define VGT_DBG_REG_54__indx_valid_r1_q__SHIFT 0x00000001 -#define VGT_DBG_REG_54__valid_r1_q__SHIFT 0x00000002 -#define VGT_DBG_REG_54__indx_valid_r0_q__SHIFT 0x00000003 -#define VGT_DBG_REG_54__prim_valid_r0_q__SHIFT 0x00000004 -#define VGT_DBG_REG_54__valid_r0_q__SHIFT 0x00000005 -#define VGT_DBG_REG_54__send_event_q__SHIFT 0x00000006 -#define VGT_DBG_REG_54__SPARE24__SHIFT 0x00000007 -#define VGT_DBG_REG_54__vert_seen_since_sopg_r2_q__SHIFT 0x00000008 -#define VGT_DBG_REG_54__gog_out_prim_state_sel_0__SHIFT 0x00000009 -#define VGT_DBG_REG_54__gog_out_prim_state_sel_1__SHIFT 0x0000000a -#define VGT_DBG_REG_54__gog_out_prim_state_sel_2__SHIFT 0x0000000b -#define VGT_DBG_REG_54__multiple_streams_en_r1_q__SHIFT 0x0000000c -#define VGT_DBG_REG_54__vs_vert_count_r2_q_not_0__SHIFT 0x0000000d -#define VGT_DBG_REG_54__num_gs_r2_q_not_0__SHIFT 0x0000000e -#define VGT_DBG_REG_54__new_vs_thread_r2__SHIFT 0x0000000f -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_0__SHIFT 0x00000010 -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_1__SHIFT 0x00000011 -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_2__SHIFT 0x00000012 -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_3__SHIFT 0x00000013 -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_4__SHIFT 0x00000014 -#define VGT_DBG_REG_54__gog_out_prim_rel_indx2_5_0_5__SHIFT 0x00000015 -#define VGT_DBG_REG_54__gog_out_prim_rel_indx1_5_0_0__SHIFT 0x00000016 -#define VGT_DBG_REG_54__gog_out_prim_rel_indx1_5_0_1__SHIFT 0x00000017 -#define VGT_DBG_REG_54__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_55 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_2__SHIFT 0x00000000 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_3__SHIFT 0x00000001 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_4__SHIFT 0x00000002 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx1_5_0_5__SHIFT 0x00000003 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_0__SHIFT 0x00000004 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_1__SHIFT 0x00000005 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_2__SHIFT 0x00000006 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_3__SHIFT 0x00000007 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_4__SHIFT 0x00000008 -#define VGT_DBG_REG_55__gog_out_prim_rel_indx0_5_0_5__SHIFT 0x00000009 -#define VGT_DBG_REG_55__gog_out_indx_13_0_0__SHIFT 0x0000000a -#define VGT_DBG_REG_55__gog_out_indx_13_0_1__SHIFT 0x0000000b -#define VGT_DBG_REG_55__gog_out_indx_13_0_2__SHIFT 0x0000000c -#define VGT_DBG_REG_55__gog_out_indx_13_0_3__SHIFT 0x0000000d -#define VGT_DBG_REG_55__gog_out_indx_13_0_4__SHIFT 0x0000000e -#define VGT_DBG_REG_55__gog_out_indx_13_0_5__SHIFT 0x0000000f -#define VGT_DBG_REG_55__gog_out_indx_13_0_6__SHIFT 0x00000010 -#define VGT_DBG_REG_55__gog_out_indx_13_0_7__SHIFT 0x00000011 -#define VGT_DBG_REG_55__gog_out_indx_13_0_8__SHIFT 0x00000012 -#define VGT_DBG_REG_55__gog_out_indx_13_0_9__SHIFT 0x00000013 -#define VGT_DBG_REG_55__gog_out_indx_13_0_10__SHIFT 0x00000014 -#define VGT_DBG_REG_55__gog_out_indx_13_0_11__SHIFT 0x00000015 -#define VGT_DBG_REG_55__gog_out_indx_13_0_12__SHIFT 0x00000016 -#define VGT_DBG_REG_55__gog_out_indx_13_0_13__SHIFT 0x00000017 -#define VGT_DBG_REG_55__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_56 -#define VGT_DBG_REG_56__grp_vr_valid__SHIFT 0x00000000 -#define VGT_DBG_REG_56__pipe0_dr__SHIFT 0x00000001 -#define VGT_DBG_REG_56__pipe1_dr__SHIFT 0x00000002 -#define VGT_DBG_REG_56__vr_grp_read__SHIFT 0x00000003 -#define VGT_DBG_REG_56__pipe0_rtr__SHIFT 0x00000004 -#define VGT_DBG_REG_56__pipe1_rtr__SHIFT 0x00000005 -#define VGT_DBG_REG_56__out_vr_indx_read__SHIFT 0x00000006 -#define VGT_DBG_REG_56__out_vr_prim_read__SHIFT 0x00000007 -#define VGT_DBG_REG_56__indices_to_send_q_0__SHIFT 0x00000008 -#define VGT_DBG_REG_56__indices_to_send_q_1__SHIFT 0x00000009 -#define VGT_DBG_REG_56__indices_to_send_q_2__SHIFT 0x0000000a -#define VGT_DBG_REG_56__valid_indices__SHIFT 0x0000000b -#define VGT_DBG_REG_56__last_indx_of_prim__SHIFT 0x0000000c -#define VGT_DBG_REG_56__indx0_new_d__SHIFT 0x0000000d -#define VGT_DBG_REG_56__indx1_new_d__SHIFT 0x0000000e -#define VGT_DBG_REG_56__indx2_new_d__SHIFT 0x0000000f -#define VGT_DBG_REG_56__indx2_hit_d__SHIFT 0x00000010 -#define VGT_DBG_REG_56__indx1_hit_d__SHIFT 0x00000011 -#define VGT_DBG_REG_56__indx0_hit_d__SHIFT 0x00000012 -#define VGT_DBG_REG_56__st_vertex_reuse_off_r0_q__SHIFT 0x00000013 -#define VGT_DBG_REG_56__last_group_of_instance_r0_q__SHIFT 0x00000014 -#define VGT_DBG_REG_56__null_primitive_r0_q__SHIFT 0x00000015 -#define VGT_DBG_REG_56__eop_r0_q__SHIFT 0x00000016 -#define VGT_DBG_REG_56__eject_vtx_vect_r1_d__SHIFT 0x00000017 -#define VGT_DBG_REG_56__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_57 -#define VGT_DBG_REG_57__sub_prim_type_r0_q_0__SHIFT 0x00000000 -#define VGT_DBG_REG_57__sub_prim_type_r0_q_1__SHIFT 0x00000001 -#define VGT_DBG_REG_57__sub_prim_type_r0_q_2__SHIFT 0x00000002 -#define VGT_DBG_REG_57__gs_scenario_a_r0_q__SHIFT 0x00000003 -#define VGT_DBG_REG_57__gs_scenario_b_r0_q__SHIFT 0x00000004 -#define VGT_DBG_REG_57__components_valid_r0_q_29__SHIFT 0x00000005 -#define VGT_DBG_REG_57__components_valid_r0_q_30__SHIFT 0x00000006 -#define VGT_DBG_REG_57__components_valid_r0_q_31__SHIFT 0x00000007 -#define VGT_DBG_REG_57__separate_out_busy_q__SHIFT 0x00000008 -#define VGT_DBG_REG_57__separate_out_indx_busy_q__SHIFT 0x00000009 -#define VGT_DBG_REG_57__prim_buffer_empty__SHIFT 0x0000000a -#define VGT_DBG_REG_57__prim_buffer_full__SHIFT 0x0000000b -#define VGT_DBG_REG_57__pa_clips_fifo_busy_q__SHIFT 0x0000000c -#define VGT_DBG_REG_57__pa_clipp_fifo_busy_q__SHIFT 0x0000000d -#define VGT_DBG_REG_57__VGT_PA_clips_rtr_q__SHIFT 0x0000000e -#define VGT_DBG_REG_57__VGT_PA_clipp_rtr_q__SHIFT 0x0000000f -#define VGT_DBG_REG_57__spi_vsthread_fifo_busy_q__SHIFT 0x00000010 -#define VGT_DBG_REG_57__spi_vsvert_fifo_busy_q__SHIFT 0x00000011 -#define VGT_DBG_REG_57__pa_clipv_fifo_busy_q__SHIFT 0x00000012 -#define VGT_DBG_REG_57__hold_prim__SHIFT 0x00000013 -#define VGT_DBG_REG_57__VGT_SPI_vsthread_rtr_q__SHIFT 0x00000014 -#define VGT_DBG_REG_57__VGT_SPI_vsvert_rtr_q__SHIFT 0x00000015 -#define VGT_DBG_REG_57__VGT_PA_clipv_rtr_q__SHIFT 0x00000016 -#define VGT_DBG_REG_57__new_packet_q__SHIFT 0x00000017 -#define VGT_DBG_REG_57__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_58 -#define VGT_DBG_REG_58__buffered_prim_event__SHIFT 0x00000000 -#define VGT_DBG_REG_58__buffered_prim_null_primitive__SHIFT 0x00000001 -#define VGT_DBG_REG_58__buffered_prim_eop__SHIFT 0x00000002 -#define VGT_DBG_REG_58__buffered_prim_eject_vtx_vect__SHIFT 0x00000003 -#define VGT_DBG_REG_58__buffered_prim_type_event_0__SHIFT 0x00000004 -#define VGT_DBG_REG_58__buffered_prim_type_event_1__SHIFT 0x00000005 -#define VGT_DBG_REG_58__buffered_prim_type_event_2__SHIFT 0x00000006 -#define VGT_DBG_REG_58__buffered_prim_type_event_3__SHIFT 0x00000007 -#define VGT_DBG_REG_58__buffered_prim_type_event_4__SHIFT 0x00000008 -#define VGT_DBG_REG_58__buffered_prim_type_event_5__SHIFT 0x00000009 -#define VGT_DBG_REG_58__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x0000000a -#define VGT_DBG_REG_58__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x0000000b -#define VGT_DBG_REG_58__num_new_unique_rel_indx_0__SHIFT 0x0000000c -#define VGT_DBG_REG_58__num_new_unique_rel_indx_1__SHIFT 0x0000000d -#define VGT_DBG_REG_58__null_terminate_vtx_vector__SHIFT 0x0000000e -#define VGT_DBG_REG_58__filter_event__SHIFT 0x0000000f -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_0__SHIFT 0x00000010 -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_1__SHIFT 0x00000011 -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_2__SHIFT 0x00000012 -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_3__SHIFT 0x00000013 -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_4__SHIFT 0x00000014 -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_5__SHIFT 0x00000015 -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_6__SHIFT 0x00000016 -#define VGT_DBG_REG_58__dbg_VGT_SPI_vsthread_sovertexindex_7__SHIFT 0x00000017 -#define VGT_DBG_REG_58__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_59 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_8__SHIFT 0x00000000 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_9__SHIFT 0x00000001 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_10__SHIFT 0x00000002 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_11__SHIFT 0x00000003 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_12__SHIFT 0x00000004 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_13__SHIFT 0x00000005 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_14__SHIFT 0x00000006 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexindex_15__SHIFT 0x00000007 -#define VGT_DBG_REG_59__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x00000008 -#define VGT_DBG_REG_59__Reserved1__SHIFT 0x00000009 -#define VGT_DBG_REG_59__alloc_counter_q_0__SHIFT 0x0000000a -#define VGT_DBG_REG_59__alloc_counter_q_1__SHIFT 0x0000000b -#define VGT_DBG_REG_59__alloc_counter_q_2__SHIFT 0x0000000c -#define VGT_DBG_REG_59__alloc_counter_q_3__SHIFT 0x0000000d -#define VGT_DBG_REG_59__curr_dealloc_distance_q_0__SHIFT 0x0000000e -#define VGT_DBG_REG_59__curr_dealloc_distance_q_1__SHIFT 0x0000000f -#define VGT_DBG_REG_59__curr_dealloc_distance_q_2__SHIFT 0x00000010 -#define VGT_DBG_REG_59__curr_dealloc_distance_q_3__SHIFT 0x00000011 -#define VGT_DBG_REG_59__curr_dealloc_distance_q_4__SHIFT 0x00000012 -#define VGT_DBG_REG_59__curr_dealloc_distance_q_5__SHIFT 0x00000013 -#define VGT_DBG_REG_59__curr_dealloc_distance_q_6__SHIFT 0x00000014 -#define VGT_DBG_REG_59__new_allocate_q__SHIFT 0x00000015 -#define VGT_DBG_REG_59__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x00000016 -#define VGT_DBG_REG_59__int_vtx_counter_q_not_0__SHIFT 0x00000017 -#define VGT_DBG_REG_59__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_60 -#define VGT_DBG_REG_60__out_indx_fifo_empty__SHIFT 0x00000000 -#define VGT_DBG_REG_60__indx_side_fifo_empty__SHIFT 0x00000001 -#define VGT_DBG_REG_60__pipe0_dr__SHIFT 0x00000002 -#define VGT_DBG_REG_60__pipe1_dr__SHIFT 0x00000003 -#define VGT_DBG_REG_60__pipe2_dr__SHIFT 0x00000004 -#define VGT_DBG_REG_60__vsthread_buff_empty__SHIFT 0x00000005 -#define VGT_DBG_REG_60__out_indx_fifo_full__SHIFT 0x00000006 -#define VGT_DBG_REG_60__indx_side_fifo_full__SHIFT 0x00000007 -#define VGT_DBG_REG_60__pipe0_rtr__SHIFT 0x00000008 -#define VGT_DBG_REG_60__pipe1_rtr__SHIFT 0x00000009 -#define VGT_DBG_REG_60__pipe2_rtr__SHIFT 0x0000000a -#define VGT_DBG_REG_60__vsthread_buff_full__SHIFT 0x0000000b -#define VGT_DBG_REG_60__interfaces_rtr__SHIFT 0x0000000c -#define VGT_DBG_REG_60__indx_count_q_not_0__SHIFT 0x0000000d -#define VGT_DBG_REG_60__wait_for_external_eopg_q__SHIFT 0x0000000e -#define VGT_DBG_REG_60__full_state_p1_q__SHIFT 0x0000000f -#define VGT_DBG_REG_60__indx_side_indx_valid__SHIFT 0x00000010 -#define VGT_DBG_REG_60__stateid_p0_q_0__SHIFT 0x00000011 -#define VGT_DBG_REG_60__stateid_p0_q_1__SHIFT 0x00000012 -#define VGT_DBG_REG_60__stateid_p0_q_2__SHIFT 0x00000013 -#define VGT_DBG_REG_60__is_event_p0_q__SHIFT 0x00000014 -#define VGT_DBG_REG_60__lshs_dealloc_p1__SHIFT 0x00000015 -#define VGT_DBG_REG_60__stream_id_r2_q__SHIFT 0x00000016 -#define VGT_DBG_REG_60__vtx_vect_counter_q_not_0__SHIFT 0x00000017 -#define VGT_DBG_REG_60__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_61 -#define VGT_DBG_REG_61__cm_state16_0__SHIFT 0x00000000 -#define VGT_DBG_REG_61__cm_state16_1__SHIFT 0x00000001 -#define VGT_DBG_REG_61__cm_state17_0__SHIFT 0x00000002 -#define VGT_DBG_REG_61__cm_state17_1__SHIFT 0x00000003 -#define VGT_DBG_REG_61__cm_state18_0__SHIFT 0x00000004 -#define VGT_DBG_REG_61__cm_state18_1__SHIFT 0x00000005 -#define VGT_DBG_REG_61__cm_state19_0__SHIFT 0x00000006 -#define VGT_DBG_REG_61__cm_state19_1__SHIFT 0x00000007 -#define VGT_DBG_REG_61__cm_state20_0__SHIFT 0x00000008 -#define VGT_DBG_REG_61__cm_state20_1__SHIFT 0x00000009 -#define VGT_DBG_REG_61__cm_state21_0__SHIFT 0x0000000a -#define VGT_DBG_REG_61__cm_state21_1__SHIFT 0x0000000b -#define VGT_DBG_REG_61__cm_state22_0__SHIFT 0x0000000c -#define VGT_DBG_REG_61__cm_state22_1__SHIFT 0x0000000d -#define VGT_DBG_REG_61__cm_state23_0__SHIFT 0x0000000e -#define VGT_DBG_REG_61__cm_state23_1__SHIFT 0x0000000f -#define VGT_DBG_REG_61__buff_full_p1__SHIFT 0x00000010 -#define VGT_DBG_REG_61__strmout_valid_p1__SHIFT 0x00000011 -#define VGT_DBG_REG_61__eotg_r2_q__SHIFT 0x00000012 -#define VGT_DBG_REG_61__null_r2_q__SHIFT 0x00000013 -#define VGT_DBG_REG_61__p0_dr__SHIFT 0x00000014 -#define VGT_DBG_REG_61__p0_rtr__SHIFT 0x00000015 -#define VGT_DBG_REG_61__eopg_p0_q__SHIFT 0x00000016 -#define VGT_DBG_REG_61__p0_nobp__SHIFT 0x00000017 -#define VGT_DBG_REG_61__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_62 -#define VGT_DBG_REG_62__cm_state24_0__SHIFT 0x00000000 -#define VGT_DBG_REG_62__cm_state24_1__SHIFT 0x00000001 -#define VGT_DBG_REG_62__cm_state25_0__SHIFT 0x00000002 -#define VGT_DBG_REG_62__cm_state25_1__SHIFT 0x00000003 -#define VGT_DBG_REG_62__cm_state26_0__SHIFT 0x00000004 -#define VGT_DBG_REG_62__cm_state26_1__SHIFT 0x00000005 -#define VGT_DBG_REG_62__cm_state27_0__SHIFT 0x00000006 -#define VGT_DBG_REG_62__cm_state27_1__SHIFT 0x00000007 -#define VGT_DBG_REG_62__cm_state28_0__SHIFT 0x00000008 -#define VGT_DBG_REG_62__cm_state28_1__SHIFT 0x00000009 -#define VGT_DBG_REG_62__cm_state29_0__SHIFT 0x0000000a -#define VGT_DBG_REG_62__cm_state29_1__SHIFT 0x0000000b -#define VGT_DBG_REG_62__cm_state30_0__SHIFT 0x0000000c -#define VGT_DBG_REG_62__cm_state30_1__SHIFT 0x0000000d -#define VGT_DBG_REG_62__cm_state31_0__SHIFT 0x0000000e -#define VGT_DBG_REG_62__cm_state31_1__SHIFT 0x0000000f -#define VGT_DBG_REG_62__frmt_busy__SHIFT 0x00000010 -#define VGT_DBG_REG_62__rcm_frmt_vert_rtr__SHIFT 0x00000011 -#define VGT_DBG_REG_62__rcm_frmt_prim_rtr__SHIFT 0x00000012 -#define VGT_DBG_REG_62__prim_r3_rtr__SHIFT 0x00000013 -#define VGT_DBG_REG_62__prim_r2_rtr__SHIFT 0x00000014 -#define VGT_DBG_REG_62__vert_r3_rtr__SHIFT 0x00000015 -#define VGT_DBG_REG_62__vert_r2_rtr__SHIFT 0x00000016 -#define VGT_DBG_REG_62__vert_r1_rtr__SHIFT 0x00000017 -#define VGT_DBG_REG_62__Reserved0__SHIFT 0x00000018 - -// VGT_DBG_REG_63 -#define VGT_DBG_REG_63__vert_r0_rtr__SHIFT 0x00000000 -#define VGT_DBG_REG_63__prim_fifo_empty__SHIFT 0x00000001 -#define VGT_DBG_REG_63__prim_fifo_full__SHIFT 0x00000002 -#define VGT_DBG_REG_63__vert_dr_r2_q__SHIFT 0x00000003 -#define VGT_DBG_REG_63__prim_dr_r2_q__SHIFT 0x00000004 -#define VGT_DBG_REG_63__vert_dr_r1_q__SHIFT 0x00000005 -#define VGT_DBG_REG_63__vert_dr_r0_q__SHIFT 0x00000006 -#define VGT_DBG_REG_63__new_verts_r2_q_0__SHIFT 0x00000007 -#define VGT_DBG_REG_63__new_verts_r2_q_1__SHIFT 0x00000008 -#define VGT_DBG_REG_63__verts_sent_r2_q_0__SHIFT 0x00000009 -#define VGT_DBG_REG_63__verts_sent_r2_q_1__SHIFT 0x0000000a -#define VGT_DBG_REG_63__verts_sent_r2_q_2__SHIFT 0x0000000b -#define VGT_DBG_REG_63__verts_sent_r2_q_3__SHIFT 0x0000000c -#define VGT_DBG_REG_63__prim_state_sel_r2_q_0__SHIFT 0x0000000d -#define VGT_DBG_REG_63__prim_state_sel_r2_q_1__SHIFT 0x0000000e -#define VGT_DBG_REG_63__prim_state_sel_r2_q_2__SHIFT 0x0000000f -#define VGT_DBG_REG_63__Reserved7__SHIFT 0x00000010 -#define VGT_DBG_REG_63__Reserved6__SHIFT 0x00000011 -#define VGT_DBG_REG_63__Reserved5__SHIFT 0x00000012 -#define VGT_DBG_REG_63__Reserved4__SHIFT 0x00000013 -#define VGT_DBG_REG_63__Reserved3__SHIFT 0x00000014 -#define VGT_DBG_REG_63__Reserved2__SHIFT 0x00000015 -#define VGT_DBG_REG_63__Reserved1__SHIFT 0x00000016 -#define VGT_DBG_REG_63__Reserved0__SHIFT 0x0000001f - -// spi_vs_wave_ctl0 -#define spi_vs_wave_ctl0__f_double_data__SHIFT 0x00000000 -#define spi_vs_wave_ctl0__f_vs_vert_gs_on__SHIFT 0x00000001 -#define spi_vs_wave_ctl0__f_gpr_ld_line_sel__SHIFT 0x00000002 -#define spi_vs_wave_ctl0__wave_buffer_fifo_empty__SHIFT 0x00000006 -#define spi_vs_wave_ctl0__vs_wave_first_subgrp__SHIFT 0x00000007 -#define spi_vs_wave_ctl0__gsc_vsc_group_cu_id__SHIFT 0x00000008 -#define spi_vs_wave_ctl0__vs_gdbg_en_q__SHIFT 0x0000000c -#define spi_vs_wave_ctl0__tr_fits__SHIFT 0x0000000d -#define spi_vs_wave_ctl0__vs_wave_cnt_lt_lim__SHIFT 0x0000000e -#define spi_vs_wave_ctl0__pipe_id__SHIFT 0x0000000f -#define spi_vs_wave_ctl0__late_alloc_lt_lim__SHIFT 0x00000010 -#define spi_vs_wave_ctl0__outstanding_waves__SHIFT 0x00000011 -#define spi_vs_wave_ctl0__outstanding_events__SHIFT 0x00000015 -#define spi_vs_wave_ctl0__Reserved0__SHIFT 0x00000018 - -// spi_vs_wave_ctl1 -#define spi_vs_wave_ctl1__crawler_is_event__SHIFT 0x00000000 -#define spi_vs_wave_ctl1__stall_events__SHIFT 0x00000001 -#define spi_vs_wave_ctl1__wave_done_crawler_id__SHIFT 0x00000002 -#define spi_vs_wave_ctl1__wave_done__SHIFT 0x0000000c -#define spi_vs_wave_ctl1__crawler_full__SHIFT 0x0000000d -#define spi_vs_wave_ctl1__crawler_empty__SHIFT 0x0000000e -#define spi_vs_wave_ctl1__crawler_rd__SHIFT 0x0000000f -#define spi_vs_wave_ctl1__Reserved0__SHIFT 0x00000018 - -// spi_vs_wave_ctl2 -#define spi_vs_wave_ctl2__res_alloc_state__SHIFT 0x00000000 -#define spi_vs_wave_ctl2__vsc_ra_rts__SHIFT 0x00000002 -#define spi_vs_wave_ctl2__clocks_on__SHIFT 0x00000003 -#define spi_vs_wave_ctl2__UNUSED_vsc_ra_alloc_req1__SHIFT 0x00000004 -#define spi_vs_wave_ctl2__vsc_ra_alloc_req0__SHIFT 0x00000005 -#define spi_vs_wave_ctl2__UNUSED_vsc_pc_posb1_alloc_req__SHIFT 0x00000006 -#define spi_vs_wave_ctl2__vsc_pc_posb0_alloc_req__SHIFT 0x00000007 -#define spi_vs_wave_ctl2__vsc_ra_cu_id__SHIFT 0x00000008 -#define spi_vs_wave_ctl2__hsc_group_cu_id__SHIFT 0x0000000c -#define spi_vs_wave_ctl2__hsc_group_fifo_empty__SHIFT 0x00000010 -#define spi_vs_wave_ctl2__vs_wave_first_wave__SHIFT 0x00000011 -#define spi_vs_wave_ctl2__vs_wave_stateid__SHIFT 0x00000012 -#define spi_vs_wave_ctl2__vs_wave_is_event__SHIFT 0x00000015 -#define spi_vs_wave_ctl2__vgt_vswave_fifo_empty__SHIFT 0x00000016 -#define spi_vs_wave_ctl2__gsc_vsc_group_fifo_empty__SHIFT 0x00000017 -#define spi_vs_wave_ctl2__Reserved0__SHIFT 0x00000018 - -// spi_gs_wave_ctl0 -#define spi_gs_wave_ctl0__f_double_data__SHIFT 0x00000000 -#define spi_gs_wave_ctl0__f_gpr_ld_buf_sel__SHIFT 0x00000001 -#define spi_gs_wave_ctl0__wave_buffer_fifo_empty__SHIFT 0x00000003 -#define spi_gs_wave_ctl0__gsc_vsc_group_fifo_empty__SHIFT 0x00000004 -#define spi_gs_wave_ctl0__gs_gdbg_en_q__SHIFT 0x00000005 -#define spi_gs_wave_ctl0__tr_fits__SHIFT 0x00000006 -#define spi_gs_wave_ctl0__gs_wave_cnt_lt_lim__SHIFT 0x00000007 -#define spi_gs_wave_ctl0__pipe_id__SHIFT 0x00000008 -#define spi_gs_wave_ctl0__outstanding_waves__SHIFT 0x0000000a -#define spi_gs_wave_ctl0__outstanding_events__SHIFT 0x0000000e -#define spi_gs_wave_ctl0__Reserved0__SHIFT 0x00000011 - -// spi_gs_wave_ctl1 -#define spi_gs_wave_ctl1__crawler_rd__SHIFT 0x00000000 -#define spi_gs_wave_ctl1__crawler_is_event__SHIFT 0x00000007 -#define spi_gs_wave_ctl1__stall_events__SHIFT 0x00000008 -#define spi_gs_wave_ctl1__wave_done_crawler_id__SHIFT 0x00000009 -#define spi_gs_wave_ctl1__wave_done__SHIFT 0x00000013 -#define spi_gs_wave_ctl1__crawler_full__SHIFT 0x00000014 -#define spi_gs_wave_ctl1__crawler_empty__SHIFT 0x00000015 -#define spi_gs_wave_ctl1__Reserved0__SHIFT 0x00000016 - -// spi_gs_wave_ctl2 -#define spi_gs_wave_ctl2__res_alloc_state__SHIFT 0x00000000 -#define spi_gs_wave_ctl2__clocks_on__SHIFT 0x00000001 -#define spi_gs_wave_ctl2__gsc_ra_rts__SHIFT 0x00000002 -#define spi_gs_wave_ctl2__UNUSED_gsc_ra_alloc_req1__SHIFT 0x00000003 -#define spi_gs_wave_ctl2__gsc_ra_alloc_req0__SHIFT 0x00000004 -#define spi_gs_wave_ctl2__gs_wave_stateid__SHIFT 0x00000005 -#define spi_gs_wave_ctl2__gs_wave_is_event__SHIFT 0x00000008 -#define spi_gs_wave_ctl2__vgt_gswave_fifo_empty__SHIFT 0x00000009 -#define spi_gs_wave_ctl2__gs_group_fifo_full__SHIFT 0x0000000a -#define spi_gs_wave_ctl2__gs_wave_first_subgrp__SHIFT 0x0000000b -#define spi_gs_wave_ctl2__gsc_ra0_cu_id__SHIFT 0x0000000c -#define spi_gs_wave_ctl2__esc_gsc_group_cu_id__SHIFT 0x00000010 -#define spi_gs_wave_ctl2__gs_onchip__SHIFT 0x00000014 -#define spi_gs_wave_ctl2__Reserved0__SHIFT 0x00000016 - -// spi_es_wave_ctl0 -#define spi_es_wave_ctl0__f_double_data__SHIFT 0x00000000 -#define spi_es_wave_ctl0__f_gpr_ld_buf_sel__SHIFT 0x00000001 -#define spi_es_wave_ctl0__wave_buffer_fifo_empty__SHIFT 0x00000003 -#define spi_es_wave_ctl0__esc_gsc_group_fifo_empty__SHIFT 0x00000004 -#define spi_es_wave_ctl0__es_gdbg_en_q__SHIFT 0x00000005 -#define spi_es_wave_ctl0__tr_fits__SHIFT 0x00000006 -#define spi_es_wave_ctl0__es_wave_cnt_lt_lim__SHIFT 0x00000007 -#define spi_es_wave_ctl0__pipe_id__SHIFT 0x00000008 -#define spi_es_wave_ctl0__outstanding_waves__SHIFT 0x0000000a -#define spi_es_wave_ctl0__outstanding_events__SHIFT 0x0000000e -#define spi_es_wave_ctl0__gs_onchip__SHIFT 0x00000011 -#define spi_es_wave_ctl0__es_wave_offchip__SHIFT 0x00000013 -#define spi_es_wave_ctl0__es_wave_first_subgrp__SHIFT 0x00000014 -#define spi_es_wave_ctl0__esc_ra0_is_ds__SHIFT 0x00000015 -#define spi_es_wave_ctl0__Reserved0__SHIFT 0x00000016 - -// spi_es_wave_ctl1 -#define spi_es_wave_ctl1__crawler_is_event__SHIFT 0x00000000 -#define spi_es_wave_ctl1__stall_events__SHIFT 0x00000001 -#define spi_es_wave_ctl1__wave_done_crawler_id__SHIFT 0x00000002 -#define spi_es_wave_ctl1__wave_done__SHIFT 0x0000000c -#define spi_es_wave_ctl1__crawler_full__SHIFT 0x0000000d -#define spi_es_wave_ctl1__crawler_empty__SHIFT 0x0000000e -#define spi_es_wave_ctl1__crawler_rd__SHIFT 0x0000000f -#define spi_es_wave_ctl1__Reserved0__SHIFT 0x00000018 - -// spi_es_wave_ctl2 -#define spi_es_wave_ctl2__res_alloc_state__SHIFT 0x00000000 -#define spi_es_wave_ctl2__esc_ra_rts__SHIFT 0x00000001 -#define spi_es_wave_ctl2__clocks_on__SHIFT 0x00000002 -#define spi_es_wave_ctl2__esc_ra_alloc_req1__SHIFT 0x00000003 -#define spi_es_wave_ctl2__esc_ra_alloc_req0__SHIFT 0x00000004 -#define spi_es_wave_ctl2__esc_ra_cu_id__SHIFT 0x00000005 -#define spi_es_wave_ctl2__hsc_group_cu_id__SHIFT 0x00000009 -#define spi_es_wave_ctl2__hsc_group_fifo_empty__SHIFT 0x0000000d -#define spi_es_wave_ctl2__es_wave_first_wave__SHIFT 0x0000000e -#define spi_es_wave_ctl2__es_wave_stateid__SHIFT 0x0000000f -#define spi_es_wave_ctl2__es_wave_is_event__SHIFT 0x00000012 -#define spi_es_wave_ctl2__vgt_eswave_fifo_empty__SHIFT 0x00000013 -#define spi_es_wave_ctl2__es_group_fifo_full__SHIFT 0x00000014 -#define spi_es_wave_ctl2__Reserved0__SHIFT 0x00000015 - -// spi_hs_wave_ctl0 -#define spi_hs_wave_ctl0__f_gpr_ld_line_sel__SHIFT 0x00000000 -#define spi_hs_wave_ctl0__wave_buffer_fifo_empty__SHIFT 0x00000002 -#define spi_hs_wave_ctl0__hsc_group_fifo_empty__SHIFT 0x00000003 -#define spi_hs_wave_ctl0__hs_gdbg_en_q__SHIFT 0x00000004 -#define spi_hs_wave_ctl0__tr_fits__SHIFT 0x00000005 -#define spi_hs_wave_ctl0__hs_wave_cnt_lt_lim__SHIFT 0x00000006 -#define spi_hs_wave_ctl0__pipe_id__SHIFT 0x00000007 -#define spi_hs_wave_ctl0__outstanding_waves__SHIFT 0x00000009 -#define spi_hs_wave_ctl0__outstanding_events__SHIFT 0x0000000d -#define spi_hs_wave_ctl0__es_is_ds__SHIFT 0x00000010 -#define spi_hs_wave_ctl0__Reserved0__SHIFT 0x00000011 - -// spi_hs_wave_ctl1 -#define spi_hs_wave_ctl1__crawler_rd__SHIFT 0x00000000 -#define spi_hs_wave_ctl1__crawler_is_event__SHIFT 0x00000007 -#define spi_hs_wave_ctl1__stall_events__SHIFT 0x00000008 -#define spi_hs_wave_ctl1__wave_done_crawler_id__SHIFT 0x00000009 -#define spi_hs_wave_ctl1__wave_done__SHIFT 0x00000013 -#define spi_hs_wave_ctl1__crawler_full__SHIFT 0x00000014 -#define spi_hs_wave_ctl1__crawler_empty__SHIFT 0x00000015 -#define spi_hs_wave_ctl1__Reserved0__SHIFT 0x00000016 - -// spi_hs_wave_ctl2 -#define spi_hs_wave_ctl2__res_alloc_state__SHIFT 0x00000000 -#define spi_hs_wave_ctl2__hsc_ra_rts__SHIFT 0x00000001 -#define spi_hs_wave_ctl2__clocks_on__SHIFT 0x00000002 -#define spi_hs_wave_ctl2__UNUSED_hsc_ra_alloc_req1__SHIFT 0x00000003 -#define spi_hs_wave_ctl2__hsc_ra_alloc_req0__SHIFT 0x00000004 -#define spi_hs_wave_ctl2__hsc_ra_cu_id__SHIFT 0x00000005 -#define spi_hs_wave_ctl2__lsc_hsc_group_cu_id__SHIFT 0x00000009 -#define spi_hs_wave_ctl2__lsc_hsc_group_fifo_empty__SHIFT 0x0000000d -#define spi_hs_wave_ctl2__hs_group_fifo_full__SHIFT 0x0000000e -#define spi_hs_wave_ctl2__hs_wave_first_wave__SHIFT 0x0000000f -#define spi_hs_wave_ctl2__hs_wave_stateid__SHIFT 0x00000010 -#define spi_hs_wave_ctl2__hs_wave_is_event__SHIFT 0x00000013 -#define spi_hs_wave_ctl2__vgt_hswave_fifo_empty__SHIFT 0x00000014 -#define spi_hs_wave_ctl2__Reserved0__SHIFT 0x00000015 - -// spi_ls_wave_ctl0 -#define spi_ls_wave_ctl0__f_vsr_ld_buf_sel__SHIFT 0x00000000 -#define spi_ls_wave_ctl0__wave_buffer_fifo_empty__SHIFT 0x00000002 -#define spi_ls_wave_ctl0__lsc_hsc_group_fifo_empty__SHIFT 0x00000003 -#define spi_ls_wave_ctl0__ls_gdbg_en_q__SHIFT 0x00000004 -#define spi_ls_wave_ctl0__tr_fits__SHIFT 0x00000005 -#define spi_ls_wave_ctl0__ls_wave_cnt_lt_lim__SHIFT 0x00000006 -#define spi_ls_wave_ctl0__pipe_id__SHIFT 0x00000007 -#define spi_ls_wave_ctl0__outstanding_waves__SHIFT 0x00000009 -#define spi_ls_wave_ctl0__outstanding_events__SHIFT 0x0000000d -#define spi_ls_wave_ctl0__Reserved0__SHIFT 0x00000010 - -// spi_ls_wave_ctl1 -#define spi_ls_wave_ctl1__crawler_rd__SHIFT 0x00000000 -#define spi_ls_wave_ctl1__crawler_is_event__SHIFT 0x00000007 -#define spi_ls_wave_ctl1__stall_events__SHIFT 0x00000008 -#define spi_ls_wave_ctl1__wave_done_crawler_id__SHIFT 0x00000009 -#define spi_ls_wave_ctl1__wave_done__SHIFT 0x00000013 -#define spi_ls_wave_ctl1__crawler_full__SHIFT 0x00000014 -#define spi_ls_wave_ctl1__crawler_empty__SHIFT 0x00000015 -#define spi_ls_wave_ctl1__Reserved0__SHIFT 0x00000016 - -// spi_ls_wave_ctl2 -#define spi_ls_wave_ctl2__res_alloc_state__SHIFT 0x00000000 -#define spi_ls_wave_ctl2__lsc_ra_rts__SHIFT 0x00000002 -#define spi_ls_wave_ctl2__clocks_on__SHIFT 0x00000003 -#define spi_ls_wave_ctl2__UNUSED_lsc_ra_alloc_req1__SHIFT 0x00000004 -#define spi_ls_wave_ctl2__lsc_ra_alloc_req0__SHIFT 0x00000005 -#define spi_ls_wave_ctl2__lsc_olm_alloc_req__SHIFT 0x00000006 -#define spi_ls_wave_ctl2__Reserved1__SHIFT 0x00000007 -#define spi_ls_wave_ctl2__ls_group_fifo_full__SHIFT 0x0000000b -#define spi_ls_wave_ctl2__ls_wave_first_wave__SHIFT 0x0000000c -#define spi_ls_wave_ctl2__ls_wave_stateid__SHIFT 0x0000000d -#define spi_ls_wave_ctl2__ls_wave_is_event__SHIFT 0x00000010 -#define spi_ls_wave_ctl2__vgt_lswave_fifo_empty__SHIFT 0x00000011 -#define spi_ls_wave_ctl2__Reserved0__SHIFT 0x00000012 - -// spi_cs_ctl_gfx0 -#define spi_cs_ctl_gfx0__UNUSED_remaining_threads1__SHIFT 0x00000000 -#define spi_cs_ctl_gfx0__remaining_threads0__SHIFT 0x00000007 -#define spi_cs_ctl_gfx0__UNUSED_csc_ra1_last_wave__SHIFT 0x0000000e -#define spi_cs_ctl_gfx0__csc_ra0_last_wave__SHIFT 0x0000000f -#define spi_cs_ctl_gfx0__UNUSED_csc_ra1_first_wave__SHIFT 0x00000010 -#define spi_cs_ctl_gfx0__csc_ra0_first_wave__SHIFT 0x00000011 -#define spi_cs_ctl_gfx0__csdata_is_state__SHIFT 0x00000012 -#define spi_cs_ctl_gfx0__csdata_is_event__SHIFT 0x00000013 -#define spi_cs_ctl_gfx0__cpg_csdata_fifo_empty__SHIFT 0x00000014 -#define spi_cs_ctl_gfx0__cpg_csdata_fifo_full__SHIFT 0x00000015 -#define spi_cs_ctl_gfx0__Reserved0__SHIFT 0x00000016 - -// spi_cs_ctl_gfx1 -#define spi_cs_ctl_gfx1__crw_event_id__SHIFT 0x00000000 -#define spi_cs_ctl_gfx1__crw_event_valid__SHIFT 0x00000006 -#define spi_cs_ctl_gfx1__stall_events__SHIFT 0x00000007 -#define spi_cs_ctl_gfx1__wave_done_crawler_id__SHIFT 0x00000008 -#define spi_cs_ctl_gfx1__wave_done__SHIFT 0x00000012 -#define spi_cs_ctl_gfx1__crawler_full__SHIFT 0x00000013 -#define spi_cs_ctl_gfx1__crawler_empty__SHIFT 0x00000014 -#define spi_cs_ctl_gfx1__event_count__SHIFT 0x00000015 -#define spi_cs_ctl_gfx1__Reserved0__SHIFT 0x00000018 - -// spi_cs_ctl_gfx2 -#define spi_cs_ctl_gfx2__send_to_shader_array_0__SHIFT 0x00000000 -#define spi_cs_ctl_gfx2__wave_count__SHIFT 0x00000001 -#define spi_cs_ctl_gfx2__waves_sent0_d__SHIFT 0x00000007 -#define spi_cs_ctl_gfx2__UNUSED_stall1__SHIFT 0x0000000d -#define spi_cs_ctl_gfx2__stall0__SHIFT 0x0000000e -#define spi_cs_ctl_gfx2__UNUSED_res_alloc_req1__SHIFT 0x0000000f -#define spi_cs_ctl_gfx2__res_alloc_req0__SHIFT 0x00000010 -#define spi_cs_ctl_gfx2__UNUSED_current_state1_q__SHIFT 0x00000011 -#define spi_cs_ctl_gfx2__current_state0_q__SHIFT 0x00000014 -#define spi_cs_ctl_gfx2__Reserved0__SHIFT 0x00000017 - -// spi_cs_ctl0 -#define spi_cs_ctl0__Reserved3__SHIFT 0x00000000 -#define spi_cs_ctl0__remaining_threads0__SHIFT 0x00000007 -#define spi_cs_ctl0__Reserved2__SHIFT 0x0000000e -#define spi_cs_ctl0__csc_ca_last_wave__SHIFT 0x0000000f -#define spi_cs_ctl0__Reserved1__SHIFT 0x00000010 -#define spi_cs_ctl0__csc_ca_first_wave__SHIFT 0x00000011 -#define spi_cs_ctl0__csdata_is_state__SHIFT 0x00000012 -#define spi_cs_ctl0__csdata_is_event__SHIFT 0x00000013 -#define spi_cs_ctl0__cpc_csdata_fifo_empty__SHIFT 0x00000014 -#define spi_cs_ctl0__cpc_csdata_fifo_full__SHIFT 0x00000015 -#define spi_cs_ctl0__Reserved0__SHIFT 0x00000016 - -// spi_cs_ctl1 -#define spi_cs_ctl1__crw_event_id__SHIFT 0x00000000 -#define spi_cs_ctl1__crw_event_valid__SHIFT 0x00000006 -#define spi_cs_ctl1__stall_events__SHIFT 0x00000007 -#define spi_cs_ctl1__wave_done_crawler_id__SHIFT 0x00000008 -#define spi_cs_ctl1__wave_done__SHIFT 0x00000012 -#define spi_cs_ctl1__crawler_full__SHIFT 0x00000013 -#define spi_cs_ctl1__crawler_empty__SHIFT 0x00000014 -#define spi_cs_ctl1__event_count__SHIFT 0x00000015 -#define spi_cs_ctl1__Reserved0__SHIFT 0x00000018 - -// spi_cs_ctl2 -#define spi_cs_ctl2__send_to_shader_array_0__SHIFT 0x00000000 -#define spi_cs_ctl2__wave_count__SHIFT 0x00000001 -#define spi_cs_ctl2__waves_sent0_d__SHIFT 0x00000007 -#define spi_cs_ctl2__Reserved3__SHIFT 0x0000000d -#define spi_cs_ctl2__stall0__SHIFT 0x0000000e -#define spi_cs_ctl2__Reserved2__SHIFT 0x0000000f -#define spi_cs_ctl2__res_alloc_req0__SHIFT 0x00000010 -#define spi_cs_ctl2__Reserved1__SHIFT 0x00000011 -#define spi_cs_ctl2__current_state0_q__SHIFT 0x00000014 -#define spi_cs_ctl2__Reserved0__SHIFT 0x00000017 - -// spi_gfx_tmp_ring_mgr -#define spi_gfx_tmp_ring_mgr__trm_tr_slots_used__SHIFT 0x00000000 -#define spi_gfx_tmp_ring_mgr__trm_hs_lock__SHIFT 0x00000009 -#define spi_gfx_tmp_ring_mgr__Reserved0__SHIFT 0x0000000a - -// spi_cs_wave_gfx_ctl -#define spi_cs_wave_gfx_ctl__tr_slots_used0__SHIFT 0x00000000 -#define spi_cs_wave_gfx_ctl__loader_state_q__SHIFT 0x00000009 -#define spi_cs_wave_gfx_ctl__Reserved2__SHIFT 0x0000000b -#define spi_cs_wave_gfx_ctl__csdata_is_private__SHIFT 0x0000000e -#define spi_cs_wave_gfx_ctl__csdata_is_tg__SHIFT 0x0000000f -#define spi_cs_wave_gfx_ctl__Reserved1__SHIFT 0x00000010 -#define spi_cs_wave_gfx_ctl__csc_ra0_first_req_dispatch__SHIFT 0x00000012 -#define spi_cs_wave_gfx_ctl__Reserved0__SHIFT 0x00000013 - -// spi_cs_wave_ctl -#define spi_cs_wave_ctl__tr_slots_used__SHIFT 0x00000000 -#define spi_cs_wave_ctl__loader_state_q__SHIFT 0x00000009 -#define spi_cs_wave_ctl__halt_state_q__SHIFT 0x0000000c -#define spi_cs_wave_ctl__csdata_is_private__SHIFT 0x0000000f -#define spi_cs_wave_ctl__csdata_is_tg__SHIFT 0x00000010 -#define spi_cs_wave_ctl__csc_ca_last_tg__SHIFT 0x00000011 -#define spi_cs_wave_ctl__csc_ca_first_tg__SHIFT 0x00000012 -#define spi_cs_wave_ctl__csc_ca_first_req_dispatch__SHIFT 0x00000013 -#define spi_cs_wave_ctl__Reserved0__SHIFT 0x00000014 - -// spi_ps_ctl0_0 -#define spi_ps_ctl0_0__new_vector1_save_q__SHIFT 0x00000000 -#define spi_ps_ctl0_0__new_vector0_save_q__SHIFT 0x00000001 -#define spi_ps_ctl0_0__vtx_sync_cnt_q__SHIFT 0x00000002 -#define spi_ps_ctl0_0__vtx_sync_wrapped__SHIFT 0x0000000a -#define spi_ps_ctl0_0__ose_vtx_sync_cnt_q__SHIFT 0x0000000b -#define spi_ps_ctl0_0__psc_wr_line_q__SHIFT 0x00000013 -#define spi_ps_ctl0_0__psc_gdbg_en_q__SHIFT 0x00000016 -#define spi_ps_ctl0_0__Reserved0__SHIFT 0x00000017 - -// spi_ps_ctl0_1 -#define spi_ps_ctl0_1__wd_end_of_wave__SHIFT 0x00000000 -#define spi_ps_ctl0_1__wd_fifo_empty__SHIFT 0x00000001 -#define spi_ps_ctl0_1__wd_fifo_full__SHIFT 0x00000002 -#define spi_ps_ctl0_1__ef_end_of_wave__SHIFT 0x00000003 -#define spi_ps_ctl0_1__ef_state_id__SHIFT 0x00000004 -#define spi_ps_ctl0_1__ef_event_id__SHIFT 0x00000007 -#define spi_ps_ctl0_1__ef_event__SHIFT 0x0000000d -#define spi_ps_ctl0_1__ef_new1__SHIFT 0x0000000e -#define spi_ps_ctl0_1__ef_new0__SHIFT 0x0000000f -#define spi_ps_ctl0_1__ef_empty__SHIFT 0x00000010 -#define spi_ps_ctl0_1__ef_full__SHIFT 0x00000011 -#define spi_ps_ctl0_1__ef_new3__SHIFT 0x00000012 -#define spi_ps_ctl0_1__ef_new2__SHIFT 0x00000013 -#define spi_ps_ctl0_1__pipe_id__SHIFT 0x00000014 -#define spi_ps_ctl0_1__Reserved0__SHIFT 0x00000016 - -// spi_ps_ctl0_2 -#define spi_ps_ctl0_2__res_alloc_state__SHIFT 0x00000000 -#define spi_ps_ctl0_2__psr_wave_cnt__SHIFT 0x00000001 -#define spi_ps_ctl0_2__psc_read_data__SHIFT 0x00000007 -#define spi_ps_ctl0_2__pc_free_cnt__SHIFT 0x0000000c -#define spi_ps_ctl0_2__dealloc1_save_q__SHIFT 0x00000010 -#define spi_ps_ctl0_2__dealloc0_save_q__SHIFT 0x00000013 -#define spi_ps_ctl0_2__tr_fits__SHIFT 0x00000016 -#define spi_ps_ctl0_2__ps_wave_cnt_lt_lim__SHIFT 0x00000017 -#define spi_ps_ctl0_2__Reserved0__SHIFT 0x00000018 - -// spi_ps_ctl0_3 -#define spi_ps_ctl0_3__new_vector2_save_q__SHIFT 0x00000000 -#define spi_ps_ctl0_3__new_vector3_save_q__SHIFT 0x00000001 -#define spi_ps_ctl0_3__ose1_vtx_sync_cnt_q__SHIFT 0x00000002 -#define spi_ps_ctl0_3__ose2_vtx_sync_cnt_q__SHIFT 0x0000000a -#define spi_ps_ctl0_3__dealloc2_save_q__SHIFT 0x00000012 -#define spi_ps_ctl0_3__dealloc3_save_q__SHIFT 0x00000015 -#define spi_ps_ctl0_3__Reserved0__SHIFT 0x00000018 - -// spi_ps_ctl0_4 -#define spi_ps_ctl0_4__crawler_rd__SHIFT 0x00000000 -#define spi_ps_ctl0_4__crawler_is_event__SHIFT 0x00000007 -#define spi_ps_ctl0_4__stall_events__SHIFT 0x00000008 -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_crawler_id_q__SHIFT 0x00000009 -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_ps_pkr_id_q__SHIFT 0x00000011 -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_wave_type_q__SHIFT 0x00000012 -#define spi_ps_ctl0_4__SPIS_SPIM_wbcrw_wave_done_q__SHIFT 0x00000015 -#define spi_ps_ctl0_4__crawler_full__SHIFT 0x00000016 -#define spi_ps_ctl0_4__crawler_empty__SHIFT 0x00000017 -#define spi_ps_ctl0_4__Reserved0__SHIFT 0x00000018 - -// spi_ps_ctl1_0 -#define spi_ps_ctl1_0__new_vector1_save_q__SHIFT 0x00000000 -#define spi_ps_ctl1_0__new_vector0_save_q__SHIFT 0x00000001 -#define spi_ps_ctl1_0__vtx_sync_cnt_q__SHIFT 0x00000002 -#define spi_ps_ctl1_0__vtx_sync_wrapped__SHIFT 0x0000000a -#define spi_ps_ctl1_0__ose_vtx_sync_cnt_q__SHIFT 0x0000000b -#define spi_ps_ctl1_0__psc_wr_line_q__SHIFT 0x00000013 -#define spi_ps_ctl1_0__psc_gdbg_en_q__SHIFT 0x00000016 -#define spi_ps_ctl1_0__Reserved0__SHIFT 0x00000017 - -// spi_ps_ctl1_1 -#define spi_ps_ctl1_1__wd_end_of_wave__SHIFT 0x00000000 -#define spi_ps_ctl1_1__wd_fifo_empty__SHIFT 0x00000001 -#define spi_ps_ctl1_1__wd_fifo_full__SHIFT 0x00000002 -#define spi_ps_ctl1_1__ef_end_of_wave__SHIFT 0x00000003 -#define spi_ps_ctl1_1__ef_state_id__SHIFT 0x00000004 -#define spi_ps_ctl1_1__ef_event_id__SHIFT 0x00000007 -#define spi_ps_ctl1_1__ef_event__SHIFT 0x0000000d -#define spi_ps_ctl1_1__ef_new1__SHIFT 0x0000000e -#define spi_ps_ctl1_1__ef_new0__SHIFT 0x0000000f -#define spi_ps_ctl1_1__ef_empty__SHIFT 0x00000010 -#define spi_ps_ctl1_1__ef_full__SHIFT 0x00000011 -#define spi_ps_ctl1_1__ef_new3__SHIFT 0x00000012 -#define spi_ps_ctl1_1__ef_new2__SHIFT 0x00000013 -#define spi_ps_ctl1_1__pipe_id__SHIFT 0x00000014 -#define spi_ps_ctl1_1__Reserved0__SHIFT 0x00000016 - -// spi_ps_ctl1_2 -#define spi_ps_ctl1_2__res_alloc_state__SHIFT 0x00000000 -#define spi_ps_ctl1_2__psr_wave_cnt__SHIFT 0x00000001 -#define spi_ps_ctl1_2__psc_read_data__SHIFT 0x00000007 -#define spi_ps_ctl1_2__pc_free_cnt__SHIFT 0x0000000c -#define spi_ps_ctl1_2__dealloc1_save_q__SHIFT 0x00000010 -#define spi_ps_ctl1_2__dealloc0_save_q__SHIFT 0x00000013 -#define spi_ps_ctl1_2__tr_fits__SHIFT 0x00000016 -#define spi_ps_ctl1_2__ps_wave_cnt_lt_lim__SHIFT 0x00000017 -#define spi_ps_ctl1_2__Reserved0__SHIFT 0x00000018 - -// spi_ps_ctl1_3 -#define spi_ps_ctl1_3__new_vector2_save_q__SHIFT 0x00000000 -#define spi_ps_ctl1_3__new_vector3_save_q__SHIFT 0x00000001 -#define spi_ps_ctl1_3__ose1_vtx_sync_cnt_q__SHIFT 0x00000002 -#define spi_ps_ctl1_3__ose2_vtx_sync_cnt_q__SHIFT 0x0000000a -#define spi_ps_ctl1_3__dealloc2_save_q__SHIFT 0x00000012 -#define spi_ps_ctl1_3__dealloc3_save_q__SHIFT 0x00000015 -#define spi_ps_ctl1_3__Reserved0__SHIFT 0x00000018 - -// spi_ps_ctl1_4 -#define spi_ps_ctl1_4__crawler_rd__SHIFT 0x00000000 -#define spi_ps_ctl1_4__crawler_is_event__SHIFT 0x00000007 -#define spi_ps_ctl1_4__stall_events__SHIFT 0x00000008 -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_crawler_id_q_7_0__SHIFT 0x00000009 -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_ps_pkr_id_q__SHIFT 0x00000011 -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_wave_type_q__SHIFT 0x00000012 -#define spi_ps_ctl1_4__SPIS_SPIM_wbcrw_wave_done_q__SHIFT 0x00000015 -#define spi_ps_ctl1_4__crawler_full__SHIFT 0x00000016 -#define spi_ps_ctl1_4__crawler_empty__SHIFT 0x00000017 -#define spi_ps_ctl1_4__Reserved0__SHIFT 0x00000018 - -// spi_pc_dealloc_ctl0 -#define spi_pc_dealloc_ctl0__decr_pc_dealloc_cnt__SHIFT 0x00000000 -#define spi_pc_dealloc_ctl0__pc_dealloc_min_cnt__SHIFT 0x00000001 -#define spi_pc_dealloc_ctl0__pc0_dealloc_cnt__SHIFT 0x0000000b -#define spi_pc_dealloc_ctl0__Reserved0__SHIFT 0x00000015 - -// spi_pc_dealloc_ctl1 -#define spi_pc_dealloc_ctl1__pc1_dealloc_cnt__SHIFT 0x00000000 -#define spi_pc_dealloc_ctl1__pc_deallocIn0_cnt__SHIFT 0x0000000a -#define spi_pc_dealloc_ctl1__Reserved0__SHIFT 0x00000014 - -// spi_pc_dealloc_ctl2 -#define spi_pc_dealloc_ctl2__pc_deallocIn1_cnt__SHIFT 0x00000000 -#define spi_pc_dealloc_ctl2__pc_deallocIn2_cnt__SHIFT 0x0000000a -#define spi_pc_dealloc_ctl2__Reserved0__SHIFT 0x00000014 - -// spi_pc_dealloc_ctl3 -#define spi_pc_dealloc_ctl3__pc0_deallocOut0_cnt__SHIFT 0x00000000 -#define spi_pc_dealloc_ctl3__pc0_deallocOut1_cnt__SHIFT 0x0000000a -#define spi_pc_dealloc_ctl3__Reserved0__SHIFT 0x00000014 - -// spi_pc_dealloc_ctl4 -#define spi_pc_dealloc_ctl4__pc0_deallocOut2_cnt__SHIFT 0x00000000 -#define spi_pc_dealloc_ctl4__pc1_deallocOut0_cnt__SHIFT 0x0000000a -#define spi_pc_dealloc_ctl4__Reserved0__SHIFT 0x00000014 - -// spi_pc_dealloc_ctl5 -#define spi_pc_dealloc_ctl5__pc1_deallocOut1_cnt__SHIFT 0x00000000 -#define spi_pc_dealloc_ctl5__pc1_deallocOut2_cnt__SHIFT 0x0000000a -#define spi_pc_dealloc_ctl5__Reserved0__SHIFT 0x00000014 - -// spi_offchip_lds_mgr0 -#define spi_offchip_lds_mgr0__es_threadgroup_done_count__SHIFT 0x00000000 -#define spi_offchip_lds_mgr0__Reserved2__SHIFT 0x00000007 -#define spi_offchip_lds_mgr0__lds_offchip_tail__SHIFT 0x00000008 -#define spi_offchip_lds_mgr0__Reserved1__SHIFT 0x0000000f -#define spi_offchip_lds_mgr0__lds_offchip_head__SHIFT 0x00000010 -#define spi_offchip_lds_mgr0__Reserved0__SHIFT 0x00000017 - -// spi_offchip_lds_mgr1 -#define spi_offchip_lds_mgr1__lds_offchip_full__SHIFT 0x00000000 -#define spi_offchip_lds_mgr1__order_fifo_rd__SHIFT 0x00000001 -#define spi_offchip_lds_mgr1__order_fifo_full__SHIFT 0x00000002 -#define spi_offchip_lds_mgr1__order_fifo_empty__SHIFT 0x00000003 -#define spi_offchip_lds_mgr1__esc_olm_ds_offchip_done__SHIFT 0x00000004 -#define spi_offchip_lds_mgr1__vsc_olm_ds_offchip_done__SHIFT 0x00000005 -#define spi_offchip_lds_mgr1__Reserved1__SHIFT 0x00000006 -#define spi_offchip_lds_mgr1__vs_threadgroup_done_count__SHIFT 0x00000008 -#define spi_offchip_lds_mgr1__Reserved0__SHIFT 0x0000000f - -// spi_lds_wr_ctl0 -#define spi_lds_wr_ctl0__state_id__SHIFT 0x00000000 -#define spi_lds_wr_ctl0__lds_in_fifo_empty__SHIFT 0x00000003 -#define spi_lds_wr_ctl0__lds_in_fifo_full__SHIFT 0x00000004 -#define spi_lds_wr_ctl0__lds_write_state__SHIFT 0x00000005 -#define spi_lds_wr_ctl0__even_debug_lds_valid_d__SHIFT 0x00000007 -#define spi_lds_wr_ctl0__even_debug_lds_valid_q1__SHIFT 0x00000008 -#define spi_lds_wr_ctl0__even_debug_lwc_pc_valid__SHIFT 0x00000009 -#define spi_lds_wr_ctl0__even_debug_lds_param_sent_cnt_q__SHIFT 0x0000000a -#define spi_lds_wr_ctl0__even_debug_lds_pass_cnt_q__SHIFT 0x00000010 -#define spi_lds_wr_ctl0__even_debug_stall_odd__SHIFT 0x00000014 -#define spi_lds_wr_ctl0__Reserved0__SHIFT 0x00000015 - -// spi_lds_wr_ctl1 -#define spi_lds_wr_ctl1__odd_debug_lds_valid_d__SHIFT 0x00000000 -#define spi_lds_wr_ctl1__odd_debug_lds_valid_q1__SHIFT 0x00000001 -#define spi_lds_wr_ctl1__odd_debug_lwc_pc_valid__SHIFT 0x00000002 -#define spi_lds_wr_ctl1__odd_debug_lds_param_sent_cnt_q__SHIFT 0x00000003 -#define spi_lds_wr_ctl1__odd_debug_lds_pass_cnt_q__SHIFT 0x00000009 -#define spi_lds_wr_ctl1__Reserved0__SHIFT 0x0000000d - -// spi_resource_alloc0 -#define spi_resource_alloc0__Reserved1__SHIFT 0x00000000 -#define spi_resource_alloc0__lds_updating_cu_simd_id_q__SHIFT 0x00000001 -#define spi_resource_alloc0__sgpr_updating_cu_simd_id_q__SHIFT 0x00000005 -#define spi_resource_alloc0__vgpr_updating_cu_simd_id_q__SHIFT 0x0000000b -#define spi_resource_alloc0__allocating_cu_simd_q__SHIFT 0x00000011 -#define spi_resource_alloc0__Reserved0__SHIFT 0x00000017 - -// spi_resource_alloc1 -#define spi_resource_alloc1__vgpr_dealloc_pointer_23_0__SHIFT 0x00000000 -#define spi_resource_alloc1__Reserved0__SHIFT 0x00000018 - -// spi_resource_alloc2 -#define spi_resource_alloc2__vgpr_dealloc_pointer_47_24__SHIFT 0x00000000 -#define spi_resource_alloc2__Reserved0__SHIFT 0x00000018 - -// spi_resource_alloc3 -#define spi_resource_alloc3__sgpr_dealloc_pointer_23_0__SHIFT 0x00000000 -#define spi_resource_alloc3__Reserved0__SHIFT 0x00000018 - -// spi_resource_alloc4 -#define spi_resource_alloc4__sgpr_dealloc_pointer_47_24__SHIFT 0x00000000 -#define spi_resource_alloc4__Reserved0__SHIFT 0x00000018 - -// spi_resource_alloc5 -#define spi_resource_alloc5__Reserved0__SHIFT 0x00000000 - -// spi_resource_alloc6 -#define spi_resource_alloc6__sgpr_max_fits_cnt__SHIFT 0x00000000 -#define spi_resource_alloc6__vgpr_max_fits_cnt__SHIFT 0x00000007 -#define spi_resource_alloc6__dbg_cu_simd_id__SHIFT 0x0000000e -#define spi_resource_alloc6__Reserved0__SHIFT 0x00000014 - -// spi_resource_alloc7 -#define spi_resource_alloc7__alloc_state_q__SHIFT 0x00000000 -#define spi_resource_alloc7__ts_priority__SHIFT 0x00000001 -#define spi_resource_alloc7__dbg_lds_dealloc_pointer__SHIFT 0x00000004 -#define spi_resource_alloc7__Reserved0__SHIFT 0x00000014 - -// spi_resource_alloc8 -#define spi_resource_alloc8__dbg_lock_mask__SHIFT 0x00000000 -#define spi_resource_alloc8__Reserved0__SHIFT 0x00000010 - -// spi_resource_alloc9 -#define spi_resource_alloc9__wave_cnt_cu_simd__SHIFT 0x00000000 -#define spi_resource_alloc9__vgpr_rsv_max_fits_cnt__SHIFT 0x00000004 -#define spi_resource_alloc9__sgpr_rsv_max_fits_cnt__SHIFT 0x0000000b -#define spi_resource_alloc9__Reserved0__SHIFT 0x00000012 - -// spi_resource_alloc10 -#define spi_resource_alloc10__barrier_cnt_per_cu__SHIFT 0x00000000 -#define spi_resource_alloc10__lds_rsv_max_fits_cnt__SHIFT 0x00000005 -#define spi_resource_alloc10__Reserved1__SHIFT 0x0000000d -#define spi_resource_alloc10__lds_max_fits_cnt__SHIFT 0x0000000e -#define spi_resource_alloc10__Reserved0__SHIFT 0x00000016 - -// spi_clk_gate0 -#define spi_clk_gate0__read_ack_out__SHIFT 0x00000000 -#define spi_clk_gate0__program_ack_out__SHIFT 0x00000001 -#define spi_clk_gate0__sm_busy_out__SHIFT 0x00000002 -#define spi_clk_gate0__force_data_out__SHIFT 0x00000003 -#define spi_clk_gate0__data_out__SHIFT 0x00000004 -#define spi_clk_gate0__valid_out__SHIFT 0x00000005 -#define spi_clk_gate0__state_out__SHIFT 0x00000006 -#define spi_clk_gate0__program_out__SHIFT 0x00000007 -#define spi_clk_gate0__curr_sm_state__SHIFT 0x00000008 -#define spi_clk_gate0__off_cmd__SHIFT 0x0000000d -#define spi_clk_gate0__all_clks_on_flag_in__SHIFT 0x0000000e -#define spi_clk_gate0__off_flag_in__SHIFT 0x0000000f -#define spi_clk_gate0__read_flag_in__SHIFT 0x00000010 -#define spi_clk_gate0__program_flag_in__SHIFT 0x00000011 -#define spi_clk_gate0__on_cmd__SHIFT 0x00000012 -#define spi_clk_gate0__on_flag_in__SHIFT 0x00000013 -#define spi_clk_gate0__force_override_in__SHIFT 0x00000014 -#define spi_clk_gate0__cgtt_reg_oclk_vld__SHIFT 0x00000015 -#define spi_clk_gate0__cgtt_dyn_oclk_vld__SHIFT 0x00000016 -#define spi_clk_gate0__Reserved0__SHIFT 0x00000017 - -// spi_clk_gate1 -#define spi_clk_gate1__off_seq_cnt_eq0__SHIFT 0x00000000 -#define spi_clk_gate1__off_seq_cnt_decr__SHIFT 0x00000001 -#define spi_clk_gate1__off_seq_cnt_ld__SHIFT 0x00000002 -#define spi_clk_gate1__on_seq_cnt_eq0__SHIFT 0x00000003 -#define spi_clk_gate1__on_seq_cnt_decr__SHIFT 0x00000004 -#define spi_clk_gate1__on_seq_cnt_ld__SHIFT 0x00000005 -#define spi_clk_gate1__blk_row_cnt_last__SHIFT 0x00000006 -#define spi_clk_gate1__mxn_bit_cnt_last__SHIFT 0x00000007 -#define spi_clk_gate1__cu_cnt_out__SHIFT 0x00000008 -#define spi_clk_gate1__blk_row_cnt_out__SHIFT 0x0000000c -#define spi_clk_gate1__blk_row_cnt_sel_out__SHIFT 0x00000010 -#define spi_clk_gate1__Reserved1__SHIFT 0x00000011 -#define spi_clk_gate1__mxn_bit_reg_ld_out__SHIFT 0x00000012 -#define spi_clk_gate1__mxn_bit_reg_shift_out__SHIFT 0x00000013 -#define spi_clk_gate1__Reserved0__SHIFT 0x00000014 - -// spi_clk_gate2 -#define spi_clk_gate2__on_monitor_cnt_10_0__SHIFT 0x00000000 -#define spi_clk_gate2__clkgate_all_on_out__SHIFT 0x0000000b -#define spi_clk_gate2__spi_active_in__SHIFT 0x0000000c -#define spi_clk_gate2__data_out__SHIFT 0x0000000d -#define spi_clk_gate2__on_monitor_flag__SHIFT 0x0000000e -#define spi_clk_gate2__off_seq_decode__SHIFT 0x0000000f -#define spi_clk_gate2__on_seq_decode__SHIFT 0x00000010 -#define spi_clk_gate2__ctrl_ls_override__SHIFT 0x00000011 -#define spi_clk_gate2__rss_clkgate_en_combined__SHIFT 0x00000012 -#define spi_clk_gate2__rss_cnt_eq0__SHIFT 0x00000013 -#define spi_clk_gate2__rss_cnt_ld__SHIFT 0x00000014 -#define spi_clk_gate2__Reserved0__SHIFT 0x00000015 - -// spi_clk_gate3 -#define spi_clk_gate3__rd_row_mux_sel__SHIFT 0x00000000 -#define spi_clk_gate3__rd_reg_loaded_dummy__SHIFT 0x00000005 -#define spi_clk_gate3__rdbus_data__SHIFT 0x00000006 -#define spi_clk_gate3__rdbus_valid__SHIFT 0x00000007 -#define spi_clk_gate3__rd_reg_loaded__SHIFT 0x00000008 -#define spi_clk_gate3__Reserved0__SHIFT 0x00000012 - -// CPC_debug_bus0_p0 -#define CPC_debug_bus0_p0__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p0__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p0__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p0__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p0__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p0 -#define CPC_debug_bus1_p0__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p0__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p0__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p0 -#define CPC_debug_bus2_p0__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p0__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p0__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p0__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p0__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p0__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p0__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p0__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p0__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p0__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p0__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p0__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p0__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p0__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p0__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p0__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p0__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p0 -#define CPC_debug_bus3_p0__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p0__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p0__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p0__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p0 -#define CPC_debug_bus4_p0__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p0__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p0__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus0_p1 -#define CPC_debug_bus0_p1__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p1__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p1__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p1__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p1__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p1 -#define CPC_debug_bus1_p1__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p1__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p1__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p1 -#define CPC_debug_bus2_p1__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p1__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p1__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p1__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p1__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p1__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p1__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p1__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p1__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p1__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p1__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p1__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p1__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p1__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p1__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p1__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p1__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p1 -#define CPC_debug_bus3_p1__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p1__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p1__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p1__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p1 -#define CPC_debug_bus4_p1__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p1__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p1__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus0_p2 -#define CPC_debug_bus0_p2__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p2__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p2__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p2__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p2__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p2 -#define CPC_debug_bus1_p2__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p2__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p2__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p2 -#define CPC_debug_bus2_p2__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p2__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p2__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p2__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p2__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p2__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p2__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p2__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p2__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p2__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p2__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p2__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p2__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p2__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p2__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p2__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p2__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p2 -#define CPC_debug_bus3_p2__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p2__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p2__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p2__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p2 -#define CPC_debug_bus4_p2__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p2__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p2__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus0_p3 -#define CPC_debug_bus0_p3__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p3__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p3__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p3__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p3__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p3 -#define CPC_debug_bus1_p3__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p3__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p3__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p3 -#define CPC_debug_bus2_p3__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p3__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p3__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p3__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p3__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p3__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p3__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p3__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p3__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p3__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p3__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p3__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p3__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p3__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p3__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p3__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p3__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p3 -#define CPC_debug_bus3_p3__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p3__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p3__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p3__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p3 -#define CPC_debug_bus4_p3__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p3__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p3__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus0_p4 -#define CPC_debug_bus0_p4__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p4__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p4__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p4__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p4__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p4 -#define CPC_debug_bus1_p4__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p4__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p4__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p4 -#define CPC_debug_bus2_p4__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p4__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p4__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p4__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p4__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p4__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p4__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p4__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p4__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p4__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p4__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p4__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p4__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p4__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p4__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p4__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p4__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p4 -#define CPC_debug_bus3_p4__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p4__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p4__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p4__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p4 -#define CPC_debug_bus4_p4__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p4__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p4__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus0_p5 -#define CPC_debug_bus0_p5__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p5__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p5__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p5__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p5__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p5 -#define CPC_debug_bus1_p5__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p5__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p5__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p5 -#define CPC_debug_bus2_p5__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p5__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p5__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p5__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p5__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p5__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p5__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p5__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p5__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p5__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p5__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p5__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p5__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p5__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p5__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p5__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p5__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p5 -#define CPC_debug_bus3_p5__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p5__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p5__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p5__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p5 -#define CPC_debug_bus4_p5__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p5__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p5__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus0_p6 -#define CPC_debug_bus0_p6__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p6__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p6__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p6__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p6__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p6 -#define CPC_debug_bus1_p6__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p6__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p6__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p6 -#define CPC_debug_bus2_p6__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p6__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p6__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p6__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p6__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p6__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p6__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p6__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p6__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p6__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p6__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p6__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p6__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p6__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p6__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p6__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p6__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p6 -#define CPC_debug_bus3_p6__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p6__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p6__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p6__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p6 -#define CPC_debug_bus4_p6__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p6__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p6__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus0_p7 -#define CPC_debug_bus0_p7__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus0_p7__gd_data_type__SHIFT 0x00000001 -#define CPC_debug_bus0_p7__gd_addr__SHIFT 0x00000003 -#define CPC_debug_bus0_p7__gd_data_13_0__SHIFT 0x0000000a -#define CPC_debug_bus0_p7__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus1_p7 -#define CPC_debug_bus1_p7__gd_valid__SHIFT 0x00000000 -#define CPC_debug_bus1_p7__gd_data_31_14__SHIFT 0x00000001 -#define CPC_debug_bus1_p7__Reserved0__SHIFT 0x00000013 - -// CPC_debug_bus2_p7 -#define CPC_debug_bus2_p7__valid_q0__SHIFT 0x00000000 -#define CPC_debug_bus2_p7__state_q__SHIFT 0x00000001 -#define CPC_debug_bus2_p7__steering_state_q__SHIFT 0x00000005 -#define CPC_debug_bus2_p7__first_thread_group_q0__SHIFT 0x00000008 -#define CPC_debug_bus2_p7__last_thread_group_q0__SHIFT 0x00000009 -#define CPC_debug_bus2_p7__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPC_debug_bus2_p7__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPC_debug_bus2_p7__gd_stall__SHIFT 0x0000000c -#define CPC_debug_bus2_p7__disp_stall_q__SHIFT 0x0000000d -#define CPC_debug_bus2_p7__no_serializer_is_busy__SHIFT 0x0000000e -#define CPC_debug_bus2_p7__gd_dispatch_busy__SHIFT 0x0000000f -#define CPC_debug_bus2_p7__gd_busy__SHIFT 0x00000010 -#define CPC_debug_bus2_p7__num_se_with_cu_active__SHIFT 0x00000011 -#define CPC_debug_bus2_p7__send_num_threads_x_q__SHIFT 0x00000014 -#define CPC_debug_bus2_p7__send_num_threads_y_q__SHIFT 0x00000015 -#define CPC_debug_bus2_p7__send_num_threads_z_q__SHIFT 0x00000016 -#define CPC_debug_bus2_p7__Reserved0__SHIFT 0x00000017 - -// CPC_debug_bus3_p7 -#define CPC_debug_bus3_p7__gddata_send__SHIFT 0x00000000 -#define CPC_debug_bus3_p7__gddata_data_type__SHIFT 0x00000001 -#define CPC_debug_bus3_p7__data_x_q1_20_0__SHIFT 0x00000003 -#define CPC_debug_bus3_p7__Reserved0__SHIFT 0x00000018 - -// CPC_debug_bus4_p7 -#define CPC_debug_bus4_p7__data_y_q1_11_0__SHIFT 0x00000000 -#define CPC_debug_bus4_p7__data_z_q1_11_0__SHIFT 0x0000000c -#define CPC_debug_bus4_p7__Reserved0__SHIFT 0x00000018 - -// CPC_SRDebugBus_23_0 -#define CPC_SRDebugBus_23_0__SRSaveSmDebugBus__SHIFT 0x00000000 -#define CPC_SRDebugBus_23_0__SRSaveTciuDebugBus_14_0__SHIFT 0x00000009 -#define CPC_SRDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPC_SRDebugBus_47_24 -#define CPC_SRDebugBus_47_24__SRSaveTciuDebugBus_20_15__SHIFT 0x00000000 -#define CPC_SRDebugBus_47_24__SRSaveIntrptDebugBus_17_0__SHIFT 0x00000006 -#define CPC_SRDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPC_SRDebugBus_71_48 -#define CPC_SRDebugBus_71_48__SRSaveIntrptDebugBus_27_18__SHIFT 0x00000000 -#define CPC_SRDebugBus_71_48__crawler0_data_5_0__SHIFT 0x0000000a -#define CPC_SRDebugBus_71_48__crawler1_data_5_0__SHIFT 0x00000010 -#define CPC_SRDebugBus_71_48__crawler2_data_1_0__SHIFT 0x00000016 -#define CPC_SRDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPC_SRDebugBus_95_72 -#define CPC_SRDebugBus_95_72__crawler2_data_5_2__SHIFT 0x00000000 -#define CPC_SRDebugBus_95_72__crawler3_data_5_0__SHIFT 0x00000004 -#define CPC_SRDebugBus_95_72__Reserved0__SHIFT 0x0000000a - -// CPC_SRDebugBus_119_96 -#define CPC_SRDebugBus_119_96__Reserved0__SHIFT 0x00000000 - -// CPC_QueryUnitDebugBus_23_0 -#define CPC_QueryUnitDebugBus_23_0__RegisterClkValid__SHIFT 0x00000000 -#define CPC_QueryUnitDebugBus_23_0__Reserved1__SHIFT 0x00000002 -#define CPC_QueryUnitDebugBus_23_0__qCsinvocWrError__SHIFT 0x00000004 -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoEmpty__SHIFT 0x00000005 -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoFull__SHIFT 0x00000006 -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoRdEn__SHIFT 0x00000007 -#define CPC_QueryUnitDebugBus_23_0__QueryWrFifoWrEn__SHIFT 0x00000008 -#define CPC_QueryUnitDebugBus_23_0__qQueryState__SHIFT 0x00000009 -#define CPC_QueryUnitDebugBus_23_0__CsinvocWrErrorThread_0__SHIFT 0x0000000c -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoEmpty_0__SHIFT 0x0000000d -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoFull_0__SHIFT 0x0000000e -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoRdEn_0__SHIFT 0x0000000f -#define CPC_QueryUnitDebugBus_23_0__CsinvocFifoWrEn_0__SHIFT 0x00000010 -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoEmpty_0__SHIFT 0x00000011 -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoFull_0__SHIFT 0x00000012 -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoRdEn_0__SHIFT 0x00000013 -#define CPC_QueryUnitDebugBus_23_0__PipeStatsFifoWrEn_0__SHIFT 0x00000014 -#define CPC_QueryUnitDebugBus_23_0__PipeOutstandingTagCnt0_neq_0__SHIFT 0x00000015 -#define CPC_QueryUnitDebugBus_23_0__PipeStatsBusyThread_0__SHIFT 0x00000016 -#define CPC_QueryUnitDebugBus_23_0__PipeStatsPendFlagThread_0__SHIFT 0x00000017 -#define CPC_QueryUnitDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPC_QueryUnitDebugBus_47_24 -#define CPC_QueryUnitDebugBus_47_24__CsinvocWrErrorThread_1__SHIFT 0x00000000 -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoEmpty_1__SHIFT 0x00000001 -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoFull_1__SHIFT 0x00000002 -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoRdEn_1__SHIFT 0x00000003 -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoWrEn_1__SHIFT 0x00000004 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoEmpty_1__SHIFT 0x00000005 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoFull_1__SHIFT 0x00000006 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoRdEn_1__SHIFT 0x00000007 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoWrEn_1__SHIFT 0x00000008 -#define CPC_QueryUnitDebugBus_47_24__PipeOutstandingTagCnt1_neq_0__SHIFT 0x00000009 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsBusyThread_1__SHIFT 0x0000000a -#define CPC_QueryUnitDebugBus_47_24__PipeStatsPendFlagThread_1__SHIFT 0x0000000b -#define CPC_QueryUnitDebugBus_47_24__CsinvocWrErrorThread_2__SHIFT 0x0000000c -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoEmpty_2__SHIFT 0x0000000d -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoFull_2__SHIFT 0x0000000e -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoRdEn_2__SHIFT 0x0000000f -#define CPC_QueryUnitDebugBus_47_24__CsinvocFifoWrEn_2__SHIFT 0x00000010 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoEmpty_2__SHIFT 0x00000011 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoFull_2__SHIFT 0x00000012 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoRdEn_2__SHIFT 0x00000013 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsFifoWrEn_2__SHIFT 0x00000014 -#define CPC_QueryUnitDebugBus_47_24__PipeOutstandingTagCnt2_neq_0__SHIFT 0x00000015 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsBusyThread_2__SHIFT 0x00000016 -#define CPC_QueryUnitDebugBus_47_24__PipeStatsPendFlagThread_2__SHIFT 0x00000017 -#define CPC_QueryUnitDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPC_QueryUnitDebugBus_71_48 -#define CPC_QueryUnitDebugBus_71_48__CsinvocWrErrorThread_3__SHIFT 0x00000000 -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoEmpty_3__SHIFT 0x00000001 -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoFull_3__SHIFT 0x00000002 -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoRdEn_3__SHIFT 0x00000003 -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoWrEn_3__SHIFT 0x00000004 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoEmpty_3__SHIFT 0x00000005 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoFull_3__SHIFT 0x00000006 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoRdEn_3__SHIFT 0x00000007 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoWrEn_3__SHIFT 0x00000008 -#define CPC_QueryUnitDebugBus_71_48__PipeOutstandingTagCnt3_neq_0__SHIFT 0x00000009 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsBusyThread_3__SHIFT 0x0000000a -#define CPC_QueryUnitDebugBus_71_48__PipeStatsPendFlagThread_3__SHIFT 0x0000000b -#define CPC_QueryUnitDebugBus_71_48__CsinvocWrErrorThread_4__SHIFT 0x0000000c -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoEmpty_4__SHIFT 0x0000000d -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoFull_4__SHIFT 0x0000000e -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoRdEn_4__SHIFT 0x0000000f -#define CPC_QueryUnitDebugBus_71_48__CsinvocFifoWrEn_4__SHIFT 0x00000010 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoEmpty_4__SHIFT 0x00000011 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoFull_4__SHIFT 0x00000012 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoRdEn_4__SHIFT 0x00000013 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsFifoWrEn_4__SHIFT 0x00000014 -#define CPC_QueryUnitDebugBus_71_48__PipeOutstandingTagCnt4_neq_0__SHIFT 0x00000015 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsBusyThread_4__SHIFT 0x00000016 -#define CPC_QueryUnitDebugBus_71_48__PipeStatsPendFlagThread_4__SHIFT 0x00000017 -#define CPC_QueryUnitDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPC_QueryUnitDebugBus_95_72 -#define CPC_QueryUnitDebugBus_95_72__CsinvocWrErrorThread_5__SHIFT 0x00000000 -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoEmpty_5__SHIFT 0x00000001 -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoFull_5__SHIFT 0x00000002 -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoRdEn_5__SHIFT 0x00000003 -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoWrEn_5__SHIFT 0x00000004 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoEmpty_5__SHIFT 0x00000005 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoFull_5__SHIFT 0x00000006 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoRdEn_5__SHIFT 0x00000007 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoWrEn_5__SHIFT 0x00000008 -#define CPC_QueryUnitDebugBus_95_72__PipeOutstandingTagCnt5_neq_0__SHIFT 0x00000009 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsBusyThread_5__SHIFT 0x0000000a -#define CPC_QueryUnitDebugBus_95_72__PipeStatsPendFlagThread_5__SHIFT 0x0000000b -#define CPC_QueryUnitDebugBus_95_72__CsinvocWrErrorThread_6__SHIFT 0x0000000c -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoEmpty_6__SHIFT 0x0000000d -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoFull_6__SHIFT 0x0000000e -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoRdEn_6__SHIFT 0x0000000f -#define CPC_QueryUnitDebugBus_95_72__CsinvocFifoWrEn_6__SHIFT 0x00000010 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoEmpty_6__SHIFT 0x00000011 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoFull_6__SHIFT 0x00000012 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoRdEn_6__SHIFT 0x00000013 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsFifoWrEn_6__SHIFT 0x00000014 -#define CPC_QueryUnitDebugBus_95_72__PipeOutstandingTagCnt6_neq_0__SHIFT 0x00000015 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsBusyThread_6__SHIFT 0x00000016 -#define CPC_QueryUnitDebugBus_95_72__PipeStatsPendFlagThread_6__SHIFT 0x00000017 -#define CPC_QueryUnitDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPC_QueryUnitDebugBus_119_96 -#define CPC_QueryUnitDebugBus_119_96__CsinvocWrErrorThread_7__SHIFT 0x00000000 -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoEmpty_7__SHIFT 0x00000001 -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoFull_7__SHIFT 0x00000002 -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoRdEn_7__SHIFT 0x00000003 -#define CPC_QueryUnitDebugBus_119_96__CsinvocFifoWrEn_7__SHIFT 0x00000004 -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoEmpty_7__SHIFT 0x00000005 -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoFull_7__SHIFT 0x00000006 -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoRdEn_7__SHIFT 0x00000007 -#define CPC_QueryUnitDebugBus_119_96__PipeStatsFifoWrEn_7__SHIFT 0x00000008 -#define CPC_QueryUnitDebugBus_119_96__PipeOutstandingTagCnt7_neq_0__SHIFT 0x00000009 -#define CPC_QueryUnitDebugBus_119_96__PipeStatsBusyThread_7__SHIFT 0x0000000a -#define CPC_QueryUnitDebugBus_119_96__PipeStatsPendFlagThread_7__SHIFT 0x0000000b -#define CPC_QueryUnitDebugBus_119_96__Reserved0__SHIFT 0x0000000c - -// CPC_QueryUnitDebugBus_127_120 -#define CPC_QueryUnitDebugBus_127_120__Reserved0__SHIFT 0x00000000 - -// CPC_MecScratchDebugBus_7_0 -#define CPC_MecScratchDebugBus_7_0__qWrArbState__SHIFT 0x00000000 -#define CPC_MecScratchDebugBus_7_0__qRdClientSelect__SHIFT 0x00000001 -#define CPC_MecScratchDebugBus_7_0__qMec2ReadState__SHIFT 0x00000002 -#define CPC_MecScratchDebugBus_7_0__qMec1ReadState__SHIFT 0x00000004 -#define CPC_MecScratchDebugBus_7_0__qRegReadState__SHIFT 0x00000006 -#define CPC_MecScratchDebugBus_7_0__Reserved0__SHIFT 0x00000008 - -// CPC_RbiuDebugBus_11_0 -#define CPC_RbiuDebugBus_11_0__qGRBM_CPC_reg_send__SHIFT 0x00000000 -#define CPC_RbiuDebugBus_11_0__qReadState__SHIFT 0x00000001 -#define CPC_RbiuDebugBus_11_0__qReadCycleCount__SHIFT 0x00000002 -#define CPC_RbiuDebugBus_11_0__Reserved0__SHIFT 0x00000005 - -// CPC_RciuDebugBus_23_0 -#define CPC_RciuDebugBus_23_0__qCpcGrbmSendArb__SHIFT 0x00000000 -#define CPC_RciuDebugBus_23_0__qCpcGrbmPipeSend__SHIFT 0x00000003 -#define CPC_RciuDebugBus_23_0__OR_qMec1SendCntUnderflow__SHIFT 0x00000004 -#define CPC_RciuDebugBus_23_0__OR_qMec1SendCntOverflow__SHIFT 0x00000005 -#define CPC_RciuDebugBus_23_0__OR_qMec2SendCntUnderflow__SHIFT 0x00000006 -#define CPC_RciuDebugBus_23_0__OR_qMec2SendCntOverflow__SHIFT 0x00000007 -#define CPC_RciuDebugBus_23_0__qGrbmCpReadValid__SHIFT 0x00000008 -#define CPC_RciuDebugBus_23_0__qGrbmCpReadPipeId__SHIFT 0x00000009 -#define CPC_RciuDebugBus_23_0__qGrbmCpReadMeId__SHIFT 0x0000000b -#define CPC_RciuDebugBus_23_0__Mec1RciuFifoFull_3_0__SHIFT 0x0000000d -#define CPC_RciuDebugBus_23_0__Mec1RciuFifoEmpty_3_0__SHIFT 0x00000011 -#define CPC_RciuDebugBus_23_0__qMec1GrbmSendCnt0_neq_qMec1SendCntMax0__SHIFT 0x00000015 -#define CPC_RciuDebugBus_23_0__qMec1GrbmSendCnt1_neq_qMec1SendCntMax1__SHIFT 0x00000016 -#define CPC_RciuDebugBus_23_0__qMec1GrbmSendCnt2_neq_qMec1SendCntMax2__SHIFT 0x00000017 -#define CPC_RciuDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPC_RciuDebugBus_47_24 -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt3_neq_qMec1SendCntMax3__SHIFT 0x00000000 -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt0_eq_0__SHIFT 0x00000001 -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt1_eq_0__SHIFT 0x00000002 -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt2_eq_0__SHIFT 0x00000003 -#define CPC_RciuDebugBus_47_24__qMec1GrbmSendCnt3_eq_0__SHIFT 0x00000004 -#define CPC_RciuDebugBus_47_24__qMec1GrbmFree_3_0__SHIFT 0x00000005 -#define CPC_RciuDebugBus_47_24__Mec1RciuRdReqFifoEmpty_3_0__SHIFT 0x00000009 -#define CPC_RciuDebugBus_47_24__Mec1RciuRdReqFifoFull_3_0__SHIFT 0x0000000d -#define CPC_RciuDebugBus_47_24__Mec2RciuFifoFull_3_0__SHIFT 0x00000011 -#define CPC_RciuDebugBus_47_24__Mec2RciuFifoEmpty_2_0__SHIFT 0x00000015 -#define CPC_RciuDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPC_RciuDebugBus_69_48 -#define CPC_RciuDebugBus_69_48__Mec2RciuFifoEmpty_3__SHIFT 0x00000000 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt0_neq_qMec2SendCntMax0__SHIFT 0x00000001 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt1_neq_qMec2SendCntMax1__SHIFT 0x00000002 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt2_neq_qMec2SendCntMax2__SHIFT 0x00000003 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt3_neq_qMec2SendCntMax3__SHIFT 0x00000004 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt0_eq_0__SHIFT 0x00000005 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt1_eq_0__SHIFT 0x00000006 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt2_eq_0__SHIFT 0x00000007 -#define CPC_RciuDebugBus_69_48__qMec2GrbmSendCnt3_eq_0__SHIFT 0x00000008 -#define CPC_RciuDebugBus_69_48__qMec2GrbmFree_3_0__SHIFT 0x00000009 -#define CPC_RciuDebugBus_69_48__Mec2RciuRdReqFifoEmpty_3_0__SHIFT 0x0000000d -#define CPC_RciuDebugBus_69_48__Mec2RciuRdReqFifoFull_3_0__SHIFT 0x00000011 -#define CPC_RciuDebugBus_69_48__Reserved0__SHIFT 0x00000015 - -// CPC_CpcRoqDebugBus_23_0 -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendPq_3_0__SHIFT 0x00000000 -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendIb_3_0__SHIFT 0x00000004 -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendIq_3_0__SHIFT 0x00000008 -#define CPC_CpcRoqDebugBus_23_0__Mec1_qRoQueueSendEop_3_0__SHIFT 0x0000000c -#define CPC_CpcRoqDebugBus_23_0__Mec1_Pq_QueueFifoEmpty_3_0__SHIFT 0x00000010 -#define CPC_CpcRoqDebugBus_23_0__Mec1_Pq_QueueFifoFull_3_0__SHIFT 0x00000014 -#define CPC_CpcRoqDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPC_CpcRoqDebugBus_47_24 -#define CPC_CpcRoqDebugBus_47_24__Mec1_Ib_QueueFifoEmpty_3_0__SHIFT 0x00000000 -#define CPC_CpcRoqDebugBus_47_24__Mec1_Ib_QueueFifoFull_3_0__SHIFT 0x00000004 -#define CPC_CpcRoqDebugBus_47_24__Mec1_Iq_QueueFifoEmpty_3_0__SHIFT 0x00000008 -#define CPC_CpcRoqDebugBus_47_24__Mec1_Iq_QueueFifoFull_3_0__SHIFT 0x0000000c -#define CPC_CpcRoqDebugBus_47_24__Mec1_Eop_QueueFifoEmpty_3_0__SHIFT 0x00000010 -#define CPC_CpcRoqDebugBus_47_24__Mec1_Eop_QueueFifoFull_3_0__SHIFT 0x00000014 -#define CPC_CpcRoqDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPC_CpcRoqDebugBus_71_48 -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendPq_3_0__SHIFT 0x00000000 -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendIb_3_0__SHIFT 0x00000004 -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendIq_3_0__SHIFT 0x00000008 -#define CPC_CpcRoqDebugBus_71_48__Mec2_qRoQueueSendEop_3_0__SHIFT 0x0000000c -#define CPC_CpcRoqDebugBus_71_48__Mec2_Pq_QueueFifoEmpty_3_0__SHIFT 0x00000010 -#define CPC_CpcRoqDebugBus_71_48__Mec2_Pq_QueueFifoFull_3_0__SHIFT 0x00000014 -#define CPC_CpcRoqDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPC_CpcRoqDebugBus_95_72 -#define CPC_CpcRoqDebugBus_95_72__Mec2_Ib_QueueFifoEmpty_3_0__SHIFT 0x00000000 -#define CPC_CpcRoqDebugBus_95_72__Mec2_Ib_QueueFifoFull_3_0__SHIFT 0x00000004 -#define CPC_CpcRoqDebugBus_95_72__Mec2_Iq_QueueFifoEmpty_3_0__SHIFT 0x00000008 -#define CPC_CpcRoqDebugBus_95_72__Mec2_Iq_QueueFifoFull_3_0__SHIFT 0x0000000c -#define CPC_CpcRoqDebugBus_95_72__Mec2_Eop_QueueFifoEmpty_3_0__SHIFT 0x00000010 -#define CPC_CpcRoqDebugBus_95_72__Mec2_Eop_QueueFifoFull_3_0__SHIFT 0x00000014 -#define CPC_CpcRoqDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPC_TciuDebugBus_12_0 -#define CPC_TciuDebugBus_12_0__qTcSender__SHIFT 0x00000000 -#define CPC_TciuDebugBus_12_0__TcRequestFifoEmpty__SHIFT 0x00000004 -#define CPC_TciuDebugBus_12_0__TcRequestFifoFull__SHIFT 0x00000005 -#define CPC_TciuDebugBus_12_0__qCPC_CPG_tcreq_send__SHIFT 0x00000006 -#define CPC_TciuDebugBus_12_0__qCPC_CPG_tcreq_free__SHIFT 0x00000007 -#define CPC_TciuDebugBus_12_0__qCpcCpgSendCount_eq_0x8__SHIFT 0x00000008 -#define CPC_TciuDebugBus_12_0__qCpcCpgSendCount_eq_0__SHIFT 0x00000009 -#define CPC_TciuDebugBus_12_0__qTcReqCntUnderFlow__SHIFT 0x0000000a -#define CPC_TciuDebugBus_12_0__qTcReqCntOverFlow__SHIFT 0x0000000b -#define CPC_TciuDebugBus_12_0__qCPG_CPC_tcret_vld__SHIFT 0x0000000c -#define CPC_TciuDebugBus_12_0__Reserved0__SHIFT 0x0000000d - -// CPC_Dynamic_and_Register_Clk_Valid -#define CPC_Dynamic_and_Register_Clk_Valid__RegisterClkValid__SHIFT 0x00000000 -#define CPC_Dynamic_and_Register_Clk_Valid__DynamicClkValid__SHIFT 0x00000001 -#define CPC_Dynamic_and_Register_Clk_Valid__Reserved0__SHIFT 0x00000002 - -// CPC_MecParserDebugBus_23_0 -#define CPC_MecParserDebugBus_23_0__qEnableDiscardType2__SHIFT 0x00000000 -#define CPC_MecParserDebugBus_23_0__MecMsgFifoEmpty__SHIFT 0x00000001 -#define CPC_MecParserDebugBus_23_0__MecMsgFifoFull__SHIFT 0x00000002 -#define CPC_MecParserDebugBus_23_0__QueueManagerQueueId__SHIFT 0x00000003 -#define CPC_MecParserDebugBus_23_0__QueueManagerMessage__SHIFT 0x00000006 -#define CPC_MecParserDebugBus_23_0__QueManagerFifoEmpty__SHIFT 0x0000000e -#define CPC_MecParserDebugBus_23_0__qBlockSwitch__SHIFT 0x0000000f -#define CPC_MecParserDebugBus_23_0__qMessageDwordRts__SHIFT 0x00000012 -#define CPC_MecParserDebugBus_23_0__qEopQueueDwordRts__SHIFT 0x00000013 -#define CPC_MecParserDebugBus_23_0__qIqQueueDwordRts__SHIFT 0x00000014 -#define CPC_MecParserDebugBus_23_0__qPcktCntPqEq0__SHIFT 0x00000015 -#define CPC_MecParserDebugBus_23_0__qPcktCntIbEq0__SHIFT 0x00000016 -#define CPC_MecParserDebugBus_23_0__qPcktCntIqEq0__SHIFT 0x00000017 -#define CPC_MecParserDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPC_MecParserDebugBus_47_24 -#define CPC_MecParserDebugBus_47_24__qPcktCntEopEq0__SHIFT 0x00000000 -#define CPC_MecParserDebugBus_47_24__qPcktCntEq0__SHIFT 0x00000001 -#define CPC_MecParserDebugBus_47_24__qReservedBitClean__SHIFT 0x00000002 -#define CPC_MecParserDebugBus_47_24__qReservedBitDirty__SHIFT 0x00000003 -#define CPC_MecParserDebugBus_47_24__qIndrBufCntNeq0__SHIFT 0x00000004 -#define CPC_MecParserDebugBus_47_24__qIbEndState__SHIFT 0x00000005 -#define CPC_MecParserDebugBus_47_24__IqSizeFifoEmpty__SHIFT 0x00000007 -#define CPC_MecParserDebugBus_47_24__IqSizeFifoFull__SHIFT 0x00000008 -#define CPC_MecParserDebugBus_47_24__qIqBufCntNeq0__SHIFT 0x00000009 -#define CPC_MecParserDebugBus_47_24__qIqQueueId__SHIFT 0x0000000a -#define CPC_MecParserDebugBus_47_24__qIqEndState__SHIFT 0x0000000d -#define CPC_MecParserDebugBus_47_24__qPrgmStrmSelect__SHIFT 0x0000000f -#define CPC_MecParserDebugBus_47_24__qEopReturnStream_3_0__SHIFT 0x00000012 -#define CPC_MecParserDebugBus_47_24__qIqReturnStream_1_0__SHIFT 0x00000016 -#define CPC_MecParserDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPC_MecParserDebugBus_71_48 -#define CPC_MecParserDebugBus_71_48__qIqReturnStream_3_2__SHIFT 0x00000000 -#define CPC_MecParserDebugBus_71_48__qRegBusSelect__SHIFT 0x00000002 -#define CPC_MecParserDebugBus_71_48__qMecVqid__SHIFT 0x00000006 -#define CPC_MecParserDebugBus_71_48__qMecVqEn__SHIFT 0x00000010 -#define CPC_MecParserDebugBus_71_48__qMecSrcVm__SHIFT 0x00000011 -#define CPC_MecParserDebugBus_71_48__MecDcFifoEmpty__SHIFT 0x00000013 -#define CPC_MecParserDebugBus_71_48__MecDcFifoFull__SHIFT 0x00000014 -#define CPC_MecParserDebugBus_71_48__oMecHqdWrRts__SHIFT 0x00000015 -#define CPC_MecParserDebugBus_71_48__MecRciuFifoEmpty__SHIFT 0x00000016 -#define CPC_MecParserDebugBus_71_48__MecRciuFifoFull__SHIFT 0x00000017 -#define CPC_MecParserDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPC_MecParserDebugBus_95_72 -#define CPC_MecParserDebugBus_95_72__qUpdateWrAddr__SHIFT 0x00000000 -#define CPC_MecParserDebugBus_95_72__qMecWrOneAddr__SHIFT 0x00000001 -#define CPC_MecParserDebugBus_95_72__Reserved2__SHIFT 0x00000002 -#define CPC_MecParserDebugBus_95_72__qPrivilegedStatePq__SHIFT 0x00000004 -#define CPC_MecParserDebugBus_95_72__qQueueId__SHIFT 0x00000005 -#define CPC_MecParserDebugBus_95_72__qBlockCsmdRdPntrUpdate__SHIFT 0x00000008 -#define CPC_MecParserDebugBus_95_72__qBlockCsmdRdPntrRead__SHIFT 0x00000009 -#define CPC_MecParserDebugBus_95_72__qIbDrainCount_neq_0__SHIFT 0x0000000a -#define CPC_MecParserDebugBus_95_72__qPqDrainCount_neq_0__SHIFT 0x0000000b -#define CPC_MecParserDebugBus_95_72__oMecDcDiscardReq__SHIFT 0x0000000c -#define CPC_MecParserDebugBus_95_72__oMecDcHaltReq__SHIFT 0x0000000d -#define CPC_MecParserDebugBus_95_72__qPendingEopqWpFlag_Dse0__SHIFT 0x0000000e -#define CPC_MecParserDebugBus_95_72__oEopqWrPntrRts__SHIFT 0x0000000f -#define CPC_MecParserDebugBus_95_72__Reserved1__SHIFT 0x00000010 -#define CPC_MecParserDebugBus_95_72__qMecDmaPendingQueue__SHIFT 0x00000011 -#define CPC_MecParserDebugBus_95_72__qMecDmaPendingFlag__SHIFT 0x00000014 -#define CPC_MecParserDebugBus_95_72__PartialFlushPendingQ0__SHIFT 0x00000015 -#define CPC_MecParserDebugBus_95_72__oDoorbellRts__SHIFT 0x00000016 -#define CPC_MecParserDebugBus_95_72__CpTcTxActionDebugBus_0__SHIFT 0x00000017 -#define CPC_MecParserDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPC_MecParserDebugBus_119_96 -#define CPC_MecParserDebugBus_119_96__CpTcTxActionDebugBus_3_1__SHIFT 0x00000000 -#define CPC_MecParserDebugBus_119_96__Reserved0__SHIFT 0x00000003 - -// CPC_F32MecDebugBus_23_0 -#define CPC_F32MecDebugBus_23_0__LdStrBufferData_23_0__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_47_24 -#define CPC_F32MecDebugBus_47_24__LdStrBufferData_47_24__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_71_48 -#define CPC_F32MecDebugBus_71_48__LdStrBufferData_63_48__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_71_48__LdStrBufferAddress_7_0__SHIFT 0x00000010 -#define CPC_F32MecDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_95_72 -#define CPC_F32MecDebugBus_95_72__LdStrBufferAddress_31_8__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_119_96 -#define CPC_F32MecDebugBus_119_96__LdStrBufferAddress_47_32__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_119_96__LdStrBufferInstrOp__SHIFT 0x00000010 -#define CPC_F32MecDebugBus_119_96__LdStrInstrSel__SHIFT 0x00000011 -#define CPC_F32MecDebugBus_119_96__LdStrMemSpace__SHIFT 0x00000013 -#define CPC_F32MecDebugBus_119_96__qLoadStoreBusy__SHIFT 0x00000015 -#define CPC_F32MecDebugBus_119_96__Reserved1__SHIFT 0x00000016 -#define CPC_F32MecDebugBus_119_96__qLoadState_B_0__SHIFT 0x00000017 -#define CPC_F32MecDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_143_120 -#define CPC_F32MecDebugBus_143_120__qLoadState_B_1__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_143_120__qLoadState_A__SHIFT 0x00000001 -#define CPC_F32MecDebugBus_143_120__LdStrBufferEmpty__SHIFT 0x00000003 -#define CPC_F32MecDebugBus_143_120__LdStrBufferFull__SHIFT 0x00000004 -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc2Valid_B__SHIFT 0x00000005 -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc1Valid_B__SHIFT 0x00000006 -#define CPC_F32MecDebugBus_143_120__qInstrMeValid_B__SHIFT 0x00000007 -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc2Valid_A__SHIFT 0x00000008 -#define CPC_F32MecDebugBus_143_120__qInstrMeSrc1Valid_A__SHIFT 0x00000009 -#define CPC_F32MecDebugBus_143_120__qInstrMeValid_A__SHIFT 0x0000000a -#define CPC_F32MecDebugBus_143_120__Reserved0__SHIFT 0x0000000b - -// CPC_F32MecDebugBus_167_144 -#define CPC_F32MecDebugBus_167_144__Reserved1__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_167_144__qLoadArbState__SHIFT 0x00000010 -#define CPC_F32MecDebugBus_167_144__qStoreArbState__SHIFT 0x00000012 -#define CPC_F32MecDebugBus_167_144__Reserved0__SHIFT 0x00000014 - -// CPC_F32MecDebugBus_191_168 -#define CPC_F32MecDebugBus_191_168__Reserved0__SHIFT 0x00000000 - -// CPC_F32MecDebugBus_215_192 -#define CPC_F32MecDebugBus_215_192__qAluArbState_B__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_215_192__qAluArbState_A__SHIFT 0x00000002 -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B__SHIFT 0x00000004 -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B__SHIFT 0x00000005 -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExValid_B__SHIFT 0x00000006 -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A__SHIFT 0x00000007 -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A__SHIFT 0x00000008 -#define CPC_F32MecDebugBus_215_192__DebugBusO_qInstrExValid_A__SHIFT 0x00000009 -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B__SHIFT 0x0000000a -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B__SHIFT 0x0000000b -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExValid_B__SHIFT 0x0000000c -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A__SHIFT 0x0000000d -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A__SHIFT 0x0000000e -#define CPC_F32MecDebugBus_215_192__DebugBus1_qInstrExValid_A__SHIFT 0x0000000f -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B__SHIFT 0x00000010 -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B__SHIFT 0x00000011 -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExValid_B__SHIFT 0x00000012 -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A__SHIFT 0x00000013 -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A__SHIFT 0x00000014 -#define CPC_F32MecDebugBus_215_192__DebugBus2_qInstrExValid_A__SHIFT 0x00000015 -#define CPC_F32MecDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B__SHIFT 0x00000016 -#define CPC_F32MecDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B__SHIFT 0x00000017 -#define CPC_F32MecDebugBus_215_192__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_239_216 -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExValid_B__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A__SHIFT 0x00000001 -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A__SHIFT 0x00000002 -#define CPC_F32MecDebugBus_239_216__DebugBus3_qInstrExValid_A__SHIFT 0x00000003 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid15__SHIFT 0x00000004 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid14__SHIFT 0x00000005 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid13__SHIFT 0x00000006 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid12__SHIFT 0x00000007 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid11__SHIFT 0x00000008 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid10__SHIFT 0x00000009 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid9__SHIFT 0x0000000a -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid8__SHIFT 0x0000000b -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid7__SHIFT 0x0000000c -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid6__SHIFT 0x0000000d -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid5__SHIFT 0x0000000e -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid4__SHIFT 0x0000000f -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid3__SHIFT 0x00000010 -#define CPC_F32MecDebugBus_239_216__DebugBus0_qGprValid2__SHIFT 0x00000011 -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid15__SHIFT 0x00000012 -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid14__SHIFT 0x00000013 -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid13__SHIFT 0x00000014 -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid12__SHIFT 0x00000015 -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid11__SHIFT 0x00000016 -#define CPC_F32MecDebugBus_239_216__DebugBus1_qGprValid10__SHIFT 0x00000017 -#define CPC_F32MecDebugBus_239_216__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_263_240 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid9__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid8__SHIFT 0x00000001 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid7__SHIFT 0x00000002 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid6__SHIFT 0x00000003 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid5__SHIFT 0x00000004 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid4__SHIFT 0x00000005 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid3__SHIFT 0x00000006 -#define CPC_F32MecDebugBus_263_240__DebugBus1_qGprValid2__SHIFT 0x00000007 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid15__SHIFT 0x00000008 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid14__SHIFT 0x00000009 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid13__SHIFT 0x0000000a -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid12__SHIFT 0x0000000b -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid11__SHIFT 0x0000000c -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid10__SHIFT 0x0000000d -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid9__SHIFT 0x0000000e -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid8__SHIFT 0x0000000f -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid7__SHIFT 0x00000010 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid6__SHIFT 0x00000011 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid5__SHIFT 0x00000012 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid4__SHIFT 0x00000013 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid3__SHIFT 0x00000014 -#define CPC_F32MecDebugBus_263_240__DebugBus2_qGprValid2__SHIFT 0x00000015 -#define CPC_F32MecDebugBus_263_240__DebugBus3_qGprValid15__SHIFT 0x00000016 -#define CPC_F32MecDebugBus_263_240__DebugBus3_qGprValid14__SHIFT 0x00000017 -#define CPC_F32MecDebugBus_263_240__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_287_264 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid13__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid12__SHIFT 0x00000001 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid11__SHIFT 0x00000002 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid10__SHIFT 0x00000003 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid9__SHIFT 0x00000004 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid8__SHIFT 0x00000005 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid7__SHIFT 0x00000006 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid6__SHIFT 0x00000007 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid5__SHIFT 0x00000008 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid4__SHIFT 0x00000009 -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid3__SHIFT 0x0000000a -#define CPC_F32MecDebugBus_287_264__DebugBus3_qGprValid2__SHIFT 0x0000000b -#define CPC_F32MecDebugBus_287_264__qDecodeInstr_A_11_0__SHIFT 0x0000000c -#define CPC_F32MecDebugBus_287_264__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_311_288 -#define CPC_F32MecDebugBus_311_288__qDecodeInstr_A_31_12__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_311_288__qDecodeInstr_B_3_0__SHIFT 0x00000014 -#define CPC_F32MecDebugBus_311_288__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_335_312 -#define CPC_F32MecDebugBus_335_312__qDecodeInstr_B_27_4__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_335_312__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_359_336 -#define CPC_F32MecDebugBus_359_336__qDecodeInstr_B_31_28__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_359_336__qDecodeAddress_A_padded__SHIFT 0x00000004 -#define CPC_F32MecDebugBus_359_336__qDecodeAddress_B_padded_3_0__SHIFT 0x00000014 -#define CPC_F32MecDebugBus_359_336__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_383_360 -#define CPC_F32MecDebugBus_383_360__qDecodeAddress_B_padded_15_4__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_383_360__qAluIntUnitPntr_A__SHIFT 0x0000000c -#define CPC_F32MecDebugBus_383_360__AluIntUnitPntr_B__SHIFT 0x0000000f -#define CPC_F32MecDebugBus_383_360__qLdStrUnitPntr_A__SHIFT 0x00000012 -#define CPC_F32MecDebugBus_383_360__qLdStrUnitPntr_B__SHIFT 0x00000015 -#define CPC_F32MecDebugBus_383_360__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_407_384 -#define CPC_F32MecDebugBus_407_384__qDecodeInstrRts_A__SHIFT 0x00000000 -#define CPC_F32MecDebugBus_407_384__qDecodeInstrRts_B__SHIFT 0x00000001 -#define CPC_F32MecDebugBus_407_384__qJumpSourceRts__SHIFT 0x00000002 -#define CPC_F32MecDebugBus_407_384__qInstrEtsCnt_le_6__SHIFT 0x00000003 -#define CPC_F32MecDebugBus_407_384__Reserved1__SHIFT 0x00000004 -#define CPC_F32MecDebugBus_407_384__qThreadIdState__SHIFT 0x00000014 -#define CPC_F32MecDebugBus_407_384__Reserved0__SHIFT 0x00000018 - -// CPC_F32MecDebugBus_431_408 -#define CPC_F32MecDebugBus_431_408__Reserved0__SHIFT 0x00000000 - -// CPC_F32MecDebugBus_447_432 -#define CPC_F32MecDebugBus_447_432__Reserved0__SHIFT 0x00000000 - -// CPC_UtcL2iuDebugIntf_23_0 -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_tag__SHIFT 0x00000000 -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_nack__SHIFT 0x00000007 -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_mtype__SHIFT 0x00000009 -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_memlog__SHIFT 0x0000000b -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_no_pte__SHIFT 0x0000000c -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_pte_tmz__SHIFT 0x0000000d -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_spa__SHIFT 0x0000000e -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_io_steer__SHIFT 0x0000000f -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_fragment_size_5_0__SHIFT 0x00000010 -#define CPC_UtcL2iuDebugIntf_23_0__iUTCL2_CPC_ret_perms_granted_1_0__SHIFT 0x00000016 -#define CPC_UtcL2iuDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPC_UtcL2iuDebugIntf_47_24 -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_perms_granted_2__SHIFT 0x00000000 -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_perms_requested_2_0__SHIFT 0x00000001 -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_snoop__SHIFT 0x00000004 -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_valid__SHIFT 0x00000005 -#define CPC_UtcL2iuDebugIntf_47_24__iUTCL2_CPC_ret_perms_requested_17_0__SHIFT 0x00000006 -#define CPC_UtcL2iuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPC_UtcL2iuDebugIntf_71_48 -#define CPC_UtcL2iuDebugIntf_71_48__iUTCL2_CPC_ret_perms_requested_35_18__SHIFT 0x00000000 -#define CPC_UtcL2iuDebugIntf_71_48__CPC_UTCL2_req_data_5_0__SHIFT 0x00000012 -#define CPC_UtcL2iuDebugIntf_71_48__Reserved0__SHIFT 0x00000018 - -// CPC_UtcL2iuDebugIntf_95_72 -#define CPC_UtcL2iuDebugIntf_95_72__CPC_UTCL2_req_data_15_6__SHIFT 0x00000000 -#define CPC_UtcL2iuDebugIntf_95_72__qCPC_UTCL2_req_free__SHIFT 0x0000000a -#define CPC_UtcL2iuDebugIntf_95_72__CPC_UTCL2_req_send__SHIFT 0x0000000b -#define CPC_UtcL2iuDebugIntf_95_72__qUtcL2XferCycle_eq_0__SHIFT 0x0000000c -#define CPC_UtcL2iuDebugIntf_95_72__Reserved0__SHIFT 0x0000000d - -// CPG_RbiuDebugIntf_23_0 -#define CPG_RbiuDebugIntf_23_0__GRBM_CP_reg_free__SHIFT 0x00000000 -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_send__SHIFT 0x00000001 -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_clken__SHIFT 0x00000002 -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_priv__SHIFT 0x00000003 -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_op__SHIFT 0x00000004 -#define CPG_RbiuDebugIntf_23_0__RdReturnValid__SHIFT 0x00000005 -#define CPG_RbiuDebugIntf_23_0__iGRBM_CP_reg_addr__SHIFT 0x00000006 -#define CPG_RbiuDebugIntf_23_0__Reserved0__SHIFT 0x00000016 - -// CPG_RbiuDebugIntf_47_24 -#define CPG_RbiuDebugIntf_47_24__iGRBM_CP_reg_data_11_0__SHIFT 0x00000000 -#define CPG_RbiuDebugIntf_47_24__RdReturnData_11_0__SHIFT 0x0000000c -#define CPG_RbiuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_RciuDebugIntf_23_0 -#define CPG_RciuDebugIntf_23_0__GRBM_CP_reg_free__SHIFT 0x00000000 -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_send__SHIFT 0x00000001 -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_clken__SHIFT 0x00000002 -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_priv__SHIFT 0x00000003 -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_op__SHIFT 0x00000004 -#define CPG_RciuDebugIntf_23_0__RdReturnValid__SHIFT 0x00000005 -#define CPG_RciuDebugIntf_23_0__iGRBM_CP_reg_addr__SHIFT 0x00000006 -#define CPG_RciuDebugIntf_23_0__Reserved0__SHIFT 0x00000016 - -// CPG_RciuDebugIntf_47_24 -#define CPG_RciuDebugIntf_47_24__iGRBM_CP_reg_data_11_0__SHIFT 0x00000000 -#define CPG_RciuDebugIntf_47_24__RdReturnData_11_0__SHIFT 0x0000000c -#define CPG_RciuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_SurfSyncDebugIntf -#define CPG_SurfSyncDebugIntf__Reserved2__SHIFT 0x00000000 -#define CPG_SurfSyncDebugIntf__StartClient2__SHIFT 0x00000003 -#define CPG_SurfSyncDebugIntf__StartClient1__SHIFT 0x00000004 -#define CPG_SurfSyncDebugIntf__StartClient0__SHIFT 0x00000005 -#define CPG_SurfSyncDebugIntf__Reserved1__SHIFT 0x00000006 -#define CPG_SurfSyncDebugIntf__CleanClient2__SHIFT 0x00000009 -#define CPG_SurfSyncDebugIntf__CleanClient1__SHIFT 0x0000000a -#define CPG_SurfSyncDebugIntf__CleanClient0__SHIFT 0x0000000b -#define CPG_SurfSyncDebugIntf__Reserved0__SHIFT 0x0000000c - -// CPG_PfpParserDebugIntf_23_0 -#define CPG_PfpParserDebugIntf_23_0__qPrgmStrmXfc__SHIFT 0x00000000 -#define CPG_PfpParserDebugIntf_23_0__qPrgmStrmRts__SHIFT 0x00000001 -#define CPG_PfpParserDebugIntf_23_0__qPrgmStrmData_21_0__SHIFT 0x00000002 -#define CPG_PfpParserDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_PfpParserDebugIntf_47_24 -#define CPG_PfpParserDebugIntf_47_24__qPrgmStrmData_31_22__SHIFT 0x00000000 -#define CPG_PfpParserDebugIntf_47_24__Reserved1__SHIFT 0x0000000a -#define CPG_PfpParserDebugIntf_47_24__StoreRtr_R0__SHIFT 0x0000000c -#define CPG_PfpParserDebugIntf_47_24__StoreRts__SHIFT 0x0000000d -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceGlobal__SHIFT 0x0000000e -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceMemory__SHIFT 0x0000000f -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceMmReg__SHIFT 0x00000010 -#define CPG_PfpParserDebugIntf_47_24__StMemSpaceLocal__SHIFT 0x00000011 -#define CPG_PfpParserDebugIntf_47_24__StoreData_5_0__SHIFT 0x00000012 -#define CPG_PfpParserDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_PfpParserDebugIntf_71_48 -#define CPG_PfpParserDebugIntf_71_48__StoreData_29_6__SHIFT 0x00000000 -#define CPG_PfpParserDebugIntf_71_48__Reserved0__SHIFT 0x00000018 - -// CPG_PfpParserDebugIntf_95_72 -#define CPG_PfpParserDebugIntf_95_72__StoreData_31_30__SHIFT 0x00000000 -#define CPG_PfpParserDebugIntf_95_72__qStoreAddr_21_0__SHIFT 0x00000002 -#define CPG_PfpParserDebugIntf_95_72__Reserved0__SHIFT 0x00000018 - -// CPG_PfpParserDebugIntf_119_96 -#define CPG_PfpParserDebugIntf_119_96__qStoreAddr_45_22__SHIFT 0x00000000 -#define CPG_PfpParserDebugIntf_119_96__Reserved0__SHIFT 0x00000018 - -// CPG_PfpParserDebugIntf_143_120 -#define CPG_PfpParserDebugIntf_143_120__qStoreAddr_47_46__SHIFT 0x00000000 -#define CPG_PfpParserDebugIntf_143_120__Reserved0__SHIFT 0x00000002 - -// CPG_MeParserDebugIntf_23_0 -#define CPG_MeParserDebugIntf_23_0__StoreRts__SHIFT 0x00000000 -#define CPG_MeParserDebugIntf_23_0__StMemSpaceGlobal__SHIFT 0x00000001 -#define CPG_MeParserDebugIntf_23_0__StMemSpaceMemory__SHIFT 0x00000002 -#define CPG_MeParserDebugIntf_23_0__StMemSpaceMmReg__SHIFT 0x00000003 -#define CPG_MeParserDebugIntf_23_0__StMemSpaceLocal__SHIFT 0x00000004 -#define CPG_MeParserDebugIntf_23_0__Reserved0__SHIFT 0x00000005 - -// CPG_MeParserDebugIntf_47_24 -#define CPG_MeParserDebugIntf_47_24__Reserved0__SHIFT 0x00000000 - -// CPG_MeParserDebugIntf_71_48 -#define CPG_MeParserDebugIntf_71_48__Reserved0__SHIFT 0x00000000 - -// CPG_MeParserDebugIntf_95_72 -#define CPG_MeParserDebugIntf_95_72__Reserved1__SHIFT 0x00000000 -#define CPG_MeParserDebugIntf_95_72__qSPI0_CP_cs_done__SHIFT 0x0000000d -#define CPG_MeParserDebugIntf_95_72__qSPI0_CP_ps_done_R0__SHIFT 0x0000000e -#define CPG_MeParserDebugIntf_95_72__qSPI0_CP_partial0_flush__SHIFT 0x0000000f -#define CPG_MeParserDebugIntf_95_72__qSPI1_CP_cs_done__SHIFT 0x00000010 -#define CPG_MeParserDebugIntf_95_72__qSPI1_CP_ps_done_R0__SHIFT 0x00000011 -#define CPG_MeParserDebugIntf_95_72__qSPI1_CP_partial0_flush__SHIFT 0x00000012 -#define CPG_MeParserDebugIntf_95_72__qSPI2_CP_cs_done__SHIFT 0x00000013 -#define CPG_MeParserDebugIntf_95_72__qSPI2_CP_ps_done_R0__SHIFT 0x00000014 -#define CPG_MeParserDebugIntf_95_72__qSPI2_CP_partial0_flush__SHIFT 0x00000015 -#define CPG_MeParserDebugIntf_95_72__qSPI3_CP_cs_done__SHIFT 0x00000016 -#define CPG_MeParserDebugIntf_95_72__qSPI3_CP_ps_done_R0__SHIFT 0x00000017 -#define CPG_MeParserDebugIntf_95_72__Reserved0__SHIFT 0x00000018 - -// CPG_MeParserDebugIntf_119_96 -#define CPG_MeParserDebugIntf_119_96__qSPI3_CP_partial0_flush__SHIFT 0x00000000 -#define CPG_MeParserDebugIntf_119_96__Reserved0__SHIFT 0x00000001 - -// CPG_QueryUnitDebugIntf_23_0 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_sample__SHIFT 0x00000000 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_incr__SHIFT 0x00000001 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_pipeid__SHIFT 0x00000006 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc1_valid__SHIFT 0x00000007 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_sample__SHIFT 0x00000008 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_incr__SHIFT 0x00000009 -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_pipeid__SHIFT 0x0000000e -#define CPG_QueryUnitDebugIntf_23_0__qSC0_CP_psinvoc0_valid__SHIFT 0x0000000f -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_sample__SHIFT 0x00000010 -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_incr__SHIFT 0x00000011 -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_pipeid__SHIFT 0x00000012 -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cprim_valid__SHIFT 0x00000013 -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_sample__SHIFT 0x00000014 -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_incr__SHIFT 0x00000015 -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_pipeid__SHIFT 0x00000016 -#define CPG_QueryUnitDebugIntf_23_0__qPA0_CP_cinvoc_valid__SHIFT 0x00000017 -#define CPG_QueryUnitDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_QueryUnitDebugIntf_47_24 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_sample__SHIFT 0x00000000 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_incr__SHIFT 0x00000001 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_pipeid__SHIFT 0x00000002 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsinvoc_valid__SHIFT 0x00000003 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_sample__SHIFT 0x00000004 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_incr__SHIFT 0x00000005 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_pipeid__SHIFT 0x00000009 -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_vsinvoc_valid__SHIFT 0x0000000a -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_sample__SHIFT 0x0000000b -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_incr__SHIFT 0x0000000c -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_pipeid__SHIFT 0x0000000d -#define CPG_QueryUnitDebugIntf_47_24__qVGT0_CP_gsprim_valid__SHIFT 0x0000000e -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iaprim_sample__SHIFT 0x0000000f -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iaprim_incr__SHIFT 0x00000010 -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iaprim_valid__SHIFT 0x00000012 -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iavert_sample__SHIFT 0x00000013 -#define CPG_QueryUnitDebugIntf_47_24__qIA0_CP_iavert_incr__SHIFT 0x00000014 -#define CPG_QueryUnitDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_QueryUnitDebugIntf_71_48 -#define CPG_QueryUnitDebugIntf_71_48__qIA0_CP_iavert_valid__SHIFT 0x00000000 -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_flushed__SHIFT 0x00000001 -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_sample__SHIFT 0x00000002 -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_incr1_neq_0__SHIFT 0x00000003 -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_incr0_neq_0__SHIFT 0x00000004 -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_pipeid__SHIFT 0x00000005 -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_id__SHIFT 0x00000006 -#define CPG_QueryUnitDebugIntf_71_48__qVGT0_CP_strmout_valid__SHIFT 0x00000008 -#define CPG_QueryUnitDebugIntf_71_48__qSE0SC_CP_eop1_done__SHIFT 0x00000009 -#define CPG_QueryUnitDebugIntf_71_48__qSE0SC_CP_eop0_done__SHIFT 0x0000000a -#define CPG_QueryUnitDebugIntf_71_48__qEopdOutstandingTagCnt_R1_neq_0__SHIFT 0x0000000b -#define CPG_QueryUnitDebugIntf_71_48__qEopdOutstandingTagCnt_R0_neq_0__SHIFT 0x0000000c -#define CPG_QueryUnitDebugIntf_71_48__qStrmOutstandingTagCnt_R1_neq_0__SHIFT 0x0000000d -#define CPG_QueryUnitDebugIntf_71_48__qStrmOutstandingTagCnt_R0_neq_0__SHIFT 0x0000000e -#define CPG_QueryUnitDebugIntf_71_48__qPipeOutstandingTagCnt_R1_neq_0__SHIFT 0x0000000f -#define CPG_QueryUnitDebugIntf_71_48__qPipeOutstandingTagCnt_R0_neq_0__SHIFT 0x00000010 -#define CPG_QueryUnitDebugIntf_71_48__Reserved0__SHIFT 0x00000011 - -// CPG_Clk_Valid -#define CPG_Clk_Valid__RegisterClkValid__SHIFT 0x00000000 -#define CPG_Clk_Valid__DynamicClkValid__SHIFT 0x00000001 -#define CPG_Clk_Valid__Reserved0__SHIFT 0x00000002 - -// CPG_DcDebugIntf0 -#define CPG_DcDebugIntf0__gd_valid__SHIFT 0x00000000 -#define CPG_DcDebugIntf0__gd_data_type__SHIFT 0x00000001 -#define CPG_DcDebugIntf0__gd_addr__SHIFT 0x00000003 -#define CPG_DcDebugIntf0__gd_data_13_0__SHIFT 0x0000000a -#define CPG_DcDebugIntf0__Reserved0__SHIFT 0x00000018 - -// CPG_DcDebugIntf1 -#define CPG_DcDebugIntf1__gd_valid__SHIFT 0x00000000 -#define CPG_DcDebugIntf1__gd_data_31_14__SHIFT 0x00000001 -#define CPG_DcDebugIntf1__Reserved0__SHIFT 0x00000013 - -// CPG_DcDebugIntf2 -#define CPG_DcDebugIntf2__valid_q0__SHIFT 0x00000000 -#define CPG_DcDebugIntf2__state_q__SHIFT 0x00000001 -#define CPG_DcDebugIntf2__steering_state_q__SHIFT 0x00000005 -#define CPG_DcDebugIntf2__first_thread_group_q0__SHIFT 0x00000008 -#define CPG_DcDebugIntf2__last_thread_group_q0__SHIFT 0x00000009 -#define CPG_DcDebugIntf2__kill_dispatch_mode0__SHIFT 0x0000000a -#define CPG_DcDebugIntf2__kill_dispatch_mode1__SHIFT 0x0000000b -#define CPG_DcDebugIntf2__gd_stall__SHIFT 0x0000000c -#define CPG_DcDebugIntf2__disp_stall_q__SHIFT 0x0000000d -#define CPG_DcDebugIntf2__no_serializer_is_busy__SHIFT 0x0000000e -#define CPG_DcDebugIntf2__gd_dispatch_busy__SHIFT 0x0000000f -#define CPG_DcDebugIntf2__gd_busy__SHIFT 0x00000010 -#define CPG_DcDebugIntf2__num_se_with_cu_active__SHIFT 0x00000011 -#define CPG_DcDebugIntf2__send_num_threads_x_q__SHIFT 0x00000014 -#define CPG_DcDebugIntf2__send_num_threads_y_q__SHIFT 0x00000015 -#define CPG_DcDebugIntf2__send_num_threads_z_q__SHIFT 0x00000016 -#define CPG_DcDebugIntf2__Reserved0__SHIFT 0x00000017 - -// CPG_DcDebugIntf3 -#define CPG_DcDebugIntf3__gddata_send__SHIFT 0x00000000 -#define CPG_DcDebugIntf3__gddata_data_type__SHIFT 0x00000001 -#define CPG_DcDebugIntf3__data_x_q1__SHIFT 0x00000003 -#define CPG_DcDebugIntf3__Reserved0__SHIFT 0x00000018 - -// CPG_DcDebugIntf4 -#define CPG_DcDebugIntf4__data_y_q1__SHIFT 0x00000000 -#define CPG_DcDebugIntf4__data_z_q1__SHIFT 0x0000000c -#define CPG_DcDebugIntf4__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_23_0 -#define CPG_F32CeDebugBus_23_0__LdStrBufferData_23_0__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_47_24 -#define CPG_F32CeDebugBus_47_24__LdStrBufferData_47_24__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_71_48 -#define CPG_F32CeDebugBus_71_48__LdStrBufferData_63_48__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_71_48__LdStrBufferAddress_7_0__SHIFT 0x00000010 -#define CPG_F32CeDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_95_72 -#define CPG_F32CeDebugBus_95_72__LdStrBufferAddress_31_8__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_119_96 -#define CPG_F32CeDebugBus_119_96__LdStrBufferAddress_47_32__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_119_96__LdStrBufferInstrOp__SHIFT 0x00000010 -#define CPG_F32CeDebugBus_119_96__LdStrInstrSel__SHIFT 0x00000011 -#define CPG_F32CeDebugBus_119_96__LdStrMemSpace__SHIFT 0x00000013 -#define CPG_F32CeDebugBus_119_96__qLoadStoreBusy__SHIFT 0x00000015 -#define CPG_F32CeDebugBus_119_96__Reserved1__SHIFT 0x00000016 -#define CPG_F32CeDebugBus_119_96__qLoadState_B_0__SHIFT 0x00000017 -#define CPG_F32CeDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_143_120 -#define CPG_F32CeDebugBus_143_120__qLoadState_B_1__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_143_120__qLoadState_A__SHIFT 0x00000001 -#define CPG_F32CeDebugBus_143_120__LdStrBufferEmpty__SHIFT 0x00000003 -#define CPG_F32CeDebugBus_143_120__LdStrBufferFull__SHIFT 0x00000004 -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc2Valid_B__SHIFT 0x00000005 -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc1Valid_B__SHIFT 0x00000006 -#define CPG_F32CeDebugBus_143_120__qInstrMeValid_B__SHIFT 0x00000007 -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc2Valid_A__SHIFT 0x00000008 -#define CPG_F32CeDebugBus_143_120__qInstrMeSrc1Valid_A__SHIFT 0x00000009 -#define CPG_F32CeDebugBus_143_120__qInstrMeValid_A__SHIFT 0x0000000a -#define CPG_F32CeDebugBus_143_120__Reserved0__SHIFT 0x0000000b - -// CPG_F32CeDebugBus_167_144 -#define CPG_F32CeDebugBus_167_144__Reserved1__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_167_144__qLoadArbState__SHIFT 0x00000010 -#define CPG_F32CeDebugBus_167_144__qStoreArbState__SHIFT 0x00000012 -#define CPG_F32CeDebugBus_167_144__Reserved0__SHIFT 0x00000014 - -// CPG_F32CeDebugBus_191_168 -#define CPG_F32CeDebugBus_191_168__Reserved0__SHIFT 0x00000000 - -// CPG_F32CeDebugBus_215_192 -#define CPG_F32CeDebugBus_215_192__qAluArbState_B__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_215_192__qAluArbState_A__SHIFT 0x00000002 -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B__SHIFT 0x00000004 -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B__SHIFT 0x00000005 -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExValid_B__SHIFT 0x00000006 -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A__SHIFT 0x00000007 -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A__SHIFT 0x00000008 -#define CPG_F32CeDebugBus_215_192__DebugBusO_qInstrExValid_A__SHIFT 0x00000009 -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B__SHIFT 0x0000000a -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B__SHIFT 0x0000000b -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExValid_B__SHIFT 0x0000000c -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A__SHIFT 0x0000000d -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A__SHIFT 0x0000000e -#define CPG_F32CeDebugBus_215_192__DebugBus1_qInstrExValid_A__SHIFT 0x0000000f -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B__SHIFT 0x00000010 -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B__SHIFT 0x00000011 -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExValid_B__SHIFT 0x00000012 -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A__SHIFT 0x00000013 -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A__SHIFT 0x00000014 -#define CPG_F32CeDebugBus_215_192__DebugBus2_qInstrExValid_A__SHIFT 0x00000015 -#define CPG_F32CeDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B__SHIFT 0x00000016 -#define CPG_F32CeDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B__SHIFT 0x00000017 -#define CPG_F32CeDebugBus_215_192__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_239_216 -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExValid_B__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A__SHIFT 0x00000001 -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A__SHIFT 0x00000002 -#define CPG_F32CeDebugBus_239_216__DebugBus3_qInstrExValid_A__SHIFT 0x00000003 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid15__SHIFT 0x00000004 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid14__SHIFT 0x00000005 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid13__SHIFT 0x00000006 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid12__SHIFT 0x00000007 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid11__SHIFT 0x00000008 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid10__SHIFT 0x00000009 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid9__SHIFT 0x0000000a -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid8__SHIFT 0x0000000b -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid7__SHIFT 0x0000000c -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid6__SHIFT 0x0000000d -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid5__SHIFT 0x0000000e -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid4__SHIFT 0x0000000f -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid3__SHIFT 0x00000010 -#define CPG_F32CeDebugBus_239_216__DebugBus0_qGprValid2__SHIFT 0x00000011 -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid15__SHIFT 0x00000012 -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid14__SHIFT 0x00000013 -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid13__SHIFT 0x00000014 -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid12__SHIFT 0x00000015 -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid11__SHIFT 0x00000016 -#define CPG_F32CeDebugBus_239_216__DebugBus1_qGprValid10__SHIFT 0x00000017 -#define CPG_F32CeDebugBus_239_216__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_263_240 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid9__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid8__SHIFT 0x00000001 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid7__SHIFT 0x00000002 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid6__SHIFT 0x00000003 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid5__SHIFT 0x00000004 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid4__SHIFT 0x00000005 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid3__SHIFT 0x00000006 -#define CPG_F32CeDebugBus_263_240__DebugBus1_qGprValid2__SHIFT 0x00000007 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid15__SHIFT 0x00000008 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid14__SHIFT 0x00000009 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid13__SHIFT 0x0000000a -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid12__SHIFT 0x0000000b -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid11__SHIFT 0x0000000c -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid10__SHIFT 0x0000000d -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid9__SHIFT 0x0000000e -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid8__SHIFT 0x0000000f -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid7__SHIFT 0x00000010 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid6__SHIFT 0x00000011 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid5__SHIFT 0x00000012 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid4__SHIFT 0x00000013 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid3__SHIFT 0x00000014 -#define CPG_F32CeDebugBus_263_240__DebugBus2_qGprValid2__SHIFT 0x00000015 -#define CPG_F32CeDebugBus_263_240__DebugBus3_qGprValid15__SHIFT 0x00000016 -#define CPG_F32CeDebugBus_263_240__DebugBus3_qGprValid14__SHIFT 0x00000017 -#define CPG_F32CeDebugBus_263_240__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_287_264 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid13__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid12__SHIFT 0x00000001 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid11__SHIFT 0x00000002 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid10__SHIFT 0x00000003 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid9__SHIFT 0x00000004 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid8__SHIFT 0x00000005 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid7__SHIFT 0x00000006 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid6__SHIFT 0x00000007 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid5__SHIFT 0x00000008 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid4__SHIFT 0x00000009 -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid3__SHIFT 0x0000000a -#define CPG_F32CeDebugBus_287_264__DebugBus3_qGprValid2__SHIFT 0x0000000b -#define CPG_F32CeDebugBus_287_264__qDecodeInstr_A_11_0__SHIFT 0x0000000c -#define CPG_F32CeDebugBus_287_264__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_311_288 -#define CPG_F32CeDebugBus_311_288__qDecodeInstr_A_31_12__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_311_288__qDecodeInstr_B_3_0__SHIFT 0x00000014 -#define CPG_F32CeDebugBus_311_288__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_335_312 -#define CPG_F32CeDebugBus_335_312__qDecodeInstr_B_27_4__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_335_312__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_359_336 -#define CPG_F32CeDebugBus_359_336__qDecodeInstr_B_31_28__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_359_336__qDecodeAddress_A_padded__SHIFT 0x00000004 -#define CPG_F32CeDebugBus_359_336__qDecodeAddress_B_padded_3_0__SHIFT 0x00000014 -#define CPG_F32CeDebugBus_359_336__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_383_360 -#define CPG_F32CeDebugBus_383_360__qDecodeAddress_B_padded_15_4__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_383_360__qAluIntUnitPntr_A__SHIFT 0x0000000c -#define CPG_F32CeDebugBus_383_360__AluIntUnitPntr_B__SHIFT 0x0000000f -#define CPG_F32CeDebugBus_383_360__qLdStrUnitPntr_A__SHIFT 0x00000012 -#define CPG_F32CeDebugBus_383_360__qLdStrUnitPntr_B__SHIFT 0x00000015 -#define CPG_F32CeDebugBus_383_360__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_407_384 -#define CPG_F32CeDebugBus_407_384__qDecodeInstrRts_A__SHIFT 0x00000000 -#define CPG_F32CeDebugBus_407_384__qDecodeInstrRts_B__SHIFT 0x00000001 -#define CPG_F32CeDebugBus_407_384__qJumpSourceRts__SHIFT 0x00000002 -#define CPG_F32CeDebugBus_407_384__qInstrEtsCnt_le_6__SHIFT 0x00000003 -#define CPG_F32CeDebugBus_407_384__Reserved1__SHIFT 0x00000004 -#define CPG_F32CeDebugBus_407_384__qThreadIdState__SHIFT 0x00000014 -#define CPG_F32CeDebugBus_407_384__Reserved0__SHIFT 0x00000018 - -// CPG_F32CeDebugBus_431_408 -#define CPG_F32CeDebugBus_431_408__Reserved0__SHIFT 0x00000000 - -// CPG_F32CeDebugBus_447_432 -#define CPG_F32CeDebugBus_447_432__Reserved0__SHIFT 0x00000000 - -// CPG_AtcL2iuDebugIntf_23_0 -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_tag__SHIFT 0x00000000 -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_xnack__SHIFT 0x00000007 -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_snoop__SHIFT 0x00000009 -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_valid__SHIFT 0x0000000a -#define CPG_AtcL2iuDebugIntf_23_0__qATCL2_CPG_ret_physical_address_12_0__SHIFT 0x0000000b -#define CPG_AtcL2iuDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_AtcL2iuDebugIntf_47_24 -#define CPG_AtcL2iuDebugIntf_47_24__qATCL2_CPG_ret_physical_address_35_13__SHIFT 0x00000000 -#define CPG_AtcL2iuDebugIntf_47_24__CPG_ATCL2_req_data_0__SHIFT 0x00000017 -#define CPG_AtcL2iuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_AtcL2iuDebugIntf_71_48 -#define CPG_AtcL2iuDebugIntf_71_48__CPG_ATCL2_req_data_15_1__SHIFT 0x00000000 -#define CPG_AtcL2iuDebugIntf_71_48__qCPG_ATCL2_req_free__SHIFT 0x0000000f -#define CPG_AtcL2iuDebugIntf_71_48__CPG_ATCL2_req_send__SHIFT 0x00000010 -#define CPG_AtcL2iuDebugIntf_71_48__qAtcL2XferCycle_eq_0__SHIFT 0x00000011 -#define CPG_AtcL2iuDebugIntf_71_48__Reserved0__SHIFT 0x00000012 - -// CPG_CeParserDebugIntf_23_0 -#define CPG_CeParserDebugIntf_23_0__qPrgmStrmXfc__SHIFT 0x00000000 -#define CPG_CeParserDebugIntf_23_0__qPrgmStrmRts__SHIFT 0x00000001 -#define CPG_CeParserDebugIntf_23_0__qPrgmStrmData_21_0__SHIFT 0x00000002 -#define CPG_CeParserDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_CeParserDebugIntf_47_24 -#define CPG_CeParserDebugIntf_47_24__qPrgmStrmData_31_22__SHIFT 0x00000000 -#define CPG_CeParserDebugIntf_47_24__StoreRtr_2__SHIFT 0x0000000a -#define CPG_CeParserDebugIntf_47_24__StoreRtr_1__SHIFT 0x0000000b -#define CPG_CeParserDebugIntf_47_24__StoreRtr_0__SHIFT 0x0000000c -#define CPG_CeParserDebugIntf_47_24__StoreRts__SHIFT 0x0000000d -#define CPG_CeParserDebugIntf_47_24__StMemSpaceGlobal__SHIFT 0x0000000e -#define CPG_CeParserDebugIntf_47_24__StMemSpaceMemory__SHIFT 0x0000000f -#define CPG_CeParserDebugIntf_47_24__StMemSpaceMmReg__SHIFT 0x00000010 -#define CPG_CeParserDebugIntf_47_24__StMemSpaceLocal__SHIFT 0x00000011 -#define CPG_CeParserDebugIntf_47_24__StoreData_5_0__SHIFT 0x00000012 -#define CPG_CeParserDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_CeParserDebugIntf_71_48 -#define CPG_CeParserDebugIntf_71_48__StoreData_29_6__SHIFT 0x00000000 -#define CPG_CeParserDebugIntf_71_48__Reserved0__SHIFT 0x00000018 - -// CPG_CeParserDebugIntf_95_72 -#define CPG_CeParserDebugIntf_95_72__StoreData_31_30__SHIFT 0x00000000 -#define CPG_CeParserDebugIntf_95_72__qStoreAddr_21_0__SHIFT 0x00000002 -#define CPG_CeParserDebugIntf_95_72__Reserved0__SHIFT 0x00000018 - -// CPG_CeParserDebugIntf_119_96 -#define CPG_CeParserDebugIntf_119_96__qStoreAddr_45_22__SHIFT 0x00000000 -#define CPG_CeParserDebugIntf_119_96__Reserved0__SHIFT 0x00000018 - -// CPG_TciuDebugIntf_23_0 -#define CPG_TciuDebugIntf_23_0__CPG_TC_info_stall__SHIFT 0x00000000 -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_send__SHIFT 0x00000001 -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_vmid__SHIFT 0x00000002 -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_op__SHIFT 0x00000006 -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_submask__SHIFT 0x0000000d -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_fed__SHIFT 0x00000015 -#define CPG_TciuDebugIntf_23_0__CPG_TC_req_tag_1_0__SHIFT 0x00000016 -#define CPG_TciuDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_TciuDebugIntf_47_24 -#define CPG_TciuDebugIntf_47_24__CPG_TC_req_tag_9_2__SHIFT 0x00000000 -#define CPG_TciuDebugIntf_47_24__CPG_TC_req_addr_15_0__SHIFT 0x00000008 -#define CPG_TciuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_TciuDebugIntf_71_48 -#define CPG_TciuDebugIntf_71_48__CPG_TC_req_addr_39_16__SHIFT 0x00000000 -#define CPG_TciuDebugIntf_71_48__Reserved0__SHIFT 0x00000018 - -// CPG_TciuDebugIntf_95_72 -#define CPG_TciuDebugIntf_95_72__CPG_TC_req_addr_41_40__SHIFT 0x00000000 -#define CPG_TciuDebugIntf_95_72__CPG_TC_req_subdata_21_0__SHIFT 0x00000002 -#define CPG_TciuDebugIntf_95_72__Reserved0__SHIFT 0x00000018 - -// CPG_TciuDebugIntf_119_96 -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_subdata_31_22__SHIFT 0x00000000 -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_physical__SHIFT 0x0000000a -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_snoop__SHIFT 0x0000000b -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_mtype__SHIFT 0x0000000c -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_policy__SHIFT 0x0000000e -#define CPG_TciuDebugIntf_119_96__CPG_TC_req_exe__SHIFT 0x0000000f -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_valid__SHIFT 0x00000010 -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_fed__SHIFT 0x00000011 -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_ack__SHIFT 0x00000012 -#define CPG_TciuDebugIntf_119_96__Aligned_TC_CPG_ret_tag_4_0__SHIFT 0x00000013 -#define CPG_TciuDebugIntf_119_96__Reserved0__SHIFT 0x00000018 - -// CPG_TciuDebugIntf_143_120 -#define CPG_TciuDebugIntf_143_120__Aligned_TC_CPG_ret_tag_9_5__SHIFT 0x00000000 -#define CPG_TciuDebugIntf_143_120__Aligned_TC_CPG_ret_subdata_18_0__SHIFT 0x00000005 -#define CPG_TciuDebugIntf_143_120__Reserved0__SHIFT 0x00000018 - -// CPG_TciuDebugIntf_167_144 -#define CPG_TciuDebugIntf_167_144__Aligned_TC_CPG_ret_subdata_31_19__SHIFT 0x00000000 -#define CPG_TciuDebugIntf_167_144__Reserved0__SHIFT 0x0000000d - -// CPG_SemaphoreDebugIntf -#define CPG_SemaphoreDebugIntf__qCPF_CPG_resp_pipeid__SHIFT 0x00000000 -#define CPG_SemaphoreDebugIntf__qCPF_CPG_resp_status__SHIFT 0x00000002 -#define CPG_SemaphoreDebugIntf__qCPF_CPG_resp_valid__SHIFT 0x00000004 -#define CPG_SemaphoreDebugIntf__qCP_SEM_poll_addr__SHIFT 0x00000005 -#define CPG_SemaphoreDebugIntf__qCP_SEM_poll_cmd__SHIFT 0x00000011 -#define CPG_SemaphoreDebugIntf__qCP_SEM_poll_send__SHIFT 0x00000012 -#define CPG_SemaphoreDebugIntf__Reserved0__SHIFT 0x00000013 - -// CPG_F32PfpDebugBus_23_0 -#define CPG_F32PfpDebugBus_23_0__LdStrBufferData_23_0__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_47_24 -#define CPG_F32PfpDebugBus_47_24__LdStrBufferData_47_24__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_71_48 -#define CPG_F32PfpDebugBus_71_48__LdStrBufferData_63_48__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_71_48__LdStrBufferAddress_7_0__SHIFT 0x00000010 -#define CPG_F32PfpDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_95_72 -#define CPG_F32PfpDebugBus_95_72__LdStrBufferAddress_31_8__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_119_96 -#define CPG_F32PfpDebugBus_119_96__LdStrBufferAddress_47_32__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_119_96__LdStrBufferInstrOp__SHIFT 0x00000010 -#define CPG_F32PfpDebugBus_119_96__LdStrInstrSel__SHIFT 0x00000011 -#define CPG_F32PfpDebugBus_119_96__LdStrMemSpace__SHIFT 0x00000013 -#define CPG_F32PfpDebugBus_119_96__qLoadStoreBusy__SHIFT 0x00000015 -#define CPG_F32PfpDebugBus_119_96__Reserved1__SHIFT 0x00000016 -#define CPG_F32PfpDebugBus_119_96__qLoadState_B_0__SHIFT 0x00000017 -#define CPG_F32PfpDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_143_120 -#define CPG_F32PfpDebugBus_143_120__qLoadState_B_1__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_143_120__qLoadState_A__SHIFT 0x00000001 -#define CPG_F32PfpDebugBus_143_120__LdStrBufferEmpty__SHIFT 0x00000003 -#define CPG_F32PfpDebugBus_143_120__LdStrBufferFull__SHIFT 0x00000004 -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc2Valid_B__SHIFT 0x00000005 -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc1Valid_B__SHIFT 0x00000006 -#define CPG_F32PfpDebugBus_143_120__qInstrMeValid_B__SHIFT 0x00000007 -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc2Valid_A__SHIFT 0x00000008 -#define CPG_F32PfpDebugBus_143_120__qInstrMeSrc1Valid_A__SHIFT 0x00000009 -#define CPG_F32PfpDebugBus_143_120__qInstrMeValid_A__SHIFT 0x0000000a -#define CPG_F32PfpDebugBus_143_120__Reserved0__SHIFT 0x0000000b - -// CPG_F32PfpDebugBus_167_144 -#define CPG_F32PfpDebugBus_167_144__Reserved1__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_167_144__qLoadArbState__SHIFT 0x00000010 -#define CPG_F32PfpDebugBus_167_144__qStoreArbState__SHIFT 0x00000012 -#define CPG_F32PfpDebugBus_167_144__Reserved0__SHIFT 0x00000014 - -// CPG_F32PfpDebugBus_191_168 -#define CPG_F32PfpDebugBus_191_168__Reserved0__SHIFT 0x00000000 - -// CPG_F32PfpDebugBus_215_192 -#define CPG_F32PfpDebugBus_215_192__qAluArbState_B__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_215_192__qAluArbState_A__SHIFT 0x00000002 -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B__SHIFT 0x00000004 -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B__SHIFT 0x00000005 -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExValid_B__SHIFT 0x00000006 -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A__SHIFT 0x00000007 -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A__SHIFT 0x00000008 -#define CPG_F32PfpDebugBus_215_192__DebugBusO_qInstrExValid_A__SHIFT 0x00000009 -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B__SHIFT 0x0000000a -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B__SHIFT 0x0000000b -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExValid_B__SHIFT 0x0000000c -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A__SHIFT 0x0000000d -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A__SHIFT 0x0000000e -#define CPG_F32PfpDebugBus_215_192__DebugBus1_qInstrExValid_A__SHIFT 0x0000000f -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B__SHIFT 0x00000010 -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B__SHIFT 0x00000011 -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExValid_B__SHIFT 0x00000012 -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A__SHIFT 0x00000013 -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A__SHIFT 0x00000014 -#define CPG_F32PfpDebugBus_215_192__DebugBus2_qInstrExValid_A__SHIFT 0x00000015 -#define CPG_F32PfpDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B__SHIFT 0x00000016 -#define CPG_F32PfpDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B__SHIFT 0x00000017 -#define CPG_F32PfpDebugBus_215_192__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_239_216 -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExValid_B__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A__SHIFT 0x00000001 -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A__SHIFT 0x00000002 -#define CPG_F32PfpDebugBus_239_216__DebugBus3_qInstrExValid_A__SHIFT 0x00000003 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid15__SHIFT 0x00000004 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid14__SHIFT 0x00000005 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid13__SHIFT 0x00000006 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid12__SHIFT 0x00000007 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid11__SHIFT 0x00000008 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid10__SHIFT 0x00000009 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid9__SHIFT 0x0000000a -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid8__SHIFT 0x0000000b -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid7__SHIFT 0x0000000c -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid6__SHIFT 0x0000000d -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid5__SHIFT 0x0000000e -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid4__SHIFT 0x0000000f -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid3__SHIFT 0x00000010 -#define CPG_F32PfpDebugBus_239_216__DebugBus0_qGprValid2__SHIFT 0x00000011 -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid15__SHIFT 0x00000012 -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid14__SHIFT 0x00000013 -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid13__SHIFT 0x00000014 -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid12__SHIFT 0x00000015 -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid11__SHIFT 0x00000016 -#define CPG_F32PfpDebugBus_239_216__DebugBus1_qGprValid10__SHIFT 0x00000017 -#define CPG_F32PfpDebugBus_239_216__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_263_240 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid9__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid8__SHIFT 0x00000001 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid7__SHIFT 0x00000002 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid6__SHIFT 0x00000003 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid5__SHIFT 0x00000004 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid4__SHIFT 0x00000005 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid3__SHIFT 0x00000006 -#define CPG_F32PfpDebugBus_263_240__DebugBus1_qGprValid2__SHIFT 0x00000007 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid15__SHIFT 0x00000008 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid14__SHIFT 0x00000009 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid13__SHIFT 0x0000000a -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid12__SHIFT 0x0000000b -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid11__SHIFT 0x0000000c -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid10__SHIFT 0x0000000d -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid9__SHIFT 0x0000000e -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid8__SHIFT 0x0000000f -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid7__SHIFT 0x00000010 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid6__SHIFT 0x00000011 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid5__SHIFT 0x00000012 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid4__SHIFT 0x00000013 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid3__SHIFT 0x00000014 -#define CPG_F32PfpDebugBus_263_240__DebugBus2_qGprValid2__SHIFT 0x00000015 -#define CPG_F32PfpDebugBus_263_240__DebugBus3_qGprValid15__SHIFT 0x00000016 -#define CPG_F32PfpDebugBus_263_240__DebugBus3_qGprValid14__SHIFT 0x00000017 -#define CPG_F32PfpDebugBus_263_240__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_287_264 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid13__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid12__SHIFT 0x00000001 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid11__SHIFT 0x00000002 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid10__SHIFT 0x00000003 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid9__SHIFT 0x00000004 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid8__SHIFT 0x00000005 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid7__SHIFT 0x00000006 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid6__SHIFT 0x00000007 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid5__SHIFT 0x00000008 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid4__SHIFT 0x00000009 -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid3__SHIFT 0x0000000a -#define CPG_F32PfpDebugBus_287_264__DebugBus3_qGprValid2__SHIFT 0x0000000b -#define CPG_F32PfpDebugBus_287_264__qDecodeInstr_A_11_0__SHIFT 0x0000000c -#define CPG_F32PfpDebugBus_287_264__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_311_288 -#define CPG_F32PfpDebugBus_311_288__qDecodeInstr_A_31_12__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_311_288__qDecodeInstr_B_3_0__SHIFT 0x00000014 -#define CPG_F32PfpDebugBus_311_288__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_335_312 -#define CPG_F32PfpDebugBus_335_312__qDecodeInstr_B_27_4__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_335_312__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_359_336 -#define CPG_F32PfpDebugBus_359_336__qDecodeInstr_B_31_28__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_359_336__qDecodeAddress_A_padded__SHIFT 0x00000004 -#define CPG_F32PfpDebugBus_359_336__qDecodeAddress_B_padded_3_0__SHIFT 0x00000014 -#define CPG_F32PfpDebugBus_359_336__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_383_360 -#define CPG_F32PfpDebugBus_383_360__qDecodeAddress_B_padded_15_4__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_383_360__qAluIntUnitPntr_A__SHIFT 0x0000000c -#define CPG_F32PfpDebugBus_383_360__AluIntUnitPntr_B__SHIFT 0x0000000f -#define CPG_F32PfpDebugBus_383_360__qLdStrUnitPntr_A__SHIFT 0x00000012 -#define CPG_F32PfpDebugBus_383_360__qLdStrUnitPntr_B__SHIFT 0x00000015 -#define CPG_F32PfpDebugBus_383_360__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_407_384 -#define CPG_F32PfpDebugBus_407_384__qDecodeInstrRts_A__SHIFT 0x00000000 -#define CPG_F32PfpDebugBus_407_384__qDecodeInstrRts_B__SHIFT 0x00000001 -#define CPG_F32PfpDebugBus_407_384__qJumpSourceRts__SHIFT 0x00000002 -#define CPG_F32PfpDebugBus_407_384__qInstrEtsCnt_le_6__SHIFT 0x00000003 -#define CPG_F32PfpDebugBus_407_384__Reserved1__SHIFT 0x00000004 -#define CPG_F32PfpDebugBus_407_384__qThreadIdState__SHIFT 0x00000014 -#define CPG_F32PfpDebugBus_407_384__Reserved0__SHIFT 0x00000018 - -// CPG_F32PfpDebugBus_431_408 -#define CPG_F32PfpDebugBus_431_408__Reserved0__SHIFT 0x00000000 - -// CPG_F32PfpDebugBus_447_432 -#define CPG_F32PfpDebugBus_447_432__Reserved0__SHIFT 0x00000000 - -// CPG_F32MeDebugBus_23_0 -#define CPG_F32MeDebugBus_23_0__LdStrBufferData_23_0__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_47_24 -#define CPG_F32MeDebugBus_47_24__LdStrBufferData_47_24__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_71_48 -#define CPG_F32MeDebugBus_71_48__LdStrBufferData_63_48__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_71_48__LdStrBufferAddress_7_0__SHIFT 0x00000010 -#define CPG_F32MeDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_95_72 -#define CPG_F32MeDebugBus_95_72__LdStrBufferAddress_31_8__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_119_96 -#define CPG_F32MeDebugBus_119_96__LdStrBufferAddress_47_32__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_119_96__LdStrBufferInstrOp__SHIFT 0x00000010 -#define CPG_F32MeDebugBus_119_96__LdStrInstrSel__SHIFT 0x00000011 -#define CPG_F32MeDebugBus_119_96__LdStrMemSpace__SHIFT 0x00000013 -#define CPG_F32MeDebugBus_119_96__qLoadStoreBusy__SHIFT 0x00000015 -#define CPG_F32MeDebugBus_119_96__Reserved1__SHIFT 0x00000016 -#define CPG_F32MeDebugBus_119_96__qLoadState_B_0__SHIFT 0x00000017 -#define CPG_F32MeDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_143_120 -#define CPG_F32MeDebugBus_143_120__qLoadState_B_1__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_143_120__qLoadState_A__SHIFT 0x00000001 -#define CPG_F32MeDebugBus_143_120__LdStrBufferEmpty__SHIFT 0x00000003 -#define CPG_F32MeDebugBus_143_120__LdStrBufferFull__SHIFT 0x00000004 -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc2Valid_B__SHIFT 0x00000005 -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc1Valid_B__SHIFT 0x00000006 -#define CPG_F32MeDebugBus_143_120__qInstrMeValid_B__SHIFT 0x00000007 -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc2Valid_A__SHIFT 0x00000008 -#define CPG_F32MeDebugBus_143_120__qInstrMeSrc1Valid_A__SHIFT 0x00000009 -#define CPG_F32MeDebugBus_143_120__qInstrMeValid_A__SHIFT 0x0000000a -#define CPG_F32MeDebugBus_143_120__Reserved0__SHIFT 0x0000000b - -// CPG_F32MeDebugBus_167_144 -#define CPG_F32MeDebugBus_167_144__Reserved1__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_167_144__qLoadArbState__SHIFT 0x00000010 -#define CPG_F32MeDebugBus_167_144__qStoreArbState__SHIFT 0x00000012 -#define CPG_F32MeDebugBus_167_144__Reserved0__SHIFT 0x00000014 - -// CPG_F32MeDebugBus_191_168 -#define CPG_F32MeDebugBus_191_168__Reserved0__SHIFT 0x00000000 - -// CPG_F32MeDebugBus_215_192 -#define CPG_F32MeDebugBus_215_192__qAluArbState_B__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_215_192__qAluArbState_A__SHIFT 0x00000002 -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_B__SHIFT 0x00000004 -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_B__SHIFT 0x00000005 -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExValid_B__SHIFT 0x00000006 -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc2Valid_A__SHIFT 0x00000007 -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExSrc1Valid_A__SHIFT 0x00000008 -#define CPG_F32MeDebugBus_215_192__DebugBusO_qInstrExValid_A__SHIFT 0x00000009 -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_B__SHIFT 0x0000000a -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_B__SHIFT 0x0000000b -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExValid_B__SHIFT 0x0000000c -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc2Valid_A__SHIFT 0x0000000d -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExSrc1Valid_A__SHIFT 0x0000000e -#define CPG_F32MeDebugBus_215_192__DebugBus1_qInstrExValid_A__SHIFT 0x0000000f -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_B__SHIFT 0x00000010 -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_B__SHIFT 0x00000011 -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExValid_B__SHIFT 0x00000012 -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc2Valid_A__SHIFT 0x00000013 -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExSrc1Valid_A__SHIFT 0x00000014 -#define CPG_F32MeDebugBus_215_192__DebugBus2_qInstrExValid_A__SHIFT 0x00000015 -#define CPG_F32MeDebugBus_215_192__DebugBus3_qInstrExSrc2Valid_B__SHIFT 0x00000016 -#define CPG_F32MeDebugBus_215_192__DebugBus3_qInstrExSrc1Valid_B__SHIFT 0x00000017 -#define CPG_F32MeDebugBus_215_192__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_239_216 -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExValid_B__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExSrc2Valid_A__SHIFT 0x00000001 -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExSrc1Valid_A__SHIFT 0x00000002 -#define CPG_F32MeDebugBus_239_216__DebugBus3_qInstrExValid_A__SHIFT 0x00000003 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid15__SHIFT 0x00000004 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid14__SHIFT 0x00000005 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid13__SHIFT 0x00000006 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid12__SHIFT 0x00000007 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid11__SHIFT 0x00000008 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid10__SHIFT 0x00000009 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid9__SHIFT 0x0000000a -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid8__SHIFT 0x0000000b -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid7__SHIFT 0x0000000c -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid6__SHIFT 0x0000000d -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid5__SHIFT 0x0000000e -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid4__SHIFT 0x0000000f -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid3__SHIFT 0x00000010 -#define CPG_F32MeDebugBus_239_216__DebugBus0_qGprValid2__SHIFT 0x00000011 -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid15__SHIFT 0x00000012 -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid14__SHIFT 0x00000013 -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid13__SHIFT 0x00000014 -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid12__SHIFT 0x00000015 -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid11__SHIFT 0x00000016 -#define CPG_F32MeDebugBus_239_216__DebugBus1_qGprValid10__SHIFT 0x00000017 -#define CPG_F32MeDebugBus_239_216__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_263_240 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid9__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid8__SHIFT 0x00000001 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid7__SHIFT 0x00000002 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid6__SHIFT 0x00000003 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid5__SHIFT 0x00000004 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid4__SHIFT 0x00000005 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid3__SHIFT 0x00000006 -#define CPG_F32MeDebugBus_263_240__DebugBus1_qGprValid2__SHIFT 0x00000007 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid15__SHIFT 0x00000008 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid14__SHIFT 0x00000009 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid13__SHIFT 0x0000000a -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid12__SHIFT 0x0000000b -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid11__SHIFT 0x0000000c -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid10__SHIFT 0x0000000d -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid9__SHIFT 0x0000000e -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid8__SHIFT 0x0000000f -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid7__SHIFT 0x00000010 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid6__SHIFT 0x00000011 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid5__SHIFT 0x00000012 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid4__SHIFT 0x00000013 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid3__SHIFT 0x00000014 -#define CPG_F32MeDebugBus_263_240__DebugBus2_qGprValid2__SHIFT 0x00000015 -#define CPG_F32MeDebugBus_263_240__DebugBus3_qGprValid15__SHIFT 0x00000016 -#define CPG_F32MeDebugBus_263_240__DebugBus3_qGprValid14__SHIFT 0x00000017 -#define CPG_F32MeDebugBus_263_240__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_287_264 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid13__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid12__SHIFT 0x00000001 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid11__SHIFT 0x00000002 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid10__SHIFT 0x00000003 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid9__SHIFT 0x00000004 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid8__SHIFT 0x00000005 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid7__SHIFT 0x00000006 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid6__SHIFT 0x00000007 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid5__SHIFT 0x00000008 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid4__SHIFT 0x00000009 -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid3__SHIFT 0x0000000a -#define CPG_F32MeDebugBus_287_264__DebugBus3_qGprValid2__SHIFT 0x0000000b -#define CPG_F32MeDebugBus_287_264__qDecodeInstr_A_11_0__SHIFT 0x0000000c -#define CPG_F32MeDebugBus_287_264__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_311_288 -#define CPG_F32MeDebugBus_311_288__qDecodeInstr_A_31_12__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_311_288__qDecodeInstr_B_3_0__SHIFT 0x00000014 -#define CPG_F32MeDebugBus_311_288__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_335_312 -#define CPG_F32MeDebugBus_335_312__qDecodeInstr_B_27_4__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_335_312__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_359_336 -#define CPG_F32MeDebugBus_359_336__qDecodeInstr_B_31_28__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_359_336__qDecodeAddress_A_padded__SHIFT 0x00000004 -#define CPG_F32MeDebugBus_359_336__qDecodeAddress_B_padded_3_0__SHIFT 0x00000014 -#define CPG_F32MeDebugBus_359_336__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_383_360 -#define CPG_F32MeDebugBus_383_360__qDecodeAddress_B_padded_15_4__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_383_360__qAluIntUnitPntr_A__SHIFT 0x0000000c -#define CPG_F32MeDebugBus_383_360__AluIntUnitPntr_B__SHIFT 0x0000000f -#define CPG_F32MeDebugBus_383_360__qLdStrUnitPntr_A__SHIFT 0x00000012 -#define CPG_F32MeDebugBus_383_360__qLdStrUnitPntr_B__SHIFT 0x00000015 -#define CPG_F32MeDebugBus_383_360__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_407_384 -#define CPG_F32MeDebugBus_407_384__qDecodeInstrRts_A__SHIFT 0x00000000 -#define CPG_F32MeDebugBus_407_384__qDecodeInstrRts_B__SHIFT 0x00000001 -#define CPG_F32MeDebugBus_407_384__qJumpSourceRts__SHIFT 0x00000002 -#define CPG_F32MeDebugBus_407_384__qInstrEtsCnt_le_6__SHIFT 0x00000003 -#define CPG_F32MeDebugBus_407_384__Reserved1__SHIFT 0x00000004 -#define CPG_F32MeDebugBus_407_384__qThreadIdState__SHIFT 0x00000014 -#define CPG_F32MeDebugBus_407_384__Reserved0__SHIFT 0x00000018 - -// CPG_F32MeDebugBus_431_408 -#define CPG_F32MeDebugBus_431_408__Reserved0__SHIFT 0x00000000 - -// CPG_F32MeDebugBus_447_432 -#define CPG_F32MeDebugBus_447_432__Reserved0__SHIFT 0x00000000 - -// CPF_RbiuDebugIntf_23_0 -#define CPF_RbiuDebugIntf_23_0__GRBM_CP_reg_free__SHIFT 0x00000000 -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_send__SHIFT 0x00000001 -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_clken__SHIFT 0x00000002 -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_priv__SHIFT 0x00000003 -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_op__SHIFT 0x00000004 -#define CPF_RbiuDebugIntf_23_0__RdReturnValid__SHIFT 0x00000005 -#define CPF_RbiuDebugIntf_23_0__iGRBM_CP_reg_addr__SHIFT 0x00000006 -#define CPF_RbiuDebugIntf_23_0__Reserved0__SHIFT 0x00000016 - -// CPF_RbiuDebugIntf_47_24 -#define CPF_RbiuDebugIntf_47_24__iGRBM_CP_reg_data__SHIFT 0x00000000 -#define CPF_RbiuDebugIntf_47_24__RdReturnData__SHIFT 0x0000000c -#define CPF_RbiuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_SemaphoreDebugIntf -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_pipeid__SHIFT 0x00000000 -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_meid__SHIFT 0x00000002 -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_status__SHIFT 0x00000004 -#define CPF_SemaphoreDebugIntf__qSEM_CP_resp_send__SHIFT 0x00000006 -#define CPF_SemaphoreDebugIntf__Reserved0__SHIFT 0x00000007 - -// CPF_Rbiu_Semaphore_DebugBus -#define CPF_Rbiu_Semaphore_DebugBus__Reserved2__SHIFT 0x00000000 -#define CPF_Rbiu_Semaphore_DebugBus__qReadCycleCount__SHIFT 0x0000000a -#define CPF_Rbiu_Semaphore_DebugBus__qReadState__SHIFT 0x0000000d -#define CPF_Rbiu_Semaphore_DebugBus__qWriteHold__SHIFT 0x0000000e -#define CPF_Rbiu_Semaphore_DebugBus__qFreeCountUnderflow__SHIFT 0x0000000f -#define CPF_Rbiu_Semaphore_DebugBus__qFreeCountOverflow__SHIFT 0x00000010 -#define CPF_Rbiu_Semaphore_DebugBus__qFreeCount_neq_0__SHIFT 0x00000011 -#define CPF_Rbiu_Semaphore_DebugBus__qGRBM_CP_reg_send__SHIFT 0x00000012 -#define CPF_Rbiu_Semaphore_DebugBus__GrbmCpFifoFull__SHIFT 0x00000013 -#define CPF_Rbiu_Semaphore_DebugBus__GrbmCpFifoEmpty__SHIFT 0x00000014 -#define CPF_Rbiu_Semaphore_DebugBus__Reserved1__SHIFT 0x00000015 -#define CPF_Rbiu_Semaphore_DebugBus__iHQD1_TCIU_rdreq_rts__SHIFT 0x00000016 -#define CPF_Rbiu_Semaphore_DebugBus__iCSF_TCIU_rdreq_rts__SHIFT 0x00000017 -#define CPF_Rbiu_Semaphore_DebugBus__Reserved0__SHIFT 0x00000018 - -// CPF_TciuDebugBus_47_24 -#define CPF_TciuDebugBus_47_24__XferId__SHIFT 0x00000000 -#define CPF_TciuDebugBus_47_24__qDmaTransCnt__SHIFT 0x00000003 -#define CPF_TciuDebugBus_47_24__qHqd2TransCnt__SHIFT 0x00000007 -#define CPF_TciuDebugBus_47_24__qHqd1TransCnt__SHIFT 0x0000000b -#define CPF_TciuDebugBus_47_24__qCsfTransCnt__SHIFT 0x0000000f -#define CPF_TciuDebugBus_47_24__DmaRts__SHIFT 0x00000013 -#define CPF_TciuDebugBus_47_24__Hqd2Rts__SHIFT 0x00000014 -#define CPF_TciuDebugBus_47_24__Hqd1Rts__SHIFT 0x00000015 -#define CPF_TciuDebugBus_47_24__CsfRts__SHIFT 0x00000016 -#define CPF_TciuDebugBus_47_24__iHQD2_TCIU_rdreq_rts__SHIFT 0x00000017 -#define CPF_TciuDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_TciuDebugBus_23_0 -#define CPF_TciuDebugBus_23_0__CpfTciuPostArbFifo_Empty__SHIFT 0x00000000 -#define CPF_TciuDebugBus_23_0__CpfTciuPostArbFifo_Full__SHIFT 0x00000001 -#define CPF_TciuDebugBus_23_0__CpfTcOutCnt__SHIFT 0x00000002 -#define CPF_TciuDebugBus_23_0__CpfTcCnt__SHIFT 0x0000000c -#define CPF_TciuDebugBus_23_0__CpgTciuRdReqFifo_Empty__SHIFT 0x00000011 -#define CPF_TciuDebugBus_23_0__CpgTciuRdReqFifo_Full__SHIFT 0x00000012 -#define CPF_TciuDebugBus_23_0__TagBusy__SHIFT 0x00000013 -#define CPF_TciuDebugBus_23_0__oTciuBusy__SHIFT 0x00000014 -#define CPF_TciuDebugBus_23_0__Aligned_TcRetXferCycle__SHIFT 0x00000015 -#define CPF_TciuDebugBus_23_0__TcClkenWarmupRdy__SHIFT 0x00000016 -#define CPF_TciuDebugBus_23_0__TcRdy__SHIFT 0x00000017 -#define CPF_TciuDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_TciuDebugIntf_23_0 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdnfo_stall__SHIFT 0x00000000 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_send__SHIFT 0x00000001 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_exe__SHIFT 0x00000002 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_physical__SHIFT 0x00000003 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_snoop__SHIFT 0x00000004 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_policy__SHIFT 0x00000005 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_mtype__SHIFT 0x00000006 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_vmid__SHIFT 0x00000008 -#define CPF_TciuDebugIntf_23_0__CPF_TC_rdreq_tag_11_0__SHIFT 0x0000000c -#define CPF_TciuDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_TciuDebugIntf_47_24 -#define CPF_TciuDebugIntf_47_24__CPF_TC_rdreq_tag_15_12__SHIFT 0x00000000 -#define CPF_TciuDebugIntf_47_24__CPF_TC_rdreq_addr_19_0__SHIFT 0x00000004 -#define CPF_TciuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_TciuDebugIntf_71_48 -#define CPF_TciuDebugIntf_71_48__CPF_TC_rdreq_addr_41_20__SHIFT 0x00000000 -#define CPF_TciuDebugIntf_71_48__Aligned_TC_CPF_rdret_valid__SHIFT 0x00000016 -#define CPF_TciuDebugIntf_71_48__Aligned_TC_CPF_rdret_fed__SHIFT 0x00000017 -#define CPF_TciuDebugIntf_71_48__Reserved0__SHIFT 0x00000018 - -// CPF_TciuDebugIntf_95_72 -#define CPF_TciuDebugIntf_95_72__Aligned_TC_CPF_rdret_tag__SHIFT 0x00000000 -#define CPF_TciuDebugIntf_95_72__Aligned_TC_CPF_rdret_subdata_7_0__SHIFT 0x00000010 -#define CPF_TciuDebugIntf_95_72__Reserved0__SHIFT 0x00000018 - -// CPF_TciuDebugIntf_119_96 -#define CPF_TciuDebugIntf_119_96__Aligned_TC_CPF_rdret_subdata_31_8__SHIFT 0x00000000 -#define CPF_TciuDebugIntf_119_96__Reserved0__SHIFT 0x00000018 - -// CPF_UtcL2iuDebugIntf_23_0 -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_tag__SHIFT 0x00000000 -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_nack__SHIFT 0x00000007 -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_mtype__SHIFT 0x00000009 -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_memlog__SHIFT 0x0000000b -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_no_pte__SHIFT 0x0000000c -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_pte_tmz__SHIFT 0x0000000d -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_spa__SHIFT 0x0000000e -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_io_steer__SHIFT 0x0000000f -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_fragment_size_5_0__SHIFT 0x00000010 -#define CPF_UtcL2iuDebugIntf_23_0__iUTCL2_CPF_ret_perms_granted_1_0__SHIFT 0x00000016 -#define CPF_UtcL2iuDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_UtcL2iuDebugIntf_47_24 -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_perms_granted_2__SHIFT 0x00000000 -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_perms_requested_2_0__SHIFT 0x00000001 -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_snoop__SHIFT 0x00000004 -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_valid__SHIFT 0x00000005 -#define CPF_UtcL2iuDebugIntf_47_24__iUTCL2_CPF_ret_perms_requested_17_0__SHIFT 0x00000006 -#define CPF_UtcL2iuDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_UtcL2iuDebugIntf_71_48 -#define CPF_UtcL2iuDebugIntf_71_48__iUTCL2_CPF_ret_perms_requested_35_18__SHIFT 0x00000000 -#define CPF_UtcL2iuDebugIntf_71_48__CPF_UTCL2_req_data_5_0__SHIFT 0x00000012 -#define CPF_UtcL2iuDebugIntf_71_48__Reserved0__SHIFT 0x00000018 - -// CPF_UtcL2iuDebugIntf_95_72 -#define CPF_UtcL2iuDebugIntf_95_72__CPF_UTCL2_req_data_15_6__SHIFT 0x00000000 -#define CPF_UtcL2iuDebugIntf_95_72__qCPF_UTCL2_req_free__SHIFT 0x0000000a -#define CPF_UtcL2iuDebugIntf_95_72__CPF_UTCL2_req_send__SHIFT 0x0000000b -#define CPF_UtcL2iuDebugIntf_95_72__qUtcL2XferCycle_eq_0__SHIFT 0x0000000c -#define CPF_UtcL2iuDebugIntf_95_72__Reserved0__SHIFT 0x00000012 - -// CPF_HqdQueueDebugBus_23_0 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_23_0__HqdQueueDebugBus_0_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueueDebugBus_47_24 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_47_24__HqdQueueDebugBus_1_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueueDebugBus_71_48 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_71_48__HqdQueueDebugBus_2_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueueDebugBus_95_72 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_95_72__HqdQueueDebugBus_3_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueueDebugBus_119_96 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_119_96__HqdQueueDebugBus_4_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueueDebugBus_143_120 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_143_120__HqdQueueDebugBus_5_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_143_120__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueueDebugBus_167_144 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_167_144__HqdQueueDebugBus_6_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_167_144__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueueDebugBus_191_168 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_0_qImmedPend__SHIFT 0x00000000 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_0_qSemEccMessageRts__SHIFT 0x00000001 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_0_qTimerWaitMessageRts__SHIFT 0x00000002 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_1_qImmedPend__SHIFT 0x00000003 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_1_qSemEccMessageRts__SHIFT 0x00000004 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_1_qTimerWaitMessageRts__SHIFT 0x00000005 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_2_qImmedPend__SHIFT 0x00000006 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_2_qSemEccMessageRts__SHIFT 0x00000007 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_2_qTimerWaitMessageRts__SHIFT 0x00000008 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_3_qImmedPend__SHIFT 0x00000009 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_3_qSemEccMessageRts__SHIFT 0x0000000a -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_3_qTimerWaitMessageRts__SHIFT 0x0000000b -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_4_qImmedPend__SHIFT 0x0000000c -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_4_qSemEccMessageRts__SHIFT 0x0000000d -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_4_qTimerWaitMessageRts__SHIFT 0x0000000e -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_5_qImmedPend__SHIFT 0x0000000f -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_5_qSemEccMessageRts__SHIFT 0x00000010 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_5_qTimerWaitMessageRts__SHIFT 0x00000011 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_6_qImmedPend__SHIFT 0x00000012 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_6_qSemEccMessageRts__SHIFT 0x00000013 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_6_qTimerWaitMessageRts__SHIFT 0x00000014 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_7_qImmedPend__SHIFT 0x00000015 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_7_qSemEccMessageRts__SHIFT 0x00000016 -#define CPF_HqdQueueDebugBus_191_168__HqdQueueDebugBus_7_7_qTimerWaitMessageRts__SHIFT 0x00000017 -#define CPF_HqdQueueDebugBus_191_168__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_23_0 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqReadPntr_neq_qPqWritePntr__SHIFT 0x00000001 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqWritePntr_le_qPqReadPntr__SHIFT 0x00000002 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_23_0__QueueFetcher_0_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_47_24 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqReadPntr_neq_qPqWritePntr__SHIFT \ - 0x00000001 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqWritePntr_le_qPqReadPntr__SHIFT 0x00000002 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_47_24__QueueFetcher_1_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_71_48 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqReadPntr_neq_qPqWritePntr__SHIFT \ - 0x00000001 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqWritePntr_le_qPqReadPntr__SHIFT 0x00000002 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_71_48__QueueFetcher_2_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_95_72 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqReadPntr_neq_qPqWritePntr__SHIFT \ - 0x00000001 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqWritePntr_le_qPqReadPntr__SHIFT 0x00000002 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_95_72__QueueFetcher_3_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_119_96 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqReadPntr_neq_qPqWritePntr__SHIFT \ - 0x00000001 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqWritePntr_le_qPqReadPntr__SHIFT \ - 0x00000002 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_119_96__QueueFetcher_4_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_143_120 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqReadPntr_neq_qPqWritePntr__SHIFT \ - 0x00000001 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqWritePntr_le_qPqReadPntr__SHIFT \ - 0x00000002 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_143_120__QueueFetcher_5_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_143_120__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_167_144 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqReadPntr_neq_qPqWritePntr__SHIFT \ - 0x00000001 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqWritePntr_le_qPqReadPntr__SHIFT \ - 0x00000002 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_167_144__QueueFetcher_6_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_167_144__Reserved0__SHIFT 0x00000018 - -// CPF_QueueFetcherDebugBus_191_168 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqQueueSize_neq_0__SHIFT 0x00000000 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqReadPntr_neq_qPqWritePntr__SHIFT \ - 0x00000001 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqWritePntr_le_qPqReadPntr__SHIFT \ - 0x00000002 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_EopqQueueSize_neq_0__SHIFT 0x00000003 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_IqFetcherFifoEmpty__SHIFT 0x00000004 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_IqFetcherFifoFull__SHIFT 0x00000005 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIqBufSize_eq_0__SHIFT 0x00000006 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIbBufSize_neq_0__SHIFT 0x00000007 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedIbRdPntr_neq_qPreCsmdIbRdPntr__SHIFT \ - 0x00000008 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPreCsmdIbBufSize_eq_0__SHIFT 0x00000009 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedIbBufSize_neq_0__SHIFT 0x0000000a -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqValidReqState__SHIFT 0x0000000b -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIbValidReqState__SHIFT 0x0000000c -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIqValidReqState__SHIFT 0x0000000d -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qEopValidReqState__SHIFT 0x0000000e -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedRdPntr_neq_qPqWritePntr__SHIFT \ - 0x0000000f -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qConsumedRdPntr_eq_qHostRdPntr__SHIFT \ - 0x00000010 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqEmpty__SHIFT 0x00000011 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqRoqAvailCnt_neq_qPqRoqDepth_000__SHIFT \ - 0x00000012 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIbRoqAvailCnt_neq_qIbRoqDepth_000__SHIFT \ - 0x00000013 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qIqRoqAvailCnt_neq_qIqRoqDepth_000__SHIFT \ - 0x00000014 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qEopRoqAvailCnt_neq_qEopRoqDepth_000__SHIFT \ - 0x00000015 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqRdPntrReportRts__SHIFT 0x00000016 -#define CPF_QueueFetcherDebugBus_191_168__QueueFetcher_7_qPqRptrTagCount_neq_0__SHIFT 0x00000017 -#define CPF_QueueFetcherDebugBus_191_168__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueMngrDebugBus_23_0 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable0__SHIFT 0x00000000 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable1__SHIFT 0x00000001 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable2__SHIFT 0x00000002 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable3__SHIFT 0x00000003 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable4__SHIFT 0x00000004 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable5__SHIFT 0x00000005 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable6__SHIFT 0x00000006 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueAvailable7__SHIFT 0x00000007 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qMappedQueue__SHIFT 0x00000008 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_0_qQueueState__SHIFT 0x0000000b -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable0__SHIFT 0x00000010 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable1__SHIFT 0x00000011 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable2__SHIFT 0x00000012 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable3__SHIFT 0x00000013 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable4__SHIFT 0x00000014 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable5__SHIFT 0x00000015 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable6__SHIFT 0x00000016 -#define CPF_HqdQueMngrDebugBus_23_0__HqdQueMngr_1_qQueueAvailable7__SHIFT 0x00000017 -#define CPF_HqdQueMngrDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueMngrDebugBus_47_24 -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_1_qMappedQueue__SHIFT 0x00000000 -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_1_qQueueState__SHIFT 0x00000003 -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable0__SHIFT 0x00000008 -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable1__SHIFT 0x00000009 -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable2__SHIFT 0x0000000a -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable3__SHIFT 0x0000000b -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable4__SHIFT 0x0000000c -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable5__SHIFT 0x0000000d -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable6__SHIFT 0x0000000e -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueAvailable7__SHIFT 0x0000000f -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qMappedQueue__SHIFT 0x00000010 -#define CPF_HqdQueMngrDebugBus_47_24__HqdQueMngr_2_qQueueState__SHIFT 0x00000013 -#define CPF_HqdQueMngrDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueMngrDebugBus_71_48 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable0__SHIFT 0x00000000 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable1__SHIFT 0x00000001 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable2__SHIFT 0x00000002 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable3__SHIFT 0x00000003 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable4__SHIFT 0x00000004 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable5__SHIFT 0x00000005 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable6__SHIFT 0x00000006 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueAvailable7__SHIFT 0x00000007 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qMappedQueue__SHIFT 0x00000008 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_3_qQueueState__SHIFT 0x0000000b -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable0__SHIFT 0x00000010 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable1__SHIFT 0x00000011 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable2__SHIFT 0x00000012 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable3__SHIFT 0x00000013 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable4__SHIFT 0x00000014 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable5__SHIFT 0x00000015 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable6__SHIFT 0x00000016 -#define CPF_HqdQueMngrDebugBus_71_48__HqdQueMngr_4_qQueueAvailable7__SHIFT 0x00000017 -#define CPF_HqdQueMngrDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueMngrDebugBus_95_72 -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_4_qMappedQueue__SHIFT 0x00000000 -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_4_qQueueState__SHIFT 0x00000003 -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable0__SHIFT 0x00000008 -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable1__SHIFT 0x00000009 -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable2__SHIFT 0x0000000a -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable3__SHIFT 0x0000000b -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable4__SHIFT 0x0000000c -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable5__SHIFT 0x0000000d -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable6__SHIFT 0x0000000e -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueAvailable7__SHIFT 0x0000000f -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qMappedQueue__SHIFT 0x00000010 -#define CPF_HqdQueMngrDebugBus_95_72__HqdQueMngr_5_qQueueState__SHIFT 0x00000013 -#define CPF_HqdQueMngrDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueMngrDebugBus_119_96 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable0__SHIFT 0x00000000 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable1__SHIFT 0x00000001 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable2__SHIFT 0x00000002 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable3__SHIFT 0x00000003 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable4__SHIFT 0x00000004 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable5__SHIFT 0x00000005 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable6__SHIFT 0x00000006 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueAvailable7__SHIFT 0x00000007 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qMappedQueue__SHIFT 0x00000008 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_6_qQueueState__SHIFT 0x0000000b -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable0__SHIFT 0x00000010 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable1__SHIFT 0x00000011 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable2__SHIFT 0x00000012 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable3__SHIFT 0x00000013 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable4__SHIFT 0x00000014 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable5__SHIFT 0x00000015 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable6__SHIFT 0x00000016 -#define CPF_HqdQueMngrDebugBus_119_96__HqdQueMngr_7_qQueueAvailable7__SHIFT 0x00000017 -#define CPF_HqdQueMngrDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPF_HqdQueMngrDebugBus_127_120 -#define CPF_HqdQueMngrDebugBus_127_120__HqdQueMngr_7_qMappedQueue__SHIFT 0x00000000 -#define CPF_HqdQueMngrDebugBus_127_120__HqdQueMngr_7_qQueueState__SHIFT 0x00000003 -#define CPF_HqdQueMngrDebugBus_127_120__HqdArbitrateDebugBus_11_0__SHIFT 0x00000008 -#define CPF_HqdQueMngrDebugBus_127_120__Reserved0__SHIFT 0x00000014 - -// CPF_HqdRoqCmdQueDebugBus_23_0 -#define CPF_HqdRoqCmdQueDebugBus_23_0__Mec1_HqdRoqThreadDebugBus0__SHIFT 0x00000000 -#define CPF_HqdRoqCmdQueDebugBus_23_0__Mec1_HqdRoqThreadDebugBus1__SHIFT 0x0000000c -#define CPF_HqdRoqCmdQueDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_HqdRoqCmdQueDebugBus_47_24 -#define CPF_HqdRoqCmdQueDebugBus_47_24__Mec1_HqdRoqThreadDebugBus2__SHIFT 0x00000000 -#define CPF_HqdRoqCmdQueDebugBus_47_24__Mec1_HqdRoqThreadDebugBus3__SHIFT 0x0000000c -#define CPF_HqdRoqCmdQueDebugBus_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_HqdRoqCmdQueDebugBus_71_48 -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree0__SHIFT 0x00000000 -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree1__SHIFT 0x00000004 -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree2__SHIFT 0x00000008 -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueFree3__SHIFT 0x0000000c -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueSend0__SHIFT 0x00000010 -#define CPF_HqdRoqCmdQueDebugBus_71_48__Mec1_qRoQueueSend1__SHIFT 0x00000014 -#define CPF_HqdRoqCmdQueDebugBus_71_48__Reserved0__SHIFT 0x00000018 - -// CPF_HqdRoqCmdQueDebugBus_95_72 -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec1_HqdRoqThreadDebugBusqRoQueueSend2__SHIFT 0x00000000 -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec1_HqdRoqThreadDebugBusqRoQueueSend3__SHIFT 0x00000004 -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec1_HqdRoqThreadDebugBusPipeSelect__SHIFT 0x00000008 -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec2_HqdRoqThreadDebugBus0__SHIFT 0x0000000a -#define CPF_HqdRoqCmdQueDebugBus_95_72__Mec2_HqdRoqThreadDebugBus1_1_0__SHIFT 0x00000016 -#define CPF_HqdRoqCmdQueDebugBus_95_72__Reserved0__SHIFT 0x00000018 - -// CPF_HqdRoqCmdQueDebugBus_119_96 -#define CPF_HqdRoqCmdQueDebugBus_119_96__Mec2_HqdRoqThreadDebugBus1_11_2__SHIFT 0x00000000 -#define CPF_HqdRoqCmdQueDebugBus_119_96__Mec2_HqdRoqThreadDebugBus2__SHIFT 0x0000000a -#define CPF_HqdRoqCmdQueDebugBus_119_96__Mec2_HqdRoqThreadDebugBus3_1_0__SHIFT 0x00000016 -#define CPF_HqdRoqCmdQueDebugBus_119_96__Reserved0__SHIFT 0x00000018 - -// CPF_HqdRoqCmdQueDebugBus_143_120 -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_HqdRoqThreadDebugBus3_11_2__SHIFT 0x00000000 -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree0__SHIFT 0x0000000a -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree1__SHIFT 0x0000000e -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree2__SHIFT 0x00000012 -#define CPF_HqdRoqCmdQueDebugBus_143_120__Mec2_qRoQueueFree3_1_0__SHIFT 0x00000016 -#define CPF_HqdRoqCmdQueDebugBus_143_120__Reserved0__SHIFT 0x00000018 - -// CPF_HqdRoqCmdQueDebugBus_163_144 -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_qRoQueueFree3_3_2__SHIFT 0x00000000 -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_qRoQueueSend0__SHIFT 0x00000002 -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_qRoQueueSend1__SHIFT 0x00000006 -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_HqdRoqThreadDebugBusqRoQueueSend2__SHIFT 0x0000000a -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_HqdRoqThreadDebugBusqRoQueueSend3__SHIFT 0x0000000e -#define CPF_HqdRoqCmdQueDebugBus_163_144__Mec2_HqdRoqThreadDebugBusPipeSelect__SHIFT 0x00000012 -#define CPF_HqdRoqCmdQueDebugBus_163_144__Reserved0__SHIFT 0x00000014 - -// CPF_HqdRoqAlignDebugBus -#define CPF_HqdRoqAlignDebugBus__Mec1_qDuplicateMaskError__SHIFT 0x00000000 -#define CPF_HqdRoqAlignDebugBus__Mec1_qBufferDeallocCount_neq_0__SHIFT 0x00000001 -#define CPF_HqdRoqAlignDebugBus__Mec1_ScratchMaskRts__SHIFT 0x00000002 -#define CPF_HqdRoqAlignDebugBus__Mec1_BufOutEmpty__SHIFT 0x00000003 -#define CPF_HqdRoqAlignDebugBus__Mec1_BufOutFull__SHIFT 0x00000004 -#define CPF_HqdRoqAlignDebugBus__Mec1_BufferEmpty__SHIFT 0x00000005 -#define CPF_HqdRoqAlignDebugBus__Mec1_BufferFull__SHIFT 0x00000006 -#define CPF_HqdRoqAlignDebugBus__Mec1_qBufferOverFlowError__SHIFT 0x00000007 -#define CPF_HqdRoqAlignDebugBus__Mec1_qRdRetSendCnt_neq_0__SHIFT 0x00000008 -#define CPF_HqdRoqAlignDebugBus__Mec2_qDuplicateMaskError__SHIFT 0x00000009 -#define CPF_HqdRoqAlignDebugBus__Mec2_qBufferDeallocCount_neq_0__SHIFT 0x0000000a -#define CPF_HqdRoqAlignDebugBus__Mec2_ScratchMaskRts__SHIFT 0x0000000b -#define CPF_HqdRoqAlignDebugBus__Mec2_BufOutEmpty__SHIFT 0x0000000c -#define CPF_HqdRoqAlignDebugBus__Mec2_BufOutFull__SHIFT 0x0000000d -#define CPF_HqdRoqAlignDebugBus__Mec2_BufferEmpty__SHIFT 0x0000000e -#define CPF_HqdRoqAlignDebugBus__Mec2_BufferFull__SHIFT 0x0000000f -#define CPF_HqdRoqAlignDebugBus__Mec2_qBufferOverFlowError__SHIFT 0x00000010 -#define CPF_HqdRoqAlignDebugBus__Mec2_qRdRetSendCnt_neq_0__SHIFT 0x00000011 -#define CPF_HqdRoqAlignDebugBus__Reserved0__SHIFT 0x00000012 - -// CPF_Roq_StQueue_Align_DebugBus -#define CPF_Roq_StQueue_Align_DebugBus__qDuplicateMaskError__SHIFT 0x00000000 -#define CPF_Roq_StQueue_Align_DebugBus__qBufferDeallocCount_neq_0__SHIFT 0x00000001 -#define CPF_Roq_StQueue_Align_DebugBus__ScratchMaskRts__SHIFT 0x00000002 -#define CPF_Roq_StQueue_Align_DebugBus__BufOutEmpty__SHIFT 0x00000003 -#define CPF_Roq_StQueue_Align_DebugBus__BufOutFull__SHIFT 0x00000004 -#define CPF_Roq_StQueue_Align_DebugBus__BufferEmpty__SHIFT 0x00000005 -#define CPF_Roq_StQueue_Align_DebugBus__BufferFull__SHIFT 0x00000006 -#define CPF_Roq_StQueue_Align_DebugBus__qBufferOverFlowError__SHIFT 0x00000007 -#define CPF_Roq_StQueue_Align_DebugBus__qRdRetSendCnt_neq_0__SHIFT 0x00000008 -#define CPF_Roq_StQueue_Align_DebugBus__Reserved1__SHIFT 0x00000009 -#define CPF_Roq_StQueue_Align_DebugBus__qStqAvailCnt_R2_neq_qStqMaxCnt_R2__SHIFT 0x00000010 -#define CPF_Roq_StQueue_Align_DebugBus__qStqAvailCnt_R1_neq_qStqMaxCnt_R1__SHIFT 0x00000011 -#define CPF_Roq_StQueue_Align_DebugBus__qStqAvailCnt_R0_neq_qStqMaxCnt_R0__SHIFT 0x00000012 -#define CPF_Roq_StQueue_Align_DebugBus__qRingIdState__SHIFT 0x00000013 -#define CPF_Roq_StQueue_Align_DebugBus__StqRts_R2__SHIFT 0x00000015 -#define CPF_Roq_StQueue_Align_DebugBus__StqRts_R1__SHIFT 0x00000016 -#define CPF_Roq_StQueue_Align_DebugBus__StqRts_R0__SHIFT 0x00000017 -#define CPF_Roq_StQueue_Align_DebugBus__Reserved0__SHIFT 0x00000018 - -// CPF_RoqCmdQueueDebugBus_23_0 -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_RealAvailCntQueue_R2_neq_qI2_MaxCntQueue_R2__SHIFT \ - 0x00000000 -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_RealAvailCntQueue_R1_neq_qI2_MaxCntQueue_R1__SHIFT \ - 0x00000001 -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_RealAvailCntQueue_R0_neq_qI2_MaxCntQueue_R0__SHIFT \ - 0x00000002 -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_RealAvailCntQueue_R2_neq_qI1_MaxCntQueue_R2__SHIFT \ - 0x00000003 -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_RealAvailCntQueue_R1_neq_qI1_MaxCntQueue_R1__SHIFT \ - 0x00000004 -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_RealAvailCntQueue_R0_neq_qI1_MaxCntQueue_R0__SHIFT \ - 0x00000005 -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_RealAvailCntQueue_R2_neq_qRb_MaxCntQueue_R2__SHIFT \ - 0x00000006 -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_RealAvailCntQueue_R1_neq_qRb_MaxCntQueue_R1__SHIFT \ - 0x00000007 -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_RealAvailCntQueue_R0_neq_qRb_MaxCntQueue_R0__SHIFT \ - 0x00000008 -#define CPF_RoqCmdQueueDebugBus_23_0__Reserved1__SHIFT 0x00000009 -#define CPF_RoqCmdQueueDebugBus_23_0__qRingIdState__SHIFT 0x0000000f -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_SlipCntQueue_R2_neq_0__SHIFT 0x00000011 -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_SlipCntQueue_R1_neq_0__SHIFT 0x00000012 -#define CPF_RoqCmdQueueDebugBus_23_0__qI2_SlipCntQueue_R0_neq_0__SHIFT 0x00000013 -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_SlipCntQueue_R2_neq_0__SHIFT 0x00000014 -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_SlipCntQueue_R1_neq_0__SHIFT 0x00000015 -#define CPF_RoqCmdQueueDebugBus_23_0__qI1_SlipCntQueue_R0_neq_0__SHIFT 0x00000016 -#define CPF_RoqCmdQueueDebugBus_23_0__qRb_SlipCntQueue_R2_neq_0__SHIFT 0x00000017 -#define CPF_RoqCmdQueueDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_RoqCmdQueueDebugBus_47_24 -#define CPF_RoqCmdQueueDebugBus_47_24__qRb_SlipCntQueue_R1_neq_0__SHIFT 0x00000000 -#define CPF_RoqCmdQueueDebugBus_47_24__qRb_SlipCntQueue_R0_neq_0__SHIFT 0x00000001 -#define CPF_RoqCmdQueueDebugBus_47_24__I2_QueueRts_R2__SHIFT 0x00000002 -#define CPF_RoqCmdQueueDebugBus_47_24__I2_QueueRts_R1__SHIFT 0x00000003 -#define CPF_RoqCmdQueueDebugBus_47_24__I2_QueueRts_R0__SHIFT 0x00000004 -#define CPF_RoqCmdQueueDebugBus_47_24__I1_QueueRts_R2__SHIFT 0x00000005 -#define CPF_RoqCmdQueueDebugBus_47_24__I1_QueueRts_R1__SHIFT 0x00000006 -#define CPF_RoqCmdQueueDebugBus_47_24__I1_QueueRts_R0__SHIFT 0x00000007 -#define CPF_RoqCmdQueueDebugBus_47_24__Rb_QueueRts_R2__SHIFT 0x00000008 -#define CPF_RoqCmdQueueDebugBus_47_24__Rb_QueueRts_R1__SHIFT 0x00000009 -#define CPF_RoqCmdQueueDebugBus_47_24__Rb_QueueRts_R0__SHIFT 0x0000000a -#define CPF_RoqCmdQueueDebugBus_47_24__Reserved0__SHIFT 0x0000000b - -// CPF_RoqCnstQueueDebugBus_23_0 -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_RealAvailCntQueue_R2_neq_qI2_MaxCntQueue_R2__SHIFT \ - 0x00000000 -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_RealAvailCntQueue_R1_neq_qI2_MaxCntQueue_R1__SHIFT \ - 0x00000001 -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_RealAvailCntQueue_R0_neq_qI2_MaxCntQueue_R0__SHIFT \ - 0x00000002 -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_RealAvailCntQueue_R2_neq_qI1_MaxCntQueue_R2__SHIFT \ - 0x00000003 -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_RealAvailCntQueue_R1_neq_qI1_MaxCntQueue_R1__SHIFT \ - 0x00000004 -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_RealAvailCntQueue_R0_neq_qI1_MaxCntQueue_R0__SHIFT \ - 0x00000005 -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_RealAvailCntQueue_R2_neq_qRb_MaxCntQueue_R2__SHIFT \ - 0x00000006 -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_RealAvailCntQueue_R1_neq_qRb_MaxCntQueue_R1__SHIFT \ - 0x00000007 -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_RealAvailCntQueue_R0_neq_qRb_MaxCntQueue_R0__SHIFT \ - 0x00000008 -#define CPF_RoqCnstQueueDebugBus_23_0__Reserved1__SHIFT 0x00000009 -#define CPF_RoqCnstQueueDebugBus_23_0__qRingIdState__SHIFT 0x0000000f -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_SlipCntQueue_R2_neq_0__SHIFT 0x00000011 -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_SlipCntQueue_R1_neq_0__SHIFT 0x00000012 -#define CPF_RoqCnstQueueDebugBus_23_0__qI2_SlipCntQueue_R0_neq_0__SHIFT 0x00000013 -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_SlipCntQueue_R2_neq_0__SHIFT 0x00000014 -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_SlipCntQueue_R1_neq_0__SHIFT 0x00000015 -#define CPF_RoqCnstQueueDebugBus_23_0__qI1_SlipCntQueue_R0_neq_0__SHIFT 0x00000016 -#define CPF_RoqCnstQueueDebugBus_23_0__qRb_SlipCntQueue_R2_neq_0__SHIFT 0x00000017 -#define CPF_RoqCnstQueueDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_RoqCnstQueueDebugBus_47_24 -#define CPF_RoqCnstQueueDebugBus_47_24__qRb_SlipCntQueue_R1_neq_0__SHIFT 0x00000000 -#define CPF_RoqCnstQueueDebugBus_47_24__qRb_SlipCntQueue_R0_neq_0__SHIFT 0x00000001 -#define CPF_RoqCnstQueueDebugBus_47_24__I2_QueueRts_R2__SHIFT 0x00000002 -#define CPF_RoqCnstQueueDebugBus_47_24__I2_QueueRts_R1__SHIFT 0x00000003 -#define CPF_RoqCnstQueueDebugBus_47_24__I2_QueueRts_R0__SHIFT 0x00000004 -#define CPF_RoqCnstQueueDebugBus_47_24__I1_QueueRts_R2__SHIFT 0x00000005 -#define CPF_RoqCnstQueueDebugBus_47_24__I1_QueueRts_R1__SHIFT 0x00000006 -#define CPF_RoqCnstQueueDebugBus_47_24__I1_QueueRts_R0__SHIFT 0x00000007 -#define CPF_RoqCnstQueueDebugBus_47_24__Rb_QueueRts_R2__SHIFT 0x00000008 -#define CPF_RoqCnstQueueDebugBus_47_24__Rb_QueueRts_R1__SHIFT 0x00000009 -#define CPF_RoqCnstQueueDebugBus_47_24__Rb_QueueRts_R0__SHIFT 0x0000000a -#define CPF_RoqCnstQueueDebugBus_47_24__Reserved0__SHIFT 0x0000000b - -// CPF_WrPntrPollDebugBus_31_8 -#define CPF_WrPntrPollDebugBus_31_8__qMeId__SHIFT 0x00000000 -#define CPF_WrPntrPollDebugBus_31_8__startPollAll__SHIFT 0x00000001 -#define CPF_WrPntrPollDebugBus_31_8__queueActive__SHIFT 0x00000002 -#define CPF_WrPntrPollDebugBus_31_8__qWptrPollBusy__SHIFT 0x00000003 -#define CPF_WrPntrPollDebugBus_31_8__oWPP_TC_rdreq_rts__SHIFT 0x00000004 -#define CPF_WrPntrPollDebugBus_31_8__iWPP_TC_rdreq_rtr__SHIFT 0x00000005 -#define CPF_WrPntrPollDebugBus_31_8__IncrWptrPollCount__SHIFT 0x00000006 -#define CPF_WrPntrPollDebugBus_31_8__TcWppTarget__SHIFT 0x00000007 -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollValid__SHIFT 0x00000008 -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollMeId__SHIFT 0x00000009 -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollPipeId__SHIFT 0x0000000b -#define CPF_WrPntrPollDebugBus_31_8__qWrPntrPollQueueId__SHIFT 0x0000000d -#define CPF_WrPntrPollDebugBus_31_8__qWppFifoState__SHIFT 0x00000010 -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoEmpty__SHIFT 0x00000012 -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoFull__SHIFT 0x00000013 -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoRdEn__SHIFT 0x00000014 -#define CPF_WrPntrPollDebugBus_31_8__WptrPollFifoWrEn__SHIFT 0x00000015 -#define CPF_WrPntrPollDebugBus_31_8__qWptrPollOutstandingTagCnt_neq_1ff__SHIFT 0x00000016 -#define CPF_WrPntrPollDebugBus_31_8__qWptrPollOutstandingTagCnt_neq_0__SHIFT 0x00000017 -#define CPF_WrPntrPollDebugBus_31_8__Reserved0__SHIFT 0x00000018 - -// CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24 -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qInterruptVmid_3__SHIFT 0x00000000 -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__Reserved1__SHIFT 0x00000001 -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qWptrPollState__SHIFT 0x00000008 -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qQueueId__SHIFT 0x0000000b -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__qPipeId__SHIFT 0x0000000e -#define CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24__Reserved0__SHIFT 0x00000010 - -// CPF_InterruptDebugBus_23_0 -#define CPF_InterruptDebugBus_23_0__qCP_RLC_intrequest_id4__SHIFT 0x00000000 -#define CPF_InterruptDebugBus_23_0__qInterruptRequestActive__SHIFT 0x00000008 -#define CPF_InterruptDebugBus_23_0__qInterruptRequestId__SHIFT 0x00000009 -#define CPF_InterruptDebugBus_23_0__qInterruptQueueId__SHIFT 0x0000000e -#define CPF_InterruptDebugBus_23_0__qInterruptRingId__SHIFT 0x00000011 -#define CPF_InterruptDebugBus_23_0__qInterruptMeId__SHIFT 0x00000013 -#define CPF_InterruptDebugBus_23_0__qInterruptVmid_2_0__SHIFT 0x00000015 -#define CPF_InterruptDebugBus_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_InterruptDebugIntf_23_0 -#define CPF_InterruptDebugIntf_23_0__qRLC_CP_intresponse_status__SHIFT 0x00000000 -#define CPF_InterruptDebugIntf_23_0__qRLC_CP_intresponse_valid__SHIFT 0x00000001 -#define CPF_InterruptDebugIntf_23_0__qCP_RLC_intrequest_id__SHIFT 0x00000002 -#define CPF_InterruptDebugIntf_23_0__qCP_RLC_intrequest_info_13_0__SHIFT 0x0000000a -#define CPF_InterruptDebugIntf_23_0__Reserved0__SHIFT 0x00000018 - -// CPF_InterruptDebugIntf_47_24 -#define CPF_InterruptDebugIntf_47_24__qCP_RLC_intrequest_info_37_14__SHIFT 0x00000000 -#define CPF_InterruptDebugIntf_47_24__Reserved0__SHIFT 0x00000018 - -// CPF_InterruptDebugIntf_58_48 -#define CPF_InterruptDebugIntf_58_48__qCP_RLC_intrequest_info_47_38__SHIFT 0x00000000 -#define CPF_InterruptDebugIntf_58_48__qCP_RLC_intrequest_valid__SHIFT 0x0000000a -#define CPF_InterruptDebugIntf_58_48__Reserved0__SHIFT 0x0000000b - -// CPF_RciuDebugBus -#define CPF_RciuDebugBus__qCpfSendCntUnderflow__SHIFT 0x00000000 -#define CPF_RciuDebugBus__qCpfSendCntOverflow__SHIFT 0x00000001 -#define CPF_RciuDebugBus__CpfRciuFifoFull__SHIFT 0x00000002 -#define CPF_RciuDebugBus__CpfRciuFreeFifoEmpty__SHIFT 0x00000004 -#define CPF_RciuDebugBus__CpfRciuFreeFifoFull__SHIFT 0x00000005 -#define CPF_RciuDebugBus__SendCountHitMax__SHIFT 0x00000006 -#define CPF_RciuDebugBus__SendCountEqZero__SHIFT 0x00000007 -#define CPF_RciuDebugBus__CpfGrbmFree__SHIFT 0x00000008 -#define CPF_RciuDebugBus__Reserved0__SHIFT 0x00000009 - -// bci_control0_dbg_bus -#define bci_control0_dbg_bus__accum_offset23_1_0__SHIFT 0x00000000 -#define bci_control0_dbg_bus__accum_offset01__SHIFT 0x00000002 -#define bci_control0_dbg_bus__spi_interface_full__SHIFT 0x00000006 -#define bci_control0_dbg_bus__start_of_wave__SHIFT 0x00000007 -#define bci_control0_dbg_bus__bc_state_reg2_3_0__SHIFT 0x00000008 -#define bci_control0_dbg_bus__bc_op_reg2__SHIFT 0x0000000c -#define bci_control0_dbg_bus__bc_num_reg2__SHIFT 0x0000000e -#define bci_control0_dbg_bus__start_with_bank01__SHIFT 0x00000010 -#define bci_control0_dbg_bus__primary_bank__SHIFT 0x00000011 -#define bci_control0_dbg_bus__bc_state_id__SHIFT 0x00000012 -#define bci_control0_dbg_bus__in_fifo_empty__SHIFT 0x00000015 -#define bci_control0_dbg_bus__no_outstanding_loads__SHIFT 0x00000016 -#define bci_control0_dbg_bus__Reserved0__SHIFT 0x00000017 - -// bci_control1_dbg_bus -#define bci_control1_dbg_bus__accum_offset23_1_0__SHIFT 0x00000000 -#define bci_control1_dbg_bus__accum_offset01__SHIFT 0x00000002 -#define bci_control1_dbg_bus__spi_interface_full__SHIFT 0x00000006 -#define bci_control1_dbg_bus__start_of_wave__SHIFT 0x00000007 -#define bci_control1_dbg_bus__bc_state_reg2_3_0__SHIFT 0x00000008 -#define bci_control1_dbg_bus__bc_op_reg2__SHIFT 0x0000000c -#define bci_control1_dbg_bus__bc_num_reg2__SHIFT 0x0000000e -#define bci_control1_dbg_bus__start_with_bank01__SHIFT 0x00000010 -#define bci_control1_dbg_bus__primary_bank__SHIFT 0x00000011 -#define bci_control1_dbg_bus__bc_state_id__SHIFT 0x00000012 -#define bci_control1_dbg_bus__in_fifo_empty__SHIFT 0x00000015 -#define bci_control1_dbg_bus__no_outstanding_loads__SHIFT 0x00000016 -#define bci_control1_dbg_bus__Reserved0__SHIFT 0x00000017 - -// bci_pipe0_dbg_bus -#define bci_pipe0_dbg_bus__bci_pipe0_fifo_empty__SHIFT 0x00000000 -#define bci_pipe0_dbg_bus__pipe0_fifo_re__SHIFT 0x00000001 -#define bci_pipe0_dbg_bus__pipe0_fifo_we__SHIFT 0x00000002 -#define bci_pipe0_dbg_bus__end_of_vector__SHIFT 0x00000003 -#define bci_pipe0_dbg_bus__stage_row_cnt_reg__SHIFT 0x00000004 -#define bci_pipe0_dbg_bus__row_xfer_phase__SHIFT 0x00000006 -#define bci_pipe0_dbg_bus__even_odd_boundary_reg__SHIFT 0x00000008 -#define bci_pipe0_dbg_bus__bc_quad0_data_is_double_quad__SHIFT 0x00000009 -#define bci_pipe0_dbg_bus__bc_state_reg__SHIFT 0x0000000a -#define bci_pipe0_dbg_bus__bc_state_id_rb_plus__SHIFT 0x0000000c -#define bci_pipe0_dbg_bus__in_fifo_full__SHIFT 0x0000000f -#define bci_pipe0_dbg_bus__in_fifo_empty_rb_plus__SHIFT 0x00000010 -#define bci_pipe0_dbg_bus__Reserved0__SHIFT 0x00000011 - -// bci_pipe1_dbg_bus -#define bci_pipe1_dbg_bus__bci_pipe0_fifo_empty__SHIFT 0x00000000 -#define bci_pipe1_dbg_bus__pipe0_fifo_re__SHIFT 0x00000001 -#define bci_pipe1_dbg_bus__pipe0_fifo_we__SHIFT 0x00000002 -#define bci_pipe1_dbg_bus__end_of_vector__SHIFT 0x00000003 -#define bci_pipe1_dbg_bus__stage_row_cnt_reg__SHIFT 0x00000004 -#define bci_pipe1_dbg_bus__row_xfer_phase__SHIFT 0x00000006 -#define bci_pipe1_dbg_bus__even_odd_boundary_reg__SHIFT 0x00000008 -#define bci_pipe1_dbg_bus__bc_quad0_data_is_double_quad__SHIFT 0x00000009 -#define bci_pipe1_dbg_bus__bc_state_reg__SHIFT 0x0000000a -#define bci_pipe1_dbg_bus__bc_state_id_rb_plus__SHIFT 0x0000000c -#define bci_pipe1_dbg_bus__in_fifo_full__SHIFT 0x0000000f -#define bci_pipe1_dbg_bus__in_fifo_empty_rb_plus__SHIFT 0x00000010 -#define bci_pipe1_dbg_bus__Reserved0__SHIFT 0x00000011 - -// RMI_DEBUGBUS_0 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID7__SHIFT 0x00000000 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID6__SHIFT 0x00000001 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID5__SHIFT 0x00000002 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID4__SHIFT 0x00000003 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID3__SHIFT 0x00000004 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID2__SHIFT 0x00000005 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID1__SHIFT 0x00000006 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_REQ_START_FINISH_VMID0__SHIFT 0x00000007 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID_ALL__SHIFT 0x00000008 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID15__SHIFT 0x00000009 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID14__SHIFT 0x0000000a -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID13__SHIFT 0x0000000b -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID12__SHIFT 0x0000000c -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID11__SHIFT 0x0000000d -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID10__SHIFT 0x0000000e -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID9__SHIFT 0x0000000f -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID8__SHIFT 0x00000010 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID7__SHIFT 0x00000011 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID6__SHIFT 0x00000012 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID5__SHIFT 0x00000013 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID4__SHIFT 0x00000014 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID3__SHIFT 0x00000015 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID2__SHIFT 0x00000016 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID1__SHIFT 0x00000017 -#define RMI_DEBUGBUS_0__RMI_INVALIDATION_ATC_REQ_VMID0__SHIFT 0x00000018 -#define RMI_DEBUGBUS_0__EVENT_SEND0__SHIFT 0x00000019 -#define RMI_DEBUGBUS_0__PERF_WINDOW0__SHIFT 0x0000001a -#define RMI_DEBUGBUS_0__DYN_CLK_PERF_VLD__SHIFT 0x0000001b -#define RMI_DEBUGBUS_0__DYN_CLK_RB0_VLD__SHIFT 0x0000001c -#define RMI_DEBUGBUS_0__DYN_CLK_CMN_VLD__SHIFT 0x0000001d -#define RMI_DEBUGBUS_0__REG_CLK_VLD__SHIFT 0x0000001e -#define RMI_DEBUGBUS_0__BUSY__SHIFT 0x0000001f - -// RMI_DEBUGBUS_1 -#define RMI_DEBUGBUS_1__RB0_RMI_RDREQ_BUSY__SHIFT 0x00000000 -#define RMI_DEBUGBUS_1__RB0_RMI_RDREQ_ALL_CID__SHIFT 0x00000001 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID7__SHIFT 0x00000002 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID6__SHIFT 0x00000003 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID5__SHIFT 0x00000004 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID4__SHIFT 0x00000005 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID3__SHIFT 0x00000006 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID2__SHIFT 0x00000007 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID1__SHIFT 0x00000008 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_CID0__SHIFT 0x00000009 -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_BUSY__SHIFT 0x0000000a -#define RMI_DEBUGBUS_1__RB0_RMI_WRREQ_ALL_CID__SHIFT 0x0000000b -#define RMI_DEBUGBUS_1__UTCL1_STALL_MULTI_MISS__SHIFT 0x0000000c -#define RMI_DEBUGBUS_1__UTCL1_HIT_FIFO_FULL__SHIFT 0x0000000d -#define RMI_DEBUGBUS_1__UTCL1_STALL_MISSFIFO_FULL__SHIFT 0x0000000e -#define RMI_DEBUGBUS_1__UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS__SHIFT 0x0000000f -#define RMI_DEBUGBUS_1__UTCL1_STALL_LFIFO_NOT_RES0__SHIFT 0x00000010 -#define RMI_DEBUGBUS_1__UTCL1_LFIFO_FULL__SHIFT 0x00000011 -#define RMI_DEBUGBUS_1__UTCL1_STALL_LRU_INFLIGHT__SHIFT 0x00000012 -#define RMI_DEBUGBUS_1__UTCL1_STALL_INFLIGHT_MAX__SHIFT 0x00000013 -#define RMI_DEBUGBUS_1__UTCL1_REQUEST0__SHIFT 0x00000014 -#define RMI_DEBUGBUS_1__UTCL1_PERMISSION_MISS__SHIFT 0x00000015 -#define RMI_DEBUGBUS_1__UTCL1_TRANSLATION_MISS__SHIFT 0x00000016 -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL__SHIFT 0x00000017 -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID15__SHIFT 0x00000018 -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID14__SHIFT 0x00000019 -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID13__SHIFT 0x0000001a -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID12__SHIFT 0x0000001b -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID11__SHIFT 0x0000001c -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID10__SHIFT 0x0000001d -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID9__SHIFT 0x0000001e -#define RMI_DEBUGBUS_1__RMI_INVALIDATION_REQ_START_FINISH_VMID8__SHIFT 0x0000001f - -// RMI_DEBUGBUS_2 -#define RMI_DEBUGBUS_2__RMI_UTC_REQ0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK3__SHIFT 0x00000001 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK2__SHIFT 0x00000002 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK1__SHIFT 0x00000003 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_NACK0__SHIFT 0x00000004 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID7__SHIFT 0x00000005 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID6__SHIFT 0x00000006 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID5__SHIFT 0x00000007 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID4__SHIFT 0x00000008 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID3__SHIFT 0x00000009 -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID2__SHIFT 0x0000000a -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID1__SHIFT 0x0000000b -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_CID0__SHIFT 0x0000000c -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID__SHIFT 0x0000000d -#define RMI_DEBUGBUS_2__RMI_RB0_WRRET_VALID_ALL_CID__SHIFT 0x00000013 -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_RESIDENCY__SHIFT 0x00000014 -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_BURST_ALL_ORONE_CID__SHIFT 0x00000015 -#define RMI_DEBUGBUS_2__RB0_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID__SHIFT 0x00000016 - -// RMI_DEBUGBUS_3 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID7__SHIFT 0x00000000 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID6__SHIFT 0x00000004 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID5__SHIFT 0x00000008 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID4__SHIFT 0x0000000c -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID3__SHIFT 0x00000010 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID2__SHIFT 0x00000014 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID1__SHIFT 0x00000018 -#define RMI_DEBUGBUS_3__RB0_RMI_32BRDREQ_CID0__SHIFT 0x0000001c - -// RMI_DEBUGBUS_4 -#define RMI_DEBUGBUS_4__RMI_UTC_BUSY0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_4__RMI_RB0_32BRDRET_VALID_ALL_CID__SHIFT 0x00000001 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_RESIDENCY__SHIFT 0x00000002 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_BURST_ALL_ORONE_CID__SHIFT 0x00000003 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID__SHIFT 0x00000004 -#define RMI_DEBUGBUS_4__RB0_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID__SHIFT 0x0000000a -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID7__SHIFT 0x00000014 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID6__SHIFT 0x00000015 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID5__SHIFT 0x00000016 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID4__SHIFT 0x00000017 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID3__SHIFT 0x00000018 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID2__SHIFT 0x00000019 -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID1__SHIFT 0x0000001a -#define RMI_DEBUGBUS_4__RB0_RMI_RDREQ_CID0__SHIFT 0x0000001b -#define RMI_DEBUGBUS_4__RB0_RMI_32BRDREQ_ALL_CID__SHIFT 0x0000001c - -// RMI_DEBUGBUS_5 -#define RMI_DEBUGBUS_5__RMI0_TC_RDREQ_ALL_CID__SHIFT 0x00000000 -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_INFLIGHT_ALL_CID__SHIFT 0x00000001 -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID7__SHIFT 0x0000000a -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID6__SHIFT 0x0000000b -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID5__SHIFT 0x0000000c -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID4__SHIFT 0x0000000d -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID3__SHIFT 0x0000000e -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID2__SHIFT 0x0000000f -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID1__SHIFT 0x00000010 -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_CID0__SHIFT 0x00000011 -#define RMI_DEBUGBUS_5__RMI0_TC_REQ_BUSY__SHIFT 0x00000012 -#define RMI_DEBUGBUS_5__RMI0_TC_WRREQ_ALL_CID__SHIFT 0x00000013 -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK3__SHIFT 0x00000014 -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK2__SHIFT 0x00000015 -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK1__SHIFT 0x00000016 -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_NACK0__SHIFT 0x00000017 -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID7__SHIFT 0x00000018 -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID6__SHIFT 0x00000019 -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID5__SHIFT 0x0000001a -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID4__SHIFT 0x0000001b -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID3__SHIFT 0x0000001c -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID2__SHIFT 0x0000001d -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID1__SHIFT 0x0000001e -#define RMI_DEBUGBUS_5__RMI_RB0_32BRDRET_VALID_CID0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_6 -#define RMI_DEBUGBUS_6__XNACK_FIFO_FULL__SHIFT 0x00000000 -#define RMI_DEBUGBUS_6__XNACK_FIFO_NUM_USED__SHIFT 0x00000001 -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_XNACK_NORETRY_FAULT__SHIFT 0x0000000a -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_PRT_FAULT__SHIFT 0x0000000b -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_ALL_FAULT__SHIFT 0x0000000c -#define RMI_DEBUGBUS_6__PROBE0_UTCL1_XNACK_RETRY__SHIFT 0x0000000d -#define RMI_DEBUGBUS_6__TC_RMI0_RDRET_VALID_ALL_CID__SHIFT 0x0000000e -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_INFLIGHT_ALL_CID__SHIFT 0x0000000f -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID7__SHIFT 0x00000018 -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID6__SHIFT 0x00000019 -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID5__SHIFT 0x0000001a -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID4__SHIFT 0x0000001b -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID3__SHIFT 0x0000001c -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID2__SHIFT 0x0000001d -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID1__SHIFT 0x0000001e -#define RMI_DEBUGBUS_6__RMI0_TC_RDREQ_CID0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_7 -#define RMI_DEBUGBUS_7__DEMUX_TCIW_FORMATTER0_RTS_RTRB__SHIFT 0x00000000 -#define RMI_DEBUGBUS_7__DEMUX_TCIW_FORMATTER0_RTSB_RTR__SHIFT 0x00000001 -#define RMI_DEBUGBUS_7__DEMUX_TCIW_FORMATTER0_RTS_RTR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTSB_RTRB__SHIFT 0x00000003 -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTS_RTRB__SHIFT 0x00000005 -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTSB_RTR__SHIFT 0x00000006 -#define RMI_DEBUGBUS_7__XBAR_PROBEGEN0_RTS_RTR__SHIFT 0x00000007 -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK3__SHIFT 0x00000008 -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK2__SHIFT 0x00000009 -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK1__SHIFT 0x0000000a -#define RMI_DEBUGBUS_7__DEMUX_TCIW0_RESIDENCY_ALL_ORONE_VMID_NACK0__SHIFT 0x0000000b -#define RMI_DEBUGBUS_7__TC_RMI0_WRRET_VALID_ALL_CID__SHIFT 0x0000000c -#define RMI_DEBUGBUS_7__SKID_FIFO_0_BUSY__SHIFT 0x0000000d -#define RMI_DEBUGBUS_7__SKID_FIFO_0_REQ__SHIFT 0x0000000e -#define RMI_DEBUGBUS_7__TCIW0_BUSY__SHIFT 0x0000000f -#define RMI_DEBUGBUS_7__TCIW0_REQ__SHIFT 0x00000010 -#define RMI_DEBUGBUS_7__PRT_FIFO_0_BUSY__SHIFT 0x00000011 -#define RMI_DEBUGBUS_7__PRT_FIFO_0_REQ__SHIFT 0x00000012 -#define RMI_DEBUGBUS_7__XNACK_FIFO_BUSY__SHIFT 0x00000013 -#define RMI_DEBUGBUS_7__LAT_FIFO_0_FULL__SHIFT 0x00000014 -#define RMI_DEBUGBUS_7__LAT_FIFO_0_NONBLOCKING_REQ__SHIFT 0x00000015 -#define RMI_DEBUGBUS_7__LAT_FIFO_0_BLOCKING_REQ__SHIFT 0x00000016 -#define RMI_DEBUGBUS_7__LAT_FIFO_0_NUM_USED__SHIFT 0x00000017 -#define RMI_DEBUGBUS_7__UTCL1_UTCL2_REQ__SHIFT 0x0000001e -#define RMI_DEBUGBUS_7__UTCL1_BUSY__SHIFT 0x0000001f - -// RMI_DEBUGBUS_8 -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTSB_RTRB__SHIFT 0x00000000 -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTS_RTRB__SHIFT 0x00000001 -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTSB_RTR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_8__WRREQCONSUMER0_XBAR_WRREQ_RTS_RTR__SHIFT 0x00000003 -#define RMI_DEBUGBUS_8__DEMUX_TCIW_FORMATTER0_RTSB_RTRB__SHIFT 0x00000004 -#define RMI_DEBUGBUS_8__PRT_FIFO_0_NUM_USED__SHIFT 0x00000005 -#define RMI_DEBUGBUS_8__TCIW0_INFLIGHT_COUNT__SHIFT 0x0000000e -#define RMI_DEBUGBUS_8__SKID_FIFO_0_DEPTH__SHIFT 0x00000017 - -// RMI_DEBUGBUS_9 -#define RMI_DEBUGBUS_9__SKID_FIFO_0_OUT_RTSB__SHIFT 0x00000000 -#define RMI_DEBUGBUS_9__SKID_FIFO_0_OUT_RTS__SHIFT 0x00000001 -#define RMI_DEBUGBUS_9__SKID_FIFO_0_IN_RTSB__SHIFT 0x00000002 -#define RMI_DEBUGBUS_9__SKID_FIFO_0_IN_RTS__SHIFT 0x00000003 -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTSB_RTRB__SHIFT 0x00000004 -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTS_RTRB__SHIFT 0x00000005 -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTSB_RTR__SHIFT 0x00000006 -#define RMI_DEBUGBUS_9__PRTFIFO_RTNFORMATTER0_RTS_RTR__SHIFT 0x00000007 -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTSB_RTRB__SHIFT 0x00000008 -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTS_RTRB__SHIFT 0x00000009 -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTSB_RTR__SHIFT 0x0000000a -#define RMI_DEBUGBUS_9__XNACK_PROBEGEN0_RTS_RTR__SHIFT 0x0000000b -#define RMI_DEBUGBUS_9__POP0_XNACK_RTSB_RTRB__SHIFT 0x0000000c -#define RMI_DEBUGBUS_9__POP0_XNACK_RTS_RTRB__SHIFT 0x0000000d -#define RMI_DEBUGBUS_9__POP0_XNACK_RTSB_RTR__SHIFT 0x0000000e -#define RMI_DEBUGBUS_9__POP0_XNACK_RTS_RTR__SHIFT 0x0000000f -#define RMI_DEBUGBUS_9__UTC_POP0_RTSB_RTRB__SHIFT 0x00000010 -#define RMI_DEBUGBUS_9__UTC_POP0_RTS_RTRB__SHIFT 0x00000011 -#define RMI_DEBUGBUS_9__UTC_POP0_RTSB_RTR__SHIFT 0x00000012 -#define RMI_DEBUGBUS_9__UTC_POP0_RTS_RTR__SHIFT 0x00000013 -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTSB_RTRB__SHIFT 0x00000014 -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTS_RTRB__SHIFT 0x00000015 -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTSB_RTR__SHIFT 0x00000016 -#define RMI_DEBUGBUS_9__PROBEGEN0_UTC_RTS_RTR__SHIFT 0x00000017 -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTSB_RTRB__SHIFT 0x00000018 -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTS_RTRB__SHIFT 0x00000019 -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTSB_RTR__SHIFT 0x0000001a -#define RMI_DEBUGBUS_9__POP0_DEMUX_RTS_RTR__SHIFT 0x0000001b -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTSB_RTRB__SHIFT 0x0000001c -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTS_RTRB__SHIFT 0x0000001d -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTSB_RTR__SHIFT 0x0000001e -#define RMI_DEBUGBUS_9__RDREQCONSUMER0_XBAR_RDREQ_RTS_RTR__SHIFT 0x0000001f - -// RMI_DEBUGBUS_10 -#define RMI_DEBUGBUS_10__UTCL1_STALL_LFIFO_NOT_RES1__SHIFT 0x00000000 -#define RMI_DEBUGBUS_10__RB1_RMI_RDREQ_BUSY__SHIFT 0x00000001 -#define RMI_DEBUGBUS_10__RB1_RMI_RDREQ_ALL_CID__SHIFT 0x00000002 -#define RMI_DEBUGBUS_10__RB1_RMI_WRREQ_BUSY__SHIFT 0x00000003 -#define RMI_DEBUGBUS_10__RB1_RMI_WRREQ_ALL_CID__SHIFT 0x00000004 -#define RMI_DEBUGBUS_10__UTCL1_REQUEST1__SHIFT 0x00000005 -#define RMI_DEBUGBUS_10__EVENT_SEND1__SHIFT 0x00000006 -#define RMI_DEBUGBUS_10__PERF_WINDOW1__SHIFT 0x00000007 -#define RMI_DEBUGBUS_10__DYN_CLK_RB1_VLD__SHIFT 0x00000008 -#define RMI_DEBUGBUS_10__PROBE0_UTCL1_VMID_BYPASS__SHIFT 0x00000009 -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK3__SHIFT 0x0000000a -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK2__SHIFT 0x0000000b -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK1__SHIFT 0x0000000c -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_NACK0__SHIFT 0x0000000d -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID7__SHIFT 0x0000000e -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID6__SHIFT 0x0000000f -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID5__SHIFT 0x00000010 -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID4__SHIFT 0x00000011 -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID3__SHIFT 0x00000012 -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID2__SHIFT 0x00000013 -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID1__SHIFT 0x00000014 -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_CID0__SHIFT 0x00000015 -#define RMI_DEBUGBUS_10__RMI_RB0_EARLY_WRACK_ALL_CID__SHIFT 0x00000016 -#define RMI_DEBUGBUS_10__REORDER_FIFO_0_BUSY__SHIFT 0x00000017 -#define RMI_DEBUGBUS_10__REORDER_FIFO_0_REQ__SHIFT 0x00000018 -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_DB_RTS_RTR__SHIFT 0x00000019 -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_CB_RTS_RTR__SHIFT 0x0000001a -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_IN1_RTS_RTR__SHIFT 0x0000001b -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_IN0_RTS_RTR__SHIFT 0x0000001c -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_WRITE_RTS_RTR__SHIFT 0x0000001d -#define RMI_DEBUGBUS_10__XBAR_PROBEGEN0_READ_RTS_RTR__SHIFT 0x0000001e -#define RMI_DEBUGBUS_10__RESERVED0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_11 -#define RMI_DEBUGBUS_11__RMI_UTC_REQ1__SHIFT 0x00000000 -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK3__SHIFT 0x00000001 -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK2__SHIFT 0x00000002 -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK1__SHIFT 0x00000003 -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_NACK0__SHIFT 0x00000004 -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID__SHIFT 0x00000005 -#define RMI_DEBUGBUS_11__RMI_RB1_WRRET_VALID_ALL_CID__SHIFT 0x0000000b -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_RESIDENCY__SHIFT 0x0000000c -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_BURST_ALL_ORONE_CID__SHIFT 0x0000000d -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID__SHIFT 0x0000000e -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID7__SHIFT 0x00000018 -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID6__SHIFT 0x00000019 -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID5__SHIFT 0x0000001a -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID4__SHIFT 0x0000001b -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID3__SHIFT 0x0000001c -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID2__SHIFT 0x0000001d -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID1__SHIFT 0x0000001e -#define RMI_DEBUGBUS_11__RB1_RMI_WRREQ_CID0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_12 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID7__SHIFT 0x00000000 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID6__SHIFT 0x00000004 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID5__SHIFT 0x00000008 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID4__SHIFT 0x0000000c -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID3__SHIFT 0x00000010 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID2__SHIFT 0x00000014 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID1__SHIFT 0x00000018 -#define RMI_DEBUGBUS_12__RB1_RMI_32BRDREQ_CID0__SHIFT 0x0000001c - -// RMI_DEBUGBUS_13 -#define RMI_DEBUGBUS_13__RMI_UTC_BUSY1__SHIFT 0x00000000 -#define RMI_DEBUGBUS_13__RMI_RB1_32BRDRET_VALID_ALL_CID__SHIFT 0x00000001 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_RESIDENCY__SHIFT 0x00000002 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_BURST_ALL_ORONE_CID__SHIFT 0x00000003 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID__SHIFT 0x00000004 -#define RMI_DEBUGBUS_13__RB1_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID__SHIFT 0x0000000a -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID7__SHIFT 0x00000014 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID6__SHIFT 0x00000015 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID5__SHIFT 0x00000016 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID4__SHIFT 0x00000017 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID3__SHIFT 0x00000018 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID2__SHIFT 0x00000019 -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID1__SHIFT 0x0000001a -#define RMI_DEBUGBUS_13__RB1_RMI_RDREQ_CID0__SHIFT 0x0000001b -#define RMI_DEBUGBUS_13__RB1_RMI_32BRDREQ_ALL_CID__SHIFT 0x0000001c - -// RMI_DEBUGBUS_14 -#define RMI_DEBUGBUS_14__RMI1_TC_RDREQ_ALL_CID__SHIFT 0x00000000 -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_INFLIGHT_ALL_CID__SHIFT 0x00000001 -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID7__SHIFT 0x0000000a -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID6__SHIFT 0x0000000b -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID5__SHIFT 0x0000000c -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID4__SHIFT 0x0000000d -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID3__SHIFT 0x0000000e -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID2__SHIFT 0x0000000f -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID1__SHIFT 0x00000010 -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_CID0__SHIFT 0x00000011 -#define RMI_DEBUGBUS_14__RMI1_TC_REQ_BUSY__SHIFT 0x00000012 -#define RMI_DEBUGBUS_14__RMI1_TC_WRREQ_ALL_CID__SHIFT 0x00000013 -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK3__SHIFT 0x00000014 -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK2__SHIFT 0x00000015 -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK1__SHIFT 0x00000016 -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_NACK0__SHIFT 0x00000017 -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID7__SHIFT 0x00000018 -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID6__SHIFT 0x00000019 -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID5__SHIFT 0x0000001a -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID4__SHIFT 0x0000001b -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID3__SHIFT 0x0000001c -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID2__SHIFT 0x0000001d -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID1__SHIFT 0x0000001e -#define RMI_DEBUGBUS_14__RMI_RB1_32BRDRET_VALID_CID0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_15 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID7__SHIFT 0x00000000 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID6__SHIFT 0x00000001 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID5__SHIFT 0x00000002 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID4__SHIFT 0x00000003 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID3__SHIFT 0x00000004 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID2__SHIFT 0x00000005 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID1__SHIFT 0x00000006 -#define RMI_DEBUGBUS_15__RMI_RB1_WRRET_VALID_CID0__SHIFT 0x00000007 -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_XNACK_NORETRY_FAULT__SHIFT 0x00000008 -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_PRT_FAULT__SHIFT 0x00000009 -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_ALL_FAULT__SHIFT 0x0000000a -#define RMI_DEBUGBUS_15__PROBE1_UTCL1_XNACK_RETRY__SHIFT 0x0000000b -#define RMI_DEBUGBUS_15__RESERVED0__SHIFT 0x0000000c -#define RMI_DEBUGBUS_15__TC_RMI1_RDRET_VALID_ALL_CID__SHIFT 0x0000000d -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_INFLIGHT_ALL_CID__SHIFT 0x0000000f -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID7__SHIFT 0x00000018 -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID6__SHIFT 0x00000019 -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID5__SHIFT 0x0000001a -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID4__SHIFT 0x0000001b -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID3__SHIFT 0x0000001c -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID2__SHIFT 0x0000001d -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID1__SHIFT 0x0000001e -#define RMI_DEBUGBUS_15__RMI1_TC_RDREQ_CID0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_16 -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTSB_RTRB__SHIFT 0x00000000 -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTS_RTRB__SHIFT 0x00000001 -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTSB_RTR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_16__XBAR_PROBEGEN1_RTS_RTR__SHIFT 0x00000003 -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTSB_RTRB__SHIFT 0x00000004 -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTS_RTRB__SHIFT 0x00000005 -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTSB_RTR__SHIFT 0x00000006 -#define RMI_DEBUGBUS_16__DEMUX_TCIW_FORMATTER1_RTS_RTR__SHIFT 0x00000007 -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK3__SHIFT 0x00000008 -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK2__SHIFT 0x00000009 -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK1__SHIFT 0x0000000a -#define RMI_DEBUGBUS_16__DEMUX_TCIW1_RESIDENCY_ALL_ORONE_VMID_NACK0__SHIFT 0x0000000b -#define RMI_DEBUGBUS_16__TC_RMI1_WRRET_VALID_ALL_CID__SHIFT 0x0000000c -#define RMI_DEBUGBUS_16__SKID_FIFO_1_BUSY__SHIFT 0x0000000e -#define RMI_DEBUGBUS_16__SKID_FIFO_1_REQ__SHIFT 0x0000000f -#define RMI_DEBUGBUS_16__TCIW1_BUSY__SHIFT 0x00000010 -#define RMI_DEBUGBUS_16__TCIW1_REQ__SHIFT 0x00000011 -#define RMI_DEBUGBUS_16__PRT_FIFO_1_BUSY__SHIFT 0x00000012 -#define RMI_DEBUGBUS_16__PRT_FIFO_1_REQ__SHIFT 0x00000013 -#define RMI_DEBUGBUS_16__LAT_FIFO_1_FULL__SHIFT 0x00000014 -#define RMI_DEBUGBUS_16__SKID_FIFO_1_OUT_RTSB__SHIFT 0x00000015 -#define RMI_DEBUGBUS_16__SKID_FIFO_1_OUT_RTS__SHIFT 0x00000016 -#define RMI_DEBUGBUS_16__LAT_FIFO_1_NONBLOCKING_REQ__SHIFT 0x00000017 -#define RMI_DEBUGBUS_16__LAT_FIFO_1_BLOCKING_REQ__SHIFT 0x00000018 -#define RMI_DEBUGBUS_16__LAT_FIFO_1_NUM_USED__SHIFT 0x00000019 - -// RMI_DEBUGBUS_17 -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTSB_RTRB__SHIFT 0x00000000 -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTS_RTRB__SHIFT 0x00000001 -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTSB_RTR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_17__WRREQCONSUMER1_XBAR_WRREQ_RTS_RTR__SHIFT 0x00000003 -#define RMI_DEBUGBUS_17__RESERVED0__SHIFT 0x00000004 -#define RMI_DEBUGBUS_17__PRT_FIFO_1_NUM_USED__SHIFT 0x00000005 -#define RMI_DEBUGBUS_17__TCIW1_INFLIGHT_COUNT__SHIFT 0x0000000e -#define RMI_DEBUGBUS_17__SKID_FIFO_1_DEPTH__SHIFT 0x00000017 - -// RMI_DEBUGBUS_18 -#define RMI_DEBUGBUS_18__RESERVED0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_18__SKID_FIFO_1_IN_RTSB__SHIFT 0x00000002 -#define RMI_DEBUGBUS_18__SKID_FIFO_1_IN_RTS__SHIFT 0x00000003 -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTSB_RTRB__SHIFT 0x00000004 -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTS_RTRB__SHIFT 0x00000005 -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTSB_RTR__SHIFT 0x00000006 -#define RMI_DEBUGBUS_18__PRTFIFO_RTNFORMATTER1_RTS_RTR__SHIFT 0x00000007 -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTSB_RTRB__SHIFT 0x00000008 -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTS_RTRB__SHIFT 0x00000009 -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTSB_RTR__SHIFT 0x0000000a -#define RMI_DEBUGBUS_18__XNACK_PROBEGEN1_RTS_RTR__SHIFT 0x0000000b -#define RMI_DEBUGBUS_18__POP1_XNACK_RTSB_RTRB__SHIFT 0x0000000c -#define RMI_DEBUGBUS_18__POP1_XNACK_RTS_RTRB__SHIFT 0x0000000d -#define RMI_DEBUGBUS_18__POP1_XNACK_RTSB_RTR__SHIFT 0x0000000e -#define RMI_DEBUGBUS_18__POP1_XNACK_RTS_RTR__SHIFT 0x0000000f -#define RMI_DEBUGBUS_18__UTC_POP1_RTSB_RTRB__SHIFT 0x00000010 -#define RMI_DEBUGBUS_18__UTC_POP1_RTS_RTRB__SHIFT 0x00000011 -#define RMI_DEBUGBUS_18__UTC_POP1_RTSB_RTR__SHIFT 0x00000012 -#define RMI_DEBUGBUS_18__UTC_POP1_RTS_RTR__SHIFT 0x00000013 -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTSB_RTRB__SHIFT 0x00000014 -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTS_RTRB__SHIFT 0x00000015 -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTSB_RTR__SHIFT 0x00000016 -#define RMI_DEBUGBUS_18__POP1_DEMUX_RTS_RTR__SHIFT 0x00000017 -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTSB_RTRB__SHIFT 0x00000018 -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTS_RTRB__SHIFT 0x00000019 -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTSB_RTR__SHIFT 0x0000001a -#define RMI_DEBUGBUS_18__PROBEGEN1_UTC_RTS_RTR__SHIFT 0x0000001b -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTSB_RTRB__SHIFT 0x0000001c -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTS_RTRB__SHIFT 0x0000001d -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTSB_RTR__SHIFT 0x0000001e -#define RMI_DEBUGBUS_18__RDREQCONSUMER1_XBAR_RDREQ_RTS_RTR__SHIFT 0x0000001f - -// RMI_DEBUGBUS_19 -#define RMI_DEBUGBUS_19__Reserved0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK3__SHIFT 0x0000000a -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK2__SHIFT 0x0000000b -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK1__SHIFT 0x0000000c -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_NACK0__SHIFT 0x0000000d -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID7__SHIFT 0x0000000e -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID6__SHIFT 0x0000000f -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID5__SHIFT 0x00000010 -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID4__SHIFT 0x00000011 -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID3__SHIFT 0x00000012 -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID2__SHIFT 0x00000013 -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID1__SHIFT 0x00000014 -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_CID0__SHIFT 0x00000015 -#define RMI_DEBUGBUS_19__RMI_RB1_EARLY_WRACK_ALL_CID_EVENT__SHIFT 0x00000016 -#define RMI_DEBUGBUS_19__REORDER_FIFO_1_BUSY__SHIFT 0x00000017 -#define RMI_DEBUGBUS_19__REORDER_FIFO_1_REQ__SHIFT 0x00000018 -#define RMI_DEBUGBUS_19__PROBE1_UTCL1_VMID_BYPASS__SHIFT 0x00000019 -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_DB_RTS_RTR__SHIFT 0x0000001a -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_CB_RTS_RTR__SHIFT 0x0000001b -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_IN1_RTS_RTR__SHIFT 0x0000001c -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_IN0_RTS_RTR__SHIFT 0x0000001d -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_WRITE_RTS_RTR__SHIFT 0x0000001e -#define RMI_DEBUGBUS_19__XBAR_PROBEGEN1_READ_RTS_RTR__SHIFT 0x0000001f - -// RMI_DEBUGBUS_20 -#define RMI_DEBUGBUS_20__RB0_WRREQ_CONSUMER_FIFO_EMPTY__SHIFT 0x00000000 -#define RMI_DEBUGBUS_20__RB0_RDREQ_CONSUMER_FIFO_EMPTY__SHIFT 0x00000001 -#define RMI_DEBUGBUS_20__RB0_WRREQ_CONSUMER_FIFO_FULL__SHIFT 0x00000002 -#define RMI_DEBUGBUS_20__RB0_RDREQ_CONSUMER_FIFO_FULL__SHIFT 0x00000003 -#define RMI_DEBUGBUS_20__RB0_WRREQ_CONSUMER_FIFO_BUSY__SHIFT 0x00000004 -#define RMI_DEBUGBUS_20__RB0_RDREQ_CONSUMER_FIFO_BUSY__SHIFT 0x00000005 -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x00000006 -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x00000007 -#define RMI_DEBUGBUS_20__XNACK_FIFO_EMPTY__SHIFT 0x00000008 -#define RMI_DEBUGBUS_20__XNACK_FIFO_FULL__SHIFT 0x00000009 -#define RMI_DEBUGBUS_20__UTCL1_STALL_MISSFIFO_FULL_EVENT__SHIFT 0x0000000a -#define RMI_DEBUGBUS_20__UTCL1_STALL_INFLIGHT_MAX_EVENT__SHIFT 0x0000000b -#define RMI_DEBUGBUS_20__UTCL1_STALL_LRU_INFLIGHT_EVENT__SHIFT 0x0000000c -#define RMI_DEBUGBUS_20__UTCL1_LFIFO_FULL_EVENT__SHIFT 0x0000000d -#define RMI_DEBUGBUS_20__UTCL1_HIT_FIFO_FULL_EVENT__SHIFT 0x0000000e -#define RMI_DEBUGBUS_20__UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_EVENT__SHIFT 0x0000000f -#define RMI_DEBUGBUS_20__UTCL1_STALL_LFIFO_NOT_RES_EVENT__SHIFT 0x00000010 -#define RMI_DEBUGBUS_20__RB1_WRREQ_CONSUMER_FIFO_EMPTY__SHIFT 0x00000011 -#define RMI_DEBUGBUS_20__RB1_RDREQ_CONSUMER_FIFO_EMPTY__SHIFT 0x00000012 -#define RMI_DEBUGBUS_20__RB1_WRREQ_CONSUMER_FIFO_FULL__SHIFT 0x00000013 -#define RMI_DEBUGBUS_20__RB1_RDREQ_CONSUMER_FIFO_FULL__SHIFT 0x00000014 -#define RMI_DEBUGBUS_20__RB1_WRREQ_CONSUMER_FIFO_BUSY__SHIFT 0x00000015 -#define RMI_DEBUGBUS_20__RB1_RDREQ_CONSUMER_FIFO_BUSY__SHIFT 0x00000016 -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x00000017 -#define RMI_DEBUGBUS_20__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x00000018 -#define RMI_DEBUGBUS_20__UTC_OUT_STALL_SOURCE__SHIFT 0x00000019 -#define RMI_DEBUGBUS_20__UTC_IN_STALL_SOURCE__SHIFT 0x0000001c -#define RMI_DEBUGBUS_20__UTCL1_INFLIGHT_WATERMARK_HIT__SHIFT 0x0000001f - -// RMI_DEBUGBUS_21 -#define RMI_DEBUGBUS_21__TCIW0_PRODUCER_CREDIT_CNT__SHIFT 0x00000000 -#define RMI_DEBUGBUS_21__TCIW1_PRODUCER_CREDIT_CNT__SHIFT 0x00000006 -#define RMI_DEBUGBUS_21__POP0_DEMUX_RTR__SHIFT 0x0000000c -#define RMI_DEBUGBUS_21__POP0_DEMUX_RTS__SHIFT 0x0000000d -#define RMI_DEBUGBUS_21__POP1_DEMUX_RTR__SHIFT 0x0000000e -#define RMI_DEBUGBUS_21__POP1_DEMUX_RTS__SHIFT 0x0000000f -#define RMI_DEBUGBUS_21__RB0RDREQCONSUMER_XBAR_RDREQ_RTR__SHIFT 0x00000010 -#define RMI_DEBUGBUS_21__RB0RDREQCONSUMER_XBAR_RDREQ_RTS__SHIFT 0x00000011 -#define RMI_DEBUGBUS_21__RB0WRREQCONSUMER_XBAR_WRREQ_RTR__SHIFT 0x00000012 -#define RMI_DEBUGBUS_21__RB0WRREQCONSUMER_XBAR_WRREQ_RTS__SHIFT 0x00000013 -#define RMI_DEBUGBUS_21__RB1RDREQCONSUMER_XBAR_RDREQ_RTR__SHIFT 0x00000014 -#define RMI_DEBUGBUS_21__RB1RDREQCONSUMER_XBAR_RDREQ_RTS__SHIFT 0x00000015 -#define RMI_DEBUGBUS_21__RB1WRREQCONSUMER_XBAR_WRREQ_RTR__SHIFT 0x00000016 -#define RMI_DEBUGBUS_21__RB1WRREQCONSUMER_XBAR_WRREQ_RTS__SHIFT 0x00000017 -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER0_RTR__SHIFT 0x00000018 -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER0_RTS__SHIFT 0x00000019 -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER1_RTR__SHIFT 0x0000001a -#define RMI_DEBUGBUS_21__DEMUX_TCIW_FORMATTER1_RTS__SHIFT 0x0000001b -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN0_RTR__SHIFT 0x0000001c -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN0_RTS__SHIFT 0x0000001d -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN1_RTR__SHIFT 0x0000001e -#define RMI_DEBUGBUS_21__XBAR_PROBEGEN1_RTS__SHIFT 0x0000001f - -// RMI_DEBUGBUS_22 -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO0_F1__SHIFT 0x00000000 -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO0_F2__SHIFT 0x00000008 -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO1_F1__SHIFT 0x00000010 -#define RMI_DEBUGBUS_22__RTNFORMATTER_REQFORMATTER_SKIDFIFO1_F2__SHIFT 0x00000018 - -// RMI_DEBUGBUS_23 -#define RMI_DEBUGBUS_23__ARBITER0_REQ_OUT_DATA_FLOPPED_EN__SHIFT 0x00000000 -#define RMI_DEBUGBUS_23__ARBITER0_REQ_OUT_RTS__SHIFT 0x00000001 -#define RMI_DEBUGBUS_23__ARBITER0_GATED_BY_WEIGHTEDRR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_23__ARBITER0_WAITING_FOR_END_OF_BURST__SHIFT 0x00000003 -#define RMI_DEBUGBUS_23__ARBITER0_MASKED_REQUESTS_FOR_WRAPPING_REDUCED__SHIFT 0x00000004 -#define RMI_DEBUGBUS_23__ARBITER0_MASKED_REQUESTS_REDUCED__SHIFT 0x00000005 -#define RMI_DEBUGBUS_23__ARBITER0_REQ_OUT_STALLED__SHIFT 0x00000006 -#define RMI_DEBUGBUS_23__ARBITER0_ARBITER_DISABLE_D__SHIFT 0x00000007 -#define RMI_DEBUGBUS_23__ARBITER0_OUTPUT_STALLED__SHIFT 0x00000008 -#define RMI_DEBUGBUS_23__ARBITER0_CURRENT_REQUEST_ID__SHIFT 0x00000009 -#define RMI_DEBUGBUS_23__ARBITER0_REQ_IN_RTR_FSM__SHIFT 0x0000000a -#define RMI_DEBUGBUS_23__ARBITER0_REQUEST_MASKS__SHIFT 0x0000000c -#define RMI_DEBUGBUS_23__Reserved0__SHIFT 0x0000000e - -// RMI_DEBUGBUS_24 -#define RMI_DEBUGBUS_24__ARBITER1_REQ_OUT_DATA_FLOPPED_EN__SHIFT 0x00000000 -#define RMI_DEBUGBUS_24__ARBITER1_REQ_OUT_RTS__SHIFT 0x00000001 -#define RMI_DEBUGBUS_24__ARBITER1_GATED_BY_WEIGHTEDRR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_24__ARBITER1_WAITING_FOR_END_OF_BURST__SHIFT 0x00000003 -#define RMI_DEBUGBUS_24__ARBITER1_MASKED_REQUESTS_FOR_WRAPPING_REDUCED__SHIFT 0x00000004 -#define RMI_DEBUGBUS_24__ARBITER1_MASKED_REQUESTS_REDUCED__SHIFT 0x00000005 -#define RMI_DEBUGBUS_24__ARBITER1_REQ_OUT_STALLED__SHIFT 0x00000006 -#define RMI_DEBUGBUS_24__ARBITER1_ARBITER_DISABLE_D__SHIFT 0x00000007 -#define RMI_DEBUGBUS_24__ARBITER1_OUTPUT_STALLED__SHIFT 0x00000008 -#define RMI_DEBUGBUS_24__ARBITER1_CURRENT_REQUEST_ID__SHIFT 0x00000009 -#define RMI_DEBUGBUS_24__ARBITER1_REQ_IN_RTR_FSM__SHIFT 0x0000000a -#define RMI_DEBUGBUS_24__ARBITER1_REQUEST_MASKS__SHIFT 0x0000000c -#define RMI_DEBUGBUS_24__XBAR_CONFIG_OVERRIDE_DB__SHIFT 0x0000000e -#define RMI_DEBUGBUS_24__XBAR_ARBITER_DISABLE_INT__SHIFT 0x0000000f -#define RMI_DEBUGBUS_24__Reserved0__SHIFT 0x00000010 - -// RMI_DEBUGBUS_25 -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_REENABLE_INPUT_RB0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_FLUSH_START_RB0__SHIFT 0x00000001 -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_REENABLE_INPUT_RB1__SHIFT 0x00000002 -#define RMI_DEBUGBUS_25__XBAR_INCOMING_REQUESTS_FLUSH_START_RB1__SHIFT 0x00000003 -#define RMI_DEBUGBUS_25__RB0RDREQCONSUMER_XBAR_RDREQ_RTR_PROBE0__SHIFT 0x00000004 -#define RMI_DEBUGBUS_25__RB0WRREQCONSUMER_XBAR_WRREQ_RTR_PROBE0__SHIFT 0x00000005 -#define RMI_DEBUGBUS_25__RB1RDREQCONSUMER_XBAR_RDREQ_RTR_PROBE0__SHIFT 0x00000006 -#define RMI_DEBUGBUS_25__RB1WRREQCONSUMER_XBAR_WRREQ_RTR_PROBE0__SHIFT 0x00000007 -#define RMI_DEBUGBUS_25__RB1_WR_RTS_ARBITER_PROBE1__SHIFT 0x00000008 -#define RMI_DEBUGBUS_25__RB1_RD_RTS_ARBITER_PROBE1__SHIFT 0x00000009 -#define RMI_DEBUGBUS_25__RB0_WR_RTS_ARBITER_PROBE1__SHIFT 0x0000000a -#define RMI_DEBUGBUS_25__RB0_RD_RTS_ARBITER_PROBE1__SHIFT 0x0000000b -#define RMI_DEBUGBUS_25__RB1RDREQCONSUMER_XBAR_RDREQ_LAST_OF_REQ_BURST__SHIFT 0x0000000c -#define RMI_DEBUGBUS_25__RB0RDREQCONSUMER_XBAR_RDREQ_LAST_OF_REQ_BURST__SHIFT 0x0000000d -#define RMI_DEBUGBUS_25__RB0WRREQCONSUMER_XBAR_WRREQ_LAST_OF_REQ_BURST__SHIFT 0x0000000e -#define RMI_DEBUGBUS_25__RB1WRREQCONSUMER_XBAR_WRREQ_LAST_OF_REQ_BURST__SHIFT 0x0000000f -#define RMI_DEBUGBUS_25__RB0_WR_RTS_ARBITER_PROBE0__SHIFT 0x00000010 -#define RMI_DEBUGBUS_25__RB1_WR_RTS_ARBITER_PROBE0__SHIFT 0x00000011 -#define RMI_DEBUGBUS_25__RB0_RD_RTS_ARBITER_PROBE0__SHIFT 0x00000012 -#define RMI_DEBUGBUS_25__RB1_RD_RTS_ARBITER_PROBE0__SHIFT 0x00000013 -#define RMI_DEBUGBUS_25__RB0_WR_SEL__SHIFT 0x00000014 -#define RMI_DEBUGBUS_25__RB1_WR_SEL__SHIFT 0x00000015 -#define RMI_DEBUGBUS_25__RB0_RD_SEL__SHIFT 0x00000016 -#define RMI_DEBUGBUS_25__RB1_RD_SEL__SHIFT 0x00000017 -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB0_WR__SHIFT 0x00000018 -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB1_WR__SHIFT 0x00000019 -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB0_RD__SHIFT 0x0000001a -#define RMI_DEBUGBUS_25__IS_FROM_DB_RB1_RD__SHIFT 0x0000001b -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB0_WR__SHIFT 0x0000001c -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB1_WR__SHIFT 0x0000001d -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB0_RD__SHIFT 0x0000001e -#define RMI_DEBUGBUS_25__IS_FROM_CB_RB1_RD__SHIFT 0x0000001f - -// RMI_DEBUGBUS_26 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_OUT_DATA_FLOPPED_EN__SHIFT 0x00000000 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_OUT_RTS__SHIFT 0x00000001 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_GATED_BY_WEIGHTEDRR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_WAITING_FOR_END_OF_BURST__SHIFT 0x00000003 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_MASKED_REQUESTS_FOR_WRAPPING_REDUCED__SHIFT 0x00000004 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_MASKED_REQUESTS_REDUCED__SHIFT 0x00000005 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_OUT_STALLED__SHIFT 0x00000006 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_ARBITER_DISABLE_D__SHIFT 0x00000007 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_OUTPUT_STALLED__SHIFT 0x00000008 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_CURRENT_REQUEST_ID__SHIFT 0x00000009 -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQ_IN_RTR_FSM__SHIFT 0x0000000a -#define RMI_DEBUGBUS_26__DEMUX_ARBITER0_REQUEST_MASKS__SHIFT 0x0000000c -#define RMI_DEBUGBUS_26__Reserved0__SHIFT 0x0000000e - -// RMI_DEBUGBUS_27 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_OUT_DATA_FLOPPED_EN__SHIFT 0x00000000 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_OUT_RTS__SHIFT 0x00000001 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_GATED_BY_WEIGHTEDRR__SHIFT 0x00000002 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_WAITING_FOR_END_OF_BURST__SHIFT 0x00000003 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_MASKED_REQUESTS_FOR_WRAPPING_REDUCED__SHIFT 0x00000004 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_MASKED_REQUESTS_REDUCED__SHIFT 0x00000005 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_OUT_STALLED__SHIFT 0x00000006 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_ARBITER_DISABLE_D__SHIFT 0x00000007 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_OUTPUT_STALLED__SHIFT 0x00000008 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_CURRENT_REQUEST_ID__SHIFT 0x00000009 -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQ_IN_RTR_FSM__SHIFT 0x0000000a -#define RMI_DEBUGBUS_27__DEMUX_ARBITER1_REQUEST_MASKS__SHIFT 0x0000000c -#define RMI_DEBUGBUS_27__Reserved0__SHIFT 0x0000000e - -// RMI_DEBUGBUS_28 -#define RMI_DEBUGBUS_28__RUNNING_CNT0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_28__RUNNING_CNT1__SHIFT 0x0000000c -#define RMI_DEBUGBUS_28__PROBE0_SB_INVREQ_CLEAN__SHIFT 0x00000018 -#define RMI_DEBUGBUS_28__PROBE1_SB_INVREQ_CLEAN__SHIFT 0x00000019 -#define RMI_DEBUGBUS_28__RMI_SCOREBOARD_CP_VMID_INVAL_PROGRESS__SHIFT 0x0000001a -#define RMI_DEBUGBUS_28__CPF_RMI_INVREQ_FLUSHTYPE_INT__SHIFT 0x0000001b -#define RMI_DEBUGBUS_28__SB_PROBE_SESSION_ID_CURR__SHIFT 0x0000001c -#define RMI_DEBUGBUS_28__RTNFORMATTER0_SB_SESSION_ID__SHIFT 0x0000001d -#define RMI_DEBUGBUS_28__RTNFORMATTER1_SB_SESSION_ID__SHIFT 0x0000001e -#define RMI_DEBUGBUS_28__Reserved0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_29 -#define RMI_DEBUGBUS_29__SNAPSHOT_CNT0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_29__SNAPSHOT_CNT1__SHIFT 0x0000000c -#define RMI_DEBUGBUS_29__VMID_INVAL_FORCE_DONE__SHIFT 0x00000018 -#define RMI_DEBUGBUS_29__VMID_INVAL_WATCHDOG_IN_PROGRESS__SHIFT 0x00000019 -#define RMI_DEBUGBUS_29__RMI_SCOREBOARD_FLUSH_DONE_RB0__SHIFT 0x0000001a -#define RMI_DEBUGBUS_29__RMI_SCOREBOARD_FLUSH_DONE_RB1__SHIFT 0x0000001b -#define RMI_DEBUGBUS_29__CPF_RMI_INVREQ_CLEAN__SHIFT 0x0000001c -#define RMI_DEBUGBUS_29__CPF_RMI_INVREQ_START__SHIFT 0x0000001d -#define RMI_DEBUGBUS_29__CPF_RMI_INVREQ_CLEAN_NXT__SHIFT 0x0000001e -#define RMI_DEBUGBUS_29__Reserved0__SHIFT 0x0000001f - -// RMI_DEBUGBUS_30 -#define RMI_DEBUGBUS_30__UPDATE_SNAPSHOT_CNT0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_30__UPDATE_SNAPSHOT_CNT1__SHIFT 0x00000001 -#define RMI_DEBUGBUS_30__UPDATE_RUNNING_CNT0__SHIFT 0x00000002 -#define RMI_DEBUGBUS_30__UPDATE_RUNNING_CNT1__SHIFT 0x00000003 -#define RMI_DEBUGBUS_30__SB_PROBE_SESSION_ID_PREV__SHIFT 0x00000004 -#define RMI_DEBUGBUS_30__POP0_SB_XNACK_SESSION_ID__SHIFT 0x00000005 -#define RMI_DEBUGBUS_30__POP0_SB_XNACK_RBID__SHIFT 0x00000006 -#define RMI_DEBUGBUS_30__POP0_SB_XNACK_VALID__SHIFT 0x00000007 -#define RMI_DEBUGBUS_30__POP1_SB_XNACK_SESSION_ID__SHIFT 0x00000008 -#define RMI_DEBUGBUS_30__POP1_SB_XNACK_RBID__SHIFT 0x00000009 -#define RMI_DEBUGBUS_30__POP1_SB_XNACK_VALID__SHIFT 0x0000000a -#define RMI_DEBUGBUS_30__PROBE0_SB_RBID__SHIFT 0x0000000b -#define RMI_DEBUGBUS_30__PROBE0_SB_VALID__SHIFT 0x0000000c -#define RMI_DEBUGBUS_30__PROBE1_SB_RBID__SHIFT 0x0000000d -#define RMI_DEBUGBUS_30__PROBE1_SB_VALID__SHIFT 0x0000000e -#define RMI_DEBUGBUS_30__SB_PROBE_INVREQ_VMID_VEC__SHIFT 0x0000000f -#define RMI_DEBUGBUS_30__SB_PROBE_INVREQ_START__SHIFT 0x0000001f - -// RMI_DEBUGBUS_31 -#define RMI_DEBUGBUS_31__RTNFORMATTER_RB_SEND_TCIW0__SHIFT 0x00000000 -#define RMI_DEBUGBUS_31__SEND_BOTH_HALVES_TO_RB_TCIW0__SHIFT 0x00000001 -#define RMI_DEBUGBUS_31__CLT_TAG_STORE_OUT_VALID_TCIW0__SHIFT 0x00000002 -#define RMI_DEBUGBUS_31__CLT_TAG_STORE_OUT_RMIMASK_TCIW0__SHIFT 0x00000003 -#define RMI_DEBUGBUS_31__SKID_FIFO_OUT_RTR_TCIW0__SHIFT 0x00000005 -#define RMI_DEBUGBUS_31__SKID_FIFO_OUT_RTS_TCIW0__SHIFT 0x00000006 -#define RMI_DEBUGBUS_31__CLT_TAG_STORE_OUT_TMP_STORE_VALID_TCIW0__SHIFT 0x00000007 -#define RMI_DEBUGBUS_31__RTNFORMATTER_TCIW_TAG_FREE_TCIW0__SHIFT 0x00000008 -#define RMI_DEBUGBUS_31__STATE_TCIW0__SHIFT 0x00000009 -#define RMI_DEBUGBUS_31__Reserved0__SHIFT 0x0000000b - -// RMI_DEBUGBUS_32 -#define RMI_DEBUGBUS_32__RTNFORMATTER_RB_SEND_TCIW1__SHIFT 0x00000000 -#define RMI_DEBUGBUS_32__SEND_BOTH_HALVES_TO_RB_TCIW1__SHIFT 0x00000001 -#define RMI_DEBUGBUS_32__CLT_TAG_STORE_OUT_VALID_TCIW1__SHIFT 0x00000002 -#define RMI_DEBUGBUS_32__CLT_TAG_STORE_OUT_RMIMASK_TCIW1__SHIFT 0x00000003 -#define RMI_DEBUGBUS_32__SKID_FIFO_OUT_RTR_TCIW1__SHIFT 0x00000005 -#define RMI_DEBUGBUS_32__SKID_FIFO_OUT_RTS_TCIW1__SHIFT 0x00000006 -#define RMI_DEBUGBUS_32__CLT_TAG_STORE_OUT_TMP_STORE_VALID_TCIW1__SHIFT 0x00000007 -#define RMI_DEBUGBUS_32__RTNFORMATTER_TCIW_TAG_FREE_TCIW1__SHIFT 0x00000008 -#define RMI_DEBUGBUS_32__STATE_TCIW1__SHIFT 0x00000009 -#define RMI_DEBUGBUS_32__Reserved0__SHIFT 0x0000000b - -// DB_DEBUG_BUS_0 -#define DB_DEBUG_BUS_0__BUSY_DATA0__SHIFT 0x00000000 - -// DB_DEBUG_BUS_1 -#define DB_DEBUG_BUS_1__BUSY_DATA1__SHIFT 0x00000000 - -// DB_DEBUG_BUS_2 -#define DB_DEBUG_BUS_2__BUSY_DATA2__SHIFT 0x00000000 - -// DB_DEBUG_BUS_3 -#define DB_DEBUG_BUS_3__BUSY_DATA3__SHIFT 0x00000000 - -// DB_DEBUG_BUS_4 -#define DB_DEBUG_BUS_4__STALL_DATA0__SHIFT 0x00000000 - -// DB_DEBUG_BUS_5 -#define DB_DEBUG_BUS_5__STALL_DATA1__SHIFT 0x00000000 - -// DB_DEBUG_BUS_6 -#define DB_DEBUG_BUS_6__STALL_DATA2__SHIFT 0x00000000 - -// DB_DEBUG_BUS_7 -#define DB_DEBUG_BUS_7__STALL_DATA3__SHIFT 0x00000000 - -// DB_DEBUG_BUS_8 -#define DB_DEBUG_BUS_8__STALL_DATA4__SHIFT 0x00000000 - -// DB_DEBUG_BUS_9 -#define DB_DEBUG_BUS_9__STALL_DATA5__SHIFT 0x00000000 - -// DB_DEBUG_BUS_A -#define DB_DEBUG_BUS_A__STALL_DATA6__SHIFT 0x00000000 - -// DB_DEBUG_BUS_B -#define DB_DEBUG_BUS_B__INFO_DATA0__SHIFT 0x00000000 - -// DB_DEBUG_BUS_C -#define DB_DEBUG_BUS_C__INFO_DATA1__SHIFT 0x00000000 - -// DB_DEBUG_BUS_D -#define DB_DEBUG_BUS_D__INFO_DATA2__SHIFT 0x00000000 - -// DB_DEBUG_BUS_E -#define DB_DEBUG_BUS_E__INFO_DATA3__SHIFT 0x00000000 - -// DB_DEBUG_BUS_F -#define DB_DEBUG_BUS_F__INFO_DATA4__SHIFT 0x00000000 - -// ATC_L2_CNTL -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x00000000 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x00000003 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x00000006 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x00000007 -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x00000008 -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x0000000b - -// ATC_L2_CNTL2 -#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x00000000 -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x00000006 -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x00000008 -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x00000009 -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0x0000000c -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x0000000f - -// ATC_L2_DEBUG -#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x00000000 -#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x00000007 -#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x00000008 -#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x00000014 -#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x00000015 -#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x00000017 -#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x00000019 -#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x0000001a -#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x0000001b -#define ATC_L2_DEBUG__IFIFO_SEND_DELAY__SHIFT 0x0000001c - -// ATC_L2_DEBUG2 -#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x00000000 -#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000005 -#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x00000008 -#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x00000009 -#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0x0000000a -#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0x0000000b -#define ATC_L2_DEBUG2__ATS_SNOOP_OVERRIDE__SHIFT 0x0000000c -#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0x0000000d -#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x0000000f -#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x00000011 -#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x00000015 -#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_BY_ADDR_RANGE__SHIFT 0x00000016 -#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_BY_DOMAIN__SHIFT 0x00000017 -#define ATC_L2_DEBUG2__CGCG_OVERRIDE__SHIFT 0x00000018 - -// ATC_L2_CACHE_DATA0 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x00000000 -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x00000001 -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x00000002 -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x00000017 - -// ATC_L2_CACHE_DATA1 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x00000000 - -// ATC_L2_CACHE_DATA2 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x00000000 - -// ATC_L2_CNTL3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x00000000 -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x00000003 - -// ATC_L2_STATUS -#define ATC_L2_STATUS__BUSY__SHIFT 0x00000000 -#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x00000001 - -// ATC_L2_STATUS2 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x00000000 -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x00000008 - -// ATC_L2_MISC_CG -#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x00000006 -#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x00000012 -#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013 - -// ATC_L2_MEM_POWER_LS -#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000 -#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006 - -// ATC_L2_CGTT_CLK_CTRL -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0x0000000f -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x00000010 -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x00000018 - -// ATC_L2_PERFCOUNTER_LO -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x00000000 - -// ATC_L2_PERFCOUNTER_HI -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x00000000 -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x00000010 - -// ATC_L2_PERFCOUNTER0_CFG -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x00000000 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x00000018 -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x0000001c -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x0000001d - -// ATC_L2_PERFCOUNTER1_CFG -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x00000000 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x00000018 -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x0000001c -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x0000001d - -// ATC_L2_PERFCOUNTER_RSLT_CNTL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x00000008 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x00000010 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x00000018 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x00000019 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x0000001a - -// VM_L2_CNTL -#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x00000000 -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x00000001 -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x00000002 -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x00000004 -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x00000008 -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x00000009 -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x0000000a -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x0000000b -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0x0000000c -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0x0000000f -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x00000012 -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x00000013 -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x00000015 -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x0000001a - -// VM_L2_CNTL2 -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x00000000 -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x00000001 -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x00000015 -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x00000016 -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x00000017 -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x0000001a -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x0000001c - -// VM_L2_CNTL3 -#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x00000000 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x00000006 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x00000008 -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x0000000f -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x00000014 -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x00000015 -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x00000018 -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x0000001c -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x0000001d -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x0000001e -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x0000001f - -// VM_L2_STATUS -#define VM_L2_STATUS__L2_BUSY__SHIFT 0x00000000 -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x00000001 -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x00000011 -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x00000012 -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x00000013 -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x00000014 -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x00000015 - -// VM_DUMMY_PAGE_FAULT_CNTL -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x00000000 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x00000001 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x00000002 - -// VM_DUMMY_PAGE_FAULT_ADDR_LO32 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x00000000 - -// VM_DUMMY_PAGE_FAULT_ADDR_HI32 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x00000000 - -// VM_L2_PROTECTION_FAULT_CNTL -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT \ - 0x00000001 -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000002 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000003 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000005 -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT \ - 0x00000006 -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000008 -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000009 -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000b -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0000000d -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0000001d -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x0000001e -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x0000001f - -// VM_L2_PROTECTION_FAULT_CNTL2 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x00000000 -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x00000010 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x00000011 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x00000012 -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x00000013 - -// VM_L2_PROTECTION_FAULT_MM_CNTL3 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT \ - 0x00000000 - -// VM_L2_PROTECTION_FAULT_MM_CNTL4 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT \ - 0x00000000 - -// VM_L2_PROTECTION_FAULT_STATUS -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x00000000 -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x00000001 -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x00000004 -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x00000008 -#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x00000009 -#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x00000012 -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x00000013 -#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000014 -#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x00000018 -#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x00000019 - -// VM_L2_PROTECTION_FAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x00000000 - -// VM_L2_PROTECTION_FAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x00000000 - -// VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x00000000 - -// VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x00000000 - -// VM_DEBUG -#define VM_DEBUG__FLAGS__SHIFT 0x00000000 - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x00000000 - -// VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x00000000 - -// VM_L2_CNTL4 -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x00000000 -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x00000006 -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x00000007 -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x00000008 -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x00000012 -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x0000001c - -// VM_L2_MM_GROUP_RT_CLASSES -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x00000000 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x00000001 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x00000002 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x00000003 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x00000004 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x00000005 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x00000006 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x00000007 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x00000008 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x00000009 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0x0000000a -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0x0000000b -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0x0000000c -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0x0000000d -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0x0000000e -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0x0000000f -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x00000010 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x00000011 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x00000012 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x00000013 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x00000014 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x00000015 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x00000016 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x00000017 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x00000018 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x00000019 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x0000001a -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x0000001b -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x0000001c -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x0000001d -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x0000001e -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x0000001f - -// VM_L2_BANK_SELECT_RESERVED_CID -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x00000000 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0x0000000a -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x00000014 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x00000018 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x00000019 - -// VM_L2_BANK_SELECT_RESERVED_CID2 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x00000000 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0x0000000a -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x00000014 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x00000018 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x00000019 - -// VM_L2_CACHE_PARITY_CNTL -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x00000000 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x00000001 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x00000002 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x00000003 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x00000004 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x00000005 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x00000006 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x00000009 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0x0000000c - -// VM_L2_IH_LOG_CNTL -#define VM_L2_IH_LOG_CNTL__ENABLE_LOGGING__SHIFT 0x00000000 -#define VM_L2_IH_LOG_CNTL__USE_L_BIT__SHIFT 0x00000001 -#define VM_L2_IH_LOG_CNTL__REGISTER_ADDRESS__SHIFT 0x00000002 -#define VM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS__SHIFT 0x00000014 - -// VM_L2_IH_LOG_BUSY -#define VM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY__SHIFT 0x00000000 -#define VM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY__SHIFT 0x00000010 - -// VM_L2_CGTT_CLK_CTRL -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0x0000000f -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x00000010 -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x00000018 - -// VML2_SEC_MASTER -#define VML2_SEC_MASTER__UNIT_ID__SHIFT 0x00000000 -#define VML2_SEC_MASTER__TRUST_LEVEL__SHIFT 0x00000006 - -// VM_CONTEXT0_CNTL -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT1_CNTL -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT2_CNTL -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT3_CNTL -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT4_CNTL -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT5_CNTL -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT6_CNTL -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT7_CNTL -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT8_CNTL -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT9_CNTL -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT10_CNTL -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT11_CNTL -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT12_CNTL -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT13_CNTL -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT14_CNTL -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXT15_CNTL -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000003 -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x00000007 -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x00000008 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000b -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000c -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000d -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000e -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000011 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000012 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000013 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000014 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 -#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000017 -#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000018 - -// VM_CONTEXTS_DISABLE -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x00000000 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x00000001 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x00000002 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x00000003 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x00000004 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x00000005 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x00000006 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x00000007 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x00000008 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x00000009 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0x0000000a -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0x0000000b -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0x0000000c -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0x0000000d -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0x0000000e -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0x0000000f - -// VM_INVALIDATE_ENG0_SEM -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG1_SEM -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG2_SEM -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG3_SEM -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG4_SEM -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG5_SEM -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG6_SEM -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG7_SEM -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG8_SEM -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG9_SEM -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG10_SEM -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG11_SEM -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG12_SEM -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG13_SEM -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG14_SEM -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG15_SEM -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG16_SEM -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG17_SEM -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG0_REQ -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG1_REQ -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG2_REQ -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG3_REQ -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG4_REQ -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG5_REQ -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG6_REQ -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG7_REQ -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG8_REQ -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG9_REQ -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG10_REQ -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG11_REQ -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG12_REQ -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG13_REQ -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG14_REQ -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG15_REQ -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG16_REQ -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG17_REQ -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x00000010 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x00000012 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x00000013 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x00000014 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x00000015 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x00000016 -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000017 -#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x00000018 - -// VM_INVALIDATE_ENG0_ACK -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG1_ACK -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG2_ACK -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG3_ACK -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG4_ACK -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG5_ACK -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG6_ACK -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG7_ACK -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG8_ACK -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG9_ACK -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG10_ACK -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG11_ACK -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG12_ACK -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG13_ACK -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG14_ACK -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG15_ACK -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG16_ACK -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG17_ACK -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x00000010 - -// VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x00000000 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x00000001 - -// VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x00000000 - -// VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x00000000 - -// VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x00000000 - -// VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x00000000 - -// VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x00000000 - -// MC_VM_L2_PERFCOUNTER0_CFG -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER1_CFG -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER2_CFG -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER3_CFG -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER4_CFG -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER5_CFG -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER6_CFG -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER7_CFG -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x0000001c -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x0000001d - -// MC_VM_L2_PERFCOUNTER_RSLT_CNTL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x00000008 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x00000010 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x00000018 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x00000019 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x0000001a - -// MC_VM_L2_PERFCOUNTER_LO -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x00000000 - -// MC_VM_L2_PERFCOUNTER_HI -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x00000000 -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF1 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF2 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF3 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF4 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF5 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF6 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF7 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF8 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF9 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF11 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF12 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF13 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF14 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x00000010 - -// MC_VM_FB_SIZE_OFFSET_VF15 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x00000000 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x00000010 - -// VM_IOMMU_MMIO_CNTRL_1 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x00000008 - -// MC_VM_MARC_BASE_LO_0 -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0x0000000c - -// MC_VM_MARC_BASE_LO_1 -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0x0000000c - -// MC_VM_MARC_BASE_LO_2 -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0x0000000c - -// MC_VM_MARC_BASE_LO_3 -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0x0000000c - -// MC_VM_MARC_BASE_HI_0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x00000000 - -// MC_VM_MARC_BASE_HI_1 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x00000000 - -// MC_VM_MARC_BASE_HI_2 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x00000000 - -// MC_VM_MARC_BASE_HI_3 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x00000000 - -// MC_VM_MARC_RELOC_LO_0 -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x00000000 -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x00000001 -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0x0000000c - -// MC_VM_MARC_RELOC_LO_1 -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x00000000 -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x00000001 -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0x0000000c - -// MC_VM_MARC_RELOC_LO_2 -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x00000000 -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x00000001 -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0x0000000c - -// MC_VM_MARC_RELOC_LO_3 -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x00000000 -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x00000001 -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0x0000000c - -// MC_VM_MARC_RELOC_HI_0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x00000000 - -// MC_VM_MARC_RELOC_HI_1 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x00000000 - -// MC_VM_MARC_RELOC_HI_2 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x00000000 - -// MC_VM_MARC_RELOC_HI_3 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x00000000 - -// MC_VM_MARC_LEN_LO_0 -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0x0000000c - -// MC_VM_MARC_LEN_LO_1 -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0x0000000c - -// MC_VM_MARC_LEN_LO_2 -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0x0000000c - -// MC_VM_MARC_LEN_LO_3 -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0x0000000c - -// MC_VM_MARC_LEN_HI_0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x00000000 - -// MC_VM_MARC_LEN_HI_1 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x00000000 - -// MC_VM_MARC_LEN_HI_2 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x00000000 - -// MC_VM_MARC_LEN_HI_3 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x00000000 - -// VM_IOMMU_CONTROL_REGISTER -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x00000000 - -// VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0x0000000d - -// VM_PCIE_ATS_CNTL -#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x00000010 -#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_0 -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_1 -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_2 -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_3 -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_4 -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_5 -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_6 -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_7 -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_8 -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_9 -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_10 -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_11 -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_12 -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_13 -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_14 -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x0000001f - -// VM_PCIE_ATS_CNTL_VF_15 -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x0000001f - -// UTCL2_CGTT_CLK_CTRL -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0x0000000c -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0x0000000f -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x00000010 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x00000018 - -// MC_VM_NB_MMIOBASE -#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x00000000 - -// MC_VM_NB_MMIOLIMIT -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x00000000 - -// MC_VM_NB_PCI_CTRL -#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x00000017 - -// MC_VM_NB_PCI_ARB -#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x00000003 - -// MC_VM_NB_TOP_OF_DRAM_SLOT1 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x00000017 - -// MC_VM_NB_LOWER_TOP_OF_DRAM2 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x00000000 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x00000017 - -// MC_VM_NB_UPPER_TOP_OF_DRAM2 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x00000000 - -// MC_VM_FB_OFFSET -#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x00000000 - -// MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x00000000 - -// MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x00000000 - -// MC_VM_STEERING -#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x00000000 - -// MC_SHARED_VIRT_RESET_REQ -#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x00000000 -#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x0000001f - -// MC_MEM_POWER_LS -#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000 -#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006 - -// MC_VM_CACHEABLE_DRAM_ADDRESS_START -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x00000000 - -// MC_VM_CACHEABLE_DRAM_ADDRESS_END -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x00000000 - -// MC_VM_APT_CNTL -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x00000000 -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x00000001 - -// MC_VM_LOCAL_HBM_ADDRESS_START -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x00000000 - -// MC_VM_LOCAL_HBM_ADDRESS_END -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x00000000 - -// MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x00000000 - -// MC_VM_FB_LOCATION_BASE -#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x00000000 - -// MC_VM_FB_LOCATION_TOP -#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x00000000 - -// MC_VM_AGP_TOP -#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x00000000 - -// MC_VM_AGP_BOT -#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x00000000 - -// MC_VM_AGP_BASE -#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x00000000 - -// MC_VM_SYSTEM_APERTURE_LOW_ADDR -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x00000000 - -// MC_VM_SYSTEM_APERTURE_HIGH_ADDR -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x00000000 - -// MC_VM_MX_L1_TLB_CNTL -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x00000000 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x00000003 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x00000005 -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x00000006 -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x00000007 -#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0x0000000b -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0x0000000d - -// GCEA_DRAM_RD_CLI2GRP_MAP0 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x00000000 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x00000002 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x00000004 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x00000006 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x00000008 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0x0000000a -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0x0000000c -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0x0000000e -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x00000010 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x00000012 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x00000014 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x00000016 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x00000018 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x0000001a -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x0000001c -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x0000001e - -// GCEA_DRAM_RD_CLI2GRP_MAP1 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x00000000 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x00000002 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x00000004 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x00000006 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x00000008 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0x0000000a -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0x0000000c -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0x0000000e -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x00000010 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x00000012 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x00000014 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x00000016 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x00000018 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x0000001a -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x0000001c -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x0000001e - -// GCEA_DRAM_WR_CLI2GRP_MAP0 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x00000000 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x00000002 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x00000004 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x00000006 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x00000008 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0x0000000a -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0x0000000c -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0x0000000e -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x00000010 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x00000012 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x00000014 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x00000016 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x00000018 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x0000001a -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x0000001c -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x0000001e - -// GCEA_DRAM_WR_CLI2GRP_MAP1 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x00000000 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x00000002 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x00000004 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x00000006 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x00000008 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0x0000000a -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0x0000000c -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0x0000000e -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x00000010 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x00000012 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x00000014 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x00000016 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x00000018 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x0000001a -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x0000001c -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x0000001e - -// GCEA_DRAM_RD_GRP2VC_MAP -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x00000000 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x00000003 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x00000006 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x00000009 - -// GCEA_DRAM_WR_GRP2VC_MAP -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x00000000 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x00000003 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x00000006 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x00000009 - -// GCEA_DRAM_RD_LAZY -#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x00000000 -#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x00000003 -#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x00000006 -#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x00000009 - -// GCEA_DRAM_WR_LAZY -#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x00000000 -#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x00000003 -#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x00000006 -#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x00000009 - -// GCEA_DRAM_RD_CAM_CNTL -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x00000000 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x00000004 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x00000008 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0x0000000c -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x00000010 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x00000013 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x00000016 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x00000019 - -// GCEA_DRAM_WR_CAM_CNTL -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x00000000 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x00000004 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x00000008 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0x0000000c -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x00000010 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x00000013 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x00000016 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x00000019 - -// GCEA_DRAM_PAGE_BURST -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x00000000 -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x00000008 -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x00000010 -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x00000018 - -// GCEA_DRAM_RD_PRI_AGE -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x00000000 -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x00000003 -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x00000006 -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x00000009 -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0x0000000c -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0x0000000f -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x00000012 -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x00000015 - -// GCEA_DRAM_WR_PRI_AGE -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x00000000 -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x00000003 -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x00000006 -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x00000009 -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0x0000000c -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0x0000000f -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x00000012 -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x00000015 - -// GCEA_DRAM_RD_PRI_QUEUING -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_DRAM_WR_PRI_QUEUING -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_DRAM_RD_PRI_FIXED -#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_DRAM_WR_PRI_FIXED -#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_DRAM_RD_PRI_URGENCY -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x00000009 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0x0000000c -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0x0000000d -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0x0000000e -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0x0000000f - -// GCEA_DRAM_WR_PRI_URGENCY -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x00000009 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0x0000000c -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0x0000000d -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0x0000000e -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0x0000000f - -// GCEA_DRAM_RD_PRI_QUANT_PRI1 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_DRAM_RD_PRI_QUANT_PRI2 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_DRAM_RD_PRI_QUANT_PRI3 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_DRAM_WR_PRI_QUANT_PRI1 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_DRAM_WR_PRI_QUANT_PRI2 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_DRAM_WR_PRI_QUANT_PRI3 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_ADDRNORM_BASE_ADDR0 -#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x00000000 -#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x00000001 -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x00000004 -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x00000008 -#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0x0000000c - -// GCEA_ADDRNORM_LIMIT_ADDR0 -#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x00000000 -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x00000008 -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0x0000000a -#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0x0000000c - -// GCEA_ADDRNORM_BASE_ADDR1 -#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x00000000 -#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x00000001 -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x00000004 -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x00000008 -#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0x0000000c - -// GCEA_ADDRNORM_LIMIT_ADDR1 -#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x00000000 -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x00000008 -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0x0000000a -#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0x0000000c - -// GCEA_ADDRNORM_OFFSET_ADDR1 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x00000000 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x00000014 - -// GCEA_ADDRNORM_HOLE_CNTL -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x00000000 -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x00000007 - -// GCEA_ADDRDEC_BANK_CFG -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x00000000 -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x00000005 -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0x0000000a -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0x0000000d -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x00000010 -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x00000011 - -// GCEA_ADDRDEC_MISC_CFG -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x00000000 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x00000001 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x00000002 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x00000003 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x00000004 -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x00000008 -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x00000009 -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0x0000000c -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x00000010 -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x00000014 -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x00000016 -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x00000018 -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x0000001b - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x00000001 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0x0000000e - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x00000001 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0x0000000e - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x00000001 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0x0000000e - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x00000001 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0x0000000e - -// GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x00000001 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0x0000000e - -// GCEA_ADDRDECDRAM_ADDR_HASH_PC -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x00000001 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0x0000000e - -// GCEA_ADDRDECDRAM_ADDR_HASH_PC2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x00000000 - -// GCEA_ADDRDECDRAM_ADDR_HASH_CS0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x00000001 - -// GCEA_ADDRDECDRAM_ADDR_HASH_CS1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x00000001 - -// GCEA_ADDRDECDRAM_HARVEST_ENABLE -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x00000000 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x00000001 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x00000002 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x00000003 - -// GCEA_ADDRDEC0_BASE_ADDR_CS0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_BASE_ADDR_CS1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_BASE_ADDR_CS2 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_BASE_ADDR_CS3 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_ADDR_MASK_CS01 -#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_ADDR_MASK_CS23 -#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC0_ADDR_CFG_CS01 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x00000002 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x00000014 - -// GCEA_ADDRDEC0_ADDR_CFG_CS23 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x00000002 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x00000014 - -// GCEA_ADDRDEC0_ADDR_SEL_CS01 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x00000018 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x0000001c - -// GCEA_ADDRDEC0_ADDR_SEL_CS23 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x00000018 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x0000001c - -// GCEA_ADDRDEC0_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x00000014 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x00000018 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x0000001c - -// GCEA_ADDRDEC0_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x00000014 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x00000018 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x0000001c - -// GCEA_ADDRDEC0_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x00000014 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x00000018 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x0000001c - -// GCEA_ADDRDEC0_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x00000014 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x00000018 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x0000001c - -// GCEA_ADDRDEC0_RM_SEL_CS01 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_ADDRDEC0_RM_SEL_CS23 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_ADDRDEC0_RM_SEL_SECCS01 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_ADDRDEC0_RM_SEL_SECCS23 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_ADDRDEC1_BASE_ADDR_CS0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_BASE_ADDR_CS1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_BASE_ADDR_CS2 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_BASE_ADDR_CS3 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_ADDR_MASK_CS01 -#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_ADDR_MASK_CS23 -#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x00000001 - -// GCEA_ADDRDEC1_ADDR_CFG_CS01 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x00000002 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x00000014 - -// GCEA_ADDRDEC1_ADDR_CFG_CS23 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x00000002 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x00000014 - -// GCEA_ADDRDEC1_ADDR_SEL_CS01 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x00000018 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x0000001c - -// GCEA_ADDRDEC1_ADDR_SEL_CS23 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x00000018 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x0000001c - -// GCEA_ADDRDEC1_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x00000014 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x00000018 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x0000001c - -// GCEA_ADDRDEC1_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x00000014 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x00000018 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x0000001c - -// GCEA_ADDRDEC1_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x00000014 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x00000018 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x0000001c - -// GCEA_ADDRDEC1_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x00000014 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x00000018 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x0000001c - -// GCEA_ADDRDEC1_RM_SEL_CS01 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_ADDRDEC1_RM_SEL_CS23 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_ADDRDEC1_RM_SEL_SECCS01 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_ADDRDEC1_RM_SEL_SECCS23 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x00000000 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x00000004 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x00000008 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0x0000000c -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x00000010 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x00000012 - -// GCEA_IO_RD_CLI2GRP_MAP0 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x00000000 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x00000002 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x00000004 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x00000006 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x00000008 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0x0000000a -#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0x0000000c -#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0x0000000e -#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x00000010 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x00000012 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x00000014 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x00000016 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x00000018 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x0000001a -#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x0000001c -#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x0000001e - -// GCEA_IO_RD_CLI2GRP_MAP1 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x00000000 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x00000002 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x00000004 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x00000006 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x00000008 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0x0000000a -#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0x0000000c -#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0x0000000e -#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x00000010 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x00000012 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x00000014 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x00000016 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x00000018 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x0000001a -#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x0000001c -#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x0000001e - -// GCEA_IO_WR_CLI2GRP_MAP0 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x00000000 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x00000002 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x00000004 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x00000006 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x00000008 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0x0000000a -#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0x0000000c -#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0x0000000e -#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x00000010 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x00000012 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x00000014 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x00000016 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x00000018 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x0000001a -#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x0000001c -#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x0000001e - -// GCEA_IO_WR_CLI2GRP_MAP1 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x00000000 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x00000002 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x00000004 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x00000006 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x00000008 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0x0000000a -#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0x0000000c -#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0x0000000e -#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x00000010 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x00000012 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x00000014 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x00000016 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x00000018 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x0000001a -#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x0000001c -#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x0000001e - -// GCEA_IO_RD_COMBINE_FLUSH -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x00000000 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x00000004 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x00000008 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0x0000000c - -// GCEA_IO_WR_COMBINE_FLUSH -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x00000000 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x00000004 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x00000008 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0x0000000c - -// GCEA_IO_GROUP_BURST -#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x00000000 -#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x00000008 -#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x00000010 -#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x00000018 - -// GCEA_IO_RD_PRI_AGE -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x00000003 -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x00000006 -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x00000009 -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0x0000000c -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0x0000000f -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x00000012 -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x00000015 - -// GCEA_IO_WR_PRI_AGE -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x00000003 -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x00000006 -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x00000009 -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0x0000000c -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0x0000000f -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x00000012 -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x00000015 - -// GCEA_IO_RD_PRI_QUEUING -#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_IO_WR_PRI_QUEUING -#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_IO_RD_PRI_FIXED -#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_IO_WR_PRI_FIXED -#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x00000009 - -// GCEA_IO_RD_PRI_URGENCY -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x00000009 -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0x0000000c -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0x0000000d -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0x0000000e -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0x0000000f - -// GCEA_IO_WR_PRI_URGENCY -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x00000003 -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x00000006 -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x00000009 -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0x0000000c -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0x0000000d -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0x0000000e -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0x0000000f - -// GCEA_IO_RD_PRI_URGENCY_MASK -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x00000001 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x00000002 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x00000003 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x00000004 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x00000005 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x00000006 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x00000007 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x00000008 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x00000009 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0x0000000a -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0x0000000b -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0x0000000c -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0x0000000d -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0x0000000e -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0x0000000f -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x00000010 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x00000011 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x00000012 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x00000013 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x00000014 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x00000015 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x00000016 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x00000017 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x00000018 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x00000019 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x0000001a -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x0000001b -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x0000001c -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x0000001d -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x0000001e -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x0000001f - -// GCEA_IO_WR_PRI_URGENCY_MASK -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x00000001 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x00000002 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x00000003 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x00000004 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x00000005 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x00000006 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x00000007 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x00000008 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x00000009 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0x0000000a -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0x0000000b -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0x0000000c -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0x0000000d -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0x0000000e -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0x0000000f -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x00000010 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x00000011 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x00000012 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x00000013 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x00000014 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x00000015 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x00000016 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x00000017 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x00000018 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x00000019 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x0000001a -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x0000001b -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x0000001c -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x0000001d -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x0000001e -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x0000001f - -// GCEA_IO_RD_PRI_QUANT_PRI1 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_IO_RD_PRI_QUANT_PRI2 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_IO_RD_PRI_QUANT_PRI3 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_IO_WR_PRI_QUANT_PRI1 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_IO_WR_PRI_QUANT_PRI2 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_IO_WR_PRI_QUANT_PRI3 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x00000000 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x00000010 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x00000018 - -// GCEA_SDP_ARB_DRAM -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x00000000 -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x00000008 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x00000010 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x00000011 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x00000012 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x00000013 -#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x00000014 - -// GCEA_SDP_ARB_FINAL -#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x00000000 -#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x00000005 -#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0x0000000a -#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0x0000000f -#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x00000011 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x00000012 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x00000013 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x00000014 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x00000015 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x00000016 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x00000017 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x00000018 -#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x00000019 -#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x0000001a - -// GCEA_SDP_DRAM_PRIORITY -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x00000000 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x00000004 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x00000008 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0x0000000c -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x00000010 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x00000014 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x00000018 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x0000001c - -// GCEA_SDP_IO_PRIORITY -#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x00000000 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x00000004 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x00000008 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0x0000000c -#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x00000010 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x00000014 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x00000018 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x0000001c - -// GCEA_SDP_CREDITS -#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x00000000 -#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x00000008 -#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x00000010 -#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x00000018 - -// GCEA_SDP_TAG_RESERVE0 -#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x00000000 -#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x00000008 -#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x00000010 -#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x00000018 - -// GCEA_SDP_TAG_RESERVE1 -#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x00000000 -#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x00000008 -#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x00000010 -#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x00000018 - -// GCEA_SDP_VCC_RESERVE0 -#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x00000000 -#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x00000006 -#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0x0000000c -#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x00000012 -#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x00000018 - -// GCEA_SDP_VCC_RESERVE1 -#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x00000000 -#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x00000006 -#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0x0000000c -#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x0000001f - -// GCEA_SDP_VCD_RESERVE0 -#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x00000000 -#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x00000006 -#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0x0000000c -#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x00000012 -#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x00000018 - -// GCEA_SDP_VCD_RESERVE1 -#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x00000000 -#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x00000006 -#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0x0000000c -#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x0000001f - -// GCEA_SDP_REQ_CNTL -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x00000000 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x00000001 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x00000002 -#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x00000003 -#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x00000004 - -// GCEA_MISC -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x00000000 -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x00000001 -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x00000002 -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x00000003 -#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x00000004 -#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x00000005 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x00000006 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x00000007 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x00000008 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x00000009 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x0000000a -#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x0000000b -#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x0000000c -#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x0000000d -#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x0000000e -#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x0000000f -#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x00000011 -#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x00000013 -#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x00000015 -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x0000001a -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x0000001b -#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x0000001c -#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x0000001d -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x0000001e -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x0000001f - -// GCEA_LATENCY_SAMPLING -#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x00000000 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x00000001 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x00000002 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x00000003 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x00000004 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x00000005 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x00000006 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x00000007 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x00000008 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x00000009 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0x0000000a -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0x0000000b -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0x0000000c -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0x0000000d -#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0x0000000e -#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x00000016 - -// GCEA_PERFCOUNTER_LO -#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x00000000 - -// GCEA_PERFCOUNTER_HI -#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x00000000 -#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x00000010 - -// GCEA_PERFCOUNTER0_CFG -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x00000000 -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x00000018 -#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x0000001c -#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x0000001d - -// GCEA_PERFCOUNTER1_CFG -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x00000000 -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x00000008 -#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x00000018 -#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x0000001c -#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x0000001d - -// GCEA_PERFCOUNTER_RSLT_CNTL -#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 -#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x00000008 -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x00000010 -#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x00000018 -#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x00000019 -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x0000001a - -// GCEA_MAM_CTRL -#define GCEA_MAM_CTRL__ADRAM_MODE__SHIFT 0x00000000 -#define GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE__SHIFT 0x00000002 -#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD__SHIFT 0x00000003 -#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE__SHIFT 0x00000006 -#define GCEA_MAM_CTRL__ARAM_FORCE_FLUSH__SHIFT 0x00000007 -#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x00000008 -#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x0000000b -#define GCEA_MAM_CTRL__ALOG_ACTIVE__SHIFT 0x0000000c -#define GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT 0x0000000d -#define GCEA_MAM_CTRL__CLIENT_ID__SHIFT 0x00000011 -#define GCEA_MAM_CTRL__MAM_DISABLE__SHIFT 0x00000016 -#define GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE__SHIFT 0x00000017 -#define GCEA_MAM_CTRL__ALOG_MODE__SHIFT 0x0000001b -#define GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW__SHIFT 0x0000001c -#define GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT__SHIFT 0x0000001f - -// GCEA_MAM_CTRL2 -#define GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD__SHIFT 0x00000000 -#define GCEA_MAM_CTRL2__ALOG_SPACE__SHIFT 0x00000002 -#define GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT 0x00000004 -#define GCEA_MAM_CTRL2__ADDR_HI__SHIFT 0x0000001c - -// GCEA_MAM_ARAM_FLUSH_ADDR_LO -#define GCEA_MAM_ARAM_FLUSH_ADDR_LO__ADDR_LO__SHIFT 0x00000000 - -// GCEA_MAM_DBIT_QUERY -#define GCEA_MAM_DBIT_QUERY__QUERY_EN__SHIFT 0x00000000 -#define GCEA_MAM_DBIT_QUERY__DBIT_PRESERVE__SHIFT 0x00000001 -#define GCEA_MAM_DBIT_QUERY__RESERVED_FIELD__SHIFT 0x00000002 -#define GCEA_MAM_DBIT_QUERY__QUERY_ADDR_LO__SHIFT 0x00000004 - -// GCEA_MAM_STATUS -#define GCEA_MAM_STATUS__DBIT_QUERY_RDY__SHIFT 0x00000000 -#define GCEA_MAM_STATUS__DBIT_QUERY_DIRTY__SHIFT 0x00000001 -#define GCEA_MAM_STATUS__ALOG_CLEAN__SHIFT 0x00000002 -#define GCEA_MAM_STATUS__ALOG_IDLE__SHIFT 0x00000003 -#define GCEA_MAM_STATUS__RESERVED_FIELD__SHIFT 0x00000004 - -// GCEA_EDC_CNT -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x00000000 -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x00000002 -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x00000004 -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x00000006 -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x00000008 -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0x0000000a -#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0x0000000c -#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0x0000000e -#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x00000010 -#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x00000012 -#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x00000014 -#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x00000016 -#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x00000018 -#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x0000001a -#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x0000001c - -// GCEA_EDC_CNT2 -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x00000000 -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x00000002 -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x00000004 -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x00000006 -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x00000008 -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0x0000000a -#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0x0000000c -#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0x0000000e -#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x00000010 -#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x00000012 -#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x00000014 -#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x00000016 - -// GCEA_DSM_CNTL -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000003 -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000006 -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 -#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000009 -#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000b -#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x0000000c -#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000e -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0000000f -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000011 -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000012 -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000014 -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000015 -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000017 - -// GCEA_DSM_CNTLA -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000003 -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000006 -#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000009 -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000b -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x0000000c -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000e -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0000000f -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000011 -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x00000012 -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000014 - -// GCEA_DSM_CNTLB -#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x00000000 -#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000002 -#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x00000003 -#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000005 -#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x00000006 -#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x00000008 -#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x00000009 -#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0x0000000b - -// GCEA_DSM_CNTL2 -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0000000f -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x00000011 -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000012 -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x00000014 -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000015 -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x00000017 -#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x0000001a - -// GCEA_DSM_CNTL2A -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x0000000b -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x0000000c -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x0000000e -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0000000f -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x00000011 -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x00000012 -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x00000014 - -// GCEA_DSM_CNTL2B -#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x00000000 -#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x00000002 -#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x00000003 -#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x00000005 -#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x00000006 -#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x00000008 -#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x00000009 -#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0x0000000b - -// GCEA_TCC_XBR_CREDITS -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x00000000 -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x00000006 -#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x00000008 -#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0x0000000e -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x00000010 -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x00000016 -#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x00000018 -#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x0000001e - -// GCEA_TCC_XBR_MAXBURST -#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x00000000 -#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x00000004 -#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x00000008 -#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0x0000000c - -// GCEA_PROBE_CNTL -#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x00000000 -#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x00000005 - -// GCEA_PROBE_MAP -#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x00000000 -#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x00000001 -#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x00000002 -#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x00000003 -#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x00000004 -#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x00000005 -#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x00000006 -#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x00000007 -#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x00000008 -#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x00000009 -#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0x0000000a -#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0x0000000b -#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0x0000000c -#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0x0000000d -#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0x0000000e -#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0x0000000f -#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x00000010 - -// GCEA_ERR_STATUS -#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x00000000 -#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x00000004 -#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x00000008 -#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x00000009 -#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0x0000000a - -// GCEA_MISC2 -#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x00000000 -#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x00000001 -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x00000002 -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x00000007 - -// GCEA_SDP_BACKDOOR_CMDCREDITS0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x00000000 - -// GCEA_SDP_BACKDOOR_CMDCREDITS1 -#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x00000000 - -// GCEA_SDP_BACKDOOR_DATACREDITS0 -#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x00000000 - -// GCEA_SDP_BACKDOOR_DATACREDITS1 -#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x00000000 - -// GCEA_SDP_BACKDOOR_MISCCREDITS -#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x00000000 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x00000008 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x00000010 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x00000017 - -// GCEA_SDP_ENABLE -#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x00000000 - -// GCEA_CGTT_CLK_CTRL -#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 -#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 -#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x00000016 -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x0000001e -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x0000001f - -// GCEA_SECURE_CTRL -#define GCEA_SECURE_CTRL__SECLEVEL__SHIFT 0x00000000 -#define GCEA_SECURE_CTRL__TMZ__SHIFT 0x00000003 -#define GCEA_SECURE_CTRL__CREST_OFFSET__SHIFT 0x00000004 - -} // gfx9 -} // pm4_profile - -#endif diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_typedef.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_typedef.h deleted file mode 100644 index c9652d5aba..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_typedef.h +++ /dev/null @@ -1,10759 +0,0 @@ -#if !defined(_greenland_TYPEDEF_HEADER) -#define _greenland_TYPEDEF_HEADER -/* -* gfx9_typedef.h -* -* Register Spec Release: -* -* -* (c) 2000 ATI Technologies Inc. (unpublished) -* -* All rights reserved. This notice is intended as a precaution against -* inadvertent publication and does not imply publication or any waiver -* of confidentiality. The year included in the foregoing notice is the -* year of creation of the work. -* -*/ - -#include "gfx9_registers.h" - -namespace pm4_profile { -namespace gfx9 { - -typedef union ATC_ATS_CNTL regATC_ATS_CNTL; -typedef union ATC_ATS_DEBUG regATC_ATS_DEBUG; -typedef union ATC_ATS_FAULT_DEBUG regATC_ATS_FAULT_DEBUG; -typedef union ATC_ATS_STATUS regATC_ATS_STATUS; -typedef union ATC_ATS_FAULT_CNTL regATC_ATS_FAULT_CNTL; -typedef union ATC_ATS_FAULT_STATUS_INFO regATC_ATS_FAULT_STATUS_INFO; -typedef union ATC_ATS_FAULT_STATUS_ADDR regATC_ATS_FAULT_STATUS_ADDR; -typedef union ATC_ATS_DEFAULT_PAGE_LOW regATC_ATS_DEFAULT_PAGE_LOW; -typedef union ATC_TRANS_FAULT_RSPCNTRL regATC_TRANS_FAULT_RSPCNTRL; -typedef union ATC_ATS_FAULT_STATUS_INFO2 regATC_ATS_FAULT_STATUS_INFO2; -typedef union ATHUB_MISC_CNTL regATHUB_MISC_CNTL; -typedef union ATC_VMID_PASID_MAPPING_UPDATE_STATUS regATC_VMID_PASID_MAPPING_UPDATE_STATUS; -typedef union ATC_VMID0_PASID_MAPPING regATC_VMID0_PASID_MAPPING; -typedef union ATC_VMID1_PASID_MAPPING regATC_VMID1_PASID_MAPPING; -typedef union ATC_VMID2_PASID_MAPPING regATC_VMID2_PASID_MAPPING; -typedef union ATC_VMID3_PASID_MAPPING regATC_VMID3_PASID_MAPPING; -typedef union ATC_VMID4_PASID_MAPPING regATC_VMID4_PASID_MAPPING; -typedef union ATC_VMID5_PASID_MAPPING regATC_VMID5_PASID_MAPPING; -typedef union ATC_VMID6_PASID_MAPPING regATC_VMID6_PASID_MAPPING; -typedef union ATC_VMID7_PASID_MAPPING regATC_VMID7_PASID_MAPPING; -typedef union ATC_VMID8_PASID_MAPPING regATC_VMID8_PASID_MAPPING; -typedef union ATC_VMID9_PASID_MAPPING regATC_VMID9_PASID_MAPPING; -typedef union ATC_VMID10_PASID_MAPPING regATC_VMID10_PASID_MAPPING; -typedef union ATC_VMID11_PASID_MAPPING regATC_VMID11_PASID_MAPPING; -typedef union ATC_VMID12_PASID_MAPPING regATC_VMID12_PASID_MAPPING; -typedef union ATC_VMID13_PASID_MAPPING regATC_VMID13_PASID_MAPPING; -typedef union ATC_VMID14_PASID_MAPPING regATC_VMID14_PASID_MAPPING; -typedef union ATC_VMID15_PASID_MAPPING regATC_VMID15_PASID_MAPPING; -typedef union ATC_ATS_VMID_STATUS regATC_ATS_VMID_STATUS; -typedef union ATC_ATS_GFX_ATCL2_STATUS regATC_ATS_GFX_ATCL2_STATUS; -typedef union ATC_PERFCOUNTER0_CFG regATC_PERFCOUNTER0_CFG; -typedef union ATC_PERFCOUNTER1_CFG regATC_PERFCOUNTER1_CFG; -typedef union ATC_PERFCOUNTER2_CFG regATC_PERFCOUNTER2_CFG; -typedef union ATC_PERFCOUNTER3_CFG regATC_PERFCOUNTER3_CFG; -typedef union ATC_PERFCOUNTER_RSLT_CNTL regATC_PERFCOUNTER_RSLT_CNTL; -typedef union ATC_PERFCOUNTER_LO regATC_PERFCOUNTER_LO; -typedef union ATC_PERFCOUNTER_HI regATC_PERFCOUNTER_HI; -typedef union ATHUB_PCIE_ATS_CNTL regATHUB_PCIE_ATS_CNTL; -typedef union ATHUB_PCIE_PASID_CNTL regATHUB_PCIE_PASID_CNTL; -typedef union ATHUB_PCIE_PAGE_REQ_CNTL regATHUB_PCIE_PAGE_REQ_CNTL; -typedef union ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC regATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC; -typedef union ATHUB_COMMAND regATHUB_COMMAND; -typedef union ATHUB_PCIE_ATS_CNTL_VF_0 regATHUB_PCIE_ATS_CNTL_VF_0; -typedef union ATHUB_PCIE_ATS_CNTL_VF_1 regATHUB_PCIE_ATS_CNTL_VF_1; -typedef union ATHUB_PCIE_ATS_CNTL_VF_2 regATHUB_PCIE_ATS_CNTL_VF_2; -typedef union ATHUB_PCIE_ATS_CNTL_VF_3 regATHUB_PCIE_ATS_CNTL_VF_3; -typedef union ATHUB_PCIE_ATS_CNTL_VF_4 regATHUB_PCIE_ATS_CNTL_VF_4; -typedef union ATHUB_PCIE_ATS_CNTL_VF_5 regATHUB_PCIE_ATS_CNTL_VF_5; -typedef union ATHUB_PCIE_ATS_CNTL_VF_6 regATHUB_PCIE_ATS_CNTL_VF_6; -typedef union ATHUB_PCIE_ATS_CNTL_VF_7 regATHUB_PCIE_ATS_CNTL_VF_7; -typedef union ATHUB_PCIE_ATS_CNTL_VF_8 regATHUB_PCIE_ATS_CNTL_VF_8; -typedef union ATHUB_PCIE_ATS_CNTL_VF_9 regATHUB_PCIE_ATS_CNTL_VF_9; -typedef union ATHUB_PCIE_ATS_CNTL_VF_10 regATHUB_PCIE_ATS_CNTL_VF_10; -typedef union ATHUB_PCIE_ATS_CNTL_VF_11 regATHUB_PCIE_ATS_CNTL_VF_11; -typedef union ATHUB_PCIE_ATS_CNTL_VF_12 regATHUB_PCIE_ATS_CNTL_VF_12; -typedef union ATHUB_PCIE_ATS_CNTL_VF_13 regATHUB_PCIE_ATS_CNTL_VF_13; -typedef union ATHUB_PCIE_ATS_CNTL_VF_14 regATHUB_PCIE_ATS_CNTL_VF_14; -typedef union ATHUB_PCIE_ATS_CNTL_VF_15 regATHUB_PCIE_ATS_CNTL_VF_15; -typedef union ATHUB_MEM_POWER_LS regATHUB_MEM_POWER_LS; -typedef union ATS_IH_CREDIT regATS_IH_CREDIT; -typedef union ATHUB_IH_CREDIT regATHUB_IH_CREDIT; -typedef union ATC_VMID16_PASID_MAPPING regATC_VMID16_PASID_MAPPING; -typedef union ATC_VMID17_PASID_MAPPING regATC_VMID17_PASID_MAPPING; -typedef union ATC_VMID18_PASID_MAPPING regATC_VMID18_PASID_MAPPING; -typedef union ATC_VMID19_PASID_MAPPING regATC_VMID19_PASID_MAPPING; -typedef union ATC_VMID20_PASID_MAPPING regATC_VMID20_PASID_MAPPING; -typedef union ATC_VMID21_PASID_MAPPING regATC_VMID21_PASID_MAPPING; -typedef union ATC_VMID22_PASID_MAPPING regATC_VMID22_PASID_MAPPING; -typedef union ATC_VMID23_PASID_MAPPING regATC_VMID23_PASID_MAPPING; -typedef union ATC_VMID24_PASID_MAPPING regATC_VMID24_PASID_MAPPING; -typedef union ATC_VMID25_PASID_MAPPING regATC_VMID25_PASID_MAPPING; -typedef union ATC_VMID26_PASID_MAPPING regATC_VMID26_PASID_MAPPING; -typedef union ATC_VMID27_PASID_MAPPING regATC_VMID27_PASID_MAPPING; -typedef union ATC_VMID28_PASID_MAPPING regATC_VMID28_PASID_MAPPING; -typedef union ATC_VMID29_PASID_MAPPING regATC_VMID29_PASID_MAPPING; -typedef union ATC_VMID30_PASID_MAPPING regATC_VMID30_PASID_MAPPING; -typedef union ATC_VMID31_PASID_MAPPING regATC_VMID31_PASID_MAPPING; -typedef union ATC_ATS_MMHUB_ATCL2_STATUS regATC_ATS_MMHUB_ATCL2_STATUS; -typedef union ATHUB_SHARED_VIRT_RESET_REQ regATHUB_SHARED_VIRT_RESET_REQ; -typedef union ATHUB_SHARED_ACTIVE_FCN_ID regATHUB_SHARED_ACTIVE_FCN_ID; -typedef union ATC_ATS_SDPPORT_CNTL regATC_ATS_SDPPORT_CNTL; -typedef union ATC_ATS_DEBUG2 regATC_ATS_DEBUG2; -typedef union ATC_ATS_VMID_SNAPSHOT_GFX_STAT regATC_ATS_VMID_SNAPSHOT_GFX_STAT; -typedef union ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT regATC_ATS_VMID_SNAPSHOT_MMHUB_STAT; -typedef union XPB_RTR_SRC_APRTR0 regXPB_RTR_SRC_APRTR0; -typedef union XPB_RTR_SRC_APRTR1 regXPB_RTR_SRC_APRTR1; -typedef union XPB_RTR_SRC_APRTR2 regXPB_RTR_SRC_APRTR2; -typedef union XPB_RTR_SRC_APRTR3 regXPB_RTR_SRC_APRTR3; -typedef union XPB_RTR_SRC_APRTR4 regXPB_RTR_SRC_APRTR4; -typedef union XPB_RTR_SRC_APRTR5 regXPB_RTR_SRC_APRTR5; -typedef union XPB_RTR_SRC_APRTR6 regXPB_RTR_SRC_APRTR6; -typedef union XPB_RTR_SRC_APRTR7 regXPB_RTR_SRC_APRTR7; -typedef union XPB_RTR_SRC_APRTR8 regXPB_RTR_SRC_APRTR8; -typedef union XPB_RTR_SRC_APRTR9 regXPB_RTR_SRC_APRTR9; -typedef union XPB_XDMA_RTR_SRC_APRTR0 regXPB_XDMA_RTR_SRC_APRTR0; -typedef union XPB_XDMA_RTR_SRC_APRTR1 regXPB_XDMA_RTR_SRC_APRTR1; -typedef union XPB_XDMA_RTR_SRC_APRTR2 regXPB_XDMA_RTR_SRC_APRTR2; -typedef union XPB_XDMA_RTR_SRC_APRTR3 regXPB_XDMA_RTR_SRC_APRTR3; -typedef union XPB_RTR_DEST_MAP0 regXPB_RTR_DEST_MAP0; -typedef union XPB_RTR_DEST_MAP1 regXPB_RTR_DEST_MAP1; -typedef union XPB_RTR_DEST_MAP2 regXPB_RTR_DEST_MAP2; -typedef union XPB_RTR_DEST_MAP3 regXPB_RTR_DEST_MAP3; -typedef union XPB_RTR_DEST_MAP4 regXPB_RTR_DEST_MAP4; -typedef union XPB_RTR_DEST_MAP5 regXPB_RTR_DEST_MAP5; -typedef union XPB_RTR_DEST_MAP6 regXPB_RTR_DEST_MAP6; -typedef union XPB_RTR_DEST_MAP7 regXPB_RTR_DEST_MAP7; -typedef union XPB_RTR_DEST_MAP8 regXPB_RTR_DEST_MAP8; -typedef union XPB_RTR_DEST_MAP9 regXPB_RTR_DEST_MAP9; -typedef union XPB_XDMA_RTR_DEST_MAP0 regXPB_XDMA_RTR_DEST_MAP0; -typedef union XPB_XDMA_RTR_DEST_MAP1 regXPB_XDMA_RTR_DEST_MAP1; -typedef union XPB_XDMA_RTR_DEST_MAP2 regXPB_XDMA_RTR_DEST_MAP2; -typedef union XPB_XDMA_RTR_DEST_MAP3 regXPB_XDMA_RTR_DEST_MAP3; -typedef union XPB_CLG_CFG0 regXPB_CLG_CFG0; -typedef union XPB_CLG_CFG1 regXPB_CLG_CFG1; -typedef union XPB_CLG_CFG2 regXPB_CLG_CFG2; -typedef union XPB_CLG_CFG3 regXPB_CLG_CFG3; -typedef union XPB_CLG_CFG4 regXPB_CLG_CFG4; -typedef union XPB_CLG_CFG5 regXPB_CLG_CFG5; -typedef union XPB_CLG_CFG6 regXPB_CLG_CFG6; -typedef union XPB_CLG_CFG7 regXPB_CLG_CFG7; -typedef union XPB_CLG_EXTRA regXPB_CLG_EXTRA; -typedef union XPB_CLG_EXTRA_MSK regXPB_CLG_EXTRA_MSK; -typedef union XPB_LB_ADDR regXPB_LB_ADDR; -typedef union XPB_WCB_STS regXPB_WCB_STS; -typedef union XPB_HST_CFG regXPB_HST_CFG; -typedef union XPB_P2P_BAR_CFG regXPB_P2P_BAR_CFG; -typedef union XPB_P2P_BAR0 regXPB_P2P_BAR0; -typedef union XPB_P2P_BAR1 regXPB_P2P_BAR1; -typedef union XPB_P2P_BAR2 regXPB_P2P_BAR2; -typedef union XPB_P2P_BAR3 regXPB_P2P_BAR3; -typedef union XPB_P2P_BAR4 regXPB_P2P_BAR4; -typedef union XPB_P2P_BAR5 regXPB_P2P_BAR5; -typedef union XPB_P2P_BAR6 regXPB_P2P_BAR6; -typedef union XPB_P2P_BAR7 regXPB_P2P_BAR7; -typedef union XPB_P2P_BAR_SETUP regXPB_P2P_BAR_SETUP; -typedef union XPB_P2P_BAR_DEBUG regXPB_P2P_BAR_DEBUG; -typedef union XPB_P2P_BAR_DELTA_ABOVE regXPB_P2P_BAR_DELTA_ABOVE; -typedef union XPB_P2P_BAR_DELTA_BELOW regXPB_P2P_BAR_DELTA_BELOW; -typedef union XPB_PEER_SYS_BAR0 regXPB_PEER_SYS_BAR0; -typedef union XPB_PEER_SYS_BAR1 regXPB_PEER_SYS_BAR1; -typedef union XPB_PEER_SYS_BAR2 regXPB_PEER_SYS_BAR2; -typedef union XPB_PEER_SYS_BAR3 regXPB_PEER_SYS_BAR3; -typedef union XPB_PEER_SYS_BAR4 regXPB_PEER_SYS_BAR4; -typedef union XPB_PEER_SYS_BAR5 regXPB_PEER_SYS_BAR5; -typedef union XPB_PEER_SYS_BAR6 regXPB_PEER_SYS_BAR6; -typedef union XPB_PEER_SYS_BAR7 regXPB_PEER_SYS_BAR7; -typedef union XPB_PEER_SYS_BAR8 regXPB_PEER_SYS_BAR8; -typedef union XPB_PEER_SYS_BAR9 regXPB_PEER_SYS_BAR9; -typedef union XPB_XDMA_PEER_SYS_BAR0 regXPB_XDMA_PEER_SYS_BAR0; -typedef union XPB_XDMA_PEER_SYS_BAR1 regXPB_XDMA_PEER_SYS_BAR1; -typedef union XPB_XDMA_PEER_SYS_BAR2 regXPB_XDMA_PEER_SYS_BAR2; -typedef union XPB_XDMA_PEER_SYS_BAR3 regXPB_XDMA_PEER_SYS_BAR3; -typedef union XPB_CLK_GAT regXPB_CLK_GAT; -typedef union XPB_INTF_CFG regXPB_INTF_CFG; -typedef union XPB_INTF_STS regXPB_INTF_STS; -typedef union XPB_PIPE_STS regXPB_PIPE_STS; -typedef union XPB_SUB_CTRL regXPB_SUB_CTRL; -typedef union XPB_MAP_INVERT_FLUSH_NUM_LSB regXPB_MAP_INVERT_FLUSH_NUM_LSB; -typedef union XPB_PERF_KNOBS regXPB_PERF_KNOBS; -typedef union XPB_STICKY regXPB_STICKY; -typedef union XPB_STICKY_W1C regXPB_STICKY_W1C; -typedef union XPB_MISC_CFG regXPB_MISC_CFG; -typedef union XPB_INTF_CFG2 regXPB_INTF_CFG2; -typedef union XPB_CLG_EXTRA_RD regXPB_CLG_EXTRA_RD; -typedef union XPB_CLG_EXTRA_MSK_RD regXPB_CLG_EXTRA_MSK_RD; -typedef union XPB_CLG_GFX_MATCH regXPB_CLG_GFX_MATCH; -typedef union XPB_CLG_GFX_MATCH_MSK regXPB_CLG_GFX_MATCH_MSK; -typedef union XPB_CLG_MM_MATCH regXPB_CLG_MM_MATCH; -typedef union XPB_CLG_MM_MATCH_MSK regXPB_CLG_MM_MATCH_MSK; -typedef union XPB_CLG_GFX_UNITID_MAPPING0 regXPB_CLG_GFX_UNITID_MAPPING0; -typedef union XPB_CLG_GFX_UNITID_MAPPING1 regXPB_CLG_GFX_UNITID_MAPPING1; -typedef union XPB_CLG_GFX_UNITID_MAPPING2 regXPB_CLG_GFX_UNITID_MAPPING2; -typedef union XPB_CLG_GFX_UNITID_MAPPING3 regXPB_CLG_GFX_UNITID_MAPPING3; -typedef union XPB_CLG_GFX_UNITID_MAPPING4 regXPB_CLG_GFX_UNITID_MAPPING4; -typedef union XPB_CLG_GFX_UNITID_MAPPING5 regXPB_CLG_GFX_UNITID_MAPPING5; -typedef union XPB_CLG_GFX_UNITID_MAPPING6 regXPB_CLG_GFX_UNITID_MAPPING6; -typedef union XPB_CLG_GFX_UNITID_MAPPING7 regXPB_CLG_GFX_UNITID_MAPPING7; -typedef union XPB_CLG_MM_UNITID_MAPPING0 regXPB_CLG_MM_UNITID_MAPPING0; -typedef union XPB_CLG_MM_UNITID_MAPPING1 regXPB_CLG_MM_UNITID_MAPPING1; -typedef union XPB_CLG_MM_UNITID_MAPPING2 regXPB_CLG_MM_UNITID_MAPPING2; -typedef union XPB_CLG_MM_UNITID_MAPPING3 regXPB_CLG_MM_UNITID_MAPPING3; -typedef union RPB_PASSPW_CONF regRPB_PASSPW_CONF; -typedef union RPB_BLOCKLEVEL_CONF regRPB_BLOCKLEVEL_CONF; -typedef union RPB_SECLEVEL_CONF regRPB_SECLEVEL_CONF; -typedef union RPB_TAG_CONF regRPB_TAG_CONF; -typedef union RPB_DBG1 regRPB_DBG1; -typedef union RPB_EFF_CNTL regRPB_EFF_CNTL; -typedef union RPB_ARB_CNTL regRPB_ARB_CNTL; -typedef union RPB_ARB_CNTL2 regRPB_ARB_CNTL2; -typedef union RPB_BIF_CNTL regRPB_BIF_CNTL; -typedef union RPB_WR_SWITCH_CNTL regRPB_WR_SWITCH_CNTL; -typedef union RPB_WR_COMBINE_CNTL regRPB_WR_COMBINE_CNTL; -typedef union RPB_RD_SWITCH_CNTL regRPB_RD_SWITCH_CNTL; -typedef union RPB_CID_QUEUE_WR regRPB_CID_QUEUE_WR; -typedef union RPB_CID_QUEUE_RD regRPB_CID_QUEUE_RD; -typedef union RPB_PERF_COUNTER_CNTL regRPB_PERF_COUNTER_CNTL; -typedef union RPB_PERF_COUNTER_STATUS regRPB_PERF_COUNTER_STATUS; -typedef union RPB_CID_QUEUE_EX regRPB_CID_QUEUE_EX; -typedef union RPB_CID_QUEUE_EX_DATA regRPB_CID_QUEUE_EX_DATA; -typedef union RPB_SWITCH_CNTL2 regRPB_SWITCH_CNTL2; -typedef union RPB_DEINTRLV_COMBINE_CNTL regRPB_DEINTRLV_COMBINE_CNTL; -typedef union RPB_VC_SWITCH_RDWR regRPB_VC_SWITCH_RDWR; -typedef union RPB_PERFCOUNTER_LO regRPB_PERFCOUNTER_LO; -typedef union RPB_PERFCOUNTER_HI regRPB_PERFCOUNTER_HI; -typedef union RPB_PERFCOUNTER0_CFG regRPB_PERFCOUNTER0_CFG; -typedef union RPB_PERFCOUNTER1_CFG regRPB_PERFCOUNTER1_CFG; -typedef union RPB_PERFCOUNTER2_CFG regRPB_PERFCOUNTER2_CFG; -typedef union RPB_PERFCOUNTER3_CFG regRPB_PERFCOUNTER3_CFG; -typedef union RPB_PERFCOUNTER_RSLT_CNTL regRPB_PERFCOUNTER_RSLT_CNTL; -typedef union RPB_MISC_CG regRPB_MISC_CG; -typedef union RPB_RD_QUEUE_CNTL regRPB_RD_QUEUE_CNTL; -typedef union RPB_RD_QUEUE_CNTL2 regRPB_RD_QUEUE_CNTL2; -typedef union RPB_WR_QUEUE_CNTL regRPB_WR_QUEUE_CNTL; -typedef union RPB_WR_QUEUE_CNTL2 regRPB_WR_QUEUE_CNTL2; -typedef union RPB_EA_QUEUE_WR regRPB_EA_QUEUE_WR; -typedef union RPB_ATS_CNTL regRPB_ATS_CNTL; -typedef union RPB_ATS_CNTL2 regRPB_ATS_CNTL2; -typedef union RPB_SDPPORT_CNTL regRPB_SDPPORT_CNTL; -typedef union RSMU_HCID_GENERIC regRSMU_HCID_GENERIC; -typedef union RSMU_SIID_GENERIC regRSMU_SIID_GENERIC; -typedef union RSMU_DBG_MUX_CONTROL_GENERIC regRSMU_DBG_MUX_CONTROL_GENERIC; -typedef union RSMU_SW_MMIO_PUB_IND_ADDR_0_GENERIC regRSMU_SW_MMIO_PUB_IND_ADDR_0_GENERIC; -typedef union RSMU_SW_MMIO_PUB_IND_DATA_0_GENERIC regRSMU_SW_MMIO_PUB_IND_DATA_0_GENERIC; -typedef union RSMU_SW_MMIO_PUB_IND_ADDR_1_GENERIC regRSMU_SW_MMIO_PUB_IND_ADDR_1_GENERIC; -typedef union RSMU_SW_MMIO_PUB_IND_DATA_1_GENERIC regRSMU_SW_MMIO_PUB_IND_DATA_1_GENERIC; -typedef union RSMU_SOFT_RESETB_GENERIC regRSMU_SOFT_RESETB_GENERIC; -typedef union RSMU_PGFSM_CONTROL_GENERIC regRSMU_PGFSM_CONTROL_GENERIC; -typedef union RSMU_PGFSM_WR_DATA_GENERIC regRSMU_PGFSM_WR_DATA_GENERIC; -typedef union RSMU_PGFSM_RD_DATA_GENERIC regRSMU_PGFSM_RD_DATA_GENERIC; -typedef union RSMU_IH_CREDIT_GENERIC regRSMU_IH_CREDIT_GENERIC; -typedef union RSMU_IH_RESET_CNTL_GENERIC regRSMU_IH_RESET_CNTL_GENERIC; -typedef union RSMU_SEM_RESP_GENERIC regRSMU_SEM_RESP_GENERIC; -typedef union RSMU_SEM_RESET_CNTL_GENERIC regRSMU_SEM_RESET_CNTL_GENERIC; -typedef union RSMU_VIRTUAL_WIRE_SRC_ID_GENERIC regRSMU_VIRTUAL_WIRE_SRC_ID_GENERIC; -typedef union RSMU_VIRTUAL_WIRE_INDEX_GENERIC regRSMU_VIRTUAL_WIRE_INDEX_GENERIC; -typedef union RSMU_SW_STRAPRX_ADDR_GENERIC regRSMU_SW_STRAPRX_ADDR_GENERIC; -typedef union RSMU_SW_STRAPRX_DATA_GENERIC regRSMU_SW_STRAPRX_DATA_GENERIC; -typedef union RSMU_SW_STRAP_CONTROL_GENERIC regRSMU_SW_STRAP_CONTROL_GENERIC; -typedef union RSMU_TIMEOUT_ERROR_LOG_REG_GENERIC regRSMU_TIMEOUT_ERROR_LOG_REG_GENERIC; -typedef union RSMU_IP_MASTER_STATUS_GENERIC regRSMU_IP_MASTER_STATUS_GENERIC; -typedef union RSMU_GPUREG_SCRATCH_REG_0_GENERIC regRSMU_GPUREG_SCRATCH_REG_0_GENERIC; -typedef union RSMU_GPUREG_SCRATCH_REG_1_GENERIC regRSMU_GPUREG_SCRATCH_REG_1_GENERIC; -typedef union RSMU_COLD_RESETB_GENERIC regRSMU_COLD_RESETB_GENERIC; -typedef union RSMU_HARD_RESETB_GENERIC regRSMU_HARD_RESETB_GENERIC; -typedef union RSMU_PUB_FUSE_ADDR_GENERIC regRSMU_PUB_FUSE_ADDR_GENERIC; -typedef union RSMU_SEC_FUSE_ADDR_GENERIC regRSMU_SEC_FUSE_ADDR_GENERIC; -typedef union RSMU_ROM_ADDR_GENERIC regRSMU_ROM_ADDR_GENERIC; -typedef union RSMU_MEM_POWER_CTRL_GENERIC regRSMU_MEM_POWER_CTRL_GENERIC; -typedef union RSMU_MP0_STRAPRX_ADDR_GENERIC regRSMU_MP0_STRAPRX_ADDR_GENERIC; -typedef union RSMU_MP0_STRAPRX_DATA_GENERIC regRSMU_MP0_STRAPRX_DATA_GENERIC; -typedef union RSMU_SMS_FUSE_CFG_GENERIC regRSMU_SMS_FUSE_CFG_GENERIC; -typedef union RSMU_SMS_FUSE_ADDR_BASE_GENERIC regRSMU_SMS_FUSE_ADDR_BASE_GENERIC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GENERIC regRSMU_SMS_FUSE_ADDR_OFFSET_GENERIC; -typedef union RSMU_STRAP_CONTROL_GENERIC regRSMU_STRAP_CONTROL_GENERIC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC - regRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GENERIC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC - regRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GENERIC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC - regRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GENERIC; -typedef union RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC - regRSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GENERIC; -typedef union RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC - regRSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GENERIC; -typedef union RSMU_CAC_LKG_WEIGHT_0_GENERIC regRSMU_CAC_LKG_WEIGHT_0_GENERIC; -typedef union RSMU_CAC_LKG_WEIGHT_1_GENERIC regRSMU_CAC_LKG_WEIGHT_1_GENERIC; -typedef union RSMU_CAC_LKG_WEIGHT_2_GENERIC regRSMU_CAC_LKG_WEIGHT_2_GENERIC; -typedef union RSMU_CAC_LKG_WEIGHT_3_GENERIC regRSMU_CAC_LKG_WEIGHT_3_GENERIC; -typedef union RSMU_CAC_LKG_ACC_0_GENERIC regRSMU_CAC_LKG_ACC_0_GENERIC; -typedef union RSMU_CAC_LKG_ACC_1_GENERIC regRSMU_CAC_LKG_ACC_1_GENERIC; -typedef union RSMU_CAC_LKG_ACC_2_GENERIC regRSMU_CAC_LKG_ACC_2_GENERIC; -typedef union RSMU_CAC_LKG_ACC_3_GENERIC regRSMU_CAC_LKG_ACC_3_GENERIC; -typedef union RSMU_CAC_LKG_ACC_4_GENERIC regRSMU_CAC_LKG_ACC_4_GENERIC; -typedef union RSMU_CAC_LKG_ACC_5_GENERIC regRSMU_CAC_LKG_ACC_5_GENERIC; -typedef union RSMU_CAC_LKG_ACC_6_GENERIC regRSMU_CAC_LKG_ACC_6_GENERIC; -typedef union RSMU_CAC_LKG_ACC_7_GENERIC regRSMU_CAC_LKG_ACC_7_GENERIC; -typedef union RSMU_CAC_CONTROL_GENERIC regRSMU_CAC_CONTROL_GENERIC; -typedef union RSMU_CAC_WEIGHT_0_GENERIC regRSMU_CAC_WEIGHT_0_GENERIC; -typedef union RSMU_CAC_WEIGHT_1_GENERIC regRSMU_CAC_WEIGHT_1_GENERIC; -typedef union RSMU_CAC_WEIGHT_2_GENERIC regRSMU_CAC_WEIGHT_2_GENERIC; -typedef union RSMU_CAC_WEIGHT_3_GENERIC regRSMU_CAC_WEIGHT_3_GENERIC; -typedef union RSMU_CAC_WEIGHT_4_GENERIC regRSMU_CAC_WEIGHT_4_GENERIC; -typedef union RSMU_CAC_WEIGHT_5_GENERIC regRSMU_CAC_WEIGHT_5_GENERIC; -typedef union RSMU_CAC_WEIGHT_6_GENERIC regRSMU_CAC_WEIGHT_6_GENERIC; -typedef union RSMU_CAC_WEIGHT_7_GENERIC regRSMU_CAC_WEIGHT_7_GENERIC; -typedef union RSMU_CAC_ACC_0_GENERIC regRSMU_CAC_ACC_0_GENERIC; -typedef union RSMU_CAC_ACC_1_GENERIC regRSMU_CAC_ACC_1_GENERIC; -typedef union RSMU_CAC_ACC_2_GENERIC regRSMU_CAC_ACC_2_GENERIC; -typedef union RSMU_CAC_ACC_3_GENERIC regRSMU_CAC_ACC_3_GENERIC; -typedef union RSMU_CAC_ACC_4_GENERIC regRSMU_CAC_ACC_4_GENERIC; -typedef union RSMU_CAC_ACC_5_GENERIC regRSMU_CAC_ACC_5_GENERIC; -typedef union RSMU_CAC_ACC_6_GENERIC regRSMU_CAC_ACC_6_GENERIC; -typedef union RSMU_CAC_ACC_7_GENERIC regRSMU_CAC_ACC_7_GENERIC; -typedef union RSMU_CAC_ACC_8_GENERIC regRSMU_CAC_ACC_8_GENERIC; -typedef union RSMU_CAC_ACC_9_GENERIC regRSMU_CAC_ACC_9_GENERIC; -typedef union RSMU_CAC_ACC_10_GENERIC regRSMU_CAC_ACC_10_GENERIC; -typedef union RSMU_CAC_ACC_11_GENERIC regRSMU_CAC_ACC_11_GENERIC; -typedef union RSMU_CAC_ACC_12_GENERIC regRSMU_CAC_ACC_12_GENERIC; -typedef union RSMU_CAC_ACC_13_GENERIC regRSMU_CAC_ACC_13_GENERIC; -typedef union RSMU_CAC_ACC_14_GENERIC regRSMU_CAC_ACC_14_GENERIC; -typedef union RSMU_CAC_ACC_15_GENERIC regRSMU_CAC_ACC_15_GENERIC; -typedef union RSMU_CAC_AGGR_LO_GENERIC regRSMU_CAC_AGGR_LO_GENERIC; -typedef union RSMU_CAC_AGGR_HI_GENERIC regRSMU_CAC_AGGR_HI_GENERIC; -typedef union RSMU_DPM_CONTROL_GENERIC regRSMU_DPM_CONTROL_GENERIC; -typedef union RSMU_DPM_ACC_GENERIC regRSMU_DPM_ACC_GENERIC; -typedef union RSMU_DPM_IPCLK_REF_COUNTER_GENERIC regRSMU_DPM_IPCLK_REF_COUNTER_GENERIC; -typedef union RSMU_COUNTER_0_GENERIC regRSMU_COUNTER_0_GENERIC; -typedef union RSMU_COUNTER_1_GENERIC regRSMU_COUNTER_1_GENERIC; -typedef union RSMU_PWRMGT_INTR_ENABLE_P0_GENERIC regRSMU_PWRMGT_INTR_ENABLE_P0_GENERIC; -typedef union RSMU_PWRMGT_INTR_ENABLE_P1_GENERIC regRSMU_PWRMGT_INTR_ENABLE_P1_GENERIC; -typedef union RSMU_PWRMGT_INTR_ENABLE_P2_GENERIC regRSMU_PWRMGT_INTR_ENABLE_P2_GENERIC; -typedef union RSMU_PWRMGT_INTR_TARGET_ADDR_P0_GENERIC regRSMU_PWRMGT_INTR_TARGET_ADDR_P0_GENERIC; -typedef union RSMU_PWRMGT_INTR_TARGET_ADDR_P1_GENERIC regRSMU_PWRMGT_INTR_TARGET_ADDR_P1_GENERIC; -typedef union RSMU_PWRMGT_INTR_TARGET_ADDR_P2_GENERIC regRSMU_PWRMGT_INTR_TARGET_ADDR_P2_GENERIC; -typedef union RSMU_PWRMGT_INTR_CONFIG_P0_GENERIC regRSMU_PWRMGT_INTR_CONFIG_P0_GENERIC; -typedef union RSMU_PWRMGT_INTR_CONFIG_P1_GENERIC regRSMU_PWRMGT_INTR_CONFIG_P1_GENERIC; -typedef union RSMU_PWRMGT_INTR_CONFIG_P2_GENERIC regRSMU_PWRMGT_INTR_CONFIG_P2_GENERIC; -typedef union RSMU_PWRMGT_INTR_STATUS_GENERIC regRSMU_PWRMGT_INTR_STATUS_GENERIC; -typedef union RSMU_PWRMGT_INTR_PENDING_P0_GENERIC regRSMU_PWRMGT_INTR_PENDING_P0_GENERIC; -typedef union RSMU_PWRMGT_INTR_PENDING_P1_GENERIC regRSMU_PWRMGT_INTR_PENDING_P1_GENERIC; -typedef union RSMU_PWRMGT_INTR_PENDING_P2_GENERIC regRSMU_PWRMGT_INTR_PENDING_P2_GENERIC; -typedef union RSMU_PWRMGT_INTR_TYPE_GENERIC regRSMU_PWRMGT_INTR_TYPE_GENERIC; -typedef union RSMU_PWRMGT_INTR_INTERCEPT_GENERIC regRSMU_PWRMGT_INTR_INTERCEPT_GENERIC; -typedef union RSMU_PWRMGT_INTR_CLEAR_GENERIC regRSMU_PWRMGT_INTR_CLEAR_GENERIC; -typedef union RSMU_HARD_RESETB_DELAY_GENERIC regRSMU_HARD_RESETB_DELAY_GENERIC; -typedef union RSMU_MMIOPUB_SCRATCH_REG_0_GENERIC regRSMU_MMIOPUB_SCRATCH_REG_0_GENERIC; -typedef union RSMU_VF_ENABLE_GENERIC regRSMU_VF_ENABLE_GENERIC; -typedef union RSMU_MGCG_CONTROL_GENERIC regRSMU_MGCG_CONTROL_GENERIC; -typedef union RSMU_CUSTOM_HARD_RESETB_GENERIC regRSMU_CUSTOM_HARD_RESETB_GENERIC; -typedef union RSMU_SEC_AXI_MASTER_ENABLE_GENERIC regRSMU_SEC_AXI_MASTER_ENABLE_GENERIC; -typedef union RSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC regRSMU_SEC_SLAVE_ERROR_COUNTER_GENERIC; -typedef union RSMU_AXI_MASTER_QOS_CNTL_GENERIC regRSMU_AXI_MASTER_QOS_CNTL_GENERIC; -typedef union RSMU_MASTER_ERROR_COUNTER_GENERIC regRSMU_MASTER_ERROR_COUNTER_GENERIC; -typedef union RSMU_SLAVE_TIMEOUT_VALUE_GENERIC regRSMU_SLAVE_TIMEOUT_VALUE_GENERIC; -typedef union RSMU_RESET_TIMEOUT_CONTROL_GENERIC regRSMU_RESET_TIMEOUT_CONTROL_GENERIC; -typedef union RSMU_SLAVE_ERROR_COUNTER_GENERIC regRSMU_SLAVE_ERROR_COUNTER_GENERIC; -typedef union RSMU_AEB_LOCK_0_GENERIC regRSMU_AEB_LOCK_0_GENERIC; -typedef union RSMU_AEB_LOCK_1_GENERIC regRSMU_AEB_LOCK_1_GENERIC; -typedef union RSMU_AEB_OVERRIDE_0_GENERIC regRSMU_AEB_OVERRIDE_0_GENERIC; -typedef union RSMU_AEB_OVERRIDE_1_GENERIC regRSMU_AEB_OVERRIDE_1_GENERIC; -typedef union RSMU_SEC_INTR_ENABLE_GENERIC regRSMU_SEC_INTR_ENABLE_GENERIC; -typedef union RSMU_SEC_INTR_TARGET_ADDR_GENERIC regRSMU_SEC_INTR_TARGET_ADDR_GENERIC; -typedef union RSMU_SEC_INTR_CONFIG_GENERIC regRSMU_SEC_INTR_CONFIG_GENERIC; -typedef union RSMU_SEC_INTR_STATUS_GENERIC regRSMU_SEC_INTR_STATUS_GENERIC; -typedef union RSMU_SEC_INTR_PENDING_GENERIC regRSMU_SEC_INTR_PENDING_GENERIC; -typedef union RSMU_SEC_INTR_TYPE_GENERIC regRSMU_SEC_INTR_TYPE_GENERIC; -typedef union RSMU_SEC_INTR_INTERCEPT_GENERIC regRSMU_SEC_INTR_INTERCEPT_GENERIC; -typedef union RSMU_SEC_INTR_CLEAR_GENERIC regRSMU_SEC_INTR_CLEAR_GENERIC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_0_GENERIC regRSMU_SEC_MASTER_TRUST_LEVEL_0_GENERIC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GENERIC regRSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC regRSMU_SEC_ACCESS_CONTROL_RSMU_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC - regRSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC - regRSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC - regRSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_0_GENERIC regRSMU_SEC_START_ADDR_GROUP_0_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_0_GENERIC regRSMU_SEC_END_ADDR_GROUP_0_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_0_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_0_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_0_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_0_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_0_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_0_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_0_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_0_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_0_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_1_GENERIC regRSMU_SEC_START_ADDR_GROUP_1_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_1_GENERIC regRSMU_SEC_END_ADDR_GROUP_1_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_1_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_1_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_1_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_1_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_1_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_1_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_1_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_1_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_1_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_2_GENERIC regRSMU_SEC_START_ADDR_GROUP_2_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_2_GENERIC regRSMU_SEC_END_ADDR_GROUP_2_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_2_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_2_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_2_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_2_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_2_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_2_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_2_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_2_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_2_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_3_GENERIC regRSMU_SEC_START_ADDR_GROUP_3_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_3_GENERIC regRSMU_SEC_END_ADDR_GROUP_3_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_3_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_3_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_3_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_3_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_3_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_3_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_3_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_3_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_3_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_4_GENERIC regRSMU_SEC_START_ADDR_GROUP_4_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_4_GENERIC regRSMU_SEC_END_ADDR_GROUP_4_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_4_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_4_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_4_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_4_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_4_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_4_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_4_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_4_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_4_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_5_GENERIC regRSMU_SEC_START_ADDR_GROUP_5_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_5_GENERIC regRSMU_SEC_END_ADDR_GROUP_5_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_5_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_5_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_5_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_5_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_5_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_5_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_5_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_5_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_5_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_6_GENERIC regRSMU_SEC_START_ADDR_GROUP_6_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_6_GENERIC regRSMU_SEC_END_ADDR_GROUP_6_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_6_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_6_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_6_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_6_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_6_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_6_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_6_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_6_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_6_GENERIC; -typedef union RSMU_SEC_START_ADDR_GROUP_7_GENERIC regRSMU_SEC_START_ADDR_GROUP_7_GENERIC; -typedef union RSMU_SEC_END_ADDR_GROUP_7_GENERIC regRSMU_SEC_END_ADDR_GROUP_7_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_7_GENERIC - regRSMU_SEC_INITID_MASK_SET0_GROUP_7_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GENERIC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_7_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC regRSMU_SEC_MISC_MASK_SET0_GROUP_7_GENERIC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_7_GENERIC - regRSMU_SEC_INITID_MASK_SET1_GROUP_7_GENERIC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GENERIC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_7_GENERIC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC regRSMU_SEC_MISC_MASK_SET1_GROUP_7_GENERIC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC regRSMU_SEC_ACCESS_CONTROL_GROUP_7_GENERIC; -typedef union RSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC regRSMU_SEC_SLAVE_ERROR_LOG_REG_GENERIC; -typedef union RSMU_MMIOSEC_SCRATCH_REG_0_GENERIC regRSMU_MMIOSEC_SCRATCH_REG_0_GENERIC; -typedef union RSMU_HCID_GC regRSMU_HCID_GC; -typedef union RSMU_SIID_GC regRSMU_SIID_GC; -typedef union RSMU_DBG_MUX_CONTROL_GC regRSMU_DBG_MUX_CONTROL_GC; -typedef union RSMU_SW_MMIO_PUB_IND_ADDR_0_GC regRSMU_SW_MMIO_PUB_IND_ADDR_0_GC; -typedef union RSMU_SW_MMIO_PUB_IND_DATA_0_GC regRSMU_SW_MMIO_PUB_IND_DATA_0_GC; -typedef union RSMU_SW_MMIO_PUB_IND_ADDR_1_GC regRSMU_SW_MMIO_PUB_IND_ADDR_1_GC; -typedef union RSMU_SW_MMIO_PUB_IND_DATA_1_GC regRSMU_SW_MMIO_PUB_IND_DATA_1_GC; -typedef union RSMU_SOFT_RESETB_GC regRSMU_SOFT_RESETB_GC; -typedef union RSMU_IH_CREDIT_GC regRSMU_IH_CREDIT_GC; -typedef union RSMU_IH_RESET_CNTL_GC regRSMU_IH_RESET_CNTL_GC; -typedef union RSMU_SEM_RESP_GC regRSMU_SEM_RESP_GC; -typedef union RSMU_SEM_RESET_CNTL_GC regRSMU_SEM_RESET_CNTL_GC; -typedef union RSMU_SW_STRAPRX_ADDR_GC regRSMU_SW_STRAPRX_ADDR_GC; -typedef union RSMU_SW_STRAPRX_DATA_GC regRSMU_SW_STRAPRX_DATA_GC; -typedef union RSMU_SW_STRAP_CONTROL_GC regRSMU_SW_STRAP_CONTROL_GC; -typedef union RSMU_TIMEOUT_ERROR_LOG_REG_GC regRSMU_TIMEOUT_ERROR_LOG_REG_GC; -typedef union RSMU_IP_MASTER_STATUS_GC regRSMU_IP_MASTER_STATUS_GC; -typedef union RSMU_GPUREG_SCRATCH_REG_0_GC regRSMU_GPUREG_SCRATCH_REG_0_GC; -typedef union RSMU_GPUREG_SCRATCH_REG_1_GC regRSMU_GPUREG_SCRATCH_REG_1_GC; -typedef union RSMU_COLD_RESETB_GC regRSMU_COLD_RESETB_GC; -typedef union RSMU_HARD_RESETB_GC regRSMU_HARD_RESETB_GC; -typedef union RSMU_PUB_FUSE_ADDR_GC regRSMU_PUB_FUSE_ADDR_GC; -typedef union RSMU_SEC_FUSE_ADDR_GC regRSMU_SEC_FUSE_ADDR_GC; -typedef union RSMU_MEM_POWER_CTRL_GC regRSMU_MEM_POWER_CTRL_GC; -typedef union RSMU_MP0_STRAPRX_ADDR_GC regRSMU_MP0_STRAPRX_ADDR_GC; -typedef union RSMU_MP0_STRAPRX_DATA_GC regRSMU_MP0_STRAPRX_DATA_GC; -typedef union RSMU_SMS_FUSE_CFG_GC regRSMU_SMS_FUSE_CFG_GC; -typedef union RSMU_SMS_FUSE_ADDR_BASE_GC regRSMU_SMS_FUSE_ADDR_BASE_GC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GC regRSMU_SMS_FUSE_ADDR_OFFSET_GC; -typedef union RSMU_STRAP_CONTROL_GC regRSMU_STRAP_CONTROL_GC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC regRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET1_GC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC regRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET2_GC; -typedef union RSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC regRSMU_SMS_FUSE_ADDR_OFFSET_GRP_SET3_GC; -typedef union RSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC regRSMU_SMS_FUSE_CNTL_SET_NONE_DEFAULT_GC; -typedef union RSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC regRSMU_SMS_FUSE_STATUS_SET_NONE_DEFAULT_GC; -typedef union RSMU_DPM_CONTROL_GC regRSMU_DPM_CONTROL_GC; -typedef union RSMU_DPM_ACC_GC regRSMU_DPM_ACC_GC; -typedef union RSMU_DPM_IPCLK_REF_COUNTER_GC regRSMU_DPM_IPCLK_REF_COUNTER_GC; -typedef union RSMU_COUNTER_0_GC regRSMU_COUNTER_0_GC; -typedef union RSMU_COUNTER_1_GC regRSMU_COUNTER_1_GC; -typedef union RSMU_HARD_RESETB_DELAY_GC regRSMU_HARD_RESETB_DELAY_GC; -typedef union RSMU_MMIOPUB_SCRATCH_REG_0_GC regRSMU_MMIOPUB_SCRATCH_REG_0_GC; -typedef union RSMU_VF_ENABLE_GC regRSMU_VF_ENABLE_GC; -typedef union RSMU_MGCG_CONTROL_GC regRSMU_MGCG_CONTROL_GC; -typedef union RSMU_RESIDENCY_COUNTER_CNTL_GC regRSMU_RESIDENCY_COUNTER_CNTL_GC; -typedef union RSMU_RESIDENCY_COUNTER_GC regRSMU_RESIDENCY_COUNTER_GC; -typedef union RSMU_RESIDENCY_REF_COUNTER_GC regRSMU_RESIDENCY_REF_COUNTER_GC; -typedef union RSMU_CUSTOM_HARD_RESETB_GC regRSMU_CUSTOM_HARD_RESETB_GC; -typedef union RSMU_SEC_AXI_MASTER_ENABLE_GC regRSMU_SEC_AXI_MASTER_ENABLE_GC; -typedef union RSMU_SEC_SLAVE_ERROR_COUNTER_GC regRSMU_SEC_SLAVE_ERROR_COUNTER_GC; -typedef union RSMU_AXI_MASTER_QOS_CNTL_GC regRSMU_AXI_MASTER_QOS_CNTL_GC; -typedef union RSMU_MASTER_ERROR_COUNTER_GC regRSMU_MASTER_ERROR_COUNTER_GC; -typedef union RSMU_SLAVE_TIMEOUT_VALUE_GC regRSMU_SLAVE_TIMEOUT_VALUE_GC; -typedef union RSMU_RESET_TIMEOUT_CONTROL_GC regRSMU_RESET_TIMEOUT_CONTROL_GC; -typedef union RSMU_SLAVE_ERROR_COUNTER_GC regRSMU_SLAVE_ERROR_COUNTER_GC; -typedef union RSMU_AEB_LOCK_0_GC regRSMU_AEB_LOCK_0_GC; -typedef union RSMU_AEB_LOCK_1_GC regRSMU_AEB_LOCK_1_GC; -typedef union RSMU_AEB_OVERRIDE_0_GC regRSMU_AEB_OVERRIDE_0_GC; -typedef union RSMU_AEB_OVERRIDE_1_GC regRSMU_AEB_OVERRIDE_1_GC; -typedef union RSMU_SEC_INTR_ENABLE_GC regRSMU_SEC_INTR_ENABLE_GC; -typedef union RSMU_SEC_INTR_TARGET_ADDR_GC regRSMU_SEC_INTR_TARGET_ADDR_GC; -typedef union RSMU_SEC_INTR_CONFIG_GC regRSMU_SEC_INTR_CONFIG_GC; -typedef union RSMU_SEC_INTR_STATUS_GC regRSMU_SEC_INTR_STATUS_GC; -typedef union RSMU_SEC_INTR_PENDING_GC regRSMU_SEC_INTR_PENDING_GC; -typedef union RSMU_SEC_INTR_TYPE_GC regRSMU_SEC_INTR_TYPE_GC; -typedef union RSMU_SEC_INTR_INTERCEPT_GC regRSMU_SEC_INTR_INTERCEPT_GC; -typedef union RSMU_SEC_INTR_CLEAR_GC regRSMU_SEC_INTR_CLEAR_GC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_0_GC regRSMU_SEC_MASTER_TRUST_LEVEL_0_GC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_1_GC regRSMU_SEC_MASTER_TRUST_LEVEL_1_GC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_2_GC regRSMU_SEC_MASTER_TRUST_LEVEL_2_GC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_3_GC regRSMU_SEC_MASTER_TRUST_LEVEL_3_GC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_5_GC regRSMU_SEC_MASTER_TRUST_LEVEL_5_GC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_6_GC regRSMU_SEC_MASTER_TRUST_LEVEL_6_GC; -typedef union RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC regRSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_RSMU_GC regRSMU_SEC_ACCESS_CONTROL_RSMU_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GC - regRSMU_SEC_INITID_MASK_SET0_GROUP_DEFAULT_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GC - regRSMU_SEC_UNITID_MASK_SET0_GROUP_DEFAULT_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GC - regRSMU_SEC_INITID_MASK_SET1_GROUP_DEFAULT_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GC - regRSMU_SEC_UNITID_MASK_SET1_GROUP_DEFAULT_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_0_GC regRSMU_SEC_START_ADDR_GROUP_0_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_0_GC regRSMU_SEC_END_ADDR_GROUP_0_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_0_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_0_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_0_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_0_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_0_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_0_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_0_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_0_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_0_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_0_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_0_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_1_GC regRSMU_SEC_START_ADDR_GROUP_1_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_1_GC regRSMU_SEC_END_ADDR_GROUP_1_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_1_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_1_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_1_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_1_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_1_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_1_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_1_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_1_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_1_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_1_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_1_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_2_GC regRSMU_SEC_START_ADDR_GROUP_2_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_2_GC regRSMU_SEC_END_ADDR_GROUP_2_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_2_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_2_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_2_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_2_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_2_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_2_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_2_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_2_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_2_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_2_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_2_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_3_GC regRSMU_SEC_START_ADDR_GROUP_3_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_3_GC regRSMU_SEC_END_ADDR_GROUP_3_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_3_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_3_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_3_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_3_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_3_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_3_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_3_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_3_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_3_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_3_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_3_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_4_GC regRSMU_SEC_START_ADDR_GROUP_4_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_4_GC regRSMU_SEC_END_ADDR_GROUP_4_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_4_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_4_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_4_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_4_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_4_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_4_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_4_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_4_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_4_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_4_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_4_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_5_GC regRSMU_SEC_START_ADDR_GROUP_5_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_5_GC regRSMU_SEC_END_ADDR_GROUP_5_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_5_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_5_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_5_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_5_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_5_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_5_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_5_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_5_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_5_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_5_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_5_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_5_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_5_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_5_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_6_GC regRSMU_SEC_START_ADDR_GROUP_6_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_6_GC regRSMU_SEC_END_ADDR_GROUP_6_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_6_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_6_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_6_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_6_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_6_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_6_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_6_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_6_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_6_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_6_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_6_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_6_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_6_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_6_GC; -typedef union RSMU_SEC_START_ADDR_GROUP_7_GC regRSMU_SEC_START_ADDR_GROUP_7_GC; -typedef union RSMU_SEC_END_ADDR_GROUP_7_GC regRSMU_SEC_END_ADDR_GROUP_7_GC; -typedef union RSMU_SEC_INITID_MASK_SET0_GROUP_7_GC regRSMU_SEC_INITID_MASK_SET0_GROUP_7_GC; -typedef union RSMU_SEC_UNITID_MASK_SET0_GROUP_7_GC regRSMU_SEC_UNITID_MASK_SET0_GROUP_7_GC; -typedef union RSMU_SEC_MISC_MASK_SET0_GROUP_7_GC regRSMU_SEC_MISC_MASK_SET0_GROUP_7_GC; -typedef union RSMU_SEC_INITID_MASK_SET1_GROUP_7_GC regRSMU_SEC_INITID_MASK_SET1_GROUP_7_GC; -typedef union RSMU_SEC_UNITID_MASK_SET1_GROUP_7_GC regRSMU_SEC_UNITID_MASK_SET1_GROUP_7_GC; -typedef union RSMU_SEC_MISC_MASK_SET1_GROUP_7_GC regRSMU_SEC_MISC_MASK_SET1_GROUP_7_GC; -typedef union RSMU_SEC_ACCESS_CONTROL_GROUP_7_GC regRSMU_SEC_ACCESS_CONTROL_GROUP_7_GC; -typedef union RSMU_SEC_SLAVE_ERROR_LOG_REG_GC regRSMU_SEC_SLAVE_ERROR_LOG_REG_GC; -typedef union RSMU_MMIOSEC_SCRATCH_REG_0_GC regRSMU_MMIOSEC_SCRATCH_REG_0_GC; -typedef union nbif_gpu_HARD_RST_CTRL regnbif_gpu_HARD_RST_CTRL; -typedef union nbif_gpu_RSMU_SOFT_RST_CTRL regnbif_gpu_RSMU_SOFT_RST_CTRL; -typedef union nbif_gpu_SELF_SOFT_RST regnbif_gpu_SELF_SOFT_RST; -typedef union nbif_gpu_GFX_DRV_MODE1_RST_CTRL regnbif_gpu_GFX_DRV_MODE1_RST_CTRL; -typedef union nbif_gpu_BIF_RST_MISC_CTRL regnbif_gpu_BIF_RST_MISC_CTRL; -typedef union nbif_gpu_BIF_RST_MISC_CTRL2 regnbif_gpu_BIF_RST_MISC_CTRL2; -typedef union nbif_gpu_BIF_RST_MISC_CTRL3 regnbif_gpu_BIF_RST_MISC_CTRL3; -typedef union nbif_gpu_BIF_RST_GFXVF_FLR_IDLE regnbif_gpu_BIF_RST_GFXVF_FLR_IDLE; -typedef union nbif_gpu_DEV0_PF0_FLR_RST_CTRL regnbif_gpu_DEV0_PF0_FLR_RST_CTRL; -typedef union nbif_gpu_DEV0_PF1_FLR_RST_CTRL regnbif_gpu_DEV0_PF1_FLR_RST_CTRL; -typedef union nbif_gpu_DEV0_PF2_FLR_RST_CTRL regnbif_gpu_DEV0_PF2_FLR_RST_CTRL; -typedef union nbif_gpu_DEV0_PF3_FLR_RST_CTRL regnbif_gpu_DEV0_PF3_FLR_RST_CTRL; -typedef union nbif_gpu_DEV0_PF4_FLR_RST_CTRL regnbif_gpu_DEV0_PF4_FLR_RST_CTRL; -typedef union nbif_gpu_DEV0_PF5_FLR_RST_CTRL regnbif_gpu_DEV0_PF5_FLR_RST_CTRL; -typedef union nbif_gpu_DEV0_PF6_FLR_RST_CTRL regnbif_gpu_DEV0_PF6_FLR_RST_CTRL; -typedef union nbif_gpu_DEV0_PF7_FLR_RST_CTRL regnbif_gpu_DEV0_PF7_FLR_RST_CTRL; -typedef union nbif_gpu_BIF_INST_RESET_INTR_STS regnbif_gpu_BIF_INST_RESET_INTR_STS; -typedef union nbif_gpu_BIF_PF_FLR_INTR_STS regnbif_gpu_BIF_PF_FLR_INTR_STS; -typedef union nbif_gpu_BIF_D3HOTD0_INTR_STS regnbif_gpu_BIF_D3HOTD0_INTR_STS; -typedef union nbif_gpu_BIF_POWER_INTR_STS regnbif_gpu_BIF_POWER_INTR_STS; -typedef union nbif_gpu_BIF_PF_DSTATE_INTR_STS regnbif_gpu_BIF_PF_DSTATE_INTR_STS; -typedef union nbif_gpu_BIF_PF0_VF_FLR_INTR_STS regnbif_gpu_BIF_PF0_VF_FLR_INTR_STS; -typedef union nbif_gpu_BIF_INST_RESET_INTR_MASK regnbif_gpu_BIF_INST_RESET_INTR_MASK; -typedef union nbif_gpu_BIF_PF_FLR_INTR_MASK regnbif_gpu_BIF_PF_FLR_INTR_MASK; -typedef union nbif_gpu_BIF_D3HOTD0_INTR_MASK regnbif_gpu_BIF_D3HOTD0_INTR_MASK; -typedef union nbif_gpu_BIF_POWER_INTR_MASK regnbif_gpu_BIF_POWER_INTR_MASK; -typedef union nbif_gpu_BIF_PF_DSTATE_INTR_MASK regnbif_gpu_BIF_PF_DSTATE_INTR_MASK; -typedef union nbif_gpu_BIF_PF0_VF_FLR_INTR_MASK regnbif_gpu_BIF_PF0_VF_FLR_INTR_MASK; -typedef union nbif_gpu_BIF_PF_FLR_RST regnbif_gpu_BIF_PF_FLR_RST; -typedef union nbif_gpu_BIF_PF_FLR_PROTECT regnbif_gpu_BIF_PF_FLR_PROTECT; -typedef union nbif_gpu_BIF_PF0_VF_FLR_RST regnbif_gpu_BIF_PF0_VF_FLR_RST; -typedef union nbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF0_DSTATE_VALUE; -typedef union nbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF1_DSTATE_VALUE; -typedef union nbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF2_DSTATE_VALUE; -typedef union nbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF3_DSTATE_VALUE; -typedef union nbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF4_DSTATE_VALUE; -typedef union nbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF5_DSTATE_VALUE; -typedef union nbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF6_DSTATE_VALUE; -typedef union nbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE regnbif_gpu_BIF_DEV0_PF7_DSTATE_VALUE; -typedef union nbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF0_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF1_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF2_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF3_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF4_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF5_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF6_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL regnbif_gpu_DEV0_PF7_D3HOTD0_RST_CTRL; -typedef union nbif_gpu_BIF_GFX_VF_FLR_PROTECT regnbif_gpu_BIF_GFX_VF_FLR_PROTECT; -typedef union nbif_gpu_BIF_PORT0_DSTATE_VALUE regnbif_gpu_BIF_PORT0_DSTATE_VALUE; -typedef union nbif_gpu_MISC_SECURITY_SET regnbif_gpu_MISC_SECURITY_SET; -typedef union nbif_gpu_MISC_SCRATCH regnbif_gpu_MISC_SCRATCH; -typedef union nbif_gpu_INTR_LINE_POLARITY regnbif_gpu_INTR_LINE_POLARITY; -typedef union nbif_gpu_INTR_LINE_ENABLE regnbif_gpu_INTR_LINE_ENABLE; -typedef union nbif_gpu_OUTSTANDING_VC_ALLOC regnbif_gpu_OUTSTANDING_VC_ALLOC; -typedef union nbif_gpu_BIFC_MISC_CTRL0 regnbif_gpu_BIFC_MISC_CTRL0; -typedef union nbif_gpu_BIFC_MISC_CTRL1 regnbif_gpu_BIFC_MISC_CTRL1; -typedef union nbif_gpu_BIFC_BME_ERR_LOG regnbif_gpu_BIFC_BME_ERR_LOG; -typedef union nbif_gpu_BIFC_RCCBIH_BME_ERR_LOG regnbif_gpu_BIFC_RCCBIH_BME_ERR_LOG; -typedef union nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 - regnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1; -typedef union nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 - regnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3; -typedef union nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 - regnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5; -typedef union nbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 - regnbif_gpu_BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7; -typedef union nbif_gpu_NBIF_VWIRE_CTRL regnbif_gpu_NBIF_VWIRE_CTRL; -typedef union nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL regnbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL; -typedef union nbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0 regnbif_gpu_NBIF_SMN_VWR_VCHG_RST_CTRL0; -typedef union nbif_gpu_NBIF_SMN_VWR_VCHG_TRIG regnbif_gpu_NBIF_SMN_VWR_VCHG_TRIG; -typedef union nbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL regnbif_gpu_NBIF_SMN_VWR_WTRIG_CNTL; -typedef union nbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1 regnbif_gpu_NBIF_SMN_VWR_VCHG_DIS_CTRL_1; -typedef union nbif_gpu_NBIF_MGCG_CTRL regnbif_gpu_NBIF_MGCG_CTRL; -typedef union nbif_gpu_NBIF_DS_CTRL_LCLK regnbif_gpu_NBIF_DS_CTRL_LCLK; -typedef union nbif_gpu_SMN_MST_CNTL0 regnbif_gpu_SMN_MST_CNTL0; -typedef union nbif_gpu_SMN_MST_EP_CNTL1 regnbif_gpu_SMN_MST_EP_CNTL1; -typedef union nbif_gpu_SMN_MST_EP_CNTL2 regnbif_gpu_SMN_MST_EP_CNTL2; -typedef union nbif_gpu_SMN_MST_EP_CNTL3 regnbif_gpu_SMN_MST_EP_CNTL3; -typedef union nbif_gpu_SMN_MST_EP_CNTL4 regnbif_gpu_SMN_MST_EP_CNTL4; -typedef union nbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL regnbif_gpu_NBIF_SDP_VWR_VCHG_DIS_CTRL; -typedef union nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0 regnbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL0; -typedef union nbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1 regnbif_gpu_NBIF_SDP_VWR_VCHG_RST_CTRL1; -typedef union nbif_gpu_NBIF_SDP_VWR_VCHG_TRIG regnbif_gpu_NBIF_SDP_VWR_VCHG_TRIG; -typedef union nbif_gpu_BME_DUMMY_CNTL_0 regnbif_gpu_BME_DUMMY_CNTL_0; -typedef union nbif_gpu_BIFC_THT_CNTL regnbif_gpu_BIFC_THT_CNTL; -typedef union nbif_gpu_BIFC_HSTARB_CNTL regnbif_gpu_BIFC_HSTARB_CNTL; -typedef union nbif_gpu_BIFC_GSI_CNTL regnbif_gpu_BIFC_GSI_CNTL; -typedef union nbif_gpu_BIFC_PCIEFUNC_CNTL regnbif_gpu_BIFC_PCIEFUNC_CNTL; -typedef union nbif_gpu_BIFC_SDP_CNTL_0 regnbif_gpu_BIFC_SDP_CNTL_0; -typedef union nbif_gpu_BIFC_PERF_CNTL_0 regnbif_gpu_BIFC_PERF_CNTL_0; -typedef union nbif_gpu_BIFC_PERF_CNTL_1 regnbif_gpu_BIFC_PERF_CNTL_1; -typedef union nbif_gpu_BIFC_PERF_CNT_MMIO_RD regnbif_gpu_BIFC_PERF_CNT_MMIO_RD; -typedef union nbif_gpu_BIFC_PERF_CNT_MMIO_WR regnbif_gpu_BIFC_PERF_CNT_MMIO_WR; -typedef union nbif_gpu_BIFC_PERF_CNT_DMA_RD regnbif_gpu_BIFC_PERF_CNT_DMA_RD; -typedef union nbif_gpu_BIFC_PERF_CNT_DMA_WR regnbif_gpu_BIFC_PERF_CNT_DMA_WR; -typedef union nbif_gpu_NBIF_REGIF_ERRSET_CTRL regnbif_gpu_NBIF_REGIF_ERRSET_CTRL; -typedef union nbif_gpu_BIF_RAS_LEAF0_CTRL regnbif_gpu_BIF_RAS_LEAF0_CTRL; -typedef union nbif_gpu_BIF_RAS_LEAF1_CTRL regnbif_gpu_BIF_RAS_LEAF1_CTRL; -typedef union nbif_gpu_BIF_RAS_LEAF2_CTRL regnbif_gpu_BIF_RAS_LEAF2_CTRL; -typedef union nbif_gpu_BIF_RAS_MISC_CTRL regnbif_gpu_BIF_RAS_MISC_CTRL; -typedef union nbif_gpu_SUM_INDEX regnbif_gpu_SUM_INDEX; -typedef union nbif_gpu_SUM_DATA regnbif_gpu_SUM_DATA; -typedef union nbif_gpu_SBIOS_SCRATCH_0 regnbif_gpu_SBIOS_SCRATCH_0; -typedef union nbif_gpu_SBIOS_SCRATCH_1 regnbif_gpu_SBIOS_SCRATCH_1; -typedef union nbif_gpu_SBIOS_SCRATCH_2 regnbif_gpu_SBIOS_SCRATCH_2; -typedef union nbif_gpu_SBIOS_SCRATCH_3 regnbif_gpu_SBIOS_SCRATCH_3; -typedef union nbif_gpu_BIF_RLC_INTR_CNTL regnbif_gpu_BIF_RLC_INTR_CNTL; -typedef union nbif_gpu_BIF_VCE_INTR_CNTL regnbif_gpu_BIF_VCE_INTR_CNTL; -typedef union nbif_gpu_BIF_UVD_INTR_CNTL regnbif_gpu_BIF_UVD_INTR_CNTL; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR0 regnbif_gpu_GFX_MMIOREG_CAM_ADDR0; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR0; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR1 regnbif_gpu_GFX_MMIOREG_CAM_ADDR1; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR1; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR2 regnbif_gpu_GFX_MMIOREG_CAM_ADDR2; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR2; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR3 regnbif_gpu_GFX_MMIOREG_CAM_ADDR3; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR3; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR4 regnbif_gpu_GFX_MMIOREG_CAM_ADDR4; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR4; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR5 regnbif_gpu_GFX_MMIOREG_CAM_ADDR5; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR5; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR6 regnbif_gpu_GFX_MMIOREG_CAM_ADDR6; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR6; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ADDR7 regnbif_gpu_GFX_MMIOREG_CAM_ADDR7; -typedef union nbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7 regnbif_gpu_GFX_MMIOREG_CAM_REMAP_ADDR7; -typedef union nbif_gpu_GFX_MMIOREG_CAM_CNTL regnbif_gpu_GFX_MMIOREG_CAM_CNTL; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL regnbif_gpu_GFX_MMIOREG_CAM_ZERO_CPL; -typedef union nbif_gpu_GFX_MMIOREG_CAM_ONE_CPL regnbif_gpu_GFX_MMIOREG_CAM_ONE_CPL; -typedef union nbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL - regnbif_gpu_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL; -typedef union nbif_gpu_MM_INDEX regnbif_gpu_MM_INDEX; -typedef union nbif_gpu_MM_INDEX_HI regnbif_gpu_MM_INDEX_HI; -typedef union nbif_gpu_MM_DATA regnbif_gpu_MM_DATA; -typedef union nbif_gpu_SYSHUB_INDEX_OVLP regnbif_gpu_SYSHUB_INDEX_OVLP; -typedef union nbif_gpu_SYSHUB_DATA_OVLP regnbif_gpu_SYSHUB_DATA_OVLP; -typedef union nbif_gpu_PCIE_INDEX regnbif_gpu_PCIE_INDEX; -typedef union nbif_gpu_PCIE_DATA regnbif_gpu_PCIE_DATA; -typedef union nbif_gpu_PCIE_INDEX2 regnbif_gpu_PCIE_INDEX2; -typedef union nbif_gpu_PCIE_DATA2 regnbif_gpu_PCIE_DATA2; -typedef union nbif_gpu_CC_BIF_BX_STRAP0 regnbif_gpu_CC_BIF_BX_STRAP0; -typedef union nbif_gpu_CC_BIF_BX_PINSTRAP0 regnbif_gpu_CC_BIF_BX_PINSTRAP0; -typedef union nbif_gpu_CC_BIF_BX_FUSESTRAP0 regnbif_gpu_CC_BIF_BX_FUSESTRAP0; -typedef union nbif_gpu_BIF_MM_INDACCESS_CNTL regnbif_gpu_BIF_MM_INDACCESS_CNTL; -typedef union nbif_gpu_BUS_CNTL regnbif_gpu_BUS_CNTL; -typedef union nbif_gpu_BIF_SCRATCH0 regnbif_gpu_BIF_SCRATCH0; -typedef union nbif_gpu_BIF_SCRATCH1 regnbif_gpu_BIF_SCRATCH1; -typedef union nbif_gpu_BX_RESET_EN regnbif_gpu_BX_RESET_EN; -typedef union nbif_gpu_MM_CFGREGS_CNTL regnbif_gpu_MM_CFGREGS_CNTL; -typedef union nbif_gpu_HW_DEBUG regnbif_gpu_HW_DEBUG; -typedef union nbif_gpu_BX_RESET_CNTL regnbif_gpu_BX_RESET_CNTL; -typedef union nbif_gpu_INTERRUPT_CNTL regnbif_gpu_INTERRUPT_CNTL; -typedef union nbif_gpu_INTERRUPT_CNTL2 regnbif_gpu_INTERRUPT_CNTL2; -typedef union nbif_gpu_CLKREQB_PAD_CNTL regnbif_gpu_CLKREQB_PAD_CNTL; -typedef union nbif_gpu_CLKREQB_PERF_COUNTER regnbif_gpu_CLKREQB_PERF_COUNTER; -typedef union nbif_gpu_BIF_CLK_CTRL regnbif_gpu_BIF_CLK_CTRL; -typedef union nbif_gpu_BIF_FEATURES_CONTROL_MISC regnbif_gpu_BIF_FEATURES_CONTROL_MISC; -typedef union nbif_gpu_BIF_DOORBELL_CNTL regnbif_gpu_BIF_DOORBELL_CNTL; -typedef union nbif_gpu_BIF_DOORBELL_INT_CNTL regnbif_gpu_BIF_DOORBELL_INT_CNTL; -typedef union nbif_gpu_BIF_SLVARB_MODE regnbif_gpu_BIF_SLVARB_MODE; -typedef union nbif_gpu_BIF_FB_EN regnbif_gpu_BIF_FB_EN; -typedef union nbif_gpu_BIF_BUSY_DELAY_CNTR regnbif_gpu_BIF_BUSY_DELAY_CNTR; -typedef union nbif_gpu_BIF_PERFMON_CNTL regnbif_gpu_BIF_PERFMON_CNTL; -typedef union nbif_gpu_BIF_PERFCOUNTER0_RESULT regnbif_gpu_BIF_PERFCOUNTER0_RESULT; -typedef union nbif_gpu_BIF_PERFCOUNTER1_RESULT regnbif_gpu_BIF_PERFCOUNTER1_RESULT; -typedef union nbif_gpu_BIF_MST_TRANS_PENDING_VF regnbif_gpu_BIF_MST_TRANS_PENDING_VF; -typedef union nbif_gpu_BIF_SLV_TRANS_PENDING_VF regnbif_gpu_BIF_SLV_TRANS_PENDING_VF; -typedef union nbif_gpu_BACO_CNTL regnbif_gpu_BACO_CNTL; -typedef union nbif_gpu_BIF_BACO_EXIT_TIME0 regnbif_gpu_BIF_BACO_EXIT_TIME0; -typedef union nbif_gpu_BIF_BACO_EXIT_TIMER1 regnbif_gpu_BIF_BACO_EXIT_TIMER1; -typedef union nbif_gpu_BIF_BACO_EXIT_TIMER2 regnbif_gpu_BIF_BACO_EXIT_TIMER2; -typedef union nbif_gpu_BIF_BACO_EXIT_TIMER3 regnbif_gpu_BIF_BACO_EXIT_TIMER3; -typedef union nbif_gpu_BIF_BACO_EXIT_TIMER4 regnbif_gpu_BIF_BACO_EXIT_TIMER4; -typedef union nbif_gpu_MEM_TYPE_CNTL regnbif_gpu_MEM_TYPE_CNTL; -typedef union nbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS regnbif_gpu_SMU_BIF_VDDGFX_PWR_STATUS; -typedef union nbif_gpu_BIF_VDDGFX_GFX0_LOWER regnbif_gpu_BIF_VDDGFX_GFX0_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_GFX0_UPPER regnbif_gpu_BIF_VDDGFX_GFX0_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_GFX1_LOWER regnbif_gpu_BIF_VDDGFX_GFX1_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_GFX1_UPPER regnbif_gpu_BIF_VDDGFX_GFX1_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_GFX2_LOWER regnbif_gpu_BIF_VDDGFX_GFX2_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_GFX2_UPPER regnbif_gpu_BIF_VDDGFX_GFX2_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_GFX3_LOWER regnbif_gpu_BIF_VDDGFX_GFX3_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_GFX3_UPPER regnbif_gpu_BIF_VDDGFX_GFX3_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_GFX4_LOWER regnbif_gpu_BIF_VDDGFX_GFX4_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_GFX4_UPPER regnbif_gpu_BIF_VDDGFX_GFX4_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_GFX5_LOWER regnbif_gpu_BIF_VDDGFX_GFX5_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_GFX5_UPPER regnbif_gpu_BIF_VDDGFX_GFX5_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_RSV1_LOWER regnbif_gpu_BIF_VDDGFX_RSV1_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_RSV1_UPPER regnbif_gpu_BIF_VDDGFX_RSV1_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_RSV2_LOWER regnbif_gpu_BIF_VDDGFX_RSV2_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_RSV2_UPPER regnbif_gpu_BIF_VDDGFX_RSV2_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_RSV3_LOWER regnbif_gpu_BIF_VDDGFX_RSV3_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_RSV3_UPPER regnbif_gpu_BIF_VDDGFX_RSV3_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_RSV4_LOWER regnbif_gpu_BIF_VDDGFX_RSV4_LOWER; -typedef union nbif_gpu_BIF_VDDGFX_RSV4_UPPER regnbif_gpu_BIF_VDDGFX_RSV4_UPPER; -typedef union nbif_gpu_BIF_VDDGFX_FB_CMP regnbif_gpu_BIF_VDDGFX_FB_CMP; -typedef union nbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER regnbif_gpu_BIF_DOORBELL_GBLAPER1_LOWER; -typedef union nbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER regnbif_gpu_BIF_DOORBELL_GBLAPER1_UPPER; -typedef union nbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER regnbif_gpu_BIF_DOORBELL_GBLAPER2_LOWER; -typedef union nbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER regnbif_gpu_BIF_DOORBELL_GBLAPER2_UPPER; -typedef union nbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL regnbif_gpu_REMAP_HDP_MEM_FLUSH_CNTL; -typedef union nbif_gpu_REMAP_HDP_REG_FLUSH_CNTL regnbif_gpu_REMAP_HDP_REG_FLUSH_CNTL; -typedef union nbif_gpu_BIF_RB_CNTL regnbif_gpu_BIF_RB_CNTL; -typedef union nbif_gpu_BIF_RB_BASE regnbif_gpu_BIF_RB_BASE; -typedef union nbif_gpu_BIF_RB_RPTR regnbif_gpu_BIF_RB_RPTR; -typedef union nbif_gpu_BIF_RB_WPTR regnbif_gpu_BIF_RB_WPTR; -typedef union nbif_gpu_BIF_RB_WPTR_ADDR_HI regnbif_gpu_BIF_RB_WPTR_ADDR_HI; -typedef union nbif_gpu_BIF_RB_WPTR_ADDR_LO regnbif_gpu_BIF_RB_WPTR_ADDR_LO; -typedef union nbif_gpu_MAILBOX_INDEX regnbif_gpu_MAILBOX_INDEX; -typedef union nbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION regnbif_gpu_BIF_GPUIOV_RESET_NOTIFICATION; -typedef union nbif_gpu_BIF_GMI_WRR_WEIGHT regnbif_gpu_BIF_GMI_WRR_WEIGHT; -typedef union nbif_gpu_NBIF_STRAP_WRITE_CTRL regnbif_gpu_NBIF_STRAP_WRITE_CTRL; -typedef union nbif_gpu_BIF_BME_STATUS regnbif_gpu_BIF_BME_STATUS; -typedef union nbif_gpu_BIF_ATOMIC_ERR_LOG regnbif_gpu_BIF_ATOMIC_ERR_LOG; -typedef union nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH - regnbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_HIGH; -typedef union nbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW - regnbif_gpu_DOORBELL_SELFRING_GPA_APER_BASE_LOW; -typedef union nbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL regnbif_gpu_DOORBELL_SELFRING_GPA_APER_CNTL; -typedef union nbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL regnbif_gpu_HDP_REG_COHERENCY_FLUSH_CNTL; -typedef union nbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL regnbif_gpu_HDP_MEM_COHERENCY_FLUSH_CNTL; -typedef union nbif_gpu_GPU_HDP_FLUSH_REQ regnbif_gpu_GPU_HDP_FLUSH_REQ; -typedef union nbif_gpu_GPU_HDP_FLUSH_DONE regnbif_gpu_GPU_HDP_FLUSH_DONE; -typedef union nbif_gpu_BIF_TRANS_PENDING regnbif_gpu_BIF_TRANS_PENDING; -typedef union nbif_gpu_MAILBOX_MSGBUF_TRN_DW0 regnbif_gpu_MAILBOX_MSGBUF_TRN_DW0; -typedef union nbif_gpu_MAILBOX_MSGBUF_TRN_DW1 regnbif_gpu_MAILBOX_MSGBUF_TRN_DW1; -typedef union nbif_gpu_MAILBOX_MSGBUF_TRN_DW2 regnbif_gpu_MAILBOX_MSGBUF_TRN_DW2; -typedef union nbif_gpu_MAILBOX_MSGBUF_TRN_DW3 regnbif_gpu_MAILBOX_MSGBUF_TRN_DW3; -typedef union nbif_gpu_MAILBOX_MSGBUF_RCV_DW0 regnbif_gpu_MAILBOX_MSGBUF_RCV_DW0; -typedef union nbif_gpu_MAILBOX_MSGBUF_RCV_DW1 regnbif_gpu_MAILBOX_MSGBUF_RCV_DW1; -typedef union nbif_gpu_MAILBOX_MSGBUF_RCV_DW2 regnbif_gpu_MAILBOX_MSGBUF_RCV_DW2; -typedef union nbif_gpu_MAILBOX_MSGBUF_RCV_DW3 regnbif_gpu_MAILBOX_MSGBUF_RCV_DW3; -typedef union nbif_gpu_MAILBOX_CONTROL regnbif_gpu_MAILBOX_CONTROL; -typedef union nbif_gpu_MAILBOX_INT_CNTL regnbif_gpu_MAILBOX_INT_CNTL; -typedef union nbif_gpu_BIF_VMHV_MAILBOX regnbif_gpu_BIF_VMHV_MAILBOX; -typedef union nbif_gpu_VENDOR_ID_epf regnbif_gpu_VENDOR_ID_epf; -typedef union nbif_gpu_DEVICE_ID_epf regnbif_gpu_DEVICE_ID_epf; -typedef union nbif_gpu_COMMAND_epf regnbif_gpu_COMMAND_epf; -typedef union nbif_gpu_STATUS_epf regnbif_gpu_STATUS_epf; -typedef union nbif_gpu_REVISION_ID_epf regnbif_gpu_REVISION_ID_epf; -typedef union nbif_gpu_PROG_INTERFACE_epf regnbif_gpu_PROG_INTERFACE_epf; -typedef union nbif_gpu_SUB_CLASS_epf regnbif_gpu_SUB_CLASS_epf; -typedef union nbif_gpu_BASE_CLASS_epf regnbif_gpu_BASE_CLASS_epf; -typedef union nbif_gpu_CACHE_LINE_epf regnbif_gpu_CACHE_LINE_epf; -typedef union nbif_gpu_LATENCY_epf regnbif_gpu_LATENCY_epf; -typedef union nbif_gpu_HEADER_epf regnbif_gpu_HEADER_epf; -typedef union nbif_gpu_BIST_epf regnbif_gpu_BIST_epf; -typedef union nbif_gpu_BASE_ADDR_1_epf regnbif_gpu_BASE_ADDR_1_epf; -typedef union nbif_gpu_BASE_ADDR_2_epf regnbif_gpu_BASE_ADDR_2_epf; -typedef union nbif_gpu_BASE_ADDR_3_epf regnbif_gpu_BASE_ADDR_3_epf; -typedef union nbif_gpu_BASE_ADDR_4_epf regnbif_gpu_BASE_ADDR_4_epf; -typedef union nbif_gpu_BASE_ADDR_5_epf regnbif_gpu_BASE_ADDR_5_epf; -typedef union nbif_gpu_BASE_ADDR_6_epf regnbif_gpu_BASE_ADDR_6_epf; -typedef union nbif_gpu_ROM_BASE_ADDR_epf regnbif_gpu_ROM_BASE_ADDR_epf; -typedef union nbif_gpu_CAP_PTR_epf regnbif_gpu_CAP_PTR_epf; -typedef union nbif_gpu_INTERRUPT_LINE_epf regnbif_gpu_INTERRUPT_LINE_epf; -typedef union nbif_gpu_INTERRUPT_PIN_epf regnbif_gpu_INTERRUPT_PIN_epf; -typedef union nbif_gpu_ADAPTER_ID_epf regnbif_gpu_ADAPTER_ID_epf; -typedef union nbif_gpu_MIN_GRANT_epf regnbif_gpu_MIN_GRANT_epf; -typedef union nbif_gpu_MAX_LATENCY_epf regnbif_gpu_MAX_LATENCY_epf; -typedef union nbif_gpu_VENDOR_CAP_LIST_epf regnbif_gpu_VENDOR_CAP_LIST_epf; -typedef union nbif_gpu_ADAPTER_ID_W_epf regnbif_gpu_ADAPTER_ID_W_epf; -typedef union nbif_gpu_PMI_CAP_LIST_epf regnbif_gpu_PMI_CAP_LIST_epf; -typedef union nbif_gpu_PMI_CAP_epf regnbif_gpu_PMI_CAP_epf; -typedef union nbif_gpu_PMI_STATUS_CNTL_epf regnbif_gpu_PMI_STATUS_CNTL_epf; -typedef union nbif_gpu_PCIE_CAP_LIST_epf regnbif_gpu_PCIE_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_CAP_epf regnbif_gpu_PCIE_CAP_epf; -typedef union nbif_gpu_DEVICE_CAP_epf regnbif_gpu_DEVICE_CAP_epf; -typedef union nbif_gpu_DEVICE_CNTL_epf regnbif_gpu_DEVICE_CNTL_epf; -typedef union nbif_gpu_DEVICE_STATUS_epf regnbif_gpu_DEVICE_STATUS_epf; -typedef union nbif_gpu_LINK_CAP_epf regnbif_gpu_LINK_CAP_epf; -typedef union nbif_gpu_LINK_CNTL_epf regnbif_gpu_LINK_CNTL_epf; -typedef union nbif_gpu_LINK_STATUS_epf regnbif_gpu_LINK_STATUS_epf; -typedef union nbif_gpu_DEVICE_CAP2_epf regnbif_gpu_DEVICE_CAP2_epf; -typedef union nbif_gpu_DEVICE_CNTL2_epf regnbif_gpu_DEVICE_CNTL2_epf; -typedef union nbif_gpu_DEVICE_STATUS2_epf regnbif_gpu_DEVICE_STATUS2_epf; -typedef union nbif_gpu_LINK_CAP2_epf regnbif_gpu_LINK_CAP2_epf; -typedef union nbif_gpu_LINK_CNTL2_epf regnbif_gpu_LINK_CNTL2_epf; -typedef union nbif_gpu_LINK_STATUS2_epf regnbif_gpu_LINK_STATUS2_epf; -typedef union nbif_gpu_SLOT_CAP2_epf regnbif_gpu_SLOT_CAP2_epf; -typedef union nbif_gpu_SLOT_CNTL2_epf regnbif_gpu_SLOT_CNTL2_epf; -typedef union nbif_gpu_SLOT_STATUS2_epf regnbif_gpu_SLOT_STATUS2_epf; -typedef union nbif_gpu_MSI_CAP_LIST_epf regnbif_gpu_MSI_CAP_LIST_epf; -typedef union nbif_gpu_MSI_MSG_CNTL_epf regnbif_gpu_MSI_MSG_CNTL_epf; -typedef union nbif_gpu_MSI_MSG_ADDR_LO_epf regnbif_gpu_MSI_MSG_ADDR_LO_epf; -typedef union nbif_gpu_MSI_MSG_ADDR_HI_epf regnbif_gpu_MSI_MSG_ADDR_HI_epf; -typedef union nbif_gpu_MSI_MSG_DATA_64_epf regnbif_gpu_MSI_MSG_DATA_64_epf; -typedef union nbif_gpu_MSI_MSG_DATA_epf regnbif_gpu_MSI_MSG_DATA_epf; -typedef union nbif_gpu_MSI_MASK_epf regnbif_gpu_MSI_MASK_epf; -typedef union nbif_gpu_MSI_PENDING_epf regnbif_gpu_MSI_PENDING_epf; -typedef union nbif_gpu_MSI_MASK_64_epf regnbif_gpu_MSI_MASK_64_epf; -typedef union nbif_gpu_MSI_PENDING_64_epf regnbif_gpu_MSI_PENDING_64_epf; -typedef union nbif_gpu_MSIX_CAP_LIST_epf regnbif_gpu_MSIX_CAP_LIST_epf; -typedef union nbif_gpu_MSIX_MSG_CNTL_epf regnbif_gpu_MSIX_MSG_CNTL_epf; -typedef union nbif_gpu_MSIX_TABLE_epf regnbif_gpu_MSIX_TABLE_epf; -typedef union nbif_gpu_MSIX_PBA_epf regnbif_gpu_MSIX_PBA_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC1_epf regnbif_gpu_PCIE_VENDOR_SPECIFIC1_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC2_epf regnbif_gpu_PCIE_VENDOR_SPECIFIC2_epf; -typedef union nbif_gpu_PCIE_VC_ENH_CAP_LIST_epf regnbif_gpu_PCIE_VC_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_PORT_VC_CAP_REG1_epf regnbif_gpu_PCIE_PORT_VC_CAP_REG1_epf; -typedef union nbif_gpu_PCIE_PORT_VC_CAP_REG2_epf regnbif_gpu_PCIE_PORT_VC_CAP_REG2_epf; -typedef union nbif_gpu_PCIE_PORT_VC_CNTL_epf regnbif_gpu_PCIE_PORT_VC_CNTL_epf; -typedef union nbif_gpu_PCIE_PORT_VC_STATUS_epf regnbif_gpu_PCIE_PORT_VC_STATUS_epf; -typedef union nbif_gpu_PCIE_VC0_RESOURCE_CAP_epf regnbif_gpu_PCIE_VC0_RESOURCE_CAP_epf; -typedef union nbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf regnbif_gpu_PCIE_VC0_RESOURCE_CNTL_epf; -typedef union nbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf regnbif_gpu_PCIE_VC0_RESOURCE_STATUS_epf; -typedef union nbif_gpu_PCIE_VC1_RESOURCE_CAP_epf regnbif_gpu_PCIE_VC1_RESOURCE_CAP_epf; -typedef union nbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf regnbif_gpu_PCIE_VC1_RESOURCE_CNTL_epf; -typedef union nbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf regnbif_gpu_PCIE_VC1_RESOURCE_STATUS_epf; -typedef union nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf - regnbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf regnbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_epf; -typedef union nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf regnbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_epf; -typedef union nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf - regnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_UNCORR_ERR_STATUS_epf regnbif_gpu_PCIE_UNCORR_ERR_STATUS_epf; -typedef union nbif_gpu_PCIE_UNCORR_ERR_MASK_epf regnbif_gpu_PCIE_UNCORR_ERR_MASK_epf; -typedef union nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf regnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epf; -typedef union nbif_gpu_PCIE_CORR_ERR_STATUS_epf regnbif_gpu_PCIE_CORR_ERR_STATUS_epf; -typedef union nbif_gpu_PCIE_CORR_ERR_MASK_epf regnbif_gpu_PCIE_CORR_ERR_MASK_epf; -typedef union nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf regnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epf; -typedef union nbif_gpu_PCIE_HDR_LOG0_epf regnbif_gpu_PCIE_HDR_LOG0_epf; -typedef union nbif_gpu_PCIE_HDR_LOG1_epf regnbif_gpu_PCIE_HDR_LOG1_epf; -typedef union nbif_gpu_PCIE_HDR_LOG2_epf regnbif_gpu_PCIE_HDR_LOG2_epf; -typedef union nbif_gpu_PCIE_HDR_LOG3_epf regnbif_gpu_PCIE_HDR_LOG3_epf; -typedef union nbif_gpu_PCIE_ROOT_ERR_CMD_epf regnbif_gpu_PCIE_ROOT_ERR_CMD_epf; -typedef union nbif_gpu_PCIE_ROOT_ERR_STATUS_epf regnbif_gpu_PCIE_ROOT_ERR_STATUS_epf; -typedef union nbif_gpu_PCIE_ERR_SRC_ID_epf regnbif_gpu_PCIE_ERR_SRC_ID_epf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG0_epf regnbif_gpu_PCIE_TLP_PREFIX_LOG0_epf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG1_epf regnbif_gpu_PCIE_TLP_PREFIX_LOG1_epf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG2_epf regnbif_gpu_PCIE_TLP_PREFIX_LOG2_epf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG3_epf regnbif_gpu_PCIE_TLP_PREFIX_LOG3_epf; -typedef union nbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf regnbif_gpu_PCIE_BAR_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_BAR1_CAP_epf regnbif_gpu_PCIE_BAR1_CAP_epf; -typedef union nbif_gpu_PCIE_BAR1_CNTL_epf regnbif_gpu_PCIE_BAR1_CNTL_epf; -typedef union nbif_gpu_PCIE_BAR2_CAP_epf regnbif_gpu_PCIE_BAR2_CAP_epf; -typedef union nbif_gpu_PCIE_BAR2_CNTL_epf regnbif_gpu_PCIE_BAR2_CNTL_epf; -typedef union nbif_gpu_PCIE_BAR3_CAP_epf regnbif_gpu_PCIE_BAR3_CAP_epf; -typedef union nbif_gpu_PCIE_BAR3_CNTL_epf regnbif_gpu_PCIE_BAR3_CNTL_epf; -typedef union nbif_gpu_PCIE_BAR4_CAP_epf regnbif_gpu_PCIE_BAR4_CAP_epf; -typedef union nbif_gpu_PCIE_BAR4_CNTL_epf regnbif_gpu_PCIE_BAR4_CNTL_epf; -typedef union nbif_gpu_PCIE_BAR5_CAP_epf regnbif_gpu_PCIE_BAR5_CAP_epf; -typedef union nbif_gpu_PCIE_BAR5_CNTL_epf regnbif_gpu_PCIE_BAR5_CNTL_epf; -typedef union nbif_gpu_PCIE_BAR6_CAP_epf regnbif_gpu_PCIE_BAR6_CAP_epf; -typedef union nbif_gpu_PCIE_BAR6_CNTL_epf regnbif_gpu_PCIE_BAR6_CNTL_epf; -typedef union nbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf - regnbif_gpu_PCIE_PWR_BUDGET_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf regnbif_gpu_PCIE_PWR_BUDGET_DATA_SELECT_epf; -typedef union nbif_gpu_PCIE_PWR_BUDGET_DATA_epf regnbif_gpu_PCIE_PWR_BUDGET_DATA_epf; -typedef union nbif_gpu_PCIE_PWR_BUDGET_CAP_epf regnbif_gpu_PCIE_PWR_BUDGET_CAP_epf; -typedef union nbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf regnbif_gpu_PCIE_DPA_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_DPA_CAP_epf regnbif_gpu_PCIE_DPA_CAP_epf; -typedef union nbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf regnbif_gpu_PCIE_DPA_LATENCY_INDICATOR_epf; -typedef union nbif_gpu_PCIE_DPA_STATUS_epf regnbif_gpu_PCIE_DPA_STATUS_epf; -typedef union nbif_gpu_PCIE_DPA_CNTL_epf regnbif_gpu_PCIE_DPA_CNTL_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_epf; -typedef union nbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf - regnbif_gpu_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_epf; -typedef union nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf regnbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_LINK_CNTL3_epf regnbif_gpu_PCIE_LINK_CNTL3_epf; -typedef union nbif_gpu_PCIE_LANE_ERROR_STATUS_epf regnbif_gpu_PCIE_LANE_ERROR_STATUS_epf; -typedef union nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf - regnbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_epf; -typedef union nbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf regnbif_gpu_PCIE_ACS_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_ACS_CAP_epf regnbif_gpu_PCIE_ACS_CAP_epf; -typedef union nbif_gpu_PCIE_ACS_CNTL_epf regnbif_gpu_PCIE_ACS_CNTL_epf; -typedef union nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf regnbif_gpu_PCIE_ATS_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_ATS_CAP_epf regnbif_gpu_PCIE_ATS_CAP_epf; -typedef union nbif_gpu_PCIE_ATS_CNTL_epf regnbif_gpu_PCIE_ATS_CNTL_epf; -typedef union nbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf regnbif_gpu_PCIE_PAGE_REQ_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_PAGE_REQ_CNTL_epf regnbif_gpu_PCIE_PAGE_REQ_CNTL_epf; -typedef union nbif_gpu_PCIE_PAGE_REQ_STATUS_epf regnbif_gpu_PCIE_PAGE_REQ_STATUS_epf; -typedef union nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf - regnbif_gpu_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_epf; -typedef union nbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf - regnbif_gpu_PCIE_OUTSTAND_PAGE_REQ_ALLOC_epf; -typedef union nbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf regnbif_gpu_PCIE_PASID_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_PASID_CAP_epf regnbif_gpu_PCIE_PASID_CAP_epf; -typedef union nbif_gpu_PCIE_PASID_CNTL_epf regnbif_gpu_PCIE_PASID_CNTL_epf; -typedef union nbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf regnbif_gpu_PCIE_TPH_REQR_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_TPH_REQR_CAP_epf regnbif_gpu_PCIE_TPH_REQR_CAP_epf; -typedef union nbif_gpu_PCIE_TPH_REQR_CNTL_epf regnbif_gpu_PCIE_TPH_REQR_CNTL_epf; -typedef union nbif_gpu_PCIE_MC_ENH_CAP_LIST_epf regnbif_gpu_PCIE_MC_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_MC_CAP_epf regnbif_gpu_PCIE_MC_CAP_epf; -typedef union nbif_gpu_PCIE_MC_CNTL_epf regnbif_gpu_PCIE_MC_CNTL_epf; -typedef union nbif_gpu_PCIE_MC_ADDR0_epf regnbif_gpu_PCIE_MC_ADDR0_epf; -typedef union nbif_gpu_PCIE_MC_ADDR1_epf regnbif_gpu_PCIE_MC_ADDR1_epf; -typedef union nbif_gpu_PCIE_MC_RCV0_epf regnbif_gpu_PCIE_MC_RCV0_epf; -typedef union nbif_gpu_PCIE_MC_RCV1_epf regnbif_gpu_PCIE_MC_RCV1_epf; -typedef union nbif_gpu_PCIE_MC_BLOCK_ALL0_epf regnbif_gpu_PCIE_MC_BLOCK_ALL0_epf; -typedef union nbif_gpu_PCIE_MC_BLOCK_ALL1_epf regnbif_gpu_PCIE_MC_BLOCK_ALL1_epf; -typedef union nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf - regnbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_0_epf; -typedef union nbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf - regnbif_gpu_PCIE_MC_BLOCK_UNTRANSLATED_1_epf; -typedef union nbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf regnbif_gpu_PCIE_LTR_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_LTR_CAP_epf regnbif_gpu_PCIE_LTR_CAP_epf; -typedef union nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf regnbif_gpu_PCIE_ARI_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_ARI_CAP_epf regnbif_gpu_PCIE_ARI_CAP_epf; -typedef union nbif_gpu_PCIE_ARI_CNTL_epf regnbif_gpu_PCIE_ARI_CNTL_epf; -typedef union nbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf regnbif_gpu_PCIE_SRIOV_ENH_CAP_LIST_epf; -typedef union nbif_gpu_PCIE_SRIOV_CAP_epf regnbif_gpu_PCIE_SRIOV_CAP_epf; -typedef union nbif_gpu_PCIE_SRIOV_CONTROL_epf regnbif_gpu_PCIE_SRIOV_CONTROL_epf; -typedef union nbif_gpu_PCIE_SRIOV_STATUS_epf regnbif_gpu_PCIE_SRIOV_STATUS_epf; -typedef union nbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf regnbif_gpu_PCIE_SRIOV_INITIAL_VFS_epf; -typedef union nbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf regnbif_gpu_PCIE_SRIOV_TOTAL_VFS_epf; -typedef union nbif_gpu_PCIE_SRIOV_NUM_VFS_epf regnbif_gpu_PCIE_SRIOV_NUM_VFS_epf; -typedef union nbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf regnbif_gpu_PCIE_SRIOV_FUNC_DEP_LINK_epf; -typedef union nbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf regnbif_gpu_PCIE_SRIOV_FIRST_VF_OFFSET_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_STRIDE_epf regnbif_gpu_PCIE_SRIOV_VF_STRIDE_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf regnbif_gpu_PCIE_SRIOV_VF_DEVICE_ID_epf; -typedef union nbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf - regnbif_gpu_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_epf; -typedef union nbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf regnbif_gpu_PCIE_SRIOV_SYSTEM_PAGE_SIZE_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf regnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_0_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf regnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_1_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf regnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_2_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf regnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_3_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf regnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_4_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf regnbif_gpu_PCIE_SRIOV_VF_BASE_ADDR_5_epf; -typedef union nbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf - regnbif_gpu_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_epf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_epf; -typedef union nbif_gpu_VENDOR_ID_epvf regnbif_gpu_VENDOR_ID_epvf; -typedef union nbif_gpu_DEVICE_ID_epvf regnbif_gpu_DEVICE_ID_epvf; -typedef union nbif_gpu_COMMAND_epvf regnbif_gpu_COMMAND_epvf; -typedef union nbif_gpu_STATUS_epvf regnbif_gpu_STATUS_epvf; -typedef union nbif_gpu_REVISION_ID_epvf regnbif_gpu_REVISION_ID_epvf; -typedef union nbif_gpu_PROG_INTERFACE_epvf regnbif_gpu_PROG_INTERFACE_epvf; -typedef union nbif_gpu_SUB_CLASS_epvf regnbif_gpu_SUB_CLASS_epvf; -typedef union nbif_gpu_BASE_CLASS_epvf regnbif_gpu_BASE_CLASS_epvf; -typedef union nbif_gpu_CACHE_LINE_epvf regnbif_gpu_CACHE_LINE_epvf; -typedef union nbif_gpu_LATENCY_epvf regnbif_gpu_LATENCY_epvf; -typedef union nbif_gpu_HEADER_epvf regnbif_gpu_HEADER_epvf; -typedef union nbif_gpu_BIST_epvf regnbif_gpu_BIST_epvf; -typedef union nbif_gpu_BASE_ADDR_1_epvf regnbif_gpu_BASE_ADDR_1_epvf; -typedef union nbif_gpu_BASE_ADDR_2_epvf regnbif_gpu_BASE_ADDR_2_epvf; -typedef union nbif_gpu_BASE_ADDR_3_epvf regnbif_gpu_BASE_ADDR_3_epvf; -typedef union nbif_gpu_BASE_ADDR_4_epvf regnbif_gpu_BASE_ADDR_4_epvf; -typedef union nbif_gpu_BASE_ADDR_5_epvf regnbif_gpu_BASE_ADDR_5_epvf; -typedef union nbif_gpu_BASE_ADDR_6_epvf regnbif_gpu_BASE_ADDR_6_epvf; -typedef union nbif_gpu_ROM_BASE_ADDR_epvf regnbif_gpu_ROM_BASE_ADDR_epvf; -typedef union nbif_gpu_CAP_PTR_epvf regnbif_gpu_CAP_PTR_epvf; -typedef union nbif_gpu_INTERRUPT_LINE_epvf regnbif_gpu_INTERRUPT_LINE_epvf; -typedef union nbif_gpu_INTERRUPT_PIN_epvf regnbif_gpu_INTERRUPT_PIN_epvf; -typedef union nbif_gpu_ADAPTER_ID_epvf regnbif_gpu_ADAPTER_ID_epvf; -typedef union nbif_gpu_PCIE_CAP_LIST_epvf regnbif_gpu_PCIE_CAP_LIST_epvf; -typedef union nbif_gpu_PCIE_CAP_epvf regnbif_gpu_PCIE_CAP_epvf; -typedef union nbif_gpu_DEVICE_CAP_epvf regnbif_gpu_DEVICE_CAP_epvf; -typedef union nbif_gpu_DEVICE_CNTL_epvf regnbif_gpu_DEVICE_CNTL_epvf; -typedef union nbif_gpu_DEVICE_STATUS_epvf regnbif_gpu_DEVICE_STATUS_epvf; -typedef union nbif_gpu_LINK_CAP_epvf regnbif_gpu_LINK_CAP_epvf; -typedef union nbif_gpu_LINK_CNTL_epvf regnbif_gpu_LINK_CNTL_epvf; -typedef union nbif_gpu_LINK_STATUS_epvf regnbif_gpu_LINK_STATUS_epvf; -typedef union nbif_gpu_DEVICE_CAP2_epvf regnbif_gpu_DEVICE_CAP2_epvf; -typedef union nbif_gpu_DEVICE_CNTL2_epvf regnbif_gpu_DEVICE_CNTL2_epvf; -typedef union nbif_gpu_DEVICE_STATUS2_epvf regnbif_gpu_DEVICE_STATUS2_epvf; -typedef union nbif_gpu_LINK_CAP2_epvf regnbif_gpu_LINK_CAP2_epvf; -typedef union nbif_gpu_LINK_CNTL2_epvf regnbif_gpu_LINK_CNTL2_epvf; -typedef union nbif_gpu_LINK_STATUS2_epvf regnbif_gpu_LINK_STATUS2_epvf; -typedef union nbif_gpu_SLOT_CAP2_epvf regnbif_gpu_SLOT_CAP2_epvf; -typedef union nbif_gpu_SLOT_CNTL2_epvf regnbif_gpu_SLOT_CNTL2_epvf; -typedef union nbif_gpu_SLOT_STATUS2_epvf regnbif_gpu_SLOT_STATUS2_epvf; -typedef union nbif_gpu_MSI_CAP_LIST_epvf regnbif_gpu_MSI_CAP_LIST_epvf; -typedef union nbif_gpu_MSI_MSG_CNTL_epvf regnbif_gpu_MSI_MSG_CNTL_epvf; -typedef union nbif_gpu_MSI_MSG_ADDR_LO_epvf regnbif_gpu_MSI_MSG_ADDR_LO_epvf; -typedef union nbif_gpu_MSI_MSG_ADDR_HI_epvf regnbif_gpu_MSI_MSG_ADDR_HI_epvf; -typedef union nbif_gpu_MSI_MSG_DATA_64_epvf regnbif_gpu_MSI_MSG_DATA_64_epvf; -typedef union nbif_gpu_MSI_MSG_DATA_epvf regnbif_gpu_MSI_MSG_DATA_epvf; -typedef union nbif_gpu_MSI_MASK_epvf regnbif_gpu_MSI_MASK_epvf; -typedef union nbif_gpu_MSI_PENDING_epvf regnbif_gpu_MSI_PENDING_epvf; -typedef union nbif_gpu_MSI_MASK_64_epvf regnbif_gpu_MSI_MASK_64_epvf; -typedef union nbif_gpu_MSI_PENDING_64_epvf regnbif_gpu_MSI_PENDING_64_epvf; -typedef union nbif_gpu_MSIX_CAP_LIST_epvf regnbif_gpu_MSIX_CAP_LIST_epvf; -typedef union nbif_gpu_MSIX_MSG_CNTL_epvf regnbif_gpu_MSIX_MSG_CNTL_epvf; -typedef union nbif_gpu_MSIX_TABLE_epvf regnbif_gpu_MSIX_TABLE_epvf; -typedef union nbif_gpu_MSIX_PBA_epvf regnbif_gpu_MSIX_PBA_epvf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf - regnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_epvf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_epvf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf regnbif_gpu_PCIE_VENDOR_SPECIFIC1_epvf; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf regnbif_gpu_PCIE_VENDOR_SPECIFIC2_epvf; -typedef union nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf - regnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_epvf; -typedef union nbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf regnbif_gpu_PCIE_UNCORR_ERR_STATUS_epvf; -typedef union nbif_gpu_PCIE_UNCORR_ERR_MASK_epvf regnbif_gpu_PCIE_UNCORR_ERR_MASK_epvf; -typedef union nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf regnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_epvf; -typedef union nbif_gpu_PCIE_CORR_ERR_STATUS_epvf regnbif_gpu_PCIE_CORR_ERR_STATUS_epvf; -typedef union nbif_gpu_PCIE_CORR_ERR_MASK_epvf regnbif_gpu_PCIE_CORR_ERR_MASK_epvf; -typedef union nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf regnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_epvf; -typedef union nbif_gpu_PCIE_HDR_LOG0_epvf regnbif_gpu_PCIE_HDR_LOG0_epvf; -typedef union nbif_gpu_PCIE_HDR_LOG1_epvf regnbif_gpu_PCIE_HDR_LOG1_epvf; -typedef union nbif_gpu_PCIE_HDR_LOG2_epvf regnbif_gpu_PCIE_HDR_LOG2_epvf; -typedef union nbif_gpu_PCIE_HDR_LOG3_epvf regnbif_gpu_PCIE_HDR_LOG3_epvf; -typedef union nbif_gpu_PCIE_ROOT_ERR_CMD_epvf regnbif_gpu_PCIE_ROOT_ERR_CMD_epvf; -typedef union nbif_gpu_PCIE_ROOT_ERR_STATUS_epvf regnbif_gpu_PCIE_ROOT_ERR_STATUS_epvf; -typedef union nbif_gpu_PCIE_ERR_SRC_ID_epvf regnbif_gpu_PCIE_ERR_SRC_ID_epvf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf regnbif_gpu_PCIE_TLP_PREFIX_LOG0_epvf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf regnbif_gpu_PCIE_TLP_PREFIX_LOG1_epvf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf regnbif_gpu_PCIE_TLP_PREFIX_LOG2_epvf; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf regnbif_gpu_PCIE_TLP_PREFIX_LOG3_epvf; -typedef union nbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf regnbif_gpu_PCIE_ATS_ENH_CAP_LIST_epvf; -typedef union nbif_gpu_PCIE_ATS_CAP_epvf regnbif_gpu_PCIE_ATS_CAP_epvf; -typedef union nbif_gpu_PCIE_ATS_CNTL_epvf regnbif_gpu_PCIE_ATS_CNTL_epvf; -typedef union nbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf regnbif_gpu_PCIE_ARI_ENH_CAP_LIST_epvf; -typedef union nbif_gpu_PCIE_ARI_CAP_epvf regnbif_gpu_PCIE_ARI_CAP_epvf; -typedef union nbif_gpu_PCIE_ARI_CNTL_epvf regnbif_gpu_PCIE_ARI_CNTL_epvf; -typedef union nbif_gpu_RCC_BACO_CNTL_MISC regnbif_gpu_RCC_BACO_CNTL_MISC; -typedef union nbif_gpu_RCC_RESET_EN regnbif_gpu_RCC_RESET_EN; -typedef union nbif_gpu_RCC_VDM_SUPPORT regnbif_gpu_RCC_VDM_SUPPORT; -typedef union nbif_gpu_RCC_BUS_CNTL regnbif_gpu_RCC_BUS_CNTL; -typedef union nbif_gpu_RCC_CONFIG_CNTL regnbif_gpu_RCC_CONFIG_CNTL; -typedef union nbif_gpu_RCC_CONFIG_F0_BASE regnbif_gpu_RCC_CONFIG_F0_BASE; -typedef union nbif_gpu_RCC_CONFIG_APER_SIZE regnbif_gpu_RCC_CONFIG_APER_SIZE; -typedef union nbif_gpu_RCC_CONFIG_REG_APER_SIZE regnbif_gpu_RCC_CONFIG_REG_APER_SIZE; -typedef union nbif_gpu_RCC_XDMA_LO regnbif_gpu_RCC_XDMA_LO; -typedef union nbif_gpu_RCC_XDMA_HI regnbif_gpu_RCC_XDMA_HI; -typedef union nbif_gpu_RCC_FEATURES_CONTROL_MISC regnbif_gpu_RCC_FEATURES_CONTROL_MISC; -typedef union nbif_gpu_RCC_BUSNUM_CNTL1 regnbif_gpu_RCC_BUSNUM_CNTL1; -typedef union nbif_gpu_RCC_BUSNUM_LIST0 regnbif_gpu_RCC_BUSNUM_LIST0; -typedef union nbif_gpu_RCC_BUSNUM_LIST1 regnbif_gpu_RCC_BUSNUM_LIST1; -typedef union nbif_gpu_RCC_BUSNUM_CNTL2 regnbif_gpu_RCC_BUSNUM_CNTL2; -typedef union nbif_gpu_RCC_CAPTURE_HOST_BUSNUM regnbif_gpu_RCC_CAPTURE_HOST_BUSNUM; -typedef union nbif_gpu_RCC_HOST_BUSNUM regnbif_gpu_RCC_HOST_BUSNUM; -typedef union nbif_gpu_RCC_PEER0_FB_OFFSET_HI regnbif_gpu_RCC_PEER0_FB_OFFSET_HI; -typedef union nbif_gpu_RCC_PEER0_FB_OFFSET_LO regnbif_gpu_RCC_PEER0_FB_OFFSET_LO; -typedef union nbif_gpu_RCC_PEER1_FB_OFFSET_HI regnbif_gpu_RCC_PEER1_FB_OFFSET_HI; -typedef union nbif_gpu_RCC_PEER1_FB_OFFSET_LO regnbif_gpu_RCC_PEER1_FB_OFFSET_LO; -typedef union nbif_gpu_RCC_PEER2_FB_OFFSET_HI regnbif_gpu_RCC_PEER2_FB_OFFSET_HI; -typedef union nbif_gpu_RCC_PEER2_FB_OFFSET_LO regnbif_gpu_RCC_PEER2_FB_OFFSET_LO; -typedef union nbif_gpu_RCC_PEER3_FB_OFFSET_HI regnbif_gpu_RCC_PEER3_FB_OFFSET_HI; -typedef union nbif_gpu_RCC_PEER3_FB_OFFSET_LO regnbif_gpu_RCC_PEER3_FB_OFFSET_LO; -typedef union nbif_gpu_RCC_DEVFUNCNUM_LIST0 regnbif_gpu_RCC_DEVFUNCNUM_LIST0; -typedef union nbif_gpu_RCC_DEVFUNCNUM_LIST1 regnbif_gpu_RCC_DEVFUNCNUM_LIST1; -typedef union nbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO regnbif_gpu_RCC_GPUIOV_FB_TOTAL_FB_INFO; -typedef union nbif_gpu_RCC_DEV0_LINK_CNTL regnbif_gpu_RCC_DEV0_LINK_CNTL; -typedef union nbif_gpu_RCC_CMN_LINK_CNTL regnbif_gpu_RCC_CMN_LINK_CNTL; -typedef union nbif_gpu_RCC_EP_REQUESTERID_RESTORE regnbif_gpu_RCC_EP_REQUESTERID_RESTORE; -typedef union nbif_gpu_RCC_LTR_LSWITCH_CNTL regnbif_gpu_RCC_LTR_LSWITCH_CNTL; -typedef union nbif_gpu_RCC_MH_ARB_CNTL regnbif_gpu_RCC_MH_ARB_CNTL; -typedef union nbif_gpu_GFXMSIX_VECT0_ADDR_LO regnbif_gpu_GFXMSIX_VECT0_ADDR_LO; -typedef union nbif_gpu_GFXMSIX_VECT1_ADDR_LO regnbif_gpu_GFXMSIX_VECT1_ADDR_LO; -typedef union nbif_gpu_GFXMSIX_VECT2_ADDR_LO regnbif_gpu_GFXMSIX_VECT2_ADDR_LO; -typedef union nbif_gpu_GFXMSIX_VECT0_ADDR_HI regnbif_gpu_GFXMSIX_VECT0_ADDR_HI; -typedef union nbif_gpu_GFXMSIX_VECT1_ADDR_HI regnbif_gpu_GFXMSIX_VECT1_ADDR_HI; -typedef union nbif_gpu_GFXMSIX_VECT2_ADDR_HI regnbif_gpu_GFXMSIX_VECT2_ADDR_HI; -typedef union nbif_gpu_GFXMSIX_VECT0_MSG_DATA regnbif_gpu_GFXMSIX_VECT0_MSG_DATA; -typedef union nbif_gpu_GFXMSIX_VECT1_MSG_DATA regnbif_gpu_GFXMSIX_VECT1_MSG_DATA; -typedef union nbif_gpu_GFXMSIX_VECT2_MSG_DATA regnbif_gpu_GFXMSIX_VECT2_MSG_DATA; -typedef union nbif_gpu_GFXMSIX_VECT0_CONTROL regnbif_gpu_GFXMSIX_VECT0_CONTROL; -typedef union nbif_gpu_GFXMSIX_VECT1_CONTROL regnbif_gpu_GFXMSIX_VECT1_CONTROL; -typedef union nbif_gpu_GFXMSIX_VECT2_CONTROL regnbif_gpu_GFXMSIX_VECT2_CONTROL; -typedef union nbif_gpu_GFXMSIX_PBA regnbif_gpu_GFXMSIX_PBA; -typedef union nbif_gpu_RCC_DOORBELL_APER_EN regnbif_gpu_RCC_DOORBELL_APER_EN; -typedef union nbif_gpu_RCC_CONFIG_MEMSIZE regnbif_gpu_RCC_CONFIG_MEMSIZE; -typedef union nbif_gpu_RCC_CONFIG_RESERVED regnbif_gpu_RCC_CONFIG_RESERVED; -typedef union nbif_gpu_RCC_IOV_FUNC_IDENTIFIER regnbif_gpu_RCC_IOV_FUNC_IDENTIFIER; -typedef union nbif_gpu_DN_PCIE_RESERVED regnbif_gpu_DN_PCIE_RESERVED; -typedef union nbif_gpu_DN_PCIE_SCRATCH regnbif_gpu_DN_PCIE_SCRATCH; -typedef union nbif_gpu_DN_PCIE_HW_DEBUG regnbif_gpu_DN_PCIE_HW_DEBUG; -typedef union nbif_gpu_DN_PCIE_CNTL regnbif_gpu_DN_PCIE_CNTL; -typedef union nbif_gpu_DN_PCIE_CONFIG_CNTL regnbif_gpu_DN_PCIE_CONFIG_CNTL; -typedef union nbif_gpu_DN_PCIE_RX_CNTL2 regnbif_gpu_DN_PCIE_RX_CNTL2; -typedef union nbif_gpu_DN_PCIE_BUS_CNTL regnbif_gpu_DN_PCIE_BUS_CNTL; -typedef union nbif_gpu_DN_PCIE_CFG_CNTL regnbif_gpu_DN_PCIE_CFG_CNTL; -typedef union nbif_gpu_DN_PCIE_STRAP_F0 regnbif_gpu_DN_PCIE_STRAP_F0; -typedef union nbif_gpu_DN_PCIE_STRAP_MISC regnbif_gpu_DN_PCIE_STRAP_MISC; -typedef union nbif_gpu_DN_PCIE_STRAP_MISC2 regnbif_gpu_DN_PCIE_STRAP_MISC2; -typedef union nbif_gpu_PCIEP_RESERVED regnbif_gpu_PCIEP_RESERVED; -typedef union nbif_gpu_PCIEP_SCRATCH regnbif_gpu_PCIEP_SCRATCH; -typedef union nbif_gpu_PCIEP_HW_DEBUG regnbif_gpu_PCIEP_HW_DEBUG; -typedef union nbif_gpu_PCIE_ERR_CNTL regnbif_gpu_PCIE_ERR_CNTL; -typedef union nbif_gpu_PCIE_RX_CNTL regnbif_gpu_PCIE_RX_CNTL; -typedef union nbif_gpu_PCIE_LC_SPEED_CNTL regnbif_gpu_PCIE_LC_SPEED_CNTL; -typedef union nbif_gpu_PCIE_LC_CNTL2 regnbif_gpu_PCIE_LC_CNTL2; -typedef union nbif_gpu_PCIEP_STRAP_MISC regnbif_gpu_PCIEP_STRAP_MISC; -typedef union nbif_gpu_LTR_MSG_INFO_FROM_EP regnbif_gpu_LTR_MSG_INFO_FROM_EP; -typedef union nbif_gpu_VENDOR_ID_swds regnbif_gpu_VENDOR_ID_swds; -typedef union nbif_gpu_DEVICE_ID_swds regnbif_gpu_DEVICE_ID_swds; -typedef union nbif_gpu_COMMAND_swds regnbif_gpu_COMMAND_swds; -typedef union nbif_gpu_STATUS_swds regnbif_gpu_STATUS_swds; -typedef union nbif_gpu_REVISION_ID_swds regnbif_gpu_REVISION_ID_swds; -typedef union nbif_gpu_PROG_INTERFACE_swds regnbif_gpu_PROG_INTERFACE_swds; -typedef union nbif_gpu_SUB_CLASS_swds regnbif_gpu_SUB_CLASS_swds; -typedef union nbif_gpu_BASE_CLASS_swds regnbif_gpu_BASE_CLASS_swds; -typedef union nbif_gpu_CACHE_LINE_swds regnbif_gpu_CACHE_LINE_swds; -typedef union nbif_gpu_LATENCY_swds regnbif_gpu_LATENCY_swds; -typedef union nbif_gpu_HEADER_swds regnbif_gpu_HEADER_swds; -typedef union nbif_gpu_BIST_swds regnbif_gpu_BIST_swds; -typedef union nbif_gpu_BASE_ADDR_1_swds regnbif_gpu_BASE_ADDR_1_swds; -typedef union nbif_gpu_SUB_BUS_NUMBER_LATENCY_swds regnbif_gpu_SUB_BUS_NUMBER_LATENCY_swds; -typedef union nbif_gpu_IO_BASE_LIMIT_swds regnbif_gpu_IO_BASE_LIMIT_swds; -typedef union nbif_gpu_SECONDARY_STATUS_swds regnbif_gpu_SECONDARY_STATUS_swds; -typedef union nbif_gpu_MEM_BASE_LIMIT_swds regnbif_gpu_MEM_BASE_LIMIT_swds; -typedef union nbif_gpu_PREF_BASE_LIMIT_swds regnbif_gpu_PREF_BASE_LIMIT_swds; -typedef union nbif_gpu_PREF_BASE_UPPER_swds regnbif_gpu_PREF_BASE_UPPER_swds; -typedef union nbif_gpu_PREF_LIMIT_UPPER_swds regnbif_gpu_PREF_LIMIT_UPPER_swds; -typedef union nbif_gpu_IO_BASE_LIMIT_HI_swds regnbif_gpu_IO_BASE_LIMIT_HI_swds; -typedef union nbif_gpu_IRQ_BRIDGE_CNTL_swds regnbif_gpu_IRQ_BRIDGE_CNTL_swds; -typedef union nbif_gpu_CAP_PTR_swds regnbif_gpu_CAP_PTR_swds; -typedef union nbif_gpu_INTERRUPT_LINE_swds regnbif_gpu_INTERRUPT_LINE_swds; -typedef union nbif_gpu_INTERRUPT_PIN_swds regnbif_gpu_INTERRUPT_PIN_swds; -typedef union nbif_gpu_PMI_CAP_LIST_swds regnbif_gpu_PMI_CAP_LIST_swds; -typedef union nbif_gpu_PMI_CAP_swds regnbif_gpu_PMI_CAP_swds; -typedef union nbif_gpu_PMI_STATUS_CNTL_swds regnbif_gpu_PMI_STATUS_CNTL_swds; -typedef union nbif_gpu_PCIE_CAP_LIST_swds regnbif_gpu_PCIE_CAP_LIST_swds; -typedef union nbif_gpu_PCIE_CAP_swds regnbif_gpu_PCIE_CAP_swds; -typedef union nbif_gpu_DEVICE_CAP_swds regnbif_gpu_DEVICE_CAP_swds; -typedef union nbif_gpu_DEVICE_CNTL_swds regnbif_gpu_DEVICE_CNTL_swds; -typedef union nbif_gpu_DEVICE_STATUS_swds regnbif_gpu_DEVICE_STATUS_swds; -typedef union nbif_gpu_LINK_CAP_swds regnbif_gpu_LINK_CAP_swds; -typedef union nbif_gpu_LINK_CNTL_swds regnbif_gpu_LINK_CNTL_swds; -typedef union nbif_gpu_LINK_STATUS_swds regnbif_gpu_LINK_STATUS_swds; -typedef union nbif_gpu_SLOT_CAP_swds regnbif_gpu_SLOT_CAP_swds; -typedef union nbif_gpu_SLOT_CNTL_swds regnbif_gpu_SLOT_CNTL_swds; -typedef union nbif_gpu_SLOT_STATUS_swds regnbif_gpu_SLOT_STATUS_swds; -typedef union nbif_gpu_DEVICE_CAP2_swds regnbif_gpu_DEVICE_CAP2_swds; -typedef union nbif_gpu_DEVICE_CNTL2_swds regnbif_gpu_DEVICE_CNTL2_swds; -typedef union nbif_gpu_DEVICE_STATUS2_swds regnbif_gpu_DEVICE_STATUS2_swds; -typedef union nbif_gpu_LINK_CAP2_swds regnbif_gpu_LINK_CAP2_swds; -typedef union nbif_gpu_LINK_CNTL2_swds regnbif_gpu_LINK_CNTL2_swds; -typedef union nbif_gpu_LINK_STATUS2_swds regnbif_gpu_LINK_STATUS2_swds; -typedef union nbif_gpu_SLOT_CAP2_swds regnbif_gpu_SLOT_CAP2_swds; -typedef union nbif_gpu_SLOT_CNTL2_swds regnbif_gpu_SLOT_CNTL2_swds; -typedef union nbif_gpu_SLOT_STATUS2_swds regnbif_gpu_SLOT_STATUS2_swds; -typedef union nbif_gpu_MSI_CAP_LIST_swds regnbif_gpu_MSI_CAP_LIST_swds; -typedef union nbif_gpu_MSI_MSG_CNTL_swds regnbif_gpu_MSI_MSG_CNTL_swds; -typedef union nbif_gpu_MSI_MSG_ADDR_LO_swds regnbif_gpu_MSI_MSG_ADDR_LO_swds; -typedef union nbif_gpu_MSI_MSG_ADDR_HI_swds regnbif_gpu_MSI_MSG_ADDR_HI_swds; -typedef union nbif_gpu_MSI_MSG_DATA_64_swds regnbif_gpu_MSI_MSG_DATA_64_swds; -typedef union nbif_gpu_MSI_MSG_DATA_swds regnbif_gpu_MSI_MSG_DATA_swds; -typedef union nbif_gpu_SSID_CAP_LIST_swds regnbif_gpu_SSID_CAP_LIST_swds; -typedef union nbif_gpu_SSID_CAP_swds regnbif_gpu_SSID_CAP_swds; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds - regnbif_gpu_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_swds; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds regnbif_gpu_PCIE_VENDOR_SPECIFIC_HDR_swds; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC1_swds regnbif_gpu_PCIE_VENDOR_SPECIFIC1_swds; -typedef union nbif_gpu_PCIE_VENDOR_SPECIFIC2_swds regnbif_gpu_PCIE_VENDOR_SPECIFIC2_swds; -typedef union nbif_gpu_PCIE_VC_ENH_CAP_LIST_swds regnbif_gpu_PCIE_VC_ENH_CAP_LIST_swds; -typedef union nbif_gpu_PCIE_PORT_VC_CAP_REG1_swds regnbif_gpu_PCIE_PORT_VC_CAP_REG1_swds; -typedef union nbif_gpu_PCIE_PORT_VC_CAP_REG2_swds regnbif_gpu_PCIE_PORT_VC_CAP_REG2_swds; -typedef union nbif_gpu_PCIE_PORT_VC_CNTL_swds regnbif_gpu_PCIE_PORT_VC_CNTL_swds; -typedef union nbif_gpu_PCIE_PORT_VC_STATUS_swds regnbif_gpu_PCIE_PORT_VC_STATUS_swds; -typedef union nbif_gpu_PCIE_VC0_RESOURCE_CAP_swds regnbif_gpu_PCIE_VC0_RESOURCE_CAP_swds; -typedef union nbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds regnbif_gpu_PCIE_VC0_RESOURCE_CNTL_swds; -typedef union nbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds regnbif_gpu_PCIE_VC0_RESOURCE_STATUS_swds; -typedef union nbif_gpu_PCIE_VC1_RESOURCE_CAP_swds regnbif_gpu_PCIE_VC1_RESOURCE_CAP_swds; -typedef union nbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds regnbif_gpu_PCIE_VC1_RESOURCE_CNTL_swds; -typedef union nbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds regnbif_gpu_PCIE_VC1_RESOURCE_STATUS_swds; -typedef union nbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds - regnbif_gpu_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_swds; -typedef union nbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds regnbif_gpu_PCIE_DEV_SERIAL_NUM_DW1_swds; -typedef union nbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds regnbif_gpu_PCIE_DEV_SERIAL_NUM_DW2_swds; -typedef union nbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds - regnbif_gpu_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_swds; -typedef union nbif_gpu_PCIE_UNCORR_ERR_STATUS_swds regnbif_gpu_PCIE_UNCORR_ERR_STATUS_swds; -typedef union nbif_gpu_PCIE_UNCORR_ERR_MASK_swds regnbif_gpu_PCIE_UNCORR_ERR_MASK_swds; -typedef union nbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds regnbif_gpu_PCIE_UNCORR_ERR_SEVERITY_swds; -typedef union nbif_gpu_PCIE_CORR_ERR_STATUS_swds regnbif_gpu_PCIE_CORR_ERR_STATUS_swds; -typedef union nbif_gpu_PCIE_CORR_ERR_MASK_swds regnbif_gpu_PCIE_CORR_ERR_MASK_swds; -typedef union nbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds regnbif_gpu_PCIE_ADV_ERR_CAP_CNTL_swds; -typedef union nbif_gpu_PCIE_HDR_LOG0_swds regnbif_gpu_PCIE_HDR_LOG0_swds; -typedef union nbif_gpu_PCIE_HDR_LOG1_swds regnbif_gpu_PCIE_HDR_LOG1_swds; -typedef union nbif_gpu_PCIE_HDR_LOG2_swds regnbif_gpu_PCIE_HDR_LOG2_swds; -typedef union nbif_gpu_PCIE_HDR_LOG3_swds regnbif_gpu_PCIE_HDR_LOG3_swds; -typedef union nbif_gpu_PCIE_ROOT_ERR_CMD_swds regnbif_gpu_PCIE_ROOT_ERR_CMD_swds; -typedef union nbif_gpu_PCIE_ROOT_ERR_STATUS_swds regnbif_gpu_PCIE_ROOT_ERR_STATUS_swds; -typedef union nbif_gpu_PCIE_ERR_SRC_ID_swds regnbif_gpu_PCIE_ERR_SRC_ID_swds; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG0_swds regnbif_gpu_PCIE_TLP_PREFIX_LOG0_swds; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG1_swds regnbif_gpu_PCIE_TLP_PREFIX_LOG1_swds; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG2_swds regnbif_gpu_PCIE_TLP_PREFIX_LOG2_swds; -typedef union nbif_gpu_PCIE_TLP_PREFIX_LOG3_swds regnbif_gpu_PCIE_TLP_PREFIX_LOG3_swds; -typedef union nbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds - regnbif_gpu_PCIE_SECONDARY_ENH_CAP_LIST_swds; -typedef union nbif_gpu_PCIE_LINK_CNTL3_swds regnbif_gpu_PCIE_LINK_CNTL3_swds; -typedef union nbif_gpu_PCIE_LANE_ERROR_STATUS_swds regnbif_gpu_PCIE_LANE_ERROR_STATUS_swds; -typedef union nbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_0_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_1_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_2_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_3_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_4_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_5_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_6_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_7_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_8_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_9_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_10_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_11_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_12_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_13_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_14_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds - regnbif_gpu_PCIE_LANE_15_EQUALIZATION_CNTL_swds; -typedef union nbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds regnbif_gpu_PCIE_ACS_ENH_CAP_LIST_swds; -typedef union nbif_gpu_PCIE_ACS_CAP_swds regnbif_gpu_PCIE_ACS_CAP_swds; -typedef union nbif_gpu_PCIE_ACS_CNTL_swds regnbif_gpu_PCIE_ACS_CNTL_swds; -typedef union nbif_gpu_SHADOW_COMMAND regnbif_gpu_SHADOW_COMMAND; -typedef union nbif_gpu_SHADOW_BASE_ADDR_1 regnbif_gpu_SHADOW_BASE_ADDR_1; -typedef union nbif_gpu_SHADOW_BASE_ADDR_2 regnbif_gpu_SHADOW_BASE_ADDR_2; -typedef union nbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY regnbif_gpu_SHADOW_SUB_BUS_NUMBER_LATENCY; -typedef union nbif_gpu_SHADOW_IO_BASE_LIMIT regnbif_gpu_SHADOW_IO_BASE_LIMIT; -typedef union nbif_gpu_SHADOW_MEM_BASE_LIMIT regnbif_gpu_SHADOW_MEM_BASE_LIMIT; -typedef union nbif_gpu_SHADOW_PREF_BASE_LIMIT regnbif_gpu_SHADOW_PREF_BASE_LIMIT; -typedef union nbif_gpu_SHADOW_PREF_BASE_UPPER regnbif_gpu_SHADOW_PREF_BASE_UPPER; -typedef union nbif_gpu_SHADOW_PREF_LIMIT_UPPER regnbif_gpu_SHADOW_PREF_LIMIT_UPPER; -typedef union nbif_gpu_SHADOW_IO_BASE_LIMIT_HI regnbif_gpu_SHADOW_IO_BASE_LIMIT_HI; -typedef union nbif_gpu_SHADOW_IRQ_BRIDGE_CNTL regnbif_gpu_SHADOW_IRQ_BRIDGE_CNTL; -typedef union nbif_gpu_SUC_INDEX regnbif_gpu_SUC_INDEX; -typedef union nbif_gpu_SUC_DATA regnbif_gpu_SUC_DATA; -typedef union nbif_gpu_EP_PCIE_SCRATCH regnbif_gpu_EP_PCIE_SCRATCH; -typedef union nbif_gpu_EP_PCIE_HW_DEBUG regnbif_gpu_EP_PCIE_HW_DEBUG; -typedef union nbif_gpu_EP_PCIE_CNTL regnbif_gpu_EP_PCIE_CNTL; -typedef union nbif_gpu_EP_PCIE_INT_CNTL regnbif_gpu_EP_PCIE_INT_CNTL; -typedef union nbif_gpu_EP_PCIE_INT_STATUS regnbif_gpu_EP_PCIE_INT_STATUS; -typedef union nbif_gpu_EP_PCIE_RX_CNTL2 regnbif_gpu_EP_PCIE_RX_CNTL2; -typedef union nbif_gpu_EP_PCIE_BUS_CNTL regnbif_gpu_EP_PCIE_BUS_CNTL; -typedef union nbif_gpu_EP_PCIE_CFG_CNTL regnbif_gpu_EP_PCIE_CFG_CNTL; -typedef union nbif_gpu_EP_PCIE_OBFF_CNTL regnbif_gpu_EP_PCIE_OBFF_CNTL; -typedef union nbif_gpu_EP_PCIE_TX_LTR_CNTL regnbif_gpu_EP_PCIE_TX_LTR_CNTL; -typedef union nbif_gpu_EP_PCIE_STRAP_MISC regnbif_gpu_EP_PCIE_STRAP_MISC; -typedef union nbif_gpu_EP_PCIE_STRAP_MISC2 regnbif_gpu_EP_PCIE_STRAP_MISC2; -typedef union nbif_gpu_EP_PCIE_STRAP_PI regnbif_gpu_EP_PCIE_STRAP_PI; -typedef union nbif_gpu_EP_PCIE_F0_DPA_CAP regnbif_gpu_EP_PCIE_F0_DPA_CAP; -typedef union nbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR - regnbif_gpu_EP_PCIE_F0_DPA_LATENCY_INDICATOR; -typedef union nbif_gpu_EP_PCIE_F0_DPA_CNTL regnbif_gpu_EP_PCIE_F0_DPA_CNTL; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6; -typedef union nbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 - regnbif_gpu_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7; -typedef union nbif_gpu_EP_PCIE_PME_CONTROL regnbif_gpu_EP_PCIE_PME_CONTROL; -typedef union nbif_gpu_EP_PCIEP_RESERVED regnbif_gpu_EP_PCIEP_RESERVED; -typedef union nbif_gpu_EP_PCIEP_HW_DEBUG regnbif_gpu_EP_PCIEP_HW_DEBUG; -typedef union nbif_gpu_EP_PCIE_TX_CNTL regnbif_gpu_EP_PCIE_TX_CNTL; -typedef union nbif_gpu_EP_PCIE_TX_REQUESTER_ID regnbif_gpu_EP_PCIE_TX_REQUESTER_ID; -typedef union nbif_gpu_EP_PCIE_ERR_CNTL regnbif_gpu_EP_PCIE_ERR_CNTL; -typedef union nbif_gpu_EP_PCIE_RX_CNTL regnbif_gpu_EP_PCIE_RX_CNTL; -typedef union nbif_gpu_EP_PCIE_LC_SPEED_CNTL regnbif_gpu_EP_PCIE_LC_SPEED_CNTL; -typedef union nbif_gpu_A2S_CNTL_CL0 regnbif_gpu_A2S_CNTL_CL0; -typedef union nbif_gpu_A2S_CNTL_CL1 regnbif_gpu_A2S_CNTL_CL1; -typedef union nbif_gpu_A2S_CNTL_CL2 regnbif_gpu_A2S_CNTL_CL2; -typedef union nbif_gpu_A2S_CNTL_CL3 regnbif_gpu_A2S_CNTL_CL3; -typedef union nbif_gpu_A2S_CNTL_CL4 regnbif_gpu_A2S_CNTL_CL4; -typedef union nbif_gpu_A2S_CNTL_SW0 regnbif_gpu_A2S_CNTL_SW0; -typedef union nbif_gpu_A2S_CNTL_SW1 regnbif_gpu_A2S_CNTL_SW1; -typedef union nbif_gpu_A2S_CNTL_SW2 regnbif_gpu_A2S_CNTL_SW2; -typedef union nbif_gpu_A2S_CNTL2_SEC_CL0 regnbif_gpu_A2S_CNTL2_SEC_CL0; -typedef union nbif_gpu_A2S_CNTL2_SEC_CL1 regnbif_gpu_A2S_CNTL2_SEC_CL1; -typedef union nbif_gpu_A2S_CNTL2_SEC_CL2 regnbif_gpu_A2S_CNTL2_SEC_CL2; -typedef union nbif_gpu_A2S_CNTL2_SEC_CL3 regnbif_gpu_A2S_CNTL2_SEC_CL3; -typedef union nbif_gpu_A2S_CNTL2_SEC_CL4 regnbif_gpu_A2S_CNTL2_SEC_CL4; -typedef union nbif_gpu_NGDC_MGCG_CTRL regnbif_gpu_NGDC_MGCG_CTRL; -typedef union nbif_gpu_A2S_MISC_CNTL regnbif_gpu_A2S_MISC_CNTL; -typedef union nbif_gpu_NGDC_SDP_PORT_CTRL regnbif_gpu_NGDC_SDP_PORT_CTRL; -typedef union nbif_gpu_BIF_SDMA0_DOORBELL_RANGE regnbif_gpu_BIF_SDMA0_DOORBELL_RANGE; -typedef union nbif_gpu_BIF_SDMA1_DOORBELL_RANGE regnbif_gpu_BIF_SDMA1_DOORBELL_RANGE; -typedef union nbif_gpu_BIF_IH_DOORBELL_RANGE regnbif_gpu_BIF_IH_DOORBELL_RANGE; -typedef union nbif_gpu_BIF_MMSCH0_DOORBELL_RANGE regnbif_gpu_BIF_MMSCH0_DOORBELL_RANGE; -typedef union nbif_gpu_S2A_MISC_CNTL regnbif_gpu_S2A_MISC_CNTL; -typedef union nbif_gpu_GDC_RAS_LEAF0_CTRL regnbif_gpu_GDC_RAS_LEAF0_CTRL; -typedef union nbif_gpu_GDC_RAS_LEAF1_CTRL regnbif_gpu_GDC_RAS_LEAF1_CTRL; -typedef union nbif_gpu_GDC_RAS_LEAF2_CTRL regnbif_gpu_GDC_RAS_LEAF2_CTRL; -typedef union nbif_gpu_GDC_RAS_LEAF3_CTRL regnbif_gpu_GDC_RAS_LEAF3_CTRL; -typedef union nbif_gpu_GDC_RAS_LEAF4_CTRL regnbif_gpu_GDC_RAS_LEAF4_CTRL; -typedef union nbif_gpu_GDC_RAS_LEAF5_CTRL regnbif_gpu_GDC_RAS_LEAF5_CTRL; -typedef union nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG0 regnbif_gpu_SION_CL0_RdRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL0_RdRsp_BurstTarget_REG1 regnbif_gpu_SION_CL0_RdRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG0 regnbif_gpu_SION_CL0_RdRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL0_RdRsp_TimeSlot_REG1 regnbif_gpu_SION_CL0_RdRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG0 regnbif_gpu_SION_CL0_WrRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL0_WrRsp_BurstTarget_REG1 regnbif_gpu_SION_CL0_WrRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG0 regnbif_gpu_SION_CL0_WrRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL0_WrRsp_TimeSlot_REG1 regnbif_gpu_SION_CL0_WrRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL0_Req_BurstTarget_REG0 regnbif_gpu_SION_CL0_Req_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL0_Req_BurstTarget_REG1 regnbif_gpu_SION_CL0_Req_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL0_Req_TimeSlot_REG0 regnbif_gpu_SION_CL0_Req_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL0_Req_TimeSlot_REG1 regnbif_gpu_SION_CL0_Req_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL0_ReqPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL0_DataPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL0_RdRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL0_WrRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG0 regnbif_gpu_SION_CL1_RdRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL1_RdRsp_BurstTarget_REG1 regnbif_gpu_SION_CL1_RdRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG0 regnbif_gpu_SION_CL1_RdRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL1_RdRsp_TimeSlot_REG1 regnbif_gpu_SION_CL1_RdRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG0 regnbif_gpu_SION_CL1_WrRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL1_WrRsp_BurstTarget_REG1 regnbif_gpu_SION_CL1_WrRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG0 regnbif_gpu_SION_CL1_WrRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL1_WrRsp_TimeSlot_REG1 regnbif_gpu_SION_CL1_WrRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL1_Req_BurstTarget_REG0 regnbif_gpu_SION_CL1_Req_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL1_Req_BurstTarget_REG1 regnbif_gpu_SION_CL1_Req_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL1_Req_TimeSlot_REG0 regnbif_gpu_SION_CL1_Req_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL1_Req_TimeSlot_REG1 regnbif_gpu_SION_CL1_Req_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL1_ReqPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL1_DataPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL1_RdRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL1_WrRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG0 regnbif_gpu_SION_CL2_RdRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL2_RdRsp_BurstTarget_REG1 regnbif_gpu_SION_CL2_RdRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG0 regnbif_gpu_SION_CL2_RdRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL2_RdRsp_TimeSlot_REG1 regnbif_gpu_SION_CL2_RdRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG0 regnbif_gpu_SION_CL2_WrRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL2_WrRsp_BurstTarget_REG1 regnbif_gpu_SION_CL2_WrRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG0 regnbif_gpu_SION_CL2_WrRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL2_WrRsp_TimeSlot_REG1 regnbif_gpu_SION_CL2_WrRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL2_Req_BurstTarget_REG0 regnbif_gpu_SION_CL2_Req_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL2_Req_BurstTarget_REG1 regnbif_gpu_SION_CL2_Req_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL2_Req_TimeSlot_REG0 regnbif_gpu_SION_CL2_Req_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL2_Req_TimeSlot_REG1 regnbif_gpu_SION_CL2_Req_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL2_ReqPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL2_DataPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL2_RdRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL2_WrRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG0 regnbif_gpu_SION_CL3_RdRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL3_RdRsp_BurstTarget_REG1 regnbif_gpu_SION_CL3_RdRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG0 regnbif_gpu_SION_CL3_RdRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL3_RdRsp_TimeSlot_REG1 regnbif_gpu_SION_CL3_RdRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG0 regnbif_gpu_SION_CL3_WrRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL3_WrRsp_BurstTarget_REG1 regnbif_gpu_SION_CL3_WrRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG0 regnbif_gpu_SION_CL3_WrRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL3_WrRsp_TimeSlot_REG1 regnbif_gpu_SION_CL3_WrRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL3_Req_BurstTarget_REG0 regnbif_gpu_SION_CL3_Req_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL3_Req_BurstTarget_REG1 regnbif_gpu_SION_CL3_Req_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL3_Req_TimeSlot_REG0 regnbif_gpu_SION_CL3_Req_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL3_Req_TimeSlot_REG1 regnbif_gpu_SION_CL3_Req_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL3_ReqPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL3_DataPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL3_RdRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL3_WrRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG0 regnbif_gpu_SION_CL4_RdRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL4_RdRsp_BurstTarget_REG1 regnbif_gpu_SION_CL4_RdRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG0 regnbif_gpu_SION_CL4_RdRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL4_RdRsp_TimeSlot_REG1 regnbif_gpu_SION_CL4_RdRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG0 regnbif_gpu_SION_CL4_WrRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL4_WrRsp_BurstTarget_REG1 regnbif_gpu_SION_CL4_WrRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG0 regnbif_gpu_SION_CL4_WrRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL4_WrRsp_TimeSlot_REG1 regnbif_gpu_SION_CL4_WrRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL4_Req_BurstTarget_REG0 regnbif_gpu_SION_CL4_Req_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL4_Req_BurstTarget_REG1 regnbif_gpu_SION_CL4_Req_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL4_Req_TimeSlot_REG0 regnbif_gpu_SION_CL4_Req_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL4_Req_TimeSlot_REG1 regnbif_gpu_SION_CL4_Req_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL4_ReqPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL4_DataPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL4_RdRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL4_WrRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG0 regnbif_gpu_SION_CL5_RdRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL5_RdRsp_BurstTarget_REG1 regnbif_gpu_SION_CL5_RdRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG0 regnbif_gpu_SION_CL5_RdRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL5_RdRsp_TimeSlot_REG1 regnbif_gpu_SION_CL5_RdRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG0 regnbif_gpu_SION_CL5_WrRsp_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL5_WrRsp_BurstTarget_REG1 regnbif_gpu_SION_CL5_WrRsp_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG0 regnbif_gpu_SION_CL5_WrRsp_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL5_WrRsp_TimeSlot_REG1 regnbif_gpu_SION_CL5_WrRsp_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL5_Req_BurstTarget_REG0 regnbif_gpu_SION_CL5_Req_BurstTarget_REG0; -typedef union nbif_gpu_SION_CL5_Req_BurstTarget_REG1 regnbif_gpu_SION_CL5_Req_BurstTarget_REG1; -typedef union nbif_gpu_SION_CL5_Req_TimeSlot_REG0 regnbif_gpu_SION_CL5_Req_TimeSlot_REG0; -typedef union nbif_gpu_SION_CL5_Req_TimeSlot_REG1 regnbif_gpu_SION_CL5_Req_TimeSlot_REG1; -typedef union nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL5_ReqPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL5_DataPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL5_RdRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG0 - regnbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG0; -typedef union nbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG1 - regnbif_gpu_SION_CL5_WrRspPoolCredit_Alloc_REG1; -typedef union nbif_gpu_SION_CNTL_REG0 regnbif_gpu_SION_CNTL_REG0; -typedef union nbif_gpu_SION_CNTL_REG1 regnbif_gpu_SION_CNTL_REG1; -typedef union nbif_gpu_RCC_BIF_STRAP0 regnbif_gpu_RCC_BIF_STRAP0; -typedef union nbif_gpu_RCC_BIF_STRAP1 regnbif_gpu_RCC_BIF_STRAP1; -typedef union nbif_gpu_RCC_BIF_STRAP2 regnbif_gpu_RCC_BIF_STRAP2; -typedef union nbif_gpu_RCC_BIF_STRAP3 regnbif_gpu_RCC_BIF_STRAP3; -typedef union nbif_gpu_RCC_BIF_STRAP4 regnbif_gpu_RCC_BIF_STRAP4; -typedef union nbif_gpu_RCC_BIF_STRAP5 regnbif_gpu_RCC_BIF_STRAP5; -typedef union nbif_gpu_RCC_BIF_STRAP6 regnbif_gpu_RCC_BIF_STRAP6; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP0 regnbif_gpu_RCC_DEV0_PORT_STRAP0; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP1 regnbif_gpu_RCC_DEV0_PORT_STRAP1; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP2 regnbif_gpu_RCC_DEV0_PORT_STRAP2; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP3 regnbif_gpu_RCC_DEV0_PORT_STRAP3; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP4 regnbif_gpu_RCC_DEV0_PORT_STRAP4; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP5 regnbif_gpu_RCC_DEV0_PORT_STRAP5; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP6 regnbif_gpu_RCC_DEV0_PORT_STRAP6; -typedef union nbif_gpu_RCC_DEV0_PORT_STRAP7 regnbif_gpu_RCC_DEV0_PORT_STRAP7; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP0 regnbif_gpu_RCC_DEV0_EPF0_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP1 regnbif_gpu_RCC_DEV0_EPF0_STRAP1; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP13 regnbif_gpu_RCC_DEV0_EPF0_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP2 regnbif_gpu_RCC_DEV0_EPF0_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP3 regnbif_gpu_RCC_DEV0_EPF0_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP4 regnbif_gpu_RCC_DEV0_EPF0_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP5 regnbif_gpu_RCC_DEV0_EPF0_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP8 regnbif_gpu_RCC_DEV0_EPF0_STRAP8; -typedef union nbif_gpu_RCC_DEV0_EPF0_STRAP9 regnbif_gpu_RCC_DEV0_EPF0_STRAP9; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP0 regnbif_gpu_RCC_DEV0_EPF1_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP10 regnbif_gpu_RCC_DEV0_EPF1_STRAP10; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP11 regnbif_gpu_RCC_DEV0_EPF1_STRAP11; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP12 regnbif_gpu_RCC_DEV0_EPF1_STRAP12; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP13 regnbif_gpu_RCC_DEV0_EPF1_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP2 regnbif_gpu_RCC_DEV0_EPF1_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP3 regnbif_gpu_RCC_DEV0_EPF1_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP4 regnbif_gpu_RCC_DEV0_EPF1_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP5 regnbif_gpu_RCC_DEV0_EPF1_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP6 regnbif_gpu_RCC_DEV0_EPF1_STRAP6; -typedef union nbif_gpu_RCC_DEV0_EPF1_STRAP7 regnbif_gpu_RCC_DEV0_EPF1_STRAP7; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP0 regnbif_gpu_RCC_DEV1_PORT_STRAP0; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP1 regnbif_gpu_RCC_DEV1_PORT_STRAP1; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP2 regnbif_gpu_RCC_DEV1_PORT_STRAP2; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP3 regnbif_gpu_RCC_DEV1_PORT_STRAP3; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP4 regnbif_gpu_RCC_DEV1_PORT_STRAP4; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP5 regnbif_gpu_RCC_DEV1_PORT_STRAP5; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP6 regnbif_gpu_RCC_DEV1_PORT_STRAP6; -typedef union nbif_gpu_RCC_DEV1_PORT_STRAP7 regnbif_gpu_RCC_DEV1_PORT_STRAP7; -typedef union nbif_gpu_RCC_DEV0_EPF2_STRAP0 regnbif_gpu_RCC_DEV0_EPF2_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF2_STRAP13 regnbif_gpu_RCC_DEV0_EPF2_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF2_STRAP2 regnbif_gpu_RCC_DEV0_EPF2_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF2_STRAP3 regnbif_gpu_RCC_DEV0_EPF2_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF2_STRAP4 regnbif_gpu_RCC_DEV0_EPF2_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF2_STRAP5 regnbif_gpu_RCC_DEV0_EPF2_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF2_STRAP6 regnbif_gpu_RCC_DEV0_EPF2_STRAP6; -typedef union nbif_gpu_RCC_DEV0_EPF3_STRAP0 regnbif_gpu_RCC_DEV0_EPF3_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF3_STRAP13 regnbif_gpu_RCC_DEV0_EPF3_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF3_STRAP2 regnbif_gpu_RCC_DEV0_EPF3_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF3_STRAP3 regnbif_gpu_RCC_DEV0_EPF3_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF3_STRAP4 regnbif_gpu_RCC_DEV0_EPF3_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF3_STRAP5 regnbif_gpu_RCC_DEV0_EPF3_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF3_STRAP6 regnbif_gpu_RCC_DEV0_EPF3_STRAP6; -typedef union nbif_gpu_RCC_DEV0_EPF4_STRAP0 regnbif_gpu_RCC_DEV0_EPF4_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF4_STRAP13 regnbif_gpu_RCC_DEV0_EPF4_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF4_STRAP2 regnbif_gpu_RCC_DEV0_EPF4_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF4_STRAP3 regnbif_gpu_RCC_DEV0_EPF4_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF4_STRAP4 regnbif_gpu_RCC_DEV0_EPF4_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF4_STRAP5 regnbif_gpu_RCC_DEV0_EPF4_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF4_STRAP6 regnbif_gpu_RCC_DEV0_EPF4_STRAP6; -typedef union nbif_gpu_RCC_DEV0_EPF5_STRAP0 regnbif_gpu_RCC_DEV0_EPF5_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF5_STRAP13 regnbif_gpu_RCC_DEV0_EPF5_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF5_STRAP2 regnbif_gpu_RCC_DEV0_EPF5_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF5_STRAP3 regnbif_gpu_RCC_DEV0_EPF5_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF5_STRAP4 regnbif_gpu_RCC_DEV0_EPF5_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF5_STRAP5 regnbif_gpu_RCC_DEV0_EPF5_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF5_STRAP6 regnbif_gpu_RCC_DEV0_EPF5_STRAP6; -typedef union nbif_gpu_RCC_DEV0_EPF6_STRAP0 regnbif_gpu_RCC_DEV0_EPF6_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF6_STRAP13 regnbif_gpu_RCC_DEV0_EPF6_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF6_STRAP2 regnbif_gpu_RCC_DEV0_EPF6_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF6_STRAP3 regnbif_gpu_RCC_DEV0_EPF6_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF6_STRAP4 regnbif_gpu_RCC_DEV0_EPF6_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF6_STRAP5 regnbif_gpu_RCC_DEV0_EPF6_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF6_STRAP6 regnbif_gpu_RCC_DEV0_EPF6_STRAP6; -typedef union nbif_gpu_RCC_DEV0_EPF7_STRAP0 regnbif_gpu_RCC_DEV0_EPF7_STRAP0; -typedef union nbif_gpu_RCC_DEV0_EPF7_STRAP13 regnbif_gpu_RCC_DEV0_EPF7_STRAP13; -typedef union nbif_gpu_RCC_DEV0_EPF7_STRAP2 regnbif_gpu_RCC_DEV0_EPF7_STRAP2; -typedef union nbif_gpu_RCC_DEV0_EPF7_STRAP3 regnbif_gpu_RCC_DEV0_EPF7_STRAP3; -typedef union nbif_gpu_RCC_DEV0_EPF7_STRAP4 regnbif_gpu_RCC_DEV0_EPF7_STRAP4; -typedef union nbif_gpu_RCC_DEV0_EPF7_STRAP5 regnbif_gpu_RCC_DEV0_EPF7_STRAP5; -typedef union nbif_gpu_RCC_DEV0_EPF7_STRAP6 regnbif_gpu_RCC_DEV0_EPF7_STRAP6; -typedef union nbif_gpu_RCC_DEV1_EPF0_STRAP0 regnbif_gpu_RCC_DEV1_EPF0_STRAP0; -typedef union nbif_gpu_RCC_DEV1_EPF0_STRAP13 regnbif_gpu_RCC_DEV1_EPF0_STRAP13; -typedef union nbif_gpu_RCC_DEV1_EPF0_STRAP2 regnbif_gpu_RCC_DEV1_EPF0_STRAP2; -typedef union nbif_gpu_RCC_DEV1_EPF0_STRAP3 regnbif_gpu_RCC_DEV1_EPF0_STRAP3; -typedef union nbif_gpu_RCC_DEV1_EPF0_STRAP4 regnbif_gpu_RCC_DEV1_EPF0_STRAP4; -typedef union nbif_gpu_RCC_DEV1_EPF0_STRAP5 regnbif_gpu_RCC_DEV1_EPF0_STRAP5; -typedef union nbif_gpu_RCC_DEV1_EPF0_STRAP6 regnbif_gpu_RCC_DEV1_EPF0_STRAP6; -typedef union nbif_gpu_RCC_DEV1_EPF1_STRAP0 regnbif_gpu_RCC_DEV1_EPF1_STRAP0; -typedef union nbif_gpu_RCC_DEV1_EPF1_STRAP13 regnbif_gpu_RCC_DEV1_EPF1_STRAP13; -typedef union nbif_gpu_RCC_DEV1_EPF1_STRAP2 regnbif_gpu_RCC_DEV1_EPF1_STRAP2; -typedef union nbif_gpu_RCC_DEV1_EPF1_STRAP3 regnbif_gpu_RCC_DEV1_EPF1_STRAP3; -typedef union nbif_gpu_RCC_DEV1_EPF1_STRAP4 regnbif_gpu_RCC_DEV1_EPF1_STRAP4; -typedef union nbif_gpu_RCC_DEV1_EPF1_STRAP5 regnbif_gpu_RCC_DEV1_EPF1_STRAP5; -typedef union nbif_gpu_RCC_DEV1_EPF1_STRAP6 regnbif_gpu_RCC_DEV1_EPF1_STRAP6; -typedef union nbif_gpu_RCC_DEV1_EPF2_STRAP0 regnbif_gpu_RCC_DEV1_EPF2_STRAP0; -typedef union nbif_gpu_RCC_DEV1_EPF2_STRAP13 regnbif_gpu_RCC_DEV1_EPF2_STRAP13; -typedef union nbif_gpu_RCC_DEV1_EPF2_STRAP2 regnbif_gpu_RCC_DEV1_EPF2_STRAP2; -typedef union nbif_gpu_RCC_DEV1_EPF2_STRAP3 regnbif_gpu_RCC_DEV1_EPF2_STRAP3; -typedef union nbif_gpu_RCC_DEV1_EPF2_STRAP4 regnbif_gpu_RCC_DEV1_EPF2_STRAP4; -typedef union nbif_gpu_RCC_DEV1_EPF2_STRAP5 regnbif_gpu_RCC_DEV1_EPF2_STRAP5; -typedef union nbif_gpu_RCC_DEV1_EPF2_STRAP6 regnbif_gpu_RCC_DEV1_EPF2_STRAP6; -typedef union nbif_gpu_SHUB_PF_FLR_RST regnbif_gpu_SHUB_PF_FLR_RST; -typedef union nbif_gpu_SHUB_GFX_DRV_MODE1_RST regnbif_gpu_SHUB_GFX_DRV_MODE1_RST; -typedef union nbif_gpu_SHUB_LINK_RESET regnbif_gpu_SHUB_LINK_RESET; -typedef union nbif_gpu_SHUB_PF0_VF_FLR_RST regnbif_gpu_SHUB_PF0_VF_FLR_RST; -typedef union nbif_gpu_SHUB_HARD_RST_CTRL regnbif_gpu_SHUB_HARD_RST_CTRL; -typedef union nbif_gpu_SHUB_SOFT_RST_CTRL regnbif_gpu_SHUB_SOFT_RST_CTRL; -typedef union nbif_gpu_SHUB_SDP_PORT_RST regnbif_gpu_SHUB_SDP_PORT_RST; -typedef union nbif_gpu_PCIEMSIX_VECT0_ADDR_LO regnbif_gpu_PCIEMSIX_VECT0_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT1_ADDR_LO regnbif_gpu_PCIEMSIX_VECT1_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT2_ADDR_LO regnbif_gpu_PCIEMSIX_VECT2_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT3_ADDR_LO regnbif_gpu_PCIEMSIX_VECT3_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT4_ADDR_LO regnbif_gpu_PCIEMSIX_VECT4_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT5_ADDR_LO regnbif_gpu_PCIEMSIX_VECT5_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT6_ADDR_LO regnbif_gpu_PCIEMSIX_VECT6_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT7_ADDR_LO regnbif_gpu_PCIEMSIX_VECT7_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT8_ADDR_LO regnbif_gpu_PCIEMSIX_VECT8_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT9_ADDR_LO regnbif_gpu_PCIEMSIX_VECT9_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT10_ADDR_LO regnbif_gpu_PCIEMSIX_VECT10_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT11_ADDR_LO regnbif_gpu_PCIEMSIX_VECT11_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT12_ADDR_LO regnbif_gpu_PCIEMSIX_VECT12_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT13_ADDR_LO regnbif_gpu_PCIEMSIX_VECT13_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT14_ADDR_LO regnbif_gpu_PCIEMSIX_VECT14_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT15_ADDR_LO regnbif_gpu_PCIEMSIX_VECT15_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT16_ADDR_LO regnbif_gpu_PCIEMSIX_VECT16_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT17_ADDR_LO regnbif_gpu_PCIEMSIX_VECT17_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT18_ADDR_LO regnbif_gpu_PCIEMSIX_VECT18_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT19_ADDR_LO regnbif_gpu_PCIEMSIX_VECT19_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT20_ADDR_LO regnbif_gpu_PCIEMSIX_VECT20_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT21_ADDR_LO regnbif_gpu_PCIEMSIX_VECT21_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT22_ADDR_LO regnbif_gpu_PCIEMSIX_VECT22_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT23_ADDR_LO regnbif_gpu_PCIEMSIX_VECT23_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT24_ADDR_LO regnbif_gpu_PCIEMSIX_VECT24_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT25_ADDR_LO regnbif_gpu_PCIEMSIX_VECT25_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT26_ADDR_LO regnbif_gpu_PCIEMSIX_VECT26_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT27_ADDR_LO regnbif_gpu_PCIEMSIX_VECT27_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT28_ADDR_LO regnbif_gpu_PCIEMSIX_VECT28_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT29_ADDR_LO regnbif_gpu_PCIEMSIX_VECT29_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT30_ADDR_LO regnbif_gpu_PCIEMSIX_VECT30_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT31_ADDR_LO regnbif_gpu_PCIEMSIX_VECT31_ADDR_LO; -typedef union nbif_gpu_PCIEMSIX_VECT0_ADDR_HI regnbif_gpu_PCIEMSIX_VECT0_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT1_ADDR_HI regnbif_gpu_PCIEMSIX_VECT1_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT2_ADDR_HI regnbif_gpu_PCIEMSIX_VECT2_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT3_ADDR_HI regnbif_gpu_PCIEMSIX_VECT3_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT4_ADDR_HI regnbif_gpu_PCIEMSIX_VECT4_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT5_ADDR_HI regnbif_gpu_PCIEMSIX_VECT5_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT6_ADDR_HI regnbif_gpu_PCIEMSIX_VECT6_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT7_ADDR_HI regnbif_gpu_PCIEMSIX_VECT7_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT8_ADDR_HI regnbif_gpu_PCIEMSIX_VECT8_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT9_ADDR_HI regnbif_gpu_PCIEMSIX_VECT9_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT10_ADDR_HI regnbif_gpu_PCIEMSIX_VECT10_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT11_ADDR_HI regnbif_gpu_PCIEMSIX_VECT11_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT12_ADDR_HI regnbif_gpu_PCIEMSIX_VECT12_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT13_ADDR_HI regnbif_gpu_PCIEMSIX_VECT13_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT14_ADDR_HI regnbif_gpu_PCIEMSIX_VECT14_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT15_ADDR_HI regnbif_gpu_PCIEMSIX_VECT15_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT16_ADDR_HI regnbif_gpu_PCIEMSIX_VECT16_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT17_ADDR_HI regnbif_gpu_PCIEMSIX_VECT17_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT18_ADDR_HI regnbif_gpu_PCIEMSIX_VECT18_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT19_ADDR_HI regnbif_gpu_PCIEMSIX_VECT19_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT20_ADDR_HI regnbif_gpu_PCIEMSIX_VECT20_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT21_ADDR_HI regnbif_gpu_PCIEMSIX_VECT21_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT22_ADDR_HI regnbif_gpu_PCIEMSIX_VECT22_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT23_ADDR_HI regnbif_gpu_PCIEMSIX_VECT23_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT24_ADDR_HI regnbif_gpu_PCIEMSIX_VECT24_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT25_ADDR_HI regnbif_gpu_PCIEMSIX_VECT25_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT26_ADDR_HI regnbif_gpu_PCIEMSIX_VECT26_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT27_ADDR_HI regnbif_gpu_PCIEMSIX_VECT27_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT28_ADDR_HI regnbif_gpu_PCIEMSIX_VECT28_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT29_ADDR_HI regnbif_gpu_PCIEMSIX_VECT29_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT30_ADDR_HI regnbif_gpu_PCIEMSIX_VECT30_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT31_ADDR_HI regnbif_gpu_PCIEMSIX_VECT31_ADDR_HI; -typedef union nbif_gpu_PCIEMSIX_VECT0_MSG_DATA regnbif_gpu_PCIEMSIX_VECT0_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT1_MSG_DATA regnbif_gpu_PCIEMSIX_VECT1_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT2_MSG_DATA regnbif_gpu_PCIEMSIX_VECT2_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT3_MSG_DATA regnbif_gpu_PCIEMSIX_VECT3_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT4_MSG_DATA regnbif_gpu_PCIEMSIX_VECT4_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT5_MSG_DATA regnbif_gpu_PCIEMSIX_VECT5_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT6_MSG_DATA regnbif_gpu_PCIEMSIX_VECT6_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT7_MSG_DATA regnbif_gpu_PCIEMSIX_VECT7_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT8_MSG_DATA regnbif_gpu_PCIEMSIX_VECT8_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT9_MSG_DATA regnbif_gpu_PCIEMSIX_VECT9_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT10_MSG_DATA regnbif_gpu_PCIEMSIX_VECT10_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT11_MSG_DATA regnbif_gpu_PCIEMSIX_VECT11_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT12_MSG_DATA regnbif_gpu_PCIEMSIX_VECT12_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT13_MSG_DATA regnbif_gpu_PCIEMSIX_VECT13_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT14_MSG_DATA regnbif_gpu_PCIEMSIX_VECT14_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT15_MSG_DATA regnbif_gpu_PCIEMSIX_VECT15_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT16_MSG_DATA regnbif_gpu_PCIEMSIX_VECT16_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT17_MSG_DATA regnbif_gpu_PCIEMSIX_VECT17_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT18_MSG_DATA regnbif_gpu_PCIEMSIX_VECT18_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT19_MSG_DATA regnbif_gpu_PCIEMSIX_VECT19_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT20_MSG_DATA regnbif_gpu_PCIEMSIX_VECT20_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT21_MSG_DATA regnbif_gpu_PCIEMSIX_VECT21_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT22_MSG_DATA regnbif_gpu_PCIEMSIX_VECT22_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT23_MSG_DATA regnbif_gpu_PCIEMSIX_VECT23_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT24_MSG_DATA regnbif_gpu_PCIEMSIX_VECT24_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT25_MSG_DATA regnbif_gpu_PCIEMSIX_VECT25_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT26_MSG_DATA regnbif_gpu_PCIEMSIX_VECT26_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT27_MSG_DATA regnbif_gpu_PCIEMSIX_VECT27_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT28_MSG_DATA regnbif_gpu_PCIEMSIX_VECT28_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT29_MSG_DATA regnbif_gpu_PCIEMSIX_VECT29_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT30_MSG_DATA regnbif_gpu_PCIEMSIX_VECT30_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT31_MSG_DATA regnbif_gpu_PCIEMSIX_VECT31_MSG_DATA; -typedef union nbif_gpu_PCIEMSIX_VECT0_CONTROL regnbif_gpu_PCIEMSIX_VECT0_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT1_CONTROL regnbif_gpu_PCIEMSIX_VECT1_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT2_CONTROL regnbif_gpu_PCIEMSIX_VECT2_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT3_CONTROL regnbif_gpu_PCIEMSIX_VECT3_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT4_CONTROL regnbif_gpu_PCIEMSIX_VECT4_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT5_CONTROL regnbif_gpu_PCIEMSIX_VECT5_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT6_CONTROL regnbif_gpu_PCIEMSIX_VECT6_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT7_CONTROL regnbif_gpu_PCIEMSIX_VECT7_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT8_CONTROL regnbif_gpu_PCIEMSIX_VECT8_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT9_CONTROL regnbif_gpu_PCIEMSIX_VECT9_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT10_CONTROL regnbif_gpu_PCIEMSIX_VECT10_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT11_CONTROL regnbif_gpu_PCIEMSIX_VECT11_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT12_CONTROL regnbif_gpu_PCIEMSIX_VECT12_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT13_CONTROL regnbif_gpu_PCIEMSIX_VECT13_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT14_CONTROL regnbif_gpu_PCIEMSIX_VECT14_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT15_CONTROL regnbif_gpu_PCIEMSIX_VECT15_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT16_CONTROL regnbif_gpu_PCIEMSIX_VECT16_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT17_CONTROL regnbif_gpu_PCIEMSIX_VECT17_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT18_CONTROL regnbif_gpu_PCIEMSIX_VECT18_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT19_CONTROL regnbif_gpu_PCIEMSIX_VECT19_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT20_CONTROL regnbif_gpu_PCIEMSIX_VECT20_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT21_CONTROL regnbif_gpu_PCIEMSIX_VECT21_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT22_CONTROL regnbif_gpu_PCIEMSIX_VECT22_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT23_CONTROL regnbif_gpu_PCIEMSIX_VECT23_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT24_CONTROL regnbif_gpu_PCIEMSIX_VECT24_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT25_CONTROL regnbif_gpu_PCIEMSIX_VECT25_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT26_CONTROL regnbif_gpu_PCIEMSIX_VECT26_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT27_CONTROL regnbif_gpu_PCIEMSIX_VECT27_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT28_CONTROL regnbif_gpu_PCIEMSIX_VECT28_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT29_CONTROL regnbif_gpu_PCIEMSIX_VECT29_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT30_CONTROL regnbif_gpu_PCIEMSIX_VECT30_CONTROL; -typedef union nbif_gpu_PCIEMSIX_VECT31_CONTROL regnbif_gpu_PCIEMSIX_VECT31_CONTROL; -typedef union nbif_gpu_PCIEMSIX_PBA regnbif_gpu_PCIEMSIX_PBA; -typedef union nbif_gpu_RCC_PFC_LTR_CNTL regnbif_gpu_RCC_PFC_LTR_CNTL; -typedef union nbif_gpu_RCC_PFC_PME_RESTORE regnbif_gpu_RCC_PFC_PME_RESTORE; -typedef union nbif_gpu_RCC_PFC_STICKY_RESTORE_0 regnbif_gpu_RCC_PFC_STICKY_RESTORE_0; -typedef union nbif_gpu_RCC_PFC_STICKY_RESTORE_1 regnbif_gpu_RCC_PFC_STICKY_RESTORE_1; -typedef union nbif_gpu_RCC_PFC_STICKY_RESTORE_2 regnbif_gpu_RCC_PFC_STICKY_RESTORE_2; -typedef union nbif_gpu_RCC_PFC_STICKY_RESTORE_3 regnbif_gpu_RCC_PFC_STICKY_RESTORE_3; -typedef union nbif_gpu_RCC_PFC_STICKY_RESTORE_4 regnbif_gpu_RCC_PFC_STICKY_RESTORE_4; -typedef union nbif_gpu_RCC_PFC_STICKY_RESTORE_5 regnbif_gpu_RCC_PFC_STICKY_RESTORE_5; -typedef union nbif_gpu_RCC_PFC_AUXPWR_CNTL regnbif_gpu_RCC_PFC_AUXPWR_CNTL; -typedef union IH_VMID_0_LUT regIH_VMID_0_LUT; -typedef union IH_VMID_1_LUT regIH_VMID_1_LUT; -typedef union IH_VMID_2_LUT regIH_VMID_2_LUT; -typedef union IH_VMID_3_LUT regIH_VMID_3_LUT; -typedef union IH_VMID_4_LUT regIH_VMID_4_LUT; -typedef union IH_VMID_5_LUT regIH_VMID_5_LUT; -typedef union IH_VMID_6_LUT regIH_VMID_6_LUT; -typedef union IH_VMID_7_LUT regIH_VMID_7_LUT; -typedef union IH_VMID_8_LUT regIH_VMID_8_LUT; -typedef union IH_VMID_9_LUT regIH_VMID_9_LUT; -typedef union IH_VMID_10_LUT regIH_VMID_10_LUT; -typedef union IH_VMID_11_LUT regIH_VMID_11_LUT; -typedef union IH_VMID_12_LUT regIH_VMID_12_LUT; -typedef union IH_VMID_13_LUT regIH_VMID_13_LUT; -typedef union IH_VMID_14_LUT regIH_VMID_14_LUT; -typedef union IH_VMID_15_LUT regIH_VMID_15_LUT; -typedef union IH_VMID_0_LUT_MM regIH_VMID_0_LUT_MM; -typedef union IH_VMID_1_LUT_MM regIH_VMID_1_LUT_MM; -typedef union IH_VMID_2_LUT_MM regIH_VMID_2_LUT_MM; -typedef union IH_VMID_3_LUT_MM regIH_VMID_3_LUT_MM; -typedef union IH_VMID_4_LUT_MM regIH_VMID_4_LUT_MM; -typedef union IH_VMID_5_LUT_MM regIH_VMID_5_LUT_MM; -typedef union IH_VMID_6_LUT_MM regIH_VMID_6_LUT_MM; -typedef union IH_VMID_7_LUT_MM regIH_VMID_7_LUT_MM; -typedef union IH_VMID_8_LUT_MM regIH_VMID_8_LUT_MM; -typedef union IH_VMID_9_LUT_MM regIH_VMID_9_LUT_MM; -typedef union IH_VMID_10_LUT_MM regIH_VMID_10_LUT_MM; -typedef union IH_VMID_11_LUT_MM regIH_VMID_11_LUT_MM; -typedef union IH_VMID_12_LUT_MM regIH_VMID_12_LUT_MM; -typedef union IH_VMID_13_LUT_MM regIH_VMID_13_LUT_MM; -typedef union IH_VMID_14_LUT_MM regIH_VMID_14_LUT_MM; -typedef union IH_VMID_15_LUT_MM regIH_VMID_15_LUT_MM; -typedef union IH_COOKIE_0 regIH_COOKIE_0; -typedef union IH_COOKIE_1 regIH_COOKIE_1; -typedef union IH_COOKIE_2 regIH_COOKIE_2; -typedef union IH_COOKIE_3 regIH_COOKIE_3; -typedef union IH_COOKIE_4 regIH_COOKIE_4; -typedef union IH_COOKIE_5 regIH_COOKIE_5; -typedef union IH_COOKIE_6 regIH_COOKIE_6; -typedef union IH_COOKIE_7 regIH_COOKIE_7; -typedef union IH_REGISTER_LAST_PART0 regIH_REGISTER_LAST_PART0; -typedef union IH_RB_CNTL regIH_RB_CNTL; -typedef union IH_RB_BASE regIH_RB_BASE; -typedef union IH_RB_BASE_HI regIH_RB_BASE_HI; -typedef union IH_RB_RPTR regIH_RB_RPTR; -typedef union IH_RB_WPTR regIH_RB_WPTR; -typedef union IH_RB_WPTR_ADDR_HI regIH_RB_WPTR_ADDR_HI; -typedef union IH_RB_WPTR_ADDR_LO regIH_RB_WPTR_ADDR_LO; -typedef union IH_DOORBELL_RPTR regIH_DOORBELL_RPTR; -typedef union IH_RB_CNTL_RING1 regIH_RB_CNTL_RING1; -typedef union IH_RB_BASE_RING1 regIH_RB_BASE_RING1; -typedef union IH_RB_BASE_HI_RING1 regIH_RB_BASE_HI_RING1; -typedef union IH_RB_RPTR_RING1 regIH_RB_RPTR_RING1; -typedef union IH_RB_WPTR_RING1 regIH_RB_WPTR_RING1; -typedef union IH_DOORBELL_RPTR_RING1 regIH_DOORBELL_RPTR_RING1; -typedef union IH_RB_CNTL_RING2 regIH_RB_CNTL_RING2; -typedef union IH_RB_BASE_RING2 regIH_RB_BASE_RING2; -typedef union IH_RB_BASE_HI_RING2 regIH_RB_BASE_HI_RING2; -typedef union IH_RB_RPTR_RING2 regIH_RB_RPTR_RING2; -typedef union IH_RB_WPTR_RING2 regIH_RB_WPTR_RING2; -typedef union IH_DOORBELL_RPTR_RING2 regIH_DOORBELL_RPTR_RING2; -typedef union IH_VERSION regIH_VERSION; -typedef union IH_CNTL regIH_CNTL; -typedef union IH_CNTL2 regIH_CNTL2; -typedef union IH_STATUS regIH_STATUS; -typedef union IH_PERFMON_CNTL regIH_PERFMON_CNTL; -typedef union IH_PERFCOUNTER0_RESULT regIH_PERFCOUNTER0_RESULT; -typedef union IH_PERFCOUNTER1_RESULT regIH_PERFCOUNTER1_RESULT; -typedef union IH_DEBUG regIH_DEBUG; -typedef union IH_DSM_MATCH_VALUE_BIT_31_0 regIH_DSM_MATCH_VALUE_BIT_31_0; -typedef union IH_DSM_MATCH_VALUE_BIT_63_32 regIH_DSM_MATCH_VALUE_BIT_63_32; -typedef union IH_DSM_MATCH_VALUE_BIT_95_64 regIH_DSM_MATCH_VALUE_BIT_95_64; -typedef union IH_DSM_MATCH_FIELD_CONTROL regIH_DSM_MATCH_FIELD_CONTROL; -typedef union IH_DSM_MATCH_DATA_CONTROL regIH_DSM_MATCH_DATA_CONTROL; -typedef union IH_DSM_MATCH_FCN_ID regIH_DSM_MATCH_FCN_ID; -typedef union IH_LIMIT_INT_RATE_CNTL regIH_LIMIT_INT_RATE_CNTL; -typedef union IH_VF_RB_STATUS regIH_VF_RB_STATUS; -typedef union IH_VF_RB_STATUS2 regIH_VF_RB_STATUS2; -typedef union IH_VF_RB1_STATUS regIH_VF_RB1_STATUS; -typedef union IH_VF_RB1_STATUS2 regIH_VF_RB1_STATUS2; -typedef union IH_VF_RB2_STATUS regIH_VF_RB2_STATUS; -typedef union IH_VF_RB2_STATUS2 regIH_VF_RB2_STATUS2; -typedef union IH_INT_FLOOD_CNTL regIH_INT_FLOOD_CNTL; -typedef union IH_RB0_INT_FLOOD_STATUS regIH_RB0_INT_FLOOD_STATUS; -typedef union IH_RB1_INT_FLOOD_STATUS regIH_RB1_INT_FLOOD_STATUS; -typedef union IH_RB2_INT_FLOOD_STATUS regIH_RB2_INT_FLOOD_STATUS; -typedef union IH_INT_FLOOD_STATUS regIH_INT_FLOOD_STATUS; -typedef union IH_STORM_CLIENT_LIST_CNTL regIH_STORM_CLIENT_LIST_CNTL; -typedef union IH_CLK_CTRL regIH_CLK_CTRL; -typedef union IH_INT_FLAGS regIH_INT_FLAGS; -typedef union IH_LAST_INT_INFO0 regIH_LAST_INT_INFO0; -typedef union IH_LAST_INT_INFO1 regIH_LAST_INT_INFO1; -typedef union IH_LAST_INT_INFO2 regIH_LAST_INT_INFO2; -typedef union IH_SCRATCH regIH_SCRATCH; -typedef union IH_CLIENT_CREDIT_ERROR regIH_CLIENT_CREDIT_ERROR; -typedef union IH_GPU_IOV_VIOLATION_LOG regIH_GPU_IOV_VIOLATION_LOG; -typedef union IH_COOKIE_REC_VIOLATION_LOG regIH_COOKIE_REC_VIOLATION_LOG; -typedef union IH_CREDIT_STATUS regIH_CREDIT_STATUS; -typedef union IH_MMHUB_ERROR regIH_MMHUB_ERROR; -typedef union IH_DEBUG_INDEX regIH_DEBUG_INDEX; -typedef union IH_DEBUG_DATA regIH_DEBUG_DATA; -typedef union IH_REGISTER_LAST_PART2 regIH_REGISTER_LAST_PART2; -typedef union IH_ACTIVE_FCN_ID regIH_ACTIVE_FCN_ID; -typedef union IH_VIRT_RESET_REQ regIH_VIRT_RESET_REQ; -typedef union IH_CLIENT_CFG regIH_CLIENT_CFG; -typedef union IH_CLIENT_CFG_INDEX regIH_CLIENT_CFG_INDEX; -typedef union IH_CLIENT_CFG_DATA regIH_CLIENT_CFG_DATA; -typedef union IH_CID_REMAP_INDEX regIH_CID_REMAP_INDEX; -typedef union IH_CID_REMAP_DATA regIH_CID_REMAP_DATA; -typedef union IH_CHICKEN regIH_CHICKEN; -typedef union IH_MMHUB_TLVL regIH_MMHUB_TLVL; -typedef union IH_REGISTER_LAST_PART1 regIH_REGISTER_LAST_PART1; -typedef union SEM_REQ_INPUT_0 regSEM_REQ_INPUT_0; -typedef union SEM_REQ_INPUT_1 regSEM_REQ_INPUT_1; -typedef union SEM_REQ_INPUT_2 regSEM_REQ_INPUT_2; -typedef union SEM_REQ_INPUT_3 regSEM_REQ_INPUT_3; -typedef union SEM_REGISTER_LAST_PART0 regSEM_REGISTER_LAST_PART0; -typedef union SEM_CLK_CTRL regSEM_CLK_CTRL; -typedef union SEM_UTC_CREDIT regSEM_UTC_CREDIT; -typedef union SEM_UTC_CONFIG regSEM_UTC_CONFIG; -typedef union SEM_UTCL2_TRAN_EN_LUT regSEM_UTCL2_TRAN_EN_LUT; -typedef union SEM_MCIF_CONFIG regSEM_MCIF_CONFIG; -typedef union SEM_PERFMON_CNTL regSEM_PERFMON_CNTL; -typedef union SEM_PERFCOUNTER0_RESULT regSEM_PERFCOUNTER0_RESULT; -typedef union SEM_PERFCOUNTER1_RESULT regSEM_PERFCOUNTER1_RESULT; -typedef union SEM_STATUS regSEM_STATUS; -typedef union SEM_MAILBOX_CLIENTCONFIG regSEM_MAILBOX_CLIENTCONFIG; -typedef union SEM_MAILBOX regSEM_MAILBOX; -typedef union SEM_MAILBOX_CONTROL regSEM_MAILBOX_CONTROL; -typedef union SEM_CHICKEN_BITS regSEM_CHICKEN_BITS; -typedef union SEM_MAILBOX_CLIENTCONFIG_EXTRA regSEM_MAILBOX_CLIENTCONFIG_EXTRA; -typedef union SEM_GPU_IOV_VIOLATION_LOG regSEM_GPU_IOV_VIOLATION_LOG; -typedef union SEM_OUTSTANDING_THRESHOLD regSEM_OUTSTANDING_THRESHOLD; -typedef union SEM_REGISTER_LAST_PART2 regSEM_REGISTER_LAST_PART2; -typedef union SEM_ACTIVE_FCN_ID regSEM_ACTIVE_FCN_ID; -typedef union SEM_VIRT_RESET_REQ regSEM_VIRT_RESET_REQ; -typedef union SEM_RESP_SDMA0 regSEM_RESP_SDMA0; -typedef union SEM_RESP_SDMA1 regSEM_RESP_SDMA1; -typedef union SEM_RESP_UVD regSEM_RESP_UVD; -typedef union SEM_RESP_VCE_0 regSEM_RESP_VCE_0; -typedef union SEM_RESP_ACP regSEM_RESP_ACP; -typedef union SEM_RESP_ISP regSEM_RESP_ISP; -typedef union SEM_RESP_VCE_1 regSEM_RESP_VCE_1; -typedef union SEM_RESP_VP8 regSEM_RESP_VP8; -typedef union SEM_RESP_GC regSEM_RESP_GC; -typedef union SEM_CID_REMAP_INDEX regSEM_CID_REMAP_INDEX; -typedef union SEM_CID_REMAP_DATA regSEM_CID_REMAP_DATA; -typedef union SEM_ATOMIC_OP_LUT regSEM_ATOMIC_OP_LUT; -typedef union SEM_EDC_CONFIG regSEM_EDC_CONFIG; -typedef union SEM_CHICKEN_BITS2 regSEM_CHICKEN_BITS2; -typedef union SEM_MMHUB_TLVL regSEM_MMHUB_TLVL; -typedef union SEM_REGISTER_LAST_PART1 regSEM_REGISTER_LAST_PART1; -typedef union SDMA0_UCODE_ADDR regSDMA0_UCODE_ADDR; -typedef union SDMA0_UCODE_DATA regSDMA0_UCODE_DATA; -typedef union SDMA0_REGISTER_SECURITY_CNTL regSDMA0_REGISTER_SECURITY_CNTL; -typedef union SDMA0_VM_CNTL regSDMA0_VM_CNTL; -typedef union SDMA0_VM_CTX_LO regSDMA0_VM_CTX_LO; -typedef union SDMA0_VM_CTX_HI regSDMA0_VM_CTX_HI; -typedef union SDMA0_ACTIVE_FCN_ID regSDMA0_ACTIVE_FCN_ID; -typedef union SDMA0_VM_CTX_CNTL regSDMA0_VM_CTX_CNTL; -typedef union SDMA0_VIRT_RESET_REQ regSDMA0_VIRT_RESET_REQ; -typedef union SDMA0_CONTEXT_REG_TYPE0 regSDMA0_CONTEXT_REG_TYPE0; -typedef union SDMA0_CONTEXT_REG_TYPE1 regSDMA0_CONTEXT_REG_TYPE1; -typedef union SDMA0_CONTEXT_REG_TYPE2 regSDMA0_CONTEXT_REG_TYPE2; -typedef union SDMA0_CONTEXT_REG_TYPE3 regSDMA0_CONTEXT_REG_TYPE3; -typedef union SDMA0_PUB_REG_TYPE0 regSDMA0_PUB_REG_TYPE0; -typedef union SDMA0_PUB_REG_TYPE1 regSDMA0_PUB_REG_TYPE1; -typedef union SDMA0_PUB_REG_TYPE2 regSDMA0_PUB_REG_TYPE2; -typedef union SDMA0_PUB_REG_TYPE3 regSDMA0_PUB_REG_TYPE3; -typedef union SDMA0_CONTEXT_GROUP_BOUNDARY regSDMA0_CONTEXT_GROUP_BOUNDARY; -typedef union SDMA0_POWER_CNTL regSDMA0_POWER_CNTL; -typedef union SDMA0_CLK_CTRL regSDMA0_CLK_CTRL; -typedef union SDMA0_CNTL regSDMA0_CNTL; -typedef union SDMA0_CHICKEN_BITS regSDMA0_CHICKEN_BITS; -typedef union SDMA0_GB_ADDR_CONFIG regSDMA0_GB_ADDR_CONFIG; -typedef union SDMA0_GB_ADDR_CONFIG_READ regSDMA0_GB_ADDR_CONFIG_READ; -typedef union SDMA0_RB_RPTR_FETCH_HI regSDMA0_RB_RPTR_FETCH_HI; -typedef union SDMA0_SEM_WAIT_FAIL_TIMER_CNTL regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL; -typedef union SDMA0_RB_RPTR_FETCH regSDMA0_RB_RPTR_FETCH; -typedef union SDMA0_IB_OFFSET_FETCH regSDMA0_IB_OFFSET_FETCH; -typedef union SDMA0_PROGRAM regSDMA0_PROGRAM; -typedef union SDMA0_STATUS_REG regSDMA0_STATUS_REG; -typedef union SDMA0_STATUS1_REG regSDMA0_STATUS1_REG; -typedef union SDMA0_RD_BURST_CNTL regSDMA0_RD_BURST_CNTL; -typedef union SDMA0_HBM_PAGE_CONFIG regSDMA0_HBM_PAGE_CONFIG; -typedef union SDMA0_UCODE_CHECKSUM regSDMA0_UCODE_CHECKSUM; -typedef union SDMA0_F32_CNTL regSDMA0_F32_CNTL; -typedef union SDMA0_FREEZE regSDMA0_FREEZE; -typedef union SDMA0_PHASE0_QUANTUM regSDMA0_PHASE0_QUANTUM; -typedef union SDMA0_PHASE1_QUANTUM regSDMA0_PHASE1_QUANTUM; -typedef union SDMA_POWER_GATING regSDMA_POWER_GATING; -typedef union SDMA_PGFSM_CONFIG regSDMA_PGFSM_CONFIG; -typedef union SDMA_PGFSM_WRITE regSDMA_PGFSM_WRITE; -typedef union SDMA_PGFSM_READ regSDMA_PGFSM_READ; -typedef union SDMA0_EDC_CONFIG regSDMA0_EDC_CONFIG; -typedef union SDMA0_BA_THRESHOLD regSDMA0_BA_THRESHOLD; -typedef union SDMA0_ID regSDMA0_ID; -typedef union SDMA0_VERSION regSDMA0_VERSION; -typedef union SDMA0_EDC_COUNTER regSDMA0_EDC_COUNTER; -typedef union SDMA0_EDC_COUNTER_CLEAR regSDMA0_EDC_COUNTER_CLEAR; -typedef union SDMA0_STATUS2_REG regSDMA0_STATUS2_REG; -typedef union SDMA0_ATOMIC_CNTL regSDMA0_ATOMIC_CNTL; -typedef union SDMA0_ATOMIC_PREOP_LO regSDMA0_ATOMIC_PREOP_LO; -typedef union SDMA0_ATOMIC_PREOP_HI regSDMA0_ATOMIC_PREOP_HI; -typedef union SDMA0_UTCL1_CNTL regSDMA0_UTCL1_CNTL; -typedef union SDMA0_UTCL1_WATERMK regSDMA0_UTCL1_WATERMK; -typedef union SDMA0_UTCL1_RD_STATUS regSDMA0_UTCL1_RD_STATUS; -typedef union SDMA0_UTCL1_WR_STATUS regSDMA0_UTCL1_WR_STATUS; -typedef union SDMA0_UTCL1_INV0 regSDMA0_UTCL1_INV0; -typedef union SDMA0_UTCL1_INV1 regSDMA0_UTCL1_INV1; -typedef union SDMA0_UTCL1_INV2 regSDMA0_UTCL1_INV2; -typedef union SDMA0_UTCL1_RD_XNACK0 regSDMA0_UTCL1_RD_XNACK0; -typedef union SDMA0_UTCL1_RD_XNACK1 regSDMA0_UTCL1_RD_XNACK1; -typedef union SDMA0_UTCL1_WR_XNACK0 regSDMA0_UTCL1_WR_XNACK0; -typedef union SDMA0_UTCL1_WR_XNACK1 regSDMA0_UTCL1_WR_XNACK1; -typedef union SDMA0_UTCL1_TIMEOUT regSDMA0_UTCL1_TIMEOUT; -typedef union SDMA0_UTCL1_PAGE regSDMA0_UTCL1_PAGE; -typedef union SDMA0_POWER_CNTL_IDLE regSDMA0_POWER_CNTL_IDLE; -typedef union SDMA0_RELAX_ORDERING_LUT regSDMA0_RELAX_ORDERING_LUT; -typedef union SDMA0_CHICKEN_BITS_2 regSDMA0_CHICKEN_BITS_2; -typedef union SDMA0_STATUS3_REG regSDMA0_STATUS3_REG; -typedef union SDMA0_PHYSICAL_ADDR_LO regSDMA0_PHYSICAL_ADDR_LO; -typedef union SDMA0_PHYSICAL_ADDR_HI regSDMA0_PHYSICAL_ADDR_HI; -typedef union SDMA0_PHASE2_QUANTUM regSDMA0_PHASE2_QUANTUM; -typedef union SDMA0_ERROR_LOG regSDMA0_ERROR_LOG; -typedef union SDMA0_PUB_DUMMY_REG0 regSDMA0_PUB_DUMMY_REG0; -typedef union SDMA0_PUB_DUMMY_REG1 regSDMA0_PUB_DUMMY_REG1; -typedef union SDMA0_PUB_DUMMY_REG2 regSDMA0_PUB_DUMMY_REG2; -typedef union SDMA0_PUB_DUMMY_REG3 regSDMA0_PUB_DUMMY_REG3; -typedef union SDMA0_F32_COUNTER regSDMA0_F32_COUNTER; -typedef union SDMA0_UNBREAKABLE regSDMA0_UNBREAKABLE; -typedef union SDMA0_PERFMON_CNTL regSDMA0_PERFMON_CNTL; -typedef union SDMA0_PERFCOUNTER0_RESULT regSDMA0_PERFCOUNTER0_RESULT; -typedef union SDMA0_PERFCOUNTER1_RESULT regSDMA0_PERFCOUNTER1_RESULT; -typedef union SDMA0_PERFCOUNTER_TAG_DELAY_RANGE regSDMA0_PERFCOUNTER_TAG_DELAY_RANGE; -typedef union SDMA0_CRD_CNTL regSDMA0_CRD_CNTL; -typedef union SDMA0_MMHUB_TRUSTLVL regSDMA0_MMHUB_TRUSTLVL; -typedef union SDMA0_GPU_IOV_VIOLATION_LOG regSDMA0_GPU_IOV_VIOLATION_LOG; -typedef union SDMA0_ULV_CNTL regSDMA0_ULV_CNTL; -typedef union SDMA0_EA_DBIT_ADDR_DATA regSDMA0_EA_DBIT_ADDR_DATA; -typedef union SDMA0_EA_DBIT_ADDR_INDEX regSDMA0_EA_DBIT_ADDR_INDEX; -typedef union SDMA0_GFX_RB_CNTL regSDMA0_GFX_RB_CNTL; -typedef union SDMA0_GFX_RB_BASE regSDMA0_GFX_RB_BASE; -typedef union SDMA0_GFX_RB_BASE_HI regSDMA0_GFX_RB_BASE_HI; -typedef union SDMA0_GFX_RB_RPTR regSDMA0_GFX_RB_RPTR; -typedef union SDMA0_GFX_RB_RPTR_HI regSDMA0_GFX_RB_RPTR_HI; -typedef union SDMA0_GFX_RB_WPTR regSDMA0_GFX_RB_WPTR; -typedef union SDMA0_GFX_RB_WPTR_HI regSDMA0_GFX_RB_WPTR_HI; -typedef union SDMA0_GFX_RB_WPTR_POLL_CNTL regSDMA0_GFX_RB_WPTR_POLL_CNTL; -typedef union SDMA0_GFX_RB_RPTR_ADDR_HI regSDMA0_GFX_RB_RPTR_ADDR_HI; -typedef union SDMA0_GFX_RB_RPTR_ADDR_LO regSDMA0_GFX_RB_RPTR_ADDR_LO; -typedef union SDMA0_GFX_IB_CNTL regSDMA0_GFX_IB_CNTL; -typedef union SDMA0_GFX_IB_RPTR regSDMA0_GFX_IB_RPTR; -typedef union SDMA0_GFX_IB_OFFSET regSDMA0_GFX_IB_OFFSET; -typedef union SDMA0_GFX_IB_BASE_LO regSDMA0_GFX_IB_BASE_LO; -typedef union SDMA0_GFX_IB_BASE_HI regSDMA0_GFX_IB_BASE_HI; -typedef union SDMA0_GFX_IB_SIZE regSDMA0_GFX_IB_SIZE; -typedef union SDMA0_GFX_SKIP_CNTL regSDMA0_GFX_SKIP_CNTL; -typedef union SDMA0_GFX_CONTEXT_STATUS regSDMA0_GFX_CONTEXT_STATUS; -typedef union SDMA0_GFX_DOORBELL regSDMA0_GFX_DOORBELL; -typedef union SDMA0_GFX_CONTEXT_CNTL regSDMA0_GFX_CONTEXT_CNTL; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY0 regSDMA0_GFX_DRM_WRAPPEDKEY0; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY1 regSDMA0_GFX_DRM_WRAPPEDKEY1; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY2 regSDMA0_GFX_DRM_WRAPPEDKEY2; -typedef union SDMA0_GFX_DRM_WRAPPEDKEY3 regSDMA0_GFX_DRM_WRAPPEDKEY3; -typedef union SDMA0_GFX_DRM_COUNTERKEY0 regSDMA0_GFX_DRM_COUNTERKEY0; -typedef union SDMA0_GFX_DRM_COUNTERKEY1 regSDMA0_GFX_DRM_COUNTERKEY1; -typedef union SDMA0_GFX_DRM_COUNTERKEY2 regSDMA0_GFX_DRM_COUNTERKEY2; -typedef union SDMA0_GFX_DRM_COUNTERKEY3 regSDMA0_GFX_DRM_COUNTERKEY3; -typedef union SDMA0_GFX_DRM_COUNTERDATA0 regSDMA0_GFX_DRM_COUNTERDATA0; -typedef union SDMA0_GFX_DRM_COUNTERDATA1 regSDMA0_GFX_DRM_COUNTERDATA1; -typedef union SDMA0_GFX_DRM_COUNTERDATA2 regSDMA0_GFX_DRM_COUNTERDATA2; -typedef union SDMA0_GFX_DRM_COUNTERDATA3 regSDMA0_GFX_DRM_COUNTERDATA3; -typedef union SDMA0_GFX_DRM_OFFSET regSDMA0_GFX_DRM_OFFSET; -typedef union SDMA0_GFX_DRM_IVLOAD0 regSDMA0_GFX_DRM_IVLOAD0; -typedef union SDMA0_GFX_DRM_IVLOAD1 regSDMA0_GFX_DRM_IVLOAD1; -typedef union SDMA0_GFX_DRM_IVLOAD2 regSDMA0_GFX_DRM_IVLOAD2; -typedef union SDMA0_GFX_DRM_IVLOAD3 regSDMA0_GFX_DRM_IVLOAD3; -typedef union SDMA0_GFX_DRM_IVLOAD4 regSDMA0_GFX_DRM_IVLOAD4; -typedef union SDMA0_GFX_DRM_UNROLLKEY regSDMA0_GFX_DRM_UNROLLKEY; -typedef union SDMA0_GFX_AES regSDMA0_GFX_AES; -typedef union SDMA0_GFX_STATUS regSDMA0_GFX_STATUS; -typedef union SDMA0_GFX_DOORBELL_LOG regSDMA0_GFX_DOORBELL_LOG; -typedef union SDMA0_GFX_WATERMARK regSDMA0_GFX_WATERMARK; -typedef union SDMA0_GFX_DOORBELL_OFFSET regSDMA0_GFX_DOORBELL_OFFSET; -typedef union SDMA0_GFX_CSA_ADDR_LO regSDMA0_GFX_CSA_ADDR_LO; -typedef union SDMA0_GFX_CSA_ADDR_HI regSDMA0_GFX_CSA_ADDR_HI; -typedef union SDMA0_GFX_IB_SUB_REMAIN regSDMA0_GFX_IB_SUB_REMAIN; -typedef union SDMA0_GFX_PREEMPT regSDMA0_GFX_PREEMPT; -typedef union SDMA0_GFX_DUMMY_REG regSDMA0_GFX_DUMMY_REG; -typedef union SDMA0_GFX_RB_WPTR_POLL_ADDR_HI regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA0_GFX_RB_WPTR_POLL_ADDR_LO regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA0_GFX_RB_AQL_CNTL regSDMA0_GFX_RB_AQL_CNTL; -typedef union SDMA0_GFX_MINOR_PTR_UPDATE regSDMA0_GFX_MINOR_PTR_UPDATE; -typedef union SDMA0_GFX_MIDCMD_DATA0 regSDMA0_GFX_MIDCMD_DATA0; -typedef union SDMA0_GFX_MIDCMD_DATA1 regSDMA0_GFX_MIDCMD_DATA1; -typedef union SDMA0_GFX_MIDCMD_DATA2 regSDMA0_GFX_MIDCMD_DATA2; -typedef union SDMA0_GFX_MIDCMD_DATA3 regSDMA0_GFX_MIDCMD_DATA3; -typedef union SDMA0_GFX_MIDCMD_DATA4 regSDMA0_GFX_MIDCMD_DATA4; -typedef union SDMA0_GFX_MIDCMD_DATA5 regSDMA0_GFX_MIDCMD_DATA5; -typedef union SDMA0_GFX_MIDCMD_DATA6 regSDMA0_GFX_MIDCMD_DATA6; -typedef union SDMA0_GFX_MIDCMD_DATA7 regSDMA0_GFX_MIDCMD_DATA7; -typedef union SDMA0_GFX_MIDCMD_DATA8 regSDMA0_GFX_MIDCMD_DATA8; -typedef union SDMA0_GFX_MIDCMD_CNTL regSDMA0_GFX_MIDCMD_CNTL; -typedef union SDMA0_PAGE_RB_CNTL regSDMA0_PAGE_RB_CNTL; -typedef union SDMA0_PAGE_RB_BASE regSDMA0_PAGE_RB_BASE; -typedef union SDMA0_PAGE_RB_BASE_HI regSDMA0_PAGE_RB_BASE_HI; -typedef union SDMA0_PAGE_RB_RPTR regSDMA0_PAGE_RB_RPTR; -typedef union SDMA0_PAGE_RB_RPTR_HI regSDMA0_PAGE_RB_RPTR_HI; -typedef union SDMA0_PAGE_RB_WPTR regSDMA0_PAGE_RB_WPTR; -typedef union SDMA0_PAGE_RB_WPTR_HI regSDMA0_PAGE_RB_WPTR_HI; -typedef union SDMA0_PAGE_RB_WPTR_POLL_CNTL regSDMA0_PAGE_RB_WPTR_POLL_CNTL; -typedef union SDMA0_PAGE_RB_RPTR_ADDR_HI regSDMA0_PAGE_RB_RPTR_ADDR_HI; -typedef union SDMA0_PAGE_RB_RPTR_ADDR_LO regSDMA0_PAGE_RB_RPTR_ADDR_LO; -typedef union SDMA0_PAGE_IB_CNTL regSDMA0_PAGE_IB_CNTL; -typedef union SDMA0_PAGE_IB_RPTR regSDMA0_PAGE_IB_RPTR; -typedef union SDMA0_PAGE_IB_OFFSET regSDMA0_PAGE_IB_OFFSET; -typedef union SDMA0_PAGE_IB_BASE_LO regSDMA0_PAGE_IB_BASE_LO; -typedef union SDMA0_PAGE_IB_BASE_HI regSDMA0_PAGE_IB_BASE_HI; -typedef union SDMA0_PAGE_IB_SIZE regSDMA0_PAGE_IB_SIZE; -typedef union SDMA0_PAGE_SKIP_CNTL regSDMA0_PAGE_SKIP_CNTL; -typedef union SDMA0_PAGE_CONTEXT_STATUS regSDMA0_PAGE_CONTEXT_STATUS; -typedef union SDMA0_PAGE_DOORBELL regSDMA0_PAGE_DOORBELL; -typedef union SDMA0_PAGE_STATUS regSDMA0_PAGE_STATUS; -typedef union SDMA0_PAGE_DOORBELL_LOG regSDMA0_PAGE_DOORBELL_LOG; -typedef union SDMA0_PAGE_WATERMARK regSDMA0_PAGE_WATERMARK; -typedef union SDMA0_PAGE_DOORBELL_OFFSET regSDMA0_PAGE_DOORBELL_OFFSET; -typedef union SDMA0_PAGE_CSA_ADDR_LO regSDMA0_PAGE_CSA_ADDR_LO; -typedef union SDMA0_PAGE_CSA_ADDR_HI regSDMA0_PAGE_CSA_ADDR_HI; -typedef union SDMA0_PAGE_IB_SUB_REMAIN regSDMA0_PAGE_IB_SUB_REMAIN; -typedef union SDMA0_PAGE_PREEMPT regSDMA0_PAGE_PREEMPT; -typedef union SDMA0_PAGE_DUMMY_REG regSDMA0_PAGE_DUMMY_REG; -typedef union SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA0_PAGE_RB_AQL_CNTL regSDMA0_PAGE_RB_AQL_CNTL; -typedef union SDMA0_PAGE_MINOR_PTR_UPDATE regSDMA0_PAGE_MINOR_PTR_UPDATE; -typedef union SDMA0_PAGE_MIDCMD_DATA0 regSDMA0_PAGE_MIDCMD_DATA0; -typedef union SDMA0_PAGE_MIDCMD_DATA1 regSDMA0_PAGE_MIDCMD_DATA1; -typedef union SDMA0_PAGE_MIDCMD_DATA2 regSDMA0_PAGE_MIDCMD_DATA2; -typedef union SDMA0_PAGE_MIDCMD_DATA3 regSDMA0_PAGE_MIDCMD_DATA3; -typedef union SDMA0_PAGE_MIDCMD_DATA4 regSDMA0_PAGE_MIDCMD_DATA4; -typedef union SDMA0_PAGE_MIDCMD_DATA5 regSDMA0_PAGE_MIDCMD_DATA5; -typedef union SDMA0_PAGE_MIDCMD_DATA6 regSDMA0_PAGE_MIDCMD_DATA6; -typedef union SDMA0_PAGE_MIDCMD_DATA7 regSDMA0_PAGE_MIDCMD_DATA7; -typedef union SDMA0_PAGE_MIDCMD_DATA8 regSDMA0_PAGE_MIDCMD_DATA8; -typedef union SDMA0_PAGE_MIDCMD_CNTL regSDMA0_PAGE_MIDCMD_CNTL; -typedef union SDMA0_RLC0_RB_CNTL regSDMA0_RLC0_RB_CNTL; -typedef union SDMA0_RLC0_RB_BASE regSDMA0_RLC0_RB_BASE; -typedef union SDMA0_RLC0_RB_BASE_HI regSDMA0_RLC0_RB_BASE_HI; -typedef union SDMA0_RLC0_RB_RPTR regSDMA0_RLC0_RB_RPTR; -typedef union SDMA0_RLC0_RB_RPTR_HI regSDMA0_RLC0_RB_RPTR_HI; -typedef union SDMA0_RLC0_RB_WPTR regSDMA0_RLC0_RB_WPTR; -typedef union SDMA0_RLC0_RB_WPTR_HI regSDMA0_RLC0_RB_WPTR_HI; -typedef union SDMA0_RLC0_RB_WPTR_POLL_CNTL regSDMA0_RLC0_RB_WPTR_POLL_CNTL; -typedef union SDMA0_RLC0_RB_RPTR_ADDR_HI regSDMA0_RLC0_RB_RPTR_ADDR_HI; -typedef union SDMA0_RLC0_RB_RPTR_ADDR_LO regSDMA0_RLC0_RB_RPTR_ADDR_LO; -typedef union SDMA0_RLC0_IB_CNTL regSDMA0_RLC0_IB_CNTL; -typedef union SDMA0_RLC0_IB_RPTR regSDMA0_RLC0_IB_RPTR; -typedef union SDMA0_RLC0_IB_OFFSET regSDMA0_RLC0_IB_OFFSET; -typedef union SDMA0_RLC0_IB_BASE_LO regSDMA0_RLC0_IB_BASE_LO; -typedef union SDMA0_RLC0_IB_BASE_HI regSDMA0_RLC0_IB_BASE_HI; -typedef union SDMA0_RLC0_IB_SIZE regSDMA0_RLC0_IB_SIZE; -typedef union SDMA0_RLC0_SKIP_CNTL regSDMA0_RLC0_SKIP_CNTL; -typedef union SDMA0_RLC0_CONTEXT_STATUS regSDMA0_RLC0_CONTEXT_STATUS; -typedef union SDMA0_RLC0_DOORBELL regSDMA0_RLC0_DOORBELL; -typedef union SDMA0_RLC0_STATUS regSDMA0_RLC0_STATUS; -typedef union SDMA0_RLC0_DOORBELL_LOG regSDMA0_RLC0_DOORBELL_LOG; -typedef union SDMA0_RLC0_WATERMARK regSDMA0_RLC0_WATERMARK; -typedef union SDMA0_RLC0_DOORBELL_OFFSET regSDMA0_RLC0_DOORBELL_OFFSET; -typedef union SDMA0_RLC0_CSA_ADDR_LO regSDMA0_RLC0_CSA_ADDR_LO; -typedef union SDMA0_RLC0_CSA_ADDR_HI regSDMA0_RLC0_CSA_ADDR_HI; -typedef union SDMA0_RLC0_IB_SUB_REMAIN regSDMA0_RLC0_IB_SUB_REMAIN; -typedef union SDMA0_RLC0_PREEMPT regSDMA0_RLC0_PREEMPT; -typedef union SDMA0_RLC0_DUMMY_REG regSDMA0_RLC0_DUMMY_REG; -typedef union SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA0_RLC0_RB_AQL_CNTL regSDMA0_RLC0_RB_AQL_CNTL; -typedef union SDMA0_RLC0_MINOR_PTR_UPDATE regSDMA0_RLC0_MINOR_PTR_UPDATE; -typedef union SDMA0_RLC0_MIDCMD_DATA0 regSDMA0_RLC0_MIDCMD_DATA0; -typedef union SDMA0_RLC0_MIDCMD_DATA1 regSDMA0_RLC0_MIDCMD_DATA1; -typedef union SDMA0_RLC0_MIDCMD_DATA2 regSDMA0_RLC0_MIDCMD_DATA2; -typedef union SDMA0_RLC0_MIDCMD_DATA3 regSDMA0_RLC0_MIDCMD_DATA3; -typedef union SDMA0_RLC0_MIDCMD_DATA4 regSDMA0_RLC0_MIDCMD_DATA4; -typedef union SDMA0_RLC0_MIDCMD_DATA5 regSDMA0_RLC0_MIDCMD_DATA5; -typedef union SDMA0_RLC0_MIDCMD_DATA6 regSDMA0_RLC0_MIDCMD_DATA6; -typedef union SDMA0_RLC0_MIDCMD_DATA7 regSDMA0_RLC0_MIDCMD_DATA7; -typedef union SDMA0_RLC0_MIDCMD_DATA8 regSDMA0_RLC0_MIDCMD_DATA8; -typedef union SDMA0_RLC0_MIDCMD_CNTL regSDMA0_RLC0_MIDCMD_CNTL; -typedef union SDMA0_RLC1_RB_CNTL regSDMA0_RLC1_RB_CNTL; -typedef union SDMA0_RLC1_RB_BASE regSDMA0_RLC1_RB_BASE; -typedef union SDMA0_RLC1_RB_BASE_HI regSDMA0_RLC1_RB_BASE_HI; -typedef union SDMA0_RLC1_RB_RPTR regSDMA0_RLC1_RB_RPTR; -typedef union SDMA0_RLC1_RB_RPTR_HI regSDMA0_RLC1_RB_RPTR_HI; -typedef union SDMA0_RLC1_RB_WPTR regSDMA0_RLC1_RB_WPTR; -typedef union SDMA0_RLC1_RB_WPTR_HI regSDMA0_RLC1_RB_WPTR_HI; -typedef union SDMA0_RLC1_RB_WPTR_POLL_CNTL regSDMA0_RLC1_RB_WPTR_POLL_CNTL; -typedef union SDMA0_RLC1_RB_RPTR_ADDR_HI regSDMA0_RLC1_RB_RPTR_ADDR_HI; -typedef union SDMA0_RLC1_RB_RPTR_ADDR_LO regSDMA0_RLC1_RB_RPTR_ADDR_LO; -typedef union SDMA0_RLC1_IB_CNTL regSDMA0_RLC1_IB_CNTL; -typedef union SDMA0_RLC1_IB_RPTR regSDMA0_RLC1_IB_RPTR; -typedef union SDMA0_RLC1_IB_OFFSET regSDMA0_RLC1_IB_OFFSET; -typedef union SDMA0_RLC1_IB_BASE_LO regSDMA0_RLC1_IB_BASE_LO; -typedef union SDMA0_RLC1_IB_BASE_HI regSDMA0_RLC1_IB_BASE_HI; -typedef union SDMA0_RLC1_IB_SIZE regSDMA0_RLC1_IB_SIZE; -typedef union SDMA0_RLC1_SKIP_CNTL regSDMA0_RLC1_SKIP_CNTL; -typedef union SDMA0_RLC1_CONTEXT_STATUS regSDMA0_RLC1_CONTEXT_STATUS; -typedef union SDMA0_RLC1_DOORBELL regSDMA0_RLC1_DOORBELL; -typedef union SDMA0_RLC1_STATUS regSDMA0_RLC1_STATUS; -typedef union SDMA0_RLC1_DOORBELL_LOG regSDMA0_RLC1_DOORBELL_LOG; -typedef union SDMA0_RLC1_WATERMARK regSDMA0_RLC1_WATERMARK; -typedef union SDMA0_RLC1_DOORBELL_OFFSET regSDMA0_RLC1_DOORBELL_OFFSET; -typedef union SDMA0_RLC1_CSA_ADDR_LO regSDMA0_RLC1_CSA_ADDR_LO; -typedef union SDMA0_RLC1_CSA_ADDR_HI regSDMA0_RLC1_CSA_ADDR_HI; -typedef union SDMA0_RLC1_IB_SUB_REMAIN regSDMA0_RLC1_IB_SUB_REMAIN; -typedef union SDMA0_RLC1_PREEMPT regSDMA0_RLC1_PREEMPT; -typedef union SDMA0_RLC1_DUMMY_REG regSDMA0_RLC1_DUMMY_REG; -typedef union SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA0_RLC1_RB_AQL_CNTL regSDMA0_RLC1_RB_AQL_CNTL; -typedef union SDMA0_RLC1_MINOR_PTR_UPDATE regSDMA0_RLC1_MINOR_PTR_UPDATE; -typedef union SDMA0_RLC1_MIDCMD_DATA0 regSDMA0_RLC1_MIDCMD_DATA0; -typedef union SDMA0_RLC1_MIDCMD_DATA1 regSDMA0_RLC1_MIDCMD_DATA1; -typedef union SDMA0_RLC1_MIDCMD_DATA2 regSDMA0_RLC1_MIDCMD_DATA2; -typedef union SDMA0_RLC1_MIDCMD_DATA3 regSDMA0_RLC1_MIDCMD_DATA3; -typedef union SDMA0_RLC1_MIDCMD_DATA4 regSDMA0_RLC1_MIDCMD_DATA4; -typedef union SDMA0_RLC1_MIDCMD_DATA5 regSDMA0_RLC1_MIDCMD_DATA5; -typedef union SDMA0_RLC1_MIDCMD_DATA6 regSDMA0_RLC1_MIDCMD_DATA6; -typedef union SDMA0_RLC1_MIDCMD_DATA7 regSDMA0_RLC1_MIDCMD_DATA7; -typedef union SDMA0_RLC1_MIDCMD_DATA8 regSDMA0_RLC1_MIDCMD_DATA8; -typedef union SDMA0_RLC1_MIDCMD_CNTL regSDMA0_RLC1_MIDCMD_CNTL; -typedef union SDMA1_UCODE_ADDR regSDMA1_UCODE_ADDR; -typedef union SDMA1_UCODE_DATA regSDMA1_UCODE_DATA; -typedef union SDMA1_REGISTER_SECURITY_CNTL regSDMA1_REGISTER_SECURITY_CNTL; -typedef union SDMA1_VM_CNTL regSDMA1_VM_CNTL; -typedef union SDMA1_VM_CTX_LO regSDMA1_VM_CTX_LO; -typedef union SDMA1_VM_CTX_HI regSDMA1_VM_CTX_HI; -typedef union SDMA1_ACTIVE_FCN_ID regSDMA1_ACTIVE_FCN_ID; -typedef union SDMA1_VM_CTX_CNTL regSDMA1_VM_CTX_CNTL; -typedef union SDMA1_VIRT_RESET_REQ regSDMA1_VIRT_RESET_REQ; -typedef union SDMA1_CONTEXT_REG_TYPE0 regSDMA1_CONTEXT_REG_TYPE0; -typedef union SDMA1_CONTEXT_REG_TYPE1 regSDMA1_CONTEXT_REG_TYPE1; -typedef union SDMA1_CONTEXT_REG_TYPE2 regSDMA1_CONTEXT_REG_TYPE2; -typedef union SDMA1_CONTEXT_REG_TYPE3 regSDMA1_CONTEXT_REG_TYPE3; -typedef union SDMA1_PUB_REG_TYPE0 regSDMA1_PUB_REG_TYPE0; -typedef union SDMA1_PUB_REG_TYPE1 regSDMA1_PUB_REG_TYPE1; -typedef union SDMA1_PUB_REG_TYPE2 regSDMA1_PUB_REG_TYPE2; -typedef union SDMA1_PUB_REG_TYPE3 regSDMA1_PUB_REG_TYPE3; -typedef union SDMA1_CONTEXT_GROUP_BOUNDARY regSDMA1_CONTEXT_GROUP_BOUNDARY; -typedef union SDMA1_POWER_CNTL regSDMA1_POWER_CNTL; -typedef union SDMA1_CLK_CTRL regSDMA1_CLK_CTRL; -typedef union SDMA1_CNTL regSDMA1_CNTL; -typedef union SDMA1_CHICKEN_BITS regSDMA1_CHICKEN_BITS; -typedef union SDMA1_GB_ADDR_CONFIG regSDMA1_GB_ADDR_CONFIG; -typedef union SDMA1_GB_ADDR_CONFIG_READ regSDMA1_GB_ADDR_CONFIG_READ; -typedef union SDMA1_RB_RPTR_FETCH_HI regSDMA1_RB_RPTR_FETCH_HI; -typedef union SDMA1_SEM_WAIT_FAIL_TIMER_CNTL regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL; -typedef union SDMA1_RB_RPTR_FETCH regSDMA1_RB_RPTR_FETCH; -typedef union SDMA1_IB_OFFSET_FETCH regSDMA1_IB_OFFSET_FETCH; -typedef union SDMA1_PROGRAM regSDMA1_PROGRAM; -typedef union SDMA1_STATUS_REG regSDMA1_STATUS_REG; -typedef union SDMA1_STATUS1_REG regSDMA1_STATUS1_REG; -typedef union SDMA1_RD_BURST_CNTL regSDMA1_RD_BURST_CNTL; -typedef union SDMA1_HBM_PAGE_CONFIG regSDMA1_HBM_PAGE_CONFIG; -typedef union SDMA1_UCODE_CHECKSUM regSDMA1_UCODE_CHECKSUM; -typedef union SDMA1_F32_CNTL regSDMA1_F32_CNTL; -typedef union SDMA1_FREEZE regSDMA1_FREEZE; -typedef union SDMA1_PHASE0_QUANTUM regSDMA1_PHASE0_QUANTUM; -typedef union SDMA1_PHASE1_QUANTUM regSDMA1_PHASE1_QUANTUM; -typedef union SDMA1_EDC_CONFIG regSDMA1_EDC_CONFIG; -typedef union SDMA1_BA_THRESHOLD regSDMA1_BA_THRESHOLD; -typedef union SDMA1_ID regSDMA1_ID; -typedef union SDMA1_VERSION regSDMA1_VERSION; -typedef union SDMA1_EDC_COUNTER regSDMA1_EDC_COUNTER; -typedef union SDMA1_EDC_COUNTER_CLEAR regSDMA1_EDC_COUNTER_CLEAR; -typedef union SDMA1_STATUS2_REG regSDMA1_STATUS2_REG; -typedef union SDMA1_ATOMIC_CNTL regSDMA1_ATOMIC_CNTL; -typedef union SDMA1_ATOMIC_PREOP_LO regSDMA1_ATOMIC_PREOP_LO; -typedef union SDMA1_ATOMIC_PREOP_HI regSDMA1_ATOMIC_PREOP_HI; -typedef union SDMA1_UTCL1_CNTL regSDMA1_UTCL1_CNTL; -typedef union SDMA1_UTCL1_WATERMK regSDMA1_UTCL1_WATERMK; -typedef union SDMA1_UTCL1_RD_STATUS regSDMA1_UTCL1_RD_STATUS; -typedef union SDMA1_UTCL1_WR_STATUS regSDMA1_UTCL1_WR_STATUS; -typedef union SDMA1_UTCL1_INV0 regSDMA1_UTCL1_INV0; -typedef union SDMA1_UTCL1_INV1 regSDMA1_UTCL1_INV1; -typedef union SDMA1_UTCL1_INV2 regSDMA1_UTCL1_INV2; -typedef union SDMA1_UTCL1_RD_XNACK0 regSDMA1_UTCL1_RD_XNACK0; -typedef union SDMA1_UTCL1_RD_XNACK1 regSDMA1_UTCL1_RD_XNACK1; -typedef union SDMA1_UTCL1_WR_XNACK0 regSDMA1_UTCL1_WR_XNACK0; -typedef union SDMA1_UTCL1_WR_XNACK1 regSDMA1_UTCL1_WR_XNACK1; -typedef union SDMA1_UTCL1_TIMEOUT regSDMA1_UTCL1_TIMEOUT; -typedef union SDMA1_UTCL1_PAGE regSDMA1_UTCL1_PAGE; -typedef union SDMA1_POWER_CNTL_IDLE regSDMA1_POWER_CNTL_IDLE; -typedef union SDMA1_RELAX_ORDERING_LUT regSDMA1_RELAX_ORDERING_LUT; -typedef union SDMA1_CHICKEN_BITS_2 regSDMA1_CHICKEN_BITS_2; -typedef union SDMA1_STATUS3_REG regSDMA1_STATUS3_REG; -typedef union SDMA1_PHYSICAL_ADDR_LO regSDMA1_PHYSICAL_ADDR_LO; -typedef union SDMA1_PHYSICAL_ADDR_HI regSDMA1_PHYSICAL_ADDR_HI; -typedef union SDMA1_PHASE2_QUANTUM regSDMA1_PHASE2_QUANTUM; -typedef union SDMA1_ERROR_LOG regSDMA1_ERROR_LOG; -typedef union SDMA1_PUB_DUMMY_REG0 regSDMA1_PUB_DUMMY_REG0; -typedef union SDMA1_PUB_DUMMY_REG1 regSDMA1_PUB_DUMMY_REG1; -typedef union SDMA1_PUB_DUMMY_REG2 regSDMA1_PUB_DUMMY_REG2; -typedef union SDMA1_PUB_DUMMY_REG3 regSDMA1_PUB_DUMMY_REG3; -typedef union SDMA1_F32_COUNTER regSDMA1_F32_COUNTER; -typedef union SDMA1_UNBREAKABLE regSDMA1_UNBREAKABLE; -typedef union SDMA1_PERFMON_CNTL regSDMA1_PERFMON_CNTL; -typedef union SDMA1_PERFCOUNTER0_RESULT regSDMA1_PERFCOUNTER0_RESULT; -typedef union SDMA1_PERFCOUNTER1_RESULT regSDMA1_PERFCOUNTER1_RESULT; -typedef union SDMA1_PERFCOUNTER_TAG_DELAY_RANGE regSDMA1_PERFCOUNTER_TAG_DELAY_RANGE; -typedef union SDMA1_CRD_CNTL regSDMA1_CRD_CNTL; -typedef union SDMA1_MMHUB_TRUSTLVL regSDMA1_MMHUB_TRUSTLVL; -typedef union SDMA1_GPU_IOV_VIOLATION_LOG regSDMA1_GPU_IOV_VIOLATION_LOG; -typedef union SDMA1_ULV_CNTL regSDMA1_ULV_CNTL; -typedef union SDMA1_EA_DBIT_ADDR_DATA regSDMA1_EA_DBIT_ADDR_DATA; -typedef union SDMA1_EA_DBIT_ADDR_INDEX regSDMA1_EA_DBIT_ADDR_INDEX; -typedef union SDMA1_GFX_RB_CNTL regSDMA1_GFX_RB_CNTL; -typedef union SDMA1_GFX_RB_BASE regSDMA1_GFX_RB_BASE; -typedef union SDMA1_GFX_RB_BASE_HI regSDMA1_GFX_RB_BASE_HI; -typedef union SDMA1_GFX_RB_RPTR regSDMA1_GFX_RB_RPTR; -typedef union SDMA1_GFX_RB_RPTR_HI regSDMA1_GFX_RB_RPTR_HI; -typedef union SDMA1_GFX_RB_WPTR regSDMA1_GFX_RB_WPTR; -typedef union SDMA1_GFX_RB_WPTR_HI regSDMA1_GFX_RB_WPTR_HI; -typedef union SDMA1_GFX_RB_WPTR_POLL_CNTL regSDMA1_GFX_RB_WPTR_POLL_CNTL; -typedef union SDMA1_GFX_RB_RPTR_ADDR_HI regSDMA1_GFX_RB_RPTR_ADDR_HI; -typedef union SDMA1_GFX_RB_RPTR_ADDR_LO regSDMA1_GFX_RB_RPTR_ADDR_LO; -typedef union SDMA1_GFX_IB_CNTL regSDMA1_GFX_IB_CNTL; -typedef union SDMA1_GFX_IB_RPTR regSDMA1_GFX_IB_RPTR; -typedef union SDMA1_GFX_IB_OFFSET regSDMA1_GFX_IB_OFFSET; -typedef union SDMA1_GFX_IB_BASE_LO regSDMA1_GFX_IB_BASE_LO; -typedef union SDMA1_GFX_IB_BASE_HI regSDMA1_GFX_IB_BASE_HI; -typedef union SDMA1_GFX_IB_SIZE regSDMA1_GFX_IB_SIZE; -typedef union SDMA1_GFX_SKIP_CNTL regSDMA1_GFX_SKIP_CNTL; -typedef union SDMA1_GFX_CONTEXT_STATUS regSDMA1_GFX_CONTEXT_STATUS; -typedef union SDMA1_GFX_DOORBELL regSDMA1_GFX_DOORBELL; -typedef union SDMA1_GFX_CONTEXT_CNTL regSDMA1_GFX_CONTEXT_CNTL; -typedef union SDMA1_GFX_AES regSDMA1_GFX_AES; -typedef union SDMA1_GFX_STATUS regSDMA1_GFX_STATUS; -typedef union SDMA1_GFX_DOORBELL_LOG regSDMA1_GFX_DOORBELL_LOG; -typedef union SDMA1_GFX_WATERMARK regSDMA1_GFX_WATERMARK; -typedef union SDMA1_GFX_DOORBELL_OFFSET regSDMA1_GFX_DOORBELL_OFFSET; -typedef union SDMA1_GFX_CSA_ADDR_LO regSDMA1_GFX_CSA_ADDR_LO; -typedef union SDMA1_GFX_CSA_ADDR_HI regSDMA1_GFX_CSA_ADDR_HI; -typedef union SDMA1_GFX_IB_SUB_REMAIN regSDMA1_GFX_IB_SUB_REMAIN; -typedef union SDMA1_GFX_PREEMPT regSDMA1_GFX_PREEMPT; -typedef union SDMA1_GFX_DUMMY_REG regSDMA1_GFX_DUMMY_REG; -typedef union SDMA1_GFX_RB_WPTR_POLL_ADDR_HI regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA1_GFX_RB_WPTR_POLL_ADDR_LO regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA1_GFX_RB_AQL_CNTL regSDMA1_GFX_RB_AQL_CNTL; -typedef union SDMA1_GFX_MINOR_PTR_UPDATE regSDMA1_GFX_MINOR_PTR_UPDATE; -typedef union SDMA1_GFX_MIDCMD_DATA0 regSDMA1_GFX_MIDCMD_DATA0; -typedef union SDMA1_GFX_MIDCMD_DATA1 regSDMA1_GFX_MIDCMD_DATA1; -typedef union SDMA1_GFX_MIDCMD_DATA2 regSDMA1_GFX_MIDCMD_DATA2; -typedef union SDMA1_GFX_MIDCMD_DATA3 regSDMA1_GFX_MIDCMD_DATA3; -typedef union SDMA1_GFX_MIDCMD_DATA4 regSDMA1_GFX_MIDCMD_DATA4; -typedef union SDMA1_GFX_MIDCMD_DATA5 regSDMA1_GFX_MIDCMD_DATA5; -typedef union SDMA1_GFX_MIDCMD_DATA6 regSDMA1_GFX_MIDCMD_DATA6; -typedef union SDMA1_GFX_MIDCMD_DATA7 regSDMA1_GFX_MIDCMD_DATA7; -typedef union SDMA1_GFX_MIDCMD_DATA8 regSDMA1_GFX_MIDCMD_DATA8; -typedef union SDMA1_GFX_MIDCMD_CNTL regSDMA1_GFX_MIDCMD_CNTL; -typedef union SDMA1_PAGE_RB_CNTL regSDMA1_PAGE_RB_CNTL; -typedef union SDMA1_PAGE_RB_BASE regSDMA1_PAGE_RB_BASE; -typedef union SDMA1_PAGE_RB_BASE_HI regSDMA1_PAGE_RB_BASE_HI; -typedef union SDMA1_PAGE_RB_RPTR regSDMA1_PAGE_RB_RPTR; -typedef union SDMA1_PAGE_RB_RPTR_HI regSDMA1_PAGE_RB_RPTR_HI; -typedef union SDMA1_PAGE_RB_WPTR regSDMA1_PAGE_RB_WPTR; -typedef union SDMA1_PAGE_RB_WPTR_HI regSDMA1_PAGE_RB_WPTR_HI; -typedef union SDMA1_PAGE_RB_WPTR_POLL_CNTL regSDMA1_PAGE_RB_WPTR_POLL_CNTL; -typedef union SDMA1_PAGE_RB_RPTR_ADDR_HI regSDMA1_PAGE_RB_RPTR_ADDR_HI; -typedef union SDMA1_PAGE_RB_RPTR_ADDR_LO regSDMA1_PAGE_RB_RPTR_ADDR_LO; -typedef union SDMA1_PAGE_IB_CNTL regSDMA1_PAGE_IB_CNTL; -typedef union SDMA1_PAGE_IB_RPTR regSDMA1_PAGE_IB_RPTR; -typedef union SDMA1_PAGE_IB_OFFSET regSDMA1_PAGE_IB_OFFSET; -typedef union SDMA1_PAGE_IB_BASE_LO regSDMA1_PAGE_IB_BASE_LO; -typedef union SDMA1_PAGE_IB_BASE_HI regSDMA1_PAGE_IB_BASE_HI; -typedef union SDMA1_PAGE_IB_SIZE regSDMA1_PAGE_IB_SIZE; -typedef union SDMA1_PAGE_SKIP_CNTL regSDMA1_PAGE_SKIP_CNTL; -typedef union SDMA1_PAGE_CONTEXT_STATUS regSDMA1_PAGE_CONTEXT_STATUS; -typedef union SDMA1_PAGE_DOORBELL regSDMA1_PAGE_DOORBELL; -typedef union SDMA1_PAGE_STATUS regSDMA1_PAGE_STATUS; -typedef union SDMA1_PAGE_DOORBELL_LOG regSDMA1_PAGE_DOORBELL_LOG; -typedef union SDMA1_PAGE_WATERMARK regSDMA1_PAGE_WATERMARK; -typedef union SDMA1_PAGE_DOORBELL_OFFSET regSDMA1_PAGE_DOORBELL_OFFSET; -typedef union SDMA1_PAGE_CSA_ADDR_LO regSDMA1_PAGE_CSA_ADDR_LO; -typedef union SDMA1_PAGE_CSA_ADDR_HI regSDMA1_PAGE_CSA_ADDR_HI; -typedef union SDMA1_PAGE_IB_SUB_REMAIN regSDMA1_PAGE_IB_SUB_REMAIN; -typedef union SDMA1_PAGE_PREEMPT regSDMA1_PAGE_PREEMPT; -typedef union SDMA1_PAGE_DUMMY_REG regSDMA1_PAGE_DUMMY_REG; -typedef union SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA1_PAGE_RB_AQL_CNTL regSDMA1_PAGE_RB_AQL_CNTL; -typedef union SDMA1_PAGE_MINOR_PTR_UPDATE regSDMA1_PAGE_MINOR_PTR_UPDATE; -typedef union SDMA1_PAGE_MIDCMD_DATA0 regSDMA1_PAGE_MIDCMD_DATA0; -typedef union SDMA1_PAGE_MIDCMD_DATA1 regSDMA1_PAGE_MIDCMD_DATA1; -typedef union SDMA1_PAGE_MIDCMD_DATA2 regSDMA1_PAGE_MIDCMD_DATA2; -typedef union SDMA1_PAGE_MIDCMD_DATA3 regSDMA1_PAGE_MIDCMD_DATA3; -typedef union SDMA1_PAGE_MIDCMD_DATA4 regSDMA1_PAGE_MIDCMD_DATA4; -typedef union SDMA1_PAGE_MIDCMD_DATA5 regSDMA1_PAGE_MIDCMD_DATA5; -typedef union SDMA1_PAGE_MIDCMD_DATA6 regSDMA1_PAGE_MIDCMD_DATA6; -typedef union SDMA1_PAGE_MIDCMD_DATA7 regSDMA1_PAGE_MIDCMD_DATA7; -typedef union SDMA1_PAGE_MIDCMD_DATA8 regSDMA1_PAGE_MIDCMD_DATA8; -typedef union SDMA1_PAGE_MIDCMD_CNTL regSDMA1_PAGE_MIDCMD_CNTL; -typedef union SDMA1_RLC0_RB_CNTL regSDMA1_RLC0_RB_CNTL; -typedef union SDMA1_RLC0_RB_BASE regSDMA1_RLC0_RB_BASE; -typedef union SDMA1_RLC0_RB_BASE_HI regSDMA1_RLC0_RB_BASE_HI; -typedef union SDMA1_RLC0_RB_RPTR regSDMA1_RLC0_RB_RPTR; -typedef union SDMA1_RLC0_RB_RPTR_HI regSDMA1_RLC0_RB_RPTR_HI; -typedef union SDMA1_RLC0_RB_WPTR regSDMA1_RLC0_RB_WPTR; -typedef union SDMA1_RLC0_RB_WPTR_HI regSDMA1_RLC0_RB_WPTR_HI; -typedef union SDMA1_RLC0_RB_WPTR_POLL_CNTL regSDMA1_RLC0_RB_WPTR_POLL_CNTL; -typedef union SDMA1_RLC0_RB_RPTR_ADDR_HI regSDMA1_RLC0_RB_RPTR_ADDR_HI; -typedef union SDMA1_RLC0_RB_RPTR_ADDR_LO regSDMA1_RLC0_RB_RPTR_ADDR_LO; -typedef union SDMA1_RLC0_IB_CNTL regSDMA1_RLC0_IB_CNTL; -typedef union SDMA1_RLC0_IB_RPTR regSDMA1_RLC0_IB_RPTR; -typedef union SDMA1_RLC0_IB_OFFSET regSDMA1_RLC0_IB_OFFSET; -typedef union SDMA1_RLC0_IB_BASE_LO regSDMA1_RLC0_IB_BASE_LO; -typedef union SDMA1_RLC0_IB_BASE_HI regSDMA1_RLC0_IB_BASE_HI; -typedef union SDMA1_RLC0_IB_SIZE regSDMA1_RLC0_IB_SIZE; -typedef union SDMA1_RLC0_SKIP_CNTL regSDMA1_RLC0_SKIP_CNTL; -typedef union SDMA1_RLC0_CONTEXT_STATUS regSDMA1_RLC0_CONTEXT_STATUS; -typedef union SDMA1_RLC0_DOORBELL regSDMA1_RLC0_DOORBELL; -typedef union SDMA1_RLC0_STATUS regSDMA1_RLC0_STATUS; -typedef union SDMA1_RLC0_DOORBELL_LOG regSDMA1_RLC0_DOORBELL_LOG; -typedef union SDMA1_RLC0_WATERMARK regSDMA1_RLC0_WATERMARK; -typedef union SDMA1_RLC0_DOORBELL_OFFSET regSDMA1_RLC0_DOORBELL_OFFSET; -typedef union SDMA1_RLC0_CSA_ADDR_LO regSDMA1_RLC0_CSA_ADDR_LO; -typedef union SDMA1_RLC0_CSA_ADDR_HI regSDMA1_RLC0_CSA_ADDR_HI; -typedef union SDMA1_RLC0_IB_SUB_REMAIN regSDMA1_RLC0_IB_SUB_REMAIN; -typedef union SDMA1_RLC0_PREEMPT regSDMA1_RLC0_PREEMPT; -typedef union SDMA1_RLC0_DUMMY_REG regSDMA1_RLC0_DUMMY_REG; -typedef union SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA1_RLC0_RB_AQL_CNTL regSDMA1_RLC0_RB_AQL_CNTL; -typedef union SDMA1_RLC0_MINOR_PTR_UPDATE regSDMA1_RLC0_MINOR_PTR_UPDATE; -typedef union SDMA1_RLC0_MIDCMD_DATA0 regSDMA1_RLC0_MIDCMD_DATA0; -typedef union SDMA1_RLC0_MIDCMD_DATA1 regSDMA1_RLC0_MIDCMD_DATA1; -typedef union SDMA1_RLC0_MIDCMD_DATA2 regSDMA1_RLC0_MIDCMD_DATA2; -typedef union SDMA1_RLC0_MIDCMD_DATA3 regSDMA1_RLC0_MIDCMD_DATA3; -typedef union SDMA1_RLC0_MIDCMD_DATA4 regSDMA1_RLC0_MIDCMD_DATA4; -typedef union SDMA1_RLC0_MIDCMD_DATA5 regSDMA1_RLC0_MIDCMD_DATA5; -typedef union SDMA1_RLC0_MIDCMD_DATA6 regSDMA1_RLC0_MIDCMD_DATA6; -typedef union SDMA1_RLC0_MIDCMD_DATA7 regSDMA1_RLC0_MIDCMD_DATA7; -typedef union SDMA1_RLC0_MIDCMD_DATA8 regSDMA1_RLC0_MIDCMD_DATA8; -typedef union SDMA1_RLC0_MIDCMD_CNTL regSDMA1_RLC0_MIDCMD_CNTL; -typedef union SDMA1_RLC1_RB_CNTL regSDMA1_RLC1_RB_CNTL; -typedef union SDMA1_RLC1_RB_BASE regSDMA1_RLC1_RB_BASE; -typedef union SDMA1_RLC1_RB_BASE_HI regSDMA1_RLC1_RB_BASE_HI; -typedef union SDMA1_RLC1_RB_RPTR regSDMA1_RLC1_RB_RPTR; -typedef union SDMA1_RLC1_RB_RPTR_HI regSDMA1_RLC1_RB_RPTR_HI; -typedef union SDMA1_RLC1_RB_WPTR regSDMA1_RLC1_RB_WPTR; -typedef union SDMA1_RLC1_RB_WPTR_HI regSDMA1_RLC1_RB_WPTR_HI; -typedef union SDMA1_RLC1_RB_WPTR_POLL_CNTL regSDMA1_RLC1_RB_WPTR_POLL_CNTL; -typedef union SDMA1_RLC1_RB_RPTR_ADDR_HI regSDMA1_RLC1_RB_RPTR_ADDR_HI; -typedef union SDMA1_RLC1_RB_RPTR_ADDR_LO regSDMA1_RLC1_RB_RPTR_ADDR_LO; -typedef union SDMA1_RLC1_IB_CNTL regSDMA1_RLC1_IB_CNTL; -typedef union SDMA1_RLC1_IB_RPTR regSDMA1_RLC1_IB_RPTR; -typedef union SDMA1_RLC1_IB_OFFSET regSDMA1_RLC1_IB_OFFSET; -typedef union SDMA1_RLC1_IB_BASE_LO regSDMA1_RLC1_IB_BASE_LO; -typedef union SDMA1_RLC1_IB_BASE_HI regSDMA1_RLC1_IB_BASE_HI; -typedef union SDMA1_RLC1_IB_SIZE regSDMA1_RLC1_IB_SIZE; -typedef union SDMA1_RLC1_SKIP_CNTL regSDMA1_RLC1_SKIP_CNTL; -typedef union SDMA1_RLC1_CONTEXT_STATUS regSDMA1_RLC1_CONTEXT_STATUS; -typedef union SDMA1_RLC1_DOORBELL regSDMA1_RLC1_DOORBELL; -typedef union SDMA1_RLC1_STATUS regSDMA1_RLC1_STATUS; -typedef union SDMA1_RLC1_DOORBELL_LOG regSDMA1_RLC1_DOORBELL_LOG; -typedef union SDMA1_RLC1_WATERMARK regSDMA1_RLC1_WATERMARK; -typedef union SDMA1_RLC1_DOORBELL_OFFSET regSDMA1_RLC1_DOORBELL_OFFSET; -typedef union SDMA1_RLC1_CSA_ADDR_LO regSDMA1_RLC1_CSA_ADDR_LO; -typedef union SDMA1_RLC1_CSA_ADDR_HI regSDMA1_RLC1_CSA_ADDR_HI; -typedef union SDMA1_RLC1_IB_SUB_REMAIN regSDMA1_RLC1_IB_SUB_REMAIN; -typedef union SDMA1_RLC1_PREEMPT regSDMA1_RLC1_PREEMPT; -typedef union SDMA1_RLC1_DUMMY_REG regSDMA1_RLC1_DUMMY_REG; -typedef union SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI; -typedef union SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO; -typedef union SDMA1_RLC1_RB_AQL_CNTL regSDMA1_RLC1_RB_AQL_CNTL; -typedef union SDMA1_RLC1_MINOR_PTR_UPDATE regSDMA1_RLC1_MINOR_PTR_UPDATE; -typedef union SDMA1_RLC1_MIDCMD_DATA0 regSDMA1_RLC1_MIDCMD_DATA0; -typedef union SDMA1_RLC1_MIDCMD_DATA1 regSDMA1_RLC1_MIDCMD_DATA1; -typedef union SDMA1_RLC1_MIDCMD_DATA2 regSDMA1_RLC1_MIDCMD_DATA2; -typedef union SDMA1_RLC1_MIDCMD_DATA3 regSDMA1_RLC1_MIDCMD_DATA3; -typedef union SDMA1_RLC1_MIDCMD_DATA4 regSDMA1_RLC1_MIDCMD_DATA4; -typedef union SDMA1_RLC1_MIDCMD_DATA5 regSDMA1_RLC1_MIDCMD_DATA5; -typedef union SDMA1_RLC1_MIDCMD_DATA6 regSDMA1_RLC1_MIDCMD_DATA6; -typedef union SDMA1_RLC1_MIDCMD_DATA7 regSDMA1_RLC1_MIDCMD_DATA7; -typedef union SDMA1_RLC1_MIDCMD_DATA8 regSDMA1_RLC1_MIDCMD_DATA8; -typedef union SDMA1_RLC1_MIDCMD_CNTL regSDMA1_RLC1_MIDCMD_CNTL; -typedef union MP0_SMNIF_ERROR regMP0_SMNIF_ERROR; -typedef union MP0_SFUSE_PUB regMP0_SFUSE_PUB; -typedef union MP0_FW_DEBUG_CNT0 regMP0_FW_DEBUG_CNT0; -typedef union MP0_FW_DEBUG_CNT1 regMP0_FW_DEBUG_CNT1; -typedef union MP0_FW_DEBUG_CNT2 regMP0_FW_DEBUG_CNT2; -typedef union MP0_FW_DEBUG_CNT3 regMP0_FW_DEBUG_CNT3; -typedef union MP0_FW_DEBUG_SIGNAL0 regMP0_FW_DEBUG_SIGNAL0; -typedef union MP0_FW_DEBUG_SIGNAL1 regMP0_FW_DEBUG_SIGNAL1; -typedef union MP0_DSM_ENABLE regMP0_DSM_ENABLE; -typedef union MP0_SOC_INFO regMP0_SOC_INFO; -typedef union MP0_MUTEX_0 regMP0_MUTEX_0; -typedef union MP0_MUTEX_1 regMP0_MUTEX_1; -typedef union MP0_MUTEX_2 regMP0_MUTEX_2; -typedef union MP0_MUTEX_3 regMP0_MUTEX_3; -typedef union MP0_PUB_SCRATCH0 regMP0_PUB_SCRATCH0; -typedef union MP0_PUB_SCRATCH1 regMP0_PUB_SCRATCH1; -typedef union MP0_PUB_SCRATCH2 regMP0_PUB_SCRATCH2; -typedef union MP0_PUB_SCRATCH3 regMP0_PUB_SCRATCH3; -typedef union MP0_RSMU_SECINTR regMP0_RSMU_SECINTR; -typedef union MP0_FW_INTF regMP0_FW_INTF; -typedef union MP0_FW_CHRONO_LO regMP0_FW_CHRONO_LO; -typedef union MP0_FW_CHRONO_HI regMP0_FW_CHRONO_HI; -typedef union MP0_PIC0_MASK_0 regMP0_PIC0_MASK_0; -typedef union MP0_PIC0_MASK_1 regMP0_PIC0_MASK_1; -typedef union MP0_PIC0_MASK_2 regMP0_PIC0_MASK_2; -typedef union MP0_PIC0_MASK_3 regMP0_PIC0_MASK_3; -typedef union MP0_PIC0_STATUS_0 regMP0_PIC0_STATUS_0; -typedef union MP0_PIC0_STATUS_1 regMP0_PIC0_STATUS_1; -typedef union MP0_PIC0_STATUS_2 regMP0_PIC0_STATUS_2; -typedef union MP0_PIC0_STATUS_3 regMP0_PIC0_STATUS_3; -typedef union MP0_PIC0_INTR regMP0_PIC0_INTR; -typedef union MP0_PIC0_ID regMP0_PIC0_ID; -typedef union MP0_PIC1_MASK_0 regMP0_PIC1_MASK_0; -typedef union MP0_PIC1_MASK_1 regMP0_PIC1_MASK_1; -typedef union MP0_PIC1_MASK_2 regMP0_PIC1_MASK_2; -typedef union MP0_PIC1_MASK_3 regMP0_PIC1_MASK_3; -typedef union MP0_PIC1_STATUS_0 regMP0_PIC1_STATUS_0; -typedef union MP0_PIC1_STATUS_1 regMP0_PIC1_STATUS_1; -typedef union MP0_PIC1_STATUS_2 regMP0_PIC1_STATUS_2; -typedef union MP0_PIC1_STATUS_3 regMP0_PIC1_STATUS_3; -typedef union MP0_PIC1_INTR regMP0_PIC1_INTR; -typedef union MP0_PIC1_ID regMP0_PIC1_ID; -typedef union MP0_TIMER_0_CTRL0 regMP0_TIMER_0_CTRL0; -typedef union MP0_TIMER_1_CTRL0 regMP0_TIMER_1_CTRL0; -typedef union MP0_TIMER_2_CTRL0 regMP0_TIMER_2_CTRL0; -typedef union MP0_TIMER_3_CTRL0 regMP0_TIMER_3_CTRL0; -typedef union MP0_TIMER_0_CTRL1 regMP0_TIMER_0_CTRL1; -typedef union MP0_TIMER_1_CTRL1 regMP0_TIMER_1_CTRL1; -typedef union MP0_TIMER_2_CTRL1 regMP0_TIMER_2_CTRL1; -typedef union MP0_TIMER_3_CTRL1 regMP0_TIMER_3_CTRL1; -typedef union MP0_TIMER_0_CMP0_AUTOINC regMP0_TIMER_0_CMP0_AUTOINC; -typedef union MP0_TIMER_1_CMP0_AUTOINC regMP0_TIMER_1_CMP0_AUTOINC; -typedef union MP0_TIMER_2_CMP0_AUTOINC regMP0_TIMER_2_CMP0_AUTOINC; -typedef union MP0_TIMER_3_CMP0_AUTOINC regMP0_TIMER_3_CMP0_AUTOINC; -typedef union MP0_TIMER_0_INTEN regMP0_TIMER_0_INTEN; -typedef union MP0_TIMER_1_INTEN regMP0_TIMER_1_INTEN; -typedef union MP0_TIMER_2_INTEN regMP0_TIMER_2_INTEN; -typedef union MP0_TIMER_3_INTEN regMP0_TIMER_3_INTEN; -typedef union MP0_TIMER_OCMP0_0_0 regMP0_TIMER_OCMP0_0_0; -typedef union MP0_TIMER_OCMP0_1_0 regMP0_TIMER_OCMP0_1_0; -typedef union MP0_TIMER_OCMP0_2_0 regMP0_TIMER_OCMP0_2_0; -typedef union MP0_TIMER_OCMP0_3_0 regMP0_TIMER_OCMP0_3_0; -typedef union MP0_TIMER_OCMP0_0_1 regMP0_TIMER_OCMP0_0_1; -typedef union MP0_TIMER_OCMP0_1_1 regMP0_TIMER_OCMP0_1_1; -typedef union MP0_TIMER_OCMP0_2_1 regMP0_TIMER_OCMP0_2_1; -typedef union MP0_TIMER_OCMP0_3_1 regMP0_TIMER_OCMP0_3_1; -typedef union MP0_TIMER_OCMP0_0_2 regMP0_TIMER_OCMP0_0_2; -typedef union MP0_TIMER_OCMP0_1_2 regMP0_TIMER_OCMP0_1_2; -typedef union MP0_TIMER_OCMP0_2_2 regMP0_TIMER_OCMP0_2_2; -typedef union MP0_TIMER_OCMP0_3_2 regMP0_TIMER_OCMP0_3_2; -typedef union MP0_TIMER_OCMP0_0_3 regMP0_TIMER_OCMP0_0_3; -typedef union MP0_TIMER_OCMP0_1_3 regMP0_TIMER_OCMP0_1_3; -typedef union MP0_TIMER_OCMP0_2_3 regMP0_TIMER_OCMP0_2_3; -typedef union MP0_TIMER_OCMP0_3_3 regMP0_TIMER_OCMP0_3_3; -typedef union MP0_TIMER_0_CNT regMP0_TIMER_0_CNT; -typedef union MP0_TIMER_1_CNT regMP0_TIMER_1_CNT; -typedef union MP0_TIMER_2_CNT regMP0_TIMER_2_CNT; -typedef union MP0_TIMER_3_CNT regMP0_TIMER_3_CNT; -typedef union MP0_C2PMSG_0 regMP0_C2PMSG_0; -typedef union MP0_C2PMSG_1 regMP0_C2PMSG_1; -typedef union MP0_C2PMSG_2 regMP0_C2PMSG_2; -typedef union MP0_C2PMSG_3 regMP0_C2PMSG_3; -typedef union MP0_C2PMSG_4 regMP0_C2PMSG_4; -typedef union MP0_C2PMSG_5 regMP0_C2PMSG_5; -typedef union MP0_C2PMSG_6 regMP0_C2PMSG_6; -typedef union MP0_C2PMSG_7 regMP0_C2PMSG_7; -typedef union MP0_C2PMSG_8 regMP0_C2PMSG_8; -typedef union MP0_C2PMSG_9 regMP0_C2PMSG_9; -typedef union MP0_C2PMSG_10 regMP0_C2PMSG_10; -typedef union MP0_C2PMSG_11 regMP0_C2PMSG_11; -typedef union MP0_C2PMSG_12 regMP0_C2PMSG_12; -typedef union MP0_C2PMSG_13 regMP0_C2PMSG_13; -typedef union MP0_C2PMSG_14 regMP0_C2PMSG_14; -typedef union MP0_C2PMSG_15 regMP0_C2PMSG_15; -typedef union MP0_C2PMSG_16 regMP0_C2PMSG_16; -typedef union MP0_C2PMSG_17 regMP0_C2PMSG_17; -typedef union MP0_C2PMSG_18 regMP0_C2PMSG_18; -typedef union MP0_C2PMSG_19 regMP0_C2PMSG_19; -typedef union MP0_C2PMSG_20 regMP0_C2PMSG_20; -typedef union MP0_C2PMSG_21 regMP0_C2PMSG_21; -typedef union MP0_C2PMSG_22 regMP0_C2PMSG_22; -typedef union MP0_C2PMSG_23 regMP0_C2PMSG_23; -typedef union MP0_C2PMSG_24 regMP0_C2PMSG_24; -typedef union MP0_C2PMSG_25 regMP0_C2PMSG_25; -typedef union MP0_C2PMSG_26 regMP0_C2PMSG_26; -typedef union MP0_C2PMSG_27 regMP0_C2PMSG_27; -typedef union MP0_C2PMSG_28 regMP0_C2PMSG_28; -typedef union MP0_C2PMSG_29 regMP0_C2PMSG_29; -typedef union MP0_C2PMSG_30 regMP0_C2PMSG_30; -typedef union MP0_C2PMSG_31 regMP0_C2PMSG_31; -typedef union MP0_C2PMSG_32 regMP0_C2PMSG_32; -typedef union MP0_C2PMSG_33 regMP0_C2PMSG_33; -typedef union MP0_C2PMSG_34 regMP0_C2PMSG_34; -typedef union MP0_C2PMSG_35 regMP0_C2PMSG_35; -typedef union MP0_C2PMSG_36 regMP0_C2PMSG_36; -typedef union MP0_C2PMSG_37 regMP0_C2PMSG_37; -typedef union MP0_C2PMSG_38 regMP0_C2PMSG_38; -typedef union MP0_C2PMSG_39 regMP0_C2PMSG_39; -typedef union MP0_C2PMSG_40 regMP0_C2PMSG_40; -typedef union MP0_C2PMSG_41 regMP0_C2PMSG_41; -typedef union MP0_C2PMSG_42 regMP0_C2PMSG_42; -typedef union MP0_C2PMSG_43 regMP0_C2PMSG_43; -typedef union MP0_C2PMSG_44 regMP0_C2PMSG_44; -typedef union MP0_C2PMSG_45 regMP0_C2PMSG_45; -typedef union MP0_C2PMSG_46 regMP0_C2PMSG_46; -typedef union MP0_C2PMSG_47 regMP0_C2PMSG_47; -typedef union MP0_C2PMSG_48 regMP0_C2PMSG_48; -typedef union MP0_C2PMSG_49 regMP0_C2PMSG_49; -typedef union MP0_C2PMSG_50 regMP0_C2PMSG_50; -typedef union MP0_C2PMSG_51 regMP0_C2PMSG_51; -typedef union MP0_C2PMSG_52 regMP0_C2PMSG_52; -typedef union MP0_C2PMSG_53 regMP0_C2PMSG_53; -typedef union MP0_C2PMSG_54 regMP0_C2PMSG_54; -typedef union MP0_C2PMSG_55 regMP0_C2PMSG_55; -typedef union MP0_C2PMSG_56 regMP0_C2PMSG_56; -typedef union MP0_C2PMSG_57 regMP0_C2PMSG_57; -typedef union MP0_C2PMSG_58 regMP0_C2PMSG_58; -typedef union MP0_C2PMSG_59 regMP0_C2PMSG_59; -typedef union MP0_C2PMSG_60 regMP0_C2PMSG_60; -typedef union MP0_C2PMSG_61 regMP0_C2PMSG_61; -typedef union MP0_C2PMSG_62 regMP0_C2PMSG_62; -typedef union MP0_C2PMSG_63 regMP0_C2PMSG_63; -typedef union MP0_C2PMSG_64 regMP0_C2PMSG_64; -typedef union MP0_C2PMSG_65 regMP0_C2PMSG_65; -typedef union MP0_C2PMSG_66 regMP0_C2PMSG_66; -typedef union MP0_C2PMSG_67 regMP0_C2PMSG_67; -typedef union MP0_C2PMSG_68 regMP0_C2PMSG_68; -typedef union MP0_C2PMSG_69 regMP0_C2PMSG_69; -typedef union MP0_C2PMSG_70 regMP0_C2PMSG_70; -typedef union MP0_C2PMSG_71 regMP0_C2PMSG_71; -typedef union MP0_C2PMSG_72 regMP0_C2PMSG_72; -typedef union MP0_C2PMSG_73 regMP0_C2PMSG_73; -typedef union MP0_C2PMSG_74 regMP0_C2PMSG_74; -typedef union MP0_C2PMSG_75 regMP0_C2PMSG_75; -typedef union MP0_C2PMSG_76 regMP0_C2PMSG_76; -typedef union MP0_C2PMSG_77 regMP0_C2PMSG_77; -typedef union MP0_C2PMSG_78 regMP0_C2PMSG_78; -typedef union MP0_C2PMSG_79 regMP0_C2PMSG_79; -typedef union MP0_C2PMSG_80 regMP0_C2PMSG_80; -typedef union MP0_C2PMSG_81 regMP0_C2PMSG_81; -typedef union MP0_C2PMSG_82 regMP0_C2PMSG_82; -typedef union MP0_C2PMSG_83 regMP0_C2PMSG_83; -typedef union MP0_C2PMSG_84 regMP0_C2PMSG_84; -typedef union MP0_C2PMSG_85 regMP0_C2PMSG_85; -typedef union MP0_C2PMSG_86 regMP0_C2PMSG_86; -typedef union MP0_C2PMSG_87 regMP0_C2PMSG_87; -typedef union MP0_C2PMSG_88 regMP0_C2PMSG_88; -typedef union MP0_C2PMSG_89 regMP0_C2PMSG_89; -typedef union MP0_C2PMSG_90 regMP0_C2PMSG_90; -typedef union MP0_C2PMSG_91 regMP0_C2PMSG_91; -typedef union MP0_C2PMSG_92 regMP0_C2PMSG_92; -typedef union MP0_C2PMSG_93 regMP0_C2PMSG_93; -typedef union MP0_C2PMSG_94 regMP0_C2PMSG_94; -typedef union MP0_C2PMSG_95 regMP0_C2PMSG_95; -typedef union MP0_P2CMSG_0 regMP0_P2CMSG_0; -typedef union MP0_P2CMSG_1 regMP0_P2CMSG_1; -typedef union MP0_P2CMSG_2 regMP0_P2CMSG_2; -typedef union MP0_P2CMSG_3 regMP0_P2CMSG_3; -typedef union MP0_P2CMSG_INTEN regMP0_P2CMSG_INTEN; -typedef union MP0_P2CMSG_INTSTS regMP0_P2CMSG_INTSTS; -typedef union MP0_C2PMSG_ATTR_0 regMP0_C2PMSG_ATTR_0; -typedef union MP0_C2PMSG_ATTR_1 regMP0_C2PMSG_ATTR_1; -typedef union MP0_C2PMSG_ATTR_2 regMP0_C2PMSG_ATTR_2; -typedef union MP0_C2PMSG_ATTR_3 regMP0_C2PMSG_ATTR_3; -typedef union MP0_C2PMSG_ATTR_4 regMP0_C2PMSG_ATTR_4; -typedef union MP0_C2PMSG_ATTR_5 regMP0_C2PMSG_ATTR_5; -typedef union MP0_P2CMSG_ATTR regMP0_P2CMSG_ATTR; -typedef union MP0_P2SMSG_0 regMP0_P2SMSG_0; -typedef union MP0_P2SMSG_1 regMP0_P2SMSG_1; -typedef union MP0_P2SMSG_2 regMP0_P2SMSG_2; -typedef union MP0_P2SMSG_3 regMP0_P2SMSG_3; -typedef union MP0_P2SMSG_ATTR regMP0_P2SMSG_ATTR; -typedef union MP0_S2PMSG_ATTR regMP0_S2PMSG_ATTR; -typedef union MP0_P2SMSG_INTSTS regMP0_P2SMSG_INTSTS; -typedef union MP0_S2PMSG_0 regMP0_S2PMSG_0; -typedef union MP0_PUB_RSMU_HCID regMP0_PUB_RSMU_HCID; -typedef union MP0_PUB_RSMU_SIID regMP0_PUB_RSMU_SIID; -typedef union MP0_SAM_IH_EXT_ERR_INTR regMP0_SAM_IH_EXT_ERR_INTR; -typedef union MP0_SAM_IH_EXT_ERR_INTR_STATUS regMP0_SAM_IH_EXT_ERR_INTR_STATUS; -typedef union MP0_REVID regMP0_REVID; -typedef union MP0_RSMU_HCID regMP0_RSMU_HCID; -typedef union MP0_RSMU_SIID regMP0_RSMU_SIID; -typedef union MP0_RAM_REPAIR_DONE regMP0_RAM_REPAIR_DONE; -typedef union MP0_RAM_REPAIR_RESULT regMP0_RAM_REPAIR_RESULT; -typedef union MP0_FUSE_HARVESTING regMP0_FUSE_HARVESTING; -typedef union MP0_FUSE_RMBITS regMP0_FUSE_RMBITS; -typedef union MP0_SMS_CFG regMP0_SMS_CFG; -typedef union MP0_FUSE_SMS_0 regMP0_FUSE_SMS_0; -typedef union MP0_FUSE_SMS_1 regMP0_FUSE_SMS_1; -typedef union MP0_FUSE_SMS_2 regMP0_FUSE_SMS_2; -typedef union MP0_FUSE_SMS_3 regMP0_FUSE_SMS_3; -typedef union MP0_FUSE_SMS_4 regMP0_FUSE_SMS_4; -typedef union MP0_FUSE_SMS_5 regMP0_FUSE_SMS_5; -typedef union MP0_FUSE_SMS_6 regMP0_FUSE_SMS_6; -typedef union MP0_FUSE_SMS_7 regMP0_FUSE_SMS_7; -typedef union MP0_ACC_VIO_INTSTS regMP0_ACC_VIO_INTSTS; -typedef union MP0_TDR_MISC0_STATUS regMP0_TDR_MISC0_STATUS; -typedef union MP0_FW_OVERRIDE regMP0_FW_OVERRIDE; -typedef union MP0_BOOTROM_REVID regMP0_BOOTROM_REVID; -typedef union MP0_CRU_CPU_CTRL_STS regMP0_CRU_CPU_CTRL_STS; -typedef union MP0_SFUSE_SEC regMP0_SFUSE_SEC; -typedef union MP0_COLD_BOOT_EVENTS regMP0_COLD_BOOT_EVENTS; -typedef union MP0_WARM_BOOT_EVENTS regMP0_WARM_BOOT_EVENTS; -typedef union MP0_NSWORLD_P2CMSG_INTR_CTRL regMP0_NSWORLD_P2CMSG_INTR_CTRL; -typedef union MP0_NSWORLD_P2CMSG_CTRL regMP0_NSWORLD_P2CMSG_CTRL; -typedef union MP0_NSWORLD_C2PMSG_CTRL regMP0_NSWORLD_C2PMSG_CTRL; -typedef union MP0_NSWORLD_C2PMSG_CTRL_1 regMP0_NSWORLD_C2PMSG_CTRL_1; -typedef union MP0_NSWORLD_C2PMSG_CTRL_2 regMP0_NSWORLD_C2PMSG_CTRL_2; -typedef union MP0_NSWORLD_P2SMSG_CTRL regMP0_NSWORLD_P2SMSG_CTRL; -typedef union MP0_NSWORLD_S2PMSG_CTRL regMP0_NSWORLD_S2PMSG_CTRL; -typedef union MP0_NSWORLD_PIC0_CTRL_0 regMP0_NSWORLD_PIC0_CTRL_0; -typedef union MP0_NSWORLD_PIC0_CTRL_1 regMP0_NSWORLD_PIC0_CTRL_1; -typedef union MP0_NSWORLD_PIC0_CTRL_2 regMP0_NSWORLD_PIC0_CTRL_2; -typedef union MP0_NSWORLD_PIC0_CTRL_3 regMP0_NSWORLD_PIC0_CTRL_3; -typedef union MP0_NSWORLD_PIC1_CTRL_0 regMP0_NSWORLD_PIC1_CTRL_0; -typedef union MP0_NSWORLD_PIC1_CTRL_1 regMP0_NSWORLD_PIC1_CTRL_1; -typedef union MP0_NSWORLD_PIC1_CTRL_2 regMP0_NSWORLD_PIC1_CTRL_2; -typedef union MP0_NSWORLD_PIC1_CTRL_3 regMP0_NSWORLD_PIC1_CTRL_3; -typedef union MP0_NSWORLD_TIMER_CTRL regMP0_NSWORLD_TIMER_CTRL; -typedef union MP0_EVCNTCTL regMP0_EVCNTCTL; -typedef union MP0_EVCNTSEL regMP0_EVCNTSEL; -typedef union MP0_EVCNT0 regMP0_EVCNT0; -typedef union MP0_EVCNT1 regMP0_EVCNT1; -typedef union MP0_EVCNTHI regMP0_EVCNTHI; -typedef union MP0_J2P_MBOX0 regMP0_J2P_MBOX0; -typedef union MP0_J2P_MBOX1 regMP0_J2P_MBOX1; -typedef union MP0_J2P_ATTR regMP0_J2P_ATTR; -typedef union MP0_CRU_ACC_VIO_INTSTS regMP0_CRU_ACC_VIO_INTSTS; -typedef union MP0_ACC_VIOL_LOG0 regMP0_ACC_VIOL_LOG0; -typedef union MP0_ACC_VIOL_LOG1 regMP0_ACC_VIOL_LOG1; -typedef union MP0_SEC_SCRATCH0 regMP0_SEC_SCRATCH0; -typedef union MP0_SEC_SCRATCH1 regMP0_SEC_SCRATCH1; -typedef union MP0_SEC_SCRATCH2 regMP0_SEC_SCRATCH2; -typedef union MP0_SEC_SCRATCH3 regMP0_SEC_SCRATCH3; -typedef union MP0_STICKY regMP0_STICKY; -typedef union MP0_CRU_MISC_CTRL regMP0_CRU_MISC_CTRL; -typedef union MP0_SOFT_RESET_CTRL regMP0_SOFT_RESET_CTRL; -typedef union MP0_NS_PROT_FAULT_STATUS_0 regMP0_NS_PROT_FAULT_STATUS_0; -typedef union MP0_FW_STATUS regMP0_FW_STATUS; -typedef union MP0_ROM_FW_CNTL regMP0_ROM_FW_CNTL; -typedef union MP0_FW_MISC_CTRL regMP0_FW_MISC_CTRL; -typedef union MP0_AEB_STATUS_0 regMP0_AEB_STATUS_0; -typedef union MP0_AEB_STATUS_1 regMP0_AEB_STATUS_1; -typedef union MP0_AEB_JTAG_DBG_CTRL regMP0_AEB_JTAG_DBG_CTRL; -typedef union MP0_AEB_JTAG_DBG_CTRL_LOCK regMP0_AEB_JTAG_DBG_CTRL_LOCK; -typedef union MP0_AEB_CNTL_0 regMP0_AEB_CNTL_0; -typedef union MP0_AEB_CNTL_1 regMP0_AEB_CNTL_1; -typedef union MP0_PIC0_LEVEL_0 regMP0_PIC0_LEVEL_0; -typedef union MP0_PIC0_LEVEL_1 regMP0_PIC0_LEVEL_1; -typedef union MP0_PIC0_LEVEL_2 regMP0_PIC0_LEVEL_2; -typedef union MP0_PIC0_LEVEL_3 regMP0_PIC0_LEVEL_3; -typedef union MP0_PIC0_EDGE_0 regMP0_PIC0_EDGE_0; -typedef union MP0_PIC0_EDGE_1 regMP0_PIC0_EDGE_1; -typedef union MP0_PIC0_EDGE_2 regMP0_PIC0_EDGE_2; -typedef union MP0_PIC0_EDGE_3 regMP0_PIC0_EDGE_3; -typedef union MP0_PIC0_PRIORITY_0 regMP0_PIC0_PRIORITY_0; -typedef union MP0_PIC0_PRIORITY_1 regMP0_PIC0_PRIORITY_1; -typedef union MP0_PIC0_PRIORITY_2 regMP0_PIC0_PRIORITY_2; -typedef union MP0_PIC0_PRIORITY_3 regMP0_PIC0_PRIORITY_3; -typedef union MP0_PIC0_PRIORITY_4 regMP0_PIC0_PRIORITY_4; -typedef union MP0_PIC0_PRIORITY_5 regMP0_PIC0_PRIORITY_5; -typedef union MP0_PIC0_PRIORITY_6 regMP0_PIC0_PRIORITY_6; -typedef union MP0_PIC0_PRIORITY_7 regMP0_PIC0_PRIORITY_7; -typedef union MP0_PIC0_PRIORITY_8 regMP0_PIC0_PRIORITY_8; -typedef union MP0_PIC0_PRIORITY_9 regMP0_PIC0_PRIORITY_9; -typedef union MP0_PIC0_PRIORITY_10 regMP0_PIC0_PRIORITY_10; -typedef union MP0_PIC0_PRIORITY_11 regMP0_PIC0_PRIORITY_11; -typedef union MP0_PIC0_PRIORITY_12 regMP0_PIC0_PRIORITY_12; -typedef union MP0_PIC0_PRIORITY_13 regMP0_PIC0_PRIORITY_13; -typedef union MP0_PIC0_PRIORITY_14 regMP0_PIC0_PRIORITY_14; -typedef union MP0_PIC0_PRIORITY_15 regMP0_PIC0_PRIORITY_15; -typedef union MP0_PIC0_PRIORITY_16 regMP0_PIC0_PRIORITY_16; -typedef union MP0_PIC0_PRIORITY_17 regMP0_PIC0_PRIORITY_17; -typedef union MP0_PIC0_PRIORITY_18 regMP0_PIC0_PRIORITY_18; -typedef union MP0_PIC0_PRIORITY_19 regMP0_PIC0_PRIORITY_19; -typedef union MP0_PIC0_PRIORITY_20 regMP0_PIC0_PRIORITY_20; -typedef union MP0_PIC0_PRIORITY_21 regMP0_PIC0_PRIORITY_21; -typedef union MP0_PIC0_PRIORITY_22 regMP0_PIC0_PRIORITY_22; -typedef union MP0_PIC0_PRIORITY_23 regMP0_PIC0_PRIORITY_23; -typedef union MP0_PIC0_PRIORITY_24 regMP0_PIC0_PRIORITY_24; -typedef union MP0_PIC0_PRIORITY_25 regMP0_PIC0_PRIORITY_25; -typedef union MP0_PIC0_PRIORITY_26 regMP0_PIC0_PRIORITY_26; -typedef union MP0_PIC0_PRIORITY_27 regMP0_PIC0_PRIORITY_27; -typedef union MP0_PIC0_PRIORITY_28 regMP0_PIC0_PRIORITY_28; -typedef union MP0_PIC0_PRIORITY_29 regMP0_PIC0_PRIORITY_29; -typedef union MP0_PIC0_PRIORITY_30 regMP0_PIC0_PRIORITY_30; -typedef union MP0_PIC0_PRIORITY_31 regMP0_PIC0_PRIORITY_31; -typedef union MP0_PIC1_LEVEL_0 regMP0_PIC1_LEVEL_0; -typedef union MP0_PIC1_LEVEL_1 regMP0_PIC1_LEVEL_1; -typedef union MP0_PIC1_LEVEL_2 regMP0_PIC1_LEVEL_2; -typedef union MP0_PIC1_LEVEL_3 regMP0_PIC1_LEVEL_3; -typedef union MP0_PIC1_EDGE_0 regMP0_PIC1_EDGE_0; -typedef union MP0_PIC1_EDGE_1 regMP0_PIC1_EDGE_1; -typedef union MP0_PIC1_EDGE_2 regMP0_PIC1_EDGE_2; -typedef union MP0_PIC1_EDGE_3 regMP0_PIC1_EDGE_3; -typedef union MP0_PIC1_PRIORITY_0 regMP0_PIC1_PRIORITY_0; -typedef union MP0_PIC1_PRIORITY_1 regMP0_PIC1_PRIORITY_1; -typedef union MP0_PIC1_PRIORITY_2 regMP0_PIC1_PRIORITY_2; -typedef union MP0_PIC1_PRIORITY_3 regMP0_PIC1_PRIORITY_3; -typedef union MP0_PIC1_PRIORITY_4 regMP0_PIC1_PRIORITY_4; -typedef union MP0_PIC1_PRIORITY_5 regMP0_PIC1_PRIORITY_5; -typedef union MP0_PIC1_PRIORITY_6 regMP0_PIC1_PRIORITY_6; -typedef union MP0_PIC1_PRIORITY_7 regMP0_PIC1_PRIORITY_7; -typedef union MP0_PIC1_PRIORITY_8 regMP0_PIC1_PRIORITY_8; -typedef union MP0_PIC1_PRIORITY_9 regMP0_PIC1_PRIORITY_9; -typedef union MP0_PIC1_PRIORITY_10 regMP0_PIC1_PRIORITY_10; -typedef union MP0_PIC1_PRIORITY_11 regMP0_PIC1_PRIORITY_11; -typedef union MP0_PIC1_PRIORITY_12 regMP0_PIC1_PRIORITY_12; -typedef union MP0_PIC1_PRIORITY_13 regMP0_PIC1_PRIORITY_13; -typedef union MP0_PIC1_PRIORITY_14 regMP0_PIC1_PRIORITY_14; -typedef union MP0_PIC1_PRIORITY_15 regMP0_PIC1_PRIORITY_15; -typedef union MP0_PIC1_PRIORITY_16 regMP0_PIC1_PRIORITY_16; -typedef union MP0_PIC1_PRIORITY_17 regMP0_PIC1_PRIORITY_17; -typedef union MP0_PIC1_PRIORITY_18 regMP0_PIC1_PRIORITY_18; -typedef union MP0_PIC1_PRIORITY_19 regMP0_PIC1_PRIORITY_19; -typedef union MP0_PIC1_PRIORITY_20 regMP0_PIC1_PRIORITY_20; -typedef union MP0_PIC1_PRIORITY_21 regMP0_PIC1_PRIORITY_21; -typedef union MP0_PIC1_PRIORITY_22 regMP0_PIC1_PRIORITY_22; -typedef union MP0_PIC1_PRIORITY_23 regMP0_PIC1_PRIORITY_23; -typedef union MP0_PIC1_PRIORITY_24 regMP0_PIC1_PRIORITY_24; -typedef union MP0_PIC1_PRIORITY_25 regMP0_PIC1_PRIORITY_25; -typedef union MP0_PIC1_PRIORITY_26 regMP0_PIC1_PRIORITY_26; -typedef union MP0_PIC1_PRIORITY_27 regMP0_PIC1_PRIORITY_27; -typedef union MP0_PIC1_PRIORITY_28 regMP0_PIC1_PRIORITY_28; -typedef union MP0_PIC1_PRIORITY_29 regMP0_PIC1_PRIORITY_29; -typedef union MP0_PIC1_PRIORITY_30 regMP0_PIC1_PRIORITY_30; -typedef union MP0_PIC1_PRIORITY_31 regMP0_PIC1_PRIORITY_31; -typedef union MP0_SAM_IH_EXT_ERR_INTR_ACK regMP0_SAM_IH_EXT_ERR_INTR_ACK; -typedef union MP0_RSMU_SECINTR_FETCH0 regMP0_RSMU_SECINTR_FETCH0; -typedef union MP0_RSMU_SECINTR_FETCH1 regMP0_RSMU_SECINTR_FETCH1; -typedef union MP0_RSMU_SECINTR_STATUS regMP0_RSMU_SECINTR_STATUS; -typedef union MP0_RSMU_SECINTR_FLUSH0 regMP0_RSMU_SECINTR_FLUSH0; -typedef union MP0_RSMU_SECINTR_FLUSH1 regMP0_RSMU_SECINTR_FLUSH1; -typedef union MP0_RSMU_SECINTR_CTRL regMP0_RSMU_SECINTR_CTRL; -typedef union MP0_RSMU_SECINTR_OFCNT regMP0_RSMU_SECINTR_OFCNT; -typedef union MP0_SMN_SAM_IH_EXT_ERR_INTR regMP0_SMN_SAM_IH_EXT_ERR_INTR; -typedef union MP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS regMP0_SMN_SAM_IH_EXT_ERR_INTR_STATUS; -typedef union MP0_SMN_C2PMSG_32 regMP0_SMN_C2PMSG_32; -typedef union MP0_SMN_C2PMSG_33 regMP0_SMN_C2PMSG_33; -typedef union MP0_SMN_C2PMSG_34 regMP0_SMN_C2PMSG_34; -typedef union MP0_SMN_C2PMSG_35 regMP0_SMN_C2PMSG_35; -typedef union MP0_SMN_C2PMSG_36 regMP0_SMN_C2PMSG_36; -typedef union MP0_SMN_C2PMSG_37 regMP0_SMN_C2PMSG_37; -typedef union MP0_SMN_C2PMSG_38 regMP0_SMN_C2PMSG_38; -typedef union MP0_SMN_C2PMSG_39 regMP0_SMN_C2PMSG_39; -typedef union MP0_SMN_C2PMSG_40 regMP0_SMN_C2PMSG_40; -typedef union MP0_SMN_C2PMSG_41 regMP0_SMN_C2PMSG_41; -typedef union MP0_SMN_C2PMSG_42 regMP0_SMN_C2PMSG_42; -typedef union MP0_SMN_C2PMSG_43 regMP0_SMN_C2PMSG_43; -typedef union MP0_SMN_C2PMSG_44 regMP0_SMN_C2PMSG_44; -typedef union MP0_SMN_C2PMSG_45 regMP0_SMN_C2PMSG_45; -typedef union MP0_SMN_C2PMSG_46 regMP0_SMN_C2PMSG_46; -typedef union MP0_SMN_C2PMSG_47 regMP0_SMN_C2PMSG_47; -typedef union MP0_SMN_C2PMSG_48 regMP0_SMN_C2PMSG_48; -typedef union MP0_SMN_C2PMSG_49 regMP0_SMN_C2PMSG_49; -typedef union MP0_SMN_C2PMSG_50 regMP0_SMN_C2PMSG_50; -typedef union MP0_SMN_C2PMSG_51 regMP0_SMN_C2PMSG_51; -typedef union MP0_SMN_C2PMSG_52 regMP0_SMN_C2PMSG_52; -typedef union MP0_SMN_C2PMSG_53 regMP0_SMN_C2PMSG_53; -typedef union MP0_SMN_C2PMSG_54 regMP0_SMN_C2PMSG_54; -typedef union MP0_SMN_C2PMSG_55 regMP0_SMN_C2PMSG_55; -typedef union MP0_SMN_C2PMSG_56 regMP0_SMN_C2PMSG_56; -typedef union MP0_SMN_C2PMSG_57 regMP0_SMN_C2PMSG_57; -typedef union MP0_SMN_C2PMSG_58 regMP0_SMN_C2PMSG_58; -typedef union MP0_SMN_C2PMSG_59 regMP0_SMN_C2PMSG_59; -typedef union MP0_SMN_C2PMSG_60 regMP0_SMN_C2PMSG_60; -typedef union MP0_SMN_C2PMSG_61 regMP0_SMN_C2PMSG_61; -typedef union MP0_SMN_C2PMSG_62 regMP0_SMN_C2PMSG_62; -typedef union MP0_SMN_C2PMSG_63 regMP0_SMN_C2PMSG_63; -typedef union MP0_SMN_C2PMSG_64 regMP0_SMN_C2PMSG_64; -typedef union MP0_SMN_C2PMSG_65 regMP0_SMN_C2PMSG_65; -typedef union MP0_SMN_C2PMSG_66 regMP0_SMN_C2PMSG_66; -typedef union MP0_SMN_C2PMSG_67 regMP0_SMN_C2PMSG_67; -typedef union MP0_SMN_C2PMSG_68 regMP0_SMN_C2PMSG_68; -typedef union MP0_SMN_C2PMSG_69 regMP0_SMN_C2PMSG_69; -typedef union MP0_SMN_C2PMSG_70 regMP0_SMN_C2PMSG_70; -typedef union MP0_SMN_C2PMSG_71 regMP0_SMN_C2PMSG_71; -typedef union MP0_SMN_C2PMSG_72 regMP0_SMN_C2PMSG_72; -typedef union MP0_SMN_C2PMSG_73 regMP0_SMN_C2PMSG_73; -typedef union MP0_SMN_C2PMSG_74 regMP0_SMN_C2PMSG_74; -typedef union MP0_SMN_C2PMSG_75 regMP0_SMN_C2PMSG_75; -typedef union MP0_SMN_C2PMSG_76 regMP0_SMN_C2PMSG_76; -typedef union MP0_SMN_C2PMSG_77 regMP0_SMN_C2PMSG_77; -typedef union MP0_SMN_C2PMSG_78 regMP0_SMN_C2PMSG_78; -typedef union MP0_SMN_C2PMSG_79 regMP0_SMN_C2PMSG_79; -typedef union MP0_SMN_C2PMSG_80 regMP0_SMN_C2PMSG_80; -typedef union MP0_SMN_C2PMSG_81 regMP0_SMN_C2PMSG_81; -typedef union MP0_SMN_C2PMSG_82 regMP0_SMN_C2PMSG_82; -typedef union MP0_SMN_C2PMSG_83 regMP0_SMN_C2PMSG_83; -typedef union MP0_SMN_C2PMSG_84 regMP0_SMN_C2PMSG_84; -typedef union MP0_SMN_C2PMSG_85 regMP0_SMN_C2PMSG_85; -typedef union MP0_SMN_C2PMSG_86 regMP0_SMN_C2PMSG_86; -typedef union MP0_SMN_C2PMSG_87 regMP0_SMN_C2PMSG_87; -typedef union MP0_SMN_C2PMSG_88 regMP0_SMN_C2PMSG_88; -typedef union MP0_SMN_C2PMSG_89 regMP0_SMN_C2PMSG_89; -typedef union MP0_SMN_C2PMSG_90 regMP0_SMN_C2PMSG_90; -typedef union MP0_SMN_C2PMSG_91 regMP0_SMN_C2PMSG_91; -typedef union MP0_SMN_C2PMSG_92 regMP0_SMN_C2PMSG_92; -typedef union MP0_SMN_C2PMSG_93 regMP0_SMN_C2PMSG_93; -typedef union MP0_SMN_C2PMSG_94 regMP0_SMN_C2PMSG_94; -typedef union MP0_SMN_C2PMSG_95 regMP0_SMN_C2PMSG_95; -typedef union MP0_RSMU_PUB_RSMU_HCID regMP0_RSMU_PUB_RSMU_HCID; -typedef union MP0_RSMU_PUB_RSMU_SIID regMP0_RSMU_PUB_RSMU_SIID; -typedef union MP0_MMU_SRAM_FLOP_START_ADDR regMP0_MMU_SRAM_FLOP_START_ADDR; -typedef union MP0_MMU_SRAM_ACC_VIOLATION_LOG_ADDR regMP0_MMU_SRAM_ACC_VIOLATION_LOG_ADDR; -typedef union MP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS regMP0_MMU_SRAM_ACC_VIOLATION_LOG_STATUS; -typedef union MP0_MMU_MISC_CNTL regMP0_MMU_MISC_CNTL; -typedef union MP0_MMU_ACCESS_ERR_LOG regMP0_MMU_ACCESS_ERR_LOG; -typedef union MP0_MMU_SRAM_UNSECURE_BAR regMP0_MMU_SRAM_UNSECURE_BAR; -typedef union MP0_MMU_SCRATCH_0 regMP0_MMU_SCRATCH_0; -typedef union MP0_MMU_SCRATCH_1 regMP0_MMU_SCRATCH_1; -typedef union MP0_MMU_SCRATCH_2 regMP0_MMU_SCRATCH_2; -typedef union MP0_MMU_SCRATCH_3 regMP0_MMU_SCRATCH_3; -typedef union MP0_MMU_SCRATCH_4 regMP0_MMU_SCRATCH_4; -typedef union MP0_MMU_SCRATCH_5 regMP0_MMU_SCRATCH_5; -typedef union MP0_MMU_SCRATCH_6 regMP0_MMU_SCRATCH_6; -typedef union MP0_MMU_SCRATCH_7 regMP0_MMU_SCRATCH_7; -typedef union MP0_MCA_ACCESS_CNTL regMP0_MCA_ACCESS_CNTL; -typedef union MP0_MCA_ACCESS_WR_DATA regMP0_MCA_ACCESS_WR_DATA; -typedef union MP0_MCA_ACCESS_RD_DATA regMP0_MCA_ACCESS_RD_DATA; -typedef union MP0_MMHUB_SOC_TLB0_1 regMP0_MMHUB_SOC_TLB0_1; -typedef union MP0_MMHUB_SOC_TLB0_2 regMP0_MMHUB_SOC_TLB0_2; -typedef union MP0_MMHUB_SOC_TLB0_3 regMP0_MMHUB_SOC_TLB0_3; -typedef union MP0_MMHUB_SOC_TLB0_4 regMP0_MMHUB_SOC_TLB0_4; -typedef union MP0_MMHUB_SOC_TLB0_5 regMP0_MMHUB_SOC_TLB0_5; -typedef union MP0_MMHUB_SOC_TLB0_6 regMP0_MMHUB_SOC_TLB0_6; -typedef union MP0_MMHUB_SOC_TLB0_7 regMP0_MMHUB_SOC_TLB0_7; -typedef union MP0_MMHUB_SOC_TLB0_8 regMP0_MMHUB_SOC_TLB0_8; -typedef union MP0_MMHUB_SOC_TLB0_9 regMP0_MMHUB_SOC_TLB0_9; -typedef union MP0_MMHUB_SOC_TLB0_10 regMP0_MMHUB_SOC_TLB0_10; -typedef union MP0_MMHUB_SOC_TLB0_11 regMP0_MMHUB_SOC_TLB0_11; -typedef union MP0_MMHUB_SOC_TLB0_12 regMP0_MMHUB_SOC_TLB0_12; -typedef union MP0_MMHUB_SOC_TLB0_13 regMP0_MMHUB_SOC_TLB0_13; -typedef union MP0_MMHUB_SOC_TLB0_14 regMP0_MMHUB_SOC_TLB0_14; -typedef union MP0_MMHUB_SOC_TLB0_15 regMP0_MMHUB_SOC_TLB0_15; -typedef union MP0_MMHUB_SOC_TLB0_16 regMP0_MMHUB_SOC_TLB0_16; -typedef union MP0_MMHUB_SOC_TLB0_17 regMP0_MMHUB_SOC_TLB0_17; -typedef union MP0_MMHUB_SOC_TLB0_18 regMP0_MMHUB_SOC_TLB0_18; -typedef union MP0_MMHUB_SOC_TLB0_19 regMP0_MMHUB_SOC_TLB0_19; -typedef union MP0_MMHUB_SOC_TLB0_20 regMP0_MMHUB_SOC_TLB0_20; -typedef union MP0_MMHUB_SOC_TLB0_21 regMP0_MMHUB_SOC_TLB0_21; -typedef union MP0_MMHUB_SOC_TLB0_22 regMP0_MMHUB_SOC_TLB0_22; -typedef union MP0_MMHUB_SOC_TLB0_23 regMP0_MMHUB_SOC_TLB0_23; -typedef union MP0_MMHUB_SOC_TLB0_24 regMP0_MMHUB_SOC_TLB0_24; -typedef union MP0_MMHUB_SOC_TLB0_25 regMP0_MMHUB_SOC_TLB0_25; -typedef union MP0_MMHUB_SOC_TLB0_26 regMP0_MMHUB_SOC_TLB0_26; -typedef union MP0_MMHUB_SOC_TLB0_27 regMP0_MMHUB_SOC_TLB0_27; -typedef union MP0_MMHUB_SOC_TLB0_28 regMP0_MMHUB_SOC_TLB0_28; -typedef union MP0_MMHUB_SOC_TLB0_29 regMP0_MMHUB_SOC_TLB0_29; -typedef union MP0_MMHUB_SOC_TLB0_30 regMP0_MMHUB_SOC_TLB0_30; -typedef union MP0_MMHUB_SOC_TLB0_31 regMP0_MMHUB_SOC_TLB0_31; -typedef union MP0_MMHUB_SOC_TLB0_32 regMP0_MMHUB_SOC_TLB0_32; -typedef union MP0_MMHUB_SOC_TLB0_33 regMP0_MMHUB_SOC_TLB0_33; -typedef union MP0_MMHUB_SOC_TLB0_34 regMP0_MMHUB_SOC_TLB0_34; -typedef union MP0_MMHUB_SOC_TLB0_35 regMP0_MMHUB_SOC_TLB0_35; -typedef union MP0_MMHUB_SOC_TLB0_36 regMP0_MMHUB_SOC_TLB0_36; -typedef union MP0_MMHUB_SOC_TLB0_37 regMP0_MMHUB_SOC_TLB0_37; -typedef union MP0_MMHUB_SOC_TLB0_38 regMP0_MMHUB_SOC_TLB0_38; -typedef union MP0_MMHUB_SOC_TLB0_39 regMP0_MMHUB_SOC_TLB0_39; -typedef union MP0_MMHUB_SOC_TLB0_40 regMP0_MMHUB_SOC_TLB0_40; -typedef union MP0_MMHUB_SOC_TLB0_41 regMP0_MMHUB_SOC_TLB0_41; -typedef union MP0_MMHUB_SOC_TLB0_42 regMP0_MMHUB_SOC_TLB0_42; -typedef union MP0_MMHUB_SOC_TLB0_43 regMP0_MMHUB_SOC_TLB0_43; -typedef union MP0_MMHUB_SOC_TLB0_44 regMP0_MMHUB_SOC_TLB0_44; -typedef union MP0_MMHUB_SOC_TLB0_45 regMP0_MMHUB_SOC_TLB0_45; -typedef union MP0_MMHUB_SOC_TLB0_46 regMP0_MMHUB_SOC_TLB0_46; -typedef union MP0_MMHUB_SOC_TLB0_47 regMP0_MMHUB_SOC_TLB0_47; -typedef union MP0_MMHUB_SOC_TLB0_48 regMP0_MMHUB_SOC_TLB0_48; -typedef union MP0_MMHUB_SOC_TLB0_49 regMP0_MMHUB_SOC_TLB0_49; -typedef union MP0_MMHUB_SOC_TLB0_50 regMP0_MMHUB_SOC_TLB0_50; -typedef union MP0_MMHUB_SOC_TLB0_51 regMP0_MMHUB_SOC_TLB0_51; -typedef union MP0_MMHUB_SOC_TLB0_52 regMP0_MMHUB_SOC_TLB0_52; -typedef union MP0_MMHUB_SOC_TLB0_53 regMP0_MMHUB_SOC_TLB0_53; -typedef union MP0_MMHUB_SOC_TLB0_54 regMP0_MMHUB_SOC_TLB0_54; -typedef union MP0_MMHUB_SOC_TLB0_55 regMP0_MMHUB_SOC_TLB0_55; -typedef union MP0_MMHUB_SOC_TLB0_56 regMP0_MMHUB_SOC_TLB0_56; -typedef union MP0_MMHUB_SOC_TLB0_57 regMP0_MMHUB_SOC_TLB0_57; -typedef union MP0_MMHUB_SOC_TLB0_58 regMP0_MMHUB_SOC_TLB0_58; -typedef union MP0_MMHUB_SOC_TLB0_59 regMP0_MMHUB_SOC_TLB0_59; -typedef union MP0_MMHUB_SOC_TLB0_60 regMP0_MMHUB_SOC_TLB0_60; -typedef union MP0_MMHUB_SOC_TLB0_61 regMP0_MMHUB_SOC_TLB0_61; -typedef union MP0_MMHUB_SOC_TLB0_62 regMP0_MMHUB_SOC_TLB0_62; -typedef union MP0_MMHUB_SOC_TLB1_1 regMP0_MMHUB_SOC_TLB1_1; -typedef union MP0_MMHUB_SOC_TLB1_2 regMP0_MMHUB_SOC_TLB1_2; -typedef union MP0_MMHUB_SOC_TLB1_3 regMP0_MMHUB_SOC_TLB1_3; -typedef union MP0_MMHUB_SOC_TLB1_4 regMP0_MMHUB_SOC_TLB1_4; -typedef union MP0_MMHUB_SOC_TLB1_5 regMP0_MMHUB_SOC_TLB1_5; -typedef union MP0_MMHUB_SOC_TLB1_6 regMP0_MMHUB_SOC_TLB1_6; -typedef union MP0_MMHUB_SOC_TLB1_7 regMP0_MMHUB_SOC_TLB1_7; -typedef union MP0_MMHUB_SOC_TLB1_8 regMP0_MMHUB_SOC_TLB1_8; -typedef union MP0_MMHUB_SOC_TLB1_9 regMP0_MMHUB_SOC_TLB1_9; -typedef union MP0_MMHUB_SOC_TLB1_10 regMP0_MMHUB_SOC_TLB1_10; -typedef union MP0_MMHUB_SOC_TLB1_11 regMP0_MMHUB_SOC_TLB1_11; -typedef union MP0_MMHUB_SOC_TLB1_12 regMP0_MMHUB_SOC_TLB1_12; -typedef union MP0_MMHUB_SOC_TLB1_13 regMP0_MMHUB_SOC_TLB1_13; -typedef union MP0_MMHUB_SOC_TLB1_14 regMP0_MMHUB_SOC_TLB1_14; -typedef union MP0_MMHUB_SOC_TLB1_15 regMP0_MMHUB_SOC_TLB1_15; -typedef union MP0_MMHUB_SOC_TLB1_16 regMP0_MMHUB_SOC_TLB1_16; -typedef union MP0_MMHUB_SOC_TLB1_17 regMP0_MMHUB_SOC_TLB1_17; -typedef union MP0_MMHUB_SOC_TLB1_18 regMP0_MMHUB_SOC_TLB1_18; -typedef union MP0_MMHUB_SOC_TLB1_19 regMP0_MMHUB_SOC_TLB1_19; -typedef union MP0_MMHUB_SOC_TLB1_20 regMP0_MMHUB_SOC_TLB1_20; -typedef union MP0_MMHUB_SOC_TLB1_21 regMP0_MMHUB_SOC_TLB1_21; -typedef union MP0_MMHUB_SOC_TLB1_22 regMP0_MMHUB_SOC_TLB1_22; -typedef union MP0_MMHUB_SOC_TLB1_23 regMP0_MMHUB_SOC_TLB1_23; -typedef union MP0_MMHUB_SOC_TLB1_24 regMP0_MMHUB_SOC_TLB1_24; -typedef union MP0_MMHUB_SOC_TLB1_25 regMP0_MMHUB_SOC_TLB1_25; -typedef union MP0_MMHUB_SOC_TLB1_26 regMP0_MMHUB_SOC_TLB1_26; -typedef union MP0_MMHUB_SOC_TLB1_27 regMP0_MMHUB_SOC_TLB1_27; -typedef union MP0_MMHUB_SOC_TLB1_28 regMP0_MMHUB_SOC_TLB1_28; -typedef union MP0_MMHUB_SOC_TLB1_29 regMP0_MMHUB_SOC_TLB1_29; -typedef union MP0_MMHUB_SOC_TLB1_30 regMP0_MMHUB_SOC_TLB1_30; -typedef union MP0_MMHUB_SOC_TLB1_31 regMP0_MMHUB_SOC_TLB1_31; -typedef union MP0_MMHUB_SOC_TLB1_32 regMP0_MMHUB_SOC_TLB1_32; -typedef union MP0_MMHUB_SOC_TLB1_33 regMP0_MMHUB_SOC_TLB1_33; -typedef union MP0_MMHUB_SOC_TLB1_34 regMP0_MMHUB_SOC_TLB1_34; -typedef union MP0_MMHUB_SOC_TLB1_35 regMP0_MMHUB_SOC_TLB1_35; -typedef union MP0_MMHUB_SOC_TLB1_36 regMP0_MMHUB_SOC_TLB1_36; -typedef union MP0_MMHUB_SOC_TLB1_37 regMP0_MMHUB_SOC_TLB1_37; -typedef union MP0_MMHUB_SOC_TLB1_38 regMP0_MMHUB_SOC_TLB1_38; -typedef union MP0_MMHUB_SOC_TLB1_39 regMP0_MMHUB_SOC_TLB1_39; -typedef union MP0_MMHUB_SOC_TLB1_40 regMP0_MMHUB_SOC_TLB1_40; -typedef union MP0_MMHUB_SOC_TLB1_41 regMP0_MMHUB_SOC_TLB1_41; -typedef union MP0_MMHUB_SOC_TLB1_42 regMP0_MMHUB_SOC_TLB1_42; -typedef union MP0_MMHUB_SOC_TLB1_43 regMP0_MMHUB_SOC_TLB1_43; -typedef union MP0_MMHUB_SOC_TLB1_44 regMP0_MMHUB_SOC_TLB1_44; -typedef union MP0_MMHUB_SOC_TLB1_45 regMP0_MMHUB_SOC_TLB1_45; -typedef union MP0_MMHUB_SOC_TLB1_46 regMP0_MMHUB_SOC_TLB1_46; -typedef union MP0_MMHUB_SOC_TLB1_47 regMP0_MMHUB_SOC_TLB1_47; -typedef union MP0_MMHUB_SOC_TLB1_48 regMP0_MMHUB_SOC_TLB1_48; -typedef union MP0_MMHUB_SOC_TLB1_49 regMP0_MMHUB_SOC_TLB1_49; -typedef union MP0_MMHUB_SOC_TLB1_50 regMP0_MMHUB_SOC_TLB1_50; -typedef union MP0_MMHUB_SOC_TLB1_51 regMP0_MMHUB_SOC_TLB1_51; -typedef union MP0_MMHUB_SOC_TLB1_52 regMP0_MMHUB_SOC_TLB1_52; -typedef union MP0_MMHUB_SOC_TLB1_53 regMP0_MMHUB_SOC_TLB1_53; -typedef union MP0_MMHUB_SOC_TLB1_54 regMP0_MMHUB_SOC_TLB1_54; -typedef union MP0_MMHUB_SOC_TLB1_55 regMP0_MMHUB_SOC_TLB1_55; -typedef union MP0_MMHUB_SOC_TLB1_56 regMP0_MMHUB_SOC_TLB1_56; -typedef union MP0_MMHUB_SOC_TLB1_57 regMP0_MMHUB_SOC_TLB1_57; -typedef union MP0_MMHUB_SOC_TLB1_58 regMP0_MMHUB_SOC_TLB1_58; -typedef union MP0_MMHUB_SOC_TLB1_59 regMP0_MMHUB_SOC_TLB1_59; -typedef union MP0_MMHUB_SOC_TLB1_60 regMP0_MMHUB_SOC_TLB1_60; -typedef union MP0_MMHUB_SOC_TLB1_61 regMP0_MMHUB_SOC_TLB1_61; -typedef union MP0_MMHUB_SOC_TLB1_62 regMP0_MMHUB_SOC_TLB1_62; -typedef union MP0_MMHUB_SOC_TLB2_1 regMP0_MMHUB_SOC_TLB2_1; -typedef union MP0_MMHUB_SOC_TLB2_2 regMP0_MMHUB_SOC_TLB2_2; -typedef union MP0_MMHUB_SOC_TLB2_3 regMP0_MMHUB_SOC_TLB2_3; -typedef union MP0_MMHUB_SOC_TLB2_4 regMP0_MMHUB_SOC_TLB2_4; -typedef union MP0_MMHUB_SOC_TLB2_5 regMP0_MMHUB_SOC_TLB2_5; -typedef union MP0_MMHUB_SOC_TLB2_6 regMP0_MMHUB_SOC_TLB2_6; -typedef union MP0_MMHUB_SOC_TLB2_7 regMP0_MMHUB_SOC_TLB2_7; -typedef union MP0_MMHUB_SOC_TLB2_8 regMP0_MMHUB_SOC_TLB2_8; -typedef union MP0_MMHUB_SOC_TLB2_9 regMP0_MMHUB_SOC_TLB2_9; -typedef union MP0_MMHUB_SOC_TLB2_10 regMP0_MMHUB_SOC_TLB2_10; -typedef union MP0_MMHUB_SOC_TLB2_11 regMP0_MMHUB_SOC_TLB2_11; -typedef union MP0_MMHUB_SOC_TLB2_12 regMP0_MMHUB_SOC_TLB2_12; -typedef union MP0_MMHUB_SOC_TLB2_13 regMP0_MMHUB_SOC_TLB2_13; -typedef union MP0_MMHUB_SOC_TLB2_14 regMP0_MMHUB_SOC_TLB2_14; -typedef union MP0_MMHUB_SOC_TLB2_15 regMP0_MMHUB_SOC_TLB2_15; -typedef union MP0_MMHUB_SOC_TLB2_16 regMP0_MMHUB_SOC_TLB2_16; -typedef union MP0_MMHUB_SOC_TLB2_17 regMP0_MMHUB_SOC_TLB2_17; -typedef union MP0_MMHUB_SOC_TLB2_18 regMP0_MMHUB_SOC_TLB2_18; -typedef union MP0_MMHUB_SOC_TLB2_19 regMP0_MMHUB_SOC_TLB2_19; -typedef union MP0_MMHUB_SOC_TLB2_20 regMP0_MMHUB_SOC_TLB2_20; -typedef union MP0_MMHUB_SOC_TLB2_21 regMP0_MMHUB_SOC_TLB2_21; -typedef union MP0_MMHUB_SOC_TLB2_22 regMP0_MMHUB_SOC_TLB2_22; -typedef union MP0_MMHUB_SOC_TLB2_23 regMP0_MMHUB_SOC_TLB2_23; -typedef union MP0_MMHUB_SOC_TLB2_24 regMP0_MMHUB_SOC_TLB2_24; -typedef union MP0_MMHUB_SOC_TLB2_25 regMP0_MMHUB_SOC_TLB2_25; -typedef union MP0_MMHUB_SOC_TLB2_26 regMP0_MMHUB_SOC_TLB2_26; -typedef union MP0_MMHUB_SOC_TLB2_27 regMP0_MMHUB_SOC_TLB2_27; -typedef union MP0_MMHUB_SOC_TLB2_28 regMP0_MMHUB_SOC_TLB2_28; -typedef union MP0_MMHUB_SOC_TLB2_29 regMP0_MMHUB_SOC_TLB2_29; -typedef union MP0_MMHUB_SOC_TLB2_30 regMP0_MMHUB_SOC_TLB2_30; -typedef union MP0_MMHUB_SOC_TLB2_31 regMP0_MMHUB_SOC_TLB2_31; -typedef union MP0_MMHUB_SOC_TLB2_32 regMP0_MMHUB_SOC_TLB2_32; -typedef union MP0_MMHUB_SOC_TLB2_33 regMP0_MMHUB_SOC_TLB2_33; -typedef union MP0_MMHUB_SOC_TLB2_34 regMP0_MMHUB_SOC_TLB2_34; -typedef union MP0_MMHUB_SOC_TLB2_35 regMP0_MMHUB_SOC_TLB2_35; -typedef union MP0_MMHUB_SOC_TLB2_36 regMP0_MMHUB_SOC_TLB2_36; -typedef union MP0_MMHUB_SOC_TLB2_37 regMP0_MMHUB_SOC_TLB2_37; -typedef union MP0_MMHUB_SOC_TLB2_38 regMP0_MMHUB_SOC_TLB2_38; -typedef union MP0_MMHUB_SOC_TLB2_39 regMP0_MMHUB_SOC_TLB2_39; -typedef union MP0_MMHUB_SOC_TLB2_40 regMP0_MMHUB_SOC_TLB2_40; -typedef union MP0_MMHUB_SOC_TLB2_41 regMP0_MMHUB_SOC_TLB2_41; -typedef union MP0_MMHUB_SOC_TLB2_42 regMP0_MMHUB_SOC_TLB2_42; -typedef union MP0_MMHUB_SOC_TLB2_43 regMP0_MMHUB_SOC_TLB2_43; -typedef union MP0_MMHUB_SOC_TLB2_44 regMP0_MMHUB_SOC_TLB2_44; -typedef union MP0_MMHUB_SOC_TLB2_45 regMP0_MMHUB_SOC_TLB2_45; -typedef union MP0_MMHUB_SOC_TLB2_46 regMP0_MMHUB_SOC_TLB2_46; -typedef union MP0_MMHUB_SOC_TLB2_47 regMP0_MMHUB_SOC_TLB2_47; -typedef union MP0_MMHUB_SOC_TLB2_48 regMP0_MMHUB_SOC_TLB2_48; -typedef union MP0_MMHUB_SOC_TLB2_49 regMP0_MMHUB_SOC_TLB2_49; -typedef union MP0_MMHUB_SOC_TLB2_50 regMP0_MMHUB_SOC_TLB2_50; -typedef union MP0_MMHUB_SOC_TLB2_51 regMP0_MMHUB_SOC_TLB2_51; -typedef union MP0_MMHUB_SOC_TLB2_52 regMP0_MMHUB_SOC_TLB2_52; -typedef union MP0_MMHUB_SOC_TLB2_53 regMP0_MMHUB_SOC_TLB2_53; -typedef union MP0_MMHUB_SOC_TLB2_54 regMP0_MMHUB_SOC_TLB2_54; -typedef union MP0_MMHUB_SOC_TLB2_55 regMP0_MMHUB_SOC_TLB2_55; -typedef union MP0_MMHUB_SOC_TLB2_56 regMP0_MMHUB_SOC_TLB2_56; -typedef union MP0_MMHUB_SOC_TLB2_57 regMP0_MMHUB_SOC_TLB2_57; -typedef union MP0_MMHUB_SOC_TLB2_58 regMP0_MMHUB_SOC_TLB2_58; -typedef union MP0_MMHUB_SOC_TLB2_59 regMP0_MMHUB_SOC_TLB2_59; -typedef union MP0_MMHUB_SOC_TLB2_60 regMP0_MMHUB_SOC_TLB2_60; -typedef union MP0_MMHUB_SOC_TLB2_61 regMP0_MMHUB_SOC_TLB2_61; -typedef union MP0_MMHUB_SOC_TLB2_62 regMP0_MMHUB_SOC_TLB2_62; -typedef union MP0_MMHUB_SOC_TLB3_1 regMP0_MMHUB_SOC_TLB3_1; -typedef union MP0_MMHUB_SOC_TLB3_2 regMP0_MMHUB_SOC_TLB3_2; -typedef union MP0_MMHUB_SOC_TLB3_3 regMP0_MMHUB_SOC_TLB3_3; -typedef union MP0_MMHUB_SOC_TLB3_4 regMP0_MMHUB_SOC_TLB3_4; -typedef union MP0_MMHUB_SOC_TLB3_5 regMP0_MMHUB_SOC_TLB3_5; -typedef union MP0_MMHUB_SOC_TLB3_6 regMP0_MMHUB_SOC_TLB3_6; -typedef union MP0_MMHUB_SOC_TLB3_7 regMP0_MMHUB_SOC_TLB3_7; -typedef union MP0_MMHUB_SOC_TLB3_8 regMP0_MMHUB_SOC_TLB3_8; -typedef union MP0_MMHUB_SOC_TLB3_9 regMP0_MMHUB_SOC_TLB3_9; -typedef union MP0_MMHUB_SOC_TLB3_10 regMP0_MMHUB_SOC_TLB3_10; -typedef union MP0_MMHUB_SOC_TLB3_11 regMP0_MMHUB_SOC_TLB3_11; -typedef union MP0_MMHUB_SOC_TLB3_12 regMP0_MMHUB_SOC_TLB3_12; -typedef union MP0_MMHUB_SOC_TLB3_13 regMP0_MMHUB_SOC_TLB3_13; -typedef union MP0_MMHUB_SOC_TLB3_14 regMP0_MMHUB_SOC_TLB3_14; -typedef union MP0_MMHUB_SOC_TLB3_15 regMP0_MMHUB_SOC_TLB3_15; -typedef union MP0_MMHUB_SOC_TLB3_16 regMP0_MMHUB_SOC_TLB3_16; -typedef union MP0_MMHUB_SOC_TLB3_17 regMP0_MMHUB_SOC_TLB3_17; -typedef union MP0_MMHUB_SOC_TLB3_18 regMP0_MMHUB_SOC_TLB3_18; -typedef union MP0_MMHUB_SOC_TLB3_19 regMP0_MMHUB_SOC_TLB3_19; -typedef union MP0_MMHUB_SOC_TLB3_20 regMP0_MMHUB_SOC_TLB3_20; -typedef union MP0_MMHUB_SOC_TLB3_21 regMP0_MMHUB_SOC_TLB3_21; -typedef union MP0_MMHUB_SOC_TLB3_22 regMP0_MMHUB_SOC_TLB3_22; -typedef union MP0_MMHUB_SOC_TLB3_23 regMP0_MMHUB_SOC_TLB3_23; -typedef union MP0_MMHUB_SOC_TLB3_24 regMP0_MMHUB_SOC_TLB3_24; -typedef union MP0_MMHUB_SOC_TLB3_25 regMP0_MMHUB_SOC_TLB3_25; -typedef union MP0_MMHUB_SOC_TLB3_26 regMP0_MMHUB_SOC_TLB3_26; -typedef union MP0_MMHUB_SOC_TLB3_27 regMP0_MMHUB_SOC_TLB3_27; -typedef union MP0_MMHUB_SOC_TLB3_28 regMP0_MMHUB_SOC_TLB3_28; -typedef union MP0_MMHUB_SOC_TLB3_29 regMP0_MMHUB_SOC_TLB3_29; -typedef union MP0_MMHUB_SOC_TLB3_30 regMP0_MMHUB_SOC_TLB3_30; -typedef union MP0_MMHUB_SOC_TLB3_31 regMP0_MMHUB_SOC_TLB3_31; -typedef union MP0_MMHUB_SOC_TLB3_32 regMP0_MMHUB_SOC_TLB3_32; -typedef union MP0_MMHUB_SOC_TLB3_33 regMP0_MMHUB_SOC_TLB3_33; -typedef union MP0_MMHUB_SOC_TLB3_34 regMP0_MMHUB_SOC_TLB3_34; -typedef union MP0_MMHUB_SOC_TLB3_35 regMP0_MMHUB_SOC_TLB3_35; -typedef union MP0_MMHUB_SOC_TLB3_36 regMP0_MMHUB_SOC_TLB3_36; -typedef union MP0_MMHUB_SOC_TLB3_37 regMP0_MMHUB_SOC_TLB3_37; -typedef union MP0_MMHUB_SOC_TLB3_38 regMP0_MMHUB_SOC_TLB3_38; -typedef union MP0_MMHUB_SOC_TLB3_39 regMP0_MMHUB_SOC_TLB3_39; -typedef union MP0_MMHUB_SOC_TLB3_40 regMP0_MMHUB_SOC_TLB3_40; -typedef union MP0_MMHUB_SOC_TLB3_41 regMP0_MMHUB_SOC_TLB3_41; -typedef union MP0_MMHUB_SOC_TLB3_42 regMP0_MMHUB_SOC_TLB3_42; -typedef union MP0_MMHUB_SOC_TLB3_43 regMP0_MMHUB_SOC_TLB3_43; -typedef union MP0_MMHUB_SOC_TLB3_44 regMP0_MMHUB_SOC_TLB3_44; -typedef union MP0_MMHUB_SOC_TLB3_45 regMP0_MMHUB_SOC_TLB3_45; -typedef union MP0_MMHUB_SOC_TLB3_46 regMP0_MMHUB_SOC_TLB3_46; -typedef union MP0_MMHUB_SOC_TLB3_47 regMP0_MMHUB_SOC_TLB3_47; -typedef union MP0_MMHUB_SOC_TLB3_48 regMP0_MMHUB_SOC_TLB3_48; -typedef union MP0_MMHUB_SOC_TLB3_49 regMP0_MMHUB_SOC_TLB3_49; -typedef union MP0_MMHUB_SOC_TLB3_50 regMP0_MMHUB_SOC_TLB3_50; -typedef union MP0_MMHUB_SOC_TLB3_51 regMP0_MMHUB_SOC_TLB3_51; -typedef union MP0_MMHUB_SOC_TLB3_52 regMP0_MMHUB_SOC_TLB3_52; -typedef union MP0_MMHUB_SOC_TLB3_53 regMP0_MMHUB_SOC_TLB3_53; -typedef union MP0_MMHUB_SOC_TLB3_54 regMP0_MMHUB_SOC_TLB3_54; -typedef union MP0_MMHUB_SOC_TLB3_55 regMP0_MMHUB_SOC_TLB3_55; -typedef union MP0_MMHUB_SOC_TLB3_56 regMP0_MMHUB_SOC_TLB3_56; -typedef union MP0_MMHUB_SOC_TLB3_57 regMP0_MMHUB_SOC_TLB3_57; -typedef union MP0_MMHUB_SOC_TLB3_58 regMP0_MMHUB_SOC_TLB3_58; -typedef union MP0_MMHUB_SOC_TLB3_59 regMP0_MMHUB_SOC_TLB3_59; -typedef union MP0_MMHUB_SOC_TLB3_60 regMP0_MMHUB_SOC_TLB3_60; -typedef union MP0_MMHUB_SOC_TLB3_61 regMP0_MMHUB_SOC_TLB3_61; -typedef union MP0_MMHUB_SOC_TLB3_62 regMP0_MMHUB_SOC_TLB3_62; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61; -typedef union MP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 regMP0_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_1 regMP0_MMHUB_TLB_ATTRIBUTE_1; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_2 regMP0_MMHUB_TLB_ATTRIBUTE_2; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_3 regMP0_MMHUB_TLB_ATTRIBUTE_3; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_4 regMP0_MMHUB_TLB_ATTRIBUTE_4; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_5 regMP0_MMHUB_TLB_ATTRIBUTE_5; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_6 regMP0_MMHUB_TLB_ATTRIBUTE_6; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_7 regMP0_MMHUB_TLB_ATTRIBUTE_7; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_8 regMP0_MMHUB_TLB_ATTRIBUTE_8; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_9 regMP0_MMHUB_TLB_ATTRIBUTE_9; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_10 regMP0_MMHUB_TLB_ATTRIBUTE_10; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_11 regMP0_MMHUB_TLB_ATTRIBUTE_11; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_12 regMP0_MMHUB_TLB_ATTRIBUTE_12; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_13 regMP0_MMHUB_TLB_ATTRIBUTE_13; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_14 regMP0_MMHUB_TLB_ATTRIBUTE_14; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_15 regMP0_MMHUB_TLB_ATTRIBUTE_15; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_16 regMP0_MMHUB_TLB_ATTRIBUTE_16; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_17 regMP0_MMHUB_TLB_ATTRIBUTE_17; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_18 regMP0_MMHUB_TLB_ATTRIBUTE_18; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_19 regMP0_MMHUB_TLB_ATTRIBUTE_19; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_20 regMP0_MMHUB_TLB_ATTRIBUTE_20; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_21 regMP0_MMHUB_TLB_ATTRIBUTE_21; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_22 regMP0_MMHUB_TLB_ATTRIBUTE_22; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_23 regMP0_MMHUB_TLB_ATTRIBUTE_23; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_24 regMP0_MMHUB_TLB_ATTRIBUTE_24; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_25 regMP0_MMHUB_TLB_ATTRIBUTE_25; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_26 regMP0_MMHUB_TLB_ATTRIBUTE_26; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_27 regMP0_MMHUB_TLB_ATTRIBUTE_27; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_28 regMP0_MMHUB_TLB_ATTRIBUTE_28; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_29 regMP0_MMHUB_TLB_ATTRIBUTE_29; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_30 regMP0_MMHUB_TLB_ATTRIBUTE_30; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_31 regMP0_MMHUB_TLB_ATTRIBUTE_31; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_32 regMP0_MMHUB_TLB_ATTRIBUTE_32; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_33 regMP0_MMHUB_TLB_ATTRIBUTE_33; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_34 regMP0_MMHUB_TLB_ATTRIBUTE_34; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_35 regMP0_MMHUB_TLB_ATTRIBUTE_35; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_36 regMP0_MMHUB_TLB_ATTRIBUTE_36; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_37 regMP0_MMHUB_TLB_ATTRIBUTE_37; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_38 regMP0_MMHUB_TLB_ATTRIBUTE_38; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_39 regMP0_MMHUB_TLB_ATTRIBUTE_39; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_40 regMP0_MMHUB_TLB_ATTRIBUTE_40; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_41 regMP0_MMHUB_TLB_ATTRIBUTE_41; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_42 regMP0_MMHUB_TLB_ATTRIBUTE_42; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_43 regMP0_MMHUB_TLB_ATTRIBUTE_43; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_44 regMP0_MMHUB_TLB_ATTRIBUTE_44; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_45 regMP0_MMHUB_TLB_ATTRIBUTE_45; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_46 regMP0_MMHUB_TLB_ATTRIBUTE_46; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_47 regMP0_MMHUB_TLB_ATTRIBUTE_47; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_48 regMP0_MMHUB_TLB_ATTRIBUTE_48; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_49 regMP0_MMHUB_TLB_ATTRIBUTE_49; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_50 regMP0_MMHUB_TLB_ATTRIBUTE_50; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_51 regMP0_MMHUB_TLB_ATTRIBUTE_51; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_52 regMP0_MMHUB_TLB_ATTRIBUTE_52; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_53 regMP0_MMHUB_TLB_ATTRIBUTE_53; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_54 regMP0_MMHUB_TLB_ATTRIBUTE_54; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_55 regMP0_MMHUB_TLB_ATTRIBUTE_55; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_56 regMP0_MMHUB_TLB_ATTRIBUTE_56; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_57 regMP0_MMHUB_TLB_ATTRIBUTE_57; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_58 regMP0_MMHUB_TLB_ATTRIBUTE_58; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_59 regMP0_MMHUB_TLB_ATTRIBUTE_59; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_60 regMP0_MMHUB_TLB_ATTRIBUTE_60; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_61 regMP0_MMHUB_TLB_ATTRIBUTE_61; -typedef union MP0_MMHUB_TLB_ATTRIBUTE_62 regMP0_MMHUB_TLB_ATTRIBUTE_62; -typedef union MP0_MMHUB_INT_STATUS regMP0_MMHUB_INT_STATUS; -typedef union MP0_MMHUB_WR_INT_ADDR regMP0_MMHUB_WR_INT_ADDR; -typedef union MP0_MMHUB_WR_INT_OTHER regMP0_MMHUB_WR_INT_OTHER; -typedef union MP0_MMHUB_RD_INT_ADDR regMP0_MMHUB_RD_INT_ADDR; -typedef union MP0_MMHUB_RD_INT_OTHER regMP0_MMHUB_RD_INT_OTHER; -typedef union MP0_MMHUB_REG_INT_ADDR regMP0_MMHUB_REG_INT_ADDR; -typedef union MP0_MMHUB_REG_INT_OTHER regMP0_MMHUB_REG_INT_OTHER; -typedef union MP0_MMHUB_AXCACHE_CFG regMP0_MMHUB_AXCACHE_CFG; -typedef union MP0_MMHUB_DS_OVERRIDE regMP0_MMHUB_DS_OVERRIDE; -typedef union MP0_MMHUB_OUTSTANDING regMP0_MMHUB_OUTSTANDING; -typedef union MP0_SYSHUB_SOC_TLB0_1 regMP0_SYSHUB_SOC_TLB0_1; -typedef union MP0_SYSHUB_SOC_TLB0_2 regMP0_SYSHUB_SOC_TLB0_2; -typedef union MP0_SYSHUB_SOC_TLB0_3 regMP0_SYSHUB_SOC_TLB0_3; -typedef union MP0_SYSHUB_SOC_TLB0_4 regMP0_SYSHUB_SOC_TLB0_4; -typedef union MP0_SYSHUB_SOC_TLB0_5 regMP0_SYSHUB_SOC_TLB0_5; -typedef union MP0_SYSHUB_SOC_TLB0_6 regMP0_SYSHUB_SOC_TLB0_6; -typedef union MP0_SYSHUB_SOC_TLB0_7 regMP0_SYSHUB_SOC_TLB0_7; -typedef union MP0_SYSHUB_SOC_TLB0_8 regMP0_SYSHUB_SOC_TLB0_8; -typedef union MP0_SYSHUB_SOC_TLB0_9 regMP0_SYSHUB_SOC_TLB0_9; -typedef union MP0_SYSHUB_SOC_TLB0_10 regMP0_SYSHUB_SOC_TLB0_10; -typedef union MP0_SYSHUB_SOC_TLB0_11 regMP0_SYSHUB_SOC_TLB0_11; -typedef union MP0_SYSHUB_SOC_TLB0_12 regMP0_SYSHUB_SOC_TLB0_12; -typedef union MP0_SYSHUB_SOC_TLB0_13 regMP0_SYSHUB_SOC_TLB0_13; -typedef union MP0_SYSHUB_SOC_TLB0_14 regMP0_SYSHUB_SOC_TLB0_14; -typedef union MP0_SYSHUB_SOC_TLB0_15 regMP0_SYSHUB_SOC_TLB0_15; -typedef union MP0_SYSHUB_SOC_TLB0_16 regMP0_SYSHUB_SOC_TLB0_16; -typedef union MP0_SYSHUB_SOC_TLB0_17 regMP0_SYSHUB_SOC_TLB0_17; -typedef union MP0_SYSHUB_SOC_TLB0_18 regMP0_SYSHUB_SOC_TLB0_18; -typedef union MP0_SYSHUB_SOC_TLB0_19 regMP0_SYSHUB_SOC_TLB0_19; -typedef union MP0_SYSHUB_SOC_TLB0_20 regMP0_SYSHUB_SOC_TLB0_20; -typedef union MP0_SYSHUB_SOC_TLB0_21 regMP0_SYSHUB_SOC_TLB0_21; -typedef union MP0_SYSHUB_SOC_TLB0_22 regMP0_SYSHUB_SOC_TLB0_22; -typedef union MP0_SYSHUB_SOC_TLB0_23 regMP0_SYSHUB_SOC_TLB0_23; -typedef union MP0_SYSHUB_SOC_TLB0_24 regMP0_SYSHUB_SOC_TLB0_24; -typedef union MP0_SYSHUB_SOC_TLB0_25 regMP0_SYSHUB_SOC_TLB0_25; -typedef union MP0_SYSHUB_SOC_TLB0_26 regMP0_SYSHUB_SOC_TLB0_26; -typedef union MP0_SYSHUB_SOC_TLB0_27 regMP0_SYSHUB_SOC_TLB0_27; -typedef union MP0_SYSHUB_SOC_TLB0_28 regMP0_SYSHUB_SOC_TLB0_28; -typedef union MP0_SYSHUB_SOC_TLB0_29 regMP0_SYSHUB_SOC_TLB0_29; -typedef union MP0_SYSHUB_SOC_TLB0_30 regMP0_SYSHUB_SOC_TLB0_30; -typedef union MP0_SYSHUB_SOC_TLB0_31 regMP0_SYSHUB_SOC_TLB0_31; -typedef union MP0_SYSHUB_SOC_TLB0_32 regMP0_SYSHUB_SOC_TLB0_32; -typedef union MP0_SYSHUB_SOC_TLB0_33 regMP0_SYSHUB_SOC_TLB0_33; -typedef union MP0_SYSHUB_SOC_TLB0_34 regMP0_SYSHUB_SOC_TLB0_34; -typedef union MP0_SYSHUB_SOC_TLB0_35 regMP0_SYSHUB_SOC_TLB0_35; -typedef union MP0_SYSHUB_SOC_TLB0_36 regMP0_SYSHUB_SOC_TLB0_36; -typedef union MP0_SYSHUB_SOC_TLB0_37 regMP0_SYSHUB_SOC_TLB0_37; -typedef union MP0_SYSHUB_SOC_TLB0_38 regMP0_SYSHUB_SOC_TLB0_38; -typedef union MP0_SYSHUB_SOC_TLB0_39 regMP0_SYSHUB_SOC_TLB0_39; -typedef union MP0_SYSHUB_SOC_TLB0_40 regMP0_SYSHUB_SOC_TLB0_40; -typedef union MP0_SYSHUB_SOC_TLB0_41 regMP0_SYSHUB_SOC_TLB0_41; -typedef union MP0_SYSHUB_SOC_TLB0_42 regMP0_SYSHUB_SOC_TLB0_42; -typedef union MP0_SYSHUB_SOC_TLB0_43 regMP0_SYSHUB_SOC_TLB0_43; -typedef union MP0_SYSHUB_SOC_TLB0_44 regMP0_SYSHUB_SOC_TLB0_44; -typedef union MP0_SYSHUB_SOC_TLB0_45 regMP0_SYSHUB_SOC_TLB0_45; -typedef union MP0_SYSHUB_SOC_TLB0_46 regMP0_SYSHUB_SOC_TLB0_46; -typedef union MP0_SYSHUB_SOC_TLB0_47 regMP0_SYSHUB_SOC_TLB0_47; -typedef union MP0_SYSHUB_SOC_TLB0_48 regMP0_SYSHUB_SOC_TLB0_48; -typedef union MP0_SYSHUB_SOC_TLB0_49 regMP0_SYSHUB_SOC_TLB0_49; -typedef union MP0_SYSHUB_SOC_TLB0_50 regMP0_SYSHUB_SOC_TLB0_50; -typedef union MP0_SYSHUB_SOC_TLB0_51 regMP0_SYSHUB_SOC_TLB0_51; -typedef union MP0_SYSHUB_SOC_TLB0_52 regMP0_SYSHUB_SOC_TLB0_52; -typedef union MP0_SYSHUB_SOC_TLB0_53 regMP0_SYSHUB_SOC_TLB0_53; -typedef union MP0_SYSHUB_SOC_TLB0_54 regMP0_SYSHUB_SOC_TLB0_54; -typedef union MP0_SYSHUB_SOC_TLB0_55 regMP0_SYSHUB_SOC_TLB0_55; -typedef union MP0_SYSHUB_SOC_TLB0_56 regMP0_SYSHUB_SOC_TLB0_56; -typedef union MP0_SYSHUB_SOC_TLB0_57 regMP0_SYSHUB_SOC_TLB0_57; -typedef union MP0_SYSHUB_SOC_TLB0_58 regMP0_SYSHUB_SOC_TLB0_58; -typedef union MP0_SYSHUB_SOC_TLB0_59 regMP0_SYSHUB_SOC_TLB0_59; -typedef union MP0_SYSHUB_SOC_TLB0_60 regMP0_SYSHUB_SOC_TLB0_60; -typedef union MP0_SYSHUB_SOC_TLB0_61 regMP0_SYSHUB_SOC_TLB0_61; -typedef union MP0_SYSHUB_SOC_TLB0_62 regMP0_SYSHUB_SOC_TLB0_62; -typedef union MP0_SYSHUB_SOC_TLB1_1 regMP0_SYSHUB_SOC_TLB1_1; -typedef union MP0_SYSHUB_SOC_TLB1_2 regMP0_SYSHUB_SOC_TLB1_2; -typedef union MP0_SYSHUB_SOC_TLB1_3 regMP0_SYSHUB_SOC_TLB1_3; -typedef union MP0_SYSHUB_SOC_TLB1_4 regMP0_SYSHUB_SOC_TLB1_4; -typedef union MP0_SYSHUB_SOC_TLB1_5 regMP0_SYSHUB_SOC_TLB1_5; -typedef union MP0_SYSHUB_SOC_TLB1_6 regMP0_SYSHUB_SOC_TLB1_6; -typedef union MP0_SYSHUB_SOC_TLB1_7 regMP0_SYSHUB_SOC_TLB1_7; -typedef union MP0_SYSHUB_SOC_TLB1_8 regMP0_SYSHUB_SOC_TLB1_8; -typedef union MP0_SYSHUB_SOC_TLB1_9 regMP0_SYSHUB_SOC_TLB1_9; -typedef union MP0_SYSHUB_SOC_TLB1_10 regMP0_SYSHUB_SOC_TLB1_10; -typedef union MP0_SYSHUB_SOC_TLB1_11 regMP0_SYSHUB_SOC_TLB1_11; -typedef union MP0_SYSHUB_SOC_TLB1_12 regMP0_SYSHUB_SOC_TLB1_12; -typedef union MP0_SYSHUB_SOC_TLB1_13 regMP0_SYSHUB_SOC_TLB1_13; -typedef union MP0_SYSHUB_SOC_TLB1_14 regMP0_SYSHUB_SOC_TLB1_14; -typedef union MP0_SYSHUB_SOC_TLB1_15 regMP0_SYSHUB_SOC_TLB1_15; -typedef union MP0_SYSHUB_SOC_TLB1_16 regMP0_SYSHUB_SOC_TLB1_16; -typedef union MP0_SYSHUB_SOC_TLB1_17 regMP0_SYSHUB_SOC_TLB1_17; -typedef union MP0_SYSHUB_SOC_TLB1_18 regMP0_SYSHUB_SOC_TLB1_18; -typedef union MP0_SYSHUB_SOC_TLB1_19 regMP0_SYSHUB_SOC_TLB1_19; -typedef union MP0_SYSHUB_SOC_TLB1_20 regMP0_SYSHUB_SOC_TLB1_20; -typedef union MP0_SYSHUB_SOC_TLB1_21 regMP0_SYSHUB_SOC_TLB1_21; -typedef union MP0_SYSHUB_SOC_TLB1_22 regMP0_SYSHUB_SOC_TLB1_22; -typedef union MP0_SYSHUB_SOC_TLB1_23 regMP0_SYSHUB_SOC_TLB1_23; -typedef union MP0_SYSHUB_SOC_TLB1_24 regMP0_SYSHUB_SOC_TLB1_24; -typedef union MP0_SYSHUB_SOC_TLB1_25 regMP0_SYSHUB_SOC_TLB1_25; -typedef union MP0_SYSHUB_SOC_TLB1_26 regMP0_SYSHUB_SOC_TLB1_26; -typedef union MP0_SYSHUB_SOC_TLB1_27 regMP0_SYSHUB_SOC_TLB1_27; -typedef union MP0_SYSHUB_SOC_TLB1_28 regMP0_SYSHUB_SOC_TLB1_28; -typedef union MP0_SYSHUB_SOC_TLB1_29 regMP0_SYSHUB_SOC_TLB1_29; -typedef union MP0_SYSHUB_SOC_TLB1_30 regMP0_SYSHUB_SOC_TLB1_30; -typedef union MP0_SYSHUB_SOC_TLB1_31 regMP0_SYSHUB_SOC_TLB1_31; -typedef union MP0_SYSHUB_SOC_TLB1_32 regMP0_SYSHUB_SOC_TLB1_32; -typedef union MP0_SYSHUB_SOC_TLB1_33 regMP0_SYSHUB_SOC_TLB1_33; -typedef union MP0_SYSHUB_SOC_TLB1_34 regMP0_SYSHUB_SOC_TLB1_34; -typedef union MP0_SYSHUB_SOC_TLB1_35 regMP0_SYSHUB_SOC_TLB1_35; -typedef union MP0_SYSHUB_SOC_TLB1_36 regMP0_SYSHUB_SOC_TLB1_36; -typedef union MP0_SYSHUB_SOC_TLB1_37 regMP0_SYSHUB_SOC_TLB1_37; -typedef union MP0_SYSHUB_SOC_TLB1_38 regMP0_SYSHUB_SOC_TLB1_38; -typedef union MP0_SYSHUB_SOC_TLB1_39 regMP0_SYSHUB_SOC_TLB1_39; -typedef union MP0_SYSHUB_SOC_TLB1_40 regMP0_SYSHUB_SOC_TLB1_40; -typedef union MP0_SYSHUB_SOC_TLB1_41 regMP0_SYSHUB_SOC_TLB1_41; -typedef union MP0_SYSHUB_SOC_TLB1_42 regMP0_SYSHUB_SOC_TLB1_42; -typedef union MP0_SYSHUB_SOC_TLB1_43 regMP0_SYSHUB_SOC_TLB1_43; -typedef union MP0_SYSHUB_SOC_TLB1_44 regMP0_SYSHUB_SOC_TLB1_44; -typedef union MP0_SYSHUB_SOC_TLB1_45 regMP0_SYSHUB_SOC_TLB1_45; -typedef union MP0_SYSHUB_SOC_TLB1_46 regMP0_SYSHUB_SOC_TLB1_46; -typedef union MP0_SYSHUB_SOC_TLB1_47 regMP0_SYSHUB_SOC_TLB1_47; -typedef union MP0_SYSHUB_SOC_TLB1_48 regMP0_SYSHUB_SOC_TLB1_48; -typedef union MP0_SYSHUB_SOC_TLB1_49 regMP0_SYSHUB_SOC_TLB1_49; -typedef union MP0_SYSHUB_SOC_TLB1_50 regMP0_SYSHUB_SOC_TLB1_50; -typedef union MP0_SYSHUB_SOC_TLB1_51 regMP0_SYSHUB_SOC_TLB1_51; -typedef union MP0_SYSHUB_SOC_TLB1_52 regMP0_SYSHUB_SOC_TLB1_52; -typedef union MP0_SYSHUB_SOC_TLB1_53 regMP0_SYSHUB_SOC_TLB1_53; -typedef union MP0_SYSHUB_SOC_TLB1_54 regMP0_SYSHUB_SOC_TLB1_54; -typedef union MP0_SYSHUB_SOC_TLB1_55 regMP0_SYSHUB_SOC_TLB1_55; -typedef union MP0_SYSHUB_SOC_TLB1_56 regMP0_SYSHUB_SOC_TLB1_56; -typedef union MP0_SYSHUB_SOC_TLB1_57 regMP0_SYSHUB_SOC_TLB1_57; -typedef union MP0_SYSHUB_SOC_TLB1_58 regMP0_SYSHUB_SOC_TLB1_58; -typedef union MP0_SYSHUB_SOC_TLB1_59 regMP0_SYSHUB_SOC_TLB1_59; -typedef union MP0_SYSHUB_SOC_TLB1_60 regMP0_SYSHUB_SOC_TLB1_60; -typedef union MP0_SYSHUB_SOC_TLB1_61 regMP0_SYSHUB_SOC_TLB1_61; -typedef union MP0_SYSHUB_SOC_TLB1_62 regMP0_SYSHUB_SOC_TLB1_62; -typedef union MP0_SYSHUB_SOC_TLB2_1 regMP0_SYSHUB_SOC_TLB2_1; -typedef union MP0_SYSHUB_SOC_TLB2_2 regMP0_SYSHUB_SOC_TLB2_2; -typedef union MP0_SYSHUB_SOC_TLB2_3 regMP0_SYSHUB_SOC_TLB2_3; -typedef union MP0_SYSHUB_SOC_TLB2_4 regMP0_SYSHUB_SOC_TLB2_4; -typedef union MP0_SYSHUB_SOC_TLB2_5 regMP0_SYSHUB_SOC_TLB2_5; -typedef union MP0_SYSHUB_SOC_TLB2_6 regMP0_SYSHUB_SOC_TLB2_6; -typedef union MP0_SYSHUB_SOC_TLB2_7 regMP0_SYSHUB_SOC_TLB2_7; -typedef union MP0_SYSHUB_SOC_TLB2_8 regMP0_SYSHUB_SOC_TLB2_8; -typedef union MP0_SYSHUB_SOC_TLB2_9 regMP0_SYSHUB_SOC_TLB2_9; -typedef union MP0_SYSHUB_SOC_TLB2_10 regMP0_SYSHUB_SOC_TLB2_10; -typedef union MP0_SYSHUB_SOC_TLB2_11 regMP0_SYSHUB_SOC_TLB2_11; -typedef union MP0_SYSHUB_SOC_TLB2_12 regMP0_SYSHUB_SOC_TLB2_12; -typedef union MP0_SYSHUB_SOC_TLB2_13 regMP0_SYSHUB_SOC_TLB2_13; -typedef union MP0_SYSHUB_SOC_TLB2_14 regMP0_SYSHUB_SOC_TLB2_14; -typedef union MP0_SYSHUB_SOC_TLB2_15 regMP0_SYSHUB_SOC_TLB2_15; -typedef union MP0_SYSHUB_SOC_TLB2_16 regMP0_SYSHUB_SOC_TLB2_16; -typedef union MP0_SYSHUB_SOC_TLB2_17 regMP0_SYSHUB_SOC_TLB2_17; -typedef union MP0_SYSHUB_SOC_TLB2_18 regMP0_SYSHUB_SOC_TLB2_18; -typedef union MP0_SYSHUB_SOC_TLB2_19 regMP0_SYSHUB_SOC_TLB2_19; -typedef union MP0_SYSHUB_SOC_TLB2_20 regMP0_SYSHUB_SOC_TLB2_20; -typedef union MP0_SYSHUB_SOC_TLB2_21 regMP0_SYSHUB_SOC_TLB2_21; -typedef union MP0_SYSHUB_SOC_TLB2_22 regMP0_SYSHUB_SOC_TLB2_22; -typedef union MP0_SYSHUB_SOC_TLB2_23 regMP0_SYSHUB_SOC_TLB2_23; -typedef union MP0_SYSHUB_SOC_TLB2_24 regMP0_SYSHUB_SOC_TLB2_24; -typedef union MP0_SYSHUB_SOC_TLB2_25 regMP0_SYSHUB_SOC_TLB2_25; -typedef union MP0_SYSHUB_SOC_TLB2_26 regMP0_SYSHUB_SOC_TLB2_26; -typedef union MP0_SYSHUB_SOC_TLB2_27 regMP0_SYSHUB_SOC_TLB2_27; -typedef union MP0_SYSHUB_SOC_TLB2_28 regMP0_SYSHUB_SOC_TLB2_28; -typedef union MP0_SYSHUB_SOC_TLB2_29 regMP0_SYSHUB_SOC_TLB2_29; -typedef union MP0_SYSHUB_SOC_TLB2_30 regMP0_SYSHUB_SOC_TLB2_30; -typedef union MP0_SYSHUB_SOC_TLB2_31 regMP0_SYSHUB_SOC_TLB2_31; -typedef union MP0_SYSHUB_SOC_TLB2_32 regMP0_SYSHUB_SOC_TLB2_32; -typedef union MP0_SYSHUB_SOC_TLB2_33 regMP0_SYSHUB_SOC_TLB2_33; -typedef union MP0_SYSHUB_SOC_TLB2_34 regMP0_SYSHUB_SOC_TLB2_34; -typedef union MP0_SYSHUB_SOC_TLB2_35 regMP0_SYSHUB_SOC_TLB2_35; -typedef union MP0_SYSHUB_SOC_TLB2_36 regMP0_SYSHUB_SOC_TLB2_36; -typedef union MP0_SYSHUB_SOC_TLB2_37 regMP0_SYSHUB_SOC_TLB2_37; -typedef union MP0_SYSHUB_SOC_TLB2_38 regMP0_SYSHUB_SOC_TLB2_38; -typedef union MP0_SYSHUB_SOC_TLB2_39 regMP0_SYSHUB_SOC_TLB2_39; -typedef union MP0_SYSHUB_SOC_TLB2_40 regMP0_SYSHUB_SOC_TLB2_40; -typedef union MP0_SYSHUB_SOC_TLB2_41 regMP0_SYSHUB_SOC_TLB2_41; -typedef union MP0_SYSHUB_SOC_TLB2_42 regMP0_SYSHUB_SOC_TLB2_42; -typedef union MP0_SYSHUB_SOC_TLB2_43 regMP0_SYSHUB_SOC_TLB2_43; -typedef union MP0_SYSHUB_SOC_TLB2_44 regMP0_SYSHUB_SOC_TLB2_44; -typedef union MP0_SYSHUB_SOC_TLB2_45 regMP0_SYSHUB_SOC_TLB2_45; -typedef union MP0_SYSHUB_SOC_TLB2_46 regMP0_SYSHUB_SOC_TLB2_46; -typedef union MP0_SYSHUB_SOC_TLB2_47 regMP0_SYSHUB_SOC_TLB2_47; -typedef union MP0_SYSHUB_SOC_TLB2_48 regMP0_SYSHUB_SOC_TLB2_48; -typedef union MP0_SYSHUB_SOC_TLB2_49 regMP0_SYSHUB_SOC_TLB2_49; -typedef union MP0_SYSHUB_SOC_TLB2_50 regMP0_SYSHUB_SOC_TLB2_50; -typedef union MP0_SYSHUB_SOC_TLB2_51 regMP0_SYSHUB_SOC_TLB2_51; -typedef union MP0_SYSHUB_SOC_TLB2_52 regMP0_SYSHUB_SOC_TLB2_52; -typedef union MP0_SYSHUB_SOC_TLB2_53 regMP0_SYSHUB_SOC_TLB2_53; -typedef union MP0_SYSHUB_SOC_TLB2_54 regMP0_SYSHUB_SOC_TLB2_54; -typedef union MP0_SYSHUB_SOC_TLB2_55 regMP0_SYSHUB_SOC_TLB2_55; -typedef union MP0_SYSHUB_SOC_TLB2_56 regMP0_SYSHUB_SOC_TLB2_56; -typedef union MP0_SYSHUB_SOC_TLB2_57 regMP0_SYSHUB_SOC_TLB2_57; -typedef union MP0_SYSHUB_SOC_TLB2_58 regMP0_SYSHUB_SOC_TLB2_58; -typedef union MP0_SYSHUB_SOC_TLB2_59 regMP0_SYSHUB_SOC_TLB2_59; -typedef union MP0_SYSHUB_SOC_TLB2_60 regMP0_SYSHUB_SOC_TLB2_60; -typedef union MP0_SYSHUB_SOC_TLB2_61 regMP0_SYSHUB_SOC_TLB2_61; -typedef union MP0_SYSHUB_SOC_TLB2_62 regMP0_SYSHUB_SOC_TLB2_62; -typedef union MP0_SYSHUB_SOC_TLB3_1 regMP0_SYSHUB_SOC_TLB3_1; -typedef union MP0_SYSHUB_SOC_TLB3_2 regMP0_SYSHUB_SOC_TLB3_2; -typedef union MP0_SYSHUB_SOC_TLB3_3 regMP0_SYSHUB_SOC_TLB3_3; -typedef union MP0_SYSHUB_SOC_TLB3_4 regMP0_SYSHUB_SOC_TLB3_4; -typedef union MP0_SYSHUB_SOC_TLB3_5 regMP0_SYSHUB_SOC_TLB3_5; -typedef union MP0_SYSHUB_SOC_TLB3_6 regMP0_SYSHUB_SOC_TLB3_6; -typedef union MP0_SYSHUB_SOC_TLB3_7 regMP0_SYSHUB_SOC_TLB3_7; -typedef union MP0_SYSHUB_SOC_TLB3_8 regMP0_SYSHUB_SOC_TLB3_8; -typedef union MP0_SYSHUB_SOC_TLB3_9 regMP0_SYSHUB_SOC_TLB3_9; -typedef union MP0_SYSHUB_SOC_TLB3_10 regMP0_SYSHUB_SOC_TLB3_10; -typedef union MP0_SYSHUB_SOC_TLB3_11 regMP0_SYSHUB_SOC_TLB3_11; -typedef union MP0_SYSHUB_SOC_TLB3_12 regMP0_SYSHUB_SOC_TLB3_12; -typedef union MP0_SYSHUB_SOC_TLB3_13 regMP0_SYSHUB_SOC_TLB3_13; -typedef union MP0_SYSHUB_SOC_TLB3_14 regMP0_SYSHUB_SOC_TLB3_14; -typedef union MP0_SYSHUB_SOC_TLB3_15 regMP0_SYSHUB_SOC_TLB3_15; -typedef union MP0_SYSHUB_SOC_TLB3_16 regMP0_SYSHUB_SOC_TLB3_16; -typedef union MP0_SYSHUB_SOC_TLB3_17 regMP0_SYSHUB_SOC_TLB3_17; -typedef union MP0_SYSHUB_SOC_TLB3_18 regMP0_SYSHUB_SOC_TLB3_18; -typedef union MP0_SYSHUB_SOC_TLB3_19 regMP0_SYSHUB_SOC_TLB3_19; -typedef union MP0_SYSHUB_SOC_TLB3_20 regMP0_SYSHUB_SOC_TLB3_20; -typedef union MP0_SYSHUB_SOC_TLB3_21 regMP0_SYSHUB_SOC_TLB3_21; -typedef union MP0_SYSHUB_SOC_TLB3_22 regMP0_SYSHUB_SOC_TLB3_22; -typedef union MP0_SYSHUB_SOC_TLB3_23 regMP0_SYSHUB_SOC_TLB3_23; -typedef union MP0_SYSHUB_SOC_TLB3_24 regMP0_SYSHUB_SOC_TLB3_24; -typedef union MP0_SYSHUB_SOC_TLB3_25 regMP0_SYSHUB_SOC_TLB3_25; -typedef union MP0_SYSHUB_SOC_TLB3_26 regMP0_SYSHUB_SOC_TLB3_26; -typedef union MP0_SYSHUB_SOC_TLB3_27 regMP0_SYSHUB_SOC_TLB3_27; -typedef union MP0_SYSHUB_SOC_TLB3_28 regMP0_SYSHUB_SOC_TLB3_28; -typedef union MP0_SYSHUB_SOC_TLB3_29 regMP0_SYSHUB_SOC_TLB3_29; -typedef union MP0_SYSHUB_SOC_TLB3_30 regMP0_SYSHUB_SOC_TLB3_30; -typedef union MP0_SYSHUB_SOC_TLB3_31 regMP0_SYSHUB_SOC_TLB3_31; -typedef union MP0_SYSHUB_SOC_TLB3_32 regMP0_SYSHUB_SOC_TLB3_32; -typedef union MP0_SYSHUB_SOC_TLB3_33 regMP0_SYSHUB_SOC_TLB3_33; -typedef union MP0_SYSHUB_SOC_TLB3_34 regMP0_SYSHUB_SOC_TLB3_34; -typedef union MP0_SYSHUB_SOC_TLB3_35 regMP0_SYSHUB_SOC_TLB3_35; -typedef union MP0_SYSHUB_SOC_TLB3_36 regMP0_SYSHUB_SOC_TLB3_36; -typedef union MP0_SYSHUB_SOC_TLB3_37 regMP0_SYSHUB_SOC_TLB3_37; -typedef union MP0_SYSHUB_SOC_TLB3_38 regMP0_SYSHUB_SOC_TLB3_38; -typedef union MP0_SYSHUB_SOC_TLB3_39 regMP0_SYSHUB_SOC_TLB3_39; -typedef union MP0_SYSHUB_SOC_TLB3_40 regMP0_SYSHUB_SOC_TLB3_40; -typedef union MP0_SYSHUB_SOC_TLB3_41 regMP0_SYSHUB_SOC_TLB3_41; -typedef union MP0_SYSHUB_SOC_TLB3_42 regMP0_SYSHUB_SOC_TLB3_42; -typedef union MP0_SYSHUB_SOC_TLB3_43 regMP0_SYSHUB_SOC_TLB3_43; -typedef union MP0_SYSHUB_SOC_TLB3_44 regMP0_SYSHUB_SOC_TLB3_44; -typedef union MP0_SYSHUB_SOC_TLB3_45 regMP0_SYSHUB_SOC_TLB3_45; -typedef union MP0_SYSHUB_SOC_TLB3_46 regMP0_SYSHUB_SOC_TLB3_46; -typedef union MP0_SYSHUB_SOC_TLB3_47 regMP0_SYSHUB_SOC_TLB3_47; -typedef union MP0_SYSHUB_SOC_TLB3_48 regMP0_SYSHUB_SOC_TLB3_48; -typedef union MP0_SYSHUB_SOC_TLB3_49 regMP0_SYSHUB_SOC_TLB3_49; -typedef union MP0_SYSHUB_SOC_TLB3_50 regMP0_SYSHUB_SOC_TLB3_50; -typedef union MP0_SYSHUB_SOC_TLB3_51 regMP0_SYSHUB_SOC_TLB3_51; -typedef union MP0_SYSHUB_SOC_TLB3_52 regMP0_SYSHUB_SOC_TLB3_52; -typedef union MP0_SYSHUB_SOC_TLB3_53 regMP0_SYSHUB_SOC_TLB3_53; -typedef union MP0_SYSHUB_SOC_TLB3_54 regMP0_SYSHUB_SOC_TLB3_54; -typedef union MP0_SYSHUB_SOC_TLB3_55 regMP0_SYSHUB_SOC_TLB3_55; -typedef union MP0_SYSHUB_SOC_TLB3_56 regMP0_SYSHUB_SOC_TLB3_56; -typedef union MP0_SYSHUB_SOC_TLB3_57 regMP0_SYSHUB_SOC_TLB3_57; -typedef union MP0_SYSHUB_SOC_TLB3_58 regMP0_SYSHUB_SOC_TLB3_58; -typedef union MP0_SYSHUB_SOC_TLB3_59 regMP0_SYSHUB_SOC_TLB3_59; -typedef union MP0_SYSHUB_SOC_TLB3_60 regMP0_SYSHUB_SOC_TLB3_60; -typedef union MP0_SYSHUB_SOC_TLB3_61 regMP0_SYSHUB_SOC_TLB3_61; -typedef union MP0_SYSHUB_SOC_TLB3_62 regMP0_SYSHUB_SOC_TLB3_62; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61; -typedef union MP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 regMP0_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_1 regMP0_SYSHUB_TLB_ATTRIBUTE_1; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_2 regMP0_SYSHUB_TLB_ATTRIBUTE_2; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_3 regMP0_SYSHUB_TLB_ATTRIBUTE_3; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_4 regMP0_SYSHUB_TLB_ATTRIBUTE_4; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_5 regMP0_SYSHUB_TLB_ATTRIBUTE_5; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_6 regMP0_SYSHUB_TLB_ATTRIBUTE_6; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_7 regMP0_SYSHUB_TLB_ATTRIBUTE_7; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_8 regMP0_SYSHUB_TLB_ATTRIBUTE_8; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_9 regMP0_SYSHUB_TLB_ATTRIBUTE_9; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_10 regMP0_SYSHUB_TLB_ATTRIBUTE_10; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_11 regMP0_SYSHUB_TLB_ATTRIBUTE_11; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_12 regMP0_SYSHUB_TLB_ATTRIBUTE_12; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_13 regMP0_SYSHUB_TLB_ATTRIBUTE_13; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_14 regMP0_SYSHUB_TLB_ATTRIBUTE_14; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_15 regMP0_SYSHUB_TLB_ATTRIBUTE_15; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_16 regMP0_SYSHUB_TLB_ATTRIBUTE_16; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_17 regMP0_SYSHUB_TLB_ATTRIBUTE_17; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_18 regMP0_SYSHUB_TLB_ATTRIBUTE_18; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_19 regMP0_SYSHUB_TLB_ATTRIBUTE_19; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_20 regMP0_SYSHUB_TLB_ATTRIBUTE_20; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_21 regMP0_SYSHUB_TLB_ATTRIBUTE_21; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_22 regMP0_SYSHUB_TLB_ATTRIBUTE_22; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_23 regMP0_SYSHUB_TLB_ATTRIBUTE_23; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_24 regMP0_SYSHUB_TLB_ATTRIBUTE_24; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_25 regMP0_SYSHUB_TLB_ATTRIBUTE_25; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_26 regMP0_SYSHUB_TLB_ATTRIBUTE_26; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_27 regMP0_SYSHUB_TLB_ATTRIBUTE_27; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_28 regMP0_SYSHUB_TLB_ATTRIBUTE_28; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_29 regMP0_SYSHUB_TLB_ATTRIBUTE_29; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_30 regMP0_SYSHUB_TLB_ATTRIBUTE_30; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_31 regMP0_SYSHUB_TLB_ATTRIBUTE_31; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_32 regMP0_SYSHUB_TLB_ATTRIBUTE_32; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_33 regMP0_SYSHUB_TLB_ATTRIBUTE_33; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_34 regMP0_SYSHUB_TLB_ATTRIBUTE_34; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_35 regMP0_SYSHUB_TLB_ATTRIBUTE_35; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_36 regMP0_SYSHUB_TLB_ATTRIBUTE_36; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_37 regMP0_SYSHUB_TLB_ATTRIBUTE_37; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_38 regMP0_SYSHUB_TLB_ATTRIBUTE_38; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_39 regMP0_SYSHUB_TLB_ATTRIBUTE_39; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_40 regMP0_SYSHUB_TLB_ATTRIBUTE_40; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_41 regMP0_SYSHUB_TLB_ATTRIBUTE_41; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_42 regMP0_SYSHUB_TLB_ATTRIBUTE_42; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_43 regMP0_SYSHUB_TLB_ATTRIBUTE_43; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_44 regMP0_SYSHUB_TLB_ATTRIBUTE_44; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_45 regMP0_SYSHUB_TLB_ATTRIBUTE_45; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_46 regMP0_SYSHUB_TLB_ATTRIBUTE_46; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_47 regMP0_SYSHUB_TLB_ATTRIBUTE_47; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_48 regMP0_SYSHUB_TLB_ATTRIBUTE_48; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_49 regMP0_SYSHUB_TLB_ATTRIBUTE_49; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_50 regMP0_SYSHUB_TLB_ATTRIBUTE_50; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_51 regMP0_SYSHUB_TLB_ATTRIBUTE_51; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_52 regMP0_SYSHUB_TLB_ATTRIBUTE_52; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_53 regMP0_SYSHUB_TLB_ATTRIBUTE_53; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_54 regMP0_SYSHUB_TLB_ATTRIBUTE_54; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_55 regMP0_SYSHUB_TLB_ATTRIBUTE_55; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_56 regMP0_SYSHUB_TLB_ATTRIBUTE_56; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_57 regMP0_SYSHUB_TLB_ATTRIBUTE_57; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_58 regMP0_SYSHUB_TLB_ATTRIBUTE_58; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_59 regMP0_SYSHUB_TLB_ATTRIBUTE_59; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_60 regMP0_SYSHUB_TLB_ATTRIBUTE_60; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_61 regMP0_SYSHUB_TLB_ATTRIBUTE_61; -typedef union MP0_SYSHUB_TLB_ATTRIBUTE_62 regMP0_SYSHUB_TLB_ATTRIBUTE_62; -typedef union MP0_SYSHUB_INT_STATUS regMP0_SYSHUB_INT_STATUS; -typedef union MP0_SYSHUB_WR_INT_ADDR regMP0_SYSHUB_WR_INT_ADDR; -typedef union MP0_SYSHUB_WR_INT_OTHER regMP0_SYSHUB_WR_INT_OTHER; -typedef union MP0_SYSHUB_RD_INT_ADDR regMP0_SYSHUB_RD_INT_ADDR; -typedef union MP0_SYSHUB_RD_INT_OTHER regMP0_SYSHUB_RD_INT_OTHER; -typedef union MP0_SYSHUB_REG_INT_ADDR regMP0_SYSHUB_REG_INT_ADDR; -typedef union MP0_SYSHUB_REG_INT_OTHER regMP0_SYSHUB_REG_INT_OTHER; -typedef union MP0_SYSHUB_AXCACHE_CFG regMP0_SYSHUB_AXCACHE_CFG; -typedef union MP0_SYSHUB_DS_OVERRIDE regMP0_SYSHUB_DS_OVERRIDE; -typedef union MP0_SYSHUB_OUTSTANDING regMP0_SYSHUB_OUTSTANDING; -typedef union MP1_SMNIF_ERROR regMP1_SMNIF_ERROR; -typedef union MP1_LX3_PDEBUGPC regMP1_LX3_PDEBUGPC; -typedef union MP1_LX3_PWAITMODE regMP1_LX3_PWAITMODE; -typedef union MP1_IH_MP0SW_INT_CTXID regMP1_IH_MP0SW_INT_CTXID; -typedef union MP1_IH_MP1SW_INT_CTXID regMP1_IH_MP1SW_INT_CTXID; -typedef union MP1_IH_DISP_TIMER_ID regMP1_IH_DISP_TIMER_ID; -typedef union MP1_FW_DEBUG_CNT0 regMP1_FW_DEBUG_CNT0; -typedef union MP1_FW_DEBUG_CNT1 regMP1_FW_DEBUG_CNT1; -typedef union MP1_FW_DEBUG_CNT2 regMP1_FW_DEBUG_CNT2; -typedef union MP1_FW_DEBUG_CNT3 regMP1_FW_DEBUG_CNT3; -typedef union MP1_FW_DEBUG_SIGNAL0 regMP1_FW_DEBUG_SIGNAL0; -typedef union MP1_FW_DEBUG_SIGNAL1 regMP1_FW_DEBUG_SIGNAL1; -typedef union MP1_DSM_ENABLE regMP1_DSM_ENABLE; -typedef union MP1_FIRMWARE_FLAGS regMP1_FIRMWARE_FLAGS; -typedef union MP1_MUTEX_0 regMP1_MUTEX_0; -typedef union MP1_MUTEX_1 regMP1_MUTEX_1; -typedef union MP1_MUTEX_2 regMP1_MUTEX_2; -typedef union MP1_MUTEX_3 regMP1_MUTEX_3; -typedef union MP1_PUB_SCRATCH0 regMP1_PUB_SCRATCH0; -typedef union MP1_PUB_SCRATCH1 regMP1_PUB_SCRATCH1; -typedef union MP1_PUB_SCRATCH2 regMP1_PUB_SCRATCH2; -typedef union MP1_PUB_SCRATCH3 regMP1_PUB_SCRATCH3; -typedef union MP1_FW_CHRONO_LO regMP1_FW_CHRONO_LO; -typedef union MP1_FW_CHRONO_HI regMP1_FW_CHRONO_HI; -typedef union MP1_C2PMSG_0 regMP1_C2PMSG_0; -typedef union MP1_C2PMSG_1 regMP1_C2PMSG_1; -typedef union MP1_C2PMSG_2 regMP1_C2PMSG_2; -typedef union MP1_C2PMSG_3 regMP1_C2PMSG_3; -typedef union MP1_C2PMSG_4 regMP1_C2PMSG_4; -typedef union MP1_C2PMSG_5 regMP1_C2PMSG_5; -typedef union MP1_C2PMSG_6 regMP1_C2PMSG_6; -typedef union MP1_C2PMSG_7 regMP1_C2PMSG_7; -typedef union MP1_C2PMSG_8 regMP1_C2PMSG_8; -typedef union MP1_C2PMSG_9 regMP1_C2PMSG_9; -typedef union MP1_C2PMSG_10 regMP1_C2PMSG_10; -typedef union MP1_C2PMSG_11 regMP1_C2PMSG_11; -typedef union MP1_C2PMSG_12 regMP1_C2PMSG_12; -typedef union MP1_C2PMSG_13 regMP1_C2PMSG_13; -typedef union MP1_C2PMSG_14 regMP1_C2PMSG_14; -typedef union MP1_C2PMSG_15 regMP1_C2PMSG_15; -typedef union MP1_C2PMSG_16 regMP1_C2PMSG_16; -typedef union MP1_C2PMSG_17 regMP1_C2PMSG_17; -typedef union MP1_C2PMSG_18 regMP1_C2PMSG_18; -typedef union MP1_C2PMSG_19 regMP1_C2PMSG_19; -typedef union MP1_C2PMSG_20 regMP1_C2PMSG_20; -typedef union MP1_C2PMSG_21 regMP1_C2PMSG_21; -typedef union MP1_C2PMSG_22 regMP1_C2PMSG_22; -typedef union MP1_C2PMSG_23 regMP1_C2PMSG_23; -typedef union MP1_C2PMSG_24 regMP1_C2PMSG_24; -typedef union MP1_C2PMSG_25 regMP1_C2PMSG_25; -typedef union MP1_C2PMSG_26 regMP1_C2PMSG_26; -typedef union MP1_C2PMSG_27 regMP1_C2PMSG_27; -typedef union MP1_C2PMSG_28 regMP1_C2PMSG_28; -typedef union MP1_C2PMSG_29 regMP1_C2PMSG_29; -typedef union MP1_C2PMSG_30 regMP1_C2PMSG_30; -typedef union MP1_C2PMSG_31 regMP1_C2PMSG_31; -typedef union MP1_C2PMSG_32 regMP1_C2PMSG_32; -typedef union MP1_C2PMSG_33 regMP1_C2PMSG_33; -typedef union MP1_C2PMSG_34 regMP1_C2PMSG_34; -typedef union MP1_C2PMSG_35 regMP1_C2PMSG_35; -typedef union MP1_C2PMSG_36 regMP1_C2PMSG_36; -typedef union MP1_C2PMSG_37 regMP1_C2PMSG_37; -typedef union MP1_C2PMSG_38 regMP1_C2PMSG_38; -typedef union MP1_C2PMSG_39 regMP1_C2PMSG_39; -typedef union MP1_C2PMSG_40 regMP1_C2PMSG_40; -typedef union MP1_C2PMSG_41 regMP1_C2PMSG_41; -typedef union MP1_C2PMSG_42 regMP1_C2PMSG_42; -typedef union MP1_C2PMSG_43 regMP1_C2PMSG_43; -typedef union MP1_C2PMSG_44 regMP1_C2PMSG_44; -typedef union MP1_C2PMSG_45 regMP1_C2PMSG_45; -typedef union MP1_C2PMSG_46 regMP1_C2PMSG_46; -typedef union MP1_C2PMSG_47 regMP1_C2PMSG_47; -typedef union MP1_C2PMSG_48 regMP1_C2PMSG_48; -typedef union MP1_C2PMSG_49 regMP1_C2PMSG_49; -typedef union MP1_C2PMSG_50 regMP1_C2PMSG_50; -typedef union MP1_C2PMSG_51 regMP1_C2PMSG_51; -typedef union MP1_C2PMSG_52 regMP1_C2PMSG_52; -typedef union MP1_C2PMSG_53 regMP1_C2PMSG_53; -typedef union MP1_C2PMSG_54 regMP1_C2PMSG_54; -typedef union MP1_C2PMSG_55 regMP1_C2PMSG_55; -typedef union MP1_C2PMSG_56 regMP1_C2PMSG_56; -typedef union MP1_C2PMSG_57 regMP1_C2PMSG_57; -typedef union MP1_C2PMSG_58 regMP1_C2PMSG_58; -typedef union MP1_C2PMSG_59 regMP1_C2PMSG_59; -typedef union MP1_C2PMSG_60 regMP1_C2PMSG_60; -typedef union MP1_C2PMSG_61 regMP1_C2PMSG_61; -typedef union MP1_C2PMSG_62 regMP1_C2PMSG_62; -typedef union MP1_C2PMSG_63 regMP1_C2PMSG_63; -typedef union MP1_C2PMSG_64 regMP1_C2PMSG_64; -typedef union MP1_C2PMSG_65 regMP1_C2PMSG_65; -typedef union MP1_C2PMSG_66 regMP1_C2PMSG_66; -typedef union MP1_C2PMSG_67 regMP1_C2PMSG_67; -typedef union MP1_C2PMSG_68 regMP1_C2PMSG_68; -typedef union MP1_C2PMSG_69 regMP1_C2PMSG_69; -typedef union MP1_C2PMSG_70 regMP1_C2PMSG_70; -typedef union MP1_C2PMSG_71 regMP1_C2PMSG_71; -typedef union MP1_C2PMSG_72 regMP1_C2PMSG_72; -typedef union MP1_C2PMSG_73 regMP1_C2PMSG_73; -typedef union MP1_C2PMSG_74 regMP1_C2PMSG_74; -typedef union MP1_C2PMSG_75 regMP1_C2PMSG_75; -typedef union MP1_C2PMSG_76 regMP1_C2PMSG_76; -typedef union MP1_C2PMSG_77 regMP1_C2PMSG_77; -typedef union MP1_C2PMSG_78 regMP1_C2PMSG_78; -typedef union MP1_C2PMSG_79 regMP1_C2PMSG_79; -typedef union MP1_C2PMSG_80 regMP1_C2PMSG_80; -typedef union MP1_C2PMSG_81 regMP1_C2PMSG_81; -typedef union MP1_C2PMSG_82 regMP1_C2PMSG_82; -typedef union MP1_C2PMSG_83 regMP1_C2PMSG_83; -typedef union MP1_C2PMSG_84 regMP1_C2PMSG_84; -typedef union MP1_C2PMSG_85 regMP1_C2PMSG_85; -typedef union MP1_C2PMSG_86 regMP1_C2PMSG_86; -typedef union MP1_C2PMSG_87 regMP1_C2PMSG_87; -typedef union MP1_C2PMSG_88 regMP1_C2PMSG_88; -typedef union MP1_C2PMSG_89 regMP1_C2PMSG_89; -typedef union MP1_C2PMSG_90 regMP1_C2PMSG_90; -typedef union MP1_C2PMSG_91 regMP1_C2PMSG_91; -typedef union MP1_C2PMSG_92 regMP1_C2PMSG_92; -typedef union MP1_C2PMSG_93 regMP1_C2PMSG_93; -typedef union MP1_C2PMSG_94 regMP1_C2PMSG_94; -typedef union MP1_C2PMSG_95 regMP1_C2PMSG_95; -typedef union MP1_P2CMSG_0 regMP1_P2CMSG_0; -typedef union MP1_P2CMSG_1 regMP1_P2CMSG_1; -typedef union MP1_P2CMSG_2 regMP1_P2CMSG_2; -typedef union MP1_P2CMSG_3 regMP1_P2CMSG_3; -typedef union MP1_P2CMSG_INTEN regMP1_P2CMSG_INTEN; -typedef union MP1_P2CMSG_INTSTS regMP1_P2CMSG_INTSTS; -typedef union MP1_P2SMSG_0 regMP1_P2SMSG_0; -typedef union MP1_P2SMSG_1 regMP1_P2SMSG_1; -typedef union MP1_P2SMSG_2 regMP1_P2SMSG_2; -typedef union MP1_P2SMSG_3 regMP1_P2SMSG_3; -typedef union MP1_P2SMSG_INTSTS regMP1_P2SMSG_INTSTS; -typedef union MP1_S2PMSG_0 regMP1_S2PMSG_0; -typedef union MP1_PUB_RSMU_HCID regMP1_PUB_RSMU_HCID; -typedef union MP1_PUB_RSMU_SIID regMP1_PUB_RSMU_SIID; -typedef union MP1_SRBMTMR_0_CTRL0 regMP1_SRBMTMR_0_CTRL0; -typedef union MP1_SRBMTMR_1_CTRL0 regMP1_SRBMTMR_1_CTRL0; -typedef union MP1_SRBMTMR_0_CTRL1 regMP1_SRBMTMR_0_CTRL1; -typedef union MP1_SRBMTMR_1_CTRL1 regMP1_SRBMTMR_1_CTRL1; -typedef union MP1_SRBMTMR_0_CMP_AUTOINC regMP1_SRBMTMR_0_CMP_AUTOINC; -typedef union MP1_SRBMTMR_1_CMP_AUTOINC regMP1_SRBMTMR_1_CMP_AUTOINC; -typedef union MP1_SRBMTMR_0_INTEN regMP1_SRBMTMR_0_INTEN; -typedef union MP1_SRBMTMR_1_INTEN regMP1_SRBMTMR_1_INTEN; -typedef union MP1_SRBMTMR_OCMP_0_0 regMP1_SRBMTMR_OCMP_0_0; -typedef union MP1_SRBMTMR_OCMP_1_0 regMP1_SRBMTMR_OCMP_1_0; -typedef union MP1_SRBMTMR_0_CNT regMP1_SRBMTMR_0_CNT; -typedef union MP1_SRBMTMR_1_CNT regMP1_SRBMTMR_1_CNT; -typedef union MP1_ACP2MP_RESP regMP1_ACP2MP_RESP; -typedef union MP1_DC2MP_RESP regMP1_DC2MP_RESP; -typedef union MP1_UVD2MP_RESP regMP1_UVD2MP_RESP; -typedef union MP1_VCE2MP_RESP regMP1_VCE2MP_RESP; -typedef union MP1_RLC2MP_RESP regMP1_RLC2MP_RESP; -typedef union MP1_IH_MP0SW_INT regMP1_IH_MP0SW_INT; -typedef union MP1_IH_MP1SW_INT regMP1_IH_MP1SW_INT; -typedef union MP1_IH_SW_INT_CTRL regMP1_IH_SW_INT_CTRL; -typedef union MP1_IH_DISPTMR0_INT_CTRL regMP1_IH_DISPTMR0_INT_CTRL; -typedef union MP1_IH_DISPTMR1_INT_CTRL regMP1_IH_DISPTMR1_INT_CTRL; -typedef union MP1_FPS_CNT regMP1_FPS_CNT; -typedef union MP1_REVID regMP1_REVID; -typedef union MP1_RSMU_HCID regMP1_RSMU_HCID; -typedef union MP1_RSMU_SIID regMP1_RSMU_SIID; -typedef union MP1_RAM_REPAIR_DONE regMP1_RAM_REPAIR_DONE; -typedef union MP1_RAM_REPAIR_RESULT regMP1_RAM_REPAIR_RESULT; -typedef union MP1_FUSE_HARVESTING regMP1_FUSE_HARVESTING; -typedef union MP1_FUSE_RMBITS regMP1_FUSE_RMBITS; -typedef union MP1_SMS_CFG regMP1_SMS_CFG; -typedef union MP1_FUSE_SMS_0 regMP1_FUSE_SMS_0; -typedef union MP1_FUSE_SMS_1 regMP1_FUSE_SMS_1; -typedef union MP1_FUSE_SMS_2 regMP1_FUSE_SMS_2; -typedef union MP1_FUSE_SMS_3 regMP1_FUSE_SMS_3; -typedef union MP1_FUSE_SMS_4 regMP1_FUSE_SMS_4; -typedef union MP1_FUSE_SMS_5 regMP1_FUSE_SMS_5; -typedef union MP1_FUSE_SMS_6 regMP1_FUSE_SMS_6; -typedef union MP1_FUSE_SMS_7 regMP1_FUSE_SMS_7; -typedef union MP1_ACC_VIO_INTSTS regMP1_ACC_VIO_INTSTS; -typedef union MP1_TDR_MISC0_STATUS regMP1_TDR_MISC0_STATUS; -typedef union MP1_EVCNTCTL regMP1_EVCNTCTL; -typedef union MP1_EVCNTSEL regMP1_EVCNTSEL; -typedef union MP1_EVCNT0 regMP1_EVCNT0; -typedef union MP1_EVCNT1 regMP1_EVCNT1; -typedef union MP1_EVCNTHI regMP1_EVCNTHI; -typedef union MP1_J2P_MBOX0 regMP1_J2P_MBOX0; -typedef union MP1_J2P_MBOX1 regMP1_J2P_MBOX1; -typedef union MP1_J2P_ATTR regMP1_J2P_ATTR; -typedef union MP1_CRU_ACC_VIO_INTSTS regMP1_CRU_ACC_VIO_INTSTS; -typedef union MP1_ACC_VIOL_LOG0 regMP1_ACC_VIOL_LOG0; -typedef union MP1_ACC_VIOL_LOG1 regMP1_ACC_VIOL_LOG1; -typedef union MP1_SEC_SCRATCH0 regMP1_SEC_SCRATCH0; -typedef union MP1_SEC_SCRATCH1 regMP1_SEC_SCRATCH1; -typedef union MP1_SEC_SCRATCH2 regMP1_SEC_SCRATCH2; -typedef union MP1_SEC_SCRATCH3 regMP1_SEC_SCRATCH3; -typedef union MP1_STICKY regMP1_STICKY; -typedef union MP1_CRU_MISC_CTRL regMP1_CRU_MISC_CTRL; -typedef union MP1_SOFT_RESET_CTRL regMP1_SOFT_RESET_CTRL; -typedef union MP1_NS_PROT_FAULT_STATUS_0 regMP1_NS_PROT_FAULT_STATUS_0; -typedef union MP1_FW_MISC_CTRL regMP1_FW_MISC_CTRL; -typedef union MP1_AEB_STATUS_0 regMP1_AEB_STATUS_0; -typedef union MP1_PIC0_MASK_0 regMP1_PIC0_MASK_0; -typedef union MP1_PIC0_LEVEL_0 regMP1_PIC0_LEVEL_0; -typedef union MP1_PIC0_EDGE_0 regMP1_PIC0_EDGE_0; -typedef union MP1_PIC0_PRIORITY_0 regMP1_PIC0_PRIORITY_0; -typedef union MP1_PIC0_PRIORITY_1 regMP1_PIC0_PRIORITY_1; -typedef union MP1_PIC0_STATUS_0 regMP1_PIC0_STATUS_0; -typedef union MP1_PIC0_INTR regMP1_PIC0_INTR; -typedef union MP1_PIC0_ID regMP1_PIC0_ID; -typedef union MP1_PIC1_MASK_0 regMP1_PIC1_MASK_0; -typedef union MP1_PIC1_MASK_1 regMP1_PIC1_MASK_1; -typedef union MP1_PIC1_MASK_2 regMP1_PIC1_MASK_2; -typedef union MP1_PIC1_MASK_3 regMP1_PIC1_MASK_3; -typedef union MP1_PIC1_LEVEL_0 regMP1_PIC1_LEVEL_0; -typedef union MP1_PIC1_LEVEL_1 regMP1_PIC1_LEVEL_1; -typedef union MP1_PIC1_LEVEL_2 regMP1_PIC1_LEVEL_2; -typedef union MP1_PIC1_LEVEL_3 regMP1_PIC1_LEVEL_3; -typedef union MP1_PIC1_EDGE_0 regMP1_PIC1_EDGE_0; -typedef union MP1_PIC1_EDGE_1 regMP1_PIC1_EDGE_1; -typedef union MP1_PIC1_EDGE_2 regMP1_PIC1_EDGE_2; -typedef union MP1_PIC1_EDGE_3 regMP1_PIC1_EDGE_3; -typedef union MP1_PIC1_PRIORITY_0 regMP1_PIC1_PRIORITY_0; -typedef union MP1_PIC1_PRIORITY_1 regMP1_PIC1_PRIORITY_1; -typedef union MP1_PIC1_PRIORITY_2 regMP1_PIC1_PRIORITY_2; -typedef union MP1_PIC1_PRIORITY_3 regMP1_PIC1_PRIORITY_3; -typedef union MP1_PIC1_PRIORITY_4 regMP1_PIC1_PRIORITY_4; -typedef union MP1_PIC1_PRIORITY_5 regMP1_PIC1_PRIORITY_5; -typedef union MP1_PIC1_PRIORITY_6 regMP1_PIC1_PRIORITY_6; -typedef union MP1_PIC1_PRIORITY_7 regMP1_PIC1_PRIORITY_7; -typedef union MP1_PIC1_PRIORITY_8 regMP1_PIC1_PRIORITY_8; -typedef union MP1_PIC1_PRIORITY_9 regMP1_PIC1_PRIORITY_9; -typedef union MP1_PIC1_PRIORITY_10 regMP1_PIC1_PRIORITY_10; -typedef union MP1_PIC1_PRIORITY_11 regMP1_PIC1_PRIORITY_11; -typedef union MP1_PIC1_PRIORITY_12 regMP1_PIC1_PRIORITY_12; -typedef union MP1_PIC1_PRIORITY_13 regMP1_PIC1_PRIORITY_13; -typedef union MP1_PIC1_PRIORITY_14 regMP1_PIC1_PRIORITY_14; -typedef union MP1_PIC1_PRIORITY_15 regMP1_PIC1_PRIORITY_15; -typedef union MP1_PIC1_PRIORITY_16 regMP1_PIC1_PRIORITY_16; -typedef union MP1_PIC1_PRIORITY_17 regMP1_PIC1_PRIORITY_17; -typedef union MP1_PIC1_PRIORITY_18 regMP1_PIC1_PRIORITY_18; -typedef union MP1_PIC1_PRIORITY_19 regMP1_PIC1_PRIORITY_19; -typedef union MP1_PIC1_PRIORITY_20 regMP1_PIC1_PRIORITY_20; -typedef union MP1_PIC1_PRIORITY_21 regMP1_PIC1_PRIORITY_21; -typedef union MP1_PIC1_PRIORITY_22 regMP1_PIC1_PRIORITY_22; -typedef union MP1_PIC1_PRIORITY_23 regMP1_PIC1_PRIORITY_23; -typedef union MP1_PIC1_PRIORITY_24 regMP1_PIC1_PRIORITY_24; -typedef union MP1_PIC1_PRIORITY_25 regMP1_PIC1_PRIORITY_25; -typedef union MP1_PIC1_PRIORITY_26 regMP1_PIC1_PRIORITY_26; -typedef union MP1_PIC1_PRIORITY_27 regMP1_PIC1_PRIORITY_27; -typedef union MP1_PIC1_PRIORITY_28 regMP1_PIC1_PRIORITY_28; -typedef union MP1_PIC1_PRIORITY_29 regMP1_PIC1_PRIORITY_29; -typedef union MP1_PIC1_PRIORITY_30 regMP1_PIC1_PRIORITY_30; -typedef union MP1_PIC1_PRIORITY_31 regMP1_PIC1_PRIORITY_31; -typedef union MP1_PIC1_STATUS_0 regMP1_PIC1_STATUS_0; -typedef union MP1_PIC1_STATUS_1 regMP1_PIC1_STATUS_1; -typedef union MP1_PIC1_STATUS_2 regMP1_PIC1_STATUS_2; -typedef union MP1_PIC1_STATUS_3 regMP1_PIC1_STATUS_3; -typedef union MP1_PIC1_INTR regMP1_PIC1_INTR; -typedef union MP1_PIC1_ID regMP1_PIC1_ID; -typedef union MP1_TIMER_0_CTRL0 regMP1_TIMER_0_CTRL0; -typedef union MP1_TIMER_1_CTRL0 regMP1_TIMER_1_CTRL0; -typedef union MP1_TIMER_2_CTRL0 regMP1_TIMER_2_CTRL0; -typedef union MP1_TIMER_3_CTRL0 regMP1_TIMER_3_CTRL0; -typedef union MP1_TIMER_4_CTRL0 regMP1_TIMER_4_CTRL0; -typedef union MP1_TIMER_5_CTRL0 regMP1_TIMER_5_CTRL0; -typedef union MP1_TIMER_6_CTRL0 regMP1_TIMER_6_CTRL0; -typedef union MP1_TIMER_7_CTRL0 regMP1_TIMER_7_CTRL0; -typedef union MP1_TIMER_0_CTRL1 regMP1_TIMER_0_CTRL1; -typedef union MP1_TIMER_1_CTRL1 regMP1_TIMER_1_CTRL1; -typedef union MP1_TIMER_2_CTRL1 regMP1_TIMER_2_CTRL1; -typedef union MP1_TIMER_3_CTRL1 regMP1_TIMER_3_CTRL1; -typedef union MP1_TIMER_4_CTRL1 regMP1_TIMER_4_CTRL1; -typedef union MP1_TIMER_5_CTRL1 regMP1_TIMER_5_CTRL1; -typedef union MP1_TIMER_6_CTRL1 regMP1_TIMER_6_CTRL1; -typedef union MP1_TIMER_7_CTRL1 regMP1_TIMER_7_CTRL1; -typedef union MP1_TIMER_0_CMP_AUTOINC regMP1_TIMER_0_CMP_AUTOINC; -typedef union MP1_TIMER_1_CMP_AUTOINC regMP1_TIMER_1_CMP_AUTOINC; -typedef union MP1_TIMER_2_CMP_AUTOINC regMP1_TIMER_2_CMP_AUTOINC; -typedef union MP1_TIMER_3_CMP_AUTOINC regMP1_TIMER_3_CMP_AUTOINC; -typedef union MP1_TIMER_4_CMP_AUTOINC regMP1_TIMER_4_CMP_AUTOINC; -typedef union MP1_TIMER_5_CMP_AUTOINC regMP1_TIMER_5_CMP_AUTOINC; -typedef union MP1_TIMER_6_CMP_AUTOINC regMP1_TIMER_6_CMP_AUTOINC; -typedef union MP1_TIMER_7_CMP_AUTOINC regMP1_TIMER_7_CMP_AUTOINC; -typedef union MP1_TIMER_0_INTEN regMP1_TIMER_0_INTEN; -typedef union MP1_TIMER_1_INTEN regMP1_TIMER_1_INTEN; -typedef union MP1_TIMER_2_INTEN regMP1_TIMER_2_INTEN; -typedef union MP1_TIMER_3_INTEN regMP1_TIMER_3_INTEN; -typedef union MP1_TIMER_4_INTEN regMP1_TIMER_4_INTEN; -typedef union MP1_TIMER_5_INTEN regMP1_TIMER_5_INTEN; -typedef union MP1_TIMER_6_INTEN regMP1_TIMER_6_INTEN; -typedef union MP1_TIMER_7_INTEN regMP1_TIMER_7_INTEN; -typedef union MP1_TIMER_OCMP_0_0 regMP1_TIMER_OCMP_0_0; -typedef union MP1_TIMER_OCMP_1_0 regMP1_TIMER_OCMP_1_0; -typedef union MP1_TIMER_OCMP_2_0 regMP1_TIMER_OCMP_2_0; -typedef union MP1_TIMER_OCMP_3_0 regMP1_TIMER_OCMP_3_0; -typedef union MP1_TIMER_OCMP_4_0 regMP1_TIMER_OCMP_4_0; -typedef union MP1_TIMER_OCMP_5_0 regMP1_TIMER_OCMP_5_0; -typedef union MP1_TIMER_OCMP_6_0 regMP1_TIMER_OCMP_6_0; -typedef union MP1_TIMER_OCMP_7_0 regMP1_TIMER_OCMP_7_0; -typedef union MP1_TIMER_OCMP_0_1 regMP1_TIMER_OCMP_0_1; -typedef union MP1_TIMER_OCMP_1_1 regMP1_TIMER_OCMP_1_1; -typedef union MP1_TIMER_OCMP_2_1 regMP1_TIMER_OCMP_2_1; -typedef union MP1_TIMER_OCMP_3_1 regMP1_TIMER_OCMP_3_1; -typedef union MP1_TIMER_OCMP_4_1 regMP1_TIMER_OCMP_4_1; -typedef union MP1_TIMER_OCMP_5_1 regMP1_TIMER_OCMP_5_1; -typedef union MP1_TIMER_OCMP_6_1 regMP1_TIMER_OCMP_6_1; -typedef union MP1_TIMER_OCMP_7_1 regMP1_TIMER_OCMP_7_1; -typedef union MP1_TIMER_OCMP_0_2 regMP1_TIMER_OCMP_0_2; -typedef union MP1_TIMER_OCMP_1_2 regMP1_TIMER_OCMP_1_2; -typedef union MP1_TIMER_OCMP_2_2 regMP1_TIMER_OCMP_2_2; -typedef union MP1_TIMER_OCMP_3_2 regMP1_TIMER_OCMP_3_2; -typedef union MP1_TIMER_OCMP_4_2 regMP1_TIMER_OCMP_4_2; -typedef union MP1_TIMER_OCMP_5_2 regMP1_TIMER_OCMP_5_2; -typedef union MP1_TIMER_OCMP_6_2 regMP1_TIMER_OCMP_6_2; -typedef union MP1_TIMER_OCMP_7_2 regMP1_TIMER_OCMP_7_2; -typedef union MP1_TIMER_OCMP_0_3 regMP1_TIMER_OCMP_0_3; -typedef union MP1_TIMER_OCMP_1_3 regMP1_TIMER_OCMP_1_3; -typedef union MP1_TIMER_OCMP_2_3 regMP1_TIMER_OCMP_2_3; -typedef union MP1_TIMER_OCMP_3_3 regMP1_TIMER_OCMP_3_3; -typedef union MP1_TIMER_OCMP_4_3 regMP1_TIMER_OCMP_4_3; -typedef union MP1_TIMER_OCMP_5_3 regMP1_TIMER_OCMP_5_3; -typedef union MP1_TIMER_OCMP_6_3 regMP1_TIMER_OCMP_6_3; -typedef union MP1_TIMER_OCMP_7_3 regMP1_TIMER_OCMP_7_3; -typedef union MP1_TIMER_0_CNT regMP1_TIMER_0_CNT; -typedef union MP1_TIMER_1_CNT regMP1_TIMER_1_CNT; -typedef union MP1_TIMER_2_CNT regMP1_TIMER_2_CNT; -typedef union MP1_TIMER_3_CNT regMP1_TIMER_3_CNT; -typedef union MP1_TIMER_4_CNT regMP1_TIMER_4_CNT; -typedef union MP1_TIMER_5_CNT regMP1_TIMER_5_CNT; -typedef union MP1_TIMER_6_CNT regMP1_TIMER_6_CNT; -typedef union MP1_TIMER_7_CNT regMP1_TIMER_7_CNT; -typedef union MP1_C2PMSG_ATTR_0 regMP1_C2PMSG_ATTR_0; -typedef union MP1_C2PMSG_ATTR_1 regMP1_C2PMSG_ATTR_1; -typedef union MP1_C2PMSG_ATTR_2 regMP1_C2PMSG_ATTR_2; -typedef union MP1_C2PMSG_ATTR_3 regMP1_C2PMSG_ATTR_3; -typedef union MP1_C2PMSG_ATTR_4 regMP1_C2PMSG_ATTR_4; -typedef union MP1_C2PMSG_ATTR_5 regMP1_C2PMSG_ATTR_5; -typedef union MP1_P2CMSG_ATTR regMP1_P2CMSG_ATTR; -typedef union MP1_S2PMSG_ATTR regMP1_S2PMSG_ATTR; -typedef union MP1_P2SMSG_ATTR regMP1_P2SMSG_ATTR; -typedef union MP1_SMN_SRBMTMR_0_CTRL0 regMP1_SMN_SRBMTMR_0_CTRL0; -typedef union MP1_SMN_SRBMTMR_1_CTRL0 regMP1_SMN_SRBMTMR_1_CTRL0; -typedef union MP1_SMN_SRBMTMR_0_CTRL1 regMP1_SMN_SRBMTMR_0_CTRL1; -typedef union MP1_SMN_SRBMTMR_1_CTRL1 regMP1_SMN_SRBMTMR_1_CTRL1; -typedef union MP1_SMN_SRBMTMR_0_CMP_AUTOINC regMP1_SMN_SRBMTMR_0_CMP_AUTOINC; -typedef union MP1_SMN_SRBMTMR_1_CMP_AUTOINC regMP1_SMN_SRBMTMR_1_CMP_AUTOINC; -typedef union MP1_SMN_SRBMTMR_0_INTEN regMP1_SMN_SRBMTMR_0_INTEN; -typedef union MP1_SMN_SRBMTMR_1_INTEN regMP1_SMN_SRBMTMR_1_INTEN; -typedef union MP1_SMN_SRBMTMR_OCMP_0_0 regMP1_SMN_SRBMTMR_OCMP_0_0; -typedef union MP1_SMN_SRBMTMR_OCMP_1_0 regMP1_SMN_SRBMTMR_OCMP_1_0; -typedef union MP1_SMN_SRBMTMR_0_CNT regMP1_SMN_SRBMTMR_0_CNT; -typedef union MP1_SMN_SRBMTMR_1_CNT regMP1_SMN_SRBMTMR_1_CNT; -typedef union MP1_SMN_ACP2MP_RESP regMP1_SMN_ACP2MP_RESP; -typedef union MP1_SMN_DC2MP_RESP regMP1_SMN_DC2MP_RESP; -typedef union MP1_SMN_UVD2MP_RESP regMP1_SMN_UVD2MP_RESP; -typedef union MP1_SMN_VCE2MP_RESP regMP1_SMN_VCE2MP_RESP; -typedef union MP1_SMN_RLC2MP_RESP regMP1_SMN_RLC2MP_RESP; -typedef union MP1_SMN_C2PMSG_32 regMP1_SMN_C2PMSG_32; -typedef union MP1_SMN_C2PMSG_33 regMP1_SMN_C2PMSG_33; -typedef union MP1_SMN_C2PMSG_34 regMP1_SMN_C2PMSG_34; -typedef union MP1_SMN_C2PMSG_35 regMP1_SMN_C2PMSG_35; -typedef union MP1_SMN_C2PMSG_36 regMP1_SMN_C2PMSG_36; -typedef union MP1_SMN_C2PMSG_37 regMP1_SMN_C2PMSG_37; -typedef union MP1_SMN_C2PMSG_38 regMP1_SMN_C2PMSG_38; -typedef union MP1_SMN_C2PMSG_39 regMP1_SMN_C2PMSG_39; -typedef union MP1_SMN_C2PMSG_40 regMP1_SMN_C2PMSG_40; -typedef union MP1_SMN_C2PMSG_41 regMP1_SMN_C2PMSG_41; -typedef union MP1_SMN_C2PMSG_42 regMP1_SMN_C2PMSG_42; -typedef union MP1_SMN_C2PMSG_43 regMP1_SMN_C2PMSG_43; -typedef union MP1_SMN_C2PMSG_44 regMP1_SMN_C2PMSG_44; -typedef union MP1_SMN_C2PMSG_45 regMP1_SMN_C2PMSG_45; -typedef union MP1_SMN_C2PMSG_46 regMP1_SMN_C2PMSG_46; -typedef union MP1_SMN_C2PMSG_47 regMP1_SMN_C2PMSG_47; -typedef union MP1_SMN_C2PMSG_48 regMP1_SMN_C2PMSG_48; -typedef union MP1_SMN_C2PMSG_49 regMP1_SMN_C2PMSG_49; -typedef union MP1_SMN_C2PMSG_50 regMP1_SMN_C2PMSG_50; -typedef union MP1_SMN_C2PMSG_51 regMP1_SMN_C2PMSG_51; -typedef union MP1_SMN_C2PMSG_52 regMP1_SMN_C2PMSG_52; -typedef union MP1_SMN_C2PMSG_53 regMP1_SMN_C2PMSG_53; -typedef union MP1_SMN_C2PMSG_54 regMP1_SMN_C2PMSG_54; -typedef union MP1_SMN_C2PMSG_55 regMP1_SMN_C2PMSG_55; -typedef union MP1_SMN_C2PMSG_56 regMP1_SMN_C2PMSG_56; -typedef union MP1_SMN_C2PMSG_57 regMP1_SMN_C2PMSG_57; -typedef union MP1_SMN_C2PMSG_58 regMP1_SMN_C2PMSG_58; -typedef union MP1_SMN_C2PMSG_59 regMP1_SMN_C2PMSG_59; -typedef union MP1_SMN_C2PMSG_60 regMP1_SMN_C2PMSG_60; -typedef union MP1_SMN_C2PMSG_61 regMP1_SMN_C2PMSG_61; -typedef union MP1_SMN_C2PMSG_62 regMP1_SMN_C2PMSG_62; -typedef union MP1_SMN_C2PMSG_63 regMP1_SMN_C2PMSG_63; -typedef union MP1_SMN_C2PMSG_64 regMP1_SMN_C2PMSG_64; -typedef union MP1_SMN_C2PMSG_65 regMP1_SMN_C2PMSG_65; -typedef union MP1_SMN_C2PMSG_66 regMP1_SMN_C2PMSG_66; -typedef union MP1_SMN_C2PMSG_67 regMP1_SMN_C2PMSG_67; -typedef union MP1_SMN_C2PMSG_68 regMP1_SMN_C2PMSG_68; -typedef union MP1_SMN_C2PMSG_69 regMP1_SMN_C2PMSG_69; -typedef union MP1_SMN_C2PMSG_70 regMP1_SMN_C2PMSG_70; -typedef union MP1_SMN_C2PMSG_71 regMP1_SMN_C2PMSG_71; -typedef union MP1_SMN_C2PMSG_72 regMP1_SMN_C2PMSG_72; -typedef union MP1_SMN_C2PMSG_73 regMP1_SMN_C2PMSG_73; -typedef union MP1_SMN_C2PMSG_74 regMP1_SMN_C2PMSG_74; -typedef union MP1_SMN_C2PMSG_75 regMP1_SMN_C2PMSG_75; -typedef union MP1_SMN_C2PMSG_76 regMP1_SMN_C2PMSG_76; -typedef union MP1_SMN_C2PMSG_77 regMP1_SMN_C2PMSG_77; -typedef union MP1_SMN_C2PMSG_78 regMP1_SMN_C2PMSG_78; -typedef union MP1_SMN_C2PMSG_79 regMP1_SMN_C2PMSG_79; -typedef union MP1_SMN_C2PMSG_80 regMP1_SMN_C2PMSG_80; -typedef union MP1_SMN_C2PMSG_81 regMP1_SMN_C2PMSG_81; -typedef union MP1_SMN_C2PMSG_82 regMP1_SMN_C2PMSG_82; -typedef union MP1_SMN_C2PMSG_83 regMP1_SMN_C2PMSG_83; -typedef union MP1_SMN_C2PMSG_84 regMP1_SMN_C2PMSG_84; -typedef union MP1_SMN_C2PMSG_85 regMP1_SMN_C2PMSG_85; -typedef union MP1_SMN_C2PMSG_86 regMP1_SMN_C2PMSG_86; -typedef union MP1_SMN_C2PMSG_87 regMP1_SMN_C2PMSG_87; -typedef union MP1_SMN_C2PMSG_88 regMP1_SMN_C2PMSG_88; -typedef union MP1_SMN_C2PMSG_89 regMP1_SMN_C2PMSG_89; -typedef union MP1_SMN_C2PMSG_90 regMP1_SMN_C2PMSG_90; -typedef union MP1_SMN_C2PMSG_91 regMP1_SMN_C2PMSG_91; -typedef union MP1_SMN_C2PMSG_92 regMP1_SMN_C2PMSG_92; -typedef union MP1_SMN_C2PMSG_93 regMP1_SMN_C2PMSG_93; -typedef union MP1_SMN_C2PMSG_94 regMP1_SMN_C2PMSG_94; -typedef union MP1_SMN_C2PMSG_95 regMP1_SMN_C2PMSG_95; -typedef union MP1_SMN_IH_MP0SW_INT regMP1_SMN_IH_MP0SW_INT; -typedef union MP1_SMN_IH_MP1SW_INT regMP1_SMN_IH_MP1SW_INT; -typedef union MP1_SMN_IH_SW_INT_CTRL regMP1_SMN_IH_SW_INT_CTRL; -typedef union MP1_SMN_IH_DISPTMR0_INT_CTRL regMP1_SMN_IH_DISPTMR0_INT_CTRL; -typedef union MP1_SMN_IH_DISPTMR1_INT_CTRL regMP1_SMN_IH_DISPTMR1_INT_CTRL; -typedef union MP1_SMN_FPS_CNT regMP1_SMN_FPS_CNT; -typedef union MP1_RSMU_PUB_RSMU_HCID regMP1_RSMU_PUB_RSMU_HCID; -typedef union MP1_RSMU_PUB_RSMU_SIID regMP1_RSMU_PUB_RSMU_SIID; -typedef union MP1_PMI_0_START regMP1_PMI_0_START; -typedef union MP1_PMI_0_FIFO regMP1_PMI_0_FIFO; -typedef union MP1_PMI_0_STATUS regMP1_PMI_0_STATUS; -typedef union MP1_PMI_0_READ_POINTER regMP1_PMI_0_READ_POINTER; -typedef union MP1_PMI_0_WRITE_POINTER regMP1_PMI_0_WRITE_POINTER; -typedef union MP1_PMI_1_START regMP1_PMI_1_START; -typedef union MP1_PMI_1_FIFO regMP1_PMI_1_FIFO; -typedef union MP1_PMI_1_STATUS regMP1_PMI_1_STATUS; -typedef union MP1_PMI_1_READ_POINTER regMP1_PMI_1_READ_POINTER; -typedef union MP1_PMI_1_WRITE_POINTER regMP1_PMI_1_WRITE_POINTER; -typedef union MP1_PMI_2_START regMP1_PMI_2_START; -typedef union MP1_PMI_2_FIFO regMP1_PMI_2_FIFO; -typedef union MP1_PMI_2_STATUS regMP1_PMI_2_STATUS; -typedef union MP1_PMI_2_READ_POINTER regMP1_PMI_2_READ_POINTER; -typedef union MP1_PMI_2_WRITE_POINTER regMP1_PMI_2_WRITE_POINTER; -typedef union MP1_PMI_OUT_CONFIG regMP1_PMI_OUT_CONFIG; -typedef union MP1_PMI_RELOAD regMP1_PMI_RELOAD; -typedef union MP1_PMI_INTERRUPT_CONTROL regMP1_PMI_INTERRUPT_CONTROL; -typedef union MP1_MMU_SRAM_ACC_VIOLATION_LOG_ADDR regMP1_MMU_SRAM_ACC_VIOLATION_LOG_ADDR; -typedef union MP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS regMP1_MMU_SRAM_ACC_VIOLATION_LOG_STATUS; -typedef union MP1_MMU_MISC_CNTL regMP1_MMU_MISC_CNTL; -typedef union MP1_MMU_ACCESS_ERR_LOG regMP1_MMU_ACCESS_ERR_LOG; -typedef union MP1_MMU_SRAM_UNSECURE_BAR regMP1_MMU_SRAM_UNSECURE_BAR; -typedef union MP1_MMU_SCRATCH_0 regMP1_MMU_SCRATCH_0; -typedef union MP1_MMU_SCRATCH_1 regMP1_MMU_SCRATCH_1; -typedef union MP1_MMU_SCRATCH_2 regMP1_MMU_SCRATCH_2; -typedef union MP1_MMU_SCRATCH_3 regMP1_MMU_SCRATCH_3; -typedef union MP1_MMU_SCRATCH_4 regMP1_MMU_SCRATCH_4; -typedef union MP1_MMU_SCRATCH_5 regMP1_MMU_SCRATCH_5; -typedef union MP1_MMU_SCRATCH_6 regMP1_MMU_SCRATCH_6; -typedef union MP1_MMU_SCRATCH_7 regMP1_MMU_SCRATCH_7; -typedef union MP1_MCA_ACCESS_CNTL regMP1_MCA_ACCESS_CNTL; -typedef union MP1_MCA_ACCESS_WR_DATA regMP1_MCA_ACCESS_WR_DATA; -typedef union MP1_MCA_ACCESS_RD_DATA regMP1_MCA_ACCESS_RD_DATA; -typedef union MP1_PMI_0 regMP1_PMI_0; -typedef union MP1_PMI_1 regMP1_PMI_1; -typedef union MP1_PMI_2 regMP1_PMI_2; -typedef union MP1_MMHUB_SOC_TLB0_1 regMP1_MMHUB_SOC_TLB0_1; -typedef union MP1_MMHUB_SOC_TLB0_2 regMP1_MMHUB_SOC_TLB0_2; -typedef union MP1_MMHUB_SOC_TLB0_3 regMP1_MMHUB_SOC_TLB0_3; -typedef union MP1_MMHUB_SOC_TLB0_4 regMP1_MMHUB_SOC_TLB0_4; -typedef union MP1_MMHUB_SOC_TLB0_5 regMP1_MMHUB_SOC_TLB0_5; -typedef union MP1_MMHUB_SOC_TLB0_6 regMP1_MMHUB_SOC_TLB0_6; -typedef union MP1_MMHUB_SOC_TLB0_7 regMP1_MMHUB_SOC_TLB0_7; -typedef union MP1_MMHUB_SOC_TLB0_8 regMP1_MMHUB_SOC_TLB0_8; -typedef union MP1_MMHUB_SOC_TLB0_9 regMP1_MMHUB_SOC_TLB0_9; -typedef union MP1_MMHUB_SOC_TLB0_10 regMP1_MMHUB_SOC_TLB0_10; -typedef union MP1_MMHUB_SOC_TLB0_11 regMP1_MMHUB_SOC_TLB0_11; -typedef union MP1_MMHUB_SOC_TLB0_12 regMP1_MMHUB_SOC_TLB0_12; -typedef union MP1_MMHUB_SOC_TLB0_13 regMP1_MMHUB_SOC_TLB0_13; -typedef union MP1_MMHUB_SOC_TLB0_14 regMP1_MMHUB_SOC_TLB0_14; -typedef union MP1_MMHUB_SOC_TLB0_15 regMP1_MMHUB_SOC_TLB0_15; -typedef union MP1_MMHUB_SOC_TLB0_16 regMP1_MMHUB_SOC_TLB0_16; -typedef union MP1_MMHUB_SOC_TLB0_17 regMP1_MMHUB_SOC_TLB0_17; -typedef union MP1_MMHUB_SOC_TLB0_18 regMP1_MMHUB_SOC_TLB0_18; -typedef union MP1_MMHUB_SOC_TLB0_19 regMP1_MMHUB_SOC_TLB0_19; -typedef union MP1_MMHUB_SOC_TLB0_20 regMP1_MMHUB_SOC_TLB0_20; -typedef union MP1_MMHUB_SOC_TLB0_21 regMP1_MMHUB_SOC_TLB0_21; -typedef union MP1_MMHUB_SOC_TLB0_22 regMP1_MMHUB_SOC_TLB0_22; -typedef union MP1_MMHUB_SOC_TLB0_23 regMP1_MMHUB_SOC_TLB0_23; -typedef union MP1_MMHUB_SOC_TLB0_24 regMP1_MMHUB_SOC_TLB0_24; -typedef union MP1_MMHUB_SOC_TLB0_25 regMP1_MMHUB_SOC_TLB0_25; -typedef union MP1_MMHUB_SOC_TLB0_26 regMP1_MMHUB_SOC_TLB0_26; -typedef union MP1_MMHUB_SOC_TLB0_27 regMP1_MMHUB_SOC_TLB0_27; -typedef union MP1_MMHUB_SOC_TLB0_28 regMP1_MMHUB_SOC_TLB0_28; -typedef union MP1_MMHUB_SOC_TLB0_29 regMP1_MMHUB_SOC_TLB0_29; -typedef union MP1_MMHUB_SOC_TLB0_30 regMP1_MMHUB_SOC_TLB0_30; -typedef union MP1_MMHUB_SOC_TLB0_31 regMP1_MMHUB_SOC_TLB0_31; -typedef union MP1_MMHUB_SOC_TLB0_32 regMP1_MMHUB_SOC_TLB0_32; -typedef union MP1_MMHUB_SOC_TLB0_33 regMP1_MMHUB_SOC_TLB0_33; -typedef union MP1_MMHUB_SOC_TLB0_34 regMP1_MMHUB_SOC_TLB0_34; -typedef union MP1_MMHUB_SOC_TLB0_35 regMP1_MMHUB_SOC_TLB0_35; -typedef union MP1_MMHUB_SOC_TLB0_36 regMP1_MMHUB_SOC_TLB0_36; -typedef union MP1_MMHUB_SOC_TLB0_37 regMP1_MMHUB_SOC_TLB0_37; -typedef union MP1_MMHUB_SOC_TLB0_38 regMP1_MMHUB_SOC_TLB0_38; -typedef union MP1_MMHUB_SOC_TLB0_39 regMP1_MMHUB_SOC_TLB0_39; -typedef union MP1_MMHUB_SOC_TLB0_40 regMP1_MMHUB_SOC_TLB0_40; -typedef union MP1_MMHUB_SOC_TLB0_41 regMP1_MMHUB_SOC_TLB0_41; -typedef union MP1_MMHUB_SOC_TLB0_42 regMP1_MMHUB_SOC_TLB0_42; -typedef union MP1_MMHUB_SOC_TLB0_43 regMP1_MMHUB_SOC_TLB0_43; -typedef union MP1_MMHUB_SOC_TLB0_44 regMP1_MMHUB_SOC_TLB0_44; -typedef union MP1_MMHUB_SOC_TLB0_45 regMP1_MMHUB_SOC_TLB0_45; -typedef union MP1_MMHUB_SOC_TLB0_46 regMP1_MMHUB_SOC_TLB0_46; -typedef union MP1_MMHUB_SOC_TLB0_47 regMP1_MMHUB_SOC_TLB0_47; -typedef union MP1_MMHUB_SOC_TLB0_48 regMP1_MMHUB_SOC_TLB0_48; -typedef union MP1_MMHUB_SOC_TLB0_49 regMP1_MMHUB_SOC_TLB0_49; -typedef union MP1_MMHUB_SOC_TLB0_50 regMP1_MMHUB_SOC_TLB0_50; -typedef union MP1_MMHUB_SOC_TLB0_51 regMP1_MMHUB_SOC_TLB0_51; -typedef union MP1_MMHUB_SOC_TLB0_52 regMP1_MMHUB_SOC_TLB0_52; -typedef union MP1_MMHUB_SOC_TLB0_53 regMP1_MMHUB_SOC_TLB0_53; -typedef union MP1_MMHUB_SOC_TLB0_54 regMP1_MMHUB_SOC_TLB0_54; -typedef union MP1_MMHUB_SOC_TLB0_55 regMP1_MMHUB_SOC_TLB0_55; -typedef union MP1_MMHUB_SOC_TLB0_56 regMP1_MMHUB_SOC_TLB0_56; -typedef union MP1_MMHUB_SOC_TLB0_57 regMP1_MMHUB_SOC_TLB0_57; -typedef union MP1_MMHUB_SOC_TLB0_58 regMP1_MMHUB_SOC_TLB0_58; -typedef union MP1_MMHUB_SOC_TLB0_59 regMP1_MMHUB_SOC_TLB0_59; -typedef union MP1_MMHUB_SOC_TLB0_60 regMP1_MMHUB_SOC_TLB0_60; -typedef union MP1_MMHUB_SOC_TLB0_61 regMP1_MMHUB_SOC_TLB0_61; -typedef union MP1_MMHUB_SOC_TLB0_62 regMP1_MMHUB_SOC_TLB0_62; -typedef union MP1_MMHUB_SOC_TLB1_1 regMP1_MMHUB_SOC_TLB1_1; -typedef union MP1_MMHUB_SOC_TLB1_2 regMP1_MMHUB_SOC_TLB1_2; -typedef union MP1_MMHUB_SOC_TLB1_3 regMP1_MMHUB_SOC_TLB1_3; -typedef union MP1_MMHUB_SOC_TLB1_4 regMP1_MMHUB_SOC_TLB1_4; -typedef union MP1_MMHUB_SOC_TLB1_5 regMP1_MMHUB_SOC_TLB1_5; -typedef union MP1_MMHUB_SOC_TLB1_6 regMP1_MMHUB_SOC_TLB1_6; -typedef union MP1_MMHUB_SOC_TLB1_7 regMP1_MMHUB_SOC_TLB1_7; -typedef union MP1_MMHUB_SOC_TLB1_8 regMP1_MMHUB_SOC_TLB1_8; -typedef union MP1_MMHUB_SOC_TLB1_9 regMP1_MMHUB_SOC_TLB1_9; -typedef union MP1_MMHUB_SOC_TLB1_10 regMP1_MMHUB_SOC_TLB1_10; -typedef union MP1_MMHUB_SOC_TLB1_11 regMP1_MMHUB_SOC_TLB1_11; -typedef union MP1_MMHUB_SOC_TLB1_12 regMP1_MMHUB_SOC_TLB1_12; -typedef union MP1_MMHUB_SOC_TLB1_13 regMP1_MMHUB_SOC_TLB1_13; -typedef union MP1_MMHUB_SOC_TLB1_14 regMP1_MMHUB_SOC_TLB1_14; -typedef union MP1_MMHUB_SOC_TLB1_15 regMP1_MMHUB_SOC_TLB1_15; -typedef union MP1_MMHUB_SOC_TLB1_16 regMP1_MMHUB_SOC_TLB1_16; -typedef union MP1_MMHUB_SOC_TLB1_17 regMP1_MMHUB_SOC_TLB1_17; -typedef union MP1_MMHUB_SOC_TLB1_18 regMP1_MMHUB_SOC_TLB1_18; -typedef union MP1_MMHUB_SOC_TLB1_19 regMP1_MMHUB_SOC_TLB1_19; -typedef union MP1_MMHUB_SOC_TLB1_20 regMP1_MMHUB_SOC_TLB1_20; -typedef union MP1_MMHUB_SOC_TLB1_21 regMP1_MMHUB_SOC_TLB1_21; -typedef union MP1_MMHUB_SOC_TLB1_22 regMP1_MMHUB_SOC_TLB1_22; -typedef union MP1_MMHUB_SOC_TLB1_23 regMP1_MMHUB_SOC_TLB1_23; -typedef union MP1_MMHUB_SOC_TLB1_24 regMP1_MMHUB_SOC_TLB1_24; -typedef union MP1_MMHUB_SOC_TLB1_25 regMP1_MMHUB_SOC_TLB1_25; -typedef union MP1_MMHUB_SOC_TLB1_26 regMP1_MMHUB_SOC_TLB1_26; -typedef union MP1_MMHUB_SOC_TLB1_27 regMP1_MMHUB_SOC_TLB1_27; -typedef union MP1_MMHUB_SOC_TLB1_28 regMP1_MMHUB_SOC_TLB1_28; -typedef union MP1_MMHUB_SOC_TLB1_29 regMP1_MMHUB_SOC_TLB1_29; -typedef union MP1_MMHUB_SOC_TLB1_30 regMP1_MMHUB_SOC_TLB1_30; -typedef union MP1_MMHUB_SOC_TLB1_31 regMP1_MMHUB_SOC_TLB1_31; -typedef union MP1_MMHUB_SOC_TLB1_32 regMP1_MMHUB_SOC_TLB1_32; -typedef union MP1_MMHUB_SOC_TLB1_33 regMP1_MMHUB_SOC_TLB1_33; -typedef union MP1_MMHUB_SOC_TLB1_34 regMP1_MMHUB_SOC_TLB1_34; -typedef union MP1_MMHUB_SOC_TLB1_35 regMP1_MMHUB_SOC_TLB1_35; -typedef union MP1_MMHUB_SOC_TLB1_36 regMP1_MMHUB_SOC_TLB1_36; -typedef union MP1_MMHUB_SOC_TLB1_37 regMP1_MMHUB_SOC_TLB1_37; -typedef union MP1_MMHUB_SOC_TLB1_38 regMP1_MMHUB_SOC_TLB1_38; -typedef union MP1_MMHUB_SOC_TLB1_39 regMP1_MMHUB_SOC_TLB1_39; -typedef union MP1_MMHUB_SOC_TLB1_40 regMP1_MMHUB_SOC_TLB1_40; -typedef union MP1_MMHUB_SOC_TLB1_41 regMP1_MMHUB_SOC_TLB1_41; -typedef union MP1_MMHUB_SOC_TLB1_42 regMP1_MMHUB_SOC_TLB1_42; -typedef union MP1_MMHUB_SOC_TLB1_43 regMP1_MMHUB_SOC_TLB1_43; -typedef union MP1_MMHUB_SOC_TLB1_44 regMP1_MMHUB_SOC_TLB1_44; -typedef union MP1_MMHUB_SOC_TLB1_45 regMP1_MMHUB_SOC_TLB1_45; -typedef union MP1_MMHUB_SOC_TLB1_46 regMP1_MMHUB_SOC_TLB1_46; -typedef union MP1_MMHUB_SOC_TLB1_47 regMP1_MMHUB_SOC_TLB1_47; -typedef union MP1_MMHUB_SOC_TLB1_48 regMP1_MMHUB_SOC_TLB1_48; -typedef union MP1_MMHUB_SOC_TLB1_49 regMP1_MMHUB_SOC_TLB1_49; -typedef union MP1_MMHUB_SOC_TLB1_50 regMP1_MMHUB_SOC_TLB1_50; -typedef union MP1_MMHUB_SOC_TLB1_51 regMP1_MMHUB_SOC_TLB1_51; -typedef union MP1_MMHUB_SOC_TLB1_52 regMP1_MMHUB_SOC_TLB1_52; -typedef union MP1_MMHUB_SOC_TLB1_53 regMP1_MMHUB_SOC_TLB1_53; -typedef union MP1_MMHUB_SOC_TLB1_54 regMP1_MMHUB_SOC_TLB1_54; -typedef union MP1_MMHUB_SOC_TLB1_55 regMP1_MMHUB_SOC_TLB1_55; -typedef union MP1_MMHUB_SOC_TLB1_56 regMP1_MMHUB_SOC_TLB1_56; -typedef union MP1_MMHUB_SOC_TLB1_57 regMP1_MMHUB_SOC_TLB1_57; -typedef union MP1_MMHUB_SOC_TLB1_58 regMP1_MMHUB_SOC_TLB1_58; -typedef union MP1_MMHUB_SOC_TLB1_59 regMP1_MMHUB_SOC_TLB1_59; -typedef union MP1_MMHUB_SOC_TLB1_60 regMP1_MMHUB_SOC_TLB1_60; -typedef union MP1_MMHUB_SOC_TLB1_61 regMP1_MMHUB_SOC_TLB1_61; -typedef union MP1_MMHUB_SOC_TLB1_62 regMP1_MMHUB_SOC_TLB1_62; -typedef union MP1_MMHUB_SOC_TLB2_1 regMP1_MMHUB_SOC_TLB2_1; -typedef union MP1_MMHUB_SOC_TLB2_2 regMP1_MMHUB_SOC_TLB2_2; -typedef union MP1_MMHUB_SOC_TLB2_3 regMP1_MMHUB_SOC_TLB2_3; -typedef union MP1_MMHUB_SOC_TLB2_4 regMP1_MMHUB_SOC_TLB2_4; -typedef union MP1_MMHUB_SOC_TLB2_5 regMP1_MMHUB_SOC_TLB2_5; -typedef union MP1_MMHUB_SOC_TLB2_6 regMP1_MMHUB_SOC_TLB2_6; -typedef union MP1_MMHUB_SOC_TLB2_7 regMP1_MMHUB_SOC_TLB2_7; -typedef union MP1_MMHUB_SOC_TLB2_8 regMP1_MMHUB_SOC_TLB2_8; -typedef union MP1_MMHUB_SOC_TLB2_9 regMP1_MMHUB_SOC_TLB2_9; -typedef union MP1_MMHUB_SOC_TLB2_10 regMP1_MMHUB_SOC_TLB2_10; -typedef union MP1_MMHUB_SOC_TLB2_11 regMP1_MMHUB_SOC_TLB2_11; -typedef union MP1_MMHUB_SOC_TLB2_12 regMP1_MMHUB_SOC_TLB2_12; -typedef union MP1_MMHUB_SOC_TLB2_13 regMP1_MMHUB_SOC_TLB2_13; -typedef union MP1_MMHUB_SOC_TLB2_14 regMP1_MMHUB_SOC_TLB2_14; -typedef union MP1_MMHUB_SOC_TLB2_15 regMP1_MMHUB_SOC_TLB2_15; -typedef union MP1_MMHUB_SOC_TLB2_16 regMP1_MMHUB_SOC_TLB2_16; -typedef union MP1_MMHUB_SOC_TLB2_17 regMP1_MMHUB_SOC_TLB2_17; -typedef union MP1_MMHUB_SOC_TLB2_18 regMP1_MMHUB_SOC_TLB2_18; -typedef union MP1_MMHUB_SOC_TLB2_19 regMP1_MMHUB_SOC_TLB2_19; -typedef union MP1_MMHUB_SOC_TLB2_20 regMP1_MMHUB_SOC_TLB2_20; -typedef union MP1_MMHUB_SOC_TLB2_21 regMP1_MMHUB_SOC_TLB2_21; -typedef union MP1_MMHUB_SOC_TLB2_22 regMP1_MMHUB_SOC_TLB2_22; -typedef union MP1_MMHUB_SOC_TLB2_23 regMP1_MMHUB_SOC_TLB2_23; -typedef union MP1_MMHUB_SOC_TLB2_24 regMP1_MMHUB_SOC_TLB2_24; -typedef union MP1_MMHUB_SOC_TLB2_25 regMP1_MMHUB_SOC_TLB2_25; -typedef union MP1_MMHUB_SOC_TLB2_26 regMP1_MMHUB_SOC_TLB2_26; -typedef union MP1_MMHUB_SOC_TLB2_27 regMP1_MMHUB_SOC_TLB2_27; -typedef union MP1_MMHUB_SOC_TLB2_28 regMP1_MMHUB_SOC_TLB2_28; -typedef union MP1_MMHUB_SOC_TLB2_29 regMP1_MMHUB_SOC_TLB2_29; -typedef union MP1_MMHUB_SOC_TLB2_30 regMP1_MMHUB_SOC_TLB2_30; -typedef union MP1_MMHUB_SOC_TLB2_31 regMP1_MMHUB_SOC_TLB2_31; -typedef union MP1_MMHUB_SOC_TLB2_32 regMP1_MMHUB_SOC_TLB2_32; -typedef union MP1_MMHUB_SOC_TLB2_33 regMP1_MMHUB_SOC_TLB2_33; -typedef union MP1_MMHUB_SOC_TLB2_34 regMP1_MMHUB_SOC_TLB2_34; -typedef union MP1_MMHUB_SOC_TLB2_35 regMP1_MMHUB_SOC_TLB2_35; -typedef union MP1_MMHUB_SOC_TLB2_36 regMP1_MMHUB_SOC_TLB2_36; -typedef union MP1_MMHUB_SOC_TLB2_37 regMP1_MMHUB_SOC_TLB2_37; -typedef union MP1_MMHUB_SOC_TLB2_38 regMP1_MMHUB_SOC_TLB2_38; -typedef union MP1_MMHUB_SOC_TLB2_39 regMP1_MMHUB_SOC_TLB2_39; -typedef union MP1_MMHUB_SOC_TLB2_40 regMP1_MMHUB_SOC_TLB2_40; -typedef union MP1_MMHUB_SOC_TLB2_41 regMP1_MMHUB_SOC_TLB2_41; -typedef union MP1_MMHUB_SOC_TLB2_42 regMP1_MMHUB_SOC_TLB2_42; -typedef union MP1_MMHUB_SOC_TLB2_43 regMP1_MMHUB_SOC_TLB2_43; -typedef union MP1_MMHUB_SOC_TLB2_44 regMP1_MMHUB_SOC_TLB2_44; -typedef union MP1_MMHUB_SOC_TLB2_45 regMP1_MMHUB_SOC_TLB2_45; -typedef union MP1_MMHUB_SOC_TLB2_46 regMP1_MMHUB_SOC_TLB2_46; -typedef union MP1_MMHUB_SOC_TLB2_47 regMP1_MMHUB_SOC_TLB2_47; -typedef union MP1_MMHUB_SOC_TLB2_48 regMP1_MMHUB_SOC_TLB2_48; -typedef union MP1_MMHUB_SOC_TLB2_49 regMP1_MMHUB_SOC_TLB2_49; -typedef union MP1_MMHUB_SOC_TLB2_50 regMP1_MMHUB_SOC_TLB2_50; -typedef union MP1_MMHUB_SOC_TLB2_51 regMP1_MMHUB_SOC_TLB2_51; -typedef union MP1_MMHUB_SOC_TLB2_52 regMP1_MMHUB_SOC_TLB2_52; -typedef union MP1_MMHUB_SOC_TLB2_53 regMP1_MMHUB_SOC_TLB2_53; -typedef union MP1_MMHUB_SOC_TLB2_54 regMP1_MMHUB_SOC_TLB2_54; -typedef union MP1_MMHUB_SOC_TLB2_55 regMP1_MMHUB_SOC_TLB2_55; -typedef union MP1_MMHUB_SOC_TLB2_56 regMP1_MMHUB_SOC_TLB2_56; -typedef union MP1_MMHUB_SOC_TLB2_57 regMP1_MMHUB_SOC_TLB2_57; -typedef union MP1_MMHUB_SOC_TLB2_58 regMP1_MMHUB_SOC_TLB2_58; -typedef union MP1_MMHUB_SOC_TLB2_59 regMP1_MMHUB_SOC_TLB2_59; -typedef union MP1_MMHUB_SOC_TLB2_60 regMP1_MMHUB_SOC_TLB2_60; -typedef union MP1_MMHUB_SOC_TLB2_61 regMP1_MMHUB_SOC_TLB2_61; -typedef union MP1_MMHUB_SOC_TLB2_62 regMP1_MMHUB_SOC_TLB2_62; -typedef union MP1_MMHUB_SOC_TLB3_1 regMP1_MMHUB_SOC_TLB3_1; -typedef union MP1_MMHUB_SOC_TLB3_2 regMP1_MMHUB_SOC_TLB3_2; -typedef union MP1_MMHUB_SOC_TLB3_3 regMP1_MMHUB_SOC_TLB3_3; -typedef union MP1_MMHUB_SOC_TLB3_4 regMP1_MMHUB_SOC_TLB3_4; -typedef union MP1_MMHUB_SOC_TLB3_5 regMP1_MMHUB_SOC_TLB3_5; -typedef union MP1_MMHUB_SOC_TLB3_6 regMP1_MMHUB_SOC_TLB3_6; -typedef union MP1_MMHUB_SOC_TLB3_7 regMP1_MMHUB_SOC_TLB3_7; -typedef union MP1_MMHUB_SOC_TLB3_8 regMP1_MMHUB_SOC_TLB3_8; -typedef union MP1_MMHUB_SOC_TLB3_9 regMP1_MMHUB_SOC_TLB3_9; -typedef union MP1_MMHUB_SOC_TLB3_10 regMP1_MMHUB_SOC_TLB3_10; -typedef union MP1_MMHUB_SOC_TLB3_11 regMP1_MMHUB_SOC_TLB3_11; -typedef union MP1_MMHUB_SOC_TLB3_12 regMP1_MMHUB_SOC_TLB3_12; -typedef union MP1_MMHUB_SOC_TLB3_13 regMP1_MMHUB_SOC_TLB3_13; -typedef union MP1_MMHUB_SOC_TLB3_14 regMP1_MMHUB_SOC_TLB3_14; -typedef union MP1_MMHUB_SOC_TLB3_15 regMP1_MMHUB_SOC_TLB3_15; -typedef union MP1_MMHUB_SOC_TLB3_16 regMP1_MMHUB_SOC_TLB3_16; -typedef union MP1_MMHUB_SOC_TLB3_17 regMP1_MMHUB_SOC_TLB3_17; -typedef union MP1_MMHUB_SOC_TLB3_18 regMP1_MMHUB_SOC_TLB3_18; -typedef union MP1_MMHUB_SOC_TLB3_19 regMP1_MMHUB_SOC_TLB3_19; -typedef union MP1_MMHUB_SOC_TLB3_20 regMP1_MMHUB_SOC_TLB3_20; -typedef union MP1_MMHUB_SOC_TLB3_21 regMP1_MMHUB_SOC_TLB3_21; -typedef union MP1_MMHUB_SOC_TLB3_22 regMP1_MMHUB_SOC_TLB3_22; -typedef union MP1_MMHUB_SOC_TLB3_23 regMP1_MMHUB_SOC_TLB3_23; -typedef union MP1_MMHUB_SOC_TLB3_24 regMP1_MMHUB_SOC_TLB3_24; -typedef union MP1_MMHUB_SOC_TLB3_25 regMP1_MMHUB_SOC_TLB3_25; -typedef union MP1_MMHUB_SOC_TLB3_26 regMP1_MMHUB_SOC_TLB3_26; -typedef union MP1_MMHUB_SOC_TLB3_27 regMP1_MMHUB_SOC_TLB3_27; -typedef union MP1_MMHUB_SOC_TLB3_28 regMP1_MMHUB_SOC_TLB3_28; -typedef union MP1_MMHUB_SOC_TLB3_29 regMP1_MMHUB_SOC_TLB3_29; -typedef union MP1_MMHUB_SOC_TLB3_30 regMP1_MMHUB_SOC_TLB3_30; -typedef union MP1_MMHUB_SOC_TLB3_31 regMP1_MMHUB_SOC_TLB3_31; -typedef union MP1_MMHUB_SOC_TLB3_32 regMP1_MMHUB_SOC_TLB3_32; -typedef union MP1_MMHUB_SOC_TLB3_33 regMP1_MMHUB_SOC_TLB3_33; -typedef union MP1_MMHUB_SOC_TLB3_34 regMP1_MMHUB_SOC_TLB3_34; -typedef union MP1_MMHUB_SOC_TLB3_35 regMP1_MMHUB_SOC_TLB3_35; -typedef union MP1_MMHUB_SOC_TLB3_36 regMP1_MMHUB_SOC_TLB3_36; -typedef union MP1_MMHUB_SOC_TLB3_37 regMP1_MMHUB_SOC_TLB3_37; -typedef union MP1_MMHUB_SOC_TLB3_38 regMP1_MMHUB_SOC_TLB3_38; -typedef union MP1_MMHUB_SOC_TLB3_39 regMP1_MMHUB_SOC_TLB3_39; -typedef union MP1_MMHUB_SOC_TLB3_40 regMP1_MMHUB_SOC_TLB3_40; -typedef union MP1_MMHUB_SOC_TLB3_41 regMP1_MMHUB_SOC_TLB3_41; -typedef union MP1_MMHUB_SOC_TLB3_42 regMP1_MMHUB_SOC_TLB3_42; -typedef union MP1_MMHUB_SOC_TLB3_43 regMP1_MMHUB_SOC_TLB3_43; -typedef union MP1_MMHUB_SOC_TLB3_44 regMP1_MMHUB_SOC_TLB3_44; -typedef union MP1_MMHUB_SOC_TLB3_45 regMP1_MMHUB_SOC_TLB3_45; -typedef union MP1_MMHUB_SOC_TLB3_46 regMP1_MMHUB_SOC_TLB3_46; -typedef union MP1_MMHUB_SOC_TLB3_47 regMP1_MMHUB_SOC_TLB3_47; -typedef union MP1_MMHUB_SOC_TLB3_48 regMP1_MMHUB_SOC_TLB3_48; -typedef union MP1_MMHUB_SOC_TLB3_49 regMP1_MMHUB_SOC_TLB3_49; -typedef union MP1_MMHUB_SOC_TLB3_50 regMP1_MMHUB_SOC_TLB3_50; -typedef union MP1_MMHUB_SOC_TLB3_51 regMP1_MMHUB_SOC_TLB3_51; -typedef union MP1_MMHUB_SOC_TLB3_52 regMP1_MMHUB_SOC_TLB3_52; -typedef union MP1_MMHUB_SOC_TLB3_53 regMP1_MMHUB_SOC_TLB3_53; -typedef union MP1_MMHUB_SOC_TLB3_54 regMP1_MMHUB_SOC_TLB3_54; -typedef union MP1_MMHUB_SOC_TLB3_55 regMP1_MMHUB_SOC_TLB3_55; -typedef union MP1_MMHUB_SOC_TLB3_56 regMP1_MMHUB_SOC_TLB3_56; -typedef union MP1_MMHUB_SOC_TLB3_57 regMP1_MMHUB_SOC_TLB3_57; -typedef union MP1_MMHUB_SOC_TLB3_58 regMP1_MMHUB_SOC_TLB3_58; -typedef union MP1_MMHUB_SOC_TLB3_59 regMP1_MMHUB_SOC_TLB3_59; -typedef union MP1_MMHUB_SOC_TLB3_60 regMP1_MMHUB_SOC_TLB3_60; -typedef union MP1_MMHUB_SOC_TLB3_61 regMP1_MMHUB_SOC_TLB3_61; -typedef union MP1_MMHUB_SOC_TLB3_62 regMP1_MMHUB_SOC_TLB3_62; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61; -typedef union MP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 regMP1_MMHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_1 regMP1_MMHUB_TLB_ATTRIBUTE_1; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_2 regMP1_MMHUB_TLB_ATTRIBUTE_2; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_3 regMP1_MMHUB_TLB_ATTRIBUTE_3; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_4 regMP1_MMHUB_TLB_ATTRIBUTE_4; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_5 regMP1_MMHUB_TLB_ATTRIBUTE_5; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_6 regMP1_MMHUB_TLB_ATTRIBUTE_6; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_7 regMP1_MMHUB_TLB_ATTRIBUTE_7; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_8 regMP1_MMHUB_TLB_ATTRIBUTE_8; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_9 regMP1_MMHUB_TLB_ATTRIBUTE_9; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_10 regMP1_MMHUB_TLB_ATTRIBUTE_10; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_11 regMP1_MMHUB_TLB_ATTRIBUTE_11; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_12 regMP1_MMHUB_TLB_ATTRIBUTE_12; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_13 regMP1_MMHUB_TLB_ATTRIBUTE_13; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_14 regMP1_MMHUB_TLB_ATTRIBUTE_14; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_15 regMP1_MMHUB_TLB_ATTRIBUTE_15; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_16 regMP1_MMHUB_TLB_ATTRIBUTE_16; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_17 regMP1_MMHUB_TLB_ATTRIBUTE_17; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_18 regMP1_MMHUB_TLB_ATTRIBUTE_18; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_19 regMP1_MMHUB_TLB_ATTRIBUTE_19; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_20 regMP1_MMHUB_TLB_ATTRIBUTE_20; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_21 regMP1_MMHUB_TLB_ATTRIBUTE_21; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_22 regMP1_MMHUB_TLB_ATTRIBUTE_22; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_23 regMP1_MMHUB_TLB_ATTRIBUTE_23; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_24 regMP1_MMHUB_TLB_ATTRIBUTE_24; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_25 regMP1_MMHUB_TLB_ATTRIBUTE_25; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_26 regMP1_MMHUB_TLB_ATTRIBUTE_26; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_27 regMP1_MMHUB_TLB_ATTRIBUTE_27; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_28 regMP1_MMHUB_TLB_ATTRIBUTE_28; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_29 regMP1_MMHUB_TLB_ATTRIBUTE_29; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_30 regMP1_MMHUB_TLB_ATTRIBUTE_30; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_31 regMP1_MMHUB_TLB_ATTRIBUTE_31; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_32 regMP1_MMHUB_TLB_ATTRIBUTE_32; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_33 regMP1_MMHUB_TLB_ATTRIBUTE_33; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_34 regMP1_MMHUB_TLB_ATTRIBUTE_34; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_35 regMP1_MMHUB_TLB_ATTRIBUTE_35; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_36 regMP1_MMHUB_TLB_ATTRIBUTE_36; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_37 regMP1_MMHUB_TLB_ATTRIBUTE_37; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_38 regMP1_MMHUB_TLB_ATTRIBUTE_38; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_39 regMP1_MMHUB_TLB_ATTRIBUTE_39; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_40 regMP1_MMHUB_TLB_ATTRIBUTE_40; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_41 regMP1_MMHUB_TLB_ATTRIBUTE_41; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_42 regMP1_MMHUB_TLB_ATTRIBUTE_42; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_43 regMP1_MMHUB_TLB_ATTRIBUTE_43; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_44 regMP1_MMHUB_TLB_ATTRIBUTE_44; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_45 regMP1_MMHUB_TLB_ATTRIBUTE_45; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_46 regMP1_MMHUB_TLB_ATTRIBUTE_46; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_47 regMP1_MMHUB_TLB_ATTRIBUTE_47; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_48 regMP1_MMHUB_TLB_ATTRIBUTE_48; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_49 regMP1_MMHUB_TLB_ATTRIBUTE_49; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_50 regMP1_MMHUB_TLB_ATTRIBUTE_50; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_51 regMP1_MMHUB_TLB_ATTRIBUTE_51; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_52 regMP1_MMHUB_TLB_ATTRIBUTE_52; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_53 regMP1_MMHUB_TLB_ATTRIBUTE_53; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_54 regMP1_MMHUB_TLB_ATTRIBUTE_54; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_55 regMP1_MMHUB_TLB_ATTRIBUTE_55; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_56 regMP1_MMHUB_TLB_ATTRIBUTE_56; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_57 regMP1_MMHUB_TLB_ATTRIBUTE_57; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_58 regMP1_MMHUB_TLB_ATTRIBUTE_58; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_59 regMP1_MMHUB_TLB_ATTRIBUTE_59; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_60 regMP1_MMHUB_TLB_ATTRIBUTE_60; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_61 regMP1_MMHUB_TLB_ATTRIBUTE_61; -typedef union MP1_MMHUB_TLB_ATTRIBUTE_62 regMP1_MMHUB_TLB_ATTRIBUTE_62; -typedef union MP1_MMHUB_INT_STATUS regMP1_MMHUB_INT_STATUS; -typedef union MP1_MMHUB_WR_INT_ADDR regMP1_MMHUB_WR_INT_ADDR; -typedef union MP1_MMHUB_WR_INT_OTHER regMP1_MMHUB_WR_INT_OTHER; -typedef union MP1_MMHUB_RD_INT_ADDR regMP1_MMHUB_RD_INT_ADDR; -typedef union MP1_MMHUB_RD_INT_OTHER regMP1_MMHUB_RD_INT_OTHER; -typedef union MP1_MMHUB_REG_INT_ADDR regMP1_MMHUB_REG_INT_ADDR; -typedef union MP1_MMHUB_REG_INT_OTHER regMP1_MMHUB_REG_INT_OTHER; -typedef union MP1_MMHUB_AXCACHE_CFG regMP1_MMHUB_AXCACHE_CFG; -typedef union MP1_MMHUB_DS_OVERRIDE regMP1_MMHUB_DS_OVERRIDE; -typedef union MP1_MMHUB_OUTSTANDING regMP1_MMHUB_OUTSTANDING; -typedef union MP1_SYSHUB_SOC_TLB0_1 regMP1_SYSHUB_SOC_TLB0_1; -typedef union MP1_SYSHUB_SOC_TLB0_2 regMP1_SYSHUB_SOC_TLB0_2; -typedef union MP1_SYSHUB_SOC_TLB0_3 regMP1_SYSHUB_SOC_TLB0_3; -typedef union MP1_SYSHUB_SOC_TLB0_4 regMP1_SYSHUB_SOC_TLB0_4; -typedef union MP1_SYSHUB_SOC_TLB0_5 regMP1_SYSHUB_SOC_TLB0_5; -typedef union MP1_SYSHUB_SOC_TLB0_6 regMP1_SYSHUB_SOC_TLB0_6; -typedef union MP1_SYSHUB_SOC_TLB0_7 regMP1_SYSHUB_SOC_TLB0_7; -typedef union MP1_SYSHUB_SOC_TLB0_8 regMP1_SYSHUB_SOC_TLB0_8; -typedef union MP1_SYSHUB_SOC_TLB0_9 regMP1_SYSHUB_SOC_TLB0_9; -typedef union MP1_SYSHUB_SOC_TLB0_10 regMP1_SYSHUB_SOC_TLB0_10; -typedef union MP1_SYSHUB_SOC_TLB0_11 regMP1_SYSHUB_SOC_TLB0_11; -typedef union MP1_SYSHUB_SOC_TLB0_12 regMP1_SYSHUB_SOC_TLB0_12; -typedef union MP1_SYSHUB_SOC_TLB0_13 regMP1_SYSHUB_SOC_TLB0_13; -typedef union MP1_SYSHUB_SOC_TLB0_14 regMP1_SYSHUB_SOC_TLB0_14; -typedef union MP1_SYSHUB_SOC_TLB0_15 regMP1_SYSHUB_SOC_TLB0_15; -typedef union MP1_SYSHUB_SOC_TLB0_16 regMP1_SYSHUB_SOC_TLB0_16; -typedef union MP1_SYSHUB_SOC_TLB0_17 regMP1_SYSHUB_SOC_TLB0_17; -typedef union MP1_SYSHUB_SOC_TLB0_18 regMP1_SYSHUB_SOC_TLB0_18; -typedef union MP1_SYSHUB_SOC_TLB0_19 regMP1_SYSHUB_SOC_TLB0_19; -typedef union MP1_SYSHUB_SOC_TLB0_20 regMP1_SYSHUB_SOC_TLB0_20; -typedef union MP1_SYSHUB_SOC_TLB0_21 regMP1_SYSHUB_SOC_TLB0_21; -typedef union MP1_SYSHUB_SOC_TLB0_22 regMP1_SYSHUB_SOC_TLB0_22; -typedef union MP1_SYSHUB_SOC_TLB0_23 regMP1_SYSHUB_SOC_TLB0_23; -typedef union MP1_SYSHUB_SOC_TLB0_24 regMP1_SYSHUB_SOC_TLB0_24; -typedef union MP1_SYSHUB_SOC_TLB0_25 regMP1_SYSHUB_SOC_TLB0_25; -typedef union MP1_SYSHUB_SOC_TLB0_26 regMP1_SYSHUB_SOC_TLB0_26; -typedef union MP1_SYSHUB_SOC_TLB0_27 regMP1_SYSHUB_SOC_TLB0_27; -typedef union MP1_SYSHUB_SOC_TLB0_28 regMP1_SYSHUB_SOC_TLB0_28; -typedef union MP1_SYSHUB_SOC_TLB0_29 regMP1_SYSHUB_SOC_TLB0_29; -typedef union MP1_SYSHUB_SOC_TLB0_30 regMP1_SYSHUB_SOC_TLB0_30; -typedef union MP1_SYSHUB_SOC_TLB0_31 regMP1_SYSHUB_SOC_TLB0_31; -typedef union MP1_SYSHUB_SOC_TLB0_32 regMP1_SYSHUB_SOC_TLB0_32; -typedef union MP1_SYSHUB_SOC_TLB0_33 regMP1_SYSHUB_SOC_TLB0_33; -typedef union MP1_SYSHUB_SOC_TLB0_34 regMP1_SYSHUB_SOC_TLB0_34; -typedef union MP1_SYSHUB_SOC_TLB0_35 regMP1_SYSHUB_SOC_TLB0_35; -typedef union MP1_SYSHUB_SOC_TLB0_36 regMP1_SYSHUB_SOC_TLB0_36; -typedef union MP1_SYSHUB_SOC_TLB0_37 regMP1_SYSHUB_SOC_TLB0_37; -typedef union MP1_SYSHUB_SOC_TLB0_38 regMP1_SYSHUB_SOC_TLB0_38; -typedef union MP1_SYSHUB_SOC_TLB0_39 regMP1_SYSHUB_SOC_TLB0_39; -typedef union MP1_SYSHUB_SOC_TLB0_40 regMP1_SYSHUB_SOC_TLB0_40; -typedef union MP1_SYSHUB_SOC_TLB0_41 regMP1_SYSHUB_SOC_TLB0_41; -typedef union MP1_SYSHUB_SOC_TLB0_42 regMP1_SYSHUB_SOC_TLB0_42; -typedef union MP1_SYSHUB_SOC_TLB0_43 regMP1_SYSHUB_SOC_TLB0_43; -typedef union MP1_SYSHUB_SOC_TLB0_44 regMP1_SYSHUB_SOC_TLB0_44; -typedef union MP1_SYSHUB_SOC_TLB0_45 regMP1_SYSHUB_SOC_TLB0_45; -typedef union MP1_SYSHUB_SOC_TLB0_46 regMP1_SYSHUB_SOC_TLB0_46; -typedef union MP1_SYSHUB_SOC_TLB0_47 regMP1_SYSHUB_SOC_TLB0_47; -typedef union MP1_SYSHUB_SOC_TLB0_48 regMP1_SYSHUB_SOC_TLB0_48; -typedef union MP1_SYSHUB_SOC_TLB0_49 regMP1_SYSHUB_SOC_TLB0_49; -typedef union MP1_SYSHUB_SOC_TLB0_50 regMP1_SYSHUB_SOC_TLB0_50; -typedef union MP1_SYSHUB_SOC_TLB0_51 regMP1_SYSHUB_SOC_TLB0_51; -typedef union MP1_SYSHUB_SOC_TLB0_52 regMP1_SYSHUB_SOC_TLB0_52; -typedef union MP1_SYSHUB_SOC_TLB0_53 regMP1_SYSHUB_SOC_TLB0_53; -typedef union MP1_SYSHUB_SOC_TLB0_54 regMP1_SYSHUB_SOC_TLB0_54; -typedef union MP1_SYSHUB_SOC_TLB0_55 regMP1_SYSHUB_SOC_TLB0_55; -typedef union MP1_SYSHUB_SOC_TLB0_56 regMP1_SYSHUB_SOC_TLB0_56; -typedef union MP1_SYSHUB_SOC_TLB0_57 regMP1_SYSHUB_SOC_TLB0_57; -typedef union MP1_SYSHUB_SOC_TLB0_58 regMP1_SYSHUB_SOC_TLB0_58; -typedef union MP1_SYSHUB_SOC_TLB0_59 regMP1_SYSHUB_SOC_TLB0_59; -typedef union MP1_SYSHUB_SOC_TLB0_60 regMP1_SYSHUB_SOC_TLB0_60; -typedef union MP1_SYSHUB_SOC_TLB0_61 regMP1_SYSHUB_SOC_TLB0_61; -typedef union MP1_SYSHUB_SOC_TLB0_62 regMP1_SYSHUB_SOC_TLB0_62; -typedef union MP1_SYSHUB_SOC_TLB1_1 regMP1_SYSHUB_SOC_TLB1_1; -typedef union MP1_SYSHUB_SOC_TLB1_2 regMP1_SYSHUB_SOC_TLB1_2; -typedef union MP1_SYSHUB_SOC_TLB1_3 regMP1_SYSHUB_SOC_TLB1_3; -typedef union MP1_SYSHUB_SOC_TLB1_4 regMP1_SYSHUB_SOC_TLB1_4; -typedef union MP1_SYSHUB_SOC_TLB1_5 regMP1_SYSHUB_SOC_TLB1_5; -typedef union MP1_SYSHUB_SOC_TLB1_6 regMP1_SYSHUB_SOC_TLB1_6; -typedef union MP1_SYSHUB_SOC_TLB1_7 regMP1_SYSHUB_SOC_TLB1_7; -typedef union MP1_SYSHUB_SOC_TLB1_8 regMP1_SYSHUB_SOC_TLB1_8; -typedef union MP1_SYSHUB_SOC_TLB1_9 regMP1_SYSHUB_SOC_TLB1_9; -typedef union MP1_SYSHUB_SOC_TLB1_10 regMP1_SYSHUB_SOC_TLB1_10; -typedef union MP1_SYSHUB_SOC_TLB1_11 regMP1_SYSHUB_SOC_TLB1_11; -typedef union MP1_SYSHUB_SOC_TLB1_12 regMP1_SYSHUB_SOC_TLB1_12; -typedef union MP1_SYSHUB_SOC_TLB1_13 regMP1_SYSHUB_SOC_TLB1_13; -typedef union MP1_SYSHUB_SOC_TLB1_14 regMP1_SYSHUB_SOC_TLB1_14; -typedef union MP1_SYSHUB_SOC_TLB1_15 regMP1_SYSHUB_SOC_TLB1_15; -typedef union MP1_SYSHUB_SOC_TLB1_16 regMP1_SYSHUB_SOC_TLB1_16; -typedef union MP1_SYSHUB_SOC_TLB1_17 regMP1_SYSHUB_SOC_TLB1_17; -typedef union MP1_SYSHUB_SOC_TLB1_18 regMP1_SYSHUB_SOC_TLB1_18; -typedef union MP1_SYSHUB_SOC_TLB1_19 regMP1_SYSHUB_SOC_TLB1_19; -typedef union MP1_SYSHUB_SOC_TLB1_20 regMP1_SYSHUB_SOC_TLB1_20; -typedef union MP1_SYSHUB_SOC_TLB1_21 regMP1_SYSHUB_SOC_TLB1_21; -typedef union MP1_SYSHUB_SOC_TLB1_22 regMP1_SYSHUB_SOC_TLB1_22; -typedef union MP1_SYSHUB_SOC_TLB1_23 regMP1_SYSHUB_SOC_TLB1_23; -typedef union MP1_SYSHUB_SOC_TLB1_24 regMP1_SYSHUB_SOC_TLB1_24; -typedef union MP1_SYSHUB_SOC_TLB1_25 regMP1_SYSHUB_SOC_TLB1_25; -typedef union MP1_SYSHUB_SOC_TLB1_26 regMP1_SYSHUB_SOC_TLB1_26; -typedef union MP1_SYSHUB_SOC_TLB1_27 regMP1_SYSHUB_SOC_TLB1_27; -typedef union MP1_SYSHUB_SOC_TLB1_28 regMP1_SYSHUB_SOC_TLB1_28; -typedef union MP1_SYSHUB_SOC_TLB1_29 regMP1_SYSHUB_SOC_TLB1_29; -typedef union MP1_SYSHUB_SOC_TLB1_30 regMP1_SYSHUB_SOC_TLB1_30; -typedef union MP1_SYSHUB_SOC_TLB1_31 regMP1_SYSHUB_SOC_TLB1_31; -typedef union MP1_SYSHUB_SOC_TLB1_32 regMP1_SYSHUB_SOC_TLB1_32; -typedef union MP1_SYSHUB_SOC_TLB1_33 regMP1_SYSHUB_SOC_TLB1_33; -typedef union MP1_SYSHUB_SOC_TLB1_34 regMP1_SYSHUB_SOC_TLB1_34; -typedef union MP1_SYSHUB_SOC_TLB1_35 regMP1_SYSHUB_SOC_TLB1_35; -typedef union MP1_SYSHUB_SOC_TLB1_36 regMP1_SYSHUB_SOC_TLB1_36; -typedef union MP1_SYSHUB_SOC_TLB1_37 regMP1_SYSHUB_SOC_TLB1_37; -typedef union MP1_SYSHUB_SOC_TLB1_38 regMP1_SYSHUB_SOC_TLB1_38; -typedef union MP1_SYSHUB_SOC_TLB1_39 regMP1_SYSHUB_SOC_TLB1_39; -typedef union MP1_SYSHUB_SOC_TLB1_40 regMP1_SYSHUB_SOC_TLB1_40; -typedef union MP1_SYSHUB_SOC_TLB1_41 regMP1_SYSHUB_SOC_TLB1_41; -typedef union MP1_SYSHUB_SOC_TLB1_42 regMP1_SYSHUB_SOC_TLB1_42; -typedef union MP1_SYSHUB_SOC_TLB1_43 regMP1_SYSHUB_SOC_TLB1_43; -typedef union MP1_SYSHUB_SOC_TLB1_44 regMP1_SYSHUB_SOC_TLB1_44; -typedef union MP1_SYSHUB_SOC_TLB1_45 regMP1_SYSHUB_SOC_TLB1_45; -typedef union MP1_SYSHUB_SOC_TLB1_46 regMP1_SYSHUB_SOC_TLB1_46; -typedef union MP1_SYSHUB_SOC_TLB1_47 regMP1_SYSHUB_SOC_TLB1_47; -typedef union MP1_SYSHUB_SOC_TLB1_48 regMP1_SYSHUB_SOC_TLB1_48; -typedef union MP1_SYSHUB_SOC_TLB1_49 regMP1_SYSHUB_SOC_TLB1_49; -typedef union MP1_SYSHUB_SOC_TLB1_50 regMP1_SYSHUB_SOC_TLB1_50; -typedef union MP1_SYSHUB_SOC_TLB1_51 regMP1_SYSHUB_SOC_TLB1_51; -typedef union MP1_SYSHUB_SOC_TLB1_52 regMP1_SYSHUB_SOC_TLB1_52; -typedef union MP1_SYSHUB_SOC_TLB1_53 regMP1_SYSHUB_SOC_TLB1_53; -typedef union MP1_SYSHUB_SOC_TLB1_54 regMP1_SYSHUB_SOC_TLB1_54; -typedef union MP1_SYSHUB_SOC_TLB1_55 regMP1_SYSHUB_SOC_TLB1_55; -typedef union MP1_SYSHUB_SOC_TLB1_56 regMP1_SYSHUB_SOC_TLB1_56; -typedef union MP1_SYSHUB_SOC_TLB1_57 regMP1_SYSHUB_SOC_TLB1_57; -typedef union MP1_SYSHUB_SOC_TLB1_58 regMP1_SYSHUB_SOC_TLB1_58; -typedef union MP1_SYSHUB_SOC_TLB1_59 regMP1_SYSHUB_SOC_TLB1_59; -typedef union MP1_SYSHUB_SOC_TLB1_60 regMP1_SYSHUB_SOC_TLB1_60; -typedef union MP1_SYSHUB_SOC_TLB1_61 regMP1_SYSHUB_SOC_TLB1_61; -typedef union MP1_SYSHUB_SOC_TLB1_62 regMP1_SYSHUB_SOC_TLB1_62; -typedef union MP1_SYSHUB_SOC_TLB2_1 regMP1_SYSHUB_SOC_TLB2_1; -typedef union MP1_SYSHUB_SOC_TLB2_2 regMP1_SYSHUB_SOC_TLB2_2; -typedef union MP1_SYSHUB_SOC_TLB2_3 regMP1_SYSHUB_SOC_TLB2_3; -typedef union MP1_SYSHUB_SOC_TLB2_4 regMP1_SYSHUB_SOC_TLB2_4; -typedef union MP1_SYSHUB_SOC_TLB2_5 regMP1_SYSHUB_SOC_TLB2_5; -typedef union MP1_SYSHUB_SOC_TLB2_6 regMP1_SYSHUB_SOC_TLB2_6; -typedef union MP1_SYSHUB_SOC_TLB2_7 regMP1_SYSHUB_SOC_TLB2_7; -typedef union MP1_SYSHUB_SOC_TLB2_8 regMP1_SYSHUB_SOC_TLB2_8; -typedef union MP1_SYSHUB_SOC_TLB2_9 regMP1_SYSHUB_SOC_TLB2_9; -typedef union MP1_SYSHUB_SOC_TLB2_10 regMP1_SYSHUB_SOC_TLB2_10; -typedef union MP1_SYSHUB_SOC_TLB2_11 regMP1_SYSHUB_SOC_TLB2_11; -typedef union MP1_SYSHUB_SOC_TLB2_12 regMP1_SYSHUB_SOC_TLB2_12; -typedef union MP1_SYSHUB_SOC_TLB2_13 regMP1_SYSHUB_SOC_TLB2_13; -typedef union MP1_SYSHUB_SOC_TLB2_14 regMP1_SYSHUB_SOC_TLB2_14; -typedef union MP1_SYSHUB_SOC_TLB2_15 regMP1_SYSHUB_SOC_TLB2_15; -typedef union MP1_SYSHUB_SOC_TLB2_16 regMP1_SYSHUB_SOC_TLB2_16; -typedef union MP1_SYSHUB_SOC_TLB2_17 regMP1_SYSHUB_SOC_TLB2_17; -typedef union MP1_SYSHUB_SOC_TLB2_18 regMP1_SYSHUB_SOC_TLB2_18; -typedef union MP1_SYSHUB_SOC_TLB2_19 regMP1_SYSHUB_SOC_TLB2_19; -typedef union MP1_SYSHUB_SOC_TLB2_20 regMP1_SYSHUB_SOC_TLB2_20; -typedef union MP1_SYSHUB_SOC_TLB2_21 regMP1_SYSHUB_SOC_TLB2_21; -typedef union MP1_SYSHUB_SOC_TLB2_22 regMP1_SYSHUB_SOC_TLB2_22; -typedef union MP1_SYSHUB_SOC_TLB2_23 regMP1_SYSHUB_SOC_TLB2_23; -typedef union MP1_SYSHUB_SOC_TLB2_24 regMP1_SYSHUB_SOC_TLB2_24; -typedef union MP1_SYSHUB_SOC_TLB2_25 regMP1_SYSHUB_SOC_TLB2_25; -typedef union MP1_SYSHUB_SOC_TLB2_26 regMP1_SYSHUB_SOC_TLB2_26; -typedef union MP1_SYSHUB_SOC_TLB2_27 regMP1_SYSHUB_SOC_TLB2_27; -typedef union MP1_SYSHUB_SOC_TLB2_28 regMP1_SYSHUB_SOC_TLB2_28; -typedef union MP1_SYSHUB_SOC_TLB2_29 regMP1_SYSHUB_SOC_TLB2_29; -typedef union MP1_SYSHUB_SOC_TLB2_30 regMP1_SYSHUB_SOC_TLB2_30; -typedef union MP1_SYSHUB_SOC_TLB2_31 regMP1_SYSHUB_SOC_TLB2_31; -typedef union MP1_SYSHUB_SOC_TLB2_32 regMP1_SYSHUB_SOC_TLB2_32; -typedef union MP1_SYSHUB_SOC_TLB2_33 regMP1_SYSHUB_SOC_TLB2_33; -typedef union MP1_SYSHUB_SOC_TLB2_34 regMP1_SYSHUB_SOC_TLB2_34; -typedef union MP1_SYSHUB_SOC_TLB2_35 regMP1_SYSHUB_SOC_TLB2_35; -typedef union MP1_SYSHUB_SOC_TLB2_36 regMP1_SYSHUB_SOC_TLB2_36; -typedef union MP1_SYSHUB_SOC_TLB2_37 regMP1_SYSHUB_SOC_TLB2_37; -typedef union MP1_SYSHUB_SOC_TLB2_38 regMP1_SYSHUB_SOC_TLB2_38; -typedef union MP1_SYSHUB_SOC_TLB2_39 regMP1_SYSHUB_SOC_TLB2_39; -typedef union MP1_SYSHUB_SOC_TLB2_40 regMP1_SYSHUB_SOC_TLB2_40; -typedef union MP1_SYSHUB_SOC_TLB2_41 regMP1_SYSHUB_SOC_TLB2_41; -typedef union MP1_SYSHUB_SOC_TLB2_42 regMP1_SYSHUB_SOC_TLB2_42; -typedef union MP1_SYSHUB_SOC_TLB2_43 regMP1_SYSHUB_SOC_TLB2_43; -typedef union MP1_SYSHUB_SOC_TLB2_44 regMP1_SYSHUB_SOC_TLB2_44; -typedef union MP1_SYSHUB_SOC_TLB2_45 regMP1_SYSHUB_SOC_TLB2_45; -typedef union MP1_SYSHUB_SOC_TLB2_46 regMP1_SYSHUB_SOC_TLB2_46; -typedef union MP1_SYSHUB_SOC_TLB2_47 regMP1_SYSHUB_SOC_TLB2_47; -typedef union MP1_SYSHUB_SOC_TLB2_48 regMP1_SYSHUB_SOC_TLB2_48; -typedef union MP1_SYSHUB_SOC_TLB2_49 regMP1_SYSHUB_SOC_TLB2_49; -typedef union MP1_SYSHUB_SOC_TLB2_50 regMP1_SYSHUB_SOC_TLB2_50; -typedef union MP1_SYSHUB_SOC_TLB2_51 regMP1_SYSHUB_SOC_TLB2_51; -typedef union MP1_SYSHUB_SOC_TLB2_52 regMP1_SYSHUB_SOC_TLB2_52; -typedef union MP1_SYSHUB_SOC_TLB2_53 regMP1_SYSHUB_SOC_TLB2_53; -typedef union MP1_SYSHUB_SOC_TLB2_54 regMP1_SYSHUB_SOC_TLB2_54; -typedef union MP1_SYSHUB_SOC_TLB2_55 regMP1_SYSHUB_SOC_TLB2_55; -typedef union MP1_SYSHUB_SOC_TLB2_56 regMP1_SYSHUB_SOC_TLB2_56; -typedef union MP1_SYSHUB_SOC_TLB2_57 regMP1_SYSHUB_SOC_TLB2_57; -typedef union MP1_SYSHUB_SOC_TLB2_58 regMP1_SYSHUB_SOC_TLB2_58; -typedef union MP1_SYSHUB_SOC_TLB2_59 regMP1_SYSHUB_SOC_TLB2_59; -typedef union MP1_SYSHUB_SOC_TLB2_60 regMP1_SYSHUB_SOC_TLB2_60; -typedef union MP1_SYSHUB_SOC_TLB2_61 regMP1_SYSHUB_SOC_TLB2_61; -typedef union MP1_SYSHUB_SOC_TLB2_62 regMP1_SYSHUB_SOC_TLB2_62; -typedef union MP1_SYSHUB_SOC_TLB3_1 regMP1_SYSHUB_SOC_TLB3_1; -typedef union MP1_SYSHUB_SOC_TLB3_2 regMP1_SYSHUB_SOC_TLB3_2; -typedef union MP1_SYSHUB_SOC_TLB3_3 regMP1_SYSHUB_SOC_TLB3_3; -typedef union MP1_SYSHUB_SOC_TLB3_4 regMP1_SYSHUB_SOC_TLB3_4; -typedef union MP1_SYSHUB_SOC_TLB3_5 regMP1_SYSHUB_SOC_TLB3_5; -typedef union MP1_SYSHUB_SOC_TLB3_6 regMP1_SYSHUB_SOC_TLB3_6; -typedef union MP1_SYSHUB_SOC_TLB3_7 regMP1_SYSHUB_SOC_TLB3_7; -typedef union MP1_SYSHUB_SOC_TLB3_8 regMP1_SYSHUB_SOC_TLB3_8; -typedef union MP1_SYSHUB_SOC_TLB3_9 regMP1_SYSHUB_SOC_TLB3_9; -typedef union MP1_SYSHUB_SOC_TLB3_10 regMP1_SYSHUB_SOC_TLB3_10; -typedef union MP1_SYSHUB_SOC_TLB3_11 regMP1_SYSHUB_SOC_TLB3_11; -typedef union MP1_SYSHUB_SOC_TLB3_12 regMP1_SYSHUB_SOC_TLB3_12; -typedef union MP1_SYSHUB_SOC_TLB3_13 regMP1_SYSHUB_SOC_TLB3_13; -typedef union MP1_SYSHUB_SOC_TLB3_14 regMP1_SYSHUB_SOC_TLB3_14; -typedef union MP1_SYSHUB_SOC_TLB3_15 regMP1_SYSHUB_SOC_TLB3_15; -typedef union MP1_SYSHUB_SOC_TLB3_16 regMP1_SYSHUB_SOC_TLB3_16; -typedef union MP1_SYSHUB_SOC_TLB3_17 regMP1_SYSHUB_SOC_TLB3_17; -typedef union MP1_SYSHUB_SOC_TLB3_18 regMP1_SYSHUB_SOC_TLB3_18; -typedef union MP1_SYSHUB_SOC_TLB3_19 regMP1_SYSHUB_SOC_TLB3_19; -typedef union MP1_SYSHUB_SOC_TLB3_20 regMP1_SYSHUB_SOC_TLB3_20; -typedef union MP1_SYSHUB_SOC_TLB3_21 regMP1_SYSHUB_SOC_TLB3_21; -typedef union MP1_SYSHUB_SOC_TLB3_22 regMP1_SYSHUB_SOC_TLB3_22; -typedef union MP1_SYSHUB_SOC_TLB3_23 regMP1_SYSHUB_SOC_TLB3_23; -typedef union MP1_SYSHUB_SOC_TLB3_24 regMP1_SYSHUB_SOC_TLB3_24; -typedef union MP1_SYSHUB_SOC_TLB3_25 regMP1_SYSHUB_SOC_TLB3_25; -typedef union MP1_SYSHUB_SOC_TLB3_26 regMP1_SYSHUB_SOC_TLB3_26; -typedef union MP1_SYSHUB_SOC_TLB3_27 regMP1_SYSHUB_SOC_TLB3_27; -typedef union MP1_SYSHUB_SOC_TLB3_28 regMP1_SYSHUB_SOC_TLB3_28; -typedef union MP1_SYSHUB_SOC_TLB3_29 regMP1_SYSHUB_SOC_TLB3_29; -typedef union MP1_SYSHUB_SOC_TLB3_30 regMP1_SYSHUB_SOC_TLB3_30; -typedef union MP1_SYSHUB_SOC_TLB3_31 regMP1_SYSHUB_SOC_TLB3_31; -typedef union MP1_SYSHUB_SOC_TLB3_32 regMP1_SYSHUB_SOC_TLB3_32; -typedef union MP1_SYSHUB_SOC_TLB3_33 regMP1_SYSHUB_SOC_TLB3_33; -typedef union MP1_SYSHUB_SOC_TLB3_34 regMP1_SYSHUB_SOC_TLB3_34; -typedef union MP1_SYSHUB_SOC_TLB3_35 regMP1_SYSHUB_SOC_TLB3_35; -typedef union MP1_SYSHUB_SOC_TLB3_36 regMP1_SYSHUB_SOC_TLB3_36; -typedef union MP1_SYSHUB_SOC_TLB3_37 regMP1_SYSHUB_SOC_TLB3_37; -typedef union MP1_SYSHUB_SOC_TLB3_38 regMP1_SYSHUB_SOC_TLB3_38; -typedef union MP1_SYSHUB_SOC_TLB3_39 regMP1_SYSHUB_SOC_TLB3_39; -typedef union MP1_SYSHUB_SOC_TLB3_40 regMP1_SYSHUB_SOC_TLB3_40; -typedef union MP1_SYSHUB_SOC_TLB3_41 regMP1_SYSHUB_SOC_TLB3_41; -typedef union MP1_SYSHUB_SOC_TLB3_42 regMP1_SYSHUB_SOC_TLB3_42; -typedef union MP1_SYSHUB_SOC_TLB3_43 regMP1_SYSHUB_SOC_TLB3_43; -typedef union MP1_SYSHUB_SOC_TLB3_44 regMP1_SYSHUB_SOC_TLB3_44; -typedef union MP1_SYSHUB_SOC_TLB3_45 regMP1_SYSHUB_SOC_TLB3_45; -typedef union MP1_SYSHUB_SOC_TLB3_46 regMP1_SYSHUB_SOC_TLB3_46; -typedef union MP1_SYSHUB_SOC_TLB3_47 regMP1_SYSHUB_SOC_TLB3_47; -typedef union MP1_SYSHUB_SOC_TLB3_48 regMP1_SYSHUB_SOC_TLB3_48; -typedef union MP1_SYSHUB_SOC_TLB3_49 regMP1_SYSHUB_SOC_TLB3_49; -typedef union MP1_SYSHUB_SOC_TLB3_50 regMP1_SYSHUB_SOC_TLB3_50; -typedef union MP1_SYSHUB_SOC_TLB3_51 regMP1_SYSHUB_SOC_TLB3_51; -typedef union MP1_SYSHUB_SOC_TLB3_52 regMP1_SYSHUB_SOC_TLB3_52; -typedef union MP1_SYSHUB_SOC_TLB3_53 regMP1_SYSHUB_SOC_TLB3_53; -typedef union MP1_SYSHUB_SOC_TLB3_54 regMP1_SYSHUB_SOC_TLB3_54; -typedef union MP1_SYSHUB_SOC_TLB3_55 regMP1_SYSHUB_SOC_TLB3_55; -typedef union MP1_SYSHUB_SOC_TLB3_56 regMP1_SYSHUB_SOC_TLB3_56; -typedef union MP1_SYSHUB_SOC_TLB3_57 regMP1_SYSHUB_SOC_TLB3_57; -typedef union MP1_SYSHUB_SOC_TLB3_58 regMP1_SYSHUB_SOC_TLB3_58; -typedef union MP1_SYSHUB_SOC_TLB3_59 regMP1_SYSHUB_SOC_TLB3_59; -typedef union MP1_SYSHUB_SOC_TLB3_60 regMP1_SYSHUB_SOC_TLB3_60; -typedef union MP1_SYSHUB_SOC_TLB3_61 regMP1_SYSHUB_SOC_TLB3_61; -typedef union MP1_SYSHUB_SOC_TLB3_62 regMP1_SYSHUB_SOC_TLB3_62; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_1; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_2; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_3; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_4; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_5; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_6; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_7; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_8; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_9; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_10; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_11; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_12; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_13; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_14; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_15; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_16; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_17; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_18; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_19; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_20; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_21; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_22; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_23; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_24; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_25; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_26; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_27; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_28; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_29; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_30; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_31; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_32; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_33; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_34; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_35; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_36; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_37; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_38; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_39; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_40; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_41; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_42; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_43; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_44; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_45; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_46; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_47; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_48; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_49; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_50; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_51; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_52; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_53; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_54; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_55; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_56; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_57; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_58; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_59; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_60; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_61; -typedef union MP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62 regMP1_SYSHUB_TLB_SUB_PAGE_ATTRIBUTE_RW_62; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_1 regMP1_SYSHUB_TLB_ATTRIBUTE_1; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_2 regMP1_SYSHUB_TLB_ATTRIBUTE_2; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_3 regMP1_SYSHUB_TLB_ATTRIBUTE_3; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_4 regMP1_SYSHUB_TLB_ATTRIBUTE_4; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_5 regMP1_SYSHUB_TLB_ATTRIBUTE_5; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_6 regMP1_SYSHUB_TLB_ATTRIBUTE_6; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_7 regMP1_SYSHUB_TLB_ATTRIBUTE_7; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_8 regMP1_SYSHUB_TLB_ATTRIBUTE_8; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_9 regMP1_SYSHUB_TLB_ATTRIBUTE_9; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_10 regMP1_SYSHUB_TLB_ATTRIBUTE_10; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_11 regMP1_SYSHUB_TLB_ATTRIBUTE_11; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_12 regMP1_SYSHUB_TLB_ATTRIBUTE_12; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_13 regMP1_SYSHUB_TLB_ATTRIBUTE_13; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_14 regMP1_SYSHUB_TLB_ATTRIBUTE_14; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_15 regMP1_SYSHUB_TLB_ATTRIBUTE_15; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_16 regMP1_SYSHUB_TLB_ATTRIBUTE_16; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_17 regMP1_SYSHUB_TLB_ATTRIBUTE_17; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_18 regMP1_SYSHUB_TLB_ATTRIBUTE_18; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_19 regMP1_SYSHUB_TLB_ATTRIBUTE_19; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_20 regMP1_SYSHUB_TLB_ATTRIBUTE_20; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_21 regMP1_SYSHUB_TLB_ATTRIBUTE_21; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_22 regMP1_SYSHUB_TLB_ATTRIBUTE_22; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_23 regMP1_SYSHUB_TLB_ATTRIBUTE_23; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_24 regMP1_SYSHUB_TLB_ATTRIBUTE_24; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_25 regMP1_SYSHUB_TLB_ATTRIBUTE_25; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_26 regMP1_SYSHUB_TLB_ATTRIBUTE_26; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_27 regMP1_SYSHUB_TLB_ATTRIBUTE_27; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_28 regMP1_SYSHUB_TLB_ATTRIBUTE_28; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_29 regMP1_SYSHUB_TLB_ATTRIBUTE_29; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_30 regMP1_SYSHUB_TLB_ATTRIBUTE_30; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_31 regMP1_SYSHUB_TLB_ATTRIBUTE_31; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_32 regMP1_SYSHUB_TLB_ATTRIBUTE_32; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_33 regMP1_SYSHUB_TLB_ATTRIBUTE_33; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_34 regMP1_SYSHUB_TLB_ATTRIBUTE_34; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_35 regMP1_SYSHUB_TLB_ATTRIBUTE_35; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_36 regMP1_SYSHUB_TLB_ATTRIBUTE_36; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_37 regMP1_SYSHUB_TLB_ATTRIBUTE_37; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_38 regMP1_SYSHUB_TLB_ATTRIBUTE_38; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_39 regMP1_SYSHUB_TLB_ATTRIBUTE_39; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_40 regMP1_SYSHUB_TLB_ATTRIBUTE_40; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_41 regMP1_SYSHUB_TLB_ATTRIBUTE_41; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_42 regMP1_SYSHUB_TLB_ATTRIBUTE_42; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_43 regMP1_SYSHUB_TLB_ATTRIBUTE_43; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_44 regMP1_SYSHUB_TLB_ATTRIBUTE_44; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_45 regMP1_SYSHUB_TLB_ATTRIBUTE_45; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_46 regMP1_SYSHUB_TLB_ATTRIBUTE_46; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_47 regMP1_SYSHUB_TLB_ATTRIBUTE_47; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_48 regMP1_SYSHUB_TLB_ATTRIBUTE_48; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_49 regMP1_SYSHUB_TLB_ATTRIBUTE_49; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_50 regMP1_SYSHUB_TLB_ATTRIBUTE_50; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_51 regMP1_SYSHUB_TLB_ATTRIBUTE_51; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_52 regMP1_SYSHUB_TLB_ATTRIBUTE_52; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_53 regMP1_SYSHUB_TLB_ATTRIBUTE_53; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_54 regMP1_SYSHUB_TLB_ATTRIBUTE_54; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_55 regMP1_SYSHUB_TLB_ATTRIBUTE_55; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_56 regMP1_SYSHUB_TLB_ATTRIBUTE_56; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_57 regMP1_SYSHUB_TLB_ATTRIBUTE_57; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_58 regMP1_SYSHUB_TLB_ATTRIBUTE_58; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_59 regMP1_SYSHUB_TLB_ATTRIBUTE_59; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_60 regMP1_SYSHUB_TLB_ATTRIBUTE_60; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_61 regMP1_SYSHUB_TLB_ATTRIBUTE_61; -typedef union MP1_SYSHUB_TLB_ATTRIBUTE_62 regMP1_SYSHUB_TLB_ATTRIBUTE_62; -typedef union MP1_SYSHUB_INT_STATUS regMP1_SYSHUB_INT_STATUS; -typedef union MP1_SYSHUB_WR_INT_ADDR regMP1_SYSHUB_WR_INT_ADDR; -typedef union MP1_SYSHUB_WR_INT_OTHER regMP1_SYSHUB_WR_INT_OTHER; -typedef union MP1_SYSHUB_RD_INT_ADDR regMP1_SYSHUB_RD_INT_ADDR; -typedef union MP1_SYSHUB_RD_INT_OTHER regMP1_SYSHUB_RD_INT_OTHER; -typedef union MP1_SYSHUB_REG_INT_ADDR regMP1_SYSHUB_REG_INT_ADDR; -typedef union MP1_SYSHUB_REG_INT_OTHER regMP1_SYSHUB_REG_INT_OTHER; -typedef union MP1_SYSHUB_AXCACHE_CFG regMP1_SYSHUB_AXCACHE_CFG; -typedef union MP1_SYSHUB_DS_OVERRIDE regMP1_SYSHUB_DS_OVERRIDE; -typedef union MP1_SYSHUB_OUTSTANDING regMP1_SYSHUB_OUTSTANDING; -typedef union MP_HUBIF_SOC_TLB0_1 regMP_HUBIF_SOC_TLB0_1; -typedef union MP_HUBIF_SOC_TLB0_2 regMP_HUBIF_SOC_TLB0_2; -typedef union MP_HUBIF_SOC_TLB0_3 regMP_HUBIF_SOC_TLB0_3; -typedef union MP_HUBIF_SOC_TLB0_4 regMP_HUBIF_SOC_TLB0_4; -typedef union MP_HUBIF_SOC_TLB0_5 regMP_HUBIF_SOC_TLB0_5; -typedef union MP_HUBIF_SOC_TLB0_6 regMP_HUBIF_SOC_TLB0_6; -typedef union MP_HUBIF_SOC_TLB0_7 regMP_HUBIF_SOC_TLB0_7; -typedef union MP_HUBIF_SOC_TLB0_8 regMP_HUBIF_SOC_TLB0_8; -typedef union MP_HUBIF_SOC_TLB0_9 regMP_HUBIF_SOC_TLB0_9; -typedef union MP_HUBIF_SOC_TLB0_10 regMP_HUBIF_SOC_TLB0_10; -typedef union MP_HUBIF_SOC_TLB0_11 regMP_HUBIF_SOC_TLB0_11; -typedef union MP_HUBIF_SOC_TLB0_12 regMP_HUBIF_SOC_TLB0_12; -typedef union MP_HUBIF_SOC_TLB0_13 regMP_HUBIF_SOC_TLB0_13; -typedef union MP_HUBIF_SOC_TLB0_14 regMP_HUBIF_SOC_TLB0_14; -typedef union MP_HUBIF_SOC_TLB0_15 regMP_HUBIF_SOC_TLB0_15; -typedef union MP_HUBIF_SOC_TLB0_16 regMP_HUBIF_SOC_TLB0_16; -typedef union MP_HUBIF_SOC_TLB0_17 regMP_HUBIF_SOC_TLB0_17; -typedef union MP_HUBIF_SOC_TLB0_18 regMP_HUBIF_SOC_TLB0_18; -typedef union MP_HUBIF_SOC_TLB0_19 regMP_HUBIF_SOC_TLB0_19; -typedef union MP_HUBIF_SOC_TLB0_20 regMP_HUBIF_SOC_TLB0_20; -typedef union MP_HUBIF_SOC_TLB0_21 regMP_HUBIF_SOC_TLB0_21; -typedef union MP_HUBIF_SOC_TLB0_22 regMP_HUBIF_SOC_TLB0_22; -typedef union MP_HUBIF_SOC_TLB0_23 regMP_HUBIF_SOC_TLB0_23; -typedef union MP_HUBIF_SOC_TLB0_24 regMP_HUBIF_SOC_TLB0_24; -typedef union MP_HUBIF_SOC_TLB0_25 regMP_HUBIF_SOC_TLB0_25; -typedef union MP_HUBIF_SOC_TLB0_26 regMP_HUBIF_SOC_TLB0_26; -typedef union MP_HUBIF_SOC_TLB0_27 regMP_HUBIF_SOC_TLB0_27; -typedef union MP_HUBIF_SOC_TLB0_28 regMP_HUBIF_SOC_TLB0_28; -typedef union MP_HUBIF_SOC_TLB0_29 regMP_HUBIF_SOC_TLB0_29; -typedef union MP_HUBIF_SOC_TLB0_30 regMP_HUBIF_SOC_TLB0_30; -typedef union MP_HUBIF_SOC_TLB0_31 regMP_HUBIF_SOC_TLB0_31; -typedef union MP_HUBIF_SOC_TLB0_32 regMP_HUBIF_SOC_TLB0_32; -typedef union MP_HUBIF_SOC_TLB0_33 regMP_HUBIF_SOC_TLB0_33; -typedef union MP_HUBIF_SOC_TLB0_34 regMP_HUBIF_SOC_TLB0_34; -typedef union MP_HUBIF_SOC_TLB0_35 regMP_HUBIF_SOC_TLB0_35; -typedef union MP_HUBIF_SOC_TLB0_36 regMP_HUBIF_SOC_TLB0_36; -typedef union MP_HUBIF_SOC_TLB0_37 regMP_HUBIF_SOC_TLB0_37; -typedef union MP_HUBIF_SOC_TLB0_38 regMP_HUBIF_SOC_TLB0_38; -typedef union MP_HUBIF_SOC_TLB0_39 regMP_HUBIF_SOC_TLB0_39; -typedef union MP_HUBIF_SOC_TLB0_40 regMP_HUBIF_SOC_TLB0_40; -typedef union MP_HUBIF_SOC_TLB0_41 regMP_HUBIF_SOC_TLB0_41; -typedef union MP_HUBIF_SOC_TLB0_42 regMP_HUBIF_SOC_TLB0_42; -typedef union MP_HUBIF_SOC_TLB0_43 regMP_HUBIF_SOC_TLB0_43; -typedef union MP_HUBIF_SOC_TLB0_44 regMP_HUBIF_SOC_TLB0_44; -typedef union MP_HUBIF_SOC_TLB0_45 regMP_HUBIF_SOC_TLB0_45; -typedef union MP_HUBIF_SOC_TLB0_46 regMP_HUBIF_SOC_TLB0_46; -typedef union MP_HUBIF_SOC_TLB0_47 regMP_HUBIF_SOC_TLB0_47; -typedef union MP_HUBIF_SOC_TLB0_48 regMP_HUBIF_SOC_TLB0_48; -typedef union MP_HUBIF_SOC_TLB0_49 regMP_HUBIF_SOC_TLB0_49; -typedef union MP_HUBIF_SOC_TLB0_50 regMP_HUBIF_SOC_TLB0_50; -typedef union MP_HUBIF_SOC_TLB0_51 regMP_HUBIF_SOC_TLB0_51; -typedef union MP_HUBIF_SOC_TLB0_52 regMP_HUBIF_SOC_TLB0_52; -typedef union MP_HUBIF_SOC_TLB0_53 regMP_HUBIF_SOC_TLB0_53; -typedef union MP_HUBIF_SOC_TLB0_54 regMP_HUBIF_SOC_TLB0_54; -typedef union MP_HUBIF_SOC_TLB0_55 regMP_HUBIF_SOC_TLB0_55; -typedef union MP_HUBIF_SOC_TLB0_56 regMP_HUBIF_SOC_TLB0_56; -typedef union MP_HUBIF_SOC_TLB0_57 regMP_HUBIF_SOC_TLB0_57; -typedef union MP_HUBIF_SOC_TLB0_58 regMP_HUBIF_SOC_TLB0_58; -typedef union MP_HUBIF_SOC_TLB0_59 regMP_HUBIF_SOC_TLB0_59; -typedef union MP_HUBIF_SOC_TLB0_60 regMP_HUBIF_SOC_TLB0_60; -typedef union MP_HUBIF_SOC_TLB0_61 regMP_HUBIF_SOC_TLB0_61; -typedef union MP_HUBIF_SOC_TLB0_62 regMP_HUBIF_SOC_TLB0_62; -typedef union MP_HUBIF_SOC_TLB1_1 regMP_HUBIF_SOC_TLB1_1; -typedef union MP_HUBIF_SOC_TLB1_2 regMP_HUBIF_SOC_TLB1_2; -typedef union MP_HUBIF_SOC_TLB1_3 regMP_HUBIF_SOC_TLB1_3; -typedef union MP_HUBIF_SOC_TLB1_4 regMP_HUBIF_SOC_TLB1_4; -typedef union MP_HUBIF_SOC_TLB1_5 regMP_HUBIF_SOC_TLB1_5; -typedef union MP_HUBIF_SOC_TLB1_6 regMP_HUBIF_SOC_TLB1_6; -typedef union MP_HUBIF_SOC_TLB1_7 regMP_HUBIF_SOC_TLB1_7; -typedef union MP_HUBIF_SOC_TLB1_8 regMP_HUBIF_SOC_TLB1_8; -typedef union MP_HUBIF_SOC_TLB1_9 regMP_HUBIF_SOC_TLB1_9; -typedef union MP_HUBIF_SOC_TLB1_10 regMP_HUBIF_SOC_TLB1_10; -typedef union MP_HUBIF_SOC_TLB1_11 regMP_HUBIF_SOC_TLB1_11; -typedef union MP_HUBIF_SOC_TLB1_12 regMP_HUBIF_SOC_TLB1_12; -typedef union MP_HUBIF_SOC_TLB1_13 regMP_HUBIF_SOC_TLB1_13; -typedef union MP_HUBIF_SOC_TLB1_14 regMP_HUBIF_SOC_TLB1_14; -typedef union MP_HUBIF_SOC_TLB1_15 regMP_HUBIF_SOC_TLB1_15; -typedef union MP_HUBIF_SOC_TLB1_16 regMP_HUBIF_SOC_TLB1_16; -typedef union MP_HUBIF_SOC_TLB1_17 regMP_HUBIF_SOC_TLB1_17; -typedef union MP_HUBIF_SOC_TLB1_18 regMP_HUBIF_SOC_TLB1_18; -typedef union MP_HUBIF_SOC_TLB1_19 regMP_HUBIF_SOC_TLB1_19; -typedef union MP_HUBIF_SOC_TLB1_20 regMP_HUBIF_SOC_TLB1_20; -typedef union MP_HUBIF_SOC_TLB1_21 regMP_HUBIF_SOC_TLB1_21; -typedef union MP_HUBIF_SOC_TLB1_22 regMP_HUBIF_SOC_TLB1_22; -typedef union MP_HUBIF_SOC_TLB1_23 regMP_HUBIF_SOC_TLB1_23; -typedef union MP_HUBIF_SOC_TLB1_24 regMP_HUBIF_SOC_TLB1_24; -typedef union MP_HUBIF_SOC_TLB1_25 regMP_HUBIF_SOC_TLB1_25; -typedef union MP_HUBIF_SOC_TLB1_26 regMP_HUBIF_SOC_TLB1_26; -typedef union MP_HUBIF_SOC_TLB1_27 regMP_HUBIF_SOC_TLB1_27; -typedef union MP_HUBIF_SOC_TLB1_28 regMP_HUBIF_SOC_TLB1_28; -typedef union MP_HUBIF_SOC_TLB1_29 regMP_HUBIF_SOC_TLB1_29; -typedef union MP_HUBIF_SOC_TLB1_30 regMP_HUBIF_SOC_TLB1_30; -typedef union MP_HUBIF_SOC_TLB1_31 regMP_HUBIF_SOC_TLB1_31; -typedef union MP_HUBIF_SOC_TLB1_32 regMP_HUBIF_SOC_TLB1_32; -typedef union MP_HUBIF_SOC_TLB1_33 regMP_HUBIF_SOC_TLB1_33; -typedef union MP_HUBIF_SOC_TLB1_34 regMP_HUBIF_SOC_TLB1_34; -typedef union MP_HUBIF_SOC_TLB1_35 regMP_HUBIF_SOC_TLB1_35; -typedef union MP_HUBIF_SOC_TLB1_36 regMP_HUBIF_SOC_TLB1_36; -typedef union MP_HUBIF_SOC_TLB1_37 regMP_HUBIF_SOC_TLB1_37; -typedef union MP_HUBIF_SOC_TLB1_38 regMP_HUBIF_SOC_TLB1_38; -typedef union MP_HUBIF_SOC_TLB1_39 regMP_HUBIF_SOC_TLB1_39; -typedef union MP_HUBIF_SOC_TLB1_40 regMP_HUBIF_SOC_TLB1_40; -typedef union MP_HUBIF_SOC_TLB1_41 regMP_HUBIF_SOC_TLB1_41; -typedef union MP_HUBIF_SOC_TLB1_42 regMP_HUBIF_SOC_TLB1_42; -typedef union MP_HUBIF_SOC_TLB1_43 regMP_HUBIF_SOC_TLB1_43; -typedef union MP_HUBIF_SOC_TLB1_44 regMP_HUBIF_SOC_TLB1_44; -typedef union MP_HUBIF_SOC_TLB1_45 regMP_HUBIF_SOC_TLB1_45; -typedef union MP_HUBIF_SOC_TLB1_46 regMP_HUBIF_SOC_TLB1_46; -typedef union MP_HUBIF_SOC_TLB1_47 regMP_HUBIF_SOC_TLB1_47; -typedef union MP_HUBIF_SOC_TLB1_48 regMP_HUBIF_SOC_TLB1_48; -typedef union MP_HUBIF_SOC_TLB1_49 regMP_HUBIF_SOC_TLB1_49; -typedef union MP_HUBIF_SOC_TLB1_50 regMP_HUBIF_SOC_TLB1_50; -typedef union MP_HUBIF_SOC_TLB1_51 regMP_HUBIF_SOC_TLB1_51; -typedef union MP_HUBIF_SOC_TLB1_52 regMP_HUBIF_SOC_TLB1_52; -typedef union MP_HUBIF_SOC_TLB1_53 regMP_HUBIF_SOC_TLB1_53; -typedef union MP_HUBIF_SOC_TLB1_54 regMP_HUBIF_SOC_TLB1_54; -typedef union MP_HUBIF_SOC_TLB1_55 regMP_HUBIF_SOC_TLB1_55; -typedef union MP_HUBIF_SOC_TLB1_56 regMP_HUBIF_SOC_TLB1_56; -typedef union MP_HUBIF_SOC_TLB1_57 regMP_HUBIF_SOC_TLB1_57; -typedef union MP_HUBIF_SOC_TLB1_58 regMP_HUBIF_SOC_TLB1_58; -typedef union MP_HUBIF_SOC_TLB1_59 regMP_HUBIF_SOC_TLB1_59; -typedef union MP_HUBIF_SOC_TLB1_60 regMP_HUBIF_SOC_TLB1_60; -typedef union MP_HUBIF_SOC_TLB1_61 regMP_HUBIF_SOC_TLB1_61; -typedef union MP_HUBIF_SOC_TLB1_62 regMP_HUBIF_SOC_TLB1_62; -typedef union MP_HUBIF_SOC_TLB2_1 regMP_HUBIF_SOC_TLB2_1; -typedef union MP_HUBIF_SOC_TLB2_2 regMP_HUBIF_SOC_TLB2_2; -typedef union MP_HUBIF_SOC_TLB2_3 regMP_HUBIF_SOC_TLB2_3; -typedef union MP_HUBIF_SOC_TLB2_4 regMP_HUBIF_SOC_TLB2_4; -typedef union MP_HUBIF_SOC_TLB2_5 regMP_HUBIF_SOC_TLB2_5; -typedef union MP_HUBIF_SOC_TLB2_6 regMP_HUBIF_SOC_TLB2_6; -typedef union MP_HUBIF_SOC_TLB2_7 regMP_HUBIF_SOC_TLB2_7; -typedef union MP_HUBIF_SOC_TLB2_8 regMP_HUBIF_SOC_TLB2_8; -typedef union MP_HUBIF_SOC_TLB2_9 regMP_HUBIF_SOC_TLB2_9; -typedef union MP_HUBIF_SOC_TLB2_10 regMP_HUBIF_SOC_TLB2_10; -typedef union MP_HUBIF_SOC_TLB2_11 regMP_HUBIF_SOC_TLB2_11; -typedef union MP_HUBIF_SOC_TLB2_12 regMP_HUBIF_SOC_TLB2_12; -typedef union MP_HUBIF_SOC_TLB2_13 regMP_HUBIF_SOC_TLB2_13; -typedef union MP_HUBIF_SOC_TLB2_14 regMP_HUBIF_SOC_TLB2_14; -typedef union MP_HUBIF_SOC_TLB2_15 regMP_HUBIF_SOC_TLB2_15; -typedef union MP_HUBIF_SOC_TLB2_16 regMP_HUBIF_SOC_TLB2_16; -typedef union MP_HUBIF_SOC_TLB2_17 regMP_HUBIF_SOC_TLB2_17; -typedef union MP_HUBIF_SOC_TLB2_18 regMP_HUBIF_SOC_TLB2_18; -typedef union MP_HUBIF_SOC_TLB2_19 regMP_HUBIF_SOC_TLB2_19; -typedef union MP_HUBIF_SOC_TLB2_20 regMP_HUBIF_SOC_TLB2_20; -typedef union MP_HUBIF_SOC_TLB2_21 regMP_HUBIF_SOC_TLB2_21; -typedef union MP_HUBIF_SOC_TLB2_22 regMP_HUBIF_SOC_TLB2_22; -typedef union MP_HUBIF_SOC_TLB2_23 regMP_HUBIF_SOC_TLB2_23; -typedef union MP_HUBIF_SOC_TLB2_24 regMP_HUBIF_SOC_TLB2_24; -typedef union MP_HUBIF_SOC_TLB2_25 regMP_HUBIF_SOC_TLB2_25; -typedef union MP_HUBIF_SOC_TLB2_26 regMP_HUBIF_SOC_TLB2_26; -typedef union MP_HUBIF_SOC_TLB2_27 regMP_HUBIF_SOC_TLB2_27; -typedef union MP_HUBIF_SOC_TLB2_28 regMP_HUBIF_SOC_TLB2_28; -typedef union MP_HUBIF_SOC_TLB2_29 regMP_HUBIF_SOC_TLB2_29; -typedef union MP_HUBIF_SOC_TLB2_30 regMP_HUBIF_SOC_TLB2_30; -typedef union MP_HUBIF_SOC_TLB2_31 regMP_HUBIF_SOC_TLB2_31; -typedef union MP_HUBIF_SOC_TLB2_32 regMP_HUBIF_SOC_TLB2_32; -typedef union MP_HUBIF_SOC_TLB2_33 regMP_HUBIF_SOC_TLB2_33; -typedef union MP_HUBIF_SOC_TLB2_34 regMP_HUBIF_SOC_TLB2_34; -typedef union MP_HUBIF_SOC_TLB2_35 regMP_HUBIF_SOC_TLB2_35; -typedef union MP_HUBIF_SOC_TLB2_36 regMP_HUBIF_SOC_TLB2_36; -typedef union MP_HUBIF_SOC_TLB2_37 regMP_HUBIF_SOC_TLB2_37; -typedef union MP_HUBIF_SOC_TLB2_38 regMP_HUBIF_SOC_TLB2_38; -typedef union MP_HUBIF_SOC_TLB2_39 regMP_HUBIF_SOC_TLB2_39; -typedef union MP_HUBIF_SOC_TLB2_40 regMP_HUBIF_SOC_TLB2_40; -typedef union MP_HUBIF_SOC_TLB2_41 regMP_HUBIF_SOC_TLB2_41; -typedef union MP_HUBIF_SOC_TLB2_42 regMP_HUBIF_SOC_TLB2_42; -typedef union MP_HUBIF_SOC_TLB2_43 regMP_HUBIF_SOC_TLB2_43; -typedef union MP_HUBIF_SOC_TLB2_44 regMP_HUBIF_SOC_TLB2_44; -typedef union MP_HUBIF_SOC_TLB2_45 regMP_HUBIF_SOC_TLB2_45; -typedef union MP_HUBIF_SOC_TLB2_46 regMP_HUBIF_SOC_TLB2_46; -typedef union MP_HUBIF_SOC_TLB2_47 regMP_HUBIF_SOC_TLB2_47; -typedef union MP_HUBIF_SOC_TLB2_48 regMP_HUBIF_SOC_TLB2_48; -typedef union MP_HUBIF_SOC_TLB2_49 regMP_HUBIF_SOC_TLB2_49; -typedef union MP_HUBIF_SOC_TLB2_50 regMP_HUBIF_SOC_TLB2_50; -typedef union MP_HUBIF_SOC_TLB2_51 regMP_HUBIF_SOC_TLB2_51; -typedef union MP_HUBIF_SOC_TLB2_52 regMP_HUBIF_SOC_TLB2_52; -typedef union MP_HUBIF_SOC_TLB2_53 regMP_HUBIF_SOC_TLB2_53; -typedef union MP_HUBIF_SOC_TLB2_54 regMP_HUBIF_SOC_TLB2_54; -typedef union MP_HUBIF_SOC_TLB2_55 regMP_HUBIF_SOC_TLB2_55; -typedef union MP_HUBIF_SOC_TLB2_56 regMP_HUBIF_SOC_TLB2_56; -typedef union MP_HUBIF_SOC_TLB2_57 regMP_HUBIF_SOC_TLB2_57; -typedef union MP_HUBIF_SOC_TLB2_58 regMP_HUBIF_SOC_TLB2_58; -typedef union MP_HUBIF_SOC_TLB2_59 regMP_HUBIF_SOC_TLB2_59; -typedef union MP_HUBIF_SOC_TLB2_60 regMP_HUBIF_SOC_TLB2_60; -typedef union MP_HUBIF_SOC_TLB2_61 regMP_HUBIF_SOC_TLB2_61; -typedef union MP_HUBIF_SOC_TLB2_62 regMP_HUBIF_SOC_TLB2_62; -typedef union MP_HUBIF_SOC_TLB3_1 regMP_HUBIF_SOC_TLB3_1; -typedef union MP_HUBIF_SOC_TLB3_2 regMP_HUBIF_SOC_TLB3_2; -typedef union MP_HUBIF_SOC_TLB3_3 regMP_HUBIF_SOC_TLB3_3; -typedef union MP_HUBIF_SOC_TLB3_4 regMP_HUBIF_SOC_TLB3_4; -typedef union MP_HUBIF_SOC_TLB3_5 regMP_HUBIF_SOC_TLB3_5; -typedef union MP_HUBIF_SOC_TLB3_6 regMP_HUBIF_SOC_TLB3_6; -typedef union MP_HUBIF_SOC_TLB3_7 regMP_HUBIF_SOC_TLB3_7; -typedef union MP_HUBIF_SOC_TLB3_8 regMP_HUBIF_SOC_TLB3_8; -typedef union MP_HUBIF_SOC_TLB3_9 regMP_HUBIF_SOC_TLB3_9; -typedef union MP_HUBIF_SOC_TLB3_10 regMP_HUBIF_SOC_TLB3_10; -typedef union MP_HUBIF_SOC_TLB3_11 regMP_HUBIF_SOC_TLB3_11; -typedef union MP_HUBIF_SOC_TLB3_12 regMP_HUBIF_SOC_TLB3_12; -typedef union MP_HUBIF_SOC_TLB3_13 regMP_HUBIF_SOC_TLB3_13; -typedef union MP_HUBIF_SOC_TLB3_14 regMP_HUBIF_SOC_TLB3_14; -typedef union MP_HUBIF_SOC_TLB3_15 regMP_HUBIF_SOC_TLB3_15; -typedef union MP_HUBIF_SOC_TLB3_16 regMP_HUBIF_SOC_TLB3_16; -typedef union MP_HUBIF_SOC_TLB3_17 regMP_HUBIF_SOC_TLB3_17; -typedef union MP_HUBIF_SOC_TLB3_18 regMP_HUBIF_SOC_TLB3_18; -typedef union MP_HUBIF_SOC_TLB3_19 regMP_HUBIF_SOC_TLB3_19; -typedef union MP_HUBIF_SOC_TLB3_20 regMP_HUBIF_SOC_TLB3_20; -typedef union MP_HUBIF_SOC_TLB3_21 regMP_HUBIF_SOC_TLB3_21; -typedef union MP_HUBIF_SOC_TLB3_22 regMP_HUBIF_SOC_TLB3_22; -typedef union MP_HUBIF_SOC_TLB3_23 regMP_HUBIF_SOC_TLB3_23; -typedef union MP_HUBIF_SOC_TLB3_24 regMP_HUBIF_SOC_TLB3_24; -typedef union MP_HUBIF_SOC_TLB3_25 regMP_HUBIF_SOC_TLB3_25; -typedef union MP_HUBIF_SOC_TLB3_26 regMP_HUBIF_SOC_TLB3_26; -typedef union MP_HUBIF_SOC_TLB3_27 regMP_HUBIF_SOC_TLB3_27; -typedef union MP_HUBIF_SOC_TLB3_28 regMP_HUBIF_SOC_TLB3_28; -typedef union MP_HUBIF_SOC_TLB3_29 regMP_HUBIF_SOC_TLB3_29; -typedef union MP_HUBIF_SOC_TLB3_30 regMP_HUBIF_SOC_TLB3_30; -typedef union MP_HUBIF_SOC_TLB3_31 regMP_HUBIF_SOC_TLB3_31; -typedef union MP_HUBIF_SOC_TLB3_32 regMP_HUBIF_SOC_TLB3_32; -typedef union MP_HUBIF_SOC_TLB3_33 regMP_HUBIF_SOC_TLB3_33; -typedef union MP_HUBIF_SOC_TLB3_34 regMP_HUBIF_SOC_TLB3_34; -typedef union MP_HUBIF_SOC_TLB3_35 regMP_HUBIF_SOC_TLB3_35; -typedef union MP_HUBIF_SOC_TLB3_36 regMP_HUBIF_SOC_TLB3_36; -typedef union MP_HUBIF_SOC_TLB3_37 regMP_HUBIF_SOC_TLB3_37; -typedef union MP_HUBIF_SOC_TLB3_38 regMP_HUBIF_SOC_TLB3_38; -typedef union MP_HUBIF_SOC_TLB3_39 regMP_HUBIF_SOC_TLB3_39; -typedef union MP_HUBIF_SOC_TLB3_40 regMP_HUBIF_SOC_TLB3_40; -typedef union MP_HUBIF_SOC_TLB3_41 regMP_HUBIF_SOC_TLB3_41; -typedef union MP_HUBIF_SOC_TLB3_42 regMP_HUBIF_SOC_TLB3_42; -typedef union MP_HUBIF_SOC_TLB3_43 regMP_HUBIF_SOC_TLB3_43; -typedef union MP_HUBIF_SOC_TLB3_44 regMP_HUBIF_SOC_TLB3_44; -typedef union MP_HUBIF_SOC_TLB3_45 regMP_HUBIF_SOC_TLB3_45; -typedef union MP_HUBIF_SOC_TLB3_46 regMP_HUBIF_SOC_TLB3_46; -typedef union MP_HUBIF_SOC_TLB3_47 regMP_HUBIF_SOC_TLB3_47; -typedef union MP_HUBIF_SOC_TLB3_48 regMP_HUBIF_SOC_TLB3_48; -typedef union MP_HUBIF_SOC_TLB3_49 regMP_HUBIF_SOC_TLB3_49; -typedef union MP_HUBIF_SOC_TLB3_50 regMP_HUBIF_SOC_TLB3_50; -typedef union MP_HUBIF_SOC_TLB3_51 regMP_HUBIF_SOC_TLB3_51; -typedef union MP_HUBIF_SOC_TLB3_52 regMP_HUBIF_SOC_TLB3_52; -typedef union MP_HUBIF_SOC_TLB3_53 regMP_HUBIF_SOC_TLB3_53; -typedef union MP_HUBIF_SOC_TLB3_54 regMP_HUBIF_SOC_TLB3_54; -typedef union MP_HUBIF_SOC_TLB3_55 regMP_HUBIF_SOC_TLB3_55; -typedef union MP_HUBIF_SOC_TLB3_56 regMP_HUBIF_SOC_TLB3_56; -typedef union MP_HUBIF_SOC_TLB3_57 regMP_HUBIF_SOC_TLB3_57; -typedef union MP_HUBIF_SOC_TLB3_58 regMP_HUBIF_SOC_TLB3_58; -typedef union MP_HUBIF_SOC_TLB3_59 regMP_HUBIF_SOC_TLB3_59; -typedef union MP_HUBIF_SOC_TLB3_60 regMP_HUBIF_SOC_TLB3_60; -typedef union MP_HUBIF_SOC_TLB3_61 regMP_HUBIF_SOC_TLB3_61; -typedef union MP_HUBIF_SOC_TLB3_62 regMP_HUBIF_SOC_TLB3_62; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_1 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_1; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_2 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_2; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_3 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_3; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_4 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_4; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_5 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_5; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_6 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_6; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_7 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_7; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_8 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_8; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_9 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_9; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_10 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_10; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_11 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_11; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_12 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_12; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_13 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_13; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_14 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_14; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_15 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_15; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_16 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_16; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_17 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_17; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_18 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_18; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_19 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_19; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_20 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_20; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_21 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_21; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_22 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_22; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_23 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_23; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_24 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_24; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_25 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_25; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_26 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_26; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_27 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_27; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_28 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_28; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_29 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_29; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_30 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_30; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_31 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_31; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_32 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_32; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_33 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_33; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_34 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_34; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_35 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_35; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_36 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_36; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_37 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_37; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_38 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_38; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_39 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_39; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_40 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_40; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_41 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_41; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_42 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_42; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_43 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_43; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_44 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_44; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_45 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_45; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_46 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_46; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_47 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_47; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_48 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_48; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_49 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_49; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_50 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_50; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_51 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_51; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_52 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_52; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_53 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_53; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_54 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_54; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_55 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_55; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_56 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_56; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_57 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_57; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_58 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_58; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_59 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_59; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_60 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_60; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_61 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_61; -typedef union MP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_62 regMP_HUBIF_TLB_SUB_PAGE_ATTRIBUTE_RW_62; -typedef union MP_HUBIF_TLB_ATTRIBUTE_1 regMP_HUBIF_TLB_ATTRIBUTE_1; -typedef union MP_HUBIF_TLB_ATTRIBUTE_2 regMP_HUBIF_TLB_ATTRIBUTE_2; -typedef union MP_HUBIF_TLB_ATTRIBUTE_3 regMP_HUBIF_TLB_ATTRIBUTE_3; -typedef union MP_HUBIF_TLB_ATTRIBUTE_4 regMP_HUBIF_TLB_ATTRIBUTE_4; -typedef union MP_HUBIF_TLB_ATTRIBUTE_5 regMP_HUBIF_TLB_ATTRIBUTE_5; -typedef union MP_HUBIF_TLB_ATTRIBUTE_6 regMP_HUBIF_TLB_ATTRIBUTE_6; -typedef union MP_HUBIF_TLB_ATTRIBUTE_7 regMP_HUBIF_TLB_ATTRIBUTE_7; -typedef union MP_HUBIF_TLB_ATTRIBUTE_8 regMP_HUBIF_TLB_ATTRIBUTE_8; -typedef union MP_HUBIF_TLB_ATTRIBUTE_9 regMP_HUBIF_TLB_ATTRIBUTE_9; -typedef union MP_HUBIF_TLB_ATTRIBUTE_10 regMP_HUBIF_TLB_ATTRIBUTE_10; -typedef union MP_HUBIF_TLB_ATTRIBUTE_11 regMP_HUBIF_TLB_ATTRIBUTE_11; -typedef union MP_HUBIF_TLB_ATTRIBUTE_12 regMP_HUBIF_TLB_ATTRIBUTE_12; -typedef union MP_HUBIF_TLB_ATTRIBUTE_13 regMP_HUBIF_TLB_ATTRIBUTE_13; -typedef union MP_HUBIF_TLB_ATTRIBUTE_14 regMP_HUBIF_TLB_ATTRIBUTE_14; -typedef union MP_HUBIF_TLB_ATTRIBUTE_15 regMP_HUBIF_TLB_ATTRIBUTE_15; -typedef union MP_HUBIF_TLB_ATTRIBUTE_16 regMP_HUBIF_TLB_ATTRIBUTE_16; -typedef union MP_HUBIF_TLB_ATTRIBUTE_17 regMP_HUBIF_TLB_ATTRIBUTE_17; -typedef union MP_HUBIF_TLB_ATTRIBUTE_18 regMP_HUBIF_TLB_ATTRIBUTE_18; -typedef union MP_HUBIF_TLB_ATTRIBUTE_19 regMP_HUBIF_TLB_ATTRIBUTE_19; -typedef union MP_HUBIF_TLB_ATTRIBUTE_20 regMP_HUBIF_TLB_ATTRIBUTE_20; -typedef union MP_HUBIF_TLB_ATTRIBUTE_21 regMP_HUBIF_TLB_ATTRIBUTE_21; -typedef union MP_HUBIF_TLB_ATTRIBUTE_22 regMP_HUBIF_TLB_ATTRIBUTE_22; -typedef union MP_HUBIF_TLB_ATTRIBUTE_23 regMP_HUBIF_TLB_ATTRIBUTE_23; -typedef union MP_HUBIF_TLB_ATTRIBUTE_24 regMP_HUBIF_TLB_ATTRIBUTE_24; -typedef union MP_HUBIF_TLB_ATTRIBUTE_25 regMP_HUBIF_TLB_ATTRIBUTE_25; -typedef union MP_HUBIF_TLB_ATTRIBUTE_26 regMP_HUBIF_TLB_ATTRIBUTE_26; -typedef union MP_HUBIF_TLB_ATTRIBUTE_27 regMP_HUBIF_TLB_ATTRIBUTE_27; -typedef union MP_HUBIF_TLB_ATTRIBUTE_28 regMP_HUBIF_TLB_ATTRIBUTE_28; -typedef union MP_HUBIF_TLB_ATTRIBUTE_29 regMP_HUBIF_TLB_ATTRIBUTE_29; -typedef union MP_HUBIF_TLB_ATTRIBUTE_30 regMP_HUBIF_TLB_ATTRIBUTE_30; -typedef union MP_HUBIF_TLB_ATTRIBUTE_31 regMP_HUBIF_TLB_ATTRIBUTE_31; -typedef union MP_HUBIF_TLB_ATTRIBUTE_32 regMP_HUBIF_TLB_ATTRIBUTE_32; -typedef union MP_HUBIF_TLB_ATTRIBUTE_33 regMP_HUBIF_TLB_ATTRIBUTE_33; -typedef union MP_HUBIF_TLB_ATTRIBUTE_34 regMP_HUBIF_TLB_ATTRIBUTE_34; -typedef union MP_HUBIF_TLB_ATTRIBUTE_35 regMP_HUBIF_TLB_ATTRIBUTE_35; -typedef union MP_HUBIF_TLB_ATTRIBUTE_36 regMP_HUBIF_TLB_ATTRIBUTE_36; -typedef union MP_HUBIF_TLB_ATTRIBUTE_37 regMP_HUBIF_TLB_ATTRIBUTE_37; -typedef union MP_HUBIF_TLB_ATTRIBUTE_38 regMP_HUBIF_TLB_ATTRIBUTE_38; -typedef union MP_HUBIF_TLB_ATTRIBUTE_39 regMP_HUBIF_TLB_ATTRIBUTE_39; -typedef union MP_HUBIF_TLB_ATTRIBUTE_40 regMP_HUBIF_TLB_ATTRIBUTE_40; -typedef union MP_HUBIF_TLB_ATTRIBUTE_41 regMP_HUBIF_TLB_ATTRIBUTE_41; -typedef union MP_HUBIF_TLB_ATTRIBUTE_42 regMP_HUBIF_TLB_ATTRIBUTE_42; -typedef union MP_HUBIF_TLB_ATTRIBUTE_43 regMP_HUBIF_TLB_ATTRIBUTE_43; -typedef union MP_HUBIF_TLB_ATTRIBUTE_44 regMP_HUBIF_TLB_ATTRIBUTE_44; -typedef union MP_HUBIF_TLB_ATTRIBUTE_45 regMP_HUBIF_TLB_ATTRIBUTE_45; -typedef union MP_HUBIF_TLB_ATTRIBUTE_46 regMP_HUBIF_TLB_ATTRIBUTE_46; -typedef union MP_HUBIF_TLB_ATTRIBUTE_47 regMP_HUBIF_TLB_ATTRIBUTE_47; -typedef union MP_HUBIF_TLB_ATTRIBUTE_48 regMP_HUBIF_TLB_ATTRIBUTE_48; -typedef union MP_HUBIF_TLB_ATTRIBUTE_49 regMP_HUBIF_TLB_ATTRIBUTE_49; -typedef union MP_HUBIF_TLB_ATTRIBUTE_50 regMP_HUBIF_TLB_ATTRIBUTE_50; -typedef union MP_HUBIF_TLB_ATTRIBUTE_51 regMP_HUBIF_TLB_ATTRIBUTE_51; -typedef union MP_HUBIF_TLB_ATTRIBUTE_52 regMP_HUBIF_TLB_ATTRIBUTE_52; -typedef union MP_HUBIF_TLB_ATTRIBUTE_53 regMP_HUBIF_TLB_ATTRIBUTE_53; -typedef union MP_HUBIF_TLB_ATTRIBUTE_54 regMP_HUBIF_TLB_ATTRIBUTE_54; -typedef union MP_HUBIF_TLB_ATTRIBUTE_55 regMP_HUBIF_TLB_ATTRIBUTE_55; -typedef union MP_HUBIF_TLB_ATTRIBUTE_56 regMP_HUBIF_TLB_ATTRIBUTE_56; -typedef union MP_HUBIF_TLB_ATTRIBUTE_57 regMP_HUBIF_TLB_ATTRIBUTE_57; -typedef union MP_HUBIF_TLB_ATTRIBUTE_58 regMP_HUBIF_TLB_ATTRIBUTE_58; -typedef union MP_HUBIF_TLB_ATTRIBUTE_59 regMP_HUBIF_TLB_ATTRIBUTE_59; -typedef union MP_HUBIF_TLB_ATTRIBUTE_60 regMP_HUBIF_TLB_ATTRIBUTE_60; -typedef union MP_HUBIF_TLB_ATTRIBUTE_61 regMP_HUBIF_TLB_ATTRIBUTE_61; -typedef union MP_HUBIF_TLB_ATTRIBUTE_62 regMP_HUBIF_TLB_ATTRIBUTE_62; -typedef union MP_HUBIF_INT_STATUS regMP_HUBIF_INT_STATUS; -typedef union MP_HUBIF_WR_INT_ADDR regMP_HUBIF_WR_INT_ADDR; -typedef union MP_HUBIF_WR_INT_OTHER regMP_HUBIF_WR_INT_OTHER; -typedef union MP_HUBIF_RD_INT_ADDR regMP_HUBIF_RD_INT_ADDR; -typedef union MP_HUBIF_RD_INT_OTHER regMP_HUBIF_RD_INT_OTHER; -typedef union MP_HUBIF_REG_INT_ADDR regMP_HUBIF_REG_INT_ADDR; -typedef union MP_HUBIF_REG_INT_OTHER regMP_HUBIF_REG_INT_OTHER; -typedef union MP_HUBIF_AXCACHE_CFG regMP_HUBIF_AXCACHE_CFG; -typedef union MP_HUBIF_DS_OVERRIDE regMP_HUBIF_DS_OVERRIDE; -typedef union MP_HUBIF_OUTSTANDING regMP_HUBIF_OUTSTANDING; -typedef union HUBIF_NB_AX_ADDR_LO regHUBIF_NB_AX_ADDR_LO; -typedef union HUBIF_NB_AX_MISC regHUBIF_NB_AX_MISC; -typedef union HUBIF_NB_AX_MISC_2 regHUBIF_NB_AX_MISC_2; -typedef union HUBIF_NB_WSTRB0 regHUBIF_NB_WSTRB0; -typedef union HUBIF_NB_WSTRB1 regHUBIF_NB_WSTRB1; -typedef union HUBIF_NB_WDATA0 regHUBIF_NB_WDATA0; -typedef union HUBIF_NB_WDATA1 regHUBIF_NB_WDATA1; -typedef union HUBIF_NB_WDATA2 regHUBIF_NB_WDATA2; -typedef union HUBIF_NB_WDATA3 regHUBIF_NB_WDATA3; -typedef union HUBIF_NB_WDATA4 regHUBIF_NB_WDATA4; -typedef union HUBIF_NB_WDATA5 regHUBIF_NB_WDATA5; -typedef union HUBIF_NB_WDATA6 regHUBIF_NB_WDATA6; -typedef union HUBIF_NB_WDATA7 regHUBIF_NB_WDATA7; -typedef union HUBIF_NB_WDATA8 regHUBIF_NB_WDATA8; -typedef union HUBIF_NB_WDATA9 regHUBIF_NB_WDATA9; -typedef union HUBIF_NB_WDATA10 regHUBIF_NB_WDATA10; -typedef union HUBIF_NB_WDATA11 regHUBIF_NB_WDATA11; -typedef union HUBIF_NB_WDATA12 regHUBIF_NB_WDATA12; -typedef union HUBIF_NB_WDATA13 regHUBIF_NB_WDATA13; -typedef union HUBIF_NB_WDATA14 regHUBIF_NB_WDATA14; -typedef union HUBIF_NB_WDATA15 regHUBIF_NB_WDATA15; -typedef union HUBIF_NB_RDATA0 regHUBIF_NB_RDATA0; -typedef union HUBIF_NB_RDATA1 regHUBIF_NB_RDATA1; -typedef union HUBIF_NB_RDATA2 regHUBIF_NB_RDATA2; -typedef union HUBIF_NB_RDATA3 regHUBIF_NB_RDATA3; -typedef union HUBIF_NB_RDATA4 regHUBIF_NB_RDATA4; -typedef union HUBIF_NB_RDATA5 regHUBIF_NB_RDATA5; -typedef union HUBIF_NB_RDATA6 regHUBIF_NB_RDATA6; -typedef union HUBIF_NB_RDATA7 regHUBIF_NB_RDATA7; -typedef union HUBIF_NB_RDATA8 regHUBIF_NB_RDATA8; -typedef union HUBIF_NB_RDATA9 regHUBIF_NB_RDATA9; -typedef union HUBIF_NB_RDATA10 regHUBIF_NB_RDATA10; -typedef union HUBIF_NB_RDATA11 regHUBIF_NB_RDATA11; -typedef union HUBIF_NB_RDATA12 regHUBIF_NB_RDATA12; -typedef union HUBIF_NB_RDATA13 regHUBIF_NB_RDATA13; -typedef union HUBIF_NB_RDATA14 regHUBIF_NB_RDATA14; -typedef union HUBIF_NB_RDATA15 regHUBIF_NB_RDATA15; -typedef union HUBIF_NB_AXI_RESP regHUBIF_NB_AXI_RESP; -typedef union HUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS regHUBIF_NB_ACC_VIOLATION_INT_LOG_STATUS; -typedef union HUBIF_ACC_VIOLATION_LOG_ADDR regHUBIF_ACC_VIOLATION_LOG_ADDR; -typedef union SMNIF_TLB_0 regSMNIF_TLB_0; -typedef union SMNIF_TLB_1 regSMNIF_TLB_1; -typedef union SMNIF_TLB_2 regSMNIF_TLB_2; -typedef union SMNIF_TLB_3 regSMNIF_TLB_3; -typedef union SMNIF_TLB_4 regSMNIF_TLB_4; -typedef union SMNIF_TLB_5 regSMNIF_TLB_5; -typedef union SMNIF_TLB_6 regSMNIF_TLB_6; -typedef union SMNIF_TLB_7 regSMNIF_TLB_7; -typedef union SMNIF_TLB_8 regSMNIF_TLB_8; -typedef union SMNIF_TLB_9 regSMNIF_TLB_9; -typedef union SMNIF_TLB_10 regSMNIF_TLB_10; -typedef union SMNIF_TLB_11 regSMNIF_TLB_11; -typedef union SMNIF_TLB_12 regSMNIF_TLB_12; -typedef union SMNIF_TLB_13 regSMNIF_TLB_13; -typedef union SMNIF_TLB_14 regSMNIF_TLB_14; -typedef union SMNIF_TLB_15 regSMNIF_TLB_15; -typedef union SMNIF_TLV0 regSMNIF_TLV0; -typedef union SMNIF_TLV1 regSMNIF_TLV1; -typedef union SMNIF_TLV2 regSMNIF_TLV2; -typedef union SMNIF_TLV3 regSMNIF_TLV3; -typedef union SMNIF_TLB_QOS regSMNIF_TLB_QOS; -typedef union SMNIF_ACC_VIOLATION_LOG_ADDR regSMNIF_ACC_VIOLATION_LOG_ADDR; -typedef union SMNIF_ACC_VIOLATION_LOG_STATUS regSMNIF_ACC_VIOLATION_LOG_STATUS; -typedef union SMNIF_LPBK_WR_VIOL_ADDR regSMNIF_LPBK_WR_VIOL_ADDR; -typedef union SMNIF_LPBK_WR_VIOL_STATUS regSMNIF_LPBK_WR_VIOL_STATUS; -typedef union SMNIF_LPBK_RD_VIOL_ADDR regSMNIF_LPBK_RD_VIOL_ADDR; -typedef union SMNIF_LPBK_RD_VIOL_STATUS regSMNIF_LPBK_RD_VIOL_STATUS; -typedef union SMNIF_MISC_CTRL regSMNIF_MISC_CTRL; -typedef union SMNIF_REQ_CNT regSMNIF_REQ_CNT; -typedef union SMNIF_SCRATCH0 regSMNIF_SCRATCH0; -typedef union SMNIF_SCRATCH1 regSMNIF_SCRATCH1; -typedef union SMNIF_SCRATCH2 regSMNIF_SCRATCH2; -typedef union SMNIF_SCRATCH3 regSMNIF_SCRATCH3; -typedef union SMNIF_SECURE_CTRL regSMNIF_SECURE_CTRL; -typedef union SMNIF_TLVMASK_SECURE regSMNIF_TLVMASK_SECURE; -typedef union SMNIF_TLVMASK_NONSECURE regSMNIF_TLVMASK_NONSECURE; -typedef union SMNIF_TLR_0 regSMNIF_TLR_0; -typedef union SMNIF_TLR_ADDR_0 regSMNIF_TLR_ADDR_0; -typedef union SMNIF_TLR_1 regSMNIF_TLR_1; -typedef union SMNIF_TLR_ADDR_1 regSMNIF_TLR_ADDR_1; -typedef union SMNIF_TLR_2 regSMNIF_TLR_2; -typedef union SMNIF_TLR_ADDR_2 regSMNIF_TLR_ADDR_2; -typedef union SMNIF_TLR_3 regSMNIF_TLR_3; -typedef union SMNIF_TLR_ADDR_3 regSMNIF_TLR_ADDR_3; -typedef union SMNIF_TLR_4 regSMNIF_TLR_4; -typedef union SMNIF_TLR_ADDR_4 regSMNIF_TLR_ADDR_4; -typedef union SMNIF_TLR_5 regSMNIF_TLR_5; -typedef union SMNIF_TLR_ADDR_5 regSMNIF_TLR_ADDR_5; -typedef union SMNIF_TLR_6 regSMNIF_TLR_6; -typedef union SMNIF_TLR_ADDR_6 regSMNIF_TLR_ADDR_6; -typedef union SMNIF_TLR_7 regSMNIF_TLR_7; -typedef union SMNIF_TLR_ADDR_7 regSMNIF_TLR_ADDR_7; -typedef union SMNIF_TLR_8 regSMNIF_TLR_8; -typedef union SMNIF_TLR_ADDR_8 regSMNIF_TLR_ADDR_8; -typedef union SMNIF_TLR_9 regSMNIF_TLR_9; -typedef union SMNIF_TLR_ADDR_9 regSMNIF_TLR_ADDR_9; -typedef union SMNIF_TLR_10 regSMNIF_TLR_10; -typedef union SMNIF_TLR_ADDR_10 regSMNIF_TLR_ADDR_10; -typedef union SMNIF_TLR_11 regSMNIF_TLR_11; -typedef union SMNIF_TLR_ADDR_11 regSMNIF_TLR_ADDR_11; -typedef union SMNIF_TLR_12 regSMNIF_TLR_12; -typedef union SMNIF_TLR_ADDR_12 regSMNIF_TLR_ADDR_12; -typedef union SMNIF_TLR_13 regSMNIF_TLR_13; -typedef union SMNIF_TLR_ADDR_13 regSMNIF_TLR_ADDR_13; -typedef union SMNIF_TLR_14 regSMNIF_TLR_14; -typedef union SMNIF_TLR_ADDR_14 regSMNIF_TLR_ADDR_14; -typedef union SMNIF_TLR_15 regSMNIF_TLR_15; -typedef union SMNIF_TLR_ADDR_15 regSMNIF_TLR_ADDR_15; -typedef union MP_ROM_ACC_VIOLATION_LOG_ADDR regMP_ROM_ACC_VIOLATION_LOG_ADDR; -typedef union MP_ROM_ACC_VIOLATION_LOG_STATUS regMP_ROM_ACC_VIOLATION_LOG_STATUS; -typedef union MP_ROM_MISC_CNTL regMP_ROM_MISC_CNTL; -typedef union MP_ROM_SCRATCH_0 regMP_ROM_SCRATCH_0; -typedef union MP_ROM_SCRATCH_1 regMP_ROM_SCRATCH_1; -typedef union MP_ROM_SCRATCH_2 regMP_ROM_SCRATCH_2; -typedef union MP_ROM_SCRATCH_3 regMP_ROM_SCRATCH_3; -typedef union DMAC_ACC_VIOLATION_LOG_ADDR regDMAC_ACC_VIOLATION_LOG_ADDR; -typedef union DMAC_ACC_VIOLATION_LOG_STATUS regDMAC_ACC_VIOLATION_LOG_STATUS; -typedef union DMAC_MISC_CTRL regDMAC_MISC_CTRL; -typedef union SMUSVI0_PLANE1_LOAD regSMUSVI0_PLANE1_LOAD; -typedef union SMUSVI0_PLANE0_LOAD regSMUSVI0_PLANE0_LOAD; -typedef union SMUSVI0_TFN regSMUSVI0_TFN; -typedef union SMUSVI0_TEL_PLANE1 regSMUSVI0_TEL_PLANE1; -typedef union SMUSVI0_TEL_PLANE0 regSMUSVI0_TEL_PLANE0; -typedef union SMUSVI1_TEL_PLANE0 regSMUSVI1_TEL_PLANE0; -typedef union SMUSVI1_PLANE0_LOAD regSMUSVI1_PLANE0_LOAD; -typedef union SMUSVI1_TFN regSMUSVI1_TFN; -typedef union SMUSVI1_PLANE0_PSI0 regSMUSVI1_PLANE0_PSI0; -typedef union SMUSVI0_MISC_VID_STATUS regSMUSVI0_MISC_VID_STATUS; -typedef union SMUSVI0_PWR_CTL_MISC regSMUSVI0_PWR_CTL_MISC; -typedef union SMUSVI0_PLANE_VIDCHG regSMUSVI0_PLANE_VIDCHG; -typedef union SMUSVI1_PLANE_VIDCHG regSMUSVI1_PLANE_VIDCHG; -typedef union SMUSVI_WARMRESET_TARGET_VID regSMUSVI_WARMRESET_TARGET_VID; -typedef union SMUSVI_WARMRESET_SEL regSMUSVI_WARMRESET_SEL; -typedef union SMUSVI0_PLANE0_VIDCHGBUSY regSMUSVI0_PLANE0_VIDCHGBUSY; -typedef union SMUSVI0_PLANE1_VIDCHGBUSY regSMUSVI0_PLANE1_VIDCHGBUSY; -typedef union SMUSVI1_PLANE0_VIDCHGBUSY regSMUSVI1_PLANE0_VIDCHGBUSY; -typedef union SMUSVI1_PLANE1_VIDCHGBUSY regSMUSVI1_PLANE1_VIDCHGBUSY; -typedef union SMUSVI0_PLANE0_CURRENTVID regSMUSVI0_PLANE0_CURRENTVID; -typedef union SMUSVI1_PLANE0_CURRENTVID regSMUSVI1_PLANE0_CURRENTVID; -typedef union SMUSVI0_PLANE1_CURRENTVID regSMUSVI0_PLANE1_CURRENTVID; -typedef union SMUSVI_ALL_CPU_IN_CC6 regSMUSVI_ALL_CPU_IN_CC6; -typedef union SMUSVI_BOOTVID regSMUSVI_BOOTVID; -typedef union SMUSVI_STARTUP_VID_COMPLETE regSMUSVI_STARTUP_VID_COMPLETE; -typedef union SMUSVI_WARM_RESET regSMUSVI_WARM_RESET; -typedef union SMUSVI_SVC0 regSMUSVI_SVC0; -typedef union SMUSVI_SVD0 regSMUSVI_SVD0; -typedef union SMUSVI_SVT0 regSMUSVI_SVT0; -typedef union SMUSVI_PLANE_USAGE regSMUSVI_PLANE_USAGE; -typedef union SMUIO_MCM_CONFIG regSMUIO_MCM_CONFIG; -typedef union SMUSVI_STARTUP_VID_EN regSMUSVI_STARTUP_VID_EN; -typedef union SMUSVI_STARTUP_VID_TRIGGER regSMUSVI_STARTUP_VID_TRIGGER; -typedef union SMUIO_RESET_SEL regSMUIO_RESET_SEL; -typedef union SMUIO_MP_RESET_INTR regSMUIO_MP_RESET_INTR; -typedef union SMUIO_RESET_DELAY regSMUIO_RESET_DELAY; -typedef union ROM_CNTL regROM_CNTL; -typedef union PAGE_MIRROR_CNTL regPAGE_MIRROR_CNTL; -typedef union ROM_STATUS regROM_STATUS; -typedef union CGTT_ROM_CLK_CTRL0 regCGTT_ROM_CLK_CTRL0; -typedef union ROM_INDEX regROM_INDEX; -typedef union ROM_DATA regROM_DATA; -typedef union ROM_START regROM_START; -typedef union ROM_SW_CNTL regROM_SW_CNTL; -typedef union ROM_SW_STATUS regROM_SW_STATUS; -typedef union ROM_SW_COMMAND regROM_SW_COMMAND; -typedef union ROM_SW_DATA_1 regROM_SW_DATA_1; -typedef union ROM_SW_DATA_2 regROM_SW_DATA_2; -typedef union ROM_SW_DATA_3 regROM_SW_DATA_3; -typedef union ROM_SW_DATA_4 regROM_SW_DATA_4; -typedef union ROM_SW_DATA_5 regROM_SW_DATA_5; -typedef union ROM_SW_DATA_6 regROM_SW_DATA_6; -typedef union ROM_SW_DATA_7 regROM_SW_DATA_7; -typedef union ROM_SW_DATA_8 regROM_SW_DATA_8; -typedef union ROM_SW_DATA_9 regROM_SW_DATA_9; -typedef union ROM_SW_DATA_10 regROM_SW_DATA_10; -typedef union ROM_SW_DATA_11 regROM_SW_DATA_11; -typedef union ROM_SW_DATA_12 regROM_SW_DATA_12; -typedef union ROM_SW_DATA_13 regROM_SW_DATA_13; -typedef union ROM_SW_DATA_14 regROM_SW_DATA_14; -typedef union ROM_SW_DATA_15 regROM_SW_DATA_15; -typedef union ROM_SW_DATA_16 regROM_SW_DATA_16; -typedef union ROM_SW_DATA_17 regROM_SW_DATA_17; -typedef union ROM_SW_DATA_18 regROM_SW_DATA_18; -typedef union ROM_SW_DATA_19 regROM_SW_DATA_19; -typedef union ROM_SW_DATA_20 regROM_SW_DATA_20; -typedef union ROM_SW_DATA_21 regROM_SW_DATA_21; -typedef union ROM_SW_DATA_22 regROM_SW_DATA_22; -typedef union ROM_SW_DATA_23 regROM_SW_DATA_23; -typedef union ROM_SW_DATA_24 regROM_SW_DATA_24; -typedef union ROM_SW_DATA_25 regROM_SW_DATA_25; -typedef union ROM_SW_DATA_26 regROM_SW_DATA_26; -typedef union ROM_SW_DATA_27 regROM_SW_DATA_27; -typedef union ROM_SW_DATA_28 regROM_SW_DATA_28; -typedef union ROM_SW_DATA_29 regROM_SW_DATA_29; -typedef union ROM_SW_DATA_30 regROM_SW_DATA_30; -typedef union ROM_SW_DATA_31 regROM_SW_DATA_31; -typedef union ROM_SW_DATA_32 regROM_SW_DATA_32; -typedef union ROM_SW_DATA_33 regROM_SW_DATA_33; -typedef union ROM_SW_DATA_34 regROM_SW_DATA_34; -typedef union ROM_SW_DATA_35 regROM_SW_DATA_35; -typedef union ROM_SW_DATA_36 regROM_SW_DATA_36; -typedef union ROM_SW_DATA_37 regROM_SW_DATA_37; -typedef union ROM_SW_DATA_38 regROM_SW_DATA_38; -typedef union ROM_SW_DATA_39 regROM_SW_DATA_39; -typedef union ROM_SW_DATA_40 regROM_SW_DATA_40; -typedef union ROM_SW_DATA_41 regROM_SW_DATA_41; -typedef union ROM_SW_DATA_42 regROM_SW_DATA_42; -typedef union ROM_SW_DATA_43 regROM_SW_DATA_43; -typedef union ROM_SW_DATA_44 regROM_SW_DATA_44; -typedef union ROM_SW_DATA_45 regROM_SW_DATA_45; -typedef union ROM_SW_DATA_46 regROM_SW_DATA_46; -typedef union ROM_SW_DATA_47 regROM_SW_DATA_47; -typedef union ROM_SW_DATA_48 regROM_SW_DATA_48; -typedef union ROM_SW_DATA_49 regROM_SW_DATA_49; -typedef union ROM_SW_DATA_50 regROM_SW_DATA_50; -typedef union ROM_SW_DATA_51 regROM_SW_DATA_51; -typedef union ROM_SW_DATA_52 regROM_SW_DATA_52; -typedef union ROM_SW_DATA_53 regROM_SW_DATA_53; -typedef union ROM_SW_DATA_54 regROM_SW_DATA_54; -typedef union ROM_SW_DATA_55 regROM_SW_DATA_55; -typedef union ROM_SW_DATA_56 regROM_SW_DATA_56; -typedef union ROM_SW_DATA_57 regROM_SW_DATA_57; -typedef union ROM_SW_DATA_58 regROM_SW_DATA_58; -typedef union ROM_SW_DATA_59 regROM_SW_DATA_59; -typedef union ROM_SW_DATA_60 regROM_SW_DATA_60; -typedef union ROM_SW_DATA_61 regROM_SW_DATA_61; -typedef union ROM_SW_DATA_62 regROM_SW_DATA_62; -typedef union ROM_SW_DATA_63 regROM_SW_DATA_63; -typedef union ROM_SW_DATA_64 regROM_SW_DATA_64; -typedef union SMU_GPIOPAD_SW_INT_STAT regSMU_GPIOPAD_SW_INT_STAT; -typedef union SMU_GPIOPAD_MASK regSMU_GPIOPAD_MASK; -typedef union SMU_GPIOPAD_A regSMU_GPIOPAD_A; -typedef union SMU_GPIOPAD_TXIMPSEL regSMU_GPIOPAD_TXIMPSEL; -typedef union SMU_GPIOPAD_EN regSMU_GPIOPAD_EN; -typedef union SMU_GPIOPAD_Y regSMU_GPIOPAD_Y; -typedef union SMU_GPIOPAD_RXEN regSMU_GPIOPAD_RXEN; -typedef union SMU_GPIOPAD_RCVR_SEL0 regSMU_GPIOPAD_RCVR_SEL0; -typedef union SMU_GPIOPAD_RCVR_SEL1 regSMU_GPIOPAD_RCVR_SEL1; -typedef union SMU_GPIOPAD_PU_EN regSMU_GPIOPAD_PU_EN; -typedef union SMU_GPIOPAD_PD_EN regSMU_GPIOPAD_PD_EN; -typedef union SMU_GPIOPAD_PINSTRAPS regSMU_GPIOPAD_PINSTRAPS; -typedef union SMU_GPIOPAD_INT_STAT_EN regSMU_GPIOPAD_INT_STAT_EN; -typedef union SMU_GPIOPAD_INT_STAT regSMU_GPIOPAD_INT_STAT; -typedef union SMU_GPIOPAD_INT_STAT_AK regSMU_GPIOPAD_INT_STAT_AK; -typedef union SMU_GPIOPAD_INT_EN regSMU_GPIOPAD_INT_EN; -typedef union SMU_GPIOPAD_INT_TYPE regSMU_GPIOPAD_INT_TYPE; -typedef union SMU_GPIOPAD_INT_POLARITY regSMU_GPIOPAD_INT_POLARITY; -typedef union ROM_CC_BIF_PINSTRAP regROM_CC_BIF_PINSTRAP; -typedef union IO_SMUIO_PINSTRAP regIO_SMUIO_PINSTRAP; -typedef union SMUIO_PCC_CONTROL regSMUIO_PCC_CONTROL; -typedef union SMUIO_PCC_GPIO_SELECT regSMUIO_PCC_GPIO_SELECT; -typedef union SMUIO_GPIO_INT_SELECT regSMUIO_GPIO_INT_SELECT; -typedef union SMIO_INDEX regSMIO_INDEX; -typedef union S0_VID_SMIO_CNTL regS0_VID_SMIO_CNTL; -typedef union S1_VID_SMIO_CNTL regS1_VID_SMIO_CNTL; -typedef union OPEN_DRAIN_SELECT regOPEN_DRAIN_SELECT; -typedef union SMIO_ENABLE regSMIO_ENABLE; -typedef union CPL_VDDCR_SOC_IDLE regCPL_VDDCR_SOC_IDLE; -typedef union ROM_SW_SECURE regROM_SW_SECURE; -typedef union GDS_CONFIG regGDS_CONFIG; -typedef union GDS_CNTL_STATUS regGDS_CNTL_STATUS; -typedef union GDS_ENHANCE2 regGDS_ENHANCE2; -typedef union GDS_PROTECTION_FAULT regGDS_PROTECTION_FAULT; -typedef union GDS_VM_PROTECTION_FAULT regGDS_VM_PROTECTION_FAULT; -typedef union GDS_EDC_CNT regGDS_EDC_CNT; -typedef union GDS_EDC_GRBM_CNT regGDS_EDC_GRBM_CNT; -typedef union GDS_EDC_OA_DED regGDS_EDC_OA_DED; -typedef union GDS_DEBUG_CNTL regGDS_DEBUG_CNTL; -typedef union GDS_DEBUG_DATA regGDS_DEBUG_DATA; -typedef union GDS_DSM_CNTL regGDS_DSM_CNTL; -typedef union GDS_EDC_OA_PHY_CNT regGDS_EDC_OA_PHY_CNT; -typedef union GDS_EDC_OA_PIPE_CNT regGDS_EDC_OA_PIPE_CNT; -typedef union GDS_DSM_CNTL2 regGDS_DSM_CNTL2; -typedef union GDS_WD_GDS_CSB regGDS_WD_GDS_CSB; -typedef union GDS_VMID0_BASE regGDS_VMID0_BASE; -typedef union GDS_VMID1_BASE regGDS_VMID1_BASE; -typedef union GDS_VMID2_BASE regGDS_VMID2_BASE; -typedef union GDS_VMID3_BASE regGDS_VMID3_BASE; -typedef union GDS_VMID4_BASE regGDS_VMID4_BASE; -typedef union GDS_VMID5_BASE regGDS_VMID5_BASE; -typedef union GDS_VMID6_BASE regGDS_VMID6_BASE; -typedef union GDS_VMID7_BASE regGDS_VMID7_BASE; -typedef union GDS_VMID8_BASE regGDS_VMID8_BASE; -typedef union GDS_VMID9_BASE regGDS_VMID9_BASE; -typedef union GDS_VMID10_BASE regGDS_VMID10_BASE; -typedef union GDS_VMID11_BASE regGDS_VMID11_BASE; -typedef union GDS_VMID12_BASE regGDS_VMID12_BASE; -typedef union GDS_VMID13_BASE regGDS_VMID13_BASE; -typedef union GDS_VMID14_BASE regGDS_VMID14_BASE; -typedef union GDS_VMID15_BASE regGDS_VMID15_BASE; -typedef union GDS_VMID0_SIZE regGDS_VMID0_SIZE; -typedef union GDS_VMID1_SIZE regGDS_VMID1_SIZE; -typedef union GDS_VMID2_SIZE regGDS_VMID2_SIZE; -typedef union GDS_VMID3_SIZE regGDS_VMID3_SIZE; -typedef union GDS_VMID4_SIZE regGDS_VMID4_SIZE; -typedef union GDS_VMID5_SIZE regGDS_VMID5_SIZE; -typedef union GDS_VMID6_SIZE regGDS_VMID6_SIZE; -typedef union GDS_VMID7_SIZE regGDS_VMID7_SIZE; -typedef union GDS_VMID8_SIZE regGDS_VMID8_SIZE; -typedef union GDS_VMID9_SIZE regGDS_VMID9_SIZE; -typedef union GDS_VMID10_SIZE regGDS_VMID10_SIZE; -typedef union GDS_VMID11_SIZE regGDS_VMID11_SIZE; -typedef union GDS_VMID12_SIZE regGDS_VMID12_SIZE; -typedef union GDS_VMID13_SIZE regGDS_VMID13_SIZE; -typedef union GDS_VMID14_SIZE regGDS_VMID14_SIZE; -typedef union GDS_VMID15_SIZE regGDS_VMID15_SIZE; -typedef union GDS_GWS_VMID0 regGDS_GWS_VMID0; -typedef union GDS_GWS_VMID1 regGDS_GWS_VMID1; -typedef union GDS_GWS_VMID2 regGDS_GWS_VMID2; -typedef union GDS_GWS_VMID3 regGDS_GWS_VMID3; -typedef union GDS_GWS_VMID4 regGDS_GWS_VMID4; -typedef union GDS_GWS_VMID5 regGDS_GWS_VMID5; -typedef union GDS_GWS_VMID6 regGDS_GWS_VMID6; -typedef union GDS_GWS_VMID7 regGDS_GWS_VMID7; -typedef union GDS_GWS_VMID8 regGDS_GWS_VMID8; -typedef union GDS_GWS_VMID9 regGDS_GWS_VMID9; -typedef union GDS_GWS_VMID10 regGDS_GWS_VMID10; -typedef union GDS_GWS_VMID11 regGDS_GWS_VMID11; -typedef union GDS_GWS_VMID12 regGDS_GWS_VMID12; -typedef union GDS_GWS_VMID13 regGDS_GWS_VMID13; -typedef union GDS_GWS_VMID14 regGDS_GWS_VMID14; -typedef union GDS_GWS_VMID15 regGDS_GWS_VMID15; -typedef union GDS_OA_VMID0 regGDS_OA_VMID0; -typedef union GDS_OA_VMID1 regGDS_OA_VMID1; -typedef union GDS_OA_VMID2 regGDS_OA_VMID2; -typedef union GDS_OA_VMID3 regGDS_OA_VMID3; -typedef union GDS_OA_VMID4 regGDS_OA_VMID4; -typedef union GDS_OA_VMID5 regGDS_OA_VMID5; -typedef union GDS_OA_VMID6 regGDS_OA_VMID6; -typedef union GDS_OA_VMID7 regGDS_OA_VMID7; -typedef union GDS_OA_VMID8 regGDS_OA_VMID8; -typedef union GDS_OA_VMID9 regGDS_OA_VMID9; -typedef union GDS_OA_VMID10 regGDS_OA_VMID10; -typedef union GDS_OA_VMID11 regGDS_OA_VMID11; -typedef union GDS_OA_VMID12 regGDS_OA_VMID12; -typedef union GDS_OA_VMID13 regGDS_OA_VMID13; -typedef union GDS_OA_VMID14 regGDS_OA_VMID14; -typedef union GDS_OA_VMID15 regGDS_OA_VMID15; -typedef union GDS_GWS_RESET0 regGDS_GWS_RESET0; -typedef union GDS_GWS_RESET1 regGDS_GWS_RESET1; -typedef union GDS_GWS_RESOURCE_RESET regGDS_GWS_RESOURCE_RESET; -typedef union GDS_COMPUTE_MAX_WAVE_ID regGDS_COMPUTE_MAX_WAVE_ID; -typedef union GDS_OA_RESET_MASK regGDS_OA_RESET_MASK; -typedef union GDS_OA_RESET regGDS_OA_RESET; -typedef union GDS_ENHANCE regGDS_ENHANCE; -typedef union GDS_OA_CGPG_RESTORE regGDS_OA_CGPG_RESTORE; -typedef union GDS_CS_CTXSW_STATUS regGDS_CS_CTXSW_STATUS; -typedef union GDS_CS_CTXSW_CNT0 regGDS_CS_CTXSW_CNT0; -typedef union GDS_CS_CTXSW_CNT1 regGDS_CS_CTXSW_CNT1; -typedef union GDS_CS_CTXSW_CNT2 regGDS_CS_CTXSW_CNT2; -typedef union GDS_CS_CTXSW_CNT3 regGDS_CS_CTXSW_CNT3; -typedef union GDS_GFX_CTXSW_STATUS regGDS_GFX_CTXSW_STATUS; -typedef union GDS_VS_CTXSW_CNT0 regGDS_VS_CTXSW_CNT0; -typedef union GDS_VS_CTXSW_CNT1 regGDS_VS_CTXSW_CNT1; -typedef union GDS_VS_CTXSW_CNT2 regGDS_VS_CTXSW_CNT2; -typedef union GDS_VS_CTXSW_CNT3 regGDS_VS_CTXSW_CNT3; -typedef union GDS_PS0_CTXSW_CNT0 regGDS_PS0_CTXSW_CNT0; -typedef union GDS_PS1_CTXSW_CNT0 regGDS_PS1_CTXSW_CNT0; -typedef union GDS_PS2_CTXSW_CNT0 regGDS_PS2_CTXSW_CNT0; -typedef union GDS_PS3_CTXSW_CNT0 regGDS_PS3_CTXSW_CNT0; -typedef union GDS_PS4_CTXSW_CNT0 regGDS_PS4_CTXSW_CNT0; -typedef union GDS_PS5_CTXSW_CNT0 regGDS_PS5_CTXSW_CNT0; -typedef union GDS_PS6_CTXSW_CNT0 regGDS_PS6_CTXSW_CNT0; -typedef union GDS_PS7_CTXSW_CNT0 regGDS_PS7_CTXSW_CNT0; -typedef union GDS_PS0_CTXSW_CNT1 regGDS_PS0_CTXSW_CNT1; -typedef union GDS_PS1_CTXSW_CNT1 regGDS_PS1_CTXSW_CNT1; -typedef union GDS_PS2_CTXSW_CNT1 regGDS_PS2_CTXSW_CNT1; -typedef union GDS_PS3_CTXSW_CNT1 regGDS_PS3_CTXSW_CNT1; -typedef union GDS_PS4_CTXSW_CNT1 regGDS_PS4_CTXSW_CNT1; -typedef union GDS_PS5_CTXSW_CNT1 regGDS_PS5_CTXSW_CNT1; -typedef union GDS_PS6_CTXSW_CNT1 regGDS_PS6_CTXSW_CNT1; -typedef union GDS_PS7_CTXSW_CNT1 regGDS_PS7_CTXSW_CNT1; -typedef union GDS_PS0_CTXSW_CNT2 regGDS_PS0_CTXSW_CNT2; -typedef union GDS_PS1_CTXSW_CNT2 regGDS_PS1_CTXSW_CNT2; -typedef union GDS_PS2_CTXSW_CNT2 regGDS_PS2_CTXSW_CNT2; -typedef union GDS_PS3_CTXSW_CNT2 regGDS_PS3_CTXSW_CNT2; -typedef union GDS_PS4_CTXSW_CNT2 regGDS_PS4_CTXSW_CNT2; -typedef union GDS_PS5_CTXSW_CNT2 regGDS_PS5_CTXSW_CNT2; -typedef union GDS_PS6_CTXSW_CNT2 regGDS_PS6_CTXSW_CNT2; -typedef union GDS_PS7_CTXSW_CNT2 regGDS_PS7_CTXSW_CNT2; -typedef union GDS_PS0_CTXSW_CNT3 regGDS_PS0_CTXSW_CNT3; -typedef union GDS_PS1_CTXSW_CNT3 regGDS_PS1_CTXSW_CNT3; -typedef union GDS_PS2_CTXSW_CNT3 regGDS_PS2_CTXSW_CNT3; -typedef union GDS_PS3_CTXSW_CNT3 regGDS_PS3_CTXSW_CNT3; -typedef union GDS_PS4_CTXSW_CNT3 regGDS_PS4_CTXSW_CNT3; -typedef union GDS_PS5_CTXSW_CNT3 regGDS_PS5_CTXSW_CNT3; -typedef union GDS_PS6_CTXSW_CNT3 regGDS_PS6_CTXSW_CNT3; -typedef union GDS_PS7_CTXSW_CNT3 regGDS_PS7_CTXSW_CNT3; -typedef union GDS_GS_CTXSW_CNT0 regGDS_GS_CTXSW_CNT0; -typedef union GDS_GS_CTXSW_CNT1 regGDS_GS_CTXSW_CNT1; -typedef union GDS_GS_CTXSW_CNT2 regGDS_GS_CTXSW_CNT2; -typedef union GDS_GS_CTXSW_CNT3 regGDS_GS_CTXSW_CNT3; -typedef union GDS_RD_ADDR regGDS_RD_ADDR; -typedef union GDS_RD_DATA regGDS_RD_DATA; -typedef union GDS_RD_BURST_ADDR regGDS_RD_BURST_ADDR; -typedef union GDS_RD_BURST_COUNT regGDS_RD_BURST_COUNT; -typedef union GDS_RD_BURST_DATA regGDS_RD_BURST_DATA; -typedef union GDS_WR_ADDR regGDS_WR_ADDR; -typedef union GDS_WR_DATA regGDS_WR_DATA; -typedef union GDS_WR_BURST_ADDR regGDS_WR_BURST_ADDR; -typedef union GDS_WR_BURST_DATA regGDS_WR_BURST_DATA; -typedef union GDS_WRITE_COMPLETE regGDS_WRITE_COMPLETE; -typedef union GDS_ATOM_CNTL regGDS_ATOM_CNTL; -typedef union GDS_ATOM_COMPLETE regGDS_ATOM_COMPLETE; -typedef union GDS_ATOM_BASE regGDS_ATOM_BASE; -typedef union GDS_ATOM_SIZE regGDS_ATOM_SIZE; -typedef union GDS_ATOM_OFFSET0 regGDS_ATOM_OFFSET0; -typedef union GDS_ATOM_OFFSET1 regGDS_ATOM_OFFSET1; -typedef union GDS_ATOM_DST regGDS_ATOM_DST; -typedef union GDS_ATOM_OP regGDS_ATOM_OP; -typedef union GDS_ATOM_SRC0 regGDS_ATOM_SRC0; -typedef union GDS_ATOM_SRC0_U regGDS_ATOM_SRC0_U; -typedef union GDS_ATOM_SRC1 regGDS_ATOM_SRC1; -typedef union GDS_ATOM_SRC1_U regGDS_ATOM_SRC1_U; -typedef union GDS_ATOM_READ0 regGDS_ATOM_READ0; -typedef union GDS_ATOM_READ0_U regGDS_ATOM_READ0_U; -typedef union GDS_ATOM_READ1 regGDS_ATOM_READ1; -typedef union GDS_ATOM_READ1_U regGDS_ATOM_READ1_U; -typedef union GDS_GWS_RESOURCE_CNTL regGDS_GWS_RESOURCE_CNTL; -typedef union GDS_GWS_RESOURCE regGDS_GWS_RESOURCE; -typedef union GDS_GWS_RESOURCE_CNT regGDS_GWS_RESOURCE_CNT; -typedef union GDS_OA_CNTL regGDS_OA_CNTL; -typedef union GDS_OA_COUNTER regGDS_OA_COUNTER; -typedef union GDS_OA_ADDRESS regGDS_OA_ADDRESS; -typedef union GDS_OA_INCDEC regGDS_OA_INCDEC; -typedef union GDS_OA_RING_SIZE regGDS_OA_RING_SIZE; -typedef union GDS_PERFCOUNTER0_LO regGDS_PERFCOUNTER0_LO; -typedef union GDS_PERFCOUNTER1_LO regGDS_PERFCOUNTER1_LO; -typedef union GDS_PERFCOUNTER2_LO regGDS_PERFCOUNTER2_LO; -typedef union GDS_PERFCOUNTER3_LO regGDS_PERFCOUNTER3_LO; -typedef union GDS_PERFCOUNTER0_HI regGDS_PERFCOUNTER0_HI; -typedef union GDS_PERFCOUNTER1_HI regGDS_PERFCOUNTER1_HI; -typedef union GDS_PERFCOUNTER2_HI regGDS_PERFCOUNTER2_HI; -typedef union GDS_PERFCOUNTER3_HI regGDS_PERFCOUNTER3_HI; -typedef union GDS_PERFCOUNTER0_SELECT regGDS_PERFCOUNTER0_SELECT; -typedef union GDS_PERFCOUNTER1_SELECT regGDS_PERFCOUNTER1_SELECT; -typedef union GDS_PERFCOUNTER2_SELECT regGDS_PERFCOUNTER2_SELECT; -typedef union GDS_PERFCOUNTER3_SELECT regGDS_PERFCOUNTER3_SELECT; -typedef union GDS_PERFCOUNTER0_SELECT1 regGDS_PERFCOUNTER0_SELECT1; -typedef union CGTT_GDS_CLK_CTRL regCGTT_GDS_CLK_CTRL; -typedef union GDS_DEBUG_REG0 regGDS_DEBUG_REG0; -typedef union GDS_DEBUG_REG1 regGDS_DEBUG_REG1; -typedef union GDS_DEBUG_REG2 regGDS_DEBUG_REG2; -typedef union GDS_DEBUG_REG3 regGDS_DEBUG_REG3; -typedef union GDS_DEBUG_REG4 regGDS_DEBUG_REG4; -typedef union GDS_DEBUG_REG5 regGDS_DEBUG_REG5; -typedef union GDS_DEBUG_REG6 regGDS_DEBUG_REG6; -typedef union GDS_DEBUG_REG7 regGDS_DEBUG_REG7; -typedef union GDS_DEBUG_REG8 regGDS_DEBUG_REG8; -typedef union CB_HW_CONTROL regCB_HW_CONTROL; -typedef union CB_HW_CONTROL_1 regCB_HW_CONTROL_1; -typedef union CB_HW_CONTROL_2 regCB_HW_CONTROL_2; -typedef union CB_HW_CONTROL_3 regCB_HW_CONTROL_3; -typedef union CB_HW_MEM_ARBITER_RD regCB_HW_MEM_ARBITER_RD; -typedef union CB_HW_MEM_ARBITER_WR regCB_HW_MEM_ARBITER_WR; -typedef union CB_DCC_CONFIG regCB_DCC_CONFIG; -typedef union CB_DEBUG_BUS_1 regCB_DEBUG_BUS_1; -typedef union CB_DEBUG_BUS_2 regCB_DEBUG_BUS_2; -typedef union CB_DEBUG_BUS_3 regCB_DEBUG_BUS_3; -typedef union CB_DEBUG_BUS_4 regCB_DEBUG_BUS_4; -typedef union CB_DEBUG_BUS_5 regCB_DEBUG_BUS_5; -typedef union CB_DEBUG_BUS_6 regCB_DEBUG_BUS_6; -typedef union CB_DEBUG_BUS_7 regCB_DEBUG_BUS_7; -typedef union CB_DEBUG_BUS_8 regCB_DEBUG_BUS_8; -typedef union CB_DEBUG_BUS_9 regCB_DEBUG_BUS_9; -typedef union CB_DEBUG_BUS_10 regCB_DEBUG_BUS_10; -typedef union CB_DEBUG_BUS_11 regCB_DEBUG_BUS_11; -typedef union CB_DEBUG_BUS_12 regCB_DEBUG_BUS_12; -typedef union CB_DEBUG_BUS_13 regCB_DEBUG_BUS_13; -typedef union CB_DEBUG_BUS_14 regCB_DEBUG_BUS_14; -typedef union CB_DEBUG_BUS_15 regCB_DEBUG_BUS_15; -typedef union CB_DEBUG_BUS_16 regCB_DEBUG_BUS_16; -typedef union CB_DEBUG_BUS_17 regCB_DEBUG_BUS_17; -typedef union CB_DEBUG_BUS_18 regCB_DEBUG_BUS_18; -typedef union CB_DEBUG_BUS_19 regCB_DEBUG_BUS_19; -typedef union CB_DEBUG_BUS_20 regCB_DEBUG_BUS_20; -typedef union CB_DEBUG_BUS_21 regCB_DEBUG_BUS_21; -typedef union CB_DEBUG_BUS_22 regCB_DEBUG_BUS_22; -typedef union CB_BLEND_RED regCB_BLEND_RED; -typedef union CB_BLEND_GREEN regCB_BLEND_GREEN; -typedef union CB_BLEND_BLUE regCB_BLEND_BLUE; -typedef union CB_BLEND_ALPHA regCB_BLEND_ALPHA; -typedef union CB_DCC_CONTROL regCB_DCC_CONTROL; -typedef union CB_COLOR_CONTROL regCB_COLOR_CONTROL; -typedef union CB_BLEND0_CONTROL regCB_BLEND0_CONTROL; -typedef union CB_BLEND1_CONTROL regCB_BLEND1_CONTROL; -typedef union CB_BLEND2_CONTROL regCB_BLEND2_CONTROL; -typedef union CB_BLEND3_CONTROL regCB_BLEND3_CONTROL; -typedef union CB_BLEND4_CONTROL regCB_BLEND4_CONTROL; -typedef union CB_BLEND5_CONTROL regCB_BLEND5_CONTROL; -typedef union CB_BLEND6_CONTROL regCB_BLEND6_CONTROL; -typedef union CB_BLEND7_CONTROL regCB_BLEND7_CONTROL; -typedef union CB_MRT0_EPITCH regCB_MRT0_EPITCH; -typedef union CB_MRT1_EPITCH regCB_MRT1_EPITCH; -typedef union CB_MRT2_EPITCH regCB_MRT2_EPITCH; -typedef union CB_MRT3_EPITCH regCB_MRT3_EPITCH; -typedef union CB_MRT4_EPITCH regCB_MRT4_EPITCH; -typedef union CB_MRT5_EPITCH regCB_MRT5_EPITCH; -typedef union CB_MRT6_EPITCH regCB_MRT6_EPITCH; -typedef union CB_MRT7_EPITCH regCB_MRT7_EPITCH; -typedef union CB_COLOR0_BASE regCB_COLOR0_BASE; -typedef union CB_COLOR1_BASE regCB_COLOR1_BASE; -typedef union CB_COLOR2_BASE regCB_COLOR2_BASE; -typedef union CB_COLOR3_BASE regCB_COLOR3_BASE; -typedef union CB_COLOR4_BASE regCB_COLOR4_BASE; -typedef union CB_COLOR5_BASE regCB_COLOR5_BASE; -typedef union CB_COLOR6_BASE regCB_COLOR6_BASE; -typedef union CB_COLOR7_BASE regCB_COLOR7_BASE; -typedef union CB_COLOR0_BASE_EXT regCB_COLOR0_BASE_EXT; -typedef union CB_COLOR1_BASE_EXT regCB_COLOR1_BASE_EXT; -typedef union CB_COLOR2_BASE_EXT regCB_COLOR2_BASE_EXT; -typedef union CB_COLOR3_BASE_EXT regCB_COLOR3_BASE_EXT; -typedef union CB_COLOR4_BASE_EXT regCB_COLOR4_BASE_EXT; -typedef union CB_COLOR5_BASE_EXT regCB_COLOR5_BASE_EXT; -typedef union CB_COLOR6_BASE_EXT regCB_COLOR6_BASE_EXT; -typedef union CB_COLOR7_BASE_EXT regCB_COLOR7_BASE_EXT; -typedef union CB_COLOR0_ATTRIB2 regCB_COLOR0_ATTRIB2; -typedef union CB_COLOR1_ATTRIB2 regCB_COLOR1_ATTRIB2; -typedef union CB_COLOR2_ATTRIB2 regCB_COLOR2_ATTRIB2; -typedef union CB_COLOR3_ATTRIB2 regCB_COLOR3_ATTRIB2; -typedef union CB_COLOR4_ATTRIB2 regCB_COLOR4_ATTRIB2; -typedef union CB_COLOR5_ATTRIB2 regCB_COLOR5_ATTRIB2; -typedef union CB_COLOR6_ATTRIB2 regCB_COLOR6_ATTRIB2; -typedef union CB_COLOR7_ATTRIB2 regCB_COLOR7_ATTRIB2; -typedef union CB_COLOR0_VIEW regCB_COLOR0_VIEW; -typedef union CB_COLOR1_VIEW regCB_COLOR1_VIEW; -typedef union CB_COLOR2_VIEW regCB_COLOR2_VIEW; -typedef union CB_COLOR3_VIEW regCB_COLOR3_VIEW; -typedef union CB_COLOR4_VIEW regCB_COLOR4_VIEW; -typedef union CB_COLOR5_VIEW regCB_COLOR5_VIEW; -typedef union CB_COLOR6_VIEW regCB_COLOR6_VIEW; -typedef union CB_COLOR7_VIEW regCB_COLOR7_VIEW; -typedef union CB_COLOR0_INFO regCB_COLOR0_INFO; -typedef union CB_COLOR1_INFO regCB_COLOR1_INFO; -typedef union CB_COLOR2_INFO regCB_COLOR2_INFO; -typedef union CB_COLOR3_INFO regCB_COLOR3_INFO; -typedef union CB_COLOR4_INFO regCB_COLOR4_INFO; -typedef union CB_COLOR5_INFO regCB_COLOR5_INFO; -typedef union CB_COLOR6_INFO regCB_COLOR6_INFO; -typedef union CB_COLOR7_INFO regCB_COLOR7_INFO; -typedef union CB_COLOR0_ATTRIB regCB_COLOR0_ATTRIB; -typedef union CB_COLOR1_ATTRIB regCB_COLOR1_ATTRIB; -typedef union CB_COLOR2_ATTRIB regCB_COLOR2_ATTRIB; -typedef union CB_COLOR3_ATTRIB regCB_COLOR3_ATTRIB; -typedef union CB_COLOR4_ATTRIB regCB_COLOR4_ATTRIB; -typedef union CB_COLOR5_ATTRIB regCB_COLOR5_ATTRIB; -typedef union CB_COLOR6_ATTRIB regCB_COLOR6_ATTRIB; -typedef union CB_COLOR7_ATTRIB regCB_COLOR7_ATTRIB; -typedef union CB_COLOR0_DCC_CONTROL regCB_COLOR0_DCC_CONTROL; -typedef union CB_COLOR1_DCC_CONTROL regCB_COLOR1_DCC_CONTROL; -typedef union CB_COLOR2_DCC_CONTROL regCB_COLOR2_DCC_CONTROL; -typedef union CB_COLOR3_DCC_CONTROL regCB_COLOR3_DCC_CONTROL; -typedef union CB_COLOR4_DCC_CONTROL regCB_COLOR4_DCC_CONTROL; -typedef union CB_COLOR5_DCC_CONTROL regCB_COLOR5_DCC_CONTROL; -typedef union CB_COLOR6_DCC_CONTROL regCB_COLOR6_DCC_CONTROL; -typedef union CB_COLOR7_DCC_CONTROL regCB_COLOR7_DCC_CONTROL; -typedef union CB_COLOR0_CMASK regCB_COLOR0_CMASK; -typedef union CB_COLOR1_CMASK regCB_COLOR1_CMASK; -typedef union CB_COLOR2_CMASK regCB_COLOR2_CMASK; -typedef union CB_COLOR3_CMASK regCB_COLOR3_CMASK; -typedef union CB_COLOR4_CMASK regCB_COLOR4_CMASK; -typedef union CB_COLOR5_CMASK regCB_COLOR5_CMASK; -typedef union CB_COLOR6_CMASK regCB_COLOR6_CMASK; -typedef union CB_COLOR7_CMASK regCB_COLOR7_CMASK; -typedef union CB_COLOR0_CMASK_BASE_EXT regCB_COLOR0_CMASK_BASE_EXT; -typedef union CB_COLOR1_CMASK_BASE_EXT regCB_COLOR1_CMASK_BASE_EXT; -typedef union CB_COLOR2_CMASK_BASE_EXT regCB_COLOR2_CMASK_BASE_EXT; -typedef union CB_COLOR3_CMASK_BASE_EXT regCB_COLOR3_CMASK_BASE_EXT; -typedef union CB_COLOR4_CMASK_BASE_EXT regCB_COLOR4_CMASK_BASE_EXT; -typedef union CB_COLOR5_CMASK_BASE_EXT regCB_COLOR5_CMASK_BASE_EXT; -typedef union CB_COLOR6_CMASK_BASE_EXT regCB_COLOR6_CMASK_BASE_EXT; -typedef union CB_COLOR7_CMASK_BASE_EXT regCB_COLOR7_CMASK_BASE_EXT; -typedef union CB_COLOR0_FMASK regCB_COLOR0_FMASK; -typedef union CB_COLOR1_FMASK regCB_COLOR1_FMASK; -typedef union CB_COLOR2_FMASK regCB_COLOR2_FMASK; -typedef union CB_COLOR3_FMASK regCB_COLOR3_FMASK; -typedef union CB_COLOR4_FMASK regCB_COLOR4_FMASK; -typedef union CB_COLOR5_FMASK regCB_COLOR5_FMASK; -typedef union CB_COLOR6_FMASK regCB_COLOR6_FMASK; -typedef union CB_COLOR7_FMASK regCB_COLOR7_FMASK; -typedef union CB_COLOR0_FMASK_BASE_EXT regCB_COLOR0_FMASK_BASE_EXT; -typedef union CB_COLOR1_FMASK_BASE_EXT regCB_COLOR1_FMASK_BASE_EXT; -typedef union CB_COLOR2_FMASK_BASE_EXT regCB_COLOR2_FMASK_BASE_EXT; -typedef union CB_COLOR3_FMASK_BASE_EXT regCB_COLOR3_FMASK_BASE_EXT; -typedef union CB_COLOR4_FMASK_BASE_EXT regCB_COLOR4_FMASK_BASE_EXT; -typedef union CB_COLOR5_FMASK_BASE_EXT regCB_COLOR5_FMASK_BASE_EXT; -typedef union CB_COLOR6_FMASK_BASE_EXT regCB_COLOR6_FMASK_BASE_EXT; -typedef union CB_COLOR7_FMASK_BASE_EXT regCB_COLOR7_FMASK_BASE_EXT; -typedef union CB_COLOR0_CLEAR_WORD0 regCB_COLOR0_CLEAR_WORD0; -typedef union CB_COLOR1_CLEAR_WORD0 regCB_COLOR1_CLEAR_WORD0; -typedef union CB_COLOR2_CLEAR_WORD0 regCB_COLOR2_CLEAR_WORD0; -typedef union CB_COLOR3_CLEAR_WORD0 regCB_COLOR3_CLEAR_WORD0; -typedef union CB_COLOR4_CLEAR_WORD0 regCB_COLOR4_CLEAR_WORD0; -typedef union CB_COLOR5_CLEAR_WORD0 regCB_COLOR5_CLEAR_WORD0; -typedef union CB_COLOR6_CLEAR_WORD0 regCB_COLOR6_CLEAR_WORD0; -typedef union CB_COLOR7_CLEAR_WORD0 regCB_COLOR7_CLEAR_WORD0; -typedef union CB_COLOR0_CLEAR_WORD1 regCB_COLOR0_CLEAR_WORD1; -typedef union CB_COLOR1_CLEAR_WORD1 regCB_COLOR1_CLEAR_WORD1; -typedef union CB_COLOR2_CLEAR_WORD1 regCB_COLOR2_CLEAR_WORD1; -typedef union CB_COLOR3_CLEAR_WORD1 regCB_COLOR3_CLEAR_WORD1; -typedef union CB_COLOR4_CLEAR_WORD1 regCB_COLOR4_CLEAR_WORD1; -typedef union CB_COLOR5_CLEAR_WORD1 regCB_COLOR5_CLEAR_WORD1; -typedef union CB_COLOR6_CLEAR_WORD1 regCB_COLOR6_CLEAR_WORD1; -typedef union CB_COLOR7_CLEAR_WORD1 regCB_COLOR7_CLEAR_WORD1; -typedef union CB_COLOR0_DCC_BASE regCB_COLOR0_DCC_BASE; -typedef union CB_COLOR1_DCC_BASE regCB_COLOR1_DCC_BASE; -typedef union CB_COLOR2_DCC_BASE regCB_COLOR2_DCC_BASE; -typedef union CB_COLOR3_DCC_BASE regCB_COLOR3_DCC_BASE; -typedef union CB_COLOR4_DCC_BASE regCB_COLOR4_DCC_BASE; -typedef union CB_COLOR5_DCC_BASE regCB_COLOR5_DCC_BASE; -typedef union CB_COLOR6_DCC_BASE regCB_COLOR6_DCC_BASE; -typedef union CB_COLOR7_DCC_BASE regCB_COLOR7_DCC_BASE; -typedef union CB_COLOR0_DCC_BASE_EXT regCB_COLOR0_DCC_BASE_EXT; -typedef union CB_COLOR1_DCC_BASE_EXT regCB_COLOR1_DCC_BASE_EXT; -typedef union CB_COLOR2_DCC_BASE_EXT regCB_COLOR2_DCC_BASE_EXT; -typedef union CB_COLOR3_DCC_BASE_EXT regCB_COLOR3_DCC_BASE_EXT; -typedef union CB_COLOR4_DCC_BASE_EXT regCB_COLOR4_DCC_BASE_EXT; -typedef union CB_COLOR5_DCC_BASE_EXT regCB_COLOR5_DCC_BASE_EXT; -typedef union CB_COLOR6_DCC_BASE_EXT regCB_COLOR6_DCC_BASE_EXT; -typedef union CB_COLOR7_DCC_BASE_EXT regCB_COLOR7_DCC_BASE_EXT; -typedef union CB_TARGET_MASK regCB_TARGET_MASK; -typedef union CB_SHADER_MASK regCB_SHADER_MASK; -typedef union CB_PERFCOUNTER0_LO regCB_PERFCOUNTER0_LO; -typedef union CB_PERFCOUNTER1_LO regCB_PERFCOUNTER1_LO; -typedef union CB_PERFCOUNTER2_LO regCB_PERFCOUNTER2_LO; -typedef union CB_PERFCOUNTER3_LO regCB_PERFCOUNTER3_LO; -typedef union CB_PERFCOUNTER0_HI regCB_PERFCOUNTER0_HI; -typedef union CB_PERFCOUNTER1_HI regCB_PERFCOUNTER1_HI; -typedef union CB_PERFCOUNTER2_HI regCB_PERFCOUNTER2_HI; -typedef union CB_PERFCOUNTER3_HI regCB_PERFCOUNTER3_HI; -typedef union CB_PERFCOUNTER_FILTER regCB_PERFCOUNTER_FILTER; -typedef union CB_PERFCOUNTER0_SELECT regCB_PERFCOUNTER0_SELECT; -typedef union CB_PERFCOUNTER0_SELECT1 regCB_PERFCOUNTER0_SELECT1; -typedef union CB_PERFCOUNTER1_SELECT regCB_PERFCOUNTER1_SELECT; -typedef union CB_PERFCOUNTER2_SELECT regCB_PERFCOUNTER2_SELECT; -typedef union CB_PERFCOUNTER3_SELECT regCB_PERFCOUNTER3_SELECT; -typedef union CB_CGTT_SCLK_CTRL regCB_CGTT_SCLK_CTRL; -typedef union GC_CAC_CTRL_1 regGC_CAC_CTRL_1; -typedef union GC_CAC_CTRL_2 regGC_CAC_CTRL_2; -typedef union GC_CAC_CGTT_CLK_CTRL regGC_CAC_CGTT_CLK_CTRL; -typedef union GC_CAC_AGGR_LOWER regGC_CAC_AGGR_LOWER; -typedef union GC_CAC_AGGR_UPPER regGC_CAC_AGGR_UPPER; -typedef union GC_CAC_SOFT_CTRL regGC_CAC_SOFT_CTRL; -typedef union GC_DIDT_CTRL0 regGC_DIDT_CTRL0; -typedef union GC_DIDT_CTRL1 regGC_DIDT_CTRL1; -typedef union GC_DIDT_CTRL2 regGC_DIDT_CTRL2; -typedef union GC_DIDT_WEIGHT regGC_DIDT_WEIGHT; -typedef union GC_DIDT_WEIGHT_1 regGC_DIDT_WEIGHT_1; -typedef union GC_EDC_CTRL regGC_EDC_CTRL; -typedef union GC_EDC_THRESHOLD regGC_EDC_THRESHOLD; -typedef union GC_EDC_STATUS regGC_EDC_STATUS; -typedef union GC_EDC_OVERFLOW regGC_EDC_OVERFLOW; -typedef union GC_EDC_ROLLING_POWER_DELTA regGC_EDC_ROLLING_POWER_DELTA; -typedef union GC_DIDT_DROOP_CTRL regGC_DIDT_DROOP_CTRL; -typedef union GC_EDC_DROOP_CTRL regGC_EDC_DROOP_CTRL; -typedef union GC_CAC_IND_INDEX regGC_CAC_IND_INDEX; -typedef union GC_CAC_IND_DATA regGC_CAC_IND_DATA; -typedef union SE_CAC_CGTT_CLK_CTRL regSE_CAC_CGTT_CLK_CTRL; -typedef union SE_CAC_IND_INDEX regSE_CAC_IND_INDEX; -typedef union SE_CAC_IND_DATA regSE_CAC_IND_DATA; -typedef union GC_CAC_CNTL regGC_CAC_CNTL; -typedef union GC_CAC_OVR_SEL regGC_CAC_OVR_SEL; -typedef union GC_CAC_OVR_VAL regGC_CAC_OVR_VAL; -typedef union GC_CAC_WEIGHT_BCI_0 regGC_CAC_WEIGHT_BCI_0; -typedef union GC_CAC_WEIGHT_CB_0 regGC_CAC_WEIGHT_CB_0; -typedef union GC_CAC_WEIGHT_CB_1 regGC_CAC_WEIGHT_CB_1; -typedef union GC_CAC_WEIGHT_CBR_0 regGC_CAC_WEIGHT_CBR_0; -typedef union GC_CAC_WEIGHT_CBR_1 regGC_CAC_WEIGHT_CBR_1; -typedef union GC_CAC_WEIGHT_CP_0 regGC_CAC_WEIGHT_CP_0; -typedef union GC_CAC_WEIGHT_CP_1 regGC_CAC_WEIGHT_CP_1; -typedef union GC_CAC_WEIGHT_DB_0 regGC_CAC_WEIGHT_DB_0; -typedef union GC_CAC_WEIGHT_DB_1 regGC_CAC_WEIGHT_DB_1; -typedef union GC_CAC_WEIGHT_DBR_0 regGC_CAC_WEIGHT_DBR_0; -typedef union GC_CAC_WEIGHT_DBR_1 regGC_CAC_WEIGHT_DBR_1; -typedef union GC_CAC_WEIGHT_GDS_0 regGC_CAC_WEIGHT_GDS_0; -typedef union GC_CAC_WEIGHT_GDS_1 regGC_CAC_WEIGHT_GDS_1; -typedef union GC_CAC_WEIGHT_IA_0 regGC_CAC_WEIGHT_IA_0; -typedef union GC_CAC_WEIGHT_LDS_0 regGC_CAC_WEIGHT_LDS_0; -typedef union GC_CAC_WEIGHT_LDS_1 regGC_CAC_WEIGHT_LDS_1; -typedef union GC_CAC_WEIGHT_PA_0 regGC_CAC_WEIGHT_PA_0; -typedef union GC_CAC_WEIGHT_PC_0 regGC_CAC_WEIGHT_PC_0; -typedef union GC_CAC_WEIGHT_SC_0 regGC_CAC_WEIGHT_SC_0; -typedef union GC_CAC_WEIGHT_SPI_0 regGC_CAC_WEIGHT_SPI_0; -typedef union GC_CAC_WEIGHT_SPI_1 regGC_CAC_WEIGHT_SPI_1; -typedef union GC_CAC_WEIGHT_SPI_2 regGC_CAC_WEIGHT_SPI_2; -typedef union GC_CAC_WEIGHT_SQ_0 regGC_CAC_WEIGHT_SQ_0; -typedef union GC_CAC_WEIGHT_SQ_1 regGC_CAC_WEIGHT_SQ_1; -typedef union GC_CAC_WEIGHT_SQ_2 regGC_CAC_WEIGHT_SQ_2; -typedef union GC_CAC_WEIGHT_SQ_3 regGC_CAC_WEIGHT_SQ_3; -typedef union GC_CAC_WEIGHT_SQ_4 regGC_CAC_WEIGHT_SQ_4; -typedef union GC_CAC_WEIGHT_SX_0 regGC_CAC_WEIGHT_SX_0; -typedef union GC_CAC_WEIGHT_SXRB_0 regGC_CAC_WEIGHT_SXRB_0; -typedef union GC_CAC_WEIGHT_TA_0 regGC_CAC_WEIGHT_TA_0; -typedef union GC_CAC_WEIGHT_TCC_0 regGC_CAC_WEIGHT_TCC_0; -typedef union GC_CAC_WEIGHT_TCC_1 regGC_CAC_WEIGHT_TCC_1; -typedef union GC_CAC_WEIGHT_TCC_2 regGC_CAC_WEIGHT_TCC_2; -typedef union GC_CAC_WEIGHT_TCP_0 regGC_CAC_WEIGHT_TCP_0; -typedef union GC_CAC_WEIGHT_TCP_1 regGC_CAC_WEIGHT_TCP_1; -typedef union GC_CAC_WEIGHT_TCP_2 regGC_CAC_WEIGHT_TCP_2; -typedef union GC_CAC_WEIGHT_TD_0 regGC_CAC_WEIGHT_TD_0; -typedef union GC_CAC_WEIGHT_TD_1 regGC_CAC_WEIGHT_TD_1; -typedef union GC_CAC_WEIGHT_TD_2 regGC_CAC_WEIGHT_TD_2; -typedef union GC_CAC_WEIGHT_VGT_0 regGC_CAC_WEIGHT_VGT_0; -typedef union GC_CAC_WEIGHT_VGT_1 regGC_CAC_WEIGHT_VGT_1; -typedef union GC_CAC_WEIGHT_RMI_0 regGC_CAC_WEIGHT_RMI_0; -typedef union GC_CAC_WEIGHT_WD_0 regGC_CAC_WEIGHT_WD_0; -typedef union GC_CAC_WEIGHT_EA_0 regGC_CAC_WEIGHT_EA_0; -typedef union GC_CAC_WEIGHT_EA_1 regGC_CAC_WEIGHT_EA_1; -typedef union GC_CAC_WEIGHT_EA_2 regGC_CAC_WEIGHT_EA_2; -typedef union GC_CAC_WEIGHT_UTCL2_ATCL2_0 regGC_CAC_WEIGHT_UTCL2_ATCL2_0; -typedef union GC_CAC_WEIGHT_UTCL2_ATCL2_1 regGC_CAC_WEIGHT_UTCL2_ATCL2_1; -typedef union GC_CAC_WEIGHT_UTCL2_ATCL2_2 regGC_CAC_WEIGHT_UTCL2_ATCL2_2; -typedef union GC_CAC_WEIGHT_UTCL2_ROUTER_0 regGC_CAC_WEIGHT_UTCL2_ROUTER_0; -typedef union GC_CAC_WEIGHT_UTCL2_ROUTER_1 regGC_CAC_WEIGHT_UTCL2_ROUTER_1; -typedef union GC_CAC_WEIGHT_UTCL2_ROUTER_2 regGC_CAC_WEIGHT_UTCL2_ROUTER_2; -typedef union GC_CAC_WEIGHT_UTCL2_ROUTER_3 regGC_CAC_WEIGHT_UTCL2_ROUTER_3; -typedef union GC_CAC_WEIGHT_UTCL2_ROUTER_4 regGC_CAC_WEIGHT_UTCL2_ROUTER_4; -typedef union GC_CAC_WEIGHT_UTCL2_VML2_0 regGC_CAC_WEIGHT_UTCL2_VML2_0; -typedef union GC_CAC_WEIGHT_UTCL2_VML2_1 regGC_CAC_WEIGHT_UTCL2_VML2_1; -typedef union GC_CAC_WEIGHT_UTCL2_VML2_2 regGC_CAC_WEIGHT_UTCL2_VML2_2; -typedef union GC_CAC_WEIGHT_CU_0 regGC_CAC_WEIGHT_CU_0; -typedef union GC_CAC_WEIGHT_CU_1 regGC_CAC_WEIGHT_CU_1; -typedef union GC_CAC_WEIGHT_CU_2 regGC_CAC_WEIGHT_CU_2; -typedef union GC_CAC_WEIGHT_CU_3 regGC_CAC_WEIGHT_CU_3; -typedef union GC_CAC_WEIGHT_CU_4 regGC_CAC_WEIGHT_CU_4; -typedef union GC_CAC_WEIGHT_CU_5 regGC_CAC_WEIGHT_CU_5; -typedef union GC_CAC_WEIGHT_CU_6 regGC_CAC_WEIGHT_CU_6; -typedef union GC_CAC_WEIGHT_CU_7 regGC_CAC_WEIGHT_CU_7; -typedef union GC_CAC_ACC_BCI0 regGC_CAC_ACC_BCI0; -typedef union GC_CAC_ACC_BCI1 regGC_CAC_ACC_BCI1; -typedef union GC_CAC_ACC_CB0 regGC_CAC_ACC_CB0; -typedef union GC_CAC_ACC_CB1 regGC_CAC_ACC_CB1; -typedef union GC_CAC_ACC_CB2 regGC_CAC_ACC_CB2; -typedef union GC_CAC_ACC_CB3 regGC_CAC_ACC_CB3; -typedef union GC_CAC_ACC_CBR0 regGC_CAC_ACC_CBR0; -typedef union GC_CAC_ACC_CBR1 regGC_CAC_ACC_CBR1; -typedef union GC_CAC_ACC_CBR2 regGC_CAC_ACC_CBR2; -typedef union GC_CAC_ACC_CBR3 regGC_CAC_ACC_CBR3; -typedef union GC_CAC_ACC_CP0 regGC_CAC_ACC_CP0; -typedef union GC_CAC_ACC_CP1 regGC_CAC_ACC_CP1; -typedef union GC_CAC_ACC_CP2 regGC_CAC_ACC_CP2; -typedef union GC_CAC_ACC_DB0 regGC_CAC_ACC_DB0; -typedef union GC_CAC_ACC_DB1 regGC_CAC_ACC_DB1; -typedef union GC_CAC_ACC_DB2 regGC_CAC_ACC_DB2; -typedef union GC_CAC_ACC_DB3 regGC_CAC_ACC_DB3; -typedef union GC_CAC_ACC_DBR0 regGC_CAC_ACC_DBR0; -typedef union GC_CAC_ACC_DBR1 regGC_CAC_ACC_DBR1; -typedef union GC_CAC_ACC_DBR2 regGC_CAC_ACC_DBR2; -typedef union GC_CAC_ACC_DBR3 regGC_CAC_ACC_DBR3; -typedef union GC_CAC_ACC_GDS0 regGC_CAC_ACC_GDS0; -typedef union GC_CAC_ACC_GDS1 regGC_CAC_ACC_GDS1; -typedef union GC_CAC_ACC_GDS2 regGC_CAC_ACC_GDS2; -typedef union GC_CAC_ACC_GDS3 regGC_CAC_ACC_GDS3; -typedef union GC_CAC_ACC_IA0 regGC_CAC_ACC_IA0; -typedef union GC_CAC_ACC_LDS0 regGC_CAC_ACC_LDS0; -typedef union GC_CAC_ACC_LDS1 regGC_CAC_ACC_LDS1; -typedef union GC_CAC_ACC_LDS2 regGC_CAC_ACC_LDS2; -typedef union GC_CAC_ACC_LDS3 regGC_CAC_ACC_LDS3; -typedef union GC_CAC_ACC_PA0 regGC_CAC_ACC_PA0; -typedef union GC_CAC_ACC_PA1 regGC_CAC_ACC_PA1; -typedef union GC_CAC_ACC_PC0 regGC_CAC_ACC_PC0; -typedef union GC_CAC_ACC_SC0 regGC_CAC_ACC_SC0; -typedef union GC_CAC_ACC_SPI0 regGC_CAC_ACC_SPI0; -typedef union GC_CAC_ACC_SPI1 regGC_CAC_ACC_SPI1; -typedef union GC_CAC_ACC_SPI2 regGC_CAC_ACC_SPI2; -typedef union GC_CAC_ACC_SPI3 regGC_CAC_ACC_SPI3; -typedef union GC_CAC_ACC_SPI4 regGC_CAC_ACC_SPI4; -typedef union GC_CAC_ACC_SPI5 regGC_CAC_ACC_SPI5; -typedef union GC_CAC_ACC_SQ0_LOWER regGC_CAC_ACC_SQ0_LOWER; -typedef union GC_CAC_ACC_SQ0_UPPER regGC_CAC_ACC_SQ0_UPPER; -typedef union GC_CAC_ACC_SQ1_LOWER regGC_CAC_ACC_SQ1_LOWER; -typedef union GC_CAC_ACC_SQ1_UPPER regGC_CAC_ACC_SQ1_UPPER; -typedef union GC_CAC_ACC_SQ2_LOWER regGC_CAC_ACC_SQ2_LOWER; -typedef union GC_CAC_ACC_SQ2_UPPER regGC_CAC_ACC_SQ2_UPPER; -typedef union GC_CAC_ACC_SQ3_LOWER regGC_CAC_ACC_SQ3_LOWER; -typedef union GC_CAC_ACC_SQ3_UPPER regGC_CAC_ACC_SQ3_UPPER; -typedef union GC_CAC_ACC_SQ4_LOWER regGC_CAC_ACC_SQ4_LOWER; -typedef union GC_CAC_ACC_SQ4_UPPER regGC_CAC_ACC_SQ4_UPPER; -typedef union GC_CAC_ACC_SQ5_LOWER regGC_CAC_ACC_SQ5_LOWER; -typedef union GC_CAC_ACC_SQ5_UPPER regGC_CAC_ACC_SQ5_UPPER; -typedef union GC_CAC_ACC_SQ6_LOWER regGC_CAC_ACC_SQ6_LOWER; -typedef union GC_CAC_ACC_SQ6_UPPER regGC_CAC_ACC_SQ6_UPPER; -typedef union GC_CAC_ACC_SQ7_LOWER regGC_CAC_ACC_SQ7_LOWER; -typedef union GC_CAC_ACC_SQ7_UPPER regGC_CAC_ACC_SQ7_UPPER; -typedef union GC_CAC_ACC_SQ8_LOWER regGC_CAC_ACC_SQ8_LOWER; -typedef union GC_CAC_ACC_SQ8_UPPER regGC_CAC_ACC_SQ8_UPPER; -typedef union GC_CAC_ACC_SX0 regGC_CAC_ACC_SX0; -typedef union GC_CAC_ACC_SXRB0 regGC_CAC_ACC_SXRB0; -typedef union GC_CAC_ACC_SXRB1 regGC_CAC_ACC_SXRB1; -typedef union GC_CAC_ACC_TA0 regGC_CAC_ACC_TA0; -typedef union GC_CAC_ACC_TCC0 regGC_CAC_ACC_TCC0; -typedef union GC_CAC_ACC_TCC1 regGC_CAC_ACC_TCC1; -typedef union GC_CAC_ACC_TCC2 regGC_CAC_ACC_TCC2; -typedef union GC_CAC_ACC_TCC3 regGC_CAC_ACC_TCC3; -typedef union GC_CAC_ACC_TCC4 regGC_CAC_ACC_TCC4; -typedef union GC_CAC_ACC_TCP0 regGC_CAC_ACC_TCP0; -typedef union GC_CAC_ACC_TCP1 regGC_CAC_ACC_TCP1; -typedef union GC_CAC_ACC_TCP2 regGC_CAC_ACC_TCP2; -typedef union GC_CAC_ACC_TCP3 regGC_CAC_ACC_TCP3; -typedef union GC_CAC_ACC_TCP4 regGC_CAC_ACC_TCP4; -typedef union GC_CAC_ACC_TD0 regGC_CAC_ACC_TD0; -typedef union GC_CAC_ACC_TD1 regGC_CAC_ACC_TD1; -typedef union GC_CAC_ACC_TD2 regGC_CAC_ACC_TD2; -typedef union GC_CAC_ACC_TD3 regGC_CAC_ACC_TD3; -typedef union GC_CAC_ACC_TD4 regGC_CAC_ACC_TD4; -typedef union GC_CAC_ACC_TD5 regGC_CAC_ACC_TD5; -typedef union GC_CAC_ACC_VGT0 regGC_CAC_ACC_VGT0; -typedef union GC_CAC_ACC_VGT1 regGC_CAC_ACC_VGT1; -typedef union GC_CAC_ACC_VGT2 regGC_CAC_ACC_VGT2; -typedef union GC_CAC_ACC_RMI0 regGC_CAC_ACC_RMI0; -typedef union GC_CAC_ACC_WD0 regGC_CAC_ACC_WD0; -typedef union GC_CAC_ACC_EA0 regGC_CAC_ACC_EA0; -typedef union GC_CAC_ACC_EA1 regGC_CAC_ACC_EA1; -typedef union GC_CAC_ACC_EA2 regGC_CAC_ACC_EA2; -typedef union GC_CAC_ACC_EA3 regGC_CAC_ACC_EA3; -typedef union GC_CAC_ACC_EA4 regGC_CAC_ACC_EA4; -typedef union GC_CAC_ACC_EA5 regGC_CAC_ACC_EA5; -typedef union GC_CAC_ACC_UTCL2_ATCL20 regGC_CAC_ACC_UTCL2_ATCL20; -typedef union GC_CAC_ACC_UTCL2_ATCL21 regGC_CAC_ACC_UTCL2_ATCL21; -typedef union GC_CAC_ACC_UTCL2_ATCL22 regGC_CAC_ACC_UTCL2_ATCL22; -typedef union GC_CAC_ACC_UTCL2_ATCL23 regGC_CAC_ACC_UTCL2_ATCL23; -typedef union GC_CAC_ACC_UTCL2_ATCL24 regGC_CAC_ACC_UTCL2_ATCL24; -typedef union GC_CAC_ACC_UTCL2_ROUTER0 regGC_CAC_ACC_UTCL2_ROUTER0; -typedef union GC_CAC_ACC_UTCL2_ROUTER1 regGC_CAC_ACC_UTCL2_ROUTER1; -typedef union GC_CAC_ACC_UTCL2_ROUTER2 regGC_CAC_ACC_UTCL2_ROUTER2; -typedef union GC_CAC_ACC_UTCL2_ROUTER3 regGC_CAC_ACC_UTCL2_ROUTER3; -typedef union GC_CAC_ACC_UTCL2_ROUTER4 regGC_CAC_ACC_UTCL2_ROUTER4; -typedef union GC_CAC_ACC_UTCL2_ROUTER5 regGC_CAC_ACC_UTCL2_ROUTER5; -typedef union GC_CAC_ACC_UTCL2_ROUTER6 regGC_CAC_ACC_UTCL2_ROUTER6; -typedef union GC_CAC_ACC_UTCL2_ROUTER7 regGC_CAC_ACC_UTCL2_ROUTER7; -typedef union GC_CAC_ACC_UTCL2_ROUTER8 regGC_CAC_ACC_UTCL2_ROUTER8; -typedef union GC_CAC_ACC_UTCL2_ROUTER9 regGC_CAC_ACC_UTCL2_ROUTER9; -typedef union GC_CAC_ACC_UTCL2_VML20 regGC_CAC_ACC_UTCL2_VML20; -typedef union GC_CAC_ACC_UTCL2_VML21 regGC_CAC_ACC_UTCL2_VML21; -typedef union GC_CAC_ACC_UTCL2_VML22 regGC_CAC_ACC_UTCL2_VML22; -typedef union GC_CAC_ACC_UTCL2_VML23 regGC_CAC_ACC_UTCL2_VML23; -typedef union GC_CAC_ACC_UTCL2_VML24 regGC_CAC_ACC_UTCL2_VML24; -typedef union GC_CAC_ACC_CU0 regGC_CAC_ACC_CU0; -typedef union GC_CAC_ACC_CU1 regGC_CAC_ACC_CU1; -typedef union GC_CAC_ACC_CU2 regGC_CAC_ACC_CU2; -typedef union GC_CAC_ACC_CU3 regGC_CAC_ACC_CU3; -typedef union GC_CAC_ACC_CU4 regGC_CAC_ACC_CU4; -typedef union GC_CAC_ACC_CU5 regGC_CAC_ACC_CU5; -typedef union GC_CAC_ACC_CU6 regGC_CAC_ACC_CU6; -typedef union GC_CAC_ACC_CU7 regGC_CAC_ACC_CU7; -typedef union GC_CAC_ACC_CU8 regGC_CAC_ACC_CU8; -typedef union GC_CAC_ACC_CU9 regGC_CAC_ACC_CU9; -typedef union GC_CAC_ACC_CU10 regGC_CAC_ACC_CU10; -typedef union GC_CAC_ACC_CU11 regGC_CAC_ACC_CU11; -typedef union GC_CAC_ACC_CU12 regGC_CAC_ACC_CU12; -typedef union GC_CAC_ACC_CU13 regGC_CAC_ACC_CU13; -typedef union GC_CAC_ACC_CU14 regGC_CAC_ACC_CU14; -typedef union GC_CAC_ACC_CU15 regGC_CAC_ACC_CU15; -typedef union GC_CAC_OVRD_BCI regGC_CAC_OVRD_BCI; -typedef union GC_CAC_OVRD_CB regGC_CAC_OVRD_CB; -typedef union GC_CAC_OVRD_CBR regGC_CAC_OVRD_CBR; -typedef union GC_CAC_OVRD_CP regGC_CAC_OVRD_CP; -typedef union GC_CAC_OVRD_DB regGC_CAC_OVRD_DB; -typedef union GC_CAC_OVRD_DBR regGC_CAC_OVRD_DBR; -typedef union GC_CAC_OVRD_GDS regGC_CAC_OVRD_GDS; -typedef union GC_CAC_OVRD_IA regGC_CAC_OVRD_IA; -typedef union GC_CAC_OVRD_LDS regGC_CAC_OVRD_LDS; -typedef union GC_CAC_OVRD_PA regGC_CAC_OVRD_PA; -typedef union GC_CAC_OVRD_PC regGC_CAC_OVRD_PC; -typedef union GC_CAC_OVRD_SC regGC_CAC_OVRD_SC; -typedef union GC_CAC_OVRD_SPI regGC_CAC_OVRD_SPI; -typedef union GC_CAC_OVRD_CU regGC_CAC_OVRD_CU; -typedef union GC_CAC_OVRD_SQ regGC_CAC_OVRD_SQ; -typedef union GC_CAC_OVRD_SX regGC_CAC_OVRD_SX; -typedef union GC_CAC_OVRD_SXRB regGC_CAC_OVRD_SXRB; -typedef union GC_CAC_OVRD_TA regGC_CAC_OVRD_TA; -typedef union GC_CAC_OVRD_TCC regGC_CAC_OVRD_TCC; -typedef union GC_CAC_OVRD_TCP regGC_CAC_OVRD_TCP; -typedef union GC_CAC_OVRD_TD regGC_CAC_OVRD_TD; -typedef union GC_CAC_OVRD_VGT regGC_CAC_OVRD_VGT; -typedef union GC_CAC_OVRD_RMI regGC_CAC_OVRD_RMI; -typedef union GC_CAC_OVRD_WD regGC_CAC_OVRD_WD; -typedef union GC_CAC_OVRD_EA regGC_CAC_OVRD_EA; -typedef union GC_CAC_OVRD_UTCL2_ATCL2 regGC_CAC_OVRD_UTCL2_ATCL2; -typedef union GC_CAC_OVRD_UTCL2_ROUTER regGC_CAC_OVRD_UTCL2_ROUTER; -typedef union GC_CAC_OVRD_UTCL2_VML2 regGC_CAC_OVRD_UTCL2_VML2; -typedef union GC_CAC_WEIGHT_UTCL2_WALKER_0 regGC_CAC_WEIGHT_UTCL2_WALKER_0; -typedef union GC_CAC_WEIGHT_UTCL2_WALKER_1 regGC_CAC_WEIGHT_UTCL2_WALKER_1; -typedef union GC_CAC_WEIGHT_UTCL2_WALKER_2 regGC_CAC_WEIGHT_UTCL2_WALKER_2; -typedef union GC_CAC_ACC_UTCL2_WALKER0 regGC_CAC_ACC_UTCL2_WALKER0; -typedef union GC_CAC_ACC_UTCL2_WALKER1 regGC_CAC_ACC_UTCL2_WALKER1; -typedef union GC_CAC_ACC_UTCL2_WALKER2 regGC_CAC_ACC_UTCL2_WALKER2; -typedef union GC_CAC_ACC_UTCL2_WALKER3 regGC_CAC_ACC_UTCL2_WALKER3; -typedef union GC_CAC_ACC_UTCL2_WALKER4 regGC_CAC_ACC_UTCL2_WALKER4; -typedef union GC_CAC_OVRD_UTCL2_WALKER regGC_CAC_OVRD_UTCL2_WALKER; -typedef union SE_CAC_CNTL regSE_CAC_CNTL; -typedef union SE_CAC_OVR_SEL regSE_CAC_OVR_SEL; -typedef union SE_CAC_OVR_VAL regSE_CAC_OVR_VAL; -typedef union RLC_GPM_PERF_COUNT_0 regRLC_GPM_PERF_COUNT_0; -typedef union RLC_GPM_PERF_COUNT_1 regRLC_GPM_PERF_COUNT_1; -typedef union RLC_PERFCOUNTER0_LO regRLC_PERFCOUNTER0_LO; -typedef union RLC_PERFCOUNTER1_LO regRLC_PERFCOUNTER1_LO; -typedef union RLC_PERFCOUNTER0_HI regRLC_PERFCOUNTER0_HI; -typedef union RLC_PERFCOUNTER1_HI regRLC_PERFCOUNTER1_HI; -typedef union RLC_PERFMON_CLK_CNTL regRLC_PERFMON_CLK_CNTL; -typedef union RLC_PERFMON_CNTL regRLC_PERFMON_CNTL; -typedef union RLC_PERFCOUNTER0_SELECT regRLC_PERFCOUNTER0_SELECT; -typedef union RLC_PERFCOUNTER1_SELECT regRLC_PERFCOUNTER1_SELECT; -typedef union RLC_GPU_IOV_PERF_CNT_CNTL regRLC_GPU_IOV_PERF_CNT_CNTL; -typedef union RLC_GPU_IOV_PERF_CNT_WR_ADDR regRLC_GPU_IOV_PERF_CNT_WR_ADDR; -typedef union RLC_GPU_IOV_PERF_CNT_WR_DATA regRLC_GPU_IOV_PERF_CNT_WR_DATA; -typedef union RLC_GPU_IOV_PERF_CNT_RD_ADDR regRLC_GPU_IOV_PERF_CNT_RD_ADDR; -typedef union RLC_GPU_IOV_PERF_CNT_RD_DATA regRLC_GPU_IOV_PERF_CNT_RD_DATA; -typedef union RLC_SPM_PERFMON_CNTL regRLC_SPM_PERFMON_CNTL; -typedef union RLC_SPM_PERFMON_RING_BASE_LO regRLC_SPM_PERFMON_RING_BASE_LO; -typedef union RLC_SPM_PERFMON_RING_BASE_HI regRLC_SPM_PERFMON_RING_BASE_HI; -typedef union RLC_SPM_PERFMON_RING_SIZE regRLC_SPM_PERFMON_RING_SIZE; -typedef union RLC_SPM_PERFMON_SEGMENT_SIZE regRLC_SPM_PERFMON_SEGMENT_SIZE; -typedef union RLC_SPM_SE_MUXSEL_ADDR regRLC_SPM_SE_MUXSEL_ADDR; -typedef union RLC_SPM_SE_MUXSEL_DATA regRLC_SPM_SE_MUXSEL_DATA; -typedef union RLC_SPM_CPG_PERFMON_SAMPLE_DELAY regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_CPC_PERFMON_SAMPLE_DELAY regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_CPF_PERFMON_SAMPLE_DELAY regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_CB_PERFMON_SAMPLE_DELAY regRLC_SPM_CB_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_DB_PERFMON_SAMPLE_DELAY regRLC_SPM_DB_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_PA_PERFMON_SAMPLE_DELAY regRLC_SPM_PA_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_GDS_PERFMON_SAMPLE_DELAY regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_IA_PERFMON_SAMPLE_DELAY regRLC_SPM_IA_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_SC_PERFMON_SAMPLE_DELAY regRLC_SPM_SC_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_TCC_PERFMON_SAMPLE_DELAY regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_TCA_PERFMON_SAMPLE_DELAY regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_TCP_PERFMON_SAMPLE_DELAY regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_TA_PERFMON_SAMPLE_DELAY regRLC_SPM_TA_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_TD_PERFMON_SAMPLE_DELAY regRLC_SPM_TD_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_VGT_PERFMON_SAMPLE_DELAY regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_SPI_PERFMON_SAMPLE_DELAY regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_SQG_PERFMON_SAMPLE_DELAY regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_SX_PERFMON_SAMPLE_DELAY regRLC_SPM_SX_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_GLOBAL_MUXSEL_ADDR regRLC_SPM_GLOBAL_MUXSEL_ADDR; -typedef union RLC_SPM_GLOBAL_MUXSEL_DATA regRLC_SPM_GLOBAL_MUXSEL_DATA; -typedef union RLC_SPM_RING_RDPTR regRLC_SPM_RING_RDPTR; -typedef union RLC_SPM_SEGMENT_THRESHOLD regRLC_SPM_SEGMENT_THRESHOLD; -typedef union RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY regRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY regRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY regRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY regRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY; -typedef union RLC_SPM_RMI_PERFMON_SAMPLE_DELAY regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY; -typedef union RLC_CNTL regRLC_CNTL; -typedef union RLC_DEBUG_SELECT regRLC_DEBUG_SELECT; -typedef union RLC_DEBUG regRLC_DEBUG; -typedef union RLC_STAT regRLC_STAT; -typedef union RLC_INT_STAT regRLC_INT_STAT; -typedef union RLC_SAFE_MODE regRLC_SAFE_MODE; -typedef union RLC_MEM_SLP_CNTL regRLC_MEM_SLP_CNTL; -typedef union SMU_RLC_RESPONSE regSMU_RLC_RESPONSE; -typedef union RLC_RLCV_SAFE_MODE regRLC_RLCV_SAFE_MODE; -typedef union RLC_SMU_SAFE_MODE regRLC_SMU_SAFE_MODE; -typedef union RLC_RLCV_COMMAND regRLC_RLCV_COMMAND; -typedef union RLC_REFCLOCK_TIMESTAMP_LSB regRLC_REFCLOCK_TIMESTAMP_LSB; -typedef union RLC_REFCLOCK_TIMESTAMP_MSB regRLC_REFCLOCK_TIMESTAMP_MSB; -typedef union RLC_GPM_TIMER_INT_0 regRLC_GPM_TIMER_INT_0; -typedef union RLC_GPM_TIMER_INT_1 regRLC_GPM_TIMER_INT_1; -typedef union RLC_GPM_TIMER_INT_2 regRLC_GPM_TIMER_INT_2; -typedef union RLC_GPM_TIMER_INT_3 regRLC_GPM_TIMER_INT_3; -typedef union RLC_GPM_TIMER_CTRL regRLC_GPM_TIMER_CTRL; -typedef union RLC_GPM_TIMER_STAT regRLC_GPM_TIMER_STAT; -typedef union RLC_LB_CNTL regRLC_LB_CNTL; -typedef union RLC_LB_CNTR_MAX regRLC_LB_CNTR_MAX; -typedef union RLC_LB_CNTR_INIT regRLC_LB_CNTR_INIT; -typedef union RLC_LOAD_BALANCE_CNTR regRLC_LOAD_BALANCE_CNTR; -typedef union RLC_JUMP_TABLE_RESTORE regRLC_JUMP_TABLE_RESTORE; -typedef union RLC_PG_DELAY_2 regRLC_PG_DELAY_2; -typedef union RLC_GPM_DEBUG_INST_HIST regRLC_GPM_DEBUG_INST_HIST; -typedef union RLC_GPM_DEBUG_SELECT regRLC_GPM_DEBUG_SELECT; -typedef union RLC_GPM_DEBUG regRLC_GPM_DEBUG; -typedef union RLC_GPM_DEBUG_INST_A regRLC_GPM_DEBUG_INST_A; -typedef union RLC_GPM_DEBUG_INST_B regRLC_GPM_DEBUG_INST_B; -typedef union RLC_GPM_DEBUG_INST_ADDR regRLC_GPM_DEBUG_INST_ADDR; -typedef union RLC_SEMAPHORE_0 regRLC_SEMAPHORE_0; -typedef union RLC_SEMAPHORE_1 regRLC_SEMAPHORE_1; -typedef union RLC_RLCV_SPARE_INT regRLC_RLCV_SPARE_INT; -typedef union RLC_GPU_CLOCK_COUNT_LSB regRLC_GPU_CLOCK_COUNT_LSB; -typedef union RLC_GPU_CLOCK_COUNT_MSB regRLC_GPU_CLOCK_COUNT_MSB; -typedef union RLC_CAPTURE_GPU_CLOCK_COUNT regRLC_CAPTURE_GPU_CLOCK_COUNT; -typedef union RLC_UCODE_CNTL regRLC_UCODE_CNTL; -typedef union RLC_GPM_STAT regRLC_GPM_STAT; -typedef union RLC_GPU_CLOCK_32_RES_SEL regRLC_GPU_CLOCK_32_RES_SEL; -typedef union RLC_GPU_CLOCK_32 regRLC_GPU_CLOCK_32; -typedef union RLC_PG_CNTL regRLC_PG_CNTL; -typedef union RLC_GPM_THREAD_PRIORITY regRLC_GPM_THREAD_PRIORITY; -typedef union RLC_GPM_THREAD_ENABLE regRLC_GPM_THREAD_ENABLE; -typedef union RLC_CGTT_MGCG_OVERRIDE regRLC_CGTT_MGCG_OVERRIDE; -typedef union RLC_CGCG_CGLS_CTRL regRLC_CGCG_CGLS_CTRL; -typedef union RLC_CGCG_RAMP_CTRL regRLC_CGCG_RAMP_CTRL; -typedef union RLC_CGCG_CGLS_CTRL_3D regRLC_CGCG_CGLS_CTRL_3D; -typedef union RLC_CGCG_RAMP_CTRL_3D regRLC_CGCG_RAMP_CTRL_3D; -typedef union RLC_DYN_PG_STATUS regRLC_DYN_PG_STATUS; -typedef union RLC_DYN_PG_REQUEST regRLC_DYN_PG_REQUEST; -typedef union RLC_PG_DELAY regRLC_PG_DELAY; -typedef union RLC_CU_STATUS regRLC_CU_STATUS; -typedef union RLC_LB_INIT_CU_MASK regRLC_LB_INIT_CU_MASK; -typedef union RLC_LB_ALWAYS_ACTIVE_CU_MASK regRLC_LB_ALWAYS_ACTIVE_CU_MASK; -typedef union RLC_LB_PARAMS regRLC_LB_PARAMS; -typedef union RLC_THREAD1_DELAY regRLC_THREAD1_DELAY; -typedef union RLC_LB_THR_CONFIG_1 regRLC_LB_THR_CONFIG_1; -typedef union RLC_LB_THR_CONFIG_2 regRLC_LB_THR_CONFIG_2; -typedef union RLC_LB_THR_CONFIG_3 regRLC_LB_THR_CONFIG_3; -typedef union RLC_LB_THR_CONFIG_4 regRLC_LB_THR_CONFIG_4; -typedef union RLC_LB_DEBUG_1 regRLC_LB_DEBUG_1; -typedef union RLC_PG_ALWAYS_ON_CU_MASK regRLC_PG_ALWAYS_ON_CU_MASK; -typedef union RLC_MAX_PG_CU regRLC_MAX_PG_CU; -typedef union RLC_AUTO_PG_CTRL regRLC_AUTO_PG_CTRL; -typedef union RLC_SMU_GRBM_REG_SAVE_CTRL regRLC_SMU_GRBM_REG_SAVE_CTRL; -typedef union RLC_SERDES_RD_MASTER_INDEX regRLC_SERDES_RD_MASTER_INDEX; -typedef union RLC_SERDES_RD_DATA_0 regRLC_SERDES_RD_DATA_0; -typedef union RLC_SERDES_RD_DATA_1 regRLC_SERDES_RD_DATA_1; -typedef union RLC_SERDES_RD_DATA_2 regRLC_SERDES_RD_DATA_2; -typedef union RLC_SERDES_WR_CU_MASTER_MASK regRLC_SERDES_WR_CU_MASTER_MASK; -typedef union RLC_SERDES_WR_NONCU_MASTER_MASK regRLC_SERDES_WR_NONCU_MASTER_MASK; -typedef union RLC_SERDES_WR_NONCU_MASTER_MASK_1 regRLC_SERDES_WR_NONCU_MASTER_MASK_1; -typedef union RLC_SERDES_NONCU_MASTER_BUSY_1 regRLC_SERDES_NONCU_MASTER_BUSY_1; -typedef union RLC_SERDES_WR_CTRL regRLC_SERDES_WR_CTRL; -typedef union RLC_SERDES_WR_DATA regRLC_SERDES_WR_DATA; -typedef union RLC_SERDES_CU_MASTER_BUSY regRLC_SERDES_CU_MASTER_BUSY; -typedef union RLC_SERDES_NONCU_MASTER_BUSY regRLC_SERDES_NONCU_MASTER_BUSY; -typedef union RLC_GPM_GENERAL_0 regRLC_GPM_GENERAL_0; -typedef union RLC_GPM_GENERAL_1 regRLC_GPM_GENERAL_1; -typedef union RLC_GPM_GENERAL_2 regRLC_GPM_GENERAL_2; -typedef union RLC_GPM_GENERAL_3 regRLC_GPM_GENERAL_3; -typedef union RLC_GPM_GENERAL_4 regRLC_GPM_GENERAL_4; -typedef union RLC_GPM_GENERAL_5 regRLC_GPM_GENERAL_5; -typedef union RLC_GPM_GENERAL_6 regRLC_GPM_GENERAL_6; -typedef union RLC_GPM_GENERAL_7 regRLC_GPM_GENERAL_7; -typedef union RLC_GPM_SCRATCH_ADDR regRLC_GPM_SCRATCH_ADDR; -typedef union RLC_GPM_SCRATCH_DATA regRLC_GPM_SCRATCH_DATA; -typedef union RLC_STATIC_PG_STATUS regRLC_STATIC_PG_STATUS; -typedef union RLC_GPR_REG1 regRLC_GPR_REG1; -typedef union RLC_GPR_REG2 regRLC_GPR_REG2; -typedef union RLC_MGCG_CTRL regRLC_MGCG_CTRL; -typedef union RLC_GPM_THREAD_RESET regRLC_GPM_THREAD_RESET; -typedef union RLC_GPM_CP_DMA_COMPLETE_T0 regRLC_GPM_CP_DMA_COMPLETE_T0; -typedef union RLC_GPM_CP_DMA_COMPLETE_T1 regRLC_GPM_CP_DMA_COMPLETE_T1; -typedef union RLC_FIREWALL_VIOLATION regRLC_FIREWALL_VIOLATION; -typedef union RLC_SPM_MC_CNTL regRLC_SPM_MC_CNTL; -typedef union RLC_SPM_INT_CNTL regRLC_SPM_INT_CNTL; -typedef union RLC_SPM_INT_STATUS regRLC_SPM_INT_STATUS; -typedef union RLC_SPM_DEBUG_SELECT regRLC_SPM_DEBUG_SELECT; -typedef union RLC_SPM_DEBUG regRLC_SPM_DEBUG; -typedef union RLC_SMU_MESSAGE regRLC_SMU_MESSAGE; -typedef union RLC_GPM_LOG_SIZE regRLC_GPM_LOG_SIZE; -typedef union RLC_GPM_LOG_CONT regRLC_GPM_LOG_CONT; -typedef union RLC_PG_DELAY_3 regRLC_PG_DELAY_3; -typedef union RLC_GPM_INT_DISABLE_TH0 regRLC_GPM_INT_DISABLE_TH0; -typedef union RLC_GPM_INT_DISABLE_TH1 regRLC_GPM_INT_DISABLE_TH1; -typedef union RLC_GPM_INT_FORCE_TH0 regRLC_GPM_INT_FORCE_TH0; -typedef union RLC_GPM_INT_FORCE_TH1 regRLC_GPM_INT_FORCE_TH1; -typedef union RLC_SRM_CNTL regRLC_SRM_CNTL; -typedef union RLC_SRM_DEBUG_SELECT regRLC_SRM_DEBUG_SELECT; -typedef union RLC_SRM_DEBUG regRLC_SRM_DEBUG; -typedef union RLC_SRM_ARAM_ADDR regRLC_SRM_ARAM_ADDR; -typedef union RLC_SRM_ARAM_DATA regRLC_SRM_ARAM_DATA; -typedef union RLC_SRM_DRAM_ADDR regRLC_SRM_DRAM_ADDR; -typedef union RLC_SRM_DRAM_DATA regRLC_SRM_DRAM_DATA; -typedef union RLC_SRM_GPM_COMMAND regRLC_SRM_GPM_COMMAND; -typedef union RLC_SRM_GPM_COMMAND_STATUS regRLC_SRM_GPM_COMMAND_STATUS; -typedef union RLC_SRM_RLCV_COMMAND regRLC_SRM_RLCV_COMMAND; -typedef union RLC_SRM_RLCV_COMMAND_STATUS regRLC_SRM_RLCV_COMMAND_STATUS; -typedef union RLC_SRM_INDEX_CNTL_ADDR_0 regRLC_SRM_INDEX_CNTL_ADDR_0; -typedef union RLC_SRM_INDEX_CNTL_ADDR_1 regRLC_SRM_INDEX_CNTL_ADDR_1; -typedef union RLC_SRM_INDEX_CNTL_ADDR_2 regRLC_SRM_INDEX_CNTL_ADDR_2; -typedef union RLC_SRM_INDEX_CNTL_ADDR_3 regRLC_SRM_INDEX_CNTL_ADDR_3; -typedef union RLC_SRM_INDEX_CNTL_ADDR_4 regRLC_SRM_INDEX_CNTL_ADDR_4; -typedef union RLC_SRM_INDEX_CNTL_ADDR_5 regRLC_SRM_INDEX_CNTL_ADDR_5; -typedef union RLC_SRM_INDEX_CNTL_ADDR_6 regRLC_SRM_INDEX_CNTL_ADDR_6; -typedef union RLC_SRM_INDEX_CNTL_ADDR_7 regRLC_SRM_INDEX_CNTL_ADDR_7; -typedef union RLC_SRM_INDEX_CNTL_DATA_0 regRLC_SRM_INDEX_CNTL_DATA_0; -typedef union RLC_SRM_INDEX_CNTL_DATA_1 regRLC_SRM_INDEX_CNTL_DATA_1; -typedef union RLC_SRM_INDEX_CNTL_DATA_2 regRLC_SRM_INDEX_CNTL_DATA_2; -typedef union RLC_SRM_INDEX_CNTL_DATA_3 regRLC_SRM_INDEX_CNTL_DATA_3; -typedef union RLC_SRM_INDEX_CNTL_DATA_4 regRLC_SRM_INDEX_CNTL_DATA_4; -typedef union RLC_SRM_INDEX_CNTL_DATA_5 regRLC_SRM_INDEX_CNTL_DATA_5; -typedef union RLC_SRM_INDEX_CNTL_DATA_6 regRLC_SRM_INDEX_CNTL_DATA_6; -typedef union RLC_SRM_INDEX_CNTL_DATA_7 regRLC_SRM_INDEX_CNTL_DATA_7; -typedef union RLC_SRM_STAT regRLC_SRM_STAT; -typedef union RLC_SRM_GPM_ABORT regRLC_SRM_GPM_ABORT; -typedef union RLC_CSIB_ADDR_LO regRLC_CSIB_ADDR_LO; -typedef union RLC_CSIB_ADDR_HI regRLC_CSIB_ADDR_HI; -typedef union RLC_CSIB_LENGTH regRLC_CSIB_LENGTH; -typedef union RLC_SMU_COMMAND regRLC_SMU_COMMAND; -typedef union RLC_CP_SCHEDULERS regRLC_CP_SCHEDULERS; -typedef union RLC_SMU_ARGUMENT_1 regRLC_SMU_ARGUMENT_1; -typedef union RLC_SMU_ARGUMENT_2 regRLC_SMU_ARGUMENT_2; -typedef union RLC_GPM_GENERAL_8 regRLC_GPM_GENERAL_8; -typedef union RLC_GPM_GENERAL_9 regRLC_GPM_GENERAL_9; -typedef union RLC_GPM_GENERAL_10 regRLC_GPM_GENERAL_10; -typedef union RLC_GPM_GENERAL_11 regRLC_GPM_GENERAL_11; -typedef union RLC_GPM_GENERAL_12 regRLC_GPM_GENERAL_12; -typedef union RLC_UTCL2_CNTL regRLC_UTCL2_CNTL; -typedef union RLC_GPM_UTCL1_CNTL_0 regRLC_GPM_UTCL1_CNTL_0; -typedef union RLC_GPM_UTCL1_CNTL_1 regRLC_GPM_UTCL1_CNTL_1; -typedef union RLC_GPM_UTCL1_CNTL_2 regRLC_GPM_UTCL1_CNTL_2; -typedef union RLC_SPM_UTCL1_CNTL regRLC_SPM_UTCL1_CNTL; -typedef union RLC_PREWALKER_UTCL1_CNTL regRLC_PREWALKER_UTCL1_CNTL; -typedef union RLC_PREWALKER_UTCL1_TRIG regRLC_PREWALKER_UTCL1_TRIG; -typedef union RLC_PREWALKER_UTCL1_ADDR_LSB regRLC_PREWALKER_UTCL1_ADDR_LSB; -typedef union RLC_PREWALKER_UTCL1_ADDR_MSB regRLC_PREWALKER_UTCL1_ADDR_MSB; -typedef union RLC_PREWALKER_UTCL1_SIZE_LSB regRLC_PREWALKER_UTCL1_SIZE_LSB; -typedef union RLC_PREWALKER_UTCL1_SIZE_MSB regRLC_PREWALKER_UTCL1_SIZE_MSB; -typedef union RLC_DSM_TRIG regRLC_DSM_TRIG; -typedef union RLC_UTCL1_STATUS_2 regRLC_UTCL1_STATUS_2; -typedef union RLC_SPM_UTCL1_ERROR_1 regRLC_SPM_UTCL1_ERROR_1; -typedef union RLC_SPM_UTCL1_ERROR_2 regRLC_SPM_UTCL1_ERROR_2; -typedef union RLC_GPM_UTCL1_TH0_ERROR_1 regRLC_GPM_UTCL1_TH0_ERROR_1; -typedef union RLC_GPM_UTCL1_TH0_ERROR_2 regRLC_GPM_UTCL1_TH0_ERROR_2; -typedef union RLC_GPM_UTCL1_TH1_ERROR_1 regRLC_GPM_UTCL1_TH1_ERROR_1; -typedef union RLC_GPM_UTCL1_TH1_ERROR_2 regRLC_GPM_UTCL1_TH1_ERROR_2; -typedef union RLC_GPM_UTCL1_TH2_ERROR_1 regRLC_GPM_UTCL1_TH2_ERROR_1; -typedef union RLC_GPM_UTCL1_TH2_ERROR_2 regRLC_GPM_UTCL1_TH2_ERROR_2; -typedef union RLC_CP_EOF_INT regRLC_CP_EOF_INT; -typedef union RLC_CP_EOF_INT_CNT regRLC_CP_EOF_INT_CNT; -typedef union RLC_R2I_CNTL_0 regRLC_R2I_CNTL_0; -typedef union RLC_R2I_CNTL_1 regRLC_R2I_CNTL_1; -typedef union RLC_R2I_CNTL_2 regRLC_R2I_CNTL_2; -typedef union RLC_R2I_CNTL_3 regRLC_R2I_CNTL_3; -typedef union RLC_SPARE_INT regRLC_SPARE_INT; -typedef union RLC_UTCL1_STATUS regRLC_UTCL1_STATUS; -typedef union RLC_LBPW_CU_STAT regRLC_LBPW_CU_STAT; -typedef union RLC_DS_CNTL regRLC_DS_CNTL; -typedef union CGTT_RLC_CLK_CTRL regCGTT_RLC_CLK_CTRL; -typedef union RLC_GFX_RM_CNTL regRLC_GFX_RM_CNTL; -typedef union RLC_CLK_CNTL regRLC_CLK_CNTL; -typedef union RLC_GPM_UCODE_ADDR regRLC_GPM_UCODE_ADDR; -typedef union RLC_GPM_UCODE_DATA regRLC_GPM_UCODE_DATA; -typedef union RLC_GC_FUSESTRAP_RELOAD regRLC_GC_FUSESTRAP_RELOAD; -typedef union RLC_GC_FUSESTRAP_GC_WRITE_DISABLE regRLC_GC_FUSESTRAP_GC_WRITE_DISABLE; -typedef union RLC_GC_FUSESTRAP_CC_WRITE_DISABLE regRLC_GC_FUSESTRAP_CC_WRITE_DISABLE; -typedef union RLC_GC_FUSESTRAP_DEBE_0 regRLC_GC_FUSESTRAP_DEBE_0; -typedef union RLC_GC_FUSESTRAP_DEBE_1 regRLC_GC_FUSESTRAP_DEBE_1; -typedef union RLC_GC_FUSESTRAP_DEBE_2 regRLC_GC_FUSESTRAP_DEBE_2; -typedef union RLC_GC_FUSESTRAP_DEBE_3 regRLC_GC_FUSESTRAP_DEBE_3; -typedef union RLC_GC_FUSESTRAP_DPFP_RATE regRLC_GC_FUSESTRAP_DPFP_RATE; -typedef union RLC_GC_FUSESTRAP_DISABLE_EDC regRLC_GC_FUSESTRAP_DISABLE_EDC; -typedef union RLC_HYP_SEMAPHORE_2 regRLC_HYP_SEMAPHORE_2; -typedef union RLC_HYP_SEMAPHORE_3 regRLC_HYP_SEMAPHORE_3; -typedef union RLC_GPU_IOV_VF_ENABLE regRLC_GPU_IOV_VF_ENABLE; -typedef union RLC_GPU_IOV_CFG_REG1 regRLC_GPU_IOV_CFG_REG1; -typedef union RLC_GPU_IOV_CFG_REG2 regRLC_GPU_IOV_CFG_REG2; -typedef union RLC_GPU_IOV_SCH_BLOCK regRLC_GPU_IOV_SCH_BLOCK; -typedef union RLC_GPU_IOV_CFG_REG6 regRLC_GPU_IOV_CFG_REG6; -typedef union RLC_GPU_IOV_CFG_REG8 regRLC_GPU_IOV_CFG_REG8; -typedef union RLC_GPU_IOV_UCODE_ADDR regRLC_GPU_IOV_UCODE_ADDR; -typedef union RLC_GPU_IOV_UCODE_DATA regRLC_GPU_IOV_UCODE_DATA; -typedef union RLC_GPU_IOV_SCRATCH_ADDR regRLC_GPU_IOV_SCRATCH_ADDR; -typedef union RLC_GPU_IOV_SCRATCH_DATA regRLC_GPU_IOV_SCRATCH_DATA; -typedef union RLC_GPU_IOV_F32_CNTL regRLC_GPU_IOV_F32_CNTL; -typedef union RLC_GPU_IOV_F32_RESET regRLC_GPU_IOV_F32_RESET; -typedef union RLC_GPU_IOV_SDMA0_STATUS regRLC_GPU_IOV_SDMA0_STATUS; -typedef union RLC_GPU_IOV_SDMA1_STATUS regRLC_GPU_IOV_SDMA1_STATUS; -typedef union RLC_GPU_IOV_SMU_RESPONSE regRLC_GPU_IOV_SMU_RESPONSE; -typedef union RLC_GPU_IOV_VIRT_RESET_REQ regRLC_GPU_IOV_VIRT_RESET_REQ; -typedef union RLC_GPU_IOV_SDMA0_BUSY_STATUS regRLC_GPU_IOV_SDMA0_BUSY_STATUS; -typedef union RLC_GPU_IOV_SDMA1_BUSY_STATUS regRLC_GPU_IOV_SDMA1_BUSY_STATUS; -typedef union RLC_GPU_IOV_VM_BUSY_STATUS regRLC_GPU_IOV_VM_BUSY_STATUS; -typedef union RLC_GPU_IOV_SCH_0 regRLC_GPU_IOV_SCH_0; -typedef union RLC_GPU_IOV_SCH_1 regRLC_GPU_IOV_SCH_1; -typedef union RLC_GPU_IOV_SCH_2 regRLC_GPU_IOV_SCH_2; -typedef union RLC_GPU_IOV_SCH_3 regRLC_GPU_IOV_SCH_3; -typedef union RLC_GPU_IOV_RLC_RESPONSE regRLC_GPU_IOV_RLC_RESPONSE; -typedef union RLC_GPU_IOV_ACTIVE_FCN_ID regRLC_GPU_IOV_ACTIVE_FCN_ID; -typedef union RLC_RLCV_TIMER_INT_0 regRLC_RLCV_TIMER_INT_0; -typedef union RLC_RLCV_TIMER_CTRL regRLC_RLCV_TIMER_CTRL; -typedef union RLC_RLCV_TIMER_STAT regRLC_RLCV_TIMER_STAT; -typedef union RLC_GPU_IOV_INT_DISABLE regRLC_GPU_IOV_INT_DISABLE; -typedef union RLC_GPU_IOV_INT_FORCE regRLC_GPU_IOV_INT_FORCE; -typedef union RLC_GPU_IOV_VF_DOORBELL_STATUS regRLC_GPU_IOV_VF_DOORBELL_STATUS; -typedef union RLC_GPU_IOV_VF_DOORBELL_STATUS_SET regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET; -typedef union RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR; -typedef union RLC_GPU_IOV_VF_MASK regRLC_GPU_IOV_VF_MASK; -typedef union RLC_REG_PRIV_LEVEL_A regRLC_REG_PRIV_LEVEL_A; -typedef union RLC_REG_PRIV_LEVEL_B regRLC_REG_PRIV_LEVEL_B; -typedef union RLC_REG_PRIV_LEVEL_C regRLC_REG_PRIV_LEVEL_C; -typedef union RLC_REG_PRIV_LEVEL_D regRLC_REG_PRIV_LEVEL_D; -typedef union RLC_REG_PRIV_LEVEL_E regRLC_REG_PRIV_LEVEL_E; -typedef union RLC_REG_PRIV_LEVEL_F regRLC_REG_PRIV_LEVEL_F; -typedef union RLC_REG_PRIV_LEVEL_G regRLC_REG_PRIV_LEVEL_G; -typedef union RLC_REG_PRIV_LEVEL_H regRLC_REG_PRIV_LEVEL_H; -typedef union RLC_REG_PRIV_LEVEL_I regRLC_REG_PRIV_LEVEL_I; -typedef union RLC_REG_PRIV_LEVEL_J regRLC_REG_PRIV_LEVEL_J; -typedef union RLC_REG_PRIV_LEVEL_K regRLC_REG_PRIV_LEVEL_K; -typedef union RLC_REG_PRIV_LEVEL_L regRLC_REG_PRIV_LEVEL_L; -typedef union RLC_REG_PRIV_LEVEL_M regRLC_REG_PRIV_LEVEL_M; -typedef union RLC_REG_PRIV_LEVEL_N regRLC_REG_PRIV_LEVEL_N; -typedef union RLC_REG_PRIV_LEVEL_O regRLC_REG_PRIV_LEVEL_O; -typedef union RLC_REG_PRIV_LEVEL_P regRLC_REG_PRIV_LEVEL_P; -typedef union RLC_REG_SEC_INT_STATUS regRLC_REG_SEC_INT_STATUS; -typedef union RLC_FWL_FIRST_VIOL_ADDR regRLC_FWL_FIRST_VIOL_ADDR; -typedef union SPI_PS_MAX_WAVE_ID regSPI_PS_MAX_WAVE_ID; -typedef union SPI_START_PHASE regSPI_START_PHASE; -typedef union SPI_GFX_CNTL regSPI_GFX_CNTL; -typedef union SPI_DEBUG_CNTL regSPI_DEBUG_CNTL; -typedef union SPI_DEBUG_READ regSPI_DEBUG_READ; -typedef union SPI_DSM_CNTL regSPI_DSM_CNTL; -typedef union SPI_DSM_CNTL2 regSPI_DSM_CNTL2; -typedef union SPI_EDC_CNT regSPI_EDC_CNT; -typedef union SPI_DEBUG_BUSY regSPI_DEBUG_BUSY; -typedef union SPI_CONFIG_PS_CU_EN regSPI_CONFIG_PS_CU_EN; -typedef union SPI_WF_LIFETIME_CNTL regSPI_WF_LIFETIME_CNTL; -typedef union SPI_WF_LIFETIME_LIMIT_0 regSPI_WF_LIFETIME_LIMIT_0; -typedef union SPI_WF_LIFETIME_LIMIT_1 regSPI_WF_LIFETIME_LIMIT_1; -typedef union SPI_WF_LIFETIME_LIMIT_2 regSPI_WF_LIFETIME_LIMIT_2; -typedef union SPI_WF_LIFETIME_LIMIT_3 regSPI_WF_LIFETIME_LIMIT_3; -typedef union SPI_WF_LIFETIME_LIMIT_4 regSPI_WF_LIFETIME_LIMIT_4; -typedef union SPI_WF_LIFETIME_LIMIT_5 regSPI_WF_LIFETIME_LIMIT_5; -typedef union SPI_WF_LIFETIME_LIMIT_6 regSPI_WF_LIFETIME_LIMIT_6; -typedef union SPI_WF_LIFETIME_LIMIT_7 regSPI_WF_LIFETIME_LIMIT_7; -typedef union SPI_WF_LIFETIME_LIMIT_8 regSPI_WF_LIFETIME_LIMIT_8; -typedef union SPI_WF_LIFETIME_LIMIT_9 regSPI_WF_LIFETIME_LIMIT_9; -typedef union SPI_WF_LIFETIME_STATUS_0 regSPI_WF_LIFETIME_STATUS_0; -typedef union SPI_WF_LIFETIME_STATUS_1 regSPI_WF_LIFETIME_STATUS_1; -typedef union SPI_WF_LIFETIME_STATUS_2 regSPI_WF_LIFETIME_STATUS_2; -typedef union SPI_WF_LIFETIME_STATUS_3 regSPI_WF_LIFETIME_STATUS_3; -typedef union SPI_WF_LIFETIME_STATUS_4 regSPI_WF_LIFETIME_STATUS_4; -typedef union SPI_WF_LIFETIME_STATUS_5 regSPI_WF_LIFETIME_STATUS_5; -typedef union SPI_WF_LIFETIME_STATUS_6 regSPI_WF_LIFETIME_STATUS_6; -typedef union SPI_WF_LIFETIME_STATUS_7 regSPI_WF_LIFETIME_STATUS_7; -typedef union SPI_WF_LIFETIME_STATUS_8 regSPI_WF_LIFETIME_STATUS_8; -typedef union SPI_WF_LIFETIME_STATUS_9 regSPI_WF_LIFETIME_STATUS_9; -typedef union SPI_WF_LIFETIME_STATUS_10 regSPI_WF_LIFETIME_STATUS_10; -typedef union SPI_WF_LIFETIME_STATUS_11 regSPI_WF_LIFETIME_STATUS_11; -typedef union SPI_WF_LIFETIME_STATUS_12 regSPI_WF_LIFETIME_STATUS_12; -typedef union SPI_WF_LIFETIME_STATUS_13 regSPI_WF_LIFETIME_STATUS_13; -typedef union SPI_WF_LIFETIME_STATUS_14 regSPI_WF_LIFETIME_STATUS_14; -typedef union SPI_WF_LIFETIME_STATUS_15 regSPI_WF_LIFETIME_STATUS_15; -typedef union SPI_WF_LIFETIME_STATUS_16 regSPI_WF_LIFETIME_STATUS_16; -typedef union SPI_WF_LIFETIME_STATUS_17 regSPI_WF_LIFETIME_STATUS_17; -typedef union SPI_WF_LIFETIME_STATUS_18 regSPI_WF_LIFETIME_STATUS_18; -typedef union SPI_WF_LIFETIME_STATUS_19 regSPI_WF_LIFETIME_STATUS_19; -typedef union SPI_WF_LIFETIME_STATUS_20 regSPI_WF_LIFETIME_STATUS_20; -typedef union SPI_WF_LIFETIME_DEBUG regSPI_WF_LIFETIME_DEBUG; -typedef union SPI_SLAVE_DEBUG_BUSY regSPI_SLAVE_DEBUG_BUSY; -typedef union SPI_LB_CTR_CTRL regSPI_LB_CTR_CTRL; -typedef union SPI_LB_CU_MASK regSPI_LB_CU_MASK; -typedef union SPI_LB_DATA_REG regSPI_LB_DATA_REG; -typedef union SPI_PG_ENABLE_STATIC_CU_MASK regSPI_PG_ENABLE_STATIC_CU_MASK; -typedef union SPI_GDS_CREDITS regSPI_GDS_CREDITS; -typedef union SPI_SX_EXPORT_BUFFER_SIZES regSPI_SX_EXPORT_BUFFER_SIZES; -typedef union SPI_SX_SCOREBOARD_BUFFER_SIZES regSPI_SX_SCOREBOARD_BUFFER_SIZES; -typedef union SPI_CSQ_WF_ACTIVE_STATUS regSPI_CSQ_WF_ACTIVE_STATUS; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_0 regSPI_CSQ_WF_ACTIVE_COUNT_0; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_1 regSPI_CSQ_WF_ACTIVE_COUNT_1; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_2 regSPI_CSQ_WF_ACTIVE_COUNT_2; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_3 regSPI_CSQ_WF_ACTIVE_COUNT_3; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_4 regSPI_CSQ_WF_ACTIVE_COUNT_4; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_5 regSPI_CSQ_WF_ACTIVE_COUNT_5; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_6 regSPI_CSQ_WF_ACTIVE_COUNT_6; -typedef union SPI_CSQ_WF_ACTIVE_COUNT_7 regSPI_CSQ_WF_ACTIVE_COUNT_7; -typedef union SPI_LB_DATA_WAVES regSPI_LB_DATA_WAVES; -typedef union SPI_LB_DATA_PERCU_WAVE_HSGS regSPI_LB_DATA_PERCU_WAVE_HSGS; -typedef union SPI_LB_DATA_PERCU_WAVE_VSPS regSPI_LB_DATA_PERCU_WAVE_VSPS; -typedef union SPI_LB_DATA_PERCU_WAVE_CS regSPI_LB_DATA_PERCU_WAVE_CS; -typedef union SPIS_DEBUG_READ regSPIS_DEBUG_READ; -typedef union BCI_DEBUG_READ regBCI_DEBUG_READ; -typedef union SPI_P0_TRAP_SCREEN_PSBA_LO regSPI_P0_TRAP_SCREEN_PSBA_LO; -typedef union SPI_P0_TRAP_SCREEN_PSBA_HI regSPI_P0_TRAP_SCREEN_PSBA_HI; -typedef union SPI_P0_TRAP_SCREEN_PSMA_LO regSPI_P0_TRAP_SCREEN_PSMA_LO; -typedef union SPI_P0_TRAP_SCREEN_PSMA_HI regSPI_P0_TRAP_SCREEN_PSMA_HI; -typedef union SPI_P0_TRAP_SCREEN_GPR_MIN regSPI_P0_TRAP_SCREEN_GPR_MIN; -typedef union SPI_P1_TRAP_SCREEN_PSBA_LO regSPI_P1_TRAP_SCREEN_PSBA_LO; -typedef union SPI_P1_TRAP_SCREEN_PSBA_HI regSPI_P1_TRAP_SCREEN_PSBA_HI; -typedef union SPI_P1_TRAP_SCREEN_PSMA_LO regSPI_P1_TRAP_SCREEN_PSMA_LO; -typedef union SPI_P1_TRAP_SCREEN_PSMA_HI regSPI_P1_TRAP_SCREEN_PSMA_HI; -typedef union SPI_P1_TRAP_SCREEN_GPR_MIN regSPI_P1_TRAP_SCREEN_GPR_MIN; -typedef union SPI_SHADER_PGM_LO_PS regSPI_SHADER_PGM_LO_PS; -typedef union SPI_SHADER_PGM_HI_PS regSPI_SHADER_PGM_HI_PS; -typedef union SPI_SHADER_PGM_RSRC1_PS regSPI_SHADER_PGM_RSRC1_PS; -typedef union SPI_SHADER_PGM_RSRC2_PS regSPI_SHADER_PGM_RSRC2_PS; -typedef union SPI_SHADER_PGM_RSRC3_PS regSPI_SHADER_PGM_RSRC3_PS; -typedef union SPI_SHADER_USER_DATA_PS_0 regSPI_SHADER_USER_DATA_PS_0; -typedef union SPI_SHADER_USER_DATA_PS_1 regSPI_SHADER_USER_DATA_PS_1; -typedef union SPI_SHADER_USER_DATA_PS_2 regSPI_SHADER_USER_DATA_PS_2; -typedef union SPI_SHADER_USER_DATA_PS_3 regSPI_SHADER_USER_DATA_PS_3; -typedef union SPI_SHADER_USER_DATA_PS_4 regSPI_SHADER_USER_DATA_PS_4; -typedef union SPI_SHADER_USER_DATA_PS_5 regSPI_SHADER_USER_DATA_PS_5; -typedef union SPI_SHADER_USER_DATA_PS_6 regSPI_SHADER_USER_DATA_PS_6; -typedef union SPI_SHADER_USER_DATA_PS_7 regSPI_SHADER_USER_DATA_PS_7; -typedef union SPI_SHADER_USER_DATA_PS_8 regSPI_SHADER_USER_DATA_PS_8; -typedef union SPI_SHADER_USER_DATA_PS_9 regSPI_SHADER_USER_DATA_PS_9; -typedef union SPI_SHADER_USER_DATA_PS_10 regSPI_SHADER_USER_DATA_PS_10; -typedef union SPI_SHADER_USER_DATA_PS_11 regSPI_SHADER_USER_DATA_PS_11; -typedef union SPI_SHADER_USER_DATA_PS_12 regSPI_SHADER_USER_DATA_PS_12; -typedef union SPI_SHADER_USER_DATA_PS_13 regSPI_SHADER_USER_DATA_PS_13; -typedef union SPI_SHADER_USER_DATA_PS_14 regSPI_SHADER_USER_DATA_PS_14; -typedef union SPI_SHADER_USER_DATA_PS_15 regSPI_SHADER_USER_DATA_PS_15; -typedef union SPI_SHADER_USER_DATA_PS_16 regSPI_SHADER_USER_DATA_PS_16; -typedef union SPI_SHADER_USER_DATA_PS_17 regSPI_SHADER_USER_DATA_PS_17; -typedef union SPI_SHADER_USER_DATA_PS_18 regSPI_SHADER_USER_DATA_PS_18; -typedef union SPI_SHADER_USER_DATA_PS_19 regSPI_SHADER_USER_DATA_PS_19; -typedef union SPI_SHADER_USER_DATA_PS_20 regSPI_SHADER_USER_DATA_PS_20; -typedef union SPI_SHADER_USER_DATA_PS_21 regSPI_SHADER_USER_DATA_PS_21; -typedef union SPI_SHADER_USER_DATA_PS_22 regSPI_SHADER_USER_DATA_PS_22; -typedef union SPI_SHADER_USER_DATA_PS_23 regSPI_SHADER_USER_DATA_PS_23; -typedef union SPI_SHADER_USER_DATA_PS_24 regSPI_SHADER_USER_DATA_PS_24; -typedef union SPI_SHADER_USER_DATA_PS_25 regSPI_SHADER_USER_DATA_PS_25; -typedef union SPI_SHADER_USER_DATA_PS_26 regSPI_SHADER_USER_DATA_PS_26; -typedef union SPI_SHADER_USER_DATA_PS_27 regSPI_SHADER_USER_DATA_PS_27; -typedef union SPI_SHADER_USER_DATA_PS_28 regSPI_SHADER_USER_DATA_PS_28; -typedef union SPI_SHADER_USER_DATA_PS_29 regSPI_SHADER_USER_DATA_PS_29; -typedef union SPI_SHADER_USER_DATA_PS_30 regSPI_SHADER_USER_DATA_PS_30; -typedef union SPI_SHADER_USER_DATA_PS_31 regSPI_SHADER_USER_DATA_PS_31; -typedef union SPI_SHADER_PGM_LO_VS regSPI_SHADER_PGM_LO_VS; -typedef union SPI_SHADER_PGM_HI_VS regSPI_SHADER_PGM_HI_VS; -typedef union SPI_SHADER_PGM_RSRC1_VS regSPI_SHADER_PGM_RSRC1_VS; -typedef union SPI_SHADER_PGM_RSRC2_VS regSPI_SHADER_PGM_RSRC2_VS; -typedef union SPI_SHADER_PGM_RSRC3_VS regSPI_SHADER_PGM_RSRC3_VS; -typedef union SPI_SHADER_LATE_ALLOC_VS regSPI_SHADER_LATE_ALLOC_VS; -typedef union SPI_SHADER_USER_DATA_VS_0 regSPI_SHADER_USER_DATA_VS_0; -typedef union SPI_SHADER_USER_DATA_VS_1 regSPI_SHADER_USER_DATA_VS_1; -typedef union SPI_SHADER_USER_DATA_VS_2 regSPI_SHADER_USER_DATA_VS_2; -typedef union SPI_SHADER_USER_DATA_VS_3 regSPI_SHADER_USER_DATA_VS_3; -typedef union SPI_SHADER_USER_DATA_VS_4 regSPI_SHADER_USER_DATA_VS_4; -typedef union SPI_SHADER_USER_DATA_VS_5 regSPI_SHADER_USER_DATA_VS_5; -typedef union SPI_SHADER_USER_DATA_VS_6 regSPI_SHADER_USER_DATA_VS_6; -typedef union SPI_SHADER_USER_DATA_VS_7 regSPI_SHADER_USER_DATA_VS_7; -typedef union SPI_SHADER_USER_DATA_VS_8 regSPI_SHADER_USER_DATA_VS_8; -typedef union SPI_SHADER_USER_DATA_VS_9 regSPI_SHADER_USER_DATA_VS_9; -typedef union SPI_SHADER_USER_DATA_VS_10 regSPI_SHADER_USER_DATA_VS_10; -typedef union SPI_SHADER_USER_DATA_VS_11 regSPI_SHADER_USER_DATA_VS_11; -typedef union SPI_SHADER_USER_DATA_VS_12 regSPI_SHADER_USER_DATA_VS_12; -typedef union SPI_SHADER_USER_DATA_VS_13 regSPI_SHADER_USER_DATA_VS_13; -typedef union SPI_SHADER_USER_DATA_VS_14 regSPI_SHADER_USER_DATA_VS_14; -typedef union SPI_SHADER_USER_DATA_VS_15 regSPI_SHADER_USER_DATA_VS_15; -typedef union SPI_SHADER_USER_DATA_VS_16 regSPI_SHADER_USER_DATA_VS_16; -typedef union SPI_SHADER_USER_DATA_VS_17 regSPI_SHADER_USER_DATA_VS_17; -typedef union SPI_SHADER_USER_DATA_VS_18 regSPI_SHADER_USER_DATA_VS_18; -typedef union SPI_SHADER_USER_DATA_VS_19 regSPI_SHADER_USER_DATA_VS_19; -typedef union SPI_SHADER_USER_DATA_VS_20 regSPI_SHADER_USER_DATA_VS_20; -typedef union SPI_SHADER_USER_DATA_VS_21 regSPI_SHADER_USER_DATA_VS_21; -typedef union SPI_SHADER_USER_DATA_VS_22 regSPI_SHADER_USER_DATA_VS_22; -typedef union SPI_SHADER_USER_DATA_VS_23 regSPI_SHADER_USER_DATA_VS_23; -typedef union SPI_SHADER_USER_DATA_VS_24 regSPI_SHADER_USER_DATA_VS_24; -typedef union SPI_SHADER_USER_DATA_VS_25 regSPI_SHADER_USER_DATA_VS_25; -typedef union SPI_SHADER_USER_DATA_VS_26 regSPI_SHADER_USER_DATA_VS_26; -typedef union SPI_SHADER_USER_DATA_VS_27 regSPI_SHADER_USER_DATA_VS_27; -typedef union SPI_SHADER_USER_DATA_VS_28 regSPI_SHADER_USER_DATA_VS_28; -typedef union SPI_SHADER_USER_DATA_VS_29 regSPI_SHADER_USER_DATA_VS_29; -typedef union SPI_SHADER_USER_DATA_VS_30 regSPI_SHADER_USER_DATA_VS_30; -typedef union SPI_SHADER_USER_DATA_VS_31 regSPI_SHADER_USER_DATA_VS_31; -typedef union SPI_SHADER_PGM_RSRC2_GS_VS regSPI_SHADER_PGM_RSRC2_GS_VS; -typedef union SPI_SHADER_USER_DATA_ADDR_LO_GS regSPI_SHADER_USER_DATA_ADDR_LO_GS; -typedef union SPI_SHADER_USER_DATA_ADDR_HI_GS regSPI_SHADER_USER_DATA_ADDR_HI_GS; -typedef union SPI_SHADER_PGM_LO_GS regSPI_SHADER_PGM_LO_GS; -typedef union SPI_SHADER_PGM_HI_GS regSPI_SHADER_PGM_HI_GS; -typedef union SPI_SHADER_PGM_LO_ES regSPI_SHADER_PGM_LO_ES; -typedef union SPI_SHADER_PGM_HI_ES regSPI_SHADER_PGM_HI_ES; -typedef union SPI_SHADER_PGM_RSRC1_GS regSPI_SHADER_PGM_RSRC1_GS; -typedef union SPI_SHADER_PGM_RSRC2_GS regSPI_SHADER_PGM_RSRC2_GS; -typedef union SPI_SHADER_PGM_RSRC3_GS regSPI_SHADER_PGM_RSRC3_GS; -typedef union SPI_SHADER_PGM_RSRC4_GS regSPI_SHADER_PGM_RSRC4_GS; -typedef union SPI_SHADER_USER_DATA_ES_0 regSPI_SHADER_USER_DATA_ES_0; -typedef union SPI_SHADER_USER_DATA_ES_1 regSPI_SHADER_USER_DATA_ES_1; -typedef union SPI_SHADER_USER_DATA_ES_2 regSPI_SHADER_USER_DATA_ES_2; -typedef union SPI_SHADER_USER_DATA_ES_3 regSPI_SHADER_USER_DATA_ES_3; -typedef union SPI_SHADER_USER_DATA_ES_4 regSPI_SHADER_USER_DATA_ES_4; -typedef union SPI_SHADER_USER_DATA_ES_5 regSPI_SHADER_USER_DATA_ES_5; -typedef union SPI_SHADER_USER_DATA_ES_6 regSPI_SHADER_USER_DATA_ES_6; -typedef union SPI_SHADER_USER_DATA_ES_7 regSPI_SHADER_USER_DATA_ES_7; -typedef union SPI_SHADER_USER_DATA_ES_8 regSPI_SHADER_USER_DATA_ES_8; -typedef union SPI_SHADER_USER_DATA_ES_9 regSPI_SHADER_USER_DATA_ES_9; -typedef union SPI_SHADER_USER_DATA_ES_10 regSPI_SHADER_USER_DATA_ES_10; -typedef union SPI_SHADER_USER_DATA_ES_11 regSPI_SHADER_USER_DATA_ES_11; -typedef union SPI_SHADER_USER_DATA_ES_12 regSPI_SHADER_USER_DATA_ES_12; -typedef union SPI_SHADER_USER_DATA_ES_13 regSPI_SHADER_USER_DATA_ES_13; -typedef union SPI_SHADER_USER_DATA_ES_14 regSPI_SHADER_USER_DATA_ES_14; -typedef union SPI_SHADER_USER_DATA_ES_15 regSPI_SHADER_USER_DATA_ES_15; -typedef union SPI_SHADER_USER_DATA_ES_16 regSPI_SHADER_USER_DATA_ES_16; -typedef union SPI_SHADER_USER_DATA_ES_17 regSPI_SHADER_USER_DATA_ES_17; -typedef union SPI_SHADER_USER_DATA_ES_18 regSPI_SHADER_USER_DATA_ES_18; -typedef union SPI_SHADER_USER_DATA_ES_19 regSPI_SHADER_USER_DATA_ES_19; -typedef union SPI_SHADER_USER_DATA_ES_20 regSPI_SHADER_USER_DATA_ES_20; -typedef union SPI_SHADER_USER_DATA_ES_21 regSPI_SHADER_USER_DATA_ES_21; -typedef union SPI_SHADER_USER_DATA_ES_22 regSPI_SHADER_USER_DATA_ES_22; -typedef union SPI_SHADER_USER_DATA_ES_23 regSPI_SHADER_USER_DATA_ES_23; -typedef union SPI_SHADER_USER_DATA_ES_24 regSPI_SHADER_USER_DATA_ES_24; -typedef union SPI_SHADER_USER_DATA_ES_25 regSPI_SHADER_USER_DATA_ES_25; -typedef union SPI_SHADER_USER_DATA_ES_26 regSPI_SHADER_USER_DATA_ES_26; -typedef union SPI_SHADER_USER_DATA_ES_27 regSPI_SHADER_USER_DATA_ES_27; -typedef union SPI_SHADER_USER_DATA_ES_28 regSPI_SHADER_USER_DATA_ES_28; -typedef union SPI_SHADER_USER_DATA_ES_29 regSPI_SHADER_USER_DATA_ES_29; -typedef union SPI_SHADER_USER_DATA_ES_30 regSPI_SHADER_USER_DATA_ES_30; -typedef union SPI_SHADER_USER_DATA_ES_31 regSPI_SHADER_USER_DATA_ES_31; -typedef union SPI_SHADER_USER_DATA_ADDR_LO_HS regSPI_SHADER_USER_DATA_ADDR_LO_HS; -typedef union SPI_SHADER_USER_DATA_ADDR_HI_HS regSPI_SHADER_USER_DATA_ADDR_HI_HS; -typedef union SPI_SHADER_PGM_LO_HS regSPI_SHADER_PGM_LO_HS; -typedef union SPI_SHADER_PGM_HI_HS regSPI_SHADER_PGM_HI_HS; -typedef union SPI_SHADER_PGM_LO_LS regSPI_SHADER_PGM_LO_LS; -typedef union SPI_SHADER_PGM_HI_LS regSPI_SHADER_PGM_HI_LS; -typedef union SPI_SHADER_PGM_RSRC1_HS regSPI_SHADER_PGM_RSRC1_HS; -typedef union SPI_SHADER_PGM_RSRC2_HS regSPI_SHADER_PGM_RSRC2_HS; -typedef union SPI_SHADER_PGM_RSRC3_HS regSPI_SHADER_PGM_RSRC3_HS; -typedef union SPI_SHADER_PGM_RSRC4_HS regSPI_SHADER_PGM_RSRC4_HS; -typedef union SPI_SHADER_USER_DATA_LS_0 regSPI_SHADER_USER_DATA_LS_0; -typedef union SPI_SHADER_USER_DATA_LS_1 regSPI_SHADER_USER_DATA_LS_1; -typedef union SPI_SHADER_USER_DATA_LS_2 regSPI_SHADER_USER_DATA_LS_2; -typedef union SPI_SHADER_USER_DATA_LS_3 regSPI_SHADER_USER_DATA_LS_3; -typedef union SPI_SHADER_USER_DATA_LS_4 regSPI_SHADER_USER_DATA_LS_4; -typedef union SPI_SHADER_USER_DATA_LS_5 regSPI_SHADER_USER_DATA_LS_5; -typedef union SPI_SHADER_USER_DATA_LS_6 regSPI_SHADER_USER_DATA_LS_6; -typedef union SPI_SHADER_USER_DATA_LS_7 regSPI_SHADER_USER_DATA_LS_7; -typedef union SPI_SHADER_USER_DATA_LS_8 regSPI_SHADER_USER_DATA_LS_8; -typedef union SPI_SHADER_USER_DATA_LS_9 regSPI_SHADER_USER_DATA_LS_9; -typedef union SPI_SHADER_USER_DATA_LS_10 regSPI_SHADER_USER_DATA_LS_10; -typedef union SPI_SHADER_USER_DATA_LS_11 regSPI_SHADER_USER_DATA_LS_11; -typedef union SPI_SHADER_USER_DATA_LS_12 regSPI_SHADER_USER_DATA_LS_12; -typedef union SPI_SHADER_USER_DATA_LS_13 regSPI_SHADER_USER_DATA_LS_13; -typedef union SPI_SHADER_USER_DATA_LS_14 regSPI_SHADER_USER_DATA_LS_14; -typedef union SPI_SHADER_USER_DATA_LS_15 regSPI_SHADER_USER_DATA_LS_15; -typedef union SPI_SHADER_USER_DATA_LS_16 regSPI_SHADER_USER_DATA_LS_16; -typedef union SPI_SHADER_USER_DATA_LS_17 regSPI_SHADER_USER_DATA_LS_17; -typedef union SPI_SHADER_USER_DATA_LS_18 regSPI_SHADER_USER_DATA_LS_18; -typedef union SPI_SHADER_USER_DATA_LS_19 regSPI_SHADER_USER_DATA_LS_19; -typedef union SPI_SHADER_USER_DATA_LS_20 regSPI_SHADER_USER_DATA_LS_20; -typedef union SPI_SHADER_USER_DATA_LS_21 regSPI_SHADER_USER_DATA_LS_21; -typedef union SPI_SHADER_USER_DATA_LS_22 regSPI_SHADER_USER_DATA_LS_22; -typedef union SPI_SHADER_USER_DATA_LS_23 regSPI_SHADER_USER_DATA_LS_23; -typedef union SPI_SHADER_USER_DATA_LS_24 regSPI_SHADER_USER_DATA_LS_24; -typedef union SPI_SHADER_USER_DATA_LS_25 regSPI_SHADER_USER_DATA_LS_25; -typedef union SPI_SHADER_USER_DATA_LS_26 regSPI_SHADER_USER_DATA_LS_26; -typedef union SPI_SHADER_USER_DATA_LS_27 regSPI_SHADER_USER_DATA_LS_27; -typedef union SPI_SHADER_USER_DATA_LS_28 regSPI_SHADER_USER_DATA_LS_28; -typedef union SPI_SHADER_USER_DATA_LS_29 regSPI_SHADER_USER_DATA_LS_29; -typedef union SPI_SHADER_USER_DATA_LS_30 regSPI_SHADER_USER_DATA_LS_30; -typedef union SPI_SHADER_USER_DATA_LS_31 regSPI_SHADER_USER_DATA_LS_31; -typedef union SPI_SHADER_USER_DATA_COMMON_0 regSPI_SHADER_USER_DATA_COMMON_0; -typedef union SPI_SHADER_USER_DATA_COMMON_1 regSPI_SHADER_USER_DATA_COMMON_1; -typedef union SPI_SHADER_USER_DATA_COMMON_2 regSPI_SHADER_USER_DATA_COMMON_2; -typedef union SPI_SHADER_USER_DATA_COMMON_3 regSPI_SHADER_USER_DATA_COMMON_3; -typedef union SPI_SHADER_USER_DATA_COMMON_4 regSPI_SHADER_USER_DATA_COMMON_4; -typedef union SPI_SHADER_USER_DATA_COMMON_5 regSPI_SHADER_USER_DATA_COMMON_5; -typedef union SPI_SHADER_USER_DATA_COMMON_6 regSPI_SHADER_USER_DATA_COMMON_6; -typedef union SPI_SHADER_USER_DATA_COMMON_7 regSPI_SHADER_USER_DATA_COMMON_7; -typedef union SPI_SHADER_USER_DATA_COMMON_8 regSPI_SHADER_USER_DATA_COMMON_8; -typedef union SPI_SHADER_USER_DATA_COMMON_9 regSPI_SHADER_USER_DATA_COMMON_9; -typedef union SPI_SHADER_USER_DATA_COMMON_10 regSPI_SHADER_USER_DATA_COMMON_10; -typedef union SPI_SHADER_USER_DATA_COMMON_11 regSPI_SHADER_USER_DATA_COMMON_11; -typedef union SPI_SHADER_USER_DATA_COMMON_12 regSPI_SHADER_USER_DATA_COMMON_12; -typedef union SPI_SHADER_USER_DATA_COMMON_13 regSPI_SHADER_USER_DATA_COMMON_13; -typedef union SPI_SHADER_USER_DATA_COMMON_14 regSPI_SHADER_USER_DATA_COMMON_14; -typedef union SPI_SHADER_USER_DATA_COMMON_15 regSPI_SHADER_USER_DATA_COMMON_15; -typedef union SPI_SHADER_USER_DATA_COMMON_16 regSPI_SHADER_USER_DATA_COMMON_16; -typedef union SPI_SHADER_USER_DATA_COMMON_17 regSPI_SHADER_USER_DATA_COMMON_17; -typedef union SPI_SHADER_USER_DATA_COMMON_18 regSPI_SHADER_USER_DATA_COMMON_18; -typedef union SPI_SHADER_USER_DATA_COMMON_19 regSPI_SHADER_USER_DATA_COMMON_19; -typedef union SPI_SHADER_USER_DATA_COMMON_20 regSPI_SHADER_USER_DATA_COMMON_20; -typedef union SPI_SHADER_USER_DATA_COMMON_21 regSPI_SHADER_USER_DATA_COMMON_21; -typedef union SPI_SHADER_USER_DATA_COMMON_22 regSPI_SHADER_USER_DATA_COMMON_22; -typedef union SPI_SHADER_USER_DATA_COMMON_23 regSPI_SHADER_USER_DATA_COMMON_23; -typedef union SPI_SHADER_USER_DATA_COMMON_24 regSPI_SHADER_USER_DATA_COMMON_24; -typedef union SPI_SHADER_USER_DATA_COMMON_25 regSPI_SHADER_USER_DATA_COMMON_25; -typedef union SPI_SHADER_USER_DATA_COMMON_26 regSPI_SHADER_USER_DATA_COMMON_26; -typedef union SPI_SHADER_USER_DATA_COMMON_27 regSPI_SHADER_USER_DATA_COMMON_27; -typedef union SPI_SHADER_USER_DATA_COMMON_28 regSPI_SHADER_USER_DATA_COMMON_28; -typedef union SPI_SHADER_USER_DATA_COMMON_29 regSPI_SHADER_USER_DATA_COMMON_29; -typedef union SPI_SHADER_USER_DATA_COMMON_30 regSPI_SHADER_USER_DATA_COMMON_30; -typedef union SPI_SHADER_USER_DATA_COMMON_31 regSPI_SHADER_USER_DATA_COMMON_31; -typedef union SPI_ARB_PRIORITY regSPI_ARB_PRIORITY; -typedef union SPI_ARB_CYCLES_0 regSPI_ARB_CYCLES_0; -typedef union SPI_ARB_CYCLES_1 regSPI_ARB_CYCLES_1; -typedef union SPI_CDBG_SYS_GFX regSPI_CDBG_SYS_GFX; -typedef union SPI_CDBG_SYS_HP3D regSPI_CDBG_SYS_HP3D; -typedef union SPI_CDBG_SYS_CS0 regSPI_CDBG_SYS_CS0; -typedef union SPI_CDBG_SYS_CS1 regSPI_CDBG_SYS_CS1; -typedef union SPI_WCL_PIPE_PERCENT_GFX regSPI_WCL_PIPE_PERCENT_GFX; -typedef union SPI_WCL_PIPE_PERCENT_HP3D regSPI_WCL_PIPE_PERCENT_HP3D; -typedef union SPI_WCL_PIPE_PERCENT_CS0 regSPI_WCL_PIPE_PERCENT_CS0; -typedef union SPI_WCL_PIPE_PERCENT_CS1 regSPI_WCL_PIPE_PERCENT_CS1; -typedef union SPI_WCL_PIPE_PERCENT_CS2 regSPI_WCL_PIPE_PERCENT_CS2; -typedef union SPI_WCL_PIPE_PERCENT_CS3 regSPI_WCL_PIPE_PERCENT_CS3; -typedef union SPI_WCL_PIPE_PERCENT_CS4 regSPI_WCL_PIPE_PERCENT_CS4; -typedef union SPI_WCL_PIPE_PERCENT_CS5 regSPI_WCL_PIPE_PERCENT_CS5; -typedef union SPI_WCL_PIPE_PERCENT_CS6 regSPI_WCL_PIPE_PERCENT_CS6; -typedef union SPI_WCL_PIPE_PERCENT_CS7 regSPI_WCL_PIPE_PERCENT_CS7; -typedef union SPI_GDBG_WAVE_CNTL regSPI_GDBG_WAVE_CNTL; -typedef union SPI_GDBG_TRAP_CONFIG regSPI_GDBG_TRAP_CONFIG; -typedef union SPI_GDBG_TRAP_MASK regSPI_GDBG_TRAP_MASK; -typedef union SPI_GDBG_WAVE_CNTL2 regSPI_GDBG_WAVE_CNTL2; -typedef union SPI_GDBG_WAVE_CNTL3 regSPI_GDBG_WAVE_CNTL3; -typedef union SPI_GDBG_TRAP_DATA0 regSPI_GDBG_TRAP_DATA0; -typedef union SPI_GDBG_TRAP_DATA1 regSPI_GDBG_TRAP_DATA1; -typedef union SPI_RESET_DEBUG regSPI_RESET_DEBUG; -typedef union SPI_COMPUTE_QUEUE_RESET regSPI_COMPUTE_QUEUE_RESET; -typedef union SPI_RESOURCE_RESERVE_CU_0 regSPI_RESOURCE_RESERVE_CU_0; -typedef union SPI_RESOURCE_RESERVE_CU_1 regSPI_RESOURCE_RESERVE_CU_1; -typedef union SPI_RESOURCE_RESERVE_CU_2 regSPI_RESOURCE_RESERVE_CU_2; -typedef union SPI_RESOURCE_RESERVE_CU_3 regSPI_RESOURCE_RESERVE_CU_3; -typedef union SPI_RESOURCE_RESERVE_CU_4 regSPI_RESOURCE_RESERVE_CU_4; -typedef union SPI_RESOURCE_RESERVE_CU_5 regSPI_RESOURCE_RESERVE_CU_5; -typedef union SPI_RESOURCE_RESERVE_CU_6 regSPI_RESOURCE_RESERVE_CU_6; -typedef union SPI_RESOURCE_RESERVE_CU_7 regSPI_RESOURCE_RESERVE_CU_7; -typedef union SPI_RESOURCE_RESERVE_CU_8 regSPI_RESOURCE_RESERVE_CU_8; -typedef union SPI_RESOURCE_RESERVE_CU_9 regSPI_RESOURCE_RESERVE_CU_9; -typedef union SPI_RESOURCE_RESERVE_CU_10 regSPI_RESOURCE_RESERVE_CU_10; -typedef union SPI_RESOURCE_RESERVE_CU_11 regSPI_RESOURCE_RESERVE_CU_11; -typedef union SPI_RESOURCE_RESERVE_CU_12 regSPI_RESOURCE_RESERVE_CU_12; -typedef union SPI_RESOURCE_RESERVE_CU_13 regSPI_RESOURCE_RESERVE_CU_13; -typedef union SPI_RESOURCE_RESERVE_CU_14 regSPI_RESOURCE_RESERVE_CU_14; -typedef union SPI_RESOURCE_RESERVE_CU_15 regSPI_RESOURCE_RESERVE_CU_15; -typedef union SPI_RESOURCE_RESERVE_EN_CU_0 regSPI_RESOURCE_RESERVE_EN_CU_0; -typedef union SPI_RESOURCE_RESERVE_EN_CU_1 regSPI_RESOURCE_RESERVE_EN_CU_1; -typedef union SPI_RESOURCE_RESERVE_EN_CU_2 regSPI_RESOURCE_RESERVE_EN_CU_2; -typedef union SPI_RESOURCE_RESERVE_EN_CU_3 regSPI_RESOURCE_RESERVE_EN_CU_3; -typedef union SPI_RESOURCE_RESERVE_EN_CU_4 regSPI_RESOURCE_RESERVE_EN_CU_4; -typedef union SPI_RESOURCE_RESERVE_EN_CU_5 regSPI_RESOURCE_RESERVE_EN_CU_5; -typedef union SPI_RESOURCE_RESERVE_EN_CU_6 regSPI_RESOURCE_RESERVE_EN_CU_6; -typedef union SPI_RESOURCE_RESERVE_EN_CU_7 regSPI_RESOURCE_RESERVE_EN_CU_7; -typedef union SPI_RESOURCE_RESERVE_EN_CU_8 regSPI_RESOURCE_RESERVE_EN_CU_8; -typedef union SPI_RESOURCE_RESERVE_EN_CU_9 regSPI_RESOURCE_RESERVE_EN_CU_9; -typedef union SPI_RESOURCE_RESERVE_EN_CU_10 regSPI_RESOURCE_RESERVE_EN_CU_10; -typedef union SPI_RESOURCE_RESERVE_EN_CU_11 regSPI_RESOURCE_RESERVE_EN_CU_11; -typedef union SPI_RESOURCE_RESERVE_EN_CU_12 regSPI_RESOURCE_RESERVE_EN_CU_12; -typedef union SPI_RESOURCE_RESERVE_EN_CU_13 regSPI_RESOURCE_RESERVE_EN_CU_13; -typedef union SPI_RESOURCE_RESERVE_EN_CU_14 regSPI_RESOURCE_RESERVE_EN_CU_14; -typedef union SPI_RESOURCE_RESERVE_EN_CU_15 regSPI_RESOURCE_RESERVE_EN_CU_15; -typedef union SPI_COMPUTE_WF_CTX_SAVE regSPI_COMPUTE_WF_CTX_SAVE; -typedef union SPI_ARB_CNTL_0 regSPI_ARB_CNTL_0; -typedef union SPI_PS_INPUT_CNTL_0 regSPI_PS_INPUT_CNTL_0; -typedef union SPI_PS_INPUT_CNTL_1 regSPI_PS_INPUT_CNTL_1; -typedef union SPI_PS_INPUT_CNTL_2 regSPI_PS_INPUT_CNTL_2; -typedef union SPI_PS_INPUT_CNTL_3 regSPI_PS_INPUT_CNTL_3; -typedef union SPI_PS_INPUT_CNTL_4 regSPI_PS_INPUT_CNTL_4; -typedef union SPI_PS_INPUT_CNTL_5 regSPI_PS_INPUT_CNTL_5; -typedef union SPI_PS_INPUT_CNTL_6 regSPI_PS_INPUT_CNTL_6; -typedef union SPI_PS_INPUT_CNTL_7 regSPI_PS_INPUT_CNTL_7; -typedef union SPI_PS_INPUT_CNTL_8 regSPI_PS_INPUT_CNTL_8; -typedef union SPI_PS_INPUT_CNTL_9 regSPI_PS_INPUT_CNTL_9; -typedef union SPI_PS_INPUT_CNTL_10 regSPI_PS_INPUT_CNTL_10; -typedef union SPI_PS_INPUT_CNTL_11 regSPI_PS_INPUT_CNTL_11; -typedef union SPI_PS_INPUT_CNTL_12 regSPI_PS_INPUT_CNTL_12; -typedef union SPI_PS_INPUT_CNTL_13 regSPI_PS_INPUT_CNTL_13; -typedef union SPI_PS_INPUT_CNTL_14 regSPI_PS_INPUT_CNTL_14; -typedef union SPI_PS_INPUT_CNTL_15 regSPI_PS_INPUT_CNTL_15; -typedef union SPI_PS_INPUT_CNTL_16 regSPI_PS_INPUT_CNTL_16; -typedef union SPI_PS_INPUT_CNTL_17 regSPI_PS_INPUT_CNTL_17; -typedef union SPI_PS_INPUT_CNTL_18 regSPI_PS_INPUT_CNTL_18; -typedef union SPI_PS_INPUT_CNTL_19 regSPI_PS_INPUT_CNTL_19; -typedef union SPI_PS_INPUT_CNTL_20 regSPI_PS_INPUT_CNTL_20; -typedef union SPI_PS_INPUT_CNTL_21 regSPI_PS_INPUT_CNTL_21; -typedef union SPI_PS_INPUT_CNTL_22 regSPI_PS_INPUT_CNTL_22; -typedef union SPI_PS_INPUT_CNTL_23 regSPI_PS_INPUT_CNTL_23; -typedef union SPI_PS_INPUT_CNTL_24 regSPI_PS_INPUT_CNTL_24; -typedef union SPI_PS_INPUT_CNTL_25 regSPI_PS_INPUT_CNTL_25; -typedef union SPI_PS_INPUT_CNTL_26 regSPI_PS_INPUT_CNTL_26; -typedef union SPI_PS_INPUT_CNTL_27 regSPI_PS_INPUT_CNTL_27; -typedef union SPI_PS_INPUT_CNTL_28 regSPI_PS_INPUT_CNTL_28; -typedef union SPI_PS_INPUT_CNTL_29 regSPI_PS_INPUT_CNTL_29; -typedef union SPI_PS_INPUT_CNTL_30 regSPI_PS_INPUT_CNTL_30; -typedef union SPI_PS_INPUT_CNTL_31 regSPI_PS_INPUT_CNTL_31; -typedef union SPI_VS_OUT_CONFIG regSPI_VS_OUT_CONFIG; -typedef union SPI_PS_INPUT_ENA regSPI_PS_INPUT_ENA; -typedef union SPI_PS_INPUT_ADDR regSPI_PS_INPUT_ADDR; -typedef union SPI_INTERP_CONTROL_0 regSPI_INTERP_CONTROL_0; -typedef union SPI_PS_IN_CONTROL regSPI_PS_IN_CONTROL; -typedef union SPI_BARYC_CNTL regSPI_BARYC_CNTL; -typedef union SPI_TMPRING_SIZE regSPI_TMPRING_SIZE; -typedef union SPI_SHADER_POS_FORMAT regSPI_SHADER_POS_FORMAT; -typedef union SPI_SHADER_Z_FORMAT regSPI_SHADER_Z_FORMAT; -typedef union SPI_SHADER_COL_FORMAT regSPI_SHADER_COL_FORMAT; -typedef union SPI_CONFIG_CNTL regSPI_CONFIG_CNTL; -typedef union SPI_CONFIG_CNTL_1 regSPI_CONFIG_CNTL_1; -typedef union SPI_CONFIG_CNTL_2 regSPI_CONFIG_CNTL_2; -typedef union SPI_PERFCOUNTER0_HI regSPI_PERFCOUNTER0_HI; -typedef union SPI_PERFCOUNTER0_LO regSPI_PERFCOUNTER0_LO; -typedef union SPI_PERFCOUNTER1_HI regSPI_PERFCOUNTER1_HI; -typedef union SPI_PERFCOUNTER1_LO regSPI_PERFCOUNTER1_LO; -typedef union SPI_PERFCOUNTER2_HI regSPI_PERFCOUNTER2_HI; -typedef union SPI_PERFCOUNTER2_LO regSPI_PERFCOUNTER2_LO; -typedef union SPI_PERFCOUNTER3_HI regSPI_PERFCOUNTER3_HI; -typedef union SPI_PERFCOUNTER3_LO regSPI_PERFCOUNTER3_LO; -typedef union SPI_PERFCOUNTER4_HI regSPI_PERFCOUNTER4_HI; -typedef union SPI_PERFCOUNTER4_LO regSPI_PERFCOUNTER4_LO; -typedef union SPI_PERFCOUNTER5_HI regSPI_PERFCOUNTER5_HI; -typedef union SPI_PERFCOUNTER5_LO regSPI_PERFCOUNTER5_LO; -typedef union SPI_PERFCOUNTER0_SELECT regSPI_PERFCOUNTER0_SELECT; -typedef union SPI_PERFCOUNTER1_SELECT regSPI_PERFCOUNTER1_SELECT; -typedef union SPI_PERFCOUNTER2_SELECT regSPI_PERFCOUNTER2_SELECT; -typedef union SPI_PERFCOUNTER3_SELECT regSPI_PERFCOUNTER3_SELECT; -typedef union SPI_PERFCOUNTER0_SELECT1 regSPI_PERFCOUNTER0_SELECT1; -typedef union SPI_PERFCOUNTER1_SELECT1 regSPI_PERFCOUNTER1_SELECT1; -typedef union SPI_PERFCOUNTER2_SELECT1 regSPI_PERFCOUNTER2_SELECT1; -typedef union SPI_PERFCOUNTER3_SELECT1 regSPI_PERFCOUNTER3_SELECT1; -typedef union SPI_PERFCOUNTER4_SELECT regSPI_PERFCOUNTER4_SELECT; -typedef union SPI_PERFCOUNTER5_SELECT regSPI_PERFCOUNTER5_SELECT; -typedef union SPI_PERFCOUNTER_BINS regSPI_PERFCOUNTER_BINS; -typedef union CGTS_SM_CTRL_REG regCGTS_SM_CTRL_REG; -typedef union CGTS_RD_CTRL_REG regCGTS_RD_CTRL_REG; -typedef union CGTS_RD_REG regCGTS_RD_REG; -typedef union CGTS_TCC_DISABLE regCGTS_TCC_DISABLE; -typedef union CGTS_USER_TCC_DISABLE regCGTS_USER_TCC_DISABLE; -typedef union CGTS_CU0_SP0_CTRL_REG regCGTS_CU0_SP0_CTRL_REG; -typedef union CGTS_CU0_LDS_SQ_CTRL_REG regCGTS_CU0_LDS_SQ_CTRL_REG; -typedef union CGTS_CU0_TA_SQC_CTRL_REG regCGTS_CU0_TA_SQC_CTRL_REG; -typedef union CGTS_CU0_SP1_CTRL_REG regCGTS_CU0_SP1_CTRL_REG; -typedef union CGTS_CU0_TD_TCP_CTRL_REG regCGTS_CU0_TD_TCP_CTRL_REG; -typedef union CGTS_CU0_TCPI_CTRL_REG regCGTS_CU0_TCPI_CTRL_REG; -typedef union CGTS_CU1_SP0_CTRL_REG regCGTS_CU1_SP0_CTRL_REG; -typedef union CGTS_CU1_LDS_SQ_CTRL_REG regCGTS_CU1_LDS_SQ_CTRL_REG; -typedef union CGTS_CU1_TA_SQC_CTRL_REG regCGTS_CU1_TA_SQC_CTRL_REG; -typedef union CGTS_CU1_SP1_CTRL_REG regCGTS_CU1_SP1_CTRL_REG; -typedef union CGTS_CU1_TD_TCP_CTRL_REG regCGTS_CU1_TD_TCP_CTRL_REG; -typedef union CGTS_CU1_TCPI_CTRL_REG regCGTS_CU1_TCPI_CTRL_REG; -typedef union CGTS_CU2_SP0_CTRL_REG regCGTS_CU2_SP0_CTRL_REG; -typedef union CGTS_CU2_LDS_SQ_CTRL_REG regCGTS_CU2_LDS_SQ_CTRL_REG; -typedef union CGTS_CU2_TA_SQC_CTRL_REG regCGTS_CU2_TA_SQC_CTRL_REG; -typedef union CGTS_CU2_SP1_CTRL_REG regCGTS_CU2_SP1_CTRL_REG; -typedef union CGTS_CU2_TD_TCP_CTRL_REG regCGTS_CU2_TD_TCP_CTRL_REG; -typedef union CGTS_CU2_TCPI_CTRL_REG regCGTS_CU2_TCPI_CTRL_REG; -typedef union CGTS_CU3_SP0_CTRL_REG regCGTS_CU3_SP0_CTRL_REG; -typedef union CGTS_CU3_LDS_SQ_CTRL_REG regCGTS_CU3_LDS_SQ_CTRL_REG; -typedef union CGTS_CU3_TA_SQC_CTRL_REG regCGTS_CU3_TA_SQC_CTRL_REG; -typedef union CGTS_CU3_SP1_CTRL_REG regCGTS_CU3_SP1_CTRL_REG; -typedef union CGTS_CU3_TD_TCP_CTRL_REG regCGTS_CU3_TD_TCP_CTRL_REG; -typedef union CGTS_CU3_TCPI_CTRL_REG regCGTS_CU3_TCPI_CTRL_REG; -typedef union CGTS_CU4_SP0_CTRL_REG regCGTS_CU4_SP0_CTRL_REG; -typedef union CGTS_CU4_LDS_SQ_CTRL_REG regCGTS_CU4_LDS_SQ_CTRL_REG; -typedef union CGTS_CU4_TA_SQC_CTRL_REG regCGTS_CU4_TA_SQC_CTRL_REG; -typedef union CGTS_CU4_SP1_CTRL_REG regCGTS_CU4_SP1_CTRL_REG; -typedef union CGTS_CU4_TD_TCP_CTRL_REG regCGTS_CU4_TD_TCP_CTRL_REG; -typedef union CGTS_CU4_TCPI_CTRL_REG regCGTS_CU4_TCPI_CTRL_REG; -typedef union CGTS_CU5_SP0_CTRL_REG regCGTS_CU5_SP0_CTRL_REG; -typedef union CGTS_CU5_LDS_SQ_CTRL_REG regCGTS_CU5_LDS_SQ_CTRL_REG; -typedef union CGTS_CU5_TA_SQC_CTRL_REG regCGTS_CU5_TA_SQC_CTRL_REG; -typedef union CGTS_CU5_SP1_CTRL_REG regCGTS_CU5_SP1_CTRL_REG; -typedef union CGTS_CU5_TD_TCP_CTRL_REG regCGTS_CU5_TD_TCP_CTRL_REG; -typedef union CGTS_CU5_TCPI_CTRL_REG regCGTS_CU5_TCPI_CTRL_REG; -typedef union CGTS_CU6_SP0_CTRL_REG regCGTS_CU6_SP0_CTRL_REG; -typedef union CGTS_CU6_LDS_SQ_CTRL_REG regCGTS_CU6_LDS_SQ_CTRL_REG; -typedef union CGTS_CU6_TA_SQC_CTRL_REG regCGTS_CU6_TA_SQC_CTRL_REG; -typedef union CGTS_CU6_SP1_CTRL_REG regCGTS_CU6_SP1_CTRL_REG; -typedef union CGTS_CU6_TD_TCP_CTRL_REG regCGTS_CU6_TD_TCP_CTRL_REG; -typedef union CGTS_CU6_TCPI_CTRL_REG regCGTS_CU6_TCPI_CTRL_REG; -typedef union CGTS_CU7_SP0_CTRL_REG regCGTS_CU7_SP0_CTRL_REG; -typedef union CGTS_CU7_LDS_SQ_CTRL_REG regCGTS_CU7_LDS_SQ_CTRL_REG; -typedef union CGTS_CU7_TA_SQC_CTRL_REG regCGTS_CU7_TA_SQC_CTRL_REG; -typedef union CGTS_CU7_SP1_CTRL_REG regCGTS_CU7_SP1_CTRL_REG; -typedef union CGTS_CU7_TD_TCP_CTRL_REG regCGTS_CU7_TD_TCP_CTRL_REG; -typedef union CGTS_CU7_TCPI_CTRL_REG regCGTS_CU7_TCPI_CTRL_REG; -typedef union CGTS_CU8_SP0_CTRL_REG regCGTS_CU8_SP0_CTRL_REG; -typedef union CGTS_CU8_LDS_SQ_CTRL_REG regCGTS_CU8_LDS_SQ_CTRL_REG; -typedef union CGTS_CU8_TA_SQC_CTRL_REG regCGTS_CU8_TA_SQC_CTRL_REG; -typedef union CGTS_CU8_SP1_CTRL_REG regCGTS_CU8_SP1_CTRL_REG; -typedef union CGTS_CU8_TD_TCP_CTRL_REG regCGTS_CU8_TD_TCP_CTRL_REG; -typedef union CGTS_CU8_TCPI_CTRL_REG regCGTS_CU8_TCPI_CTRL_REG; -typedef union CGTS_CU9_SP0_CTRL_REG regCGTS_CU9_SP0_CTRL_REG; -typedef union CGTS_CU9_LDS_SQ_CTRL_REG regCGTS_CU9_LDS_SQ_CTRL_REG; -typedef union CGTS_CU9_TA_SQC_CTRL_REG regCGTS_CU9_TA_SQC_CTRL_REG; -typedef union CGTS_CU9_SP1_CTRL_REG regCGTS_CU9_SP1_CTRL_REG; -typedef union CGTS_CU9_TD_TCP_CTRL_REG regCGTS_CU9_TD_TCP_CTRL_REG; -typedef union CGTS_CU9_TCPI_CTRL_REG regCGTS_CU9_TCPI_CTRL_REG; -typedef union CGTS_CU10_SP0_CTRL_REG regCGTS_CU10_SP0_CTRL_REG; -typedef union CGTS_CU10_LDS_SQ_CTRL_REG regCGTS_CU10_LDS_SQ_CTRL_REG; -typedef union CGTS_CU10_TA_SQC_CTRL_REG regCGTS_CU10_TA_SQC_CTRL_REG; -typedef union CGTS_CU10_SP1_CTRL_REG regCGTS_CU10_SP1_CTRL_REG; -typedef union CGTS_CU10_TD_TCP_CTRL_REG regCGTS_CU10_TD_TCP_CTRL_REG; -typedef union CGTS_CU10_TCPI_CTRL_REG regCGTS_CU10_TCPI_CTRL_REG; -typedef union CGTS_CU11_SP0_CTRL_REG regCGTS_CU11_SP0_CTRL_REG; -typedef union CGTS_CU11_LDS_SQ_CTRL_REG regCGTS_CU11_LDS_SQ_CTRL_REG; -typedef union CGTS_CU11_TA_SQC_CTRL_REG regCGTS_CU11_TA_SQC_CTRL_REG; -typedef union CGTS_CU11_SP1_CTRL_REG regCGTS_CU11_SP1_CTRL_REG; -typedef union CGTS_CU11_TD_TCP_CTRL_REG regCGTS_CU11_TD_TCP_CTRL_REG; -typedef union CGTS_CU11_TCPI_CTRL_REG regCGTS_CU11_TCPI_CTRL_REG; -typedef union CGTS_CU12_SP0_CTRL_REG regCGTS_CU12_SP0_CTRL_REG; -typedef union CGTS_CU12_LDS_SQ_CTRL_REG regCGTS_CU12_LDS_SQ_CTRL_REG; -typedef union CGTS_CU12_TA_SQC_CTRL_REG regCGTS_CU12_TA_SQC_CTRL_REG; -typedef union CGTS_CU12_SP1_CTRL_REG regCGTS_CU12_SP1_CTRL_REG; -typedef union CGTS_CU12_TD_TCP_CTRL_REG regCGTS_CU12_TD_TCP_CTRL_REG; -typedef union CGTS_CU12_TCPI_CTRL_REG regCGTS_CU12_TCPI_CTRL_REG; -typedef union CGTS_CU13_SP0_CTRL_REG regCGTS_CU13_SP0_CTRL_REG; -typedef union CGTS_CU13_LDS_SQ_CTRL_REG regCGTS_CU13_LDS_SQ_CTRL_REG; -typedef union CGTS_CU13_TA_SQC_CTRL_REG regCGTS_CU13_TA_SQC_CTRL_REG; -typedef union CGTS_CU13_SP1_CTRL_REG regCGTS_CU13_SP1_CTRL_REG; -typedef union CGTS_CU13_TD_TCP_CTRL_REG regCGTS_CU13_TD_TCP_CTRL_REG; -typedef union CGTS_CU13_TCPI_CTRL_REG regCGTS_CU13_TCPI_CTRL_REG; -typedef union CGTS_CU14_SP0_CTRL_REG regCGTS_CU14_SP0_CTRL_REG; -typedef union CGTS_CU14_LDS_SQ_CTRL_REG regCGTS_CU14_LDS_SQ_CTRL_REG; -typedef union CGTS_CU14_TA_SQC_CTRL_REG regCGTS_CU14_TA_SQC_CTRL_REG; -typedef union CGTS_CU14_SP1_CTRL_REG regCGTS_CU14_SP1_CTRL_REG; -typedef union CGTS_CU14_TD_TCP_CTRL_REG regCGTS_CU14_TD_TCP_CTRL_REG; -typedef union CGTS_CU14_TCPI_CTRL_REG regCGTS_CU14_TCPI_CTRL_REG; -typedef union CGTS_CU15_SP0_CTRL_REG regCGTS_CU15_SP0_CTRL_REG; -typedef union CGTS_CU15_LDS_SQ_CTRL_REG regCGTS_CU15_LDS_SQ_CTRL_REG; -typedef union CGTS_CU15_TA_SQC_CTRL_REG regCGTS_CU15_TA_SQC_CTRL_REG; -typedef union CGTS_CU15_SP1_CTRL_REG regCGTS_CU15_SP1_CTRL_REG; -typedef union CGTS_CU15_TD_TCP_CTRL_REG regCGTS_CU15_TD_TCP_CTRL_REG; -typedef union CGTS_CU15_TCPI_CTRL_REG regCGTS_CU15_TCPI_CTRL_REG; -typedef union CGTT_SPI_CLK_CTRL regCGTT_SPI_CLK_CTRL; -typedef union CGTT_PC_CLK_CTRL regCGTT_PC_CLK_CTRL; -typedef union CGTT_BCI_CLK_CTRL regCGTT_BCI_CLK_CTRL; -typedef union SQ_CONFIG regSQ_CONFIG; -typedef union SQC_CONFIG regSQC_CONFIG; -typedef union LDS_CONFIG regLDS_CONFIG; -typedef union SQC_DSM_CNTL regSQC_DSM_CNTL; -typedef union SQC_DSM_CNTLA regSQC_DSM_CNTLA; -typedef union SQC_DSM_CNTLB regSQC_DSM_CNTLB; -typedef union SQC_DSM_CNTL2 regSQC_DSM_CNTL2; -typedef union SQC_DSM_CNTL2A regSQC_DSM_CNTL2A; -typedef union SQC_DSM_CNTL2B regSQC_DSM_CNTL2B; -typedef union SQC_EDC_FUE_CNTL regSQC_EDC_FUE_CNTL; -typedef union SQC_EDC_CNT2 regSQC_EDC_CNT2; -typedef union SQC_EDC_CNT3 regSQC_EDC_CNT3; -typedef union SQ_RANDOM_WAVE_PRI regSQ_RANDOM_WAVE_PRI; -typedef union SQ_REG_CREDITS regSQ_REG_CREDITS; -typedef union SQ_FIFO_SIZES regSQ_FIFO_SIZES; -typedef union SQ_DSM_CNTL regSQ_DSM_CNTL; -typedef union SQ_DSM_CNTL2 regSQ_DSM_CNTL2; -typedef union SQ_RUNTIME_CONFIG regSQ_RUNTIME_CONFIG; -typedef union CC_GC_SHADER_RATE_CONFIG regCC_GC_SHADER_RATE_CONFIG; -typedef union GC_USER_SHADER_RATE_CONFIG regGC_USER_SHADER_RATE_CONFIG; -typedef union SQ_INTERRUPT_AUTO_MASK regSQ_INTERRUPT_AUTO_MASK; -typedef union SQ_INTERRUPT_MSG_CTRL regSQ_INTERRUPT_MSG_CTRL; -typedef union SQ_DEBUG_PERFCOUNT_TRAP regSQ_DEBUG_PERFCOUNT_TRAP; -typedef union SQ_UTCL1_CNTL1 regSQ_UTCL1_CNTL1; -typedef union SQ_UTCL1_CNTL2 regSQ_UTCL1_CNTL2; -typedef union SQ_UTCL1_STATUS regSQ_UTCL1_STATUS; -typedef union SQ_TIME_HI regSQ_TIME_HI; -typedef union SQ_TIME_LO regSQ_TIME_LO; -typedef union SQ_LB_CTR_CTRL regSQ_LB_CTR_CTRL; -typedef union SQ_LB_DATA0 regSQ_LB_DATA0; -typedef union SQ_LB_DATA1 regSQ_LB_DATA1; -typedef union SQ_LB_DATA2 regSQ_LB_DATA2; -typedef union SQ_LB_DATA3 regSQ_LB_DATA3; -typedef union SQ_LB_CTR_SEL regSQ_LB_CTR_SEL; -typedef union SQ_LB_CTR0_CU regSQ_LB_CTR0_CU; -typedef union SQ_LB_CTR1_CU regSQ_LB_CTR1_CU; -typedef union SQ_LB_CTR2_CU regSQ_LB_CTR2_CU; -typedef union SQ_LB_CTR3_CU regSQ_LB_CTR3_CU; -typedef union SQC_EDC_CNT regSQC_EDC_CNT; -typedef union SQ_EDC_SEC_CNT regSQ_EDC_SEC_CNT; -typedef union SQ_EDC_DED_CNT regSQ_EDC_DED_CNT; -typedef union SQ_EDC_INFO regSQ_EDC_INFO; -typedef union SQ_EDC_CNT regSQ_EDC_CNT; -typedef union SQ_EDC_FUE_CNTL regSQ_EDC_FUE_CNTL; -typedef union SQ_BUF_RSRC_WORD0 regSQ_BUF_RSRC_WORD0; -typedef union SQ_BUF_RSRC_WORD1 regSQ_BUF_RSRC_WORD1; -typedef union SQ_BUF_RSRC_WORD2 regSQ_BUF_RSRC_WORD2; -typedef union SQ_BUF_RSRC_WORD3 regSQ_BUF_RSRC_WORD3; -typedef union SQ_IMG_RSRC_WORD0 regSQ_IMG_RSRC_WORD0; -typedef union SQ_IMG_RSRC_WORD1 regSQ_IMG_RSRC_WORD1; -typedef union SQ_IMG_RSRC_WORD2 regSQ_IMG_RSRC_WORD2; -typedef union SQ_IMG_RSRC_WORD3 regSQ_IMG_RSRC_WORD3; -typedef union SQ_IMG_RSRC_WORD4 regSQ_IMG_RSRC_WORD4; -typedef union SQ_IMG_RSRC_WORD5 regSQ_IMG_RSRC_WORD5; -typedef union SQ_IMG_RSRC_WORD6 regSQ_IMG_RSRC_WORD6; -typedef union SQ_IMG_RSRC_WORD7 regSQ_IMG_RSRC_WORD7; -typedef union SQ_IMG_SAMP_WORD0 regSQ_IMG_SAMP_WORD0; -typedef union SQ_IMG_SAMP_WORD1 regSQ_IMG_SAMP_WORD1; -typedef union SQ_IMG_SAMP_WORD2 regSQ_IMG_SAMP_WORD2; -typedef union SQ_IMG_SAMP_WORD3 regSQ_IMG_SAMP_WORD3; -typedef union SQ_FLAT_SCRATCH_WORD0 regSQ_FLAT_SCRATCH_WORD0; -typedef union SQ_FLAT_SCRATCH_WORD1 regSQ_FLAT_SCRATCH_WORD1; -typedef union SQ_M0_GPR_IDX_WORD regSQ_M0_GPR_IDX_WORD; -typedef union SQ_IND_INDEX regSQ_IND_INDEX; -typedef union SQ_CMD regSQ_CMD; -typedef union SQ_IND_DATA regSQ_IND_DATA; -typedef union SQ_REG_TIMESTAMP regSQ_REG_TIMESTAMP; -typedef union SQ_CMD_TIMESTAMP regSQ_CMD_TIMESTAMP; -typedef union SQ_DEBUG_STS_GLOBAL regSQ_DEBUG_STS_GLOBAL; -typedef union SQ_DEBUG_STS_GLOBAL2 regSQ_DEBUG_STS_GLOBAL2; -typedef union SQ_DEBUG_STS_GLOBAL3 regSQ_DEBUG_STS_GLOBAL3; -typedef union SH_MEM_BASES regSH_MEM_BASES; -typedef union SH_MEM_CONFIG regSH_MEM_CONFIG; -typedef union SQ_SHADER_TBA_LO regSQ_SHADER_TBA_LO; -typedef union SQ_SHADER_TBA_HI regSQ_SHADER_TBA_HI; -typedef union SQ_SHADER_TMA_LO regSQ_SHADER_TMA_LO; -typedef union SQ_SHADER_TMA_HI regSQ_SHADER_TMA_HI; -typedef union SQ_THREAD_TRACE_WORD_CMN regSQ_THREAD_TRACE_WORD_CMN; -typedef union SQ_THREAD_TRACE_WORD_INST regSQ_THREAD_TRACE_WORD_INST; -typedef union SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 - regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 - regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_WAVE regSQ_THREAD_TRACE_WORD_WAVE; -typedef union SQ_THREAD_TRACE_WORD_MISC regSQ_THREAD_TRACE_WORD_MISC; -typedef union SQ_THREAD_TRACE_WORD_WAVE_START regSQ_THREAD_TRACE_WORD_WAVE_START; -typedef union SQ_THREAD_TRACE_WORD_REG_1_OF_2 regSQ_THREAD_TRACE_WORD_REG_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_REG_2_OF_2 regSQ_THREAD_TRACE_WORD_REG_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2; -typedef union SQ_THREAD_TRACE_WORD_EVENT regSQ_THREAD_TRACE_WORD_EVENT; -typedef union SQ_THREAD_TRACE_WORD_ISSUE regSQ_THREAD_TRACE_WORD_ISSUE; -typedef union SQ_THREAD_TRACE_WORD_PERF_1_OF_2 regSQ_THREAD_TRACE_WORD_PERF_1_OF_2; -typedef union SQ_THREAD_TRACE_WORD_PERF_2_OF_2 regSQ_THREAD_TRACE_WORD_PERF_2_OF_2; -typedef union SQ_WREXEC_EXEC_LO regSQ_WREXEC_EXEC_LO; -typedef union SQ_WREXEC_EXEC_HI regSQ_WREXEC_EXEC_HI; -typedef union SQC_ICACHE_UTCL1_CNTL1 regSQC_ICACHE_UTCL1_CNTL1; -typedef union SQC_ICACHE_UTCL1_CNTL2 regSQC_ICACHE_UTCL1_CNTL2; -typedef union SQC_DCACHE_UTCL1_CNTL1 regSQC_DCACHE_UTCL1_CNTL1; -typedef union SQC_DCACHE_UTCL1_CNTL2 regSQC_DCACHE_UTCL1_CNTL2; -typedef union SQC_ICACHE_UTCL1_STATUS regSQC_ICACHE_UTCL1_STATUS; -typedef union SQC_DCACHE_UTCL1_STATUS regSQC_DCACHE_UTCL1_STATUS; -typedef union SQC_CACHES regSQC_CACHES; -typedef union SQC_WRITEBACK regSQC_WRITEBACK; -typedef union SQ_THREAD_TRACE_BASE regSQ_THREAD_TRACE_BASE; -typedef union SQ_THREAD_TRACE_BASE2 regSQ_THREAD_TRACE_BASE2; -typedef union SQ_THREAD_TRACE_SIZE regSQ_THREAD_TRACE_SIZE; -typedef union SQ_THREAD_TRACE_MASK regSQ_THREAD_TRACE_MASK; -typedef union SQ_THREAD_TRACE_USERDATA_0 regSQ_THREAD_TRACE_USERDATA_0; -typedef union SQ_THREAD_TRACE_USERDATA_1 regSQ_THREAD_TRACE_USERDATA_1; -typedef union SQ_THREAD_TRACE_USERDATA_2 regSQ_THREAD_TRACE_USERDATA_2; -typedef union SQ_THREAD_TRACE_USERDATA_3 regSQ_THREAD_TRACE_USERDATA_3; -typedef union SQ_THREAD_TRACE_MODE regSQ_THREAD_TRACE_MODE; -typedef union SQ_THREAD_TRACE_CTRL regSQ_THREAD_TRACE_CTRL; -typedef union SQ_THREAD_TRACE_TOKEN_MASK regSQ_THREAD_TRACE_TOKEN_MASK; -typedef union SQ_THREAD_TRACE_TOKEN_MASK2 regSQ_THREAD_TRACE_TOKEN_MASK2; -typedef union SQ_THREAD_TRACE_PERF_MASK regSQ_THREAD_TRACE_PERF_MASK; -typedef union SQ_THREAD_TRACE_WPTR regSQ_THREAD_TRACE_WPTR; -typedef union SQ_THREAD_TRACE_STATUS regSQ_THREAD_TRACE_STATUS; -typedef union SQ_THREAD_TRACE_CNTR regSQ_THREAD_TRACE_CNTR; -typedef union SQ_THREAD_TRACE_HIWATER regSQ_THREAD_TRACE_HIWATER; -typedef union SQ_PERFCOUNTER0_LO regSQ_PERFCOUNTER0_LO; -typedef union SQ_PERFCOUNTER1_LO regSQ_PERFCOUNTER1_LO; -typedef union SQ_PERFCOUNTER2_LO regSQ_PERFCOUNTER2_LO; -typedef union SQ_PERFCOUNTER3_LO regSQ_PERFCOUNTER3_LO; -typedef union SQ_PERFCOUNTER4_LO regSQ_PERFCOUNTER4_LO; -typedef union SQ_PERFCOUNTER5_LO regSQ_PERFCOUNTER5_LO; -typedef union SQ_PERFCOUNTER6_LO regSQ_PERFCOUNTER6_LO; -typedef union SQ_PERFCOUNTER7_LO regSQ_PERFCOUNTER7_LO; -typedef union SQ_PERFCOUNTER8_LO regSQ_PERFCOUNTER8_LO; -typedef union SQ_PERFCOUNTER9_LO regSQ_PERFCOUNTER9_LO; -typedef union SQ_PERFCOUNTER10_LO regSQ_PERFCOUNTER10_LO; -typedef union SQ_PERFCOUNTER11_LO regSQ_PERFCOUNTER11_LO; -typedef union SQ_PERFCOUNTER12_LO regSQ_PERFCOUNTER12_LO; -typedef union SQ_PERFCOUNTER13_LO regSQ_PERFCOUNTER13_LO; -typedef union SQ_PERFCOUNTER14_LO regSQ_PERFCOUNTER14_LO; -typedef union SQ_PERFCOUNTER15_LO regSQ_PERFCOUNTER15_LO; -typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; -typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; -typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; -typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; -typedef union SQ_PERFCOUNTER4_HI regSQ_PERFCOUNTER4_HI; -typedef union SQ_PERFCOUNTER5_HI regSQ_PERFCOUNTER5_HI; -typedef union SQ_PERFCOUNTER6_HI regSQ_PERFCOUNTER6_HI; -typedef union SQ_PERFCOUNTER7_HI regSQ_PERFCOUNTER7_HI; -typedef union SQ_PERFCOUNTER8_HI regSQ_PERFCOUNTER8_HI; -typedef union SQ_PERFCOUNTER9_HI regSQ_PERFCOUNTER9_HI; -typedef union SQ_PERFCOUNTER10_HI regSQ_PERFCOUNTER10_HI; -typedef union SQ_PERFCOUNTER11_HI regSQ_PERFCOUNTER11_HI; -typedef union SQ_PERFCOUNTER12_HI regSQ_PERFCOUNTER12_HI; -typedef union SQ_PERFCOUNTER13_HI regSQ_PERFCOUNTER13_HI; -typedef union SQ_PERFCOUNTER14_HI regSQ_PERFCOUNTER14_HI; -typedef union SQ_PERFCOUNTER15_HI regSQ_PERFCOUNTER15_HI; -typedef union SQ_PERFCOUNTER_CTRL regSQ_PERFCOUNTER_CTRL; -typedef union SQ_PERFCOUNTER_MASK regSQ_PERFCOUNTER_MASK; -typedef union SQ_PERFCOUNTER_CTRL2 regSQ_PERFCOUNTER_CTRL2; -typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; -typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; -typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; -typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; -typedef union SQ_PERFCOUNTER4_SELECT regSQ_PERFCOUNTER4_SELECT; -typedef union SQ_PERFCOUNTER5_SELECT regSQ_PERFCOUNTER5_SELECT; -typedef union SQ_PERFCOUNTER6_SELECT regSQ_PERFCOUNTER6_SELECT; -typedef union SQ_PERFCOUNTER7_SELECT regSQ_PERFCOUNTER7_SELECT; -typedef union SQ_PERFCOUNTER8_SELECT regSQ_PERFCOUNTER8_SELECT; -typedef union SQ_PERFCOUNTER9_SELECT regSQ_PERFCOUNTER9_SELECT; -typedef union SQ_PERFCOUNTER10_SELECT regSQ_PERFCOUNTER10_SELECT; -typedef union SQ_PERFCOUNTER11_SELECT regSQ_PERFCOUNTER11_SELECT; -typedef union SQ_PERFCOUNTER12_SELECT regSQ_PERFCOUNTER12_SELECT; -typedef union SQ_PERFCOUNTER13_SELECT regSQ_PERFCOUNTER13_SELECT; -typedef union SQ_PERFCOUNTER14_SELECT regSQ_PERFCOUNTER14_SELECT; -typedef union SQ_PERFCOUNTER15_SELECT regSQ_PERFCOUNTER15_SELECT; -typedef union CGTT_SQ_CLK_CTRL regCGTT_SQ_CLK_CTRL; -typedef union CGTT_SQG_CLK_CTRL regCGTT_SQG_CLK_CTRL; -typedef union SQ_ALU_CLK_CTRL regSQ_ALU_CLK_CTRL; -typedef union SQ_TEX_CLK_CTRL regSQ_TEX_CLK_CTRL; -typedef union SQ_LDS_CLK_CTRL regSQ_LDS_CLK_CTRL; -typedef union SQ_POWER_THROTTLE regSQ_POWER_THROTTLE; -typedef union SQ_POWER_THROTTLE2 regSQ_POWER_THROTTLE2; -typedef union SQ_WAVE_INST_DW0 regSQ_WAVE_INST_DW0; -typedef union SQ_WAVE_INST_DW1 regSQ_WAVE_INST_DW1; -typedef union SQ_WAVE_PC_LO regSQ_WAVE_PC_LO; -typedef union SQ_WAVE_PC_HI regSQ_WAVE_PC_HI; -typedef union SQ_WAVE_IB_DBG0 regSQ_WAVE_IB_DBG0; -typedef union SQ_WAVE_IB_DBG1 regSQ_WAVE_IB_DBG1; -typedef union SQ_WAVE_FLUSH_IB regSQ_WAVE_FLUSH_IB; -typedef union SQ_WAVE_EXEC_LO regSQ_WAVE_EXEC_LO; -typedef union SQ_WAVE_EXEC_HI regSQ_WAVE_EXEC_HI; -typedef union SQ_WAVE_STATUS regSQ_WAVE_STATUS; -typedef union SQ_WAVE_MODE regSQ_WAVE_MODE; -typedef union SQ_WAVE_TRAPSTS regSQ_WAVE_TRAPSTS; -typedef union SQ_WAVE_HW_ID regSQ_WAVE_HW_ID; -typedef union SQ_WAVE_GPR_ALLOC regSQ_WAVE_GPR_ALLOC; -typedef union SQ_WAVE_LDS_ALLOC regSQ_WAVE_LDS_ALLOC; -typedef union SQ_WAVE_IB_STS regSQ_WAVE_IB_STS; -typedef union SQ_WAVE_M0 regSQ_WAVE_M0; -typedef union SQ_WAVE_TTMP0 regSQ_WAVE_TTMP0; -typedef union SQ_WAVE_TTMP1 regSQ_WAVE_TTMP1; -typedef union SQ_WAVE_TTMP2 regSQ_WAVE_TTMP2; -typedef union SQ_WAVE_TTMP3 regSQ_WAVE_TTMP3; -typedef union SQ_WAVE_TTMP4 regSQ_WAVE_TTMP4; -typedef union SQ_WAVE_TTMP5 regSQ_WAVE_TTMP5; -typedef union SQ_WAVE_TTMP6 regSQ_WAVE_TTMP6; -typedef union SQ_WAVE_TTMP7 regSQ_WAVE_TTMP7; -typedef union SQ_WAVE_TTMP8 regSQ_WAVE_TTMP8; -typedef union SQ_WAVE_TTMP9 regSQ_WAVE_TTMP9; -typedef union SQ_WAVE_TTMP10 regSQ_WAVE_TTMP10; -typedef union SQ_WAVE_TTMP11 regSQ_WAVE_TTMP11; -typedef union SQ_WAVE_TTMP12 regSQ_WAVE_TTMP12; -typedef union SQ_WAVE_TTMP13 regSQ_WAVE_TTMP13; -typedef union SQ_WAVE_TTMP14 regSQ_WAVE_TTMP14; -typedef union SQ_WAVE_TTMP15 regSQ_WAVE_TTMP15; -typedef union SQ_DEBUG_STS_LOCAL regSQ_DEBUG_STS_LOCAL; -typedef union SQ_DEBUG_CTRL_LOCAL regSQ_DEBUG_CTRL_LOCAL; -typedef union SQ_INTERRUPT_WORD_CMN_HI regSQ_INTERRUPT_WORD_CMN_HI; -typedef union SQ_INTERRUPT_WORD_AUTO_LO regSQ_INTERRUPT_WORD_AUTO_LO; -typedef union SQ_INTERRUPT_WORD_AUTO_HI regSQ_INTERRUPT_WORD_AUTO_HI; -typedef union SQ_INTERRUPT_WORD_WAVE_LO regSQ_INTERRUPT_WORD_WAVE_LO; -typedef union SQ_INTERRUPT_WORD_WAVE_HI regSQ_INTERRUPT_WORD_WAVE_HI; -typedef union SQ_INTERRUPT_WORD_CMN_CTXID regSQ_INTERRUPT_WORD_CMN_CTXID; -typedef union SQ_INTERRUPT_WORD_AUTO_CTXID regSQ_INTERRUPT_WORD_AUTO_CTXID; -typedef union SQ_INTERRUPT_WORD_WAVE_CTXID regSQ_INTERRUPT_WORD_WAVE_CTXID; -typedef union COMPUTE_DISPATCH_INITIATOR regCOMPUTE_DISPATCH_INITIATOR; -typedef union COMPUTE_DIM_X regCOMPUTE_DIM_X; -typedef union COMPUTE_DIM_Y regCOMPUTE_DIM_Y; -typedef union COMPUTE_DIM_Z regCOMPUTE_DIM_Z; -typedef union COMPUTE_START_X regCOMPUTE_START_X; -typedef union COMPUTE_START_Y regCOMPUTE_START_Y; -typedef union COMPUTE_START_Z regCOMPUTE_START_Z; -typedef union COMPUTE_NUM_THREAD_X regCOMPUTE_NUM_THREAD_X; -typedef union COMPUTE_NUM_THREAD_Y regCOMPUTE_NUM_THREAD_Y; -typedef union COMPUTE_NUM_THREAD_Z regCOMPUTE_NUM_THREAD_Z; -typedef union COMPUTE_PIPELINESTAT_ENABLE regCOMPUTE_PIPELINESTAT_ENABLE; -typedef union COMPUTE_PERFCOUNT_ENABLE regCOMPUTE_PERFCOUNT_ENABLE; -typedef union COMPUTE_PGM_LO regCOMPUTE_PGM_LO; -typedef union COMPUTE_PGM_HI regCOMPUTE_PGM_HI; -typedef union COMPUTE_DISPATCH_PKT_ADDR_LO regCOMPUTE_DISPATCH_PKT_ADDR_LO; -typedef union COMPUTE_DISPATCH_PKT_ADDR_HI regCOMPUTE_DISPATCH_PKT_ADDR_HI; -typedef union COMPUTE_DISPATCH_SCRATCH_BASE_LO regCOMPUTE_DISPATCH_SCRATCH_BASE_LO; -typedef union COMPUTE_DISPATCH_SCRATCH_BASE_HI regCOMPUTE_DISPATCH_SCRATCH_BASE_HI; -typedef union COMPUTE_PGM_RSRC1 regCOMPUTE_PGM_RSRC1; -typedef union COMPUTE_PGM_RSRC2 regCOMPUTE_PGM_RSRC2; -typedef union COMPUTE_VMID regCOMPUTE_VMID; -typedef union COMPUTE_RESOURCE_LIMITS regCOMPUTE_RESOURCE_LIMITS; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE0 regCOMPUTE_STATIC_THREAD_MGMT_SE0; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE1 regCOMPUTE_STATIC_THREAD_MGMT_SE1; -typedef union COMPUTE_TMPRING_SIZE regCOMPUTE_TMPRING_SIZE; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE2 regCOMPUTE_STATIC_THREAD_MGMT_SE2; -typedef union COMPUTE_STATIC_THREAD_MGMT_SE3 regCOMPUTE_STATIC_THREAD_MGMT_SE3; -typedef union COMPUTE_RESTART_X regCOMPUTE_RESTART_X; -typedef union COMPUTE_RESTART_Y regCOMPUTE_RESTART_Y; -typedef union COMPUTE_RESTART_Z regCOMPUTE_RESTART_Z; -typedef union COMPUTE_THREAD_TRACE_ENABLE regCOMPUTE_THREAD_TRACE_ENABLE; -typedef union COMPUTE_MISC_RESERVED regCOMPUTE_MISC_RESERVED; -typedef union COMPUTE_DISPATCH_ID regCOMPUTE_DISPATCH_ID; -typedef union COMPUTE_THREADGROUP_ID regCOMPUTE_THREADGROUP_ID; -typedef union COMPUTE_RELAUNCH regCOMPUTE_RELAUNCH; -typedef union COMPUTE_WAVE_RESTORE_ADDR_LO regCOMPUTE_WAVE_RESTORE_ADDR_LO; -typedef union COMPUTE_WAVE_RESTORE_ADDR_HI regCOMPUTE_WAVE_RESTORE_ADDR_HI; -typedef union COMPUTE_USER_DATA_0 regCOMPUTE_USER_DATA_0; -typedef union COMPUTE_USER_DATA_1 regCOMPUTE_USER_DATA_1; -typedef union COMPUTE_USER_DATA_2 regCOMPUTE_USER_DATA_2; -typedef union COMPUTE_USER_DATA_3 regCOMPUTE_USER_DATA_3; -typedef union COMPUTE_USER_DATA_4 regCOMPUTE_USER_DATA_4; -typedef union COMPUTE_USER_DATA_5 regCOMPUTE_USER_DATA_5; -typedef union COMPUTE_USER_DATA_6 regCOMPUTE_USER_DATA_6; -typedef union COMPUTE_USER_DATA_7 regCOMPUTE_USER_DATA_7; -typedef union COMPUTE_USER_DATA_8 regCOMPUTE_USER_DATA_8; -typedef union COMPUTE_USER_DATA_9 regCOMPUTE_USER_DATA_9; -typedef union COMPUTE_USER_DATA_10 regCOMPUTE_USER_DATA_10; -typedef union COMPUTE_USER_DATA_11 regCOMPUTE_USER_DATA_11; -typedef union COMPUTE_USER_DATA_12 regCOMPUTE_USER_DATA_12; -typedef union COMPUTE_USER_DATA_13 regCOMPUTE_USER_DATA_13; -typedef union COMPUTE_USER_DATA_14 regCOMPUTE_USER_DATA_14; -typedef union COMPUTE_USER_DATA_15 regCOMPUTE_USER_DATA_15; -typedef union COMPUTE_NOWHERE regCOMPUTE_NOWHERE; -typedef union CSPRIV_CONNECT regCSPRIV_CONNECT; -typedef union CSPRIV_CONNECT2 regCSPRIV_CONNECT2; -typedef union CSPRIV_THREAD_TRACE_TG0 regCSPRIV_THREAD_TRACE_TG0; -typedef union CSPRIV_THREAD_TRACE_TG1 regCSPRIV_THREAD_TRACE_TG1; -typedef union CSPRIV_THREAD_TRACE_TG2 regCSPRIV_THREAD_TRACE_TG2; -typedef union CSPRIV_THREAD_TRACE_TG3 regCSPRIV_THREAD_TRACE_TG3; -typedef union CSPRIV_THREAD_TRACE_EVENT regCSPRIV_THREAD_TRACE_EVENT; -typedef union VGT_DMA_PRIMITIVE_TYPE regVGT_DMA_PRIMITIVE_TYPE; -typedef union VGT_DMA_CONTROL regVGT_DMA_CONTROL; -typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; -typedef union VGT_DMA_DATA_FIFO_DEPTH regVGT_DMA_DATA_FIFO_DEPTH; -typedef union VGT_DMA_REQ_FIFO_DEPTH regVGT_DMA_REQ_FIFO_DEPTH; -typedef union VGT_DRAW_INIT_FIFO_DEPTH regVGT_DRAW_INIT_FIFO_DEPTH; -typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; -typedef union CC_GC_SHADER_ARRAY_CONFIG regCC_GC_SHADER_ARRAY_CONFIG; -typedef union GC_USER_SHADER_ARRAY_CONFIG regGC_USER_SHADER_ARRAY_CONFIG; -typedef union VGT_CACHE_INVALIDATION regVGT_CACHE_INVALIDATION; -typedef union VGT_RESET_DEBUG regVGT_RESET_DEBUG; -typedef union VGT_STRMOUT_DELAY regVGT_STRMOUT_DELAY; -typedef union VGT_FIFO_DEPTHS regVGT_FIFO_DEPTHS; -typedef union VGT_GS_VERTEX_REUSE regVGT_GS_VERTEX_REUSE; -typedef union VGT_MC_LAT_CNTL regVGT_MC_LAT_CNTL; -typedef union IA_CNTL_STATUS regIA_CNTL_STATUS; -typedef union VGT_DMA_LS_HS_CONFIG regVGT_DMA_LS_HS_CONFIG; -typedef union VGT_SYS_CONFIG regVGT_SYS_CONFIG; -typedef union WD_BUF_RESOURCE_1 regWD_BUF_RESOURCE_1; -typedef union WD_BUF_RESOURCE_2 regWD_BUF_RESOURCE_2; -typedef union VGT_VS_MAX_WAVE_ID regVGT_VS_MAX_WAVE_ID; -typedef union VGT_GS_MAX_WAVE_ID regVGT_GS_MAX_WAVE_ID; -typedef union WD_CNTL_STATUS regWD_CNTL_STATUS; -typedef union GFX_PIPE_CONTROL regGFX_PIPE_CONTROL; -typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; -typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; -typedef union IA_DEBUG_CNTL regIA_DEBUG_CNTL; -typedef union IA_DEBUG_DATA regIA_DEBUG_DATA; -typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; -typedef union WD_DEBUG_CNTL regWD_DEBUG_CNTL; -typedef union WD_DEBUG_DATA regWD_DEBUG_DATA; -typedef union WD_QOS regWD_QOS; -typedef union WD_UTCL1_CNTL regWD_UTCL1_CNTL; -typedef union WD_UTCL1_STATUS regWD_UTCL1_STATUS; -typedef union IA_UTCL1_CNTL regIA_UTCL1_CNTL; -typedef union IA_UTCL1_STATUS regIA_UTCL1_STATUS; -typedef union CC_GC_PRIM_CONFIG regCC_GC_PRIM_CONFIG; -typedef union GC_USER_PRIM_CONFIG regGC_USER_PRIM_CONFIG; -typedef union CS_COPY_STATE regCS_COPY_STATE; -typedef union GFX_COPY_STATE regGFX_COPY_STATE; -typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; -typedef union VGT_DRAW_PAYLOAD_CNTL regVGT_DRAW_PAYLOAD_CNTL; -typedef union VGT_INDEX_PAYLOAD_CNTL regVGT_INDEX_PAYLOAD_CNTL; -typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; -typedef union VGT_DMA_EVENT_INITIATOR regVGT_DMA_EVENT_INITIATOR; -typedef union VGT_EVENT_ADDRESS_REG regVGT_EVENT_ADDRESS_REG; -typedef union VGT_GS_MAX_PRIMS_PER_SUBGROUP regVGT_GS_MAX_PRIMS_PER_SUBGROUP; -typedef union VGT_DMA_BASE_HI regVGT_DMA_BASE_HI; -typedef union VGT_DMA_BASE regVGT_DMA_BASE; -typedef union VGT_DMA_INDEX_TYPE regVGT_DMA_INDEX_TYPE; -typedef union VGT_DMA_NUM_INSTANCES regVGT_DMA_NUM_INSTANCES; -typedef union IA_ENHANCE regIA_ENHANCE; -typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; -typedef union VGT_DMA_MAX_SIZE regVGT_DMA_MAX_SIZE; -typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; -typedef union VGT_PRIMITIVEID_EN regVGT_PRIMITIVEID_EN; -typedef union VGT_PRIMITIVEID_RESET regVGT_PRIMITIVEID_RESET; -typedef union VGT_VTX_CNT_EN regVGT_VTX_CNT_EN; -typedef union VGT_REUSE_OFF regVGT_REUSE_OFF; -typedef union VGT_INSTANCE_STEP_RATE_0 regVGT_INSTANCE_STEP_RATE_0; -typedef union VGT_INSTANCE_STEP_RATE_1 regVGT_INSTANCE_STEP_RATE_1; -typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; -typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; -typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; -typedef union VGT_ENHANCE regVGT_ENHANCE; -typedef union VGT_OUTPUT_PATH_CNTL regVGT_OUTPUT_PATH_CNTL; -typedef union VGT_HOS_CNTL regVGT_HOS_CNTL; -typedef union VGT_HOS_MAX_TESS_LEVEL regVGT_HOS_MAX_TESS_LEVEL; -typedef union VGT_HOS_MIN_TESS_LEVEL regVGT_HOS_MIN_TESS_LEVEL; -typedef union VGT_HOS_REUSE_DEPTH regVGT_HOS_REUSE_DEPTH; -typedef union VGT_GROUP_PRIM_TYPE regVGT_GROUP_PRIM_TYPE; -typedef union VGT_GROUP_FIRST_DECR regVGT_GROUP_FIRST_DECR; -typedef union VGT_GROUP_DECR regVGT_GROUP_DECR; -typedef union VGT_GROUP_VECT_0_CNTL regVGT_GROUP_VECT_0_CNTL; -typedef union VGT_GROUP_VECT_1_CNTL regVGT_GROUP_VECT_1_CNTL; -typedef union VGT_GROUP_VECT_0_FMT_CNTL regVGT_GROUP_VECT_0_FMT_CNTL; -typedef union VGT_GROUP_VECT_1_FMT_CNTL regVGT_GROUP_VECT_1_FMT_CNTL; -typedef union VGT_GS_MODE regVGT_GS_MODE; -typedef union VGT_GS_ONCHIP_CNTL regVGT_GS_ONCHIP_CNTL; -typedef union VGT_GS_OUT_PRIM_TYPE regVGT_GS_OUT_PRIM_TYPE; -typedef union VGT_GS_PER_ES regVGT_GS_PER_ES; -typedef union VGT_ES_PER_GS regVGT_ES_PER_GS; -typedef union VGT_GS_PER_VS regVGT_GS_PER_VS; -typedef union VGT_STRMOUT_CONFIG regVGT_STRMOUT_CONFIG; -typedef union VGT_STRMOUT_BUFFER_SIZE_0 regVGT_STRMOUT_BUFFER_SIZE_0; -typedef union VGT_STRMOUT_BUFFER_SIZE_1 regVGT_STRMOUT_BUFFER_SIZE_1; -typedef union VGT_STRMOUT_BUFFER_SIZE_2 regVGT_STRMOUT_BUFFER_SIZE_2; -typedef union VGT_STRMOUT_BUFFER_SIZE_3 regVGT_STRMOUT_BUFFER_SIZE_3; -typedef union VGT_STRMOUT_BUFFER_OFFSET_0 regVGT_STRMOUT_BUFFER_OFFSET_0; -typedef union VGT_STRMOUT_BUFFER_OFFSET_1 regVGT_STRMOUT_BUFFER_OFFSET_1; -typedef union VGT_STRMOUT_BUFFER_OFFSET_2 regVGT_STRMOUT_BUFFER_OFFSET_2; -typedef union VGT_STRMOUT_BUFFER_OFFSET_3 regVGT_STRMOUT_BUFFER_OFFSET_3; -typedef union VGT_STRMOUT_VTX_STRIDE_0 regVGT_STRMOUT_VTX_STRIDE_0; -typedef union VGT_STRMOUT_VTX_STRIDE_1 regVGT_STRMOUT_VTX_STRIDE_1; -typedef union VGT_STRMOUT_VTX_STRIDE_2 regVGT_STRMOUT_VTX_STRIDE_2; -typedef union VGT_STRMOUT_VTX_STRIDE_3 regVGT_STRMOUT_VTX_STRIDE_3; -typedef union VGT_STRMOUT_BUFFER_CONFIG regVGT_STRMOUT_BUFFER_CONFIG; -typedef union VGT_STRMOUT_DRAW_OPAQUE_OFFSET regVGT_STRMOUT_DRAW_OPAQUE_OFFSET; -typedef union VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE - regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE; -typedef union VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE; -typedef union VGT_GS_MAX_VERT_OUT regVGT_GS_MAX_VERT_OUT; -typedef union VGT_SHADER_STAGES_EN regVGT_SHADER_STAGES_EN; -typedef union VGT_DISPATCH_DRAW_INDEX regVGT_DISPATCH_DRAW_INDEX; -typedef union VGT_LS_HS_CONFIG regVGT_LS_HS_CONFIG; -typedef union VGT_TF_PARAM regVGT_TF_PARAM; -typedef union VGT_TESS_DISTRIBUTION regVGT_TESS_DISTRIBUTION; -typedef union VGT_GS_INSTANCE_CNT regVGT_GS_INSTANCE_CNT; -typedef union VGT_GSVS_RING_OFFSET_1 regVGT_GSVS_RING_OFFSET_1; -typedef union VGT_GSVS_RING_OFFSET_2 regVGT_GSVS_RING_OFFSET_2; -typedef union VGT_GSVS_RING_OFFSET_3 regVGT_GSVS_RING_OFFSET_3; -typedef union VGT_ESGS_RING_ITEMSIZE regVGT_ESGS_RING_ITEMSIZE; -typedef union VGT_GSVS_RING_ITEMSIZE regVGT_GSVS_RING_ITEMSIZE; -typedef union VGT_GS_VERT_ITEMSIZE regVGT_GS_VERT_ITEMSIZE; -typedef union VGT_GS_VERT_ITEMSIZE_1 regVGT_GS_VERT_ITEMSIZE_1; -typedef union VGT_GS_VERT_ITEMSIZE_2 regVGT_GS_VERT_ITEMSIZE_2; -typedef union VGT_GS_VERT_ITEMSIZE_3 regVGT_GS_VERT_ITEMSIZE_3; -typedef union WD_ENHANCE regWD_ENHANCE; -typedef union VGT_OBJECT_ID regVGT_OBJECT_ID; -typedef union VGT_INDEX_TYPE regVGT_INDEX_TYPE; -typedef union VGT_NUM_INDICES regVGT_NUM_INDICES; -typedef union VGT_NUM_INSTANCES regVGT_NUM_INSTANCES; -typedef union VGT_PRIMITIVE_TYPE regVGT_PRIMITIVE_TYPE; -typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; -typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; -typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; -typedef union VGT_MULTI_PRIM_IB_RESET_EN regVGT_MULTI_PRIM_IB_RESET_EN; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_0 regVGT_STRMOUT_BUFFER_FILLED_SIZE_0; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_1 regVGT_STRMOUT_BUFFER_FILLED_SIZE_1; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_2 regVGT_STRMOUT_BUFFER_FILLED_SIZE_2; -typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_3 regVGT_STRMOUT_BUFFER_FILLED_SIZE_3; -typedef union VGT_TF_RING_SIZE regVGT_TF_RING_SIZE; -typedef union VGT_HS_OFFCHIP_PARAM regVGT_HS_OFFCHIP_PARAM; -typedef union VGT_TF_MEMORY_BASE regVGT_TF_MEMORY_BASE; -typedef union VGT_TF_MEMORY_BASE_HI regVGT_TF_MEMORY_BASE_HI; -typedef union WD_POS_BUF_BASE regWD_POS_BUF_BASE; -typedef union WD_POS_BUF_BASE_HI regWD_POS_BUF_BASE_HI; -typedef union WD_CNTL_SB_BUF_BASE regWD_CNTL_SB_BUF_BASE; -typedef union WD_CNTL_SB_BUF_BASE_HI regWD_CNTL_SB_BUF_BASE_HI; -typedef union WD_INDEX_BUF_BASE regWD_INDEX_BUF_BASE; -typedef union WD_INDEX_BUF_BASE_HI regWD_INDEX_BUF_BASE_HI; -typedef union IA_MULTI_VGT_PARAM regIA_MULTI_VGT_PARAM; -typedef union VGT_GSVS_RING_SIZE regVGT_GSVS_RING_SIZE; -typedef union VGT_INSTANCE_BASE_ID regVGT_INSTANCE_BASE_ID; -typedef union VGT_PERFCOUNTER0_LO regVGT_PERFCOUNTER0_LO; -typedef union VGT_PERFCOUNTER1_LO regVGT_PERFCOUNTER1_LO; -typedef union VGT_PERFCOUNTER2_LO regVGT_PERFCOUNTER2_LO; -typedef union VGT_PERFCOUNTER3_LO regVGT_PERFCOUNTER3_LO; -typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; -typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; -typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; -typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; -typedef union IA_PERFCOUNTER0_LO regIA_PERFCOUNTER0_LO; -typedef union IA_PERFCOUNTER1_LO regIA_PERFCOUNTER1_LO; -typedef union IA_PERFCOUNTER2_LO regIA_PERFCOUNTER2_LO; -typedef union IA_PERFCOUNTER3_LO regIA_PERFCOUNTER3_LO; -typedef union IA_PERFCOUNTER0_HI regIA_PERFCOUNTER0_HI; -typedef union IA_PERFCOUNTER1_HI regIA_PERFCOUNTER1_HI; -typedef union IA_PERFCOUNTER2_HI regIA_PERFCOUNTER2_HI; -typedef union IA_PERFCOUNTER3_HI regIA_PERFCOUNTER3_HI; -typedef union WD_PERFCOUNTER0_LO regWD_PERFCOUNTER0_LO; -typedef union WD_PERFCOUNTER1_LO regWD_PERFCOUNTER1_LO; -typedef union WD_PERFCOUNTER2_LO regWD_PERFCOUNTER2_LO; -typedef union WD_PERFCOUNTER3_LO regWD_PERFCOUNTER3_LO; -typedef union WD_PERFCOUNTER0_HI regWD_PERFCOUNTER0_HI; -typedef union WD_PERFCOUNTER1_HI regWD_PERFCOUNTER1_HI; -typedef union WD_PERFCOUNTER2_HI regWD_PERFCOUNTER2_HI; -typedef union WD_PERFCOUNTER3_HI regWD_PERFCOUNTER3_HI; -typedef union VGT_PERFCOUNTER_SEID_MASK regVGT_PERFCOUNTER_SEID_MASK; -typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; -typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; -typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; -typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; -typedef union VGT_PERFCOUNTER0_SELECT1 regVGT_PERFCOUNTER0_SELECT1; -typedef union VGT_PERFCOUNTER1_SELECT1 regVGT_PERFCOUNTER1_SELECT1; -typedef union IA_PERFCOUNTER0_SELECT regIA_PERFCOUNTER0_SELECT; -typedef union IA_PERFCOUNTER1_SELECT regIA_PERFCOUNTER1_SELECT; -typedef union IA_PERFCOUNTER2_SELECT regIA_PERFCOUNTER2_SELECT; -typedef union IA_PERFCOUNTER3_SELECT regIA_PERFCOUNTER3_SELECT; -typedef union IA_PERFCOUNTER0_SELECT1 regIA_PERFCOUNTER0_SELECT1; -typedef union WD_PERFCOUNTER0_SELECT regWD_PERFCOUNTER0_SELECT; -typedef union WD_PERFCOUNTER1_SELECT regWD_PERFCOUNTER1_SELECT; -typedef union WD_PERFCOUNTER2_SELECT regWD_PERFCOUNTER2_SELECT; -typedef union WD_PERFCOUNTER3_SELECT regWD_PERFCOUNTER3_SELECT; -typedef union CGTT_VGT_CLK_CTRL regCGTT_VGT_CLK_CTRL; -typedef union CGTT_IA_CLK_CTRL regCGTT_IA_CLK_CTRL; -typedef union CGTT_WD_CLK_CTRL regCGTT_WD_CLK_CTRL; -typedef union VGT_DEBUG_REG0 regVGT_DEBUG_REG0; -typedef union VGT_DEBUG_REG1 regVGT_DEBUG_REG1; -typedef union VGT_DEBUG_REG2 regVGT_DEBUG_REG2; -typedef union VGT_DEBUG_REG3 regVGT_DEBUG_REG3; -typedef union VGT_DEBUG_REG4 regVGT_DEBUG_REG4; -typedef union VGT_DEBUG_REG5 regVGT_DEBUG_REG5; -typedef union VGT_DEBUG_REG6 regVGT_DEBUG_REG6; -typedef union VGT_DEBUG_REG7 regVGT_DEBUG_REG7; -typedef union VGT_DEBUG_REG8 regVGT_DEBUG_REG8; -typedef union VGT_DEBUG_REG9 regVGT_DEBUG_REG9; -typedef union VGT_DEBUG_REG10 regVGT_DEBUG_REG10; -typedef union VGT_DEBUG_REG11 regVGT_DEBUG_REG11; -typedef union VGT_DEBUG_REG12 regVGT_DEBUG_REG12; -typedef union VGT_DEBUG_REG13 regVGT_DEBUG_REG13; -typedef union VGT_DEBUG_REG14 regVGT_DEBUG_REG14; -typedef union VGT_DEBUG_REG15 regVGT_DEBUG_REG15; -typedef union VGT_DEBUG_REG16 regVGT_DEBUG_REG16; -typedef union VGT_DEBUG_REG17 regVGT_DEBUG_REG17; -typedef union VGT_DEBUG_REG18 regVGT_DEBUG_REG18; -typedef union VGT_DEBUG_REG19 regVGT_DEBUG_REG19; -typedef union VGT_DEBUG_REG20 regVGT_DEBUG_REG20; -typedef union VGT_DEBUG_REG21 regVGT_DEBUG_REG21; -typedef union VGT_DEBUG_REG22 regVGT_DEBUG_REG22; -typedef union VGT_DEBUG_REG23 regVGT_DEBUG_REG23; -typedef union VGT_DEBUG_REG24 regVGT_DEBUG_REG24; -typedef union VGT_DEBUG_REG25 regVGT_DEBUG_REG25; -typedef union VGT_DEBUG_REG26 regVGT_DEBUG_REG26; -typedef union VGT_DEBUG_REG27 regVGT_DEBUG_REG27; -typedef union VGT_DEBUG_REG28 regVGT_DEBUG_REG28; -typedef union VGT_DEBUG_REG29 regVGT_DEBUG_REG29; -typedef union VGT_DEBUG_REG30 regVGT_DEBUG_REG30; -typedef union VGT_DEBUG_REG31 regVGT_DEBUG_REG31; -typedef union VGT_DEBUG_REG32 regVGT_DEBUG_REG32; -typedef union VGT_DEBUG_REG33 regVGT_DEBUG_REG33; -typedef union VGT_DEBUG_REG34 regVGT_DEBUG_REG34; -typedef union VGT_DEBUG_REG36 regVGT_DEBUG_REG36; -typedef union IA_DEBUG_REG0 regIA_DEBUG_REG0; -typedef union IA_DEBUG_REG1 regIA_DEBUG_REG1; -typedef union IA_DEBUG_REG2 regIA_DEBUG_REG2; -typedef union IA_DEBUG_REG3 regIA_DEBUG_REG3; -typedef union IA_DEBUG_REG4 regIA_DEBUG_REG4; -typedef union IA_DEBUG_REG5 regIA_DEBUG_REG5; -typedef union IA_DEBUG_REG6 regIA_DEBUG_REG6; -typedef union IA_DEBUG_REG7 regIA_DEBUG_REG7; -typedef union IA_DEBUG_REG8 regIA_DEBUG_REG8; -typedef union IA_DEBUG_REG9 regIA_DEBUG_REG9; -typedef union WD_DEBUG_REG0 regWD_DEBUG_REG0; -typedef union WD_DEBUG_REG1 regWD_DEBUG_REG1; -typedef union WD_DEBUG_REG2 regWD_DEBUG_REG2; -typedef union WD_DEBUG_REG3 regWD_DEBUG_REG3; -typedef union WD_DEBUG_REG4 regWD_DEBUG_REG4; -typedef union WD_DEBUG_REG5 regWD_DEBUG_REG5; -typedef union WD_DEBUG_REG6 regWD_DEBUG_REG6; -typedef union WD_DEBUG_REG7 regWD_DEBUG_REG7; -typedef union WD_DEBUG_REG8 regWD_DEBUG_REG8; -typedef union WD_DEBUG_REG9 regWD_DEBUG_REG9; -typedef union WD_DEBUG_REG10 regWD_DEBUG_REG10; -typedef union WD_DEBUG_REG11 regWD_DEBUG_REG11; -typedef union WD_DEBUG_REG12 regWD_DEBUG_REG12; -typedef union WD_DEBUG_REG13 regWD_DEBUG_REG13; -typedef union CC_RB_REDUNDANCY regCC_RB_REDUNDANCY; -typedef union CC_RB_BACKEND_DISABLE regCC_RB_BACKEND_DISABLE; -typedef union GC_USER_RB_REDUNDANCY regGC_USER_RB_REDUNDANCY; -typedef union GC_USER_RB_BACKEND_DISABLE regGC_USER_RB_BACKEND_DISABLE; -typedef union GB_ADDR_CONFIG regGB_ADDR_CONFIG; -typedef union GB_ADDR_CONFIG_READ regGB_ADDR_CONFIG_READ; -typedef union GB_BACKEND_MAP regGB_BACKEND_MAP; -typedef union GB_GPU_ID regGB_GPU_ID; -typedef union CC_RB_DAISY_CHAIN regCC_RB_DAISY_CHAIN; -typedef union GB_TILE_MODE0 regGB_TILE_MODE0; -typedef union GB_TILE_MODE1 regGB_TILE_MODE1; -typedef union GB_TILE_MODE2 regGB_TILE_MODE2; -typedef union GB_TILE_MODE3 regGB_TILE_MODE3; -typedef union GB_TILE_MODE4 regGB_TILE_MODE4; -typedef union GB_TILE_MODE5 regGB_TILE_MODE5; -typedef union GB_TILE_MODE6 regGB_TILE_MODE6; -typedef union GB_TILE_MODE7 regGB_TILE_MODE7; -typedef union GB_TILE_MODE8 regGB_TILE_MODE8; -typedef union GB_TILE_MODE9 regGB_TILE_MODE9; -typedef union GB_TILE_MODE10 regGB_TILE_MODE10; -typedef union GB_TILE_MODE11 regGB_TILE_MODE11; -typedef union GB_TILE_MODE12 regGB_TILE_MODE12; -typedef union GB_TILE_MODE13 regGB_TILE_MODE13; -typedef union GB_TILE_MODE14 regGB_TILE_MODE14; -typedef union GB_TILE_MODE15 regGB_TILE_MODE15; -typedef union GB_TILE_MODE16 regGB_TILE_MODE16; -typedef union GB_TILE_MODE17 regGB_TILE_MODE17; -typedef union GB_TILE_MODE18 regGB_TILE_MODE18; -typedef union GB_TILE_MODE19 regGB_TILE_MODE19; -typedef union GB_TILE_MODE20 regGB_TILE_MODE20; -typedef union GB_TILE_MODE21 regGB_TILE_MODE21; -typedef union GB_TILE_MODE22 regGB_TILE_MODE22; -typedef union GB_TILE_MODE23 regGB_TILE_MODE23; -typedef union GB_TILE_MODE24 regGB_TILE_MODE24; -typedef union GB_TILE_MODE25 regGB_TILE_MODE25; -typedef union GB_TILE_MODE26 regGB_TILE_MODE26; -typedef union GB_TILE_MODE27 regGB_TILE_MODE27; -typedef union GB_TILE_MODE28 regGB_TILE_MODE28; -typedef union GB_TILE_MODE29 regGB_TILE_MODE29; -typedef union GB_TILE_MODE30 regGB_TILE_MODE30; -typedef union GB_TILE_MODE31 regGB_TILE_MODE31; -typedef union GB_MACROTILE_MODE0 regGB_MACROTILE_MODE0; -typedef union GB_MACROTILE_MODE1 regGB_MACROTILE_MODE1; -typedef union GB_MACROTILE_MODE2 regGB_MACROTILE_MODE2; -typedef union GB_MACROTILE_MODE3 regGB_MACROTILE_MODE3; -typedef union GB_MACROTILE_MODE4 regGB_MACROTILE_MODE4; -typedef union GB_MACROTILE_MODE5 regGB_MACROTILE_MODE5; -typedef union GB_MACROTILE_MODE6 regGB_MACROTILE_MODE6; -typedef union GB_MACROTILE_MODE7 regGB_MACROTILE_MODE7; -typedef union GB_MACROTILE_MODE8 regGB_MACROTILE_MODE8; -typedef union GB_MACROTILE_MODE9 regGB_MACROTILE_MODE9; -typedef union GB_MACROTILE_MODE10 regGB_MACROTILE_MODE10; -typedef union GB_MACROTILE_MODE11 regGB_MACROTILE_MODE11; -typedef union GB_MACROTILE_MODE12 regGB_MACROTILE_MODE12; -typedef union GB_MACROTILE_MODE13 regGB_MACROTILE_MODE13; -typedef union GB_MACROTILE_MODE14 regGB_MACROTILE_MODE14; -typedef union GB_MACROTILE_MODE15 regGB_MACROTILE_MODE15; -typedef union GB_EDC_MODE regGB_EDC_MODE; -typedef union CC_GC_EDC_CONFIG regCC_GC_EDC_CONFIG; -typedef union RAS_SIGNATURE_CONTROL regRAS_SIGNATURE_CONTROL; -typedef union RAS_SIGNATURE_MASK regRAS_SIGNATURE_MASK; -typedef union RAS_SX_SIGNATURE0 regRAS_SX_SIGNATURE0; -typedef union RAS_SX_SIGNATURE1 regRAS_SX_SIGNATURE1; -typedef union RAS_SX_SIGNATURE2 regRAS_SX_SIGNATURE2; -typedef union RAS_SX_SIGNATURE3 regRAS_SX_SIGNATURE3; -typedef union RAS_DB_SIGNATURE0 regRAS_DB_SIGNATURE0; -typedef union RAS_PA_SIGNATURE0 regRAS_PA_SIGNATURE0; -typedef union RAS_VGT_SIGNATURE0 regRAS_VGT_SIGNATURE0; -typedef union RAS_SQ_SIGNATURE0 regRAS_SQ_SIGNATURE0; -typedef union RAS_SC_SIGNATURE0 regRAS_SC_SIGNATURE0; -typedef union RAS_SC_SIGNATURE1 regRAS_SC_SIGNATURE1; -typedef union RAS_SC_SIGNATURE2 regRAS_SC_SIGNATURE2; -typedef union RAS_SC_SIGNATURE3 regRAS_SC_SIGNATURE3; -typedef union RAS_SC_SIGNATURE4 regRAS_SC_SIGNATURE4; -typedef union RAS_SC_SIGNATURE5 regRAS_SC_SIGNATURE5; -typedef union RAS_SC_SIGNATURE6 regRAS_SC_SIGNATURE6; -typedef union RAS_SC_SIGNATURE7 regRAS_SC_SIGNATURE7; -typedef union RAS_IA_SIGNATURE0 regRAS_IA_SIGNATURE0; -typedef union RAS_IA_SIGNATURE1 regRAS_IA_SIGNATURE1; -typedef union RAS_SPI_SIGNATURE0 regRAS_SPI_SIGNATURE0; -typedef union RAS_SPI_SIGNATURE1 regRAS_SPI_SIGNATURE1; -typedef union RAS_TA_SIGNATURE0 regRAS_TA_SIGNATURE0; -typedef union RAS_TD_SIGNATURE0 regRAS_TD_SIGNATURE0; -typedef union RAS_CB_SIGNATURE0 regRAS_CB_SIGNATURE0; -typedef union RAS_BCI_SIGNATURE0 regRAS_BCI_SIGNATURE0; -typedef union RAS_BCI_SIGNATURE1 regRAS_BCI_SIGNATURE1; -typedef union RAS_TA_SIGNATURE1 regRAS_TA_SIGNATURE1; -typedef union TD_CNTL regTD_CNTL; -typedef union TD_STATUS regTD_STATUS; -typedef union TD_DEBUG_INDEX regTD_DEBUG_INDEX; -typedef union TD_DEBUG_DATA regTD_DEBUG_DATA; -typedef union TD_DSM_CNTL regTD_DSM_CNTL; -typedef union TD_DSM_CNTL2 regTD_DSM_CNTL2; -typedef union TD_SCRATCH regTD_SCRATCH; -typedef union TA_CNTL regTA_CNTL; -typedef union TA_CNTL_AUX regTA_CNTL_AUX; -typedef union TA_RESERVED_010C regTA_RESERVED_010C; -typedef union TA_GRAD_ADJ regTA_GRAD_ADJ; -typedef union TA_STATUS regTA_STATUS; -typedef union TA_DEBUG_INDEX regTA_DEBUG_INDEX; -typedef union TA_DEBUG_DATA regTA_DEBUG_DATA; -typedef union TA_SCRATCH regTA_SCRATCH; -typedef union TCP_INVALIDATE regTCP_INVALIDATE; -typedef union TCP_STATUS regTCP_STATUS; -typedef union TCP_CNTL regTCP_CNTL; -typedef union TCP_CHAN_STEER_LO regTCP_CHAN_STEER_LO; -typedef union TCP_CHAN_STEER_HI regTCP_CHAN_STEER_HI; -typedef union TCP_ADDR_CONFIG regTCP_ADDR_CONFIG; -typedef union TCP_CREDIT regTCP_CREDIT; -typedef union TCP_DEBUG_INDEX regTCP_DEBUG_INDEX; -typedef union TCP_DEBUG_DATA regTCP_DEBUG_DATA; -typedef union TCP_BUFFER_ADDR_HASH_CNTL regTCP_BUFFER_ADDR_HASH_CNTL; -typedef union TCP_EDC_CNT regTCP_EDC_CNT; -typedef union TC_CFG_L1_LOAD_POLICY0 regTC_CFG_L1_LOAD_POLICY0; -typedef union TC_CFG_L1_LOAD_POLICY1 regTC_CFG_L1_LOAD_POLICY1; -typedef union TC_CFG_L1_STORE_POLICY regTC_CFG_L1_STORE_POLICY; -typedef union TC_CFG_L2_LOAD_POLICY0 regTC_CFG_L2_LOAD_POLICY0; -typedef union TC_CFG_L2_LOAD_POLICY1 regTC_CFG_L2_LOAD_POLICY1; -typedef union TC_CFG_L2_STORE_POLICY0 regTC_CFG_L2_STORE_POLICY0; -typedef union TC_CFG_L2_STORE_POLICY1 regTC_CFG_L2_STORE_POLICY1; -typedef union TC_CFG_L2_ATOMIC_POLICY regTC_CFG_L2_ATOMIC_POLICY; -typedef union TC_CFG_L1_VOLATILE regTC_CFG_L1_VOLATILE; -typedef union TC_CFG_L2_VOLATILE regTC_CFG_L2_VOLATILE; -typedef union TCI_STATUS regTCI_STATUS; -typedef union TCI_CNTL_1 regTCI_CNTL_1; -typedef union TCI_CNTL_2 regTCI_CNTL_2; -typedef union TCP_WATCH0_ADDR_H regTCP_WATCH0_ADDR_H; -typedef union TCP_WATCH1_ADDR_H regTCP_WATCH1_ADDR_H; -typedef union TCP_WATCH2_ADDR_H regTCP_WATCH2_ADDR_H; -typedef union TCP_WATCH3_ADDR_H regTCP_WATCH3_ADDR_H; -typedef union TCP_WATCH0_ADDR_L regTCP_WATCH0_ADDR_L; -typedef union TCP_WATCH1_ADDR_L regTCP_WATCH1_ADDR_L; -typedef union TCP_WATCH2_ADDR_L regTCP_WATCH2_ADDR_L; -typedef union TCP_WATCH3_ADDR_L regTCP_WATCH3_ADDR_L; -typedef union TCP_WATCH0_CNTL regTCP_WATCH0_CNTL; -typedef union TCP_WATCH1_CNTL regTCP_WATCH1_CNTL; -typedef union TCP_WATCH2_CNTL regTCP_WATCH2_CNTL; -typedef union TCP_WATCH3_CNTL regTCP_WATCH3_CNTL; -typedef union TCP_GATCL1_CNTL regTCP_GATCL1_CNTL; -typedef union TCP_ATC_EDC_GATCL1_CNT regTCP_ATC_EDC_GATCL1_CNT; -typedef union TCP_GATCL1_DSM_CNTL regTCP_GATCL1_DSM_CNTL; -typedef union TCP_CNTL2 regTCP_CNTL2; -typedef union TCP_UTCL1_CNTL1 regTCP_UTCL1_CNTL1; -typedef union TCP_UTCL1_CNTL2 regTCP_UTCL1_CNTL2; -typedef union TCP_UTCL1_STATUS regTCP_UTCL1_STATUS; -typedef union TCP_PERFCOUNTER_FILTER regTCP_PERFCOUNTER_FILTER; -typedef union TCP_PERFCOUNTER_FILTER_EN regTCP_PERFCOUNTER_FILTER_EN; -typedef union TA_BC_BASE_ADDR regTA_BC_BASE_ADDR; -typedef union TA_BC_BASE_ADDR_HI regTA_BC_BASE_ADDR_HI; -typedef union TA_CS_BC_BASE_ADDR regTA_CS_BC_BASE_ADDR; -typedef union TA_CS_BC_BASE_ADDR_HI regTA_CS_BC_BASE_ADDR_HI; -typedef union TA_GRAD_ADJ_UCONFIG regTA_GRAD_ADJ_UCONFIG; -typedef union TD_PERFCOUNTER0_LO regTD_PERFCOUNTER0_LO; -typedef union TD_PERFCOUNTER1_LO regTD_PERFCOUNTER1_LO; -typedef union TD_PERFCOUNTER0_HI regTD_PERFCOUNTER0_HI; -typedef union TD_PERFCOUNTER1_HI regTD_PERFCOUNTER1_HI; -typedef union TA_PERFCOUNTER0_LO regTA_PERFCOUNTER0_LO; -typedef union TA_PERFCOUNTER1_LO regTA_PERFCOUNTER1_LO; -typedef union TA_PERFCOUNTER0_HI regTA_PERFCOUNTER0_HI; -typedef union TA_PERFCOUNTER1_HI regTA_PERFCOUNTER1_HI; -typedef union TCP_PERFCOUNTER0_LO regTCP_PERFCOUNTER0_LO; -typedef union TCP_PERFCOUNTER1_LO regTCP_PERFCOUNTER1_LO; -typedef union TCP_PERFCOUNTER2_LO regTCP_PERFCOUNTER2_LO; -typedef union TCP_PERFCOUNTER3_LO regTCP_PERFCOUNTER3_LO; -typedef union TCP_PERFCOUNTER0_HI regTCP_PERFCOUNTER0_HI; -typedef union TCP_PERFCOUNTER1_HI regTCP_PERFCOUNTER1_HI; -typedef union TCP_PERFCOUNTER2_HI regTCP_PERFCOUNTER2_HI; -typedef union TCP_PERFCOUNTER3_HI regTCP_PERFCOUNTER3_HI; -typedef union TD_PERFCOUNTER0_SELECT regTD_PERFCOUNTER0_SELECT; -typedef union TD_PERFCOUNTER1_SELECT regTD_PERFCOUNTER1_SELECT; -typedef union TD_PERFCOUNTER0_SELECT1 regTD_PERFCOUNTER0_SELECT1; -typedef union TA_PERFCOUNTER0_SELECT regTA_PERFCOUNTER0_SELECT; -typedef union TA_PERFCOUNTER1_SELECT regTA_PERFCOUNTER1_SELECT; -typedef union TA_PERFCOUNTER0_SELECT1 regTA_PERFCOUNTER0_SELECT1; -typedef union TCP_PERFCOUNTER0_SELECT regTCP_PERFCOUNTER0_SELECT; -typedef union TCP_PERFCOUNTER1_SELECT regTCP_PERFCOUNTER1_SELECT; -typedef union TCP_PERFCOUNTER0_SELECT1 regTCP_PERFCOUNTER0_SELECT1; -typedef union TCP_PERFCOUNTER1_SELECT1 regTCP_PERFCOUNTER1_SELECT1; -typedef union TCP_PERFCOUNTER2_SELECT regTCP_PERFCOUNTER2_SELECT; -typedef union TCP_PERFCOUNTER3_SELECT regTCP_PERFCOUNTER3_SELECT; -typedef union TD_CGTT_CTRL regTD_CGTT_CTRL; -typedef union TA_CGTT_CTRL regTA_CGTT_CTRL; -typedef union CGTT_TCPI_CLK_CTRL regCGTT_TCPI_CLK_CTRL; -typedef union CGTT_TCPF_CLK_CTRL regCGTT_TCPF_CLK_CTRL; -typedef union CGTT_TCI_CLK_CTRL regCGTT_TCI_CLK_CTRL; -typedef union TCC_CTRL regTCC_CTRL; -typedef union TCC_CTRL2 regTCC_CTRL2; -typedef union TCC_EDC_CNT regTCC_EDC_CNT; -typedef union TCC_EDC_CNT2 regTCC_EDC_CNT2; -typedef union TCC_REDUNDANCY regTCC_REDUNDANCY; -typedef union TCC_EXE_DISABLE regTCC_EXE_DISABLE; -typedef union TCC_DSM_CNTL regTCC_DSM_CNTL; -typedef union TCC_DSM_CNTLA regTCC_DSM_CNTLA; -typedef union TCC_DSM_CNTL2 regTCC_DSM_CNTL2; -typedef union TCC_DSM_CNTL2A regTCC_DSM_CNTL2A; -typedef union TCC_DSM_CNTL2B regTCC_DSM_CNTL2B; -typedef union TCC_WBINVL2 regTCC_WBINVL2; -typedef union TCC_SOFT_RESET regTCC_SOFT_RESET; -typedef union TCA_CTRL regTCA_CTRL; -typedef union TCA_BURST_MASK regTCA_BURST_MASK; -typedef union TCA_BURST_CTRL regTCA_BURST_CTRL; -typedef union TCA_DSM_CNTL regTCA_DSM_CNTL; -typedef union TCA_DSM_CNTL2 regTCA_DSM_CNTL2; -typedef union TCA_EDC_CNT regTCA_EDC_CNT; -typedef union TCC_PERFCOUNTER0_LO regTCC_PERFCOUNTER0_LO; -typedef union TCC_PERFCOUNTER1_LO regTCC_PERFCOUNTER1_LO; -typedef union TCC_PERFCOUNTER2_LO regTCC_PERFCOUNTER2_LO; -typedef union TCC_PERFCOUNTER3_LO regTCC_PERFCOUNTER3_LO; -typedef union TCC_PERFCOUNTER0_HI regTCC_PERFCOUNTER0_HI; -typedef union TCC_PERFCOUNTER1_HI regTCC_PERFCOUNTER1_HI; -typedef union TCC_PERFCOUNTER2_HI regTCC_PERFCOUNTER2_HI; -typedef union TCC_PERFCOUNTER3_HI regTCC_PERFCOUNTER3_HI; -typedef union TCA_PERFCOUNTER0_LO regTCA_PERFCOUNTER0_LO; -typedef union TCA_PERFCOUNTER1_LO regTCA_PERFCOUNTER1_LO; -typedef union TCA_PERFCOUNTER2_LO regTCA_PERFCOUNTER2_LO; -typedef union TCA_PERFCOUNTER3_LO regTCA_PERFCOUNTER3_LO; -typedef union TCA_PERFCOUNTER0_HI regTCA_PERFCOUNTER0_HI; -typedef union TCA_PERFCOUNTER1_HI regTCA_PERFCOUNTER1_HI; -typedef union TCA_PERFCOUNTER2_HI regTCA_PERFCOUNTER2_HI; -typedef union TCA_PERFCOUNTER3_HI regTCA_PERFCOUNTER3_HI; -typedef union TCC_PERFCOUNTER0_SELECT regTCC_PERFCOUNTER0_SELECT; -typedef union TCC_PERFCOUNTER1_SELECT regTCC_PERFCOUNTER1_SELECT; -typedef union TCC_PERFCOUNTER0_SELECT1 regTCC_PERFCOUNTER0_SELECT1; -typedef union TCC_PERFCOUNTER1_SELECT1 regTCC_PERFCOUNTER1_SELECT1; -typedef union TCC_PERFCOUNTER2_SELECT regTCC_PERFCOUNTER2_SELECT; -typedef union TCC_PERFCOUNTER3_SELECT regTCC_PERFCOUNTER3_SELECT; -typedef union TCA_PERFCOUNTER0_SELECT regTCA_PERFCOUNTER0_SELECT; -typedef union TCA_PERFCOUNTER1_SELECT regTCA_PERFCOUNTER1_SELECT; -typedef union TCA_PERFCOUNTER0_SELECT1 regTCA_PERFCOUNTER0_SELECT1; -typedef union TCA_PERFCOUNTER1_SELECT1 regTCA_PERFCOUNTER1_SELECT1; -typedef union TCA_PERFCOUNTER2_SELECT regTCA_PERFCOUNTER2_SELECT; -typedef union TCA_PERFCOUNTER3_SELECT regTCA_PERFCOUNTER3_SELECT; -typedef union TCC_CGTT_SCLK_CTRL regTCC_CGTT_SCLK_CTRL; -typedef union TCA_CGTT_SCLK_CTRL regTCA_CGTT_SCLK_CTRL; -typedef union GRBM_CNTL regGRBM_CNTL; -typedef union GRBM_SKEW_CNTL regGRBM_SKEW_CNTL; -typedef union GRBM_PWR_CNTL regGRBM_PWR_CNTL; -typedef union GRBM_STATUS regGRBM_STATUS; -typedef union GRBM_STATUS2 regGRBM_STATUS2; -typedef union GRBM_STATUS_SE0 regGRBM_STATUS_SE0; -typedef union GRBM_STATUS_SE1 regGRBM_STATUS_SE1; -typedef union GRBM_STATUS_SE2 regGRBM_STATUS_SE2; -typedef union GRBM_STATUS_SE3 regGRBM_STATUS_SE3; -typedef union GRBM_SOFT_RESET regGRBM_SOFT_RESET; -typedef union GRBM_DEBUG_CNTL regGRBM_DEBUG_CNTL; -typedef union GRBM_DEBUG_DATA regGRBM_DEBUG_DATA; -typedef union GRBM_CGTT_CLK_CNTL regGRBM_CGTT_CLK_CNTL; -typedef union GRBM_GFX_CLKEN_CNTL regGRBM_GFX_CLKEN_CNTL; -typedef union GRBM_WAIT_IDLE_CLOCKS regGRBM_WAIT_IDLE_CLOCKS; -typedef union GRBM_DEBUG regGRBM_DEBUG; -typedef union GRBM_DEBUG_SNAPSHOT regGRBM_DEBUG_SNAPSHOT; -typedef union GRBM_RSMU_READ_ERROR regGRBM_RSMU_READ_ERROR; -typedef union GRBM_CHICKEN_BITS regGRBM_CHICKEN_BITS; -typedef union GRBM_READ_ERROR regGRBM_READ_ERROR; -typedef union GRBM_READ_ERROR2 regGRBM_READ_ERROR2; -typedef union GRBM_INT_CNTL regGRBM_INT_CNTL; -typedef union GRBM_TRAP_OP regGRBM_TRAP_OP; -typedef union GRBM_TRAP_ADDR regGRBM_TRAP_ADDR; -typedef union GRBM_TRAP_ADDR_MSK regGRBM_TRAP_ADDR_MSK; -typedef union GRBM_TRAP_WD regGRBM_TRAP_WD; -typedef union GRBM_TRAP_WD_MSK regGRBM_TRAP_WD_MSK; -typedef union GRBM_DSM_BYPASS regGRBM_DSM_BYPASS; -typedef union GRBM_IOV_ERROR regGRBM_IOV_ERROR; -typedef union GRBM_WRITE_ERROR regGRBM_WRITE_ERROR; -typedef union GRBM_GFX_CNTL regGRBM_GFX_CNTL; -typedef union GRBM_RSMU_CFG regGRBM_RSMU_CFG; -typedef union GRBM_IH_CREDIT regGRBM_IH_CREDIT; -typedef union GRBM_PWR_CNTL2 regGRBM_PWR_CNTL2; -typedef union GRBM_UTCL2_INVAL_RANGE_START regGRBM_UTCL2_INVAL_RANGE_START; -typedef union GRBM_UTCL2_INVAL_RANGE_END regGRBM_UTCL2_INVAL_RANGE_END; -typedef union GRBM_CHIP_REVISION regGRBM_CHIP_REVISION; -typedef union GRBM_SCRATCH_REG0 regGRBM_SCRATCH_REG0; -typedef union GRBM_SCRATCH_REG1 regGRBM_SCRATCH_REG1; -typedef union GRBM_SCRATCH_REG2 regGRBM_SCRATCH_REG2; -typedef union GRBM_SCRATCH_REG3 regGRBM_SCRATCH_REG3; -typedef union GRBM_SCRATCH_REG4 regGRBM_SCRATCH_REG4; -typedef union GRBM_SCRATCH_REG5 regGRBM_SCRATCH_REG5; -typedef union GRBM_SCRATCH_REG6 regGRBM_SCRATCH_REG6; -typedef union GRBM_SCRATCH_REG7 regGRBM_SCRATCH_REG7; -typedef union DEBUG_INDEX regDEBUG_INDEX; -typedef union DEBUG_DATA regDEBUG_DATA; -typedef union GRBM_NOWHERE regGRBM_NOWHERE; -typedef union GRBM_GFX_INDEX regGRBM_GFX_INDEX; -typedef union GRBM_PERFCOUNTER0_LO regGRBM_PERFCOUNTER0_LO; -typedef union GRBM_PERFCOUNTER0_HI regGRBM_PERFCOUNTER0_HI; -typedef union GRBM_PERFCOUNTER1_LO regGRBM_PERFCOUNTER1_LO; -typedef union GRBM_PERFCOUNTER1_HI regGRBM_PERFCOUNTER1_HI; -typedef union GRBM_SE0_PERFCOUNTER_LO regGRBM_SE0_PERFCOUNTER_LO; -typedef union GRBM_SE0_PERFCOUNTER_HI regGRBM_SE0_PERFCOUNTER_HI; -typedef union GRBM_SE1_PERFCOUNTER_LO regGRBM_SE1_PERFCOUNTER_LO; -typedef union GRBM_SE1_PERFCOUNTER_HI regGRBM_SE1_PERFCOUNTER_HI; -typedef union GRBM_SE2_PERFCOUNTER_LO regGRBM_SE2_PERFCOUNTER_LO; -typedef union GRBM_SE2_PERFCOUNTER_HI regGRBM_SE2_PERFCOUNTER_HI; -typedef union GRBM_SE3_PERFCOUNTER_LO regGRBM_SE3_PERFCOUNTER_LO; -typedef union GRBM_SE3_PERFCOUNTER_HI regGRBM_SE3_PERFCOUNTER_HI; -typedef union GRBM_PERFCOUNTER0_SELECT regGRBM_PERFCOUNTER0_SELECT; -typedef union GRBM_PERFCOUNTER1_SELECT regGRBM_PERFCOUNTER1_SELECT; -typedef union GRBM_SE0_PERFCOUNTER_SELECT regGRBM_SE0_PERFCOUNTER_SELECT; -typedef union GRBM_SE1_PERFCOUNTER_SELECT regGRBM_SE1_PERFCOUNTER_SELECT; -typedef union GRBM_SE2_PERFCOUNTER_SELECT regGRBM_SE2_PERFCOUNTER_SELECT; -typedef union GRBM_SE3_PERFCOUNTER_SELECT regGRBM_SE3_PERFCOUNTER_SELECT; -typedef union GRBM_HYP_CAM_INDEX regGRBM_HYP_CAM_INDEX; -typedef union GRBM_CAM_INDEX regGRBM_CAM_INDEX; -typedef union GRBM_HYP_CAM_DATA regGRBM_HYP_CAM_DATA; -typedef union GRBM_CAM_DATA regGRBM_CAM_DATA; -typedef union GRBM_GFX_CNTL_SR_SELECT regGRBM_GFX_CNTL_SR_SELECT; -typedef union GRBM_GFX_CNTL_SR_DATA regGRBM_GFX_CNTL_SR_DATA; -typedef union GRBM_GFX_INDEX_SR_SELECT regGRBM_GFX_INDEX_SR_SELECT; -typedef union GRBM_GFX_INDEX_SR_DATA regGRBM_GFX_INDEX_SR_DATA; -typedef union GRBM_SRCID_CAM_INDEX regGRBM_SRCID_CAM_INDEX; -typedef union GRBM_SRCID_CAM_DATA regGRBM_SRCID_CAM_DATA; -typedef union GRBM_PF_ONLY_RANGE0 regGRBM_PF_ONLY_RANGE0; -typedef union GRBM_PF_ONLY_RANGE1 regGRBM_PF_ONLY_RANGE1; -typedef union GRBM_PF_ONLY_RANGE2 regGRBM_PF_ONLY_RANGE2; -typedef union GRBM_PF_ONLY_RANGE3 regGRBM_PF_ONLY_RANGE3; -typedef union GRBM_PF_ONLY_RANGE4 regGRBM_PF_ONLY_RANGE4; -typedef union GRBM_PF_ONLY_RANGE5 regGRBM_PF_ONLY_RANGE5; -typedef union GRBM_PF_ONLY_RANGE6 regGRBM_PF_ONLY_RANGE6; -typedef union GRBM_PF_ONLY_RANGE7 regGRBM_PF_ONLY_RANGE7; -typedef union GRBM_IOV_ENABLE regGRBM_IOV_ENABLE; -typedef union CP_CPC_DEBUG_CNTL regCP_CPC_DEBUG_CNTL; -typedef union CP_CPC_DEBUG_DATA regCP_CPC_DEBUG_DATA; -typedef union CP_CPF_DEBUG_CNTL regCP_CPF_DEBUG_CNTL; -typedef union CP_CPF_DEBUG_DATA regCP_CPF_DEBUG_DATA; -typedef union CP_CPC_STATUS regCP_CPC_STATUS; -typedef union CP_CPC_BUSY_STAT regCP_CPC_BUSY_STAT; -typedef union CP_CPC_STALLED_STAT1 regCP_CPC_STALLED_STAT1; -typedef union CP_CPF_STATUS regCP_CPF_STATUS; -typedef union CP_CPF_BUSY_STAT regCP_CPF_BUSY_STAT; -typedef union CP_CPF_STALLED_STAT1 regCP_CPF_STALLED_STAT1; -typedef union CP_CPC_GRBM_FREE_COUNT regCP_CPC_GRBM_FREE_COUNT; -typedef union CP_CPC_PRIV_VIOLATION_ADDR regCP_CPC_PRIV_VIOLATION_ADDR; -typedef union CP_MEC_CNTL regCP_MEC_CNTL; -typedef union CP_MEC_ME1_HEADER_DUMP regCP_MEC_ME1_HEADER_DUMP; -typedef union CP_MEC_ME2_HEADER_DUMP regCP_MEC_ME2_HEADER_DUMP; -typedef union CP_CPC_SCRATCH_INDEX regCP_CPC_SCRATCH_INDEX; -typedef union CP_CPC_SCRATCH_DATA regCP_CPC_SCRATCH_DATA; -typedef union CP_CPF_GRBM_FREE_COUNT regCP_CPF_GRBM_FREE_COUNT; -typedef union CP_CPC_HALT_HYST_COUNT regCP_CPC_HALT_HYST_COUNT; -typedef union CP_PRT_LOD_STATS_CNTL0 regCP_PRT_LOD_STATS_CNTL0; -typedef union CP_PRT_LOD_STATS_CNTL1 regCP_PRT_LOD_STATS_CNTL1; -typedef union CP_PRT_LOD_STATS_CNTL2 regCP_PRT_LOD_STATS_CNTL2; -typedef union CP_PRT_LOD_STATS_CNTL3 regCP_PRT_LOD_STATS_CNTL3; -typedef union CP_CE_COMPARE_COUNT regCP_CE_COMPARE_COUNT; -typedef union CP_CE_DE_COUNT regCP_CE_DE_COUNT; -typedef union CP_DE_CE_COUNT regCP_DE_CE_COUNT; -typedef union CP_DE_LAST_INVAL_COUNT regCP_DE_LAST_INVAL_COUNT; -typedef union CP_DE_DE_COUNT regCP_DE_DE_COUNT; -typedef union CP_STALLED_STAT1 regCP_STALLED_STAT1; -typedef union CP_STALLED_STAT2 regCP_STALLED_STAT2; -typedef union CP_STALLED_STAT3 regCP_STALLED_STAT3; -typedef union CP_BUSY_STAT regCP_BUSY_STAT; -typedef union CP_STAT regCP_STAT; -typedef union CP_ME_HEADER_DUMP regCP_ME_HEADER_DUMP; -typedef union CP_PFP_HEADER_DUMP regCP_PFP_HEADER_DUMP; -typedef union CP_GRBM_FREE_COUNT regCP_GRBM_FREE_COUNT; -typedef union CP_CE_HEADER_DUMP regCP_CE_HEADER_DUMP; -typedef union CP_PFP_INSTR_PNTR regCP_PFP_INSTR_PNTR; -typedef union CP_ME_INSTR_PNTR regCP_ME_INSTR_PNTR; -typedef union CP_CE_INSTR_PNTR regCP_CE_INSTR_PNTR; -typedef union CP_MEC1_INSTR_PNTR regCP_MEC1_INSTR_PNTR; -typedef union CP_MEC2_INSTR_PNTR regCP_MEC2_INSTR_PNTR; -typedef union CP_CSF_STAT regCP_CSF_STAT; -typedef union CP_ME_CNTL regCP_ME_CNTL; -typedef union CP_CNTX_STAT regCP_CNTX_STAT; -typedef union CP_ME_PREEMPTION regCP_ME_PREEMPTION; -typedef union CP_RB0_RPTR regCP_RB0_RPTR; -typedef union CP_RB_RPTR regCP_RB_RPTR; -typedef union CP_RB1_RPTR regCP_RB1_RPTR; -typedef union CP_RB2_RPTR regCP_RB2_RPTR; -typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; -typedef union CP_RB_WPTR_POLL_CNTL regCP_RB_WPTR_POLL_CNTL; -typedef union CP_ROQ_THRESHOLDS regCP_ROQ_THRESHOLDS; -typedef union CP_MEQ_STQ_THRESHOLD regCP_MEQ_STQ_THRESHOLD; -typedef union CP_ROQ1_THRESHOLDS regCP_ROQ1_THRESHOLDS; -typedef union CP_ROQ2_THRESHOLDS regCP_ROQ2_THRESHOLDS; -typedef union CP_STQ_THRESHOLDS regCP_STQ_THRESHOLDS; -typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; -typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; -typedef union CP_ROQ_AVAIL regCP_ROQ_AVAIL; -typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; -typedef union CP_ROQ2_AVAIL regCP_ROQ2_AVAIL; -typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; -typedef union CP_CMD_INDEX regCP_CMD_INDEX; -typedef union CP_CMD_DATA regCP_CMD_DATA; -typedef union CP_ROQ_RB_STAT regCP_ROQ_RB_STAT; -typedef union CP_ROQ_IB1_STAT regCP_ROQ_IB1_STAT; -typedef union CP_ROQ_IB2_STAT regCP_ROQ_IB2_STAT; -typedef union CP_STQ_STAT regCP_STQ_STAT; -typedef union CP_STQ_WR_STAT regCP_STQ_WR_STAT; -typedef union CP_MEQ_STAT regCP_MEQ_STAT; -typedef union CP_CEQ1_AVAIL regCP_CEQ1_AVAIL; -typedef union CP_CEQ2_AVAIL regCP_CEQ2_AVAIL; -typedef union CP_CE_ROQ_RB_STAT regCP_CE_ROQ_RB_STAT; -typedef union CP_CE_ROQ_IB1_STAT regCP_CE_ROQ_IB1_STAT; -typedef union CP_CE_ROQ_IB2_STAT regCP_CE_ROQ_IB2_STAT; -typedef union CP_INT_STAT_DEBUG regCP_INT_STAT_DEBUG; -typedef union CP_DEBUG_CNTL regCP_DEBUG_CNTL; -typedef union CP_DEBUG_DATA regCP_DEBUG_DATA; -typedef union CP_PRIV_VIOLATION_ADDR regCP_PRIV_VIOLATION_ADDR; -typedef union CP_DFY_CNTL regCP_DFY_CNTL; -typedef union CP_DFY_STAT regCP_DFY_STAT; -typedef union CP_DFY_ADDR_HI regCP_DFY_ADDR_HI; -typedef union CP_DFY_ADDR_LO regCP_DFY_ADDR_LO; -typedef union CP_DFY_DATA_0 regCP_DFY_DATA_0; -typedef union CP_DFY_DATA_1 regCP_DFY_DATA_1; -typedef union CP_DFY_DATA_2 regCP_DFY_DATA_2; -typedef union CP_DFY_DATA_3 regCP_DFY_DATA_3; -typedef union CP_DFY_DATA_4 regCP_DFY_DATA_4; -typedef union CP_DFY_DATA_5 regCP_DFY_DATA_5; -typedef union CP_DFY_DATA_6 regCP_DFY_DATA_6; -typedef union CP_DFY_DATA_7 regCP_DFY_DATA_7; -typedef union CP_DFY_DATA_8 regCP_DFY_DATA_8; -typedef union CP_DFY_DATA_9 regCP_DFY_DATA_9; -typedef union CP_DFY_DATA_10 regCP_DFY_DATA_10; -typedef union CP_DFY_DATA_11 regCP_DFY_DATA_11; -typedef union CP_DFY_DATA_12 regCP_DFY_DATA_12; -typedef union CP_DFY_DATA_13 regCP_DFY_DATA_13; -typedef union CP_DFY_DATA_14 regCP_DFY_DATA_14; -typedef union CP_DFY_DATA_15 regCP_DFY_DATA_15; -typedef union CP_DFY_CMD regCP_DFY_CMD; -typedef union CP_EOPQ_WAIT_TIME regCP_EOPQ_WAIT_TIME; -typedef union CP_CPC_MGCG_SYNC_CNTL regCP_CPC_MGCG_SYNC_CNTL; -typedef union CPC_INT_INFO regCPC_INT_INFO; -typedef union CPC_INT_ADDR regCPC_INT_ADDR; -typedef union CPC_INT_PASID regCPC_INT_PASID; -typedef union CP_GFX_ERROR regCP_GFX_ERROR; -typedef union CPG_UTCL1_CNTL regCPG_UTCL1_CNTL; -typedef union CPC_UTCL1_CNTL regCPC_UTCL1_CNTL; -typedef union CPF_UTCL1_CNTL regCPF_UTCL1_CNTL; -typedef union CP_AQL_SMM_STATUS regCP_AQL_SMM_STATUS; -typedef union CP_RB0_BASE regCP_RB0_BASE; -typedef union CP_RB0_BASE_HI regCP_RB0_BASE_HI; -typedef union CP_RB_BASE regCP_RB_BASE; -typedef union CP_RB1_BASE regCP_RB1_BASE; -typedef union CP_RB1_BASE_HI regCP_RB1_BASE_HI; -typedef union CP_RB2_BASE regCP_RB2_BASE; -typedef union CP_RB0_CNTL regCP_RB0_CNTL; -typedef union CP_RB_CNTL regCP_RB_CNTL; -typedef union CP_RB1_CNTL regCP_RB1_CNTL; -typedef union CP_RB2_CNTL regCP_RB2_CNTL; -typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; -typedef union CP_RB0_RPTR_ADDR regCP_RB0_RPTR_ADDR; -typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; -typedef union CP_RB1_RPTR_ADDR regCP_RB1_RPTR_ADDR; -typedef union CP_RB2_RPTR_ADDR regCP_RB2_RPTR_ADDR; -typedef union CP_RB0_RPTR_ADDR_HI regCP_RB0_RPTR_ADDR_HI; -typedef union CP_RB_RPTR_ADDR_HI regCP_RB_RPTR_ADDR_HI; -typedef union CP_RB1_RPTR_ADDR_HI regCP_RB1_RPTR_ADDR_HI; -typedef union CP_RB2_RPTR_ADDR_HI regCP_RB2_RPTR_ADDR_HI; -typedef union CP_RB0_ACTIVE regCP_RB0_ACTIVE; -typedef union CP_RB_ACTIVE regCP_RB_ACTIVE; -typedef union CP_RB0_BUFSZ_MASK regCP_RB0_BUFSZ_MASK; -typedef union CP_RB_BUFSZ_MASK regCP_RB_BUFSZ_MASK; -typedef union CP_RB_WPTR_POLL_ADDR_LO regCP_RB_WPTR_POLL_ADDR_LO; -typedef union CP_RB_WPTR_POLL_ADDR_HI regCP_RB_WPTR_POLL_ADDR_HI; -typedef union GC_PRIV_MODE regGC_PRIV_MODE; -typedef union CP_INT_CNTL regCP_INT_CNTL; -typedef union CP_INT_CNTL_RING0 regCP_INT_CNTL_RING0; -typedef union CP_INT_CNTL_RING1 regCP_INT_CNTL_RING1; -typedef union CP_INT_CNTL_RING2 regCP_INT_CNTL_RING2; -typedef union CP_INT_STATUS regCP_INT_STATUS; -typedef union CP_INT_STATUS_RING0 regCP_INT_STATUS_RING0; -typedef union CP_INT_STATUS_RING1 regCP_INT_STATUS_RING1; -typedef union CP_INT_STATUS_RING2 regCP_INT_STATUS_RING2; -typedef union CP_DEVICE_ID regCP_DEVICE_ID; -typedef union CP_RING_PRIORITY_CNTS regCP_RING_PRIORITY_CNTS; -typedef union CP_ME0_PIPE_PRIORITY_CNTS regCP_ME0_PIPE_PRIORITY_CNTS; -typedef union CP_RING0_PRIORITY regCP_RING0_PRIORITY; -typedef union CP_ME0_PIPE0_PRIORITY regCP_ME0_PIPE0_PRIORITY; -typedef union CP_RING1_PRIORITY regCP_RING1_PRIORITY; -typedef union CP_ME0_PIPE1_PRIORITY regCP_ME0_PIPE1_PRIORITY; -typedef union CP_RING2_PRIORITY regCP_RING2_PRIORITY; -typedef union CP_ME0_PIPE2_PRIORITY regCP_ME0_PIPE2_PRIORITY; -typedef union CP_FATAL_ERROR regCP_FATAL_ERROR; -typedef union CP_RB_VMID regCP_RB_VMID; -typedef union CP_ME0_PIPE0_VMID regCP_ME0_PIPE0_VMID; -typedef union CP_ME0_PIPE1_VMID regCP_ME0_PIPE1_VMID; -typedef union CP_RB0_WPTR regCP_RB0_WPTR; -typedef union CP_RB_WPTR regCP_RB_WPTR; -typedef union CP_RB0_WPTR_HI regCP_RB0_WPTR_HI; -typedef union CP_RB_WPTR_HI regCP_RB_WPTR_HI; -typedef union CP_RB1_WPTR regCP_RB1_WPTR; -typedef union CP_RB1_WPTR_HI regCP_RB1_WPTR_HI; -typedef union CP_RB2_WPTR regCP_RB2_WPTR; -typedef union CP_RB_DOORBELL_CONTROL regCP_RB_DOORBELL_CONTROL; -typedef union CP_RB_DOORBELL_RANGE_LOWER regCP_RB_DOORBELL_RANGE_LOWER; -typedef union CP_RB_DOORBELL_RANGE_UPPER regCP_RB_DOORBELL_RANGE_UPPER; -typedef union CP_MEC_DOORBELL_RANGE_LOWER regCP_MEC_DOORBELL_RANGE_LOWER; -typedef union CP_MEC_DOORBELL_RANGE_UPPER regCP_MEC_DOORBELL_RANGE_UPPER; -typedef union CPG_UTCL1_ERROR regCPG_UTCL1_ERROR; -typedef union CPC_UTCL1_ERROR regCPC_UTCL1_ERROR; -typedef union CP_IB1_PRIV_BASE_LO regCP_IB1_PRIV_BASE_LO; -typedef union CP_IB1_PRIV_BASE_HI regCP_IB1_PRIV_BASE_HI; -typedef union CP_IB1_PRIV_BUFSZ regCP_IB1_PRIV_BUFSZ; -typedef union CP_ME_F32_INTERRUPT regCP_ME_F32_INTERRUPT; -typedef union CP_PFP_F32_INTERRUPT regCP_PFP_F32_INTERRUPT; -typedef union CP_CE_F32_INTERRUPT regCP_CE_F32_INTERRUPT; -typedef union CP_MEC1_F32_INTERRUPT regCP_MEC1_F32_INTERRUPT; -typedef union CP_MEC2_F32_INTERRUPT regCP_MEC2_F32_INTERRUPT; -typedef union CP_MEC1_F32_INT_DIS regCP_MEC1_F32_INT_DIS; -typedef union CP_MEC2_F32_INT_DIS regCP_MEC2_F32_INT_DIS; -typedef union CP_VIRT_STATUS regCP_VIRT_STATUS; -typedef union CP_PWR_CNTL regCP_PWR_CNTL; -typedef union CP_MEM_SLP_CNTL regCP_MEM_SLP_CNTL; -typedef union CP_ECC_FIRSTOCCURRENCE regCP_ECC_FIRSTOCCURRENCE; -typedef union CP_ECC_FIRSTOCCURRENCE_RING0 regCP_ECC_FIRSTOCCURRENCE_RING0; -typedef union CP_ECC_FIRSTOCCURRENCE_RING1 regCP_ECC_FIRSTOCCURRENCE_RING1; -typedef union CP_ECC_FIRSTOCCURRENCE_RING2 regCP_ECC_FIRSTOCCURRENCE_RING2; -typedef union CP_DEBUG regCP_DEBUG; -typedef union CP_CPF_DEBUG regCP_CPF_DEBUG; -typedef union CP_CPC_DEBUG regCP_CPC_DEBUG; -typedef union CP_PQ_WPTR_POLL_CNTL regCP_PQ_WPTR_POLL_CNTL; -typedef union CP_PQ_WPTR_POLL_CNTL1 regCP_PQ_WPTR_POLL_CNTL1; -typedef union CPC_INT_CNTL regCPC_INT_CNTL; -typedef union CP_ME1_PIPE0_INT_CNTL regCP_ME1_PIPE0_INT_CNTL; -typedef union CP_ME1_PIPE1_INT_CNTL regCP_ME1_PIPE1_INT_CNTL; -typedef union CP_ME1_PIPE2_INT_CNTL regCP_ME1_PIPE2_INT_CNTL; -typedef union CP_ME1_PIPE3_INT_CNTL regCP_ME1_PIPE3_INT_CNTL; -typedef union CP_ME2_PIPE0_INT_CNTL regCP_ME2_PIPE0_INT_CNTL; -typedef union CP_ME2_PIPE1_INT_CNTL regCP_ME2_PIPE1_INT_CNTL; -typedef union CP_ME2_PIPE2_INT_CNTL regCP_ME2_PIPE2_INT_CNTL; -typedef union CP_ME2_PIPE3_INT_CNTL regCP_ME2_PIPE3_INT_CNTL; -typedef union CPC_INT_STATUS regCPC_INT_STATUS; -typedef union CP_ME1_PIPE0_INT_STATUS regCP_ME1_PIPE0_INT_STATUS; -typedef union CP_ME1_PIPE1_INT_STATUS regCP_ME1_PIPE1_INT_STATUS; -typedef union CP_ME1_PIPE2_INT_STATUS regCP_ME1_PIPE2_INT_STATUS; -typedef union CP_ME1_PIPE3_INT_STATUS regCP_ME1_PIPE3_INT_STATUS; -typedef union CP_ME2_PIPE0_INT_STATUS regCP_ME2_PIPE0_INT_STATUS; -typedef union CP_ME2_PIPE1_INT_STATUS regCP_ME2_PIPE1_INT_STATUS; -typedef union CP_ME2_PIPE2_INT_STATUS regCP_ME2_PIPE2_INT_STATUS; -typedef union CP_ME2_PIPE3_INT_STATUS regCP_ME2_PIPE3_INT_STATUS; -typedef union CP_ME1_INT_STAT_DEBUG regCP_ME1_INT_STAT_DEBUG; -typedef union CP_ME2_INT_STAT_DEBUG regCP_ME2_INT_STAT_DEBUG; -typedef union CP_ME1_PIPE_PRIORITY_CNTS regCP_ME1_PIPE_PRIORITY_CNTS; -typedef union CP_ME1_PIPE0_PRIORITY regCP_ME1_PIPE0_PRIORITY; -typedef union CP_ME1_PIPE1_PRIORITY regCP_ME1_PIPE1_PRIORITY; -typedef union CP_ME1_PIPE2_PRIORITY regCP_ME1_PIPE2_PRIORITY; -typedef union CP_ME1_PIPE3_PRIORITY regCP_ME1_PIPE3_PRIORITY; -typedef union CP_ME2_PIPE_PRIORITY_CNTS regCP_ME2_PIPE_PRIORITY_CNTS; -typedef union CP_ME2_PIPE0_PRIORITY regCP_ME2_PIPE0_PRIORITY; -typedef union CP_ME2_PIPE1_PRIORITY regCP_ME2_PIPE1_PRIORITY; -typedef union CP_ME2_PIPE2_PRIORITY regCP_ME2_PIPE2_PRIORITY; -typedef union CP_ME2_PIPE3_PRIORITY regCP_ME2_PIPE3_PRIORITY; -typedef union CP_CE_PRGRM_CNTR_START regCP_CE_PRGRM_CNTR_START; -typedef union CP_PFP_PRGRM_CNTR_START regCP_PFP_PRGRM_CNTR_START; -typedef union CP_ME_PRGRM_CNTR_START regCP_ME_PRGRM_CNTR_START; -typedef union CP_MEC1_PRGRM_CNTR_START regCP_MEC1_PRGRM_CNTR_START; -typedef union CP_MEC2_PRGRM_CNTR_START regCP_MEC2_PRGRM_CNTR_START; -typedef union CP_CE_INTR_ROUTINE_START regCP_CE_INTR_ROUTINE_START; -typedef union CP_PFP_INTR_ROUTINE_START regCP_PFP_INTR_ROUTINE_START; -typedef union CP_ME_INTR_ROUTINE_START regCP_ME_INTR_ROUTINE_START; -typedef union CP_MEC1_INTR_ROUTINE_START regCP_MEC1_INTR_ROUTINE_START; -typedef union CP_MEC2_INTR_ROUTINE_START regCP_MEC2_INTR_ROUTINE_START; -typedef union CP_CONTEXT_CNTL regCP_CONTEXT_CNTL; -typedef union CP_MAX_CONTEXT regCP_MAX_CONTEXT; -typedef union CP_IQ_WAIT_TIME1 regCP_IQ_WAIT_TIME1; -typedef union CP_IQ_WAIT_TIME2 regCP_IQ_WAIT_TIME2; -typedef union CP_VMID_RESET regCP_VMID_RESET; -typedef union CP_VMID_PREEMPT regCP_VMID_PREEMPT; -typedef union CP_VMID_STATUS regCP_VMID_STATUS; -typedef union CPC_INT_CNTX_ID regCPC_INT_CNTX_ID; -typedef union CP_PQ_STATUS regCP_PQ_STATUS; -typedef union CP_CPC_IC_BASE_LO regCP_CPC_IC_BASE_LO; -typedef union CP_CPC_IC_BASE_HI regCP_CPC_IC_BASE_HI; -typedef union CP_CPC_IC_BASE_CNTL regCP_CPC_IC_BASE_CNTL; -typedef union CP_CPC_IC_OP_CNTL regCP_CPC_IC_OP_CNTL; -typedef union CP_RB_DOORBELL_CONTROL_SCH_0 regCP_RB_DOORBELL_CONTROL_SCH_0; -typedef union CP_RB_DOORBELL_CONTROL_SCH_1 regCP_RB_DOORBELL_CONTROL_SCH_1; -typedef union CP_RB_DOORBELL_CONTROL_SCH_2 regCP_RB_DOORBELL_CONTROL_SCH_2; -typedef union CP_RB_DOORBELL_CONTROL_SCH_3 regCP_RB_DOORBELL_CONTROL_SCH_3; -typedef union CP_RB_DOORBELL_CONTROL_SCH_4 regCP_RB_DOORBELL_CONTROL_SCH_4; -typedef union CP_RB_DOORBELL_CONTROL_SCH_5 regCP_RB_DOORBELL_CONTROL_SCH_5; -typedef union CP_RB_DOORBELL_CONTROL_SCH_6 regCP_RB_DOORBELL_CONTROL_SCH_6; -typedef union CP_RB_DOORBELL_CONTROL_SCH_7 regCP_RB_DOORBELL_CONTROL_SCH_7; -typedef union CP_RB_DOORBELL_CLEAR regCP_RB_DOORBELL_CLEAR; -typedef union CP_GFX_MQD_CONTROL regCP_GFX_MQD_CONTROL; -typedef union CP_GFX_MQD_BASE_ADDR regCP_GFX_MQD_BASE_ADDR; -typedef union CP_GFX_MQD_BASE_ADDR_HI regCP_GFX_MQD_BASE_ADDR_HI; -typedef union CP_RB_STATUS regCP_RB_STATUS; -typedef union CPG_UTCL1_STATUS regCPG_UTCL1_STATUS; -typedef union CPC_UTCL1_STATUS regCPC_UTCL1_STATUS; -typedef union CPF_UTCL1_STATUS regCPF_UTCL1_STATUS; -typedef union CP_SD_CNTL regCP_SD_CNTL; -typedef union CP_TMZ_CNTL regCP_TMZ_CNTL; -typedef union CP_SOFT_RESET_CNTL regCP_SOFT_RESET_CNTL; -typedef union CP_CPC_GFX_CNTL regCP_CPC_GFX_CNTL; -typedef union CP_SECURE_TMZ regCP_SECURE_TMZ; -typedef union CP_GFX_SECURE_REQ0 regCP_GFX_SECURE_REQ0; -typedef union CP_HQD_SECURE_REQ0 regCP_HQD_SECURE_REQ0; -typedef union CP_HQD_GFX_CONTROL regCP_HQD_GFX_CONTROL; -typedef union CP_HQD_GFX_STATUS regCP_HQD_GFX_STATUS; -typedef union CP_HPD_ROQ_OFFSETS regCP_HPD_ROQ_OFFSETS; -typedef union CP_HPD_STATUS0 regCP_HPD_STATUS0; -typedef union CP_HPD_UTCL1_CNTL regCP_HPD_UTCL1_CNTL; -typedef union CP_HPD_UTCL1_ERROR regCP_HPD_UTCL1_ERROR; -typedef union CP_HPD_UTCL1_ERROR_ADDR regCP_HPD_UTCL1_ERROR_ADDR; -typedef union CP_MQD_BASE_ADDR regCP_MQD_BASE_ADDR; -typedef union CP_MQD_BASE_ADDR_HI regCP_MQD_BASE_ADDR_HI; -typedef union CP_HQD_ACTIVE regCP_HQD_ACTIVE; -typedef union CP_HQD_VMID regCP_HQD_VMID; -typedef union CP_HQD_PERSISTENT_STATE regCP_HQD_PERSISTENT_STATE; -typedef union CP_HQD_PIPE_PRIORITY regCP_HQD_PIPE_PRIORITY; -typedef union CP_HQD_QUEUE_PRIORITY regCP_HQD_QUEUE_PRIORITY; -typedef union CP_HQD_QUANTUM regCP_HQD_QUANTUM; -typedef union CP_HQD_PQ_BASE regCP_HQD_PQ_BASE; -typedef union CP_HQD_PQ_BASE_HI regCP_HQD_PQ_BASE_HI; -typedef union CP_HQD_PQ_RPTR regCP_HQD_PQ_RPTR; -typedef union CP_HQD_PQ_RPTR_REPORT_ADDR regCP_HQD_PQ_RPTR_REPORT_ADDR; -typedef union CP_HQD_PQ_RPTR_REPORT_ADDR_HI regCP_HQD_PQ_RPTR_REPORT_ADDR_HI; -typedef union CP_HQD_PQ_WPTR_POLL_ADDR regCP_HQD_PQ_WPTR_POLL_ADDR; -typedef union CP_HQD_PQ_WPTR_POLL_ADDR_HI regCP_HQD_PQ_WPTR_POLL_ADDR_HI; -typedef union CP_HQD_PQ_DOORBELL_CONTROL regCP_HQD_PQ_DOORBELL_CONTROL; -typedef union CP_HQD_PQ_CONTROL regCP_HQD_PQ_CONTROL; -typedef union CP_HQD_IB_BASE_ADDR regCP_HQD_IB_BASE_ADDR; -typedef union CP_HQD_IB_BASE_ADDR_HI regCP_HQD_IB_BASE_ADDR_HI; -typedef union CP_HQD_IB_RPTR regCP_HQD_IB_RPTR; -typedef union CP_HQD_IB_CONTROL regCP_HQD_IB_CONTROL; -typedef union CP_HQD_IQ_TIMER regCP_HQD_IQ_TIMER; -typedef union CP_HQD_IQ_RPTR regCP_HQD_IQ_RPTR; -typedef union CP_HQD_DEQUEUE_REQUEST regCP_HQD_DEQUEUE_REQUEST; -typedef union CP_HQD_DMA_OFFLOAD regCP_HQD_DMA_OFFLOAD; -typedef union CP_HQD_OFFLOAD regCP_HQD_OFFLOAD; -typedef union CP_HQD_SEMA_CMD regCP_HQD_SEMA_CMD; -typedef union CP_HQD_MSG_TYPE regCP_HQD_MSG_TYPE; -typedef union CP_HQD_ATOMIC0_PREOP_LO regCP_HQD_ATOMIC0_PREOP_LO; -typedef union CP_HQD_ATOMIC0_PREOP_HI regCP_HQD_ATOMIC0_PREOP_HI; -typedef union CP_HQD_ATOMIC1_PREOP_LO regCP_HQD_ATOMIC1_PREOP_LO; -typedef union CP_HQD_ATOMIC1_PREOP_HI regCP_HQD_ATOMIC1_PREOP_HI; -typedef union CP_HQD_HQ_SCHEDULER0 regCP_HQD_HQ_SCHEDULER0; -typedef union CP_HQD_HQ_STATUS0 regCP_HQD_HQ_STATUS0; -typedef union CP_HQD_HQ_SCHEDULER1 regCP_HQD_HQ_SCHEDULER1; -typedef union CP_HQD_HQ_CONTROL0 regCP_HQD_HQ_CONTROL0; -typedef union CP_MQD_CONTROL regCP_MQD_CONTROL; -typedef union CP_HQD_HQ_STATUS1 regCP_HQD_HQ_STATUS1; -typedef union CP_HQD_HQ_CONTROL1 regCP_HQD_HQ_CONTROL1; -typedef union CP_HQD_EOP_BASE_ADDR regCP_HQD_EOP_BASE_ADDR; -typedef union CP_HQD_EOP_BASE_ADDR_HI regCP_HQD_EOP_BASE_ADDR_HI; -typedef union CP_HQD_EOP_CONTROL regCP_HQD_EOP_CONTROL; -typedef union CP_HQD_EOP_RPTR regCP_HQD_EOP_RPTR; -typedef union CP_HQD_EOP_WPTR regCP_HQD_EOP_WPTR; -typedef union CP_HQD_EOP_EVENTS regCP_HQD_EOP_EVENTS; -typedef union CP_HQD_CTX_SAVE_BASE_ADDR_LO regCP_HQD_CTX_SAVE_BASE_ADDR_LO; -typedef union CP_HQD_CTX_SAVE_BASE_ADDR_HI regCP_HQD_CTX_SAVE_BASE_ADDR_HI; -typedef union CP_HQD_CTX_SAVE_CONTROL regCP_HQD_CTX_SAVE_CONTROL; -typedef union CP_HQD_CNTL_STACK_OFFSET regCP_HQD_CNTL_STACK_OFFSET; -typedef union CP_HQD_CNTL_STACK_SIZE regCP_HQD_CNTL_STACK_SIZE; -typedef union CP_HQD_WG_STATE_OFFSET regCP_HQD_WG_STATE_OFFSET; -typedef union CP_HQD_CTX_SAVE_SIZE regCP_HQD_CTX_SAVE_SIZE; -typedef union CP_HQD_GDS_RESOURCE_STATE regCP_HQD_GDS_RESOURCE_STATE; -typedef union CP_HQD_ERROR regCP_HQD_ERROR; -typedef union CP_HQD_EOP_WPTR_MEM regCP_HQD_EOP_WPTR_MEM; -typedef union CP_HQD_AQL_CONTROL regCP_HQD_AQL_CONTROL; -typedef union CP_HQD_PQ_WPTR_LO regCP_HQD_PQ_WPTR_LO; -typedef union CP_HQD_PQ_WPTR_HI regCP_HQD_PQ_WPTR_HI; -typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; -typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; -typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; -typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; -typedef union COHER_DEST_BASE_HI_0 regCOHER_DEST_BASE_HI_0; -typedef union COHER_DEST_BASE_HI_1 regCOHER_DEST_BASE_HI_1; -typedef union COHER_DEST_BASE_HI_2 regCOHER_DEST_BASE_HI_2; -typedef union COHER_DEST_BASE_HI_3 regCOHER_DEST_BASE_HI_3; -typedef union CP_PERFMON_CNTX_CNTL regCP_PERFMON_CNTX_CNTL; -typedef union CP_RINGID regCP_RINGID; -typedef union CP_PIPEID regCP_PIPEID; -typedef union CP_VMID regCP_VMID; -typedef union CP_EOP_DONE_EVENT_CNTL regCP_EOP_DONE_EVENT_CNTL; -typedef union CP_EOP_DONE_DATA_CNTL regCP_EOP_DONE_DATA_CNTL; -typedef union CP_EOP_DONE_CNTX_ID regCP_EOP_DONE_CNTX_ID; -typedef union CP_EOP_DONE_ADDR_LO regCP_EOP_DONE_ADDR_LO; -typedef union CP_EOP_DONE_ADDR_HI regCP_EOP_DONE_ADDR_HI; -typedef union CP_EOP_DONE_DATA_LO regCP_EOP_DONE_DATA_LO; -typedef union CP_EOP_DONE_DATA_HI regCP_EOP_DONE_DATA_HI; -typedef union CP_EOP_LAST_FENCE_LO regCP_EOP_LAST_FENCE_LO; -typedef union CP_EOP_LAST_FENCE_HI regCP_EOP_LAST_FENCE_HI; -typedef union CP_STREAM_OUT_ADDR_LO regCP_STREAM_OUT_ADDR_LO; -typedef union CP_STREAM_OUT_ADDR_HI regCP_STREAM_OUT_ADDR_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT0_LO regCP_NUM_PRIM_WRITTEN_COUNT0_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT0_HI regCP_NUM_PRIM_WRITTEN_COUNT0_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT0_LO regCP_NUM_PRIM_NEEDED_COUNT0_LO; -typedef union CP_NUM_PRIM_NEEDED_COUNT0_HI regCP_NUM_PRIM_NEEDED_COUNT0_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT1_LO regCP_NUM_PRIM_WRITTEN_COUNT1_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT1_HI regCP_NUM_PRIM_WRITTEN_COUNT1_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT1_LO regCP_NUM_PRIM_NEEDED_COUNT1_LO; -typedef union CP_NUM_PRIM_NEEDED_COUNT1_HI regCP_NUM_PRIM_NEEDED_COUNT1_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT2_LO regCP_NUM_PRIM_WRITTEN_COUNT2_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT2_HI regCP_NUM_PRIM_WRITTEN_COUNT2_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT2_LO regCP_NUM_PRIM_NEEDED_COUNT2_LO; -typedef union CP_NUM_PRIM_NEEDED_COUNT2_HI regCP_NUM_PRIM_NEEDED_COUNT2_HI; -typedef union CP_NUM_PRIM_WRITTEN_COUNT3_LO regCP_NUM_PRIM_WRITTEN_COUNT3_LO; -typedef union CP_NUM_PRIM_WRITTEN_COUNT3_HI regCP_NUM_PRIM_WRITTEN_COUNT3_HI; -typedef union CP_NUM_PRIM_NEEDED_COUNT3_LO regCP_NUM_PRIM_NEEDED_COUNT3_LO; -typedef union CP_NUM_PRIM_NEEDED_COUNT3_HI regCP_NUM_PRIM_NEEDED_COUNT3_HI; -typedef union CP_PIPE_STATS_ADDR_LO regCP_PIPE_STATS_ADDR_LO; -typedef union CP_PIPE_STATS_ADDR_HI regCP_PIPE_STATS_ADDR_HI; -typedef union CP_VGT_IAVERT_COUNT_LO regCP_VGT_IAVERT_COUNT_LO; -typedef union CP_VGT_IAVERT_COUNT_HI regCP_VGT_IAVERT_COUNT_HI; -typedef union CP_VGT_IAPRIM_COUNT_LO regCP_VGT_IAPRIM_COUNT_LO; -typedef union CP_VGT_IAPRIM_COUNT_HI regCP_VGT_IAPRIM_COUNT_HI; -typedef union CP_VGT_GSPRIM_COUNT_LO regCP_VGT_GSPRIM_COUNT_LO; -typedef union CP_VGT_GSPRIM_COUNT_HI regCP_VGT_GSPRIM_COUNT_HI; -typedef union CP_VGT_VSINVOC_COUNT_LO regCP_VGT_VSINVOC_COUNT_LO; -typedef union CP_VGT_VSINVOC_COUNT_HI regCP_VGT_VSINVOC_COUNT_HI; -typedef union CP_VGT_GSINVOC_COUNT_LO regCP_VGT_GSINVOC_COUNT_LO; -typedef union CP_VGT_GSINVOC_COUNT_HI regCP_VGT_GSINVOC_COUNT_HI; -typedef union CP_VGT_HSINVOC_COUNT_LO regCP_VGT_HSINVOC_COUNT_LO; -typedef union CP_VGT_HSINVOC_COUNT_HI regCP_VGT_HSINVOC_COUNT_HI; -typedef union CP_VGT_DSINVOC_COUNT_LO regCP_VGT_DSINVOC_COUNT_LO; -typedef union CP_VGT_DSINVOC_COUNT_HI regCP_VGT_DSINVOC_COUNT_HI; -typedef union CP_PA_CINVOC_COUNT_LO regCP_PA_CINVOC_COUNT_LO; -typedef union CP_PA_CINVOC_COUNT_HI regCP_PA_CINVOC_COUNT_HI; -typedef union CP_PA_CPRIM_COUNT_LO regCP_PA_CPRIM_COUNT_LO; -typedef union CP_PA_CPRIM_COUNT_HI regCP_PA_CPRIM_COUNT_HI; -typedef union CP_SC_PSINVOC_COUNT0_LO regCP_SC_PSINVOC_COUNT0_LO; -typedef union CP_SC_PSINVOC_COUNT0_HI regCP_SC_PSINVOC_COUNT0_HI; -typedef union CP_SC_PSINVOC_COUNT1_LO regCP_SC_PSINVOC_COUNT1_LO; -typedef union CP_SC_PSINVOC_COUNT1_HI regCP_SC_PSINVOC_COUNT1_HI; -typedef union CP_VGT_CSINVOC_COUNT_LO regCP_VGT_CSINVOC_COUNT_LO; -typedef union CP_VGT_CSINVOC_COUNT_HI regCP_VGT_CSINVOC_COUNT_HI; -typedef union CP_PIPE_STATS_CONTROL regCP_PIPE_STATS_CONTROL; -typedef union CP_STREAM_OUT_CONTROL regCP_STREAM_OUT_CONTROL; -typedef union CP_STRMOUT_CNTL regCP_STRMOUT_CNTL; -typedef union SCRATCH_REG0 regSCRATCH_REG0; -typedef union SCRATCH_REG1 regSCRATCH_REG1; -typedef union SCRATCH_REG2 regSCRATCH_REG2; -typedef union SCRATCH_REG3 regSCRATCH_REG3; -typedef union SCRATCH_REG4 regSCRATCH_REG4; -typedef union SCRATCH_REG5 regSCRATCH_REG5; -typedef union SCRATCH_REG6 regSCRATCH_REG6; -typedef union SCRATCH_REG7 regSCRATCH_REG7; -typedef union CP_APPEND_DATA_HI regCP_APPEND_DATA_HI; -typedef union CP_APPEND_LAST_CS_FENCE_HI regCP_APPEND_LAST_CS_FENCE_HI; -typedef union CP_APPEND_LAST_PS_FENCE_HI regCP_APPEND_LAST_PS_FENCE_HI; -typedef union SCRATCH_UMSK regSCRATCH_UMSK; -typedef union SCRATCH_ADDR regSCRATCH_ADDR; -typedef union CP_PFP_ATOMIC_PREOP_LO regCP_PFP_ATOMIC_PREOP_LO; -typedef union CP_PFP_ATOMIC_PREOP_HI regCP_PFP_ATOMIC_PREOP_HI; -typedef union CP_PFP_GDS_ATOMIC0_PREOP_LO regCP_PFP_GDS_ATOMIC0_PREOP_LO; -typedef union CP_PFP_GDS_ATOMIC0_PREOP_HI regCP_PFP_GDS_ATOMIC0_PREOP_HI; -typedef union CP_PFP_GDS_ATOMIC1_PREOP_LO regCP_PFP_GDS_ATOMIC1_PREOP_LO; -typedef union CP_PFP_GDS_ATOMIC1_PREOP_HI regCP_PFP_GDS_ATOMIC1_PREOP_HI; -typedef union CP_APPEND_ADDR_LO regCP_APPEND_ADDR_LO; -typedef union CP_APPEND_ADDR_HI regCP_APPEND_ADDR_HI; -typedef union CP_APPEND_DATA_LO regCP_APPEND_DATA_LO; -typedef union CP_APPEND_LAST_CS_FENCE_LO regCP_APPEND_LAST_CS_FENCE_LO; -typedef union CP_APPEND_LAST_PS_FENCE_LO regCP_APPEND_LAST_PS_FENCE_LO; -typedef union CP_ATOMIC_PREOP_LO regCP_ATOMIC_PREOP_LO; -typedef union CP_ME_ATOMIC_PREOP_LO regCP_ME_ATOMIC_PREOP_LO; -typedef union CP_ATOMIC_PREOP_HI regCP_ATOMIC_PREOP_HI; -typedef union CP_ME_ATOMIC_PREOP_HI regCP_ME_ATOMIC_PREOP_HI; -typedef union CP_GDS_ATOMIC0_PREOP_LO regCP_GDS_ATOMIC0_PREOP_LO; -typedef union CP_ME_GDS_ATOMIC0_PREOP_LO regCP_ME_GDS_ATOMIC0_PREOP_LO; -typedef union CP_GDS_ATOMIC0_PREOP_HI regCP_GDS_ATOMIC0_PREOP_HI; -typedef union CP_ME_GDS_ATOMIC0_PREOP_HI regCP_ME_GDS_ATOMIC0_PREOP_HI; -typedef union CP_GDS_ATOMIC1_PREOP_LO regCP_GDS_ATOMIC1_PREOP_LO; -typedef union CP_ME_GDS_ATOMIC1_PREOP_LO regCP_ME_GDS_ATOMIC1_PREOP_LO; -typedef union CP_GDS_ATOMIC1_PREOP_HI regCP_GDS_ATOMIC1_PREOP_HI; -typedef union CP_ME_GDS_ATOMIC1_PREOP_HI regCP_ME_GDS_ATOMIC1_PREOP_HI; -typedef union CP_ME_MC_WADDR_LO regCP_ME_MC_WADDR_LO; -typedef union CP_ME_MC_WADDR_HI regCP_ME_MC_WADDR_HI; -typedef union CP_ME_MC_WDATA_LO regCP_ME_MC_WDATA_LO; -typedef union CP_ME_MC_WDATA_HI regCP_ME_MC_WDATA_HI; -typedef union CP_ME_MC_RADDR_LO regCP_ME_MC_RADDR_LO; -typedef union CP_ME_MC_RADDR_HI regCP_ME_MC_RADDR_HI; -typedef union CP_SEM_WAIT_TIMER regCP_SEM_WAIT_TIMER; -typedef union CP_SIG_SEM_ADDR_LO regCP_SIG_SEM_ADDR_LO; -typedef union CP_SIG_SEM_ADDR_HI regCP_SIG_SEM_ADDR_HI; -typedef union CP_WAIT_SEM_ADDR_LO regCP_WAIT_SEM_ADDR_LO; -typedef union CP_WAIT_SEM_ADDR_HI regCP_WAIT_SEM_ADDR_HI; -typedef union CP_WAIT_REG_MEM_TIMEOUT regCP_WAIT_REG_MEM_TIMEOUT; -typedef union CP_COHER_START_DELAY regCP_COHER_START_DELAY; -typedef union CP_COHER_CNTL regCP_COHER_CNTL; -typedef union CP_COHER_SIZE regCP_COHER_SIZE; -typedef union CP_COHER_SIZE_HI regCP_COHER_SIZE_HI; -typedef union CP_COHER_BASE regCP_COHER_BASE; -typedef union CP_COHER_BASE_HI regCP_COHER_BASE_HI; -typedef union CP_COHER_STATUS regCP_COHER_STATUS; -typedef union CP_DMA_PIO_SRC_ADDR regCP_DMA_PIO_SRC_ADDR; -typedef union CP_DMA_PIO_SRC_ADDR_HI regCP_DMA_PIO_SRC_ADDR_HI; -typedef union CP_DMA_PIO_DST_ADDR regCP_DMA_PIO_DST_ADDR; -typedef union CP_DMA_PIO_DST_ADDR_HI regCP_DMA_PIO_DST_ADDR_HI; -typedef union CP_DMA_PIO_CONTROL regCP_DMA_PIO_CONTROL; -typedef union CP_DMA_PIO_COMMAND regCP_DMA_PIO_COMMAND; -typedef union CP_DMA_ME_SRC_ADDR regCP_DMA_ME_SRC_ADDR; -typedef union CP_DMA_ME_SRC_ADDR_HI regCP_DMA_ME_SRC_ADDR_HI; -typedef union CP_DMA_ME_DST_ADDR regCP_DMA_ME_DST_ADDR; -typedef union CP_DMA_ME_DST_ADDR_HI regCP_DMA_ME_DST_ADDR_HI; -typedef union CP_DMA_ME_CONTROL regCP_DMA_ME_CONTROL; -typedef union CP_DMA_ME_COMMAND regCP_DMA_ME_COMMAND; -typedef union CP_DMA_PFP_SRC_ADDR regCP_DMA_PFP_SRC_ADDR; -typedef union CP_DMA_PFP_SRC_ADDR_HI regCP_DMA_PFP_SRC_ADDR_HI; -typedef union CP_DMA_PFP_DST_ADDR regCP_DMA_PFP_DST_ADDR; -typedef union CP_DMA_PFP_DST_ADDR_HI regCP_DMA_PFP_DST_ADDR_HI; -typedef union CP_DMA_PFP_CONTROL regCP_DMA_PFP_CONTROL; -typedef union CP_DMA_PFP_COMMAND regCP_DMA_PFP_COMMAND; -typedef union CP_DMA_CNTL regCP_DMA_CNTL; -typedef union CP_DMA_READ_TAGS regCP_DMA_READ_TAGS; -typedef union CP_PFP_IB_CONTROL regCP_PFP_IB_CONTROL; -typedef union CP_PFP_LOAD_CONTROL regCP_PFP_LOAD_CONTROL; -typedef union CP_SCRATCH_INDEX regCP_SCRATCH_INDEX; -typedef union CP_SCRATCH_DATA regCP_SCRATCH_DATA; -typedef union CP_RB_OFFSET regCP_RB_OFFSET; -typedef union CP_IB1_OFFSET regCP_IB1_OFFSET; -typedef union CP_IB2_OFFSET regCP_IB2_OFFSET; -typedef union CP_IB1_PREAMBLE_BEGIN regCP_IB1_PREAMBLE_BEGIN; -typedef union CP_IB1_PREAMBLE_END regCP_IB1_PREAMBLE_END; -typedef union CP_IB2_PREAMBLE_BEGIN regCP_IB2_PREAMBLE_BEGIN; -typedef union CP_IB2_PREAMBLE_END regCP_IB2_PREAMBLE_END; -typedef union CP_CE_IB1_OFFSET regCP_CE_IB1_OFFSET; -typedef union CP_CE_IB2_OFFSET regCP_CE_IB2_OFFSET; -typedef union CP_CE_COUNTER regCP_CE_COUNTER; -typedef union CP_CE_RB_OFFSET regCP_CE_RB_OFFSET; -typedef union CP_PFP_COMPLETION_STATUS regCP_PFP_COMPLETION_STATUS; -typedef union CP_CE_COMPLETION_STATUS regCP_CE_COMPLETION_STATUS; -typedef union CP_PRED_NOT_VISIBLE regCP_PRED_NOT_VISIBLE; -typedef union CP_PFP_METADATA_BASE_ADDR regCP_PFP_METADATA_BASE_ADDR; -typedef union CP_PFP_METADATA_BASE_ADDR_HI regCP_PFP_METADATA_BASE_ADDR_HI; -typedef union CP_CE_METADATA_BASE_ADDR regCP_CE_METADATA_BASE_ADDR; -typedef union CP_CE_METADATA_BASE_ADDR_HI regCP_CE_METADATA_BASE_ADDR_HI; -typedef union CP_DRAW_INDX_INDR_ADDR regCP_DRAW_INDX_INDR_ADDR; -typedef union CP_DRAW_INDX_INDR_ADDR_HI regCP_DRAW_INDX_INDR_ADDR_HI; -typedef union CP_DISPATCH_INDR_ADDR regCP_DISPATCH_INDR_ADDR; -typedef union CP_DISPATCH_INDR_ADDR_HI regCP_DISPATCH_INDR_ADDR_HI; -typedef union CP_INDEX_BASE_ADDR regCP_INDEX_BASE_ADDR; -typedef union CP_INDEX_BASE_ADDR_HI regCP_INDEX_BASE_ADDR_HI; -typedef union CP_INDEX_TYPE regCP_INDEX_TYPE; -typedef union CP_GDS_BKUP_ADDR regCP_GDS_BKUP_ADDR; -typedef union CP_GDS_BKUP_ADDR_HI regCP_GDS_BKUP_ADDR_HI; -typedef union CP_SAMPLE_STATUS regCP_SAMPLE_STATUS; -typedef union CP_ME_COHER_CNTL regCP_ME_COHER_CNTL; -typedef union CP_ME_COHER_SIZE regCP_ME_COHER_SIZE; -typedef union CP_ME_COHER_SIZE_HI regCP_ME_COHER_SIZE_HI; -typedef union CP_ME_COHER_BASE regCP_ME_COHER_BASE; -typedef union CP_ME_COHER_BASE_HI regCP_ME_COHER_BASE_HI; -typedef union CP_ME_COHER_STATUS regCP_ME_COHER_STATUS; -typedef union CP_CE_INIT_CMD_BUFSZ regCP_CE_INIT_CMD_BUFSZ; -typedef union CP_CE_IB1_CMD_BUFSZ regCP_CE_IB1_CMD_BUFSZ; -typedef union CP_CE_IB2_CMD_BUFSZ regCP_CE_IB2_CMD_BUFSZ; -typedef union CP_IB1_CMD_BUFSZ regCP_IB1_CMD_BUFSZ; -typedef union CP_IB2_CMD_BUFSZ regCP_IB2_CMD_BUFSZ; -typedef union CP_ST_CMD_BUFSZ regCP_ST_CMD_BUFSZ; -typedef union CP_CE_INIT_BASE_LO regCP_CE_INIT_BASE_LO; -typedef union CP_CE_INIT_BASE_HI regCP_CE_INIT_BASE_HI; -typedef union CP_CE_INIT_BUFSZ regCP_CE_INIT_BUFSZ; -typedef union CP_CE_IB1_BASE_LO regCP_CE_IB1_BASE_LO; -typedef union CP_CE_IB1_BASE_HI regCP_CE_IB1_BASE_HI; -typedef union CP_CE_IB1_BUFSZ regCP_CE_IB1_BUFSZ; -typedef union CP_CE_IB2_BASE_LO regCP_CE_IB2_BASE_LO; -typedef union CP_CE_IB2_BASE_HI regCP_CE_IB2_BASE_HI; -typedef union CP_CE_IB2_BUFSZ regCP_CE_IB2_BUFSZ; -typedef union CP_IB1_BASE_LO regCP_IB1_BASE_LO; -typedef union CP_IB1_BASE_HI regCP_IB1_BASE_HI; -typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; -typedef union CP_IB2_BASE_LO regCP_IB2_BASE_LO; -typedef union CP_IB2_BASE_HI regCP_IB2_BASE_HI; -typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; -typedef union CP_ST_BASE_LO regCP_ST_BASE_LO; -typedef union CP_ST_BASE_HI regCP_ST_BASE_HI; -typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; -typedef union CPG_PERFCOUNTER1_LO regCPG_PERFCOUNTER1_LO; -typedef union CPG_PERFCOUNTER1_HI regCPG_PERFCOUNTER1_HI; -typedef union CPG_PERFCOUNTER0_LO regCPG_PERFCOUNTER0_LO; -typedef union CPG_PERFCOUNTER0_HI regCPG_PERFCOUNTER0_HI; -typedef union CPC_PERFCOUNTER1_LO regCPC_PERFCOUNTER1_LO; -typedef union CPC_PERFCOUNTER1_HI regCPC_PERFCOUNTER1_HI; -typedef union CPC_PERFCOUNTER0_LO regCPC_PERFCOUNTER0_LO; -typedef union CPC_PERFCOUNTER0_HI regCPC_PERFCOUNTER0_HI; -typedef union CPF_PERFCOUNTER1_LO regCPF_PERFCOUNTER1_LO; -typedef union CPF_PERFCOUNTER1_HI regCPF_PERFCOUNTER1_HI; -typedef union CPF_PERFCOUNTER0_LO regCPF_PERFCOUNTER0_LO; -typedef union CPF_PERFCOUNTER0_HI regCPF_PERFCOUNTER0_HI; -typedef union CPF_LATENCY_STATS_DATA regCPF_LATENCY_STATS_DATA; -typedef union CPG_LATENCY_STATS_DATA regCPG_LATENCY_STATS_DATA; -typedef union CPC_LATENCY_STATS_DATA regCPC_LATENCY_STATS_DATA; -typedef union CPG_PERFCOUNTER1_SELECT regCPG_PERFCOUNTER1_SELECT; -typedef union CPG_PERFCOUNTER0_SELECT1 regCPG_PERFCOUNTER0_SELECT1; -typedef union CPG_PERFCOUNTER0_SELECT regCPG_PERFCOUNTER0_SELECT; -typedef union CPC_PERFCOUNTER1_SELECT regCPC_PERFCOUNTER1_SELECT; -typedef union CPC_PERFCOUNTER0_SELECT1 regCPC_PERFCOUNTER0_SELECT1; -typedef union CPC_PERFCOUNTER0_SELECT regCPC_PERFCOUNTER0_SELECT; -typedef union CPF_PERFCOUNTER1_SELECT regCPF_PERFCOUNTER1_SELECT; -typedef union CPF_PERFCOUNTER0_SELECT1 regCPF_PERFCOUNTER0_SELECT1; -typedef union CPF_PERFCOUNTER0_SELECT regCPF_PERFCOUNTER0_SELECT; -typedef union CPF_TC_PERF_COUNTER_WINDOW_SELECT regCPF_TC_PERF_COUNTER_WINDOW_SELECT; -typedef union CPG_TC_PERF_COUNTER_WINDOW_SELECT regCPG_TC_PERF_COUNTER_WINDOW_SELECT; -typedef union CPF_LATENCY_STATS_SELECT regCPF_LATENCY_STATS_SELECT; -typedef union CPG_LATENCY_STATS_SELECT regCPG_LATENCY_STATS_SELECT; -typedef union CPC_LATENCY_STATS_SELECT regCPC_LATENCY_STATS_SELECT; -typedef union CP_DRAW_OBJECT regCP_DRAW_OBJECT; -typedef union CP_DRAW_OBJECT_COUNTER regCP_DRAW_OBJECT_COUNTER; -typedef union CP_DRAW_WINDOW_MASK_HI regCP_DRAW_WINDOW_MASK_HI; -typedef union CP_DRAW_WINDOW_HI regCP_DRAW_WINDOW_HI; -typedef union CP_DRAW_WINDOW_LO regCP_DRAW_WINDOW_LO; -typedef union CP_DRAW_WINDOW_CNTL regCP_DRAW_WINDOW_CNTL; -typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; -typedef union CGTT_CPC_CLK_CTRL regCGTT_CPC_CLK_CTRL; -typedef union CGTT_CPF_CLK_CTRL regCGTT_CPF_CLK_CTRL; -typedef union CGTT_CP_CLK_CTRL regCGTT_CP_CLK_CTRL; -typedef union CP_HYP_PFP_UCODE_ADDR regCP_HYP_PFP_UCODE_ADDR; -typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; -typedef union CP_HYP_PFP_UCODE_DATA regCP_HYP_PFP_UCODE_DATA; -typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; -typedef union CP_HYP_ME_UCODE_ADDR regCP_HYP_ME_UCODE_ADDR; -typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; -typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; -typedef union CP_HYP_ME_UCODE_DATA regCP_HYP_ME_UCODE_DATA; -typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; -typedef union CP_HYP_CE_UCODE_ADDR regCP_HYP_CE_UCODE_ADDR; -typedef union CP_CE_UCODE_ADDR regCP_CE_UCODE_ADDR; -typedef union CP_HYP_CE_UCODE_DATA regCP_HYP_CE_UCODE_DATA; -typedef union CP_CE_UCODE_DATA regCP_CE_UCODE_DATA; -typedef union CP_HYP_MEC1_UCODE_ADDR regCP_HYP_MEC1_UCODE_ADDR; -typedef union CP_MEC_ME1_UCODE_ADDR regCP_MEC_ME1_UCODE_ADDR; -typedef union CP_HYP_MEC1_UCODE_DATA regCP_HYP_MEC1_UCODE_DATA; -typedef union CP_MEC_ME1_UCODE_DATA regCP_MEC_ME1_UCODE_DATA; -typedef union CP_HYP_MEC2_UCODE_ADDR regCP_HYP_MEC2_UCODE_ADDR; -typedef union CP_MEC_ME2_UCODE_ADDR regCP_MEC_ME2_UCODE_ADDR; -typedef union CP_HYP_MEC2_UCODE_DATA regCP_HYP_MEC2_UCODE_DATA; -typedef union CP_MEC_ME2_UCODE_DATA regCP_MEC_ME2_UCODE_DATA; -typedef union CP_HYP_PFP_UCODE_CHKSUM regCP_HYP_PFP_UCODE_CHKSUM; -typedef union CP_HYP_CE_UCODE_CHKSUM regCP_HYP_CE_UCODE_CHKSUM; -typedef union CP_HYP_ME_UCODE_CHKSUM regCP_HYP_ME_UCODE_CHKSUM; -typedef union CP_HYP_MEC_ME1_UCODE_CHKSUM regCP_HYP_MEC_ME1_UCODE_CHKSUM; -typedef union CP_HYP_MEC_ME2_UCODE_CHKSUM regCP_HYP_MEC_ME2_UCODE_CHKSUM; -typedef union CP_HYP_CONFIG_RANGE_BASE_1 regCP_HYP_CONFIG_RANGE_BASE_1; -typedef union CP_HYP_CONFIG_RANGE_END_1 regCP_HYP_CONFIG_RANGE_END_1; -typedef union CP_HYP_SHADER_RANGE_BASE regCP_HYP_SHADER_RANGE_BASE; -typedef union CP_HYP_SHADER_RANGE_END regCP_HYP_SHADER_RANGE_END; -typedef union CP_HYP_CONFIG_RANGE_BASE_2 regCP_HYP_CONFIG_RANGE_BASE_2; -typedef union CP_HYP_CONFIG_RANGE_END_2 regCP_HYP_CONFIG_RANGE_END_2; -typedef union CP_HYP_CONTEXT_RANGE_BASE regCP_HYP_CONTEXT_RANGE_BASE; -typedef union CP_HYP_CONTEXT_RANGE_END regCP_HYP_CONTEXT_RANGE_END; -typedef union CP_HYP_UCONFIG_RANGE_BASE regCP_HYP_UCONFIG_RANGE_BASE; -typedef union CP_HYP_UCONFIG_RANGE_END regCP_HYP_UCONFIG_RANGE_END; -typedef union CP_HYP_CPC_SECURE_REG0 regCP_HYP_CPC_SECURE_REG0; -typedef union CP_HYP_CPC_SECURE_REG1 regCP_HYP_CPC_SECURE_REG1; -typedef union CP_HYP_CPC_SECURE_REG2 regCP_HYP_CPC_SECURE_REG2; -typedef union CP_HYP_CPC_SECURE_REG3 regCP_HYP_CPC_SECURE_REG3; -typedef union CP_HYP_FIREWALL_MODIFIED_MASK regCP_HYP_FIREWALL_MODIFIED_MASK; -typedef union CP_PSP_REG_PRIV_LEVEL_A regCP_PSP_REG_PRIV_LEVEL_A; -typedef union CP_PSP_REG_PRIV_LEVEL_B regCP_PSP_REG_PRIV_LEVEL_B; -typedef union CP_PSP_REG_PRIV_LEVEL_C regCP_PSP_REG_PRIV_LEVEL_C; -typedef union CP_PSP_REG_PRIV_LEVEL_D regCP_PSP_REG_PRIV_LEVEL_D; -typedef union CP_PSP_REG_PRIV_LEVEL_E regCP_PSP_REG_PRIV_LEVEL_E; -typedef union CP_PSP_REG_PRIV_LEVEL_F regCP_PSP_REG_PRIV_LEVEL_F; -typedef union CP_PSP_REG_PRIV_LEVEL_G regCP_PSP_REG_PRIV_LEVEL_G; -typedef union CP_PSP_REG_PRIV_LEVEL_H regCP_PSP_REG_PRIV_LEVEL_H; -typedef union CP_PSP_REG_PRIV_LEVEL_I regCP_PSP_REG_PRIV_LEVEL_I; -typedef union CP_PSP_REG_PRIV_LEVEL_J regCP_PSP_REG_PRIV_LEVEL_J; -typedef union CP_PSP_REG_PRIV_LEVEL_K regCP_PSP_REG_PRIV_LEVEL_K; -typedef union CP_PSP_REG_PRIV_LEVEL_L regCP_PSP_REG_PRIV_LEVEL_L; -typedef union CP_PSP_REG_PRIV_LEVEL_M regCP_PSP_REG_PRIV_LEVEL_M; -typedef union CP_PSP_REG_PRIV_LEVEL_N regCP_PSP_REG_PRIV_LEVEL_N; -typedef union CP_PSP_REG_PRIV_LEVEL_O regCP_PSP_REG_PRIV_LEVEL_O; -typedef union CP_PSP_REG_PRIV_LEVEL_P regCP_PSP_REG_PRIV_LEVEL_P; -typedef union CPG_PSP_DEBUG regCPG_PSP_DEBUG; -typedef union CPC_PSP_DEBUG regCPC_PSP_DEBUG; -typedef union CPF_PSP_DEBUG regCPF_PSP_DEBUG; -typedef union CP_PSP_FIREWALL_MODIFIED_MASK regCP_PSP_FIREWALL_MODIFIED_MASK; -typedef union SQ_SOPK regSQ_SOPK; -typedef union SQ_VINTRP regSQ_VINTRP; -typedef union SQ_SCRATCH_0 regSQ_SCRATCH_0; -typedef union SQ_VOP3_0 regSQ_VOP3_0; -typedef union SQ_FLAT_0 regSQ_FLAT_0; -typedef union SQ_SMEM_0 regSQ_SMEM_0; -typedef union SQ_VOP3P_0 regSQ_VOP3P_0; -typedef union SQ_EXP_0 regSQ_EXP_0; -typedef union SQ_VOP3P_1 regSQ_VOP3P_1; -typedef union SQ_SOP1 regSQ_SOP1; -typedef union SQ_DS_0 regSQ_DS_0; -typedef union SQ_VOP_DPP regSQ_VOP_DPP; -typedef union SQ_MUBUF_0 regSQ_MUBUF_0; -typedef union SQ_VOP1 regSQ_VOP1; -typedef union SQ_GLBL_0 regSQ_GLBL_0; -typedef union SQ_VOP2 regSQ_VOP2; -typedef union SQ_GLBL_1 regSQ_GLBL_1; -typedef union SQ_MTBUF_0 regSQ_MTBUF_0; -typedef union SQ_SOPP regSQ_SOPP; -typedef union SQ_VOP_SDWA regSQ_VOP_SDWA; -typedef union SQ_VOP3_0_SDST_ENC regSQ_VOP3_0_SDST_ENC; -typedef union SQ_MIMG_0 regSQ_MIMG_0; -typedef union SQ_VOPC regSQ_VOPC; -typedef union SQ_VOP_SDWA_SDST_ENC regSQ_VOP_SDWA_SDST_ENC; -typedef union SQ_EXP_1 regSQ_EXP_1; -typedef union SQ_SMEM_1 regSQ_SMEM_1; -typedef union SQ_MTBUF_1 regSQ_MTBUF_1; -typedef union SQ_FLAT_1 regSQ_FLAT_1; -typedef union SQ_SOPC regSQ_SOPC; -typedef union SQ_MIMG_1 regSQ_MIMG_1; -typedef union SQ_VOP3_1 regSQ_VOP3_1; -typedef union SQ_DS_1 regSQ_DS_1; -typedef union SQ_MUBUF_1 regSQ_MUBUF_1; -typedef union SQ_SOP2 regSQ_SOP2; -typedef union SQ_INST regSQ_INST; -typedef union SQ_SCRATCH_1 regSQ_SCRATCH_1; -typedef union DIDT_IND_INDEX regDIDT_IND_INDEX; -typedef union DIDT_IND_DATA regDIDT_IND_DATA; -typedef union DIDT_SQ_CTRL0 regDIDT_SQ_CTRL0; -typedef union DIDT_SQ_CTRL1 regDIDT_SQ_CTRL1; -typedef union DIDT_SQ_CTRL2 regDIDT_SQ_CTRL2; -typedef union DIDT_SQ_STALL_CTRL regDIDT_SQ_STALL_CTRL; -typedef union DIDT_SQ_TUNING_CTRL regDIDT_SQ_TUNING_CTRL; -typedef union DIDT_SQ_STALL_AUTO_RELEASE_CTRL regDIDT_SQ_STALL_AUTO_RELEASE_CTRL; -typedef union DIDT_SQ_CTRL3 regDIDT_SQ_CTRL3; -typedef union DIDT_SQ_STALL_PATTERN_1_2 regDIDT_SQ_STALL_PATTERN_1_2; -typedef union DIDT_SQ_STALL_PATTERN_3_4 regDIDT_SQ_STALL_PATTERN_3_4; -typedef union DIDT_SQ_STALL_PATTERN_5_6 regDIDT_SQ_STALL_PATTERN_5_6; -typedef union DIDT_SQ_STALL_PATTERN_7 regDIDT_SQ_STALL_PATTERN_7; -typedef union DIDT_SQ_WEIGHT0_3 regDIDT_SQ_WEIGHT0_3; -typedef union DIDT_SQ_WEIGHT4_7 regDIDT_SQ_WEIGHT4_7; -typedef union DIDT_SQ_WEIGHT8_11 regDIDT_SQ_WEIGHT8_11; -typedef union DIDT_SQ_EDC_CTRL regDIDT_SQ_EDC_CTRL; -typedef union DIDT_SQ_EDC_THRESHOLD regDIDT_SQ_EDC_THRESHOLD; -typedef union DIDT_SQ_EDC_STALL_PATTERN_1_2 regDIDT_SQ_EDC_STALL_PATTERN_1_2; -typedef union DIDT_SQ_EDC_STALL_PATTERN_3_4 regDIDT_SQ_EDC_STALL_PATTERN_3_4; -typedef union DIDT_SQ_EDC_STALL_PATTERN_5_6 regDIDT_SQ_EDC_STALL_PATTERN_5_6; -typedef union DIDT_SQ_EDC_STALL_PATTERN_7 regDIDT_SQ_EDC_STALL_PATTERN_7; -typedef union DIDT_SQ_EDC_STATUS regDIDT_SQ_EDC_STATUS; -typedef union DIDT_SQ_EDC_STALL_DELAY_1 regDIDT_SQ_EDC_STALL_DELAY_1; -typedef union DIDT_SQ_EDC_STALL_DELAY_2 regDIDT_SQ_EDC_STALL_DELAY_2; -typedef union DIDT_SQ_EDC_STALL_DELAY_3 regDIDT_SQ_EDC_STALL_DELAY_3; -typedef union DIDT_SQ_EDC_STALL_DELAY_4 regDIDT_SQ_EDC_STALL_DELAY_4; -typedef union DIDT_SQ_EDC_OVERFLOW regDIDT_SQ_EDC_OVERFLOW; -typedef union DIDT_SQ_EDC_ROLLING_POWER_DELTA regDIDT_SQ_EDC_ROLLING_POWER_DELTA; -typedef union DIDT_DB_CTRL0 regDIDT_DB_CTRL0; -typedef union DIDT_DB_CTRL1 regDIDT_DB_CTRL1; -typedef union DIDT_DB_CTRL2 regDIDT_DB_CTRL2; -typedef union DIDT_DB_STALL_CTRL regDIDT_DB_STALL_CTRL; -typedef union DIDT_DB_TUNING_CTRL regDIDT_DB_TUNING_CTRL; -typedef union DIDT_DB_STALL_AUTO_RELEASE_CTRL regDIDT_DB_STALL_AUTO_RELEASE_CTRL; -typedef union DIDT_DB_CTRL3 regDIDT_DB_CTRL3; -typedef union DIDT_DB_STALL_PATTERN_1_2 regDIDT_DB_STALL_PATTERN_1_2; -typedef union DIDT_DB_STALL_PATTERN_3_4 regDIDT_DB_STALL_PATTERN_3_4; -typedef union DIDT_DB_STALL_PATTERN_5_6 regDIDT_DB_STALL_PATTERN_5_6; -typedef union DIDT_DB_STALL_PATTERN_7 regDIDT_DB_STALL_PATTERN_7; -typedef union DIDT_DB_WEIGHT0_3 regDIDT_DB_WEIGHT0_3; -typedef union DIDT_DB_WEIGHT4_7 regDIDT_DB_WEIGHT4_7; -typedef union DIDT_DB_WEIGHT8_11 regDIDT_DB_WEIGHT8_11; -typedef union DIDT_DB_EDC_CTRL regDIDT_DB_EDC_CTRL; -typedef union DIDT_DB_EDC_THRESHOLD regDIDT_DB_EDC_THRESHOLD; -typedef union DIDT_DB_EDC_STALL_PATTERN_1_2 regDIDT_DB_EDC_STALL_PATTERN_1_2; -typedef union DIDT_DB_EDC_STALL_PATTERN_3_4 regDIDT_DB_EDC_STALL_PATTERN_3_4; -typedef union DIDT_DB_EDC_STALL_PATTERN_5_6 regDIDT_DB_EDC_STALL_PATTERN_5_6; -typedef union DIDT_DB_EDC_STALL_PATTERN_7 regDIDT_DB_EDC_STALL_PATTERN_7; -typedef union DIDT_DB_EDC_STATUS regDIDT_DB_EDC_STATUS; -typedef union DIDT_DB_EDC_STALL_DELAY_1 regDIDT_DB_EDC_STALL_DELAY_1; -typedef union DIDT_DB_EDC_OVERFLOW regDIDT_DB_EDC_OVERFLOW; -typedef union DIDT_DB_EDC_ROLLING_POWER_DELTA regDIDT_DB_EDC_ROLLING_POWER_DELTA; -typedef union DIDT_TD_CTRL0 regDIDT_TD_CTRL0; -typedef union DIDT_TD_CTRL1 regDIDT_TD_CTRL1; -typedef union DIDT_TD_CTRL2 regDIDT_TD_CTRL2; -typedef union DIDT_TD_STALL_CTRL regDIDT_TD_STALL_CTRL; -typedef union DIDT_TD_TUNING_CTRL regDIDT_TD_TUNING_CTRL; -typedef union DIDT_TD_STALL_AUTO_RELEASE_CTRL regDIDT_TD_STALL_AUTO_RELEASE_CTRL; -typedef union DIDT_TD_CTRL3 regDIDT_TD_CTRL3; -typedef union DIDT_TD_STALL_PATTERN_1_2 regDIDT_TD_STALL_PATTERN_1_2; -typedef union DIDT_TD_STALL_PATTERN_3_4 regDIDT_TD_STALL_PATTERN_3_4; -typedef union DIDT_TD_STALL_PATTERN_5_6 regDIDT_TD_STALL_PATTERN_5_6; -typedef union DIDT_TD_STALL_PATTERN_7 regDIDT_TD_STALL_PATTERN_7; -typedef union DIDT_TD_WEIGHT0_3 regDIDT_TD_WEIGHT0_3; -typedef union DIDT_TD_WEIGHT4_7 regDIDT_TD_WEIGHT4_7; -typedef union DIDT_TD_WEIGHT8_11 regDIDT_TD_WEIGHT8_11; -typedef union DIDT_TD_EDC_CTRL regDIDT_TD_EDC_CTRL; -typedef union DIDT_TD_EDC_THRESHOLD regDIDT_TD_EDC_THRESHOLD; -typedef union DIDT_TD_EDC_STALL_PATTERN_1_2 regDIDT_TD_EDC_STALL_PATTERN_1_2; -typedef union DIDT_TD_EDC_STALL_PATTERN_3_4 regDIDT_TD_EDC_STALL_PATTERN_3_4; -typedef union DIDT_TD_EDC_STALL_PATTERN_5_6 regDIDT_TD_EDC_STALL_PATTERN_5_6; -typedef union DIDT_TD_EDC_STALL_PATTERN_7 regDIDT_TD_EDC_STALL_PATTERN_7; -typedef union DIDT_TD_EDC_STATUS regDIDT_TD_EDC_STATUS; -typedef union DIDT_TD_EDC_STALL_DELAY_1 regDIDT_TD_EDC_STALL_DELAY_1; -typedef union DIDT_TD_EDC_STALL_DELAY_2 regDIDT_TD_EDC_STALL_DELAY_2; -typedef union DIDT_TD_EDC_STALL_DELAY_3 regDIDT_TD_EDC_STALL_DELAY_3; -typedef union DIDT_TD_EDC_STALL_DELAY_4 regDIDT_TD_EDC_STALL_DELAY_4; -typedef union DIDT_TD_EDC_OVERFLOW regDIDT_TD_EDC_OVERFLOW; -typedef union DIDT_TD_EDC_ROLLING_POWER_DELTA regDIDT_TD_EDC_ROLLING_POWER_DELTA; -typedef union DIDT_TCP_CTRL0 regDIDT_TCP_CTRL0; -typedef union DIDT_TCP_CTRL1 regDIDT_TCP_CTRL1; -typedef union DIDT_TCP_CTRL2 regDIDT_TCP_CTRL2; -typedef union DIDT_TCP_STALL_CTRL regDIDT_TCP_STALL_CTRL; -typedef union DIDT_TCP_TUNING_CTRL regDIDT_TCP_TUNING_CTRL; -typedef union DIDT_TCP_STALL_AUTO_RELEASE_CTRL regDIDT_TCP_STALL_AUTO_RELEASE_CTRL; -typedef union DIDT_TCP_CTRL3 regDIDT_TCP_CTRL3; -typedef union DIDT_TCP_STALL_PATTERN_1_2 regDIDT_TCP_STALL_PATTERN_1_2; -typedef union DIDT_TCP_STALL_PATTERN_3_4 regDIDT_TCP_STALL_PATTERN_3_4; -typedef union DIDT_TCP_STALL_PATTERN_5_6 regDIDT_TCP_STALL_PATTERN_5_6; -typedef union DIDT_TCP_STALL_PATTERN_7 regDIDT_TCP_STALL_PATTERN_7; -typedef union DIDT_TCP_WEIGHT0_3 regDIDT_TCP_WEIGHT0_3; -typedef union DIDT_TCP_WEIGHT4_7 regDIDT_TCP_WEIGHT4_7; -typedef union DIDT_TCP_WEIGHT8_11 regDIDT_TCP_WEIGHT8_11; -typedef union DIDT_TCP_EDC_CTRL regDIDT_TCP_EDC_CTRL; -typedef union DIDT_TCP_EDC_THRESHOLD regDIDT_TCP_EDC_THRESHOLD; -typedef union DIDT_TCP_EDC_STALL_PATTERN_1_2 regDIDT_TCP_EDC_STALL_PATTERN_1_2; -typedef union DIDT_TCP_EDC_STALL_PATTERN_3_4 regDIDT_TCP_EDC_STALL_PATTERN_3_4; -typedef union DIDT_TCP_EDC_STALL_PATTERN_5_6 regDIDT_TCP_EDC_STALL_PATTERN_5_6; -typedef union DIDT_TCP_EDC_STALL_PATTERN_7 regDIDT_TCP_EDC_STALL_PATTERN_7; -typedef union DIDT_TCP_EDC_STATUS regDIDT_TCP_EDC_STATUS; -typedef union DIDT_TCP_EDC_STALL_DELAY_1 regDIDT_TCP_EDC_STALL_DELAY_1; -typedef union DIDT_TCP_EDC_STALL_DELAY_2 regDIDT_TCP_EDC_STALL_DELAY_2; -typedef union DIDT_TCP_EDC_STALL_DELAY_3 regDIDT_TCP_EDC_STALL_DELAY_3; -typedef union DIDT_TCP_EDC_STALL_DELAY_4 regDIDT_TCP_EDC_STALL_DELAY_4; -typedef union DIDT_TCP_EDC_OVERFLOW regDIDT_TCP_EDC_OVERFLOW; -typedef union DIDT_TCP_EDC_ROLLING_POWER_DELTA regDIDT_TCP_EDC_ROLLING_POWER_DELTA; -typedef union DIDT_DBR_CTRL0 regDIDT_DBR_CTRL0; -typedef union DIDT_DBR_CTRL1 regDIDT_DBR_CTRL1; -typedef union DIDT_DBR_CTRL2 regDIDT_DBR_CTRL2; -typedef union DIDT_DBR_STALL_CTRL regDIDT_DBR_STALL_CTRL; -typedef union DIDT_DBR_TUNING_CTRL regDIDT_DBR_TUNING_CTRL; -typedef union DIDT_DBR_STALL_AUTO_RELEASE_CTRL regDIDT_DBR_STALL_AUTO_RELEASE_CTRL; -typedef union DIDT_DBR_CTRL3 regDIDT_DBR_CTRL3; -typedef union DIDT_DBR_STALL_PATTERN_1_2 regDIDT_DBR_STALL_PATTERN_1_2; -typedef union DIDT_DBR_STALL_PATTERN_3_4 regDIDT_DBR_STALL_PATTERN_3_4; -typedef union DIDT_DBR_STALL_PATTERN_5_6 regDIDT_DBR_STALL_PATTERN_5_6; -typedef union DIDT_DBR_STALL_PATTERN_7 regDIDT_DBR_STALL_PATTERN_7; -typedef union DIDT_DBR_WEIGHT0_3 regDIDT_DBR_WEIGHT0_3; -typedef union DIDT_DBR_WEIGHT4_7 regDIDT_DBR_WEIGHT4_7; -typedef union DIDT_DBR_WEIGHT8_11 regDIDT_DBR_WEIGHT8_11; -typedef union DIDT_DBR_EDC_CTRL regDIDT_DBR_EDC_CTRL; -typedef union DIDT_DBR_EDC_THRESHOLD regDIDT_DBR_EDC_THRESHOLD; -typedef union DIDT_DBR_EDC_STALL_PATTERN_1_2 regDIDT_DBR_EDC_STALL_PATTERN_1_2; -typedef union DIDT_DBR_EDC_STALL_PATTERN_3_4 regDIDT_DBR_EDC_STALL_PATTERN_3_4; -typedef union DIDT_DBR_EDC_STALL_PATTERN_5_6 regDIDT_DBR_EDC_STALL_PATTERN_5_6; -typedef union DIDT_DBR_EDC_STALL_PATTERN_7 regDIDT_DBR_EDC_STALL_PATTERN_7; -typedef union DIDT_DBR_EDC_STATUS regDIDT_DBR_EDC_STATUS; -typedef union DIDT_DBR_EDC_STALL_DELAY_1 regDIDT_DBR_EDC_STALL_DELAY_1; -typedef union DIDT_DBR_EDC_OVERFLOW regDIDT_DBR_EDC_OVERFLOW; -typedef union DIDT_DBR_EDC_ROLLING_POWER_DELTA regDIDT_DBR_EDC_ROLLING_POWER_DELTA; -typedef union DIDT_SQ_STALL_EVENT_COUNTER regDIDT_SQ_STALL_EVENT_COUNTER; -typedef union DIDT_DB_STALL_EVENT_COUNTER regDIDT_DB_STALL_EVENT_COUNTER; -typedef union DIDT_TD_STALL_EVENT_COUNTER regDIDT_TD_STALL_EVENT_COUNTER; -typedef union DIDT_TCP_STALL_EVENT_COUNTER regDIDT_TCP_STALL_EVENT_COUNTER; -typedef union DIDT_DBR_STALL_EVENT_COUNTER regDIDT_DBR_STALL_EVENT_COUNTER; -typedef union SX_DEBUG_BUSY regSX_DEBUG_BUSY; -typedef union SX_DEBUG_BUSY_2 regSX_DEBUG_BUSY_2; -typedef union SX_DEBUG_BUSY_3 regSX_DEBUG_BUSY_3; -typedef union SX_DEBUG_BUSY_4 regSX_DEBUG_BUSY_4; -typedef union SX_DEBUG_BUSY_5 regSX_DEBUG_BUSY_5; -typedef union SX_DEBUG_1 regSX_DEBUG_1; -typedef union SX_PS_DOWNCONVERT regSX_PS_DOWNCONVERT; -typedef union SX_BLEND_OPT_EPSILON regSX_BLEND_OPT_EPSILON; -typedef union SX_BLEND_OPT_CONTROL regSX_BLEND_OPT_CONTROL; -typedef union SX_MRT0_BLEND_OPT regSX_MRT0_BLEND_OPT; -typedef union SX_MRT1_BLEND_OPT regSX_MRT1_BLEND_OPT; -typedef union SX_MRT2_BLEND_OPT regSX_MRT2_BLEND_OPT; -typedef union SX_MRT3_BLEND_OPT regSX_MRT3_BLEND_OPT; -typedef union SX_MRT4_BLEND_OPT regSX_MRT4_BLEND_OPT; -typedef union SX_MRT5_BLEND_OPT regSX_MRT5_BLEND_OPT; -typedef union SX_MRT6_BLEND_OPT regSX_MRT6_BLEND_OPT; -typedef union SX_MRT7_BLEND_OPT regSX_MRT7_BLEND_OPT; -typedef union SX_PERFCOUNTER0_LO regSX_PERFCOUNTER0_LO; -typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; -typedef union SX_PERFCOUNTER1_LO regSX_PERFCOUNTER1_LO; -typedef union SX_PERFCOUNTER1_HI regSX_PERFCOUNTER1_HI; -typedef union SX_PERFCOUNTER2_LO regSX_PERFCOUNTER2_LO; -typedef union SX_PERFCOUNTER2_HI regSX_PERFCOUNTER2_HI; -typedef union SX_PERFCOUNTER3_LO regSX_PERFCOUNTER3_LO; -typedef union SX_PERFCOUNTER3_HI regSX_PERFCOUNTER3_HI; -typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; -typedef union SX_PERFCOUNTER1_SELECT regSX_PERFCOUNTER1_SELECT; -typedef union SX_PERFCOUNTER2_SELECT regSX_PERFCOUNTER2_SELECT; -typedef union SX_PERFCOUNTER3_SELECT regSX_PERFCOUNTER3_SELECT; -typedef union SX_PERFCOUNTER0_SELECT1 regSX_PERFCOUNTER0_SELECT1; -typedef union SX_PERFCOUNTER1_SELECT1 regSX_PERFCOUNTER1_SELECT1; -typedef union CGTT_SX_CLK_CTRL0 regCGTT_SX_CLK_CTRL0; -typedef union CGTT_SX_CLK_CTRL1 regCGTT_SX_CLK_CTRL1; -typedef union CGTT_SX_CLK_CTRL2 regCGTT_SX_CLK_CTRL2; -typedef union CGTT_SX_CLK_CTRL3 regCGTT_SX_CLK_CTRL3; -typedef union CGTT_SX_CLK_CTRL4 regCGTT_SX_CLK_CTRL4; -typedef union DB_DEBUG regDB_DEBUG; -typedef union DB_DEBUG2 regDB_DEBUG2; -typedef union DB_DEBUG3 regDB_DEBUG3; -typedef union DB_DEBUG4 regDB_DEBUG4; -typedef union DB_RMI_CACHE_POLICY regDB_RMI_CACHE_POLICY; -typedef union DB_CREDIT_LIMIT regDB_CREDIT_LIMIT; -typedef union DB_WATERMARKS regDB_WATERMARKS; -typedef union DB_EXCEPTION_CONTROL regDB_EXCEPTION_CONTROL; -typedef union DB_SUBTILE_CONTROL regDB_SUBTILE_CONTROL; -typedef union DB_FREE_CACHELINES regDB_FREE_CACHELINES; -typedef union DB_FIFO_DEPTH1 regDB_FIFO_DEPTH1; -typedef union DB_FIFO_DEPTH2 regDB_FIFO_DEPTH2; -typedef union DB_RING_CONTROL regDB_RING_CONTROL; -typedef union DB_MEM_ARB_WATERMARKS regDB_MEM_ARB_WATERMARKS; -typedef union DB_DFSM_CONFIG regDB_DFSM_CONFIG; -typedef union DB_DFSM_WATERMARK regDB_DFSM_WATERMARK; -typedef union DB_DFSM_TILES_IN_FLIGHT regDB_DFSM_TILES_IN_FLIGHT; -typedef union DB_DFSM_PRIMS_IN_FLIGHT regDB_DFSM_PRIMS_IN_FLIGHT; -typedef union DB_DFSM_WATCHDOG regDB_DFSM_WATCHDOG; -typedef union DB_DFSM_FLUSH_ENABLE regDB_DFSM_FLUSH_ENABLE; -typedef union DB_DFSM_FLUSH_AUX_EVENT regDB_DFSM_FLUSH_AUX_EVENT; -typedef union DB_READ_DEBUG_0 regDB_READ_DEBUG_0; -typedef union DB_READ_DEBUG_1 regDB_READ_DEBUG_1; -typedef union DB_READ_DEBUG_2 regDB_READ_DEBUG_2; -typedef union DB_READ_DEBUG_3 regDB_READ_DEBUG_3; -typedef union DB_READ_DEBUG_4 regDB_READ_DEBUG_4; -typedef union DB_READ_DEBUG_5 regDB_READ_DEBUG_5; -typedef union DB_READ_DEBUG_6 regDB_READ_DEBUG_6; -typedef union DB_READ_DEBUG_7 regDB_READ_DEBUG_7; -typedef union DB_READ_DEBUG_8 regDB_READ_DEBUG_8; -typedef union DB_READ_DEBUG_9 regDB_READ_DEBUG_9; -typedef union DB_READ_DEBUG_A regDB_READ_DEBUG_A; -typedef union DB_READ_DEBUG_B regDB_READ_DEBUG_B; -typedef union DB_READ_DEBUG_C regDB_READ_DEBUG_C; -typedef union DB_READ_DEBUG_D regDB_READ_DEBUG_D; -typedef union DB_READ_DEBUG_E regDB_READ_DEBUG_E; -typedef union DB_READ_DEBUG_F regDB_READ_DEBUG_F; -typedef union DB_Z_READ_BASE regDB_Z_READ_BASE; -typedef union DB_Z_READ_BASE_HI regDB_Z_READ_BASE_HI; -typedef union DB_STENCIL_READ_BASE regDB_STENCIL_READ_BASE; -typedef union DB_STENCIL_READ_BASE_HI regDB_STENCIL_READ_BASE_HI; -typedef union DB_Z_WRITE_BASE regDB_Z_WRITE_BASE; -typedef union DB_Z_WRITE_BASE_HI regDB_Z_WRITE_BASE_HI; -typedef union DB_STENCIL_WRITE_BASE regDB_STENCIL_WRITE_BASE; -typedef union DB_STENCIL_WRITE_BASE_HI regDB_STENCIL_WRITE_BASE_HI; -typedef union DB_DFSM_CONTROL regDB_DFSM_CONTROL; -typedef union DB_Z_INFO regDB_Z_INFO; -typedef union DB_Z_INFO2 regDB_Z_INFO2; -typedef union DB_STENCIL_INFO regDB_STENCIL_INFO; -typedef union DB_STENCIL_INFO2 regDB_STENCIL_INFO2; -typedef union DB_DEPTH_SIZE regDB_DEPTH_SIZE; -typedef union DB_DEPTH_VIEW regDB_DEPTH_VIEW; -typedef union DB_RENDER_FILTER regDB_RENDER_FILTER; -typedef union DB_RENDER_CONTROL regDB_RENDER_CONTROL; -typedef union DB_COUNT_CONTROL regDB_COUNT_CONTROL; -typedef union DB_RENDER_OVERRIDE regDB_RENDER_OVERRIDE; -typedef union DB_RENDER_OVERRIDE2 regDB_RENDER_OVERRIDE2; -typedef union DB_EQAA regDB_EQAA; -typedef union DB_SHADER_CONTROL regDB_SHADER_CONTROL; -typedef union DB_DEPTH_BOUNDS_MIN regDB_DEPTH_BOUNDS_MIN; -typedef union DB_DEPTH_BOUNDS_MAX regDB_DEPTH_BOUNDS_MAX; -typedef union DB_STENCIL_CLEAR regDB_STENCIL_CLEAR; -typedef union DB_DEPTH_CLEAR regDB_DEPTH_CLEAR; -typedef union DB_HTILE_DATA_BASE regDB_HTILE_DATA_BASE; -typedef union DB_HTILE_DATA_BASE_HI regDB_HTILE_DATA_BASE_HI; -typedef union DB_HTILE_SURFACE regDB_HTILE_SURFACE; -typedef union DB_PRELOAD_CONTROL regDB_PRELOAD_CONTROL; -typedef union DB_STENCILREFMASK regDB_STENCILREFMASK; -typedef union DB_STENCILREFMASK_BF regDB_STENCILREFMASK_BF; -typedef union DB_SRESULTS_COMPARE_STATE0 regDB_SRESULTS_COMPARE_STATE0; -typedef union DB_SRESULTS_COMPARE_STATE1 regDB_SRESULTS_COMPARE_STATE1; -typedef union DB_DEPTH_CONTROL regDB_DEPTH_CONTROL; -typedef union DB_STENCIL_CONTROL regDB_STENCIL_CONTROL; -typedef union DB_ALPHA_TO_MASK regDB_ALPHA_TO_MASK; -typedef union DB_ZPASS_COUNT_LOW regDB_ZPASS_COUNT_LOW; -typedef union DB_ZPASS_COUNT_HI regDB_ZPASS_COUNT_HI; -typedef union DB_OCCLUSION_COUNT0_LOW regDB_OCCLUSION_COUNT0_LOW; -typedef union DB_OCCLUSION_COUNT0_HI regDB_OCCLUSION_COUNT0_HI; -typedef union DB_OCCLUSION_COUNT1_LOW regDB_OCCLUSION_COUNT1_LOW; -typedef union DB_OCCLUSION_COUNT1_HI regDB_OCCLUSION_COUNT1_HI; -typedef union DB_OCCLUSION_COUNT2_LOW regDB_OCCLUSION_COUNT2_LOW; -typedef union DB_OCCLUSION_COUNT2_HI regDB_OCCLUSION_COUNT2_HI; -typedef union DB_OCCLUSION_COUNT3_LOW regDB_OCCLUSION_COUNT3_LOW; -typedef union DB_OCCLUSION_COUNT3_HI regDB_OCCLUSION_COUNT3_HI; -typedef union DB_PERFCOUNTER0_LO regDB_PERFCOUNTER0_LO; -typedef union DB_PERFCOUNTER1_LO regDB_PERFCOUNTER1_LO; -typedef union DB_PERFCOUNTER2_LO regDB_PERFCOUNTER2_LO; -typedef union DB_PERFCOUNTER3_LO regDB_PERFCOUNTER3_LO; -typedef union DB_PERFCOUNTER0_HI regDB_PERFCOUNTER0_HI; -typedef union DB_PERFCOUNTER1_HI regDB_PERFCOUNTER1_HI; -typedef union DB_PERFCOUNTER2_HI regDB_PERFCOUNTER2_HI; -typedef union DB_PERFCOUNTER3_HI regDB_PERFCOUNTER3_HI; -typedef union DB_PERFCOUNTER0_SELECT regDB_PERFCOUNTER0_SELECT; -typedef union DB_PERFCOUNTER1_SELECT regDB_PERFCOUNTER1_SELECT; -typedef union DB_PERFCOUNTER2_SELECT regDB_PERFCOUNTER2_SELECT; -typedef union DB_PERFCOUNTER3_SELECT regDB_PERFCOUNTER3_SELECT; -typedef union DB_PERFCOUNTER0_SELECT1 regDB_PERFCOUNTER0_SELECT1; -typedef union DB_PERFCOUNTER1_SELECT1 regDB_PERFCOUNTER1_SELECT1; -typedef union DB_CGTT_CLK_CTRL_0 regDB_CGTT_CLK_CTRL_0; -typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; -typedef union PA_CL_RESET_DEBUG regPA_CL_RESET_DEBUG; -typedef union PA_SIDEBAND_REQUEST_DELAYS regPA_SIDEBAND_REQUEST_DELAYS; -typedef union PA_UTCL1_CNTL1 regPA_UTCL1_CNTL1; -typedef union PA_UTCL1_CNTL2 regPA_UTCL1_CNTL2; -typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; -typedef union PA_SC_ENHANCE_1 regPA_SC_ENHANCE_1; -typedef union PA_SC_DSM_CNTL regPA_SC_DSM_CNTL; -typedef union PA_SC_TILE_STEERING_CREST_OVERRIDE regPA_SC_TILE_STEERING_CREST_OVERRIDE; -typedef union PA_SC_FIFO_SIZE regPA_SC_FIFO_SIZE; -typedef union PA_SC_IF_FIFO_SIZE regPA_SC_IF_FIFO_SIZE; -typedef union PA_SC_PKR_WAVE_TABLE_CNTL regPA_SC_PKR_WAVE_TABLE_CNTL; -typedef union PA_SC_FORCE_EOV_MAX_CNTS regPA_SC_FORCE_EOV_MAX_CNTS; -typedef union PA_SC_BINNER_EVENT_CNTL_0 regPA_SC_BINNER_EVENT_CNTL_0; -typedef union PA_SC_BINNER_EVENT_CNTL_1 regPA_SC_BINNER_EVENT_CNTL_1; -typedef union PA_SC_BINNER_EVENT_CNTL_2 regPA_SC_BINNER_EVENT_CNTL_2; -typedef union PA_SC_BINNER_EVENT_CNTL_3 regPA_SC_BINNER_EVENT_CNTL_3; -typedef union PA_SC_BINNER_TIMEOUT_COUNTER regPA_SC_BINNER_TIMEOUT_COUNTER; -typedef union PA_SC_BINNER_PERF_CNTL_0 regPA_SC_BINNER_PERF_CNTL_0; -typedef union PA_SC_BINNER_PERF_CNTL_1 regPA_SC_BINNER_PERF_CNTL_1; -typedef union PA_SC_BINNER_PERF_CNTL_2 regPA_SC_BINNER_PERF_CNTL_2; -typedef union PA_SC_BINNER_PERF_CNTL_3 regPA_SC_BINNER_PERF_CNTL_3; -typedef union PA_SC_P3D_TRAP_SCREEN_HV_LOCK regPA_SC_P3D_TRAP_SCREEN_HV_LOCK; -typedef union PA_SC_HP3D_TRAP_SCREEN_HV_LOCK regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK; -typedef union PA_SC_TRAP_SCREEN_HV_LOCK regPA_SC_TRAP_SCREEN_HV_LOCK; -typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; -typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; -typedef union PA_SC_FIFO_DEPTH_CNTL regPA_SC_FIFO_DEPTH_CNTL; -typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; -typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; -typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; -typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; -typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; -typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; -typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; -typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; -typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; -typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; -typedef union PA_CL_VPORT_XSCALE_1 regPA_CL_VPORT_XSCALE_1; -typedef union PA_CL_VPORT_XSCALE_2 regPA_CL_VPORT_XSCALE_2; -typedef union PA_CL_VPORT_XSCALE_3 regPA_CL_VPORT_XSCALE_3; -typedef union PA_CL_VPORT_XSCALE_4 regPA_CL_VPORT_XSCALE_4; -typedef union PA_CL_VPORT_XSCALE_5 regPA_CL_VPORT_XSCALE_5; -typedef union PA_CL_VPORT_XSCALE_6 regPA_CL_VPORT_XSCALE_6; -typedef union PA_CL_VPORT_XSCALE_7 regPA_CL_VPORT_XSCALE_7; -typedef union PA_CL_VPORT_XSCALE_8 regPA_CL_VPORT_XSCALE_8; -typedef union PA_CL_VPORT_XSCALE_9 regPA_CL_VPORT_XSCALE_9; -typedef union PA_CL_VPORT_XSCALE_10 regPA_CL_VPORT_XSCALE_10; -typedef union PA_CL_VPORT_XSCALE_11 regPA_CL_VPORT_XSCALE_11; -typedef union PA_CL_VPORT_XSCALE_12 regPA_CL_VPORT_XSCALE_12; -typedef union PA_CL_VPORT_XSCALE_13 regPA_CL_VPORT_XSCALE_13; -typedef union PA_CL_VPORT_XSCALE_14 regPA_CL_VPORT_XSCALE_14; -typedef union PA_CL_VPORT_XSCALE_15 regPA_CL_VPORT_XSCALE_15; -typedef union PA_CL_VPORT_XOFFSET_1 regPA_CL_VPORT_XOFFSET_1; -typedef union PA_CL_VPORT_XOFFSET_2 regPA_CL_VPORT_XOFFSET_2; -typedef union PA_CL_VPORT_XOFFSET_3 regPA_CL_VPORT_XOFFSET_3; -typedef union PA_CL_VPORT_XOFFSET_4 regPA_CL_VPORT_XOFFSET_4; -typedef union PA_CL_VPORT_XOFFSET_5 regPA_CL_VPORT_XOFFSET_5; -typedef union PA_CL_VPORT_XOFFSET_6 regPA_CL_VPORT_XOFFSET_6; -typedef union PA_CL_VPORT_XOFFSET_7 regPA_CL_VPORT_XOFFSET_7; -typedef union PA_CL_VPORT_XOFFSET_8 regPA_CL_VPORT_XOFFSET_8; -typedef union PA_CL_VPORT_XOFFSET_9 regPA_CL_VPORT_XOFFSET_9; -typedef union PA_CL_VPORT_XOFFSET_10 regPA_CL_VPORT_XOFFSET_10; -typedef union PA_CL_VPORT_XOFFSET_11 regPA_CL_VPORT_XOFFSET_11; -typedef union PA_CL_VPORT_XOFFSET_12 regPA_CL_VPORT_XOFFSET_12; -typedef union PA_CL_VPORT_XOFFSET_13 regPA_CL_VPORT_XOFFSET_13; -typedef union PA_CL_VPORT_XOFFSET_14 regPA_CL_VPORT_XOFFSET_14; -typedef union PA_CL_VPORT_XOFFSET_15 regPA_CL_VPORT_XOFFSET_15; -typedef union PA_CL_VPORT_YSCALE_1 regPA_CL_VPORT_YSCALE_1; -typedef union PA_CL_VPORT_YSCALE_2 regPA_CL_VPORT_YSCALE_2; -typedef union PA_CL_VPORT_YSCALE_3 regPA_CL_VPORT_YSCALE_3; -typedef union PA_CL_VPORT_YSCALE_4 regPA_CL_VPORT_YSCALE_4; -typedef union PA_CL_VPORT_YSCALE_5 regPA_CL_VPORT_YSCALE_5; -typedef union PA_CL_VPORT_YSCALE_6 regPA_CL_VPORT_YSCALE_6; -typedef union PA_CL_VPORT_YSCALE_7 regPA_CL_VPORT_YSCALE_7; -typedef union PA_CL_VPORT_YSCALE_8 regPA_CL_VPORT_YSCALE_8; -typedef union PA_CL_VPORT_YSCALE_9 regPA_CL_VPORT_YSCALE_9; -typedef union PA_CL_VPORT_YSCALE_10 regPA_CL_VPORT_YSCALE_10; -typedef union PA_CL_VPORT_YSCALE_11 regPA_CL_VPORT_YSCALE_11; -typedef union PA_CL_VPORT_YSCALE_12 regPA_CL_VPORT_YSCALE_12; -typedef union PA_CL_VPORT_YSCALE_13 regPA_CL_VPORT_YSCALE_13; -typedef union PA_CL_VPORT_YSCALE_14 regPA_CL_VPORT_YSCALE_14; -typedef union PA_CL_VPORT_YSCALE_15 regPA_CL_VPORT_YSCALE_15; -typedef union PA_CL_VPORT_YOFFSET_1 regPA_CL_VPORT_YOFFSET_1; -typedef union PA_CL_VPORT_YOFFSET_2 regPA_CL_VPORT_YOFFSET_2; -typedef union PA_CL_VPORT_YOFFSET_3 regPA_CL_VPORT_YOFFSET_3; -typedef union PA_CL_VPORT_YOFFSET_4 regPA_CL_VPORT_YOFFSET_4; -typedef union PA_CL_VPORT_YOFFSET_5 regPA_CL_VPORT_YOFFSET_5; -typedef union PA_CL_VPORT_YOFFSET_6 regPA_CL_VPORT_YOFFSET_6; -typedef union PA_CL_VPORT_YOFFSET_7 regPA_CL_VPORT_YOFFSET_7; -typedef union PA_CL_VPORT_YOFFSET_8 regPA_CL_VPORT_YOFFSET_8; -typedef union PA_CL_VPORT_YOFFSET_9 regPA_CL_VPORT_YOFFSET_9; -typedef union PA_CL_VPORT_YOFFSET_10 regPA_CL_VPORT_YOFFSET_10; -typedef union PA_CL_VPORT_YOFFSET_11 regPA_CL_VPORT_YOFFSET_11; -typedef union PA_CL_VPORT_YOFFSET_12 regPA_CL_VPORT_YOFFSET_12; -typedef union PA_CL_VPORT_YOFFSET_13 regPA_CL_VPORT_YOFFSET_13; -typedef union PA_CL_VPORT_YOFFSET_14 regPA_CL_VPORT_YOFFSET_14; -typedef union PA_CL_VPORT_YOFFSET_15 regPA_CL_VPORT_YOFFSET_15; -typedef union PA_CL_VPORT_ZSCALE_1 regPA_CL_VPORT_ZSCALE_1; -typedef union PA_CL_VPORT_ZSCALE_2 regPA_CL_VPORT_ZSCALE_2; -typedef union PA_CL_VPORT_ZSCALE_3 regPA_CL_VPORT_ZSCALE_3; -typedef union PA_CL_VPORT_ZSCALE_4 regPA_CL_VPORT_ZSCALE_4; -typedef union PA_CL_VPORT_ZSCALE_5 regPA_CL_VPORT_ZSCALE_5; -typedef union PA_CL_VPORT_ZSCALE_6 regPA_CL_VPORT_ZSCALE_6; -typedef union PA_CL_VPORT_ZSCALE_7 regPA_CL_VPORT_ZSCALE_7; -typedef union PA_CL_VPORT_ZSCALE_8 regPA_CL_VPORT_ZSCALE_8; -typedef union PA_CL_VPORT_ZSCALE_9 regPA_CL_VPORT_ZSCALE_9; -typedef union PA_CL_VPORT_ZSCALE_10 regPA_CL_VPORT_ZSCALE_10; -typedef union PA_CL_VPORT_ZSCALE_11 regPA_CL_VPORT_ZSCALE_11; -typedef union PA_CL_VPORT_ZSCALE_12 regPA_CL_VPORT_ZSCALE_12; -typedef union PA_CL_VPORT_ZSCALE_13 regPA_CL_VPORT_ZSCALE_13; -typedef union PA_CL_VPORT_ZSCALE_14 regPA_CL_VPORT_ZSCALE_14; -typedef union PA_CL_VPORT_ZSCALE_15 regPA_CL_VPORT_ZSCALE_15; -typedef union PA_CL_VPORT_ZOFFSET_1 regPA_CL_VPORT_ZOFFSET_1; -typedef union PA_CL_VPORT_ZOFFSET_2 regPA_CL_VPORT_ZOFFSET_2; -typedef union PA_CL_VPORT_ZOFFSET_3 regPA_CL_VPORT_ZOFFSET_3; -typedef union PA_CL_VPORT_ZOFFSET_4 regPA_CL_VPORT_ZOFFSET_4; -typedef union PA_CL_VPORT_ZOFFSET_5 regPA_CL_VPORT_ZOFFSET_5; -typedef union PA_CL_VPORT_ZOFFSET_6 regPA_CL_VPORT_ZOFFSET_6; -typedef union PA_CL_VPORT_ZOFFSET_7 regPA_CL_VPORT_ZOFFSET_7; -typedef union PA_CL_VPORT_ZOFFSET_8 regPA_CL_VPORT_ZOFFSET_8; -typedef union PA_CL_VPORT_ZOFFSET_9 regPA_CL_VPORT_ZOFFSET_9; -typedef union PA_CL_VPORT_ZOFFSET_10 regPA_CL_VPORT_ZOFFSET_10; -typedef union PA_CL_VPORT_ZOFFSET_11 regPA_CL_VPORT_ZOFFSET_11; -typedef union PA_CL_VPORT_ZOFFSET_12 regPA_CL_VPORT_ZOFFSET_12; -typedef union PA_CL_VPORT_ZOFFSET_13 regPA_CL_VPORT_ZOFFSET_13; -typedef union PA_CL_VPORT_ZOFFSET_14 regPA_CL_VPORT_ZOFFSET_14; -typedef union PA_CL_VPORT_ZOFFSET_15 regPA_CL_VPORT_ZOFFSET_15; -typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; -typedef union PA_CL_VS_OUT_CNTL regPA_CL_VS_OUT_CNTL; -typedef union PA_CL_NANINF_CNTL regPA_CL_NANINF_CNTL; -typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; -typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; -typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; -typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; -typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; -typedef union PA_CL_UCP_0_X regPA_CL_UCP_0_X; -typedef union PA_CL_UCP_0_Y regPA_CL_UCP_0_Y; -typedef union PA_CL_UCP_0_Z regPA_CL_UCP_0_Z; -typedef union PA_CL_UCP_0_W regPA_CL_UCP_0_W; -typedef union PA_CL_UCP_1_X regPA_CL_UCP_1_X; -typedef union PA_CL_UCP_1_Y regPA_CL_UCP_1_Y; -typedef union PA_CL_UCP_1_Z regPA_CL_UCP_1_Z; -typedef union PA_CL_UCP_1_W regPA_CL_UCP_1_W; -typedef union PA_CL_UCP_2_X regPA_CL_UCP_2_X; -typedef union PA_CL_UCP_2_Y regPA_CL_UCP_2_Y; -typedef union PA_CL_UCP_2_Z regPA_CL_UCP_2_Z; -typedef union PA_CL_UCP_2_W regPA_CL_UCP_2_W; -typedef union PA_CL_UCP_3_X regPA_CL_UCP_3_X; -typedef union PA_CL_UCP_3_Y regPA_CL_UCP_3_Y; -typedef union PA_CL_UCP_3_Z regPA_CL_UCP_3_Z; -typedef union PA_CL_UCP_3_W regPA_CL_UCP_3_W; -typedef union PA_CL_UCP_4_X regPA_CL_UCP_4_X; -typedef union PA_CL_UCP_4_Y regPA_CL_UCP_4_Y; -typedef union PA_CL_UCP_4_Z regPA_CL_UCP_4_Z; -typedef union PA_CL_UCP_4_W regPA_CL_UCP_4_W; -typedef union PA_CL_UCP_5_X regPA_CL_UCP_5_X; -typedef union PA_CL_UCP_5_Y regPA_CL_UCP_5_Y; -typedef union PA_CL_UCP_5_Z regPA_CL_UCP_5_Z; -typedef union PA_CL_UCP_5_W regPA_CL_UCP_5_W; -typedef union PA_CL_POINT_X_RAD regPA_CL_POINT_X_RAD; -typedef union PA_CL_POINT_Y_RAD regPA_CL_POINT_Y_RAD; -typedef union PA_CL_POINT_SIZE regPA_CL_POINT_SIZE; -typedef union PA_CL_POINT_CULL_RAD regPA_CL_POINT_CULL_RAD; -typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; -typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; -typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; -typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; -typedef union PA_SU_LINE_STIPPLE_CNTL regPA_SU_LINE_STIPPLE_CNTL; -typedef union PA_SU_LINE_STIPPLE_SCALE regPA_SU_LINE_STIPPLE_SCALE; -typedef union PA_SU_PRIM_FILTER_CNTL regPA_SU_PRIM_FILTER_CNTL; -typedef union PA_SU_SMALL_PRIM_FILTER_CNTL regPA_SU_SMALL_PRIM_FILTER_CNTL; -typedef union PA_CL_OBJPRIM_ID_CNTL regPA_CL_OBJPRIM_ID_CNTL; -typedef union PA_CL_NGG_CNTL regPA_CL_NGG_CNTL; -typedef union PA_SU_OVER_RASTERIZATION_CNTL regPA_SU_OVER_RASTERIZATION_CNTL; -typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; -typedef union PA_SU_POLY_OFFSET_DB_FMT_CNTL regPA_SU_POLY_OFFSET_DB_FMT_CNTL; -typedef union PA_SU_POLY_OFFSET_CLAMP regPA_SU_POLY_OFFSET_CLAMP; -typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; -typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; -typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; -typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; -typedef union PA_SU_HARDWARE_SCREEN_OFFSET regPA_SU_HARDWARE_SCREEN_OFFSET; -typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; -typedef union PA_SC_AA_MASK_X0Y0_X1Y0 regPA_SC_AA_MASK_X0Y0_X1Y0; -typedef union PA_SC_AA_MASK_X0Y1_X1Y1 regPA_SC_AA_MASK_X0Y1_X1Y1; -typedef union PA_SC_SHADER_CONTROL regPA_SC_SHADER_CONTROL; -typedef union PA_SC_BINNER_CNTL_0 regPA_SC_BINNER_CNTL_0; -typedef union PA_SC_BINNER_CNTL_1 regPA_SC_BINNER_CNTL_1; -typedef union PA_SC_CONSERVATIVE_RASTERIZATION_CNTL regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL; -typedef union PA_SC_NGG_MODE_CNTL regPA_SC_NGG_MODE_CNTL; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2; -typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3; -typedef union PA_SC_CENTROID_PRIORITY_0 regPA_SC_CENTROID_PRIORITY_0; -typedef union PA_SC_CENTROID_PRIORITY_1 regPA_SC_CENTROID_PRIORITY_1; -typedef union PA_SC_CLIPRECT_0_TL regPA_SC_CLIPRECT_0_TL; -typedef union PA_SC_CLIPRECT_0_BR regPA_SC_CLIPRECT_0_BR; -typedef union PA_SC_CLIPRECT_1_TL regPA_SC_CLIPRECT_1_TL; -typedef union PA_SC_CLIPRECT_1_BR regPA_SC_CLIPRECT_1_BR; -typedef union PA_SC_CLIPRECT_2_TL regPA_SC_CLIPRECT_2_TL; -typedef union PA_SC_CLIPRECT_2_BR regPA_SC_CLIPRECT_2_BR; -typedef union PA_SC_CLIPRECT_3_TL regPA_SC_CLIPRECT_3_TL; -typedef union PA_SC_CLIPRECT_3_BR regPA_SC_CLIPRECT_3_BR; -typedef union PA_SC_CLIPRECT_RULE regPA_SC_CLIPRECT_RULE; -typedef union PA_SC_EDGERULE regPA_SC_EDGERULE; -typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; -typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; -typedef union PA_SC_MODE_CNTL_0 regPA_SC_MODE_CNTL_0; -typedef union PA_SC_MODE_CNTL_1 regPA_SC_MODE_CNTL_1; -typedef union PA_SC_RASTER_CONFIG regPA_SC_RASTER_CONFIG; -typedef union PA_SC_RASTER_CONFIG_1 regPA_SC_RASTER_CONFIG_1; -typedef union PA_SC_SCREEN_EXTENT_CONTROL regPA_SC_SCREEN_EXTENT_CONTROL; -typedef union PA_SC_TILE_STEERING_OVERRIDE regPA_SC_TILE_STEERING_OVERRIDE; -typedef union PA_SC_RIGHT_VERT_GRID regPA_SC_RIGHT_VERT_GRID; -typedef union PA_SC_LEFT_VERT_GRID regPA_SC_LEFT_VERT_GRID; -typedef union PA_SC_HORIZ_GRID regPA_SC_HORIZ_GRID; -typedef union PA_SC_FOV_WINDOW_LR regPA_SC_FOV_WINDOW_LR; -typedef union PA_SC_FOV_WINDOW_TB regPA_SC_FOV_WINDOW_TB; -typedef union PA_SC_GENERIC_SCISSOR_TL regPA_SC_GENERIC_SCISSOR_TL; -typedef union PA_SC_GENERIC_SCISSOR_BR regPA_SC_GENERIC_SCISSOR_BR; -typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; -typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; -typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; -typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; -typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; -typedef union PA_SC_VPORT_SCISSOR_0_TL regPA_SC_VPORT_SCISSOR_0_TL; -typedef union PA_SC_VPORT_SCISSOR_1_TL regPA_SC_VPORT_SCISSOR_1_TL; -typedef union PA_SC_VPORT_SCISSOR_2_TL regPA_SC_VPORT_SCISSOR_2_TL; -typedef union PA_SC_VPORT_SCISSOR_3_TL regPA_SC_VPORT_SCISSOR_3_TL; -typedef union PA_SC_VPORT_SCISSOR_4_TL regPA_SC_VPORT_SCISSOR_4_TL; -typedef union PA_SC_VPORT_SCISSOR_5_TL regPA_SC_VPORT_SCISSOR_5_TL; -typedef union PA_SC_VPORT_SCISSOR_6_TL regPA_SC_VPORT_SCISSOR_6_TL; -typedef union PA_SC_VPORT_SCISSOR_7_TL regPA_SC_VPORT_SCISSOR_7_TL; -typedef union PA_SC_VPORT_SCISSOR_8_TL regPA_SC_VPORT_SCISSOR_8_TL; -typedef union PA_SC_VPORT_SCISSOR_9_TL regPA_SC_VPORT_SCISSOR_9_TL; -typedef union PA_SC_VPORT_SCISSOR_10_TL regPA_SC_VPORT_SCISSOR_10_TL; -typedef union PA_SC_VPORT_SCISSOR_11_TL regPA_SC_VPORT_SCISSOR_11_TL; -typedef union PA_SC_VPORT_SCISSOR_12_TL regPA_SC_VPORT_SCISSOR_12_TL; -typedef union PA_SC_VPORT_SCISSOR_13_TL regPA_SC_VPORT_SCISSOR_13_TL; -typedef union PA_SC_VPORT_SCISSOR_14_TL regPA_SC_VPORT_SCISSOR_14_TL; -typedef union PA_SC_VPORT_SCISSOR_15_TL regPA_SC_VPORT_SCISSOR_15_TL; -typedef union PA_SC_VPORT_SCISSOR_0_BR regPA_SC_VPORT_SCISSOR_0_BR; -typedef union PA_SC_VPORT_SCISSOR_1_BR regPA_SC_VPORT_SCISSOR_1_BR; -typedef union PA_SC_VPORT_SCISSOR_2_BR regPA_SC_VPORT_SCISSOR_2_BR; -typedef union PA_SC_VPORT_SCISSOR_3_BR regPA_SC_VPORT_SCISSOR_3_BR; -typedef union PA_SC_VPORT_SCISSOR_4_BR regPA_SC_VPORT_SCISSOR_4_BR; -typedef union PA_SC_VPORT_SCISSOR_5_BR regPA_SC_VPORT_SCISSOR_5_BR; -typedef union PA_SC_VPORT_SCISSOR_6_BR regPA_SC_VPORT_SCISSOR_6_BR; -typedef union PA_SC_VPORT_SCISSOR_7_BR regPA_SC_VPORT_SCISSOR_7_BR; -typedef union PA_SC_VPORT_SCISSOR_8_BR regPA_SC_VPORT_SCISSOR_8_BR; -typedef union PA_SC_VPORT_SCISSOR_9_BR regPA_SC_VPORT_SCISSOR_9_BR; -typedef union PA_SC_VPORT_SCISSOR_10_BR regPA_SC_VPORT_SCISSOR_10_BR; -typedef union PA_SC_VPORT_SCISSOR_11_BR regPA_SC_VPORT_SCISSOR_11_BR; -typedef union PA_SC_VPORT_SCISSOR_12_BR regPA_SC_VPORT_SCISSOR_12_BR; -typedef union PA_SC_VPORT_SCISSOR_13_BR regPA_SC_VPORT_SCISSOR_13_BR; -typedef union PA_SC_VPORT_SCISSOR_14_BR regPA_SC_VPORT_SCISSOR_14_BR; -typedef union PA_SC_VPORT_SCISSOR_15_BR regPA_SC_VPORT_SCISSOR_15_BR; -typedef union PA_SC_VPORT_ZMIN_0 regPA_SC_VPORT_ZMIN_0; -typedef union PA_SC_VPORT_ZMIN_1 regPA_SC_VPORT_ZMIN_1; -typedef union PA_SC_VPORT_ZMIN_2 regPA_SC_VPORT_ZMIN_2; -typedef union PA_SC_VPORT_ZMIN_3 regPA_SC_VPORT_ZMIN_3; -typedef union PA_SC_VPORT_ZMIN_4 regPA_SC_VPORT_ZMIN_4; -typedef union PA_SC_VPORT_ZMIN_5 regPA_SC_VPORT_ZMIN_5; -typedef union PA_SC_VPORT_ZMIN_6 regPA_SC_VPORT_ZMIN_6; -typedef union PA_SC_VPORT_ZMIN_7 regPA_SC_VPORT_ZMIN_7; -typedef union PA_SC_VPORT_ZMIN_8 regPA_SC_VPORT_ZMIN_8; -typedef union PA_SC_VPORT_ZMIN_9 regPA_SC_VPORT_ZMIN_9; -typedef union PA_SC_VPORT_ZMIN_10 regPA_SC_VPORT_ZMIN_10; -typedef union PA_SC_VPORT_ZMIN_11 regPA_SC_VPORT_ZMIN_11; -typedef union PA_SC_VPORT_ZMIN_12 regPA_SC_VPORT_ZMIN_12; -typedef union PA_SC_VPORT_ZMIN_13 regPA_SC_VPORT_ZMIN_13; -typedef union PA_SC_VPORT_ZMIN_14 regPA_SC_VPORT_ZMIN_14; -typedef union PA_SC_VPORT_ZMIN_15 regPA_SC_VPORT_ZMIN_15; -typedef union PA_SC_VPORT_ZMAX_0 regPA_SC_VPORT_ZMAX_0; -typedef union PA_SC_VPORT_ZMAX_1 regPA_SC_VPORT_ZMAX_1; -typedef union PA_SC_VPORT_ZMAX_2 regPA_SC_VPORT_ZMAX_2; -typedef union PA_SC_VPORT_ZMAX_3 regPA_SC_VPORT_ZMAX_3; -typedef union PA_SC_VPORT_ZMAX_4 regPA_SC_VPORT_ZMAX_4; -typedef union PA_SC_VPORT_ZMAX_5 regPA_SC_VPORT_ZMAX_5; -typedef union PA_SC_VPORT_ZMAX_6 regPA_SC_VPORT_ZMAX_6; -typedef union PA_SC_VPORT_ZMAX_7 regPA_SC_VPORT_ZMAX_7; -typedef union PA_SC_VPORT_ZMAX_8 regPA_SC_VPORT_ZMAX_8; -typedef union PA_SC_VPORT_ZMAX_9 regPA_SC_VPORT_ZMAX_9; -typedef union PA_SC_VPORT_ZMAX_10 regPA_SC_VPORT_ZMAX_10; -typedef union PA_SC_VPORT_ZMAX_11 regPA_SC_VPORT_ZMAX_11; -typedef union PA_SC_VPORT_ZMAX_12 regPA_SC_VPORT_ZMAX_12; -typedef union PA_SC_VPORT_ZMAX_13 regPA_SC_VPORT_ZMAX_13; -typedef union PA_SC_VPORT_ZMAX_14 regPA_SC_VPORT_ZMAX_14; -typedef union PA_SC_VPORT_ZMAX_15 regPA_SC_VPORT_ZMAX_15; -typedef union PA_SU_LINE_STIPPLE_VALUE regPA_SU_LINE_STIPPLE_VALUE; -typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; -typedef union PA_SC_SCREEN_EXTENT_MIN_0 regPA_SC_SCREEN_EXTENT_MIN_0; -typedef union PA_SC_SCREEN_EXTENT_MAX_0 regPA_SC_SCREEN_EXTENT_MAX_0; -typedef union PA_SC_SCREEN_EXTENT_MIN_1 regPA_SC_SCREEN_EXTENT_MIN_1; -typedef union PA_SC_SCREEN_EXTENT_MAX_1 regPA_SC_SCREEN_EXTENT_MAX_1; -typedef union PA_SC_P3D_TRAP_SCREEN_HV_EN regPA_SC_P3D_TRAP_SCREEN_HV_EN; -typedef union PA_SC_P3D_TRAP_SCREEN_H regPA_SC_P3D_TRAP_SCREEN_H; -typedef union PA_SC_P3D_TRAP_SCREEN_V regPA_SC_P3D_TRAP_SCREEN_V; -typedef union PA_SC_P3D_TRAP_SCREEN_OCCURRENCE regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE; -typedef union PA_SC_P3D_TRAP_SCREEN_COUNT regPA_SC_P3D_TRAP_SCREEN_COUNT; -typedef union PA_SC_HP3D_TRAP_SCREEN_HV_EN regPA_SC_HP3D_TRAP_SCREEN_HV_EN; -typedef union PA_SC_HP3D_TRAP_SCREEN_H regPA_SC_HP3D_TRAP_SCREEN_H; -typedef union PA_SC_HP3D_TRAP_SCREEN_V regPA_SC_HP3D_TRAP_SCREEN_V; -typedef union PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE; -typedef union PA_SC_HP3D_TRAP_SCREEN_COUNT regPA_SC_HP3D_TRAP_SCREEN_COUNT; -typedef union PA_SC_TRAP_SCREEN_HV_EN regPA_SC_TRAP_SCREEN_HV_EN; -typedef union PA_SC_TRAP_SCREEN_H regPA_SC_TRAP_SCREEN_H; -typedef union PA_SC_TRAP_SCREEN_V regPA_SC_TRAP_SCREEN_V; -typedef union PA_SC_TRAP_SCREEN_OCCURRENCE regPA_SC_TRAP_SCREEN_OCCURRENCE; -typedef union PA_SC_TRAP_SCREEN_COUNT regPA_SC_TRAP_SCREEN_COUNT; -typedef union PA_SU_PERFCOUNTER0_LO regPA_SU_PERFCOUNTER0_LO; -typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; -typedef union PA_SU_PERFCOUNTER1_LO regPA_SU_PERFCOUNTER1_LO; -typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; -typedef union PA_SU_PERFCOUNTER2_LO regPA_SU_PERFCOUNTER2_LO; -typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; -typedef union PA_SU_PERFCOUNTER3_LO regPA_SU_PERFCOUNTER3_LO; -typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; -typedef union PA_SC_PERFCOUNTER0_LO regPA_SC_PERFCOUNTER0_LO; -typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; -typedef union PA_SC_PERFCOUNTER1_LO regPA_SC_PERFCOUNTER1_LO; -typedef union PA_SC_PERFCOUNTER1_HI regPA_SC_PERFCOUNTER1_HI; -typedef union PA_SC_PERFCOUNTER2_LO regPA_SC_PERFCOUNTER2_LO; -typedef union PA_SC_PERFCOUNTER2_HI regPA_SC_PERFCOUNTER2_HI; -typedef union PA_SC_PERFCOUNTER3_LO regPA_SC_PERFCOUNTER3_LO; -typedef union PA_SC_PERFCOUNTER3_HI regPA_SC_PERFCOUNTER3_HI; -typedef union PA_SC_PERFCOUNTER4_LO regPA_SC_PERFCOUNTER4_LO; -typedef union PA_SC_PERFCOUNTER4_HI regPA_SC_PERFCOUNTER4_HI; -typedef union PA_SC_PERFCOUNTER5_LO regPA_SC_PERFCOUNTER5_LO; -typedef union PA_SC_PERFCOUNTER5_HI regPA_SC_PERFCOUNTER5_HI; -typedef union PA_SC_PERFCOUNTER6_LO regPA_SC_PERFCOUNTER6_LO; -typedef union PA_SC_PERFCOUNTER6_HI regPA_SC_PERFCOUNTER6_HI; -typedef union PA_SC_PERFCOUNTER7_LO regPA_SC_PERFCOUNTER7_LO; -typedef union PA_SC_PERFCOUNTER7_HI regPA_SC_PERFCOUNTER7_HI; -typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; -typedef union PA_SU_PERFCOUNTER0_SELECT1 regPA_SU_PERFCOUNTER0_SELECT1; -typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; -typedef union PA_SU_PERFCOUNTER1_SELECT1 regPA_SU_PERFCOUNTER1_SELECT1; -typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; -typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; -typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; -typedef union PA_SC_PERFCOUNTER0_SELECT1 regPA_SC_PERFCOUNTER0_SELECT1; -typedef union PA_SC_PERFCOUNTER1_SELECT regPA_SC_PERFCOUNTER1_SELECT; -typedef union PA_SC_PERFCOUNTER2_SELECT regPA_SC_PERFCOUNTER2_SELECT; -typedef union PA_SC_PERFCOUNTER3_SELECT regPA_SC_PERFCOUNTER3_SELECT; -typedef union PA_SC_PERFCOUNTER4_SELECT regPA_SC_PERFCOUNTER4_SELECT; -typedef union PA_SC_PERFCOUNTER5_SELECT regPA_SC_PERFCOUNTER5_SELECT; -typedef union PA_SC_PERFCOUNTER6_SELECT regPA_SC_PERFCOUNTER6_SELECT; -typedef union PA_SC_PERFCOUNTER7_SELECT regPA_SC_PERFCOUNTER7_SELECT; -typedef union CGTT_PA_CLK_CTRL regCGTT_PA_CLK_CTRL; -typedef union CGTT_SC_CLK_CTRL0 regCGTT_SC_CLK_CTRL0; -typedef union CGTT_SC_CLK_CTRL1 regCGTT_SC_CLK_CTRL1; -typedef union CLIPPER_DEBUG_REG00 regCLIPPER_DEBUG_REG00; -typedef union CLIPPER_DEBUG_REG01 regCLIPPER_DEBUG_REG01; -typedef union CLIPPER_DEBUG_REG02 regCLIPPER_DEBUG_REG02; -typedef union CLIPPER_DEBUG_REG03 regCLIPPER_DEBUG_REG03; -typedef union CLIPPER_DEBUG_REG04 regCLIPPER_DEBUG_REG04; -typedef union CLIPPER_DEBUG_REG05 regCLIPPER_DEBUG_REG05; -typedef union CLIPPER_DEBUG_REG06 regCLIPPER_DEBUG_REG06; -typedef union CLIPPER_DEBUG_REG07 regCLIPPER_DEBUG_REG07; -typedef union CLIPPER_DEBUG_REG08 regCLIPPER_DEBUG_REG08; -typedef union CLIPPER_DEBUG_REG09 regCLIPPER_DEBUG_REG09; -typedef union CLIPPER_DEBUG_REG10 regCLIPPER_DEBUG_REG10; -typedef union CLIPPER_DEBUG_REG11 regCLIPPER_DEBUG_REG11; -typedef union CLIPPER_DEBUG_REG12 regCLIPPER_DEBUG_REG12; -typedef union CLIPPER_DEBUG_REG13 regCLIPPER_DEBUG_REG13; -typedef union CLIPPER_DEBUG_REG14 regCLIPPER_DEBUG_REG14; -typedef union CLIPPER_DEBUG_REG15 regCLIPPER_DEBUG_REG15; -typedef union CLIPPER_DEBUG_REG16 regCLIPPER_DEBUG_REG16; -typedef union CLIPPER_DEBUG_REG17 regCLIPPER_DEBUG_REG17; -typedef union CLIPPER_DEBUG_REG18 regCLIPPER_DEBUG_REG18; -typedef union CLIPPER_DEBUG_REG19 regCLIPPER_DEBUG_REG19; -typedef union SXIFCCG_DEBUG_REG0 regSXIFCCG_DEBUG_REG0; -typedef union SXIFCCG_DEBUG_REG1 regSXIFCCG_DEBUG_REG1; -typedef union SXIFCCG_DEBUG_REG2 regSXIFCCG_DEBUG_REG2; -typedef union SXIFCCG_DEBUG_REG3 regSXIFCCG_DEBUG_REG3; -typedef union SETUP_DEBUG_REG0 regSETUP_DEBUG_REG0; -typedef union SETUP_DEBUG_REG1 regSETUP_DEBUG_REG1; -typedef union SETUP_DEBUG_REG2 regSETUP_DEBUG_REG2; -typedef union SETUP_DEBUG_REG3 regSETUP_DEBUG_REG3; -typedef union SETUP_DEBUG_REG4 regSETUP_DEBUG_REG4; -typedef union SETUP_DEBUG_REG5 regSETUP_DEBUG_REG5; -typedef union PA_SC_DEBUG_REG0 regPA_SC_DEBUG_REG0; -typedef union PA_SC_DEBUG_REG1 regPA_SC_DEBUG_REG1; -typedef union RMI_GENERAL_CNTL regRMI_GENERAL_CNTL; -typedef union RMI_GENERAL_CNTL1 regRMI_GENERAL_CNTL1; -typedef union RMI_GENERAL_STATUS regRMI_GENERAL_STATUS; -typedef union RMI_SUBBLOCK_STATUS0 regRMI_SUBBLOCK_STATUS0; -typedef union RMI_SUBBLOCK_STATUS1 regRMI_SUBBLOCK_STATUS1; -typedef union RMI_SUBBLOCK_STATUS2 regRMI_SUBBLOCK_STATUS2; -typedef union RMI_SUBBLOCK_STATUS3 regRMI_SUBBLOCK_STATUS3; -typedef union RMI_XBAR_CONFIG regRMI_XBAR_CONFIG; -typedef union RMI_PROBE_POP_LOGIC_CNTL regRMI_PROBE_POP_LOGIC_CNTL; -typedef union RMI_UTC_XNACK_N_MISC_CNTL regRMI_UTC_XNACK_N_MISC_CNTL; -typedef union RMI_DEMUX_CNTL regRMI_DEMUX_CNTL; -typedef union RMI_UTCL1_CNTL1 regRMI_UTCL1_CNTL1; -typedef union RMI_UTCL1_CNTL2 regRMI_UTCL1_CNTL2; -typedef union RMI_UTC_UNIT_CONFIG regRMI_UTC_UNIT_CONFIG; -typedef union RMI_TCIW_FORMATTER0_CNTL regRMI_TCIW_FORMATTER0_CNTL; -typedef union RMI_TCIW_FORMATTER1_CNTL regRMI_TCIW_FORMATTER1_CNTL; -typedef union RMI_SCOREBOARD_CNTL regRMI_SCOREBOARD_CNTL; -typedef union RMI_SCOREBOARD_STATUS0 regRMI_SCOREBOARD_STATUS0; -typedef union RMI_SCOREBOARD_STATUS1 regRMI_SCOREBOARD_STATUS1; -typedef union RMI_SCOREBOARD_STATUS2 regRMI_SCOREBOARD_STATUS2; -typedef union RMI_XBAR_ARBITER_CONFIG regRMI_XBAR_ARBITER_CONFIG; -typedef union RMI_XBAR_ARBITER_CONFIG_1 regRMI_XBAR_ARBITER_CONFIG_1; -typedef union RMI_CLOCK_CNTRL regRMI_CLOCK_CNTRL; -typedef union RMI_UTCL1_STATUS regRMI_UTCL1_STATUS; -typedef union RMI_DEBUG0 regRMI_DEBUG0; -typedef union RMI_DEBUG1 regRMI_DEBUG1; -typedef union RMI_DEBUG2 regRMI_DEBUG2; -typedef union RMI_DEBUG3 regRMI_DEBUG3; -typedef union RMI_DEBUG4 regRMI_DEBUG4; -typedef union RMI_XNACK_DEBUG regRMI_XNACK_DEBUG; -typedef union RMI_SPARE regRMI_SPARE; -typedef union RMI_SPARE_1 regRMI_SPARE_1; -typedef union RMI_SPARE_2 regRMI_SPARE_2; -typedef union RMI_PERFCOUNTER0_LO regRMI_PERFCOUNTER0_LO; -typedef union RMI_PERFCOUNTER1_LO regRMI_PERFCOUNTER1_LO; -typedef union RMI_PERFCOUNTER2_LO regRMI_PERFCOUNTER2_LO; -typedef union RMI_PERFCOUNTER3_LO regRMI_PERFCOUNTER3_LO; -typedef union RMI_PERFCOUNTER0_HI regRMI_PERFCOUNTER0_HI; -typedef union RMI_PERFCOUNTER1_HI regRMI_PERFCOUNTER1_HI; -typedef union RMI_PERFCOUNTER2_HI regRMI_PERFCOUNTER2_HI; -typedef union RMI_PERFCOUNTER3_HI regRMI_PERFCOUNTER3_HI; -typedef union RMI_PERFCOUNTER0_SELECT regRMI_PERFCOUNTER0_SELECT; -typedef union RMI_PERFCOUNTER0_SELECT1 regRMI_PERFCOUNTER0_SELECT1; -typedef union RMI_PERFCOUNTER1_SELECT regRMI_PERFCOUNTER1_SELECT; -typedef union RMI_PERFCOUNTER2_SELECT regRMI_PERFCOUNTER2_SELECT; -typedef union RMI_PERFCOUNTER2_SELECT1 regRMI_PERFCOUNTER2_SELECT1; -typedef union RMI_PERFCOUNTER3_SELECT regRMI_PERFCOUNTER3_SELECT; -typedef union RMI_PERF_COUNTER_CNTL regRMI_PERF_COUNTER_CNTL; -typedef union RMI_CGTT_SCLK_CTRL regRMI_CGTT_SCLK_CTRL; -typedef union port_a_addr regport_a_addr; -typedef union port_a_data_lo regport_a_data_lo; -typedef union port_a_data_hi regport_a_data_hi; -typedef union port_b_addr regport_b_addr; -typedef union port_b_data_lo regport_b_data_lo; -typedef union port_b_data_hi regport_b_data_hi; -typedef union port_c_addr regport_c_addr; -typedef union port_c_data_lo regport_c_data_lo; -typedef union port_c_data_hi regport_c_data_hi; -typedef union port_d_addr regport_d_addr; -typedef union port_d_data_lo regport_d_data_lo; -typedef union port_d_data_hi regport_d_data_hi; -typedef union DEBUG_BUS_RSMU regDEBUG_BUS_RSMU; -typedef union DEBUG_BUS_RLC regDEBUG_BUS_RLC; -typedef union DEBUG_BUS_ME0PIPE0_PF regDEBUG_BUS_ME0PIPE0_PF; -typedef union DEBUG_BUS_ME0PIPE0_CF regDEBUG_BUS_ME0PIPE0_CF; -typedef union DEBUG_BUS_ME0PIPE1_PF regDEBUG_BUS_ME0PIPE1_PF; -typedef union DEBUG_BUS_ME0PIPE1_CF regDEBUG_BUS_ME0PIPE1_CF; -typedef union DEBUG_BUS_ME1PIPE0 regDEBUG_BUS_ME1PIPE0; -typedef union DEBUG_BUS_ME1PIPE1 regDEBUG_BUS_ME1PIPE1; -typedef union DEBUG_BUS_ME1PIPE2 regDEBUG_BUS_ME1PIPE2; -typedef union DEBUG_BUS_ME1PIPE3 regDEBUG_BUS_ME1PIPE3; -typedef union DEBUG_BUS_ME2PIPE0 regDEBUG_BUS_ME2PIPE0; -typedef union DEBUG_BUS_ME2PIPE1 regDEBUG_BUS_ME2PIPE1; -typedef union DEBUG_BUS_ME2PIPE2 regDEBUG_BUS_ME2PIPE2; -typedef union DEBUG_BUS_ME2PIPE3 regDEBUG_BUS_ME2PIPE3; -typedef union DEBUG_BUS_GDS_DMA regDEBUG_BUS_GDS_DMA; -typedef union DEBUG_BUS_SCH0 regDEBUG_BUS_SCH0; -typedef union DEBUG_BUS_SCH1 regDEBUG_BUS_SCH1; -typedef union DEBUG_BUS_SCH2 regDEBUG_BUS_SCH2; -typedef union DEBUG_BUS_SCH3 regDEBUG_BUS_SCH3; -typedef union DEBUG_BUS_SCH_CNTL0 regDEBUG_BUS_SCH_CNTL0; -typedef union DEBUG_BUS_SCH_CNTL1 regDEBUG_BUS_SCH_CNTL1; -typedef union DEBUG_BUS_SCH_CNTL2 regDEBUG_BUS_SCH_CNTL2; -typedef union DEBUG_BUS_SCH_CNTL3 regDEBUG_BUS_SCH_CNTL3; -typedef union DEBUG_BUS_SCH_CNTL4 regDEBUG_BUS_SCH_CNTL4; -typedef union DEBUG_BUS_SCH_ME0PIPE0_WD_DMA regDEBUG_BUS_SCH_ME0PIPE0_WD_DMA; -typedef union DEBUG_BUS_SCH_ME0PIPE1_WD_DMA regDEBUG_BUS_SCH_ME0PIPE1_WD_DMA; -typedef union DEBUG_BUS_SCH_HAND0 regDEBUG_BUS_SCH_HAND0; -typedef union DEBUG_BUS_SCH_HAND1 regDEBUG_BUS_SCH_HAND1; -typedef union DEBUG_BUS_SCH_HAND2 regDEBUG_BUS_SCH_HAND2; -typedef union DEBUG_BUS_SCH_HAND3 regDEBUG_BUS_SCH_HAND3; -typedef union DEBUG_BUS_SCH_HAND4 regDEBUG_BUS_SCH_HAND4; -typedef union DEBUG_BUS_SCH_HAND5 regDEBUG_BUS_SCH_HAND5; -typedef union DEBUG_BUS_SCH_HAND6 regDEBUG_BUS_SCH_HAND6; -typedef union DEBUG_BUS_SCH_HAND7 regDEBUG_BUS_SCH_HAND7; -typedef union DEBUG_BUS_SCH_HAND8 regDEBUG_BUS_SCH_HAND8; -typedef union DEBUG_BUS_SCH_HAND9 regDEBUG_BUS_SCH_HAND9; -typedef union DEBUG_BUS_SCH_HAND10 regDEBUG_BUS_SCH_HAND10; -typedef union DEBUG_BUS_SCH_HAND11 regDEBUG_BUS_SCH_HAND11; -typedef union DEBUG_BUS_SCH_HAND12 regDEBUG_BUS_SCH_HAND12; -typedef union DEBUG_BUS_REG0 regDEBUG_BUS_REG0; -typedef union DEBUG_BUS_REG1 regDEBUG_BUS_REG1; -typedef union DEBUG_BUS_REG2 regDEBUG_BUS_REG2; -typedef union wbuf_DEBUG_DATA regwbuf_DEBUG_DATA; -typedef union rbuf_DEBUG_DATA regrbuf_DEBUG_DATA; -typedef union oa_wc0_DEBUG_DATA regoa_wc0_DEBUG_DATA; -typedef union oa_wc1_DEBUG_DATA regoa_wc1_DEBUG_DATA; -typedef union gws_DEBUG_DATA reggws_DEBUG_DATA; -typedef union alloc_DEBUG_DATA regalloc_DEBUG_DATA; -typedef union ord_app_DEBUG_DATA regord_app_DEBUG_DATA; -typedef union GPM_CMN_debug_0_data regGPM_CMN_debug_0_data; -typedef union GPM_CMN_debug_1_data regGPM_CMN_debug_1_data; -typedef union GPM_CMN_debug_2_data regGPM_CMN_debug_2_data; -typedef union GPM_CMN_debug_3_data regGPM_CMN_debug_3_data; -typedef union GPM_CMN_debug_4_data regGPM_CMN_debug_4_data; -typedef union GPM_CMN_debug_5_data regGPM_CMN_debug_5_data; -typedef union GPM_CMN_debug_6_data regGPM_CMN_debug_6_data; -typedef union GPM_CMN_debug_7_data regGPM_CMN_debug_7_data; -typedef union GPM_CMN_debug_8_data regGPM_CMN_debug_8_data; -typedef union GPM_CMN_debug_9_data regGPM_CMN_debug_9_data; -typedef union GPM_CMN_debug_10_data regGPM_CMN_debug_10_data; -typedef union GPM_CMN_debug_11_data regGPM_CMN_debug_11_data; -typedef union GPM_CMN_debug_12_data regGPM_CMN_debug_12_data; -typedef union GPM_CMN_debug_13_data regGPM_CMN_debug_13_data; -typedef union GPM_CMN_debug_14_data regGPM_CMN_debug_14_data; -typedef union GPM_CMN_debug_15_data regGPM_CMN_debug_15_data; -typedef union GPM_CMN_debug_16_data regGPM_CMN_debug_16_data; -typedef union GPM_CMN_debug_17_data regGPM_CMN_debug_17_data; -typedef union GPM_CMN_debug_18_data regGPM_CMN_debug_18_data; -typedef union GPM_CMN_debug_19_data regGPM_CMN_debug_19_data; -typedef union GPM_CMN_debug_20_data regGPM_CMN_debug_20_data; -typedef union GPM_CMN_debug_21_data regGPM_CMN_debug_21_data; -typedef union GPM_CMN_debug_22_data regGPM_CMN_debug_22_data; -typedef union GPM_CMN_debug_23_data regGPM_CMN_debug_23_data; -typedef union GPM_CMN_debug_24_data regGPM_CMN_debug_24_data; -typedef union GPM_CMN_debug_25_data regGPM_CMN_debug_25_data; -typedef union SPM_CMN_debug_0_data regSPM_CMN_debug_0_data; -typedef union SPM_CMN_debug_1_data regSPM_CMN_debug_1_data; -typedef union SPM_CMN_debug_2_data regSPM_CMN_debug_2_data; -typedef union SPM_CMN_debug_3_data regSPM_CMN_debug_3_data; -typedef union SPM_CMN_debug_4_data regSPM_CMN_debug_4_data; -typedef union SPM_CMN_debug_5_data regSPM_CMN_debug_5_data; -typedef union SPM_CMN_debug_6_data regSPM_CMN_debug_6_data; -typedef union SPM_CMN_debug_7_data regSPM_CMN_debug_7_data; -typedef union SPM_CMN_debug_8_data regSPM_CMN_debug_8_data; -typedef union SPM_CMN_debug_9_data regSPM_CMN_debug_9_data; -typedef union SRM_CMN_debug_0_data regSRM_CMN_debug_0_data; -typedef union SRM_CMN_debug_1_data regSRM_CMN_debug_1_data; -typedef union SRM_CMN_debug_2_data regSRM_CMN_debug_2_data; -typedef union SRM_CMN_debug_3_data regSRM_CMN_debug_3_data; -typedef union SRM_CMN_debug_4_data regSRM_CMN_debug_4_data; -typedef union SRM_CMN_debug_5_data regSRM_CMN_debug_5_data; -typedef union SRM_CMN_debug_6_data regSRM_CMN_debug_6_data; -typedef union SRM_CMN_debug_7_data regSRM_CMN_debug_7_data; -typedef union SRM_CMN_debug_8_data regSRM_CMN_debug_8_data; -typedef union SRM_CMN_debug_9_data regSRM_CMN_debug_9_data; -typedef union SRM_CMN_debug_10_data regSRM_CMN_debug_10_data; -typedef union SRM_CMN_debug_11_data regSRM_CMN_debug_11_data; -typedef union SRM_CMN_debug_12_data regSRM_CMN_debug_12_data; -typedef union SRM_CMN_debug_13_data regSRM_CMN_debug_13_data; -typedef union SRM_CMN_debug_14_data regSRM_CMN_debug_14_data; -typedef union SRM_CMN_debug_15_data regSRM_CMN_debug_15_data; -typedef union CB_DEBUGBUS_1 regCB_DEBUGBUS_1; -typedef union CB_DEBUGBUS_2 regCB_DEBUGBUS_2; -typedef union CB_DEBUGBUS_3 regCB_DEBUGBUS_3; -typedef union CB_DEBUGBUS_4 regCB_DEBUGBUS_4; -typedef union CB_DEBUGBUS_5 regCB_DEBUGBUS_5; -typedef union CB_DEBUGBUS_6 regCB_DEBUGBUS_6; -typedef union CB_DEBUGBUS_7 regCB_DEBUGBUS_7; -typedef union CB_DEBUGBUS_8 regCB_DEBUGBUS_8; -typedef union CB_DEBUGBUS_9 regCB_DEBUGBUS_9; -typedef union CB_DEBUGBUS_10 regCB_DEBUGBUS_10; -typedef union CB_DEBUGBUS_11 regCB_DEBUGBUS_11; -typedef union CB_DEBUGBUS_12 regCB_DEBUGBUS_12; -typedef union CB_DEBUGBUS_13 regCB_DEBUGBUS_13; -typedef union CB_DEBUGBUS_14 regCB_DEBUGBUS_14; -typedef union CB_DEBUGBUS_15 regCB_DEBUGBUS_15; -typedef union CB_DEBUGBUS_16 regCB_DEBUGBUS_16; -typedef union CB_DEBUGBUS_17 regCB_DEBUGBUS_17; -typedef union CB_DEBUGBUS_18 regCB_DEBUGBUS_18; -typedef union CB_DEBUGBUS_19 regCB_DEBUGBUS_19; -typedef union CB_DEBUGBUS_20 regCB_DEBUGBUS_20; -typedef union CB_DEBUGBUS_21 regCB_DEBUGBUS_21; -typedef union CB_DEBUGBUS_22 regCB_DEBUGBUS_22; -typedef union PA_DEBUG00_0 regPA_DEBUG00_0; -typedef union PA_DEBUG00_1 regPA_DEBUG00_1; -typedef union PA_DEBUG01_0 regPA_DEBUG01_0; -typedef union PA_DEBUG01_1 regPA_DEBUG01_1; -typedef union PA_DEBUG02_0 regPA_DEBUG02_0; -typedef union PA_DEBUG02_1 regPA_DEBUG02_1; -typedef union PA_DEBUG03_0 regPA_DEBUG03_0; -typedef union PA_DEBUG03_1 regPA_DEBUG03_1; -typedef union PA_DEBUG04_0 regPA_DEBUG04_0; -typedef union PA_DEBUG04_1 regPA_DEBUG04_1; -typedef union PA_DEBUG05_0 regPA_DEBUG05_0; -typedef union PA_DEBUG05_1 regPA_DEBUG05_1; -typedef union PA_DEBUG06_0 regPA_DEBUG06_0; -typedef union PA_DEBUG06_1 regPA_DEBUG06_1; -typedef union PA_DEBUG07_0 regPA_DEBUG07_0; -typedef union PA_DEBUG07_1 regPA_DEBUG07_1; -typedef union PA_DEBUG08_0 regPA_DEBUG08_0; -typedef union PA_DEBUG08_1 regPA_DEBUG08_1; -typedef union PA_DEBUG09_0 regPA_DEBUG09_0; -typedef union PA_DEBUG09_1 regPA_DEBUG09_1; -typedef union PA_DEBUG10_0 regPA_DEBUG10_0; -typedef union PA_DEBUG10_1 regPA_DEBUG10_1; -typedef union PA_DEBUG11_0 regPA_DEBUG11_0; -typedef union PA_DEBUG11_1 regPA_DEBUG11_1; -typedef union PA_DEBUG12_0 regPA_DEBUG12_0; -typedef union PA_DEBUG12_1 regPA_DEBUG12_1; -typedef union PA_DEBUG13_0 regPA_DEBUG13_0; -typedef union PA_DEBUG13_1 regPA_DEBUG13_1; -typedef union PA_DEBUG14_0 regPA_DEBUG14_0; -typedef union PA_DEBUG14_1 regPA_DEBUG14_1; -typedef union PA_DEBUG15_0 regPA_DEBUG15_0; -typedef union PA_DEBUG15_1 regPA_DEBUG15_1; -typedef union PA_DEBUG16_0 regPA_DEBUG16_0; -typedef union PA_DEBUG16_1 regPA_DEBUG16_1; -typedef union PA_DEBUG17_0 regPA_DEBUG17_0; -typedef union PA_DEBUG17_1 regPA_DEBUG17_1; -typedef union PA_DEBUG18_0 regPA_DEBUG18_0; -typedef union PA_DEBUG18_1 regPA_DEBUG18_1; -typedef union PA_DEBUG19_0 regPA_DEBUG19_0; -typedef union PA_DEBUG19_1 regPA_DEBUG19_1; -typedef union PA_DEBUG20_0 regPA_DEBUG20_0; -typedef union PA_DEBUG20_1 regPA_DEBUG20_1; -typedef union PA_DEBUG21_0 regPA_DEBUG21_0; -typedef union PA_DEBUG21_1 regPA_DEBUG21_1; -typedef union PA_DEBUG22_0 regPA_DEBUG22_0; -typedef union PA_DEBUG22_1 regPA_DEBUG22_1; -typedef union PA_DEBUG23_0 regPA_DEBUG23_0; -typedef union PA_DEBUG24_0 regPA_DEBUG24_0; -typedef union PA_DEBUG25_0 regPA_DEBUG25_0; -typedef union PA_DEBUG26_0 regPA_DEBUG26_0; -typedef union PA_DEBUG27_0 regPA_DEBUG27_0; -typedef union PA_DEBUG28_0 regPA_DEBUG28_0; -typedef union PA_DEBUG29_0 regPA_DEBUG29_0; -typedef union PA_DEBUG30_0 regPA_DEBUG30_0; -typedef union PA_DEBUG31_0 regPA_DEBUG31_0; -typedef union PA_DEBUG32_0 regPA_DEBUG32_0; -typedef union PA_DEBUG33_0 regPA_DEBUG33_0; -typedef union PA_DEBUG34_0 regPA_DEBUG34_0; -typedef union PA_DEBUG34_1 regPA_DEBUG34_1; -typedef union PA_DEBUG35_0 regPA_DEBUG35_0; -typedef union PA_DEBUG35_1 regPA_DEBUG35_1; -typedef union PA_DEBUG36_0 regPA_DEBUG36_0; -typedef union PA_DEBUG36_1 regPA_DEBUG36_1; -typedef union PA_DEBUG37_0 regPA_DEBUG37_0; -typedef union PA_DEBUG37_1 regPA_DEBUG37_1; -typedef union PA_DEBUG38_0 regPA_DEBUG38_0; -typedef union PA_DEBUG38_1 regPA_DEBUG38_1; -typedef union PA_DEBUG39_0 regPA_DEBUG39_0; -typedef union PA_DEBUG39_1 regPA_DEBUG39_1; -typedef union PA_DEBUG40_0 regPA_DEBUG40_0; -typedef union PA_DEBUG40_1 regPA_DEBUG40_1; -typedef union PA_DEBUG41_0 regPA_DEBUG41_0; -typedef union PA_DEBUG41_1 regPA_DEBUG41_1; -typedef union PA_DEBUG42_0 regPA_DEBUG42_0; -typedef union PA_DEBUG42_1 regPA_DEBUG42_1; -typedef union PA_DEBUG43_0 regPA_DEBUG43_0; -typedef union PA_DEBUG43_1 regPA_DEBUG43_1; -typedef union PA_DEBUG44_0 regPA_DEBUG44_0; -typedef union PA_DEBUG44_1 regPA_DEBUG44_1; -typedef union PA_DEBUG45_0 regPA_DEBUG45_0; -typedef union PA_DEBUG45_1 regPA_DEBUG45_1; -typedef union PA_DEBUG46_0 regPA_DEBUG46_0; -typedef union PA_DEBUG46_1 regPA_DEBUG46_1; -typedef union PA_DEBUG47_0 regPA_DEBUG47_0; -typedef union PA_DEBUG47_1 regPA_DEBUG47_1; -typedef union PA_DEBUG48_0 regPA_DEBUG48_0; -typedef union PA_DEBUG48_1 regPA_DEBUG48_1; -typedef union PA_DEBUG49_0 regPA_DEBUG49_0; -typedef union PA_DEBUG49_1 regPA_DEBUG49_1; -typedef union PA_DEBUG50_0 regPA_DEBUG50_0; -typedef union PA_DEBUG50_1 regPA_DEBUG50_1; -typedef union PA_DEBUG51_0 regPA_DEBUG51_0; -typedef union PA_DEBUG52_0 regPA_DEBUG52_0; -typedef union PA_DEBUG53_0 regPA_DEBUG53_0; -typedef union PA_DEBUG54_0 regPA_DEBUG54_0; -typedef union PA_DEBUG55_0 regPA_DEBUG55_0; -typedef union Idebug0 regIdebug0; -typedef union Idebug1 regIdebug1; -typedef union Idebug2 regIdebug2; -typedef union Idebug3 regIdebug3; -typedef union Idebug4 regIdebug4; -typedef union Idebug5 regIdebug5; -typedef union Idebug6 regIdebug6; -typedef union Idebug7 regIdebug7; -typedef union Idebug8 regIdebug8; -typedef union Idebug9 regIdebug9; -typedef union Idebug11 regIdebug11; -typedef union Idebug12 regIdebug12; -typedef union signal_debug_00 regsignal_debug_00; -typedef union signal_debug_01 regsignal_debug_01; -typedef union signal_debug_02 regsignal_debug_02; -typedef union signal_debug_03 regsignal_debug_03; -typedef union signal_debug_04 regsignal_debug_04; -typedef union signal_debug_05 regsignal_debug_05; -typedef union signal_debug_06 regsignal_debug_06; -typedef union signal_debug_07 regsignal_debug_07; -typedef union signal_debug_08 regsignal_debug_08; -typedef union signal_debug_09 regsignal_debug_09; -typedef union signal_debug_10 regsignal_debug_10; -typedef union signal_debug_11 regsignal_debug_11; -typedef union signal_debug_12 regsignal_debug_12; -typedef union signal_debug_13 regsignal_debug_13; -typedef union signal_debug_14 regsignal_debug_14; -typedef union signal_debug_15 regsignal_debug_15; -typedef union signal_debug_16 regsignal_debug_16; -typedef union signal_debug_17 regsignal_debug_17; -typedef union signal_debug_18 regsignal_debug_18; -typedef union signal_debug_19 regsignal_debug_19; -typedef union signal_debug_20 regsignal_debug_20; -typedef union signal_debug_21 regsignal_debug_21; -typedef union signal_debug_22 regsignal_debug_22; -typedef union signal_debug_23 regsignal_debug_23; -typedef union signal_debug_24 regsignal_debug_24; -typedef union signal_debug_25 regsignal_debug_25; -typedef union SC_DBG_REG_0 regSC_DBG_REG_0; -typedef union SC_DBG_REG_1 regSC_DBG_REG_1; -typedef union SC_DBG_REG_2 regSC_DBG_REG_2; -typedef union SC_DBG_REG_3 regSC_DBG_REG_3; -typedef union SC_DBG_REG_4 regSC_DBG_REG_4; -typedef union SC_DBG_REG_5 regSC_DBG_REG_5; -typedef union SC_DBG_REG_6 regSC_DBG_REG_6; -typedef union SC_DBG_REG_7 regSC_DBG_REG_7; -typedef union SC_DBG_REG_8 regSC_DBG_REG_8; -typedef union SC_DBG_REG_9 regSC_DBG_REG_9; -typedef union SC_DBG_REG_10 regSC_DBG_REG_10; -typedef union SC_DBG_REG_11 regSC_DBG_REG_11; -typedef union SC_DBG_REG_12 regSC_DBG_REG_12; -typedef union SC_DBG_REG_13 regSC_DBG_REG_13; -typedef union SC_DBG_REG_14 regSC_DBG_REG_14; -typedef union SC_DBG_REG_15 regSC_DBG_REG_15; -typedef union SC_DBG_REG_16 regSC_DBG_REG_16; -typedef union SC_DBG_REG_17 regSC_DBG_REG_17; -typedef union SC_DBG_REG_18 regSC_DBG_REG_18; -typedef union SC_DBG_REG_19 regSC_DBG_REG_19; -typedef union SC_DBG_REG_20 regSC_DBG_REG_20; -typedef union SC_DBG_REG_21 regSC_DBG_REG_21; -typedef union SC_DBG_REG_22 regSC_DBG_REG_22; -typedef union SC_DBG_REG_23 regSC_DBG_REG_23; -typedef union SC_DBG_REG_24 regSC_DBG_REG_24; -typedef union SC_DBG_REG_25 regSC_DBG_REG_25; -typedef union SC_DBG_REG_26 regSC_DBG_REG_26; -typedef union SC_DBG_REG_27 regSC_DBG_REG_27; -typedef union SC_DBG_REG_28 regSC_DBG_REG_28; -typedef union SC_DBG_REG_29 regSC_DBG_REG_29; -typedef union SC_DBG_REG_30 regSC_DBG_REG_30; -typedef union SC_DBG_REG_31 regSC_DBG_REG_31; -typedef union SC_DBG_REG_32 regSC_DBG_REG_32; -typedef union SC_DBG_REG_33 regSC_DBG_REG_33; -typedef union SC_DBG_REG_34 regSC_DBG_REG_34; -typedef union SC_DBG_REG_35 regSC_DBG_REG_35; -typedef union SC_DBG_REG_36 regSC_DBG_REG_36; -typedef union SC_DBG_REG_37 regSC_DBG_REG_37; -typedef union SC_DBG_REG_38 regSC_DBG_REG_38; -typedef union SC_DBG_REG_39 regSC_DBG_REG_39; -typedef union SC_DBG_REG_40 regSC_DBG_REG_40; -typedef union SC_DBG_REG_41 regSC_DBG_REG_41; -typedef union SC_DBG_REG_42 regSC_DBG_REG_42; -typedef union SC_DBG_REG_43 regSC_DBG_REG_43; -typedef union SC_DBG_REG_44 regSC_DBG_REG_44; -typedef union SC_DBG_REG_45 regSC_DBG_REG_45; -typedef union SC_DBG_REG_46 regSC_DBG_REG_46; -typedef union SC_DBG_REG_47 regSC_DBG_REG_47; -typedef union SC_DBG_REG_48 regSC_DBG_REG_48; -typedef union SC_DBG_REG_49 regSC_DBG_REG_49; -typedef union SC_DBG_REG_50 regSC_DBG_REG_50; -typedef union SC_DBG_REG_51 regSC_DBG_REG_51; -typedef union SC_DBG_REG_52 regSC_DBG_REG_52; -typedef union SC_DBG_REG_53 regSC_DBG_REG_53; -typedef union SC_DBG_REG_54 regSC_DBG_REG_54; -typedef union SC_DBG_REG_55 regSC_DBG_REG_55; -typedef union SC_DBG_REG_56 regSC_DBG_REG_56; -typedef union SC_DBG_REG_57 regSC_DBG_REG_57; -typedef union SC_DBG_REG_58 regSC_DBG_REG_58; -typedef union SC_DBG_REG_59 regSC_DBG_REG_59; -typedef union SC_DBG_REG_60 regSC_DBG_REG_60; -typedef union SC_DBG_REG_61 regSC_DBG_REG_61; -typedef union SC_DBG_REG_62 regSC_DBG_REG_62; -typedef union SC_DBG_REG_63 regSC_DBG_REG_63; -typedef union WD_DBG_REG_0 regWD_DBG_REG_0; -typedef union WD_DBG_REG_1 regWD_DBG_REG_1; -typedef union WD_DBG_REG_2 regWD_DBG_REG_2; -typedef union WD_DBG_REG_3 regWD_DBG_REG_3; -typedef union WD_DBG_REG_4 regWD_DBG_REG_4; -typedef union WD_DBG_REG_5 regWD_DBG_REG_5; -typedef union WD_DBG_REG_6 regWD_DBG_REG_6; -typedef union WD_DBG_REG_7 regWD_DBG_REG_7; -typedef union WD_DBG_REG_8 regWD_DBG_REG_8; -typedef union WD_DBG_REG_9 regWD_DBG_REG_9; -typedef union WD_DBG_REG_10 regWD_DBG_REG_10; -typedef union WD_DBG_REG_11 regWD_DBG_REG_11; -typedef union WD_DBG_REG_12 regWD_DBG_REG_12; -typedef union WD_DBG_REG_13 regWD_DBG_REG_13; -typedef union WD_DBG_REG_14 regWD_DBG_REG_14; -typedef union WD_DBG_REG_15 regWD_DBG_REG_15; -typedef union IA_DBG_REG_0 regIA_DBG_REG_0; -typedef union IA_DBG_REG_1 regIA_DBG_REG_1; -typedef union IA_DBG_REG_2 regIA_DBG_REG_2; -typedef union IA_DBG_REG_3 regIA_DBG_REG_3; -typedef union IA_DBG_REG_4 regIA_DBG_REG_4; -typedef union IA_DBG_REG_5 regIA_DBG_REG_5; -typedef union IA_DBG_REG_6 regIA_DBG_REG_6; -typedef union IA_DBG_REG_7 regIA_DBG_REG_7; -typedef union IA_DBG_REG_8 regIA_DBG_REG_8; -typedef union IA_DBG_REG_9 regIA_DBG_REG_9; -typedef union IA_DBG_REG_10 regIA_DBG_REG_10; -typedef union IA_DBG_REG_11 regIA_DBG_REG_11; -typedef union IA_DBG_REG_12 regIA_DBG_REG_12; -typedef union IA_DBG_REG_13 regIA_DBG_REG_13; -typedef union IA_DBG_REG_14 regIA_DBG_REG_14; -typedef union IA_DBG_REG_15 regIA_DBG_REG_15; -typedef union VGT_DBG_REG_0 regVGT_DBG_REG_0; -typedef union VGT_DBG_REG_1 regVGT_DBG_REG_1; -typedef union VGT_DBG_REG_2 regVGT_DBG_REG_2; -typedef union VGT_DBG_REG_3 regVGT_DBG_REG_3; -typedef union VGT_DBG_REG_4 regVGT_DBG_REG_4; -typedef union VGT_DBG_REG_5 regVGT_DBG_REG_5; -typedef union VGT_DBG_REG_6 regVGT_DBG_REG_6; -typedef union VGT_DBG_REG_7 regVGT_DBG_REG_7; -typedef union VGT_DBG_REG_8 regVGT_DBG_REG_8; -typedef union VGT_DBG_REG_9 regVGT_DBG_REG_9; -typedef union VGT_DBG_REG_10 regVGT_DBG_REG_10; -typedef union VGT_DBG_REG_11 regVGT_DBG_REG_11; -typedef union VGT_DBG_REG_12 regVGT_DBG_REG_12; -typedef union VGT_DBG_REG_13 regVGT_DBG_REG_13; -typedef union VGT_DBG_REG_14 regVGT_DBG_REG_14; -typedef union VGT_DBG_REG_15 regVGT_DBG_REG_15; -typedef union VGT_DBG_REG_16 regVGT_DBG_REG_16; -typedef union VGT_DBG_REG_17 regVGT_DBG_REG_17; -typedef union VGT_DBG_REG_18 regVGT_DBG_REG_18; -typedef union VGT_DBG_REG_19 regVGT_DBG_REG_19; -typedef union VGT_DBG_REG_20 regVGT_DBG_REG_20; -typedef union VGT_DBG_REG_21 regVGT_DBG_REG_21; -typedef union VGT_DBG_REG_22 regVGT_DBG_REG_22; -typedef union VGT_DBG_REG_23 regVGT_DBG_REG_23; -typedef union VGT_DBG_REG_24 regVGT_DBG_REG_24; -typedef union VGT_DBG_REG_25 regVGT_DBG_REG_25; -typedef union VGT_DBG_REG_26 regVGT_DBG_REG_26; -typedef union VGT_DBG_REG_27 regVGT_DBG_REG_27; -typedef union VGT_DBG_REG_28 regVGT_DBG_REG_28; -typedef union VGT_DBG_REG_29 regVGT_DBG_REG_29; -typedef union VGT_DBG_REG_30 regVGT_DBG_REG_30; -typedef union VGT_DBG_REG_31 regVGT_DBG_REG_31; -typedef union VGT_DBG_REG_32 regVGT_DBG_REG_32; -typedef union VGT_DBG_REG_33 regVGT_DBG_REG_33; -typedef union VGT_DBG_REG_34 regVGT_DBG_REG_34; -typedef union VGT_DBG_REG_35 regVGT_DBG_REG_35; -typedef union VGT_DBG_REG_36 regVGT_DBG_REG_36; -typedef union VGT_DBG_REG_37 regVGT_DBG_REG_37; -typedef union VGT_DBG_REG_38 regVGT_DBG_REG_38; -typedef union VGT_DBG_REG_39 regVGT_DBG_REG_39; -typedef union VGT_DBG_REG_40 regVGT_DBG_REG_40; -typedef union VGT_DBG_REG_41 regVGT_DBG_REG_41; -typedef union VGT_DBG_REG_42 regVGT_DBG_REG_42; -typedef union VGT_DBG_REG_43 regVGT_DBG_REG_43; -typedef union VGT_DBG_REG_44 regVGT_DBG_REG_44; -typedef union VGT_DBG_REG_45 regVGT_DBG_REG_45; -typedef union VGT_DBG_REG_46 regVGT_DBG_REG_46; -typedef union VGT_DBG_REG_47 regVGT_DBG_REG_47; -typedef union VGT_DBG_REG_48 regVGT_DBG_REG_48; -typedef union VGT_DBG_REG_49 regVGT_DBG_REG_49; -typedef union VGT_DBG_REG_50 regVGT_DBG_REG_50; -typedef union VGT_DBG_REG_51 regVGT_DBG_REG_51; -typedef union VGT_DBG_REG_52 regVGT_DBG_REG_52; -typedef union VGT_DBG_REG_53 regVGT_DBG_REG_53; -typedef union VGT_DBG_REG_54 regVGT_DBG_REG_54; -typedef union VGT_DBG_REG_55 regVGT_DBG_REG_55; -typedef union VGT_DBG_REG_56 regVGT_DBG_REG_56; -typedef union VGT_DBG_REG_57 regVGT_DBG_REG_57; -typedef union VGT_DBG_REG_58 regVGT_DBG_REG_58; -typedef union VGT_DBG_REG_59 regVGT_DBG_REG_59; -typedef union VGT_DBG_REG_60 regVGT_DBG_REG_60; -typedef union VGT_DBG_REG_61 regVGT_DBG_REG_61; -typedef union VGT_DBG_REG_62 regVGT_DBG_REG_62; -typedef union VGT_DBG_REG_63 regVGT_DBG_REG_63; -typedef union spi_vs_wave_ctl0 regspi_vs_wave_ctl0; -typedef union spi_vs_wave_ctl1 regspi_vs_wave_ctl1; -typedef union spi_vs_wave_ctl2 regspi_vs_wave_ctl2; -typedef union spi_gs_wave_ctl0 regspi_gs_wave_ctl0; -typedef union spi_gs_wave_ctl1 regspi_gs_wave_ctl1; -typedef union spi_gs_wave_ctl2 regspi_gs_wave_ctl2; -typedef union spi_es_wave_ctl0 regspi_es_wave_ctl0; -typedef union spi_es_wave_ctl1 regspi_es_wave_ctl1; -typedef union spi_es_wave_ctl2 regspi_es_wave_ctl2; -typedef union spi_hs_wave_ctl0 regspi_hs_wave_ctl0; -typedef union spi_hs_wave_ctl1 regspi_hs_wave_ctl1; -typedef union spi_hs_wave_ctl2 regspi_hs_wave_ctl2; -typedef union spi_ls_wave_ctl0 regspi_ls_wave_ctl0; -typedef union spi_ls_wave_ctl1 regspi_ls_wave_ctl1; -typedef union spi_ls_wave_ctl2 regspi_ls_wave_ctl2; -typedef union spi_cs_ctl_gfx0 regspi_cs_ctl_gfx0; -typedef union spi_cs_ctl_gfx1 regspi_cs_ctl_gfx1; -typedef union spi_cs_ctl_gfx2 regspi_cs_ctl_gfx2; -typedef union spi_cs_ctl0 regspi_cs_ctl0; -typedef union spi_cs_ctl1 regspi_cs_ctl1; -typedef union spi_cs_ctl2 regspi_cs_ctl2; -typedef union spi_gfx_tmp_ring_mgr regspi_gfx_tmp_ring_mgr; -typedef union spi_cs_wave_gfx_ctl regspi_cs_wave_gfx_ctl; -typedef union spi_cs_wave_ctl regspi_cs_wave_ctl; -typedef union spi_ps_ctl0_0 regspi_ps_ctl0_0; -typedef union spi_ps_ctl0_1 regspi_ps_ctl0_1; -typedef union spi_ps_ctl0_2 regspi_ps_ctl0_2; -typedef union spi_ps_ctl0_3 regspi_ps_ctl0_3; -typedef union spi_ps_ctl0_4 regspi_ps_ctl0_4; -typedef union spi_ps_ctl1_0 regspi_ps_ctl1_0; -typedef union spi_ps_ctl1_1 regspi_ps_ctl1_1; -typedef union spi_ps_ctl1_2 regspi_ps_ctl1_2; -typedef union spi_ps_ctl1_3 regspi_ps_ctl1_3; -typedef union spi_ps_ctl1_4 regspi_ps_ctl1_4; -typedef union spi_pc_dealloc_ctl0 regspi_pc_dealloc_ctl0; -typedef union spi_pc_dealloc_ctl1 regspi_pc_dealloc_ctl1; -typedef union spi_pc_dealloc_ctl2 regspi_pc_dealloc_ctl2; -typedef union spi_pc_dealloc_ctl3 regspi_pc_dealloc_ctl3; -typedef union spi_pc_dealloc_ctl4 regspi_pc_dealloc_ctl4; -typedef union spi_pc_dealloc_ctl5 regspi_pc_dealloc_ctl5; -typedef union spi_offchip_lds_mgr0 regspi_offchip_lds_mgr0; -typedef union spi_offchip_lds_mgr1 regspi_offchip_lds_mgr1; -typedef union spi_lds_wr_ctl0 regspi_lds_wr_ctl0; -typedef union spi_lds_wr_ctl1 regspi_lds_wr_ctl1; -typedef union spi_resource_alloc0 regspi_resource_alloc0; -typedef union spi_resource_alloc1 regspi_resource_alloc1; -typedef union spi_resource_alloc2 regspi_resource_alloc2; -typedef union spi_resource_alloc3 regspi_resource_alloc3; -typedef union spi_resource_alloc4 regspi_resource_alloc4; -typedef union spi_resource_alloc5 regspi_resource_alloc5; -typedef union spi_resource_alloc6 regspi_resource_alloc6; -typedef union spi_resource_alloc7 regspi_resource_alloc7; -typedef union spi_resource_alloc8 regspi_resource_alloc8; -typedef union spi_resource_alloc9 regspi_resource_alloc9; -typedef union spi_resource_alloc10 regspi_resource_alloc10; -typedef union spi_clk_gate0 regspi_clk_gate0; -typedef union spi_clk_gate1 regspi_clk_gate1; -typedef union spi_clk_gate2 regspi_clk_gate2; -typedef union spi_clk_gate3 regspi_clk_gate3; -typedef union CPC_debug_bus0_p0 regCPC_debug_bus0_p0; -typedef union CPC_debug_bus1_p0 regCPC_debug_bus1_p0; -typedef union CPC_debug_bus2_p0 regCPC_debug_bus2_p0; -typedef union CPC_debug_bus3_p0 regCPC_debug_bus3_p0; -typedef union CPC_debug_bus4_p0 regCPC_debug_bus4_p0; -typedef union CPC_debug_bus0_p1 regCPC_debug_bus0_p1; -typedef union CPC_debug_bus1_p1 regCPC_debug_bus1_p1; -typedef union CPC_debug_bus2_p1 regCPC_debug_bus2_p1; -typedef union CPC_debug_bus3_p1 regCPC_debug_bus3_p1; -typedef union CPC_debug_bus4_p1 regCPC_debug_bus4_p1; -typedef union CPC_debug_bus0_p2 regCPC_debug_bus0_p2; -typedef union CPC_debug_bus1_p2 regCPC_debug_bus1_p2; -typedef union CPC_debug_bus2_p2 regCPC_debug_bus2_p2; -typedef union CPC_debug_bus3_p2 regCPC_debug_bus3_p2; -typedef union CPC_debug_bus4_p2 regCPC_debug_bus4_p2; -typedef union CPC_debug_bus0_p3 regCPC_debug_bus0_p3; -typedef union CPC_debug_bus1_p3 regCPC_debug_bus1_p3; -typedef union CPC_debug_bus2_p3 regCPC_debug_bus2_p3; -typedef union CPC_debug_bus3_p3 regCPC_debug_bus3_p3; -typedef union CPC_debug_bus4_p3 regCPC_debug_bus4_p3; -typedef union CPC_debug_bus0_p4 regCPC_debug_bus0_p4; -typedef union CPC_debug_bus1_p4 regCPC_debug_bus1_p4; -typedef union CPC_debug_bus2_p4 regCPC_debug_bus2_p4; -typedef union CPC_debug_bus3_p4 regCPC_debug_bus3_p4; -typedef union CPC_debug_bus4_p4 regCPC_debug_bus4_p4; -typedef union CPC_debug_bus0_p5 regCPC_debug_bus0_p5; -typedef union CPC_debug_bus1_p5 regCPC_debug_bus1_p5; -typedef union CPC_debug_bus2_p5 regCPC_debug_bus2_p5; -typedef union CPC_debug_bus3_p5 regCPC_debug_bus3_p5; -typedef union CPC_debug_bus4_p5 regCPC_debug_bus4_p5; -typedef union CPC_debug_bus0_p6 regCPC_debug_bus0_p6; -typedef union CPC_debug_bus1_p6 regCPC_debug_bus1_p6; -typedef union CPC_debug_bus2_p6 regCPC_debug_bus2_p6; -typedef union CPC_debug_bus3_p6 regCPC_debug_bus3_p6; -typedef union CPC_debug_bus4_p6 regCPC_debug_bus4_p6; -typedef union CPC_debug_bus0_p7 regCPC_debug_bus0_p7; -typedef union CPC_debug_bus1_p7 regCPC_debug_bus1_p7; -typedef union CPC_debug_bus2_p7 regCPC_debug_bus2_p7; -typedef union CPC_debug_bus3_p7 regCPC_debug_bus3_p7; -typedef union CPC_debug_bus4_p7 regCPC_debug_bus4_p7; -typedef union CPC_SRDebugBus_23_0 regCPC_SRDebugBus_23_0; -typedef union CPC_SRDebugBus_47_24 regCPC_SRDebugBus_47_24; -typedef union CPC_SRDebugBus_71_48 regCPC_SRDebugBus_71_48; -typedef union CPC_SRDebugBus_95_72 regCPC_SRDebugBus_95_72; -typedef union CPC_SRDebugBus_119_96 regCPC_SRDebugBus_119_96; -typedef union CPC_QueryUnitDebugBus_23_0 regCPC_QueryUnitDebugBus_23_0; -typedef union CPC_QueryUnitDebugBus_47_24 regCPC_QueryUnitDebugBus_47_24; -typedef union CPC_QueryUnitDebugBus_71_48 regCPC_QueryUnitDebugBus_71_48; -typedef union CPC_QueryUnitDebugBus_95_72 regCPC_QueryUnitDebugBus_95_72; -typedef union CPC_QueryUnitDebugBus_119_96 regCPC_QueryUnitDebugBus_119_96; -typedef union CPC_QueryUnitDebugBus_127_120 regCPC_QueryUnitDebugBus_127_120; -typedef union CPC_MecScratchDebugBus_7_0 regCPC_MecScratchDebugBus_7_0; -typedef union CPC_RbiuDebugBus_11_0 regCPC_RbiuDebugBus_11_0; -typedef union CPC_RciuDebugBus_23_0 regCPC_RciuDebugBus_23_0; -typedef union CPC_RciuDebugBus_47_24 regCPC_RciuDebugBus_47_24; -typedef union CPC_RciuDebugBus_69_48 regCPC_RciuDebugBus_69_48; -typedef union CPC_CpcRoqDebugBus_23_0 regCPC_CpcRoqDebugBus_23_0; -typedef union CPC_CpcRoqDebugBus_47_24 regCPC_CpcRoqDebugBus_47_24; -typedef union CPC_CpcRoqDebugBus_71_48 regCPC_CpcRoqDebugBus_71_48; -typedef union CPC_CpcRoqDebugBus_95_72 regCPC_CpcRoqDebugBus_95_72; -typedef union CPC_TciuDebugBus_12_0 regCPC_TciuDebugBus_12_0; -typedef union CPC_Dynamic_and_Register_Clk_Valid regCPC_Dynamic_and_Register_Clk_Valid; -typedef union CPC_MecParserDebugBus_23_0 regCPC_MecParserDebugBus_23_0; -typedef union CPC_MecParserDebugBus_47_24 regCPC_MecParserDebugBus_47_24; -typedef union CPC_MecParserDebugBus_71_48 regCPC_MecParserDebugBus_71_48; -typedef union CPC_MecParserDebugBus_95_72 regCPC_MecParserDebugBus_95_72; -typedef union CPC_MecParserDebugBus_119_96 regCPC_MecParserDebugBus_119_96; -typedef union CPC_F32MecDebugBus_23_0 regCPC_F32MecDebugBus_23_0; -typedef union CPC_F32MecDebugBus_47_24 regCPC_F32MecDebugBus_47_24; -typedef union CPC_F32MecDebugBus_71_48 regCPC_F32MecDebugBus_71_48; -typedef union CPC_F32MecDebugBus_95_72 regCPC_F32MecDebugBus_95_72; -typedef union CPC_F32MecDebugBus_119_96 regCPC_F32MecDebugBus_119_96; -typedef union CPC_F32MecDebugBus_143_120 regCPC_F32MecDebugBus_143_120; -typedef union CPC_F32MecDebugBus_167_144 regCPC_F32MecDebugBus_167_144; -typedef union CPC_F32MecDebugBus_191_168 regCPC_F32MecDebugBus_191_168; -typedef union CPC_F32MecDebugBus_215_192 regCPC_F32MecDebugBus_215_192; -typedef union CPC_F32MecDebugBus_239_216 regCPC_F32MecDebugBus_239_216; -typedef union CPC_F32MecDebugBus_263_240 regCPC_F32MecDebugBus_263_240; -typedef union CPC_F32MecDebugBus_287_264 regCPC_F32MecDebugBus_287_264; -typedef union CPC_F32MecDebugBus_311_288 regCPC_F32MecDebugBus_311_288; -typedef union CPC_F32MecDebugBus_335_312 regCPC_F32MecDebugBus_335_312; -typedef union CPC_F32MecDebugBus_359_336 regCPC_F32MecDebugBus_359_336; -typedef union CPC_F32MecDebugBus_383_360 regCPC_F32MecDebugBus_383_360; -typedef union CPC_F32MecDebugBus_407_384 regCPC_F32MecDebugBus_407_384; -typedef union CPC_F32MecDebugBus_431_408 regCPC_F32MecDebugBus_431_408; -typedef union CPC_F32MecDebugBus_447_432 regCPC_F32MecDebugBus_447_432; -typedef union CPC_UtcL2iuDebugIntf_23_0 regCPC_UtcL2iuDebugIntf_23_0; -typedef union CPC_UtcL2iuDebugIntf_47_24 regCPC_UtcL2iuDebugIntf_47_24; -typedef union CPC_UtcL2iuDebugIntf_71_48 regCPC_UtcL2iuDebugIntf_71_48; -typedef union CPC_UtcL2iuDebugIntf_95_72 regCPC_UtcL2iuDebugIntf_95_72; -typedef union CPG_RbiuDebugIntf_23_0 regCPG_RbiuDebugIntf_23_0; -typedef union CPG_RbiuDebugIntf_47_24 regCPG_RbiuDebugIntf_47_24; -typedef union CPG_RciuDebugIntf_23_0 regCPG_RciuDebugIntf_23_0; -typedef union CPG_RciuDebugIntf_47_24 regCPG_RciuDebugIntf_47_24; -typedef union CPG_SurfSyncDebugIntf regCPG_SurfSyncDebugIntf; -typedef union CPG_PfpParserDebugIntf_23_0 regCPG_PfpParserDebugIntf_23_0; -typedef union CPG_PfpParserDebugIntf_47_24 regCPG_PfpParserDebugIntf_47_24; -typedef union CPG_PfpParserDebugIntf_71_48 regCPG_PfpParserDebugIntf_71_48; -typedef union CPG_PfpParserDebugIntf_95_72 regCPG_PfpParserDebugIntf_95_72; -typedef union CPG_PfpParserDebugIntf_119_96 regCPG_PfpParserDebugIntf_119_96; -typedef union CPG_PfpParserDebugIntf_143_120 regCPG_PfpParserDebugIntf_143_120; -typedef union CPG_MeParserDebugIntf_23_0 regCPG_MeParserDebugIntf_23_0; -typedef union CPG_MeParserDebugIntf_47_24 regCPG_MeParserDebugIntf_47_24; -typedef union CPG_MeParserDebugIntf_71_48 regCPG_MeParserDebugIntf_71_48; -typedef union CPG_MeParserDebugIntf_95_72 regCPG_MeParserDebugIntf_95_72; -typedef union CPG_MeParserDebugIntf_119_96 regCPG_MeParserDebugIntf_119_96; -typedef union CPG_QueryUnitDebugIntf_23_0 regCPG_QueryUnitDebugIntf_23_0; -typedef union CPG_QueryUnitDebugIntf_47_24 regCPG_QueryUnitDebugIntf_47_24; -typedef union CPG_QueryUnitDebugIntf_71_48 regCPG_QueryUnitDebugIntf_71_48; -typedef union CPG_Clk_Valid regCPG_Clk_Valid; -typedef union CPG_DcDebugIntf0 regCPG_DcDebugIntf0; -typedef union CPG_DcDebugIntf1 regCPG_DcDebugIntf1; -typedef union CPG_DcDebugIntf2 regCPG_DcDebugIntf2; -typedef union CPG_DcDebugIntf3 regCPG_DcDebugIntf3; -typedef union CPG_DcDebugIntf4 regCPG_DcDebugIntf4; -typedef union CPG_F32CeDebugBus_23_0 regCPG_F32CeDebugBus_23_0; -typedef union CPG_F32CeDebugBus_47_24 regCPG_F32CeDebugBus_47_24; -typedef union CPG_F32CeDebugBus_71_48 regCPG_F32CeDebugBus_71_48; -typedef union CPG_F32CeDebugBus_95_72 regCPG_F32CeDebugBus_95_72; -typedef union CPG_F32CeDebugBus_119_96 regCPG_F32CeDebugBus_119_96; -typedef union CPG_F32CeDebugBus_143_120 regCPG_F32CeDebugBus_143_120; -typedef union CPG_F32CeDebugBus_167_144 regCPG_F32CeDebugBus_167_144; -typedef union CPG_F32CeDebugBus_191_168 regCPG_F32CeDebugBus_191_168; -typedef union CPG_F32CeDebugBus_215_192 regCPG_F32CeDebugBus_215_192; -typedef union CPG_F32CeDebugBus_239_216 regCPG_F32CeDebugBus_239_216; -typedef union CPG_F32CeDebugBus_263_240 regCPG_F32CeDebugBus_263_240; -typedef union CPG_F32CeDebugBus_287_264 regCPG_F32CeDebugBus_287_264; -typedef union CPG_F32CeDebugBus_311_288 regCPG_F32CeDebugBus_311_288; -typedef union CPG_F32CeDebugBus_335_312 regCPG_F32CeDebugBus_335_312; -typedef union CPG_F32CeDebugBus_359_336 regCPG_F32CeDebugBus_359_336; -typedef union CPG_F32CeDebugBus_383_360 regCPG_F32CeDebugBus_383_360; -typedef union CPG_F32CeDebugBus_407_384 regCPG_F32CeDebugBus_407_384; -typedef union CPG_F32CeDebugBus_431_408 regCPG_F32CeDebugBus_431_408; -typedef union CPG_F32CeDebugBus_447_432 regCPG_F32CeDebugBus_447_432; -typedef union CPG_AtcL2iuDebugIntf_23_0 regCPG_AtcL2iuDebugIntf_23_0; -typedef union CPG_AtcL2iuDebugIntf_47_24 regCPG_AtcL2iuDebugIntf_47_24; -typedef union CPG_AtcL2iuDebugIntf_71_48 regCPG_AtcL2iuDebugIntf_71_48; -typedef union CPG_CeParserDebugIntf_23_0 regCPG_CeParserDebugIntf_23_0; -typedef union CPG_CeParserDebugIntf_47_24 regCPG_CeParserDebugIntf_47_24; -typedef union CPG_CeParserDebugIntf_71_48 regCPG_CeParserDebugIntf_71_48; -typedef union CPG_CeParserDebugIntf_95_72 regCPG_CeParserDebugIntf_95_72; -typedef union CPG_CeParserDebugIntf_119_96 regCPG_CeParserDebugIntf_119_96; -typedef union CPG_TciuDebugIntf_23_0 regCPG_TciuDebugIntf_23_0; -typedef union CPG_TciuDebugIntf_47_24 regCPG_TciuDebugIntf_47_24; -typedef union CPG_TciuDebugIntf_71_48 regCPG_TciuDebugIntf_71_48; -typedef union CPG_TciuDebugIntf_95_72 regCPG_TciuDebugIntf_95_72; -typedef union CPG_TciuDebugIntf_119_96 regCPG_TciuDebugIntf_119_96; -typedef union CPG_TciuDebugIntf_143_120 regCPG_TciuDebugIntf_143_120; -typedef union CPG_TciuDebugIntf_167_144 regCPG_TciuDebugIntf_167_144; -typedef union CPG_SemaphoreDebugIntf regCPG_SemaphoreDebugIntf; -typedef union CPG_F32PfpDebugBus_23_0 regCPG_F32PfpDebugBus_23_0; -typedef union CPG_F32PfpDebugBus_47_24 regCPG_F32PfpDebugBus_47_24; -typedef union CPG_F32PfpDebugBus_71_48 regCPG_F32PfpDebugBus_71_48; -typedef union CPG_F32PfpDebugBus_95_72 regCPG_F32PfpDebugBus_95_72; -typedef union CPG_F32PfpDebugBus_119_96 regCPG_F32PfpDebugBus_119_96; -typedef union CPG_F32PfpDebugBus_143_120 regCPG_F32PfpDebugBus_143_120; -typedef union CPG_F32PfpDebugBus_167_144 regCPG_F32PfpDebugBus_167_144; -typedef union CPG_F32PfpDebugBus_191_168 regCPG_F32PfpDebugBus_191_168; -typedef union CPG_F32PfpDebugBus_215_192 regCPG_F32PfpDebugBus_215_192; -typedef union CPG_F32PfpDebugBus_239_216 regCPG_F32PfpDebugBus_239_216; -typedef union CPG_F32PfpDebugBus_263_240 regCPG_F32PfpDebugBus_263_240; -typedef union CPG_F32PfpDebugBus_287_264 regCPG_F32PfpDebugBus_287_264; -typedef union CPG_F32PfpDebugBus_311_288 regCPG_F32PfpDebugBus_311_288; -typedef union CPG_F32PfpDebugBus_335_312 regCPG_F32PfpDebugBus_335_312; -typedef union CPG_F32PfpDebugBus_359_336 regCPG_F32PfpDebugBus_359_336; -typedef union CPG_F32PfpDebugBus_383_360 regCPG_F32PfpDebugBus_383_360; -typedef union CPG_F32PfpDebugBus_407_384 regCPG_F32PfpDebugBus_407_384; -typedef union CPG_F32PfpDebugBus_431_408 regCPG_F32PfpDebugBus_431_408; -typedef union CPG_F32PfpDebugBus_447_432 regCPG_F32PfpDebugBus_447_432; -typedef union CPG_F32MeDebugBus_23_0 regCPG_F32MeDebugBus_23_0; -typedef union CPG_F32MeDebugBus_47_24 regCPG_F32MeDebugBus_47_24; -typedef union CPG_F32MeDebugBus_71_48 regCPG_F32MeDebugBus_71_48; -typedef union CPG_F32MeDebugBus_95_72 regCPG_F32MeDebugBus_95_72; -typedef union CPG_F32MeDebugBus_119_96 regCPG_F32MeDebugBus_119_96; -typedef union CPG_F32MeDebugBus_143_120 regCPG_F32MeDebugBus_143_120; -typedef union CPG_F32MeDebugBus_167_144 regCPG_F32MeDebugBus_167_144; -typedef union CPG_F32MeDebugBus_191_168 regCPG_F32MeDebugBus_191_168; -typedef union CPG_F32MeDebugBus_215_192 regCPG_F32MeDebugBus_215_192; -typedef union CPG_F32MeDebugBus_239_216 regCPG_F32MeDebugBus_239_216; -typedef union CPG_F32MeDebugBus_263_240 regCPG_F32MeDebugBus_263_240; -typedef union CPG_F32MeDebugBus_287_264 regCPG_F32MeDebugBus_287_264; -typedef union CPG_F32MeDebugBus_311_288 regCPG_F32MeDebugBus_311_288; -typedef union CPG_F32MeDebugBus_335_312 regCPG_F32MeDebugBus_335_312; -typedef union CPG_F32MeDebugBus_359_336 regCPG_F32MeDebugBus_359_336; -typedef union CPG_F32MeDebugBus_383_360 regCPG_F32MeDebugBus_383_360; -typedef union CPG_F32MeDebugBus_407_384 regCPG_F32MeDebugBus_407_384; -typedef union CPG_F32MeDebugBus_431_408 regCPG_F32MeDebugBus_431_408; -typedef union CPG_F32MeDebugBus_447_432 regCPG_F32MeDebugBus_447_432; -typedef union CPF_RbiuDebugIntf_23_0 regCPF_RbiuDebugIntf_23_0; -typedef union CPF_RbiuDebugIntf_47_24 regCPF_RbiuDebugIntf_47_24; -typedef union CPF_SemaphoreDebugIntf regCPF_SemaphoreDebugIntf; -typedef union CPF_Rbiu_Semaphore_DebugBus regCPF_Rbiu_Semaphore_DebugBus; -typedef union CPF_TciuDebugBus_47_24 regCPF_TciuDebugBus_47_24; -typedef union CPF_TciuDebugBus_23_0 regCPF_TciuDebugBus_23_0; -typedef union CPF_TciuDebugIntf_23_0 regCPF_TciuDebugIntf_23_0; -typedef union CPF_TciuDebugIntf_47_24 regCPF_TciuDebugIntf_47_24; -typedef union CPF_TciuDebugIntf_71_48 regCPF_TciuDebugIntf_71_48; -typedef union CPF_TciuDebugIntf_95_72 regCPF_TciuDebugIntf_95_72; -typedef union CPF_TciuDebugIntf_119_96 regCPF_TciuDebugIntf_119_96; -typedef union CPF_UtcL2iuDebugIntf_23_0 regCPF_UtcL2iuDebugIntf_23_0; -typedef union CPF_UtcL2iuDebugIntf_47_24 regCPF_UtcL2iuDebugIntf_47_24; -typedef union CPF_UtcL2iuDebugIntf_71_48 regCPF_UtcL2iuDebugIntf_71_48; -typedef union CPF_UtcL2iuDebugIntf_95_72 regCPF_UtcL2iuDebugIntf_95_72; -typedef union CPF_HqdQueueDebugBus_23_0 regCPF_HqdQueueDebugBus_23_0; -typedef union CPF_HqdQueueDebugBus_47_24 regCPF_HqdQueueDebugBus_47_24; -typedef union CPF_HqdQueueDebugBus_71_48 regCPF_HqdQueueDebugBus_71_48; -typedef union CPF_HqdQueueDebugBus_95_72 regCPF_HqdQueueDebugBus_95_72; -typedef union CPF_HqdQueueDebugBus_119_96 regCPF_HqdQueueDebugBus_119_96; -typedef union CPF_HqdQueueDebugBus_143_120 regCPF_HqdQueueDebugBus_143_120; -typedef union CPF_HqdQueueDebugBus_167_144 regCPF_HqdQueueDebugBus_167_144; -typedef union CPF_HqdQueueDebugBus_191_168 regCPF_HqdQueueDebugBus_191_168; -typedef union CPF_QueueFetcherDebugBus_23_0 regCPF_QueueFetcherDebugBus_23_0; -typedef union CPF_QueueFetcherDebugBus_47_24 regCPF_QueueFetcherDebugBus_47_24; -typedef union CPF_QueueFetcherDebugBus_71_48 regCPF_QueueFetcherDebugBus_71_48; -typedef union CPF_QueueFetcherDebugBus_95_72 regCPF_QueueFetcherDebugBus_95_72; -typedef union CPF_QueueFetcherDebugBus_119_96 regCPF_QueueFetcherDebugBus_119_96; -typedef union CPF_QueueFetcherDebugBus_143_120 regCPF_QueueFetcherDebugBus_143_120; -typedef union CPF_QueueFetcherDebugBus_167_144 regCPF_QueueFetcherDebugBus_167_144; -typedef union CPF_QueueFetcherDebugBus_191_168 regCPF_QueueFetcherDebugBus_191_168; -typedef union CPF_HqdQueMngrDebugBus_23_0 regCPF_HqdQueMngrDebugBus_23_0; -typedef union CPF_HqdQueMngrDebugBus_47_24 regCPF_HqdQueMngrDebugBus_47_24; -typedef union CPF_HqdQueMngrDebugBus_71_48 regCPF_HqdQueMngrDebugBus_71_48; -typedef union CPF_HqdQueMngrDebugBus_95_72 regCPF_HqdQueMngrDebugBus_95_72; -typedef union CPF_HqdQueMngrDebugBus_119_96 regCPF_HqdQueMngrDebugBus_119_96; -typedef union CPF_HqdQueMngrDebugBus_127_120 regCPF_HqdQueMngrDebugBus_127_120; -typedef union CPF_HqdRoqCmdQueDebugBus_23_0 regCPF_HqdRoqCmdQueDebugBus_23_0; -typedef union CPF_HqdRoqCmdQueDebugBus_47_24 regCPF_HqdRoqCmdQueDebugBus_47_24; -typedef union CPF_HqdRoqCmdQueDebugBus_71_48 regCPF_HqdRoqCmdQueDebugBus_71_48; -typedef union CPF_HqdRoqCmdQueDebugBus_95_72 regCPF_HqdRoqCmdQueDebugBus_95_72; -typedef union CPF_HqdRoqCmdQueDebugBus_119_96 regCPF_HqdRoqCmdQueDebugBus_119_96; -typedef union CPF_HqdRoqCmdQueDebugBus_143_120 regCPF_HqdRoqCmdQueDebugBus_143_120; -typedef union CPF_HqdRoqCmdQueDebugBus_163_144 regCPF_HqdRoqCmdQueDebugBus_163_144; -typedef union CPF_HqdRoqAlignDebugBus regCPF_HqdRoqAlignDebugBus; -typedef union CPF_Roq_StQueue_Align_DebugBus regCPF_Roq_StQueue_Align_DebugBus; -typedef union CPF_RoqCmdQueueDebugBus_23_0 regCPF_RoqCmdQueueDebugBus_23_0; -typedef union CPF_RoqCmdQueueDebugBus_47_24 regCPF_RoqCmdQueueDebugBus_47_24; -typedef union CPF_RoqCnstQueueDebugBus_23_0 regCPF_RoqCnstQueueDebugBus_23_0; -typedef union CPF_RoqCnstQueueDebugBus_47_24 regCPF_RoqCnstQueueDebugBus_47_24; -typedef union CPF_WrPntrPollDebugBus_31_8 regCPF_WrPntrPollDebugBus_31_8; -typedef union CPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24 - regCPF_WrPntrPollDebugBus_7_0_InterruptDebugBus_31_24; -typedef union CPF_InterruptDebugBus_23_0 regCPF_InterruptDebugBus_23_0; -typedef union CPF_InterruptDebugIntf_23_0 regCPF_InterruptDebugIntf_23_0; -typedef union CPF_InterruptDebugIntf_47_24 regCPF_InterruptDebugIntf_47_24; -typedef union CPF_InterruptDebugIntf_58_48 regCPF_InterruptDebugIntf_58_48; -typedef union CPF_RciuDebugBus regCPF_RciuDebugBus; -typedef union bci_control0_dbg_bus regbci_control0_dbg_bus; -typedef union bci_control1_dbg_bus regbci_control1_dbg_bus; -typedef union bci_pipe0_dbg_bus regbci_pipe0_dbg_bus; -typedef union bci_pipe1_dbg_bus regbci_pipe1_dbg_bus; -typedef union RMI_DEBUGBUS_0 regRMI_DEBUGBUS_0; -typedef union RMI_DEBUGBUS_1 regRMI_DEBUGBUS_1; -typedef union RMI_DEBUGBUS_2 regRMI_DEBUGBUS_2; -typedef union RMI_DEBUGBUS_3 regRMI_DEBUGBUS_3; -typedef union RMI_DEBUGBUS_4 regRMI_DEBUGBUS_4; -typedef union RMI_DEBUGBUS_5 regRMI_DEBUGBUS_5; -typedef union RMI_DEBUGBUS_6 regRMI_DEBUGBUS_6; -typedef union RMI_DEBUGBUS_7 regRMI_DEBUGBUS_7; -typedef union RMI_DEBUGBUS_8 regRMI_DEBUGBUS_8; -typedef union RMI_DEBUGBUS_9 regRMI_DEBUGBUS_9; -typedef union RMI_DEBUGBUS_10 regRMI_DEBUGBUS_10; -typedef union RMI_DEBUGBUS_11 regRMI_DEBUGBUS_11; -typedef union RMI_DEBUGBUS_12 regRMI_DEBUGBUS_12; -typedef union RMI_DEBUGBUS_13 regRMI_DEBUGBUS_13; -typedef union RMI_DEBUGBUS_14 regRMI_DEBUGBUS_14; -typedef union RMI_DEBUGBUS_15 regRMI_DEBUGBUS_15; -typedef union RMI_DEBUGBUS_16 regRMI_DEBUGBUS_16; -typedef union RMI_DEBUGBUS_17 regRMI_DEBUGBUS_17; -typedef union RMI_DEBUGBUS_18 regRMI_DEBUGBUS_18; -typedef union RMI_DEBUGBUS_19 regRMI_DEBUGBUS_19; -typedef union RMI_DEBUGBUS_20 regRMI_DEBUGBUS_20; -typedef union RMI_DEBUGBUS_21 regRMI_DEBUGBUS_21; -typedef union RMI_DEBUGBUS_22 regRMI_DEBUGBUS_22; -typedef union RMI_DEBUGBUS_23 regRMI_DEBUGBUS_23; -typedef union RMI_DEBUGBUS_24 regRMI_DEBUGBUS_24; -typedef union RMI_DEBUGBUS_25 regRMI_DEBUGBUS_25; -typedef union RMI_DEBUGBUS_26 regRMI_DEBUGBUS_26; -typedef union RMI_DEBUGBUS_27 regRMI_DEBUGBUS_27; -typedef union RMI_DEBUGBUS_28 regRMI_DEBUGBUS_28; -typedef union RMI_DEBUGBUS_29 regRMI_DEBUGBUS_29; -typedef union RMI_DEBUGBUS_30 regRMI_DEBUGBUS_30; -typedef union RMI_DEBUGBUS_31 regRMI_DEBUGBUS_31; -typedef union RMI_DEBUGBUS_32 regRMI_DEBUGBUS_32; -typedef union DB_DEBUG_BUS_0 regDB_DEBUG_BUS_0; -typedef union DB_DEBUG_BUS_1 regDB_DEBUG_BUS_1; -typedef union DB_DEBUG_BUS_2 regDB_DEBUG_BUS_2; -typedef union DB_DEBUG_BUS_3 regDB_DEBUG_BUS_3; -typedef union DB_DEBUG_BUS_4 regDB_DEBUG_BUS_4; -typedef union DB_DEBUG_BUS_5 regDB_DEBUG_BUS_5; -typedef union DB_DEBUG_BUS_6 regDB_DEBUG_BUS_6; -typedef union DB_DEBUG_BUS_7 regDB_DEBUG_BUS_7; -typedef union DB_DEBUG_BUS_8 regDB_DEBUG_BUS_8; -typedef union DB_DEBUG_BUS_9 regDB_DEBUG_BUS_9; -typedef union DB_DEBUG_BUS_A regDB_DEBUG_BUS_A; -typedef union DB_DEBUG_BUS_B regDB_DEBUG_BUS_B; -typedef union DB_DEBUG_BUS_C regDB_DEBUG_BUS_C; -typedef union DB_DEBUG_BUS_D regDB_DEBUG_BUS_D; -typedef union DB_DEBUG_BUS_E regDB_DEBUG_BUS_E; -typedef union DB_DEBUG_BUS_F regDB_DEBUG_BUS_F; -typedef union ATC_L2_CNTL regATC_L2_CNTL; -typedef union ATC_L2_CNTL2 regATC_L2_CNTL2; -typedef union ATC_L2_DEBUG regATC_L2_DEBUG; -typedef union ATC_L2_DEBUG2 regATC_L2_DEBUG2; -typedef union ATC_L2_CACHE_DATA0 regATC_L2_CACHE_DATA0; -typedef union ATC_L2_CACHE_DATA1 regATC_L2_CACHE_DATA1; -typedef union ATC_L2_CACHE_DATA2 regATC_L2_CACHE_DATA2; -typedef union ATC_L2_CNTL3 regATC_L2_CNTL3; -typedef union ATC_L2_STATUS regATC_L2_STATUS; -typedef union ATC_L2_STATUS2 regATC_L2_STATUS2; -typedef union ATC_L2_MISC_CG regATC_L2_MISC_CG; -typedef union ATC_L2_MEM_POWER_LS regATC_L2_MEM_POWER_LS; -typedef union ATC_L2_CGTT_CLK_CTRL regATC_L2_CGTT_CLK_CTRL; -typedef union ATC_L2_PERFCOUNTER_LO regATC_L2_PERFCOUNTER_LO; -typedef union ATC_L2_PERFCOUNTER_HI regATC_L2_PERFCOUNTER_HI; -typedef union ATC_L2_PERFCOUNTER0_CFG regATC_L2_PERFCOUNTER0_CFG; -typedef union ATC_L2_PERFCOUNTER1_CFG regATC_L2_PERFCOUNTER1_CFG; -typedef union ATC_L2_PERFCOUNTER_RSLT_CNTL regATC_L2_PERFCOUNTER_RSLT_CNTL; -typedef union VM_L2_CNTL regVM_L2_CNTL; -typedef union VM_L2_CNTL2 regVM_L2_CNTL2; -typedef union VM_L2_CNTL3 regVM_L2_CNTL3; -typedef union VM_L2_STATUS regVM_L2_STATUS; -typedef union VM_DUMMY_PAGE_FAULT_CNTL regVM_DUMMY_PAGE_FAULT_CNTL; -typedef union VM_DUMMY_PAGE_FAULT_ADDR_LO32 regVM_DUMMY_PAGE_FAULT_ADDR_LO32; -typedef union VM_DUMMY_PAGE_FAULT_ADDR_HI32 regVM_DUMMY_PAGE_FAULT_ADDR_HI32; -typedef union VM_L2_PROTECTION_FAULT_CNTL regVM_L2_PROTECTION_FAULT_CNTL; -typedef union VM_L2_PROTECTION_FAULT_CNTL2 regVM_L2_PROTECTION_FAULT_CNTL2; -typedef union VM_L2_PROTECTION_FAULT_MM_CNTL3 regVM_L2_PROTECTION_FAULT_MM_CNTL3; -typedef union VM_L2_PROTECTION_FAULT_MM_CNTL4 regVM_L2_PROTECTION_FAULT_MM_CNTL4; -typedef union VM_L2_PROTECTION_FAULT_STATUS regVM_L2_PROTECTION_FAULT_STATUS; -typedef union VM_L2_PROTECTION_FAULT_ADDR_LO32 regVM_L2_PROTECTION_FAULT_ADDR_LO32; -typedef union VM_L2_PROTECTION_FAULT_ADDR_HI32 regVM_L2_PROTECTION_FAULT_ADDR_HI32; -typedef union VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; -typedef union VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; -typedef union VM_DEBUG regVM_DEBUG; -typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 - regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32; -typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 - regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32; -typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 - regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32; -typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 - regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32; -typedef union VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 - regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32; -typedef union VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 - regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32; -typedef union VM_L2_CNTL4 regVM_L2_CNTL4; -typedef union VM_L2_MM_GROUP_RT_CLASSES regVM_L2_MM_GROUP_RT_CLASSES; -typedef union VM_L2_BANK_SELECT_RESERVED_CID regVM_L2_BANK_SELECT_RESERVED_CID; -typedef union VM_L2_BANK_SELECT_RESERVED_CID2 regVM_L2_BANK_SELECT_RESERVED_CID2; -typedef union VM_L2_CACHE_PARITY_CNTL regVM_L2_CACHE_PARITY_CNTL; -typedef union VM_L2_IH_LOG_CNTL regVM_L2_IH_LOG_CNTL; -typedef union VM_L2_IH_LOG_BUSY regVM_L2_IH_LOG_BUSY; -typedef union VM_L2_CGTT_CLK_CTRL regVM_L2_CGTT_CLK_CTRL; -typedef union VML2_SEC_MASTER regVML2_SEC_MASTER; -typedef union VM_CONTEXT0_CNTL regVM_CONTEXT0_CNTL; -typedef union VM_CONTEXT1_CNTL regVM_CONTEXT1_CNTL; -typedef union VM_CONTEXT2_CNTL regVM_CONTEXT2_CNTL; -typedef union VM_CONTEXT3_CNTL regVM_CONTEXT3_CNTL; -typedef union VM_CONTEXT4_CNTL regVM_CONTEXT4_CNTL; -typedef union VM_CONTEXT5_CNTL regVM_CONTEXT5_CNTL; -typedef union VM_CONTEXT6_CNTL regVM_CONTEXT6_CNTL; -typedef union VM_CONTEXT7_CNTL regVM_CONTEXT7_CNTL; -typedef union VM_CONTEXT8_CNTL regVM_CONTEXT8_CNTL; -typedef union VM_CONTEXT9_CNTL regVM_CONTEXT9_CNTL; -typedef union VM_CONTEXT10_CNTL regVM_CONTEXT10_CNTL; -typedef union VM_CONTEXT11_CNTL regVM_CONTEXT11_CNTL; -typedef union VM_CONTEXT12_CNTL regVM_CONTEXT12_CNTL; -typedef union VM_CONTEXT13_CNTL regVM_CONTEXT13_CNTL; -typedef union VM_CONTEXT14_CNTL regVM_CONTEXT14_CNTL; -typedef union VM_CONTEXT15_CNTL regVM_CONTEXT15_CNTL; -typedef union VM_CONTEXTS_DISABLE regVM_CONTEXTS_DISABLE; -typedef union VM_INVALIDATE_ENG0_SEM regVM_INVALIDATE_ENG0_SEM; -typedef union VM_INVALIDATE_ENG1_SEM regVM_INVALIDATE_ENG1_SEM; -typedef union VM_INVALIDATE_ENG2_SEM regVM_INVALIDATE_ENG2_SEM; -typedef union VM_INVALIDATE_ENG3_SEM regVM_INVALIDATE_ENG3_SEM; -typedef union VM_INVALIDATE_ENG4_SEM regVM_INVALIDATE_ENG4_SEM; -typedef union VM_INVALIDATE_ENG5_SEM regVM_INVALIDATE_ENG5_SEM; -typedef union VM_INVALIDATE_ENG6_SEM regVM_INVALIDATE_ENG6_SEM; -typedef union VM_INVALIDATE_ENG7_SEM regVM_INVALIDATE_ENG7_SEM; -typedef union VM_INVALIDATE_ENG8_SEM regVM_INVALIDATE_ENG8_SEM; -typedef union VM_INVALIDATE_ENG9_SEM regVM_INVALIDATE_ENG9_SEM; -typedef union VM_INVALIDATE_ENG10_SEM regVM_INVALIDATE_ENG10_SEM; -typedef union VM_INVALIDATE_ENG11_SEM regVM_INVALIDATE_ENG11_SEM; -typedef union VM_INVALIDATE_ENG12_SEM regVM_INVALIDATE_ENG12_SEM; -typedef union VM_INVALIDATE_ENG13_SEM regVM_INVALIDATE_ENG13_SEM; -typedef union VM_INVALIDATE_ENG14_SEM regVM_INVALIDATE_ENG14_SEM; -typedef union VM_INVALIDATE_ENG15_SEM regVM_INVALIDATE_ENG15_SEM; -typedef union VM_INVALIDATE_ENG16_SEM regVM_INVALIDATE_ENG16_SEM; -typedef union VM_INVALIDATE_ENG17_SEM regVM_INVALIDATE_ENG17_SEM; -typedef union VM_INVALIDATE_ENG0_REQ regVM_INVALIDATE_ENG0_REQ; -typedef union VM_INVALIDATE_ENG1_REQ regVM_INVALIDATE_ENG1_REQ; -typedef union VM_INVALIDATE_ENG2_REQ regVM_INVALIDATE_ENG2_REQ; -typedef union VM_INVALIDATE_ENG3_REQ regVM_INVALIDATE_ENG3_REQ; -typedef union VM_INVALIDATE_ENG4_REQ regVM_INVALIDATE_ENG4_REQ; -typedef union VM_INVALIDATE_ENG5_REQ regVM_INVALIDATE_ENG5_REQ; -typedef union VM_INVALIDATE_ENG6_REQ regVM_INVALIDATE_ENG6_REQ; -typedef union VM_INVALIDATE_ENG7_REQ regVM_INVALIDATE_ENG7_REQ; -typedef union VM_INVALIDATE_ENG8_REQ regVM_INVALIDATE_ENG8_REQ; -typedef union VM_INVALIDATE_ENG9_REQ regVM_INVALIDATE_ENG9_REQ; -typedef union VM_INVALIDATE_ENG10_REQ regVM_INVALIDATE_ENG10_REQ; -typedef union VM_INVALIDATE_ENG11_REQ regVM_INVALIDATE_ENG11_REQ; -typedef union VM_INVALIDATE_ENG12_REQ regVM_INVALIDATE_ENG12_REQ; -typedef union VM_INVALIDATE_ENG13_REQ regVM_INVALIDATE_ENG13_REQ; -typedef union VM_INVALIDATE_ENG14_REQ regVM_INVALIDATE_ENG14_REQ; -typedef union VM_INVALIDATE_ENG15_REQ regVM_INVALIDATE_ENG15_REQ; -typedef union VM_INVALIDATE_ENG16_REQ regVM_INVALIDATE_ENG16_REQ; -typedef union VM_INVALIDATE_ENG17_REQ regVM_INVALIDATE_ENG17_REQ; -typedef union VM_INVALIDATE_ENG0_ACK regVM_INVALIDATE_ENG0_ACK; -typedef union VM_INVALIDATE_ENG1_ACK regVM_INVALIDATE_ENG1_ACK; -typedef union VM_INVALIDATE_ENG2_ACK regVM_INVALIDATE_ENG2_ACK; -typedef union VM_INVALIDATE_ENG3_ACK regVM_INVALIDATE_ENG3_ACK; -typedef union VM_INVALIDATE_ENG4_ACK regVM_INVALIDATE_ENG4_ACK; -typedef union VM_INVALIDATE_ENG5_ACK regVM_INVALIDATE_ENG5_ACK; -typedef union VM_INVALIDATE_ENG6_ACK regVM_INVALIDATE_ENG6_ACK; -typedef union VM_INVALIDATE_ENG7_ACK regVM_INVALIDATE_ENG7_ACK; -typedef union VM_INVALIDATE_ENG8_ACK regVM_INVALIDATE_ENG8_ACK; -typedef union VM_INVALIDATE_ENG9_ACK regVM_INVALIDATE_ENG9_ACK; -typedef union VM_INVALIDATE_ENG10_ACK regVM_INVALIDATE_ENG10_ACK; -typedef union VM_INVALIDATE_ENG11_ACK regVM_INVALIDATE_ENG11_ACK; -typedef union VM_INVALIDATE_ENG12_ACK regVM_INVALIDATE_ENG12_ACK; -typedef union VM_INVALIDATE_ENG13_ACK regVM_INVALIDATE_ENG13_ACK; -typedef union VM_INVALIDATE_ENG14_ACK regVM_INVALIDATE_ENG14_ACK; -typedef union VM_INVALIDATE_ENG15_ACK regVM_INVALIDATE_ENG15_ACK; -typedef union VM_INVALIDATE_ENG16_ACK regVM_INVALIDATE_ENG16_ACK; -typedef union VM_INVALIDATE_ENG17_ACK regVM_INVALIDATE_ENG17_ACK; -typedef union VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32; -typedef union VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32; -typedef union VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32; -typedef union VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32; -typedef union VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32; -typedef union VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32; -typedef union VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32; -typedef union VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32; -typedef union VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32; -typedef union VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32; -typedef union MC_VM_L2_PERFCOUNTER0_CFG regMC_VM_L2_PERFCOUNTER0_CFG; -typedef union MC_VM_L2_PERFCOUNTER1_CFG regMC_VM_L2_PERFCOUNTER1_CFG; -typedef union MC_VM_L2_PERFCOUNTER2_CFG regMC_VM_L2_PERFCOUNTER2_CFG; -typedef union MC_VM_L2_PERFCOUNTER3_CFG regMC_VM_L2_PERFCOUNTER3_CFG; -typedef union MC_VM_L2_PERFCOUNTER4_CFG regMC_VM_L2_PERFCOUNTER4_CFG; -typedef union MC_VM_L2_PERFCOUNTER5_CFG regMC_VM_L2_PERFCOUNTER5_CFG; -typedef union MC_VM_L2_PERFCOUNTER6_CFG regMC_VM_L2_PERFCOUNTER6_CFG; -typedef union MC_VM_L2_PERFCOUNTER7_CFG regMC_VM_L2_PERFCOUNTER7_CFG; -typedef union MC_VM_L2_PERFCOUNTER_RSLT_CNTL regMC_VM_L2_PERFCOUNTER_RSLT_CNTL; -typedef union MC_VM_L2_PERFCOUNTER_LO regMC_VM_L2_PERFCOUNTER_LO; -typedef union MC_VM_L2_PERFCOUNTER_HI regMC_VM_L2_PERFCOUNTER_HI; -typedef union MC_VM_FB_SIZE_OFFSET_VF0 regMC_VM_FB_SIZE_OFFSET_VF0; -typedef union MC_VM_FB_SIZE_OFFSET_VF1 regMC_VM_FB_SIZE_OFFSET_VF1; -typedef union MC_VM_FB_SIZE_OFFSET_VF2 regMC_VM_FB_SIZE_OFFSET_VF2; -typedef union MC_VM_FB_SIZE_OFFSET_VF3 regMC_VM_FB_SIZE_OFFSET_VF3; -typedef union MC_VM_FB_SIZE_OFFSET_VF4 regMC_VM_FB_SIZE_OFFSET_VF4; -typedef union MC_VM_FB_SIZE_OFFSET_VF5 regMC_VM_FB_SIZE_OFFSET_VF5; -typedef union MC_VM_FB_SIZE_OFFSET_VF6 regMC_VM_FB_SIZE_OFFSET_VF6; -typedef union MC_VM_FB_SIZE_OFFSET_VF7 regMC_VM_FB_SIZE_OFFSET_VF7; -typedef union MC_VM_FB_SIZE_OFFSET_VF8 regMC_VM_FB_SIZE_OFFSET_VF8; -typedef union MC_VM_FB_SIZE_OFFSET_VF9 regMC_VM_FB_SIZE_OFFSET_VF9; -typedef union MC_VM_FB_SIZE_OFFSET_VF10 regMC_VM_FB_SIZE_OFFSET_VF10; -typedef union MC_VM_FB_SIZE_OFFSET_VF11 regMC_VM_FB_SIZE_OFFSET_VF11; -typedef union MC_VM_FB_SIZE_OFFSET_VF12 regMC_VM_FB_SIZE_OFFSET_VF12; -typedef union MC_VM_FB_SIZE_OFFSET_VF13 regMC_VM_FB_SIZE_OFFSET_VF13; -typedef union MC_VM_FB_SIZE_OFFSET_VF14 regMC_VM_FB_SIZE_OFFSET_VF14; -typedef union MC_VM_FB_SIZE_OFFSET_VF15 regMC_VM_FB_SIZE_OFFSET_VF15; -typedef union VM_IOMMU_MMIO_CNTRL_1 regVM_IOMMU_MMIO_CNTRL_1; -typedef union MC_VM_MARC_BASE_LO_0 regMC_VM_MARC_BASE_LO_0; -typedef union MC_VM_MARC_BASE_LO_1 regMC_VM_MARC_BASE_LO_1; -typedef union MC_VM_MARC_BASE_LO_2 regMC_VM_MARC_BASE_LO_2; -typedef union MC_VM_MARC_BASE_LO_3 regMC_VM_MARC_BASE_LO_3; -typedef union MC_VM_MARC_BASE_HI_0 regMC_VM_MARC_BASE_HI_0; -typedef union MC_VM_MARC_BASE_HI_1 regMC_VM_MARC_BASE_HI_1; -typedef union MC_VM_MARC_BASE_HI_2 regMC_VM_MARC_BASE_HI_2; -typedef union MC_VM_MARC_BASE_HI_3 regMC_VM_MARC_BASE_HI_3; -typedef union MC_VM_MARC_RELOC_LO_0 regMC_VM_MARC_RELOC_LO_0; -typedef union MC_VM_MARC_RELOC_LO_1 regMC_VM_MARC_RELOC_LO_1; -typedef union MC_VM_MARC_RELOC_LO_2 regMC_VM_MARC_RELOC_LO_2; -typedef union MC_VM_MARC_RELOC_LO_3 regMC_VM_MARC_RELOC_LO_3; -typedef union MC_VM_MARC_RELOC_HI_0 regMC_VM_MARC_RELOC_HI_0; -typedef union MC_VM_MARC_RELOC_HI_1 regMC_VM_MARC_RELOC_HI_1; -typedef union MC_VM_MARC_RELOC_HI_2 regMC_VM_MARC_RELOC_HI_2; -typedef union MC_VM_MARC_RELOC_HI_3 regMC_VM_MARC_RELOC_HI_3; -typedef union MC_VM_MARC_LEN_LO_0 regMC_VM_MARC_LEN_LO_0; -typedef union MC_VM_MARC_LEN_LO_1 regMC_VM_MARC_LEN_LO_1; -typedef union MC_VM_MARC_LEN_LO_2 regMC_VM_MARC_LEN_LO_2; -typedef union MC_VM_MARC_LEN_LO_3 regMC_VM_MARC_LEN_LO_3; -typedef union MC_VM_MARC_LEN_HI_0 regMC_VM_MARC_LEN_HI_0; -typedef union MC_VM_MARC_LEN_HI_1 regMC_VM_MARC_LEN_HI_1; -typedef union MC_VM_MARC_LEN_HI_2 regMC_VM_MARC_LEN_HI_2; -typedef union MC_VM_MARC_LEN_HI_3 regMC_VM_MARC_LEN_HI_3; -typedef union VM_IOMMU_CONTROL_REGISTER regVM_IOMMU_CONTROL_REGISTER; -typedef union VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER - regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER; -typedef union VM_PCIE_ATS_CNTL regVM_PCIE_ATS_CNTL; -typedef union VM_PCIE_ATS_CNTL_VF_0 regVM_PCIE_ATS_CNTL_VF_0; -typedef union VM_PCIE_ATS_CNTL_VF_1 regVM_PCIE_ATS_CNTL_VF_1; -typedef union VM_PCIE_ATS_CNTL_VF_2 regVM_PCIE_ATS_CNTL_VF_2; -typedef union VM_PCIE_ATS_CNTL_VF_3 regVM_PCIE_ATS_CNTL_VF_3; -typedef union VM_PCIE_ATS_CNTL_VF_4 regVM_PCIE_ATS_CNTL_VF_4; -typedef union VM_PCIE_ATS_CNTL_VF_5 regVM_PCIE_ATS_CNTL_VF_5; -typedef union VM_PCIE_ATS_CNTL_VF_6 regVM_PCIE_ATS_CNTL_VF_6; -typedef union VM_PCIE_ATS_CNTL_VF_7 regVM_PCIE_ATS_CNTL_VF_7; -typedef union VM_PCIE_ATS_CNTL_VF_8 regVM_PCIE_ATS_CNTL_VF_8; -typedef union VM_PCIE_ATS_CNTL_VF_9 regVM_PCIE_ATS_CNTL_VF_9; -typedef union VM_PCIE_ATS_CNTL_VF_10 regVM_PCIE_ATS_CNTL_VF_10; -typedef union VM_PCIE_ATS_CNTL_VF_11 regVM_PCIE_ATS_CNTL_VF_11; -typedef union VM_PCIE_ATS_CNTL_VF_12 regVM_PCIE_ATS_CNTL_VF_12; -typedef union VM_PCIE_ATS_CNTL_VF_13 regVM_PCIE_ATS_CNTL_VF_13; -typedef union VM_PCIE_ATS_CNTL_VF_14 regVM_PCIE_ATS_CNTL_VF_14; -typedef union VM_PCIE_ATS_CNTL_VF_15 regVM_PCIE_ATS_CNTL_VF_15; -typedef union UTCL2_CGTT_CLK_CTRL regUTCL2_CGTT_CLK_CTRL; -typedef union MC_VM_NB_MMIOBASE regMC_VM_NB_MMIOBASE; -typedef union MC_VM_NB_MMIOLIMIT regMC_VM_NB_MMIOLIMIT; -typedef union MC_VM_NB_PCI_CTRL regMC_VM_NB_PCI_CTRL; -typedef union MC_VM_NB_PCI_ARB regMC_VM_NB_PCI_ARB; -typedef union MC_VM_NB_TOP_OF_DRAM_SLOT1 regMC_VM_NB_TOP_OF_DRAM_SLOT1; -typedef union MC_VM_NB_LOWER_TOP_OF_DRAM2 regMC_VM_NB_LOWER_TOP_OF_DRAM2; -typedef union MC_VM_NB_UPPER_TOP_OF_DRAM2 regMC_VM_NB_UPPER_TOP_OF_DRAM2; -typedef union MC_VM_FB_OFFSET regMC_VM_FB_OFFSET; -typedef union MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; -typedef union MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; -typedef union MC_VM_STEERING regMC_VM_STEERING; -typedef union MC_SHARED_VIRT_RESET_REQ regMC_SHARED_VIRT_RESET_REQ; -typedef union MC_MEM_POWER_LS regMC_MEM_POWER_LS; -typedef union MC_VM_CACHEABLE_DRAM_ADDRESS_START regMC_VM_CACHEABLE_DRAM_ADDRESS_START; -typedef union MC_VM_CACHEABLE_DRAM_ADDRESS_END regMC_VM_CACHEABLE_DRAM_ADDRESS_END; -typedef union MC_VM_APT_CNTL regMC_VM_APT_CNTL; -typedef union MC_VM_LOCAL_HBM_ADDRESS_START regMC_VM_LOCAL_HBM_ADDRESS_START; -typedef union MC_VM_LOCAL_HBM_ADDRESS_END regMC_VM_LOCAL_HBM_ADDRESS_END; -typedef union MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL; -typedef union MC_VM_FB_LOCATION_BASE regMC_VM_FB_LOCATION_BASE; -typedef union MC_VM_FB_LOCATION_TOP regMC_VM_FB_LOCATION_TOP; -typedef union MC_VM_AGP_TOP regMC_VM_AGP_TOP; -typedef union MC_VM_AGP_BOT regMC_VM_AGP_BOT; -typedef union MC_VM_AGP_BASE regMC_VM_AGP_BASE; -typedef union MC_VM_SYSTEM_APERTURE_LOW_ADDR regMC_VM_SYSTEM_APERTURE_LOW_ADDR; -typedef union MC_VM_SYSTEM_APERTURE_HIGH_ADDR regMC_VM_SYSTEM_APERTURE_HIGH_ADDR; -typedef union MC_VM_MX_L1_TLB_CNTL regMC_VM_MX_L1_TLB_CNTL; -typedef union GCEA_DRAM_RD_CLI2GRP_MAP0 regGCEA_DRAM_RD_CLI2GRP_MAP0; -typedef union GCEA_DRAM_RD_CLI2GRP_MAP1 regGCEA_DRAM_RD_CLI2GRP_MAP1; -typedef union GCEA_DRAM_WR_CLI2GRP_MAP0 regGCEA_DRAM_WR_CLI2GRP_MAP0; -typedef union GCEA_DRAM_WR_CLI2GRP_MAP1 regGCEA_DRAM_WR_CLI2GRP_MAP1; -typedef union GCEA_DRAM_RD_GRP2VC_MAP regGCEA_DRAM_RD_GRP2VC_MAP; -typedef union GCEA_DRAM_WR_GRP2VC_MAP regGCEA_DRAM_WR_GRP2VC_MAP; -typedef union GCEA_DRAM_RD_LAZY regGCEA_DRAM_RD_LAZY; -typedef union GCEA_DRAM_WR_LAZY regGCEA_DRAM_WR_LAZY; -typedef union GCEA_DRAM_RD_CAM_CNTL regGCEA_DRAM_RD_CAM_CNTL; -typedef union GCEA_DRAM_WR_CAM_CNTL regGCEA_DRAM_WR_CAM_CNTL; -typedef union GCEA_DRAM_PAGE_BURST regGCEA_DRAM_PAGE_BURST; -typedef union GCEA_DRAM_RD_PRI_AGE regGCEA_DRAM_RD_PRI_AGE; -typedef union GCEA_DRAM_WR_PRI_AGE regGCEA_DRAM_WR_PRI_AGE; -typedef union GCEA_DRAM_RD_PRI_QUEUING regGCEA_DRAM_RD_PRI_QUEUING; -typedef union GCEA_DRAM_WR_PRI_QUEUING regGCEA_DRAM_WR_PRI_QUEUING; -typedef union GCEA_DRAM_RD_PRI_FIXED regGCEA_DRAM_RD_PRI_FIXED; -typedef union GCEA_DRAM_WR_PRI_FIXED regGCEA_DRAM_WR_PRI_FIXED; -typedef union GCEA_DRAM_RD_PRI_URGENCY regGCEA_DRAM_RD_PRI_URGENCY; -typedef union GCEA_DRAM_WR_PRI_URGENCY regGCEA_DRAM_WR_PRI_URGENCY; -typedef union GCEA_DRAM_RD_PRI_QUANT_PRI1 regGCEA_DRAM_RD_PRI_QUANT_PRI1; -typedef union GCEA_DRAM_RD_PRI_QUANT_PRI2 regGCEA_DRAM_RD_PRI_QUANT_PRI2; -typedef union GCEA_DRAM_RD_PRI_QUANT_PRI3 regGCEA_DRAM_RD_PRI_QUANT_PRI3; -typedef union GCEA_DRAM_WR_PRI_QUANT_PRI1 regGCEA_DRAM_WR_PRI_QUANT_PRI1; -typedef union GCEA_DRAM_WR_PRI_QUANT_PRI2 regGCEA_DRAM_WR_PRI_QUANT_PRI2; -typedef union GCEA_DRAM_WR_PRI_QUANT_PRI3 regGCEA_DRAM_WR_PRI_QUANT_PRI3; -typedef union GCEA_ADDRNORM_BASE_ADDR0 regGCEA_ADDRNORM_BASE_ADDR0; -typedef union GCEA_ADDRNORM_LIMIT_ADDR0 regGCEA_ADDRNORM_LIMIT_ADDR0; -typedef union GCEA_ADDRNORM_BASE_ADDR1 regGCEA_ADDRNORM_BASE_ADDR1; -typedef union GCEA_ADDRNORM_LIMIT_ADDR1 regGCEA_ADDRNORM_LIMIT_ADDR1; -typedef union GCEA_ADDRNORM_OFFSET_ADDR1 regGCEA_ADDRNORM_OFFSET_ADDR1; -typedef union GCEA_ADDRNORM_HOLE_CNTL regGCEA_ADDRNORM_HOLE_CNTL; -typedef union GCEA_ADDRDEC_BANK_CFG regGCEA_ADDRDEC_BANK_CFG; -typedef union GCEA_ADDRDEC_MISC_CFG regGCEA_ADDRDEC_MISC_CFG; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 regGCEA_ADDRDECDRAM_ADDR_HASH_BANK0; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 regGCEA_ADDRDECDRAM_ADDR_HASH_BANK1; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 regGCEA_ADDRDECDRAM_ADDR_HASH_BANK2; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 regGCEA_ADDRDECDRAM_ADDR_HASH_BANK3; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 regGCEA_ADDRDECDRAM_ADDR_HASH_BANK4; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_PC regGCEA_ADDRDECDRAM_ADDR_HASH_PC; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_PC2 regGCEA_ADDRDECDRAM_ADDR_HASH_PC2; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_CS0 regGCEA_ADDRDECDRAM_ADDR_HASH_CS0; -typedef union GCEA_ADDRDECDRAM_ADDR_HASH_CS1 regGCEA_ADDRDECDRAM_ADDR_HASH_CS1; -typedef union GCEA_ADDRDECDRAM_HARVEST_ENABLE regGCEA_ADDRDECDRAM_HARVEST_ENABLE; -typedef union GCEA_ADDRDEC0_BASE_ADDR_CS0 regGCEA_ADDRDEC0_BASE_ADDR_CS0; -typedef union GCEA_ADDRDEC0_BASE_ADDR_CS1 regGCEA_ADDRDEC0_BASE_ADDR_CS1; -typedef union GCEA_ADDRDEC0_BASE_ADDR_CS2 regGCEA_ADDRDEC0_BASE_ADDR_CS2; -typedef union GCEA_ADDRDEC0_BASE_ADDR_CS3 regGCEA_ADDRDEC0_BASE_ADDR_CS3; -typedef union GCEA_ADDRDEC0_BASE_ADDR_SECCS0 regGCEA_ADDRDEC0_BASE_ADDR_SECCS0; -typedef union GCEA_ADDRDEC0_BASE_ADDR_SECCS1 regGCEA_ADDRDEC0_BASE_ADDR_SECCS1; -typedef union GCEA_ADDRDEC0_BASE_ADDR_SECCS2 regGCEA_ADDRDEC0_BASE_ADDR_SECCS2; -typedef union GCEA_ADDRDEC0_BASE_ADDR_SECCS3 regGCEA_ADDRDEC0_BASE_ADDR_SECCS3; -typedef union GCEA_ADDRDEC0_ADDR_MASK_CS01 regGCEA_ADDRDEC0_ADDR_MASK_CS01; -typedef union GCEA_ADDRDEC0_ADDR_MASK_CS23 regGCEA_ADDRDEC0_ADDR_MASK_CS23; -typedef union GCEA_ADDRDEC0_ADDR_MASK_SECCS01 regGCEA_ADDRDEC0_ADDR_MASK_SECCS01; -typedef union GCEA_ADDRDEC0_ADDR_MASK_SECCS23 regGCEA_ADDRDEC0_ADDR_MASK_SECCS23; -typedef union GCEA_ADDRDEC0_ADDR_CFG_CS01 regGCEA_ADDRDEC0_ADDR_CFG_CS01; -typedef union GCEA_ADDRDEC0_ADDR_CFG_CS23 regGCEA_ADDRDEC0_ADDR_CFG_CS23; -typedef union GCEA_ADDRDEC0_ADDR_SEL_CS01 regGCEA_ADDRDEC0_ADDR_SEL_CS01; -typedef union GCEA_ADDRDEC0_ADDR_SEL_CS23 regGCEA_ADDRDEC0_ADDR_SEL_CS23; -typedef union GCEA_ADDRDEC0_COL_SEL_LO_CS01 regGCEA_ADDRDEC0_COL_SEL_LO_CS01; -typedef union GCEA_ADDRDEC0_COL_SEL_LO_CS23 regGCEA_ADDRDEC0_COL_SEL_LO_CS23; -typedef union GCEA_ADDRDEC0_COL_SEL_HI_CS01 regGCEA_ADDRDEC0_COL_SEL_HI_CS01; -typedef union GCEA_ADDRDEC0_COL_SEL_HI_CS23 regGCEA_ADDRDEC0_COL_SEL_HI_CS23; -typedef union GCEA_ADDRDEC0_RM_SEL_CS01 regGCEA_ADDRDEC0_RM_SEL_CS01; -typedef union GCEA_ADDRDEC0_RM_SEL_CS23 regGCEA_ADDRDEC0_RM_SEL_CS23; -typedef union GCEA_ADDRDEC0_RM_SEL_SECCS01 regGCEA_ADDRDEC0_RM_SEL_SECCS01; -typedef union GCEA_ADDRDEC0_RM_SEL_SECCS23 regGCEA_ADDRDEC0_RM_SEL_SECCS23; -typedef union GCEA_ADDRDEC1_BASE_ADDR_CS0 regGCEA_ADDRDEC1_BASE_ADDR_CS0; -typedef union GCEA_ADDRDEC1_BASE_ADDR_CS1 regGCEA_ADDRDEC1_BASE_ADDR_CS1; -typedef union GCEA_ADDRDEC1_BASE_ADDR_CS2 regGCEA_ADDRDEC1_BASE_ADDR_CS2; -typedef union GCEA_ADDRDEC1_BASE_ADDR_CS3 regGCEA_ADDRDEC1_BASE_ADDR_CS3; -typedef union GCEA_ADDRDEC1_BASE_ADDR_SECCS0 regGCEA_ADDRDEC1_BASE_ADDR_SECCS0; -typedef union GCEA_ADDRDEC1_BASE_ADDR_SECCS1 regGCEA_ADDRDEC1_BASE_ADDR_SECCS1; -typedef union GCEA_ADDRDEC1_BASE_ADDR_SECCS2 regGCEA_ADDRDEC1_BASE_ADDR_SECCS2; -typedef union GCEA_ADDRDEC1_BASE_ADDR_SECCS3 regGCEA_ADDRDEC1_BASE_ADDR_SECCS3; -typedef union GCEA_ADDRDEC1_ADDR_MASK_CS01 regGCEA_ADDRDEC1_ADDR_MASK_CS01; -typedef union GCEA_ADDRDEC1_ADDR_MASK_CS23 regGCEA_ADDRDEC1_ADDR_MASK_CS23; -typedef union GCEA_ADDRDEC1_ADDR_MASK_SECCS01 regGCEA_ADDRDEC1_ADDR_MASK_SECCS01; -typedef union GCEA_ADDRDEC1_ADDR_MASK_SECCS23 regGCEA_ADDRDEC1_ADDR_MASK_SECCS23; -typedef union GCEA_ADDRDEC1_ADDR_CFG_CS01 regGCEA_ADDRDEC1_ADDR_CFG_CS01; -typedef union GCEA_ADDRDEC1_ADDR_CFG_CS23 regGCEA_ADDRDEC1_ADDR_CFG_CS23; -typedef union GCEA_ADDRDEC1_ADDR_SEL_CS01 regGCEA_ADDRDEC1_ADDR_SEL_CS01; -typedef union GCEA_ADDRDEC1_ADDR_SEL_CS23 regGCEA_ADDRDEC1_ADDR_SEL_CS23; -typedef union GCEA_ADDRDEC1_COL_SEL_LO_CS01 regGCEA_ADDRDEC1_COL_SEL_LO_CS01; -typedef union GCEA_ADDRDEC1_COL_SEL_LO_CS23 regGCEA_ADDRDEC1_COL_SEL_LO_CS23; -typedef union GCEA_ADDRDEC1_COL_SEL_HI_CS01 regGCEA_ADDRDEC1_COL_SEL_HI_CS01; -typedef union GCEA_ADDRDEC1_COL_SEL_HI_CS23 regGCEA_ADDRDEC1_COL_SEL_HI_CS23; -typedef union GCEA_ADDRDEC1_RM_SEL_CS01 regGCEA_ADDRDEC1_RM_SEL_CS01; -typedef union GCEA_ADDRDEC1_RM_SEL_CS23 regGCEA_ADDRDEC1_RM_SEL_CS23; -typedef union GCEA_ADDRDEC1_RM_SEL_SECCS01 regGCEA_ADDRDEC1_RM_SEL_SECCS01; -typedef union GCEA_ADDRDEC1_RM_SEL_SECCS23 regGCEA_ADDRDEC1_RM_SEL_SECCS23; -typedef union GCEA_IO_RD_CLI2GRP_MAP0 regGCEA_IO_RD_CLI2GRP_MAP0; -typedef union GCEA_IO_RD_CLI2GRP_MAP1 regGCEA_IO_RD_CLI2GRP_MAP1; -typedef union GCEA_IO_WR_CLI2GRP_MAP0 regGCEA_IO_WR_CLI2GRP_MAP0; -typedef union GCEA_IO_WR_CLI2GRP_MAP1 regGCEA_IO_WR_CLI2GRP_MAP1; -typedef union GCEA_IO_RD_COMBINE_FLUSH regGCEA_IO_RD_COMBINE_FLUSH; -typedef union GCEA_IO_WR_COMBINE_FLUSH regGCEA_IO_WR_COMBINE_FLUSH; -typedef union GCEA_IO_GROUP_BURST regGCEA_IO_GROUP_BURST; -typedef union GCEA_IO_RD_PRI_AGE regGCEA_IO_RD_PRI_AGE; -typedef union GCEA_IO_WR_PRI_AGE regGCEA_IO_WR_PRI_AGE; -typedef union GCEA_IO_RD_PRI_QUEUING regGCEA_IO_RD_PRI_QUEUING; -typedef union GCEA_IO_WR_PRI_QUEUING regGCEA_IO_WR_PRI_QUEUING; -typedef union GCEA_IO_RD_PRI_FIXED regGCEA_IO_RD_PRI_FIXED; -typedef union GCEA_IO_WR_PRI_FIXED regGCEA_IO_WR_PRI_FIXED; -typedef union GCEA_IO_RD_PRI_URGENCY regGCEA_IO_RD_PRI_URGENCY; -typedef union GCEA_IO_WR_PRI_URGENCY regGCEA_IO_WR_PRI_URGENCY; -typedef union GCEA_IO_RD_PRI_URGENCY_MASK regGCEA_IO_RD_PRI_URGENCY_MASK; -typedef union GCEA_IO_WR_PRI_URGENCY_MASK regGCEA_IO_WR_PRI_URGENCY_MASK; -typedef union GCEA_IO_RD_PRI_QUANT_PRI1 regGCEA_IO_RD_PRI_QUANT_PRI1; -typedef union GCEA_IO_RD_PRI_QUANT_PRI2 regGCEA_IO_RD_PRI_QUANT_PRI2; -typedef union GCEA_IO_RD_PRI_QUANT_PRI3 regGCEA_IO_RD_PRI_QUANT_PRI3; -typedef union GCEA_IO_WR_PRI_QUANT_PRI1 regGCEA_IO_WR_PRI_QUANT_PRI1; -typedef union GCEA_IO_WR_PRI_QUANT_PRI2 regGCEA_IO_WR_PRI_QUANT_PRI2; -typedef union GCEA_IO_WR_PRI_QUANT_PRI3 regGCEA_IO_WR_PRI_QUANT_PRI3; -typedef union GCEA_SDP_ARB_DRAM regGCEA_SDP_ARB_DRAM; -typedef union GCEA_SDP_ARB_FINAL regGCEA_SDP_ARB_FINAL; -typedef union GCEA_SDP_DRAM_PRIORITY regGCEA_SDP_DRAM_PRIORITY; -typedef union GCEA_SDP_IO_PRIORITY regGCEA_SDP_IO_PRIORITY; -typedef union GCEA_SDP_CREDITS regGCEA_SDP_CREDITS; -typedef union GCEA_SDP_TAG_RESERVE0 regGCEA_SDP_TAG_RESERVE0; -typedef union GCEA_SDP_TAG_RESERVE1 regGCEA_SDP_TAG_RESERVE1; -typedef union GCEA_SDP_VCC_RESERVE0 regGCEA_SDP_VCC_RESERVE0; -typedef union GCEA_SDP_VCC_RESERVE1 regGCEA_SDP_VCC_RESERVE1; -typedef union GCEA_SDP_VCD_RESERVE0 regGCEA_SDP_VCD_RESERVE0; -typedef union GCEA_SDP_VCD_RESERVE1 regGCEA_SDP_VCD_RESERVE1; -typedef union GCEA_SDP_REQ_CNTL regGCEA_SDP_REQ_CNTL; -typedef union GCEA_MISC regGCEA_MISC; -typedef union GCEA_LATENCY_SAMPLING regGCEA_LATENCY_SAMPLING; -typedef union GCEA_PERFCOUNTER_LO regGCEA_PERFCOUNTER_LO; -typedef union GCEA_PERFCOUNTER_HI regGCEA_PERFCOUNTER_HI; -typedef union GCEA_PERFCOUNTER0_CFG regGCEA_PERFCOUNTER0_CFG; -typedef union GCEA_PERFCOUNTER1_CFG regGCEA_PERFCOUNTER1_CFG; -typedef union GCEA_PERFCOUNTER_RSLT_CNTL regGCEA_PERFCOUNTER_RSLT_CNTL; -typedef union GCEA_MAM_CTRL regGCEA_MAM_CTRL; -typedef union GCEA_MAM_CTRL2 regGCEA_MAM_CTRL2; -typedef union GCEA_MAM_ARAM_FLUSH_ADDR_LO regGCEA_MAM_ARAM_FLUSH_ADDR_LO; -typedef union GCEA_MAM_DBIT_QUERY regGCEA_MAM_DBIT_QUERY; -typedef union GCEA_MAM_STATUS regGCEA_MAM_STATUS; -typedef union GCEA_EDC_CNT regGCEA_EDC_CNT; -typedef union GCEA_EDC_CNT2 regGCEA_EDC_CNT2; -typedef union GCEA_DSM_CNTL regGCEA_DSM_CNTL; -typedef union GCEA_DSM_CNTLA regGCEA_DSM_CNTLA; -typedef union GCEA_DSM_CNTLB regGCEA_DSM_CNTLB; -typedef union GCEA_DSM_CNTL2 regGCEA_DSM_CNTL2; -typedef union GCEA_DSM_CNTL2A regGCEA_DSM_CNTL2A; -typedef union GCEA_DSM_CNTL2B regGCEA_DSM_CNTL2B; -typedef union GCEA_TCC_XBR_CREDITS regGCEA_TCC_XBR_CREDITS; -typedef union GCEA_TCC_XBR_MAXBURST regGCEA_TCC_XBR_MAXBURST; -typedef union GCEA_PROBE_CNTL regGCEA_PROBE_CNTL; -typedef union GCEA_PROBE_MAP regGCEA_PROBE_MAP; -typedef union GCEA_ERR_STATUS regGCEA_ERR_STATUS; -typedef union GCEA_MISC2 regGCEA_MISC2; -typedef union GCEA_SDP_BACKDOOR_CMDCREDITS0 regGCEA_SDP_BACKDOOR_CMDCREDITS0; -typedef union GCEA_SDP_BACKDOOR_CMDCREDITS1 regGCEA_SDP_BACKDOOR_CMDCREDITS1; -typedef union GCEA_SDP_BACKDOOR_DATACREDITS0 regGCEA_SDP_BACKDOOR_DATACREDITS0; -typedef union GCEA_SDP_BACKDOOR_DATACREDITS1 regGCEA_SDP_BACKDOOR_DATACREDITS1; -typedef union GCEA_SDP_BACKDOOR_MISCCREDITS regGCEA_SDP_BACKDOOR_MISCCREDITS; -typedef union GCEA_SDP_ENABLE regGCEA_SDP_ENABLE; -typedef union GCEA_CGTT_CLK_CTRL regGCEA_CGTT_CLK_CTRL; -typedef union GCEA_SECURE_CTRL regGCEA_SECURE_CTRL; - -} // gfx9 -} // pm4_profile - -#endif diff --git a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_utils.h b/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_utils.h deleted file mode 100644 index 9d561ae814..0000000000 --- a/runtime/hsa-amd-aqlprofile/gfxip/gfx9/gfx9_utils.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - *********************************************************************************************************************** - * - * Trade secret of Advanced Micro Devices, Inc. - * Copyright (c) 2016, Advanced Micro Devices, Inc., (unpublished) - * - * All rights reserved. This notice is intended as a precaution against inadvertent publication and - *does not imply - * publication or any waiver of confidentiality. The year included in the foregoing notice is the - *year of creation of - * the work. - * - **********************************************************************************************************************/ - -#ifndef _GFX9_UTILS_H_ -#define _GFX9_UTILS_H_ - -namespace pm4_profile { -namespace gfx9 { - -/* - * PM4 packet helper constants and macros. - * Constructed from header file: - * core/hw/gfxip/gfx9/chip/gfx9_f32_pfp_pm4_packets_gr.h - */ - -// Shift amounts for each field of a type-3 PM4 header: -#define PM4_PREDICATE_SHIFT 0 -#define PM4_SHADERTYPE_SHIFT 1 -#define PM4_TYPE_SHIFT 30 -#define PM4_COUNT_SHIFT 16 -#define PM4_OPCODE_SHIFT 8 - -/* - * Constructs a PM4 type-3 header and packs it into a uint. - */ -#define PM4_TYPE3_HDR(_opc_, _count_) \ - (uint32_t)((3) << PM4_TYPE_SHIFT | ((_count_)-2) << PM4_COUNT_SHIFT | (_opc_) << PM4_OPCODE_SHIFT) - -// Packet shader types: -#define PM4_SHADER_GRAPHICS 0 -#define PM4_SHADER_COMPUTE 1 - -// Indices into VGT event type table -#define EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP 0 -#define EVENT_WRITE_INDEX_ZPASS_DONE 1 -#define EVENT_WRITE_INDEX_SAMPLE_PIPELINESTAT 2 -#define EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS 3 -#define EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH 4 -#define EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP 5 -#define EVENT_WRITE_INDEX_ANY_EOS_TIMESTAMP 6 -#define EVENT_WRITE_EOS_INDEX_CSDONE_PSDONE 6 -#define EVENT_WRITE_INDEX_CACHE_FLUSH_EVENT 7 -#define EVENT_WRITE_INDEX_INVALID 0xffffffff - -static const uint8_t EventTypeToIndexTable[] = { - 0, // Reserved_0x00 0x00000000 - EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS1 - // 0x00000001 - EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS2 - // 0x00000002 - EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS3 - // 0x00000003 - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_TS 0x00000004 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CONTEXT_DONE 0x00000005 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH 0x00000006 - EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // CS_PARTIAL_FLUSH 0x00000007 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_SYNC 0x00000008 - 0, // Reserved_0x09 0x00000009 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_RESET 0x0000000a - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_INCR_DE 0x0000000b - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_IB_END 0x0000000c - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RST_PIX_CNT 0x0000000d - 0, // Reserved_0x0E 0x0000000e - EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // VS_PARTIAL_FLUSH 0x0000000f - EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // PS_PARTIAL_FLUSH 0x00000010 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_HS_OUTPUT 0x00000011 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_LS_OUTPUT 0x00000012 - 0, // Reserved_0x13 0x00000013 - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_AND_INV_TS_EVENT - // 0x00000014 - EVENT_WRITE_INDEX_ZPASS_DONE, // ZPASS_DONE 0x00000015 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH_AND_INV_EVENT - // 0x00000016 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_START 0x00000017 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_STOP 0x00000018 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_START 0x00000019 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_STOP 0x0000001a - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_SAMPLE 0x0000001b - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_ES_OUTPUT 0x0000001c - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_GS_OUTPUT 0x0000001d - EVENT_WRITE_INDEX_SAMPLE_PIPELINESTAT, // SAMPLE_PIPELINESTAT 0x0000001e - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SO_VGTSTREAMOUT_FLUSH 0x0000001f - EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS - // 0x00000020 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RESET_VTX_CNT 0x00000021 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // BLOCK_CONTEXT_DONE 0x00000022 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CS_CONTEXT_DONE 0x00000023 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_FLUSH 0x00000024 - 0, // Reserved_0x25 0x00000025 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SQ_NON_EVENT 0x00000026 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SC_SEND_DB_VPZ 0x00000027 - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // BOTTOM_OF_PIPE_TS 0x00000028 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_SX_TS 0x00000029 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // DB_CACHE_FLUSH_AND_INV 0x0000002a - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_DB_DATA_TS 0x0000002b - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_DB_META 0x0000002c - EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_CB_DATA_TS 0x0000002d - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_META 0x0000002e - EVENT_WRITE_EOS_INDEX_CSDONE_PSDONE, // CS_DONE 0x0000002f - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PS_DONE 0x00000030 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_PIXEL_DATA - // 0x00000031 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SX_CB_RAT_ACK_REQUEST 0x00000032 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_START 0x00000033 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_STOP 0x00000034 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_MARKER 0x00000035 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FLUSH 0x00000036 - EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FINISH 0x00000037 -}; - -/// @brief Enum specifying the size of elements of a buffer -enum BufElementSize { - kBufElementSize2 = 0, - kBufElementSize4 = 1, - kBufElementSize8 = 2, - kBufElementSize16 = 3 -}; - -/// @brief Enum specifying the striding of a buffer -enum BufIndexStride { - kBufIndexStride8 = 0, - kBufIndexStride16 = 1, - kBufIndexStride32 = 2, - kBufIndexStride64 = 3 -}; - -} // gfx9 -} // pm4_profile - -#endif // _GFX9_UTILS_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/CMakeLists.txt b/runtime/hsa-amd-aqlprofile/src/CMakeLists.txt deleted file mode 100644 index 36b8928879..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/CMakeLists.txt +++ /dev/null @@ -1,70 +0,0 @@ -# -# Minimum version of cmake required -# -cmake_minimum_required ( VERSION 3.5.0 ) - -# -# Setup flag to be verbose or not -# -set ( CMAKE_VERBOSE_MAKEFILE TRUE CACHE BOOL "Verbose Output" FORCE ) - -# -# Set name for the project -# @note: Must come before adding any sub-directories -# -set ( TARGET_NAME "aqlprofile" ) -project ( ${TARGET_NAME} ) - -if ( NOT DEFINED PROJ_DIR ) - set ( PROJ_DIR ${CMAKE_CURRENT_SOURCE_DIR} ) - set ( ROOT_DIR ${PROJ_DIR}/.. ) -endif () - -set ( HSA_RUNTIME_DIR ${PROJ_DIR}/../../hsa-runtime ) -set ( API_DIR ${HSA_RUNTIME_DIR}/inc ) -set ( CORE_UTIL_DIR ${HSA_RUNTIME_DIR}/core/util ) - -include_directories ( ${ROOT_DIR} ) - -# -# Validate required build environment is setup correctly -# -include ( ${ROOT_DIR}/cmake_modules/validateBldEnv.cmake ) - -# -# Setup tool chain flags - preprocessor, compiler and linker -# -include ( ${ROOT_DIR}/cmake_modules/exportToolFlags.cmake ) - -# -# Set Name for Cmdwriter library and build it as a -# static library to be linked with others -# -set ( CMDWRITER_LIB "commandwriter${ONLY64STR}" ) -add_subdirectory ( ${PROJ_DIR}/commandwriter "${PROJECT_BINARY_DIR}/commandwriter" ) - -# -# Set Name for ThreadTrace library and build it as a -# static library to be linked with others -# -set ( SQTT_LIB "sqtt${ONLY64STR}" ) -add_subdirectory ( ${PROJ_DIR}/threadtrace "${PROJECT_BINARY_DIR}/threadtrace" ) - -# -# Set Name for Profiler library and build it as a -# static library to be linked with others -# -set ( PMC_LIB "pmc${ONLY64STR}" ) -add_subdirectory ( ${PROJ_DIR}/perfcounter "${PROJECT_BINARY_DIR}/perfcounter" ) - -# -# Build the library and link it with other static -# libraries that have been built in this regard -# -set ( TARGET_LIB "${TARGET_NAME}${ONLY64STR}" ) -add_subdirectory ( ${PROJ_DIR}/core "${PROJECT_BINARY_DIR}/core" ) - -# -# Creating the library link -# -execute_process ( COMMAND sh -xc "/bin/ln -s core/lib${TARGET_LIB}.so libhsa-amd-${TARGET_LIB}.so.1" ) diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/CMakeLists.txt b/runtime/hsa-amd-aqlprofile/src/commandwriter/CMakeLists.txt deleted file mode 100644 index a7fca078b3..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# -# Source files for Rocr Cmdwriter -# -set ( CmdWriterSrcs gfx8_cmdwriter.cpp ) -set ( CmdWriterSrcs ${CmdWriterSrcs} gfx9_cmdwriter.cpp ) - -# -# Build Cmdwriter as a Static Library object -# -add_library ( ${CMDWRITER_LIB} STATIC ${CmdWriterSrcs} ) diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/cmdwriter.h b/runtime/hsa-amd-aqlprofile/src/commandwriter/cmdwriter.h deleted file mode 100644 index c7c403840d..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/cmdwriter.h +++ /dev/null @@ -1,498 +0,0 @@ -// cmdwriter.h -// Header file for CommandWriter and CmdBuf interfaces - -#ifndef _CMDWRITER_H_ -#define _CMDWRITER_H_ - -#include -#include -#include - -namespace pm4_profile { - -// User defined options for flusing cache -typedef struct FlushCacheOptions_ { - bool l1, l2; - bool icache, kcache; - bool l1_vol, l2_vol, kcache_vol; - FlushCacheOptions_() { - l1 = l2 = icache = kcache = false; - l1_vol = l2_vol = kcache_vol = false; - }; -} FlushCacheOptions; - -/// @brief Interface to build a list of Gpu commands into a byte -/// buffer. Classes implementing this interface are used to translate -/// various Gpu commands as byte stream. -/// -/// @note: The Api does not require implementations to be thread safe. -/// Users are therefore required to be access in a serialized manner. -class CmdBuf { - public: - /// Default destructor. - virtual ~CmdBuf() {} - - /// @brief Resets the command buffer object. All of the commands - /// previously packed into the buffer are lost i.e. the number of - /// bytes in command stream is reset. - /// - /// @note: This convenience Api is provided to allow reuse of the - /// command buffer object. - /// - /// @return bool true if successful, false otherwise. - virtual bool Reset(void) = 0; - - /// @brief Appends input command into a buffer that could - /// be queried for its size and other properties. The append - /// does not verify the contents. - /// - /// @param cmd Buffer containing one or more instances of Gpu commands - /// - /// @param size size of the Gpu commands in bytes. - /// - /// @return void - virtual void AppendCommand(const void* cmd, uint32_t size) = 0; - - /// @brief Returns the total size (in bytes) of the accumulated commands. - /// - /// @return size_t size of Gpu commands in bytes - virtual size_t Size() const = 0; - - private: - /// Indexes the command buffer by dwords. Allows accessing constants - /// in an assembled command buffer. - virtual uint32_t& operator[](size_t index) = 0; - - friend class CommandWriter; -}; - -/// @brief Implements the interface CmdBuf and thus can be used to -/// translate various Gpu commands as byte stream. -/// -/// @note: The Api does not require implementations to be thread safe. -/// Users are therefore required to be access in a serialized manner. -class DefaultCmdBuf : public CmdBuf { - public: - /// @brief Append the command into the underlying buffer - /// - /// @param cmd Buffer containing one or more instances of Gpu commands - /// - /// @param size Size of Gpu command(s) in bytes - /// - /// @retur void - virtual void AppendCommand(const void* cmd, uint32_t size) { - memcpy(ReserveCmdbufSpace(size), cmd, size); - } - - /// @brief Resets the Gpu command buffer - bool Reset() { - cmdbuf_.clear(); - return true; - } - - /// Size of Gpu commands in bytes in the underlying buffer - size_t Size() const { return cmdbuf_.size() * sizeof(StorageType); } - - /// Address of the start of accumulated commands. - const void* Base() const { return &cmdbuf_[0]; } - - private: - /// @brief Returns reference to the value of Gpu command buffer - /// at specified index - /// - /// @param index Specifies the buffer index whose value is needed - /// - /// @return uint32_t & Reference of the value being returned - uint32_t& operator[](size_t index) { return cmdbuf_[index]; } - - /// @brief Increase Gpu command buffer by specified size - /// - /// @param size Size in bytes by which command buffer should - /// be resized. - /// - /// @return void * Pointer into the buffer where the next - /// command can be written - void* ReserveCmdbufSpace(std::size_t size) { - const size_t len = cmdbuf_.size(); - cmdbuf_.resize(len + size / sizeof(StorageType)); - return &cmdbuf_[len]; - } - - /// @brief Defines Gpu command buffer as a vector of StorageType - typedef uint32_t StorageType; - std::vector cmdbuf_; -}; - -/// @brief Specifies the public interface of CommandWriter for use by -/// clients to build Gpu command streams. -class CommandWriter { - public: - /// @brief These enums specify the operation to perform in the packet - /// generated by BuildAtomicPacket. The commenting for each enum uses - /// the arguments to the function BuildAtomicPacket to express the - /// resulting operation. - enum AtomicType { - - /// *destination = *destination + 1; - kAtomicTypeIncrement, - - /// *destination = *destination - 1; - kAtomicTypeDecrement, - - /// if (*destination == compare) *destination = value; - kAtomicTypeCompareAndSwap, - - /// while (*destination != compare); - /// *destination = value; - kAtomicTypeBlockingCompareAndSwap, - - /// *destination = *destination + value; - kAtomicAdd, - - /// *destination = *destination - value; - kAtomicSubtract, - - /// *destination = value; - kAtomicSwap - }; - - /// @brief These enums specify the VGT EVENT TYPE to issue and wait for. - /// Command Processor (CP) uses these events to communicate with SPI to - /// learn about outstanding waves and determine kernel completion. - enum VgtEventType { - - /// Enable Performance Counters - kPerfCntrsStart, - - /// Disable Performance Counters - kPerfCntrsStop, - - /// Read Performance Counters - kPerfCntrsSample, - - /// Enable a Thread Trace session - kThrdTraceStart, - - /// Disable a Thread Trace session - kThrdTraceStop, - - /// Enable flushing of thread trace buffers - kThrdTraceFlush, - - /// Enables resetting of BASE register to its last value - /// including flushing of thread trace buffers. This could - /// be used to toggle between two buffers so as to allow - /// collection of large token data - kThrdTraceFinish - }; - - /// @brief Returns the Dword that encodes a No-Op for the CP - /// - /// @return uint32_t Dword that can be used to populate a Pm4 - /// command queue. - /// - virtual uint32_t GetNoOpCmd() = 0; - - /// @brief Build an instance of Barrier command and copy it into - /// the input commmand buffer - /// - /// @param cmdbuf Pointer to command buffer which is updated with - /// an instance of Barrier command. - /// - /// @return void - virtual void BuildBarrierCommand(CmdBuf* cmdbuf) = 0; - - /// @brief Builds the Gpu command to reference indirectly a stream - /// of other Gpu commands. The launch command is then copied into - /// the command buffer parameter. - /// - /// @param cmdBuf command buffer to be appended with launch command - /// - /// @param cmd_addr Address of command buffer carrying command stream - /// - /// @param cmd_size Size of dispatch command stream in bytes - /// - /// @return void - virtual void BuildIndirectBufferCmd(CmdBuf* cmdbuf, const void* cmd_addr, - std::size_t cmd_size) = 0; - - /// @brief Build a Gpu command that triggers an event whose type - /// is specified by input parameter. It then copies it into the input - /// command buffer - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param event Id of Event to be triggered by Gpu - /// - /// @return void - virtual void BuildWriteEventPacket(CmdBuf* cmdbuf, uint32_t event) = 0; - - /// @bried Builds a Gpu command to wait until condition is realized - /// - /// @param cmdbuf command buffer to be appended with launch command - /// - /// @param mem_space if the address is in memory or is a register offset - /// - /// @param wait_addr address to wait on - /// - /// @param func_eq true means equal, false means not-equal - /// - /// @param mask_val Mask to apply on value from addr in comparison - /// - /// @param wait_val value to apply for the func given above - virtual void BuildWaitRegMemCommand(CmdBuf* cmdbuf, bool mem_space, uint64_t wait_addr, - bool func_eq, uint32_t mask_val, uint32_t wait_val) = 0; - - virtual void BuildUpdateHostAddress(CmdBuf* cmdbuf, uint64_t* addr, int64_t value) = 0; - - /// @brief Build CP command to program a Gpu register - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// @param addr Register to be programmed - /// @param value Value to write into register - /// - /// @return void - virtual void BuildWriteUConfigRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) = 0; - - /// @brief Build and copy WriteShReg command - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param addr Offset of the register - /// - /// @param value Value to write into register - /// - /// @return void - virtual void BuildWriteShRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) = 0; - - /// @brief Builds a Gpu command to flush Gpu caches and write a - /// user defined value at a configurable location that is Gpu - /// accessible. - /// - /// @param cmdBuf Command buffer to be appended with bottom of pipe - /// notification command - /// - /// @param write_addr Address into which Gpu should write - /// - /// @param write_val Value to write into user provided address - /// - /// @param interrupt True if Gpu should raise an interrupt upon writing - /// the user value - /// - /// @return void - virtual void BuildBOPNotifyCmd(CmdBuf* cmdbuf, const void* write_addr, uint32_t write_val, - bool intrpt) = 0; - - - /// @brief Build a Gpu command that copies data from a specified - /// source to destination - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param reg_to_mem flag to indicate if values are being read from a - /// Register or a memory location - /// - /// @param src_addr_lo Low 32-bit Source address of the data to read from - /// - /// @param src_addr_hi High 32-bit Source address of the data to read from - /// - /// @param dst_addr Destination address for the data to be written to - /// - /// @param size Size of the data to be written - /// - /// @param wait True if Gpu command should confirm the write operation - /// operation has completed successfully - /// - /// @return void - /// - /// @NOTE Change interface to use void* for Src and void* for Dest - virtual void BuildCopyDataPacket(CmdBuf* cmdbuf, uint32_t src_sel, uint32_t src_addr_lo, - uint32_t src_addr_hi, uint32_t* dst_addr, uint32_t size, - bool wait) = 0; - - /// @brief Build and copy a WaitIdle Gpu command into command buffer - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @return void - virtual void BuildWriteWaitIdlePacket(CmdBuf* cmdbuf) = 0; - - // Will issue a VGT event including a cache flush later on - virtual void BuildVgtEventPacket(CmdBuf* cmdbuf, uint32_t vgtEvent) = 0; - - /// @brief Build and copy a WriteRegister Gpu command into command buffer - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param addr Register into which to write - /// - /// @param value Value to write into register - /// - /// @return void - virtual void BuildWriteRegisterPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) = 0; - - /// @brief Build and copy a Gpu command to query the status of a - /// WriteEvent into command buffer - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param event Id of Event whose status is to be queried - /// - /// @param addr Address to update the status of WriteEvent operation - /// - /// @return void - virtual void BuildWriteEventQueryPacket(CmdBuf* cmdBuf, uint32_t event, uint32_t* addr) = 0; - - /// @brief Builds and copies a Gpu comamnd to peform user specified - /// operation atomically. The various atomic operations on integers - /// that are supported include: increment, decrement, add, subtract, - /// compare-and-swap and swap. The operation to perform is specified - /// by the enum AtomicType. - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param atomic_op Id of the atomic operation to perform - /// - /// @param addr Pointer to the memory block where atomic operation - /// would be performed - /// - /// @param value New value to write if atomic operation can be performed - /// - /// @param compare Value to compare if atomic operation is a compare-and-swap - /// - /// @return void - virtual void BuildAtomicPacket(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint32_t* addr, - uint32_t value = 0, uint32_t compare = 0) = 0; - - /// @brief Builds and copies a Gpu comamnd to peform user specified - /// operation atomically. The various atomic operations on integers - /// that are supported include: increment, decrement, add, subtract, - /// compare-and-swap and swap. The operation to perform is specified - /// by the enum AtomicType. - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param atomic_op Id of the atomic operation to perform - /// - /// @param addr Pointer to the memory block where atomic operation - /// would be performed - /// - /// @param value New value to write if atomic operation can be performed - /// - /// @param compare Value to compare if atomic operation is a compare-and-swap - /// - /// @return void - virtual void BuildAtomicPacket64(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint64_t* addr, - uint64_t value = 0, uint64_t compare = 0) = 0; - - /// @brief Returns the size of an atomic packet - /// - /// @return size_t Size of atomic packet - virtual size_t SizeOfAtomicPacket() const = 0; - - /// @brief Build and copy a Gpu command that will tell command processor - /// to conditionally execute or skip the next sequence of packets. - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param signal Pointer to an integer that tells the command processor - /// whether to skip or execute the next block of packets. If it is set - /// to 0 the following packets will be skipped, else it will execute the - /// following packets - /// - /// @param count The number of dwords in the following packet stream - /// that will be conditionally executed - /// - /// @return void - virtual void BuildConditionalExecute(CmdBuf* cmdbuf, uint32_t* signal, uint16_t count) = 0; - - /// @brief Builds a CP command to write user specified value - /// at a user specified address. The command is then copied - /// into the command buffer for submission to a device queue. - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param write_addr Address into which CP will write the user - /// specified value - /// - /// @param write_value Value to write into the user specified address - /// - /// @return void - virtual void BuildWriteDataCommand(CmdBuf* cmdbuf, uint32_t* write_addr, - uint32_t write_value) = 0; - - /// @brief Builds a CP command to write user specified value - /// at a user specified address. The command is then copied - /// into the command buffer for submission to a device queue. - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// - /// @param write_addr Address into which CP will write the user - /// specified value - /// - /// @param write_value Value to write into the user specified address - /// - /// @return void - virtual void BuildWriteData64Command(CmdBuf* cmdbuf, uint64_t* write_addr, - uint64_t write_value) = 0; - - /// Writes into input buffer Gpu commands to flush its cache. It is - /// necessary that the buffer provided for flush commands is large - /// enough to accommodate the full set of commands. It should be at - /// least 512 bytes. - /// - /// @param tsCmdBuf Buffer to write commands to. - /// @param writeAddr Registered address into which GPU should write - /// a user provided value upon executing the flush commands. - /// @param writeVal User provided value written by GPU at user provided - /// address, upon executing the flush commands. - /// - /// @return void - virtual void BuildFlushCacheCmd(CmdBuf* cmdbuf, FlushCacheOptions* options, uint32_t* writeAddr, - uint32_t writeVal) = 0; - - /// @brief Builds Gpu command to copy data from source to destination - /// buffer using DMA engine. - /// - /// @param cmdbuf Buffer updated with Gpu copy command - /// @param srcAddr Address of source buffer address - /// @param dstAddr Address of destination buffer address - /// @param copySize Size of data to copy in bytes - /// @param waitForCompletion if command should wait for copying to complete - virtual void BuildDmaDataPacket(CmdBuf* cmdbuf, uint32_t* srcAddrLo, uint32_t* dstAddr, - uint32_t copySize, bool waitForCompletion) = 0; - - /// @brief Release resources used by CommandWriter - virtual ~CommandWriter(){}; - - protected: - /// @brief Return the reference to a value in the command buffer - uint32_t& IndexBuffer(CmdBuf* cmdbuf, uint32_t index) { return (*cmdbuf)[index]; } -}; - -/// @brief Returns the lower 32-bits of a value -inline uint32_t Low32(uint64_t u) { return (u & 0xFFFFFFFFUL); } - -/// @brief Returns the upper 32-bits of a value -inline uint32_t High32(uint64_t u) { return (u >> 32); } - -/// @brief Returns the lower 32-bits of an address -inline uint32_t PtrLow32(const void* p) { - return static_cast(reinterpret_cast(p)); -} - -/// @brief Returns the upper 32-bits of an address -inline uint32_t PtrHigh32(const void* p) { - uint32_t hi_32 = 0; -#ifdef HSA_LARGE_MODEL - hi_32 = static_cast(reinterpret_cast(p) >> 32); - static_assert(sizeof(void*) == 8, "HSA_LARGE_MODEL is not set properly here!"); -#else - static_assert(sizeof(void*) == 4, "HSA_LARGE_MODEL is not set properly here!"); -#endif - return hi_32; -} - -} // pm4_profile - -#endif // _CMDWRITER_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmds.h b/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmds.h deleted file mode 100644 index 2db962c03b..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmds.h +++ /dev/null @@ -1,161 +0,0 @@ -#ifndef _GFX8_CMDS_H_ -#define _GFX8_CMDS_H_ - -#include "gfxip/gfx8/si_ci_vi_merged_enum.h" -#include "gfxip/gfx8/si_ci_vi_merged_mask.h" -#include "gfxip/gfx8/si_ci_vi_merged_offset.h" -#include "gfxip/gfx8/si_ci_vi_merged_registers.h" -#include "gfxip/gfx8/si_ci_vi_merged_typedef.h" -#include "gfxip/gfx8/si_ci_vi_merged_pm4_it_opcodes.h" -#include "gfxip/gfx8/si_pm4defs.h" - -namespace pm4_profile { - -namespace gfx8 { - -// Desc: Defines the Gpu command to dispatch a kernel. It embeds -// various Gpu hardware specific data structures for initialization -// and configuration before a dispatch begins to run -struct DispatchTemplate { - // Desc: Structure used to initialize the group dimensions - // of a kernel dispatch and if performance counters are enabled - struct DispatchDimensionRegs { - PM4CMDSETDATA cmd_set_data; - regCOMPUTE_START_X compute_start_x; - regCOMPUTE_START_Y compute_start_y; - regCOMPUTE_START_Z compute_start_z; - regCOMPUTE_NUM_THREAD_X compute_num_thread_x; - regCOMPUTE_NUM_THREAD_Y compute_num_thread_y; - regCOMPUTE_NUM_THREAD_Z compute_num_thread_z; - regCOMPUTE_PIPELINESTAT_ENABLE__CI__VI compute_pipelinestat_enable; - } dimension_regs; - - // Desc: Structure used to initialize kernel Isa, trap - // handler, trap handler buffer, number of SGPR and VGPR - // registers needed, amount of Group memory and LDS needed, - // Rounding mode for Floating point numbers, etc. - struct DispatchProgramRegs { - PM4CMDSETDATA cmd_set_data; - regCOMPUTE_PGM_LO compute_pgm_lo; - regCOMPUTE_PGM_HI compute_pgm_hi; - regCOMPUTE_TBA_LO compute_tba_lo; - regCOMPUTE_TBA_HI compute_tba_hi; - regCOMPUTE_TMA_LO compute_tma_lo; - regCOMPUTE_TMA_HI compute_tma_hi; - regCOMPUTE_PGM_RSRC1 compute_pgm_rsrc1; - regCOMPUTE_PGM_RSRC2 compute_pgm_rsrc2; - } program_regs; - - // Desc: Structure used to initialize parameters related to - // thread management i.e. number of waves to issue and number - // of Compute Units to use - struct DispatchResourceRegs { - PM4CMDSETDATA cmd_set_data; - regCOMPUTE_RESOURCE_LIMITS compute_resource_limits; - regCOMPUTE_STATIC_THREAD_MGMT_SE0 compute_static_thread_mgmt_se0; - regCOMPUTE_STATIC_THREAD_MGMT_SE1 compute_static_thread_mgmt_se1; - regCOMPUTE_TMPRING_SIZE compute_tmpring_size; - regCOMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI compute_static_thread_mgmt_se2; - regCOMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI compute_static_thread_mgmt_se3; - regCOMPUTE_RESTART_X__CI__VI compute_restart_x; - regCOMPUTE_RESTART_Y__CI__VI compute_restart_y; - regCOMPUTE_RESTART_Z__CI__VI compute_restart_z; - regCOMPUTE_THREAD_TRACE_ENABLE__CI__VI compute_thread_trace_enable; - } resource_regs; - - // Desc: Structure used to pass handles of the Aql dispatch - // packet, Aql queue, Kernel argument address block, Scratch - // buffer - struct DispatchComputeUserDataRegs { - PM4CMDSETDATA cmd_set_data; - uint32_t compute_user_data[16]; - } compute_user_data_regs; - - // Desc: Structure used to configure Cache flush policy - // and dimensions of total work size - PM4CMDDISPATCHDIRECT dispatch_direct; -}; - -// Desc: Structure used to issue a Gpu Barrier command -struct BarrierTemplate { - PM4CMDEVENTWRITE event_write; -}; - -// Desc: Structure used to configure the flushing -// of various caches - instruction, constants, L1 -// and L2 -struct AcquireMemTemplate { - PM4CMDACQUIREMEM acquire_mem; -}; - -// Desc: Structure used to reference another Gpu command -// indirectly. Generally used to reference a list of Gpu -// commands (dispatch cmds) indirectly -struct LaunchTemplate { - PM4CMDINDIRECTBUFFER indirect_buffer; -}; - -// Desc: Structure used to determine the end of -// a kernel including cache flushes and writing to -// a user configurable memory location -struct EndofKernelNotifyTemplate { - PM4CMDRELEASEMEM release_mem; -}; - -// Desc: Strucuture used to perform various atomic -// operations - add, subtract, increment, etc -struct AtomicTemplate { - PM4CMDATOMIC atomic; -}; - -// Desc: Structure used to conditionalize the execution -// of a Gpu command stream -struct ConditionalExecuteTemplate { - PM4CMDCONDEXEC_CI conditional; -}; - -// Desc: PM4 command to write a 32-bit value into a memory -// location accessible to Gpu -struct WriteDataTemplate { - PM4CMDWRITEDATA write_data; - uint32_t write_data_value; -}; - -// Desc: PM4 command to write a 64-bit value into a memory -// location accessible to Gpu -struct WriteData64Template { - PM4CMDWRITEDATA write_data; - uint64_t write_data_value; -}; - -// Desc: PM4 command to wait for a certain event before proceeding -// to process another command on the queue -struct WaitRegMemTemplate { - PM4CMDWAITREGMEM wait_reg_mem; -}; - -// Desc: Initializer for commands that set shader registers -template void GenerateSetShRegHeader(T* pm4, uint32_t reg_addr) { - pm4->cmd_set_data.header.u32All = - PM4_TYPE_3_HDR(IT_SET_SH_REG, sizeof(T) / sizeof(uint32_t), ShaderCompute, 0); - pm4->cmd_set_data.regOffset = reg_addr - PERSISTENT_SPACE_START; -} - -// Desc: Initializer for various Gpu command headers -template void GenerateCmdHeader(T* pm4, IT_OpCodeType op_code) { - pm4->header.u32All = PM4_TYPE_3_HDR(op_code, sizeof(T) / sizeof(uint32_t), ShaderCompute, 0); -} - -// Desc: Initializer for commands that set configuration registers -template void GenerateSetConfigRegHeader(T* pm4, uint32_t reg_addr) { - pm4->cmd_set_data.header.u32All = - PM4_TYPE_3_HDR(IT_SET_CONFIG_REG, sizeof(T) / sizeof(uint32_t), ShaderCompute, 0); - pm4->cmd_set_data.regOffset = reg_addr - CONFIG_SPACE_START; -} - - -} // gfx8 - -} // pm4_profile - -#endif // _GFX8_CMDS_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmdwriter.cpp b/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmdwriter.cpp deleted file mode 100644 index b7b066801d..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmdwriter.cpp +++ /dev/null @@ -1,765 +0,0 @@ -#include -#include -#include -#include -#include - -#include "gfx8_cmdwriter.h" -#include "gfxip/gfx8/gfx8_utils.h" - -// RELEASE MEM DST SEL Definitions -#define RELEASE_MEM_DST_SEL_MEMORY_CONTROLLER 0 -#define RELEASE_MEM_DST_SEL_TC_L2 1 - -// RELEASE MEM CACHE POLICY Definitions -#define RELEASE_MEM_CACHE_POLICY_LRU 0 -#define RELEASE_MEM_CACHE_POLICY_STREAM 1 -#define RELEASE_MEM_CACHE_POLICY_BYPASS 2 - -template static void PrintPm4Packet(const T& command, const char* name) { -#if !defined(NDEBUG) - uint32_t* cmd = (uint32_t*)&command; - uint32_t size = sizeof(command) / sizeof(uint32_t); - std::ostringstream oss; - oss << "'" << name << "' size(" << std::dec << size << ")"; - std::clog << std::setw(40) << std::left << oss.str() << ":"; - for (uint32_t idx = 0; idx < size; idx++) { - std::clog << " " << std::hex << std::setw(8) << std::setfill('0') << cmd[idx]; - } - std::clog << std::setfill(' ') << std::endl; -#endif -} - -#define APPEND_COMMAND_WRAPPER(cmdbuf, command) \ - PrintPm4Packet(command, __FUNCTION__); \ - AppendCommand(cmdbuf, command); - -namespace pm4_profile { -namespace gfx8 { - -template void Gfx8CmdWriter::AppendCommand(CmdBuf* cmdbuf, const T& command) { - cmdbuf->AppendCommand(&command, sizeof(command)); -} - -void Gfx8CmdWriter::InitializeAtomicTemplate() { - memset(&atomic_template_.atomic, 0, sizeof(atomic_template_)); - GenerateCmdHeader(&atomic_template_.atomic, IT_ATOMIC_MEM__CI); - - if (atc_support_) { - const uint32_t kAtcShift = 24; - atomic_template_.atomic.ordinal2 |= 1 << kAtcShift; - } -} - -void Gfx8CmdWriter::InitializeConditionalTemplate() { - memset(&conditional_template_.conditional, 0, sizeof(conditional_template_)); - gfx8::GenerateCmdHeader(&conditional_template_.conditional, IT_COND_EXEC); - - if (atc_support_) { - const uint32_t kAtcShift = 24; - conditional_template_.conditional.ordinal4 |= 1 << kAtcShift; - } -} - -void Gfx8CmdWriter::InitializeLaunchTemplate() { - memset(&launch_template_, 0, sizeof(launch_template_)); - - GenerateCmdHeader(&launch_template_.indirect_buffer, IT_INDIRECT_BUFFER); - launch_template_.indirect_buffer.CI.valid = true; -} - -void Gfx8CmdWriter::InitializeWriteDataTemplate() { - // Set the header of write data command - memset(&write_data_template_, 0, sizeof(write_data_template_)); - - // Initialize the header of command packet - PM4CMDWRITEDATA* command = &(write_data_template_.write_data); - uint32_t cmd_size = sizeof(write_data_template_) / sizeof(uint32_t); - command->ordinal1 = PM4_TYPE_3_HDR(IT_WRITE_DATA, cmd_size, ShaderCompute, 0); - - // Set the ATC bit of command template - specifies if the address - // belongs to system memory - write_data_template_.write_data.atc__CI = (atc_support_) ? 1 : 0; - - // Set the bit to confirm the write operation and cache policy - write_data_template_.write_data.wrConfirm = 1; - write_data_template_.write_data.cachePolicy__CI = WRITE_DATA_CACHE_POLICY_BYPASS; - - // Specify the module that will execute the write data command - write_data_template_.write_data.engineSel = WRITE_DATA_ENGINE_ME; - - // Specify the class to which the write destination belongs - write_data_template_.write_data.dstSel = WRITE_DATA_DST_SEL_MEMORY_ASYNC; -} - -void Gfx8CmdWriter::InitializeWriteData64Template() { - // Set the header of write data command - memset(&write_data64_template_, 0, sizeof(write_data64_template_)); - - // Initialize the header of command packet - PM4CMDWRITEDATA* command = &(write_data64_template_.write_data); - uint32_t cmd_size = sizeof(write_data64_template_) / sizeof(uint32_t); - command->ordinal1 = PM4_TYPE_3_HDR(IT_WRITE_DATA, cmd_size, ShaderCompute, 0); - - // Set the ATC bit of command template - specifies if the address - // belongs to system memory - write_data64_template_.write_data.atc__CI = (atc_support_) ? 1 : 0; - - // Set the bit to confirm the write operation and cache policy - write_data64_template_.write_data.wrConfirm = 1; - write_data64_template_.write_data.cachePolicy__CI = WRITE_DATA_CACHE_POLICY_BYPASS; - - // Specify the module that will execute the write data command - write_data64_template_.write_data.engineSel = WRITE_DATA_ENGINE_ME; - - // Specify the class to which the write destination belongs - // write_data64_template_.write_data.dstSel = WRITE_DATA_DST_SEL_TCL2; - // TODO: For Hawaii bring up only. - write_data64_template_.write_data.dstSel = WRITE_DATA_DST_SEL_MEMORY_ASYNC; -} - -void Gfx8CmdWriter::InitializeBarrierTemplate() { - memset(&pending_dispatch_template_, 0, sizeof(pending_dispatch_template_)); - - gfx8::GenerateCmdHeader(&pending_dispatch_template_.event_write, IT_EVENT_WRITE); - pending_dispatch_template_.event_write.eventType = CS_PARTIAL_FLUSH; - pending_dispatch_template_.event_write.eventIndex = EventTypeToIndexTable[CS_PARTIAL_FLUSH]; -} - -void Gfx8CmdWriter::InitializeAcquireMemTemplate() { - memset(&invalidate_cache_template_, 0, sizeof(invalidate_cache_template_)); - - gfx8::GenerateCmdHeader(&invalidate_cache_template_.acquire_mem, IT_ACQUIRE_MEM__CI__VI); - invalidate_cache_template_.acquire_mem.cpCoherBase.u32All = 0x00; - invalidate_cache_template_.acquire_mem.cpCoherBaseHi.u32All = 0x00; - invalidate_cache_template_.acquire_mem.cpCoherSize.u32All = 0xFFFFFFFF; - invalidate_cache_template_.acquire_mem.cpCoherSizeHi.u32All = 0xFF; - invalidate_cache_template_.acquire_mem.pollInterval = 0; -} - -void Gfx8CmdWriter::InitializeWaitRegMemTemplate() { - memset(&wait_reg_mem_template_, 0, sizeof(wait_reg_mem_template_)); - - gfx8::GenerateCmdHeader(&wait_reg_mem_template_.wait_reg_mem, IT_WAIT_REG_MEM); - wait_reg_mem_template_.wait_reg_mem.atc__CI = (atc_support_) ? 1 : 0; - wait_reg_mem_template_.wait_reg_mem.cachePolicy__CI = 2; // bypass - wait_reg_mem_template_.wait_reg_mem.pollInterval = 0; - wait_reg_mem_template_.wait_reg_mem.engine = WAIT_REG_MEM_ENGINE_ME; -} - -Gfx8CmdWriter::Gfx8CmdWriter(bool atc_support, bool pcie_atomic_support) { - // Initialize various state variables related to - // atomic operations and atc support - pcie_atomic_support_ = pcie_atomic_support; - atc_support_ = atc_support; - - InitializeLaunchTemplate(); - InitializeAtomicTemplate(); - InitializeConditionalTemplate(); - InitializeWriteDataTemplate(); - InitializeWriteData64Template(); - InitializeBarrierTemplate(); - InitializeAcquireMemTemplate(); - InitializeWaitRegMemTemplate(); -} - -void Gfx8CmdWriter::BuildWaitRegMemCommand(CmdBuf* cmdbuf, bool mem_space, uint64_t wait_addr, - bool func_eq, uint32_t mask_val, uint32_t wait_val) { - gfx8::WaitRegMemTemplate wait_cmd = wait_reg_mem_template_; - - // Apply the space to which addr belongs - if (mem_space) { - wait_cmd.wait_reg_mem.memSpace = WAIT_REG_MEM_SPACE_MEMORY; - } else { - wait_cmd.wait_reg_mem.memSpace = WAIT_REG_MEM_SPACE_REGISTER; - } - - // Apply the function - equal / not equal desired by user - if (func_eq) { - wait_cmd.wait_reg_mem.function = WAIT_REG_MEM_FUNC_EQUAL; - } else { - wait_cmd.wait_reg_mem.function = WAIT_REG_MEM_FUNC_NOT_EQUAL; - } - - // Apply the mask on value at address/register - wait_cmd.wait_reg_mem.mask = mask_val; - - // Value to use in applying equal / not equal function - wait_cmd.wait_reg_mem.reference = wait_val; - - // Update upper 32 bit address if addr is not a register - if (mem_space) { - assert(!(wait_addr & 0x3) && "WaitRegMem address must be 4 byte aligned"); - } - wait_cmd.wait_reg_mem.pollAddressLo = Low32(wait_addr); - if (mem_space) { - wait_cmd.wait_reg_mem.pollAddressHi = High32(wait_addr); - } - - APPEND_COMMAND_WRAPPER(cmdbuf, wait_cmd); -} - -void Gfx8CmdWriter::BuildUpdateHostAddress(CmdBuf* cmdbuf, uint64_t* addr, int64_t value) { - // If Atomics are supported, use it - if (pcie_atomic_support_) { - BuildAtomicPacket64(cmdbuf, CommandWriter::AtomicType::kAtomicSwap, (volatile uint64_t*)addr, - value); - return; - } - - BuildWriteData64Command(cmdbuf, addr, value); - return; -} - -void Gfx8CmdWriter::BuildIndirectBufferCmd(CmdBuf* cmdbuf, const void* cmd_addr, - std::size_t cmd_size) { - gfx8::LaunchTemplate launch = launch_template_; - - launch.indirect_buffer.ibBaseLo = PtrLow32(cmd_addr); - launch.indirect_buffer.ibBaseHi = PtrHigh32(cmd_addr); - launch.indirect_buffer.CI.ibSize = cmd_size / sizeof(uint32_t); - - APPEND_COMMAND_WRAPPER(cmdbuf, launch); -} - -void Gfx8CmdWriter::BuildBOPNotifyCmd(CmdBuf* cmdbuf, const void* write_addr, uint32_t write_val, - bool interrupt) { - // Initialize the command including its header - gfx8::EndofKernelNotifyTemplate eopCmd; - memset(&eopCmd, 0, sizeof(eopCmd)); - gfx8::GenerateCmdHeader(&eopCmd.release_mem, IT_RELEASE_MEM__CI__VI); - - // Program CP to wait until following event is notified by SPI - eopCmd.release_mem.eventType = BOTTOM_OF_PIPE_TS; - eopCmd.release_mem.eventIndex = EventTypeToIndexTable[BOTTOM_OF_PIPE_TS]; - - // Program CP to perform various cache operations - // which complete before Write operation commences - eopCmd.release_mem.atc = atc_support_; - eopCmd.release_mem.l2Invlidate = true; - eopCmd.release_mem.l2WriteBack = true; - - // Set destination as Memory with Write bypassing Cache - eopCmd.release_mem.cachePolicy = RELEASE_MEM_CACHE_POLICY_BYPASS; - eopCmd.release_mem.dstSel = RELEASE_MEM_DST_SEL_MEMORY_CONTROLLER; - - // Program CP to write user specified value to user specified address - eopCmd.release_mem.ordinal4 = Low32(uint64_t(write_addr)); - eopCmd.release_mem.addrHi = High32(uint64_t(write_addr)); - eopCmd.release_mem.dataLo = Low32(write_val); - eopCmd.release_mem.dataHi = High32(write_val); - eopCmd.release_mem.dataSel = EVENTWRITEEOP_DATA_SEL_SEND_DATA32; - - // Determine if host will poll or wait for interrupt - eopCmd.release_mem.intSel = - (interrupt == false) ? EVENTWRITEEOP_INT_SEL_NONE : EVENTWRITEEOP_INT_SEL_SEND_INT_ON_CONFIRM; - - APPEND_COMMAND_WRAPPER(cmdbuf, eopCmd); -} - - -void Gfx8CmdWriter::BuildBarrierFenceCommands(CmdBuf* cmdbuf) { - gfx8::AcquireMemTemplate invalidate_src_caches = invalidate_cache_template_; - - // wbINVL2 by default writes-back and invalidates both L1 and L2 - invalidate_src_caches.acquire_mem.coherCntl = - CP_COHER_CNTL__TC_ACTION_ENA_MASK | CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK__CI__VI; - - APPEND_COMMAND_WRAPPER(cmdbuf, invalidate_src_caches); -} - -// PM4 packet for profilers -#define PM4_PACKET3 (0xC0000000) -#define PM4_PACKET3_CMD_SHIFT 8 -#define PM4_PACKET3_COUNT_SHIFT 16 - -#define PACKET3(cmd, count) \ - (PM4_PACKET3 | (((count)-1) << PM4_PACKET3_COUNT_SHIFT) | ((cmd) << PM4_PACKET3_CMD_SHIFT)) - -// Structure to store the event PM4 packet -typedef struct WriteRegPacket_ { uint32_t item[3]; } WriteRegPacket; - -typedef struct WriteEventPacket_ { uint32_t item[7]; } WriteEventPacket; - -void Gfx8CmdWriter::BuildWriteEventPacket(CmdBuf* cmdbuf, uint32_t event) { - PM4CMDEVENTWRITE cp_event_initiator; - cp_event_initiator.ordinal1 = PACKET3(IT_EVENT_WRITE, 1); - cp_event_initiator.ordinal2 = 0; - - VGT_EVENT_TYPE eventType = Reserved_0x00; - switch (event) { - case kPerfCntrsStart: - eventType = PERFCOUNTER_START; - break; - case kPerfCntrsStop: - eventType = PERFCOUNTER_STOP; - break; - case kPerfCntrsSample: - eventType = PERFCOUNTER_SAMPLE; - break; - default: - assert(false && "Illegal VGT Event Id"); - } - - cp_event_initiator.eventType = eventType; - cp_event_initiator.eventIndex = EventTypeToIndexTable[eventType]; - - APPEND_COMMAND_WRAPPER(cmdbuf, cp_event_initiator); - - return; -} - -void Gfx8CmdWriter::BuildWriteUnshadowRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - WriteRegPacket packet; - packet.item[0] = (PM4_TYPE_3_HDR(IT_SET_UCONFIG_REG__CI__VI, 1 + PM4_CMD_SET_CONFIG_REG_DWORDS, - ShaderGraphics, 0)); - packet.item[1] = (addr - UCONFIG_SPACE_START__CI__VI); - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); - - return; -} - -void Gfx8CmdWriter::BuildWriteUConfigRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - WriteRegPacket packet; - packet.item[0] = (PM4_TYPE_3_HDR(IT_SET_UCONFIG_REG__CI__VI, 1 + PM4_CMD_SET_CONFIG_REG_DWORDS, - ShaderCompute, 0)); - packet.item[1] = (addr - UCONFIG_SPACE_START__CI__VI); - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); - - return; -} - -void Gfx8CmdWriter::BuildWriteShRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - WriteRegPacket packet; - packet.item[0] = (PM4_TYPE_3_HDR(IT_SET_SH_REG, 1 + PM4_CMD_SET_SH_REG_DWORDS, ShaderCompute, 0)); - packet.item[1] = (addr - PERSISTENT_SPACE_START); - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); - - return; -} - -void Gfx8CmdWriter::BuildCopyDataPacket(CmdBuf* cmdbuf, uint32_t src_sel, uint32_t src_addr_lo, - uint32_t src_addr_hi, uint32_t* dst_addr, uint32_t size, - bool wait) { - PM4CMDCOPYDATA cmd_data; - memset(&cmd_data, 0, sizeof(PM4CMDCOPYDATA)); - - cmd_data.header.u32All = PACKET3(IT_COPY_DATA, 5); - - cmd_data.srcAtc__CI = atc_support_; - cmd_data.srcCachePolicy__CI = COPY_DATA_SRC_CACHE_POLICY_BYPASS; - cmd_data.srcSel = src_sel; - - cmd_data.dstAtc__CI = atc_support_; - cmd_data.dstSel = COPY_DATA_SEL_DST_ASYNC_MEMORY; - cmd_data.dstCachePolicy__CI = COPY_DATA_DST_CACHE_POLICY_BYPASS; - - uint32_t dst_addr_lo, dst_addr_hi; - - dst_addr_lo = PtrLow32(dst_addr); - dst_addr_hi = PtrHigh32(dst_addr); - - cmd_data.srcAddressLo = src_addr_lo; - cmd_data.srcAddressHi = src_addr_hi; - cmd_data.dstAddressLo = dst_addr_lo; - cmd_data.dstAddressHi = dst_addr_hi; - - cmd_data.countSel = size; - cmd_data.wrConfirm = wait; - cmd_data.engineSel = COPY_DATA_ENGINE_ME; - - APPEND_COMMAND_WRAPPER(cmdbuf, cmd_data); - - return; -} - -void Gfx8CmdWriter::BuildCacheFlushPacket(CmdBuf* cmdbuf) { - WriteEventPacket packet; - packet.item[0] = PACKET3(IT_ACQUIRE_MEM__CI__VI, 6); - packet.item[1] = 0x28C00000; - packet.item[2] = 0xFFFFFFFF; - packet.item[3] = 0; - packet.item[4] = 0; - packet.item[5] = 0; - packet.item[6] = 0x00000004; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); -} - -void Gfx8CmdWriter::BuildWriteWaitIdlePacket(CmdBuf* cmdbuf) { - BuildBarrierCommand(cmdbuf); - BuildCacheFlushPacket(cmdbuf); - return; -} - -// Will issue a VGT event including a cache flush later on -void Gfx8CmdWriter::BuildVgtEventPacket(CmdBuf* cmdbuf, uint32_t vgtEvent) { - PM4CMDEVENTWRITE cp_event_initiator; - - cp_event_initiator.ordinal1 = PACKET3(IT_EVENT_WRITE, 1); - cp_event_initiator.ordinal2 = 0; - - VGT_EVENT_TYPE eventType = Reserved_0x00; - switch (vgtEvent) { - case kPerfCntrsStart: - eventType = PERFCOUNTER_START; - break; - case kPerfCntrsStop: - eventType = PERFCOUNTER_STOP; - break; - case kPerfCntrsSample: - eventType = PERFCOUNTER_SAMPLE; - break; - case kThrdTraceStart: - eventType = THREAD_TRACE_START; - break; - case kThrdTraceStop: - eventType = THREAD_TRACE_STOP; - break; - case kThrdTraceFlush: - eventType = THREAD_TRACE_FLUSH; - break; - case kThrdTraceFinish: - eventType = THREAD_TRACE_FINISH; - break; - default: - assert(false && "Illegal VGT Event Id"); - } - - cp_event_initiator.eventType = eventType; - cp_event_initiator.eventIndex = EventTypeToIndexTable[eventType]; - - APPEND_COMMAND_WRAPPER(cmdbuf, cp_event_initiator); - - // Check If I should be issuing a cache flush operation as well - // test and remove it - BuildCacheFlushPacket(cmdbuf); - return; -} - -void Gfx8CmdWriter::BuildWriteRegisterPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - WriteRegPacket packet; - packet.item[0] = - (PM4_TYPE_3_HDR(IT_SET_CONFIG_REG, 1 + PM4_CMD_SET_CONFIG_REG_DWORDS, ShaderGraphics, 0)); - packet.item[1] = addr - CONFIG_SPACE_START; - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); - - return; -} - -void Gfx8CmdWriter::BuildWriteEventQueryPacket(CmdBuf* cmdbuf, uint32_t event, uint32_t* addr) { - PM4CMDEVENTWRITEQUERY cp_event_initiator; - cp_event_initiator.ordinal1 = PACKET3(IT_EVENT_WRITE, 3); - cp_event_initiator.ordinal2 = 0; - - // Update switch statements you want to support - VGT_EVENT_TYPE eventType = Reserved_0x00; - switch (event) { - default: - assert(false && "Illegal VGT Event Id"); - } - - cp_event_initiator.eventType = eventType; - cp_event_initiator.eventIndex = EventTypeToIndexTable[eventType]; - - // set the address - uint32_t addrLo = PtrLow32(addr); - uint32_t addrHi = PtrHigh32(addr); - ((addrLo & 0x7) != 0) ? assert(false) : assert(true); - - cp_event_initiator.ordinal3 = 0; - cp_event_initiator.ordinal4 = 0; - cp_event_initiator.addressLo = addrLo; - cp_event_initiator.addressHi = addrHi; - - APPEND_COMMAND_WRAPPER(cmdbuf, cp_event_initiator); - - return; -} - -void Gfx8CmdWriter::BuildBarrierCommand(CmdBuf* cmdBuf) { - APPEND_COMMAND_WRAPPER(cmdBuf, pending_dispatch_template_); -} - -void Gfx8CmdWriter::WriteUserData(uint32_t* dst_addr, uint32_t count, const void* src_addr) { - memcpy(dst_addr, src_addr, count * sizeof(uint32_t)); -} - - -void Gfx8CmdWriter::BuildAtomicPacket(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint32_t* addr, - uint32_t value, uint32_t compare) { - gfx8::AtomicTemplate atomic = atomic_template_; - - // make sure the destination adddress is aligned - uint32_t address_low = PtrLow32((void*)addr); - uint32_t address_high = PtrHigh32((void*)addr); - assert(!(address_low & 0x7) && "destination address must be 8 byte aligned"); - - atomic.atomic.addressLo = address_low; - atomic.atomic.addressHi = address_high; - - switch (atomic_op) { - case CommandWriter::kAtomicTypeIncrement: { - atomic.atomic.atomOp = TC_OP_ATOMIC_ADD_RTN_32; - atomic.atomic.srcDataLo = 1; - break; - } - case CommandWriter::kAtomicTypeDecrement: { - atomic.atomic.atomOp = TC_OP_ATOMIC_SUB_RTN_32; - atomic.atomic.srcDataLo = 1; - break; - } - case CommandWriter::kAtomicTypeCompareAndSwap: { - atomic.atomic.atomOp = TC_OP_ATOMIC_CMPSWAP_RTN_32; - atomic.atomic.srcDataLo = value; - atomic.atomic.cmpDataLo = compare; - break; - } - case CommandWriter::kAtomicTypeBlockingCompareAndSwap: { - atomic.atomic.atomOp = TC_OP_ATOMIC_CMPSWAP_RTN_32; - atomic.atomic.srcDataLo = value; - atomic.atomic.cmpDataLo = compare; - atomic.atomic.command = 1; - atomic.atomic.loopInterval = 128; - break; - } - case CommandWriter::kAtomicAdd: { - atomic.atomic.atomOp = TC_OP_ATOMIC_ADD_RTN_32; - atomic.atomic.srcDataLo = value; - break; - } - case CommandWriter::kAtomicSubtract: { - atomic.atomic.atomOp = TC_OP_ATOMIC_SUB_RTN_32; - atomic.atomic.srcDataLo = value; - break; - } - case CommandWriter::kAtomicSwap: { - atomic.atomic.atomOp = TC_OP_ATOMIC_SWAP_RTN_32; - atomic.atomic.srcDataLo = value; - break; - } - } - - APPEND_COMMAND_WRAPPER(cmdbuf, atomic); -} - -void Gfx8CmdWriter::BuildAtomicPacket64(CmdBuf* cmdbuf, AtomicType atomic_op, - volatile uint64_t* addr, uint64_t value, uint64_t compare) { - AtomicTemplate atomic = atomic_template_; - - // make sure the destination adddress is aligned - uint32_t address_low = PtrLow32((void*)addr); - uint32_t address_high = PtrHigh32((void*)addr); - assert(!(address_low & 0x7) && "destination address must be 8 byte aligned"); - - atomic.atomic.addressLo = address_low; - atomic.atomic.addressHi = address_high; - - atomic.atomic.atc = (atc_support_) ? 1 : 0; - atomic.atomic.cachePolicy = 2; - - switch (atomic_op) { - case CommandWriter::kAtomicTypeIncrement: { - atomic.atomic.atomOp = TC_OP_ATOMIC_ADD_RTN_64; - atomic.atomic.srcDataLo = 1; - break; - } - case CommandWriter::kAtomicTypeDecrement: { - atomic.atomic.atomOp = TC_OP_ATOMIC_SUB_RTN_64; - atomic.atomic.srcDataLo = 1; - break; - } - case CommandWriter::kAtomicTypeCompareAndSwap: { - atomic.atomic.atomOp = TC_OP_ATOMIC_CMPSWAP_RTN_64; - atomic.atomic.srcDataLo = Low32(value); - atomic.atomic.srcDataHi = High32(value); - atomic.atomic.cmpDataLo = Low32(compare); - atomic.atomic.cmpDataHi = High32(compare); - break; - } - case CommandWriter::kAtomicTypeBlockingCompareAndSwap: { - atomic.atomic.atomOp = TC_OP_ATOMIC_CMPSWAP_RTN_64; - atomic.atomic.srcDataLo = Low32(value); - atomic.atomic.srcDataHi = High32(value); - atomic.atomic.cmpDataLo = Low32(compare); - atomic.atomic.cmpDataHi = High32(compare); - atomic.atomic.command = 1; - atomic.atomic.loopInterval = 128; - break; - } - case CommandWriter::kAtomicAdd: { - atomic.atomic.atomOp = TC_OP_ATOMIC_ADD_RTN_64; - atomic.atomic.srcDataLo = Low32(value); - atomic.atomic.srcDataHi = High32(value); - break; - } - case CommandWriter::kAtomicSubtract: { - atomic.atomic.atomOp = TC_OP_ATOMIC_SUB_RTN_64; - atomic.atomic.srcDataLo = Low32(value); - atomic.atomic.srcDataHi = High32(value); - break; - } - case CommandWriter::kAtomicSwap: { - atomic.atomic.atomOp = TC_OP_ATOMIC_SWAP_RTN_64; - atomic.atomic.srcDataLo = Low32(value); - atomic.atomic.srcDataHi = High32(value); - break; - } - } - - APPEND_COMMAND_WRAPPER(cmdbuf, atomic); -} - -size_t Gfx8CmdWriter::SizeOfAtomicPacket() const { - return sizeof(AtomicTemplate) / sizeof(uint32_t); -} - -void Gfx8CmdWriter::BuildConditionalExecute(CmdBuf* cmdbuf, uint32_t* signal, uint16_t count) { - ConditionalExecuteTemplate conditional = conditional_template_; - - uint32_t address_low = PtrLow32(signal); - uint32_t address_high = PtrHigh32(signal); - assert(!(address_low & 0x7) && "destination address must be 8 byte aligned"); - - conditional.conditional.boolAddrLo = address_low; - conditional.conditional.boolAddrHi = address_high; - conditional.conditional.execCount = count; - - APPEND_COMMAND_WRAPPER(cmdbuf, conditional); -} - -void Gfx8CmdWriter::BuildWriteDataCommand(CmdBuf* cmdbuf, uint32_t* write_addr, - uint32_t write_value) { - // Copy the initialize command packet - gfx8::WriteDataTemplate command = write_data_template_; - - // Encode the user specified value to write - command.write_data_value = write_value; - - // Encode the user specified address to write to - command.write_data.dstAddrLo = PtrLow32(write_addr); - command.write_data.dstAddrHi = PtrHigh32(write_addr); - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, command); -} - -void Gfx8CmdWriter::BuildWriteData64Command(CmdBuf* cmdbuf, uint64_t* write_addr, - uint64_t write_value) { - // Copy the initialize command packet - gfx8::WriteData64Template command = write_data64_template_; - - // Encode the user specified value to write - command.write_data_value = write_value; - - // Encode the user specified address to write to - command.write_data.dstAddrLo = PtrLow32(write_addr); - command.write_data.dstAddrHi = PtrHigh32(write_addr); - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, command); -} - -void Gfx8CmdWriter::BuildFlushCacheCmd(CmdBuf* cmdbuf, FlushCacheOptions* options, - uint32_t* writeAddr, uint32_t writeVal) { - PM4CMDACQUIREMEM flushCmd; - memset(&flushCmd, 0, sizeof(flushCmd)); - - // Verify write back address is valid. Note that this address is NOT - // used on CI. But to have a same interface as that on SI, we keep - // the address argument in this function. Thus, this check always pass - // no matter the address is NULL or not. - (writeAddr == NULL) ? assert(true) : assert(true); - - // Initialize the command header - gfx8::GenerateCmdHeader(&flushCmd, IT_ACQUIRE_MEM__CI__VI); - - // Specify the base address of memory being synchronized. - // The starting address is indicated as follows: bits [0-48]. - flushCmd.cpCoherBase.u32All = 0; - flushCmd.cpCoherBaseHi.u32All = 0; - - // Specify the size of memory being synchronized. It is indicated - // as follows: - // COHER_SIZE_256B_MASK = 0xffffffffL - // COHER_SIZE_HI_256B_MASK__CI__VI = 0x000000ffL - flushCmd.cpCoherSize.u32All = CP_COHER_SIZE__COHER_SIZE_256B_MASK; - flushCmd.cpCoherSizeHi.u32All = CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK__CI__VI; - - // Periodicity of polling - interval to wait from the time - // of unsuccessful polling result is returned and a new - // poll is issued - flushCmd.pollInterval = 0x04; - - // Program Coherence Control Register. Initialize L2 Cache flush - // for Non-Coherent memory blocks - uint32_t coher_cntl = 0; - - coher_cntl |= (options->l1) ? CP_COHER_CNTL__TCL1_ACTION_ENA_MASK : 0; - coher_cntl |= (options->l2) - ? (CP_COHER_CNTL__TC_ACTION_ENA_MASK | CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK__CI__VI) - : 0; - coher_cntl |= (options->icache) ? CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK : 0; - coher_cntl |= (options->kcache) ? CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK : 0; - flushCmd.coherCntl = coher_cntl; - - // Copy AcquireMem command buffer stream - APPEND_COMMAND_WRAPPER(cmdbuf, flushCmd); - return; -} - -void Gfx8CmdWriter::BuildDmaDataPacket(CmdBuf* cmdbuf, uint32_t* srcAddr, uint32_t* dstAddr, - uint32_t copySize, bool waitForConfirm) { - PM4CMDDMADATA cmdDmaData; - memset(&cmdDmaData, 0, sizeof(PM4CMDDMADATA)); - cmdDmaData.header.u32All = - (PM4_TYPE_3_HDR(IT_DMA_DATA__CI__VI, PM4_CMD_DMA_DATA_DWORDS, ShaderCompute, 0)); - - // Id of Micro Engine - cmdDmaData.engine = 0; - - // Specify attributes of source buffer such as its - // location, ATC property, Cache policy and Volatile - // A value of 1 for cache policy means to Stream - cmdDmaData.srcSel = 0; - cmdDmaData.srcATC = atc_support_; - cmdDmaData.srcCachePolicy = 1; - cmdDmaData.srcVolatile = 0; - - // Specify attributes of destination buffer such as - // its location, ATC property, Cache policy and Volatile - // A value of 1 for cache policy means to Stream - cmdDmaData.dstSel = 0; - cmdDmaData.dstATC = atc_support_; - cmdDmaData.dstCachePolicy = 1; - cmdDmaData.dstVolatile = 0; - - // Specify the source and destination addr - cmdDmaData.srcAddrHi = PtrHigh32(srcAddr); - cmdDmaData.srcAddrLoOrData = PtrLow32(srcAddr); - cmdDmaData.dstAddrLo = PtrLow32(dstAddr); - cmdDmaData.dstAddrHi = PtrHigh32(dstAddr); - - // Number of bytes to copy. The command restricts - // the size to be (2 MB - 1) - 21 Bits - assert(copySize < 0x1FFFFF); - cmdDmaData.command.byteCount = copySize; - - // Indicate that DMA Cmd should wait if its source - // is the destination of a previous DMA Cmd - cmdDmaData.command.rawWait = waitForConfirm; - - APPEND_COMMAND_WRAPPER(cmdbuf, cmdDmaData); - return; -} - -} // gfx8 -} // pm4_profile diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmdwriter.h b/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmdwriter.h deleted file mode 100644 index 9e14c1ab29..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx8_cmdwriter.h +++ /dev/null @@ -1,201 +0,0 @@ -#ifndef _GFX8_CMDWRITER_H_ -#define _GFX8_CMDWRITER_H_ - -#include "cmdwriter.h" -#include "gfx8_cmds.h" - -namespace pm4_profile { - -namespace gfx8 { - -/// @brief class Gfx8CmdWriter implements the virtual class CommandWriter -/// for Sea Islands (CI) and VI chipset -class Gfx8CmdWriter : public CommandWriter { - public: - Gfx8CmdWriter(bool atc_support, bool pcie_atomic_support); - - /// @brief Dword specifying NOOP command for SI/CI/VI chipsets. The macro - /// populates the NOOP command which is 32-bits wide. The second parameter, - /// the COUNT field of NOOP command, specifies the number of Dwords to skip. - /// To skip ZERO Dwords the value should be set to 0x3FFF. Since the macro - /// decrements the second parameter by TWO, an artifact of its definition, - /// the value is incremented by TWO to 0x4001 (0x3FFF + 2). - /// - inline uint32_t GetNoOpCmd() { - static const uint32_t nopCmd = PM4_TYPE_3_HDR(IT_NOP, 0x4001, ShaderCompute, 0); - return nopCmd; - } - - void BuildBarrierCommand(CmdBuf* cmdBuf); - - void BuildIndirectBufferCmd(CmdBuf* cmdbuf, const void* cmd_addr, std::size_t cmd_size); - - void BuildBOPNotifyCmd(CmdBuf* cmdbuf, const void* write_addr, uint32_t write_val, - bool interrupt); - - void BuildBarrierFenceCommands(CmdBuf* cmdbuf); - - void BuildWriteEventPacket(CmdBuf* cmdbuf, uint32_t event); - - void BuildWaitRegMemCommand(CmdBuf* cmdbuf, bool mem_space, uint64_t wait_addr, bool func_eq, - uint32_t mask_val, uint32_t wait_val); - - void BuildWriteUnshadowRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - /// @brief Build CP command to program a Gpu register - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// @param addr Register to be programmed - /// @param value Value to write into register - /// - /// @return void - void BuildWriteUConfigRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - void BuildWriteShRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - void BuildCopyDataPacket(CmdBuf* cmdbuf, uint32_t src_sel, uint32_t src_addr_lo, - uint32_t src_addr_hi, uint32_t* dst_addr, uint32_t size, bool wait); - - void BuildWriteWaitIdlePacket(CmdBuf* cmdbuf); - - // Will issue a VGT event including a cache flush later on - void BuildVgtEventPacket(CmdBuf* cmdbuf, uint32_t vgtEvent); - - void BuildWriteRegisterPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - void BuildWriteEventQueryPacket(CmdBuf* cmdbuf, uint32_t event, uint32_t* addr); - - void BuildAtomicPacket(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint32_t* addr, - uint32_t value, uint32_t compare); - - void BuildAtomicPacket64(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint64_t* addr, - uint64_t value = 0, uint64_t compare = 0); - - size_t SizeOfAtomicPacket() const; - - void BuildConditionalExecute(CmdBuf* cmdbuf, uint32_t* signal, uint16_t count); - - void BuildWriteDataCommand(CmdBuf* cmdbuf, uint32_t* write_addr, uint32_t write_value); - - void BuildWriteData64Command(CmdBuf* cmdbuf, uint64_t* write_addr, uint64_t write_value); - - void BuildCacheFlushPacket(CmdBuf* cmdbuf); - - /// Writes into input buffer Gpu commands to flush its cache. It is - /// necessary that the buffer provided for flush commands is large - /// enough to accommodate the full set of commands. It should be at - /// least 512 bytes. - /// - /// @param tsCmdBuf Buffer to write commands to. - /// @param writeAddr Registered address into which GPU should write - /// a user provided value upon executing the flush commands. - /// @param writeVal User provided value written by GPU at user provided - /// address, upon executing the flush commands. - /// - /// @return void - void BuildFlushCacheCmd(CmdBuf* cmdBuf, FlushCacheOptions* options, uint32_t* writeAddr, - uint32_t writeVal); - - /// Builds Gpu command to copy data from source to destination buffer - /// using DMA engine. - /// - /// @param cmdbuf Buffer updated with Gpu copy command - /// @param srcAddr Address of source buffer address - /// @param dstAddr Address of destination buffer address - /// @param copySize Size of data to copy in bytes - /// @param waitForCompletion if command should wait for copying to complete - void BuildDmaDataPacket(CmdBuf* cmdBuf, uint32_t* srcAddr, uint32_t* dstAddr, uint32_t copySize, - bool waitForCompletion); - - protected: - /// @brief Copies data from source buffer to destination buffer - /// - /// @param dst_addr Address of destination buffer data - /// - /// @count Size of data to copy in 32-bit words - /// - /// @param src_addr Address of buffer containing source data - /// - /// @return void - virtual void WriteUserData(uint32_t* dst_addr, uint32_t count, const void* src_addr); - - /// @brief Append an instance of Gpu command into input command buffer stream. - /// - /// @param cmdbuf CommandWriter object appended with anohter Gpu command - /// - /// @param cmd Gpu command to be appended into command buffer - /// - /// @return void - template void AppendCommand(CmdBuf* cmdbuf, const T& cmd); - - private: - /// @brief Initializes a Gpu command which can be used to - /// reference a Gpu command stream indirectly - void InitializeLaunchTemplate(); - - /// @brief Initializes a Gpu command to perform atomic operations - //// - void InitializeAtomicTemplate(); - - /// @brief Initializes a Gpu command to allow conditional execution - /// of a Gpu command stream - void InitializeConditionalTemplate(); - - /// @brief Initializes a Gpu command to let command processor - /// wait for some update before letting other commands to be - /// processed - void InitializeWaitRegMemTemplate(); - - /// @brief Initializes the template for Barrier command. - /// Applications can use Barrier command to ensure their - /// command is executed only after all other commands have - /// completed their execution. - void InitializeBarrierTemplate(); - - void BuildUpdateHostAddress(CmdBuf* cmdbuf, uint64_t* addr, int64_t value); - - /// @brief Initializes Acquire Memory command template. Users - /// can submit this command to invalidate Gpu caches - L1 and - /// or L2. - void InitializeAcquireMemTemplate(); - - /// @brief Initializes an instance of Write Data command - /// for use by an application - void InitializeWriteDataTemplate(); - void InitializeWriteData64Template(); - - /// @brief Instance of Gpu command to reference dispatch commands - LaunchTemplate launch_template_; - - /// @brief Instance of Gpu command to use in performing atomic operations - AtomicTemplate atomic_template_; - - /// @brief Instance of Gpu command to use in conditional execution - /// of a command stream - ConditionalExecuteTemplate conditional_template_; - - /// @brief Instance of Pm4 command WRITE_DATA - WriteDataTemplate write_data_template_; - WriteData64Template write_data64_template_; - - /// @brief Instance of Pm4 command EVENT_WRITE - BarrierTemplate pending_dispatch_template_; - - /// @brief Instance of Pm4 command ACQUIRE_MEM - AcquireMemTemplate invalidate_cache_template_; - - /// @brief Instance of Pm4 command WAIT_REG_MEM - WaitRegMemTemplate wait_reg_mem_template_; - - /// @brief ATC support. - bool atc_support_; - - /// @brief PCIe atomic support. - bool pcie_atomic_support_; -}; - -} // gfx8 - -} // pm4_profile - -#endif // _GFX8_CMDWRITER_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmds.h b/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmds.h deleted file mode 100644 index 5dac4f07d1..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmds.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef _GFX9_CMDS_H_ -#define _GFX9_CMDS_H_ - -#include "gfxip/gfx9/gfx9_utils.h" -#include "gfxip/gfx9/gfx9_enum.h" -#include "gfxip/gfx9/gfx9_mask.h" -#include "gfxip/gfx9/gfx9_offset.h" -#include "gfxip/gfx9/gfx9_typedef.h" -#include "gfxip/gfx9/gfx9_registers.h" -#include "gfxip/gfx9/gfx9_pm4_it_opcodes.h" -#include "gfxip/gfx9/f32_mec_pm4_packets_vg10.h" -#include "gfxip/gfx9/f32_pfp_pm4_packets_vg10.h" - -namespace pm4_profile { - -namespace gfx9 { - -/// @brief Initializer for commands that set shader registers -template void GenerateSetShRegHeader(T* pm4, uint32_t reg_addr) { - pm4->cmd_set_data.header.u32All = PM4_TYPE3_HDR(IT_SET_SH_REG, sizeof(T) / sizeof(uint32_t)); - pm4->cmd_set_data.bitfields2.reg_offset = reg_addr - PERSISTENT_SPACE_START; -} - -// @brief Initializer for various Gpu command headers -template void GenerateCmdHeader(T* pm4, IT_OpCodeType op_code) { - pm4->header.u32All = PM4_TYPE3_HDR(op_code, sizeof(T) / sizeof(uint32_t)); -} - -// @brief Initializer for commands that set configuration registers -template void GenerateSetConfigRegHeader(T* pm4, uint32_t reg_addr) { - pm4->cmd_set_data.header.u32All = PM4_TYPE3_HDR(IT_SET_CONFIG_REG, sizeof(T) / sizeof(uint32_t)); - pm4->cmd_set_data.bitfields2.reg_offset = reg_addr - CONFIG_SPACE_START; -} - -/// @brief Structure used to issue a Gpu Barrier command -struct BarrierTemplate { - PM4MEC_EVENT_WRITE event_write; -}; - -/// @brief Structure used to configure the flushing of -/// various caches - instruction, constants, L1 and L2 -struct AcquireMemTemplate { - PM4MEC_ACQUIRE_MEM acquire_mem; -}; - -/// @brief Structure used to reference another Gpu command -/// indirectly. Generally used to reference a list of Gpu -/// commands (dispatch cmds) indirectly -struct LaunchTemplate { - PM4MEC_INDIRECT_BUFFER indirect_buffer; -}; - -/// @brief Structure used to determine the end of -/// a kernel including cache flushes and writing to -/// a user configurable memory location -struct EndofKernelNotifyTemplate { - PM4MEC_RELEASE_MEM release_mem; -}; - -// Desc: Strucuture used to perform various atomic -// operations - add, subtract, increment, etc -struct AtomicTemplate { - PM4MEC_ATOMIC_MEM atomic; -}; - -/// @brief PM4 command to write a 32-bit value into a memory -/// location accessible to Gpu -struct WriteDataTemplate { - PM4MEC_WRITE_DATA write_data; - uint32_t write_data_value; -}; - -/// @brief PM4 command to write a 64-bit value into a memory -/// location accessible to Gpu -struct WriteData64Template { - PM4MEC_WRITE_DATA write_data; - uint64_t write_data_value; -}; - -/// @brief PM4 command to wait for a certain event before proceeding -/// to process another command on the queue -struct WaitRegMemTemplate { - PM4MEC_WAIT_REG_MEM wait_reg_mem; -}; - -} // gfx9 - -} // pm4_profile - -#endif // _GFX9_CMDS_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmdwriter.cpp b/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmdwriter.cpp deleted file mode 100644 index 3e0f93be55..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmdwriter.cpp +++ /dev/null @@ -1,743 +0,0 @@ -#include -#include -#include -#include -#include - -#include "gfx9_cmdwriter.h" - -template static void PrintPm4Packet(const T& command, const char* name) { -#if !defined(NDEBUG) - uint32_t* cmd = (uint32_t*)&command; - uint32_t size = sizeof(command) / sizeof(uint32_t); - std::ostringstream oss; - oss << "'" << name << "' size(" << std::dec << size << ")"; - std::clog << std::setw(40) << std::left << oss.str() << ":"; - for (uint32_t idx = 0; idx < size; idx++) { - std::clog << " " << std::hex << std::setw(8) << std::setfill('0') << cmd[idx]; - } - std::clog << std::setfill(' ') << std::endl; -#endif -} - -#define APPEND_COMMAND_WRAPPER(cmdbuf, command) \ - PrintPm4Packet(command, __FUNCTION__); \ - AppendCommand(cmdbuf, command); - -namespace pm4_profile { -namespace gfx9 { - -template void Gfx9CmdWriter::AppendCommand(CmdBuf* cmdbuf, const T& command) { - cmdbuf->AppendCommand(&command, sizeof(command)); -} - -void Gfx9CmdWriter::InitializeLaunchTemplate() { - memset(&launch_template_, 0, sizeof(launch_template_)); - GenerateCmdHeader(&launch_template_.indirect_buffer, IT_INDIRECT_BUFFER); -} - -void Gfx9CmdWriter::InitializeAtomicTemplate() { - memset(&atomic_template_.atomic, 0, sizeof(atomic_template_)); - GenerateCmdHeader(&atomic_template_.atomic, IT_ATOMIC_MEM); - - // Specify the micro engine and cache policies - PM4MEC_ATOMIC_MEM* atomicCmd = &atomic_template_.atomic; - atomicCmd->bitfields2.cache_policy = cache_policy__mec_atomic_mem__stream; -} - -void Gfx9CmdWriter::InitializeBarrierTemplate() { - memset(&pending_dispatch_template_, 0, sizeof(pending_dispatch_template_)); - GenerateCmdHeader(&pending_dispatch_template_.event_write, IT_EVENT_WRITE); - - MEC_EVENT_WRITE_event_index_enum index; - index = event_index__mec_event_write__cs_partial_flush; - pending_dispatch_template_.event_write.bitfields2.event_index = index; - pending_dispatch_template_.event_write.bitfields2.event_type = CS_PARTIAL_FLUSH; -} - -void Gfx9CmdWriter::InitializeAcquireMemTemplate() { - memset(&invalidate_cache_template_, 0, sizeof(invalidate_cache_template_)); - GenerateCmdHeader(&invalidate_cache_template_.acquire_mem, IT_ACQUIRE_MEM); - - // Specify the CP module which will process this packet - PM4MEC_ACQUIRE_MEM* acquire_mem = &invalidate_cache_template_.acquire_mem; - - // Specify the size of memory to invalidate. Size is - // specified in terms of 256 byte chunks. A coher_size - // of 0xFFFFFFFF actually specified 0xFFFFFFFF00 (40 bits) - // of memory. The field coher_size_hi specifies memory from - // bits 40-64 for a total of 256 TB. - acquire_mem->coher_size = 0xFFFFFFFF; - acquire_mem->bitfields4.coher_size_hi = 0xFFFFFF; - - // Specify the address of memory to invalidate. The - // address must be 256 byte aligned. - acquire_mem->coher_base_lo = 0x00; - acquire_mem->bitfields6.coher_base_hi = 0x00; - - // Specify the poll interval for determing if operation is complete - acquire_mem->bitfields7.poll_interval = 0x04; -} - -void Gfx9CmdWriter::InitializeWaitRegMemTemplate() { - memset(&wait_reg_mem_template_, 0, sizeof(wait_reg_mem_template_)); - GenerateCmdHeader(&wait_reg_mem_template_.wait_reg_mem, IT_WAIT_REG_MEM); - - PM4MEC_WAIT_REG_MEM* wait_reg_mem = &wait_reg_mem_template_.wait_reg_mem; - - wait_reg_mem->bitfields7.poll_interval = 0x04; - wait_reg_mem->bitfields2.operation = operation__mec_wait_reg_mem__wait_reg_mem; -} - -void Gfx9CmdWriter::InitializeWriteDataTemplate(PM4MEC_WRITE_DATA* write_data, bool bit32) { - // Initialize the header of command packet by adjusting the - // size of payload - one 32bit DWord or two 32bit DWords - uint32_t cmd_size = (bit32) ? 1 : 2; - memset(write_data, 0, sizeof(PM4MEC_WRITE_DATA)); - cmd_size = cmd_size + (sizeof(PM4MEC_WRITE_DATA) / sizeof(uint32_t)); - write_data->ordinal1 = PM4_TYPE3_HDR(IT_WRITE_DATA, cmd_size); - - // Set the bit to confirm the write operation and cache policy - write_data->bitfields2.wr_confirm = wr_confirm__mec_write_data__wait_for_write_confirmation; - write_data->bitfields2.cache_policy = cache_policy__mec_write_data__stream; - - // Specify the command to increment address if writing more than one DWord - write_data->bitfields2.addr_incr = addr_incr__mec_write_data__increment_address; - - // Specify the class to which the write destination belongs - write_data->bitfields2.dst_sel = dst_sel__mec_write_data__memory; -} - -void Gfx9CmdWriter::InitializeWriteDataTemplate() { - InitializeWriteDataTemplate(&write_data_template_.write_data, true); -} - -void Gfx9CmdWriter::InitializeWriteData64Template() { - InitializeWriteDataTemplate(&write_data64_template_.write_data, false); -} - -void Gfx9CmdWriter::InitializeConditionalTemplate() { - /* - memset(&conditional_template_.conditional, 0, sizeof(conditional_template_)); - GenerateCmdHeader(&conditional_template_.conditional, IT_COND_EXEC); - - if (atc_support_) { - const uint32_t kAtcShift = 24; - conditional_template_.conditional.ordinal4 |= 1 << kAtcShift; - } - */ -} - -void Gfx9CmdWriter::InitializeEndOfKernelNotifyTemplate() { - memset(¬ify_template_, 0, sizeof(notify_template_)); - GenerateCmdHeader(¬ify_template_.release_mem, IT_RELEASE_MEM); - - // Set the event type to be bottom of pipe and cache policy - PM4MEC_RELEASE_MEM* rel_mem; - rel_mem = ¬ify_template_.release_mem; - rel_mem->bitfields2.event_type = BOTTOM_OF_PIPE_TS; - rel_mem->bitfields2.cache_policy = cache_policy__mec_release_mem__stream; - rel_mem->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe; - - // Specify the attributes of source and destinations of data - rel_mem->bitfields3.int_sel = int_sel__mec_release_mem__none; - rel_mem->bitfields3.data_sel = data_sel__mec_release_mem__none; - rel_mem->bitfields3.dst_sel = dst_sel__mec_release_mem__memory_controller; -} - -Gfx9CmdWriter::Gfx9CmdWriter(bool atc_support, bool pcie_atomic_support) { - // Initialize various state variables related to - // atomic operations and atc support - this->atc_support_ = atc_support; - this->pcie_atomic_support_ = pcie_atomic_support; - - // Initialize various command templates - InitializeLaunchTemplate(); - InitializeAtomicTemplate(); - InitializeBarrierTemplate(); - InitializeAcquireMemTemplate(); - InitializeWaitRegMemTemplate(); - InitializeWriteDataTemplate(); - InitializeWriteData64Template(); - InitializeConditionalTemplate(); - InitializeEndOfKernelNotifyTemplate(); -} - -void Gfx9CmdWriter::BuildIndirectBufferCmd(CmdBuf* cmdbuf, const void* cmd_addr, - std::size_t cmd_size) { - // Verify the address is 4-byte aligned - uint64_t addr = uintptr_t(cmd_addr); - assert(!(addr & 0x3) && "IndirectBuffer address must be 4 byte aligned"); - - // Specify the address of indirect buffer encoding cmd stream - LaunchTemplate launch = launch_template_; - - launch.indirect_buffer.bitfields2.ib_base_lo = (PtrLow32(cmd_addr) >> 2); - launch.indirect_buffer.ib_base_hi = PtrHigh32(cmd_addr); - - // Specify the size of indirect buffer and cache policy to set - // upon executing the cmds of indirect buffer - launch.indirect_buffer.bitfields4.priv = 0; - launch.indirect_buffer.bitfields4.valid = 1; - launch.indirect_buffer.bitfields4.ib_size = cmd_size / sizeof(uint32_t); - launch.indirect_buffer.bitfields4.cache_policy = cache_policy__mec_indirect_buffer__stream; - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, launch); -} - -void Gfx9CmdWriter::BuildAtomicPacket(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint32_t* addr, - uint32_t value, uint32_t compare) { - AtomicTemplate atomicTemplate = atomic_template_; - PM4MEC_ATOMIC_MEM* atomicCmd = &atomicTemplate.atomic; - - // make sure the destination adddress is aligned - uint32_t address_low = PtrLow32((void*)addr); - uint32_t address_high = PtrHigh32((void*)addr); - assert(!(address_low & 0x7) && "destination address must be 8 byte aligned"); - atomicCmd->addr_lo = address_low; - atomicCmd->addr_hi = address_high; - - switch (atomic_op) { - case CommandWriter::kAtomicTypeIncrement: - assert(!(value != 0x01) && "Atomic Increment value should be 1"); - case CommandWriter::kAtomicAdd: - atomicCmd->src_data_lo = value; - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_ADD_RTN_32; - break; - case CommandWriter::kAtomicTypeDecrement: - assert(!(value != 0x01) && "Atomic Decrement value should be 1"); - case CommandWriter::kAtomicSubtract: - atomicCmd->src_data_lo = value; - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_SUB_RTN_32; - break; - case CommandWriter::kAtomicTypeBlockingCompareAndSwap: - atomicCmd->bitfields9.loop_interval = 128; - atomicCmd->bitfields2.command = command__mec_atomic_mem__loop_until_compare_satisfied; - case CommandWriter::kAtomicTypeCompareAndSwap: - atomicCmd->src_data_lo = value; - atomicCmd->cmp_data_lo = compare; - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_CMPSWAP_RTN_32; - break; - case CommandWriter::kAtomicSwap: - atomicCmd->src_data_lo = value; - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_SWAP_RTN_32; - break; - default: - assert((false) && "Atomic operation id is invalid"); - } - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, atomicTemplate); -} - -void Gfx9CmdWriter::BuildAtomicPacket64(CmdBuf* cmdbuf, AtomicType atomic_op, - volatile uint64_t* addr, uint64_t value, uint64_t compare) { - AtomicTemplate atomicTemplate = atomic_template_; - PM4MEC_ATOMIC_MEM* atomicCmd = &atomicTemplate.atomic; - - // make sure the destination adddress is aligned - uint32_t address_low = PtrLow32((void*)addr); - uint32_t address_high = PtrHigh32((void*)addr); - assert(!(address_low & 0x7) && "destination address must be 8 byte aligned"); - atomicCmd->addr_lo = address_low; - atomicCmd->addr_hi = address_high; - - switch (atomic_op) { - case CommandWriter::kAtomicTypeIncrement: - assert(!(value != 0x01) && "Atomic Increment value should be 1"); - case CommandWriter::kAtomicAdd: - atomicCmd->src_data_lo = Low32(value); - atomicCmd->src_data_hi = High32(value); - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_ADD_RTN_64; - break; - case CommandWriter::kAtomicTypeDecrement: - assert(!(value != 0x01) && "Atomic Decrement value should be 1"); - case CommandWriter::kAtomicSubtract: - atomicCmd->src_data_lo = Low32(value); - atomicCmd->src_data_hi = High32(value); - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_SUB_RTN_64; - break; - case CommandWriter::kAtomicTypeBlockingCompareAndSwap: - atomicCmd->bitfields9.loop_interval = 128; - atomicCmd->bitfields2.command = command__mec_atomic_mem__loop_until_compare_satisfied; - case CommandWriter::kAtomicTypeCompareAndSwap: - atomicCmd->src_data_lo = Low32(value); - atomicCmd->src_data_hi = High32(value); - atomicCmd->cmp_data_lo = Low32(compare); - atomicCmd->cmp_data_hi = High32(compare); - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_CMPSWAP_RTN_64; - break; - case CommandWriter::kAtomicSwap: - atomicCmd->src_data_lo = Low32(value); - atomicCmd->src_data_hi = High32(value); - atomicCmd->bitfields2.atomic = TC_OP_ATOMIC_SWAP_RTN_64; - break; - default: - assert((false) && "Atomic operation id is invalid"); - } - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, atomicTemplate); -} - -void Gfx9CmdWriter::BuildBarrierCommand(CmdBuf* cmdBuf) { - APPEND_COMMAND_WRAPPER(cmdBuf, pending_dispatch_template_); -} - -void Gfx9CmdWriter::BuildWriteDataCommand(CmdBuf* cmdbuf, uint32_t* write_addr, - uint32_t write_value) { - // Copy the initialized command packet and its payload - WriteDataTemplate command = write_data_template_; - - // Encode the user specified address to write to - uint64_t addr = uintptr_t(write_addr); - assert(!(addr & 0x3) && "WriteData address must be 4 byte aligned"); - - // Specify the value to write - command.write_data_value = write_value; - - // Test Code to see if this makes a difference - command.write_data.dst_mem_addr_hi = PtrHigh32(write_addr); - command.write_data.bitfields3c.dst_mem_addr_lo = (PtrLow32(write_addr) >> 2); - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, command); -} - -void Gfx9CmdWriter::BuildWriteData64Command(CmdBuf* cmdbuf, uint64_t* write_addr, - uint64_t write_value) { - // Copy the initialized command packet and its payload - WriteData64Template command = write_data64_template_; - - // Encode the user specified address to write to - uint64_t addr = uintptr_t(write_addr); - assert(!(addr & 0x3) && "WriteData address must be 4 byte aligned"); - - command.write_data.bitfields3c.dst_mem_addr_lo = (PtrLow32(write_addr) >> 2); - command.write_data.dst_mem_addr_hi = PtrHigh32(write_addr); - - // Specify the value to write - command.write_data_value = write_value; - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, command); -} - -void Gfx9CmdWriter::BuildWaitRegMemCommand(CmdBuf* cmdbuf, bool mem_space, uint64_t wait_addr, - bool func_eq, uint32_t mask_val, uint32_t wait_val) { - WaitRegMemTemplate wait_cmd = wait_reg_mem_template_; - - // Apply the space to which addr belongs - if (mem_space) { - wait_cmd.wait_reg_mem.bitfields2.mem_space = mem_space__mec_wait_reg_mem__memory_space; - } else { - wait_cmd.wait_reg_mem.bitfields2.mem_space = mem_space__mec_wait_reg_mem__register_space; - } - - // Apply the function - equal / not equal desired by user - if (func_eq) { - wait_cmd.wait_reg_mem.bitfields2.function = - function__mec_wait_reg_mem__equal_to_the_reference_value; - } else { - wait_cmd.wait_reg_mem.bitfields2.function = - function__mec_wait_reg_mem__not_equal_reference_value; - } - - // Value to use in applying equal / not equal function - wait_cmd.wait_reg_mem.reference = wait_val; - - // Apply the mask on value at address/register - wait_cmd.wait_reg_mem.mask = mask_val; - - // The address to poll should be DWord (4 byte) aligned - // Update upper 32 bit address if addr is not a register - if (mem_space) { - assert(!(wait_addr & 0x3) && "WaitRegMem address must be 4 byte aligned"); - } - wait_cmd.wait_reg_mem.bitfields3a.mem_poll_addr_lo = (Low32(wait_addr) >> 2); - if (mem_space) { - wait_cmd.wait_reg_mem.mem_poll_addr_hi = High32(wait_addr); - } - - // Append the command to cmd stream - APPEND_COMMAND_WRAPPER(cmdbuf, wait_cmd); -} - -void Gfx9CmdWriter::BuildConditionalExecute(CmdBuf* cmdbuf, uint32_t* signal, uint16_t count) { - assert(false && "BuildConditionalExecute method is not implemented"); - /* - ConditionalExecuteTemplate conditional = conditional_template_; - - uint32_t address_low = PtrLow32(signal); - uint32_t address_high = PtrHigh32(signal); - assert(!(address_low & 0x7) && "destination address must be 8 byte aligned"); - - conditional.conditional.boolAddrLo = address_low; - conditional.conditional.boolAddrHi = address_high; - conditional.conditional.execCount = count; - - APPEND_COMMAND_WRAPPER(cmdbuf, conditional); - */ -} - -void Gfx9CmdWriter::BuildUpdateHostAddress(CmdBuf* cmdbuf, uint64_t* addr, int64_t value) { - // If Atomics are supported, use it - if (pcie_atomic_support_) { - BuildAtomicPacket64(cmdbuf, CommandWriter::AtomicType::kAtomicSwap, (volatile uint64_t*)addr, - value); - return; - } - - BuildWriteData64Command(cmdbuf, addr, value); - return; -} - -void Gfx9CmdWriter::BuildBOPNotifyCmd(CmdBuf* cmdbuf, const void* write_addr, uint32_t write_value, - bool interrupt) { - // Initialize the command including its header - EndofKernelNotifyTemplate eop = notify_template_; - PM4MEC_RELEASE_MEM* rel_mem = &eop.release_mem; - - // Program CP to perform various cache operations - // before issuing the write operation commences - rel_mem->bitfields2.tc_action_ena = true; - rel_mem->bitfields2.tc_wb_action_ena = true; - - // Update cmd to write a user specified 32-bit value - rel_mem->data_lo = write_value; - rel_mem->bitfields3.data_sel = data_sel__mec_release_mem__send_32_bit_low; - - // Update cmd with user specified address to write to - rel_mem->address_hi = High32(uint64_t(write_addr)); - rel_mem->bitfields4b.address_lo_64b = (Low32(uint64_t(write_addr) >> 3)); - - // Update cmd to issue interrupt if user has requested it - if (interrupt) { - rel_mem->bitfields3.int_sel = int_sel__mec_release_mem__send_interrupt_after_write_confirm; - } - - // Serialize the command as stream of Dwords - APPEND_COMMAND_WRAPPER(cmdbuf, eop); -} - -void Gfx9CmdWriter::BuildBarrierFenceCommands(CmdBuf* cmdbuf) { - // TODO: temporarily remove the check because some OpenCL tests - // (test_buffers, test_relationals) are failing. - // if (using_cc_memory_policy_) - // return; - AcquireMemTemplate invalidate_src_caches = invalidate_cache_template_; - - // wbINVL2 by default writes-back and invalidates both L1 and L2 - invalidate_src_caches.acquire_mem.bitfields2.coher_cntl = CP_COHER_CNTL__TC_ACTION_ENA_MASK; - invalidate_src_caches.acquire_mem.bitfields2.coher_cntl |= CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK; - - APPEND_COMMAND_WRAPPER(cmdbuf, invalidate_src_caches); -} - -/* -// PM4 packet for profilers -#define PM4_PACKET3 (0xC0000000) -#define PM4_PACKET3_CMD_SHIFT 8 -#define PM4_PACKET3_COUNT_SHIFT 16 - -#define PACKET3(cmd, count) \ - (PM4_PACKET3 | (((count)-1) << PM4_PACKET3_COUNT_SHIFT) | \ - ((cmd) << PM4_PACKET3_CMD_SHIFT)) -*/ - -// Structure to store the event PM4 packet -typedef struct WriteRegPacket_ { uint32_t item[3]; } WriteRegPacket; - -void Gfx9CmdWriter::BuildWriteEventPacket(CmdBuf* cmdbuf, uint32_t event) { - PM4MEC_EVENT_WRITE cp_event_initiator; - memset(&cp_event_initiator, 0, sizeof(PM4MEC_EVENT_WRITE)); - cp_event_initiator.ordinal1 = - PM4_TYPE3_HDR(IT_EVENT_WRITE, (sizeof(PM4MEC_EVENT_WRITE) / sizeof(uint32_t))); - cp_event_initiator.ordinal2 = 0; - - VGT_EVENT_TYPE eventType = Reserved_0x00; - switch (event) { - case kPerfCntrsStart: - eventType = PERFCOUNTER_START; - break; - case kPerfCntrsStop: - eventType = PERFCOUNTER_STOP; - break; - case kPerfCntrsSample: - eventType = PERFCOUNTER_SAMPLE; - break; - default: - assert(false && "Illegal VGT Event Id"); - } - - MEC_EVENT_WRITE_event_index_enum index; - index = event_index__mec_event_write__other; - cp_event_initiator.bitfields2.event_index = index; - cp_event_initiator.bitfields2.event_type = eventType; - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, cp_event_initiator); -} - -void Gfx9CmdWriter::BuildWriteUnshadowRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - WriteRegPacket packet; - packet.item[0] = - PM4_TYPE3_HDR(IT_SET_UCONFIG_REG, (1 + sizeof(PM4MEC_SET_CONFIG_REG) / sizeof(uint32_t))); - packet.item[1] = (addr - UCONFIG_SPACE_START); - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); -} - -void Gfx9CmdWriter::BuildWriteUConfigRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - WriteRegPacket packet; - packet.item[0] = - PM4_TYPE3_HDR(IT_SET_UCONFIG_REG, (1 + sizeof(PM4MEC_SET_CONFIG_REG) / sizeof(uint32_t))); - packet.item[1] = (addr - UCONFIG_SPACE_START); - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); -} - -void Gfx9CmdWriter::BuildWriteShRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - WriteRegPacket packet; - packet.item[0] = - PM4_TYPE3_HDR(IT_SET_SH_REG, (1 + sizeof(PM4MEC_SET_CONFIG_REG) / sizeof(uint32_t))); - packet.item[1] = (addr - PERSISTENT_SPACE_START); - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); -} - -void Gfx9CmdWriter::BuildCopyDataPacket(CmdBuf* cmdbuf, uint32_t src_sel, uint32_t src_addr_lo, - uint32_t src_addr_hi, uint32_t* dst_addr, uint32_t size, - bool wait) { - PM4MEC_COPY_DATA cmd_data; - memset(&cmd_data, 0, sizeof(PM4MEC_COPY_DATA)); - cmd_data.ordinal1 = PM4_TYPE3_HDR(IT_COPY_DATA, (sizeof(PM4MEC_COPY_DATA) / sizeof(uint32_t))); - - MEC_COPY_DATA_src_sel_enum data_src = src_sel__mec_copy_data__memory; - switch (src_sel) { - case 0: - data_src = src_sel__mec_copy_data__mem_mapped_register; - break; - case 4: - data_src = src_sel__mec_copy_data__perfcounters; - break; - default: - assert(false && "CopyData Illegal value for source of data"); - break; - } - cmd_data.bitfields2.src_sel = data_src; - cmd_data.bitfields2.src_cache_policy = src_cache_policy__mec_copy_data__stream; - - cmd_data.bitfields2.dst_sel = dst_sel__mec_copy_data__memory; - cmd_data.bitfields2.dst_cache_policy = dst_cache_policy__mec_copy_data__stream; - - cmd_data.bitfields2.wr_confirm = (MEC_COPY_DATA_wr_confirm_enum)wait; - cmd_data.bitfields2.count_sel = (size == 0) ? count_sel__mec_copy_data__32_bits_of_data - : count_sel__mec_copy_data__64_bits_of_data; - - // Specify the source register offset - cmd_data.bitfields3a.src_reg_offset = src_addr_lo; - - // Specify the destination memory address - cmd_data.dst_addr_hi = PtrHigh32(dst_addr); - if (size == 0) { - cmd_data.bitfields5b.dst_32b_addr_lo = (PtrLow32(dst_addr) >> 2); - } else { - cmd_data.bitfields5c.dst_64b_addr_lo = (PtrLow32(dst_addr) >> 3); - } - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, cmd_data); -} - -void Gfx9CmdWriter::BuildCacheFlushPacket(CmdBuf* cmdbuf) { - // Initialize the command header - PM4MEC_ACQUIRE_MEM cache_flush = invalidate_cache_template_.acquire_mem; - - // Program Coherence Control Register. Initialize L2 Cache flush - // for Non-Coherent memory blocks - uint32_t coher_cntl = 0; - - coher_cntl |= CP_COHER_CNTL__TC_ACTION_ENA_MASK; - coher_cntl |= CP_COHER_CNTL__TCL1_ACTION_ENA_MASK; - coher_cntl |= CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK; - coher_cntl |= CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK; - coher_cntl |= CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK; - cache_flush.bitfields2.coher_cntl = coher_cntl; - - // Copy AcquireMem command buffer stream - APPEND_COMMAND_WRAPPER(cmdbuf, cache_flush); -} - -void Gfx9CmdWriter::BuildWriteWaitIdlePacket(CmdBuf* cmdbuf) { - BuildBarrierCommand(cmdbuf); - BuildCacheFlushPacket(cmdbuf); -} - -// Will issue a VGT event including a cache flush later on -void Gfx9CmdWriter::BuildVgtEventPacket(CmdBuf* cmdbuf, uint32_t vgtEvent) { - PM4MEC_EVENT_WRITE cp_event_initiator; - memset(&cp_event_initiator, 0, sizeof(PM4MEC_EVENT_WRITE)); - cp_event_initiator.ordinal1 = - PM4_TYPE3_HDR(IT_EVENT_WRITE, (sizeof(PM4MEC_EVENT_WRITE) / sizeof(uint32_t))); - cp_event_initiator.ordinal2 = 0; - - VGT_EVENT_TYPE eventType = Reserved_0x00; - switch (vgtEvent) { - case kPerfCntrsStart: - eventType = PERFCOUNTER_START; - break; - case kPerfCntrsStop: - eventType = PERFCOUNTER_STOP; - break; - case kPerfCntrsSample: - eventType = PERFCOUNTER_SAMPLE; - break; - case kThrdTraceStart: - eventType = THREAD_TRACE_START; - break; - case kThrdTraceStop: - eventType = THREAD_TRACE_STOP; - break; - case kThrdTraceFlush: - eventType = THREAD_TRACE_FLUSH; - break; - case kThrdTraceFinish: - eventType = THREAD_TRACE_FINISH; - break; - default: - assert(false && "Illegal VGT Event Id"); - } - - MEC_EVENT_WRITE_event_index_enum index; - index = event_index__mec_event_write__other; - cp_event_initiator.bitfields2.event_index = index; - cp_event_initiator.bitfields2.event_type = eventType; - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, cp_event_initiator); - - // Check If I should be issuing a cache flush operation as well - // test and remove it - BuildCacheFlushPacket(cmdbuf); -} - -void Gfx9CmdWriter::BuildWriteRegisterPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value) { - /* - WriteRegPacket packet; - packet.item[0] = (PM4_TYPE3_HDR( - IT_SET_CONFIG_REG, 1 + PM4_CMD_SET_CONFIG_REG_DWORDS, ShaderGraphics, 0)); - packet.item[1] = addr - CONFIG_SPACE_START; - packet.item[2] = value; - - APPEND_COMMAND_WRAPPER(cmdbuf, packet); - - return; - */ -} - -void Gfx9CmdWriter::BuildWriteEventQueryPacket(CmdBuf* cmdbuf, uint32_t event, uint32_t* addr) { - PM4MEC_EVENT_WRITE_QUERY cp_event_initiator; - memset(&cp_event_initiator, 0, sizeof(PM4MEC_EVENT_WRITE_QUERY)); - cp_event_initiator.ordinal1 = - PM4_TYPE3_HDR(IT_EVENT_WRITE, (sizeof(PM4MEC_EVENT_WRITE_QUERY) / sizeof(uint32_t))); - cp_event_initiator.ordinal2 = 0; - - // Update switch statements you want to support - VGT_EVENT_TYPE eventType = Reserved_0x00; - switch (event) { - default: - assert(false && "Illegal VGT Event Id"); - } - - MEC_EVENT_WRITE_event_index_enum index; - cp_event_initiator.bitfields2.event_type = eventType; - index = (MEC_EVENT_WRITE_event_index_enum)EventTypeToIndexTable[eventType]; - cp_event_initiator.bitfields2.event_index = index; - - // set the address - uint32_t addrLo = PtrLow32(addr); - uint32_t addrHi = PtrHigh32(addr); - ((addrLo & 0x7) != 0) ? assert(false) : assert(true); - - cp_event_initiator.address_hi = addrHi; - cp_event_initiator.bitfields3.address_lo = (addrLo >> 3); - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, cp_event_initiator); -} - -size_t Gfx9CmdWriter::SizeOfAtomicPacket() const { - return sizeof(AtomicTemplate) / sizeof(uint32_t); -} - -void Gfx9CmdWriter::BuildFlushCacheCmd(CmdBuf* cmdbuf, FlushCacheOptions* options, - uint32_t* writeAddr, uint32_t writeVal) { - PM4MEC_ACQUIRE_MEM cache_flush = invalidate_cache_template_.acquire_mem; - - // Verify write back address is valid. Note that this address is NOT - // used on CI. But to have a same interface as that on SI, we keep - // the address argument in this function. Thus, this check always pass - // no matter the address is NULL or not. - (writeAddr == NULL) ? assert(true) : assert(true); - - // Program Coherence Control Register. Initialize L2 Cache flush - // for Non-Coherent memory blocks - uint32_t coher_cntl = 0; - coher_cntl |= (options->l1) ? CP_COHER_CNTL__TCL1_ACTION_ENA_MASK : 0; - coher_cntl |= (options->l2) - ? (CP_COHER_CNTL__TC_ACTION_ENA_MASK | CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK) - : 0; - coher_cntl |= (options->icache) ? CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK : 0; - coher_cntl |= (options->kcache) ? CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK : 0; - cache_flush.bitfields2.coher_cntl = coher_cntl; - - // Append the built command into output Command Buffer - APPEND_COMMAND_WRAPPER(cmdbuf, cache_flush); - return; -} - -void Gfx9CmdWriter::BuildDmaDataPacket(CmdBuf* cmdbuf, uint32_t* srcAddr, uint32_t* dstAddr, - uint32_t copySize, bool waitForConfirm) { - PM4MEC_DMA_DATA cmdDmaData; - memset(&cmdDmaData, 0, sizeof(PM4MEC_DMA_DATA)); - cmdDmaData.header.u32All = - PM4_TYPE3_HDR(IT_DMA_DATA, (sizeof(PM4MEC_DMA_DATA) / sizeof(uint32_t))); - - // Specify attributes of source buffer such as its - // location and Cache policy - cmdDmaData.bitfields2.src_sel = src_sel__mec_dma_data__src_addr_using_sas; - cmdDmaData.bitfields2.src_cache_policy = src_cache_policy__mec_dma_data__stream; - - // Specify attributes of destination buffer such as its - // location and Cache policy - cmdDmaData.bitfields2.dst_sel = dst_sel__mec_dma_data__dst_addr_using_das; - cmdDmaData.bitfields2.dst_cache_policy = dst_cache_policy__mec_dma_data__stream; - - // Specify the source and destination addr - cmdDmaData.src_addr_lo_or_data = PtrLow32(srcAddr); - cmdDmaData.src_addr_hi = PtrHigh32(srcAddr); - cmdDmaData.dst_addr_lo = PtrLow32(dstAddr); - cmdDmaData.dst_addr_hi = PtrHigh32(dstAddr); - - // Number of bytes to copy. The command restricts - // the size to be (64 MB - 1) - 26 Bits - assert(copySize < 0x1FFFFF); - cmdDmaData.bitfields7.byte_count = copySize; - - // Indicate that DMA Cmd should wait if its source - // is the destination of a previous DMA Cmd - cmdDmaData.bitfields7.raw_wait = waitForConfirm; - - APPEND_COMMAND_WRAPPER(cmdbuf, cmdDmaData); - return; -} - - -} // gfx9 namespace - -} // pm4_profile diff --git a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmdwriter.h b/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmdwriter.h deleted file mode 100644 index fe7e3ce216..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/commandwriter/gfx9_cmdwriter.h +++ /dev/null @@ -1,199 +0,0 @@ -#ifndef _GFX9_CMDWRITER_H_ -#define _GFX9_CMDWRITER_H_ - -#include "cmdwriter.h" -#include "gfx9_cmds.h" - -namespace pm4_profile { - -namespace gfx9 { - - -/// @brief class Gfx9CmdWriter implements the virtual class CommandWriter -/// for GFX9 chipsets -class Gfx9CmdWriter : public CommandWriter { - public: - Gfx9CmdWriter(bool atc_support, bool pcie_atomic_support); - - /// @brief Dword specifying NOOP command for GFX9 chipsets. The macro - /// populates the NOOP command which is 32-bits wide. The second parameter, - /// the COUNT field of NOOP command, specifies the number of Dwords to skip. - /// To skip ZERO Dwords the value should be set to 0x3FFF. Since the macro - /// decrements the second parameter by TWO, an artifact of its definition, - /// the value is incremented by TWO to 0x4001 (0x3FFF + 2). - /// - inline uint32_t GetNoOpCmd() { - static const uint32_t nopCmd = PM4_TYPE3_HDR(IT_NOP, 0x4001); - return nopCmd; - } - - void BuildBarrierCommand(CmdBuf* cmdBuf); - - void BuildIndirectBufferCmd(CmdBuf* cmdbuf, const void* cmd_addr, std::size_t cmd_size); - - void BuildBOPNotifyCmd(CmdBuf* cmdbuf, const void* write_addr, uint32_t write_val, - bool interrupt); - - void BuildBarrierFenceCommands(CmdBuf* cmdbuf); - - void BuildWriteEventPacket(CmdBuf* cmdbuf, uint32_t event); - - void BuildWaitRegMemCommand(CmdBuf* cmdbuf, bool mem_space, uint64_t wait_addr, bool func_eq, - uint32_t mask_val, uint32_t wait_val); - - void BuildWriteUnshadowRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - /// @brief Build CP command to program a Gpu register - /// - /// @param cmdbuf Pointer to command buffer to be appended - /// @param addr Register to be programmed - /// @param value Value to write into register - /// - /// @return void - void BuildWriteUConfigRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - void BuildWriteShRegPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - void BuildCopyDataPacket(CmdBuf* cmdbuf, uint32_t src_sel, uint32_t src_addr_lo, - uint32_t src_addr_hi, uint32_t* dst_addr, uint32_t size, bool wait); - - void BuildWriteWaitIdlePacket(CmdBuf* cmdbuf); - - // Will issue a VGT event including a cache flush later on - void BuildVgtEventPacket(CmdBuf* cmdbuf, uint32_t vgtEvent); - - void BuildWriteRegisterPacket(CmdBuf* cmdbuf, uint32_t addr, uint32_t value); - - void BuildWriteEventQueryPacket(CmdBuf* cmdbuf, uint32_t event, uint32_t* addr); - - void BuildAtomicPacket(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint32_t* addr, - uint32_t value, uint32_t compare); - - void BuildAtomicPacket64(CmdBuf* cmdbuf, AtomicType atomic_op, volatile uint64_t* addr, - uint64_t value = 0, uint64_t compare = 0); - - size_t SizeOfAtomicPacket() const; - - void BuildConditionalExecute(CmdBuf* cmdbuf, uint32_t* signal, uint16_t count); - - void BuildWriteDataCommand(CmdBuf* cmdbuf, uint32_t* write_addr, uint32_t write_value); - - void BuildWriteData64Command(CmdBuf* cmdbuf, uint64_t* write_addr, uint64_t write_value); - - void BuildCacheFlushPacket(CmdBuf* cmdbuf); - - /// Writes into input buffer Gpu commands to flush its cache. It is - /// necessary that the buffer provided for flush commands is large - /// enough to accommodate the full set of commands. It should be at - /// least 512 bytes. - /// - /// @param tsCmdBuf Buffer to write commands to. - /// @param writeAddr Registered address into which GPU should write - /// a user provided value upon executing the flush commands. - /// @param writeVal User provided value written by GPU at user provided - /// address, upon executing the flush commands. - /// - /// @return void - void BuildFlushCacheCmd(CmdBuf* cmdBuf, FlushCacheOptions* options, uint32_t* writeAddr, - uint32_t writeVal); - - /// Builds Gpu command to copy data from source to destination buffer - /// using DMA engine. - /// - /// @param cmdbuf Buffer updated with Gpu copy command - /// @param srcAddr Address of source buffer address - /// @param dstAddr Address of destination buffer address - /// @param copySize Size of data to copy in bytes - /// @param waitForCompletion if command should wait for copying to complete - void BuildDmaDataPacket(CmdBuf* cmdBuf, uint32_t* srcAddr, uint32_t* dstAddr, uint32_t copySize, - bool waitForCompletion); - - protected: - /// @brief Append an instance of Gpu command into input command buffer stream. - /// - /// @param cmdbuf CommandWriter object appended with anohter Gpu command - /// - /// @param cmd Gpu command to be appended into command buffer - /// - /// @return void - template void AppendCommand(CmdBuf* cmdbuf, const T& cmd); - - private: - /// @brief Initializes a Gpu command which can be used to - /// reference a Gpu command stream indirectly - void InitializeLaunchTemplate(); - - /// @brief Initializes a Gpu command which can be used to - /// flush Gpu caches and write to a user configurable address - /// to indicate an end of kernel - void InitializeEndOfKernelNotifyTemplate(); - - /// @brief Initializes a Gpu command to perform atomic operations - //// - void InitializeAtomicTemplate(); - - /// @brief Initializes a Gpu command to allow conditional execution - /// of a Gpu command stream - void InitializeConditionalTemplate(); - - /// @brief Initializes a Gpu command to let command processor - /// wait for some update before letting other commands to be - /// processed - void InitializeWaitRegMemTemplate(); - - /// @brief Initializes the template for Barrier command. - /// Applications can use Barrier command to ensure their - /// command is executed only after all other commands have - /// completed their execution. - void InitializeBarrierTemplate(); - - void BuildUpdateHostAddress(CmdBuf* cmdbuf, uint64_t* addr, int64_t value); - - /// @brief Initializes Acquire Memory command template. Users - /// can submit this command to invalidate Gpu caches - L1 and - /// or L2. - void InitializeAcquireMemTemplate(); - - /// @brief Initializes an instance of Write Data command - /// for use by an application - void InitializeWriteDataTemplate(); - void InitializeWriteData64Template(); - void InitializeWriteDataTemplate(PM4MEC_WRITE_DATA* write_data, bool bit32); - - /// @brief Builds wait_reg_mem with EQUALS condition - void BuildWaitRegMemCommand(CmdBuf* cmdbuf, uint64_t wait_addr, uint32_t wait_value); - - /// @brief Instance of Gpu command to reference dispatch commands - LaunchTemplate launch_template_; - - /// @brief Instance of Gpu command to use in determing end of kernel - EndofKernelNotifyTemplate notify_template_; - - /// @brief Instance of Gpu command to use in performing atomic operations - AtomicTemplate atomic_template_; - - /// @brief Instance of Pm4 command WRITE_DATA - WriteDataTemplate write_data_template_; - WriteData64Template write_data64_template_; - - /// @brief Instance of Pm4 command EVENT_WRITE - BarrierTemplate pending_dispatch_template_; - - /// @brief Instance of Pm4 command ACQUIRE_MEM - AcquireMemTemplate invalidate_cache_template_; - - /// @brief Instance of Pm4 command WAIT_REG_MEM - WaitRegMemTemplate wait_reg_mem_template_; - - /// @brief ATC support. - bool atc_support_; - - /// @brief PCIe atomic support. - bool pcie_atomic_support_; -}; - -} // gfx9 - -} // pm4_profile - -#endif // _GFX9_CMDWRITER_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/core/CMakeLists.txt b/runtime/hsa-amd-aqlprofile/src/core/CMakeLists.txt deleted file mode 100644 index d35c2c934c..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/CMakeLists.txt +++ /dev/null @@ -1,20 +0,0 @@ -# -# Source files for Rocr Service Manager -# -set ( LIB_SRC aql_profile.cpp populate_aql.cpp gfx8_factory.cpp gfx9_factory.cpp legacy_pm4.cpp ) - -# -# Header files include path(s). -# -include_directories ( $ENV{ROCR_INC_DIR} ) -include_directories ( ${PROJ_DIR}/perfcounter ) -include_directories ( ${PROJ_DIR}/threadtrace ) -include_directories ( ${PROJ_DIR}/commandwriter ) -include_directories ( ${API_DIR} ) - -# -# Build Service Manager as a dynamic Library object -# -set ( LIB_LIST ${PMC_LIB} ${SQTT_LIB} ${CMDWRITER_LIB} ) -add_library ( ${TARGET_LIB} SHARED ${LIB_SRC} ) -target_link_libraries( ${TARGET_LIB} ${LIB_LIST} c stdc++ dl pthread rt ) diff --git a/runtime/hsa-amd-aqlprofile/src/core/amd_aql_pm4_ib_packet.h b/runtime/hsa-amd-aqlprofile/src/core/amd_aql_pm4_ib_packet.h deleted file mode 100644 index bd364593b3..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/amd_aql_pm4_ib_packet.h +++ /dev/null @@ -1,67 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Copyright 2017 ADVANCED MICRO DEVICES, INC. -// -// AMD is granting you permission to use this software and documentation(if any) -// (collectively, the "Materials") pursuant to the terms and conditions of the -// Software License Agreement included with the Materials.If you do not have a -// copy of the Software License Agreement, contact your AMD representative for a -// copy. -// -// You agree that you will not reverse engineer or decompile the Materials, in -// whole or in part, except as allowed by applicable law. -// -// WARRANTY DISCLAIMER : THE SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF -// ANY KIND.AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, -// INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE, TITLE, NON - INFRINGEMENT, THAT THE -// SOFTWARE WILL RUN UNINTERRUPTED OR ERROR - FREE OR WARRANTIES ARISING FROM -// CUSTOM OF TRADE OR COURSE OF USAGE.THE ENTIRE RISK ASSOCIATED WITH THE USE OF -// THE SOFTWARE IS ASSUMED BY YOU.Some jurisdictions do not allow the exclusion -// of implied warranties, so the above exclusion may not apply to You. -// -// LIMITATION OF LIABILITY AND INDEMNIFICATION : AMD AND ITS LICENSORS WILL NOT, -// UNDER ANY CIRCUMSTANCES BE LIABLE TO YOU FOR ANY PUNITIVE, DIRECT, -// INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM USE OF -// THE SOFTWARE OR THIS AGREEMENT EVEN IF AMD AND ITS LICENSORS HAVE BEEN -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.In no event shall AMD's total -// liability to You for all damages, losses, and causes of action (whether in -// contract, tort (including negligence) or otherwise) exceed the amount of $100 -// USD. You agree to defend, indemnify and hold harmless AMD and its licensors, -// and any of their directors, officers, employees, affiliates or agents from -// and against any and all loss, damage, liability and other expenses (including -// reasonable attorneys' fees), resulting from Your use of the Software or -// violation of the terms and conditions of this Agreement. -// -// U.S.GOVERNMENT RESTRICTED RIGHTS : The Materials are provided with -// "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is -// subject to the restrictions as set forth in FAR 52.227 - 14 and DFAR252.227 - -// 7013, et seq., or its successor.Use of the Materials by the Government -// constitutes acknowledgement of AMD's proprietary rights in them. -// -// EXPORT RESTRICTIONS: The Materials may be subject to export restrictions as -// stated in the Software License Agreement. -// -//////////////////////////////////////////////////////////////////////////////// - -#ifndef _AMD_AQL_PM4_IB_PACKET_H_ -#define _AMD_AQL_PM4_IB_PACKET_H_ - -// Value of 'pm4_ib_format' field of amd_aql_pm4_ib_packet_t packet -const static uint32_t AMD_AQL_PM4_IB_FORMAT = 1; -// Value of 'dw_count_remain' field of amd_aql_pm4_ib_packet_t packet -const static uint32_t AMD_AQL_PM4_IB_DW_COUNT_REMAIN = 10; -// Size of 'reserved' array of amd_aql_pm4_ib_packet_t packet -const static uint32_t AMD_AQL_PM4_IB_RESERVED_COUNT = 8; - -// AQL Vendor Specific Packet which carry PM4 IB command -typedef struct { - uint16_t header; - uint16_t pm4_ib_format; - uint32_t pm4_ib_command[4]; - uint32_t dw_count_remain; - uint32_t reserved[AMD_AQL_PM4_IB_RESERVED_COUNT]; - hsa_signal_t completion_signal; -} amd_aql_pm4_ib_packet_t; - -#endif // _AMD_AQL_PM4_IB_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/core/aql_profile.cpp b/runtime/hsa-amd-aqlprofile/src/core/aql_profile.cpp deleted file mode 100644 index e6abeea75f..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/aql_profile.cpp +++ /dev/null @@ -1,503 +0,0 @@ -#include "aql_profile.h" - -#include -#include -#include - -#include "pm4_factory.h" -#include "cmdwriter.h" // commandwriter -#include "perf_counter.h" // perfcounter -#include "thread_trace.h" // threadtrace -#include "gpu_block_info.h" -#include "logger.h" - -#define PUBLIC_API __attribute__((visibility("default"))) -#define DESTRUCTOR_API __attribute__((destructor)) -#define ERR_CHECK(cond, err, msg) \ - { \ - if (cond) { \ - ERR_LOGGING << msg; \ - return err; \ - } \ - } - -namespace aql_profile { - -// Command buffer partitioning manager -// Supports Pre/Post commands partitioning -// and postfix control partition -class CommandBufferMgr { - const static uint32_t align_size = 0x100; - const static uint32_t align_mask = align_size - 1; - - struct info_t { - uint32_t precmds_size; - uint32_t postcmds_size; - }; - - descriptor_t buffer; - uint32_t postfix_size; - info_t* info; - - uint32_t align(const uint32_t& size) { return (size + align_mask) & ~align_mask; } - - public: - explicit CommandBufferMgr(const profile_t* profile) - : buffer(profile->command_buffer), postfix_size(0), info(NULL) { - info = (info_t*)setPostfix(sizeof(info_t)); - } - - uint32_t getSize() { return buffer.size; } - - void* setPostfix(const uint32_t& size) { - if (size > postfix_size) { - const uint32_t delta = size - postfix_size; - postfix_size = size; - buffer.size -= (delta < buffer.size) ? delta : buffer.size; - } - if (buffer.size == 0) - throw aql_profile_exc_msg("CommandBufferMgr::setPostfix(): buffer size set to zero"); - return (buffer.size != 0) ? buffer.ptr + buffer.size : NULL; - } - - bool setPreSize(const uint32_t& size) { - bool suc = (size <= buffer.size); - if (suc) info->precmds_size = size; - if (!suc) - throw aql_profile_exc_msg("CommandBufferMgr::setPreSize(): size set out of the buffer"); - return suc; - } - - uint32_t getPostOffset() { return align(info->precmds_size); } - - bool checkTotalSize(const uint32_t& size) { - bool suc = (size <= buffer.size); - if (suc) suc = (size >= info->precmds_size); - if (suc) { - info->postcmds_size = size - info->precmds_size; - suc = ((getPostOffset() + info->postcmds_size) <= buffer.size); - } - if (!suc) - throw aql_profile_exc_msg("CommandBufferMgr::checkTotalSize(): size set out of the buffer"); - return suc; - } - - descriptor_t getPreDescr() { - descriptor_t descr; - descr.ptr = buffer.ptr; - descr.size = info->precmds_size; - return descr; - } - - descriptor_t getPostDescr() { - descriptor_t descr; - descr.ptr = buffer.ptr + getPostOffset(); - descr.size = info->postcmds_size; - return descr; - } -}; - -static inline pm4_profile::CountersMap CountersMapCreate(const profile_t* profile, - const Pm4Factory* pm4_factory) { - pm4_profile::CountersMap countersMap; - for (const hsa_ven_amd_aqlprofile_event_t* p = profile->events; - p < profile->events + profile->event_count; ++p) { - countersMap[pm4_factory->getBlockId(p)].push_back(p->counter_id); - } - return countersMap; -} - -typedef std::vector EventsVec; -static inline EventsVec EventsVecCreate(const profile_t* profile, const Pm4Factory* pm4_factory) { - pm4_profile::CountersMap countersMap = CountersMapCreate(profile, pm4_factory); - - std::map id_map; - for (const hsa_ven_amd_aqlprofile_event_t* p = profile->events; - p < profile->events + profile->event_count; ++p) { - id_map.insert(decltype(id_map)::value_type(pm4_factory->getBlockId(p), p)); - } - - // Iterate through the list of blocks/counters to generate correct order events vector - EventsVec eventsVec; - for (pm4_profile::CountersMap::const_iterator block_it = countersMap.begin(); - block_it != countersMap.end(); ++block_it) { - const uint32_t block_id = block_it->first; - const pm4_profile::CountersVec& counters = block_it->second; - const uint32_t counter_count = counters.size(); - - for (uint32_t ind = 0; ind < counter_count; ++ind) { - eventsVec.push_back(id_map[block_id] + ind); - } - } - - return eventsVec; -} - -static inline bool is_event_match(const event_t& event1, const event_t& event2) { - return (event1.block_name == event2.block_name) && (event1.block_index == event2.block_index) && - (event1.counter_id == event2.counter_id); -} - -hsa_status_t default_pmcdata_callback(hsa_ven_amd_aqlprofile_info_type_t info_type, - hsa_ven_amd_aqlprofile_info_data_t* info_data, - void* callback_data) { - hsa_status_t status = HSA_STATUS_SUCCESS; - hsa_ven_amd_aqlprofile_info_data_t* passed_data = - reinterpret_cast(callback_data); - - if (info_type == HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA) { - if (is_event_match(info_data->pmc_data.event, passed_data->pmc_data.event)) { - if (passed_data->sample_id == UINT32_MAX) { - passed_data->pmc_data.result += info_data->pmc_data.result; - } else if (passed_data->sample_id == info_data->sample_id) { - passed_data->pmc_data.result = info_data->pmc_data.result; - status = HSA_STATUS_INFO_BREAK; - } - } - } - - return status; -} - -struct sqtt_ctrl_t { - uint32_t status; - uint32_t counter; - uint32_t writePtr; -}; - -hsa_status_t default_sqttdata_callback(hsa_ven_amd_aqlprofile_info_type_t info_type, - hsa_ven_amd_aqlprofile_info_data_t* info_data, - void* callback_data) { - hsa_status_t status = HSA_STATUS_SUCCESS; - hsa_ven_amd_aqlprofile_info_data_t* passed_data = - reinterpret_cast(callback_data); - - if (info_type == HSA_VEN_AMD_AQLPROFILE_INFO_SQTT_DATA) { - if (info_data->sample_id == passed_data->sample_id) { - passed_data->sqtt_data = info_data->sqtt_data; - status = HSA_STATUS_INFO_BREAK; - } - } - - return status; -} - -std::mutex Logger::mutex; -Logger* Logger::instance = NULL; -std::mutex Pm4Factory::mutex; -Pm4Factory::instances_t Pm4Factory::instances; - -DESTRUCTOR_API void destructor() { - Logger::Destroy(); - Pm4Factory::Destroy(); -} - -} // aql_profile - -extern "C" { - -PUBLIC_API hsa_status_t hsa_ven_amd_aqlprofile_error_string(const char** str) { - *str = aql_profile::Logger::LastMessage().c_str(); - return HSA_STATUS_SUCCESS; -} - -// Check if event is valid for the specific GPU -PUBLIC_API hsa_status_t hsa_ven_amd_aqlprofile_validate_event( - hsa_agent_t agent, const hsa_ven_amd_aqlprofile_event_t* event, bool* result) { - hsa_status_t status = HSA_STATUS_SUCCESS; - *result = false; - - try { - aql_profile::Pm4Factory* pm4_factory = aql_profile::Pm4Factory::Create(agent); - if (pm4_factory->getBlockInfo(event) != NULL) *result = true; - } catch (aql_profile::event_exception& e) { - INFO_LOGGING << e.what(); - } catch (std::exception& e) { - ERR_LOGGING << e.what(); - status = HSA_STATUS_ERROR; - } - - return status; -} - -// Method to populate the provided AQL packet with profiling start commands -PUBLIC_API hsa_status_t hsa_ven_amd_aqlprofile_start( - const hsa_ven_amd_aqlprofile_profile_t* profile, aql_profile::packet_t* aql_start_packet) { - try { - aql_profile::Pm4Factory* pm4_factory = aql_profile::Pm4Factory::Create(profile); - pm4_profile::CommandWriter* cmdWriter = pm4_factory->getCommandWriter(); - pm4_profile::DefaultCmdBuf commands; - aql_profile::CommandBufferMgr cmdBufMgr(profile); - - if (profile->type == HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC) { - pm4_profile::PerfCounter* pmcMgr = pm4_factory->getPmcMgr(); - - // Generate start commands - const pm4_profile::CountersMap countersMap = CountersMapCreate(profile, pm4_factory); - pmcMgr->begin(&commands, cmdWriter, countersMap); - cmdBufMgr.setPreSize(commands.Size()); - - // Generate stop commands - const uint32_t data_size = - pmcMgr->end(&commands, cmdWriter, countersMap, profile->output_buffer.ptr); - ERR_CHECK(data_size == 0, HSA_STATUS_ERROR, "PMC mgr end(): data size set to zero"); - assert(data_size <= profile->output_buffer.size); - if (data_size > profile->output_buffer.size) { - ERR_LOGGING << "data size assertion failed, data_size(" << data_size << "), buffer size(" - << profile->output_buffer.size << ")"; - return HSA_STATUS_ERROR; - } - } else if (profile->type == HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_SQTT) { - pm4_profile::ThreadTrace* sqttMgr = pm4_factory->getSqttMgr(); - - pm4_profile::ThreadTraceConfig sqtt_config; - sqttMgr->InitThreadTraceConfig(&sqtt_config); - if (profile->parameters) { - for (const hsa_ven_amd_aqlprofile_parameter_t* p = profile->parameters; - p < (profile->parameters + profile->parameter_count); ++p) { - switch (p->parameter_name) { - case HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET: - sqtt_config.threadTraceTargetCu = p->value; - break; - case HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK: - sqtt_config.threadTraceVmIdMask = p->value; - break; - case HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK: - sqtt_config.threadTraceMask = p->value; - break; - case HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK: - sqtt_config.threadTraceTokenMask = p->value; - break; - case HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2: - sqtt_config.threadTraceTokenMask2 = p->value; - break; - default: - ERR_LOGGING << "Bad SQTT parameter name (" << p->parameter_name << ")"; - return HSA_STATUS_ERROR_INVALID_ARGUMENT; - } - } - } - sqttMgr->Init(&sqtt_config); - - sqttMgr->setSqttDataBuff((uint8_t*)profile->output_buffer.ptr, profile->output_buffer.size); - - // Control buffer registering - const uint32_t status_size = sqttMgr->StatusSizeInfo(); - void* status_ptr = cmdBufMgr.setPostfix(status_size); - sqttMgr->setSqttCtrlBuff((uint32_t*)status_ptr); - - // Generate start commands - sqttMgr->BeginSession(&commands, cmdWriter); - cmdBufMgr.setPreSize(commands.Size()); - // Generate stop commands - sqttMgr->StopSession(&commands, cmdWriter); - } else { - ERR_LOGGING << "Bad profile type (" << profile->type << ")"; - return HSA_STATUS_ERROR_INVALID_ARGUMENT; - } - - cmdBufMgr.checkTotalSize(commands.Size()); - - const aql_profile::descriptor_t pre_descr = cmdBufMgr.getPreDescr(); - const aql_profile::descriptor_t post_descr = cmdBufMgr.getPostDescr(); - memcpy(pre_descr.ptr, commands.Base(), pre_descr.size); - memcpy(post_descr.ptr, commands.Base() + pre_descr.size, post_descr.size); - // Populate start aql packet - aql_profile::populateAql(pre_descr.ptr, pre_descr.size, cmdWriter, aql_start_packet); - } catch (std::exception& e) { - ERR_LOGGING << e.what(); - return HSA_STATUS_ERROR; - } - - return HSA_STATUS_SUCCESS; -} - -// Method to populate the provided AQL packet with profiling stop commands -PUBLIC_API hsa_status_t hsa_ven_amd_aqlprofile_stop(const hsa_ven_amd_aqlprofile_profile_t* profile, - aql_profile::packet_t* aql_stop_packet) { - try { - aql_profile::Pm4Factory* pm4_factory = aql_profile::Pm4Factory::Create(profile); - pm4_profile::CommandWriter* cmdWriter = pm4_factory->getCommandWriter(); - aql_profile::CommandBufferMgr cmdBufMgr(profile); - - // Populate stop aql packet - const aql_profile::descriptor_t post_descr = cmdBufMgr.getPostDescr(); - aql_profile::populateAql(post_descr.ptr, post_descr.size, cmdWriter, aql_stop_packet); - } catch (std::exception& e) { - ERR_LOGGING << e.what(); - return HSA_STATUS_ERROR; - } - - return HSA_STATUS_SUCCESS; -} - -// Legacy devices, converting of the profiling AQL packet to PM4 packet blob -PUBLIC_API hsa_status_t -hsa_ven_amd_aqlprofile_legacy_get_pm4(const aql_profile::packet_t* aql_packet, void* data) { - try { - // Populate GFX8 pm4 packet blob - // Adding HSA barrier acquire packet - data = aql_profile::legacyAqlAcquire(aql_packet, data); - // Adding PM4 command packet - data = aql_profile::legacyPm4(aql_packet, data); - // Adding HSA barrier release packet - data = aql_profile::legacyAqlRelease(aql_packet, data); - } catch (std::exception& e) { - ERR_LOGGING << e.what(); - return HSA_STATUS_ERROR; - } - - return HSA_STATUS_SUCCESS; -} - -// Method for getting the profile info -PUBLIC_API hsa_status_t -hsa_ven_amd_aqlprofile_get_info(const hsa_ven_amd_aqlprofile_profile_t* profile, - hsa_ven_amd_aqlprofile_info_type_t attribute, void* value) { - hsa_status_t status = HSA_STATUS_SUCCESS; - - try { - switch (attribute) { - case HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE: - *(uint32_t*)value = 0x1000; // a current approximation as 4K is big enaugh - break; - case HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE: - *(uint32_t*)value = 0x1000; // a current approximation as 4K is big enaugh - break; - case HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA: - reinterpret_cast(value)->pmc_data.result = 0; - status = hsa_ven_amd_aqlprofile_iterate_data(profile, aql_profile::default_pmcdata_callback, - value); - break; - case HSA_VEN_AMD_AQLPROFILE_INFO_SQTT_DATA: - status = hsa_ven_amd_aqlprofile_iterate_data(profile, - aql_profile::default_sqttdata_callback, value); - break; - default: - status = HSA_STATUS_ERROR_INVALID_ARGUMENT; - ERR_LOGGING << "Invalid attribute (" << attribute << ")"; - } - } catch (std::exception& e) { - ERR_LOGGING << e.what(); - return HSA_STATUS_ERROR; - } - - return status; -} - -// Method for iterating the events output data -PUBLIC_API hsa_status_t -hsa_ven_amd_aqlprofile_iterate_data(const hsa_ven_amd_aqlprofile_profile_t* profile, - hsa_ven_amd_aqlprofile_data_callback_t callback, void* data) { - hsa_status_t status = HSA_STATUS_SUCCESS; - - try { - aql_profile::Pm4Factory* pm4_factory = aql_profile::Pm4Factory::Create(profile); - - if (profile->type == HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC) { - uint32_t info_size = 0; - void* info_data; - uint64_t* samples = (uint64_t*)profile->output_buffer.ptr; - const uint32_t sample_count = profile->output_buffer.size / sizeof(uint64_t); - uint32_t sample_index = 0; - - pm4_profile::PerfCounter* pmcMgr = pm4_factory->getPmcMgr(); - - aql_profile::EventsVec eventsVec = EventsVecCreate(profile, pm4_factory); - for (aql_profile::EventsVec::const_iterator it = eventsVec.begin(); it != eventsVec.end(); - ++it) { - const hsa_ven_amd_aqlprofile_event_t* p = *it; - const pm4_profile::CntlMethod method = pm4_factory->getBlockInfo(p)->method; - // A perfcounter data sample per ShaderEngine - const uint32_t block_samples_count = (method == pm4_profile::CntlMethodBySe || - method == pm4_profile::CntlMethodBySeAndInstance) - ? pmcMgr->getNumSe() - : 1; - for (uint32_t i = 0; i < block_samples_count; ++i) { - assert(sample_index < sample_count); - if (sample_index >= sample_count) { - ERR_LOGGING << "Bad sample index (" << sample_index << "/" << sample_count << ")"; - return HSA_STATUS_ERROR; - } - - hsa_ven_amd_aqlprofile_info_data_t sample_info; - sample_info.sample_id = i; - sample_info.pmc_data.event = *p; - sample_info.pmc_data.result = samples[sample_index]; - status = callback(HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA, &sample_info, data); - if (status == HSA_STATUS_INFO_BREAK) { - status = HSA_STATUS_SUCCESS; - break; - } - if (status != HSA_STATUS_SUCCESS) { - ERR_LOGGING << "PMC data callback error, sample_id(" << i << ") status(" << status - << ")"; - break; - } - ++sample_index; - } - } - } else if (profile->type == HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_SQTT) { - pm4_profile::ThreadTrace* sqttMgr = pm4_factory->getSqttMgr(); - aql_profile::CommandBufferMgr cmdBufMgr(profile); - - // Control buffer was allocated as the CmdBuffer postfix partition - const uint32_t status_size = sqttMgr->StatusSizeInfo(); - void* status_ptr = cmdBufMgr.setPostfix(status_size); - // Control buffer registering - sqttMgr->setSqttCtrlBuff((uint32_t*)status_ptr); - // Validate SQTT status and normalize WRPTR - if (sqttMgr->Validate() == false) { - ERR_LOGGING << "SQTT data corrupted"; - return HSA_STATUS_ERROR; - } - - const uint32_t se_number = sqttMgr->getNumSe(); - // Casting status pointer to SQTT control per ShaderEngine array - aql_profile::sqtt_ctrl_t* sqtt_ctrl = (aql_profile::sqtt_ctrl_t*)status_ptr; - const uint32_t status_size_exp = sizeof(aql_profile::sqtt_ctrl_t) * se_number; - assert(status_size == status_size_exp); - if (status_size != status_size_exp) { - ERR_LOGGING << "Bad SQTT controll data structure" - << ", status_size(" << status_size << "), status_size_exp(" << status_size_exp - << "), se_number(" << se_number << ")"; - return HSA_STATUS_ERROR; - } - // SQTT output buffer and capacity per ShaderEngine - void* sample_ptr = profile->output_buffer.ptr; - const uint32_t sample_capacity = profile->output_buffer.size / se_number; - // The samples sizes are returned in the control buffer - for (int i = 0; i < se_number; ++i) { - // WPTR specifies the index in thread trace buffer where next token will be - // written by hardware. The index is incremented by size of 32 bytes. - uint32_t sample_size = sqtt_ctrl[i].writePtr * TT_WRITE_PTR_BLK; - - hsa_ven_amd_aqlprofile_info_data_t sample_info; - sample_info.sample_id = i; - sample_info.sqtt_data.ptr = sample_ptr; - sample_info.sqtt_data.size = sample_size; - status = callback(HSA_VEN_AMD_AQLPROFILE_INFO_SQTT_DATA, &sample_info, data); - if (status == HSA_STATUS_INFO_BREAK) { - status = HSA_STATUS_SUCCESS; - break; - } - if (status != HSA_STATUS_SUCCESS) { - ERR_LOGGING << "SQTT data callback error, sample_id(" << i << ") status(" << status - << ")"; - break; - } - - sample_ptr += sample_capacity; - } - } else { - ERR_LOGGING << "Bad profile type (" << profile->type << ")"; - status = HSA_STATUS_ERROR_INVALID_ARGUMENT; - } - } catch (std::exception& e) { - ERR_LOGGING << e.what(); - return HSA_STATUS_ERROR; - } - - return status; -} -} diff --git a/runtime/hsa-amd-aqlprofile/src/core/aql_profile.h b/runtime/hsa-amd-aqlprofile/src/core/aql_profile.h deleted file mode 100644 index a7e32f6ab9..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/aql_profile.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef _AQL_PROFILE_H_ -#define _AQL_PROFILE_H_ - -#include -#include - -#include "hsa_ven_amd_aqlprofile.h" -#include "aql_profile_exception.h" - -namespace pm4_profile { -class CommandWriter; -} - -namespace aql_profile { -typedef hsa_ven_amd_aqlprofile_descriptor_t descriptor_t; -typedef hsa_ven_amd_aqlprofile_profile_t profile_t; -typedef hsa_ven_amd_aqlprofile_info_type_t info_type_t; -typedef hsa_ven_amd_aqlprofile_data_callback_t data_callback_t; -typedef hsa_ext_amd_aql_pm4_packet_t packet_t; -typedef hsa_ven_amd_aqlprofile_event_t event_t; - -void populateAql(const void* cmd_buffer, uint32_t cmd_size, pm4_profile::CommandWriter* cmd_writer, - packet_t* aql_packet); -void* legacyAqlAcquire(const packet_t* aql_packet, void* data); -void* legacyAqlRelease(const packet_t* aql_packet, void* data); -void* legacyPm4(const packet_t* aql_packet, void* data); - -class event_exception : public aql_profile_exc_val { - public: - event_exception(const std::string& m, const event_t& ev) : aql_profile_exc_val(m, ev) {} -}; - -static std::ostream& operator<<(std::ostream& os, const event_t& ev) { - os << "event( block(" << ev.block_name << "." << ev.block_index << "), Id(" << ev.counter_id - << "))"; - return os; -} -} // namespace aql_profile - -#endif // _AQL_PROFILE_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/core/aql_profile_exception.h b/runtime/hsa-amd-aqlprofile/src/core/aql_profile_exception.h deleted file mode 100644 index 210ab40ab6..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/aql_profile_exception.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _AQL_PROFILE_EXCEPTION_H_ -#define _AQL_PROFILE_EXCEPTION_H_ - -#include - -#include -#include - -namespace aql_profile { - -class aql_profile_exc_msg : public std::exception { - public: - explicit aql_profile_exc_msg(const std::string& msg) : str(msg) {} - virtual const char* what() const throw() { return str.c_str(); } - - protected: - std::string str; -}; - -template class aql_profile_exc_val : public std::exception { - public: - aql_profile_exc_val(const std::string& msg, const T& val) { - std::ostringstream oss; - oss << msg << "(" << val << ")"; - str = oss.str(); - } - virtual const char* what() const throw() { return str.c_str(); } - - protected: - std::string str; -}; -} // namespace aql_profile - -#endif // _AQL_PROFILE_EXCEPTION_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/core/gfx8_factory.cpp b/runtime/hsa-amd-aqlprofile/src/core/gfx8_factory.cpp deleted file mode 100644 index 0694e085c2..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/gfx8_factory.cpp +++ /dev/null @@ -1,50 +0,0 @@ -#include "pm4_factory.h" -// Commandwriter includes -#include "gfx8_cmdwriter.h" -// PMC includes -#include "gfx8_perf_counter.h" -// SQTT includes -#include "gfx8_thread_trace.h" -// Block info -#include "gfx8_block_info.h" - -namespace aql_profile { - -// GFX9 block ID mapping table -uint32_t Gfx8Factory::block_id_table[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER] = { - pm4_profile::kHsaViCounterBlockIdCb0, pm4_profile::kHsaViCounterBlockIdCpf, - pm4_profile::kHsaViCounterBlockIdDb0, pm4_profile::kHsaViCounterBlockIdGrbm, - pm4_profile::kHsaViCounterBlockIdGrbmSe, pm4_profile::kHsaViCounterBlockIdPaSu, - pm4_profile::kHsaViCounterBlockIdPaSc, pm4_profile::kHsaViCounterBlockIdSpi, - pm4_profile::kHsaViCounterBlockIdSq, pm4_profile::kHsaViCounterBlockIdSqEs, - pm4_profile::kHsaViCounterBlockIdSqGs, pm4_profile::kHsaViCounterBlockIdSqVs, - pm4_profile::kHsaViCounterBlockIdSqPs, pm4_profile::kHsaViCounterBlockIdSqLs, - pm4_profile::kHsaViCounterBlockIdSqHs, pm4_profile::kHsaViCounterBlockIdSqCs, - pm4_profile::kHsaViCounterBlockIdSx, pm4_profile::kHsaViCounterBlockIdTa0, - pm4_profile::kHsaViCounterBlockIdTca0, pm4_profile::kHsaViCounterBlockIdTcc0, - pm4_profile::kHsaViCounterBlockIdTd0, pm4_profile::kHsaViCounterBlockIdTcp0, - pm4_profile::kHsaViCounterBlockIdGds, pm4_profile::kHsaViCounterBlockIdVgt, - pm4_profile::kHsaViCounterBlockIdIa, pm4_profile::kHsaViCounterBlockIdMc, - pm4_profile::kHsaViCounterBlockIdSrbm, pm4_profile::kHsaViCounterBlockIdTcs, - pm4_profile::kHsaViCounterBlockIdWd, pm4_profile::kHsaViCounterBlockIdCpg, - pm4_profile::kHsaViCounterBlockIdCpc}; - -pm4_profile::CommandWriter* Gfx8Factory::getCommandWriter() { - auto p = new pm4_profile::gfx8::Gfx8CmdWriter(false, true); - if (p == NULL) throw aql_profile_exc_msg("CommandWriter allocation failed"); - return p; -} - -pm4_profile::PerfCounter* Gfx8Factory::getPmcMgr() { - auto p = new pm4_profile::Gfx8PerfCounter(); - if (p == NULL) throw aql_profile_exc_msg("PerfCounter mgr allocation failed"); - return p; -} - -pm4_profile::ThreadTrace* Gfx8Factory::getSqttMgr() { - auto p = new pm4_profile::Gfx8ThreadTrace(); - if (p == NULL) throw aql_profile_exc_msg("ThreadTrace mgr allocation failed"); - return p; -} - -} // aql_profile diff --git a/runtime/hsa-amd-aqlprofile/src/core/gfx9_factory.cpp b/runtime/hsa-amd-aqlprofile/src/core/gfx9_factory.cpp deleted file mode 100644 index c6d51a3cad..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/gfx9_factory.cpp +++ /dev/null @@ -1,65 +0,0 @@ -#include "pm4_factory.h" -// Commandwriter includes -#include "gfx9_cmdwriter.h" -// PMC includes -#include "gfx9_perf_counter.h" -// SQTT includes -#include "gfx9_thread_trace.h" -// Block info -#include "gfx9_block_info.h" - -namespace aql_profile { - -// GFX9 block ID mapping table -uint32_t Gfx9Factory::block_id_table[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER] = { - pm4_profile::kHsaAiCounterBlockIdCb0, - kBadBlockId /*CPF*/, - pm4_profile::kHsaAiCounterBlockIdDb0, - pm4_profile::kHsaAiCounterBlockIdGrbm, - pm4_profile::kHsaAiCounterBlockIdGrbmSe, - pm4_profile::kHsaAiCounterBlockIdPaSu, - pm4_profile::kHsaAiCounterBlockIdPaSc, - pm4_profile::kHsaAiCounterBlockIdSpi, - pm4_profile::kHsaAiCounterBlockIdSq, - kBadBlockId /*GFX8:SQES*/, - pm4_profile::kHsaAiCounterBlockIdSqGs, - pm4_profile::kHsaAiCounterBlockIdSqVs, - pm4_profile::kHsaAiCounterBlockIdSqPs, - kBadBlockId /*GFX8:SQLS*/, - pm4_profile::kHsaAiCounterBlockIdSqHs, - pm4_profile::kHsaAiCounterBlockIdSqCs, - pm4_profile::kHsaAiCounterBlockIdSx, - pm4_profile::kHsaAiCounterBlockIdTa0, - pm4_profile::kHsaAiCounterBlockIdTca0, - pm4_profile::kHsaAiCounterBlockIdTcc0, - pm4_profile::kHsaAiCounterBlockIdTd0, - pm4_profile::kHsaAiCounterBlockIdTcp0, - pm4_profile::kHsaAiCounterBlockIdGds, - pm4_profile::kHsaAiCounterBlockIdVgt, - pm4_profile::kHsaAiCounterBlockIdIa, - pm4_profile::kHsaAiCounterBlockIdMc, - kBadBlockId /*SRBM*/, - pm4_profile::kHsaAiCounterBlockIdTcs, - pm4_profile::kHsaAiCounterBlockIdWd, - kBadBlockId /*CPG*/, - pm4_profile::kHsaAiCounterBlockIdCpc}; - -pm4_profile::CommandWriter* Gfx9Factory::getCommandWriter() { - auto p = new pm4_profile::gfx9::Gfx9CmdWriter(false, true); - if (p == NULL) throw aql_profile_exc_msg("CommandWriter allocation failed"); - return p; -} - -pm4_profile::PerfCounter* Gfx9Factory::getPmcMgr() { - auto p = new pm4_profile::Gfx9PerfCounter(); - if (p == NULL) throw aql_profile_exc_msg("PerfCounter mgr allocation failed"); - return p; -} - -pm4_profile::ThreadTrace* Gfx9Factory::getSqttMgr() { - auto p = new pm4_profile::Gfx9ThreadTrace(); - if (p == NULL) throw aql_profile_exc_msg("ThreadTrace mgr allocation failed"); - return p; -} - -} // aql_profile diff --git a/runtime/hsa-amd-aqlprofile/src/core/legacy_pm4.cpp b/runtime/hsa-amd-aqlprofile/src/core/legacy_pm4.cpp deleted file mode 100644 index eb4044349d..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/legacy_pm4.cpp +++ /dev/null @@ -1,97 +0,0 @@ -#include -#include - -#include -#include -#include - -#include "aql_profile.h" -#include "amd_aql_pm4_ib_packet.h" -#include "gfxip/gfx8/si_pm4defs.h" -#include "gfxip/gfx8/si_ci_vi_merged_pm4_it_opcodes.h" -#include "gfxip/gfx8/si_ci_vi_merged_pm4cmds.h" - -namespace aql_profile { - -typedef uint16_t aql_packet_header_t; - -void* legacyAqlAcquire(const packet_t* aql_packet, void* data) { - hsa_barrier_and_packet_t* aql_barrier = reinterpret_cast(data); - memset(aql_barrier, 0, sizeof(hsa_barrier_and_packet_t)); - const aql_packet_header_t aql_header_type = HSA_PACKET_TYPE_BARRIER_AND << HSA_PACKET_HEADER_TYPE; - const aql_packet_header_t aql_header_barrier = 1ul << HSA_PACKET_HEADER_BARRIER; - const aql_packet_header_t aql_header_acquire = HSA_FENCE_SCOPE_SYSTEM - << HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE; - aql_barrier->header |= aql_header_type; - aql_barrier->header |= aql_header_barrier; - aql_barrier->header |= aql_header_acquire; - return data + sizeof(hsa_barrier_and_packet_t); -} - -void* legacyAqlRelease(const packet_t* aql_packet, void* data) { - hsa_barrier_and_packet_t* aql_barrier = reinterpret_cast(data); - memset(aql_barrier, 0, sizeof(hsa_barrier_and_packet_t)); - const aql_packet_header_t aql_header_type = HSA_PACKET_TYPE_BARRIER_AND << HSA_PACKET_HEADER_TYPE; - const aql_packet_header_t aql_header_barrier = 1ul << HSA_PACKET_HEADER_BARRIER; - const aql_packet_header_t aql_header_release = HSA_FENCE_SCOPE_SYSTEM - << HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE; - aql_barrier->header |= aql_header_type; - aql_barrier->header |= aql_header_barrier; - aql_barrier->header |= aql_header_release; - aql_barrier->completion_signal = aql_packet->completion_signal; - return data + sizeof(hsa_barrier_and_packet_t); -} - -void* legacyPm4(const packet_t* aql_packet, void* data) { - constexpr uint32_t major_version = 8; - constexpr uint32_t slot_size_b = 0x40; - constexpr uint32_t slot_size_dw = uint32_t(slot_size_b / sizeof(uint32_t)); - constexpr uint32_t ib_jump_size_dw = 4; - constexpr uint32_t rel_mem_size_dw = 7; - constexpr uint32_t nop_pad_size_dw = slot_size_dw - (ib_jump_size_dw + rel_mem_size_dw); - - // Construct a set of PM4 to fit inside the AQL packet slot. - const amd_aql_pm4_ib_packet_t* aql_pm4_ib = - reinterpret_cast(aql_packet); - uint32_t* const slot_data = (uint32_t*)data; - uint32_t slot_dw_idx = 0; - - // Construct a no-op command to pad the queue slot. - uint32_t* nop_pad = &slot_data[slot_dw_idx]; - slot_dw_idx += nop_pad_size_dw; - nop_pad[0] = PM4_CMD(IT_NOP, nop_pad_size_dw); - for (int i = 1; i < nop_pad_size_dw; ++i) { - nop_pad[i] = 0; - } - - // Copy in command to execute the IB. - assert(slot_dw_idx + ib_jump_size_dw <= slot_size_dw); - uint32_t* ib_jump = &slot_data[slot_dw_idx]; - slot_dw_idx += ib_jump_size_dw; - assert(ib_jump_size_dw == sizeof(aql_pm4_ib->pm4_ib_command) / sizeof(uint32_t)); - memcpy(ib_jump, aql_pm4_ib->pm4_ib_command, sizeof(aql_pm4_ib->pm4_ib_command)); - - // Construct a command to advance the read index and invalidate the packet - // header. This must be the last command since this releases the queue slot - // for writing. - assert(slot_dw_idx + rel_mem_size_dw <= slot_size_dw); - PM4CMDRELEASEMEM* rel_mem = reinterpret_cast(&slot_data[slot_dw_idx]); - assert(rel_mem_size_dw == sizeof(*rel_mem) / sizeof(uint32_t)); - memset(rel_mem, 0, sizeof(*rel_mem)); - rel_mem->ordinal1 = PM4_CMD(IT_RELEASE_MEM__CI__VI, rel_mem_size_dw); - rel_mem->eventIndex = EVENT_WRITE_INDEX_CACHE_FLUSH_EVENT; - -#if !defined(NDEBUG) - std::ostringstream oss; - oss << "AQL 'Legacy PM4' size(" << slot_size_dw << ")"; - std::clog << std::setw(40) << std::left << oss.str() << ":"; - for (int idx = 0; idx < 16; idx++) { - std::clog << " " << std::hex << std::setw(8) << std::setfill('0') << slot_data[idx]; - } - std::clog << std::setfill(' ') << std::endl; -#endif - - return data + slot_size_b; -} - -} // aql_profile diff --git a/runtime/hsa-amd-aqlprofile/src/core/logger.h b/runtime/hsa-amd-aqlprofile/src/core/logger.h deleted file mode 100644 index 5e7c8bbaab..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/logger.h +++ /dev/null @@ -1,137 +0,0 @@ -#ifndef _LOGGER_H_ -#define _LOGGER_H_ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -namespace aql_profile { - -class Logger { - public: - template Logger& operator<<(const T& m) { - std::ostringstream oss; - oss << m; - if (!streaming) - log(oss.str()); - else - put(oss.str()); - streaming = true; - return *this; - } - - typedef void (Logger::*manip_t)(); - Logger& operator<<(manip_t f) { - (this->*f)(); - return *this; - } - - void begm() { messaging = true; } - void endl() { resetStreaming(); } - - static const std::string& LastMessage() { - Logger& logger = Instance(); - std::lock_guard lck(mutex); - return logger.message[GetTid()]; - } - - static Logger& Instance() { - std::lock_guard lck(mutex); - if (instance == NULL) instance = new Logger(); - return *instance; - } - - static void Destroy() { - std::lock_guard lck(mutex); - if (instance != NULL) delete instance; - instance = NULL; - } - - private: - static uint32_t GetPid() { return syscall(__NR_getpid); } - static uint32_t GetTid() { return syscall(__NR_gettid); } - - Logger() : file(NULL), dirty(false), streaming(false), messaging(false) { - const char* path = getenv("HSA_VEN_AMD_AQLPROFILE_LOG"); - if (path != NULL) { - file = fopen("/tmp/aql_profile_log.txt", "a"); - } - resetStreaming(); - } - - ~Logger() { - if (file != NULL) { - if (dirty) put("\n"); - fclose(file); - } - } - - void resetStreaming() { - std::lock_guard lck(mutex); - if (messaging) { - message[GetTid()] = ""; - } - messaging = false; - streaming = false; - } - - void put(const std::string& m) { - std::lock_guard lck(mutex); - if (messaging) { - message[GetTid()] += m; - } - if (file != NULL) { - dirty = true; - flock(fileno(file), LOCK_EX); - fprintf(file, "%s", m.c_str()); - fflush(file); - flock(fileno(file), LOCK_UN); - } - } - - void log(const std::string& m) { - const time_t rawtime = time(NULL); - tm tm_info; - localtime_r(&rawtime, &tm_info); - char tm_str[26]; - strftime(tm_str, 26, "%Y-%m-%d %H:%M:%S", &tm_info); - std::ostringstream oss; - oss << "\n<" << tm_str << std::dec << " pid" << GetPid() << " tid" << GetTid() << "> " << m; - put(oss.str()); - } - - FILE* file; - bool dirty; - bool streaming; - bool messaging; - - static std::mutex mutex; - static Logger* instance; - std::map message; -}; - -} // namespace aql_profile - -#define ERR_LOGGING \ - (aql_profile::Logger::Instance() << aql_profile::Logger::endl \ - << "Error: " << __FUNCTION__ \ - << "(): " << aql_profile::Logger::begm) -#define INFO_LOGGING \ - (aql_profile::Logger::Instance() << aql_profile::Logger::endl \ - << "Info: " << __FUNCTION__ \ - << "(): " << aql_profile::Logger::begm) - -#endif // _LOGGER_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/core/pm4_factory.h b/runtime/hsa-amd-aqlprofile/src/core/pm4_factory.h deleted file mode 100644 index 0e8b320d0f..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/pm4_factory.h +++ /dev/null @@ -1,157 +0,0 @@ -#ifndef _PM4_FACTORY_H_ -#define _PM4_FACTORY_H_ - -#include -#include -#include - -#include -#include -#include -#include - -#include "aql_profile.h" -#include "gpu_block_info.h" -#include "aql_profile_exception.h" - -namespace pm4_profile { -class CommandWriter; -class PerfCounter; -class ThreadTrace; -extern GpuBlockInfo Gfx9HwBlocks[]; -extern const uint32_t Gfx9HwBlockCount; -extern GpuBlockInfo Gfx8HwBlocks[]; -extern const uint32_t Gfx8HwBlockCount; -} - -namespace aql_profile { - -class BlockMap { - public: - typedef std::map map_t; - typedef map_t::const_iterator iter_t; - - void init(uint32_t* id_table, pm4_profile::GpuBlockInfo* info_table, const uint32_t& info_count) { - if (block_map.size() == 0) fill(id_table, info_table, info_count); - } - - const pm4_profile::GpuBlockInfo* get(const uint32_t& id) const { - iter_t it = block_map.find(id); - return (it != block_map.end()) ? it->second : NULL; - } - - private: - void fill(uint32_t* id_table, pm4_profile::GpuBlockInfo* info_table, const uint32_t& info_count) { - map_t info_map; - for (uint32_t i = 0; i < info_count; ++i) { - const pm4_profile::GpuBlockInfo& entry = info_table[i]; - info_map[entry.counterGroupId] = &entry; - } - for (uint32_t i = 0; i < HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER; ++i) { - iter_t it = info_map.find(id_table[i]); - if (it != info_map.end()) block_map[i] = it->second; - } - } - - map_t block_map; -}; - -class Pm4Factory { - public: - enum { kBadBlockId = UINT_MAX }; - - static Pm4Factory* Create(const hsa_agent_t agent); - static Pm4Factory* Create(const profile_t* profile) { return Create(profile->agent); } - static void Destroy(); - - virtual pm4_profile::CommandWriter* getCommandWriter() = 0; - virtual pm4_profile::PerfCounter* getPmcMgr() = 0; - virtual pm4_profile::ThreadTrace* getSqttMgr() = 0; - - const pm4_profile::GpuBlockInfo* getBlockInfo(const event_t* event) const { - const pm4_profile::GpuBlockInfo* info = block_map.get(event->block_name); - if (info == NULL) throw event_exception(std::string("Bad block, "), *event); - if (event->block_index >= info->maxInstanceCount) - throw event_exception(std::string("Bad block index, "), *event); - if (event->counter_id > info->maxEventId) - throw event_exception(std::string("Bad event ID, "), *event); - return info; - } - - uint32_t getBlockId(const event_t* event) const { - return getBlockInfo(event)->counterGroupId + event->block_index; - } - - protected: - explicit Pm4Factory(const BlockMap& map) : block_map(map) {} - virtual ~Pm4Factory() {} - - private: - typedef std::map instances_t; - - static std::mutex mutex; - static instances_t instances; - const BlockMap& block_map; -}; - -class Gfx8Factory : public Pm4Factory { - public: - Gfx8Factory() : Pm4Factory(block_map) { - block_map.init(block_id_table, pm4_profile::Gfx8HwBlocks, pm4_profile::Gfx8HwBlockCount); - } - pm4_profile::CommandWriter* getCommandWriter(); - pm4_profile::PerfCounter* getPmcMgr(); - pm4_profile::ThreadTrace* getSqttMgr(); - - private: - static uint32_t block_id_table[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER]; - BlockMap block_map; -}; - -class Gfx9Factory : public Pm4Factory { - public: - Gfx9Factory() : Pm4Factory(block_map) { - block_map.init(block_id_table, pm4_profile::Gfx9HwBlocks, pm4_profile::Gfx9HwBlockCount); - } - pm4_profile::CommandWriter* getCommandWriter(); - pm4_profile::PerfCounter* getPmcMgr(); - pm4_profile::ThreadTrace* getSqttMgr(); - - private: - static uint32_t block_id_table[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER]; - BlockMap block_map; -}; - -inline Pm4Factory* Pm4Factory::Create(const hsa_agent_t agent) { - std::lock_guard lck(mutex); - - char agent_name[64]; - hsa_agent_get_info(agent, HSA_AGENT_INFO_NAME, agent_name); - instances_t::iterator it = instances.find(agent_name); - - if (it == instances.end()) { - if (strncmp(agent_name, "gfx801", 6) == 0) { - throw aql_profile_exc_val(std::string("GFX8 Carrizo is not supported "), - agent_name); - } else if (strncmp(agent_name, "gfx8", 4) == 0) { - it->second = new Gfx8Factory(); - } else if (strncmp(agent_name, "gfx9", 4) == 0) { - it->second = new Gfx9Factory(); - } else { - throw aql_profile_exc_val("Unsupported GFXIP", agent_name); - } - } - - if (it->second == NULL) throw aql_profile_exc_msg("Pm4Factory allocation failed"); - return it->second; -} - -inline void Pm4Factory::Destroy() { - std::lock_guard lck(mutex); - for (auto it : instances) delete it.second; - instances.clear(); -} - -} // namespace aql_profile - -#endif // _PM4_FACTORY_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/core/populate_aql.cpp b/runtime/hsa-amd-aqlprofile/src/core/populate_aql.cpp deleted file mode 100644 index 502b84b780..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/core/populate_aql.cpp +++ /dev/null @@ -1,49 +0,0 @@ -#include - -#include -#include -#include - -#include "aql_profile.h" -#include "cmdwriter.h" -#include "amd_aql_pm4_ib_packet.h" - -namespace aql_profile { - -void populateAql(const uint32_t* ib_packet, packet_t* aql_packet) { - // Populate relevant fields of Aql pkt - // Size of IB pkt is four DWords - // Header and completion sinal are not set - amd_aql_pm4_ib_packet_t* aql_pm4_ib = reinterpret_cast(aql_packet); - aql_pm4_ib->pm4_ib_format = AMD_AQL_PM4_IB_FORMAT; - aql_pm4_ib->pm4_ib_command[0] = ib_packet[0]; - aql_pm4_ib->pm4_ib_command[1] = ib_packet[1]; - aql_pm4_ib->pm4_ib_command[2] = ib_packet[2]; - aql_pm4_ib->pm4_ib_command[3] = ib_packet[3]; - aql_pm4_ib->dw_count_remain = AMD_AQL_PM4_IB_DW_COUNT_REMAIN; - for (int i = 0; i < AMD_AQL_PM4_IB_RESERVED_COUNT; ++i) { - aql_pm4_ib->reserved[i] = 0; - } - -#if !defined(NDEBUG) - const uint32_t* dwords = (uint32_t*)aql_packet; - const uint32_t dword_count = sizeof(*aql_packet) / sizeof(uint32_t); - std::ostringstream oss; - oss << "AQL 'IB' size(" << dword_count << ")"; - std::clog << std::setw(40) << std::left << "AQL 'IB' size(16)" - << ":"; - for (int idx = 0; idx < dword_count; idx++) { - std::clog << " " << std::hex << std::setw(8) << std::setfill('0') << dwords[idx]; - } - std::clog << std::setfill(' ') << std::endl; -#endif -} - -void populateAql(const void* cmd_buffer, uint32_t cmd_size, pm4_profile::CommandWriter* cmd_writer, - packet_t* aql_packet) { - pm4_profile::DefaultCmdBuf ib_buffer; - cmd_writer->BuildIndirectBufferCmd(&ib_buffer, cmd_buffer, (size_t)cmd_size); - populateAql((const uint32_t*)ib_buffer.Base(), aql_packet); -} - -} // aql_profile diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/CMakeLists.txt b/runtime/hsa-amd-aqlprofile/src/perfcounter/CMakeLists.txt deleted file mode 100644 index 1f8b81d95e..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# -# Source files for Rocr PerfCntr -# -set ( LIB_SRC gfx8_perf_counter.cpp ) -set ( LIB_SRC ${LIB_SRC} gfx9_perf_counter.cpp ) -set ( LIB_SRC ${LIB_SRC} gfx8_block_info.cpp ) -set ( LIB_SRC ${LIB_SRC} gfx9_block_info.cpp ) - -# -# Header files include path(s). -# -include_directories ( ${PROJ_DIR}/commandwriter ) - -# -# Build PerfCntr as a Static Library object -# -add_library ( ${PMC_LIB} STATIC ${LIB_SRC} ) diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_block_info.cpp b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_block_info.cpp deleted file mode 100644 index 4093b28c3e..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_block_info.cpp +++ /dev/null @@ -1,624 +0,0 @@ -#include "gfx8_block_info.h" -#include "gfxip/gfx8/si_ci_vi_merged_offset.h" - -namespace pm4_profile { -/** - * Table containing CounterGroups which represent VI hardware blocks - * as defined by \ref GpuBlockInfo structure - */ -GpuBlockInfo Gfx8HwBlocks[] = { - // Counter block CB - {"VI_CB0", kHsaViCounterBlockIdCb0, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_CB, - CntlMethodBySeAndInstance, 395, VI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_CB1", kHsaViCounterBlockIdCb1, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_CB, - CntlMethodBySeAndInstance, 395, VI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_CB2", kHsaViCounterBlockIdCb2, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_CB, - CntlMethodBySeAndInstance, 395, VI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_CB3", kHsaViCounterBlockIdCb3, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_CB, - CntlMethodBySeAndInstance, 395, VI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block CPF - {"VI_CPF", kHsaViCounterBlockIdCpf, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 19, - VI_COUNTER_NUM_PER_CPF, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block DB - {"VI_DB0", kHsaViCounterBlockIdDb0, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_DB, - CntlMethodBySeAndInstance, 256, VI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_DB1", kHsaViCounterBlockIdDb1, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_DB, - CntlMethodBySeAndInstance, 256, VI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_DB2", kHsaViCounterBlockIdDb2, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_DB, - CntlMethodBySeAndInstance, 256, VI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_DB3", kHsaViCounterBlockIdDb3, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_DB, - CntlMethodBySeAndInstance, 256, VI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block GRBM - {"VI_GRBM", kHsaViCounterBlockIdGrbm, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 33, - VI_COUNTER_NUM_PER_GRBM, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block GRBMSE - {"VI_GRBMSE", kHsaViCounterBlockIdGrbmSe, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 14, - VI_COUNTER_NUM_PER_GRBMSE, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block PA_SU - {"VI_PA_SU", kHsaViCounterBlockIdPaSu, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 152, - VI_COUNTER_NUM_PER_PA_SU, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block PA_SC - {"VI_PA_SC", kHsaViCounterBlockIdPaSc, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 396, - VI_COUNTER_NUM_PER_PA_SC, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block SPI - {"VI_SPI", kHsaViCounterBlockIdSpi, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 196, - VI_COUNTER_NUM_PER_SPI, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block SQ - {"VI_SQ", kHsaViCounterBlockIdSq, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_SQ_ES", kHsaViCounterBlockIdSqEs, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_SQ_GS", kHsaViCounterBlockIdSqGs, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_SQ_VS", kHsaViCounterBlockIdSqVs, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_SQ_PS", kHsaViCounterBlockIdSqPs, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_SQ_LS", kHsaViCounterBlockIdSqLs, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_SQ_HS", kHsaViCounterBlockIdSqHs, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_SQ_CS", kHsaViCounterBlockIdSqCs, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - VI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block SX - {"VI_SX", kHsaViCounterBlockIdSx, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 33, - VI_COUNTER_NUM_PER_SX, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TA - {"VI_TA0", kHsaViCounterBlockIdTa0, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA1", kHsaViCounterBlockIdTa1, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA2", kHsaViCounterBlockIdTa2, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA3", kHsaViCounterBlockIdTa3, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA4", kHsaViCounterBlockIdTa4, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA5", kHsaViCounterBlockIdTa5, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA6", kHsaViCounterBlockIdTa6, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA7", kHsaViCounterBlockIdTa7, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA8", kHsaViCounterBlockIdTa8, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA9", kHsaViCounterBlockIdTa9, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA10", kHsaViCounterBlockIdTa10, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA11", kHsaViCounterBlockIdTa11, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA12", kHsaViCounterBlockIdTa12, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA13", kHsaViCounterBlockIdTa13, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA14", kHsaViCounterBlockIdTa14, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TA15", kHsaViCounterBlockIdTa15, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TA, - CntlMethodBySeAndInstance, 118, VI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TCA - {"VI_TCA0", kHsaViCounterBlockIdTca0, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCA, - CntlMethodByInstance, 34, VI_COUNTER_NUM_PER_TCA, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCA1", kHsaViCounterBlockIdTca1, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCA, - CntlMethodByInstance, 34, VI_COUNTER_NUM_PER_TCA, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TCC - {"VI_TCC0", kHsaViCounterBlockIdTcc0, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC1", kHsaViCounterBlockIdTcc1, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC2", kHsaViCounterBlockIdTcc2, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC3", kHsaViCounterBlockIdTcc3, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC4", kHsaViCounterBlockIdTcc4, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC5", kHsaViCounterBlockIdTcc5, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC6", kHsaViCounterBlockIdTcc6, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC7", kHsaViCounterBlockIdTcc7, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC8", kHsaViCounterBlockIdTcc8, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC9", kHsaViCounterBlockIdTcc9, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC10", kHsaViCounterBlockIdTcc10, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC11", kHsaViCounterBlockIdTcc11, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC12", kHsaViCounterBlockIdTcc12, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC13", kHsaViCounterBlockIdTcc13, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC14", kHsaViCounterBlockIdTcc14, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCC15", kHsaViCounterBlockIdTcc15, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCC, - CntlMethodByInstance, 191, VI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TD - {"VI_TD0", kHsaViCounterBlockIdTd0, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD1", kHsaViCounterBlockIdTd1, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD2", kHsaViCounterBlockIdTd2, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD3", kHsaViCounterBlockIdTd3, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD4", kHsaViCounterBlockIdTd4, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD5", kHsaViCounterBlockIdTd5, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD6", kHsaViCounterBlockIdTd6, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD7", kHsaViCounterBlockIdTd7, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD8", kHsaViCounterBlockIdTd8, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD9", kHsaViCounterBlockIdTd9, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD10", kHsaViCounterBlockIdTd10, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD11", kHsaViCounterBlockIdTd11, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD12", kHsaViCounterBlockIdTd12, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD13", kHsaViCounterBlockIdTd13, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD14", kHsaViCounterBlockIdTd14, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TD15", kHsaViCounterBlockIdTd15, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TD, - CntlMethodBySeAndInstance, 54, VI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TCP - {"VI_TCP0", kHsaViCounterBlockIdTcp0, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP1", kHsaViCounterBlockIdTcp1, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP2", kHsaViCounterBlockIdTcp2, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP3", kHsaViCounterBlockIdTcp3, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP4", kHsaViCounterBlockIdTcp4, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP5", kHsaViCounterBlockIdTcp5, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP6", kHsaViCounterBlockIdTcp6, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP7", kHsaViCounterBlockIdTcp7, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP8", kHsaViCounterBlockIdTcp8, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP9", kHsaViCounterBlockIdTcp9, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP10", kHsaViCounterBlockIdTcp10, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP11", kHsaViCounterBlockIdTcp11, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP12", kHsaViCounterBlockIdTcp12, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP13", kHsaViCounterBlockIdTcp13, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP14", kHsaViCounterBlockIdTcp14, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"VI_TCP15", kHsaViCounterBlockIdTcp15, VI_MAX_NUM_SHADER_ENGINES, 2, VI_NUM_TCP, - CntlMethodBySeAndInstance, 182, VI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block GDS - {"VI_GDS", kHsaViCounterBlockIdGds, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 120, - VI_COUNTER_NUM_PER_GDS, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block VGT - {"VI_VGT", kHsaViCounterBlockIdVgt, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 145, - VI_COUNTER_NUM_PER_VGT, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block IA - {"VI_IA", kHsaViCounterBlockIdIa, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 23, - VI_COUNTER_NUM_PER_IA, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block MC - {"VI_MC", kHsaViCounterBlockIdMc, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 22, - VI_COUNTER_NUM_PER_MC, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block SRBM - {"VI_SRBM", kHsaViCounterBlockIdSrbm, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 19, - VI_COUNTER_NUM_PER_SRBM, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block WD - {"VI_WD", kHsaViCounterBlockIdWd, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 36, - VI_COUNTER_NUM_PER_WD, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block CPG - {"VI_CPG", kHsaViCounterBlockIdCpg, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 48, - VI_COUNTER_NUM_PER_CPG, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block CPC - {"VI_CPC", kHsaViCounterBlockIdCpc, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 24, - VI_COUNTER_NUM_PER_CPC, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block IOMMUV2 - {"VI_IOMMUV2", kHsaViCounterBlockIdIommuV2, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 25, - 8, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block KernelDriver - {"VI_KD", kHsaViCounterBlockIdKernelDriver, VI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 0, - 0, 0, 0, true, 0, 0, false, 0, 0}, - - // Name of the last line should be empty to indicate end of all counter groups - {"", kHsaViCounterBlockIdBlocksLast, 0, 0, 0, CntlMethodNone, 0, 0, 0, 0, false, 0, 0, false, 0, - 0}}; - -extern const uint32_t Gfx8HwBlockCount = sizeof(Gfx8HwBlocks) / sizeof(GpuBlockInfo); - -/* - * The following tables contain register addresses of the SQ counter registers - */ - -/* - * SQ - */ -GpuCounterRegInfo ViSqCounterRegAddr[] = { - {mmSQ_PERFCOUNTER0_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER0_LO__CI__VI, - mmSQ_PERFCOUNTER0_HI__CI__VI}, - {mmSQ_PERFCOUNTER1_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER1_LO__CI__VI, - mmSQ_PERFCOUNTER1_HI__CI__VI}, - {mmSQ_PERFCOUNTER2_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER2_LO__CI__VI, - mmSQ_PERFCOUNTER2_HI__CI__VI}, - {mmSQ_PERFCOUNTER3_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER3_LO__CI__VI, - mmSQ_PERFCOUNTER3_HI__CI__VI}, - {mmSQ_PERFCOUNTER4_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER4_LO__CI__VI, - mmSQ_PERFCOUNTER4_HI__CI__VI}, - {mmSQ_PERFCOUNTER5_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER5_LO__CI__VI, - mmSQ_PERFCOUNTER5_HI__CI__VI}, - {mmSQ_PERFCOUNTER6_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER6_LO__CI__VI, - mmSQ_PERFCOUNTER6_HI__CI__VI}, - {mmSQ_PERFCOUNTER7_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER7_LO__CI__VI, - mmSQ_PERFCOUNTER7_HI__CI__VI}, - {mmSQ_PERFCOUNTER8_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER8_LO__CI__VI, - mmSQ_PERFCOUNTER8_HI__CI__VI}, - {mmSQ_PERFCOUNTER9_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, mmSQ_PERFCOUNTER9_LO__CI__VI, - mmSQ_PERFCOUNTER9_HI__CI__VI}, - {mmSQ_PERFCOUNTER10_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, - mmSQ_PERFCOUNTER10_LO__CI__VI, mmSQ_PERFCOUNTER10_HI__CI__VI}, - {mmSQ_PERFCOUNTER11_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, - mmSQ_PERFCOUNTER11_LO__CI__VI, mmSQ_PERFCOUNTER11_HI__CI__VI}, - {mmSQ_PERFCOUNTER12_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, - mmSQ_PERFCOUNTER12_LO__CI__VI, mmSQ_PERFCOUNTER12_HI__CI__VI}, - {mmSQ_PERFCOUNTER13_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, - mmSQ_PERFCOUNTER13_LO__CI__VI, mmSQ_PERFCOUNTER13_HI__CI__VI}, - {mmSQ_PERFCOUNTER14_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, - mmSQ_PERFCOUNTER14_LO__CI__VI, mmSQ_PERFCOUNTER14_HI__CI__VI}, - {mmSQ_PERFCOUNTER15_SELECT__CI__VI, mmSQ_PERFCOUNTER_CTRL__CI__VI, - mmSQ_PERFCOUNTER15_LO__CI__VI, mmSQ_PERFCOUNTER15_HI__CI__VI}}; - -/* - * DRMDMA - */ -GpuCounterRegInfo ViDrmdmaCounterRegAddr[] = { - {mmSDMA0_PERFMON_CNTL__VI, 0, mmSDMA0_PERFCOUNTER0_RESULT__VI, 0}, - {mmSDMA0_PERFMON_CNTL__VI, 0, mmSDMA0_PERFCOUNTER1_RESULT__VI, 0}, - {mmSDMA1_PERFMON_CNTL__VI, 0, mmSDMA1_PERFCOUNTER0_RESULT__VI, 0}, - {mmSDMA1_PERFMON_CNTL__VI, 0, mmSDMA1_PERFCOUNTER1_RESULT__VI, 0}, -}; - -/* - * IH - */ -GpuCounterRegInfo ViIhCounterRegAddr[] = { - {mmIH_PERFMON_CNTL__VI, 0, mmIH_PERFCOUNTER0_RESULT__VI, 0}, - {mmIH_PERFMON_CNTL__VI, 0, mmIH_PERFCOUNTER1_RESULT__VI, 0}}; - -/* - * CPF - */ -GpuCounterRegInfo ViCpfCounterRegAddr[] = { - {mmCPF_PERFCOUNTER0_SELECT__CI__VI, 0, mmCPF_PERFCOUNTER0_LO__CI__VI, - mmCPF_PERFCOUNTER0_HI__CI__VI}, - {mmCPF_PERFCOUNTER1_SELECT__CI__VI, 0, mmCPF_PERFCOUNTER1_LO__CI__VI, - mmCPF_PERFCOUNTER1_HI__CI__VI}}; - -/* - * DRM - */ -GpuCounterRegInfo ViDrmCounterRegAddr[] = { - {mmDRM_PERFCOUNTER1_SELECT, 0, mmDRM_PERFCOUNTER1_LO, mmDRM_PERFCOUNTER1_HI}, - {mmDRM_PERFCOUNTER2_SELECT, 0, mmDRM_PERFCOUNTER2_LO, mmDRM_PERFCOUNTER2_HI}}; - -/* - * GRBM - */ -GpuCounterRegInfo ViGrbmCounterRegAddr[] = { - {mmGRBM_PERFCOUNTER0_SELECT__CI__VI, 0, mmGRBM_PERFCOUNTER0_LO__CI__VI, - mmGRBM_PERFCOUNTER0_HI__CI__VI}, - {mmGRBM_PERFCOUNTER1_SELECT__CI__VI, 0, mmGRBM_PERFCOUNTER1_LO__CI__VI, - mmGRBM_PERFCOUNTER1_HI__CI__VI}}; - -/* - * GRBM_SE - */ -GpuCounterRegInfo ViGrbmSeCounterRegAddr[] = { - {mmGRBM_SE0_PERFCOUNTER_SELECT__CI__VI, 0, mmGRBM_SE0_PERFCOUNTER_LO__CI__VI, - mmGRBM_SE0_PERFCOUNTER_HI__CI__VI}, - {mmGRBM_SE1_PERFCOUNTER_SELECT__CI__VI, 0, mmGRBM_SE1_PERFCOUNTER_LO__CI__VI, - mmGRBM_SE1_PERFCOUNTER_HI__CI__VI}, - {mmGRBM_SE2_PERFCOUNTER_SELECT__CI__VI, 0, mmGRBM_SE2_PERFCOUNTER_LO__CI__VI, - mmGRBM_SE2_PERFCOUNTER_HI__CI__VI}, - {mmGRBM_SE3_PERFCOUNTER_SELECT__CI__VI, 0, mmGRBM_SE3_PERFCOUNTER_LO__CI__VI, - mmGRBM_SE3_PERFCOUNTER_HI__CI__VI}}; - -/* - * PA_SU - */ -GpuCounterRegInfo ViPaSuCounterRegAddr[] = { - {mmPA_SU_PERFCOUNTER0_SELECT__CI__VI, 0, mmPA_SU_PERFCOUNTER0_LO__CI__VI, - mmPA_SU_PERFCOUNTER0_HI__CI__VI}, - {mmPA_SU_PERFCOUNTER1_SELECT__CI__VI, 0, mmPA_SU_PERFCOUNTER1_LO__CI__VI, - mmPA_SU_PERFCOUNTER1_HI__CI__VI}, - {mmPA_SU_PERFCOUNTER2_SELECT__CI__VI, 0, mmPA_SU_PERFCOUNTER2_LO__CI__VI, - mmPA_SU_PERFCOUNTER2_HI__CI__VI}, - {mmPA_SU_PERFCOUNTER3_SELECT__CI__VI, 0, mmPA_SU_PERFCOUNTER3_LO__CI__VI, - mmPA_SU_PERFCOUNTER3_HI__CI__VI}}; - -/* - * PA_SC - */ -GpuCounterRegInfo ViPaScCounterRegAddr[] = { - {mmPA_SC_PERFCOUNTER0_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER0_LO__CI__VI, - mmPA_SC_PERFCOUNTER0_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER1_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER1_LO__CI__VI, - mmPA_SC_PERFCOUNTER1_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER2_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER2_LO__CI__VI, - mmPA_SC_PERFCOUNTER2_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER3_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER3_LO__CI__VI, - mmPA_SC_PERFCOUNTER3_HI__CI__VI}}; - -/* - * SPI - */ -GpuCounterRegInfo ViSpiCounterRegAddr[] = { - {mmSPI_PERFCOUNTER0_SELECT__CI__VI, 0, mmSPI_PERFCOUNTER0_LO__CI__VI, - mmSPI_PERFCOUNTER0_HI__CI__VI}, - {mmSPI_PERFCOUNTER1_SELECT__CI__VI, 0, mmSPI_PERFCOUNTER1_LO__CI__VI, - mmSPI_PERFCOUNTER1_HI__CI__VI}, - {mmSPI_PERFCOUNTER2_SELECT__CI__VI, 0, mmSPI_PERFCOUNTER2_LO__CI__VI, - mmSPI_PERFCOUNTER2_HI__CI__VI}, - {mmSPI_PERFCOUNTER3_SELECT__CI__VI, 0, mmSPI_PERFCOUNTER3_LO__CI__VI, - mmSPI_PERFCOUNTER3_HI__CI__VI}, - {mmSPI_PERFCOUNTER4_SELECT__CI__VI, 0, mmSPI_PERFCOUNTER4_LO__CI__VI, - mmSPI_PERFCOUNTER4_HI__CI__VI}, - {mmSPI_PERFCOUNTER5_SELECT__CI__VI, 0, mmSPI_PERFCOUNTER5_LO__CI__VI, - mmSPI_PERFCOUNTER5_HI__CI__VI}}; - -/* - * TCA - */ -GpuCounterRegInfo ViTcaCounterRegAddr[] = { - {mmTCA_PERFCOUNTER0_SELECT__CI__VI, 0, mmTCA_PERFCOUNTER0_LO__CI__VI, - mmTCA_PERFCOUNTER0_HI__CI__VI}, - {mmTCA_PERFCOUNTER1_SELECT__CI__VI, 0, mmTCA_PERFCOUNTER1_LO__CI__VI, - mmTCA_PERFCOUNTER1_HI__CI__VI}, - {mmTCA_PERFCOUNTER2_SELECT__CI__VI, 0, mmTCA_PERFCOUNTER2_LO__CI__VI, - mmTCA_PERFCOUNTER2_HI__CI__VI}, - {mmTCA_PERFCOUNTER3_SELECT__CI__VI, 0, mmTCA_PERFCOUNTER3_LO__CI__VI, - mmTCA_PERFCOUNTER3_HI__CI__VI}}; - -/* - * TCC - */ -GpuCounterRegInfo ViTccCounterRegAddr[] = { - {mmTCC_PERFCOUNTER0_SELECT__CI__VI, 0, mmTCC_PERFCOUNTER0_LO__CI__VI, - mmTCC_PERFCOUNTER0_HI__CI__VI}, - {mmTCC_PERFCOUNTER1_SELECT__CI__VI, 0, mmTCC_PERFCOUNTER1_LO__CI__VI, - mmTCC_PERFCOUNTER1_HI__CI__VI}, - {mmTCC_PERFCOUNTER2_SELECT__CI__VI, 0, mmTCC_PERFCOUNTER2_LO__CI__VI, - mmTCC_PERFCOUNTER2_HI__CI__VI}, - {mmTCC_PERFCOUNTER3_SELECT__CI__VI, 0, mmTCC_PERFCOUNTER3_LO__CI__VI, - mmTCC_PERFCOUNTER3_HI__CI__VI}}; - -/* - * TCP - */ -GpuCounterRegInfo ViTcpCounterRegAddr[] = { - {mmTCP_PERFCOUNTER0_SELECT__CI__VI, 0, mmTCP_PERFCOUNTER0_LO__CI__VI, - mmTCP_PERFCOUNTER0_HI__CI__VI}, - {mmTCP_PERFCOUNTER1_SELECT__CI__VI, 0, mmTCP_PERFCOUNTER1_LO__CI__VI, - mmTCP_PERFCOUNTER1_HI__CI__VI}, - {mmTCP_PERFCOUNTER2_SELECT__CI__VI, 0, mmTCP_PERFCOUNTER2_LO__CI__VI, - mmTCP_PERFCOUNTER2_HI__CI__VI}, - {mmTCP_PERFCOUNTER3_SELECT__CI__VI, 0, mmTCP_PERFCOUNTER3_LO__CI__VI, - mmTCP_PERFCOUNTER3_HI__CI__VI}}; - -/* - * CB - */ -GpuCounterRegInfo ViCbCounterRegAddr[] = { - {mmCB_PERFCOUNTER0_SELECT__CI__VI, 0, mmCB_PERFCOUNTER0_LO__CI__VI, - mmCB_PERFCOUNTER0_HI__CI__VI}, - {mmCB_PERFCOUNTER1_SELECT__CI__VI, 0, mmCB_PERFCOUNTER1_LO__CI__VI, - mmCB_PERFCOUNTER1_HI__CI__VI}, - {mmCB_PERFCOUNTER2_SELECT__CI__VI, 0, mmCB_PERFCOUNTER2_LO__CI__VI, - mmCB_PERFCOUNTER2_HI__CI__VI}, - {mmCB_PERFCOUNTER3_SELECT__CI__VI, 0, mmCB_PERFCOUNTER3_LO__CI__VI, - mmCB_PERFCOUNTER3_HI__CI__VI}}; - -/* - * DB - */ -GpuCounterRegInfo ViDbCounterRegAddr[] = { - {mmDB_PERFCOUNTER0_SELECT__CI__VI, 0, mmDB_PERFCOUNTER0_LO__CI__VI, - mmDB_PERFCOUNTER0_HI__CI__VI}, - {mmDB_PERFCOUNTER1_SELECT__CI__VI, 0, mmDB_PERFCOUNTER1_LO__CI__VI, - mmDB_PERFCOUNTER1_HI__CI__VI}, - {mmDB_PERFCOUNTER2_SELECT__CI__VI, 0, mmDB_PERFCOUNTER2_LO__CI__VI, - mmDB_PERFCOUNTER2_HI__CI__VI}, - {mmDB_PERFCOUNTER3_SELECT__CI__VI, 0, mmDB_PERFCOUNTER3_LO__CI__VI, - mmDB_PERFCOUNTER3_HI__CI__VI}}; - -/* - * RLC - */ -GpuCounterRegInfo ViRlcCounterRegAddr[] = { - {mmRLC_PERFCOUNTER0_SELECT__CI__VI, 0, mmRLC_PERFCOUNTER0_LO__CI__VI, - mmRLC_PERFCOUNTER0_HI__CI__VI}, - {mmRLC_PERFCOUNTER1_SELECT__CI__VI, 0, mmRLC_PERFCOUNTER1_LO__CI__VI, - mmRLC_PERFCOUNTER1_HI__CI__VI}}; - -/* - * SC - */ -GpuCounterRegInfo ViScCounterRegAddr[] = { - {mmPA_SC_PERFCOUNTER0_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER0_LO__CI__VI, - mmPA_SC_PERFCOUNTER0_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER1_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER1_LO__CI__VI, - mmPA_SC_PERFCOUNTER1_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER2_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER2_LO__CI__VI, - mmPA_SC_PERFCOUNTER2_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER3_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER3_LO__CI__VI, - mmPA_SC_PERFCOUNTER3_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER4_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER4_LO__CI__VI, - mmPA_SC_PERFCOUNTER4_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER5_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER5_LO__CI__VI, - mmPA_SC_PERFCOUNTER5_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER6_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER6_LO__CI__VI, - mmPA_SC_PERFCOUNTER6_HI__CI__VI}, - {mmPA_SC_PERFCOUNTER7_SELECT__CI__VI, 0, mmPA_SC_PERFCOUNTER7_LO__CI__VI, - mmPA_SC_PERFCOUNTER7_HI__CI__VI}}; - -/* - * SX - */ -GpuCounterRegInfo ViSxCounterRegAddr[] = { - {mmSX_PERFCOUNTER0_SELECT__CI__VI, 0, mmSX_PERFCOUNTER0_LO__CI__VI, - mmSX_PERFCOUNTER0_HI__CI__VI}, - {mmSX_PERFCOUNTER1_SELECT__CI__VI, 0, mmSX_PERFCOUNTER1_LO__CI__VI, - mmSX_PERFCOUNTER1_HI__CI__VI}, - {mmSX_PERFCOUNTER2_SELECT__CI__VI, 0, mmSX_PERFCOUNTER2_LO__CI__VI, - mmSX_PERFCOUNTER2_HI__CI__VI}, - {mmSX_PERFCOUNTER3_SELECT__CI__VI, 0, mmSX_PERFCOUNTER3_LO__CI__VI, - mmSX_PERFCOUNTER3_HI__CI__VI}}; - -/* - * TA - */ -GpuCounterRegInfo ViTaCounterRegAddr[] = { - {mmTA_PERFCOUNTER0_SELECT__CI__VI, 0, mmTA_PERFCOUNTER0_LO__CI__VI, - mmTA_PERFCOUNTER0_HI__CI__VI}, - {mmTA_PERFCOUNTER1_SELECT__CI__VI, 0, mmTA_PERFCOUNTER1_LO__CI__VI, - mmTA_PERFCOUNTER1_HI__CI__VI}}; - -/* - * TD - */ -GpuCounterRegInfo ViTdCounterRegAddr[] = { - {mmTD_PERFCOUNTER0_SELECT__CI__VI, 0, mmTD_PERFCOUNTER0_LO__CI__VI, - mmTD_PERFCOUNTER0_HI__CI__VI}, - {mmTD_PERFCOUNTER1_SELECT__CI__VI, 0, mmTD_PERFCOUNTER1_LO__CI__VI, - mmTD_PERFCOUNTER1_HI__CI__VI}}; - -/* - * GDS - */ -GpuCounterRegInfo ViGdsCounterRegAddr[] = { - {mmGDS_PERFCOUNTER0_SELECT__CI__VI, 0, mmGDS_PERFCOUNTER0_LO__CI__VI, - mmGDS_PERFCOUNTER0_HI__CI__VI}, - {mmGDS_PERFCOUNTER1_SELECT__CI__VI, 0, mmGDS_PERFCOUNTER1_LO__CI__VI, - mmGDS_PERFCOUNTER1_HI__CI__VI}, - {mmGDS_PERFCOUNTER2_SELECT__CI__VI, 0, mmGDS_PERFCOUNTER2_LO__CI__VI, - mmGDS_PERFCOUNTER2_HI__CI__VI}, - {mmGDS_PERFCOUNTER3_SELECT__CI__VI, 0, mmGDS_PERFCOUNTER3_LO__CI__VI, - mmGDS_PERFCOUNTER3_HI__CI__VI}}; - -/* - * VGT - */ -GpuCounterRegInfo ViVgtCounterRegAddr[] = { - {mmVGT_PERFCOUNTER0_SELECT__CI__VI, 0, mmVGT_PERFCOUNTER0_LO__CI__VI, - mmVGT_PERFCOUNTER0_HI__CI__VI}, - {mmVGT_PERFCOUNTER1_SELECT__CI__VI, 0, mmVGT_PERFCOUNTER1_LO__CI__VI, - mmVGT_PERFCOUNTER1_HI__CI__VI}, - {mmVGT_PERFCOUNTER2_SELECT__CI__VI, 0, mmVGT_PERFCOUNTER2_LO__CI__VI, - mmVGT_PERFCOUNTER2_HI__CI__VI}, - {mmVGT_PERFCOUNTER3_SELECT__CI__VI, 0, mmVGT_PERFCOUNTER3_LO__CI__VI, - mmVGT_PERFCOUNTER3_HI__CI__VI}}; - -/* - * IA - */ -GpuCounterRegInfo ViIaCounterRegAddr[] = { - {mmIA_PERFCOUNTER0_SELECT__CI__VI, 0, mmIA_PERFCOUNTER0_LO__CI__VI, - mmIA_PERFCOUNTER0_HI__CI__VI}, - {mmIA_PERFCOUNTER1_SELECT__CI__VI, 0, mmIA_PERFCOUNTER1_LO__CI__VI, - mmIA_PERFCOUNTER1_HI__CI__VI}, - {mmIA_PERFCOUNTER2_SELECT__CI__VI, 0, mmIA_PERFCOUNTER2_LO__CI__VI, - mmIA_PERFCOUNTER2_HI__CI__VI}, - {mmIA_PERFCOUNTER3_SELECT__CI__VI, 0, mmIA_PERFCOUNTER3_LO__CI__VI, - mmIA_PERFCOUNTER3_HI__CI__VI}}; - -/* - * MC - */ -GpuCounterRegInfo ViMcCounterRegAddr[] = { - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_A_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_A_I1__VI}, - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_B_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_B_I1__VI}, - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_C_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_C_I1__VI}, - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_D_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_D_I1__VI}}; - -/* - * SRBM - */ -GpuCounterRegInfo ViSrbmCounterRegAddr[] = { - {mmSRBM_PERFCOUNTER0_SELECT__VI, 0, mmSRBM_PERFCOUNTER0_LO__VI, mmSRBM_PERFCOUNTER0_HI__VI}, - {mmSRBM_PERFCOUNTER1_SELECT__VI, 0, mmSRBM_PERFCOUNTER1_LO__VI, mmSRBM_PERFCOUNTER1_HI__VI}}; - -/* - * WD - */ -GpuCounterRegInfo ViWdCounterRegAddr[] = { - {mmWD_PERFCOUNTER0_SELECT__CI__VI, 0, mmWD_PERFCOUNTER0_LO__CI__VI, - mmWD_PERFCOUNTER0_HI__CI__VI}, - {mmWD_PERFCOUNTER1_SELECT__CI__VI, 0, mmWD_PERFCOUNTER1_LO__CI__VI, - mmWD_PERFCOUNTER1_HI__CI__VI}, - {mmWD_PERFCOUNTER2_SELECT__CI__VI, 0, mmWD_PERFCOUNTER2_LO__CI__VI, - mmWD_PERFCOUNTER2_HI__CI__VI}, - {mmWD_PERFCOUNTER3_SELECT__CI__VI, 0, mmWD_PERFCOUNTER3_LO__CI__VI, - mmWD_PERFCOUNTER3_HI__CI__VI}}; - -/* - * CPG - */ -GpuCounterRegInfo ViCpgCounterRegAddr[] = { - {mmCPG_PERFCOUNTER0_SELECT__CI__VI, 0, mmCPG_PERFCOUNTER0_LO__CI__VI, - mmCPG_PERFCOUNTER0_HI__CI__VI}, - {mmCPG_PERFCOUNTER1_SELECT__CI__VI, 0, mmCPG_PERFCOUNTER1_LO__CI__VI, - mmCPG_PERFCOUNTER1_HI__CI__VI}}; - -/* - * CPC - */ -GpuCounterRegInfo ViCpcCounterRegAddr[] = { - {mmCPC_PERFCOUNTER0_SELECT__CI__VI, 0, mmCPC_PERFCOUNTER0_LO__CI__VI, - mmCPC_PERFCOUNTER0_HI__CI__VI}, - {mmCPC_PERFCOUNTER1_SELECT__CI__VI, 0, mmCPC_PERFCOUNTER1_LO__CI__VI, - mmCPC_PERFCOUNTER1_HI__CI__VI}}; - -GpuPrivCounterBlockId ViBlockIdSq = {{0xb5c396b6, 0x47e4d310, 0xc35cfc86, 0x08f53a04}}; -GpuPrivCounterBlockId ViBlockIdMc = {{0x13900b57, 0x4d984956, 0x5268d081, 0x9cf53719}}; -GpuPrivCounterBlockId ViBlockIdIommuV2 = {{0x80969879, 0x4be6b0f6, 0x636af697, 0x1d10f500}}; -GpuPrivCounterBlockId ViBlockIdKernelDriver = {{0xea9b5ae1, 0x44b36c3f, 0xf0da5489, 0x0aa96575}}; - -} // pm4_profile diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_block_info.h b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_block_info.h deleted file mode 100644 index 28a64a4d74..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_block_info.h +++ /dev/null @@ -1,227 +0,0 @@ -#ifndef _VI_BLOCKINFO_H_ -#define _VI_BLOCKINFO_H_ - -#include "gpu_block_info.h" - -namespace pm4_profile { - -// MAX Number of block instances for VOLCANIC ISLANDS (From Fiji) -// Values are found here //gfxip/gfx8/main/src/meta/features/variant/Fiji/album.dj - -// @brief Number of block instances. - -// We index per SE and instance -#define VI_NUM_CB 4 // CB has 4 instances per SE -#define VI_NUM_DB 4 // DB has 4 instances per SE - -// For TA, TD and TCP, the values below are the same as the number of CUs -// per SH. We index per SE and instance -#define VI_NUM_TA 16 // TA has 11 instances -#define VI_NUM_TD 16 // TD has 11 instances -#define VI_NUM_TCP 16 // TCP has 11 instances - -// These values are per chip, we index directly per instance -#define VI_NUM_TCA 2 // TCA has 2 instances per chip -#define VI_NUM_TCC 16 // TCC has 16 instances per chip -#define VI_NUM_SDMA 2 // There are two SDMA blocks on VI, exposed as 2 - // instances here - -// Number of counter registers per block for volcanic islands -#define VI_COUNTER_NUM_PER_DRM 2 -#define VI_COUNTER_NUM_PER_DRMDMA 2 -#define VI_COUNTER_NUM_PER_IH 2 -#define VI_COUNTER_NUM_PER_SRBM 2 -#define VI_COUNTER_NUM_PER_CB 4 -#define VI_COUNTER_NUM_PER_CPF 2 -#define VI_COUNTER_NUM_PER_DB 4 -#define VI_COUNTER_NUM_PER_GRBM 2 -#define VI_COUNTER_NUM_PER_GRBMSE 4 -#define VI_COUNTER_NUM_PER_PA_SU 4 -#define VI_COUNTER_NUM_PER_RLC 2 -#define VI_COUNTER_NUM_PER_PA_SC 8 -#define VI_COUNTER_NUM_PER_SPI 6 // [Shucai: To do: double check the value] -#define VI_COUNTER_NUM_PER_SQ 16 -#define VI_COUNTER_NUM_PER_SX 4 -#define VI_COUNTER_NUM_PER_TA 2 -#define VI_COUNTER_NUM_PER_TCA 4 -#define VI_COUNTER_NUM_PER_TCC 4 -#define VI_COUNTER_NUM_PER_TD 2 // [Shucai: To do: double check the value] -#define VI_COUNTER_NUM_PER_TCP 4 -#define VI_COUNTER_NUM_PER_GDS 4 -#define VI_COUNTER_NUM_PER_VGT 4 -#define VI_COUNTER_NUM_PER_IA 4 -#define VI_COUNTER_NUM_PER_MC 4 -#define VI_COUNTER_NUM_PER_TCS 4 -#define VI_COUNTER_NUM_PER_WD 4 -#define VI_COUNTER_NUM_PER_CPG 2 -#define VI_COUNTER_NUM_PER_CPC 2 -#define VI_COUNTER_NUM_PER_VM 1 -#define VI_COUNTER_NUM_PER_VM_MD 1 -#define VI_COUNTER_NUM_PER_PIPESTATS 12 - -#define VI_MAX_NUM_SHADER_ENGINES 1 - -// Enumeration of VI hardware counter blocks -typedef enum HsaViCounterBlockId { - kHsaViCounterBlockIdCb0 = 0, - kHsaViCounterBlockIdCb1, - kHsaViCounterBlockIdCb2, - kHsaViCounterBlockIdCb3, - - kHsaViCounterBlockIdCpf, - - kHsaViCounterBlockIdDb0, - kHsaViCounterBlockIdDb1, - kHsaViCounterBlockIdDb2, - kHsaViCounterBlockIdDb3, - - kHsaViCounterBlockIdGrbm, - kHsaViCounterBlockIdGrbmSe, - kHsaViCounterBlockIdPaSu, - kHsaViCounterBlockIdPaSc, - kHsaViCounterBlockIdSpi, - - kHsaViCounterBlockIdSq, - kHsaViCounterBlockIdSqEs, - kHsaViCounterBlockIdSqGs, - kHsaViCounterBlockIdSqVs, - kHsaViCounterBlockIdSqPs, - kHsaViCounterBlockIdSqLs, - kHsaViCounterBlockIdSqHs, - kHsaViCounterBlockIdSqCs, - - kHsaViCounterBlockIdSx, - - kHsaViCounterBlockIdTa0, - kHsaViCounterBlockIdTa1, - kHsaViCounterBlockIdTa2, - kHsaViCounterBlockIdTa3, - kHsaViCounterBlockIdTa4, - kHsaViCounterBlockIdTa5, - kHsaViCounterBlockIdTa6, - kHsaViCounterBlockIdTa7, - kHsaViCounterBlockIdTa8, - kHsaViCounterBlockIdTa9, - kHsaViCounterBlockIdTa10, - kHsaViCounterBlockIdTa11, - kHsaViCounterBlockIdTa12, - kHsaViCounterBlockIdTa13, - kHsaViCounterBlockIdTa14, - kHsaViCounterBlockIdTa15, - - kHsaViCounterBlockIdTca0, - kHsaViCounterBlockIdTca1, - - kHsaViCounterBlockIdTcc0, - kHsaViCounterBlockIdTcc1, - kHsaViCounterBlockIdTcc2, - kHsaViCounterBlockIdTcc3, - kHsaViCounterBlockIdTcc4, - kHsaViCounterBlockIdTcc5, - kHsaViCounterBlockIdTcc6, - kHsaViCounterBlockIdTcc7, - kHsaViCounterBlockIdTcc8, - kHsaViCounterBlockIdTcc9, - kHsaViCounterBlockIdTcc10, - kHsaViCounterBlockIdTcc11, - kHsaViCounterBlockIdTcc12, - kHsaViCounterBlockIdTcc13, - kHsaViCounterBlockIdTcc14, - kHsaViCounterBlockIdTcc15, - - kHsaViCounterBlockIdTd0, - kHsaViCounterBlockIdTd1, - kHsaViCounterBlockIdTd2, - kHsaViCounterBlockIdTd3, - kHsaViCounterBlockIdTd4, - kHsaViCounterBlockIdTd5, - kHsaViCounterBlockIdTd6, - kHsaViCounterBlockIdTd7, - kHsaViCounterBlockIdTd8, - kHsaViCounterBlockIdTd9, - kHsaViCounterBlockIdTd10, - kHsaViCounterBlockIdTd11, - kHsaViCounterBlockIdTd12, - kHsaViCounterBlockIdTd13, - kHsaViCounterBlockIdTd14, - kHsaViCounterBlockIdTd15, - - kHsaViCounterBlockIdTcp0, - kHsaViCounterBlockIdTcp1, - kHsaViCounterBlockIdTcp2, - kHsaViCounterBlockIdTcp3, - kHsaViCounterBlockIdTcp4, - kHsaViCounterBlockIdTcp5, - kHsaViCounterBlockIdTcp6, - kHsaViCounterBlockIdTcp7, - kHsaViCounterBlockIdTcp8, - kHsaViCounterBlockIdTcp9, - kHsaViCounterBlockIdTcp10, - kHsaViCounterBlockIdTcp11, - kHsaViCounterBlockIdTcp12, - kHsaViCounterBlockIdTcp13, - kHsaViCounterBlockIdTcp14, - kHsaViCounterBlockIdTcp15, - - kHsaViCounterBlockIdGds, - kHsaViCounterBlockIdVgt, - kHsaViCounterBlockIdIa, - kHsaViCounterBlockIdMc, - kHsaViCounterBlockIdSrbm, - - kHsaViCounterBlockIdTcs, - kHsaViCounterBlockIdWd, - kHsaViCounterBlockIdCpg, - kHsaViCounterBlockIdCpc, - - // Counters retrieved by KFD - kHsaViCounterBlockIdIommuV2, - kHsaViCounterBlockIdKernelDriver, - - kHsaViCounterBlockIdCpPipeStats, - kHsaViCounterBlockIdHwInfo, - kHsaViCounterBlockIdBlocksFirst = kHsaViCounterBlockIdCb0, - kHsaViCounterBlockIdBlocksLast = kHsaViCounterBlockIdHwInfo -} HsaViCounterBlockId; - -extern GpuBlockInfo Gfx8HwBlocks[]; -extern GpuCounterRegInfo ViSqCounterRegAddr[]; -extern GpuCounterRegInfo ViCbCounterRegAddr[]; -extern GpuCounterRegInfo ViDrmdmaCounterRegAddr[]; -extern GpuCounterRegInfo ViIhCounterRegAddr[]; -extern GpuCounterRegInfo ViCpfCounterRegAddr[]; -extern GpuCounterRegInfo ViCpgCounterRegAddr[]; -extern GpuCounterRegInfo ViCpcCounterRegAddr[]; -extern GpuCounterRegInfo ViDrmCounterRegAddr[]; -extern GpuCounterRegInfo ViGrbmCounterRegAddr[]; -extern GpuCounterRegInfo ViGrbmSeCounterRegAddr[]; -extern GpuCounterRegInfo ViPaSuCounterRegAddr[]; -extern GpuCounterRegInfo ViPaScCounterRegAddr[]; -extern GpuCounterRegInfo ViSpiCounterRegAddr[]; -extern GpuCounterRegInfo ViTcaCounterRegAddr[]; -extern GpuCounterRegInfo ViTccCounterRegAddr[]; -extern GpuCounterRegInfo ViTcpCounterRegAddr[]; -extern GpuCounterRegInfo ViDbCounterRegAddr[]; -extern GpuCounterRegInfo ViRlcCounterRegAddr[]; -extern GpuCounterRegInfo ViScCounterRegAddr[]; -extern GpuCounterRegInfo ViSxCounterRegAddr[]; -extern GpuCounterRegInfo ViTaCounterRegAddr[]; -extern GpuCounterRegInfo ViTdCounterRegAddr[]; -extern GpuCounterRegInfo ViGdsCounterRegAddr[]; -extern GpuCounterRegInfo ViVgtCounterRegAddr[]; -extern GpuCounterRegInfo ViIaCounterRegAddr[]; -extern GpuCounterRegInfo ViMcCounterRegAddr[]; -extern GpuCounterRegInfo ViSrbmCounterRegAddr[]; - -// No Tcs Counter block on VI -// extern GpuCounterRegInfo ViTcsCounterRegAddr[]; -extern GpuCounterRegInfo ViWdCounterRegAddr[]; -extern GpuCounterRegInfo ViCpgCounterRegAddr[]; -extern GpuCounterRegInfo ViCpcCounterRegAddr[]; - -extern GpuPrivCounterBlockId ViBlockIdSq; -extern GpuPrivCounterBlockId ViBlockIdMc; -extern GpuPrivCounterBlockId ViBlockIdIommuV2; -extern GpuPrivCounterBlockId ViBlockIdKernelDriver; -} -#endif diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_perf_counter.cpp b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_perf_counter.cpp deleted file mode 100644 index f25d5ab30b..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_perf_counter.cpp +++ /dev/null @@ -1,1307 +0,0 @@ -#include - -#include "gfxip/gfx8/si_ci_vi_merged_typedef.h" -#include "gfxip/gfx8/si_ci_vi_merged_offset.h" -#include "gfxip/gfx8/si_ci_vi_merged_enum.h" -#include "gfxip/gfx8/si_pm4defs.h" - -#include "gfx8_perf_counter.h" -#include "gfx8_block_info.h" -#include "cmdwriter.h" - -using namespace std; -using namespace pm4_profile; - -// A flag to indicate the current packet is for copy register value -#define MAX_REG_NUM 100 -#define COPY_DATA_FLAG 0xFFFFFFFF - -namespace pm4_profile { - -Gfx8PerfCounter::Gfx8PerfCounter() { - // Initialize the number of shader engines - num_se_ = 4; - Init(); -} - -void Gfx8PerfCounter::Init() { - // Initialize the value to use in resetting GRBM - regGRBM_GFX_INDEX grbm_gfx_index; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - reset_grbm_ = grbm_gfx_index.u32All; -} - -void Gfx8PerfCounter::begin(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, - const CountersMap& countersMap) { - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, reset_grbm_); - - // Reset the counter list - regCP_PERFMON_CNTL cp_perfmon_cntl = {0}; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL__CI__VI, cp_perfmon_cntl.u32All); - - // Iterate through the list of blocks to generate Pm4 commands to - // program corresponding perf counters of each block - for (CountersMap::const_iterator block_it = countersMap.begin(); block_it != countersMap.end(); - ++block_it) { - const uint32_t block_id = block_it->first; - const CountersVec& counters = block_it->second; - const uint32_t counter_count = counters.size(); - - // Iterate through each enabled perf counter and building - // corresponding Pm4 commands to program the various control - // registers involved - for (uint32_t ind = 0; ind < counter_count; ++ind) { - const uint32_t counter_id = counters[ind]; - - // Build the list of control registers to program which - // varies per perf counter block - uint32_t reg_addr[MAX_REG_NUM], reg_val[MAX_REG_NUM]; - const uint32_t reg_num = - BuildCounterSelRegister(ind, reg_addr, reg_val, block_id, counter_id); - - // Build the list of Pm4 commands that support control - // register programming - for (uint32_t n = 0; n < reg_num; ++n) { - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, reg_addr[n], reg_val[n]); - } - } - } - - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, reset_grbm_); - - // Program Compute_Perfcount_Enable register to support perf counting - regCOMPUTE_PERFCOUNT_ENABLE__CI__VI cp_perfcount_enable; - cp_perfcount_enable.u32All = 0; - cp_perfcount_enable.bits.PERFCOUNT_ENABLE = 1; - cmdWriter->BuildWriteShRegPacket(cmdBuff, mmCOMPUTE_PERFCOUNT_ENABLE__CI__VI, - cp_perfcount_enable.u32All); - - // Reset the counter list - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL__CI__VI, cp_perfmon_cntl.u32All); - - // Start the counter list - cp_perfmon_cntl.bits.PERFMON_STATE = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL__CI__VI, cp_perfmon_cntl.u32All); - - // Issue barrier command to apply the commands to configure perfcounters - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); -} - -uint32_t Gfx8PerfCounter::end(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, - const CountersMap& countersMap, void* dataBuff) { - // Issue barrier command to wait for dispatch to complete - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Build PM4 packet to stop and freeze counters - regCP_PERFMON_CNTL cp_perfmon_cntl; - cp_perfmon_cntl.u32All = 0; - cp_perfmon_cntl.bits.PERFMON_STATE = 2; - cp_perfmon_cntl.bits.PERFMON_SAMPLE_ENABLE = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL__CI__VI, cp_perfmon_cntl.u32All); - - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, reset_grbm_); - - // Iterate through the list of blocks to create PM4 packets to read counter values - uint32_t total_counter_num = 0; - for (CountersMap::const_iterator block_it = countersMap.begin(); block_it != countersMap.end(); - ++block_it) { - const uint32_t block_id = block_it->first; - const uint32_t counter_count = block_it->second.size(); - - for (uint32_t ind = 0; ind < counter_count; ++ind) { - // retrieve the registers to be set - uint32_t reg_addr[MAX_REG_NUM], reg_val[MAX_REG_NUM]; - const uint32_t reg_num = BuildCounterReadRegisters(ind, block_id, reg_addr, reg_val); - - for (uint32_t n = 0; n < reg_num; n++) { - if (reg_val[n] == COPY_DATA_FLAG) { - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_REG, reg_addr[n], 0, - ((uint32_t*)dataBuff) + total_counter_num, - COPY_DATA_SEL_COUNT_1DW, false); - total_counter_num++; - } else { - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, reg_addr[n], reg_val[n]); - } - } - } - } - - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, reset_grbm_); - - return total_counter_num * sizeof(uint32_t); -} - -uint32_t Gfx8PerfCounter::ProgramTcpCntrs(uint32_t tcpRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaViCounterBlockIdTcp0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX__CI__VI; - regIdx++; - - regTCP_PERFCOUNTER0_SELECT__CI__VI tcp_perf_counter_select; - tcp_perf_counter_select.u32All = 0; - tcp_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = tcp_perf_counter_select.u32All; - regAddr[regIdx] = ViTcpCounterRegAddr[tcpRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx8PerfCounter::ProgramTdCntrs(uint32_t tdRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaViCounterBlockIdTd0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX__CI__VI; - regIdx++; - - regTD_PERFCOUNTER0_SELECT td_perf_counter_select; - td_perf_counter_select.u32All = 0; - td_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[regIdx] = td_perf_counter_select.u32All; - regAddr[regIdx] = ViTdCounterRegAddr[tdRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx8PerfCounter::ProgramTccCntrs(uint32_t tccRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaViCounterBlockIdTcc0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX__CI__VI; - regIdx++; - - regTCC_PERFCOUNTER0_SELECT__CI__VI tcc_perf_counter_select; - tcc_perf_counter_select.u32All = 0; - tcc_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = tcc_perf_counter_select.u32All; - regAddr[regIdx] = ViTccCounterRegAddr[tccRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx8PerfCounter::ProgramTcaCntrs(uint32_t tcaRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaViCounterBlockIdTca0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX__CI__VI; - regIdx++; - - regTCA_PERFCOUNTER0_SELECT__CI__VI tca_perf_counter_select; - tca_perf_counter_select.u32All = 0; - tca_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = tca_perf_counter_select.u32All; - regAddr[regIdx] = ViTcaCounterRegAddr[tcaRegIdx].counterSelRegAddr; - regIdx++; - return regIdx; -} - -uint32_t Gfx8PerfCounter::ProgramTaCntrs(uint32_t taRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaViCounterBlockIdTa0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX__CI__VI; - regIdx++; - - regTA_PERFCOUNTER0_SELECT ta_perf_counter_select; - ta_perf_counter_select.u32All = 0; - ta_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = ta_perf_counter_select.u32All; - regAddr[regIdx] = ViTaCounterRegAddr[taRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx8PerfCounter::ProgramSQCntrs(uint32_t sqRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - uint32_t regIdx = 0; - - // Program the SQ Counter Select Register - regSQ_PERFCOUNTER0_SELECT__CI__VI sq_cntr_sel; - sq_cntr_sel.u32All = 0; - sq_cntr_sel.bits.SIMD_MASK = 0xF; - sq_cntr_sel.bits.SQC_BANK_MASK = 0xF; - sq_cntr_sel.bits.SQC_CLIENT_MASK = 0xF; - sq_cntr_sel.bits.PERF_SEL = blkCntrIdx; - regVal[regIdx] = sq_cntr_sel.u32All; - regAddr[regIdx] = ViSqCounterRegAddr[sqRegIdx].counterSelRegAddr; - regIdx++; - - // Program the SQ Counter Mask Register - regSQ_PERFCOUNTER_MASK__CI__VI sq_cntr_mask; - sq_cntr_mask.u32All = 0; - sq_cntr_mask.bits.SH0_MASK = 0xFFFF; - sq_cntr_mask.bits.SH1_MASK = 0xFFFF; - regVal[regIdx] = sq_cntr_mask.u32All; - regAddr[regIdx] = mmSQ_PERFCOUNTER_MASK__CI__VI; - regIdx++; - - // Initialize the register content - // Program the SQ Counter Control Register - regSQ_PERFCOUNTER_CTRL sq_cntr_ctrl; - sq_cntr_ctrl.u32All = 0; - if (blkId == kHsaViCounterBlockIdSq) { - sq_cntr_ctrl.bits.ES_EN = 0x1; - sq_cntr_ctrl.bits.GS_EN = 0x1; - sq_cntr_ctrl.bits.VS_EN = 0x1; - sq_cntr_ctrl.bits.PS_EN = 0x1; - sq_cntr_ctrl.bits.LS_EN = 0x1; - sq_cntr_ctrl.bits.HS_EN = 0x1; - sq_cntr_ctrl.bits.CS_EN = 0x1; - } else if (blkId == kHsaViCounterBlockIdSqEs) { - sq_cntr_ctrl.bits.ES_EN = 0x1; - } else if (blkId == kHsaViCounterBlockIdSqGs) { - sq_cntr_ctrl.bits.GS_EN = 0x1; - } else if (blkId == kHsaViCounterBlockIdSqVs) { - sq_cntr_ctrl.bits.VS_EN = 0x1; - } else if (blkId == kHsaViCounterBlockIdSqPs) { - sq_cntr_ctrl.bits.PS_EN = 0x1; - } else if (blkId == kHsaViCounterBlockIdSqLs) { - sq_cntr_ctrl.bits.LS_EN = 0x1; - } else if (blkId == kHsaViCounterBlockIdSqHs) { - sq_cntr_ctrl.bits.HS_EN = 0x1; - } else if (blkId == kHsaViCounterBlockIdSqCs) { - sq_cntr_ctrl.bits.CS_EN = 0x1; - } - - regVal[regIdx] = sq_cntr_ctrl.u32All; - regAddr[regIdx] = ViSqCounterRegAddr[sqRegIdx].counterCntlRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx8PerfCounter::BuildCounterSelRegister(uint32_t cntrIdx, uint32_t* regAddr, - uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx) { - uint32_t instance_index = 0; - regGRBM_GFX_INDEX grbm_gfx_index = {0}; - uint32_t regIdx = 0; - - switch (blkId) { - // Program counters belonging to SQ block - case kHsaViCounterBlockIdSq: - case kHsaViCounterBlockIdSqEs: - case kHsaViCounterBlockIdSqGs: - case kHsaViCounterBlockIdSqVs: - case kHsaViCounterBlockIdSqPs: - case kHsaViCounterBlockIdSqLs: - case kHsaViCounterBlockIdSqHs: - case kHsaViCounterBlockIdSqCs: - return ProgramSQCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaViCounterBlockIdCb0: - case kHsaViCounterBlockIdCb1: - case kHsaViCounterBlockIdCb2: - case kHsaViCounterBlockIdCb3: { - regIdx = 0; - instance_index = blkId - kHsaViCounterBlockIdCb0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER0_LO__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER0_HI__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER1_LO__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER1_HI__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER2_LO__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER2_HI__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER3_LO__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER3_HI__CI__VI; - regIdx++; - - regCB_PERFCOUNTER0_SELECT__CI__VI cb_perf_counter_select; - cb_perf_counter_select.u32All = 0; - cb_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = cb_perf_counter_select.u32All; - regAddr[regIdx] = ViCbCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx++; - - break; - } - - case kHsaViCounterBlockIdCpf: { - regCPF_PERFCOUNTER0_SELECT__CI__VI cpf_perf_counter_select; - cpf_perf_counter_select.u32All = 0; - cpf_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[0] = cpf_perf_counter_select.u32All; - regAddr[0] = ViCpfCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdDb0: - case kHsaViCounterBlockIdDb1: - case kHsaViCounterBlockIdDb2: - case kHsaViCounterBlockIdDb3: { - instance_index = blkId - kHsaViCounterBlockIdDb0; - regIdx = 0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER0_LO__CI__VI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER0_HI__CI__VI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER1_LO__CI__VI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER1_HI__CI__VI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER2_LO__CI__VI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER2_HI__CI__VI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER3_LO__CI__VI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER3_HI__CI__VI; - regIdx++; - - regDB_PERFCOUNTER0_SELECT db_perf_counter_select; - db_perf_counter_select.u32All = 0; - db_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[regIdx] = db_perf_counter_select.u32All; - regAddr[regIdx] = ViDbCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx++; - break; - } - - case kHsaViCounterBlockIdGrbm: { - regGRBM_PERFCOUNTER0_SELECT grbm_perf_counter_select; - grbm_perf_counter_select.u32All = 0; - grbm_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = grbm_perf_counter_select.u32All; - regAddr[0] = ViGrbmCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdGrbmSe: { - regGRBM_SE0_PERFCOUNTER_SELECT grbm_se0_perf_counter_select; - grbm_se0_perf_counter_select.u32All = 0; - grbm_se0_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = grbm_se0_perf_counter_select.u32All; - regAddr[0] = ViGrbmSeCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdPaSu: { - regPA_SU_PERFCOUNTER0_SELECT pa_su_perf_counter_select; - pa_su_perf_counter_select.u32All = 0; - pa_su_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = pa_su_perf_counter_select.u32All; - regAddr[0] = ViPaSuCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdPaSc: { - regPA_SC_PERFCOUNTER0_SELECT pa_sc_perf_counter_select; - pa_sc_perf_counter_select.u32All = 0; - pa_sc_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = pa_sc_perf_counter_select.u32All; - regAddr[0] = ViPaScCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdSpi: { - regSPI_PERFCOUNTER0_SELECT spi_perf_counter_select; - spi_perf_counter_select.u32All = 0; - spi_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = spi_perf_counter_select.u32All; - regAddr[0] = ViSpiCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdSx: { - regIdx = 0; - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER0_LO__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER0_HI__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER1_LO__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER1_HI__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER2_LO__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER2_HI__CI__VI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER3_LO__CI__VI; - regIdx++; - - regSX_PERFCOUNTER0_SELECT sx_perf_counter_select; - sx_perf_counter_select.u32All = 0; - sx_perf_counter_select.bits.PERFCOUNTER_SELECT = blkCntrIdx; - regVal[regIdx] = sx_perf_counter_select.u32All; - regAddr[regIdx] = ViSxCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx++; - break; - } - - case kHsaViCounterBlockIdTa0: - case kHsaViCounterBlockIdTa1: - case kHsaViCounterBlockIdTa2: - case kHsaViCounterBlockIdTa3: - case kHsaViCounterBlockIdTa4: - case kHsaViCounterBlockIdTa5: - case kHsaViCounterBlockIdTa6: - case kHsaViCounterBlockIdTa7: - case kHsaViCounterBlockIdTa8: - case kHsaViCounterBlockIdTa9: - case kHsaViCounterBlockIdTa10: - case kHsaViCounterBlockIdTa11: - case kHsaViCounterBlockIdTa12: - case kHsaViCounterBlockIdTa13: - case kHsaViCounterBlockIdTa14: - case kHsaViCounterBlockIdTa15: - return ProgramTaCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaViCounterBlockIdTca0: - case kHsaViCounterBlockIdTca1: - return ProgramTcaCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaViCounterBlockIdTcc0: - case kHsaViCounterBlockIdTcc1: - case kHsaViCounterBlockIdTcc2: - case kHsaViCounterBlockIdTcc3: - case kHsaViCounterBlockIdTcc4: - case kHsaViCounterBlockIdTcc5: - case kHsaViCounterBlockIdTcc6: - case kHsaViCounterBlockIdTcc7: - case kHsaViCounterBlockIdTcc8: - case kHsaViCounterBlockIdTcc9: - case kHsaViCounterBlockIdTcc10: - case kHsaViCounterBlockIdTcc11: - case kHsaViCounterBlockIdTcc12: - case kHsaViCounterBlockIdTcc13: - case kHsaViCounterBlockIdTcc14: - case kHsaViCounterBlockIdTcc15: - return ProgramTccCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaViCounterBlockIdTd0: - case kHsaViCounterBlockIdTd1: - case kHsaViCounterBlockIdTd2: - case kHsaViCounterBlockIdTd3: - case kHsaViCounterBlockIdTd4: - case kHsaViCounterBlockIdTd5: - case kHsaViCounterBlockIdTd6: - case kHsaViCounterBlockIdTd7: - case kHsaViCounterBlockIdTd8: - case kHsaViCounterBlockIdTd9: - case kHsaViCounterBlockIdTd10: - case kHsaViCounterBlockIdTd11: - case kHsaViCounterBlockIdTd12: - case kHsaViCounterBlockIdTd13: - case kHsaViCounterBlockIdTd14: - case kHsaViCounterBlockIdTd15: - return ProgramTdCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaViCounterBlockIdTcp0: - case kHsaViCounterBlockIdTcp1: - case kHsaViCounterBlockIdTcp2: - case kHsaViCounterBlockIdTcp3: - case kHsaViCounterBlockIdTcp4: - case kHsaViCounterBlockIdTcp5: - case kHsaViCounterBlockIdTcp6: - case kHsaViCounterBlockIdTcp7: - case kHsaViCounterBlockIdTcp8: - case kHsaViCounterBlockIdTcp9: - case kHsaViCounterBlockIdTcp10: - case kHsaViCounterBlockIdTcp11: - case kHsaViCounterBlockIdTcp12: - case kHsaViCounterBlockIdTcp13: - case kHsaViCounterBlockIdTcp14: - case kHsaViCounterBlockIdTcp15: - return ProgramTcpCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaViCounterBlockIdGds: { - regGDS_PERFCOUNTER0_SELECT gds_perf_counter_select; - gds_perf_counter_select.u32All = 0; - gds_perf_counter_select.bits.PERFCOUNTER_SELECT = blkCntrIdx; - regVal[0] = gds_perf_counter_select.u32All; - regAddr[0] = ViGdsCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdVgt: { - regVGT_PERFCOUNTER0_SELECT__CI__VI vgt_perf_counter_select; - vgt_perf_counter_select.u32All = 0; - vgt_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = vgt_perf_counter_select.u32All; - regAddr[0] = ViVgtCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdIa: { - regIA_PERFCOUNTER0_SELECT__CI__VI ia_perf_counter_select; - ia_perf_counter_select.u32All = 0; - ia_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = ia_perf_counter_select.u32All; - regAddr[0] = ViIaCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - /* - case kHsaViCounterBlockIdMc: { - // To be investigated later - //regMC_SEQ_PERF_SEQ_CTL mc_perfcounter_select; - //mc_perfcounter_select.u32All = 0; - //mc_perfcounter_select.bits.PERF_SEL = blkCntrIdx; - //regVal[0] = mc_perfcounter_select.u32All; - //regAddr[0] = ViMcCounterRegAddr[cntrIdx].counterSelRegAddr; - //regIdx = 1; - } - break; - */ - - case kHsaViCounterBlockIdSrbm: { - regSRBM_PERFCOUNTER0_SELECT srbm_perf_counter_select; - srbm_perf_counter_select.u32All = 0; - srbm_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = srbm_perf_counter_select.u32All; - regAddr[0] = ViSrbmCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - /* - case kHsaViCounterBlockIdTcs: { - regTCS_PERFCOUNTER0_SELECT__CI tcs_perf_counter_select; - tcs_perf_counter_select.u32All = 0; - tcs_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = tcs_perf_counter_select.u32All; - regAddr[0] = ViTcsCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - */ - - case kHsaViCounterBlockIdWd: { - regWD_PERFCOUNTER0_SELECT__CI__VI wd_perf_counter_select; - wd_perf_counter_select.u32All = 0; - wd_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = wd_perf_counter_select.u32All; - regAddr[0] = ViWdCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdCpg: { - regCPG_PERFCOUNTER0_SELECT__CI__VI cpg_perf_counter_select; - cpg_perf_counter_select.u32All = 0; - cpg_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = cpg_perf_counter_select.u32All; - regAddr[0] = ViCpgCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaViCounterBlockIdCpc: { - regCPC_PERFCOUNTER0_SELECT__CI__VI cpc_perf_counter_select; - cpc_perf_counter_select.u32All = 0; - cpc_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = cpc_perf_counter_select.u32All; - regAddr[0] = ViCpcCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - /* - case kHsaViCounterBlockIdMc: { - AddPriviledgedCountersToList(ViBlockIdMc, blkCntrIdx); - //Num of regs equals to 0 means it is processed by KFD - regIdx = 0; - break; - } - - case kHsaViCounterBlockIdIommuV2: { - AddPriviledgedCountersToList(ViBlockIdIommuV2, blkCntrIdx); - //Num of regs equals to 0 means it is processed by KFD - regIdx = 0; - break; - } - - case kHsaViCounterBlockIdKernelDriver: { - AddPriviledgedCountersToList(ViBlockIdKernelDriver, blkCntrIdx); - //Num of regs equals to 0 means it is processed by KFD - regIdx = 0; - break; - } - */ - - default: { - regIdx = 0; - break; - } - } - - return regIdx; -} - -uint32_t Gfx8PerfCounter::BuildCounterReadRegisters(uint32_t reg_index, uint32_t block_id, - uint32_t* reg_addr, uint32_t* reg_val) { - uint32_t ii; - uint32_t reg_num = 0; - uint32_t instance_index; - regGRBM_GFX_INDEX grbm_gfx_index; - switch (block_id) { - case kHsaViCounterBlockIdSq: - case kHsaViCounterBlockIdSqEs: - case kHsaViCounterBlockIdSqGs: - case kHsaViCounterBlockIdSqVs: - case kHsaViCounterBlockIdSqPs: - case kHsaViCounterBlockIdSqLs: - case kHsaViCounterBlockIdSqHs: - case kHsaViCounterBlockIdSqCs: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViSqCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViSqCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdCb0: - case kHsaViCounterBlockIdCb1: - case kHsaViCounterBlockIdCb2: - case kHsaViCounterBlockIdCb3: { - instance_index = block_id - kHsaViCounterBlockIdCb0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViCbCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViCbCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdCpf: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViCpfCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViCpfCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdDb0: - case kHsaViCounterBlockIdDb1: - case kHsaViCounterBlockIdDb2: - case kHsaViCounterBlockIdDb3: { - instance_index = block_id - kHsaViCounterBlockIdDb0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViDbCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViDbCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdGrbm: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViGrbmCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViGrbmCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdGrbmSe: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViGrbmSeCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViGrbmSeCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdPaSu: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViPaSuCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViPaSuCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdPaSc: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViPaScCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViPaScCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdSpi: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViSpiCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViSpiCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdSx: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViSxCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViSxCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdTa0: - case kHsaViCounterBlockIdTa1: - case kHsaViCounterBlockIdTa2: - case kHsaViCounterBlockIdTa3: - case kHsaViCounterBlockIdTa4: - case kHsaViCounterBlockIdTa5: - case kHsaViCounterBlockIdTa6: - case kHsaViCounterBlockIdTa7: - case kHsaViCounterBlockIdTa8: - case kHsaViCounterBlockIdTa9: - case kHsaViCounterBlockIdTa10: - case kHsaViCounterBlockIdTa11: - case kHsaViCounterBlockIdTa12: - case kHsaViCounterBlockIdTa13: - case kHsaViCounterBlockIdTa14: - case kHsaViCounterBlockIdTa15: { - instance_index = block_id - kHsaViCounterBlockIdTa0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViTaCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViTaCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdTca0: - case kHsaViCounterBlockIdTca1: { - instance_index = block_id - kHsaViCounterBlockIdTca0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViTcaCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViTcaCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdTcc0: - case kHsaViCounterBlockIdTcc1: - case kHsaViCounterBlockIdTcc2: - case kHsaViCounterBlockIdTcc3: - case kHsaViCounterBlockIdTcc4: - case kHsaViCounterBlockIdTcc5: - case kHsaViCounterBlockIdTcc6: - case kHsaViCounterBlockIdTcc7: - case kHsaViCounterBlockIdTcc8: - case kHsaViCounterBlockIdTcc9: - case kHsaViCounterBlockIdTcc10: - case kHsaViCounterBlockIdTcc11: - case kHsaViCounterBlockIdTcc12: - case kHsaViCounterBlockIdTcc13: - case kHsaViCounterBlockIdTcc14: - case kHsaViCounterBlockIdTcc15: { - instance_index = block_id - kHsaViCounterBlockIdTcc0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViTccCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViTccCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdTd0: - case kHsaViCounterBlockIdTd1: - case kHsaViCounterBlockIdTd2: - case kHsaViCounterBlockIdTd3: - case kHsaViCounterBlockIdTd4: - case kHsaViCounterBlockIdTd5: - case kHsaViCounterBlockIdTd6: - case kHsaViCounterBlockIdTd7: - case kHsaViCounterBlockIdTd8: - case kHsaViCounterBlockIdTd9: - case kHsaViCounterBlockIdTd10: - case kHsaViCounterBlockIdTd11: - case kHsaViCounterBlockIdTd12: - case kHsaViCounterBlockIdTd13: - case kHsaViCounterBlockIdTd14: - case kHsaViCounterBlockIdTd15: { - instance_index = block_id - kHsaViCounterBlockIdTd0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViTdCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViTdCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdTcp0: - case kHsaViCounterBlockIdTcp1: - case kHsaViCounterBlockIdTcp2: - case kHsaViCounterBlockIdTcp3: - case kHsaViCounterBlockIdTcp4: - case kHsaViCounterBlockIdTcp5: - case kHsaViCounterBlockIdTcp6: - case kHsaViCounterBlockIdTcp7: - case kHsaViCounterBlockIdTcp8: - case kHsaViCounterBlockIdTcp9: - case kHsaViCounterBlockIdTcp10: - case kHsaViCounterBlockIdTcp11: - case kHsaViCounterBlockIdTcp12: - case kHsaViCounterBlockIdTcp13: - case kHsaViCounterBlockIdTcp14: - case kHsaViCounterBlockIdTcp15: { - instance_index = block_id - kHsaViCounterBlockIdTcp0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViTcpCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViTcpCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdGds: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViGdsCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViGdsCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdVgt: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViVgtCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViVgtCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaViCounterBlockIdIa: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = ViIaCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViIaCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - /* - case kHsaViCounterBlockIdMc: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViMcCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViMcCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - */ - case kHsaViCounterBlockIdSrbm: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViSrbmCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViSrbmCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - /* - case kHsaViCounterBlockIdTcs: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViTcsCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViTcsCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - */ - case kHsaViCounterBlockIdWd: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViWdCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViWdCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdCpg: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViCpgCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViCpgCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaViCounterBlockIdCpc: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX__CI__VI; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = ViCpcCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = ViCpcCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - // IommuV2, MC, kernel driver counters are retrieved via - // KFD implementation - case kHsaViCounterBlockIdMc: - case kHsaViCounterBlockIdIommuV2: - case kHsaViCounterBlockIdKernelDriver: { - reg_num = 0; - break; - } - - default: { break; } - } - - return reg_num; -} - -} /* namespace */ diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_perf_counter.h b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_perf_counter.h deleted file mode 100644 index ed3c39681d..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx8_perf_counter.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _VI_PMU_H_ -#define _VI_PMU_H_ - -#include - -#include "perf_counter.h" - -namespace pm4_profile { -class CommandWriter; - -// This class implement the VI PMU. It is responsible for setting up -// CounterGroups to represent each VI hardware block which exposes performance -// counters. -class Gfx8PerfCounter : public pm4_profile::PerfCounter { - public: - Gfx8PerfCounter(); - - // Returns number of shader engines per block - // for the blocks featured shader engines instancing - uint32_t getNumSe() { return num_se_; } - - void begin(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, const CountersMap& countersMap); - - uint32_t end(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, const CountersMap& countersMap, - void* dataBuff); - - private: - void Init(); - - // Program SQ block related counters - uint32_t ProgramSQCntrs(uint32_t sqRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TA block related counters - uint32_t ProgramTaCntrs(uint32_t taRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TCA block related counters - uint32_t ProgramTcaCntrs(uint32_t tcaRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TCC block related counters - uint32_t ProgramTccCntrs(uint32_t tccRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TCP block related counters - uint32_t ProgramTcpCntrs(uint32_t tcpRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TD block related counters - uint32_t ProgramTdCntrs(uint32_t tdRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Build counter selection register, return how many registers are built - uint32_t BuildCounterSelRegister(uint32_t cntrIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx); - - // Build counter selection register, return how many registers are built - uint32_t BuildCounterReadRegisters(uint32_t reg_index, uint32_t block_id, uint32_t* reg_addr, - uint32_t* reg_val); - - private: - // Indicates the number of Shader Engines Present - uint32_t num_se_; - - // Used to reset GRBM to its default state - uint32_t reset_grbm_; -}; -} - -#endif // _VI_PMU_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_block_info.cpp b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_block_info.cpp deleted file mode 100644 index bacefc0b01..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_block_info.cpp +++ /dev/null @@ -1,553 +0,0 @@ -#include "gfx9_block_info.h" -#include "gfxip/gfx9/gfx9_offset.h" -#include "gfxip/gfx9/gfx9_typedef.h" - -namespace pm4_profile { -/** - * Table containing CounterGroups which represent AI hardware blocks - * as defined by \ref GpuBlockInfo structure - */ -GpuBlockInfo Gfx9HwBlocks[] = { - // Counter block CB - {"AI_CB0", kHsaAiCounterBlockIdCb0, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_CB, - CntlMethodBySeAndInstance, 395, AI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_CB1", kHsaAiCounterBlockIdCb1, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_CB, - CntlMethodBySeAndInstance, 395, AI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_CB2", kHsaAiCounterBlockIdCb2, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_CB, - CntlMethodBySeAndInstance, 395, AI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_CB3", kHsaAiCounterBlockIdCb3, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_CB, - CntlMethodBySeAndInstance, 395, AI_COUNTER_NUM_PER_CB, 0, 0, true, 0, 0, false, 0, 0}, - - // Temp commented for Vega10 - // Counter block CPF - /* - {"AI_CPF", kHsaAiCounterBlockIdCpf, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 19, - AI_COUNTER_NUM_PER_CPF, 0, 0, true, 0, 0, false, 0, 0}, - */ - - // Counter block DB - {"AI_DB0", kHsaAiCounterBlockIdDb0, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_DB, - CntlMethodBySeAndInstance, 256, AI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_DB1", kHsaAiCounterBlockIdDb1, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_DB, - CntlMethodBySeAndInstance, 256, AI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_DB2", kHsaAiCounterBlockIdDb2, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_DB, - CntlMethodBySeAndInstance, 256, AI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_DB3", kHsaAiCounterBlockIdDb3, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_DB, - CntlMethodBySeAndInstance, 256, AI_COUNTER_NUM_PER_DB, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block GRBM - {"AI_GRBM", kHsaAiCounterBlockIdGrbm, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 33, - AI_COUNTER_NUM_PER_GRBM, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block GRBMSE - {"AI_GRBMSE", kHsaAiCounterBlockIdGrbmSe, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 14, - AI_COUNTER_NUM_PER_GRBMSE, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block PA_SU - {"AI_PA_SU", kHsaAiCounterBlockIdPaSu, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 152, - AI_COUNTER_NUM_PER_PA_SU, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block PA_SC - {"AI_PA_SC", kHsaAiCounterBlockIdPaSc, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 396, - AI_COUNTER_NUM_PER_PA_SC, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block SPI - {"AI_SPI", kHsaAiCounterBlockIdSpi, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 196, - AI_COUNTER_NUM_PER_SPI, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block SQ - {"AI_SQ", kHsaAiCounterBlockIdSq, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 171, - AI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_SQ_GS", kHsaAiCounterBlockIdSqGs, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - AI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_SQ_VS", kHsaAiCounterBlockIdSqVs, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - AI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_SQ_PS", kHsaAiCounterBlockIdSqPs, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - AI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_SQ_HS", kHsaAiCounterBlockIdSqHs, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - AI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_SQ_CS", kHsaAiCounterBlockIdSqCs, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 298, - AI_COUNTER_NUM_PER_SQ, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block SX - {"AI_SX", kHsaAiCounterBlockIdSx, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 33, - AI_COUNTER_NUM_PER_SX, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TA - {"AI_TA0", kHsaAiCounterBlockIdTa0, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA1", kHsaAiCounterBlockIdTa1, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA2", kHsaAiCounterBlockIdTa2, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA3", kHsaAiCounterBlockIdTa3, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA4", kHsaAiCounterBlockIdTa4, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA5", kHsaAiCounterBlockIdTa5, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA6", kHsaAiCounterBlockIdTa6, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA7", kHsaAiCounterBlockIdTa7, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA8", kHsaAiCounterBlockIdTa8, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA9", kHsaAiCounterBlockIdTa9, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA10", kHsaAiCounterBlockIdTa10, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA11", kHsaAiCounterBlockIdTa11, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA12", kHsaAiCounterBlockIdTa12, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA13", kHsaAiCounterBlockIdTa13, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA14", kHsaAiCounterBlockIdTa14, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TA15", kHsaAiCounterBlockIdTa15, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TA, - CntlMethodBySeAndInstance, 118, AI_COUNTER_NUM_PER_TA, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TCA - {"AI_TCA0", kHsaAiCounterBlockIdTca0, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCA, - CntlMethodByInstance, 34, AI_COUNTER_NUM_PER_TCA, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCA1", kHsaAiCounterBlockIdTca1, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCA, - CntlMethodByInstance, 34, AI_COUNTER_NUM_PER_TCA, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TCC - {"AI_TCC0", kHsaAiCounterBlockIdTcc0, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC1", kHsaAiCounterBlockIdTcc1, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC2", kHsaAiCounterBlockIdTcc2, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC3", kHsaAiCounterBlockIdTcc3, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC4", kHsaAiCounterBlockIdTcc4, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC5", kHsaAiCounterBlockIdTcc5, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC6", kHsaAiCounterBlockIdTcc6, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC7", kHsaAiCounterBlockIdTcc7, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC8", kHsaAiCounterBlockIdTcc8, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC9", kHsaAiCounterBlockIdTcc9, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC10", kHsaAiCounterBlockIdTcc10, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC11", kHsaAiCounterBlockIdTcc11, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC12", kHsaAiCounterBlockIdTcc12, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC13", kHsaAiCounterBlockIdTcc13, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC14", kHsaAiCounterBlockIdTcc14, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCC15", kHsaAiCounterBlockIdTcc15, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCC, - CntlMethodByInstance, 191, AI_COUNTER_NUM_PER_TCC, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TD - {"AI_TD0", kHsaAiCounterBlockIdTd0, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD1", kHsaAiCounterBlockIdTd1, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD2", kHsaAiCounterBlockIdTd2, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD3", kHsaAiCounterBlockIdTd3, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD4", kHsaAiCounterBlockIdTd4, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD5", kHsaAiCounterBlockIdTd5, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD6", kHsaAiCounterBlockIdTd6, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD7", kHsaAiCounterBlockIdTd7, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD8", kHsaAiCounterBlockIdTd8, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD9", kHsaAiCounterBlockIdTd9, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD10", kHsaAiCounterBlockIdTd10, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD11", kHsaAiCounterBlockIdTd11, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD12", kHsaAiCounterBlockIdTd12, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD13", kHsaAiCounterBlockIdTd13, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD14", kHsaAiCounterBlockIdTd14, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TD15", kHsaAiCounterBlockIdTd15, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TD, - CntlMethodBySeAndInstance, 54, AI_COUNTER_NUM_PER_TD, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block TCP - {"AI_TCP0", kHsaAiCounterBlockIdTcp0, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP1", kHsaAiCounterBlockIdTcp1, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP2", kHsaAiCounterBlockIdTcp2, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP3", kHsaAiCounterBlockIdTcp3, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP4", kHsaAiCounterBlockIdTcp4, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP5", kHsaAiCounterBlockIdTcp5, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP6", kHsaAiCounterBlockIdTcp6, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP7", kHsaAiCounterBlockIdTcp7, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP8", kHsaAiCounterBlockIdTcp8, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP9", kHsaAiCounterBlockIdTcp9, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP10", kHsaAiCounterBlockIdTcp10, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP11", kHsaAiCounterBlockIdTcp11, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP12", kHsaAiCounterBlockIdTcp12, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP13", kHsaAiCounterBlockIdTcp13, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP14", kHsaAiCounterBlockIdTcp14, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - {"AI_TCP15", kHsaAiCounterBlockIdTcp15, AI_MAX_NUM_SHADER_ENGINES, 2, AI_NUM_TCP, - CntlMethodBySeAndInstance, 182, AI_COUNTER_NUM_PER_TCP, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block GDS - {"AI_GDS", kHsaAiCounterBlockIdGds, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 120, - AI_COUNTER_NUM_PER_GDS, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block VGT - {"AI_VGT", kHsaAiCounterBlockIdVgt, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 145, - AI_COUNTER_NUM_PER_VGT, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block IA - {"AI_IA", kHsaAiCounterBlockIdIa, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodBySe, 23, - AI_COUNTER_NUM_PER_IA, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block MC - {"AI_MC", kHsaAiCounterBlockIdMc, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 22, - AI_COUNTER_NUM_PER_MC, 0, 0, true, 0, 0, false, 0, 0}, - - // Temp commented out for Vega10 - // Counter block SRBM - /* - {"AI_SRBM", kHsaAiCounterBlockIdSrbm, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 19, - AI_COUNTER_NUM_PER_SRBM, 0, 0, true, 0, 0, false, 0, 0}, - */ - - // Counter block WD - {"AI_WD", kHsaAiCounterBlockIdWd, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 36, - AI_COUNTER_NUM_PER_WD, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block CPG - // Temp commented for Vega10 - /* - {"AI_CPG", kHsaAiCounterBlockIdCpg, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 48, - AI_COUNTER_NUM_PER_CPG, 0, 0, true, 0, 0, false, 0, 0}, - */ - - // Counter block CPC - // Temp commented for Vega10 - {"AI_CPC", kHsaAiCounterBlockIdCpc, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 34, - AI_COUNTER_NUM_PER_CPC, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block IOMMUV2 - {"AI_IOMMUV2", kHsaAiCounterBlockIdIommuV2, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 25, - 8, 0, 0, true, 0, 0, false, 0, 0}, - - // Counter block KernelDriver - {"AI_KD", kHsaAiCounterBlockIdKernelDriver, AI_MAX_NUM_SHADER_ENGINES, 2, 1, CntlMethodNone, 0, - 0, 0, 0, true, 0, 0, false, 0, 0}, - - // Name of the last line should be empty to indicate end of all counter groups - {"", kHsaAiCounterBlockIdBlocksLast, 0, 0, 0, CntlMethodNone, 0, 0, 0, 0, false, 0, 0, false, 0, - 0}}; - -extern const uint32_t Gfx9HwBlockCount = sizeof(Gfx9HwBlocks) / sizeof(GpuBlockInfo); - -/* - * The following tables contain register addresses of the SQ counter registers - */ - -/* - * SQ - */ -GpuCounterRegInfo AiSqCounterRegAddr[] = { - {mmSQ_PERFCOUNTER0_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER0_LO, mmSQ_PERFCOUNTER0_HI}, - {mmSQ_PERFCOUNTER1_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER1_LO, mmSQ_PERFCOUNTER1_HI}, - {mmSQ_PERFCOUNTER2_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER2_LO, mmSQ_PERFCOUNTER2_HI}, - {mmSQ_PERFCOUNTER3_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER3_LO, mmSQ_PERFCOUNTER3_HI}, - {mmSQ_PERFCOUNTER4_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER4_LO, mmSQ_PERFCOUNTER4_HI}, - {mmSQ_PERFCOUNTER5_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER5_LO, mmSQ_PERFCOUNTER5_HI}, - {mmSQ_PERFCOUNTER6_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER6_LO, mmSQ_PERFCOUNTER6_HI}, - {mmSQ_PERFCOUNTER7_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER7_LO, mmSQ_PERFCOUNTER7_HI}, - {mmSQ_PERFCOUNTER8_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER8_LO, mmSQ_PERFCOUNTER8_HI}, - {mmSQ_PERFCOUNTER9_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER9_LO, mmSQ_PERFCOUNTER9_HI}, - {mmSQ_PERFCOUNTER10_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER10_LO, - mmSQ_PERFCOUNTER10_HI}, - {mmSQ_PERFCOUNTER11_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER11_LO, - mmSQ_PERFCOUNTER11_HI}, - {mmSQ_PERFCOUNTER12_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER12_LO, - mmSQ_PERFCOUNTER12_HI}, - {mmSQ_PERFCOUNTER13_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER13_LO, - mmSQ_PERFCOUNTER13_HI}, - {mmSQ_PERFCOUNTER14_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER14_LO, - mmSQ_PERFCOUNTER14_HI}, - {mmSQ_PERFCOUNTER15_SELECT, mmSQ_PERFCOUNTER_CTRL, mmSQ_PERFCOUNTER15_LO, - mmSQ_PERFCOUNTER15_HI}}; - -/* - * DRMDMA - */ -GpuCounterRegInfo AiDrmdmaCounterRegAddr[] = { - {mmSDMA0_PERFMON_CNTL, 0, mmSDMA0_PERFCOUNTER0_RESULT, 0}, - {mmSDMA0_PERFMON_CNTL, 0, mmSDMA0_PERFCOUNTER1_RESULT, 0}, - {mmSDMA1_PERFMON_CNTL, 0, mmSDMA1_PERFCOUNTER0_RESULT, 0}, - {mmSDMA1_PERFMON_CNTL, 0, mmSDMA1_PERFCOUNTER1_RESULT, 0}, -}; - -/* - * IH - */ -GpuCounterRegInfo AiIhCounterRegAddr[] = {{mmIH_PERFMON_CNTL, 0, mmIH_PERFCOUNTER0_RESULT, 0}, - {mmIH_PERFMON_CNTL, 0, mmIH_PERFCOUNTER1_RESULT, 0}}; - -/* - * CPF - */ -GpuCounterRegInfo AiCpfCounterRegAddr[] = { - {mmCPF_PERFCOUNTER0_SELECT, 0, mmCPF_PERFCOUNTER0_LO, mmCPF_PERFCOUNTER0_HI}, - {mmCPF_PERFCOUNTER1_SELECT, 0, mmCPF_PERFCOUNTER1_LO, mmCPF_PERFCOUNTER1_HI}}; - -/* - * DRM - */ -GpuCounterRegInfo AiDrmCounterRegAddr[] = { - /* - {mmDRM_PERFCOUNTER1_SELECT, 0, mmDRM_PERFCOUNTER1_LO, mmDRM_PERFCOUNTER1_HI}, - {mmDRM_PERFCOUNTER2_SELECT, 0, mmDRM_PERFCOUNTER2_LO, mmDRM_PERFCOUNTER2_HI} - */ -}; - -/* - * GRBM - */ -GpuCounterRegInfo AiGrbmCounterRegAddr[] = { - {mmGRBM_PERFCOUNTER0_SELECT, 0, mmGRBM_PERFCOUNTER0_LO, mmGRBM_PERFCOUNTER0_HI}, - {mmGRBM_PERFCOUNTER1_SELECT, 0, mmGRBM_PERFCOUNTER1_LO, mmGRBM_PERFCOUNTER1_HI}}; - -/* - * GRBM_SE - */ -GpuCounterRegInfo AiGrbmSeCounterRegAddr[] = { - {mmGRBM_SE0_PERFCOUNTER_SELECT, 0, mmGRBM_SE0_PERFCOUNTER_LO, mmGRBM_SE0_PERFCOUNTER_HI}, - {mmGRBM_SE1_PERFCOUNTER_SELECT, 0, mmGRBM_SE1_PERFCOUNTER_LO, mmGRBM_SE1_PERFCOUNTER_HI}, - {mmGRBM_SE2_PERFCOUNTER_SELECT, 0, mmGRBM_SE2_PERFCOUNTER_LO, mmGRBM_SE2_PERFCOUNTER_HI}, - {mmGRBM_SE3_PERFCOUNTER_SELECT, 0, mmGRBM_SE3_PERFCOUNTER_LO, mmGRBM_SE3_PERFCOUNTER_HI}}; - -/* - * PA_SU - */ -GpuCounterRegInfo AiPaSuCounterRegAddr[] = { - {mmPA_SU_PERFCOUNTER0_SELECT, 0, mmPA_SU_PERFCOUNTER0_LO, mmPA_SU_PERFCOUNTER0_HI}, - {mmPA_SU_PERFCOUNTER1_SELECT, 0, mmPA_SU_PERFCOUNTER1_LO, mmPA_SU_PERFCOUNTER1_HI}, - {mmPA_SU_PERFCOUNTER2_SELECT, 0, mmPA_SU_PERFCOUNTER2_LO, mmPA_SU_PERFCOUNTER2_HI}, - {mmPA_SU_PERFCOUNTER3_SELECT, 0, mmPA_SU_PERFCOUNTER3_LO, mmPA_SU_PERFCOUNTER3_HI}}; - -/* - * PA_SC - */ -GpuCounterRegInfo AiPaScCounterRegAddr[] = { - {mmPA_SC_PERFCOUNTER0_SELECT, 0, mmPA_SC_PERFCOUNTER0_LO, mmPA_SC_PERFCOUNTER0_HI}, - {mmPA_SC_PERFCOUNTER1_SELECT, 0, mmPA_SC_PERFCOUNTER1_LO, mmPA_SC_PERFCOUNTER1_HI}, - {mmPA_SC_PERFCOUNTER2_SELECT, 0, mmPA_SC_PERFCOUNTER2_LO, mmPA_SC_PERFCOUNTER2_HI}, - {mmPA_SC_PERFCOUNTER3_SELECT, 0, mmPA_SC_PERFCOUNTER3_LO, mmPA_SC_PERFCOUNTER3_HI}}; - -/* - * SPI - */ -GpuCounterRegInfo AiSpiCounterRegAddr[] = { - {mmSPI_PERFCOUNTER0_SELECT, 0, mmSPI_PERFCOUNTER0_LO, mmSPI_PERFCOUNTER0_HI}, - {mmSPI_PERFCOUNTER1_SELECT, 0, mmSPI_PERFCOUNTER1_LO, mmSPI_PERFCOUNTER1_HI}, - {mmSPI_PERFCOUNTER2_SELECT, 0, mmSPI_PERFCOUNTER2_LO, mmSPI_PERFCOUNTER2_HI}, - {mmSPI_PERFCOUNTER3_SELECT, 0, mmSPI_PERFCOUNTER3_LO, mmSPI_PERFCOUNTER3_HI}, - {mmSPI_PERFCOUNTER4_SELECT, 0, mmSPI_PERFCOUNTER4_LO, mmSPI_PERFCOUNTER4_HI}, - {mmSPI_PERFCOUNTER5_SELECT, 0, mmSPI_PERFCOUNTER5_LO, mmSPI_PERFCOUNTER5_HI}}; - -/* - * TCA - */ -GpuCounterRegInfo AiTcaCounterRegAddr[] = { - {mmTCA_PERFCOUNTER0_SELECT, 0, mmTCA_PERFCOUNTER0_LO, mmTCA_PERFCOUNTER0_HI}, - {mmTCA_PERFCOUNTER1_SELECT, 0, mmTCA_PERFCOUNTER1_LO, mmTCA_PERFCOUNTER1_HI}, - {mmTCA_PERFCOUNTER2_SELECT, 0, mmTCA_PERFCOUNTER2_LO, mmTCA_PERFCOUNTER2_HI}, - {mmTCA_PERFCOUNTER3_SELECT, 0, mmTCA_PERFCOUNTER3_LO, mmTCA_PERFCOUNTER3_HI}}; - -/* - * TCC - */ -GpuCounterRegInfo AiTccCounterRegAddr[] = { - {mmTCC_PERFCOUNTER0_SELECT, 0, mmTCC_PERFCOUNTER0_LO, mmTCC_PERFCOUNTER0_HI}, - {mmTCC_PERFCOUNTER1_SELECT, 0, mmTCC_PERFCOUNTER1_LO, mmTCC_PERFCOUNTER1_HI}, - {mmTCC_PERFCOUNTER2_SELECT, 0, mmTCC_PERFCOUNTER2_LO, mmTCC_PERFCOUNTER2_HI}, - {mmTCC_PERFCOUNTER3_SELECT, 0, mmTCC_PERFCOUNTER3_LO, mmTCC_PERFCOUNTER3_HI}}; - -/* - * TCP - */ -GpuCounterRegInfo AiTcpCounterRegAddr[] = { - {mmTCP_PERFCOUNTER0_SELECT, 0, mmTCP_PERFCOUNTER0_LO, mmTCP_PERFCOUNTER0_HI}, - {mmTCP_PERFCOUNTER1_SELECT, 0, mmTCP_PERFCOUNTER1_LO, mmTCP_PERFCOUNTER1_HI}, - {mmTCP_PERFCOUNTER2_SELECT, 0, mmTCP_PERFCOUNTER2_LO, mmTCP_PERFCOUNTER2_HI}, - {mmTCP_PERFCOUNTER3_SELECT, 0, mmTCP_PERFCOUNTER3_LO, mmTCP_PERFCOUNTER3_HI}}; - -/* - * CB - */ -GpuCounterRegInfo AiCbCounterRegAddr[] = { - {mmCB_PERFCOUNTER0_SELECT, 0, mmCB_PERFCOUNTER0_LO, mmCB_PERFCOUNTER0_HI}, - {mmCB_PERFCOUNTER1_SELECT, 0, mmCB_PERFCOUNTER1_LO, mmCB_PERFCOUNTER1_HI}, - {mmCB_PERFCOUNTER2_SELECT, 0, mmCB_PERFCOUNTER2_LO, mmCB_PERFCOUNTER2_HI}, - {mmCB_PERFCOUNTER3_SELECT, 0, mmCB_PERFCOUNTER3_LO, mmCB_PERFCOUNTER3_HI}}; - -/* - * DB - */ -GpuCounterRegInfo AiDbCounterRegAddr[] = { - {mmDB_PERFCOUNTER0_SELECT, 0, mmDB_PERFCOUNTER0_LO, mmDB_PERFCOUNTER0_HI}, - {mmDB_PERFCOUNTER1_SELECT, 0, mmDB_PERFCOUNTER1_LO, mmDB_PERFCOUNTER1_HI}, - {mmDB_PERFCOUNTER2_SELECT, 0, mmDB_PERFCOUNTER2_LO, mmDB_PERFCOUNTER2_HI}, - {mmDB_PERFCOUNTER3_SELECT, 0, mmDB_PERFCOUNTER3_LO, mmDB_PERFCOUNTER3_HI}}; - -/* - * RLC - */ -GpuCounterRegInfo AiRlcCounterRegAddr[] = { - {mmRLC_PERFCOUNTER0_SELECT, 0, mmRLC_PERFCOUNTER0_LO, mmRLC_PERFCOUNTER0_HI}, - {mmRLC_PERFCOUNTER1_SELECT, 0, mmRLC_PERFCOUNTER1_LO, mmRLC_PERFCOUNTER1_HI}}; - -/* - * SC - */ -GpuCounterRegInfo AiScCounterRegAddr[] = { - {mmPA_SC_PERFCOUNTER0_SELECT, 0, mmPA_SC_PERFCOUNTER0_LO, mmPA_SC_PERFCOUNTER0_HI}, - {mmPA_SC_PERFCOUNTER1_SELECT, 0, mmPA_SC_PERFCOUNTER1_LO, mmPA_SC_PERFCOUNTER1_HI}, - {mmPA_SC_PERFCOUNTER2_SELECT, 0, mmPA_SC_PERFCOUNTER2_LO, mmPA_SC_PERFCOUNTER2_HI}, - {mmPA_SC_PERFCOUNTER3_SELECT, 0, mmPA_SC_PERFCOUNTER3_LO, mmPA_SC_PERFCOUNTER3_HI}, - {mmPA_SC_PERFCOUNTER4_SELECT, 0, mmPA_SC_PERFCOUNTER4_LO, mmPA_SC_PERFCOUNTER4_HI}, - {mmPA_SC_PERFCOUNTER5_SELECT, 0, mmPA_SC_PERFCOUNTER5_LO, mmPA_SC_PERFCOUNTER5_HI}, - {mmPA_SC_PERFCOUNTER6_SELECT, 0, mmPA_SC_PERFCOUNTER6_LO, mmPA_SC_PERFCOUNTER6_HI}, - {mmPA_SC_PERFCOUNTER7_SELECT, 0, mmPA_SC_PERFCOUNTER7_LO, mmPA_SC_PERFCOUNTER7_HI}}; - -/* - * SX - */ -GpuCounterRegInfo AiSxCounterRegAddr[] = { - {mmSX_PERFCOUNTER0_SELECT, 0, mmSX_PERFCOUNTER0_LO, mmSX_PERFCOUNTER0_HI}, - {mmSX_PERFCOUNTER1_SELECT, 0, mmSX_PERFCOUNTER1_LO, mmSX_PERFCOUNTER1_HI}, - {mmSX_PERFCOUNTER2_SELECT, 0, mmSX_PERFCOUNTER2_LO, mmSX_PERFCOUNTER2_HI}, - {mmSX_PERFCOUNTER3_SELECT, 0, mmSX_PERFCOUNTER3_LO, mmSX_PERFCOUNTER3_HI}}; - -/* - * TA - */ -GpuCounterRegInfo AiTaCounterRegAddr[] = { - {mmTA_PERFCOUNTER0_SELECT, 0, mmTA_PERFCOUNTER0_LO, mmTA_PERFCOUNTER0_HI}, - {mmTA_PERFCOUNTER1_SELECT, 0, mmTA_PERFCOUNTER1_LO, mmTA_PERFCOUNTER1_HI}}; - -/* - * TD - */ -GpuCounterRegInfo AiTdCounterRegAddr[] = { - {mmTD_PERFCOUNTER0_SELECT, 0, mmTD_PERFCOUNTER0_LO, mmTD_PERFCOUNTER0_HI}, - {mmTD_PERFCOUNTER1_SELECT, 0, mmTD_PERFCOUNTER1_LO, mmTD_PERFCOUNTER1_HI}}; - -/* - * GDS - */ -GpuCounterRegInfo AiGdsCounterRegAddr[] = { - {mmGDS_PERFCOUNTER0_SELECT, 0, mmGDS_PERFCOUNTER0_LO, mmGDS_PERFCOUNTER0_HI}, - {mmGDS_PERFCOUNTER1_SELECT, 0, mmGDS_PERFCOUNTER1_LO, mmGDS_PERFCOUNTER1_HI}, - {mmGDS_PERFCOUNTER2_SELECT, 0, mmGDS_PERFCOUNTER2_LO, mmGDS_PERFCOUNTER2_HI}, - {mmGDS_PERFCOUNTER3_SELECT, 0, mmGDS_PERFCOUNTER3_LO, mmGDS_PERFCOUNTER3_HI}}; - -/* - * VGT - */ -GpuCounterRegInfo AiVgtCounterRegAddr[] = { - {mmVGT_PERFCOUNTER0_SELECT, 0, mmVGT_PERFCOUNTER0_LO, mmVGT_PERFCOUNTER0_HI}, - {mmVGT_PERFCOUNTER1_SELECT, 0, mmVGT_PERFCOUNTER1_LO, mmVGT_PERFCOUNTER1_HI}, - {mmVGT_PERFCOUNTER2_SELECT, 0, mmVGT_PERFCOUNTER2_LO, mmVGT_PERFCOUNTER2_HI}, - {mmVGT_PERFCOUNTER3_SELECT, 0, mmVGT_PERFCOUNTER3_LO, mmVGT_PERFCOUNTER3_HI}}; - -/* - * IA - */ -GpuCounterRegInfo AiIaCounterRegAddr[] = { - {mmIA_PERFCOUNTER0_SELECT, 0, mmIA_PERFCOUNTER0_LO, mmIA_PERFCOUNTER0_HI}, - {mmIA_PERFCOUNTER1_SELECT, 0, mmIA_PERFCOUNTER1_LO, mmIA_PERFCOUNTER1_HI}, - {mmIA_PERFCOUNTER2_SELECT, 0, mmIA_PERFCOUNTER2_LO, mmIA_PERFCOUNTER2_HI}, - {mmIA_PERFCOUNTER3_SELECT, 0, mmIA_PERFCOUNTER3_LO, mmIA_PERFCOUNTER3_HI}}; - -/* - * MC - */ -GpuCounterRegInfo AiMcCounterRegAddr[] = { - /* - - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_A_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_A_I1__VI}, - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_B_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_B_I1__VI}, - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_C_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_C_I1__VI}, - {mmMC_SEQ_PERF_SEQ_CTL__SI__VI, 0, mmMC_SEQ_PERF_SEQ_CNT_D_I0__VI, - mmMC_SEQ_PERF_SEQ_CNT_D_I1__VI} - - */ -}; - -/* - * SRBM - */ -GpuCounterRegInfo AiSrbmCounterRegAddr[] = { - /* - {mmSRBM_PERFCOUNTER0_SELECT, 0, mmSRBM_PERFCOUNTER0_LO, - mmSRBM_PERFCOUNTER0_HI}, - {mmSRBM_PERFCOUNTER1_SELECT, 0, mmSRBM_PERFCOUNTER1_LO, - mmSRBM_PERFCOUNTER1_HI} - */ -}; - -/* - * WD - */ -GpuCounterRegInfo AiWdCounterRegAddr[] = { - {mmWD_PERFCOUNTER0_SELECT, 0, mmWD_PERFCOUNTER0_LO, mmWD_PERFCOUNTER0_HI}, - {mmWD_PERFCOUNTER1_SELECT, 0, mmWD_PERFCOUNTER1_LO, mmWD_PERFCOUNTER1_HI}, - {mmWD_PERFCOUNTER2_SELECT, 0, mmWD_PERFCOUNTER2_LO, mmWD_PERFCOUNTER2_HI}, - {mmWD_PERFCOUNTER3_SELECT, 0, mmWD_PERFCOUNTER3_LO, mmWD_PERFCOUNTER3_HI}}; - -/* - * CPG - */ -GpuCounterRegInfo AiCpgCounterRegAddr[] = { - {mmCPG_PERFCOUNTER0_SELECT, 0, mmCPG_PERFCOUNTER0_LO, mmCPG_PERFCOUNTER0_HI}, - {mmCPG_PERFCOUNTER1_SELECT, 0, mmCPG_PERFCOUNTER1_LO, mmCPG_PERFCOUNTER1_HI}}; - -/* - * CPC - */ -GpuCounterRegInfo AiCpcCounterRegAddr[] = { - {mmCPC_PERFCOUNTER0_SELECT, 0, mmCPC_PERFCOUNTER0_LO, mmCPC_PERFCOUNTER0_HI}, - {mmCPC_PERFCOUNTER1_SELECT, 0, mmCPC_PERFCOUNTER1_LO, mmCPC_PERFCOUNTER1_HI}}; - -GpuPrivCounterBlockId AiBlockIdSq = {{0xb5c396b6, 0x47e4d310, 0xc35cfc86, 0x08f53a04}}; -GpuPrivCounterBlockId AiBlockIdMc = {{0x13900b57, 0x4d984956, 0x5268d081, 0x9cf53719}}; -GpuPrivCounterBlockId AiBlockIdIommuV2 = {{0x80969879, 0x4be6b0f6, 0x636af697, 0x1d10f500}}; -GpuPrivCounterBlockId AiBlockIdKernelDriver = {{0xea9b5ae1, 0x44b36c3f, 0xf0da5489, 0x0aa96575}}; - -} // pm4_profile diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_block_info.h b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_block_info.h deleted file mode 100644 index 078ef60145..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_block_info.h +++ /dev/null @@ -1,245 +0,0 @@ -#ifndef _AI_BLOCKINFO_H_ -#define _AI_BLOCKINFO_H_ - -#include "gpu_block_info.h" - -namespace pm4_profile { - -// MAX Number of block instances for ARCTIC ISLANDS (From Vega10) -// Values are found here //gfxip/gfx8/main/src/meta/features/variant/Fiji/album.dj - -// @brief Number of block instances. - -// Number of CB block instances per SE -// and number of Perf Cntrs per CB block -#define AI_NUM_CB 4 -#define AI_COUNTER_NUM_PER_CB 4 - -// Number of DB block instances per SE -// and number of Perf Cntrs per DB block -#define AI_NUM_DB 4 -#define AI_COUNTER_NUM_PER_DB 4 - -// Number of TA block instances per SE -// and number of Perf Cntrs per TA block -#define AI_NUM_TA 16 -#define AI_COUNTER_NUM_PER_TA 2 - -// Number of TD block instances per SE -// and number of Perf Cntrs per TD block -#define AI_NUM_TD 16 -#define AI_COUNTER_NUM_PER_TD 2 - -// Number of TCP block instances per SE -// and number of Perf Cntrs per TCP block -#define AI_NUM_TCP 16 -#define AI_COUNTER_NUM_PER_TCP 4 - -// Number of TCA block instances per chip -// and number of Perf Cntrs per TCA block -#define AI_NUM_TCA 2 -#define AI_COUNTER_NUM_PER_TCA 4 - -// Number of TCC block instances per chip -// and number of Perf Cntrs per TCC block -#define AI_NUM_TCC 16 -#define AI_COUNTER_NUM_PER_TCC 4 - -// Number of SDMA block instances per chip -// and number of Perf Cntrs per SDMA block -#define AI_NUM_SDMA 2 - -// Number of counter registers per block for arctic islands -#define AI_COUNTER_NUM_PER_DRM 2 -#define AI_COUNTER_NUM_PER_DRMDMA 2 -#define AI_COUNTER_NUM_PER_IH 2 -#define AI_COUNTER_NUM_PER_SRBM 2 -#define AI_COUNTER_NUM_PER_CPF 2 -#define AI_COUNTER_NUM_PER_GRBM 2 -#define AI_COUNTER_NUM_PER_GRBMSE 4 -#define AI_COUNTER_NUM_PER_PA_SU 4 -#define AI_COUNTER_NUM_PER_RLC 2 -#define AI_COUNTER_NUM_PER_PA_SC 8 -#define AI_COUNTER_NUM_PER_SPI 6 // [Shucai: To do: double check the value] -#define AI_COUNTER_NUM_PER_SQ 16 -#define AI_COUNTER_NUM_PER_SX 4 -#define AI_COUNTER_NUM_PER_GDS 4 -#define AI_COUNTER_NUM_PER_VGT 4 -#define AI_COUNTER_NUM_PER_IA 4 -#define AI_COUNTER_NUM_PER_MC 4 -#define AI_COUNTER_NUM_PER_TCS 4 -#define AI_COUNTER_NUM_PER_WD 4 -#define AI_COUNTER_NUM_PER_CPG 2 -#define AI_COUNTER_NUM_PER_CPC 2 -#define AI_COUNTER_NUM_PER_VM 1 -#define AI_COUNTER_NUM_PER_VM_MD 1 -#define AI_COUNTER_NUM_PER_PIPESTATS 12 - -#define AI_MAX_NUM_SHADER_ENGINES 1 - -// Enumeration of AI hardware counter blocks -typedef enum HsaAiCounterBlockId { - kHsaAiCounterBlockIdCb0 = 0, - kHsaAiCounterBlockIdCb1, - kHsaAiCounterBlockIdCb2, - kHsaAiCounterBlockIdCb3, - - // Temp commented out for Vega10 - // kHsaAiCounterBlockIdCpf, - - kHsaAiCounterBlockIdDb0, - kHsaAiCounterBlockIdDb1, - kHsaAiCounterBlockIdDb2, - kHsaAiCounterBlockIdDb3, - - kHsaAiCounterBlockIdGrbm, - kHsaAiCounterBlockIdGrbmSe, - kHsaAiCounterBlockIdPaSu, - kHsaAiCounterBlockIdPaSc, - kHsaAiCounterBlockIdSpi, - - kHsaAiCounterBlockIdSq, - kHsaAiCounterBlockIdSqGs, - kHsaAiCounterBlockIdSqVs, - kHsaAiCounterBlockIdSqPs, - kHsaAiCounterBlockIdSqHs, - kHsaAiCounterBlockIdSqCs, - - kHsaAiCounterBlockIdSx, - - kHsaAiCounterBlockIdTa0, - kHsaAiCounterBlockIdTa1, - kHsaAiCounterBlockIdTa2, - kHsaAiCounterBlockIdTa3, - kHsaAiCounterBlockIdTa4, - kHsaAiCounterBlockIdTa5, - kHsaAiCounterBlockIdTa6, - kHsaAiCounterBlockIdTa7, - kHsaAiCounterBlockIdTa8, - kHsaAiCounterBlockIdTa9, - kHsaAiCounterBlockIdTa10, - kHsaAiCounterBlockIdTa11, - kHsaAiCounterBlockIdTa12, - kHsaAiCounterBlockIdTa13, - kHsaAiCounterBlockIdTa14, - kHsaAiCounterBlockIdTa15, - - kHsaAiCounterBlockIdTca0, - kHsaAiCounterBlockIdTca1, - - kHsaAiCounterBlockIdTcc0, - kHsaAiCounterBlockIdTcc1, - kHsaAiCounterBlockIdTcc2, - kHsaAiCounterBlockIdTcc3, - kHsaAiCounterBlockIdTcc4, - kHsaAiCounterBlockIdTcc5, - kHsaAiCounterBlockIdTcc6, - kHsaAiCounterBlockIdTcc7, - kHsaAiCounterBlockIdTcc8, - kHsaAiCounterBlockIdTcc9, - kHsaAiCounterBlockIdTcc10, - kHsaAiCounterBlockIdTcc11, - kHsaAiCounterBlockIdTcc12, - kHsaAiCounterBlockIdTcc13, - kHsaAiCounterBlockIdTcc14, - kHsaAiCounterBlockIdTcc15, - - kHsaAiCounterBlockIdTd0, - kHsaAiCounterBlockIdTd1, - kHsaAiCounterBlockIdTd2, - kHsaAiCounterBlockIdTd3, - kHsaAiCounterBlockIdTd4, - kHsaAiCounterBlockIdTd5, - kHsaAiCounterBlockIdTd6, - kHsaAiCounterBlockIdTd7, - kHsaAiCounterBlockIdTd8, - kHsaAiCounterBlockIdTd9, - kHsaAiCounterBlockIdTd10, - kHsaAiCounterBlockIdTd11, - kHsaAiCounterBlockIdTd12, - kHsaAiCounterBlockIdTd13, - kHsaAiCounterBlockIdTd14, - kHsaAiCounterBlockIdTd15, - - kHsaAiCounterBlockIdTcp0, - kHsaAiCounterBlockIdTcp1, - kHsaAiCounterBlockIdTcp2, - kHsaAiCounterBlockIdTcp3, - kHsaAiCounterBlockIdTcp4, - kHsaAiCounterBlockIdTcp5, - kHsaAiCounterBlockIdTcp6, - kHsaAiCounterBlockIdTcp7, - kHsaAiCounterBlockIdTcp8, - kHsaAiCounterBlockIdTcp9, - kHsaAiCounterBlockIdTcp10, - kHsaAiCounterBlockIdTcp11, - kHsaAiCounterBlockIdTcp12, - kHsaAiCounterBlockIdTcp13, - kHsaAiCounterBlockIdTcp14, - kHsaAiCounterBlockIdTcp15, - - kHsaAiCounterBlockIdGds, - kHsaAiCounterBlockIdVgt, - kHsaAiCounterBlockIdIa, - kHsaAiCounterBlockIdMc, - - // Temp commented out for Vega10 - // kHsaAiCounterBlockIdSrbm, - - kHsaAiCounterBlockIdTcs, - kHsaAiCounterBlockIdWd, - - // Temp commented out for Vega10 - // kHsaAiCounterBlockIdCpg, - - kHsaAiCounterBlockIdCpc, - - // Counters retrieved by KFD - kHsaAiCounterBlockIdIommuV2, - kHsaAiCounterBlockIdKernelDriver, - - kHsaAiCounterBlockIdCpPipeStats, - kHsaAiCounterBlockIdHwInfo, - kHsaAiCounterBlockIdBlocksFirst = kHsaAiCounterBlockIdCb0, - kHsaAiCounterBlockIdBlocksLast = kHsaAiCounterBlockIdHwInfo -} HsaAiCounterBlockId; - -extern GpuBlockInfo Gfx9HwBlocks[]; -extern GpuCounterRegInfo AiSqCounterRegAddr[]; -extern GpuCounterRegInfo AiCbCounterRegAddr[]; -extern GpuCounterRegInfo AiDrmdmaCounterRegAddr[]; -extern GpuCounterRegInfo AiIhCounterRegAddr[]; -extern GpuCounterRegInfo AiCpfCounterRegAddr[]; -extern GpuCounterRegInfo AiCpgCounterRegAddr[]; -extern GpuCounterRegInfo AiCpcCounterRegAddr[]; -extern GpuCounterRegInfo AiDrmCounterRegAddr[]; -extern GpuCounterRegInfo AiGrbmCounterRegAddr[]; -extern GpuCounterRegInfo AiGrbmSeCounterRegAddr[]; -extern GpuCounterRegInfo AiPaSuCounterRegAddr[]; -extern GpuCounterRegInfo AiPaScCounterRegAddr[]; -extern GpuCounterRegInfo AiSpiCounterRegAddr[]; -extern GpuCounterRegInfo AiTcaCounterRegAddr[]; -extern GpuCounterRegInfo AiTccCounterRegAddr[]; -extern GpuCounterRegInfo AiTcpCounterRegAddr[]; -extern GpuCounterRegInfo AiDbCounterRegAddr[]; -extern GpuCounterRegInfo AiRlcCounterRegAddr[]; -extern GpuCounterRegInfo AiScCounterRegAddr[]; -extern GpuCounterRegInfo AiSxCounterRegAddr[]; -extern GpuCounterRegInfo AiTaCounterRegAddr[]; -extern GpuCounterRegInfo AiTdCounterRegAddr[]; -extern GpuCounterRegInfo AiGdsCounterRegAddr[]; -extern GpuCounterRegInfo AiVgtCounterRegAddr[]; -extern GpuCounterRegInfo AiIaCounterRegAddr[]; -extern GpuCounterRegInfo AiMcCounterRegAddr[]; -extern GpuCounterRegInfo AiSrbmCounterRegAddr[]; -// No Tcs Counter block on AI -// extern GpuCounterRegInfo AiTcsCounterRegAddr[]; -extern GpuCounterRegInfo AiWdCounterRegAddr[]; - -extern GpuPrivCounterBlockId AiBlockIdSq; -extern GpuPrivCounterBlockId AiBlockIdMc; -extern GpuPrivCounterBlockId AiBlockIdIommuV2; -extern GpuPrivCounterBlockId AiBlockIdKernelDriver; -} - -#endif // _AI_BLOCKINFO_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_perf_counter.cpp b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_perf_counter.cpp deleted file mode 100644 index eb5e30cab0..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_perf_counter.cpp +++ /dev/null @@ -1,1327 +0,0 @@ -#include - -#include "gfxip/gfx9/gfx9_registers.h" -#include "gfxip/gfx9/gfx9_typedef.h" -#include "gfxip/gfx9/gfx9_offset.h" -#include "gfxip/gfx9/gfx9_pm4defs.h" - -#include "gfx9_perf_counter.h" -#include "gfx9_block_info.h" -#include "cmdwriter.h" - -using namespace std; -using namespace pm4_profile; -using namespace pm4_profile::gfx9; - -// A flag to indicate the current packet is for copy register value -#define MAX_REG_NUM 100 -#define COPY_DATA_FLAG 0xFFFFFFFF - -namespace pm4_profile { - -Gfx9PerfCounter::Gfx9PerfCounter() { - // Initialize the number of shader engines - num_se_ = 4; - Init(); -} - -void Gfx9PerfCounter::Init() { - // Initialize the value to use in resetting GRBM - regGRBM_GFX_INDEX grbm_gfx_index; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - reset_grbm_ = grbm_gfx_index.u32All; -} - -void Gfx9PerfCounter::begin(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, - const CountersMap& countersMap) { - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, reset_grbm_); - - // Disable RLC Perfmon Clock Gating - // On Vega this is needed to collect Perf Cntrs - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmRLC_PERFMON_CLK_CNTL, 1); - - // Reset the counter list - regCP_PERFMON_CNTL cp_perfmon_cntl = {0}; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL, cp_perfmon_cntl.u32All); - - // Iterate through the list of blocks to generate Pm4 commands to - // program corresponding perf counters of each block - for (CountersMap::const_iterator block_it = countersMap.begin(); block_it != countersMap.end(); - ++block_it) { - const uint32_t block_id = block_it->first; - const CountersVec& counters = block_it->second; - const uint32_t counter_count = counters.size(); - - // Iterate through each enabled perf counter and building - // corresponding Pm4 commands to program the various control - // registers involved - for (uint32_t ind = 0; ind < counter_count; ++ind) { - const uint32_t counter_id = counters[ind]; - - // Build the list of control registers to program which - // varies per perf counter block - uint32_t reg_addr[MAX_REG_NUM], reg_val[MAX_REG_NUM]; - const uint32_t reg_num = - BuildCounterSelRegister(ind, reg_addr, reg_val, block_id, counter_id); - - // Build the list of Pm4 commands that support control - // register programming - for (uint32_t n = 0; n < reg_num; ++n) { - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, reg_addr[n], reg_val[n]); - } - } - } - - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, reset_grbm_); - - // Program Compute_Perfcount_Enable register to support perf counting - regCOMPUTE_PERFCOUNT_ENABLE cp_perfcount_enable; - cp_perfcount_enable.u32All = 0; - cp_perfcount_enable.bits.PERFCOUNT_ENABLE = 1; - cmdWriter->BuildWriteShRegPacket(cmdBuff, mmCOMPUTE_PERFCOUNT_ENABLE, cp_perfcount_enable.u32All); - - // Reset the counter list - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL, cp_perfmon_cntl.u32All); - - // Start the counter list - cp_perfmon_cntl.bits.PERFMON_STATE = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL, cp_perfmon_cntl.u32All); - - // Issue barrier command to apply the commands to configure perfcounters - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); -} - -uint32_t Gfx9PerfCounter::end(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, - const CountersMap& countersMap, void* dataBuff) { - // Issue barrier command to wait for dispatch to complete - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Build PM4 packet to stop and freeze counters - regCP_PERFMON_CNTL cp_perfmon_cntl; - cp_perfmon_cntl.u32All = 0; - cp_perfmon_cntl.bits.PERFMON_STATE = 2; - cp_perfmon_cntl.bits.PERFMON_SAMPLE_ENABLE = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmCP_PERFMON_CNTL, cp_perfmon_cntl.u32All); - - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, reset_grbm_); - - // Iterate through the list of blocks to create PM4 packets to read counter values - uint32_t total_counter_num = 0; - for (CountersMap::const_iterator block_it = countersMap.begin(); block_it != countersMap.end(); - ++block_it) { - const uint32_t block_id = block_it->first; - const uint32_t counter_count = block_it->second.size(); - - for (uint32_t ind = 0; ind < counter_count; ++ind) { - // retrieve the registers to be set - uint32_t reg_addr[MAX_REG_NUM], reg_val[MAX_REG_NUM]; - const uint32_t reg_num = BuildCounterReadRegisters(ind, block_id, reg_addr, reg_val); - - for (uint32_t n = 0; n < reg_num; n++) { - if (reg_val[n] == COPY_DATA_FLAG) { - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_REG, reg_addr[n], 0, - ((uint32_t*)dataBuff) + total_counter_num, - COPY_DATA_SEL_COUNT_1DW, false); - total_counter_num++; - } else { - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, reg_addr[n], reg_val[n]); - } - } - } - } - - // Reset Grbm to its default state - broadcast - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, reset_grbm_); - - // Enable RLC Perfmon Clock Gating. On Vega this is - // was disabled during Perf Cntrs collection session - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmRLC_PERFMON_CLK_CNTL, 0); - - return total_counter_num * sizeof(uint32_t); -} - -uint32_t Gfx9PerfCounter::ProgramTcpCntrs(uint32_t tcpRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaAiCounterBlockIdTcp0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX; - regIdx++; - - regTCP_PERFCOUNTER0_SELECT tcp_perf_counter_select; - tcp_perf_counter_select.u32All = 0; - tcp_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = tcp_perf_counter_select.u32All; - regAddr[regIdx] = AiTcpCounterRegAddr[tcpRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx9PerfCounter::ProgramTdCntrs(uint32_t tdRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaAiCounterBlockIdTd0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX; - regIdx++; - - regTD_PERFCOUNTER0_SELECT td_perf_counter_select; - td_perf_counter_select.u32All = 0; - td_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[regIdx] = td_perf_counter_select.u32All; - regAddr[regIdx] = AiTdCounterRegAddr[tdRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx9PerfCounter::ProgramTccCntrs(uint32_t tccRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaAiCounterBlockIdTcc0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX; - regIdx++; - - regTCC_PERFCOUNTER0_SELECT tcc_perf_counter_select; - tcc_perf_counter_select.u32All = 0; - tcc_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = tcc_perf_counter_select.u32All; - regAddr[regIdx] = AiTccCounterRegAddr[tccRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx9PerfCounter::ProgramTcaCntrs(uint32_t tcaRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaAiCounterBlockIdTca0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX; - regIdx++; - - regTCA_PERFCOUNTER0_SELECT tca_perf_counter_select; - tca_perf_counter_select.u32All = 0; - tca_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = tca_perf_counter_select.u32All; - regAddr[regIdx] = AiTcaCounterRegAddr[tcaRegIdx].counterSelRegAddr; - regIdx++; - return regIdx; -} - -uint32_t Gfx9PerfCounter::ProgramTaCntrs(uint32_t taRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - regGRBM_GFX_INDEX grbm_gfx_index; - - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_INDEX = blkId - kHsaAiCounterBlockIdTa0; - - uint32_t regIdx = 0; - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX; - regIdx++; - - regTA_PERFCOUNTER0_SELECT ta_perf_counter_select; - ta_perf_counter_select.u32All = 0; - ta_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = ta_perf_counter_select.u32All; - regAddr[regIdx] = AiTaCounterRegAddr[taRegIdx].counterSelRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx9PerfCounter::ProgramSQCntrs(uint32_t sqRegIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx) { - uint32_t regIdx = 0; - - // Program the SQ Counter Select Register - regSQ_PERFCOUNTER0_SELECT sq_cntr_sel; - sq_cntr_sel.u32All = 0; - sq_cntr_sel.bits.SIMD_MASK = 0xF; - sq_cntr_sel.bits.SQC_BANK_MASK = 0xF; - sq_cntr_sel.bits.SQC_CLIENT_MASK = 0xF; - sq_cntr_sel.bits.PERF_SEL = blkCntrIdx; - regVal[regIdx] = sq_cntr_sel.u32All; - regAddr[regIdx] = AiSqCounterRegAddr[sqRegIdx].counterSelRegAddr; - regIdx++; - - // Program the SQ Counter Mask Register - regSQ_PERFCOUNTER_MASK sq_cntr_mask; - sq_cntr_mask.u32All = 0; - sq_cntr_mask.bits.SH0_MASK = 0xFFFF; - sq_cntr_mask.bits.SH1_MASK = 0xFFFF; - regVal[regIdx] = sq_cntr_mask.u32All; - regAddr[regIdx] = mmSQ_PERFCOUNTER_MASK; - regIdx++; - - // Initialize the register content - // Program the SQ Counter Control Register - regSQ_PERFCOUNTER_CTRL sq_cntr_ctrl; - sq_cntr_ctrl.u32All = 0; - if (blkId == kHsaAiCounterBlockIdSq) { - sq_cntr_ctrl.bits.PS_EN = 0x1; - sq_cntr_ctrl.bits.VS_EN = 0x1; - sq_cntr_ctrl.bits.GS_EN = 0x1; - sq_cntr_ctrl.bits.HS_EN = 0x1; - sq_cntr_ctrl.bits.CS_EN = 0x1; - } else if (blkId == kHsaAiCounterBlockIdSqGs) { - sq_cntr_ctrl.bits.GS_EN = 0x1; - } else if (blkId == kHsaAiCounterBlockIdSqVs) { - sq_cntr_ctrl.bits.VS_EN = 0x1; - } else if (blkId == kHsaAiCounterBlockIdSqPs) { - sq_cntr_ctrl.bits.PS_EN = 0x1; - } else if (blkId == kHsaAiCounterBlockIdSqHs) { - sq_cntr_ctrl.bits.HS_EN = 0x1; - } else if (blkId == kHsaAiCounterBlockIdSqCs) { - sq_cntr_ctrl.bits.CS_EN = 0x1; - } - - regVal[regIdx] = sq_cntr_ctrl.u32All; - regAddr[regIdx] = AiSqCounterRegAddr[sqRegIdx].counterCntlRegAddr; - regIdx++; - - return regIdx; -} - -uint32_t Gfx9PerfCounter::BuildCounterSelRegister(uint32_t cntrIdx, uint32_t* regAddr, - uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx) { - uint32_t instance_index = 0; - regGRBM_GFX_INDEX grbm_gfx_index = {0}; - uint32_t regIdx = 0; - - switch (blkId) { - // Program counters belonging to SQ block - case kHsaAiCounterBlockIdSq: - case kHsaAiCounterBlockIdSqGs: - case kHsaAiCounterBlockIdSqVs: - case kHsaAiCounterBlockIdSqPs: - case kHsaAiCounterBlockIdSqHs: - case kHsaAiCounterBlockIdSqCs: - return ProgramSQCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaAiCounterBlockIdCb0: - case kHsaAiCounterBlockIdCb1: - case kHsaAiCounterBlockIdCb2: - case kHsaAiCounterBlockIdCb3: { - regIdx = 0; - instance_index = blkId - kHsaAiCounterBlockIdCb0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER0_LO; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER0_HI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER1_LO; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER1_HI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER2_LO; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER2_HI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER3_LO; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmCB_PERFCOUNTER3_HI; - regIdx++; - - regCB_PERFCOUNTER0_SELECT cb_perf_counter_select; - cb_perf_counter_select.u32All = 0; - cb_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[regIdx] = cb_perf_counter_select.u32All; - regAddr[regIdx] = AiCbCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx++; - - break; - } - - // Temp commented for Vega10 - /* - case kHsaAiCounterBlockIdCpf: { - regCPF_PERFCOUNTER0_SELECT cpf_perf_counter_select; - cpf_perf_counter_select.u32All = 0; - cpf_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - - regVal[0] = cpf_perf_counter_select.u32All; - regAddr[0] = AiCpfCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - */ - - case kHsaAiCounterBlockIdDb0: - case kHsaAiCounterBlockIdDb1: - case kHsaAiCounterBlockIdDb2: - case kHsaAiCounterBlockIdDb3: { - instance_index = blkId - kHsaAiCounterBlockIdDb0; - regIdx = 0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - regVal[regIdx] = grbm_gfx_index.u32All; - regAddr[regIdx] = mmGRBM_GFX_INDEX; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER0_LO; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER0_HI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER1_LO; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER1_HI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER2_LO; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER2_HI; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER3_LO; - regIdx++; - regVal[regIdx] = 0; - regAddr[regIdx] = mmDB_PERFCOUNTER3_HI; - regIdx++; - - regDB_PERFCOUNTER0_SELECT db_perf_counter_select; - db_perf_counter_select.u32All = 0; - db_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[regIdx] = db_perf_counter_select.u32All; - regAddr[regIdx] = AiDbCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx++; - break; - } - - case kHsaAiCounterBlockIdGrbm: { - regGRBM_PERFCOUNTER0_SELECT grbm_perf_counter_select; - grbm_perf_counter_select.u32All = 0; - grbm_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = grbm_perf_counter_select.u32All; - regAddr[0] = AiGrbmCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaAiCounterBlockIdGrbmSe: { - regGRBM_SE0_PERFCOUNTER_SELECT grbm_se0_perf_counter_select; - grbm_se0_perf_counter_select.u32All = 0; - grbm_se0_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = grbm_se0_perf_counter_select.u32All; - regAddr[0] = AiGrbmSeCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaAiCounterBlockIdPaSu: { - regPA_SU_PERFCOUNTER0_SELECT pa_su_perf_counter_select; - pa_su_perf_counter_select.u32All = 0; - pa_su_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = pa_su_perf_counter_select.u32All; - regAddr[0] = AiPaSuCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaAiCounterBlockIdPaSc: { - regPA_SC_PERFCOUNTER0_SELECT pa_sc_perf_counter_select; - pa_sc_perf_counter_select.u32All = 0; - pa_sc_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = pa_sc_perf_counter_select.u32All; - regAddr[0] = AiPaScCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaAiCounterBlockIdSpi: { - regSPI_PERFCOUNTER0_SELECT spi_perf_counter_select; - spi_perf_counter_select.u32All = 0; - spi_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = spi_perf_counter_select.u32All; - regAddr[0] = AiSpiCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaAiCounterBlockIdSx: { - regIdx = 0; - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER0_LO; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER0_HI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER1_LO; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER1_HI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER2_LO; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER2_HI; - regIdx++; - - regVal[regIdx] = 0; - regAddr[regIdx] = mmSX_PERFCOUNTER3_LO; - regIdx++; - - regSX_PERFCOUNTER0_SELECT sx_perf_counter_select; - sx_perf_counter_select.u32All = 0; - sx_perf_counter_select.bits.PERFCOUNTER_SELECT = blkCntrIdx; - regVal[regIdx] = sx_perf_counter_select.u32All; - regAddr[regIdx] = AiSxCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx++; - break; - } - - case kHsaAiCounterBlockIdTa0: - case kHsaAiCounterBlockIdTa1: - case kHsaAiCounterBlockIdTa2: - case kHsaAiCounterBlockIdTa3: - case kHsaAiCounterBlockIdTa4: - case kHsaAiCounterBlockIdTa5: - case kHsaAiCounterBlockIdTa6: - case kHsaAiCounterBlockIdTa7: - case kHsaAiCounterBlockIdTa8: - case kHsaAiCounterBlockIdTa9: - case kHsaAiCounterBlockIdTa10: - case kHsaAiCounterBlockIdTa11: - case kHsaAiCounterBlockIdTa12: - case kHsaAiCounterBlockIdTa13: - case kHsaAiCounterBlockIdTa14: - case kHsaAiCounterBlockIdTa15: - return ProgramTaCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaAiCounterBlockIdTca0: - case kHsaAiCounterBlockIdTca1: - return ProgramTcaCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaAiCounterBlockIdTcc0: - case kHsaAiCounterBlockIdTcc1: - case kHsaAiCounterBlockIdTcc2: - case kHsaAiCounterBlockIdTcc3: - case kHsaAiCounterBlockIdTcc4: - case kHsaAiCounterBlockIdTcc5: - case kHsaAiCounterBlockIdTcc6: - case kHsaAiCounterBlockIdTcc7: - case kHsaAiCounterBlockIdTcc8: - case kHsaAiCounterBlockIdTcc9: - case kHsaAiCounterBlockIdTcc10: - case kHsaAiCounterBlockIdTcc11: - case kHsaAiCounterBlockIdTcc12: - case kHsaAiCounterBlockIdTcc13: - case kHsaAiCounterBlockIdTcc14: - case kHsaAiCounterBlockIdTcc15: - return ProgramTccCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaAiCounterBlockIdTd0: - case kHsaAiCounterBlockIdTd1: - case kHsaAiCounterBlockIdTd2: - case kHsaAiCounterBlockIdTd3: - case kHsaAiCounterBlockIdTd4: - case kHsaAiCounterBlockIdTd5: - case kHsaAiCounterBlockIdTd6: - case kHsaAiCounterBlockIdTd7: - case kHsaAiCounterBlockIdTd8: - case kHsaAiCounterBlockIdTd9: - case kHsaAiCounterBlockIdTd10: - case kHsaAiCounterBlockIdTd11: - case kHsaAiCounterBlockIdTd12: - case kHsaAiCounterBlockIdTd13: - case kHsaAiCounterBlockIdTd14: - case kHsaAiCounterBlockIdTd15: - return ProgramTdCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaAiCounterBlockIdTcp0: - case kHsaAiCounterBlockIdTcp1: - case kHsaAiCounterBlockIdTcp2: - case kHsaAiCounterBlockIdTcp3: - case kHsaAiCounterBlockIdTcp4: - case kHsaAiCounterBlockIdTcp5: - case kHsaAiCounterBlockIdTcp6: - case kHsaAiCounterBlockIdTcp7: - case kHsaAiCounterBlockIdTcp8: - case kHsaAiCounterBlockIdTcp9: - case kHsaAiCounterBlockIdTcp10: - case kHsaAiCounterBlockIdTcp11: - case kHsaAiCounterBlockIdTcp12: - case kHsaAiCounterBlockIdTcp13: - case kHsaAiCounterBlockIdTcp14: - case kHsaAiCounterBlockIdTcp15: - return ProgramTcpCntrs(cntrIdx, regAddr, regVal, blkId, blkCntrIdx); - - case kHsaAiCounterBlockIdGds: { - regGDS_PERFCOUNTER0_SELECT gds_perf_counter_select; - gds_perf_counter_select.u32All = 0; - gds_perf_counter_select.bits.PERFCOUNTER_SELECT = blkCntrIdx; - regVal[0] = gds_perf_counter_select.u32All; - regAddr[0] = AiGdsCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaAiCounterBlockIdVgt: { - regVGT_PERFCOUNTER0_SELECT vgt_perf_counter_select; - vgt_perf_counter_select.u32All = 0; - vgt_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = vgt_perf_counter_select.u32All; - regAddr[0] = AiVgtCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - case kHsaAiCounterBlockIdIa: { - regIA_PERFCOUNTER0_SELECT ia_perf_counter_select; - ia_perf_counter_select.u32All = 0; - ia_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = ia_perf_counter_select.u32All; - regAddr[0] = AiIaCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - /* - case kHsaAiCounterBlockIdMc: { - // To be investigated later - //regMC_SEQ_PERF_SEQ_CTL mc_perfcounter_select; - //mc_perfcounter_select.u32All = 0; - //mc_perfcounter_select.bits.PERF_SEL = blkCntrIdx; - //regVal[0] = mc_perfcounter_select.u32All; - //regAddr[0] = AiMcCounterRegAddr[cntrIdx].counterSelRegAddr; - //regIdx = 1; - } - break; - */ - - // Temp Commented out for Vega10 - /* - case kHsaAiCounterBlockIdSrbm: { - regSRBM_PERFCOUNTER0_SELECT srbm_perf_counter_select; - srbm_perf_counter_select.u32All = 0; - srbm_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = srbm_perf_counter_select.u32All; - regAddr[0] = AiSrbmCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - */ - - /* - case kHsaAiCounterBlockIdTcs: { - regTCS_PERFCOUNTER0_SELECT__CI tcs_perf_counter_select; - tcs_perf_counter_select.u32All = 0; - tcs_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = tcs_perf_counter_select.u32All; - regAddr[0] = AiTcsCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - */ - - case kHsaAiCounterBlockIdWd: { - regWD_PERFCOUNTER0_SELECT wd_perf_counter_select; - wd_perf_counter_select.u32All = 0; - wd_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = wd_perf_counter_select.u32All; - regAddr[0] = AiWdCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - // Temp commented for Vega10 - /* - case kHsaAiCounterBlockIdCpg: { - regCPG_PERFCOUNTER0_SELECT cpg_perf_counter_select; - cpg_perf_counter_select.u32All = 0; - cpg_perf_counter_select.bits.PERF_SEL = blkCntrIdx; - regVal[0] = cpg_perf_counter_select.u32All; - regAddr[0] = AiCpgCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - */ - - // Temp commented for Vega10 - case kHsaAiCounterBlockIdCpc: { - regCPC_PERFCOUNTER0_SELECT cpc_perf_counter_select; - cpc_perf_counter_select.u32All = 0; - cpc_perf_counter_select.bits.CNTR_SEL0 = blkCntrIdx; - regVal[0] = cpc_perf_counter_select.u32All; - regAddr[0] = AiCpcCounterRegAddr[cntrIdx].counterSelRegAddr; - regIdx = 1; - break; - } - - /* - case kHsaAiCounterBlockIdMc: { - AddPriviledgedCountersToList(AiBlockIdMc, blkCntrIdx); - //Num of regs equals to 0 means it is processed by KFD - regIdx = 0; - break; - } - - case kHsaAiCounterBlockIdIommuV2: { - AddPriviledgedCountersToList(AiBlockIdIommuV2, blkCntrIdx); - //Num of regs equals to 0 means it is processed by KFD - regIdx = 0; - break; - } - - case kHsaAiCounterBlockIdKernelDriver: { - AddPriviledgedCountersToList(AiBlockIdKernelDriver, blkCntrIdx); - //Num of regs equals to 0 means it is processed by KFD - regIdx = 0; - break; - } - */ - - default: { - regIdx = 0; - break; - } - } - - return regIdx; -} - -uint32_t Gfx9PerfCounter::BuildCounterReadRegisters(uint32_t reg_index, uint32_t block_id, - uint32_t* reg_addr, uint32_t* reg_val) { - uint32_t ii; - uint32_t reg_num = 0; - uint32_t instance_index; - regGRBM_GFX_INDEX grbm_gfx_index; - switch (block_id) { - case kHsaAiCounterBlockIdSq: - case kHsaAiCounterBlockIdSqGs: - case kHsaAiCounterBlockIdSqVs: - case kHsaAiCounterBlockIdSqPs: - case kHsaAiCounterBlockIdSqHs: - case kHsaAiCounterBlockIdSqCs: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiSqCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiSqCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdCb0: - case kHsaAiCounterBlockIdCb1: - case kHsaAiCounterBlockIdCb2: - case kHsaAiCounterBlockIdCb3: { - instance_index = block_id - kHsaAiCounterBlockIdCb0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiCbCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiCbCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - // Temp commented for Vega10 - /* - case kHsaAiCounterBlockIdCpf: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiCpfCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiCpfCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - */ - - case kHsaAiCounterBlockIdDb0: - case kHsaAiCounterBlockIdDb1: - case kHsaAiCounterBlockIdDb2: - case kHsaAiCounterBlockIdDb3: { - instance_index = block_id - kHsaAiCounterBlockIdDb0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiDbCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiDbCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdGrbm: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiGrbmCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiGrbmCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaAiCounterBlockIdGrbmSe: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiGrbmSeCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiGrbmSeCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaAiCounterBlockIdPaSu: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiPaSuCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiPaSuCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdPaSc: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiPaScCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiPaScCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdSpi: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiSpiCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiSpiCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdSx: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiSxCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiSxCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdTa0: - case kHsaAiCounterBlockIdTa1: - case kHsaAiCounterBlockIdTa2: - case kHsaAiCounterBlockIdTa3: - case kHsaAiCounterBlockIdTa4: - case kHsaAiCounterBlockIdTa5: - case kHsaAiCounterBlockIdTa6: - case kHsaAiCounterBlockIdTa7: - case kHsaAiCounterBlockIdTa8: - case kHsaAiCounterBlockIdTa9: - case kHsaAiCounterBlockIdTa10: - case kHsaAiCounterBlockIdTa11: - case kHsaAiCounterBlockIdTa12: - case kHsaAiCounterBlockIdTa13: - case kHsaAiCounterBlockIdTa14: - case kHsaAiCounterBlockIdTa15: { - instance_index = block_id - kHsaAiCounterBlockIdTa0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiTaCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiTaCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdTca0: - case kHsaAiCounterBlockIdTca1: { - instance_index = block_id - kHsaAiCounterBlockIdTca0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiTcaCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiTcaCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaAiCounterBlockIdTcc0: - case kHsaAiCounterBlockIdTcc1: - case kHsaAiCounterBlockIdTcc2: - case kHsaAiCounterBlockIdTcc3: - case kHsaAiCounterBlockIdTcc4: - case kHsaAiCounterBlockIdTcc5: - case kHsaAiCounterBlockIdTcc6: - case kHsaAiCounterBlockIdTcc7: - case kHsaAiCounterBlockIdTcc8: - case kHsaAiCounterBlockIdTcc9: - case kHsaAiCounterBlockIdTcc10: - case kHsaAiCounterBlockIdTcc11: - case kHsaAiCounterBlockIdTcc12: - case kHsaAiCounterBlockIdTcc13: - case kHsaAiCounterBlockIdTcc14: - case kHsaAiCounterBlockIdTcc15: { - instance_index = block_id - kHsaAiCounterBlockIdTcc0; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiTccCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiTccCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaAiCounterBlockIdTd0: - case kHsaAiCounterBlockIdTd1: - case kHsaAiCounterBlockIdTd2: - case kHsaAiCounterBlockIdTd3: - case kHsaAiCounterBlockIdTd4: - case kHsaAiCounterBlockIdTd5: - case kHsaAiCounterBlockIdTd6: - case kHsaAiCounterBlockIdTd7: - case kHsaAiCounterBlockIdTd8: - case kHsaAiCounterBlockIdTd9: - case kHsaAiCounterBlockIdTd10: - case kHsaAiCounterBlockIdTd11: - case kHsaAiCounterBlockIdTd12: - case kHsaAiCounterBlockIdTd13: - case kHsaAiCounterBlockIdTd14: - case kHsaAiCounterBlockIdTd15: { - instance_index = block_id - kHsaAiCounterBlockIdTd0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiTdCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiTdCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdTcp0: - case kHsaAiCounterBlockIdTcp1: - case kHsaAiCounterBlockIdTcp2: - case kHsaAiCounterBlockIdTcp3: - case kHsaAiCounterBlockIdTcp4: - case kHsaAiCounterBlockIdTcp5: - case kHsaAiCounterBlockIdTcp6: - case kHsaAiCounterBlockIdTcp7: - case kHsaAiCounterBlockIdTcp8: - case kHsaAiCounterBlockIdTcp9: - case kHsaAiCounterBlockIdTcp10: - case kHsaAiCounterBlockIdTcp11: - case kHsaAiCounterBlockIdTcp12: - case kHsaAiCounterBlockIdTcp13: - case kHsaAiCounterBlockIdTcp14: - case kHsaAiCounterBlockIdTcp15: { - instance_index = block_id - kHsaAiCounterBlockIdTcp0; - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_INDEX = instance_index; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiTcpCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiTcpCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdGds: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiGdsCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiGdsCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - case kHsaAiCounterBlockIdVgt: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiVgtCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiVgtCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - - case kHsaAiCounterBlockIdIa: { - for (ii = 0; ii < num_se_; ii++) { - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_INDEX = ii; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = grbm_gfx_index.u32All; - reg_num++; - - reg_addr[reg_num] = AiIaCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiIaCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - } - break; - } - /* - case kHsaAiCounterBlockIdMc: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiMcCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiMcCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - */ - // Temp Commented out for Vega10 - /* - case kHsaAiCounterBlockIdSrbm: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiSrbmCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiSrbmCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - */ - /* - case kHsaAiCounterBlockIdTcs: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiTcsCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiTcsCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - */ - case kHsaAiCounterBlockIdWd: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiWdCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiWdCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - // Temp commented for Vega10 - /* - case kHsaAiCounterBlockIdCpg: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiCpgCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiCpgCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - */ - - // Temp commented for Vega10 - case kHsaAiCounterBlockIdCpc: { - reg_addr[reg_num] = mmGRBM_GFX_INDEX; - reg_val[reg_num] = reset_grbm_; - reg_num++; - - reg_addr[reg_num] = AiCpcCounterRegAddr[reg_index].counterReadRegAddrLo; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - - reg_addr[reg_num] = AiCpcCounterRegAddr[reg_index].counterReadRegAddrHi; - reg_val[reg_num] = COPY_DATA_FLAG; - reg_num++; - break; - } - - // IommuV2, MC, kernel driver counters are retrieved via - // KFD implementation - case kHsaAiCounterBlockIdMc: - case kHsaAiCounterBlockIdIommuV2: - case kHsaAiCounterBlockIdKernelDriver: { - reg_num = 0; - break; - } - - default: { break; } - } - - return reg_num; -} - -} /* namespace */ diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_perf_counter.h b/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_perf_counter.h deleted file mode 100644 index ddebd331a7..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gfx9_perf_counter.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef _AI_PMU_H_ -#define _AI_PMU_H_ - -#include - -#include "perf_counter.h" - -namespace pm4_profile { -class CommandWriter; - -// This class implement the AI PMU. It is responsible for setting up -// CounterGroups to represent each AI hardware block which exposes performance -// counters. -class Gfx9PerfCounter : public pm4_profile::PerfCounter { - public: - Gfx9PerfCounter(); - - void begin(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, const CountersMap& countersMap); - - uint32_t end(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, const CountersMap& countersMap, - void* dataBuff); - - uint32_t getNumSe() { return num_se_; } - - private: - void Init(); - - // Program SQ block related counters - uint32_t ProgramSQCntrs(uint32_t sqRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TA block related counters - uint32_t ProgramTaCntrs(uint32_t taRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TCA block related counters - uint32_t ProgramTcaCntrs(uint32_t tcaRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TCC block related counters - uint32_t ProgramTccCntrs(uint32_t tccRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TCP block related counters - uint32_t ProgramTcpCntrs(uint32_t tcpRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Program TD block related counters - uint32_t ProgramTdCntrs(uint32_t tdRegIdx, uint32_t* regAddr, uint32_t* regVal, uint32_t blkId, - uint32_t blkCntrIdx); - - // Build counter selection register, return how many registers are built - uint32_t BuildCounterSelRegister(uint32_t cntrIdx, uint32_t* regAddr, uint32_t* regVal, - uint32_t blkId, uint32_t blkCntrIdx); - - // Build counter selection register, return how many registers are built - uint32_t BuildCounterReadRegisters(uint32_t reg_index, uint32_t block_id, uint32_t* reg_addr, - uint32_t* reg_val); - - private: - // Indicates the number of Shader Engines Present - uint32_t num_se_; - - // Used to reset GRBM to its default state - uint32_t reset_grbm_; -}; -} - -#endif // _AI_PMU_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/gpu_block_info.h b/runtime/hsa-amd-aqlprofile/src/perfcounter/gpu_block_info.h deleted file mode 100644 index e41eebf1b5..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/gpu_block_info.h +++ /dev/null @@ -1,98 +0,0 @@ -#ifndef _GPU_BLOCKINFO_H_ -#define _GPU_BLOCKINFO_H_ - -#include - -namespace pm4_profile { - -typedef enum CntlMethod { - CntlMethodNone = 0, - CntlMethodByInstance = 1, - CntlMethodBySe = 2, - CntlMethodBySeAndInstance = 3 -} CntlMethod; - -// Structure which contains information about a specific hardware block for CI. -#define GPU_BLOCK_NAME_SIZE 15 - -typedef struct GpuBlockInfo_ { - // Unique string identifier of the block. - const char blockName[GPU_BLOCK_NAME_SIZE]; - - // Unique string identifier of the block. - uint32_t counterGroupId; - - // Maximum number of shader engines - uint32_t maxShaderEngineCount; - - // Maximum number of shader arrays - uint32_t maxShaderArrayCount; - - // Maximum number of block instances in the group per shader array - uint32_t maxInstanceCount; - - // Counter control method - CntlMethod method; - - // Maximum counter event ID - uint32_t maxEventId; - - // Maximum number of counters that can be enabled at once - uint32_t maxSimultaneousCounters; - - // Maximum number of streaming counters that can be enabled at once - uint32_t maxStreamingCounters; - - // The number of hardware counters that are shared - // between regular and streaming counters. - // This is important so that resources are not double-booked - // between the two types of counters. - uint32_t sharedHWCounters; - - // Block counters can be configured with additional filters - bool hasFilters; - - //------------------------------------------ - // Trace specific stuff regarding when they get locked - - // Buffer size in bytes - uint32_t bufferSize; - - // Current write pointer offset from beginning of the buffer - uint32_t wptrOffset; - - // Flag that buffer might have wrapped - bool wrapped; - - // If buffer has wrapped, this could indicate approximate - // total amount of data that was dumpued in the trace buffer - uint32_t dataSizeEstimate; - - // Buffer data pointer - void* pData; -} GpuBlockInfo; - -// Register address corresponding to each counter -typedef struct GpuCounterRegInfo_ { - // counter select register address - uint32_t counterSelRegAddr; - - // counter control register address - uint32_t counterCntlRegAddr; - - // counter read register address low - uint32_t counterReadRegAddrLo; - - // counter read register address high - uint32_t counterReadRegAddrHi; -} GpuCounterRegInfo; - -// Gpu Privileged Block ID info. This number should be the same as that -// defined in KFD -typedef struct GpuPrivCounterBlockId_ { - // Block ID consists of 4 dwords - uint32_t items[4]; -} GpuPrivCounterBlockId; - -} // pm4_profile -#endif diff --git a/runtime/hsa-amd-aqlprofile/src/perfcounter/perf_counter.h b/runtime/hsa-amd-aqlprofile/src/perfcounter/perf_counter.h deleted file mode 100644 index 601a86de87..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/perfcounter/perf_counter.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef _HSA_PERF_H_ -#define _HSA_PERF_H_ - -#include - -#include -#include -#include - -namespace pm4_profile { -class DefaultCmdBuf; -class CommandWriter; - -typedef std::vector CountersVec; -typedef std::map CountersMap; - -class PerfCounter { - public: - virtual ~PerfCounter() {} - - // Generate start profiling commands. - virtual void begin(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, - const CountersMap& countersMap) = 0; - - // Generate stop profiling commands. - // Return actual required data buffer size. - virtual uint32_t end(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter, - const CountersMap& countersMap, void* dataBuff) = 0; - - // Returns number of shader engines per block - // for the blocks featured shader engines instancing - virtual uint32_t getNumSe() = 0; -}; -} // namespace pm4_profile -#endif // _HSA_PERF_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/threadtrace/CMakeLists.txt b/runtime/hsa-amd-aqlprofile/src/threadtrace/CMakeLists.txt deleted file mode 100644 index 274d95d9b9..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/threadtrace/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# -# Source files for Rocr ThreadTrace -# -set ( LIB_SRC thread_trace.cpp ) -set ( LIB_SRC ${LIB_SRC} gfx8_thread_trace.cpp ) -set ( LIB_SRC ${LIB_SRC} gfx9_thread_trace.cpp ) - -# -# Header files include path(s). -# -include_directories ( ${PROJ_DIR}/commandwriter ) - -# -# Build ThreadTrace as a Static Library object -# -add_library ( ${SQTT_LIB} STATIC ${LIB_SRC} ) diff --git a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx8_thread_trace.cpp b/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx8_thread_trace.cpp deleted file mode 100644 index 67d5af90bd..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx8_thread_trace.cpp +++ /dev/null @@ -1,352 +0,0 @@ -#include "gfx8_thread_trace.h" - -/// @brief Returns the lower 32-bits of a value -inline uint32_t Low32(uint64_t u) { return (u & 0xFFFFFFFFUL); } - -/// @brief Returns the upper 32-bits of a value -inline uint32_t High32(uint64_t u) { return (u >> 32); } - -namespace pm4_profile { - -Gfx8ThreadTrace::Gfx8ThreadTrace() { - // Initialize the number of shader engines - numSE_ = 4; -} - -Gfx8ThreadTrace::~Gfx8ThreadTrace() {} - -bool Gfx8ThreadTrace::Init(const ThreadTraceConfig* config) { - // Initialize SQTT Configuration and Register objects - if (!ThreadTrace::Init(config)) return false; - InitThreadTraceCfgRegs(); - return true; -} - -void Gfx8ThreadTrace::InitThreadTraceCfgRegs() { - // Indicates the size of buffer to use per Shader Engine instance. - // The size is specified in terms of 4KB blocks - ttCfgRegs_.ttRegSize.u32All = 0; - - // Indicates various attributes of a thread trace session. - // - // MASK_CS: Which shader types should be enabled for data collection - // Enable CS Shader types. - // - // WRAP: How trace buffer should be used as a ring buffer or as a linear - // buffer - Disable WRAP mode i.e use it as a linear buffer - // - // MODE: Enables a thread trace session - // - // CAPTURE_MODE: When thread trace data is collected immediately after MODE - // is enabled or wait until a Thread Trace Start event is received - // - // AUTOFLUSH_EN: Flush thread trace data to buffer often automatically - // - ttCfgRegs_.ttRegMode.u32All = 0; - ttCfgRegs_.ttRegMode.bits.WRAP = 0; - ttCfgRegs_.ttRegMode.bits.CAPTURE_MODE = 0; - ttCfgRegs_.ttRegMode.bits.MASK_CS = 1; - ttCfgRegs_.ttRegMode.bits.AUTOFLUSH_EN = 1; - ttCfgRegs_.ttRegMode.bits.MODE = SQ_THREAD_TRACE_MODE_OFF; - - // Enable Thread Trace for all VM Id's - // Enable all of the SIMD's of the compute unit - // Enable Compute Unit (CU) at index Zero to be used for fine-grained data - // Enable Shader Array (SH) at index Zero to be used for fine-grained data - // - // @note: Not enabling REG_STALL_EN, SPI_STALL_EN and SQ_STALL_EN bits. They - // are useful if we wish to program buffer throttling. - // - ttCfgRegs_.ttRegMask.u32All = 0; - ttCfgRegs_.ttRegMask.bits.SH_SEL = 0x0; - ttCfgRegs_.ttRegMask.bits.SIMD_EN = 0xF; - ttCfgRegs_.ttRegMask.bits.CU_SEL = GetCuId(); - ttCfgRegs_.ttRegMask.bits.SQ_STALL_EN__CI__VI = 0x1; - ttCfgRegs_.ttRegMask.bits.SPI_STALL_EN__CI__VI = 0x1; - ttCfgRegs_.ttRegMask.bits.REG_STALL_EN__CI__VI = 0x1; - ttCfgRegs_.ttRegMask.bits.VM_ID_MASK = GetVmId(); - - // Override Mask value if a user value is available - uint32_t ttMask = GetMask(); - if (ttMask) { - ttCfgRegs_.ttRegMask.u32All = ttMask; - } - - // Mask of compute units to get thread trace data from - ttCfgRegs_.ttRegPerfMask.u32All = 0; - ttCfgRegs_.ttRegPerfMask.bits.SH0_MASK = 0xFFFF; - ttCfgRegs_.ttRegPerfMask.bits.SH1_MASK = 0xFFFF; - - // Indicate the different TT messages/tokens that should be enabled/logged - // Indicate the different TT tokens that specify register operations to be logged - ttCfgRegs_.ttRegTokenMask.u32All = 0; - ttCfgRegs_.ttRegTokenMask.bits.REG_MASK = 0xFF; - ttCfgRegs_.ttRegTokenMask.bits.TOKEN_MASK = 0xFFFF; - ttCfgRegs_.ttRegTokenMask.bits.REG_DROP_ON_STALL__CI__VI = 0x1; - - // Override TokenMask1 value if a user value is available - uint32_t tokenMask1 = GetTokenMask(); - if (tokenMask1) { - ttCfgRegs_.ttRegTokenMask.u32All = tokenMask1; - } - - // Indicate the different TT tokens that specify instruction operations to be logged - // Disabling specifically instruction operations updating Program Counter (PC). - // @note: The field is defined in the spec incorrectly as a 16-bit value - ttCfgRegs_.ttRegTokenMask2.u32All = 0; - ttCfgRegs_.ttRegTokenMask2.bits.INST_MASK = 0xFFFFFF7F; - - // Override TokenMask2 value if a user value is available - uint32_t tokenMask2 = GetTokenMask2(); - if (tokenMask2) { - ttCfgRegs_.ttRegTokenMask2.u32All = tokenMask2; - } -} - -void Gfx8ThreadTrace::setSqttDataBuff(uint8_t* sqttBuffer, uint32_t sqttBuffSz) { - // Compute the size of buffer available for each shader engine - ttBuffSize_ = sqttBuffSz / numSE_; - - // Populate the sqtt buffer array submitted to device - for (int idx = 0; idx < numSE_; idx++) { - uint64_t sqttSEAddr = uint64_t(sqttBuffer + (ttBuffSize_ * idx)); - devMemList_.push_back(sqttSEAddr); - } - - // Update the size bit-field of sqtt ctrl register - ttCfgRegs_.ttRegSize.bits.SIZE = ttBuffSize_ >> TT_BUFF_ALIGN_SHIFT; -} - -void Gfx8ThreadTrace::BeginSession(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter) { - // Program Grbm to broadcast messages to all shader engines - regGRBM_GFX_INDEX grbm_gfx_index; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, grbm_gfx_index.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Disable RLC Perfmon Clock Gating - // On Vega this is needed to collect Perf Cntrs - // cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmRLC_PERFMON_CLK_CNTL__VI, 1); - - // Program the Compute register to indicate SQTT is enabled - /* - regCOMPUTE_THREAD_TRACE_ENABLE__CI__VI enableTT = {0}; - enableTT.bits.THREAD_TRACE_ENABLE = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, - mmCOMPUTE_THREAD_TRACE_ENABLE__CI__VI, - enableTT.u32All); - */ - - // Program the thread trace mask - specifies SH, CU, SIMD and - // VM Id masks to apply. Enabling SQ/SPI/REG_STALL_EN bits - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MASK__VI, - ttCfgRegs_.ttRegMask.u32All); - - // Program the thread trace Perf mask - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_PERF_MASK__VI, - ttCfgRegs_.ttRegPerfMask.u32All); - - // Program the thread trace token mask - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_TOKEN_MASK__VI, - ttCfgRegs_.ttRegTokenMask.u32All); - - // Program the thread trace token mask2 to specify the list of instruction - // tokens to record. Disabling INST_PC instruction tokens - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_TOKEN_MASK2__VI, - ttCfgRegs_.ttRegTokenMask2.u32All); - - // Program the thread trace mode register - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MODE__VI, - ttCfgRegs_.ttRegMode.u32All); - - // Program the HiWaterMark register to support stalling - if ((ttCfgRegs_.ttRegMask.bits.SQ_STALL_EN__CI__VI) || - (ttCfgRegs_.ttRegMask.bits.SPI_STALL_EN__CI__VI) || - (ttCfgRegs_.ttRegMask.bits.REG_STALL_EN__CI__VI) || - (ttCfgRegs_.ttRegTokenMask.bits.REG_DROP_ON_STALL__CI__VI)) { - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_HIWATER__VI, 0x06); - } - - // Iterate through the list of SE's and program the register - // for carrying address of thread trace buffer which is aligned - // to 4KB per thread trace specification - uint64_t baseAddr = 0; - for (int idx = 0; idx < numSE_; idx++) { - // Program Grbm to direct writes to one SE - grbm_gfx_index.bitfields.SH_INDEX = 0; - grbm_gfx_index.bitfields.SE_INDEX = idx; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, grbm_gfx_index.u32All); - - // Program base2 address of buffer to use for thread trace - // Encodes ATC bit, so the correct way to program is to use - // ATC Bit property of the device - /* - regSQ_THREAD_TRACE_BASE2__CI__VI sqttBase2 = {}; - sqttBase2.u32All = 0; - sqttBase2.bits.ATC = 0; - sqttBase2.bits.ADDR_HI = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, - mmSQ_THREAD_TRACE_BASE2__VI, - sqttBase2.u32All); - */ - - // Program the base address to use - baseAddr = devMemList_[idx] >> TT_BUFF_ALIGN_SHIFT; - - // Program base address of buffer to use for thread trace - regSQ_THREAD_TRACE_BASE sqttBase = {}; - sqttBase.bits.ADDR = Low32(baseAddr); - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_BASE__VI, sqttBase.u32All); - - // Program the size of thread trace buffer - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_SIZE__VI, - ttCfgRegs_.ttRegSize.u32All); - - // Program the thread trace ctrl register - regSQ_THREAD_TRACE_CTRL sqttCtrl = {}; - sqttCtrl.u32All = 0; - sqttCtrl.bits.RESET_BUFFER = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_CTRL__VI, sqttCtrl.u32All); - } - - // Reset the GRBM to broadcast mode - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, grbm_gfx_index.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Program the thread trace mode register - ttCfgRegs_.ttRegMode.bits.MODE = SQ_THREAD_TRACE_MODE_ON; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MODE__VI, - ttCfgRegs_.ttRegMode.u32All); - ttCfgRegs_.ttRegMode.bits.MODE = SQ_THREAD_TRACE_MODE_OFF; - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - return; -} - -void Gfx8ThreadTrace::StopSession(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter) { - // Program Grbm to broadcast messages to all shader engines - regGRBM_GFX_INDEX grbm_gfx_index; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, grbm_gfx_index.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Program the thread trace mode register to disable thread trace - // The MODE register is set to disable thread trace by default - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MODE__VI, - ttCfgRegs_.ttRegMode.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Iterate through the list of SE's and read the Status, Counter and - // Write Pointer registers of Thread Trace subsystem - uint64_t baseAddr = 0; - for (int idx = 0; idx < numSE_; idx++) { - // Program Grbm to direct writes to one SE - grbm_gfx_index.bitfields.SH_INDEX = 0; - grbm_gfx_index.bitfields.SE_INDEX = idx; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, grbm_gfx_index.u32All); - - // Issue WaitRegMem command to wait until SQTT event has completed - bool funcEq = false; - bool memSpace = false; - uint32_t waitVal = 0x01; - uint32_t maskVal = 0x40000000L; - uint32_t statusOffset = mmSQ_THREAD_TRACE_STATUS__VI - UCONFIG_SPACE_START__CI__VI; - cmdWriter->BuildWaitRegMemCommand(cmdBuff, memSpace, statusOffset, funcEq, maskVal, waitVal); - - // Retrieve the values from various status registers - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_SRC_SYS_PERF_COUNTER, - mmSQ_THREAD_TRACE_STATUS__VI, 0, - ttStatus_ + ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_STATUS), - COPY_DATA_SEL_COUNT_1DW, true); - - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_SRC_SYS_PERF_COUNTER, - mmSQ_THREAD_TRACE_CNTR, 0, - ttStatus_ + ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_CNTR), - COPY_DATA_SEL_COUNT_1DW, true); - - uint32_t wptrIdx = ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_WPTR); - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_SRC_SYS_PERF_COUNTER, - mmSQ_THREAD_TRACE_WPTR__VI, 0, ttStatus_ + wptrIdx, - COPY_DATA_SEL_COUNT_1DW, true); - } - - // Reset the GRBM to broadcast mode - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX__CI__VI, grbm_gfx_index.u32All); - - // Initialize cache flush request object - FlushCacheOptions flush; - flush.l1 = true; - flush.l2 = true; - flush.icache = true; - flush.kcache = true; - cmdWriter->BuildFlushCacheCmd(cmdBuff, &flush, NULL, 0); - - // Program the size of thread trace buffer - regSQ_THREAD_TRACE_SIZE ttRegSize = {0}; - ttRegSize.u32All = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_SIZE__VI, ttRegSize.u32All); - - // Program the thread trace ctrl register - regSQ_THREAD_TRACE_CTRL sqttCtrl = {}; - sqttCtrl.u32All = 0; - sqttCtrl.bits.RESET_BUFFER = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_CTRL__VI, sqttCtrl.u32All); - - // Program the compute_thread_trace_enable register - /* - regCOMPUTE_THREAD_TRACE_ENABLE__CI__VI disableTT = {0}; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, - mmCOMPUTE_THREAD_TRACE_ENABLE__CI__VI, - disableTT.u32All); - */ - - // Disable RLC Perfmon Clock Gating - // On Vega this is needed to collect Perf Cntrs - // cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmRLC_PERFMON_CLK_CNTL__VI, 0); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - return; -} - -bool Gfx8ThreadTrace::Validate() { - // Iterate through the list of SE to verify - for (int idx = 0; idx < numSE_; idx++) { - // Determine if the buffer has wrapped - uint32_t statusIdx = ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_STATUS); - if (ttStatus_[statusIdx] & 0x80000000) { - return false; - } - - // Adjust the value of Write Ptr which is bits [29-0] - uint32_t wptrIdx = ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_WPTR); - ttStatus_[wptrIdx] = (ttStatus_[wptrIdx] & TT_WRITE_PTR_MASK); - } - - return true; -} - -} // pm4_profile diff --git a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx8_thread_trace.h b/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx8_thread_trace.h deleted file mode 100644 index 718a0ff6ea..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx8_thread_trace.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef _GFX8_THREAD_TRACE_H_ -#define _GFX8_THREAD_TRACE_H_ - -#include "gfxip/gfx8/si_ci_vi_merged_typedef.h" -#include "gfxip/gfx8/si_ci_vi_merged_offset.h" -#include "gfxip/gfx8/si_ci_vi_merged_enum.h" -#include "gfxip/gfx8/si_pm4defs.h" -#include "thread_trace.h" - -namespace pm4_profile { - -typedef struct Gfx8ThreadTraceCfgRegs { - // Size of thread trace buffer - regSQ_THREAD_TRACE_SIZE ttRegSize; - // Thread trace mode - regSQ_THREAD_TRACE_MODE ttRegMode; - // Thread trace wave mask - regSQ_THREAD_TRACE_MASK ttRegMask; - // Thread trace token mask - regSQ_THREAD_TRACE_TOKEN_MASK ttRegTokenMask; - // Thread trace token mask2 - regSQ_THREAD_TRACE_TOKEN_MASK2__VI ttRegTokenMask2; - // Thread trace perf mask - regSQ_THREAD_TRACE_PERF_MASK ttRegPerfMask; -} Gfx8ThreadTraceCfgRegs; - -// Encapsulates the various Api and structures used to enable a thread -// trace session and collect its data -class Gfx8ThreadTrace : public ThreadTrace { - public: - Gfx8ThreadTrace(); - - ~Gfx8ThreadTrace(); - - // Initializes various data structures and handles that - // are needed to support a thread trace session - bool Init(const ThreadTraceConfig* config); - - // Builds Pm4 command stream to program hardware registers that - // enable a thread trace session, including the issue of an event - // to begin thread session - void BeginSession(pm4_profile::DefaultCmdBuf* cmdBuff, pm4_profile::CommandWriter* cmdWriter); - - // Builds Pm4 command stream to program hardware registers that - // disable a thread trace session, including the issue of an event - // to stop currently ongoing thread session - void StopSession(pm4_profile::DefaultCmdBuf* cmdBuff, pm4_profile::CommandWriter* cmdWriter); - - // Validates that thread trace session ran correctly i.e. did not - // encounter any errors. - bool Validate(); - - // Initializes the handle of buffer used to collect SQTT data - void setSqttDataBuff(uint8_t* sqttBuffer, uint32_t sqttBuffSz); - - // Initializes the handle of buffer used to read control data of SQTT - void setSqttCtrlBuff(uint32_t* ctrlBuff) { ttStatus_ = ctrlBuff; } - - // Return status info size - uint32_t StatusSizeInfo() const { return TT_STATUS_IDX_MAX * sizeof(uint32_t) * numSE_; } - - // Return number of Shader Engines - uint32_t getNumSe() { return numSE_; } - - private: - // Holds number of Shader Engines present on device - uint32_t numSE_; - - // Thread traces status register indices to determine - // status of thread trace run - typedef enum { - TT_STATUS_IDX_STATUS = 0, - TT_STATUS_IDX_CNTR = 1, - TT_STATUS_IDX_WPTR = 2, - TT_STATUS_IDX_MAX = 3 - } TTStatusReg; - - // A list of tuples of TT_STATUS_IDX_MAX size, - // giving status of thread trace - uint32_t* ttStatus_; - - // Size of thread trace buffer per shader engine - uint32_t ttBuffSize_; - - // Handles of Device memory used for thread trace - std::vector devMemList_; - - // Registers that need to be programmed for Thread Trace - Gfx8ThreadTraceCfgRegs ttCfgRegs_; - - // Initializes thread trace registers with default parameters. - // These are potentially updated based on updates to thread trace - // configuration object by user - void InitThreadTraceCfgRegs(); -}; - -} // pm4_profile - -#endif // _GFX8_THREAD_TRACE_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx9_thread_trace.cpp b/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx9_thread_trace.cpp deleted file mode 100644 index 089bccb8f9..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx9_thread_trace.cpp +++ /dev/null @@ -1,348 +0,0 @@ -#include "gfx9_thread_trace.h" - -/// @brief Returns the lower 32-bits of a value -inline uint32_t Low32(uint64_t u) { return (u & 0xFFFFFFFFUL); } - -/// @brief Returns the upper 32-bits of a value -inline uint32_t High32(uint64_t u) { return (u >> 32); } - -namespace pm4_profile { - -Gfx9ThreadTrace::Gfx9ThreadTrace() { - // Initialize the number of shader engines - numSE_ = 4; -} - -Gfx9ThreadTrace::~Gfx9ThreadTrace() {} - -bool Gfx9ThreadTrace::Init(const ThreadTraceConfig* config) { - // Initialize SQTT Configuration and Register objects - if (!ThreadTrace::Init(config)) return false; - InitThreadTraceCfgRegs(); - return true; -} - -void Gfx9ThreadTrace::InitThreadTraceCfgRegs() { - // Indicates the size of buffer to use per Shader Engine instance. - // The size is specified in terms of 4KB blocks - ttCfgRegs_.ttRegSize.u32All = 0; - - // Indicates various attributes of a thread trace session. - // - // MASK_CS: Which shader types should be enabled for data collection - // Enable CS Shader types. - // - // WRAP: How trace buffer should be used as a ring buffer or as a linear - // buffer - Disable WRAP mode i.e use it as a linear buffer - // - // MODE: Enables a thread trace session - // - // CAPTURE_MODE: When thread trace data is collected immediately after MODE - // is enabled or wait until a Thread Trace Start event is received - // - // AUTOFLUSH_EN: Flush thread trace data to buffer often automatically - // - ttCfgRegs_.ttRegMode.u32All = 0; - ttCfgRegs_.ttRegMode.bits.WRAP = 0; - ttCfgRegs_.ttRegMode.bits.CAPTURE_MODE = 0; - ttCfgRegs_.ttRegMode.bits.MASK_CS = 1; - ttCfgRegs_.ttRegMode.bits.AUTOFLUSH_EN = 1; - ttCfgRegs_.ttRegMode.bits.MODE = SQ_THREAD_TRACE_MODE_OFF; - - // Enable Thread Trace for all VM Id's - // Enable all of the SIMD's of the compute unit - // Enable Compute Unit (CU) at index Zero to be used for fine-grained data - // Enable Shader Array (SH) at index Zero to be used for fine-grained data - // - // @note: Not enabling REG_STALL_EN, SPI_STALL_EN and SQ_STALL_EN bits. They - // are useful if we wish to program buffer throttling. - // - ttCfgRegs_.ttRegMask.u32All = 0; - ttCfgRegs_.ttRegMask.bits.SH_SEL = 0x0; - ttCfgRegs_.ttRegMask.bits.SIMD_EN = 0xF; - ttCfgRegs_.ttRegMask.bits.CU_SEL = GetCuId(); - ttCfgRegs_.ttRegMask.bits.SQ_STALL_EN = 0x1; - ttCfgRegs_.ttRegMask.bits.SPI_STALL_EN = 0x1; - ttCfgRegs_.ttRegMask.bits.REG_STALL_EN = 0x1; - ttCfgRegs_.ttRegMask.bits.VM_ID_MASK = GetVmId(); - - // Override Mask value if a user value is available - uint32_t ttMask = GetMask(); - if (ttMask) { - ttCfgRegs_.ttRegMask.u32All = ttMask; - } - - // Mask of compute units to get thread trace data from - ttCfgRegs_.ttRegPerfMask.u32All = 0; - ttCfgRegs_.ttRegPerfMask.bits.SH0_MASK = 0xFFFF; - ttCfgRegs_.ttRegPerfMask.bits.SH1_MASK = 0xFFFF; - - // Indicate the different TT messages/tokens that should be enabled/logged - // Indicate the different TT tokens that specify register operations to be logged - ttCfgRegs_.ttRegTokenMask.u32All = 0; - ttCfgRegs_.ttRegTokenMask.bits.REG_MASK = 0xFF; - ttCfgRegs_.ttRegTokenMask.bits.TOKEN_MASK = 0xFFFF; - ttCfgRegs_.ttRegTokenMask.bits.REG_DROP_ON_STALL = 0x1; - - // Override TokenMask1 value if a user value is available - uint32_t tokenMask1 = GetTokenMask(); - if (tokenMask1) { - ttCfgRegs_.ttRegTokenMask.u32All = tokenMask1; - } - - // Indicate the different TT tokens that specify instruction operations to be logged - // Disabling specifically instruction operations updating Program Counter (PC). - // @note: The field is defined in the spec incorrectly as a 16-bit value - ttCfgRegs_.ttRegTokenMask2.u32All = 0; - ttCfgRegs_.ttRegTokenMask2.bits.INST_MASK = 0xFFFFFF7F; - - // Override TokenMask2 value if a user value is available - uint32_t tokenMask2 = GetTokenMask2(); - if (tokenMask2) { - ttCfgRegs_.ttRegTokenMask2.u32All = tokenMask2; - } -} - -void Gfx9ThreadTrace::setSqttDataBuff(uint8_t* sqttBuffer, uint32_t sqttBuffSz) { - // Compute the size of buffer available for each shader engine - ttBuffSize_ = sqttBuffSz / numSE_; - - // Populate the sqtt buffer array submitted to device - for (int idx = 0; idx < numSE_; idx++) { - uint64_t sqttSEAddr = uint64_t(sqttBuffer + (ttBuffSize_ * idx)); - devMemList_.push_back(sqttSEAddr); - } - - // Update the size bit-field of sqtt ctrl register - ttCfgRegs_.ttRegSize.bits.SIZE = ttBuffSize_ >> TT_BUFF_ALIGN_SHIFT; -} - -void Gfx9ThreadTrace::BeginSession(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter) { - // Program Grbm to broadcast messages to all shader engines - regGRBM_GFX_INDEX grbm_gfx_index; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, grbm_gfx_index.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Disable RLC Perfmon Clock Gating - // On Vega this is needed to collect Perf Cntrs - // cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmRLC_PERFMON_CLK_CNTL, 1); - - // Program the Compute register to indicate SQTT is enabled - /* - regCOMPUTE_THREAD_TRACE_ENABLE enableTT = {0}; - enableTT.bits.THREAD_TRACE_ENABLE = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, - mmCOMPUTE_THREAD_TRACE_ENABLE, - enableTT.u32All); - */ - - // Program the thread trace mask - specifies SH, CU, SIMD and - // VM Id masks to apply. Enabling SQ/SPI/REG_STALL_EN bits - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MASK, - ttCfgRegs_.ttRegMask.u32All); - - // Program the thread trace Perf mask - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_PERF_MASK, - ttCfgRegs_.ttRegPerfMask.u32All); - - // Program the thread trace token mask - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_TOKEN_MASK, - ttCfgRegs_.ttRegTokenMask.u32All); - - // Program the thread trace token mask2 to specify the list of instruction - // tokens to record. Disabling INST_PC instruction tokens - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_TOKEN_MASK2, - ttCfgRegs_.ttRegTokenMask2.u32All); - - // Program the thread trace mode register - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MODE, - ttCfgRegs_.ttRegMode.u32All); - - // Program the HiWaterMark register to support stalling - if ((ttCfgRegs_.ttRegMask.bits.SQ_STALL_EN) || (ttCfgRegs_.ttRegMask.bits.SPI_STALL_EN) || - (ttCfgRegs_.ttRegMask.bits.REG_STALL_EN) || - (ttCfgRegs_.ttRegTokenMask.bits.REG_DROP_ON_STALL)) { - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_HIWATER, 0x06); - } - - // Iterate through the list of SE's and program the register - // for carrying address of thread trace buffer which is aligned - // to 4KB per thread trace specification - uint64_t baseAddr = 0; - for (int idx = 0; idx < numSE_; idx++) { - // Program Grbm to direct writes to one SE - grbm_gfx_index.bitfields.SH_INDEX = 0; - grbm_gfx_index.bitfields.SE_INDEX = idx; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, grbm_gfx_index.u32All); - - // Program base2 address of buffer to use for thread trace - /* - regSQ_THREAD_TRACE_BASE2 sqttBase2 = {}; - sqttBase2.u32All = 0; - sqttBase2.bits.ADDR_HI = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, - mmSQ_THREAD_TRACE_BASE2, - sqttBase2.u32All); - */ - - // Program the base address to use - baseAddr = devMemList_[idx] >> TT_BUFF_ALIGN_SHIFT; - - // Program base address of buffer to use for thread trace - regSQ_THREAD_TRACE_BASE sqttBase = {}; - sqttBase.bits.ADDR = Low32(baseAddr); - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_BASE, sqttBase.u32All); - - // Program the size of thread trace buffer - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_SIZE, - ttCfgRegs_.ttRegSize.u32All); - - // Program the thread trace ctrl register - regSQ_THREAD_TRACE_CTRL sqttCtrl = {}; - sqttCtrl.u32All = 0; - sqttCtrl.bits.RESET_BUFFER = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_CTRL, sqttCtrl.u32All); - } - - // Reset the GRBM to broadcast mode - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, grbm_gfx_index.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Program the thread trace mode register - ttCfgRegs_.ttRegMode.bits.MODE = SQ_THREAD_TRACE_MODE_ON; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MODE, - ttCfgRegs_.ttRegMode.u32All); - ttCfgRegs_.ttRegMode.bits.MODE = SQ_THREAD_TRACE_MODE_OFF; - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - return; -} - -void Gfx9ThreadTrace::StopSession(DefaultCmdBuf* cmdBuff, CommandWriter* cmdWriter) { - // Program Grbm to broadcast messages to all shader engines - regGRBM_GFX_INDEX grbm_gfx_index; - grbm_gfx_index.u32All = 0; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.INSTANCE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, grbm_gfx_index.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Program the thread trace mode register to disable thread trace - // The MODE register is set to disable thread trace by default - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_MODE, - ttCfgRegs_.ttRegMode.u32All); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - - // Iterate through the list of SE's and read the Status, Counter and - // Write Pointer registers of Thread Trace subsystem - uint64_t baseAddr = 0; - for (int idx = 0; idx < numSE_; idx++) { - // Program Grbm to direct writes to one SE - grbm_gfx_index.bitfields.SH_INDEX = 0; - grbm_gfx_index.bitfields.SE_INDEX = idx; - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 0; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, grbm_gfx_index.u32All); - - // Issue WaitRegMem command to wait until SQTT event has completed - bool funcEq = false; - bool memSpace = false; - uint32_t waitVal = 0x01; - uint32_t maskVal = 0x40000000L; - uint32_t statusOffset = mmSQ_THREAD_TRACE_STATUS - UCONFIG_SPACE_START; - cmdWriter->BuildWaitRegMemCommand(cmdBuff, memSpace, statusOffset, funcEq, maskVal, waitVal); - - // Retrieve the values from various status registers - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_SRC_SYS_PERF_COUNTER, - mmSQ_THREAD_TRACE_STATUS, 0, - ttStatus_ + ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_STATUS), - COPY_DATA_SEL_COUNT_1DW, true); - - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_SRC_SYS_PERF_COUNTER, - mmSQ_THREAD_TRACE_CNTR, 0, - ttStatus_ + ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_CNTR), - COPY_DATA_SEL_COUNT_1DW, true); - - uint32_t wptrIdx = ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_WPTR); - cmdWriter->BuildCopyDataPacket(cmdBuff, COPY_DATA_SEL_SRC_SYS_PERF_COUNTER, - mmSQ_THREAD_TRACE_WPTR, 0, ttStatus_ + wptrIdx, - COPY_DATA_SEL_COUNT_1DW, true); - } - - // Reset the GRBM to broadcast mode - grbm_gfx_index.bitfields.SH_BROADCAST_WRITES = 1; - grbm_gfx_index.bitfields.SE_BROADCAST_WRITES = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmGRBM_GFX_INDEX, grbm_gfx_index.u32All); - - // Initialize cache flush request object - FlushCacheOptions flush; - flush.l1 = true; - flush.l2 = true; - flush.icache = true; - flush.kcache = true; - cmdWriter->BuildFlushCacheCmd(cmdBuff, &flush, NULL, 0); - - // Program the size of thread trace buffer - regSQ_THREAD_TRACE_SIZE ttRegSize = {0}; - ttRegSize.u32All = 0; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_SIZE, ttRegSize.u32All); - - // Program the thread trace ctrl register - regSQ_THREAD_TRACE_CTRL sqttCtrl = {}; - sqttCtrl.u32All = 0; - sqttCtrl.bits.RESET_BUFFER = 1; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmSQ_THREAD_TRACE_CTRL, sqttCtrl.u32All); - - // Program the compute_thread_trace_enable register - /* - regCOMPUTE_THREAD_TRACE_ENABLE disableTT = {0}; - cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, - mmCOMPUTE_THREAD_TRACE_ENABLE, - disableTT.u32All); - */ - - // Disable RLC Perfmon Clock Gating - // On Vega this is needed to collect Perf Cntrs - // cmdWriter->BuildWriteUConfigRegPacket(cmdBuff, mmRLC_PERFMON_CLK_CNTL, 0); - - // Issue a CSPartialFlush cmd including cache flush - cmdWriter->BuildWriteWaitIdlePacket(cmdBuff); - return; -} - -bool Gfx9ThreadTrace::Validate() { - // Iterate through the list of SE to verify - for (int idx = 0; idx < numSE_; idx++) { - // Determine if the buffer has wrapped - uint32_t statusIdx = ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_STATUS); - if (ttStatus_[statusIdx] & 0x80000000) { - return false; - } - - // Adjust the value of Write Ptr which is bits [29-0] - uint32_t wptrIdx = ((TT_STATUS_IDX_MAX * idx) + TT_STATUS_IDX_WPTR); - ttStatus_[wptrIdx] = (ttStatus_[wptrIdx] & TT_WRITE_PTR_MASK); - } - - return true; -} - -} // pm4_profile diff --git a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx9_thread_trace.h b/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx9_thread_trace.h deleted file mode 100644 index 86e0db8734..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/threadtrace/gfx9_thread_trace.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef _GFX9_THREAD_TRACE_H_ -#define _GFX9_THREAD_TRACE_H_ - -#include "gfxip/gfx9/gfx9_registers.h" -#include "gfxip/gfx9/gfx9_typedef.h" -#include "gfxip/gfx9/gfx9_enum.h" -#include "gfxip/gfx9/gfx9_offset.h" -#include "gfxip/gfx9/gfx9_pm4defs.h" -#include "thread_trace.h" - -#include - -using namespace pm4_profile::gfx9; - -namespace pm4_profile { - -typedef struct Gfx9ThreadTraceCfgRegs { - // Size of thread trace buffer - regSQ_THREAD_TRACE_SIZE ttRegSize; - // Thread trace mode - regSQ_THREAD_TRACE_MODE ttRegMode; - // Thread trace wave mask - regSQ_THREAD_TRACE_MASK ttRegMask; - // Thread trace token mask - regSQ_THREAD_TRACE_TOKEN_MASK ttRegTokenMask; - // Thread trace token mask2 - regSQ_THREAD_TRACE_TOKEN_MASK2 ttRegTokenMask2; - // Thread trace perf mask - regSQ_THREAD_TRACE_PERF_MASK ttRegPerfMask; -} Gfx9ThreadTraceCfgRegs; - -// Encapsulates the various Api and structures used to enable a thread -// trace session and collect its data -class Gfx9ThreadTrace : public ThreadTrace { - public: - Gfx9ThreadTrace(); - - ~Gfx9ThreadTrace(); - - // Initializes various data structures and handles that - // are needed to support a thread trace session - bool Init(const ThreadTraceConfig* config); - - // Builds Pm4 command stream to program hardware registers that - // enable a thread trace session, including the issue of an event - // to begin thread session - void BeginSession(pm4_profile::DefaultCmdBuf* cmdBuff, pm4_profile::CommandWriter* cmdWriter); - - // Builds Pm4 command stream to program hardware registers that - // disable a thread trace session, including the issue of an event - // to stop currently ongoing thread session - void StopSession(pm4_profile::DefaultCmdBuf* cmdBuff, pm4_profile::CommandWriter* cmdWriter); - - // Validates that thread trace session ran correctly i.e. did not - // encounter any errors. - bool Validate(); - - // Initializes the handle of buffer used to collect SQTT data - void setSqttDataBuff(uint8_t* sqttBuffer, uint32_t sqttBuffSz); - - // Initializes the handle of buffer used to read control data of SQTT - void setSqttCtrlBuff(uint32_t* ctrlBuff) { ttStatus_ = ctrlBuff; } - - // Return status info size - uint32_t StatusSizeInfo() const { return TT_STATUS_IDX_MAX * sizeof(uint32_t) * numSE_; } - - // Return number of Shader Engines - uint32_t getNumSe() { return numSE_; } - - private: - // Holds number of Shader Engines present on device - uint32_t numSE_; - - // Thread traces status register indices to determine - // status of thread trace run - typedef enum { - TT_STATUS_IDX_STATUS = 0, - TT_STATUS_IDX_CNTR = 1, - TT_STATUS_IDX_WPTR = 2, - TT_STATUS_IDX_MAX = 3 - } TTStatusReg; - - // A list of tuples of TT_STATUS_IDX_MAX size, - // giving status of thread trace - uint32_t* ttStatus_; - - // Size of thread trace buffer per shader engine - uint32_t ttBuffSize_; - - // Handles of Device memory used for thread trace - std::vector devMemList_; - - // Registers that need to be programmed for Thread Trace - Gfx9ThreadTraceCfgRegs ttCfgRegs_; - - // Initializes thread trace registers with default parameters. - // These are potentially updated based on updates to thread trace - // configuration object by user - void InitThreadTraceCfgRegs(); -}; - -} // pm4_profile - -#endif // _GFX9_THREAD_TRACE_H_ diff --git a/runtime/hsa-amd-aqlprofile/src/threadtrace/thread_trace.cpp b/runtime/hsa-amd-aqlprofile/src/threadtrace/thread_trace.cpp deleted file mode 100644 index 50e2920307..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/threadtrace/thread_trace.cpp +++ /dev/null @@ -1,59 +0,0 @@ -#include - -#include "thread_trace.h" - -namespace pm4_profile { - -bool ThreadTrace::Init(const ThreadTraceConfig* config) { - if (config) { - ttConfig_ = *config; - } else { - InitThreadTraceConfig(&ttConfig_); - } - return true; -} - -void ThreadTrace::InitThreadTraceConfig(ThreadTraceConfig* config) const { - memset(config, 0, sizeof(ThreadTraceConfig)); - - config->threadTraceTargetCu = 0; - config->threadTraceVmIdMask = 0; - config->threadTraceMask = 0; - config->threadTraceTokenMask = 0; - config->threadTraceTokenMask2 = 0; -} - -uint8_t ThreadTrace::GetCuId() { - uint32_t cuId = ttConfig_.threadTraceTargetCu; - assert((cuId <= 15) && "Cu Id must be between 0 and 15"); - return cuId; -} - -uint8_t ThreadTrace::GetVmId() { - uint32_t vmId = ttConfig_.threadTraceVmIdMask; - assert((vmId <= 2) && "VmId must be between 0 and 2"); - return vmId; -} - -uint32_t ThreadTrace::GetMask() { - uint32_t ttMask = ttConfig_.threadTraceMask; - const uint32_t validMask = 0x00C0D0; - assert(((ttMask & validMask) == 0) && "Mask should have bits [4,6,7] set to Zero"); - return ttMask; -} - -uint32_t ThreadTrace::GetTokenMask() { - uint32_t tokenMask = ttConfig_.threadTraceTokenMask; - const uint32_t validMask = 0xFF000000; - assert(((tokenMask & validMask) == 0) && "TokenMask should have bits [31:25] set to Zero"); - return tokenMask; -} - -uint32_t ThreadTrace::GetTokenMask2() { - uint32_t tokenMask2 = ttConfig_.threadTraceTokenMask2; - const uint32_t validMask = 0xFFFF0000; - assert(((tokenMask2 & validMask) == 0) && "TokenMask2 should have bits [31:16] set to Zero"); - return tokenMask2; -} - -} // pm4_profile diff --git a/runtime/hsa-amd-aqlprofile/src/threadtrace/thread_trace.h b/runtime/hsa-amd-aqlprofile/src/threadtrace/thread_trace.h deleted file mode 100644 index 6bc34f9b46..0000000000 --- a/runtime/hsa-amd-aqlprofile/src/threadtrace/thread_trace.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _THREAD_TRACE_H_ -#define _THREAD_TRACE_H_ - -#include - -#include "cmdwriter.h" - -// Move them as static variables later on -#define TT_WRITE_PTR_MASK (0x3FFFFFFF) -// Size of block in bytesper increment in WPTR -#define TT_WRITE_PTR_BLK (32) -// Factor by which to shift buffer address -#define TT_BUFF_ALIGN_SHIFT (12) - -namespace pm4_profile { - -// ThreadTrace config -typedef struct ThreadTraceConfig { - uint32_t threadTraceTargetCu; - uint32_t threadTraceVmIdMask; - uint32_t threadTraceMask; - uint32_t threadTraceTokenMask; - uint32_t threadTraceTokenMask2; -} ThreadTraceConfig; - -// Encapsulates the various Api and structures that are used to enable -// a thread trace session and collect its data. Implementations of this -// interface program device specific registers to realize the functionality -class ThreadTrace { - // Holds Thread Trace configuration information - // @note: Currently not used i.e. is not exposed to users - ThreadTraceConfig ttConfig_; - - public: - // Destructor of the thread trace service handle - virtual ~ThreadTrace(){}; - - // Obtain the CU id to use for thread tracing - uint8_t GetCuId(); - - // Obtain the VM id to use for thread tracing - uint8_t GetVmId(); - - // Obtain the Mask to use for thread tracing - uint32_t GetMask(); - - // Obtain the Token Mask 1 to use for thread tracing - uint32_t GetTokenMask(); - - // Obtain the Token Mask 2 to use for thread tracing - uint32_t GetTokenMask2(); - - // Initializes various data structures and handles that - // are needed to support a thread trace session - virtual bool Init(const ThreadTraceConfig* config); - - // Initializes thread trace configuration object with default - // parameters, that could potentially be overriden by user - // @note: Currently not used i.e. is not exposed to users - virtual void InitThreadTraceConfig(ThreadTraceConfig* config) const; - - // Allows user to configure various parameters of a thread trace session - // @note: Currently not used i.e. is not exposed to users - bool Config(uint32_t key, uint32_t value) { return true; }; - - // Builds Pm4 command stream to program hardware registers that - // enable a thread trace session, including the issue of an event - // to begin thread session - virtual void BeginSession(pm4_profile::DefaultCmdBuf* cmdBuff, - pm4_profile::CommandWriter* cmdWriter) = 0; - - // Builds Pm4 command stream to program hardware registers that - // disable a thread trace session, including the issue of an event - // to stop currently ongoing thread session - virtual void StopSession(pm4_profile::DefaultCmdBuf* cmdBuff, - pm4_profile::CommandWriter* cmdWriter) = 0; - - // Validates that thread trace session ran correctly i.e. did not - // encounter any errors. - virtual bool Validate() = 0; - - // Initializes the handle of buffer used to collect SQTT data - virtual void setSqttDataBuff(uint8_t* sqttBuffer, uint32_t sqttBuffSz) = 0; - - // Initializes the handle of buffer used to read control data of SQTT - virtual void setSqttCtrlBuff(uint32_t* ctrlBuff) = 0; - - // Return number of Shader Engines - virtual uint32_t getNumSe() = 0; - - // Return status info size - virtual uint32_t StatusSizeInfo() const = 0; -}; - -} // pm4_profile - -#endif // _THREAD_TRACE_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/CMakeLists.txt b/runtime/hsa-amd-aqlprofile/test/CMakeLists.txt deleted file mode 100644 index 0b4e0461db..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/CMakeLists.txt +++ /dev/null @@ -1,48 +0,0 @@ -# -# Header files include path(s). -# -include_directories ( $ENV{ROCR_INC_DIR} ) -include_directories ( ${API_DIR} ) -include_directories ( ${TEST_DIR}/util ) -include_directories ( ${TEST_DIR}/ctrl ) - -# -# Specify the directory containing the libraries of HsaRt -# to be linked against for building a Hsa Perf application -# -LINK_DIRECTORIES($ENV{ROCR_LIB_DIR}) -find_library ( ROCR_LIB NAMES hsa-runtime64 PATHS $ENV{ROCR_LIB_DIR} ) - -# -# Set Name for Common library and build it as a -# static library to be linked with others -# -set ( UTIL_LIB "util${ONLY64STR}" ) -add_subdirectory ( ${TEST_DIR}/util "${PROJECT_BINARY_DIR}/util" ) - -# -# Build the test library -# -set ( TEST_NAME simple_convolution ) -include_directories ( ${TEST_DIR}/${TEST_NAME} ) -set ( LIB_NAME "${TEST_NAME}${ONLY64STR}" ) -add_library ( ${LIB_NAME} STATIC ${TEST_DIR}/${TEST_NAME}/${TEST_NAME}.cpp ) -target_link_libraries( ${LIB_NAME} c stdc++ ) -set ( TEST_LIBS ${LIB_NAME} ) - -# -# Build the test control -# -set ( SRC_LIST ${TEST_DIR}/ctrl/test.cpp ) -set ( SRC_LIST ${SRC_LIST} ${TEST_DIR}/ctrl/test_pmgr.cpp ) -set ( SRC_LIST ${SRC_LIST} ${TEST_DIR}/ctrl/test_hsa.cpp ) -set ( LIB_LIST ${TEST_LIBS} ${UTIL_LIB} ${CORE_UTILS_LIB} ${ROCR_LIB} ) -set ( EXE_NAME "ctrl" ) -add_executable ( ${EXE_NAME} ${SRC_LIST} ) -target_link_libraries( ${EXE_NAME} ${LIB_LIST} c stdc++ dl pthread rt atomic ) - -# -# Copy the test files -# -execute_process ( COMMAND sh -xc "cp ${TEST_DIR}/${TEST_NAME}/*.hsaco ${PROJECT_BINARY_DIR}" ) -execute_process ( COMMAND sh -xc "cp ${TEST_DIR}/run.sh ${PROJECT_BINARY_DIR}" ) diff --git a/runtime/hsa-amd-aqlprofile/test/binary_search/binary_search.cc b/runtime/hsa-amd-aqlprofile/test/binary_search/binary_search.cc deleted file mode 100755 index 9d699abbc0..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/binary_search/binary_search.cc +++ /dev/null @@ -1,876 +0,0 @@ -/* - * ============================================================================= - * ROC Runtime Conformance Release License - * ============================================================================= - * The University of Illinois/NCSA - * Open Source License (NCSA) - * - * Copyright (c) 2017, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Developed by: - * - * AMD Research and AMD ROC Software Development - * - * Advanced Micro Devices, Inc. - * - * www.amd.com - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal with the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimers. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimers in - * the documentation and/or other materials provided with the distribution. - * - Neither the names of , - * nor the names of its contributors may be used to endorse or promote - * products derived from this Software without specific prior written - * permission. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS WITH THE SOFTWARE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "hsa/hsa.h" -#include "hsa/hsa_ext_amd.h" - -#define RET_IF_HSA_ERR(err) { \ - if ((err) != HSA_STATUS_SUCCESS) { \ - std::cout << "hsa api call failure at line " << __LINE__ << ", file: " << \ - __FILE__ << ". Call returned " << err << std::endl; \ - return (err); \ - } \ -} - -static const uint32_t kBinarySearchLength = 512; -static const uint32_t kBinarySearchFindMe = 108; -static const uint32_t kWorkGroupSize = 256; - -// Hold all the info specific to binary search -typedef struct BinarySearch { - // Binary Search parameters - uint32_t length; - uint32_t work_group_size; - uint32_t work_grid_size; - uint32_t num_sub_divisions; - uint32_t find_me; - - // Buffers needed for this application - uint32_t* input; - uint32_t* input_arr; - uint32_t* input_arr_local; - uint32_t* output; - // Keneral argument buffers and addresses - void* kern_arg_buffer; // Begin of allocated memory - // this pointer to be deallocated - void* kern_arg_address; // Properly aligned address to be used in aql - // packet (don't use for deallocation) - - // Kernel code - std::string kernel_file_name; - std::string kernel_name; - uint32_t kernarg_size; - uint32_t kernarg_align; - - // HSA/RocR objects needed for this application - hsa_agent_t gpu_dev; - hsa_agent_t cpu_dev; - hsa_signal_t signal; - hsa_queue_t* queue; - hsa_amd_memory_pool_t cpu_pool; - hsa_amd_memory_pool_t gpu_pool; - hsa_amd_memory_pool_t kern_arg_pool; - - // Other items we need to populate AQL packet - uint64_t kernel_object; - uint32_t group_segment_size; ///< Kernel group seg size - uint32_t private_segment_size; ///< Kernel private seg size -} BinarySearch; - -void InitializeBinarySearch(BinarySearch* bs) { - bs->kernel_file_name = "./binary_search_kernels.hsaco"; - bs->kernel_name = "binarySearch"; - bs->length = 512; - bs->find_me = 108; - bs->work_group_size = 256; - bs->num_sub_divisions = bs->length / bs->work_group_size; -} - -// This function is called by the call-back functions used to find an agent of -// the specified hsa_device_type_t. Note that it cannot be called directly from -// hsa_iterate_agents() as it does not match the prototype of the call-back -// function. It must be wrapped by a function with the correct prototype. -// -// Return values: -// HSA_STATUS_INFO_BREAK -- "agent" is of the specified type (dev_type) -// HSA_STATUS_SUCCESS -- "agent" is not of the specified type -// Other -- Some error occurred -static hsa_status_t FindAgent(hsa_agent_t agent, void* data, - hsa_device_type_t dev_type) { - if (data == nullptr) { - return HSA_STATUS_ERROR_INVALID_ARGUMENT; - } - - // See if the provided agent matches the input type (dev_type) - hsa_device_type_t hsa_device_type; - hsa_status_t hsa_error_code = hsa_agent_get_info(agent, HSA_AGENT_INFO_DEVICE, - &hsa_device_type); - RET_IF_HSA_ERR(hsa_error_code); - - if (hsa_device_type == dev_type) { - *(reinterpret_cast(data)) = agent; - return HSA_STATUS_INFO_BREAK; - } - - return HSA_STATUS_SUCCESS; -} - -// This is the call-back function used to find a GPU type agent. Note that the -// prototype of this function is dictated by the HSA specification -hsa_status_t FindGPUDevice(hsa_agent_t agent, void* data) { - return FindAgent(agent, data, HSA_DEVICE_TYPE_GPU); -} - -// This is the call-back function used to find a CPU type agent. Note that the -// prototype of this function is dictated by the HSA specification -hsa_status_t FindCPUDevice(hsa_agent_t agent, void* data) { - return FindAgent(agent, data, HSA_DEVICE_TYPE_CPU); -} - -// Find the CPU and GPU agents we need to run this sample, and save them in the -// BinarySearch structure for later use. -hsa_status_t FindDevices(BinarySearch* bs) { - hsa_status_t err; - - // Note that hsa_iterate_agents iterate through all known agents until - // HSA_STATUS_SUCCESS is not returned. The call-backs are implemented such - // that HSA_STATUS_INFO_BREAK means we found an agent of the specified type. - // This value is returned by hsa_iterate_agents. - bs->gpu_dev.handle = 0; - err = hsa_iterate_agents(FindGPUDevice, &bs->gpu_dev); - - if (err != HSA_STATUS_INFO_BREAK) { - return HSA_STATUS_ERROR; - } - - bs->cpu_dev.handle = 0; - err = hsa_iterate_agents(FindCPUDevice, &bs->cpu_dev); - - if (err != HSA_STATUS_INFO_BREAK) { - return HSA_STATUS_ERROR; - } - - if (0 == bs->gpu_dev.handle) { - std::cout << "GPU Device is not Created properly!" << std::endl; - RET_IF_HSA_ERR(HSA_STATUS_ERROR); - } - - if (0 == bs->cpu_dev.handle) { - std::cout << "CPU Device is not Created properly!" << std::endl; - RET_IF_HSA_ERR(HSA_STATUS_ERROR); - } - - return HSA_STATUS_SUCCESS; -} - -// This function checks to see if the provided -// pool has the HSA_AMD_SEGMENT_GLOBAL property. If the kern_arg flag is true, -// the function adds an additional requirement that the pool have the -// HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT property. If kern_arg is false, -// pools must NOT have this property. -// Upon finding a pool that meets these conditions, HSA_STATUS_INFO_BREAK is -// returned. HSA_STATUS_SUCCESS is returned if no errors were encountered, but -// no pool was found meeting the requirements. If an error is encountered, we -// return that error. - -// Note that this function does not match the required prototype for the -// hsa_amd_agent_iterate_memory_pools call back function, and therefore must be -// wrapped by a function with the correct prototype. -static hsa_status_t -FindGlobalPool(hsa_amd_memory_pool_t pool, void* data, bool kern_arg) { - hsa_status_t err; - hsa_amd_segment_t segment; - uint32_t flag; - - if (nullptr == data) { - return HSA_STATUS_ERROR_INVALID_ARGUMENT; - } - - err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SEGMENT, - &segment); - RET_IF_HSA_ERR(err); - - if (HSA_AMD_SEGMENT_GLOBAL != segment) { - return HSA_STATUS_SUCCESS; - } - - err = hsa_amd_memory_pool_get_info(pool, - HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS, &flag); - RET_IF_HSA_ERR(err); - - uint32_t karg_st = flag & HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT; - - if ((karg_st == 0 && kern_arg) || - (karg_st != 0 && !kern_arg)) { - return HSA_STATUS_SUCCESS; - } - - *(reinterpret_cast(data)) = pool; - return HSA_STATUS_INFO_BREAK; -} - -// This is the call-back function for hsa_amd_agent_iterate_memory_pools() that -// finds a pool with the properties of HSA_AMD_SEGMENT_GLOBAL and that is NOT -// HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT -hsa_status_t FindStandardPool(hsa_amd_memory_pool_t pool, void* data) { - return FindGlobalPool(pool, data, false); -} - -// This is the call-back function for hsa_amd_agent_iterate_memory_pools() that -// finds a pool with the properties of HSA_AMD_SEGMENT_GLOBAL and that IS -// HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT -hsa_status_t FindKernArgPool(hsa_amd_memory_pool_t pool, void* data) { - return FindGlobalPool(pool, data, true); -} - -// Find memory pools that we will need to allocate from for this sample -// application. We will need memory associated with the host CPU, the GPU -// executing the kernels, and for kernel arguments. This function will -// save the found pools to the BinarySearch structure for use elsewhere -// in this program. -hsa_status_t FindPools(BinarySearch* bs) { - hsa_status_t err; - - err = hsa_amd_agent_iterate_memory_pools(bs->cpu_dev, FindStandardPool, - &bs->cpu_pool); - - if (err != HSA_STATUS_INFO_BREAK) { - return HSA_STATUS_ERROR; - } - - err = hsa_amd_agent_iterate_memory_pools(bs->gpu_dev, FindStandardPool, - &bs->gpu_pool); - - if (err != HSA_STATUS_INFO_BREAK) { - return HSA_STATUS_ERROR; - } - - err = hsa_amd_agent_iterate_memory_pools(bs->cpu_dev, - FindKernArgPool, &bs->kern_arg_pool); - - if (err != HSA_STATUS_INFO_BREAK) { - return HSA_STATUS_ERROR; - } - - return HSA_STATUS_SUCCESS; -} - -// Once the needed memory pools have been found and the BinarySearch structure -// has been updated with these handles, this function is then used to allocate -// memory from those pools. -// Devices with which a pool is associated already have access to the pool. -// However, other devices may also need to read or write to that memory. Below, -// we see how we can grant access to other devices to address this issue. -hsa_status_t AllocateAndInitBuffers(BinarySearch* bs) { - hsa_status_t err; - uint32_t out_length = 4 * sizeof(uint32_t); - uint32_t in_length = bs->num_sub_divisions * 2 * sizeof(uint32_t); - - // In all of these examples, we want both the cpu and gpu to have access to - // the buffer in question. We use the array of agents below in the susequent - // calls to hsa_amd_agents_allow_access() for this purpose. - hsa_agent_t ag_list[2] = {bs->gpu_dev, bs->cpu_dev}; - - err = hsa_amd_memory_pool_allocate(bs->cpu_pool, in_length, 0, - reinterpret_cast(&bs->input)); - RET_IF_HSA_ERR(err); - err = hsa_amd_agents_allow_access(2, ag_list, NULL, bs->input); - RET_IF_HSA_ERR(err); - (void)memset(bs->input, 0, in_length); - - err = hsa_amd_memory_pool_allocate(bs->cpu_pool, out_length, 0, - reinterpret_cast(&bs->output)); - RET_IF_HSA_ERR(err); - err = hsa_amd_agents_allow_access(2, ag_list, NULL, bs->output); - RET_IF_HSA_ERR(err); - (void)memset(bs->input, 0, in_length); - - err = hsa_amd_memory_pool_allocate(bs->cpu_pool, in_length, 0, - reinterpret_cast(&bs->input_arr)); - RET_IF_HSA_ERR(err); - err = hsa_amd_agents_allow_access(2, ag_list, NULL, bs->input_arr); - RET_IF_HSA_ERR(err); - (void)memset(bs->input, 0, in_length); - - err = hsa_amd_memory_pool_allocate(bs->cpu_pool, in_length, 0, - reinterpret_cast(&bs->input_arr_local)); - RET_IF_HSA_ERR(err); - err = hsa_amd_agents_allow_access(2, ag_list, NULL, bs->input_arr_local); - RET_IF_HSA_ERR(err); - - // Binary-search application specific code... - // Initialize input buffer with random values in an increasing order - uint32_t max = bs->length * 20; - bs->input[0] = 0; - - uint32_t seed = (unsigned int)time(NULL); - srand(seed); - - for (uint32_t i = 1; i < bs->length; ++i) { - bs->input[i] = bs->input[i - 1] + - static_cast(max * rand_r(&seed) / static_cast(RAND_MAX)); - } - -// #define VERBOSE 1 -#ifdef VERBOSE - std::cout << "Input array values:" << std::endl; - - for (uint32_t i = 0; i < bs->length; ++i) { - std::cout << "input[" << i << "] = " << bs->input[i] << " "; - - if (i % 4 == 0) { - std::cout << std::endl; - } - } - - std::cout << std::endl; -#endif - - return err; -} - -// The code in this function illustrates how to load a kernel from -// pre-compiled code. The goal is to get a handle that can be later -// used in an AQL packet and also to extract information about kernel -// that we will need. All of the information hand kernel handle will -// be saved to the BinarySearch structure. It will be used when we -// populate the AQL packet. -hsa_status_t LoadKernelFromObjFile(BinarySearch* bs) { - hsa_status_t err; - hsa_code_object_reader_t code_obj_rdr = {0}; - hsa_executable_t executable = {0}; - - hsa_file_t file_handle = open(bs->kernel_file_name.c_str(), O_RDONLY); - - if (file_handle == -1) { - std::cout << "failed to open " << bs->kernel_file_name.c_str() << - " at line " << __LINE__ << ", errno: " << errno << std::endl; - return HSA_STATUS_ERROR; - } - - err = hsa_code_object_reader_create_from_file(file_handle, &code_obj_rdr); - RET_IF_HSA_ERR(err); - close(file_handle); - - err = hsa_executable_create_alt(HSA_PROFILE_FULL, - HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT, NULL, &executable); - RET_IF_HSA_ERR(err); - - err = hsa_executable_load_agent_code_object(executable, bs->gpu_dev, - code_obj_rdr, NULL, NULL); - RET_IF_HSA_ERR(err); - - err = hsa_executable_freeze(executable, NULL); - RET_IF_HSA_ERR(err); - - hsa_executable_symbol_t kern_sym; - err = hsa_executable_get_symbol(executable, NULL, bs->kernel_name.c_str(), - bs->gpu_dev, 0, &kern_sym); - RET_IF_HSA_ERR(err); - - err = hsa_executable_symbol_get_info(kern_sym, - HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT, - &bs->kernel_object); - RET_IF_HSA_ERR(err); - - err = hsa_executable_symbol_get_info(kern_sym, - HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE, - &bs->private_segment_size); - RET_IF_HSA_ERR(err); - - err = hsa_executable_symbol_get_info(kern_sym, - HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE, - &bs->group_segment_size); - RET_IF_HSA_ERR(err); - - err = hsa_executable_symbol_get_info(kern_sym, - HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE, - &bs->kernarg_size); - RET_IF_HSA_ERR(err); - - err = hsa_executable_symbol_get_info(kern_sym, - HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT, - &bs->kernarg_align); - RET_IF_HSA_ERR(err); - - return err; -} - -// This function shows how to do an asynchronous copy. We have to create a -// signal and use the signal to notify us when the copy has completed. -hsa_status_t AgentMemcpy(void* dst, const void* src, - size_t size, hsa_agent_t dst_ag, hsa_agent_t src_ag) { - hsa_signal_t s; - hsa_status_t err; - - err = hsa_signal_create(1, 0, NULL, &s); - RET_IF_HSA_ERR(err); - - err = hsa_amd_memory_async_copy(dst, dst_ag, src, src_ag, size, 0, NULL, s); - RET_IF_HSA_ERR(err); - - if (hsa_signal_wait_scacquire(s, HSA_SIGNAL_CONDITION_LT, 1, - UINT64_MAX, HSA_WAIT_STATE_BLOCKED) != 0) { - err = HSA_STATUS_ERROR; - std::cout << "Async copy signal error" << std::endl; - - RET_IF_HSA_ERR(err); - } - - err = hsa_signal_destroy(s); - - RET_IF_HSA_ERR(err); - - return err; -} - -// AlignDown and AlignUp are 2 utility functions we use to find an aligned -// boundary either below or above a given value (address). The function will -// return a value that has the specified alignment. -static intptr_t -AlignDown(intptr_t value, size_t alignment) { - return (intptr_t) (value & ~(alignment - 1)); -} -static void* -AlignUp(void* value, size_t alignment) { - return reinterpret_cast(AlignDown((uintptr_t) - (reinterpret_cast(value) + alignment - 1), alignment)); -} - -// This function populates the AQL patch with the information -// we have collected and stored in the BinarySearch structure thus far. -void PopulateAQLPacket(BinarySearch const* bs, - hsa_kernel_dispatch_packet_t* aql) { - aql->header = 0; // Dummy val. for now. Set this right before doorbell ring - aql->setup = 1; - aql->workgroup_size_x = bs->work_group_size; - aql->workgroup_size_y = 1; - aql->workgroup_size_z = 1; - aql->grid_size_x = bs->work_grid_size; - aql->grid_size_y = 1; - aql->grid_size_z = 1; - aql->private_segment_size = bs->private_segment_size; - aql->group_segment_size = bs->group_segment_size; - aql->kernel_object = bs->kernel_object; - aql->kernarg_address = bs->kern_arg_address; - aql->completion_signal = bs->signal; - - return; -} -/* - * Write everything in the provided AQL packet to the queue except the first 32 - * bits which include the header and setup fields. That should be done - * last. - */ -void WriteAQLToQueue(hsa_kernel_dispatch_packet_t const* in_aql, - hsa_queue_t* q) { - void* queue_base = q->base_address; - const uint32_t queue_mask = q->size - 1; - uint64_t que_idx = hsa_queue_add_write_index_relaxed(q, 1); - - hsa_kernel_dispatch_packet_t* queue_aql_packet; - - queue_aql_packet = - &(reinterpret_cast(queue_base)) - [que_idx & queue_mask]; - - queue_aql_packet->workgroup_size_x = in_aql->workgroup_size_x; - queue_aql_packet->workgroup_size_y = in_aql->workgroup_size_y; - queue_aql_packet->workgroup_size_z = in_aql->workgroup_size_z; - queue_aql_packet->grid_size_x = in_aql->grid_size_x; - queue_aql_packet->grid_size_y = in_aql->grid_size_y; - queue_aql_packet->grid_size_z = in_aql->grid_size_z; - queue_aql_packet->private_segment_size = in_aql->private_segment_size; - queue_aql_packet->group_segment_size = in_aql->group_segment_size; - queue_aql_packet->kernel_object = in_aql->kernel_object; - queue_aql_packet->kernarg_address = in_aql->kernarg_address; - queue_aql_packet->completion_signal = in_aql->completion_signal; -} - -// This function allocates memory from the kern_arg pool we already found, and -// then sets the argument values needed by the kernel code. -hsa_status_t AllocAndSetKernArgs(BinarySearch* bs, void* args, - size_t arg_size, void** aql_buf_ptr) { - void* kern_arg_buf = nullptr; - hsa_status_t err; - size_t buf_size; - size_t req_align; - - // The kernel code must be written to memory at the correct alignment. We - // already queried the executable to get the correct alignment, which is - // stored in bs->kernarg_align. In case the memory returned from - // hsa_amd_memory_pool is not of the correct alignment, we request a little - // more than what we need in case we need to adjust. - req_align = bs->kernarg_align; - // Allocate enough extra space for alignment adjustments if ncessary - buf_size = arg_size + (req_align << 1); - - err = hsa_amd_memory_pool_allocate(bs->kern_arg_pool, buf_size, 0, - reinterpret_cast(&kern_arg_buf)); - RET_IF_HSA_ERR(err); - - // Address of the allocated buffer - bs->kern_arg_buffer = kern_arg_buf; - - // Addr. of kern arg start. - bs->kern_arg_address = AlignUp(kern_arg_buf, req_align); - - assert(arg_size >= bs->kernarg_size); - assert(((uintptr_t)bs->kern_arg_address + arg_size) < - ((uintptr_t)bs->kern_arg_buffer + buf_size)); - - (void)memcpy(bs->kern_arg_address, args, arg_size); - RET_IF_HSA_ERR(err); - - // Make sure both the CPU and GPU can access the kernel arguments - hsa_agent_t ag_list[2] = {bs->gpu_dev, bs->cpu_dev}; - err = hsa_amd_agents_allow_access(2, ag_list, NULL, bs->kern_arg_buffer); - RET_IF_HSA_ERR(err); - - // Save this info in our BinarySearch structure for later. - *aql_buf_ptr = bs->kern_arg_address; - - return HSA_STATUS_SUCCESS; -} - -// This wrapper atomically writes the provided header and setup to the -// provided AQL packet. The provided AQL packet address should be in the -// queue memory space. -inline void AtomicSetPacketHeader(uint16_t header, uint16_t setup, - hsa_kernel_dispatch_packet_t* queue_packet) { - __atomic_store_n(reinterpret_cast(queue_packet), - header | (setup << 16), __ATOMIC_RELEASE); -} - -// Once all the required data for kernel execution is collected (in this -// application it is stored in the BinarySearch structure) we can put it in -// an AQL packet and ring the queue door bell to tell the command processor to -// execute it. -hsa_status_t Run(BinarySearch* bs) { - hsa_status_t err; - - std::cout << "Executing kernel " << bs->kernel_name << std::endl; - - // Adjust the size of workgroup - // This is mostly application specific. - if (bs->work_group_size > 64) { - bs->work_group_size = 64; - bs->num_sub_divisions = bs->length / bs->work_group_size; - - if (bs->num_sub_divisions < bs->work_group_size) { - bs->num_sub_divisions = bs->work_group_size; - } - - bs->work_grid_size = bs->num_sub_divisions; - } - - // Explanation of BinarySearch algorithm. - /* - * Since a plain binary search on the GPU would not achieve much benefit - * over the GPU we are doing an N'ary search. We split the array into N - * segments every pass and therefore get log (base N) passes instead of log - * (base 2) passes. - * - * In every pass, only the thread that can potentially have the element we - * are looking for writes to the output array. For ex: if we are looking to - * find 4567 in the array and every thread is searching over a segment of - * 1000 values and the input array is 1, 2, 3, 4,... then the first thread - * is searching in 1 to 1000, the second one from 1001 to 2000, etc. The - * first one does not write to the output. The second one doesn't either. - * The fifth one however is from 4001 to 5000. So it can potentially have - * the element 4567 which lies between them. - * - * This particular thread writes to the output the lower bound, upper bound - * and whether the element equals the lower bound element. So, it would be - * 4001, 5000, 0 - * - * The next pass would subdivide 4001 to 5000 into smaller segments and - * continue the same process from there. - * - * When a pass returns 1 in the third element, it means the element has been - * found and we can stop executing the kernel. If the element is not found, - * then the execution stops after looking at segment of size 1. - */ - - uint32_t global_lower_bound = 0; - uint32_t global_upper_bound = bs->length - 1; - uint32_t sub_div_size = (global_upper_bound - global_lower_bound + 1) / - bs->num_sub_divisions; - - if ((bs->input[0] > bs->find_me) || - (bs->input[bs->length - 1] < bs->find_me)) { - bs->output[0] = 0; - bs->output[1] = bs->length - 1; - bs->output[2] = 0; - std::cout << "Returning too early" << std::endl; - return HSA_STATUS_SUCCESS; - } - - bs->output[3] = 1; - - // Setup the kernel args - // See the meta-data for the compiled OpenCL kernel code to ascertain - // the sizes, padding and alignment required for kernel arguments. - // This can be seen by executing - // $ amdgcn-amd-amdhsa-readelf -aw ./binary_search_kernels.hsaco - // The kernel code will expect the following arguments aligned as shown. - typedef uint32_t uint2[2]; - typedef uint32_t uint4[4]; - struct __attribute__((aligned(16))) local_args_t { - uint4* outputArray; - uint2* sortedArray; - uint32_t findMe; - uint32_t pad; - uint64_t global_offset_x; - uint64_t global_offset_y; - uint64_t global_offset_z; - } local_args; - - local_args.outputArray = reinterpret_cast(bs->output); - local_args.sortedArray = reinterpret_cast(bs->input_arr_local); - local_args.findMe = bs->find_me; - local_args.global_offset_x = 0; - local_args.global_offset_y = 0; - local_args.global_offset_z = 0; - - // Copy the kernel args structure into kernel arg memory - err = AllocAndSetKernArgs(bs, &local_args, sizeof(local_args), - &bs->kern_arg_address); - RET_IF_HSA_ERR(err); - - // Populate an AQL packet with the info we've gathered - hsa_kernel_dispatch_packet_t aql; - PopulateAQLPacket(bs, &aql); - - uint32_t in_length = bs->num_sub_divisions * 2 * sizeof(uint32_t); - - while ((sub_div_size > 1) && (bs->output[3] != 0)) { - for (uint32_t i = 0 ; i < bs->num_sub_divisions; i++) { - int idx1 = i * sub_div_size; - int idx2 = ((i + 1) * sub_div_size) - 1; - bs->input_arr[2 * i] = bs->input[idx1]; - bs->input_arr[2 * i + 1] = bs->input[idx2]; - } - - // Copy kernel parameter from system memory to local memory - err = AgentMemcpy(reinterpret_cast(bs->input_arr_local), - reinterpret_cast(bs->input_arr), - in_length, bs->gpu_dev, bs->cpu_dev); - - RET_IF_HSA_ERR(err); - - // Reset output buffer to zero - bs->output[3] = 0; - - // Dispatch kernel with global work size, work group size with ONE dimesion - // and wait for kernel to complete - - // Compute the write index of queue and copy Aql packet into it - uint64_t que_idx = hsa_queue_load_write_index_relaxed(bs->queue); - - const uint32_t mask = bs->queue->size - 1; - - // This function simply copies the data we've collected so far into our - // local AQL packet, except the the setup and header fields. - WriteAQLToQueue(&aql, bs->queue); - - uint32_t aql_header = HSA_PACKET_TYPE_KERNEL_DISPATCH; - aql_header |= HSA_FENCE_SCOPE_SYSTEM << - HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE; - aql_header |= HSA_FENCE_SCOPE_SYSTEM << - HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE; - - // Set the packet's type, acquire and release fences. This should be done - // atomically after all the other fields have been set, using release - // memory ordering to ensure all the fields are set when the door bell - // signal is activated. - void* q_base = bs->queue->base_address; - - AtomicSetPacketHeader(aql_header, aql.setup, - &(reinterpret_cast - (q_base))[que_idx & mask]); - - // Increment the write index and ring the doorbell to dispatch kernel. - hsa_queue_store_write_index_relaxed(bs->queue, (que_idx + 1)); - hsa_signal_store_relaxed(bs->queue->doorbell_signal, que_idx); - - // Wait on the dispatch signal until the kernel is finished. - // Modify the wait condition to HSA_WAIT_STATE_ACTIVE (instead of - // HSA_WAIT_STATE_BLOCKED) if polling is needed instead of blocking, as we - // have below. - // The call below will block until the condition is met. Below we have said - // the condition is that the signal value (initiailzed to 1) associated with - // the queue is less than 1. When the kernel associated with the queued AQL - // packet has completed execution, the signal value is automatically - // decremented by the packet processor. - hsa_signal_value_t value = hsa_signal_wait_scacquire(bs->signal, - HSA_SIGNAL_CONDITION_LT, 1, - UINT64_MAX, HSA_WAIT_STATE_BLOCKED); - - // value should be 0, or we timed-out - if (value) { - std::cout << "Timed out waiting for kernel to complete?" << std::endl; - RET_IF_HSA_ERR(HSA_STATUS_ERROR); - } - - // Reset the signal to its initial value for the next iteration - hsa_signal_store_screlease(bs->signal, 1); - - // Binary search algorithm stuff... - global_lower_bound = bs->output[0] * sub_div_size; - global_upper_bound = global_lower_bound + sub_div_size - 1; - sub_div_size = (global_upper_bound - global_lower_bound + 1) / - bs->num_sub_divisions; - } - - uint32_t element_index = UINT_MAX; - - for (uint32_t i = global_lower_bound; i <= global_upper_bound; i++) { - if (bs->input[i] == bs->find_me) { - element_index = i; - bs->output[0] = i; - bs->output[1] = i + 1; - bs->output[2] = 1; - break; - } - - // Element is not found in region specified - // by global lower bound to global upper bound - bs->output[2] = 0; - } - - uint32_t is_elem_found = bs->output[2]; - - std::cout << "Lower bound = " << global_lower_bound << std::endl; - std::cout << "Upper bound = " << global_upper_bound << std::endl; - std::cout << "Element search for = " << bs->find_me << std::endl; - - - if (is_elem_found == 1) { - std::cout << "Element found at index " << element_index << std::endl; - } else { - std::cout << "Element value " << bs->find_me << " not found" << std::endl; - } - - return HSA_STATUS_SUCCESS; -} - -// Release all the RocR resources we have acquired in this application. -hsa_status_t CleanUp(BinarySearch* bs) { - hsa_status_t err; - - err = hsa_amd_memory_pool_free(bs->input); - RET_IF_HSA_ERR(err); - - err = hsa_amd_memory_pool_free(bs->output); - RET_IF_HSA_ERR(err); - - err = hsa_amd_memory_pool_free(bs->input_arr); - RET_IF_HSA_ERR(err); - - err = hsa_amd_memory_pool_free(bs->kern_arg_buffer); - RET_IF_HSA_ERR(err); - - err = hsa_queue_destroy(bs->queue); - RET_IF_HSA_ERR(err); - - err = hsa_signal_destroy(bs->signal); - RET_IF_HSA_ERR(err); - - err = hsa_shut_down(); - RET_IF_HSA_ERR(err); - - return HSA_STATUS_SUCCESS; -} - -int main(int argc, char* argv[]) { - // This BinarySearch structure (bs) below holds all of the appl. specific - // info we need to run the sample. This includes algorithm specific - // information as well as handles to RocR/HSA objects. - - // The basic structure of this sample is to fill in this structure with the - // required RocR/HSA handles to RocR resources (e.g., agents, memory pools, - // queues, etc.) and then dispatch the packets to the queue, and examine the - // output. - - BinarySearch bs; - hsa_status_t err; - - // Set some working values specific to this application - InitializeBinarySearch(&bs); - - // hsa_init() initializes internal data structures and causes devices - // (agents), memory pools and other resources to be discovered. - err = hsa_init(); - RET_IF_HSA_ERR(err); - - // Find the agents needed for the sample - err = FindDevices(&bs); - RET_IF_HSA_ERR(err); - - // Create the completion signal used when dispatching a packet - err = hsa_signal_create(1, 0, NULL, &bs.signal); - RET_IF_HSA_ERR(err); - - // Create a queue to submit our binary search AQL packets - err = hsa_queue_create(bs.gpu_dev, 128, HSA_QUEUE_TYPE_MULTI, NULL, NULL, - UINT32_MAX, UINT32_MAX, &bs.queue); - RET_IF_HSA_ERR(err); - - // Find the HSA memory pools we need to run this sample - err = FindPools(&bs); - RET_IF_HSA_ERR(err); - - // Allocate memory from the correct memory pool, and initialize them as - // neeeded for the algorihm. - err = AllocateAndInitBuffers(&bs); - RET_IF_HSA_ERR(err); - - // Create a kernel object from the pre-compiled kernel, and read some - // attributes associated with the kernel that we will need. - err = LoadKernelFromObjFile(&bs); - RET_IF_HSA_ERR(err); - - // Fill in the AQL packet, assign the kernel arguments, enqueue the packet, - // "ring" the doorbell, and wait for completion. - err = Run(&bs); - RET_IF_HSA_ERR(err); - - // Release all the RocR resources we've acquired and shutdown HSA. - err = CleanUp(&bs); - - return 0; -} - - -#undef RET_IF_HSA_ERR diff --git a/runtime/hsa-amd-aqlprofile/test/binary_search/binary_search_kernels.cl b/runtime/hsa-amd-aqlprofile/test/binary_search/binary_search_kernels.cl deleted file mode 100755 index eb3cca6c86..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/binary_search/binary_search_kernels.cl +++ /dev/null @@ -1,127 +0,0 @@ -/* - * ============================================================================= - * ROC Runtime Conformance Release License - * ============================================================================= - * The University of Illinois/NCSA - * Open Source License (NCSA) - * - * Copyright (c) 2017, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Developed by: - * - * AMD Research and AMD ROC Software Development - * - * Advanced Micro Devices, Inc. - * - * www.amd.com - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal with the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimers. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimers in - * the documentation and/or other materials provided with the distribution. - * - Neither the names of , - * nor the names of its contributors may be used to endorse or promote - * products derived from this Software without specific prior written - * permission. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS WITH THE SOFTWARE. - * - */ - -/** - * One instance of this kernel call is a thread. - * Each thread finds out the segment in which it should look for the element. - * After that, it checks if the element is between the lower bound and upper - * bound of its segment. If yes, then this segment becomes the total - * searchspace for the next pass. - * - * To achieve this, it writes the lower bound and upper bound to the output - * array. In case the element at the left end (lower bound) matches the element - * we are looking for, that is marked in the output and we no longer need to - * look any further. - */ - -__kernel void -binarySearch(__global uint4 * outputArray, - __const __global uint2 * sortedArray, - const unsigned int findMe) { - unsigned int tid = get_global_id(0); - - // Then we find the elements for this thread - uint2 element = sortedArray[tid]; - - - // If the element to be found does not lie between - // them, then nothing left to do in this thread - if((element.x > findMe) || (element.y < findMe)) { - return; - } else { - // However, if the element does lie between the lower - // and upper bounds of this thread's searchspace - // we need to narrow down the search further in this - // search space - // The search space for this thread is marked in the - // output as being the total search space for the next pass - outputArray[0].x = tid; - outputArray[0].w = 1; - } -} - - -__kernel void -binarySearch_mulkeys(__global int *keys, - __global uint *input, - const unsigned int numKeys, - __global int *output) { - - int gid = get_global_id(0); - int lBound = gid * 256; - int uBound = lBound + 255; - - for(int i = 0; i < numKeys; i++) { - if(keys[i] >= input[lBound] && keys[i] <= input[uBound]) - output[i]=lBound; - } - -} - - -__kernel void -binarySearch_mulkeysConcurrent(__global uint *keys, - __global uint *input, - const unsigned int inputSize, // num. of inputs - const unsigned int numSubdivisions, - __global int *output) { - - int lBound = (get_global_id(0) % numSubdivisions) * (inputSize / numSubdivisions); - int uBound = lBound + inputSize / numSubdivisions; - int myKey = keys[get_global_id(0) / numSubdivisions]; - int mid; - - while(uBound >= lBound) { - mid = (lBound + uBound) / 2; - if(input[mid] == myKey) { - output[get_global_id(0) / numSubdivisions] = mid; - return; - } else if(input[mid] > myKey) { - uBound = mid - 1; - } else { - lBound = mid + 1; - } - } -} diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test.cpp b/runtime/hsa-amd-aqlprofile/test/ctrl/test.cpp deleted file mode 100644 index da865e1d4d..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test.cpp +++ /dev/null @@ -1,91 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include "test_assert.h" -#include "simple_convolution.h" -#include "test_hsa.h" -#include "test_pgen_pmc.h" -#include "test_pgen_sqtt.h" - -int main(int argc, char* argv[]) { -#if defined(NDEBUG) - clog.rdbuf(NULL); -#endif - - bool ret_val = true; - - // Create SimpleConvolution test object - TestKernel* test_kernel = new SimpleConvolution(); - TestAql* test_aql = new TestHSA(test_kernel); - - const bool pmc_enable = (getenv("ROCR_ENABLE_PMC") != NULL); - const bool sqtt_enable = (getenv("ROCR_ENABLE_SQTT") != NULL); - if (pmc_enable) - test_aql = new TestPGenPMC(test_aql); - else if (sqtt_enable) - test_aql = new TestPGenSQTT(test_aql); - test_assert(test_aql != NULL); - if (test_aql == NULL) return 1; - - // Initialization of Hsa Runtime - ret_val = test_aql->initialize(argc, argv); - if (ret_val == false) { - std::cout << "Error in the test initialization" << std::endl; - test_assert(ret_val); - return 1; - } - - // Setup Hsa resources needed for execution - ret_val = test_aql->setup(); - if (ret_val == false) { - std::cout << "Error in creating hsa resources" << std::endl; - test_assert(ret_val); - return 1; - } - - // Run SimpleConvolution kernel - ret_val = test_aql->run(); - if (ret_val == false) { - std::cout << "Error in running the test kernel" << std::endl; - test_assert(ret_val); - return 1; - } - - // Verify the results of the execution - ret_val = test_aql->verify_results(); - if (ret_val) { - std::cout << "Test : Passed" << std::endl; - } else { - std::cout << "Test : Failed" << std::endl; - } - - // Print time taken by sample - test_aql->print_time(); - test_aql->cleanup(); - - return (ret_val) ? 0 : 1; -} diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_aql.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_aql.h deleted file mode 100644 index 4139734afc..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_aql.h +++ /dev/null @@ -1,78 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _TEST_AQL_H_ -#define _TEST_AQL_H_ - -#include "hsa.h" -#include "hsa_rsrc_factory.h" -#include "hsa_ven_amd_aqlprofile.h" - -// Test AQL interface -class TestAql { - TestAql* const test_aql; - - public: - explicit TestAql(TestAql* t = 0) : test_aql(t) {} - virtual ~TestAql() {} - - TestAql* testAql() { return test_aql; } - virtual AgentInfo* getAgentInfo() { return (test_aql) ? test_aql->getAgentInfo() : 0; } - virtual hsa_queue_t* getQueue() { return (test_aql) ? test_aql->getQueue() : 0; } - virtual HsaRsrcFactory* getRsrcFactory() { return (test_aql) ? test_aql->getRsrcFactory() : 0; } - - // Initialize application environment including setting - // up of various configuration parameters based on - // command line arguments - // @return bool true on success and false on failure - virtual bool initialize(int argc, char** argv) { - return (test_aql) ? test_aql->initialize(argc, argv) : true; - } - - // Setup application parameters for exectuion - // @return bool true on success and false on failure - virtual bool setup() { return (test_aql) ? test_aql->setup() : true; } - - // Run the kernel - // @return bool true on success and false on failure - virtual bool run() { return (test_aql) ? test_aql->run() : true; } - - // Verify results - // @return bool true on success and false on failure - virtual bool verify_results() { return (test_aql) ? test_aql->verify_results() : true; } - - // Print to console the time taken to execute kernel - virtual void print_time() { - if (test_aql) test_aql->print_time(); - } - - // Release resources e.g. memory allocations - // @return bool true on success and false on failure - virtual bool cleanup() { return (test_aql) ? test_aql->cleanup() : true; } -}; - -#endif // _TEST_AQL_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_assert.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_assert.h deleted file mode 100644 index 37d012720d..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_assert.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _TEST_ASSERT_H_ -#define _TEST_ASSERT_H_ - -#define test_assert(cond) \ - { \ - if (!(cond)) { \ - std::cout << "ASSERT FAILED(" << #cond << ") at \"" << __FILE__ << "\" line " << __LINE__ \ - << std::endl; \ - exit(-1); \ - } \ - } - -#endif // _TEST_ASSERT_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_hsa.cpp b/runtime/hsa-amd-aqlprofile/test/ctrl/test_hsa.cpp deleted file mode 100644 index 69bfca56ed..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_hsa.cpp +++ /dev/null @@ -1,237 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include "test_assert.h" -#include - -//#include "os.h" -#include "helper_funcs.h" -#include "hsa_rsrc_factory.h" -#include "test_hsa.h" - -bool TestHSA::initialize(int arg_cnt, char** arg_list) { - std::cout << "TestHSA::initialize :" << std::endl; - // Initialize command line arguments - hsa_cmdline_arg_cnt = arg_cnt; - hsa_cmdline_arg_list = arg_list; - - // Instantiate a Timer object - setup_timer_idx_ = hsa_timer_.CreateTimer(); - dispatch_timer_idx_ = hsa_timer_.CreateTimer(); - - // Instantiate an instance of Hsa Resources Factory - hsa_rsrc_ = new HsaRsrcFactory(); - - // Print properties of the agents - hsa_rsrc_->PrintGpuAgents("> GPU agents"); - - // Create an instance of Gpu agent - const char* p = getenv("ROCR_AGENT_IND"); - const uint32_t agent_ind = (p == NULL) ? 0 : atol(p); - if (!hsa_rsrc_->GetGpuAgentInfo(agent_ind, &agent_info_)) { - std::cout << "> error: agent[" << agent_ind << "] is not found" << std::endl; - return false; - } - std::cout << "> Using agent[" << agent_ind << "] : " << agent_info_->name << std::endl; - - // Create an instance of Aql Queue - uint32_t num_pkts = 128; - hsa_rsrc_->CreateQueue(agent_info_, num_pkts, &hsa_queue_); - - // Obtain handle of signal - hsa_rsrc_->CreateSignal(1, &hsa_signal_); - - // Obtain the code object file name - std::string agentName(agent_info_->name); - if (agentName.compare(0, 4, "gfx8") == 0) { - brig_path_obj_.append("gfx8"); - } else if (agentName.compare(0, 4, "gfx9") == 0) { - brig_path_obj_.append("gfx9"); - } else { - test_assert(false); - return false; - } - brig_path_obj_.append("_" + name_ + ".hsaco"); - - return true; -} - -bool TestHSA::setup() { - std::cout << "TestHSA::setup :" << std::endl; - - // Start the timer object - hsa_timer_.StartTimer(setup_timer_idx_); - - mem_map_t& mem_map = test_->get_mem_map(); - for (mem_it_t it = mem_map.begin(); it != mem_map.end(); ++it) { - mem_descr_t& des = it->second; - void* ptr = (des.local) ? hsa_rsrc_->AllocateLocalMemory(agent_info_, des.size) - : hsa_rsrc_->AllocateSysMemory(agent_info_, des.size); - des.ptr = ptr; - test_assert(ptr != NULL); - if (ptr == NULL) return false; - } - test_->init(); - - // Load and Finalize Kernel Code Descriptor - char* brig_path = (char*)brig_path_obj_.c_str(); - const bool ret_val = - hsa_rsrc_->LoadAndFinalize(agent_info_, brig_path, strdup(name_.c_str()), &kernel_code_desc_); - if (ret_val == false) { - std::cout << "Error in loading and finalizing Kernel" << std::endl; - return ret_val; - } - - // Stop the timer object - hsa_timer_.StopTimer(setup_timer_idx_); - setup_time_taken_ = hsa_timer_.ReadTimer(setup_timer_idx_); - total_time_taken_ = setup_time_taken_; - - return true; -} - -bool TestHSA::run() { - std::cout << "TestHSA::run :" << std::endl; - - const uint32_t work_group_size = 64; - const uint32_t work_grid_size = test_->get_elements_count(); - uint32_t group_segment_size = 0; - uint32_t private_segment_size = 0; - const size_t kernarg_segment_size = test_->get_kernarg_size(); - uint64_t code_handle = 0; - - // Retrieve the amount of group memory needed - hsa_executable_symbol_get_info( - kernel_code_desc_, HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE, &group_segment_size); - - // Retrieve the amount of private memory needed - hsa_executable_symbol_get_info(kernel_code_desc_, - HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE, - &private_segment_size); - - // Check the kernel args size - size_t size_info = 0; - hsa_executable_symbol_get_info( - kernel_code_desc_, HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE, &size_info); - test_assert(kernarg_segment_size == size_info); - if (kernarg_segment_size != size_info) return false; - - // Retrieve handle of the code block - hsa_executable_symbol_get_info(kernel_code_desc_, HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT, - &code_handle); - - // Initialize the dispatch packet. - hsa_kernel_dispatch_packet_t aql; - memset(&aql, 0, sizeof(aql)); - // Set the packet's type, barrier bit, acquire and release fences - aql.header = HSA_PACKET_TYPE_KERNEL_DISPATCH; - aql.header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE; - aql.header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE; - // Populate Aql packet with default values - aql.setup = 1; - aql.grid_size_x = work_grid_size; - aql.grid_size_y = 1; - aql.grid_size_z = 1; - aql.workgroup_size_x = work_group_size; - aql.workgroup_size_y = 1; - aql.workgroup_size_z = 1; - // Bind the kernel code descriptor and arguments - aql.kernel_object = code_handle; - aql.kernarg_address = test_->get_kernarg_ptr(); - aql.group_segment_size = group_segment_size; - aql.private_segment_size = private_segment_size; - // Initialize Aql packet with handle of signal - aql.completion_signal = hsa_signal_; - - // Compute the write index of queue and copy Aql packet into it - const uint64_t que_idx = hsa_queue_load_write_index_relaxed(hsa_queue_); - const uint32_t mask = hsa_queue_->size - 1; - - std::cout << "> Executing kernel: \"" << name_ << "\"" << std::endl; - - // Start the timer object - hsa_timer_.StartTimer(dispatch_timer_idx_); - - // Disable packet so that submission to HW is complete - const auto header = aql.header; - const uint8_t packet_type_mask = (1 << HSA_PACKET_HEADER_WIDTH_TYPE) - 1; - aql.header &= (~packet_type_mask) << HSA_PACKET_HEADER_TYPE; - aql.header |= HSA_PACKET_TYPE_INVALID << HSA_PACKET_HEADER_TYPE; - - // Copy Aql packet into queue buffer - ((hsa_kernel_dispatch_packet_t*)(hsa_queue_->base_address))[que_idx & mask] = aql; - - // After AQL packet is fully copied into queue buffer - // update packet header from invalid state to valid state - std::atomic_thread_fence(std::memory_order_release); - ((hsa_kernel_dispatch_packet_t*)(hsa_queue_->base_address))[que_idx & mask].header = header; - - // Increment the write index and ring the doorbell to dispatch the kernel. - hsa_queue_store_write_index_relaxed(hsa_queue_, (que_idx + 1)); - hsa_signal_store_relaxed(hsa_queue_->doorbell_signal, que_idx); - - std::cout << "> Waiting on kernel dispatch signal" << std::endl; - - // Wait on the dispatch signal until the kernel is finished. - // Update wait condition to HSA_WAIT_STATE_ACTIVE for Polling - hsa_signal_value_t value = hsa_signal_wait_acquire(hsa_signal_, HSA_SIGNAL_CONDITION_LT, 1, - (uint64_t)-1, HSA_WAIT_STATE_BLOCKED); - - // Stop the timer object - hsa_timer_.StopTimer(dispatch_timer_idx_); - dispatch_time_taken_ = hsa_timer_.ReadTimer(dispatch_timer_idx_); - total_time_taken_ += dispatch_time_taken_; - - // Copy kernel buffers from local memory into system memory - hsa_rsrc_->TransferData((uint8_t*)test_->get_output_ptr(), (uint8_t*)test_->get_local_ptr(), - test_->get_output_size(), false); - test_->print_output(); - - return true; -} - -bool TestHSA::verify_results() { - // Compare the results and see if they match - const int32_t cmp_val = - memcmp(test_->get_output_ptr(), test_->get_refout_ptr(), test_->get_output_size()); - return (cmp_val == 0); -} - -void TestHSA::print_time() { - std::cout << "Time taken for Setup by " << this->name_ << " : " << this->setup_time_taken_ - << std::endl; - std::cout << "Time taken for Dispatch by " << this->name_ << " : " << this->dispatch_time_taken_ - << std::endl; - std::cout << "Time taken in Total by " << this->name_ << " : " << this->total_time_taken_ - << std::endl; -} - -bool TestHSA::cleanup() { - // shutdown Hsa Runtime system - hsa_status_t ret_val = hsa_shut_down(); - return (HSA_STATUS_SUCCESS == ret_val); -} diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_hsa.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_hsa.h deleted file mode 100644 index 7ca894de40..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_hsa.h +++ /dev/null @@ -1,115 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _TEST_HSA_H_ -#define _TEST_HSA_H_ - -#include "test_aql.h" -#include "test_kernel.h" -#include "hsa_rsrc_factory.h" - -// Class implements HSA test -class TestHSA : public TestAql { - public: - // Constructor - explicit TestHSA(TestKernel* test) : test_(test), name_(test->Name()) { - total_time_taken_ = 0; - setup_time_taken_ = 0; - dispatch_time_taken_ = 0; - } - - // Get methods for Agent Info, HAS queue, HSA Resourcse Manager - AgentInfo* getAgentInfo() { return agent_info_; } - hsa_queue_t* getQueue() { return hsa_queue_; } - HsaRsrcFactory* getRsrcFactory() { return hsa_rsrc_; } - - // Initialize application environment including setting - // up of various configuration parameters based on - // command line arguments - // @return bool true on success and false on failure - bool initialize(int argc, char** argv); - - // Setup application parameters for exectuion - // @return bool true on success and false on failure - bool setup(); - - // Run the BinarySearch kernel - // @return bool true on success and false on failure - bool run(); - - // Verify against reference implementation - // @return bool true on success and false on failure - bool verify_results(); - - // Print to console the time taken to execute kernel - void print_time(); - - // Release resources e.g. memory allocations - // @return bool true on success and false on failure - bool cleanup(); - - private: - typedef TestKernel::mem_descr_t mem_descr_t; - typedef TestKernel::mem_map_t mem_map_t; - typedef TestKernel::mem_it_t mem_it_t; - - // Test object - TestKernel* test_; - - // Path of Brig file - std::string brig_path_obj_; - - // Used to track time taken to run the sample - double total_time_taken_; - double setup_time_taken_; - double dispatch_time_taken_; - - // Handle to an Hsa Gpu Agent - AgentInfo* agent_info_; - - // Handle to an Hsa Queue - hsa_queue_t* hsa_queue_; - - // Handle of signal - hsa_signal_t hsa_signal_; - - // Handle of Kernel Code Descriptor - hsa_executable_symbol_t kernel_code_desc_; - - // Instance of timer object - uint32_t setup_timer_idx_; - uint32_t dispatch_timer_idx_; - PerfTimer hsa_timer_; - - // Instance of Hsa Resources Factory - HsaRsrcFactory* hsa_rsrc_; - - // Test kernel name - std::string name_; -}; - -#endif // _TEST_HSA_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_kernel.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_kernel.h deleted file mode 100644 index 7af51e3c1f..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_kernel.h +++ /dev/null @@ -1,105 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _TEST_KERNEL_H_ -#define _TEST_KERNEL_H_ - -#include -#include - -// Class implements Kernel test -class TestKernel { - public: - // Memory descriptors IDs - enum { INPUT_DES_ID, OUTPUT_DES_ID, LOCAL_DES_ID, MASK_DES_ID, KERNARG_DES_ID, REFOUT_DES_ID }; - - // Memory descriptors vector declaration - struct mem_descr_t { - void* ptr; - uint32_t size; - bool local; - }; - - // Memory map declaration - typedef std::map mem_map_t; - typedef mem_map_t::iterator mem_it_t; - typedef mem_map_t::const_iterator mem_const_it_t; - - // Initialize method - virtual void init() = 0; - - // Return kernel memory map - mem_map_t& get_mem_map() { return mem_map_; } - - // Return NULL descriptor - static mem_descr_t null_descriptor() { return {0, 0, 0}; } - - // Methods to get the kernel attributes - void* get_kernarg_ptr() const { return get_descr(KERNARG_DES_ID).ptr; } - uint32_t get_kernarg_size() const { return get_descr(KERNARG_DES_ID).size; } - void* get_output_ptr() const { return get_descr(OUTPUT_DES_ID).ptr; } - uint32_t get_output_size() const { return get_descr(OUTPUT_DES_ID).size; } - void* get_local_ptr() const { return get_descr(LOCAL_DES_ID).ptr; } - void* get_refout_ptr() const { return get_descr(REFOUT_DES_ID).ptr; } - virtual uint32_t get_elements_count() const = 0; - - // Print output - virtual void print_output() const = 0; - - // Return name - virtual std::string Name() const = 0; - - protected: - // Set system memory descriptor - bool set_sys_descr(const uint32_t& id, const uint32_t& size) { - return set_mem_descr(id, size, false); - } - - // Set local memory descriptor - bool set_local_descr(const uint32_t& id, const uint32_t& size) { - return set_mem_descr(id, size, true); - } - - // Get memory descriptor - mem_descr_t get_descr(const uint32_t& id) const { - mem_const_it_t it = mem_map_.find(id); - return (it != mem_map_.end()) ? it->second : null_descriptor(); - } - - private: - // Set memory descriptor - bool set_mem_descr(const uint32_t& id, const uint32_t& size, const bool& local) { - const mem_descr_t des = {NULL, size, local}; - auto ret = mem_map_.insert(mem_map_t::value_type(id, des)); - return ret.second; - } - - // Kernel memory map object - mem_map_t mem_map_; -}; - -#endif // _TEST_KERNEL_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen.h deleted file mode 100644 index 662dbd2c2e..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen.h +++ /dev/null @@ -1,45 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _TEST_PGEN_H_ -#define _TEST_PGEN_H_ - -#include "test_pmgr.h" - -// SimpleConvolution: Class implements OpenCL SimpleConvolution sample -class TestPGen : public TestPMgr { - protected: - typedef hsa_ext_amd_aql_pm4_packet_t packet_t; - - packet_t* PrePacket() { return reinterpret_cast(&prePacket); } - packet_t* PostPacket() { return reinterpret_cast(&postPacket); } - - public: - explicit TestPGen(TestAql* t) : TestPMgr(t) {} -}; - -#endif // _TEST_PGEN_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen_pmc.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen_pmc.h deleted file mode 100644 index e62b5bb172..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen_pmc.h +++ /dev/null @@ -1,163 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _TEST_PGEN_PMC_H_ -#define _TEST_PGEN_PMC_H_ - -#include "test_assert.h" -#include "test_pgen.h" - -#include - -hsa_status_t TestPGenPMC_Callback(hsa_ven_amd_aqlprofile_info_type_t info_type, - hsa_ven_amd_aqlprofile_info_data_t* info_data, - void* callback_data) { - hsa_status_t status = HSA_STATUS_SUCCESS; - typedef std::vector passed_data_t; - reinterpret_cast(callback_data)->push_back(*info_data); - return status; -} - -// SimpleConvolution: Class implements OpenCL SimpleConvolution sample -class TestPGenPMC : public TestPGen { - const static uint32_t buffer_alignment = 0x1000; // 4K - - hsa_agent_t agent; - hsa_ven_amd_aqlprofile_profile_t profile; - hsa_ven_amd_aqlprofile_event_t* events; - - bool buildPackets() { return true; } - - bool dumpData() { - std::cout << "TestPGenPMC::dumpData :" << std::endl; - - typedef std::vector callback_data_t; - - callback_data_t data; - api.hsa_ven_amd_aqlprofile_iterate_data(&profile, TestPGenPMC_Callback, &data); - for (callback_data_t::iterator it = data.begin(); it != data.end(); ++it) { - std::cout << dec << "event( block(" << it->pmc_data.event.block_name << "_" - << it->pmc_data.event.block_index << "), id(" << it->pmc_data.event.counter_id - << ")), sample(" << it->sample_id << "), result(" << it->pmc_data.result << ")" - << std::endl; - } - - return true; - } - - public: - explicit TestPGenPMC(TestAql* t) : TestPGen(t) { std::cout << "Test: PGen PMC" << std::endl; } - - bool initialize(int arg_cnt, char** arg_list) { - if (!TestPMgr::initialize(arg_cnt, arg_list)) return false; - - hsa_status_t status; - hsa_agent_t agent; - uint32_t command_buffer_alignment; - uint32_t command_buffer_size; - uint32_t output_buffer_alignment; - uint32_t output_buffer_size; - - // GPU identificator - agent = getAgentInfo()->dev_id; - - // Instantiation of the profile object - // ////////////////////////////////////////////////////////////// - // Set the event fields - const hsa_ven_amd_aqlprofile_event_t events_arr[] = { - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 4 /*WAVES*/}, - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 14 /*ITEMS*/}, - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 47 /*WAVE_READY*/}, - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC, 2, 1 /*CYCLE*/}, - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC, 2, 3 /*REQ*/}, - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC, 2, 22 /*WRITEBACK*/}, - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC, 0, 0 /*ALWAYS_COUNT*/}, - {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC, 0, 8 /*ME1_STALL_WAIT_ON_RCIU_READ*/}, - }; - const size_t event_count = sizeof(events_arr) / sizeof(hsa_ven_amd_aqlprofile_event_t); - events = new hsa_ven_amd_aqlprofile_event_t[event_count]; - memcpy(events, events_arr, sizeof(events_arr)); - - // Initialization the profile - memset(&profile, 0, sizeof(profile)); - profile.agent = agent; - profile.type = HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC; - - // set enabled events list - profile.events = events; - profile.event_count = event_count; - - // Profile buffers attributes - command_buffer_alignment = buffer_alignment; - status = api.hsa_ven_amd_aqlprofile_get_info( - &profile, HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE, &command_buffer_size); - if (status != HSA_STATUS_SUCCESS) { - const char* str = ""; - api.hsa_ven_amd_aqlprofile_error_string(&str); - std::cout << "aqlprofile err: " << str << std::endl; - } - test_assert(status == HSA_STATUS_SUCCESS); - - output_buffer_alignment = buffer_alignment; - status = api.hsa_ven_amd_aqlprofile_get_info( - &profile, HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE, &output_buffer_size); - test_assert(status == HSA_STATUS_SUCCESS); - - // Application is allocating the command buffer - // Allocate(command_buffer_alignment, command_buffer_size, - // MODE_HOST_ACC|MODE_DEV_ACC|MODE_EXEC_DATA) - profile.command_buffer.ptr = - getRsrcFactory()->AllocateSysMemory(getAgentInfo(), command_buffer_size); - profile.command_buffer.size = command_buffer_size; - - // Application is allocating the output buffer - // Allocate(output_buffer_alignment, output_buffer_size, - // MODE_HOST_ACC|MODE_DEV_ACC) - profile.output_buffer.ptr = - getRsrcFactory()->AllocateSysMemory(getAgentInfo(), output_buffer_size); - profile.output_buffer.size = output_buffer_size; - memset(profile.output_buffer.ptr, 0x77, output_buffer_size); - - // Populating the AQL start packet - status = api.hsa_ven_amd_aqlprofile_start(&profile, PrePacket()); - if (status != HSA_STATUS_SUCCESS) { - const char* str; - api.hsa_ven_amd_aqlprofile_error_string(&str); - std::cout << "aqlprofile err: " << str << std::endl; - } - test_assert(status == HSA_STATUS_SUCCESS); - if (status != HSA_STATUS_SUCCESS) return false; - - // Populating the AQL stop packet - status = api.hsa_ven_amd_aqlprofile_stop(&profile, PostPacket()); - test_assert(status == HSA_STATUS_SUCCESS); - - return (status == HSA_STATUS_SUCCESS); - } -}; - -#endif // _TEST_PGEN_PMC_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen_sqtt.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen_sqtt.h deleted file mode 100644 index 88f603c468..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pgen_sqtt.h +++ /dev/null @@ -1,162 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _TEST_PGEN_SQTT_H_ -#define _TEST_PGEN_SQTT_H_ - -#include -#include -#include -#include - -#include "test_assert.h" -#include "test_pgen.h" - -hsa_status_t TestPGenSQTT_Callback(hsa_ven_amd_aqlprofile_info_type_t info_type, - hsa_ven_amd_aqlprofile_info_data_t* info_data, - void* callback_data) { - hsa_status_t status = HSA_STATUS_SUCCESS; - typedef std::vector passed_data_t; - reinterpret_cast(callback_data)->push_back(*info_data); - return status; -} - -// SimpleConvolution: Class implements OpenCL SimpleConvolution sample -class TestPGenSQTT : public TestPGen { - const static uint32_t buffer_alignment = 0x1000; // 4K - const static uint32_t buffer_size = 0x2000000; // 32M - - hsa_agent_t agent; - hsa_ven_amd_aqlprofile_profile_t profile; - - bool buildPackets() { return true; } - - bool dumpData() { - std::cout << "TestPGenSQTT::dumpData :" << std::endl; - - typedef std::vector callback_data_t; - - callback_data_t data; - api.hsa_ven_amd_aqlprofile_iterate_data(&profile, TestPGenSQTT_Callback, &data); - for (callback_data_t::iterator it = data.begin(); it != data.end(); ++it) { - std::cout << "> sample(" << dec << it->sample_id << ") ptr(" << hex << it->sqtt_data.ptr - << ") size(" << dec << it->sqtt_data.size << ")" << std::endl; - - void* sys_buf = getRsrcFactory()->AllocateSysMemory(getAgentInfo(), it->sqtt_data.size); - test_assert(sys_buf != NULL); - if (sys_buf == NULL) return HSA_STATUS_ERROR; - - hsa_status_t status = hsa_memory_copy(sys_buf, it->sqtt_data.ptr, it->sqtt_data.size); - test_assert(status == HSA_STATUS_SUCCESS); - if (status != HSA_STATUS_SUCCESS) return status; - - std::string file_name; - file_name.append("sqtt_dump_"); - file_name.append(std::to_string(it->sample_id)); - file_name.append(".txt"); - std::ofstream out_file; - out_file.open(file_name); - - // Write the buffer in terms of shorts (16 bits) - short* sqtt_data = (short*)sys_buf; - for (int i = 0; i < (it->sqtt_data.size / sizeof(short)); ++i) { - out_file << std::setw(4) << std::setfill('0') << std::hex << sqtt_data[i] << "\n"; - } - - out_file.close(); - } - - return true; - } - - public: - explicit TestPGenSQTT(TestAql* t) : TestPGen(t) { std::cout << "Test: PGen SQTT" << std::endl; } - - bool initialize(int arg_cnt, char** arg_list) { - if (!TestPMgr::initialize(arg_cnt, arg_list)) return false; - - hsa_status_t status; - hsa_agent_t agent; - uint32_t command_buffer_alignment; - uint32_t command_buffer_size; - uint32_t output_buffer_alignment; - uint32_t output_buffer_size; - - // GPU identificator - agent = getAgentInfo()->dev_id; - - // Instantiation of the profile object - // ////////////////////////////////////////////////////////////// - // Set the parameters - // parameters = ....; - - // Initialization the profile - memset(&profile, 0, sizeof(profile)); - profile.agent = agent; - profile.type = HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_SQTT; - - // set parameters - // profile.parameters = &event; - // profile.parameter_count = 1; - - // Profile buffers attributes - command_buffer_alignment = buffer_alignment; - status = api.hsa_ven_amd_aqlprofile_get_info( - &profile, HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE, &command_buffer_size); - test_assert(status == HSA_STATUS_SUCCESS); - - output_buffer_alignment = buffer_alignment; - output_buffer_size = buffer_size; - - // Application is allocating the command buffer - // AllocateSystem(command_buffer_alignment, command_buffer_size, - // MODE_HOST_ACC|MODE_DEV_ACC|MODE_EXEC_DATA) - profile.command_buffer.ptr = - getRsrcFactory()->AllocateSysMemory(getAgentInfo(), command_buffer_size); - profile.command_buffer.size = command_buffer_size; - - // Application is allocating the output buffer - // AllocateLocal(output_buffer_alignment, output_buffer_size, - // MODE_DEV_ACC) - profile.output_buffer.ptr = - getRsrcFactory()->AllocateLocalMemory(getAgentInfo(), output_buffer_size); - profile.output_buffer.size = output_buffer_size; - - // Populating the AQL start packet - status = api.hsa_ven_amd_aqlprofile_start(&profile, PrePacket()); - test_assert(status == HSA_STATUS_SUCCESS); - if (status != HSA_STATUS_SUCCESS) return false; - - // Populating the AQL stop packet - status = api.hsa_ven_amd_aqlprofile_stop(&profile, PostPacket()); - test_assert(status == HSA_STATUS_SUCCESS); - - return (status == HSA_STATUS_SUCCESS); - } -}; - -#endif // _TEST_PGEN_SQTT_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pmgr.cpp b/runtime/hsa-amd-aqlprofile/test/ctrl/test_pmgr.cpp deleted file mode 100644 index 3f95b449c0..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pmgr.cpp +++ /dev/null @@ -1,130 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include -#include "test_assert.h" - -#include "test_pmgr.h" - -bool TestPMgr::addPacketGfx9(const packet_t* packet) { - packet_t aql_packet = *packet; - - // Compute the write index of queue and copy Aql packet into it - uint64_t que_idx = hsa_queue_load_write_index_relaxed(getQueue()); - const uint32_t mask = getQueue()->size - 1; - - // Disable packet so that submission to HW is complete - const auto header = HSA_PACKET_TYPE_VENDOR_SPECIFIC << HSA_PACKET_HEADER_TYPE; - aql_packet.header &= (~((1 << HSA_PACKET_HEADER_WIDTH_TYPE) - 1)) << HSA_PACKET_HEADER_TYPE; - aql_packet.header |= HSA_PACKET_TYPE_INVALID << HSA_PACKET_HEADER_TYPE; - - // Copy Aql packet into queue buffer - ((packet_t*)(getQueue()->base_address))[que_idx & mask] = aql_packet; - - // After AQL packet is fully copied into queue buffer - // update packet header from invalid state to valid state - std::atomic_thread_fence(std::memory_order_release); - ((packet_t*)(getQueue()->base_address))[que_idx & mask].header = header; - - // Increment the write index and ring the doorbell to dispatch the kernel. - hsa_queue_store_write_index_relaxed(getQueue(), (que_idx + 1)); - hsa_signal_store_relaxed(getQueue()->doorbell_signal, que_idx); - - return true; -} - -bool TestPMgr::addPacketGfx8(const packet_t* packet) { - // Create legacy devices PM4 data - const hsa_ext_amd_aql_pm4_packet_t* aql_packet = (const hsa_ext_amd_aql_pm4_packet_t*)packet; - slot_pm4_s data; - api.hsa_ven_amd_aqlprofile_legacy_get_pm4(aql_packet, reinterpret_cast(data.words)); - - // Compute the write index of queue and copy Aql packet into it - uint64_t que_idx = hsa_queue_load_write_index_relaxed(getQueue()); - const uint32_t mask = getQueue()->size - 1; - - // Copy Aql packet into queue buffer - packet_t* ptr = ((packet_t*)(getQueue()->base_address)) + (que_idx & mask); - slot_pm4_t* slot_pm4 = (slot_pm4_t*)ptr; - slot_pm4->store(data, std::memory_order_relaxed); - - // Increment the write index and ring the doorbell to dispatch the kernel. - hsa_queue_store_write_index_relaxed(getQueue(), (que_idx + SLOT_PM4_SIZE_AQLP)); - hsa_signal_store_relaxed(getQueue()->doorbell_signal, que_idx + SLOT_PM4_SIZE_AQLP - 1); - - return true; -} - -bool TestPMgr::addPacket(const packet_t* packet) { - const char* agent_name = getAgentInfo()->name; - return (strncmp(agent_name, "gfx8", 4) == 0) ? addPacketGfx8(packet) : addPacketGfx9(packet); -} - -bool TestPMgr::run() { - // Build Aql Pkts - const bool active = buildPackets(); - if (active) { - // Submit Pre-Dispatch Aql packet - addPacket(&prePacket); - } - - testAql()->run(); - - if (active) { - // Set post packet completion signal - postPacket.completion_signal = postSignal; - - // Submit Post-Dispatch Aql packet - addPacket(&postPacket); - - // Wait for Post-Dispatch packet to complete - hsa_signal_wait_acquire(postSignal, HSA_SIGNAL_CONDITION_LT, 1, (uint64_t)-1, - HSA_WAIT_STATE_BLOCKED); - - // Dumping profiling data - dumpData(); - } - - return true; -} - -bool TestPMgr::initialize(int argc, char** argv) { - TestAql::initialize(argc, argv); - hsa_status_t status = hsa_signal_create(1, 0, NULL, &postSignal); - test_assert(status == HSA_STATUS_SUCCESS); - return (status == HSA_STATUS_SUCCESS); -} - -TestPMgr::TestPMgr(TestAql* t) : TestAql(t) { - dummySignal.handle = 0; - postSignal = dummySignal; - - hsa_status_t status = hsa_init(); - test_assert(status == HSA_STATUS_SUCCESS); - status = hsa_system_get_extension_table(HSA_EXTENSION_AMD_AQLPROFILE, 1, 0, &api); - test_assert(status == HSA_STATUS_SUCCESS); -} diff --git a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pmgr.h b/runtime/hsa-amd-aqlprofile/test/ctrl/test_pmgr.h deleted file mode 100644 index c74f1fd2eb..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/ctrl/test_pmgr.h +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _TEST_PMGR_H_ -#define _TEST_PMGR_H_ - -#include - -#include "hsa.h" -#include "test_aql.h" -#include "hsa_ven_amd_aqlprofile.h" - -// SimpleConvolution: Class implements OpenCL SimpleConvolution sample -class TestPMgr : public TestAql { - public: - typedef hsa_ext_amd_aql_pm4_packet_t packet_t; - explicit TestPMgr(TestAql* t); - bool run(); - - protected: - packet_t prePacket; - packet_t postPacket; - hsa_signal_t dummySignal; - hsa_signal_t postSignal; - - hsa_ven_amd_aqlprofile_1_00_pfn_t api; - - virtual bool buildPackets() { return false; } - virtual bool dumpData() { return false; } - virtual bool initialize(int argc, char** argv); - - private: - enum { - SLOT_PM4_SIZE_DW = HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE / sizeof(uint32_t), - SLOT_PM4_SIZE_AQLP = HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE / sizeof(packet_t) - }; - struct slot_pm4_s { - uint32_t words[SLOT_PM4_SIZE_DW]; - }; - typedef std::atomic slot_pm4_t; - - bool addPacket(const packet_t* packet); - bool addPacketGfx8(const packet_t* packet); - bool addPacketGfx9(const packet_t* packet); -}; - -#endif // _TEST_PMGR_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/run.sh b/runtime/hsa-amd-aqlprofile/test/run.sh deleted file mode 100755 index 54ead87204..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/run.sh +++ /dev/null @@ -1,30 +0,0 @@ -#/bin/sh -set -x - -tbin=./test/ctrl - -CDIR=`pwd` -export LD_LIBRARY_PATH=$CDIR - -export HSA_ENABLE_SDMA=0 -export HSA_EMULATE_AQL=1 - -echo -echo "Run simple convolution kernel" -unset ROCR_ENABLE_PMC -unset ROCR_ENABLE_SQTT -eval $tbin - -echo -echo "Run with PMC" -export ROCR_ENABLE_PMC=1 -unset ROCR_ENABLE_SQTT -eval $tbin - -echo -echo "Run with SQTT" -unset ROCR_ENABLE_PMC -export ROCR_ENABLE_SQTT=1 -eval $tbin - - diff --git a/runtime/hsa-amd-aqlprofile/test/simple_convolution/gfx8_simpleConvolution.hsaco b/runtime/hsa-amd-aqlprofile/test/simple_convolution/gfx8_simpleConvolution.hsaco deleted file mode 100644 index 0a865581e06386b1898c5601c775d972dfdbfb24..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9392 zcmeHN?N1a(7@wWn+dKA-1(8x}Yh6=Yn+7h&dYnkw1O%l-P<&6*G_t}9r}skd#Ymf5 z7kmK|qsAKJztE&f{{z6UZPEbkhko#bU;5p@0Qx*TGk3QKO$WbaueT26Fc}^r8H#0^bBjm+iJ^<23dPo@h2x%Y+%w?Cy26=4<9sTpu%p2LJ9c7yr+zC= zx~b^gaUC7!Y!L_Z!*&wv+<0vImwSxm#>0fM)zJiZDkz7^wZWV*e*fs8YldT#zYU)N z=gTAnd(N8Rf&S3gS*H6OHU;JAqqDP9{aQCOld;jkb5_2P%4K`?&vm0i@6x~Ma0SB! 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All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -********************************************************************************/ - -/** - * SimpleConvolution is where each pixel of the output image - * is the weighted sum of the neighborhood pixels of the input image - * The neighborhood is defined by the dimensions of the mask and - * weight of each neighbor is defined by the mask itself. - * @param output Output matrix after performing convolution - * @param input Input matrix on which convolution is to be performed - * @param mask mask matrix using which convolution was to be performed - * @param inputDimensions dimensions of the input matrix - * @param maskDimensions dimensions of the mask matrix - */ -__kernel void simpleConvolution(__global uint * output, - __global uint * input, - __global float * mask, - const uint2 inputDimensions, - const uint2 maskDimensions) { - - uint tid = get_global_id(0); - - uint width = inputDimensions.x; - uint height = inputDimensions.y; - - uint x = tid%width; - uint y = tid/width; - - uint maskWidth = maskDimensions.x; - uint maskHeight = maskDimensions.y; - - uint vstep = (maskWidth -1)/2; - uint hstep = (maskHeight -1)/2; - - // find the left, right, top and bottom indices such that - // the indices do not go beyond image boundaires - uint left = (x < vstep) ? 0 : (x - vstep); - uint right = ((x + vstep) >= width) ? width - 1 : (x + vstep); - uint top = (y < hstep) ? 0 : (y - hstep); - uint bottom = ((y + hstep) >= height)? height - 1: (y + hstep); - - // initializing wighted sum value - float sumFX = 0; - - for(uint i = left; i <= right; ++i) { - for(uint j = top ; j <= bottom; ++j) { - // performing wighted sum within the mask boundaries - uint maskIndex = (j - (y - hstep)) * maskWidth + (i - (x - vstep)); - uint index = j * width + i; - sumFX += ((float)input[index] * mask[maskIndex]); - } - } - - // To round to the nearest integer - sumFX += 0.5f; - output[tid] = (uint)sumFX; -} diff --git a/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.cpp b/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.cpp deleted file mode 100644 index 86d795fbd2..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.cpp +++ /dev/null @@ -1,160 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include -#include - -#include "helper_funcs.h" -#include "simple_convolution.h" - -SimpleConvolution::SimpleConvolution() { - width_ = 64; - height_ = 64; - mask_width_ = 3; - mask_height_ = mask_width_; - - if (!isPowerOf2(width_)) { - width_ = roundToPowerOf2(width_); - } - - if (!isPowerOf2(height_)) { - height_ = roundToPowerOf2(height_); - } - - if (!(mask_width_ % 2)) { - mask_width_++; - } - - if (!(mask_height_ % 2)) { - mask_height_++; - } - - if (width_ * height_ < 256) { - width_ = 64; - height_ = 64; - } - - const uint32_t input_size_bytes = width_ * height_ * sizeof(uint32_t); - const uint32_t mask_size_bytes = mask_width_ * mask_height_ * sizeof(float); - - set_sys_descr(KERNARG_DES_ID, sizeof(kernel_args_t)); - set_sys_descr(INPUT_DES_ID, input_size_bytes); - set_sys_descr(OUTPUT_DES_ID, input_size_bytes); - set_local_descr(LOCAL_DES_ID, input_size_bytes); - set_sys_descr(MASK_DES_ID, mask_size_bytes); - set_sys_descr(REFOUT_DES_ID, input_size_bytes); -} - -void SimpleConvolution::init() { - std::cout << "SimpleConvolution::init :" << std::endl; - - mem_descr_t input_des = get_descr(INPUT_DES_ID); - mem_descr_t local_des = get_descr(LOCAL_DES_ID); - mem_descr_t mask_des = get_descr(MASK_DES_ID); - mem_descr_t refout_des = get_descr(REFOUT_DES_ID); - mem_descr_t kernarg_des = get_descr(KERNARG_DES_ID); - - uint32_t* input = (uint32_t*)input_des.ptr; - uint32_t* output_local = (uint32_t*)local_des.ptr; - float* mask = (float*)mask_des.ptr; - kernel_args_t* kernel_args = (kernel_args_t*)kernarg_des.ptr; - - // random initialisation of input - fillRandom(input, width_, height_, 0, 255); - - // Fill a blurr filter or some other filter of your choice - const float val = 1.0f / (mask_width_ * 2.0f - 1.0f); - for (uint32_t i = 0; i < (mask_width_ * mask_height_); i++) { - mask[i] = 0; - } - for (uint32_t i = 0; i < mask_width_; i++) { - uint32_t y = mask_height_ / 2; - mask[y * mask_width_ + i] = val; - } - for (uint32_t i = 0; i < mask_height_; i++) { - uint32_t x = mask_width_ / 2; - mask[i * mask_width_ + x] = val; - } - - // Print the INPUT array. - printArray("> Input[0]", input, width_, 1); - printArray("> Mask", mask, mask_width_, mask_height_); - - // Fill the kernel args - kernel_args->arg1 = output_local; - kernel_args->arg2 = input; - kernel_args->arg3 = mask; - kernel_args->arg4 = width_; - kernel_args->arg41 = height_; - kernel_args->arg5 = mask_width_; - kernel_args->arg51 = mask_height_; - - // Calculate the reference output - memset(refout_des.ptr, 0, refout_des.size); - reference_impl((uint32_t*)refout_des.ptr, input, mask, width_, height_, mask_width_, - mask_height_); -} - -void SimpleConvolution::print_output() const { - printArray("> Output[0]", (uint32_t*)get_output_ptr(), width_, 1); -} - -bool SimpleConvolution::reference_impl(uint32_t* output, const uint32_t* input, const float* mask, - const uint32_t width, const uint32_t height, - const uint32_t mask_width, const uint32_t mask_height) { - const uint32_t vstep = (mask_width - 1) / 2; - const uint32_t hstep = (mask_height - 1) / 2; - - // for each pixel in the input - for (uint32_t x = 0; x < width; x++) { - for (uint32_t y = 0; y < height; y++) { - // find the left, right, top and bottom indices such that - // the indices do not go beyond image boundaires - const uint32_t left = (x < vstep) ? 0 : (x - vstep); - const uint32_t right = ((x + vstep) >= width) ? width - 1 : (x + vstep); - const uint32_t top = (y < hstep) ? 0 : (y - hstep); - const uint32_t bottom = ((y + hstep) >= height) ? height - 1 : (y + hstep); - - // initializing wighted sum value - float sum_fx = 0; - for (uint32_t i = left; i <= right; ++i) { - for (uint32_t j = top; j <= bottom; ++j) { - // performing wighted sum within the mask boundaries - uint32_t mask_idx = (j - (y - hstep)) * mask_width + (i - (x - vstep)); - uint32_t index = j * width + i; - - // to round to the nearest integer - sum_fx += ((float)input[index] * mask[mask_idx]); - } - } - sum_fx += 0.5f; - output[y * width + x] = uint32_t(sum_fx); - } - } - - return true; -} diff --git a/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.h b/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.h deleted file mode 100644 index 27f3271428..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.h +++ /dev/null @@ -1,90 +0,0 @@ -/****************************************************************************** - -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef _SIMPLE_CONVOLUTION_H_ -#define _SIMPLE_CONVOLUTION_H_ - -#include -#include - -#include "test_kernel.h" - -// SimpleConvolution: Class implements OpenCL SimpleConvolution sample -class SimpleConvolution : public TestKernel { - public: - // Constructor - SimpleConvolution(); - - // Initialize method - void init(); - - // Return number of compute elements - uint32_t get_elements_count() const { return width_ * height_; } - - // Print output - void print_output() const; - - // Return name - std::string Name() const { return std::string("simpleConvolution"); } - - private: - // Local kernel arguments declaration - struct kernel_args_t { - void* arg1; - void* arg2; - void* arg3; - uint32_t arg4; - uint32_t arg41; - uint32_t arg5; - uint32_t arg51; - }; - - // Width of the Input array - uint32_t width_; - - // Height of the Input array - uint32_t height_; - - // Mask dimensions - uint32_t mask_width_; - - // Mask dimensions - uint32_t mask_height_; - - // Reference CPU implementation of Simple Convolution - // @param output Output matrix after performing convolution - // @param input Input matrix on which convolution is to be performed - // @param mask mask matrix using which convolution was to be performed - // @param input_dimensions dimensions of the input matrix - // @param mask_dimensions dimensions of the mask matrix - // @return bool true on success and false on failure - bool reference_impl(uint32_t* output, const uint32_t* input, const float* mask, - const uint32_t width, const uint32_t height, const uint32_t maskWidth, - const uint32_t maskHeight); -}; - -#endif // _SIMPLE_CONVOLUTION_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.hsail b/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.hsail deleted file mode 100644 index 223ef8eddb..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/simple_convolution/simple_convolution.hsail +++ /dev/null @@ -1,154 +0,0 @@ -module &m:1:0:$full:$large:$default; -extension "amd:gcn"; -extension "IMAGE"; - -decl prog function &abort()(); - -prog kernel &__OpenCL_SimpleConvolution(kernarg_u64 %__global_offset_0, - kernarg_u64 %output, - kernarg_u64 %input, - kernarg_u64 %mask, - kernarg_u32 %inputDimensions[2], - kernarg_u32 %maskDimensions[2]) { - - pragma "AMD RTI", "ARGSTART:__OpenCL_SimpleConvolution"; - pragma "AMD RTI", "version:3:1:104"; - pragma "AMD RTI", "device:generic"; - pragma "AMD RTI", "uniqueid:1024"; - pragma "AMD RTI", "memory:private:0"; - pragma "AMD RTI", "memory:region:0"; - pragma "AMD RTI", "memory:local:0"; - pragma "AMD RTI", "value:__global_offset_0:u64:1:1:0"; - pragma "AMD RTI", "pointer:output:u32:1:1:96:uav:7:4:RW:0:0:0"; - pragma "AMD RTI", "pointer:input:u32:1:1:112:uav:7:4:RW:0:0:0"; - pragma "AMD RTI", "pointer:mask:float:1:1:128:uav:7:4:RW:0:0:0"; - pragma "AMD RTI", "value:inputDimensions:u32:2:1:144"; - pragma "AMD RTI", "constarg:4:inputDimensions"; - pragma "AMD RTI", "value:maskDimensions:u32:2:1:160"; - pragma "AMD RTI", "constarg:5:maskDimensions"; - pragma "AMD RTI", "function:1:0"; - pragma "AMD RTI", "memory:64bitABI"; - pragma "AMD RTI", "privateid:8"; - pragma "AMD RTI", "enqueue_kernel:0"; - pragma "AMD RTI", "kernel_index:0"; - pragma "AMD RTI", "reflection:0:size_t"; - pragma "AMD RTI", "reflection:1:uint*"; - pragma "AMD RTI", "reflection:2:uint*"; - pragma "AMD RTI", "reflection:3:float*"; - pragma "AMD RTI", "reflection:4:uint2"; - pragma "AMD RTI", "reflection:5:uint2"; - pragma "AMD RTI", "ARGEND:__OpenCL_SimpleConvolution"; - - @__OpenCL_SimpleConvolution_Entry: - - // BB#0: // %entry - - workitemabsid_u32 $s6, 0; - cvt_u64_u32 $d0, $s6; - ld_kernarg_align(8)_width(all)_u64 $d4, [%__global_offset_0]; - add_u64 $d0, $d0, $d4; - cvt_u32_u64 $s5, $d0; - ld_v2_kernarg_align(4)_width(all)_u32 ($s0, $s4), [%inputDimensions]; - ld_v2_kernarg_align(4)_width(all)_u32 ($s1, $s9), [%maskDimensions]; - rem_u32 $s7, $s5, $s0; - add_u32 $s2, $s1, 4294967295; - shr_u32 $s8, $s2, 1; - add_u32 $s2, $s7, $s8; - add_u32 $s3, $s0, 4294967295; - cmp_ge_b1_u32 $c0, $s2, $s0; - cmov_b32 $s2, $c0, $s3, $s2; - sub_u32 $s3, $s7, $s8; - cmp_lt_b1_u32 $c0, $s7, $s8; - cmov_b32 $s3, $c0, 0, $s3; - ld_kernarg_align(8)_width(all)_u64 $d1, [%output]; - cmp_le_b1_u32 $c0, $s3, $s2; - cbr_b1 $c0, @BB0_2; - - // BB#1: - - mov_b32 $s6, 0; - br @BB0_6; - - // @BB0_2: // %for.cond32.preheader.lr.ph - - @BB0_2: - - div_u32 $s5, $s5, $s0; - add_u32 $s9, $s9, 4294967295; - shr_u32 $s9, $s9, 1; - add_u32 $s10, $s5, $s9; - add_u32 $s11, $s4, 4294967295; - cmp_ge_b1_u32 $c0, $s10, $s4; - cmov_b32 $s4, $c0, $s11, $s10; - sub_u32 $s10, $s5, $s9; - cmp_lt_b1_u32 $c0, $s5, $s9; - cmov_b32 $s5, $c0, 0, $s10; - ld_kernarg_align(8)_width(all)_u64 $d2, [%mask]; - ld_kernarg_align(8)_width(all)_u64 $d3, [%input]; - cvt_u64_u32 $d5, $s6; - add_u64 $d4, $d4, $d5; - cvt_u32_u64 $s6, $d4; - div_u32 $s6, $s6, $s0; - max_u32 $s10, $s9, $s6; - sub_u32 $s12, $s10, $s6; - max_u32 $s11, $s7, $s8; - mov_b32 $s6, 0; - mad_u32 $s12, $s1, $s12, $s11; - sub_u32 $s7, $s12, $s7; - sub_u32 $s9, $s10, $s9; - mad_u32 $s9, $s0, $s9, $s11; - sub_u32 $s8, $s9, $s8; - - // @BB0_3: // %for.cond32.preheader - - @BB0_3: - - cmp_gt_b1_u32 $c0, $s5, $s4; - mov_b32 $s9, $s7; - mov_b32 $s10, $s8; - mov_b32 $s11, $s5; - cbr_b1 $c0, @BB0_5; - - // @BB0_4: // %for.body35 - - @BB0_4: - - cvt_u64_u32 $d4, $s9; - shl_u64 $d4, $d4, 2; - add_u64 $d4, $d2, $d4; - ld_global_align(4)_f32 $s12, [$d4]; - cvt_u64_u32 $d4, $s10; - shl_u64 $d4, $d4, 2; - add_u64 $d4, $d3, $d4; - ld_global_align(4)_u32 $s13, [$d4]; - cvt_f32_u32 $s13, $s13; - mul_ftz_f32 $s12, $s13, $s12; - add_u32 $s9, $s9, $s1; - add_u32 $s10, $s10, $s0; - add_u32 $s11, $s11, 1; - add_ftz_f32 $s6, $s6, $s12; - cmp_le_b1_u32 $c0, $s11, $s4; - cbr_b1 $c0, @BB0_4; - - // @BB0_5: // %for.inc48 - - @BB0_5: - - add_u32 $s7, $s7, 1; - add_u32 $s8, $s8, 1; - add_u32 $s3, $s3, 1; - cmp_le_b1_u32 $c0, $s3, $s2; - cbr_b1 $c0, @BB0_3; - - // @BB0_6: // %for.end50 - - @BB0_6: - - and_b64 $d0, $d0, 4294967295; - shl_u64 $d0, $d0, 2; - add_u64 $d0, $d1, $d0; - add_ftz_f32 $s0, $s6, 0F3f000000; - cvt_ftz_u32_f32 $s0, $s0; - st_global_align(4)_u32 $s0, [$d0]; - ret; -}; diff --git a/runtime/hsa-amd-aqlprofile/test/util/CMakeLists.txt b/runtime/hsa-amd-aqlprofile/test/util/CMakeLists.txt deleted file mode 100644 index 920ae8fb73..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/util/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# -# Source files for Rocr Utils library -# -file( GLOB MODULE_SRC "*.cpp" ) - -# -# Header files include path(s). -# -include_directories ( $ENV{ROCR_INC_DIR} ) - -# -# Build Utils as a Static Library object -# -add_library( ${UTIL_LIB} STATIC ${MODULE_SRC} ) -target_link_libraries( ${UTIL_LIB} c stdc++ dl pthread rt ) diff --git a/runtime/hsa-amd-aqlprofile/test/util/helper_funcs.cpp b/runtime/hsa-amd-aqlprofile/test/util/helper_funcs.cpp deleted file mode 100644 index 83a9d0504f..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/util/helper_funcs.cpp +++ /dev/null @@ -1,230 +0,0 @@ -/********************************************************************** -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, are permitted -provided that the following conditions are met: - -• Redistributions of source code must retain the above copyright notice, this list of -conditions and the following disclaimer. -• Redistributions in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. -********************************************************************/ - -#include -#include -#include -#include -#include - -#include "helper_funcs.h" - -#ifndef _WIN32 -#include -#endif - -void error(std::string errorMsg) { std::cout << "Error: " << errorMsg << std::endl; } - -/* - * Prints no more than 256 elements of the given array. - * Prints full array if length is less than 256. - * Prints Array name followed by elements. - */ -template -void printArray(const std::string header, const T* data, const int width, const int height) { - std::cout << header << " :\n"; - for (int i = 0; i < height; i++) { - std::cout << "> "; - for (int j = 0; j < width; j++) { - std::cout << data[i * width + j] << " "; - } - std::cout << "\n"; - } -} - -template -bool fillRandom(T* arrayPtr, const int width, const int height, const T rangeMin, const T rangeMax, - unsigned int seed) { - if (!arrayPtr) { - error("Cannot fill array. NULL pointer."); - return false; - } - - if (!seed) seed = (unsigned int)time(NULL); - - srand(seed); - double range = double(rangeMax - rangeMin) + 1.0; - - /* random initialisation of input */ - for (int i = 0; i < height; i++) - for (int j = 0; j < width; j++) { - int index = i * width + j; - arrayPtr[index] = rangeMin + T(range * rand() / (RAND_MAX + 1.0)); - } - - return true; -} - -template bool fillPos(T* arrayPtr, const int width, const int height) { - if (!arrayPtr) { - error("Cannot fill array. NULL pointer."); - return false; - } - - /* initialisation of input with positions*/ - for (T i = 0; i < height; i++) - for (T j = 0; j < width; j++) { - T index = i * width + j; - arrayPtr[index] = index; - } - - return true; -} - -template -bool fillConstant(T* arrayPtr, const int width, const int height, const T val) { - if (!arrayPtr) { - error("Cannot fill array. NULL pointer."); - return false; - } - - /* initialisation of input with constant value*/ - for (int i = 0; i < height; i++) - for (int j = 0; j < width; j++) { - int index = i * width + j; - arrayPtr[index] = val; - } - - return true; -} - -template T roundToPowerOf2(T val) { - int bytes = sizeof(T); - - val--; - for (int i = 0; i < bytes; i++) val |= val >> (1 << i); - val++; - - return val; -} - -template bool isPowerOf2(T val) { - long long _val = val; - return (((_val & (-_val)) - _val == 0) && (_val != 0)); -} - -template std::string toString(T t, std::ios_base& (*r)(std::ios_base&)) { - std::ostringstream output; - output << r << t; - return output.str(); -} - -bool compare(const float* refData, const float* data, const int length, const float epsilon) { - float error = 0.0f; - float ref = 0.0f; - - for (int i = 1; i < length; ++i) { - float diff = refData[i] - data[i]; - error += diff * diff; - ref += refData[i] * refData[i]; - } - - float normRef = ::sqrtf((float)ref); - if (::fabs((float)ref) < 1e-7f) { - return false; - } - float normError = ::sqrtf((float)error); - error = normError / normRef; - - return error < epsilon; -} - -bool compare(const double* refData, const double* data, const int length, const double epsilon) { - double error = 0.0; - double ref = 0.0; - - for (int i = 1; i < length; ++i) { - double diff = refData[i] - data[i]; - error += diff * diff; - ref += refData[i] * refData[i]; - } - - double normRef = ::sqrt((double)ref); - if (::fabs((double)ref) < 1e-7) { - return false; - } - double normError = ::sqrt((double)error); - error = normError / normRef; - - return error < epsilon; -} - -///////////////////////////////////////////////////////////////// -// Template Instantiations -///////////////////////////////////////////////////////////////// -template void printArray(const std::string, const short*, int, int); -template void printArray(const std::string, const unsigned char*, int, int); -template void printArray(const std::string, const unsigned int*, int, int); -template void printArray(const std::string, const int*, int, int); -template void printArray(const std::string, const long*, int, int); -template void printArray(const std::string, const float*, int, int); -template void printArray(const std::string, const double*, int, int); - -template bool fillRandom(unsigned char* arrayPtr, const int width, const int height, - unsigned char rangeMin, unsigned char rangeMax, - unsigned int seed); -template bool fillRandom(unsigned int* arrayPtr, const int width, const int height, - unsigned int rangeMin, unsigned int rangeMax, - unsigned int seed); -template bool fillRandom(int* arrayPtr, const int width, const int height, int rangeMin, - int rangeMax, unsigned int seed); -template bool fillRandom(long* arrayPtr, const int width, const int height, long rangeMin, - long rangeMax, unsigned int seed); -template bool fillRandom(float* arrayPtr, const int width, const int height, float rangeMin, - float rangeMax, unsigned int seed); -template bool fillRandom(double* arrayPtr, const int width, const int height, - double rangeMin, double rangeMax, unsigned int seed); - -template short roundToPowerOf2(short val); -template unsigned int roundToPowerOf2(unsigned int val); -template int roundToPowerOf2(int val); -template long roundToPowerOf2(long val); - -template bool isPowerOf2(short val); -template bool isPowerOf2(unsigned int val); -template bool isPowerOf2(int val); -template bool isPowerOf2(long val); - -template <> bool fillPos(short* arrayPtr, const int width, const int height); -template <> bool fillPos(unsigned int* arrayPtr, const int width, const int height); -template <> bool fillPos(int* arrayPtr, const int width, const int height); -template <> bool fillPos(long* arrayPtr, const int width, const int height); - -template <> -bool fillConstant(short* arrayPtr, const int width, const int height, const short val); -template <> -bool fillConstant(unsigned int* arrayPtr, const int width, const int height, - const unsigned int val); -template <> bool fillConstant(int* arrayPtr, const int width, const int height, const int val); -template <> bool fillConstant(long* arrayPtr, const int width, const int height, const long val); -template <> bool fillConstant(long* arrayPtr, const int width, const int height, const long val); -template <> bool fillConstant(long* arrayPtr, const int width, const int height, const long val); - -template std::string toString(char t, std::ios_base& (*r)(std::ios_base&)); -template std::string toString(short t, std::ios_base& (*r)(std::ios_base&)); -template std::string toString(unsigned int t, std::ios_base& (*r)(std::ios_base&)); -template std::string toString(int t, std::ios_base& (*r)(std::ios_base&)); -template std::string toString(long t, std::ios_base& (*r)(std::ios_base&)); -template std::string toString(float t, std::ios_base& (*r)(std::ios_base&)); -template std::string toString(double t, std::ios_base& (*r)(std::ios_base&)); diff --git a/runtime/hsa-amd-aqlprofile/test/util/helper_funcs.h b/runtime/hsa-amd-aqlprofile/test/util/helper_funcs.h deleted file mode 100644 index 190bc3089a..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/util/helper_funcs.h +++ /dev/null @@ -1,90 +0,0 @@ -/********************************************************************** -Copyright ©2013 Advanced Micro Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, are permitted -provided that the following conditions are met: - -• Redistributions of source code must retain the above copyright notice, this list of -conditions and the following disclaimer. -• Redistributions in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. -********************************************************************/ -#ifndef _HELPER_FUNCS_H_ -#define _HELPER_FUNCS_H_ - -#include - -/** - * compare template version - * compare data to check error - * @param refData templated input - * @param data templated input - * @param length number of values to compare - * @param epsilon errorWindow - */ -bool compare(const float* refData, const float* data, const int length, - const float epsilon = 1e-6f); -bool compare(const double* refData, const double* data, const int length, - const double epsilon = 1e-6); - -/** - * printArray - * displays a array on std::out - */ -template -void printArray(const std::string header, const T* data, const int width, const int height); - - -/** - * fillRandom - * fill array with random values - */ -template -bool fillRandom(T* arrayPtr, const int width, const int height, const T rangeMin, const T rangeMax, - unsigned int seed = 123); - -/** - * fillPos - * fill the specified positions - */ -template bool fillPos(T* arrayPtr, const int width, const int height); - -/** - * fillConstant - * fill the array with constant value - */ -template -bool fillConstant(T* arrayPtr, const int width, const int height, const T val); - - -/** - * roundToPowerOf2 - * rounds to a power of 2 - */ -template T roundToPowerOf2(T val); - -/** - * isPowerOf2 - * checks if input is a power of 2 - */ -template bool isPowerOf2(T val); - -/** - * toString - * convert a T type to string - */ -template std::string toString(T t, std::ios_base& (*r)(std::ios_base&)); - -#endif // _HELPER_FUNCS_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/util/hsa_rsrc_factory.cpp b/runtime/hsa-amd-aqlprofile/test/util/hsa_rsrc_factory.cpp deleted file mode 100644 index 6c0cd31825..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/util/hsa_rsrc_factory.cpp +++ /dev/null @@ -1,473 +0,0 @@ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "hsa.h" -#include "hsa_rsrc_factory.h" -#include "hsa_ext_finalize.h" - -using namespace std; - -// Provide access to command line arguments passed in by user -uint32_t hsa_cmdline_arg_cnt; -char** hsa_cmdline_arg_list; - -// Callback function to find and bind kernarg region of an agent -static hsa_status_t find_memregions(hsa_region_t region, void* data) { - hsa_region_global_flag_t flags; - hsa_region_segment_t segment_id; - - hsa_region_get_info(region, HSA_REGION_INFO_SEGMENT, &segment_id); - if (segment_id != HSA_REGION_SEGMENT_GLOBAL) { - return HSA_STATUS_SUCCESS; - } - - AgentInfo* agent_info = (AgentInfo*)data; - hsa_region_get_info(region, HSA_REGION_INFO_GLOBAL_FLAGS, &flags); - if (flags & HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED) { - agent_info->coarse_region = region; - } - - if (flags & HSA_REGION_GLOBAL_FLAG_KERNARG) { - agent_info->kernarg_region = region; - } - - return HSA_STATUS_SUCCESS; -} - -// Callback function to get the number of agents -static hsa_status_t get_hsa_agents(hsa_agent_t agent, void* data) { - // Copy handle of agent and increment number of agents reported - HsaRsrcFactory* rsrcFactory = reinterpret_cast(data); - - // Determine if device is a Gpu agent - hsa_status_t status; - hsa_device_type_t type; - status = hsa_agent_get_info(agent, HSA_AGENT_INFO_DEVICE, &type); - if (type == HSA_DEVICE_TYPE_DSP) { - return HSA_STATUS_SUCCESS; - } - - if (type == HSA_DEVICE_TYPE_CPU) { - AgentInfo* agent_info = reinterpret_cast(malloc(sizeof(AgentInfo))); - agent_info->dev_id = agent; - agent_info->dev_type = HSA_DEVICE_TYPE_CPU; - rsrcFactory->AddAgentInfo(agent_info, false); - return HSA_STATUS_SUCCESS; - } - - // Device is a Gpu agent, build an instance of AgentInfo - AgentInfo* agent_info = reinterpret_cast(malloc(sizeof(AgentInfo))); - agent_info->dev_id = agent; - agent_info->dev_type = HSA_DEVICE_TYPE_GPU; - hsa_agent_get_info(agent, HSA_AGENT_INFO_NAME, agent_info->name); - agent_info->max_wave_size = 0; - hsa_agent_get_info(agent, HSA_AGENT_INFO_WAVEFRONT_SIZE, &agent_info->max_wave_size); - agent_info->max_queue_size = 0; - hsa_agent_get_info(agent, HSA_AGENT_INFO_QUEUE_MAX_SIZE, &agent_info->max_queue_size); - agent_info->profile = hsa_profile_t(108); - hsa_agent_get_info(agent, HSA_AGENT_INFO_PROFILE, &agent_info->profile); - - // Initialize memory regions to zero - agent_info->kernarg_region.handle = 0; - agent_info->coarse_region.handle = 0; - - // Find and Bind Memory regions of the Gpu agent - hsa_agent_iterate_regions(agent, find_memregions, agent_info); - - // Save the instance of AgentInfo - rsrcFactory->AddAgentInfo(agent_info, true); - return HSA_STATUS_SUCCESS; -} - -// Definitions for Static Data members of the class -char* HsaRsrcFactory::brig_path_ = NULL; -uint32_t HsaRsrcFactory::num_cus_ = 4; -uint32_t HsaRsrcFactory::num_waves_; -uint32_t HsaRsrcFactory::num_workitems_; -uint32_t HsaRsrcFactory::kernel_loop_count_; -bool HsaRsrcFactory::print_debug_info_ = false; - -char* HsaRsrcFactory::num_cus_key_ = "num_cus"; -char* HsaRsrcFactory::brig_path_key_ = "brig_path"; -char* HsaRsrcFactory::num_waves_key_ = "waves_per_cu"; -char* HsaRsrcFactory::num_workitems_key_ = "workitems_per_wave"; -char* HsaRsrcFactory::print_debug_key_ = "print_debug"; -char* HsaRsrcFactory::kernel_loop_count_key_ = "kernel_loop_count"; - -// Constructor of the class -HsaRsrcFactory::HsaRsrcFactory() { - // Initialize the Hsa Runtime - hsa_status_t status = hsa_init(); - check("Error in hsa_init", status); - - // Discover the set of Gpu devices available on the platform - status = hsa_iterate_agents(get_hsa_agents, this); - check("Error Calling hsa_iterate_agents", status); - - // Process command line arguments - ProcessCmdline(); -} - -// Destructor of the class -HsaRsrcFactory::~HsaRsrcFactory() {} - -// Get the count of Hsa Gpu Agents available on the platform -// -// @return uint32_t Number of Gpu agents on platform -// -uint32_t HsaRsrcFactory::GetCountOfGpuAgents() { return uint32_t(gpu_list_.size()); } - -// Get the count of Hsa Cpu Agents available on the platform -// -// @return uint32_t Number of Cpu agents on platform -// -uint32_t HsaRsrcFactory::GetCountOfCpuAgents() { return uint32_t(cpu_list_.size()); } - -// Get the AgentInfo handle of a Gpu device -// -// @param idx Gpu Agent at specified index -// -// @param agent_info Output parameter updated with AgentInfo -// -// @return bool true if successful, false otherwise -// -bool HsaRsrcFactory::GetGpuAgentInfo(uint32_t idx, AgentInfo** agent_info) { - // Determine if request is valid - uint32_t size = uint32_t(gpu_list_.size()); - if (idx >= size) { - return false; - } - - // Copy AgentInfo from specified index - *agent_info = gpu_list_[idx]; - return true; -} - -// Get the AgentInfo handle of a Cpu device -// -// @param idx Cpu Agent at specified index -// -// @param agent_info Output parameter updated with AgentInfo -// -// @return bool true if successful, false otherwise -// -bool HsaRsrcFactory::GetCpuAgentInfo(uint32_t idx, AgentInfo** agent_info) { - // Determine if request is valid - uint32_t size = uint32_t(cpu_list_.size()); - if (idx >= size) { - return false; - } - - // Copy AgentInfo from specified index - *agent_info = cpu_list_[idx]; - return true; -} - -// Create a Queue object and return its handle. The queue object is expected -// to support user requested number of Aql dispatch packets. -// -// @param agent_info Gpu Agent on which to create a queue object -// -// @param num_Pkts Number of packets to be held by queue -// -// @param queue Output parameter updated with handle of queue object -// -// @return bool true if successful, false otherwise -// -bool HsaRsrcFactory::CreateQueue(AgentInfo* agent_info, uint32_t num_pkts, hsa_queue_t** queue) { - hsa_status_t status; - status = hsa_queue_create(agent_info->dev_id, num_pkts, HSA_QUEUE_TYPE_MULTI, NULL, NULL, - UINT32_MAX, UINT32_MAX, queue); - return (status == HSA_STATUS_SUCCESS); -} - -// Create a Signal object and return its handle. -// -// @param value Initial value of signal object -// -// @param signal Output parameter updated with handle of signal object -// -// @return bool true if successful, false otherwise -// -bool HsaRsrcFactory::CreateSignal(uint32_t value, hsa_signal_t* signal) { - hsa_status_t status; - status = hsa_signal_create(value, 0, NULL, signal); - return (status == HSA_STATUS_SUCCESS); -} - -// Allocate memory for use by a kernel of specified size in specified -// agent's memory region. Currently supports Global segment whose Kernarg -// flag set. -// -// @param agent_info Agent from whose memory region to allocate -// -// @param size Size of memory in terms of bytes -// -// @return uint8_t* Pointer to buffer, null if allocation fails. -// -uint8_t* HsaRsrcFactory::AllocateLocalMemory(AgentInfo* agent_info, size_t size) { - hsa_status_t status; - uint8_t* buffer = NULL; - - if (agent_info->coarse_region.handle != 0) { - // Allocate in local memory if it is available - status = hsa_memory_allocate(agent_info->coarse_region, size, (void**)&buffer); - if (status == HSA_STATUS_SUCCESS) { - status = hsa_memory_assign_agent(buffer, agent_info->dev_id, HSA_ACCESS_PERMISSION_RW); - } - } else { - // Allocate in system memory if local memory is not available - status = hsa_memory_allocate(agent_info->kernarg_region, size, (void**)&buffer); - } - - return (status == HSA_STATUS_SUCCESS) ? buffer : NULL; -} - -// Allocate memory tp pass kernel parameters. -// -// @param agent_info Agent from whose memory region to allocate -// -// @param size Size of memory in terms of bytes -// -// @return uint8_t* Pointer to buffer, null if allocation fails. -// -uint8_t* HsaRsrcFactory::AllocateSysMemory(AgentInfo* agent_info, size_t size) { - hsa_status_t status; - uint8_t* buffer = NULL; - status = hsa_memory_allocate(agent_info->kernarg_region, size, (void**)&buffer); - return (status == HSA_STATUS_SUCCESS) ? buffer : NULL; -} - -bool HsaRsrcFactory::TransferData(uint8_t* dest_buff, uint8_t* src_buff, uint32_t length, - bool host_to_dev) { - hsa_status_t status; - status = hsa_memory_copy(dest_buff, src_buff, length); - return (status == HSA_STATUS_SUCCESS); -} - -// Fake method for compilation steps only -uint8_t* HsaRsrcFactory::AllocateMemory(AgentInfo* agent_info, size_t size) { - hsa_status_t status; - uint8_t* buffer = NULL; - status = hsa_memory_allocate(agent_info->kernarg_region, size, (void**)&buffer); - return (status == HSA_STATUS_SUCCESS) ? buffer : NULL; -} - -// Loads an Assembled Brig file and Finalizes it into Device Isa -// -// @param agent_info Gpu device for which to finalize -// -// @param brig_path File path of the Assembled Brig file -// -// @param kernel_name Name of the kernel to finalize -// -// @param code_desc Handle of finalized Code Descriptor that could -// be used to submit for execution -// -// @return bool true if successful, false otherwise -// -bool HsaRsrcFactory::LoadAndFinalize(AgentInfo* agent_info, const char* brig_path, - char* kernel_name, hsa_executable_symbol_t* code_desc) { - // Finalize the Hsail object into code object - hsa_status_t status; - hsa_code_object_t code_object; - - // Build the code object filename - std::string filename(brig_path); - std::cout << "Code object filename: " << filename << std::endl; - - // Open the file containing code object - std::ifstream codeStream(filename.c_str(), std::ios::binary | std::ios::ate); - if (!codeStream) { - std::cout << "Error: failed to load " << filename << std::endl; - assert(false); - return false; - } - - // Allocate memory to read in code object from file - size_t size = std::string::size_type(codeStream.tellg()); - char* codeBuff = (char*)AllocateSysMemory(agent_info, size); - if (!codeBuff) { - std::cout << "Error: failed to allocate memory for code object." << std::endl; - assert(false); - return false; - } - - // Read the code object into allocated memory - codeStream.seekg(0, std::ios::beg); - std::copy(std::istreambuf_iterator(codeStream), std::istreambuf_iterator(), codeBuff); - - // De-Serialize the code object that has been read into memory - status = hsa_code_object_deserialize(codeBuff, size, NULL, &code_object); - if (status != HSA_STATUS_SUCCESS) { - std::cout << "Failed to deserialize code object" << std::endl; - return false; - } - - // Create executable. - hsa_executable_t hsaExecutable; - // status = hsa_executable_create(agent_info->profile, - status = - hsa_executable_create(HSA_PROFILE_FULL, HSA_EXECUTABLE_STATE_UNFROZEN, "", &hsaExecutable); - check("Error in creating executable object", status); - - // Load code object. - status = hsa_executable_load_code_object(hsaExecutable, agent_info->dev_id, code_object, ""); - check("Error in loading executable object", status); - - // Freeze executable. - status = hsa_executable_freeze(hsaExecutable, ""); - check("Error in freezing executable object", status); - - // Get symbol handle. - hsa_executable_symbol_t kernelSymbol; - status = hsa_executable_get_symbol(hsaExecutable, NULL, kernel_name, agent_info->dev_id, 0, - &kernelSymbol); - check("Error in looking up kernel symbol", status); - - // Update output parameter - *code_desc = kernelSymbol; - return true; -} - -// Add an instance of AgentInfo representing a Hsa Gpu agent -void HsaRsrcFactory::AddAgentInfo(AgentInfo* agent_info, bool gpu) { - // Add input to Gpu list - if (gpu) { - gpu_list_.push_back(agent_info); - return; - } - - // Add input to Cpu list - cpu_list_.push_back(agent_info); -} - -// Print the various fields of Hsa Gpu Agents -bool HsaRsrcFactory::PrintGpuAgents(const std::string& header) { - std::cout << header << " :" << std::endl; - - AgentInfo* agent_info; - int size = uint32_t(gpu_list_.size()); - for (int idx = 0; idx < size; idx++) { - agent_info = gpu_list_[idx]; - - std::cout << "> agent[" << idx << "] :" << std::endl; - std::cout << ">> Name : " << agent_info->name << std::endl; - std::cout << ">> Max Wave Size : " << agent_info->max_wave_size << std::endl; - std::cout << ">> Max Queue Size : " << agent_info->max_queue_size << std::endl; - std::cout << ">> Kernarg Region Id : " << agent_info->coarse_region.handle << std::endl; - } - return true; -} - -// Returns the file path where brig files is located. Value is -// available only after an instance has been built. -char* HsaRsrcFactory::GetBrigPath() { return HsaRsrcFactory::brig_path_; } - -// Returns the number of compute units present on platform -// Value is available only after an instance has been built. -uint32_t HsaRsrcFactory::GetNumOfCUs() { return HsaRsrcFactory::num_cus_; } - -// Returns the maximum number of waves that can be launched -// per compute unit. The actual number that can be launched -// is affected by resource availability -// -// Value is available only after an instance has been built. -uint32_t HsaRsrcFactory::GetNumOfWavesPerCU() { return HsaRsrcFactory::num_waves_; } - -// Returns the number of work-items that can execute per wave -// Value is available only after an instance has been built. -uint32_t HsaRsrcFactory::GetNumOfWorkItemsPerWave() { return HsaRsrcFactory::num_workitems_; } - -// Returns the number of times kernel loop body should execute. -// Value is available only after an instance has been built. -uint32_t HsaRsrcFactory::GetKernelLoopCount() { return HsaRsrcFactory::kernel_loop_count_; } - -// Returns boolean flag to indicate if debug info should be printed -// Value is available only after an instance has been built. -uint32_t HsaRsrcFactory::GetPrintDebugInfo() { return HsaRsrcFactory::print_debug_info_; } - -// Process command line arguments. The method will capture -// various user command line parameters for tests to use -void HsaRsrcFactory::ProcessCmdline() { - // Command line arguments are given - uint32_t idx; - uint32_t arg_idx; - for (idx = 1; idx < hsa_cmdline_arg_cnt; idx += 2) { - arg_idx = GetArgIndex((char*)hsa_cmdline_arg_list[idx]); - switch (arg_idx) { - case 0: - HsaRsrcFactory::brig_path_ = hsa_cmdline_arg_list[idx + 1]; - break; - case 1: - HsaRsrcFactory::num_cus_ = atoi(hsa_cmdline_arg_list[idx + 1]); - break; - case 2: - HsaRsrcFactory::num_waves_ = atoi(hsa_cmdline_arg_list[idx + 1]); - break; - case 3: - HsaRsrcFactory::num_workitems_ = atoi(hsa_cmdline_arg_list[idx + 1]); - break; - case 4: - HsaRsrcFactory::kernel_loop_count_ = atoi(hsa_cmdline_arg_list[idx + 1]); - break; - case 5: - HsaRsrcFactory::print_debug_info_ = true; - break; - } - } -} - -uint32_t HsaRsrcFactory::GetArgIndex(char* arg_value) { - // Map Brig file path to index zero - if (!strcmp(HsaRsrcFactory::brig_path_key_, arg_value)) { - return 0; - } - - // Map Number of Compute Units to index one - if (!strcmp(HsaRsrcFactory::num_cus_key_, arg_value)) { - return 1; - } - - // Map Number of Waves per CU to index two - if (!strcmp(HsaRsrcFactory::num_waves_key_, arg_value)) { - return 2; - } - - // Map Number of Workitems per Wave to index three - if (!strcmp(HsaRsrcFactory::num_workitems_key_, arg_value)) { - return 3; - } - - // Map Kernel Loop Count to index four - if (!strcmp(HsaRsrcFactory::kernel_loop_count_key_, arg_value)) { - return 4; - } - - // Map print debug info parameter - if (!strcmp(HsaRsrcFactory::print_debug_key_, arg_value)) { - return 5; - } - - return 108; -} - -void HsaRsrcFactory::PrintHelpMsg() { - std::cout << "Key for passing Brig filepath: " << HsaRsrcFactory::brig_path_key_ << std::endl; - std::cout << "Key for passing Number of Compute Units: " << HsaRsrcFactory::num_cus_key_ - << std::endl; - std::cout << "Key for passing Number of Waves per CU: " << HsaRsrcFactory::num_waves_key_ - << std::endl; - std::cout << "Key for passing Number of Workitems per Wave: " - << HsaRsrcFactory::num_workitems_key_ << std::endl; - std::cout << "Key for passing Kernel Loop Count: " << HsaRsrcFactory::kernel_loop_count_key_ - << std::endl; -} diff --git a/runtime/hsa-amd-aqlprofile/test/util/hsa_rsrc_factory.h b/runtime/hsa-amd-aqlprofile/test/util/hsa_rsrc_factory.h deleted file mode 100644 index 6b2f3511e2..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/util/hsa_rsrc_factory.h +++ /dev/null @@ -1,262 +0,0 @@ -#ifndef HSA_RSRC_FACTORY_H_ -#define HSA_RSRC_FACTORY_H_ - -#include -#include -#include -#include - -#include -#include -#include - -#include "perf_timer.h" -#include "hsa.h" -#include "hsa_ext_finalize.h" - -#define HSA_ARGUMENT_ALIGN_BYTES 16 -#define HSA_QUEUE_ALIGN_BYTES 64 -#define HSA_PACKET_ALIGN_BYTES 64 - -#define check(msg, status) \ - if (status != HSA_STATUS_SUCCESS) { \ - const char* emsg = 0; \ - hsa_status_string(status, &emsg); \ - printf("%s: %s\n", msg, emsg ? emsg : ""); \ - exit(1); \ - } - -#define check_build(msg, status) \ - if (status != STATUS_SUCCESS) { \ - printf("%s\n", msg); \ - exit(1); \ - } - -// Provide access to command line arguments passed in by user -extern uint32_t hsa_cmdline_arg_cnt; -extern char** hsa_cmdline_arg_list; - -// Encapsulates information about a Hsa Agent such as its -// handle, name, max queue size, max wavefront size, etc. -typedef struct { - // Handle of Agent - hsa_agent_t dev_id; - - // Agent type - Cpu = 0, Gpu = 1 or Dsp = 2 - uint32_t dev_type; - - // Name of Agent whose length is less than 64 - char name[64]; - - // Max size of Wavefront size - uint32_t max_wave_size; - - // Max size of Queue buffer - uint32_t max_queue_size; - - // Hsail profile supported by agent - hsa_profile_t profile; - - // Memory region supporting kernel parameters - hsa_region_t coarse_region; - - // Memory region supporting kernel arguments - hsa_region_t kernarg_region; - -} AgentInfo; - -class HsaRsrcFactory { - public: - // Constructor of the class. Will initialize the Hsa Runtime and - // query the system topology to get the list of Cpu and Gpu devices - HsaRsrcFactory(); - - // Destructor of the class - ~HsaRsrcFactory(); - - // Get the count of Hsa Gpu Agents available on the platform - // - // @return uint32_t Number of Gpu agents on platform - // - uint32_t GetCountOfGpuAgents(); - - // Get the count of Hsa Cpu Agents available on the platform - // - // @return uint32_t Number of Cpu agents on platform - // - uint32_t GetCountOfCpuAgents(); - - // Get the AgentInfo handle of a Gpu device - // - // @param idx Gpu Agent at specified index - // - // @param agent_info Output parameter updated with AgentInfo - // - // @return bool true if successful, false otherwise - // - bool GetGpuAgentInfo(uint32_t idx, AgentInfo** agent_info); - - // Get the AgentInfo handle of a Cpu device - // - // @param idx Cpu Agent at specified index - // - // @param agent_info Output parameter updated with AgentInfo - // - // @return bool true if successful, false otherwise - // - bool GetCpuAgentInfo(uint32_t idx, AgentInfo** agent_info); - - // Create a Queue object and return its handle. The queue object is expected - // to support user requested number of Aql dispatch packets. - // - // @param agent_info Gpu Agent on which to create a queue object - // - // @param num_Pkts Number of packets to be held by queue - // - // @param queue Output parameter updated with handle of queue object - // - // @return bool true if successful, false otherwise - // - bool CreateQueue(AgentInfo* agent_info, uint32_t num_pkts, hsa_queue_t** queue); - - // Create a Signal object and return its handle. - // - // @param value Initial value of signal object - // - // @param signal Output parameter updated with handle of signal object - // - // @return bool true if successful, false otherwise - // - bool CreateSignal(uint32_t value, hsa_signal_t* signal); - - // Allocate memory for use by a kernel of specified size in specified - // agent's memory region. Currently supports Global segment whose Kernarg - // flag set. - // - // @param agent_info Agent from whose memory region to allocate - // - // @param size Size of memory in terms of bytes - // - // @return uint8_t* Pointer to buffer, null if allocation fails. - // - uint8_t* AllocateLocalMemory(AgentInfo* agent_info, size_t size); - uint8_t* AllocateMemory(AgentInfo* agent_info, size_t size); - - bool TransferData(uint8_t* dest_buff, uint8_t* src_buff, uint32_t length, bool host_to_dev); - - // Allocate memory tp pass kernel parameters. - // - // @param agent_info Agent from whose memory region to allocate - // - // @param size Size of memory in terms of bytes - // - // @return uint8_t* Pointer to buffer, null if allocation fails. - // - uint8_t* AllocateSysMemory(AgentInfo* agent_info, size_t size); - - // Loads an Assembled Brig file and Finalizes it into Device Isa - // - // @param agent_info Gpu device for which to finalize - // - // @param brig_path File path of the Assembled Brig file - // - // @param kernel_name Name of the kernel to finalize - // - // @param code_desc Handle of finalized Code Descriptor that could - // be used to submit for execution - // - // @return bool true if successful, false otherwise - // - bool LoadAndFinalize(AgentInfo* agent_info, const char* brig_path, char* kernel_name, - hsa_executable_symbol_t* code_desc); - - // Add an instance of AgentInfo representing a Hsa Gpu agent - void AddAgentInfo(AgentInfo* agent_info, bool gpu); - - // Returns the file path where brig files is located - static char* GetBrigPath(); - - // Returns the number of compute units present on platform - static uint32_t GetNumOfCUs(); - - // Returns the maximum number of waves that can be launched - // per compute unit. The actual number that can be launched - // is affected by resource availability - static uint32_t GetNumOfWavesPerCU(); - - // Returns the number of work-items that can execute per wave - static uint32_t GetNumOfWorkItemsPerWave(); - - // Returns the number of times kernel loop body should execute. - static uint32_t GetKernelLoopCount(); - - // Returns boolean flag to indicate if debug info should be printed - static uint32_t GetPrintDebugInfo(); - - // Print the various fields of Hsa Gpu Agents - bool PrintGpuAgents(const std::string& header); - - private: - // Number of queues to create - uint32_t num_queues_; - - // Used to maintain a list of Hsa Queue handles - std::vector queue_list_; - - // Number of Signals to create - uint32_t num_signals_; - - // Used to maintain a list of Hsa Signal handles - std::vector signal_list_; - - // Number of agents reported by platform - uint32_t num_agents_; - - // Used to maintain a list of Hsa Gpu Agent Info - std::vector gpu_list_; - - // Used to maintain a list of Hsa Cpu Agent Info - std::vector cpu_list_; - - // Records the file path where Brig file is located. - // Value is available only after an instance has been built. - static char* brig_path_; - static char* brig_path_key_; - - // Records the number of Compute units present on system. - // Value is available only after an instance has been built. - static uint32_t num_cus_; - static char* num_cus_key_; - - // Records the number of waves that can be launched per Compute unit - // Value is available only after an instance has been built. - static uint32_t num_waves_; - static char* num_waves_key_; - - // Records the number of work-items that can be packed into a wave - // Value is available only after an instance has been built. - static uint32_t num_workitems_; - static char* num_workitems_key_; - - // Records the number of times kernel loop body should run. Value - // is available only after an instance has been built. - static uint32_t kernel_loop_count_; - static char* kernel_loop_count_key_; - - // Records the number of times kernel loop body should run. Value - // is available only after an instance has been built. - static bool print_debug_info_; - static char* print_debug_key_; - - // Process command line arguments. The method will capture - // various user command line parameters for tests to use - static void ProcessCmdline(); - - // Prints the help banner on user arg keys - static void PrintHelpMsg(); - - // Maps an index for the user argument - static uint32_t GetArgIndex(char* arg_value); -}; - -#endif // HSA_RSRC_FACTORY_H_ diff --git a/runtime/hsa-amd-aqlprofile/test/util/perf_timer.cpp b/runtime/hsa-amd-aqlprofile/test/util/perf_timer.cpp deleted file mode 100644 index c893c067e2..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/util/perf_timer.cpp +++ /dev/null @@ -1,157 +0,0 @@ -#include "perf_timer.h" - -PerfTimer::PerfTimer() { freq_in_100mhz = MeasureTSCFreqHz(); } - -PerfTimer::~PerfTimer() { - while (!_timers.empty()) { - Timer* temp = _timers.back(); - _timers.pop_back(); - delete temp; - } -} - -// a new cretaed timer instantance index will be returned -int PerfTimer::CreateTimer() { - Timer* newTimer = new Timer; - newTimer->_start = 0; - newTimer->_clocks = 0; - -#ifdef _WIN32 - QueryPerformanceFrequency((LARGE_INTEGER*)&newTimer->_freq); -#else - newTimer->_freq = (long long)1.0E3; -#endif - - /* Push back the address of new Timer instance created */ - _timers.push_back(newTimer); - return (int)(_timers.size() - 1); -} - -int PerfTimer::StartTimer(int index) { - if (index >= (int)_timers.size()) { - Error("Cannot reset timer. Invalid handle."); - return FAILURE; - } - -#ifdef _WIN32 -// General Windows timing method -#ifndef _AMD - long long tmpStart; - QueryPerformanceCounter((LARGE_INTEGER*)&(tmpStart)); - _timers[index]->_start = (double)tmpStart; -#else -// AMD Windows timing method -#endif -#else -// General Linux timing method -#ifndef _AMD - struct timeval s; - gettimeofday(&s, 0); - _timers[index]->_start = s.tv_sec * 1.0E3 + ((double)(s.tv_usec / 1.0E3)); -#else - // AMD timing method - unsigned int unused; - _timers[index]->_start = __rdtscp(&unused); -#endif -#endif - - return SUCCESS; -} - - -int PerfTimer::StopTimer(int index) { - double n = 0; - if (index >= (int)_timers.size()) { - Error("Cannot reset timer. Invalid handle."); - return FAILURE; - } -#ifdef _WIN32 -#ifndef _AMD - long long n1; - QueryPerformanceCounter((LARGE_INTEGER*)&(n1)); - n = (double)n1; -#else -// AMD Window Timing -#endif - -#else -// General Linux timing method -#ifndef _AMD - struct timeval s; - gettimeofday(&s, 0); - n = s.tv_sec * 1.0E3 + (double)(s.tv_usec / 1.0E3); -#else - // AMD Linux timing - unsigned int unused; - n = __rdtscp(&unused); -#endif -#endif - - n -= _timers[index]->_start; - _timers[index]->_start = 0; - -#ifndef _AMD - _timers[index]->_clocks += n; -#else - //_timers[index]->_clocks += 10 * n /freq_in_100mhz; // unit is ns - _timers[index]->_clocks += 1.0E-6 * 10 * n / freq_in_100mhz; // convert to ms -#endif - - return SUCCESS; -} - -void PerfTimer::Error(string str) { cout << str << endl; } - - -double PerfTimer::ReadTimer(int index) { - if (index >= (int)_timers.size()) { - Error("Cannot read timer. Invalid handle."); - return FAILURE; - } - - double reading = double(_timers[index]->_clocks); - - reading = double(reading / _timers[index]->_freq); - - return reading; -} - - -uint64_t PerfTimer::CoarseTimestampUs() { -#ifdef _WIN32 - uint64_t freqHz, ticks; - QueryPerformanceFrequency((LARGE_INTEGER*)&freqHz); - QueryPerformanceCounter((LARGE_INTEGER*)&ticks); - - // Scale numerator and divisor until (ticks * 1000000) fits in uint64_t. - while (ticks > (1ULL << 44)) { - ticks /= 16; - freqHz /= 16; - } - - return (ticks * 1000000) / freqHz; -#else - struct timespec ts; - clock_gettime(CLOCK_MONOTONIC_RAW, &ts); - return uint64_t(ts.tv_sec) * 1000000 + ts.tv_nsec / 1000; -#endif -} - -uint64_t PerfTimer::MeasureTSCFreqHz() { - // Make a coarse interval measurement of TSC ticks for 1 gigacycles. - unsigned int unused; - uint64_t tscTicksEnd; - - uint64_t coarseBeginUs = CoarseTimestampUs(); - uint64_t tscTicksBegin = __rdtscp(&unused); - do { - tscTicksEnd = __rdtscp(&unused); - } while (tscTicksEnd - tscTicksBegin < 1000000000); - - uint64_t coarseEndUs = CoarseTimestampUs(); - - // Compute the TSC frequency and round to nearest 100MHz. - uint64_t coarseIntervalNs = (coarseEndUs - coarseBeginUs) * 1000; - uint64_t tscIntervalTicks = tscTicksEnd - tscTicksBegin; - return (tscIntervalTicks * 10 + (coarseIntervalNs / 2)) / coarseIntervalNs; -} diff --git a/runtime/hsa-amd-aqlprofile/test/util/perf_timer.h b/runtime/hsa-amd-aqlprofile/test/util/perf_timer.h deleted file mode 100644 index 61ee3b5d90..0000000000 --- a/runtime/hsa-amd-aqlprofile/test/util/perf_timer.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef _PERF_TIMER_H_ -#define _PERF_TIMER_H_ - -// Will use AMD timer and general Linux timer based on users' need --> compilation flag -// need to consider platform is Windows or Linux - -#include -#include -#include -#include -#include -#include -#include -#if defined(_MSC_VER) -#include -#include -#include -#else -#if defined(__GNUC__) -#include -#include -#endif // __GNUC__ -#endif //_MSC_VER - -using namespace std; - -class PerfTimer { - public: - enum { SUCCESS = 0, FAILURE = 1 }; - - PerfTimer(); - ~PerfTimer(); - - // General Linux timing method - int CreateTimer(); - int StartTimer(int index); - int StopTimer(int index); - - // retrieve time - double ReadTimer(int index); - // write into a file - double WriteTimer(int index); - - private: - struct Timer { - string name; /* < name name of time object*/ - long long _freq; /* < _freq frequency*/ - double _clocks; /* < _clocks number of ticks at end*/ - double _start; /* < _start start point ticks*/ - }; - - std::vector _timers; /*< _timers vector to Timer objects */ - double freq_in_100mhz; - - // AMD timing method - uint64_t CoarseTimestampUs(); - uint64_t MeasureTSCFreqHz(); - - void Error(string str); -}; - -#endif // _PERF_TIMER_H_